diff --git a/.github/CODEOWNERS b/.github/CODEOWNERS index af9aa33347921..3528e51466d19 100644 --- a/.github/CODEOWNERS +++ b/.github/CODEOWNERS @@ -905,9 +905,7 @@ arch/arm/include/mps/irq.h anjiahao@xiaomi.com alin.jerpelea@sony.com arch/arm/include/mx8mp/chip.h philippe.leduc@wandercraft.eu alin.jerpelea@sony.com arch/arm/include/mx8mp/irq.h philippe.leduc@wandercraft.eu alin.jerpelea@sony.com arch/arm/include/mx8mp/mx8mp_irq.h philippe.leduc@wandercraft.eu devel@sumpfralle.de alin.jerpelea@sony.com - arch/arm/include/nrf* raiden00@railab.me alin.jerpelea@sony.com - arch/arm/include/nuc1xx/chip.h alin.jerpelea@sony.com loketep@yahoo.com xiaoxiang@xiaomi.com arch/arm/include/nuc1xx/irq.h alin.jerpelea@sony.com 59230071+hartmannathan@users.noreply.github.com xiaoxiang@xiaomi.com arch/arm/include/nuc1xx/nuc120_irq.h alin.jerpelea@sony.com 59230071+hartmannathan@users.noreply.github.com xiaoxiang@xiaomi.com @@ -964,27 +962,30 @@ arch/arm/include/samv7/samv71_irq.h alin.jerpelea@sony.com petro.karashchenko@gm arch/arm/include/setjmp.h david.s.alessio@gmail.com alin.jerpelea@sony.com guowei15@xiaomi.com xiaoxiang@xiaomi.com huangqi3@xiaomi.com arch/arm/include/spinlock.h alin.jerpelea@sony.com anchao.archer@bytedance.com xiaoxiang@xiaomi.com hujun5@xiaomi.com arch/arm/include/stdarg.h alin.jerpelea@sony.com guoshichao@xiaomi.com -arch/arm/include/stm32/chip.h raiden00pl@gmail.com 59230071+hartmannathan@users.noreply.github.com paul-a.patience@polymtl.ca -arch/arm/include/stm32/irq.h alin.jerpelea@sony.com 59230071+hartmannathan@users.noreply.github.com raiden00@railab.me -arch/arm/include/stm32/stm32f10xxx_irq.h alin.jerpelea@sony.com 59230071+hartmannathan@users.noreply.github.com david_s5@usa.net -arch/arm/include/stm32/stm32f20xxx_irq.h 59230071+hartmannathan@users.noreply.github.com david_s5@usa.net alin.jerpelea@sony.com -arch/arm/include/stm32/stm32f30xxx_irq.h 59230071+hartmannathan@users.noreply.github.com david_s5@usa.net alin.jerpelea@sony.com -arch/arm/include/stm32/stm32f33xxx_irq.h 59230071+hartmannathan@users.noreply.github.com raiden00pl@gmail.com alin.jerpelea@sony.com -arch/arm/include/stm32/stm32f37xxx_irq.h 59230071+hartmannathan@users.noreply.github.com david_s5@usa.net alin.jerpelea@sony.com xiaoxiang@xiaomi.com -arch/arm/include/stm32/stm32f40xxx_irq.h gwenj@trabucayre.com paul-a.patience@polymtl.ca david_s5@usa.net alin.jerpelea@sony.com -arch/arm/include/stm32/stm32g4xxxx_irq.h raiden00@railab.me alin.jerpelea@sony.com devel@sumpfralle.de gustavo.nihei@espressif.com -arch/arm/include/stm32/stm32l15xxx_irq.h 59230071+hartmannathan@users.noreply.github.com david_s5@usa.net alin.jerpelea@sony.com xiaoxiang@xiaomi.com -arch/arm/include/stm32f0l0g0/chip.h raiden00@railab.me 59230071+hartmannathan@users.noreply.github.com alin.jerpelea@sony.com tbennett@2g-eng.com -arch/arm/include/stm32f0l0g0/irq.h alin.jerpelea@sony.com 59230071+hartmannathan@users.noreply.github.com raiden00@railab.me gustavo.nihei@espressif.com -arch/arm/include/stm32f0l0g0/stm32c0_irq.h raiden00@railab.me -arch/arm/include/stm32f0l0g0/stm32f0_irq.h alin.jerpelea@sony.com 59230071+hartmannathan@users.noreply.github.com -arch/arm/include/stm32f0l0g0/stm32g0_irq.h dpo@certi.org.br 59230071+hartmannathan@users.noreply.github.com alin.jerpelea@sony.com kwilson@2g-eng.com -arch/arm/include/stm32f0l0g0/stm32l0_irq.h alin.jerpelea@sony.com raiden00@railab.me 59230071+hartmannathan@users.noreply.github.com xiaoxiang@xiaomi.com +arch/arm/include/stm32c0/chip.h raiden00@railab.me +arch/arm/include/stm32c0/irq.h raiden00pl@gmail.com dpo@certi.org.br raiden00@railab.me 59230071+hartmannathan@users.noreply.github.com alin.jerpelea@sony.com +arch/arm/include/stm32f0/chip.h raiden00@railab.me juha.niskanen@haltian.com dave@marples.net acassis@gmail.com +arch/arm/include/stm32f0/irq.h raiden00pl@gmail.com raiden00@railab.me alin.jerpelea@sony.com 59230071+hartmannathan@users.noreply.github.com peter.barada@gmail.com +arch/arm/include/stm32f1/chip.h raiden00@railab.me +arch/arm/include/stm32f1/irq.h raiden00@railab.me alin.jerpelea@sony.com 59230071+hartmannathan@users.noreply.github.com david_s5@usa.net peter.barada@gmail.com +arch/arm/include/stm32f2/chip.h raiden00@railab.me +arch/arm/include/stm32f2/irq.h david_s5@usa.net 59230071+hartmannathan@users.noreply.github.com raiden00@railab.me alin.jerpelea@sony.com peter.barada@gmail.com +arch/arm/include/stm32f3/chip.h raiden00@railab.me +arch/arm/include/stm32f3/irq.h raiden00@railab.me 59230071+hartmannathan@users.noreply.github.com alin.jerpelea@sony.com mijung@gmx.net simon@leitwert.ch +arch/arm/include/stm32f3/stm32f30xxx_irq.h david_s5@usa.net 59230071+hartmannathan@users.noreply.github.com alin.jerpelea@sony.com raiden00@railab.me peter.barada@gmail.com +arch/arm/include/stm32f3/stm32f33xxx_irq.h david_s5@usa.net 59230071+hartmannathan@users.noreply.github.com raiden00pl@gmail.com alin.jerpelea@sony.com raiden00@railab.me +arch/arm/include/stm32f3/stm32f37xxx_irq.h david_s5@usa.net 59230071+hartmannathan@users.noreply.github.com alin.jerpelea@sony.com raiden00@railab.me peter.barada@gmail.com +arch/arm/include/stm32f4/chip.h raiden00@railab.me +arch/arm/include/stm32f4/irq.h david_s5@usa.net gwenj@trabucayre.com paul-a.patience@polymtl.ca alin.jerpelea@sony.com raiden00@railab.me arch/arm/include/stm32f7/chip.h david_s5@usa.net alin.jerpelea@sony.com bob.feretich@rafresearch.com dave@marples.net arch/arm/include/stm32f7/irq.h alin.jerpelea@sony.com 59230071+hartmannathan@users.noreply.github.com bob.feretich@rafresearch.com david_s5@usa.net arch/arm/include/stm32f7/stm32f72xx73xx_irq.h bob.feretich@rafresearch.com alin.jerpelea@sony.com 59230071+hartmannathan@users.noreply.github.com gustavo.nihei@espressif.com arch/arm/include/stm32f7/stm32f74xx75xx_irq.h alin.jerpelea@sony.com 59230071+hartmannathan@users.noreply.github.com gustavo.nihei@espressif.com titus@elbe-informatik.de arch/arm/include/stm32f7/stm32f76xx77xx_irq.h 59230071+hartmannathan@users.noreply.github.com david_s5@usa.net alin.jerpelea@sony.com gustavo.nihei@espressif.com +arch/arm/include/stm32g0/chip.h raiden00@railab.me +arch/arm/include/stm32g0/irq.h raiden00pl@gmail.com dpo@certi.org.br raiden00@railab.me 59230071+hartmannathan@users.noreply.github.com alin.jerpelea@sony.com +arch/arm/include/stm32g4/chip.h raiden00@railab.me +arch/arm/include/stm32g4/irq.h 59230071+hartmannathan@users.noreply.github.com raiden00@railab.me alin.jerpelea@sony.com peter.barada@gmail.com devel@sumpfralle.de arch/arm/include/stm32h5/chip.h kwilson@2g-eng.com tbennett@2g-eng.com alin.jerpelea@sony.com arch/arm/include/stm32h5/irq.h kwilson@2g-eng.com alin.jerpelea@sony.com arch/arm/include/stm32h5/stm32h5xx_irq.h kwilson@2g-eng.com alin.jerpelea@sony.com @@ -994,6 +995,10 @@ arch/arm/include/stm32h7/stm32h7x3xx_irq.h simon@leitwert.ch David.Sidrane@NscDg arch/arm/include/stm32h7/stm32h7x5xx_cpu2_irq.h raiden00@railab.me alin.jerpelea@sony.com arch/arm/include/stm32h7/stm32h7x5xx_irq.h raiden00@railab.me alin.jerpelea@sony.com arch/arm/include/stm32h7/stm32h7x7xx_irq.h 59230071+hartmannathan@users.noreply.github.com lwazeh@gmail.com alin.jerpelea@sony.com gustavo.nihei@espressif.com +arch/arm/include/stm32l0/chip.h raiden00@railab.me +arch/arm/include/stm32l0/irq.h raiden00pl@gmail.com raiden00@railab.me alin.jerpelea@sony.com peter.barada@gmail.com 59230071+hartmannathan@users.noreply.github.com +arch/arm/include/stm32l1/chip.h raiden00@railab.me +arch/arm/include/stm32l1/irq.h david_s5@usa.net 59230071+hartmannathan@users.noreply.github.com raiden00@railab.me alin.jerpelea@sony.com peter.barada@gmail.com arch/arm/include/stm32l4/chip.h juha.niskanen@haltian.com sebastien@lorquet.fr dave@marples.net alin.jerpelea@sony.com arch/arm/include/stm32l4/irq.h sebastien@lorquet.fr 59230071+hartmannathan@users.noreply.github.com alin.jerpelea@sony.com juha.niskanen@haltian.com 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alin.jerpelea@sony.com raiden00@railab.me +arch/arm/src/stm32f4/hardware/stm32f412xx_pinmap.h David.Sidrane@NscDg.com alin.jerpelea@sony.com raiden00@railab.me gustavo.nihei@espressif.com +arch/arm/src/stm32f4/stm32.h alin.jerpelea@sony.com raiden00@railab.me abdelatif.guettouche@gmail.com raiden00pl@gmail.com xiaoxiang@xiaomi.com +arch/arm/src/stm32f4/stm32_rcc.c 59230071+hartmannathan@users.noreply.github.com alin.jerpelea@sony.com raiden00@railab.me xiaoxiang@xiaomi.com f.panag@amco.gr +arch/arm/src/stm32f4/stm32f40xxx_alarm.h NeilH20@biomonitors.com alin.jerpelea@sony.com xiaoxiang@xiaomi.com juha.niskanen@haltian.com raiden00@railab.me +arch/arm/src/stm32f4/stm32f40xxx_rcc.c f.panag@amco.gr paul-a.patience@polymtl.ca david_s5@nscdg.com david_s5@usa.net alin.jerpelea@sony.com arch/arm/src/stm32f7/Kconfig david_s5@nscdg.com raiden00@railab.me david_s5@usa.net titus@elbe-informatik.de arch/arm/src/stm32f7/chip.h alin.jerpelea@sony.com 59230071+hartmannathan@users.noreply.github.com Lok Tep 1 file changed, 1 insertion(+) arch/arm/src/stm32f7/hardware/stm32_adc.h alin.jerpelea@sony.com @@ -4046,6 +4048,47 @@ arch/arm/src/stm32f7/stm32_waste.h ville.juven@unikie.com 101105604+simbit18@use arch/arm/src/stm32f7/stm32f72xx73xx_rcc.c bob.feretich@rafresearch.com alin.jerpelea@sony.com b.brandt@messwerk-gmbh.de ramtin@lambdaconcept.com arch/arm/src/stm32f7/stm32f74xx75xx_rcc.c david_s5@nscdg.com jussi.kivilinna@haltian.com alin.jerpelea@sony.com b.brandt@messwerk-gmbh.de arch/arm/src/stm32f7/stm32f76xx77xx_rcc.c david_s5@usa.net david_s5@nscdg.com titus@elbe-informatik.de jussi.kivilinna@haltian.com alin.jerpelea@sony.com +arch/arm/src/stm32g0/Kconfig raiden00@railab.me +arch/arm/src/stm32g0/chip.h alin.jerpelea@sony.com acassis@gmail.com raiden00@railab.me raiden00pl@gmail.com +arch/arm/src/stm32g0/hardware/stm32_memorymap.h raiden00@railab.me +arch/arm/src/stm32g0/hardware/stm32_pinmap.h raiden00@railab.me +arch/arm/src/stm32g0/hardware/stm32g0_dmamux.h kwilson@2g-eng.com raiden00pl@gmail.com raiden00@railab.me pettitkd@gmail.com alin.jerpelea@sony.com +arch/arm/src/stm32g0/hardware/stm32g0_exti.h raiden00pl@gmail.com raiden00@railab.me alin.jerpelea@sony.com +arch/arm/src/stm32g0/hardware/stm32g0_flash.h tbennett@2g-eng.com raiden00pl@gmail.com alin.jerpelea@sony.com raiden00@railab.me +arch/arm/src/stm32g0/hardware/stm32g0_memorymap.h raiden00pl@gmail.com raiden00@railab.me alin.jerpelea@sony.com petro.karashchenko@gmail.com kwilson@2g-eng.com +arch/arm/src/stm32g0/hardware/stm32g0_pinmap.h raiden00pl@gmail.com dpo@certi.org.br raiden00@railab.me David.Sidrane@NscDg.com gvr@certi.org.br +arch/arm/src/stm32g0/hardware/stm32g0_pwr.h raiden00pl@gmail.com alin.jerpelea@sony.com raiden00@railab.me +arch/arm/src/stm32g0/hardware/stm32g0_rcc.h raiden00pl@gmail.com raiden00@railab.me alin.jerpelea@sony.com kwilson@2g-eng.com tbennett@2g-eng.com +arch/arm/src/stm32g0/hardware/stm32g0_syscfg.h raiden00pl@gmail.com raiden00@railab.me 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David.Sidrane@NscDg.com 59230071+hartmannathan@users.noreply.github.com raiden00@railab.me alin.jerpelea@sony.com gustavo.nihei@espressif.com +arch/arm/src/stm32g4/hardware/stm32g4xxk_pinmap.h David.Sidrane@NscDg.com danieloak@gmail.com 59230071+hartmannathan@users.noreply.github.com raiden00@railab.me alin.jerpelea@sony.com +arch/arm/src/stm32g4/hardware/stm32g4xxm_pinmap.h David.Sidrane@NscDg.com 59230071+hartmannathan@users.noreply.github.com alin.jerpelea@sony.com raiden00@railab.me gustavo.nihei@espressif.com +arch/arm/src/stm32g4/hardware/stm32g4xxp_pinmap.h 59230071+hartmannathan@users.noreply.github.com raiden00@railab.me alin.jerpelea@sony.com gustavo.nihei@espressif.com +arch/arm/src/stm32g4/hardware/stm32g4xxq_pinmap.h David.Sidrane@NscDg.com 59230071+hartmannathan@users.noreply.github.com raiden00@railab.me alin.jerpelea@sony.com gustavo.nihei@espressif.com +arch/arm/src/stm32g4/hardware/stm32g4xxr_pinmap.h David.Sidrane@NscDg.com 59230071+hartmannathan@users.noreply.github.com raiden00@railab.me alin.jerpelea@sony.com kwilson@2g-eng.com +arch/arm/src/stm32g4/hardware/stm32g4xxv_pinmap.h David.Sidrane@NscDg.com 59230071+hartmannathan@users.noreply.github.com raiden00@railab.me alin.jerpelea@sony.com gustavo.nihei@espressif.com +arch/arm/src/stm32g4/hardware/stm32g4xxxx_comp.h danieloak@gmail.com raiden00@railab.me alin.jerpelea@sony.com 101105604+simbit18@users.noreply.github.com +arch/arm/src/stm32g4/hardware/stm32g4xxxx_cordic.h raiden00@railab.me alin.jerpelea@sony.com +arch/arm/src/stm32g4/hardware/stm32g4xxxx_dmamux.h raiden00@railab.me 59230071+hartmannathan@users.noreply.github.com alin.jerpelea@sony.com +arch/arm/src/stm32g4/hardware/stm32g4xxxx_gpio.h 59230071+hartmannathan@users.noreply.github.com raiden00@railab.me alin.jerpelea@sony.com gustavo.nihei@espressif.com +arch/arm/src/stm32g4/hardware/stm32g4xxxx_memorymap.h 59230071+hartmannathan@users.noreply.github.com alin.jerpelea@sony.com raiden00@railab.me hanyazou@gmail.com gustavo.nihei@espressif.com +arch/arm/src/stm32g4/hardware/stm32g4xxxx_opamp.h raiden00@railab.me alin.jerpelea@sony.com +arch/arm/src/stm32g4/hardware/stm32g4xxxx_pinmap.h raiden00@railab.me David.Sidrane@NscDg.com 59230071+hartmannathan@users.noreply.github.com alin.jerpelea@sony.com gustavo.nihei@espressif.com +arch/arm/src/stm32g4/hardware/stm32g4xxxx_pwr.h 59230071+hartmannathan@users.noreply.github.com raiden00@railab.me alin.jerpelea@sony.com gustavo.nihei@espressif.com +arch/arm/src/stm32g4/hardware/stm32g4xxxx_rcc.h 59230071+hartmannathan@users.noreply.github.com raiden00@railab.me danieloak@gmail.com liuxuanfu@xiaomi.com alin.jerpelea@sony.com +arch/arm/src/stm32g4/hardware/stm32g4xxxx_syscfg.h 59230071+hartmannathan@users.noreply.github.com raiden00@railab.me alin.jerpelea@sony.com gustavo.nihei@espressif.com +arch/arm/src/stm32g4/hardware/stm32g4xxxx_vrefbuf.h 59230071+hartmannathan@users.noreply.github.com raiden00@railab.me alin.jerpelea@sony.com gustavo.nihei@espressif.com +arch/arm/src/stm32g4/stm32.h alin.jerpelea@sony.com raiden00@railab.me abdelatif.guettouche@gmail.com raiden00pl@gmail.com xiaoxiang@xiaomi.com +arch/arm/src/stm32g4/stm32_rcc.c 59230071+hartmannathan@users.noreply.github.com alin.jerpelea@sony.com raiden00@railab.me xiaoxiang@xiaomi.com f.panag@amco.gr +arch/arm/src/stm32g4/stm32g4xxxx_rcc.c 59230071+hartmannathan@users.noreply.github.com raiden00@railab.me danieloak@gmail.com matteo.golin@gmail.com jerryslhao@gmail.com arch/arm/src/stm32h5/Kconfig kwilson@2g-eng.com tbennett@2g-eng.com 101105604+simbit18@users.noreply.github.com raiden00@railab.me jlange@2g-eng.com arch/arm/src/stm32h5/chip.h kwilson@2g-eng.com tbennett@2g-eng.com alin.jerpelea@sony.com arch/arm/src/stm32h5/hardware/stm32_adc.h tbennett@2g-eng.com 101105604+simbit18@users.noreply.github.com @@ -4276,6 +4319,34 @@ arch/arm/src/stm32h7/stm32h743xx_flash.c javiercasas@geotab.com petro.karashchen arch/arm/src/stm32h7/stm32h7b3xx_flash.c javiercasas@geotab.com petro.karashchenko@gmail.com alin.jerpelea@sony.com lipengfei28@xiaomi.com arch/arm/src/stm32h7/stm32h7x3xx_rcc.c simon@leitwert.ch raiden00pl@gmail.com david.sidrane@nscdg.com raiden00@railab.me anthony@vergeaero.com arch/arm/src/stm32h7/stm32h7x7xx_rcc.c lwazeh@gmail.com anthony@vergeaero.com raiden00@railab.me alin.jerpelea@sony.com jfbblue0922@gmail.com +arch/arm/src/stm32l0/Kconfig raiden00@railab.me +arch/arm/src/stm32l0/chip.h alin.jerpelea@sony.com acassis@gmail.com raiden00@railab.me raiden00pl@gmail.com +arch/arm/src/stm32l0/hardware/stm32_memorymap.h raiden00@railab.me +arch/arm/src/stm32l0/hardware/stm32_pinmap.h raiden00@railab.me +arch/arm/src/stm32l0/hardware/stm32l0_exti.h alin.jerpelea@sony.com raiden00pl@gmail.com raiden00@railab.me david_s5@usa.net bob.feretich@rafresearch.com +arch/arm/src/stm32l0/hardware/stm32l0_flash.h raiden00pl@gmail.com alin.jerpelea@sony.com raiden00@railab.me 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juha.niskanen@haltian.com matteo.golin@gmail.com xiaoxiang@xiaomi.com +arch/arm/src/stm32l1/Kconfig raiden00@railab.me +arch/arm/src/stm32l1/chip.h raiden00pl@gmail.com alin.jerpelea@sony.com raiden00@railab.me peter.barada@gmail.com paul-a.patience@polymtl.ca +arch/arm/src/stm32l1/hardware/stm32_memorymap.h raiden00@railab.me +arch/arm/src/stm32l1/hardware/stm32_pinmap.h raiden00@railab.me +arch/arm/src/stm32l1/hardware/stm32l15xxx_aes.h alin.jerpelea@sony.com raiden00@railab.me +arch/arm/src/stm32l1/hardware/stm32l15xxx_gpio.h alin.jerpelea@sony.com raiden00@railab.me hartman.nathan@gmail.com +arch/arm/src/stm32l1/hardware/stm32l15xxx_memorymap.h alin.jerpelea@sony.com juha.niskanen@haltian.com raiden00pl@gmail.com raiden00@railab.me +arch/arm/src/stm32l1/hardware/stm32l15xxx_pinmap.h David.Sidrane@NscDg.com alin.jerpelea@sony.com juha.niskanen@haltian.com raiden00pl@gmail.com raiden00@railab.me +arch/arm/src/stm32l1/hardware/stm32l15xxx_rcc.h alin.jerpelea@sony.com raiden00pl@gmail.com raiden00@railab.me gustavo.nihei@espressif.com xiaoxiang@xiaomi.com +arch/arm/src/stm32l1/hardware/stm32l15xxx_syscfg.h alin.jerpelea@sony.com raiden00@railab.me 59230071+hartmannathan@users.noreply.github.com +arch/arm/src/stm32l1/stm32.h alin.jerpelea@sony.com raiden00@railab.me abdelatif.guettouche@gmail.com raiden00pl@gmail.com xiaoxiang@xiaomi.com +arch/arm/src/stm32l1/stm32_rcc.c 59230071+hartmannathan@users.noreply.github.com alin.jerpelea@sony.com raiden00@railab.me xiaoxiang@xiaomi.com f.panag@amco.gr +arch/arm/src/stm32l1/stm32l15xxx_alarm.h NeilH20@biomonitors.com juha.niskanen@haltian.com alin.jerpelea@sony.com xiaoxiang@xiaomi.com 59230071+hartmannathan@users.noreply.github.com +arch/arm/src/stm32l1/stm32l15xxx_rcc.c 59230071+hartmannathan@users.noreply.github.com juha.niskanen@haltian.com alin.jerpelea@sony.com raiden00pl@gmail.com matteo.golin@gmail.com arch/arm/src/stm32l4/Kconfig dev@ziggurat29.com danieloak@gmail.com juha.niskanen@haltian.com sebastien@lorquet.fr arch/arm/src/stm32l4/chip.h sebastien@lorquet.fr alin.jerpelea@sony.com juha.niskanen@haltian.com arch/arm/src/stm32l4/hardware/stm32l4_adc.h danieloak@gmail.com alin.jerpelea@sony.com anchao@xiaomi.com acassis@gmail.com @@ -4698,12 +4769,10 @@ arch/arm/src/stm32wl5/stm32wl5_userspace.c michal.lyszczek@bofc.pl alin.jerpelea arch/arm/src/stm32wl5/stm32wl5_userspace.h michal.lyszczek@bofc.pl alin.jerpelea@sony.com arch/arm/src/stm32wl5/stm32wl5_waste.c michal.lyszczek@bofc.pl alin.jerpelea@sony.com arch/arm/src/stm32wl5/stm32wl5_waste.h michal.lyszczek@bofc.pl alin.jerpelea@sony.com - arch/arm/src/str71x/* alin.jerpelea@sony.com arch/arm/src/tiva/* alin.jerpelea@sony.com xiaoxiang@xiaomi.com hartman.nathan@gmail.com arch/arm/src/tlsr82/* wangbowen6@xiaomi.com devel@sumpfralle.de alin.jerpelea@sony.com arch/arm/src/tms570/* xiaoxiang@xiaomi.com alin.jerpelea@sony.com - arch/arm/src/xmc4/Kconfig 101105604+simbit18@users.noreply.github.com adrien.desproges@gmail.com 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anchao@xiaomi.com -boards/arm/stm32/stm32f334-disco/configs/powerled/defconfig alin.jerpelea@sony.com lucas.vaz@espressif.com xiaoxiang@xiaomi.com liguiding1@xiaomi.com anchao@xiaomi.com -boards/arm/stm32/stm32f334-disco/include/board.h alin.jerpelea@sony.com raiden00@railab.me devel@sumpfralle.de thomas.narayana-swamy@wandercraft.eu xiaoxiang@xiaomi.com -boards/arm/stm32/stm32f334-disco/scripts/ld.script alin.jerpelea@sony.com acassis@gmail.com no1wudi@qq.com cuiziwei@xiaomi.com -boards/arm/stm32/stm32f334-disco/src/stm32_adc.c alin.jerpelea@sony.com raiden00@railab.me xiaoxiang@xiaomi.com -boards/arm/stm32/stm32f334-disco/src/stm32_appinit.c alin.jerpelea@sony.com raiden00@railab.me gustavo.nihei@espressif.com 59230071+hartmannathan@users.noreply.github.com hartman.nathan@gmail.com -boards/arm/stm32/stm32f334-disco/src/stm32_autoleds.c alin.jerpelea@sony.com raiden00@railab.me -boards/arm/stm32/stm32f334-disco/src/stm32_boot.c alin.jerpelea@sony.com raiden00@railab.me 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rcsim10@gmail.com wangjianyu3@xiaomi.com -boards/arm/stm32/stm32f401rc-rs485/configs/rndis/defconfig rcsim10@gmail.com wangjianyu3@xiaomi.com acassis@gmail.com tiago.medicci@espressif.com -boards/arm/stm32/stm32f401rc-rs485/configs/sdcard/defconfig rcsim10@gmail.com wangjianyu3@xiaomi.com -boards/arm/stm32/stm32f401rc-rs485/configs/ssd1309/defconfig acassis@gmail.com wangjianyu3@xiaomi.com -boards/arm/stm32/stm32f401rc-rs485/configs/telnetd/defconfig rcsim10@gmail.com wangjianyu3@xiaomi.com -boards/arm/stm32/stm32f401rc-rs485/configs/usbmsc/defconfig rcsim10@gmail.com wangjianyu3@xiaomi.com -boards/arm/stm32/stm32f401rc-rs485/configs/usbnsh/defconfig rcsim10@gmail.com wangjianyu3@xiaomi.com -boards/arm/stm32/stm32f401rc-rs485/configs/ws2812/defconfig rcsim10@gmail.com wangjianyu3@xiaomi.com -boards/arm/stm32/stm32f401rc-rs485/include/board.h rcsim10@gmail.com halysson1007@gmail.com devel@sumpfralle.de alin.jerpelea@sony.com -boards/arm/stm32/stm32f401rc-rs485/scripts/ld.script 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alin.jerpelea@sony.com -boards/arm/stm32/stm32f411-minimum/Kconfig michal.lyszczek@bofc.pl 101105604+simbit18@users.noreply.github.com tolstov_den@mail.ru acassis@gmail.com -boards/arm/stm32/stm32f411-minimum/Kconfig.gpio michal.lyszczek@bofc.pl -boards/arm/stm32/stm32f411-minimum/configs/composite/defconfig tolstov_den@mail.ru acassis@gmail.com wangjianyu3@xiaomi.com -boards/arm/stm32/stm32f411-minimum/configs/nsh/defconfig acassis@gmail.com tolstov_den@mail.ru xiaoxiang@xiaomi.com wangjianyu3@xiaomi.com liguiding1@xiaomi.com -boards/arm/stm32/stm32f411-minimum/configs/pwm/defconfig samymtz66@gmail.com wangjianyu3@xiaomi.com -boards/arm/stm32/stm32f411-minimum/configs/rgbled/defconfig samymtz66@gmail.com wangjianyu3@xiaomi.com -boards/arm/stm32/stm32f411-minimum/configs/spifsnsh/defconfig tolstov_den@mail.ru acassis@gmail.com wangjianyu3@xiaomi.com -boards/arm/stm32/stm32f411-minimum/configs/usbmsc/defconfig tolstov_den@mail.ru acassis@gmail.com wangjianyu3@xiaomi.com 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+boards/arm/stm32l0/nucleo-l073rz/src/nucleo-l073rz.h alin.jerpelea@sony.com raiden00@railab.me xiaoxiang@xiaomi.com +boards/arm/stm32l0/nucleo-l073rz/src/stm32_appinit.c alin.jerpelea@sony.com raiden00@railab.me gustavo.nihei@espressif.com 59230071+hartmannathan@users.noreply.github.com hartman.nathan@gmail.com +boards/arm/stm32l0/nucleo-l073rz/src/stm32_autoleds.c alin.jerpelea@sony.com raiden00@railab.me +boards/arm/stm32l0/nucleo-l073rz/src/stm32_boot.c alin.jerpelea@sony.com raiden00@railab.me xiaoxiang@xiaomi.com +boards/arm/stm32l0/nucleo-l073rz/src/stm32_bringup.c alin.jerpelea@sony.com raiden00@railab.me xiaoxiang@xiaomi.com +boards/arm/stm32l0/nucleo-l073rz/src/stm32_buttons.c alin.jerpelea@sony.com xiaoxiang@xiaomi.com +boards/arm/stm32l0/nucleo-l073rz/src/stm32_mfrc522.c alin.jerpelea@sony.com raiden00@railab.me xiaoxiang@xiaomi.com +boards/arm/stm32l0/nucleo-l073rz/src/stm32_nrf24l01.c alin.jerpelea@sony.com raiden00@railab.me xiaoxiang@xiaomi.com +boards/arm/stm32l0/nucleo-l073rz/src/stm32_spi.c alin.jerpelea@sony.com raiden00@railab.me xiaoxiang@xiaomi.com +boards/arm/stm32l0/nucleo-l073rz/src/stm32_sx127x.c alin.jerpelea@sony.com raiden00@railab.me xiaoxiang@xiaomi.com +boards/arm/stm32f0/stm32f051-discovery/Kconfig alin.jerpelea@sony.com +boards/arm/stm32f0/stm32f051-discovery/configs/nsh/defconfig alin.jerpelea@sony.com xiaoxiang@xiaomi.com liguiding1@xiaomi.com dongjiuzhu1@xiaomi.com +boards/arm/stm32f0/stm32f051-discovery/include/board.h alin.jerpelea@sony.com raiden00@railab.me xiaoxiang@xiaomi.com devel@sumpfralle.de anthony@vergeaero.com +boards/arm/stm32f0/stm32f051-discovery/scripts/flash.ld alin.jerpelea@sony.com raiden00@railab.me cuiziwei@xiaomi.com +boards/arm/stm32f0/stm32f051-discovery/src/stm32_appinit.c alin.jerpelea@sony.com 59230071+hartmannathan@users.noreply.github.com hartman.nathan@gmail.com +boards/arm/stm32f0/stm32f051-discovery/src/stm32_autoleds.c alin.jerpelea@sony.com +boards/arm/stm32f0/stm32f051-discovery/src/stm32_boot.c alin.jerpelea@sony.com xiaoxiang@xiaomi.com +boards/arm/stm32f0/stm32f051-discovery/src/stm32_bringup.c alin.jerpelea@sony.com xiaoxiang@xiaomi.com +boards/arm/stm32f0/stm32f051-discovery/src/stm32_buttons.c alin.jerpelea@sony.com xiaoxiang@xiaomi.com gustavo.nihei@espressif.com +boards/arm/stm32f0/stm32f051-discovery/src/stm32_userleds.c alin.jerpelea@sony.com xiaoxiang@xiaomi.com +boards/arm/stm32f0/stm32f051-discovery/src/stm32f051-discovery.h alin.jerpelea@sony.com xiaoxiang@xiaomi.com +boards/arm/stm32f0/stm32f072-discovery/Kconfig alin.jerpelea@sony.com +boards/arm/stm32f0/stm32f072-discovery/configs/nsh/defconfig alin.jerpelea@sony.com xiaoxiang@xiaomi.com liguiding1@xiaomi.com dongjiuzhu1@xiaomi.com +boards/arm/stm32f0/stm32f072-discovery/include/board.h alin.jerpelea@sony.com raiden00@railab.me xiaoxiang@xiaomi.com devel@sumpfralle.de anthony@vergeaero.com +boards/arm/stm32f0/stm32f072-discovery/scripts/flash.ld alin.jerpelea@sony.com raiden00@railab.me cuiziwei@xiaomi.com +boards/arm/stm32f0/stm32f072-discovery/src/stm32_appinit.c alin.jerpelea@sony.com 59230071+hartmannathan@users.noreply.github.com hartman.nathan@gmail.com +boards/arm/stm32f0/stm32f072-discovery/src/stm32_autoleds.c alin.jerpelea@sony.com +boards/arm/stm32f0/stm32f072-discovery/src/stm32_boot.c alin.jerpelea@sony.com xiaoxiang@xiaomi.com gustavo.nihei@espressif.com +boards/arm/stm32f0/stm32f072-discovery/src/stm32_bringup.c alin.jerpelea@sony.com xiaoxiang@xiaomi.com +boards/arm/stm32f0/stm32f072-discovery/src/stm32_buttons.c alin.jerpelea@sony.com xiaoxiang@xiaomi.com gustavo.nihei@espressif.com +boards/arm/stm32f0/stm32f072-discovery/src/stm32_userleds.c alin.jerpelea@sony.com xiaoxiang@xiaomi.com +boards/arm/stm32f0/stm32f072-discovery/src/stm32f072-discovery.h alin.jerpelea@sony.com xiaoxiang@xiaomi.com +boards/arm/stm32g0/stm32g071b-disco/Kconfig raiden00@railab.me +boards/arm/stm32g0/stm32g071b-disco/configs/nsh/defconfig raiden00@railab.me xiaoxiang@xiaomi.com wangjianyu3@xiaomi.com +boards/arm/stm32g0/stm32g071b-disco/configs/oled/defconfig raiden00@railab.me xiaoxiang@xiaomi.com wangjianyu3@xiaomi.com +boards/arm/stm32g0/stm32g071b-disco/include/board.h raiden00@railab.me alin.jerpelea@sony.com +boards/arm/stm32g0/stm32g071b-disco/scripts/ld.script raiden00@railab.me cuiziwei@xiaomi.com alin.jerpelea@sony.com +boards/arm/stm32g0/stm32g071b-disco/src/stm32_appinit.c raiden00@railab.me alin.jerpelea@sony.com +boards/arm/stm32g0/stm32g071b-disco/src/stm32_boot.c raiden00@railab.me alin.jerpelea@sony.com +boards/arm/stm32g0/stm32g071b-disco/src/stm32_bringup.c raiden00@railab.me alin.jerpelea@sony.com +boards/arm/stm32g0/stm32g071b-disco/src/stm32_djoystick.c raiden00@railab.me alin.jerpelea@sony.com +boards/arm/stm32g0/stm32g071b-disco/src/stm32_gpio.c raiden00@railab.me alin.jerpelea@sony.com +boards/arm/stm32g0/stm32g071b-disco/src/stm32_ina226.c raiden00@railab.me alin.jerpelea@sony.com +boards/arm/stm32g0/stm32g071b-disco/src/stm32_lcd_ssd1306.c raiden00@railab.me alin.jerpelea@sony.com +boards/arm/stm32g0/stm32g071b-disco/src/stm32_spi.c raiden00@railab.me alin.jerpelea@sony.com +boards/arm/stm32g0/stm32g071b-disco/src/stm32_userleds.c raiden00@railab.me alin.jerpelea@sony.com +boards/arm/stm32g0/stm32g071b-disco/src/stm32g071b-disco.h raiden00@railab.me alin.jerpelea@sony.com +boards/arm/stm32l0/stm32l0538-disco/Kconfig raiden00@railab.me +boards/arm/stm32l0/stm32l0538-disco/configs/nsh/defconfig raiden00@railab.me xiaoxiang@xiaomi.com dongjiuzhu1@xiaomi.com +boards/arm/stm32l0/stm32l0538-disco/include/board.h raiden00@railab.me devel@sumpfralle.de alin.jerpelea@sony.com +boards/arm/stm32l0/stm32l0538-disco/scripts/ld.script raiden00@railab.me cuiziwei@xiaomi.com alin.jerpelea@sony.com +boards/arm/stm32l0/stm32l0538-disco/src/stm32_appinit.c raiden00@railab.me alin.jerpelea@sony.com +boards/arm/stm32l0/stm32l0538-disco/src/stm32_autoleds.c raiden00@railab.me alin.jerpelea@sony.com +boards/arm/stm32l0/stm32l0538-disco/src/stm32_boot.c raiden00@railab.me alin.jerpelea@sony.com +boards/arm/stm32l0/stm32l0538-disco/src/stm32_bringup.c raiden00@railab.me alin.jerpelea@sony.com +boards/arm/stm32l0/stm32l0538-disco/src/stm32_buttons.c raiden00@railab.me alin.jerpelea@sony.com +boards/arm/stm32l0/stm32l0538-disco/src/stm32l0538-disco.h raiden00@railab.me alin.jerpelea@sony.com boards/arm/stm32f7/common/Kconfig raiden00@railab.me acassis@gmail.com boards/arm/stm32f7/common/Makefile acassis@gmail.com alin.jerpelea@sony.com boards/arm/stm32f7/common/include/stm32_bh1750.h acassis@gmail.com alin.jerpelea@sony.com diff --git a/Documentation/applications/examples/ft80x/index.rst b/Documentation/applications/examples/ft80x/index.rst index 9020d67baf0a2..e093218737a09 100644 --- a/Documentation/applications/examples/ft80x/index.rst +++ b/Documentation/applications/examples/ft80x/index.rst @@ -4,4 +4,4 @@ This examples has ports of several FTDI demos for the FTDI/BridgeTek FT80x GUI chip. As an example configuration, see -``nuttx/boards/arm/stm32/viewtool-stm32f107/configs/ft80x/defconfig``. +``nuttx/boards/arm/stm32f1/viewtool-stm32f107/configs/ft80x/defconfig``. diff --git a/Documentation/applications/system/usbmsc/index.rst b/Documentation/applications/system/usbmsc/index.rst index 57da5b303581a..f387859f0ca77 100644 --- a/Documentation/applications/system/usbmsc/index.rst +++ b/Documentation/applications/system/usbmsc/index.rst @@ -13,7 +13,7 @@ This function will be called by the ``system/usbmsc`` indirectly via the ``board block device drivers. For examples of the implementation of ``board_usbmsc_initialize()`` see ``boards/arm/lpc214x/mcu123-lpc214x/src/up_usbmsc.c`` or -``boards/arm/stm32/stm3210e-eval/src/usbmsc.c``. +``boards/arm/stm32f1/stm3210e-eval/src/usbmsc.c``. Configuration options: diff --git a/Documentation/components/drivers/character/input/keypad.rst b/Documentation/components/drivers/character/input/keypad.rst index 93d357bc7ac29..58425f4fd5e32 100644 --- a/Documentation/components/drivers/character/input/keypad.rst +++ b/Documentation/components/drivers/character/input/keypad.rst @@ -62,7 +62,7 @@ kbd-codec layer. ``board_kmatrix_initialize("/dev/keypad0")``). **Reference Implementation (STM32F4Discovery)**. The current reference -is in ``boards/arm/stm32/common/src/stm32_kmatrix_gpio.c``: +is in ``boards/arm/common/stm32/src/stm32_kmatrix_gpio.c``: - Rows: ``BOARD_KMATRIX_ROW0..3`` (outputs) - Columns: ``BOARD_KMATRIX_COL0..2`` (inputs with pull-up) diff --git a/Documentation/components/drivers/character/input/mpr121.rst b/Documentation/components/drivers/character/input/mpr121.rst index 9a24b3158fbf4..c8ccae104208a 100644 --- a/Documentation/components/drivers/character/input/mpr121.rst +++ b/Documentation/components/drivers/character/input/mpr121.rst @@ -53,7 +53,7 @@ kbd-codec layer. ``board_mpr121_initialize(0, 1)`` for ``/dev/keymap0`` and ``i2c1``). **Reference Implementation (STM32F4Discovery)**. The current reference -is in ``boards/arm/stm32/common/src/stm32_mpr121.c``: +is in ``boards/arm/common/stm32/src/stm32_mpr121.c``: - Keymap: 4x3 keypad layout - Registration: ``board_mpr121_initialize()`` calls diff --git a/Documentation/components/drivers/character/input/sbutton.rst b/Documentation/components/drivers/character/input/sbutton.rst index 3281db7fd4a51..ca118f95e7430 100644 --- a/Documentation/components/drivers/character/input/sbutton.rst +++ b/Documentation/components/drivers/character/input/sbutton.rst @@ -23,7 +23,7 @@ It uses a kind of "polymorphism" in C to allow the driver to get access to the functions responsible to attach and enable the interrupt and to get the status of the pin. See ``include/nuttx/input/sbutton.h`` -and ``boards/arm/stm32/common/src/stm32_sbutton.c`` to understand +and ``boards/arm/common/stm32/src/stm32_sbutton.c`` to understand better how it works. But basically the board file (config data) creates a struct when the first field (variable) is the config struct used the but SButton driver (``drivers/input/sbutton.c``). diff --git a/Documentation/components/drivers/character/leds/userled.rst b/Documentation/components/drivers/character/leds/userled.rst index dd8ae215ccbea..feccbcb4c7dfa 100644 --- a/Documentation/components/drivers/character/leds/userled.rst +++ b/Documentation/components/drivers/character/leds/userled.rst @@ -59,7 +59,7 @@ Files supporting USERLED can be found in the following locations: Something important to note is that your board initialization code (normally named ``_bringup.c`` should call the function to register the driver. -For stm32f4discovery board this initialization code is placed at ``boards/arm/stm32/stm32f4discovery/src/stm32_bringup.c`` and this is the block responsible to initialize the subsystem: +For stm32f4discovery board this initialization code is placed at ``boards/arm/stm32f4/stm32f4discovery/src/stm32_bringup.c`` and this is the block responsible to initialize the subsystem: .. code-block:: C diff --git a/Documentation/components/drivers/character/serial.rst b/Documentation/components/drivers/character/serial.rst index 7af619f1270ea..6fb2e9cb3fc3f 100644 --- a/Documentation/components/drivers/character/serial.rst +++ b/Documentation/components/drivers/character/serial.rst @@ -39,7 +39,7 @@ Serial Device Drivers `character drivers <#chardrivers>`__ and are accessed as other character drivers. -- **Examples**: ``arch/arm/src/stm32/stm32_serial.c``, +- **Examples**: ``arch/arm/src/common/stm32/stm32_serial_m3m4_usart_v1v2v3v4.c``, ``arch/arm/src/lpc214x/lpc214x_serial.c``, ``arch/z16/src/z16f/z16f_serial.c``, etc. diff --git a/Documentation/components/drivers/character/timers/capture.rst b/Documentation/components/drivers/character/timers/capture.rst index 026174e83a1f5..50208b54f37da 100644 --- a/Documentation/components/drivers/character/timers/capture.rst +++ b/Documentation/components/drivers/character/timers/capture.rst @@ -109,7 +109,7 @@ To enable the capture driver, enable the following configuration options: * ``CONFIG_CAPTURE`` - Enable the capture driver framework * ``CONFIG_CAPTURE_NOTIFY`` - Enable signal notification support for edge events * ``CONFIG_FAKE_CAPTURE`` - Enable fake capture driver for testing (generates 10Hz signal with 50% duty cycle) -* ``CONFIG_STM32H7_TIM4_CAP`` (for STM32H7 Timer 4, platform-specific) +* ``CONFIG_STM32_TIM4_CAP`` (for STM32H7 Timer 4, platform-specific) The ``CONFIG_CAPTURE`` option enables the lower-half driver and registers the ``/dev/capture`` device. diff --git a/Documentation/components/drivers/special/lcd.rst b/Documentation/components/drivers/special/lcd.rst index 3e415e19694c9..5417a2a1bb96a 100644 --- a/Documentation/components/drivers/special/lcd.rst +++ b/Documentation/components/drivers/special/lcd.rst @@ -85,7 +85,7 @@ LCDs Generic LCD driver for LCDs based on the Solomon Systech SSD1289 LCD controller. Think of this as a template for an LCD driver that you will probably have to customize for any particular LCD - hardware. (See also boards/arm/stm32/hymini-stm32v/src/ssd1289.c below). + hardware. (See also boards/arm/stm32f1/hymini-stm32v/src/ssd1289.c below). - ``st7567.c`` @@ -120,7 +120,7 @@ OLEDs OLED Display Module, UUG-2864AMBAG01, Univision Technology Inc. Based on the SH1101A controller. Example usage:: - boards/arm/stm32/stm32f4discovery + boards/arm/stm32f4/stm32f4discovery boards/arm/lpc214x/zp214xpa - ``ug-9664hswag01.c`` @@ -140,7 +140,7 @@ OLEDs Densitron Technologies DD-12864WO-4A which is based on SSD1309 LCD controller. Example usage:: - boards/arm/stm32/stm32f4discovery + boards/arm/stm32f4/stm32f4discovery boards/arm/sam34/sam4l-xplained Segment LCDS (SLCDs) diff --git a/Documentation/components/drivers/special/sdio.rst b/Documentation/components/drivers/special/sdio.rst index 6822b82d38867..ba62f20495750 100644 --- a/Documentation/components/drivers/special/sdio.rst +++ b/Documentation/components/drivers/special/sdio.rst @@ -29,7 +29,7 @@ SDIO Device Drivers #. Provide that instance to the initialization method of the higher level device driver. -- **Examples**: ``arch/arm/src/stm32/stm32_sdio.c`` and +- **Examples**: ``arch/arm/src/common/stm32/stm32_sdio_m3m4_v1.c`` and ``drivers/mmcsd/mmcsd_sdio.c`` Implementing an SDIO lower-half diff --git a/Documentation/components/drivers/special/usbdev.rst b/Documentation/components/drivers/special/usbdev.rst index 589a60b7b7f0c..1b83d9a20d783 100644 --- a/Documentation/components/drivers/special/usbdev.rst +++ b/Documentation/components/drivers/special/usbdev.rst @@ -19,7 +19,7 @@ USB Device-Side Drivers ``arch/arm/src/lpc17xx_40xx/lpc17_40_usbdev.c``, ``arch/arm/src/lpc214x/lpc214x_usbdev.c``, ``arch/arm/src/lpc313x/lpc313x_usbdev.c``, and - ``arch/arm/src/stm32/stm32_usbdev.c``. + ``arch/arm/src/common/stm32/stm32_usbdev_m3m4_v1.c``. - ``struct usbdevclass_driver_s``. Each USB device class driver must implement an instance of diff --git a/Documentation/components/drivers/special/usbhost.rst b/Documentation/components/drivers/special/usbhost.rst index 63077758d102b..078677d5e2968 100644 --- a/Documentation/components/drivers/special/usbhost.rst +++ b/Documentation/components/drivers/special/usbhost.rst @@ -17,7 +17,7 @@ USB Host-Side Drivers **Examples**: ``arch/arm/src/lpc17xx_40xx/lpc17_40_usbhost.c``, - ``arch/arm/src/stm32/stm32_otgfshost.c``, + ``arch/arm/src/common/stm32/stm32_otgfshost_m3m4_v1.c``, ``arch/arm/src/sama5/sam_ohci.c``, and ``arch/arm/src/sama5/sam_ehci.c``. diff --git a/Documentation/contributing/making-changes.rst b/Documentation/contributing/making-changes.rst index a60182210b486..7cbe6cb0add28 100644 --- a/Documentation/contributing/making-changes.rst +++ b/Documentation/contributing/making-changes.rst @@ -227,7 +227,7 @@ squash before submitting the Pull Request: .. code-block:: bash - arch/arm/stm32/: Add arch support for stm32 platform + arch/arm/stm32f4/: Add arch support for stm32f4 platform This patch adds initial support for stm32 platform. Please read the documentation included for more details how to wire the display. diff --git a/Documentation/guides/changing_systemclockconfig.rst b/Documentation/guides/changing_systemclockconfig.rst index a6291c712a88f..579795ff72ac6 100644 --- a/Documentation/guides/changing_systemclockconfig.rst +++ b/Documentation/guides/changing_systemclockconfig.rst @@ -28,7 +28,7 @@ Custom Clock Configuration The ``configs/vsn/`` configuration does something like you say. It skips the initial clock configuration by defining ``CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG=y``. Then the normal clock -configuration logic in ``arch/arm/src/stm32/stm32_rcc.c`` is not executed. +configuration logic in ``arch/arm/src/stm32f4/stm32_rcc.c`` is not executed. Instead, the "custom" clock initialization at ``configs/vsn/src/sysclock.c`` is called: @@ -83,7 +83,7 @@ are hardcoded in the board.h header file. So you have two options: 2. **Variable Peripheral Clocking**. You can make the peripheral clocking variable. I had to do this for the SAMA5Dx family. Look at - ``boards/arm/stm32/sama5d4-ek/include/board_sdram.h`` for example. Notice + ``boards/arm/sama5/sama5d4-ek/include/board_sdram.h`` for example. Notice that the frequencies are not constants, but function calls: .. code-block:: c @@ -169,4 +169,4 @@ Here is some Power Management documentation: .. toctree:: :maxdepth: 1 - /components/drivers/special/power/pm/index.rst \ No newline at end of file + /components/drivers/special/power/pm/index.rst diff --git a/Documentation/guides/etcromfs.rst b/Documentation/guides/etcromfs.rst index 8bc92ef989e61..39ce17bddd2ea 100644 --- a/Documentation/guides/etcromfs.rst +++ b/Documentation/guides/etcromfs.rst @@ -86,7 +86,7 @@ behave as follows at Nuttx start-up time: ``CONFIG_ETC_ROMFS=y`` in the NuttX configuration file. They might provide useful examples: - - ``boards/arm/stm32/hymini-stm32v/nsh2`` + - ``boards/arm/stm32f1/hymini-stm32v/nsh2`` - ``boards/arm/dm320/ntosd-dm320/nsh`` - ``boards/sim/sim/sim/nsh`` - ``boards/sim/sim/sim/nsh2`` diff --git a/Documentation/guides/index.rst b/Documentation/guides/index.rst index f1e11bc9a456b..acbb2a118b554 100644 --- a/Documentation/guides/index.rst +++ b/Documentation/guides/index.rst @@ -61,4 +61,5 @@ Guides optee.rst qemu_tips.rst lwl.rst + stm32_ports.rst diff --git a/Documentation/guides/ipv6.rst b/Documentation/guides/ipv6.rst index d67c30c51899b..bf02bc57f8137 100644 --- a/Documentation/guides/ipv6.rst +++ b/Documentation/guides/ipv6.rst @@ -218,7 +218,7 @@ Board Configurations At present, there are three board configuration that are pre-configured to use IPv6: ``nuttx/boards/arm/tiva/dk-tm4c129x/configs/ipv6``, -``nuttx/boards/arm/stm32/stm32f4discovery/ipv6``, and +``nuttx/boards/arm/stm32f4/stm32f4discovery/ipv6``, and ``nuttx/boards/arm/tiva/tm4c1294-launchpad/configs/ipv6``. These default configurations have only IPv6 enabled. But the `README` files at in those board directories describes how to enable `both` IPv4 and IPv6 simultaneously. @@ -345,4 +345,4 @@ the network utils (``netutils``). * Netutils: The network utilities in ``apps/netutils`` have been adapted to work with IPv6: DHCP, FTP, TFTP, Telnet, etc. Support for managing IPv6 address have been included in the ``netlib``, but nothing else has yet been - updated. \ No newline at end of file + updated. diff --git a/Documentation/guides/nsh_network_link_management.rst b/Documentation/guides/nsh_network_link_management.rst index 3100f7ba7d810..05cc4f9d41946 100644 --- a/Documentation/guides/nsh_network_link_management.rst +++ b/Documentation/guides/nsh_network_link_management.rst @@ -45,7 +45,7 @@ must be satisfied: are implemented for Atmel SAM4/4, SAMA5 families, and for the STMicro STM32. See ``nuttx/arch/arm/src/sam34/sam_emac.c``, ``nuttx/arch/arm/src/sam34/sam_emaca.c``, ``sam_emacb.c``, and ``sam_gmac.c``, - and ``nuttx/arch/arm/src/stm32/stm32_eth.c``. + and ``nuttx/arch/arm/src/common/stm32/stm32_eth_m3m4_v1.c``. - ``CONFIG_ARCH_PHY_INTERRUPT`` This is not a user-selectable option. Rather, it is set when selecting a board that supports PHY interrupts. In most architectures, the PHY interrupt is not diff --git a/Documentation/guides/ofloader.rst b/Documentation/guides/ofloader.rst index 743fb9d1328b5..4dfe2375dc989 100644 --- a/Documentation/guides/ofloader.rst +++ b/Documentation/guides/ofloader.rst @@ -52,7 +52,7 @@ Precautions 1.If you need to implement the ofloader on a different board, you will need to read the `wiki ` and refer to the implementation of "ofloader.ld" linker script located -in the "boards/arm/stm32/stm32f429i-disco/scripts" directory. +in the "boards/arm/stm32f4/stm32f429i-disco/scripts" directory. This linker script defines how the different sections of the NuttX image are placed in memory. You should configure the corresponding sections to be located in RAM, where the J-Link can write the image correctly. diff --git a/Documentation/guides/partially_linked_elf.rst b/Documentation/guides/partially_linked_elf.rst index 0fe721e69edc0..b2b6ee8f307d3 100644 --- a/Documentation/guides/partially_linked_elf.rst +++ b/Documentation/guides/partially_linked_elf.rst @@ -40,7 +40,7 @@ compatible with the example provided here: In this example, let's illustrate this using an STM32F4-Discovery configuration. We will assume that you have modified the - ``boards/arm/stm32/stm32fdiscovery/src/stm32_bringup.c`` file, adding the + ``boards/arm/stm32f4/stm32f4discovery/src/stm32_bringup.c`` file, adding the following: .. code-block:: c diff --git a/Documentation/guides/port_drivers_to_stm32f7.rst b/Documentation/guides/port_drivers_to_stm32f7.rst index 0d552320695c8..876d184242fc3 100644 --- a/Documentation/guides/port_drivers_to_stm32f7.rst +++ b/Documentation/guides/port_drivers_to_stm32f7.rst @@ -191,7 +191,7 @@ An Example There is a good example in the STM32 Ethernet driver. The STM32 F7 Ethernet driver (``arch/arm/src/stm32f7/stm32_ethernet.c``) derives directly from the STM32 F4 Ethernet driver -(``arch/arm/src/stm32/stm32_eth.c``). These two Ethernet MAC peripherals +(``arch/arm/src/common/stm32/stm32_eth_m3m4_v1.c``). These two Ethernet MAC peripherals are nearly identical. Only changes that are a direct consequence of the STM32 F7 D-Cache were required to make the driver work on the STM32 F7. Those changes are summarized below. @@ -262,7 +262,7 @@ the buffers to the Cortex-M7 D-Cache line size: #define DMA_ALIGN_UP(n) (((n) + DMA_BUFFER_MASK) & ~DMA_BUFFER_MASK) #define DMA_ALIGN_DOWN(n) ((n) & ~DMA_BUFFER_MASK) - #ifndef CONFIG_STM32F7_ETH_ENHANCEDDESC + #ifndef CONFIG_STM32_ETH_ENHANCEDDESC # define RXDESC_SIZE 16 # define TXDESC_SIZE 16 #else @@ -274,10 +274,10 @@ the buffers to the Cortex-M7 D-Cache line size: #define TXDESC_PADSIZE DMA_ALIGN_UP(TXDESC_SIZE) #define ALIGNED_BUFSIZE DMA_ALIGN_UP(ETH_BUFSIZE) - #define RXTABLE_SIZE (STM32F7_NETHERNET * CONFIG_STM32F7_ETH_NRXDESC) - #define TXTABLE_SIZE (STM32F7_NETHERNET * CONFIG_STM32F7_ETH_NTXDESC) + #define RXTABLE_SIZE (STM32F7_NETHERNET * CONFIG_STM32_ETH_NRXDESC) + #define TXTABLE_SIZE (STM32F7_NETHERNET * CONFIG_STM32_ETH_NTXDESC) - #define RXBUFFER_SIZE (CONFIG_STM32F7_ETH_NRXDESC * ALIGNED_BUFSIZE) + #define RXBUFFER_SIZE (CONFIG_STM32_ETH_NRXDESC * ALIGNED_BUFSIZE) #define RXBUFFER_ALLOC (STM32F7_NETHERNET * RXBUFFER_SIZE) #define TXBUFFER_SIZE (STM32_ETH_NFREEBUFFERS * ALIGNED_BUFSIZE) @@ -366,8 +366,8 @@ Here is an example where the RX descriptors are invalidated: for (i = 0; (rxdesc->rdes0 & ETH_RDES0_OWN) == 0 && - i < CONFIG_STM32F7_ETH_NRXDESC && - priv->inflight < CONFIG_STM32F7_ETH_NTXDESC; + i < CONFIG_STM32_ETH_NRXDESC && + priv->inflight < CONFIG_STM32_ETH_NTXDESC; i++) { ... diff --git a/Documentation/guides/protected_build.rst b/Documentation/guides/protected_build.rst index e2a60713a3ae8..a49702df5c7ee 100644 --- a/Documentation/guides/protected_build.rst +++ b/Documentation/guides/protected_build.rst @@ -177,10 +177,10 @@ Files and Directories Here is a summary of directories and files used by the STM32F4Discovery protected build: -* ``boards/arm/stm32/stm32f4discovery/configs/kostest``. This is the kernel +* ``boards/arm/stm32f4/stm32f4discovery/configs/kostest``. This is the kernel mode OS test configuration. The two standard configuration files can be found in this directory: (1) ``defconfig`` and (2) ``Make.defs``. -* ``boards/arm/stm32/stm32f4discovery/kernel``. This is the first past +* ``boards/arm/stm32f4/stm32f4discovery/kernel``. This is the first past build directory. The Makefile in this directory is invoked to produce the pass1 object (``nuttx_user.elf`` in this case). The second pass object is created by ``arch/arm/src/Makefile``. Also @@ -188,7 +188,7 @@ protected build: contains a header that includes information need by the kernel blob in order to interface with the user-code. That header is defined in by this file. -* ``boards/arm/stm32/stm32f4discovery/scripts``. Linker scripts for +* ``boards/arm/stm32f4/stm32f4discovery/scripts``. Linker scripts for the kernel mode build are found in this directory. This includes (1) ``memory.ld`` which hold the common memory map, (2) ``user-space.ld`` that is used for linking the pass1 user-mode blob, and (3) @@ -314,11 +314,11 @@ Comparing the "Flat" Build Configuration with the Protected Build Configuration =============================================================================== Compare, for example the configuration -``boards/arm/stm32/stm32f4discovery/configs/ostest`` and the -configuration ``boards/arm/stm32/stm32f4discovery/configs/kostest``. +``boards/arm/stm32f4/stm32f4discovery/configs/ostest`` and the +configuration ``boards/arm/stm32f4/stm32f4discovery/configs/kostest``. These two configurations are identical except that one builds a "flat" version of OS test and the other builds a kernel version -of the OS test. See the file ``boards/arm/stm32/stm32f4discovery/README.txt`` +of the OS test. See the file ``boards/arm/stm32f4/stm32f4discovery/README.txt`` for more details about those configurations. The configurations can be compared using the ``cmpconfig`` tool: @@ -328,7 +328,7 @@ The configurations can be compared using the ``cmpconfig`` tool: cd tools make -f Makefile.host cmpconfig cd .. - tools/cmpconfig boards/arm/stm32/stm32f4discovery/configs/ostest/defconfig boards/arm/stm32/stm32f4discovery/configs/kostest/defconfig + tools/cmpconfig boards/arm/stm32f4/stm32f4discovery/configs/ostest/defconfig boards/arm/stm32f4/stm32f4discovery/configs/kostest/defconfig Here is a summary of the meaning of all of the important differences in the configurations. This should be enough information for you to convert any @@ -337,7 +337,7 @@ configuration from a "flat" to a protected build: * ``CONFIG_BUILD_2PASS=y``. This enables the two pass build. * ``CONFIG_BUILD_PROTECTED=y``. This option enables the "two pass" protected build. -* ``CONFIG_PASS1_BUILDIR="boards/arm/stm32/stm32f4discovery/kernel"``. +* ``CONFIG_PASS1_BUILDIR="boards/arm/stm32f4/stm32f4discovery/kernel"``. This tells the build system the (relative) location of the pass1 build directory. * ``CONFIG_PASS1_OBJECT=""``. In some "two pass" build configurations, the build system need to know the name of the first pass object. @@ -382,7 +382,7 @@ configuration from a "flat" to a protected build: These includes such things as initializing device drivers. These same initialization steps must be performed in kernel mode for the protected build and ``CONFIG_BOARD_LATE_INITIALIZE``. - See ``boards/arm/stm32/stm32f4discovery/src/up_boot.c`` for an + See ``boards/arm/stm32f4/stm32f4discovery/src/up_boot.c`` for an example of such board initialization code. Architecture-Specific Options: @@ -409,8 +409,8 @@ Size Expansion The protected build will, or course, result in a FLASH image that is larger than that of the corresponding "flat" build. How much larger? I don't have the numbers in hand, but you can build -``boards/arm/stm32/stm32f4discovery/configs/nsh`` and -``boards/arm/stm32/stm32f4discovery/configs/kostest`` and compare +``boards/arm/stm32f4/stm32f4discovery/configs/nsh`` and +``boards/arm/stm32f4/stm32f4discovery/configs/kostest`` and compare the resulting binaries for yourself using the ``size`` command. Increases in size are expected because: diff --git a/Documentation/guides/renode.rst b/Documentation/guides/renode.rst index b3918d2e8ca8b..ccafddf944fb7 100644 --- a/Documentation/guides/renode.rst +++ b/Documentation/guides/renode.rst @@ -119,7 +119,7 @@ nucleo-h743zi ============= Renode doesn't support ``PWR_CSR1_ACTVOSRDY`` bit so we have to disable -it with ``CONFIG_STM32H7_PWR_IGNORE_ACTVOSRDY=y``. +it with ``CONFIG_STM32_PWR_IGNORE_ACTVOSRDY=y``. Renode script:: diff --git a/Documentation/guides/smaller_vector_tables.rst b/Documentation/guides/smaller_vector_tables.rst index 2cc629fa2a5c8..ed44b0432d201 100644 --- a/Documentation/guides/smaller_vector_tables.rst +++ b/Documentation/guides/smaller_vector_tables.rst @@ -202,7 +202,7 @@ Most ARMv7-M architectures support two mechanism for handling interrupts: ``CONFIG_ARMV7M_CMNVECTOR=y`` that can be found in ``arch/arm/src/armv7-m/``, and * MCU-specific interrupt handling logic. For the - STM32, this logic can be found at ``arch/arm/src/stm32/gnu/stm32_vectors.S``. + STM32, this logic can be found at ``arch/arm/src/stm32f4/gnu/stm32_vectors.S``. The `common` vector logic is slightly more efficient, the MCU-specific logic is slightly more flexible. @@ -229,7 +229,7 @@ This technical approach requires changes to three files: define ``only`` the small set of 20 ``mapped`` IRQ numbers in the range from 0 through 19. It would also set ``NR_IRQS`` to the value 20. -* A new header file at ``arch/arm/src/stm32/hardware``, say +* A new header file at ``arch/arm/src/stm32f4/hardware``, say ``xyz_vector.h``. It would be similar to the other vector definitions files in that directory: It will consist of a sequence of 100 ``VECTOR`` and ``UNUSED`` macros. It will @@ -248,7 +248,7 @@ This has all been replaced with the common vector handling at Vector Definitions ================== -In ``arch/arm/src/stm32/gnu/stm32_vector.S``, notice that the +In ``arch/arm/src/stm32f4/gnu/stm32_vectors.S``, notice that the ``xyz_vector.h`` file will be included twice. Before each inclusion, the macros ``VECTOR`` and ``UNUSED`` are defined. @@ -290,7 +290,7 @@ file like this: ... Where the value of ``STM32_IRQ_USART1`` was defined to -be 12 in the ``arch/arm/include/stm32/xyz_irq.h`` header +be 12 in the ``arch/arm/include/stm32f4/xyz_irq.h`` header file. When ``xyz_vector.h`` is included by ``stm32_vectors.S`` with the above definitions for ``VECTOR`` and ``UNUSED``, the following would result: @@ -349,7 +349,7 @@ second time the ``xzy_vector.h`` is included by ``stm32_vectors.S``: In the above USART1 example, a single handler would be generated that will provide the IRQ number 12. Remember that 12 is the expansion of the macro ``STM32_IRQ_USART1`` -that is provided in the ``arch/arm/include/stm32/xyz_irq.h`` +that is provided in the ``arch/arm/include/stm32f4/xyz_irq.h`` header file: .. code-block:: asm diff --git a/Documentation/guides/stm32_ports.rst b/Documentation/guides/stm32_ports.rst new file mode 100644 index 0000000000000..8121a5c241b3c --- /dev/null +++ b/Documentation/guides/stm32_ports.rst @@ -0,0 +1,899 @@ +=========== +STM32 ports +=========== + +This page records the STM32 families supported by the NuttX ARM port and the +peripheral IP-core selections used by the common STM32 implementation. The +goal of this inventory is to keep shared STM32 code selected by peripheral IP +version, not by family name. + +Family status +============= + +============ ================ =========== =========================== +Family CPU core Status NuttX source directory +============ ================ =========== =========================== +STM32C0 Cortex-M0+ supported ``arch/arm/src/stm32c0`` +STM32C5 Cortex-M33 unsupported none +STM32F0 Cortex-M0 supported ``arch/arm/src/stm32f0`` +STM32F1 Cortex-M3 supported ``arch/arm/src/stm32f1`` +STM32F2 Cortex-M3 supported ``arch/arm/src/stm32f2`` +STM32F3 Cortex-M4 supported ``arch/arm/src/stm32f3`` +STM32F4 Cortex-M4 supported ``arch/arm/src/stm32f4`` +STM32F7 Cortex-M7 supported ``arch/arm/src/stm32f7`` +STM32G0 Cortex-M0+ supported ``arch/arm/src/stm32g0`` +STM32G4 Cortex-M4 supported ``arch/arm/src/stm32g4`` +STM32H5 Cortex-M33 supported ``arch/arm/src/stm32h5`` +STM32H7 Cortex-M7 supported ``arch/arm/src/stm32h7`` +STM32L0 Cortex-M0+ supported ``arch/arm/src/stm32l0`` +STM32L1 Cortex-M3 supported ``arch/arm/src/stm32l1`` +STM32L4 Cortex-M4 supported ``arch/arm/src/stm32l4`` +STM32L5 Cortex-M33 supported ``arch/arm/src/stm32l5`` +STM32MP1 Cortex-A7 unsupported none +STM32MP1 Cortex-M4 unsupported none +STM32MP2 Cortex-A35 unsupported none +STM32MP2 Cortex-M33 unsupported none +STM32N6 Cortex-M55 supported ``arch/arm/src/stm32n6`` +STM32U0 Cortex-M0+ unsupported none +STM32U3 Cortex-M33 unsupported none +STM32U5 Cortex-M33 supported ``arch/arm/src/stm32u5`` +STM32WB Cortex-M4 supported ``arch/arm/src/stm32wb`` +STM32WB Cortex-M0+ unsupported none +STM32WB0 Cortex-M0+ unsupported none +STM32WBA Cortex-M33 unsupported none +STM32WL3 Cortex-M0+ unsupported none +STM32WL5 Cortex-M4 supported ``arch/arm/src/stm32wl5`` +STM32WL5 Cortex-M0+ unsupported none +STM32WLE Cortex-M4 unsupported none +============ ================ =========== =========================== + +Normalized common IP-core selections +==================================== + +Common STM32 code is selected by ``STM32_HAVE_IP_*`` Kconfig symbols. The +selector names describe the common implementation or hardware register layout; +they must not encode a composite family name. A family not listed for an IP +core does not currently select that normalized common IP flag. + +============ ============================================================== +Peripheral Common IP-core selectors +============ ============================================================== +ADC ``STM32_HAVE_IP_ADC_M3M4_V1``, + ``STM32_HAVE_IP_ADC_M3M4_V1_BASIC``, + ``STM32_HAVE_IP_ADC_M3M4_V2``, + ``STM32_HAVE_IP_ADC_M3M4_V2_BASIC``, + ``STM32_HAVE_IP_ADC_M0_V1``, ``STM32_HAVE_IP_SDADC_M3M4_V1`` +AES/CRYP ``STM32_HAVE_IP_AES_M0_V1``, ``STM32_HAVE_IP_AES_M3M4_V1``, + ``STM32_HAVE_IP_CRYPTO_M3M4_V1`` +Backup SRAM ``STM32_HAVE_IP_BBSRAM_M3M4_V1``, + ``STM32_HAVE_IP_BKP_M3M4_V1`` +CAN/FDCAN ``STM32_HAVE_IP_CAN_BXCAN_M0_V1``, + ``STM32_HAVE_IP_CAN_BXCAN_M3M4_V1``, + ``STM32_HAVE_IP_FDCAN_MCAN_M0_V1``, + ``STM32_HAVE_IP_FDCAN_MCAN_M3M4_V1`` +CCM ``STM32_HAVE_IP_CCM_M3M4_V1`` +COMP ``STM32_HAVE_IP_COMP_M0_V1``, ``STM32_HAVE_IP_COMP_M3M4_V1``, + ``STM32_HAVE_IP_COMP_M3M4_V2`` +CORDIC ``STM32_HAVE_IP_CORDIC_M3M4_V1`` +DAC ``STM32_HAVE_IP_DAC_M0_V1``, ``STM32_HAVE_IP_DAC_M3M4_V1``, + ``STM32_HAVE_IP_DAC_M3M4_V2`` +DBGMCU ``STM32_HAVE_IP_DBGMCU_M0_V1``, + ``STM32_HAVE_IP_DBGMCU_M3M4_V1``, + ``STM32_HAVE_IP_DBGMCU_M3M4_V2``, + ``STM32_HAVE_IP_DBGMCU_M3M4_V3`` +DCMI ``STM32_HAVE_IP_DCMI_V1`` +DMA ``STM32_HAVE_IP_DMA_V1``, ``STM32_HAVE_IP_DMA_V1_7CH``, + ``STM32_HAVE_IP_DMA_V1_7CH_DMAMUX``, + ``STM32_HAVE_IP_DMA_V1_8CH``, + ``STM32_HAVE_IP_DMA_V1_8CH_DMAMUX``, ``STM32_HAVE_IP_DMA_V2``, + ``STM32_HAVE_IP_DMA_V2_STREAM`` +DMA2D ``STM32_HAVE_IP_DMA2D_M3M4_V1`` +ETH ``STM32_HAVE_IP_ETHMAC_M3M4_V1`` +EXTI ``STM32_HAVE_IP_EXTI_V1``, ``STM32_HAVE_IP_EXTI_V2`` +FLASH ``STM32_HAVE_IP_FLASH_M0_V1``, + ``STM32_HAVE_IP_FLASH_M3M4_V1``, + ``STM32_HAVE_IP_FLASH_M0_G0C0``, + ``STM32_HAVE_IP_FLASH_M3M4_L1``, + ``STM32_HAVE_IP_FLASH_M3M4_F1F3``, + ``STM32_HAVE_IP_FLASH_M3M4_F2F4``, + ``STM32_HAVE_IP_FLASH_M3M4_G4`` +FMC/FSMC ``STM32_HAVE_IP_FMC_M3M4_V1``, ``STM32_HAVE_IP_FSMC_M3M4_V1`` +GPIO ``STM32_HAVE_IP_GPIO_M0_V1``, ``STM32_HAVE_IP_GPIO_M3M4_V1`` +I2C ``STM32_HAVE_IP_I2C_M0_V1``, ``STM32_HAVE_IP_I2C_M3M4_V1``, + ``STM32_HAVE_IP_I2C_M3M4_V2`` +I2S ``STM32_HAVE_IP_I2S_M3M4_V1`` +LTDC ``STM32_HAVE_IP_LTDC_M3M4_V1`` +OPAMP ``STM32_HAVE_IP_OPAMP_M3M4_V1`` +Power ``STM32_HAVE_IP_PWR_M0_V1``, ``STM32_HAVE_IP_PWR_G0``, + ``STM32_HAVE_IP_PWR_M3M4_V1`` +RNG ``STM32_HAVE_IP_RNG_M0_V1``, ``STM32_HAVE_IP_RNG_M3M4_V1`` +RTC ``STM32_HAVE_IP_RTC_COUNTER_M3M4_V1``, + ``STM32_HAVE_IP_RTCC_M0_V1``, ``STM32_HAVE_IP_RTCC_M3M4_V1``, + ``STM32_HAVE_IP_RTCC_M3M4_L1``, + ``STM32_HAVE_IP_RTCC_M3M4_F4``, ``STM32_HAVE_IP_RTC_M3M4_V1`` +SDIO ``STM32_HAVE_IP_SDIO_M3M4_V1`` +SPI ``STM32_HAVE_IP_SPI_V1``, ``STM32_HAVE_IP_SPI_V2``, + ``STM32_HAVE_IP_SPI_V3``, ``STM32_HAVE_IP_SPI_V4`` +System ``STM32_HAVE_IP_DFUMODE_M3M4_V1``, + ``STM32_HAVE_IP_HSI48_M0_V1``, + ``STM32_HAVE_IP_SYSCFG_M3M4_V1`` +TIM ``STM32_HAVE_IP_TIMERS_M0_V1``, + ``STM32_HAVE_IP_TIMERS_M3M4_V1``, + ``STM32_HAVE_IP_TIMERS_M3M4_V2``, + ``STM32_HAVE_IP_TIMERS_M3M4_V3``, + ``STM32_HAVE_IP_HRTIM_M3M4_V1``, + ``STM32_HAVE_IP_ONESHOT_M3M4_V1``, + ``STM32_HAVE_IP_FREERUN_M3M4_V1`` +USART/LPUART ``STM32_HAVE_IP_USART_V1``, ``STM32_HAVE_IP_USART_V2``, + ``STM32_HAVE_IP_USART_V3``, ``STM32_HAVE_IP_USART_V4`` +USB ``STM32_HAVE_IP_USBDEV_M0_V1``, + ``STM32_HAVE_IP_USBDEV_M3M4_V1``, + ``STM32_HAVE_IP_USBFS_M3M4_V1``, + ``STM32_HAVE_IP_OTGFS_M3M4_V1``, + ``STM32_HAVE_IP_OTGHS_M3M4_V1`` +Watchdog ``STM32_HAVE_IP_WDG_M0_V1``, ``STM32_HAVE_IP_WDG_M3M4_V1`` +============ ============================================================== + +DMA public interfaces are shared by channel and stream DMA; register maps and +request mappings stay split by hardware shape. + +Kconfig option organization +=========================== + +STM32 common Kconfig symbols are split into three layers, each with a fixed +home so contributors always know where a given option belongs: + +================================= ============================ ==================== +Layer Symbol form File +================================= ============================ ==================== +Capability flags (hidden) ``STM32_HAVE_*`` ``Kconfig.have`` +Instance feature flags (hidden) ``STM32__HAVE_*`` ``Kconfig.`` +Peripheral selection ``STM32_`` ``Kconfig.periph`` +Peripheral options ``STM32__*`` ``Kconfig.`` +================================= ============================ ==================== + +All ``STM32_HAVE_*`` and ``STM32_HAVE_IP_*`` symbols are defined in the single +file ``arch/arm/src/common/stm32/Kconfig.have`` — the authoritative description +of what hardware exists. The ``STM32_HAVE_IP_*`` selectors listed above are a +subset of it. The rules for these capability flags are: + +* They are prompt-less ``bool`` symbols, defined exactly once. Never give a + capability flag a prompt. +* Family Kconfig files (``arch/arm/src/stm32/Kconfig``) ``select`` these + symbols to describe the silicon of each chip. +* Presence and feature flags may use ``default y if `` so + the right instances and features light up automatically once a family selects + its IP-core version. +* User-visible options in ``Kconfig.periph`` and ``Kconfig.`` should + ``depends on`` the capability flags rather than on family names. + +The ``STM32_HAVE_`` prefix is reserved for **chip capabilities** — things the +silicon *has*, independent of any single peripheral instance. Those live in +``Kconfig.have``. A flag that instead describes a feature of one **specific +peripheral instance** ("ADC3 *has* a DMA path", "USART1 *supports* RX DMA") is +not a chip capability: it must be named ``STM32__HAVE_`` +(``HAVE`` *after* the instance) and defined in that peripheral's +``Kconfig.`` file, never in ``Kconfig.have``. It is still a prompt-less +``bool`` ``select``-ed by the family Kconfig files, just homed with the rest of +its peripheral's options. For example: + +============================ ============================ ==================== +Wrong (chip-capability form) Correct (instance-feature) Home +============================ ============================ ==================== +``STM32_HAVE_ADC3_DMA`` ``STM32_ADC3_HAVE_DMA`` ``Kconfig.adc`` +``STM32_HAVE_SDADC1_DMA`` ``STM32_SDADC1_HAVE_DMA`` ``Kconfig.sdadc`` +``STM32_HAVE_USART1_RXDMA`` ``STM32_USART1_HAVE_RXDMA`` ``Kconfig.uart`` +``STM32_HAVE_PHY_POLLED`` ``STM32_PHY_HAVE_POLLED`` ``Kconfig.eth`` +============================ ============================ ==================== + +Capability-flag naming: + +* IP-core version selectors: ``STM32_HAVE_IP___V`` (see + `IP-core naming convention`_; the version number resets per core). +* Per-instance presence: ``STM32_HAVE_`` (for example + ``STM32_HAVE_ADC2`` or ``STM32_HAVE_USART3``). +* Feature capability (chip-wide, **no** instance number): ``STM32_HAVE_`` + (for example ``STM32_HAVE_ADC_OVERSAMPLE``). A feature tied to a specific + instance is **not** written this way — see ``STM32__HAVE_`` + above. +* Per-instance feature: ``STM32__HAVE_`` (for example + ``STM32_ADC3_HAVE_DMA``), defined in ``Kconfig.``. + +Family peripheral inventory +=========================== + +Each family table records every peripheral group currently tracked by this +inventory. ``unsupported`` means the peripheral is not available in that +family or is intentionally not implemented by the NuttX family port. +``to be done`` means the peripheral exists or needs confirmation, but the +exact IP core version has not been documented yet. + +STM32C0 +------- + +============ ============ ============ +Peripheral Core version NuttX status +============ ============ ============ +ADC v1 supported +AES/CRYP v1 unsupported +CAN/FDCAN FDCAN supported +CRC to be done unsupported +DAC v1 unsupported +DBGMCU v1 supported +DMA v1 supported +DMAMUX v1 7ch supported +EXTI v2 supported +FLASH G0/C0 supported +GPIO v1 supported +I2C v1 supported +IWDG v1 supported +PWR G0 supported +RCC to be done supported +RTC RTCC M0 unsupported +SPI/I2S v2 supported +SYSCFG to be done unsupported +TIM v1 supported +USART/LPUART v4 supported +USB device unsupported +WWDG v1 supported +============ ============ ============ + +STM32F0 +------- + +============ ============ ============ +Peripheral Core version NuttX status +============ ============ ============ +ADC v1 supported +CAN/FDCAN bxCAN unsupported +CRC to be done unsupported +DAC v1 unsupported +DMA v1 supported +EXTI v1 supported +FLASH M0 v1 unsupported +GPIO v1 supported +HDMI-CEC to be done unsupported +I2C v1 supported +IWDG v1 supported +PWR v1 supported +RCC to be done supported +RTC RTCC M0 unsupported +SPI/I2S v2 supported +SYSCFG to be done supported +TIM v1 supported +USART/LPUART v3 supported +USB device supported +WWDG v1 supported +============ ============ ============ + +STM32F1 +------- + +============ ============= ============ +Peripheral Core version NuttX status +============ ============= ============ +ADC v1 basic supported +CAN/FDCAN bxCAN supported +CRC to be done unsupported +DAC v1 supported +DBGMCU v1 supported +DMA v1 supported +ETH to be done supported +EXTI v1 supported +FLASH F1/F3 supported +FSMC v1 supported +GPIO v1 supported +I2C v1 supported +IWDG v1 supported +PWR v1 supported +RCC to be done supported +RTC counter supported +SDIO v1 supported +SPI/I2S v1 supported +TIM v1 supported +USART/LPUART v1 supported +USB device/OTG FS supported +WWDG v1 supported +============ ============= ============ + +STM32F2 +------- + +============ ============ ============ +Peripheral Core version NuttX status +============ ============ ============ +ADC v1 supported +CAN/FDCAN bxCAN supported +CRYP v1 supported +DAC v1 supported +DMA v2 supported +ETH to be done supported +EXTI v1 supported +FLASH F2/F4 supported +FSMC v1 supported +GPIO v1 supported +HASH to be done to be done +I2C v1 supported +IWDG v1 supported +RCC to be done supported +RNG v1 supported +RTC RTCC v1 supported +SDIO v1 supported +SPI/I2S v2 supported +TIM v1 supported +USART/LPUART v2 supported +USB OTG FS/HS supported +WWDG v1 supported +============ ============ ============ + +STM32F3 +------- + +============ ============== ============ +Peripheral Core version NuttX status +============ ============== ============ +ADC v1 basic or v2 supported +CAN/FDCAN bxCAN supported +COMP v1 supported +DAC v1 supported +DBGMCU v2 supported +DMA v1 supported +EXTI v1 supported +FLASH F1/F3 supported +GPIO v1 supported +HRTIM v1 supported +I2C v2 supported +IWDG v1 supported +OPAMP v1 supported +RCC to be done supported +RTC RTCC v1 supported +SDADC v1 supported +SPI/I2S v3 supported +SYSCFG v1 supported +TIM v1 or v2 supported +USART/LPUART v3 supported +USB device supported +WWDG v1 supported +============ ============== ============ + +STM32F4 +------- + +============ ============ ============ +Peripheral Core version NuttX status +============ ============ ============ +ADC v1 supported +CAN/FDCAN bxCAN supported +CRYP v1 supported +DAC v1 supported +DMA v2 supported +DMA2D v1 supported +ETH to be done supported +EXTI v1 supported +FLASH F2/F4 supported +FMC/FSMC v1 supported +GPIO v1 supported +HASH to be done to be done +I2C v1 supported +IWDG v1 supported +LTDC v1 supported +QUADSPI to be done supported +RCC to be done supported +RNG v1 supported +RTC RTCC F4 supported +SDIO v1 supported +SPI/I2S v2 supported +TIM v1 supported +USART/LPUART v2 supported +USB OTG FS/HS supported +WWDG v1 supported +============ ============ ============ + +STM32G4 +------- + +============ ============ ============ +Peripheral Core version NuttX status +============ ============ ============ +ADC v2 supported +AES v1 supported +CAN/FDCAN FDCAN supported +COMP v2 supported +CORDIC v1 supported +DAC v2 supported +DMA v1 supported +DMAMUX v1 8ch supported +EXTI v2 supported +FLASH G4 supported +GPIO v1 supported +HRTIM v1 supported +I2C v2 supported +IWDG v1 supported +OPAMP v1 supported +RCC to be done supported +RNG v1 supported +RTC RTCC v1 supported +SPI/I2S v3 supported +TIM v3 supported +USART/LPUART v4 supported +USB device supported +WWDG v1 supported +============ ============ ============ + +STM32L4 +------- + +============ ============ ============ +Peripheral Core version NuttX status +============ ============ ============ +ADC to be done supported +CAN/FDCAN bxCAN supported +COMP to be done supported +DAC to be done supported +DFSDM to be done supported +DMA v1+DMAMUX supported +EXTI to be done supported +FLASH to be done supported +GPIO to be done supported +I2C to be done supported +IWDG v1 supported +LPTIM to be done supported +PWR to be done supported +QSPI to be done supported +RCC to be done supported +RNG to be done supported +RTC to be done supported +SAI to be done supported +SDMMC to be done supported +SPI/I2S to be done supported +TIM to be done supported +USART/LPUART v3 supported +USB OTG FS supported +============ ============ ============ + +STM32F7 +------- + +============ ============ ============ +Peripheral Core version NuttX status +============ ============ ============ +ADC to be done supported +CAN/FDCAN bxCAN supported +DAC to be done supported +DMA v2 style supported +DMA2D v1 supported +ETH to be done supported +EXTI to be done supported +FLASH to be done supported +FMC/FSMC to be done supported +GPIO to be done supported +I2C to be done supported +IWDG v1 supported +LTDC to be done supported +PWR to be done to be done +QUADSPI to be done supported +RCC to be done supported +RNG to be done supported +RTC to be done supported +SDMMC to be done supported +SPI/I2S to be done to be done +TIM to be done supported +USART/LPUART v3 supported +USB OTG FS/HS supported +WWDG v1 supported +============ ============ ============ + +STM32G0 +------- + +============ ============ ============ +Peripheral Core version NuttX status +============ ============ ============ +ADC v1 supported +AES v1 supported +CAN/FDCAN FDCAN unsupported +DAC v1 unsupported +DMA v1 supported +DMAMUX v1 7ch supported +EXTI v2 supported +FLASH G0/C0 unsupported +GPIO v1 supported +I2C v1 supported +IWDG v1 supported +PWR G0 unsupported +RCC to be done supported +RNG v1 supported +RTC RTCC M0 unsupported +SPI/I2S v2 supported +SYSCFG to be done supported +TIM v1 supported +USART/LPUART v4 supported +USB device to be done +WWDG v1 supported +============ ============ ============ + +STM32H5 +------- + +============ ============ ============ +Peripheral Core version NuttX status +============ ============ ============ +ADC to be done supported +AES/CRYP to be done unsupported +CAN/FDCAN FDCAN supported +DAC to be done unsupported +DTS to be done supported +ETH to be done supported +EXTI to be done unsupported +FLASH to be done supported +GPIO to be done supported +GPDMA to be done supported +I2C to be done supported +ICACHE to be done supported +OCTOSPI to be done supported +PWR to be done supported +RCC to be done supported +SPI/I2S to be done supported +TIM to be done supported +USART/LPUART v3 supported +USB FS supported +============ ============ ============ + +STM32H7 +------- + +============ ============ ============ +Peripheral Core version NuttX status +============ ============ ============ +ADC to be done supported +BDMA to be done supported +CAN/FDCAN FDCAN supported +DAC to be done supported +DMA v2 style supported +DMA2D to be done supported +ETH to be done supported +EXTI to be done supported +FLASH to be done supported +FMC/FSMC to be done supported +GPIO to be done supported +HSEM to be done supported +I2C to be done supported +IWDG v1 supported +LTDC to be done supported +MDMA to be done to be done +PWR to be done to be done +QUADSPI to be done supported +RCC to be done supported +RNG to be done supported +RTC to be done supported +SDMMC to be done supported +SPI/I2S to be done to be done +TIM to be done supported +USART/LPUART v4 supported +USB OTG FS/HS supported +WWDG v1 supported +============ ============ ============ + +STM32L0 +------- + +============ ============ ============ +Peripheral Core version NuttX status +============ ============ ============ +ADC v1 supported +AES v1 supported +CAN/FDCAN to be done unsupported +DAC v1 unsupported +DMA v1 supported +EXTI v1 supported +FLASH M0 v1 unsupported +GPIO v1 supported +I2C v1 supported +IWDG v1 supported +PWR v1 supported +RCC to be done supported +RNG v1 supported +RTC RTCC M0 unsupported +SPI/I2S v1 supported +TIM v1 supported +USART/LPUART v3 supported +USB device supported +WWDG v1 supported +============ ============ ============ + +STM32L1 +------- + +============ ============ ============ +Peripheral Core version NuttX status +============ ============ ============ +ADC v1 supported +AES v1 to be done +CAN/FDCAN bxCAN unsupported +DAC v1 supported +DBGMCU v2 supported +DMA v1 supported +EXTI v1 supported +FLASH L1 supported +FSMC v1 supported +GPIO v1 supported +I2C v1 supported +IWDG v1 supported +LCD to be done to be done +PWR v1 supported +RCC to be done supported +RTC RTCC L1 supported +SDIO v1 supported +SPI/I2S v1 supported +TIM v1 supported +USART/LPUART v2 supported +USB device supported +WWDG v1 supported +============ ============ ============ + +STM32L5 +------- + +============ ============ ============ +Peripheral Core version NuttX status +============ ============ ============ +ADC to be done unsupported +DAC to be done unsupported +DMA/DMAMUX to be done unsupported +EXTI to be done supported +FLASH to be done supported +GPIO to be done supported +GTZC to be done unsupported +HASH to be done unsupported +I2C to be done unsupported +OCTOSPI to be done unsupported +PWR to be done supported +RCC to be done supported +RNG to be done unsupported +RTC to be done unsupported +SDMMC to be done unsupported +SPI/I2S to be done supported +TIM/LPTIM to be done supported +USART/LPUART v3 supported +USB device unsupported +============ ============ ============ + +STM32N6 +------- + +============ ============ ============ +Peripheral Core version NuttX status +============ ============ ============ +ADC to be done unsupported +CAN/FDCAN to be done unsupported +DAC to be done unsupported +ETH to be done unsupported +EXTI to be done supported +GPIO to be done supported +GPDMA to be done unsupported +I2C to be done unsupported +PWR to be done supported +RCC to be done supported +SPI/I2S to be done unsupported +TIM to be done supported +USART/LPUART v4 supported +USB device unsupported +XSPI to be done unsupported +============ ============ ============ + +STM32U5 +------- + +============ ============ ============ +Peripheral Core version NuttX status +============ ============ ============ +ADC to be done unsupported +CAN/FDCAN FDCAN unsupported +DAC to be done unsupported +DCACHE to be done unsupported +EXTI to be done supported +FLASH to be done supported +GPIO to be done supported +GPDMA to be done unsupported +HASH to be done unsupported +I2C to be done supported +ICACHE to be done unsupported +OCTOSPI to be done unsupported +PWR to be done supported +RCC to be done supported +RNG to be done unsupported +RTC to be done unsupported +SAES/AES to be done unsupported +SDMMC to be done unsupported +SPI/I2S to be done supported +TAMP to be done unsupported +TIM/LPTIM to be done supported +USART/LPUART v3 supported +USB device supported +============ ============ ============ + +STM32WB +------- + +============ ============ ============ +Peripheral Core version NuttX status +============ ============ ============ +ADC to be done supported +AES to be done supported +CAN/FDCAN to be done unsupported +DAC to be done unsupported +DMA to be done supported +EXTI to be done supported +FLASH to be done supported +GPIO to be done supported +I2C to be done supported +IPCC to be done supported +PWR to be done supported +Radio to be done supported +RCC to be done supported +RNG to be done supported +RTC to be done supported +SPI/I2S to be done supported +TIM/LPTIM to be done supported +USART/LPUART v4 supported +USB device supported +============ ============ ============ + +STM32WL/WL5 +----------- + +============ ============ ============ +Peripheral Core version NuttX status +============ ============ ============ +ADC to be done to be done +AES to be done to be done +CAN/FDCAN to be done unsupported +DAC to be done unsupported +DMA to be done to be done +EXTI to be done supported +FLASH to be done supported +GPIO to be done supported +I2C to be done to be done +IPCC to be done supported +PWR to be done supported +Radio to be done to be done +RCC to be done supported +RNG to be done to be done +RTC to be done to be done +SPI/I2S to be done supported +TIM/LPTIM to be done supported +USART/LPUART v3 supported +USB to be done unsupported +============ ============ ============ + +Source naming rules +=================== + +IP-core naming convention +------------------------- + +STM32 common files use a ``_`` naming convention that +encodes the CPU core family and peripheral IP version in filenames and +Kconfig symbols. Version numbers are reset per core: the first version +of a peripheral on a given core is ``V1``. + +**Header file naming** (under ``arch/arm/src/common/stm32/``): + +- Facade headers: ``stm32_.h`` — dispatch on Kconfig IP symbols +- M0-core variants: ``stm32__m0_v1.h`` +- M3/M4-core variants: ``stm32__m3m4_v1.h``, ``stm32__m3m4_v2.h`` +- Combined variants: ``stm32__m3m4_v1v2.h``, ``stm32__m3m4_v1v2v3.h`` + +**Source file naming** (``.c`` files): + +- Follow the same convention as headers: ``stm32_gpio_m3m4_v1v2.c``, + ``stm32_adc_m0_v1.c``, ``stm32_tim_m0_v1.c``, ``stm32_pwm_m3m4_v1v2v3.c`` + +**Kconfig symbol naming** (``CONFIG_STM32_HAVE_IP___``): + +- M0: ``CONFIG_STM32_HAVE_IP_GPIO_M0_V1``, ``CONFIG_STM32_HAVE_IP_ADC_M0_V1`` +- M3/M4: ``CONFIG_STM32_HAVE_IP_GPIO_M3M4_V1``, + ``CONFIG_STM32_HAVE_IP_ADC_M3M4_V1``, ``CONFIG_STM32_HAVE_IP_ADC_M3M4_V2``, + ``CONFIG_STM32_HAVE_IP_TIMERS_M3M4_V1``, ``CONFIG_STM32_HAVE_IP_TIMERS_M3M4_V2``, + ``CONFIG_STM32_HAVE_IP_TIMERS_M3M4_V3`` + +Note that in the future the core prefix may be dropped and a single +version number space used across all cores. For now the core prefix is +kept to make migration of families into common code simpler. + +Common STM32 files should follow these rules: + +* Files shared by more than one family are placed under + ``arch/arm/src/common/stm32``. +* Board-facing public headers use stable peripheral names such as + ``stm32_adc.h``, ``stm32_gpio.h``, and ``stm32_uart.h``. Boards and + drivers should not include IP-versioned public headers directly. +* Public STM32 symbols must use canonical ``stm32_*`` names, not + family-prefixed names (for example, use ``stm32_tim_init``, + ``stm32_dmachannel``, and ``stm32_caninitialize`` rather than + ``stm32l4_*``/``stm32h7_*`` forms). +* Public API-facing type names must also use canonical ``stm32_*`` forms + (for example, ``struct stm32_tim_dev_s``, ``struct stm32_dmaregs_s``, + and ``struct stm32_freerun_s``). +* When an equivalent STM32 API already exists, new family code must reuse + the exact public function name and compatible prototype/type signature. +* Family root aggregation headers should use ``stm32.h`` and family code + should include ```` for that root header include path. +* Hardware register selectors keep the ``hardware/stm32_.h`` + public name and may include hardware-version headers when those headers + describe real register layouts. +* Private common implementation selectors may be split only when the API, + register map, or reusable hardware shape really differs. Prefer capability + names over family names for these splits. +* Common STM32 source and hardware header names must not encode composite + family groups. If a reusable distinction is still named after a family, the + next cleanup step is to map that distinction to an IP-core version or a + hardware feature. +* Public compatibility selectors such as ``stm32_adc.h`` and + ``hardware/stm32_adc.h`` keep their public include names while selecting the + proper common implementation internally. + +Hardware definition naming convention +-------------------------------------- + +All STM32 hardware definitions (IRQ vectors, peripheral counts, SRAM sizes) +must use the standard ``STM32_`` prefix rather than family-specific prefixes. +Family-specific prefixes prevent common code from referencing hardware +definitions across families and create unnecessary differences between ports. + +**IRQ vectors** must use ``STM32_IRQ_`` (not ``STM32L4_IRQ_``, +``STM32WB_IRQ_``, etc.). + +**Peripheral count macros** (``NATIM``, ``NADC``, ``NSPI``, etc.) and SRAM +size macros must use ``STM32_`` prefix (not ``STM32F7_``, ``STM32H5_``, etc.). + +**Per-family hardware register definitions** (in ``arch/arm/src//hardware/``) +must use ``STM32_XXX_`` (not ``STM32L4_XXX_``, ``STM32WB4_XXX_``, etc.). + +Next steps +========== + +The goal is for all STM32 families to follow the rules above, so that shared +code is selected by peripheral IP version instead of family name and code +duplication is limited. The remaining work is: + +Architecture +------------ + +* Migrate the remaining families to use the common ``arch/arm/src/common/stm32`` + code. +* Review every family's selectors so they use the correct IP cores and select + only the peripherals each family actually supports. +* Remove all family-specific options that were left for later, and simplify the + complex Kconfig conditions. +* Unify the remaining peripheral-driver public headers so the API is the same + for all families. +* Better organize the CMake and Make build files for common STM32. Now it's a mess. +* Unify all supported features across families. + +Boards +------ + +* Move all families to shared ``boards/common/stm32`` board code, including + boards that do not yet use the recently added common code. +* Unify all supported features across boards of the same class (such as the + Nucleo boards) so they follow the same patterns. + +Kconfig simplification +---------------------- + +Many Kconfig conditions are still long, mix normalized ``STM32_HAVE_IP_*`` +flags with family names, and rely on composite family-group symbols +(``STM32_COMMON_LEGACY``, ``STM32_COMMON_F7_H7``, ``STM32_COMMON_L4_L5_U5``, +``STM32_COMMON_L4_H5_L5_U5``, …) that the naming rules forbid. These are the +most likely to need rework and should be reduced to depend on capability flags +only: + +* ``Kconfig.tim`` and ``Kconfig.uart`` hold the bulk of the family-name + conditions (hundreds of lines each) and are the biggest cleanup. +* ``Kconfig.adc``, ``Kconfig.periph`` and ``Kconfig.have`` carry many mixed + family/IP ``||`` chains (for example ``(STM32_HAVE_IP_ADC_M3M4_V1 || + STM32_HAVE_IP_ADC_M3M4_V2) || ARCH_CHIP_STM32F7``), where F7/H5/L4 are patched + in by family name only because they have no IP flag yet. +* Replace the composite ``STM32_COMMON_*`` family-group symbols with per-IP-core + or per-feature flags. diff --git a/Documentation/guides/stm32ccm.rst b/Documentation/guides/stm32ccm.rst index 4ec8ba5acb398..1414813180506 100644 --- a/Documentation/guides/stm32ccm.rst +++ b/Documentation/guides/stm32ccm.rst @@ -34,7 +34,7 @@ This memory allocator is automatically enabled when the following options are se * ``CONFIG_MM_MULTIHEAP`` Support for multiple heaps is enabled. Under those conditions, the CCM memory allocator is enabled and the allocator -interfaces prototyped in the ``arch/arm/src/stm32/stm32_ccm.h`` are available. +interfaces prototyped in the ``arch/arm/src/common/stm32/stm32_ccm.h`` are available. NOTE: These interfaces are, technically, not prototyped since they are really provided via C pre-processor macros. diff --git a/Documentation/guides/usingkernelthreads.rst b/Documentation/guides/usingkernelthreads.rst index 5818842037a20..434dacd62a04a 100644 --- a/Documentation/guides/usingkernelthreads.rst +++ b/Documentation/guides/usingkernelthreads.rst @@ -52,7 +52,7 @@ In order to build the task into the OS as a kernel thread, you simply have to: (1) place the kernel thread code in your board source code directory, and (2) start it with ``kthread_create()`` in your board bring-up logic. There a few examples of this in the NuttX source tree. Here is one: -`https://github.com/apache/nuttx/blob/master/boards/arm/stm32/viewtool-stm32f107/src/stm32_highpri.c `_ +`https://github.com/apache/nuttx/blob/master/boards/arm/stm32f1/viewtool-stm32f107/src/stm32_highpri.c `_ So that is another trick that you can use to architecture optimal solutions: Create parts of your applications as kernel threads: They need to reside in diff --git a/Documentation/guides/zerolatencyinterrupts.rst b/Documentation/guides/zerolatencyinterrupts.rst index 7acd9352656fc..2a5f14e70c2ed 100644 --- a/Documentation/guides/zerolatencyinterrupts.rst +++ b/Documentation/guides/zerolatencyinterrupts.rst @@ -302,8 +302,8 @@ You can find an example that tests the high priority, nested interrupts in the N * :doc:`/platforms/arm/stm32f1/boards/viewtool-stm32f107/index` Description of the configuration -* ``nuttx/boards/arm/stm32/viewtool-stm32f107/highpri`` Test configuration +* ``nuttx/boards/arm/stm32f1/viewtool-stm32f107/highpri`` Test configuration -* ``nuttx/boards/arm/stm32/viewtool-stm32f107/src/stm32_highpri`` Test +* ``nuttx/boards/arm/stm32f1/viewtool-stm32f107/src/stm32_highpri`` Test driver. diff --git a/Documentation/implementation/chip_h.rst b/Documentation/implementation/chip_h.rst index a2b7158412689..2a9d9641986be 100644 --- a/Documentation/implementation/chip_h.rst +++ b/Documentation/implementation/chip_h.rst @@ -12,16 +12,16 @@ If you wonder about the purpose of the two ``chip.h`` files in each arm chip. .. code:: sh $ find arch/arm -name chip.h | grep stm32 - arch/arm/include/stm32/chip.h - arch/arm/src/stm32/chip.h + arch/arm/include/stm32f4/chip.h + arch/arm/src/stm32f4/chip.h -The reason behind ``arch/arm/src/stm32/chip.h`` file was a bad idea +The reason behind ``arch/arm/src/stm32f4/chip.h`` file was a bad idea that happened a long time ago. Right now, I believe that its only required when ``CONFIG_ARMV7M_CMNVECTOR`` -is selected in the configuration. In that case, ``arch/arm/src/stm32/chip.h`` +is selected in the configuration. In that case, ``arch/arm/src/stm32f4/chip.h`` is included by ``arch/arm/src/armv7-m/up_vectors.c`` in order provide -the number of interrupt vectors. In stm32, ``arch/arm/src/stm32/chip.h`` +the number of interrupt vectors. In stm32, ``arch/arm/src/stm32f4/chip.h`` provides the number of vectors indirectly by including the correct, chip-specific vectors.h file. This function is a little more obvious in ``arch/arm/srch/lpc43xx/chip.h``. diff --git a/Documentation/implementation/file_descriptors.rst b/Documentation/implementation/file_descriptors.rst index dfad984a347c8..a54ffae2f04ee 100644 --- a/Documentation/implementation/file_descriptors.rst +++ b/Documentation/implementation/file_descriptors.rst @@ -135,7 +135,7 @@ Detached File Helpers Once the file structure has been detached from its file descriptor, you can no longer use the standard VFS functions ``read()``, ``write()``, ``ioctl()``, etc. Fortunately, there are a parallel set of interfaces -that can be used with detached files. These are decribed in detail +that can be used with detached files. These are described in detail in ``include/nuttx/fs/fs.h`` and only listed here below: .. code-block:: c @@ -153,8 +153,8 @@ in ``include/nuttx/fs/fs.h`` and only listed here below: int file_vfcntl(FAR struct file *filep, int cmd, va_list ap); -The SYLOG Device: A Case Study -============================== +The SYSLOG Device: A Case Study +=============================== This technique is used for the SYSLOG device. Originally, NuttX used file descriptor ``1`` for SYSLOG output by default. For most task groups, @@ -179,7 +179,7 @@ Other Examples There are some other examples in analog joystick lower half drivers that use the ADC character driver to read joystick positions:: - boards/arm/stm32/nucleo-f4x1re/src/stm32_ajoystick.c: + boards/arm/stm32f4/nucleo-f411re/src/stm32_ajoystick.c: ret = file_detach(fd, &g_adcfile); boards/arm/stm32l4/nucleo-l476rg/src/stm32_ajoystick.c: diff --git a/Documentation/implementation/nuttx_initialization_sequence.rst b/Documentation/implementation/nuttx_initialization_sequence.rst index d3255a5e8ca5c..315010cc0894a 100644 --- a/Documentation/implementation/nuttx_initialization_sequence.rst +++ b/Documentation/implementation/nuttx_initialization_sequence.rst @@ -35,7 +35,7 @@ to any supported architecture. Here is the map of initialization function calls:: - __start()-arch/arm/src/stm32/stm32_start.c + __start()-arch/arm/src/common/stm32/stm32_start_m3m4_v1.c | +--*Set stack limit +--stm32_clockconfig() @@ -45,7 +45,7 @@ Here is the map of initialization function calls:: +--showprogress('A') +-- +-- - +--stm32_boardinitialize()-boards/arm/stm32/stm32f4discovery/src/stm32_boot.c + +--stm32_boardinitialize()-boards/arm/stm32f4/stm32f4discovery/src/stm32_boot.c | | | +--stm32_spidev_initialize()-stm32_spi.c:ONLY CHIP SELECTS | +--stm32_usbinitialize()- @@ -196,7 +196,7 @@ There are few important things to note about this file. ``.section .vectors, ax``. This pseudo operation will place all of the vectors into a special section call ``.vectors``. On of the STM32 F4 linker scripts is located at -``nuttx/boards/arm/stm32/stm32f4discovery/scripts/ld.script``. +``nuttx/boards/arm/stm32f4/stm32f4discovery/scripts/ld.script``. In that file, you can see that section ``.vectors`` is forced to lie at the very beginning of FLASH memory. The STM32 F4 can be configured to boot in different ways via strapping. @@ -229,7 +229,7 @@ nuttx/arch/arm/src/stm32_start.c ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ The reset vector ``__start`` lies in the file -``nuttx/arch/arm/src/stm32/stm32_start.c`` and does the real, +``nuttx/arch/arm/src/common/stm32/stm32_start_m3m4_v1.c`` and does the real, low-level architecture-specific initialization. This initialization includes: 1. ``stm32_clockconfig()`` - Initialize the PLLs and peripheral clocking @@ -262,7 +262,7 @@ low-level architecture-specific initialization. This initialization includes: 7. ``stm32_boardinitialize()`` - Board-specific logic is initialized by calling this function. For the case of the STM32F4Discovery board, this logic can be found at - ``nuttx/boards/arm/stm32/stm32f4discovery/src/stm32_boot.c`` and does + ``nuttx/boards/arm/stm32f4/stm32f4discovery/src/stm32_boot.c`` and does the following operations: a. ``stm32_spidev_initialize()`` - Initialize SPI chip selects @@ -351,19 +351,19 @@ file and in that case those operations are not performed: ``nx_start()``. However, if the board supports multiple, discontiguous memory regions, any addition memory regions can be added to the heap by this function. For the STM32 F4, ``up_addregion()`` is implemented - in ``nuttx/arch/arm/src/stm32/stm32_allocateheap.c``. + in ``nuttx/arch/arm/src/common/stm32/stm32_allocateheap_m3m4_v1.c``. * ``arm_pminitialize()`` - If ``CONFIG_PM`` is defined, the function must initialize the power management subsystem. This MCU-specific function - must be called very early in the intialization sequence before any other + must be called very early in the initialization sequence before any other device drivers are initialized (since they may attempt to register with the power management subsystem). There is no implementation of ``up_pminitialize()`` for any STM32 platform. * ``arm_dmainitialize()`` - Initialize the DMA subsystem. For the STM32 F4, this DMA initialization can be found in - ``nuttx/arch/arm/src/stm32/stm32_dma.c`` (which includes - ``nuttx/arch/arm/src/stm32f4xxx_dma.c``). + ``nuttx/arch/arm/src/common/stm32/stm32_dma_m3m4_v1_8ch.c`` (which includes + ``nuttx/arch/arm/src/common/stm32/stm32_dma_m3m4_v1_8ch.c``). * ``devnull_register()`` - Registers the standard ``/dev/null``. @@ -378,14 +378,14 @@ file and in that case those operations are not performed: * ``note_register()`` - Registers the standard ``/dev/note``. * ``arm_serialinit()`` - Initialize the **standard** serial driver - (found at ``nuttx/arch/arm/src/stm32/stm32_serial.c`` STM32 F4). + (found at ``nuttx/arch/arm/src/common/stm32/stm32_serial_m3m4_usart_v1v2v3v4.c`` STM32 F4). * ``arm_netinitialize()`` - Initialize the network. For the STM32 F4, - this function is in ``nuttx/arch/arm/src/stm32/stm32_eth.c``. + this function is in ``nuttx/arch/arm/src/common/stm32/stm32_eth_m3m4_v1.c``. * ``arm_usbinitialize()`` - Initialize USB (host or device). For the STM32 F4, this function is in - ``nuttx/arch/arm/src/stm32/stm32_otgfsdev.c``. + ``nuttx/arch/arm/src/common/stm32/stm32_otgfsdev_m3m4_v1.c``. * ``arm_l2ccinitialize()`` - Initialize the L2 cache if present and selected. @@ -448,7 +448,7 @@ This function performed the following specific operations: for a variety of purposes like misc garbage clean-up. * ``nx_create_initthread()`` - Once the operating system has been initialized, - this funcions either directly calls ``nx_start_application()`` or creates + this functions either directly calls ``nx_start_application()`` or creates a thread for running it * ``nx_start_application()`` - If set in the NuttX configuration, @@ -640,7 +640,7 @@ The resulting ROMFS file system can be found in * ``board_app_initialize()`` - For the STM32F4Discovery, this architecture specific initialization can be found at - ``boards/arm/stm32/stm32f4discovery/src/stm32_appinit.c``. + ``boards/arm/stm32f4/stm32f4discovery/src/stm32_appinit.c``. This it does things like: 1. Initialize SPI devices. diff --git a/Documentation/platforms/arm/stm32f1/boards/fire-stm32v2/index.rst b/Documentation/platforms/arm/stm32f1/boards/fire-stm32v2/index.rst index e82450a5e2f9e..9c15d336c5d1c 100644 --- a/Documentation/platforms/arm/stm32f1/boards/fire-stm32v2/index.rst +++ b/Documentation/platforms/arm/stm32f1/boards/fire-stm32v2/index.rst @@ -228,13 +228,13 @@ OpenOCD ======= I have also used OpenOCD with the M3 Wildfire. In this case, I used -the Olimex USB ARM OCD. See the script in boards/arm/stm32/fire-stm32v2/tools/oocd.sh +the Olimex USB ARM OCD. See the script in boards/arm/stm32f1/fire-stm32v2/tools/oocd.sh for more information. Using the script: - Start the OpenOCD GDB server:: cd - boards/arm/stm32/fire-stm32v2/tools/oocd.sh $PWD + boards/arm/stm32f1/fire-stm32v2/tools/oocd.sh $PWD - Load NuttX:: @@ -324,7 +324,7 @@ M3 Wildfire-specific Configuration Options CONFIG_ARCH_CHIP_name - For use in C code to identify the exact chip: - CONFIG_ARCH_CHIP_STM32 + CONFIG_ARCH_CHIP_STM32F1 CONFIG_ARCH_CHIP_STM32F103VE CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG - Enables special STM32 clock diff --git a/Documentation/platforms/arm/stm32f1/boards/shenzhou/index.rst b/Documentation/platforms/arm/stm32f1/boards/shenzhou/index.rst index d544bea76b21c..14f2d03a4cd87 100644 --- a/Documentation/platforms/arm/stm32f1/boards/shenzhou/index.rst +++ b/Documentation/platforms/arm/stm32f1/boards/shenzhou/index.rst @@ -517,7 +517,7 @@ NOTES: ADC_IN8 (PB0) CON5 CN14 Pin2 ADC_IN9 (PB1) CON5 CN14 Pin1 - The signal selection is hard-coded in boards/arm/stm32/shenzhou/src/up_adc.c: The + The signal selection is hard-coded in boards/arm/stm32f1/shenzhou/src/up_adc.c: The potentiometer input (only) is selected. These selections will enable sampling the potentiometer input at 100Hz using diff --git a/Documentation/platforms/arm/stm32f1/boards/stm3210e-eval/index.rst b/Documentation/platforms/arm/stm32f1/boards/stm3210e-eval/index.rst index fb218ff3c3b13..3e499fbfe9b2c 100644 --- a/Documentation/platforms/arm/stm32f1/boards/stm3210e-eval/index.rst +++ b/Documentation/platforms/arm/stm32f1/boards/stm3210e-eval/index.rst @@ -87,13 +87,13 @@ OpenOCD ======= I have also used OpenOCD with the STM3210E-EVAL. In this case, I used -the Olimex USB ARM OCD. See the script in boards/arm/stm32/stm3210e-eval/tools/oocd.sh +the Olimex USB ARM OCD. See the script in boards/arm/stm32f1/stm3210e-eval/tools/oocd.sh for more information. Using the script: - Start the OpenOCD GDB server:: cd - boards/arm/stm32/stm3210e-eval/tools/oocd.sh $PWD + boards/arm/stm32f1/stm3210e-eval/tools/oocd.sh $PWD - Load NuttX:: @@ -171,7 +171,7 @@ More complex temperature sensor operations are also available. See the IOCTL commands enumerated in include/nuttx/sensors/lm75.h. Also read the descriptions of the stm32_lm75initialize() and stm32_lm75attach() interfaces in the arch/board/board.h file (sames as -boards/arm/stm32/stm3210e-eval/include/board.h). +boards/arm/stm32f1/stm3210e-eval/include/board.h). NSH Command Line Application ---------------------------- @@ -812,7 +812,7 @@ NOTES: CONFIG_ARCH_CUSTOM_PMINIT=y CONFIG_ARCH_CUSTOM_PMINIT moves the PM initialization from - arch/arm/src/stm32/stm32_pminitialiaze.c to boards/arm/stm32/stm3210-eval/src/stm32_pm.c. + arch/arm/src/common/stm32/stm32_pminitialize_m3m4_v1.c to boards/arm/stm32f1/stm3210e-eval/src/stm32_pm.c. This allows us to support board-specific PM initialization.:: CONFIG_ARCH_IDLE_CUSTOM=y @@ -824,8 +824,8 @@ NOTES: management. The configuration CONFIG_ARCH_IDLE_CUSTOM allows us to "steal" the - normal STM32 IDLE loop (of arch/arm/src/stm32/stm32_idle.c) and replace - this with our own custom IDLE loop (at boards/arm/stm32/stm3210-eval/src/up_idle.c). + normal STM32 IDLE loop (of arch/arm/src/common/stm32/stm32_idle_m3m4_v1.c) and replace + this with our own custom IDLE loop (at boards/arm/stm32f1/stm3210e-eval/src/up_idle.c). 4. Here are some additional things to note in the configuration:: diff --git a/Documentation/platforms/arm/stm32f1/boards/stm32f103-minimum/index.rst b/Documentation/platforms/arm/stm32f1/boards/stm32f103-minimum/index.rst index 68819f0f60316..e818cabd22119 100644 --- a/Documentation/platforms/arm/stm32f1/boards/stm32f103-minimum/index.rst +++ b/Documentation/platforms/arm/stm32f1/boards/stm32f103-minimum/index.rst @@ -186,7 +186,7 @@ instead of 64KiB as documented in the datasheet and reported by its internal register. In order to enable 128KiB you need modify the linker script to reflect this -new size. Open the boards/arm/stm32/stm32f103-minimum/scripts/ld.script and replace:: +new size. Open the boards/arm/stm32f1/stm32f103-minimum/scripts/ld.script and replace:: flash (rx) : ORIGIN = 0x08000000, LENGTH = 64K @@ -358,7 +358,7 @@ enable/disable these options using "make menuconfig" :: Memory Management ---> [*] Small memory model - Also change the boards/arm/stm32/stm32f103-minimum/scripts/ld.script file to use 128KB + Also change the boards/arm/stm32f1/stm32f103-minimum/scripts/ld.script file to use 128KB of Flash instead 64KB (since this board has a hidden 64KB flash) : MEMORY diff --git a/Documentation/platforms/arm/stm32f1/boards/stm32vldiscovery/index.rst b/Documentation/platforms/arm/stm32f1/boards/stm32vldiscovery/index.rst index 8e76e5abc8c3a..81c6d7b82893a 100644 --- a/Documentation/platforms/arm/stm32f1/boards/stm32vldiscovery/index.rst +++ b/Documentation/platforms/arm/stm32f1/boards/stm32vldiscovery/index.rst @@ -12,7 +12,7 @@ LEDs It is assumed that STMicro STM32F100RB generic board board has one LED on PA0. You should configure the port and pin number in -boards/arm/stm32/stm32vldiscovery/src/stm32vldiscovery.h. This LED is not used by +boards/arm/stm32f1/stm32vldiscovery/src/stm32vldiscovery.h. This LED is not used by the board port unless CONFIG_ARCH_LEDS is defined. In that case, the usage by the board port is defined in include/board.h and src/up_leds.c. The LED is used to encode OS-related events as follows:: diff --git a/Documentation/platforms/arm/stm32f4/boards/clicker2-stm32/index.rst b/Documentation/platforms/arm/stm32f4/boards/clicker2-stm32/index.rst index 40be36a057637..b2584194578dd 100644 --- a/Documentation/platforms/arm/stm32f4/boards/clicker2-stm32/index.rst +++ b/Documentation/platforms/arm/stm32f4/boards/clicker2-stm32/index.rst @@ -79,7 +79,7 @@ Using JTAG The Clicker2 comes with the mikroBootloader installed. That bootloader has not been used and is possibly incompatible with the Clicker2-STM32 -linker script at boards/arm/stm32/clicker2-stm32/scripts/flash.ld. Often code must +linker script at boards/arm/stm32f4/clicker2-stm32/scripts/flash.ld. Often code must be built to execute at an offset in to FLASH when a bootloader is used. Certainly that is the case for the ST-Micro DFU bootloader but I am not aware of the requirements for use with the mikroBootloader. diff --git a/Documentation/platforms/arm/stm32f4/boards/omnibusf4/index.rst b/Documentation/platforms/arm/stm32f4/boards/omnibusf4/index.rst index 7021a333f0edc..e81cd71ba97bc 100644 --- a/Documentation/platforms/arm/stm32f4/boards/omnibusf4/index.rst +++ b/Documentation/platforms/arm/stm32f4/boards/omnibusf4/index.rst @@ -79,6 +79,6 @@ package as flexible as, say, an STM32F4 Discovery board. Build Instructions ================== -The boards/arm/stm32/omnibusf4/nsh/defconfig file creates a basic setup, and +The boards/arm/stm32f4/omnibusf4/nsh/defconfig file creates a basic setup, and includes drivers for all supported onboard chips. The console and command prompt are sent to USART3. diff --git a/Documentation/platforms/arm/stm32f4/boards/stm32f4discovery/index.rst b/Documentation/platforms/arm/stm32f4/boards/stm32f4discovery/index.rst index 65a7eaf78317a..ea78006fcfde1 100644 --- a/Documentation/platforms/arm/stm32f4/boards/stm32f4discovery/index.rst +++ b/Documentation/platforms/arm/stm32f4/boards/stm32f4discovery/index.rst @@ -517,7 +517,7 @@ MAPPING TO STM32 F4:: 4 Also the reset pin for the CS43L22 audio Codec. NOTE: The configuration to test this LCD configuration is available at -boards/arm/stm32/stm32f4discovery/nxlines. As of this writing, I have not seen the +boards/arm/stm32f4/stm32f4discovery/nxlines. As of this writing, I have not seen the LCD working so I probably have some things wrong. I might need to use a bit-banging interface. Below is the pin configuration @@ -613,7 +613,7 @@ that I am using:: Darcy Gong recently added support for the UG-2864HSWEG01 OLED which is also an option with this configuration. I have little technical information about -the UG-2864HSWEG01 interface (see boards/arm/stm32/stm32f4discovery/src/up_ug2864hsweg01.c). +the UG-2864HSWEG01 interface (see boards/arm/stm32f4/stm32f4discovery/src/up_ug2864hsweg01.c). NiceRF LoRa (2AD66-LoRa V2) =========================== @@ -639,7 +639,7 @@ connect the CS to PA4, connect RST to PE1 and finally connect INT to PE4. The next step is to enable the ENC28J60 in the menuconfig ("make menuconfig") and the necessary Network configuration, you can use the -boards/arm/stm32/fire-stm32v2/configs/nsh/defconfig as reference. +boards/arm/stm32f1/fire-stm32v2/configs/nsh/defconfig as reference. HCI UART ======== @@ -1202,7 +1202,7 @@ NOTES: The HCI UART selection can be changed by re-configuring and assigning the different U[S]ART to the HCI. The U[S]ART pin selections can be changed by modifying the disambiguation definitions in -boards/arm/stm32/stm32f4discovery/include/board.h +boards/arm/stm32f4/stm32f4discovery/include/board.h I have been testing with the DVK_BT960_SA board via J10 as follows:: @@ -2021,7 +2021,7 @@ NOTES: CONFIG_ARCH_CUSTOM_PMINIT=y CONFIG_ARCH_CUSTOM_PMINIT moves the PM initialization from - arch/arm/src/stm32/stm32_pminitialiaze.c to boards/arm/stm32/stm3210-eval/src/stm32_pm.c. + arch/arm/src/common/stm32/stm32_pminitialize_m3m4_v1.c to boards/arm/stm32f1/stm3210e-eval/src/stm32_pm.c. This allows us to support board-specific PM initialization.:: CONFIG_ARCH_IDLE_CUSTOM=y @@ -2033,8 +2033,8 @@ NOTES: management. The configuration CONFIG_ARCH_IDLE_CUSTOM allows us to "steal" the - normal STM32 IDLE loop (of arch/arm/src/stm32/stm32_idle.c) and replace - this with our own custom IDLE loop (at boards/arm/stm32/stm3210-eval/src/up_idle.c). + normal STM32 IDLE loop (of arch/arm/src/common/stm32/stm32_idle_m3m4_v1.c) and replace + this with our own custom IDLE loop (at boards/arm/stm32f1/stm3210e-eval/src/up_idle.c). 3. Here are some additional things to note in the configuration:: diff --git a/Documentation/platforms/arm/stm32f4/index.rst b/Documentation/platforms/arm/stm32f4/index.rst index 3684b7dd5a012..474dae92be608 100644 --- a/Documentation/platforms/arm/stm32f4/index.rst +++ b/Documentation/platforms/arm/stm32f4/index.rst @@ -389,7 +389,7 @@ Here are a few tips before you start that effort: on the command line. Startup files will probably cause you some headaches. The NuttX startup file -is arch/arm/src/stm32/stm32_vectors.S. With RIDE, I have to build NuttX +is arch/arm/src/stm32f4/gnu/stm32_vectors.S. With RIDE, I have to build NuttX one time from the Cygwin command line in order to obtain the pre-built startup object needed by RIDE. diff --git a/Documentation/platforms/arm/stm32f7/boards/nucleo-f722ze/index.rst b/Documentation/platforms/arm/stm32f7/boards/nucleo-f722ze/index.rst index 7beb7bb52a087..0243fbc5dec89 100644 --- a/Documentation/platforms/arm/stm32f7/boards/nucleo-f722ze/index.rst +++ b/Documentation/platforms/arm/stm32f7/boards/nucleo-f722ze/index.rst @@ -177,7 +177,7 @@ You must use a 3.3 TTL to RS-232 converter or a USB to 3.3V TTL Use make menuconfig to configure USART6 as the console:: - CONFIG_STM32F7_USART6=y + CONFIG_STM32_USART6=y CONFIG_USARTs_SERIALDRIVER=y CONFIG_USARTS_SERIAL_CONSOLE=y CONFIG_USART6_RXBUFSIZE=256 @@ -213,7 +213,7 @@ You must use a 3.3 TTL to RS-232 converter or a USB to 3.3V TTL:: Use make menuconfig to configure USART8 as the console:: - CONFIG_STM32F7_UART8=y + CONFIG_STM32_UART8=y CONFIG_UART8_SERIALDRIVER=y CONFIG_UART8_SERIAL_CONSOLE=y CONFIG_UART8_RXBUFSIZE=256 diff --git a/Documentation/platforms/arm/stm32f7/boards/nucleo-f746zg/index.rst b/Documentation/platforms/arm/stm32f7/boards/nucleo-f746zg/index.rst index f9ce45c6e3b74..f010732432a12 100644 --- a/Documentation/platforms/arm/stm32f7/boards/nucleo-f746zg/index.rst +++ b/Documentation/platforms/arm/stm32f7/boards/nucleo-f746zg/index.rst @@ -219,7 +219,7 @@ You must use a 3.3 TTL to RS-232 converter or a USB to 3.3V TTL Use make menuconfig to configure USART6 as the console:: - CONFIG_STM32F7_USART6=y + CONFIG_STM32_USART6=y CONFIG_USARTs_SERIALDRIVER=y CONFIG_USARTS_SERIAL_CONSOLE=y CONFIG_USART6_RXBUFSIZE=256 @@ -255,7 +255,7 @@ You must use a 3.3 TTL to RS-232 converter or a USB to 3.3V TTL:: Use make menuconfig to configure USART8 as the console:: - CONFIG_STM32F7_UART8=y + CONFIG_STM32_UART8=y CONFIG_UART8_SERIALDRIVER=y CONFIG_UART8_SERIAL_CONSOLE=y CONFIG_UART8_RXBUFSIZE=256 diff --git a/Documentation/platforms/arm/stm32f7/boards/nucleo-f767zi/index.rst b/Documentation/platforms/arm/stm32f7/boards/nucleo-f767zi/index.rst index ef64085ad76b3..addc01caee40b 100644 --- a/Documentation/platforms/arm/stm32f7/boards/nucleo-f767zi/index.rst +++ b/Documentation/platforms/arm/stm32f7/boards/nucleo-f767zi/index.rst @@ -221,7 +221,7 @@ You must use a 3.3 TTL to RS-232 converter or a USB to 3.3V TTL Use make menuconfig to configure USART6 as the console:: - CONFIG_STM32F7_USART6=y + CONFIG_STM32_USART6=y CONFIG_USARTs_SERIALDRIVER=y CONFIG_USARTS_SERIAL_CONSOLE=y CONFIG_USART6_RXBUFSIZE=256 @@ -257,7 +257,7 @@ You must use a 3.3 TTL to RS-232 converter or a USB to 3.3V TTL:: Use make menuconfig to configure USART8 as the console:: - CONFIG_STM32F7_UART8=y + CONFIG_STM32_UART8=y CONFIG_UART8_SERIALDRIVER=y CONFIG_UART8_SERIAL_CONSOLE=y CONFIG_UART8_RXBUFSIZE=256 diff --git a/Documentation/platforms/arm/stm32f7/boards/stm32f769i-disco/index.rst b/Documentation/platforms/arm/stm32f7/boards/stm32f769i-disco/index.rst index d510c3e498131..dbe20d4247b5f 100644 --- a/Documentation/platforms/arm/stm32f7/boards/stm32f769i-disco/index.rst +++ b/Documentation/platforms/arm/stm32f7/boards/stm32f769i-disco/index.rst @@ -129,9 +129,9 @@ configuration no builtin applications are selected. And these for enabling the STM32 timer PWM channel: - CONFIG_STM32F7_TIM1=y - CONFIG_STM32F7_TIM1_PWM=y - CONFIG_STM32F7_TIM1_CHANNEL=4 + CONFIG_STM32_TIM1=y + CONFIG_STM32_TIM1_PWM=y + CONFIG_STM32_TIM1_CHANNEL=4 nsh-ehternet ------------ diff --git a/Documentation/platforms/arm/stm32f7/index.rst b/Documentation/platforms/arm/stm32f7/index.rst index 5669353e6a07f..6f525e8e2fe6b 100644 --- a/Documentation/platforms/arm/stm32f7/index.rst +++ b/Documentation/platforms/arm/stm32f7/index.rst @@ -106,7 +106,7 @@ managed with dtcm_malloc(), dtcm_free(), etc. In order to use FMC SRAM, the following additional things need to be present in the NuttX configuration file: -- CONFIG_STM32F7_FMC_SRAM - Indicates that SRAM is available via the +- CONFIG_STM32_FMC_SRAM - Indicates that SRAM is available via the FMC (as opposed to an LCD or FLASH). - CONFIG_HEAP2_BASE - The base address of the SRAM in the FMC address space (hex) @@ -123,10 +123,10 @@ present in the NuttX configuration file: Clock ----- -- CONFIG_ARCH_BOARD_STM32F7_CUSTOM_CLOCKCONFIG - Enables special STM32F7 clock +- CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG - Enables special STM32 clock configuration features.:: - CONFIG_ARCH_BOARD_STM32F7_CUSTOM_CLOCKCONFIG=n + CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG=n - CONFIG_ARCH_LOOPSPERMSEC - Must be calibrated for correct operation of delay loops @@ -134,23 +134,23 @@ Timers ------ Timer devices may be used for different purposes. One special purpose is -to generate modulated outputs for such things as motor control. If CONFIG_STM32F7_TIMn +to generate modulated outputs for such things as motor control. If CONFIG_STM32_TIMn is defined (as above) then the following may also be defined to indicate that the timer is intended to be used for pulsed output modulation, ADC conversion, or DAC conversion. Note that ADC/DAC require two definition: Not only do you have to assign the timer (n) for used by the ADC or DAC, but then you also have to configure which ADC or DAC (m) it is assigned to.: -- CONFIG_STM32F7_TIMn_PWM Reserve timer n for use by PWM, n=1,..,14 -- CONFIG_STM32F7_TIMn_ADC Reserve timer n for use by ADC, n=1,..,14 -- CONFIG_STM32F7_TIMn_ADCm Reserve timer n to trigger ADCm, n=1,..,14, m=1,..,3 -- CONFIG_STM32F7_TIMn_DAC Reserve timer n for use by DAC, n=1,..,14 -- CONFIG_STM32F7_TIMn_DACm Reserve timer n to trigger DACm, n=1,..,14, m=1,..,2 +- CONFIG_STM32_TIMn_PWM Reserve timer n for use by PWM, n=1,..,14 +- CONFIG_STM32_TIMn_ADC Reserve timer n for use by ADC, n=1,..,14 +- CONFIG_STM32_TIMn_ADCm Reserve timer n to trigger ADCm, n=1,..,14, m=1,..,3 +- CONFIG_STM32_TIMn_DAC Reserve timer n for use by DAC, n=1,..,14 +- CONFIG_STM32_TIMn_DACm Reserve timer n to trigger DACm, n=1,..,14, m=1,..,2 For each timer that is enabled for PWM usage, we need the following additional configuration settings: -- CONFIG_STM32F7_TIMx_CHANNEL - Specifies the timer output channel {1,..,4} +- CONFIG_STM32_TIMx_CHANNEL - Specifies the timer output channel {1,..,4} NOTE: The STM32 timers are each capable of generating different signals on each of the four channels with different duty cycles. That capability is @@ -206,11 +206,11 @@ CAN - CONFIG_STM32F7F7_CAN2_BAUD - CAN1 BAUD rate. Required if CONFIG_STM32F7F7_CAN2 is defined. -- CONFIG_STM32F7_CAN_TSEG1 - The number of CAN time quanta in segment 1. Default: 6 +- CONFIG_STM32_CAN_TSEG1 - The number of CAN time quanta in segment 1. Default: 6 -- CONFIG_STM32F7_CAN_TSEG2 - the number of CAN time quanta in segment 2. Default: 7 +- CONFIG_STM32_CAN_TSEG2 - the number of CAN time quanta in segment 2. Default: 7 -- CONFIG_STM32F7_CAN_REGDEBUG - If CONFIG_DEBUG_FEATURES is set, this will generate an +- CONFIG_STM32_CAN_REGDEBUG - If CONFIG_DEBUG_FEATURES is set, this will generate an dump of all CAN registers. CAN SocketCAN @@ -221,12 +221,12 @@ TODO SPI --- -- CONFIG_STM32F7_SPI_INTERRUPTS - Select to enable interrupt driven SPI +- CONFIG_STM32_SPI_INTERRUPTS - Select to enable interrupt driven SPI support. Non-interrupt-driven, poll-waiting is recommended if the interrupt rate would be to high in the interrupt driven case. -- CONFIG_STM32F7_SPIx_DMA - Use DMA to improve SPIx transfer performance. - Cannot be used with CONFIG_STM32F7_SPI_INTERRUPT. +- CONFIG_STM32_SPIx_DMA - Use DMA to improve SPIx transfer performance. + Cannot be used with CONFIG_STM32_SPI_INTERRUPT. SDIO ---- @@ -238,41 +238,41 @@ ETH Options: -- CONFIG_STM32F7_PHYADDR - The 5-bit address of the PHY on the board +- CONFIG_STM32_PHYADDR - The 5-bit address of the PHY on the board -- CONFIG_STM32F7_MII - Support Ethernet MII interface +- CONFIG_STM32_MII - Support Ethernet MII interface -- CONFIG_STM32F7_MII_MCO1 - Use MCO1 to clock the MII interface +- CONFIG_STM32_MII_MCO1 - Use MCO1 to clock the MII interface -- CONFIG_STM32F7_MII_MCO2 - Use MCO2 to clock the MII interface +- CONFIG_STM32_MII_MCO2 - Use MCO2 to clock the MII interface -- CONFIG_STM32F7_RMII - Support Ethernet RMII interface +- CONFIG_STM32_RMII - Support Ethernet RMII interface -- CONFIG_STM32F7_AUTONEG - Use PHY autonegotiation to determine speed and mode +- CONFIG_STM32_AUTONEG - Use PHY autonegotiation to determine speed and mode -- CONFIG_STM32F7_ETHFD - If CONFIG_STM32F7_AUTONEG is not defined, then this +- CONFIG_STM32_ETHFD - If CONFIG_STM32_AUTONEG is not defined, then this may be defined to select full duplex mode. Default: half-duplex -- CONFIG_STM32F7_ETH100MBPS - If CONFIG_STM32F7_AUTONEG is not defined, then this +- CONFIG_STM32_ETH100MBPS - If CONFIG_STM32_AUTONEG is not defined, then this may be defined to select 100 MBps speed. Default: 10 Mbps -- CONFIG_STM32F7_PHYSR - This must be provided if CONFIG_STM32F7_AUTONEG is +- CONFIG_STM32_PHYSR - This must be provided if CONFIG_STM32_AUTONEG is defined. The PHY status register address may diff from PHY to PHY. This configuration sets the address of the PHY status register. -- CONFIG_STM32F7_PHYSR_SPEED - This must be provided if CONFIG_STM32F7_AUTONEG is +- CONFIG_STM32_PHYSR_SPEED - This must be provided if CONFIG_STM32_AUTONEG is defined. This provides bit mask indicating 10 or 100MBps speed. -- CONFIG_STM32F7_PHYSR_100MBPS - This must be provided if CONFIG_STM32F7_AUTONEG is +- CONFIG_STM32_PHYSR_100MBPS - This must be provided if CONFIG_STM32_AUTONEG is defined. This provides the value of the speed bit(s) indicating 100MBps speed. -- CONFIG_STM32F7_PHYSR_MODE - This must be provided if CONFIG_STM32F7_AUTONEG is +- CONFIG_STM32_PHYSR_MODE - This must be provided if CONFIG_STM32_AUTONEG is defined. This provide bit mask indicating full or half duplex modes. -- CONFIG_STM32F7_PHYSR_FULLDUPLEX - This must be provided if CONFIG_STM32F7_AUTONEG is +- CONFIG_STM32_PHYSR_FULLDUPLEX - This must be provided if CONFIG_STM32_AUTONEG is defined. This provides the value of the mode bits indicating full duplex mode. -- CONFIG_STM32F7_ETH_PTP - Precision Time Protocol (PTP). Not supported +- CONFIG_STM32_ETH_PTP - Precision Time Protocol (PTP). Not supported but some hooks are indicated with this condition. USB OTG FS @@ -284,30 +284,30 @@ Pre-requisites: - CONFIG_USBDEV - Enable USB device support - CONFIG_USBHOST - Enable USB host support -- CONFIG_STM32F7_OTGFS - Enable the STM32 USB OTG FS block -- CONFIG_STM32F7_SYSCFG - Needed +- CONFIG_STM32_OTGFS - Enable the STM32 USB OTG FS block +- CONFIG_STM32_SYSCFG - Needed - CONFIG_SCHED_WORKQUEUE - Worker thread support is required Options: -- CONFIG_STM32F7_OTGFS_RXFIFO_SIZE - Size of the RX FIFO in 32-bit words. +- CONFIG_STM32_OTGFS_RXFIFO_SIZE - Size of the RX FIFO in 32-bit words. Default 128 (512 bytes) -- CONFIG_STM32F7_OTGFS_NPTXFIFO_SIZE - Size of the non-periodic Tx FIFO +- CONFIG_STM32_OTGFS_NPTXFIFO_SIZE - Size of the non-periodic Tx FIFO in 32-bit words. Default 96 (384 bytes) -- CONFIG_STM32F7_OTGFS_PTXFIFO_SIZE - Size of the periodic Tx FIFO in 32-bit +- CONFIG_STM32_OTGFS_PTXFIFO_SIZE - Size of the periodic Tx FIFO in 32-bit words. Default 96 (384 bytes) -- CONFIG_STM32F7_OTGFS_DESCSIZE - Maximum size of a descriptor. Default: 128 +- CONFIG_STM32_OTGFS_DESCSIZE - Maximum size of a descriptor. Default: 128 -- CONFIG_STM32F7_OTGFS_SOFINTR - Enable SOF interrupts. Why would you ever +- CONFIG_STM32_OTGFS_SOFINTR - Enable SOF interrupts. Why would you ever want to do that? -- CONFIG_STM32F7_USBHOST_REGDEBUG - Enable very low-level register access +- CONFIG_STM32_USBHOST_REGDEBUG - Enable very low-level register access debug. Depends on CONFIG_DEBUG_FEATURES. -- CONFIG_STM32F7_USBHOST_PKTDUMP - Dump all incoming and outgoing USB +- CONFIG_STM32_USBHOST_PKTDUMP - Dump all incoming and outgoing USB packets. Depends on CONFIG_DEBUG_FEATURES. USB OTG HS @@ -353,16 +353,16 @@ Available for some Nucleo boards. The builtin SPI test facility can be enabled with the following settings:: - +CONFIG_STM32F7_SPI=y - +CONFIG_STM32F7_SPI1=y - +CONFIG_STM32F7_SPI2=y - +CONFIG_STM32F7_SPI3=y + +CONFIG_STM32_SPI=y + +CONFIG_STM32_SPI1=y + +CONFIG_STM32_SPI2=y + +CONFIG_STM32_SPI3=y - +# CONFIG_STM32F7_SPI_INTERRUPTS is not set - +# CONFIG_STM32F7_SPI1_DMA is not set - +# CONFIG_STM32F7_SPI2_DMA is not set - +# CONFIG_STM32F7_SPI3_DMA is not set - # CONFIG_STM32F7_CUSTOM_CLOCKCONFIG is not set + +# CONFIG_STM32_SPI_INTERRUPTS is not set + +# CONFIG_STM32_SPI1_DMA is not set + +# CONFIG_STM32_SPI2_DMA is not set + +# CONFIG_STM32_SPI3_DMA is not set + # CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is not set +CONFIG_NUCLEO_SPI_TEST=y +CONFIG_NUCLEO_SPI_TEST_MESSAGE="Hello World" diff --git a/Documentation/platforms/arm/stm32h5/boards/nucleo-h563zi/index.rst b/Documentation/platforms/arm/stm32h5/boards/nucleo-h563zi/index.rst index b6e324ef32c91..0ff9e56e127b3 100644 --- a/Documentation/platforms/arm/stm32h5/boards/nucleo-h563zi/index.rst +++ b/Documentation/platforms/arm/stm32h5/boards/nucleo-h563zi/index.rst @@ -182,7 +182,7 @@ This configuration enables USB Host support with the Mass Storage Class USB mass-storage device (e.g. a USB flash drive) to the board's USB-C connector. Key options enabled: -- ``CONFIG_STM32H5_USBFS_HOST`` — STM32H5 USB full-speed host controller +- ``CONFIG_STM32_USBFS_HOST`` — STM32H5 USB full-speed host controller - ``CONFIG_USBHOST_MSC`` — USB Mass Storage Class host driver - ``CONFIG_USBHOST_HUB`` — USB hub support - ``CONFIG_FS_FAT`` — FAT filesystem for mounting the storage device @@ -196,7 +196,7 @@ configured in this build. USB Host requires a stable 48 MHz clock. HSI48 is not accurate enough for reliable USB operation, so this configuration uses the external high-speed oscillator (HSE) as the USB clock source - (``CONFIG_STM32H5_USE_HSE=y``). On the Nucleo-H563ZI development board + (``CONFIG_STM32_USE_HSE=y``). On the Nucleo-H563ZI development board HSE is not connected by default; to enable it you must: - **Connect** solder bridges **SB3** and **SB4** @@ -214,7 +214,7 @@ full networking support and the CDC-ECM USB Ethernet host driver. It is intended to test USB Host operation with a USB-to-Ethernet adapter that uses the CDC-ECM (Ethernet Control Model) protocol. Key options enabled: -- ``CONFIG_STM32H5_USBFS_HOST`` — STM32H5 USB full-speed host controller +- ``CONFIG_STM32_USBFS_HOST`` — STM32H5 USB full-speed host controller - ``CONFIG_USBHOST_CDCECM`` — USB CDC-ECM Ethernet host driver - ``CONFIG_USBHOST_COMPOSITE`` — composite USB device support - ``CONFIG_USBHOST_HUB`` — USB hub support @@ -233,7 +233,7 @@ verify network connectivity. USB Host requires a stable 48 MHz clock. HSI48 is not accurate enough for reliable USB operation, so this configuration uses the external high-speed oscillator (HSE) as the USB clock source - (``CONFIG_STM32H5_USE_HSE=y``). On the Nucleo-H563ZI development board + (``CONFIG_STM32_USE_HSE=y``). On the Nucleo-H563ZI development board HSE is not connected by default; to enable it you must: - **Connect** solder bridges **SB3** and **SB4** diff --git a/Documentation/platforms/arm/stm32h5/index.rst b/Documentation/platforms/arm/stm32h5/index.rst index 882a75ea5e4d7..fb49d8558da88 100644 --- a/Documentation/platforms/arm/stm32h5/index.rst +++ b/Documentation/platforms/arm/stm32h5/index.rst @@ -95,7 +95,7 @@ capable of operating as a device or host. Pre-requisites: - CONFIG_USBHOST - Enable USB host support -- CONFIG_STM32H5_USBFS_HOST - Enable the STM32 USB OTG FS block in host mode +- CONFIG_STM32_USBFS_HOST - Enable the STM32 USB OTG FS block in host mode USB host requires a stable 48MHz clock. This should come from a PLL driven by the HSE. HSI48 cannot be reliably used in host mode due to drift. It can only be used in device mode. diff --git a/Documentation/platforms/arm/stm32h7/boards/linum-stm32h753bi/index.rst b/Documentation/platforms/arm/stm32h7/boards/linum-stm32h753bi/index.rst index bcba3e81df6da..0adfaf5562541 100644 --- a/Documentation/platforms/arm/stm32h7/boards/linum-stm32h753bi/index.rst +++ b/Documentation/platforms/arm/stm32h7/boards/linum-stm32h753bi/index.rst @@ -721,7 +721,7 @@ After that check if your PC recognized the usb driver:: [27221.266103] sd 0:0:0:0: [sda] Attached SCSI removable disk [27228.147377] FAT-fs (sda1): Volume was not properly unmounted. Some data may be corrupt. Please run fsck. -**OBS:** This example disable the macro CONFIG_STM32H7_SDMMC_IDMA, for more information read the file: arch/arm/stm32h7/stm32_sdmmc.c +**OBS:** This example disable the macro CONFIG_STM32_SDMMC_IDMA, for more information read the file: arch/arm/stm32h7/stm32_sdmmc.c netnsh ------ diff --git a/Documentation/platforms/arm/stm32h7/index.rst b/Documentation/platforms/arm/stm32h7/index.rst index b042e33c30ce5..61e1f4387be2a 100644 --- a/Documentation/platforms/arm/stm32h7/index.rst +++ b/Documentation/platforms/arm/stm32h7/index.rst @@ -114,7 +114,7 @@ The selection of the core for which the image is build is made using options: - ``CONFIG_ARCH_CHIP_STM32H7_CORTEXM4`` - selects Cortex-M4 core Support for the CM7 core is always enabled, support for the CM4 core is controlled -with the ``CONFIG_STM32H7_CORTEXM4_ENABLED`` option. +with the ``CONFIG_STM32_CORTEXM4_ENABLED`` option. Interprocessor communication between cores is realized with the NuttX RPTUN device based on the OpenAMP framework. ``HSEM`` is used for synchronization and diff --git a/Documentation/platforms/arm/stm32l4/boards/nucleo-l432kc/index.rst b/Documentation/platforms/arm/stm32l4/boards/nucleo-l432kc/index.rst index 578ca414e579b..0c691673f2abe 100644 --- a/Documentation/platforms/arm/stm32l4/boards/nucleo-l432kc/index.rst +++ b/Documentation/platforms/arm/stm32l4/boards/nucleo-l432kc/index.rst @@ -106,7 +106,7 @@ Here are a few tips before you start that effort: on the command line. Startup files will probably cause you some headaches. The NuttX startup file -is arch/arm/src/stm32/stm32_vectors.S. With RIDE, I have to build NuttX +is arch/arm/src/stm32f4/gnu/stm32_vectors.S. With RIDE, I have to build NuttX one time from the Cygwin command line in order to obtain the pre-built startup object needed by RIDE. diff --git a/Documentation/platforms/arm/stm32l4/boards/nucleo-l476rg/index.rst b/Documentation/platforms/arm/stm32l4/boards/nucleo-l476rg/index.rst index 17cb93b0dcc15..914494906fa04 100644 --- a/Documentation/platforms/arm/stm32l4/boards/nucleo-l476rg/index.rst +++ b/Documentation/platforms/arm/stm32l4/boards/nucleo-l476rg/index.rst @@ -107,7 +107,7 @@ Here are a few tips before you start that effort: on the command line. Startup files will probably cause you some headaches. The NuttX startup file -is arch/arm/src/stm32/stm32_vectors.S. With RIDE, I have to build NuttX +is arch/arm/src/stm32f4/gnu/stm32_vectors.S. With RIDE, I have to build NuttX one time from the Cygwin command line in order to obtain the pre-built startup object needed by RIDE. diff --git a/Documentation/platforms/arm/stm32l4/boards/nucleo-l496zg/index.rst b/Documentation/platforms/arm/stm32l4/boards/nucleo-l496zg/index.rst index 0080c9db8d29e..89df8dc28f4f3 100644 --- a/Documentation/platforms/arm/stm32l4/boards/nucleo-l496zg/index.rst +++ b/Documentation/platforms/arm/stm32l4/boards/nucleo-l496zg/index.rst @@ -153,7 +153,7 @@ You must use a 3.3 TTL to RS-232 converter or a USB to 3.3V TTL:: Use make menuconfig to configure USART3 as the console:: - CONFIG_STM32L4_USART3=y + CONFIG_STM32_USART3=y CONFIG_USART3_SERIALDRIVER=y CONFIG_USART3_SERIAL_CONSOLE=y CONFIG_USART3_RXBUFSIZE=256 diff --git a/Documentation/platforms/arm/stm32l4/boards/stm32l476vg-disco/index.rst b/Documentation/platforms/arm/stm32l4/boards/stm32l476vg-disco/index.rst index f3eb6fc33a360..c1d763f67d797 100644 --- a/Documentation/platforms/arm/stm32l4/boards/stm32l476vg-disco/index.rst +++ b/Documentation/platforms/arm/stm32l4/boards/stm32l476vg-disco/index.rst @@ -468,7 +468,7 @@ NOTES: not enabled in the default configuration but can be enabled with the following settings:: - CONFIG_STM32L4_OTGFS=y + CONFIG_STM32_OTGFS=y CONFIG_USBDEV=y CONFIG_USBDEV_SELFPOWERED=y diff --git a/Documentation/platforms/arm/stm32l4/boards/stm32l4r9ai-disco/index.rst b/Documentation/platforms/arm/stm32l4/boards/stm32l4r9ai-disco/index.rst index ddec498f57da6..b87198bfdd5a1 100644 --- a/Documentation/platforms/arm/stm32l4/boards/stm32l4r9ai-disco/index.rst +++ b/Documentation/platforms/arm/stm32l4/boards/stm32l4r9ai-disco/index.rst @@ -130,7 +130,7 @@ Pins and Connectors:: To configure USART1 as the console:: - CONFIG_STM32L4_USART1=y + CONFIG_STM32_USART1=y CONFIG_USART1_SERIALDRIVER=y CONFIG_USART1_SERIAL_CONSOLE=y CONFIG_USART1_RXBUFSIZE=256 @@ -172,7 +172,7 @@ Pins and Connectors:: To configure USART2 as the console:: - CONFIG_STM32L4_USART2=y + CONFIG_STM32_USART2=y CONFIG_USART2_SERIALDRIVER=y CONFIG_USART2_SERIAL_CONSOLE=y CONFIG_USART2_RXBUFSIZE=256 @@ -192,7 +192,7 @@ Pins and Connectors:: To configure USART4 as the console:: - CONFIG_STM32L4_UART4=y + CONFIG_STM32_UART4=y CONFIG_USART4_SERIALDRIVER=y CONFIG_USART4_SERIAL_CONSOLE=y CONFIG_USART4_RXBUFSIZE=512 @@ -357,7 +357,7 @@ NOTES: not enabled in the default configuration but can be enabled with the following settings: (TODO: need to test!):: - CONFIG_STM32L4_OTGFS=y + CONFIG_STM32_OTGFS=y CONFIG_USBDEV=y CONFIG_USBDEV_SELFPOWERED=y diff --git a/Documentation/platforms/arm/stm32l4/index.rst b/Documentation/platforms/arm/stm32l4/index.rst index 6be0b2f932cc8..2e8e1080c39dd 100644 --- a/Documentation/platforms/arm/stm32l4/index.rst +++ b/Documentation/platforms/arm/stm32l4/index.rst @@ -28,9 +28,9 @@ STM32L4X6 Yes RM0351 STM32L4XR Yes RM0432 (STM32L4+) ============ ======= ====== ================================ -[1]: Please avoid depending on CONFIG_STM32L4_STM32L4X1 and -CONFIG_STM32L4_STM32L4X2 as the MCUs are of the same subfamily -as CONFIG_STM32L4_STM32L4X3. +[1]: Please avoid depending on CONFIG_STM32_STM32L4X1 and +CONFIG_STM32_STM32L4X2 as the MCUs are of the same subfamily +as CONFIG_STM32_STM32L4X3. Peripheral Support ================== diff --git a/Documentation/platforms/arm/stm32l5/boards/nucleo-l552ze/index.rst b/Documentation/platforms/arm/stm32l5/boards/nucleo-l552ze/index.rst index fcc67d7977d2c..663867803175e 100644 --- a/Documentation/platforms/arm/stm32l5/boards/nucleo-l552ze/index.rst +++ b/Documentation/platforms/arm/stm32l5/boards/nucleo-l552ze/index.rst @@ -104,7 +104,7 @@ You must use a 3.3 TTL to RS-232 converter or a USB to 3.3V TTL Use make menuconfig to configure USART3 as the console:: - CONFIG_STM32L5_USART3=y + CONFIG_STM32_USART3=y CONFIG_USART3_SERIALDRIVER=y CONFIG_USART3_SERIAL_CONSOLE=y CONFIG_USART3_RXBUFSIZE=256 @@ -126,7 +126,7 @@ Solder Bridges (active by default on Nucleo-L552ZE-Q):: Use make menuconfig to configure LPUART1 as the console:: - CONFIG_STM32L5_LPUART1=y + CONFIG_STM32_LPUART1=y CONFIG_LPUART1_SERIAL_CONSOLE=y CONFIG_LPUART1_RXBUFSIZE=256 CONFIG_LPUART1_TXBUFSIZE=256 diff --git a/Documentation/platforms/arm/stm32l5/boards/stm32l562e-dk/index.rst b/Documentation/platforms/arm/stm32l5/boards/stm32l562e-dk/index.rst index 6769e7af2288e..ddba39b1801f0 100644 --- a/Documentation/platforms/arm/stm32l5/boards/stm32l562e-dk/index.rst +++ b/Documentation/platforms/arm/stm32l5/boards/stm32l562e-dk/index.rst @@ -84,7 +84,7 @@ the STLINK Virtual COM Port. Use make menuconfig to configure USART1 as the console:: - CONFIG_STM32L5_USART1=y + CONFIG_STM32_USART1=y CONFIG_USART1_SERIALDRIVER=y CONFIG_USART1_SERIAL_CONSOLE=y CONFIG_USART1_RXBUFSIZE=256 @@ -220,9 +220,9 @@ NOTES: output on USART1, as described above under "Serial Console". The elevant configuration settings are listed below:: - CONFIG_STM32L5_USART1=y - CONFIG_STM32L5_USART1_SERIALDRIVER=y - CONFIG_STM32L5_USART=y + CONFIG_STM32_USART1=y + CONFIG_STM32_USART1_SERIALDRIVER=y + CONFIG_STM32_USART=y CONFIG_USART1_SERIALDRIVER=y CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/Documentation/platforms/arm/stm32u5/boards/b-u585i-iot02a/index.rst b/Documentation/platforms/arm/stm32u5/boards/b-u585i-iot02a/index.rst index 38846fffccc57..60af81e77fa91 100644 --- a/Documentation/platforms/arm/stm32u5/boards/b-u585i-iot02a/index.rst +++ b/Documentation/platforms/arm/stm32u5/boards/b-u585i-iot02a/index.rst @@ -102,9 +102,9 @@ NOTES: output on USART3, as described above under "Serial Console". The elevant configuration settings are listed below:: - CONFIG_STM32L5_USART3=y - CONFIG_STM32L5_USART3_SERIALDRIVER=y - CONFIG_STM32L5_USART=y + CONFIG_STM32_USART3=y + CONFIG_STM32_USART3_SERIALDRIVER=y + CONFIG_STM32_USART=y CONFIG_USART3_SERIALDRIVER=y CONFIG_USART3_SERIAL_CONSOLE=y diff --git a/Documentation/quickstart/organization.rst b/Documentation/quickstart/organization.rst index 006444feb8e43..af0cb591ebed9 100644 --- a/Documentation/quickstart/organization.rst +++ b/Documentation/quickstart/organization.rst @@ -68,7 +68,7 @@ specified by several settings in the NuttX configuration file. sub-directories and are discussed in a paragraph `below <#boards-subdirectory-structure>`__. - The directory ``boards/arm/stm32/stm32f4disovery/``, as an + The directory ``boards/arm/stm32f4/stm32f4discovery/``, as an example, holds board-specific logic for the STM32F4 Discovery board and is selected via the ``CONFIG_ARCH_BOARD="stm32f4discovery"`` configuration setting. diff --git a/LICENSE b/LICENSE index f78dcd33b6ea2..a22fd18f55966 100644 --- a/LICENSE +++ b/LICENSE @@ -2918,7 +2918,7 @@ LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -boards/arm/stm32/photon/src/stm32_wlan_firmware.c +boards/arm/stm32f2/photon/src/stm32_wlan_firmware.c drivers/wireless/ieee80211/bcm43xxx/bcmf_ioctl.h ================================================ @@ -3249,8 +3249,8 @@ ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. boards/arm/rp2040/common/src/rp2040_ina219.c -boards/arm/stm32/common/src/stm32_ina219.c -boards/arm/stm32/olimex-stm32-e407/src/stm32_dac.c +boards/arm/common/stm32/src/stm32_ina219.c +boards/arm/stm32f4/olimex-stm32-e407/src/stm32_dac.c =============================================== Copyright (C) 2018,2019 Erle Robotics (Juan Flores Muñoz). All rights reserved. @@ -3282,9 +3282,9 @@ LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -boards/arm/stm32/nucleo-f303re/src/stm32_uid.c -boards/arm/stm32/omnibusf4/src/stm32_uid.c -boards/arm/stm32/stm32f4discovery/src/stm32_uid.c +boards/arm/stm32f3/nucleo-f303re/src/stm32_uid.c +boards/arm/stm32f4/omnibusf4/src/stm32_uid.c +boards/arm/stm32f4/stm32f4discovery/src/stm32_uid.c boards/arm/stm32h7/nucleo-h743zi/src/stm32_uid.c boards/arm/stm32h7/stm32h747i-disco/src/stm32_uid.c =============================================== @@ -3317,8 +3317,8 @@ LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -boards/arm/stm32/nucleo-f412zg/src/stm32_usb.c -boards/arm/stm32/stm32f411e-disco/src/stm32_usb.c +boards/arm/stm32f4/nucleo-f412zg/src/stm32_usb.c +boards/arm/stm32f4/stm32f411e-disco/src/stm32_usb.c ================================================= Copyright (C) 2017 Gregory Nutt. All rights reserved. Copyright (C) 2017 Brian Webb. All rights reserved. @@ -3350,10 +3350,10 @@ LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -boards/arm/stm32/omnibusf4/src/stm32_romfs.h -boards/arm/stm32/omnibusf4/src/stm32_romfs_initialize.c -boards/arm/stm32/stm32f4discovery/src/stm32_romfs.h -boards/arm/stm32/stm32f4discovery/src/stm32_romfs_initialize.c +boards/arm/stm32f4/omnibusf4/src/stm32_romfs.h +boards/arm/stm32f4/omnibusf4/src/stm32_romfs_initialize.c +boards/arm/stm32f4/stm32f4discovery/src/stm32_romfs.h +boards/arm/stm32f4/stm32f4discovery/src/stm32_romfs_initialize.c boards/arm/stm32f7/common/include/stm32_romfs.h boards/arm/stm32f7/common/src/stm32_romfs_initialize.c ============================================================= @@ -3386,9 +3386,9 @@ LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -boards/arm/stm32f0l0g0/nucleo-g070rb/src/stm32_gpio.c -boards/arm/stm32f0l0g0/nucleo-g070rb/src/stm32_pwm.c -boards/arm/stm32f0l0g0/nucleo-g070rb/src/stm32_timer.c +boards/arm/stm32g0/nucleo-g070rb/src/stm32_gpio.c +boards/arm/stm32g0/nucleo-g070rb/src/stm32_pwm.c +boards/arm/stm32g0/nucleo-g070rb/src/stm32_timer.c ===================================================== Copyright (C) 2019 Fundação CERTI. All rights reserved. @@ -3975,7 +3975,7 @@ LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -arch/arm/src/stm32/hardware/stm32f100_pinmap.h +arch/arm/src/stm32f1/hardware/stm32f100_pinmap.h ================================================= Copyright (C) 2009 Gregory Nutt. All rights reserved. @@ -4009,7 +4009,7 @@ LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -arch/arm/src/stm32/hardware/stm32f37xxx_sdadc.h +arch/arm/src/stm32f3/hardware/stm32f37xxx_sdadc.h ==================================================== Copyright (C) 2009, 2011, 2013 Gregory Nutt. All rights reserved. @@ -4042,7 +4042,7 @@ LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -arch/arm/src/stm32/stm32_i2c_alt.c +arch/arm/src/common/stm32/stm32_i2c_m3m4_v1_alt.c =================================== Copyright (C) 2011 Uros Platise. All rights reserved. @@ -4076,7 +4076,7 @@ LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -arch/arm/src/stm32/stm32_i2c_v2.c +arch/arm/src/common/stm32/stm32_i2c_m3m4_v2.c =========================================== Copyright (C) 2011 Uros Platise. All rights reserved. @@ -4110,8 +4110,8 @@ LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -arch/arm/src/stm32/stm32_sdadc.c -arch/arm/src/stm32/stm32_sdadc.h +arch/arm/src/common/stm32/stm32_sdadc_m3m4_v1.c +arch/arm/src/common/stm32/stm32_sdadc.h =================================== Copyright (C) 2011, 2013, 2015-2017 Gregory Nutt. All rights reserved. @@ -4144,7 +4144,7 @@ LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -arch/arm/src/stm32/stm32_tickless.c +arch/arm/src/common/stm32/stm32_tickless_m3m4_v1.c ====================================== Copyright (C) 2016-2017 Gregory Nutt. All rights reserved. @@ -4177,7 +4177,7 @@ LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -arch/arm/src/stm32/stm32_tim_lowerhalf.c +arch/arm/src/common/stm32/stm32_tim_m3m4_v1v2v3_lowerhalf.c =========================================== Copyright (C) 2015 Wail Khemir. All rights reserved. @@ -4210,8 +4210,8 @@ LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -arch/arm/src/stm32/stm32_uid.c -arch/arm/src/stm32/stm32_uid.h +arch/arm/src/common/stm32/stm32_uid_m3m4_v1v2.c +arch/arm/src/common/stm32/stm32_uid.h =================================== Copyright (C) 2015 Marawan Ragab. All rights reserved. @@ -4243,7 +4243,7 @@ LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -arch/arm/src/stm32f0l0g0/hardware/stm32g0_pinmap.h +arch/arm/src/stm32g0/hardware/stm32g0_pinmap.h ===================================================== Copyright (C) 2019 Gregory Nutt. All rights reserved. @@ -4276,7 +4276,7 @@ LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -arch/arm/src/stm32f0l0g0/stm32_i2c.c +arch/arm/src/common/stm32/stm32_i2c_m0_v1.c =========================================== Copyright (C) 2011 Uros Platise. All rights reserved. @@ -4309,7 +4309,7 @@ LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -arch/arm/src/stm32f0l0g0/stm32_pwm.c +arch/arm/src/common/stm32/stm32_pwm_m0_v1.c ======================================= Copyright (C) 2019 Fundação CERTI. All rights reserved. @@ -4341,9 +4341,9 @@ LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -arch/arm/src/stm32f0l0g0/stm32_pwm.h -arch/arm/src/stm32f0l0g0/stm32_tim.c -arch/arm/src/stm32f0l0g0/stm32_tim.h +arch/arm/src/common/stm32/stm32_pwm_m0_v1.h +arch/arm/src/common/stm32/stm32_tim_m0_v1.c +arch/arm/src/common/stm32/stm32_tim_m0_v1.h ======================================= Copyright (C) 2019 Fundação CERTI. All rights reserved. @@ -4375,7 +4375,7 @@ LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -arch/arm/src/stm32f0l0g0/stm32_tim_lowerhalf.c +arch/arm/src/common/stm32/stm32_tim_m0_v1_lowerhalf.c ================================================= Copyright (C) 2019 Fundação CERTI. All rights reserved. diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index cdf4df2bb137a..e45eed4a24eee 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -55,7 +55,7 @@ endchoice # ARM Toolchain Selection choice prompt "ARM MCU selection" - default ARCH_CHIP_STM32 + default ARCH_CHIP_STM32F1 config ARCH_CHIP_A1X bool "Allwinner A1X" @@ -489,8 +489,77 @@ config ARCH_CHIP_SIMPLELINK ---help--- TI SimpleLink CCxxx architectures (ARM Cortex-M3 or M4) -config ARCH_CHIP_STM32 - bool "STMicro STM32 F1/F2/F3/F4/G4/L1" +config ARCH_CHIP_STM32F1 + bool "STMicro STM32 F1" + select ARCH_CHIP_STM32 + select ARCH_HAVE_MPU + select ARCH_HAVE_FETCHADD + select ARCH_HAVE_I2CRESET + select ARCH_HAVE_HEAPCHECK + select ARCH_HAVE_PROGMEM + select ARCH_HAVE_SPI_BITORDER + select ARCH_HAVE_TICKLESS + select ARCH_HAVE_TIMEKEEPING + select ARM_HAVE_MPU_UNIFIED + select ARMV7M_HAVE_STACKCHECK + select ARCH_HAVE_ADJTIME + ---help--- + STMicro STM32F1 architectures (ARM Cortex-M3). + +config ARCH_CHIP_STM32F2 + bool "STMicro STM32 F2" + select ARCH_CHIP_STM32 + select ARCH_HAVE_MPU + select ARCH_HAVE_FETCHADD + select ARCH_HAVE_I2CRESET + select ARCH_HAVE_HEAPCHECK + select ARCH_HAVE_PROGMEM + select ARCH_HAVE_SPI_BITORDER + select ARCH_HAVE_TICKLESS + select ARCH_HAVE_TIMEKEEPING + select ARM_HAVE_MPU_UNIFIED + select ARMV7M_HAVE_STACKCHECK + select ARCH_HAVE_ADJTIME + ---help--- + STMicro STM32F2 architectures (ARM Cortex-M3). + +config ARCH_CHIP_STM32F3 + bool "STMicro STM32 F3" + select ARCH_CHIP_STM32 + select ARCH_HAVE_MPU + select ARCH_HAVE_FETCHADD + select ARCH_HAVE_I2CRESET + select ARCH_HAVE_HEAPCHECK + select ARCH_HAVE_PROGMEM + select ARCH_HAVE_SPI_BITORDER + select ARCH_HAVE_TICKLESS + select ARCH_HAVE_TIMEKEEPING + select ARM_HAVE_MPU_UNIFIED + select ARMV7M_HAVE_STACKCHECK + select ARCH_HAVE_ADJTIME + ---help--- + STMicro STM32F3 architectures (ARM Cortex-M4). + +config ARCH_CHIP_STM32F4 + bool "STMicro STM32 F4" + select ARCH_CHIP_STM32 + select ARCH_HAVE_MPU + select ARCH_HAVE_FETCHADD + select ARCH_HAVE_I2CRESET + select ARCH_HAVE_HEAPCHECK + select ARCH_HAVE_PROGMEM + select ARCH_HAVE_SPI_BITORDER + select ARCH_HAVE_TICKLESS + select ARCH_HAVE_TIMEKEEPING + select ARM_HAVE_MPU_UNIFIED + select ARMV7M_HAVE_STACKCHECK + select ARCH_HAVE_ADJTIME + ---help--- + STMicro STM32F4 architectures (ARM Cortex-M4). + +config ARCH_CHIP_STM32G4 + bool "STMicro STM32 G4" + select ARCH_CHIP_STM32 select ARCH_HAVE_MPU select ARCH_HAVE_FETCHADD select ARCH_HAVE_I2CRESET @@ -503,22 +572,42 @@ config ARCH_CHIP_STM32 select ARMV7M_HAVE_STACKCHECK select ARCH_HAVE_ADJTIME ---help--- - STMicro STM32 architectures (ARM Cortex-M3/4). + STMicro STM32G4 architectures (ARM Cortex-M4). + +config ARCH_CHIP_STM32L1 + bool "STMicro STM32 L1" + select ARCH_CHIP_STM32 + select ARCH_HAVE_MPU + select ARCH_HAVE_FETCHADD + select ARCH_HAVE_I2CRESET + select ARCH_HAVE_HEAPCHECK + select ARCH_HAVE_PROGMEM + select ARCH_HAVE_SPI_BITORDER + select ARCH_HAVE_TICKLESS + select ARCH_HAVE_TIMEKEEPING + select ARM_HAVE_MPU_UNIFIED + select ARMV7M_HAVE_STACKCHECK + select ARCH_HAVE_ADJTIME + ---help--- + STMicro STM32L1 architectures (ARM Cortex-M3). config ARCH_CHIP_STM32F0 bool "STMicro STM32 F0" + select ARCH_CHIP_STM32 select ARCH_CORTEXM0 ---help--- STMicro STM32F0 architectures (ARM Cortex-M0). config ARCH_CHIP_STM32L0 bool "STMicro STM32 L0" + select ARCH_CHIP_STM32 select ARCH_CORTEXM0 ---help--- STMicro STM32L0 architectures (ARM Cortex-M0+). config ARCH_CHIP_STM32G0 bool "STMicro STM32 G0" + select ARCH_CHIP_STM32 select ARCH_CORTEXM0 select ARCH_HAVE_PROGMEM ---help--- @@ -526,12 +615,14 @@ config ARCH_CHIP_STM32G0 config ARCH_CHIP_STM32C0 bool "STMicro STM32 C0" + select ARCH_CHIP_STM32 select ARCH_CORTEXM0 ---help--- STMicro STM32C0 architectures (ARM Cortex-M0+). config ARCH_CHIP_STM32F7 bool "STMicro STM32 F7" + select ARCH_CHIP_STM32 select ARCH_CORTEXM7 select ARCH_HAVE_MPU select ARCH_HAVE_FETCHADD @@ -548,6 +639,7 @@ config ARCH_CHIP_STM32F7 config ARCH_CHIP_STM32H7 bool "STMicro STM32 H7" + select ARCH_CHIP_STM32 select ARCH_HAVE_MPU select ARCH_HAVE_I2CRESET select ARCH_HAVE_PROGMEM @@ -563,6 +655,7 @@ config ARCH_CHIP_STM32H7 config ARCH_CHIP_STM32L4 bool "STMicro STM32 L4" + select ARCH_CHIP_STM32 select ARCH_CORTEXM4 select ARCH_HAVE_MPU select ARCH_HAVE_FETCHADD @@ -578,6 +671,7 @@ config ARCH_CHIP_STM32L4 config ARCH_CHIP_STM32H5 bool "STMicro STM32 H5" + select ARCH_CHIP_STM32 select ARCH_CORTEXM33 select ARCH_HAVE_MPU select ARM_HAVE_DSP @@ -593,6 +687,7 @@ config ARCH_CHIP_STM32H5 config ARCH_CHIP_STM32N6 bool "STMicro STM32 N6" + select ARCH_CHIP_STM32 select ARCH_CORTEXM55 select ARCH_HAVE_FPU select ARCH_HAVE_MPU @@ -606,6 +701,7 @@ config ARCH_CHIP_STM32N6 config ARCH_CHIP_STM32L5 bool "STMicro STM32 L5" + select ARCH_CHIP_STM32 select ARCH_CORTEXM33 select ARCH_HAVE_MPU select ARM_HAVE_DSP @@ -621,6 +717,7 @@ config ARCH_CHIP_STM32L5 config ARCH_CHIP_STM32U5 bool "STMicro STM32 U5" + select ARCH_CHIP_STM32 select ARCH_CORTEXM33 select ARCH_HAVE_MPU select ARM_HAVE_DSP @@ -637,6 +734,7 @@ config ARCH_CHIP_STM32U5 config ARCH_CHIP_STM32WB bool "STMicro STM32 WB" + select ARCH_CHIP_STM32 select ARCH_CORTEXM4 select ARCH_HAVE_FPU select ARCH_HAVE_MPU @@ -653,6 +751,7 @@ config ARCH_CHIP_STM32WB config ARCH_CHIP_STM32WL5 bool "STMicro STM32 WL5" + select ARCH_CHIP_STM32 select ARCH_CORTEXM4 select ARCH_HAVE_MPU select ARCH_HAVE_FETCHADD @@ -812,6 +911,13 @@ config ARCH_CHIP_ARM_CUSTOM endchoice # ARM MCU selection +config ARCH_CHIP_STM32 + bool + default n + ---help--- + Common STM32 architecture selector. This is selected by the concrete + STM32 family options and gates shared STM32 Kconfig options. + config ARCH_ARM7TDMI bool default n @@ -1211,8 +1317,16 @@ config ARCH_CHIP default "samd5e5" if ARCH_CHIP_SAMD5X || ARCH_CHIP_SAME5X default "sam34" if ARCH_CHIP_SAM34 default "samv7" if ARCH_CHIP_SAMV7 - default "stm32" if ARCH_CHIP_STM32 - default "stm32f0l0g0" if ARCH_CHIP_STM32F0 || ARCH_CHIP_STM32L0 || ARCH_CHIP_STM32G0 || ARCH_CHIP_STM32C0 + default "stm32f1" if ARCH_CHIP_STM32F1 + default "stm32f2" if ARCH_CHIP_STM32F2 + default "stm32f3" if ARCH_CHIP_STM32F3 + default "stm32f4" if ARCH_CHIP_STM32F4 + default "stm32g4" if ARCH_CHIP_STM32G4 + default "stm32l1" if ARCH_CHIP_STM32L1 + default "stm32f0" if ARCH_CHIP_STM32F0 + default "stm32l0" if ARCH_CHIP_STM32L0 + default "stm32g0" if ARCH_CHIP_STM32G0 + default "stm32c0" if ARCH_CHIP_STM32C0 default "stm32f7" if ARCH_CHIP_STM32F7 default "stm32h7" if ARCH_CHIP_STM32H7 default "stm32l4" if ARCH_CHIP_STM32L4 @@ -1713,11 +1827,35 @@ endif if ARCH_CHIP_SAMV7 source "arch/arm/src/samv7/Kconfig" endif -if ARCH_CHIP_STM32 -source "arch/arm/src/stm32/Kconfig" +if ARCH_CHIP_STM32F1 +source "arch/arm/src/stm32f1/Kconfig" endif -if ARCH_CHIP_STM32F0 || ARCH_CHIP_STM32L0 || ARCH_CHIP_STM32G0 || ARCH_CHIP_STM32C0 -source "arch/arm/src/stm32f0l0g0/Kconfig" +if ARCH_CHIP_STM32F2 +source "arch/arm/src/stm32f2/Kconfig" +endif +if ARCH_CHIP_STM32F3 +source "arch/arm/src/stm32f3/Kconfig" +endif +if ARCH_CHIP_STM32F4 +source "arch/arm/src/stm32f4/Kconfig" +endif +if ARCH_CHIP_STM32G4 +source "arch/arm/src/stm32g4/Kconfig" +endif +if ARCH_CHIP_STM32L1 +source "arch/arm/src/stm32l1/Kconfig" +endif +if ARCH_CHIP_STM32F0 +source "arch/arm/src/stm32f0/Kconfig" +endif +if ARCH_CHIP_STM32L0 +source "arch/arm/src/stm32l0/Kconfig" +endif +if ARCH_CHIP_STM32G0 +source "arch/arm/src/stm32g0/Kconfig" +endif +if ARCH_CHIP_STM32C0 +source "arch/arm/src/stm32c0/Kconfig" endif if ARCH_CHIP_STM32F7 source "arch/arm/src/stm32f7/Kconfig" @@ -1746,6 +1884,9 @@ endif if ARCH_CHIP_STM32WL5 source "arch/arm/src/stm32wl5/Kconfig" endif +if ARCH_CHIP_STM32 +source "arch/arm/src/common/stm32/Kconfig" +endif if ARCH_CHIP_STR71X source "arch/arm/src/str71x/Kconfig" endif diff --git a/arch/arm/include/phy62xx/phy62xx_irq.h b/arch/arm/include/phy62xx/phy62xx_irq.h index b8bf21ed912b9..c6d55217f6276 100644 --- a/arch/arm/include/phy62xx/phy62xx_irq.h +++ b/arch/arm/include/phy62xx/phy62xx_irq.h @@ -44,7 +44,7 @@ * memory in the IRQ to handle mapping tables. * * Processor Exceptions (vectors 0-15). These common definitions can be - * found in nuttx/arch/arm/include/stm32f0l0g0/irq.h + * found in nuttx/arch/arm/include/phy62xx/irq.h */ #define PHY62XX_IRQ_BB_IRQn (PHY62XX_IRQ_EXTINT + 4) /* 4: RCC and CRS */ diff --git a/arch/arm/include/stm32/chip.h b/arch/arm/include/stm32/chip.h deleted file mode 100644 index 1c62bcc3c4b57..0000000000000 --- a/arch/arm/include/stm32/chip.h +++ /dev/null @@ -1,2756 +0,0 @@ -/**************************************************************************** - * arch/arm/include/stm32/chip.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_INCLUDE_STM32_CHIP_H -#define __ARCH_ARM_INCLUDE_STM32_CHIP_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -/**************************************************************************** - * Pre-processor Prototypes - ****************************************************************************/ - -/* Check the STM32 family configuration. - * It must be done in arch/arm/src/stm32/Kconfig ! - */ - -#ifdef CONFIG_STM32_STM32F10XX -# define __HAVE_F1 1 -#else -# define __HAVE_F1 0 -#endif -#ifdef CONFIG_STM32_STM32F20XX -# define __HAVE_F2 1 -#else -# define __HAVE_F2 0 -#endif -#ifdef CONFIG_STM32_STM32F30XX -# define __HAVE_F30 1 -#else -# define __HAVE_F30 0 -#endif -#ifdef CONFIG_STM32_STM32F33XX -# define __HAVE_F33 1 -#else -# define __HAVE_F33 0 -#endif -#ifdef CONFIG_STM32_STM32F37XX -# define __HAVE_F37 1 -#else -# define __HAVE_F37 0 -#endif -#ifdef CONFIG_STM32_STM32F4XXX -# define __HAVE_F4 1 -#else -# define __HAVE_F4 0 -#endif -#ifdef CONFIG_STM32_STM32G4XXX -# define __HAVE_G4 1 -#else -# define __HAVE_G4 0 -#endif -#ifdef CONFIG_STM32_STM32L15XX -# define __HAVE_L1 1 -#else -# define __HAVE_L1 0 -#endif - -#if ((__HAVE_F1 + __HAVE_F2 + __HAVE_F30 + __HAVE_F33 + __HAVE_F37 + __HAVE_F4 + \ - __HAVE_G4 + __HAVE_L1) != 1) -# error "Only one STM32 family must be selected !" -#endif - -#ifdef CONFIG_STM32_LOWDENSITY -# define __HAVE_LD 1 -#else -# define __HAVE_LD 0 -#endif -#ifdef CONFIG_STM32_MEDIUMDENSITY -# define __HAVE_MD 1 -#else -# define __HAVE_MD 0 -#endif -#ifdef CONFIG_STM32_MEDIUMPLUSDENSITY -# define __HAVE_MPD 1 -#else -# define __HAVE_MPD 0 -#endif -#ifdef CONFIG_STM32_HIGHDENSITY -# define __HAVE_HD 1 -#else -# define __HAVE_HD 0 -#endif - -#if (__HAVE_LD +__HAVE_MD + __HAVE_MPD + __HAVE_HD) > 1 -# error "Up to one density configuration must be selected" -#endif - -/* Get customizations for each supported chip and provide alternate function - * pin-mapping - * - * NOTE: Each GPIO pin may serve either for general purpose I/O or for a - * special alternate function (such as USART, CAN, USB, SDIO, etc.). That - * particular pin-mapping will depend on the package and STM32 family. If - * you are incorporating a new STM32 chip into NuttX, you will need to add - * the pin-mapping to a header file and to include that header file below. - * The chip-specific pin-mapping is defined in the chip datasheet. - */ - -/* STM32L EnergyLite Line ***************************************************/ - -/* STM32L151XX -- No LCD - * STM32L152XX -- With LCD - * - * STM32L15XCX -- 48-pins - * STM32L15XRX -- 64-pins - * STM32L15XVX -- 100-pins - * STM32L15XZX -- 144-pins - * - * STM32L15XX6 -- 32KB FLASH, 10KB SRAM, 4KB EEPROM - * STM32L15XX8 -- 64KB FLASH, 10KB SRAM, 4KB EEPROM - * STM32L15XXB -- 128KB FLASH, 16KB SRAM, 4KB EEPROM - * - * STM32L15XXC -- 256KB FLASH, 32KB SRAM, 8KB EEPROM (medium+ density) - * - * STM32L16XXD -- 384KB FLASH, 48KB SRAM, 12KB EEPROM (high density) - * STM32L16XXE -- 512KB FLASH, 80KB SRAM, 16KB EEPROM (high density) - */ - -#if defined(CONFIG_ARCH_CHIP_STM32L151C6) || defined(CONFIG_ARCH_CHIP_STM32L151C8) || \ - defined(CONFIG_ARCH_CHIP_STM32L151CB) -# define STM32_NFSMC 0 /* No FSMC */ -# define STM32_NATIM 0 /* No advanced timers */ -# define STM32_NGTIM 3 /* 16-bit general up/down timers TIM2-4 with DMA */ -# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */ -# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 with DMA */ -# define STM32_NDMA 1 /* DMA1, 7-channels */ -# define STM32_NSPI 2 /* SPI1-2 */ -# define STM32_NI2S 0 /* No I2S */ -# define STM32_NUSART 3 /* USART1-3 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 2 /* I2C1-2 */ -# define STM32_NCAN 0 /* No CAN */ -# define STM32_NSDIO 0 /* No SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (only USB 2.0 device) */ -# define STM32_NGPIO 37 /* GPIOA-E,H */ -# define STM32_NADC 1 /* ADC1, 14-channels */ -# define STM32_NDAC 2 /* DAC 1, 2 channels */ -# define STM32_NCMP 2 /* (2) Comparators */ -# define STM32_NCAPSENSE 13 /* Capacitive sensing channels */ -# define STM32_NCRC 0 /* No CRC */ -# define STM32_NETHERNET 0 /* No Ethernet */ -# define STM32_NRNG 0 /* No random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32L151R6) || defined(CONFIG_ARCH_CHIP_STM32L151R8) || \ - defined(CONFIG_ARCH_CHIP_STM32L151RB) -# define STM32_NFSMC 0 /* No FSMC */ -# define STM32_NATIM 0 /* No advanced timers */ -# define STM32_NGTIM 3 /* 16-bit general up/down timers TIM2-4 with DMA */ -# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */ -# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 with DMA */ -# define STM32_NDMA 1 /* DMA1, 7-channels */ -# define STM32_NSPI 2 /* SPI1-2 */ -# define STM32_NI2S 0 /* No I2S */ -# define STM32_NUSART 3 /* USART1-3 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 2 /* I2C1-2 */ -# define STM32_NCAN 0 /* No CAN */ -# define STM32_NSDIO 0 /* No SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (only USB 2.0 device) */ -# define STM32_NGPIO 51 /* GPIOA-E,H */ -# define STM32_NADC 1 /* ADC1, 20-channels */ -# define STM32_NDAC 2 /* DAC , 2 channels */ -# define STM32_NCMP 2 /* (2) Comparators */ -# define STM32_NCAPSENSE 20 /* Capacitive sensing channels */ -# define STM32_NCRC 0 /* No CRC */ -# define STM32_NETHERNET 0 /* No Ethernet */ -# define STM32_NRNG 0 /* No random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32L151V6) || defined(CONFIG_ARCH_CHIP_STM32L151V8) || \ - defined(CONFIG_ARCH_CHIP_STM32L151VB) -# define STM32_NFSMC 0 /* No FSMC */ -# define STM32_NATIM 0 /* No advanced timers */ -# define STM32_NGTIM 3 /* 16-bit general up/down timers TIM2-4 with DMA */ -# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */ -# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 with DMA */ -# define STM32_NDMA 1 /* DMA1, 7-channels */ -# define STM32_NSPI 2 /* SPI1-2 */ -# define STM32_NI2S 0 /* No I2S */ -# define STM32_NUSART 3 /* USART1-3 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 2 /* I2C1-2 */ -# define STM32_NCAN 0 /* No CAN */ -# define STM32_NSDIO 0 /* No SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (only USB 2.0 device) */ -# define STM32_NGPIO 83 /* GPIOA-E,H */ -# define STM32_NADC 1 /* ADC1, 24-channels */ -# define STM32_NDAC 2 /* DAC 1, 2 channels */ -# define STM32_NCMP 2 /* (2) Comparators */ -# define STM32_NCAPSENSE 20 /* Capacitive sensing channels */ -# define STM32_NCRC 0 /* No CRC */ -# define STM32_NETHERNET 0 /* No Ethernet */ -# define STM32_NRNG 0 /* No random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32L152C6) || defined(CONFIG_ARCH_CHIP_STM32L152C8) || \ - defined(CONFIG_ARCH_CHIP_STM32L152CB) -# define STM32_NFSMC 0 /* No FSMC */ -# define STM32_NATIM 0 /* No advanced timers */ -# define STM32_NGTIM 3 /* 16-bit general up/down timers TIM2-4 with DMA */ -# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */ -# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 with DMA */ -# define STM32_NDMA 1 /* DMA1, 7-channels */ -# define STM32_NSPI 2 /* SPI1-2 */ -# define STM32_NI2S 0 /* No I2S */ -# define STM32_NUSART 3 /* USART1-3 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 2 /* I2C1-2 */ -# define STM32_NCAN 0 /* No CAN */ -# define STM32_NSDIO 0 /* No SDIO */ -# define STM32_NLCD 1 /* LCD 4x18 */ -# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (only USB 2.0 device) */ -# define STM32_NGPIO 37 /* GPIOA-E,H */ -# define STM32_NADC 1 /* ADC1, 14-channels */ -# define STM32_NDAC 2 /* DAC 1, 2 channels */ -# define STM32_NCMP 2 /* (2) Comparators */ -# define STM32_NCAPSENSE 13 /* Capacitive sensing channels */ -# define STM32_NCRC 0 /* No CRC */ -# define STM32_NETHERNET 0 /* No Ethernet */ -# define STM32_NRNG 0 /* No random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32L152R6) || defined(CONFIG_ARCH_CHIP_STM32L152R8) || \ - defined(CONFIG_ARCH_CHIP_STM32L152RB) -# define STM32_NFSMC 0 /* No FSMC */ -# define STM32_NATIM 0 /* No advanced timers */ -# define STM32_NGTIM 3 /* 16-bit general up/down timers TIM2-4 with DMA */ -# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */ -# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 with DMA */ -# define STM32_NDMA 1 /* DMA1, 7-channels */ -# define STM32_NSPI 2 /* SPI1-2 */ -# define STM32_NI2S 0 /* No I2S */ -# define STM32_NUSART 3 /* USART1-3 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 2 /* I2C1-2 */ -# define STM32_NCAN 0 /* No CAN */ -# define STM32_NSDIO 0 /* No SDIO */ -# define STM32_NLCD 1 /* LCD 4x32, 8x28 */ -# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (only USB 2.0 device) */ -# define STM32_NGPIO 51 /* GPIOA-E,H */ -# define STM32_NADC 1 /* ADC1, 20-channels */ -# define STM32_NDAC 2 /* DAC 1, 2 channels */ -# define STM32_NCMP 2 /* (2) Comparators */ -# define STM32_NCAPSENSE 20 /* Capacitive sensing channels */ -# define STM32_NCRC 0 /* No CRC */ -# define STM32_NETHERNET 0 /* No Ethernet */ -# define STM32_NRNG 0 /* No random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32L152V6) || defined(CONFIG_ARCH_CHIP_STM32L152V8) || \ - defined(CONFIG_ARCH_CHIP_STM32L152VB) -# define STM32_NFSMC 0 /* No FSMC */ -# define STM32_NATIM 0 /* No advanced timers */ -# define STM32_NGTIM 3 /* 16-bit general up/down timers TIM2-4 with DMA */ -# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */ -# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 with DMA */ -# define STM32_NDMA 1 /* DMA1, 7-channels */ -# define STM32_NSPI 2 /* SPI1-2 */ -# define STM32_NI2S 0 /* No I2S */ -# define STM32_NUSART 3 /* USART1-3 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 2 /* I2C1-2 */ -# define STM32_NCAN 0 /* No CAN */ -# define STM32_NSDIO 0 /* No SDIO */ -# define STM32_NLCD 1 /* LCD 4x44, 8x40 */ -# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (only USB 2.0 device) */ -# define STM32_NGPIO 83 /* GPIOA-E,H */ -# define STM32_NADC 1 /* ADC1, 24-channels */ -# define STM32_NDAC 2 /* DAC 1, 2 channels */ -# define STM32_NCMP 2 /* (2) Comparators */ -# define STM32_NCAPSENSE 20 /* Capacitive sensing channels */ -# define STM32_NCRC 0 /* No CRC */ -# define STM32_NETHERNET 0 /* No Ethernet */ -# define STM32_NRNG 0 /* No random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32L152CC) -# define STM32_NFSMC 0 /* No FSMC */ -# define STM32_NATIM 0 /* No advanced timers */ -# define STM32_NGTIM 3 /* 16-bit general up/down timers TIM2-4 with DMA */ -# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */ -# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 with DMA */ -# define STM32_NDMA 2 /* DMA1, 7-channels, DMA2 (5 channels) */ -# define STM32_NSPI 3 /* SPI1-3 */ -# define STM32_NI2S 2 /* I2S1-2, overlapping with SPI2-3 */ -# define STM32_NUSART 3 /* USART1-3 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 2 /* I2C1-2 */ -# define STM32_NCAN 0 /* No CAN */ -# define STM32_NSDIO 0 /* No SDIO */ -# define STM32_NLCD 1 /* LCD 4x18 */ -# define STM32_NUSBOTG 1 /* USB OTG FS/HS (only USB 2.0 device) */ -# define STM32_NGPIO 37 /* GPIOA-E,H */ -# define STM32_NADC 1 /* ADC1, 14-channels */ -# define STM32_NDAC 2 /* DAC 1, 2 channels */ -# define STM32_NCMP 2 /* (2) Comparators */ -# define STM32_NCAPSENSE 16 /* Capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 0 /* No ethernet */ -# define STM32_NRNG 0 /* No random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32L152RC) -# define STM32_NFSMC 0 /* No FSMC */ -# define STM32_NATIM 0 /* No advanced timers */ -# define STM32_NGTIM 3 /* 16-bit general up/down timers TIM2-4 with DMA */ -# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */ -# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 with DMA */ -# define STM32_NDMA 2 /* DMA1, 7-channels, DMA2 (5 channels) */ -# define STM32_NSPI 3 /* SPI1-3 */ -# define STM32_NI2S 2 /* I2S1-2, overlapping with SPI2-3 */ -# define STM32_NUSART 3 /* USART1-3 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 2 /* I2C1-2 */ -# define STM32_NCAN 0 /* No CAN */ -# define STM32_NSDIO 0 /* No SDIO */ -# define STM32_NLCD 1 /* LCD 4x32, 8x28 */ -# define STM32_NUSBOTG 1 /* USB OTG FS/HS (only USB 2.0 device) */ -# define STM32_NGPIO 51 /* GPIOA-E,H */ -# define STM32_NADC 1 /* ADC1, 21-channels */ -# define STM32_NDAC 2 /* DAC 1, 2 channels */ -# define STM32_NCMP 2 /* (2) Comparators */ -# define STM32_NCAPSENSE 23 /* Capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 0 /* No ethernet */ -# define STM32_NRNG 0 /* No random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32L152VC) -# define STM32_NFSMC 0 /* No FSMC */ -# define STM32_NATIM 0 /* No advanced timers */ -# define STM32_NGTIM 3 /* 16-bit general up/down timers TIM2-4 with DMA */ -# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */ -# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 with DMA */ -# define STM32_NDMA 2 /* DMA1, 7-channels, DMA2 (5 channels) */ -# define STM32_NSPI 3 /* SPI1-3 */ -# define STM32_NI2S 2 /* I2S1-2, overlapping with SPI2-3 */ -# define STM32_NUSART 3 /* USART1-3 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 2 /* I2C1-2 */ -# define STM32_NCAN 0 /* No CAN */ -# define STM32_NSDIO 0 /* No SDIO */ -# define STM32_NLCD 1 /* LCD 4x44, 8x40 */ -# define STM32_NUSBOTG 1 /* USB OTG FS/HS (only USB 2.0 device) */ -# define STM32_NGPIO 83 /* GPIOA-E,H */ -# define STM32_NADC 1 /* ADC1, 25-channels */ -# define STM32_NDAC 2 /* DAC 1, 2 channels */ -# define STM32_NCMP 2 /* (2) Comparators */ -# define STM32_NCAPSENSE 23 /* Capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 0 /* No ethernet */ -# define STM32_NRNG 0 /* No random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32L151RE) || defined(CONFIG_ARCH_CHIP_STM32L152RE) -# define STM32_NFSMC 0 /* No FSMC */ -# define STM32_NATIM 0 /* No advanced timers */ -# define STM32_NGTIM 3 /* 16-bit general up/down timers TIM2-4 with DMA */ -# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */ -# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 with DMA */ -# define STM32_NDMA 2 /* DMA1, 7-channels, DMA2 (5 channels) */ -# define STM32_NSPI 3 /* SPI1-3 */ -# define STM32_NI2S 2 /* I2S1-2, overlapping with SPI2-3 */ -# define STM32_NUSART 5 /* USART1-5 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 2 /* I2C1-2 */ -# define STM32_NCAN 0 /* No CAN */ -# define STM32_NSDIO 0 /* No SDIO */ -# define STM32_NLCD 1 /* LCD 4x44, 8x40 */ -# define STM32_NUSBOTG 1 /* USB OTG FS/HS (only USB 2.0 device) */ -# define STM32_NGPIO 51 /* GPIOA-E,H */ -# define STM32_NADC 1 /* ADC1, 25-channels */ -# define STM32_NDAC 2 /* DAC 1, 2 channels */ -# define STM32_NCMP 2 /* (2) Comparators */ -# define STM32_NCAPSENSE 23 /* Capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 0 /* No ethernet */ -# define STM32_NRNG 0 /* No random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32L151VE) || defined(CONFIG_ARCH_CHIP_STM32L152VE) -# define STM32_NFSMC 0 /* No FSMC */ -# define STM32_NATIM 0 /* No advanced timers */ -# define STM32_NGTIM 3 /* 16-bit general up/down timers TIM2-4 with DMA */ -# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */ -# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 with DMA */ -# define STM32_NDMA 2 /* DMA1, 7-channels, DMA2 (5 channels) */ -# define STM32_NSPI 3 /* SPI1-3 */ -# define STM32_NI2S 2 /* I2S1-2, overlapping with SPI2-3 */ -# define STM32_NUSART 5 /* USART1-5 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 2 /* I2C1-2 */ -# define STM32_NCAN 0 /* No CAN */ -# define STM32_NSDIO 0 /* No SDIO */ -# define STM32_NLCD 1 /* LCD 4x44, 8x40 */ -# define STM32_NUSBOTG 1 /* USB OTG FS/HS (only USB 2.0 device) */ -# define STM32_NGPIO 83 /* GPIOA-E,H */ -# define STM32_NADC 1 /* ADC1, 25-channels */ -# define STM32_NDAC 2 /* DAC 1, 2 channels */ -# define STM32_NCMP 2 /* (2) Comparators */ -# define STM32_NCAPSENSE 23 /* Capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 0 /* No ethernet */ -# define STM32_NRNG 0 /* No random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32L151QE) || defined(CONFIG_ARCH_CHIP_STM32L152QE) -# define STM32_NFSMC 0 /* No FSMC */ -# define STM32_NATIM 0 /* No advanced timers */ -# define STM32_NGTIM 3 /* 16-bit general up/down timers TIM2-4 with DMA */ -# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */ -# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 with DMA */ -# define STM32_NDMA 2 /* DMA1, 7-channels, DMA2 (5 channels) */ -# define STM32_NSPI 3 /* SPI1-3 */ -# define STM32_NI2S 2 /* I2S1-2, overlapping with SPI2-3 */ -# define STM32_NUSART 5 /* USART1-5 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 2 /* I2C1-2 */ -# define STM32_NCAN 0 /* No CAN */ -# define STM32_NSDIO 0 /* No SDIO */ -# define STM32_NLCD 1 /* LCD 4x44, 8x40 */ -# define STM32_NUSBOTG 1 /* USB OTG FS/HS (only USB 2.0 device) */ -# define STM32_NGPIO 109 /* GPIOA-E,H */ -# define STM32_NADC 1 /* ADC1, 25-channels */ -# define STM32_NDAC 2 /* DAC 1, 2 channels */ -# define STM32_NCMP 2 /* (2) Comparators */ -# define STM32_NCAPSENSE 33 /* Capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 0 /* No ethernet */ -# define STM32_NRNG 0 /* No random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32L151ZE) || defined(CONFIG_ARCH_CHIP_STM32L152ZE) -# define STM32_NFSMC 0 /* No FSMC */ -# define STM32_NATIM 0 /* No advanced timers */ -# define STM32_NGTIM 3 /* 16-bit general up/down timers TIM2-4 with DMA */ -# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */ -# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 with DMA */ -# define STM32_NDMA 2 /* DMA1, 7-channels, DMA2 (5 channels) */ -# define STM32_NSPI 3 /* SPI1-3 */ -# define STM32_NI2S 2 /* I2S1-2, overlapping with SPI2-3 */ -# define STM32_NUSART 5 /* USART1-5 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 2 /* I2C1-2 */ -# define STM32_NCAN 0 /* No CAN */ -# define STM32_NSDIO 0 /* No SDIO */ -# define STM32_NLCD 1 /* LCD 4x44, 8x40 */ -# define STM32_NUSBOTG 1 /* USB OTG FS/HS (only USB 2.0 device) */ -# define STM32_NGPIO 115 /* GPIOA-E,H */ -# define STM32_NADC 1 /* ADC1, 25-channels */ -# define STM32_NDAC 2 /* DAC 1, 2 channels */ -# define STM32_NCMP 2 /* (2) Comparators */ -# define STM32_NCAPSENSE 34 /* Capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 0 /* No ethernet */ -# define STM32_NRNG 0 /* No random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32L162ZD) -# define STM32_NFSMC 1 /* FSMC */ -# define STM32_NATIM 0 /* No advanced timers */ -# define STM32_NGTIM 4 /* 16-bit general timers TIM2-4 with DMA - * 32-bit general timer TIM5 with DMA */ -# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */ -# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 without DMA */ -# define STM32_NDMA 2 /* DMA1, 7-channels, DMA2 (5 channels) */ -# define STM32_NSPI 3 /* SPI1-3 */ -# define STM32_NI2S 2 /* I2S1-2, overlapping with SPI2-3 */ -# define STM32_NUSART 5 /* USART1-3, UART4-5 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 2 /* I2C1-2 */ -# define STM32_NCAN 0 /* No CAN */ -# define STM32_NSDIO 1 /* SDIO */ -# define STM32_NLCD 1 /* LCD 4x44, 8x40 */ -# define STM32_NUSBOTG 1 /* USB OTG FS/HS (only USB 2.0 device) */ -# define STM32_NGPIO 115 /* GPIOA-G,H */ -# define STM32_NADC 1 /* ADC1, 40-channels */ -# define STM32_NDAC 2 /* DAC 1, 2 channels */ -# define STM32_NCMP 2 /* (2) Comparators */ -# define STM32_NCAPSENSE 34 /* Capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 0 /* No ethernet */ -# define STM32_NRNG 0 /* No random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32L162VE) -# define STM32_NFSMC 0 /* No FSMC */ -# define STM32_NATIM 0 /* No advanced timers */ -# define STM32_NGTIM 4 /* 16-bit general timers TIM2-4 with DMA - * 32-bit general timer TIM5 with DMA */ -# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */ -# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 with DMA */ -# define STM32_NDMA 2 /* DMA1, 12-channels */ -# define STM32_NSPI 3 /* SPI1-3 */ -# define STM32_NI2S 2 /* I2S1-2, overlapping with SPI2-3 */ -# define STM32_NUSART 5 /* USART1-3, UART4-5 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 2 /* I2C1-2 */ -# define STM32_NCAN 0 /* No CAN */ -# define STM32_NSDIO 0 /* No SDIO */ -# define STM32_NLCD 1 /* LCD 4x44, 8x40*/ -# define STM32_NUSBOTG 1 /* USB OTG FS/HS (only USB 2.0 device) */ -# define STM32_NGPIO 83 /* GPIOA-G,H */ - -# define STM32_NADC 1 /* ADC1, 25-channels */ -# define STM32_NDAC 2 /* DAC 1, 2 channels */ -# define STM32_NCMP 2 /* (2) Comparators */ -# define STM32_NCAPSENSE 23 /* Capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 0 /* No ethernet */ -# define STM32_NRNG 0 /* No random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -/* STM32 F100 Value Line ****************************************************/ - -#elif defined(CONFIG_ARCH_CHIP_STM32F100C8) || defined(CONFIG_ARCH_CHIP_STM32F100CB) \ - || defined(CONFIG_ARCH_CHIP_STM32F100R8) || defined(CONFIG_ARCH_CHIP_STM32F100RB) -# define STM32_NFSMC 0 /* No FSMC */ -# define STM32_NATIM 1 /* One advanced timer TIM1 */ -# define STM32_NGTIM 3 /* 16-bit general timers TIM2-4 with DMA */ -# define STM32_NGTIMNDMA 0 /* No 16-bit general timers without DMA */ -# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 */ - -/* TODO: there are also 3 additional timers (15-17) - * that don't fit any existing category - */ - -# define STM32_NDMA 1 /* DMA1 */ -# define STM32_NSPI 2 /* SPI1-2 */ -# define STM32_NI2S 0 /* No I2S */ -# define STM32_NUSART 3 /* USART1-3 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 2 /* I2C1-2 */ -# define STM32_NCAN 0 /* No CAN */ -# define STM32_NSDIO 0 /* No SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 0 /* No USB OTG FS/HS */ -# define STM32_NGPIO 64 /* GPIOA-D */ -# define STM32_NADC 1 /* ADC1 */ -# define STM32_NDAC 2 /* DAC 1, 2 channels */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC1 */ -# define STM32_NETHERNET 0 /* No Ethernet */ -# define STM32_NRNG 0 /* No random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F100V8) || defined(CONFIG_ARCH_CHIP_STM32F100VB) -# define STM32_NFSMC 0 /* FSMC */ -# define STM32_NATIM 1 /* One advanced timer TIM1 */ -# define STM32_NGTIM 3 /* 16-bit general timers TIM2-4 with DMA */ -# define STM32_NGTIMNDMA 0 /* No 16-bit general timers without DMA */ -# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 */ - -/* TODO: there are also 3 additional timers (15-17) - * that don't fit any existing category - */ - -# define STM32_NDMA 1 /* DMA1 */ -# define STM32_NSPI 2 /* SPI1-2 */ -# define STM32_NI2S 0 /* No I2S */ -# define STM32_NUSART 3 /* USART1-3 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 2 /* I2C1-2 */ -# define STM32_NCAN 0 /* No CAN */ -# define STM32_NSDIO 0 /* No SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 0 /* No USB OTG FS/HS */ -# define STM32_NGPIO 80 /* GPIOA-E */ -# define STM32_NADC 1 /* ADC1 */ -# define STM32_NDAC 2 /* DAC 1, 2 channels */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC1 */ -# define STM32_NETHERNET 0 /* No Ethernet */ -# define STM32_NRNG 0 /* No random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -/* STM32 F100 High-density value Line ***************************************/ - -#elif defined(CONFIG_ARCH_CHIP_STM32F100RC) || defined(CONFIG_ARCH_CHIP_STM32F100RD) \ - || defined(CONFIG_ARCH_CHIP_STM32F100RE) -# define STM32_NFSMC 0 /* FSMC */ -# define STM32_NATIM 1 /* One advanced timer TIM1 */ -# define STM32_NGTIM 4 /* 16-bit general timers TIM2-5 with DMA */ -# define STM32_NGTIMNDMA 0 /* No 16-bit general timers without DMA */ -# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 */ - -/* TODO: there are also 6 additional timers (12-17) - * that don't fit any existing category - */ - -# define STM32_NDMA 2 /* DMA1-2 */ -# define STM32_NSPI 3 /* SPI1-3 */ -# define STM32_NI2S 0 /* No I2S */ -# define STM32_NUSART 5 /* USART1-5 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 2 /* I2C1-2 */ -# define STM32_NCAN 0 /* No CAN */ -# define STM32_NSDIO 0 /* No SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 0 /* No USB OTG FS/HS */ -# define STM32_NGPIO 64 /* GPIOA-D */ -# define STM32_NADC 1 /* ADC1 */ -# define STM32_NDAC 2 /* DAC 1, 2 channels */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC1 */ -# define STM32_NETHERNET 0 /* No Ethernet */ -# define STM32_NRNG 0 /* No random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F100VC) || defined(CONFIG_ARCH_CHIP_STM32F100VD) \ - || defined(CONFIG_ARCH_CHIP_STM32F100VE) -# define STM32_NFSMC 1 /* FSMC */ -# define STM32_NATIM 1 /* One advanced timer TIM1 */ -# define STM32_NGTIM 4 /* 16-bit general timers TIM2-5 with DMA */ -# define STM32_NGTIMNDMA 0 /* No 16-bit general timers without DMA */ -# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 */ - -/* TODO: there are also 6 additional timers (12-17) - * that don't fit any existing category - */ - -# define STM32_NDMA 2 /* DMA1-2 */ -# define STM32_NSPI 3 /* SPI1-3 */ -# define STM32_NI2S 0 /* No I2S */ -# define STM32_NUSART 5 /* USART1-5 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 2 /* I2C1-2 */ -# define STM32_NCAN 0 /* No CAN */ -# define STM32_NSDIO 0 /* No SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 0 /* No USB OTG FS/HS */ -# define STM32_NGPIO 80 /* GPIOA-E */ -# define STM32_NADC 1 /* ADC1 */ -# define STM32_NDAC 2 /* DAC 1, 2 channels */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC1 */ -# define STM32_NETHERNET 0 /* No Ethernet */ -# define STM32_NRNG 0 /* No random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -/* STM32 F102x8/102xB Medium Density USB Access Family **********************/ - -#elif defined(CONFIG_ARCH_CHIP_STM32F102CB) -# define STM32_NFSMC 1 /* FSMC */ -# define STM32_NATIM 0 /* No advanced timer TIM1 */ -# define STM32_NGTIM 3 /* 16-bit general timers TIM2-4 */ -# define STM32_NGTIMNDMA 0 /* No 16-bit general timers without DMA */ -# define STM32_NBTIM 0 /* No basic timers */ -# define STM32_NDMA 1 /* DMA */ -# define STM32_NSPI 2 /* SPI1-2 */ -# define STM32_NI2S 0 /* No I2S */ -# define STM32_NUSART 3 /* USART1-3 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 2 /* I2C1-2 */ -# define STM32_NCAN 0 /* No CAN */ -# define STM32_NSDIO 0 /* No SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 0 /* No USB OTG FS/HS */ -# define STM32_NGPIO 37 /* GPIOA-D */ -# define STM32_NADC 1 /* ADC1 */ -# define STM32_NDAC 0 /* No DAC */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC1 */ -# define STM32_NETHERNET 0 /* No ethernet */ -# define STM32_NRNG 0 /* No random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -/* STM32 F103 Low Density Family ********************************************/ - -/* STM32F103C4 & STM32F103C6 */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F103C4) -# define STM32_NFSMC 0 /* FSMC */ -# define STM32_NATIM 1 /* One advanced timer TIM1 */ -# define STM32_NGTIM 2 /* General timers TIM2,3 */ -# define STM32_NGTIMNDMA 0 /* No 16-bit general timers without DMA */ -# define STM32_NBTIM 0 /* No basic timer */ -# define STM32_NDMA 1 /* DMA1 */ -# define STM32_NSPI 1 /* SPI1 */ -# define STM32_NI2S 0 /* No I2S */ -# define STM32_NUSART 2 /* USART1-2 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 1 /* I2C1 */ -# define STM32_NCAN 1 /* bxCAN1 */ -# define STM32_NSDIO 0 /* No SDIO */ -# define STM32_NUSBOTG 0 /* No USB OTG FS/HS */ -# define STM32_NGPIO 37 /* GPIOA-C */ -# define STM32_NADC 2 /* ADC1-2 */ -# define STM32_NDAC 0 /* No DAC */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 0 /* No Ethernet */ -# define STM32_NRNG 0 /* No random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -/* STM32 F103 Medium Density Performance Line *******************************/ - -#elif defined(CONFIG_ARCH_CHIP_STM32F103T8) || defined(CONFIG_ARCH_CHIP_STM32F103TB) -# define STM32_NFSMC 0 /* No FSMC */ -# define STM32_NATIM 1 /* One advanced timer TIM1 */ -# define STM32_NGTIM 3 /* General timers TIM2-4 */ -# define STM32_NGTIMNDMA 0 /* No 16-bit general timers without DMA */ -# define STM32_NBTIM 0 /* No basic timers */ -# define STM32_NDMA 1 /* DMA1, 7 channels */ -# define STM32_NSPI 1 /* SPI1 */ -# define STM32_NI2S 0 /* No I2S */ -# define STM32_NUSART 2 /* USART1-2 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 1 /* I2C1 */ -# define STM32_NCAN 1 /* bxCAN1 */ -# define STM32_NSDIO 0 /* No SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 0 /* No USB OTG FS/HS */ -# define STM32_NGPIO 26 /* GPIOA-E */ -# define STM32_NADC 2 /* ADC1-2 */ -# define STM32_NDAC 0 /* No DAC */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 0 /* No Ethernet */ -# define STM32_NRNG 0 /* No random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F103C8) || defined(CONFIG_ARCH_CHIP_STM32F103CB) -# define STM32_NFSMC 0 /* No FSMC */ -# define STM32_NATIM 1 /* One advanced timer TIM1 */ -# define STM32_NGTIM 3 /* General timers TIM2-4 */ -# define STM32_NGTIMNDMA 0 /* No 16-bit general timers without DMA */ -# define STM32_NBTIM 0 /* No basic timers */ -# define STM32_NDMA 1 /* DMA1, 7 channels */ -# define STM32_NSPI 2 /* SPI1-2 */ -# define STM32_NI2S 0 /* No I2S */ -# define STM32_NUSART 3 /* USART1-3 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 2 /* I2C1-2 */ -# define STM32_NCAN 1 /* bxCAN1 */ -# define STM32_NSDIO 0 /* No SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 0 /* No USB OTG FS/HS */ -# define STM32_NGPIO 37 /* GPIOA-C */ -# define STM32_NADC 2 /* ADC1-2 */ -# define STM32_NDAC 0 /* No DAC */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 0 /* No Ethernet */ -# define STM32_NRNG 0 /* No random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F103R8) || defined(CONFIG_ARCH_CHIP_STM32F103RB) -# define STM32_NFSMC 0 /* No FSMC */ -# define STM32_NATIM 1 /* One advanced timer TIM1 */ -# define STM32_NGTIM 3 /* General timers TIM2-4 */ -# define STM32_NGTIMNDMA 0 /* No 16-bit general timers without DMA */ -# define STM32_NBTIM 0 /* No basic timers */ -# define STM32_NDMA 1 /* DMA1, 7 channels */ -# define STM32_NSPI 2 /* SPI1-2 */ -# define STM32_NI2S 0 /* No I2S */ -# define STM32_NUSART 3 /* USART1-3 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 2 /* I2C1-2 */ -# define STM32_NCAN 1 /* bxCAN1 */ -# define STM32_NSDIO 0 /* No SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 0 /* No USB OTG FS/HS */ -# define STM32_NGPIO 51 /* GPIOA-E */ -# define STM32_NADC 2 /* ADC1-2 */ -# define STM32_NDAC 0 /* No DAC */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 0 /* No Ethernet */ -# define STM32_NRNG 0 /* No random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -/* STM32 F103 High Density Family *******************************************/ - -/* STM32F103RC, STM32F103RD, and STM32F103RE are all provided in 64 pin - * packages and differ only in the available FLASH and SRAM. - */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F103RC) || defined(CONFIG_ARCH_CHIP_STM32F103RD) || \ - defined(CONFIG_ARCH_CHIP_STM32F103RE) || defined(CONFIG_ARCH_CHIP_STM32F103RG) -# define STM32_NFSMC 1 /* FSMC */ -# define STM32_NATIM 2 /* Two advanced timers TIM1 and TIM8 */ -# define STM32_NGTIM 4 /* 16-bit general timers TIM2-5 with DMA */ -# define STM32_NGTIMNDMA 0 /* No 16-bit general timers without DMA */ -# define STM32_NBTIM 2 /* Two basic timers TIM6 and TIM7 */ -# define STM32_NDMA 2 /* DMA1-2 */ -# define STM32_NSPI 3 /* SPI1-3 */ -# define STM32_NI2S 0 /* No I2S (?) */ -# define STM32_NUSART 5 /* USART1-5 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 2 /* I2C1-2 */ -# define STM32_NCAN 1 /* CAN1 */ -# define STM32_NSDIO 1 /* SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 0 /* No USB OTG FS/HS */ -# define STM32_NGPIO 51 /* GPIOA-D */ -# define STM32_NADC 2 /* ADC1-2 */ -# define STM32_NDAC 2 /* DAC1, 2 channels */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 0 /* No Ethernet */ -# define STM32_NRNG 0 /* No random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -/* STM32F103VC, STM32F103VD, and STM32F103VE are all provided in 100 pin - * packages and differ only in the available FLASH and SRAM. - */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F103VC) || defined(CONFIG_ARCH_CHIP_STM32F103VE) -# define STM32_NFSMC 1 /* FSMC */ -# define STM32_NATIM 2 /* Two advanced timers TIM1 and TIM8 */ -# define STM32_NGTIM 4 /* General timers TIM2-5 */ -# define STM32_NGTIMNDMA 0 /* No 16-bit general timers without DMA */ -# define STM32_NBTIM 2 /* Two basic timers TIM6 and TIM7 */ -# define STM32_NDMA 2 /* DMA1-2 */ -# define STM32_NSPI 3 /* SPI1-3 */ -# define STM32_NI2S 0 /* No I2S (?) */ -# define STM32_NUSART 5 /* USART1-5 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 2 /* I2C1-2 */ -# define STM32_NCAN 1 /* bxCAN1 */ -# define STM32_NSDIO 1 /* SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 0 /* No USB OTG FS/HS */ -# define STM32_NGPIO 80 /* GPIOA-E */ -# define STM32_NADC 3 /* ADC1-3 */ -# define STM32_NDAC 2 /* DAC1, 2 channels */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 0 /* No Ethernet */ -# define STM32_NRNG 0 /* No random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -/* STM32F103ZC, STM32F103ZD, and STM32F103ZE are all provided in 144 pin - * packages and differ only in the available FLASH and SRAM. - */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F103ZE) -# define STM32_NFSMC 1 /* FSMC */ -# define STM32_NATIM 1 /* One advanced timer TIM1 */ -# define STM32_NGTIM 4 /* 16-bit general timers TIM2-5 with DMA */ -# define STM32_NGTIMNDMA 0 /* No 16-bit general timers without DMA */ -# define STM32_NBTIM 0 /* No basic timers */ -# define STM32_NDMA 2 /* DMA1-2 */ -# define STM32_NSPI 3 /* SPI1-3 */ -# define STM32_NI2S 0 /* No I2S (?) */ -# define STM32_NUSART 3 /* USART1-3 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 2 /* I2C1-2 */ -# define STM32_NCAN 1 /* CAN1 */ -# define STM32_NSDIO 1 /* SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 0 /* No USB OTG FS/HS */ -# define STM32_NGPIO 112 /* GPIOA-G */ -# define STM32_NADC 1 /* ADC1 */ -# define STM32_NDAC 0 /* No DAC */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 0 /* No CRC */ -# define STM32_NETHERNET 0 /* No Ethernet */ -# define STM32_NRNG 0 /* No random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -/* STM32 F105/F107 Connectivity Line ****************************************/ - -#elif defined(CONFIG_ARCH_CHIP_STM32F105VB) -# define STM32_NFSMC 1 /* FSMC */ -# define STM32_NATIM 1 /* One advanced timers TIM1 */ -# define STM32_NGTIM 4 /* 16-bit general timers TIM2-5 with DMA */ -# define STM32_NGTIMNDMA 0 /* No 16-bit general timers without DMA */ -# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ -# define STM32_NDMA 2 /* DMA1-2 */ -# define STM32_NSPI 3 /* SPI1-3 */ -# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ -# define STM32_NUSART 5 /* USART1-3, UART 4-5 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 2 /* I2C1-2 */ -# define STM32_NCAN 2 /* CAN1-2 */ -# define STM32_NSDIO 0 /* No SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ -# define STM32_NGPIO 80 /* GPIOA-E */ -# define STM32_NADC 2 /* ADC1-2 */ -# define STM32_NDAC 2 /* DAC1, 2 channels */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 0 /* 100/100 Ethernet MAC */ -# define STM32_NRNG 0 /* No random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F105RB) -# define STM32_NFSMC 1 /* FSMC */ -# define STM32_NATIM 1 /* One advanced timers TIM1 */ -# define STM32_NGTIM 4 /* 16-bit general timers TIM2-5 with DMA */ -# define STM32_NGTIMNDMA 0 /* No 16-bit general timers without DMA */ -# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ -# define STM32_NDMA 2 /* DMA1-2 */ -# define STM32_NSPI 3 /* SPI1-3 */ -# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ -# define STM32_NUSART 5 /* USART1-3, UART 4-5 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 2 /* I2C1-2 */ -# define STM32_NCAN 2 /* CAN1-2 */ -# define STM32_NSDIO 0 /* No SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ -# define STM32_NGPIO 51 /* GPIOA-E */ -# define STM32_NADC 2 /* ADC1-2 */ -# define STM32_NDAC 2 /* DAC1, 2 channels */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 0 /* 100/100 Ethernet MAC */ -# define STM32_NRNG 0 /* No random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F107VC) -# define STM32_NFSMC 1 /* FSMC */ -# define STM32_NATIM 1 /* One advanced timers TIM1 */ -# define STM32_NGTIM 4 /* 16-bit general timers TIM2-5 with DMA */ -# define STM32_NGTIMNDMA 0 /* No 16-bit general timers without DMA */ -# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ -# define STM32_NDMA 2 /* DMA1-2 */ -# define STM32_NSPI 3 /* SPI1-3 */ -# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ -# define STM32_NUSART 5 /* USART1-3, UART 4-5 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 1 /* I2C1 */ -# define STM32_NCAN 2 /* CAN1-2 */ -# define STM32_NSDIO 0 /* No SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 0 /* No USB OTG FS/HS */ -# define STM32_NGPIO 80 /* GPIOA-E */ -# define STM32_NADC 2 /* ADC1-2*/ -# define STM32_NDAC 2 /* DAC1, 2 channels */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */ -# define STM32_NRNG 0 /* No random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -/* STM32 F2 Family **********************************************************/ - -#elif defined(CONFIG_ARCH_CHIP_STM32F205RG) /* UFBGA-176 1024Kb FLASH 128Kb SRAM */ -# define STM32_NFSMC 0 /* No FSMC */ -# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ -# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA - * 32-bit general timers TIM2 and 5 with DMA */ -# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ -# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ -# define STM32_NDMA 2 /* DMA1-2 */ -# define STM32_NSPI 3 /* SPI1-3 */ -# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ -# define STM32_NUSART 6 /* USART1-3 and 6, UART 4-5 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 3 /* I2C1-3 */ -# define STM32_NCAN 2 /* CAN1-2 */ -# define STM32_NSDIO 1 /* SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ -# define STM32_NGPIO 51 /* GPIOA-I */ -# define STM32_NADC 3 /* 12-bit ADC1-3, 16 channels */ -# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 0 /* No Ethernet MAC */ -# define STM32_NRNG 1 /* Random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F207VC) || defined(CONFIG_ARCH_CHIP_STM32F207VE) || \ - defined(CONFIG_ARCH_CHIP_STM32F207VF) || defined(CONFIG_ARCH_CHIP_STM32F207VG) -# define STM32_NFSMC 1 /* FSMC */ -# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ -# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA - * 32-bit general timers TIM2 and 5 with DMA */ -# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ -# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ -# define STM32_NDMA 2 /* DMA1-2 */ -# define STM32_NSPI 3 /* SPI1-3 */ -# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ -# define STM32_NUSART 6 /* USART1-3 and 6, UART 4-5 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 3 /* I2C1-3 */ -# define STM32_NCAN 2 /* CAN1-2 */ -# define STM32_NSDIO 1 /* SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ -# define STM32_NGPIO 82 /* GPIOA-I */ -# define STM32_NADC 3 /* 12-bit ADC1-3, 24 channels */ -# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */ -# define STM32_NRNG 1 /* Random number generator (RNG) */ -# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F207IC) || defined(CONFIG_ARCH_CHIP_STM32F207IE) || \ - defined(CONFIG_ARCH_CHIP_STM32F207IF) || defined(CONFIG_ARCH_CHIP_STM32F207IG) -# define STM32_NFSMC 1 /* FSMC */ -# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ -# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA - * 32-bit general timers TIM2 and 5 with DMA */ -# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ -# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ -# define STM32_NDMA 2 /* DMA1-2 */ -# define STM32_NSPI 3 /* SPI1-3 */ -# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ -# define STM32_NUSART 6 /* USART1-3 and 6, UART 4-5 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 3 /* I2C1-3 */ -# define STM32_NCAN 2 /* CAN1-2 */ -# define STM32_NSDIO 1 /* SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ -# define STM32_NGPIO 140 /* GPIOA-I */ -# define STM32_NADC 3 /* 12-bit ADC1-3, 24 channels */ -# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */ -# define STM32_NRNG 1 /* Random number generator (RNG) */ -# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F207ZC) || defined(CONFIG_ARCH_CHIP_STM32F207ZE) || \ - defined(CONFIG_ARCH_CHIP_STM32F207ZF) || defined(CONFIG_ARCH_CHIP_STM32F207ZG) -# define STM32_NFSMC 1 /* FSMC */ -# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ -# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA - * 32-bit general timers TIM2 and 5 with DMA */ -# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ -# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ -# define STM32_NDMA 2 /* DMA1-2 */ -# define STM32_NSPI 3 /* SPI1-3 */ -# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ -# define STM32_NUSART 6 /* USART1-3 and 6, UART 4-5 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 3 /* I2C1-3 */ -# define STM32_NCAN 2 /* CAN1-2 */ -# define STM32_NSDIO 1 /* SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ -# define STM32_NGPIO 114 /* GPIOA-I */ -# define STM32_NADC 3 /* 12-bit ADC1-3, 24 channels */ -# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */ -# define STM32_NRNG 1 /* Random number generator (RNG) */ -# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */ - -/* STM23 F3 Family **********************************************************/ - -/* Part Numbering: STM32Fssscfxxx - * - * Where - * sss = 302/303, 334 or 372/373 - * c = C (48pins) R (68 pins) V (100 pins) - * c = K (32 pins), C (48 pins), R (68 pins), V (100 pins) - * f = 6 (32KB FLASH), 8 (64KB FLASH), B (128KB FLASH), C (256KB FLASH) - * xxx = Package, temperature range, options (ignored here) - */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F302K6) || defined(CONFIG_ARCH_CHIP_STM32F302K8) -# define STM32_NFSMC 0 /* No FSMC */ -# define STM32_NATIM 1 /* (1) Advanced 16-bit timers with DMA: TIM1 (no TIM8) */ -# define STM32_NGTIM 6 /* (2) 16-bit general timers with DMA: TIM3 and TIM4 - * (1) 32-bit general timers with DMA: TIM2 - * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ -# define STM32_NGTIMNDMA 0 /* All timers have DMA */ - -# define STM32_NBTIM 1 /* (1) Basic timers: TIM6 (no TIM7) */ -# define STM32_NDMA 1 /* (1) DMA1 (7 channels) */ -# define STM32_NSPI 2 /* (3) SPI1-3 */ -# define STM32_NI2S 0 /* (0) No I2S */ -# define STM32_NUSART 2 /* (2) USART1-2, no UARTs */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 3 /* (3) I2C1-3 */ -# define STM32_NCAN 1 /* (1) CAN1 */ -# define STM32_NSDIO 0 /* (0) No SDIO */ -# define STM32_NLCD 0 /* (0) No LCD */ -# define STM32_NUSBOTG 0 /* USB FS device, but no USB OTG FS/HS */ -# define STM32_NGPIO 24 /* GPIOA-F */ -# define STM32_NADC 1 /* (1) 12-bit ADC1 */ -# define STM32_NDAC 1 /* (1) 12-bit DAC1, 1 channel */ -# define STM32_NCMP 2 /* (2) Ultra-fast analog comparators: COMP2 and COMP4 */ -# define STM32_NPGA 1 /* (1) Operational amplifiers: OPAMP */ -# define STM32_NCAPSENSE 13 /* (13) Capacitive sensing channels */ -# define STM32_NCRC 1 /* (1) CRC calculation unit */ -# define STM32_NETHERNET 0 /* (0) No Ethernet MAC */ -# define STM32_NRNG 0 /* (0) No random number generator (RNG) */ -# define STM32_NDCMI 0 /* (0) No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F302C6) || defined(CONFIG_ARCH_CHIP_STM32F302C8) -# define STM32_NFSMC 0 /* No FSMC */ -# define STM32_NATIM 1 /* (1) Advanced 16-bit timers with DMA: TIM1 (no TIM8) */ -# define STM32_NGTIM 6 /* (2) 16-bit general timers with DMA: TIM3 and TIM4 - * (1) 32-bit general timers with DMA: TIM2 - * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ -# define STM32_NGTIMNDMA 0 /* All timers have DMA */ - -# define STM32_NBTIM 1 /* (1) Basic timers: TIM6 (no TIM7) */ -# define STM32_NDMA 1 /* (1) DMA1 (7 channels) */ -# define STM32_NSPI 2 /* (3) SPI1-3 */ -# define STM32_NI2S 0 /* (0) No I2S */ -# define STM32_NUSART 3 /* (3) USART1-3, no UARTs */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 3 /* (3) I2C1-3 */ -# define STM32_NCAN 1 /* (1) CAN1 */ -# define STM32_NSDIO 0 /* (0) No SDIO */ -# define STM32_NLCD 0 /* (0) No LCD */ -# define STM32_NUSBOTG 0 /* USB FS device, but no USB OTG FS/HS */ -# define STM32_NGPIO 37 /* GPIOA-F */ -# define STM32_NADC 1 /* (1) 12-bit ADC1 */ -# define STM32_NDAC 1 /* (1) 12-bit DAC1, 1 channel */ -# define STM32_NCMP 3 /* (3) Ultra-fast analog comparators: COMP2, COMP4 and COMP6*/ -# define STM32_NPGA 1 /* (1) Operational amplifiers: OPAMP */ -# define STM32_NCAPSENSE 17 /* (17) Capacitive sensing channels */ -# define STM32_NCRC 1 /* (1) CRC calculation unit */ -# define STM32_NETHERNET 0 /* (0) No Ethernet MAC */ -# define STM32_NRNG 0 /* (0) No random number generator (RNG) */ -# define STM32_NDCMI 0 /* (0) No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F302R6) || defined(CONFIG_ARCH_CHIP_STM32F302R8) -# define STM32_NFSMC 0 /* No FSMC */ -# define STM32_NATIM 1 /* (1) Advanced 16-bit timers with DMA: TIM1 (no TIM8) */ -# define STM32_NGTIM 6 /* (2) 16-bit general timers with DMA: TIM3 and TIM4 - * (1) 32-bit general timers with DMA: TIM2 - * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ -# define STM32_NGTIMNDMA 0 /* All timers have DMA */ - -# define STM32_NBTIM 1 /* (1) Basic timers: TIM6 (no TIM7) */ -# define STM32_NDMA 1 /* (1) DMA1 (7 channels) */ -# define STM32_NSPI 2 /* (3) SPI1-3 */ -# define STM32_NI2S 0 /* (0) No I2S */ -# define STM32_NUSART 3 /* (2) USART1-3, no UARTs */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 3 /* (3) I2C1-3 */ -# define STM32_NCAN 1 /* (1) CAN1 */ -# define STM32_NSDIO 0 /* (0) No SDIO */ -# define STM32_NLCD 0 /* (0) No LCD */ -# define STM32_NUSBOTG 0 /* USB FS device, but no USB OTG FS/HS */ -# define STM32_NGPIO 51 /* GPIOA-F */ -# define STM32_NADC 1 /* (1) 12-bit ADC1 */ -# define STM32_NDAC 1 /* (1) 12-bit DAC1, 1 channel */ -# define STM32_NCMP 3 /* (3) Ultra-fast analog comparators: COMP2, COMP4 and COMP6*/ -# define STM32_NPGA 1 /* (1) Operational amplifiers: OPAMP */ -# define STM32_NCAPSENSE 18 /* (18) Capacitive sensing channels */ -# define STM32_NCRC 1 /* (1) CRC calculation unit */ -# define STM32_NETHERNET 0 /* (0) No Ethernet MAC */ -# define STM32_NRNG 0 /* (0) No random number generator (RNG) */ -# define STM32_NDCMI 0 /* (0) No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F302CB) || defined(CONFIG_ARCH_CHIP_STM32F302CC) -# define STM32_NFSMC 0 /* No FSMC */ -# define STM32_NATIM 1 /* (1) Advanced 16-bit timers with DMA: TIM1 (no TIM8) */ -# define STM32_NGTIM 6 /* (2) 16-bit general timers with DMA: TIM3 and TIM4 - * (1) 32-bit general timers with DMA: TIM2 - * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ -# define STM32_NGTIMNDMA 0 /* All timers have DMA */ - -# define STM32_NBTIM 1 /* (1) Basic timers: TIM6 (no TIM7) */ -# define STM32_NDMA 2 /* (2) DMA1 (7 channels) and DMA2 (5 channels) */ -# define STM32_NSPI 3 /* (3) SPI1-3 */ -# define STM32_NI2S 0 /* (0) No I2S */ -# define STM32_NUSART 3 /* (3) No UART1-3, no UARTs */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 2 /* (2) I2C1-2 */ -# define STM32_NCAN 1 /* (1) CAN1 */ -# define STM32_NSDIO 0 /* (0) No SDIO */ -# define STM32_NLCD 0 /* (0) No LCD */ -# define STM32_NUSBOTG 0 /* USB FS device, but no USB OTG FS/HS */ -# define STM32_NGPIO 37 /* GPIOA-F */ -# define STM32_NADC 2 /* (2) 12-bit ADC1-2 */ -# define STM32_NDAC 1 /* (1) 12-bit DAC1, 1 channel */ -# define STM32_NCAPSENSE 0 /* (0) No capacitive sensing channels */ -# define STM32_NCRC 1 /* (1) CRC calculation unit */ -# define STM32_NETHERNET 0 /* (0) No Ethernet MAC */ -# define STM32_NRNG 0 /* (0) No random number generator (RNG) */ -# define STM32_NDCMI 0 /* (0) No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F302RB) || defined(CONFIG_ARCH_CHIP_STM32F302RC) -# define STM32_NFSMC 0 /* No FSMC */ -# define STM32_NATIM 1 /* (1) Advanced 16-bit timers with DMA: TIM1 (no TIM8) */ -# define STM32_NGTIM 6 /* (2) 16-bit general timers with DMA: TIM3 and TIM4 - * (1) 32-bit general timers with DMA: TIM2 - * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ -# define STM32_NGTIMNDMA 0 /* All timers have DMA */ - -# define STM32_NBTIM 1 /* (1) Basic timers: TIM6 (no TIM7) */ -# define STM32_NDMA 2 /* (2) DMA1 (7 channels) and DMA2 (5 channels) */ -# define STM32_NSPI 3 /* (3) SPI1-3 */ -# define STM32_NI2S 0 /* (0) No I2S */ -# define STM32_NUSART 5 /* (5) USART1-3, UART4-5 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 2 /* (2) I2C1-2 */ -# define STM32_NCAN 1 /* (1) CAN1 */ -# define STM32_NSDIO 0 /* (0) No SDIO */ -# define STM32_NLCD 0 /* (0) No LCD */ -# define STM32_NUSBOTG 0 /* USB FS device, but no USB OTG FS/HS */ -# define STM32_NGPIO 52 /* GPIOA-F */ -# define STM32_NADC 2 /* (2) 12-bit ADC1-2 */ -# define STM32_NDAC 1 /* (1) 12-bit DAC1, 1 channel */ -# define STM32_NCAPSENSE 0 /* (0) No capacitive sensing channels */ -# define STM32_NCRC 1 /* (1) CRC calculation unit */ -# define STM32_NETHERNET 0 /* (0) No Ethernet MAC */ -# define STM32_NRNG 0 /* (0) No random number generator (RNG) */ -# define STM32_NDCMI 0 /* (0) No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F302VB) || defined(CONFIG_ARCH_CHIP_STM32F302VC) -# define STM32_NFSMC 0 /* No FSMC */ -# define STM32_NATIM 1 /* (1) Advanced 16-bit timers with DMA: TIM1 (no TIM8) */ -# define STM32_NGTIM 6 /* (2) 16-bit general timers with DMA: TIM3 and TIM4 - * (1) 32-bit general timers with DMA: TIM2 - * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ -# define STM32_NGTIMNDMA 0 /* All timers have DMA */ - -# define STM32_NBTIM 1 /* (1) Basic timers: TIM6 (no TIM7) */ -# define STM32_NDMA 2 /* (2) DMA1 (7 channels) and DMA2 (5 channels) */ -# define STM32_NSPI 3 /* (3) SPI1-3 */ -# define STM32_NI2S 0 /* (0) No I2S */ -# define STM32_NUSART 5 /* (5) USART1-3, UART4-5 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 2 /* (2) I2C1-2 */ -# define STM32_NCAN 1 /* (1) CAN1 */ -# define STM32_NSDIO 0 /* (0) No SDIO */ -# define STM32_NLCD 0 /* (0) No LCD */ -# define STM32_NUSBOTG 0 /* USB FS device, but no USB OTG FS/HS */ -# define STM32_NGPIO 87 /* GPIOA-F */ -# define STM32_NADC 2 /* (2) 12-bit ADC1-2 */ -# define STM32_NDAC 1 /* (1) 12-bit DAC1, 1 channel */ -# define STM32_NCAPSENSE 0 /* (0) No capacitive sensing channels */ -# define STM32_NCRC 1 /* (1) CRC calculation unit */ -# define STM32_NETHERNET 0 /* (0) No Ethernet MAC */ -# define STM32_NRNG 0 /* (0) No random number generator (RNG) */ -# define STM32_NDCMI 0 /* (0) No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F303K6) || defined(CONFIG_ARCH_CHIP_STM32F303K8) -# define STM32_NFSMC 0 /* No FSMC */ -# define STM32_NATIM 1 /* (1) Advanced 16-bit timers with DMA: TIM1 */ -# define STM32_NGTIM 5 /* (1) 16-bit general timers with DMA: TIM3 - * (1) 32-bit general timers with DMA: TIM2 - * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ -# define STM32_NGTIMNDMA 0 /* All timers have DMA */ -# define STM32_NBTIM 2 /* (2) Basic timers: TIM6 and TIM7 */ -# define STM32_NDMA 1 /* (1) DMA1 (7 channels) */ -# define STM32_NSPI 1 /* (1) SPI1 */ -# define STM32_NI2S 0 /* (0) No I2S */ -# define STM32_NUSART 2 /* (2) USART1-2, no UARTs */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 1 /* (1) I2C1 */ -# define STM32_NCAN 1 /* (1) CAN1 */ -# define STM32_NSDIO 0 /* (0) No SDIO */ -# define STM32_NLCD 0 /* (0) No LCD */ -# define STM32_NUSBOTG 0 /* No USB OTG FS/HS */ -# define STM32_NGPIO 25 /* GPIOA-F */ -# define STM32_NADC 2 /* (2) 12-bit ADC1-2 */ -# define STM32_NDAC 3 /* (3) 12-bit DAC1-2, 3 channels */ -# define STM32_NCAPSENSE 0 /* (0) No capacitive sensing channels */ -# define STM32_NCRC 1 /* (1) CRC calculation unit */ -# define STM32_NETHERNET 0 /* (0) No Ethernet MAC */ -# define STM32_NRNG 0 /* (0) No random number generator (RNG) */ -# define STM32_NDCMI 0 /* (0) No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F303C6) || defined(CONFIG_ARCH_CHIP_STM32F303C8) -# define STM32_NFSMC 0 /* No FSMC */ -# define STM32_NATIM 1 /* (1) Advanced 16-bit timers with DMA: TIM1 */ -# define STM32_NGTIM 5 /* (1) 16-bit general timers with DMA: TIM3 - * (1) 32-bit general timers with DMA: TIM2 - * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ -# define STM32_NGTIMNDMA 0 /* All timers have DMA */ -# define STM32_NBTIM 2 /* (2) Basic timers: TIM6 and TIM7 */ -# define STM32_NDMA 1 /* (1) DMA1 (7 channels) */ -# define STM32_NSPI 1 /* (1) SPI1 */ -# define STM32_NI2S 0 /* (0) No I2S */ -# define STM32_NUSART 3 /* (3) USART1-3, no UARTs */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 1 /* (1) I2C1 */ -# define STM32_NCAN 1 /* (1) CAN1 */ -# define STM32_NSDIO 0 /* (0) No SDIO */ -# define STM32_NLCD 0 /* (0) No LCD */ -# define STM32_NUSBOTG 0 /* No USB OTG FS/HS */ -# define STM32_NGPIO 37 /* GPIOA-F */ -# define STM32_NADC 2 /* (2) 12-bit ADC1-2 */ -# define STM32_NDAC 3 /* (3) 12-bit DAC1-2, 3 channels */ -# define STM32_NCAPSENSE 0 /* (0) No capacitive sensing channels */ -# define STM32_NCRC 1 /* (1) CRC calculation unit */ -# define STM32_NETHERNET 0 /* (0) No Ethernet MAC */ -# define STM32_NRNG 0 /* (0) No random number generator (RNG) */ -# define STM32_NDCMI 0 /* (0) No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F303CB) || defined(CONFIG_ARCH_CHIP_STM32F303CC) -# define STM32_NFSMC 0 /* No FSMC */ -# define STM32_NATIM 2 /* (2) Advanced 16-bit timers with DMA: TIM1 and TIM8 */ -# define STM32_NGTIM 6 /* (2) 16-bit general timers with DMA: TIM3 and TIM4 - * (1) 32-bit general timers with DMA: TIM2 - * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ -# define STM32_NGTIMNDMA 0 /* All timers have DMA */ -# define STM32_NBTIM 2 /* (2) Basic timers: TIM6 and TIM7 */ -# define STM32_NDMA 2 /* (2) DMA1 (7 channels) and DMA2 (5 channels) */ -# define STM32_NSPI 3 /* (3) SPI1-3 */ -# define STM32_NI2S 2 /* (2) I2S1-2 (multiplexed with SPI2-3) */ -# define STM32_NUSART 3 /* (3) No UART1-3, no UARTs */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 2 /* (2) I2C1-2 */ -# define STM32_NCAN 1 /* (1) CAN1 */ -# define STM32_NSDIO 0 /* (0) No SDIO */ -# define STM32_NLCD 0 /* (0) No LCD */ -# define STM32_NUSBOTG 0 /* USB FS device, but no USB OTG FS/HS */ -# define STM32_NGPIO 37 /* GPIOA-F */ -# define STM32_NADC 4 /* (3) 12-bit ADC1-4 */ -# define STM32_NDAC 2 /* (2) 12-bit DAC1, 2 channels */ -# define STM32_NCAPSENSE 0 /* (0) No capacitive sensing channels */ -# define STM32_NCRC 1 /* (1) CRC calculation unit */ -# define STM32_NETHERNET 0 /* (0) No Ethernet MAC */ -# define STM32_NRNG 0 /* (0) No random number generator (RNG) */ -# define STM32_NDCMI 0 /* (0) No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F303RB) || defined(CONFIG_ARCH_CHIP_STM32F303RC) -# define STM32_NFSMC 0 /* No FSMC */ -# define STM32_NATIM 2 /* (2) Advanced 16-bit timers with DMA: TIM1 and TIM8 */ -# define STM32_NGTIM 6 /* (2) 16-bit general timers with DMA: TIM3 and TIM4 - * (1) 32-bit general timers with DMA: TIM2 - * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ -# define STM32_NGTIMNDMA 0 /* All timers have DMA */ -# define STM32_NBTIM 2 /* (2) Basic timers: TIM6 and TIM7 */ -# define STM32_NDMA 2 /* (2) DMA1 (7 channels) and DMA2 (5 channels) */ -# define STM32_NSPI 3 /* (3) SPI1-3 */ -# define STM32_NI2S 2 /* (2) I2S1-2 (multiplexed with SPI2-3) */ -# define STM32_NUSART 5 /* (5) USART1-3, UART4-5 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 2 /* (2) I2C1-2 */ -# define STM32_NCAN 1 /* (1) CAN1 */ -# define STM32_NSDIO 0 /* (0) No SDIO */ -# define STM32_NLCD 0 /* (0) No LCD */ -# define STM32_NUSBOTG 0 /* USB FS device, but no USB OTG FS/HS */ -# define STM32_NGPIO 52 /* GPIOA-F */ -# define STM32_NADC 4 /* (3) 12-bit ADC1-4 */ -# define STM32_NDAC 2 /* (2) 12-bit DAC1, 2 channels */ -# define STM32_NCAPSENSE 0 /* (0) No capacitive sensing channels */ -# define STM32_NCRC 1 /* (1) CRC calculation unit */ -# define STM32_NETHERNET 0 /* (0) No Ethernet MAC */ -# define STM32_NRNG 0 /* (0) No random number generator (RNG) */ -# define STM32_NDCMI 0 /* (0) No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F303RD) || defined(CONFIG_ARCH_CHIP_STM32F303RE) -# define STM32_NFSMC 0 /* No FSMC */ -# define STM32_NATIM 2 /* (2) Advanced 16-bit timers with DMA: TIM1 and TIM8 */ -# define STM32_NGTIM 6 /* (2) 16-bit general timers with DMA: TIM3 and TIM4 - * (1) 32-bit general timers with DMA: TIM2 - * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ -# define STM32_NGTIMNDMA 0 /* All timers have DMA */ -# define STM32_NBTIM 2 /* (2) Basic timers: TIM6 and TIM7 */ -# define STM32_NDMA 2 /* (2) DMA1 (7 channels) and DMA2 (5 channels) */ -# define STM32_NSPI 4 /* (4) SPI1-4 */ -# define STM32_NI2S 2 /* (2) I2S1-2 (multiplexed with SPI2-3) */ -# define STM32_NUSART 5 /* (5) USART1-3, UART4-5 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 3 /* (2) I2C1-3 */ -# define STM32_NCAN 1 /* (1) CAN1 */ -# define STM32_NSDIO 0 /* (0) No SDIO */ -# define STM32_NLCD 0 /* (0) No LCD */ -# define STM32_NUSBOTG 0 /* USB FS device, but no USB OTG FS/HS */ -# define STM32_NGPIO 51 /* GPIOA-F */ -# define STM32_NADC 4 /* (4) 12-bit ADC1-4 */ -# define STM32_NDAC 2 /* (2) 12-bit DAC1, 2 channels */ -# define STM32_NCAPSENSE 0 /* (0) No capacitive sensing channels */ -# define STM32_NCRC 1 /* (1) CRC calculation unit */ -# define STM32_NETHERNET 0 /* (0) No Ethernet MAC */ -# define STM32_NRNG 0 /* (0) No random number generator (RNG) */ -# define STM32_NDCMI 0 /* (0) No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F303VB) || defined(CONFIG_ARCH_CHIP_STM32F303VC) -# define STM32_NFSMC 0 /* No FSMC */ -# define STM32_NATIM 2 /* (2) Advanced 16-bit timers with DMA: TIM1 and TIM8 */ -# define STM32_NGTIM 6 /* (2) 16-bit general timers with DMA: TIM3 and TIM4 - * (1) 32-bit general timers with DMA: TIM2 - * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ -# define STM32_NGTIMNDMA 0 /* All timers have DMA */ -# define STM32_NBTIM 2 /* (2) Basic timers: TIM6 and TIM7 */ -# define STM32_NDMA 2 /* (2) DMA1 (7 channels) and DMA2 (5 channels) */ -# define STM32_NSPI 3 /* (3) SPI1-3 */ -# define STM32_NI2S 2 /* (2) I2S1-2 (multiplexed with SPI2-3) */ -# define STM32_NUSART 5 /* (5) USART1-3, UART4-5 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 2 /* (2) I2C1-2 */ -# define STM32_NCAN 1 /* (1) CAN1 */ -# define STM32_NSDIO 0 /* (0) No SDIO */ -# define STM32_NLCD 0 /* (0) No LCD */ -# define STM32_NUSBOTG 0 /* USB FS device, but no USB OTG FS/HS */ -# define STM32_NGPIO 87 /* GPIOA-F */ -# define STM32_NADC 4 /* (3) 12-bit ADC1-4 */ -# define STM32_NDAC 2 /* (2) 12-bit DAC1, 2 channels */ -# define STM32_NCAPSENSE 0 /* (0) No capacitive sensing channels */ -# define STM32_NCRC 1 /* (1) CRC calculation unit */ -# define STM32_NETHERNET 0 /* (0) No Ethernet MAC */ -# define STM32_NRNG 0 /* (0) No random number generator (RNG) */ -# define STM32_NDCMI 0 /* (0) No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F303RD) || defined(CONFIG_ARCH_CHIP_STM32F303RE) -# define STM32_NFSMC 0 /* No FSMC */ -# define STM32_NATIM 2 /* (2) Advanced 16-bit timers with DMA: TIM1 and TIM8 */ -# define STM32_NGTIM 6 /* (5) 16-bit general timers - * (1) 32-bit general timers */ -# define STM32_NGTIMNDMA 0 /* All timers have DMA */ -# define STM32_NBTIM 2 /* (2) Basic timers: TIM6 and TIM7 */ -# define STM32_NDMA 2 /* (2) DMA1 (7 channels) and DMA2 (5 channels) */ -# define STM32_NSPI 4 /* (4) SPI1-4 */ -# define STM32_NI2S 2 /* (2) I2S1-2 (multiplexed with SPI2-3) */ -# define STM32_NUSART 5 /* (5) USART1-3, UART4-5 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 3 /* (3) I2C1-3 */ -# define STM32_NCAN 1 /* (1) CAN1 */ -# define STM32_NSDIO 0 /* (0) No SDIO */ -# define STM32_NLCD 0 /* (0) No LCD */ -# define STM32_NUSBOTG 0 /* USB FS device, but no USB OTG FS/HS */ -# define STM32_NGPIO 51 /* GPIOA-F */ -# define STM32_NADC 4 /* (4) 12-bit ADC1-4 */ -# define STM32_NDAC 2 /* (2) 12-bit DAC1, 2 channels */ -# define STM32_NCAPSENSE 18 /* (18) No capacitive sensing channels */ -# define STM32_NCRC 1 /* (1) CRC calculation unit */ -# define STM32_NETHERNET 0 /* (0) No Ethernet MAC */ -# define STM32_NRNG 0 /* (0) No random number generator (RNG) */ -# define STM32_NDCMI 0 /* (0) No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F303VD) || defined(CONFIG_ARCH_CHIP_STM32F303VE) -# define STM32_NFSMC 0 /* No FSMC */ -# define STM32_NATIM 3 /* (3) Advanced 16-bit timers with DMA: TIM1, TIM8 and TIM20 */ -# define STM32_NGTIM 6 /* (5) 16-bit general timers - * (1) 32-bit general timers */ -# define STM32_NGTIMNDMA 0 /* All timers have DMA */ -# define STM32_NBTIM 2 /* (2) Basic timers: TIM6 and TIM7 */ -# define STM32_NDMA 2 /* (2) DMA1 (7 channels) and DMA2 (5 channels) */ -# define STM32_NSPI 4 /* (4) SPI1-4 */ -# define STM32_NI2S 2 /* (2) I2S1-2 (multiplexed with SPI2-3) */ -# define STM32_NUSART 5 /* (5) USART1-3, UART4-5 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 3 /* (3) I2C1-3 */ -# define STM32_NCAN 1 /* (1) CAN1 */ -# define STM32_NSDIO 0 /* (0) No SDIO */ -# define STM32_NLCD 0 /* (0) No LCD */ -# define STM32_NUSBOTG 0 /* USB FS device, but no USB OTG FS/HS */ -# define STM32_NGPIO 84 /* GPIOA-F (depends on package) */ -# define STM32_NADC 4 /* (4) 12-bit ADC1-4 */ -# define STM32_NDAC 2 /* (2) 12-bit DAC1, 2 channels */ -# define STM32_NCAPSENSE 24 /* (24) No capacitive sensing channels */ -# define STM32_NCRC 1 /* (1) CRC calculation unit */ -# define STM32_NETHERNET 0 /* (0) No Ethernet MAC */ -# define STM32_NRNG 0 /* (0) No random number generator (RNG) */ -# define STM32_NDCMI 0 /* (0) No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F303ZD) || defined(CONFIG_ARCH_CHIP_STM32F303ZE) -# define STM32_NFSMC 0 /* No FSMC */ -# define STM32_NATIM 3 /* (3) Advanced 16-bit timers with DMA: TIM1, TIM8 and TIM20 */ -# define STM32_NGTIM 6 /* (5) 16-bit general timers - * (1) 32-bit general timers */ -# define STM32_NGTIMNDMA 0 /* All timers have DMA */ -# define STM32_NBTIM 2 /* (2) Basic timers: TIM6 and TIM7 */ -# define STM32_NDMA 2 /* (2) DMA1 (7 channels) and DMA2 (5 channels) */ -# define STM32_NSPI 4 /* (4) SPI1-4 */ -# define STM32_NI2S 2 /* (2) I2S1-2 (multiplexed with SPI2-3) */ -# define STM32_NUSART 5 /* (5) USART1-3, UART4-5 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 3 /* (3) I2C1-3 */ -# define STM32_NCAN 1 /* (1) CAN1 */ -# define STM32_NSDIO 0 /* (0) No SDIO */ -# define STM32_NLCD 0 /* (0) No LCD */ -# define STM32_NUSBOTG 0 /* USB FS device, but no USB OTG FS/HS */ -# define STM32_NGPIO 115 /* GPIOA-F */ -# define STM32_NADC 4 /* (4) 12-bit ADC1-4 */ -# define STM32_NDAC 2 /* (2) 12-bit DAC1, 2 channels */ -# define STM32_NCAPSENSE 24 /* (24) No capacitive sensing channels */ -# define STM32_NCRC 1 /* (1) CRC calculation unit */ -# define STM32_NETHERNET 0 /* (0) No Ethernet MAC */ -# define STM32_NRNG 0 /* (0) No random number generator (RNG) */ -# define STM32_NDCMI 0 /* (0) No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F334K4) || defined(CONFIG_ARCH_CHIP_STM32F334K6) || defined(CONFIG_ARCH_CHIP_STM32F334K8) -# define STM32_NFSMC 0 /* No FSMC */ -# define STM32_HRTIM 1 /* (1) High-resolution timer 16-bit, 10 channels: HRTIM1 */ -# define STM32_NATIM 1 /* (1) Advanced 16-bit timers with DMA: TIM1*/ -# define STM32_NGTIM 5 /* (1) 16-bit general timers with DMA: TIM3 - * (1) 32-bit general timers with DMA: TIM2 - * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ -# define STM32_NGTIMNDMA 0 /* All timers have DMA */ -# define STM32_NBTIM 2 /* (2) Basic timers: TIM6 and TIM7 */ -# define STM32_NDMA 1 /* (1) DMA1 (7 channels) */ -# define STM32_NSPI 1 /* (1) SPI1 */ -# define STM32_NI2S 0 /* (0) No I2S1 */ -# define STM32_NUSART 2 /* (2) USART1-2 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 1 /* (1) I2C1 */ -# define STM32_NCAN 1 /* (1) CAN1 */ -# define STM32_NSDIO 0 /* (0) No SDIO */ -# define STM32_NLCD 0 /* (0) No LCD */ -# define STM32_NUSBOTG 0 /* (0) No USB */ -# define STM32_NGPIO 25 /* GPIOA-F */ -# define STM32_NADC 2 /* (2) 12-bit ADC1-2 */ -# define STM32_NDAC 3 /* (3) 12-bit DAC1-2, 3 channels */ -# define STM32_NCMP 2 /* (2) Ultra-fast analog comparators: COMP2 and COMP4 */ -# define STM32_NPGA 1 /* (1) Operational amplifiers: OPAMP */ -# define STM32_NCAPSENSE 14 /* (14) Capacitive sensing channels */ -# define STM32_NCRC 1 /* (1) CRC calculation unit */ -# define STM32_NETHERNET 0 /* (0) No Ethernet MAC */ -# define STM32_NRNG 0 /* (0) No random number generator (RNG) */ -# define STM32_NDCMI 0 /* (0) No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F334C4) || defined(CONFIG_ARCH_CHIP_STM32F334C6) || defined(CONFIG_ARCH_CHIP_STM32F334C8) -# define STM32_NFSMC 0 /* No FSMC */ -# define STM32_HRTIM 1 /* (1) High-resolution timer 16-bit, 10 channels: HRTIM1 */ -# define STM32_NATIM 1 /* (1) Advanced 16-bit timers with DMA: TIM1*/ -# define STM32_NGTIM 5 /* (1) 16-bit general timers with DMA: TIM3 - * (1) 32-bit general timers with DMA: TIM2 - * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ -# define STM32_NGTIMNDMA 0 /* All timers have DMA */ -# define STM32_NBTIM 2 /* (2) Basic timers: TIM6 and TIM7 */ -# define STM32_NDMA 1 /* (1) DMA1 (7 channels) */ -# define STM32_NSPI 1 /* (1) SPI1 */ -# define STM32_NI2S 0 /* (0) No I2S1 */ -# define STM32_NUSART 3 /* (3) USART1-3 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 1 /* (1) I2C1 */ -# define STM32_NCAN 1 /* (1) CAN1 */ -# define STM32_NSDIO 0 /* (0) No SDIO */ -# define STM32_NLCD 0 /* (0) No LCD */ -# define STM32_NUSBOTG 0 /* (0) No USB */ -# define STM32_NGPIO 37 /* GPIOA-F */ -# define STM32_NADC 2 /* (2) 12-bit ADC1-2 */ -# define STM32_NDAC 3 /* (3) 12-bit DAC1-2, 3 channels */ -# define STM32_NCMP 3 /* (3) Ultra-fast analog comparators: COMP2, COMP4 and COMP6 */ -# define STM32_NPGA 1 /* (1) Operational amplifiers: OPAMP */ -# define STM32_NCAPSENSE 17 /* (17) Capacitive sensing channels */ -# define STM32_NCRC 1 /* (1) CRC calculation unit */ -# define STM32_NETHERNET 0 /* (0) No Ethernet MAC */ -# define STM32_NRNG 0 /* (0) No random number generator (RNG) */ -# define STM32_NDCMI 0 /* (0) No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F334R4) || defined(CONFIG_ARCH_CHIP_STM32F334R6) || defined(CONFIG_ARCH_CHIP_STM32F334R8) -# define STM32_NFSMC 0 /* No FSMC */ -# define STM32_HRTIM 1 /* (1) High-resolution timer 16-bit, 10 channels: HRTIM1 */ -# define STM32_NATIM 1 /* (1) Advanced 16-bit timers with DMA: TIM1*/ -# define STM32_NGTIM 5 /* (1) 16-bit general timers with DMA: TIM3 - * (1) 32-bit general timers with DMA: TIM2 - * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ -# define STM32_NGTIMNDMA 0 /* All timers have DMA */ -# define STM32_NBTIM 2 /* (2) Basic timers: TIM6 and TIM7 */ -# define STM32_NDMA 1 /* (1) DMA1 (7 channels) */ -# define STM32_NSPI 1 /* (1) SPI1 */ -# define STM32_NI2S 0 /* (0) No I2S1 */ -# define STM32_NUSART 3 /* (3) USART1-3 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 1 /* (1) I2C1 */ -# define STM32_NCAN 1 /* (1) CAN1 */ -# define STM32_NSDIO 0 /* (0) No SDIO */ -# define STM32_NLCD 0 /* (0) No LCD */ -# define STM32_NUSBOTG 0 /* (0) No USB */ -# define STM32_NGPIO 51 /* GPIOA-F */ -# define STM32_NADC 2 /* (2) 12-bit ADC1-2 */ -# define STM32_NDAC 3 /* (3) 12-bit DAC1-2, 3 channels */ -# define STM32_NCMP 3 /* (3) Ultra-fast analog comparators: COMP2, COMP4 and COMP6 */ -# define STM32_NPGA 1 /* (1) Operational amplifiers: OPAMP */ -# define STM32_NCAPSENSE 18 /* (18) Capacitive sensing channels */ -# define STM32_NCRC 1 /* (1) CRC calculation unit */ -# define STM32_NETHERNET 0 /* (0) No Ethernet MAC */ -# define STM32_NRNG 0 /* (0) No random number generator (RNG) */ -# define STM32_NDCMI 0 /* (0) No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F373C8) || defined(CONFIG_ARCH_CHIP_STM32F373CB) || defined(CONFIG_ARCH_CHIP_STM32F373CC) -# define STM32_NFSMC 0 /* No FSMC */ -# define STM32_NATIM 0 /* (0) Advanced 16-bit timers with DMA: */ -# define STM32_NGTIM 8 /* (3) 16-bit general timers with DMA: TIM3, TIM4 and TIM19 - * (2) 32-bit general timers with DMA: TIM2 and TIM5 - * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ -# define STM32_NGTIMNDMA 3 /* (3) 16-bit general timers count-up timers without DMA: TIM12-14 */ -# define STM32_NBTIM 3 /* (3) Basic timers: TIM6, TIM7 and TIM18 */ -# define STM32_NDMA 2 /* (2) DMA1 (7 channels) and DMA2 (5 channels) */ -# define STM32_NSPI 3 /* (3) SPI1-3 */ -# define STM32_NI2S 3 /* (3) I2S1-2 (multiplexed with SPI1-3) */ -# define STM32_NUSART 3 /* (3) USART1-3 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 2 /* (2) I2C1-2 */ -# define STM32_NCAN 1 /* (1) CAN1 */ -# define STM32_NSDIO 0 /* (0) No SDIO */ -# define STM32_NLCD 0 /* (0) No LCD */ -# define STM32_NUSBOTG 0 /* USB FS device, but no USB OTG FS/HS */ -# define STM32_NGPIO 87 /* GPIOA-F */ -# define STM32_NADC 1 /* (1) 12-bit ADC1 */ -# define STM32_NSDADC 3 /* (3) 16-bit SDADC1-3 */ -# define STM32_NDAC 3 /* (3) 12-bit DAC1-2, 3 channels */ -# define STM32_NCAPSENSE 0 /* (0) No capacitive sensing channels */ -# define STM32_NCRC 1 /* (1) CRC calculation unit */ -# define STM32_NETHERNET 0 /* (0) No Ethernet MAC */ -# define STM32_NRNG 0 /* (0) No random number generator (RNG) */ -# define STM32_NDCMI 0 /* (0) No digital camera interface (DCMI) */ - -/* STM23 F4 Family **********************************************************/ - -/* STM32F01xB/C Family Differences: - * - * PART PACKAGE FLASH SDIO ADC Channels - * ----------- ---------------- ----- ---- ------------ - * STM32F401CB WLCSP49/UFQFPN48 128Kb No 10 - * STM32F401RB LQFP64 128Kb Yes 16 - * STM32F401VB UFBGA100/LQFP100 128Kb Yes 16 - * STM32F401CC WLCSP49/UFQFPN48 256Kb No 10 - * STM32F401RC LQFP64 256Kb Yes 16 - * STM32F401VC UFBGA100/LQFP100 256Kb Yes 16 - */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F401CB) || defined(CONFIG_ARCH_CHIP_STM32F401RB) || \ - defined(CONFIG_ARCH_CHIP_STM32F401VB) || defined(CONFIG_ARCH_CHIP_STM32F401CC) || \ - defined(CONFIG_ARCH_CHIP_STM32F401RC) || defined(CONFIG_ARCH_CHIP_STM32F401VC) -# define STM32_NFSMC 0 /* No FSMC */ -# define STM32_NATIM 1 /* One advanced timers TIM1 */ -# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA - * 32-bit general timers TIM2 and 5 with DMA */ -# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */ -# define STM32_NBTIM 0 /* No basic timers */ -# define STM32_NDMA 2 /* DMA1-2 with 8 streams each*/ -# define STM32_NSPI 3 /* SPI1-3 */ -# define STM32_NI2S 2 /* I2S2-3 (multiplexed with SPI2-3) */ -# define STM32_NUSART 6 /* Actually only 3: USART1, 2 and 6 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 3 /* I2C1-3 */ -# define STM32_NCAN 0 /* No CAN */ -# if defined(CONFIG_ARCH_CHIP_STM32F401CB) || defined(CONFIG_ARCH_CHIP_STM32F401CC) -# define STM32_NSDIO 0 /* No SDIO interface */ -# else -# define STM32_NSDIO 1 /* One SDIO interface */ -# endif -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 1 /* USB OTG FS (only) */ -# define STM32_NGPIO 50 /* GPIOA-H */ -# define STM32_NADC 1 /* One 12-bit ADC1, 10 or 16 channels */ -# define STM32_NDAC 0 /* No DAC */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* No CRC */ -# define STM32_NETHERNET 0 /* No Ethernet MAC */ -# define STM32_NRNG 0 /* No Random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -/* STM32F01xD/E Family Differences: - * - * PART PACKAGE FLASH SDIO ADC Channels - * ----------- ---------------- ----- ---- ------------ - * STM32F401CD WLCSP49/UFQFPN48 384Kb No 10 - * STM32F401RD LQFP64 384Kb Yes 16 - * STM32F401VD UFBGA100/LQFP100 384Kb Yes 16 - * STM32F401CE WLCSP49/UFQFPN48 512Kb No 10 - * STM32F401RE LQFP64 512Kb Yes 16 - * STM32F401VE UFBGA100/LQFP100 512Kb Yes 16 - */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F401CD) || defined(CONFIG_ARCH_CHIP_STM32F401RD) || \ - defined(CONFIG_ARCH_CHIP_STM32F401VD) || defined(CONFIG_ARCH_CHIP_STM32F401CE) || \ - defined(CONFIG_ARCH_CHIP_STM32F401RE) || defined(CONFIG_ARCH_CHIP_STM32F401VE) -# define STM32_NFSMC 0 /* No FSMC */ -# define STM32_NATIM 1 /* One advanced timers TIM1 */ -# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA - * 32-bit general timers TIM2 and 5 with DMA */ -# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */ -# define STM32_NBTIM 0 /* No basic timers */ -# define STM32_NDMA 2 /* DMA1-2 with 8 streams each*/ -# define STM32_NSPI 4 /* SPI1-4 */ -# define STM32_NI2S 2 /* I2S2-3 (multiplexed with SPI2-3) */ -# define STM32_NUSART 6 /* Actually only 3: USART1, 2 and 6 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 3 /* I2C1-3 */ -# define STM32_NCAN 0 /* No CAN */ -# if defined(CONFIG_ARCH_CHIP_STM32F401CD) || defined(CONFIG_ARCH_CHIP_STM32F401CE) -# define STM32_NSDIO 0 /* No SDIO interface */ -# else -# define STM32_NSDIO 1 /* One SDIO interface */ -# endif -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 1 /* USB OTG FS (only) */ -# define STM32_NGPIO 50 /* GPIOA-H */ -# define STM32_NADC 1 /* One 12-bit ADC1, 10 or 16 channels */ -# define STM32_NDAC 0 /* No DAC */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* No CRC */ -# define STM32_NETHERNET 0 /* No Ethernet MAC */ -# define STM32_NRNG 0 /* No Random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F410RB) /* LQFP64 package, 512Kb FLASH, 96KiB SRAM */ -# define STM32_NFSMC 0 /* No FSMC */ -# define STM32_NATIM 1 /* One advanced timers TIM1 */ -# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA - * 32-bit general timers TIM2 and 5 with DMA */ -# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */ -# define STM32_NBTIM 0 /* No basic timers */ -# define STM32_NDMA 2 /* DMA1-2 with 8 streams each*/ -# define STM32_NSPI 3 /* SPI1-4 */ -# define STM32_NI2S 0 /* I2S1-2 (multiplexed with SPI2-3) */ -# define STM32_NUSART 3 /* Actually only 3: USART1, 2 and 6 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 3 /* I2C1-3 */ -# define STM32_NCAN 0 /* No CAN */ -# define STM32_NSDIO 0 /* One SDIO interface */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 0 /* USB OTG FS (only) */ -# define STM32_NGPIO 50 /* GPIOA-H */ -# define STM32_NADC 1 /* One 12-bit ADC1, 16 channels */ -# define STM32_NDAC 1 /* 12-bit DAC1, 1 channel */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* No CRC */ -# define STM32_NETHERNET 0 /* No Ethernet MAC */ -# define STM32_NRNG 1 /* No Random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F411CE) /* LQFP64 package, 512Kb FLASH, 128KiB SRAM */ -# define STM32_NFSMC 0 /* No FSMC */ -# define STM32_NATIM 1 /* One advanced timers TIM1 */ -# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA - * 32-bit general timers TIM2 and 5 with DMA */ -# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */ -# define STM32_NBTIM 0 /* No basic timers */ -# define STM32_NDMA 2 /* DMA1-2 with 8 streams each*/ -# define STM32_NSPI 5 /* SPI1-5 */ -# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ -# define STM32_NUSART 6 /* Actually only 3: USART1, 2 and 6 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 3 /* I2C1-3 */ -# define STM32_NCAN 0 /* No CAN */ -# define STM32_NSDIO 1 /* One SDIO interface */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 1 /* USB OTG FS (only) */ -# define STM32_NGPIO 50 /* GPIOA-H */ -# define STM32_NADC 1 /* One 12-bit ADC1, 16 channels */ -# define STM32_NDAC 0 /* No DAC */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* No CRC */ -# define STM32_NETHERNET 0 /* No Ethernet MAC */ -# define STM32_NRNG 0 /* No Random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F411RE) /* LQFP64 package, 512Kb FLASH, 128KiB SRAM */ -# define STM32_NFSMC 0 /* No FSMC */ -# define STM32_NATIM 1 /* One advanced timers TIM1 */ -# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA - * 32-bit general timers TIM2 and 5 with DMA */ -# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */ -# define STM32_NBTIM 0 /* No basic timers */ -# define STM32_NDMA 2 /* DMA1-2 with 8 streams each*/ -# define STM32_NSPI 5 /* SPI1-5 */ -# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ -# define STM32_NUSART 6 /* Actually only 3: USART1, 2 and 6 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 3 /* I2C1-3 */ -# define STM32_NCAN 0 /* No CAN */ -# define STM32_NSDIO 1 /* One SDIO interface */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 1 /* USB OTG FS (only) */ -# define STM32_NGPIO 50 /* GPIOA-H */ -# define STM32_NADC 1 /* One 12-bit ADC1, 16 channels */ -# define STM32_NDAC 0 /* No DAC */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* No CRC */ -# define STM32_NETHERNET 0 /* No Ethernet MAC */ -# define STM32_NRNG 0 /* No Random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F411VE) /* 100 pin LQFP/BGA package, 512Kb FLASH, 128KiB SRAM */ -# define STM32_NFSMC 0 /* No FSMC */ -# define STM32_NATIM 1 /* One advanced timers TIM1 */ -# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA - * 32-bit general timers TIM2 and 5 with DMA */ -# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */ -# define STM32_NBTIM 0 /* No basic timers */ -# define STM32_NDMA 2 /* DMA1-2 with 8 streams each*/ -# define STM32_NSPI 5 /* SPI1-5 */ -# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ -# define STM32_NUSART 6 /* Actually only 3: USART1, 2 and 6 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 3 /* I2C1-3 */ -# define STM32_NCAN 0 /* No CAN */ -# define STM32_NSDIO 1 /* One SDIO interface */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 1 /* USB OTG FS (only) */ -# define STM32_NGPIO 81 /* GPIOA-H */ -# define STM32_NADC 1 /* One 12-bit ADC1, 16 channels */ -# define STM32_NDAC 0 /* No DAC */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* No CRC */ -# define STM32_NETHERNET 0 /* No Ethernet MAC */ -# define STM32_NRNG 0 /* No Random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F412CE) /* UFQFPN48 package, 512Kb FLASH, 256KiB SRAM */ -# define STM32_NFSMC 1 /* FSMC */ -# define STM32_NATIM 2 /* Two advanced timers TIM1 and TIM8 */ -# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA - * 32-bit general timers TIM2 and 5 with DMA */ -# define STM32_NGTIMNDMA 4 /* 16-bit general timers 9, 12, 13, and 14 without DMA */ -# define STM32_NBTIM 0 /* 2 basic timers TIM6 and TIM7 */ -# define STM32_NDMA 2 /* DMA1-2 with 8 streams each*/ -# define STM32_NSPI 5 /* SPI1-5 */ -# define STM32_NI2S 3 /* I2S1-3 */ -# define STM32_NUSART 4 /* USART1, 2, 3 and 6 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 3 /* I2C1-3 */ -# define STM32_NCAN 2 /* 2 CAN */ -# define STM32_NSDIO 1 /* One SDIO interface */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 1 /* USB OTG FS (only) */ -# define STM32_NGPIO 34 /* GPIOA-B (sans PB11) and 3 Bits of C */ -# define STM32_NADC 1 /* One 12-bit ADC1, 16 channels */ -# define STM32_NDAC 0 /* No DAC */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 0 /* No Ethernet MAC */ -# define STM32_NRNG 1 /* Random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F412ZG) /* 144 pin LQFP package, 1MB FLASH, 256KiB SRAM */ -# define STM32_NFSMC 1 /* FSMC */ -# define STM32_NATIM 2 /* Two advanced timers TIM1 and TIM8 */ -# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA - * 32-bit general timers TIM2 and 5 with DMA */ -# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ -# define STM32_NBTIM 2 /* 2 basic timers TIM6 and TIM7 */ -# define STM32_NDMA 2 /* DMA1-2 with 8 streams each*/ -# define STM32_NSPI 5 /* SPI1-5 */ -# define STM32_NI2S 3 /* I2S1-3 */ -# define STM32_NUSART 6 /* USART1, 2, 3 and 6 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 3 /* I2C1-3 */ -# define STM32_NCAN 2 /* 2 CAN */ -# define STM32_NSDIO 1 /* One SDIO interface */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 1 /* USB OTG FS (only) */ -# define STM32_NGPIO 113 /* GPIOA-H */ -# define STM32_NADC 1 /* One 12-bit ADC1, 16 channels */ -# define STM32_NDAC 0 /* No DAC */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 0 /* No Ethernet MAC */ -# define STM32_NRNG 1 /* Random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F405RG) /* LQFP 64 10x10x1.4 1024Kb FLASH 192Kb SRAM */ -# define STM32_NFSMC 0 /* No FSMC */ -# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ -# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA - * 32-bit general timers TIM2 and 5 with DMA */ -# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ -# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ -# define STM32_NDMA 2 /* DMA1-2 */ -# define STM32_NSPI 3 /* SPI1-3 */ -# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ -# define STM32_NUSART 6 /* USART1-3 and 6, UART 4-5 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 3 /* I2C1-3 */ -# define STM32_NCAN 2 /* CAN1-2 */ -# define STM32_NSDIO 1 /* SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ -# define STM32_NGPIO 139 /* GPIOA-I */ -# define STM32_NADC 3 /* 12-bit ADC1-3, 16 channels */ -# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 0 /* No Ethernet MAC */ -# define STM32_NRNG 1 /* Random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F405VG) /* LQFP 100 14x14x1.4 1024Kb FLASH 192Kb SRAM */ -# define STM32_NFSMC 1 /* FSMC */ -# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ -# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA - * 32-bit general timers TIM2 and 5 with DMA */ -# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ -# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ -# define STM32_NDMA 2 /* DMA1-2 */ -# define STM32_NSPI 3 /* SPI1-3 */ -# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ -# define STM32_NUSART 6 /* USART1-3 and 6, UART 4-5 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 3 /* I2C1-3 */ -# define STM32_NCAN 2 /* CAN1-2 */ -# define STM32_NSDIO 1 /* SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ -# define STM32_NGPIO 139 /* GPIOA-I */ -# define STM32_NADC 3 /* 12-bit ADC1-3, 16 channels */ -# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 0 /* No Ethernet MAC */ -# define STM32_NRNG 1 /* Random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F405ZG) /* LQFP 144 20x20x1.4 1024Kb FLASH 192Kb SRAM */ -# define STM32_NFSMC 1 /* FSMC */ -# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ -# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA - * 32-bit general timers TIM2 and 5 with DMA */ -# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ -# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ -# define STM32_NDMA 2 /* DMA1-2 */ -# define STM32_NSPI 3 /* SPI1-3 */ -# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ -# define STM32_NUSART 6 /* USART1-3 and 6, UART 4-5 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 3 /* I2C1-3 */ -# define STM32_NCAN 2 /* CAN1-2 */ -# define STM32_NSDIO 1 /* SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ -# define STM32_NGPIO 139 /* GPIOA-I */ -# define STM32_NADC 3 /* 12-bit ADC1-3, 24 channels */ -# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 0 /* No Ethernet MAC */ -# define STM32_NRNG 1 /* Random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F407VE) /* LQFP-100 512Kb FLASH 192Kb SRAM */ -# define STM32_NFSMC 1 /* FSMC */ -# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ -# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA - * 32-bit general timers TIM2 and 5 with DMA */ -# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ -# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ -# define STM32_NDMA 2 /* DMA1-2 */ -# define STM32_NSPI 3 /* SPI1-3 */ -# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ -# define STM32_NUSART 6 /* USART1-3 and 6, UART 4-5 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 3 /* I2C1-3 */ -# define STM32_NCAN 2 /* CAN1-2 */ -# define STM32_NSDIO 1 /* SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ -# define STM32_NGPIO 139 /* GPIOA-I */ -# define STM32_NADC 3 /* 12-bit ADC1-3, 16 channels */ -# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */ -# define STM32_NRNG 1 /* Random number generator (RNG) */ -# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F407VG) /* LQFP-100 14x14x1.4 1024Kb FLASH 192Kb SRAM */ -# define STM32_NFSMC 1 /* FSMC */ -# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ -# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA - * 32-bit general timers TIM2 and 5 with DMA */ -# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ -# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ -# define STM32_NDMA 2 /* DMA1-2 */ -# define STM32_NSPI 3 /* SPI1-3 */ -# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ -# define STM32_NUSART 6 /* USART1-3 and 6, UART 4-5 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 3 /* I2C1-3 */ -# define STM32_NCAN 2 /* CAN1-2 */ -# define STM32_NSDIO 1 /* SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ -# define STM32_NGPIO 139 /* GPIOA-I */ -# define STM32_NADC 3 /* 12-bit ADC1-3, 16 channels */ -# define STM32_NDAC 1 /* 12-bit DAC1, 1 channel */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */ -# define STM32_NRNG 1 /* Random number generator (RNG) */ -# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F407ZE) /* LQFP-144 512Kb FLASH 192Kb SRAM */ -# define STM32_NFSMC 1 /* FSMC */ -# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ -# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA - * 32-bit general timers TIM2 and 5 with DMA */ -# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ -# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ -# define STM32_NDMA 2 /* DMA1-2 */ -# define STM32_NSPI 3 /* SPI1-3 */ -# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ -# define STM32_NUSART 6 /* USART1-3 and 6, UART 4-5 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 3 /* I2C1-3 */ -# define STM32_NCAN 2 /* CAN1-2 */ -# define STM32_NSDIO 1 /* SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ -# define STM32_NGPIO 139 /* GPIOA-I */ -# define STM32_NADC 3 /* 12-bit ADC1-3, 24 channels */ -# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */ -# define STM32_NRNG 1 /* Random number generator (RNG) */ -# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F407ZG) /* LQFP 144 20x20x1.4 1024Kb FLASH 192Kb SRAM */ -# define STM32_NFSMC 1 /* FSMC */ -# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ -# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA - * 32-bit general timers TIM2 and 5 with DMA */ -# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ -# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ -# define STM32_NDMA 2 /* DMA1-2 */ -# define STM32_NSPI 3 /* SPI1-3 */ -# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ -# define STM32_NUSART 6 /* USART1-3 and 6, UART 4-5 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 3 /* I2C1-3 */ -# define STM32_NCAN 2 /* CAN1-2 */ -# define STM32_NSDIO 1 /* SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ -# define STM32_NGPIO 139 /* GPIOA-I */ -# define STM32_NADC 3 /* 12-bit ADC1-3, 24 channels */ -# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */ -# define STM32_NRNG 1 /* Random number generator (RNG) */ -# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F407IE) /* LQFP 176 24x24x1.4 512Kb FLASH 192Kb SRAM */ -# define STM32_NFSMC 1 /* FSMC */ -# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ -# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA - * 32-bit general timers TIM2 and 5 with DMA */ -# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ -# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ -# define STM32_NDMA 2 /* DMA1-2 */ -# define STM32_NSPI 3 /* SPI1-3 */ -# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ -# define STM32_NUSART 6 /* USART1-3 and 6, UART 4-5 (?) */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 3 /* I2C1-3 */ -# define STM32_NCAN 2 /* CAN1-2 */ -# define STM32_NSDIO 1 /* SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ -# define STM32_NGPIO 139 /* GPIOA-I */ -# define STM32_NADC 3 /* 12-bit ADC1-3, 24 channels */ -# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */ -# define STM32_NRNG 1 /* Random number generator (RNG) */ -# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F407IG) /* BGA 176; LQFP 176 24x24x1.4 1024Kb FLASH 192Kb SRAM */ -# define STM32_NFSMC 1 /* FSMC */ -# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ -# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA - * 32-bit general timers TIM2 and 5 with DMA */ -# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ -# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ -# define STM32_NDMA 2 /* DMA1-2 */ -# define STM32_NSPI 3 /* SPI1-3 */ -# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ -# define STM32_NUSART 6 /* USART1-3 and 6, UART 4-5 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 3 /* I2C1-3 */ -# define STM32_NCAN 2 /* CAN1-2 */ -# define STM32_NSDIO 1 /* SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ -# define STM32_NGPIO 139 /* GPIOA-I */ -# define STM32_NADC 3 /* 12-bit ADC1-3, 24 channels */ -# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */ -# define STM32_NRNG 1 /* Random number generator (RNG) */ -# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F427I) /* BGA176; LQFP176 1024/2048KiB flash 256KiB SRAM */ -# define STM32_NFSMC 1 /* FSMC */ -# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ -# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA - * 32-bit general timers TIM2 and 5 with DMA */ -# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ -# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ -# define STM32_NDMA 2 /* DMA1-2 */ -# define STM32_NSPI 6 /* SPI1-6 */ -# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ -# define STM32_NUSART 8 /* USART1-3 and 6, UART 4-5 and 7-8 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 3 /* I2C1-3 */ -# define STM32_NCAN 2 /* CAN1-2 */ -# define STM32_NSDIO 1 /* SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ -# define STM32_NGPIO 139 /* GPIOA-I */ -# define STM32_NADC 3 /* 12-bit ADC1-3, 24 channels */ -# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */ -# define STM32_NRNG 1 /* Random number generator (RNG) */ -# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F427Z) /* LQFP144 1024/2048KiB flash 256KiB SRAM */ -# define STM32_NFSMC 1 /* FSMC */ -# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ -# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA - * 32-bit general timers TIM2 and 5 with DMA */ -# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ -# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ -# define STM32_NDMA 2 /* DMA1-2 */ -# define STM32_NSPI 6 /* SPI1-6 */ -# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ -# define STM32_NUSART 8 /* USART1-3 and 6, UART 4-5 and 7-8 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 3 /* I2C1-3 */ -# define STM32_NCAN 2 /* CAN1-2 */ -# define STM32_NSDIO 1 /* SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ -# define STM32_NGPIO 139 /* GPIOA-I */ -# define STM32_NADC 3 /* 12-bit ADC1-3, 24 channels */ -# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */ -# define STM32_NRNG 1 /* Random number generator (RNG) */ -# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F427V) /* LQFP100 1024/2048KiB flash 256KiB SRAM */ -# define STM32_NFSMC 1 /* FSMC */ -# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ -# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA - * 32-bit general timers TIM2 and 5 with DMA */ -# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ -# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ -# define STM32_NDMA 2 /* DMA1-2 */ -# define STM32_NSPI 4 /* SPI1-4 */ -# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ -# define STM32_NUSART 8 /* USART1-3 and 6, UART 4-5 and 7-8 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 3 /* I2C1-3 */ -# define STM32_NCAN 2 /* CAN1-2 */ -# define STM32_NSDIO 1 /* SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ -# define STM32_NGPIO 139 /* GPIOA-I */ -# define STM32_NADC 3 /* 12-bit ADC1-3, 24 channels */ -# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */ -# define STM32_NRNG 1 /* Random number generator (RNG) */ -# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F429I) /* BGA176; LQFP176 1024/2048KiB flash 256KiB SRAM */ -# define STM32_NFSMC 1 /* FSMC */ -# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ -# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA - * 32-bit general timers TIM2 and 5 with DMA */ -# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ -# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ -# define STM32_NDMA 2 /* DMA1-2 */ -# define STM32_NSPI 6 /* SPI1-6 */ -# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ -# define STM32_NUSART 8 /* USART1-3 and 6, UART 4-5 and 7-8 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 3 /* I2C1-3 */ -# define STM32_NCAN 2 /* CAN1-2 */ -# define STM32_NSDIO 1 /* SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ -# define STM32_NGPIO 139 /* GPIOA-I */ -# define STM32_NADC 3 /* 12-bit ADC1-3, 24 channels */ -# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */ -# define STM32_NRNG 1 /* Random number generator (RNG) */ -# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F429Z) /* LQFP144 1024/2048KiB flash 256KiB SRAM */ -# define STM32_NFSMC 1 /* FSMC */ -# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ -# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA - * 32-bit general timers TIM2 and 5 with DMA */ -# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ -# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ -# define STM32_NDMA 2 /* DMA1-2 */ -# define STM32_NSPI 6 /* SPI1-6 */ -# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ -# define STM32_NUSART 8 /* USART1-3 and 6, UART 4-5 and 7-8 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 3 /* I2C1-3 */ -# define STM32_NCAN 2 /* CAN1-2 */ -# define STM32_NSDIO 1 /* SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ -# define STM32_NGPIO 139 /* GPIOA-I */ -# define STM32_NADC 3 /* 12-bit ADC1-3, 24 channels */ -# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */ -# define STM32_NRNG 1 /* Random number generator (RNG) */ -# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F429V) /* LQFP100 1024/2048KiB flash 256KiB SRAM */ -# define STM32_NFSMC 1 /* FSMC */ -# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ -# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA - * 32-bit general timers TIM2 and 5 with DMA */ -# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ -# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ -# define STM32_NDMA 2 /* DMA1-2 */ -# define STM32_NSPI 4 /* SPI1-4 */ -# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ -# define STM32_NUSART 8 /* USART1-3 and 6, UART 4-5 and 7-8 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 3 /* I2C1-3 */ -# define STM32_NCAN 2 /* CAN1-2 */ -# define STM32_NSDIO 1 /* SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ -# define STM32_NGPIO 139 /* GPIOA-I */ -# define STM32_NADC 3 /* 12-bit ADC1-3, 24 channels */ -# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */ -# define STM32_NRNG 1 /* Random number generator (RNG) */ -# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F446M) /* WLCSP81 256/512KiB flash 128KiB SRAM */ -# define STM32_NFSMC 0 /* FSMC */ -# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ -# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA - * 32-bit general timers TIM2 and 5 with DMA */ -# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ -# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ -# define STM32_NDMA 2 /* DMA1-2 */ -# define STM32_NSPI 4 /* SPI1-4 */ -# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ -# define STM32_NUSART 6 /* USART1-3 and 6, UART 4-5 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 3 /* I2C1-3 */ -# define STM32_NCAN 2 /* CAN1-2 */ -# define STM32_NSDIO 1 /* SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ -# define STM32_NGPIO 114 /* GPIOA-I */ -# define STM32_NADC 2 /* 12-bit ADC1-3, 14 channels */ -# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 0 /* 100/100 Ethernet MAC */ -# define STM32_NRNG 0 /* Random number generator (RNG) */ -# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F446R) /* LQFP64 256/512KiB flash 128KiB SRAM */ -# define STM32_NFSMC 0 /* FSMC */ -# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ -# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA - * 32-bit general timers TIM2 and 5 with DMA */ -# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ -# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ -# define STM32_NDMA 2 /* DMA1-2 */ -# define STM32_NSPI 4 /* SPI1-4 */ -# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ -# define STM32_NUSART 6 /* USART1-3 and 6, UART 4-5 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 3 /* I2C1-3 */ -# define STM32_NCAN 2 /* CAN1-2 */ -# define STM32_NSDIO 1 /* SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ -# define STM32_NGPIO 114 /* GPIOA-I */ -# define STM32_NADC 2 /* 12-bit ADC1-3, 16 channels */ -# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 0 /* 100/100 Ethernet MAC */ -# define STM32_NRNG 0 /* Random number generator (RNG) */ -# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F446V) /* LQFP100 256/512KiB flash 128KiB SRAM */ -# define STM32_NFSMC 1 /* FSMC */ -# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ -# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA - * 32-bit general timers TIM2 and 5 with DMA */ -# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ -# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ -# define STM32_NDMA 2 /* DMA1-2 */ -# define STM32_NSPI 4 /* SPI1-4 */ -# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ -# define STM32_NUSART 6 /* USART1-3 and 6, UART 4-5 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 3 /* I2C1-3 */ -# define STM32_NCAN 2 /* CAN1-2 */ -# define STM32_NSDIO 1 /* SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ -# define STM32_NGPIO 114 /* GPIOA-I */ -# define STM32_NADC 2 /* 12-bit ADC1-3, 16 channels */ -# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 0 /* 100/100 Ethernet MAC */ -# define STM32_NRNG 0 /* Random number generator (RNG) */ -# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F446Z) /* LQFP144 UFBGA144 256/512KiB flash 128KiB SRAM */ -# define STM32_NFSMC 1 /* FSMC */ -# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ -# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA - * 32-bit general timers TIM2 and 5 with DMA */ -# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ -# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ -# define STM32_NDMA 2 /* DMA1-2 */ -# define STM32_NSPI 4 /* SPI1-4 */ -# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ -# define STM32_NUSART 6 /* USART1-3 and 6, UART 4-5 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 3 /* I2C1-3 */ -# define STM32_NCAN 2 /* CAN1-2 */ -# define STM32_NSDIO 1 /* SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ -# define STM32_NGPIO 114 /* GPIOA-I */ -# define STM32_NADC 2 /* 12-bit ADC1-3, 16 channels */ -# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 0 /* 100/100 Ethernet MAC */ -# define STM32_NRNG 0 /* Random number generator (RNG) */ -# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F429N) /* TFBGA216 1024/2048KiB flash 256KiB SRAM */ -# define STM32_NFSMC 1 /* FSMC */ -# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ -# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA - * 32-bit general timers TIM2 and 5 with DMA */ -# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ -# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ -# define STM32_NDMA 2 /* DMA1-2 */ -# define STM32_NSPI 6 /* SPI1-6 */ -# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ -# define STM32_NUSART 8 /* USART1-3 and 6, UART 4-5 and 7-8 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 3 /* I2C1-3 */ -# define STM32_NCAN 2 /* CAN1-2 */ -# define STM32_NSDIO 1 /* SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ -# define STM32_NGPIO 168 /* GPIOA-K */ -# define STM32_NADC 3 /* 12-bit ADC1-3, 24 channels */ -# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */ -# define STM32_NRNG 1 /* Random number generator (RNG) */ -# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F469A) || \ - defined(CONFIG_ARCH_CHIP_STM32F469I) || \ - defined(CONFIG_ARCH_CHIP_STM32F469B) || \ - defined(CONFIG_ARCH_CHIP_STM32F469N) -# define STM32_NFSMC 1 /* FSMC */ -# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ -# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA - * 32-bit general timers TIM2 and 5 with DMA */ -# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ -# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ -# define STM32_NDMA 2 /* DMA1-2 */ -# define STM32_NSPI 6 /* SPI1-6 */ -# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ -# define STM32_NUSART 8 /* USART1-3 and 6, UART 4-5 and 7-8 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 3 /* I2C1-3 */ -# define STM32_NCAN 2 /* CAN1-2 */ -# define STM32_NSDIO 1 /* SDIO */ -# define STM32_NLCD 1 /* LCD */ -# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ -# if defined(CONFIG_ARCH_CHIP_STM32F469A) -# define STM32_NGPIO 114 /* GPIOA-I */ -# elif defined(CONFIG_ARCH_CHIP_STM32F469I) -# define STM32_NGPIO 131 /* GPIOA-I */ -# elif defined(CONFIG_ARCH_CHIP_STM32F469B) || \ - defined(CONFIG_ARCH_CHIP_STM32F469N) -# define STM32_NGPIO 161 /* GPIOA-K */ -# endif -# define STM32_NADC 3 /* 12-bit ADC1-3, 24 channels */ -# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# if defined(CONFIG_ARCH_CHIP_STM32F469A) -# define STM32_NETHERNET 0 /* No Ethernet MAC */ -# elif defined(CONFIG_ARCH_CHIP_STM32F469I) || \ - defined(CONFIG_ARCH_CHIP_STM32F469B) || \ - defined(CONFIG_ARCH_CHIP_STM32F469N) -# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */ -# endif -# define STM32_NRNG 1 /* Random number generator (RNG) */ -# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */ - -#elif defined (CONFIG_ARCH_CHIP_STM32G431K) -# define STM32_NFSMC 0 /* FSMC */ -# define STM32_NATIM 2 /* (2) Advanced motor control timers TIM1, 8 with DMA */ -# define STM32_NGTIM 6 /* (2) 16-bit general timers TIM3 and 4 with DMA - * (1) 32-bit general timers TIM2 with DMA - * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ -# define STM32_NGTIMNDMA 0 /* (0) 16-bit general timers TIM9-14 without DMA */ -# define STM32_NBTIM 2 /* (2) Basic timers, TIM6-7 */ -# define STM32_NDMA 2 /* DMA1-2 */ -# define STM32_NSPI 3 /* SPI1-3 */ -# define STM32_NI2S 2 /* I2S2-3 (multiplexed with SPI2-3) */ -# define STM32_NUSART 2 /* USART1-2 */ -# define STM32_NLPUART 1 /* LPUART1 */ -# define STM32_NI2C 3 /* I2C1-3 */ -# define STM32_NCAN 1 /* FDCAN1 */ -# define STM32_NSDIO 0 /* No SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (but there is USB 2.0 full-speed - * with LPM and BCD support) */ -# define STM32_NGPIO 26 /* GPIOA-G */ -# define STM32_NADC 2 /* 12-bit ADC1-2 */ -# define STM32_NDAC 2 /* 12-bit DAC1-2, 4 channels (2 external, 2 internal) */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 0 /* No Ethernet MAC */ -# define STM32_NRNG 1 /* Random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -#elif defined (CONFIG_ARCH_CHIP_STM32G431C) -# define STM32_NFSMC 0 /* FSMC */ -# define STM32_NATIM 2 /* (2) Advanced motor control timers TIM1, 8 with DMA */ -# define STM32_NGTIM 6 /* (2) 16-bit general timers TIM3 and 4 with DMA - * (1) 32-bit general timers TIM2 with DMA - * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ -# define STM32_NGTIMNDMA 0 /* (0) 16-bit general timers TIM9-14 without DMA */ -# define STM32_NBTIM 2 /* (2) Basic timers, TIM6-7 */ -# define STM32_NDMA 2 /* DMA1-2 */ -# define STM32_NSPI 3 /* SPI1-3 */ -# define STM32_NI2S 2 /* I2S2-3 (multiplexed with SPI2-3) */ -# define STM32_NUSART 3 /* USART1-3 */ -# define STM32_NLPUART 1 /* LPUART1 */ -# define STM32_NI2C 3 /* I2C1-3 */ -# define STM32_NCAN 1 /* FDCAN1 */ -# define STM32_NSDIO 0 /* No SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (but there is USB 2.0 full-speed - * with LPM and BCD support) */ -# define STM32_NGPIO 42 /* GPIOA-G */ -# define STM32_NADC 2 /* 12-bit ADC1-2 */ -# define STM32_NDAC 2 /* 12-bit DAC1-2, 4 channels (2 external, 2 internal) */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 0 /* No Ethernet MAC */ -# define STM32_NRNG 1 /* Random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -#elif defined (CONFIG_ARCH_CHIP_STM32G431R) -# define STM32_NFSMC 0 /* FSMC */ -# define STM32_NATIM 2 /* (2) Advanced motor control timers TIM1, 8 with DMA */ -# define STM32_NGTIM 6 /* (2) 16-bit general timers TIM3 and 4 with DMA - * (1) 32-bit general timers TIM2 with DMA - * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ -# define STM32_NGTIMNDMA 0 /* (0) 16-bit general timers TIM9-14 without DMA */ -# define STM32_NBTIM 2 /* (2) Basic timers, TIM6-7 */ -# define STM32_NDMA 2 /* DMA1-2 */ -# define STM32_NSPI 3 /* SPI1-3 */ -# define STM32_NI2S 2 /* I2S2-3 (multiplexed with SPI2-3) */ -# define STM32_NUSART 4 /* USART1-3 and UART4*/ -# define STM32_NLPUART 1 /* LPUART1 */ -# define STM32_NI2C 3 /* I2C1-3 */ -# define STM32_NCAN 1 /* FDCAN1 */ -# define STM32_NSDIO 0 /* No SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (but there is USB 2.0 full-speed - * with LPM and BCD support) */ -# define STM32_NGPIO 52 /* GPIOA-G */ -# define STM32_NADC 2 /* 12-bit ADC1-2 */ -# define STM32_NDAC 2 /* 12-bit DAC1-2, 4 channels (2 external, 2 internal) */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 0 /* No Ethernet MAC */ -# define STM32_NRNG 1 /* Random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -#elif defined (CONFIG_ARCH_CHIP_STM32G431M) -# define STM32_NFSMC 0 /* FSMC */ -# define STM32_NATIM 2 /* (2) Advanced motor control timers TIM1, 8 with DMA */ -# define STM32_NGTIM 6 /* (2) 16-bit general timers TIM3 and 4 with DMA - * (1) 32-bit general timers TIM2 with DMA - * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ -# define STM32_NGTIMNDMA 0 /* (0) 16-bit general timers TIM9-14 without DMA */ -# define STM32_NBTIM 2 /* (2) Basic timers, TIM6-7 */ -# define STM32_NDMA 2 /* DMA1-2 */ -# define STM32_NSPI 3 /* SPI1-3 */ -# define STM32_NI2S 2 /* I2S2-3 (multiplexed with SPI2-3) */ -# define STM32_NUSART 4 /* USART1-3 and UART4*/ -# define STM32_NLPUART 1 /* LPUART1 */ -# define STM32_NI2C 3 /* I2C1-3 */ -# define STM32_NCAN 1 /* FDCAN1 */ -# define STM32_NSDIO 0 /* No SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (but there is USB 2.0 full-speed - * with LPM and BCD support) */ -# define STM32_NGPIO 66 /* GPIOA-G */ -# define STM32_NADC 2 /* 12-bit ADC1-2 */ -# define STM32_NDAC 2 /* 12-bit DAC1-2, 4 channels (2 external, 2 internal) */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 0 /* No Ethernet MAC */ -# define STM32_NRNG 1 /* Random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -#elif defined (CONFIG_ARCH_CHIP_STM32G431V) -# define STM32_NFSMC 0 /* FSMC */ -# define STM32_NATIM 2 /* (2) Advanced motor control timers TIM1, 8 with DMA */ -# define STM32_NGTIM 6 /* (2) 16-bit general timers TIM3 and 4 with DMA - * (1) 32-bit general timers TIM2 with DMA - * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ -# define STM32_NGTIMNDMA 0 /* (0) 16-bit general timers TIM9-14 without DMA */ -# define STM32_NBTIM 2 /* (2) Basic timers, TIM6-7 */ -# define STM32_NDMA 2 /* DMA1-2 */ -# define STM32_NSPI 3 /* SPI1-3 */ -# define STM32_NI2S 2 /* I2S2-3 (multiplexed with SPI2-3) */ -# define STM32_NUSART 4 /* USART1-3 and UART4*/ -# define STM32_NLPUART 1 /* LPUART1 */ -# define STM32_NI2C 3 /* I2C1-3 */ -# define STM32_NCAN 1 /* FDCAN1 */ -# define STM32_NSDIO 0 /* No SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (but there is USB 2.0 full-speed - * with LPM and BCD support) */ -# define STM32_NGPIO 86 /* GPIOA-G */ -# define STM32_NADC 2 /* 12-bit ADC1-2 */ -# define STM32_NDAC 2 /* 12-bit DAC1-2, 4 channels (2 external, 2 internal) */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 0 /* No Ethernet MAC */ -# define STM32_NRNG 1 /* Random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -#elif defined (CONFIG_ARCH_CHIP_STM32G474C) -# define STM32_NFSMC 0 /* FSMC */ -# define STM32_NATIM 3 /* (3) Advanced motor control timers TIM1, 8, and 20 with DMA */ -# define STM32_NGTIM 7 /* (2) 16-bit general timers TIM3 and 4 with DMA - * (2) 32-bit general timers TIM2 and 5 with DMA - * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ -# define STM32_NGTIMNDMA 0 /* (0) 16-bit general timers TIM9-14 without DMA */ -# define STM32_NBTIM 2 /* (2) Basic timers, TIM6-7 */ -# define STM32_NDMA 2 /* DMA1-2 */ -# define STM32_NSPI 3 /* SPI1-3 */ -# define STM32_NI2S 2 /* I2S2-3 (multiplexed with SPI2-3) */ -# define STM32_NUSART 3 /* USART1-3 */ -# define STM32_NLPUART 1 /* LPUART1 */ -# define STM32_NI2C 4 /* I2C1-4 */ -# define STM32_NCAN 3 /* FDCAN1-3 */ -# define STM32_NSDIO 0 /* No SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (but there is USB 2.0 full-speed - * with LPM and BCD support) */ -# define STM32_NGPIO 42 /* GPIOA-C, F-G */ -# define STM32_NADC 5 /* 12-bit ADC1-5 */ -# define STM32_NDAC 4 /* 12-bit DAC1-4, 7 channels (3 external, 4 internal) */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 0 /* No Ethernet MAC */ -# define STM32_NRNG 1 /* Random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -#elif defined (CONFIG_ARCH_CHIP_STM32G474M) -# define STM32_NFSMC 0 /* FSMC */ -# define STM32_NATIM 3 /* (3) Advanced motor control timers TIM1, 8, and 20 with DMA */ -# define STM32_NGTIM 7 /* (2) 16-bit general timers TIM3 and 4 with DMA - * (2) 32-bit general timers TIM2 and 5 with DMA - * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ -# define STM32_NGTIMNDMA 0 /* (0) 16-bit general timers TIM9-14 without DMA */ -# define STM32_NBTIM 2 /* (2) Basic timers, TIM6-7 */ -# define STM32_NDMA 2 /* DMA1-2 */ -# define STM32_NSPI 4 /* SPI1-4 */ -# define STM32_NI2S 2 /* I2S2-3 (multiplexed with SPI2-3) */ -# define STM32_NUSART 5 /* USART1-3 and UART 4-5 */ -# define STM32_NLPUART 1 /* LPUART1 */ -# define STM32_NI2C 4 /* I2C1-4 */ -# define STM32_NCAN 3 /* FDCAN1-3 */ -# define STM32_NSDIO 0 /* No SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (but there is USB 2.0 full-speed - * with LPM and BCD support) */ -# define STM32_NGPIO 67 /* GPIOA-G */ -# define STM32_NADC 5 /* 12-bit ADC1-5 */ -# define STM32_NDAC 4 /* 12-bit DAC1-4, 7 channels (3 external, 4 internal) */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 0 /* No Ethernet MAC */ -# define STM32_NRNG 1 /* Random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -#elif defined (CONFIG_ARCH_CHIP_STM32G474R) -# define STM32_NFSMC 0 /* FSMC */ -# define STM32_NATIM 3 /* (3) Advanced motor control timers TIM1, 8, and 20 with DMA */ -# define STM32_NGTIM 7 /* (2) 16-bit general timers TIM3 and 4 with DMA - * (2) 32-bit general timers TIM2 and 5 with DMA - * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ -# define STM32_NGTIMNDMA 0 /* (0) 16-bit general timers TIM9-14 without DMA */ -# define STM32_NBTIM 2 /* (2) Basic timers, TIM6-7 */ -# define STM32_NDMA 2 /* DMA1-2 */ -# define STM32_NSPI 3 /* SPI1-3 */ -# define STM32_NI2S 2 /* I2S2-3 (multiplexed with SPI2-3) */ -# define STM32_NUSART 5 /* USART1-3 and UART 4-5 */ -# define STM32_NLPUART 1 /* LPUART1 */ -# define STM32_NI2C 4 /* I2C1-4 */ -# define STM32_NCAN 3 /* FDCAN1-3 */ -# define STM32_NSDIO 0 /* No SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (but there is USB 2.0 full-speed - * with LPM and BCD support) */ -# define STM32_NGPIO 52 /* GPIOA-D, F-G */ -# define STM32_NADC 5 /* 12-bit ADC1-5 */ -# define STM32_NDAC 4 /* 12-bit DAC1-4, 7 channels (3 external, 4 internal) */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 0 /* No Ethernet MAC */ -# define STM32_NRNG 1 /* Random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -#elif defined (CONFIG_ARCH_CHIP_STM32G474Q) -# define STM32_NFSMC 1 /* FSMC */ -# define STM32_NATIM 3 /* (3) Advanced motor control timers TIM1, 8, and 20 with DMA */ -# define STM32_NGTIM 7 /* (2) 16-bit general timers TIM3 and 4 with DMA - * (2) 32-bit general timers TIM2 and 5 with DMA - * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ -# define STM32_NGTIMNDMA 0 /* (0) 16-bit general timers TIM9-14 without DMA */ -# define STM32_NBTIM 2 /* (2) Basic timers, TIM6-7 */ -# define STM32_NDMA 2 /* DMA1-2 */ -# define STM32_NSPI 4 /* SPI1-4 */ -# define STM32_NI2S 2 /* I2S2-3 (multiplexed with SPI2-3) */ -# define STM32_NUSART 5 /* USART1-3 and UART 4-5 */ -# define STM32_NLPUART 1 /* LPUART1 */ -# define STM32_NI2C 4 /* I2C1-4 */ -# define STM32_NCAN 3 /* FDCAN1-3 */ -# define STM32_NSDIO 0 /* No SDIO */ -# define STM32_NLCD 1 /* LCD parallel interface possible via FMC */ -# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (but there is USB 2.0 full-speed - * with LPM and BCD support) */ -# define STM32_NGPIO 107 /* GPIOA-G */ -# define STM32_NADC 5 /* 12-bit ADC1-5 */ -# define STM32_NDAC 4 /* 12-bit DAC1-4, 7 channels (3 external, 4 internal) */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 0 /* No Ethernet MAC */ -# define STM32_NRNG 1 /* Random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -#elif defined (CONFIG_ARCH_CHIP_STM32G474V) -# define STM32_NFSMC 1 /* FSMC */ -# define STM32_NATIM 3 /* (3) Advanced motor control timers TIM1, 8, and 20 with DMA */ -# define STM32_NGTIM 7 /* (2) 16-bit general timers TIM3 and 4 with DMA - * (2) 32-bit general timers TIM2 and 5 with DMA - * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ -# define STM32_NGTIMNDMA 0 /* (0) 16-bit general timers TIM9-14 without DMA */ -# define STM32_NBTIM 2 /* (2) Basic timers, TIM6-7 */ -# define STM32_NDMA 2 /* DMA1-2 */ -# define STM32_NSPI 4 /* SPI1-4 */ -# define STM32_NI2S 2 /* I2S2-3 (multiplexed with SPI2-3) */ -# define STM32_NUSART 5 /* USART1-3 and UART 4-5 */ -# define STM32_NLPUART 1 /* LPUART1 */ -# define STM32_NI2C 4 /* I2C1-4 */ -# define STM32_NCAN 3 /* FDCAN1-3 */ -# define STM32_NSDIO 0 /* No SDIO */ -# define STM32_NLCD 1 /* LCD parallel interface possible via FMC */ -# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (but there is USB 2.0 full-speed - * with LPM and BCD support) */ -# define STM32_NGPIO 86 /* GPIOA-G */ -# define STM32_NADC 5 /* 12-bit ADC1-5 */ -# define STM32_NDAC 4 /* 12-bit DAC1-4, 7 channels (3 external, 4 internal) */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 0 /* No Ethernet MAC */ -# define STM32_NRNG 1 /* Random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -#else -# error "Unsupported STM32 chip" -#endif - -/* Peripheral IP versions ***************************************************/ - -/* Peripheral IP versions are invariant and should be decided here, not in - * Kconfig. - * - * REVISIT: Currently only SPI IP version is handled here, with others being - * handled in Kconfig. Those others need to be gradually refactored - * and resolved here. - */ - -#if defined(CONFIG_STM32_STM32F10XX) -# define STM32_HAVE_IP_SPI_V1 - -#elif defined(CONFIG_STM32_STM32F20XX) -# define STM32_HAVE_IP_SPI_V2 - -#elif defined(CONFIG_STM32_STM32F30XX) -# define STM32_HAVE_IP_SPI_V3 - -#elif defined(CONFIG_STM32_STM32F33XX) -# define STM32_HAVE_IP_SPI_V1 - -#elif defined(CONFIG_STM32_STM32F37XX) -# define STM32_HAVE_IP_SPI_V3 - -#elif defined(CONFIG_STM32_STM32F4XXX) -# define STM32_HAVE_IP_SPI_V2 - -#elif defined(CONFIG_STM32_STM32G4XXX) -# define STM32_HAVE_IP_SPI_V4 - -#elif defined(CONFIG_STM32_STM32L15XX) -# define STM32_HAVE_IP_SPI_V1 - -#else -# error "Did not resolve peripheral IP versions!" -#endif - -/* NVIC priority levels *****************************************************/ - -#define NVIC_SYSH_PRIORITY_MIN 0xf0 /* All bits set in minimum priority */ -#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */ -#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */ -#define NVIC_SYSH_PRIORITY_STEP 0x10 /* Four bits of interrupt priority used */ - -#endif /* __ARCH_ARM_INCLUDE_STM32_CHIP_H */ diff --git a/arch/arm/include/stm32/irq.h b/arch/arm/include/stm32/irq.h deleted file mode 100644 index 6e55b57a3fcf5..0000000000000 --- a/arch/arm/include/stm32/irq.h +++ /dev/null @@ -1,121 +0,0 @@ -/**************************************************************************** - * arch/arm/include/stm32/irq.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* This file should never be included directly but, rather, - * only indirectly through nuttx/irq.h - */ - -#ifndef __ARCH_ARM_INCLUDE_STM32_IRQ_H -#define __ARCH_ARM_INCLUDE_STM32_IRQ_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include -#include - -/**************************************************************************** - * Pre-processor Prototypes - ****************************************************************************/ - -/* IRQ numbers. - * The IRQ number corresponds vector number and hence map directly to - * bits in the NVIC. This does, however, waste several words of memory in - * the IRQ to handle mapping tables. - */ - -/* Processor Exceptions (vectors 0-15) */ - -#define STM32_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */ - /* Vector 0: Reset stack pointer value */ - /* Vector 1: Reset (not handler as an IRQ) */ -#define STM32_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */ -#define STM32_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */ -#define STM32_IRQ_MEMFAULT (4) /* Vector 4: Memory management (MPU) */ -#define STM32_IRQ_BUSFAULT (5) /* Vector 5: Bus fault */ -#define STM32_IRQ_USAGEFAULT (6) /* Vector 6: Usage fault */ -#define STM32_IRQ_SVCALL (11) /* Vector 11: SVC call */ -#define STM32_IRQ_DBGMONITOR (12) /* Vector 12: Debug Monitor */ - /* Vector 13: Reserved */ -#define STM32_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */ -#define STM32_IRQ_SYSTICK (15) /* Vector 15: System tick */ - -/* External interrupts (vectors >= 16). - * These definitions are chip-specific - */ - -#define STM32_IRQ_FIRST (16) /* Vector number of the first external interrupt */ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#if defined(CONFIG_STM32_STM32L15XX) -# include -#elif defined(CONFIG_STM32_STM32F10XX) -# include -#elif defined(CONFIG_STM32_STM32F20XX) -# include -#elif defined(CONFIG_STM32_STM32F30XX) -# include -#elif defined(CONFIG_STM32_STM32F33XX) -# include -#elif defined(CONFIG_STM32_STM32F37XX) -# include -#elif defined(CONFIG_STM32_STM32F4XXX) -# include -#elif defined(CONFIG_STM32_STM32G4XXX) -# include -#else -# error "Unsupported STM32 chip" -#endif - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -#ifndef __ASSEMBLY__ -#ifdef __cplusplus -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -#undef EXTERN -#ifdef __cplusplus -} -#endif -#endif - -#endif /* __ARCH_ARM_INCLUDE_STM32_IRQ_H */ diff --git a/arch/arm/include/stm32/stm32f10xxx_irq.h b/arch/arm/include/stm32/stm32f10xxx_irq.h deleted file mode 100644 index 52d1b038f7826..0000000000000 --- a/arch/arm/include/stm32/stm32f10xxx_irq.h +++ /dev/null @@ -1,298 +0,0 @@ -/**************************************************************************** - * arch/arm/include/stm32/stm32f10xxx_irq.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* This file should never be included directly but, rather, - * only indirectly through nuttx/irq.h - */ - -#ifndef __ARCH_ARM_INCLUDE_STM32_STM32F10XXX_IRQ_H -#define __ARCH_ARM_INCLUDE_STM32_STM32F10XXX_IRQ_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include - -/**************************************************************************** - * Pre-processor Prototypes - ****************************************************************************/ - -/* IRQ numbers. The IRQ number corresponds vector number and hence map - * directly to bits in the NVIC. This does, however, waste several words of - * memory in the IRQ to handle mapping tables. - * - * Processor Exceptions (vectors 0-15). These common definitions can be - * found in nuttx/arch/arm/include/stm32/irq.h - * - * External interrupts (vectors >= 16) - */ - -/* Value line devices */ - -#if defined(CONFIG_STM32_VALUELINE) -# define STM32_IRQ_WWDG (16) /* 0: Window Watchdog interrupt */ -# define STM32_IRQ_PVD (17) /* 1: PVD through EXTI Line detection interrupt */ -# define STM32_IRQ_TAMPER (18) /* 2: Tamper interrupt */ -# define STM32_IRQ_RTC (19) /* 3: RTC Wakeup through EXTI line interrupt */ -# define STM32_IRQ_FLASH (20) /* 4: Flash global interrupt */ -# define STM32_IRQ_RCC (21) /* 5: RCC global interrupt */ -# define STM32_IRQ_EXTI0 (22) /* 6: EXTI Line 0 interrupt */ -# define STM32_IRQ_EXTI1 (23) /* 7: EXTI Line 1 interrupt */ -# define STM32_IRQ_EXTI2 (24) /* 8: EXTI Line 2 interrupt */ -# define STM32_IRQ_EXTI3 (25) /* 9: EXTI Line 3 interrupt */ -# define STM32_IRQ_EXTI4 (26) /* 10: EXTI Line 4 interrupt */ -# define STM32_IRQ_DMA1CH1 (27) /* 11: DMA1 Channel 1 global interrupt */ -# define STM32_IRQ_DMA1CH2 (28) /* 12: DMA1 Channel 2 global interrupt */ -# define STM32_IRQ_DMA1CH3 (29) /* 13: DMA1 Channel 3 global interrupt */ -# define STM32_IRQ_DMA1CH4 (30) /* 14: DMA1 Channel 4 global interrupt */ -# define STM32_IRQ_DMA1CH5 (31) /* 15: DMA1 Channel 5 global interrupt */ -# define STM32_IRQ_DMA1CH6 (32) /* 16: DMA1 Channel 6 global interrupt */ -# define STM32_IRQ_DMA1CH7 (33) /* 17: DMA1 Channel 7 global interrupt */ -# define STM32_IRQ_ADC1 (34) /* 18: ADC1 global interrupt */ -# define STM32_IRQ_RESERVED0 (35) /* 19: Reserved 0 */ -# define STM32_IRQ_RESERVED1 (36) /* 20: Reserved 1 */ -# define STM32_IRQ_RESERVED2 (37) /* 21: Reserved 2 */ -# define STM32_IRQ_RESERVED3 (38) /* 22: Reserved 3 */ -# define STM32_IRQ_EXTI95 (39) /* 23: EXTI Line[9:5] interrupts */ -# define STM32_IRQ_TIM1BRK (40) /* 24: TIM1 Break interrupt */ -# define STM32_IRQ_TIM15 (40) /* TIM15 global interrupt */ -# define STM32_IRQ_TIM1UP (41) /* 25: TIM1 Update interrupt */ -# define STM32_IRQ_TIM16 (41) /* TIM16 global interrupt */ -# define STM32_IRQ_TIM1TRGCOM (42) /* 26: TIM1 Trigger and Commutation interrupts */ -# define STM32_IRQ_TIM17 (42) /* TIM17 global interrupt */ -# define STM32_IRQ_TIM1CC (43) /* 27: TIM1 Capture Compare interrupt */ -# define STM32_IRQ_TIM2 (44) /* 28: TIM2 global interrupt */ -# define STM32_IRQ_TIM3 (45) /* 29: TIM3 global interrupt */ -# define STM32_IRQ_TIM4 (46) /* 30: TIM4 global interrupt */ -# define STM32_IRQ_I2C1EV (47) /* 31: I2C1 event interrupt */ -# define STM32_IRQ_I2C1ER (48) /* 32: I2C1 error interrupt */ -# define STM32_IRQ_I2C2EV (49) /* 33: I2C2 event interrupt */ -# define STM32_IRQ_I2C2ER (50) /* 34: I2C2 error interrupt */ -# define STM32_IRQ_SPI1 (51) /* 35: SPI1 global interrupt */ -# define STM32_IRQ_SPI2 (52) /* 36: SPI2 global interrupt */ -# define STM32_IRQ_USART1 (53) /* 37: USART1 global interrupt */ -# define STM32_IRQ_USART2 (54) /* 38: USART2 global interrupt */ -# define STM32_IRQ_USART3 (55) /* 39: USART3 global interrupt */ -# define STM32_IRQ_EXTI1510 (56) /* 40: EXTI Line[15:10] interrupts */ -# define STM32_IRQ_RTCALR (57) /* 41: RTC alarms (A and B) through EXTI line interrupt */ -# define STM32_IRQ_CEC (58) /* 42: CEC global interrupt */ -# define STM32_IRQ_TIM12 (59) /* 43: TIM12 global interrupt */ -# define STM32_IRQ_TIM13 (60) /* 44: TIM13 global interrupt */ -# define STM32_IRQ_TIM14 (61) /* 45: TIM14 global interrupt */ -# define STM32_IRQ_RESERVED4 (62) /* 46: Reserved 4 */ -# define STM32_IRQ_RESERVED5 (63) /* 47: Reserved 5 */ -# define STM32_IRQ_FSMC (64) /* 48: FSMC global interrupt */ -# define STM32_IRQ_RESERVED6 (65) /* 49: Reserved 6 */ -# define STM32_IRQ_TIM5 (66) /* 50: TIM5 global interrupt */ -# define STM32_IRQ_SPI3 (67) /* 51: SPI3 global interrupt */ -# define STM32_IRQ_UART4 (68) /* 52: USART2 global interrupt */ -# define STM32_IRQ_UART5 (69) /* 53: UART5 global interrupt */ -# define STM32_IRQ_TIM6 (70) /* 54: TIM6 global interrupt */ -# define STM32_IRQ_TIM7 (71) /* 55: TIM7 global interrupt */ -# define STM32_IRQ_DMA2CH1 (72) /* 56: DMA2 Channel 1 global interrupt */ -# define STM32_IRQ_DMA2CH2 (73) /* 57: DMA2 Channel 2 global interrupt */ -# define STM32_IRQ_DMA2CH3 (74) /* 58: DMA2 Channel 3 global interrupt */ -# define STM32_IRQ_DMA2CH45 (75) /* 59: DMA2 Channel 4 and 5 global interrupt */ -# define STM32_IRQ_DMA2CH5 (76) /* 60: DMA2 Channel 5 global interrupt */ - -# define STM32_IRQ_NEXTINTS (61) - -/* Connectivity Line Devices */ - -#elif defined(CONFIG_STM32_CONNECTIVITYLINE) -# define STM32_IRQ_WWDG (16) /* 0: Window Watchdog interrupt */ -# define STM32_IRQ_PVD (17) /* 1: PVD through EXTI Line detection interrupt */ -# define STM32_IRQ_TAMPER (18) /* 2: Tamper interrupt */ -# define STM32_IRQ_RTC (19) /* 3: RTC global interrupt */ -# define STM32_IRQ_FLASH (20) /* 4: Flash global interrupt */ -# define STM32_IRQ_RCC (21) /* 5: RCC global interrupt */ -# define STM32_IRQ_EXTI0 (22) /* 6: EXTI Line 0 interrupt */ -# define STM32_IRQ_EXTI1 (23) /* 7: EXTI Line 1 interrupt */ -# define STM32_IRQ_EXTI2 (24) /* 8: EXTI Line 2 interrupt */ -# define STM32_IRQ_EXTI3 (25) /* 9: EXTI Line 3 interrupt */ -# define STM32_IRQ_EXTI4 (26) /* 10: EXTI Line 4 interrupt */ -# define STM32_IRQ_DMA1CH1 (27) /* 11: DMA1 Channel 1 global interrupt */ -# define STM32_IRQ_DMA1CH2 (28) /* 12: DMA1 Channel 2 global interrupt */ -# define STM32_IRQ_DMA1CH3 (29) /* 13: DMA1 Channel 3 global interrupt */ -# define STM32_IRQ_DMA1CH4 (30) /* 14: DMA1 Channel 4 global interrupt */ -# define STM32_IRQ_DMA1CH5 (31) /* 15: DMA1 Channel 5 global interrupt */ -# define STM32_IRQ_DMA1CH6 (32) /* 16: DMA1 Channel 6 global interrupt */ -# define STM32_IRQ_DMA1CH7 (33) /* 17: DMA1 Channel 7 global interrupt */ -# define STM32_IRQ_ADC12 (34) /* 18: ADC1 and ADC2 global interrupt */ -# define STM32_IRQ_CAN1TX (35) /* 19: CAN1 TX interrupts */ -# define STM32_IRQ_CAN1RX0 (36) /* 20: CAN1 RX0 interrupts */ -# define STM32_IRQ_CAN1RX1 (37) /* 21: CAN1 RX1 interrupt */ -# define STM32_IRQ_CAN1SCE (38) /* 22: CAN1 SCE interrupt */ -# define STM32_IRQ_EXTI95 (39) /* 23: EXTI Line[9:5] interrupts */ -# define STM32_IRQ_TIM1BRK (40) /* 24: TIM1 Break interrupt */ -# define STM32_IRQ_TIM1UP (41) /* 25: TIM1 Update interrupt */ -# define STM32_IRQ_TIM1TRGCOM (42) /* 26: TIM1 Trigger and Commutation interrupts */ -# define STM32_IRQ_TIM1CC (43) /* 27: TIM1 Capture Compare interrupt */ -# define STM32_IRQ_TIM2 (44) /* 28: TIM2 global interrupt */ -# define STM32_IRQ_TIM3 (45) /* 29: TIM3 global interrupt */ -# define STM32_IRQ_TIM4 (46) /* 30: TIM4 global interrupt */ -# define STM32_IRQ_I2C1EV (47) /* 31: I2C1 event interrupt */ -# define STM32_IRQ_I2C1ER (48) /* 32: I2C1 error interrupt */ -# define STM32_IRQ_I2C2EV (49) /* 33: I2C2 event interrupt */ -# define STM32_IRQ_I2C2ER (50) /* 34: I2C2 error interrupt */ -# define STM32_IRQ_SPI1 (51) /* 35: SPI1 global interrupt */ -# define STM32_IRQ_SPI2 (52) /* 36: SPI2 global interrupt */ -# define STM32_IRQ_USART1 (53) /* 37: USART1 global interrupt */ -# define STM32_IRQ_USART2 (54) /* 38: USART2 global interrupt */ -# define STM32_IRQ_USART3 (55) /* 39: USART3 global interrupt */ -# define STM32_IRQ_EXTI1510 (56) /* 40: EXTI Line[15:10] interrupts */ -# define STM32_IRQ_RTCALRM (57) /* 41: RTC alarm through EXTI line interrupt */ -# define STM32_IRQ_OTGFSWKUP (58) /* 42: USB On-The-Go FS Wakeup through EXTI line interrupt */ -# define STM32_IRQ_RESERVED0 (59) /* 43: Reserved 0 */ -# define STM32_IRQ_RESERVED1 (60) /* 44: Reserved 1 */ -# define STM32_IRQ_RESERVED2 (61) /* 45: Reserved 2 */ -# define STM32_IRQ_RESERVED3 (62) /* 46: Reserved 3 */ -# define STM32_IRQ_RESERVED4 (63) /* 47: Reserved 4 */ -# define STM32_IRQ_RESERVED5 (64) /* 48: Reserved 5 */ -# define STM32_IRQ_RESERVED6 (65) /* 49: Reserved 6 */ -# define STM32_IRQ_TIM5 (66) /* 50: TIM5 global interrupt */ -# define STM32_IRQ_SPI3 (67) /* 51: SPI3 global interrupt */ -# define STM32_IRQ_UART4 (68) /* 52: UART4 global interrupt */ -# define STM32_IRQ_UART5 (69) /* 53: UART5 global interrupt */ -# define STM32_IRQ_TIM6 (70) /* 54: TIM6 global interrupt */ -# define STM32_IRQ_TIM7 (71) /* 55: TIM7 global interrupt */ -# define STM32_IRQ_DMA2CH1 (72) /* 56: DMA2 Channel 1 global interrupt */ -# define STM32_IRQ_DMA2CH2 (73) /* 57: DMA2 Channel 2 global interrupt */ -# define STM32_IRQ_DMA2CH3 (74) /* 58: DMA2 Channel 3 global interrupt */ -# define STM32_IRQ_DMA2CH4 (75) /* 59: DMA2 Channel 4 global interrupt */ -# define STM32_IRQ_DMA2CH5 (76) /* 60: DMA2 Channel 5 global interrupt */ -# define STM32_IRQ_ETH (77) /* 61: Ethernet global interrupt */ -# define STM32_IRQ_ETHWKUP (78) /* 62: Ethernet Wakeup through EXTI line interrupt */ -# define STM32_IRQ_CAN2TX (79) /* 63: CAN2 TX interrupts */ -# define STM32_IRQ_CAN2RX0 (80) /* 64: CAN2 RX0 interrupts */ -# define STM32_IRQ_CAN2RX1 (81) /* 65: CAN2 RX1 interrupt */ -# define STM32_IRQ_CAN2SCE (82) /* 66: CAN2 SCE interrupt */ -# define STM32_IRQ_OTGFS (83) /* 67: USB On The Go FS global interrupt */ - -# define STM32_IRQ_NEXTINTS (68) - -/* Medium and High Density Devices */ - -#else -# define STM32_IRQ_WWDG (16) /* 0: Window Watchdog interrupt */ -# define STM32_IRQ_PVD (17) /* 1: PVD through EXTI Line detection interrupt */ -# define STM32_IRQ_TAMPER (18) /* 2: Tamper interrupt */ -# define STM32_IRQ_RTC (19) /* 3: RTC global interrupt */ -# define STM32_IRQ_FLASH (20) /* 4: Flash global interrupt */ -# define STM32_IRQ_RCC (21) /* 5: RCC global interrupt */ -# define STM32_IRQ_EXTI0 (22) /* 6: EXTI Line 0 interrupt */ -# define STM32_IRQ_EXTI1 (23) /* 7: EXTI Line 1 interrupt */ -# define STM32_IRQ_EXTI2 (24) /* 8: EXTI Line 2 interrupt */ -# define STM32_IRQ_EXTI3 (25) /* 9: EXTI Line 3 interrupt */ -# define STM32_IRQ_EXTI4 (26) /* 10: EXTI Line 4 interrupt */ -# define STM32_IRQ_DMA1CH1 (27) /* 11: DMA1 Channel 1 global interrupt */ -# define STM32_IRQ_DMA1CH2 (28) /* 12: DMA1 Channel 2 global interrupt */ -# define STM32_IRQ_DMA1CH3 (29) /* 13: DMA1 Channel 3 global interrupt */ -# define STM32_IRQ_DMA1CH4 (30) /* 14: DMA1 Channel 4 global interrupt */ -# define STM32_IRQ_DMA1CH5 (31) /* 15: DMA1 Channel 5 global interrupt */ -# define STM32_IRQ_DMA1CH6 (32) /* 16: DMA1 Channel 6 global interrupt */ -# define STM32_IRQ_DMA1CH7 (33) /* 17: DMA1 Channel 7 global interrupt */ -# define STM32_IRQ_ADC12 (34) /* 18: ADC1 and ADC2 global interrupt */ -# define STM32_IRQ_USBHPCANTX (35) /* 19: USB High Priority or CAN TX interrupts*/ -# define STM32_IRQ_USBLPCANRX0 (36) /* 20: USB Low Priority or CAN RX0 interrupts*/ -# define STM32_IRQ_CAN1RX1 (37) /* 21: CAN1 RX1 interrupt */ -# define STM32_IRQ_CAN1SCE (38) /* 22: CAN1 SCE interrupt */ -# define STM32_IRQ_EXTI95 (39) /* 23: EXTI Line[9:5] interrupts */ -# define STM32_IRQ_TIM1BRK (40) /* 24: TIM1 Break interrupt */ -# define STM32_IRQ_TIM1UP (41) /* 25: TIM1 Update interrupt */ -# define STM32_IRQ_TIM1TRGCOM (42) /* 26: TIM1 Trigger and Commutation interrupts */ -# define STM32_IRQ_TIM1CC (43) /* 27: TIM1 Capture Compare interrupt */ -# define STM32_IRQ_TIM2 (44) /* 28: TIM2 global interrupt */ -# define STM32_IRQ_TIM3 (45) /* 29: TIM3 global interrupt */ -# define STM32_IRQ_TIM4 (46) /* 30: TIM4 global interrupt */ -# define STM32_IRQ_I2C1EV (47) /* 31: I2C1 event interrupt */ -# define STM32_IRQ_I2C1ER (48) /* 32: I2C1 error interrupt */ -# define STM32_IRQ_I2C2EV (49) /* 33: I2C2 event interrupt */ -# define STM32_IRQ_I2C2ER (50) /* 34: I2C2 error interrupt */ -# define STM32_IRQ_SPI1 (51) /* 35: SPI1 global interrupt */ -# define STM32_IRQ_SPI2 (52) /* 36: SPI2 global interrupt */ -# define STM32_IRQ_USART1 (53) /* 37: USART1 global interrupt */ -# define STM32_IRQ_USART2 (54) /* 38: USART2 global interrupt */ -# define STM32_IRQ_USART3 (55) /* 39: USART3 global interrupt */ -# define STM32_IRQ_EXTI1510 (56) /* 40: EXTI Line[15:10] interrupts */ -# define STM32_IRQ_RTCALRM (57) /* 41: RTC alarm through EXTI line interrupt */ -# define STM32_IRQ_USBWKUP (58) /* 42: USB wakeup from suspend through EXTI line interrupt*/ -# define STM32_IRQ_TIM8BRK (59) /* 43: TIM8 Break interrupt */ -# define STM32_IRQ_TIM8UP (60) /* 44: TIM8 Update interrupt */ -# define STM32_IRQ_TIM8TRGCOM (61) /* 45: TIM8 Trigger and Commutation interrupts */ -# define STM32_IRQ_TIM8CC (62) /* 46: TIM8 Capture Compare interrupt */ -# define STM32_IRQ_ADC3 (63) /* 47: ADC3 global interrupt */ -# define STM32_IRQ_FSMC (64) /* 48: FSMC global interrupt */ -# define STM32_IRQ_SDIO (65) /* 49: SDIO global interrupt */ -# define STM32_IRQ_TIM5 (66) /* 50: TIM5 global interrupt */ -# define STM32_IRQ_SPI3 (67) /* 51: SPI3 global interrupt */ -# define STM32_IRQ_UART4 (68) /* 52: UART4 global interrupt */ -# define STM32_IRQ_UART5 (69) /* 53: UART5 global interrupt */ -# define STM32_IRQ_TIM6 (70) /* 54: TIM6 global interrupt */ -# define STM32_IRQ_TIM7 (71) /* 55: TIM7 global interrupt */ -# define STM32_IRQ_DMA2CH1 (72) /* 56: DMA2 Channel 1 global interrupt */ -# define STM32_IRQ_DMA2CH2 (73) /* 57: DMA2 Channel 2 global interrupt */ -# define STM32_IRQ_DMA2CH3 (74) /* 58: DMA2 Channel 3 global interrupt */ -# define STM32_IRQ_DMA2CH45 (75) /* 59: DMA2 Channel 4&5 global interrupt */ - -# define STM32_IRQ_NEXTINTS (60) - -/* Convenience definitions for interrupts with multiple functions */ - -# define STM32_IRQ_USBHP STM32_IRQ_USBHPCANTX -# define STM32_IRQ_CAN1TX STM32_IRQ_USBHPCANTX -# define STM32_IRQ_USBLP STM32_IRQ_USBLPCANRX0 -# define STM32_IRQ_CAN1RX0 STM32_IRQ_USBLPCANRX0 -#endif - -# define NR_IRQS (STM32_IRQ_FIRST + STM32_IRQ_NEXTINTS) - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -#ifndef __ASSEMBLY__ -#ifdef __cplusplus -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -#undef EXTERN -#ifdef __cplusplus -} -#endif -#endif - -#endif /* __ARCH_ARM_INCLUDE_STM32_STM32F10XXX_IRQ_H */ diff --git a/arch/arm/include/stm32/stm32f20xxx_irq.h b/arch/arm/include/stm32/stm32f20xxx_irq.h deleted file mode 100644 index fddc984135928..0000000000000 --- a/arch/arm/include/stm32/stm32f20xxx_irq.h +++ /dev/null @@ -1,172 +0,0 @@ -/**************************************************************************** - * arch/arm/include/stm32/stm32f20xxx_irq.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* This file should never be included directly but, rather, only indirectly - * through nuttx/irq.h - */ - -#ifndef __ARCH_ARM_INCLUDE_STM32_STM32F20XXX_IRQ_H -#define __ARCH_ARM_INCLUDE_STM32_STM32F20XXX_IRQ_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include - -/**************************************************************************** - * Pre-processor Prototypes - ****************************************************************************/ - -/* IRQ numbers. The IRQ number corresponds vector number and hence map - * directly to bits in the NVIC. This does, however, waste several words of - * memory in the IRQ to handle mapping tables. - * - * Processor Exceptions (vectors 0-15). These common definitions can be - * found in nuttx/arch/arm/include/stm32/irq.h - * - * External interrupts (vectors >= 16) - */ - -#define STM32_IRQ_WWDG (STM32_IRQ_FIRST + 0) /* 0: Window Watchdog interrupt */ -#define STM32_IRQ_PVD (STM32_IRQ_FIRST + 1) /* 1: PVD through EXTI Line detection interrupt */ -#define STM32_IRQ_TAMPER (STM32_IRQ_FIRST + 2) /* 2: Tamper and time stamp interrupts */ -#define STM32_IRQ_TIMESTAMP (STM32_IRQ_FIRST + 2) /* 2: Tamper and time stamp interrupts */ -#define STM32_IRQ_RTC_WKUP (STM32_IRQ_FIRST + 3) /* 3: RTC global interrupt */ -#define STM32_IRQ_FLASH (STM32_IRQ_FIRST + 4) /* 4: Flash global interrupt */ -#define STM32_IRQ_RCC (STM32_IRQ_FIRST + 5) /* 5: RCC global interrupt */ -#define STM32_IRQ_EXTI0 (STM32_IRQ_FIRST + 6) /* 6: EXTI Line 0 interrupt */ -#define STM32_IRQ_EXTI1 (STM32_IRQ_FIRST + 7) /* 7: EXTI Line 1 interrupt */ -#define STM32_IRQ_EXTI2 (STM32_IRQ_FIRST + 8) /* 8: EXTI Line 2 interrupt */ -#define STM32_IRQ_EXTI3 (STM32_IRQ_FIRST + 9) /* 9: EXTI Line 3 interrupt */ -#define STM32_IRQ_EXTI4 (STM32_IRQ_FIRST + 10) /* 10: EXTI Line 4 interrupt */ -#define STM32_IRQ_DMA1S0 (STM32_IRQ_FIRST + 11) /* 11: DMA1 Stream 0 global interrupt */ -#define STM32_IRQ_DMA1S1 (STM32_IRQ_FIRST + 12) /* 12: DMA1 Stream 1 global interrupt */ -#define STM32_IRQ_DMA1S2 (STM32_IRQ_FIRST + 13) /* 13: DMA1 Stream 2 global interrupt */ -#define STM32_IRQ_DMA1S3 (STM32_IRQ_FIRST + 14) /* 14: DMA1 Stream 3 global interrupt */ -#define STM32_IRQ_DMA1S4 (STM32_IRQ_FIRST + 15) /* 15: DMA1 Stream 4 global interrupt */ -#define STM32_IRQ_DMA1S5 (STM32_IRQ_FIRST + 16) /* 16: DMA1 Stream 5 global interrupt */ -#define STM32_IRQ_DMA1S6 (STM32_IRQ_FIRST + 17) /* 17: DMA1 Stream 6 global interrupt */ -#define STM32_IRQ_ADC (STM32_IRQ_FIRST + 18) /* 18: ADC1, ADC2, and ADC3 global interrupt */ -#define STM32_IRQ_CAN1TX (STM32_IRQ_FIRST + 19) /* 19: CAN1 TX interrupts */ -#define STM32_IRQ_CAN1RX0 (STM32_IRQ_FIRST + 20) /* 20: CAN1 RX0 interrupts */ -#define STM32_IRQ_CAN1RX1 (STM32_IRQ_FIRST + 21) /* 21: CAN1 RX1 interrupt */ -#define STM32_IRQ_CAN1SCE (STM32_IRQ_FIRST + 22) /* 22: CAN1 SCE interrupt */ -#define STM32_IRQ_EXTI95 (STM32_IRQ_FIRST + 23) /* 23: EXTI Line[9:5] interrupts */ -#define STM32_IRQ_TIM1BRK (STM32_IRQ_FIRST + 24) /* 24: TIM1 Break interrupt */ -#define STM32_IRQ_TIM9 (STM32_IRQ_FIRST + 24) /* 24: TIM9 global interrupt */ -#define STM32_IRQ_TIM1UP (STM32_IRQ_FIRST + 25) /* 25: TIM1 Update interrupt */ -#define STM32_IRQ_TIM10 (STM32_IRQ_FIRST + 25) /* 25: TIM10 global interrupt */ -#define STM32_IRQ_TIM1TRGCOM (STM32_IRQ_FIRST + 26) /* 26: TIM1 Trigger and Commutation interrupts */ -#define STM32_IRQ_TIM11 (STM32_IRQ_FIRST + 26) /* 26: TIM11 global interrupt */ -#define STM32_IRQ_TIM1CC (STM32_IRQ_FIRST + 27) /* 27: TIM1 Capture Compare interrupt */ -#define STM32_IRQ_TIM2 (STM32_IRQ_FIRST + 28) /* 28: TIM2 global interrupt */ -#define STM32_IRQ_TIM3 (STM32_IRQ_FIRST + 29) /* 29: TIM3 global interrupt */ -#define STM32_IRQ_TIM4 (STM32_IRQ_FIRST + 30) /* 30: TIM4 global interrupt */ -#define STM32_IRQ_I2C1EV (STM32_IRQ_FIRST + 31) /* 31: I2C1 event interrupt */ -#define STM32_IRQ_I2C1ER (STM32_IRQ_FIRST + 32) /* 32: I2C1 error interrupt */ -#define STM32_IRQ_I2C2EV (STM32_IRQ_FIRST + 33) /* 33: I2C2 event interrupt */ -#define STM32_IRQ_I2C2ER (STM32_IRQ_FIRST + 34) /* 34: I2C2 error interrupt */ -#define STM32_IRQ_SPI1 (STM32_IRQ_FIRST + 35) /* 35: SPI1 global interrupt */ -#define STM32_IRQ_SPI2 (STM32_IRQ_FIRST + 36) /* 36: SPI2 global interrupt */ -#define STM32_IRQ_USART1 (STM32_IRQ_FIRST + 37) /* 37: USART1 global interrupt */ -#define STM32_IRQ_USART2 (STM32_IRQ_FIRST + 38) /* 38: USART2 global interrupt */ -#define STM32_IRQ_USART3 (STM32_IRQ_FIRST + 39) /* 39: USART3 global interrupt */ -#define STM32_IRQ_EXTI1510 (STM32_IRQ_FIRST + 40) /* 40: EXTI Line[15:10] interrupts */ -#define STM32_IRQ_RTCALRM (STM32_IRQ_FIRST + 41) /* 41: RTC alarm through EXTI line interrupt */ -#define STM32_IRQ_OTGFSWKUP (STM32_IRQ_FIRST + 42) /* 42: USB On-The-Go FS Wakeup through EXTI line interrupt */ -#define STM32_IRQ_TIM8BRK (STM32_IRQ_FIRST + 43) /* 43: TIM8 Break interrupt */ -#define STM32_IRQ_TIM12 (STM32_IRQ_FIRST + 43) /* 43: TIM12 global interrupt */ -#define STM32_IRQ_TIM8UP (STM32_IRQ_FIRST + 44) /* 44: TIM8 Update interrupt */ -#define STM32_IRQ_TIM13 (STM32_IRQ_FIRST + 44) /* 44: TIM13 global interrupt */ -#define STM32_IRQ_TIM8TRGCOM (STM32_IRQ_FIRST + 45) /* 45: TIM8 Trigger and Commutation interrupts */ -#define STM32_IRQ_TIM14 (STM32_IRQ_FIRST + 45) /* 45: TIM14 global interrupt */ -#define STM32_IRQ_TIM8CC (STM32_IRQ_FIRST + 46) /* 46: TIM8 Capture Compare interrupt */ -#define STM32_IRQ_DMA1S7 (STM32_IRQ_FIRST + 47) /* 47: DMA1 Stream 7 global interrupt */ -#define STM32_IRQ_FSMC (STM32_IRQ_FIRST + 48) /* 48: FSMC global interrupt */ -#define STM32_IRQ_SDIO (STM32_IRQ_FIRST + 49) /* 49: SDIO global interrupt */ -#define STM32_IRQ_TIM5 (STM32_IRQ_FIRST + 50) /* 50: TIM5 global interrupt */ -#define STM32_IRQ_SPI3 (STM32_IRQ_FIRST + 51) /* 51: SPI3 global interrupt */ -#define STM32_IRQ_UART4 (STM32_IRQ_FIRST + 52) /* 52: UART4 global interrupt */ -#define STM32_IRQ_UART5 (STM32_IRQ_FIRST + 53) /* 53: UART5 global interrupt */ -#define STM32_IRQ_TIM6 (STM32_IRQ_FIRST + 54) /* 54: TIM6 global interrupt */ -#define STM32_IRQ_DAC (STM32_IRQ_FIRST + 54) /* 54: DAC1 and DAC2 underrun error interrupts */ -#define STM32_IRQ_TIM7 (STM32_IRQ_FIRST + 55) /* 55: TIM7 global interrupt */ -#define STM32_IRQ_DMA2S0 (STM32_IRQ_FIRST + 56) /* 56: DMA2 Stream 0 global interrupt */ -#define STM32_IRQ_DMA2S1 (STM32_IRQ_FIRST + 57) /* 57: DMA2 Stream 1 global interrupt */ -#define STM32_IRQ_DMA2S2 (STM32_IRQ_FIRST + 58) /* 58: DMA2 Stream 2 global interrupt */ -#define STM32_IRQ_DMA2S3 (STM32_IRQ_FIRST + 59) /* 59: DMA2 Stream 3 global interrupt */ -#define STM32_IRQ_DMA2S4 (STM32_IRQ_FIRST + 60) /* 60: DMA2 Stream 4 global interrupt */ -#define STM32_IRQ_ETH (STM32_IRQ_FIRST + 61) /* 61: Ethernet global interrupt */ -#define STM32_IRQ_ETHWKUP (STM32_IRQ_FIRST + 62) /* 62: Ethernet Wakeup through EXTI line interrupt */ -#define STM32_IRQ_CAN2TX (STM32_IRQ_FIRST + 63) /* 63: CAN2 TX interrupts */ -#define STM32_IRQ_CAN2RX0 (STM32_IRQ_FIRST + 64) /* 64: CAN2 RX0 interrupts */ -#define STM32_IRQ_CAN2RX1 (STM32_IRQ_FIRST + 65) /* 65: CAN2 RX1 interrupt */ -#define STM32_IRQ_CAN2SCE (STM32_IRQ_FIRST + 66) /* 66: CAN2 SCE interrupt */ -#define STM32_IRQ_OTGFS (STM32_IRQ_FIRST + 67) /* 67: USB On The Go FS global interrupt */ -#define STM32_IRQ_DMA2S5 (STM32_IRQ_FIRST + 68) /* 68: DMA2 Stream 5 global interrupt */ -#define STM32_IRQ_DMA2S6 (STM32_IRQ_FIRST + 69) /* 69: DMA2 Stream 6 global interrupt */ -#define STM32_IRQ_DMA2S7 (STM32_IRQ_FIRST + 70) /* 70: DMA2 Stream 7 global interrupt */ -#define STM32_IRQ_USART6 (STM32_IRQ_FIRST + 71) /* 71: USART6 global interrupt */ -#define STM32_IRQ_I2C3EV (STM32_IRQ_FIRST + 72) /* 72: I2C3 event interrupt */ -#define STM32_IRQ_I2C3ER (STM32_IRQ_FIRST + 73) /* 73: I2C3 error interrupt */ -#define STM32_IRQ_OTGHSEP1OUT (STM32_IRQ_FIRST + 74) /* 74: USB On The Go HS End Point 1 Out global interrupt */ -#define STM32_IRQ_OTGHSEP1IN (STM32_IRQ_FIRST + 75) /* 75: USB On The Go HS End Point 1 In global interrupt */ -#define STM32_IRQ_OTGHSWKUP (STM32_IRQ_FIRST + 76) /* 76: USB On The Go HS Wakeup through EXTI interrupt */ -#define STM32_IRQ_OTGHS (STM32_IRQ_FIRST + 77) /* 77: USB On The Go HS global interrupt */ -#define STM32_IRQ_DCMI (STM32_IRQ_FIRST + 78) /* 78: DCMI global interrupt */ -#define STM32_IRQ_CRYP (STM32_IRQ_FIRST + 79) /* 79: CRYP crypto global interrupt */ -#define STM32_IRQ_HASH (STM32_IRQ_FIRST + 80) /* 80: Hash and Rng global interrupt */ -#define STM32_IRQ_RNG (STM32_IRQ_FIRST + 80) /* 80: Hash and Rng global interrupt */ - -#define STM32_IRQ_NEXTINTS (81) -#define NR_IRQS (STM32_IRQ_FIRST + STM32_IRQ_NEXTINTS) - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -#ifndef __ASSEMBLY__ -#ifdef __cplusplus -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -#undef EXTERN -#ifdef __cplusplus -} -#endif -#endif - -#endif /* __ARCH_ARM_INCLUDE_STM32_STM32F20XXX_IRQ_H */ diff --git a/arch/arm/include/stm32/stm32f40xxx_irq.h b/arch/arm/include/stm32/stm32f40xxx_irq.h deleted file mode 100644 index 268bcc2323bf1..0000000000000 --- a/arch/arm/include/stm32/stm32f40xxx_irq.h +++ /dev/null @@ -1,347 +0,0 @@ -/**************************************************************************** - * arch/arm/include/stm32/stm32f40xxx_irq.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* This file should never be included directly but, rather, - * only indirectly through nuttx/irq.h - */ - -#ifndef __ARCH_ARM_INCLUDE_STM32_STM32F40XXX_IRQ_H -#define __ARCH_ARM_INCLUDE_STM32_STM32F40XXX_IRQ_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include - -/**************************************************************************** - * Pre-processor Prototypes - ****************************************************************************/ - -/* IRQ numbers. - * The IRQ number corresponds vector number and hence map directly to - * bits in the NVIC. This does, however, waste several words of memory in - * the IRQ to handle mapping tables. - * - * Processor Exceptions (vectors 0-15). These common definitions can - * be found in nuttx/arch/arm/include/stm32/irq.h - * - * External interrupts (vectors >= 16) - */ - -#define STM32_IRQ_WWDG (STM32_IRQ_FIRST+0) /* 0: Window Watchdog interrupt */ -#define STM32_IRQ_PVD (STM32_IRQ_FIRST+1) /* 1: PVD through EXTI Line detection interrupt */ -#define STM32_IRQ_TAMPER (STM32_IRQ_FIRST+2) /* 2: Tamper and time stamp interrupts */ -#define STM32_IRQ_TIMESTAMP (STM32_IRQ_FIRST+2) /* 2: Tamper and time stamp interrupts */ -#define STM32_IRQ_RTC_WKUP (STM32_IRQ_FIRST+3) /* 3: RTC global interrupt */ -#define STM32_IRQ_FLASH (STM32_IRQ_FIRST+4) /* 4: Flash global interrupt */ -#define STM32_IRQ_RCC (STM32_IRQ_FIRST+5) /* 5: RCC global interrupt */ -#define STM32_IRQ_EXTI0 (STM32_IRQ_FIRST+6) /* 6: EXTI Line 0 interrupt */ -#define STM32_IRQ_EXTI1 (STM32_IRQ_FIRST+7) /* 7: EXTI Line 1 interrupt */ -#define STM32_IRQ_EXTI2 (STM32_IRQ_FIRST+8) /* 8: EXTI Line 2 interrupt */ -#define STM32_IRQ_EXTI3 (STM32_IRQ_FIRST+9) /* 9: EXTI Line 3 interrupt */ -#define STM32_IRQ_EXTI4 (STM32_IRQ_FIRST+10) /* 10: EXTI Line 4 interrupt */ -#define STM32_IRQ_DMA1S0 (STM32_IRQ_FIRST+11) /* 11: DMA1 Stream 0 global interrupt */ -#define STM32_IRQ_DMA1S1 (STM32_IRQ_FIRST+12) /* 12: DMA1 Stream 1 global interrupt */ -#define STM32_IRQ_DMA1S2 (STM32_IRQ_FIRST+13) /* 13: DMA1 Stream 2 global interrupt */ -#define STM32_IRQ_DMA1S3 (STM32_IRQ_FIRST+14) /* 14: DMA1 Stream 3 global interrupt */ -#define STM32_IRQ_DMA1S4 (STM32_IRQ_FIRST+15) /* 15: DMA1 Stream 4 global interrupt */ -#define STM32_IRQ_DMA1S5 (STM32_IRQ_FIRST+16) /* 16: DMA1 Stream 5 global interrupt */ -#define STM32_IRQ_DMA1S6 (STM32_IRQ_FIRST+17) /* 17: DMA1 Stream 6 global interrupt */ -#define STM32_IRQ_ADC (STM32_IRQ_FIRST+18) /* 18: ADC1, ADC2, and ADC3 global interrupt */ - -#if defined(CONFIG_STM32_STM32F410) -# define STM32_IRQ_RESERVED19 (STM32_IRQ_FIRST+19) /* 19: Reserved */ -# define STM32_IRQ_RESERVED20 (STM32_IRQ_FIRST+20) /* 20: Reserved */ -# define STM32_IRQ_RESERVED21 (STM32_IRQ_FIRST+21) /* 21: Reserved */ -# define STM32_IRQ_RESERVED22 (STM32_IRQ_FIRST+22) /* 22: Reserved */ -#else -# define STM32_IRQ_CAN1TX (STM32_IRQ_FIRST+19) /* 19: CAN1 TX interrupts */ -# define STM32_IRQ_CAN1RX0 (STM32_IRQ_FIRST+20) /* 20: CAN1 RX0 interrupts */ -# define STM32_IRQ_CAN1RX1 (STM32_IRQ_FIRST+21) /* 21: CAN1 RX1 interrupt */ -# define STM32_IRQ_CAN1SCE (STM32_IRQ_FIRST+22) /* 22: CAN1 SCE interrupt */ -#endif - -#define STM32_IRQ_EXTI95 (STM32_IRQ_FIRST+23) /* 23: EXTI Line[9:5] interrupts */ -#define STM32_IRQ_TIM1BRK (STM32_IRQ_FIRST+24) /* 24: TIM1 Break interrupt */ -#define STM32_IRQ_TIM9 (STM32_IRQ_FIRST+24) /* 24: TIM9 global interrupt */ -#define STM32_IRQ_TIM1UP (STM32_IRQ_FIRST+25) /* 25: TIM1 Update interrupt */ -#define STM32_IRQ_TIM10 (STM32_IRQ_FIRST+25) /* 25: TIM10 global interrupt */ -#define STM32_IRQ_TIM1TRGCOM (STM32_IRQ_FIRST+26) /* 26: TIM1 Trigger and Commutation interrupts */ -#define STM32_IRQ_TIM11 (STM32_IRQ_FIRST+26) /* 26: TIM11 global interrupt */ -#define STM32_IRQ_TIM1CC (STM32_IRQ_FIRST+27) /* 27: TIM1 Capture Compare interrupt */ - -#if defined(CONFIG_STM32_STM32F410) -# define STM32_IRQ_RESERVED28 (STM32_IRQ_FIRST+28) /* 28: Reserved */ -# define STM32_IRQ_RESERVED29 (STM32_IRQ_FIRST+29) /* 29: Reserved */ -# define STM32_IRQ_RESERVED30 (STM32_IRQ_FIRST+30) /* 30: Reserved */ -#else -# define STM32_IRQ_TIM2 (STM32_IRQ_FIRST+28) /* 28: TIM2 global interrupt */ -# define STM32_IRQ_TIM3 (STM32_IRQ_FIRST+29) /* 29: TIM3 global interrupt */ -# define STM32_IRQ_TIM4 (STM32_IRQ_FIRST+30) /* 30: TIM4 global interrupt */ -#endif - -#define STM32_IRQ_I2C1EV (STM32_IRQ_FIRST+31) /* 31: I2C1 event interrupt */ -#define STM32_IRQ_I2C1ER (STM32_IRQ_FIRST+32) /* 32: I2C1 error interrupt */ -#define STM32_IRQ_I2C2EV (STM32_IRQ_FIRST+33) /* 33: I2C2 event interrupt */ -#define STM32_IRQ_I2C2ER (STM32_IRQ_FIRST+34) /* 34: I2C2 error interrupt */ -#define STM32_IRQ_SPI1 (STM32_IRQ_FIRST+35) /* 35: SPI1 global interrupt */ -#define STM32_IRQ_SPI2 (STM32_IRQ_FIRST+36) /* 36: SPI2 global interrupt */ -#define STM32_IRQ_USART1 (STM32_IRQ_FIRST+37) /* 37: USART1 global interrupt */ -#define STM32_IRQ_USART2 (STM32_IRQ_FIRST+38) /* 38: USART2 global interrupt */ - -#if defined(CONFIG_STM32_STM32F410) -# define STM32_IRQ_RESERVED39 (STM32_IRQ_FIRST+39) /* 39: Reserved */ -#else -# define STM32_IRQ_USART3 (STM32_IRQ_FIRST+39) /* 39: USART3 global interrupt */ -#endif - -#define STM32_IRQ_EXTI1510 (STM32_IRQ_FIRST+40) /* 40: EXTI Line[15:10] interrupts */ -#define STM32_IRQ_RTCALRM (STM32_IRQ_FIRST+41) /* 41: RTC alarm through EXTI line interrupt */ - -#if defined(CONFIG_STM32_STM32F410) -# define STM32_IRQ_RESERVED42 (STM32_IRQ_FIRST+42) /* 42: Reserved */ -# define STM32_IRQ_RESERVED43 (STM32_IRQ_FIRST+43) /* 43: Reserved */ -# define STM32_IRQ_RESERVED44 (STM32_IRQ_FIRST+44) /* 44: Reserved */ -# define STM32_IRQ_RESERVED45 (STM32_IRQ_FIRST+45) /* 45: Reserved */ -# define STM32_IRQ_RESERVED46 (STM32_IRQ_FIRST+46) /* 46: Reserved */ -#else -# define STM32_IRQ_OTGFSWKUP (STM32_IRQ_FIRST+42) /* 42: USB On-The-Go FS Wakeup through EXTI line interrupt */ -# define STM32_IRQ_TIM8BRK (STM32_IRQ_FIRST+43) /* 43: TIM8 Break interrupt */ -# define STM32_IRQ_TIM12 (STM32_IRQ_FIRST+43) /* 43: TIM12 global interrupt */ -# define STM32_IRQ_TIM8UP (STM32_IRQ_FIRST+44) /* 44: TIM8 Update interrupt */ -# define STM32_IRQ_TIM13 (STM32_IRQ_FIRST+44) /* 44: TIM13 global interrupt */ -# define STM32_IRQ_TIM8TRGCOM (STM32_IRQ_FIRST+45) /* 45: TIM8 Trigger and Commutation interrupts */ -# define STM32_IRQ_TIM14 (STM32_IRQ_FIRST+45) /* 45: TIM14 global interrupt */ -# define STM32_IRQ_TIM8CC (STM32_IRQ_FIRST+46) /* 46: TIM8 Capture Compare interrupt */ -#endif - -#define STM32_IRQ_DMA1S7 (STM32_IRQ_FIRST+47) /* 47: DMA1 Stream 7 global interrupt */ - -#if defined(CONFIG_STM32_STM32F410) -# define STM32_IRQ_RESERVED48 (STM32_IRQ_FIRST+48) /* 48: Reserved */ -# define STM32_IRQ_RESERVED49 (STM32_IRQ_FIRST+49) /* 48: Reserved */ -#else -# define STM32_IRQ_FSMC (STM32_IRQ_FIRST+48) /* 48: FSMC global interrupt */ -# define STM32_IRQ_SDIO (STM32_IRQ_FIRST+49) /* 49: SDIO global interrupt */ -#endif - -#define STM32_IRQ_TIM5 (STM32_IRQ_FIRST+50) /* 50: TIM5 global interrupt */ - -#if defined(CONFIG_STM32_STM32F410) -# define STM32_IRQ_RESERVED51 (STM32_IRQ_FIRST+51) /* 51: Reserved */ -# define STM32_IRQ_RESERVED52 (STM32_IRQ_FIRST+52) /* 52: Reserved */ -# define STM32_IRQ_RESERVED53 (STM32_IRQ_FIRST+53) /* 53: Reserved */ -#else -# define STM32_IRQ_SPI3 (STM32_IRQ_FIRST+51) /* 51: SPI3 global interrupt */ -# define STM32_IRQ_UART4 (STM32_IRQ_FIRST+52) /* 52: UART4 global interrupt */ -# define STM32_IRQ_UART5 (STM32_IRQ_FIRST+53) /* 53: UART5 global interrupt */ -#endif - -#define STM32_IRQ_TIM6 (STM32_IRQ_FIRST+54) /* 54: TIM6 global interrupt */ -#define STM32_IRQ_DAC (STM32_IRQ_FIRST+54) /* 54: DAC1 and DAC2 underrun error interrupts */ - -#if defined(CONFIG_STM32_STM32F410) -# define STM32_IRQ_RESERVED55 (STM32_IRQ_FIRST+55) /* 55: Reserved */ -#else -# define STM32_IRQ_TIM7 (STM32_IRQ_FIRST+55) /* 55: TIM7 global interrupt */ -#endif - -#define STM32_IRQ_DMA2S0 (STM32_IRQ_FIRST+56) /* 56: DMA2 Stream 0 global interrupt */ -#define STM32_IRQ_DMA2S1 (STM32_IRQ_FIRST+57) /* 57: DMA2 Stream 1 global interrupt */ -#define STM32_IRQ_DMA2S2 (STM32_IRQ_FIRST+58) /* 58: DMA2 Stream 2 global interrupt */ -#define STM32_IRQ_DMA2S3 (STM32_IRQ_FIRST+59) /* 59: DMA2 Stream 3 global interrupt */ -#define STM32_IRQ_DMA2S4 (STM32_IRQ_FIRST+60) /* 60: DMA2 Stream 4 global interrupt */ - -#if defined(CONFIG_STM32_STM32F446) -# define STM32_IRQ_RESERVED61 (STM32_IRQ_FIRST+61) /* 61: Reserved */ -# define STM32_IRQ_RESERVED62 (STM32_IRQ_FIRST+62) /* 62: Reserved */ -#else -# define STM32_IRQ_ETH (STM32_IRQ_FIRST+61) /* 61: Ethernet global interrupt */ -# define STM32_IRQ_ETHWKUP (STM32_IRQ_FIRST+62) /* 62: Ethernet Wakeup through EXTI line interrupt */ -#endif - -#if defined(CONFIG_STM32_STM32F410) -# define STM32_IRQ_RESERVED63 (STM32_IRQ_FIRST+63) /* 63: Reserved */ -# define STM32_IRQ_RESERVED64 (STM32_IRQ_FIRST+64) /* 63: Reserved */ -# define STM32_IRQ_RESERVED65 (STM32_IRQ_FIRST+65) /* 63: Reserved */ -# define STM32_IRQ_RESERVED66 (STM32_IRQ_FIRST+66) /* 63: Reserved */ -# define STM32_IRQ_RESERVED67 (STM32_IRQ_FIRST+67) /* 63: Reserved */ -#else -# define STM32_IRQ_CAN2TX (STM32_IRQ_FIRST+63) /* 63: CAN2 TX interrupts */ -# define STM32_IRQ_CAN2RX0 (STM32_IRQ_FIRST+64) /* 64: CAN2 RX0 interrupts */ -# define STM32_IRQ_CAN2RX1 (STM32_IRQ_FIRST+65) /* 65: CAN2 RX1 interrupt */ -# define STM32_IRQ_CAN2SCE (STM32_IRQ_FIRST+66) /* 66: CAN2 SCE interrupt */ -# define STM32_IRQ_OTGFS (STM32_IRQ_FIRST+67) /* 67: USB On The Go FS global interrupt */ -#endif - -#define STM32_IRQ_DMA2S5 (STM32_IRQ_FIRST+68) /* 68: DMA2 Stream 5 global interrupt */ -#define STM32_IRQ_DMA2S6 (STM32_IRQ_FIRST+69) /* 69: DMA2 Stream 6 global interrupt */ -#define STM32_IRQ_DMA2S7 (STM32_IRQ_FIRST+70) /* 70: DMA2 Stream 7 global interrupt */ -#define STM32_IRQ_USART6 (STM32_IRQ_FIRST+71) /* 71: USART6 global interrupt */ - -#if defined(CONFIG_STM32_STM32F410) -# define STM32_IRQ_RESERVED72 (STM32_IRQ_FIRST+72) /* 72: Reserved */ -# define STM32_IRQ_RESERVED73 (STM32_IRQ_FIRST+73) /* 73: Reserved */ -# define STM32_IRQ_RESERVED74 (STM32_IRQ_FIRST+74) /* 74: Reserved */ -# define STM32_IRQ_RESERVED75 (STM32_IRQ_FIRST+75) /* 75: Reserved */ -# define STM32_IRQ_RESERVED76 (STM32_IRQ_FIRST+76) /* 76: Reserved */ -# define STM32_IRQ_RESERVED77 (STM32_IRQ_FIRST+77) /* 77: Reserved */ -# define STM32_IRQ_RESERVED78 (STM32_IRQ_FIRST+78) /* 78: Reserved */ -#else -# define STM32_IRQ_I2C3EV (STM32_IRQ_FIRST+72) /* 72: I2C3 event interrupt */ -# define STM32_IRQ_I2C3ER (STM32_IRQ_FIRST+73) /* 73: I2C3 error interrupt */ -# define STM32_IRQ_OTGHSEP1OUT (STM32_IRQ_FIRST+74) /* 74: USB On The Go HS End Point 1 Out global interrupt */ -# define STM32_IRQ_OTGHSEP1IN (STM32_IRQ_FIRST+75) /* 75: USB On The Go HS End Point 1 In global interrupt */ -# define STM32_IRQ_OTGHSWKUP (STM32_IRQ_FIRST+76) /* 76: USB On The Go HS Wakeup through EXTI interrupt */ -# define STM32_IRQ_OTGHS (STM32_IRQ_FIRST+77) /* 77: USB On The Go HS global interrupt */ -# define STM32_IRQ_DCMI (STM32_IRQ_FIRST+78) /* 78: DCMI global interrupt */ -#endif - -#if defined(CONFIG_STM32_STM32F446) -# define STM32_IRQ_RESERVED79 (STM32_IRQ_FIRST+79) /* 79: Reserved */ -# define STM32_IRQ_RESERVED80 (STM32_IRQ_FIRST+80) /* 80: Reserved */ -#else -# if defined(CONFIG_STM32_STM32F410) -# define STM32_IRQ_RESERVED79 (STM32_IRQ_FIRST+79) /* 79: Reserved */ -# else -# define STM32_IRQ_CRYP (STM32_IRQ_FIRST+79) /* 79: CRYP crypto global interrupt */ -# endif -# define STM32_IRQ_HASH (STM32_IRQ_FIRST+80) /* 80: Hash and Rng global interrupt */ -# define STM32_IRQ_RNG (STM32_IRQ_FIRST+80) /* 80: Hash and Rng global interrupt */ -#endif - -#define STM32_IRQ_FPU (STM32_IRQ_FIRST+81) /* 81: FPU global interrupt */ - -#if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429) || \ - defined(CONFIG_STM32_STM32F469) -# define STM32_IRQ_UART7 (STM32_IRQ_FIRST+82) /* 82: UART7 interrupt */ -# define STM32_IRQ_UART8 (STM32_IRQ_FIRST+83) /* 83: UART8 interrupt */ -#elif defined(CONFIG_STM32_STM32F446) || defined(CONFIG_STM32_STM32F410) -# define STM32_IRQ_RESERVED82 (STM32_IRQ_FIRST+82) /* 82: Reserved */ -# define STM32_IRQ_RESERVED83 (STM32_IRQ_FIRST+83) /* 83: Reserved */ -#endif - -#if defined(CONFIG_STM32_STM32F410) -# define STM32_IRQ_RESERVED84 (STM32_IRQ_FIRST+84) /* 84: Reserved */ -#elif defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429) || \ - defined(CONFIG_STM32_STM32F446) || defined(CONFIG_STM32_STM32F469) -# define STM32_IRQ_SPI4 (STM32_IRQ_FIRST+84) /* 84: SPI4 interrupt */ -#endif - -#if defined(CONFIG_STM32_STM32F410) -# define STM32_IRQ_SPI5 (STM32_IRQ_FIRST+85) /* 85: SPI5 interrupt */ -# define STM32_IRQ_RESERVED86 (STM32_IRQ_FIRST+86) /* 86: Reserved */ -#elif defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429) || \ - defined(CONFIG_STM32_STM32F469) -# define STM32_IRQ_SPI5 (STM32_IRQ_FIRST+85) /* 85: SPI5 interrupt */ -# define STM32_IRQ_SPI6 (STM32_IRQ_FIRST+86) /* 86: SPI6 interrupt */ -#elif defined(CONFIG_STM32_STM32F446) -# define STM32_IRQ_RESERVED85 (STM32_IRQ_FIRST+85) /* 85: Reserved */ -# define STM32_IRQ_RESERVED86 (STM32_IRQ_FIRST+86) /* 86: Reserved */ -#endif - -#if defined(CONFIG_STM32_STM32F410) -# define STM32_IRQ_RESERVED87 (STM32_IRQ_FIRST+87) /* 87: Reserved */ -#elif defined(CONFIG_STM32_STM32F429) || defined(CONFIG_STM32_STM32F446) || \ - defined(CONFIG_STM32_STM32F446) || defined(CONFIG_STM32_STM32F469) -# define STM32_IRQ_SAI1 (STM32_IRQ_FIRST+87) /* 87: SAI1 interrupt */ -#endif - -#if defined(CONFIG_STM32_STM32F429) || defined(CONFIG_STM32_STM32F469) -# define STM32_IRQ_LTDCINT (STM32_IRQ_FIRST+88) /* 88: LTDCINT interrupt */ -# define STM32_IRQ_LTDCERRINT (STM32_IRQ_FIRST+89) /* 89: LTDCERRINT interrupt */ -# define STM32_IRQ_DMA2D (STM32_IRQ_FIRST+90) /* 90: DMA2D interrupt */ -#elif defined(CONFIG_STM32_STM32F446) || defined(CONFIG_STM32_STM32F410) -# define STM32_IRQ_RESERVED88 (STM32_IRQ_FIRST+88) /* 88: Reserved */ -# define STM32_IRQ_RESERVED89 (STM32_IRQ_FIRST+89) /* 89: Reserved */ -# define STM32_IRQ_RESERVED90 (STM32_IRQ_FIRST+90) /* 90: Reserved */ -#endif - -#if defined(CONFIG_STM32_STM32F410) -# define STM32_IRQ_RESERVED91 (STM32_IRQ_FIRST+91) /* 91: Reserved */ -# define STM32_IRQ_RESERVED92 (STM32_IRQ_FIRST+92) /* 92: Reserved */ -#elif defined(CONFIG_STM32_STM32F446) -# define STM32_IRQ_SAI2 (STM32_IRQ_FIRST+91) /* 91: SAI2 Global interrupt */ -# define STM32_IRQ_QUADSPI (STM32_IRQ_FIRST+92) /* 92: QuadSPI Global interrupt */ -#elif defined(CONFIG_STM32_STM32F469) -# define STM32_IRQ_QUADSPI (STM32_IRQ_FIRST+91) /* 92: QuadSPI Global interrupt */ -# define STM32_IRQ_DSI (STM32_IRQ_FIRST+92) /* 91: DSI Global interrupt */ -#endif - -#if defined(CONFIG_STM32_STM32F446) -# define STM32_IRQ_HDMICEC (STM32_IRQ_FIRST+93) /* 93: HDMI-CEC Global interrupt */ -# define STM32_IRQ_SPDIFRX (STM32_IRQ_FIRST+94) /* 94: SPDIF-Rx Global interrupt */ -# define STM32_IRQ_FMPI2C1 (STM32_IRQ_FIRST+95) /* 95: FMPI2C1 event interrupt */ -# define STM32_IRQ_FMPI2C1ERR (STM32_IRQ_FIRST+96) /* 96: FMPI2C1 Error event interrupt */ -#endif - -#if defined(CONFIG_STM32_STM32F410) -# define STM32_IRQ_RESERVED93 (STM32_IRQ_FIRST+93) /* 93: Reserved */ -# define STM32_IRQ_RESERVED94 (STM32_IRQ_FIRST+94) /* 94: Reserved */ -# define STM32_IRQ_RESERVED95 (STM32_IRQ_FIRST+95) /* 95: Reserved */ -# define STM32_IRQ_RESERVED96 (STM32_IRQ_FIRST+96) /* 96: Reserved */ -# define STM32_IRQ_RESERVED97 (STM32_IRQ_FIRST+97) /* 97: Reserved */ -#endif - -#if defined(CONFIG_STM32_STM32F401) || defined(CONFIG_STM32_STM32F411) || \ - defined(CONFIG_STM32_STM32F405) || defined(CONFIG_STM32_STM32F407) -# define STM32_IRQ_NEXTINTS (82) -#elif defined(CONFIG_STM32_STM32F410) -# define STM32_IRQ_NEXTINTS (98) -#elif defined(CONFIG_STM32_STM32F427) -# define STM32_IRQ_NEXTINTS (87) -#elif defined(CONFIG_STM32_STM32F429) -# define STM32_IRQ_NEXTINTS (91) -#elif defined(CONFIG_STM32_STM32F446) || defined(CONFIG_STM32_STM32F412) -# define STM32_IRQ_NEXTINTS (97) -#elif defined(CONFIG_STM32_STM32F469) -# define STM32_IRQ_NEXTINTS (93) -#endif - -# define NR_IRQS (STM32_IRQ_FIRST+STM32_IRQ_NEXTINTS) - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -#ifndef __ASSEMBLY__ -#ifdef __cplusplus -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -#undef EXTERN -#ifdef __cplusplus -} -#endif -#endif - -#endif /* __ARCH_ARM_INCLUDE_STM32_STM32F40XXX_IRQ_H */ diff --git a/arch/arm/include/stm32/stm32g4xxxx_irq.h b/arch/arm/include/stm32/stm32g4xxxx_irq.h deleted file mode 100644 index 1d0418be96a18..0000000000000 --- a/arch/arm/include/stm32/stm32g4xxxx_irq.h +++ /dev/null @@ -1,202 +0,0 @@ -/**************************************************************************** - * arch/arm/include/stm32/stm32g4xxxx_irq.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* This file should never be included directly but, rather, only indirectly - * through nuttx/irq.h - */ - -#ifndef __ARCH_ARM_INCLUDE_STM32_STM32G4XXXX_IRQ_H -#define __ARCH_ARM_INCLUDE_STM32_STM32G4XXXX_IRQ_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include - -/**************************************************************************** - * Pre-processor Prototypes - ****************************************************************************/ - -/* IRQ numbers. The IRQ numbers correspond to the vector numbers and hence - * map directly to bits in the NVIC. This does, however, waste several words - * of memory in the IRQ to handle mapping tables. - * - * Processor Exceptions (vectors 0-15) are common to all STM32 parts and are - * found in nuttx/arch/arm/include/stm32/irq.h. They are not repeated here. - * - * Other interrupts (vectors >= 16) are defined below. - */ - -#define STM32_IRQ_WWDG (STM32_IRQ_FIRST + 0) /* 0: Window Watchdog interrupt */ -#define STM32_IRQ_PVD (STM32_IRQ_FIRST + 1) /* 1: PVD through EXTI Line detection interrupt */ -#define STM32_IRQ_TAMPER (STM32_IRQ_FIRST + 2) /* 2: Tamper interrupt, or Time Stamp (shared with STM32_IRQ_TIMESTAMP) */ -#define STM32_IRQ_TIMESTAMP (STM32_IRQ_FIRST + 2) /* 2: Time stamp interrupt (shared with STM32_IRQ_TAMPER) */ -#define STM32_IRQ_RTC_WKUP (STM32_IRQ_FIRST + 3) /* 3: RTC global interrupt */ -#define STM32_IRQ_FLASH (STM32_IRQ_FIRST + 4) /* 4: Flash global interrupt */ -#define STM32_IRQ_RCC (STM32_IRQ_FIRST + 5) /* 5: RCC global interrupt */ -#define STM32_IRQ_EXTI0 (STM32_IRQ_FIRST + 6) /* 6: EXTI Line 0 interrupt */ -#define STM32_IRQ_EXTI1 (STM32_IRQ_FIRST + 7) /* 7: EXTI Line 1 interrupt */ -#define STM32_IRQ_EXTI2 (STM32_IRQ_FIRST + 8) /* 8: EXTI Line 2 interrupt, or */ -#define STM32_IRQ_EXTI3 (STM32_IRQ_FIRST + 9) /* 9: EXTI Line 3 interrupt */ - -#define STM32_IRQ_EXTI4 (STM32_IRQ_FIRST + 10) /* 10: EXTI Line 4 interrupt */ -#define STM32_IRQ_DMA1CH1 (STM32_IRQ_FIRST + 11) /* 11: DMA1 channel 1 global interrupt */ -#define STM32_IRQ_DMA1CH2 (STM32_IRQ_FIRST + 12) /* 12: DMA1 channel 2 global interrupt */ -#define STM32_IRQ_DMA1CH3 (STM32_IRQ_FIRST + 13) /* 13: DMA1 channel 3 global interrupt */ -#define STM32_IRQ_DMA1CH4 (STM32_IRQ_FIRST + 14) /* 14: DMA1 channel 4 global interrupt */ -#define STM32_IRQ_DMA1CH5 (STM32_IRQ_FIRST + 15) /* 15: DMA1 channel 5 global interrupt */ -#define STM32_IRQ_DMA1CH6 (STM32_IRQ_FIRST + 16) /* 16: DMA1 channel 6 global interrupt */ -#define STM32_IRQ_DMA1CH7 (STM32_IRQ_FIRST + 17) /* 17: DMA1 channel 7 global interrupt */ -#define STM32_IRQ_ADC12 (STM32_IRQ_FIRST + 18) /* 18: ADC1 and ADC2 shared global interrupt */ -#define STM32_IRQ_USBHP (STM32_IRQ_FIRST + 19) /* 19: USB High priority interrupt */ - -#define STM32_IRQ_USBLP (STM32_IRQ_FIRST + 20) /* 20: USB Low priority interrupt */ -#define STM32_IRQ_FDCAN1_0 (STM32_IRQ_FIRST + 21) /* 21: FDCAN1 interrupt 0 */ -#define STM32_IRQ_FDCAN1_1 (STM32_IRQ_FIRST + 22) /* 22: FDCAN1 interrupt 1 */ -#define STM32_IRQ_EXTI95 (STM32_IRQ_FIRST + 23) /* 23: EXTI Line[9:5] interrupts */ -#define STM32_IRQ_TIM15 (STM32_IRQ_FIRST + 24) /* 24: TIM15 global interrupt (shared with STM32_IRQ_TIM1BRK) */ -#define STM32_IRQ_TIM1BRK (STM32_IRQ_FIRST + 24) /* 24: TIM1 Break, Transition error, Index error (shared with STM32_IRQ_TIM15) */ -#define STM32_IRQ_TIM16 (STM32_IRQ_FIRST + 25) /* 25: TIM16 global interrupt (shared with STM32_IRQ_TIM1UP) */ -#define STM32_IRQ_TIM1UP (STM32_IRQ_FIRST + 25) /* 25: TIM1 Update interrupt (shared with STM32_IRQ_TIM16) */ -#define STM32_IRQ_TIM17 (STM32_IRQ_FIRST + 26) /* 26: TIM17 global interrupt (shared with STM32_IRQ_TIM1TRGCOM) */ -#define STM32_IRQ_TIM1TRGCOM (STM32_IRQ_FIRST + 26) /* 26: TIM1 Trigger, Commutation, Direction Change, and Index interrupt (shared with STM32_IRQ_TIM17) */ -#define STM32_IRQ_TIM1CC (STM32_IRQ_FIRST + 27) /* 27: TIM1 Capture Compare interrupt */ -#define STM32_IRQ_TIM2 (STM32_IRQ_FIRST + 28) /* 28: TIM2 global interrupt */ -#define STM32_IRQ_TIM3 (STM32_IRQ_FIRST + 29) /* 29: TIM3 global interrupt */ - -#define STM32_IRQ_TIM4 (STM32_IRQ_FIRST + 30) /* 30: TIM4 global interrupt */ -#define STM32_IRQ_I2C1EV (STM32_IRQ_FIRST + 31) /* 31: I2C1 event interrupt */ -#define STM32_IRQ_I2C1ER (STM32_IRQ_FIRST + 32) /* 32: I2C1 error interrupt */ -#define STM32_IRQ_I2C2EV (STM32_IRQ_FIRST + 33) /* 33: I2C2 event interrupt */ -#define STM32_IRQ_I2C2ER (STM32_IRQ_FIRST + 34) /* 34: I2C2 error interrupt */ -#define STM32_IRQ_SPI1 (STM32_IRQ_FIRST + 35) /* 35: SPI1 global interrupt */ -#define STM32_IRQ_SPI2 (STM32_IRQ_FIRST + 36) /* 36: SPI2 global interrupt */ -#define STM32_IRQ_USART1 (STM32_IRQ_FIRST + 37) /* 37: USART1 global interrupt */ -#define STM32_IRQ_USART2 (STM32_IRQ_FIRST + 38) /* 38: USART2 global interrupt */ -#define STM32_IRQ_USART3 (STM32_IRQ_FIRST + 39) /* 39: USART3 global interrupt */ - -#define STM32_IRQ_EXTI1510 (STM32_IRQ_FIRST + 40) /* 40: EXTI Line[15:10] interrupts */ -#define STM32_IRQ_RTCALRM (STM32_IRQ_FIRST + 41) /* 41: RTC alarm through EXTI line interrupt */ -#define STM32_IRQ_USBWKUP (STM32_IRQ_FIRST + 42) /* 42: 42: USB wakeup from suspend through EXTI line interrupt */ -#define STM32_IRQ_TIM8BRK (STM32_IRQ_FIRST + 43) /* 43: TIM8 Break, Transition error, Index error */ -#define STM32_IRQ_TIM8UP (STM32_IRQ_FIRST + 44) /* 44: TIM8 Update interrupt */ -#define STM32_IRQ_TIM8TRGCOM (STM32_IRQ_FIRST + 45) /* 45: TIM8 Trigger, Commutation, Direction Change, and Index interrupt */ -#define STM32_IRQ_TIM8CC (STM32_IRQ_FIRST + 46) /* 46: TIM8 Capture Compare interrupt */ -#define STM32_IRQ_ADC3 (STM32_IRQ_FIRST + 47) /* 47: ADC3 global interrupt */ -#define STM32_IRQ_FMC (STM32_IRQ_FIRST + 48) /* 48: FMC global interrupt */ -#define STM32_IRQ_LPTIM1 (STM32_IRQ_FIRST + 49) /* 49: LPTIM1 interrupt */ - -#define STM32_IRQ_TIM5 (STM32_IRQ_FIRST + 50) /* 50: TIM5 global interrupt */ -#define STM32_IRQ_SPI3 (STM32_IRQ_FIRST + 51) /* 51: SPI3 global interrupt */ -#define STM32_IRQ_UART4 (STM32_IRQ_FIRST + 52) /* 52: UART4 global interrupt */ -#define STM32_IRQ_UART5 (STM32_IRQ_FIRST + 53) /* 53: UART5 global interrupt */ -#define STM32_IRQ_TIM6 (STM32_IRQ_FIRST + 54) /* 54: TIM6 global interrupt (shared with STM32_IRQ_DAC1, STM32_IRQ_DAC3) */ -#define STM32_IRQ_DAC1 (STM32_IRQ_FIRST + 54) /* 54: DAC1 underrun error interrupt (shared with STM32_IRQ_TIM6, STM32_IRQ_DAC3) */ -#define STM32_IRQ_DAC3 (STM32_IRQ_FIRST + 54) /* 54: DAC3 underrun error interrupt (shared with STM32_IRQ_TIM6, STM32_IRQ_DAC1) */ -#define STM32_IRQ_TIM7 (STM32_IRQ_FIRST + 55) /* 55: TIM7 global interrupt (shared with STM32_IRQ_DAC2, STM32_IRQ_DAC4) */ -#define STM32_IRQ_DAC2 (STM32_IRQ_FIRST + 55) /* 55: DAC2 underrun error interrupt (shared with STM32_IRQ_TIM7) */ -#define STM32_IRQ_DAC4 (STM32_IRQ_FIRST + 55) /* 55: DAC4 underrun error interrupt (shared with STM32_IRQ_TIM7) */ -#define STM32_IRQ_DMA2CH1 (STM32_IRQ_FIRST + 56) /* 56: DMA2 channel 1 global interrupt */ -#define STM32_IRQ_DMA2CH2 (STM32_IRQ_FIRST + 57) /* 57: DMA2 channel 2 global interrupt */ -#define STM32_IRQ_DMA2CH3 (STM32_IRQ_FIRST + 58) /* 58: DMA2 channel 3 global interrupt */ -#define STM32_IRQ_DMA2CH4 (STM32_IRQ_FIRST + 59) /* 59: DMA2 channel 4 global interrupt */ - -#define STM32_IRQ_DMA2CH5 (STM32_IRQ_FIRST + 60) /* 60: DMA2 channel 5 global interrupt */ -#define STM32_IRQ_ADC4 (STM32_IRQ_FIRST + 61) /* 61: ADC4 global interrupt */ -#define STM32_IRQ_ADC5 (STM32_IRQ_FIRST + 62) /* 62: ADC5 global interrupt */ -#define STM32_IRQ_UCPD (STM32_IRQ_FIRST + 63) /* 63: UCPD global interrupt */ -#define STM32_IRQ_COMP123 (STM32_IRQ_FIRST + 64) /* 64: COMP1, COMP2, and COMP3 interrupts */ -#define STM32_IRQ_COMP456 (STM32_IRQ_FIRST + 65) /* 65: COMP4, COMP5, and COMP6 interrupts */ -#define STM32_IRQ_COMP7 (STM32_IRQ_FIRST + 66) /* 66: COMPP7 interrupt */ -#define STM32_IRQ_HRTIM1MST (STM32_IRQ_FIRST + 67) /* 67: HRTIM1 master timer interrupt */ -#define STM32_IRQ_HRTIM1TIMA (STM32_IRQ_FIRST + 68) /* 68: HRTIM1 timer A interrupt */ -#define STM32_IRQ_HRTIM1TIMB (STM32_IRQ_FIRST + 69) /* 69: HRTIM1 timer B interrupt */ - -#define STM32_IRQ_HRTIM1TIMC (STM32_IRQ_FIRST + 70) /* 70: HRTIM1 timer C interrupt */ -#define STM32_IRQ_HRTIM1TIMD (STM32_IRQ_FIRST + 71) /* 71: HRTIM1 timer D interrupt */ -#define STM32_IRQ_HRTIM1TIME (STM32_IRQ_FIRST + 72) /* 72: HRTIM1 timer E interrupt */ -#define STM32_IRQ_HRTIM1FLT (STM32_IRQ_FIRST + 73) /* 73: HRTIM1 fault interrupt */ -#define STM32_IRQ_HRTIM1TIMF (STM32_IRQ_FIRST + 74) /* 74: HRTIM1 timer E interrupt */ -#define STM32_IRQ_CRS (STM32_IRQ_FIRST + 75) /* 75: CRS (Clock Recovery System) global interrupt */ -#define STM32_IRQ_SAI1 (STM32_IRQ_FIRST + 76) /* 76: SAI4 global interrupt */ -#define STM32_IRQ_TIM20BRK (STM32_IRQ_FIRST + 77) /* 77: TIM20 Break, Transition error, Index error interrupt */ -#define STM32_IRQ_TIM20UP (STM32_IRQ_FIRST + 78) /* 78: TIM20 Update interrupt */ -#define STM32_IRQ_TIM20TRGCOM (STM32_IRQ_FIRST + 79) /* 79: TIM20 Trigger, Commutation, Direction Change, and Index interrupt */ - -#define STM32_IRQ_TIM20CC (STM32_IRQ_FIRST + 80) /* 80: TIM20 Capture Compare interrupt */ -#define STM32_IRQ_FPU (STM32_IRQ_FIRST + 81) /* 81: FPU global interrupt */ -#define STM32_IRQ_I2C4EV (STM32_IRQ_FIRST + 82) /* 82: I2C4 event interrupt */ -#define STM32_IRQ_I2C4ER (STM32_IRQ_FIRST + 83) /* 83: I2C4 error interrupt */ -#define STM32_IRQ_SPI4 (STM32_IRQ_FIRST + 84) /* 84: SPI4 global interrupt */ -#define STM32_IRQ_AES (STM32_IRQ_FIRST + 85) /* 85: AES global interrupt */ -#define STM32_IRQ_FDCAN2_0 (STM32_IRQ_FIRST + 86) /* 86: FDCAN2 interrupt 0 */ -#define STM32_IRQ_FDCAN2_1 (STM32_IRQ_FIRST + 87) /* 87: FDCAN2 interrupt 1 */ -#define STM32_IRQ_FDCAN3_0 (STM32_IRQ_FIRST + 88) /* 88: FDCAN3 interrupt 0 */ -#define STM32_IRQ_FDCAN3_1 (STM32_IRQ_FIRST + 89) /* 89: FDCAN3 interrupt 1 */ - -#define STM32_IRQ_RNG (STM32_IRQ_FIRST + 90) /* 90: RNG global interrupt */ -#define STM32_IRQ_LPUART (STM32_IRQ_FIRST + 91) /* 91: LPUART global interrupt */ -#define STM32_IRQ_I2C3EV (STM32_IRQ_FIRST + 92) /* 92: I2C3 event interrupt */ -#define STM32_IRQ_I2C3ER (STM32_IRQ_FIRST + 93) /* 93: I2C3 error interrupt */ -#define STM32_IRQ_DMAMUXOV (STM32_IRQ_FIRST + 94) /* 94: DMAMUX overrun interrupt */ -#define STM32_IRQ_QUADSPI (STM32_IRQ_FIRST + 95) /* 95: QuadSPI global interrupt */ -#define STM32_IRQ_DMA1CH8 (STM32_IRQ_FIRST + 96) /* 96: DMA1 channel 8 global interrupt */ -#define STM32_IRQ_DMA2CH6 (STM32_IRQ_FIRST + 97) /* 97: DMA2 channel 6 global interrupt */ -#define STM32_IRQ_DMA2CH7 (STM32_IRQ_FIRST + 98) /* 98: DMA2 channel 7 global interrupt */ -#define STM32_IRQ_DMA2CH8 (STM32_IRQ_FIRST + 99) /* 99: DMA2 channel 8 global interrupt */ - -#define STM32_IRQ_CORDIC (STM32_IRQ_FIRST + 100) /* 100: CORDIC trigonometric accelerator interrupt */ -#define STM32_IRQ_FMAC (STM32_IRQ_FIRST + 101) /* 101: FMAC filter math accelerator interrupt */ - -#define STM32_IRQ_NEXTINTS (102) -#define NR_IRQS (STM32_IRQ_FIRST + 102) - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -#ifndef __ASSEMBLY__ -#ifdef __cplusplus -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -#undef EXTERN -#ifdef __cplusplus -} -#endif -#endif - -#endif /* __ARCH_ARM_INCLUDE_STM32_STM32G4XXXX_IRQ_H */ diff --git a/arch/arm/include/stm32/stm32l15xxx_irq.h b/arch/arm/include/stm32/stm32l15xxx_irq.h deleted file mode 100644 index 432d4b013c83d..0000000000000 --- a/arch/arm/include/stm32/stm32l15xxx_irq.h +++ /dev/null @@ -1,260 +0,0 @@ -/**************************************************************************** - * arch/arm/include/stm32/stm32l15xxx_irq.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* This file should never be included directly but, rather, only indirectly - * through nuttx/irq.h - */ - -#ifndef __ARCH_ARM_INCLUDE_STM32_STM32FL15XXX_IRQ_H -#define __ARCH_ARM_INCLUDE_STM32_STM32FL15XXX_IRQ_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include - -/**************************************************************************** - * Pre-processor Prototypes - ****************************************************************************/ - -/* IRQ numbers. The IRQ number corresponds vector number and hence map - * directly to bits in the NVIC. This does, however, waste several words of - * memory in the IRQ to handle mapping tables. - * - * Processor Exceptions (vectors 0-15). These common definitions can be - * found in nuttx/arch/arm/include/stm32/irq.h - * - * External interrupts (vectors >= 16) for low and medium density devices - */ - -#if defined(CONFIG_STM32_LOWDENSITY) || defined(CONFIG_STM32_MEDIUMDENSITY) -# define STM32_IRQ_WWDG (STM32_IRQ_FIRST + 0) /* 0: Window Watchdog interrupt */ -# define STM32_IRQ_PVD (STM32_IRQ_FIRST + 1) /* 1: PVD through EXTI Line detection interrupt */ -# define STM32_IRQ_TAMPER (STM32_IRQ_FIRST + 2) /* 2: Tamper through EXTI line interrupt, or */ -# define STM32_IRQ_TIMESTAMP (STM32_IRQ_FIRST + 2) /* 2: Time stamp through EXTI line interrupt */ -# define STM32_IRQ_RTC_WKUP (STM32_IRQ_FIRST + 3) /* 3: RTC Wakeup through EXTI line interrupt */ -# define STM32_IRQ_FLASH (STM32_IRQ_FIRST + 4) /* 4: Flash global interrupt */ -# define STM32_IRQ_RCC (STM32_IRQ_FIRST + 5) /* 5: RCC global interrupt */ -# define STM32_IRQ_EXTI0 (STM32_IRQ_FIRST + 6) /* 6: EXTI Line 0 interrupt */ -# define STM32_IRQ_EXTI1 (STM32_IRQ_FIRST + 7) /* 7: EXTI Line 1 interrupt */ -# define STM32_IRQ_EXTI2 (STM32_IRQ_FIRST + 8) /* 8: EXTI Line 2 interrupt */ -# define STM32_IRQ_EXTI3 (STM32_IRQ_FIRST + 9) /* 9: EXTI Line 3 interrupt */ -# define STM32_IRQ_EXTI4 (STM32_IRQ_FIRST + 10) /* 10: EXTI Line 4 interrupt */ -# define STM32_IRQ_DMA1CH1 (STM32_IRQ_FIRST + 11) /* 11: DMA1 channel 1 global interrupt */ -# define STM32_IRQ_DMA1CH2 (STM32_IRQ_FIRST + 12) /* 12: DMA1 channel 2 global interrupt */ -# define STM32_IRQ_DMA1CH3 (STM32_IRQ_FIRST + 13) /* 13: DMA1 channel 3 global interrupt */ -# define STM32_IRQ_DMA1CH4 (STM32_IRQ_FIRST + 14) /* 14: DMA1 channel 4 global interrupt */ -# define STM32_IRQ_DMA1CH5 (STM32_IRQ_FIRST + 15) /* 15: DMA1 channel 5 global interrupt */ -# define STM32_IRQ_DMA1CH6 (STM32_IRQ_FIRST + 16) /* 16: DMA1 channel 6 global interrupt */ -# define STM32_IRQ_DMA1CH7 (STM32_IRQ_FIRST + 17) /* 17: DMA1 channel 7 global interrupt */ -# define STM32_IRQ_ADC1 (STM32_IRQ_FIRST + 18) /* 18: ADC1 global interrupt */ -# define STM32_IRQ_USBHP (STM32_IRQ_FIRST + 19) /* 19: USB High Priority interrupts */ -# define STM32_IRQ_USBLP (STM32_IRQ_FIRST + 20) /* 20: USB Low Priority interrupt */ -# define STM32_IRQ_DAC (STM32_IRQ_FIRST + 21) /* 21: DAC interrupt */ -# define STM32_IRQ_COMP (STM32_IRQ_FIRST + 22) /* 22: Comparator wakeup through EXTI interrupt */ -# define STM32_IRQ_EXTI95 (STM32_IRQ_FIRST + 23) /* 23: EXTI Line[9:5] interrupts */ -# define STM32_IRQ_LDC (STM32_IRQ_FIRST + 24) /* 24: LCD global interrupt */ -# define STM32_IRQ_TIM9 (STM32_IRQ_FIRST + 25) /* 25: TIM9 global interrupt */ -# define STM32_IRQ_TIM10 (STM32_IRQ_FIRST + 26) /* 26: TIM10 global interrupt */ -# define STM32_IRQ_TIM11 (STM32_IRQ_FIRST + 27) /* 27: TIM11 global interrupt */ -# define STM32_IRQ_TIM2 (STM32_IRQ_FIRST + 28) /* 28: TIM2 global interrupt */ -# define STM32_IRQ_TIM3 (STM32_IRQ_FIRST + 29) /* 29: TIM3 global interrupt */ -# define STM32_IRQ_TIM4 (STM32_IRQ_FIRST + 30) /* 30: TIM4 global interrupt */ -# define STM32_IRQ_I2C1EV (STM32_IRQ_FIRST + 31) /* 31: I2C1 event interrupt */ -# define STM32_IRQ_I2C1ER (STM32_IRQ_FIRST + 32) /* 32: I2C1 error interrupt */ -# define STM32_IRQ_I2C2EV (STM32_IRQ_FIRST + 33) /* 33: I2C2 event interrupt */ -# define STM32_IRQ_I2C2ER (STM32_IRQ_FIRST + 34) /* 34: I2C2 error interrupt */ -# define STM32_IRQ_SPI1 (STM32_IRQ_FIRST + 35) /* 35: SPI1 global interrupt */ -# define STM32_IRQ_SPI2 (STM32_IRQ_FIRST + 36) /* 36: SPI2 global interrupt */ -# define STM32_IRQ_USART1 (STM32_IRQ_FIRST + 37) /* 37: USART1 global interrupt */ -# define STM32_IRQ_USART2 (STM32_IRQ_FIRST + 38) /* 38: USART2 global interrupt */ -# define STM32_IRQ_USART3 (STM32_IRQ_FIRST + 39) /* 39: USART3 global interrupt */ -# define STM32_IRQ_EXTI1510 (STM32_IRQ_FIRST + 40) /* 40: EXTI Line[15:10] interrupts */ -# define STM32_IRQ_RTCALRM (STM32_IRQ_FIRST + 41) /* 41: RTC alarm through EXTI line interrupt */ -# define STM32_IRQ_USBWKUP (STM32_IRQ_FIRST + 42) /* 42: USB wakeup from suspend through EXTI line interrupt */ -# define STM32_IRQ_TIM6 (STM32_IRQ_FIRST + 43) /* 43: TIM6 global interrupt */ -# define STM32_IRQ_TIM7 (STM32_IRQ_FIRST + 44) /* 44: TIM7 global interrupt */ - -# define STM32_IRQ_NEXTINTS (45) - -/* External interrupts (vectors >= 16) medium+ density devices */ - -#elif defined(CONFIG_STM32_MEDIUMPLUSDENSITY) -# define STM32_IRQ_WWDG (STM32_IRQ_FIRST + 0) /* 0: Window Watchdog interrupt */ -# define STM32_IRQ_PVD (STM32_IRQ_FIRST + 1) /* 1: PVD through EXTI Line detection interrupt */ -# define STM32_IRQ_TAMPER (STM32_IRQ_FIRST + 2) /* 2: Tamper through EXTI line interrupt, or */ -# define STM32_IRQ_TIMESTAMP (STM32_IRQ_FIRST + 2) /* 2: Time stamp through EXTI line interrupt */ -# define STM32_IRQ_RTC_WKUP (STM32_IRQ_FIRST + 3) /* 3: RTC Wakeup through EXTI line interrupt */ -# define STM32_IRQ_FLASH (STM32_IRQ_FIRST + 4) /* 4: Flash global interrupt */ -# define STM32_IRQ_RCC (STM32_IRQ_FIRST + 5) /* 5: RCC global interrupt */ -# define STM32_IRQ_EXTI0 (STM32_IRQ_FIRST + 6) /* 6: EXTI Line 0 interrupt */ -# define STM32_IRQ_EXTI1 (STM32_IRQ_FIRST + 7) /* 7: EXTI Line 1 interrupt */ -# define STM32_IRQ_EXTI2 (STM32_IRQ_FIRST + 8) /* 8: EXTI Line 2 interrupt */ -# define STM32_IRQ_EXTI3 (STM32_IRQ_FIRST + 9) /* 9: EXTI Line 3 interrupt */ -# define STM32_IRQ_EXTI4 (STM32_IRQ_FIRST + 10) /* 10: EXTI Line 4 interrupt */ -# define STM32_IRQ_DMA1CH1 (STM32_IRQ_FIRST + 11) /* 11: DMA1 channel 1 global interrupt */ -# define STM32_IRQ_DMA1CH2 (STM32_IRQ_FIRST + 12) /* 12: DMA1 channel 2 global interrupt */ -# define STM32_IRQ_DMA1CH3 (STM32_IRQ_FIRST + 13) /* 13: DMA1 channel 3 global interrupt */ -# define STM32_IRQ_DMA1CH4 (STM32_IRQ_FIRST + 14) /* 14: DMA1 channel 4 global interrupt */ -# define STM32_IRQ_DMA1CH5 (STM32_IRQ_FIRST + 15) /* 15: DMA1 channel 5 global interrupt */ -# define STM32_IRQ_DMA1CH6 (STM32_IRQ_FIRST + 16) /* 16: DMA1 channel 6 global interrupt */ -# define STM32_IRQ_DMA1CH7 (STM32_IRQ_FIRST + 17) /* 17: DMA1 channel 7 global interrupt */ -# define STM32_IRQ_ADC1 (STM32_IRQ_FIRST + 18) /* 18: ADC1 global interrupt */ -# define STM32_IRQ_USBHP (STM32_IRQ_FIRST + 19) /* 19: USB High Priority interrupts */ -# define STM32_IRQ_USBLP (STM32_IRQ_FIRST + 20) /* 20: USB Low Priority interrupt */ -# define STM32_IRQ_DAC (STM32_IRQ_FIRST + 21) /* 21: DAC interrupt */ -# define STM32_IRQ_COMP (STM32_IRQ_FIRST + 22) /* 22: Comparator wakeup through EXTI interrupt, or */ -# define STM32_IRQ_CA (STM32_IRQ_FIRST + 22) /* 22: Channel acquisition interrupt */ -# define STM32_IRQ_EXTI95 (STM32_IRQ_FIRST + 23) /* 23: EXTI Line[9:5] interrupts */ -# define STM32_IRQ_LDC (STM32_IRQ_FIRST + 24) /* 24: LCD global interrupt */ -# define STM32_IRQ_TIM9 (STM32_IRQ_FIRST + 25) /* 25: TIM9 global interrupt */ -# define STM32_IRQ_TIM10 (STM32_IRQ_FIRST + 26) /* 26: TIM10 global interrupt */ -# define STM32_IRQ_TIM11 (STM32_IRQ_FIRST + 27) /* 27: TIM11 global interrupt */ -# define STM32_IRQ_TIM2 (STM32_IRQ_FIRST + 28) /* 28: TIM2 global interrupt */ -# define STM32_IRQ_TIM3 (STM32_IRQ_FIRST + 29) /* 29: TIM3 global interrupt */ -# define STM32_IRQ_TIM4 (STM32_IRQ_FIRST + 30) /* 30: TIM4 global interrupt */ -# define STM32_IRQ_I2C1EV (STM32_IRQ_FIRST + 31) /* 31: I2C1 event interrupt */ -# define STM32_IRQ_I2C1ER (STM32_IRQ_FIRST + 32) /* 32: I2C1 error interrupt */ -# define STM32_IRQ_I2C2EV (STM32_IRQ_FIRST + 33) /* 33: I2C2 event interrupt */ -# define STM32_IRQ_I2C2ER (STM32_IRQ_FIRST + 34) /* 34: I2C2 error interrupt */ -# define STM32_IRQ_SPI1 (STM32_IRQ_FIRST + 35) /* 35: SPI1 global interrupt */ -# define STM32_IRQ_SPI2 (STM32_IRQ_FIRST + 36) /* 36: SPI2 global interrupt */ -# define STM32_IRQ_USART1 (STM32_IRQ_FIRST + 37) /* 37: USART1 global interrupt */ -# define STM32_IRQ_USART2 (STM32_IRQ_FIRST + 38) /* 38: USART2 global interrupt */ -# define STM32_IRQ_USART3 (STM32_IRQ_FIRST + 39) /* 39: USART3 global interrupt */ -# define STM32_IRQ_EXTI1510 (STM32_IRQ_FIRST + 40) /* 40: EXTI Line[15:10] interrupts */ -# define STM32_IRQ_RTCALRM (STM32_IRQ_FIRST + 41) /* 41: RTC alarm through EXTI line interrupt */ -# define STM32_IRQ_USBWKUP (STM32_IRQ_FIRST + 42) /* 42: USB wakeup from suspend through EXTI line interrupt */ -# define STM32_IRQ_TIM6 (STM32_IRQ_FIRST + 43) /* 43: TIM6 global interrupt */ -# define STM32_IRQ_TIM7 (STM32_IRQ_FIRST + 44) /* 44: TIM7 global interrupt */ -# define STM32_IRQ_TIM5 (STM32_IRQ_FIRST + 45) /* 45: TIM5 global interrupt */ -# define STM32_IRQ_SPI3 (STM32_IRQ_FIRST + 46) /* 46: SPI3 global interrupt */ -# define STM32_IRQ_DMA2CH1 (STM32_IRQ_FIRST + 47) /* 47: DMA2 channel 1 global interrupt */ -# define STM32_IRQ_DMA2CH2 (STM32_IRQ_FIRST + 48) /* 48: DMA2 channel 2 global interrupt */ -# define STM32_IRQ_DMA2CH3 (STM32_IRQ_FIRST + 49) /* 49: DMA2 channel 3 global interrupt */ -# define STM32_IRQ_DMA2CH4 (STM32_IRQ_FIRST + 50) /* 50: DMA2 channel 4 global interrupt */ -# define STM32_IRQ_DMA2CH5 (STM32_IRQ_FIRST + 51) /* 51: DMA2 channel 5 global interrupt */ -# define STM32_IRQ_AES (STM32_IRQ_FIRST + 52) /* 52: AES global interrupt */ -# define STM32_IRQ_COMPACQ (STM32_IRQ_FIRST + 53) /* 53: Comparator Channel Acquisition Interrupt */ - -# define STM32_IRQ_NEXTINTS (54) - -/* External interrupts (vectors >= 16) high density devices */ - -#elif defined(CONFIG_STM32_HIGHDENSITY) -# define STM32_IRQ_WWDG (STM32_IRQ_FIRST + 0) /* 0: Window Watchdog interrupt */ -# define STM32_IRQ_PVD (STM32_IRQ_FIRST + 1) /* 1: PVD through EXTI Line detection interrupt */ -# define STM32_IRQ_TAMPER (STM32_IRQ_FIRST + 2) /* 2: Tamper through EXTI line interrupt, or */ -# define STM32_IRQ_TIMESTAMP (STM32_IRQ_FIRST + 2) /* 2: Time stamp through EXTI line interrupt */ -# define STM32_IRQ_RTC_WKUP (STM32_IRQ_FIRST + 3) /* 3: RTC Wakeup through EXTI line interrupt */ -# define STM32_IRQ_FLASH (STM32_IRQ_FIRST + 4) /* 4: Flash global interrupt */ -# define STM32_IRQ_RCC (STM32_IRQ_FIRST + 5) /* 5: RCC global interrupt */ -# define STM32_IRQ_EXTI0 (STM32_IRQ_FIRST + 6) /* 6: EXTI Line 0 interrupt */ -# define STM32_IRQ_EXTI1 (STM32_IRQ_FIRST + 7) /* 7: EXTI Line 1 interrupt */ -# define STM32_IRQ_EXTI2 (STM32_IRQ_FIRST + 8) /* 8: EXTI Line 2 interrupt */ -# define STM32_IRQ_EXTI3 (STM32_IRQ_FIRST + 9) /* 9: EXTI Line 3 interrupt */ -# define STM32_IRQ_EXTI4 (STM32_IRQ_FIRST + 10) /* 10: EXTI Line 4 interrupt */ -# define STM32_IRQ_DMA1CH1 (STM32_IRQ_FIRST + 11) /* 11: DMA1 channel 1 global interrupt */ -# define STM32_IRQ_DMA1CH2 (STM32_IRQ_FIRST + 12) /* 12: DMA1 channel 2 global interrupt */ -# define STM32_IRQ_DMA1CH3 (STM32_IRQ_FIRST + 13) /* 13: DMA1 channel 3 global interrupt */ -# define STM32_IRQ_DMA1CH4 (STM32_IRQ_FIRST + 14) /* 14: DMA1 channel 4 global interrupt */ -# define STM32_IRQ_DMA1CH5 (STM32_IRQ_FIRST + 15) /* 15: DMA1 channel 5 global interrupt */ -# define STM32_IRQ_DMA1CH6 (STM32_IRQ_FIRST + 16) /* 16: DMA1 channel 6 global interrupt */ -# define STM32_IRQ_DMA1CH7 (STM32_IRQ_FIRST + 17) /* 17: DMA1 channel 7 global interrupt */ -# define STM32_IRQ_ADC1 (STM32_IRQ_FIRST + 18) /* 18: ADC1 global interrupt */ -# define STM32_IRQ_USBHP (STM32_IRQ_FIRST + 19) /* 19: USB High Priority interrupts */ -# define STM32_IRQ_USBLP (STM32_IRQ_FIRST + 20) /* 20: USB Low Priority interrupt */ -# define STM32_IRQ_DAC (STM32_IRQ_FIRST + 21) /* 21: DAC interrupt */ -# define STM32_IRQ_COMP (STM32_IRQ_FIRST + 22) /* 22: Comparator wakeup through EXTI interrupt, or */ -# define STM32_IRQ_CA (STM32_IRQ_FIRST + 22) /* 22: Channel acquisition interrupt */ -# define STM32_IRQ_EXTI95 (STM32_IRQ_FIRST + 23) /* 23: EXTI Line[9:5] interrupts */ -# define STM32_IRQ_LDC (STM32_IRQ_FIRST + 24) /* 24: LCD global interrupt */ -# define STM32_IRQ_TIM9 (STM32_IRQ_FIRST + 25) /* 25: TIM9 global interrupt */ -# define STM32_IRQ_TIM10 (STM32_IRQ_FIRST + 26) /* 26: TIM10 global interrupt */ -# define STM32_IRQ_TIM11 (STM32_IRQ_FIRST + 27) /* 27: TIM11 global interrupt */ -# define STM32_IRQ_TIM2 (STM32_IRQ_FIRST + 28) /* 28: TIM2 global interrupt */ -# define STM32_IRQ_TIM3 (STM32_IRQ_FIRST + 29) /* 29: TIM3 global interrupt */ -# define STM32_IRQ_TIM4 (STM32_IRQ_FIRST + 30) /* 30: TIM4 global interrupt */ -# define STM32_IRQ_I2C1EV (STM32_IRQ_FIRST + 31) /* 31: I2C1 event interrupt */ -# define STM32_IRQ_I2C1ER (STM32_IRQ_FIRST + 32) /* 32: I2C1 error interrupt */ -# define STM32_IRQ_I2C2EV (STM32_IRQ_FIRST + 33) /* 33: I2C2 event interrupt */ -# define STM32_IRQ_I2C2ER (STM32_IRQ_FIRST + 34) /* 34: I2C2 error interrupt */ -# define STM32_IRQ_SPI1 (STM32_IRQ_FIRST + 35) /* 35: SPI1 global interrupt */ -# define STM32_IRQ_SPI2 (STM32_IRQ_FIRST + 36) /* 36: SPI2 global interrupt */ -# define STM32_IRQ_USART1 (STM32_IRQ_FIRST + 37) /* 37: USART1 global interrupt */ -# define STM32_IRQ_USART2 (STM32_IRQ_FIRST + 38) /* 38: USART2 global interrupt */ -# define STM32_IRQ_USART3 (STM32_IRQ_FIRST + 39) /* 39: USART3 global interrupt */ -# define STM32_IRQ_EXTI1510 (STM32_IRQ_FIRST + 40) /* 40: EXTI Line[15:10] interrupts */ -# define STM32_IRQ_RTCALRM (STM32_IRQ_FIRST + 41) /* 41: RTC alarm through EXTI line interrupt */ -# define STM32_IRQ_USBWKUP (STM32_IRQ_FIRST + 42) /* 42: USB wakeup from suspend through EXTI line interrupt */ -# define STM32_IRQ_TIM6 (STM32_IRQ_FIRST + 43) /* 43: TIM6 global interrupt */ -# define STM32_IRQ_TIM7 (STM32_IRQ_FIRST + 44) /* 44: TIM7 global interrupt */ -# define STM32_IRQ_SDIO (STM32_IRQ_FIRST + 45) /* 45: SDIO Global interrupt */ -# define STM32_IRQ_TIM5 (STM32_IRQ_FIRST + 46) /* 46: TIM5 global interrupt */ -# define STM32_IRQ_SPI3 (STM32_IRQ_FIRST + 47) /* 47: SPI3 global interrupt */ -# define STM32_IRQ_UART4 (STM32_IRQ_FIRST + 48) /* 48: UART4 global interrupt */ -# define STM32_IRQ_UART5 (STM32_IRQ_FIRST + 49) /* 49: UART5 global interrupt */ -# define STM32_IRQ_DMA2CH1 (STM32_IRQ_FIRST + 50) /* 50: DMA2 channel 1 global interrupt */ -# define STM32_IRQ_DMA2CH2 (STM32_IRQ_FIRST + 51) /* 51: DMA2 channel 2 global interrupt */ -# define STM32_IRQ_DMA2CH3 (STM32_IRQ_FIRST + 52) /* 52: DMA2 channel 3 global interrupt */ -# define STM32_IRQ_DMA2CH4 (STM32_IRQ_FIRST + 53) /* 53: DMA2 channel 4 global interrupt */ -# define STM32_IRQ_DMA2CH5 (STM32_IRQ_FIRST + 54) /* 54: DMA2 channel 5 global interrupt */ -# define STM32_IRQ_AES (STM32_IRQ_FIRST + 55) /* 55: AES global interrupt */ -# define STM32_IRQ_COMPACQ (STM32_IRQ_FIRST + 56) /* 56: Comparator Channel Acquisition Interrupt */ - -# define STM32_IRQ_NEXTINTS (57) -#else -# error "Unknown STM32L density" -#endif - -# define NR_IRQS (STM32_IRQ_FIRST + STM32_IRQ_NEXTINTS) - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -#ifndef __ASSEMBLY__ -#ifdef __cplusplus -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -#undef EXTERN -#ifdef __cplusplus -} -#endif -#endif - -#endif /* __ARCH_ARM_INCLUDE_STM32_STM32FL15XXX_IRQ_H */ diff --git a/arch/arm/include/stm32c0/chip.h b/arch/arm/include/stm32c0/chip.h new file mode 100644 index 0000000000000..64eb965d03f2d --- /dev/null +++ b/arch/arm/include/stm32c0/chip.h @@ -0,0 +1,157 @@ +/**************************************************************************** + * arch/arm/include/stm32c0/chip.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_INCLUDE_STM32C0_CHIP_H +#define __ARCH_ARM_INCLUDE_STM32C0_CHIP_H + +#define ARMV6M_PERIPHERAL_INTERRUPTS 32 + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Prototypes + ****************************************************************************/ + +/* Get customizations for each supported chip */ + +#if defined(CONFIG_ARCH_CHIP_STM32C051XX) +# define STM32_NATIM 1 /* One advanced timers TIM1 */ +# define STM32_NGTIM16 4 /* Four 16-bit general up/down timers TIM3, TIM14, + * TIM16 and TIM17 */ +# define STM32_NGTIM32 1 /* One 32-bit general up/down timer TIM2 */ +# define STM32_NBTIM 0 /* No basic timers */ + /* One LPTIMER */ +# define STM32_NSPI 2 /* Two SPI modules SPI1-2 */ +# define STM32_NI2S 0 /* No I2S module */ +# define STM32_NI2C 2 /* Two I2C */ +# define STM32_NDMA 1 /* One DMA1, 5-channels */ +# define STM32_NUSART 2 /* Two USART modules, USART1-2 */ +# define STM32_NCAN 0 /* No CAN controllers */ +# define STM32_FDCAN 0 /* No FD CAN */ +# define STM32_NLCD 0 /* No LCD controller */ +# define STM32_NUSBDEV 0 /* No USB full-speed device controller */ +# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (only USB 2.0 device) */ +# define STM32_NCEC 0 /* No HDMI-CEC controller */ +# define STM32_NADC 1 /* One 12-bit module */ +# define STM32_NDAC 0 /* No DAC channels */ +# define STM32_NCOMP 0 /* No Analog Comparators */ +# define STM32_NCRC 1 /* One CRC module */ +# define STM32_NRNG 0 /* No Random number generator (RNG) */ +# define STM32_NCAP 0 /* No Capacitive sensing channels */ +# define STM32_NPORTS 5 /* Five GPIO ports, GPIOA-D, F */ +#elif defined(CONFIG_ARCH_CHIP_STM32C071XX) +# define STM32_NATIM 1 /* One advanced timers TIM1 */ +# define STM32_NGTIM16 4 /* 16-bit general up/down timers TIM3, TIM14, + * TIM16 and TIM17 */ +# define STM32_NGTIM32 1 /* One 32-bit general up/down timer TIM2 */ +# define STM32_NBTIM 0 /* No basic timers */ + /* One LPTIMER */ +# define STM32_NSPI 2 /* Two SPI modules SPI1-2 */ +# define STM32_NI2S 0 /* No I2S module */ +# define STM32_NI2C 2 /* Two I2C */ +# define STM32_NDMA 1 /* One DMA1, 5-channels */ +# define STM32_NUSART 2 /* Two USART modules, USART1-2 */ +# define STM32_NCAN 0 /* No CAN controllers */ +# define STM32_FDCAN 0 /* No FD CAN */ +# define STM32_NLCD 0 /* No LCD controller */ +# define STM32_NUSBDEV 1 /* USB full-speed device controller */ +# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (only USB 2.0 device) */ +# define STM32_NCEC 0 /* No HDMI-CEC controller */ +# define STM32_NADC 1 /* One 12-bit module */ +# define STM32_NDAC 0 /* No DAC channels */ +# define STM32_NCOMP 0 /* No Analog Comparators */ +# define STM32_NCRC 1 /* One CRC module */ +# define STM32_NRNG 0 /* No Random number generator (RNG) */ +# define STM32_NCAP 0 /* No Capacitive sensing channels */ +# define STM32_NPORTS 5 /* Five GPIO ports, GPIOA-D, F */ +#elif defined(CONFIG_ARCH_CHIP_STM32C091XX) +# define STM32_NATIM 1 /* One advanced timers TIM1 */ +# define STM32_NGTIM16 5 /* 16-bit general up/down timers TIM3, TIM14, + * TIM15, TIM16 and TIM17 */ +# define STM32_NGTIM32 1 /* One 32-bit general up/down timer TIM2 */ +# define STM32_NBTIM 0 /* No basic timers */ + /* One LPTIMER */ +# define STM32_NSPI 2 /* Two SPI modules SPI1-2 */ +# define STM32_NI2S 0 /* No I2S module */ +# define STM32_NI2C 2 /* Two I2C */ +# define STM32_NDMA 1 /* One DMA1, 5-channels */ +# define STM32_NUSART 4 /* Four USART modules, USART1-4 */ +# define STM32_NCAN 0 /* No CAN controllers */ +# define STM32_FDCAN 0 /* No FD CAN */ +# define STM32_NLCD 0 /* No LCD controller */ +# define STM32_NUSBDEV 1 /* USB full-speed device controller */ +# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (only USB 2.0 device) */ +# define STM32_NCEC 0 /* No HDMI-CEC controller */ +# define STM32_NADC 1 /* One 12-bit module */ +# define STM32_NDAC 0 /* No DAC channels */ +# define STM32_NCOMP 0 /* No Analog Comparators */ +# define STM32_NCRC 1 /* One CRC module */ +# define STM32_NRNG 0 /* No Random number generator (RNG) */ +# define STM32_NCAP 0 /* No Capacitive sensing channels */ +# define STM32_NPORTS 5 /* Five GPIO ports, GPIOA-D, F */ +#elif defined(CONFIG_ARCH_CHIP_STM32C092XX) +# define STM32_NATIM 1 /* One advanced timers TIM1 */ +# define STM32_NGTIM16 5 /* 16-bit general up/down timers TIM3, TIM14, + * TIM15, TIM16 and TIM17 */ +# define STM32_NGTIM32 1 /* One 32-bit general up/down timer TIM2 */ +# define STM32_NBTIM 0 /* No basic timers */ + /* One LPTIMER */ +# define STM32_NSPI 2 /* Two SPI modules SPI1-2 */ +# define STM32_NI2S 0 /* No I2S module */ +# define STM32_NI2C 2 /* Two I2C */ +# define STM32_NDMA 1 /* One DMA1, 5-channels */ +# define STM32_NUSART 4 /* Four USART modules, USART1-4 */ +# define STM32_NCAN 0 /* No CAN controllers */ +# define STM32_FDCAN 1 /* One FD CAN */ +# define STM32_NLCD 0 /* No LCD controller */ +# define STM32_NUSBDEV 1 /* USB full-speed device controller */ +# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (only USB 2.0 device) */ +# define STM32_NCEC 0 /* No HDMI-CEC controller */ +# define STM32_NADC 1 /* One 12-bit module */ +# define STM32_NDAC 0 /* No DAC channels */ +# define STM32_NCOMP 0 /* No Analog Comparators */ +# define STM32_NCRC 1 /* One CRC module */ +# define STM32_NRNG 0 /* No Random number generator (RNG) */ +# define STM32_NCAP 0 /* No Capacitive sensing channels */ +# define STM32_NPORTS 5 /* Five GPIO ports, GPIOA-D, F */ +#else +# error "Unsupported STM32 Cortex M0 chip" +#endif + +/* NVIC priority levels *****************************************************/ + +/* Each priority field holds a priority value, 0-31. The lower the value, + * the greater the priority of the corresponding interrupt. The processor + * implements only bits[7:6] of each field, bits[5:0] read as zero and + * ignore writes. + */ + +#define NVIC_SYSH_PRIORITY_MIN 0xc0 /* All bits[7:6] set is minimum priority */ +#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */ +#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */ +#define NVIC_SYSH_PRIORITY_STEP 0x40 /* Two bits of interrupt priority used */ + +#endif /* __ARCH_ARM_INCLUDE_STM32C0_CHIP_H */ diff --git a/arch/arm/include/stm32c0/irq.h b/arch/arm/include/stm32c0/irq.h new file mode 100644 index 0000000000000..aba16028025fb --- /dev/null +++ b/arch/arm/include/stm32c0/irq.h @@ -0,0 +1,113 @@ +/**************************************************************************** + * arch/arm/include/stm32c0/irq.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* This file should never be included directly but, rather, only indirectly + * through nuttx/irq.h + */ + +#ifndef __ARCH_ARM_INCLUDE_STM32C0_IRQ_H +#define __ARCH_ARM_INCLUDE_STM32C0_IRQ_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#ifndef __ASSEMBLY__ +# include +#endif +#include + +/**************************************************************************** + * Pre-processor Prototypes + ****************************************************************************/ + +/* IRQ numbers. The IRQ number corresponds vector number and hence map + * directly to bits in the NVIC. This does, however, waste several words of + * memory in the IRQ to handle mapping tables. + */ + +/* Common Processor Exceptions (vectors 0-15) */ + +#define STM32_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */ + /* Vector 0: Reset stack pointer value */ + /* Vector 1: Reset (not handler as an IRQ) */ +#define STM32_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */ +#define STM32_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */ + /* Vectors 4-10: Reserved */ +#define STM32_IRQ_SVCALL (11) /* Vector 11: SVC call */ + /* Vector 12-13: Reserved */ +#define STM32_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */ +#define STM32_IRQ_SYSTICK (15) /* Vector 15: System tick */ + +/* External interrupts (vectors >= 16) */ + +#define STM32_IRQ_EXTINT (16) /* Vector number of the first external interrupt */ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/* External interrupt vectors */ + +#define STM32_IRQ_WWDG (STM32_IRQ_EXTINT + 0) /* 0: Window Watchdog interrupt */ +#define STM32_IRQ_PVM (STM32_IRQ_EXTINT + 1) /* 1: VDDIO2 monitor interrupt */ +#define STM32_IRQ_RTC (STM32_IRQ_EXTINT + 2) /* 2: RTC */ +#define STM32_IRQ_FLASH (STM32_IRQ_EXTINT + 3) /* 3: Flash */ +#define STM32_IRQ_RCC (STM32_IRQ_EXTINT + 4) /* 4: RCC */ +#define STM32_IRQ_EXTI0_1 (STM32_IRQ_EXTINT + 5) /* 5: EXTI0_1 */ +#define STM32_IRQ_EXTI2_3 (STM32_IRQ_EXTINT + 6) /* 6: EXTI2_3 */ +#define STM32_IRQ_EXTI4_15 (STM32_IRQ_EXTINT + 7) /* 7: EXTI4_15 */ +#define STM32_IRQ_USB (STM32_IRQ_EXTINT + 8) /* 8: USB global interrupt */ +#define STM32_IRQ_DMA1CH1 (STM32_IRQ_EXTINT + 9) /* 9: DMA1_CH1 */ +#define STM32_IRQ_DMA1CH2 (STM32_IRQ_EXTINT + 10) /* 10: DMA1_CH2 */ +#define STM32_IRQ_DMA1CH3 (STM32_IRQ_EXTINT + 10) /* 10: DMA1_CH3 */ +#define STM32_IRQ_DMA1CH4 (STM32_IRQ_EXTINT + 11) /* 11: DMA1_CH4 */ +#define STM32_IRQ_DMA1CH5 (STM32_IRQ_EXTINT + 11) /* 11: DMA1_CH5 */ +#define STM32_IRQ_DMA1CH6 (STM32_IRQ_EXTINT + 11) /* 11: DMA1_CH6 */ +#define STM32_IRQ_DMA1CH7 (STM32_IRQ_EXTINT + 11) /* 11: DMA1_CH7 */ +#define STM32_IRQ_DMAMUX (STM32_IRQ_EXTINT + 11) /* 11: DMAMUX */ +#define STM32_IRQ_ADC (STM32_IRQ_EXTINT + 12) /* 12: ADC */ +#define STM32_IRQ_TIM1_BRK (STM32_IRQ_EXTINT + 13) /* 13: TIM1_BRK_UP_TRG_COM */ +#define STM32_IRQ_TIM1_CC (STM32_IRQ_EXTINT + 14) /* 14: TIM1_CC */ +#define STM32_IRQ_TIM2 (STM32_IRQ_EXTINT + 15) /* 15: TIM2 */ +#define STM32_IRQ_TIM3 (STM32_IRQ_EXTINT + 16) /* 16: TIM3 */ +#define STM32_IRQ_TIM6 (STM32_IRQ_EXTINT + 17) /* 17: TIM6 */ +#define STM32_IRQ_TIM14 (STM32_IRQ_EXTINT + 19) /* 19: TIM14 */ +#define STM32_IRQ_TIM15 (STM32_IRQ_EXTINT + 20) /* 20: TIM15 */ +#define STM32_IRQ_TIM16 (STM32_IRQ_EXTINT + 21) /* 21: TIM16 */ +#define STM32_IRQ_TIM17 (STM32_IRQ_EXTINT + 22) /* 22: TIM17 */ +#define STM32_IRQ_I2C1 (STM32_IRQ_EXTINT + 23) /* 23: I2C1 */ +#define STM32_IRQ_I2C2 (STM32_IRQ_EXTINT + 24) /* 24: I2C2 */ +#define STM32_IRQ_SPI1 (STM32_IRQ_EXTINT + 25) /* 25: SPI1 */ +#define STM32_IRQ_SPI2 (STM32_IRQ_EXTINT + 26) /* 26: SPI2 */ +#define STM32_IRQ_USART1 (STM32_IRQ_EXTINT + 27) /* 27: USART1 */ +#define STM32_IRQ_USART2 (STM32_IRQ_EXTINT + 28) /* 28: USART2 */ +#define STM32_IRQ_USART3 (STM32_IRQ_EXTINT + 29) /* 29: USART3 */ +#define STM32_IRQ_USART4 (STM32_IRQ_EXTINT + 29) /* 29: USART4 */ +#define STM32_IRQ_FDCAN1_0 (STM32_IRQ_EXTINT + 30) /* 30: FDCAN global interrupt 0 */ +#define STM32_IRQ_FDCAN1_1 (STM32_IRQ_EXTINT + 31) /* 31: FDCAN global interrupt 1 */ + +#define STM32_IRQ_NEXTINTS (32) + +#define NR_IRQS (STM32_IRQ_EXTINT + STM32_IRQ_NEXTINTS) + +#endif /* __ARCH_ARM_INCLUDE_STM32C0_IRQ_H */ diff --git a/arch/arm/include/stm32f0/chip.h b/arch/arm/include/stm32f0/chip.h new file mode 100644 index 0000000000000..c045084d62e0a --- /dev/null +++ b/arch/arm/include/stm32f0/chip.h @@ -0,0 +1,238 @@ +/**************************************************************************** + * arch/arm/include/stm32f0/chip.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_INCLUDE_STM32F0_CHIP_H +#define __ARCH_ARM_INCLUDE_STM32F0_CHIP_H + +#define ARMV6M_PERIPHERAL_INTERRUPTS 32 + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Prototypes + ****************************************************************************/ + +/* Get customizations for each supported chip */ + +#if defined(CONFIG_ARCH_CHIP_STM32F030RC) || defined(CONFIG_ARCH_CHIP_STM32F030CC) + +# define STM32_FLASH_SIZE (256 * 1024) /* 256Kb */ +# define STM32_SRAM_SIZE (32 * 1024) /* 32Kb */ + +# define STM32_NSPI 2 /* Two SPI modules (SPI or I2S) */ +# define STM32_NI2S 0 /* No I2S modules */ +# define STM32_NI2C 2 /* Two I2C modules */ +# define STM32_NDMA 1 /* 1 DMA1, 7-channels */ +# define STM32_NUSART 6 /* Six USARTs modules */ +# define STM32_NCAN 0 /* No CAN controllers */ +# define STM32_NUSBDEV 0 /* One USB full-speed device controller */ +# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (only USB 2.0 device) */ +# define STM32_NADC 1 /* One 12-bit module */ +# define STM32_NDAC 0 /* One DAC channel */ +# define STM32_NCOMP 0 /* Two Analog Comparators */ +# define STM32_NCAP 0 /* Capacitive sensing channels (14 on UFQFPN32)) */ +# define STM32_NPORTS 5 /* Five GPIO ports, GPIOA-D, F */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F051R8) + +# define STM32_FLASH_SIZE (64 * 1024) /* 64Kb */ +# define STM32_SRAM_SIZE (8 * 1024) /* 8Kb */ + +# define STM32_NSPI 2 /* Two SPI modules (SPI or I2S) */ +# define STM32_NI2S 2 /* Two I2S modules (SPI or I2S) */ +# define STM32_NI2C 2 /* Two I2C modules */ +# define STM32_NDMA 1 /* 1 DMA1, 7-channels */ +# define STM32_NUSART 2 /* Two USARTs modules */ +# define STM32_NCAN 0 /* No CAN controllers */ +# define STM32_NUSBDEV 1 /* One USB full-speed device controller */ +# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (only USB 2.0 device) */ +# define STM32_NADC 1 /* One 12-bit module */ +# define STM32_NDAC 1 /* One DAC channel */ +# define STM32_NCOMP 2 /* Two Analog Comparators */ +# define STM32_NCAP 13 /* Capacitive sensing channels (14 on UFQFPN32)) */ +# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-F */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F072C8) || defined(CONFIG_ARCH_CHIP_STM32F072CB) + +# ifdef CONFIG_ARCH_CHIP_STM32F072C8 +# define STM32_FLASH_SIZE (64 * 1024) /* 64Kb */ +# else +# define STM32_FLASH_SIZE (128 * 1024) /* 128Kb */ +# endif +# define STM32_SRAM_SIZE (16 * 1024) /* 16Kb */ + +# define STM32_NATIM 1 /* One advanced timer TIM1 */ +# define STM32_NGTIM16 5 /* 16-bit general up/down timers TIM3, TIM14-17 */ +# define STM32_NGTIM32 1 /* 32-bit general up/down timers TIM2 */ +# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 */ +# define STM32_NSPI 2 /* Two SPI modules (SPI or I2S) */ +# define STM32_NI2S 2 /* Two I2S modules (SPI or I2S) */ +# define STM32_NI2C 2 /* Two I2C modules */ +# define STM32_NDMA 1 /* 1 DMA1, 7-channels */ +# define STM32_NUSART 4 /* Four USARTs module */ +# define STM32_NCAN 1 /* One CAN controller */ +# define STM32_NUSBDEV 1 /* One USB full-speed device controller */ +# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (only USB 2.0 device) */ +# define STM32_NCEC 1 /* One HDMI-CEC controller */ +# define STM32_NADC 1 /* One 12-bit module */ +# define STM32_NDAC 2 /* Two DAC channel */ +# define STM32_NCOMP 2 /* Two Analog Comparators */ +# define STM32_NCAP 17 /* Capacitive sensing channels */ +# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-F */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F072R8) || defined(CONFIG_ARCH_CHIP_STM32F072RB) + +# ifdef CONFIG_ARCH_CHIP_STM32F072R8 +# define STM32_FLASH_SIZE (64*1024) /* 64Kb */ +# else +# define STM32_FLASH_SIZE (128*1024) /* 128Kb */ +# endif +# define STM32_SRAM_SIZE (16*1024) /* 16Kb */ + +# define STM32_NATIM 1 /* One advanced timer TIM1 */ +# define STM32_NGTIM16 5 /* 16-bit general up/down timers TIM3, TIM14-17 */ +# define STM32_NGTIM32 1 /* 32-bit general up/down timers TIM2 */ +# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 */ +# define STM32_NSPI 2 /* Two SPI modules (SPI or I2S) */ +# define STM32_NI2S 2 /* Two I2S modules (SPI or I2S) */ +# define STM32_NI2C 2 /* Two I2C modules */ +# define STM32_NDMA 1 /* 1 DMA1, 7-channels */ +# define STM32_NUSART 4 /* Four USARTs module */ +# define STM32_NCAN 1 /* One CAN controller */ +# define STM32_NUSBDEV 1 /* One USB full-speed device controller */ +# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (only USB 2.0 device) */ +# define STM32_NCEC 1 /* One HDMI-CEC controller */ +# define STM32_NADC 1 /* One 12-bit module */ +# define STM32_NDAC 2 /* Two DAC channel */ +# define STM32_NCOMP 2 /* Two Analog Comparators */ +# define STM32_NCAP 18 /* Capacitive sensing channels */ +# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-F */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F072V8) || defined(CONFIG_ARCH_CHIP_STM32F072VB) + +# ifdef CONFIG_ARCH_CHIP_STM32F072V8 +# define STM32_FLASH_SIZE (64 * 1024) /* 64Kb */ +# else +# define STM32_FLASH_SIZE (128 * 1024) /* 128Kb */ +# endif +# define STM32_SRAM_SIZE (16 * 1024) /* 16Kb */ + +# define STM32_NATIM 1 /* One advanced timer TIM1 */ +# define STM32_NGTIM16 5 /* 16-bit general up/down timers TIM3, TIM14-17 */ +# define STM32_NGTIM32 1 /* 32-bit general up/down timers TIM2 */ +# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 */ +# define STM32_NSPI 2 /* Two SPI modules (SPI or I2S) */ +# define STM32_NI2S 2 /* Two I2S modules (SPI or I2S) */ +# define STM32_NI2C 2 /* Two I2C modules */ +# define STM32_NDMA 1 /* 1 DMA1, 7-channels */ +# define STM32_NUSART 4 /* Four USARTs module */ +# define STM32_NCAN 1 /* One CAN controller */ +# define STM32_NUSBDEV 1 /* One USB full-speed device controller */ +# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (only USB 2.0 device) */ +# define STM32_NCEC 1 /* One HDMI-CEC controller */ +# define STM32_NADC 1 /* One 12-bit module */ +# define STM32_NDAC 2 /* Two DAC channel */ +# define STM32_NCOMP 2 /* Two Analog Comparators */ +# define STM32_NCAP 24 /* Capacitive sensing channels */ +# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-F */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F091CB) || defined(CONFIG_ARCH_CHIP_STM32F091CC) + +# ifdef CONFIG_ARCH_CHIP_STM32F091CB +# define STM32_FLASH_SIZE (128 * 1024) /* 128Kb */ +# else +# define STM32_FLASH_SIZE (256 * 1024) /* 256Kb */ +# endif +# define STM32_SRAM_SIZE (32 * 1024) /* 32Kb */ + +# define STM32_NATIM 1 /* One advanced timer TIM1 */ +# define STM32_NGTIM16 5 /* 16-bit general up/down timers TIM3, TIM14-17 */ +# define STM32_NGTIM32 1 /* 32-bit general up/down timers TIM2 */ +# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 */ +# define STM32_NSPI 2 /* Two SPI modules (SPI or I2S) */ +# define STM32_NI2S 2 /* Two I2S modules (SPI or I2S) */ +# define STM32_NI2C 2 /* Two I2C modules */ +# define STM32_NDMA 2 /* DMA1, DMA2 */ +# define STM32_NUSART 6 /* Six USARTs modules */ +# define STM32_NCAN 1 /* One CAN controller */ +# define STM32_NUSBDEV 0 /* No USB full-speed device controller */ +# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (only USB 2.0 device) */ +# define STM32_NCEC 1 /* One HDMI-CEC controller */ +# define STM32_NADC 1 /* One 12-bit module */ +# define STM32_NDAC 2 /* Two DAC channel */ +# define STM32_NCOMP 2 /* Two Analog Comparators */ +# define STM32_NCAP 17 /* Capacitive sensing channels */ +# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-F */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F091RB) || defined(CONFIG_ARCH_CHIP_STM32F091RC) || \ + defined(CONFIG_ARCH_CHIP_STM32F091VB) || defined(CONFIG_ARCH_CHIP_STM32F091VC) + +# if defined(CONFIG_ARCH_CHIP_STM32F091RB) || defined(CONFIG_ARCH_CHIP_STM32F091VB) +# define STM32_FLASH_SIZE (128 * 1024) /* 128Kb */ +# else +# define STM32_FLASH_SIZE (256 * 1024) /* 256Kb */ +# endif +# define STM32_SRAM_SIZE (32 * 1024) /* 32Kb */ + +# define STM32_NATIM 1 /* One advanced timer TIM1 */ +# define STM32_NGTIM16 5 /* 16-bit general up/down timers TIM3, TIM14-17 */ +# define STM32_NGTIM32 1 /* 32-bit general up/down timers TIM2 */ +# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 */ +# define STM32_NSPI 2 /* Two SPI modules (SPI or I2S) */ +# define STM32_NI2S 2 /* Two I2S modules (SPI or I2S) */ +# define STM32_NI2C 2 /* Two I2C modules */ +# define STM32_NDMA 2 /* DMA1, DMA2 */ +# define STM32_NUSART 8 /* Eight USARTs modules */ +# define STM32_NCAN 1 /* One CAN controller */ +# define STM32_NUSBDEV 0 /* No USB full-speed device controller */ +# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (only USB 2.0 device) */ +# define STM32_NCEC 1 /* One HDMI-CEC controller */ +# define STM32_NADC 1 /* One 12-bit module */ +# define STM32_NDAC 2 /* Two DAC channel */ +# define STM32_NCOMP 2 /* Two Analog Comparators */ +# if defined(CONFIG_ARCH_CHIP_STM32F091VB) || defined(CONFIG_ARCH_CHIP_STM32F091VC) +# define STM32_NCAP 24 /* Capacitive sensing channels */ +# else +# define STM32_NCAP 18 /* Capacitive sensing channels */ +# endif +# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-F */ + +#endif + +/* NVIC priority levels *****************************************************/ + +/* Each priority field holds a priority value, 0-31. The lower the value, + * the greater the priority of the corresponding interrupt. The processor + * implements only bits[7:6] of each field, bits[5:0] read as zero and + * ignore writes. + */ + +#define NVIC_SYSH_PRIORITY_MIN 0xc0 /* All bits[7:6] set is minimum priority */ +#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */ +#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */ +#define NVIC_SYSH_PRIORITY_STEP 0x40 /* Two bits of interrupt priority used */ + +#endif /* __ARCH_ARM_INCLUDE_STM32F0_CHIP_H */ diff --git a/arch/arm/include/stm32f0/irq.h b/arch/arm/include/stm32f0/irq.h new file mode 100644 index 0000000000000..c142f9068bef7 --- /dev/null +++ b/arch/arm/include/stm32f0/irq.h @@ -0,0 +1,125 @@ +/**************************************************************************** + * arch/arm/include/stm32f0/irq.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* This file should never be included directly but, rather, only indirectly + * through nuttx/irq.h + */ + +#ifndef __ARCH_ARM_INCLUDE_STM32F0_IRQ_H +#define __ARCH_ARM_INCLUDE_STM32F0_IRQ_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#ifndef __ASSEMBLY__ +# include +#endif +#include + +/**************************************************************************** + * Pre-processor Prototypes + ****************************************************************************/ + +/* IRQ numbers. The IRQ number corresponds vector number and hence map + * directly to bits in the NVIC. This does, however, waste several words of + * memory in the IRQ to handle mapping tables. + */ + +/* Common Processor Exceptions (vectors 0-15) */ + +#define STM32_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */ + /* Vector 0: Reset stack pointer value */ + /* Vector 1: Reset (not handler as an IRQ) */ +#define STM32_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */ +#define STM32_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */ + /* Vectors 4-10: Reserved */ +#define STM32_IRQ_SVCALL (11) /* Vector 11: SVC call */ + /* Vector 12-13: Reserved */ +#define STM32_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */ +#define STM32_IRQ_SYSTICK (15) /* Vector 15: System tick */ + +/* External interrupts (vectors >= 16) */ + +#define STM32_IRQ_EXTINT (16) /* Vector number of the first external interrupt */ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/* External interrupt vectors */ + +#define STM32_IRQ_WWDG (STM32_IRQ_EXTINT + 0) /* 0: WWDG */ +#define STM32_IRQ_PVD_VDDIO2 (STM32_IRQ_EXTINT + 1) /* 1: PVD_VDDIO2 */ +#define STM32_IRQ_RTC (STM32_IRQ_EXTINT + 2) /* 2: RTC */ +#define STM32_IRQ_FLASH (STM32_IRQ_EXTINT + 3) /* 3: FLASH */ +#define STM32_IRQ_RCC_CRS (STM32_IRQ_EXTINT + 4) /* 4: RCC and CRS */ +#define STM32_IRQ_EXTI0_1 (STM32_IRQ_EXTINT + 5) /* 5: EXTI0_1 */ +#define STM32_IRQ_EXTI2_3 (STM32_IRQ_EXTINT + 6) /* 6: EXTI2_3 */ +#define STM32_IRQ_EXTI4_15 (STM32_IRQ_EXTINT + 7) /* 7: EXTI4_15 */ +#define STM32_IRQ_TSC (STM32_IRQ_EXTINT + 8) /* 8: TSC */ +#define STM32_IRQ_DMA1CH1 (STM32_IRQ_EXTINT + 9) /* 9: DMA1_CH1 */ +#define STM32_IRQ_DMA1CH2 (STM32_IRQ_EXTINT + 10) /* 10: DMA1_CH2 */ +#define STM32_IRQ_DMA1CH3 (STM32_IRQ_EXTINT + 10) /* 10: DMA1_CH3 */ +#define STM32_IRQ_DMA2CH1 (STM32_IRQ_EXTINT + 10) /* 10: DMA2_CH1 */ +#define STM32_IRQ_DMA2CH2 (STM32_IRQ_EXTINT + 10) /* 10: DMA2_CH2 */ +#define STM32_IRQ_DMA1CH4 (STM32_IRQ_EXTINT + 11) /* 11: DMA1_CH4 */ +#define STM32_IRQ_DMA1CH5 (STM32_IRQ_EXTINT + 11) /* 11: DMA1_CH5 */ +#define STM32_IRQ_DMA1CH6 (STM32_IRQ_EXTINT + 11) /* 11: DMA1_CH6 */ +#define STM32_IRQ_DMA1CH7 (STM32_IRQ_EXTINT + 11) /* 11: DMA1_CH7 */ +#define STM32_IRQ_DMA2CH3 (STM32_IRQ_EXTINT + 11) /* 11: DMA2_CH3 */ +#define STM32_IRQ_DMA2CH4 (STM32_IRQ_EXTINT + 11) /* 11: DMA2_CH4 */ +#define STM32_IRQ_DMA2CH5 (STM32_IRQ_EXTINT + 11) /* 11: DMA2_CH5 */ +#define STM32_IRQ_ADC (STM32_IRQ_EXTINT + 12) /* 12: ADC */ +#define STM32_IRQ_COMP (STM32_IRQ_EXTINT + 12) /* 12: COMP */ +#define STM32_IRQ_TIM1_BRK (STM32_IRQ_EXTINT + 13) /* 13: TIM1_BRK_UP_TRG_COM */ +#define STM32_IRQ_TIM1_CC (STM32_IRQ_EXTINT + 14) /* 14: TIM1_CC */ +#define STM32_IRQ_TIM2 (STM32_IRQ_EXTINT + 15) /* 15: TIM2 */ +#define STM32_IRQ_TIM3 (STM32_IRQ_EXTINT + 16) /* 16: TIM3 */ +#define STM32_IRQ_TIM6 (STM32_IRQ_EXTINT + 17) /* 17: TIM6 */ +#define STM32_IRQ_DAC (STM32_IRQ_EXTINT + 17) /* 17: DAC */ +#define STM32_IRQ_TIM7 (STM32_IRQ_EXTINT + 18) /* 18: TIM7 */ +#define STM32_IRQ_TIM14 (STM32_IRQ_EXTINT + 19) /* 19: TIM14 */ +#define STM32_IRQ_TIM15 (STM32_IRQ_EXTINT + 20) /* 20: TIM15 */ +#define STM32_IRQ_TIM16 (STM32_IRQ_EXTINT + 21) /* 21: TIM16 */ +#define STM32_IRQ_TIM17 (STM32_IRQ_EXTINT + 22) /* 22: TIM17 */ +#define STM32_IRQ_I2C1 (STM32_IRQ_EXTINT + 23) /* 23: I2C1 */ +#define STM32_IRQ_I2C2 (STM32_IRQ_EXTINT + 24) /* 24: I2C2 */ +#define STM32_IRQ_SPI1 (STM32_IRQ_EXTINT + 25) /* 25: SPI1 */ +#define STM32_IRQ_SPI2 (STM32_IRQ_EXTINT + 26) /* 26: SPI2 */ +#define STM32_IRQ_USART1 (STM32_IRQ_EXTINT + 27) /* 27: USART1 */ +#define STM32_IRQ_USART2 (STM32_IRQ_EXTINT + 28) /* 28: USART2 */ +#define STM32_IRQ_USART3 (STM32_IRQ_EXTINT + 29) /* 29: USART3 */ +#define STM32_IRQ_USART4 (STM32_IRQ_EXTINT + 29) /* 29: USART4 */ +#define STM32_IRQ_USART5 (STM32_IRQ_EXTINT + 29) /* 29: USART5 */ +#define STM32_IRQ_USART6 (STM32_IRQ_EXTINT + 29) /* 29: USART6 */ +#define STM32_IRQ_USART7 (STM32_IRQ_EXTINT + 29) /* 29: USART7 */ +#define STM32_IRQ_USART8 (STM32_IRQ_EXTINT + 29) /* 29: USART8 */ +#define STM32_IRQ_CEC (STM32_IRQ_EXTINT + 30) /* 30: HDMI CEC */ +#define STM32_IRQ_CAN (STM32_IRQ_EXTINT + 30) /* 30: HDMI CAN */ +#define STM32_IRQ_USB (STM32_IRQ_EXTINT + 31) /* 31: USB */ + +#define STM32_IRQ_NEXTINTS (32) + +#define NR_IRQS (STM32_IRQ_EXTINT + STM32_IRQ_NEXTINTS) + +#endif /* __ARCH_ARM_INCLUDE_STM32F0_IRQ_H */ diff --git a/arch/arm/include/stm32f0l0g0/chip.h b/arch/arm/include/stm32f0l0g0/chip.h deleted file mode 100644 index 11626cd2e83b3..0000000000000 --- a/arch/arm/include/stm32f0l0g0/chip.h +++ /dev/null @@ -1,776 +0,0 @@ -/**************************************************************************** - * arch/arm/include/stm32f0l0g0/chip.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_INCLUDE_STM32F0L0G0_CHIP_H -#define __ARCH_ARM_INCLUDE_STM32F0L0G0_CHIP_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -/**************************************************************************** - * Pre-processor Prototypes - ****************************************************************************/ - -/* Get customizations for each supported chip */ - -#if defined(CONFIG_ARCH_CHIP_STM32F030RC) || defined(CONFIG_ARCH_CHIP_STM32F030CC) - -# define STM32_FLASH_SIZE (256 * 1024) /* 256Kb */ -# define STM32_SRAM_SIZE (32 * 1024) /* 32Kb */ - -# define STM32_NSPI 2 /* Two SPI modules (SPI or I2S) */ -# define STM32_NI2S 0 /* No I2S modules */ -# define STM32_NI2C 2 /* Two I2C modules */ -# define STM32_NDMA 1 /* 1 DMA1, 7-channels */ -# define STM32_NUSART 6 /* Six USARTs modules */ -# define STM32_NCAN 0 /* No CAN controllers */ -# define STM32_NUSBDEV 0 /* One USB full-speed device controller */ -# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (only USB 2.0 device) */ -# define STM32_NADC 1 /* One 12-bit module */ -# define STM32_NDAC 0 /* One DAC channel */ -# define STM32_NCOMP 0 /* Two Analog Comparators */ -# define STM32_NCAP 0 /* Capacitive sensing channels (14 on UFQFPN32)) */ -# define STM32_NPORTS 5 /* Five GPIO ports, GPIOA-D, F */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F051R8) - -# define STM32_FLASH_SIZE (64 * 1024) /* 64Kb */ -# define STM32_SRAM_SIZE (8 * 1024) /* 8Kb */ - -# define STM32_NSPI 2 /* Two SPI modules (SPI or I2S) */ -# define STM32_NI2S 2 /* Two I2S modules (SPI or I2S) */ -# define STM32_NI2C 2 /* Two I2C modules */ -# define STM32_NDMA 1 /* 1 DMA1, 7-channels */ -# define STM32_NUSART 2 /* Two USARTs modules */ -# define STM32_NCAN 0 /* No CAN controllers */ -# define STM32_NUSBDEV 1 /* One USB full-speed device controller */ -# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (only USB 2.0 device) */ -# define STM32_NADC 1 /* One 12-bit module */ -# define STM32_NDAC 1 /* One DAC channel */ -# define STM32_NCOMP 2 /* Two Analog Comparators */ -# define STM32_NCAP 13 /* Capacitive sensing channels (14 on UFQFPN32)) */ -# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-F */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F072C8) || defined(CONFIG_ARCH_CHIP_STM32F072CB) - -# ifdef CONFIG_ARCH_CHIP_STM32F072C8 -# define STM32_FLASH_SIZE (64 * 1024) /* 64Kb */ -# else -# define STM32_FLASH_SIZE (128 * 1024) /* 128Kb */ -# endif -# define STM32_SRAM_SIZE (16 * 1024) /* 16Kb */ - -# define STM32_NATIM 1 /* One advanced timer TIM1 */ -# define STM32_NGTIM16 5 /* 16-bit general up/down timers TIM3, TIM14-17 */ -# define STM32_NGTIM32 1 /* 32-bit general up/down timers TIM2 */ -# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 */ -# define STM32_NSPI 2 /* Two SPI modules (SPI or I2S) */ -# define STM32_NI2S 2 /* Two I2S modules (SPI or I2S) */ -# define STM32_NI2C 2 /* Two I2C modules */ -# define STM32_NDMA 1 /* 1 DMA1, 7-channels */ -# define STM32_NUSART 4 /* Four USARTs module */ -# define STM32_NCAN 1 /* One CAN controller */ -# define STM32_NUSBDEV 1 /* One USB full-speed device controller */ -# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (only USB 2.0 device) */ -# define STM32_NCEC 1 /* One HDMI-CEC controller */ -# define STM32_NADC 1 /* One 12-bit module */ -# define STM32_NDAC 2 /* Two DAC channel */ -# define STM32_NCOMP 2 /* Two Analog Comparators */ -# define STM32_NCAP 17 /* Capacitive sensing channels */ -# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-F */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F072R8) || defined(CONFIG_ARCH_CHIP_STM32F072RB) - -# ifdef CONFIG_ARCH_CHIP_STM32F072R8 -# define STM32_FLASH_SIZE (64*1024) /* 64Kb */ -# else -# define STM32_FLASH_SIZE (128*1024) /* 128Kb */ -# endif -# define STM32_SRAM_SIZE (16*1024) /* 16Kb */ - -# define STM32_NATIM 1 /* One advanced timer TIM1 */ -# define STM32_NGTIM16 5 /* 16-bit general up/down timers TIM3, TIM14-17 */ -# define STM32_NGTIM32 1 /* 32-bit general up/down timers TIM2 */ -# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 */ -# define STM32_NSPI 2 /* Two SPI modules (SPI or I2S) */ -# define STM32_NI2S 2 /* Two I2S modules (SPI or I2S) */ -# define STM32_NI2C 2 /* Two I2C modules */ -# define STM32_NDMA 1 /* 1 DMA1, 7-channels */ -# define STM32_NUSART 4 /* Four USARTs module */ -# define STM32_NCAN 1 /* One CAN controller */ -# define STM32_NUSBDEV 1 /* One USB full-speed device controller */ -# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (only USB 2.0 device) */ -# define STM32_NCEC 1 /* One HDMI-CEC controller */ -# define STM32_NADC 1 /* One 12-bit module */ -# define STM32_NDAC 2 /* Two DAC channel */ -# define STM32_NCOMP 2 /* Two Analog Comparators */ -# define STM32_NCAP 18 /* Capacitive sensing channels */ -# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-F */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F072V8) || defined(CONFIG_ARCH_CHIP_STM32F072VB) - -# ifdef CONFIG_ARCH_CHIP_STM32F072V8 -# define STM32_FLASH_SIZE (64 * 1024) /* 64Kb */ -# else -# define STM32_FLASH_SIZE (128 * 1024) /* 128Kb */ -# endif -# define STM32_SRAM_SIZE (16 * 1024) /* 16Kb */ - -# define STM32_NATIM 1 /* One advanced timer TIM1 */ -# define STM32_NGTIM16 5 /* 16-bit general up/down timers TIM3, TIM14-17 */ -# define STM32_NGTIM32 1 /* 32-bit general up/down timers TIM2 */ -# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 */ -# define STM32_NSPI 2 /* Two SPI modules (SPI or I2S) */ -# define STM32_NI2S 2 /* Two I2S modules (SPI or I2S) */ -# define STM32_NI2C 2 /* Two I2C modules */ -# define STM32_NDMA 1 /* 1 DMA1, 7-channels */ -# define STM32_NUSART 4 /* Four USARTs module */ -# define STM32_NCAN 1 /* One CAN controller */ -# define STM32_NUSBDEV 1 /* One USB full-speed device controller */ -# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (only USB 2.0 device) */ -# define STM32_NCEC 1 /* One HDMI-CEC controller */ -# define STM32_NADC 1 /* One 12-bit module */ -# define STM32_NDAC 2 /* Two DAC channel */ -# define STM32_NCOMP 2 /* Two Analog Comparators */ -# define STM32_NCAP 24 /* Capacitive sensing channels */ -# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-F */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F091CB) || defined(CONFIG_ARCH_CHIP_STM32F091CC) - -# ifdef CONFIG_ARCH_CHIP_STM32F091CB -# define STM32_FLASH_SIZE (128 * 1024) /* 128Kb */ -# else -# define STM32_FLASH_SIZE (256 * 1024) /* 256Kb */ -# endif -# define STM32_SRAM_SIZE (32 * 1024) /* 32Kb */ - -# define STM32_NATIM 1 /* One advanced timer TIM1 */ -# define STM32_NGTIM16 5 /* 16-bit general up/down timers TIM3, TIM14-17 */ -# define STM32_NGTIM32 1 /* 32-bit general up/down timers TIM2 */ -# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 */ -# define STM32_NSPI 2 /* Two SPI modules (SPI or I2S) */ -# define STM32_NI2S 2 /* Two I2S modules (SPI or I2S) */ -# define STM32_NI2C 2 /* Two I2C modules */ -# define STM32_NDMA 2 /* DMA1, DMA2 */ -# define STM32_NUSART 6 /* Six USARTs modules */ -# define STM32_NCAN 1 /* One CAN controller */ -# define STM32_NUSBDEV 0 /* No USB full-speed device controller */ -# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (only USB 2.0 device) */ -# define STM32_NCEC 1 /* One HDMI-CEC controller */ -# define STM32_NADC 1 /* One 12-bit module */ -# define STM32_NDAC 2 /* Two DAC channel */ -# define STM32_NCOMP 2 /* Two Analog Comparators */ -# define STM32_NCAP 17 /* Capacitive sensing channels */ -# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-F */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F091RB) || defined(CONFIG_ARCH_CHIP_STM32F091RC) || \ - defined(CONFIG_ARCH_CHIP_STM32F091VB) || defined(CONFIG_ARCH_CHIP_STM32F091VC) - -# if defined(CONFIG_ARCH_CHIP_STM32F091RB) || defined(CONFIG_ARCH_CHIP_STM32F091VB) -# define STM32_FLASH_SIZE (128 * 1024) /* 128Kb */ -# else -# define STM32_FLASH_SIZE (256 * 1024) /* 256Kb */ -# endif -# define STM32_SRAM_SIZE (32 * 1024) /* 32Kb */ - -# define STM32_NATIM 1 /* One advanced timer TIM1 */ -# define STM32_NGTIM16 5 /* 16-bit general up/down timers TIM3, TIM14-17 */ -# define STM32_NGTIM32 1 /* 32-bit general up/down timers TIM2 */ -# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 */ -# define STM32_NSPI 2 /* Two SPI modules (SPI or I2S) */ -# define STM32_NI2S 2 /* Two I2S modules (SPI or I2S) */ -# define STM32_NI2C 2 /* Two I2C modules */ -# define STM32_NDMA 2 /* DMA1, DMA2 */ -# define STM32_NUSART 8 /* Eight USARTs modules */ -# define STM32_NCAN 1 /* One CAN controller */ -# define STM32_NUSBDEV 0 /* No USB full-speed device controller */ -# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (only USB 2.0 device) */ -# define STM32_NCEC 1 /* One HDMI-CEC controller */ -# define STM32_NADC 1 /* One 12-bit module */ -# define STM32_NDAC 2 /* Two DAC channel */ -# define STM32_NCOMP 2 /* Two Analog Comparators */ -# if defined(CONFIG_ARCH_CHIP_STM32F091VB) || defined(CONFIG_ARCH_CHIP_STM32F091VC) -# define STM32_NCAP 24 /* Capacitive sensing channels */ -# else -# define STM32_NCAP 18 /* Capacitive sensing channels */ -# endif -# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-F */ - -#elif defined(CONFIG_ARCH_CHIP_STM32G070KB) || defined(CONFIG_ARCH_CHIP_STM32G070CB) || \ - defined(CONFIG_ARCH_CHIP_STM32G070RB) - -# define STM32_FLASH_SIZE (128 * 1024) /* 128Kb */ -# define STM32_SRAM_SIZE (32 * 1024) /* 32Kb */ - -# define STM32_NATIM 1 /* One advanced timer TIM1 */ -# define STM32_NGTIM16 5 /* 16-bit general up/down timers TIM3, - * TIM14-17 */ -# define STM32_NGTIM32 0 /* No 32-bit general up/down timers */ -# define STM32_NBTIM 2 /* Two basic timers: TIM6, TIM7 */ -# define STM32_NSPI 2 /* Two SPI modules SPI1-2 */ -# define STM32_NI2S 1 /* One I2S module (SPI or I2S) */ -# define STM32_NI2C 2 /* Two I2C (1 with SMBus/PMBus) */ -# define STM32_NDMA 1 /* One DMA1, 7-channels */ -# define STM32_NUSART 4 /* Four USART modules, USART1-4 */ -# define STM32_NCAN 0 /* No CAN controllers */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBDEV 0 /* No USB full-speed device controller */ -# define STM32_NUSBOTG 0 /* No USB OTG */ -# define STM32_NCEC 0 /* One HDMI-CEC controller */ -# define STM32_NADC 1 /* (1) ADC1, 16-channels */ - -# define STM32_NDAC 0 /* No DAC */ -# define STM32_NCOMP 0 /* No Analog Comparators */ -# define STM32_NCRC 1 /* No CRC module */ -# define STM32_NRNG 0 /* No Random number generator (RNG) */ -# define STM32_NCAP 0 /* No Capacitive sensing channels */ -# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-F */ - -#elif defined(CONFIG_ARCH_CHIP_STM32G071EB) || defined(CONFIG_ARCH_CHIP_STM32G071G8) || \ - defined(CONFIG_ARCH_CHIP_STM32G071GB) || defined(CONFIG_ARCH_CHIP_STM32G071G8XN) || \ - defined(CONFIG_ARCH_CHIP_STM32G071GBXN) || defined(CONFIG_ARCH_CHIP_STM32G071K8) || \ - defined(CONFIG_ARCH_CHIP_STM32G071KB) || defined(CONFIG_ARCH_CHIP_STM32G071K8XN) || \ - defined(CONFIG_ARCH_CHIP_STM32G071KBXN) || defined(CONFIG_ARCH_CHIP_STM32G071C8) || \ - defined(CONFIG_ARCH_CHIP_STM32G071CB) || defined(CONFIG_ARCH_CHIP_STM32G071R8) || \ - defined(CONFIG_ARCH_CHIP_STM32G071RB) - -# define STM32_NATIM 1 /* One advanced timer TIM1 */ -# define STM32_NGTIM16 4 /* 16-bit general up/down timers TIM2-3 - * (with DMA) and TIM21-22 without DMA */ -# define STM32_NGTIM32 0 /* No 32-bit general up/down timers */ -# define STM32_NBTIM 2 /* Two basic timers: TIM6, TIM7 with DMA */ - /* Two LPTIMER */ -# define STM32_NSPI 2 /* Two SPI modules SPI1-2 */ -# define STM32_NI2C 2 /* Two I2C (2 with SMBus/PMBus) */ -# define STM32_NDMA 1 /* One DMA1, 7-channels */ -# define STM32_NUSART 4 /* Four USART modules, USART1-4 */ - /* One LPUART */ -# define STM32_NCAN 0 /* No CAN controllers */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBDEV 0 /* No USB full-speed device controller */ -# define STM32_NUSBOTG 0 /* No USB OTG */ -# define STM32_NCEC 1 /* One HDMI-CEC controller */ -# define STM32_NADC 1 /* (1) ADC1, 12-channels */ - -# define STM32_NDAC 2 /* Two DAC channels */ -# define STM32_NCOMP 2 /* Two Analog Comparators */ -# define STM32_NCRC 0 /* No CRC module */ -# define STM32_NRNG 0 /* No Random number generator (RNG) */ -# define STM32_NCAP 0 /* No Capacitive sensing channels */ -# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-F */ - -#elif defined(CONFIG_ARCH_CHIP_STM32G0B1KB) || defined(CONFIG_ARCH_CHIP_STM32G0B1CB) || \ - defined(CONFIG_ARCH_CHIP_STM32G0B1RB) || defined(CONFIG_ARCH_CHIP_STM32G0B1MB) || \ - defined(CONFIG_ARCH_CHIP_STM32G0B1VB) || defined(CONFIG_ARCH_CHIP_STM32G0B1KC) || \ - defined(CONFIG_ARCH_CHIP_STM32G0B1CC) || defined(CONFIG_ARCH_CHIP_STM32G0B1RC) || \ - defined(CONFIG_ARCH_CHIP_STM32G0B1MC) || defined(CONFIG_ARCH_CHIP_STM32G0B1VC) || \ - defined(CONFIG_ARCH_CHIP_STM32G0B1KE) || defined(CONFIG_ARCH_CHIP_STM32G0B1CE) || \ - defined(CONFIG_ARCH_CHIP_STM32G0B1RE) || defined(CONFIG_ARCH_CHIP_STM32G0B1NE) || \ - defined(CONFIG_ARCH_CHIP_STM32G0B1ME) || defined(CONFIG_ARCH_CHIP_STM32G0B1VE) - -# define STM32_NATIM 1 /* One advanced timer TIM1 */ -# define STM32_NGTIM16 6 /* 16-bit general purpose timers */ -# define STM32_NGTIM32 1 /* TIM2 */ -# define STM32_NBTIM 2 /* Two basic timers: TIM6, TIM7 with DMA */ - /* One LPTIMER */ -# define STM32_NSPI 3 /* Two SPI modules SPI1-2 */ -# define STM32_NI2C 3 /* Two I2C (2 with SMBus/PMBus) */ -# define STM32_NDMA 2 /* DMA1 7-channels, DMA2 5-channels DMA1 */ -# define STM32_NUSART 6 /* Six USART modules, USART1-6 */ - /* Two LPUART */ -# define STM32_NCAN 1 /* One FDCAN controller */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBDEV 1 /* One USB full-speed controller */ -# define STM32_NUSBOTG 0 /* No USB OTG */ -# define STM32_NCEC 1 /* One HDMI-CEC controller */ -# define STM32_NADC 1 /* (1) ADC1, 12-channels */ - -# define STM32_NDAC 2 /* Two DAC channels */ -# define STM32_NCOMP 3 /* Three Analog Comparators */ -# define STM32_NCRC 0 /* No CRC module */ -# define STM32_NRNG 1 /* One Random number generator (RNG) */ -# define STM32_NCAP 0 /* No Capacitive sensing channels */ -# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-F */ - -/* STM32L EnergyLite Line ***************************************************/ - -/* STM32L073XX - With LCD - * STM32L072XX - No LCD - * STM32L071XX - Access line, no LCD - * - * STM32L0XXX8 - 64KB FLASH, 20KB SRAM, 3KB EEPROM - * STM32L0XXXB - 128KB FLASH, 20KB SRAM, 6KB EEPROM - * STM32L0XXXZ - 192KB FLASH, 20KB SRAM, 3KB EEPROM - * - * STM32L0XXCX - 48-pins - * STM32L0XXRX - 64-pins - * STM32L0XXVX - 100-pins - */ - -#elif defined(CONFIG_ARCH_CHIP_STM32L071K8) -# define STM32_NATIM 0 /* No advanced timers */ -# define STM32_NGTIM16 4 /* 16-bit general up/down timers TIM2-3 - * (with DMA) and TIM21-22 without DMA */ -# define STM32_NGTIM32 0 /* No 32-bit general up/down timers */ -# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 with DMA */ - /* 1 LPTIMER */ -# define STM32_NSPI 1 /* 1 SPI modules SPI1 */ -# define STM32_NI2S 0 /* 0 I2S module */ -# define STM32_NI2C 2 /* 2 I2C */ -# define STM32_NDMA 1 /* 1 DMA1, 7-channels */ -# define STM32_NUSART 3 /* 3 USART modules, USART1-3 */ - /* 1 LPUART */ -# define STM32_NCAN 0 /* 0 CAN controllers */ -# define STM32_NLCD 0 /* 0 LCD */ -# define STM32_NUSBDEV 0 /* 0 USB full-speed device controller */ -# define STM32_NUSBOTG 0 /* 0 USB OTG FS/HS (only USB 2.0 device) */ -# define STM32_NCEC 0 /* 0 HDMI-CEC controller */ -# define STM32_NADC 1 /* One 12-bit module */ -# define STM32_NDAC 0 /* 0 DAC channel */ -# define STM32_NCOMP 2 /* 2 Analog Comparators */ -# define STM32_NCRC 0 /* 0 CRC module */ -# define STM32_NRNG 0 /* 0 Random number generator (RNG) */ -# define STM32_NCAP 0 /* 0 Capacitive sensing channels */ -# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-E, H */ - -#elif defined(CONFIG_ARCH_CHIP_STM32L053C8) -# define STM32_NATIM 0 /* No advanced timers */ -# define STM32_NGTIM16 3 /* 16-bit general up/down timers TIM2-3 - * (with DMA) and TIM22 without DMA */ -# define STM32_NGTIM32 0 /* No 32-bit general up/down timers */ -# define STM32_NBTIM 1 /* 1 basic timers: TIM6 with DMA */ - /* 1 LPTIMER */ -# define STM32_NSPI 2 /* 2 SPI modules SPI1 */ -# define STM32_NI2S 1 /* 1 I2S module */ -# define STM32_NI2C 2 /* 2 I2C */ -# define STM32_NDMA 1 /* 1 DMA1, 7-channels */ -# define STM32_NUSART 2 /* 2 USART modules, USART1-1 */ - /* 1 LPUART */ -# define STM32_NCAN 0 /* 0 CAN controllers */ -# define STM32_NLCD 1 /* 1 LCD */ -# define STM32_NUSBDEV 1 /* 1 USB full-speed device controller */ -# define STM32_NUSBOTG 0 /* 0 USB OTG FS/HS (only USB 2.0 device) */ -# define STM32_NCEC 0 /* 0 HDMI-CEC controller */ -# define STM32_NADC 1 /* One 12-bit module */ -# define STM32_NDAC 0 /* 0 DAC channel */ -# define STM32_NCOMP 2 /* 2 Analog Comparators */ -# define STM32_NCRC 0 /* 0 CRC module */ -# define STM32_NRNG 0 /* 0 Random number generator (RNG) */ -# define STM32_NCAP 24 /* 24 Capacitive sensing channels */ -# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-E, H */ - -#elif defined(CONFIG_ARCH_CHIP_STM32L053R8) -# define STM32_NATIM 0 /* No advanced timers */ -# define STM32_NGTIM16 3 /* 16-bit general up/down timers TIM2-3 - * (with DMA) and TIM22 without DMA */ -# define STM32_NGTIM32 0 /* No 32-bit general up/down timers */ -# define STM32_NBTIM 1 /* 1 basic timers: TIM6 with DMA */ - /* 1 LPTIMER */ -# define STM32_NSPI 2 /* 2 SPI modules SPI1 */ -# define STM32_NI2S 1 /* 1 I2S module */ -# define STM32_NI2C 2 /* 2 I2C */ -# define STM32_NDMA 1 /* 1 DMA1, 7-channels */ -# define STM32_NUSART 2 /* 2 USART modules, USART1-1 */ - /* 1 LPUART */ -# define STM32_NCAN 0 /* 0 CAN controllers */ -# define STM32_NLCD 1 /* 1 LCD */ -# define STM32_NUSBDEV 1 /* 1 USB full-speed device controller */ -# define STM32_NUSBOTG 0 /* 0 USB OTG FS/HS (only USB 2.0 device) */ -# define STM32_NCEC 0 /* 0 HDMI-CEC controller */ -# define STM32_NADC 1 /* One 12-bit module */ -# define STM32_NDAC 0 /* 0 DAC channel */ -# define STM32_NCOMP 2 /* 2 Analog Comparators */ -# define STM32_NCRC 0 /* 0 CRC module */ -# define STM32_NRNG 0 /* 0 Random number generator (RNG) */ -# define STM32_NCAP 24 /* 24 Capacitive sensing channels */ -# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-E, H */ - -#elif defined(CONFIG_ARCH_CHIP_STM32L071C8) || defined(CONFIG_ARCH_CHIP_STM32L071V8) || \ - defined(CONFIG_ARCH_CHIP_STM32L071CB) || defined(CONFIG_ARCH_CHIP_STM32L071VB) || \ - defined(CONFIG_ARCH_CHIP_STM32L071RB) || defined(CONFIG_ARCH_CHIP_STM32L071CZ) || \ - defined(CONFIG_ARCH_CHIP_STM32L071VZ) || defined(CONFIG_ARCH_CHIP_STM32L071RZ) -# define STM32_NATIM 0 /* 0 advanced timers */ -# define STM32_NGTIM16 4 /* 16-bit general up/down timers TIM2-3 - * (with DMA) and TIM21-22 without DMA */ -# define STM32_NGTIM32 0 /* 0 32-bit general up/down timers */ -# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 with DMA */ - /* 1 LPTIMER */ -# define STM32_NSPI 2 /* 2 SPI modules SPI1-2 */ -# define STM32_NI2S 1 /* 1 I2S module */ -# define STM32_NI2C 3 /* 3 I2C */ -# define STM32_NDMA 1 /* 1 DMA1, 7-channels */ -# define STM32_NUSART 4 /* 4 USART modules, USART1-4 */ - /* 1 LPUART */ -# define STM32_NCAN 0 /* 0 CAN controllers */ -# define STM32_NLCD 0 /* 0 LCD */ -# define STM32_NUSBDEV 0 /* 0 USB full-speed device controller */ -# define STM32_NUSBOTG 0 /* 0 USB OTG FS/HS (only USB 2.0 device) */ -# define STM32_NCEC 0 /* 0 HDMI-CEC controller */ -# define STM32_NADC 1 /* One 12-bit module */ -# define STM32_NDAC 0 /* 0 DAC channel */ -# define STM32_NCOMP 2 /* 2 Analog Comparators */ -# define STM32_NCRC 0 /* 0 CRC module */ -# define STM32_NRNG 0 /* 0 Random number generator (RNG) */ -# define STM32_NCAP 0 /* 0 Capacitive sensing channels */ -# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-E, H */ - -#elif defined(CONFIG_ARCH_CHIP_STM32L071KB) || defined(CONFIG_ARCH_CHIP_STM32L071KZ) -# define STM32_NATIM 0 /* 0 advanced timers */ -# define STM32_NGTIM16 4 /* 16-bit general up/down timers TIM2-3 - * (with DMA) and TIM21-22 without DMA */ -# define STM32_NGTIM32 0 /* 0 32-bit general up/down timers */ -# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 with DMA */ - /* 1 LPTIMER */ -# define STM32_NSPI 1 /* 1 SPI modules SPI1 */ -# define STM32_NI2S 0 /* 0 I2S module */ -# define STM32_NI2C 3 /* 3 I2C */ -# define STM32_NDMA 1 /* 1 DMA1, 7-channels */ -# define STM32_NUSART 4 /* 4 USART modules, USART1-4 */ - /* 1 LPUART */ -# define STM32_NCAN 0 /* 0 CAN controllers */ -# define STM32_NLCD 0 /* 0 LCD */ -# define STM32_NUSBDEV 0 /* 0 USB full-speed device controller */ -# define STM32_NUSBOTG 0 /* 0 USB OTG FS/HS (only USB 2.0 device) */ -# define STM32_NCEC 0 /* 0 HDMI-CEC controller */ -# define STM32_NADC 1 /* One 12-bit module */ -# define STM32_NDAC 0 /* 0 DAC channel */ -# define STM32_NCOMP 2 /* 2 Analog Comparators */ -# define STM32_NCRC 0 /* 0 CRC module */ -# define STM32_NRNG 0 /* 0 Random number generator (RNG) */ -# define STM32_NCAP 0 /* 0 Capacitive sensing channels */ -# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-E, H */ - -#elif defined(CONFIG_ARCH_CHIP_STM32L072V8) || defined(CONFIG_ARCH_CHIP_STM32L072VB) || \ - defined(CONFIG_ARCH_CHIP_STM32L072VZ) -# define STM32_NATIM 0 /* No advanced timers */ -# define STM32_NGTIM16 4 /* 16-bit general up/down timers TIM2-3 - * (with DMA) and TIM21-22 without DMA */ -# define STM32_NGTIM32 0 /* No 32-bit general up/down timers */ -# define STM32_NBTIM 2 /* Two basic timers: TIM6, TIM7 with DMA */ - /* One LPTIMER */ -# define STM32_NSPI 2 /* Two SPI modules SPI1-2 */ -# define STM32_NI2S 1 /* One I2S module */ -# define STM32_NI2C 3 /* Three I2C (2 with SMBus/PMBus) */ -# define STM32_NDMA 1 /* One DMA1, 7-channels */ -# define STM32_NUSART 4 /* Four USART modules, USART1-4 */ - /* One LPUART */ -# define STM32_NCAN 0 /* No CAN controllers */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBDEV 0 /* No USB full-speed device controller */ -# define STM32_NUSBOTG 1 /* One USB OTG FS/HS (only USB 2.0 device) */ -# define STM32_NCEC 0 /* No HDMI-CEC controller */ -# define STM32_NADC 1 /* One 12-bit module */ -# define STM32_NDAC 2 /* Two DAC channels */ -# define STM32_NCOMP 2 /* Two Analog Comparators */ -# define STM32_NCRC 1 /* One CRC module */ -# define STM32_NRNG 1 /* One Random number generator (RNG) */ -# define STM32_NCAP 24 /* Twenty-four Capacitive sensing channels */ -# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-E, H */ - -#elif defined(CONFIG_ARCH_CHIP_STM32L072KB) || defined(CONFIG_ARCH_CHIP_STM32L072KZ) -# define STM32_NATIM 0 /* No advanced timers */ -# define STM32_NGTIM16 4 /* 16-bit general up/down timers TIM2-3 - * (with DMA) and TIM21-22 without DMA */ -# define STM32_NGTIM32 0 /* No 32-bit general up/down timers */ -# define STM32_NBTIM 2 /* Two basic timers: TIM6, TIM7 with DMA */ - /* One LPTIMER */ -# define STM32_NSPI 2 /* Two SPI modules SPI1-2 */ -# define STM32_NI2C 3 /* Three I2C (2 with SMBus/PMBus) */ -# define STM32_NDMA 1 /* One DMA1, 7-channels */ -# define STM32_NUSART 4 /* Four USART modules, USART1-4 */ - /* One LPUART */ -# define STM32_NCAN 0 /* No CAN controllers */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBDEV 0 /* No USB full-speed device controller */ -# define STM32_NUSBOTG 1 /* One USB OTG FS/HS (only USB 2.0 device) */ -# define STM32_NCEC 0 /* No HDMI-CEC controller */ -# define STM32_NADC 1 /* One 12-bit module */ -# define STM32_NDAC 2 /* Two DAC channels */ -# define STM32_NCOMP 2 /* Two Analog Comparators */ -# define STM32_NCRC 1 /* One CRC module */ -# define STM32_NRNG 1 /* One Random number generator (RNG) */ -# define STM32_NCAP 13 /* Thirteen Capacitive sensing channels */ -# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-E, H */ - -#elif defined(CONFIG_ARCH_CHIP_STM32L072CB) || defined(CONFIG_ARCH_CHIP_STM32L072CZ) -# define STM32_NATIM 0 /* No advanced timers */ -# define STM32_NGTIM16 4 /* 16-bit general up/down timers TIM2-3 - * (with DMA) and TIM21-22 without DMA */ -# define STM32_NGTIM32 0 /* No 32-bit general up/down timers */ -# define STM32_NBTIM 2 /* Two basic timers: TIM6, TIM7 with DMA */ - /* One LPTIMER */ -# define STM32_NSPI 2 /* Two SPI modules SPI1-2 */ -# define STM32_NI2S 1 /* One I2S module */ -# define STM32_NI2C 3 /* Three I2C (2 with SMBus/PMBus) */ -# define STM32_NDMA 1 /* One DMA1, 7-channels */ -# define STM32_NUSART 4 /* Four USART modules, USART1-4 */ - /* One LPUART */ -# define STM32_NCAN 0 /* No CAN controllers */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBDEV 0 /* No USB full-speed device controller */ -# define STM32_NUSBOTG 1 /* One USB OTG FS/HS (only USB 2.0 device) */ -# define STM32_NCEC 0 /* No HDMI-CEC controller */ -# define STM32_NADC 1 /* One 12-bit module */ -# define STM32_NDAC 2 /* Two DAC channels */ -# define STM32_NCOMP 2 /* Two Analog Comparators */ -# define STM32_NCRC 1 /* One CRC module */ -# define STM32_NRNG 1 /* One Random number generator (RNG) */ -# define STM32_NCAP 18 /* Nineteen Capacitive sensing channels */ -# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-E, H */ - -#elif defined(CONFIG_ARCH_CHIP_STM32L072RB) || defined(CONFIG_ARCH_CHIP_STM32L072RZ) -# define STM32_NATIM 0 /* No advanced timers */ -# define STM32_NGTIM16 4 /* 16-bit general up/down timers TIM2-3 - * (with DMA) and TIM21-22 without DMA */ -# define STM32_NGTIM32 0 /* No 32-bit general up/down timers */ -# define STM32_NBTIM 2 /* Two basic timers: TIM6, TIM7 with DMA */ - /* One LPTIMER */ -# define STM32_NSPI 2 /* Two SPI modules SPI1-2 */ -# define STM32_NI2S 1 /* One I2S module */ -# define STM32_NI2C 3 /* Three I2C (2 with SMBus/PMBus) */ -# define STM32_NDMA 1 /* One DMA1, 7-channels */ -# define STM32_NUSART 4 /* Four USART modules, USART1-4 */ - /* One LPUART */ -# define STM32_NCAN 0 /* No CAN controllers */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBDEV 0 /* No USB full-speed device controller */ -# define STM32_NUSBOTG 1 /* One USB OTG FS/HS (only USB 2.0 device) */ -# define STM32_NCEC 0 /* No HDMI-CEC controller */ -# define STM32_NADC 1 /* One 12-bit module */ -# define STM32_NDAC 2 /* Two DAC channels */ -# define STM32_NCOMP 2 /* Two Analog Comparators */ -# define STM32_NCRC 1 /* One CRC module */ -# define STM32_NRNG 1 /* One Random number generator (RNG) */ -# define STM32_NCAP 24 /* Twenty-four Capacitive sensing channels */ -# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-E, H */ - -#elif defined(CONFIG_ARCH_CHIP_STM32L073V8) || defined(CONFIG_ARCH_CHIP_STM32L073VB) || \ - defined(CONFIG_ARCH_CHIP_STM32L073VZ) -# define STM32_NATIM 0 /* No advanced timers */ -# define STM32_NGTIM16 4 /* 16-bit general up/down timers TIM2-3 - * (with DMA) and TIM21-22 without DMA */ -# define STM32_NGTIM32 0 /* No 32-bit general up/down timers */ -# define STM32_NBTIM 2 /* Two basic timers: TIM6, TIM7 with DMA */ - /* One LPTIMER */ -# define STM32_NSPI 2 /* Two SPI modules SPI1-2 */ -# define STM32_NI2S 1 /* One I2S module */ -# define STM32_NI2C 3 /* Three I2C (2 with SMBus/PMBus) */ -# define STM32_NDMA 1 /* One DMA1, 7-channels */ -# define STM32_NUSART 4 /* Four USART modules, USART1-4 */ - /* One LPUART */ -# define STM32_NCAN 0 /* No CAN controllers */ -# define STM32_NLCD 1 /* One LCD controller */ -# define STM32_NUSBDEV 0 /* No USB full-speed device controller */ -# define STM32_NUSBOTG 1 /* One USB OTG FS/HS (only USB 2.0 device) */ -# define STM32_NCEC 0 /* No HDMI-CEC controller */ -# define STM32_NADC 1 /* One 12-bit module */ -# define STM32_NDAC 2 /* Two DAC channels */ -# define STM32_NCOMP 2 /* Two Analog Comparators */ -# define STM32_NCRC 1 /* One CRC module */ -# define STM32_NRNG 1 /* One Random number generator (RNG) */ -# define STM32_NCAP 24 /* Twenty-four Capacitive sensing channels */ -# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-E, H */ - -#elif defined(CONFIG_ARCH_CHIP_STM32L073CB) || defined(CONFIG_ARCH_CHIP_STM32L073CZ) -# define STM32_NATIM 0 /* No advanced timers */ -# define STM32_NGTIM16 4 /* 16-bit general up/down timers TIM2-3 - * (with DMA) and TIM21-22 without DMA */ -# define STM32_NGTIM32 0 /* No 32-bit general up/down timers */ -# define STM32_NBTIM 2 /* Two basic timers: TIM6, TIM7 with DMA */ - /* One LPTIMER */ -# define STM32_NSPI 2 /* Two SPI modules SPI1-2 */ -# define STM32_NI2S 1 /* One I2S module */ -# define STM32_NI2C 3 /* Three I2C (2 with SMBus/PMBus) */ -# define STM32_NDMA 1 /* One DMA1, 7-channels */ -# define STM32_NUSART 4 /* Four USART modules, USART1-4 */ - /* One LPUART */ -# define STM32_NCAN 0 /* No CAN controllers */ -# define STM32_NLCD 1 /* One LCD controller */ -# define STM32_NUSBDEV 0 /* No USB full-speed device controller */ -# define STM32_NUSBOTG 1 /* One USB OTG FS/HS (only USB 2.0 device) */ -# define STM32_NCEC 0 /* No HDMI-CEC controller */ -# define STM32_NADC 1 /* One 12-bit module */ -# define STM32_NDAC 2 /* Two DAC channels */ -# define STM32_NCOMP 2 /* Two Analog Comparators */ -# define STM32_NCRC 1 /* One CRC module */ -# define STM32_NRNG 1 /* One Random number generator (RNG) */ -# define STM32_NCAP 17 /* Seventeen Capacitive sensing channels */ -# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-E, H */ - -#elif defined(CONFIG_ARCH_CHIP_STM32L073RB) || defined(CONFIG_ARCH_CHIP_STM32L073RZ) -# define STM32_NATIM 0 /* No advanced timers */ -# define STM32_NGTIM16 4 /* 16-bit general up/down timers TIM2-3 - * (with DMA) and TIM21-22 without DMA */ -# define STM32_NGTIM32 0 /* No 32-bit general up/down timers */ -# define STM32_NBTIM 2 /* Two basic timers: TIM6, TIM7 with DMA */ - /* One LPTIMER */ -# define STM32_NSPI 2 /* Two SPI modules SPI1-2 */ -# define STM32_NI2S 1 /* One I2S module */ -# define STM32_NI2C 3 /* Three I2C (2 with SMBus/PMBus) */ -# define STM32_NDMA 1 /* One DMA1, 7-channels */ -# define STM32_NUSART 4 /* Four USART modules, USART1-4 */ - /* One LPUART */ -# define STM32_NCAN 0 /* No CAN controllers */ -# define STM32_NLCD 1 /* One LCD controller */ -# define STM32_NUSBDEV 0 /* No USB full-speed device controller */ -# define STM32_NUSBOTG 1 /* One USB OTG FS/HS (only USB 2.0 device) */ -# define STM32_NCEC 0 /* No HDMI-CEC controller */ -# define STM32_NADC 1 /* One 12-bit module */ -# define STM32_NDAC 2 /* Two DAC channels */ -# define STM32_NCOMP 2 /* Two Analog Comparators */ -# define STM32_NCRC 1 /* One CRC module */ -# define STM32_NRNG 1 /* One Random number generator (RNG) */ -# define STM32_NCAP 24 /* Twenty-four Capacitive sensing channels */ -# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-E, H */ -#elif defined(CONFIG_ARCH_CHIP_STM32C051XX) -# define STM32_NATIM 1 /* One advanced timers TIM1 */ -# define STM32_NGTIM16 4 /* Four 16-bit general up/down timers TIM3, TIM14, - * TIM16 and TIM17 */ -# define STM32_NGTIM32 1 /* One 32-bit general up/down timer TIM2 */ -# define STM32_NBTIM 0 /* No basic timers */ - /* One LPTIMER */ -# define STM32_NSPI 2 /* Two SPI modules SPI1-2 */ -# define STM32_NI2S 0 /* No I2S module */ -# define STM32_NI2C 2 /* Two I2C */ -# define STM32_NDMA 1 /* One DMA1, 5-channels */ -# define STM32_NUSART 2 /* Two USART modules, USART1-2 */ -# define STM32_NCAN 0 /* No CAN controllers */ -# define STM32_FDCAN 0 /* No FD CAN */ -# define STM32_NLCD 0 /* No LCD controller */ -# define STM32_NUSBDEV 0 /* No USB full-speed device controller */ -# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (only USB 2.0 device) */ -# define STM32_NCEC 0 /* No HDMI-CEC controller */ -# define STM32_NADC 1 /* One 12-bit module */ -# define STM32_NDAC 0 /* No DAC channels */ -# define STM32_NCOMP 0 /* No Analog Comparators */ -# define STM32_NCRC 1 /* One CRC module */ -# define STM32_NRNG 0 /* No Random number generator (RNG) */ -# define STM32_NCAP 0 /* No Capacitive sensing channels */ -# define STM32_NPORTS 5 /* Five GPIO ports, GPIOA-D, F */ -#elif defined(CONFIG_ARCH_CHIP_STM32C071XX) -# define STM32_NATIM 1 /* One advanced timers TIM1 */ -# define STM32_NGTIM16 4 /* 16-bit general up/down timers TIM3, TIM14, - * TIM16 and TIM17 */ -# define STM32_NGTIM32 1 /* One 32-bit general up/down timer TIM2 */ -# define STM32_NBTIM 0 /* No basic timers */ - /* One LPTIMER */ -# define STM32_NSPI 2 /* Two SPI modules SPI1-2 */ -# define STM32_NI2S 0 /* No I2S module */ -# define STM32_NI2C 2 /* Two I2C */ -# define STM32_NDMA 1 /* One DMA1, 5-channels */ -# define STM32_NUSART 2 /* Two USART modules, USART1-2 */ -# define STM32_NCAN 0 /* No CAN controllers */ -# define STM32_FDCAN 0 /* No FD CAN */ -# define STM32_NLCD 0 /* No LCD controller */ -# define STM32_NUSBDEV 1 /* USB full-speed device controller */ -# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (only USB 2.0 device) */ -# define STM32_NCEC 0 /* No HDMI-CEC controller */ -# define STM32_NADC 1 /* One 12-bit module */ -# define STM32_NDAC 0 /* No DAC channels */ -# define STM32_NCOMP 0 /* No Analog Comparators */ -# define STM32_NCRC 1 /* One CRC module */ -# define STM32_NRNG 0 /* No Random number generator (RNG) */ -# define STM32_NCAP 0 /* No Capacitive sensing channels */ -# define STM32_NPORTS 5 /* Five GPIO ports, GPIOA-D, F */ -#elif defined(CONFIG_ARCH_CHIP_STM32C091XX) -# define STM32_NATIM 1 /* One advanced timers TIM1 */ -# define STM32_NGTIM16 5 /* 16-bit general up/down timers TIM3, TIM14, - * TIM15, TIM16 and TIM17 */ -# define STM32_NGTIM32 1 /* One 32-bit general up/down timer TIM2 */ -# define STM32_NBTIM 0 /* No basic timers */ - /* One LPTIMER */ -# define STM32_NSPI 2 /* Two SPI modules SPI1-2 */ -# define STM32_NI2S 0 /* No I2S module */ -# define STM32_NI2C 2 /* Two I2C */ -# define STM32_NDMA 1 /* One DMA1, 5-channels */ -# define STM32_NUSART 4 /* Four USART modules, USART1-4 */ -# define STM32_NCAN 0 /* No CAN controllers */ -# define STM32_FDCAN 0 /* No FD CAN */ -# define STM32_NLCD 0 /* No LCD controller */ -# define STM32_NUSBDEV 1 /* USB full-speed device controller */ -# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (only USB 2.0 device) */ -# define STM32_NCEC 0 /* No HDMI-CEC controller */ -# define STM32_NADC 1 /* One 12-bit module */ -# define STM32_NDAC 0 /* No DAC channels */ -# define STM32_NCOMP 0 /* No Analog Comparators */ -# define STM32_NCRC 1 /* One CRC module */ -# define STM32_NRNG 0 /* No Random number generator (RNG) */ -# define STM32_NCAP 0 /* No Capacitive sensing channels */ -# define STM32_NPORTS 5 /* Five GPIO ports, GPIOA-D, F */ -#elif defined(CONFIG_ARCH_CHIP_STM32C092XX) -# define STM32_NATIM 1 /* One advanced timers TIM1 */ -# define STM32_NGTIM16 5 /* 16-bit general up/down timers TIM3, TIM14, - * TIM15, TIM16 and TIM17 */ -# define STM32_NGTIM32 1 /* One 32-bit general up/down timer TIM2 */ -# define STM32_NBTIM 0 /* No basic timers */ - /* One LPTIMER */ -# define STM32_NSPI 2 /* Two SPI modules SPI1-2 */ -# define STM32_NI2S 0 /* No I2S module */ -# define STM32_NI2C 2 /* Two I2C */ -# define STM32_NDMA 1 /* One DMA1, 5-channels */ -# define STM32_NUSART 4 /* Four USART modules, USART1-4 */ -# define STM32_NCAN 0 /* No CAN controllers */ -# define STM32_FDCAN 1 /* One FD CAN */ -# define STM32_NLCD 0 /* No LCD controller */ -# define STM32_NUSBDEV 1 /* USB full-speed device controller */ -# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (only USB 2.0 device) */ -# define STM32_NCEC 0 /* No HDMI-CEC controller */ -# define STM32_NADC 1 /* One 12-bit module */ -# define STM32_NDAC 0 /* No DAC channels */ -# define STM32_NCOMP 0 /* No Analog Comparators */ -# define STM32_NCRC 1 /* One CRC module */ -# define STM32_NRNG 0 /* No Random number generator (RNG) */ -# define STM32_NCAP 0 /* No Capacitive sensing channels */ -# define STM32_NPORTS 5 /* Five GPIO ports, GPIOA-D, F */ -#else -# error "Unsupported STM32 Cortex M0 chip" -#endif - -/* NVIC priority levels *****************************************************/ - -/* Each priority field holds a priority value, 0-31. The lower the value, - * the greater the priority of the corresponding interrupt. The processor - * implements only bits[7:6] of each field, bits[5:0] read as zero and - * ignore writes. - */ - -#define NVIC_SYSH_PRIORITY_MIN 0xc0 /* All bits[7:6] set is minimum priority */ -#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */ -#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */ -#define NVIC_SYSH_PRIORITY_STEP 0x40 /* Two bits of interrupt priority used */ - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -#endif /* __ARCH_ARM_INCLUDE_STM32F0L0G0_CHIP_H */ diff --git a/arch/arm/include/stm32f0l0g0/irq.h b/arch/arm/include/stm32f0l0g0/irq.h deleted file mode 100644 index 450d793e120de..0000000000000 --- a/arch/arm/include/stm32f0l0g0/irq.h +++ /dev/null @@ -1,114 +0,0 @@ -/**************************************************************************** - * arch/arm/include/stm32f0l0g0/irq.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* This file should never be included directly but, rather, only indirectly - * through nuttx/irq.h - */ - -#ifndef __ARCH_ARM_INCLUDE_STM32F0L0G0_IRQ_H -#define __ARCH_ARM_INCLUDE_STM32F0L0G0_IRQ_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#ifndef __ASSEMBLY__ -# include -#endif -#include - -/**************************************************************************** - * Pre-processor Prototypes - ****************************************************************************/ - -/* IRQ numbers. The IRQ number corresponds vector number and hence map - * directly to bits in the NVIC. This does, however, waste several words of - * memory in the IRQ to handle mapping tables. - */ - -/* Common Processor Exceptions (vectors 0-15) */ - -#define STM32_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */ - /* Vector 0: Reset stack pointer value */ - /* Vector 1: Reset (not handler as an IRQ) */ -#define STM32_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */ -#define STM32_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */ - /* Vectors 4-10: Reserved */ -#define STM32_IRQ_SVCALL (11) /* Vector 11: SVC call */ - /* Vector 12-13: Reserved */ -#define STM32_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */ -#define STM32_IRQ_SYSTICK (15) /* Vector 15: System tick */ - -/* External interrupts (vectors >= 16) */ - -#define STM32_IRQ_EXTINT (16) /* Vector number of the first external interrupt */ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -/* Include MCU-specific external interrupt definitions */ - -#if defined(CONFIG_ARCH_CHIP_STM32F0) -# include -#elif defined(CONFIG_ARCH_CHIP_STM32L0) -# include -#elif defined(CONFIG_ARCH_CHIP_STM32G0) -# include -#elif defined(CONFIG_ARCH_CHIP_STM32C0) -# include -#else -# error Unrecognized STM32 Cortex M0 family -#endif - -#define NR_IRQS (STM32_IRQ_EXTINT + STM32_IRQ_NEXTINTS) - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -#ifndef __ASSEMBLY__ -typedef void (*vic_vector_t)(uint32_t *regs); - -/**************************************************************************** - * Inline functions - ****************************************************************************/ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -#ifdef __cplusplus -extern "C" -{ -#endif - -#ifdef __cplusplus -} -#endif -#endif /* __ASSEMBLY__ */ - -#endif /* __ARCH_ARM_INCLUDE_STM32F0L0G0_IRQ_H */ diff --git a/arch/arm/include/stm32f0l0g0/stm32c0_irq.h b/arch/arm/include/stm32f0l0g0/stm32c0_irq.h deleted file mode 100644 index fe52e407a7dee..0000000000000 --- a/arch/arm/include/stm32f0l0g0/stm32c0_irq.h +++ /dev/null @@ -1,117 +0,0 @@ -/**************************************************************************** - * arch/arm/include/stm32f0l0g0/stm32c0_irq.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* This file should never be included directly but, rather, only indirectly - * through nuttx/irq.h - */ - -#ifndef __ARCH_ARM_INCLUDE_STM32F0L0G0_STM32G0_IRQ_H -#define __ARCH_ARM_INCLUDE_STM32F0L0G0_STM32G0_IRQ_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include -#include - -/**************************************************************************** - * Pre-processor Prototypes - ****************************************************************************/ - -/* IRQ numbers. The IRQ number corresponds vector number and hence map - * directly to bits in the NVIC. This does, however, waste several words of - * memory in the IRQ to handle mapping tables. - * - * Processor Exceptions (vectors 0-15). These common definitions can be - * found in nuttx/arch/arm/include/stm32f0l0g0/irq.h - */ - -#define STM32_IRQ_WWDG (STM32_IRQ_EXTINT + 0) /* 0: Window Watchdog interrupt */ -#define STM32_IRQ_PVM (STM32_IRQ_EXTINT + 1) /* 1: VDDIO2 monitor interrupt */ -#define STM32_IRQ_RTC (STM32_IRQ_EXTINT + 2) /* 2: RTC */ -#define STM32_IRQ_FLASH (STM32_IRQ_EXTINT + 3) /* 3: Flash */ -#define STM32_IRQ_RCC (STM32_IRQ_EXTINT + 4) /* 4: RCC */ -#define STM32_IRQ_EXTI0_1 (STM32_IRQ_EXTINT + 5) /* 5: EXTI0_1 */ -#define STM32_IRQ_EXTI2_3 (STM32_IRQ_EXTINT + 6) /* 6: EXTI2_3 */ -#define STM32_IRQ_EXTI4_15 (STM32_IRQ_EXTINT + 7) /* 7: EXTI4_15 */ -#define STM32_IRQ_USB (STM32_IRQ_EXTINT + 8) /* 8: USB global interrupt */ -#define STM32_IRQ_DMA1CH1 (STM32_IRQ_EXTINT + 9) /* 9: DMA1_CH1 */ -#define STM32_IRQ_DMA1CH2 (STM32_IRQ_EXTINT + 10) /* 10: DMA1_CH2 */ -#define STM32_IRQ_DMA1CH3 (STM32_IRQ_EXTINT + 10) /* 10: DMA1_CH3 */ -#define STM32_IRQ_DMA1CH4 (STM32_IRQ_EXTINT + 11) /* 11: DMA1_CH4 */ -#define STM32_IRQ_DMA1CH5 (STM32_IRQ_EXTINT + 11) /* 11: DMA1_CH5 */ -#define STM32_IRQ_DMA1CH6 (STM32_IRQ_EXTINT + 11) /* 11: DMA1_CH6 */ -#define STM32_IRQ_DMA1CH7 (STM32_IRQ_EXTINT + 11) /* 11: DMA1_CH7 */ -#define STM32_IRQ_DMAMUX (STM32_IRQ_EXTINT + 11) /* 11: DMAMUX */ -#define STM32_IRQ_ADC (STM32_IRQ_EXTINT + 12) /* 12: ADC */ -#define STM32_IRQ_TIM1_BRK (STM32_IRQ_EXTINT + 13) /* 13: TIM1_BRK_UP_TRG_COM */ -#define STM32_IRQ_TIM1_CC (STM32_IRQ_EXTINT + 14) /* 14: TIM1_CC */ -#define STM32_IRQ_TIM2 (STM32_IRQ_EXTINT + 15) /* 15: TIM2 */ -#define STM32_IRQ_TIM3 (STM32_IRQ_EXTINT + 16) /* 16: TIM3 */ -#define STM32_IRQ_TIM6 (STM32_IRQ_EXTINT + 17) /* 17: TIM6 */ -#define STM32_IRQ_TIM14 (STM32_IRQ_EXTINT + 19) /* 19: TIM14 */ -#define STM32_IRQ_TIM15 (STM32_IRQ_EXTINT + 20) /* 20: TIM15 */ -#define STM32_IRQ_TIM16 (STM32_IRQ_EXTINT + 21) /* 21: TIM16 */ -#define STM32_IRQ_TIM17 (STM32_IRQ_EXTINT + 22) /* 22: TIM17 */ -#define STM32_IRQ_I2C1 (STM32_IRQ_EXTINT + 23) /* 23: I2C1 */ -#define STM32_IRQ_I2C2 (STM32_IRQ_EXTINT + 24) /* 24: I2C2 */ -#define STM32_IRQ_SPI1 (STM32_IRQ_EXTINT + 25) /* 25: SPI1 */ -#define STM32_IRQ_SPI2 (STM32_IRQ_EXTINT + 26) /* 26: SPI2 */ -#define STM32_IRQ_USART1 (STM32_IRQ_EXTINT + 27) /* 27: USART1 */ -#define STM32_IRQ_USART2 (STM32_IRQ_EXTINT + 28) /* 28: USART2 */ -#define STM32_IRQ_USART3 (STM32_IRQ_EXTINT + 29) /* 29: USART3 */ -#define STM32_IRQ_USART4 (STM32_IRQ_EXTINT + 29) /* 29: USART4 */ -#define STM32_IRQ_FDCAN1_0 (STM32_IRQ_EXTINT + 30) /* 30: FDCAN global interrupt 0 */ -#define STM32_IRQ_FDCAN1_1 (STM32_IRQ_EXTINT + 31) /* 31: FDCAN global interrupt 1 */ - -#define STM32_IRQ_NEXTINTS (32) - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -#ifndef __ASSEMBLY__ -#ifdef __cplusplus -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -#undef EXTERN -#ifdef __cplusplus -} -#endif -#endif - -#endif /* __ARCH_ARM_INCLUDE_STM32F0L0G0_STM32G0_IRQ_H */ diff --git a/arch/arm/include/stm32f0l0g0/stm32f0_irq.h b/arch/arm/include/stm32f0l0g0/stm32f0_irq.h deleted file mode 100644 index 1d214b1569c1f..0000000000000 --- a/arch/arm/include/stm32f0l0g0/stm32f0_irq.h +++ /dev/null @@ -1,131 +0,0 @@ -/**************************************************************************** - * arch/arm/include/stm32f0l0g0/stm32f0_irq.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* This file should never be included directly but, rather, only indirectly - * through nuttx/irq.h - */ - -#ifndef __ARCH_ARM_INCLUDE_STM32F0L0G0_STM32F0_IRQ_H -#define __ARCH_ARM_INCLUDE_STM32F0L0G0_STM32F0_IRQ_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include -#include - -/**************************************************************************** - * Pre-processor Prototypes - ****************************************************************************/ - -/* IRQ numbers. The IRQ number corresponds vector number and hence map - * directly to bits in the NVIC. This does, however, waste several words of - * memory in the IRQ to handle mapping tables. - * - * Processor Exceptions (vectors 0-15). These common definitions can be - * found in nuttx/arch/arm/include/stm32f0l0g0/irq.h - */ - -#define STM32_IRQ_WWDG (STM32_IRQ_EXTINT + 0) /* 0: WWDG */ -#define STM32_IRQ_PVD_VDDIO2 (STM32_IRQ_EXTINT + 1) /* 1: PVD_VDDIO2 */ -#define STM32_IRQ_RTC (STM32_IRQ_EXTINT + 2) /* 2: RTC */ -#define STM32_IRQ_FLASH (STM32_IRQ_EXTINT + 3) /* 3: FLASH */ -#define STM32_IRQ_RCC_CRS (STM32_IRQ_EXTINT + 4) /* 4: RCC and CRS */ -#define STM32_IRQ_EXTI0_1 (STM32_IRQ_EXTINT + 5) /* 5: EXTI0_1 */ -#define STM32_IRQ_EXTI2_3 (STM32_IRQ_EXTINT + 6) /* 6: EXTI2_3 */ -#define STM32_IRQ_EXTI4_15 (STM32_IRQ_EXTINT + 7) /* 7: EXTI4_15 */ -#define STM32_IRQ_TSC (STM32_IRQ_EXTINT + 8) /* 8: TSC */ -#define STM32_IRQ_DMA1CH1 (STM32_IRQ_EXTINT + 9) /* 9: DMA1_CH1 */ -#define STM32_IRQ_DMA1CH2 (STM32_IRQ_EXTINT + 10) /* 10: DMA1_CH2 */ -#define STM32_IRQ_DMA1CH3 (STM32_IRQ_EXTINT + 10) /* 10: DMA1_CH3 */ -#define STM32_IRQ_DMA2CH1 (STM32_IRQ_EXTINT + 10) /* 10: DMA2_CH1 */ -#define STM32_IRQ_DMA2CH2 (STM32_IRQ_EXTINT + 10) /* 10: DMA2_CH2 */ -#define STM32_IRQ_DMA1CH4 (STM32_IRQ_EXTINT + 11) /* 11: DMA1_CH4 */ -#define STM32_IRQ_DMA1CH5 (STM32_IRQ_EXTINT + 11) /* 11: DMA1_CH5 */ -#define STM32_IRQ_DMA1CH6 (STM32_IRQ_EXTINT + 11) /* 11: DMA1_CH6 */ -#define STM32_IRQ_DMA1CH7 (STM32_IRQ_EXTINT + 11) /* 11: DMA1_CH7 */ -#define STM32_IRQ_DMA2CH3 (STM32_IRQ_EXTINT + 11) /* 11: DMA2_CH3 */ -#define STM32_IRQ_DMA2CH4 (STM32_IRQ_EXTINT + 11) /* 11: DMA2_CH4 */ -#define STM32_IRQ_DMA2CH5 (STM32_IRQ_EXTINT + 11) /* 11: DMA2_CH5 */ -#define STM32_IRQ_ADC (STM32_IRQ_EXTINT + 12) /* 12: ADC */ -#define STM32_IRQ_COMP (STM32_IRQ_EXTINT + 12) /* 12: COMP */ -#define STM32_IRQ_TIM1_BRK (STM32_IRQ_EXTINT + 13) /* 13: TIM1_BRK_UP_TRG_COM */ -#define STM32_IRQ_TIM1_CC (STM32_IRQ_EXTINT + 14) /* 14: TIM1_CC */ -#define STM32_IRQ_TIM2 (STM32_IRQ_EXTINT + 15) /* 15: TIM2 */ -#define STM32_IRQ_TIM3 (STM32_IRQ_EXTINT + 16) /* 16: TIM3 */ -#define STM32_IRQ_TIM6 (STM32_IRQ_EXTINT + 17) /* 17: TIM6 */ -#define STM32_IRQ_DAC (STM32_IRQ_EXTINT + 17) /* 17: DAC */ -#define STM32_IRQ_TIM7 (STM32_IRQ_EXTINT + 18) /* 18: TIM7 */ -#define STM32_IRQ_TIM14 (STM32_IRQ_EXTINT + 19) /* 19: TIM14 */ -#define STM32_IRQ_TIM15 (STM32_IRQ_EXTINT + 20) /* 20: TIM15 */ -#define STM32_IRQ_TIM16 (STM32_IRQ_EXTINT + 21) /* 21: TIM16 */ -#define STM32_IRQ_TIM17 (STM32_IRQ_EXTINT + 22) /* 22: TIM17 */ -#define STM32_IRQ_I2C1 (STM32_IRQ_EXTINT + 23) /* 23: I2C1 */ -#define STM32_IRQ_I2C2 (STM32_IRQ_EXTINT + 24) /* 24: I2C2 */ -#define STM32_IRQ_SPI1 (STM32_IRQ_EXTINT + 25) /* 25: SPI1 */ -#define STM32_IRQ_SPI2 (STM32_IRQ_EXTINT + 26) /* 26: SPI2 */ -#define STM32_IRQ_USART1 (STM32_IRQ_EXTINT + 27) /* 27: USART1 */ -#define STM32_IRQ_USART2 (STM32_IRQ_EXTINT + 28) /* 28: USART2 */ -#define STM32_IRQ_USART3 (STM32_IRQ_EXTINT + 29) /* 29: USART3 */ -#define STM32_IRQ_USART4 (STM32_IRQ_EXTINT + 29) /* 29: USART4 */ -#define STM32_IRQ_USART5 (STM32_IRQ_EXTINT + 29) /* 29: USART5 */ -#define STM32_IRQ_USART6 (STM32_IRQ_EXTINT + 29) /* 29: USART6 */ -#define STM32_IRQ_USART7 (STM32_IRQ_EXTINT + 29) /* 29: USART7 */ -#define STM32_IRQ_USART8 (STM32_IRQ_EXTINT + 29) /* 29: USART8 */ -#define STM32_IRQ_CEC (STM32_IRQ_EXTINT + 30) /* 30: HDMI CEC */ -#define STM32_IRQ_CAN (STM32_IRQ_EXTINT + 30) /* 30: HDMI CAN */ -#define STM32_IRQ_USB (STM32_IRQ_EXTINT + 31) /* 31: USB */ - -#define STM32_IRQ_NEXTINTS (32) /* 32 external interrupts */ - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -#ifndef __ASSEMBLY__ -typedef void (*vic_vector_t)(uint32_t *regs); - -/**************************************************************************** - * Inline functions - ****************************************************************************/ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -#ifdef __cplusplus -extern "C" -{ -#endif - -#ifdef __cplusplus -} -#endif -#endif /* __ASSEMBLY__ */ - -#endif /* __ARCH_ARM_INCLUDE_STM32F0L0G0_STM32F0_IRQ_H */ diff --git a/arch/arm/include/stm32f0l0g0/stm32g0_irq.h b/arch/arm/include/stm32f0l0g0/stm32g0_irq.h deleted file mode 100644 index ef718cff08533..0000000000000 --- a/arch/arm/include/stm32f0l0g0/stm32g0_irq.h +++ /dev/null @@ -1,195 +0,0 @@ -/**************************************************************************** - * arch/arm/include/stm32f0l0g0/stm32g0_irq.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* This file should never be included directly but, rather, only indirectly - * through nuttx/irq.h - */ - -#ifndef __ARCH_ARM_INCLUDE_STM32F0L0G0_STM32G0_IRQ_H -#define __ARCH_ARM_INCLUDE_STM32F0L0G0_STM32G0_IRQ_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include -#include - -/**************************************************************************** - * Pre-processor Prototypes - ****************************************************************************/ - -/* IRQ numbers. The IRQ number corresponds vector number and hence map - * directly to bits in the NVIC. This does, however, waste several words of - * memory in the IRQ to handle mapping tables. - * - * Processor Exceptions (vectors 0-15). These common definitions can be - * found in nuttx/arch/arm/include/stm32f0l0g0/irq.h - */ - -#define STM32_IRQ_WWDG (STM32_IRQ_EXTINT + 0) /* 0: Window Watchdog interrupt */ - -#if defined(CONFIG_ARCH_CHIP_STM32G070KB) || defined(CONFIG_ARCH_CHIP_STM32G070CB) || \ - defined(CONFIG_ARCH_CHIP_STM32G070RB) -# define STM32_IRQ_RESERVED1 (STM32_IRQ_EXTINT + 1) /* 1: Reserved */ -#else -# define STM32_IRQ_PVD (STM32_IRQ_EXTINT + 1) /* 1: PVD through EXTI Line detection interrupt */ -#endif - -#define STM32_IRQ_RTC (STM32_IRQ_EXTINT + 2) /* 2: RTC */ -#define STM32_IRQ_FLASH (STM32_IRQ_EXTINT + 3) /* 3: Flash */ -#define STM32_IRQ_RCC (STM32_IRQ_EXTINT + 4) /* 4: RCC */ -#define STM32_IRQ_EXTI0_1 (STM32_IRQ_EXTINT + 5) /* 5: EXTI0_1 */ -#define STM32_IRQ_EXTI2_3 (STM32_IRQ_EXTINT + 6) /* 6: EXTI2_3 */ -#define STM32_IRQ_EXTI4_15 (STM32_IRQ_EXTINT + 7) /* 7: EXTI4_15 */ - -#if defined(CONFIG_ARCH_CHIP_STM32G070KB) || defined(CONFIG_ARCH_CHIP_STM32G070CB) || \ - defined(CONFIG_ARCH_CHIP_STM32G070RB) -# define STM32_IRQ_RESERVED8 (STM32_IRQ_EXTINT + 8) /* 8: Reserved */ -#else -# define STM32_IRQ_UCPD12 (STM32_IRQ_EXTINT + 8) /* 8: UCPD1_2 */ -# define STM32_IRQ_EXTI32_33 (STM32_IRQ_EXTINT + 8) /* 8: EXTI_32_33 */ -#endif - -#define STM32_IRQ_DMA1CH1 (STM32_IRQ_EXTINT + 9) /* 9: DMA1_CH1 */ -#define STM32_IRQ_DMA1CH2 (STM32_IRQ_EXTINT + 10) /* 10: DMA1_CH2 */ -#define STM32_IRQ_DMA1CH3 (STM32_IRQ_EXTINT + 10) /* 10: DMA1_CH3 */ -#define STM32_IRQ_DMA1CH4 (STM32_IRQ_EXTINT + 11) /* 11: DMA1_CH4 */ -#define STM32_IRQ_DMA1CH5 (STM32_IRQ_EXTINT + 11) /* 11: DMA1_CH5 */ -#define STM32_IRQ_DMA1CH6 (STM32_IRQ_EXTINT + 11) /* 11: DMA1_CH6 */ -#define STM32_IRQ_DMA1CH7 (STM32_IRQ_EXTINT + 11) /* 11: DMA1_CH7 */ -#define STM32_IRQ_DMAMUX (STM32_IRQ_EXTINT + 11) /* 11: DMAMUX */ - -#if defined(CONFIG_STM32F0L0G0_STM32G0BX) || \ - defined(CONFIG_STM32F0L0G0_STM32G0C1) -# define STM32_IRQ_DMA2CH1 (STM32_IRQ_EXTINT + 11) /* 11: DMA2_CH1 */ -# define STM32_IRQ_DMA2CH2 (STM32_IRQ_EXTINT + 11) /* 11: DMA2_CH2 */ -# define STM32_IRQ_DMA2CH3 (STM32_IRQ_EXTINT + 11) /* 11: DMA2_CH3 */ -# define STM32_IRQ_DMA2CH4 (STM32_IRQ_EXTINT + 11) /* 11: DMA2_CH4 */ -# define STM32_IRQ_DMA2CH5 (STM32_IRQ_EXTINT + 11) /* 11: DMA2_CH5 */ -#endif - -#define STM32_IRQ_ADC (STM32_IRQ_EXTINT + 12) /* 12: ADC */ -#define STM32_IRQ_EXTI17_18 (STM32_IRQ_EXTINT + 12) /* 12: EXTI_17_18 */ - -#if defined(CONFIG_ARCH_CHIP_STM32G070KB) || defined(CONFIG_ARCH_CHIP_STM32G070CB) || \ - defined(CONFIG_ARCH_CHIP_STM32G070RB) -/* No STM32_IRQ_COMP */ - -#else -# define STM32_IRQ_COMP (STM32_IRQ_EXTINT + 12) /* 12: COMP */ -#endif - -#define STM32_IRQ_TIM1_BRK (STM32_IRQ_EXTINT + 13) /* 13: TIM1_BRK_UP_TRG_COM */ -#define STM32_IRQ_TIM1_CC (STM32_IRQ_EXTINT + 14) /* 14: TIM1_CC */ - -#if defined(CONFIG_ARCH_CHIP_STM32G070KB) || defined(CONFIG_ARCH_CHIP_STM32G070CB) || \ - defined(CONFIG_ARCH_CHIP_STM32G070RB) -# define STM32_IRQ_RESERVED15 (STM32_IRQ_EXTINT + 15) /* 15: Reserved */ -#else -# define STM32_IRQ_TIM2 (STM32_IRQ_EXTINT + 15) /* 15: TIM2 */ -#endif - -#define STM32_IRQ_TIM3 (STM32_IRQ_EXTINT + 16) /* 16: TIM3 */ -#define STM32_IRQ_TIM6 (STM32_IRQ_EXTINT + 17) /* 17: TIM6 */ - -#if defined(CONFIG_ARCH_CHIP_STM32G070KB) || defined(CONFIG_ARCH_CHIP_STM32G070CB) || \ - defined(CONFIG_ARCH_CHIP_STM32G070RB) -/* No STM32_IRQ_DAC */ - -/* No STM32_IRQ_LPTIM1 */ - -#else -# define STM32_IRQ_DAC (STM32_IRQ_EXTINT + 17) /* 17: DAC */ -# define STM32_IRQ_LPTIM1 (STM32_IRQ_EXTINT + 17) /* 17: LPTIM1 */ -#endif - -#define STM32_IRQ_TIM7 (STM32_IRQ_EXTINT + 18) /* 18: TIM7 */ - -#if defined(CONFIG_ARCH_CHIP_STM32G070KB) || defined(CONFIG_ARCH_CHIP_STM32G070CB) || \ - defined(CONFIG_ARCH_CHIP_STM32G070RB) -/* No STM32_IRQ_LPTIM2 */ - -#else -# define STM32_IRQ_LPTIM2 (STM32_IRQ_EXTINT + 18) /* 18: LPTIM2 */ -#endif - -#define STM32_IRQ_TIM14 (STM32_IRQ_EXTINT + 19) /* 19: TIM14 */ -#define STM32_IRQ_TIM15 (STM32_IRQ_EXTINT + 20) /* 20: TIM15 */ -#define STM32_IRQ_TIM16 (STM32_IRQ_EXTINT + 21) /* 21: TIM16 */ -#define STM32_IRQ_TIM17 (STM32_IRQ_EXTINT + 22) /* 22: TIM17 */ -#define STM32_IRQ_I2C1 (STM32_IRQ_EXTINT + 23) /* 23: I2C1 */ -#define STM32_IRQ_EXTI23 (STM32_IRQ_EXTINT + 23) /* 23: EXTI_23 */ -#define STM32_IRQ_I2C2 (STM32_IRQ_EXTINT + 24) /* 24: I2C2 */ -#define STM32_IRQ_SPI1 (STM32_IRQ_EXTINT + 25) /* 25: SPI1 */ -#define STM32_IRQ_SPI2 (STM32_IRQ_EXTINT + 26) /* 26: SPI2 */ -#define STM32_IRQ_USART1 (STM32_IRQ_EXTINT + 27) /* 27: USART1 */ -#define STM32_IRQ_EXTI25 (STM32_IRQ_EXTINT + 27) /* 27: EXTI_25 */ -#define STM32_IRQ_USART2 (STM32_IRQ_EXTINT + 28) /* 28: USART2 */ -#define STM32_IRQ_EXTI26 (STM32_IRQ_EXTINT + 28) /* 28: EXTI_26 */ -#define STM32_IRQ_USART3 (STM32_IRQ_EXTINT + 29) /* 29: USART3 */ -#define STM32_IRQ_USART4 (STM32_IRQ_EXTINT + 29) /* 29: USART4 */ -#define STM32_IRQ_LPUART1 (STM32_IRQ_EXTINT + 29) /* 29: LPUART1 */ -#define STM32_IRQ_EXTI28 (STM32_IRQ_EXTINT + 29) /* 29: EXTI_28 */ - -#if defined(CONFIG_ARCH_CHIP_STM32G070KB) || defined(CONFIG_ARCH_CHIP_STM32G070CB) || \ - defined(CONFIG_ARCH_CHIP_STM32G070RB) -# define STM32_IRQ_RESERVED30 (STM32_IRQ_EXTINT + 30) /* 30: Reserved */ -# define STM32_IRQ_RESERVED31 (STM32_IRQ_EXTINT + 31) /* 31: Reserved */ -#else -# define STM32_IRQ_CEC (STM32_IRQ_EXTINT + 30) /* 30: HDMI CEC */ -# define STM32_IRQ_EXTI27 (STM32_IRQ_EXTINT + 30) /* 30: EXTI_27 */ -# define STM32_IRQ_AES (STM32_IRQ_EXTINT + 31) /* 31: AES */ -# define STM32_IRQ_RNG (STM32_IRQ_EXTINT + 31) /* 31: RNG */ -#endif - -#define STM32_IRQ_NEXTINTS (32) - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -#ifndef __ASSEMBLY__ -#ifdef __cplusplus -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -#undef EXTERN -#ifdef __cplusplus -} -#endif -#endif - -#endif /* __ARCH_ARM_INCLUDE_STM32F0L0G0_STM32G0_IRQ_H */ diff --git a/arch/arm/include/stm32f0l0g0/stm32l0_irq.h b/arch/arm/include/stm32f0l0g0/stm32l0_irq.h deleted file mode 100644 index 166815ea7fa98..0000000000000 --- a/arch/arm/include/stm32f0l0g0/stm32l0_irq.h +++ /dev/null @@ -1,122 +0,0 @@ -/**************************************************************************** - * arch/arm/include/stm32f0l0g0/stm32l0_irq.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* This file should never be included directly but, rather, - * only indirectly through nuttx/irq.h - */ - -#ifndef __ARCH_ARM_INCLUDE_STM32F0L0G0_STM32L0_IRQ_H -#define __ARCH_ARM_INCLUDE_STM32F0L0G0_STM32L0_IRQ_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include -#include - -/**************************************************************************** - * Pre-processor Prototypes - ****************************************************************************/ - -/* IRQ numbers. - * The IRQ number corresponds vector number and hence map directly to - * bits in the NVIC. This does, however, waste several words of memory in - * the IRQ to handle mapping tables. - * - * Processor Exceptions (vectors 0-15). These common definitions - * can be found in nuttx/arch/arm/include/stm32f0l0g0/irq.h - */ - -#define STM32_IRQ_WWDG (STM32_IRQ_EXTINT + 0) /* 0: Window Watchdog interrupt */ -#define STM32_IRQ_PVD (STM32_IRQ_EXTINT + 1) /* 1: PVD through EXTI Line detection interrupt */ -#define STM32_IRQ_RTC (STM32_IRQ_EXTINT + 2) /* 2: RTC global interrupt */ -#define STM32_IRQ_FLASH (STM32_IRQ_EXTINT + 3) /* 3: Flash global interrupt */ -#define STM32_IRQ_RCC_CRS (STM32_IRQ_EXTINT + 4) /* 4: RCC and CRS global interrupt */ -#define STM32_IRQ_EXTI0_1 (STM32_IRQ_EXTINT + 5) /* 5: EXTI Line 0-1 interrupt */ -#define STM32_IRQ_EXTI2_3 (STM32_IRQ_EXTINT + 6) /* 6: EXTI Line 2-3 interrupt */ -#define STM32_IRQ_EXTI4_15 (STM32_IRQ_EXTINT + 7) /* 7: EXTI Line 4-15 interrupt */ -#define STM32_IRQ_TSC (STM32_IRQ_EXTINT + 8) /* 8: TSC global interrupt */ -#define STM32_IRQ_DMA1CH1 (STM32_IRQ_EXTINT + 9) /* 9: DMA1 channel 1 global interrupt */ -#define STM32_IRQ_DMA1CH2 (STM32_IRQ_EXTINT + 10) /* 10: DMA1 channel 2 global interrupt */ -#define STM32_IRQ_DMA1CH3 (STM32_IRQ_EXTINT + 10) /* 10: DMA1 channel 3 global interrupt */ -#define STM32_IRQ_DMA1CH4 (STM32_IRQ_EXTINT + 11) /* 11: DMA1 channel 4 global interrupt */ -#define STM32_IRQ_DMA1CH5 (STM32_IRQ_EXTINT + 11) /* 11: DMA1 channel 5 global interrupt */ -#define STM32_IRQ_DMA1CH6 (STM32_IRQ_EXTINT + 11) /* 11: DMA1 channel 6 global interrupt */ -#define STM32_IRQ_DMA1CH7 (STM32_IRQ_EXTINT + 11) /* 11: DMA1 channel 7 global interrupt */ -#define STM32_IRQ_ADC (STM32_IRQ_EXTINT + 12) /* 12: ADC global interrupt */ -#define STM32_IRQ_COMP (STM32_IRQ_EXTINT + 12) /* 12: COMP global interrupt */ -#define STM32_IRQ_LPTIM1 (STM32_IRQ_EXTINT + 13) /* 13: LPTIM1 global interrupt */ -#define STM32_IRQ_USART4 (STM32_IRQ_EXTINT + 14) /* 14: USART4 global interrupt */ -#define STM32_IRQ_USART5 (STM32_IRQ_EXTINT + 14) /* 14: USART5 global interrupt */ -#define STM32_IRQ_TIM2 (STM32_IRQ_EXTINT + 15) /* 15: TIM2 global interrupt */ -#define STM32_IRQ_TIM3 (STM32_IRQ_EXTINT + 16) /* 16: TIM3 global interrupt */ -#define STM32_IRQ_TIM6 (STM32_IRQ_EXTINT + 17) /* 17: TIM6 global interrupt */ -#define STM32_IRQ_DAC1 (STM32_IRQ_EXTINT + 17) /* 17: DAC1 global interrupts */ -#define STM32_IRQ_TIM7 (STM32_IRQ_EXTINT + 18) /* 18: TIM7 global interrupt */ -#define STM32_IRQ_RESERVED18 (STM32_IRQ_EXTINT + 18) /* 19: Reserved */ -#define STM32_IRQ_TIM21 (STM32_IRQ_EXTINT + 20) /* 20: TIM21 global interrupt */ -#define STM32_IRQ_I2C3 (STM32_IRQ_EXTINT + 21) /* 21: I2C3 global interrupt */ -#define STM32_IRQ_TIM22 (STM32_IRQ_EXTINT + 22) /* 22: TIM22 global interrupt */ -#define STM32_IRQ_I2C1 (STM32_IRQ_EXTINT + 23) /* 23: I2C1 global interrupt */ -#define STM32_IRQ_I2C2 (STM32_IRQ_EXTINT + 24) /* 24: I2C2 global interrupt */ -#define STM32_IRQ_SPI1 (STM32_IRQ_EXTINT + 25) /* 25: SPI1 global interrupt */ -#define STM32_IRQ_SPI2 (STM32_IRQ_EXTINT + 26) /* 26: SPI2 global interrupt */ -#define STM32_IRQ_USART1 (STM32_IRQ_EXTINT + 27) /* 27: USART1 global interrupt */ -#define STM32_IRQ_USART2 (STM32_IRQ_EXTINT + 28) /* 28: USART2 global interrupt */ -#define STM32_IRQ_LPUART1 (STM32_IRQ_EXTINT + 29) /* 29: LPUART1 global interrupt */ -#define STM32_IRQ_AES (STM32_IRQ_EXTINT + 29) /* 29: AES global interrupt */ -#define STM32_IRQ_RNG (STM32_IRQ_EXTINT + 29) /* 29: RNG global interrupt */ -#define STM32_IRQ_LCD (STM32_IRQ_EXTINT + 30) /* 30: LCD global interrupt */ -#define STM32_IRQ_USB (STM32_IRQ_EXTINT + 31) /* 31: USB global interrupt */ - -#define STM32_IRQ_NEXTINTS (32) - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -#ifndef __ASSEMBLY__ -#ifdef __cplusplus -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Public Functions Prototypes - ****************************************************************************/ - -#undef EXTERN -#ifdef __cplusplus -} -#endif -#endif - -#endif /* __ARCH_ARM_INCLUDE_STM32F0L0G0_STM32L0_IRQ_H */ diff --git a/arch/arm/include/stm32f1/chip.h b/arch/arm/include/stm32f1/chip.h new file mode 100644 index 0000000000000..a216966d478ef --- /dev/null +++ b/arch/arm/include/stm32f1/chip.h @@ -0,0 +1,495 @@ +/**************************************************************************** + * arch/arm/include/stm32f1/chip.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_INCLUDE_STM32F1_CHIP_H +#define __ARCH_ARM_INCLUDE_STM32F1_CHIP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Prototypes + ****************************************************************************/ + +/* Get customizations for each supported chip and provide alternate function + * pin-mapping + * + * NOTE: Each GPIO pin may serve either for general purpose I/O or for a + * special alternate function (such as USART, CAN, USB, SDIO, etc.). That + * particular pin-mapping will depend on the package and STM32 family. If + * you are incorporating a new STM32 chip into NuttX, you will need to add + * the pin-mapping to a header file and to include that header file below. + * The chip-specific pin-mapping is defined in the chip datasheet. + */ + +#if defined(CONFIG_ARCH_CHIP_STM32F100C8) || defined(CONFIG_ARCH_CHIP_STM32F100CB) \ + || defined(CONFIG_ARCH_CHIP_STM32F100R8) || defined(CONFIG_ARCH_CHIP_STM32F100RB) +# define STM32_NFSMC 0 /* No FSMC */ +# define STM32_NATIM 1 /* One advanced timer TIM1 */ +# define STM32_NGTIM 3 /* 16-bit general timers TIM2-4 with DMA */ +# define STM32_NGTIMNDMA 0 /* No 16-bit general timers without DMA */ +# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 */ + +/* TODO: there are also 3 additional timers (15-17) + * that don't fit any existing category + */ + +# define STM32_NDMA 1 /* DMA1 */ +# define STM32_NSPI 2 /* SPI1-2 */ +# define STM32_NI2S 0 /* No I2S */ +# define STM32_NUSART 3 /* USART1-3 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 2 /* I2C1-2 */ +# define STM32_NCAN 0 /* No CAN */ +# define STM32_NSDIO 0 /* No SDIO */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 0 /* No USB OTG FS/HS */ +# define STM32_NGPIO 64 /* GPIOA-D */ +# define STM32_NADC 1 /* ADC1 */ +# define STM32_NDAC 2 /* DAC 1, 2 channels */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC1 */ +# define STM32_NETHERNET 0 /* No Ethernet */ +# define STM32_NRNG 0 /* No random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F100V8) || defined(CONFIG_ARCH_CHIP_STM32F100VB) +# define STM32_NFSMC 0 /* FSMC */ +# define STM32_NATIM 1 /* One advanced timer TIM1 */ +# define STM32_NGTIM 3 /* 16-bit general timers TIM2-4 with DMA */ +# define STM32_NGTIMNDMA 0 /* No 16-bit general timers without DMA */ +# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 */ + +/* TODO: there are also 3 additional timers (15-17) + * that don't fit any existing category + */ + +# define STM32_NDMA 1 /* DMA1 */ +# define STM32_NSPI 2 /* SPI1-2 */ +# define STM32_NI2S 0 /* No I2S */ +# define STM32_NUSART 3 /* USART1-3 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 2 /* I2C1-2 */ +# define STM32_NCAN 0 /* No CAN */ +# define STM32_NSDIO 0 /* No SDIO */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 0 /* No USB OTG FS/HS */ +# define STM32_NGPIO 80 /* GPIOA-E */ +# define STM32_NADC 1 /* ADC1 */ +# define STM32_NDAC 2 /* DAC 1, 2 channels */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC1 */ +# define STM32_NETHERNET 0 /* No Ethernet */ +# define STM32_NRNG 0 /* No random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + +/* STM32 F100 High-density value Line ***************************************/ + +#elif defined(CONFIG_ARCH_CHIP_STM32F100RC) || defined(CONFIG_ARCH_CHIP_STM32F100RD) \ + || defined(CONFIG_ARCH_CHIP_STM32F100RE) +# define STM32_NFSMC 0 /* FSMC */ +# define STM32_NATIM 1 /* One advanced timer TIM1 */ +# define STM32_NGTIM 4 /* 16-bit general timers TIM2-5 with DMA */ +# define STM32_NGTIMNDMA 0 /* No 16-bit general timers without DMA */ +# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 */ + +/* TODO: there are also 6 additional timers (12-17) + * that don't fit any existing category + */ + +# define STM32_NDMA 2 /* DMA1-2 */ +# define STM32_NSPI 3 /* SPI1-3 */ +# define STM32_NI2S 0 /* No I2S */ +# define STM32_NUSART 5 /* USART1-5 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 2 /* I2C1-2 */ +# define STM32_NCAN 0 /* No CAN */ +# define STM32_NSDIO 0 /* No SDIO */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 0 /* No USB OTG FS/HS */ +# define STM32_NGPIO 64 /* GPIOA-D */ +# define STM32_NADC 1 /* ADC1 */ +# define STM32_NDAC 2 /* DAC 1, 2 channels */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC1 */ +# define STM32_NETHERNET 0 /* No Ethernet */ +# define STM32_NRNG 0 /* No random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F100VC) || defined(CONFIG_ARCH_CHIP_STM32F100VD) \ + || defined(CONFIG_ARCH_CHIP_STM32F100VE) +# define STM32_NFSMC 1 /* FSMC */ +# define STM32_NATIM 1 /* One advanced timer TIM1 */ +# define STM32_NGTIM 4 /* 16-bit general timers TIM2-5 with DMA */ +# define STM32_NGTIMNDMA 0 /* No 16-bit general timers without DMA */ +# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 */ + +/* TODO: there are also 6 additional timers (12-17) + * that don't fit any existing category + */ + +# define STM32_NDMA 2 /* DMA1-2 */ +# define STM32_NSPI 3 /* SPI1-3 */ +# define STM32_NI2S 0 /* No I2S */ +# define STM32_NUSART 5 /* USART1-5 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 2 /* I2C1-2 */ +# define STM32_NCAN 0 /* No CAN */ +# define STM32_NSDIO 0 /* No SDIO */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 0 /* No USB OTG FS/HS */ +# define STM32_NGPIO 80 /* GPIOA-E */ +# define STM32_NADC 1 /* ADC1 */ +# define STM32_NDAC 2 /* DAC 1, 2 channels */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC1 */ +# define STM32_NETHERNET 0 /* No Ethernet */ +# define STM32_NRNG 0 /* No random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + +/* STM32 F102x8/102xB Medium Density USB Access Family **********************/ + +#elif defined(CONFIG_ARCH_CHIP_STM32F102CB) +# define STM32_NFSMC 1 /* FSMC */ +# define STM32_NATIM 0 /* No advanced timer TIM1 */ +# define STM32_NGTIM 3 /* 16-bit general timers TIM2-4 */ +# define STM32_NGTIMNDMA 0 /* No 16-bit general timers without DMA */ +# define STM32_NBTIM 0 /* No basic timers */ +# define STM32_NDMA 1 /* DMA */ +# define STM32_NSPI 2 /* SPI1-2 */ +# define STM32_NI2S 0 /* No I2S */ +# define STM32_NUSART 3 /* USART1-3 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 2 /* I2C1-2 */ +# define STM32_NCAN 0 /* No CAN */ +# define STM32_NSDIO 0 /* No SDIO */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 0 /* No USB OTG FS/HS */ +# define STM32_NGPIO 37 /* GPIOA-D */ +# define STM32_NADC 1 /* ADC1 */ +# define STM32_NDAC 0 /* No DAC */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC1 */ +# define STM32_NETHERNET 0 /* No ethernet */ +# define STM32_NRNG 0 /* No random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + +/* STM32 F103 Low Density Family ********************************************/ + +/* STM32F103C4 & STM32F103C6 */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F103C4) +# define STM32_NFSMC 0 /* FSMC */ +# define STM32_NATIM 1 /* One advanced timer TIM1 */ +# define STM32_NGTIM 2 /* General timers TIM2,3 */ +# define STM32_NGTIMNDMA 0 /* No 16-bit general timers without DMA */ +# define STM32_NBTIM 0 /* No basic timer */ +# define STM32_NDMA 1 /* DMA1 */ +# define STM32_NSPI 1 /* SPI1 */ +# define STM32_NI2S 0 /* No I2S */ +# define STM32_NUSART 2 /* USART1-2 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 1 /* I2C1 */ +# define STM32_NCAN 1 /* bxCAN1 */ +# define STM32_NSDIO 0 /* No SDIO */ +# define STM32_NUSBOTG 0 /* No USB OTG FS/HS */ +# define STM32_NGPIO 37 /* GPIOA-C */ +# define STM32_NADC 2 /* ADC1-2 */ +# define STM32_NDAC 0 /* No DAC */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NETHERNET 0 /* No Ethernet */ +# define STM32_NRNG 0 /* No random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + +/* STM32 F103 Medium Density Performance Line *******************************/ + +#elif defined(CONFIG_ARCH_CHIP_STM32F103T8) || defined(CONFIG_ARCH_CHIP_STM32F103TB) +# define STM32_NFSMC 0 /* No FSMC */ +# define STM32_NATIM 1 /* One advanced timer TIM1 */ +# define STM32_NGTIM 3 /* General timers TIM2-4 */ +# define STM32_NGTIMNDMA 0 /* No 16-bit general timers without DMA */ +# define STM32_NBTIM 0 /* No basic timers */ +# define STM32_NDMA 1 /* DMA1, 7 channels */ +# define STM32_NSPI 1 /* SPI1 */ +# define STM32_NI2S 0 /* No I2S */ +# define STM32_NUSART 2 /* USART1-2 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 1 /* I2C1 */ +# define STM32_NCAN 1 /* bxCAN1 */ +# define STM32_NSDIO 0 /* No SDIO */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 0 /* No USB OTG FS/HS */ +# define STM32_NGPIO 26 /* GPIOA-E */ +# define STM32_NADC 2 /* ADC1-2 */ +# define STM32_NDAC 0 /* No DAC */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NETHERNET 0 /* No Ethernet */ +# define STM32_NRNG 0 /* No random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F103C8) || defined(CONFIG_ARCH_CHIP_STM32F103CB) +# define STM32_NFSMC 0 /* No FSMC */ +# define STM32_NATIM 1 /* One advanced timer TIM1 */ +# define STM32_NGTIM 3 /* General timers TIM2-4 */ +# define STM32_NGTIMNDMA 0 /* No 16-bit general timers without DMA */ +# define STM32_NBTIM 0 /* No basic timers */ +# define STM32_NDMA 1 /* DMA1, 7 channels */ +# define STM32_NSPI 2 /* SPI1-2 */ +# define STM32_NI2S 0 /* No I2S */ +# define STM32_NUSART 3 /* USART1-3 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 2 /* I2C1-2 */ +# define STM32_NCAN 1 /* bxCAN1 */ +# define STM32_NSDIO 0 /* No SDIO */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 0 /* No USB OTG FS/HS */ +# define STM32_NGPIO 37 /* GPIOA-C */ +# define STM32_NADC 2 /* ADC1-2 */ +# define STM32_NDAC 0 /* No DAC */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NETHERNET 0 /* No Ethernet */ +# define STM32_NRNG 0 /* No random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F103R8) || defined(CONFIG_ARCH_CHIP_STM32F103RB) +# define STM32_NFSMC 0 /* No FSMC */ +# define STM32_NATIM 1 /* One advanced timer TIM1 */ +# define STM32_NGTIM 3 /* General timers TIM2-4 */ +# define STM32_NGTIMNDMA 0 /* No 16-bit general timers without DMA */ +# define STM32_NBTIM 0 /* No basic timers */ +# define STM32_NDMA 1 /* DMA1, 7 channels */ +# define STM32_NSPI 2 /* SPI1-2 */ +# define STM32_NI2S 0 /* No I2S */ +# define STM32_NUSART 3 /* USART1-3 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 2 /* I2C1-2 */ +# define STM32_NCAN 1 /* bxCAN1 */ +# define STM32_NSDIO 0 /* No SDIO */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 0 /* No USB OTG FS/HS */ +# define STM32_NGPIO 51 /* GPIOA-E */ +# define STM32_NADC 2 /* ADC1-2 */ +# define STM32_NDAC 0 /* No DAC */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NETHERNET 0 /* No Ethernet */ +# define STM32_NRNG 0 /* No random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + +/* STM32 F103 High Density Family *******************************************/ + +/* STM32F103RC, STM32F103RD, and STM32F103RE are all provided in 64 pin + * packages and differ only in the available FLASH and SRAM. + */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F103RC) || defined(CONFIG_ARCH_CHIP_STM32F103RD) || \ + defined(CONFIG_ARCH_CHIP_STM32F103RE) || defined(CONFIG_ARCH_CHIP_STM32F103RG) +# define STM32_NFSMC 1 /* FSMC */ +# define STM32_NATIM 2 /* Two advanced timers TIM1 and TIM8 */ +# define STM32_NGTIM 4 /* 16-bit general timers TIM2-5 with DMA */ +# define STM32_NGTIMNDMA 0 /* No 16-bit general timers without DMA */ +# define STM32_NBTIM 2 /* Two basic timers TIM6 and TIM7 */ +# define STM32_NDMA 2 /* DMA1-2 */ +# define STM32_NSPI 3 /* SPI1-3 */ +# define STM32_NI2S 0 /* No I2S (?) */ +# define STM32_NUSART 5 /* USART1-5 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 2 /* I2C1-2 */ +# define STM32_NCAN 1 /* CAN1 */ +# define STM32_NSDIO 1 /* SDIO */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 0 /* No USB OTG FS/HS */ +# define STM32_NGPIO 51 /* GPIOA-D */ +# define STM32_NADC 2 /* ADC1-2 */ +# define STM32_NDAC 2 /* DAC1, 2 channels */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NETHERNET 0 /* No Ethernet */ +# define STM32_NRNG 0 /* No random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + +/* STM32F103VC, STM32F103VD, and STM32F103VE are all provided in 100 pin + * packages and differ only in the available FLASH and SRAM. + */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F103VC) || defined(CONFIG_ARCH_CHIP_STM32F103VE) +# define STM32_NFSMC 1 /* FSMC */ +# define STM32_NATIM 2 /* Two advanced timers TIM1 and TIM8 */ +# define STM32_NGTIM 4 /* General timers TIM2-5 */ +# define STM32_NGTIMNDMA 0 /* No 16-bit general timers without DMA */ +# define STM32_NBTIM 2 /* Two basic timers TIM6 and TIM7 */ +# define STM32_NDMA 2 /* DMA1-2 */ +# define STM32_NSPI 3 /* SPI1-3 */ +# define STM32_NI2S 0 /* No I2S (?) */ +# define STM32_NUSART 5 /* USART1-5 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 2 /* I2C1-2 */ +# define STM32_NCAN 1 /* bxCAN1 */ +# define STM32_NSDIO 1 /* SDIO */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 0 /* No USB OTG FS/HS */ +# define STM32_NGPIO 80 /* GPIOA-E */ +# define STM32_NADC 3 /* ADC1-3 */ +# define STM32_NDAC 2 /* DAC1, 2 channels */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NETHERNET 0 /* No Ethernet */ +# define STM32_NRNG 0 /* No random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + +/* STM32F103ZC, STM32F103ZD, and STM32F103ZE are all provided in 144 pin + * packages and differ only in the available FLASH and SRAM. + */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F103ZE) +# define STM32_NFSMC 1 /* FSMC */ +# define STM32_NATIM 1 /* One advanced timer TIM1 */ +# define STM32_NGTIM 4 /* 16-bit general timers TIM2-5 with DMA */ +# define STM32_NGTIMNDMA 0 /* No 16-bit general timers without DMA */ +# define STM32_NBTIM 0 /* No basic timers */ +# define STM32_NDMA 2 /* DMA1-2 */ +# define STM32_NSPI 3 /* SPI1-3 */ +# define STM32_NI2S 0 /* No I2S (?) */ +# define STM32_NUSART 3 /* USART1-3 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 2 /* I2C1-2 */ +# define STM32_NCAN 1 /* CAN1 */ +# define STM32_NSDIO 1 /* SDIO */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 0 /* No USB OTG FS/HS */ +# define STM32_NGPIO 112 /* GPIOA-G */ +# define STM32_NADC 1 /* ADC1 */ +# define STM32_NDAC 0 /* No DAC */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 0 /* No CRC */ +# define STM32_NETHERNET 0 /* No Ethernet */ +# define STM32_NRNG 0 /* No random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + +/* STM32 F105/F107 Connectivity Line ****************************************/ + +#elif defined(CONFIG_ARCH_CHIP_STM32F105VB) +# define STM32_NFSMC 1 /* FSMC */ +# define STM32_NATIM 1 /* One advanced timers TIM1 */ +# define STM32_NGTIM 4 /* 16-bit general timers TIM2-5 with DMA */ +# define STM32_NGTIMNDMA 0 /* No 16-bit general timers without DMA */ +# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ +# define STM32_NDMA 2 /* DMA1-2 */ +# define STM32_NSPI 3 /* SPI1-3 */ +# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ +# define STM32_NUSART 5 /* USART1-3, UART 4-5 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 2 /* I2C1-2 */ +# define STM32_NCAN 2 /* CAN1-2 */ +# define STM32_NSDIO 0 /* No SDIO */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ +# define STM32_NGPIO 80 /* GPIOA-E */ +# define STM32_NADC 2 /* ADC1-2 */ +# define STM32_NDAC 2 /* DAC1, 2 channels */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NETHERNET 0 /* 100/100 Ethernet MAC */ +# define STM32_NRNG 0 /* No random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F105RB) +# define STM32_NFSMC 1 /* FSMC */ +# define STM32_NATIM 1 /* One advanced timers TIM1 */ +# define STM32_NGTIM 4 /* 16-bit general timers TIM2-5 with DMA */ +# define STM32_NGTIMNDMA 0 /* No 16-bit general timers without DMA */ +# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ +# define STM32_NDMA 2 /* DMA1-2 */ +# define STM32_NSPI 3 /* SPI1-3 */ +# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ +# define STM32_NUSART 5 /* USART1-3, UART 4-5 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 2 /* I2C1-2 */ +# define STM32_NCAN 2 /* CAN1-2 */ +# define STM32_NSDIO 0 /* No SDIO */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ +# define STM32_NGPIO 51 /* GPIOA-E */ +# define STM32_NADC 2 /* ADC1-2 */ +# define STM32_NDAC 2 /* DAC1, 2 channels */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NETHERNET 0 /* 100/100 Ethernet MAC */ +# define STM32_NRNG 0 /* No random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F107VC) +# define STM32_NFSMC 1 /* FSMC */ +# define STM32_NATIM 1 /* One advanced timers TIM1 */ +# define STM32_NGTIM 4 /* 16-bit general timers TIM2-5 with DMA */ +# define STM32_NGTIMNDMA 0 /* No 16-bit general timers without DMA */ +# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ +# define STM32_NDMA 2 /* DMA1-2 */ +# define STM32_NSPI 3 /* SPI1-3 */ +# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ +# define STM32_NUSART 5 /* USART1-3, UART 4-5 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 1 /* I2C1 */ +# define STM32_NCAN 2 /* CAN1-2 */ +# define STM32_NSDIO 0 /* No SDIO */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 0 /* No USB OTG FS/HS */ +# define STM32_NGPIO 80 /* GPIOA-E */ +# define STM32_NADC 2 /* ADC1-2*/ +# define STM32_NDAC 2 /* DAC1, 2 channels */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */ +# define STM32_NRNG 0 /* No random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + +/* STM32 F2 Family **********************************************************/ + +#else +# error "Unsupported STM32 chip" +#endif + +/* Peripheral IP versions ***************************************************/ + +/* Peripheral IP versions are invariant and should be decided here, not in + * Kconfig. + * + * REVISIT: Currently only SPI IP version is handled here, with others being + * handled in Kconfig. Those others need to be gradually refactored + * and resolved here. + */ + +#define STM32_HAVE_IP_SPI_V1 + +/* NVIC priority levels *****************************************************/ + +#define NVIC_SYSH_PRIORITY_MIN 0xf0 /* All bits set in minimum priority */ +#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */ +#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */ +#define NVIC_SYSH_PRIORITY_STEP 0x10 /* Four bits of interrupt priority used */ + +#endif /* __ARCH_ARM_INCLUDE_STM32F1_CHIP_H */ diff --git a/arch/arm/include/stm32f1/irq.h b/arch/arm/include/stm32f1/irq.h new file mode 100644 index 0000000000000..50020cb6d587d --- /dev/null +++ b/arch/arm/include/stm32f1/irq.h @@ -0,0 +1,286 @@ +/**************************************************************************** + * arch/arm/include/stm32f1/irq.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* This file should never be included directly but, rather, + * only indirectly through nuttx/irq.h + */ + +#ifndef __ARCH_ARM_INCLUDE_STM32F1_IRQ_H +#define __ARCH_ARM_INCLUDE_STM32F1_IRQ_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include + +/**************************************************************************** + * Pre-processor Prototypes + ****************************************************************************/ + +/* IRQ numbers. + * The IRQ number corresponds vector number and hence map directly to + * bits in the NVIC. This does, however, waste several words of memory in + * the IRQ to handle mapping tables. + */ + +/* Processor Exceptions (vectors 0-15) */ + +#define STM32_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */ + /* Vector 0: Reset stack pointer value */ + /* Vector 1: Reset (not handler as an IRQ) */ +#define STM32_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */ +#define STM32_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */ +#define STM32_IRQ_MEMFAULT (4) /* Vector 4: Memory management (MPU) */ +#define STM32_IRQ_BUSFAULT (5) /* Vector 5: Bus fault */ +#define STM32_IRQ_USAGEFAULT (6) /* Vector 6: Usage fault */ +#define STM32_IRQ_SVCALL (11) /* Vector 11: SVC call */ +#define STM32_IRQ_DBGMONITOR (12) /* Vector 12: Debug Monitor */ + /* Vector 13: Reserved */ +#define STM32_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */ +#define STM32_IRQ_SYSTICK (15) /* Vector 15: System tick */ + +/* External interrupts (vectors >= 16). + * These definitions are chip-specific + */ + +#define STM32_IRQ_FIRST (16) /* Vector number of the first external interrupt */ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#if defined(CONFIG_STM32_VALUELINE) +# define STM32_IRQ_WWDG (16) /* 0: Window Watchdog interrupt */ +# define STM32_IRQ_PVD (17) /* 1: PVD through EXTI Line detection interrupt */ +# define STM32_IRQ_TAMPER (18) /* 2: Tamper interrupt */ +# define STM32_IRQ_RTC (19) /* 3: RTC Wakeup through EXTI line interrupt */ +# define STM32_IRQ_FLASH (20) /* 4: Flash global interrupt */ +# define STM32_IRQ_RCC (21) /* 5: RCC global interrupt */ +# define STM32_IRQ_EXTI0 (22) /* 6: EXTI Line 0 interrupt */ +# define STM32_IRQ_EXTI1 (23) /* 7: EXTI Line 1 interrupt */ +# define STM32_IRQ_EXTI2 (24) /* 8: EXTI Line 2 interrupt */ +# define STM32_IRQ_EXTI3 (25) /* 9: EXTI Line 3 interrupt */ +# define STM32_IRQ_EXTI4 (26) /* 10: EXTI Line 4 interrupt */ +# define STM32_IRQ_DMA1CH1 (27) /* 11: DMA1 Channel 1 global interrupt */ +# define STM32_IRQ_DMA1CH2 (28) /* 12: DMA1 Channel 2 global interrupt */ +# define STM32_IRQ_DMA1CH3 (29) /* 13: DMA1 Channel 3 global interrupt */ +# define STM32_IRQ_DMA1CH4 (30) /* 14: DMA1 Channel 4 global interrupt */ +# define STM32_IRQ_DMA1CH5 (31) /* 15: DMA1 Channel 5 global interrupt */ +# define STM32_IRQ_DMA1CH6 (32) /* 16: DMA1 Channel 6 global interrupt */ +# define STM32_IRQ_DMA1CH7 (33) /* 17: DMA1 Channel 7 global interrupt */ +# define STM32_IRQ_ADC1 (34) /* 18: ADC1 global interrupt */ +# define STM32_IRQ_RESERVED0 (35) /* 19: Reserved 0 */ +# define STM32_IRQ_RESERVED1 (36) /* 20: Reserved 1 */ +# define STM32_IRQ_RESERVED2 (37) /* 21: Reserved 2 */ +# define STM32_IRQ_RESERVED3 (38) /* 22: Reserved 3 */ +# define STM32_IRQ_EXTI95 (39) /* 23: EXTI Line[9:5] interrupts */ +# define STM32_IRQ_TIM1BRK (40) /* 24: TIM1 Break interrupt */ +# define STM32_IRQ_TIM15 (40) /* TIM15 global interrupt */ +# define STM32_IRQ_TIM1UP (41) /* 25: TIM1 Update interrupt */ +# define STM32_IRQ_TIM16 (41) /* TIM16 global interrupt */ +# define STM32_IRQ_TIM1TRGCOM (42) /* 26: TIM1 Trigger and Commutation interrupts */ +# define STM32_IRQ_TIM17 (42) /* TIM17 global interrupt */ +# define STM32_IRQ_TIM1CC (43) /* 27: TIM1 Capture Compare interrupt */ +# define STM32_IRQ_TIM2 (44) /* 28: TIM2 global interrupt */ +# define STM32_IRQ_TIM3 (45) /* 29: TIM3 global interrupt */ +# define STM32_IRQ_TIM4 (46) /* 30: TIM4 global interrupt */ +# define STM32_IRQ_I2C1EV (47) /* 31: I2C1 event interrupt */ +# define STM32_IRQ_I2C1ER (48) /* 32: I2C1 error interrupt */ +# define STM32_IRQ_I2C2EV (49) /* 33: I2C2 event interrupt */ +# define STM32_IRQ_I2C2ER (50) /* 34: I2C2 error interrupt */ +# define STM32_IRQ_SPI1 (51) /* 35: SPI1 global interrupt */ +# define STM32_IRQ_SPI2 (52) /* 36: SPI2 global interrupt */ +# define STM32_IRQ_USART1 (53) /* 37: USART1 global interrupt */ +# define STM32_IRQ_USART2 (54) /* 38: USART2 global interrupt */ +# define STM32_IRQ_USART3 (55) /* 39: USART3 global interrupt */ +# define STM32_IRQ_EXTI1510 (56) /* 40: EXTI Line[15:10] interrupts */ +# define STM32_IRQ_RTCALR (57) /* 41: RTC alarms (A and B) through EXTI line interrupt */ +# define STM32_IRQ_CEC (58) /* 42: CEC global interrupt */ +# define STM32_IRQ_TIM12 (59) /* 43: TIM12 global interrupt */ +# define STM32_IRQ_TIM13 (60) /* 44: TIM13 global interrupt */ +# define STM32_IRQ_TIM14 (61) /* 45: TIM14 global interrupt */ +# define STM32_IRQ_RESERVED4 (62) /* 46: Reserved 4 */ +# define STM32_IRQ_RESERVED5 (63) /* 47: Reserved 5 */ +# define STM32_IRQ_FSMC (64) /* 48: FSMC global interrupt */ +# define STM32_IRQ_RESERVED6 (65) /* 49: Reserved 6 */ +# define STM32_IRQ_TIM5 (66) /* 50: TIM5 global interrupt */ +# define STM32_IRQ_SPI3 (67) /* 51: SPI3 global interrupt */ +# define STM32_IRQ_UART4 (68) /* 52: USART2 global interrupt */ +# define STM32_IRQ_UART5 (69) /* 53: UART5 global interrupt */ +# define STM32_IRQ_TIM6 (70) /* 54: TIM6 global interrupt */ +# define STM32_IRQ_TIM7 (71) /* 55: TIM7 global interrupt */ +# define STM32_IRQ_DMA2CH1 (72) /* 56: DMA2 Channel 1 global interrupt */ +# define STM32_IRQ_DMA2CH2 (73) /* 57: DMA2 Channel 2 global interrupt */ +# define STM32_IRQ_DMA2CH3 (74) /* 58: DMA2 Channel 3 global interrupt */ +# define STM32_IRQ_DMA2CH45 (75) /* 59: DMA2 Channel 4 and 5 global interrupt */ +# define STM32_IRQ_DMA2CH5 (76) /* 60: DMA2 Channel 5 global interrupt */ + +# define STM32_IRQ_NEXTINTS (61) + +#elif defined(CONFIG_STM32_CONNECTIVITYLINE) +# define STM32_IRQ_WWDG (16) /* 0: Window Watchdog interrupt */ +# define STM32_IRQ_PVD (17) /* 1: PVD through EXTI Line detection interrupt */ +# define STM32_IRQ_TAMPER (18) /* 2: Tamper interrupt */ +# define STM32_IRQ_RTC (19) /* 3: RTC global interrupt */ +# define STM32_IRQ_FLASH (20) /* 4: Flash global interrupt */ +# define STM32_IRQ_RCC (21) /* 5: RCC global interrupt */ +# define STM32_IRQ_EXTI0 (22) /* 6: EXTI Line 0 interrupt */ +# define STM32_IRQ_EXTI1 (23) /* 7: EXTI Line 1 interrupt */ +# define STM32_IRQ_EXTI2 (24) /* 8: EXTI Line 2 interrupt */ +# define STM32_IRQ_EXTI3 (25) /* 9: EXTI Line 3 interrupt */ +# define STM32_IRQ_EXTI4 (26) /* 10: EXTI Line 4 interrupt */ +# define STM32_IRQ_DMA1CH1 (27) /* 11: DMA1 Channel 1 global interrupt */ +# define STM32_IRQ_DMA1CH2 (28) /* 12: DMA1 Channel 2 global interrupt */ +# define STM32_IRQ_DMA1CH3 (29) /* 13: DMA1 Channel 3 global interrupt */ +# define STM32_IRQ_DMA1CH4 (30) /* 14: DMA1 Channel 4 global interrupt */ +# define STM32_IRQ_DMA1CH5 (31) /* 15: DMA1 Channel 5 global interrupt */ +# define STM32_IRQ_DMA1CH6 (32) /* 16: DMA1 Channel 6 global interrupt */ +# define STM32_IRQ_DMA1CH7 (33) /* 17: DMA1 Channel 7 global interrupt */ +# define STM32_IRQ_ADC12 (34) /* 18: ADC1 and ADC2 global interrupt */ +# define STM32_IRQ_CAN1TX (35) /* 19: CAN1 TX interrupts */ +# define STM32_IRQ_CAN1RX0 (36) /* 20: CAN1 RX0 interrupts */ +# define STM32_IRQ_CAN1RX1 (37) /* 21: CAN1 RX1 interrupt */ +# define STM32_IRQ_CAN1SCE (38) /* 22: CAN1 SCE interrupt */ +# define STM32_IRQ_EXTI95 (39) /* 23: EXTI Line[9:5] interrupts */ +# define STM32_IRQ_TIM1BRK (40) /* 24: TIM1 Break interrupt */ +# define STM32_IRQ_TIM1UP (41) /* 25: TIM1 Update interrupt */ +# define STM32_IRQ_TIM1TRGCOM (42) /* 26: TIM1 Trigger and Commutation interrupts */ +# define STM32_IRQ_TIM1CC (43) /* 27: TIM1 Capture Compare interrupt */ +# define STM32_IRQ_TIM2 (44) /* 28: TIM2 global interrupt */ +# define STM32_IRQ_TIM3 (45) /* 29: TIM3 global interrupt */ +# define STM32_IRQ_TIM4 (46) /* 30: TIM4 global interrupt */ +# define STM32_IRQ_I2C1EV (47) /* 31: I2C1 event interrupt */ +# define STM32_IRQ_I2C1ER (48) /* 32: I2C1 error interrupt */ +# define STM32_IRQ_I2C2EV (49) /* 33: I2C2 event interrupt */ +# define STM32_IRQ_I2C2ER (50) /* 34: I2C2 error interrupt */ +# define STM32_IRQ_SPI1 (51) /* 35: SPI1 global interrupt */ +# define STM32_IRQ_SPI2 (52) /* 36: SPI2 global interrupt */ +# define STM32_IRQ_USART1 (53) /* 37: USART1 global interrupt */ +# define STM32_IRQ_USART2 (54) /* 38: USART2 global interrupt */ +# define STM32_IRQ_USART3 (55) /* 39: USART3 global interrupt */ +# define STM32_IRQ_EXTI1510 (56) /* 40: EXTI Line[15:10] interrupts */ +# define STM32_IRQ_RTCALRM (57) /* 41: RTC alarm through EXTI line interrupt */ +# define STM32_IRQ_OTGFSWKUP (58) /* 42: USB On-The-Go FS Wakeup through EXTI line interrupt */ +# define STM32_IRQ_RESERVED0 (59) /* 43: Reserved 0 */ +# define STM32_IRQ_RESERVED1 (60) /* 44: Reserved 1 */ +# define STM32_IRQ_RESERVED2 (61) /* 45: Reserved 2 */ +# define STM32_IRQ_RESERVED3 (62) /* 46: Reserved 3 */ +# define STM32_IRQ_RESERVED4 (63) /* 47: Reserved 4 */ +# define STM32_IRQ_RESERVED5 (64) /* 48: Reserved 5 */ +# define STM32_IRQ_RESERVED6 (65) /* 49: Reserved 6 */ +# define STM32_IRQ_TIM5 (66) /* 50: TIM5 global interrupt */ +# define STM32_IRQ_SPI3 (67) /* 51: SPI3 global interrupt */ +# define STM32_IRQ_UART4 (68) /* 52: UART4 global interrupt */ +# define STM32_IRQ_UART5 (69) /* 53: UART5 global interrupt */ +# define STM32_IRQ_TIM6 (70) /* 54: TIM6 global interrupt */ +# define STM32_IRQ_TIM7 (71) /* 55: TIM7 global interrupt */ +# define STM32_IRQ_DMA2CH1 (72) /* 56: DMA2 Channel 1 global interrupt */ +# define STM32_IRQ_DMA2CH2 (73) /* 57: DMA2 Channel 2 global interrupt */ +# define STM32_IRQ_DMA2CH3 (74) /* 58: DMA2 Channel 3 global interrupt */ +# define STM32_IRQ_DMA2CH4 (75) /* 59: DMA2 Channel 4 global interrupt */ +# define STM32_IRQ_DMA2CH5 (76) /* 60: DMA2 Channel 5 global interrupt */ +# define STM32_IRQ_ETH (77) /* 61: Ethernet global interrupt */ +# define STM32_IRQ_ETHWKUP (78) /* 62: Ethernet Wakeup through EXTI line interrupt */ +# define STM32_IRQ_CAN2TX (79) /* 63: CAN2 TX interrupts */ +# define STM32_IRQ_CAN2RX0 (80) /* 64: CAN2 RX0 interrupts */ +# define STM32_IRQ_CAN2RX1 (81) /* 65: CAN2 RX1 interrupt */ +# define STM32_IRQ_CAN2SCE (82) /* 66: CAN2 SCE interrupt */ +# define STM32_IRQ_OTGFS (83) /* 67: USB On The Go FS global interrupt */ + +# define STM32_IRQ_NEXTINTS (68) + +#else +# define STM32_IRQ_WWDG (16) /* 0: Window Watchdog interrupt */ +# define STM32_IRQ_PVD (17) /* 1: PVD through EXTI Line detection interrupt */ +# define STM32_IRQ_TAMPER (18) /* 2: Tamper interrupt */ +# define STM32_IRQ_RTC (19) /* 3: RTC global interrupt */ +# define STM32_IRQ_FLASH (20) /* 4: Flash global interrupt */ +# define STM32_IRQ_RCC (21) /* 5: RCC global interrupt */ +# define STM32_IRQ_EXTI0 (22) /* 6: EXTI Line 0 interrupt */ +# define STM32_IRQ_EXTI1 (23) /* 7: EXTI Line 1 interrupt */ +# define STM32_IRQ_EXTI2 (24) /* 8: EXTI Line 2 interrupt */ +# define STM32_IRQ_EXTI3 (25) /* 9: EXTI Line 3 interrupt */ +# define STM32_IRQ_EXTI4 (26) /* 10: EXTI Line 4 interrupt */ +# define STM32_IRQ_DMA1CH1 (27) /* 11: DMA1 Channel 1 global interrupt */ +# define STM32_IRQ_DMA1CH2 (28) /* 12: DMA1 Channel 2 global interrupt */ +# define STM32_IRQ_DMA1CH3 (29) /* 13: DMA1 Channel 3 global interrupt */ +# define STM32_IRQ_DMA1CH4 (30) /* 14: DMA1 Channel 4 global interrupt */ +# define STM32_IRQ_DMA1CH5 (31) /* 15: DMA1 Channel 5 global interrupt */ +# define STM32_IRQ_DMA1CH6 (32) /* 16: DMA1 Channel 6 global interrupt */ +# define STM32_IRQ_DMA1CH7 (33) /* 17: DMA1 Channel 7 global interrupt */ +# define STM32_IRQ_ADC12 (34) /* 18: ADC1 and ADC2 global interrupt */ +# define STM32_IRQ_USBHPCANTX (35) /* 19: USB High Priority or CAN TX interrupts*/ +# define STM32_IRQ_USBLPCANRX0 (36) /* 20: USB Low Priority or CAN RX0 interrupts*/ +# define STM32_IRQ_CAN1RX1 (37) /* 21: CAN1 RX1 interrupt */ +# define STM32_IRQ_CAN1SCE (38) /* 22: CAN1 SCE interrupt */ +# define STM32_IRQ_EXTI95 (39) /* 23: EXTI Line[9:5] interrupts */ +# define STM32_IRQ_TIM1BRK (40) /* 24: TIM1 Break interrupt */ +# define STM32_IRQ_TIM1UP (41) /* 25: TIM1 Update interrupt */ +# define STM32_IRQ_TIM1TRGCOM (42) /* 26: TIM1 Trigger and Commutation interrupts */ +# define STM32_IRQ_TIM1CC (43) /* 27: TIM1 Capture Compare interrupt */ +# define STM32_IRQ_TIM2 (44) /* 28: TIM2 global interrupt */ +# define STM32_IRQ_TIM3 (45) /* 29: TIM3 global interrupt */ +# define STM32_IRQ_TIM4 (46) /* 30: TIM4 global interrupt */ +# define STM32_IRQ_I2C1EV (47) /* 31: I2C1 event interrupt */ +# define STM32_IRQ_I2C1ER (48) /* 32: I2C1 error interrupt */ +# define STM32_IRQ_I2C2EV (49) /* 33: I2C2 event interrupt */ +# define STM32_IRQ_I2C2ER (50) /* 34: I2C2 error interrupt */ +# define STM32_IRQ_SPI1 (51) /* 35: SPI1 global interrupt */ +# define STM32_IRQ_SPI2 (52) /* 36: SPI2 global interrupt */ +# define STM32_IRQ_USART1 (53) /* 37: USART1 global interrupt */ +# define STM32_IRQ_USART2 (54) /* 38: USART2 global interrupt */ +# define STM32_IRQ_USART3 (55) /* 39: USART3 global interrupt */ +# define STM32_IRQ_EXTI1510 (56) /* 40: EXTI Line[15:10] interrupts */ +# define STM32_IRQ_RTCALRM (57) /* 41: RTC alarm through EXTI line interrupt */ +# define STM32_IRQ_USBWKUP (58) /* 42: USB wakeup from suspend through EXTI line interrupt*/ +# define STM32_IRQ_TIM8BRK (59) /* 43: TIM8 Break interrupt */ +# define STM32_IRQ_TIM8UP (60) /* 44: TIM8 Update interrupt */ +# define STM32_IRQ_TIM8TRGCOM (61) /* 45: TIM8 Trigger and Commutation interrupts */ +# define STM32_IRQ_TIM8CC (62) /* 46: TIM8 Capture Compare interrupt */ +# define STM32_IRQ_ADC3 (63) /* 47: ADC3 global interrupt */ +# define STM32_IRQ_FSMC (64) /* 48: FSMC global interrupt */ +# define STM32_IRQ_SDIO (65) /* 49: SDIO global interrupt */ +# define STM32_IRQ_TIM5 (66) /* 50: TIM5 global interrupt */ +# define STM32_IRQ_SPI3 (67) /* 51: SPI3 global interrupt */ +# define STM32_IRQ_UART4 (68) /* 52: UART4 global interrupt */ +# define STM32_IRQ_UART5 (69) /* 53: UART5 global interrupt */ +# define STM32_IRQ_TIM6 (70) /* 54: TIM6 global interrupt */ +# define STM32_IRQ_TIM7 (71) /* 55: TIM7 global interrupt */ +# define STM32_IRQ_DMA2CH1 (72) /* 56: DMA2 Channel 1 global interrupt */ +# define STM32_IRQ_DMA2CH2 (73) /* 57: DMA2 Channel 2 global interrupt */ +# define STM32_IRQ_DMA2CH3 (74) /* 58: DMA2 Channel 3 global interrupt */ +# define STM32_IRQ_DMA2CH45 (75) /* 59: DMA2 Channel 4&5 global interrupt */ + +# define STM32_IRQ_NEXTINTS (60) + +# define STM32_IRQ_USBHP STM32_IRQ_USBHPCANTX +# define STM32_IRQ_CAN1TX STM32_IRQ_USBHPCANTX +# define STM32_IRQ_USBLP STM32_IRQ_USBLPCANRX0 +# define STM32_IRQ_CAN1RX0 STM32_IRQ_USBLPCANRX0 +#endif + +# define NR_IRQS (STM32_IRQ_FIRST + STM32_IRQ_NEXTINTS) + +#endif /* __ARCH_ARM_INCLUDE_STM32F1_IRQ_H */ diff --git a/arch/arm/include/stm32f2/chip.h b/arch/arm/include/stm32f2/chip.h new file mode 100644 index 0000000000000..6252fc7ad06ed --- /dev/null +++ b/arch/arm/include/stm32f2/chip.h @@ -0,0 +1,189 @@ +/**************************************************************************** + * arch/arm/include/stm32f2/chip.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_INCLUDE_STM32F2_CHIP_H +#define __ARCH_ARM_INCLUDE_STM32F2_CHIP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Prototypes + ****************************************************************************/ + +/* Get customizations for each supported chip and provide alternate function + * pin-mapping + * + * NOTE: Each GPIO pin may serve either for general purpose I/O or for a + * special alternate function (such as USART, CAN, USB, SDIO, etc.). That + * particular pin-mapping will depend on the package and STM32 family. If + * you are incorporating a new STM32 chip into NuttX, you will need to add + * the pin-mapping to a header file and to include that header file below. + * The chip-specific pin-mapping is defined in the chip datasheet. + */ + +#if defined(CONFIG_ARCH_CHIP_STM32F205RG) /* UFBGA-176 1024Kb FLASH 128Kb SRAM */ +# define STM32_NFSMC 0 /* No FSMC */ +# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ +# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA + * 32-bit general timers TIM2 and 5 with DMA */ +# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ +# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ +# define STM32_NDMA 2 /* DMA1-2 */ +# define STM32_NSPI 3 /* SPI1-3 */ +# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ +# define STM32_NUSART 6 /* USART1-3 and 6, UART 4-5 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 3 /* I2C1-3 */ +# define STM32_NCAN 2 /* CAN1-2 */ +# define STM32_NSDIO 1 /* SDIO */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ +# define STM32_NGPIO 51 /* GPIOA-I */ +# define STM32_NADC 3 /* 12-bit ADC1-3, 16 channels */ +# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NETHERNET 0 /* No Ethernet MAC */ +# define STM32_NRNG 1 /* Random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F207VC) || defined(CONFIG_ARCH_CHIP_STM32F207VE) || \ + defined(CONFIG_ARCH_CHIP_STM32F207VF) || defined(CONFIG_ARCH_CHIP_STM32F207VG) +# define STM32_NFSMC 1 /* FSMC */ +# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ +# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA + * 32-bit general timers TIM2 and 5 with DMA */ +# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ +# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ +# define STM32_NDMA 2 /* DMA1-2 */ +# define STM32_NSPI 3 /* SPI1-3 */ +# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ +# define STM32_NUSART 6 /* USART1-3 and 6, UART 4-5 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 3 /* I2C1-3 */ +# define STM32_NCAN 2 /* CAN1-2 */ +# define STM32_NSDIO 1 /* SDIO */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ +# define STM32_NGPIO 82 /* GPIOA-I */ +# define STM32_NADC 3 /* 12-bit ADC1-3, 24 channels */ +# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */ +# define STM32_NRNG 1 /* Random number generator (RNG) */ +# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F207IC) || defined(CONFIG_ARCH_CHIP_STM32F207IE) || \ + defined(CONFIG_ARCH_CHIP_STM32F207IF) || defined(CONFIG_ARCH_CHIP_STM32F207IG) +# define STM32_NFSMC 1 /* FSMC */ +# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ +# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA + * 32-bit general timers TIM2 and 5 with DMA */ +# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ +# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ +# define STM32_NDMA 2 /* DMA1-2 */ +# define STM32_NSPI 3 /* SPI1-3 */ +# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ +# define STM32_NUSART 6 /* USART1-3 and 6, UART 4-5 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 3 /* I2C1-3 */ +# define STM32_NCAN 2 /* CAN1-2 */ +# define STM32_NSDIO 1 /* SDIO */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ +# define STM32_NGPIO 140 /* GPIOA-I */ +# define STM32_NADC 3 /* 12-bit ADC1-3, 24 channels */ +# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */ +# define STM32_NRNG 1 /* Random number generator (RNG) */ +# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F207ZC) || defined(CONFIG_ARCH_CHIP_STM32F207ZE) || \ + defined(CONFIG_ARCH_CHIP_STM32F207ZF) || defined(CONFIG_ARCH_CHIP_STM32F207ZG) +# define STM32_NFSMC 1 /* FSMC */ +# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ +# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA + * 32-bit general timers TIM2 and 5 with DMA */ +# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ +# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ +# define STM32_NDMA 2 /* DMA1-2 */ +# define STM32_NSPI 3 /* SPI1-3 */ +# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ +# define STM32_NUSART 6 /* USART1-3 and 6, UART 4-5 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 3 /* I2C1-3 */ +# define STM32_NCAN 2 /* CAN1-2 */ +# define STM32_NSDIO 1 /* SDIO */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ +# define STM32_NGPIO 114 /* GPIOA-I */ +# define STM32_NADC 3 /* 12-bit ADC1-3, 24 channels */ +# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */ +# define STM32_NRNG 1 /* Random number generator (RNG) */ +# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */ + +/* STM23 F3 Family **********************************************************/ + +/* Part Numbering: STM32Fssscfxxx + * + * Where + * sss = 302/303, 334 or 372/373 + * c = C (48pins) R (68 pins) V (100 pins) + * c = K (32 pins), C (48 pins), R (68 pins), V (100 pins) + * f = 6 (32KB FLASH), 8 (64KB FLASH), B (128KB FLASH), C (256KB FLASH) + * xxx = Package, temperature range, options (ignored here) + */ + +#else +# error "Unsupported STM32 chip" +#endif + +/* Peripheral IP versions ***************************************************/ + +/* Peripheral IP versions are invariant and should be decided here, not in + * Kconfig. + * + * REVISIT: Currently only SPI IP version is handled here, with others being + * handled in Kconfig. Those others need to be gradually refactored + * and resolved here. + */ + +#define STM32_HAVE_IP_SPI_V2 + +/* NVIC priority levels *****************************************************/ + +#define NVIC_SYSH_PRIORITY_MIN 0xf0 /* All bits set in minimum priority */ +#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */ +#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */ +#define NVIC_SYSH_PRIORITY_STEP 0x10 /* Four bits of interrupt priority used */ + +#endif /* __ARCH_ARM_INCLUDE_STM32F2_CHIP_H */ diff --git a/arch/arm/include/stm32f2/irq.h b/arch/arm/include/stm32f2/irq.h new file mode 100644 index 0000000000000..b91d6952fa90c --- /dev/null +++ b/arch/arm/include/stm32f2/irq.h @@ -0,0 +1,168 @@ +/**************************************************************************** + * arch/arm/include/stm32f2/irq.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* This file should never be included directly but, rather, + * only indirectly through nuttx/irq.h + */ + +#ifndef __ARCH_ARM_INCLUDE_STM32F2_IRQ_H +#define __ARCH_ARM_INCLUDE_STM32F2_IRQ_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include + +/**************************************************************************** + * Pre-processor Prototypes + ****************************************************************************/ + +/* IRQ numbers. + * The IRQ number corresponds vector number and hence map directly to + * bits in the NVIC. This does, however, waste several words of memory in + * the IRQ to handle mapping tables. + */ + +/* Processor Exceptions (vectors 0-15) */ + +#define STM32_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */ + /* Vector 0: Reset stack pointer value */ + /* Vector 1: Reset (not handler as an IRQ) */ +#define STM32_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */ +#define STM32_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */ +#define STM32_IRQ_MEMFAULT (4) /* Vector 4: Memory management (MPU) */ +#define STM32_IRQ_BUSFAULT (5) /* Vector 5: Bus fault */ +#define STM32_IRQ_USAGEFAULT (6) /* Vector 6: Usage fault */ +#define STM32_IRQ_SVCALL (11) /* Vector 11: SVC call */ +#define STM32_IRQ_DBGMONITOR (12) /* Vector 12: Debug Monitor */ + /* Vector 13: Reserved */ +#define STM32_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */ +#define STM32_IRQ_SYSTICK (15) /* Vector 15: System tick */ + +/* External interrupts (vectors >= 16). + * These definitions are chip-specific + */ + +#define STM32_IRQ_FIRST (16) /* Vector number of the first external interrupt */ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#define STM32_IRQ_WWDG (STM32_IRQ_FIRST + 0) /* 0: Window Watchdog interrupt */ +#define STM32_IRQ_PVD (STM32_IRQ_FIRST + 1) /* 1: PVD through EXTI Line detection interrupt */ +#define STM32_IRQ_TAMPER (STM32_IRQ_FIRST + 2) /* 2: Tamper and time stamp interrupts */ +#define STM32_IRQ_TIMESTAMP (STM32_IRQ_FIRST + 2) /* 2: Tamper and time stamp interrupts */ +#define STM32_IRQ_RTC_WKUP (STM32_IRQ_FIRST + 3) /* 3: RTC global interrupt */ +#define STM32_IRQ_FLASH (STM32_IRQ_FIRST + 4) /* 4: Flash global interrupt */ +#define STM32_IRQ_RCC (STM32_IRQ_FIRST + 5) /* 5: RCC global interrupt */ +#define STM32_IRQ_EXTI0 (STM32_IRQ_FIRST + 6) /* 6: EXTI Line 0 interrupt */ +#define STM32_IRQ_EXTI1 (STM32_IRQ_FIRST + 7) /* 7: EXTI Line 1 interrupt */ +#define STM32_IRQ_EXTI2 (STM32_IRQ_FIRST + 8) /* 8: EXTI Line 2 interrupt */ +#define STM32_IRQ_EXTI3 (STM32_IRQ_FIRST + 9) /* 9: EXTI Line 3 interrupt */ +#define STM32_IRQ_EXTI4 (STM32_IRQ_FIRST + 10) /* 10: EXTI Line 4 interrupt */ +#define STM32_IRQ_DMA1S0 (STM32_IRQ_FIRST + 11) /* 11: DMA1 Stream 0 global interrupt */ +#define STM32_IRQ_DMA1S1 (STM32_IRQ_FIRST + 12) /* 12: DMA1 Stream 1 global interrupt */ +#define STM32_IRQ_DMA1S2 (STM32_IRQ_FIRST + 13) /* 13: DMA1 Stream 2 global interrupt */ +#define STM32_IRQ_DMA1S3 (STM32_IRQ_FIRST + 14) /* 14: DMA1 Stream 3 global interrupt */ +#define STM32_IRQ_DMA1S4 (STM32_IRQ_FIRST + 15) /* 15: DMA1 Stream 4 global interrupt */ +#define STM32_IRQ_DMA1S5 (STM32_IRQ_FIRST + 16) /* 16: DMA1 Stream 5 global interrupt */ +#define STM32_IRQ_DMA1S6 (STM32_IRQ_FIRST + 17) /* 17: DMA1 Stream 6 global interrupt */ +#define STM32_IRQ_ADC (STM32_IRQ_FIRST + 18) /* 18: ADC1, ADC2, and ADC3 global interrupt */ +#define STM32_IRQ_CAN1TX (STM32_IRQ_FIRST + 19) /* 19: CAN1 TX interrupts */ +#define STM32_IRQ_CAN1RX0 (STM32_IRQ_FIRST + 20) /* 20: CAN1 RX0 interrupts */ +#define STM32_IRQ_CAN1RX1 (STM32_IRQ_FIRST + 21) /* 21: CAN1 RX1 interrupt */ +#define STM32_IRQ_CAN1SCE (STM32_IRQ_FIRST + 22) /* 22: CAN1 SCE interrupt */ +#define STM32_IRQ_EXTI95 (STM32_IRQ_FIRST + 23) /* 23: EXTI Line[9:5] interrupts */ +#define STM32_IRQ_TIM1BRK (STM32_IRQ_FIRST + 24) /* 24: TIM1 Break interrupt */ +#define STM32_IRQ_TIM9 (STM32_IRQ_FIRST + 24) /* 24: TIM9 global interrupt */ +#define STM32_IRQ_TIM1UP (STM32_IRQ_FIRST + 25) /* 25: TIM1 Update interrupt */ +#define STM32_IRQ_TIM10 (STM32_IRQ_FIRST + 25) /* 25: TIM10 global interrupt */ +#define STM32_IRQ_TIM1TRGCOM (STM32_IRQ_FIRST + 26) /* 26: TIM1 Trigger and Commutation interrupts */ +#define STM32_IRQ_TIM11 (STM32_IRQ_FIRST + 26) /* 26: TIM11 global interrupt */ +#define STM32_IRQ_TIM1CC (STM32_IRQ_FIRST + 27) /* 27: TIM1 Capture Compare interrupt */ +#define STM32_IRQ_TIM2 (STM32_IRQ_FIRST + 28) /* 28: TIM2 global interrupt */ +#define STM32_IRQ_TIM3 (STM32_IRQ_FIRST + 29) /* 29: TIM3 global interrupt */ +#define STM32_IRQ_TIM4 (STM32_IRQ_FIRST + 30) /* 30: TIM4 global interrupt */ +#define STM32_IRQ_I2C1EV (STM32_IRQ_FIRST + 31) /* 31: I2C1 event interrupt */ +#define STM32_IRQ_I2C1ER (STM32_IRQ_FIRST + 32) /* 32: I2C1 error interrupt */ +#define STM32_IRQ_I2C2EV (STM32_IRQ_FIRST + 33) /* 33: I2C2 event interrupt */ +#define STM32_IRQ_I2C2ER (STM32_IRQ_FIRST + 34) /* 34: I2C2 error interrupt */ +#define STM32_IRQ_SPI1 (STM32_IRQ_FIRST + 35) /* 35: SPI1 global interrupt */ +#define STM32_IRQ_SPI2 (STM32_IRQ_FIRST + 36) /* 36: SPI2 global interrupt */ +#define STM32_IRQ_USART1 (STM32_IRQ_FIRST + 37) /* 37: USART1 global interrupt */ +#define STM32_IRQ_USART2 (STM32_IRQ_FIRST + 38) /* 38: USART2 global interrupt */ +#define STM32_IRQ_USART3 (STM32_IRQ_FIRST + 39) /* 39: USART3 global interrupt */ +#define STM32_IRQ_EXTI1510 (STM32_IRQ_FIRST + 40) /* 40: EXTI Line[15:10] interrupts */ +#define STM32_IRQ_RTCALRM (STM32_IRQ_FIRST + 41) /* 41: RTC alarm through EXTI line interrupt */ +#define STM32_IRQ_OTGFSWKUP (STM32_IRQ_FIRST + 42) /* 42: USB On-The-Go FS Wakeup through EXTI line interrupt */ +#define STM32_IRQ_TIM8BRK (STM32_IRQ_FIRST + 43) /* 43: TIM8 Break interrupt */ +#define STM32_IRQ_TIM12 (STM32_IRQ_FIRST + 43) /* 43: TIM12 global interrupt */ +#define STM32_IRQ_TIM8UP (STM32_IRQ_FIRST + 44) /* 44: TIM8 Update interrupt */ +#define STM32_IRQ_TIM13 (STM32_IRQ_FIRST + 44) /* 44: TIM13 global interrupt */ +#define STM32_IRQ_TIM8TRGCOM (STM32_IRQ_FIRST + 45) /* 45: TIM8 Trigger and Commutation interrupts */ +#define STM32_IRQ_TIM14 (STM32_IRQ_FIRST + 45) /* 45: TIM14 global interrupt */ +#define STM32_IRQ_TIM8CC (STM32_IRQ_FIRST + 46) /* 46: TIM8 Capture Compare interrupt */ +#define STM32_IRQ_DMA1S7 (STM32_IRQ_FIRST + 47) /* 47: DMA1 Stream 7 global interrupt */ +#define STM32_IRQ_FSMC (STM32_IRQ_FIRST + 48) /* 48: FSMC global interrupt */ +#define STM32_IRQ_SDIO (STM32_IRQ_FIRST + 49) /* 49: SDIO global interrupt */ +#define STM32_IRQ_TIM5 (STM32_IRQ_FIRST + 50) /* 50: TIM5 global interrupt */ +#define STM32_IRQ_SPI3 (STM32_IRQ_FIRST + 51) /* 51: SPI3 global interrupt */ +#define STM32_IRQ_UART4 (STM32_IRQ_FIRST + 52) /* 52: UART4 global interrupt */ +#define STM32_IRQ_UART5 (STM32_IRQ_FIRST + 53) /* 53: UART5 global interrupt */ +#define STM32_IRQ_TIM6 (STM32_IRQ_FIRST + 54) /* 54: TIM6 global interrupt */ +#define STM32_IRQ_DAC (STM32_IRQ_FIRST + 54) /* 54: DAC1 and DAC2 underrun error interrupts */ +#define STM32_IRQ_TIM7 (STM32_IRQ_FIRST + 55) /* 55: TIM7 global interrupt */ +#define STM32_IRQ_DMA2S0 (STM32_IRQ_FIRST + 56) /* 56: DMA2 Stream 0 global interrupt */ +#define STM32_IRQ_DMA2S1 (STM32_IRQ_FIRST + 57) /* 57: DMA2 Stream 1 global interrupt */ +#define STM32_IRQ_DMA2S2 (STM32_IRQ_FIRST + 58) /* 58: DMA2 Stream 2 global interrupt */ +#define STM32_IRQ_DMA2S3 (STM32_IRQ_FIRST + 59) /* 59: DMA2 Stream 3 global interrupt */ +#define STM32_IRQ_DMA2S4 (STM32_IRQ_FIRST + 60) /* 60: DMA2 Stream 4 global interrupt */ +#define STM32_IRQ_ETH (STM32_IRQ_FIRST + 61) /* 61: Ethernet global interrupt */ +#define STM32_IRQ_ETHWKUP (STM32_IRQ_FIRST + 62) /* 62: Ethernet Wakeup through EXTI line interrupt */ +#define STM32_IRQ_CAN2TX (STM32_IRQ_FIRST + 63) /* 63: CAN2 TX interrupts */ +#define STM32_IRQ_CAN2RX0 (STM32_IRQ_FIRST + 64) /* 64: CAN2 RX0 interrupts */ +#define STM32_IRQ_CAN2RX1 (STM32_IRQ_FIRST + 65) /* 65: CAN2 RX1 interrupt */ +#define STM32_IRQ_CAN2SCE (STM32_IRQ_FIRST + 66) /* 66: CAN2 SCE interrupt */ +#define STM32_IRQ_OTGFS (STM32_IRQ_FIRST + 67) /* 67: USB On The Go FS global interrupt */ +#define STM32_IRQ_DMA2S5 (STM32_IRQ_FIRST + 68) /* 68: DMA2 Stream 5 global interrupt */ +#define STM32_IRQ_DMA2S6 (STM32_IRQ_FIRST + 69) /* 69: DMA2 Stream 6 global interrupt */ +#define STM32_IRQ_DMA2S7 (STM32_IRQ_FIRST + 70) /* 70: DMA2 Stream 7 global interrupt */ +#define STM32_IRQ_USART6 (STM32_IRQ_FIRST + 71) /* 71: USART6 global interrupt */ +#define STM32_IRQ_I2C3EV (STM32_IRQ_FIRST + 72) /* 72: I2C3 event interrupt */ +#define STM32_IRQ_I2C3ER (STM32_IRQ_FIRST + 73) /* 73: I2C3 error interrupt */ +#define STM32_IRQ_OTGHSEP1OUT (STM32_IRQ_FIRST + 74) /* 74: USB On The Go HS End Point 1 Out global interrupt */ +#define STM32_IRQ_OTGHSEP1IN (STM32_IRQ_FIRST + 75) /* 75: USB On The Go HS End Point 1 In global interrupt */ +#define STM32_IRQ_OTGHSWKUP (STM32_IRQ_FIRST + 76) /* 76: USB On The Go HS Wakeup through EXTI interrupt */ +#define STM32_IRQ_OTGHS (STM32_IRQ_FIRST + 77) /* 77: USB On The Go HS global interrupt */ +#define STM32_IRQ_DCMI (STM32_IRQ_FIRST + 78) /* 78: DCMI global interrupt */ +#define STM32_IRQ_CRYP (STM32_IRQ_FIRST + 79) /* 79: CRYP crypto global interrupt */ +#define STM32_IRQ_HASH (STM32_IRQ_FIRST + 80) /* 80: Hash and Rng global interrupt */ +#define STM32_IRQ_RNG (STM32_IRQ_FIRST + 80) /* 80: Hash and Rng global interrupt */ + +#define STM32_IRQ_NEXTINTS (81) +#define NR_IRQS (STM32_IRQ_FIRST + STM32_IRQ_NEXTINTS) + +#endif /* __ARCH_ARM_INCLUDE_STM32F2_IRQ_H */ diff --git a/arch/arm/include/stm32f3/chip.h b/arch/arm/include/stm32f3/chip.h new file mode 100644 index 0000000000000..f97f301c8f070 --- /dev/null +++ b/arch/arm/include/stm32f3/chip.h @@ -0,0 +1,627 @@ +/**************************************************************************** + * arch/arm/include/stm32f3/chip.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_INCLUDE_STM32F3_CHIP_H +#define __ARCH_ARM_INCLUDE_STM32F3_CHIP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Prototypes + ****************************************************************************/ + +/* Get customizations for each supported chip and provide alternate function + * pin-mapping + * + * NOTE: Each GPIO pin may serve either for general purpose I/O or for a + * special alternate function (such as USART, CAN, USB, SDIO, etc.). That + * particular pin-mapping will depend on the package and STM32 family. If + * you are incorporating a new STM32 chip into NuttX, you will need to add + * the pin-mapping to a header file and to include that header file below. + * The chip-specific pin-mapping is defined in the chip datasheet. + */ + +#if defined(CONFIG_ARCH_CHIP_STM32F302K6) || defined(CONFIG_ARCH_CHIP_STM32F302K8) +# define STM32_NFSMC 0 /* No FSMC */ +# define STM32_NATIM 1 /* (1) Advanced 16-bit timers with DMA: TIM1 (no TIM8) */ +# define STM32_NGTIM 6 /* (2) 16-bit general timers with DMA: TIM3 and TIM4 + * (1) 32-bit general timers with DMA: TIM2 + * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ +# define STM32_NGTIMNDMA 0 /* All timers have DMA */ + +# define STM32_NBTIM 1 /* (1) Basic timers: TIM6 (no TIM7) */ +# define STM32_NDMA 1 /* (1) DMA1 (7 channels) */ +# define STM32_NSPI 2 /* (3) SPI1-3 */ +# define STM32_NI2S 0 /* (0) No I2S */ +# define STM32_NUSART 2 /* (2) USART1-2, no UARTs */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 3 /* (3) I2C1-3 */ +# define STM32_NCAN 1 /* (1) CAN1 */ +# define STM32_NSDIO 0 /* (0) No SDIO */ +# define STM32_NLCD 0 /* (0) No LCD */ +# define STM32_NUSBOTG 0 /* USB FS device, but no USB OTG FS/HS */ +# define STM32_NGPIO 24 /* GPIOA-F */ +# define STM32_NADC 1 /* (1) 12-bit ADC1 */ +# define STM32_NDAC 1 /* (1) 12-bit DAC1, 1 channel */ +# define STM32_NCMP 2 /* (2) Ultra-fast analog comparators: COMP2 and COMP4 */ +# define STM32_NPGA 1 /* (1) Operational amplifiers: OPAMP */ +# define STM32_NCAPSENSE 13 /* (13) Capacitive sensing channels */ +# define STM32_NCRC 1 /* (1) CRC calculation unit */ +# define STM32_NETHERNET 0 /* (0) No Ethernet MAC */ +# define STM32_NRNG 0 /* (0) No random number generator (RNG) */ +# define STM32_NDCMI 0 /* (0) No digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F302C6) || defined(CONFIG_ARCH_CHIP_STM32F302C8) +# define STM32_NFSMC 0 /* No FSMC */ +# define STM32_NATIM 1 /* (1) Advanced 16-bit timers with DMA: TIM1 (no TIM8) */ +# define STM32_NGTIM 6 /* (2) 16-bit general timers with DMA: TIM3 and TIM4 + * (1) 32-bit general timers with DMA: TIM2 + * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ +# define STM32_NGTIMNDMA 0 /* All timers have DMA */ + +# define STM32_NBTIM 1 /* (1) Basic timers: TIM6 (no TIM7) */ +# define STM32_NDMA 1 /* (1) DMA1 (7 channels) */ +# define STM32_NSPI 2 /* (3) SPI1-3 */ +# define STM32_NI2S 0 /* (0) No I2S */ +# define STM32_NUSART 3 /* (3) USART1-3, no UARTs */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 3 /* (3) I2C1-3 */ +# define STM32_NCAN 1 /* (1) CAN1 */ +# define STM32_NSDIO 0 /* (0) No SDIO */ +# define STM32_NLCD 0 /* (0) No LCD */ +# define STM32_NUSBOTG 0 /* USB FS device, but no USB OTG FS/HS */ +# define STM32_NGPIO 37 /* GPIOA-F */ +# define STM32_NADC 1 /* (1) 12-bit ADC1 */ +# define STM32_NDAC 1 /* (1) 12-bit DAC1, 1 channel */ +# define STM32_NCMP 3 /* (3) Ultra-fast analog comparators: COMP2, COMP4 and COMP6*/ +# define STM32_NPGA 1 /* (1) Operational amplifiers: OPAMP */ +# define STM32_NCAPSENSE 17 /* (17) Capacitive sensing channels */ +# define STM32_NCRC 1 /* (1) CRC calculation unit */ +# define STM32_NETHERNET 0 /* (0) No Ethernet MAC */ +# define STM32_NRNG 0 /* (0) No random number generator (RNG) */ +# define STM32_NDCMI 0 /* (0) No digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F302R6) || defined(CONFIG_ARCH_CHIP_STM32F302R8) +# define STM32_NFSMC 0 /* No FSMC */ +# define STM32_NATIM 1 /* (1) Advanced 16-bit timers with DMA: TIM1 (no TIM8) */ +# define STM32_NGTIM 6 /* (2) 16-bit general timers with DMA: TIM3 and TIM4 + * (1) 32-bit general timers with DMA: TIM2 + * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ +# define STM32_NGTIMNDMA 0 /* All timers have DMA */ + +# define STM32_NBTIM 1 /* (1) Basic timers: TIM6 (no TIM7) */ +# define STM32_NDMA 1 /* (1) DMA1 (7 channels) */ +# define STM32_NSPI 2 /* (3) SPI1-3 */ +# define STM32_NI2S 0 /* (0) No I2S */ +# define STM32_NUSART 3 /* (2) USART1-3, no UARTs */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 3 /* (3) I2C1-3 */ +# define STM32_NCAN 1 /* (1) CAN1 */ +# define STM32_NSDIO 0 /* (0) No SDIO */ +# define STM32_NLCD 0 /* (0) No LCD */ +# define STM32_NUSBOTG 0 /* USB FS device, but no USB OTG FS/HS */ +# define STM32_NGPIO 51 /* GPIOA-F */ +# define STM32_NADC 1 /* (1) 12-bit ADC1 */ +# define STM32_NDAC 1 /* (1) 12-bit DAC1, 1 channel */ +# define STM32_NCMP 3 /* (3) Ultra-fast analog comparators: COMP2, COMP4 and COMP6*/ +# define STM32_NPGA 1 /* (1) Operational amplifiers: OPAMP */ +# define STM32_NCAPSENSE 18 /* (18) Capacitive sensing channels */ +# define STM32_NCRC 1 /* (1) CRC calculation unit */ +# define STM32_NETHERNET 0 /* (0) No Ethernet MAC */ +# define STM32_NRNG 0 /* (0) No random number generator (RNG) */ +# define STM32_NDCMI 0 /* (0) No digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F302CB) || defined(CONFIG_ARCH_CHIP_STM32F302CC) +# define STM32_NFSMC 0 /* No FSMC */ +# define STM32_NATIM 1 /* (1) Advanced 16-bit timers with DMA: TIM1 (no TIM8) */ +# define STM32_NGTIM 6 /* (2) 16-bit general timers with DMA: TIM3 and TIM4 + * (1) 32-bit general timers with DMA: TIM2 + * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ +# define STM32_NGTIMNDMA 0 /* All timers have DMA */ + +# define STM32_NBTIM 1 /* (1) Basic timers: TIM6 (no TIM7) */ +# define STM32_NDMA 2 /* (2) DMA1 (7 channels) and DMA2 (5 channels) */ +# define STM32_NSPI 3 /* (3) SPI1-3 */ +# define STM32_NI2S 0 /* (0) No I2S */ +# define STM32_NUSART 3 /* (3) No UART1-3, no UARTs */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 2 /* (2) I2C1-2 */ +# define STM32_NCAN 1 /* (1) CAN1 */ +# define STM32_NSDIO 0 /* (0) No SDIO */ +# define STM32_NLCD 0 /* (0) No LCD */ +# define STM32_NUSBOTG 0 /* USB FS device, but no USB OTG FS/HS */ +# define STM32_NGPIO 37 /* GPIOA-F */ +# define STM32_NADC 2 /* (2) 12-bit ADC1-2 */ +# define STM32_NDAC 1 /* (1) 12-bit DAC1, 1 channel */ +# define STM32_NCAPSENSE 0 /* (0) No capacitive sensing channels */ +# define STM32_NCRC 1 /* (1) CRC calculation unit */ +# define STM32_NETHERNET 0 /* (0) No Ethernet MAC */ +# define STM32_NRNG 0 /* (0) No random number generator (RNG) */ +# define STM32_NDCMI 0 /* (0) No digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F302RB) || defined(CONFIG_ARCH_CHIP_STM32F302RC) +# define STM32_NFSMC 0 /* No FSMC */ +# define STM32_NATIM 1 /* (1) Advanced 16-bit timers with DMA: TIM1 (no TIM8) */ +# define STM32_NGTIM 6 /* (2) 16-bit general timers with DMA: TIM3 and TIM4 + * (1) 32-bit general timers with DMA: TIM2 + * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ +# define STM32_NGTIMNDMA 0 /* All timers have DMA */ + +# define STM32_NBTIM 1 /* (1) Basic timers: TIM6 (no TIM7) */ +# define STM32_NDMA 2 /* (2) DMA1 (7 channels) and DMA2 (5 channels) */ +# define STM32_NSPI 3 /* (3) SPI1-3 */ +# define STM32_NI2S 0 /* (0) No I2S */ +# define STM32_NUSART 5 /* (5) USART1-3, UART4-5 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 2 /* (2) I2C1-2 */ +# define STM32_NCAN 1 /* (1) CAN1 */ +# define STM32_NSDIO 0 /* (0) No SDIO */ +# define STM32_NLCD 0 /* (0) No LCD */ +# define STM32_NUSBOTG 0 /* USB FS device, but no USB OTG FS/HS */ +# define STM32_NGPIO 52 /* GPIOA-F */ +# define STM32_NADC 2 /* (2) 12-bit ADC1-2 */ +# define STM32_NDAC 1 /* (1) 12-bit DAC1, 1 channel */ +# define STM32_NCAPSENSE 0 /* (0) No capacitive sensing channels */ +# define STM32_NCRC 1 /* (1) CRC calculation unit */ +# define STM32_NETHERNET 0 /* (0) No Ethernet MAC */ +# define STM32_NRNG 0 /* (0) No random number generator (RNG) */ +# define STM32_NDCMI 0 /* (0) No digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F302VB) || defined(CONFIG_ARCH_CHIP_STM32F302VC) +# define STM32_NFSMC 0 /* No FSMC */ +# define STM32_NATIM 1 /* (1) Advanced 16-bit timers with DMA: TIM1 (no TIM8) */ +# define STM32_NGTIM 6 /* (2) 16-bit general timers with DMA: TIM3 and TIM4 + * (1) 32-bit general timers with DMA: TIM2 + * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ +# define STM32_NGTIMNDMA 0 /* All timers have DMA */ + +# define STM32_NBTIM 1 /* (1) Basic timers: TIM6 (no TIM7) */ +# define STM32_NDMA 2 /* (2) DMA1 (7 channels) and DMA2 (5 channels) */ +# define STM32_NSPI 3 /* (3) SPI1-3 */ +# define STM32_NI2S 0 /* (0) No I2S */ +# define STM32_NUSART 5 /* (5) USART1-3, UART4-5 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 2 /* (2) I2C1-2 */ +# define STM32_NCAN 1 /* (1) CAN1 */ +# define STM32_NSDIO 0 /* (0) No SDIO */ +# define STM32_NLCD 0 /* (0) No LCD */ +# define STM32_NUSBOTG 0 /* USB FS device, but no USB OTG FS/HS */ +# define STM32_NGPIO 87 /* GPIOA-F */ +# define STM32_NADC 2 /* (2) 12-bit ADC1-2 */ +# define STM32_NDAC 1 /* (1) 12-bit DAC1, 1 channel */ +# define STM32_NCAPSENSE 0 /* (0) No capacitive sensing channels */ +# define STM32_NCRC 1 /* (1) CRC calculation unit */ +# define STM32_NETHERNET 0 /* (0) No Ethernet MAC */ +# define STM32_NRNG 0 /* (0) No random number generator (RNG) */ +# define STM32_NDCMI 0 /* (0) No digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F303K6) || defined(CONFIG_ARCH_CHIP_STM32F303K8) +# define STM32_NFSMC 0 /* No FSMC */ +# define STM32_NATIM 1 /* (1) Advanced 16-bit timers with DMA: TIM1 */ +# define STM32_NGTIM 5 /* (1) 16-bit general timers with DMA: TIM3 + * (1) 32-bit general timers with DMA: TIM2 + * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ +# define STM32_NGTIMNDMA 0 /* All timers have DMA */ +# define STM32_NBTIM 2 /* (2) Basic timers: TIM6 and TIM7 */ +# define STM32_NDMA 1 /* (1) DMA1 (7 channels) */ +# define STM32_NSPI 1 /* (1) SPI1 */ +# define STM32_NI2S 0 /* (0) No I2S */ +# define STM32_NUSART 2 /* (2) USART1-2, no UARTs */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 1 /* (1) I2C1 */ +# define STM32_NCAN 1 /* (1) CAN1 */ +# define STM32_NSDIO 0 /* (0) No SDIO */ +# define STM32_NLCD 0 /* (0) No LCD */ +# define STM32_NUSBOTG 0 /* No USB OTG FS/HS */ +# define STM32_NGPIO 25 /* GPIOA-F */ +# define STM32_NADC 2 /* (2) 12-bit ADC1-2 */ +# define STM32_NDAC 3 /* (3) 12-bit DAC1-2, 3 channels */ +# define STM32_NCAPSENSE 0 /* (0) No capacitive sensing channels */ +# define STM32_NCRC 1 /* (1) CRC calculation unit */ +# define STM32_NETHERNET 0 /* (0) No Ethernet MAC */ +# define STM32_NRNG 0 /* (0) No random number generator (RNG) */ +# define STM32_NDCMI 0 /* (0) No digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F303C6) || defined(CONFIG_ARCH_CHIP_STM32F303C8) +# define STM32_NFSMC 0 /* No FSMC */ +# define STM32_NATIM 1 /* (1) Advanced 16-bit timers with DMA: TIM1 */ +# define STM32_NGTIM 5 /* (1) 16-bit general timers with DMA: TIM3 + * (1) 32-bit general timers with DMA: TIM2 + * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ +# define STM32_NGTIMNDMA 0 /* All timers have DMA */ +# define STM32_NBTIM 2 /* (2) Basic timers: TIM6 and TIM7 */ +# define STM32_NDMA 1 /* (1) DMA1 (7 channels) */ +# define STM32_NSPI 1 /* (1) SPI1 */ +# define STM32_NI2S 0 /* (0) No I2S */ +# define STM32_NUSART 3 /* (3) USART1-3, no UARTs */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 1 /* (1) I2C1 */ +# define STM32_NCAN 1 /* (1) CAN1 */ +# define STM32_NSDIO 0 /* (0) No SDIO */ +# define STM32_NLCD 0 /* (0) No LCD */ +# define STM32_NUSBOTG 0 /* No USB OTG FS/HS */ +# define STM32_NGPIO 37 /* GPIOA-F */ +# define STM32_NADC 2 /* (2) 12-bit ADC1-2 */ +# define STM32_NDAC 3 /* (3) 12-bit DAC1-2, 3 channels */ +# define STM32_NCAPSENSE 0 /* (0) No capacitive sensing channels */ +# define STM32_NCRC 1 /* (1) CRC calculation unit */ +# define STM32_NETHERNET 0 /* (0) No Ethernet MAC */ +# define STM32_NRNG 0 /* (0) No random number generator (RNG) */ +# define STM32_NDCMI 0 /* (0) No digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F303CB) || defined(CONFIG_ARCH_CHIP_STM32F303CC) +# define STM32_NFSMC 0 /* No FSMC */ +# define STM32_NATIM 2 /* (2) Advanced 16-bit timers with DMA: TIM1 and TIM8 */ +# define STM32_NGTIM 6 /* (2) 16-bit general timers with DMA: TIM3 and TIM4 + * (1) 32-bit general timers with DMA: TIM2 + * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ +# define STM32_NGTIMNDMA 0 /* All timers have DMA */ +# define STM32_NBTIM 2 /* (2) Basic timers: TIM6 and TIM7 */ +# define STM32_NDMA 2 /* (2) DMA1 (7 channels) and DMA2 (5 channels) */ +# define STM32_NSPI 3 /* (3) SPI1-3 */ +# define STM32_NI2S 2 /* (2) I2S1-2 (multiplexed with SPI2-3) */ +# define STM32_NUSART 3 /* (3) No UART1-3, no UARTs */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 2 /* (2) I2C1-2 */ +# define STM32_NCAN 1 /* (1) CAN1 */ +# define STM32_NSDIO 0 /* (0) No SDIO */ +# define STM32_NLCD 0 /* (0) No LCD */ +# define STM32_NUSBOTG 0 /* USB FS device, but no USB OTG FS/HS */ +# define STM32_NGPIO 37 /* GPIOA-F */ +# define STM32_NADC 4 /* (3) 12-bit ADC1-4 */ +# define STM32_NDAC 2 /* (2) 12-bit DAC1, 2 channels */ +# define STM32_NCAPSENSE 0 /* (0) No capacitive sensing channels */ +# define STM32_NCRC 1 /* (1) CRC calculation unit */ +# define STM32_NETHERNET 0 /* (0) No Ethernet MAC */ +# define STM32_NRNG 0 /* (0) No random number generator (RNG) */ +# define STM32_NDCMI 0 /* (0) No digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F303RB) || defined(CONFIG_ARCH_CHIP_STM32F303RC) +# define STM32_NFSMC 0 /* No FSMC */ +# define STM32_NATIM 2 /* (2) Advanced 16-bit timers with DMA: TIM1 and TIM8 */ +# define STM32_NGTIM 6 /* (2) 16-bit general timers with DMA: TIM3 and TIM4 + * (1) 32-bit general timers with DMA: TIM2 + * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ +# define STM32_NGTIMNDMA 0 /* All timers have DMA */ +# define STM32_NBTIM 2 /* (2) Basic timers: TIM6 and TIM7 */ +# define STM32_NDMA 2 /* (2) DMA1 (7 channels) and DMA2 (5 channels) */ +# define STM32_NSPI 3 /* (3) SPI1-3 */ +# define STM32_NI2S 2 /* (2) I2S1-2 (multiplexed with SPI2-3) */ +# define STM32_NUSART 5 /* (5) USART1-3, UART4-5 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 2 /* (2) I2C1-2 */ +# define STM32_NCAN 1 /* (1) CAN1 */ +# define STM32_NSDIO 0 /* (0) No SDIO */ +# define STM32_NLCD 0 /* (0) No LCD */ +# define STM32_NUSBOTG 0 /* USB FS device, but no USB OTG FS/HS */ +# define STM32_NGPIO 52 /* GPIOA-F */ +# define STM32_NADC 4 /* (3) 12-bit ADC1-4 */ +# define STM32_NDAC 2 /* (2) 12-bit DAC1, 2 channels */ +# define STM32_NCAPSENSE 0 /* (0) No capacitive sensing channels */ +# define STM32_NCRC 1 /* (1) CRC calculation unit */ +# define STM32_NETHERNET 0 /* (0) No Ethernet MAC */ +# define STM32_NRNG 0 /* (0) No random number generator (RNG) */ +# define STM32_NDCMI 0 /* (0) No digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F303RD) || defined(CONFIG_ARCH_CHIP_STM32F303RE) +# define STM32_NFSMC 0 /* No FSMC */ +# define STM32_NATIM 2 /* (2) Advanced 16-bit timers with DMA: TIM1 and TIM8 */ +# define STM32_NGTIM 6 /* (2) 16-bit general timers with DMA: TIM3 and TIM4 + * (1) 32-bit general timers with DMA: TIM2 + * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ +# define STM32_NGTIMNDMA 0 /* All timers have DMA */ +# define STM32_NBTIM 2 /* (2) Basic timers: TIM6 and TIM7 */ +# define STM32_NDMA 2 /* (2) DMA1 (7 channels) and DMA2 (5 channels) */ +# define STM32_NSPI 4 /* (4) SPI1-4 */ +# define STM32_NI2S 2 /* (2) I2S1-2 (multiplexed with SPI2-3) */ +# define STM32_NUSART 5 /* (5) USART1-3, UART4-5 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 3 /* (2) I2C1-3 */ +# define STM32_NCAN 1 /* (1) CAN1 */ +# define STM32_NSDIO 0 /* (0) No SDIO */ +# define STM32_NLCD 0 /* (0) No LCD */ +# define STM32_NUSBOTG 0 /* USB FS device, but no USB OTG FS/HS */ +# define STM32_NGPIO 51 /* GPIOA-F */ +# define STM32_NADC 4 /* (4) 12-bit ADC1-4 */ +# define STM32_NDAC 2 /* (2) 12-bit DAC1, 2 channels */ +# define STM32_NCAPSENSE 0 /* (0) No capacitive sensing channels */ +# define STM32_NCRC 1 /* (1) CRC calculation unit */ +# define STM32_NETHERNET 0 /* (0) No Ethernet MAC */ +# define STM32_NRNG 0 /* (0) No random number generator (RNG) */ +# define STM32_NDCMI 0 /* (0) No digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F303VB) || defined(CONFIG_ARCH_CHIP_STM32F303VC) +# define STM32_NFSMC 0 /* No FSMC */ +# define STM32_NATIM 2 /* (2) Advanced 16-bit timers with DMA: TIM1 and TIM8 */ +# define STM32_NGTIM 6 /* (2) 16-bit general timers with DMA: TIM3 and TIM4 + * (1) 32-bit general timers with DMA: TIM2 + * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ +# define STM32_NGTIMNDMA 0 /* All timers have DMA */ +# define STM32_NBTIM 2 /* (2) Basic timers: TIM6 and TIM7 */ +# define STM32_NDMA 2 /* (2) DMA1 (7 channels) and DMA2 (5 channels) */ +# define STM32_NSPI 3 /* (3) SPI1-3 */ +# define STM32_NI2S 2 /* (2) I2S1-2 (multiplexed with SPI2-3) */ +# define STM32_NUSART 5 /* (5) USART1-3, UART4-5 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 2 /* (2) I2C1-2 */ +# define STM32_NCAN 1 /* (1) CAN1 */ +# define STM32_NSDIO 0 /* (0) No SDIO */ +# define STM32_NLCD 0 /* (0) No LCD */ +# define STM32_NUSBOTG 0 /* USB FS device, but no USB OTG FS/HS */ +# define STM32_NGPIO 87 /* GPIOA-F */ +# define STM32_NADC 4 /* (3) 12-bit ADC1-4 */ +# define STM32_NDAC 2 /* (2) 12-bit DAC1, 2 channels */ +# define STM32_NCAPSENSE 0 /* (0) No capacitive sensing channels */ +# define STM32_NCRC 1 /* (1) CRC calculation unit */ +# define STM32_NETHERNET 0 /* (0) No Ethernet MAC */ +# define STM32_NRNG 0 /* (0) No random number generator (RNG) */ +# define STM32_NDCMI 0 /* (0) No digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F303RD) || defined(CONFIG_ARCH_CHIP_STM32F303RE) +# define STM32_NFSMC 0 /* No FSMC */ +# define STM32_NATIM 2 /* (2) Advanced 16-bit timers with DMA: TIM1 and TIM8 */ +# define STM32_NGTIM 6 /* (5) 16-bit general timers + * (1) 32-bit general timers */ +# define STM32_NGTIMNDMA 0 /* All timers have DMA */ +# define STM32_NBTIM 2 /* (2) Basic timers: TIM6 and TIM7 */ +# define STM32_NDMA 2 /* (2) DMA1 (7 channels) and DMA2 (5 channels) */ +# define STM32_NSPI 4 /* (4) SPI1-4 */ +# define STM32_NI2S 2 /* (2) I2S1-2 (multiplexed with SPI2-3) */ +# define STM32_NUSART 5 /* (5) USART1-3, UART4-5 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 3 /* (3) I2C1-3 */ +# define STM32_NCAN 1 /* (1) CAN1 */ +# define STM32_NSDIO 0 /* (0) No SDIO */ +# define STM32_NLCD 0 /* (0) No LCD */ +# define STM32_NUSBOTG 0 /* USB FS device, but no USB OTG FS/HS */ +# define STM32_NGPIO 51 /* GPIOA-F */ +# define STM32_NADC 4 /* (4) 12-bit ADC1-4 */ +# define STM32_NDAC 2 /* (2) 12-bit DAC1, 2 channels */ +# define STM32_NCAPSENSE 18 /* (18) No capacitive sensing channels */ +# define STM32_NCRC 1 /* (1) CRC calculation unit */ +# define STM32_NETHERNET 0 /* (0) No Ethernet MAC */ +# define STM32_NRNG 0 /* (0) No random number generator (RNG) */ +# define STM32_NDCMI 0 /* (0) No digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F303VD) || defined(CONFIG_ARCH_CHIP_STM32F303VE) +# define STM32_NFSMC 0 /* No FSMC */ +# define STM32_NATIM 3 /* (3) Advanced 16-bit timers with DMA: TIM1, TIM8 and TIM20 */ +# define STM32_NGTIM 6 /* (5) 16-bit general timers + * (1) 32-bit general timers */ +# define STM32_NGTIMNDMA 0 /* All timers have DMA */ +# define STM32_NBTIM 2 /* (2) Basic timers: TIM6 and TIM7 */ +# define STM32_NDMA 2 /* (2) DMA1 (7 channels) and DMA2 (5 channels) */ +# define STM32_NSPI 4 /* (4) SPI1-4 */ +# define STM32_NI2S 2 /* (2) I2S1-2 (multiplexed with SPI2-3) */ +# define STM32_NUSART 5 /* (5) USART1-3, UART4-5 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 3 /* (3) I2C1-3 */ +# define STM32_NCAN 1 /* (1) CAN1 */ +# define STM32_NSDIO 0 /* (0) No SDIO */ +# define STM32_NLCD 0 /* (0) No LCD */ +# define STM32_NUSBOTG 0 /* USB FS device, but no USB OTG FS/HS */ +# define STM32_NGPIO 84 /* GPIOA-F (depends on package) */ +# define STM32_NADC 4 /* (4) 12-bit ADC1-4 */ +# define STM32_NDAC 2 /* (2) 12-bit DAC1, 2 channels */ +# define STM32_NCAPSENSE 24 /* (24) No capacitive sensing channels */ +# define STM32_NCRC 1 /* (1) CRC calculation unit */ +# define STM32_NETHERNET 0 /* (0) No Ethernet MAC */ +# define STM32_NRNG 0 /* (0) No random number generator (RNG) */ +# define STM32_NDCMI 0 /* (0) No digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F303ZD) || defined(CONFIG_ARCH_CHIP_STM32F303ZE) +# define STM32_NFSMC 0 /* No FSMC */ +# define STM32_NATIM 3 /* (3) Advanced 16-bit timers with DMA: TIM1, TIM8 and TIM20 */ +# define STM32_NGTIM 6 /* (5) 16-bit general timers + * (1) 32-bit general timers */ +# define STM32_NGTIMNDMA 0 /* All timers have DMA */ +# define STM32_NBTIM 2 /* (2) Basic timers: TIM6 and TIM7 */ +# define STM32_NDMA 2 /* (2) DMA1 (7 channels) and DMA2 (5 channels) */ +# define STM32_NSPI 4 /* (4) SPI1-4 */ +# define STM32_NI2S 2 /* (2) I2S1-2 (multiplexed with SPI2-3) */ +# define STM32_NUSART 5 /* (5) USART1-3, UART4-5 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 3 /* (3) I2C1-3 */ +# define STM32_NCAN 1 /* (1) CAN1 */ +# define STM32_NSDIO 0 /* (0) No SDIO */ +# define STM32_NLCD 0 /* (0) No LCD */ +# define STM32_NUSBOTG 0 /* USB FS device, but no USB OTG FS/HS */ +# define STM32_NGPIO 115 /* GPIOA-F */ +# define STM32_NADC 4 /* (4) 12-bit ADC1-4 */ +# define STM32_NDAC 2 /* (2) 12-bit DAC1, 2 channels */ +# define STM32_NCAPSENSE 24 /* (24) No capacitive sensing channels */ +# define STM32_NCRC 1 /* (1) CRC calculation unit */ +# define STM32_NETHERNET 0 /* (0) No Ethernet MAC */ +# define STM32_NRNG 0 /* (0) No random number generator (RNG) */ +# define STM32_NDCMI 0 /* (0) No digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F334K4) || defined(CONFIG_ARCH_CHIP_STM32F334K6) || defined(CONFIG_ARCH_CHIP_STM32F334K8) +# define STM32_NFSMC 0 /* No FSMC */ +# define STM32_HRTIM 1 /* (1) High-resolution timer 16-bit, 10 channels: HRTIM1 */ +# define STM32_NATIM 1 /* (1) Advanced 16-bit timers with DMA: TIM1*/ +# define STM32_NGTIM 5 /* (1) 16-bit general timers with DMA: TIM3 + * (1) 32-bit general timers with DMA: TIM2 + * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ +# define STM32_NGTIMNDMA 0 /* All timers have DMA */ +# define STM32_NBTIM 2 /* (2) Basic timers: TIM6 and TIM7 */ +# define STM32_NDMA 1 /* (1) DMA1 (7 channels) */ +# define STM32_NSPI 1 /* (1) SPI1 */ +# define STM32_NI2S 0 /* (0) No I2S1 */ +# define STM32_NUSART 2 /* (2) USART1-2 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 1 /* (1) I2C1 */ +# define STM32_NCAN 1 /* (1) CAN1 */ +# define STM32_NSDIO 0 /* (0) No SDIO */ +# define STM32_NLCD 0 /* (0) No LCD */ +# define STM32_NUSBOTG 0 /* (0) No USB */ +# define STM32_NGPIO 25 /* GPIOA-F */ +# define STM32_NADC 2 /* (2) 12-bit ADC1-2 */ +# define STM32_NDAC 3 /* (3) 12-bit DAC1-2, 3 channels */ +# define STM32_NCMP 2 /* (2) Ultra-fast analog comparators: COMP2 and COMP4 */ +# define STM32_NPGA 1 /* (1) Operational amplifiers: OPAMP */ +# define STM32_NCAPSENSE 14 /* (14) Capacitive sensing channels */ +# define STM32_NCRC 1 /* (1) CRC calculation unit */ +# define STM32_NETHERNET 0 /* (0) No Ethernet MAC */ +# define STM32_NRNG 0 /* (0) No random number generator (RNG) */ +# define STM32_NDCMI 0 /* (0) No digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F334C4) || defined(CONFIG_ARCH_CHIP_STM32F334C6) || defined(CONFIG_ARCH_CHIP_STM32F334C8) +# define STM32_NFSMC 0 /* No FSMC */ +# define STM32_HRTIM 1 /* (1) High-resolution timer 16-bit, 10 channels: HRTIM1 */ +# define STM32_NATIM 1 /* (1) Advanced 16-bit timers with DMA: TIM1*/ +# define STM32_NGTIM 5 /* (1) 16-bit general timers with DMA: TIM3 + * (1) 32-bit general timers with DMA: TIM2 + * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ +# define STM32_NGTIMNDMA 0 /* All timers have DMA */ +# define STM32_NBTIM 2 /* (2) Basic timers: TIM6 and TIM7 */ +# define STM32_NDMA 1 /* (1) DMA1 (7 channels) */ +# define STM32_NSPI 1 /* (1) SPI1 */ +# define STM32_NI2S 0 /* (0) No I2S1 */ +# define STM32_NUSART 3 /* (3) USART1-3 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 1 /* (1) I2C1 */ +# define STM32_NCAN 1 /* (1) CAN1 */ +# define STM32_NSDIO 0 /* (0) No SDIO */ +# define STM32_NLCD 0 /* (0) No LCD */ +# define STM32_NUSBOTG 0 /* (0) No USB */ +# define STM32_NGPIO 37 /* GPIOA-F */ +# define STM32_NADC 2 /* (2) 12-bit ADC1-2 */ +# define STM32_NDAC 3 /* (3) 12-bit DAC1-2, 3 channels */ +# define STM32_NCMP 3 /* (3) Ultra-fast analog comparators: COMP2, COMP4 and COMP6 */ +# define STM32_NPGA 1 /* (1) Operational amplifiers: OPAMP */ +# define STM32_NCAPSENSE 17 /* (17) Capacitive sensing channels */ +# define STM32_NCRC 1 /* (1) CRC calculation unit */ +# define STM32_NETHERNET 0 /* (0) No Ethernet MAC */ +# define STM32_NRNG 0 /* (0) No random number generator (RNG) */ +# define STM32_NDCMI 0 /* (0) No digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F334R4) || defined(CONFIG_ARCH_CHIP_STM32F334R6) || defined(CONFIG_ARCH_CHIP_STM32F334R8) +# define STM32_NFSMC 0 /* No FSMC */ +# define STM32_HRTIM 1 /* (1) High-resolution timer 16-bit, 10 channels: HRTIM1 */ +# define STM32_NATIM 1 /* (1) Advanced 16-bit timers with DMA: TIM1*/ +# define STM32_NGTIM 5 /* (1) 16-bit general timers with DMA: TIM3 + * (1) 32-bit general timers with DMA: TIM2 + * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ +# define STM32_NGTIMNDMA 0 /* All timers have DMA */ +# define STM32_NBTIM 2 /* (2) Basic timers: TIM6 and TIM7 */ +# define STM32_NDMA 1 /* (1) DMA1 (7 channels) */ +# define STM32_NSPI 1 /* (1) SPI1 */ +# define STM32_NI2S 0 /* (0) No I2S1 */ +# define STM32_NUSART 3 /* (3) USART1-3 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 1 /* (1) I2C1 */ +# define STM32_NCAN 1 /* (1) CAN1 */ +# define STM32_NSDIO 0 /* (0) No SDIO */ +# define STM32_NLCD 0 /* (0) No LCD */ +# define STM32_NUSBOTG 0 /* (0) No USB */ +# define STM32_NGPIO 51 /* GPIOA-F */ +# define STM32_NADC 2 /* (2) 12-bit ADC1-2 */ +# define STM32_NDAC 3 /* (3) 12-bit DAC1-2, 3 channels */ +# define STM32_NCMP 3 /* (3) Ultra-fast analog comparators: COMP2, COMP4 and COMP6 */ +# define STM32_NPGA 1 /* (1) Operational amplifiers: OPAMP */ +# define STM32_NCAPSENSE 18 /* (18) Capacitive sensing channels */ +# define STM32_NCRC 1 /* (1) CRC calculation unit */ +# define STM32_NETHERNET 0 /* (0) No Ethernet MAC */ +# define STM32_NRNG 0 /* (0) No random number generator (RNG) */ +# define STM32_NDCMI 0 /* (0) No digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F373C8) || defined(CONFIG_ARCH_CHIP_STM32F373CB) || defined(CONFIG_ARCH_CHIP_STM32F373CC) +# define STM32_NFSMC 0 /* No FSMC */ +# define STM32_NATIM 0 /* (0) Advanced 16-bit timers with DMA: */ +# define STM32_NGTIM 8 /* (3) 16-bit general timers with DMA: TIM3, TIM4 and TIM19 + * (2) 32-bit general timers with DMA: TIM2 and TIM5 + * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ +# define STM32_NGTIMNDMA 3 /* (3) 16-bit general timers count-up timers without DMA: TIM12-14 */ +# define STM32_NBTIM 3 /* (3) Basic timers: TIM6, TIM7 and TIM18 */ +# define STM32_NDMA 2 /* (2) DMA1 (7 channels) and DMA2 (5 channels) */ +# define STM32_NSPI 3 /* (3) SPI1-3 */ +# define STM32_NI2S 3 /* (3) I2S1-2 (multiplexed with SPI1-3) */ +# define STM32_NUSART 3 /* (3) USART1-3 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 2 /* (2) I2C1-2 */ +# define STM32_NCAN 1 /* (1) CAN1 */ +# define STM32_NSDIO 0 /* (0) No SDIO */ +# define STM32_NLCD 0 /* (0) No LCD */ +# define STM32_NUSBOTG 0 /* USB FS device, but no USB OTG FS/HS */ +# define STM32_NGPIO 87 /* GPIOA-F */ +# define STM32_NADC 1 /* (1) 12-bit ADC1 */ +# define STM32_NSDADC 3 /* (3) 16-bit SDADC1-3 */ +# define STM32_NDAC 3 /* (3) 12-bit DAC1-2, 3 channels */ +# define STM32_NCAPSENSE 0 /* (0) No capacitive sensing channels */ +# define STM32_NCRC 1 /* (1) CRC calculation unit */ +# define STM32_NETHERNET 0 /* (0) No Ethernet MAC */ +# define STM32_NRNG 0 /* (0) No random number generator (RNG) */ +# define STM32_NDCMI 0 /* (0) No digital camera interface (DCMI) */ + +/* STM23 F4 Family **********************************************************/ + +/* STM32F01xB/C Family Differences: + * + * PART PACKAGE FLASH SDIO ADC Channels + * ----------- ---------------- ----- ---- ------------ + * STM32F401CB WLCSP49/UFQFPN48 128Kb No 10 + * STM32F401RB LQFP64 128Kb Yes 16 + * STM32F401VB UFBGA100/LQFP100 128Kb Yes 16 + * STM32F401CC WLCSP49/UFQFPN48 256Kb No 10 + * STM32F401RC LQFP64 256Kb Yes 16 + * STM32F401VC UFBGA100/LQFP100 256Kb Yes 16 + */ + +#else +# error "Unsupported STM32 chip" +#endif + +/* Peripheral IP versions ***************************************************/ + +/* Peripheral IP versions are invariant and should be decided here, not in + * Kconfig. + * + * REVISIT: Currently only SPI IP version is handled here, with others being + * handled in Kconfig. Those others need to be gradually refactored + * and resolved here. + */ + +#if defined(CONFIG_STM32_STM32F30XX) +# define STM32_HAVE_IP_SPI_V3 + +#elif defined(CONFIG_STM32_STM32F33XX) +# define STM32_HAVE_IP_SPI_V1 + +#elif defined(CONFIG_STM32_STM32F37XX) +# define STM32_HAVE_IP_SPI_V3 + +#else +# error "Did not resolve peripheral IP versions!" +#endif + +/* NVIC priority levels *****************************************************/ + +#define NVIC_SYSH_PRIORITY_MIN 0xf0 /* All bits set in minimum priority */ +#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */ +#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */ +#define NVIC_SYSH_PRIORITY_STEP 0x10 /* Four bits of interrupt priority used */ + +#endif /* __ARCH_ARM_INCLUDE_STM32F3_CHIP_H */ diff --git a/arch/arm/include/stm32f3/irq.h b/arch/arm/include/stm32f3/irq.h new file mode 100644 index 0000000000000..91c056320ef9b --- /dev/null +++ b/arch/arm/include/stm32f3/irq.h @@ -0,0 +1,84 @@ +/**************************************************************************** + * arch/arm/include/stm32f3/irq.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* This file should never be included directly but, rather, + * only indirectly through nuttx/irq.h + */ + +#ifndef __ARCH_ARM_INCLUDE_STM32F3_IRQ_H +#define __ARCH_ARM_INCLUDE_STM32F3_IRQ_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include + +/**************************************************************************** + * Pre-processor Prototypes + ****************************************************************************/ + +/* IRQ numbers. + * The IRQ number corresponds vector number and hence map directly to + * bits in the NVIC. This does, however, waste several words of memory in + * the IRQ to handle mapping tables. + */ + +/* Processor Exceptions (vectors 0-15) */ + +#define STM32_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */ + /* Vector 0: Reset stack pointer value */ + /* Vector 1: Reset (not handler as an IRQ) */ +#define STM32_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */ +#define STM32_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */ +#define STM32_IRQ_MEMFAULT (4) /* Vector 4: Memory management (MPU) */ +#define STM32_IRQ_BUSFAULT (5) /* Vector 5: Bus fault */ +#define STM32_IRQ_USAGEFAULT (6) /* Vector 6: Usage fault */ +#define STM32_IRQ_SVCALL (11) /* Vector 11: SVC call */ +#define STM32_IRQ_DBGMONITOR (12) /* Vector 12: Debug Monitor */ + /* Vector 13: Reserved */ +#define STM32_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */ +#define STM32_IRQ_SYSTICK (15) /* Vector 15: System tick */ + +/* External interrupts (vectors >= 16). + * These definitions are chip-specific + */ + +#define STM32_IRQ_FIRST (16) /* Vector number of the first external interrupt */ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#if defined(CONFIG_STM32_STM32F30XX) +# include +#elif defined(CONFIG_STM32_STM32F33XX) +# include +#elif defined(CONFIG_STM32_STM32F37XX) +# include +#else +# error "Unsupported STM32F3 chip" +#endif + +#endif /* __ARCH_ARM_INCLUDE_STM32F3_IRQ_H */ diff --git a/arch/arm/include/stm32/stm32f30xxx_irq.h b/arch/arm/include/stm32f3/stm32f30xxx_irq.h similarity index 93% rename from arch/arm/include/stm32/stm32f30xxx_irq.h rename to arch/arm/include/stm32f3/stm32f30xxx_irq.h index 32c5dc0d55767..b5a5612cfa2ae 100644 --- a/arch/arm/include/stm32/stm32f30xxx_irq.h +++ b/arch/arm/include/stm32f3/stm32f30xxx_irq.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/include/stm32/stm32f30xxx_irq.h + * arch/arm/include/stm32f3/stm32f30xxx_irq.h * * SPDX-License-Identifier: Apache-2.0 * @@ -43,7 +43,7 @@ * memory in the IRQ to handle mapping tables. * * Processor Exceptions (vectors 0-15). These common definitions can be - * found in nuttx/arch/arm/include/stm32/irq.h + * found in nuttx/arch/arm/include/stm32f3/irq.h * * External interrupts (vectors >= 16) */ @@ -153,31 +153,4 @@ #define STM32_IRQ_NEXTINTS (82) #define NR_IRQS (STM32_IRQ_FIRST + STM32_IRQ_NEXTINTS) -/**************************************************************************** - * Public Types - ****************************************************************************/ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -#ifndef __ASSEMBLY__ -#ifdef __cplusplus -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -#undef EXTERN -#ifdef __cplusplus -} -#endif -#endif - #endif /* __ARCH_ARM_INCLUDE_STM32_STM32F30XXX_IRQ_H */ diff --git a/arch/arm/include/stm32/stm32f33xxx_irq.h b/arch/arm/include/stm32f3/stm32f33xxx_irq.h similarity index 92% rename from arch/arm/include/stm32/stm32f33xxx_irq.h rename to arch/arm/include/stm32f3/stm32f33xxx_irq.h index bb6e9f84cc9cb..4dde150c30d89 100644 --- a/arch/arm/include/stm32/stm32f33xxx_irq.h +++ b/arch/arm/include/stm32f3/stm32f33xxx_irq.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/include/stm32/stm32f33xxx_irq.h + * arch/arm/include/stm32f3/stm32f33xxx_irq.h * * SPDX-License-Identifier: Apache-2.0 * @@ -43,7 +43,7 @@ * memory in the IRQ to handle mapping tables. * * Processor Exceptions (vectors 0-15). These common definitions can be - * found in nuttx/arch/arm/include/stm32/irq.h + * found in nuttx/arch/arm/include/stm32f3/irq.h * * External interrupts (vectors >= 16) */ @@ -143,31 +143,4 @@ #define STM32_IRQ_NEXTINTS (82) #define NR_IRQS (STM32_IRQ_FIRST + STM32_IRQ_NEXTINTS) -/**************************************************************************** - * Public Types - ****************************************************************************/ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -#ifndef __ASSEMBLY__ -#ifdef __cplusplus -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -#undef EXTERN -#ifdef __cplusplus -} -#endif -#endif - #endif /* __ARCH_ARM_INCLUDE_STM32F30XXX_IRQ_H */ diff --git a/arch/arm/include/stm32/stm32f37xxx_irq.h b/arch/arm/include/stm32f3/stm32f37xxx_irq.h similarity index 92% rename from arch/arm/include/stm32/stm32f37xxx_irq.h rename to arch/arm/include/stm32f3/stm32f37xxx_irq.h index cf052a8493a5a..445fa0c657bf4 100644 --- a/arch/arm/include/stm32/stm32f37xxx_irq.h +++ b/arch/arm/include/stm32f3/stm32f37xxx_irq.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/include/stm32/stm32f37xxx_irq.h + * arch/arm/include/stm32f3/stm32f37xxx_irq.h * * SPDX-License-Identifier: Apache-2.0 * @@ -43,7 +43,7 @@ * memory in the IRQ to handle mapping tables. * * Processor Exceptions (vectors 0-15). These common definitions can be - * found in nuttx/arch/arm/include/stm32/irq.h + * found in nuttx/arch/arm/include/stm32f3/irq.h * * External interrupts (vectors >= 16) */ @@ -138,31 +138,4 @@ #define STM32_IRQ_NEXTINTS (82) #define NR_IRQS (STM32_IRQ_FIRST + STM32_IRQ_NEXTINTS) -/**************************************************************************** - * Public Types - ****************************************************************************/ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -#ifndef __ASSEMBLY__ -#ifdef __cplusplus -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -#undef EXTERN -#ifdef __cplusplus -} -#endif -#endif - #endif /* __ARCH_ARM_INCLUDE_STM32F30XXX_IRQ_H */ diff --git a/arch/arm/include/stm32f4/chip.h b/arch/arm/include/stm32f4/chip.h new file mode 100644 index 0000000000000..796e1590ab464 --- /dev/null +++ b/arch/arm/include/stm32f4/chip.h @@ -0,0 +1,864 @@ +/**************************************************************************** + * arch/arm/include/stm32f4/chip.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_INCLUDE_STM32F4_CHIP_H +#define __ARCH_ARM_INCLUDE_STM32F4_CHIP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Prototypes + ****************************************************************************/ + +/* Get customizations for each supported chip and provide alternate function + * pin-mapping + * + * NOTE: Each GPIO pin may serve either for general purpose I/O or for a + * special alternate function (such as USART, CAN, USB, SDIO, etc.). That + * particular pin-mapping will depend on the package and STM32 family. If + * you are incorporating a new STM32 chip into NuttX, you will need to add + * the pin-mapping to a header file and to include that header file below. + * The chip-specific pin-mapping is defined in the chip datasheet. + */ + +#if defined(CONFIG_ARCH_CHIP_STM32F401CB) || defined(CONFIG_ARCH_CHIP_STM32F401RB) || \ + defined(CONFIG_ARCH_CHIP_STM32F401VB) || defined(CONFIG_ARCH_CHIP_STM32F401CC) || \ + defined(CONFIG_ARCH_CHIP_STM32F401RC) || defined(CONFIG_ARCH_CHIP_STM32F401VC) +# define STM32_NFSMC 0 /* No FSMC */ +# define STM32_NATIM 1 /* One advanced timers TIM1 */ +# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA + * 32-bit general timers TIM2 and 5 with DMA */ +# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */ +# define STM32_NBTIM 0 /* No basic timers */ +# define STM32_NDMA 2 /* DMA1-2 with 8 streams each*/ +# define STM32_NSPI 3 /* SPI1-3 */ +# define STM32_NI2S 2 /* I2S2-3 (multiplexed with SPI2-3) */ +# define STM32_NUSART 6 /* Actually only 3: USART1, 2 and 6 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 3 /* I2C1-3 */ +# define STM32_NCAN 0 /* No CAN */ +# if defined(CONFIG_ARCH_CHIP_STM32F401CB) || defined(CONFIG_ARCH_CHIP_STM32F401CC) +# define STM32_NSDIO 0 /* No SDIO interface */ +# else +# define STM32_NSDIO 1 /* One SDIO interface */ +# endif +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 1 /* USB OTG FS (only) */ +# define STM32_NGPIO 50 /* GPIOA-H */ +# define STM32_NADC 1 /* One 12-bit ADC1, 10 or 16 channels */ +# define STM32_NDAC 0 /* No DAC */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* No CRC */ +# define STM32_NETHERNET 0 /* No Ethernet MAC */ +# define STM32_NRNG 0 /* No Random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + +/* STM32F01xD/E Family Differences: + * + * PART PACKAGE FLASH SDIO ADC Channels + * ----------- ---------------- ----- ---- ------------ + * STM32F401CD WLCSP49/UFQFPN48 384Kb No 10 + * STM32F401RD LQFP64 384Kb Yes 16 + * STM32F401VD UFBGA100/LQFP100 384Kb Yes 16 + * STM32F401CE WLCSP49/UFQFPN48 512Kb No 10 + * STM32F401RE LQFP64 512Kb Yes 16 + * STM32F401VE UFBGA100/LQFP100 512Kb Yes 16 + */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F401CD) || defined(CONFIG_ARCH_CHIP_STM32F401RD) || \ + defined(CONFIG_ARCH_CHIP_STM32F401VD) || defined(CONFIG_ARCH_CHIP_STM32F401CE) || \ + defined(CONFIG_ARCH_CHIP_STM32F401RE) || defined(CONFIG_ARCH_CHIP_STM32F401VE) +# define STM32_NFSMC 0 /* No FSMC */ +# define STM32_NATIM 1 /* One advanced timers TIM1 */ +# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA + * 32-bit general timers TIM2 and 5 with DMA */ +# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */ +# define STM32_NBTIM 0 /* No basic timers */ +# define STM32_NDMA 2 /* DMA1-2 with 8 streams each*/ +# define STM32_NSPI 4 /* SPI1-4 */ +# define STM32_NI2S 2 /* I2S2-3 (multiplexed with SPI2-3) */ +# define STM32_NUSART 6 /* Actually only 3: USART1, 2 and 6 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 3 /* I2C1-3 */ +# define STM32_NCAN 0 /* No CAN */ +# if defined(CONFIG_ARCH_CHIP_STM32F401CD) || defined(CONFIG_ARCH_CHIP_STM32F401CE) +# define STM32_NSDIO 0 /* No SDIO interface */ +# else +# define STM32_NSDIO 1 /* One SDIO interface */ +# endif +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 1 /* USB OTG FS (only) */ +# define STM32_NGPIO 50 /* GPIOA-H */ +# define STM32_NADC 1 /* One 12-bit ADC1, 10 or 16 channels */ +# define STM32_NDAC 0 /* No DAC */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* No CRC */ +# define STM32_NETHERNET 0 /* No Ethernet MAC */ +# define STM32_NRNG 0 /* No Random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F410RB) /* LQFP64 package, 512Kb FLASH, 96KiB SRAM */ +# define STM32_NFSMC 0 /* No FSMC */ +# define STM32_NATIM 1 /* One advanced timers TIM1 */ +# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA + * 32-bit general timers TIM2 and 5 with DMA */ +# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */ +# define STM32_NBTIM 0 /* No basic timers */ +# define STM32_NDMA 2 /* DMA1-2 with 8 streams each*/ +# define STM32_NSPI 3 /* SPI1-4 */ +# define STM32_NI2S 0 /* I2S1-2 (multiplexed with SPI2-3) */ +# define STM32_NUSART 3 /* Actually only 3: USART1, 2 and 6 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 3 /* I2C1-3 */ +# define STM32_NCAN 0 /* No CAN */ +# define STM32_NSDIO 0 /* One SDIO interface */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 0 /* USB OTG FS (only) */ +# define STM32_NGPIO 50 /* GPIOA-H */ +# define STM32_NADC 1 /* One 12-bit ADC1, 16 channels */ +# define STM32_NDAC 1 /* 12-bit DAC1, 1 channel */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* No CRC */ +# define STM32_NETHERNET 0 /* No Ethernet MAC */ +# define STM32_NRNG 1 /* No Random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F411CE) /* LQFP64 package, 512Kb FLASH, 128KiB SRAM */ +# define STM32_NFSMC 0 /* No FSMC */ +# define STM32_NATIM 1 /* One advanced timers TIM1 */ +# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA + * 32-bit general timers TIM2 and 5 with DMA */ +# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */ +# define STM32_NBTIM 0 /* No basic timers */ +# define STM32_NDMA 2 /* DMA1-2 with 8 streams each*/ +# define STM32_NSPI 5 /* SPI1-5 */ +# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ +# define STM32_NUSART 6 /* Actually only 3: USART1, 2 and 6 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 3 /* I2C1-3 */ +# define STM32_NCAN 0 /* No CAN */ +# define STM32_NSDIO 1 /* One SDIO interface */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 1 /* USB OTG FS (only) */ +# define STM32_NGPIO 50 /* GPIOA-H */ +# define STM32_NADC 1 /* One 12-bit ADC1, 16 channels */ +# define STM32_NDAC 0 /* No DAC */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* No CRC */ +# define STM32_NETHERNET 0 /* No Ethernet MAC */ +# define STM32_NRNG 0 /* No Random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F411RE) /* LQFP64 package, 512Kb FLASH, 128KiB SRAM */ +# define STM32_NFSMC 0 /* No FSMC */ +# define STM32_NATIM 1 /* One advanced timers TIM1 */ +# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA + * 32-bit general timers TIM2 and 5 with DMA */ +# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */ +# define STM32_NBTIM 0 /* No basic timers */ +# define STM32_NDMA 2 /* DMA1-2 with 8 streams each*/ +# define STM32_NSPI 5 /* SPI1-5 */ +# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ +# define STM32_NUSART 6 /* Actually only 3: USART1, 2 and 6 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 3 /* I2C1-3 */ +# define STM32_NCAN 0 /* No CAN */ +# define STM32_NSDIO 1 /* One SDIO interface */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 1 /* USB OTG FS (only) */ +# define STM32_NGPIO 50 /* GPIOA-H */ +# define STM32_NADC 1 /* One 12-bit ADC1, 16 channels */ +# define STM32_NDAC 0 /* No DAC */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* No CRC */ +# define STM32_NETHERNET 0 /* No Ethernet MAC */ +# define STM32_NRNG 0 /* No Random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F411VE) /* 100 pin LQFP/BGA package, 512Kb FLASH, 128KiB SRAM */ +# define STM32_NFSMC 0 /* No FSMC */ +# define STM32_NATIM 1 /* One advanced timers TIM1 */ +# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA + * 32-bit general timers TIM2 and 5 with DMA */ +# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */ +# define STM32_NBTIM 0 /* No basic timers */ +# define STM32_NDMA 2 /* DMA1-2 with 8 streams each*/ +# define STM32_NSPI 5 /* SPI1-5 */ +# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ +# define STM32_NUSART 6 /* Actually only 3: USART1, 2 and 6 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 3 /* I2C1-3 */ +# define STM32_NCAN 0 /* No CAN */ +# define STM32_NSDIO 1 /* One SDIO interface */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 1 /* USB OTG FS (only) */ +# define STM32_NGPIO 81 /* GPIOA-H */ +# define STM32_NADC 1 /* One 12-bit ADC1, 16 channels */ +# define STM32_NDAC 0 /* No DAC */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* No CRC */ +# define STM32_NETHERNET 0 /* No Ethernet MAC */ +# define STM32_NRNG 0 /* No Random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F412CE) /* UFQFPN48 package, 512Kb FLASH, 256KiB SRAM */ +# define STM32_NFSMC 1 /* FSMC */ +# define STM32_NATIM 2 /* Two advanced timers TIM1 and TIM8 */ +# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA + * 32-bit general timers TIM2 and 5 with DMA */ +# define STM32_NGTIMNDMA 4 /* 16-bit general timers 9, 12, 13, and 14 without DMA */ +# define STM32_NBTIM 0 /* 2 basic timers TIM6 and TIM7 */ +# define STM32_NDMA 2 /* DMA1-2 with 8 streams each*/ +# define STM32_NSPI 5 /* SPI1-5 */ +# define STM32_NI2S 3 /* I2S1-3 */ +# define STM32_NUSART 4 /* USART1, 2, 3 and 6 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 3 /* I2C1-3 */ +# define STM32_NCAN 2 /* 2 CAN */ +# define STM32_NSDIO 1 /* One SDIO interface */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 1 /* USB OTG FS (only) */ +# define STM32_NGPIO 34 /* GPIOA-B (sans PB11) and 3 Bits of C */ +# define STM32_NADC 1 /* One 12-bit ADC1, 16 channels */ +# define STM32_NDAC 0 /* No DAC */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NETHERNET 0 /* No Ethernet MAC */ +# define STM32_NRNG 1 /* Random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F412ZG) /* 144 pin LQFP package, 1MB FLASH, 256KiB SRAM */ +# define STM32_NFSMC 1 /* FSMC */ +# define STM32_NATIM 2 /* Two advanced timers TIM1 and TIM8 */ +# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA + * 32-bit general timers TIM2 and 5 with DMA */ +# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ +# define STM32_NBTIM 2 /* 2 basic timers TIM6 and TIM7 */ +# define STM32_NDMA 2 /* DMA1-2 with 8 streams each*/ +# define STM32_NSPI 5 /* SPI1-5 */ +# define STM32_NI2S 3 /* I2S1-3 */ +# define STM32_NUSART 6 /* USART1, 2, 3 and 6 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 3 /* I2C1-3 */ +# define STM32_NCAN 2 /* 2 CAN */ +# define STM32_NSDIO 1 /* One SDIO interface */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 1 /* USB OTG FS (only) */ +# define STM32_NGPIO 113 /* GPIOA-H */ +# define STM32_NADC 1 /* One 12-bit ADC1, 16 channels */ +# define STM32_NDAC 0 /* No DAC */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NETHERNET 0 /* No Ethernet MAC */ +# define STM32_NRNG 1 /* Random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F405RG) /* LQFP 64 10x10x1.4 1024Kb FLASH 192Kb SRAM */ +# define STM32_NFSMC 0 /* No FSMC */ +# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ +# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA + * 32-bit general timers TIM2 and 5 with DMA */ +# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ +# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ +# define STM32_NDMA 2 /* DMA1-2 */ +# define STM32_NSPI 3 /* SPI1-3 */ +# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ +# define STM32_NUSART 6 /* USART1-3 and 6, UART 4-5 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 3 /* I2C1-3 */ +# define STM32_NCAN 2 /* CAN1-2 */ +# define STM32_NSDIO 1 /* SDIO */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ +# define STM32_NGPIO 139 /* GPIOA-I */ +# define STM32_NADC 3 /* 12-bit ADC1-3, 16 channels */ +# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NETHERNET 0 /* No Ethernet MAC */ +# define STM32_NRNG 1 /* Random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F405VG) /* LQFP 100 14x14x1.4 1024Kb FLASH 192Kb SRAM */ +# define STM32_NFSMC 1 /* FSMC */ +# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ +# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA + * 32-bit general timers TIM2 and 5 with DMA */ +# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ +# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ +# define STM32_NDMA 2 /* DMA1-2 */ +# define STM32_NSPI 3 /* SPI1-3 */ +# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ +# define STM32_NUSART 6 /* USART1-3 and 6, UART 4-5 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 3 /* I2C1-3 */ +# define STM32_NCAN 2 /* CAN1-2 */ +# define STM32_NSDIO 1 /* SDIO */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ +# define STM32_NGPIO 139 /* GPIOA-I */ +# define STM32_NADC 3 /* 12-bit ADC1-3, 16 channels */ +# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NETHERNET 0 /* No Ethernet MAC */ +# define STM32_NRNG 1 /* Random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F405ZG) /* LQFP 144 20x20x1.4 1024Kb FLASH 192Kb SRAM */ +# define STM32_NFSMC 1 /* FSMC */ +# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ +# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA + * 32-bit general timers TIM2 and 5 with DMA */ +# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ +# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ +# define STM32_NDMA 2 /* DMA1-2 */ +# define STM32_NSPI 3 /* SPI1-3 */ +# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ +# define STM32_NUSART 6 /* USART1-3 and 6, UART 4-5 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 3 /* I2C1-3 */ +# define STM32_NCAN 2 /* CAN1-2 */ +# define STM32_NSDIO 1 /* SDIO */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ +# define STM32_NGPIO 139 /* GPIOA-I */ +# define STM32_NADC 3 /* 12-bit ADC1-3, 24 channels */ +# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NETHERNET 0 /* No Ethernet MAC */ +# define STM32_NRNG 1 /* Random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F407VE) /* LQFP-100 512Kb FLASH 192Kb SRAM */ +# define STM32_NFSMC 1 /* FSMC */ +# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ +# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA + * 32-bit general timers TIM2 and 5 with DMA */ +# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ +# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ +# define STM32_NDMA 2 /* DMA1-2 */ +# define STM32_NSPI 3 /* SPI1-3 */ +# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ +# define STM32_NUSART 6 /* USART1-3 and 6, UART 4-5 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 3 /* I2C1-3 */ +# define STM32_NCAN 2 /* CAN1-2 */ +# define STM32_NSDIO 1 /* SDIO */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ +# define STM32_NGPIO 139 /* GPIOA-I */ +# define STM32_NADC 3 /* 12-bit ADC1-3, 16 channels */ +# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */ +# define STM32_NRNG 1 /* Random number generator (RNG) */ +# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F407VG) /* LQFP-100 14x14x1.4 1024Kb FLASH 192Kb SRAM */ +# define STM32_NFSMC 1 /* FSMC */ +# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ +# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA + * 32-bit general timers TIM2 and 5 with DMA */ +# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ +# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ +# define STM32_NDMA 2 /* DMA1-2 */ +# define STM32_NSPI 3 /* SPI1-3 */ +# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ +# define STM32_NUSART 6 /* USART1-3 and 6, UART 4-5 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 3 /* I2C1-3 */ +# define STM32_NCAN 2 /* CAN1-2 */ +# define STM32_NSDIO 1 /* SDIO */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ +# define STM32_NGPIO 139 /* GPIOA-I */ +# define STM32_NADC 3 /* 12-bit ADC1-3, 16 channels */ +# define STM32_NDAC 1 /* 12-bit DAC1, 1 channel */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */ +# define STM32_NRNG 1 /* Random number generator (RNG) */ +# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F407ZE) /* LQFP-144 512Kb FLASH 192Kb SRAM */ +# define STM32_NFSMC 1 /* FSMC */ +# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ +# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA + * 32-bit general timers TIM2 and 5 with DMA */ +# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ +# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ +# define STM32_NDMA 2 /* DMA1-2 */ +# define STM32_NSPI 3 /* SPI1-3 */ +# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ +# define STM32_NUSART 6 /* USART1-3 and 6, UART 4-5 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 3 /* I2C1-3 */ +# define STM32_NCAN 2 /* CAN1-2 */ +# define STM32_NSDIO 1 /* SDIO */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ +# define STM32_NGPIO 139 /* GPIOA-I */ +# define STM32_NADC 3 /* 12-bit ADC1-3, 24 channels */ +# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */ +# define STM32_NRNG 1 /* Random number generator (RNG) */ +# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F407ZG) /* LQFP 144 20x20x1.4 1024Kb FLASH 192Kb SRAM */ +# define STM32_NFSMC 1 /* FSMC */ +# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ +# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA + * 32-bit general timers TIM2 and 5 with DMA */ +# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ +# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ +# define STM32_NDMA 2 /* DMA1-2 */ +# define STM32_NSPI 3 /* SPI1-3 */ +# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ +# define STM32_NUSART 6 /* USART1-3 and 6, UART 4-5 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 3 /* I2C1-3 */ +# define STM32_NCAN 2 /* CAN1-2 */ +# define STM32_NSDIO 1 /* SDIO */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ +# define STM32_NGPIO 139 /* GPIOA-I */ +# define STM32_NADC 3 /* 12-bit ADC1-3, 24 channels */ +# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */ +# define STM32_NRNG 1 /* Random number generator (RNG) */ +# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F407IE) /* LQFP 176 24x24x1.4 512Kb FLASH 192Kb SRAM */ +# define STM32_NFSMC 1 /* FSMC */ +# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ +# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA + * 32-bit general timers TIM2 and 5 with DMA */ +# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ +# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ +# define STM32_NDMA 2 /* DMA1-2 */ +# define STM32_NSPI 3 /* SPI1-3 */ +# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ +# define STM32_NUSART 6 /* USART1-3 and 6, UART 4-5 (?) */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 3 /* I2C1-3 */ +# define STM32_NCAN 2 /* CAN1-2 */ +# define STM32_NSDIO 1 /* SDIO */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ +# define STM32_NGPIO 139 /* GPIOA-I */ +# define STM32_NADC 3 /* 12-bit ADC1-3, 24 channels */ +# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */ +# define STM32_NRNG 1 /* Random number generator (RNG) */ +# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F407IG) /* BGA 176; LQFP 176 24x24x1.4 1024Kb FLASH 192Kb SRAM */ +# define STM32_NFSMC 1 /* FSMC */ +# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ +# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA + * 32-bit general timers TIM2 and 5 with DMA */ +# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ +# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ +# define STM32_NDMA 2 /* DMA1-2 */ +# define STM32_NSPI 3 /* SPI1-3 */ +# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ +# define STM32_NUSART 6 /* USART1-3 and 6, UART 4-5 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 3 /* I2C1-3 */ +# define STM32_NCAN 2 /* CAN1-2 */ +# define STM32_NSDIO 1 /* SDIO */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ +# define STM32_NGPIO 139 /* GPIOA-I */ +# define STM32_NADC 3 /* 12-bit ADC1-3, 24 channels */ +# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */ +# define STM32_NRNG 1 /* Random number generator (RNG) */ +# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F427I) /* BGA176; LQFP176 1024/2048KiB flash 256KiB SRAM */ +# define STM32_NFSMC 1 /* FSMC */ +# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ +# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA + * 32-bit general timers TIM2 and 5 with DMA */ +# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ +# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ +# define STM32_NDMA 2 /* DMA1-2 */ +# define STM32_NSPI 6 /* SPI1-6 */ +# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ +# define STM32_NUSART 8 /* USART1-3 and 6, UART 4-5 and 7-8 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 3 /* I2C1-3 */ +# define STM32_NCAN 2 /* CAN1-2 */ +# define STM32_NSDIO 1 /* SDIO */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ +# define STM32_NGPIO 139 /* GPIOA-I */ +# define STM32_NADC 3 /* 12-bit ADC1-3, 24 channels */ +# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */ +# define STM32_NRNG 1 /* Random number generator (RNG) */ +# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F427Z) /* LQFP144 1024/2048KiB flash 256KiB SRAM */ +# define STM32_NFSMC 1 /* FSMC */ +# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ +# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA + * 32-bit general timers TIM2 and 5 with DMA */ +# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ +# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ +# define STM32_NDMA 2 /* DMA1-2 */ +# define STM32_NSPI 6 /* SPI1-6 */ +# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ +# define STM32_NUSART 8 /* USART1-3 and 6, UART 4-5 and 7-8 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 3 /* I2C1-3 */ +# define STM32_NCAN 2 /* CAN1-2 */ +# define STM32_NSDIO 1 /* SDIO */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ +# define STM32_NGPIO 139 /* GPIOA-I */ +# define STM32_NADC 3 /* 12-bit ADC1-3, 24 channels */ +# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */ +# define STM32_NRNG 1 /* Random number generator (RNG) */ +# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F427V) /* LQFP100 1024/2048KiB flash 256KiB SRAM */ +# define STM32_NFSMC 1 /* FSMC */ +# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ +# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA + * 32-bit general timers TIM2 and 5 with DMA */ +# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ +# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ +# define STM32_NDMA 2 /* DMA1-2 */ +# define STM32_NSPI 4 /* SPI1-4 */ +# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ +# define STM32_NUSART 8 /* USART1-3 and 6, UART 4-5 and 7-8 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 3 /* I2C1-3 */ +# define STM32_NCAN 2 /* CAN1-2 */ +# define STM32_NSDIO 1 /* SDIO */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ +# define STM32_NGPIO 139 /* GPIOA-I */ +# define STM32_NADC 3 /* 12-bit ADC1-3, 24 channels */ +# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */ +# define STM32_NRNG 1 /* Random number generator (RNG) */ +# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F429I) /* BGA176; LQFP176 1024/2048KiB flash 256KiB SRAM */ +# define STM32_NFSMC 1 /* FSMC */ +# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ +# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA + * 32-bit general timers TIM2 and 5 with DMA */ +# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ +# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ +# define STM32_NDMA 2 /* DMA1-2 */ +# define STM32_NSPI 6 /* SPI1-6 */ +# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ +# define STM32_NUSART 8 /* USART1-3 and 6, UART 4-5 and 7-8 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 3 /* I2C1-3 */ +# define STM32_NCAN 2 /* CAN1-2 */ +# define STM32_NSDIO 1 /* SDIO */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ +# define STM32_NGPIO 139 /* GPIOA-I */ +# define STM32_NADC 3 /* 12-bit ADC1-3, 24 channels */ +# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */ +# define STM32_NRNG 1 /* Random number generator (RNG) */ +# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F429Z) /* LQFP144 1024/2048KiB flash 256KiB SRAM */ +# define STM32_NFSMC 1 /* FSMC */ +# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ +# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA + * 32-bit general timers TIM2 and 5 with DMA */ +# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ +# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ +# define STM32_NDMA 2 /* DMA1-2 */ +# define STM32_NSPI 6 /* SPI1-6 */ +# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ +# define STM32_NUSART 8 /* USART1-3 and 6, UART 4-5 and 7-8 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 3 /* I2C1-3 */ +# define STM32_NCAN 2 /* CAN1-2 */ +# define STM32_NSDIO 1 /* SDIO */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ +# define STM32_NGPIO 139 /* GPIOA-I */ +# define STM32_NADC 3 /* 12-bit ADC1-3, 24 channels */ +# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */ +# define STM32_NRNG 1 /* Random number generator (RNG) */ +# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F429V) /* LQFP100 1024/2048KiB flash 256KiB SRAM */ +# define STM32_NFSMC 1 /* FSMC */ +# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ +# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA + * 32-bit general timers TIM2 and 5 with DMA */ +# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ +# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ +# define STM32_NDMA 2 /* DMA1-2 */ +# define STM32_NSPI 4 /* SPI1-4 */ +# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ +# define STM32_NUSART 8 /* USART1-3 and 6, UART 4-5 and 7-8 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 3 /* I2C1-3 */ +# define STM32_NCAN 2 /* CAN1-2 */ +# define STM32_NSDIO 1 /* SDIO */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ +# define STM32_NGPIO 139 /* GPIOA-I */ +# define STM32_NADC 3 /* 12-bit ADC1-3, 24 channels */ +# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */ +# define STM32_NRNG 1 /* Random number generator (RNG) */ +# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F446M) /* WLCSP81 256/512KiB flash 128KiB SRAM */ +# define STM32_NFSMC 0 /* FSMC */ +# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ +# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA + * 32-bit general timers TIM2 and 5 with DMA */ +# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ +# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ +# define STM32_NDMA 2 /* DMA1-2 */ +# define STM32_NSPI 4 /* SPI1-4 */ +# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ +# define STM32_NUSART 6 /* USART1-3 and 6, UART 4-5 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 3 /* I2C1-3 */ +# define STM32_NCAN 2 /* CAN1-2 */ +# define STM32_NSDIO 1 /* SDIO */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ +# define STM32_NGPIO 114 /* GPIOA-I */ +# define STM32_NADC 2 /* 12-bit ADC1-3, 14 channels */ +# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NETHERNET 0 /* 100/100 Ethernet MAC */ +# define STM32_NRNG 0 /* Random number generator (RNG) */ +# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F446R) /* LQFP64 256/512KiB flash 128KiB SRAM */ +# define STM32_NFSMC 0 /* FSMC */ +# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ +# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA + * 32-bit general timers TIM2 and 5 with DMA */ +# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ +# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ +# define STM32_NDMA 2 /* DMA1-2 */ +# define STM32_NSPI 4 /* SPI1-4 */ +# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ +# define STM32_NUSART 6 /* USART1-3 and 6, UART 4-5 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 3 /* I2C1-3 */ +# define STM32_NCAN 2 /* CAN1-2 */ +# define STM32_NSDIO 1 /* SDIO */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ +# define STM32_NGPIO 114 /* GPIOA-I */ +# define STM32_NADC 2 /* 12-bit ADC1-3, 16 channels */ +# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NETHERNET 0 /* 100/100 Ethernet MAC */ +# define STM32_NRNG 0 /* Random number generator (RNG) */ +# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F446V) /* LQFP100 256/512KiB flash 128KiB SRAM */ +# define STM32_NFSMC 1 /* FSMC */ +# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ +# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA + * 32-bit general timers TIM2 and 5 with DMA */ +# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ +# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ +# define STM32_NDMA 2 /* DMA1-2 */ +# define STM32_NSPI 4 /* SPI1-4 */ +# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ +# define STM32_NUSART 6 /* USART1-3 and 6, UART 4-5 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 3 /* I2C1-3 */ +# define STM32_NCAN 2 /* CAN1-2 */ +# define STM32_NSDIO 1 /* SDIO */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ +# define STM32_NGPIO 114 /* GPIOA-I */ +# define STM32_NADC 2 /* 12-bit ADC1-3, 16 channels */ +# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NETHERNET 0 /* 100/100 Ethernet MAC */ +# define STM32_NRNG 0 /* Random number generator (RNG) */ +# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F446Z) /* LQFP144 UFBGA144 256/512KiB flash 128KiB SRAM */ +# define STM32_NFSMC 1 /* FSMC */ +# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ +# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA + * 32-bit general timers TIM2 and 5 with DMA */ +# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ +# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ +# define STM32_NDMA 2 /* DMA1-2 */ +# define STM32_NSPI 4 /* SPI1-4 */ +# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ +# define STM32_NUSART 6 /* USART1-3 and 6, UART 4-5 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 3 /* I2C1-3 */ +# define STM32_NCAN 2 /* CAN1-2 */ +# define STM32_NSDIO 1 /* SDIO */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ +# define STM32_NGPIO 114 /* GPIOA-I */ +# define STM32_NADC 2 /* 12-bit ADC1-3, 16 channels */ +# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NETHERNET 0 /* 100/100 Ethernet MAC */ +# define STM32_NRNG 0 /* Random number generator (RNG) */ +# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F429N) /* TFBGA216 1024/2048KiB flash 256KiB SRAM */ +# define STM32_NFSMC 1 /* FSMC */ +# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ +# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA + * 32-bit general timers TIM2 and 5 with DMA */ +# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ +# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ +# define STM32_NDMA 2 /* DMA1-2 */ +# define STM32_NSPI 6 /* SPI1-6 */ +# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ +# define STM32_NUSART 8 /* USART1-3 and 6, UART 4-5 and 7-8 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 3 /* I2C1-3 */ +# define STM32_NCAN 2 /* CAN1-2 */ +# define STM32_NSDIO 1 /* SDIO */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ +# define STM32_NGPIO 168 /* GPIOA-K */ +# define STM32_NADC 3 /* 12-bit ADC1-3, 24 channels */ +# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */ +# define STM32_NRNG 1 /* Random number generator (RNG) */ +# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F469A) || \ + defined(CONFIG_ARCH_CHIP_STM32F469I) || \ + defined(CONFIG_ARCH_CHIP_STM32F469B) || \ + defined(CONFIG_ARCH_CHIP_STM32F469N) +# define STM32_NFSMC 1 /* FSMC */ +# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ +# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA + * 32-bit general timers TIM2 and 5 with DMA */ +# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ +# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ +# define STM32_NDMA 2 /* DMA1-2 */ +# define STM32_NSPI 6 /* SPI1-6 */ +# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ +# define STM32_NUSART 8 /* USART1-3 and 6, UART 4-5 and 7-8 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 3 /* I2C1-3 */ +# define STM32_NCAN 2 /* CAN1-2 */ +# define STM32_NSDIO 1 /* SDIO */ +# define STM32_NLCD 1 /* LCD */ +# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ +# if defined(CONFIG_ARCH_CHIP_STM32F469A) +# define STM32_NGPIO 114 /* GPIOA-I */ +# elif defined(CONFIG_ARCH_CHIP_STM32F469I) +# define STM32_NGPIO 131 /* GPIOA-I */ +# elif defined(CONFIG_ARCH_CHIP_STM32F469B) || \ + defined(CONFIG_ARCH_CHIP_STM32F469N) +# define STM32_NGPIO 161 /* GPIOA-K */ +# endif +# define STM32_NADC 3 /* 12-bit ADC1-3, 24 channels */ +# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# if defined(CONFIG_ARCH_CHIP_STM32F469A) +# define STM32_NETHERNET 0 /* No Ethernet MAC */ +# elif defined(CONFIG_ARCH_CHIP_STM32F469I) || \ + defined(CONFIG_ARCH_CHIP_STM32F469B) || \ + defined(CONFIG_ARCH_CHIP_STM32F469N) +# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */ +# endif +# define STM32_NRNG 1 /* Random number generator (RNG) */ +# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */ + +#else +# error "Unsupported STM32 chip" +#endif + +/* Peripheral IP versions ***************************************************/ + +/* Peripheral IP versions are invariant and should be decided here, not in + * Kconfig. + * + * REVISIT: Currently only SPI IP version is handled here, with others being + * handled in Kconfig. Those others need to be gradually refactored + * and resolved here. + */ + +#define STM32_HAVE_IP_SPI_V2 + +/* NVIC priority levels *****************************************************/ + +#define NVIC_SYSH_PRIORITY_MIN 0xf0 /* All bits set in minimum priority */ +#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */ +#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */ +#define NVIC_SYSH_PRIORITY_STEP 0x10 /* Four bits of interrupt priority used */ + +#endif /* __ARCH_ARM_INCLUDE_STM32F4_CHIP_H */ diff --git a/arch/arm/include/stm32f4/irq.h b/arch/arm/include/stm32f4/irq.h new file mode 100644 index 0000000000000..eb9eb5e34385a --- /dev/null +++ b/arch/arm/include/stm32f4/irq.h @@ -0,0 +1,346 @@ +/**************************************************************************** + * arch/arm/include/stm32f4/irq.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* This file should never be included directly but, rather, + * only indirectly through nuttx/irq.h + */ + +#ifndef __ARCH_ARM_INCLUDE_STM32F4_IRQ_H +#define __ARCH_ARM_INCLUDE_STM32F4_IRQ_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include + +/**************************************************************************** + * Pre-processor Prototypes + ****************************************************************************/ + +/* IRQ numbers. + * The IRQ number corresponds vector number and hence map directly to + * bits in the NVIC. This does, however, waste several words of memory in + * the IRQ to handle mapping tables. + */ + +/* Processor Exceptions (vectors 0-15) */ + +#define STM32_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */ + /* Vector 0: Reset stack pointer value */ + /* Vector 1: Reset (not handler as an IRQ) */ +#define STM32_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */ +#define STM32_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */ +#define STM32_IRQ_MEMFAULT (4) /* Vector 4: Memory management (MPU) */ +#define STM32_IRQ_BUSFAULT (5) /* Vector 5: Bus fault */ +#define STM32_IRQ_USAGEFAULT (6) /* Vector 6: Usage fault */ +#define STM32_IRQ_SVCALL (11) /* Vector 11: SVC call */ +#define STM32_IRQ_DBGMONITOR (12) /* Vector 12: Debug Monitor */ + /* Vector 13: Reserved */ +#define STM32_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */ +#define STM32_IRQ_SYSTICK (15) /* Vector 15: System tick */ + +/* External interrupts (vectors >= 16). + * These definitions are chip-specific + */ + +#define STM32_IRQ_FIRST (16) /* Vector number of the first external interrupt */ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#define STM32_IRQ_WWDG (STM32_IRQ_FIRST+0) /* 0: Window Watchdog interrupt */ +#define STM32_IRQ_PVD (STM32_IRQ_FIRST+1) /* 1: PVD through EXTI Line detection interrupt */ +#define STM32_IRQ_TAMPER (STM32_IRQ_FIRST+2) /* 2: Tamper and time stamp interrupts */ +#define STM32_IRQ_TIMESTAMP (STM32_IRQ_FIRST+2) /* 2: Tamper and time stamp interrupts */ +#define STM32_IRQ_RTC_WKUP (STM32_IRQ_FIRST+3) /* 3: RTC global interrupt */ +#define STM32_IRQ_FLASH (STM32_IRQ_FIRST+4) /* 4: Flash global interrupt */ +#define STM32_IRQ_RCC (STM32_IRQ_FIRST+5) /* 5: RCC global interrupt */ +#define STM32_IRQ_EXTI0 (STM32_IRQ_FIRST+6) /* 6: EXTI Line 0 interrupt */ +#define STM32_IRQ_EXTI1 (STM32_IRQ_FIRST+7) /* 7: EXTI Line 1 interrupt */ +#define STM32_IRQ_EXTI2 (STM32_IRQ_FIRST+8) /* 8: EXTI Line 2 interrupt */ +#define STM32_IRQ_EXTI3 (STM32_IRQ_FIRST+9) /* 9: EXTI Line 3 interrupt */ +#define STM32_IRQ_EXTI4 (STM32_IRQ_FIRST+10) /* 10: EXTI Line 4 interrupt */ +#define STM32_IRQ_DMA1S0 (STM32_IRQ_FIRST+11) /* 11: DMA1 Stream 0 global interrupt */ +#define STM32_IRQ_DMA1S1 (STM32_IRQ_FIRST+12) /* 12: DMA1 Stream 1 global interrupt */ +#define STM32_IRQ_DMA1S2 (STM32_IRQ_FIRST+13) /* 13: DMA1 Stream 2 global interrupt */ +#define STM32_IRQ_DMA1S3 (STM32_IRQ_FIRST+14) /* 14: DMA1 Stream 3 global interrupt */ +#define STM32_IRQ_DMA1S4 (STM32_IRQ_FIRST+15) /* 15: DMA1 Stream 4 global interrupt */ +#define STM32_IRQ_DMA1S5 (STM32_IRQ_FIRST+16) /* 16: DMA1 Stream 5 global interrupt */ +#define STM32_IRQ_DMA1S6 (STM32_IRQ_FIRST+17) /* 17: DMA1 Stream 6 global interrupt */ +#define STM32_IRQ_ADC (STM32_IRQ_FIRST+18) /* 18: ADC1, ADC2, and ADC3 global interrupt */ + +#if defined(CONFIG_STM32_STM32F410) +# define STM32_IRQ_RESERVED19 (STM32_IRQ_FIRST+19) /* 19: Reserved */ +# define STM32_IRQ_RESERVED20 (STM32_IRQ_FIRST+20) /* 20: Reserved */ +# define STM32_IRQ_RESERVED21 (STM32_IRQ_FIRST+21) /* 21: Reserved */ +# define STM32_IRQ_RESERVED22 (STM32_IRQ_FIRST+22) /* 22: Reserved */ +#else +# define STM32_IRQ_CAN1TX (STM32_IRQ_FIRST+19) /* 19: CAN1 TX interrupts */ +# define STM32_IRQ_CAN1RX0 (STM32_IRQ_FIRST+20) /* 20: CAN1 RX0 interrupts */ +# define STM32_IRQ_CAN1RX1 (STM32_IRQ_FIRST+21) /* 21: CAN1 RX1 interrupt */ +# define STM32_IRQ_CAN1SCE (STM32_IRQ_FIRST+22) /* 22: CAN1 SCE interrupt */ +#endif + +#define STM32_IRQ_EXTI95 (STM32_IRQ_FIRST+23) /* 23: EXTI Line[9:5] interrupts */ +#define STM32_IRQ_TIM1BRK (STM32_IRQ_FIRST+24) /* 24: TIM1 Break interrupt */ +#define STM32_IRQ_TIM9 (STM32_IRQ_FIRST+24) /* 24: TIM9 global interrupt */ +#define STM32_IRQ_TIM1UP (STM32_IRQ_FIRST+25) /* 25: TIM1 Update interrupt */ +#define STM32_IRQ_TIM10 (STM32_IRQ_FIRST+25) /* 25: TIM10 global interrupt */ +#define STM32_IRQ_TIM1TRGCOM (STM32_IRQ_FIRST+26) /* 26: TIM1 Trigger and Commutation interrupts */ +#define STM32_IRQ_TIM11 (STM32_IRQ_FIRST+26) /* 26: TIM11 global interrupt */ +#define STM32_IRQ_TIM1CC (STM32_IRQ_FIRST+27) /* 27: TIM1 Capture Compare interrupt */ + +#if defined(CONFIG_STM32_STM32F410) +# define STM32_IRQ_RESERVED28 (STM32_IRQ_FIRST+28) /* 28: Reserved */ +# define STM32_IRQ_RESERVED29 (STM32_IRQ_FIRST+29) /* 29: Reserved */ +# define STM32_IRQ_RESERVED30 (STM32_IRQ_FIRST+30) /* 30: Reserved */ +#else +# define STM32_IRQ_TIM2 (STM32_IRQ_FIRST+28) /* 28: TIM2 global interrupt */ +# define STM32_IRQ_TIM3 (STM32_IRQ_FIRST+29) /* 29: TIM3 global interrupt */ +# define STM32_IRQ_TIM4 (STM32_IRQ_FIRST+30) /* 30: TIM4 global interrupt */ +#endif + +#define STM32_IRQ_I2C1EV (STM32_IRQ_FIRST+31) /* 31: I2C1 event interrupt */ +#define STM32_IRQ_I2C1ER (STM32_IRQ_FIRST+32) /* 32: I2C1 error interrupt */ +#define STM32_IRQ_I2C2EV (STM32_IRQ_FIRST+33) /* 33: I2C2 event interrupt */ +#define STM32_IRQ_I2C2ER (STM32_IRQ_FIRST+34) /* 34: I2C2 error interrupt */ +#define STM32_IRQ_SPI1 (STM32_IRQ_FIRST+35) /* 35: SPI1 global interrupt */ +#define STM32_IRQ_SPI2 (STM32_IRQ_FIRST+36) /* 36: SPI2 global interrupt */ +#define STM32_IRQ_USART1 (STM32_IRQ_FIRST+37) /* 37: USART1 global interrupt */ +#define STM32_IRQ_USART2 (STM32_IRQ_FIRST+38) /* 38: USART2 global interrupt */ + +#if defined(CONFIG_STM32_STM32F410) +# define STM32_IRQ_RESERVED39 (STM32_IRQ_FIRST+39) /* 39: Reserved */ +#else +# define STM32_IRQ_USART3 (STM32_IRQ_FIRST+39) /* 39: USART3 global interrupt */ +#endif + +#define STM32_IRQ_EXTI1510 (STM32_IRQ_FIRST+40) /* 40: EXTI Line[15:10] interrupts */ +#define STM32_IRQ_RTCALRM (STM32_IRQ_FIRST+41) /* 41: RTC alarm through EXTI line interrupt */ + +#if defined(CONFIG_STM32_STM32F410) +# define STM32_IRQ_RESERVED42 (STM32_IRQ_FIRST+42) /* 42: Reserved */ +# define STM32_IRQ_RESERVED43 (STM32_IRQ_FIRST+43) /* 43: Reserved */ +# define STM32_IRQ_RESERVED44 (STM32_IRQ_FIRST+44) /* 44: Reserved */ +# define STM32_IRQ_RESERVED45 (STM32_IRQ_FIRST+45) /* 45: Reserved */ +# define STM32_IRQ_RESERVED46 (STM32_IRQ_FIRST+46) /* 46: Reserved */ +#else +# define STM32_IRQ_OTGFSWKUP (STM32_IRQ_FIRST+42) /* 42: USB On-The-Go FS Wakeup through EXTI line interrupt */ +# define STM32_IRQ_TIM8BRK (STM32_IRQ_FIRST+43) /* 43: TIM8 Break interrupt */ +# define STM32_IRQ_TIM12 (STM32_IRQ_FIRST+43) /* 43: TIM12 global interrupt */ +# define STM32_IRQ_TIM8UP (STM32_IRQ_FIRST+44) /* 44: TIM8 Update interrupt */ +# define STM32_IRQ_TIM13 (STM32_IRQ_FIRST+44) /* 44: TIM13 global interrupt */ +# define STM32_IRQ_TIM8TRGCOM (STM32_IRQ_FIRST+45) /* 45: TIM8 Trigger and Commutation interrupts */ +# define STM32_IRQ_TIM14 (STM32_IRQ_FIRST+45) /* 45: TIM14 global interrupt */ +# define STM32_IRQ_TIM8CC (STM32_IRQ_FIRST+46) /* 46: TIM8 Capture Compare interrupt */ +#endif + +#define STM32_IRQ_DMA1S7 (STM32_IRQ_FIRST+47) /* 47: DMA1 Stream 7 global interrupt */ + +#if defined(CONFIG_STM32_STM32F410) +# define STM32_IRQ_RESERVED48 (STM32_IRQ_FIRST+48) /* 48: Reserved */ +# define STM32_IRQ_RESERVED49 (STM32_IRQ_FIRST+49) /* 48: Reserved */ +#else +# define STM32_IRQ_FSMC (STM32_IRQ_FIRST+48) /* 48: FSMC global interrupt */ +# define STM32_IRQ_SDIO (STM32_IRQ_FIRST+49) /* 49: SDIO global interrupt */ +#endif + +#define STM32_IRQ_TIM5 (STM32_IRQ_FIRST+50) /* 50: TIM5 global interrupt */ + +#if defined(CONFIG_STM32_STM32F410) +# define STM32_IRQ_RESERVED51 (STM32_IRQ_FIRST+51) /* 51: Reserved */ +# define STM32_IRQ_RESERVED52 (STM32_IRQ_FIRST+52) /* 52: Reserved */ +# define STM32_IRQ_RESERVED53 (STM32_IRQ_FIRST+53) /* 53: Reserved */ +#else +# define STM32_IRQ_SPI3 (STM32_IRQ_FIRST+51) /* 51: SPI3 global interrupt */ +# define STM32_IRQ_UART4 (STM32_IRQ_FIRST+52) /* 52: UART4 global interrupt */ +# define STM32_IRQ_UART5 (STM32_IRQ_FIRST+53) /* 53: UART5 global interrupt */ +#endif + +#define STM32_IRQ_TIM6 (STM32_IRQ_FIRST+54) /* 54: TIM6 global interrupt */ +#define STM32_IRQ_DAC (STM32_IRQ_FIRST+54) /* 54: DAC1 and DAC2 underrun error interrupts */ + +#if defined(CONFIG_STM32_STM32F410) +# define STM32_IRQ_RESERVED55 (STM32_IRQ_FIRST+55) /* 55: Reserved */ +#else +# define STM32_IRQ_TIM7 (STM32_IRQ_FIRST+55) /* 55: TIM7 global interrupt */ +#endif + +#define STM32_IRQ_DMA2S0 (STM32_IRQ_FIRST+56) /* 56: DMA2 Stream 0 global interrupt */ +#define STM32_IRQ_DMA2S1 (STM32_IRQ_FIRST+57) /* 57: DMA2 Stream 1 global interrupt */ +#define STM32_IRQ_DMA2S2 (STM32_IRQ_FIRST+58) /* 58: DMA2 Stream 2 global interrupt */ +#define STM32_IRQ_DMA2S3 (STM32_IRQ_FIRST+59) /* 59: DMA2 Stream 3 global interrupt */ +#define STM32_IRQ_DMA2S4 (STM32_IRQ_FIRST+60) /* 60: DMA2 Stream 4 global interrupt */ + +#if defined(CONFIG_STM32_STM32F446) +# define STM32_IRQ_RESERVED61 (STM32_IRQ_FIRST+61) /* 61: Reserved */ +# define STM32_IRQ_RESERVED62 (STM32_IRQ_FIRST+62) /* 62: Reserved */ +#else +# define STM32_IRQ_ETH (STM32_IRQ_FIRST+61) /* 61: Ethernet global interrupt */ +# define STM32_IRQ_ETHWKUP (STM32_IRQ_FIRST+62) /* 62: Ethernet Wakeup through EXTI line interrupt */ +#endif + +#if defined(CONFIG_STM32_STM32F410) +# define STM32_IRQ_RESERVED63 (STM32_IRQ_FIRST+63) /* 63: Reserved */ +# define STM32_IRQ_RESERVED64 (STM32_IRQ_FIRST+64) /* 63: Reserved */ +# define STM32_IRQ_RESERVED65 (STM32_IRQ_FIRST+65) /* 63: Reserved */ +# define STM32_IRQ_RESERVED66 (STM32_IRQ_FIRST+66) /* 63: Reserved */ +# define STM32_IRQ_RESERVED67 (STM32_IRQ_FIRST+67) /* 63: Reserved */ +#else +# define STM32_IRQ_CAN2TX (STM32_IRQ_FIRST+63) /* 63: CAN2 TX interrupts */ +# define STM32_IRQ_CAN2RX0 (STM32_IRQ_FIRST+64) /* 64: CAN2 RX0 interrupts */ +# define STM32_IRQ_CAN2RX1 (STM32_IRQ_FIRST+65) /* 65: CAN2 RX1 interrupt */ +# define STM32_IRQ_CAN2SCE (STM32_IRQ_FIRST+66) /* 66: CAN2 SCE interrupt */ +# define STM32_IRQ_OTGFS (STM32_IRQ_FIRST+67) /* 67: USB On The Go FS global interrupt */ +#endif + +#define STM32_IRQ_DMA2S5 (STM32_IRQ_FIRST+68) /* 68: DMA2 Stream 5 global interrupt */ +#define STM32_IRQ_DMA2S6 (STM32_IRQ_FIRST+69) /* 69: DMA2 Stream 6 global interrupt */ +#define STM32_IRQ_DMA2S7 (STM32_IRQ_FIRST+70) /* 70: DMA2 Stream 7 global interrupt */ +#define STM32_IRQ_USART6 (STM32_IRQ_FIRST+71) /* 71: USART6 global interrupt */ + +#if defined(CONFIG_STM32_STM32F410) +# define STM32_IRQ_RESERVED72 (STM32_IRQ_FIRST+72) /* 72: Reserved */ +# define STM32_IRQ_RESERVED73 (STM32_IRQ_FIRST+73) /* 73: Reserved */ +# define STM32_IRQ_RESERVED74 (STM32_IRQ_FIRST+74) /* 74: Reserved */ +# define STM32_IRQ_RESERVED75 (STM32_IRQ_FIRST+75) /* 75: Reserved */ +# define STM32_IRQ_RESERVED76 (STM32_IRQ_FIRST+76) /* 76: Reserved */ +# define STM32_IRQ_RESERVED77 (STM32_IRQ_FIRST+77) /* 77: Reserved */ +# define STM32_IRQ_RESERVED78 (STM32_IRQ_FIRST+78) /* 78: Reserved */ +#else +# define STM32_IRQ_I2C3EV (STM32_IRQ_FIRST+72) /* 72: I2C3 event interrupt */ +# define STM32_IRQ_I2C3ER (STM32_IRQ_FIRST+73) /* 73: I2C3 error interrupt */ +# define STM32_IRQ_OTGHSEP1OUT (STM32_IRQ_FIRST+74) /* 74: USB On The Go HS End Point 1 Out global interrupt */ +# define STM32_IRQ_OTGHSEP1IN (STM32_IRQ_FIRST+75) /* 75: USB On The Go HS End Point 1 In global interrupt */ +# define STM32_IRQ_OTGHSWKUP (STM32_IRQ_FIRST+76) /* 76: USB On The Go HS Wakeup through EXTI interrupt */ +# define STM32_IRQ_OTGHS (STM32_IRQ_FIRST+77) /* 77: USB On The Go HS global interrupt */ +# define STM32_IRQ_DCMI (STM32_IRQ_FIRST+78) /* 78: DCMI global interrupt */ +#endif + +#if defined(CONFIG_STM32_STM32F446) +# define STM32_IRQ_RESERVED79 (STM32_IRQ_FIRST+79) /* 79: Reserved */ +# define STM32_IRQ_RESERVED80 (STM32_IRQ_FIRST+80) /* 80: Reserved */ +#else +# if defined(CONFIG_STM32_STM32F410) +# define STM32_IRQ_RESERVED79 (STM32_IRQ_FIRST+79) /* 79: Reserved */ +# else +# define STM32_IRQ_CRYP (STM32_IRQ_FIRST+79) /* 79: CRYP crypto global interrupt */ +# endif +# define STM32_IRQ_HASH (STM32_IRQ_FIRST+80) /* 80: Hash and Rng global interrupt */ +# define STM32_IRQ_RNG (STM32_IRQ_FIRST+80) /* 80: Hash and Rng global interrupt */ +#endif + +#define STM32_IRQ_FPU (STM32_IRQ_FIRST+81) /* 81: FPU global interrupt */ + +#if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429) || \ + defined(CONFIG_STM32_STM32F469) +# define STM32_IRQ_UART7 (STM32_IRQ_FIRST+82) /* 82: UART7 interrupt */ +# define STM32_IRQ_UART8 (STM32_IRQ_FIRST+83) /* 83: UART8 interrupt */ +#elif defined(CONFIG_STM32_STM32F446) || defined(CONFIG_STM32_STM32F410) +# define STM32_IRQ_RESERVED82 (STM32_IRQ_FIRST+82) /* 82: Reserved */ +# define STM32_IRQ_RESERVED83 (STM32_IRQ_FIRST+83) /* 83: Reserved */ +#endif + +#if defined(CONFIG_STM32_STM32F410) +# define STM32_IRQ_RESERVED84 (STM32_IRQ_FIRST+84) /* 84: Reserved */ +#elif defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429) || \ + defined(CONFIG_STM32_STM32F446) || defined(CONFIG_STM32_STM32F469) +# define STM32_IRQ_SPI4 (STM32_IRQ_FIRST+84) /* 84: SPI4 interrupt */ +#endif + +#if defined(CONFIG_STM32_STM32F410) +# define STM32_IRQ_SPI5 (STM32_IRQ_FIRST+85) /* 85: SPI5 interrupt */ +# define STM32_IRQ_RESERVED86 (STM32_IRQ_FIRST+86) /* 86: Reserved */ +#elif defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429) || \ + defined(CONFIG_STM32_STM32F469) +# define STM32_IRQ_SPI5 (STM32_IRQ_FIRST+85) /* 85: SPI5 interrupt */ +# define STM32_IRQ_SPI6 (STM32_IRQ_FIRST+86) /* 86: SPI6 interrupt */ +#elif defined(CONFIG_STM32_STM32F446) +# define STM32_IRQ_RESERVED85 (STM32_IRQ_FIRST+85) /* 85: Reserved */ +# define STM32_IRQ_RESERVED86 (STM32_IRQ_FIRST+86) /* 86: Reserved */ +#endif + +#if defined(CONFIG_STM32_STM32F410) +# define STM32_IRQ_RESERVED87 (STM32_IRQ_FIRST+87) /* 87: Reserved */ +#elif defined(CONFIG_STM32_STM32F429) || defined(CONFIG_STM32_STM32F446) || \ + defined(CONFIG_STM32_STM32F446) || defined(CONFIG_STM32_STM32F469) +# define STM32_IRQ_SAI1 (STM32_IRQ_FIRST+87) /* 87: SAI1 interrupt */ +#endif + +#if defined(CONFIG_STM32_STM32F429) || defined(CONFIG_STM32_STM32F469) +# define STM32_IRQ_LTDCINT (STM32_IRQ_FIRST+88) /* 88: LTDCINT interrupt */ +# define STM32_IRQ_LTDCERRINT (STM32_IRQ_FIRST+89) /* 89: LTDCERRINT interrupt */ +# define STM32_IRQ_DMA2D (STM32_IRQ_FIRST+90) /* 90: DMA2D interrupt */ +#elif defined(CONFIG_STM32_STM32F446) || defined(CONFIG_STM32_STM32F410) +# define STM32_IRQ_RESERVED88 (STM32_IRQ_FIRST+88) /* 88: Reserved */ +# define STM32_IRQ_RESERVED89 (STM32_IRQ_FIRST+89) /* 89: Reserved */ +# define STM32_IRQ_RESERVED90 (STM32_IRQ_FIRST+90) /* 90: Reserved */ +#endif + +#if defined(CONFIG_STM32_STM32F410) +# define STM32_IRQ_RESERVED91 (STM32_IRQ_FIRST+91) /* 91: Reserved */ +# define STM32_IRQ_RESERVED92 (STM32_IRQ_FIRST+92) /* 92: Reserved */ +#elif defined(CONFIG_STM32_STM32F446) +# define STM32_IRQ_SAI2 (STM32_IRQ_FIRST+91) /* 91: SAI2 Global interrupt */ +# define STM32_IRQ_QUADSPI (STM32_IRQ_FIRST+92) /* 92: QuadSPI Global interrupt */ +#elif defined(CONFIG_STM32_STM32F469) +# define STM32_IRQ_QUADSPI (STM32_IRQ_FIRST+91) /* 92: QuadSPI Global interrupt */ +# define STM32_IRQ_DSI (STM32_IRQ_FIRST+92) /* 91: DSI Global interrupt */ +#endif + +#if defined(CONFIG_STM32_STM32F446) +# define STM32_IRQ_HDMICEC (STM32_IRQ_FIRST+93) /* 93: HDMI-CEC Global interrupt */ +# define STM32_IRQ_SPDIFRX (STM32_IRQ_FIRST+94) /* 94: SPDIF-Rx Global interrupt */ +# define STM32_IRQ_FMPI2C1 (STM32_IRQ_FIRST+95) /* 95: FMPI2C1 event interrupt */ +# define STM32_IRQ_FMPI2C1ERR (STM32_IRQ_FIRST+96) /* 96: FMPI2C1 Error event interrupt */ +#endif + +#if defined(CONFIG_STM32_STM32F410) +# define STM32_IRQ_RESERVED93 (STM32_IRQ_FIRST+93) /* 93: Reserved */ +# define STM32_IRQ_RESERVED94 (STM32_IRQ_FIRST+94) /* 94: Reserved */ +# define STM32_IRQ_RESERVED95 (STM32_IRQ_FIRST+95) /* 95: Reserved */ +# define STM32_IRQ_RESERVED96 (STM32_IRQ_FIRST+96) /* 96: Reserved */ +# define STM32_IRQ_RESERVED97 (STM32_IRQ_FIRST+97) /* 97: Reserved */ +#endif + +#if defined(CONFIG_STM32_STM32F401) || defined(CONFIG_STM32_STM32F411) || \ + defined(CONFIG_STM32_STM32F405) || defined(CONFIG_STM32_STM32F407) +# define STM32_IRQ_NEXTINTS (82) +#elif defined(CONFIG_STM32_STM32F410) +# define STM32_IRQ_NEXTINTS (98) +#elif defined(CONFIG_STM32_STM32F427) +# define STM32_IRQ_NEXTINTS (87) +#elif defined(CONFIG_STM32_STM32F429) +# define STM32_IRQ_NEXTINTS (91) +#elif defined(CONFIG_STM32_STM32F446) || defined(CONFIG_STM32_STM32F412) +# define STM32_IRQ_NEXTINTS (97) +#elif defined(CONFIG_STM32_STM32F469) +# define STM32_IRQ_NEXTINTS (93) +#endif + +# define NR_IRQS (STM32_IRQ_FIRST+STM32_IRQ_NEXTINTS) + +#endif /* __ARCH_ARM_INCLUDE_STM32F4_IRQ_H */ diff --git a/arch/arm/include/stm32f7/chip.h b/arch/arm/include/stm32f7/chip.h index 5b2eb34fc1fc6..2d17d6538fc5d 100644 --- a/arch/arm/include/stm32f7/chip.h +++ b/arch/arm/include/stm32f7/chip.h @@ -181,8 +181,8 @@ * Parts STM32F74xxG have 1024Kb of FLASH * Parts STM32F74xxI have 2048Kb of FLASH * - * The correct FLASH size will be set CONFIG_STM32F7_FLASH_CONFIG_x - * or overridden with CONFIG_STM32F7_FLASH_OVERRIDE_x + * The correct FLASH size will be set CONFIG_STM32_FLASH_CONFIG_x + * or overridden with CONFIG_STM32_FLASH_OVERRIDE_x * */ #if defined(CONFIG_ARCH_CHIP_STM32F722RC) || \ @@ -264,44 +264,44 @@ /* Size SRAM */ -#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX) -# define STM32F7_SRAM1_SIZE (176*1024) /* 176Kb SRAM1 on AHB bus Matrix */ -# define STM32F7_SRAM2_SIZE (16*1024) /* 16Kb SRAM2 on AHB bus Matrix */ +#if defined(CONFIG_STM32_STM32F72XX) || defined(CONFIG_STM32_STM32F73XX) +# define STM32_SRAM1_SIZE (176*1024) /* 176Kb SRAM1 on AHB bus Matrix */ +# define STM32_SRAM2_SIZE (16*1024) /* 16Kb SRAM2 on AHB bus Matrix */ # if defined(CONFIG_ARMV7M_HAVE_DTCM) -# define STM32F7_DTCM_SRAM_SIZE (64*1024) /* 64Kb DTCM SRAM on TCM interface */ +# define STM32_DTCM_SRAM_SIZE (64*1024) /* 64Kb DTCM SRAM on TCM interface */ # else -# define STM32F7_DTCM_SRAM_SIZE (0) /* No DTCM SRAM on TCM interface */ +# define STM32_DTCM_SRAM_SIZE (0) /* No DTCM SRAM on TCM interface */ # endif # if defined(CONFIG_ARMV7M_HAVE_ITCM) -# define STM32F7_ITCM_SRAM_SIZE (16*1024) /* 16Kb ITCM SRAM on TCM interface */ +# define STM32_ITCM_SRAM_SIZE (16*1024) /* 16Kb ITCM SRAM on TCM interface */ # else -# define STM32F7_ITCM_SRAM_SIZE (0) /* No ITCM SRAM on TCM interface */ +# define STM32_ITCM_SRAM_SIZE (0) /* No ITCM SRAM on TCM interface */ # endif -#elif defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) -# define STM32F7_SRAM1_SIZE (240*1024) /* 240Kb SRAM1 on AHB bus Matrix */ -# define STM32F7_SRAM2_SIZE (16*1024) /* 16Kb SRAM2 on AHB bus Matrix */ +#elif defined(CONFIG_STM32_STM32F74XX) || defined(CONFIG_STM32_STM32F75XX) +# define STM32_SRAM1_SIZE (240*1024) /* 240Kb SRAM1 on AHB bus Matrix */ +# define STM32_SRAM2_SIZE (16*1024) /* 16Kb SRAM2 on AHB bus Matrix */ # if defined(CONFIG_ARMV7M_HAVE_DTCM) -# define STM32F7_DTCM_SRAM_SIZE (64*1024) /* 64Kb DTCM SRAM on TCM interface */ +# define STM32_DTCM_SRAM_SIZE (64*1024) /* 64Kb DTCM SRAM on TCM interface */ # else -# define STM32F7_DTCM_SRAM_SIZE (0) /* No DTCM SRAM on TCM interface */ +# define STM32_DTCM_SRAM_SIZE (0) /* No DTCM SRAM on TCM interface */ # endif # if defined(CONFIG_ARMV7M_HAVE_ITCM) -# define STM32F7_ITCM_SRAM_SIZE (16*1024) /* 16Kb ITCM SRAM on TCM interface */ +# define STM32_ITCM_SRAM_SIZE (16*1024) /* 16Kb ITCM SRAM on TCM interface */ # else -# define STM32F7_ITCM_SRAM_SIZE (0) /* No ITCM SRAM on TCM interface */ +# define STM32_ITCM_SRAM_SIZE (0) /* No ITCM SRAM on TCM interface */ # endif -#elif defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) -# define STM32F7_SRAM1_SIZE (368*1024) /* 368Kb SRAM1 on AHB bus Matrix */ -# define STM32F7_SRAM2_SIZE (16*1024) /* 16Kb SRAM2 on AHB bus Matrix */ +#elif defined(CONFIG_STM32_STM32F76XX) || defined(CONFIG_STM32_STM32F77XX) +# define STM32_SRAM1_SIZE (368*1024) /* 368Kb SRAM1 on AHB bus Matrix */ +# define STM32_SRAM2_SIZE (16*1024) /* 16Kb SRAM2 on AHB bus Matrix */ # if defined(CONFIG_ARMV7M_HAVE_DTCM) -# define STM32F7_DTCM_SRAM_SIZE (128*1024) /* 128Kb DTCM SRAM on TCM interface */ +# define STM32_DTCM_SRAM_SIZE (128*1024) /* 128Kb DTCM SRAM on TCM interface */ # else -# define STM32F7_DTCM_SRAM_SIZE (0) /* No DTCM SRAM on TCM interface */ +# define STM32_DTCM_SRAM_SIZE (0) /* No DTCM SRAM on TCM interface */ # endif # if defined(CONFIG_ARMV7M_HAVE_ITCM) -# define STM32F7_ITCM_SRAM_SIZE (16*1024) /* 16Kb ITCM SRAM on TCM interface */ +# define STM32_ITCM_SRAM_SIZE (16*1024) /* 16Kb ITCM SRAM on TCM interface */ # else -# define STM32F7_ITCM_SRAM_SIZE (0) /* No ITCM SRAM on TCM interface */ +# define STM32_ITCM_SRAM_SIZE (0) /* No ITCM SRAM on TCM interface */ # endif #else # error STM32 F7 chip Family not identified @@ -309,34 +309,34 @@ /* Common to all Advanced (vs Foundation) Family members */ -#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX) -# define STM32F7_NSPDIFRX 0 /* Not supported */ -# define STM32F7_NGPIO 9 /* 9 GPIO ports, GPIOA-I */ -# define STM32F7_NI2C 3 /* I2C1-3 */ +#if defined(CONFIG_STM32_STM32F72XX) || defined(CONFIG_STM32_STM32F73XX) +# define STM32_NSPDIFRX 0 /* Not supported */ +# define STM32_NGPIO 9 /* 9 GPIO ports, GPIOA-I */ +# define STM32_NI2C 3 /* I2C1-3 */ #else -# define STM32F7_NSPDIFRX 4 /* 4 SPDIFRX inputs */ -# define STM32F7_NGPIO 11 /* 11 GPIO ports, GPIOA-K */ -# define STM32F7_NI2C 4 /* I2C1-4 */ +# define STM32_NSPDIFRX 4 /* 4 SPDIFRX inputs */ +# define STM32_NGPIO 11 /* 11 GPIO ports, GPIOA-K */ +# define STM32_NI2C 4 /* I2C1-4 */ #endif /* Common to all Family members */ -# define STM32F7_NATIM 2 /* Two advanced timers TIM1 and 8 */ -# define STM32F7_NGTIM32 2 /* 32-bit general timers TIM2 and 5 with DMA */ -# define STM32F7_NGTIM16 2 /* 16-bit general timers TIM3 and 4 with DMA */ -# define STM32F7_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ -# define STM32F7_NBTIM 2 /* Two basic timers, TIM6-7 */ -# define STM32F7_NUART 4 /* UART 4-5 and 7-8 */ -# define STM32F7_NUSART 4 /* USART1-3 and 6 */ -# define STM32F7_NI2S 3 /* I2S1-2 (multiplexed with SPI1-3) */ -# define STM32F7_NUSBOTGFS 1 /* USB OTG FS */ -# define STM32F7_NUSBOTGHS 1 /* USB OTG HS */ -# define STM32F7_NSAI 2 /* SAI1-2 */ -# define STM32F7_NDMA 2 /* DMA1-2 */ -# define STM32F7_NADC 3 /* 12-bit ADC1-3, number of channels vary */ -# define STM32F7_NDAC 2 /* 12-bit DAC1-2 */ -# define STM32F7_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32F7_NCRC 1 /* CRC */ +# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ +# define STM32_NGTIM32 2 /* 32-bit general timers TIM2 and 5 with DMA */ +# define STM32_NGTIM16 2 /* 16-bit general timers TIM3 and 4 with DMA */ +# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ +# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ +# define STM32_NUART 4 /* UART 4-5 and 7-8 */ +# define STM32_NUSART 4 /* USART1-3 and 6 */ +# define STM32_NI2S 3 /* I2S1-2 (multiplexed with SPI1-3) */ +# define STM32_NUSBOTGFS 1 /* USB OTG FS */ +# define STM32_NUSBOTGHS 1 /* USB OTG HS */ +# define STM32_NSAI 2 /* SAI1-2 */ +# define STM32_NDMA 2 /* DMA1-2 */ +# define STM32_NADC 3 /* 12-bit ADC1-3, number of channels vary */ +# define STM32_NDAC 2 /* 12-bit DAC1-2 */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ /* TBD FPU Configuration */ @@ -350,83 +350,83 @@ /* Diversification based on Family and package */ -#if defined(CONFIG_STM32F7_HAVE_FMC) -# define STM32F7_NFMC 1 /* Have FMC memory controller */ +#if defined(CONFIG_STM32_HAVE_FMC) +# define STM32_NFMC 1 /* Have FMC memory controller */ #else -# define STM32F7_NFMC 0 /* No FMC memory controller */ +# define STM32_NFMC 0 /* No FMC memory controller */ #endif -#if defined(CONFIG_STM32F7_HAVE_ETHRNET) -# define STM32F7_NETHERNET 1 /* 100/100 Ethernet MAC */ +#if defined(CONFIG_STM32_HAVE_ETHRNET) +# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */ #else -# define STM32F7_NETHERNET 0 /* No 100/100 Ethernet MAC */ +# define STM32_NETHERNET 0 /* No 100/100 Ethernet MAC */ #endif -#if defined(CONFIG_STM32F7_HAVE_RNG) -# define STM32F7_NRNG 1 /* Random number generator (RNG) */ +#if defined(CONFIG_STM32_HAVE_RNG) +# define STM32_NRNG 1 /* Random number generator (RNG) */ #else -# define STM32F7_NRNG 0 /* No Random number generator (RNG) */ +# define STM32_NRNG 0 /* No Random number generator (RNG) */ #endif -#if defined(CONFIG_STM32F7_HAVE_SPI5) && defined(CONFIG_STM32F7_HAVE_SPI6) -# define STM32F7_NSPI 6 /* SPI1-6 (Advanced Family Except V series) */ -#elif defined(CONFIG_STM32F7_HAVE_SPI5) -# define STM32F7_NSPI 5 /* SPI1-5 (Foundation Family Except V & R series) */ -#elif defined(CONFIG_STM32F7_HAVE_SPI4) -# define STM32F7_NSPI 4 /* SPI1-4 V series */ +#if defined(CONFIG_STM32_HAVE_SPI5) && defined(CONFIG_STM32_HAVE_SPI6) +# define STM32_NSPI 6 /* SPI1-6 (Advanced Family Except V series) */ +#elif defined(CONFIG_STM32_HAVE_SPI5) +# define STM32_NSPI 5 /* SPI1-5 (Foundation Family Except V & R series) */ +#elif defined(CONFIG_STM32_HAVE_SPI4) +# define STM32_NSPI 4 /* SPI1-4 V series */ #else -# define STM32F7_NSPI 3 /* SPI1-3 R series */ +# define STM32_NSPI 3 /* SPI1-3 R series */ #endif -#if defined(CONFIG_STM32F7_HAVE_SDMMC2) -# define STM32F7_NSDMMC 2 /* 2 SDMMC interfaces */ +#if defined(CONFIG_STM32_HAVE_SDMMC2) +# define STM32_NSDMMC 2 /* 2 SDMMC interfaces */ #else -# define STM32F7_NSDMMC 1 /* 1 SDMMC interface */ +# define STM32_NSDMMC 1 /* 1 SDMMC interface */ #endif -#if defined(CONFIG_STM32F7_HAVE_CAN3) -# define STM32F7_NCAN 3 /* CAN1-3 */ -#elif defined(CONFIG_STM32F7_HAVE_CAN2) -# define STM32F7_NCAN 2 /* CAN1-2 */ +#if defined(CONFIG_STM32_HAVE_CAN3) +# define STM32_NCAN 3 /* CAN1-3 */ +#elif defined(CONFIG_STM32_HAVE_CAN2) +# define STM32_NCAN 2 /* CAN1-2 */ #else -# define STM32F7_NCAN 1 /* CAN1 only */ +# define STM32_NCAN 1 /* CAN1 only */ #endif -#if defined(CONFIG_STM32F7_HAVE_DCMI) -# define STM32F7_NDCMI 1 /* Digital camera interface (DCMI) */ +#if defined(CONFIG_STM32_HAVE_DCMI) +# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */ #else -# define STM32F7_NDCMI 0 /* No Digital camera interface (DCMI) */ +# define STM32_NDCMI 0 /* No Digital camera interface (DCMI) */ #endif -#if defined(CONFIG_STM32F7_HAVE_DSIHOST) -# define STM32F7_NDSIHOST 1 /* Have MIPI DSI Host */ +#if defined(CONFIG_STM32_HAVE_DSIHOST) +# define STM32_NDSIHOST 1 /* Have MIPI DSI Host */ #else -# define STM32F7_NDSIHOST 0 /* No MIPI DSI Host */ +# define STM32_NDSIHOST 0 /* No MIPI DSI Host */ #endif -#if defined (CONFIG_STM32F7_HAVE_LTDC) -# define STM32F7_NLCDTFT 1 /* One LCD-TFT */ +#if defined (CONFIG_STM32_HAVE_LTDC) +# define STM32_NLCDTFT 1 /* One LCD-TFT */ #else -# define STM32F7_NLCDTFT 0 /* No LCD-TFT */ +# define STM32_NLCDTFT 0 /* No LCD-TFT */ #endif -#if defined(CONFIG_STM32F7_HAVE_DMA2D) /* bf20171107 Swapped defines they were reversed. */ -# define STM32F7_NDMA2D 1 /* DChrom-ART Accelerator™ (DMA2D) */ +#if defined(CONFIG_STM32_HAVE_DMA2D) /* bf20171107 Swapped defines they were reversed. */ +# define STM32_NDMA2D 1 /* DChrom-ART Accelerator™ (DMA2D) */ #else -# define STM32F7_NDMA2D 0 /* No DChrom-ART Accelerator™ (DMA2D) */ +# define STM32_NDMA2D 0 /* No DChrom-ART Accelerator™ (DMA2D) */ #endif -#if defined(CONFIG_STM32F7_HAVE_JPEG) -#define STM32F7_NJPEG 1 /* One JPEG Converter */ +#if defined(CONFIG_STM32_HAVE_JPEG) +#define STM32_NJPEG 1 /* One JPEG Converter */ #else -#define STM32F7_NJPEG 0 /* No JPEG Converter */ +#define STM32_NJPEG 0 /* No JPEG Converter */ #endif -#if defined(CONFIG_STM32F7_HAVE_CRYP) -#define STM32F7_NCRYP 1 /* One CRYP engine */ +#if defined(CONFIG_STM32_HAVE_CRYP) +#define STM32_NCRYP 1 /* One CRYP engine */ #else -#define STM32F7_NCRYP 0 /* No CRYP engine */ +#define STM32_NCRYP 0 /* No CRYP engine */ #endif -#if defined(CONFIG_STM32F7_HAVE_HASH) -#define STM32F7_NHASH 1 /* One HASH engine */ +#if defined(CONFIG_STM32_HAVE_HASH) +#define STM32_NHASH 1 /* One HASH engine */ #else -#define STM32F7_NHASH 0 /* No HASH engine */ +#define STM32_NHASH 0 /* No HASH engine */ #endif -#if defined(CONFIG_STM32F7_HAVE_DFSDM) -#define STM32F7_NDFSDM 4 /* One set of 4 Digital filters */ +#if defined(CONFIG_STM32_HAVE_DFSDM) +#define STM32_NDFSDM 4 /* One set of 4 Digital filters */ #else -#define STM32F7_NDFSDM 0 /* No Digital filters */ +#define STM32_NDFSDM 0 /* No Digital filters */ #endif /* NVIC priority levels *****************************************************/ diff --git a/arch/arm/include/stm32f7/irq.h b/arch/arm/include/stm32f7/irq.h index 3c786310d6806..c755977dfdca5 100644 --- a/arch/arm/include/stm32f7/irq.h +++ b/arch/arm/include/stm32f7/irq.h @@ -69,11 +69,11 @@ * Included Files ****************************************************************************/ -#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX) +#if defined(CONFIG_STM32_STM32F72XX) || defined(CONFIG_STM32_STM32F73XX) # include -#elif defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) +#elif defined(CONFIG_STM32_STM32F74XX) || defined(CONFIG_STM32_STM32F75XX) # include -#elif defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) +#elif defined(CONFIG_STM32_STM32F76XX) || defined(CONFIG_STM32_STM32F77XX) # include #else # error "Unsupported STM32 F7 chip" diff --git a/arch/arm/include/stm32g0/chip.h b/arch/arm/include/stm32g0/chip.h new file mode 100644 index 0000000000000..4c92e149ced06 --- /dev/null +++ b/arch/arm/include/stm32g0/chip.h @@ -0,0 +1,166 @@ +/**************************************************************************** + * arch/arm/include/stm32g0/chip.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_INCLUDE_STM32G0_CHIP_H +#define __ARCH_ARM_INCLUDE_STM32G0_CHIP_H + +#define ARMV6M_PERIPHERAL_INTERRUPTS 32 + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Prototypes + ****************************************************************************/ + +/* Get customizations for each supported chip */ + +#if defined(CONFIG_ARCH_CHIP_STM32G070KB) || defined(CONFIG_ARCH_CHIP_STM32G070CB) || \ + defined(CONFIG_ARCH_CHIP_STM32G070RB) + +# define STM32_FLASH_SIZE (128 * 1024) /* 128Kb */ +# define STM32_SRAM_SIZE (32 * 1024) /* 32Kb */ + +# define STM32_NATIM 1 /* One advanced timer TIM1 */ +# define STM32_NGTIM16 5 /* 16-bit general up/down timers TIM3, + * TIM14-17 */ +# define STM32_NGTIM32 0 /* No 32-bit general up/down timers */ +# define STM32_NBTIM 2 /* Two basic timers: TIM6, TIM7 */ +# define STM32_NSPI 2 /* Two SPI modules SPI1-2 */ +# define STM32_NI2S 1 /* One I2S module (SPI or I2S) */ +# define STM32_NI2C 2 /* Two I2C (1 with SMBus/PMBus) */ +# define STM32_NDMA 1 /* One DMA1, 7-channels */ +# define STM32_NUSART 4 /* Four USART modules, USART1-4 */ +# define STM32_NCAN 0 /* No CAN controllers */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBDEV 0 /* No USB full-speed device controller */ +# define STM32_NUSBOTG 0 /* No USB OTG */ +# define STM32_NCEC 0 /* One HDMI-CEC controller */ +# define STM32_NADC 1 /* (1) ADC1, 16-channels */ + +# define STM32_NDAC 0 /* No DAC */ +# define STM32_NCOMP 0 /* No Analog Comparators */ +# define STM32_NCRC 1 /* No CRC module */ +# define STM32_NRNG 0 /* No Random number generator (RNG) */ +# define STM32_NCAP 0 /* No Capacitive sensing channels */ +# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-F */ + +#elif defined(CONFIG_ARCH_CHIP_STM32G071EB) || defined(CONFIG_ARCH_CHIP_STM32G071G8) || \ + defined(CONFIG_ARCH_CHIP_STM32G071GB) || defined(CONFIG_ARCH_CHIP_STM32G071G8XN) || \ + defined(CONFIG_ARCH_CHIP_STM32G071GBXN) || defined(CONFIG_ARCH_CHIP_STM32G071K8) || \ + defined(CONFIG_ARCH_CHIP_STM32G071KB) || defined(CONFIG_ARCH_CHIP_STM32G071K8XN) || \ + defined(CONFIG_ARCH_CHIP_STM32G071KBXN) || defined(CONFIG_ARCH_CHIP_STM32G071C8) || \ + defined(CONFIG_ARCH_CHIP_STM32G071CB) || defined(CONFIG_ARCH_CHIP_STM32G071R8) || \ + defined(CONFIG_ARCH_CHIP_STM32G071RB) + +# define STM32_NATIM 1 /* One advanced timer TIM1 */ +# define STM32_NGTIM16 4 /* 16-bit general up/down timers TIM2-3 + * (with DMA) and TIM21-22 without DMA */ +# define STM32_NGTIM32 0 /* No 32-bit general up/down timers */ +# define STM32_NBTIM 2 /* Two basic timers: TIM6, TIM7 with DMA */ + /* Two LPTIMER */ +# define STM32_NSPI 2 /* Two SPI modules SPI1-2 */ +# define STM32_NI2C 2 /* Two I2C (2 with SMBus/PMBus) */ +# define STM32_NDMA 1 /* One DMA1, 7-channels */ +# define STM32_NUSART 4 /* Four USART modules, USART1-4 */ + /* One LPUART */ +# define STM32_NCAN 0 /* No CAN controllers */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBDEV 0 /* No USB full-speed device controller */ +# define STM32_NUSBOTG 0 /* No USB OTG */ +# define STM32_NCEC 1 /* One HDMI-CEC controller */ +# define STM32_NADC 1 /* (1) ADC1, 12-channels */ + +# define STM32_NDAC 2 /* Two DAC channels */ +# define STM32_NCOMP 2 /* Two Analog Comparators */ +# define STM32_NCRC 0 /* No CRC module */ +# define STM32_NRNG 0 /* No Random number generator (RNG) */ +# define STM32_NCAP 0 /* No Capacitive sensing channels */ +# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-F */ + +#elif defined(CONFIG_ARCH_CHIP_STM32G0B1KB) || defined(CONFIG_ARCH_CHIP_STM32G0B1CB) || \ + defined(CONFIG_ARCH_CHIP_STM32G0B1RB) || defined(CONFIG_ARCH_CHIP_STM32G0B1MB) || \ + defined(CONFIG_ARCH_CHIP_STM32G0B1VB) || defined(CONFIG_ARCH_CHIP_STM32G0B1KC) || \ + defined(CONFIG_ARCH_CHIP_STM32G0B1CC) || defined(CONFIG_ARCH_CHIP_STM32G0B1RC) || \ + defined(CONFIG_ARCH_CHIP_STM32G0B1MC) || defined(CONFIG_ARCH_CHIP_STM32G0B1VC) || \ + defined(CONFIG_ARCH_CHIP_STM32G0B1KE) || defined(CONFIG_ARCH_CHIP_STM32G0B1CE) || \ + defined(CONFIG_ARCH_CHIP_STM32G0B1RE) || defined(CONFIG_ARCH_CHIP_STM32G0B1NE) || \ + defined(CONFIG_ARCH_CHIP_STM32G0B1ME) || defined(CONFIG_ARCH_CHIP_STM32G0B1VE) + +# define STM32_NATIM 1 /* One advanced timer TIM1 */ +# define STM32_NGTIM16 6 /* 16-bit general purpose timers */ +# define STM32_NGTIM32 1 /* TIM2 */ +# define STM32_NBTIM 2 /* Two basic timers: TIM6, TIM7 with DMA */ + /* One LPTIMER */ +# define STM32_NSPI 3 /* Two SPI modules SPI1-2 */ +# define STM32_NI2C 3 /* Two I2C (2 with SMBus/PMBus) */ +# define STM32_NDMA 2 /* DMA1 7-channels, DMA2 5-channels DMA1 */ +# define STM32_NUSART 6 /* Six USART modules, USART1-6 */ + /* Two LPUART */ +# define STM32_NCAN 1 /* One FDCAN controller */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBDEV 1 /* One USB full-speed controller */ +# define STM32_NUSBOTG 0 /* No USB OTG */ +# define STM32_NCEC 1 /* One HDMI-CEC controller */ +# define STM32_NADC 1 /* (1) ADC1, 12-channels */ + +# define STM32_NDAC 2 /* Two DAC channels */ +# define STM32_NCOMP 3 /* Three Analog Comparators */ +# define STM32_NCRC 0 /* No CRC module */ +# define STM32_NRNG 1 /* One Random number generator (RNG) */ +# define STM32_NCAP 0 /* No Capacitive sensing channels */ +# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-F */ + +/* STM32L EnergyLite Line ***************************************************/ + +/* STM32L073XX - With LCD + * STM32L072XX - No LCD + * STM32L071XX - Access line, no LCD + * + * STM32L0XXX8 - 64KB FLASH, 20KB SRAM, 3KB EEPROM + * STM32L0XXXB - 128KB FLASH, 20KB SRAM, 6KB EEPROM + * STM32L0XXXZ - 192KB FLASH, 20KB SRAM, 3KB EEPROM + * + * STM32L0XXCX - 48-pins + * STM32L0XXRX - 64-pins + * STM32L0XXVX - 100-pins + */ + +#endif + +/* NVIC priority levels *****************************************************/ + +/* Each priority field holds a priority value, 0-31. The lower the value, + * the greater the priority of the corresponding interrupt. The processor + * implements only bits[7:6] of each field, bits[5:0] read as zero and + * ignore writes. + */ + +#define NVIC_SYSH_PRIORITY_MIN 0xc0 /* All bits[7:6] set is minimum priority */ +#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */ +#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */ +#define NVIC_SYSH_PRIORITY_STEP 0x40 /* Two bits of interrupt priority used */ + +#endif /* __ARCH_ARM_INCLUDE_STM32G0_CHIP_H */ diff --git a/arch/arm/include/stm32g0/irq.h b/arch/arm/include/stm32g0/irq.h new file mode 100644 index 0000000000000..1edbcd2b85070 --- /dev/null +++ b/arch/arm/include/stm32g0/irq.h @@ -0,0 +1,183 @@ +/**************************************************************************** + * arch/arm/include/stm32g0/irq.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* This file should never be included directly but, rather, only indirectly + * through nuttx/irq.h + */ + +#ifndef __ARCH_ARM_INCLUDE_STM32G0_IRQ_H +#define __ARCH_ARM_INCLUDE_STM32G0_IRQ_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#ifndef __ASSEMBLY__ +# include +#endif +#include + +/**************************************************************************** + * Pre-processor Prototypes + ****************************************************************************/ + +/* IRQ numbers. The IRQ number corresponds vector number and hence map + * directly to bits in the NVIC. This does, however, waste several words of + * memory in the IRQ to handle mapping tables. + */ + +/* Common Processor Exceptions (vectors 0-15) */ + +#define STM32_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */ + /* Vector 0: Reset stack pointer value */ + /* Vector 1: Reset (not handler as an IRQ) */ +#define STM32_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */ +#define STM32_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */ + /* Vectors 4-10: Reserved */ +#define STM32_IRQ_SVCALL (11) /* Vector 11: SVC call */ + /* Vector 12-13: Reserved */ +#define STM32_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */ +#define STM32_IRQ_SYSTICK (15) /* Vector 15: System tick */ + +/* External interrupts (vectors >= 16) */ + +#define STM32_IRQ_EXTINT (16) /* Vector number of the first external interrupt */ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/* External interrupt vectors */ + +#define STM32_IRQ_WWDG (STM32_IRQ_EXTINT + 0) /* 0: Window Watchdog interrupt */ + +#if defined(CONFIG_ARCH_CHIP_STM32G070KB) || defined(CONFIG_ARCH_CHIP_STM32G070CB) || \ + defined(CONFIG_ARCH_CHIP_STM32G070RB) +# define STM32_IRQ_RESERVED1 (STM32_IRQ_EXTINT + 1) /* 1: Reserved */ +#else +# define STM32_IRQ_PVD (STM32_IRQ_EXTINT + 1) /* 1: PVD through EXTI Line detection interrupt */ +#endif + +#define STM32_IRQ_RTC (STM32_IRQ_EXTINT + 2) /* 2: RTC */ +#define STM32_IRQ_FLASH (STM32_IRQ_EXTINT + 3) /* 3: Flash */ +#define STM32_IRQ_RCC (STM32_IRQ_EXTINT + 4) /* 4: RCC */ +#define STM32_IRQ_EXTI0_1 (STM32_IRQ_EXTINT + 5) /* 5: EXTI0_1 */ +#define STM32_IRQ_EXTI2_3 (STM32_IRQ_EXTINT + 6) /* 6: EXTI2_3 */ +#define STM32_IRQ_EXTI4_15 (STM32_IRQ_EXTINT + 7) /* 7: EXTI4_15 */ + +#if defined(CONFIG_ARCH_CHIP_STM32G070KB) || defined(CONFIG_ARCH_CHIP_STM32G070CB) || \ + defined(CONFIG_ARCH_CHIP_STM32G070RB) +# define STM32_IRQ_RESERVED8 (STM32_IRQ_EXTINT + 8) /* 8: Reserved */ +#else +# define STM32_IRQ_UCPD12 (STM32_IRQ_EXTINT + 8) /* 8: UCPD1_2 */ +# define STM32_IRQ_EXTI32_33 (STM32_IRQ_EXTINT + 8) /* 8: EXTI_32_33 */ +#endif + +#define STM32_IRQ_DMA1CH1 (STM32_IRQ_EXTINT + 9) /* 9: DMA1_CH1 */ +#define STM32_IRQ_DMA1CH2 (STM32_IRQ_EXTINT + 10) /* 10: DMA1_CH2 */ +#define STM32_IRQ_DMA1CH3 (STM32_IRQ_EXTINT + 10) /* 10: DMA1_CH3 */ +#define STM32_IRQ_DMA1CH4 (STM32_IRQ_EXTINT + 11) /* 11: DMA1_CH4 */ +#define STM32_IRQ_DMA1CH5 (STM32_IRQ_EXTINT + 11) /* 11: DMA1_CH5 */ +#define STM32_IRQ_DMA1CH6 (STM32_IRQ_EXTINT + 11) /* 11: DMA1_CH6 */ +#define STM32_IRQ_DMA1CH7 (STM32_IRQ_EXTINT + 11) /* 11: DMA1_CH7 */ +#define STM32_IRQ_DMAMUX (STM32_IRQ_EXTINT + 11) /* 11: DMAMUX */ + +#if defined(CONFIG_STM32_STM32G0BX) || \ + defined(CONFIG_STM32_STM32G0C1) +# define STM32_IRQ_DMA2CH1 (STM32_IRQ_EXTINT + 11) /* 11: DMA2_CH1 */ +# define STM32_IRQ_DMA2CH2 (STM32_IRQ_EXTINT + 11) /* 11: DMA2_CH2 */ +# define STM32_IRQ_DMA2CH3 (STM32_IRQ_EXTINT + 11) /* 11: DMA2_CH3 */ +# define STM32_IRQ_DMA2CH4 (STM32_IRQ_EXTINT + 11) /* 11: DMA2_CH4 */ +# define STM32_IRQ_DMA2CH5 (STM32_IRQ_EXTINT + 11) /* 11: DMA2_CH5 */ +#endif + +#define STM32_IRQ_ADC (STM32_IRQ_EXTINT + 12) /* 12: ADC */ +#define STM32_IRQ_EXTI17_18 (STM32_IRQ_EXTINT + 12) /* 12: EXTI_17_18 */ + +#if defined(CONFIG_ARCH_CHIP_STM32G070KB) || defined(CONFIG_ARCH_CHIP_STM32G070CB) || \ + defined(CONFIG_ARCH_CHIP_STM32G070RB) +#else +# define STM32_IRQ_COMP (STM32_IRQ_EXTINT + 12) /* 12: COMP */ +#endif + +#define STM32_IRQ_TIM1_BRK (STM32_IRQ_EXTINT + 13) /* 13: TIM1_BRK_UP_TRG_COM */ +#define STM32_IRQ_TIM1_CC (STM32_IRQ_EXTINT + 14) /* 14: TIM1_CC */ + +#if defined(CONFIG_ARCH_CHIP_STM32G070KB) || defined(CONFIG_ARCH_CHIP_STM32G070CB) || \ + defined(CONFIG_ARCH_CHIP_STM32G070RB) +# define STM32_IRQ_RESERVED15 (STM32_IRQ_EXTINT + 15) /* 15: Reserved */ +#else +# define STM32_IRQ_TIM2 (STM32_IRQ_EXTINT + 15) /* 15: TIM2 */ +#endif + +#define STM32_IRQ_TIM3 (STM32_IRQ_EXTINT + 16) /* 16: TIM3 */ +#define STM32_IRQ_TIM6 (STM32_IRQ_EXTINT + 17) /* 17: TIM6 */ + +#if defined(CONFIG_ARCH_CHIP_STM32G070KB) || defined(CONFIG_ARCH_CHIP_STM32G070CB) || \ + defined(CONFIG_ARCH_CHIP_STM32G070RB) +#else +# define STM32_IRQ_DAC (STM32_IRQ_EXTINT + 17) /* 17: DAC */ +# define STM32_IRQ_LPTIM1 (STM32_IRQ_EXTINT + 17) /* 17: LPTIM1 */ +#endif + +#define STM32_IRQ_TIM7 (STM32_IRQ_EXTINT + 18) /* 18: TIM7 */ + +#if defined(CONFIG_ARCH_CHIP_STM32G070KB) || defined(CONFIG_ARCH_CHIP_STM32G070CB) || \ + defined(CONFIG_ARCH_CHIP_STM32G070RB) +#else +# define STM32_IRQ_LPTIM2 (STM32_IRQ_EXTINT + 18) /* 18: LPTIM2 */ +#endif + +#define STM32_IRQ_TIM14 (STM32_IRQ_EXTINT + 19) /* 19: TIM14 */ +#define STM32_IRQ_TIM15 (STM32_IRQ_EXTINT + 20) /* 20: TIM15 */ +#define STM32_IRQ_TIM16 (STM32_IRQ_EXTINT + 21) /* 21: TIM16 */ +#define STM32_IRQ_TIM17 (STM32_IRQ_EXTINT + 22) /* 22: TIM17 */ +#define STM32_IRQ_I2C1 (STM32_IRQ_EXTINT + 23) /* 23: I2C1 */ +#define STM32_IRQ_EXTI23 (STM32_IRQ_EXTINT + 23) /* 23: EXTI_23 */ +#define STM32_IRQ_I2C2 (STM32_IRQ_EXTINT + 24) /* 24: I2C2 */ +#define STM32_IRQ_SPI1 (STM32_IRQ_EXTINT + 25) /* 25: SPI1 */ +#define STM32_IRQ_SPI2 (STM32_IRQ_EXTINT + 26) /* 26: SPI2 */ +#define STM32_IRQ_USART1 (STM32_IRQ_EXTINT + 27) /* 27: USART1 */ +#define STM32_IRQ_EXTI25 (STM32_IRQ_EXTINT + 27) /* 27: EXTI_25 */ +#define STM32_IRQ_USART2 (STM32_IRQ_EXTINT + 28) /* 28: USART2 */ +#define STM32_IRQ_EXTI26 (STM32_IRQ_EXTINT + 28) /* 28: EXTI_26 */ +#define STM32_IRQ_USART3 (STM32_IRQ_EXTINT + 29) /* 29: USART3 */ +#define STM32_IRQ_USART4 (STM32_IRQ_EXTINT + 29) /* 29: USART4 */ +#define STM32_IRQ_LPUART1 (STM32_IRQ_EXTINT + 29) /* 29: LPUART1 */ +#define STM32_IRQ_EXTI28 (STM32_IRQ_EXTINT + 29) /* 29: EXTI_28 */ + +#if defined(CONFIG_ARCH_CHIP_STM32G070KB) || defined(CONFIG_ARCH_CHIP_STM32G070CB) || \ + defined(CONFIG_ARCH_CHIP_STM32G070RB) +# define STM32_IRQ_RESERVED30 (STM32_IRQ_EXTINT + 30) /* 30: Reserved */ +# define STM32_IRQ_RESERVED31 (STM32_IRQ_EXTINT + 31) /* 31: Reserved */ +#else +# define STM32_IRQ_CEC (STM32_IRQ_EXTINT + 30) /* 30: HDMI CEC */ +# define STM32_IRQ_EXTI27 (STM32_IRQ_EXTINT + 30) /* 30: EXTI_27 */ +# define STM32_IRQ_AES (STM32_IRQ_EXTINT + 31) /* 31: AES */ +# define STM32_IRQ_RNG (STM32_IRQ_EXTINT + 31) /* 31: RNG */ +#endif + +#define STM32_IRQ_NEXTINTS (32) + +#define NR_IRQS (STM32_IRQ_EXTINT + STM32_IRQ_NEXTINTS) + +#endif /* __ARCH_ARM_INCLUDE_STM32G0_IRQ_H */ diff --git a/arch/arm/include/stm32g4/chip.h b/arch/arm/include/stm32g4/chip.h new file mode 100644 index 0000000000000..f552caac654f4 --- /dev/null +++ b/arch/arm/include/stm32g4/chip.h @@ -0,0 +1,350 @@ +/**************************************************************************** + * arch/arm/include/stm32g4/chip.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_INCLUDE_STM32G4_CHIP_H +#define __ARCH_ARM_INCLUDE_STM32G4_CHIP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Prototypes + ****************************************************************************/ + +/* Get customizations for each supported chip and provide alternate function + * pin-mapping + * + * NOTE: Each GPIO pin may serve either for general purpose I/O or for a + * special alternate function (such as USART, CAN, USB, SDIO, etc.). That + * particular pin-mapping will depend on the package and STM32 family. If + * you are incorporating a new STM32 chip into NuttX, you will need to add + * the pin-mapping to a header file and to include that header file below. + * The chip-specific pin-mapping is defined in the chip datasheet. + */ + +#if defined (CONFIG_ARCH_CHIP_STM32G431K) +# define STM32_NFSMC 0 /* FSMC */ +# define STM32_NATIM 2 /* (2) Advanced motor control timers TIM1, 8 with DMA */ +# define STM32_NGTIM 6 /* (2) 16-bit general timers TIM3 and 4 with DMA + * (1) 32-bit general timers TIM2 with DMA + * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ +# define STM32_NGTIMNDMA 0 /* (0) 16-bit general timers TIM9-14 without DMA */ +# define STM32_NBTIM 2 /* (2) Basic timers, TIM6-7 */ +# define STM32_NDMA 2 /* DMA1-2 */ +# define STM32_NSPI 3 /* SPI1-3 */ +# define STM32_NI2S 2 /* I2S2-3 (multiplexed with SPI2-3) */ +# define STM32_NUSART 2 /* USART1-2 */ +# define STM32_NLPUART 1 /* LPUART1 */ +# define STM32_NI2C 3 /* I2C1-3 */ +# define STM32_NCAN 1 /* FDCAN1 */ +# define STM32_NSDIO 0 /* No SDIO */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (but there is USB 2.0 full-speed + * with LPM and BCD support) */ +# define STM32_NGPIO 26 /* GPIOA-G */ +# define STM32_NADC 2 /* 12-bit ADC1-2 */ +# define STM32_NDAC 2 /* 12-bit DAC1-2, 4 channels (2 external, 2 internal) */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NETHERNET 0 /* No Ethernet MAC */ +# define STM32_NRNG 1 /* Random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + +#elif defined (CONFIG_ARCH_CHIP_STM32G431C) +# define STM32_NFSMC 0 /* FSMC */ +# define STM32_NATIM 2 /* (2) Advanced motor control timers TIM1, 8 with DMA */ +# define STM32_NGTIM 6 /* (2) 16-bit general timers TIM3 and 4 with DMA + * (1) 32-bit general timers TIM2 with DMA + * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ +# define STM32_NGTIMNDMA 0 /* (0) 16-bit general timers TIM9-14 without DMA */ +# define STM32_NBTIM 2 /* (2) Basic timers, TIM6-7 */ +# define STM32_NDMA 2 /* DMA1-2 */ +# define STM32_NSPI 3 /* SPI1-3 */ +# define STM32_NI2S 2 /* I2S2-3 (multiplexed with SPI2-3) */ +# define STM32_NUSART 3 /* USART1-3 */ +# define STM32_NLPUART 1 /* LPUART1 */ +# define STM32_NI2C 3 /* I2C1-3 */ +# define STM32_NCAN 1 /* FDCAN1 */ +# define STM32_NSDIO 0 /* No SDIO */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (but there is USB 2.0 full-speed + * with LPM and BCD support) */ +# define STM32_NGPIO 42 /* GPIOA-G */ +# define STM32_NADC 2 /* 12-bit ADC1-2 */ +# define STM32_NDAC 2 /* 12-bit DAC1-2, 4 channels (2 external, 2 internal) */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NETHERNET 0 /* No Ethernet MAC */ +# define STM32_NRNG 1 /* Random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + +#elif defined (CONFIG_ARCH_CHIP_STM32G431R) +# define STM32_NFSMC 0 /* FSMC */ +# define STM32_NATIM 2 /* (2) Advanced motor control timers TIM1, 8 with DMA */ +# define STM32_NGTIM 6 /* (2) 16-bit general timers TIM3 and 4 with DMA + * (1) 32-bit general timers TIM2 with DMA + * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ +# define STM32_NGTIMNDMA 0 /* (0) 16-bit general timers TIM9-14 without DMA */ +# define STM32_NBTIM 2 /* (2) Basic timers, TIM6-7 */ +# define STM32_NDMA 2 /* DMA1-2 */ +# define STM32_NSPI 3 /* SPI1-3 */ +# define STM32_NI2S 2 /* I2S2-3 (multiplexed with SPI2-3) */ +# define STM32_NUSART 4 /* USART1-3 and UART4*/ +# define STM32_NLPUART 1 /* LPUART1 */ +# define STM32_NI2C 3 /* I2C1-3 */ +# define STM32_NCAN 1 /* FDCAN1 */ +# define STM32_NSDIO 0 /* No SDIO */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (but there is USB 2.0 full-speed + * with LPM and BCD support) */ +# define STM32_NGPIO 52 /* GPIOA-G */ +# define STM32_NADC 2 /* 12-bit ADC1-2 */ +# define STM32_NDAC 2 /* 12-bit DAC1-2, 4 channels (2 external, 2 internal) */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NETHERNET 0 /* No Ethernet MAC */ +# define STM32_NRNG 1 /* Random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + +#elif defined (CONFIG_ARCH_CHIP_STM32G431M) +# define STM32_NFSMC 0 /* FSMC */ +# define STM32_NATIM 2 /* (2) Advanced motor control timers TIM1, 8 with DMA */ +# define STM32_NGTIM 6 /* (2) 16-bit general timers TIM3 and 4 with DMA + * (1) 32-bit general timers TIM2 with DMA + * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ +# define STM32_NGTIMNDMA 0 /* (0) 16-bit general timers TIM9-14 without DMA */ +# define STM32_NBTIM 2 /* (2) Basic timers, TIM6-7 */ +# define STM32_NDMA 2 /* DMA1-2 */ +# define STM32_NSPI 3 /* SPI1-3 */ +# define STM32_NI2S 2 /* I2S2-3 (multiplexed with SPI2-3) */ +# define STM32_NUSART 4 /* USART1-3 and UART4*/ +# define STM32_NLPUART 1 /* LPUART1 */ +# define STM32_NI2C 3 /* I2C1-3 */ +# define STM32_NCAN 1 /* FDCAN1 */ +# define STM32_NSDIO 0 /* No SDIO */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (but there is USB 2.0 full-speed + * with LPM and BCD support) */ +# define STM32_NGPIO 66 /* GPIOA-G */ +# define STM32_NADC 2 /* 12-bit ADC1-2 */ +# define STM32_NDAC 2 /* 12-bit DAC1-2, 4 channels (2 external, 2 internal) */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NETHERNET 0 /* No Ethernet MAC */ +# define STM32_NRNG 1 /* Random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + +#elif defined (CONFIG_ARCH_CHIP_STM32G431V) +# define STM32_NFSMC 0 /* FSMC */ +# define STM32_NATIM 2 /* (2) Advanced motor control timers TIM1, 8 with DMA */ +# define STM32_NGTIM 6 /* (2) 16-bit general timers TIM3 and 4 with DMA + * (1) 32-bit general timers TIM2 with DMA + * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ +# define STM32_NGTIMNDMA 0 /* (0) 16-bit general timers TIM9-14 without DMA */ +# define STM32_NBTIM 2 /* (2) Basic timers, TIM6-7 */ +# define STM32_NDMA 2 /* DMA1-2 */ +# define STM32_NSPI 3 /* SPI1-3 */ +# define STM32_NI2S 2 /* I2S2-3 (multiplexed with SPI2-3) */ +# define STM32_NUSART 4 /* USART1-3 and UART4*/ +# define STM32_NLPUART 1 /* LPUART1 */ +# define STM32_NI2C 3 /* I2C1-3 */ +# define STM32_NCAN 1 /* FDCAN1 */ +# define STM32_NSDIO 0 /* No SDIO */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (but there is USB 2.0 full-speed + * with LPM and BCD support) */ +# define STM32_NGPIO 86 /* GPIOA-G */ +# define STM32_NADC 2 /* 12-bit ADC1-2 */ +# define STM32_NDAC 2 /* 12-bit DAC1-2, 4 channels (2 external, 2 internal) */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NETHERNET 0 /* No Ethernet MAC */ +# define STM32_NRNG 1 /* Random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + +#elif defined (CONFIG_ARCH_CHIP_STM32G474C) +# define STM32_NFSMC 0 /* FSMC */ +# define STM32_NATIM 3 /* (3) Advanced motor control timers TIM1, 8, and 20 with DMA */ +# define STM32_NGTIM 7 /* (2) 16-bit general timers TIM3 and 4 with DMA + * (2) 32-bit general timers TIM2 and 5 with DMA + * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ +# define STM32_NGTIMNDMA 0 /* (0) 16-bit general timers TIM9-14 without DMA */ +# define STM32_NBTIM 2 /* (2) Basic timers, TIM6-7 */ +# define STM32_NDMA 2 /* DMA1-2 */ +# define STM32_NSPI 3 /* SPI1-3 */ +# define STM32_NI2S 2 /* I2S2-3 (multiplexed with SPI2-3) */ +# define STM32_NUSART 3 /* USART1-3 */ +# define STM32_NLPUART 1 /* LPUART1 */ +# define STM32_NI2C 4 /* I2C1-4 */ +# define STM32_NCAN 3 /* FDCAN1-3 */ +# define STM32_NSDIO 0 /* No SDIO */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (but there is USB 2.0 full-speed + * with LPM and BCD support) */ +# define STM32_NGPIO 42 /* GPIOA-C, F-G */ +# define STM32_NADC 5 /* 12-bit ADC1-5 */ +# define STM32_NDAC 4 /* 12-bit DAC1-4, 7 channels (3 external, 4 internal) */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NETHERNET 0 /* No Ethernet MAC */ +# define STM32_NRNG 1 /* Random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + +#elif defined (CONFIG_ARCH_CHIP_STM32G474M) +# define STM32_NFSMC 0 /* FSMC */ +# define STM32_NATIM 3 /* (3) Advanced motor control timers TIM1, 8, and 20 with DMA */ +# define STM32_NGTIM 7 /* (2) 16-bit general timers TIM3 and 4 with DMA + * (2) 32-bit general timers TIM2 and 5 with DMA + * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ +# define STM32_NGTIMNDMA 0 /* (0) 16-bit general timers TIM9-14 without DMA */ +# define STM32_NBTIM 2 /* (2) Basic timers, TIM6-7 */ +# define STM32_NDMA 2 /* DMA1-2 */ +# define STM32_NSPI 4 /* SPI1-4 */ +# define STM32_NI2S 2 /* I2S2-3 (multiplexed with SPI2-3) */ +# define STM32_NUSART 5 /* USART1-3 and UART 4-5 */ +# define STM32_NLPUART 1 /* LPUART1 */ +# define STM32_NI2C 4 /* I2C1-4 */ +# define STM32_NCAN 3 /* FDCAN1-3 */ +# define STM32_NSDIO 0 /* No SDIO */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (but there is USB 2.0 full-speed + * with LPM and BCD support) */ +# define STM32_NGPIO 67 /* GPIOA-G */ +# define STM32_NADC 5 /* 12-bit ADC1-5 */ +# define STM32_NDAC 4 /* 12-bit DAC1-4, 7 channels (3 external, 4 internal) */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NETHERNET 0 /* No Ethernet MAC */ +# define STM32_NRNG 1 /* Random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + +#elif defined (CONFIG_ARCH_CHIP_STM32G474R) +# define STM32_NFSMC 0 /* FSMC */ +# define STM32_NATIM 3 /* (3) Advanced motor control timers TIM1, 8, and 20 with DMA */ +# define STM32_NGTIM 7 /* (2) 16-bit general timers TIM3 and 4 with DMA + * (2) 32-bit general timers TIM2 and 5 with DMA + * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ +# define STM32_NGTIMNDMA 0 /* (0) 16-bit general timers TIM9-14 without DMA */ +# define STM32_NBTIM 2 /* (2) Basic timers, TIM6-7 */ +# define STM32_NDMA 2 /* DMA1-2 */ +# define STM32_NSPI 3 /* SPI1-3 */ +# define STM32_NI2S 2 /* I2S2-3 (multiplexed with SPI2-3) */ +# define STM32_NUSART 5 /* USART1-3 and UART 4-5 */ +# define STM32_NLPUART 1 /* LPUART1 */ +# define STM32_NI2C 4 /* I2C1-4 */ +# define STM32_NCAN 3 /* FDCAN1-3 */ +# define STM32_NSDIO 0 /* No SDIO */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (but there is USB 2.0 full-speed + * with LPM and BCD support) */ +# define STM32_NGPIO 52 /* GPIOA-D, F-G */ +# define STM32_NADC 5 /* 12-bit ADC1-5 */ +# define STM32_NDAC 4 /* 12-bit DAC1-4, 7 channels (3 external, 4 internal) */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NETHERNET 0 /* No Ethernet MAC */ +# define STM32_NRNG 1 /* Random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + +#elif defined (CONFIG_ARCH_CHIP_STM32G474Q) +# define STM32_NFSMC 1 /* FSMC */ +# define STM32_NATIM 3 /* (3) Advanced motor control timers TIM1, 8, and 20 with DMA */ +# define STM32_NGTIM 7 /* (2) 16-bit general timers TIM3 and 4 with DMA + * (2) 32-bit general timers TIM2 and 5 with DMA + * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ +# define STM32_NGTIMNDMA 0 /* (0) 16-bit general timers TIM9-14 without DMA */ +# define STM32_NBTIM 2 /* (2) Basic timers, TIM6-7 */ +# define STM32_NDMA 2 /* DMA1-2 */ +# define STM32_NSPI 4 /* SPI1-4 */ +# define STM32_NI2S 2 /* I2S2-3 (multiplexed with SPI2-3) */ +# define STM32_NUSART 5 /* USART1-3 and UART 4-5 */ +# define STM32_NLPUART 1 /* LPUART1 */ +# define STM32_NI2C 4 /* I2C1-4 */ +# define STM32_NCAN 3 /* FDCAN1-3 */ +# define STM32_NSDIO 0 /* No SDIO */ +# define STM32_NLCD 1 /* LCD parallel interface possible via FMC */ +# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (but there is USB 2.0 full-speed + * with LPM and BCD support) */ +# define STM32_NGPIO 107 /* GPIOA-G */ +# define STM32_NADC 5 /* 12-bit ADC1-5 */ +# define STM32_NDAC 4 /* 12-bit DAC1-4, 7 channels (3 external, 4 internal) */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NETHERNET 0 /* No Ethernet MAC */ +# define STM32_NRNG 1 /* Random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + +#elif defined (CONFIG_ARCH_CHIP_STM32G474V) +# define STM32_NFSMC 1 /* FSMC */ +# define STM32_NATIM 3 /* (3) Advanced motor control timers TIM1, 8, and 20 with DMA */ +# define STM32_NGTIM 7 /* (2) 16-bit general timers TIM3 and 4 with DMA + * (2) 32-bit general timers TIM2 and 5 with DMA + * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ +# define STM32_NGTIMNDMA 0 /* (0) 16-bit general timers TIM9-14 without DMA */ +# define STM32_NBTIM 2 /* (2) Basic timers, TIM6-7 */ +# define STM32_NDMA 2 /* DMA1-2 */ +# define STM32_NSPI 4 /* SPI1-4 */ +# define STM32_NI2S 2 /* I2S2-3 (multiplexed with SPI2-3) */ +# define STM32_NUSART 5 /* USART1-3 and UART 4-5 */ +# define STM32_NLPUART 1 /* LPUART1 */ +# define STM32_NI2C 4 /* I2C1-4 */ +# define STM32_NCAN 3 /* FDCAN1-3 */ +# define STM32_NSDIO 0 /* No SDIO */ +# define STM32_NLCD 1 /* LCD parallel interface possible via FMC */ +# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (but there is USB 2.0 full-speed + * with LPM and BCD support) */ +# define STM32_NGPIO 86 /* GPIOA-G */ +# define STM32_NADC 5 /* 12-bit ADC1-5 */ +# define STM32_NDAC 4 /* 12-bit DAC1-4, 7 channels (3 external, 4 internal) */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NETHERNET 0 /* No Ethernet MAC */ +# define STM32_NRNG 1 /* Random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + +#else +# error "Unsupported STM32 chip" +#endif + +/* Peripheral IP versions ***************************************************/ + +/* Peripheral IP versions are invariant and should be decided here, not in + * Kconfig. + * + * REVISIT: Currently only SPI IP version is handled here, with others being + * handled in Kconfig. Those others need to be gradually refactored + * and resolved here. + */ + +#define STM32_HAVE_IP_SPI_V4 + +/* NVIC priority levels *****************************************************/ + +#define NVIC_SYSH_PRIORITY_MIN 0xf0 /* All bits set in minimum priority */ +#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */ +#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */ +#define NVIC_SYSH_PRIORITY_STEP 0x10 /* Four bits of interrupt priority used */ + +#endif /* __ARCH_ARM_INCLUDE_STM32G4_CHIP_H */ diff --git a/arch/arm/include/stm32g4/irq.h b/arch/arm/include/stm32g4/irq.h new file mode 100644 index 0000000000000..ef6c1fd7fa635 --- /dev/null +++ b/arch/arm/include/stm32g4/irq.h @@ -0,0 +1,225 @@ +/**************************************************************************** + * arch/arm/include/stm32g4/irq.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* This file should never be included directly but, rather, + * only indirectly through nuttx/irq.h + */ + +#ifndef __ARCH_ARM_INCLUDE_STM32G4_IRQ_H +#define __ARCH_ARM_INCLUDE_STM32G4_IRQ_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include + +/**************************************************************************** + * Pre-processor Prototypes + ****************************************************************************/ + +/* IRQ numbers. + * The IRQ number corresponds vector number and hence map directly to + * bits in the NVIC. This does, however, waste several words of memory in + * the IRQ to handle mapping tables. + */ + +/* Processor Exceptions (vectors 0-15) */ + +#define STM32_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */ + /* Vector 0: Reset stack pointer value */ + /* Vector 1: Reset (not handler as an IRQ) */ +#define STM32_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */ +#define STM32_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */ +#define STM32_IRQ_MEMFAULT (4) /* Vector 4: Memory management (MPU) */ +#define STM32_IRQ_BUSFAULT (5) /* Vector 5: Bus fault */ +#define STM32_IRQ_USAGEFAULT (6) /* Vector 6: Usage fault */ +#define STM32_IRQ_SVCALL (11) /* Vector 11: SVC call */ +#define STM32_IRQ_DBGMONITOR (12) /* Vector 12: Debug Monitor */ + /* Vector 13: Reserved */ +#define STM32_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */ +#define STM32_IRQ_SYSTICK (15) /* Vector 15: System tick */ + +/* External interrupts (vectors >= 16). + * These definitions are chip-specific + */ + +#define STM32_IRQ_FIRST (16) /* Vector number of the first external interrupt */ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#define STM32_IRQ_WWDG (STM32_IRQ_FIRST + 0) /* 0: Window Watchdog interrupt */ +#define STM32_IRQ_PVD (STM32_IRQ_FIRST + 1) /* 1: PVD through EXTI Line detection interrupt */ +#define STM32_IRQ_TAMPER (STM32_IRQ_FIRST + 2) /* 2: Tamper interrupt, or Time Stamp (shared with STM32_IRQ_TIMESTAMP) */ +#define STM32_IRQ_TIMESTAMP (STM32_IRQ_FIRST + 2) /* 2: Time stamp interrupt (shared with STM32_IRQ_TAMPER) */ +#define STM32_IRQ_RTC_WKUP (STM32_IRQ_FIRST + 3) /* 3: RTC global interrupt */ +#define STM32_IRQ_FLASH (STM32_IRQ_FIRST + 4) /* 4: Flash global interrupt */ +#define STM32_IRQ_RCC (STM32_IRQ_FIRST + 5) /* 5: RCC global interrupt */ +#define STM32_IRQ_EXTI0 (STM32_IRQ_FIRST + 6) /* 6: EXTI Line 0 interrupt */ +#define STM32_IRQ_EXTI1 (STM32_IRQ_FIRST + 7) /* 7: EXTI Line 1 interrupt */ +#define STM32_IRQ_EXTI2 (STM32_IRQ_FIRST + 8) /* 8: EXTI Line 2 interrupt, or */ +#define STM32_IRQ_EXTI3 (STM32_IRQ_FIRST + 9) /* 9: EXTI Line 3 interrupt */ + +#define STM32_IRQ_EXTI4 (STM32_IRQ_FIRST + 10) /* 10: EXTI Line 4 interrupt */ +#define STM32_IRQ_DMA1CH1 (STM32_IRQ_FIRST + 11) /* 11: DMA1 channel 1 global interrupt */ +#define STM32_IRQ_DMA1CH2 (STM32_IRQ_FIRST + 12) /* 12: DMA1 channel 2 global interrupt */ +#define STM32_IRQ_DMA1CH3 (STM32_IRQ_FIRST + 13) /* 13: DMA1 channel 3 global interrupt */ +#define STM32_IRQ_DMA1CH4 (STM32_IRQ_FIRST + 14) /* 14: DMA1 channel 4 global interrupt */ +#define STM32_IRQ_DMA1CH5 (STM32_IRQ_FIRST + 15) /* 15: DMA1 channel 5 global interrupt */ +#define STM32_IRQ_DMA1CH6 (STM32_IRQ_FIRST + 16) /* 16: DMA1 channel 6 global interrupt */ +#define STM32_IRQ_DMA1CH7 (STM32_IRQ_FIRST + 17) /* 17: DMA1 channel 7 global interrupt */ +#define STM32_IRQ_ADC12 (STM32_IRQ_FIRST + 18) /* 18: ADC1 and ADC2 shared global interrupt */ +#define STM32_IRQ_USBHP (STM32_IRQ_FIRST + 19) /* 19: USB High priority interrupt */ + +#define STM32_IRQ_USBLP (STM32_IRQ_FIRST + 20) /* 20: USB Low priority interrupt */ +#define STM32_IRQ_FDCAN1_0 (STM32_IRQ_FIRST + 21) /* 21: FDCAN1 interrupt 0 */ +#define STM32_IRQ_FDCAN1_1 (STM32_IRQ_FIRST + 22) /* 22: FDCAN1 interrupt 1 */ +#define STM32_IRQ_EXTI95 (STM32_IRQ_FIRST + 23) /* 23: EXTI Line[9:5] interrupts */ +#define STM32_IRQ_TIM15 (STM32_IRQ_FIRST + 24) /* 24: TIM15 global interrupt (shared with STM32_IRQ_TIM1BRK) */ +#define STM32_IRQ_TIM1BRK (STM32_IRQ_FIRST + 24) /* 24: TIM1 Break, Transition error, Index error (shared with STM32_IRQ_TIM15) */ +#define STM32_IRQ_TIM16 (STM32_IRQ_FIRST + 25) /* 25: TIM16 global interrupt (shared with STM32_IRQ_TIM1UP) */ +#define STM32_IRQ_TIM1UP (STM32_IRQ_FIRST + 25) /* 25: TIM1 Update interrupt (shared with STM32_IRQ_TIM16) */ +#define STM32_IRQ_TIM17 (STM32_IRQ_FIRST + 26) /* 26: TIM17 global interrupt (shared with STM32_IRQ_TIM1TRGCOM) */ +#define STM32_IRQ_TIM1TRGCOM (STM32_IRQ_FIRST + 26) /* 26: TIM1 Trigger, Commutation, Direction Change, and Index interrupt (shared with STM32_IRQ_TIM17) */ +#define STM32_IRQ_TIM1CC (STM32_IRQ_FIRST + 27) /* 27: TIM1 Capture Compare interrupt */ +#define STM32_IRQ_TIM2 (STM32_IRQ_FIRST + 28) /* 28: TIM2 global interrupt */ +#define STM32_IRQ_TIM3 (STM32_IRQ_FIRST + 29) /* 29: TIM3 global interrupt */ + +#define STM32_IRQ_TIM4 (STM32_IRQ_FIRST + 30) /* 30: TIM4 global interrupt */ +#define STM32_IRQ_I2C1EV (STM32_IRQ_FIRST + 31) /* 31: I2C1 event interrupt */ +#define STM32_IRQ_I2C1ER (STM32_IRQ_FIRST + 32) /* 32: I2C1 error interrupt */ +#define STM32_IRQ_I2C2EV (STM32_IRQ_FIRST + 33) /* 33: I2C2 event interrupt */ +#define STM32_IRQ_I2C2ER (STM32_IRQ_FIRST + 34) /* 34: I2C2 error interrupt */ +#define STM32_IRQ_SPI1 (STM32_IRQ_FIRST + 35) /* 35: SPI1 global interrupt */ +#define STM32_IRQ_SPI2 (STM32_IRQ_FIRST + 36) /* 36: SPI2 global interrupt */ +#define STM32_IRQ_USART1 (STM32_IRQ_FIRST + 37) /* 37: USART1 global interrupt */ +#define STM32_IRQ_USART2 (STM32_IRQ_FIRST + 38) /* 38: USART2 global interrupt */ +#define STM32_IRQ_USART3 (STM32_IRQ_FIRST + 39) /* 39: USART3 global interrupt */ + +#define STM32_IRQ_EXTI1510 (STM32_IRQ_FIRST + 40) /* 40: EXTI Line[15:10] interrupts */ +#define STM32_IRQ_RTCALRM (STM32_IRQ_FIRST + 41) /* 41: RTC alarm through EXTI line interrupt */ +#define STM32_IRQ_USBWKUP (STM32_IRQ_FIRST + 42) /* 42: 42: USB wakeup from suspend through EXTI line interrupt */ +#define STM32_IRQ_TIM8BRK (STM32_IRQ_FIRST + 43) /* 43: TIM8 Break, Transition error, Index error */ +#define STM32_IRQ_TIM8UP (STM32_IRQ_FIRST + 44) /* 44: TIM8 Update interrupt */ +#define STM32_IRQ_TIM8TRGCOM (STM32_IRQ_FIRST + 45) /* 45: TIM8 Trigger, Commutation, Direction Change, and Index interrupt */ +#define STM32_IRQ_TIM8CC (STM32_IRQ_FIRST + 46) /* 46: TIM8 Capture Compare interrupt */ +#define STM32_IRQ_ADC3 (STM32_IRQ_FIRST + 47) /* 47: ADC3 global interrupt */ +#define STM32_IRQ_FMC (STM32_IRQ_FIRST + 48) /* 48: FMC global interrupt */ +#define STM32_IRQ_LPTIM1 (STM32_IRQ_FIRST + 49) /* 49: LPTIM1 interrupt */ + +#define STM32_IRQ_TIM5 (STM32_IRQ_FIRST + 50) /* 50: TIM5 global interrupt */ +#define STM32_IRQ_SPI3 (STM32_IRQ_FIRST + 51) /* 51: SPI3 global interrupt */ +#define STM32_IRQ_UART4 (STM32_IRQ_FIRST + 52) /* 52: UART4 global interrupt */ +#define STM32_IRQ_UART5 (STM32_IRQ_FIRST + 53) /* 53: UART5 global interrupt */ +#define STM32_IRQ_TIM6 (STM32_IRQ_FIRST + 54) /* 54: TIM6 global interrupt (shared with STM32_IRQ_DAC1, STM32_IRQ_DAC3) */ +#define STM32_IRQ_DAC1 (STM32_IRQ_FIRST + 54) /* 54: DAC1 underrun error interrupt (shared with STM32_IRQ_TIM6, STM32_IRQ_DAC3) */ +#define STM32_IRQ_DAC3 (STM32_IRQ_FIRST + 54) /* 54: DAC3 underrun error interrupt (shared with STM32_IRQ_TIM6, STM32_IRQ_DAC1) */ +#define STM32_IRQ_TIM7 (STM32_IRQ_FIRST + 55) /* 55: TIM7 global interrupt (shared with STM32_IRQ_DAC2, STM32_IRQ_DAC4) */ +#define STM32_IRQ_DAC2 (STM32_IRQ_FIRST + 55) /* 55: DAC2 underrun error interrupt (shared with STM32_IRQ_TIM7) */ +#define STM32_IRQ_DAC4 (STM32_IRQ_FIRST + 55) /* 55: DAC4 underrun error interrupt (shared with STM32_IRQ_TIM7) */ +#define STM32_IRQ_DMA2CH1 (STM32_IRQ_FIRST + 56) /* 56: DMA2 channel 1 global interrupt */ +#define STM32_IRQ_DMA2CH2 (STM32_IRQ_FIRST + 57) /* 57: DMA2 channel 2 global interrupt */ +#define STM32_IRQ_DMA2CH3 (STM32_IRQ_FIRST + 58) /* 58: DMA2 channel 3 global interrupt */ +#define STM32_IRQ_DMA2CH4 (STM32_IRQ_FIRST + 59) /* 59: DMA2 channel 4 global interrupt */ + +#define STM32_IRQ_DMA2CH5 (STM32_IRQ_FIRST + 60) /* 60: DMA2 channel 5 global interrupt */ +#define STM32_IRQ_ADC4 (STM32_IRQ_FIRST + 61) /* 61: ADC4 global interrupt */ +#define STM32_IRQ_ADC5 (STM32_IRQ_FIRST + 62) /* 62: ADC5 global interrupt */ +#define STM32_IRQ_UCPD (STM32_IRQ_FIRST + 63) /* 63: UCPD global interrupt */ +#define STM32_IRQ_COMP123 (STM32_IRQ_FIRST + 64) /* 64: COMP1, COMP2, and COMP3 interrupts */ +#define STM32_IRQ_COMP456 (STM32_IRQ_FIRST + 65) /* 65: COMP4, COMP5, and COMP6 interrupts */ +#define STM32_IRQ_COMP7 (STM32_IRQ_FIRST + 66) /* 66: COMPP7 interrupt */ +#define STM32_IRQ_HRTIM1MST (STM32_IRQ_FIRST + 67) /* 67: HRTIM1 master timer interrupt */ +#define STM32_IRQ_HRTIM1TIMA (STM32_IRQ_FIRST + 68) /* 68: HRTIM1 timer A interrupt */ +#define STM32_IRQ_HRTIM1TIMB (STM32_IRQ_FIRST + 69) /* 69: HRTIM1 timer B interrupt */ + +#define STM32_IRQ_HRTIM1TIMC (STM32_IRQ_FIRST + 70) /* 70: HRTIM1 timer C interrupt */ +#define STM32_IRQ_HRTIM1TIMD (STM32_IRQ_FIRST + 71) /* 71: HRTIM1 timer D interrupt */ +#define STM32_IRQ_HRTIM1TIME (STM32_IRQ_FIRST + 72) /* 72: HRTIM1 timer E interrupt */ +#define STM32_IRQ_HRTIM1FLT (STM32_IRQ_FIRST + 73) /* 73: HRTIM1 fault interrupt */ +#define STM32_IRQ_HRTIM1TIMF (STM32_IRQ_FIRST + 74) /* 74: HRTIM1 timer E interrupt */ +#define STM32_IRQ_CRS (STM32_IRQ_FIRST + 75) /* 75: CRS (Clock Recovery System) global interrupt */ +#define STM32_IRQ_SAI1 (STM32_IRQ_FIRST + 76) /* 76: SAI4 global interrupt */ +#define STM32_IRQ_TIM20BRK (STM32_IRQ_FIRST + 77) /* 77: TIM20 Break, Transition error, Index error interrupt */ +#define STM32_IRQ_TIM20UP (STM32_IRQ_FIRST + 78) /* 78: TIM20 Update interrupt */ +#define STM32_IRQ_TIM20TRGCOM (STM32_IRQ_FIRST + 79) /* 79: TIM20 Trigger, Commutation, Direction Change, and Index interrupt */ + +#define STM32_IRQ_TIM20CC (STM32_IRQ_FIRST + 80) /* 80: TIM20 Capture Compare interrupt */ +#define STM32_IRQ_FPU (STM32_IRQ_FIRST + 81) /* 81: FPU global interrupt */ +#define STM32_IRQ_I2C4EV (STM32_IRQ_FIRST + 82) /* 82: I2C4 event interrupt */ +#define STM32_IRQ_I2C4ER (STM32_IRQ_FIRST + 83) /* 83: I2C4 error interrupt */ +#define STM32_IRQ_SPI4 (STM32_IRQ_FIRST + 84) /* 84: SPI4 global interrupt */ +#define STM32_IRQ_AES (STM32_IRQ_FIRST + 85) /* 85: AES global interrupt */ +#define STM32_IRQ_FDCAN2_0 (STM32_IRQ_FIRST + 86) /* 86: FDCAN2 interrupt 0 */ +#define STM32_IRQ_FDCAN2_1 (STM32_IRQ_FIRST + 87) /* 87: FDCAN2 interrupt 1 */ +#define STM32_IRQ_FDCAN3_0 (STM32_IRQ_FIRST + 88) /* 88: FDCAN3 interrupt 0 */ +#define STM32_IRQ_FDCAN3_1 (STM32_IRQ_FIRST + 89) /* 89: FDCAN3 interrupt 1 */ + +#define STM32_IRQ_RNG (STM32_IRQ_FIRST + 90) /* 90: RNG global interrupt */ +#define STM32_IRQ_LPUART (STM32_IRQ_FIRST + 91) /* 91: LPUART global interrupt */ +#define STM32_IRQ_I2C3EV (STM32_IRQ_FIRST + 92) /* 92: I2C3 event interrupt */ +#define STM32_IRQ_I2C3ER (STM32_IRQ_FIRST + 93) /* 93: I2C3 error interrupt */ +#define STM32_IRQ_DMAMUXOV (STM32_IRQ_FIRST + 94) /* 94: DMAMUX overrun interrupt */ +#define STM32_IRQ_QUADSPI (STM32_IRQ_FIRST + 95) /* 95: QuadSPI global interrupt */ +#define STM32_IRQ_DMA1CH8 (STM32_IRQ_FIRST + 96) /* 96: DMA1 channel 8 global interrupt */ +#define STM32_IRQ_DMA2CH6 (STM32_IRQ_FIRST + 97) /* 97: DMA2 channel 6 global interrupt */ +#define STM32_IRQ_DMA2CH7 (STM32_IRQ_FIRST + 98) /* 98: DMA2 channel 7 global interrupt */ +#define STM32_IRQ_DMA2CH8 (STM32_IRQ_FIRST + 99) /* 99: DMA2 channel 8 global interrupt */ + +#define STM32_IRQ_CORDIC (STM32_IRQ_FIRST + 100) /* 100: CORDIC trigonometric accelerator interrupt */ +#define STM32_IRQ_FMAC (STM32_IRQ_FIRST + 101) /* 101: FMAC filter math accelerator interrupt */ + +#define STM32_IRQ_NEXTINTS (102) +#define NR_IRQS (STM32_IRQ_FIRST + 102) + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#ifndef __ASSEMBLY__ +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#undef EXTERN +#ifdef __cplusplus +} +#endif +#endif + +#endif /* __ARCH_ARM_INCLUDE_STM32G4_IRQ_H */ diff --git a/arch/arm/include/stm32h5/chip.h b/arch/arm/include/stm32h5/chip.h index 3db5fd6905a80..da0f658d7892b 100644 --- a/arch/arm/include/stm32h5/chip.h +++ b/arch/arm/include/stm32h5/chip.h @@ -33,66 +33,66 @@ * Pre-processor Prototypes ****************************************************************************/ -#if defined(CONFIG_STM32H5_STM32H52XXX) || defined(CONFIG_STM32H5_STM32H53XXX) -# define STM32H5_SRAM1_SIZE (128*1024) /* 192Kb SRAM1 on AHB bus Matrix */ -# define STM32H5_SRAM2_SIZE (80*1024) /* 80Kb SRAM2 on AHB bus Matrix */ -# define STM32H5_SRAM3_SIZE (64*1024) /* 64Kb SRAM3 on AHB bus Matrix */ -#elif defined(CONFIG_STM32H5_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX) -# define STM32H5_SRAM1_SIZE (256*1024) /* 192Kb SRAM1 on AHB bus Matrix */ -# define STM32H5_SRAM2_SIZE (64*1024) /* 64Kb SRAM2 on AHB bus Matrix */ -# define STM32H5_SRAM3_SIZE (320*1024) /* 320Kb SRAM3 on AHB bus Matrix */ +#if defined(CONFIG_STM32_STM32H52XXX) || defined(CONFIG_STM32_STM32H53XXX) +# define STM32_SRAM1_SIZE (128*1024) /* 192Kb SRAM1 on AHB bus Matrix */ +# define STM32_SRAM2_SIZE (80*1024) /* 80Kb SRAM2 on AHB bus Matrix */ +# define STM32_SRAM3_SIZE (64*1024) /* 64Kb SRAM3 on AHB bus Matrix */ +#elif defined(CONFIG_STM32_STM32H56XXX) || defined(CONFIG_STM32_STM32H57XXX) +# define STM32_SRAM1_SIZE (256*1024) /* 192Kb SRAM1 on AHB bus Matrix */ +# define STM32_SRAM2_SIZE (64*1024) /* 64Kb SRAM2 on AHB bus Matrix */ +# define STM32_SRAM3_SIZE (320*1024) /* 320Kb SRAM3 on AHB bus Matrix */ #else # error "Unsupported STM32H5 chip" #endif -#define STM32H5_NFSMC (1) /* Have FSMC memory controller */ -#define STM32H5_NATIM (2) /* Two advanced timers TIM1 and TIM8 */ -#define STM32H5_NGTIM32 (2) /* 32-bit general timers TIM2 and 5 with DMA */ -#define STM32H5_NGTIM16 (2) /* 16-bit general timers TIM3 and 4 with DMA */ -#define STM32H5_NGTIMNDMA (3) /* 16-bit general timers TIM15-17 without DMA */ -#define STM32H5_NBTIM (2) /* Two basic timers, TIM6-7 */ -#define STM32H5_NLPTIM (6) /* Six low-power timers, LPTIM1-LPTIM6. */ -#define STM32H5_NRNG (1) /* Random number generator (RNG) */ - -#if defined(CONFIG_STM32H5_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX) -# define STM32H5_NUART (6) /* UART 4-5, 7-8, 9, 12 */ -# define STM32H5_NUSART (5) /* USART 1-3, 6, 10-11 */ -#elif defined(CONFIG_STM32H5_STM32H52XXX) || defined(CONFIG_STM32H5_STM32H53XXX) -# define STM32H5_NUART (2) /* UART 4-5 */ -# define STM32H5_NUSART (4) /* USART 1-3, 6*/ +#define STM32_NFSMC (1) /* Have FSMC memory controller */ +#define STM32_NATIM (2) /* Two advanced timers TIM1 and TIM8 */ +#define STM32_NGTIM32 (2) /* 32-bit general timers TIM2 and 5 with DMA */ +#define STM32_NGTIM16 (2) /* 16-bit general timers TIM3 and 4 with DMA */ +#define STM32_NGTIMNDMA (3) /* 16-bit general timers TIM15-17 without DMA */ +#define STM32_NBTIM (2) /* Two basic timers, TIM6-7 */ +#define STM32_NLPTIM (6) /* Six low-power timers, LPTIM1-LPTIM6. */ +#define STM32_NRNG (1) /* Random number generator (RNG) */ + +#if defined(CONFIG_STM32_STM32H56XXX) || defined(CONFIG_STM32_STM32H57XXX) +# define STM32_NUART (6) /* UART 4-5, 7-8, 9, 12 */ +# define STM32_NUSART (5) /* USART 1-3, 6, 10-11 */ +#elif defined(CONFIG_STM32_STM32H52XXX) || defined(CONFIG_STM32_STM32H53XXX) +# define STM32_NUART (2) /* UART 4-5 */ +# define STM32_NUSART (4) /* USART 1-3, 6*/ #endif -#define STM32H5_NLPUART (1) /* LPUART 1 */ -#define STM32H5_QSPI (0) /* No QuadSPI1 */ -#define STM32H5_OCTOSPI (1) /* OCTOSPI1*/ +#define STM32_NLPUART (1) /* LPUART 1 */ +#define STM32_QSPI (0) /* No QuadSPI1 */ +#define STM32_OCTOSPI (1) /* OCTOSPI1*/ -#if defined(CONFIG_STM32H5_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX) -# define STM32H5_NSPI (6) /* SPI1-SPI6 */ -# define STM32H5_NI2C (4) /* I2C1-4 */ -#elif defined(CONFIG_STM32H5_STM32H52XXX) || defined(CONFIG_STM32H5_STM32H53XXX) -# define STM32H5_NSPI (3) /* SPI1-SPI3 */ -# define STM32H5_NI2C (3) /* I2C1-3 */ +#if defined(CONFIG_STM32_STM32H56XXX) || defined(CONFIG_STM32_STM32H57XXX) +# define STM32_NSPI (6) /* SPI1-SPI6 */ +# define STM32_NI2C (4) /* I2C1-4 */ +#elif defined(CONFIG_STM32_STM32H52XXX) || defined(CONFIG_STM32_STM32H53XXX) +# define STM32_NSPI (3) /* SPI1-SPI3 */ +# define STM32_NI2C (3) /* I2C1-3 */ #endif -#define STM32H5_NSWPMI (0) /* No SWPMI1 */ -#define STM32H5_NUSBOTGFS (0) /* USB OTG FS */ -#define STM32H5_NUSBFS (1) /* No USB FS */ -#define STM32H5_NCAN (2) /* CAN1 */ -#define STM32H5_NSAI (2) /* SAI1-2 */ +#define STM32_NSWPMI (0) /* No SWPMI1 */ +#define STM32_NUSBOTGFS (0) /* USB OTG FS */ +#define STM32_NUSBFS (1) /* No USB FS */ +#define STM32_NCAN (2) /* CAN1 */ +#define STM32_NSAI (2) /* SAI1-2 */ -#if defined(CONFIG_STM32H5_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX) -# define STM32H5_NSDMMC (2) /* SDMMC interface */ -#elif defined(CONFIG_STM32H5_STM32H52XXX) || defined(CONFIG_STM32H5_STM32H53XXX) -# define STM32H5_NSDMMC (1) /* SDMMC interface */ +#if defined(CONFIG_STM32_STM32H56XXX) || defined(CONFIG_STM32_STM32H57XXX) +# define STM32_NSDMMC (2) /* SDMMC interface */ +#elif defined(CONFIG_STM32_STM32H52XXX) || defined(CONFIG_STM32_STM32H53XXX) +# define STM32_NSDMMC (1) /* SDMMC interface */ #endif -#define STM32H5_NDMA (2) /* DMA1-2 */ -#define STM32H5_NPORTS (8) /* 8 GPIO ports, GPIOA-GPIOI */ -#define STM32H5_NADC (2) /* 12-bit ADC1, up to 20 channels */ -#define STM32H5_NDAC (1) /* 12-bit DAC1 */ -#define STM32H5_NCRC (1) /* CRC */ -#define STM32H5_NCOMP (0) /* Comparators */ -#define STM32H5_NOPAMP (0) /* Operational Amplifiers */ +#define STM32_NDMA (2) /* DMA1-2 */ +#define STM32_NPORTS (8) /* 8 GPIO ports, GPIOA-GPIOI */ +#define STM32_NADC (2) /* 12-bit ADC1, up to 20 channels */ +#define STM32_NDAC (1) /* 12-bit DAC1 */ +#define STM32_NCRC (1) /* CRC */ +#define STM32_NCOMP (0) /* Comparators */ +#define STM32_NOPAMP (0) /* Operational Amplifiers */ /* NVIC priority levels *****************************************************/ @@ -103,10 +103,10 @@ #define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */ #define NVIC_SYSH_PRIORITY_STEP 0x10 /* Four bits of interrupt priority used */ -#if defined(CONFIG_STM32H5_HAVE_ETHERNET) -# define STM32H5_NETHERNET 1 /* Ethernet MAC */ +#if defined(CONFIG_STM32_HAVE_ETHERNET) +# define STM32_NETHERNET 1 /* Ethernet MAC */ #else -# define STM32H5_NETHERNET 0 /* No Ethernet MAC */ +# define STM32_NETHERNET 0 /* No Ethernet MAC */ #endif #endif /* __ARCH_ARM_INCLUDE_STM32H5_CHIP_H */ diff --git a/arch/arm/include/stm32h5/irq.h b/arch/arm/include/stm32h5/irq.h index 945ef81a9f2a2..68c53b2704ec2 100644 --- a/arch/arm/include/stm32h5/irq.h +++ b/arch/arm/include/stm32h5/irq.h @@ -65,8 +65,8 @@ #define STM32_IRQ_FIRST (16) /* Vector number of the first external interrupt */ -#if defined(CONFIG_STM32H5_STM32H52XXX) || defined(CONFIG_STM32H5_STM32H53XXX) || \ - defined(CONFIG_STM32H5_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX) +#if defined(CONFIG_STM32_STM32H52XXX) || defined(CONFIG_STM32_STM32H53XXX) || \ + defined(CONFIG_STM32_STM32H56XXX) || defined(CONFIG_STM32_STM32H57XXX) # include #else # error "Unsupported STM32 H5 chip" diff --git a/arch/arm/include/stm32h5/stm32h5xx_irq.h b/arch/arm/include/stm32h5/stm32h5xx_irq.h index 6c3746e1fcc60..b6582c3ec075f 100644 --- a/arch/arm/include/stm32h5/stm32h5xx_irq.h +++ b/arch/arm/include/stm32h5/stm32h5xx_irq.h @@ -119,7 +119,7 @@ # define STM32_IRQ_ADC2 (STM32_IRQ_FIRST + 69) /* 69: ADC2 global interrupt */ # define STM32_IRQ_LPTIM2 (STM32_IRQ_FIRST + 70) /* 70: LPTIM2 global interrupt */ # define STM32_IRQ_TIM15 (STM32_IRQ_FIRST + 71) /* 71: TIM15 global interrupt */ -#if defined(CONFIG_STM32H5_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX) +#if defined(CONFIG_STM32_STM32H56XXX) || defined(CONFIG_STM32_STM32H57XXX) # define STM32_IRQ_TIM16 (STM32_IRQ_FIRST + 72) /* 72: TIM16 global interrupt */ # define STM32_IRQ_TIM17 (STM32_IRQ_FIRST + 73) /* 73: TIM17 global interrupt */ #endif @@ -132,12 +132,12 @@ # define STM32_IRQ_I2C3_EV (STM32_IRQ_FIRST + 80) /* 80: I2C3_EV global interrupt */ # define STM32_IRQ_I2C3_ER (STM32_IRQ_FIRST + 81) /* 81: I2C3_ER global interrupt */ # define STM32_IRQ_SPI4 (STM32_IRQ_FIRST + 82) /* 82: SPI4 global interrupt */ -#if defined(CONFIG_STM32H5_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX) +#if defined(CONFIG_STM32_STM32H56XXX) || defined(CONFIG_STM32_STM32H57XXX) # define STM32_IRQ_SPI5 (STM32_IRQ_FIRST + 83) /* 83: SPI5 global interrupt */ # define STM32_IRQ_SPI6 (STM32_IRQ_FIRST + 84) /* 84: SPI6 global interrupt */ #endif # define STM32_IRQ_USART6 (STM32_IRQ_FIRST + 85) /* 85: USART6 global interrupt */ -#if defined(CONFIG_STM32H5_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX) +#if defined(CONFIG_STM32_STM32H56XXX) || defined(CONFIG_STM32_STM32H57XXX) # define STM32_IRQ_USART10 (STM32_IRQ_FIRST + 86) /* 86: USART10 global interrupt */ # define STM32_IRQ_USART11 (STM32_IRQ_FIRST + 87) /* 87: USART11 global interrupt */ # define STM32_IRQ_SAI1 (STM32_IRQ_FIRST + 88) /* 88: SAI1 global interrupt */ @@ -151,7 +151,7 @@ # define STM32_IRQ_GPDMA2_CH5 (STM32_IRQ_FIRST + 95) /* 95: GPDMA2_CH5 global interrupt */ # define STM32_IRQ_GPDMA2_CH6 (STM32_IRQ_FIRST + 96) /* 96: GPDMA2_CH6 global interrupt */ # define STM32_IRQ_GPDMA2_CH7 (STM32_IRQ_FIRST + 97) /* 97: GPDMA2_CH7 global interrupt */ -#if defined(CONFIG_STM32H5_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX) +#if defined(CONFIG_STM32_STM32H56XXX) || defined(CONFIG_STM32_STM32H57XXX) # define STM32_IRQ_UART7 (STM32_IRQ_FIRST + 98) /* 98: UART7 global interrupt */ # define STM32_IRQ_UART8 (STM32_IRQ_FIRST + 99) /* 99: UART8 global interrupt */ # define STM32_IRQ_UART9 (STM32_IRQ_FIRST + 100) /* 100: UART9 global interrupt */ @@ -161,14 +161,14 @@ # define STM32_IRQ_FPU (STM32_IRQ_FIRST + 103) /* 103: FPU global interrupt */ # define STM32_IRQ_ICACHE (STM32_IRQ_FIRST + 104) /* 104: ICACHE global interrupt */ # define STM32_IRQ_DCACHE (STM32_IRQ_FIRST + 105) /* 105: DCACHE global interrupt */ -#if defined(CONFIG_STM32H5_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX) +#if defined(CONFIG_STM32_STM32H56XXX) || defined(CONFIG_STM32_STM32H57XXX) # define STM32_IRQ_ETH (STM32_IRQ_FIRST + 106) /* 106: ETH global interrupt */ # define STM32_IRQ_ETH_WKUP (STM32_IRQ_FIRST + 107) /* 107: ETH_WKUP global interrupt */ #endif # define STM32_IRQ_DCMI_PSSI (STM32_IRQ_FIRST + 108) /* 108: DCMI PSSI global interrupt */ # define STM32_IRQ_FDCAN2_IT0 (STM32_IRQ_FIRST + 109) /* 109: FDCAN2_IT0 global interrupt */ # define STM32_IRQ_FDCAN2_IT1 (STM32_IRQ_FIRST + 110) /* 110: FDCAN2_IT1 global interrupt */ -#if defined(CONFIG_STM32H5_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX) +#if defined(CONFIG_STM32_STM32H56XXX) || defined(CONFIG_STM32_STM32H57XXX) # define STM32_IRQ_CORDIC (STM32_IRQ_FIRST + 111) /* 111: CORDIC global interrupt */ # define STM32_IRQ_FMAC (STM32_IRQ_FIRST + 112) /* 112: FMAC global interrupt */ #endif @@ -180,13 +180,13 @@ # define STM32_IRQ_PKA (STM32_IRQ_FIRST + 118) /* 118: PKA global interrupt */ # define STM32_IRQ_CEC (STM32_IRQ_FIRST + 119) /* 119: CEC global interrupt */ # define STM32_IRQ_TIM12 (STM32_IRQ_FIRST + 120) /* 120: TIM12 global interrupt */ -#if defined(CONFIG_STM32H5_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX) +#if defined(CONFIG_STM32_STM32H56XXX) || defined(CONFIG_STM32_STM32H57XXX) # define STM32_IRQ_TIM13 (STM32_IRQ_FIRST + 121) /* 121: TIM13 global interrupt */ # define STM32_IRQ_TIM14 (STM32_IRQ_FIRST + 122) /* 122: TIM14 global interrupt */ #endif # define STM32_IRQ_I3C1_EV (STM32_IRQ_FIRST + 123) /* 123: I3C1_EV global interrupt */ # define STM32_IRQ_I3C1_ER (STM32_IRQ_FIRST + 124) /* 124: I3C1_ER global interrupt */ -#if defined(CONFIG_STM32H5_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX) +#if defined(CONFIG_STM32_STM32H56XXX) || defined(CONFIG_STM32_STM32H57XXX) # define STM32_IRQ_I2C4_EV (STM32_IRQ_FIRST + 125) /* 125: I2C4_EV global interrupt */ # define STM32_IRQ_I2C4_ER (STM32_IRQ_FIRST + 126) /* 126: I2C4_ER global interrupt */ # define STM32_IRQ_LPTIM3 (STM32_IRQ_FIRST + 127) /* 127: LPTIM3 global interrupt */ @@ -194,14 +194,14 @@ # define STM32_IRQ_LPTIM5 (STM32_IRQ_FIRST + 129) /* 129: LPTIM5 global interrupt */ # define STM32_IRQ_LPTIM6 (STM32_IRQ_FIRST + 130) /* 130: LPTIM6 global interrupt */ #endif -#if defined(CONFIG_STM32H5_STM32H52XXX) || defined(CONFIG_STM32H5_STM32H53XXX) +#if defined(CONFIG_STM32_STM32H52XXX) || defined(CONFIG_STM32_STM32H53XXX) # define STM32_IRQ_I3C2_EV (STM32_IRQ_FIRST + 131) /* 131: I3C2_EV global interrupt */ # define STM32_IRQ_I3C2_ER (STM32_IRQ_FIRST + 132) /* 132: I3C2_ER global interrupt */ #endif -#if defined(CONFIG_STM32H5_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX) +#if defined(CONFIG_STM32_STM32H56XXX) || defined(CONFIG_STM32_STM32H57XXX) # define STM32_IRQ_NEXTINTS 131 -#elif defined(CONFIG_STM32H5_STM32H52XXX) || defined(CONFIG_STM32H5_STM32H53XXX) +#elif defined(CONFIG_STM32_STM32H52XXX) || defined(CONFIG_STM32_STM32H53XXX) # define STM32_IRQ_NEXTINTS 133 #endif diff --git a/arch/arm/include/stm32h7/chip.h b/arch/arm/include/stm32h7/chip.h index b97a8659e6c32..841d6a506a878 100644 --- a/arch/arm/include/stm32h7/chip.h +++ b/arch/arm/include/stm32h7/chip.h @@ -51,8 +51,8 @@ * * Parts STM32H7xxxI have 2048Kb of FLASH * - * The correct FLASH size will be set CONFIG_STM32H7_FLASH_CONFIG_x or - * overridden with CONFIG_STM32H7_FLASH_OVERRIDE_x + * The correct FLASH size will be set CONFIG_STM32_FLASH_CONFIG_x or + * overridden with CONFIG_STM32_FLASH_OVERRIDE_x */ #if defined (CONFIG_ARCH_CHIP_STM32H723VG) || \ @@ -91,158 +91,158 @@ /* Size SRAM */ -#if defined(CONFIG_STM32H7_STM32H7X0XX) || defined(CONFIG_STM32H7_STM32H7X3XX) || defined(CONFIG_STM32H7_STM32H7X5XX) +#if defined(CONFIG_STM32_STM32H7X0XX) || defined(CONFIG_STM32_STM32H7X3XX) || defined(CONFIG_STM32_STM32H7X5XX) /* Memory */ -# ifdef CONFIG_STM32H7_STM32H72XXX_OR_STM32H73XXX -# define STM32H7_SRAM_SIZE (320*1024) /* 320Kb SRAM on AXI bus Matrix (D1) */ -# define STM32H7_SRAM1_SIZE (16*1024) /* 16Kb SRAM1 on AHB bus Matrix (D2) */ -# define STM32H7_SRAM2_SIZE (16*1024) /* 16Kb SRAM2 on AHB bus Matrix (D2) */ -# define STM32H7_SRAM3_SIZE (0*1024) /* No SRAM3 on AHB bus Matrix (D2) */ -# define STM32H7_SRAM123_SIZE (32*1024) /* 32Kb SRAM123 on AHB bus Matrix (D2) */ -# define STM32H7_SRAM4_SIZE (16*1024) /* 16Kb SRAM4 on AHB bus Matrix (D3) */ +# ifdef CONFIG_STM32_STM32H72XXX_OR_STM32H73XXX +# define STM32_SRAM_SIZE (320*1024) /* 320Kb SRAM on AXI bus Matrix (D1) */ +# define STM32_SRAM1_SIZE (16*1024) /* 16Kb SRAM1 on AHB bus Matrix (D2) */ +# define STM32_SRAM2_SIZE (16*1024) /* 16Kb SRAM2 on AHB bus Matrix (D2) */ +# define STM32_SRAM3_SIZE (0*1024) /* No SRAM3 on AHB bus Matrix (D2) */ +# define STM32_SRAM123_SIZE (32*1024) /* 32Kb SRAM123 on AHB bus Matrix (D2) */ +# define STM32_SRAM4_SIZE (16*1024) /* 16Kb SRAM4 on AHB bus Matrix (D3) */ # else /* STM32H74XXX or STM32H75XXX with full SRAM configuration */ -# define STM32H7_SRAM_SIZE (512*1024) /* 512Kb SRAM on AXI bus Matrix (D1) */ -# define STM32H7_SRAM1_SIZE (128*1024) /* 128Kb SRAM1 on AHB bus Matrix (D2) */ -# define STM32H7_SRAM2_SIZE (128*1024) /* 128Kb SRAM2 on AHB bus Matrix (D2) */ -# define STM32H7_SRAM3_SIZE (32*1024) /* 32Kb SRAM3 on AHB bus Matrix (D2) */ -# define STM32H7_SRAM123_SIZE (288*1024) /* 128Kb SRAM123 on AHB bus Matrix (D2) */ -# define STM32H7_SRAM4_SIZE (64*1024) /* 64Kb SRAM2 on AHB bus Matrix (D3) */ +# define STM32_SRAM_SIZE (512*1024) /* 512Kb SRAM on AXI bus Matrix (D1) */ +# define STM32_SRAM1_SIZE (128*1024) /* 128Kb SRAM1 on AHB bus Matrix (D2) */ +# define STM32_SRAM2_SIZE (128*1024) /* 128Kb SRAM2 on AHB bus Matrix (D2) */ +# define STM32_SRAM3_SIZE (32*1024) /* 32Kb SRAM3 on AHB bus Matrix (D2) */ +# define STM32_SRAM123_SIZE (288*1024) /* 128Kb SRAM123 on AHB bus Matrix (D2) */ +# define STM32_SRAM4_SIZE (64*1024) /* 64Kb SRAM2 on AHB bus Matrix (D3) */ # endif /* STM32H72XXX or STM32H73XXX / STM32H74XXX or STM32H75XXX */ # if defined(CONFIG_ARMV7M_HAVE_DTCM) -# define STM32H7_DTCM_SRAM_SIZE (128*1024) /* 128Kb DTCM SRAM on TCM interface */ +# define STM32_DTCM_SRAM_SIZE (128*1024) /* 128Kb DTCM SRAM on TCM interface */ # else -# define STM32H7_DTCM_SRAM_SIZE (0) /* No DTCM SRAM on TCM interface */ +# define STM32_DTCM_SRAM_SIZE (0) /* No DTCM SRAM on TCM interface */ # endif # if defined(CONFIG_ARMV7M_HAVE_ITCM) -# define STM32H7_ITCM_SRAM_SIZE (64*1024) /* 64b ITCM SRAM on TCM interface */ +# define STM32_ITCM_SRAM_SIZE (64*1024) /* 64b ITCM SRAM on TCM interface */ # else -# define STM32H7_ITCM_SRAM_SIZE (0) /* No ITCM SRAM on TCM interface */ +# define STM32_ITCM_SRAM_SIZE (0) /* No ITCM SRAM on TCM interface */ # endif /* Peripherals */ # if defined(CONFIG_STM32H7_IO_CONFIG_A) -# define STM32H7_NGPIO (10) /* GPIOA-GPIOJ */ +# define STM32_NGPIO (10) /* GPIOA-GPIOJ */ # elif defined(CONFIG_STM32H7_IO_CONFIG_B) -# define STM32H7_NGPIO (11) /* GPIOA-GPIOK */ +# define STM32_NGPIO (11) /* GPIOA-GPIOK */ # elif defined(CONFIG_STM32H7_IO_CONFIG_I) -# define STM32H7_NGPIO (9) /* GPIOA-GPIOI */ +# define STM32_NGPIO (9) /* GPIOA-GPIOI */ # elif defined(CONFIG_STM32H7_IO_CONFIG_V) -# define STM32H7_NGPIO (8) /* GPIOA-GPIOH, missing GPIOF-GPIOG */ +# define STM32_NGPIO (8) /* GPIOA-GPIOH, missing GPIOF-GPIOG */ # elif defined(CONFIG_STM32H7_IO_CONFIG_X) -# define STM32H7_NGPIO (11) /* GPIOA-GPIOK */ +# define STM32_NGPIO (11) /* GPIOA-GPIOK */ # elif defined(CONFIG_STM32H7_IO_CONFIG_Z) -# define STM32H7_NGPIO (8) /* GPIOA-GPIOH */ +# define STM32_NGPIO (8) /* GPIOA-GPIOH */ # else # error CONFIG_STM32H7_IO_CONFIG_x Not Set # endif -# define STM32H7_NDMA (4) /* (4) DMA1, DMA2, BDMA and MDMA */ -# define STM32H7_NADC (3) /* (3) ADC1-3*/ -# define STM32H7_NDAC (2) /* (2) DAC1-2*/ -# define STM32H7_NCMP (2) /* (2) ultra-low power comparators */ -# define STM32H7_NPGA (2) /* (2) Operational amplifiers: OPAMP */ -# define STM32H7_NDFSDM (1) /* (1) digital filters for sigma delta modulator */ -# define STM32H7_NUSART (4) /* (4) USART1-3, 6 */ -# define STM32H7_NSPI (6) /* (6) SPI1-6 */ -# define STM32H7_NI2S (3) /* (3) I2S1-3 */ -# define STM32H7_NUART (4) /* (4) UART4-5, 7-8 */ -# define STM32H7_NI2C (4) /* (4) I2C1-4 */ -# define STM32H7_NSAI (4) /* (4) SAI1-4*/ -# define STM32H7_NCAN (2) /* (2) CAN1-2 */ -# define STM32H7_NSDIO (2) /* (2) SDIO */ -#elif defined(CONFIG_STM32H7_STM32H7B3XX) +# define STM32_NDMA (4) /* (4) DMA1, DMA2, BDMA and MDMA */ +# define STM32_NADC (3) /* (3) ADC1-3*/ +# define STM32_NDAC (2) /* (2) DAC1-2*/ +# define STM32_NCMP (2) /* (2) ultra-low power comparators */ +# define STM32_NPGA (2) /* (2) Operational amplifiers: OPAMP */ +# define STM32_NDFSDM (1) /* (1) digital filters for sigma delta modulator */ +# define STM32_NUSART (4) /* (4) USART1-3, 6 */ +# define STM32_NSPI (6) /* (6) SPI1-6 */ +# define STM32_NI2S (3) /* (3) I2S1-3 */ +# define STM32_NUART (4) /* (4) UART4-5, 7-8 */ +# define STM32_NI2C (4) /* (4) I2C1-4 */ +# define STM32_NSAI (4) /* (4) SAI1-4*/ +# define STM32_NCAN (2) /* (2) CAN1-2 */ +# define STM32_NSDIO (2) /* (2) SDIO */ +#elif defined(CONFIG_STM32_STM32H7B3XX) /* Memory */ -# define STM32H7_SRAM_SIZE (1024*1024) /* 1024Kb SRAM on AXI bus Matrix (D1) */ -# define STM32H7_SRAM1_SIZE (64*1024) /* 64Kb SRAM1 on AHB bus Matrix (D2) */ -# define STM32H7_SRAM2_SIZE (64*1024) /* 64Kb SRAM2 on AHB bus Matrix (D2) */ -# define STM32H7_SRAM3_SIZE (0*1024) /* No SRAM3 on AHB bus Matrix (D2) */ -# define STM32H7_SRAM123_SIZE (128*1024) /* 128Kb SRAM123 on AHB bus Matrix (D2) */ -# define STM32H7_SRAM4_SIZE (32*1024) /* 32Kb SRAM2 on AHB bus Matrix (D3) */ +# define STM32_SRAM_SIZE (1024*1024) /* 1024Kb SRAM on AXI bus Matrix (D1) */ +# define STM32_SRAM1_SIZE (64*1024) /* 64Kb SRAM1 on AHB bus Matrix (D2) */ +# define STM32_SRAM2_SIZE (64*1024) /* 64Kb SRAM2 on AHB bus Matrix (D2) */ +# define STM32_SRAM3_SIZE (0*1024) /* No SRAM3 on AHB bus Matrix (D2) */ +# define STM32_SRAM123_SIZE (128*1024) /* 128Kb SRAM123 on AHB bus Matrix (D2) */ +# define STM32_SRAM4_SIZE (32*1024) /* 32Kb SRAM2 on AHB bus Matrix (D3) */ # if defined(CONFIG_ARMV7M_HAVE_DTCM) -# define STM32H7_DTCM_SRAM_SIZE (128*1024) /* 128Kb DTCM SRAM on TCM interface */ +# define STM32_DTCM_SRAM_SIZE (128*1024) /* 128Kb DTCM SRAM on TCM interface */ # else -# define STM32H7_DTCM_SRAM_SIZE (0) /* No DTCM SRAM on TCM interface */ +# define STM32_DTCM_SRAM_SIZE (0) /* No DTCM SRAM on TCM interface */ # endif # if defined(CONFIG_ARMV7M_HAVE_ITCM) -# define STM32H7_ITCM_SRAM_SIZE (64*1024) /* 64b ITCM SRAM on TCM interface */ +# define STM32_ITCM_SRAM_SIZE (64*1024) /* 64b ITCM SRAM on TCM interface */ # else -# define STM32H7_ITCM_SRAM_SIZE (0) /* No ITCM SRAM on TCM interface */ +# define STM32_ITCM_SRAM_SIZE (0) /* No ITCM SRAM on TCM interface */ # endif /* Peripherals */ # if defined(CONFIG_STM32H7_IO_CONFIG_A) -# define STM32H7_NGPIO (10) /* GPIOA-GPIOJ */ +# define STM32_NGPIO (10) /* GPIOA-GPIOJ */ # elif defined(CONFIG_STM32H7_IO_CONFIG_B) -# define STM32H7_NGPIO (11) /* GPIOA-GPIOK */ +# define STM32_NGPIO (11) /* GPIOA-GPIOK */ # elif defined(CONFIG_STM32H7_IO_CONFIG_I) -# define STM32H7_NGPIO (9) /* GPIOA-GPIOI */ +# define STM32_NGPIO (9) /* GPIOA-GPIOI */ # elif defined(CONFIG_STM32H7_IO_CONFIG_L) -# define STM32H7_NGPIO (11) /* GPIOA-GPIOK */ +# define STM32_NGPIO (11) /* GPIOA-GPIOK */ # elif defined(CONFIG_STM32H7_IO_CONFIG_V) -# define STM32H7_NGPIO (8) /* GPIOA-GPIOH, missing GPIOF-GPIOG */ +# define STM32_NGPIO (8) /* GPIOA-GPIOH, missing GPIOF-GPIOG */ # elif defined(CONFIG_STM32H7_IO_CONFIG_X) -# define STM32H7_NGPIO (11) /* GPIOA-GPIOK */ +# define STM32_NGPIO (11) /* GPIOA-GPIOK */ # elif defined(CONFIG_STM32H7_IO_CONFIG_Z) -# define STM32H7_NGPIO (8) /* GPIOA-GPIOH */ +# define STM32_NGPIO (8) /* GPIOA-GPIOH */ # else # error CONFIG_STM32H7_IO_CONFIG_x Not Set # endif -# define STM32H7_NDMA (4) /* (4) DMA1, DMA2, BDMA and MDMA */ -# define STM32H7_NADC (3) /* (3) ADC1-3*/ -# define STM32H7_NDAC (2) /* (2) DAC1-2*/ -# define STM32H7_NCMP (2) /* (2) ultra-low power comparators */ -# define STM32H7_NPGA (2) /* (2) Operational amplifiers: OPAMP */ -# define STM32H7_NDFSDM (1) /* (1) digital filters for sigma delta modulator */ -# define STM32H7_NUSART (4) /* (4) USART1-3, 6 */ -# define STM32H7_NSPI (6) /* (6) SPI1-6 */ -# define STM32H7_NI2S (3) /* (3) I2S1-3 */ -# define STM32H7_NUART (4) /* (4) UART4-5, 7-8 */ -# define STM32H7_NI2C (4) /* (4) I2C1-4 */ -# define STM32H7_NSAI (4) /* (4) SAI1-4*/ -# define STM32H7_NCAN (2) /* (2) CAN1-2 */ -# define STM32H7_NSDIO (2) /* (2) SDIO */ -#elif defined(CONFIG_STM32H7_STM32H7X7XX) +# define STM32_NDMA (4) /* (4) DMA1, DMA2, BDMA and MDMA */ +# define STM32_NADC (3) /* (3) ADC1-3*/ +# define STM32_NDAC (2) /* (2) DAC1-2*/ +# define STM32_NCMP (2) /* (2) ultra-low power comparators */ +# define STM32_NPGA (2) /* (2) Operational amplifiers: OPAMP */ +# define STM32_NDFSDM (1) /* (1) digital filters for sigma delta modulator */ +# define STM32_NUSART (4) /* (4) USART1-3, 6 */ +# define STM32_NSPI (6) /* (6) SPI1-6 */ +# define STM32_NI2S (3) /* (3) I2S1-3 */ +# define STM32_NUART (4) /* (4) UART4-5, 7-8 */ +# define STM32_NI2C (4) /* (4) I2C1-4 */ +# define STM32_NSAI (4) /* (4) SAI1-4*/ +# define STM32_NCAN (2) /* (2) CAN1-2 */ +# define STM32_NSDIO (2) /* (2) SDIO */ +#elif defined(CONFIG_STM32_STM32H7X7XX) /* Memory */ -# define STM32H7_SRAM_SIZE (512*1024) /* 512Kb SRAM on AXI bus Matrix (D1) */ -# define STM32H7_SRAM1_SIZE (128*1024) /* 128Kb SRAM1 on AHB bus Matrix (D2) */ -# define STM32H7_SRAM2_SIZE (128*1024) /* 128Kb SRAM2 on AHB bus Matrix (D2) */ -# define STM32H7_SRAM3_SIZE (32*1024) /* 32Kb SRAM3 on AHB bus Matrix (D2) */ -# define STM32H7_SRAM123_SIZE (288*1024) /* 128Kb SRAM123 on AHB bus Matrix (D2) */ -# define STM32H7_SRAM4_SIZE (64*1024) /* 64Kb SRAM2 on AHB bus Matrix (D3) */ +# define STM32_SRAM_SIZE (512*1024) /* 512Kb SRAM on AXI bus Matrix (D1) */ +# define STM32_SRAM1_SIZE (128*1024) /* 128Kb SRAM1 on AHB bus Matrix (D2) */ +# define STM32_SRAM2_SIZE (128*1024) /* 128Kb SRAM2 on AHB bus Matrix (D2) */ +# define STM32_SRAM3_SIZE (32*1024) /* 32Kb SRAM3 on AHB bus Matrix (D2) */ +# define STM32_SRAM123_SIZE (288*1024) /* 128Kb SRAM123 on AHB bus Matrix (D2) */ +# define STM32_SRAM4_SIZE (64*1024) /* 64Kb SRAM2 on AHB bus Matrix (D3) */ # if defined(CONFIG_ARMV7M_HAVE_DTCM) -# define STM32H7_DTCM_SRAM_SIZE (128*1024) /* 128Kb DTCM SRAM on TCM interface */ +# define STM32_DTCM_SRAM_SIZE (128*1024) /* 128Kb DTCM SRAM on TCM interface */ # else -# define STM32H7_DTCM_SRAM_SIZE (0) /* No DTCM SRAM on TCM interface */ +# define STM32_DTCM_SRAM_SIZE (0) /* No DTCM SRAM on TCM interface */ # endif # if defined(CONFIG_ARMV7M_HAVE_ITCM) -# define STM32H7_ITCM_SRAM_SIZE (64*1024) /* 64b ITCM SRAM on TCM interface */ +# define STM32_ITCM_SRAM_SIZE (64*1024) /* 64b ITCM SRAM on TCM interface */ # else -# define STM32H7_ITCM_SRAM_SIZE (0) /* No ITCM SRAM on TCM interface */ +# define STM32_ITCM_SRAM_SIZE (0) /* No ITCM SRAM on TCM interface */ # endif /* Peripherals */ -# define STM32H7_NGPIO (11) /* GPIOA-GPIOK */ -# define STM32H7_NDMA (4) /* (4) DMA1, DMA2, BDMA and MDMA */ -# define STM32H7_NADC (3) /* (3) ADC1-3*/ -# define STM32H7_NDAC (2) /* (2) DAC1-2*/ -# define STM32H7_NCMP (2) /* (2) ultra-low power comparators */ -# define STM32H7_NPGA (2) /* (2) Operational amplifiers: OPAMP */ -# define STM32H7_NDFSDM (1) /* (1) digital filters for sigma delta modulator */ -# define STM32H7_NUSART (4) /* (4) USART1-3, 6 */ -# define STM32H7_NSPI (6) /* (6) SPI1-6 */ -# define STM32H7_NI2S (3) /* (3) I2S1-3 */ -# define STM32H7_NUART (4) /* (4) UART4-5, 7-8 */ -# define STM32H7_NI2C (4) /* (4) I2C1-4 */ -# define STM32H7_NSAI (4) /* (4) SAI1-4*/ -# define STM32H7_NCAN (2) /* (2) CAN1-2 */ -# define STM32H7_NSDIO (2) /* (2) SDIO */ +# define STM32_NGPIO (11) /* GPIOA-GPIOK */ +# define STM32_NDMA (4) /* (4) DMA1, DMA2, BDMA and MDMA */ +# define STM32_NADC (3) /* (3) ADC1-3*/ +# define STM32_NDAC (2) /* (2) DAC1-2*/ +# define STM32_NCMP (2) /* (2) ultra-low power comparators */ +# define STM32_NPGA (2) /* (2) Operational amplifiers: OPAMP */ +# define STM32_NDFSDM (1) /* (1) digital filters for sigma delta modulator */ +# define STM32_NUSART (4) /* (4) USART1-3, 6 */ +# define STM32_NSPI (6) /* (6) SPI1-6 */ +# define STM32_NI2S (3) /* (3) I2S1-3 */ +# define STM32_NUART (4) /* (4) UART4-5, 7-8 */ +# define STM32_NI2C (4) /* (4) I2C1-4 */ +# define STM32_NSAI (4) /* (4) SAI1-4*/ +# define STM32_NCAN (2) /* (2) CAN1-2 */ +# define STM32_NSDIO (2) /* (2) SDIO */ #else # error STM32 H7 chip Family not identified #endif @@ -259,16 +259,16 @@ /* Diversification based on Family and package */ -#if defined(CONFIG_STM32H7_HAVE_ETHERNET) -# define STM32H7_NETHERNET 1 /* 100/100 Ethernet MAC */ +#if defined(CONFIG_STM32_HAVE_ETHERNET) +# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */ #else -# define STM32H7_NETHERNET 0 /* No 100/100 Ethernet MAC */ +# define STM32_NETHERNET 0 /* No 100/100 Ethernet MAC */ #endif -#if defined(CONFIG_STM32H7_HAVE_FMC) -# define STM32H7_NFMC 1 /* Have FMC memory controller */ +#if defined(CONFIG_STM32_HAVE_FMC) +# define STM32_NFMC 1 /* Have FMC memory controller */ #else -# define STM32H7_NFMC 0 /* No FMC memory controller */ +# define STM32_NFMC 0 /* No FMC memory controller */ #endif /* NVIC priority levels *****************************************************/ diff --git a/arch/arm/include/stm32h7/irq.h b/arch/arm/include/stm32h7/irq.h index 427d6b8c1f25d..24cfc5f4add09 100644 --- a/arch/arm/include/stm32h7/irq.h +++ b/arch/arm/include/stm32h7/irq.h @@ -69,19 +69,19 @@ * Included Files ****************************************************************************/ -#if defined(CONFIG_STM32H7_STM32H7X0XX) +#if defined(CONFIG_STM32_STM32H7X0XX) # include -#elif defined(CONFIG_STM32H7_STM32H7X3XX) +#elif defined(CONFIG_STM32_STM32H7X3XX) # include -#elif defined(CONFIG_STM32H7_STM32H7B3XX) +#elif defined(CONFIG_STM32_STM32H7B3XX) # include -#elif defined(CONFIG_STM32H7_STM32H7X5XX) +#elif defined(CONFIG_STM32_STM32H7X5XX) # if CONFIG_ARCH_CHIP_STM32H7_CORTEXM7 # include # else # include # endif -#elif defined(CONFIG_STM32H7_STM32H7X7XX) +#elif defined(CONFIG_STM32_STM32H7X7XX) # include #else # error "Unsupported STM32 H7 chip" diff --git a/arch/arm/include/stm32l0/chip.h b/arch/arm/include/stm32l0/chip.h new file mode 100644 index 0000000000000..dcd8199454643 --- /dev/null +++ b/arch/arm/include/stm32l0/chip.h @@ -0,0 +1,371 @@ +/**************************************************************************** + * arch/arm/include/stm32l0/chip.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_INCLUDE_STM32L0_CHIP_H +#define __ARCH_ARM_INCLUDE_STM32L0_CHIP_H + +#define ARMV6M_PERIPHERAL_INTERRUPTS 32 + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Prototypes + ****************************************************************************/ + +/* Get customizations for each supported chip */ + +#if defined(CONFIG_ARCH_CHIP_STM32L071K8) +# define STM32_NATIM 0 /* No advanced timers */ +# define STM32_NGTIM16 4 /* 16-bit general up/down timers TIM2-3 + * (with DMA) and TIM21-22 without DMA */ +# define STM32_NGTIM32 0 /* No 32-bit general up/down timers */ +# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 with DMA */ + /* 1 LPTIMER */ +# define STM32_NSPI 1 /* 1 SPI modules SPI1 */ +# define STM32_NI2S 0 /* 0 I2S module */ +# define STM32_NI2C 2 /* 2 I2C */ +# define STM32_NDMA 1 /* 1 DMA1, 7-channels */ +# define STM32_NUSART 3 /* 3 USART modules, USART1-3 */ + /* 1 LPUART */ +# define STM32_NCAN 0 /* 0 CAN controllers */ +# define STM32_NLCD 0 /* 0 LCD */ +# define STM32_NUSBDEV 0 /* 0 USB full-speed device controller */ +# define STM32_NUSBOTG 0 /* 0 USB OTG FS/HS (only USB 2.0 device) */ +# define STM32_NCEC 0 /* 0 HDMI-CEC controller */ +# define STM32_NADC 1 /* One 12-bit module */ +# define STM32_NDAC 0 /* 0 DAC channel */ +# define STM32_NCOMP 2 /* 2 Analog Comparators */ +# define STM32_NCRC 0 /* 0 CRC module */ +# define STM32_NRNG 0 /* 0 Random number generator (RNG) */ +# define STM32_NCAP 0 /* 0 Capacitive sensing channels */ +# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-E, H */ + +#elif defined(CONFIG_ARCH_CHIP_STM32L053C8) +# define STM32_NATIM 0 /* No advanced timers */ +# define STM32_NGTIM16 3 /* 16-bit general up/down timers TIM2-3 + * (with DMA) and TIM22 without DMA */ +# define STM32_NGTIM32 0 /* No 32-bit general up/down timers */ +# define STM32_NBTIM 1 /* 1 basic timers: TIM6 with DMA */ + /* 1 LPTIMER */ +# define STM32_NSPI 2 /* 2 SPI modules SPI1 */ +# define STM32_NI2S 1 /* 1 I2S module */ +# define STM32_NI2C 2 /* 2 I2C */ +# define STM32_NDMA 1 /* 1 DMA1, 7-channels */ +# define STM32_NUSART 2 /* 2 USART modules, USART1-1 */ + /* 1 LPUART */ +# define STM32_NCAN 0 /* 0 CAN controllers */ +# define STM32_NLCD 1 /* 1 LCD */ +# define STM32_NUSBDEV 1 /* 1 USB full-speed device controller */ +# define STM32_NUSBOTG 0 /* 0 USB OTG FS/HS (only USB 2.0 device) */ +# define STM32_NCEC 0 /* 0 HDMI-CEC controller */ +# define STM32_NADC 1 /* One 12-bit module */ +# define STM32_NDAC 0 /* 0 DAC channel */ +# define STM32_NCOMP 2 /* 2 Analog Comparators */ +# define STM32_NCRC 0 /* 0 CRC module */ +# define STM32_NRNG 0 /* 0 Random number generator (RNG) */ +# define STM32_NCAP 24 /* 24 Capacitive sensing channels */ +# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-E, H */ + +#elif defined(CONFIG_ARCH_CHIP_STM32L053R8) +# define STM32_NATIM 0 /* No advanced timers */ +# define STM32_NGTIM16 3 /* 16-bit general up/down timers TIM2-3 + * (with DMA) and TIM22 without DMA */ +# define STM32_NGTIM32 0 /* No 32-bit general up/down timers */ +# define STM32_NBTIM 1 /* 1 basic timers: TIM6 with DMA */ + /* 1 LPTIMER */ +# define STM32_NSPI 2 /* 2 SPI modules SPI1 */ +# define STM32_NI2S 1 /* 1 I2S module */ +# define STM32_NI2C 2 /* 2 I2C */ +# define STM32_NDMA 1 /* 1 DMA1, 7-channels */ +# define STM32_NUSART 2 /* 2 USART modules, USART1-1 */ + /* 1 LPUART */ +# define STM32_NCAN 0 /* 0 CAN controllers */ +# define STM32_NLCD 1 /* 1 LCD */ +# define STM32_NUSBDEV 1 /* 1 USB full-speed device controller */ +# define STM32_NUSBOTG 0 /* 0 USB OTG FS/HS (only USB 2.0 device) */ +# define STM32_NCEC 0 /* 0 HDMI-CEC controller */ +# define STM32_NADC 1 /* One 12-bit module */ +# define STM32_NDAC 0 /* 0 DAC channel */ +# define STM32_NCOMP 2 /* 2 Analog Comparators */ +# define STM32_NCRC 0 /* 0 CRC module */ +# define STM32_NRNG 0 /* 0 Random number generator (RNG) */ +# define STM32_NCAP 24 /* 24 Capacitive sensing channels */ +# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-E, H */ + +#elif defined(CONFIG_ARCH_CHIP_STM32L071C8) || defined(CONFIG_ARCH_CHIP_STM32L071V8) || \ + defined(CONFIG_ARCH_CHIP_STM32L071CB) || defined(CONFIG_ARCH_CHIP_STM32L071VB) || \ + defined(CONFIG_ARCH_CHIP_STM32L071RB) || defined(CONFIG_ARCH_CHIP_STM32L071CZ) || \ + defined(CONFIG_ARCH_CHIP_STM32L071VZ) || defined(CONFIG_ARCH_CHIP_STM32L071RZ) +# define STM32_NATIM 0 /* 0 advanced timers */ +# define STM32_NGTIM16 4 /* 16-bit general up/down timers TIM2-3 + * (with DMA) and TIM21-22 without DMA */ +# define STM32_NGTIM32 0 /* 0 32-bit general up/down timers */ +# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 with DMA */ + /* 1 LPTIMER */ +# define STM32_NSPI 2 /* 2 SPI modules SPI1-2 */ +# define STM32_NI2S 1 /* 1 I2S module */ +# define STM32_NI2C 3 /* 3 I2C */ +# define STM32_NDMA 1 /* 1 DMA1, 7-channels */ +# define STM32_NUSART 4 /* 4 USART modules, USART1-4 */ + /* 1 LPUART */ +# define STM32_NCAN 0 /* 0 CAN controllers */ +# define STM32_NLCD 0 /* 0 LCD */ +# define STM32_NUSBDEV 0 /* 0 USB full-speed device controller */ +# define STM32_NUSBOTG 0 /* 0 USB OTG FS/HS (only USB 2.0 device) */ +# define STM32_NCEC 0 /* 0 HDMI-CEC controller */ +# define STM32_NADC 1 /* One 12-bit module */ +# define STM32_NDAC 0 /* 0 DAC channel */ +# define STM32_NCOMP 2 /* 2 Analog Comparators */ +# define STM32_NCRC 0 /* 0 CRC module */ +# define STM32_NRNG 0 /* 0 Random number generator (RNG) */ +# define STM32_NCAP 0 /* 0 Capacitive sensing channels */ +# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-E, H */ + +#elif defined(CONFIG_ARCH_CHIP_STM32L071KB) || defined(CONFIG_ARCH_CHIP_STM32L071KZ) +# define STM32_NATIM 0 /* 0 advanced timers */ +# define STM32_NGTIM16 4 /* 16-bit general up/down timers TIM2-3 + * (with DMA) and TIM21-22 without DMA */ +# define STM32_NGTIM32 0 /* 0 32-bit general up/down timers */ +# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 with DMA */ + /* 1 LPTIMER */ +# define STM32_NSPI 1 /* 1 SPI modules SPI1 */ +# define STM32_NI2S 0 /* 0 I2S module */ +# define STM32_NI2C 3 /* 3 I2C */ +# define STM32_NDMA 1 /* 1 DMA1, 7-channels */ +# define STM32_NUSART 4 /* 4 USART modules, USART1-4 */ + /* 1 LPUART */ +# define STM32_NCAN 0 /* 0 CAN controllers */ +# define STM32_NLCD 0 /* 0 LCD */ +# define STM32_NUSBDEV 0 /* 0 USB full-speed device controller */ +# define STM32_NUSBOTG 0 /* 0 USB OTG FS/HS (only USB 2.0 device) */ +# define STM32_NCEC 0 /* 0 HDMI-CEC controller */ +# define STM32_NADC 1 /* One 12-bit module */ +# define STM32_NDAC 0 /* 0 DAC channel */ +# define STM32_NCOMP 2 /* 2 Analog Comparators */ +# define STM32_NCRC 0 /* 0 CRC module */ +# define STM32_NRNG 0 /* 0 Random number generator (RNG) */ +# define STM32_NCAP 0 /* 0 Capacitive sensing channels */ +# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-E, H */ + +#elif defined(CONFIG_ARCH_CHIP_STM32L072V8) || defined(CONFIG_ARCH_CHIP_STM32L072VB) || \ + defined(CONFIG_ARCH_CHIP_STM32L072VZ) +# define STM32_NATIM 0 /* No advanced timers */ +# define STM32_NGTIM16 4 /* 16-bit general up/down timers TIM2-3 + * (with DMA) and TIM21-22 without DMA */ +# define STM32_NGTIM32 0 /* No 32-bit general up/down timers */ +# define STM32_NBTIM 2 /* Two basic timers: TIM6, TIM7 with DMA */ + /* One LPTIMER */ +# define STM32_NSPI 2 /* Two SPI modules SPI1-2 */ +# define STM32_NI2S 1 /* One I2S module */ +# define STM32_NI2C 3 /* Three I2C (2 with SMBus/PMBus) */ +# define STM32_NDMA 1 /* One DMA1, 7-channels */ +# define STM32_NUSART 4 /* Four USART modules, USART1-4 */ + /* One LPUART */ +# define STM32_NCAN 0 /* No CAN controllers */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBDEV 0 /* No USB full-speed device controller */ +# define STM32_NUSBOTG 1 /* One USB OTG FS/HS (only USB 2.0 device) */ +# define STM32_NCEC 0 /* No HDMI-CEC controller */ +# define STM32_NADC 1 /* One 12-bit module */ +# define STM32_NDAC 2 /* Two DAC channels */ +# define STM32_NCOMP 2 /* Two Analog Comparators */ +# define STM32_NCRC 1 /* One CRC module */ +# define STM32_NRNG 1 /* One Random number generator (RNG) */ +# define STM32_NCAP 24 /* Twenty-four Capacitive sensing channels */ +# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-E, H */ + +#elif defined(CONFIG_ARCH_CHIP_STM32L072KB) || defined(CONFIG_ARCH_CHIP_STM32L072KZ) +# define STM32_NATIM 0 /* No advanced timers */ +# define STM32_NGTIM16 4 /* 16-bit general up/down timers TIM2-3 + * (with DMA) and TIM21-22 without DMA */ +# define STM32_NGTIM32 0 /* No 32-bit general up/down timers */ +# define STM32_NBTIM 2 /* Two basic timers: TIM6, TIM7 with DMA */ + /* One LPTIMER */ +# define STM32_NSPI 2 /* Two SPI modules SPI1-2 */ +# define STM32_NI2C 3 /* Three I2C (2 with SMBus/PMBus) */ +# define STM32_NDMA 1 /* One DMA1, 7-channels */ +# define STM32_NUSART 4 /* Four USART modules, USART1-4 */ + /* One LPUART */ +# define STM32_NCAN 0 /* No CAN controllers */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBDEV 0 /* No USB full-speed device controller */ +# define STM32_NUSBOTG 1 /* One USB OTG FS/HS (only USB 2.0 device) */ +# define STM32_NCEC 0 /* No HDMI-CEC controller */ +# define STM32_NADC 1 /* One 12-bit module */ +# define STM32_NDAC 2 /* Two DAC channels */ +# define STM32_NCOMP 2 /* Two Analog Comparators */ +# define STM32_NCRC 1 /* One CRC module */ +# define STM32_NRNG 1 /* One Random number generator (RNG) */ +# define STM32_NCAP 13 /* Thirteen Capacitive sensing channels */ +# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-E, H */ + +#elif defined(CONFIG_ARCH_CHIP_STM32L072CB) || defined(CONFIG_ARCH_CHIP_STM32L072CZ) +# define STM32_NATIM 0 /* No advanced timers */ +# define STM32_NGTIM16 4 /* 16-bit general up/down timers TIM2-3 + * (with DMA) and TIM21-22 without DMA */ +# define STM32_NGTIM32 0 /* No 32-bit general up/down timers */ +# define STM32_NBTIM 2 /* Two basic timers: TIM6, TIM7 with DMA */ + /* One LPTIMER */ +# define STM32_NSPI 2 /* Two SPI modules SPI1-2 */ +# define STM32_NI2S 1 /* One I2S module */ +# define STM32_NI2C 3 /* Three I2C (2 with SMBus/PMBus) */ +# define STM32_NDMA 1 /* One DMA1, 7-channels */ +# define STM32_NUSART 4 /* Four USART modules, USART1-4 */ + /* One LPUART */ +# define STM32_NCAN 0 /* No CAN controllers */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBDEV 0 /* No USB full-speed device controller */ +# define STM32_NUSBOTG 1 /* One USB OTG FS/HS (only USB 2.0 device) */ +# define STM32_NCEC 0 /* No HDMI-CEC controller */ +# define STM32_NADC 1 /* One 12-bit module */ +# define STM32_NDAC 2 /* Two DAC channels */ +# define STM32_NCOMP 2 /* Two Analog Comparators */ +# define STM32_NCRC 1 /* One CRC module */ +# define STM32_NRNG 1 /* One Random number generator (RNG) */ +# define STM32_NCAP 18 /* Nineteen Capacitive sensing channels */ +# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-E, H */ + +#elif defined(CONFIG_ARCH_CHIP_STM32L072RB) || defined(CONFIG_ARCH_CHIP_STM32L072RZ) +# define STM32_NATIM 0 /* No advanced timers */ +# define STM32_NGTIM16 4 /* 16-bit general up/down timers TIM2-3 + * (with DMA) and TIM21-22 without DMA */ +# define STM32_NGTIM32 0 /* No 32-bit general up/down timers */ +# define STM32_NBTIM 2 /* Two basic timers: TIM6, TIM7 with DMA */ + /* One LPTIMER */ +# define STM32_NSPI 2 /* Two SPI modules SPI1-2 */ +# define STM32_NI2S 1 /* One I2S module */ +# define STM32_NI2C 3 /* Three I2C (2 with SMBus/PMBus) */ +# define STM32_NDMA 1 /* One DMA1, 7-channels */ +# define STM32_NUSART 4 /* Four USART modules, USART1-4 */ + /* One LPUART */ +# define STM32_NCAN 0 /* No CAN controllers */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBDEV 0 /* No USB full-speed device controller */ +# define STM32_NUSBOTG 1 /* One USB OTG FS/HS (only USB 2.0 device) */ +# define STM32_NCEC 0 /* No HDMI-CEC controller */ +# define STM32_NADC 1 /* One 12-bit module */ +# define STM32_NDAC 2 /* Two DAC channels */ +# define STM32_NCOMP 2 /* Two Analog Comparators */ +# define STM32_NCRC 1 /* One CRC module */ +# define STM32_NRNG 1 /* One Random number generator (RNG) */ +# define STM32_NCAP 24 /* Twenty-four Capacitive sensing channels */ +# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-E, H */ + +#elif defined(CONFIG_ARCH_CHIP_STM32L073V8) || defined(CONFIG_ARCH_CHIP_STM32L073VB) || \ + defined(CONFIG_ARCH_CHIP_STM32L073VZ) +# define STM32_NATIM 0 /* No advanced timers */ +# define STM32_NGTIM16 4 /* 16-bit general up/down timers TIM2-3 + * (with DMA) and TIM21-22 without DMA */ +# define STM32_NGTIM32 0 /* No 32-bit general up/down timers */ +# define STM32_NBTIM 2 /* Two basic timers: TIM6, TIM7 with DMA */ + /* One LPTIMER */ +# define STM32_NSPI 2 /* Two SPI modules SPI1-2 */ +# define STM32_NI2S 1 /* One I2S module */ +# define STM32_NI2C 3 /* Three I2C (2 with SMBus/PMBus) */ +# define STM32_NDMA 1 /* One DMA1, 7-channels */ +# define STM32_NUSART 4 /* Four USART modules, USART1-4 */ + /* One LPUART */ +# define STM32_NCAN 0 /* No CAN controllers */ +# define STM32_NLCD 1 /* One LCD controller */ +# define STM32_NUSBDEV 0 /* No USB full-speed device controller */ +# define STM32_NUSBOTG 1 /* One USB OTG FS/HS (only USB 2.0 device) */ +# define STM32_NCEC 0 /* No HDMI-CEC controller */ +# define STM32_NADC 1 /* One 12-bit module */ +# define STM32_NDAC 2 /* Two DAC channels */ +# define STM32_NCOMP 2 /* Two Analog Comparators */ +# define STM32_NCRC 1 /* One CRC module */ +# define STM32_NRNG 1 /* One Random number generator (RNG) */ +# define STM32_NCAP 24 /* Twenty-four Capacitive sensing channels */ +# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-E, H */ + +#elif defined(CONFIG_ARCH_CHIP_STM32L073CB) || defined(CONFIG_ARCH_CHIP_STM32L073CZ) +# define STM32_NATIM 0 /* No advanced timers */ +# define STM32_NGTIM16 4 /* 16-bit general up/down timers TIM2-3 + * (with DMA) and TIM21-22 without DMA */ +# define STM32_NGTIM32 0 /* No 32-bit general up/down timers */ +# define STM32_NBTIM 2 /* Two basic timers: TIM6, TIM7 with DMA */ + /* One LPTIMER */ +# define STM32_NSPI 2 /* Two SPI modules SPI1-2 */ +# define STM32_NI2S 1 /* One I2S module */ +# define STM32_NI2C 3 /* Three I2C (2 with SMBus/PMBus) */ +# define STM32_NDMA 1 /* One DMA1, 7-channels */ +# define STM32_NUSART 4 /* Four USART modules, USART1-4 */ + /* One LPUART */ +# define STM32_NCAN 0 /* No CAN controllers */ +# define STM32_NLCD 1 /* One LCD controller */ +# define STM32_NUSBDEV 0 /* No USB full-speed device controller */ +# define STM32_NUSBOTG 1 /* One USB OTG FS/HS (only USB 2.0 device) */ +# define STM32_NCEC 0 /* No HDMI-CEC controller */ +# define STM32_NADC 1 /* One 12-bit module */ +# define STM32_NDAC 2 /* Two DAC channels */ +# define STM32_NCOMP 2 /* Two Analog Comparators */ +# define STM32_NCRC 1 /* One CRC module */ +# define STM32_NRNG 1 /* One Random number generator (RNG) */ +# define STM32_NCAP 17 /* Seventeen Capacitive sensing channels */ +# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-E, H */ + +#elif defined(CONFIG_ARCH_CHIP_STM32L073RB) || defined(CONFIG_ARCH_CHIP_STM32L073RZ) +# define STM32_NATIM 0 /* No advanced timers */ +# define STM32_NGTIM16 4 /* 16-bit general up/down timers TIM2-3 + * (with DMA) and TIM21-22 without DMA */ +# define STM32_NGTIM32 0 /* No 32-bit general up/down timers */ +# define STM32_NBTIM 2 /* Two basic timers: TIM6, TIM7 with DMA */ + /* One LPTIMER */ +# define STM32_NSPI 2 /* Two SPI modules SPI1-2 */ +# define STM32_NI2S 1 /* One I2S module */ +# define STM32_NI2C 3 /* Three I2C (2 with SMBus/PMBus) */ +# define STM32_NDMA 1 /* One DMA1, 7-channels */ +# define STM32_NUSART 4 /* Four USART modules, USART1-4 */ + /* One LPUART */ +# define STM32_NCAN 0 /* No CAN controllers */ +# define STM32_NLCD 1 /* One LCD controller */ +# define STM32_NUSBDEV 0 /* No USB full-speed device controller */ +# define STM32_NUSBOTG 1 /* One USB OTG FS/HS (only USB 2.0 device) */ +# define STM32_NCEC 0 /* No HDMI-CEC controller */ +# define STM32_NADC 1 /* One 12-bit module */ +# define STM32_NDAC 2 /* Two DAC channels */ +# define STM32_NCOMP 2 /* Two Analog Comparators */ +# define STM32_NCRC 1 /* One CRC module */ +# define STM32_NRNG 1 /* One Random number generator (RNG) */ +# define STM32_NCAP 24 /* Twenty-four Capacitive sensing channels */ +# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-E, H */ + +#endif + +/* NVIC priority levels *****************************************************/ + +/* Each priority field holds a priority value, 0-31. The lower the value, + * the greater the priority of the corresponding interrupt. The processor + * implements only bits[7:6] of each field, bits[5:0] read as zero and + * ignore writes. + */ + +#define NVIC_SYSH_PRIORITY_MIN 0xc0 /* All bits[7:6] set is minimum priority */ +#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */ +#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */ +#define NVIC_SYSH_PRIORITY_STEP 0x40 /* Two bits of interrupt priority used */ + +#endif /* __ARCH_ARM_INCLUDE_STM32L0_CHIP_H */ diff --git a/arch/arm/include/stm32l0/irq.h b/arch/arm/include/stm32l0/irq.h new file mode 100644 index 0000000000000..93fe2b0e049ee --- /dev/null +++ b/arch/arm/include/stm32l0/irq.h @@ -0,0 +1,117 @@ +/**************************************************************************** + * arch/arm/include/stm32l0/irq.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* This file should never be included directly but, rather, only indirectly + * through nuttx/irq.h + */ + +#ifndef __ARCH_ARM_INCLUDE_STM32L0_IRQ_H +#define __ARCH_ARM_INCLUDE_STM32L0_IRQ_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#ifndef __ASSEMBLY__ +# include +#endif +#include + +/**************************************************************************** + * Pre-processor Prototypes + ****************************************************************************/ + +/* IRQ numbers. The IRQ number corresponds vector number and hence map + * directly to bits in the NVIC. This does, however, waste several words of + * memory in the IRQ to handle mapping tables. + */ + +/* Common Processor Exceptions (vectors 0-15) */ + +#define STM32_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */ + /* Vector 0: Reset stack pointer value */ + /* Vector 1: Reset (not handler as an IRQ) */ +#define STM32_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */ +#define STM32_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */ + /* Vectors 4-10: Reserved */ +#define STM32_IRQ_SVCALL (11) /* Vector 11: SVC call */ + /* Vector 12-13: Reserved */ +#define STM32_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */ +#define STM32_IRQ_SYSTICK (15) /* Vector 15: System tick */ + +/* External interrupts (vectors >= 16) */ + +#define STM32_IRQ_EXTINT (16) /* Vector number of the first external interrupt */ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/* External interrupt vectors */ + +#define STM32_IRQ_WWDG (STM32_IRQ_EXTINT + 0) /* 0: Window Watchdog interrupt */ +#define STM32_IRQ_PVD (STM32_IRQ_EXTINT + 1) /* 1: PVD through EXTI Line detection interrupt */ +#define STM32_IRQ_RTC (STM32_IRQ_EXTINT + 2) /* 2: RTC global interrupt */ +#define STM32_IRQ_FLASH (STM32_IRQ_EXTINT + 3) /* 3: Flash global interrupt */ +#define STM32_IRQ_RCC_CRS (STM32_IRQ_EXTINT + 4) /* 4: RCC and CRS global interrupt */ +#define STM32_IRQ_EXTI0_1 (STM32_IRQ_EXTINT + 5) /* 5: EXTI Line 0-1 interrupt */ +#define STM32_IRQ_EXTI2_3 (STM32_IRQ_EXTINT + 6) /* 6: EXTI Line 2-3 interrupt */ +#define STM32_IRQ_EXTI4_15 (STM32_IRQ_EXTINT + 7) /* 7: EXTI Line 4-15 interrupt */ +#define STM32_IRQ_TSC (STM32_IRQ_EXTINT + 8) /* 8: TSC global interrupt */ +#define STM32_IRQ_DMA1CH1 (STM32_IRQ_EXTINT + 9) /* 9: DMA1 channel 1 global interrupt */ +#define STM32_IRQ_DMA1CH2 (STM32_IRQ_EXTINT + 10) /* 10: DMA1 channel 2 global interrupt */ +#define STM32_IRQ_DMA1CH3 (STM32_IRQ_EXTINT + 10) /* 10: DMA1 channel 3 global interrupt */ +#define STM32_IRQ_DMA1CH4 (STM32_IRQ_EXTINT + 11) /* 11: DMA1 channel 4 global interrupt */ +#define STM32_IRQ_DMA1CH5 (STM32_IRQ_EXTINT + 11) /* 11: DMA1 channel 5 global interrupt */ +#define STM32_IRQ_DMA1CH6 (STM32_IRQ_EXTINT + 11) /* 11: DMA1 channel 6 global interrupt */ +#define STM32_IRQ_DMA1CH7 (STM32_IRQ_EXTINT + 11) /* 11: DMA1 channel 7 global interrupt */ +#define STM32_IRQ_ADC (STM32_IRQ_EXTINT + 12) /* 12: ADC global interrupt */ +#define STM32_IRQ_COMP (STM32_IRQ_EXTINT + 12) /* 12: COMP global interrupt */ +#define STM32_IRQ_LPTIM1 (STM32_IRQ_EXTINT + 13) /* 13: LPTIM1 global interrupt */ +#define STM32_IRQ_USART4 (STM32_IRQ_EXTINT + 14) /* 14: USART4 global interrupt */ +#define STM32_IRQ_USART5 (STM32_IRQ_EXTINT + 14) /* 14: USART5 global interrupt */ +#define STM32_IRQ_TIM2 (STM32_IRQ_EXTINT + 15) /* 15: TIM2 global interrupt */ +#define STM32_IRQ_TIM3 (STM32_IRQ_EXTINT + 16) /* 16: TIM3 global interrupt */ +#define STM32_IRQ_TIM6 (STM32_IRQ_EXTINT + 17) /* 17: TIM6 global interrupt */ +#define STM32_IRQ_DAC1 (STM32_IRQ_EXTINT + 17) /* 17: DAC1 global interrupts */ +#define STM32_IRQ_TIM7 (STM32_IRQ_EXTINT + 18) /* 18: TIM7 global interrupt */ +#define STM32_IRQ_RESERVED18 (STM32_IRQ_EXTINT + 18) /* 19: Reserved */ +#define STM32_IRQ_TIM21 (STM32_IRQ_EXTINT + 20) /* 20: TIM21 global interrupt */ +#define STM32_IRQ_I2C3 (STM32_IRQ_EXTINT + 21) /* 21: I2C3 global interrupt */ +#define STM32_IRQ_TIM22 (STM32_IRQ_EXTINT + 22) /* 22: TIM22 global interrupt */ +#define STM32_IRQ_I2C1 (STM32_IRQ_EXTINT + 23) /* 23: I2C1 global interrupt */ +#define STM32_IRQ_I2C2 (STM32_IRQ_EXTINT + 24) /* 24: I2C2 global interrupt */ +#define STM32_IRQ_SPI1 (STM32_IRQ_EXTINT + 25) /* 25: SPI1 global interrupt */ +#define STM32_IRQ_SPI2 (STM32_IRQ_EXTINT + 26) /* 26: SPI2 global interrupt */ +#define STM32_IRQ_USART1 (STM32_IRQ_EXTINT + 27) /* 27: USART1 global interrupt */ +#define STM32_IRQ_USART2 (STM32_IRQ_EXTINT + 28) /* 28: USART2 global interrupt */ +#define STM32_IRQ_LPUART1 (STM32_IRQ_EXTINT + 29) /* 29: LPUART1 global interrupt */ +#define STM32_IRQ_AES (STM32_IRQ_EXTINT + 29) /* 29: AES global interrupt */ +#define STM32_IRQ_RNG (STM32_IRQ_EXTINT + 29) /* 29: RNG global interrupt */ +#define STM32_IRQ_LCD (STM32_IRQ_EXTINT + 30) /* 30: LCD global interrupt */ +#define STM32_IRQ_USB (STM32_IRQ_EXTINT + 31) /* 31: USB global interrupt */ + +#define STM32_IRQ_NEXTINTS (32) + +#define NR_IRQS (STM32_IRQ_EXTINT + STM32_IRQ_NEXTINTS) + +#endif /* __ARCH_ARM_INCLUDE_STM32L0_IRQ_H */ diff --git a/arch/arm/include/stm32l1/chip.h b/arch/arm/include/stm32l1/chip.h new file mode 100644 index 0000000000000..a8b532d3673eb --- /dev/null +++ b/arch/arm/include/stm32l1/chip.h @@ -0,0 +1,491 @@ +/**************************************************************************** + * arch/arm/include/stm32l1/chip.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_INCLUDE_STM32L1_CHIP_H +#define __ARCH_ARM_INCLUDE_STM32L1_CHIP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Prototypes + ****************************************************************************/ + +/* Get customizations for each supported chip and provide alternate function + * pin-mapping + * + * NOTE: Each GPIO pin may serve either for general purpose I/O or for a + * special alternate function (such as USART, CAN, USB, SDIO, etc.). That + * particular pin-mapping will depend on the package and STM32 family. If + * you are incorporating a new STM32 chip into NuttX, you will need to add + * the pin-mapping to a header file and to include that header file below. + * The chip-specific pin-mapping is defined in the chip datasheet. + */ + +/* STM32L EnergyLite Line ***************************************************/ + +/* STM32L151XX -- No LCD + * STM32L152XX -- With LCD + * + * STM32L15XCX -- 48-pins + * STM32L15XRX -- 64-pins + * STM32L15XVX -- 100-pins + * STM32L15XZX -- 144-pins + * + * STM32L15XX6 -- 32KB FLASH, 10KB SRAM, 4KB EEPROM + * STM32L15XX8 -- 64KB FLASH, 10KB SRAM, 4KB EEPROM + * STM32L15XXB -- 128KB FLASH, 16KB SRAM, 4KB EEPROM + * + * STM32L15XXC -- 256KB FLASH, 32KB SRAM, 8KB EEPROM (medium+ density) + * + * STM32L16XXD -- 384KB FLASH, 48KB SRAM, 12KB EEPROM (high density) + * STM32L16XXE -- 512KB FLASH, 80KB SRAM, 16KB EEPROM (high density) + */ + +#if defined(CONFIG_ARCH_CHIP_STM32L151C6) || defined(CONFIG_ARCH_CHIP_STM32L151C8) || \ + defined(CONFIG_ARCH_CHIP_STM32L151CB) +# define STM32_NFSMC 0 /* No FSMC */ +# define STM32_NATIM 0 /* No advanced timers */ +# define STM32_NGTIM 3 /* 16-bit general up/down timers TIM2-4 with DMA */ +# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */ +# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 with DMA */ +# define STM32_NDMA 1 /* DMA1, 7-channels */ +# define STM32_NSPI 2 /* SPI1-2 */ +# define STM32_NI2S 0 /* No I2S */ +# define STM32_NUSART 3 /* USART1-3 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 2 /* I2C1-2 */ +# define STM32_NCAN 0 /* No CAN */ +# define STM32_NSDIO 0 /* No SDIO */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (only USB 2.0 device) */ +# define STM32_NGPIO 37 /* GPIOA-E,H */ +# define STM32_NADC 1 /* ADC1, 14-channels */ +# define STM32_NDAC 2 /* DAC 1, 2 channels */ +# define STM32_NCMP 2 /* (2) Comparators */ +# define STM32_NCAPSENSE 13 /* Capacitive sensing channels */ +# define STM32_NCRC 0 /* No CRC */ +# define STM32_NETHERNET 0 /* No Ethernet */ +# define STM32_NRNG 0 /* No random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32L151R6) || defined(CONFIG_ARCH_CHIP_STM32L151R8) || \ + defined(CONFIG_ARCH_CHIP_STM32L151RB) +# define STM32_NFSMC 0 /* No FSMC */ +# define STM32_NATIM 0 /* No advanced timers */ +# define STM32_NGTIM 3 /* 16-bit general up/down timers TIM2-4 with DMA */ +# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */ +# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 with DMA */ +# define STM32_NDMA 1 /* DMA1, 7-channels */ +# define STM32_NSPI 2 /* SPI1-2 */ +# define STM32_NI2S 0 /* No I2S */ +# define STM32_NUSART 3 /* USART1-3 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 2 /* I2C1-2 */ +# define STM32_NCAN 0 /* No CAN */ +# define STM32_NSDIO 0 /* No SDIO */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (only USB 2.0 device) */ +# define STM32_NGPIO 51 /* GPIOA-E,H */ +# define STM32_NADC 1 /* ADC1, 20-channels */ +# define STM32_NDAC 2 /* DAC , 2 channels */ +# define STM32_NCMP 2 /* (2) Comparators */ +# define STM32_NCAPSENSE 20 /* Capacitive sensing channels */ +# define STM32_NCRC 0 /* No CRC */ +# define STM32_NETHERNET 0 /* No Ethernet */ +# define STM32_NRNG 0 /* No random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32L151V6) || defined(CONFIG_ARCH_CHIP_STM32L151V8) || \ + defined(CONFIG_ARCH_CHIP_STM32L151VB) +# define STM32_NFSMC 0 /* No FSMC */ +# define STM32_NATIM 0 /* No advanced timers */ +# define STM32_NGTIM 3 /* 16-bit general up/down timers TIM2-4 with DMA */ +# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */ +# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 with DMA */ +# define STM32_NDMA 1 /* DMA1, 7-channels */ +# define STM32_NSPI 2 /* SPI1-2 */ +# define STM32_NI2S 0 /* No I2S */ +# define STM32_NUSART 3 /* USART1-3 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 2 /* I2C1-2 */ +# define STM32_NCAN 0 /* No CAN */ +# define STM32_NSDIO 0 /* No SDIO */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (only USB 2.0 device) */ +# define STM32_NGPIO 83 /* GPIOA-E,H */ +# define STM32_NADC 1 /* ADC1, 24-channels */ +# define STM32_NDAC 2 /* DAC 1, 2 channels */ +# define STM32_NCMP 2 /* (2) Comparators */ +# define STM32_NCAPSENSE 20 /* Capacitive sensing channels */ +# define STM32_NCRC 0 /* No CRC */ +# define STM32_NETHERNET 0 /* No Ethernet */ +# define STM32_NRNG 0 /* No random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32L152C6) || defined(CONFIG_ARCH_CHIP_STM32L152C8) || \ + defined(CONFIG_ARCH_CHIP_STM32L152CB) +# define STM32_NFSMC 0 /* No FSMC */ +# define STM32_NATIM 0 /* No advanced timers */ +# define STM32_NGTIM 3 /* 16-bit general up/down timers TIM2-4 with DMA */ +# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */ +# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 with DMA */ +# define STM32_NDMA 1 /* DMA1, 7-channels */ +# define STM32_NSPI 2 /* SPI1-2 */ +# define STM32_NI2S 0 /* No I2S */ +# define STM32_NUSART 3 /* USART1-3 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 2 /* I2C1-2 */ +# define STM32_NCAN 0 /* No CAN */ +# define STM32_NSDIO 0 /* No SDIO */ +# define STM32_NLCD 1 /* LCD 4x18 */ +# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (only USB 2.0 device) */ +# define STM32_NGPIO 37 /* GPIOA-E,H */ +# define STM32_NADC 1 /* ADC1, 14-channels */ +# define STM32_NDAC 2 /* DAC 1, 2 channels */ +# define STM32_NCMP 2 /* (2) Comparators */ +# define STM32_NCAPSENSE 13 /* Capacitive sensing channels */ +# define STM32_NCRC 0 /* No CRC */ +# define STM32_NETHERNET 0 /* No Ethernet */ +# define STM32_NRNG 0 /* No random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32L152R6) || defined(CONFIG_ARCH_CHIP_STM32L152R8) || \ + defined(CONFIG_ARCH_CHIP_STM32L152RB) +# define STM32_NFSMC 0 /* No FSMC */ +# define STM32_NATIM 0 /* No advanced timers */ +# define STM32_NGTIM 3 /* 16-bit general up/down timers TIM2-4 with DMA */ +# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */ +# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 with DMA */ +# define STM32_NDMA 1 /* DMA1, 7-channels */ +# define STM32_NSPI 2 /* SPI1-2 */ +# define STM32_NI2S 0 /* No I2S */ +# define STM32_NUSART 3 /* USART1-3 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 2 /* I2C1-2 */ +# define STM32_NCAN 0 /* No CAN */ +# define STM32_NSDIO 0 /* No SDIO */ +# define STM32_NLCD 1 /* LCD 4x32, 8x28 */ +# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (only USB 2.0 device) */ +# define STM32_NGPIO 51 /* GPIOA-E,H */ +# define STM32_NADC 1 /* ADC1, 20-channels */ +# define STM32_NDAC 2 /* DAC 1, 2 channels */ +# define STM32_NCMP 2 /* (2) Comparators */ +# define STM32_NCAPSENSE 20 /* Capacitive sensing channels */ +# define STM32_NCRC 0 /* No CRC */ +# define STM32_NETHERNET 0 /* No Ethernet */ +# define STM32_NRNG 0 /* No random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32L152V6) || defined(CONFIG_ARCH_CHIP_STM32L152V8) || \ + defined(CONFIG_ARCH_CHIP_STM32L152VB) +# define STM32_NFSMC 0 /* No FSMC */ +# define STM32_NATIM 0 /* No advanced timers */ +# define STM32_NGTIM 3 /* 16-bit general up/down timers TIM2-4 with DMA */ +# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */ +# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 with DMA */ +# define STM32_NDMA 1 /* DMA1, 7-channels */ +# define STM32_NSPI 2 /* SPI1-2 */ +# define STM32_NI2S 0 /* No I2S */ +# define STM32_NUSART 3 /* USART1-3 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 2 /* I2C1-2 */ +# define STM32_NCAN 0 /* No CAN */ +# define STM32_NSDIO 0 /* No SDIO */ +# define STM32_NLCD 1 /* LCD 4x44, 8x40 */ +# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (only USB 2.0 device) */ +# define STM32_NGPIO 83 /* GPIOA-E,H */ +# define STM32_NADC 1 /* ADC1, 24-channels */ +# define STM32_NDAC 2 /* DAC 1, 2 channels */ +# define STM32_NCMP 2 /* (2) Comparators */ +# define STM32_NCAPSENSE 20 /* Capacitive sensing channels */ +# define STM32_NCRC 0 /* No CRC */ +# define STM32_NETHERNET 0 /* No Ethernet */ +# define STM32_NRNG 0 /* No random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32L152CC) +# define STM32_NFSMC 0 /* No FSMC */ +# define STM32_NATIM 0 /* No advanced timers */ +# define STM32_NGTIM 3 /* 16-bit general up/down timers TIM2-4 with DMA */ +# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */ +# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 with DMA */ +# define STM32_NDMA 2 /* DMA1, 7-channels, DMA2 (5 channels) */ +# define STM32_NSPI 3 /* SPI1-3 */ +# define STM32_NI2S 2 /* I2S1-2, overlapping with SPI2-3 */ +# define STM32_NUSART 3 /* USART1-3 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 2 /* I2C1-2 */ +# define STM32_NCAN 0 /* No CAN */ +# define STM32_NSDIO 0 /* No SDIO */ +# define STM32_NLCD 1 /* LCD 4x18 */ +# define STM32_NUSBOTG 1 /* USB OTG FS/HS (only USB 2.0 device) */ +# define STM32_NGPIO 37 /* GPIOA-E,H */ +# define STM32_NADC 1 /* ADC1, 14-channels */ +# define STM32_NDAC 2 /* DAC 1, 2 channels */ +# define STM32_NCMP 2 /* (2) Comparators */ +# define STM32_NCAPSENSE 16 /* Capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NETHERNET 0 /* No ethernet */ +# define STM32_NRNG 0 /* No random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32L152RC) +# define STM32_NFSMC 0 /* No FSMC */ +# define STM32_NATIM 0 /* No advanced timers */ +# define STM32_NGTIM 3 /* 16-bit general up/down timers TIM2-4 with DMA */ +# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */ +# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 with DMA */ +# define STM32_NDMA 2 /* DMA1, 7-channels, DMA2 (5 channels) */ +# define STM32_NSPI 3 /* SPI1-3 */ +# define STM32_NI2S 2 /* I2S1-2, overlapping with SPI2-3 */ +# define STM32_NUSART 3 /* USART1-3 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 2 /* I2C1-2 */ +# define STM32_NCAN 0 /* No CAN */ +# define STM32_NSDIO 0 /* No SDIO */ +# define STM32_NLCD 1 /* LCD 4x32, 8x28 */ +# define STM32_NUSBOTG 1 /* USB OTG FS/HS (only USB 2.0 device) */ +# define STM32_NGPIO 51 /* GPIOA-E,H */ +# define STM32_NADC 1 /* ADC1, 21-channels */ +# define STM32_NDAC 2 /* DAC 1, 2 channels */ +# define STM32_NCMP 2 /* (2) Comparators */ +# define STM32_NCAPSENSE 23 /* Capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NETHERNET 0 /* No ethernet */ +# define STM32_NRNG 0 /* No random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32L152VC) +# define STM32_NFSMC 0 /* No FSMC */ +# define STM32_NATIM 0 /* No advanced timers */ +# define STM32_NGTIM 3 /* 16-bit general up/down timers TIM2-4 with DMA */ +# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */ +# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 with DMA */ +# define STM32_NDMA 2 /* DMA1, 7-channels, DMA2 (5 channels) */ +# define STM32_NSPI 3 /* SPI1-3 */ +# define STM32_NI2S 2 /* I2S1-2, overlapping with SPI2-3 */ +# define STM32_NUSART 3 /* USART1-3 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 2 /* I2C1-2 */ +# define STM32_NCAN 0 /* No CAN */ +# define STM32_NSDIO 0 /* No SDIO */ +# define STM32_NLCD 1 /* LCD 4x44, 8x40 */ +# define STM32_NUSBOTG 1 /* USB OTG FS/HS (only USB 2.0 device) */ +# define STM32_NGPIO 83 /* GPIOA-E,H */ +# define STM32_NADC 1 /* ADC1, 25-channels */ +# define STM32_NDAC 2 /* DAC 1, 2 channels */ +# define STM32_NCMP 2 /* (2) Comparators */ +# define STM32_NCAPSENSE 23 /* Capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NETHERNET 0 /* No ethernet */ +# define STM32_NRNG 0 /* No random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32L151RE) || defined(CONFIG_ARCH_CHIP_STM32L152RE) +# define STM32_NFSMC 0 /* No FSMC */ +# define STM32_NATIM 0 /* No advanced timers */ +# define STM32_NGTIM 3 /* 16-bit general up/down timers TIM2-4 with DMA */ +# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */ +# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 with DMA */ +# define STM32_NDMA 2 /* DMA1, 7-channels, DMA2 (5 channels) */ +# define STM32_NSPI 3 /* SPI1-3 */ +# define STM32_NI2S 2 /* I2S1-2, overlapping with SPI2-3 */ +# define STM32_NUSART 5 /* USART1-5 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 2 /* I2C1-2 */ +# define STM32_NCAN 0 /* No CAN */ +# define STM32_NSDIO 0 /* No SDIO */ +# define STM32_NLCD 1 /* LCD 4x44, 8x40 */ +# define STM32_NUSBOTG 1 /* USB OTG FS/HS (only USB 2.0 device) */ +# define STM32_NGPIO 51 /* GPIOA-E,H */ +# define STM32_NADC 1 /* ADC1, 25-channels */ +# define STM32_NDAC 2 /* DAC 1, 2 channels */ +# define STM32_NCMP 2 /* (2) Comparators */ +# define STM32_NCAPSENSE 23 /* Capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NETHERNET 0 /* No ethernet */ +# define STM32_NRNG 0 /* No random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32L151VE) || defined(CONFIG_ARCH_CHIP_STM32L152VE) +# define STM32_NFSMC 0 /* No FSMC */ +# define STM32_NATIM 0 /* No advanced timers */ +# define STM32_NGTIM 3 /* 16-bit general up/down timers TIM2-4 with DMA */ +# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */ +# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 with DMA */ +# define STM32_NDMA 2 /* DMA1, 7-channels, DMA2 (5 channels) */ +# define STM32_NSPI 3 /* SPI1-3 */ +# define STM32_NI2S 2 /* I2S1-2, overlapping with SPI2-3 */ +# define STM32_NUSART 5 /* USART1-5 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 2 /* I2C1-2 */ +# define STM32_NCAN 0 /* No CAN */ +# define STM32_NSDIO 0 /* No SDIO */ +# define STM32_NLCD 1 /* LCD 4x44, 8x40 */ +# define STM32_NUSBOTG 1 /* USB OTG FS/HS (only USB 2.0 device) */ +# define STM32_NGPIO 83 /* GPIOA-E,H */ +# define STM32_NADC 1 /* ADC1, 25-channels */ +# define STM32_NDAC 2 /* DAC 1, 2 channels */ +# define STM32_NCMP 2 /* (2) Comparators */ +# define STM32_NCAPSENSE 23 /* Capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NETHERNET 0 /* No ethernet */ +# define STM32_NRNG 0 /* No random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32L151QE) || defined(CONFIG_ARCH_CHIP_STM32L152QE) +# define STM32_NFSMC 0 /* No FSMC */ +# define STM32_NATIM 0 /* No advanced timers */ +# define STM32_NGTIM 3 /* 16-bit general up/down timers TIM2-4 with DMA */ +# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */ +# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 with DMA */ +# define STM32_NDMA 2 /* DMA1, 7-channels, DMA2 (5 channels) */ +# define STM32_NSPI 3 /* SPI1-3 */ +# define STM32_NI2S 2 /* I2S1-2, overlapping with SPI2-3 */ +# define STM32_NUSART 5 /* USART1-5 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 2 /* I2C1-2 */ +# define STM32_NCAN 0 /* No CAN */ +# define STM32_NSDIO 0 /* No SDIO */ +# define STM32_NLCD 1 /* LCD 4x44, 8x40 */ +# define STM32_NUSBOTG 1 /* USB OTG FS/HS (only USB 2.0 device) */ +# define STM32_NGPIO 109 /* GPIOA-E,H */ +# define STM32_NADC 1 /* ADC1, 25-channels */ +# define STM32_NDAC 2 /* DAC 1, 2 channels */ +# define STM32_NCMP 2 /* (2) Comparators */ +# define STM32_NCAPSENSE 33 /* Capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NETHERNET 0 /* No ethernet */ +# define STM32_NRNG 0 /* No random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32L151ZE) || defined(CONFIG_ARCH_CHIP_STM32L152ZE) +# define STM32_NFSMC 0 /* No FSMC */ +# define STM32_NATIM 0 /* No advanced timers */ +# define STM32_NGTIM 3 /* 16-bit general up/down timers TIM2-4 with DMA */ +# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */ +# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 with DMA */ +# define STM32_NDMA 2 /* DMA1, 7-channels, DMA2 (5 channels) */ +# define STM32_NSPI 3 /* SPI1-3 */ +# define STM32_NI2S 2 /* I2S1-2, overlapping with SPI2-3 */ +# define STM32_NUSART 5 /* USART1-5 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 2 /* I2C1-2 */ +# define STM32_NCAN 0 /* No CAN */ +# define STM32_NSDIO 0 /* No SDIO */ +# define STM32_NLCD 1 /* LCD 4x44, 8x40 */ +# define STM32_NUSBOTG 1 /* USB OTG FS/HS (only USB 2.0 device) */ +# define STM32_NGPIO 115 /* GPIOA-E,H */ +# define STM32_NADC 1 /* ADC1, 25-channels */ +# define STM32_NDAC 2 /* DAC 1, 2 channels */ +# define STM32_NCMP 2 /* (2) Comparators */ +# define STM32_NCAPSENSE 34 /* Capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NETHERNET 0 /* No ethernet */ +# define STM32_NRNG 0 /* No random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32L162ZD) +# define STM32_NFSMC 1 /* FSMC */ +# define STM32_NATIM 0 /* No advanced timers */ +# define STM32_NGTIM 4 /* 16-bit general timers TIM2-4 with DMA + * 32-bit general timer TIM5 with DMA */ +# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */ +# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 without DMA */ +# define STM32_NDMA 2 /* DMA1, 7-channels, DMA2 (5 channels) */ +# define STM32_NSPI 3 /* SPI1-3 */ +# define STM32_NI2S 2 /* I2S1-2, overlapping with SPI2-3 */ +# define STM32_NUSART 5 /* USART1-3, UART4-5 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 2 /* I2C1-2 */ +# define STM32_NCAN 0 /* No CAN */ +# define STM32_NSDIO 1 /* SDIO */ +# define STM32_NLCD 1 /* LCD 4x44, 8x40 */ +# define STM32_NUSBOTG 1 /* USB OTG FS/HS (only USB 2.0 device) */ +# define STM32_NGPIO 115 /* GPIOA-G,H */ +# define STM32_NADC 1 /* ADC1, 40-channels */ +# define STM32_NDAC 2 /* DAC 1, 2 channels */ +# define STM32_NCMP 2 /* (2) Comparators */ +# define STM32_NCAPSENSE 34 /* Capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NETHERNET 0 /* No ethernet */ +# define STM32_NRNG 0 /* No random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32L162VE) +# define STM32_NFSMC 0 /* No FSMC */ +# define STM32_NATIM 0 /* No advanced timers */ +# define STM32_NGTIM 4 /* 16-bit general timers TIM2-4 with DMA + * 32-bit general timer TIM5 with DMA */ +# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */ +# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 with DMA */ +# define STM32_NDMA 2 /* DMA1, 12-channels */ +# define STM32_NSPI 3 /* SPI1-3 */ +# define STM32_NI2S 2 /* I2S1-2, overlapping with SPI2-3 */ +# define STM32_NUSART 5 /* USART1-3, UART4-5 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 2 /* I2C1-2 */ +# define STM32_NCAN 0 /* No CAN */ +# define STM32_NSDIO 0 /* No SDIO */ +# define STM32_NLCD 1 /* LCD 4x44, 8x40*/ +# define STM32_NUSBOTG 1 /* USB OTG FS/HS (only USB 2.0 device) */ +# define STM32_NGPIO 83 /* GPIOA-G,H */ + +# define STM32_NADC 1 /* ADC1, 25-channels */ +# define STM32_NDAC 2 /* DAC 1, 2 channels */ +# define STM32_NCMP 2 /* (2) Comparators */ +# define STM32_NCAPSENSE 23 /* Capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NETHERNET 0 /* No ethernet */ +# define STM32_NRNG 0 /* No random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + +/* STM32 F100 Value Line ****************************************************/ + +#else +# error "Unsupported STM32 chip" +#endif + +/* Peripheral IP versions ***************************************************/ + +/* Peripheral IP versions are invariant and should be decided here, not in + * Kconfig. + * + * REVISIT: Currently only SPI IP version is handled here, with others being + * handled in Kconfig. Those others need to be gradually refactored + * and resolved here. + */ + +#define STM32_HAVE_IP_SPI_V1 + +/* NVIC priority levels *****************************************************/ + +#define NVIC_SYSH_PRIORITY_MIN 0xf0 /* All bits set in minimum priority */ +#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */ +#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */ +#define NVIC_SYSH_PRIORITY_STEP 0x10 /* Four bits of interrupt priority used */ + +#endif /* __ARCH_ARM_INCLUDE_STM32L1_CHIP_H */ diff --git a/arch/arm/include/stm32l1/irq.h b/arch/arm/include/stm32l1/irq.h new file mode 100644 index 0000000000000..cba5263dd4224 --- /dev/null +++ b/arch/arm/include/stm32l1/irq.h @@ -0,0 +1,252 @@ +/**************************************************************************** + * arch/arm/include/stm32l1/irq.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* This file should never be included directly but, rather, + * only indirectly through nuttx/irq.h + */ + +#ifndef __ARCH_ARM_INCLUDE_STM32L1_IRQ_H +#define __ARCH_ARM_INCLUDE_STM32L1_IRQ_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include + +/**************************************************************************** + * Pre-processor Prototypes + ****************************************************************************/ + +/* IRQ numbers. + * The IRQ number corresponds vector number and hence map directly to + * bits in the NVIC. This does, however, waste several words of memory in + * the IRQ to handle mapping tables. + */ + +/* Processor Exceptions (vectors 0-15) */ + +#define STM32_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */ + /* Vector 0: Reset stack pointer value */ + /* Vector 1: Reset (not handler as an IRQ) */ +#define STM32_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */ +#define STM32_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */ +#define STM32_IRQ_MEMFAULT (4) /* Vector 4: Memory management (MPU) */ +#define STM32_IRQ_BUSFAULT (5) /* Vector 5: Bus fault */ +#define STM32_IRQ_USAGEFAULT (6) /* Vector 6: Usage fault */ +#define STM32_IRQ_SVCALL (11) /* Vector 11: SVC call */ +#define STM32_IRQ_DBGMONITOR (12) /* Vector 12: Debug Monitor */ + /* Vector 13: Reserved */ +#define STM32_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */ +#define STM32_IRQ_SYSTICK (15) /* Vector 15: System tick */ + +/* External interrupts (vectors >= 16). + * These definitions are chip-specific + */ + +#define STM32_IRQ_FIRST (16) /* Vector number of the first external interrupt */ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#if defined(CONFIG_STM32L1_LOWDENSITY) || defined(CONFIG_STM32L1_MEDIUMDENSITY) +# define STM32_IRQ_WWDG (STM32_IRQ_FIRST + 0) /* 0: Window Watchdog interrupt */ +# define STM32_IRQ_PVD (STM32_IRQ_FIRST + 1) /* 1: PVD through EXTI Line detection interrupt */ +# define STM32_IRQ_TAMPER (STM32_IRQ_FIRST + 2) /* 2: Tamper through EXTI line interrupt, or */ +# define STM32_IRQ_TIMESTAMP (STM32_IRQ_FIRST + 2) /* 2: Time stamp through EXTI line interrupt */ +# define STM32_IRQ_RTC_WKUP (STM32_IRQ_FIRST + 3) /* 3: RTC Wakeup through EXTI line interrupt */ +# define STM32_IRQ_FLASH (STM32_IRQ_FIRST + 4) /* 4: Flash global interrupt */ +# define STM32_IRQ_RCC (STM32_IRQ_FIRST + 5) /* 5: RCC global interrupt */ +# define STM32_IRQ_EXTI0 (STM32_IRQ_FIRST + 6) /* 6: EXTI Line 0 interrupt */ +# define STM32_IRQ_EXTI1 (STM32_IRQ_FIRST + 7) /* 7: EXTI Line 1 interrupt */ +# define STM32_IRQ_EXTI2 (STM32_IRQ_FIRST + 8) /* 8: EXTI Line 2 interrupt */ +# define STM32_IRQ_EXTI3 (STM32_IRQ_FIRST + 9) /* 9: EXTI Line 3 interrupt */ +# define STM32_IRQ_EXTI4 (STM32_IRQ_FIRST + 10) /* 10: EXTI Line 4 interrupt */ +# define STM32_IRQ_DMA1CH1 (STM32_IRQ_FIRST + 11) /* 11: DMA1 channel 1 global interrupt */ +# define STM32_IRQ_DMA1CH2 (STM32_IRQ_FIRST + 12) /* 12: DMA1 channel 2 global interrupt */ +# define STM32_IRQ_DMA1CH3 (STM32_IRQ_FIRST + 13) /* 13: DMA1 channel 3 global interrupt */ +# define STM32_IRQ_DMA1CH4 (STM32_IRQ_FIRST + 14) /* 14: DMA1 channel 4 global interrupt */ +# define STM32_IRQ_DMA1CH5 (STM32_IRQ_FIRST + 15) /* 15: DMA1 channel 5 global interrupt */ +# define STM32_IRQ_DMA1CH6 (STM32_IRQ_FIRST + 16) /* 16: DMA1 channel 6 global interrupt */ +# define STM32_IRQ_DMA1CH7 (STM32_IRQ_FIRST + 17) /* 17: DMA1 channel 7 global interrupt */ +# define STM32_IRQ_ADC1 (STM32_IRQ_FIRST + 18) /* 18: ADC1 global interrupt */ +# define STM32_IRQ_USBHP (STM32_IRQ_FIRST + 19) /* 19: USB High Priority interrupts */ +# define STM32_IRQ_USBLP (STM32_IRQ_FIRST + 20) /* 20: USB Low Priority interrupt */ +# define STM32_IRQ_DAC (STM32_IRQ_FIRST + 21) /* 21: DAC interrupt */ +# define STM32_IRQ_COMP (STM32_IRQ_FIRST + 22) /* 22: Comparator wakeup through EXTI interrupt */ +# define STM32_IRQ_EXTI95 (STM32_IRQ_FIRST + 23) /* 23: EXTI Line[9:5] interrupts */ +# define STM32_IRQ_LDC (STM32_IRQ_FIRST + 24) /* 24: LCD global interrupt */ +# define STM32_IRQ_TIM9 (STM32_IRQ_FIRST + 25) /* 25: TIM9 global interrupt */ +# define STM32_IRQ_TIM10 (STM32_IRQ_FIRST + 26) /* 26: TIM10 global interrupt */ +# define STM32_IRQ_TIM11 (STM32_IRQ_FIRST + 27) /* 27: TIM11 global interrupt */ +# define STM32_IRQ_TIM2 (STM32_IRQ_FIRST + 28) /* 28: TIM2 global interrupt */ +# define STM32_IRQ_TIM3 (STM32_IRQ_FIRST + 29) /* 29: TIM3 global interrupt */ +# define STM32_IRQ_TIM4 (STM32_IRQ_FIRST + 30) /* 30: TIM4 global interrupt */ +# define STM32_IRQ_I2C1EV (STM32_IRQ_FIRST + 31) /* 31: I2C1 event interrupt */ +# define STM32_IRQ_I2C1ER (STM32_IRQ_FIRST + 32) /* 32: I2C1 error interrupt */ +# define STM32_IRQ_I2C2EV (STM32_IRQ_FIRST + 33) /* 33: I2C2 event interrupt */ +# define STM32_IRQ_I2C2ER (STM32_IRQ_FIRST + 34) /* 34: I2C2 error interrupt */ +# define STM32_IRQ_SPI1 (STM32_IRQ_FIRST + 35) /* 35: SPI1 global interrupt */ +# define STM32_IRQ_SPI2 (STM32_IRQ_FIRST + 36) /* 36: SPI2 global interrupt */ +# define STM32_IRQ_USART1 (STM32_IRQ_FIRST + 37) /* 37: USART1 global interrupt */ +# define STM32_IRQ_USART2 (STM32_IRQ_FIRST + 38) /* 38: USART2 global interrupt */ +# define STM32_IRQ_USART3 (STM32_IRQ_FIRST + 39) /* 39: USART3 global interrupt */ +# define STM32_IRQ_EXTI1510 (STM32_IRQ_FIRST + 40) /* 40: EXTI Line[15:10] interrupts */ +# define STM32_IRQ_RTCALRM (STM32_IRQ_FIRST + 41) /* 41: RTC alarm through EXTI line interrupt */ +# define STM32_IRQ_USBWKUP (STM32_IRQ_FIRST + 42) /* 42: USB wakeup from suspend through EXTI line interrupt */ +# define STM32_IRQ_TIM6 (STM32_IRQ_FIRST + 43) /* 43: TIM6 global interrupt */ +# define STM32_IRQ_TIM7 (STM32_IRQ_FIRST + 44) /* 44: TIM7 global interrupt */ + +# define STM32_IRQ_NEXTINTS (45) + +#elif defined(CONFIG_STM32_MEDIUMPLUSDENSITY) +# define STM32_IRQ_WWDG (STM32_IRQ_FIRST + 0) /* 0: Window Watchdog interrupt */ +# define STM32_IRQ_PVD (STM32_IRQ_FIRST + 1) /* 1: PVD through EXTI Line detection interrupt */ +# define STM32_IRQ_TAMPER (STM32_IRQ_FIRST + 2) /* 2: Tamper through EXTI line interrupt, or */ +# define STM32_IRQ_TIMESTAMP (STM32_IRQ_FIRST + 2) /* 2: Time stamp through EXTI line interrupt */ +# define STM32_IRQ_RTC_WKUP (STM32_IRQ_FIRST + 3) /* 3: RTC Wakeup through EXTI line interrupt */ +# define STM32_IRQ_FLASH (STM32_IRQ_FIRST + 4) /* 4: Flash global interrupt */ +# define STM32_IRQ_RCC (STM32_IRQ_FIRST + 5) /* 5: RCC global interrupt */ +# define STM32_IRQ_EXTI0 (STM32_IRQ_FIRST + 6) /* 6: EXTI Line 0 interrupt */ +# define STM32_IRQ_EXTI1 (STM32_IRQ_FIRST + 7) /* 7: EXTI Line 1 interrupt */ +# define STM32_IRQ_EXTI2 (STM32_IRQ_FIRST + 8) /* 8: EXTI Line 2 interrupt */ +# define STM32_IRQ_EXTI3 (STM32_IRQ_FIRST + 9) /* 9: EXTI Line 3 interrupt */ +# define STM32_IRQ_EXTI4 (STM32_IRQ_FIRST + 10) /* 10: EXTI Line 4 interrupt */ +# define STM32_IRQ_DMA1CH1 (STM32_IRQ_FIRST + 11) /* 11: DMA1 channel 1 global interrupt */ +# define STM32_IRQ_DMA1CH2 (STM32_IRQ_FIRST + 12) /* 12: DMA1 channel 2 global interrupt */ +# define STM32_IRQ_DMA1CH3 (STM32_IRQ_FIRST + 13) /* 13: DMA1 channel 3 global interrupt */ +# define STM32_IRQ_DMA1CH4 (STM32_IRQ_FIRST + 14) /* 14: DMA1 channel 4 global interrupt */ +# define STM32_IRQ_DMA1CH5 (STM32_IRQ_FIRST + 15) /* 15: DMA1 channel 5 global interrupt */ +# define STM32_IRQ_DMA1CH6 (STM32_IRQ_FIRST + 16) /* 16: DMA1 channel 6 global interrupt */ +# define STM32_IRQ_DMA1CH7 (STM32_IRQ_FIRST + 17) /* 17: DMA1 channel 7 global interrupt */ +# define STM32_IRQ_ADC1 (STM32_IRQ_FIRST + 18) /* 18: ADC1 global interrupt */ +# define STM32_IRQ_USBHP (STM32_IRQ_FIRST + 19) /* 19: USB High Priority interrupts */ +# define STM32_IRQ_USBLP (STM32_IRQ_FIRST + 20) /* 20: USB Low Priority interrupt */ +# define STM32_IRQ_DAC (STM32_IRQ_FIRST + 21) /* 21: DAC interrupt */ +# define STM32_IRQ_COMP (STM32_IRQ_FIRST + 22) /* 22: Comparator wakeup through EXTI interrupt, or */ +# define STM32_IRQ_CA (STM32_IRQ_FIRST + 22) /* 22: Channel acquisition interrupt */ +# define STM32_IRQ_EXTI95 (STM32_IRQ_FIRST + 23) /* 23: EXTI Line[9:5] interrupts */ +# define STM32_IRQ_LDC (STM32_IRQ_FIRST + 24) /* 24: LCD global interrupt */ +# define STM32_IRQ_TIM9 (STM32_IRQ_FIRST + 25) /* 25: TIM9 global interrupt */ +# define STM32_IRQ_TIM10 (STM32_IRQ_FIRST + 26) /* 26: TIM10 global interrupt */ +# define STM32_IRQ_TIM11 (STM32_IRQ_FIRST + 27) /* 27: TIM11 global interrupt */ +# define STM32_IRQ_TIM2 (STM32_IRQ_FIRST + 28) /* 28: TIM2 global interrupt */ +# define STM32_IRQ_TIM3 (STM32_IRQ_FIRST + 29) /* 29: TIM3 global interrupt */ +# define STM32_IRQ_TIM4 (STM32_IRQ_FIRST + 30) /* 30: TIM4 global interrupt */ +# define STM32_IRQ_I2C1EV (STM32_IRQ_FIRST + 31) /* 31: I2C1 event interrupt */ +# define STM32_IRQ_I2C1ER (STM32_IRQ_FIRST + 32) /* 32: I2C1 error interrupt */ +# define STM32_IRQ_I2C2EV (STM32_IRQ_FIRST + 33) /* 33: I2C2 event interrupt */ +# define STM32_IRQ_I2C2ER (STM32_IRQ_FIRST + 34) /* 34: I2C2 error interrupt */ +# define STM32_IRQ_SPI1 (STM32_IRQ_FIRST + 35) /* 35: SPI1 global interrupt */ +# define STM32_IRQ_SPI2 (STM32_IRQ_FIRST + 36) /* 36: SPI2 global interrupt */ +# define STM32_IRQ_USART1 (STM32_IRQ_FIRST + 37) /* 37: USART1 global interrupt */ +# define STM32_IRQ_USART2 (STM32_IRQ_FIRST + 38) /* 38: USART2 global interrupt */ +# define STM32_IRQ_USART3 (STM32_IRQ_FIRST + 39) /* 39: USART3 global interrupt */ +# define STM32_IRQ_EXTI1510 (STM32_IRQ_FIRST + 40) /* 40: EXTI Line[15:10] interrupts */ +# define STM32_IRQ_RTCALRM (STM32_IRQ_FIRST + 41) /* 41: RTC alarm through EXTI line interrupt */ +# define STM32_IRQ_USBWKUP (STM32_IRQ_FIRST + 42) /* 42: USB wakeup from suspend through EXTI line interrupt */ +# define STM32_IRQ_TIM6 (STM32_IRQ_FIRST + 43) /* 43: TIM6 global interrupt */ +# define STM32_IRQ_TIM7 (STM32_IRQ_FIRST + 44) /* 44: TIM7 global interrupt */ +# define STM32_IRQ_TIM5 (STM32_IRQ_FIRST + 45) /* 45: TIM5 global interrupt */ +# define STM32_IRQ_SPI3 (STM32_IRQ_FIRST + 46) /* 46: SPI3 global interrupt */ +# define STM32_IRQ_DMA2CH1 (STM32_IRQ_FIRST + 47) /* 47: DMA2 channel 1 global interrupt */ +# define STM32_IRQ_DMA2CH2 (STM32_IRQ_FIRST + 48) /* 48: DMA2 channel 2 global interrupt */ +# define STM32_IRQ_DMA2CH3 (STM32_IRQ_FIRST + 49) /* 49: DMA2 channel 3 global interrupt */ +# define STM32_IRQ_DMA2CH4 (STM32_IRQ_FIRST + 50) /* 50: DMA2 channel 4 global interrupt */ +# define STM32_IRQ_DMA2CH5 (STM32_IRQ_FIRST + 51) /* 51: DMA2 channel 5 global interrupt */ +# define STM32_IRQ_AES (STM32_IRQ_FIRST + 52) /* 52: AES global interrupt */ +# define STM32_IRQ_COMPACQ (STM32_IRQ_FIRST + 53) /* 53: Comparator Channel Acquisition Interrupt */ + +# define STM32_IRQ_NEXTINTS (54) + +#elif defined(CONFIG_STM32L1_HIGHDENSITY) +# define STM32_IRQ_WWDG (STM32_IRQ_FIRST + 0) /* 0: Window Watchdog interrupt */ +# define STM32_IRQ_PVD (STM32_IRQ_FIRST + 1) /* 1: PVD through EXTI Line detection interrupt */ +# define STM32_IRQ_TAMPER (STM32_IRQ_FIRST + 2) /* 2: Tamper through EXTI line interrupt, or */ +# define STM32_IRQ_TIMESTAMP (STM32_IRQ_FIRST + 2) /* 2: Time stamp through EXTI line interrupt */ +# define STM32_IRQ_RTC_WKUP (STM32_IRQ_FIRST + 3) /* 3: RTC Wakeup through EXTI line interrupt */ +# define STM32_IRQ_FLASH (STM32_IRQ_FIRST + 4) /* 4: Flash global interrupt */ +# define STM32_IRQ_RCC (STM32_IRQ_FIRST + 5) /* 5: RCC global interrupt */ +# define STM32_IRQ_EXTI0 (STM32_IRQ_FIRST + 6) /* 6: EXTI Line 0 interrupt */ +# define STM32_IRQ_EXTI1 (STM32_IRQ_FIRST + 7) /* 7: EXTI Line 1 interrupt */ +# define STM32_IRQ_EXTI2 (STM32_IRQ_FIRST + 8) /* 8: EXTI Line 2 interrupt */ +# define STM32_IRQ_EXTI3 (STM32_IRQ_FIRST + 9) /* 9: EXTI Line 3 interrupt */ +# define STM32_IRQ_EXTI4 (STM32_IRQ_FIRST + 10) /* 10: EXTI Line 4 interrupt */ +# define STM32_IRQ_DMA1CH1 (STM32_IRQ_FIRST + 11) /* 11: DMA1 channel 1 global interrupt */ +# define STM32_IRQ_DMA1CH2 (STM32_IRQ_FIRST + 12) /* 12: DMA1 channel 2 global interrupt */ +# define STM32_IRQ_DMA1CH3 (STM32_IRQ_FIRST + 13) /* 13: DMA1 channel 3 global interrupt */ +# define STM32_IRQ_DMA1CH4 (STM32_IRQ_FIRST + 14) /* 14: DMA1 channel 4 global interrupt */ +# define STM32_IRQ_DMA1CH5 (STM32_IRQ_FIRST + 15) /* 15: DMA1 channel 5 global interrupt */ +# define STM32_IRQ_DMA1CH6 (STM32_IRQ_FIRST + 16) /* 16: DMA1 channel 6 global interrupt */ +# define STM32_IRQ_DMA1CH7 (STM32_IRQ_FIRST + 17) /* 17: DMA1 channel 7 global interrupt */ +# define STM32_IRQ_ADC1 (STM32_IRQ_FIRST + 18) /* 18: ADC1 global interrupt */ +# define STM32_IRQ_USBHP (STM32_IRQ_FIRST + 19) /* 19: USB High Priority interrupts */ +# define STM32_IRQ_USBLP (STM32_IRQ_FIRST + 20) /* 20: USB Low Priority interrupt */ +# define STM32_IRQ_DAC (STM32_IRQ_FIRST + 21) /* 21: DAC interrupt */ +# define STM32_IRQ_COMP (STM32_IRQ_FIRST + 22) /* 22: Comparator wakeup through EXTI interrupt, or */ +# define STM32_IRQ_CA (STM32_IRQ_FIRST + 22) /* 22: Channel acquisition interrupt */ +# define STM32_IRQ_EXTI95 (STM32_IRQ_FIRST + 23) /* 23: EXTI Line[9:5] interrupts */ +# define STM32_IRQ_LDC (STM32_IRQ_FIRST + 24) /* 24: LCD global interrupt */ +# define STM32_IRQ_TIM9 (STM32_IRQ_FIRST + 25) /* 25: TIM9 global interrupt */ +# define STM32_IRQ_TIM10 (STM32_IRQ_FIRST + 26) /* 26: TIM10 global interrupt */ +# define STM32_IRQ_TIM11 (STM32_IRQ_FIRST + 27) /* 27: TIM11 global interrupt */ +# define STM32_IRQ_TIM2 (STM32_IRQ_FIRST + 28) /* 28: TIM2 global interrupt */ +# define STM32_IRQ_TIM3 (STM32_IRQ_FIRST + 29) /* 29: TIM3 global interrupt */ +# define STM32_IRQ_TIM4 (STM32_IRQ_FIRST + 30) /* 30: TIM4 global interrupt */ +# define STM32_IRQ_I2C1EV (STM32_IRQ_FIRST + 31) /* 31: I2C1 event interrupt */ +# define STM32_IRQ_I2C1ER (STM32_IRQ_FIRST + 32) /* 32: I2C1 error interrupt */ +# define STM32_IRQ_I2C2EV (STM32_IRQ_FIRST + 33) /* 33: I2C2 event interrupt */ +# define STM32_IRQ_I2C2ER (STM32_IRQ_FIRST + 34) /* 34: I2C2 error interrupt */ +# define STM32_IRQ_SPI1 (STM32_IRQ_FIRST + 35) /* 35: SPI1 global interrupt */ +# define STM32_IRQ_SPI2 (STM32_IRQ_FIRST + 36) /* 36: SPI2 global interrupt */ +# define STM32_IRQ_USART1 (STM32_IRQ_FIRST + 37) /* 37: USART1 global interrupt */ +# define STM32_IRQ_USART2 (STM32_IRQ_FIRST + 38) /* 38: USART2 global interrupt */ +# define STM32_IRQ_USART3 (STM32_IRQ_FIRST + 39) /* 39: USART3 global interrupt */ +# define STM32_IRQ_EXTI1510 (STM32_IRQ_FIRST + 40) /* 40: EXTI Line[15:10] interrupts */ +# define STM32_IRQ_RTCALRM (STM32_IRQ_FIRST + 41) /* 41: RTC alarm through EXTI line interrupt */ +# define STM32_IRQ_USBWKUP (STM32_IRQ_FIRST + 42) /* 42: USB wakeup from suspend through EXTI line interrupt */ +# define STM32_IRQ_TIM6 (STM32_IRQ_FIRST + 43) /* 43: TIM6 global interrupt */ +# define STM32_IRQ_TIM7 (STM32_IRQ_FIRST + 44) /* 44: TIM7 global interrupt */ +# define STM32_IRQ_SDIO (STM32_IRQ_FIRST + 45) /* 45: SDIO Global interrupt */ +# define STM32_IRQ_TIM5 (STM32_IRQ_FIRST + 46) /* 46: TIM5 global interrupt */ +# define STM32_IRQ_SPI3 (STM32_IRQ_FIRST + 47) /* 47: SPI3 global interrupt */ +# define STM32_IRQ_UART4 (STM32_IRQ_FIRST + 48) /* 48: UART4 global interrupt */ +# define STM32_IRQ_UART5 (STM32_IRQ_FIRST + 49) /* 49: UART5 global interrupt */ +# define STM32_IRQ_DMA2CH1 (STM32_IRQ_FIRST + 50) /* 50: DMA2 channel 1 global interrupt */ +# define STM32_IRQ_DMA2CH2 (STM32_IRQ_FIRST + 51) /* 51: DMA2 channel 2 global interrupt */ +# define STM32_IRQ_DMA2CH3 (STM32_IRQ_FIRST + 52) /* 52: DMA2 channel 3 global interrupt */ +# define STM32_IRQ_DMA2CH4 (STM32_IRQ_FIRST + 53) /* 53: DMA2 channel 4 global interrupt */ +# define STM32_IRQ_DMA2CH5 (STM32_IRQ_FIRST + 54) /* 54: DMA2 channel 5 global interrupt */ +# define STM32_IRQ_AES (STM32_IRQ_FIRST + 55) /* 55: AES global interrupt */ +# define STM32_IRQ_COMPACQ (STM32_IRQ_FIRST + 56) /* 56: Comparator Channel Acquisition Interrupt */ + +# define STM32_IRQ_NEXTINTS (57) +#else +# error "Unknown STM32L density" +#endif + +# define NR_IRQS (STM32_IRQ_FIRST + STM32_IRQ_NEXTINTS) + +#endif /* __ARCH_ARM_INCLUDE_STM32L1_IRQ_H */ diff --git a/arch/arm/include/stm32l4/chip.h b/arch/arm/include/stm32l4/chip.h index febd84d6fac0e..f8d06093bad42 100644 --- a/arch/arm/include/stm32l4/chip.h +++ b/arch/arm/include/stm32l4/chip.h @@ -61,266 +61,266 @@ * Parts STM32L4x6xE have 512Kb of FLASH * Parts STM32L4x6xG have 1024Kb of FLASH * - * The correct FLASH size must be set with a CONFIG_STM32L4_FLASH_CONFIG_* + * The correct FLASH size must be set with a CONFIG_STM32_FLASH_CONFIG_* * selection. */ -#if defined(CONFIG_STM32L4_STM32L4XR) -# define STM32L4_SRAM1_SIZE (192*1024) /* 192Kb SRAM1 on AHB bus Matrix */ -# define STM32L4_SRAM2_SIZE (64*1024) /* 64Kb SRAM2 on AHB bus Matrix */ -# define STM32L4_SRAM3_SIZE (384*1024) /* 384Kb SRAM3 on AHB bus Matrix */ -#elif defined(CONFIG_STM32L4_STM32L496XX) -# define STM32L4_SRAM1_SIZE (256*1024) /* 256Kb SRAM1 on AHB bus Matrix */ -# define STM32L4_SRAM2_SIZE (64*1024) /* 64Kb SRAM2 on AHB bus Matrix */ -#elif defined(CONFIG_STM32L4_STM32L475XX) || defined(CONFIG_STM32L4_STM32L476XX) || \ - defined(CONFIG_STM32L4_STM32L486XX) -# define STM32L4_SRAM1_SIZE (96*1024) /* 96Kb SRAM1 on AHB bus Matrix */ -# define STM32L4_SRAM2_SIZE (32*1024) /* 32Kb SRAM2 on AHB bus Matrix */ -#elif defined(CONFIG_STM32L4_STM32L451XX) || defined(CONFIG_STM32L4_STM32L452XX) || \ - defined(CONFIG_STM32L4_STM32L462XX) -# define STM32L4_SRAM1_SIZE (128*1024) /* 128Kb SRAM1 on AHB bus Matrix */ -# define STM32L4_SRAM2_SIZE (32*1024) /* 32Kb SRAM2 on AHB bus Matrix */ -#elif defined(CONFIG_STM32L4_STM32L432XX) || defined(CONFIG_STM32L4_STM32L433XX) -# define STM32L4_SRAM1_SIZE (48*1024) /* 48Kb SRAM1 on AHB bus Matrix */ -# define STM32L4_SRAM2_SIZE (16*1024) /* 16Kb SRAM2 on AHB bus Matrix */ -#elif defined(CONFIG_STM32L4_STM32L412XX) || defined(CONFIG_STM32L4_STM32L422XX) -# define STM32L4_SRAM1_SIZE (32*1024) /* 32Kb SRAM1 on AHB bus Matrix */ -# define STM32L4_SRAM2_SIZE (8*1024) /* 8Kb SRAM2 on AHB bus Matrix */ +#if defined(CONFIG_STM32_STM32L4XR) +# define STM32_SRAM1_SIZE (192*1024) /* 192Kb SRAM1 on AHB bus Matrix */ +# define STM32_SRAM2_SIZE (64*1024) /* 64Kb SRAM2 on AHB bus Matrix */ +# define STM32_SRAM3_SIZE (384*1024) /* 384Kb SRAM3 on AHB bus Matrix */ +#elif defined(CONFIG_STM32_STM32L496XX) +# define STM32_SRAM1_SIZE (256*1024) /* 256Kb SRAM1 on AHB bus Matrix */ +# define STM32_SRAM2_SIZE (64*1024) /* 64Kb SRAM2 on AHB bus Matrix */ +#elif defined(CONFIG_STM32_STM32L475XX) || defined(CONFIG_STM32_STM32L476XX) || \ + defined(CONFIG_STM32_STM32L486XX) +# define STM32_SRAM1_SIZE (96*1024) /* 96Kb SRAM1 on AHB bus Matrix */ +# define STM32_SRAM2_SIZE (32*1024) /* 32Kb SRAM2 on AHB bus Matrix */ +#elif defined(CONFIG_STM32_STM32L451XX) || defined(CONFIG_STM32_STM32L452XX) || \ + defined(CONFIG_STM32_STM32L462XX) +# define STM32_SRAM1_SIZE (128*1024) /* 128Kb SRAM1 on AHB bus Matrix */ +# define STM32_SRAM2_SIZE (32*1024) /* 32Kb SRAM2 on AHB bus Matrix */ +#elif defined(CONFIG_STM32_STM32L432XX) || defined(CONFIG_STM32_STM32L433XX) +# define STM32_SRAM1_SIZE (48*1024) /* 48Kb SRAM1 on AHB bus Matrix */ +# define STM32_SRAM2_SIZE (16*1024) /* 16Kb SRAM2 on AHB bus Matrix */ +#elif defined(CONFIG_STM32_STM32L412XX) || defined(CONFIG_STM32_STM32L422XX) +# define STM32_SRAM1_SIZE (32*1024) /* 32Kb SRAM1 on AHB bus Matrix */ +# define STM32_SRAM2_SIZE (8*1024) /* 8Kb SRAM2 on AHB bus Matrix */ #else # error "Unsupported STM32L4 chip" #endif -#if defined(CONFIG_STM32L4_STM32L4XR) -# define STM32L4_NFSMC 1 /* Have FSMC memory controller */ -# define STM32L4_NATIM 2 /* Two advanced timers TIM1 and 8 */ -# define STM32L4_NGTIM32 2 /* 32-bit general timers TIM2 and 5 with DMA */ -# define STM32L4_NGTIM16 2 /* 16-bit general timers TIM3 and 4 with DMA */ -# define STM32L4_NGTIMNDMA 3 /* 16-bit general timers TIM15-17 without DMA */ -# define STM32L4_NBTIM 2 /* Two basic timers, TIM6-7 */ -# define STM32L4_NLPTIM 2 /* Two low-power timers, LPTIM1-2 */ -# define STM32L4_NRNG 1 /* Random number generator (RNG) */ -# define STM32L4_NUART 2 /* UART 4-5 */ -# define STM32L4_NUSART 3 /* USART 1-3 */ -# define STM32L4_NLPUART 1 /* LPUART 1 */ -# define STM32L4_QSPI 0 /* No QuadSPI1 */ -# define STM32L4_OCTOSPI 2 /* OCTOSPI1-2 */ -# define STM32L4_NSPI 3 /* SPI1-3 */ -# define STM32L4_NI2C 4 /* I2C1-4 */ -# define STM32L4_NSWPMI 0 /* No SWPMI1 */ -# define STM32L4_NUSBOTGFS 1 /* USB OTG FS */ -# define STM32L4_NUSBFS 0 /* No USB FS */ -# define STM32L4_NCAN 1 /* CAN1 */ -# define STM32L4_NSAI 2 /* SAI1-2 */ -# define STM32L4_NSDMMC 1 /* SDMMC interface */ -# define STM32L4_NDMA 2 /* DMA1-2 */ -# define STM32L4_NPORTS 9 /* 9 GPIO ports, GPIOA-I */ -# define STM32L4_NADC 1 /* 12-bit ADC1, up to 20 channels */ -# define STM32L4_NDAC 2 /* 12-bit DAC1-2 */ -# define STM32L4_NCRC 1 /* CRC */ -# define STM32L4_NCOMP 2 /* Comparators */ -# define STM32L4_NOPAMP 2 /* Operational Amplifiers */ -#endif /* CONFIG_STM32L4_STM32L4XR */ +#if defined(CONFIG_STM32_STM32L4XR) +# define STM32_NFSMC 1 /* Have FSMC memory controller */ +# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ +# define STM32_NGTIM32 2 /* 32-bit general timers TIM2 and 5 with DMA */ +# define STM32_NGTIM16 2 /* 16-bit general timers TIM3 and 4 with DMA */ +# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM15-17 without DMA */ +# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ +# define STM32_NLPTIM 2 /* Two low-power timers, LPTIM1-2 */ +# define STM32_NRNG 1 /* Random number generator (RNG) */ +# define STM32_NUART 2 /* UART 4-5 */ +# define STM32_NUSART 3 /* USART 1-3 */ +# define STM32_NLPUART 1 /* LPUART 1 */ +# define STM32_QSPI 0 /* No QuadSPI1 */ +# define STM32_OCTOSPI 2 /* OCTOSPI1-2 */ +# define STM32_NSPI 3 /* SPI1-3 */ +# define STM32_NI2C 4 /* I2C1-4 */ +# define STM32_NSWPMI 0 /* No SWPMI1 */ +# define STM32_NUSBOTGFS 1 /* USB OTG FS */ +# define STM32_NUSBFS 0 /* No USB FS */ +# define STM32_NCAN 1 /* CAN1 */ +# define STM32_NSAI 2 /* SAI1-2 */ +# define STM32_NSDMMC 1 /* SDMMC interface */ +# define STM32_NDMA 2 /* DMA1-2 */ +# define STM32_NPORTS 9 /* 9 GPIO ports, GPIOA-I */ +# define STM32_NADC 1 /* 12-bit ADC1, up to 20 channels */ +# define STM32_NDAC 2 /* 12-bit DAC1-2 */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NCOMP 2 /* Comparators */ +# define STM32_NOPAMP 2 /* Operational Amplifiers */ +#endif /* CONFIG_STM32_STM32L4XR */ -#if defined(CONFIG_STM32L4_STM32L4X5) -# define STM32L4_NFSMC 1 /* Have FSMC memory controller */ -# define STM32L4_NATIM 2 /* Two advanced timers TIM1 and 8 */ -# define STM32L4_NGTIM32 2 /* 32-bit general timers TIM2 and 5 with DMA */ -# define STM32L4_NGTIM16 2 /* 16-bit general timers TIM3 and 4 with DMA */ -# define STM32L4_NGTIMNDMA 3 /* 16-bit general timers TIM15-17 without DMA */ -# define STM32L4_NBTIM 2 /* Two basic timers, TIM6-7 */ -# define STM32L4_NLPTIM 2 /* Two low-power timers, LPTIM1-2 */ -# define STM32L4_NRNG 1 /* Random number generator (RNG) */ -# define STM32L4_NUART 2 /* UART 4-5 */ -# define STM32L4_NUSART 3 /* USART 1-3 */ -# define STM32L4_NLPUART 1 /* LPUART 1 */ -# define STM32L4_QSPI 1 /* QuadSPI1 */ -# define STM32L4_NSPI 3 /* SPI1-3 */ -# define STM32L4_NI2C 3 /* I2C1-3 */ -# define STM32L4_NSWPMI 1 /* SWPMI1 */ -# define STM32L4_NUSBOTGFS 1 /* USB OTG FS */ -# define STM32L4_NUSBFS 0 /* No USB FS */ -# define STM32L4_NCAN 1 /* CAN1 */ -# define STM32L4_NSAI 2 /* SAI1-2 */ -# define STM32L4_NSDMMC 1 /* SDMMC interface */ -# define STM32L4_NDMA 2 /* DMA1-2 */ -# define STM32L4_NPORTS 8 /* 8 GPIO ports, GPIOA-H */ -# define STM32L4_NADC 3 /* 12-bit ADC1-3, 16 channels */ -# define STM32L4_NDAC 2 /* 12-bit DAC1-2 */ -# define STM32L4_NCRC 1 /* CRC */ -# define STM32L4_NCOMP 2 /* Comparators */ -# define STM32L4_NOPAMP 2 /* Operational Amplifiers */ -#endif /* CONFIG_STM32L4_STM32L4X5 */ +#if defined(CONFIG_STM32_STM32L4X5) +# define STM32_NFSMC 1 /* Have FSMC memory controller */ +# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ +# define STM32_NGTIM32 2 /* 32-bit general timers TIM2 and 5 with DMA */ +# define STM32_NGTIM16 2 /* 16-bit general timers TIM3 and 4 with DMA */ +# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM15-17 without DMA */ +# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ +# define STM32_NLPTIM 2 /* Two low-power timers, LPTIM1-2 */ +# define STM32_NRNG 1 /* Random number generator (RNG) */ +# define STM32_NUART 2 /* UART 4-5 */ +# define STM32_NUSART 3 /* USART 1-3 */ +# define STM32_NLPUART 1 /* LPUART 1 */ +# define STM32_QSPI 1 /* QuadSPI1 */ +# define STM32_NSPI 3 /* SPI1-3 */ +# define STM32_NI2C 3 /* I2C1-3 */ +# define STM32_NSWPMI 1 /* SWPMI1 */ +# define STM32_NUSBOTGFS 1 /* USB OTG FS */ +# define STM32_NUSBFS 0 /* No USB FS */ +# define STM32_NCAN 1 /* CAN1 */ +# define STM32_NSAI 2 /* SAI1-2 */ +# define STM32_NSDMMC 1 /* SDMMC interface */ +# define STM32_NDMA 2 /* DMA1-2 */ +# define STM32_NPORTS 8 /* 8 GPIO ports, GPIOA-H */ +# define STM32_NADC 3 /* 12-bit ADC1-3, 16 channels */ +# define STM32_NDAC 2 /* 12-bit DAC1-2 */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NCOMP 2 /* Comparators */ +# define STM32_NOPAMP 2 /* Operational Amplifiers */ +#endif /* CONFIG_STM32_STM32L4X5 */ -#if defined(CONFIG_STM32L4_STM32L4X6) -# define STM32L4_NFSMC 1 /* Have FSMC memory controller */ -# define STM32L4_NATIM 2 /* Two advanced timers TIM1 and 8 */ -# define STM32L4_NGTIM32 2 /* 32-bit general timers TIM2 and 5 with DMA */ -# define STM32L4_NGTIM16 2 /* 16-bit general timers TIM3 and 4 with DMA */ -# define STM32L4_NGTIMNDMA 3 /* 16-bit general timers TIM15-17 without DMA */ -# define STM32L4_NBTIM 2 /* Two basic timers, TIM6-7 */ -# define STM32L4_NLPTIM 2 /* Two low-power timers, LPTIM1-2 */ -# define STM32L4_NRNG 1 /* Random number generator (RNG) */ -# define STM32L4_NUART 2 /* UART 4-5 */ -# define STM32L4_NUSART 3 /* USART 1-3 */ -# define STM32L4_NLPUART 1 /* LPUART 1 */ -# define STM32L4_QSPI 1 /* QuadSPI1 */ -# define STM32L4_NSPI 3 /* SPI1-3 */ -#if defined(CONFIG_STM32L4_STM32L496XX) -# define STM32L4_NI2C 4 /* I2C1-4 */ +#if defined(CONFIG_STM32_STM32L4X6) +# define STM32_NFSMC 1 /* Have FSMC memory controller */ +# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ +# define STM32_NGTIM32 2 /* 32-bit general timers TIM2 and 5 with DMA */ +# define STM32_NGTIM16 2 /* 16-bit general timers TIM3 and 4 with DMA */ +# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM15-17 without DMA */ +# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ +# define STM32_NLPTIM 2 /* Two low-power timers, LPTIM1-2 */ +# define STM32_NRNG 1 /* Random number generator (RNG) */ +# define STM32_NUART 2 /* UART 4-5 */ +# define STM32_NUSART 3 /* USART 1-3 */ +# define STM32_NLPUART 1 /* LPUART 1 */ +# define STM32_QSPI 1 /* QuadSPI1 */ +# define STM32_NSPI 3 /* SPI1-3 */ +#if defined(CONFIG_STM32_STM32L496XX) +# define STM32_NI2C 4 /* I2C1-4 */ #else -# define STM32L4_NI2C 3 /* I2C1-3 */ +# define STM32_NI2C 3 /* I2C1-3 */ #endif -# define STM32L4_NSWPMI 1 /* SWPMI1 */ -# define STM32L4_NUSBOTGFS 1 /* USB OTG FS */ -# define STM32L4_NUSBFS 0 /* No USB FS */ -#if defined(CONFIG_STM32L4_STM32L496XX) -# define STM32L4_NCAN 2 /* CAN1-2 */ +# define STM32_NSWPMI 1 /* SWPMI1 */ +# define STM32_NUSBOTGFS 1 /* USB OTG FS */ +# define STM32_NUSBFS 0 /* No USB FS */ +#if defined(CONFIG_STM32_STM32L496XX) +# define STM32_NCAN 2 /* CAN1-2 */ #else -# define STM32L4_NCAN 1 /* CAN1 */ +# define STM32_NCAN 1 /* CAN1 */ #endif -# define STM32L4_NSAI 2 /* SAI1-2 */ -# define STM32L4_NSDMMC 1 /* SDMMC interface */ -# define STM32L4_NDMA 2 /* DMA1-2 */ -#if defined(CONFIG_STM32L4_STM32L496XX) -# define STM32L4_NPORTS 9 /* 9 GPIO ports, GPIOA-I */ +# define STM32_NSAI 2 /* SAI1-2 */ +# define STM32_NSDMMC 1 /* SDMMC interface */ +# define STM32_NDMA 2 /* DMA1-2 */ +#if defined(CONFIG_STM32_STM32L496XX) +# define STM32_NPORTS 9 /* 9 GPIO ports, GPIOA-I */ #else -# define STM32L4_NPORTS 8 /* 8 GPIO ports, GPIOA-H */ +# define STM32_NPORTS 8 /* 8 GPIO ports, GPIOA-H */ #endif -# define STM32L4_NADC 3 /* 12-bit ADC1-3, up to 24 channels */ -# define STM32L4_NDAC 2 /* 12-bit DAC1-2 */ -# define STM32L4_NCRC 1 /* CRC */ -# define STM32L4_NCOMP 2 /* Comparators */ -# define STM32L4_NOPAMP 2 /* Operational Amplifiers */ -#endif /* CONFIG_STM32L4_STM32L4X6 */ +# define STM32_NADC 3 /* 12-bit ADC1-3, up to 24 channels */ +# define STM32_NDAC 2 /* 12-bit DAC1-2 */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NCOMP 2 /* Comparators */ +# define STM32_NOPAMP 2 /* Operational Amplifiers */ +#endif /* CONFIG_STM32_STM32L4X6 */ -#if defined(CONFIG_STM32L4_STM32L451XX) || defined(CONFIG_STM32L4_STM32L452XX) || \ - defined(CONFIG_STM32L4_STM32L462XX) -# define STM32L4_NFSMC 0 /* No FSMC memory controller */ -# define STM32L4_NATIM 1 /* One advanced timer TIM1 */ -# define STM32L4_NGTIM32 1 /* 32-bit general timer TIM2 with DMA */ -# define STM32L4_NGTIM16 3 /* 16-bit general timers TIM3, TIM15-16 with DMA */ -# define STM32L4_NGTIMNDMA 0 /* No 16-bit general timers without DMA */ -# define STM32L4_NBTIM 1 /* One basic timer, TIM6 */ -# define STM32L4_NLPTIM 2 /* Two low-power timers, LPTIM1-2 */ -# define STM32L4_NRNG 1 /* Random number generator (RNG) */ -# define STM32L4_NUART 1 /* UART 4 */ -# define STM32L4_NUSART 3 /* USART 1-3 */ -# define STM32L4_NLPUART 1 /* LPUART 1 */ -# define STM32L4_QSPI 1 /* QuadSPI1 */ -# define STM32L4_NSPI 3 /* SPI1-3 */ -# define STM32L4_NI2C 4 /* I2C1-4 */ -# define STM32L4_NSWPMI 1 /* SWPMI1 */ -# define STM32L4_NUSBOTGFS 0 /* No USB OTG FS */ -#if defined(CONFIG_STM32L4_STM32L451XX) -# define STM32L4_NUSBFS 0 /* No USB FS */ +#if defined(CONFIG_STM32_STM32L451XX) || defined(CONFIG_STM32_STM32L452XX) || \ + defined(CONFIG_STM32_STM32L462XX) +# define STM32_NFSMC 0 /* No FSMC memory controller */ +# define STM32_NATIM 1 /* One advanced timer TIM1 */ +# define STM32_NGTIM32 1 /* 32-bit general timer TIM2 with DMA */ +# define STM32_NGTIM16 3 /* 16-bit general timers TIM3, TIM15-16 with DMA */ +# define STM32_NGTIMNDMA 0 /* No 16-bit general timers without DMA */ +# define STM32_NBTIM 1 /* One basic timer, TIM6 */ +# define STM32_NLPTIM 2 /* Two low-power timers, LPTIM1-2 */ +# define STM32_NRNG 1 /* Random number generator (RNG) */ +# define STM32_NUART 1 /* UART 4 */ +# define STM32_NUSART 3 /* USART 1-3 */ +# define STM32_NLPUART 1 /* LPUART 1 */ +# define STM32_QSPI 1 /* QuadSPI1 */ +# define STM32_NSPI 3 /* SPI1-3 */ +# define STM32_NI2C 4 /* I2C1-4 */ +# define STM32_NSWPMI 1 /* SWPMI1 */ +# define STM32_NUSBOTGFS 0 /* No USB OTG FS */ +#if defined(CONFIG_STM32_STM32L451XX) +# define STM32_NUSBFS 0 /* No USB FS */ #else -# define STM32L4_NUSBFS 1 /* USB FS */ +# define STM32_NUSBFS 1 /* USB FS */ #endif -# define STM32L4_NCAN 1 /* CAN1 */ -# define STM32L4_NSAI 1 /* SAI1 */ -#if defined(CONFIG_STM32L4_HAVE_SDMMC1) -# define STM32L4_NSDMMC 1 /* SDMMC interface */ +# define STM32_NCAN 1 /* CAN1 */ +# define STM32_NSAI 1 /* SAI1 */ +#if defined(CONFIG_STM32_HAVE_SDMMC1) +# define STM32_NSDMMC 1 /* SDMMC interface */ #else -# define STM32L4_NSDMMC 0 /* No SDMMC interface */ +# define STM32_NSDMMC 0 /* No SDMMC interface */ #endif -# define STM32L4_NDMA 2 /* DMA1-2 */ -# define STM32L4_NPORTS 8 /* 8 GPIO ports, GPIOA-H */ -# define STM32L4_NADC 1 /* 12-bit ADC1, 16 channels (10 in CE,CV) */ -# define STM32L4_NDAC 1 /* 12-bit DAC1 */ -# define STM32L4_NCRC 1 /* CRC */ -# define STM32L4_NCOMP 2 /* Comparators */ -# define STM32L4_NOPAMP 1 /* Operational Amplifiers */ -#endif /* CONFIG_STM32L4_STM32L451XX */ +# define STM32_NDMA 2 /* DMA1-2 */ +# define STM32_NPORTS 8 /* 8 GPIO ports, GPIOA-H */ +# define STM32_NADC 1 /* 12-bit ADC1, 16 channels (10 in CE,CV) */ +# define STM32_NDAC 1 /* 12-bit DAC1 */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NCOMP 2 /* Comparators */ +# define STM32_NOPAMP 1 /* Operational Amplifiers */ +#endif /* CONFIG_STM32_STM32L451XX */ -#if defined(CONFIG_STM32L4_STM32L432XX) -# define STM32L4_NFSMC 0 /* No FSMC memory controller */ -# define STM32L4_NATIM 1 /* One advanced timer TIM1 */ -# define STM32L4_NGTIM32 1 /* 32-bit general timer TIM2 with DMA */ -# define STM32L4_NGTIM16 2 /* 16-bit general timers TIM15-16 with DMA */ -# define STM32L4_NGTIMNDMA 0 /* No 16-bit general timers without DMA */ -# define STM32L4_NBTIM 2 /* Two basic timers, TIM6-7 */ -# define STM32L4_NLPTIM 2 /* Two low-power timers, LPTIM1-2 */ -# define STM32L4_NRNG 1 /* Random number generator (RNG) */ -# define STM32L4_NUART 0 /* No UART */ -# define STM32L4_NUSART 2 /* USART 1-2 */ -# define STM32L4_NLPUART 1 /* LPUART 1 */ -# define STM32L4_QSPI 1 /* QuadSPI1 */ -# define STM32L4_NSPI 2 /* SPI1, SPI3 */ -# define STM32L4_NI2C 2 /* I2C1, I2C3 */ -# define STM32L4_NSWPMI 1 /* SWPMI1 */ -# define STM32L4_NUSBOTGFS 0 /* No USB OTG FS */ -# define STM32L4_NUSBFS 1 /* USB FS */ -# define STM32L4_NCAN 1 /* CAN1 */ -# define STM32L4_NSAI 1 /* SAI1 */ -# define STM32L4_NSDMMC 0 /* No SDMMC interface */ -# define STM32L4_NDMA 2 /* DMA1-2 */ -# define STM32L4_NPORTS 8 /* 8 GPIO ports, GPIOA-H */ -# define STM32L4_NADC 1 /* 12-bit ADC1, 10 channels */ -# define STM32L4_NDAC 2 /* 12-bit DAC1-2 */ -# define STM32L4_NCRC 1 /* CRC */ -# define STM32L4_NCOMP 2 /* Comparators */ -# define STM32L4_NOPAMP 1 /* Operational Amplifiers */ -#endif /* CONFIG_STM32L4_STM32L432XX */ +#if defined(CONFIG_STM32_STM32L432XX) +# define STM32_NFSMC 0 /* No FSMC memory controller */ +# define STM32_NATIM 1 /* One advanced timer TIM1 */ +# define STM32_NGTIM32 1 /* 32-bit general timer TIM2 with DMA */ +# define STM32_NGTIM16 2 /* 16-bit general timers TIM15-16 with DMA */ +# define STM32_NGTIMNDMA 0 /* No 16-bit general timers without DMA */ +# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ +# define STM32_NLPTIM 2 /* Two low-power timers, LPTIM1-2 */ +# define STM32_NRNG 1 /* Random number generator (RNG) */ +# define STM32_NUART 0 /* No UART */ +# define STM32_NUSART 2 /* USART 1-2 */ +# define STM32_NLPUART 1 /* LPUART 1 */ +# define STM32_QSPI 1 /* QuadSPI1 */ +# define STM32_NSPI 2 /* SPI1, SPI3 */ +# define STM32_NI2C 2 /* I2C1, I2C3 */ +# define STM32_NSWPMI 1 /* SWPMI1 */ +# define STM32_NUSBOTGFS 0 /* No USB OTG FS */ +# define STM32_NUSBFS 1 /* USB FS */ +# define STM32_NCAN 1 /* CAN1 */ +# define STM32_NSAI 1 /* SAI1 */ +# define STM32_NSDMMC 0 /* No SDMMC interface */ +# define STM32_NDMA 2 /* DMA1-2 */ +# define STM32_NPORTS 8 /* 8 GPIO ports, GPIOA-H */ +# define STM32_NADC 1 /* 12-bit ADC1, 10 channels */ +# define STM32_NDAC 2 /* 12-bit DAC1-2 */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NCOMP 2 /* Comparators */ +# define STM32_NOPAMP 1 /* Operational Amplifiers */ +#endif /* CONFIG_STM32_STM32L432XX */ -#if defined(CONFIG_STM32L4_STM32L433XX) -# define STM32L4_NFSMC 0 /* No FSMC memory controller */ -# define STM32L4_NATIM 1 /* One advanced timer TIM1 */ -# define STM32L4_NGTIM32 1 /* 32-bit general timer TIM2 with DMA */ -# define STM32L4_NGTIM16 2 /* 16-bit general timers TIM15-16 with DMA */ -# define STM32L4_NGTIMNDMA 0 /* No 16-bit general timers without DMA */ -# define STM32L4_NBTIM 2 /* Two basic timers, TIM6-7 */ -# define STM32L4_NLPTIM 2 /* Two low-power timers, LPTIM1-2 */ -# define STM32L4_NRNG 1 /* Random number generator (RNG) */ -# define STM32L4_NUART 0 /* No UART */ -# define STM32L4_NUSART 3 /* USART 1-3 */ -# define STM32L4_NLPUART 1 /* LPUART 1 */ -# define STM32L4_QSPI 1 /* QuadSPI1 */ -# define STM32L4_NSPI 3 /* SPI1-SPI3 */ -# define STM32L4_NI2C 3 /* I2C1-I2C3 */ -# define STM32L4_NSWPMI 1 /* SWPMI1 */ -# define STM32L4_NUSBOTGFS 0 /* No USB OTG FS */ -# define STM32L4_NUSBFS 1 /* USB FS */ -# define STM32L4_NCAN 1 /* CAN1 */ -# define STM32L4_NSAI 1 /* SAI1 */ -# define STM32L4_NSDMMC 1 /* SDMMC interface */ -# define STM32L4_NDMA 2 /* DMA1-2 */ -# define STM32L4_NPORTS 8 /* 8 GPIO ports, GPIOA-H */ -# define STM32L4_NADC 1 /* 12-bit ADC1, 10 channels */ -# define STM32L4_NDAC 2 /* 12-bit DAC1-2 */ -# define STM32L4_NCRC 1 /* CRC */ -# define STM32L4_NCOMP 2 /* Comparators */ -# define STM32L4_NOPAMP 1 /* Operational Amplifiers */ -#endif /* CONFIG_STM32L4_STM32L433XX */ +#if defined(CONFIG_STM32_STM32L433XX) +# define STM32_NFSMC 0 /* No FSMC memory controller */ +# define STM32_NATIM 1 /* One advanced timer TIM1 */ +# define STM32_NGTIM32 1 /* 32-bit general timer TIM2 with DMA */ +# define STM32_NGTIM16 2 /* 16-bit general timers TIM15-16 with DMA */ +# define STM32_NGTIMNDMA 0 /* No 16-bit general timers without DMA */ +# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ +# define STM32_NLPTIM 2 /* Two low-power timers, LPTIM1-2 */ +# define STM32_NRNG 1 /* Random number generator (RNG) */ +# define STM32_NUART 0 /* No UART */ +# define STM32_NUSART 3 /* USART 1-3 */ +# define STM32_NLPUART 1 /* LPUART 1 */ +# define STM32_QSPI 1 /* QuadSPI1 */ +# define STM32_NSPI 3 /* SPI1-SPI3 */ +# define STM32_NI2C 3 /* I2C1-I2C3 */ +# define STM32_NSWPMI 1 /* SWPMI1 */ +# define STM32_NUSBOTGFS 0 /* No USB OTG FS */ +# define STM32_NUSBFS 1 /* USB FS */ +# define STM32_NCAN 1 /* CAN1 */ +# define STM32_NSAI 1 /* SAI1 */ +# define STM32_NSDMMC 1 /* SDMMC interface */ +# define STM32_NDMA 2 /* DMA1-2 */ +# define STM32_NPORTS 8 /* 8 GPIO ports, GPIOA-H */ +# define STM32_NADC 1 /* 12-bit ADC1, 10 channels */ +# define STM32_NDAC 2 /* 12-bit DAC1-2 */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NCOMP 2 /* Comparators */ +# define STM32_NOPAMP 1 /* Operational Amplifiers */ +#endif /* CONFIG_STM32_STM32L433XX */ -#if defined(CONFIG_STM32L4_STM32L412XX) || defined(CONFIG_STM32L4_STM32L422XX) -# define STM32L4_NFSMC 0 /* No FSMC memory controller */ -# define STM32L4_NATIM 1 /* One advanced timer TIM1 */ -# define STM32L4_NGTIM32 1 /* 32-bit general timer TIM2 with DMA */ -# define STM32L4_NGTIM16 2 /* 16-bit general timers TIM15-16 with DMA */ -# define STM32L4_NGTIMNDMA 0 /* No 16-bit general timers without DMA */ -# define STM32L4_NBTIM 1 /* One basic timer, TIM6 */ -# define STM32L4_NLPTIM 2 /* Two low-power timers, LPTIM1-2 */ -# define STM32L4_NRNG 1 /* Random number generator (RNG) */ -# define STM32L4_NUART 0 /* No UART */ -# define STM32L4_NUSART 3 /* USART 1-3 */ -# define STM32L4_NLPUART 1 /* LPUART 1 */ -# define STM32L4_QSPI 1 /* QuadSPI1 */ -# define STM32L4_NSPI 3 /* SPI1-SPI3 */ -# define STM32L4_NI2C 3 /* I2C1-I2C3 */ -# define STM32L4_NSWPMI 0 /* No SWPMI */ -# define STM32L4_NUSBOTGFS 0 /* No USB OTG FS */ -# define STM32L4_NUSBFS 1 /* USB FS */ -# define STM32L4_NCAN 0 /* No CAN */ -# define STM32L4_NSAI 0 /* No SAI */ -# define STM32L4_NSDMMC 0 /* No SDMMC interface */ -# define STM32L4_NDMA 2 /* DMA1-2 */ -# define STM32L4_NPORTS 8 /* 8 GPIO ports, GPIOA-H */ -# define STM32L4_NADC 2 /* 12-bit ADC1-2, 10 channels */ -# define STM32L4_NDAC 0 /* No DAC */ -# define STM32L4_NCRC 1 /* CRC */ -# define STM32L4_NCOMP 2 /* Comparators */ -# define STM32L4_NOPAMP 1 /* Operational Amplifiers */ -#endif /* CONFIG_STM32L4_STM32L412XX || CONFIG_STM32L4_STM32L422XX */ +#if defined(CONFIG_STM32_STM32L412XX) || defined(CONFIG_STM32_STM32L422XX) +# define STM32_NFSMC 0 /* No FSMC memory controller */ +# define STM32_NATIM 1 /* One advanced timer TIM1 */ +# define STM32_NGTIM32 1 /* 32-bit general timer TIM2 with DMA */ +# define STM32_NGTIM16 2 /* 16-bit general timers TIM15-16 with DMA */ +# define STM32_NGTIMNDMA 0 /* No 16-bit general timers without DMA */ +# define STM32_NBTIM 1 /* One basic timer, TIM6 */ +# define STM32_NLPTIM 2 /* Two low-power timers, LPTIM1-2 */ +# define STM32_NRNG 1 /* Random number generator (RNG) */ +# define STM32_NUART 0 /* No UART */ +# define STM32_NUSART 3 /* USART 1-3 */ +# define STM32_NLPUART 1 /* LPUART 1 */ +# define STM32_QSPI 1 /* QuadSPI1 */ +# define STM32_NSPI 3 /* SPI1-SPI3 */ +# define STM32_NI2C 3 /* I2C1-I2C3 */ +# define STM32_NSWPMI 0 /* No SWPMI */ +# define STM32_NUSBOTGFS 0 /* No USB OTG FS */ +# define STM32_NUSBFS 1 /* USB FS */ +# define STM32_NCAN 0 /* No CAN */ +# define STM32_NSAI 0 /* No SAI */ +# define STM32_NSDMMC 0 /* No SDMMC interface */ +# define STM32_NDMA 2 /* DMA1-2 */ +# define STM32_NPORTS 8 /* 8 GPIO ports, GPIOA-H */ +# define STM32_NADC 2 /* 12-bit ADC1-2, 10 channels */ +# define STM32_NDAC 0 /* No DAC */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NCOMP 2 /* Comparators */ +# define STM32_NOPAMP 1 /* Operational Amplifiers */ +#endif /* CONFIG_STM32_STM32L412XX || CONFIG_STM32_STM32L422XX */ /* NVIC priority levels *****************************************************/ diff --git a/arch/arm/include/stm32l4/irq.h b/arch/arm/include/stm32l4/irq.h index a17c156715713..11c1a9a9d1f6b 100644 --- a/arch/arm/include/stm32l4/irq.h +++ b/arch/arm/include/stm32l4/irq.h @@ -44,38 +44,38 @@ /* Processor Exceptions (vectors 0-15) */ -#define STM32L4_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */ - /* Vector 0: Reset stack pointer value */ - /* Vector 1: Reset (not handler as an IRQ) */ -#define STM32L4_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */ -#define STM32L4_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */ -#define STM32L4_IRQ_MEMFAULT (4) /* Vector 4: Memory management (MPU) */ -#define STM32L4_IRQ_BUSFAULT (5) /* Vector 5: Bus fault */ -#define STM32L4_IRQ_USAGEFAULT (6) /* Vector 6: Usage fault */ - /* Vectors 7-10: Reserved */ -#define STM32L4_IRQ_SVCALL (11) /* Vector 11: SVC call */ -#define STM32L4_IRQ_DBGMONITOR (12) /* Vector 12: Debug Monitor */ - /* Vector 13: Reserved */ -#define STM32L4_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */ -#define STM32L4_IRQ_SYSTICK (15) /* Vector 15: System tick */ +#define STM32_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */ + /* Vector 0: Reset stack pointer value */ + /* Vector 1: Reset (not handler as an IRQ) */ +#define STM32_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */ +#define STM32_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */ +#define STM32_IRQ_MEMFAULT (4) /* Vector 4: Memory management (MPU) */ +#define STM32_IRQ_BUSFAULT (5) /* Vector 5: Bus fault */ +#define STM32_IRQ_USAGEFAULT (6) /* Vector 6: Usage fault */ + /* Vectors 7-10: Reserved */ +#define STM32_IRQ_SVCALL (11) /* Vector 11: SVC call */ +#define STM32_IRQ_DBGMONITOR (12) /* Vector 12: Debug Monitor */ + /* Vector 13: Reserved */ +#define STM32_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */ +#define STM32_IRQ_SYSTICK (15) /* Vector 15: System tick */ /* External interrupts (vectors >= 16). These definitions are * chip-specific */ -#define STM32L4_IRQ_FIRST (16) /* Vector number of the first external interrupt */ +#define STM32_IRQ_FIRST (16) /* Vector number of the first external interrupt */ /**************************************************************************** * Included Files ****************************************************************************/ -#if defined(CONFIG_STM32L4_STM32L4X3) +#if defined(CONFIG_STM32_STM32L4X3) # include -#elif defined(CONFIG_STM32L4_STM32L4X5) +#elif defined(CONFIG_STM32_STM32L4X5) # include -#elif defined(CONFIG_STM32L4_STM32L4X6) +#elif defined(CONFIG_STM32_STM32L4X6) # include -#elif defined(CONFIG_STM32L4_STM32L4XR) +#elif defined(CONFIG_STM32_STM32L4XR) # include #else # error "Unsupported STM32 L4 chip" diff --git a/arch/arm/include/stm32l4/stm32l4x3xx_irq.h b/arch/arm/include/stm32l4/stm32l4x3xx_irq.h index 1b3b5b27945ff..e0d1c6bf7d1fa 100644 --- a/arch/arm/include/stm32l4/stm32l4x3xx_irq.h +++ b/arch/arm/include/stm32l4/stm32l4x3xx_irq.h @@ -52,99 +52,99 @@ * */ -#define STM32L4_IRQ_WWDG (STM32L4_IRQ_FIRST + 0) /* 0: Window Watchdog interrupt */ -#define STM32L4_IRQ_PVD (STM32L4_IRQ_FIRST + 1) /* 1: PVD through EXTI Line detection interrupt */ -#define STM32L4_IRQ_TAMPER (STM32L4_IRQ_FIRST + 2) /* 2: Tamper and time stamp interrupts */ -#define STM32L4_IRQ_TIMESTAMP (STM32L4_IRQ_FIRST + 2) /* 2: Tamper and time stamp interrupts */ -#define STM32L4_IRQ_RTC_WKUP (STM32L4_IRQ_FIRST + 3) /* 3: RTC global interrupt */ -#define STM32L4_IRQ_FLASH (STM32L4_IRQ_FIRST + 4) /* 4: Flash global interrupt */ -#define STM32L4_IRQ_RCC (STM32L4_IRQ_FIRST + 5) /* 5: RCC global interrupt */ -#define STM32L4_IRQ_EXTI0 (STM32L4_IRQ_FIRST + 6) /* 6: EXTI Line 0 interrupt */ -#define STM32L4_IRQ_EXTI1 (STM32L4_IRQ_FIRST + 7) /* 7: EXTI Line 1 interrupt */ -#define STM32L4_IRQ_EXTI2 (STM32L4_IRQ_FIRST + 8) /* 8: EXTI Line 2 interrupt */ -#define STM32L4_IRQ_EXTI3 (STM32L4_IRQ_FIRST + 9) /* 9: EXTI Line 3 interrupt */ -#define STM32L4_IRQ_EXTI4 (STM32L4_IRQ_FIRST + 10) /* 10: EXTI Line 4 interrupt */ -#define STM32L4_IRQ_DMA1CH1 (STM32L4_IRQ_FIRST + 11) /* 11: DMA1 Channel 1 global interrupt */ -#define STM32L4_IRQ_DMA1CH2 (STM32L4_IRQ_FIRST + 12) /* 12: DMA1 Channel 2 global interrupt */ -#define STM32L4_IRQ_DMA1CH3 (STM32L4_IRQ_FIRST + 13) /* 13: DMA1 Channel 3 global interrupt */ -#define STM32L4_IRQ_DMA1CH4 (STM32L4_IRQ_FIRST + 14) /* 14: DMA1 Channel 4 global interrupt */ -#define STM32L4_IRQ_DMA1CH5 (STM32L4_IRQ_FIRST + 15) /* 15: DMA1 Channel 5 global interrupt */ -#define STM32L4_IRQ_DMA1CH6 (STM32L4_IRQ_FIRST + 16) /* 16: DMA1 Channel 6 global interrupt */ -#define STM32L4_IRQ_DMA1CH7 (STM32L4_IRQ_FIRST + 17) /* 17: DMA1 Channel 7 global interrupt */ -#define STM32L4_IRQ_ADC1 (STM32L4_IRQ_FIRST + 18) /* 18: ADC1 global interrupt */ -#define STM32L4_IRQ_CAN1TX (STM32L4_IRQ_FIRST + 19) /* 19: CAN1 TX interrupts */ -#define STM32L4_IRQ_CAN1RX0 (STM32L4_IRQ_FIRST + 20) /* 20: CAN1 RX0 interrupts */ -#define STM32L4_IRQ_CAN1RX1 (STM32L4_IRQ_FIRST + 21) /* 21: CAN1 RX1 interrupt */ -#define STM32L4_IRQ_CAN1SCE (STM32L4_IRQ_FIRST + 22) /* 22: CAN1 SCE interrupt */ -#define STM32L4_IRQ_EXTI95 (STM32L4_IRQ_FIRST + 23) /* 23: EXTI Line[9:5] interrupts */ -#define STM32L4_IRQ_TIM1BRK (STM32L4_IRQ_FIRST + 24) /* 24: TIM1 Break interrupt */ -#define STM32L4_IRQ_TIM15 (STM32L4_IRQ_FIRST + 24) /* 24: TIM15 global interrupt */ -#define STM32L4_IRQ_TIM1UP (STM32L4_IRQ_FIRST + 25) /* 25: TIM1 Update interrupt */ -#define STM32L4_IRQ_TIM16 (STM32L4_IRQ_FIRST + 25) /* 25: TIM16 global interrupt */ -#define STM32L4_IRQ_TIM1TRGCOM (STM32L4_IRQ_FIRST + 26) /* 26: TIM1 Trigger and Commutation interrupts */ -#define STM32L4_IRQ_TIM1CC (STM32L4_IRQ_FIRST + 27) /* 27: TIM1 Capture Compare interrupt */ -#define STM32L4_IRQ_TIM2 (STM32L4_IRQ_FIRST + 28) /* 28: TIM2 global interrupt */ -#define STM32L4_IRQ_TIM3 (STM32L4_IRQ_FIRST + 29) /* 29: TIM3 global interrupt */ - /* Reserved 30: TIM4 global interrupt */ -#define STM32L4_IRQ_I2C1EV (STM32L4_IRQ_FIRST + 31) /* 31: I2C1 event interrupt */ -#define STM32L4_IRQ_I2C1ER (STM32L4_IRQ_FIRST + 32) /* 32: I2C1 error interrupt */ -#define STM32L4_IRQ_I2C2EV (STM32L4_IRQ_FIRST + 33) /* 33: I2C2 event interrupt */ -#define STM32L4_IRQ_I2C2ER (STM32L4_IRQ_FIRST + 34) /* 34: I2C2 error interrupt */ -#define STM32L4_IRQ_SPI1 (STM32L4_IRQ_FIRST + 35) /* 35: SPI1 global interrupt */ -#define STM32L4_IRQ_SPI2 (STM32L4_IRQ_FIRST + 36) /* 36: SPI2 global interrupt */ -#define STM32L4_IRQ_USART1 (STM32L4_IRQ_FIRST + 37) /* 37: USART1 global interrupt */ -#define STM32L4_IRQ_USART2 (STM32L4_IRQ_FIRST + 38) /* 38: USART2 global interrupt */ -#define STM32L4_IRQ_USART3 (STM32L4_IRQ_FIRST + 39) /* 39: USART3 global interrupt */ -#define STM32L4_IRQ_EXTI1510 (STM32L4_IRQ_FIRST + 40) /* 40: EXTI Line[15:10] interrupts */ -#define STM32L4_IRQ_RTCALRM (STM32L4_IRQ_FIRST + 41) /* 41: RTC alarm through EXTI line interrupt */ - /* Reserved 42-48 */ -#define STM32L4_IRQ_SDMMC1 (STM32L4_IRQ_FIRST + 49) /* 49: SDMMC1 global interrupt */ - /* Reserved 50: TIM5 global interrupt */ -#define STM32L4_IRQ_SPI3 (STM32L4_IRQ_FIRST + 51) /* 51: SPI3 global interrupt */ -#define STM32L4_IRQ_UART4 (STM32L4_IRQ_FIRST + 52) /* 52: UART4 global interrupt */ - /* Reserved 53: UART5 global interrupt */ -#define STM32L4_IRQ_TIM6 (STM32L4_IRQ_FIRST + 54) /* 54: TIM6 global interrupt */ -#define STM32L4_IRQ_DAC (STM32L4_IRQ_FIRST + 54) /* 54: DAC1 underrun error interrupts */ -#define STM32L4_IRQ_TIM7 (STM32L4_IRQ_FIRST + 55) /* 55: TIM7 global interrupt */ -#define STM32L4_IRQ_DMA2CH1 (STM32L4_IRQ_FIRST + 56) /* 56: DMA2 Channel 1 global interrupt */ -#define STM32L4_IRQ_DMA2CH2 (STM32L4_IRQ_FIRST + 57) /* 57: DMA2 Channel 2 global interrupt */ -#define STM32L4_IRQ_DMA2CH3 (STM32L4_IRQ_FIRST + 58) /* 58: DMA2 Channel 3 global interrupt */ -#define STM32L4_IRQ_DMA2CH4 (STM32L4_IRQ_FIRST + 59) /* 59: DMA2 Channel 4 global interrupt */ -#define STM32L4_IRQ_DMA2CH5 (STM32L4_IRQ_FIRST + 60) /* 60: DMA2 Channel 5 global interrupt */ -#define STM32L4_IRQ_DFSDM0 (STM32L4_IRQ_FIRST + 61) /* 61: DFSDM0 global interrupt */ -#define STM32L4_IRQ_DFSDM1 (STM32L4_IRQ_FIRST + 62) /* 62: DFSDM1 global interrupt*/ - /* Reserved 63: DFSDM2 global interrupt */ -#define STM32L4_IRQ_COMP (STM32L4_IRQ_FIRST + 64) /* 64: COMP1/COMP2 interrupts */ -#define STM32L4_IRQ_LPTIM1 (STM32L4_IRQ_FIRST + 65) /* 65: LPTIM1 global interrupt */ -#define STM32L4_IRQ_LPTIM2 (STM32L4_IRQ_FIRST + 66) /* 66: LPTIM2 global interrupt */ -#define STM32L4_IRQ_USB_FS (STM32L4_IRQ_FIRST + 67) /* 67: USB event interrupt through EXTI line 17 */ -#define STM32L4_IRQ_DMA2CH6 (STM32L4_IRQ_FIRST + 68) /* 68: DMA2 Channel 6 global interrupt */ -#define STM32L4_IRQ_DMA2CH7 (STM32L4_IRQ_FIRST + 69) /* 69: DMA2 Channel 7 global interrupt */ -#define STM32L4_IRQ_LPUART1 (STM32L4_IRQ_FIRST + 70) /* 70: Low power UART 1 global interrupt */ -#define STM32L4_IRQ_QUADSPI (STM32L4_IRQ_FIRST + 71) /* 71: QUADSPI global interrupt */ -#define STM32L4_IRQ_I2C3EV (STM32L4_IRQ_FIRST + 72) /* 72: I2C3 event interrupt */ -#define STM32L4_IRQ_I2C3ER (STM32L4_IRQ_FIRST + 73) /* 73: I2C3 error interrupt */ -#define STM32L4_IRQ_SAI1 (STM32L4_IRQ_FIRST + 74) /* 74: SAI1 global interrupt */ - /* Reserved 75: SAI2 global interrupt */ -#define STM32L4_IRQ_SWPMI1 (STM32L4_IRQ_FIRST + 76) /* 76: SWPMI1 global interrupt */ -#define STM32L4_IRQ_TSC (STM32L4_IRQ_FIRST + 77) /* 77: TSC global interrupt */ -#define STM32L4_IRQ_LCD (STM32L4_IRQ_FIRST + 78) /* 78: LCD global interrupt */ -#define STM32L4_IRQ_AES (STM32L4_IRQ_FIRST + 79) /* 79: AES crypto global interrupt */ -#define STM32L4_IRQ_RNG (STM32L4_IRQ_FIRST + 80) /* 80: RNG global interrupt */ -#define STM32L4_IRQ_FPU (STM32L4_IRQ_FIRST + 81) /* 81: FPU global interrupt */ -#define STM32L4_IRQ_CRS (STM32L4_IRQ_FIRST + 82) /* 82: CRS global interrupt */ -#define STM32L4_IRQ_I2C4EV (STM32L4_IRQ_FIRST + 83) /* 83: I2C4 event interrupt */ -#define STM32L4_IRQ_I2C4ER (STM32L4_IRQ_FIRST + 84) /* 84: I2C4 error interrupt */ - -#if defined(CONFIG_STM32L4_STM32L4X3) -# define STM32L4_IRQ_NEXTINTS 85 +#define STM32_IRQ_WWDG (STM32_IRQ_FIRST + 0) /* 0: Window Watchdog interrupt */ +#define STM32_IRQ_PVD (STM32_IRQ_FIRST + 1) /* 1: PVD through EXTI Line detection interrupt */ +#define STM32_IRQ_TAMPER (STM32_IRQ_FIRST + 2) /* 2: Tamper and time stamp interrupts */ +#define STM32_IRQ_TIMESTAMP (STM32_IRQ_FIRST + 2) /* 2: Tamper and time stamp interrupts */ +#define STM32_IRQ_RTC_WKUP (STM32_IRQ_FIRST + 3) /* 3: RTC global interrupt */ +#define STM32_IRQ_FLASH (STM32_IRQ_FIRST + 4) /* 4: Flash global interrupt */ +#define STM32_IRQ_RCC (STM32_IRQ_FIRST + 5) /* 5: RCC global interrupt */ +#define STM32_IRQ_EXTI0 (STM32_IRQ_FIRST + 6) /* 6: EXTI Line 0 interrupt */ +#define STM32_IRQ_EXTI1 (STM32_IRQ_FIRST + 7) /* 7: EXTI Line 1 interrupt */ +#define STM32_IRQ_EXTI2 (STM32_IRQ_FIRST + 8) /* 8: EXTI Line 2 interrupt */ +#define STM32_IRQ_EXTI3 (STM32_IRQ_FIRST + 9) /* 9: EXTI Line 3 interrupt */ +#define STM32_IRQ_EXTI4 (STM32_IRQ_FIRST + 10) /* 10: EXTI Line 4 interrupt */ +#define STM32_IRQ_DMA1CH1 (STM32_IRQ_FIRST + 11) /* 11: DMA1 Channel 1 global interrupt */ +#define STM32_IRQ_DMA1CH2 (STM32_IRQ_FIRST + 12) /* 12: DMA1 Channel 2 global interrupt */ +#define STM32_IRQ_DMA1CH3 (STM32_IRQ_FIRST + 13) /* 13: DMA1 Channel 3 global interrupt */ +#define STM32_IRQ_DMA1CH4 (STM32_IRQ_FIRST + 14) /* 14: DMA1 Channel 4 global interrupt */ +#define STM32_IRQ_DMA1CH5 (STM32_IRQ_FIRST + 15) /* 15: DMA1 Channel 5 global interrupt */ +#define STM32_IRQ_DMA1CH6 (STM32_IRQ_FIRST + 16) /* 16: DMA1 Channel 6 global interrupt */ +#define STM32_IRQ_DMA1CH7 (STM32_IRQ_FIRST + 17) /* 17: DMA1 Channel 7 global interrupt */ +#define STM32_IRQ_ADC1 (STM32_IRQ_FIRST + 18) /* 18: ADC1 global interrupt */ +#define STM32_IRQ_CAN1TX (STM32_IRQ_FIRST + 19) /* 19: CAN1 TX interrupts */ +#define STM32_IRQ_CAN1RX0 (STM32_IRQ_FIRST + 20) /* 20: CAN1 RX0 interrupts */ +#define STM32_IRQ_CAN1RX1 (STM32_IRQ_FIRST + 21) /* 21: CAN1 RX1 interrupt */ +#define STM32_IRQ_CAN1SCE (STM32_IRQ_FIRST + 22) /* 22: CAN1 SCE interrupt */ +#define STM32_IRQ_EXTI95 (STM32_IRQ_FIRST + 23) /* 23: EXTI Line[9:5] interrupts */ +#define STM32_IRQ_TIM1BRK (STM32_IRQ_FIRST + 24) /* 24: TIM1 Break interrupt */ +#define STM32_IRQ_TIM15 (STM32_IRQ_FIRST + 24) /* 24: TIM15 global interrupt */ +#define STM32_IRQ_TIM1UP (STM32_IRQ_FIRST + 25) /* 25: TIM1 Update interrupt */ +#define STM32_IRQ_TIM16 (STM32_IRQ_FIRST + 25) /* 25: TIM16 global interrupt */ +#define STM32_IRQ_TIM1TRGCOM (STM32_IRQ_FIRST + 26) /* 26: TIM1 Trigger and Commutation interrupts */ +#define STM32_IRQ_TIM1CC (STM32_IRQ_FIRST + 27) /* 27: TIM1 Capture Compare interrupt */ +#define STM32_IRQ_TIM2 (STM32_IRQ_FIRST + 28) /* 28: TIM2 global interrupt */ +#define STM32_IRQ_TIM3 (STM32_IRQ_FIRST + 29) /* 29: TIM3 global interrupt */ + /* Reserved 30: TIM4 global interrupt */ +#define STM32_IRQ_I2C1EV (STM32_IRQ_FIRST + 31) /* 31: I2C1 event interrupt */ +#define STM32_IRQ_I2C1ER (STM32_IRQ_FIRST + 32) /* 32: I2C1 error interrupt */ +#define STM32_IRQ_I2C2EV (STM32_IRQ_FIRST + 33) /* 33: I2C2 event interrupt */ +#define STM32_IRQ_I2C2ER (STM32_IRQ_FIRST + 34) /* 34: I2C2 error interrupt */ +#define STM32_IRQ_SPI1 (STM32_IRQ_FIRST + 35) /* 35: SPI1 global interrupt */ +#define STM32_IRQ_SPI2 (STM32_IRQ_FIRST + 36) /* 36: SPI2 global interrupt */ +#define STM32_IRQ_USART1 (STM32_IRQ_FIRST + 37) /* 37: USART1 global interrupt */ +#define STM32_IRQ_USART2 (STM32_IRQ_FIRST + 38) /* 38: USART2 global interrupt */ +#define STM32_IRQ_USART3 (STM32_IRQ_FIRST + 39) /* 39: USART3 global interrupt */ +#define STM32_IRQ_EXTI1510 (STM32_IRQ_FIRST + 40) /* 40: EXTI Line[15:10] interrupts */ +#define STM32_IRQ_RTCALRM (STM32_IRQ_FIRST + 41) /* 41: RTC alarm through EXTI line interrupt */ + /* Reserved 42-48 */ +#define STM32_IRQ_SDMMC1 (STM32_IRQ_FIRST + 49) /* 49: SDMMC1 global interrupt */ + /* Reserved 50: TIM5 global interrupt */ +#define STM32_IRQ_SPI3 (STM32_IRQ_FIRST + 51) /* 51: SPI3 global interrupt */ +#define STM32_IRQ_UART4 (STM32_IRQ_FIRST + 52) /* 52: UART4 global interrupt */ + /* Reserved 53: UART5 global interrupt */ +#define STM32_IRQ_TIM6 (STM32_IRQ_FIRST + 54) /* 54: TIM6 global interrupt */ +#define STM32_IRQ_DAC (STM32_IRQ_FIRST + 54) /* 54: DAC1 underrun error interrupts */ +#define STM32_IRQ_TIM7 (STM32_IRQ_FIRST + 55) /* 55: TIM7 global interrupt */ +#define STM32_IRQ_DMA2CH1 (STM32_IRQ_FIRST + 56) /* 56: DMA2 Channel 1 global interrupt */ +#define STM32_IRQ_DMA2CH2 (STM32_IRQ_FIRST + 57) /* 57: DMA2 Channel 2 global interrupt */ +#define STM32_IRQ_DMA2CH3 (STM32_IRQ_FIRST + 58) /* 58: DMA2 Channel 3 global interrupt */ +#define STM32_IRQ_DMA2CH4 (STM32_IRQ_FIRST + 59) /* 59: DMA2 Channel 4 global interrupt */ +#define STM32_IRQ_DMA2CH5 (STM32_IRQ_FIRST + 60) /* 60: DMA2 Channel 5 global interrupt */ +#define STM32_IRQ_DFSDM0 (STM32_IRQ_FIRST + 61) /* 61: DFSDM0 global interrupt */ +#define STM32_IRQ_DFSDM1 (STM32_IRQ_FIRST + 62) /* 62: DFSDM1 global interrupt*/ + /* Reserved 63: DFSDM2 global interrupt */ +#define STM32_IRQ_COMP (STM32_IRQ_FIRST + 64) /* 64: COMP1/COMP2 interrupts */ +#define STM32_IRQ_LPTIM1 (STM32_IRQ_FIRST + 65) /* 65: LPTIM1 global interrupt */ +#define STM32_IRQ_LPTIM2 (STM32_IRQ_FIRST + 66) /* 66: LPTIM2 global interrupt */ +#define STM32_IRQ_USB_FS (STM32_IRQ_FIRST + 67) /* 67: USB event interrupt through EXTI line 17 */ +#define STM32_IRQ_DMA2CH6 (STM32_IRQ_FIRST + 68) /* 68: DMA2 Channel 6 global interrupt */ +#define STM32_IRQ_DMA2CH7 (STM32_IRQ_FIRST + 69) /* 69: DMA2 Channel 7 global interrupt */ +#define STM32_IRQ_LPUART1 (STM32_IRQ_FIRST + 70) /* 70: Low power UART 1 global interrupt */ +#define STM32_IRQ_QUADSPI (STM32_IRQ_FIRST + 71) /* 71: QUADSPI global interrupt */ +#define STM32_IRQ_I2C3EV (STM32_IRQ_FIRST + 72) /* 72: I2C3 event interrupt */ +#define STM32_IRQ_I2C3ER (STM32_IRQ_FIRST + 73) /* 73: I2C3 error interrupt */ +#define STM32_IRQ_SAI1 (STM32_IRQ_FIRST + 74) /* 74: SAI1 global interrupt */ + /* Reserved 75: SAI2 global interrupt */ +#define STM32_IRQ_SWPMI1 (STM32_IRQ_FIRST + 76) /* 76: SWPMI1 global interrupt */ +#define STM32_IRQ_TSC (STM32_IRQ_FIRST + 77) /* 77: TSC global interrupt */ +#define STM32_IRQ_LCD (STM32_IRQ_FIRST + 78) /* 78: LCD global interrupt */ +#define STM32_IRQ_AES (STM32_IRQ_FIRST + 79) /* 79: AES crypto global interrupt */ +#define STM32_IRQ_RNG (STM32_IRQ_FIRST + 80) /* 80: RNG global interrupt */ +#define STM32_IRQ_FPU (STM32_IRQ_FIRST + 81) /* 81: FPU global interrupt */ +#define STM32_IRQ_CRS (STM32_IRQ_FIRST + 82) /* 82: CRS global interrupt */ +#define STM32_IRQ_I2C4EV (STM32_IRQ_FIRST + 83) /* 83: I2C4 event interrupt */ +#define STM32_IRQ_I2C4ER (STM32_IRQ_FIRST + 84) /* 84: I2C4 error interrupt */ + +#if defined(CONFIG_STM32_STM32L4X3) +# define STM32_IRQ_NEXTINTS 85 #else # error "Unsupported STM32L4 chip" #endif /* (EXTI interrupts do not use IRQ numbers) */ -#define NR_IRQS (STM32L4_IRQ_FIRST + STM32L4_IRQ_NEXTINTS) +#define NR_IRQS (STM32_IRQ_FIRST + STM32_IRQ_NEXTINTS) /**************************************************************************** * Public Types diff --git a/arch/arm/include/stm32l4/stm32l4x5xx_irq.h b/arch/arm/include/stm32l4/stm32l4x5xx_irq.h index 3c0c8f49842a4..e21faaae23000 100644 --- a/arch/arm/include/stm32l4/stm32l4x5xx_irq.h +++ b/arch/arm/include/stm32l4/stm32l4x5xx_irq.h @@ -48,99 +48,99 @@ * External interrupts (vectors >= 16) */ -#define STM32L4_IRQ_WWDG (STM32L4_IRQ_FIRST + 0) /* 0: Window Watchdog interrupt */ -#define STM32L4_IRQ_PVD (STM32L4_IRQ_FIRST + 1) /* 1: PVD through EXTI Line detection interrupt */ -#define STM32L4_IRQ_TAMPER (STM32L4_IRQ_FIRST + 2) /* 2: Tamper and time stamp interrupts */ -#define STM32L4_IRQ_TIMESTAMP (STM32L4_IRQ_FIRST + 2) /* 2: Tamper and time stamp interrupts */ -#define STM32L4_IRQ_RTC_WKUP (STM32L4_IRQ_FIRST + 3) /* 3: RTC global interrupt */ -#define STM32L4_IRQ_FLASH (STM32L4_IRQ_FIRST + 4) /* 4: Flash global interrupt */ -#define STM32L4_IRQ_RCC (STM32L4_IRQ_FIRST + 5) /* 5: RCC global interrupt */ -#define STM32L4_IRQ_EXTI0 (STM32L4_IRQ_FIRST + 6) /* 6: EXTI Line 0 interrupt */ -#define STM32L4_IRQ_EXTI1 (STM32L4_IRQ_FIRST + 7) /* 7: EXTI Line 1 interrupt */ -#define STM32L4_IRQ_EXTI2 (STM32L4_IRQ_FIRST + 8) /* 8: EXTI Line 2 interrupt */ -#define STM32L4_IRQ_EXTI3 (STM32L4_IRQ_FIRST + 9) /* 9: EXTI Line 3 interrupt */ -#define STM32L4_IRQ_EXTI4 (STM32L4_IRQ_FIRST + 10) /* 10: EXTI Line 4 interrupt */ -#define STM32L4_IRQ_DMA1CH1 (STM32L4_IRQ_FIRST + 11) /* 11: DMA1 Channel 1 global interrupt */ -#define STM32L4_IRQ_DMA1CH2 (STM32L4_IRQ_FIRST + 12) /* 12: DMA1 Channel 2 global interrupt */ -#define STM32L4_IRQ_DMA1CH3 (STM32L4_IRQ_FIRST + 13) /* 13: DMA1 Channel 3 global interrupt */ -#define STM32L4_IRQ_DMA1CH4 (STM32L4_IRQ_FIRST + 14) /* 14: DMA1 Channel 4 global interrupt */ -#define STM32L4_IRQ_DMA1CH5 (STM32L4_IRQ_FIRST + 15) /* 15: DMA1 Channel 5 global interrupt */ -#define STM32L4_IRQ_DMA1CH6 (STM32L4_IRQ_FIRST + 16) /* 16: DMA1 Channel 6 global interrupt */ -#define STM32L4_IRQ_DMA1CH7 (STM32L4_IRQ_FIRST + 17) /* 17: DMA1 Channel 7 global interrupt */ -#define STM32L4_IRQ_ADC12 (STM32L4_IRQ_FIRST + 18) /* 18: ADC1 and ADC2 global interrupt */ -#define STM32L4_IRQ_CAN1TX (STM32L4_IRQ_FIRST + 19) /* 19: CAN1 TX interrupts */ -#define STM32L4_IRQ_CAN1RX0 (STM32L4_IRQ_FIRST + 20) /* 20: CAN1 RX0 interrupts */ -#define STM32L4_IRQ_CAN1RX1 (STM32L4_IRQ_FIRST + 21) /* 21: CAN1 RX1 interrupt */ -#define STM32L4_IRQ_CAN1SCE (STM32L4_IRQ_FIRST + 22) /* 22: CAN1 SCE interrupt */ -#define STM32L4_IRQ_EXTI95 (STM32L4_IRQ_FIRST + 23) /* 23: EXTI Line[9:5] interrupts */ -#define STM32L4_IRQ_TIM1BRK (STM32L4_IRQ_FIRST + 24) /* 24: TIM1 Break interrupt */ -#define STM32L4_IRQ_TIM15 (STM32L4_IRQ_FIRST + 24) /* 24: TIM15 global interrupt */ -#define STM32L4_IRQ_TIM1UP (STM32L4_IRQ_FIRST + 25) /* 25: TIM1 Update interrupt */ -#define STM32L4_IRQ_TIM16 (STM32L4_IRQ_FIRST + 25) /* 25: TIM16 global interrupt */ -#define STM32L4_IRQ_TIM1TRGCOM (STM32L4_IRQ_FIRST + 26) /* 26: TIM1 Trigger and Commutation interrupts */ -#define STM32L4_IRQ_TIM17 (STM32L4_IRQ_FIRST + 26) /* 26: TIM17 global interrupt */ -#define STM32L4_IRQ_TIM1CC (STM32L4_IRQ_FIRST + 27) /* 27: TIM1 Capture Compare interrupt */ -#define STM32L4_IRQ_TIM2 (STM32L4_IRQ_FIRST + 28) /* 28: TIM2 global interrupt */ -#define STM32L4_IRQ_TIM3 (STM32L4_IRQ_FIRST + 29) /* 29: TIM3 global interrupt */ -#define STM32L4_IRQ_TIM4 (STM32L4_IRQ_FIRST + 30) /* 30: TIM4 global interrupt */ -#define STM32L4_IRQ_I2C1EV (STM32L4_IRQ_FIRST + 31) /* 31: I2C1 event interrupt */ -#define STM32L4_IRQ_I2C1ER (STM32L4_IRQ_FIRST + 32) /* 32: I2C1 error interrupt */ -#define STM32L4_IRQ_I2C2EV (STM32L4_IRQ_FIRST + 33) /* 33: I2C2 event interrupt */ -#define STM32L4_IRQ_I2C2ER (STM32L4_IRQ_FIRST + 34) /* 34: I2C2 error interrupt */ -#define STM32L4_IRQ_SPI1 (STM32L4_IRQ_FIRST + 35) /* 35: SPI1 global interrupt */ -#define STM32L4_IRQ_SPI2 (STM32L4_IRQ_FIRST + 36) /* 36: SPI2 global interrupt */ -#define STM32L4_IRQ_USART1 (STM32L4_IRQ_FIRST + 37) /* 37: USART1 global interrupt */ -#define STM32L4_IRQ_USART2 (STM32L4_IRQ_FIRST + 38) /* 38: USART2 global interrupt */ -#define STM32L4_IRQ_USART3 (STM32L4_IRQ_FIRST + 39) /* 39: USART3 global interrupt */ -#define STM32L4_IRQ_EXTI1510 (STM32L4_IRQ_FIRST + 40) /* 40: EXTI Line[15:10] interrupts */ -#define STM32L4_IRQ_RTCALRM (STM32L4_IRQ_FIRST + 41) /* 41: RTC alarm through EXTI line interrupt */ -#define STM32L4_IRQ_DFSDM3 (STM32L4_IRQ_FIRST + 42) /* 42: Digital Filter / Sigma Delta Modulator interrupt */ -#define STM32L4_IRQ_TIM8BRK (STM32L4_IRQ_FIRST + 43) /* 43: TIM8 Break interrupt */ -#define STM32L4_IRQ_TIM8UP (STM32L4_IRQ_FIRST + 44) /* 44: TIM8 Update interrupt */ -#define STM32L4_IRQ_TIM8TRGCOM (STM32L4_IRQ_FIRST + 45) /* 45: TIM8 Trigger and Commutation interrupts */ -#define STM32L4_IRQ_TIM8CC (STM32L4_IRQ_FIRST + 46) /* 46: TIM8 Capture Compare interrupt */ -#define STM32L4_IRQ_ADC3 (STM32L4_IRQ_FIRST + 47) /* 47: ADC3 global interrupt */ -#define STM32L4_IRQ_FSMC (STM32L4_IRQ_FIRST + 48) /* 48: FSMC global interrupt */ -#define STM32L4_IRQ_SDMMC1 (STM32L4_IRQ_FIRST + 49) /* 49: SDMMC1 global interrupt */ -#define STM32L4_IRQ_TIM5 (STM32L4_IRQ_FIRST + 50) /* 50: TIM5 global interrupt */ -#define STM32L4_IRQ_SPI3 (STM32L4_IRQ_FIRST + 51) /* 51: SPI3 global interrupt */ -#define STM32L4_IRQ_UART4 (STM32L4_IRQ_FIRST + 52) /* 52: UART4 global interrupt */ -#define STM32L4_IRQ_UART5 (STM32L4_IRQ_FIRST + 53) /* 53: UART5 global interrupt */ -#define STM32L4_IRQ_TIM6 (STM32L4_IRQ_FIRST + 54) /* 54: TIM6 global interrupt */ -#define STM32L4_IRQ_DAC (STM32L4_IRQ_FIRST + 54) /* 54: DAC1 and DAC2 underrun error interrupts */ -#define STM32L4_IRQ_TIM7 (STM32L4_IRQ_FIRST + 55) /* 55: TIM7 global interrupt */ -#define STM32L4_IRQ_DMA2CH1 (STM32L4_IRQ_FIRST + 56) /* 56: DMA2 Channel 1 global interrupt */ -#define STM32L4_IRQ_DMA2CH2 (STM32L4_IRQ_FIRST + 57) /* 57: DMA2 Channel 2 global interrupt */ -#define STM32L4_IRQ_DMA2CH3 (STM32L4_IRQ_FIRST + 58) /* 58: DMA2 Channel 3 global interrupt */ -#define STM32L4_IRQ_DMA2CH4 (STM32L4_IRQ_FIRST + 59) /* 59: DMA2 Channel 4 global interrupt */ -#define STM32L4_IRQ_DMA2CH5 (STM32L4_IRQ_FIRST + 60) /* 60: DMA2 Channel 5 global interrupt */ -#define STM32L4_IRQ_DFSDM0 (STM32L4_IRQ_FIRST + 61) /* 61: DFSDM0 global interrupt */ -#define STM32L4_IRQ_DFSDM1 (STM32L4_IRQ_FIRST + 62) /* 62: DFSDM1 global interrupt*/ -#define STM32L4_IRQ_DFSDM2 (STM32L4_IRQ_FIRST + 63) /* 63: DFSDM2 global interrupt */ -#define STM32L4_IRQ_COMP (STM32L4_IRQ_FIRST + 64) /* 64: COMP1/COMP2 interrupts */ -#define STM32L4_IRQ_LPTIM1 (STM32L4_IRQ_FIRST + 65) /* 65: LPTIM1 global interrupt */ -#define STM32L4_IRQ_LPTIM2 (STM32L4_IRQ_FIRST + 66) /* 66: LPTIM2 global interrupt */ -#define STM32L4_IRQ_OTGFS (STM32L4_IRQ_FIRST + 67) /* 67: USB On The Go FS global interrupt */ -#define STM32L4_IRQ_DMA2CH6 (STM32L4_IRQ_FIRST + 68) /* 68: DMA2 Channel 6 global interrupt */ -#define STM32L4_IRQ_DMA2CH7 (STM32L4_IRQ_FIRST + 69) /* 69: DMA2 Channel 7 global interrupt */ -#define STM32L4_IRQ_LPUART1 (STM32L4_IRQ_FIRST + 70) /* 70: Low power UART 1 global interrupt */ -#define STM32L4_IRQ_QUADSPI (STM32L4_IRQ_FIRST + 71) /* 71: QUADSPI global interrupt */ -#define STM32L4_IRQ_I2C3EV (STM32L4_IRQ_FIRST + 72) /* 72: I2C3 event interrupt */ -#define STM32L4_IRQ_I2C3ER (STM32L4_IRQ_FIRST + 73) /* 73: I2C3 error interrupt */ -#define STM32L4_IRQ_SAI1 (STM32L4_IRQ_FIRST + 74) /* 74: SAI1 global interrupt */ -#define STM32L4_IRQ_SAI2 (STM32L4_IRQ_FIRST + 75) /* 75: SAI2 global interrupt */ -#define STM32L4_IRQ_SWPMI1 (STM32L4_IRQ_FIRST + 76) /* 76: SWPMI1 global interrupt */ -#define STM32L4_IRQ_TSC (STM32L4_IRQ_FIRST + 77) /* 77: TSC global interrupt */ -#define STM32L4_IRQ_RESERVED78 (STM32L4_IRQ_FIRST + 78) /* 78: Reserved */ -#define STM32L4_IRQ_RESERVED79 (STM32L4_IRQ_FIRST + 79) /* 79: Reserved */ -#define STM32L4_IRQ_RNG (STM32L4_IRQ_FIRST + 80) /* 80: RNG global interrupt */ -#define STM32L4_IRQ_FPU (STM32L4_IRQ_FIRST + 81) /* 81: FPU global interrupt */ - -#define STM32L4_IRQ_NEXTINTS 82 +#define STM32_IRQ_WWDG (STM32_IRQ_FIRST + 0) /* 0: Window Watchdog interrupt */ +#define STM32_IRQ_PVD (STM32_IRQ_FIRST + 1) /* 1: PVD through EXTI Line detection interrupt */ +#define STM32_IRQ_TAMPER (STM32_IRQ_FIRST + 2) /* 2: Tamper and time stamp interrupts */ +#define STM32_IRQ_TIMESTAMP (STM32_IRQ_FIRST + 2) /* 2: Tamper and time stamp interrupts */ +#define STM32_IRQ_RTC_WKUP (STM32_IRQ_FIRST + 3) /* 3: RTC global interrupt */ +#define STM32_IRQ_FLASH (STM32_IRQ_FIRST + 4) /* 4: Flash global interrupt */ +#define STM32_IRQ_RCC (STM32_IRQ_FIRST + 5) /* 5: RCC global interrupt */ +#define STM32_IRQ_EXTI0 (STM32_IRQ_FIRST + 6) /* 6: EXTI Line 0 interrupt */ +#define STM32_IRQ_EXTI1 (STM32_IRQ_FIRST + 7) /* 7: EXTI Line 1 interrupt */ +#define STM32_IRQ_EXTI2 (STM32_IRQ_FIRST + 8) /* 8: EXTI Line 2 interrupt */ +#define STM32_IRQ_EXTI3 (STM32_IRQ_FIRST + 9) /* 9: EXTI Line 3 interrupt */ +#define STM32_IRQ_EXTI4 (STM32_IRQ_FIRST + 10) /* 10: EXTI Line 4 interrupt */ +#define STM32_IRQ_DMA1CH1 (STM32_IRQ_FIRST + 11) /* 11: DMA1 Channel 1 global interrupt */ +#define STM32_IRQ_DMA1CH2 (STM32_IRQ_FIRST + 12) /* 12: DMA1 Channel 2 global interrupt */ +#define STM32_IRQ_DMA1CH3 (STM32_IRQ_FIRST + 13) /* 13: DMA1 Channel 3 global interrupt */ +#define STM32_IRQ_DMA1CH4 (STM32_IRQ_FIRST + 14) /* 14: DMA1 Channel 4 global interrupt */ +#define STM32_IRQ_DMA1CH5 (STM32_IRQ_FIRST + 15) /* 15: DMA1 Channel 5 global interrupt */ +#define STM32_IRQ_DMA1CH6 (STM32_IRQ_FIRST + 16) /* 16: DMA1 Channel 6 global interrupt */ +#define STM32_IRQ_DMA1CH7 (STM32_IRQ_FIRST + 17) /* 17: DMA1 Channel 7 global interrupt */ +#define STM32_IRQ_ADC12 (STM32_IRQ_FIRST + 18) /* 18: ADC1 and ADC2 global interrupt */ +#define STM32_IRQ_CAN1TX (STM32_IRQ_FIRST + 19) /* 19: CAN1 TX interrupts */ +#define STM32_IRQ_CAN1RX0 (STM32_IRQ_FIRST + 20) /* 20: CAN1 RX0 interrupts */ +#define STM32_IRQ_CAN1RX1 (STM32_IRQ_FIRST + 21) /* 21: CAN1 RX1 interrupt */ +#define STM32_IRQ_CAN1SCE (STM32_IRQ_FIRST + 22) /* 22: CAN1 SCE interrupt */ +#define STM32_IRQ_EXTI95 (STM32_IRQ_FIRST + 23) /* 23: EXTI Line[9:5] interrupts */ +#define STM32_IRQ_TIM1BRK (STM32_IRQ_FIRST + 24) /* 24: TIM1 Break interrupt */ +#define STM32_IRQ_TIM15 (STM32_IRQ_FIRST + 24) /* 24: TIM15 global interrupt */ +#define STM32_IRQ_TIM1UP (STM32_IRQ_FIRST + 25) /* 25: TIM1 Update interrupt */ +#define STM32_IRQ_TIM16 (STM32_IRQ_FIRST + 25) /* 25: TIM16 global interrupt */ +#define STM32_IRQ_TIM1TRGCOM (STM32_IRQ_FIRST + 26) /* 26: TIM1 Trigger and Commutation interrupts */ +#define STM32_IRQ_TIM17 (STM32_IRQ_FIRST + 26) /* 26: TIM17 global interrupt */ +#define STM32_IRQ_TIM1CC (STM32_IRQ_FIRST + 27) /* 27: TIM1 Capture Compare interrupt */ +#define STM32_IRQ_TIM2 (STM32_IRQ_FIRST + 28) /* 28: TIM2 global interrupt */ +#define STM32_IRQ_TIM3 (STM32_IRQ_FIRST + 29) /* 29: TIM3 global interrupt */ +#define STM32_IRQ_TIM4 (STM32_IRQ_FIRST + 30) /* 30: TIM4 global interrupt */ +#define STM32_IRQ_I2C1EV (STM32_IRQ_FIRST + 31) /* 31: I2C1 event interrupt */ +#define STM32_IRQ_I2C1ER (STM32_IRQ_FIRST + 32) /* 32: I2C1 error interrupt */ +#define STM32_IRQ_I2C2EV (STM32_IRQ_FIRST + 33) /* 33: I2C2 event interrupt */ +#define STM32_IRQ_I2C2ER (STM32_IRQ_FIRST + 34) /* 34: I2C2 error interrupt */ +#define STM32_IRQ_SPI1 (STM32_IRQ_FIRST + 35) /* 35: SPI1 global interrupt */ +#define STM32_IRQ_SPI2 (STM32_IRQ_FIRST + 36) /* 36: SPI2 global interrupt */ +#define STM32_IRQ_USART1 (STM32_IRQ_FIRST + 37) /* 37: USART1 global interrupt */ +#define STM32_IRQ_USART2 (STM32_IRQ_FIRST + 38) /* 38: USART2 global interrupt */ +#define STM32_IRQ_USART3 (STM32_IRQ_FIRST + 39) /* 39: USART3 global interrupt */ +#define STM32_IRQ_EXTI1510 (STM32_IRQ_FIRST + 40) /* 40: EXTI Line[15:10] interrupts */ +#define STM32_IRQ_RTCALRM (STM32_IRQ_FIRST + 41) /* 41: RTC alarm through EXTI line interrupt */ +#define STM32_IRQ_DFSDM3 (STM32_IRQ_FIRST + 42) /* 42: Digital Filter / Sigma Delta Modulator interrupt */ +#define STM32_IRQ_TIM8BRK (STM32_IRQ_FIRST + 43) /* 43: TIM8 Break interrupt */ +#define STM32_IRQ_TIM8UP (STM32_IRQ_FIRST + 44) /* 44: TIM8 Update interrupt */ +#define STM32_IRQ_TIM8TRGCOM (STM32_IRQ_FIRST + 45) /* 45: TIM8 Trigger and Commutation interrupts */ +#define STM32_IRQ_TIM8CC (STM32_IRQ_FIRST + 46) /* 46: TIM8 Capture Compare interrupt */ +#define STM32_IRQ_ADC3 (STM32_IRQ_FIRST + 47) /* 47: ADC3 global interrupt */ +#define STM32_IRQ_FSMC (STM32_IRQ_FIRST + 48) /* 48: FSMC global interrupt */ +#define STM32_IRQ_SDMMC1 (STM32_IRQ_FIRST + 49) /* 49: SDMMC1 global interrupt */ +#define STM32_IRQ_TIM5 (STM32_IRQ_FIRST + 50) /* 50: TIM5 global interrupt */ +#define STM32_IRQ_SPI3 (STM32_IRQ_FIRST + 51) /* 51: SPI3 global interrupt */ +#define STM32_IRQ_UART4 (STM32_IRQ_FIRST + 52) /* 52: UART4 global interrupt */ +#define STM32_IRQ_UART5 (STM32_IRQ_FIRST + 53) /* 53: UART5 global interrupt */ +#define STM32_IRQ_TIM6 (STM32_IRQ_FIRST + 54) /* 54: TIM6 global interrupt */ +#define STM32_IRQ_DAC (STM32_IRQ_FIRST + 54) /* 54: DAC1 and DAC2 underrun error interrupts */ +#define STM32_IRQ_TIM7 (STM32_IRQ_FIRST + 55) /* 55: TIM7 global interrupt */ +#define STM32_IRQ_DMA2CH1 (STM32_IRQ_FIRST + 56) /* 56: DMA2 Channel 1 global interrupt */ +#define STM32_IRQ_DMA2CH2 (STM32_IRQ_FIRST + 57) /* 57: DMA2 Channel 2 global interrupt */ +#define STM32_IRQ_DMA2CH3 (STM32_IRQ_FIRST + 58) /* 58: DMA2 Channel 3 global interrupt */ +#define STM32_IRQ_DMA2CH4 (STM32_IRQ_FIRST + 59) /* 59: DMA2 Channel 4 global interrupt */ +#define STM32_IRQ_DMA2CH5 (STM32_IRQ_FIRST + 60) /* 60: DMA2 Channel 5 global interrupt */ +#define STM32_IRQ_DFSDM0 (STM32_IRQ_FIRST + 61) /* 61: DFSDM0 global interrupt */ +#define STM32_IRQ_DFSDM1 (STM32_IRQ_FIRST + 62) /* 62: DFSDM1 global interrupt*/ +#define STM32_IRQ_DFSDM2 (STM32_IRQ_FIRST + 63) /* 63: DFSDM2 global interrupt */ +#define STM32_IRQ_COMP (STM32_IRQ_FIRST + 64) /* 64: COMP1/COMP2 interrupts */ +#define STM32_IRQ_LPTIM1 (STM32_IRQ_FIRST + 65) /* 65: LPTIM1 global interrupt */ +#define STM32_IRQ_LPTIM2 (STM32_IRQ_FIRST + 66) /* 66: LPTIM2 global interrupt */ +#define STM32_IRQ_OTGFS (STM32_IRQ_FIRST + 67) /* 67: USB On The Go FS global interrupt */ +#define STM32_IRQ_DMA2CH6 (STM32_IRQ_FIRST + 68) /* 68: DMA2 Channel 6 global interrupt */ +#define STM32_IRQ_DMA2CH7 (STM32_IRQ_FIRST + 69) /* 69: DMA2 Channel 7 global interrupt */ +#define STM32_IRQ_LPUART1 (STM32_IRQ_FIRST + 70) /* 70: Low power UART 1 global interrupt */ +#define STM32_IRQ_QUADSPI (STM32_IRQ_FIRST + 71) /* 71: QUADSPI global interrupt */ +#define STM32_IRQ_I2C3EV (STM32_IRQ_FIRST + 72) /* 72: I2C3 event interrupt */ +#define STM32_IRQ_I2C3ER (STM32_IRQ_FIRST + 73) /* 73: I2C3 error interrupt */ +#define STM32_IRQ_SAI1 (STM32_IRQ_FIRST + 74) /* 74: SAI1 global interrupt */ +#define STM32_IRQ_SAI2 (STM32_IRQ_FIRST + 75) /* 75: SAI2 global interrupt */ +#define STM32_IRQ_SWPMI1 (STM32_IRQ_FIRST + 76) /* 76: SWPMI1 global interrupt */ +#define STM32_IRQ_TSC (STM32_IRQ_FIRST + 77) /* 77: TSC global interrupt */ +#define STM32_IRQ_RESERVED78 (STM32_IRQ_FIRST + 78) /* 78: Reserved */ +#define STM32_IRQ_RESERVED79 (STM32_IRQ_FIRST + 79) /* 79: Reserved */ +#define STM32_IRQ_RNG (STM32_IRQ_FIRST + 80) /* 80: RNG global interrupt */ +#define STM32_IRQ_FPU (STM32_IRQ_FIRST + 81) /* 81: FPU global interrupt */ + +#define STM32_IRQ_NEXTINTS 82 /* EXTI interrupts (Do not use IRQ numbers) */ -#define NR_IRQS (STM32L4_IRQ_FIRST + STM32L4_IRQ_NEXTINTS) +#define NR_IRQS (STM32_IRQ_FIRST + STM32_IRQ_NEXTINTS) /**************************************************************************** * Public Types diff --git a/arch/arm/include/stm32l4/stm32l4x6xx_irq.h b/arch/arm/include/stm32l4/stm32l4x6xx_irq.h index 039cc81d92a90..7b3eca2a84801 100644 --- a/arch/arm/include/stm32l4/stm32l4x6xx_irq.h +++ b/arch/arm/include/stm32l4/stm32l4x6xx_irq.h @@ -48,117 +48,117 @@ * External interrupts (vectors >= 16) */ -#define STM32L4_IRQ_WWDG (STM32L4_IRQ_FIRST + 0) /* 0: Window Watchdog interrupt */ -#define STM32L4_IRQ_PVD (STM32L4_IRQ_FIRST + 1) /* 1: PVD through EXTI Line detection interrupt */ -#define STM32L4_IRQ_TAMPER (STM32L4_IRQ_FIRST + 2) /* 2: Tamper and time stamp interrupts */ -#define STM32L4_IRQ_TIMESTAMP (STM32L4_IRQ_FIRST + 2) /* 2: Tamper and time stamp interrupts */ -#define STM32L4_IRQ_RTC_WKUP (STM32L4_IRQ_FIRST + 3) /* 3: RTC global interrupt */ -#define STM32L4_IRQ_FLASH (STM32L4_IRQ_FIRST + 4) /* 4: Flash global interrupt */ -#define STM32L4_IRQ_RCC (STM32L4_IRQ_FIRST + 5) /* 5: RCC global interrupt */ -#define STM32L4_IRQ_EXTI0 (STM32L4_IRQ_FIRST + 6) /* 6: EXTI Line 0 interrupt */ -#define STM32L4_IRQ_EXTI1 (STM32L4_IRQ_FIRST + 7) /* 7: EXTI Line 1 interrupt */ -#define STM32L4_IRQ_EXTI2 (STM32L4_IRQ_FIRST + 8) /* 8: EXTI Line 2 interrupt */ -#define STM32L4_IRQ_EXTI3 (STM32L4_IRQ_FIRST + 9) /* 9: EXTI Line 3 interrupt */ -#define STM32L4_IRQ_EXTI4 (STM32L4_IRQ_FIRST + 10) /* 10: EXTI Line 4 interrupt */ -#define STM32L4_IRQ_DMA1CH1 (STM32L4_IRQ_FIRST + 11) /* 11: DMA1 Channel 1 global interrupt */ -#define STM32L4_IRQ_DMA1CH2 (STM32L4_IRQ_FIRST + 12) /* 12: DMA1 Channel 2 global interrupt */ -#define STM32L4_IRQ_DMA1CH3 (STM32L4_IRQ_FIRST + 13) /* 13: DMA1 Channel 3 global interrupt */ -#define STM32L4_IRQ_DMA1CH4 (STM32L4_IRQ_FIRST + 14) /* 14: DMA1 Channel 4 global interrupt */ -#define STM32L4_IRQ_DMA1CH5 (STM32L4_IRQ_FIRST + 15) /* 15: DMA1 Channel 5 global interrupt */ -#define STM32L4_IRQ_DMA1CH6 (STM32L4_IRQ_FIRST + 16) /* 16: DMA1 Channel 6 global interrupt */ -#define STM32L4_IRQ_DMA1CH7 (STM32L4_IRQ_FIRST + 17) /* 17: DMA1 Channel 7 global interrupt */ -#define STM32L4_IRQ_ADC12 (STM32L4_IRQ_FIRST + 18) /* 18: ADC1 and ADC2 global interrupt */ -#define STM32L4_IRQ_CAN1TX (STM32L4_IRQ_FIRST + 19) /* 19: CAN1 TX interrupts */ -#define STM32L4_IRQ_CAN1RX0 (STM32L4_IRQ_FIRST + 20) /* 20: CAN1 RX0 interrupts */ -#define STM32L4_IRQ_CAN1RX1 (STM32L4_IRQ_FIRST + 21) /* 21: CAN1 RX1 interrupt */ -#define STM32L4_IRQ_CAN1SCE (STM32L4_IRQ_FIRST + 22) /* 22: CAN1 SCE interrupt */ -#define STM32L4_IRQ_EXTI95 (STM32L4_IRQ_FIRST + 23) /* 23: EXTI Line[9:5] interrupts */ -#define STM32L4_IRQ_TIM1BRK (STM32L4_IRQ_FIRST + 24) /* 24: TIM1 Break interrupt */ -#define STM32L4_IRQ_TIM15 (STM32L4_IRQ_FIRST + 24) /* 24: TIM15 global interrupt */ -#define STM32L4_IRQ_TIM1UP (STM32L4_IRQ_FIRST + 25) /* 25: TIM1 Update interrupt */ -#define STM32L4_IRQ_TIM16 (STM32L4_IRQ_FIRST + 25) /* 25: TIM16 global interrupt */ -#define STM32L4_IRQ_TIM1TRGCOM (STM32L4_IRQ_FIRST + 26) /* 26: TIM1 Trigger and Commutation interrupts */ -#define STM32L4_IRQ_TIM17 (STM32L4_IRQ_FIRST + 26) /* 26: TIM17 global interrupt */ -#define STM32L4_IRQ_TIM1CC (STM32L4_IRQ_FIRST + 27) /* 27: TIM1 Capture Compare interrupt */ -#define STM32L4_IRQ_TIM2 (STM32L4_IRQ_FIRST + 28) /* 28: TIM2 global interrupt */ -#define STM32L4_IRQ_TIM3 (STM32L4_IRQ_FIRST + 29) /* 29: TIM3 global interrupt */ -#define STM32L4_IRQ_TIM4 (STM32L4_IRQ_FIRST + 30) /* 30: TIM4 global interrupt */ -#define STM32L4_IRQ_I2C1EV (STM32L4_IRQ_FIRST + 31) /* 31: I2C1 event interrupt */ -#define STM32L4_IRQ_I2C1ER (STM32L4_IRQ_FIRST + 32) /* 32: I2C1 error interrupt */ -#define STM32L4_IRQ_I2C2EV (STM32L4_IRQ_FIRST + 33) /* 33: I2C2 event interrupt */ -#define STM32L4_IRQ_I2C2ER (STM32L4_IRQ_FIRST + 34) /* 34: I2C2 error interrupt */ -#define STM32L4_IRQ_SPI1 (STM32L4_IRQ_FIRST + 35) /* 35: SPI1 global interrupt */ -#define STM32L4_IRQ_SPI2 (STM32L4_IRQ_FIRST + 36) /* 36: SPI2 global interrupt */ -#define STM32L4_IRQ_USART1 (STM32L4_IRQ_FIRST + 37) /* 37: USART1 global interrupt */ -#define STM32L4_IRQ_USART2 (STM32L4_IRQ_FIRST + 38) /* 38: USART2 global interrupt */ -#define STM32L4_IRQ_USART3 (STM32L4_IRQ_FIRST + 39) /* 39: USART3 global interrupt */ -#define STM32L4_IRQ_EXTI1510 (STM32L4_IRQ_FIRST + 40) /* 40: EXTI Line[15:10] interrupts */ -#define STM32L4_IRQ_RTCALRM (STM32L4_IRQ_FIRST + 41) /* 41: RTC alarm through EXTI line interrupt */ -#define STM32L4_IRQ_DFSDM3 (STM32L4_IRQ_FIRST + 42) /* 42: Digital Filter / Sigma Delta Modulator interrupt */ -#define STM32L4_IRQ_TIM8BRK (STM32L4_IRQ_FIRST + 43) /* 43: TIM8 Break interrupt */ -#define STM32L4_IRQ_TIM8UP (STM32L4_IRQ_FIRST + 44) /* 44: TIM8 Update interrupt */ -#define STM32L4_IRQ_TIM8TRGCOM (STM32L4_IRQ_FIRST + 45) /* 45: TIM8 Trigger and Commutation interrupts */ -#define STM32L4_IRQ_TIM8CC (STM32L4_IRQ_FIRST + 46) /* 46: TIM8 Capture Compare interrupt */ -#define STM32L4_IRQ_ADC3 (STM32L4_IRQ_FIRST + 47) /* 47: ADC3 global interrupt */ -#define STM32L4_IRQ_FSMC (STM32L4_IRQ_FIRST + 48) /* 48: FSMC global interrupt */ -#define STM32L4_IRQ_SDMMC1 (STM32L4_IRQ_FIRST + 49) /* 49: SDMMC1 global interrupt */ -#define STM32L4_IRQ_TIM5 (STM32L4_IRQ_FIRST + 50) /* 50: TIM5 global interrupt */ -#define STM32L4_IRQ_SPI3 (STM32L4_IRQ_FIRST + 51) /* 51: SPI3 global interrupt */ -#define STM32L4_IRQ_UART4 (STM32L4_IRQ_FIRST + 52) /* 52: UART4 global interrupt */ -#define STM32L4_IRQ_UART5 (STM32L4_IRQ_FIRST + 53) /* 53: UART5 global interrupt */ -#define STM32L4_IRQ_TIM6 (STM32L4_IRQ_FIRST + 54) /* 54: TIM6 global interrupt */ -#define STM32L4_IRQ_DAC (STM32L4_IRQ_FIRST + 54) /* 54: DAC1 and DAC2 underrun error interrupts */ -#define STM32L4_IRQ_TIM7 (STM32L4_IRQ_FIRST + 55) /* 55: TIM7 global interrupt */ -#define STM32L4_IRQ_DMA2CH1 (STM32L4_IRQ_FIRST + 56) /* 56: DMA2 Channel 1 global interrupt */ -#define STM32L4_IRQ_DMA2CH2 (STM32L4_IRQ_FIRST + 57) /* 57: DMA2 Channel 2 global interrupt */ -#define STM32L4_IRQ_DMA2CH3 (STM32L4_IRQ_FIRST + 58) /* 58: DMA2 Channel 3 global interrupt */ -#define STM32L4_IRQ_DMA2CH4 (STM32L4_IRQ_FIRST + 59) /* 59: DMA2 Channel 4 global interrupt */ -#define STM32L4_IRQ_DMA2CH5 (STM32L4_IRQ_FIRST + 60) /* 60: DMA2 Channel 5 global interrupt */ -#define STM32L4_IRQ_DFSDM0 (STM32L4_IRQ_FIRST + 61) /* 61: DFSDM0 global interrupt */ -#define STM32L4_IRQ_DFSDM1 (STM32L4_IRQ_FIRST + 62) /* 62: DFSDM1 global interrupt*/ -#define STM32L4_IRQ_DFSDM2 (STM32L4_IRQ_FIRST + 63) /* 63: DFSDM2 global interrupt */ -#define STM32L4_IRQ_COMP (STM32L4_IRQ_FIRST + 64) /* 64: COMP1/COMP2 interrupts */ -#define STM32L4_IRQ_LPTIM1 (STM32L4_IRQ_FIRST + 65) /* 65: LPTIM1 global interrupt */ -#define STM32L4_IRQ_LPTIM2 (STM32L4_IRQ_FIRST + 66) /* 66: LPTIM2 global interrupt */ -#define STM32L4_IRQ_OTGFS (STM32L4_IRQ_FIRST + 67) /* 67: USB On The Go FS global interrupt */ -#define STM32L4_IRQ_DMA2CH6 (STM32L4_IRQ_FIRST + 68) /* 68: DMA2 Channel 6 global interrupt */ -#define STM32L4_IRQ_DMA2CH7 (STM32L4_IRQ_FIRST + 69) /* 69: DMA2 Channel 7 global interrupt */ -#define STM32L4_IRQ_LPUART1 (STM32L4_IRQ_FIRST + 70) /* 70: Low power UART 1 global interrupt */ -#define STM32L4_IRQ_QUADSPI (STM32L4_IRQ_FIRST + 71) /* 71: QUADSPI global interrupt */ -#define STM32L4_IRQ_I2C3EV (STM32L4_IRQ_FIRST + 72) /* 72: I2C3 event interrupt */ -#define STM32L4_IRQ_I2C3ER (STM32L4_IRQ_FIRST + 73) /* 73: I2C3 error interrupt */ -#define STM32L4_IRQ_SAI1 (STM32L4_IRQ_FIRST + 74) /* 74: SAI1 global interrupt */ -#define STM32L4_IRQ_SAI2 (STM32L4_IRQ_FIRST + 75) /* 75: SAI2 global interrupt */ -#define STM32L4_IRQ_SWPMI1 (STM32L4_IRQ_FIRST + 76) /* 76: SWPMI1 global interrupt */ -#define STM32L4_IRQ_TSC (STM32L4_IRQ_FIRST + 77) /* 77: TSC global interrupt */ -#define STM32L4_IRQ_LCD (STM32L4_IRQ_FIRST + 78) /* 78: LCD global interrupt */ -#define STM32L4_IRQ_AES (STM32L4_IRQ_FIRST + 79) /* 79: AES crypto global interrupt */ -#define STM32L4_IRQ_RNG (STM32L4_IRQ_FIRST + 80) /* 80: RNG global interrupt */ -#define STM32L4_IRQ_FPU (STM32L4_IRQ_FIRST + 81) /* 81: FPU global interrupt */ +#define STM32_IRQ_WWDG (STM32_IRQ_FIRST + 0) /* 0: Window Watchdog interrupt */ +#define STM32_IRQ_PVD (STM32_IRQ_FIRST + 1) /* 1: PVD through EXTI Line detection interrupt */ +#define STM32_IRQ_TAMPER (STM32_IRQ_FIRST + 2) /* 2: Tamper and time stamp interrupts */ +#define STM32_IRQ_TIMESTAMP (STM32_IRQ_FIRST + 2) /* 2: Tamper and time stamp interrupts */ +#define STM32_IRQ_RTC_WKUP (STM32_IRQ_FIRST + 3) /* 3: RTC global interrupt */ +#define STM32_IRQ_FLASH (STM32_IRQ_FIRST + 4) /* 4: Flash global interrupt */ +#define STM32_IRQ_RCC (STM32_IRQ_FIRST + 5) /* 5: RCC global interrupt */ +#define STM32_IRQ_EXTI0 (STM32_IRQ_FIRST + 6) /* 6: EXTI Line 0 interrupt */ +#define STM32_IRQ_EXTI1 (STM32_IRQ_FIRST + 7) /* 7: EXTI Line 1 interrupt */ +#define STM32_IRQ_EXTI2 (STM32_IRQ_FIRST + 8) /* 8: EXTI Line 2 interrupt */ +#define STM32_IRQ_EXTI3 (STM32_IRQ_FIRST + 9) /* 9: EXTI Line 3 interrupt */ +#define STM32_IRQ_EXTI4 (STM32_IRQ_FIRST + 10) /* 10: EXTI Line 4 interrupt */ +#define STM32_IRQ_DMA1CH1 (STM32_IRQ_FIRST + 11) /* 11: DMA1 Channel 1 global interrupt */ +#define STM32_IRQ_DMA1CH2 (STM32_IRQ_FIRST + 12) /* 12: DMA1 Channel 2 global interrupt */ +#define STM32_IRQ_DMA1CH3 (STM32_IRQ_FIRST + 13) /* 13: DMA1 Channel 3 global interrupt */ +#define STM32_IRQ_DMA1CH4 (STM32_IRQ_FIRST + 14) /* 14: DMA1 Channel 4 global interrupt */ +#define STM32_IRQ_DMA1CH5 (STM32_IRQ_FIRST + 15) /* 15: DMA1 Channel 5 global interrupt */ +#define STM32_IRQ_DMA1CH6 (STM32_IRQ_FIRST + 16) /* 16: DMA1 Channel 6 global interrupt */ +#define STM32_IRQ_DMA1CH7 (STM32_IRQ_FIRST + 17) /* 17: DMA1 Channel 7 global interrupt */ +#define STM32_IRQ_ADC12 (STM32_IRQ_FIRST + 18) /* 18: ADC1 and ADC2 global interrupt */ +#define STM32_IRQ_CAN1TX (STM32_IRQ_FIRST + 19) /* 19: CAN1 TX interrupts */ +#define STM32_IRQ_CAN1RX0 (STM32_IRQ_FIRST + 20) /* 20: CAN1 RX0 interrupts */ +#define STM32_IRQ_CAN1RX1 (STM32_IRQ_FIRST + 21) /* 21: CAN1 RX1 interrupt */ +#define STM32_IRQ_CAN1SCE (STM32_IRQ_FIRST + 22) /* 22: CAN1 SCE interrupt */ +#define STM32_IRQ_EXTI95 (STM32_IRQ_FIRST + 23) /* 23: EXTI Line[9:5] interrupts */ +#define STM32_IRQ_TIM1BRK (STM32_IRQ_FIRST + 24) /* 24: TIM1 Break interrupt */ +#define STM32_IRQ_TIM15 (STM32_IRQ_FIRST + 24) /* 24: TIM15 global interrupt */ +#define STM32_IRQ_TIM1UP (STM32_IRQ_FIRST + 25) /* 25: TIM1 Update interrupt */ +#define STM32_IRQ_TIM16 (STM32_IRQ_FIRST + 25) /* 25: TIM16 global interrupt */ +#define STM32_IRQ_TIM1TRGCOM (STM32_IRQ_FIRST + 26) /* 26: TIM1 Trigger and Commutation interrupts */ +#define STM32_IRQ_TIM17 (STM32_IRQ_FIRST + 26) /* 26: TIM17 global interrupt */ +#define STM32_IRQ_TIM1CC (STM32_IRQ_FIRST + 27) /* 27: TIM1 Capture Compare interrupt */ +#define STM32_IRQ_TIM2 (STM32_IRQ_FIRST + 28) /* 28: TIM2 global interrupt */ +#define STM32_IRQ_TIM3 (STM32_IRQ_FIRST + 29) /* 29: TIM3 global interrupt */ +#define STM32_IRQ_TIM4 (STM32_IRQ_FIRST + 30) /* 30: TIM4 global interrupt */ +#define STM32_IRQ_I2C1EV (STM32_IRQ_FIRST + 31) /* 31: I2C1 event interrupt */ +#define STM32_IRQ_I2C1ER (STM32_IRQ_FIRST + 32) /* 32: I2C1 error interrupt */ +#define STM32_IRQ_I2C2EV (STM32_IRQ_FIRST + 33) /* 33: I2C2 event interrupt */ +#define STM32_IRQ_I2C2ER (STM32_IRQ_FIRST + 34) /* 34: I2C2 error interrupt */ +#define STM32_IRQ_SPI1 (STM32_IRQ_FIRST + 35) /* 35: SPI1 global interrupt */ +#define STM32_IRQ_SPI2 (STM32_IRQ_FIRST + 36) /* 36: SPI2 global interrupt */ +#define STM32_IRQ_USART1 (STM32_IRQ_FIRST + 37) /* 37: USART1 global interrupt */ +#define STM32_IRQ_USART2 (STM32_IRQ_FIRST + 38) /* 38: USART2 global interrupt */ +#define STM32_IRQ_USART3 (STM32_IRQ_FIRST + 39) /* 39: USART3 global interrupt */ +#define STM32_IRQ_EXTI1510 (STM32_IRQ_FIRST + 40) /* 40: EXTI Line[15:10] interrupts */ +#define STM32_IRQ_RTCALRM (STM32_IRQ_FIRST + 41) /* 41: RTC alarm through EXTI line interrupt */ +#define STM32_IRQ_DFSDM3 (STM32_IRQ_FIRST + 42) /* 42: Digital Filter / Sigma Delta Modulator interrupt */ +#define STM32_IRQ_TIM8BRK (STM32_IRQ_FIRST + 43) /* 43: TIM8 Break interrupt */ +#define STM32_IRQ_TIM8UP (STM32_IRQ_FIRST + 44) /* 44: TIM8 Update interrupt */ +#define STM32_IRQ_TIM8TRGCOM (STM32_IRQ_FIRST + 45) /* 45: TIM8 Trigger and Commutation interrupts */ +#define STM32_IRQ_TIM8CC (STM32_IRQ_FIRST + 46) /* 46: TIM8 Capture Compare interrupt */ +#define STM32_IRQ_ADC3 (STM32_IRQ_FIRST + 47) /* 47: ADC3 global interrupt */ +#define STM32_IRQ_FSMC (STM32_IRQ_FIRST + 48) /* 48: FSMC global interrupt */ +#define STM32_IRQ_SDMMC1 (STM32_IRQ_FIRST + 49) /* 49: SDMMC1 global interrupt */ +#define STM32_IRQ_TIM5 (STM32_IRQ_FIRST + 50) /* 50: TIM5 global interrupt */ +#define STM32_IRQ_SPI3 (STM32_IRQ_FIRST + 51) /* 51: SPI3 global interrupt */ +#define STM32_IRQ_UART4 (STM32_IRQ_FIRST + 52) /* 52: UART4 global interrupt */ +#define STM32_IRQ_UART5 (STM32_IRQ_FIRST + 53) /* 53: UART5 global interrupt */ +#define STM32_IRQ_TIM6 (STM32_IRQ_FIRST + 54) /* 54: TIM6 global interrupt */ +#define STM32_IRQ_DAC (STM32_IRQ_FIRST + 54) /* 54: DAC1 and DAC2 underrun error interrupts */ +#define STM32_IRQ_TIM7 (STM32_IRQ_FIRST + 55) /* 55: TIM7 global interrupt */ +#define STM32_IRQ_DMA2CH1 (STM32_IRQ_FIRST + 56) /* 56: DMA2 Channel 1 global interrupt */ +#define STM32_IRQ_DMA2CH2 (STM32_IRQ_FIRST + 57) /* 57: DMA2 Channel 2 global interrupt */ +#define STM32_IRQ_DMA2CH3 (STM32_IRQ_FIRST + 58) /* 58: DMA2 Channel 3 global interrupt */ +#define STM32_IRQ_DMA2CH4 (STM32_IRQ_FIRST + 59) /* 59: DMA2 Channel 4 global interrupt */ +#define STM32_IRQ_DMA2CH5 (STM32_IRQ_FIRST + 60) /* 60: DMA2 Channel 5 global interrupt */ +#define STM32_IRQ_DFSDM0 (STM32_IRQ_FIRST + 61) /* 61: DFSDM0 global interrupt */ +#define STM32_IRQ_DFSDM1 (STM32_IRQ_FIRST + 62) /* 62: DFSDM1 global interrupt*/ +#define STM32_IRQ_DFSDM2 (STM32_IRQ_FIRST + 63) /* 63: DFSDM2 global interrupt */ +#define STM32_IRQ_COMP (STM32_IRQ_FIRST + 64) /* 64: COMP1/COMP2 interrupts */ +#define STM32_IRQ_LPTIM1 (STM32_IRQ_FIRST + 65) /* 65: LPTIM1 global interrupt */ +#define STM32_IRQ_LPTIM2 (STM32_IRQ_FIRST + 66) /* 66: LPTIM2 global interrupt */ +#define STM32_IRQ_OTGFS (STM32_IRQ_FIRST + 67) /* 67: USB On The Go FS global interrupt */ +#define STM32_IRQ_DMA2CH6 (STM32_IRQ_FIRST + 68) /* 68: DMA2 Channel 6 global interrupt */ +#define STM32_IRQ_DMA2CH7 (STM32_IRQ_FIRST + 69) /* 69: DMA2 Channel 7 global interrupt */ +#define STM32_IRQ_LPUART1 (STM32_IRQ_FIRST + 70) /* 70: Low power UART 1 global interrupt */ +#define STM32_IRQ_QUADSPI (STM32_IRQ_FIRST + 71) /* 71: QUADSPI global interrupt */ +#define STM32_IRQ_I2C3EV (STM32_IRQ_FIRST + 72) /* 72: I2C3 event interrupt */ +#define STM32_IRQ_I2C3ER (STM32_IRQ_FIRST + 73) /* 73: I2C3 error interrupt */ +#define STM32_IRQ_SAI1 (STM32_IRQ_FIRST + 74) /* 74: SAI1 global interrupt */ +#define STM32_IRQ_SAI2 (STM32_IRQ_FIRST + 75) /* 75: SAI2 global interrupt */ +#define STM32_IRQ_SWPMI1 (STM32_IRQ_FIRST + 76) /* 76: SWPMI1 global interrupt */ +#define STM32_IRQ_TSC (STM32_IRQ_FIRST + 77) /* 77: TSC global interrupt */ +#define STM32_IRQ_LCD (STM32_IRQ_FIRST + 78) /* 78: LCD global interrupt */ +#define STM32_IRQ_AES (STM32_IRQ_FIRST + 79) /* 79: AES crypto global interrupt */ +#define STM32_IRQ_RNG (STM32_IRQ_FIRST + 80) /* 80: RNG global interrupt */ +#define STM32_IRQ_FPU (STM32_IRQ_FIRST + 81) /* 81: FPU global interrupt */ /* STM32L496xx/4A6xx only: */ -#define STM32L4_IRQ_HASH_CRS (STM32L4_IRQ_FIRST + 82) /* 82: HASH and CRS global interrupt */ -#define STM32L4_IRQ_I2C4EV (STM32L4_IRQ_FIRST + 83) /* 83: I2C4 event interrupt */ -#define STM32L4_IRQ_I2C4ER (STM32L4_IRQ_FIRST + 84) /* 84: I2C4 error interrupt */ -#define STM32L4_IRQ_DCMI (STM32L4_IRQ_FIRST + 85) /* 85: DCMI global interrupt */ -#define STM32L4_IRQ_CAN2TX (STM32L4_IRQ_FIRST + 86) /* 86: CAN2 TX interrupts */ -#define STM32L4_IRQ_CAN2RX0 (STM32L4_IRQ_FIRST + 87) /* 87: CAN2 RX0 interrupts */ -#define STM32L4_IRQ_CAN2RX1 (STM32L4_IRQ_FIRST + 88) /* 88: CAN2 RX1 interrupt */ -#define STM32L4_IRQ_CAN2SCE (STM32L4_IRQ_FIRST + 89) /* 89: CAN2 SCE interrupt */ -#define STM32L4_IRQ_DMA2D (STM32L4_IRQ_FIRST + 90) /* 90: DMA2D global interrupt */ - -#if defined(CONFIG_STM32L4_STM32L476XX) || defined(CONFIG_STM32L4_STM32L486XX) -# define STM32L4_IRQ_NEXTINTS 82 -#elif defined(CONFIG_STM32L4_STM32L496XX) -# define STM32L4_IRQ_NEXTINTS 91 +#define STM32_IRQ_HASH_CRS (STM32_IRQ_FIRST + 82) /* 82: HASH and CRS global interrupt */ +#define STM32_IRQ_I2C4EV (STM32_IRQ_FIRST + 83) /* 83: I2C4 event interrupt */ +#define STM32_IRQ_I2C4ER (STM32_IRQ_FIRST + 84) /* 84: I2C4 error interrupt */ +#define STM32_IRQ_DCMI (STM32_IRQ_FIRST + 85) /* 85: DCMI global interrupt */ +#define STM32_IRQ_CAN2TX (STM32_IRQ_FIRST + 86) /* 86: CAN2 TX interrupts */ +#define STM32_IRQ_CAN2RX0 (STM32_IRQ_FIRST + 87) /* 87: CAN2 RX0 interrupts */ +#define STM32_IRQ_CAN2RX1 (STM32_IRQ_FIRST + 88) /* 88: CAN2 RX1 interrupt */ +#define STM32_IRQ_CAN2SCE (STM32_IRQ_FIRST + 89) /* 89: CAN2 SCE interrupt */ +#define STM32_IRQ_DMA2D (STM32_IRQ_FIRST + 90) /* 90: DMA2D global interrupt */ + +#if defined(CONFIG_STM32_STM32L476XX) || defined(CONFIG_STM32_STM32L486XX) +# define STM32_IRQ_NEXTINTS 82 +#elif defined(CONFIG_STM32_STM32L496XX) +# define STM32_IRQ_NEXTINTS 91 #else # error "Unsupported STM32L4 chip" #endif /* EXTI interrupts (Do not use IRQ numbers) */ -#define NR_IRQS (STM32L4_IRQ_FIRST + STM32L4_IRQ_NEXTINTS) +#define NR_IRQS (STM32_IRQ_FIRST + STM32_IRQ_NEXTINTS) /**************************************************************************** * Public Types diff --git a/arch/arm/include/stm32l4/stm32l4xrxx_irq.h b/arch/arm/include/stm32l4/stm32l4xrxx_irq.h index 803bf8dc01240..ec9f7db1f952b 100644 --- a/arch/arm/include/stm32l4/stm32l4xrxx_irq.h +++ b/arch/arm/include/stm32l4/stm32l4xrxx_irq.h @@ -48,109 +48,109 @@ * External interrupts (vectors >= 16) */ -#define STM32L4_IRQ_WWDG (STM32L4_IRQ_FIRST + 0) /* 0: Window Watchdog interrupt */ -#define STM32L4_IRQ_PVD (STM32L4_IRQ_FIRST + 1) /* 1: PVD through EXTI Line detection interrupt */ -#define STM32L4_IRQ_TAMPER (STM32L4_IRQ_FIRST + 2) /* 2: Tamper and time stamp interrupts */ -#define STM32L4_IRQ_TIMESTAMP (STM32L4_IRQ_FIRST + 2) /* 2: Tamper and time stamp interrupts */ -#define STM32L4_IRQ_RTC_WKUP (STM32L4_IRQ_FIRST + 3) /* 3: RTC global interrupt */ -#define STM32L4_IRQ_FLASH (STM32L4_IRQ_FIRST + 4) /* 4: Flash global interrupt */ -#define STM32L4_IRQ_RCC (STM32L4_IRQ_FIRST + 5) /* 5: RCC global interrupt */ -#define STM32L4_IRQ_EXTI0 (STM32L4_IRQ_FIRST + 6) /* 6: EXTI Line 0 interrupt */ -#define STM32L4_IRQ_EXTI1 (STM32L4_IRQ_FIRST + 7) /* 7: EXTI Line 1 interrupt */ -#define STM32L4_IRQ_EXTI2 (STM32L4_IRQ_FIRST + 8) /* 8: EXTI Line 2 interrupt */ -#define STM32L4_IRQ_EXTI3 (STM32L4_IRQ_FIRST + 9) /* 9: EXTI Line 3 interrupt */ -#define STM32L4_IRQ_EXTI4 (STM32L4_IRQ_FIRST + 10) /* 10: EXTI Line 4 interrupt */ -#define STM32L4_IRQ_DMA1CH1 (STM32L4_IRQ_FIRST + 11) /* 11: DMA1 Channel 1 global interrupt */ -#define STM32L4_IRQ_DMA1CH2 (STM32L4_IRQ_FIRST + 12) /* 12: DMA1 Channel 2 global interrupt */ -#define STM32L4_IRQ_DMA1CH3 (STM32L4_IRQ_FIRST + 13) /* 13: DMA1 Channel 3 global interrupt */ -#define STM32L4_IRQ_DMA1CH4 (STM32L4_IRQ_FIRST + 14) /* 14: DMA1 Channel 4 global interrupt */ -#define STM32L4_IRQ_DMA1CH5 (STM32L4_IRQ_FIRST + 15) /* 15: DMA1 Channel 5 global interrupt */ -#define STM32L4_IRQ_DMA1CH6 (STM32L4_IRQ_FIRST + 16) /* 16: DMA1 Channel 6 global interrupt */ -#define STM32L4_IRQ_DMA1CH7 (STM32L4_IRQ_FIRST + 17) /* 17: DMA1 Channel 7 global interrupt */ -#define STM32L4_IRQ_ADC1 (STM32L4_IRQ_FIRST + 18) /* 18: ADC1 global interrupt */ -#define STM32L4_IRQ_CAN1TX (STM32L4_IRQ_FIRST + 19) /* 19: CAN1 TX interrupts */ -#define STM32L4_IRQ_CAN1RX0 (STM32L4_IRQ_FIRST + 20) /* 20: CAN1 RX0 interrupts */ -#define STM32L4_IRQ_CAN1RX1 (STM32L4_IRQ_FIRST + 21) /* 21: CAN1 RX1 interrupt */ -#define STM32L4_IRQ_CAN1SCE (STM32L4_IRQ_FIRST + 22) /* 22: CAN1 SCE interrupt */ -#define STM32L4_IRQ_EXTI95 (STM32L4_IRQ_FIRST + 23) /* 23: EXTI Line[9:5] interrupts */ -#define STM32L4_IRQ_TIM1BRK (STM32L4_IRQ_FIRST + 24) /* 24: TIM1 Break interrupt */ -#define STM32L4_IRQ_TIM15 (STM32L4_IRQ_FIRST + 24) /* 24: TIM15 global interrupt */ -#define STM32L4_IRQ_TIM1UP (STM32L4_IRQ_FIRST + 25) /* 25: TIM1 Update interrupt */ -#define STM32L4_IRQ_TIM16 (STM32L4_IRQ_FIRST + 25) /* 25: TIM16 global interrupt */ -#define STM32L4_IRQ_TIM1TRGCOM (STM32L4_IRQ_FIRST + 26) /* 26: TIM1 Trigger and Commutation interrupts */ -#define STM32L4_IRQ_TIM17 (STM32L4_IRQ_FIRST + 26) /* 26: TIM17 global interrupt */ -#define STM32L4_IRQ_TIM1CC (STM32L4_IRQ_FIRST + 27) /* 27: TIM1 Capture Compare interrupt */ -#define STM32L4_IRQ_TIM2 (STM32L4_IRQ_FIRST + 28) /* 28: TIM2 global interrupt */ -#define STM32L4_IRQ_TIM3 (STM32L4_IRQ_FIRST + 29) /* 29: TIM3 global interrupt */ -#define STM32L4_IRQ_TIM4 (STM32L4_IRQ_FIRST + 30) /* 30: TIM4 global interrupt */ -#define STM32L4_IRQ_I2C1EV (STM32L4_IRQ_FIRST + 31) /* 31: I2C1 event interrupt */ -#define STM32L4_IRQ_I2C1ER (STM32L4_IRQ_FIRST + 32) /* 32: I2C1 error interrupt */ -#define STM32L4_IRQ_I2C2EV (STM32L4_IRQ_FIRST + 33) /* 33: I2C2 event interrupt */ -#define STM32L4_IRQ_I2C2ER (STM32L4_IRQ_FIRST + 34) /* 34: I2C2 error interrupt */ -#define STM32L4_IRQ_SPI1 (STM32L4_IRQ_FIRST + 35) /* 35: SPI1 global interrupt */ -#define STM32L4_IRQ_SPI2 (STM32L4_IRQ_FIRST + 36) /* 36: SPI2 global interrupt */ -#define STM32L4_IRQ_USART1 (STM32L4_IRQ_FIRST + 37) /* 37: USART1 global interrupt */ -#define STM32L4_IRQ_USART2 (STM32L4_IRQ_FIRST + 38) /* 38: USART2 global interrupt */ -#define STM32L4_IRQ_USART3 (STM32L4_IRQ_FIRST + 39) /* 39: USART3 global interrupt */ -#define STM32L4_IRQ_EXTI1510 (STM32L4_IRQ_FIRST + 40) /* 40: EXTI Line[15:10] interrupts */ -#define STM32L4_IRQ_RTCALRM (STM32L4_IRQ_FIRST + 41) /* 41: RTC alarm through EXTI line interrupt */ -#define STM32L4_IRQ_DFSDM3 (STM32L4_IRQ_FIRST + 42) /* 42: Digital Filter / Sigma Delta Modulator interrupt */ -#define STM32L4_IRQ_TIM8BRK (STM32L4_IRQ_FIRST + 43) /* 43: TIM8 Break interrupt */ -#define STM32L4_IRQ_TIM8UP (STM32L4_IRQ_FIRST + 44) /* 44: TIM8 Update interrupt */ -#define STM32L4_IRQ_TIM8TRGCOM (STM32L4_IRQ_FIRST + 45) /* 45: TIM8 Trigger and Commutation interrupts */ -#define STM32L4_IRQ_TIM8CC (STM32L4_IRQ_FIRST + 46) /* 46: TIM8 Capture Compare interrupt */ - /* Reserved 47: ADC3 global interrupt */ -#define STM32L4_IRQ_FSMC (STM32L4_IRQ_FIRST + 48) /* 48: FSMC global interrupt */ -#define STM32L4_IRQ_SDMMC1 (STM32L4_IRQ_FIRST + 49) /* 49: SDMMC1 global interrupt */ -#define STM32L4_IRQ_TIM5 (STM32L4_IRQ_FIRST + 50) /* 50: TIM5 global interrupt */ -#define STM32L4_IRQ_SPI3 (STM32L4_IRQ_FIRST + 51) /* 51: SPI3 global interrupt */ -#define STM32L4_IRQ_UART4 (STM32L4_IRQ_FIRST + 52) /* 52: UART4 global interrupt */ -#define STM32L4_IRQ_UART5 (STM32L4_IRQ_FIRST + 53) /* 53: UART5 global interrupt */ -#define STM32L4_IRQ_TIM6 (STM32L4_IRQ_FIRST + 54) /* 54: TIM6 global interrupt */ -#define STM32L4_IRQ_DAC (STM32L4_IRQ_FIRST + 54) /* 54: DAC1 and DAC2 underrun error interrupts */ -#define STM32L4_IRQ_TIM7 (STM32L4_IRQ_FIRST + 55) /* 55: TIM7 global interrupt */ -#define STM32L4_IRQ_DMA2CH1 (STM32L4_IRQ_FIRST + 56) /* 56: DMA2 Channel 1 global interrupt */ -#define STM32L4_IRQ_DMA2CH2 (STM32L4_IRQ_FIRST + 57) /* 57: DMA2 Channel 2 global interrupt */ -#define STM32L4_IRQ_DMA2CH3 (STM32L4_IRQ_FIRST + 58) /* 58: DMA2 Channel 3 global interrupt */ -#define STM32L4_IRQ_DMA2CH4 (STM32L4_IRQ_FIRST + 59) /* 59: DMA2 Channel 4 global interrupt */ -#define STM32L4_IRQ_DMA2CH5 (STM32L4_IRQ_FIRST + 60) /* 60: DMA2 Channel 5 global interrupt */ -#define STM32L4_IRQ_DFSDM0 (STM32L4_IRQ_FIRST + 61) /* 61: DFSDM0 global interrupt */ -#define STM32L4_IRQ_DFSDM1 (STM32L4_IRQ_FIRST + 62) /* 62: DFSDM1 global interrupt*/ -#define STM32L4_IRQ_DFSDM2 (STM32L4_IRQ_FIRST + 63) /* 63: DFSDM2 global interrupt */ -#define STM32L4_IRQ_COMP (STM32L4_IRQ_FIRST + 64) /* 64: COMP1/COMP2 interrupts */ -#define STM32L4_IRQ_LPTIM1 (STM32L4_IRQ_FIRST + 65) /* 65: LPTIM1 global interrupt */ -#define STM32L4_IRQ_LPTIM2 (STM32L4_IRQ_FIRST + 66) /* 66: LPTIM2 global interrupt */ -#define STM32L4_IRQ_OTGFS (STM32L4_IRQ_FIRST + 67) /* 67: USB On The Go FS global interrupt */ -#define STM32L4_IRQ_DMA2CH6 (STM32L4_IRQ_FIRST + 68) /* 68: DMA2 Channel 6 global interrupt */ -#define STM32L4_IRQ_DMA2CH7 (STM32L4_IRQ_FIRST + 69) /* 69: DMA2 Channel 7 global interrupt */ -#define STM32L4_IRQ_LPUART1 (STM32L4_IRQ_FIRST + 70) /* 70: Low power UART 1 global interrupt */ -#define STM32L4_IRQ_OCTOSPI1 (STM32L4_IRQ_FIRST + 71) /* 71: OCTOSPI1 global interrupt */ -#define STM32L4_IRQ_I2C3EV (STM32L4_IRQ_FIRST + 72) /* 72: I2C3 event interrupt */ -#define STM32L4_IRQ_I2C3ER (STM32L4_IRQ_FIRST + 73) /* 73: I2C3 error interrupt */ -#define STM32L4_IRQ_SAI1 (STM32L4_IRQ_FIRST + 74) /* 74: SAI1 global interrupt */ -#define STM32L4_IRQ_SAI2 (STM32L4_IRQ_FIRST + 75) /* 75: SAI2 global interrupt */ -#define STM32L4_IRQ_OCTOSPI2 (STM32L4_IRQ_FIRST + 76) /* 76: OCTOSPI2 global interrupt */ -#define STM32L4_IRQ_TSC (STM32L4_IRQ_FIRST + 77) /* 77: TSC global interrupt */ -#define STM32L4_IRQ_DSIHSOT (STM32L4_IRQ_FIRST + 78) /* 78: DSI global interrupt */ -#define STM32L4_IRQ_AES (STM32L4_IRQ_FIRST + 79) /* 79: AES crypto global interrupt */ -#define STM32L4_IRQ_RNG (STM32L4_IRQ_FIRST + 80) /* 80: RNG global interrupt */ -#define STM32L4_IRQ_FPU (STM32L4_IRQ_FIRST + 81) /* 81: FPU global interrupt */ -#define STM32L4_IRQ_HASH_CRS (STM32L4_IRQ_FIRST + 82) /* 82: HASH and CRS global interrupt */ -#define STM32L4_IRQ_I2C4EV (STM32L4_IRQ_FIRST + 83) /* 83: I2C4 event interrupt */ -#define STM32L4_IRQ_I2C4ER (STM32L4_IRQ_FIRST + 84) /* 84: I2C4 error interrupt */ -#define STM32L4_IRQ_DCMI (STM32L4_IRQ_FIRST + 85) /* 85: DCMI global interrupt */ - /* Reserved 86-89: CAN2 */ -#define STM32L4_IRQ_DMA2D (STM32L4_IRQ_FIRST + 90) /* 90: DMA2D global interrupt */ -#define STM32L4_IRQ_LCD_TFT (STM32L4_IRQ_FIRST + 91) /* 91: LTDC global interrupt */ -#define STM32L4_IRQ_LCD_TFT_ER (STM32L4_IRQ_FIRST + 92) /* 92: LTDC global error interrupt */ -#define STM32L4_IRQ_GFXMMU (STM32L4_IRQ_FIRST + 93) /* 93: GFXMMU global error interrupt */ -#define STM32L4_IRQ_DMAMUX1_OVR (STM32L4_IRQ_FIRST + 94) /* 94: DMAMUX overrun interrupt */ - -#define STM32L4_IRQ_NEXTINTS 95 +#define STM32_IRQ_WWDG (STM32_IRQ_FIRST + 0) /* 0: Window Watchdog interrupt */ +#define STM32_IRQ_PVD (STM32_IRQ_FIRST + 1) /* 1: PVD through EXTI Line detection interrupt */ +#define STM32_IRQ_TAMPER (STM32_IRQ_FIRST + 2) /* 2: Tamper and time stamp interrupts */ +#define STM32_IRQ_TIMESTAMP (STM32_IRQ_FIRST + 2) /* 2: Tamper and time stamp interrupts */ +#define STM32_IRQ_RTC_WKUP (STM32_IRQ_FIRST + 3) /* 3: RTC global interrupt */ +#define STM32_IRQ_FLASH (STM32_IRQ_FIRST + 4) /* 4: Flash global interrupt */ +#define STM32_IRQ_RCC (STM32_IRQ_FIRST + 5) /* 5: RCC global interrupt */ +#define STM32_IRQ_EXTI0 (STM32_IRQ_FIRST + 6) /* 6: EXTI Line 0 interrupt */ +#define STM32_IRQ_EXTI1 (STM32_IRQ_FIRST + 7) /* 7: EXTI Line 1 interrupt */ +#define STM32_IRQ_EXTI2 (STM32_IRQ_FIRST + 8) /* 8: EXTI Line 2 interrupt */ +#define STM32_IRQ_EXTI3 (STM32_IRQ_FIRST + 9) /* 9: EXTI Line 3 interrupt */ +#define STM32_IRQ_EXTI4 (STM32_IRQ_FIRST + 10) /* 10: EXTI Line 4 interrupt */ +#define STM32_IRQ_DMA1CH1 (STM32_IRQ_FIRST + 11) /* 11: DMA1 Channel 1 global interrupt */ +#define STM32_IRQ_DMA1CH2 (STM32_IRQ_FIRST + 12) /* 12: DMA1 Channel 2 global interrupt */ +#define STM32_IRQ_DMA1CH3 (STM32_IRQ_FIRST + 13) /* 13: DMA1 Channel 3 global interrupt */ +#define STM32_IRQ_DMA1CH4 (STM32_IRQ_FIRST + 14) /* 14: DMA1 Channel 4 global interrupt */ +#define STM32_IRQ_DMA1CH5 (STM32_IRQ_FIRST + 15) /* 15: DMA1 Channel 5 global interrupt */ +#define STM32_IRQ_DMA1CH6 (STM32_IRQ_FIRST + 16) /* 16: DMA1 Channel 6 global interrupt */ +#define STM32_IRQ_DMA1CH7 (STM32_IRQ_FIRST + 17) /* 17: DMA1 Channel 7 global interrupt */ +#define STM32_IRQ_ADC1 (STM32_IRQ_FIRST + 18) /* 18: ADC1 global interrupt */ +#define STM32_IRQ_CAN1TX (STM32_IRQ_FIRST + 19) /* 19: CAN1 TX interrupts */ +#define STM32_IRQ_CAN1RX0 (STM32_IRQ_FIRST + 20) /* 20: CAN1 RX0 interrupts */ +#define STM32_IRQ_CAN1RX1 (STM32_IRQ_FIRST + 21) /* 21: CAN1 RX1 interrupt */ +#define STM32_IRQ_CAN1SCE (STM32_IRQ_FIRST + 22) /* 22: CAN1 SCE interrupt */ +#define STM32_IRQ_EXTI95 (STM32_IRQ_FIRST + 23) /* 23: EXTI Line[9:5] interrupts */ +#define STM32_IRQ_TIM1BRK (STM32_IRQ_FIRST + 24) /* 24: TIM1 Break interrupt */ +#define STM32_IRQ_TIM15 (STM32_IRQ_FIRST + 24) /* 24: TIM15 global interrupt */ +#define STM32_IRQ_TIM1UP (STM32_IRQ_FIRST + 25) /* 25: TIM1 Update interrupt */ +#define STM32_IRQ_TIM16 (STM32_IRQ_FIRST + 25) /* 25: TIM16 global interrupt */ +#define STM32_IRQ_TIM1TRGCOM (STM32_IRQ_FIRST + 26) /* 26: TIM1 Trigger and Commutation interrupts */ +#define STM32_IRQ_TIM17 (STM32_IRQ_FIRST + 26) /* 26: TIM17 global interrupt */ +#define STM32_IRQ_TIM1CC (STM32_IRQ_FIRST + 27) /* 27: TIM1 Capture Compare interrupt */ +#define STM32_IRQ_TIM2 (STM32_IRQ_FIRST + 28) /* 28: TIM2 global interrupt */ +#define STM32_IRQ_TIM3 (STM32_IRQ_FIRST + 29) /* 29: TIM3 global interrupt */ +#define STM32_IRQ_TIM4 (STM32_IRQ_FIRST + 30) /* 30: TIM4 global interrupt */ +#define STM32_IRQ_I2C1EV (STM32_IRQ_FIRST + 31) /* 31: I2C1 event interrupt */ +#define STM32_IRQ_I2C1ER (STM32_IRQ_FIRST + 32) /* 32: I2C1 error interrupt */ +#define STM32_IRQ_I2C2EV (STM32_IRQ_FIRST + 33) /* 33: I2C2 event interrupt */ +#define STM32_IRQ_I2C2ER (STM32_IRQ_FIRST + 34) /* 34: I2C2 error interrupt */ +#define STM32_IRQ_SPI1 (STM32_IRQ_FIRST + 35) /* 35: SPI1 global interrupt */ +#define STM32_IRQ_SPI2 (STM32_IRQ_FIRST + 36) /* 36: SPI2 global interrupt */ +#define STM32_IRQ_USART1 (STM32_IRQ_FIRST + 37) /* 37: USART1 global interrupt */ +#define STM32_IRQ_USART2 (STM32_IRQ_FIRST + 38) /* 38: USART2 global interrupt */ +#define STM32_IRQ_USART3 (STM32_IRQ_FIRST + 39) /* 39: USART3 global interrupt */ +#define STM32_IRQ_EXTI1510 (STM32_IRQ_FIRST + 40) /* 40: EXTI Line[15:10] interrupts */ +#define STM32_IRQ_RTCALRM (STM32_IRQ_FIRST + 41) /* 41: RTC alarm through EXTI line interrupt */ +#define STM32_IRQ_DFSDM3 (STM32_IRQ_FIRST + 42) /* 42: Digital Filter / Sigma Delta Modulator interrupt */ +#define STM32_IRQ_TIM8BRK (STM32_IRQ_FIRST + 43) /* 43: TIM8 Break interrupt */ +#define STM32_IRQ_TIM8UP (STM32_IRQ_FIRST + 44) /* 44: TIM8 Update interrupt */ +#define STM32_IRQ_TIM8TRGCOM (STM32_IRQ_FIRST + 45) /* 45: TIM8 Trigger and Commutation interrupts */ +#define STM32_IRQ_TIM8CC (STM32_IRQ_FIRST + 46) /* 46: TIM8 Capture Compare interrupt */ + /* Reserved 47: ADC3 global interrupt */ +#define STM32_IRQ_FSMC (STM32_IRQ_FIRST + 48) /* 48: FSMC global interrupt */ +#define STM32_IRQ_SDMMC1 (STM32_IRQ_FIRST + 49) /* 49: SDMMC1 global interrupt */ +#define STM32_IRQ_TIM5 (STM32_IRQ_FIRST + 50) /* 50: TIM5 global interrupt */ +#define STM32_IRQ_SPI3 (STM32_IRQ_FIRST + 51) /* 51: SPI3 global interrupt */ +#define STM32_IRQ_UART4 (STM32_IRQ_FIRST + 52) /* 52: UART4 global interrupt */ +#define STM32_IRQ_UART5 (STM32_IRQ_FIRST + 53) /* 53: UART5 global interrupt */ +#define STM32_IRQ_TIM6 (STM32_IRQ_FIRST + 54) /* 54: TIM6 global interrupt */ +#define STM32_IRQ_DAC (STM32_IRQ_FIRST + 54) /* 54: DAC1 and DAC2 underrun error interrupts */ +#define STM32_IRQ_TIM7 (STM32_IRQ_FIRST + 55) /* 55: TIM7 global interrupt */ +#define STM32_IRQ_DMA2CH1 (STM32_IRQ_FIRST + 56) /* 56: DMA2 Channel 1 global interrupt */ +#define STM32_IRQ_DMA2CH2 (STM32_IRQ_FIRST + 57) /* 57: DMA2 Channel 2 global interrupt */ +#define STM32_IRQ_DMA2CH3 (STM32_IRQ_FIRST + 58) /* 58: DMA2 Channel 3 global interrupt */ +#define STM32_IRQ_DMA2CH4 (STM32_IRQ_FIRST + 59) /* 59: DMA2 Channel 4 global interrupt */ +#define STM32_IRQ_DMA2CH5 (STM32_IRQ_FIRST + 60) /* 60: DMA2 Channel 5 global interrupt */ +#define STM32_IRQ_DFSDM0 (STM32_IRQ_FIRST + 61) /* 61: DFSDM0 global interrupt */ +#define STM32_IRQ_DFSDM1 (STM32_IRQ_FIRST + 62) /* 62: DFSDM1 global interrupt*/ +#define STM32_IRQ_DFSDM2 (STM32_IRQ_FIRST + 63) /* 63: DFSDM2 global interrupt */ +#define STM32_IRQ_COMP (STM32_IRQ_FIRST + 64) /* 64: COMP1/COMP2 interrupts */ +#define STM32_IRQ_LPTIM1 (STM32_IRQ_FIRST + 65) /* 65: LPTIM1 global interrupt */ +#define STM32_IRQ_LPTIM2 (STM32_IRQ_FIRST + 66) /* 66: LPTIM2 global interrupt */ +#define STM32_IRQ_OTGFS (STM32_IRQ_FIRST + 67) /* 67: USB On The Go FS global interrupt */ +#define STM32_IRQ_DMA2CH6 (STM32_IRQ_FIRST + 68) /* 68: DMA2 Channel 6 global interrupt */ +#define STM32_IRQ_DMA2CH7 (STM32_IRQ_FIRST + 69) /* 69: DMA2 Channel 7 global interrupt */ +#define STM32_IRQ_LPUART1 (STM32_IRQ_FIRST + 70) /* 70: Low power UART 1 global interrupt */ +#define STM32_IRQ_OCTOSPI1 (STM32_IRQ_FIRST + 71) /* 71: OCTOSPI1 global interrupt */ +#define STM32_IRQ_I2C3EV (STM32_IRQ_FIRST + 72) /* 72: I2C3 event interrupt */ +#define STM32_IRQ_I2C3ER (STM32_IRQ_FIRST + 73) /* 73: I2C3 error interrupt */ +#define STM32_IRQ_SAI1 (STM32_IRQ_FIRST + 74) /* 74: SAI1 global interrupt */ +#define STM32_IRQ_SAI2 (STM32_IRQ_FIRST + 75) /* 75: SAI2 global interrupt */ +#define STM32_IRQ_OCTOSPI2 (STM32_IRQ_FIRST + 76) /* 76: OCTOSPI2 global interrupt */ +#define STM32_IRQ_TSC (STM32_IRQ_FIRST + 77) /* 77: TSC global interrupt */ +#define STM32_IRQ_DSIHSOT (STM32_IRQ_FIRST + 78) /* 78: DSI global interrupt */ +#define STM32_IRQ_AES (STM32_IRQ_FIRST + 79) /* 79: AES crypto global interrupt */ +#define STM32_IRQ_RNG (STM32_IRQ_FIRST + 80) /* 80: RNG global interrupt */ +#define STM32_IRQ_FPU (STM32_IRQ_FIRST + 81) /* 81: FPU global interrupt */ +#define STM32_IRQ_HASH_CRS (STM32_IRQ_FIRST + 82) /* 82: HASH and CRS global interrupt */ +#define STM32_IRQ_I2C4EV (STM32_IRQ_FIRST + 83) /* 83: I2C4 event interrupt */ +#define STM32_IRQ_I2C4ER (STM32_IRQ_FIRST + 84) /* 84: I2C4 error interrupt */ +#define STM32_IRQ_DCMI (STM32_IRQ_FIRST + 85) /* 85: DCMI global interrupt */ + /* Reserved 86-89: CAN2 */ +#define STM32_IRQ_DMA2D (STM32_IRQ_FIRST + 90) /* 90: DMA2D global interrupt */ +#define STM32_IRQ_LCD_TFT (STM32_IRQ_FIRST + 91) /* 91: LTDC global interrupt */ +#define STM32_IRQ_LCD_TFT_ER (STM32_IRQ_FIRST + 92) /* 92: LTDC global error interrupt */ +#define STM32_IRQ_GFXMMU (STM32_IRQ_FIRST + 93) /* 93: GFXMMU global error interrupt */ +#define STM32_IRQ_DMAMUX1_OVR (STM32_IRQ_FIRST + 94) /* 94: DMAMUX overrun interrupt */ + +#define STM32_IRQ_NEXTINTS 95 /* EXTI interrupts (Do not use IRQ numbers) */ -#define NR_IRQS (STM32L4_IRQ_FIRST + STM32L4_IRQ_NEXTINTS) +#define NR_IRQS (STM32_IRQ_FIRST + STM32_IRQ_NEXTINTS) /**************************************************************************** * Public Types diff --git a/arch/arm/include/stm32l5/chip.h b/arch/arm/include/stm32l5/chip.h index 25fae6e32e0c9..0986ac7a15068 100644 --- a/arch/arm/include/stm32l5/chip.h +++ b/arch/arm/include/stm32l5/chip.h @@ -33,43 +33,43 @@ * Pre-processor Prototypes ****************************************************************************/ -#if defined(CONFIG_STM32L5_STM32L562XX) -# define STM32L5_SRAM1_SIZE (192*1024) /* 192Kb SRAM1 on AHB bus Matrix */ -# define STM32L5_SRAM2_SIZE (64*1024) /* 64Kb SRAM2 on AHB bus Matrix */ +#if defined(CONFIG_STM32_STM32L562XX) +# define STM32_SRAM1_SIZE (192*1024) /* 192Kb SRAM1 on AHB bus Matrix */ +# define STM32_SRAM2_SIZE (64*1024) /* 64Kb SRAM2 on AHB bus Matrix */ #else # error "Unsupported STM32L5 chip" #endif -#if defined(CONFIG_STM32L5_STM32L562XX) -# define STM32L5_NFSMC 1 /* Have FSMC memory controller */ -# define STM32L5_NATIM 2 /* Two advanced timers TIM1 and 8 */ -# define STM32L5_NGTIM32 2 /* 32-bit general timers TIM2 and 5 with DMA */ -# define STM32L5_NGTIM16 2 /* 16-bit general timers TIM3 and 4 with DMA */ -# define STM32L5_NGTIMNDMA 3 /* 16-bit general timers TIM15-17 without DMA */ -# define STM32L5_NBTIM 2 /* Two basic timers, TIM6-7 */ -# define STM32L5_NLPTIM 2 /* Two low-power timers, LPTIM1-2 */ -# define STM32L5_NRNG 1 /* Random number generator (RNG) */ -# define STM32L5_NUART 2 /* UART 4-5 */ -# define STM32L5_NUSART 3 /* USART 1-3 */ -# define STM32L5_NLPUART 1 /* LPUART 1 */ -# define STM32L5_QSPI 0 /* No QuadSPI1 */ -# define STM32L5_OCTOSPI 2 /* OCTOSPI1-2 */ -# define STM32L5_NSPI 3 /* SPI1-3 */ -# define STM32L5_NI2C 4 /* I2C1-4 */ -# define STM32L5_NSWPMI 0 /* No SWPMI1 */ -# define STM32L5_NUSBOTGFS 1 /* USB OTG FS */ -# define STM32L5_NUSBFS 0 /* No USB FS */ -# define STM32L5_NCAN 1 /* CAN1 */ -# define STM32L5_NSAI 2 /* SAI1-2 */ -# define STM32L5_NSDMMC 1 /* SDMMC interface */ -# define STM32L5_NDMA 2 /* DMA1-2 */ -# define STM32L5_NPORTS 8 /* 8 GPIO ports, GPIOA-H */ -# define STM32L5_NADC 1 /* 12-bit ADC1, up to 20 channels */ -# define STM32L5_NDAC 2 /* 12-bit DAC1-2 */ -# define STM32L5_NCRC 1 /* CRC */ -# define STM32L5_NCOMP 2 /* Comparators */ -# define STM32L5_NOPAMP 2 /* Operational Amplifiers */ -#endif /* CONFIG_STM32L5_STM32L562XX */ +#if defined(CONFIG_STM32_STM32L562XX) +# define STM32_NFSMC 1 /* Have FSMC memory controller */ +# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ +# define STM32_NGTIM32 2 /* 32-bit general timers TIM2 and 5 with DMA */ +# define STM32_NGTIM16 2 /* 16-bit general timers TIM3 and 4 with DMA */ +# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM15-17 without DMA */ +# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ +# define STM32_NLPTIM 2 /* Two low-power timers, LPTIM1-2 */ +# define STM32_NRNG 1 /* Random number generator (RNG) */ +# define STM32_NUART 2 /* UART 4-5 */ +# define STM32_NUSART 3 /* USART 1-3 */ +# define STM32_NLPUART 1 /* LPUART 1 */ +# define STM32_QSPI 0 /* No QuadSPI1 */ +# define STM32_OCTOSPI 2 /* OCTOSPI1-2 */ +# define STM32_NSPI 3 /* SPI1-3 */ +# define STM32_NI2C 4 /* I2C1-4 */ +# define STM32_NSWPMI 0 /* No SWPMI1 */ +# define STM32_NUSBOTGFS 1 /* USB OTG FS */ +# define STM32_NUSBFS 0 /* No USB FS */ +# define STM32_NCAN 1 /* CAN1 */ +# define STM32_NSAI 2 /* SAI1-2 */ +# define STM32_NSDMMC 1 /* SDMMC interface */ +# define STM32_NDMA 2 /* DMA1-2 */ +# define STM32_NPORTS 8 /* 8 GPIO ports, GPIOA-H */ +# define STM32_NADC 1 /* 12-bit ADC1, up to 20 channels */ +# define STM32_NDAC 2 /* 12-bit DAC1-2 */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NCOMP 2 /* Comparators */ +# define STM32_NOPAMP 2 /* Operational Amplifiers */ +#endif /* CONFIG_STM32_STM32L562XX */ /* NVIC priority levels *****************************************************/ diff --git a/arch/arm/include/stm32l5/irq.h b/arch/arm/include/stm32l5/irq.h index 9a35b3bdaf3aa..941262961520d 100644 --- a/arch/arm/include/stm32l5/irq.h +++ b/arch/arm/include/stm32l5/irq.h @@ -33,7 +33,7 @@ #include -#if defined(CONFIG_STM32L5_STM32L562XX) +#if defined(CONFIG_STM32_STM32L562XX) # include #else # error "Unsupported STM32 L5 chip" diff --git a/arch/arm/include/stm32l5/stm32l562xx_irq.h b/arch/arm/include/stm32l5/stm32l562xx_irq.h index a8e283dcc9543..35e326d15b003 100644 --- a/arch/arm/include/stm32l5/stm32l562xx_irq.h +++ b/arch/arm/include/stm32l5/stm32l562xx_irq.h @@ -50,124 +50,124 @@ * */ -#define STM32L5_IRQ_WWDG (STM32L5_IRQ_FIRST + 0) /* 0: Window Watchdog interrupt */ -#define STM32L5_IRQ_PVD_PVM (STM32L5_IRQ_FIRST + 1) /* 1: PVD/PVM1/PVM2/PVM3/PVM4 */ -#define STM32L5_IRQ_RTC (STM32L5_IRQ_FIRST + 2) /* 2: RTC global interrupts */ -#define STM32L5_IRQ_RTC_S (STM32L5_IRQ_FIRST + 3) /* 3: RTC secure global interrupts */ -#define STM32L5_IRQ_TAMP (STM32L5_IRQ_FIRST + 4) /* 4: Tamper global interrupt */ -#define STM32L5_IRQ_TAMP_S (STM32L5_IRQ_FIRST + 5) /* 5: Tamper secure global interrupt */ -#define STM32L5_IRQ_FLASH (STM32L5_IRQ_FIRST + 6) /* 6: Flash memory global interrupt */ -#define STM32L5_IRQ_FLASH_S (STM32L5_IRQ_FIRST + 7) /* 7: Flash memory secure global interrupt */ -#define STM32L5_IRQ_GTZC (STM32L5_IRQ_FIRST + 8) /* 8: TZIC secure global interrupt */ -#define STM32L5_IRQ_RCC (STM32L5_IRQ_FIRST + 9) /* 9: RCC global interrupt */ -#define STM32L5_IRQ_RCC_S (STM32L5_IRQ_FIRST + 10) /* 10: RCC secure global interrupt */ -#define STM32L5_IRQ_EXTI0 (STM32L5_IRQ_FIRST + 11) /* 11: EXTI Line 0 interrupt */ -#define STM32L5_IRQ_EXTI1 (STM32L5_IRQ_FIRST + 12) /* 12: EXTI Line 1 interrupt */ -#define STM32L5_IRQ_EXTI2 (STM32L5_IRQ_FIRST + 13) /* 13: EXTI Line 2 interrupt */ -#define STM32L5_IRQ_EXTI3 (STM32L5_IRQ_FIRST + 14) /* 14: EXTI Line 3 interrupt */ -#define STM32L5_IRQ_EXTI4 (STM32L5_IRQ_FIRST + 15) /* 15: EXTI Line 4 interrupt */ -#define STM32L5_IRQ_EXTI5 (STM32L5_IRQ_FIRST + 16) /* 16: EXTI Line 5 interrupt */ -#define STM32L5_IRQ_EXTI6 (STM32L5_IRQ_FIRST + 17) /* 17: EXTI Line 6 interrupt */ -#define STM32L5_IRQ_EXTI7 (STM32L5_IRQ_FIRST + 18) /* 18: EXTI Line 7 interrupt */ -#define STM32L5_IRQ_EXTI8 (STM32L5_IRQ_FIRST + 19) /* 19: EXTI Line 8 interrupt */ -#define STM32L5_IRQ_EXTI9 (STM32L5_IRQ_FIRST + 20) /* 20: EXTI Line 9 interrupt */ -#define STM32L5_IRQ_EXTI10 (STM32L5_IRQ_FIRST + 21) /* 21: EXTI Line 10 interrupt */ -#define STM32L5_IRQ_EXTI11 (STM32L5_IRQ_FIRST + 22) /* 22: EXTI Line 11 interrupt */ -#define STM32L5_IRQ_EXTI12 (STM32L5_IRQ_FIRST + 23) /* 23: EXTI Line 12 interrupt */ -#define STM32L5_IRQ_EXTI13 (STM32L5_IRQ_FIRST + 24) /* 24: EXTI Line 13 interrupt */ -#define STM32L5_IRQ_EXTI14 (STM32L5_IRQ_FIRST + 25) /* 25: EXTI Line 14 interrupt */ -#define STM32L5_IRQ_EXTI15 (STM32L5_IRQ_FIRST + 26) /* 26: EXTI Line 15 interrupt */ -#define STM32L5_IRQ_DMAMUX1_OVR (STM32L5_IRQ_FIRST + 27) /* 27: DMAMUX1 overRun interrupt */ -#define STM32L5_IRQ_DMAMUX1_OVR_S (STM32L5_IRQ_FIRST + 28) /* 28: DMAMUX1 secure overRun interrupt */ -#define STM32L5_IRQ_DMA1CH1 (STM32L5_IRQ_FIRST + 29) /* 29: DMA1 Channel 1 global interrupt */ -#define STM32L5_IRQ_DMA1CH2 (STM32L5_IRQ_FIRST + 30) /* 30: DMA1 Channel 2 global interrupt */ -#define STM32L5_IRQ_DMA1CH3 (STM32L5_IRQ_FIRST + 31) /* 31: DMA1 Channel 3 global interrupt */ -#define STM32L5_IRQ_DMA1CH4 (STM32L5_IRQ_FIRST + 32) /* 32: DMA1 Channel 4 global interrupt */ -#define STM32L5_IRQ_DMA1CH5 (STM32L5_IRQ_FIRST + 33) /* 33: DMA1 Channel 5 global interrupt */ -#define STM32L5_IRQ_DMA1CH6 (STM32L5_IRQ_FIRST + 34) /* 34: DMA1 Channel 6 global interrupt */ -#define STM32L5_IRQ_DMA1CH7 (STM32L5_IRQ_FIRST + 35) /* 35: DMA1 Channel 7 global interrupt */ -#define STM32L5_IRQ_DMA1CH8 (STM32L5_IRQ_FIRST + 36) /* 36: DMA1 Channel 8 global interrupt */ -#define STM32L5_IRQ_ADC1_2 (STM32L5_IRQ_FIRST + 37) /* 37: ADC1_2 global interrupt */ -#define STM32L5_IRQ_DAC (STM32L5_IRQ_FIRST + 38) /* 38: DAC global interrupt */ -#define STM32L5_IRQ_FDCAN1_IT0 (STM32L5_IRQ_FIRST + 39) /* 39: FDCAN1_IT0: FDCAN1 Interrupt 0 */ -#define STM32L5_IRQ_FDCAN1_IT1 (STM32L5_IRQ_FIRST + 40) /* 40: FDCAN1_IT0: FDCAN1 Interrupt 1 */ -#define STM32L5_IRQ_TIM1_BRK (STM32L5_IRQ_FIRST + 41) /* 41: TIM1 break */ -#define STM32L5_IRQ_TIM1_UP (STM32L5_IRQ_FIRST + 42) /* 42: TIM1 update */ -#define STM32L5_IRQ_TIM1_TRG_COM (STM32L5_IRQ_FIRST + 43) /* 43: TIM1 trigger and communication */ -#define STM32L5_IRQ_TIM1_CC (STM32L5_IRQ_FIRST + 44) /* 44: TIM1 capture compare interrupt */ -#define STM32L5_IRQ_TIM2 (STM32L5_IRQ_FIRST + 45) /* 45: TIM2 global interrupt */ -#define STM32L5_IRQ_TIM3 (STM32L5_IRQ_FIRST + 46) /* 46: TIM3 global interrupt */ -#define STM32L5_IRQ_TIM4 (STM32L5_IRQ_FIRST + 47) /* 47: TIM4 global interrupt */ -#define STM32L5_IRQ_TIM5 (STM32L5_IRQ_FIRST + 48) /* 48: TIM5 global interrupt */ -#define STM32L5_IRQ_TIM6 (STM32L5_IRQ_FIRST + 49) /* 49: TIM6 global interrupt */ -#define STM32L5_IRQ_TIM7 (STM32L5_IRQ_FIRST + 50) /* 50: TIM7 global interrupt */ -#define STM32L5_IRQ_TIM8_BRK (STM32L5_IRQ_FIRST + 51) /* 51: TIM8 break */ -#define STM32L5_IRQ_TIM8_UP (STM32L5_IRQ_FIRST + 52) /* 52: TIM8 update */ -#define STM32L5_IRQ_TIM8_TRG_COM (STM32L5_IRQ_FIRST + 53) /* 53: TIM8 trigger and communication */ -#define STM32L5_IRQ_TIM8_CC (STM32L5_IRQ_FIRST + 54) /* 54: TIM8 capture compare interrupt */ -#define STM32L5_IRQ_I2C1_EV (STM32L5_IRQ_FIRST + 55) /* 55: I2C1 event interrupt */ -#define STM32L5_IRQ_I2C1_ER (STM32L5_IRQ_FIRST + 56) /* 56: I2C1 error interrupt */ -#define STM32L5_IRQ_I2C2_EV (STM32L5_IRQ_FIRST + 57) /* 57: I2C2 event interrupt */ -#define STM32L5_IRQ_I2C2_ER (STM32L5_IRQ_FIRST + 58) /* 58: I2C2 error interrupt */ -#define STM32L5_IRQ_SPI1 (STM32L5_IRQ_FIRST + 59) /* 59: SPI1 global interrupt */ -#define STM32L5_IRQ_SPI2 (STM32L5_IRQ_FIRST + 60) /* 60: SPI2 global interrupt */ -#define STM32L5_IRQ_USART1 (STM32L5_IRQ_FIRST + 61) /* 61: USART1 global interrupt */ -#define STM32L5_IRQ_USART2 (STM32L5_IRQ_FIRST + 62) /* 62: USART2 global interrupt */ -#define STM32L5_IRQ_USART3 (STM32L5_IRQ_FIRST + 63) /* 63: USART3 global interrupt */ -#define STM32L5_IRQ_UART4 (STM32L5_IRQ_FIRST + 64) /* 64: UART4 global interrupt */ -#define STM32L5_IRQ_UART5 (STM32L5_IRQ_FIRST + 65) /* 65: UART5 global interrupt */ -#define STM32L5_IRQ_LPUART1 (STM32L5_IRQ_FIRST + 66) /* 66: LPUART 1 global interrupt */ -#define STM32L5_IRQ_LPTIM1 (STM32L5_IRQ_FIRST + 67) /* 67: LPTIM1 global interrupt */ -#define STM32L5_IRQ_LPTIM2 (STM32L5_IRQ_FIRST + 68) /* 68: LPTIM2 global interrupt */ -#define STM32L5_IRQ_TIM15 (STM32L5_IRQ_FIRST + 69) /* 69: TIM15 global interrupt */ -#define STM32L5_IRQ_TIM16 (STM32L5_IRQ_FIRST + 70) /* 70: TIM16 global interrupt */ -#define STM32L5_IRQ_TIM17 (STM32L5_IRQ_FIRST + 71) /* 71: TIM17 global interrupt */ -#define STM32L5_IRQ_COMP (STM32L5_IRQ_FIRST + 72) /* 72: COMP1/COMP2 interrupts */ -#define STM32L5_IRQ_USB_FS (STM32L5_IRQ_FIRST + 73) /* 73: USB global interrupt */ -#define STM32L5_IRQ_CRS (STM32L5_IRQ_FIRST + 74) /* 74: CRS global interrupt */ -#define STM32L5_IRQ_FMC (STM32L5_IRQ_FIRST + 75) /* 75: FMC global interrupt */ -#define STM32L5_IRQ_OCTOSPI1 (STM32L5_IRQ_FIRST + 76) /* 76: OCTOSPI1 global interrupt */ - /* 77: Reserved */ -#define STM32L5_IRQ_SDMMC1 (STM32L5_IRQ_FIRST + 78) /* 78: SDMMC1 global interrupt */ - /* 79: Reserved */ -#define STM32L5_IRQ_DMA2CH1 (STM32L5_IRQ_FIRST + 80) /* 80: DMA2 Channel 1 global interrupt */ -#define STM32L5_IRQ_DMA2CH2 (STM32L5_IRQ_FIRST + 81) /* 81: DMA2 Channel 2 global interrupt */ -#define STM32L5_IRQ_DMA2CH3 (STM32L5_IRQ_FIRST + 82) /* 82: DMA2 Channel 3 global interrupt */ -#define STM32L5_IRQ_DMA2CH4 (STM32L5_IRQ_FIRST + 83) /* 83: DMA2 Channel 4 global interrupt */ -#define STM32L5_IRQ_DMA2CH5 (STM32L5_IRQ_FIRST + 84) /* 84: DMA2 Channel 5 global interrupt */ -#define STM32L5_IRQ_DMA2CH6 (STM32L5_IRQ_FIRST + 85) /* 85: DMA2 Channel 6 global interrupt */ -#define STM32L5_IRQ_DMA2CH7 (STM32L5_IRQ_FIRST + 86) /* 86: DMA2 Channel 7 global interrupt */ -#define STM32L5_IRQ_DMA2CH8 (STM32L5_IRQ_FIRST + 87) /* 87: DMA2 Channel 8 global interrupt */ -#define STM32L5_IRQ_I2C3_EV (STM32L5_IRQ_FIRST + 88) /* 88: I2C3 event interrupt */ -#define STM32L5_IRQ_I2C3_ER (STM32L5_IRQ_FIRST + 89) /* 89: I2C3 error interrupt */ -#define STM32L5_IRQ_SAI1 (STM32L5_IRQ_FIRST + 90) /* 90: SAI1 global interrupt */ -#define STM32L5_IRQ_SAI2 (STM32L5_IRQ_FIRST + 91) /* 91: SAI2 global interrupt */ -#define STM32L5_IRQ_TSC (STM32L5_IRQ_FIRST + 92) /* 92: TSC global interrupt */ -#define STM32L5_IRQ_AES (STM32L5_IRQ_FIRST + 93) /* 93: AES global interrupt */ -#define STM32L5_IRQ_RNG (STM32L5_IRQ_FIRST + 94) /* 94: RNG global interrupt */ -#define STM32L5_IRQ_FPU (STM32L5_IRQ_FIRST + 95) /* 95: FPU global interrupt */ -#define STM32L5_IRQ_HASH (STM32L5_IRQ_FIRST + 96) /* 96: HASH global interrupt */ -#define STM32L5_IRQ_PKA (STM32L5_IRQ_FIRST + 97) /* 97: PKA global interrupt */ -#define STM32L5_IRQ_LPTIM3 (STM32L5_IRQ_FIRST + 98) /* 98: LPTIM3 global interrupt */ -#define STM32L5_IRQ_SPI3 (STM32L5_IRQ_FIRST + 99) /* 99: SPI3 global interrupt */ -#define STM32L5_IRQ_I2C4_EV (STM32L5_IRQ_FIRST + 100) /* 100: I2C4 event interrupt */ -#define STM32L5_IRQ_I2C4_ER (STM32L5_IRQ_FIRST + 101) /* 101: I2C4 error interrupt */ -#define STM32L5_IRQ_DFSDM1_FLT0 (STM32L5_IRQ_FIRST + 102) /* 102: DFSDM1 filter 0 global interrupt */ -#define STM32L5_IRQ_DFSDM1_FLT1 (STM32L5_IRQ_FIRST + 103) /* 103: DFSDM1 filter 1 global interrupt */ -#define STM32L5_IRQ_DFSDM1_FLT2 (STM32L5_IRQ_FIRST + 104) /* 104: DFSDM1 filter 2 global interrupt */ -#define STM32L5_IRQ_DFSDM1_FLT3 (STM32L5_IRQ_FIRST + 105) /* 105: DFSDM1 filter 3 global interrupt */ -#define STM32L5_IRQ_UCPD1 (STM32L5_IRQ_FIRST + 106) /* 106: UCPD1 global interrupt */ -#define STM32L5_IRQ_ICACHE (STM32L5_IRQ_FIRST + 107) /* 107: Instruction cache global interrupt */ -#define STM32L5_IRQ_OTFDEC1 (STM32L5_IRQ_FIRST + 108) /* 108: OTFDEC1 global interrupt */ +#define STM32_IRQ_WWDG (STM32_IRQ_FIRST + 0) /* 0: Window Watchdog interrupt */ +#define STM32_IRQ_PVD_PVM (STM32_IRQ_FIRST + 1) /* 1: PVD/PVM1/PVM2/PVM3/PVM4 */ +#define STM32_IRQ_RTC (STM32_IRQ_FIRST + 2) /* 2: RTC global interrupts */ +#define STM32_IRQ_RTC_S (STM32_IRQ_FIRST + 3) /* 3: RTC secure global interrupts */ +#define STM32_IRQ_TAMP (STM32_IRQ_FIRST + 4) /* 4: Tamper global interrupt */ +#define STM32_IRQ_TAMP_S (STM32_IRQ_FIRST + 5) /* 5: Tamper secure global interrupt */ +#define STM32_IRQ_FLASH (STM32_IRQ_FIRST + 6) /* 6: Flash memory global interrupt */ +#define STM32_IRQ_FLASH_S (STM32_IRQ_FIRST + 7) /* 7: Flash memory secure global interrupt */ +#define STM32_IRQ_GTZC (STM32_IRQ_FIRST + 8) /* 8: TZIC secure global interrupt */ +#define STM32_IRQ_RCC (STM32_IRQ_FIRST + 9) /* 9: RCC global interrupt */ +#define STM32_IRQ_RCC_S (STM32_IRQ_FIRST + 10) /* 10: RCC secure global interrupt */ +#define STM32_IRQ_EXTI0 (STM32_IRQ_FIRST + 11) /* 11: EXTI Line 0 interrupt */ +#define STM32_IRQ_EXTI1 (STM32_IRQ_FIRST + 12) /* 12: EXTI Line 1 interrupt */ +#define STM32_IRQ_EXTI2 (STM32_IRQ_FIRST + 13) /* 13: EXTI Line 2 interrupt */ +#define STM32_IRQ_EXTI3 (STM32_IRQ_FIRST + 14) /* 14: EXTI Line 3 interrupt */ +#define STM32_IRQ_EXTI4 (STM32_IRQ_FIRST + 15) /* 15: EXTI Line 4 interrupt */ +#define STM32_IRQ_EXTI5 (STM32_IRQ_FIRST + 16) /* 16: EXTI Line 5 interrupt */ +#define STM32_IRQ_EXTI6 (STM32_IRQ_FIRST + 17) /* 17: EXTI Line 6 interrupt */ +#define STM32_IRQ_EXTI7 (STM32_IRQ_FIRST + 18) /* 18: EXTI Line 7 interrupt */ +#define STM32_IRQ_EXTI8 (STM32_IRQ_FIRST + 19) /* 19: EXTI Line 8 interrupt */ +#define STM32_IRQ_EXTI9 (STM32_IRQ_FIRST + 20) /* 20: EXTI Line 9 interrupt */ +#define STM32_IRQ_EXTI10 (STM32_IRQ_FIRST + 21) /* 21: EXTI Line 10 interrupt */ +#define STM32_IRQ_EXTI11 (STM32_IRQ_FIRST + 22) /* 22: EXTI Line 11 interrupt */ +#define STM32_IRQ_EXTI12 (STM32_IRQ_FIRST + 23) /* 23: EXTI Line 12 interrupt */ +#define STM32_IRQ_EXTI13 (STM32_IRQ_FIRST + 24) /* 24: EXTI Line 13 interrupt */ +#define STM32_IRQ_EXTI14 (STM32_IRQ_FIRST + 25) /* 25: EXTI Line 14 interrupt */ +#define STM32_IRQ_EXTI15 (STM32_IRQ_FIRST + 26) /* 26: EXTI Line 15 interrupt */ +#define STM32_IRQ_DMAMUX1_OVR (STM32_IRQ_FIRST + 27) /* 27: DMAMUX1 overRun interrupt */ +#define STM32_IRQ_DMAMUX1_OVR_S (STM32_IRQ_FIRST + 28) /* 28: DMAMUX1 secure overRun interrupt */ +#define STM32_IRQ_DMA1CH1 (STM32_IRQ_FIRST + 29) /* 29: DMA1 Channel 1 global interrupt */ +#define STM32_IRQ_DMA1CH2 (STM32_IRQ_FIRST + 30) /* 30: DMA1 Channel 2 global interrupt */ +#define STM32_IRQ_DMA1CH3 (STM32_IRQ_FIRST + 31) /* 31: DMA1 Channel 3 global interrupt */ +#define STM32_IRQ_DMA1CH4 (STM32_IRQ_FIRST + 32) /* 32: DMA1 Channel 4 global interrupt */ +#define STM32_IRQ_DMA1CH5 (STM32_IRQ_FIRST + 33) /* 33: DMA1 Channel 5 global interrupt */ +#define STM32_IRQ_DMA1CH6 (STM32_IRQ_FIRST + 34) /* 34: DMA1 Channel 6 global interrupt */ +#define STM32_IRQ_DMA1CH7 (STM32_IRQ_FIRST + 35) /* 35: DMA1 Channel 7 global interrupt */ +#define STM32_IRQ_DMA1CH8 (STM32_IRQ_FIRST + 36) /* 36: DMA1 Channel 8 global interrupt */ +#define STM32_IRQ_ADC1_2 (STM32_IRQ_FIRST + 37) /* 37: ADC1_2 global interrupt */ +#define STM32_IRQ_DAC (STM32_IRQ_FIRST + 38) /* 38: DAC global interrupt */ +#define STM32_IRQ_FDCAN1_IT0 (STM32_IRQ_FIRST + 39) /* 39: FDCAN1_IT0: FDCAN1 Interrupt 0 */ +#define STM32_IRQ_FDCAN1_IT1 (STM32_IRQ_FIRST + 40) /* 40: FDCAN1_IT0: FDCAN1 Interrupt 1 */ +#define STM32_IRQ_TIM1_BRK (STM32_IRQ_FIRST + 41) /* 41: TIM1 break */ +#define STM32_IRQ_TIM1_UP (STM32_IRQ_FIRST + 42) /* 42: TIM1 update */ +#define STM32_IRQ_TIM1_TRG_COM (STM32_IRQ_FIRST + 43) /* 43: TIM1 trigger and communication */ +#define STM32_IRQ_TIM1_CC (STM32_IRQ_FIRST + 44) /* 44: TIM1 capture compare interrupt */ +#define STM32_IRQ_TIM2 (STM32_IRQ_FIRST + 45) /* 45: TIM2 global interrupt */ +#define STM32_IRQ_TIM3 (STM32_IRQ_FIRST + 46) /* 46: TIM3 global interrupt */ +#define STM32_IRQ_TIM4 (STM32_IRQ_FIRST + 47) /* 47: TIM4 global interrupt */ +#define STM32_IRQ_TIM5 (STM32_IRQ_FIRST + 48) /* 48: TIM5 global interrupt */ +#define STM32_IRQ_TIM6 (STM32_IRQ_FIRST + 49) /* 49: TIM6 global interrupt */ +#define STM32_IRQ_TIM7 (STM32_IRQ_FIRST + 50) /* 50: TIM7 global interrupt */ +#define STM32_IRQ_TIM8_BRK (STM32_IRQ_FIRST + 51) /* 51: TIM8 break */ +#define STM32_IRQ_TIM8_UP (STM32_IRQ_FIRST + 52) /* 52: TIM8 update */ +#define STM32_IRQ_TIM8_TRG_COM (STM32_IRQ_FIRST + 53) /* 53: TIM8 trigger and communication */ +#define STM32_IRQ_TIM8_CC (STM32_IRQ_FIRST + 54) /* 54: TIM8 capture compare interrupt */ +#define STM32_IRQ_I2C1_EV (STM32_IRQ_FIRST + 55) /* 55: I2C1 event interrupt */ +#define STM32_IRQ_I2C1_ER (STM32_IRQ_FIRST + 56) /* 56: I2C1 error interrupt */ +#define STM32_IRQ_I2C2_EV (STM32_IRQ_FIRST + 57) /* 57: I2C2 event interrupt */ +#define STM32_IRQ_I2C2_ER (STM32_IRQ_FIRST + 58) /* 58: I2C2 error interrupt */ +#define STM32_IRQ_SPI1 (STM32_IRQ_FIRST + 59) /* 59: SPI1 global interrupt */ +#define STM32_IRQ_SPI2 (STM32_IRQ_FIRST + 60) /* 60: SPI2 global interrupt */ +#define STM32_IRQ_USART1 (STM32_IRQ_FIRST + 61) /* 61: USART1 global interrupt */ +#define STM32_IRQ_USART2 (STM32_IRQ_FIRST + 62) /* 62: USART2 global interrupt */ +#define STM32_IRQ_USART3 (STM32_IRQ_FIRST + 63) /* 63: USART3 global interrupt */ +#define STM32_IRQ_UART4 (STM32_IRQ_FIRST + 64) /* 64: UART4 global interrupt */ +#define STM32_IRQ_UART5 (STM32_IRQ_FIRST + 65) /* 65: UART5 global interrupt */ +#define STM32_IRQ_LPUART1 (STM32_IRQ_FIRST + 66) /* 66: LPUART 1 global interrupt */ +#define STM32_IRQ_LPTIM1 (STM32_IRQ_FIRST + 67) /* 67: LPTIM1 global interrupt */ +#define STM32_IRQ_LPTIM2 (STM32_IRQ_FIRST + 68) /* 68: LPTIM2 global interrupt */ +#define STM32_IRQ_TIM15 (STM32_IRQ_FIRST + 69) /* 69: TIM15 global interrupt */ +#define STM32_IRQ_TIM16 (STM32_IRQ_FIRST + 70) /* 70: TIM16 global interrupt */ +#define STM32_IRQ_TIM17 (STM32_IRQ_FIRST + 71) /* 71: TIM17 global interrupt */ +#define STM32_IRQ_COMP (STM32_IRQ_FIRST + 72) /* 72: COMP1/COMP2 interrupts */ +#define STM32_IRQ_USB_FS (STM32_IRQ_FIRST + 73) /* 73: USB global interrupt */ +#define STM32_IRQ_CRS (STM32_IRQ_FIRST + 74) /* 74: CRS global interrupt */ +#define STM32_IRQ_FMC (STM32_IRQ_FIRST + 75) /* 75: FMC global interrupt */ +#define STM32_IRQ_OCTOSPI1 (STM32_IRQ_FIRST + 76) /* 76: OCTOSPI1 global interrupt */ + /* 77: Reserved */ +#define STM32_IRQ_SDMMC1 (STM32_IRQ_FIRST + 78) /* 78: SDMMC1 global interrupt */ + /* 79: Reserved */ +#define STM32_IRQ_DMA2CH1 (STM32_IRQ_FIRST + 80) /* 80: DMA2 Channel 1 global interrupt */ +#define STM32_IRQ_DMA2CH2 (STM32_IRQ_FIRST + 81) /* 81: DMA2 Channel 2 global interrupt */ +#define STM32_IRQ_DMA2CH3 (STM32_IRQ_FIRST + 82) /* 82: DMA2 Channel 3 global interrupt */ +#define STM32_IRQ_DMA2CH4 (STM32_IRQ_FIRST + 83) /* 83: DMA2 Channel 4 global interrupt */ +#define STM32_IRQ_DMA2CH5 (STM32_IRQ_FIRST + 84) /* 84: DMA2 Channel 5 global interrupt */ +#define STM32_IRQ_DMA2CH6 (STM32_IRQ_FIRST + 85) /* 85: DMA2 Channel 6 global interrupt */ +#define STM32_IRQ_DMA2CH7 (STM32_IRQ_FIRST + 86) /* 86: DMA2 Channel 7 global interrupt */ +#define STM32_IRQ_DMA2CH8 (STM32_IRQ_FIRST + 87) /* 87: DMA2 Channel 8 global interrupt */ +#define STM32_IRQ_I2C3_EV (STM32_IRQ_FIRST + 88) /* 88: I2C3 event interrupt */ +#define STM32_IRQ_I2C3_ER (STM32_IRQ_FIRST + 89) /* 89: I2C3 error interrupt */ +#define STM32_IRQ_SAI1 (STM32_IRQ_FIRST + 90) /* 90: SAI1 global interrupt */ +#define STM32_IRQ_SAI2 (STM32_IRQ_FIRST + 91) /* 91: SAI2 global interrupt */ +#define STM32_IRQ_TSC (STM32_IRQ_FIRST + 92) /* 92: TSC global interrupt */ +#define STM32_IRQ_AES (STM32_IRQ_FIRST + 93) /* 93: AES global interrupt */ +#define STM32_IRQ_RNG (STM32_IRQ_FIRST + 94) /* 94: RNG global interrupt */ +#define STM32_IRQ_FPU (STM32_IRQ_FIRST + 95) /* 95: FPU global interrupt */ +#define STM32_IRQ_HASH (STM32_IRQ_FIRST + 96) /* 96: HASH global interrupt */ +#define STM32_IRQ_PKA (STM32_IRQ_FIRST + 97) /* 97: PKA global interrupt */ +#define STM32_IRQ_LPTIM3 (STM32_IRQ_FIRST + 98) /* 98: LPTIM3 global interrupt */ +#define STM32_IRQ_SPI3 (STM32_IRQ_FIRST + 99) /* 99: SPI3 global interrupt */ +#define STM32_IRQ_I2C4_EV (STM32_IRQ_FIRST + 100) /* 100: I2C4 event interrupt */ +#define STM32_IRQ_I2C4_ER (STM32_IRQ_FIRST + 101) /* 101: I2C4 error interrupt */ +#define STM32_IRQ_DFSDM1_FLT0 (STM32_IRQ_FIRST + 102) /* 102: DFSDM1 filter 0 global interrupt */ +#define STM32_IRQ_DFSDM1_FLT1 (STM32_IRQ_FIRST + 103) /* 103: DFSDM1 filter 1 global interrupt */ +#define STM32_IRQ_DFSDM1_FLT2 (STM32_IRQ_FIRST + 104) /* 104: DFSDM1 filter 2 global interrupt */ +#define STM32_IRQ_DFSDM1_FLT3 (STM32_IRQ_FIRST + 105) /* 105: DFSDM1 filter 3 global interrupt */ +#define STM32_IRQ_UCPD1 (STM32_IRQ_FIRST + 106) /* 106: UCPD1 global interrupt */ +#define STM32_IRQ_ICACHE (STM32_IRQ_FIRST + 107) /* 107: Instruction cache global interrupt */ +#define STM32_IRQ_OTFDEC1 (STM32_IRQ_FIRST + 108) /* 108: OTFDEC1 global interrupt */ -#if defined(CONFIG_STM32L5_STM32L562XX) -# define STM32L5_IRQ_NEXTINTS 109 +#if defined(CONFIG_STM32_STM32L562XX) +# define STM32_IRQ_NEXTINTS 109 #else # error "Unsupported STM32L5 chip" #endif /* (EXTI interrupts do not use IRQ numbers) */ -#define NR_IRQS (STM32L5_IRQ_FIRST + STM32L5_IRQ_NEXTINTS) +#define NR_IRQS (STM32_IRQ_FIRST + STM32_IRQ_NEXTINTS) #endif /* __ARCH_ARM_INCLUDE_STM32L5_STM32L562XX_IRQ_H */ diff --git a/arch/arm/include/stm32l5/stm32l5_irq.h b/arch/arm/include/stm32l5/stm32l5_irq.h index 8ffbc2ac9a97e..bca9065244e23 100644 --- a/arch/arm/include/stm32l5/stm32l5_irq.h +++ b/arch/arm/include/stm32l5/stm32l5_irq.h @@ -25,8 +25,8 @@ * (e.g. stm32l562xx_irq.h) */ -#ifndef __ARCH_ARM_INCLUDE_STM32L5_STM32L5_IRQ_H -#define __ARCH_ARM_INCLUDE_STM32L5_STM32L5_IRQ_H +#ifndef __ARCH_ARM_INCLUDE_STM32L5_STM32_IRQ_H +#define __ARCH_ARM_INCLUDE_STM32L5_STM32_IRQ_H /**************************************************************************** * Included Files @@ -46,26 +46,26 @@ /* Processor Exceptions (vectors 0-15) */ -#define STM32L5_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */ - /* Vector 0: Reset stack pointer value */ - /* Vector 1: Reset (not handler as an IRQ) */ -#define STM32L5_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */ -#define STM32L5_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */ -#define STM32L5_IRQ_MEMFAULT (4) /* Vector 4: Memory management (MPU) */ -#define STM32L5_IRQ_BUSFAULT (5) /* Vector 5: Bus fault */ -#define STM32L5_IRQ_USAGEFAULT (6) /* Vector 6: Usage fault */ - /* Vectors 7-10: Reserved */ -#define STM32L5_IRQ_SVCALL (11) /* Vector 11: SVC call */ -#define STM32L5_IRQ_DBGMONITOR (12) /* Vector 12: Debug Monitor */ - /* Vector 13: Reserved */ -#define STM32L5_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */ -#define STM32L5_IRQ_SYSTICK (15) /* Vector 15: System tick */ +#define STM32_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */ + /* Vector 0: Reset stack pointer value */ + /* Vector 1: Reset (not handler as an IRQ) */ +#define STM32_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */ +#define STM32_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */ +#define STM32_IRQ_MEMFAULT (4) /* Vector 4: Memory management (MPU) */ +#define STM32_IRQ_BUSFAULT (5) /* Vector 5: Bus fault */ +#define STM32_IRQ_USAGEFAULT (6) /* Vector 6: Usage fault */ + /* Vectors 7-10: Reserved */ +#define STM32_IRQ_SVCALL (11) /* Vector 11: SVC call */ +#define STM32_IRQ_DBGMONITOR (12) /* Vector 12: Debug Monitor */ + /* Vector 13: Reserved */ +#define STM32_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */ +#define STM32_IRQ_SYSTICK (15) /* Vector 15: System tick */ /* External interrupts (vectors >= 16). * These definitions are chip-specific */ -#define STM32L5_IRQ_FIRST (16) /* Vector number of the first external interrupt */ +#define STM32_IRQ_FIRST (16) /* Vector number of the first external interrupt */ /**************************************************************************** * Public Types @@ -94,4 +94,4 @@ extern "C" #endif #endif -#endif /* __ARCH_ARM_INCLUDE_STM32L5_STM32L5_IRQ_H */ +#endif /* __ARCH_ARM_INCLUDE_STM32L5_STM32_IRQ_H */ diff --git a/arch/arm/include/stm32n6/chip.h b/arch/arm/include/stm32n6/chip.h index 72f643ba3b687..9c50b19c7c74b 100644 --- a/arch/arm/include/stm32n6/chip.h +++ b/arch/arm/include/stm32n6/chip.h @@ -52,10 +52,10 @@ * Each bank requires its RCC MEMENR clock enable bit to be set. */ -#define STM32N6_SRAM_SIZE (4 * 1024 * 1024) /* 4194304 bytes (4 MiB) */ +#define STM32_SRAM_SIZE (4 * 1024 * 1024) /* 4194304 bytes (4 MiB) */ -#define STM32N6_NPORTS (12) /* GPIO ports A-H (8) + N, O, P, Q (4) */ -#define STM32N6_NUSART (1) /* USART1 */ +#define STM32_NPORTS (12) /* GPIO ports A-H (8) + N, O, P, Q (4) */ +#define STM32_NUSART (1) /* USART1 */ /* NVIC priority levels *****************************************************/ diff --git a/arch/arm/include/stm32u5/chip.h b/arch/arm/include/stm32u5/chip.h index 887ca72d38a28..00799d00f38a6 100644 --- a/arch/arm/include/stm32u5/chip.h +++ b/arch/arm/include/stm32u5/chip.h @@ -33,14 +33,14 @@ * Pre-processor Prototypes ****************************************************************************/ -#if defined(CONFIG_STM32U5_STM32U535XX) || defined(CONFIG_STM32U5_STM32U545XX) +#if defined(CONFIG_STM32_STM32U535XX) || defined(CONFIG_STM32_STM32U545XX) # define STM32_SRAM1_SIZE (0x00030000) /* 192Kb SRAM1 */ # define STM32_SRAM2_SIZE (0x00010000) /* 64kB SRAM2 */ -#elif defined(CONFIG_STM32U5_STM32U575XX) || defined(CONFIG_STM32U5_STM32U585XX) +#elif defined(CONFIG_STM32_STM32U575XX) || defined(CONFIG_STM32_STM32U585XX) # define STM32_SRAM1_SIZE (0x00030000) /* 192Kb SRAM1 */ # define STM32_SRAM2_SIZE (0x00010000) /* 64kB SRAM2 */ # define STM32_SRAM3_SIZE (0x00080000) /* 512kB SRAM3 */ -#elif defined(CONFIG_STM32U5_STM32U59XX) || defined(CONFIG_STM32U5_STM32U59AXX) || defined(CONFIG_STM32U5_STM32U5A5XX) || defined(CONFIG_STM32U5_STM32U5A9XX) +#elif defined(CONFIG_STM32_STM32U59XX) || defined(CONFIG_STM32_STM32U59AXX) || defined(CONFIG_STM32_STM32U5A5XX) || defined(CONFIG_STM32_STM32U5A9XX) # define STM32_SRAM1_SIZE (0x000C0000) /* 768Kb SRAM1 */ # define STM32_SRAM2_SIZE (0x00010000) /* 64kB SRAM2 */ # define STM32_SRAM3_SIZE (0x000d0000) /* 832kB SRAM3 */ @@ -49,7 +49,7 @@ # error "Unsupported STM32U5 chip" #endif -#if defined(CONFIG_STM32U5_STM32U585XX) || defined(CONFIG_STM32U5_STM32U5A5XX) +#if defined(CONFIG_STM32_STM32U585XX) || defined(CONFIG_STM32_STM32U5A5XX) # define STM32_NFSMC 1 /* Have FSMC memory controller */ # define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ # define STM32_NGTIM32 2 /* 32-bit general timers TIM2 and 5 with DMA */ @@ -78,9 +78,9 @@ # define STM32_NCRC 1 /* CRC */ # define STM32_NCOMP 2 /* Comparators */ # define STM32_NOPAMP 2 /* Operational Amplifiers */ -#endif /* CONFIG_STM32U5_STM32U585XX */ +#endif /* CONFIG_STM32_STM32U585XX */ -#if defined(CONFIG_STM32U5_STM32U5A5ZJT) +#if defined(CONFIG_STM32_STM32U5A5ZJT) # define STM32_NUSBOTGHS 1 /* USB OTG HS */ #endif diff --git a/arch/arm/include/stm32u5/irq.h b/arch/arm/include/stm32u5/irq.h index 77c5c600bde0f..1dd4a1abe7c24 100644 --- a/arch/arm/include/stm32u5/irq.h +++ b/arch/arm/include/stm32u5/irq.h @@ -33,10 +33,10 @@ #include -#if defined(CONFIG_STM32U5_STM32U535XX) || defined(CONFIG_STM32U5_STM32U545XX) || \ - defined(CONFIG_STM32U5_STM32U575XX) || defined(CONFIG_STM32U5_STM32U585XX) || \ - defined(CONFIG_STM32U5_STM32U59XX) || defined(CONFIG_STM32U5_STM32U59AXX) || \ - defined(CONFIG_STM32U5_STM32U5A5XX) || defined(CONFIG_STM32U5_STM32U5A9XX) +#if defined(CONFIG_STM32_STM32U535XX) || defined(CONFIG_STM32_STM32U545XX) || \ + defined(CONFIG_STM32_STM32U575XX) || defined(CONFIG_STM32_STM32U585XX) || \ + defined(CONFIG_STM32_STM32U59XX) || defined(CONFIG_STM32_STM32U59AXX) || \ + defined(CONFIG_STM32_STM32U5A5XX) || defined(CONFIG_STM32_STM32U5A9XX) # include #else # error "Unsupported STM32U5 chip" diff --git a/arch/arm/include/stm32u5/stm32u5xx_irq.h b/arch/arm/include/stm32u5/stm32u5xx_irq.h index f1042c3d4a91d..bb629ca1eeb0e 100644 --- a/arch/arm/include/stm32u5/stm32u5xx_irq.h +++ b/arch/arm/include/stm32u5/stm32u5xx_irq.h @@ -130,11 +130,11 @@ #define STM32_IRQ_TIM16 (STM32_IRQ_FIRST + 70) /* 70: TIM16 global interrupt */ #define STM32_IRQ_TIM17 (STM32_IRQ_FIRST + 71) /* 71: TIM17 global interrupt */ #define STM32_IRQ_COMP (STM32_IRQ_FIRST + 72) /* 72: COMP1/COMP2 interrupts */ -#if defined(CONFIG_STM32U5_STM32U535XX) || defined(CONFIG_STM32U5_STM32U545XX) || \ - defined(CONFIG_STM32U5_STM32U575XX) || defined(CONFIG_STM32U5_STM32U585XX) +#if defined(CONFIG_STM32_STM32U535XX) || defined(CONFIG_STM32_STM32U545XX) || \ + defined(CONFIG_STM32_STM32U575XX) || defined(CONFIG_STM32_STM32U585XX) # define STM32_IRQ_OTG_FS (STM32_IRQ_FIRST + 73) /* 73: USB OTG FS global interrupt */ -#elif defined(CONFIG_STM32U5_STM32U59XX) || defined(CONFIG_STM32U5_STM32U59AXX) || \ - defined(CONFIG_STM32U5_STM32U5A5XX) || defined(CONFIG_STM32U5_STM32U5A9XX) +#elif defined(CONFIG_STM32_STM32U59XX) || defined(CONFIG_STM32_STM32U59AXX) || \ + defined(CONFIG_STM32_STM32U5A5XX) || defined(CONFIG_STM32_STM32U5A9XX) # define STM32_IRQ_OTG_HS (STM32_IRQ_FIRST + 73) /* 73: USB OTG HS global interrupt */ #else # error "Unsupported STM32U5 chip" @@ -191,10 +191,10 @@ #define STM32_IRQ_CORDIC (STM32_IRQ_FIRST + 123) /* 123: CORDIC interrupt */ #define STM32_IRQ_FMAC (STM32_IRQ_FIRST + 124) /* 124: FMAC interrupt */ -#if defined(CONFIG_STM32U5_STM32U535XX) || defined(CONFIG_STM32U5_STM32U545XX) || \ - defined(CONFIG_STM32U5_STM32U575XX) || defined(CONFIG_STM32U5_STM32U585XX) || \ - defined(CONFIG_STM32U5_STM32U59XX) || defined(CONFIG_STM32U5_STM32U59AXX) || \ - defined(CONFIG_STM32U5_STM32U5A5XX) || defined(CONFIG_STM32U5_STM32U5A9XX) +#if defined(CONFIG_STM32_STM32U535XX) || defined(CONFIG_STM32_STM32U545XX) || \ + defined(CONFIG_STM32_STM32U575XX) || defined(CONFIG_STM32_STM32U585XX) || \ + defined(CONFIG_STM32_STM32U59XX) || defined(CONFIG_STM32_STM32U59AXX) || \ + defined(CONFIG_STM32_STM32U5A5XX) || defined(CONFIG_STM32_STM32U5A9XX) # define STM32_IRQ_NEXTINTS 125 #else # error "Unsupported STM32U5 chip" diff --git a/arch/arm/include/stm32wb/chip.h b/arch/arm/include/stm32wb/chip.h index 56d7912fe51fd..6945832aab647 100644 --- a/arch/arm/include/stm32wb/chip.h +++ b/arch/arm/include/stm32wb/chip.h @@ -33,83 +33,83 @@ * Pre-processor Prototypes ****************************************************************************/ -#define STM32WB_NFSMC 0 /* No FSMC */ -#define STM32WB_NBTIM 0 /* No basic timers */ -#define STM32WB_NATIM 1 /* One advanced timers TIM1 */ -#define STM32WB_NGTIM32 1 /* 32-bit general timers TIM2 with DMA */ -#define STM32WB_NLPTIM 2 /* Two low-power timers, LPTIM1-2 */ -#define STM32WB_NGTIMNDMA 0 /* No general timers without DMA */ - -#if defined(CONFIG_STM32WB_STM32WB30) || defined(CONFIG_STM32WB_STM32WB50) \ - || defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55) -# define STM32WB_NGTIM16 2 /* 16-bit general timers TIM16-17 with DMA */ +#define STM32_NFSMC 0 /* No FSMC */ +#define STM32_NBTIM 0 /* No basic timers */ +#define STM32_NATIM 1 /* One advanced timers TIM1 */ +#define STM32_NGTIM32 1 /* 32-bit general timers TIM2 with DMA */ +#define STM32_NLPTIM 2 /* Two low-power timers, LPTIM1-2 */ +#define STM32_NGTIMNDMA 0 /* No general timers without DMA */ + +#if defined(CONFIG_STM32_STM32WB30) || defined(CONFIG_STM32_STM32WB50) \ + || defined(CONFIG_STM32_STM32WB35) || defined(CONFIG_STM32_STM32WB55) +# define STM32_NGTIM16 2 /* 16-bit general timers TIM16-17 with DMA */ #else -# define STM32WB_NGTIM16 0 /* No 16-bit general timers */ +# define STM32_NGTIM16 0 /* No 16-bit general timers */ #endif -#if defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55) -# define STM32WB_NDMA 2 /* DMA1-2 with 7 channels each */ -# define STM32WB_NI2S 1 /* SAI1 (dual channel high quality audio) */ -# define STM32WB_NI2C 2 /* I2C1, I2C3 */ -# define STM32WB_NUSBOTG 1 /* USB 2.0 FS */ -# define STM32WB_NCMP 2 /* Two Comparators */ +#if defined(CONFIG_STM32_STM32WB35) || defined(CONFIG_STM32_STM32WB55) +# define STM32_NDMA 2 /* DMA1-2 with 7 channels each */ +# define STM32_NI2S 1 /* SAI1 (dual channel high quality audio) */ +# define STM32_NI2C 2 /* I2C1, I2C3 */ +# define STM32_NUSBOTG 1 /* USB 2.0 FS */ +# define STM32_NCMP 2 /* Two Comparators */ # if defined(CONFIG_STM32WB_IO_CONFIG_R) || defined(CONFIG_STM32WB_IO_CONFIG_V) -# define STM32WB_NSPI 3 /* SPI1-2, QSPI */ +# define STM32_NSPI 3 /* SPI1-2, QSPI */ # else -# define STM32WB_NSPI 2 /* SPI1, QSPI */ +# define STM32_NSPI 2 /* SPI1, QSPI */ # endif #else -# define STM32WB_NDMA 1 /* DMA1 with 7 channels */ -# define STM32WB_NI2S 0 /* No SAI */ -# define STM32WB_NI2C 1 /* I2C1 */ -# define STM32WB_NUSBOTG 0 /* No USB */ -# define STM32WB_NCMP 0 /* No Comparators */ -# define STM32WB_NSPI 1 /* SPI1 */ +# define STM32_NDMA 1 /* DMA1 with 7 channels */ +# define STM32_NI2S 0 /* No SAI */ +# define STM32_NI2C 1 /* I2C1 */ +# define STM32_NUSBOTG 0 /* No USB */ +# define STM32_NCMP 0 /* No Comparators */ +# define STM32_NSPI 1 /* SPI1 */ #endif -#if defined(CONFIG_STM32WB_STM32WB15) || defined(CONFIG_STM32WB_STM32WB35) \ - || defined(CONFIG_STM32WB_STM32WB55) -# define STM32WB_NLPUART 1 /* LPUART1 */ +#if defined(CONFIG_STM32_STM32WB15) || defined(CONFIG_STM32_STM32WB35) \ + || defined(CONFIG_STM32_STM32WB55) +# define STM32_NLPUART 1 /* LPUART1 */ #else -# define STM32WB_NLPUART 0 /* No LPUART */ +# define STM32_NLPUART 0 /* No LPUART */ #endif #if defined(CONFIG_STM32WB_IO_CONFIG_R) || defined(CONFIG_STM32WB_IO_CONFIG_V) -# define STM32WB_NCAPSENSE 18 /* Capacitive sensing channels */ +# define STM32_NCAPSENSE 18 /* Capacitive sensing channels */ #else -# define STM32WB_NCAPSENSE 0 /* No Capacitive sensing */ +# define STM32_NCAPSENSE 0 /* No Capacitive sensing */ #endif -#if defined(CONFIG_STM32WB_STM32WB55) -# define STM32WB_NLCD 1 /* One LCD controller with up to 8x40 +#if defined(CONFIG_STM32_STM32WB55) +# define STM32_NLCD 1 /* One LCD controller with up to 8x40 * terminals, depending on subfamily. * 55Cx: 4x13 * 55Rx: 4x28 * 55Vx: 4x44, 8x40 */ #else -# define STM32WB_NLCD 0 /* No LCD */ +# define STM32_NLCD 0 /* No LCD */ #endif -#define STM32WB_NUSART 1 /* USART1 */ -#define STM32WB_NCAN 0 /* No CAN */ -#define STM32WB_NSDIO 0 /* No SDIO interface */ -#define STM32WB_NADC 1 /* ADC1, up to 19-channels */ -#define STM32WB_NDAC 0 /* No DAC */ -#define STM32WB_NCRC 1 /* CRC */ -#define STM32WB_NETHERNET 0 /* No ethernet */ -#define STM32WB_NRNG 1 /* Random number generator (RNG) */ -#define STM32WB_NDCMI 0 /* No digital camera interface (DCMI) */ +#define STM32_NUSART 1 /* USART1 */ +#define STM32_NCAN 0 /* No CAN */ +#define STM32_NSDIO 0 /* No SDIO interface */ +#define STM32_NADC 1 /* ADC1, up to 19-channels */ +#define STM32_NDAC 0 /* No DAC */ +#define STM32_NCRC 1 /* CRC */ +#define STM32_NETHERNET 0 /* No ethernet */ +#define STM32_NRNG 1 /* Random number generator (RNG) */ +#define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ #if defined(CONFIG_STM32WB_IO_CONFIG_C) -# define STM32WB_NGPIO 30 /* GPIO[A,B,C,E,H] */ +# define STM32_NGPIO 30 /* GPIO[A,B,C,E,H] */ #elif defined(CONFIG_STM32WB_IO_CONFIG_C_48E) -# define STM32WB_NGPIO 37 /* GPIO[A,B,C,E,H] */ +# define STM32_NGPIO 37 /* GPIO[A,B,C,E,H] */ #elif defined(CONFIG_STM32WB_IO_CONFIG_C_49) -# define STM32WB_NGPIO 25 /* GPIO[A,B,C,H] */ +# define STM32_NGPIO 25 /* GPIO[A,B,C,H] */ #elif defined(CONFIG_STM32WB_IO_CONFIG_R) -# define STM32WB_NGPIO 49 /* GPIO[A,B,C,D,E,H] */ +# define STM32_NGPIO 49 /* GPIO[A,B,C,D,E,H] */ #elif defined(CONFIG_STM32WB_IO_CONFIG_V) -# define STM32WB_NGPIO 72 /* GPIO[A,B,C,D,E,H] */ +# define STM32_NGPIO 72 /* GPIO[A,B,C,D,E,H] */ #else # error "Unsupported STM32WB chip" #endif @@ -138,24 +138,24 @@ * 3) 32 KiB of SRAM2b beginning at address 0x2003:8000 - 0x2004:0000 */ -#if defined(CONFIG_STM32WB_STM32WB10) || defined(CONFIG_STM32WB_STM32WB15) -# define STM32WB_SRAM1_SIZE (12*1024) -# define STM32WB_SRAM2A_SIZE (32*1024) -# define STM32WB_SRAM2B_SIZE (4*1024) -#elif defined(CONFIG_STM32WB_STM32WB30) || defined(CONFIG_STM32WB_STM32WB35) -# define STM32WB_SRAM1_SIZE (32*1024) -# define STM32WB_SRAM2A_SIZE (32*1024) -# define STM32WB_SRAM2B_SIZE (32*1024) -#elif (defined(CONFIG_STM32WB_STM32WB50) || defined(CONFIG_STM32WB_STM32WB55)) \ +#if defined(CONFIG_STM32_STM32WB10) || defined(CONFIG_STM32_STM32WB15) +# define STM32_SRAM1_SIZE (12*1024) +# define STM32_SRAM2A_SIZE (32*1024) +# define STM32_SRAM2B_SIZE (4*1024) +#elif defined(CONFIG_STM32_STM32WB30) || defined(CONFIG_STM32_STM32WB35) +# define STM32_SRAM1_SIZE (32*1024) +# define STM32_SRAM2A_SIZE (32*1024) +# define STM32_SRAM2B_SIZE (32*1024) +#elif (defined(CONFIG_STM32_STM32WB50) || defined(CONFIG_STM32_STM32WB55)) \ && defined(CONFIG_STM32WB_IO_CONFIG_C) -# define STM32WB_SRAM1_SIZE (64*1024) -# define STM32WB_SRAM2A_SIZE (32*1024) -# define STM32WB_SRAM2B_SIZE (32*1024) -#elif defined(CONFIG_STM32WB_STM32WB55) && \ +# define STM32_SRAM1_SIZE (64*1024) +# define STM32_SRAM2A_SIZE (32*1024) +# define STM32_SRAM2B_SIZE (32*1024) +#elif defined(CONFIG_STM32_STM32WB55) && \ (defined(CONFIG_STM32WB_IO_CONFIG_R) || defined(CONFIG_STM32WB_IO_CONFIG_V)) -# define STM32WB_SRAM1_SIZE (192*1024) -# define STM32WB_SRAM2A_SIZE (32*1024) -# define STM32WB_SRAM2B_SIZE (32*1024) +# define STM32_SRAM1_SIZE (192*1024) +# define STM32_SRAM2A_SIZE (32*1024) +# define STM32_SRAM2B_SIZE (32*1024) #else # error "Unsupported STM32WB chip" #endif diff --git a/arch/arm/include/stm32wb/irq.h b/arch/arm/include/stm32wb/irq.h index 6bd24af39e9d4..381c7e9778db8 100644 --- a/arch/arm/include/stm32wb/irq.h +++ b/arch/arm/include/stm32wb/irq.h @@ -44,26 +44,26 @@ /* Processor Exceptions (vectors 0-15) */ -#define STM32WB_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */ - /* Vector 0: Reset stack pointer value */ - /* Vector 1: Reset (not handler as an IRQ) */ -#define STM32WB_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */ -#define STM32WB_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */ -#define STM32WB_IRQ_MEMFAULT (4) /* Vector 4: Memory management (MPU) */ -#define STM32WB_IRQ_BUSFAULT (5) /* Vector 5: Bus fault */ -#define STM32WB_IRQ_USAGEFAULT (6) /* Vector 6: Usage fault */ - /* Vectors 7-10: Reserved */ -#define STM32WB_IRQ_SVCALL (11) /* Vector 11: SVC call */ -#define STM32WB_IRQ_DBGMONITOR (12) /* Vector 12: Debug Monitor */ - /* Vector 13: Reserved */ -#define STM32WB_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */ -#define STM32WB_IRQ_SYSTICK (15) /* Vector 15: System tick */ +#define STM32_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */ + /* Vector 0: Reset stack pointer value */ + /* Vector 1: Reset (not handler as an IRQ) */ +#define STM32_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */ +#define STM32_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */ +#define STM32_IRQ_MEMFAULT (4) /* Vector 4: Memory management (MPU) */ +#define STM32_IRQ_BUSFAULT (5) /* Vector 5: Bus fault */ +#define STM32_IRQ_USAGEFAULT (6) /* Vector 6: Usage fault */ + /* Vectors 7-10: Reserved */ +#define STM32_IRQ_SVCALL (11) /* Vector 11: SVC call */ +#define STM32_IRQ_DBGMONITOR (12) /* Vector 12: Debug Monitor */ + /* Vector 13: Reserved */ +#define STM32_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */ +#define STM32_IRQ_SYSTICK (15) /* Vector 15: System tick */ /* External interrupts (vectors >= 16). These definitions are * chip-specific */ -#define STM32WB_IRQ_FIRST (16) /* Vector number of the first external interrupt */ +#define STM32_IRQ_FIRST (16) /* Vector number of the first external interrupt */ /**************************************************************************** * Included Files diff --git a/arch/arm/include/stm32wb/stm32wb_irq.h b/arch/arm/include/stm32wb/stm32wb_irq.h index 4efaba3559fbb..882ee7971a5a1 100644 --- a/arch/arm/include/stm32wb/stm32wb_irq.h +++ b/arch/arm/include/stm32wb/stm32wb_irq.h @@ -24,8 +24,8 @@ * through arch/irq.h */ -#ifndef __ARCH_ARM_INCLUDE_STM32WB_STM32WB_IRQ_H -#define __ARCH_ARM_INCLUDE_STM32WB_STM32WB_IRQ_H +#ifndef __ARCH_ARM_INCLUDE_STM32WB_STM32_IRQ_H +#define __ARCH_ARM_INCLUDE_STM32WB_STM32_IRQ_H /**************************************************************************** * Included Files @@ -51,146 +51,146 @@ * */ -#define STM32WB_IRQ_WWDG (STM32WB_IRQ_FIRST + 0) /* 0: Window Watchdog interrupt */ -#define STM32WB_IRQ_PVD (STM32WB_IRQ_FIRST + 1) /* 1: PVD through EXTI[16] Line detection interrupt */ +#define STM32_IRQ_WWDG (STM32_IRQ_FIRST + 0) /* 0: Window Watchdog interrupt */ +#define STM32_IRQ_PVD (STM32_IRQ_FIRST + 1) /* 1: PVD through EXTI[16] Line detection interrupt */ -#if defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55) -# define STM32WB_IRQ_PVM1 (STM32WB_IRQ_FIRST + 1) /* 1: PVM1 through EXTI[31] Line detection interrupt */ +#if defined(CONFIG_STM32_STM32WB35) || defined(CONFIG_STM32_STM32WB55) +# define STM32_IRQ_PVM1 (STM32_IRQ_FIRST + 1) /* 1: PVM1 through EXTI[31] Line detection interrupt */ #endif -#if defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55) \ - || defined(CONFIG_STM32WB_STM32WB15) -# define STM32WB_IRQ_PVM3 (STM32WB_IRQ_FIRST + 1) /* 1: PVM3 through EXTI[33] Line detection interrupt */ +#if defined(CONFIG_STM32_STM32WB35) || defined(CONFIG_STM32_STM32WB55) \ + || defined(CONFIG_STM32_STM32WB15) +# define STM32_IRQ_PVM3 (STM32_IRQ_FIRST + 1) /* 1: PVM3 through EXTI[33] Line detection interrupt */ #endif -#define STM32WB_IRQ_TAMPER (STM32WB_IRQ_FIRST + 2) /* 2: Tamper through EXTI[18] interrupts */ -#define STM32WB_IRQ_TIMESTAMP (STM32WB_IRQ_FIRST + 2) /* 2: Time stamp through EXTI[18] interrupts */ -#define STM32WB_IRQ_LSECSS (STM32WB_IRQ_FIRST + 2) /* 2: LSECSS through EXTI[18] interrupts */ -#define STM32WB_IRQ_RTC_WKUP (STM32WB_IRQ_FIRST + 3) /* 3: RTC global interrupt */ -#define STM32WB_IRQ_FLASH (STM32WB_IRQ_FIRST + 4) /* 4: Flash global interrupt */ -#define STM32WB_IRQ_RCC (STM32WB_IRQ_FIRST + 5) /* 5: RCC global interrupt */ -#define STM32WB_IRQ_EXTI0 (STM32WB_IRQ_FIRST + 6) /* 6: EXTI Line 0 interrupt */ -#define STM32WB_IRQ_EXTI1 (STM32WB_IRQ_FIRST + 7) /* 7: EXTI Line 1 interrupt */ -#define STM32WB_IRQ_EXTI2 (STM32WB_IRQ_FIRST + 8) /* 8: EXTI Line 2 interrupt */ -#define STM32WB_IRQ_EXTI3 (STM32WB_IRQ_FIRST + 9) /* 9: EXTI Line 3 interrupt */ -#define STM32WB_IRQ_EXTI4 (STM32WB_IRQ_FIRST + 10) /* 10: EXTI Line 4 interrupt */ -#define STM32WB_IRQ_DMA1CH1 (STM32WB_IRQ_FIRST + 11) /* 11: DMA1 Channel 1 global interrupt */ -#define STM32WB_IRQ_DMA1CH2 (STM32WB_IRQ_FIRST + 12) /* 12: DMA1 Channel 2 global interrupt */ -#define STM32WB_IRQ_DMA1CH3 (STM32WB_IRQ_FIRST + 13) /* 13: DMA1 Channel 3 global interrupt */ -#define STM32WB_IRQ_DMA1CH4 (STM32WB_IRQ_FIRST + 14) /* 14: DMA1 Channel 4 global interrupt */ -#define STM32WB_IRQ_DMA1CH5 (STM32WB_IRQ_FIRST + 15) /* 15: DMA1 Channel 5 global interrupt */ -#define STM32WB_IRQ_DMA1CH6 (STM32WB_IRQ_FIRST + 16) /* 16: DMA1 Channel 6 global interrupt */ -#define STM32WB_IRQ_DMA1CH7 (STM32WB_IRQ_FIRST + 17) /* 17: DMA1 Channel 7 global interrupt */ -#define STM32WB_IRQ_ADC1 (STM32WB_IRQ_FIRST + 18) /* 18: ADC1 global interrupt */ +#define STM32_IRQ_TAMPER (STM32_IRQ_FIRST + 2) /* 2: Tamper through EXTI[18] interrupts */ +#define STM32_IRQ_TIMESTAMP (STM32_IRQ_FIRST + 2) /* 2: Time stamp through EXTI[18] interrupts */ +#define STM32_IRQ_LSECSS (STM32_IRQ_FIRST + 2) /* 2: LSECSS through EXTI[18] interrupts */ +#define STM32_IRQ_RTC_WKUP (STM32_IRQ_FIRST + 3) /* 3: RTC global interrupt */ +#define STM32_IRQ_FLASH (STM32_IRQ_FIRST + 4) /* 4: Flash global interrupt */ +#define STM32_IRQ_RCC (STM32_IRQ_FIRST + 5) /* 5: RCC global interrupt */ +#define STM32_IRQ_EXTI0 (STM32_IRQ_FIRST + 6) /* 6: EXTI Line 0 interrupt */ +#define STM32_IRQ_EXTI1 (STM32_IRQ_FIRST + 7) /* 7: EXTI Line 1 interrupt */ +#define STM32_IRQ_EXTI2 (STM32_IRQ_FIRST + 8) /* 8: EXTI Line 2 interrupt */ +#define STM32_IRQ_EXTI3 (STM32_IRQ_FIRST + 9) /* 9: EXTI Line 3 interrupt */ +#define STM32_IRQ_EXTI4 (STM32_IRQ_FIRST + 10) /* 10: EXTI Line 4 interrupt */ +#define STM32_IRQ_DMA1CH1 (STM32_IRQ_FIRST + 11) /* 11: DMA1 Channel 1 global interrupt */ +#define STM32_IRQ_DMA1CH2 (STM32_IRQ_FIRST + 12) /* 12: DMA1 Channel 2 global interrupt */ +#define STM32_IRQ_DMA1CH3 (STM32_IRQ_FIRST + 13) /* 13: DMA1 Channel 3 global interrupt */ +#define STM32_IRQ_DMA1CH4 (STM32_IRQ_FIRST + 14) /* 14: DMA1 Channel 4 global interrupt */ +#define STM32_IRQ_DMA1CH5 (STM32_IRQ_FIRST + 15) /* 15: DMA1 Channel 5 global interrupt */ +#define STM32_IRQ_DMA1CH6 (STM32_IRQ_FIRST + 16) /* 16: DMA1 Channel 6 global interrupt */ +#define STM32_IRQ_DMA1CH7 (STM32_IRQ_FIRST + 17) /* 17: DMA1 Channel 7 global interrupt */ +#define STM32_IRQ_ADC1 (STM32_IRQ_FIRST + 18) /* 18: ADC1 global interrupt */ -#if defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55) - #define STM32WB_IRQ_USB_HP (STM32WB_IRQ_FIRST + 19) /* 19: USB High Priority Interrupt */ - #define STM32WB_IRQ_USB_LP (STM32WB_IRQ_FIRST + 20) /* 20: USB Low Priority Interrupt */ +#if defined(CONFIG_STM32_STM32WB35) || defined(CONFIG_STM32_STM32WB55) + #define STM32_IRQ_USB_HP (STM32_IRQ_FIRST + 19) /* 19: USB High Priority Interrupt */ + #define STM32_IRQ_USB_LP (STM32_IRQ_FIRST + 20) /* 20: USB Low Priority Interrupt */ #endif -#define STM32WB_IRQ_C2SEV (STM32WB_IRQ_FIRST + 21) /* 21: CPU2 SEV Interrupt */ +#define STM32_IRQ_C2SEV (STM32_IRQ_FIRST + 21) /* 21: CPU2 SEV Interrupt */ -#if defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55) \ - || defined(CONFIG_STM32WB_STM32WB15) -# define STM32WB_IRQ_COMP (STM32WB_IRQ_FIRST + 22) /* 22: COMP1/COMP2 Interrupts */ +#if defined(CONFIG_STM32_STM32WB35) || defined(CONFIG_STM32_STM32WB55) \ + || defined(CONFIG_STM32_STM32WB15) +# define STM32_IRQ_COMP (STM32_IRQ_FIRST + 22) /* 22: COMP1/COMP2 Interrupts */ #endif -#define STM32WB_IRQ_EXTI95 (STM32WB_IRQ_FIRST + 23) /* 23: EXTI Lines [9:5] Interrupt */ -#define STM32WB_IRQ_TIM1BRK (STM32WB_IRQ_FIRST + 24) /* 24: TIM1 Break interrupt */ -#define STM32WB_IRQ_TIM1UP (STM32WB_IRQ_FIRST + 25) /* 25: TIM1 Update interrupt */ -#define STM32WB_IRQ_TIM1TRGCOM (STM32WB_IRQ_FIRST + 26) /* 26: TIM1 Trigger and Communication Interrupts */ +#define STM32_IRQ_EXTI95 (STM32_IRQ_FIRST + 23) /* 23: EXTI Lines [9:5] Interrupt */ +#define STM32_IRQ_TIM1BRK (STM32_IRQ_FIRST + 24) /* 24: TIM1 Break interrupt */ +#define STM32_IRQ_TIM1UP (STM32_IRQ_FIRST + 25) /* 25: TIM1 Update interrupt */ +#define STM32_IRQ_TIM1TRGCOM (STM32_IRQ_FIRST + 26) /* 26: TIM1 Trigger and Communication Interrupts */ -#if defined(CONFIG_STM32WB_STM32WB30) || defined(CONFIG_STM32WB_STM32WB50) \ - || defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55) -# define STM32WB_IRQ_TIM16 (STM32WB_IRQ_FIRST + 25) /* 25: TIM16 global interrupt */ -# define STM32WB_IRQ_TIM17 (STM32WB_IRQ_FIRST + 26) /* 26: TIM17 global interrupt */ +#if defined(CONFIG_STM32_STM32WB30) || defined(CONFIG_STM32_STM32WB50) \ + || defined(CONFIG_STM32_STM32WB35) || defined(CONFIG_STM32_STM32WB55) +# define STM32_IRQ_TIM16 (STM32_IRQ_FIRST + 25) /* 25: TIM16 global interrupt */ +# define STM32_IRQ_TIM17 (STM32_IRQ_FIRST + 26) /* 26: TIM17 global interrupt */ #endif -#define STM32WB_IRQ_TIM1CC (STM32WB_IRQ_FIRST + 27) /* 27: TIM1 Capture Compare interrupt */ -#define STM32WB_IRQ_TIM2 (STM32WB_IRQ_FIRST + 28) /* 28: TIM2 global interrupt */ -#define STM32WB_IRQ_PKA (STM32WB_IRQ_FIRST + 29) /* 29: PKA Interrupt */ -#define STM32WB_IRQ_I2C1EV (STM32WB_IRQ_FIRST + 30) /* 30: I2C1 event interrupt */ -#define STM32WB_IRQ_I2C1ER (STM32WB_IRQ_FIRST + 31) /* 31: I2C1 error interrupt */ +#define STM32_IRQ_TIM1CC (STM32_IRQ_FIRST + 27) /* 27: TIM1 Capture Compare interrupt */ +#define STM32_IRQ_TIM2 (STM32_IRQ_FIRST + 28) /* 28: TIM2 global interrupt */ +#define STM32_IRQ_PKA (STM32_IRQ_FIRST + 29) /* 29: PKA Interrupt */ +#define STM32_IRQ_I2C1EV (STM32_IRQ_FIRST + 30) /* 30: I2C1 event interrupt */ +#define STM32_IRQ_I2C1ER (STM32_IRQ_FIRST + 31) /* 31: I2C1 error interrupt */ -#if defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55) -# define STM32WB_IRQ_I2C3EV (STM32WB_IRQ_FIRST + 32) /* 32: I2C3 event interrupt */ -# define STM32WB_IRQ_I2C3ER (STM32WB_IRQ_FIRST + 33) /* 33: I2C3 error interrupt */ +#if defined(CONFIG_STM32_STM32WB35) || defined(CONFIG_STM32_STM32WB55) +# define STM32_IRQ_I2C3EV (STM32_IRQ_FIRST + 32) /* 32: I2C3 event interrupt */ +# define STM32_IRQ_I2C3ER (STM32_IRQ_FIRST + 33) /* 33: I2C3 error interrupt */ #endif -#define STM32WB_IRQ_SPI1 (STM32WB_IRQ_FIRST + 34) /* 34: SPI1 global interrupt */ +#define STM32_IRQ_SPI1 (STM32_IRQ_FIRST + 34) /* 34: SPI1 global interrupt */ -#if defined(CONFIG_STM32WB_STM32WB55) -# define STM32WB_IRQ_SPI2 (STM32WB_IRQ_FIRST + 35) /* 35: SPI2 global interrupt */ +#if defined(CONFIG_STM32_STM32WB55) +# define STM32_IRQ_SPI2 (STM32_IRQ_FIRST + 35) /* 35: SPI2 global interrupt */ #endif -#define STM32WB_IRQ_USART1 (STM32WB_IRQ_FIRST + 36) /* 36: USART1 global interrupt */ +#define STM32_IRQ_USART1 (STM32_IRQ_FIRST + 36) /* 36: USART1 global interrupt */ -#if defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55) \ - || defined(CONFIG_STM32WB_STM32WB15) -# define STM32WB_IRQ_LPUART1 (STM32WB_IRQ_FIRST + 37) /* 37: LPUART1 global interrupt */ +#if defined(CONFIG_STM32_STM32WB35) || defined(CONFIG_STM32_STM32WB55) \ + || defined(CONFIG_STM32_STM32WB15) +# define STM32_IRQ_LPUART1 (STM32_IRQ_FIRST + 37) /* 37: LPUART1 global interrupt */ #endif -#if defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55) -# define STM32WB_IRQ_SAI1 (STM32WB_IRQ_FIRST + 38) /* 38: SAI1 A/B global interrupt */ +#if defined(CONFIG_STM32_STM32WB35) || defined(CONFIG_STM32_STM32WB55) +# define STM32_IRQ_SAI1 (STM32_IRQ_FIRST + 38) /* 38: SAI1 A/B global interrupt */ #endif -#if defined(CONFIG_STM32WB_STM32WB10) || defined(CONFIG_STM32WB_STM32WB15) \ - || defined(CONFIG_STM32WB_STM32WB55) -# define STM32WB_IRQ_TSC (STM32WB_IRQ_FIRST + 39) /* 39: TSC global interrupt */ +#if defined(CONFIG_STM32_STM32WB10) || defined(CONFIG_STM32_STM32WB15) \ + || defined(CONFIG_STM32_STM32WB55) +# define STM32_IRQ_TSC (STM32_IRQ_FIRST + 39) /* 39: TSC global interrupt */ #endif -#define STM32WB_IRQ_EXTI1510 (STM32WB_IRQ_FIRST + 40) /* 40: EXTI Line[15:10] interrupts */ -#define STM32WB_IRQ_RTCALRM (STM32WB_IRQ_FIRST + 41) /* 41: RTC alarm A/B interrupt */ +#define STM32_IRQ_EXTI1510 (STM32_IRQ_FIRST + 40) /* 40: EXTI Line[15:10] interrupts */ +#define STM32_IRQ_RTCALRM (STM32_IRQ_FIRST + 41) /* 41: RTC alarm A/B interrupt */ -#if defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55) -# define STM32WB_IRQ_CRS (STM32WB_IRQ_FIRST + 42) /* 42: CRS interrupt */ +#if defined(CONFIG_STM32_STM32WB35) || defined(CONFIG_STM32_STM32WB55) +# define STM32_IRQ_CRS (STM32_IRQ_FIRST + 42) /* 42: CRS interrupt */ #endif -#define STM32WB_IRQ_PWRSOTF (STM32WB_IRQ_FIRST + 43) /* 43: PWR switching on the fly interrupt */ -#define STM32WB_IRQ_PWRBLEACT (STM32WB_IRQ_FIRST + 43) /* 43: PWR end of BLE activity interrupt */ -#define STM32WB_IRQ_PWRRFPHASE (STM32WB_IRQ_FIRST + 43) /* 43: PWR end of critical radio phase interrupt */ +#define STM32_IRQ_PWRSOTF (STM32_IRQ_FIRST + 43) /* 43: PWR switching on the fly interrupt */ +#define STM32_IRQ_PWRBLEACT (STM32_IRQ_FIRST + 43) /* 43: PWR end of BLE activity interrupt */ +#define STM32_IRQ_PWRRFPHASE (STM32_IRQ_FIRST + 43) /* 43: PWR end of critical radio phase interrupt */ -#if defined(CONFIG_STM32WB_STM32WB30) || defined(CONFIG_STM32WB_STM32WB50) \ - || defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55) -# define STM32WB_IRQ_PWR802ACT (STM32WB_IRQ_FIRST + 43) /* 43: PWR end of 802.15.4 activity interrupt */ +#if defined(CONFIG_STM32_STM32WB30) || defined(CONFIG_STM32_STM32WB50) \ + || defined(CONFIG_STM32_STM32WB35) || defined(CONFIG_STM32_STM32WB55) +# define STM32_IRQ_PWR802ACT (STM32_IRQ_FIRST + 43) /* 43: PWR end of 802.15.4 activity interrupt */ #endif -#define STM32WB_IRQ_IPCCRX (STM32WB_IRQ_FIRST + 44) /* 44: IPCC RX occupied interrupt */ -#define STM32WB_IRQ_IPCCTX (STM32WB_IRQ_FIRST + 45) /* 45: IPCC TX free interrupt */ -#define STM32WB_IRQ_HSEM (STM32WB_IRQ_FIRST + 46) /* 46: Semaphore interrupt 0 to CPU1 */ -#define STM32WB_IRQ_LPTIM1 (STM32WB_IRQ_FIRST + 47) /* 47: LPTIM1 global interrupt */ -#define STM32WB_IRQ_LPTIM2 (STM32WB_IRQ_FIRST + 48) /* 48: LPTIM2 global interrupt */ +#define STM32_IRQ_IPCCRX (STM32_IRQ_FIRST + 44) /* 44: IPCC RX occupied interrupt */ +#define STM32_IRQ_IPCCTX (STM32_IRQ_FIRST + 45) /* 45: IPCC TX free interrupt */ +#define STM32_IRQ_HSEM (STM32_IRQ_FIRST + 46) /* 46: Semaphore interrupt 0 to CPU1 */ +#define STM32_IRQ_LPTIM1 (STM32_IRQ_FIRST + 47) /* 47: LPTIM1 global interrupt */ +#define STM32_IRQ_LPTIM2 (STM32_IRQ_FIRST + 48) /* 48: LPTIM2 global interrupt */ -#if defined(CONFIG_STM32WB_STM32WB55) -# define STM32WB_IRQ_LCD (STM32WB_IRQ_FIRST + 49) /* 49: LCD global interrupt */ +#if defined(CONFIG_STM32_STM32WB55) +# define STM32_IRQ_LCD (STM32_IRQ_FIRST + 49) /* 49: LCD global interrupt */ #endif -#if defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55) -# define STM32WB_IRQ_QUADSPI (STM32WB_IRQ_FIRST + 50) /* 50: QUADSPI global interrupt */ -# define STM32WB_IRQ_AES1 (STM32WB_IRQ_FIRST + 51) /* 51: AES1 crypto global interrupt */ +#if defined(CONFIG_STM32_STM32WB35) || defined(CONFIG_STM32_STM32WB55) +# define STM32_IRQ_QUADSPI (STM32_IRQ_FIRST + 50) /* 50: QUADSPI global interrupt */ +# define STM32_IRQ_AES1 (STM32_IRQ_FIRST + 51) /* 51: AES1 crypto global interrupt */ #endif -#define STM32WB_IRQ_AES2 (STM32WB_IRQ_FIRST + 52) /* 52: AES2 crypto global interrupt */ -#define STM32WB_IRQ_RNG (STM32WB_IRQ_FIRST + 53) /* 53: RNG global interrupt */ -#define STM32WB_IRQ_FPU (STM32WB_IRQ_FIRST + 54) /* 54: FPU global interrupt */ +#define STM32_IRQ_AES2 (STM32_IRQ_FIRST + 52) /* 52: AES2 crypto global interrupt */ +#define STM32_IRQ_RNG (STM32_IRQ_FIRST + 53) /* 53: RNG global interrupt */ +#define STM32_IRQ_FPU (STM32_IRQ_FIRST + 54) /* 54: FPU global interrupt */ -#if defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55) -# define STM32WB_IRQ_DMA2CH1 (STM32WB_IRQ_FIRST + 55) /* 55: DMA2 Channel 1 global interrupt */ -# define STM32WB_IRQ_DMA2CH2 (STM32WB_IRQ_FIRST + 56) /* 56: DMA2 Channel 2 global interrupt */ -# define STM32WB_IRQ_DMA2CH3 (STM32WB_IRQ_FIRST + 57) /* 57: DMA2 Channel 3 global interrupt */ -# define STM32WB_IRQ_DMA2CH4 (STM32WB_IRQ_FIRST + 58) /* 58: DMA2 Channel 4 global interrupt */ -# define STM32WB_IRQ_DMA2CH5 (STM32WB_IRQ_FIRST + 59) /* 59: DMA2 Channel 5 global interrupt */ -# define STM32WB_IRQ_DMA2CH6 (STM32WB_IRQ_FIRST + 60) /* 60: DMA2 Channel 6 global interrupt */ -# define STM32WB_IRQ_DMA2CH7 (STM32WB_IRQ_FIRST + 61) /* 61: DMA2 Channel 7 global interrupt */ +#if defined(CONFIG_STM32_STM32WB35) || defined(CONFIG_STM32_STM32WB55) +# define STM32_IRQ_DMA2CH1 (STM32_IRQ_FIRST + 55) /* 55: DMA2 Channel 1 global interrupt */ +# define STM32_IRQ_DMA2CH2 (STM32_IRQ_FIRST + 56) /* 56: DMA2 Channel 2 global interrupt */ +# define STM32_IRQ_DMA2CH3 (STM32_IRQ_FIRST + 57) /* 57: DMA2 Channel 3 global interrupt */ +# define STM32_IRQ_DMA2CH4 (STM32_IRQ_FIRST + 58) /* 58: DMA2 Channel 4 global interrupt */ +# define STM32_IRQ_DMA2CH5 (STM32_IRQ_FIRST + 59) /* 59: DMA2 Channel 5 global interrupt */ +# define STM32_IRQ_DMA2CH6 (STM32_IRQ_FIRST + 60) /* 60: DMA2 Channel 6 global interrupt */ +# define STM32_IRQ_DMA2CH7 (STM32_IRQ_FIRST + 61) /* 61: DMA2 Channel 7 global interrupt */ #endif -#define STM32WB_IRQ_DMAMUX1 (STM32WB_IRQ_FIRST + 62) /* 62: DMAMUX1 overrun interrupt */ +#define STM32_IRQ_DMAMUX1 (STM32_IRQ_FIRST + 62) /* 62: DMAMUX1 overrun interrupt */ -#define STM32WB_IRQ_NEXTINTS 63 +#define STM32_IRQ_NEXTINTS 63 /* (EXTI interrupts do not use IRQ numbers) */ -#define NR_IRQS (STM32WB_IRQ_FIRST + STM32WB_IRQ_NEXTINTS) +#define NR_IRQS (STM32_IRQ_FIRST + STM32_IRQ_NEXTINTS) /**************************************************************************** * Public Types @@ -219,4 +219,4 @@ extern "C" #endif #endif -#endif /* __ARCH_ARM_INCLUDE_STM32WB_STM32WB_IRQ_H */ +#endif /* __ARCH_ARM_INCLUDE_STM32WB_STM32_IRQ_H */ diff --git a/arch/arm/include/stm32wl5/chip.h b/arch/arm/include/stm32wl5/chip.h index d7da1c8c45ee6..95761ec558f53 100644 --- a/arch/arm/include/stm32wl5/chip.h +++ b/arch/arm/include/stm32wl5/chip.h @@ -33,30 +33,30 @@ * Pre-processor Prototypes ****************************************************************************/ -#if defined(CONFIG_STM32WL5_STM32WL5XXX) -# define STM32WL5_SRAM1_SIZE (32*1024) /* 32kB SRAM1 on AHB bus Matrix */ -# define STM32WL5_SRAM2_SIZE (32*1024) /* 32kB SRAM2 on AHB bus Matrix */ +#if defined(CONFIG_STM32_STM32WL5XXX) +# define STM32_SRAM1_SIZE (32*1024) /* 32kB SRAM1 on AHB bus Matrix */ +# define STM32_SRAM2_SIZE (32*1024) /* 32kB SRAM2 on AHB bus Matrix */ #else # error "Unsupported STM32L5 chip" #endif -#if defined(CONFIG_STM32WL5_STM32WL5XXX_CPU1) -# define STM32WL5_NATIM 1 /* One advanced timer TIM1 */ -# define STM32WL5_NGTIM32 1 /* 32-bit general timer TIM2 with DMA */ -# define STM32WL5_NGTIM16 2 /* 16-bit general timers TIM16 and 17 with DMA */ -# define STM32WL5_NLPTIM 3 /* Three low-power timer, LPTIM1-3 */ -# define STM32WL5_NRNG 1 /* Random number generator (RNG) */ -# define STM32WL5_NUSART 2 /* USART 1-2 */ -# define STM32WL5_NLPUART 1 /* LPUART 1 */ -# define STM32WL5_NSPI 2 /* SPI1 and SPI2S2 (spi2 shared with i2s) */ -# define STM32WL5_NI2C 3 /* I2C1-3 */ -# define STM32WL5_NDMA 2 /* Two DMA channels DMA1-2 */ -# define STM32WL5_NPORTS 4 /* GPIO{A,B,C,H} */ -# define STM32WL5_NADC 1 /* ADC1 */ -# define STM32WL5_NDAC 1 /* DAC1 */ -# define STM32WL5_NCRC 1 /* CRC1 */ -# define STM32WL5_NCOMP 1 /* COMP1 */ -#endif /* CONFIG_STM32WL5_STM32WL5XXX */ +#if defined(CONFIG_STM32_STM32WL5XXX_CPU1) +# define STM32_NATIM 1 /* One advanced timer TIM1 */ +# define STM32_NGTIM32 1 /* 32-bit general timer TIM2 with DMA */ +# define STM32_NGTIM16 2 /* 16-bit general timers TIM16 and 17 with DMA */ +# define STM32_NLPTIM 3 /* Three low-power timer, LPTIM1-3 */ +# define STM32_NRNG 1 /* Random number generator (RNG) */ +# define STM32_NUSART 2 /* USART 1-2 */ +# define STM32_NLPUART 1 /* LPUART 1 */ +# define STM32_NSPI 2 /* SPI1 and SPI2S2 (spi2 shared with i2s) */ +# define STM32_NI2C 3 /* I2C1-3 */ +# define STM32_NDMA 2 /* Two DMA channels DMA1-2 */ +# define STM32_NPORTS 4 /* GPIO{A,B,C,H} */ +# define STM32_NADC 1 /* ADC1 */ +# define STM32_NDAC 1 /* DAC1 */ +# define STM32_NCRC 1 /* CRC1 */ +# define STM32_NCOMP 1 /* COMP1 */ +#endif /* CONFIG_STM32_STM32WL5XXX */ /* NVIC priority levels *****************************************************/ diff --git a/arch/arm/include/stm32wl5/irq.h b/arch/arm/include/stm32wl5/irq.h index a8941dbeed680..500a3b957c30e 100644 --- a/arch/arm/include/stm32wl5/irq.h +++ b/arch/arm/include/stm32wl5/irq.h @@ -44,32 +44,32 @@ /* Processor Exceptions (vectors 0-15) */ -#define STM32WL5_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */ - /* Vector 0: Reset stack pointer value */ - /* Vector 1: Reset (not handler as an IRQ) */ -#define STM32WL5_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */ -#define STM32WL5_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */ -#define STM32WL5_IRQ_MEMFAULT (4) /* Vector 4: Memory management (MPU) */ -#define STM32WL5_IRQ_BUSFAULT (5) /* Vector 5: Bus fault */ -#define STM32WL5_IRQ_USAGEFAULT (6) /* Vector 6: Usage fault */ - /* Vectors 7-10: Reserved */ -#define STM32WL5_IRQ_SVCALL (11) /* Vector 11: SVC call */ -#define STM32WL5_IRQ_DBGMONITOR (12) /* Vector 12: Debug Monitor */ - /* Vector 13: Reserved */ -#define STM32WL5_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */ -#define STM32WL5_IRQ_SYSTICK (15) /* Vector 15: System tick */ +#define STM32_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */ + /* Vector 0: Reset stack pointer value */ + /* Vector 1: Reset (not handler as an IRQ) */ +#define STM32_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */ +#define STM32_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */ +#define STM32_IRQ_MEMFAULT (4) /* Vector 4: Memory management (MPU) */ +#define STM32_IRQ_BUSFAULT (5) /* Vector 5: Bus fault */ +#define STM32_IRQ_USAGEFAULT (6) /* Vector 6: Usage fault */ + /* Vectors 7-10: Reserved */ +#define STM32_IRQ_SVCALL (11) /* Vector 11: SVC call */ +#define STM32_IRQ_DBGMONITOR (12) /* Vector 12: Debug Monitor */ + /* Vector 13: Reserved */ +#define STM32_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */ +#define STM32_IRQ_SYSTICK (15) /* Vector 15: System tick */ /* External interrupts (vectors >= 16). These definitions are * chip-specific */ -#define STM32WL5_IRQ_FIRST (16) /* Vector number of the first external interrupt */ +#define STM32_IRQ_FIRST (16) /* Vector number of the first external interrupt */ /**************************************************************************** * Included Files ****************************************************************************/ -#if defined(CONFIG_STM32WL5_STM32WL5XXX_CPU1) +#if defined(CONFIG_STM32_STM32WL5XXX_CPU1) # include #else # error "Unsupported STM32 L5 chip" diff --git a/arch/arm/include/stm32wl5/stm32wl5xxx_cpu1_irq.h b/arch/arm/include/stm32wl5/stm32wl5xxx_cpu1_irq.h index 88ce31efc5a24..a8c99354b2159 100644 --- a/arch/arm/include/stm32wl5/stm32wl5xxx_cpu1_irq.h +++ b/arch/arm/include/stm32wl5/stm32wl5xxx_cpu1_irq.h @@ -48,80 +48,80 @@ * External interrupts (vectors >= 16) */ -#define STM32WL5_IRQ_WWDG (STM32WL5_IRQ_FIRST + 0) /* 0: Window watchdog early wakeup */ -#define STM32WL5_IRQ_PVD (STM32WL5_IRQ_FIRST + 1) /* 1: PVD through EXTI[16] */ -#define STM32WL5_IRQ_PVM (STM32WL5_IRQ_FIRST + 1) /* 1: PVM through EXTI[34] */ -#define STM32WL5_IRQ_TAMPER (STM32WL5_IRQ_FIRST + 2) /* 2: Tamper */ -#define STM32WL5_IRQ_LSE_CSS (STM32WL5_IRQ_FIRST + 2) /* 2: LSECSS */ -#define STM32WL5_IRQ_RTC_STAMP (STM32WL5_IRQ_FIRST + 2) /* 2: timestamp */ -#define STM32WL5_IRQ_RTC_SSRU (STM32WL5_IRQ_FIRST + 2) /* 2: RTC SSR underflow */ -#define STM32WL5_IRQ_RTC_WKUP (STM32WL5_IRQ_FIRST + 3) /* 3: RTC wakeup interrupt */ -#define STM32WL5_IRQ_FLASH (STM32WL5_IRQ_FIRST + 4) /* 4: Flash memory global interrupt and Flash memory ECC single error interrupt */ -#define STM32WL5_IRQ_RCC (STM32WL5_IRQ_FIRST + 5) /* 5: RCC global interrupt */ -#define STM32WL5_IRQ_EXTI0 (STM32WL5_IRQ_FIRST + 6) /* 6: EXTI line 0 interrupt through EXTI[0] */ -#define STM32WL5_IRQ_EXTI1 (STM32WL5_IRQ_FIRST + 7) /* 7: EXTI line 1 interrupt through EXTI[1] */ -#define STM32WL5_IRQ_EXTI2 (STM32WL5_IRQ_FIRST + 8) /* 8: EXTI line 2 interrupt through EXTI[2] */ -#define STM32WL5_IRQ_EXTI3 (STM32WL5_IRQ_FIRST + 9) /* 9: EXTI line 3 interrupt through EXTI[3] */ -#define STM32WL5_IRQ_EXTI4 (STM32WL5_IRQ_FIRST + 10) /* 10: EXTI line 4 interrupt through EXTI[4] */ -#define STM32WL5_IRQ_DMA1CH1 (STM32WL5_IRQ_FIRST + 11) /* 11: DMA1 channel 1 non-secure interrupt */ -#define STM32WL5_IRQ_DMA1CH2 (STM32WL5_IRQ_FIRST + 12) /* 12: DMA1 channel 2 non-secure interrupt */ -#define STM32WL5_IRQ_DMA1CH3 (STM32WL5_IRQ_FIRST + 13) /* 13: DMA1 channel 3 non-secure interrupt */ -#define STM32WL5_IRQ_DMA1CH4 (STM32WL5_IRQ_FIRST + 14) /* 14: DMA1 channel 4 non-secure interrupt */ -#define STM32WL5_IRQ_DMA1CH5 (STM32WL5_IRQ_FIRST + 15) /* 15: DMA1 channel 5 non-secure interrupt */ -#define STM32WL5_IRQ_DMA1CH6 (STM32WL5_IRQ_FIRST + 16) /* 16: DMA1 channel 6 non-secure interrupt */ -#define STM32WL5_IRQ_DMA1CH7 (STM32WL5_IRQ_FIRST + 17) /* 17: DMA1 channel 7 non-secure interrupt */ -#define STM32WL5_IRQ_ADC (STM32WL5_IRQ_FIRST + 18) /* 18: ADC global interrupt */ -#define STM32WL5_IRQ_DAC (STM32WL5_IRQ_FIRST + 19) /* 19: DAC global interrupt */ -#define STM32WL5_IRQ_C2SEV (STM32WL5_IRQ_FIRST + 20) /* 20: CPU2 SEV through EXTI[40] */ -#define STM32WL5_IRQ_PWRC2H (STM32WL5_IRQ_FIRST + 20) /* 20: PWR CPU2 HOLD wakeup */ -#define STM32WL5_IRQ_COMP (STM32WL5_IRQ_FIRST + 21) /* 21: COMP2 and COMP1 interrupt through EXTI[22:21] */ -#define STM32WL5_IRQ_EXTI95 (STM32WL5_IRQ_FIRST + 22) /* 22: EXTI line [9:5] interrupt through EXTI[9:5] */ -#define STM32WL5_IRQ_TIM1BRK (STM32WL5_IRQ_FIRST + 23) /* 23: Timer 1 break interrupt */ -#define STM32WL5_IRQ_TIM1UP (STM32WL5_IRQ_FIRST + 24) /* 24: Timer 1 Update */ -#define STM32WL5_IRQ_TIM1TRG_COM (STM32WL5_IRQ_FIRST + 25) /* 25: Timer 1 trigger and communication */ -#define STM32WL5_IRQ_TIM1CC (STM32WL5_IRQ_FIRST + 26) /* 26: Timer 1 capture compare interrupt */ -#define STM32WL5_IRQ_TIM2 (STM32WL5_IRQ_FIRST + 27) /* 27: Timer 2 global interrupt */ -#define STM32WL5_IRQ_TIM16 (STM32WL5_IRQ_FIRST + 28) /* 28: Timer 16 global interrupt */ -#define STM32WL5_IRQ_TIM17 (STM32WL5_IRQ_FIRST + 29) /* 29: Timer 17 global interrupt */ -#define STM32WL5_IRQ_I2C1EV (STM32WL5_IRQ_FIRST + 30) /* 30: I2C1 event interrupt */ -#define STM32WL5_IRQ_I2C1ER (STM32WL5_IRQ_FIRST + 31) /* 31: I2C1 error interrupt */ -#define STM32WL5_IRQ_I2C2EV (STM32WL5_IRQ_FIRST + 32) /* 32: I2C2 event interrupt */ -#define STM32WL5_IRQ_I2C2ER (STM32WL5_IRQ_FIRST + 33) /* 33: I2C2 error interrupt */ -#define STM32WL5_IRQ_SPI1 (STM32WL5_IRQ_FIRST + 34) /* 34: SPI1 global interrupt */ -#define STM32WL5_IRQ_SPI2S2 (STM32WL5_IRQ_FIRST + 35) /* 35: SPI2S2 global interrupt */ -#define STM32WL5_IRQ_USART1 (STM32WL5_IRQ_FIRST + 36) /* 36: USART1 global interrupt */ -#define STM32WL5_IRQ_USART2 (STM32WL5_IRQ_FIRST + 37) /* 37: USART2 global interrupt */ -#define STM32WL5_IRQ_LPUART1 (STM32WL5_IRQ_FIRST + 38) /* 38: LPUART1 global interrupt */ -#define STM32WL5_IRQ_LPTIM1 (STM32WL5_IRQ_FIRST + 39) /* 39: LP timer 1 global interrupt */ -#define STM32WL5_IRQ_LPTIM2 (STM32WL5_IRQ_FIRST + 40) /* 40: LP timer 2 global interrupt */ -#define STM32WL5_IRQ_EXTI1510 (STM32WL5_IRQ_FIRST + 41) /* 41: EXTI line [15:10] interrupt through EXTI[15:10] (IMR1[31:26]) */ -#define STM32WL5_IRQ_RTCALRM (STM32WL5_IRQ_FIRST + 42) /* 42: RTC alarms A and B interrupt */ -#define STM32WL5_IRQ_LPTIM3 (STM32WL5_IRQ_FIRST + 43) /* 43: LP timer 3 global interrupt */ - /* 44: Reserved */ -#define STM32WL5_IRQ_IPCC_C1_RX_IT (STM32WL5_IRQ_FIRST + 45) /* 45: IPCC CPU1 RX occupied interrupt */ -#define STM32WL5_IRQ_IPCC_C1_TX_IT (STM32WL5_IRQ_FIRST + 46) /* 46: IPCC CPU1 TX free interrupt */ -#define STM32WL5_IRQ_HSEM (STM32WL5_IRQ_FIRST + 47) /* 47: Semaphore interrupt 0 to CPU1 */ -#define STM32WL5_IRQ_I2C3EV (STM32WL5_IRQ_FIRST + 48) /* 48: I2C3 event interrupt */ -#define STM32WL5_IRQ_I2C3ER (STM32WL5_IRQ_FIRST + 49) /* 49: I2C3 error interrupt */ -#define STM32WL5_IRQ_RADIO (STM32WL5_IRQ_FIRST + 50) /* 50: Radio */ -#define STM32WL5_IRQ_RFBUSY (STM32WL5_IRQ_FIRST + 50) /* 50: RFBUSY interrupt through EXTI[45] */ -#define STM32WL5_IRQ_AES (STM32WL5_IRQ_FIRST + 51) /* 51: AES global interrupt */ -#define STM32WL5_IRQ_RNG (STM32WL5_IRQ_FIRST + 52) /* 52: True random number generator interrupt */ -#define STM32WL5_IRQ_PKA (STM32WL5_IRQ_FIRST + 53) /* 53: Private key accelerator interrupt */ -#define STM32WL5_IRQ_DMA2CH1 (STM32WL5_IRQ_FIRST + 54) /* 54: DMA2 channel 1 non-secure interrupt */ -#define STM32WL5_IRQ_DMA2CH2 (STM32WL5_IRQ_FIRST + 55) /* 55: DMA2 channel 2 non-secure interrupt */ -#define STM32WL5_IRQ_DMA2CH3 (STM32WL5_IRQ_FIRST + 56) /* 56: DMA2 channel 3 non-secure interrupt */ -#define STM32WL5_IRQ_DMA2CH4 (STM32WL5_IRQ_FIRST + 57) /* 57: DMA2 channel 4 non-secure interrupt */ -#define STM32WL5_IRQ_DMA2CH5 (STM32WL5_IRQ_FIRST + 58) /* 58: DMA2 channel 5 non-secure interrupt */ -#define STM32WL5_IRQ_DMA2CH6 (STM32WL5_IRQ_FIRST + 59) /* 59: DMA2 channel 6 non-secure interrupt */ -#define STM32WL5_IRQ_DMA2CH7 (STM32WL5_IRQ_FIRST + 60) /* 60: DMA2 channel 7 non-secure interrupt */ -#define STM32WL5_IRQ_DMAMUX1_OVR (STM32WL5_IRQ_FIRST + 61) /* 61: DMAMUX1 overrun interrupt */ - -#define STM32WL5_IRQ_NEXTINTS 62 +#define STM32_IRQ_WWDG (STM32_IRQ_FIRST + 0) /* 0: Window watchdog early wakeup */ +#define STM32_IRQ_PVD (STM32_IRQ_FIRST + 1) /* 1: PVD through EXTI[16] */ +#define STM32_IRQ_PVM (STM32_IRQ_FIRST + 1) /* 1: PVM through EXTI[34] */ +#define STM32_IRQ_TAMPER (STM32_IRQ_FIRST + 2) /* 2: Tamper */ +#define STM32_IRQ_LSE_CSS (STM32_IRQ_FIRST + 2) /* 2: LSECSS */ +#define STM32_IRQ_RTC_STAMP (STM32_IRQ_FIRST + 2) /* 2: timestamp */ +#define STM32_IRQ_RTC_SSRU (STM32_IRQ_FIRST + 2) /* 2: RTC SSR underflow */ +#define STM32_IRQ_RTC_WKUP (STM32_IRQ_FIRST + 3) /* 3: RTC wakeup interrupt */ +#define STM32_IRQ_FLASH (STM32_IRQ_FIRST + 4) /* 4: Flash memory global interrupt and Flash memory ECC single error interrupt */ +#define STM32_IRQ_RCC (STM32_IRQ_FIRST + 5) /* 5: RCC global interrupt */ +#define STM32_IRQ_EXTI0 (STM32_IRQ_FIRST + 6) /* 6: EXTI line 0 interrupt through EXTI[0] */ +#define STM32_IRQ_EXTI1 (STM32_IRQ_FIRST + 7) /* 7: EXTI line 1 interrupt through EXTI[1] */ +#define STM32_IRQ_EXTI2 (STM32_IRQ_FIRST + 8) /* 8: EXTI line 2 interrupt through EXTI[2] */ +#define STM32_IRQ_EXTI3 (STM32_IRQ_FIRST + 9) /* 9: EXTI line 3 interrupt through EXTI[3] */ +#define STM32_IRQ_EXTI4 (STM32_IRQ_FIRST + 10) /* 10: EXTI line 4 interrupt through EXTI[4] */ +#define STM32_IRQ_DMA1CH1 (STM32_IRQ_FIRST + 11) /* 11: DMA1 channel 1 non-secure interrupt */ +#define STM32_IRQ_DMA1CH2 (STM32_IRQ_FIRST + 12) /* 12: DMA1 channel 2 non-secure interrupt */ +#define STM32_IRQ_DMA1CH3 (STM32_IRQ_FIRST + 13) /* 13: DMA1 channel 3 non-secure interrupt */ +#define STM32_IRQ_DMA1CH4 (STM32_IRQ_FIRST + 14) /* 14: DMA1 channel 4 non-secure interrupt */ +#define STM32_IRQ_DMA1CH5 (STM32_IRQ_FIRST + 15) /* 15: DMA1 channel 5 non-secure interrupt */ +#define STM32_IRQ_DMA1CH6 (STM32_IRQ_FIRST + 16) /* 16: DMA1 channel 6 non-secure interrupt */ +#define STM32_IRQ_DMA1CH7 (STM32_IRQ_FIRST + 17) /* 17: DMA1 channel 7 non-secure interrupt */ +#define STM32_IRQ_ADC (STM32_IRQ_FIRST + 18) /* 18: ADC global interrupt */ +#define STM32_IRQ_DAC (STM32_IRQ_FIRST + 19) /* 19: DAC global interrupt */ +#define STM32_IRQ_C2SEV (STM32_IRQ_FIRST + 20) /* 20: CPU2 SEV through EXTI[40] */ +#define STM32_IRQ_PWRC2H (STM32_IRQ_FIRST + 20) /* 20: PWR CPU2 HOLD wakeup */ +#define STM32_IRQ_COMP (STM32_IRQ_FIRST + 21) /* 21: COMP2 and COMP1 interrupt through EXTI[22:21] */ +#define STM32_IRQ_EXTI95 (STM32_IRQ_FIRST + 22) /* 22: EXTI line [9:5] interrupt through EXTI[9:5] */ +#define STM32_IRQ_TIM1BRK (STM32_IRQ_FIRST + 23) /* 23: Timer 1 break interrupt */ +#define STM32_IRQ_TIM1UP (STM32_IRQ_FIRST + 24) /* 24: Timer 1 Update */ +#define STM32_IRQ_TIM1TRG_COM (STM32_IRQ_FIRST + 25) /* 25: Timer 1 trigger and communication */ +#define STM32_IRQ_TIM1CC (STM32_IRQ_FIRST + 26) /* 26: Timer 1 capture compare interrupt */ +#define STM32_IRQ_TIM2 (STM32_IRQ_FIRST + 27) /* 27: Timer 2 global interrupt */ +#define STM32_IRQ_TIM16 (STM32_IRQ_FIRST + 28) /* 28: Timer 16 global interrupt */ +#define STM32_IRQ_TIM17 (STM32_IRQ_FIRST + 29) /* 29: Timer 17 global interrupt */ +#define STM32_IRQ_I2C1EV (STM32_IRQ_FIRST + 30) /* 30: I2C1 event interrupt */ +#define STM32_IRQ_I2C1ER (STM32_IRQ_FIRST + 31) /* 31: I2C1 error interrupt */ +#define STM32_IRQ_I2C2EV (STM32_IRQ_FIRST + 32) /* 32: I2C2 event interrupt */ +#define STM32_IRQ_I2C2ER (STM32_IRQ_FIRST + 33) /* 33: I2C2 error interrupt */ +#define STM32_IRQ_SPI1 (STM32_IRQ_FIRST + 34) /* 34: SPI1 global interrupt */ +#define STM32_IRQ_SPI2S2 (STM32_IRQ_FIRST + 35) /* 35: SPI2S2 global interrupt */ +#define STM32_IRQ_USART1 (STM32_IRQ_FIRST + 36) /* 36: USART1 global interrupt */ +#define STM32_IRQ_USART2 (STM32_IRQ_FIRST + 37) /* 37: USART2 global interrupt */ +#define STM32_IRQ_LPUART1 (STM32_IRQ_FIRST + 38) /* 38: LPUART1 global interrupt */ +#define STM32_IRQ_LPTIM1 (STM32_IRQ_FIRST + 39) /* 39: LP timer 1 global interrupt */ +#define STM32_IRQ_LPTIM2 (STM32_IRQ_FIRST + 40) /* 40: LP timer 2 global interrupt */ +#define STM32_IRQ_EXTI1510 (STM32_IRQ_FIRST + 41) /* 41: EXTI line [15:10] interrupt through EXTI[15:10] (IMR1[31:26]) */ +#define STM32_IRQ_RTCALRM (STM32_IRQ_FIRST + 42) /* 42: RTC alarms A and B interrupt */ +#define STM32_IRQ_LPTIM3 (STM32_IRQ_FIRST + 43) /* 43: LP timer 3 global interrupt */ + /* 44: Reserved */ +#define STM32_IRQ_IPCC_C1_RX_IT (STM32_IRQ_FIRST + 45) /* 45: IPCC CPU1 RX occupied interrupt */ +#define STM32_IRQ_IPCC_C1_TX_IT (STM32_IRQ_FIRST + 46) /* 46: IPCC CPU1 TX free interrupt */ +#define STM32_IRQ_HSEM (STM32_IRQ_FIRST + 47) /* 47: Semaphore interrupt 0 to CPU1 */ +#define STM32_IRQ_I2C3EV (STM32_IRQ_FIRST + 48) /* 48: I2C3 event interrupt */ +#define STM32_IRQ_I2C3ER (STM32_IRQ_FIRST + 49) /* 49: I2C3 error interrupt */ +#define STM32_IRQ_RADIO (STM32_IRQ_FIRST + 50) /* 50: Radio */ +#define STM32_IRQ_RFBUSY (STM32_IRQ_FIRST + 50) /* 50: RFBUSY interrupt through EXTI[45] */ +#define STM32_IRQ_AES (STM32_IRQ_FIRST + 51) /* 51: AES global interrupt */ +#define STM32_IRQ_RNG (STM32_IRQ_FIRST + 52) /* 52: True random number generator interrupt */ +#define STM32_IRQ_PKA (STM32_IRQ_FIRST + 53) /* 53: Private key accelerator interrupt */ +#define STM32_IRQ_DMA2CH1 (STM32_IRQ_FIRST + 54) /* 54: DMA2 channel 1 non-secure interrupt */ +#define STM32_IRQ_DMA2CH2 (STM32_IRQ_FIRST + 55) /* 55: DMA2 channel 2 non-secure interrupt */ +#define STM32_IRQ_DMA2CH3 (STM32_IRQ_FIRST + 56) /* 56: DMA2 channel 3 non-secure interrupt */ +#define STM32_IRQ_DMA2CH4 (STM32_IRQ_FIRST + 57) /* 57: DMA2 channel 4 non-secure interrupt */ +#define STM32_IRQ_DMA2CH5 (STM32_IRQ_FIRST + 58) /* 58: DMA2 channel 5 non-secure interrupt */ +#define STM32_IRQ_DMA2CH6 (STM32_IRQ_FIRST + 59) /* 59: DMA2 channel 6 non-secure interrupt */ +#define STM32_IRQ_DMA2CH7 (STM32_IRQ_FIRST + 60) /* 60: DMA2 channel 7 non-secure interrupt */ +#define STM32_IRQ_DMAMUX1_OVR (STM32_IRQ_FIRST + 61) /* 61: DMAMUX1 overrun interrupt */ + +#define STM32_IRQ_NEXTINTS 62 /* (EXTI interrupts do not use IRQ numbers) */ -#define NR_IRQS (STM32WL5_IRQ_FIRST + STM32WL5_IRQ_NEXTINTS) +#define NR_IRQS (STM32_IRQ_FIRST + STM32_IRQ_NEXTINTS) /**************************************************************************** * Public Types diff --git a/arch/arm/src/common/stm32/CMakeLists.txt b/arch/arm/src/common/stm32/CMakeLists.txt new file mode 100644 index 0000000000000..427254933245d --- /dev/null +++ b/arch/arm/src/common/stm32/CMakeLists.txt @@ -0,0 +1,493 @@ +# ############################################################################## +# arch/arm/src/common/stm32/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +target_include_directories(arch BEFORE PUBLIC ${CMAKE_CURRENT_LIST_DIR}) + +if(CONFIG_BUILD_PROTECTED) + target_include_directories(arch_interface BEFORE + PUBLIC ${CMAKE_CURRENT_LIST_DIR}) +endif() + +set(SRCS) + +# Architecture-neutral sources used by every STM32 family + +list(APPEND SRCS stm32_waste.c) +list(APPEND SRCS stm32_uid.c) + +if(CONFIG_STM32_COMMON_LEGACY) + list( + APPEND + SRCS + stm32_allocateheap_m3m4_v1.c + stm32_start_m3m4_v1.c + stm32_lse_m3m4_v1.c + stm32_lsi_m3m4_v1.c + stm32_irq_m3m4_v1.c + stm32_capture_m3m4_v1.c) + + if(CONFIG_STM32_HAVE_IP_GPIO_M3M4_V1) + list(APPEND SRCS stm32_gpio_m3m4_v1v2.c) + endif() + + if(CONFIG_STM32_HAVE_IP_EXTI_V1 OR CONFIG_STM32_HAVE_IP_EXTI_V2) + list(APPEND SRCS stm32_exti_gpio_m3m4_v1v2.c) + endif() + + if(CONFIG_STM32_HAVE_IP_SPI_V1 + OR CONFIG_STM32_HAVE_IP_SPI_V2 + OR CONFIG_STM32_HAVE_IP_SPI_V3 + OR CONFIG_STM32_HAVE_IP_SPI_V4) + list(APPEND SRCS stm32_spi_m3m4_v2v3v4.c) + endif() + + if(CONFIG_STM32_HAVE_IP_I2S_M3M4_V1) + list(APPEND SRCS stm32_i2s_m3m4_v1.c) + endif() + + if(CONFIG_STM32_HAVE_IP_SDIO_M3M4_V1) + list(APPEND SRCS stm32_sdio_m3m4_v1.c) + endif() + + if(CONFIG_STM32_HAVE_IP_TIMERS) + list(APPEND SRCS stm32_tim_m3m4_v1v2v3.c) + endif() + + if(CONFIG_STM32_HAVE_IP_CCM_M3M4_V1) + list(APPEND SRCS stm32_ccm_m3m4_v1.c) + endif() + + if(CONFIG_STM32_HAVE_IP_DFUMODE_M3M4_V1) + list(APPEND SRCS stm32_dfumode_m3m4_v1.c) + endif() + + if(CONFIG_STM32_HAVE_IP_USART_V1 + OR CONFIG_STM32_HAVE_IP_USART_V2 + OR CONFIG_STM32_HAVE_IP_USART_V3 + OR CONFIG_STM32_HAVE_IP_USART_V4) + list(APPEND SRCS stm32_lowputc_usart_m3m4_v1v2v3v4.c) + endif() + + if(CONFIG_STM32_HAVE_IP_FLASH_M3M4_L1) + list(APPEND SRCS stm32_flash_m3m4_l1.c) + elseif(CONFIG_STM32_HAVE_IP_FLASH_M3M4_F1F3) + list(APPEND SRCS stm32_flash_m3m4_f1f3.c) + elseif(CONFIG_STM32_HAVE_IP_FLASH_M3M4_F2F4) + list(APPEND SRCS stm32_flash_m3m4_f2f4.c) + elseif(CONFIG_STM32_HAVE_IP_FLASH_M3M4_G4) + list(APPEND SRCS stm32_flash_m3m4_g4.c) + endif() + + if(CONFIG_STM32_TICKLESS_TIMER) + list(APPEND SRCS stm32_tickless_m3m4_v1.c) + elseif(CONFIG_ARCH_ARMV6M) + list(APPEND SRCS stm32_timerisr_armv6m.c) + else() + list(APPEND SRCS stm32_timerisr_armv7m.c) + endif() + + if(CONFIG_BUILD_PROTECTED) + list(APPEND SRCS stm32_userspace_m3m4_v1.c stm32_mpuinit_m3m4_v1.c) + endif() + + if(NOT CONFIG_ARCH_IDLE_CUSTOM) + list(APPEND SRCS stm32_idle_m3m4_v1.c) + endif() + + list(APPEND SRCS stm32_pmstop_m3m4_v1.c stm32_pmstandby_m3m4_v1.c + stm32_pmsleep_m3m4_v1.c) + + if(NOT CONFIG_ARCH_CUSTOM_PMINIT) + list(APPEND SRCS stm32_pminitialize_m3m4_v1.c) + endif() + + if(CONFIG_STM32_USART) + if(CONFIG_STM32_HAVE_IP_USART_V1 + OR CONFIG_STM32_HAVE_IP_USART_V2 + OR CONFIG_STM32_HAVE_IP_USART_V3 + OR CONFIG_STM32_HAVE_IP_USART_V4) + list(APPEND SRCS stm32_serial_m3m4_v1v2v3v4.c) + endif() + endif() + + if(CONFIG_STM32_DMA) + if(CONFIG_STM32_HAVE_IP_DMA_V1_7CH_DMAMUX) + list(APPEND SRCS stm32_dma_m0_v1_7ch_dmamux.c) + elseif(CONFIG_STM32_HAVE_IP_DMA_V1_7CH) + list(APPEND SRCS stm32_dma_m0_v1_7ch.c) + elseif(CONFIG_STM32_HAVE_IP_DMA_V1_8CH_DMAMUX) + list(APPEND SRCS stm32_dma_m3m4_v1_8ch_dmamux.c) + elseif(CONFIG_STM32_HAVE_IP_DMA_V1_8CH) + list(APPEND SRCS stm32_dma_m3m4_v1_8ch.c) + elseif(CONFIG_STM32_HAVE_IP_DMA_V2_STREAM) + list(APPEND SRCS stm32_dma_m3m4_v2_stream.c) + endif() + endif() + + if(CONFIG_TIMER AND CONFIG_STM32_HAVE_IP_TIMERS) + list(APPEND SRCS stm32_tim_m3m4_v1v2v3_lowerhalf.c) + endif() + + if(CONFIG_STM32_ONESHOT) + list(APPEND SRCS stm32_oneshot_m3m4_v1.c stm32_oneshot_m3m4_v1_lowerhalf.c) + endif() + + if(CONFIG_STM32_FREERUN) + list(APPEND SRCS stm32_freerun_m3m4_v1.c) + endif() + + if(CONFIG_STM32_HAVE_IP_I2C_M3M4_V1) + if(CONFIG_STM32_I2C_ALT) + list(APPEND SRCS stm32_i2c_m3m4_v1_alt.c) + elseif(CONFIG_STM32_STM32F4XXX) + list(APPEND SRCS stm32_i2c_m3m4_v1_f40xxx.c) + else() + list(APPEND SRCS stm32_i2c_m3m4_v1.c) + endif() + elseif(CONFIG_STM32_HAVE_IP_I2C_M3M4_V2) + list(APPEND SRCS stm32_i2c_m3m4_v2.c) + if(CONFIG_STM32_I2C_SLAVE) + list(APPEND SRCS stm32_i2c_m3m4_v2_slave.c) + endif() + endif() + + if(CONFIG_USBDEV) + if(CONFIG_STM32_USB AND CONFIG_STM32_HAVE_IP_USBDEV_M3M4_V1) + list(APPEND SRCS stm32_usbdev_m3m4_v1.c) + endif() + if(CONFIG_STM32_USBFS AND CONFIG_STM32_HAVE_IP_USBFS_M3M4_V1) + list(APPEND SRCS stm32_usbfs_m3m4_v1.c) + endif() + if(CONFIG_STM32_OTGFS AND CONFIG_STM32_HAVE_IP_OTGFS_M3M4_V1) + list(APPEND SRCS stm32_otgfsdev_m3m4_v1.c) + endif() + if(CONFIG_STM32_OTGHS AND CONFIG_STM32_HAVE_IP_OTGHS_M3M4_V1) + list(APPEND SRCS stm32_otghsdev_m3m4_v1.c) + endif() + endif() + + if(CONFIG_STM32_USBHOST) + if(CONFIG_STM32_OTGFS AND CONFIG_STM32_HAVE_IP_OTGFS_M3M4_V1) + list(APPEND SRCS stm32_otgfshost_m3m4_v1.c) + endif() + if(CONFIG_STM32_OTGHS AND CONFIG_STM32_HAVE_IP_OTGHS_M3M4_V1) + list(APPEND SRCS stm32_otghshost_m3m4_v1.c) + endif() + if(CONFIG_STM32_HAVE_COMMON_USBHOST_DEBUG AND (CONFIG_USBHOST_TRACE + OR CONFIG_DEBUG_USB)) + list(APPEND SRCS stm32_usbhost_m3m4_v1.c) + endif() + endif() + + if(CONFIG_STM32_ETHMAC AND CONFIG_STM32_HAVE_IP_ETHMAC_M3M4_V1) + list(APPEND SRCS stm32_eth_m3m4_v1.c) + endif() + + if(CONFIG_STM32_PWR AND CONFIG_STM32_HAVE_IP_PWR_M3M4_V1) + list(APPEND SRCS stm32_pwr_m3m4_v1.c stm32_exti_pwr_m3m4_v1.c) + endif() + + if(CONFIG_STM32_RTC) + if(CONFIG_STM32_HAVE_IP_RTC_COUNTER_M3M4_V1) + list(APPEND SRCS stm32_rtcounter_m3m4_v1.c) + elseif(CONFIG_STM32_HAVE_IP_RTCC_M3M4_L1) + list(APPEND SRCS stm32_rtcc_m3m4_l1.c) + elseif(CONFIG_STM32_HAVE_IP_RTCC_M3M4_F4) + list(APPEND SRCS stm32_rtcc_m3m4_f4.c) + elseif(CONFIG_STM32_HAVE_IP_RTCC_M3M4_V1) + list(APPEND SRCS stm32_rtcc_m3m4_v1.c) + endif() + if(CONFIG_RTC_ALARM) + list(APPEND SRCS stm32_exti_alarm_m3m4_v1.c) + endif() + if(CONFIG_RTC_PERIODIC) + list(APPEND SRCS stm32_exti_wakeup_m3m4_v1.c) + endif() + if(CONFIG_RTC_DRIVER AND CONFIG_STM32_HAVE_IP_RTC_M3M4_V1) + list(APPEND SRCS stm32_rtc_m3m4_v1_lowerhalf.c) + endif() + endif() + + if(CONFIG_STM32_ADC AND (CONFIG_STM32_HAVE_IP_ADC_M3M4_V1 + OR CONFIG_STM32_HAVE_IP_ADC_M3M4_V2)) + list(APPEND SRCS stm32_adc_m3m4_v1v2.c) + endif() + + if(CONFIG_STM32_SDADC AND CONFIG_STM32_HAVE_IP_SDADC_M3M4_V1) + list(APPEND SRCS stm32_sdadc_m3m4_v1.c) + endif() + + if(CONFIG_STM32_DAC AND (CONFIG_STM32_HAVE_IP_DAC_M3M4_V1 + OR CONFIG_STM32_HAVE_IP_DAC_M3M4_V2)) + list(APPEND SRCS stm32_dac_m3m4_v1.c) + endif() + + if(CONFIG_STM32_COMP) + if(CONFIG_STM32_HAVE_IP_COMP_M3M4_V1) + list(APPEND SRCS stm32_comp_m3m4_v1.c) + elseif(CONFIG_STM32_HAVE_IP_COMP_M3M4_V2) + list(APPEND SRCS stm32_comp_m3m4_v2.c) + endif() + endif() + + if(CONFIG_STM32_OPAMP AND CONFIG_STM32_HAVE_IP_OPAMP_M3M4_V1) + list(APPEND SRCS stm32_opamp_m3m4_v1.c) + endif() + + if(CONFIG_STM32_HRTIM AND CONFIG_STM32_HAVE_IP_HRTIM_M3M4_V1) + list(APPEND SRCS stm32_hrtim_m3m4_v1.c) + endif() + + if(CONFIG_STM32_1WIREDRIVER) + list(APPEND SRCS stm32_1wire_m3m4_v1.c) + endif() + + if(CONFIG_STM32_HCIUART) + list(APPEND SRCS stm32_hciuart_m3m4_v1.c) + endif() + + if(CONFIG_STM32_RNG AND CONFIG_STM32_HAVE_IP_RNG_M3M4_V1) + list(APPEND SRCS stm32_rng_m3m4_v1.c) + endif() + + if(CONFIG_STM32_LTDC AND CONFIG_STM32_HAVE_IP_LTDC_M3M4_V1) + list(APPEND SRCS stm32_ltdc_m3m4_v1.c) + endif() + + if(CONFIG_STM32_DMA2D AND CONFIG_STM32_HAVE_IP_DMA2D_M3M4_V1) + list(APPEND SRCS stm32_dma2d_m3m4_v1.c) + endif() + + if(CONFIG_STM32_PWM) + list(APPEND SRCS stm32_pwm_m3m4_v1v2v3.c) + endif() + + if(CONFIG_STM32_PULSECOUNT) + list(APPEND SRCS stm32_pulsecount_m3m4_v1v2v3.c) + endif() + + if(CONFIG_STM32_CAP) + list(APPEND SRCS stm32_capture_m3m4_v1_lowerhalf.c) + endif() + + if(CONFIG_SENSORS_QENCODER AND CONFIG_STM32_QE) + list(APPEND SRCS stm32_qencoder_m3m4_v1v2v3.c) + endif() + + if(CONFIG_STM32_CAN AND CONFIG_STM32_HAVE_IP_CAN_BXCAN_M3M4_V1) + if(CONFIG_STM32_CAN_CHARDRIVER) + list(APPEND SRCS stm32_can_m3m4_v1.c) + endif() + if(CONFIG_STM32_CAN_SOCKET) + list(APPEND SRCS stm32_can_m3m4_v1_sock.c) + endif() + endif() + + if(CONFIG_STM32_FDCAN AND CONFIG_STM32_HAVE_IP_FDCAN_MCAN_M3M4_V1) + if(CONFIG_STM32_FDCAN_CHARDRIVER) + list(APPEND SRCS stm32_fdcan_m3m4_v1.c) + endif() + if(CONFIG_STM32_FDCAN_SOCKET) + list(APPEND SRCS stm32_fdcan_m3m4_v1_sock.c) + endif() + endif() + + if(CONFIG_STM32_IWDG AND CONFIG_STM32_HAVE_IP_WDG_M3M4_V1) + list(APPEND SRCS stm32_iwdg_m3m4_v1.c) + endif() + + if(CONFIG_STM32_WWDG AND CONFIG_STM32_HAVE_IP_WDG_M3M4_V1) + list(APPEND SRCS stm32_wwdg_m3m4_v1.c) + endif() + + if(CONFIG_DEBUG_FEATURES + AND (CONFIG_STM32_HAVE_IP_DBGMCU_M3M4_V1 + OR CONFIG_STM32_HAVE_IP_DBGMCU_M3M4_V2 + OR CONFIG_STM32_HAVE_IP_DBGMCU_M3M4_V3)) + list(APPEND SRCS stm32_dumpgpio_m3m4_v1.c) + endif() + + if(CONFIG_STM32_AES AND CONFIG_STM32_HAVE_IP_AES_M3M4_V1) + list(APPEND SRCS stm32_aes_m3m4_v1.c) + endif() + + if(CONFIG_CRYPTO_CRYPTODEV_HARDWARE AND CONFIG_STM32_HAVE_IP_CRYPTO_M3M4_V1) + list(APPEND SRCS stm32_crypto_m3m4_v1.c) + endif() + + if(CONFIG_STM32_BBSRAM AND CONFIG_STM32_HAVE_IP_BBSRAM_M3M4_V1) + list(APPEND SRCS stm32_bbsram_m3m4_v1.c) + endif() + + if(CONFIG_STM32_FMC AND CONFIG_STM32_HAVE_IP_FMC_M3M4_V1) + list(APPEND SRCS stm32_fmc_m3m4_v1.c) + endif() + + if(CONFIG_STM32_FSMC AND CONFIG_STM32_HAVE_IP_FSMC_M3M4_V1) + list(APPEND SRCS stm32_fsmc_m3m4_v1.c) + endif() + + if(CONFIG_STM32_FOC) + list(APPEND SRCS stm32_foc_m3m4_v1.c) + endif() + + if(CONFIG_STM32_CORDIC AND CONFIG_STM32_HAVE_IP_CORDIC_M3M4_V1) + list(APPEND SRCS stm32_cordic_m3m4_v1.c) + endif() +endif() + +if(CONFIG_ARCH_CORTEXM0) + list(APPEND SRCS stm32_irq_m0_v1.c stm32_start_m0_v1.c stm32_lsi_m0_v1.c) + + if(CONFIG_STM32_HAVE_IP_GPIO_M0_V1) + list(APPEND SRCS stm32_gpio_m0_v1.c) + endif() + + if(CONFIG_STM32_HAVE_IP_EXTI_V1 OR CONFIG_STM32_HAVE_IP_EXTI_V2) + list(APPEND SRCS stm32_exti_gpio_m0_v1.c) + endif() + + if(CONFIG_STM32_HAVE_IP_USART_V3) + list(APPEND SRCS stm32_lowputc_usart_m0_v3.c stm32_serial_m0_v3.c) + elseif(CONFIG_STM32_HAVE_IP_USART_V4) + list(APPEND SRCS stm32_lowputc_usart_m0_v4.c stm32_serial_m0_v4.c) + endif() + + if(CONFIG_STM32_RTC_LSECLOCK OR CONFIG_LCD_LSECLOCK) + list(APPEND SRCS stm32_lse_m0_v1.c) + endif() + + if(NOT CONFIG_ARCH_IDLE_CUSTOM) + list(APPEND SRCS stm32_idle_m0_v1.c) + endif() + + if(NOT CONFIG_SCHED_TICKLESS) + if(CONFIG_ARCH_ARMV6M) + list(APPEND SRCS stm32_timerisr_armv6m.c) + else() + list(APPEND SRCS stm32_timerisr_armv7m.c) + endif() + endif() + + if(CONFIG_STM32_PWR) + if(CONFIG_STM32_HAVE_IP_PWR_M0_V1) + list(APPEND SRCS stm32_pwr_m0_v1.c) + elseif(CONFIG_STM32_HAVE_IP_PWR_G0) + list(APPEND SRCS stm32_pwr_m0_g0.c) + endif() + endif() + + if(CONFIG_STM32_DMA) + if(CONFIG_STM32_HAVE_IP_DMA_V1_7CH_DMAMUX) + list(APPEND SRCS stm32_dma_m0_v1_7ch_dmamux.c) + elseif(CONFIG_STM32_HAVE_IP_DMA_V1_7CH) + list(APPEND SRCS stm32_dma_m0_v1_7ch.c) + elseif(CONFIG_STM32_HAVE_IP_DMA_V1_8CH_DMAMUX) + list(APPEND SRCS stm32_dma_m3m4_v1_8ch_dmamux.c) + elseif(CONFIG_STM32_HAVE_IP_DMA_V1_8CH) + list(APPEND SRCS stm32_dma_m3m4_v1_8ch.c) + elseif(CONFIG_STM32_HAVE_IP_DMA_V2_STREAM) + list(APPEND SRCS stm32_dma_m3m4_v2_stream.c) + endif() + endif() + + if(CONFIG_STM32_PROGMEM) + if(CONFIG_STM32_HAVE_IP_FLASH_M0_G0C0) + list(APPEND SRCS stm32_flash_m0_g0c0.c) + elseif(CONFIG_STM32_HAVE_IP_FLASH_M3M4_L1) + list(APPEND SRCS stm32_flash_m3m4_l1.c) + elseif(CONFIG_STM32_HAVE_IP_FLASH_M3M4_F1F3) + list(APPEND SRCS stm32_flash_m3m4_f1f3.c) + elseif(CONFIG_STM32_HAVE_IP_FLASH_M3M4_F2F4) + list(APPEND SRCS stm32_flash_m3m4_f2f4.c) + elseif(CONFIG_STM32_HAVE_IP_FLASH_M3M4_G4) + list(APPEND SRCS stm32_flash_m3m4_g4.c) + endif() + endif() + + if(CONFIG_STM32_HAVE_HSI48) + list(APPEND SRCS stm32_hsi48_m0_v1.c) + endif() + + if(CONFIG_STM32_USB AND CONFIG_STM32_HAVE_IP_USBDEV_M0_V1) + list(APPEND SRCS stm32_usbdev_m0_v1.c) + endif() + + if(CONFIG_STM32_I2C) + list(APPEND SRCS stm32_i2c_m0_v1.c) + endif() + + if(CONFIG_STM32_SPI) + list(APPEND SRCS stm32_spi_m0_v1.c) + endif() + + if(CONFIG_STM32_PWM) + list(APPEND SRCS stm32_pwm_m0_v1.c) + endif() + + if(CONFIG_PULSECOUNT AND CONFIG_STM32_TIM1_PULSECOUNT) + list(APPEND SRCS stm32_pulsecount_m0_v1.c) + endif() + + if(CONFIG_STM32_ADC AND CONFIG_STM32_HAVE_IP_ADC_M0_V1) + list(APPEND SRCS stm32_adc_m0_v1.c) + endif() + + if(CONFIG_STM32_AES AND CONFIG_STM32_HAVE_IP_AES_M0_V1) + list(APPEND SRCS stm32_aes_m0_v1.c) + endif() + + if(CONFIG_STM32_RNG AND CONFIG_STM32_HAVE_IP_RNG_M0_V1) + list(APPEND SRCS stm32_rng_m0_v1.c) + endif() + + if(CONFIG_STM32_TIM AND CONFIG_STM32_HAVE_IP_TIMERS_M0_V1) + list(APPEND SRCS stm32_tim_m0_v1.c stm32_tim_m0_v1_lowerhalf.c) + endif() + + if(CONFIG_STM32_IWDG AND CONFIG_STM32_HAVE_IP_WDG_M0_V1) + list(APPEND SRCS stm32_iwdg_m0_v1.c) + endif() + + if(CONFIG_STM32_WWDG AND CONFIG_STM32_HAVE_IP_WDG_M0_V1) + list(APPEND SRCS stm32_wwdg_m0_v1.c) + endif() + + if(CONFIG_STM32_FDCAN AND CONFIG_STM32_HAVE_IP_FDCAN_MCAN_M0_V1) + if(CONFIG_STM32_FDCAN_CHARDRIVER) + list(APPEND SRCS stm32_fdcan_m0_v1.c) + endif() + if(CONFIG_STM32_FDCAN_SOCKET) + list(APPEND SRCS stm32_fdcan_m0_v1_sock.c) + endif() + endif() + + if(CONFIG_SENSORS_QENCODER) + list(APPEND SRCS stm32_qencoder_m0_v1.c) + endif() +endif() + +if(CONFIG_SENSORS_HALL3PHASE) + list(APPEND SRCS stm32_hall3ph.c) +endif() + +target_sources(arch PRIVATE ${SRCS}) diff --git a/arch/arm/src/common/stm32/Kconfig b/arch/arm/src/common/stm32/Kconfig new file mode 100644 index 0000000000000..1b0211bdd166d --- /dev/null +++ b/arch/arm/src/common/stm32/Kconfig @@ -0,0 +1,217 @@ +# +# Common STM32 Kconfig options shared by STM32 families. +# + +menu "STM32 Configuration Options" + depends on ARCH_CHIP_STM32 + +config STM32_COMMON_LEGACY + bool + default y if ARCH_CHIP_STM32F1 + default y if ARCH_CHIP_STM32F2 + default y if ARCH_CHIP_STM32F3 + default y if ARCH_CHIP_STM32F4 + default y if ARCH_CHIP_STM32G4 + default y if ARCH_CHIP_STM32L1 + +config STM32_COMMON_F0_L0_G0_C0 + bool + default y if ARCH_CHIP_STM32F0 + default y if ARCH_CHIP_STM32L0 + default y if ARCH_CHIP_STM32G0 + default y if ARCH_CHIP_STM32C0 + +config STM32_COMMON_F7_H7 + bool + default y if ARCH_CHIP_STM32F7 + default y if ARCH_CHIP_STM32H7 + +config STM32_COMMON_H7_H5 + bool + default y if ARCH_CHIP_STM32H7 + default y if ARCH_CHIP_STM32H5 + +config STM32_COMMON_F7_H7_H5 + bool + default y if STM32_COMMON_F7_H7 + default y if ARCH_CHIP_STM32H5 + +config STM32_COMMON_L4_L5_U5 + bool + default y if ARCH_CHIP_STM32L4 + default y if ARCH_CHIP_STM32L5 + default y if ARCH_CHIP_STM32U5 + +config STM32_COMMON_L5_U5 + bool + default y if ARCH_CHIP_STM32L5 + default y if ARCH_CHIP_STM32U5 + +config STM32_COMMON_L4_H5_L5_U5 + bool + default y if STM32_COMMON_L4_L5_U5 + default y if ARCH_CHIP_STM32H5 + +config STM32_COMMON_FULL_FEATURED + bool + default y if STM32_COMMON_LEGACY + default y if STM32_COMMON_F0_L0_G0_C0 + default y if STM32_COMMON_F7_H7_H5 + default y if STM32_COMMON_L4_L5_U5 + +config STM32_COMMON_SRAM2_OPTIONS + bool + default y if ARCH_CHIP_STM32L4 + default y if ARCH_CHIP_STM32H5 + default y if ARCH_CHIP_STM32L5 + default y if ARCH_CHIP_STM32U5 && STM32_SRAM2 + +config STM32_COMMON_USART_UNCONFIG_ON_CLOSE + bool + default y if ARCH_CHIP_STM32H5 + default y if ARCH_CHIP_STM32N6 + +source "arch/arm/src/common/stm32/Kconfig.have" + +source "arch/arm/src/common/stm32/Kconfig.periph" + +menu "ADC Configuration" + depends on STM32_ADC +source "arch/arm/src/common/stm32/Kconfig.adc" +endmenu # ADC Configuration + +menu "SDADC Configuration" + depends on STM32_SDADC +source "arch/arm/src/common/stm32/Kconfig.sdadc" +endmenu # SDADC Configuration + +menu "Cache Configuration" +source "arch/arm/src/common/stm32/Kconfig.cache" +endmenu # Cache Configuration + +menu "CAN Configuration" + depends on STM32_CAN +source "arch/arm/src/common/stm32/Kconfig.can" +endmenu # CAN Configuration + +menu "FDCAN Configuration" + depends on STM32_FDCAN +source "arch/arm/src/common/stm32/Kconfig.fdcan" +endmenu # FDCAN Configuration + +menu "DAC Configuration" + depends on STM32_DAC +source "arch/arm/src/common/stm32/Kconfig.dac" +endmenu # DAC Configuration + +menu "DFSDM Configuration" + depends on STM32_DFSDM1 || STM32_MDF1 || STM32_ADF1 +source "arch/arm/src/common/stm32/Kconfig.dfsdm" +endmenu # DFSDM Configuration + +menu "DMA Configuration" + depends on STM32_DMA || STM32_DMA2D +source "arch/arm/src/common/stm32/Kconfig.dma" +endmenu # DMA Configuration + +menu "Ethernet Configuration" + depends on STM32_ETHMAC +source "arch/arm/src/common/stm32/Kconfig.eth" +endmenu # Ethernet Configuration + +menu "Flash Configuration" +source "arch/arm/src/common/stm32/Kconfig.flash" +endmenu # Flash Configuration + +menu "FOC Configuration" + depends on STM32_HAVE_COMMON_FOC +source "arch/arm/src/common/stm32/Kconfig.foc" +endmenu # FOC Configuration + +menu "GPIO Configuration" +source "arch/arm/src/common/stm32/Kconfig.gpio" +endmenu # GPIO Configuration + +menu "I2C Configuration" + depends on STM32_I2C +source "arch/arm/src/common/stm32/Kconfig.i2c" +endmenu # I2C Configuration + +menu "IPCC Configuration" + depends on STM32_IPCC || STM32_HAVE_HSEM +source "arch/arm/src/common/stm32/Kconfig.ipcc" +endmenu # IPCC Configuration + +menu "BLE Configuration" + depends on STM32_BLE || STM32_MBOX +source "arch/arm/src/common/stm32/Kconfig.ble" +endmenu # BLE Configuration + +menu "LTDC Configuration" + depends on STM32_LTDC +source "arch/arm/src/common/stm32/Kconfig.ltdc" +endmenu # LTDC Configuration + +menu "Memory Configuration" +source "arch/arm/src/common/stm32/Kconfig.memory" +endmenu # Memory Configuration + +menu "QSPI/OCTOSPI Configuration" + depends on STM32_QSPI || STM32_QSPI1 || STM32_OCTOSPI1 || STM32_OCTOSPI2 +source "arch/arm/src/common/stm32/Kconfig.qspi" +endmenu # QSPI/OCTOSPI Configuration + +menu "RTC Configuration" + depends on STM32_RTC +source "arch/arm/src/common/stm32/Kconfig.rtc" +endmenu # RTC Configuration + +menu "SAI Configuration" +source "arch/arm/src/common/stm32/Kconfig.sai" +endmenu # SAI Configuration + +menu "SDIO/SDMMC Configuration" + depends on STM32_SDIO || STM32_SDMMC +source "arch/arm/src/common/stm32/Kconfig.sdio" +endmenu # SDIO/SDMMC Configuration + +menu "COMP Configuration" + depends on STM32_COMP +source "arch/arm/src/common/stm32/Kconfig.comp" +endmenu # COMP Configuration + +menu "DTS Configuration" + depends on STM32_DTS +source "arch/arm/src/common/stm32/Kconfig.dts" +endmenu # DTS Configuration + +menu "U[S]ART Configuration" + depends on STM32_USART +source "arch/arm/src/common/stm32/Kconfig.uart" +endmenu # U[S]ART Configuration + +menu "SPI/I2S Configuration" + depends on STM32_SPI || STM32_I2S +source "arch/arm/src/common/stm32/Kconfig.spi" +endmenu # SPI/I2S Configuration + +menu "System Configuration" +source "arch/arm/src/common/stm32/Kconfig.system" +endmenu # System Configuration + +menu "Timer Configuration" + depends on STM32_TIM || STM32_LPTIM +source "arch/arm/src/common/stm32/Kconfig.tim" +endmenu # Timer Configuration + +menu "HRTIM Configuration" + depends on STM32_HRTIM +source "arch/arm/src/common/stm32/Kconfig.hrtim" +endmenu # HRTIM Configuration + +menu "USB Configuration" + depends on STM32_USB || STM32_USBFS || STM32_OTGFS || STM32_OTGHS || STM32_OTGFSHS +source "arch/arm/src/common/stm32/Kconfig.usb" +endmenu # USB Configuration + +endmenu # Common STM32 Configuration Options diff --git a/arch/arm/src/common/stm32/Kconfig.adc b/arch/arm/src/common/stm32/Kconfig.adc new file mode 100644 index 0000000000000..afd9427f034f7 --- /dev/null +++ b/arch/arm/src/common/stm32/Kconfig.adc @@ -0,0 +1,990 @@ +# +# STM32 common ADC options. +# + +# STM32 ADC configuration options. + +# TODO: The options below are a special case for the legacy family-local +# stm32l4_adc.c driver (selected by STM32_HAVE_ADC_L4). They must be migrated +# to the common ADC interface used by stm32_adc_m3m4_v1v2.c (STM32_ADCx_EXTSEL / +# STM32_ADCx_JEXTSEL / STM32_ADCx_INJECTED_CHAN) and removed from here. + +# ADC per-instance capability flags +# (hidden; driven by default y if / peripheral selects, never by chip selectors) + +config STM32_ADC1_HAVE_TIMER_FREQ + bool + default y if (STM32_HAVE_IP_ADC_M3M4_V1 || STM32_HAVE_IP_ADC_M3M4_V2) && STM32_TIM && STM32_ADC1_HAVE_TIMER + default y if (STM32_HAVE_IP_ADC_M0_V1 || STM32_COMMON_F7_H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_ADC1_HAVE_TIMER + +config STM32_ADC1_HAVE_TIMTRIG + bool + default y if (STM32_HAVE_IP_ADC_M3M4_V1 || STM32_HAVE_IP_ADC_M3M4_V2) && STM32_TIM && STM32_ADC1_HAVE_TIMER + default y if (STM32_HAVE_IP_ADC_M0_V1 || STM32_COMMON_F7_H7) && STM32_ADC1_HAVE_TIMER + default y if (ARCH_CHIP_STM32H5 || STM32_COMMON_L5_U5) && STM32_ADC1_HAVE_TIMER + +config STM32_ADC2_HAVE_TIMER_FREQ + bool + default y if (STM32_HAVE_IP_ADC_M3M4_V1 || STM32_HAVE_IP_ADC_M3M4_V2) && STM32_TIM && STM32_ADC2_HAVE_TIMER + default y if (STM32_COMMON_F7_H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_ADC2_HAVE_TIMER + +config STM32_ADC2_HAVE_TIMTRIG + bool + default y if (STM32_HAVE_IP_ADC_M3M4_V1 || STM32_HAVE_IP_ADC_M3M4_V2) && STM32_TIM && STM32_ADC2_HAVE_TIMER + default y if (STM32_COMMON_F7_H7_H5) && STM32_ADC2_HAVE_TIMER + default y if STM32_COMMON_L5_U5 && STM32_ADC2_HAVE_TIMER + +config STM32_ADC3_HAVE_TIMTRIG + bool + default y if (STM32_HAVE_IP_ADC_M3M4_V1 || STM32_HAVE_IP_ADC_M3M4_V2) && STM32_TIM && STM32_ADC3_HAVE_TIMER + default y if (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4) && STM32_ADC3_HAVE_TIMER + default y if STM32_COMMON_L5_U5 && STM32_ADC3_HAVE_TIMER + +config STM32_ADC1_HAVE_DMA + bool + default y if STM32_STM32C0 + default y if STM32_STM32F0 + default y if STM32_STM32F30XX + default y if STM32_STM32F33XX + default y if STM32_F7_PERIPHERALS + default y if STM32_STM32G0 + default y if STM32_STM32L0 + +config STM32_ADC2_HAVE_DMA + bool + default y if STM32_STM32F302 + default y if STM32_STM32F303 + default y if STM32_STM32F33XX + default y if STM32_F7_PERIPHERALS + +config STM32_ADC3_HAVE_DMA + bool + default y if STM32_F7_PERIPHERALS + +config STM32_ADC4_HAVE_DMA + bool + +config STM32_ADC5_HAVE_DMA + bool + +config STM32_ADC4_HAVE_TIMER + bool + +config STM32_ADC5_HAVE_TIMER + bool + +config STM32_ADC1_HAVE_OUTPUT_DFSDM + bool + default y if ARCH_CHIP_STM32L4 && STM32_ADC && STM32_ADC1 && STM32_DFSDM1 && STM32_ADC1_DFSDM_L4_CHIP + default y if ARCH_CHIP_STM32L5 && STM32_ADC && STM32_ADC1 && STM32_DFSDM1 && STM32_ADC1_DFSDM_L5_CHIP + default y if ARCH_CHIP_STM32U5 && STM32_ADC && STM32_ADC1 && STM32_DFSDM1 && STM32_ADC1_DFSDM_U5_CHIP + +config STM32_ADC2_HAVE_OUTPUT_DFSDM + bool + default y if ARCH_CHIP_STM32L4 && STM32_ADC && STM32_ADC2 && STM32_DFSDM1 && STM32_STM32L496XX + default y if ARCH_CHIP_STM32L5 && STM32_ADC && STM32_ADC2 && STM32_DFSDM1 && STM32_STM32L596XX + default y if ARCH_CHIP_STM32U5 && STM32_ADC && STM32_ADC2 && STM32_DFSDM1 && STM32_STM32U596XX + +config STM32_ADC3_HAVE_OUTPUT_DFSDM + bool + default y if ARCH_CHIP_STM32L4 && STM32_ADC && STM32_ADC3 && STM32_DFSDM1 && STM32_STM32L496XX + default y if ARCH_CHIP_STM32L5 && STM32_ADC && STM32_ADC3 && STM32_DFSDM1 && STM32_STM32L596XX + default y if ARCH_CHIP_STM32U5 && STM32_ADC && STM32_ADC3 && STM32_DFSDM1 && STM32_STM32U596XX + +config STM32_ADC1_HAVE_TIMER + bool + +config STM32_ADC2_HAVE_TIMER + bool + +config STM32_ADC3_HAVE_TIMER + bool + +menu "STM32L4 ADC Configuration" + depends on STM32_HAVE_ADC_L4 && STM32_ADC + +config STM32_ADC_SMPR + int "ADC sample time" + default 0 + range 0 7 + ---help--- + ADC sample time + 0 - 2.5 ADC clock cycles + 1 - 6.5 ADC clock cycles + 2 - 12.5 ADC clock cycles + 3 - 24.5 ADC clock cycles + 4 - 47.5 ADC clock cycles + 5 - 92.5 ADC clock cycles + 6 - 247.5 ADC clock cycles + 7 - 640.5 ADC clock cycles + +config STM32_ADC1_INJ_CHAN + int "ADC1 configured injected channels" + depends on STM32_ADC1 + range 0 4 + default 0 + ---help--- + Number of configured ADC1 injected channels. + +config STM32_ADC2_INJ_CHAN + int "ADC2 configured injected channels" + depends on STM32_ADC2 + range 0 4 + default 0 + ---help--- + Number of configured ADC2 injected channels. + +config STM32_ADC3_INJ_CHAN + int "ADC3 configured injected channels" + depends on STM32_ADC3 + range 0 4 + default 0 + ---help--- + Number of configured ADC3 injected channels. + +menu "STM32L4 ADCx triggering Configuration" + +config STM32_ADC1_EXTTRIG + int "ADC1 External trigger configuration for regular channels" + default 0 + range 0 4 + depends on STM32_ADC1 + ---help--- + Values 0: Hardware trigger detection disabled + 1: Hardware trigger detection on the rising edge + 2: Hardware trigger detection on the falling edge + 3: Hardware trigger detection on the rising and falling edges + +if STM32_ADC1_EXTTRIG > 0 + +config STM32_ADC_L4_ADC1_EXTSEL + int "ADC1 External trigger selection for regular group" + default 0 + range 0 15 + depends on STM32_ADC1 + ---help--- + Select the external event used to trigger the start of conversion of + a regular group. See Reference Manual for more information. + +endif + +config STM32_ADC2_EXTTRIG + int "ADC2 External trigger configuration for regular channels" + default 0 + range 0 4 + depends on STM32_ADC2 + ---help--- + Values 0: Hardware trigger detection disabled + 1: Hardware trigger detection on the rising edge + 2: Hardware trigger detection on the falling edge + 3: Hardware trigger detection on the rising and falling edges + +if STM32_ADC2_EXTTRIG > 0 + +config STM32_ADC_L4_ADC2_EXTSEL + int "ADC2 External trigger selection for regular group" + default 0 + range 0 15 + depends on STM32_ADC2 + ---help--- + Select the external event used to trigger the start of conversion of + a regular group. See Reference Manual for more information. + +endif + +config STM32_ADC3_EXTTRIG + int "ADC3 External trigger configuration for regular channels" + default 0 + range 0 4 + depends on STM32_ADC3 + ---help--- + Values 0: Hardware trigger detection disabled + 1: Hardware trigger detection on the rising edge + 2: Hardware trigger detection on the falling edge + 3: Hardware trigger detection on the rising and falling edges + +if STM32_ADC3_EXTTRIG > 0 + +config STM32_ADC_L4_ADC3_EXTSEL + int "ADC3 External trigger selection for regular group" + default 0 + range 0 15 + depends on STM32_ADC3 + ---help--- + Select the external event used to trigger the start of conversion of + a regular group. See Reference Manual for more information. + +endif + +if STM32_ADC1_INJ_CHAN > 0 + +config STM32_ADC1_JEXTTRIG + int "ADC1 External Trigger Enable and Polarity Selection for injected channels" + default 0 + range 0 4 + depends on STM32_ADC1 + ---help--- + Values 0: Hardware and software trigger detection disabled, JQDIS=0 + (queue enabled) + 0: Hardware trigger detection disabled, JQDIS=1 (queue disabled) + 1: Hardware trigger detection on the rising edge + 2: Hardware trigger detection on the falling edge + 3: Hardware trigger detection on the rising and falling edges + +if STM32_ADC1_JEXTTRIG > 0 + +config STM32_ADC_L4_ADC1_JEXTSEL + int "ADC1 External Trigger Selection for injected group" + default 0 + range 0 15 + depends on STM32_ADC1 + ---help--- + Select the external event used to trigger the start of conversion of an + injected group + +endif + +endif + +if STM32_ADC2_INJ_CHAN > 0 + +config STM32_ADC2_JEXTTRIG + int "ADC2 External Trigger Enable and Polarity Selection for injected channels" + default 0 + range 0 4 + depends on STM32_ADC2 + ---help--- + Values 0: Hardware and software trigger detection disabled, JQDIS=0 + (queue enabled) + 0: Hardware trigger detection disabled, JQDIS=1 (queue disabled) + 1: Hardware trigger detection on the rising edge + 2: Hardware trigger detection on the falling edge + 3: Hardware trigger detection on the rising and falling edges + +if STM32_ADC2_JEXTTRIG > 0 + +config STM32_ADC_L4_ADC2_JEXTSEL + int "ADC2 External Trigger Selection for injected group" + default 0 + range 0 5 + depends on STM32_ADC2 + ---help--- + Select the external event used to trigger the start of conversion of an + injected group + +endif + +endif + +if STM32_ADC3_INJ_CHAN > 0 + +config STM32_ADC3_JEXTTRIG + int "ADC3 External Trigger Enable and Polarity Selection for injected channels" + default 0 + range 0 4 + depends on STM32_ADC3 + ---help--- + Values 0: Hardware and software trigger detection disabled, JQDIS=0 + (queue enabled) + 0: Hardware trigger detection disabled, JQDIS=1 (queue disabled) + 1: Hardware trigger detection on the rising edge + 2: Hardware trigger detection on the falling edge + 3: Hardware trigger detection on the rising and falling edges + +if STM32_ADC3_JEXTTRIG > 0 + +config STM32_ADC_L4_ADC3_JEXTSEL + int "ADC3 External Trigger Selection for injected group" + default 0 + range 0 5 + depends on STM32_ADC3 + ---help--- + Select the external event used to trigger the start of conversion of an + injected group + +endif + +endif + +endmenu #STM32L4 ADCx triggering Configuration + +endmenu + +menu "ADC Configuration" + depends on STM32_HAVE_ADC_H5 && STM32_ADC + +config STM32_ADC1_OVERSAMPLE + bool "Enable ADC1 hardware oversampling support" + depends on STM32_ADC1 + default n + ---help--- + Enable the on-chip ADC oversampling/accumulation block (CFGR2.OVSE). + Only STM32G0 and STM32L0 series include this hardware block. + +if STM32_ADC1_OVERSAMPLE + +config STM32_ADC1_TROVS + bool "Enable triggered oversampling (CFGR2.TROVS)" + default n + ---help--- + If set, oversampling will only occur when a trigger event occurs. + If not set, oversampling occurs continuously (TOVS=0). + +config STM32_ADC1_OVSR + int "Oversampling ratio (CFGR2.OVSR)" + default 0 + range 0 7 + ---help--- + Sets the oversampling ratio as 2^(OVSR+1). For example: + 0 -> 2× + 1 -> 4× + 2 -> 8× + ... + 7 -> 256× + +config STM32_ADC1_OVSS + int "Oversampling right-shift bits (CFGR2.OVSS)" + default 0 + range 0 8 + ---help--- + Sets how many bits the accumulated result is right-shifted. + Max of 8-bits. + +endif # STM32_ADC1_OVERSAMPLE + +config STM32_ADC1_WDG1 + bool "Enable STM32H5 ADC1 Watchdog 1" + depends on STM32_ADC1 + default n + ---help--- + Enable STM32H5 ADC1 Watchdog 1. + +config STM32_ADC1_WDG1_FLT + int "Set ADC1 Watchdog 1 Filter" + depends on STM32_ADC1_WDG1 + default 0 + range 0 7 + ---help--- + N+1 watchdog events generates an interrupt. + Default: 0. + +config STM32_ADC1_WDG1_LOWTHRESH + int "Set ADC1 Watchdog 1 Low Threshold" + depends on STM32_ADC1_WDG1 + default 0 + range 0 4095 + ---help--- + Set the ADC1 Watchdog 1 low threshold value. + Default: 0. + +config STM32_ADC1_WDG1_HIGHTHRESH + int "Set ADC1 Watchdog 1 High Threshold" + depends on STM32_ADC1_WDG1 + default 4095 + range 0 4095 + ---help--- + Set the ADC1 Watchdog 1 high threshold value. + Default: 4095. + +config STM32_ADC1_WDG1_SGL + bool "Enable STM32H5 ADC1 Watchdog 1 on a single channel" + depends on STM32_ADC1_WDG1 + default n + ---help--- + This option determines if ADC1 Watchdog 1 is enabled on all + channels or just a single channel. + +config STM32_ADC1_WDG1_CHAN + int "STM32H5 ADC1 Watchdog 1 Channel Selection" + depends on STM32_ADC1_WDG1_SGL + default 0 + range 0 19 + ---help--- + Select the channel to enable for ADC1 Watchdog 1. + +config STM32_ADC2_OVERSAMPLE + bool "Enable ADC2 hardware oversampling support" + depends on STM32_ADC2 + default n + ---help--- + Enable the on-chip ADC oversampling/accumulation block (CFGR2.OVSE). + Only STM32G0 and STM32L0 series include this hardware block. + +if STM32_ADC2_OVERSAMPLE + +config STM32_ADC2_TROVS + bool "Enable triggered oversampling (CFGR2.TROVS)" + default n + ---help--- + If set, oversampling will only occur when a trigger event occurs. + If not set, oversampling occurs continuously (TOVS=0). + +config STM32_ADC2_OVSR + int "Oversampling ratio (CFGR2.OVSR)" + default 0 + range 0 7 + ---help--- + Sets the oversampling ratio as 2^(OVSR+1). For example: + 0 -> 2× + 1 -> 4× + 2 -> 8× + ... + 7 -> 256× + +config STM32_ADC2_OVSS + int "Oversampling right-shift bits (CFGR2.OVSS)" + default 0 + range 0 8 + ---help--- + Sets how many bits the accumulated result is right-shifted. + Max of 8-bits. + +endif # STM32_ADC2_OVERSAMPLE + +config STM32_ADC2_WDG1 + bool "Enable STM32H5 ADC2 Watchdog 1" + depends on STM32_ADC2 + default n + ---help--- + Enable STM32H5 ADC2 Watchdog 1. + +config STM32_ADC2_WDG1_FLT + int "Set ADC2 Watchdog 1 Filter" + depends on STM32_ADC2_WDG1 + default 0 + range 0 7 + ---help--- + N+1 watchdog events generates an interrupt. + Default: 0. + +config STM32_ADC2_WDG1_LOWTHRESH + int "Set ADC2 Watchdog 1 Low Threshold" + depends on STM32_ADC2_WDG1 + default 0 + range 0 4095 + ---help--- + Set the ADC2 Watchdog 1 low threshold value. + Default: 0. + +config STM32_ADC2_WDG1_HIGHTHRESH + int "Set ADC2 Watchdog 1 High Threshold" + depends on STM32_ADC2_WDG1 + default 4095 + range 0 4095 + ---help--- + Set the ADC2 Watchdog 1 high threshold value. + Default: 4095. + +config STM32_ADC2_WDG1_SGL + bool "Enable STM32H5 ADC2 Watchdog 1 on a single channel" + depends on STM32_ADC2_WDG1 + default n + ---help--- + This option determines if ADC2 Watchdog 1 is enabled on all + channels or just a single channel. + +config STM32_ADC2_WDG1_CHAN + int "STM32H5 ADC2 Watchdog 1 Channel Selection" + depends on STM32_ADC2_WDG1_SGL + default 0 + range 0 19 + ---help--- + Select the channel to enable for ADC2 Watchdog 1. + +endmenu # ADC Configuration + +config STM32_ADC1_SAMPLE_FREQUENCY + int "ADC1 Sampling Frequency" + depends on STM32_ADC1_HAVE_TIMER_FREQ + default 100 + ---help--- + ADC1 sampling frequency. Default: 100Hz + +config STM32_ADC1_TIMTRIG + int "ADC1 Timer Trigger" + depends on STM32_ADC1_HAVE_TIMTRIG + default 0 + range 0 5 if STM32_HAVE_ADC_TIMTRIG_TRGO2 + range 0 4 if STM32_HAVE_ADC_TIMTRIG_TRGO + ---help--- + Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO 5:TRGO2 + +config STM32_ADC2_SAMPLE_FREQUENCY + int "ADC2 Sampling Frequency" + depends on STM32_ADC2_HAVE_TIMER_FREQ + default 100 + ---help--- + ADC2 sampling frequency. Default: 100Hz + +config STM32_ADC2_TIMTRIG + int "ADC2 Timer Trigger" + depends on STM32_ADC2_HAVE_TIMTRIG + default 0 + range 0 5 if STM32_HAVE_ADC_TIMTRIG_TRGO2 + range 0 4 if STM32_HAVE_ADC_TIMTRIG_TRGO + ---help--- + Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO 5:TRGO2 + +config STM32_ADC3_SAMPLE_FREQUENCY + int "ADC3 Sampling Frequency" + depends on STM32_ADC3_HAVE_TIMTRIG + default 100 + ---help--- + ADC3 sampling frequency. Default: 100Hz + +config STM32_ADC3_TIMTRIG + int "ADC3 Timer Trigger" + depends on STM32_ADC3_HAVE_TIMTRIG && !ARCH_CHIP_STM32L4 + default 0 + range 0 5 if STM32_HAVE_ADC_TIMTRIG_TRGO2 + range 0 4 if STM32_HAVE_ADC_TIMTRIG_TRGO + ---help--- + Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO 5:TRGO2 + +config STM32_ADC1_RESOLUTION + int "ADC1 resolution" + depends on (STM32_HAVE_IP_ADC_M3M4_V1 || STM32_HAVE_IP_ADC_M3M4_V2) && STM32_ADC && STM32_ADC1 && !STM32_HAVE_IP_ADC_M3M4_V1_BASIC || (STM32_HAVE_IP_ADC_M0_V1 || ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_ADC && STM32_ADC1 + default 0 + range 0 3 + ---help--- + ADC1 resolution. 0 - 12 bit, 1 - 10 bit, 2 - 8 bit, 3 - 6 bit + +config STM32_ADC2_RESOLUTION + int "ADC2 resolution" + depends on (STM32_HAVE_IP_ADC_M3M4_V1 || STM32_HAVE_IP_ADC_M3M4_V2) && STM32_ADC && STM32_ADC2 && !STM32_HAVE_IP_ADC_M3M4_V1_BASIC || (ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_ADC && STM32_ADC2 + default 0 + range 0 3 + ---help--- + ADC2 resolution. 0 - 12 bit, 1 - 10 bit, 2 - 8 bit, 3 - 6 bit + +config STM32_ADC3_RESOLUTION + int "ADC3 resolution" + depends on (STM32_HAVE_IP_ADC_M3M4_V1 || STM32_HAVE_IP_ADC_M3M4_V2) && STM32_ADC && STM32_ADC3 && !STM32_HAVE_IP_ADC_M3M4_V1_BASIC || (ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4) && STM32_ADC && STM32_ADC3 + default 0 + range 0 3 + ---help--- + ADC3 resolution. 0 - 12 bit, 1 - 10 bit, 2 - 8 bit, 3 - 6 bit + +config STM32_ADC_MAX_SAMPLES + int "The maximum number of channels that can be sampled" + depends on STM32_ADC + default 1 if STM32_HAVE_IP_ADC_M0_V1 && !STM32_ADC1_DMA + default 16 + ---help--- + The maximum number of samples which can be handled without + overrun depends on various factors. This is the user's + responsibility to correctly select this value. + Since the interface to update the sampling time is available + for all supported devices, the user can change the default + values in the board initialization logic and avoid ADC overrun. + +config STM32_ADC_NO_STARTUP_CONV + bool "Do not start conversion when opening ADC device" + depends on STM32_ADC + ---help--- + Do not start conversion when opening ADC device. + +config STM32_ADC_NOIRQ + bool "Do not use default ADC interrupts" + depends on STM32_ADC + ---help--- + Do not use default ADC interrupts handlers. + +config STM32_ADC_LL_OPS + bool "ADC low-level operations" + depends on STM32_ADC + ---help--- + Enable low-level ADC ops. + +config STM32_ADC_CHANGE_SAMPLETIME + bool "ADC sample time configuration" + depends on ((STM32_HAVE_IP_ADC_M3M4_V1 || STM32_HAVE_IP_ADC_M3M4_V2) || STM32_HAVE_IP_ADC_M0_V1 || ARCH_CHIP_STM32F7) && STM32_ADC_LL_OPS + ---help--- + Enable ADC sample time configuration (SMPRx registers). + +config STM32_ADC_OVERSAMPLE + bool "Enable ADC hardware oversampling support" + depends on STM32_ADC1 && STM32_HAVE_ADC_OVERSAMPLE + ---help--- + Enable the on-chip ADC oversampling/accumulation block (CFGR2.OVSE). + Only STM32G0 and STM32L0 series include this hardware block. + +if STM32_ADC_OVERSAMPLE + +config STM32_ADC_TOVS + bool "Enable triggered oversampling (CFGR2.TOVS)" + ---help--- + If set, oversampling will only occur when a trigger event occurs. + If not set, oversampling occurs continuously (TOVS=0). + +config STM32_ADC_OVSR + int "Oversampling ratio (CFGR2.OVSR)" + default 0 + range 0 7 + ---help--- + Sets the oversampling ratio as 2^(OVSR+1). For example: + 0 -> 2x + 1 -> 4x + 2 -> 8x + ... + 7 -> 256x + +config STM32_ADC_OVSS + int "Oversampling right-shift bits (CFGR2.OVSS)" + default 0 + range 0 8 + ---help--- + Sets how many bits the accumulated result is right-shifted. + Max of 8-bits. + +endif # STM32_ADC_OVERSAMPLE + +config STM32_ADC1_DMA + bool "ADC1 DMA" + depends on ((STM32_HAVE_IP_ADC_M3M4_V1 || STM32_HAVE_IP_ADC_M3M4_V2) || STM32_HAVE_IP_ADC_M0_V1 || ARCH_CHIP_STM32F7) && STM32_ADC && STM32_ADC1 && STM32_ADC1_HAVE_DMA || ARCH_CHIP_STM32H7 && STM32_ADC && STM32_ADC1 && EXPERIMENTAL || STM32_COMMON_L4_L5_U5 && STM32_ADC && STM32_ADC1 || ARCH_CHIP_STM32H5 && STM32_ADC && STM32_ADC1 && STM32_DMA + ---help--- + If DMA is selected, then the ADC may be configured to support + DMA transfer, which is necessary if multiple channels are read + or if very high trigger frequencies are used. + +config STM32_ADC1_SCAN + bool "ADC1 scan mode" + depends on ((STM32_HAVE_IP_ADC_M3M4_V1 || STM32_HAVE_IP_ADC_M3M4_V2) && STM32_ADC && STM32_ADC1 && STM32_HAVE_IP_ADC_M3M4_V1) || (ARCH_CHIP_STM32F7 && STM32_ADC && STM32_ADC1) + default STM32_ADC1_DMA + +config STM32_ADC1_DMA_CFG + int "ADC1 DMA configuration" + depends on ((STM32_HAVE_IP_ADC_M3M4_V1 || STM32_HAVE_IP_ADC_M3M4_V2) || STM32_HAVE_IP_ADC_M0_V1) && STM32_ADC && STM32_ADC1_DMA && !STM32_HAVE_IP_ADC_M3M4_V1_BASIC || (ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_ADC && STM32_ADC1_DMA + default 1 if ARCH_CHIP_STM32L4 + default 0 + range 0 1 + ---help--- + 0 - ADC1 DMA in One Shot Mode, 1 - ADC1 DMA in Circular Mode + +config STM32_ADC1_DMA_BATCH + int "ADC1 DMA number of conversions" + depends on ((STM32_HAVE_IP_ADC_M3M4_V1 || STM32_HAVE_IP_ADC_M3M4_V2) || STM32_HAVE_IP_ADC_M0_V1 || STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_ADC && STM32_ADC1 && STM32_ADC1_DMA + default 1 + ---help--- + This option allows you to select the number of regular group conversions + that will trigger a DMA callback transerring data to the upper-half driver. + By default, this value is 1, which means that data is transferred after + each group conversion. + +config STM32_ADC1_ANIOC_TRIGGER + int "ADC1 software trigger (ANIOC_TRIGGER) configuration" + depends on (((STM32_HAVE_IP_ADC_M3M4_V1 || STM32_HAVE_IP_ADC_M3M4_V2) || ARCH_CHIP_STM32F7) && STM32_ADC && STM32_ADC1) + default 3 + range 1 3 + ---help--- + 1 - ANIOC_TRIGGER only starts regular conversion + 2 - ANIOC_TRIGGER only starts injected conversion + 3 - ANIOC_TRIGGER starts both regular and injected conversions + +config STM32_ADC2_DMA + bool "ADC2 DMA" + depends on ((STM32_HAVE_IP_ADC_M3M4_V1 || STM32_HAVE_IP_ADC_M3M4_V2) || ARCH_CHIP_STM32F7) && STM32_ADC && STM32_ADC2 && STM32_ADC2_HAVE_DMA || ARCH_CHIP_STM32H7 && STM32_ADC && STM32_ADC2 && EXPERIMENTAL || STM32_COMMON_L4_L5_U5 && STM32_ADC && STM32_ADC2 || ARCH_CHIP_STM32H5 && STM32_ADC && STM32_ADC2 && STM32_DMA + ---help--- + If DMA is selected, then the ADC may be configured to support + DMA transfer, which is necessary if multiple channels are read + or if very high trigger frequencies are used. + +config STM32_ADC2_SCAN + bool "ADC2 scan mode" + depends on ((STM32_HAVE_IP_ADC_M3M4_V1 || STM32_HAVE_IP_ADC_M3M4_V2) && STM32_ADC && STM32_ADC2 && STM32_HAVE_IP_ADC_M3M4_V1) || (ARCH_CHIP_STM32F7 && STM32_ADC && STM32_ADC2) + default STM32_ADC2_DMA + +config STM32_ADC2_DMA_CFG + int "ADC2 DMA configuration" + depends on (STM32_HAVE_IP_ADC_M3M4_V1 || STM32_HAVE_IP_ADC_M3M4_V2) && STM32_ADC && STM32_ADC2_DMA && !STM32_HAVE_IP_ADC_M3M4_V1_BASIC || (ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4) && STM32_ADC && STM32_ADC2_DMA || ARCH_CHIP_STM32H5 && STM32_ADC && STM32_ADC2_DMA && STM32_DMA + default 1 if ARCH_CHIP_STM32L4 + default 0 + range 0 1 + ---help--- + 0 - ADC2 DMA in One Shot Mode, 1 - ADC2 DMA in Circular Mode + +config STM32_ADC2_DMA_BATCH + int "ADC2 DMA number of conversions" + depends on ((STM32_HAVE_IP_ADC_M3M4_V1 || STM32_HAVE_IP_ADC_M3M4_V2) || STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_ADC && STM32_ADC2 && STM32_ADC2_DMA + default 1 + ---help--- + This option allows you to select the number of regular group conversions + that will trigger a DMA callback transerring data to the upper-half driver. + By default, this value is 1, which means that data is transferred after + each group conversion. + +config STM32_ADC2_ANIOC_TRIGGER + int "ADC2 software trigger (ANIOC_TRIGGER) configuration" + depends on (((STM32_HAVE_IP_ADC_M3M4_V1 || STM32_HAVE_IP_ADC_M3M4_V2) || ARCH_CHIP_STM32F7) && STM32_ADC && STM32_ADC2) + default 3 + range 1 3 + ---help--- + 1 - ANIOC_TRIGGER only starts regular conversion + 2 - ANIOC_TRIGGER only starts injected conversion + 3 - ANIOC_TRIGGER starts both regular and injected conversions + +config STM32_ADC3_DMA + bool "ADC3 DMA" + depends on ((STM32_HAVE_IP_ADC_M3M4_V1 || STM32_HAVE_IP_ADC_M3M4_V2) || ARCH_CHIP_STM32F7) && STM32_ADC && STM32_ADC3 && STM32_ADC3_HAVE_DMA || ARCH_CHIP_STM32H7 && STM32_ADC && STM32_ADC3 && EXPERIMENTAL || STM32_COMMON_L4_L5_U5 && STM32_ADC && STM32_ADC3 + ---help--- + If DMA is selected, then the ADC may be configured to support + DMA transfer, which is necessary if multiple channels are read + or if very high trigger frequencies are used. + +config STM32_ADC3_SCAN + bool "ADC3 scan mode" + depends on ((STM32_HAVE_IP_ADC_M3M4_V1 || STM32_HAVE_IP_ADC_M3M4_V2) && STM32_ADC && STM32_ADC3 && STM32_HAVE_IP_ADC_M3M4_V1) || (ARCH_CHIP_STM32F7 && STM32_ADC && STM32_ADC3) + default STM32_ADC3_DMA + +config STM32_ADC3_DMA_CFG + int "ADC3 DMA configuration" + depends on (STM32_HAVE_IP_ADC_M3M4_V1 || STM32_HAVE_IP_ADC_M3M4_V2) && STM32_ADC && STM32_ADC3_DMA && !STM32_HAVE_IP_ADC_M3M4_V1_BASIC || (ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4) && STM32_ADC && STM32_ADC3_DMA + default 1 if ARCH_CHIP_STM32L4 + default 0 + range 0 1 + ---help--- + 0 - ADC3 DMA in One Shot Mode, 1 - ADC3 DMA in Circular Mode + +config STM32_ADC3_DMA_BATCH + int "ADC3 DMA number of conversions" + depends on ((STM32_HAVE_IP_ADC_M3M4_V1 || STM32_HAVE_IP_ADC_M3M4_V2) || STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4) && STM32_ADC && STM32_ADC3 && STM32_ADC3_DMA + default 1 + ---help--- + This option allows you to select the number of regular group conversions + that will trigger a DMA callback transerring data to the upper-half driver. + By default, this value is 1, which means that data is transferred after + each group conversion. + +config STM32_ADC3_ANIOC_TRIGGER + int "ADC3 software trigger (ANIOC_TRIGGER) configuration" + depends on (((STM32_HAVE_IP_ADC_M3M4_V1 || STM32_HAVE_IP_ADC_M3M4_V2) || ARCH_CHIP_STM32F7) && STM32_ADC && STM32_ADC3) + default 3 + range 1 3 + ---help--- + 1 - ANIOC_TRIGGER only starts regular conversion + 2 - ANIOC_TRIGGER only starts injected conversion + 3 - ANIOC_TRIGGER starts both regular and injected conversions + +config STM32_ADC1_INJECTED_CHAN + int "ADC1 injected channels" + depends on (((STM32_HAVE_IP_ADC_M3M4_V1 || STM32_HAVE_IP_ADC_M3M4_V2) || ARCH_CHIP_STM32F7) && STM32_ADC && STM32_ADC1) + default 0 + range 0 4 + ---help--- + Support for ADC1 injected channels. + +config STM32_ADC2_INJECTED_CHAN + int "ADC2 injected channels" + depends on (((STM32_HAVE_IP_ADC_M3M4_V1 || STM32_HAVE_IP_ADC_M3M4_V2) || ARCH_CHIP_STM32F7) && STM32_ADC && STM32_ADC2) + default 0 + range 0 4 + ---help--- + Support for ADC2 injected channels. + +config STM32_ADC3_INJECTED_CHAN + int "ADC3 injected channels" + depends on (((STM32_HAVE_IP_ADC_M3M4_V1 || STM32_HAVE_IP_ADC_M3M4_V2) || ARCH_CHIP_STM32F7) && STM32_ADC && STM32_ADC3) + default 0 + range 0 4 + ---help--- + Support for ADC3 injected channels. + +config STM32_ADC1_EXTSEL + bool "ADC1 external trigger for regular group" + depends on ((STM32_HAVE_IP_ADC_M3M4_V1 || STM32_HAVE_IP_ADC_M3M4_V2) || STM32_HAVE_IP_ADC_M0_V1 || ARCH_CHIP_STM32F7) && STM32_ADC && STM32_ADC1 && !STM32_ADC1_HAVE_TIMER + ---help--- + Enable EXTSEL for ADC1. + +config STM32_ADC2_EXTSEL + bool "ADC2 external trigger for regular group" + depends on (((STM32_HAVE_IP_ADC_M3M4_V1 || STM32_HAVE_IP_ADC_M3M4_V2) || ARCH_CHIP_STM32F7) && STM32_ADC && STM32_ADC2) && !STM32_ADC2_HAVE_TIMER + ---help--- + Enable EXTSEL for ADC2. + +config STM32_ADC3_EXTSEL + bool "ADC3 external trigger for regular group" + depends on (((STM32_HAVE_IP_ADC_M3M4_V1 || STM32_HAVE_IP_ADC_M3M4_V2) || ARCH_CHIP_STM32F7) && STM32_ADC && STM32_ADC3) && !STM32_ADC3_HAVE_TIMER + ---help--- + Enable EXTSEL for ADC3. + +config STM32_ADC1_JEXTSEL + bool "ADC1 external trigger for injected group" + depends on (((STM32_HAVE_IP_ADC_M3M4_V1 || STM32_HAVE_IP_ADC_M3M4_V2) || ARCH_CHIP_STM32F7) && STM32_ADC && STM32_ADC1) + ---help--- + Enable JEXTSEL for ADC1. + +config STM32_ADC2_JEXTSEL + bool "ADC2 external trigger for injected group" + depends on (((STM32_HAVE_IP_ADC_M3M4_V1 || STM32_HAVE_IP_ADC_M3M4_V2) || ARCH_CHIP_STM32F7) && STM32_ADC && STM32_ADC2) + ---help--- + Enable JEXTSEL for ADC2. + +config STM32_ADC3_JEXTSEL + bool "ADC3 external trigger for injected group" + depends on (((STM32_HAVE_IP_ADC_M3M4_V1 || STM32_HAVE_IP_ADC_M3M4_V2) || ARCH_CHIP_STM32F7) && STM32_ADC && STM32_ADC3) + ---help--- + Enable JEXTSEL for ADC3. + +config STM32_DAC1_OUTPUT_ADC + bool "DAC1 output to ADC" + depends on STM32_COMMON_L4_L5_U5 && STM32_DAC && STM32_DAC1 + ---help--- + Route DAC1 output to ADC input instead of external pin. + +config STM32_DAC2_OUTPUT_ADC + bool "DAC2 output to ADC" + depends on STM32_COMMON_L4_L5_U5 && STM32_DAC && STM32_DAC2 + ---help--- + Route DAC2 output to ADC input instead of external pin. + +config STM32_ADC1_OUTPUT_DFSDM + bool "ADC1 output to DFSDM" + depends on STM32_ADC1_HAVE_OUTPUT_DFSDM + ---help--- + Route ADC1 output directly to DFSDM parallel inputs. + +config STM32_ADC2_OUTPUT_DFSDM + bool "ADC2 output to DFSDM" + depends on STM32_ADC2_HAVE_OUTPUT_DFSDM + ---help--- + Route ADC2 output directly to DFSDM parallel inputs. + +config STM32_ADC3_OUTPUT_DFSDM + bool "ADC3 output to DFSDM" + depends on STM32_ADC3_HAVE_OUTPUT_DFSDM + ---help--- + Route ADC3 output directly to DFSDM parallel inputs. + +config STM32_ADC4_RESOLUTION + int "ADC4 resolution" + depends on STM32_ADC4 && !STM32_HAVE_IP_ADC_M3M4_V1_BASIC + default 0 + range 0 3 + ---help--- + ADC4 resolution. 0 - 12 bit, 1 - 10 bit, 2 - 8 bit, 3 - 6 bit + +config STM32_ADC5_RESOLUTION + int "ADC5 resolution" + depends on STM32_ADC5 && !STM32_HAVE_IP_ADC_M3M4_V1_BASIC + default 0 + range 0 3 + ---help--- + ADC5 resolution. 0 - 12 bit, 1 - 10 bit, 2 - 8 bit, 3 - 6 bit + +config STM32_ADC4_DMA + bool "ADC4 DMA" + depends on STM32_ADC4 && STM32_ADC4_HAVE_DMA + default n + ---help--- + If DMA is selected, then the ADC may be configured to support + DMA transfer, which is necessary if multiple channels are read + or if very high trigger frequencies are used. + +config STM32_ADC4_DMA_CFG + int "ADC4 DMA configuration" + depends on STM32_ADC4_DMA && !STM32_HAVE_IP_ADC_M3M4_V1_BASIC + range 0 1 + default 0 + ---help--- + 0 - ADC4 DMA in One Shot Mode, 1 - ADC4 DMA in Circular Mode + +config STM32_ADC4_DMA_BATCH + int "ADC4 DMA number of conversions" + depends on STM32_ADC4 && STM32_ADC4_DMA + default 1 + ---help--- + This option allows you to select the number of regular group conversions + that will trigger a DMA callback transerring data to the upper-half driver. + By default, this value is 1, which means that data is transferred after + each group conversion. + +config STM32_ADC4_ANIOC_TRIGGER + int "ADC4 software trigger (ANIOC_TRIGGER) configuration" + depends on STM32_ADC4 + range 1 3 + default 3 + ---help--- + 1 - ANIOC_TRIGGER only starts regular conversion + 2 - ANIOC_TRIGGER only starts injected conversion + 3 - ANIOC_TRIGGER starts both regular and injected conversions + +config STM32_ADC5_DMA + bool "ADC5 DMA" + depends on STM32_ADC5 && STM32_ADC5_HAVE_DMA + default n + ---help--- + If DMA is selected, then the ADC may be configured to support + DMA transfer, which is necessary if multiple channels are read + or if very high trigger frequencies are used. + +config STM32_ADC5_DMA_CFG + int "ADC5 DMA configuration" + depends on STM32_ADC5_DMA && !STM32_HAVE_IP_ADC_M3M4_V1_BASIC + range 0 1 + default 0 + ---help--- + 0 - ADC5 DMA in One Shot Mode, 1 - ADC5 DMA in Circular Mode + +config STM32_ADC5_DMA_BATCH + int "ADC5 DMA number of conversions" + depends on STM32_ADC5 && STM32_ADC5_DMA + default 1 + ---help--- + This option allows you to select the number of regular group conversions + that will trigger a DMA callback transerring data to the upper-half driver. + By default, this value is 1, which means that data is transferred after + each group conversion. + +config STM32_ADC4_INJECTED_CHAN + int "ADC4 injected channels" + depends on STM32_ADC4 + range 0 4 + default 0 + ---help--- + Support for ADC4 injected channels. + +config STM32_ADC5_INJECTED_CHAN + int "ADC5 injected channels" + depends on STM32_ADC5 + range 0 4 + default 0 + ---help--- + Support for ADC5 injected channels. + +config STM32_ADC4_EXTSEL + bool "ADC4 external trigger for regular group" + depends on STM32_ADC4 && !STM32_ADC4_HAVE_TIMER + default n + ---help--- + Enable EXTSEL for ADC4. + +config STM32_ADC5_EXTSEL + bool "ADC5 external trigger for regular group" + depends on STM32_ADC5 && !STM32_ADC5_HAVE_TIMER + default n + ---help--- + Enable EXTSEL for ADC5. + +config STM32_ADC4_JEXTSEL + bool "ADC4 external trigger for injected group" + depends on STM32_ADC4 + default n + ---help--- + Enable JEXTSEL for ADC4. + +config STM32_ADC5_JEXTSEL + bool "ADC5 external trigger for injected group" + depends on STM32_ADC5 + default n + ---help--- + Enable JEXTSEL for ADC5. + +config STM32_ADC1_CONTINUOUS + bool "Enable ADC1 Continuous Conversion Mode" + default n + depends on STM32_ADC1 && STM32_HAVE_IP_ADC_M0_V1 + ---help--- + If enabled, the ADC will operate in continuous conversion mode. + Otherwise, it will perform single conversions. + Note: Continuous and discontinuous mode cannot be defined at + the same time diff --git a/arch/arm/src/common/stm32/Kconfig.ble b/arch/arm/src/common/stm32/Kconfig.ble new file mode 100644 index 0000000000000..dd91f1fe66233 --- /dev/null +++ b/arch/arm/src/common/stm32/Kconfig.ble @@ -0,0 +1,221 @@ +# +# STM32 common BLE options. +# + +if STM32_BLE + +config STM32_BLE_C2HOST + bool "Enable CPU2 HOST stack" + default n + ---help--- + The full stack version of CPU2 firmware allows to enable CPU2 HOST stack and + control it using vendor ACL protocol. However, it is not expected to enable + this option in the current implementation. + +config STM32_BLE_MAX_CONN + int "Maximum BLE simultaneous connections" + range 1 8 + default 2 + +config STM32_BLE_GATT_MAX_ATTR_NUM + int "GATT attributes max count" + range 9 255 + default 64 + +config STM32_BLE_GATT_MAX_SVC_NUM + int "GATT services max count" + range 2 64 + default 8 + +config STM32_BLE_GATT_ATTR_BUF_SIZE + int "GATT attributes storage buf size" + default 1344 + ---help--- + Size of the storage area for attribute values. Hardcoded in CPU2 firmware. + +config STM32_BLE_DLE + bool "Support Data Length Extension (DLE)" + default y + +config STM32_BLE_MAX_ATT_MTU + int "Maximum supported attribute MTU" + range 23 512 + default 156 + +config STM32_BLE_SLAVE_SCA + int "Sleep clock accuracy in slave mode [PPM]" + default 500 + ---help--- + Sleep clock accuracy (ppm value) in slave mode. + +choice + prompt "Sleep clock accuracy in master mode" + default STM32_BLE_MASTER_SCA_0 + ---help--- + Sleep clock accuracy in master mode. + +config STM32_BLE_MASTER_SCA_0 + bool "251-500 ppm" + +config STM32_BLE_MASTER_SCA_1 + bool "151-250 ppm" + +config STM32_BLE_MASTER_SCA_2 + bool "101-150 ppm" + +config STM32_BLE_MASTER_SCA_3 + bool "76-100 ppm" + +config STM32_BLE_MASTER_SCA_4 + bool "51-75 ppm" + +config STM32_BLE_MASTER_SCA_5 + bool "31-50 ppm" + +config STM32_BLE_MASTER_SCA_6 + bool "21-30 ppm" + +config STM32_BLE_MASTER_SCA_7 + bool "0-20 ppm" + +endchoice # Sleep clock accuracy in master mode + +config STM32_BLE_MASTER_SCA + int + default 7 if STM32_BLE_MASTER_SCA_7 + default 6 if STM32_BLE_MASTER_SCA_6 + default 5 if STM32_BLE_MASTER_SCA_5 + default 4 if STM32_BLE_MASTER_SCA_4 + default 3 if STM32_BLE_MASTER_SCA_3 + default 2 if STM32_BLE_MASTER_SCA_2 + default 1 if STM32_BLE_MASTER_SCA_1 + default 0 + +choice + prompt "Low speed clock source" + default STM32_BLE_LS_CLK_SRC_LSE + ---help--- + Low speed 32 kHz clock source. + +config STM32_BLE_LS_CLK_SRC_LSE + bool "LSE" + +config STM32_BLE_LS_CLK_SRC_HSE + bool "HSE" + +endchoice # Low speed clock source + +config STM32_BLE_LS_CLK_SRC + int + default 1 if STM32_BLE_LS_CLKSRC_HSE + default 0 + +config STM32_BLE_MAX_CONN_EVT_LENGTH + hex "Max connection event length" + default 0xffffffff + ---help--- + Maximum duration of a slave connection event in units of 625/256us (~2.44us). + +config STM32_BLE_HSE_STARTUP + hex "HSE startup time" + default 0x148 + ---help--- + HSE startup time in units of 625/256us (~2.44us). + +config STM32_BLE_VITERBI + bool "Enable Viterbi algorithm" + default y + ---help--- + Enable Viterbi algorithm implementation + +config STM32_BLE_MAX_INITOR_COC_NUM + int "Max number of connection-oriented channels" + range 0 64 + default 32 + ---help--- + Maximum number of connection-oriented channels in initiator mode. + +config STM32_BLE_SVC_CHANGED_CHAR + bool "Enable service changed characteristic" + default n + +config STM32_BLE_WRITABLE_DEVICE_NAME + bool "Writable device name" + default y + +config STM32_BLE_CHAN_SEL_ALG2 + bool "Enable channel selection algorithm 2" + default n + +choice + prompt "Power class" + default STM32_BLE_POWER_CLASS_2_3 + +config STM32_BLE_POWER_CLASS_2_3 + bool "Power Class 2-3" + +config STM32_BLE_POWER_CLASS_1 + bool "Power Class 1" + +endchoice # Power class + +config STM32_BLE_MIN_TX_POWER + int "Minimum transmit power [dBm]" + range -127 20 + default 0 + +config STM32_BLE_MAX_TX_POWER + int "Maximum transmit power [dBm]" + range -127 20 + default 0 + +choice + prompt "AGC RSSI model" + default STM32_BLE_AGC_RSSI_LEGACY + +config STM32_BLE_AGC_RSSI_LEGACY + bool "AGC RSSI Legacy" + +config STM32_BLE_AGC_RSSI_IMPROVED + bool "AGC RSSI Improved" + +endchoice # AGC RSSI model + +config STM32_BLE_ADVERTISING + bool "Support advertising" + default y + +config STM32_BLE_SCANNING + bool "Support scanning" + default y + +config STM32_BLE_LE_2M_PHY + bool "Support LE 2M PHY" + default y + +config STM32_BLE_LE_CODED_PHY + bool "Support LE Coded PHY" + default STM32_STM32WB15 || STM32_STM32WB35 || STM32_STM32WB55 + depends on STM32_STM32WB15 || STM32_STM32WB35 || STM32_STM32WB55 + +config STM32_BLE_FICR_STATIC_ADDR + bool "Configure factory generated static random address" + default n + +config STM32_BLE_PUB_ADDR + hex "Configure BT public address" + default 0x0000000000 + +endif # STM32_BLE + +if STM32_MBOX + +config STM32_MBOX_TX_CMD_QUEUE_LEN + int "Mailbox TX command queue length" + default 2 + +config STM32_MBOX_RX_EVT_QUEUE_LEN + int "Mailbox RX event queue length" + default 5 + +endif # STM32_MBOX diff --git a/arch/arm/src/common/stm32/Kconfig.cache b/arch/arm/src/common/stm32/Kconfig.cache new file mode 100644 index 0000000000000..c9ebbd5e29104 --- /dev/null +++ b/arch/arm/src/common/stm32/Kconfig.cache @@ -0,0 +1,240 @@ +# +# STM32 common CACHE options. +# + +# STM32 cache configuration options. + +menu "ICACHE Configuration" + depends on STM32_ICACHE + +config STM32_ICACHE_MONITOR_EN + bool "Enable ICACHE Hit/Miss Counters" + default n + +config STM32_ICACHE_DIRECT + bool "Enable 1-Way Direct Mapped Cache (N-Way = default)" + default n + +menu "ICACHE Interrupt Configuration" + depends on STM32_ICACHE + +config STM32_ICACHE_INV_INT + bool "Enable interrupts on full invalidation completion." + default n + +config STM32_ICACHE_ERR_INT + bool "Enable interrupts on occurrences of cache errors." + default n + +endmenu # ICACHE Interrupt Configuration + +menu "ICACHE Region Configuration" + depends on STM32_ICACHE + +config STM32_ICACHE_REGION0 + bool "Enable Configuration of ICACHE Region 0" + default n + +config STM32_ICACHE_REGION1 + bool "Enable Configuration of ICACHE Region 1" + default n + +config STM32_ICACHE_REGION2 + bool "Enable Configuration of ICACHE Region 2" + default n + +config STM32_ICACHE_REGION3 + bool "Enable Configuration of ICACHE Region 3" + default n + +menu "Region 0 Configuration" + depends on STM32_ICACHE_REGION0 && STM32_HAVE_ICACHE_REMAP + +config STM32_ICACHE_REGION0_BADDR + hex "ICACHE Region 0 Base Address Bits [28:21]" + default 0 + range 0 255 + depends on STM32_ICACHE_REGION0 + ---help--- + Set bits [28:21] of the base address for ICACHE Region 0. + +config STM32_ICACHE_REGION0_RSIZE + int "ICACHE Region 0 Size" + default 1 + range 1 7 + depends on STM32_ICACHE_REGION0 + ---help--- + Set the size of Region 0. + 1 = 2 Mbytes, 2 = 4 Mbytes, 3 = 8 Mbytes, 4 = 16 Mbytes, + 5 = 2 Mbytes, 6 = 64 Mbytes, 7 = 128 Mbytes. + +config STM32_ICACHE_REGION0_REMAPADDR + hex "ICACHE Region 0 Remap Address Bits [31:21]" + default 0 + range 0 2047 + depends on STM32_ICACHE_REGION0 + ---help--- + Set bits [31:21] of ICACHE Region 0 Remap Address.. + +config STM32_ICACHE_REGION0_MSTSEL + int "ICACHE Region 0 Master Select (0 or 1)" + default 0 + range 0 1 + depends on STM32_ICACHE_REGION0 + ---help--- + Select ICACHE Region 0 Master 1 (0) or Master 2 (1). + +config STM32_ICACHE_REGION0_HBURST + int "ICACHE Region 0 Output Burst Type (0 = Wrap, 1 = Incr)" + default 0 + range 0 1 + depends on STM32_ICACHE_REGION0 + ---help--- + Select Wrap (0) or Increment (1) Output Burst Type. + +endmenu # Region 0 Configuration + +menu "Region 1 Configuration" + depends on STM32_ICACHE_REGION1 && STM32_HAVE_ICACHE_REMAP + +config STM32_ICACHE_REGION1_BADDR + hex "ICACHE Region 1 Base Address Bits [28:21]" + default 0 + range 0 255 + depends on STM32_ICACHE_REGION1 + ---help--- + Set bits [28:21] of the base address for ICACHE Region 1. + +config STM32_ICACHE_REGION1_RSIZE + int "ICACHE Region 1 Size" + default 1 + range 1 7 + depends on STM32_ICACHE_REGION1 + ---help--- + Set the size of Region 1. + 1 = 2 Mbytes, 2 = 4 Mbytes, 3 = 8 Mbytes, 4 = 16 Mbytes, + 5 = 2 Mbytes, 6 = 64 Mbytes, 7 = 128 Mbytes. + +config STM32_ICACHE_REGION1_REMAPADDR + hex "ICACHE Region 1 Remap Address Bits [31:21]" + default 0 + range 0 2047 + depends on STM32_ICACHE_REGION1 + ---help--- + Set bits [31:21] of ICACHE Region 1 Remap Address.. + +config STM32_ICACHE_REGION1_MSTSEL + int "ICACHE Region 1 Master Select (0 or 1)" + default 0 + range 0 1 + depends on STM32_ICACHE_REGION1 + ---help--- + Select ICACHE Region 1 Master 1 (0) or Master 2 (1). + +config STM32_ICACHE_REGION1_HBURST + int "ICACHE Region 1 Output Burst Type (0 = Wrap, 1 = Incr)" + default 0 + range 0 1 + depends on STM32_ICACHE_REGION1 + ---help--- + Select Wrap (0) or Increment (1) Output Burst Type. + +endmenu # Region 1 Configuration + +menu "Region 2 Configuration" + depends on STM32_ICACHE_REGION2 && STM32_HAVE_ICACHE_REMAP + +config STM32_ICACHE_REGION2_BADDR + hex "ICACHE Region 2 Base Address Bits [28:21]" + default 0 + range 0 255 + depends on STM32_ICACHE_REGION2 + ---help--- + Set bits [28:21] of the base address for ICACHE Region 2. + +config STM32_ICACHE_REGION2_RSIZE + int "ICACHE Region 2 Size" + default 1 + range 1 7 + depends on STM32_ICACHE_REGION2 + ---help--- + Set the size of Region 2. + 1 = 2 Mbytes, 2 = 4 Mbytes, 3 = 8 Mbytes, 4 = 16 Mbytes, + 5 = 2 Mbytes, 6 = 64 Mbytes, 7 = 128 Mbytes. + +config STM32_ICACHE_REGION2_REMAPADDR + hex "ICACHE Region 2 Remap Address Bits [31:21]" + default 0 + range 0 2047 + depends on STM32_ICACHE_REGION2 + ---help--- + Set bits [31:21] of ICACHE Region 2 Remap Address.. + +config STM32_ICACHE_REGION2_MSTSEL + int "ICACHE Region 2 Master Select (0 or 1)" + default 0 + range 0 1 + depends on STM32_ICACHE_REGION2 + ---help--- + Select ICACHE Region 2 Master 1 (0) or Master 2 (1). + +config STM32_ICACHE_REGION2_HBURST + int "ICACHE Region 2 Output Burst Type (0 = Wrap, 1 = Incr)" + default 0 + range 0 1 + depends on STM32_ICACHE_REGION2 + ---help--- + Select Wrap (0) or Increment (1) Output Burst Type. + +endmenu # Region 2 Configuration + +menu "Region 3 Configuration" + depends on STM32_ICACHE_REGION3 && STM32_HAVE_ICACHE_REMAP + +config STM32_ICACHE_REGION3_BADDR + hex "ICACHE Region 3 Base Address Bits [28:21]" + default 0 + range 0 255 + depends on STM32_ICACHE_REGION3 + ---help--- + Set bits [28:21] of the base address for ICACHE Region 3. + +config STM32_ICACHE_REGION3_RSIZE + int "ICACHE Region 3 Size" + default 1 + range 1 7 + depends on STM32_ICACHE_REGION3 + ---help--- + Set the size of Region 3. + 1 = 2 Mbytes, 2 = 4 Mbytes, 3 = 8 Mbytes, 4 = 16 Mbytes, + 5 = 2 Mbytes, 6 = 64 Mbytes, 7 = 128 Mbytes. + +config STM32_ICACHE_REGION3_REMAPADDR + hex "ICACHE Region 3 Remap Address Bits [31:21]" + default 0 + range 0 2047 + depends on STM32_ICACHE_REGION3 + ---help--- + Set bits [31:21] of ICACHE Region 3 Remap Address.. + +config STM32_ICACHE_REGION3_MSTSEL + int "ICACHE Region 3 Master Select (0 or 1)" + default 0 + range 0 1 + depends on STM32_ICACHE_REGION3 + ---help--- + Select ICACHE Region 3 Master 1 (0) or Master 2 (1). + +config STM32_ICACHE_REGION3_HBURST + int "ICACHE Region 3 Output Burst Type (0 = Wrap, 1 = Incr)" + default 0 + range 0 1 + depends on STM32_ICACHE_REGION3 + ---help--- + Select Wrap (0) or Increment (1) Output Burst Type. + +endmenu # Region 3 Configuration + +endmenu # ICACHE Region Configuration + +endmenu # ICACHE Configuration diff --git a/arch/arm/src/common/stm32/Kconfig.can b/arch/arm/src/common/stm32/Kconfig.can new file mode 100644 index 0000000000000..c12794cb03fc4 --- /dev/null +++ b/arch/arm/src/common/stm32/Kconfig.can @@ -0,0 +1,63 @@ +# +# STM32 common CAN options. +# + +# STM32 CAN configuration options. + +choice + prompt "CAN character driver or SocketCAN support" + depends on STM32_CAN + default STM32_CAN_CHARDRIVER + +config STM32_CAN_CHARDRIVER + bool "STM32 CAN character driver support" + select ARCH_HAVE_CAN_ERRORS + select CAN + +config STM32_CAN_SOCKET + bool "STM32 CAN SocketCAN support" + select NET_CAN_HAVE_ERRORS + +endchoice # CAN character driver or SocketCAN support + +config STM32_CAN1_BAUD + int "CAN1 BAUD" + depends on STM32_CAN1 + default 250000 + ---help--- + CAN1 BAUD rate. Required if CONFIG_STM32_CAN1 is defined. + +config STM32_CAN2_BAUD + int "CAN2 BAUD" + depends on STM32_CAN2 + default 250000 + ---help--- + CAN2 BAUD rate. Required if CONFIG_STM32_CAN2 is defined. + +config STM32_CAN3_BAUD + int "CAN3 BAUD" + depends on STM32_CAN3 + default 250000 + ---help--- + CAN3 BAUD rate. Required if CONFIG_STM32_CAN3 is defined. + +config STM32_CAN_TSEG1 + int "TSEG1 quanta" + depends on STM32_CAN + default 6 + ---help--- + The number of CAN time quanta in segment 1. Default: 6 + +config STM32_CAN_TSEG2 + int "TSEG2 quanta" + depends on STM32_CAN + default 7 + ---help--- + The number of CAN time quanta in segment 2. Default: 7 + +config STM32_CAN_REGDEBUG + bool "CAN Register level debug" + depends on STM32_CAN && DEBUG_CAN_INFO + ---help--- + Output detailed register-level CAN device debug information. + Requires also CONFIG_DEBUG_CAN_INFO. diff --git a/arch/arm/src/common/stm32/Kconfig.comp b/arch/arm/src/common/stm32/Kconfig.comp new file mode 100644 index 0000000000000..7ab482fe729eb --- /dev/null +++ b/arch/arm/src/common/stm32/Kconfig.comp @@ -0,0 +1,402 @@ +# +# STM32 common COMP options. +# + +# STM32 analog comparator (COMP) configuration options. + +menu "COMP Configuration" + depends on STM32_COMP && STM32_HAVE_IP_COMP_M3M4_V2 + +config STM32_COMP1_OUT + bool "COMP1 GPIO Output" + depends on STM32_COMP1 + default n + ---help--- + Enables COMP1 output. + +config STM32_COMP1_INM + int "COMP1 inverting input assignment" + depends on STM32_COMP1 + range 0 7 + default 0 + ---help--- + Selects COMP1 inverting input pin. + +config STM32_COMP1_INP + int "COMP1 non-inverting input assignment" + depends on STM32_COMP1 + range 0 1 + default 0 + ---help--- + Selects COMP1 non-inverting input pin. + +config STM32_COMP1_POL + int "COMP1 polarity" + depends on STM32_COMP1 + range 0 1 + default 0 + ---help--- + Selects COMP1 output polarity. + +config STM32_COMP1_HYST + int "COMP1 hysteresis" + depends on STM32_STM32G4XXX && STM32_COMP1 + range 0 7 + default 0 + ---help--- + Selects the hysteresis of the COMP1. + +config STM32_COMP1_BLANKSEL + int "COMP1 blanking signal select" + depends on STM32_COMP1 + range 0 7 + default 0 + ---help--- + Selects the blanking signal for comparator COMP1. + +config STM32_COMP1_LOCK + int "COMP1 COMP_CxCSR register lock" + depends on STM32_COMP1 + range 0 1 + default 0 + ---help--- + Locks COMP_CxCSR register. + 0 - Unlock 1 - Lock + +config STM32_COMP2_OUT + bool "COMP2 GPIO Output" + depends on STM32_COMP2 + default n + ---help--- + Enables COMP2 output. + +config STM32_COMP2_INM + int "COMP2 inverting input assignment" + depends on STM32_COMP2 + range 0 7 + default 0 + ---help--- + Selects COMP2 inverting input pin. + +config STM32_COMP2_INP + int "COMP2 non-inverting input assignment" + depends on STM32_COMP2 + range 0 1 + default 0 + ---help--- + Selects COMP2 non-inverting input pin. + +config STM32_COMP2_POL + int "COMP2 polarity" + depends on STM32_COMP2 + range 0 1 + default 0 + ---help--- + Selects COMP2 output polarity. + +config STM32_COMP2_HYST + int "COMP2 hysteresis" + depends on STM32_STM32G4XXX && STM32_COMP2 + range 0 7 + default 0 + ---help--- + Selects the hysteresis of the COMP2. + +config STM32_COMP2_BLANKSEL + int "COMP2 blanking signal select" + depends on STM32_COMP2 + range 0 7 + default 0 + ---help--- + Selects the blanking signal for comparator COMP2. + +config STM32_COMP2_LOCK + int "COMP2 COMP_CxCSR register lock" + depends on STM32_COMP2 + range 0 1 + default 0 + ---help--- + Locks COMP_CxCSR register. + 0 - Unlock 1 - Lock + +config STM32_COMP3_OUT + bool "COMP3 GPIO Output" + depends on STM32_COMP3 + default n + ---help--- + Enables COMP3 output. + +config STM32_COMP3_INM + int "COMP3 inverting input assignment" + depends on STM32_COMP3 + range 0 7 + default 0 + ---help--- + Selects COMP3 inverting input pin. + +config STM32_COMP3_INP + int "COMP3 non-inverting input assignment" + depends on STM32_COMP3 + range 0 1 + default 0 + ---help--- + Selects COMP3 non-inverting input pin. + +config STM32_COMP3_POL + int "COMP3 polarity" + depends on STM32_COMP3 + range 0 1 + default 0 + ---help--- + Selects COMP3 output polarity. + +config STM32_COMP3_HYST + int "COMP3 hysteresis" + depends on STM32_STM32G4XXX && STM32_COMP3 + range 0 7 + default 0 + ---help--- + Selects the hysteresis of the COMP3. + +config STM32_COMP3_BLANKSEL + int "COMP3 blanking signal select" + depends on STM32_COMP3 + range 0 7 + default 0 + ---help--- + Selects the blanking signal for comparator COMP3. + +config STM32_COMP3_LOCK + int "COMP3 COMP_CxCSR register lock" + depends on STM32_COMP3 + range 0 1 + default 0 + ---help--- + Locks COMP_CxCSR register. + 0 - Unlock 1 - Lock + +config STM32_COMP4_OUT + bool "COMP4 GPIO Output" + depends on STM32_COMP4 + default n + ---help--- + Enables COMP4 output. + +config STM32_COMP4_INM + int "COMP4 inverting input assignment" + depends on STM32_COMP4 + range 0 7 + default 0 + ---help--- + Selects COMP4 inverting input pin. + +config STM32_COMP4_INP + int "COMP4 non-inverting input assignment" + depends on STM32_COMP4 + range 0 1 + default 0 + ---help--- + Selects COMP4 non-inverting input pin. + +config STM32_COMP4_POL + int "COMP4 polarity" + depends on STM32_COMP4 + range 0 1 + default 0 + ---help--- + Selects COMP4 output polarity. + +config STM32_COMP4_HYST + int "COMP4 hysteresis" + depends on STM32_STM32G4XXX && STM32_COMP4 + range 0 7 + default 0 + ---help--- + Selects the hysteresis of the COMP4. + +config STM32_COMP4_BLANKSEL + int "COMP4 blanking signal select" + depends on STM32_COMP4 + range 0 7 + default 0 + ---help--- + Selects the blanking signal for comparator COMP4. + +config STM32_COMP4_LOCK + int "COMP4 COMP_CxCSR register lock" + depends on STM32_COMP4 + range 0 1 + default 0 + ---help--- + Locks COMP_CxCSR register. + 0 - Unlock 1 - Lock + +config STM32_COMP5_OUT + bool "COMP5 GPIO Output" + depends on STM32_COMP5 + default n + ---help--- + Enables COMP5 output. + +config STM32_COMP5_INM + int "COMP5 inverting input assignment" + depends on STM32_COMP5 + range 0 7 + default 0 + ---help--- + Selects COMP5 inverting input pin. + +config STM32_COMP5_INP + int "COMP5 non-inverting input assignment" + depends on STM32_COMP5 + range 0 1 + default 0 + ---help--- + Selects COMP5 non-inverting input pin. + +config STM32_COMP5_POL + int "COMP5 polarity" + depends on STM32_COMP5 + range 0 1 + default 0 + ---help--- + Selects COMP5 output polarity. + +config STM32_COMP5_HYST + int "COMP5 hysteresis" + depends on STM32_STM32G4XXX && STM32_COMP5 + range 0 7 + default 0 + ---help--- + Selects the hysteresis of the COMP5. + +config STM32_COMP5_BLANKSEL + int "COMP5 blanking signal select" + depends on STM32_COMP5 + range 0 7 + default 0 + ---help--- + Selects the blanking signal for comparator COMP5. + +config STM32_COMP5_LOCK + int "COMP5 COMP_CxCSR register lock" + depends on STM32_COMP5 + range 0 1 + default 0 + ---help--- + Locks COMP_CxCSR register. + 0 - Unlock 1 - Lock + +config STM32_COMP6_OUT + bool "COMP6 GPIO Output" + depends on STM32_COMP6 + default n + ---help--- + Enables COMP6 output. + +config STM32_COMP6_INM + int "COMP6 inverting input assignment" + depends on STM32_COMP6 + range 0 7 + default 0 + ---help--- + Selects COMP6 inverting input pin. + +config STM32_COMP6_INP + int "COMP6 non-inverting input assignment" + depends on STM32_COMP6 + range 0 1 + default 0 + ---help--- + Selects COMP6 non-inverting input pin. + +config STM32_COMP6_POL + int "COMP6 polarity" + depends on STM32_COMP6 + range 0 1 + default 0 + ---help--- + Selects COMP6 output polarity. + +config STM32_COMP6_HYST + int "COMP6 hysteresis" + depends on STM32_STM32G4XXX && STM32_COMP6 + range 0 7 + default 0 + ---help--- + Selects the hysteresis of the COMP6. + +config STM32_COMP6_BLANKSEL + int "COMP6 blanking signal select" + depends on STM32_COMP6 + range 0 7 + default 0 + ---help--- + Selects the blanking signal for comparator COMP6. + +config STM32_COMP6_LOCK + int "COMP6 COMP_CxCSR register lock" + depends on STM32_COMP6 + range 0 1 + default 0 + ---help--- + Locks COMP_CxCSR register. + 0 - Unlock 1 - Lock + +config STM32_COMP7_OUT + bool "COMP7 GPIO Output" + depends on STM32_COMP7 + default n + ---help--- + Enables COMP7 output. + +config STM32_COMP7_INM + int "COMP7 inverting input assignment" + depends on STM32_COMP7 + range 0 7 + default 0 + ---help--- + Selects COMP7 inverting input pin. + +config STM32_COMP7_INP + int "COMP7 non-inverting input assignment" + depends on STM32_COMP7 + range 0 1 + default 0 + ---help--- + Selects COMP7 non-inverting input pin. + +config STM32_COMP7_POL + int "COMP7 polarity" + depends on STM32_COMP7 + range 0 1 + default 0 + ---help--- + Selects COMP7 output polarity. + +config STM32_COMP7_HYST + int "COMP7 hysteresis" + depends on STM32_STM32G4XXX && STM32_COMP7 + range 0 7 + default 0 + ---help--- + Selects the hysteresis of the COMP7. + +config STM32_COMP7_BLANKSEL + int "COMP7 blanking signal select" + depends on STM32_COMP7 + range 0 7 + default 0 + ---help--- + Selects the blanking signal for comparator COMP7. + +config STM32_COMP7_LOCK + int "COMP7 COMP_CxCSR register lock" + depends on STM32_COMP7 + range 0 1 + default 0 + ---help--- + Locks COMP_CxCSR register. + 0 - Unlock 1 - Lock + +endmenu diff --git a/arch/arm/src/common/stm32/Kconfig.dac b/arch/arm/src/common/stm32/Kconfig.dac new file mode 100644 index 0000000000000..7e0d65af6f8ba --- /dev/null +++ b/arch/arm/src/common/stm32/Kconfig.dac @@ -0,0 +1,366 @@ +# +# STM32 common DAC options. +# + +# STM32 DAC configuration options. + +config STM32_DAC_LL_OPS + bool "DAC low-level operations" + depends on STM32_DAC + default n + ---help--- + Enable low-level DAC ops. + +config STM32_DAC1_DMA + bool "DAC1 DMA" + depends on STM32_COMMON_L4_L5_U5 && STM32_DAC && STM32_DAC1 + ---help--- + If DMA is selected, then a timer and output frequency must also be + provided to support the DMA transfer. The DMA transfer could be + supported by an EXTI trigger, but this feature is not currently + supported by the driver. + +config STM32_DAC1_TIMER + int "DAC1 timer" + depends on STM32_COMMON_L4_L5_U5 && STM32_DAC && STM32_DAC1_DMA + range 2 8 + +config STM32_DAC1_TIMER_FREQUENCY + int "DAC1 timer frequency" + depends on STM32_COMMON_L4_L5_U5 && STM32_DAC && STM32_DAC1_DMA + default 100 + ---help--- + DAC1 output frequency. Default: 100Hz + +config STM32_DAC1_DMA_BUFFER_SIZE + int "DAC1 DMA buffer size" + depends on STM32_COMMON_L4_L5_U5 && STM32_DAC && STM32_DAC1_DMA + default 1 + +config STM32_DAC2_DMA + bool "DAC2 DMA" + depends on STM32_COMMON_L4_L5_U5 && STM32_DAC && STM32_DAC2 + ---help--- + If DMA is selected, then a timer and output frequency must also be + provided to support the DMA transfer. The DMA transfer could be + supported by an EXTI trigger, but this feature is not currently + supported by the driver. + +config STM32_DAC2_TIMER + int "DAC2 timer" + depends on STM32_COMMON_L4_L5_U5 && STM32_DAC && STM32_DAC2_DMA + default 0 + range 2 8 + +config STM32_DAC2_TIMER_FREQUENCY + int "DAC2 timer frequency" + depends on STM32_COMMON_L4_L5_U5 && STM32_DAC && STM32_DAC2_DMA + default 100 + ---help--- + DAC2 output frequency. Default: 100Hz + +config STM32_DAC2_DMA_BUFFER_SIZE + int "DAC2 DMA buffer size" + depends on STM32_COMMON_L4_L5_U5 && STM32_DAC && STM32_DAC2_DMA + default 1 + +menu "DAC Configuration" + depends on STM32_DAC1 || STM32_DAC2 || STM32_DAC3 || STM32_DAC4 + +config STM32_DAC1CH1_MODE + int "DAC1CH1 channel mode" + depends on STM32_DAC1CH1 && STM32_HAVE_IP_DAC_M3M4_V2 + default 0 + range 0 7 + ---help--- + – DAC channel in Normal mode + 0: DAC channel is connected to external pin with Buffer enabled + 1: DAC channel is connected to external pin and to on chip peripherals with buffer enabled + 2: DAC channel2 is connected to external pin with buffer disabled + 3: DAC channel is connected to on chip peripherals with Buffer disabled + - DAC channel in Sample and hold mode + 4: DAC channel is connected to external pin with Buffer enabled + 5: DAC channel is connected to external pin and to on chip peripherals with Buffer enabled + 6: DAC channel is connected to external pin and to on chip peripherals with Buffer disabled + 7: DAC channel is connected to on chip peripherals with Buffer disabled + +config STM32_DAC1CH1_DMA + bool "DAC1CH1 DMA" + depends on STM32_DAC1CH1 + default n + ---help--- + If DMA is selected, then a timer and output frequency must also be + provided to support the DMA transfer. The DMA transfer could be + supported by and EXTI trigger, but this feature is not currently + supported by the driver. + +if STM32_DAC1CH1_DMA + +config STM32_DAC1CH1_DMA_BUFFER_SIZE + int "DAC1CH1 DMA buffer size" + default 256 + +config STM32_DAC1CH1_DMA_EXTERNAL + bool "DAC1CH1 DMA External Trigger" + default n + +if STM32_HRTIM_DAC + +config STM32_DAC1CH1_HRTIM_TRG1 + bool "DAC1CH1 HRTIM Trigger 1" + default n + +config STM32_DAC1CH1_HRTIM_TRG2 + bool "DAC1CH1 HRTIM Trigger 2" + default n + +endif # STM32_HRTIM_DAC + +config STM32_DAC1CH1_TIMER + int "DAC1CH1 timer" + depends on !STM32_DAC1CH1_DMA_EXTERNAL + range 2 8 + +config STM32_DAC1CH1_TIMER_FREQUENCY + int "DAC1CH1 timer frequency" + depends on !STM32_DAC1CH1_DMA_EXTERNAL + default 0 + +endif + +config STM32_DAC1CH2_MODE + int "DAC1CH2 channel mode" + depends on STM32_DAC1CH2 && STM32_HAVE_IP_DAC_M3M4_V2 + default 0 + range 0 7 + ---help--- + – DAC channel in Normal mode + 0: DAC channel is connected to external pin with Buffer enabled + 1: DAC channel is connected to external pin and to on chip peripherals with buffer enabled + 2: DAC channel2 is connected to external pin with buffer disabled + 3: DAC channel is connected to on chip peripherals with Buffer disabled + - DAC channel in Sample and hold mode + 4: DAC channel is connected to external pin with Buffer enabled + 5: DAC channel is connected to external pin and to on chip peripherals with Buffer enabled + 6: DAC channel is connected to external pin and to on chip peripherals with Buffer disabled + 7: DAC channel is connected to on chip peripherals with Buffer disabled + +config STM32_DAC1CH2_DMA + bool "DAC1CH2 DMA" + depends on STM32_DAC1CH2 + default n + ---help--- + If DMA is selected, then a timer and output frequency must also be + provided to support the DMA transfer. The DMA transfer could be + supported by and EXTI trigger, but this feature is not currently + supported by the driver. + +if STM32_DAC1CH2_DMA + +config STM32_DAC1CH2_DMA_BUFFER_SIZE + int "DAC1CH2 DMA buffer size" + default 256 + +config STM32_DAC1CH2_DMA_EXTERNAL + bool "DAC1CH2 DMA External Trigger" + default n + +if STM32_HRTIM_DAC + +config STM32_DAC1CH2_HRTIM_TRG1 + bool "DAC1CH2 HRTIM Trigger 1" + default n + +config STM32_DAC1CH2_HRTIM_TRG2 + bool "DAC1CH2 HRTIM Trigger 2" + default n + +endif # STM32_HRTIM_DAC + +config STM32_DAC1CH2_TIMER + int "DAC1CH2 timer" + depends on !STM32_DAC1CH2_DMA_EXTERNAL + range 2 8 + +config STM32_DAC1CH2_TIMER_FREQUENCY + int "DAC1CH2 timer frequency" + depends on !STM32_DAC1CH2_DMA_EXTERNAL + default 0 + +endif + +config STM32_DAC2CH1_MODE + int "DAC2CH1 channel mode" + depends on STM32_DAC2CH1 && STM32_HAVE_IP_DAC_M3M4_V2 + default 0 + range 0 7 + ---help--- + – DAC channel in Normal mode + 0: DAC channel is connected to external pin with Buffer enabled + 1: DAC channel is connected to external pin and to on chip peripherals with buffer enabled + 2: DAC channel2 is connected to external pin with buffer disabled + 3: DAC channel is connected to on chip peripherals with Buffer disabled + - DAC channel in Sample and hold mode + 4: DAC channel is connected to external pin with Buffer enabled + 5: DAC channel is connected to external pin and to on chip peripherals with Buffer enabled + 6: DAC channel is connected to external pin and to on chip peripherals with Buffer disabled + 7: DAC channel is connected to on chip peripherals with Buffer disabled + +config STM32_DAC2CH1_DMA + bool "DAC2CH1 DMA" + depends on STM32_DAC2CH1 + default n + ---help--- + If DMA is selected, then a timer and output frequency must also be + provided to support the DMA transfer. The DMA transfer could be + supported by and EXTI trigger, but this feature is not currently + supported by the driver. + +if STM32_DAC2CH1_DMA + +config STM32_DAC2CH1_DMA_BUFFER_SIZE + int "DAC2CH1 DMA buffer size" + default 256 + +config STM32_DAC2CH1_DMA_EXTERNAL + bool "DAC2CH1 DMA External Trigger" + default n + +if STM32_HRTIM_DAC + +config STM32_DAC2CH1_HRTIM_TRG3 + bool "DAC2CH1 HRTIM Trigger 3" + default n + +endif # STM32_HRTIM_DAC + +config STM32_DAC2CH1_TIMER + int "DAC2CH1 timer" + depends on !STM32_DAC2CH1_DMA_EXTERNAL + default 0 + range 2 8 + +config STM32_DAC2CH1_TIMER_FREQUENCY + int "DAC2CH1 timer frequency" + depends on !STM32_DAC2CH1_DMA_EXTERNAL + default 0 + +endif + +config STM32_DAC3CH1_MODE + int "DAC3CH1 channel mode" + depends on STM32_DAC3CH1 && STM32_HAVE_IP_DAC_M3M4_V2 + default 0 + range 0 7 + ---help--- + – DAC channel in Normal mode + 0: DAC channel is connected to external pin with Buffer enabled + 1: DAC channel is connected to external pin and to on chip peripherals with buffer enabled + 2: DAC channel is connected to external pin with buffer disabled + 3: DAC channel is connected to on chip peripherals with Buffer disabled + - DAC channel in Sample and hold mode + 4: DAC channel is connected to external pin with Buffer enabled + 5: DAC channel is connected to external pin and to on chip peripherals with Buffer enabled + 6: DAC channel is connected to external pin and to on chip peripherals with Buffer disabled + 7: DAC channel is connected to on chip peripherals with Buffer disabled + +config STM32_DAC3CH1_DMA + bool "DAC3CH1 DMA" + depends on STM32_DAC3CH1 + default n + ---help--- + If DMA is selected, then a timer and output frequency must also be + provided to support the DMA transfer. The DMA transfer could be + supported by an EXTI trigger, but this feature is not currently + supported by the driver. + +if STM32_DAC3CH1_DMA + +config STM32_DAC3CH1_DMA_BUFFER_SIZE + int "DAC3CH1 DMA buffer size" + default 256 + +config STM32_DAC3CH1_DMA_EXTERNAL + bool "DAC3CH1 DMA External Trigger" + default n + +if STM32_HRTIM_DAC + +config STM32_DAC3CH1_HRTIM_TRG3 + bool "DAC3CH1 HRTIM Trigger 3" + default n + +endif # STM32_HRTIM_DAC + +config STM32_DAC3CH1_TIMER + int "DAC3CH1 timer" + depends on !STM32_DAC3CH1_DMA_EXTERNAL + default 0 + range 2 8 + +config STM32_DAC3CH1_TIMER_FREQUENCY + int "DAC3CH1 timer frequency" + depends on !STM32_DAC3CH1_DMA_EXTERNAL + default 0 + +endif + +config STM32_DAC3CH2_MODE + int "DAC3CH2 channel mode" + depends on STM32_DAC3CH2 && STM32_HAVE_IP_DAC_M3M4_V2 + default 0 + range 0 7 + ---help--- + – DAC channel in Normal mode + 0: DAC channel is connected to external pin with Buffer enabled + 1: DAC channel is connected to external pin and to on chip peripherals with buffer enabled + 2: DAC channel2 is connected to external pin with buffer disabled + 3: DAC channel is connected to on chip peripherals with Buffer disabled + - DAC channel in Sample and hold mode + 4: DAC channel is connected to external pin with Buffer enabled + 5: DAC channel is connected to external pin and to on chip peripherals with Buffer enabled + 6: DAC channel is connected to external pin and to on chip peripherals with Buffer disabled + 7: DAC channel is connected to on chip peripherals with Buffer disabled + +config STM32_DAC3CH2_DMA + bool "DAC3CH2 DMA" + depends on STM32_DAC3CH2 + default n + ---help--- + If DMA is selected, then a timer and output frequency must also be + provided to support the DMA transfer. The DMA transfer could be + supported by an EXTI trigger, but this feature is not currently + supported by the driver. + +if STM32_DAC3CH2_DMA + +config STM32_DAC3CH2_DMA_BUFFER_SIZE + int "DAC3CH2 DMA buffer size" + default 256 + +config STM32_DAC3CH2_DMA_EXTERNAL + bool "DAC3CH1 DMA External Trigger" + default n + +if STM32_HRTIM_DAC + +config STM32_DAC3CH2_HRTIM_TRG3 + bool "DAC3CH2 HRTIM Trigger 3" + default n + +endif # STM32_HRTIM_DAC + +config STM32_DAC3CH2_TIMER + int "DAC3CH2 timer" + depends on !STM32_DAC3CH2_DMA_EXTERNAL + default 0 + range 2 8 + +config STM32_DAC3CH2_TIMER_FREQUENCY + int "DAC3CH2 timer frequency" + depends on !STM32_DAC3CH2_DMA_EXTERNAL + default 0 + +endif + +endmenu diff --git a/arch/arm/src/common/stm32/Kconfig.dfsdm b/arch/arm/src/common/stm32/Kconfig.dfsdm new file mode 100644 index 0000000000000..d29507d1707ab --- /dev/null +++ b/arch/arm/src/common/stm32/Kconfig.dfsdm @@ -0,0 +1,45 @@ +# +# STM32 common DFSDM options. +# + +# STM32 digital filter configuration options. + +config STM32_ADC1_DFSDM_L4_CHIP + bool + default y if STM32_STM32L496XX || STM32_STM32L4XR + +config STM32_ADC1_DFSDM_L5_CHIP + bool + default y if STM32_STM32L596XX || STM32_STM32L5XR + +config STM32_ADC1_DFSDM_U5_CHIP + bool + default y if STM32_STM32U596XX || STM32_STM32U5XR + +config STM32_DFSDM1_FLT0 + bool "DFSDM1 Filter 0" + depends on STM32_COMMON_L4_L5_U5 && STM32_DFSDM1 + select STM32_DFSDM + +config STM32_DFSDM1_FLT1 + bool "DFSDM1 Filter 1" + depends on STM32_COMMON_L4_L5_U5 && STM32_DFSDM1 + select STM32_DFSDM + +config STM32_DFSDM1_FLT2 + bool "DFSDM1 Filter 2" + depends on (ARCH_CHIP_STM32L4 && STM32_DFSDM1 && !STM32_STM32L4X3) || (ARCH_CHIP_STM32L5 && STM32_DFSDM1 && !STM32_STM32L5X3) || (ARCH_CHIP_STM32U5 && STM32_DFSDM1 && !STM32_STM32U5X3) + select STM32_DFSDM + +config STM32_DFSDM1_FLT3 + bool "DFSDM1 Filter 3" + depends on (ARCH_CHIP_STM32L4 && STM32_DFSDM1 && !STM32_STM32L4X3) || (ARCH_CHIP_STM32L5 && STM32_DFSDM1 && !STM32_STM32L5X3) || (ARCH_CHIP_STM32U5 && STM32_DFSDM1 && !STM32_STM32U5X3) + select STM32_DFSDM + +config STM32_DFSDM1_DMA + bool "DFSDM1 DMA" + depends on STM32_COMMON_L4_L5_U5 && STM32_DFSDM1 && STM32_DFSDM + ---help--- + If DMA is selected, then the DFSDM may be configured to support + DMA transfer, which is necessary if multiple channels are read + or if very high trigger frequencies are used. diff --git a/arch/arm/src/common/stm32/Kconfig.dma b/arch/arm/src/common/stm32/Kconfig.dma new file mode 100644 index 0000000000000..e4cd1add7ae65 --- /dev/null +++ b/arch/arm/src/common/stm32/Kconfig.dma @@ -0,0 +1,123 @@ +# +# STM32 common DMA options. +# + +# STM32 DMA configuration options. + +# DMA per-instance capability flags +# (hidden; driven by default y if / peripheral selects, never by chip selectors) + +config STM32_DMA1_HAVE_CHAN8 + bool + default y if STM32_STM32G47XX + +config STM32_DMA2_HAVE_CHAN678 + bool + default y if STM32_STM32G47XX + +config STM32_DMACAPABLE + bool "Workaround non-DMA capable memory" + depends on (STM32_COMMON_LEGACY || STM32_COMMON_F7_H7) && ARCH_DMA + default STM32_STM32F4XXX && !STM32_CCMEXCLUDE if STM32_COMMON_LEGACY && ARCH_DMA + ---help--- + This option enables the DMA interface stm32_dmacapable that can be + used to check if it is possible to do DMA from the selected address. + Drivers then may use this information to determine if they should + attempt the DMA or fall back to a different transfer method. + +if STM32_DMA2D + +config STM32_DMA2D_NLAYERS + int "Number DMA2D overlays" + default 1 + range 1 256 + ---help--- + Number of supported DMA2D layer. + +config STM32_DMA2D_LAYER_SHARED + bool "Overlays shared memory region" + ---help--- + Several overlays can share the same memory region. + Setup a whole memory area (usually multiple size of the visible screen) + allows image preprocessing before they become visible by blit operation. + +config STM32_DMA2D_LAYER_PPLINE + int "Pixel per line" + default 1 + range 1 65535 + ---help--- + If you are using the DMA2D, then you must provide the pixel per line or + width of the overlay. + +config STM32_DMA2D_FB_BASE + hex "Framebuffer memory start address" + default 0 + ---help--- + If you are using the DMA2D, then you must provide the address + of the start of the DMA2D overlays framebuffer. This address will typically + be in the SRAM or SDRAM memory region of the FSMC/FMC. + +config STM32_DMA2D_FB_SIZE + int "Framebuffer memory size (bytes)" + default 0 + ---help--- + Must be the whole size of all DMA2D overlays. + +config STM32_DMA2D_L8 + bool "8 bpp L8 (8-bit CLUT)" + depends on STM32_FB_CMAP && STM32_LTDC_L1_L8 + default y + +config STM32_DMA2D_AL44 + bool "8 bpp AL44 (4-bit alpha + 4-bit CLUT)" + depends on STM32_FB_CMAP && STM32_LTDC_L1_AL44 + default y + +config STM32_DMA2D_AL88 + bool "16 bpp AL88 (8-bit alpha + 8-bit CLUT)" + depends on STM32_FB_CMAP && STM32_LTDC_L1_AL88 + default y + +config STM32_DMA2D_RGB565 + bool "16 bpp RGB 565" + depends on STM32_LTDC_L1_RGB565 + default y + +config STM32_DMA2D_ARGB4444 + bool "16 bpp ARGB 4444" + depends on STM32_LTDC_L1_ARGB4444 + default y + +config STM32_DMA2D_ARGB1555 + bool "16 bpp ARGB 1555" + depends on STM32_LTDC_L1_ARGB15555 + default y + +config STM32_DMA2D_RGB888 + bool "24 bpp RGB 888" + depends on STM32_LTDC_L1_RGB888 + default y + +config STM32_DMA2D_ARGB8888 + bool "32 bpp ARGB 8888" + depends on STM32_LTDC_L1_ARGB8888 + default y + +config STM32_DMA2D_REGDEBUG + bool "DMA2D Register level debug" + depends on DEBUG_INFO && DEBUG_LCD + ---help--- + Output detailed register-level DMA2D device debug information. + +endif # STM32_DMA2D + +config STM32_DMACAPABLE_ASSUME_CACHE_ALIGNED + bool "Do not disqualify DMA capability based on cache alignment" + depends on STM32_COMMON_F7_H7 && STM32_DMACAPABLE && ARMV7M_DCACHE && !ARMV7M_DCACHE_WRITETHROUGH + ---help--- + This option configures the stm32_dmacapable to not disqualify + DMA operations on memory that is not dcache aligned based solely + on the starting address and byte count. + + Use this when ALL buffer extents are known to be aligned, but the + the count does not use the complete buffer. diff --git a/arch/arm/src/common/stm32/Kconfig.dts b/arch/arm/src/common/stm32/Kconfig.dts new file mode 100644 index 0000000000000..7ed7e0622c8a4 --- /dev/null +++ b/arch/arm/src/common/stm32/Kconfig.dts @@ -0,0 +1,101 @@ +# +# STM32 common DTS options. +# + +# STM32 Digital Temperature Sensor (DTS) configuration options. + +config STM32_DTS_REFCLK_LSE + bool "Use LSE (32.768 kHz crystal) as DTS reference clock" + default n + ---help--- + Select the low‑speed external (LSE) oscillator as the reference clock + for the DTS. When enabled, DTS_CFGR1.REFCLK_SEL=1 and the driver will + measure FM(T) pulses over N LSE cycles. + + If disabled, the DTS will use the APB‑bus clock (PCLK) as the reference + (REFCLK_SEL=0) and you must supply a valid HSREF_CLK_DIV to keep the + calibration prescaler ≤ 1 MHz. + +config STM32_DTS_SMP_TIME + int "DTS sampling time (TS1_SMP_TIME[3:0])" + default 1 + range 1 15 + ---help--- + Number of reference‑clock cycles (PCLK or LSE) counted per + DTS measurement. Valid range 1 (1 cycle) through 15 (15 cycles). + +config STM32_DTS_TRIGGER + int "DTS hardware trigger source (TS1_INTRIG_SEL[3:0])" + default 0 + ---help--- + If non‑zero, DTS will start measurements on the rising edge of + the selected hardware line. Values match RM0481 Table 275: + 0=Software Trigger, 1=LPTIM1_CH1,  + 2=LPTIM2_CH1, 3=LPTIM3_CH1, 4=EXTI13, 5-15 are reserved. + +config STM32_DTS_LOW_THRESHOLD + int "DTS low‑threshold (°C)" + default 0 + ---help--- + The temperature (in whole °C) below which the DTS window comparator will + assert the low‑threshold flag (TS1_ITLF). To disable, set equal to 0. + +config STM32_DTS_HIGH_THRESHOLD + int "DTS high‑threshold (°C)" + default 100 + ---help--- + The temperature (in whole °C) above which the DTS window comparator will + assert the high‑threshold flag (TS1_ITHF). Must be >= LOW_THRESHOLD. + +config STM32_DTS_ITEN_ITEF + bool "Enable DTS end‑of‑measurement interrupt (TS1_ITEF)" + default y + ---help--- + Enable the synchronous “end of measurement” interrupt for the + digital temperature sensor. When set, the driver will attach + and unmask TS1_ITEF and will call your ISR on every fresh sample. + +config STM32_DTS_ITEN_ITLF + bool "Enable DTS low‑threshold interrupt (TS1_ITLF)" + default n + ---help--- + Enable the synchronous “low threshold crossed” interrupt for the + digital temperature sensor. When set, the driver will unmask + TS1_ITLF so you can get notified whenever the measured value + drops below your programmed low‑threshold. + +config STM32_DTS_ITEN_ITHF + bool "Enable DTS high‑threshold interrupt (TS1_ITHF)" + default n + ---help--- + Enable the synchronous “high threshold crossed” interrupt for the + digital temperature sensor. When set, the driver will unmask + TS1_ITHF so you can get notified whenever the measured value + exceeds your programmed high‑threshold. + +config STM32_DTS_AITEN_AITEF + bool "Enable DTS asynchronous end‑of‑measurement interrupt (TS1_AITEF)" + depends on STM32_DTS_REFCLK_LSE + default n + ---help--- + Enable the asynchronous end‑of‑measurement interrupt. This will + set TS1_AITEEN in DTS_ITENR and cause an _asynchronous_ wakeup + event when a conversion completes (in Stop/Sleep modes). + +config STM32_DTS_AITEN_AITLF + bool "Enable DTS asynchronous low‑threshold interrupt (TS1_AITLF)" + depends on STM32_DTS_REFCLK_LSE + default n + ---help--- + Enable the asynchronous low‑threshold comparator interrupt. This + will set TS1_AITLEN in DTS_ITENR and generate a wakeup event + when the measurement drops below your low threshold. + +config STM32_DTS_AITEN_AITHF + bool "Enable DTS asynchronous high‑threshold interrupt (TS1_AITHF)" + depends on STM32_DTS_REFCLK_LSE + default n + ---help--- + Enable the asynchronous high‑threshold comparator interrupt. This + will set TS1_AITHEN in DTS_ITENR and generate a wakeup event + when the measurement exceeds your high threshold. diff --git a/arch/arm/src/common/stm32/Kconfig.eth b/arch/arm/src/common/stm32/Kconfig.eth new file mode 100644 index 0000000000000..63344d7baff77 --- /dev/null +++ b/arch/arm/src/common/stm32/Kconfig.eth @@ -0,0 +1,293 @@ +# +# STM32 common ETH options. +# + +# PHY per-instance capability flags +# (hidden; driven by default y if / peripheral selects, never by chip selectors) + +config STM32_PHY_HAVE_POLLED + bool + +if STM32_ETHMAC + +config STM32_PHYADDR + int "PHY address" + default 1 if STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7 + default 0 + ---help--- + The 5-bit address of the PHY on the board. Default: 1 + +config STM32_PHYINIT + bool "Board-specific PHY Initialization" + ---help--- + Some boards require specialized initialization of the PHY before it can be used. + This may include such things as configuring GPIOs, resetting the PHY, etc. If + STM32_PHYINIT is defined in the configuration then the board specific logic must + provide stm32_phyinitialize(); The STM32 Ethernet driver will call this function + one time before it first uses the PHY. + +config STM32_MII + bool "Use MII interface" + ---help--- + Support Ethernet MII interface. + +config STM32_AUTONEG + bool "Use autonegotiation" + default y + ---help--- + Use PHY autonegotiation to determine speed and mode + +if !STM32_AUTONEG + +config STM32_ETHFD + bool "Full duplex" + ---help--- + If STM32_AUTONEG is not defined, then this may be defined to select full duplex + mode. Default: half-duplex + +config STM32_ETH100MBPS + bool "100 Mbps" + ---help--- + If STM32_AUTONEG is not defined, then this may be defined to select 100 MBps + speed. Default: 10 Mbps + +endif # !STM32_AUTONEG + +if STM32_AUTONEG + +config STM32_PHYSR + int "PHY Status Register Address (decimal)" + ---help--- + This must be provided if STM32_AUTONEG is defined. The PHY status register + address may diff from PHY to PHY. This configuration sets the address of + the PHY status register. + +config STM32_PHYSR_ALTCONFIG + bool "PHY Status Alternate Bit Layout" + ---help--- + Different PHYs present speed and mode information in different ways. Some + will present separate information for speed and mode (this is the default). + Those PHYs, for example, may provide a 10/100 Mbps indication and a separate + full/half duplex indication. This options selects an alternative representation + where speed and mode information are combined. This might mean, for example, + separate bits for 10HD, 100HD, 10FD and 100FD. + +if !STM32_PHYSR_ALTCONFIG + +config STM32_PHYSR_SPEED + hex "PHY Speed Mask" + ---help--- + This must be provided if STM32_AUTONEG is defined. This provides bit mask + for isolating the 10 or 100MBps speed indication. + +config STM32_PHYSR_100MBPS + hex "PHY 100Mbps Speed Value" + ---help--- + This must be provided if STM32_AUTONEG is defined. This provides the value + of the speed bit(s) indicating 100MBps speed. + +config STM32_PHYSR_MODE + hex "PHY Mode Mask" + ---help--- + This must be provided if STM32_AUTONEG is defined. This provide bit mask + for isolating the full or half duplex mode bits. + +config STM32_PHYSR_FULLDUPLEX + hex "PHY Full Duplex Mode Value" + ---help--- + This must be provided if STM32_AUTONEG is defined. This provides the + value of the mode bits indicating full duplex mode. + +endif # !STM32_PHYSR_ALTCONFIG + +if STM32_PHYSR_ALTCONFIG + +config STM32_PHYSR_ALTMODE + hex "PHY Mode Mask" + ---help--- + This must be provided if STM32_AUTONEG is defined. This provide bit mask + for isolating the speed and full/half duplex mode bits. + +config STM32_PHYSR_10HD + hex "10MBase-T Half Duplex Value" + ---help--- + This must be provided if STM32_AUTONEG is defined. This is the value + under the bit mask that represents the 10Mbps, half duplex setting. + +config STM32_PHYSR_100HD + hex "100Base-T Half Duplex Value" + ---help--- + This must be provided if STM32_AUTONEG is defined. This is the value + under the bit mask that represents the 100Mbps, half duplex setting. + +config STM32_PHYSR_10FD + hex "10Base-T Full Duplex Value" + ---help--- + This must be provided if STM32_AUTONEG is defined. This is the value + under the bit mask that represents the 10Mbps, full duplex setting. + +config STM32_PHYSR_100FD + hex "100Base-T Full Duplex Value" + ---help--- + This must be provided if STM32_AUTONEG is defined. This is the value + under the bit mask that represents the 100Mbps, full duplex setting. + +endif # STM32_PHYSR_ALTCONFIG + +endif # STM32_AUTONEG + +config STM32_ETH_PTP + bool "Precision Time Protocol (PTP)" + ---help--- + Enables Precision Time Protocol (PTP) hardware timer. + +config STM32_ETH_ENHANCEDDESC + bool "Enable enhanced RX/TX descriptors" + depends on STM32_COMMON_LEGACY + default n + ---help--- + Enables double-length DMA descriptors that have space for packet + timestamps and checksum offloading. + +config STM32_ETH_PTP_GPIO + bool "PTP pulse-per-second output signal" + depends on STM32_COMMON_LEGACY && STM32_ETH_PTP + default n + ---help--- + Enables pulse-per-second output on GPIO pin. + +config STM32_ETH_PTP_RTC_HIRES + bool "Use PTP timer as system high-resolution RTC" + depends on STM32_COMMON_LEGACY && STM32_ETH_PTP + default n + ---help--- + Uses the Ethernet peripheral PTP timer as the CONFIG_RTC_HIRES source. + This provides high resolution timestamps to clock_gettime(). + Note that PTP timer is disabled when Ethernet interface is down or + being reset. During this time g_rtc_enabled is set to false and system + uses the lower resolution system tick counter. + +config STM32_ETH_TIMESTAMP_RX + bool "Hardware timestamping of received packets" + depends on STM32_COMMON_LEGACY && STM32_ETH_PTP && NET_TIMESTAMP && STM32_ETH_ENHANCEDDESC + select ARCH_HAVE_NETDEV_TIMESTAMP + default n + ---help--- + Timestamp all received Ethernet packets. + Timestamp is available to application through SO_TIMESTAMP socket option. + +config STM32_RMII + bool + default !STM32_MII + +config STM32_ETHMAC_REGDEBUG + bool "Register-Level Debug" + depends on DEBUG_NET_INFO + ---help--- + Enable very low-level register access debug. Depends on CONFIG_DEBUG_FEATURES. + +endif # STM32_ETHMAC + +choice + prompt "MII clock configuration" + depends on STM32_MII + default STM32_MII_MCO if STM32_STM32F10XX + default STM32_MII_MCO1 if STM32_STM32F20XX || STM32_STM32F4XXX + default STM32_MII_EXTCLK + +config STM32_MII_MCO + bool "Use MC0 as MII clock" + depends on STM32_STM32F10XX + ---help--- + Use MCO to clock the MII interface. Default: Use MC0 + +config STM32_MII_MCO1 + bool "Use MC01 as MII clock" + depends on (STM32_STM32F20XX || STM32_STM32F4XXX || STM32_COMMON_F7_H7_H5) + ---help--- + Use MCO1 to clock the MII interface. Default: Use MC01 + +config STM32_MII_MCO2 + bool "Use MC02 as MII clock" + depends on (STM32_STM32F20XX || STM32_STM32F4XXX || STM32_COMMON_F7_H7_H5) + ---help--- + Use MCO2 to clock the MII interface. Default: Use MC01 + +config STM32_MII_EXTCLK + bool "External MII clock" + ---help--- + Clocking is provided by external logic. Don't use MCO for MII + clock. Default: Use MC0[1] + +endchoice + +choice + prompt "RMII clock configuration" + depends on STM32_RMII + default STM32_RMII_MCO if STM32_STM32F10XX + default STM32_RMII_MCO1 if STM32_STM32F20XX || STM32_STM32F4XXX + default STM32_RMII_EXTCLK + +config STM32_RMII_MCO + bool "Use MC0 as RMII clock" + depends on STM32_STM32F10XX + ---help--- + Use MCO to clock the RMII interface. Default: Use MC0 + +config STM32_RMII_MCO1 + bool "Use MC01 as RMII clock" + depends on (STM32_STM32F20XX || STM32_STM32F4XXX || STM32_COMMON_F7_H7_H5) + ---help--- + Use MCO1 to clock the RMII interface. Default: Use MC01 + +config STM32_RMII_MCO2 + bool "Use MC02 as RMII clock" + depends on (STM32_STM32F20XX || STM32_STM32F4XXX || STM32_COMMON_F7_H7_H5) + ---help--- + Use MCO2 to clock the RMII interface. Default: Use MC01 + +config STM32_RMII_EXTCLK + bool "External RMII clock" + ---help--- + Clocking is provided by external logic. Don't use MCO for RMII + clock. Default: Use MC0[1] + +endchoice + +config STM32_PHY_POLLING + bool "Support network monitoring by polling the PHY" + depends on (STM32_COMMON_F7_H7_H5) && STM32_ETHMAC && STM32_PHY_HAVE_POLLED + select ARCH_PHY_POLLED + ---help--- + Some boards may not have an interrupt connected to the PHY. + This option allows the network monitor to be used by polling the + the PHY for status. + +config STM32_ETH_HWCHECKSUM + bool "Enable ethernet hardware checksum" + depends on ARCH_CHIP_STM32H5 && STM32_ETHMAC + ---help--- + Enable the IPv4/IPv6 header and TCP/UDP/ICMP payload checksum offload + engine in the Ethernet MAC. + When enabled, hardware generates checksums for TX and checks RX frames. + Be sure to disable software checksums (NET_TCP_CHECKSUMS, NET_UDP_CHECKSUMS, + NET_ICMP_CHECKSUMS, NET_IPV4_CHECKSUMS, NET_IPV6_CHECKSUMS) to avoid + redundant verification in the network stack. + +config STM32_NO_PHY + bool "MAC has no PHY" + depends on STM32_COMMON_H7_H5 && STM32_ETHMAC + +config STM32_ETH_NRXDESC + int "Number of RX descriptors" + depends on STM32_COMMON_H7_H5 && STM32_ETHMAC + default 8 + ---help--- + Number of RX DMA descriptors to use. + +config STM32_ETH_NTXDESC + int "Number of TX descriptors" + depends on STM32_COMMON_H7_H5 && STM32_ETHMAC + default 4 + ---help--- + Number of TX DMA descriptors to use. diff --git a/arch/arm/src/common/stm32/Kconfig.fdcan b/arch/arm/src/common/stm32/Kconfig.fdcan new file mode 100644 index 0000000000000..9118b4a3800f9 --- /dev/null +++ b/arch/arm/src/common/stm32/Kconfig.fdcan @@ -0,0 +1,520 @@ +# +# STM32 common FDCAN options. +# + +# STM32 FDCAN configuration options. + +menu "FDCAN Driver Configuration" + depends on STM32_HAVE_FDCAN_H7 && (STM32_FDCAN1 || STM32_FDCAN2 || STM32_FDCAN3) + +menu "FDCAN1 Configuration" + depends on STM32_FDCAN1 + +config FDCAN1_BITRATE + int "FDCAN1 CAN bitrate" + depends on !NET_CAN_CANFD + default 100000 + +config FDCAN1_ARBI_BITRATE + int "FDCAN1 CAN FD arbitration phase bitrate" + depends on NET_CAN_CANFD + default 100000 + +config FDCAN1_DATA_BITRATE + int "FDCAN1 CAN FD data phase bitrate" + depends on NET_CAN_CANFD + default 4000000 + +endmenu # STM32_FDCAN1 + +menu "FDCAN2 Configuration" + depends on STM32_FDCAN2 + +config FDCAN2_BITRATE + int "FDCAN2 CAN bitrate" + depends on !NET_CAN_CANFD + default 100000 + +config FDCAN2_ARBI_BITRATE + int "FDCAN2 CAN FD arbitration phase bitrate" + depends on NET_CAN_CANFD + default 100000 + +config FDCAN2_DATA_BITRATE + int "FDCAN2 CAN FD data phase bitrate" + depends on NET_CAN_CANFD + default 4000000 + +endmenu # STM32_FDCAN2 + +menu "FDCAN3 Configuration" + depends on STM32_FDCAN3 + +config FDCAN3_BITRATE + int "FDCAN3 CAN bitrate" + depends on !NET_CAN_CANFD + default 1000000 + +config FDCAN3_ARBI_BITRATE + int "FDCAN3 CAN FD arbitration phase bitrate" + depends on NET_CAN_CANFD + default 1000000 + +config FDCAN3_DATA_BITRATE + int "FDCAN3 CAN FD data phase bitrate" + depends on NET_CAN_CANFD + default 4000000 + +endmenu # STM32_FDCAN3 + +endmenu # FDCAN Driver + +choice + prompt "FDCAN character driver or SocketCAN support" + depends on STM32_FDCAN + default STM32_FDCAN_CHARDRIVER + +config STM32_FDCAN_CHARDRIVER + bool "STM32 FDCAN character driver support" + select ARCH_HAVE_CAN_ERRORS + select CAN + +config STM32_FDCAN_SOCKET + bool "STM32 FDCAN SocketCAN support" + select NET_CAN_HAVE_ERRORS + select NET_CAN_HAVE_CANFD + +endchoice # FDCAN character driver or SocketCAN support + +if STM32_FDCAN1 + +choice + prompt "FDCAN1 frame format" + default STM32_FDCAN1_ISO11898_1 + +config STM32_FDCAN1_ISO11898_1 + bool "ISO11898-1" + ---help--- + Enable ISO11898-1 frame format + +config STM32_FDCAN1_NONISO_FORMAT + bool "Non ISO" + ---help--- + Enable Non ISO, Bosch CAN FD Specification V1.0 + +endchoice # FDCAN1 frame format + +choice + prompt "FDCAN1 mode" + default STM32_FDCAN1_CLASSIC + +config STM32_FDCAN1_CLASSIC + bool "Classic CAN" + ---help--- + Enable Classic CAN mode + +config STM32_FDCAN1_FD + bool "CAN FD" + depends on CAN_FD || NET_CAN_CANFD + ---help--- + Enable CAN FD mode + +config STM32_FDCAN1_FD_BRS + bool "CAN FD with fast bit rate switching" + depends on CAN_FD || NET_CAN_CANFD + ---help--- + Enable CAN FD mode with fast bit rate switching mode. + +endchoice # FDCAN1 mode + +endif # STM32_FDCAN1 + +if STM32_FDCAN2 + +choice + prompt "FDCAN2 frame format" + default STM32_FDCAN2_ISO11898_1 + +config STM32_FDCAN2_ISO11898_1 + bool "ISO11898-1" + ---help--- + Enable ISO11898-1 frame format + +config STM32_FDCAN2_NONISO_FORMAT + bool "Non ISO" + ---help--- + Enable Non ISO, Bosch CAN FD Specification V1.0 + +endchoice # FDCAN2 frame format + +choice + prompt "FDCAN2 mode" + default STM32_FDCAN2_CLASSIC + +config STM32_FDCAN2_CLASSIC + bool "Classic CAN" + ---help--- + Enable Classic CAN mode + +config STM32_FDCAN2_FD + bool "CAN FD" + depends on CAN_FD || NET_CAN_CANFD + ---help--- + Enable CAN FD mode + +config STM32_FDCAN2_FD_BRS + bool "CAN FD with fast bit rate switching" + depends on CAN_FD || NET_CAN_CANFD + ---help--- + Enable CAN FD mode with fast bit rate switching mode. + +endchoice # FDCAN2 mode + +endif # STM32_FDCAN2 + +config STM32_FDCAN_REGDEBUG + bool "FDCAN register-level debug" + depends on STM32_FDCAN && (DEBUG_CAN_INFO || DEBUG_NET_INFO) + ---help--- + Output detailed register-level CAN device debug information. + Requires also CONFIG_DEBUG_CAN_INFO. + +config STM32_FDCAN_QUEUE_MODE + bool "FDCAN QUEUE mode (vs FIFO mode)" + depends on STM32_FDCAN + +config STM32_FDCAN_LOOPBACK + bool "Enable FDCAN loopback mode" + depends on ARCH_CHIP_STM32H7 && STM32_FDCAN + default n + ---help--- + Enable the FDCAN local loopback mode for testing purposes. + Requires a further choice of internal or external loopback mode. + +choice + prompt "FDCAN Loopback Mode" + depends on STM32_FDCAN_LOOPBACK + default STM32_FDCAN_LOOPBACK_INTERNAL + +config STM32_FDCAN_LOOPBACK_INTERNAL + bool "Internal loopback mode" + ---help--- + Enable internal loopback mode, where both Tx and Rx are + disconnected from the CAN bus. This can be used for a "Hot Selftest", + meaning the FDCAN can be used without affecting a running CAN bus. + + All transmitted frames are treated as received frames and processed + accordingly. + +config STM32_FDCAN_LOOPBACK_EXTERNAL + bool "External loopback mode" + ---help--- + Enable external loopback mode, where the Rx pin is disconnected from + the CAN bus but the Tx pin remains connected. + + All transmitted frames are treated as received frames and processed + accordingly. + +endchoice # FDCAN Loopback Mode + +choice + prompt "FDCAN WorkQueue Selection" + depends on ARCH_CHIP_STM32H7 && STM32_FDCAN + default STM32_FDCAN_LPWORK + +config STM32_FDCAN_LPWORK + bool "Use LP work queue" + ---help--- + Use the low-priority (LP) work queue for reception and transmission + of new frames and for processing of transmission timeouts. + +config STM32_FDCAN_HPWORK + bool "Use HP work queue" + ---help--- + Use the high-priority (HP) work queue for reception and transmission + of new frames and for processing of transmission timeouts. + +endchoice # FDCAN WorkQueue Selection + +if STM32_FDCAN1 + +config STM32_FDCAN1_LOOPBACK + bool "Enable FDCAN1 loopback mode" + ---help--- + Enable the FDCAN1 local loopback mode for testing purposes. + +config STM32_FDCAN1_BITRATE + int "FDCAN1 bitrate" + default 500000 + range 0 1000000 + ---help--- + FDCAN1 bitrate in bits per second. Required if STM32_FDCAN1 is defined. + +config STM32_FDCAN1_AUTO_BIT_TIMING + bool "FDCAN1 automatic bit timing" + depends on ARCH_CHIP_STM32H5 + default y + ---help--- + Automatically determine FDCAN1 bit timing (nominal and data) + based on bitrate. + +if !STM32_FDCAN1_AUTO_BIT_TIMING + +comment "FDCAN1 nominal bit timing" + +config STM32_FDCAN1_NTSEG1 + int "FDCAN1 NTSEG1 (PropSeg + PhaseSeg1)" + default 6 + range 1 256 + ---help--- + The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). + +config STM32_FDCAN1_NTSEG2 + int "FDCAN1 NTSEG2 (PhaseSeg2)" + default 7 + range 1 128 + ---help--- + The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). + +config STM32_FDCAN1_NSJW + int "FDCAN1 synchronization jump width" + default 1 + range 1 128 + ---help--- + The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). + +endif # !STM32_FDCAN1_AUTO_BIT_TIMING + +config STM32_FDCAN1_DBITRATE + int "FDCAN1 data bitrate" + depends on CAN_FD && STM32_FDCAN1_FD_BRS + default 2000000 + ---help--- + FDCAN1 bitrate in bits per second. Required if operating in FD mode with bit rate switching (BRS). + +if CAN_FD && STM32_FDCAN1_FD_BRS && !STM32_FDCAN1_AUTO_BIT_TIMING + +comment "FDCAN1 data bit timing" + +config STM32_FDCAN1_DTSEG1 + int "FDCAN1 DTSEG1 (PropSeg + PhaseSeg1 of data phase)" + default 4 + range 1 31 + ---help--- + The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). + +config STM32_FDCAN1_DTSEG2 + int "FDCAN1 DTSEG2 (PhaseSeg2 of data phase)" + default 4 + range 1 15 + ---help--- + The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). + +config STM32_FDCAN1_DSJW + int "FDCAN1 fast synchronization jump width" + default 2 + range 1 15 + ---help--- + The duration of a synchronization jump is Tcan_clk x DSJW. + +endif # CAN_FD && STM32_FDCAN1_FD_BRS && !STM32_FDCAN1_AUTO_BIT_TIMING + +endif # STM32_FDCAN1 + +if STM32_FDCAN2 + +config STM32_FDCAN2_LOOPBACK + bool "Enable FDCAN2 loopback mode" + ---help--- + Enable the FDCAN2 local loopback mode for testing purposes. + +config STM32_FDCAN2_BITRATE + int "FDCAN2 bitrate" + default 500000 + range 0 1000000 + ---help--- + FDCAN2 bitrate in bits per second. Required if STM32_FDCAN2 is defined. + +config STM32_FDCAN2_AUTO_BIT_TIMING + bool "FDCAN2 automatic bit timing" + depends on ARCH_CHIP_STM32H5 + default y + ---help--- + Automatically determine FDCAN2 bit timing (nominal and data) + based on bitrate. + +if !STM32_FDCAN2_AUTO_BIT_TIMING + +comment "FDCAN2 nominal bit timing" + +config STM32_FDCAN2_NTSEG1 + int "FDCAN2 NTSEG1 (PropSeg + PhaseSeg1)" + default 6 + range 1 256 + ---help--- + The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). + +config STM32_FDCAN2_NTSEG2 + int "FDCAN2 NTSEG2 (PhaseSeg2)" + default 7 + range 1 128 + ---help--- + The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). + +config STM32_FDCAN2_NSJW + int "FDCAN2 synchronization jump width" + default 1 + range 1 128 + ---help--- + The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). + +endif # !STM32_FDCAN2_AUTO_BIT_TIMING + +config STM32_FDCAN2_DBITRATE + int "FDCAN2 data bitrate" + depends on CAN_FD && STM32_FDCAN2_FD_BRS + default 2000000 + ---help--- + FDCAN2 bitrate in bits per second. Required if operating in FD mode with bit rate switching (BRS). + +if CAN_FD && STM32_FDCAN2_FD_BRS && !STM32_FDCAN2_AUTO_BIT_TIMING + +comment "FDCAN2 data bit timing" + +config STM32_FDCAN2_DTSEG1 + int "FDCAN2 DTSEG1 (PropSeg + PhaseSeg1 of data phase)" + default 4 + range 1 31 + ---help--- + The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). + +config STM32_FDCAN2_DTSEG2 + int "FDCAN2 DTSEG2 (PhaseSeg2 of data phase)" + default 4 + range 1 15 + ---help--- + The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). + +config STM32_FDCAN2_DSJW + int "FDCAN2 fast synchronization jump width" + default 2 + range 1 15 + ---help--- + The duration of a synchronization jump is Tcan_clk x DSJW. + +endif # CAN_FD && STM32_FDCAN2_FD_BRS && !STM32_FDCAN2_AUTO_BIT_TIMING + +endif # STM32_FDCAN2 + +if STM32_FDCAN3 + +choice + prompt "FDCAN3 frame format" + default STM32_FDCAN3_ISO11898_1 + +config STM32_FDCAN3_ISO11898_1 + bool "ISO11898-1" + ---help--- + Enable ISO11898-1 frame format + +config STM32_FDCAN3_NONISO_FORMAT + bool "Non ISO" + ---help--- + Enable Non ISO, Bosch CAN FD Specification V1.0 + +endchoice # FDCAN3 frame format + +choice + prompt "FDCAN3 mode" + default STM32_FDCAN3_CLASSIC + +config STM32_FDCAN3_CLASSIC + bool "Classic CAN" + ---help--- + Enable Classic CAN mode + +config STM32_FDCAN3_FD + bool "CAN FD" + depends on CAN_FD || NET_CAN_CANFD + ---help--- + Enable CAN FD mode + +config STM32_FDCAN3_FD_BRS + bool "CAN FD with fast bit rate switching" + depends on CAN_FD || NET_CAN_CANFD + ---help--- + Enable CAN FD mode with fast bit rate switching mode. + +endchoice # FDCAN3 mode + +config STM32_FDCAN3_LOOPBACK + bool "Enable FDCAN3 loopback mode" + default n + ---help--- + Enable the FDCAN3 local loopback mode for testing purposes. + +config STM32_FDCAN3_BITRATE + int "FDCAN3 bitrate" + default 500000 + range 0 1000000 + ---help--- + FDCAN3 bitrate in bits per second. Required if STM32_FDCAN3 is defined. + +comment "FDCAN3 nominal bit timing" + +config STM32_FDCAN3_NTSEG1 + int "FDCAN3 NTSEG1 (PropSeg + PhaseSeg1)" + default 6 + range 1 256 if STM32_STM32G4XXX + ---help--- + The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). + +config STM32_FDCAN3_NTSEG2 + int "FDCAN3 NTSEG2 (PhaseSeg2)" + default 7 + range 1 128 if STM32_STM32G4XXX + ---help--- + The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). + +config STM32_FDCAN3_NSJW + int "FDCAN3 synchronization jump width" + default 1 + range 1 128 if STM32_STM32G4XXX + ---help--- + The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). + +config STM32_FDCAN3_DBITRATE + int "FDCAN3 data bitrate" + depends on CAN_FD && STM32_FDCAN3_FD_BRS + default 2000000 + ---help--- + FDCAN3 bitrate in bits per second. Required if operating in FD mode with bit rate switching (BRS). + +if CAN_FD && STM32_FDCAN3_FD_BRS + +comment "FDCAN3 data bit timing" + +config STM32_FDCAN3_DTSEG1 + int "FDCAN3 DTSEG1 (PropSeg + PhaseSeg1 of data phase)" + default 4 + range 1 31 if STM32_STM32G4XXX + ---help--- + The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). + +config STM32_FDCAN3_DTSEG2 + int "FDCAN3 DTSEG2 (PhaseSeg2 of data phase)" + default 4 + range 1 15 if STM32_STM32G4XXX + ---help--- + The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). + +config STM32_FDCAN3_DSJW + int "FDCAN3 fast synchronization jump width" + default 2 + range 1 15 if STM32_STM32G4XXX + ---help--- + The duration of a synchronization jump is Tcan_clk x DSJW. + +endif # CAN_FD && STM32_FDCAN3_FD_BRS + +endif # STM32_FDCAN3 diff --git a/arch/arm/src/common/stm32/Kconfig.flash b/arch/arm/src/common/stm32/Kconfig.flash new file mode 100644 index 0000000000000..8d18c20cf4651 --- /dev/null +++ b/arch/arm/src/common/stm32/Kconfig.flash @@ -0,0 +1,164 @@ +# +# STM32 common FLASH options. +# + +# STM32 flash configuration options. + +# Common STM32 flash size designator options. + +config STM32_FLASH_CONFIG_DEFAULT + bool "Default or device-derived flash size" + default n + +config STM32_FLASH_CONFIG_4 + bool "Flash size designator 4, 16 KiB" + default n + +config STM32_FLASH_CONFIG_6 + bool "Flash size designator 6, 32 KiB" + default n + +config STM32_FLASH_CONFIG_8 + bool "Flash size designator 8, 64 KiB" + default n + +config STM32_FLASH_CONFIG_B + bool "Flash size designator B, 128 KiB" + default n + +config STM32_FLASH_CONFIG_C + bool "Flash size designator C, 256 KiB" + default n + +config STM32_FLASH_CONFIG_C_320 + bool "STM32WB flash size designator C, 320 KiB variant" + default n + +config STM32_FLASH_CONFIG_D + bool "Flash size designator D, 384 KiB" + default n + +config STM32_FLASH_CONFIG_E + bool "Flash size designator E, 512 KiB" + default n + +config STM32_FLASH_CONFIG_F + bool "Flash size designator F, 768 KiB" + default n + +config STM32_FLASH_CONFIG_G + bool "Flash size designator G, 1024 KiB" + default n + +config STM32_FLASH_CONFIG_I + bool "Flash size designator I, 2048 KiB" + default n + +config STM32_FLASH_CONFIG_Y + bool "Flash size designator Y, 640 KiB" + default n + +config STM32_FLASH_CONFIG_Z + bool "Legacy STM32 flash size designator Z" + default n + +config STM32_FLASH_OVERRIDE + bool "Override Flash Designator" if ARCH_CHIP_STM32G0 || ARCH_CHIP_STM32C0 + default y if ARCH_CHIP_STM32F7 || STM32_COMMON_F7_H7_H5 + default y if STM32_COMMON_L4_H5_L5_U5 || ARCH_CHIP_STM32WB + default y if ARCH_CHIP_STM32WL5 + default n + +choice + prompt "Override Flash Size Designator" + depends on STM32_FLASH_OVERRIDE + default STM32_FLASH_OVERRIDE_DEFAULT + ---help--- + STM32 parts numbering ends with a number or letter that designates + the internal FLASH size. Select "Default" to use the size from + the selected chip. Select another designator only when the part + variant differs from the listed chip selection. + +config STM32_FLASH_OVERRIDE_DEFAULT + bool "Default" + +config STM32_FLASH_OVERRIDE_6 + bool "6 32KiB" + +config STM32_FLASH_OVERRIDE_8 + bool "8 64KiB" + +config STM32_FLASH_OVERRIDE_B + bool "B 128KiB" + +config STM32_FLASH_OVERRIDE_C + bool "C 256KiB" + +config STM32_FLASH_OVERRIDE_C_320 + bool "C 320KiB" + +config STM32_FLASH_OVERRIDE_E + bool "E 512KiB" + +config STM32_FLASH_OVERRIDE_G + bool "G 1024KiB" + +config STM32_FLASH_OVERRIDE_I + bool "I 2048KiB" + +config STM32_FLASH_OVERRIDE_Y + bool "Y 640KiB" + +endchoice # Override Flash Size Designator + +config STM32_FLASH_ART_ACCELERATOR + bool "Flash ART Accelerator" + depends on STM32_HAVE_FLASH_ART_ACCELERATOR + default n + ---help--- + ART Accelerator on the flash memory ITCM interface accelerates code execution + with a system of instruction prefetch and cache lines. + + Enable if code and/or read-only data is accessed through ITCM bus instead of + AXIM bus. + +config STM32_FLASH_PREFETCH + bool "Enable FLASH Pre-fetch" + depends on STM32_STM32F20XX || STM32_STM32F4XXX || STM32_COMMON_L4_H5_L5_U5 || ARCH_CHIP_STM32WB + default STM32_STM32F427 || STM32_STM32F429 || STM32_STM32F446 + default y + ---help--- + Enable FLASH prefetch in F2 and F4 parts (FLASH pre-fetch is always enabled + on F1 parts). Some early revisions of F4 parts do not support FLASH pre-fetch + properly and enabling this option may interfere with ADC accuracy. + +config STM32_FLASH_WORKAROUND_DATA_CACHE_CORRUPTION_ON_RWW + bool "Workaround for FLASH data cache corruption" + depends on STM32_FLASH_DCACHE && (STM32_STM32F20XX || STM32_STM32F4XXX || (ARCH_CHIP_STM32L4 && (STM32_STM32L4X5 || STM32_STM32L4X6 || STM32_STM32L4XR))) + ---help--- + Enable the workaround to fix flash data cache corruption when reading + from one flash bank while writing on other flash bank. See your STM32 + errata to check if your STM32 is affected by this problem. + +config STM32_PROGMEM + bool "Flash PROGMEM support" + depends on STM32_COMMON_F0_L0_G0_C0 && ARCH_HAVE_PROGMEM || STM32_COMMON_F7_H7_H5 + select MTD if STM32_COMMON_F0_L0_G0_C0 && ARCH_HAVE_PROGMEM + select MTD_PROGMEM if STM32_COMMON_F0_L0_G0_C0 && ARCH_HAVE_PROGMEM + ---help--- + Add progmem support, start block and end block options are provided to + obtain a uniform flash memory mapping. + +config STM32_FLASH_ICACHE + bool "Enable FLASH Instruction Cache" + default y + depends on STM32_HAVE_FLASH_ICACHE + ---help--- + Enable the FLASH instruction cache. + +config STM32_FLASH_DCACHE + bool "Enable FLASH Data Cache" + default y + depends on STM32_HAVE_FLASH_DCACHE + ---help--- + Enable the FLASH data cache. diff --git a/arch/arm/src/common/stm32/Kconfig.foc b/arch/arm/src/common/stm32/Kconfig.foc new file mode 100644 index 0000000000000..79e61e292e415 --- /dev/null +++ b/arch/arm/src/common/stm32/Kconfig.foc @@ -0,0 +1,197 @@ +# +# STM32 common FOC options. +# + +config STM32_FOC_HAVE_ADC_CHAN0_WORKAROUND + bool + +config STM32_FOC_USE_TIM1 + bool + select STM32_TIM1 + select STM32_TIM1_PWM + select STM32_TIM1_CHANNEL1 + select STM32_TIM1_CHANNEL2 + select STM32_TIM1_CHANNEL3 + select STM32_TIM1_CHANNEL4 if STM32_FOC_ADC_CCR4 + select STM32_TIM1_CH1OUT + select STM32_TIM1_CH2OUT + select STM32_TIM1_CH3OUT + select STM32_TIM1_CH4OUT if STM32_FOC_ADC_CCR4 + select STM32_TIM1_CH1NOUT if STM32_FOC_HAS_PWM_COMPLEMENTARY + select STM32_TIM1_CH2NOUT if STM32_FOC_HAS_PWM_COMPLEMENTARY + select STM32_TIM1_CH3NOUT if STM32_FOC_HAS_PWM_COMPLEMENTARY + ---help--- + The TIM1 generates PWM for the FOC + +config STM32_FOC_USE_TIM8 + bool + select STM32_TIM8 + select STM32_TIM8_PWM + select STM32_TIM8_CHANNEL1 + select STM32_TIM8_CHANNEL2 + select STM32_TIM8_CHANNEL3 + select STM32_TIM8_CHANNEL4 if STM32_FOC_ADC_CCR4 + select STM32_TIM8_CH1OUT + select STM32_TIM8_CH2OUT + select STM32_TIM8_CH3OUT + select STM32_TIM8_CH4OUT if STM32_FOC_ADC_CCR4 + select STM32_TIM8_CH1NOUT if STM32_FOC_HAS_PWM_COMPLEMENTARY + select STM32_TIM8_CH2NOUT if STM32_FOC_HAS_PWM_COMPLEMENTARY + select STM32_TIM8_CH3NOUT if STM32_FOC_HAS_PWM_COMPLEMENTARY + ---help--- + The TIM8 generates PWM for the FOC + +config STM32_FOC_USE_ADC1 + bool + select STM32_ADC1 + select STM32_ADC1_SCAN if ARCH_CHIP_STM32F7 || STM32_HAVE_IP_ADC_M3M4_V1 + select STM32_ADC1_JEXTSEL + +config STM32_FOC_USE_ADC2 + bool + select STM32_ADC2 + select STM32_ADC2_SCAN if ARCH_CHIP_STM32F7 || STM32_HAVE_IP_ADC_M3M4_V1 + select STM32_ADC2_JEXTSEL + +config STM32_FOC_USE_ADC3 + bool + select STM32_ADC3 + select STM32_ADC3_SCAN if ARCH_CHIP_STM32F7 || STM32_HAVE_IP_ADC_M3M4_V1 + select STM32_ADC3_JEXTSEL + +# +# + +choice + prompt "FOC ADC trigger selection" + depends on STM32_FOC + default STM32_FOC_ADC_TRGO + +config STM32_FOC_ADC_CCR4 + bool "FOC uses CCR4 as ADC trigger" + ---help--- + This option uses the software frequency prescaler and is + not possible for 4-phase output. + +config STM32_FOC_ADC_TRGO + bool "FOC uses TRGO as ADC trigger" + depends on STM32_HAVE_IP_ADC_M3M4_V2 || ARCH_CHIP_STM32F7 || (STM32_HAVE_IP_ADC_M3M4_V1 && !STM32_FOC_FOC1) + select STM32_PWM_TRGO + ---help--- + This option allows you to use higher PWM frequency and works for 4-phase output. + It is not possible for ADC IPv1 if FOC1 enabled (no T8TRGO in JEXTSEL). + +endchoice # "FOC ADC trigger selection" + +choice + prompt "FOC0 device ADC selection" + depends on STM32_FOC_FOC0 + default STM32_FOC_FOC0_ADC1 + +config STM32_FOC_FOC0_ADC1 + bool "FOC0 uses ADC1" + depends on STM32_HAVE_ADC1 + select STM32_FOC_USE_ADC1 + +config STM32_FOC_FOC0_ADC2 + bool "FOC0 uses ADC2" + depends on STM32_HAVE_ADC2 + select STM32_FOC_USE_ADC2 + +config STM32_FOC_FOC0_ADC3 + bool "FOC0 uses ADC3" + depends on STM32_HAVE_ADC3 + select STM32_FOC_USE_ADC3 + +config STM32_FOC_FOC0_ADC4 + bool "FOC0 uses ADC4" + depends on STM32_HAVE_ADC4 + select STM32_FOC_USE_ADC4 + +endchoice # "FOC0 device ADC selection" + +choice + prompt "FOC1 device ADC selection" + depends on STM32_FOC_FOC1 + default STM32_FOC_FOC1_ADC2 + +config STM32_FOC_FOC1_ADC1 + bool "FOC1 uses ADC1" + depends on STM32_HAVE_ADC1 + select STM32_FOC_USE_ADC1 + +config STM32_FOC_FOC1_ADC2 + bool "FOC1 uses ADC2" + depends on STM32_HAVE_ADC2 + select STM32_FOC_USE_ADC2 + +config STM32_FOC_FOC1_ADC3 + bool "FOC1 uses ADC3" + depends on STM32_HAVE_ADC3 + select STM32_FOC_USE_ADC3 + +config STM32_FOC_FOC1_ADC4 + bool "FOC1 uses ADC4" + depends on STM32_HAVE_ADC4 + select STM32_FOC_USE_ADC4 + +endchoice # "FOC0 device ADC selection" + +menuconfig STM32_FOC + bool "STM32 lower-half FOC support" + depends on STM32_HAVE_COMMON_FOC || ARCH_CHIP_STM32F7 + select ARCH_IRQPRIO + select STM32_ADC + select STM32_PWM_MULTICHAN + select STM32_PWM_LL_OPS + select STM32_ADC_LL_OPS + select STM32_ADC_CHANGE_SAMPLETIME + select STM32_ADC_NO_STARTUP_CONV + +config STM32_FOC_FOC0 + bool "FOC0 device (TIM1 for PWM modulation)" + depends on STM32_FOC && STM32_HAVE_TIM1 + select STM32_FOC_USE_TIM1 + ---help--- + Enable support for FOC0 device that uses TIM1 for PWM modulation + +config STM32_FOC_FOC1 + bool "FOC1 device (TIM8 for PWM modulation)" + depends on STM32_FOC && STM32_HAVE_TIM8 + select STM32_FOC_USE_TIM8 + ---help--- + Enable support for FOC1 device that uses TIM8 for PWM modulation + +config STM32_FOC_HAS_PWM_COMPLEMENTARY + bool "FOC PWM has complementary outputs" + depends on STM32_FOC + ---help--- + Enable complementary outputs for the FOC PWM (sometimes called 6-PWM mode) + +# hidden variables and automatic configuration + +if STM32_FOC + +config STM32_FOC_USE_ADC4 + bool + default n + select STM32_ADC4 + select STM32_ADC3_JEXTSEL + +config STM32_FOC_G4_ADCCHAN0_WORKAROUND + bool "FOC G4 ADC channel 0 unwanted conversion workaround" + default n + depends on STM32_FOC_HAVE_ADC_CHAN0_WORKAROUND + ---help--- + Some STM32G4 family chips have an issue that causes unwanted ADC channel 0 + conversion when a regular conversion is interrupted by an injected conversion. + This FOC implementation uses injected conversion to sample phase currents + and allows user to use regular conversion as an auxiliary analog conversion. + In this case, there is a certain probability that regular conversion will be + interrupted by an injected conversion that will lead to an incorrect reading + of phase currents. + + This workaround inserts a dummy conversion at the beginning of the injected + sequence. For more details look at the chip errata documents. + +endif #STM32_FOC diff --git a/arch/arm/src/common/stm32/Kconfig.gpio b/arch/arm/src/common/stm32/Kconfig.gpio new file mode 100644 index 0000000000000..17ee405e9e1c6 --- /dev/null +++ b/arch/arm/src/common/stm32/Kconfig.gpio @@ -0,0 +1,11 @@ +# +# STM32 common GPIO options. +# + +# STM32 GPIO configuration options. + +config STM32_GPIO_HAVE_PORTD + bool + +config STM32_GPIO_HAVE_PORTE + bool diff --git a/arch/arm/src/common/stm32/Kconfig.have b/arch/arm/src/common/stm32/Kconfig.have new file mode 100644 index 0000000000000..b7845fd96f313 --- /dev/null +++ b/arch/arm/src/common/stm32/Kconfig.have @@ -0,0 +1,1136 @@ +# +# STM32 hidden hardware-capability flags (single source of truth). +# +# All STM32_HAVE_* / STM32_HAVE_IP_* symbols are defined here. They are +# prompt-less bool selectors describing what hardware exists on a chip and +# which IP-core version a peripheral uses. Family Kconfig files +# (arch/arm/src/stm32/Kconfig) "select" these symbols to describe their +# silicon; never add a prompt here. User-visible peripheral selection lives +# in Kconfig.periph and per-peripheral options in Kconfig.. +# +# Naming: an STM32_HAVE_IP__V symbol names the IP-core VERSION only; +# it must NOT encode the CPU core, because a given IP version is the same +# silicon regardless of whether it sits next to a Cortex-M0 or M3/M4 core (e.g. +# SPI v2 is SPI v2 on both STM32F0 and STM32F4). When a core-specific driver +# .c file or register header has to be chosen, use the standard NuttX core +# symbols (CONFIG_ARCH_CORTEXM0 for M0, CONFIG_ARCH_CORTEXM3 / ARCH_CORTEXM4 +# otherwise) -- not an STM32_HAVE_IP_* symbol. +# +# Two-level selection is intentional and must NOT be "cleaned up" as a +# duplicate: some peripherals use a "register-set" symbol that picks the +# hardware header (e.g. STM32_HAVE_IP_FLASH_M3M4_V1 -> hardware/stm32_flash.h, +# STM32_HAVE_IP_DMA_V1/_V2 -> hardware/stm32_dma.h) AND a separate +# "driver-variant" symbol that picks the .c file in Make.defs (e.g. +# STM32_HAVE_IP_FLASH_M3M4_F2F4, STM32_HAVE_IP_DMA_V2_STREAM). A family +# legitimately selects one of each. +# +# Within a single mutually-exclusive group (the #elif dispatch in +# hardware/stm32_.h and the else-if chain in Make.defs), a family must +# select exactly one member; the dispatch headers carry #error guards that +# enforce this at build time. +# + +# ADC capabilities + +config STM32_HAVE_ADC_TIMTRIG_TRGO2 + bool + default y if (STM32_HAVE_IP_ADC_M3M4_V1 || STM32_HAVE_IP_ADC_M3M4_V2) || STM32_HAVE_IP_ADC_M0_V1 || ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32H5 + +config STM32_HAVE_ADC_TIMTRIG_TRGO + bool + default y if ARCH_CHIP_STM32H7 || STM32_COMMON_L5_U5 + +config STM32_HAVE_TIM_ADC_CHANNEL + bool + +config STM32_HAVE_ADC_L4 + bool + +config STM32_HAVE_ADC_H5 + bool + +config STM32_HAVE_ADC2 + bool + +config STM32_HAVE_ADC3 + bool + +config STM32_HAVE_ADC4 + bool + +config STM32_HAVE_ADC5 + bool + +config STM32_HAVE_ADC_OVERSAMPLE + bool + default STM32_STM32L0 || STM32_STM32G0 || STM32_STM32C0 + +config STM32_HAVE_SDADC1 + bool + +config STM32_HAVE_SDADC2 + bool + +config STM32_HAVE_SDADC3 + bool + +config STM32_HAVE_IP_SDADC_M3M4_V1 + bool + +config STM32_HAVE_IP_ADC_M3M4_V1 + bool + +config STM32_HAVE_IP_ADC_M3M4_V1_BASIC + bool + select STM32_HAVE_IP_ADC_M3M4_V1 + +config STM32_HAVE_IP_ADC_M3M4_V2 + bool + +config STM32_HAVE_IP_ADC_M3M4_V2_BASIC + bool + select STM32_HAVE_IP_ADC_M3M4_V2 + +config STM32_HAVE_IP_ADC_M0_V1 + bool + +config STM32_HAVE_ADC1 + bool + default y if (STM32_HAVE_IP_ADC_M3M4_V1 || STM32_HAVE_IP_ADC_M3M4_V2) + +# BLE capabilities + +config STM32_HAVE_BLE + bool + +# CACHE capabilities + +config STM32_HAVE_DCACHE1 + bool + +config STM32_HAVE_ICACHE + bool + +# CAN capabilities + +config STM32_HAVE_CAN1 + bool + +config STM32_HAVE_CAN2 + bool + +config STM32_HAVE_CAN3 + bool + +config STM32_HAVE_IP_CAN_BXCAN_M0_V1 + bool + +config STM32_HAVE_IP_CAN_BXCAN_M3M4_V1 + bool + +# CEC capabilities + +config STM32_HAVE_CEC + bool + +# CLOCK capabilities + +config STM32_HAVE_CSI + bool + +config STM32_HAVE_CRS + bool + +config STM32_HAVE_HSI48 + bool + +config STM32_HAVE_IP_HSI48_M0_V1 + bool + +# COMP capabilities + +config STM32_HAVE_COMP1 + bool + +config STM32_HAVE_COMP2 + bool + +config STM32_HAVE_COMP3 + bool + +config STM32_HAVE_COMP4 + bool + +config STM32_HAVE_COMP5 + bool + +config STM32_HAVE_COMP6 + bool + +config STM32_HAVE_COMP7 + bool + +config STM32_HAVE_IP_COMP_M3M4_V1 + bool + +config STM32_HAVE_IP_COMP_M3M4_V2 + bool + +config STM32_HAVE_IP_COMP_M0_V1 + bool + +config STM32_HAVE_COMP + bool + default y if STM32_HAVE_COMP1 || STM32_HAVE_COMP2 || STM32_HAVE_COMP3 || STM32_HAVE_COMP4 || STM32_HAVE_COMP5 || STM32_HAVE_COMP6 || STM32_HAVE_COMP7 + +# CORDIC capabilities + +config STM32_HAVE_CORDIC + bool + +config STM32_HAVE_FMAC + bool + +config STM32_HAVE_IP_CORDIC_M3M4_V1 + bool + +# DAC capabilities + +config STM32_HAVE_DAC_LL_OPS + bool + +config STM32_HAVE_IP_DAC_M3M4_V1 + bool + +config STM32_HAVE_IP_DAC_M3M4_V2 + bool + +config STM32_HAVE_IP_DAC_M0_V1 + bool + +config STM32_HAVE_DAC1 + bool + +config STM32_HAVE_DAC2 + bool + +config STM32_HAVE_DAC3 + bool + +config STM32_HAVE_DAC4 + bool + +# DBGMCU capabilities + +config STM32_HAVE_IP_DBGMCU_M0_V1 + bool + +config STM32_HAVE_IP_DBGMCU_M3M4_V1 + bool + select STM32_DBGMCU_HAVE_TIM_FZ_IN_CR + +config STM32_HAVE_IP_DBGMCU_M3M4_V2 + bool + select STM32_DBGMCU_HAVE_TIM_FZ_IN_APB2_FZ + +config STM32_HAVE_IP_DBGMCU_M3M4_V3 + bool + select STM32_DBGMCU_HAVE_TIM_FZ_IN_APB2_FZ + +# DCMI capabilities + +config STM32_HAVE_DCMI_PSSI + bool + +config STM32_HAVE_DCMI + bool + +config STM32_HAVE_IP_DCMI_V1 + bool + +# DFSDM capabilities + +config STM32_HAVE_MDF1 + bool + +config STM32_HAVE_ADF1 + bool + +config STM32_HAVE_DFSDM1 + bool + +# DMA capabilities + +config STM32_HAVE_MDMA + bool + +config STM32_HAVE_BDMA + bool + +config STM32_HAVE_GPADMA1 + bool + +config STM32_HAVE_LPDMA1 + bool + +config STM32_HAVE_DMA1 + bool + +config STM32_HAVE_DMA2 + bool + +config STM32_HAVE_DMA2D + bool + +config STM32_HAVE_DMAMUX + bool + +config STM32_HAVE_IP_DMA_V1 + bool + +config STM32_HAVE_IP_DMA_V2 + bool + +config STM32_HAVE_IP_DMA_V1_7CH + bool + +config STM32_HAVE_IP_DMA_V1_7CH_DMAMUX + bool + +config STM32_HAVE_IP_DMA_V1_8CH + bool + +config STM32_HAVE_IP_DMA_V1_8CH_DMAMUX + bool + +config STM32_HAVE_IP_DMA_V2_STREAM + bool + +config STM32_HAVE_IP_DMA2D_M3M4_V1 + bool + +# DTS capabilities + +config STM32_HAVE_DTS + bool + +# ETH capabilities + +config STM32_HAVE_ETHMAC + bool + +config STM32_HAVE_IP_ETHMAC_M3M4_V1 + bool + +config STM32_HAVE_ETHRNET + bool + +config STM32_HAVE_ETHERNET + bool + +# FDCAN capabilities + +config STM32_HAVE_FDCAN_H7 + bool + +config STM32_HAVE_FDCAN1 + bool + +config STM32_HAVE_FDCAN2 + bool + +config STM32_HAVE_FDCAN3 + bool + +config STM32_HAVE_IP_FDCAN_MCAN_M0_V1 + bool + +config STM32_HAVE_IP_FDCAN_MCAN_M3M4_V1 + bool + +# FLASH capabilities + +config STM32_HAVE_FLASH_ART_ACCELERATOR + bool + +config STM32_HAVE_FLASH + bool + +config STM32_HAVE_OTA_PARTITION + bool + +config STM32_HAVE_IP_FLASH_M0_V1 + bool + +config STM32_HAVE_IP_FLASH_M3M4_V1 + bool + +config STM32_HAVE_IP_FLASH_M0_G0C0 + bool + +config STM32_HAVE_IP_FLASH_M3M4_L1 + bool + +config STM32_HAVE_IP_FLASH_M3M4_F1F3 + bool + +config STM32_HAVE_IP_FLASH_M3M4_F2F4 + bool + +config STM32_HAVE_IP_FLASH_M3M4_G4 + bool + +config STM32_HAVE_OTFDEC1 + bool + +config STM32_HAVE_OTFDEC2 + bool + +config STM32_HAVE_FLASH_ICACHE + bool + +config STM32_HAVE_FLASH_DCACHE + bool + +# FOC capabilities + +config STM32_HAVE_COMMON_FOC + bool + +# GPIO capabilities + +config STM32_HAVE_LPGPIO1 + bool + +config STM32_HAVE_GPIOF + bool + +config STM32_HAVE_GPIOG + bool + +# HRTIM capabilities + +config STM32_HAVE_HRTIM1 + bool + +config STM32_HAVE_IP_HRTIM_M3M4_V1 + bool + +# I2C capabilities + +config STM32_HAVE_I2C_H5 + bool + +config STM32_HAVE_I2C5 + bool + +config STM32_HAVE_I2C6 + bool + +config STM32_HAVE_IP_I2C_M3M4_V1 + bool + +config STM32_HAVE_IP_I2C_M3M4_V2 + bool + +config STM32_HAVE_IP_I2C_M0_V1 + bool + +config STM32_HAVE_I2C1 + bool + +config STM32_HAVE_I2C2 + bool + +config STM32_HAVE_I2C3 + bool + +config STM32_HAVE_I2C4 + bool + +# IPCC capabilities + +config STM32_HAVE_HSEM + bool + +config STM32_HAVE_CM4 + bool + +config STM32_HAVE_MBOX + bool + +# JPEG capabilities + +config STM32_HAVE_JPEG + bool + +# LPUART capabilities + +config STM32_HAVE_LPUART1 + bool + +config STM32_HAVE_LPUART2 + bool + +config STM32_HAVE_LPUART + bool + +# LTDC capabilities + +config STM32_HAVE_LTDC + bool + +config STM32_HAVE_IP_LTDC_M3M4_V1 + bool + +config STM32_HAVE_DSIHOST + bool + +config STM32_HAVE_LCD + bool + +# MEMORY capabilities + +config STM32_HAVE_RAMCFG + bool + +config STM32_HAVE_SRAM1 + bool + +config STM32_HAVE_SRAM2 + bool + +config STM32_HAVE_SRAM3 + bool + +config STM32_HAVE_SRAM5 + bool + +config STM32_HAVE_CCM + bool + +config STM32_HAVE_FMC + bool + +config STM32_HAVE_FSMC + bool + +config STM32_HAVE_IP_CCM_M3M4_V1 + bool + +config STM32_HAVE_IP_FMC_M3M4_V1 + bool + +config STM32_HAVE_IP_FSMC_M3M4_V1 + bool + +config STM32_HAVE_IP_BBSRAM_M3M4_V1 + bool + +config STM32_HAVE_IP_BKP_M3M4_V1 + bool + +config STM32_HAVE_COMMON_WASTE + bool + default y if STM32_COMMON_LEGACY + +config STM32_HAVE_IP_DFUMODE_M3M4_V1 + bool + +config STM32_HAVE_SRAM2A + bool + +config STM32_HAVE_SRAM2B + bool + +# OPAMP capabilities + +config STM32_HAVE_OPAMP1 + bool + +config STM32_HAVE_OPAMP2 + bool + +config STM32_HAVE_OPAMP3 + bool + +config STM32_HAVE_OPAMP4 + bool + +config STM32_HAVE_OPAMP5 + bool + +config STM32_HAVE_OPAMP6 + bool + +config STM32_HAVE_IP_OPAMP_M3M4_V1 + bool + +# POWER capabilities + +config STM32_HAVE_OVERDRIVE + bool + +config STM32_HAVE_VREF + bool + +config STM32_HAVE_VREFINT + bool + +config STM32_HAVE_PWR_DIRECT_SMPS_SUPPLY + bool + +config STM32_HAVE_IP_PWR_M0_V1 + bool + +config STM32_HAVE_IP_PWR_G0 + bool + +config STM32_HAVE_IP_PWR_M3M4_V1 + bool + +config STM32_HAVE_SMPS + bool + +# QSPI capabilities + +config STM32_HAVE_QSPI1 + bool + +config STM32_HAVE_OCTOSPIM + bool + +config STM32_HAVE_OCTOSPI1 + bool + +config STM32_HAVE_OCTOSPI2 + bool + +config STM32_HAVE_QSPI + bool + +# RNG capabilities + +config STM32_HAVE_RNG + bool + +config STM32_HAVE_IP_RNG_M0_V1 + bool + +config STM32_HAVE_IP_RNG_M3M4_V1 + bool + +# RTC capabilities + +config STM32_HAVE_RTC_MAGIC + bool + default y if STM32_COMMON_LEGACY && STM32_RTC && !STM32_HAVE_RTC_COUNTER + default y if (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4) && STM32_RTC + default y if (STM32_COMMON_L5_U5 || ARCH_CHIP_STM32WB) && STM32_RTC + +config STM32_HAVE_RTCAPB + bool + +config STM32_HAVE_RTC_COUNTER + bool + +config STM32_HAVE_IP_RTC_COUNTER_M3M4_V1 + bool + +config STM32_HAVE_IP_RTCC_M0_V1 + bool + +config STM32_HAVE_IP_RTCC_M3M4_V1 + bool + +config STM32_HAVE_IP_RTCC_M3M4_L1 + bool + +config STM32_HAVE_IP_RTCC_M3M4_F4 + bool + +config STM32_HAVE_IP_RTC_M3M4_V1 + bool + +config STM32_HAVE_RTC_SUBSECONDS + bool + select ARCH_HAVE_RTC_SUBSECONDS + +# SAI capabilities + +config STM32_HAVE_SAIPLL + bool + +config STM32_HAVE_SAI + bool + +config STM32_HAVE_I2S3 + bool + +config STM32_HAVE_I2S2 + bool + +config STM32_HAVE_SPI2S2 + bool + +config STM32_HAVE_I2SPLL + bool + +config STM32_HAVE_IP_I2S_M3M4_V1 + bool + +config STM32_HAVE_SAI1 + bool + +config STM32_HAVE_SAI2 + bool + +# SDIO capabilities + +config STM32_HAVE_SDIO + bool + +config STM32_HAVE_SDMMC1 + bool + +config STM32_HAVE_SDMMC2 + bool + +config STM32_HAVE_IP_SDIO_M3M4_V1 + bool + +# SECURITY capabilities + +config STM32_HAVE_FIREWALL + bool + +config STM32_HAVE_GTZC1 + bool + +config STM32_HAVE_GTZC2 + bool + +config STM32_HAVE_PKA + bool + +config STM32_HAVE_SAES + bool + +config STM32_HAVE_AES + bool + +config STM32_HAVE_CRYP + bool + +config STM32_HAVE_IP_AES_M0_V1 + bool + +config STM32_HAVE_IP_AES_M3M4_V1 + bool + +config STM32_HAVE_IP_CRYPTO_M3M4_V1 + bool + +config STM32_HAVE_IP_CRYPTO_H7 + bool + +config STM32_HAVE_HASH + bool + +# SPI capabilities + +config STM32_HAVE_SPI_CORE_DMA + bool + default y if STM32_COMMON_LEGACY || STM32_COMMON_F0_L0_G0_C0 + default y if STM32_COMMON_F7_H7_H5 + default y if ARCH_CHIP_STM32WL5 + default y if STM32_COMMON_L4_L5_U5 && STM32_SPI + default y if ARCH_CHIP_STM32WB && (STM32_SPI1 || STM32_SPI2) && STM32_DMA + +config STM32_HAVE_SPI_DMA_FAMILY_WL5 + bool + default y if STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7 + default y if STM32_COMMON_H7_H5 || ARCH_CHIP_STM32WL5 + +config STM32_HAVE_SPI_DMA_FAMILY + bool + default y if STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7 + default y if STM32_COMMON_H7_H5 + +config STM32_HAVE_IP_SPI_V1 + bool + +config STM32_HAVE_IP_SPI_V2 + bool + +config STM32_HAVE_IP_SPI_V3 + bool + +config STM32_HAVE_IP_SPI_V4 + bool + +config STM32_HAVE_SPI1 + bool + +config STM32_HAVE_SPI2 + bool + +config STM32_HAVE_SPI3 + bool + +config STM32_HAVE_SPI4 + bool + +config STM32_HAVE_SPI5 + bool + +config STM32_HAVE_SPI6 + bool + +# SYSTEM capabilities + +config STM32_HAVE_IP_EXTI_V1 + bool + +config STM32_HAVE_IP_EXTI_V2 + bool + +config STM32_HAVE_IP_GPIO_M0_V1 + bool + +config STM32_HAVE_IP_GPIO_M3M4_V1 + bool + + +config STM32_HAVE_SYSCFG + bool + default y if STM32_HAVE_COMP || STM32_HAVE_OPAMP1 || STM32_HAVE_OPAMP2 || STM32_HAVE_OPAMP3 || STM32_HAVE_OPAMP4 || STM32_HAVE_OPAMP5 || STM32_HAVE_OPAMP6 + +config STM32_HAVE_IP_SYSCFG_M3M4_V1 + bool + +config STM32_HAVE_IOCOMPENSATION + bool + +# TIM capabilities + +config STM32_HAVE_TIM_PWM + bool + default y if STM32_COMMON_FULL_FEATURED + +config STM32_HAVE_TIM_PWM_NO_F0 + bool + default y if STM32_HAVE_IP_TIMERS || STM32_COMMON_F7_H7 || STM32_COMMON_L4_H5_L5_U5 + +config STM32_HAVE_TIM_PWM_ADVANCED + bool + default y if STM32_HAVE_IP_TIMERS || STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5 + +config STM32_HAVE_TIM_PWM_SINGLECHAN + bool + default y if STM32_HAVE_IP_TIMERS || STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5 + +config STM32_HAVE_TIM_PWM_INTERNAL + bool + default y if STM32_HAVE_IP_TIMERS || STM32_COMMON_F7_H7_H5 + +config STM32_HAVE_TIM_PWM_STM32PWM + bool + default y if STM32_HAVE_IP_TIMERS || STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5 || ARCH_CHIP_STM32U5 + +config STM32_HAVE_TIM_PWM_CHMODE_EXTENDED + bool + default y if (STM32_HAVE_IP_TIMERS && STM32_HAVE_IP_TIMERS_M3M4_V2) || STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5 + +config STM32_HAVE_TIM_PWM_CHMODE_LEGACY + bool + default y if STM32_HAVE_IP_TIMERS && !STM32_HAVE_IP_TIMERS_M3M4_V2 + +config STM32_HAVE_TIM_PWM_CHMODE_LIMITED + bool + default y if STM32_HAVE_IP_TIMERS_M0_V1 || STM32_COMMON_L5_U5 + +config STM32_HAVE_TIM_PWM_CHMODE_TIM16_17_EXTENDED + bool + default y if STM32_HAVE_IP_TIMERS || ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5 + +config STM32_HAVE_TIM_PWM_NOUT_REQUIRES_OUT + bool + default y if STM32_HAVE_IP_TIMERS || STM32_COMMON_L4_L5_U5 + +config STM32_HAVE_PWM_MULTICHAN + bool + default y if STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_PWM + default y if (STM32_HAVE_IP_TIMERS || STM32_COMMON_F7_H7) && STM32_PWM + default y if (ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5 || ARCH_CHIP_STM32U5) && STM32_PWM + default y if ARCH_CHIP_STM32L5 && STM32_PWM_MULTICHAN_L5_TIMERS + +config STM32_HAVE_QENCODER_MAIN + bool + default y if STM32_HAVE_IP_TIMERS || STM32_COMMON_F7_H7 + default y if STM32_COMMON_L4_L5_U5 + +config STM32_HAVE_QENCODER_16BIT + bool + default y if STM32_QENCODER_STM32 || STM32_QENCODER_F0 + +config STM32_ENERGYLITE + bool + select STM32_HAVE_TIM6 if STM32_HAVE_IP_TIMERS + select STM32_HAVE_TIM7 if STM32_HAVE_IP_TIMERS + +config STM32_HAVE_LPTIM_CHANNEL + bool + +config STM32_HAVE_IP_TIMERS + bool + default y if STM32_HAVE_IP_TIMERS_M3M4_V1 + default y if STM32_HAVE_IP_TIMERS_M3M4_V2 + default y if STM32_HAVE_IP_TIMERS_M3M4_V3 + default y if STM32_HAVE_IP_TIMERS_M0_V1 + +config STM32_HAVE_IP_TIMERS_M3M4_V1 + bool + +config STM32_HAVE_IP_TIMERS_M3M4_V2 + bool + +config STM32_HAVE_IP_TIMERS_M3M4_V3 + bool + +config STM32_HAVE_IP_TIMERS_M0_V1 + bool + +config STM32_HAVE_TIM_ADC_TRIGGER + bool + default y if STM32_HAVE_IP_ADC_M3M4_V1 + default y if STM32_HAVE_IP_ADC_M3M4_V2 + default y if STM32_HAVE_IP_ADC_M0_V1 + default y if STM32_COMMON_F7_H7 + default y if STM32_COMMON_L4_H5_L5_U5 + default y if ARCH_CHIP_STM32F7 + default y if ARCH_CHIP_STM32H7 + +config STM32_HAVE_TIM_DAC_TRIGGER + bool + default y if STM32_COMMON_LEGACY + default y if ARCH_CHIP_STM32F7 + default y if STM32_COMMON_L4_L5_U5 + +config STM32_HAVE_TIM1 + bool + +config STM32_HAVE_TIM2 + bool + +config STM32_HAVE_TIM3 + bool + +config STM32_HAVE_TIM4 + bool + +config STM32_HAVE_TIM5 + bool + +config STM32_HAVE_TIM6 + bool + +config STM32_HAVE_TIM7 + bool + +config STM32_HAVE_TIM8 + bool + +config STM32_HAVE_TIM9 + bool + +config STM32_HAVE_TIM10 + bool + +config STM32_HAVE_TIM11 + bool + +config STM32_HAVE_TIM12 + bool + +config STM32_HAVE_TIM13 + bool + +config STM32_HAVE_TIM14 + bool + +config STM32_HAVE_TIM15 + bool + +config STM32_HAVE_TIM16 + bool + +config STM32_HAVE_TIM17 + bool + +config STM32_HAVE_TIM18 + bool + +config STM32_HAVE_TIM19 + bool + +config STM32_HAVE_TIM20 + bool + +config STM32_HAVE_LPTIM1 + bool + +config STM32_HAVE_IP_ONESHOT_M3M4_V1 + bool + +config STM32_HAVE_IP_FREERUN_M3M4_V1 + bool + +# TSC capabilities + +config STM32_HAVE_TSC + bool + +# UART capabilities + +config STM32_HAVE_SWPMI + bool + +config STM32_HAVE_USART_H5 + bool + +config STM32_HAVE_USART_RXFIFO_THRESHOLD + bool + +config STM32_HAVE_USART2 + bool + +config STM32_HAVE_USART3 + bool + +config STM32_HAVE_UART4 + bool + +config STM32_HAVE_UART5 + bool + +config STM32_HAVE_USART6 + bool + +config STM32_HAVE_UART7 + bool + +config STM32_HAVE_UART8 + bool + +config STM32_HAVE_IP_USART + bool + +config STM32_HAVE_IP_USART_V1 + bool + select STM32_HAVE_IP_USART + +config STM32_HAVE_IP_USART_V2 + bool + select STM32_HAVE_IP_USART + +config STM32_HAVE_IP_USART_V3 + bool + select STM32_HAVE_IP_USART + +config STM32_HAVE_IP_USART_V4 + bool + select STM32_HAVE_IP_USART + select STM32_HAVE_USART_RXFIFO_THRESHOLD + +config STM32_HAVE_USART4 + bool + +config STM32_HAVE_USART5 + bool + +config STM32_HAVE_USART7 + bool + +config STM32_HAVE_USART8 + bool + +config STM32_HAVE_UART9 + bool + +config STM32_HAVE_USART10 + bool + +config STM32_HAVE_USART11 + bool + +config STM32_HAVE_UART12 + bool + +config STM32_HAVE_USART1 + bool + +# USB capabilities + +config STM32_HAVE_USBFS_MODE + bool + +config STM32_HAVE_USBDRD_HOST + bool + +config STM32_HAVE_OTG_H7 + bool + +config STM32_HAVE_INTERNAL_ULPI + bool + +config STM32_HAVE_EXTERNAL_ULPI + bool + +config STM32_HAVE_UCPD + bool + +config STM32_HAVE_UCPD1 + bool + +config STM32_HAVE_UCPD2 + bool + +config STM32_HAVE_USBDEV + bool + +config STM32_HAVE_IP_USBDEV_M0_V1 + bool + +config STM32_HAVE_IP_USBDEV_M3M4_V1 + bool + +config STM32_HAVE_USBFS + bool + +config STM32_HAVE_IP_USBFS_M3M4_V1 + bool + +config STM32_HAVE_OTGFS + bool + +config STM32_HAVE_IP_OTGFS_M3M4_V1 + bool + +config STM32_HAVE_IP_OTGHS_M3M4_V1 + bool + +config STM32_HAVE_COMMON_USBHOST_DEBUG + bool + default y if STM32_COMMON_LEGACY + +config STM32_HAVE_USB + bool + +# WDG capabilities + +config STM32_HAVE_IP_WDG_M0_V1 + bool + +config STM32_HAVE_IP_WDG_M3M4_V1 + bool diff --git a/arch/arm/src/common/stm32/Kconfig.hciuart b/arch/arm/src/common/stm32/Kconfig.hciuart new file mode 100644 index 0000000000000..81fb4fcb4483b --- /dev/null +++ b/arch/arm/src/common/stm32/Kconfig.hciuart @@ -0,0 +1,292 @@ +# +# STM32 common HCI UART options. +# + +config STM32_HCIUART + bool + +config STM32_HCIUART_RXDMA + bool + +if STM32_USART1_HCIUART + +config STM32_HCIUART1_RXBUFSIZE + int "HCI UART1 Rx buffer size" + default 80 + ---help--- + Characters are buffered as they are received. This specifies + the size of the receive buffer. Ideally this should be at least + the size of the largest frame that can be received + +config STM32_HCIUART1_TXBUFSIZE + int "HCI UART1 Transmit buffer size" + default 80 + ---help--- + Characters are buffered before being sent. This specifies + the size of the transmit buffer. Ideally this should be at least + the size of the largest frame that can be sent + +config STM32_HCIUART1_BAUD + int "HCI UART1 initial BAUD rate" + default 115200 + ---help--- + The configured initial BAUD of the HCIR USART used during bringup. + In most cases this initial rate can be increased by the upper half + HCI UART driver using vendor-specifi HCI UART commands. + +config STM32_HCIUART1_RXDMA + bool "HCI UART1 Rx DMA" + default n + depends on (((STM32_STM32F10XX || STM32_STM32L15XX) && STM32_DMA1) || (!STM32_STM32F10XX && STM32_DMA2)) + select STM32_HCIUART_RXDMA + ---help--- + In high data rate usage, Rx DMA may eliminate Rx overrun errors + +endif # STM32_USART1_HCIUART + +if STM32_USART2_HCIUART + +config STM32_HCIUART2_RXBUFSIZE + int "HCI UART2 Rx buffer size" + default 80 + ---help--- + Characters are buffered as they are received. This specifies + the size of the receive buffer. Ideally this should be at least + the size of the largest frame that can be received + +config STM32_HCIUART2_TXBUFSIZE + int "HCI UART2 Transmit buffer size" + default 80 + ---help--- + Characters are buffered before being sent. This specifies + the size of the transmit buffer. Ideally this should be at least + the size of the largest frame that can be sent + +config STM32_HCIUART2_BAUD + int "HCI UART2 initial BAUD rate" + default 115200 + ---help--- + The configured initial BAUD of the HCIR USART used during bringup. + In most cases this initial rate can be increased by the upper half + HCI UART driver using vendor-specifi HCI UART commands. + +config STM32_HCIUART2_RXDMA + bool "HCI UART2 Rx DMA" + default n + depends on STM32_DMA1 + select STM32_HCIUART_RXDMA + ---help--- + In high data rate usage, Rx DMA may eliminate Rx overrun errors + +endif # STM32_USART2_HCIUART + +if STM32_USART3_HCIUART + +config STM32_HCIUART3_RXBUFSIZE + int "HCI UART3 Rx buffer size" + default 80 + ---help--- + Characters are buffered as they are received. This specifies + the size of the receive buffer. Ideally this should be at least + the size of the largest frame that can be received + +config STM32_HCIUART3_TXBUFSIZE + int "HCI UART3 Transmit buffer size" + default 80 + ---help--- + Characters are buffered before being sent. This specifies + the size of the transmit buffer. Ideally this should be at least + the size of the largest frame that can be sent + +config STM32_HCIUART3_BAUD + int "HCI UART3 initial BAUD rate" + default 115200 + ---help--- + The configured initial BAUD of the HCIR USART used during bringup. + In most cases this initial rate can be increased by the upper half + HCI UART driver using vendor-specifi HCI UART commands. + +config STM32_HCIUART3_RXDMA + bool "HCI UART3 Rx DMA" + default n + depends on STM32_DMA1 + select STM32_HCIUART_RXDMA + ---help--- + In high data rate usage, Rx DMA may eliminate Rx overrun errors + +endif # STM32_USART3_HCIUART + +if STM32_USART6_HCIUART + +config STM32_HCIUART6_RXBUFSIZE + int "HCI UART6 Rx buffer size" + default 80 + ---help--- + Characters are buffered as they are received. This specifies + the size of the receive buffer. Ideally this should be at least + the size of the largest frame that can be received + +config STM32_HCIUART6_TXBUFSIZE + int "HCI UART6 Transmit buffer size" + default 80 + ---help--- + Characters are buffered before being sent. This specifies + the size of the transmit buffer. Ideally this should be at least + the size of the largest frame that can be sent + +config STM32_HCIUART6_BAUD + int "HCI UART6 initial BAUD rate" + default 115200 + ---help--- + The configured initial BAUD of the HCIR USART used during bringup. + In most cases this initial rate can be increased by the upper half + HCI UART driver using vendor-specifi HCI UART commands. + +config STM32_HCIUART6_RXDMA + bool "HCI UART6 Rx DMA" + default n + depends on STM32_DMA1 + select STM32_HCIUART_RXDMA + ---help--- + In high data rate usage, Rx DMA may eliminate Rx overrun errors + +endif # STM32_USART6_HCIUART + +if STM32_UART7_HCIUART + +config STM32_HCIUART7_RXBUFSIZE + int "HCI UART7 Rx buffer size" + default 80 + ---help--- + Characters are buffered as they are received. This specifies + the size of the receive buffer. Ideally this should be at least + the size of the largest frame that can be received + +config STM32_HCIUART7_TXBUFSIZE + int "HCI UART7 Transmit buffer size" + default 80 + ---help--- + Characters are buffered before being sent. This specifies + the size of the transmit buffer. Ideally this should be at least + the size of the largest frame that can be sent + +config STM32_HCIUART7_BAUD + int "HCI UART7 initial BAUD rate" + default 115200 + ---help--- + The configured initial BAUD of the HCIR USART used during bringup. + In most cases this initial rate can be increased by the upper half + HCI UART driver using vendor-specifi HCI UART commands. + +config STM32_HCIUART7_RXDMA + bool "HCI UART7 Rx DMA" + default n + depends on STM32_DMA2 + select STM32_HCIUART_RXDMA + ---help--- + In high data rate usage, Rx DMA may eliminate Rx overrun errors + +endif # STM32_UART7_HCIUART + +if STM32_UART8_HCIUART + +config STM32_HCIUART8_RXBUFSIZE + int "HCI UART8 Rx buffer size" + default 80 + ---help--- + Characters are buffered as they are received. This specifies + the size of the receive buffer. Ideally this should be at least + the size of the largest frame that can be received + +config STM32_HCIUART8_TXBUFSIZE + int "HCI UART8 Transmit buffer size" + default 80 + ---help--- + Characters are buffered before being sent. This specifies + the size of the transmit buffer. Ideally this should be at least + the size of the largest frame that can be sent + +config STM32_HCIUART8_BAUD + int "HCI UART8 initial BAUD rate" + default 115200 + ---help--- + The configured initial BAUD of the HCIR USART used during bringup. + In most cases this initial rate can be increased by the upper half + HCI UART driver using vendor-specifi HCI UART commands. + +config STM32_HCIUART8_RXDMA + bool "HCI UART8 Rx DMA" + default n + depends on STM32_DMA2 + select STM32_HCIUART_RXDMA + ---help--- + In high data rate usage, Rx DMA may eliminate Rx overrun errors + +endif # STM32_UART8_HCIUART + +menu "HCI UART Driver Configuration" + depends on STM32_SERIALDRIVER + +config STM32_HCIUART_RXDMA_BUFSIZE + int "Rx DMA buffer size" + default 32 + range 32 4096 + depends on STM32_HCIUART_RXDMA + ---help--- + The DMA buffer size when using RX DMA to emulate a FIFO. + + When streaming data, the generic serial layer will be called + every time the FIFO receives half or this number of bytes. + + Value given here will be rounded up to next multiple of 4 bytes. + +config STM32_HCIUART_RXDMAPRIO + hex "HCI UART DMA priority" + default 0x00001000 if STM32_STM32F10XX + default 0x00010000 if !STM32_STM32F10XX + depends on STM32_HCIUART_RXDMA + ---help--- + Select HCI UART DMA priority. + + For STM32 F1 family, options are: 0x00000000 low, 0x00001000 medium, + 0x00002000 high, 0x00003000 very high. Default: medium. + + For other STM32's, options are: 0x00000000 low, 0x00010000 medium, + 0x00020000 high, 0x00030000 very high. Default: medium. + +config STM32_HCIUART_SW_RXFLOW + bool "Use Software UART RTS flow control" + default n + ---help--- + Enable UART RTS flow control using Software. Current STM32 have + broken HW based RTS behavior (they assert nRTS after every byte + received) Enable this setting workaround this issue by using + software based management of RTS + + If HCI UART DMA is enabled, this is probably the better selection + as well. In that case, the Rx DMA buffer will avoid Rx overrun due + to short, bursty activity. Software RTS management will probably + result in overall better throughput and should still avoid Rx data + overrun conditions. + +config STM32_HCIUART_UPPER_WATERMARK + int "RTS flow control upper watermark (%)" + default 75 + range 2 100 + depends on STM32_HCIUART_SW_RXFLOW + ---help--- + If software RTS flow control is enable, then RTS will be asserted + when this amount of Rx data has been buffered. The amount is + expressed as a percentage of the Rx buffer size. + +config STM32_HCIUART_LOWER_WATERMARK + int "RTS flow control lower watermark (%)" + default 25 + range 1 99 + depends on STM32_HCIUART_SW_RXFLOW + ---help--- + If software RTS flow control is enable, then RTS will be de-asserted + when there is less than this amount ofdata in the Rx buffere. The + amount is expressed as a percentage of the Rx buffer size. + +endmenu # HCI UART Driver Configuration diff --git a/arch/arm/src/common/stm32/Kconfig.hrtim b/arch/arm/src/common/stm32/Kconfig.hrtim new file mode 100644 index 0000000000000..57170b0a60c88 --- /dev/null +++ b/arch/arm/src/common/stm32/Kconfig.hrtim @@ -0,0 +1,588 @@ +# +# STM32 common HRTIM options. +# + +# STM32 HRTIM configuration options. + +# HRTIM per-instance capability flags +# (hidden; driven by default y if / peripheral selects, never by chip selectors) + +config STM32_HRTIM1_HAVE_PLLCLK + bool + default y if STM32_STM32F33XX + +config STM32_HRTIM_DISABLE_CHARDRV + bool "HRTIM Disable Character Driver" + default n + ---help--- + In most cases we do not need HRTIM Character Driver, so we can disable it + and save some memory. + +config STM32_HRTIM_NO_ENABLE_TIMERS + bool "Do not enable HRTIM timers at startup" + default n + ---help--- + Do not enable HRTIM timers at startup + +menuconfig STM32_HRTIM_ADC + bool "HRTIM ADC Triggering" + default n + ---help--- + Enable HRTIM ADC Triggering support. + +if STM32_HRTIM_ADC + +config STM32_HRTIM_ADC1_TRG1 + bool "HRTIM ADC1 Trigger 1" + default n + +config STM32_HRTIM_ADC1_TRG2 + bool "HRTIM ADC1 Trigger 2" + default n + +config STM32_HRTIM_ADC1_TRG3 + bool "HRTIM ADC1 Trigger 3" + default n + +config STM32_HRTIM_ADC1_TRG4 + bool "HRTIM ADC1 Trigger 4" + default n + +config STM32_HRTIM_ADC2_TRG1 + bool "HRTIM ADC2 Trigger 1" + default n + +config STM32_HRTIM_ADC2_TRG2 + bool "HRTIM ADC2 Trigger 2" + default n + +config STM32_HRTIM_ADC2_TRG3 + bool "HRTIM ADC2 Trigger 3" + default n + +config STM32_HRTIM_ADC2_TRG4 + bool "HRTIM ADC2 Trigger 4" + default n + +endif # STM32_HRTIM_ADC + +config STM32_HRTIM_DAC + bool "HRTIM DAC Triggering" + default n + ---help--- + Enable HRTIM DAC Triggering support. + +config STM32_HRTIM_PWM + bool "HRTIM PWM Outputs" + default n + ---help--- + Enable HRTIM PWM Outputs support. + +config STM32_HRTIM_CAP + bool "HRTIM Capture" + default n + ---help--- + Enable HRTIM Capture support. + +config STM32_HRTIM_INTERRUPTS + bool "HRTIM Interrupts" + default n + ---help--- + Enable HRTIM Interrupts support. + +config STM32_HRTIM_BURST + bool "HRTIM Burst Mode" + depends on STM32_HRTIM_PWM + default n + ---help--- + Enable HRTIM Burst Mode support for PWM outputs. + +config STM32_HRTIM_DEADTIME + bool "HRTIM Dead-time" + depends on STM32_HRTIM_PWM + default n + ---help--- + Enable HRTIM Deadtime support for PWM outputs. + +config STM32_HRTIM_PUSHPULL + bool "HRTIM Push-Pull Mode" + depends on STM32_HRTIM_PWM + default n + ---help--- + Enable HRTIM Push-Pull Mode support for PWM outputs. + +config STM32_HRTIM_CHOPPER + bool "HRTIM Chopper" + depends on STM32_HRTIM_PWM + default n + ---help--- + Enable HRTIM Chopper Mode for PWM outputs. + +config STM32_HRTIM_DMA + bool "HRTIM DMA" + default n + +config STM32_HRTIM_DMABURST + bool "HRTIM DMA Burst" + default n + +config STM32_HRTIM_AUTODELAY + bool "HRTIM Autodelay" + depends on STM32_HRTIM_PWM + default n + +menuconfig STM32_HRTIM_EVENTS + bool "HRTIM Events Configuration" + default n + ---help--- + Enable HRTIM Events support. + +if STM32_HRTIM_EVENTS + +config STM32_HRTIM_EEV1 + bool "HRTIM EEV1" + default n + +config STM32_HRTIM_EEV2 + bool "HRTIM EEV2" + default n + +config STM32_HRTIM_EEV3 + bool "HRTIM EEV3" + default n + +config STM32_HRTIM_EEV4 + bool "HRTIM EEV4" + default n + +config STM32_HRTIM_EEV5 + bool "HRTIM EEV5" + default n + +config STM32_HRTIM_EEV6 + bool "HRTIM EEV6" + default n + +config STM32_HRTIM_EEV7 + bool "HRTIM EEV7" + default n + +config STM32_HRTIM_EEV8 + bool "HRTIM EEV8" + default n + +config STM32_HRTIM_EEV9 + bool "HRTIM EEV9" + default n + +config STM32_HRTIM_EEV10 + bool "HRTIM EEV10" + default n + +endif # STM32_HRTIM_EVENTS + +menuconfig STM32_HRTIM_FAULTS + bool "HRTIM Faults Configuration" + default n + ---help--- + Enable HRTIM Faults support. + +if STM32_HRTIM_FAULTS + +config STM32_HRTIM_FAULT1 + bool "HRTIM Fault 1" + default n + +config STM32_HRTIM_FAULT2 + bool "HRTIM Fault 2" + default n + +config STM32_HRTIM_FAULT3 + bool "HRTIM Fault 3" + default n + +config STM32_HRTIM_FAULT4 + bool "HRTIM Fault 4" + default n + +endif # STM32_HRTIM_FAULTS + +config STM32_HRTIM_CLK_FROM_PLL + bool "HRTIM Clock from PLL" + default n + depends on STM32_HRTIM1_HAVE_PLLCLK + ---help--- + Set PLL as the clock source for HRTIM. + This configuration requires the following conditions: + 1) system clock is PLL, + 2) SYSCLK and PCLK2 ratio must be 1 o 2. + +menu "HRTIM Master Configuration" + depends on STM32_HRTIM_MASTER + +config STM32_HRTIM_MASTER_DAC + bool "HRTIM Master DAC Triggering" + default n + depends on STM32_HRTIM_DAC + +config STM32_HRTIM_MASTER_DMA + bool "HRTIM MASTER DMA" + default n + depends on STM32_HRTIM_DMA + +config STM32_HRTIM_MASTER_IRQ + bool "HRTIM MASTER Interrupts" + default n + depends on STM32_HRTIM_INTERRUPTS + +endmenu # "HRTIM Master Configuration" + +menu "HRTIM Timer A Configuration" + depends on STM32_HRTIM_TIMA + +config STM32_HRTIM_TIMA_CAP + bool "HRTIM TIMA Capture" + default n + depends on STM32_HRTIM_CAPTURE + +config STM32_HRTIM_TIMA_DAC + bool "HRTIM TIMA DAC Triggering" + default n + depends on STM32_HRTIM_DAC + +config STM32_HRTIM_TIMA_DMA + bool "HRTIM TIMA DMA" + default n + depends on STM32_HRTIM_DMA + +config STM32_HRTIM_TIMA_IRQ + bool "HRTIM TIMA Interrupts" + default n + depends on STM32_HRTIM_INTERRUPTS + +config STM32_HRTIM_TIMA_PWM + bool "HRTIM TIMA PWM Outputs" + default n + depends on STM32_HRTIM_PWM + +config STM32_HRTIM_TIMA_PWM_CH1 + bool "HRTIM TIMA PWM Output 1" + default n + depends on STM32_HRTIM_TIMA_PWM + +config STM32_HRTIM_TIMA_PWM_CH2 + bool "HRTIM TIMA PWM Output 2" + default n + depends on STM32_HRTIM_TIMA_PWM + +config STM32_HRTIM_TIMA_BURST + bool "HRTIM TIMA Burst" + default n + depends on (STM32_HRTIM_BURST && STM32_HRTIM_TIMA_PWM) + +config STM32_HRTIM_TIMA_BURST_CH1 + bool "HRTIM TIMA Output 1 Burst Mode" + default n + depends on (STM32_HRTIM_TIMA_BURST && STM32_HRTIM_TIMA_PWM_CH1) + +config STM32_HRTIM_TIMA_BURST_CH2 + bool "HRTIM TIMA Output 2 Burst Mode" + default n + depends on (STM32_HRTIM_TIMA_BURST && STM32_HRTIM_TIMA_PWM_CH2) + +config STM32_HRTIM_TIMA_CHOP + bool "HRTIM TIMA PWM Chopper" + default n + depends on (STM32_HRTIM_CHOPPER && STM32_HRTIM_TIMA_PWM) + +config STM32_HRTIM_TIMA_DT + bool "HRTIM TIMA PWM Dead-time" + default n + depends on (STM32_HRTIM_DEADTIME && STM32_HRTIM_TIMA_PWM) + +config STM32_HRTIM_TIMA_PSHPLL + bool "HRTIM TIMA PWM Push-pull mode" + default n + depends on (STM32_HRTIM_PUSHPULL && STM32_HRTIM_TIMA_PWM) + +endmenu # "HRTIM Timer A Configuration" + +menu "HRTIM Timer B Configuration" + depends on STM32_HRTIM_TIMB + +config STM32_HRTIM_TIMB_CAP + bool "HRTIM TIMB Capture" + default n + depends on STM32_HRTIM_CAPTURE + +config STM32_HRTIM_TIMB_DAC + bool "HRTIM TIMB DAC Triggering" + default n + depends on STM32_HRTIM_DAC + +config STM32_HRTIM_TIMB_DMA + bool "HRTIM TIMB DMA" + default n + depends on STM32_HRTIM_DMA + +config STM32_HRTIM_TIMB_IRQ + bool "HRTIM TIMB Interrupts" + default n + depends on STM32_HRTIM_INTERRUPTS + +config STM32_HRTIM_TIMB_PWM + bool "HRTIM TIMB PWM Outputs" + default n + depends on STM32_HRTIM_PWM + +config STM32_HRTIM_TIMB_PWM_CH1 + bool "HRTIM TIMB PWM Output 1" + default n + depends on STM32_HRTIM_TIMB_PWM + +config STM32_HRTIM_TIMB_PWM_CH2 + bool "HRTIM TIMB PWM Output 2" + default n + depends on STM32_HRTIM_TIMB_PWM + +config STM32_HRTIM_TIMB_BURST + bool "HRTIM TIMB Burst" + default n + depends on (STM32_HRTIM_BURST && STM32_HRTIM_TIMB_PWM) + +config STM32_HRTIM_TIMB_BURST_CH1 + bool "HRTIM TIMB Output 1 Burst Mode" + default n + depends on (STM32_HRTIM_TIMB_BURST && STM32_HRTIM_TIMB_PWM_CH1) + +config STM32_HRTIM_TIMB_BURST_CH2 + bool "HRTIM TIMB Output 2 Burst Mode" + default n + depends on (STM32_HRTIM_TIMB_BURST && STM32_HRTIM_TIMB_PWM_CH2) + +config STM32_HRTIM_TIMB_CHOP + bool "HRTIM TIMB PWM Chopper" + default n + depends on (STM32_HRTIM_CHOPPER && STM32_HRTIM_TIMB_PWM) + +config STM32_HRTIM_TIMB_DT + bool "HRTIM TIMB PWM Dead-time" + default n + depends on (STM32_HRTIM_DEADTIME && STM32_HRTIM_TIMB_PWM) + +config STM32_HRTIM_TIMB_PSHPLL + bool "HRTIM TIMB PWM Push-pull mode" + default n + depends on (STM32_HRTIM_PUSHPULL && STM32_HRTIM_TIMB_PWM) + +endmenu # "HRTIM Timer B Configuration" + +menu "HRTIM Timer C Configuration" + depends on STM32_HRTIM_TIMC + +config STM32_HRTIM_TIMC_CAP + bool "HRTIM TIMC Capture" + default n + depends on STM32_HRTIM_CAPTURE + +config STM32_HRTIM_TIMC_DAC + bool "HRTIM TIMC DAC Triggering" + default n + depends on STM32_HRTIM_DAC + +config STM32_HRTIM_TIMC_DMA + bool "HRTIM TIMC DMA" + default n + depends on STM32_HRTIM_DMA + +config STM32_HRTIM_TIMC_IRQ + bool "HRTIM TIMC Interrupts" + default n + depends on STM32_HRTIM_INTERRUPTS + +config STM32_HRTIM_TIMC_PWM + bool "HRTIM TIMC PWM Outputs" + default n + depends on STM32_HRTIM_PWM + +config STM32_HRTIM_TIMC_PWM_CH1 + bool "HRTIM TIMC PWM Output 1" + default n + depends on STM32_HRTIM_TIMC_PWM + +config STM32_HRTIM_TIMC_PWM_CH2 + bool "HRTIM TIMC PWM Output 2" + default n + depends on STM32_HRTIM_TIMC_PWM + +config STM32_HRTIM_TIMC_BURST + bool "HRTIM TIMC Burst" + default n + depends on (STM32_HRTIM_BURST && STM32_HRTIM_TIMC_PWM) + +config STM32_HRTIM_TIMC_BURST_CH1 + bool "HRTIM TIMC Output 1 Burst Mode" + default n + depends on (STM32_HRTIM_TIMC_BURST && STM32_HRTIM_TIMC_PWM_CH1) + +config STM32_HRTIM_TIMC_BURST_CH2 + bool "HRTIM TIMC Output 2 Burst Mode" + default n + depends on (STM32_HRTIM_TIMC_BURST && STM32_HRTIM_TIMC_PWM_CH2) + +config STM32_HRTIM_TIMC_CHOP + bool "HRTIM TIMC PWM Chopper" + default n + depends on (STM32_HRTIM_CHOPPER && STM32_HRTIM_TIMC_PWM) + +config STM32_HRTIM_TIMC_DT + bool "HRTIM TIMC PWM Dead-time" + default n + depends on (STM32_HRTIM_DEADTIME && STM32_HRTIM_TIMC_PWM) + +config STM32_HRTIM_TIMC_PSHPLL + bool "HRTIM TIMC PWM Push-pull mode" + default n + depends on (STM32_HRTIM_PUSHPULL && STM32_HRTIM_TIMC_PWM) + +endmenu # "HRTIM Timer C Configuration" + +menu "HRTIM Timer D Configuration" + depends on STM32_HRTIM_TIMD + +config STM32_HRTIM_TIMD_CAP + bool "HRTIM TIMD Capture" + default n + depends on STM32_HRTIM_CAPTURE + +config STM32_HRTIM_TIMD_DAC + bool "HRTIM TIMD DAC Triggering" + default n + depends on STM32_HRTIM_DAC + +config STM32_HRTIM_TIMD_DMA + bool "HRTIM TIMD DMA" + default n + depends on STM32_HRTIM_DMA + +config STM32_HRTIM_TIMD_IRQ + bool "HRTIM TIMD Interrupts" + default n + depends on STM32_HRTIM_INTERRUPTS + +config STM32_HRTIM_TIMD_PWM + bool "HRTIM TIMD PWM Outputs" + default n + depends on STM32_HRTIM_PWM + +config STM32_HRTIM_TIMD_PWM_CH1 + bool "HRTIM TIMD PWM Output 1" + default n + depends on STM32_HRTIM_TIMD_PWM + +config STM32_HRTIM_TIMD_PWM_CH2 + bool "HRTIM TIMD PWM Output 2" + default n + depends on STM32_HRTIM_TIMD_PWM + +config STM32_HRTIM_TIMD_BURST + bool "HRTIM TIMD Burst" + default n + depends on (STM32_HRTIM_BURST && STM32_HRTIM_TIMD_PWM) + +config STM32_HRTIM_TIMD_BURST_CH1 + bool "HRTIM TIMD Output 1 Burst Mode" + default n + depends on (STM32_HRTIM_TIMD_BURST && STM32_HRTIM_TIMD_PWM_CH1) + +config STM32_HRTIM_TIMD_BURST_CH2 + bool "HRTIM TIMD Output 2 Burst Mode" + default n + depends on (STM32_HRTIM_TIMD_BURST && STM32_HRTIM_TIMD_PWM_CH2) + +config STM32_HRTIM_TIMD_CHOP + bool "HRTIM TIMD PWM Chopper" + default n + depends on (STM32_HRTIM_CHOPPER && STM32_HRTIM_TIMD_PWM) + +config STM32_HRTIM_TIMD_DT + bool "HRTIM TIMD PWM Dead-time" + default n + depends on (STM32_HRTIM_DEADTIME && STM32_HRTIM_TIMD_PWM) + +config STM32_HRTIM_TIMD_PSHPLL + bool "HRTIM TIMD PWM Push-pull mode" + default n + depends on (STM32_HRTIM_PUSHPULL && STM32_HRTIM_TIMD_PWM) + +endmenu # "HRTIM Timer D Configuration" + +menu "HRTIM Timer E Configuration" + depends on STM32_HRTIM_TIME + +config STM32_HRTIM_TIME_CAP + bool "HRTIM TIME Capture" + default n + depends on STM32_HRTIM_CAPTURE + +config STM32_HRTIM_TIME_DAC + bool "HRTIM TIME DAC Triggering" + default n + depends on STM32_HRTIM_DAC + +config STM32_HRTIM_TIME_DMA + bool "HRTIM TIME DMA" + default n + depends on STM32_HRTIM_DMA + +config STM32_HRTIM_TIME_IRQ + bool "HRTIM TIME Interrupts" + default n + depends on STM32_HRTIM_INTERRUPTS + +config STM32_HRTIM_TIME_PWM + bool "HRTIM TIME PWM Outputs" + default n + depends on STM32_HRTIM_PWM + +config STM32_HRTIM_TIME_PWM_CH1 + bool "HRTIM TIME PWM Output 1" + default n + depends on STM32_HRTIM_TIME_PWM + +config STM32_HRTIM_TIME_PWM_CH2 + bool "HRTIM TIME PWM Output 2" + default n + depends on STM32_HRTIM_TIME_PWM + +config STM32_HRTIM_TIME_BURST + bool "HRTIM TIME Burst" + default n + depends on (STM32_HRTIM_BURST && STM32_HRTIM_TIME_PWM) + +config STM32_HRTIM_TIME_BURST_CH1 + bool "HRTIM TIME Output 1 Burst Mode" + default n + depends on (STM32_HRTIM_TIME_BURST && STM32_HRTIM_TIME_PWM_CH1) + +config STM32_HRTIM_TIME_BURST_CH2 + bool "HRTIM TIME Output 2 Burst Mode" + default n + depends on (STM32_HRTIM_TIME_BURST && STM32_HRTIM_TIME_PWM_CH2) + +config STM32_HRTIM_TIME_CHOP + bool "HRTIM TIME PWM Chopper" + default n + depends on (STM32_HRTIM_CHOPPER && STM32_HRTIM_TIME_PWM) + +config STM32_HRTIM_TIME_DT + bool "HRTIM TIME PWM Dead-time" + default n + depends on (STM32_HRTIM_DEADTIME && STM32_HRTIM_TIME_PWM) + +config STM32_HRTIM_TIME_PSHPLL + bool "HRTIM TIME PWM Push-pull mode" + default n + depends on (STM32_HRTIM_PUSHPULL && STM32_HRTIM_TIME_PWM) + +endmenu # "HRTIM Timer E Configuration" diff --git a/arch/arm/src/common/stm32/Kconfig.i2c b/arch/arm/src/common/stm32/Kconfig.i2c new file mode 100644 index 0000000000000..5f698da0f2ea2 --- /dev/null +++ b/arch/arm/src/common/stm32/Kconfig.i2c @@ -0,0 +1,309 @@ +# +# STM32 common I2C options. +# + +# STM32 I2C configuration options. + +config STM32_I2C_SLAVE + bool + default n + +menu "I2C Configuration" + depends on STM32_HAVE_I2C_H5 && STM32_I2C + +menu "Clock Selection" + +choice + depends on STM32_I2C1 + prompt "I2C1 Input Clock Selection" + default STM32_I2C1_CLK_PCLK1 + +config STM32_I2C1_CLK_CSI + bool "CSI" + +config STM32_I2C1_CLK_HSI + bool "HSI" + +config STM32_I2C1_CLK_PCLK1 + bool "PCLK1" + +config STM32_I2C1_CLK_PLL3R + bool "PLL3R" + +endchoice # I2C1 Input Clock Selection + +choice + depends on STM32_I2C2 + prompt "I2C2 Input Clock Selection" + default STM32_I2C2_CLK_PCLK1 + +config STM32_I2C2_CLK_CSI + bool "CSI" + +config STM32_I2C2_CLK_HSI + bool "HSI" + +config STM32_I2C2_CLK_PCLK1 + bool "PCLK1" + +config STM32_I2C2_CLK_PLL3R + bool "PLL3R" + +endchoice # I2C2 Input Clock Selection + +choice + depends on STM32_I2C3 + prompt "I2C3 Input Clock Selection" + default STM32_I2C3_CLK_PCLK3 + +config STM32_I2C3_CLK_CSI + bool "CSI" + +config STM32_I2C3_CLK_HSI + bool "HSI" + +config STM32_I2C3_CLK_PCLK3 + bool "PCLK3" + +config STM32_I2C3_CLK_PLL3R + bool "PLL3R" + +endchoice # I2C3 Input Clock Selection + +choice + depends on STM32_I2C4 + prompt "I2C4 Input Clock Selection" + default STM32_I2C4_CLK_PCLK3 + +config STM32_I2C4_CLK_CSI + bool "CSI" + +config STM32_I2C4_CLK_HSI + bool "HSI" + +config STM32_I2C4_CLK_PCLK3 + bool "PCLK3" + +config STM32_I2C4_CLK_PLL3R + bool "PLL3R" + +endchoice # I2C4 Input Clock Selection + +endmenu # Clock Selection + +menu "Rise/Fall Override" + +config STM32_I2C1_RF_OVERRIDE + bool "I2C1" + default n + depends on STM32_I2C1 + +config STM32_I2C2_RF_OVERRIDE + bool "I2C2" + default n + depends on STM32_I2C2 + +config STM32_I2C3_RF_OVERRIDE + bool "I2C3" + default n + depends on STM32_I2C3 + +config STM32_I2C4_RF_OVERRIDE + bool "I2C4" + default n + depends on STM32_I2C4 + +menu "Rise/Fall Values" + +config STM32_I2C1_RISE + int "I2C1 Rise Time (ns)" + range 0 1000 + default 20 + depends on STM32_I2C1_RF_OVERRIDE + +config STM32_I2C1_FALL + int "I2C1 Fall Time (ns)" + range 0 300 + default 20 + depends on STM32_I2C1_RF_OVERRIDE + +config STM32_I2C2_RISE + int "I2C2 Rise Time (ns)" + range 0 1000 + default 20 + depends on STM32_I2C2_RF_OVERRIDE + +config STM32_I2C2_FALL + int "I2C2 Fall Time (ns)" + range 0 300 + default 20 + depends on STM32_I2C2_RF_OVERRIDE + +config STM32_I2C3_RISE + int "I2C3 Rise Time (ns)" + range 0 1000 + default 20 + depends on STM32_I2C3_RF_OVERRIDE + +config STM32_I2C3_FALL + int "I2C3 Fall Time (ns)" + range 0 300 + default 20 + depends on STM32_I2C3_RF_OVERRIDE + +config STM32_I2C4_RISE + int "I2C4 Rise Time (ns)" + range 0 1000 + default 20 + depends on STM32_I2C4_RF_OVERRIDE + +config STM32_I2C4_FALL + int "I2C4 Fall Time (ns)" + range 0 300 + default 20 + depends on STM32_I2C4_RF_OVERRIDE + +endmenu # Rise/Fall Values + +endmenu # Rise/Fall Override + +menu "Filtering" + +menu "Digital Filters" + +config STM32_I2C1_DNF + int "I2C1 Digital Noise Filter" + range 0 15 + default 0 + depends on STM32_I2C1 + +config STM32_I2C2_DNF + int "I2C2 Digital Noise Filter" + range 0 15 + default 0 + depends on STM32_I2C2 + +config STM32_I2C3_DNF + int "I2C3 Digital Noise Filter" + range 0 15 + default 0 + depends on STM32_I2C3 + +config STM32_I2C4_DNF + int "I2C4 Digital Noise Filter" + range 0 15 + default 0 + depends on STM32_I2C4 + +endmenu # Digital Filters + +menu "Analog Filters" + +config STM32_I2C1_ANFOFF + int "Turn off I2C1 Analog Filter (0=on, 1=off)" + default 1 + range 0 1 + depends on STM32_I2C1 + +config STM32_I2C2_ANFOFF + int "Turn off I2C2 Analog Filter (0=on, 1=off)" + default 1 + range 0 1 + depends on STM32_I2C2 + +config STM32_I2C3_ANFOFF + int "Turn off I2C3 Analog Filter (0=on, 1=off)" + default 1 + range 0 1 + depends on STM32_I2C3 + +config STM32_I2C4_ANFOFF + int "Turn off I2C4 Analog Filter (0=on, 1=off)" + default 1 + range 0 1 + depends on STM32_I2C4 + +endmenu # Analog Filters + +endmenu # Filtering + +endmenu # "I2C Configuration" + +config STM32_I2C_DYNTIMEO + bool "Use dynamic timeouts" + depends on STM32_I2C + +config STM32_I2C_DYNTIMEO_USECPERBYTE + int "Timeout Microseconds per Byte" + depends on STM32_I2C && STM32_I2C_DYNTIMEO + default 500 + +config STM32_I2C_DYNTIMEO_STARTSTOP + int "Timeout for Start/Stop (Milliseconds)" + depends on STM32_I2C && STM32_I2C_DYNTIMEO + default 1000 + +config STM32_I2CTIMEOSEC + int "Timeout seconds" + depends on STM32_I2C + default 0 + +config STM32_I2CTIMEOMS + int "Timeout Milliseconds" + depends on STM32_I2C && !STM32_I2C_DYNTIMEO + default 500 + +config STM32_I2CTIMEOTICKS + int "Timeout for Done and Stop (ticks)" + depends on STM32_I2C && !STM32_I2C_DYNTIMEO + default 500 + +config STM32_I2C_ALT + bool "Alternate I2C implementation" + default STM32F1_PERFORMANCELINE + depends on !STM32_STM32F30XX && STM32_COMMON_LEGACY + ---help--- + This selection enables an alternative I2C driver. This alternate + driver implements some rather complex workarounds for errata against + the STM32 F103 "Performance Line". This selection is an option + because: (1) It has not yet been fully verified and (2) It is not + certain that he scope of this workaround is needed only for the F103. + +config STM32_I2C_DUTY16_9 + bool "Frequency with Tlow/Thigh = 16/9" + default n + depends on STM32_I2C && STM32_COMMON_LEGACY + +config STM32_I2C_DMA + bool "I2C DMA Support" + default n + depends on STM32_I2C && STM32_STM32F4XXX && STM32_DMA1 && !I2C_POLLED + ---help--- + This option enables the DMA for I2C transfers. + Note: The user can define CONFIG_I2C_DMAPRIO: a custom priority value for the + I2C dma streams, else the default priority level is set to medium. + +menu "I2C Slave Configuration" + depends on STM32_I2C_SLAVE + +config STM32_I2C_SLAVE_DEFAULT_TX + hex "Default TX byte to be sent when the TX buffer is empty" + default 0xFF + +config STM32_I2C_SLAVE_USEWQ + bool "Use work queue to delegate the isr completion status" + default n + ---help--- + With the current upperhalf I2C slave driver implementation, the user + should delegate the callback completion status using a work queue. + However, work queues introduce a delay, so in certain scenarios + it is better to use a custom driver without using a work queue. + +config STM32_I2C_SLAVE_RETRANSFER + bool "The frame is retransferred when stop is issued beforehand" + default n + ---help--- + If stop is issued before the whole frame is transferred, + the tx pointer is reset to 0. + +endmenu diff --git a/arch/arm/src/common/stm32/Kconfig.ipcc b/arch/arm/src/common/stm32/Kconfig.ipcc new file mode 100644 index 0000000000000..da34bba96d277 --- /dev/null +++ b/arch/arm/src/common/stm32/Kconfig.ipcc @@ -0,0 +1,91 @@ +# +# STM32 common IPCC options. +# + +config STM32_IPCC_CHAN1_RX_SIZE + int "Channel 1 RX size" + default 256 + depends on STM32_IPCC + ---help--- + Size of the receive buffer. Another CPU will write to this buffer and + the currently running CPU will read from it. + +config STM32_IPCC_CHAN1_TX_SIZE + int "Channel 1 TX size" + default 256 + depends on STM32_IPCC + ---help--- + Size of the send buffer. Another CPU will read from this buffer and + the currently running CPU will write to it. + +config STM32_IPCC_CHAN2 + bool "Enable channel 2" + depends on STM32_IPCC + +if STM32_IPCC_CHAN2 + +config STM32_IPCC_CHAN2_RX_SIZE + int "Channel 2 RX size" + default 256 + +config STM32_IPCC_CHAN2_TX_SIZE + int "Channel 2 TX size" + default 256 + +config STM32_IPCC_CHAN3 + bool "Enable channel 3" + +if STM32_IPCC_CHAN3 + +config STM32_IPCC_CHAN3_RX_SIZE + int "Channel 3 RX size" + default 256 + +config STM32_IPCC_CHAN3_TX_SIZE + int "Channel 3 TX size" + default 256 + +config STM32_IPCC_CHAN4 + bool "Enable channel 4" + +if STM32_IPCC_CHAN4 + +config STM32_IPCC_CHAN4_RX_SIZE + int "Channel 4 RX size" + default 256 + +config STM32_IPCC_CHAN4_TX_SIZE + int "Channel 4 TX size" + default 256 + +config STM32_IPCC_CHAN5 + bool "Enable channel 5" + +if STM32_IPCC_CHAN5 + +config STM32_IPCC_CHAN5_RX_SIZE + int "Channel 5 RX size" + default 256 + +config STM32_IPCC_CHAN5_TX_SIZE + int "Channel 5 TX size" + default 256 + +config STM32_IPCC_CHAN6 + bool "Enable channel 6" + +if STM32_IPCC_CHAN6 + +config STM32_IPCC_CHAN6_RX_SIZE + int "Channel 6 RX size" + default 256 + +config STM32_IPCC_CHAN6_TX_SIZE + int "Channel 6 TX size" + default 256 + +endif # STM32_IPCC_CHAN2 +endif # STM32_IPCC_CHAN3 +endif # STM32_IPCC_CHAN4 +endif # STM32_IPCC_CHAN5 +endif # STM32_IPCC_CHAN6 diff --git a/arch/arm/src/common/stm32/Kconfig.lpuart b/arch/arm/src/common/stm32/Kconfig.lpuart new file mode 100644 index 0000000000000..a0df333349769 --- /dev/null +++ b/arch/arm/src/common/stm32/Kconfig.lpuart @@ -0,0 +1,70 @@ +# +# STM32 common LPUART options. +# + +config LPUART1_RXDMA + bool + depends on STM32_LPUART1 && LPUART1_SERIALDRIVER + depends on STM32_HAVE_IP_USART && STM32_DMA1 || STM32_COMMON_L4_L5_U5 && (STM32_DMA1 || STM32_DMA2 || STM32_DMAMUX) || ARCH_CHIP_STM32H5 && (STM32_DMA1 || STM32_DMA2) || ARCH_CHIP_STM32WB && STM32_DMA + ---help--- + In high data rate usage, Rx DMA may eliminate Rx overrun errors + +choice + prompt "LPUART1 Driver Configuration" + depends on STM32_LPUART1 + default STM32_LPUART1_SERIALDRIVER + +config STM32_LPUART1_SERIALDRIVER + bool "Standard serial driver" + select LPUART1_SERIALDRIVER + select ARCH_HAVE_SERIAL_TERMIOS + select STM32_SERIALDRIVER + +config STM32_LPUART1_1WIREDRIVER + bool "1-Wire driver" + select STM32_1WIREDRIVER + +endchoice # LPUART1 Driver Configuration + +config LPUART1_RS485 + bool "RS-485 on LPUART1" + depends on STM32_LPUART1 && LPUART1_SERIALDRIVER + ---help--- + Enable RS-485 interface on LPUART1. Your board config will have to + provide GPIO_LPUART1_RS485_DIR pin definition. Currently it cannot be + used with LPUART1_RXDMA. + +if LPUART1_RS485 + +config LPUART1_RS485_DIR_POLARITY + int "LPUART1 RS-485 DIR pin polarity" + default 1 + range 0 1 + ---help--- + Polarity of DIR pin for RS-485 on LPUART1. Set to state on DIR pin which + enables TX (0 - low / nTXEN, 1 - high / TXEN). + +endif # LPUART1_RS485 + +if STM32_LPUART1_SERIALDRIVER + +config LPUART1_TXDMA + bool "LPUART1 Tx DMA" + default n + depends on STM32_DMA1 + ---help--- + In high data rate usage, Tx DMA may reduce CPU load + +endif # STM32_LPUART1_SERIALDRIVER + +config LPUART1_UNCONFIG_RX_ON_CLOSE + bool "Unconfigure LPUART1 RX pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && LPUART1_SERIALDRIVER + +config LPUART1_UNCONFIG_TX_ON_CLOSE + bool "Unconfigure LPUART1 TX pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && LPUART1_SERIALDRIVER + +config LPUART1_UNCONFIG_DIR_ON_CLOSE + bool "Unconfigure LPUART1 DIR pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && LPUART1_SERIALDRIVER && LPUART1_RS485 diff --git a/arch/arm/src/common/stm32/Kconfig.ltdc b/arch/arm/src/common/stm32/Kconfig.ltdc new file mode 100644 index 0000000000000..064c9270e722e --- /dev/null +++ b/arch/arm/src/common/stm32/Kconfig.ltdc @@ -0,0 +1,235 @@ +# +# STM32 common LTDC options. +# + +choice + prompt "Layer 1 color format" + depends on STM32_LTDC + default STM32_LTDC_L1_RGB565 + +config STM32_LTDC_L1_L8 + bool "8 bpp L8 (8-bit CLUT)" + depends on STM32_FB_CMAP + +config STM32_LTDC_L1_AL44 + bool "8 bpp AL44 (4-bit alpha + 4-bit CLUT)" + depends on STM32_FB_CMAP + +config STM32_LTDC_L1_AL88 + bool "16 bpp AL88 (8-bit alpha + 8-bit CLUT)" + depends on STM32_FB_CMAP + +config STM32_LTDC_L1_RGB565 + bool "16 bpp RGB 565" + depends on !STM32_FB_CMAP + +config STM32_LTDC_L1_ARGB4444 + bool "16 bpp ARGB 4444" + depends on !STM32_FB_CMAP + +config STM32_LTDC_L1_ARGB1555 + bool "16 bpp ARGB 1555" + depends on !STM32_FB_CMAP + +config STM32_LTDC_L1_RGB888 + bool "24 bpp RGB 888" + depends on !STM32_FB_CMAP + +config STM32_LTDC_L1_ARGB8888 + bool "32 bpp ARGB 8888" + depends on !STM32_FB_CMAP + +endchoice # Layer 1 color format + +choice + prompt "Layer 2 (top layer) color format" + depends on STM32_LTDC && STM32_LTDC_L2 + default STM32_LTDC_L2_RGB565 + +config STM32_LTDC_L2_L8 + bool "8 bpp L8 (8-bit CLUT)" + depends on STM32_LTDC_L1_L8 + +config STM32_LTDC_L2_AL44 + bool "8 bpp AL44 (4-bit alpha + 4-bit CLUT)" + depends on STM32_LTDC_L1_AL44 + +config STM32_LTDC_L2_AL88 + bool "16 bpp AL88 (8-bit alpha + 8-bit CLUT)" + depends on STM32_LTDC_L1_AL88 + +config STM32_LTDC_L2_RGB565 + bool "16 bpp RGB 565" + depends on STM32_LTDC_L1_RGB565 + +config STM32_LTDC_L2_ARGB4444 + bool "16 bpp ARGB 4444" + depends on STM32_LTDC_L1_ARGB4444 + +config STM32_LTDC_L2_ARGB1555 + bool "16 bpp ARGB 1555" + depends on STM32_LTDC_L1_ARGB1555 + +config STM32_LTDC_L2_RGB888 + bool "24 bpp RGB 888" + depends on STM32_LTDC_L1_RGB888 + +config STM32_LTDC_L2_ARGB8888 + bool "32 bpp ARGB 8888" + depends on STM32_LTDC_L1_ARGB8888 + +endchoice # Layer 2 color format + +if STM32_LTDC + +config STM32_LTDC_BACKLIGHT + bool "Backlight support" + default y + +config STM32_LTDC_DEFBACKLIGHT + hex "Default backlight level" + default 0xf0 + +config STM32_LTDC_BACKCOLOR + hex "Background color" + default 0x0 + ---help--- + This is the background color that will be used as the LTDC + background layer color. It is an RGB888 format value. + +config STM32_LTDC_DITHER + bool "Dither support" + +config STM32_LTDC_FB_DOUBLE_BUFFER + bool "Enable double buffering" + depends on ARCH_CHIP_STM32H7 + default n + ---help--- + Enable double buffering to allow updates to the framebuffer while + the display is being refreshed. This configuration requires two + framebuffers: one active and one inactive. When the display + refreshes, the active and inactive framebuffers are swapped, + enabling smooth and flicker-free updates. + +if STM32_LTDC_DITHER + +config STM32_LTDC_DITHER_RED + int "Dither red width" + range 0 7 + default 2 + ---help--- + This is the dither red width. + +config STM32_LTDC_DITHER_GREEN + int "Dither green width" + range 0 7 + default 2 + ---help--- + This is the dither green width. + +config STM32_LTDC_DITHER_BLUE + int "Dither blue width" + range 0 7 + default 2 + ---help--- + This is the dither blue width. + +endif # STM32_LTDC_DITHER + +config STM32_LTDC_FB_BASE + hex "Framebuffer memory start address" + default 0 + ---help--- + If you are using the LTDC, then you must provide the address + of the start of the framebuffer. This address will typically + be in the SRAM or SDRAM memory region of the FSMC/FMC. + +config STM32_LTDC_FB_SIZE + int "Framebuffer memory size (bytes)" + default 0 + ---help--- + Must be the whole size of the active LTDC layer. + +config STM32_LTDC_L1_CHROMAKEYEN + bool "Enable chromakey support for layer 1" + default y + +config STM32_LTDC_L1_CHROMAKEY + hex "Layer L1 initial chroma key" + default 0x00000000 + +config STM32_LTDC_L1_COLOR + hex "Layer L1 default color" + default 0x00000000 + +config STM32_LTDC_L2 + bool "Enable Layer 2 support" + default y + +if STM32_LTDC_L2 + +config STM32_LTDC_L2_COLOR + hex "Layer L2 default color" + default 0x00000000 + +config STM32_LTDC_L2_CHROMAKEYEN + bool "Enable chromakey support for layer 2" + default y + +config STM32_LTDC_L2_CHROMAKEY + hex "Layer L2 initial chroma key" + default 0x00000000 + +endif # STM32_LTDC_L2 + +config STM32_FB_CMAP + bool "Color map support" + default y + select FB_CMAP + ---help--- + Enabling color map support is necessary for LTDC L8 format. + +config STM32_FB_TRANSPARENCY + bool "Transparency color map support" + depends on STM32_FB_CMAP + default y + select FB_TRANSPARENCY + ---help--- + Enabling transparency color map support is necessary for LTDC L8 format. + +config STM32_LTDC_REGDEBUG + bool "LTDC Register level debug" + depends on (STM32_COMMON_LEGACY && DEBUG_INFO && DEBUG_LCD) || STM32_COMMON_F7_H7 + ---help--- + Output detailed register-level LTDC device debug information. + +endif # STM32_LTDC + +config STM32_LTDC_USE_DSI + bool "Use DSI as display connection" + depends on STM32_COMMON_F7_H7 && STM32_LTDC && STM32_DSIHOST + ---help--- + Select this if your display is connected via DSI. + Deselect option if your display is connected via digital + RGB+HSYNC+VSYNC + +# +# + +if STM32_LCD + +choice + prompt "Segment LCD Clock Source" + default LCD_LSECLOCK + +config LCD_LSICLOCK + bool "Internal Low Speed Clock" + +config LCD_LSECLOCK + bool "External Low Speed Clock" + +config LCD_HSECLOCK + bool "External High Speed Clock" + +endchoice +endif # STM32_LCD diff --git a/arch/arm/src/common/stm32/Kconfig.memory b/arch/arm/src/common/stm32/Kconfig.memory new file mode 100644 index 0000000000000..fdd9e013223c5 --- /dev/null +++ b/arch/arm/src/common/stm32/Kconfig.memory @@ -0,0 +1,171 @@ +# +# STM32 common MEMORY options. +# + +# STM32 memory and SD/MMC configuration options. + +config STM32_SRAM5_HEAP + bool "SRAM5 is used for heap" + depends on STM32_SRAM5 + default n + +config STM32_EXTERNAL_RAM + bool "External RAM on FSMC/FMC" + depends on (STM32_COMMON_LEGACY && (STM32_FSMC || STM32_FMC)) || (ARCH_CHIP_STM32F7 && STM32_FMC) + select ARCH_HAVE_HEAP2 if STM32_COMMON_LEGACY && (STM32_FSMC || STM32_FMC) + select ARCH_HAVE_HEAP2 if ARCH_CHIP_STM32F7 && STM32_FMC + ---help--- + In addition to internal SRAM, external RAM may be available through the FSMC/FMC. + +config STM32_BBSRAM_FILES + int "Max Files to support in BBSRAM" + depends on STM32_COMMON_LEGACY && STM32_BKPSRAM || STM32_COMMON_F7_H7 && STM32_BKPSRAM && STM32_BBSRAM + default 4 + +config STM32_SAVE_CRASHDUMP + bool "Enable Saving Panic to BBSRAM" + depends on STM32_COMMON_LEGACY && STM32_BKPSRAM || STM32_COMMON_F7_H7 && STM32_BKPSRAM && STM32_BBSRAM + +config STM32_DTCMEXCLUDE + bool "Exclude DTCM SRAM from the heap" + depends on STM32_COMMON_F7_H7 && ARMV7M_HAVE_DTCM + default LIBC_ARCH_ELF + ---help--- + Exclude DTCM SRAM from the HEAP because it appears to be impossible + to execute ELF modules from DTCM RAM (REVISIT!). + +config STM32_DTCM_PROCFS + bool "DTCM SRAM PROCFS support" + depends on STM32_COMMON_F7_H7 && ARMV7M_DTCM && FS_PROCFS + ---help--- + Select to build in support for /proc/dtcm. Reading from /proc/dtcm + will provide statistics about DTCM memory use similar to what you + would get from mallinfo() for the user heap. + +config STM32_SRAM2_HEAP + bool "SRAM2 is used for heap" + depends on STM32_COMMON_SRAM2_OPTIONS + select STM32_SRAM2_INIT if !ARCH_CHIP_STM32U5 || STM32_SRAM2 + ---help--- + The STM32L4 SRAM2 region has special properties (power, protection, parity) + which may be used by the application for special purposes. But if these + special properties are not needed, it may be instead added to the heap for + use by malloc(). + NOTE: you must also select an appropriate number of memory regions in the + 'Memory Management' section. + +config STM32_SRAM2_INIT + bool "SRAM2 is initialized to zero" + depends on STM32_COMMON_SRAM2_OPTIONS + ---help--- + The STM32L4 SRAM2 region has parity checking. However, when the system + powers on, the memory is in an unknown state, and reads from uninitialized + memory can trigger parity faults from the random data. This can be + avoided by first writing to all locations to force the parity into a valid + state. + However, if the SRAM2 is being used for it's battery-backed capability, + this may be undesirable (because it will destroy the contents). In that + case, the board should handle the initialization itself at the appropriate + time. + +config STM32_SRAM3_HEAP + bool "SRAM3 is used for heap" + depends on (ARCH_CHIP_STM32L4 && STM32_STM32L4XR) || (ARCH_CHIP_STM32U5 && STM32_SRAM3) + default y if ARCH_CHIP_STM32L4 && STM32_STM32L4XR + ---help--- + Add the STM32L4 SRAM3 to the heap for use by malloc(). + NOTE: you must also select an appropriate number of memory regions in the + 'Memory Management' section. + +config STM32_CCMEXCLUDE + bool "Exclude CCM SRAM from the heap" + default ARCH_DMA || LIBC_ARCH_ELF + depends on STM32_HAVE_CCM + ---help--- + Exclude CCM SRAM from the HEAP because (1) it cannot be used for DMA + and (2) it appears to be impossible to execute ELF modules from CCM + RAM. + +config STM32_CCM_PROCFS + bool "CCM PROCFS support" + default n + depends on !DISABLE_MOUNTPOINT && FS_PROCFS && FS_PROCFS_REGISTER + ---help--- + Select to build in support for /proc/ccm. Reading from /proc/ccm + will provide statistics about CCM memory use similar to what you + would get from mallinfo() for the user heap. + +comment "STM32WB SRAM2a and SRAM2b Options" + depends on STM32_HAVE_SRAM2A || STM32_HAVE_SRAM2B + +config STM32_SRAM2A_HEAP + bool "SRAM2a is used for heap" + depends on STM32_HAVE_SRAM2A + default n + +config STM32_SRAM2A_USER_BASE_OFFSET + int "SRAM2a user application base offset" + default 2048 + range 0 32768 + depends on STM32_SRAM2A_HEAP + ---help--- + The beginning part of the SRAM2a memory can be used by RF stack. The + available space for the user application can be obtained from the + release notes for STM32WB coprocessor wireless binaries. + +config STM32_SRAM2A_USER_SIZE + int "SRAM2a user application size" + default 8192 + range 0 32768 + depends on STM32_SRAM2A_HEAP + ---help--- + The ending part of the SRAM2a memory contains a secure section, which + cannot be read nor written by CPU1. The secure start address for the + SRAM2a memory can be read from the SBRSA option byte. When CPU2 update + support required, there must be some free sectors just below the secure + memory to support CPU2 firmware updates requiring more sectors to be + secure. + +config STM32_SRAM2A_INIT + bool "SRAM2a is initialized to zero" + default y + depends on STM32_SRAM2A_HEAP + ---help--- + The STM32WB SRAM2a region has parity checking. However, when the system + powers on, the memory is in an unknown state, and reads from uninitialized + memory can trigger parity faults from the random data. This can be + avoided by first writing to all locations to force the parity into a valid + state. + However, if the SRAM2a is being retained in Standby mode, this may be + undesirable (because it will destroy the contents). In that case, the board + should handle the initialization itself at the appropriate time. + +config STM32_SRAM2B_HEAP + bool "SRAM2b is used for heap" + depends on STM32_HAVE_SRAM2B + default n + +config STM32_SRAM2B_USER_SIZE + int "SRAM2b user application size" + default 32768 + range 0 32768 + depends on STM32_SRAM2B_HEAP + ---help--- + For any CPU2 firmware supporting the BLE protocol the ending part of + the SRAM2b memory contains a secure section, which cannot be read nor + written by CPU1. The secure start address for the SRAM2b memory can be + read from the SNBRSA option byte. When CPU2 update support required, + there must be some free sectors just below the secure memory to support + CPU2 firmware updates requiring more sectors to be secure. The SRAM2b + memory is all secure for any CPU2 firmware supporting the Thread protocol. + +config STM32_SRAM2B_INIT + bool "SRAM2b is initialized to zero" + default y + depends on STM32_SRAM2B_HEAP + ---help--- + The STM32WB SRAM2b region has parity checking. However, when the system + powers on, the memory is in an unknown state, and reads from uninitialized + memory can trigger parity faults from the random data. This can be + avoided by first writing to all locations to force the parity into a valid + state. diff --git a/arch/arm/src/common/stm32/Kconfig.periph b/arch/arm/src/common/stm32/Kconfig.periph new file mode 100644 index 0000000000000..1098aed2cf295 --- /dev/null +++ b/arch/arm/src/common/stm32/Kconfig.periph @@ -0,0 +1,1283 @@ +# +# STM32 common peripheral selection options. +# + +menu "STM32 Peripheral Support" + +# hidden selectors + +config STM32_OPAMP + bool + depends on STM32_HAVE_IP_OPAMP_M3M4_V1 + select STM32_SYSCFG + +config STM32_COMP + bool + depends on STM32_HAVE_COMP + select STM32_SYSCFG + select COMP if ARCH_CHIP_STM32L4 && STM32_HAVE_COMP + +# peripheral enable selectors (set by the instance selections below) + +config STM32_ADC + bool + +config STM32_SDADC + bool + default n + +config STM32_CAN + bool + +config STM32_FDCAN + bool + select NET_CAN_HAVE_ERRORS if ARCH_CHIP_STM32H7 + select NET_CAN_HAVE_CANFD if ARCH_CHIP_STM32H7 + select NET_CAN_EXTID if ARCH_CHIP_STM32H7 + select NET_CAN_HAVE_TX_DEADLINE if ARCH_CHIP_STM32H7 + +config STM32_DAC + bool + +config STM32_DMA + bool + select STM32_DMAMUX if ARCH_CHIP_STM32L4 && STM32_HAVE_DMAMUX + select STM32_DMAMUX if ARCH_CHIP_STM32WB + +config STM32_DMAMUX + bool + +config STM32_I2C + bool + +config STM32_SPI + bool + +config STM32_TIM + bool + +config STM32_LPTIM + bool + +config STM32_HRTIM + bool + +config STM32_USART + bool + +config STM32_SERIALDRIVER + bool + +config STM32_SAI + bool + +config STM32_I2S + bool + select STM32_SPI_DMA if STM32_COMMON_LEGACY + select STM32_SPI_DMA if ARCH_CHIP_STM32F7 + +config STM32_SDMMC + bool + +config STM32_DFSDM + bool + default n + +config STM32_MBOX + bool + depends on STM32_HAVE_MBOX + default n + select STM32_IPCC + +# DMA peripherals + +config STM32_MDMA + bool "MDMA" + default n + depends on STM32_HAVE_MDMA && EXPERIMENTAL + select STM32_DMA + select ARCH_DMA + +config STM32_BDMA + bool "BDMA" + default n + depends on STM32_HAVE_BDMA && EXPERIMENTAL + select STM32_DMA + select ARCH_DMA + +config STM32_GPADMA1 + depends on STM32_HAVE_GPADMA1 + bool "GPADMA1" + default n + +config STM32_LPDMA1 + depends on STM32_HAVE_LPDMA1 + bool "LPDMA1" + default n + +config STM32_DMA1 + bool "DMA1" + depends on STM32_HAVE_DMA1 + select STM32_DMA + select ARCH_DMA + select STM32_DMAMUX1 if ARCH_CHIP_STM32L4 && STM32_HAVE_DMAMUX + +config STM32_DMA2 + bool "DMA2" + depends on STM32_HAVE_DMA2 + select STM32_DMA + select ARCH_DMA + select STM32_DMAMUX1 if ARCH_CHIP_STM32L4 && STM32_HAVE_DMAMUX + +config STM32_DMAMUX1 + bool "DMAMUX1" + depends on STM32_HAVE_DMAMUX + select STM32_DMAMUX + +config STM32_DMA2D + bool "DMA2D" + depends on STM32_HAVE_DMA2D + select FB if STM32_COMMON_LEGACY && STM32_STM32F429 || ARCH_CHIP_STM32F7 && STM32_HAVE_DMA2D + select FB_OVERLAY if STM32_COMMON_LEGACY && STM32_STM32F429 || ARCH_CHIP_STM32F7 && STM32_HAVE_DMA2D + ---help--- + The STM32 DMA2D is an Chrom-Art Accelerator for image manipulation + available on the STM32F429 and STM32F439 devices. + +# CLOCK peripherals + +config STM32_CSI + bool "CSI Low-speed internal oscillator (4MHz)" + depends on STM32_HAVE_CSI + default n + +config STM32_HSI48 + bool "HSI48 High-speed 48MHz internal oscillator" + depends on STM32_HAVE_HSI48 + default n + +config STM32_CRS + bool "CRS (Clock Recovery System)" + depends on STM32_HAVE_CRS + +# POWER peripherals + +config STM32_VREF + depends on STM32_HAVE_VREF + bool "VREF" + default n + +config STM32_BKPSRAM + bool "Enable BKP RAM Domain" + depends on STM32_COMMON_LEGACY && (STM32_STM32F20XX || STM32_STM32F4XXX) || STM32_COMMON_F0_L0_G0_C0 || STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32U5 + select STM32_PWR if ARCH_CHIP_STM32H7 + +config STM32_VREFINT + bool "Enable VREFINT" + depends on STM32_HAVE_VREFINT + +config STM32_PWR + bool "PWR" + depends on STM32_COMMON_LEGACY || (STM32_COMMON_F0_L0_G0_C0 && !ARCH_CHIP_STM32C0) || STM32_COMMON_F7_H7 || STM32_COMMON_L4_L5_U5 || ARCH_CHIP_STM32WB + +# MEMORY peripherals + +config STM32_RAMCFG + depends on STM32_HAVE_RAMCFG + bool "RAMCFG" + default n + +config STM32_SRAM1 + depends on STM32_HAVE_SRAM1 + bool "SRAM1" + default y + +config STM32_SRAM2 + depends on STM32_HAVE_SRAM2 + bool "SRAM2" + default n + +config STM32_SRAM3 + bool "SRAM3" + default n + depends on STM32_HAVE_SRAM3 && (STM32_STM32U575XX || STM32_STM32U585XX || STM32_STM32U59XX || STM32_STM32U59AXX || \ + STM32_STM32U5A5XX || STM32_STM32U5A9XX) + +config STM32_SRAM5 + bool "SRAM5" + default n + depends on STM32_HAVE_SRAM5 && (STM32_STM32U575XX || STM32_STM32U585XX || STM32_STM32U59XX || STM32_STM32U59AXX || \ + STM32_STM32U5A5XX || STM32_STM32U5A9XX) + +config STM32_BKP + bool "BKP" + depends on (STM32_COMMON_LEGACY && STM32_STM32F10XX) || STM32_COMMON_F0_L0_G0_C0 + +config STM32_FSMC + bool "FSMC" + depends on STM32_HAVE_FSMC + +config STM32_FMC + bool "FMC" + depends on STM32_HAVE_FMC + ---help--- + Enable Flexible Memory Controller. + To correctly configure FMC for your hardware, you will have to define + a number of macros in your board.h file. See stm32_fmc.c for directions. + +config STM32_BBSRAM + bool "BBSRAM File Support" + depends on (STM32_COMMON_LEGACY || STM32_COMMON_F7_H7) && STM32_BKPSRAM + select ARM_MPU if ARCH_CHIP_STM32H7 && STM32_BKPSRAM + +config STM32_CCMDATARAM + bool "CMD/DATA RAM" + default n + depends on STM32_STM32F4XXX + +# FLASH peripherals + +config STM32_FLASH + depends on STM32_HAVE_FLASH + bool "FLASH" + default n + +# GPIO peripherals + +config STM32_LPGPIO1 + depends on STM32_HAVE_LPGPIO1 + bool "LPGPIO1" + default n + +config STM32_SYSCFG + bool "SYSCFG" + depends on STM32_HAVE_SYSCFG + default y + +# SECURITY peripherals + +config STM32_FIREWALL + bool "FIREWALL" + default y + depends on STM32_HAVE_FIREWALL && STM32_SYSCFG + +config STM32_GTZC1 + depends on STM32_HAVE_GTZC1 + bool "GTZC1" + default n + +config STM32_GTZC2 + depends on STM32_HAVE_GTZC2 + bool "GTZC2" + default n + +config STM32_PKA + depends on STM32_HAVE_PKA + bool "PKA" + default n + +config STM32_SAES + depends on STM32_HAVE_SAES + bool "SAES" + default n + +config STM32_OTFDEC1 + depends on STM32_HAVE_OTFDEC1 + bool "OTFDEC1" + default n + +config STM32_OTFDEC2 + depends on STM32_HAVE_OTFDEC2 + bool "OTFDEC2" + default n + +config STM32_CRC + bool "CRC" + depends on STM32_COMMON_LEGACY || STM32_COMMON_F0_L0_G0_C0 || STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32U5 || ARCH_CHIP_STM32WB + +config STM32_AES + bool "128-bit AES" + depends on STM32_HAVE_IP_AES_M0_V1 || STM32_HAVE_IP_AES_M3M4_V1 + select CRYPTO_AES192_DISABLE if (STM32_COMMON_LEGACY && STM32_HAVE_AES) && CRYPTO_ALGTEST + select CRYPTO_AES256_DISABLE if (STM32_COMMON_LEGACY && STM32_HAVE_AES) && CRYPTO_ALGTEST + select CRYPTO_AES192_DISABLE if (STM32_COMMON_F0_L0_G0_C0 && STM32_HAVE_AES) && CRYPTO_ALGTEST + select CRYPTO_AES256_DISABLE if (STM32_COMMON_F0_L0_G0_C0 && STM32_HAVE_AES) && CRYPTO_ALGTEST + +config STM32_CRYP + bool "CRYP" + depends on STM32_HAVE_CRYP + depends on STM32_HAVE_IP_CRYPTO_M3M4_V1 || STM32_HAVE_IP_CRYPTO_H7 + +config STM32_HASH + bool "HASH" + depends on STM32_HAVE_HASH + select ARCH_HAVE_HASH if ARCH_CHIP_STM32F7 && STM32_HAVE_HASH + +# BLE peripherals + +menuconfig STM32_BLE + bool "BLE" + depends on STM32_HAVE_BLE + default n + select STM32_MBOX + ---help--- + Enable BLE support. + +# CACHE peripherals + +config STM32_ICACHE + bool "ICACHE" + default n + depends on STM32_HAVE_ICACHE + +config STM32_DCACHE1 + depends on STM32_HAVE_DCACHE1 + bool "DCACHE1" + default n + +# RTC peripherals + +config STM32_RTCAPB + depends on STM32_HAVE_RTCAPB + bool "RTCAPB" + default n + +config STM32_RTC + bool "RTC" + depends on STM32_COMMON_LEGACY || STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32L5 || ARCH_CHIP_STM32WB + select RTC if !ARCH_CHIP_STM32L5 + +# RNG peripherals + +config STM32_RNG + bool "RNG" + depends on STM32_HAVE_RNG + select ARCH_HAVE_RNG if !ARCH_CHIP_STM32U5 + +# WDG peripherals + +config STM32_IWDG + bool "IWDG" + depends on STM32_HAVE_IP_WDG_M0_V1 || STM32_HAVE_IP_WDG_M3M4_V1 + select WATCHDOG + +config STM32_WWDG + bool "WWDG" + depends on STM32_HAVE_IP_WDG_M0_V1 || STM32_HAVE_IP_WDG_M3M4_V1 + select WATCHDOG if !ARCH_CHIP_STM32U5 + +# ADC peripherals + +config STM32_ADC1 + bool "ADC1" + depends on (STM32_HAVE_IP_ADC_M3M4_V1 || STM32_HAVE_IP_ADC_M3M4_V2) || STM32_HAVE_IP_ADC_M0_V1 || STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5 || ARCH_CHIP_STM32U5 + select STM32_ADC if !ARCH_CHIP_STM32U5 + select STM32_ADC1_HAVE_DMA if (STM32_HAVE_IP_ADC_M3M4_V1 || STM32_HAVE_IP_ADC_M3M4_V2) && ((STM32_STM32F10XX || STM32_STM32F37XX) && STM32_DMA1 || !STM32_STM32F10XX && STM32_DMA2 || STM32_DMAMUX) + select STM32_ADC1_HAVE_DMA if ARCH_CHIP_STM32F7 && STM32_DMA2 + +config STM32_ADC2 + bool "ADC2" + depends on ((STM32_HAVE_IP_ADC_M3M4_V1 || STM32_HAVE_IP_ADC_M3M4_V2) || ARCH_CHIP_STM32L4) && STM32_HAVE_ADC2 || STM32_COMMON_F7_H7_H5 + select STM32_ADC + select STM32_ADC2_HAVE_DMA if (STM32_HAVE_IP_ADC_M3M4_V1 || STM32_HAVE_IP_ADC_M3M4_V2) && STM32_HAVE_ADC2 && (STM32_DMA2 || STM32_DMAMUX) + select STM32_ADC2_HAVE_DMA if ARCH_CHIP_STM32F7 && STM32_DMA2 + +config STM32_ADC3 + bool "ADC3" + depends on ((STM32_HAVE_IP_ADC_M3M4_V1 || STM32_HAVE_IP_ADC_M3M4_V2) || ARCH_CHIP_STM32L4) && STM32_HAVE_ADC3 || STM32_COMMON_F7_H7 + select STM32_ADC + select STM32_ADC3_HAVE_DMA if (STM32_HAVE_IP_ADC_M3M4_V1 || STM32_HAVE_IP_ADC_M3M4_V2) && STM32_HAVE_ADC3 && (STM32_DMA2 || STM32_DMAMUX) + select STM32_ADC3_HAVE_DMA if ARCH_CHIP_STM32F7 && STM32_DMA2 + +config STM32_ADC4 + bool "ADC4" + depends on ((STM32_HAVE_IP_ADC_M3M4_V1 || STM32_HAVE_IP_ADC_M3M4_V2) && STM32_HAVE_ADC4) || ARCH_CHIP_STM32U5 + select STM32_ADC if (STM32_HAVE_IP_ADC_M3M4_V1 || STM32_HAVE_IP_ADC_M3M4_V2) + select STM32_ADC4_HAVE_DMA if (STM32_HAVE_IP_ADC_M3M4_V1 || STM32_HAVE_IP_ADC_M3M4_V2) && STM32_HAVE_ADC4 && (STM32_DMA2 || STM32_DMAMUX) + +config STM32_ADC5 + bool "ADC5" + default n + select STM32_ADC + depends on STM32_HAVE_ADC5 + select STM32_ADC5_HAVE_DMA if STM32_DMA2 + select STM32_ADC5_HAVE_DMA if STM32_DMAMUX + +config STM32_SDADC1 + bool "SDADC1" + default n + select STM32_SDADC + depends on STM32_HAVE_SDADC1 + select STM32_SDADC1_HAVE_DMA if STM32_DMA2 + +config STM32_SDADC2 + bool "SDADC2" + default n + select STM32_SDADC + depends on STM32_HAVE_SDADC2 + select STM32_SDADC2_HAVE_DMA if STM32_DMA2 + +config STM32_SDADC3 + bool "SDADC3" + default n + select STM32_SDADC + depends on STM32_HAVE_SDADC3 + select STM32_SDADC3_HAVE_DMA if STM32_DMA2 + +# DAC peripherals + +config STM32_DAC1 + bool "DAC1" + depends on STM32_HAVE_DAC1 + select STM32_DAC if !ARCH_CHIP_STM32U5 + +config STM32_DAC2 + bool "DAC2" + depends on STM32_HAVE_DAC2 + select STM32_DAC + +config STM32_DAC1CH1 + bool "DAC1CH1" + default n + depends on STM32_DAC1 + +config STM32_DAC1CH2 + bool "DAC1CH2" + default n + depends on STM32_DAC1 + +config STM32_DAC2CH1 + bool "DAC2CH1" + default n + depends on STM32_DAC2 + +config STM32_DAC3 + bool "DAC3" + default n + depends on STM32_HAVE_DAC3 + select STM32_DAC + +config STM32_DAC3CH1 + bool "DAC3CH1 Internal" + default n + depends on STM32_DAC3 + +config STM32_DAC3CH2 + bool "DAC3CH2 Internal" + default n + depends on STM32_DAC3 + +config STM32_DAC4 + bool "DAC4" + default n + depends on STM32_HAVE_DAC4 + select STM32_DAC + +config STM32_DAC4CH1 + bool "DAC4CH1 Internal" + default n + depends on STM32_DAC4 + +config STM32_DAC4CH2 + bool "DAC4CH2 Internal" + default n + depends on STM32_DAC4 + +# DFSDM peripherals + +config STM32_MDF1 + depends on STM32_HAVE_MDF1 + bool "MDF1" + default n + +config STM32_ADF1 + depends on STM32_HAVE_ADF1 + bool "ADF1" + default n + +config STM32_DFSDM1 + bool "DFSDM1" + depends on (ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4) && STM32_HAVE_DFSDM1 + select ARCH_HAVE_DFSDM1 if ARCH_CHIP_STM32F7 && STM32_HAVE_DFSDM1 + +# CAN peripherals + +config STM32_CAN1 + bool "CAN1" + depends on STM32_HAVE_CAN1 + select STM32_CAN + select CAN + +config STM32_CAN2 + bool "CAN2" + depends on STM32_HAVE_CAN2 + select STM32_CAN + select CAN + +config STM32_CAN3 + bool "CAN3" + depends on STM32_HAVE_CAN3 + select STM32_CAN + select CAN + +config STM32_FDCAN1 + bool "FDCAN1" + depends on STM32_HAVE_FDCAN1 + select STM32_FDCAN if !ARCH_CHIP_STM32U5 + +config STM32_FDCAN2 + bool "FDCAN2" + depends on STM32_HAVE_FDCAN2 + select STM32_FDCAN + +config STM32_FDCAN3 + bool "FDCAN3" + depends on STM32_HAVE_FDCAN3 + select STM32_FDCAN + +# I2C peripherals + +config STM32_I2C5 + bool "I2C5" + depends on STM32_HAVE_I2C5 && (STM32_STM32U59XX || STM32_STM32U59AXX || STM32_STM32U5A5XX || STM32_STM32U5A9XX) + default n + select STM32_I2C + +config STM32_I2C6 + bool "I2C6" + depends on STM32_HAVE_I2C6 && (STM32_STM32U59XX || STM32_STM32U59AXX || STM32_STM32U5A5XX || STM32_STM32U5A9XX) + default n + select STM32_I2C + +config STM32_I2C1 + bool "I2C1" + depends on STM32_HAVE_I2C1 + select STM32_I2C + select I2C if ARCH_CHIP_STM32WB + +config STM32_I2C2 + bool "I2C2" + depends on STM32_HAVE_I2C2 + select STM32_I2C + +config STM32_I2C3 + bool "I2C3" + depends on STM32_HAVE_I2C3 + select STM32_I2C + select I2C if ARCH_CHIP_STM32WB && STM32_HAVE_I2C3 + +config STM32_I2C4 + bool "I2C4" + depends on STM32_HAVE_I2C4 + select STM32_I2C + +# +# + +config STM32_I2C1_SLAVE + bool "I2C1 Slave" + default n + depends on !STM32_I2C1 && I2C_SLAVE + select STM32_I2C_SLAVE + +config STM32_I2C2_SLAVE + bool "I2C2 Slave" + default n + depends on STM32_HAVE_I2C2 && !STM32_I2C2 && I2C_SLAVE + select STM32_I2C_SLAVE + +config STM32_I2C3_SLAVE + bool "I2C3 Slave" + default n + depends on STM32_HAVE_I2C3 && !STM32_I2C3 && I2C_SLAVE + select STM32_I2C_SLAVE + +# SPI peripherals + +config STM32_SPI1 + bool "SPI1" + depends on STM32_HAVE_SPI1 + select SPI if !ARCH_CHIP_STM32WL5 + select STM32_SPI + +config STM32_SPI2 + bool "SPI2" + depends on STM32_HAVE_SPI2 + select SPI + select STM32_SPI + +config STM32_SPI3 + bool "SPI3" + depends on STM32_HAVE_SPI3 + select SPI + select STM32_SPI + +config STM32_SPI4 + bool "SPI4" + depends on STM32_HAVE_SPI4 + select SPI + select STM32_SPI + +config STM32_SPI5 + bool "SPI5" + depends on STM32_HAVE_SPI5 + select SPI + select STM32_SPI + +config STM32_SPI6 + bool "SPI6" + depends on STM32_HAVE_SPI6 + select SPI + select STM32_SPI + +# SERIAL peripherals + +config STM32_UART9 + bool "UART9" + default n + depends on STM32_HAVE_UART9 + select ARCH_HAVE_SERIAL_TERMIOS + select STM32_USART + +config STM32_UART12 + bool "UART12" + default n + depends on STM32_HAVE_UART12 + select ARCH_HAVE_SERIAL_TERMIOS + select STM32_USART + +config STM32_USART10 + bool "USART10" + default n + depends on STM32_HAVE_USART10 + select ARCH_HAVE_SERIAL_TERMIOS + select STM32_USART + +config STM32_USART11 + bool "USART11" + default n + depends on STM32_HAVE_USART11 + select ARCH_HAVE_SERIAL_TERMIOS + select STM32_USART + +config STM32_SWPMI + bool "SWPMI" + depends on STM32_HAVE_SWPMI + default n + +config STM32_LPUART1 + bool "LPUART1" + depends on STM32_HAVE_LPUART1 + select LPUART1_SERIALDRIVER if ARCH_CHIP_STM32L4 && STM32_HAVE_LPUART1 + select STM32_USART + select ARCH_HAVE_SERIAL_TERMIOS if !STM32_HAVE_IP_USART + select ARCH_HAVE_LPUART1 if ARCH_CHIP_STM32L4 && STM32_HAVE_LPUART1 || ARCH_CHIP_STM32WB && STM32_HAVE_LPUART + +config STM32_USART4 + bool "USART4" + depends on STM32_HAVE_USART4 + select STM32_USART + +config STM32_USART5 + bool "USART5" + depends on STM32_HAVE_USART5 + select STM32_USART + +config STM32_USART7 + bool "USART7" + depends on STM32_HAVE_USART7 + select STM32_USART + +config STM32_USART8 + bool "USART8" + depends on STM32_HAVE_USART8 + select STM32_USART + +config STM32_USART1 + bool "USART1" + depends on STM32_HAVE_USART1 + select STM32_USART + select ARCH_HAVE_SERIAL_TERMIOS if !STM32_HAVE_IP_USART + select USART1_SERIALDRIVER if STM32_COMMON_F7_H7 + +config STM32_USART2 + bool "USART2" + depends on STM32_HAVE_USART2 + select STM32_USART + select ARCH_HAVE_SERIAL_TERMIOS if !STM32_HAVE_IP_USART + select USART2_SERIALDRIVER if STM32_COMMON_F7_H7 + +config STM32_USART3 + bool "USART3" + depends on STM32_HAVE_USART3 + select STM32_USART + select ARCH_HAVE_SERIAL_TERMIOS if !STM32_HAVE_IP_USART + select USART3_SERIALDRIVER if STM32_COMMON_F7_H7 + +config STM32_UART4 + bool "UART4" + depends on STM32_HAVE_UART4 + select STM32_USART + select ARCH_HAVE_SERIAL_TERMIOS if !STM32_HAVE_IP_USART + select UART4_SERIALDRIVER if STM32_COMMON_F7_H7 + +config STM32_UART5 + bool "UART5" + depends on STM32_HAVE_UART5 + select STM32_USART + select ARCH_HAVE_SERIAL_TERMIOS if !STM32_HAVE_IP_USART + select UART5_SERIALDRIVER if STM32_COMMON_F7_H7 + +config STM32_USART6 + bool "USART6" + depends on STM32_HAVE_USART6 + select STM32_USART + select ARCH_HAVE_SERIAL_TERMIOS if !STM32_HAVE_IP_USART + select USART6_SERIALDRIVER if STM32_COMMON_F7_H7 + +config STM32_UART7 + bool "UART7" + depends on STM32_HAVE_UART7 + select STM32_USART + select ARCH_HAVE_SERIAL_TERMIOS if !STM32_HAVE_IP_USART + select UART7_SERIALDRIVER if STM32_COMMON_F7_H7 + +config STM32_UART8 + bool "UART8" + depends on STM32_HAVE_UART8 + select STM32_USART + select ARCH_HAVE_SERIAL_TERMIOS if !STM32_HAVE_IP_USART + select UART8_SERIALDRIVER if STM32_COMMON_F7_H7 + +# TIM peripherals + +config STM32_LPTIM1 + bool "LPTIM1" + depends on STM32_HAVE_LPTIM1 + select STM32_LPTIM if ARCH_CHIP_STM32H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32WB + +config STM32_TIM1 + bool "TIM1" + depends on STM32_HAVE_TIM1 + select STM32_TIM + +config STM32_TIM2 + bool "TIM2" + depends on STM32_HAVE_TIM2 + select STM32_TIM + +config STM32_TIM3 + bool "TIM3" + depends on STM32_HAVE_TIM3 + select STM32_TIM + +config STM32_TIM4 + bool "TIM4" + depends on STM32_HAVE_TIM4 + select STM32_TIM + +config STM32_TIM5 + bool "TIM5" + depends on STM32_HAVE_TIM5 + select STM32_TIM + +config STM32_TIM6 + bool "TIM6" + depends on STM32_HAVE_TIM6 + select STM32_TIM + +config STM32_TIM7 + bool "TIM7" + depends on STM32_HAVE_TIM7 + select STM32_TIM + +config STM32_TIM8 + bool "TIM8" + depends on STM32_HAVE_TIM8 + select STM32_TIM + +config STM32_TIM9 + bool "TIM9" + depends on STM32_HAVE_TIM9 + select STM32_TIM + +config STM32_TIM10 + bool "TIM10" + depends on STM32_HAVE_TIM10 + select STM32_TIM + +config STM32_TIM11 + bool "TIM11" + depends on STM32_HAVE_TIM11 + select STM32_TIM + +config STM32_TIM12 + bool "TIM12" + depends on STM32_HAVE_TIM12 + select STM32_TIM + +config STM32_TIM13 + bool "TIM13" + depends on STM32_HAVE_TIM13 + select STM32_TIM + +config STM32_TIM14 + bool "TIM14" + depends on STM32_HAVE_TIM14 + select STM32_TIM + +config STM32_TIM15 + bool "TIM15" + depends on STM32_HAVE_TIM15 + select STM32_TIM + +config STM32_TIM16 + bool "TIM16" + depends on STM32_HAVE_TIM16 + select STM32_TIM + +config STM32_TIM17 + bool "TIM17" + depends on STM32_HAVE_TIM17 + select STM32_TIM + +config STM32_LPTIM2 + bool "LPTIM2" + depends on ARCH_CHIP_STM32H7 || ARCH_CHIP_STM32U5 || ARCH_CHIP_STM32WB || ARCH_CHIP_STM32L4 && STM32_HAVE_LPTIM2 + select STM32_LPTIM if ARCH_CHIP_STM32H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32WB + +config STM32_LPTIM3 + bool "LPTIM3" + depends on ARCH_CHIP_STM32H7 || ARCH_CHIP_STM32U5 + select STM32_LPTIM if ARCH_CHIP_STM32H7 + +config STM32_LPTIM4 + bool "LPTIM4" + depends on ARCH_CHIP_STM32H7 || ARCH_CHIP_STM32U5 + select STM32_LPTIM if ARCH_CHIP_STM32H7 + +config STM32_LPTIM5 + bool "LPTIM5" + depends on ARCH_CHIP_STM32H7 + select STM32_LPTIM + +config STM32_HRTIM1 + bool "HRTIM1" + default n + depends on STM32_HAVE_HRTIM1 + select STM32_HRTIM + +config STM32_HRTIM_MASTER + bool "HRTIM MASTER" + default n + depends on STM32_HRTIM1 + ---help--- + Enable HRTIM Master Timer + +config STM32_HRTIM_TIMA + bool "HRTIM TIMA" + default n + depends on STM32_HRTIM1 + ---help--- + Enable HRTIM Timer A + +config STM32_HRTIM_TIMB + bool "HRTIM TIMB" + default n + depends on STM32_HRTIM1 + ---help--- + Enable HRTIM Timer B + +config STM32_HRTIM_TIMC + bool "HRTIM TIMC" + default n + depends on STM32_HRTIM1 + ---help--- + Enable HRTIM Timer C + +config STM32_HRTIM_TIMD + bool "HRTIM TIMD" + default n + depends on STM32_HRTIM1 + ---help--- + Enable HRTIM Timer D + +config STM32_HRTIM_TIME + bool "HRTIM TIME" + default n + depends on STM32_HRTIM1 + ---help--- + Enable HRTIM Timer E + +# USB peripherals + +choice STM32_USBFS_MODE + prompt "USB FS Mode" + depends on STM32_HAVE_USBFS_MODE && STM32_HAVE_USBFS + default STM32_USBFS_NONE + ---help--- + Select the operating mode for the USB_DRD_FS peripheral. + The hardware supports Device or Host, but not simultaneously. + +config STM32_USBFS_NONE + bool "Disabled" + +config STM32_USBFS_DEVICE + bool "USB Device" + select STM32_USBFS + select USBDEV + +config STM32_USBFS_HOST + bool "USB Host" + select USBHOST_HAVE_ASYNCH + select USBHOST + ---help--- + Enable USB host mode for USB_DRD_FS peripheral. + +endchoice + +config STM32_OTGFS + bool "OTG FS" + depends on STM32_HAVE_OTGFS + select USBHOST_HAVE_ASYNCH if !ARCH_CHIP_STM32U5 && USBHOST + +config STM32_OTGHS + bool "OTG HS" + depends on (STM32_COMMON_LEGACY && (STM32_STM32F20XX || STM32_STM32F4XXX)) || (ARCH_CHIP_STM32H7 && EXPERIMENTAL) || (ARCH_CHIP_STM32U5 && (STM32_STM32U59XX || STM32_STM32U59AXX || STM32_STM32U5A5XX || STM32_STM32U5A9XX)) + select USBHOST_HAVE_ASYNCH if !ARCH_CHIP_STM32U5 && USBHOST + +config STM32_OTGFSHS + bool "OTG FS/HS" + depends on ARCH_CHIP_STM32F7 + default n + select USBHOST_HAVE_ASYNCH if USBHOST + +config STM32_USB + bool "USB Device" + depends on STM32_HAVE_USBDEV + select USBDEV + +config STM32_USBFS + bool "USB Full Speed Device" + depends on STM32_HAVE_USBFS + select USBDEV + select USBDEV if STM32_COMMON_LEGACY || ARCH_CHIP_STM32L4 + +config STM32_USBHOST + bool "Enable USB Host Support" + depends on STM32_COMMON_LEGACY && (STM32_OTGFS || STM32_OTGHS) + default n + select USBHOST + +config STM32_UCPD + bool "UCPD (USB Type C Power Delivery)" + default n + depends on STM32_HAVE_UCPD + select USBDEV + +config STM32_UCPD1 + depends on STM32_HAVE_UCPD1 + bool "UCPD1" + default n + +# CEC peripherals + +config STM32_CEC + bool "CEC" + depends on (STM32_COMMON_LEGACY && STM32F1_VALUELINE) || (STM32_COMMON_F0_L0_G0_C0 && STM32_HAVE_CEC) || ARCH_CHIP_STM32F7 + +# SDIO peripherals + +config STM32_SDIO + bool "SDIO" + depends on (STM32_COMMON_LEGACY && !STM32F1_CONNECTIVITYLINE && !STM32F1_VALUELINE) + select ARCH_HAVE_SDIO + select ARCH_HAVE_SDIOWAIT_WRCOMPLETE + select ARCH_HAVE_SDIO_PREFLIGHT + +config STM32_SDMMC1 + bool "SDMMC1" + depends on STM32_HAVE_SDMMC1 + select STM32_SDMMC if !ARCH_CHIP_STM32U5 + select ARCH_HAVE_SDIO if !ARCH_CHIP_STM32U5 + select ARCH_HAVE_SDIOWAIT_WRCOMPLETE if !ARCH_CHIP_STM32U5 + select ARCH_HAVE_SDIO_PREFLIGHT if !ARCH_CHIP_STM32U5 + select SDIO_BLOCKSETUP if STM32_COMMON_F7_H7 + select SCHED_HPWORK if ARCH_CHIP_STM32L4 + select STM32_SAI1PLL if ARCH_CHIP_STM32L4 + +config STM32_SDMMC2 + bool "SDMMC2" + depends on STM32_HAVE_SDMMC2 + select STM32_SDMMC if !ARCH_CHIP_STM32U5 + select ARCH_HAVE_SDIO if !ARCH_CHIP_STM32U5 + select ARCH_HAVE_SDIOWAIT_WRCOMPLETE if !ARCH_CHIP_STM32U5 + select ARCH_HAVE_SDIO_PREFLIGHT if !ARCH_CHIP_STM32U5 + select SDIO_BLOCKSETUP if !ARCH_CHIP_STM32U5 + +# SAI peripherals + +config STM32_SPDIFRX + bool "SPDIFRX" + depends on ARCH_CHIP_STM32F7 + +config STM32_I2S1 + bool "I2S1" + depends on ARCH_CHIP_STM32F7 && !STM32_SPI1 + select STM32_I2S + +config STM32_I2S2 + bool "I2S2" + depends on ARCH_CHIP_STM32F7 && !STM32_SPI2 + select STM32_I2S + +config STM32_I2S3 + bool "I2S3" + depends on STM32_HAVE_I2S3 + select I2S if STM32_COMMON_LEGACY + select STM32_I2S + +config STM32_SPI2S2 + bool "SPI2S2" + depends on STM32_HAVE_SPI2S2 + select STM32_SPI + +config STM32_SAI1 + bool "SAI1" + depends on STM32_HAVE_SAI1 + +config STM32_SAI1_A + bool "SAI1 Block A" + depends on (ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4) && STM32_SAI1 + select AUDIO + select I2S + select SCHED_HPWORK + select STM32_SAI + +config STM32_SAI1_B + bool "SAI1 Block B" + depends on (ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4) && STM32_SAI1 + select AUDIO + select I2S + select SCHED_HPWORK + select STM32_SAI + +config STM32_SAI2 + bool "SAI2" + depends on STM32_HAVE_SAI2 + +config STM32_SAI2_A + bool "SAI2 Block A" + depends on (ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4) && STM32_SAI2 + select AUDIO + select I2S + select SCHED_HPWORK + select STM32_SAI + +config STM32_SAI2_B + bool "SAI2 Block B" + depends on (ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4) && STM32_SAI2 + select AUDIO + select I2S + select SCHED_HPWORK + select STM32_SAI + +# QSPI peripherals + +config STM32_QSPI1 + bool "QSPI1" + depends on STM32_HAVE_QSPI1 + default n + +config STM32_OCTOSPIM + depends on STM32_HAVE_OCTOSPIM + bool "OCTOSPIM" + default n + +config STM32_OCTOSPI1 + depends on STM32_HAVE_OCTOSPI1 + bool "OCTOSPI1" + default n + +config STM32_OCTOSPI2 + depends on STM32_HAVE_OCTOSPI2 + bool "OCTOSPI2" + default n + +config STM32_QSPI + bool "QSPI (QUADSPI)" + depends on STM32_HAVE_QSPI || STM32_COMMON_F7_H7 + ---help--- + The STM32L4 QSPI block is intended to support one serial NOR flash device + +# ETH peripherals + +config STM32_ETHMAC + bool "Ethernet MAC" + depends on STM32_HAVE_ETHERNET + select NETDEVICES + select ARCH_HAVE_PHY + select STM32_PHY_HAVE_POLLED if !STM32_COMMON_LEGACY + +# CORDIC peripherals + +config STM32_CORDIC + bool "CORDIC Accelerator" + depends on STM32_HAVE_IP_CORDIC_M3M4_V1 && MATH_CORDIC_USE_Q31 + +config STM32_FMAC + bool "FMAC (Filter Math Accelerator)" + depends on STM32_HAVE_FMAC + +# SENSOR peripherals + +config STM32_DTS + bool "DTS" + depends on STM32_HAVE_DTS + default n + ---help--- + Enable support for the on‑die digital temperature sensor (DTS) + built into STM32H5 devices. When enabled, the driver will register + a `/dev/sensor_tempX` device using the common NuttX sensor framework. + +config STM32_DCMI_PSSI + depends on STM32_HAVE_DCMI_PSSI + bool "DCMI_PSSI" + default n + +config STM32_DCMI + bool "DCMI" + depends on STM32_HAVE_DCMI + ---help--- + The devices embed a camera interface that can connect with camera + modules and CMOS sensors through an 8-bit to 14-bit parallel interface, + to receive video data. + +config STM32_SYSCFG_IOCOMPENSATION + bool "SYSCFG I/O Compensation" + depends on STM32_HAVE_IOCOMPENSATION + select STM32_CSI if ARCH_CHIP_STM32H7 + ---help--- + By default the I/O compensation cell is not used. However when the I/O + output buffer speed is configured in 50 MHz or 100 MHz mode, it is + recommended to use the compensation cell for slew rate control on I/O + tf(IO)out)/tr(IO)out commutation to reduce the I/O noise on power supply. + + The I/O compensation cell can be used only when the supply voltage ranges + from 2.4 to 3.6 V. + +config STM32_JPEG + bool "JPEG" + depends on STM32_HAVE_JPEG + ---help--- + The JPEG codec provides a hardware compressor and decompressor of JPEG + images with full management of JPEG headers. + +config STM32_TSC + bool "TSC" + depends on STM32_HAVE_TSC + +config STM32_COMP1 + bool "COMP1" + select STM32_COMP + depends on STM32_HAVE_COMP1 + +config STM32_COMP2 + bool "COMP2" + select STM32_COMP + depends on STM32_HAVE_COMP2 + +config STM32_COMP3 + bool "COMP3" + default n + select STM32_COMP + depends on STM32_HAVE_COMP3 + +config STM32_COMP4 + bool "COMP4" + default n + select STM32_COMP + depends on STM32_HAVE_COMP4 + +config STM32_COMP5 + bool "COMP5" + default n + select STM32_COMP + depends on STM32_HAVE_COMP5 + +config STM32_COMP6 + bool "COMP6" + default n + select STM32_COMP + depends on STM32_HAVE_COMP6 + +config STM32_COMP7 + bool "COMP7" + default n + select STM32_COMP + depends on STM32_HAVE_COMP7 + +config STM32_OPAMP1 + bool "OPAMP1" + default n + select STM32_OPAMP + depends on STM32_HAVE_OPAMP1 + +config STM32_OPAMP2 + bool "OPAMP2" + default n + select STM32_OPAMP + depends on STM32_HAVE_OPAMP2 + +config STM32_OPAMP3 + bool "OPAMP3" + default n + select STM32_OPAMP + depends on STM32_HAVE_OPAMP3 + +config STM32_OPAMP4 + bool "OPAMP4" + default n + select STM32_OPAMP + depends on STM32_HAVE_OPAMP4 + +# IPCC peripherals + +config STM32_IPCC + bool "IPCC" + depends on ARCH_CHIP_STM32WB || ARCH_CHIP_STM32WL5 + select IPCC if ARCH_CHIP_STM32WL5 + ---help--- + IPCC - Inter Processor Communication Controller. A very simple + character device stream driver to exchange data between + CM0 and CM4. + +config STM32_HSEM + bool "Hardware semaphore" + depends on STM32_HAVE_HSEM + default n + +# Display peripherals + +config STM32_LCD + bool "Segment LCD" + depends on STM32_HAVE_LCD + select USBDEV if STM32_COMMON_F0_L0_G0_C0 && STM32_HAVE_LCD + +config STM32_DSIHOST + bool "DSIHOST" + depends on STM32_HAVE_DSIHOST + ---help--- + The DSI Host is a dedicated peripheral for interfacing with MIPI DSI + compliant displays. + +config STM32_LTDC + bool "LTDC" + depends on STM32_HAVE_LTDC + select FB + ---help--- + The STM32 LTDC is an LCD-TFT Display Controller available on + the STM32F429 and STM32F439 devices. It is a standard parallel + video interface (HSYNC, VSYNC, etc.) for controlling TFT + LCD displays. + +endmenu # STM32 Peripheral Support diff --git a/arch/arm/src/common/stm32/Kconfig.qspi b/arch/arm/src/common/stm32/Kconfig.qspi new file mode 100644 index 0000000000000..81e31aceca319 --- /dev/null +++ b/arch/arm/src/common/stm32/Kconfig.qspi @@ -0,0 +1,169 @@ +# +# STM32 common QSPI options. +# + +# STM32 QSPI/OCTOSPI configuration options. + +if STM32_HAVE_QSPI && (STM32_QSPI || STM32_QSPI1) + +choice + prompt "DMA Channel" + default STM32_QSPI_DMA_CHAN_1_5 + depends on STM32_DMA + ---help--- + You can choose between two DMA channels for use with QSPI: + either DMA1 channel 5, or DMA2 channel 7. + If you only see one choice here, it is probably because + you have not also enabled the associated DMA controller. + +config STM32_QSPI_DMA_CHAN_1_5 + bool "DMA1 Channel 5" + depends on STM32_DMA1 && !STM32_DMAMUX + ---help--- + Use DMA1 channel 5 for QSPI. + +config STM32_QSPI_DMA_CHAN_2_7 + bool "DMA2 Channel 7" + depends on STM32_DMA2 && !STM32_DMAMUX + ---help--- + Use DMA2 channel 7 for QSPI. + +endchoice + +endif + +choice + prompt "Transfer technique" + depends on STM32_QSPI || STM32_QSPI1 + default STM32_QSPI_DMA + ---help--- + You can choose between using polling, interrupts, or DMA to transfer data + over the QSPI interface. + +config STM32_QSPI_POLLING + bool "Polling" + ---help--- + Use conventional register I/O with status polling to transfer data. + +config STM32_QSPI_INTERRUPTS + bool "Interrupts" + ---help--- + User interrupt driven I/O transfers. + +config STM32_QSPI_DMA + bool "DMA" + depends on STM32_DMA + ---help--- + Use DMA to improve QSPI transfer performance. + +endchoice + +choice + prompt "Bank selection" + depends on STM32_QSPI || STM32_QSPI1 + default STM32_QSPI_MODE_BANK1 + ---help--- + You can choose between using polling, interrupts, or DMA to transfer data + over the QSPI interface. + +config STM32_QSPI_MODE_BANK1 + bool "Bank 1" + +config STM32_QSPI_MODE_BANK2 + bool "Bank 2" + +config STM32_QSPI_MODE_DUAL + bool "Dual Bank" + +endchoice + +choice + prompt "DMA Priority" + depends on (STM32_QSPI || STM32_QSPI1) && STM32_QSPI_DMA && STM32_DMA + default STM32_QSPI_DMAPRIORITY_MEDIUM + ---help--- + The DMA controller supports priority levels. You are probably fine + with the default of 'medium' except for special cases. In the event + of contention between to channels at the same priority, the lower + numbered channel has hardware priority over the higher numbered one. + +config STM32_QSPI_DMAPRIORITY_VERYHIGH + bool "Very High priority" + depends on STM32_DMA + ---help--- + 'Highest' priority. + +config STM32_QSPI_DMAPRIORITY_HIGH + bool "High priority" + depends on STM32_DMA + ---help--- + 'High' priority. + +config STM32_QSPI_DMAPRIORITY_MEDIUM + bool "Medium priority" + depends on STM32_DMA + ---help--- + 'Medium' priority. + +config STM32_QSPI_DMAPRIORITY_LOW + bool "Low priority" + depends on STM32_DMA + ---help--- + 'Low' priority. + +endchoice + +config STM32_QSPI_FLASH_SIZE + int "Size of attached serial flash, bytes" + depends on STM32_QSPI || STM32_QSPI1 + default 16777216 + range 1 2147483647 if ARCH_CHIP_STM32L4 && STM32_QSPI + range 1 2147483648 if STM32_COMMON_F7_H7 && STM32_QSPI || ARCH_CHIP_STM32H5 && STM32_QSPI1 + ---help--- + The STM32F7 QSPI peripheral requires the size of the Flash be specified + +config STM32_QSPI_FIFO_THESHOLD + int "Number of bytes before asserting FIFO threshold flag" + depends on STM32_QSPI || STM32_QSPI1 + default 4 + range 1 16 if STM32_COMMON_F7_H7 && STM32_QSPI || ARCH_CHIP_STM32L4 && STM32_QSPI + range 1 32 if ARCH_CHIP_STM32H5 && STM32_QSPI1 + ---help--- + The STM32F7 QSPI peripheral requires that the FIFO threshold be specified + I would leave it at the default value of 4 unless you know what you are doing. + +config STM32_QSPI_CSHT + int "Number of cycles Chip Select must be inactive between transactions" + depends on STM32_QSPI || STM32_QSPI1 + default 5 if ARCH_CHIP_STM32H5 && STM32_QSPI1 + default 1 + range 1 8 if STM32_COMMON_F7_H7 && STM32_QSPI || ARCH_CHIP_STM32L4 && STM32_QSPI + range 1 64 if ARCH_CHIP_STM32H5 && STM32_QSPI1 + ---help--- + The STM32F7 QSPI peripheral requires that it be specified the minimum number + of AHB cycles that Chip Select be held inactive between transactions. + +config STM32_QSPI_DMATHRESHOLD + int "QSPI DMA threshold" + depends on (STM32_QSPI || STM32_QSPI1) && STM32_QSPI_DMA + default 4 + ---help--- + When QSPI DMA is enabled, small DMA transfers will still be performed + by polling logic. This value is the threshold below which transfers + will still be performed by conventional register status polling. + +config STM32_QSPI_DMADEBUG + bool "QSPI DMA transfer debug" + depends on (STM32_QSPI || STM32_QSPI1) && STM32_QSPI_DMA && DEBUG_SPI && DEBUG_DMA + ---help--- + Enable special debug instrumentation to analyze QSPI DMA data transfers. + This logic is as non-invasive as possible: It samples DMA + registers at key points in the data transfer and then dumps all of + the registers at the end of the transfer. + +config STM32_QSPI_REGDEBUG + bool "QSPI Register level debug" + depends on STM32_COMMON_F7_H7 && STM32_QSPI && DEBUG_SPI_INFO || ARCH_CHIP_STM32L4 && STM32_QSPI && DEBUG_SPI_INFO || ARCH_CHIP_STM32H5 && STM32_QSPI1 && DEBUG_SPI_INFO + ---help--- + Output detailed register-level QSPI device debug information. + Requires also CONFIG_DEBUG_SPI_INFO. diff --git a/arch/arm/src/common/stm32/Kconfig.rtc b/arch/arm/src/common/stm32/Kconfig.rtc new file mode 100644 index 0000000000000..b81e79860077e --- /dev/null +++ b/arch/arm/src/common/stm32/Kconfig.rtc @@ -0,0 +1,93 @@ +# +# STM32 common RTC options. +# + +choice + prompt "RTC clock source" + depends on STM32_RTC + default STM32_RTC_LSECLOCK + +config STM32_RTC_LSECLOCK + bool "LSE clock" + ---help--- + Drive the RTC with the LSE clock + +config STM32_RTC_LSICLOCK + bool "LSI clock" + ---help--- + Drive the RTC with the LSI clock + +config STM32_RTC_HSECLOCK + bool "HSE clock" + ---help--- + Drive the RTC with the HSE clock, divided down to 1MHz. + +endchoice # RTC clock source + +config STM32_RTC_MAGIC_REG + int "BKP register" + depends on STM32_HAVE_RTC_MAGIC + default 0 + range 0 19 if STM32_COMMON_LEGACY && STM32_RTC && !STM32_HAVE_RTC_COUNTER + range 0 31 if STM32_HAVE_RTC_SUBSECONDS || ARCH_CHIP_STM32U5 + ---help--- + The BKP register used to store/check the Magic value to determine if + RTC is already setup + +config STM32_RTC_MAGIC + hex "RTC Magic 1" + depends on STM32_HAVE_RTC_MAGIC + default 0xfacefeed + ---help--- + Value used as Magic to determine if the RTC is already setup + +config STM32_RTC_MAGIC_TIME_SET + hex "RTC Magic 2" + depends on STM32_HAVE_RTC_MAGIC + default 0xf00dface + ---help--- + Value used as Magic to determine if the RTC has been setup and has + time set + +config STM32_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY + bool "Automatically boost the LSE oscillator drive capability level until it starts-up" + depends on (STM32_COMMON_F7_H7 || STM32_COMMON_L5_U5) && STM32_RTC && STM32_RTC_LSECLOCK + ---help--- + This will cycle through the values from low to high. To avoid + damaging the crystal. We want to use the lowest setting that gets + the OSC running. See app note AN2867 + + 0 = Low drive capability (default) + 1 = Medium high drive capability + 2 = Medium low drive capability + 3 = High drive capability + +config STM32_RTC_LSECLOCK_START_DRV_CAPABILITY + int "LSE oscillator drive capability level at LSE start-up" + depends on ((STM32_COMMON_F7_H7 || STM32_COMMON_L5_U5) && !STM32_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32WB) && STM32_RTC && STM32_RTC_LSECLOCK + default 0 + range 0 3 if ((STM32_COMMON_F7_H7 || STM32_COMMON_L5_U5) && !STM32_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY) || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32WB + ---help--- + 0 = Low drive capability (default) + 1 = Medium high drive capability + 2 = Medium low drive capability + 3 = High drive capability + +config STM32_RTC_LSECLOCK_RUN_DRV_CAPABILITY + int "LSE oscillator drive capability level after LSE start-up" + depends on ((STM32_COMMON_F7_H7 || STM32_COMMON_L5_U5) && !STM32_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32WB) && STM32_RTC && STM32_RTC_LSECLOCK && !STM32_COMMON_L5_U5 + default 0 + range 0 3 if ((STM32_COMMON_F7_H7 || STM32_COMMON_L5_U5) && !STM32_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY) || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32WB + ---help--- + 0 = Low drive capability (default) + 1 = Medium high drive capability + 2 = Medium low drive capability + 3 = High drive capability + +config STM32_RTC_LSECLOCK_LOWER_RUN_DRV_CAPABILITY + bool "Decrease LSE oscillator drive capability after LSE start-up" + depends on STM32_COMMON_L5_U5 && STM32_RTC && STM32_RTC_LSECLOCK && !STM32_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY + ---help--- + The LSE oscillator drive capability can remain at the level used + during LSE start-up at run-time, or it can be reduced to the + 'Low drive capability' once the LSE started up successfully. diff --git a/arch/arm/src/common/stm32/Kconfig.sai b/arch/arm/src/common/stm32/Kconfig.sai new file mode 100644 index 0000000000000..67a8c8ef710c4 --- /dev/null +++ b/arch/arm/src/common/stm32/Kconfig.sai @@ -0,0 +1,88 @@ +# +# STM32 common SAI options. +# + +choice + prompt "Operation mode" + depends on STM32_SAI + default STM32_SAI_DMA + ---help--- + Select the operation mode the SAI driver should use. + +config STM32_SAI_POLLING + bool "Polling" + ---help--- + The SAI registers are polled for events. + +config STM32_SAI_INTERRUPTS + bool "Interrupt" + ---help--- + Select to enable interrupt driven SAI support. + +config STM32_SAI_DMA + bool "DMA" + ---help--- + Use DMA to improve SAI transfer performance. + +endchoice # Operation mode + +choice + prompt "SAI1 synchronization enable" + depends on STM32_SAI1_A && STM32_SAI1_B + default STM32_SAI1_BOTH_ASYNC + ---help--- + Select the synchronization mode of the SAI sub-blocks + +config STM32_SAI1_BOTH_ASYNC + bool "Both asynchronous" + +config STM32_SAI1_A_SYNC_WITH_B + bool "Block A is synchronous with Block B" + +config STM32_SAI1_B_SYNC_WITH_A + bool "Block B is synchronous with Block A" + +endchoice # SAI1 synchronization enable + +choice + prompt "SAI2 synchronization enable" + depends on STM32_SAI2_A && STM32_SAI2_B + default STM32_SAI2_BOTH_ASYNC + ---help--- + Select the synchronization mode of the SAI sub-blocks + +config STM32_SAI2_BOTH_ASYNC + bool "Both asynchronous" + +config STM32_SAI2_A_SYNC_WITH_B + bool "Block A is synchronous with Block B" + +config STM32_SAI2_B_SYNC_WITH_A + bool "Block B is synchronous with Block A" + +endchoice # SAI2 synchronization enable + +config STM32_SAI1PLL + bool "SAI1PLL" + depends on STM32_COMMON_L4_L5_U5 + ---help--- + The STM32L4 has a separate PLL for the SAI1 block. + Set this true and provide configuration parameters in + board.h to use this PLL. + +config STM32_SAI2PLL + bool "SAI2PLL" + depends on STM32_COMMON_L4_L5_U5 && STM32_HAVE_SAI2 + ---help--- + The STM32L4 has a separate PLL for the SAI2 block. + Set this true and provide configuration parameters in + board.h to use this PLL. + +config STM32_SAIPLL + bool "SAIPLL" + default n + depends on STM32_HAVE_SAIPLL + ---help--- + The STM32F446 has a separate PLL for the SAI block. + Set this true and provide configuration parameters in + board.h to use this PLL. diff --git a/arch/arm/src/common/stm32/Kconfig.sdadc b/arch/arm/src/common/stm32/Kconfig.sdadc new file mode 100644 index 0000000000000..4053ae572b026 --- /dev/null +++ b/arch/arm/src/common/stm32/Kconfig.sdadc @@ -0,0 +1,42 @@ +# +# STM32 common SDADC options. +# + +# SDADC per-instance capability flags +# (hidden; driven by default y if / peripheral selects, never by chip selectors) + +config STM32_SDADC1_HAVE_DMA + bool + +config STM32_SDADC2_HAVE_DMA + bool + +config STM32_SDADC3_HAVE_DMA + bool + +config STM32_SDADC1_DMA + bool "SDADC1 DMA" + depends on STM32_SDADC1 && STM32_SDADC1_HAVE_DMA + default n + ---help--- + If DMA is selected, then the SDADC may be configured to support + DMA transfer, which is advisable if multiple channels are read + or if very high trigger frequencies are used. + +config STM32_SDADC2_DMA + bool "SDADC2 DMA" + depends on STM32_SDADC2 && STM32_SDADC2_HAVE_DMA + default n + ---help--- + If DMA is selected, then the SDADC may be configured to support + DMA transfer, which is advisable if multiple channels are read + or if very high trigger frequencies are used. + +config STM32_SDADC3_DMA + bool "SDADC3 DMA" + depends on STM32_SDADC3 && STM32_SDADC3_HAVE_DMA + default n + ---help--- + If DMA is selected, then the SDADC may be configured to support + DMA transfer, which is advisable if multiple channels are read + or if very high trigger frequencies are used. diff --git a/arch/arm/src/common/stm32/Kconfig.sdio b/arch/arm/src/common/stm32/Kconfig.sdio new file mode 100644 index 0000000000000..3bf834a69393e --- /dev/null +++ b/arch/arm/src/common/stm32/Kconfig.sdio @@ -0,0 +1,153 @@ +# +# STM32 common SDIO options. +# + +# SDMMC per-instance capability flags +# (hidden; driven by default y if / peripheral selects, never by chip selectors) + +config STM32_SDMMC2_HAVE_DMAPRIO + bool + default y if STM32_F7_PERIPHERALS + +config STM32_SDIO_CARD + bool "SDIO Card support" + depends on STM32_COMMON_LEGACY && STM32_SDIO + default n + ---help--- + Build in additional support needed only for SDIO cards (vs. SD + memory cards) + +config STM32_SDIO_PULLUP + bool "Enable internal Pull-Ups" + depends on STM32_COMMON_LEGACY && STM32_SDIO + default n + ---help--- + If you are using an external SDCard module that does not have the + pull-up resistors for the SDIO interface (like the Gadgeteer SD Card + Module) then enable this option to activate the internal pull-up + resistors. + +config STM32_SDIO_DMA + bool "Support DMA data transfers" + default STM32_DMA2 + select SDIO_DMA + depends on STM32_COMMON_LEGACY && STM32_SDIO + depends on STM32_DMA2 + ---help--- + Support DMA data transfers. Requires STM32_SDIO and config STM32_DMA2. + +config STM32_SDIO_DMAPRIO + hex "SDIO DMA priority" + default 0x00001000 if STM32_STM32F10XX + default 0x00010000 if !STM32_STM32F10XX + depends on STM32_COMMON_LEGACY && STM32_SDIO + ---help--- + Select SDIO DMA priority. + + For STM32 F1 family, options are: 0x00000000 low, 0x00001000 medium, + 0x00002000 high, 0x00003000 very high. Default: medium. + + For other STM32's, options are: 0x00000000 low, 0x00010000 medium, + 0x00020000 high, 0x00030000 very high. Default: medium. + +config STM32_SDIO_WIDTH_D1_ONLY + bool "Use D1 only" + depends on STM32_COMMON_LEGACY && STM32_SDIO + default n + ---help--- + Select 1-bit transfer mode. Default: 4-bit transfer mode. + +config STM32_SDMMC_IDMA + bool "Support IDMA data transfers" + depends on ARCH_CHIP_STM32H7 && STM32_SDMMC + default y + select SDIO_DMA + ---help--- + Support IDMA data transfers. + +if STM32_SDMMC + +config STM32_SDMMC_XFRDEBUG + bool "SDMMC transfer debug" + depends on DEBUG_FS_INFO + ---help--- + Enable special debug instrumentation analyze SDMMC data transfers. + This logic is as non-invasive as possible: It samples SDMMC + registers at key points in the data transfer and then dumps all of + the registers at the end of the transfer. If DEBUG_DMA is also + enabled, then DMA register will be collected as well. Requires also + DEBUG_FS and CONFIG_DEBUG_INFO. + +config STM32_SDMMC_DMA + bool "Support DMA data transfers" + depends on (ARCH_CHIP_STM32F7 || STM32_COMMON_L4_L5_U5) && STM32_SDMMC && STM32_DMA + select SDIO_DMA + ---help--- + Support DMA data transfers. + +config STM32_SDMMC1_DMAPRIO + hex "SDMMC1 DMA priority" + depends on (ARCH_CHIP_STM32F7 || STM32_COMMON_L4_L5_U5) && STM32_SDMMC1 + default 0x00010000 if ARCH_CHIP_STM32F7 + default 0x00001000 + ---help--- + Select SDMMC1 DMA priority. + + Options are: 0x00000000 low, 0x00010000 medium, + 0x00020000 high, 0x00030000 very high. Default: medium. + +config SDMMC1_WIDTH_D1_ONLY + bool "Use D1 only on SDMMC1" + depends on STM32_SDMMC1 + ---help--- + Select 1-bit transfer mode. Default: 4-bit transfer mode. + +config SDMMC1_SDIO_MODE + bool "SDIO Card Support" + depends on STM32_COMMON_F7_H7 && STM32_SDMMC && STM32_SDMMC1 + ---help--- + Build in additional support needed only for SDIO cards (vs. SD + memory cards) + +config SDMMC1_SDIO_PULLUP + bool "Enable internal Pull-Ups" + depends on STM32_COMMON_F7_H7 && STM32_SDMMC && STM32_SDMMC1 + ---help--- + If you are using an external SDCard module that does not have the + pull-up resistors for the SDIO interface (like the Gadgeteer SD Card + Module) then enable this option to activate the internal pull-up + resistors. + +config SDMMC2_WIDTH_D1_ONLY + bool "Use D1 only on SDMMC2" + depends on STM32_COMMON_F7_H7 && STM32_SDMMC && STM32_SDMMC2 + ---help--- + Select 1-bit transfer mode. Default: 4-bit transfer mode. + +config SDMMC2_SDIO_MODE + bool "SDIO Card Support" + depends on STM32_COMMON_F7_H7 && STM32_SDMMC && STM32_SDMMC2 + ---help--- + Build in additional support needed only for SDIO cards (vs. SD + memory cards) + +config SDMMC2_SDIO_PULLUP + bool "Enable internal Pull-Ups" + depends on STM32_COMMON_F7_H7 && STM32_SDMMC && STM32_SDMMC2 + ---help--- + If you are using an external SDCard module that does not have the + pull-up resistors for the SDIO interface (like the Gadgeteer SD Card + Module) then enable this option to activate the internal pull-up + resistors. + +config STM32_SDMMC2_DMAPRIO + hex "SDMMC2 DMA priority" + default 0x00010000 + depends on STM32_SDMMC2 && STM32_SDMMC2_HAVE_DMAPRIO + ---help--- + Select SDMMC2 DMA priority. + + Options are: 0x00000000 low, 0x00010000 medium, + 0x00020000 high, 0x00030000 very high. Default: medium. + +endif # STM32_SDMMC diff --git a/arch/arm/src/common/stm32/Kconfig.spi b/arch/arm/src/common/stm32/Kconfig.spi new file mode 100644 index 0000000000000..cf360f805c926 --- /dev/null +++ b/arch/arm/src/common/stm32/Kconfig.spi @@ -0,0 +1,300 @@ +# +# STM32 common SPI options. +# + +config STM32_SPI_DMA + bool + depends on STM32_HAVE_SPI_CORE_DMA + +config STM32_SPI_INTERRUPTS + bool "Interrupt driver SPI" + depends on STM32_SPI + depends on STM32_COMMON_FULL_FEATURED || ARCH_CHIP_STM32WL5 || ARCH_CHIP_STM32WB && (STM32_SPI1 || STM32_SPI2) + ---help--- + Select to enable interrupt driven SPI support. Non-interrupt-driven, + poll-waiting is recommended if the interrupt rate would be to high in + the interrupt driven case. + +config STM32_SPI1_DMA + bool "SPI1 DMA" + depends on STM32_SPI && STM32_SPI1 + depends on STM32_HAVE_SPI_DMA_FAMILY_WL5 && !STM32_SPI_INTERRUPT || STM32_COMMON_F0_L0_G0_C0 && !STM32_SPI_INTERRUPTS + select STM32_SPI_DMA + ---help--- + Use DMA to improve SPI1 transfer performance. Cannot be used with STM32_SPI_INTERRUPT. + +config STM32_SPI1_DMA_BUFFER + int "SPI1 DMA buffer size" + depends on (STM32_COMMON_LEGACY || STM32_COMMON_F7_H7_H5 || ARCH_CHIP_STM32WL5) && STM32_SPI1_DMA + default 0 + ---help--- + Add a properly aligned DMA buffer for RX and TX DMA for SPI1. + +config STM32_SPI_DMATHRESHOLD + int "SPI DMA threshold" + depends on (STM32_COMMON_LEGACY || STM32_COMMON_F7_H7_H5 || ARCH_CHIP_STM32WL5) && STM32_SPI_DMA + default 4 + ---help--- + When SPI DMA is enabled, small DMA transfers will still be performed + by polling logic. But we need a threshold value to determine what + is small. + +config STM32_SPI2_DMA + bool "SPI2 DMA" + depends on STM32_SPI && STM32_SPI2 + depends on STM32_HAVE_SPI_DMA_FAMILY && !STM32_SPI_INTERRUPT || STM32_COMMON_F0_L0_G0_C0 && !STM32_SPI_INTERRUPTS + select STM32_SPI_DMA + ---help--- + Use DMA to improve SPI2 transfer performance. Cannot be used with STM32_SPI_INTERRUPT. + +config STM32_SPI2_DMA_BUFFER + int "SPI2 DMA buffer size" + depends on (STM32_COMMON_LEGACY || STM32_COMMON_F7_H7_H5) && STM32_SPI2_DMA + default 0 + ---help--- + Add a properly aligned DMA buffer for RX and TX DMA for SPI2. + +config STM32_SPI3_DMA + bool "SPI3 DMA" + depends on STM32_SPI && STM32_SPI3 + depends on STM32_HAVE_SPI_DMA_FAMILY && !STM32_SPI_INTERRUPT || STM32_COMMON_F0_L0_G0_C0 && !STM32_SPI_INTERRUPTS + select STM32_SPI_DMA + ---help--- + Use DMA to improve SPI3 transfer performance. Cannot be used with STM32_SPI_INTERRUPT. + +config STM32_SPI3_DMA_BUFFER + int "SPI3 DMA buffer size" + depends on (STM32_COMMON_LEGACY || STM32_COMMON_F7_H7_H5) && STM32_SPI3_DMA + default 0 + ---help--- + Add a properly aligned DMA buffer for RX and TX DMA for SPI3. + +config STM32_SPI4_DMA + bool "SPI4 DMA" + depends on (STM32_COMMON_LEGACY || STM32_COMMON_F7_H7_H5) && STM32_SPI && STM32_SPI4 && !STM32_SPI_INTERRUPT + select STM32_SPI_DMA + ---help--- + Use DMA to improve SPI4 transfer performance. Cannot be used with STM32_SPI_INTERRUPT. + +config STM32_SPI4_DMA_BUFFER + int "SPI4 DMA buffer size" + depends on (STM32_COMMON_LEGACY || STM32_COMMON_F7_H7_H5) && STM32_SPI4_DMA + default 0 + ---help--- + Add a properly aligned DMA buffer for RX and TX DMA for SPI4. + +config STM32_SPI5_DMA + bool "SPI5 DMA" + depends on (STM32_COMMON_LEGACY || STM32_COMMON_F7_H7_H5) && STM32_SPI && STM32_SPI5 && !STM32_SPI_INTERRUPT + select STM32_SPI_DMA + ---help--- + Use DMA to improve SPI5 transfer performance. Cannot be used with STM32_SPI_INTERRUPT. + +config STM32_SPI5_DMA_BUFFER + int "SPI5 DMA buffer size" + depends on (STM32_COMMON_LEGACY || STM32_COMMON_F7_H7_H5) && STM32_SPI5_DMA + default 0 + ---help--- + Add a properly aligned DMA buffer for RX and TX DMA for SPI5. + +config STM32_SPI6_DMA + bool "SPI6 DMA" + depends on (STM32_COMMON_LEGACY || STM32_COMMON_F7_H7_H5) && STM32_SPI && STM32_SPI6 && !STM32_SPI_INTERRUPT + select STM32_SPI_DMA + ---help--- + Use DMA to improve SPI6 transfer performance. Cannot be used with STM32_SPI_INTERRUPT. + +config STM32_SPI1_COMMTYPE + int "SPI1 Operation mode" + depends on (STM32_COMMON_F0_L0_G0_C0 || STM32_COMMON_H7_H5) && STM32_SPI && STM32_SPI1 + default 0 + range 0 3 + ---help--- + Select full-duplex (0), simplex tx (1), simplex rx (2) or half-duplex (3) + +config STM32_SPI2_COMMTYPE + int "SPI2 Operation mode" + depends on (STM32_COMMON_F0_L0_G0_C0 || STM32_COMMON_H7_H5) && STM32_SPI && STM32_SPI2 + default 0 + range 0 3 + ---help--- + Select full-duplex (0), simplex tx (1), simplex rx (2) or half-duplex (3) + +config STM32_SPI3_COMMTYPE + int "SPI3 Operation mode" + depends on (STM32_COMMON_F0_L0_G0_C0 || STM32_COMMON_H7_H5) && STM32_SPI && STM32_SPI3 + default 0 + range 0 3 + ---help--- + Select full-duplex (0), simplex tx (1), simplex rx (2) or half-duplex (3) + +config STM32_SPI6_DMA_BUFFER + int "SPI6 DMA buffer size" + depends on (STM32_COMMON_F7_H7_H5) && STM32_SPI6_DMA + default 0 + ---help--- + Add a properly aligned DMA buffer for RX and TX DMA for SPI6. + +config STM32_SPI4_COMMTYPE + int "SPI4 Operation mode" + depends on STM32_COMMON_H7_H5 && STM32_SPI && STM32_SPI4 + default 0 + range 0 3 + ---help--- + Select full-duplex (0), simplex tx (1), simplex rx (2) or half-duplex (3) + +config STM32_SPI5_COMMTYPE + int "SPI5 Operation mode" + depends on STM32_COMMON_H7_H5 && STM32_SPI && STM32_SPI5 + default 0 + range 0 3 + ---help--- + Select full-duplex (0), simplex tx (1), simplex rx (2) or half-duplex (3) + +config STM32_SPI6_COMMTYPE + int "SPI6 Operation mode" + depends on STM32_COMMON_H7_H5 && STM32_SPI && STM32_SPI6 + default 0 + range 0 3 + ---help--- + Select full-duplex (0), simplex tx (1), simplex rx (2) or half-duplex (3) + +menu "I2S Configuration" + depends on STM32_I2S + +config STM32_SPI2S2_DMA + bool "SPI2S2 DMA" + depends on STM32_SPI2 && !STM32_SPI_INTERRUPT + select STM32_SPI_DMA + ---help--- + Use DMA to improve SPI2S2 transfer performance. Cannot be used with + STM32_SPI_INTERRUPT. + +config STM32_SPI2S2_DMA_BUFFER + int "SPI2S2 DMA buffer size" + default 0 + depends on STM32_SPI2S2_DMA + ---help--- + Add a properly aligned DMA buffer for RX and TX DMA for SPI2S2. + +config STM32_I2S_MAXINFLIGHT + int "I2S queue size" + depends on (STM32_COMMON_LEGACY && STM32_I2S3) || (ARCH_CHIP_STM32F7 && STM32_I2S) + default 16 + ---help--- + This is the total number of transfers, both RX and TX, that can be + enqueue before the caller is required to wait. This setting + determines the number certain queue data structures that will be + pre-allocated. + +config STM32_I2S3_DATALEN + int "Data width (bits)" + depends on (STM32_COMMON_LEGACY && STM32_I2S3) || (ARCH_CHIP_STM32F7 && STM32_I2S && STM32_I2S3) + default 16 + ---help--- + Data width in bits. This is a default value and may be change + via the I2S interface + +config STM32_I2S1_MCK + bool "I2S1_MCK" + depends on ARCH_CHIP_STM32F7 && STM32_I2S1 + ---help--- + TBD. + +config STM32_I2S1_RX + bool "Enable I2S1 receiver" + depends on ARCH_CHIP_STM32F7 && STM32_I2S1 + ---help--- + Enable I2S receipt logic + +config STM32_I2S1_TX + bool "Enable I2S1 transmitter" + depends on ARCH_CHIP_STM32F7 && STM32_I2S1 + ---help--- + Enable I2S transmission logic + +config STM32_I2S1_DATALEN + int "I2S1 Data width (bits)" + depends on ARCH_CHIP_STM32F7 && STM32_I2S1 + default 16 + ---help--- + Data width in bits. This is a default value and may be changed via + the I2S interface. + +config STM32_I2S2_MCK + bool "I2S2_MCK" + depends on ARCH_CHIP_STM32F7 && STM32_I2S2 + ---help--- + TBD. + +config STM32_I2S2_RX + bool "Enable I2S2 receiver" + depends on ARCH_CHIP_STM32F7 && STM32_I2S2 + ---help--- + Enable I2S receipt logic + +config STM32_I2S2_TX + bool "Enable I2S2 transmitter" + depends on ARCH_CHIP_STM32F7 && STM32_I2S2 + ---help--- + Enable I2S transmission logic + +config STM32_I2S2_DATALEN + int "I2S2 Data width (bits)" + depends on ARCH_CHIP_STM32F7 && STM32_I2S2 + default 16 + ---help--- + Data width in bits. This is a default value and may be changed via + the I2S interface. + +config STM32_I2S3_MCK + bool "I2S3_MCK" + depends on ARCH_CHIP_STM32F7 && STM32_I2S3 + ---help--- + TBD. + +config STM32_I2S3_RX + bool "Enable I2S receiver" + depends on (STM32_COMMON_LEGACY && STM32_I2S3) || (ARCH_CHIP_STM32F7 && STM32_I2S && STM32_I2S3) + ---help--- + Enable I2S receipt logic + +config STM32_I2S3_TX + bool "Enable I2S transmitter" + depends on (STM32_COMMON_LEGACY && STM32_I2S3) || (ARCH_CHIP_STM32F7 && STM32_I2S && STM32_I2S3) + ---help--- + Enable I2S transmission logic + +config STM32_I2S_DMADEBUG + bool "I2S DMA transfer debug" + depends on (STM32_COMMON_LEGACY && STM32_I2S3 && DEBUG_DMA) || (ARCH_CHIP_STM32F7 && STM32_I2S && DEBUG_DMA) + ---help--- + Enable special debug instrumentation analyze I2S DMA data transfers. + This logic is as non-invasive as possible: It samples DMA + registers at key points in the data transfer and then dumps all of + the registers at the end of the transfer. + +config STM32_I2S_REGDEBUG + bool "SSC Register level debug" + depends on (STM32_COMMON_LEGACY && STM32_I2S3 && DEBUG) || (ARCH_CHIP_STM32F7 && STM32_I2S && DEBUG) + ---help--- + Output detailed register-level SSC device debug information. + Very invasive! Requires also DEBUG. + +config STM32_I2SPLL + bool "I2SPLL" + default n + depends on STM32_HAVE_I2SPLL + ---help--- + The STM32F446 has a separate PLL for the I2S block. + Set this true and provide configuration parameters in + board.h to use this PLL. + +config STM32_I2S_MCK + bool "I2S_MCK" + depends on STM32_I2S3 + default n + ---help--- + TBD. + +endmenu # I2S Configuration diff --git a/arch/arm/src/common/stm32/Kconfig.system b/arch/arm/src/common/stm32/Kconfig.system new file mode 100644 index 0000000000000..2398b1b534c78 --- /dev/null +++ b/arch/arm/src/common/stm32/Kconfig.system @@ -0,0 +1,107 @@ +# +# STM32 common SYSTEM options. +# + +config STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG + bool "Disable IDLE Sleep (WFI) in debug mode" + depends on STM32_COMMON_LEGACY || STM32_COMMON_L4_H5_L5_U5 || ARCH_CHIP_STM32WB + ---help--- + In debug configuration, disables the WFI instruction in the IDLE loop + to prevent the JTAG from disconnecting. With some JTAG debuggers, such + as the ST-LINK2 with OpenOCD, if the ARM is put to sleep via the WFI + instruction, the debugger will disconnect, terminating the debug session. + +choice + prompt "JTAG Configuration" + default STM32_JTAG_DISABLE + ---help--- + JTAG Enable settings (by default JTAG-DP and SW-DP are disabled) + +config STM32_JTAG_DISABLE + bool "Disable all JTAG clocking" + +config STM32_JTAG_FULL_ENABLE + bool "Enable full SWJ (JTAG-DP + SW-DP)" + +config STM32_JTAG_NOJNTRST_ENABLE + bool "Enable full SWJ (JTAG-DP + SW-DP) but without JNTRST" + +config STM32_JTAG_SW_ENABLE + bool "Set JTAG-DP disabled and SW-DP enabled" + +endchoice + +config STM32_DFU + bool "DFU bootloader" + depends on (STM32_COMMON_LEGACY || STM32_COMMON_F0_L0_G0_C0) && !(STM32F1_VALUELINE || STM32F0_VALUELINE) + ---help--- + Configure and position code for use with the STMicro DFU bootloader. Do + not select this option if you will load code using JTAG/SWM. + +config STM32_TICKLESS_TIMER + int "Tickless hardware timer" + depends on SCHED_TICKLESS + depends on (STM32_COMMON_LEGACY && STM32_TIM) || STM32_COMMON_F7_H7_H5 || ARCH_CHIP_STM32WB + default 2 + range 1 14 if STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7 + range 1 17 if STM32_COMMON_H7_H5 || ARCH_CHIP_STM32WB + ---help--- + If the Tickless OS feature is enabled, then one clock must be + assigned to provided the timer needed by the OS. + +config STM32_TICKLESS_CHANNEL + int "Tickless timer channel" + depends on SCHED_TICKLESS + depends on (STM32_COMMON_LEGACY && STM32_TIM) || STM32_COMMON_F7_H7_H5 || ARCH_CHIP_STM32WB + default 1 + range 1 4 + ---help--- + If the Tickless OS feature is enabled, the one clock must be + assigned to provided the free-running timer needed by the OS + and one channel on that clock is needed to handle intervals. + +config STM32_NOEXT_VECTORS + bool "Disable the ARMv7-M EXT vectors" + default n + ---help--- + Sometimes you may not need any Vector support beyond SysTick + and wish to save memory. This applies only to ARMv7-M architectures. + +# Clock options + +choice + prompt "SysTick clock source" + depends on STM32_COMMON_F0_L0_G0_C0 + default STM32_SYSTICK_CORECLK + +config STM32_SYSTICK_CORECLK + bool "Cortex-M0 core clock" + +config STM32_SYSTICK_CORECLK_DIV16 + bool "Cortex-M0 core clock divided by 16" + +endchoice + +config ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG + bool "Custom clock configuration" + default n + ---help--- + Enables special, board-specific STM32 clock configuration. + +# Power options + +config STM32_FORCEPOWER + bool "Force power" + default n + ---help--- + Timer and I2C devices may need to the following to force power to be applied + unconditionally at power up. (Otherwise, the device is powered when it is + initialized). + +# Debug MCU options + +config STM32_DBGMCU_HAVE_TIM_FZ_IN_CR + bool + +config STM32_DBGMCU_HAVE_TIM_FZ_IN_APB2_FZ + bool diff --git a/arch/arm/src/common/stm32/Kconfig.tim b/arch/arm/src/common/stm32/Kconfig.tim new file mode 100644 index 0000000000000..05d214b4c6833 --- /dev/null +++ b/arch/arm/src/common/stm32/Kconfig.tim @@ -0,0 +1,4210 @@ +# +# STM32 common TIM options. +# + +# STM32 timer configuration options. + +# LPTIM per-instance capability flags +# (hidden; driven by default y if / peripheral selects, never by chip selectors) + +config STM32_LPTIM1_HAVE_CH1OUT + bool + default y if ARCH_CHIP_STM32L4 && STM32_LPTIM1_PWM && STM32_PWM_MULTICHAN && STM32_LPTIM1_CHANNEL1 + default y if ARCH_CHIP_STM32L4 && STM32_LPTIM1_PWM && !STM32_PWM_MULTICHAN && STM32_LPTIM1_CHANNEL = 1 + +config STM32_LPTIM1_HAVE_CH1NOUT + bool + default y if STM32_LPTIM1_HAVE_CH1OUT && STM32_LPTIM1_CH1OUT + default y if ARCH_CHIP_STM32L4 && STM32_LPTIM1_PWM && !STM32_PWM_MULTICHAN && STM32_LPTIM1_CHANNEL = 1 + +config STM32_LPTIM2_HAVE_CH1OUT + bool + default y if ARCH_CHIP_STM32L4 && STM32_LPTIM2_PWM && STM32_PWM_MULTICHAN && STM32_LPTIM2_CHANNEL1 + default y if ARCH_CHIP_STM32L4 && STM32_LPTIM2_PWM && !STM32_PWM_MULTICHAN && STM32_LPTIM2_CHANNEL = 1 + +config STM32_LPTIM2_HAVE_CH1NOUT + bool + default y if STM32_LPTIM2_HAVE_CH1OUT && STM32_LPTIM2_CH1OUT + default y if ARCH_CHIP_STM32L4 && STM32_LPTIM2_PWM && !STM32_PWM_MULTICHAN && STM32_LPTIM2_CHANNEL = 1 + +config STM32_CAP + bool + default n + +config STM32_PULSECOUNT + bool + depends on STM32_HAVE_IP_TIMERS || STM32_COMMON_F0_L0_G0_C0 || STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5 + select ARCH_HAVE_PULSECOUNT + select PULSECOUNT + +config STM32_QE + bool + default n + +config STM32_PWM_MULTICHAN_L5_TIMERS + bool + default y if STM32_TIM1_PWM || STM32_TIM2_PWM || STM32_TIM3_PWM + default y if STM32_TIM4_PWM || STM32_TIM5_PWM || STM32_TIM8_PWM + default y if STM32_TIM15_PWM || STM32_TIM16_PWM || STM32_TIM17_PWM + +config STM32_QENCODER_TIMS_1_4 + bool + default y if STM32_TIM1 || STM32_TIM2 || STM32_TIM3 || STM32_TIM4 + +config STM32_QENCODER_TIMS_1_8 + bool + default y if STM32_QENCODER_TIMS_1_4 + default y if STM32_TIM5 || STM32_TIM8 + +config STM32_QENCODER_MAIN + bool + default y if STM32_HAVE_QENCODER_MAIN && SENSORS_QENCODER && STM32_QENCODER_TIMS_1_8 + +config STM32_QENCODER_STM32 + bool + default y if STM32_HAVE_IP_TIMERS && SENSORS_QENCODER && STM32_QENCODER_TIMS_1_8 + +config STM32_QENCODER_F0 + bool + default y if STM32_HAVE_IP_TIMERS && SENSORS_QENCODER && STM32_QENCODER_TIMS_1_4 + +config STM32_PWM + bool + +menu "Timer Configuration" + depends on STM32_HAVE_LPTIM_CHANNEL || STM32_HAVE_TIM_ADC_CHANNEL + +if STM32_LPTIM1_PWM + +if STM32_PWM_MULTICHAN + +config STM32_LPTIM1_CHANNEL1 + bool "LPTIM1 Channel 1" + depends on STM32_HAVE_LPTIM_CHANNEL + default n + ---help--- + Enables channel 1. + +endif # STM32_PWM_MULTICHAN + +endif # STM32_LPTIM1_PWM + +if STM32_LPTIM2_PWM + +if STM32_PWM_MULTICHAN + +config STM32_LPTIM2_CHANNEL1 + bool "LPTIM2 Channel 1" + depends on STM32_HAVE_LPTIM_CHANNEL + default n + ---help--- + Enables channel 1. + +endif # STM32_PWM_MULTICHAN + +endif # STM32_LPTIM2_PWM + +config STM32_TIM1_ADC_CHAN + int "TIM1 channel" + default 1 + range 1 4 + depends on STM32_TIM1_ADC + ---help--- + Values 1:CC1 2:CC2 3:CC3 4:CC4 + +config STM32_TIM2_ADC_CHAN + int "TIM2 channel" + default 1 + range 1 4 + depends on STM32_TIM2_ADC + ---help--- + Values 1:CC1 2:CC2 3:CC3 4:CC4 + +config STM32_TIM3_ADC_CHAN + int "TIM3 channel" + default 1 + range 1 4 + depends on STM32_TIM3_ADC + ---help--- + Values 1:CC2 2:CC2 3:CC3 4:CC4 + +config STM32_TIM4_ADC_CHAN + int "TIM4 channel" + default 1 + range 1 4 + depends on STM32_TIM4_ADC + ---help--- + Values 1:CC2 2:CC2 3:CC3 4:CC4 + +config STM32_TIM6_ADC_CHAN + int "TIM6 channel" + default 1 + range 1 4 + depends on STM32_TIM6_ADC + ---help--- + Values 1:CC2 2:CC2 3:CC3 4:CC4 + +config STM32_TIM8_ADC_CHAN + int "TIM8 channel" + default 1 + range 1 4 + depends on STM32_TIM8_ADC + ---help--- + Values 1:CC2 2:CC2 3:CC3 4:CC4 + +config STM32_TIM15_ADC_CHAN + int "TIM15 channel" + default 1 + range 1 4 + depends on STM32_TIM15_ADC + ---help--- + Values 1:CC2 2:CC2 3:CC3 4:CC4 + +endmenu # Timer Configuration + +config STM32_TIMX_CAP + bool "Helpers for Capture Drivers" + depends on ARCH_CHIP_STM32H7 + default n + +choice + prompt "Select TIM1 ADC channel" + depends on STM32_TIM1_ADC + default STM32_TIM1_ADC1 + +config STM32_TIM1_ADC1 + bool "TIM1 ADC channel 1" + depends on STM32_ADC1 + select STM32_ADC1_HAVE_TIMER + ---help--- + Reserve TIM1 to trigger ADC1 + +config STM32_TIM1_ADC2 + bool "TIM1 ADC channel 2" + depends on STM32_ADC2 + select STM32_ADC2_HAVE_TIMER + ---help--- + Reserve TIM1 to trigger ADC2 + +config STM32_TIM1_ADC3 + bool "TIM1 ADC channel 3" + depends on STM32_ADC3 + select STM32_ADC3_HAVE_TIMER + ---help--- + Reserve TIM1 to trigger ADC3 + +endchoice + +choice + prompt "Select TIM2 ADC channel" + depends on STM32_TIM2_ADC + default STM32_TIM2_ADC1 + +config STM32_TIM2_ADC1 + bool "TIM2 ADC channel 1" + depends on STM32_ADC1 + select STM32_ADC1_HAVE_TIMER + ---help--- + Reserve TIM2 to trigger ADC1 + +config STM32_TIM2_ADC2 + bool "TIM2 ADC channel 2" + depends on STM32_ADC2 + select STM32_ADC2_HAVE_TIMER + ---help--- + Reserve TIM2 to trigger ADC2 + +config STM32_TIM2_ADC3 + bool "TIM2 ADC channel 3" + depends on STM32_ADC3 + select STM32_ADC3_HAVE_TIMER + ---help--- + Reserve TIM2 to trigger ADC3 + +endchoice + +choice + prompt "Select TIM3 ADC channel" + depends on STM32_TIM3_ADC + default STM32_TIM3_ADC1 + +config STM32_TIM3_ADC1 + bool "TIM3 ADC channel 1" + depends on STM32_ADC1 + select STM32_ADC1_HAVE_TIMER + ---help--- + Reserve TIM3 to trigger ADC1 + +config STM32_TIM3_ADC2 + bool "TIM3 ADC channel 2" + depends on STM32_ADC2 + select STM32_ADC2_HAVE_TIMER + ---help--- + Reserve TIM3 to trigger ADC2 + +config STM32_TIM3_ADC3 + bool "TIM3 ADC channel 3" + depends on STM32_ADC3 + select STM32_ADC3_HAVE_TIMER + ---help--- + Reserve TIM3 to trigger ADC3 + +endchoice + +choice + prompt "Select TIM4 ADC channel" + depends on STM32_TIM4_ADC + default STM32_TIM4_ADC1 + +config STM32_TIM4_ADC1 + bool "TIM4 ADC channel 1" + depends on STM32_ADC1 + select STM32_ADC1_HAVE_TIMER + ---help--- + Reserve TIM4 to trigger ADC1 + +config STM32_TIM4_ADC2 + bool "TIM4 ADC channel 2" + depends on STM32_ADC2 + select STM32_ADC2_HAVE_TIMER + ---help--- + Reserve TIM4 to trigger ADC2 + +config STM32_TIM4_ADC3 + bool "TIM4 ADC channel 3" + depends on STM32_ADC3 + select STM32_ADC3_HAVE_TIMER + ---help--- + Reserve TIM4 to trigger ADC3 + +endchoice + +choice + prompt "Select TIM5 ADC channel" + depends on STM32_TIM5_ADC + default STM32_TIM5_ADC1 + +config STM32_TIM5_ADC1 + bool "TIM5 ADC channel 1" + depends on STM32_ADC1 + select STM32_ADC1_HAVE_TIMER + ---help--- + Reserve TIM5 to trigger ADC1 + +config STM32_TIM5_ADC2 + bool "TIM5 ADC channel 2" + depends on STM32_ADC2 + select STM32_ADC2_HAVE_TIMER + ---help--- + Reserve TIM5 to trigger ADC2 + +config STM32_TIM5_ADC3 + bool "TIM5 ADC channel 3" + depends on STM32_ADC3 + select STM32_ADC3_HAVE_TIMER + ---help--- + Reserve TIM5 to trigger ADC3 + +endchoice + +choice + prompt "Select TIM8 ADC channel" + depends on STM32_TIM8_ADC + default STM32_TIM8_ADC1 + +config STM32_TIM8_ADC1 + bool "TIM8 ADC channel 1" + depends on STM32_ADC1 + select STM32_ADC1_HAVE_TIMER + ---help--- + Reserve TIM8 to trigger ADC1 + +config STM32_TIM8_ADC2 + bool "TIM8 ADC channel 2" + depends on STM32_ADC2 + select STM32_ADC2_HAVE_TIMER + ---help--- + Reserve TIM8 to trigger ADC2 + +config STM32_TIM8_ADC3 + bool "TIM8 ADC channel 3" + depends on STM32_ADC3 + select STM32_ADC3_HAVE_TIMER + ---help--- + Reserve TIM8 to trigger ADC3 + +endchoice + +choice + prompt "Select TIM15 ADC channel" + depends on STM32_TIM15_ADC + default STM32_TIM15_ADC1 + +config STM32_TIM15_ADC1 + bool "TIM15 ADC channel 1" + depends on STM32_ADC1 + select STM32_ADC1_HAVE_TIMER + ---help--- + Reserve TIM15 to trigger ADC1 + +config STM32_TIM15_ADC2 + bool "TIM15 ADC channel 2" + depends on STM32_ADC2 + select STM32_ADC2_HAVE_TIMER + ---help--- + Reserve TIM15 to trigger ADC2 + +config STM32_TIM15_ADC3 + bool "TIM15 ADC channel 3" + depends on STM32_ADC3 + select STM32_ADC3_HAVE_TIMER + ---help--- + Reserve TIM15 to trigger ADC3 + +endchoice + +choice + prompt "Select ADC for use with TIM6" + depends on STM32_TIM6_ADC + default STM32_TIM6_ADC1 + +config STM32_TIM6_ADC1 + bool "Use TIM6 for ADC1" + depends on STM32_ADC1 + select STM32_ADC1_HAVE_TIMER + ---help--- + Reserve TIM6 to trigger ADC1 + +config STM32_TIM6_ADC2 + bool "Use TIM6 for ADC2" + depends on STM32_ADC2 + select STM32_ADC2_HAVE_TIMER + ---help--- + Reserve TIM6 to trigger ADC2 + +config STM32_TIM6_ADC3 + bool "Use TIM6 for ADC3" + depends on STM32_ADC3 + select STM32_ADC3_HAVE_TIMER + ---help--- + Reserve TIM6 to trigger ADC3 + +endchoice + +config STM32_TIM1_ADC + bool "TIM1 ADC" + depends on STM32_HAVE_TIM_ADC_TRIGGER && STM32_ADC && STM32_TIM1 + ---help--- + Reserve timer 1 for use by ADC + + Timer devices may be used for different purposes. If STM32_TIM1 is + defined then the following may also be defined to indicate that the + timer is intended to be used for ADC conversion. Note that ADC usage + requires two definition: Not only do you have to assign the timer + for used by the ADC, but then you also have to configure which ADC + channel it is assigned to. + +config STM32_TIM2_ADC + bool "TIM2 ADC" + depends on STM32_HAVE_TIM_ADC_TRIGGER && STM32_ADC && STM32_TIM2 + ---help--- + Reserve timer 1 for use by ADC + + Timer devices may be used for different purposes. If STM32_TIM2 is + defined then the following may also be defined to indicate that the + timer is intended to be used for ADC conversion. Note that ADC usage + requires two definition: Not only do you have to assign the timer + for used by the ADC, but then you also have to configure which ADC + channel it is assigned to. + +config STM32_TIM3_ADC + bool "TIM3 ADC" + depends on STM32_HAVE_TIM_ADC_TRIGGER && STM32_ADC && STM32_TIM3 + ---help--- + Reserve timer 1 for use by ADC + + Timer devices may be used for different purposes. If STM32_TIM3 is + defined then the following may also be defined to indicate that the + timer is intended to be used for ADC conversion. Note that ADC usage + requires two definition: Not only do you have to assign the timer + for used by the ADC, but then you also have to configure which ADC + channel it is assigned to. + +config STM32_TIM4_ADC + bool "TIM4 ADC" + depends on STM32_HAVE_TIM_ADC_TRIGGER && STM32_ADC && STM32_TIM4 + ---help--- + Reserve timer 1 for use by ADC + + Timer devices may be used for different purposes. If STM32_TIM4 is + defined then the following may also be defined to indicate that the + timer is intended to be used for ADC conversion. Note that ADC usage + requires two definition: Not only do you have to assign the timer + for used by the ADC, but then you also have to configure which ADC + channel it is assigned to. + +config STM32_TIM5_ADC + bool "TIM5 ADC" + depends on STM32_HAVE_TIM_ADC_TRIGGER && STM32_TIM5 && STM32_ADC + ---help--- + Reserve timer 1 for use by ADC + + Timer devices may be used for different purposes. If STM32_TIM5 is + defined then the following may also be defined to indicate that the + timer is intended to be used for ADC conversion. Note that ADC usage + requires two definition: Not only do you have to assign the timer + for used by the ADC, but then you also have to configure which ADC + channel it is assigned to. + +config STM32_TIM8_ADC + bool "TIM8 ADC" + depends on STM32_HAVE_TIM_ADC_TRIGGER && STM32_ADC && STM32_TIM8 + ---help--- + Reserve timer 1 for use by ADC + + Timer devices may be used for different purposes. If STM32_TIM8 is + defined then the following may also be defined to indicate that the + timer is intended to be used for ADC conversion. Note that ADC usage + requires two definition: Not only do you have to assign the timer + for used by the ADC, but then you also have to configure which ADC + channel it is assigned to. + +config STM32_TIM15_ADC + bool "TIM15 ADC" + depends on STM32_HAVE_TIM_ADC_TRIGGER && STM32_TIM15 && STM32_ADC + ---help--- + Reserve timer 1 for use by ADC + +config STM32_TIM6_ADC + bool "TIM6 ADC" + depends on STM32_HAVE_TIM_ADC_TRIGGER && STM32_TIM6 && STM32_ADC + ---help--- + Reserve timer 6 for use by ADC + + Timer devices may be used for different purposes. If STM32_TIM6 is + defined then the following may also be defined to indicate that the + timer is intended to be used for ADC conversion. Note that ADC usage + requires two definition: Not only do you have to assign the timer + for used by the ADC, but then you also have to configure which ADC + channel it is assigned to. + +choice + prompt "Select TIM1 DAC channel" + depends on STM32_TIM1_DAC + default STM32_TIM1_DAC1 + +config STM32_TIM1_DAC1 + bool "TIM1 DAC channel 1" + ---help--- + Reserve TIM1 to trigger DAC1 + +config STM32_TIM1_DAC2 + bool "TIM1 DAC channel 2" + ---help--- + Reserve TIM1 to trigger DAC2 + +endchoice + +choice + prompt "Select TIM2 DAC channel" + depends on STM32_TIM2_DAC + default STM32_TIM2_DAC1 + +config STM32_TIM2_DAC1 + bool "TIM2 DAC channel 1" + ---help--- + Reserve TIM2 to trigger DAC1 + +config STM32_TIM2_DAC2 + bool "TIM2 DAC channel 2" + ---help--- + Reserve TIM2 to trigger DAC2 + +endchoice + +choice + prompt "Select TIM3 DAC channel" + depends on STM32_TIM3_DAC + default STM32_TIM3_DAC1 + +config STM32_TIM3_DAC1 + bool "TIM3 DAC channel 1" + ---help--- + Reserve TIM3 to trigger DAC1 + +config STM32_TIM3_DAC2 + bool "TIM3 DAC channel 2" + ---help--- + Reserve TIM3 to trigger DAC2 + +endchoice + +choice + prompt "Select TIM4 DAC channel" + depends on STM32_TIM4_DAC + default STM32_TIM4_DAC1 + +config STM32_TIM4_DAC1 + bool "TIM4 DAC channel 1" + ---help--- + Reserve TIM4 to trigger DAC1 + +config STM32_TIM4_DAC2 + bool "TIM4 DAC channel 2" + ---help--- + Reserve TIM4 to trigger DAC2 + +endchoice + +choice + prompt "Select TIM5 DAC channel" + depends on STM32_TIM5_DAC + default STM32_TIM5_DAC1 + +config STM32_TIM5_DAC1 + bool "TIM5 DAC channel 1" + ---help--- + Reserve TIM5 to trigger DAC1 + +config STM32_TIM5_DAC2 + bool "TIM5 DAC channel 2" + ---help--- + Reserve TIM5 to trigger DAC2 + +endchoice + +choice + prompt "Select TIM6 DAC channel" + depends on STM32_TIM6_DAC + default STM32_TIM6_DAC1 + +config STM32_TIM6_DAC1 + bool "TIM6 DAC channel 1" + ---help--- + Reserve TIM6 to trigger DAC1 + +config STM32_TIM6_DAC2 + bool "TIM6 DAC channel 2" + ---help--- + Reserve TIM6 to trigger DAC2 + +endchoice + +choice + prompt "Select TIM7 DAC channel" + depends on STM32_TIM7_DAC + default STM32_TIM7_DAC1 + +config STM32_TIM7_DAC1 + bool "TIM7 DAC channel 1" + ---help--- + Reserve TIM7 to trigger DAC1 + +config STM32_TIM7_DAC2 + bool "TIM7 DAC channel 2" + ---help--- + Reserve TIM7 to trigger DAC2 + +endchoice + +choice + prompt "Select TIM8 DAC channel" + depends on STM32_TIM8_DAC + default STM32_TIM8_DAC1 + +config STM32_TIM8_DAC1 + bool "TIM8 DAC channel 1" + ---help--- + Reserve TIM8 to trigger DAC1 + +config STM32_TIM8_DAC2 + bool "TIM8 DAC channel 2" + ---help--- + Reserve TIM8 to trigger DAC2 + +endchoice + +choice + prompt "Select TIM9 DAC channel" + depends on STM32_TIM9_DAC + default STM32_TIM9_DAC1 + +config STM32_TIM9_DAC1 + bool "TIM9 DAC channel 1" + ---help--- + Reserve TIM9 to trigger DAC1 + +config STM32_TIM9_DAC2 + bool "TIM9 DAC channel 2" + ---help--- + Reserve TIM9 to trigger DAC2 + +endchoice + +choice + prompt "Select TIM10 DAC channel" + depends on STM32_TIM10_DAC + default STM32_TIM10_DAC1 + +config STM32_TIM10_DAC1 + bool "TIM10 DAC channel 1" + ---help--- + Reserve TIM10 to trigger DAC1 + +config STM32_TIM10_DAC2 + bool "TIM10 DAC channel 2" + ---help--- + Reserve TIM10 to trigger DAC2 + +endchoice + +choice + prompt "Select TIM11 DAC channel" + depends on STM32_TIM11_DAC + default STM32_TIM11_DAC1 + +config STM32_TIM11_DAC1 + bool "TIM11 DAC channel 1" + ---help--- + Reserve TIM11 to trigger DAC1 + +config STM32_TIM11_DAC2 + bool "TIM11 DAC channel 2" + ---help--- + Reserve TIM11 to trigger DAC2 + +endchoice + +choice + prompt "Select TIM12 DAC channel" + depends on STM32_TIM12_DAC + default STM32_TIM12_DAC1 + +config STM32_TIM12_DAC1 + bool "TIM12 DAC channel 1" + ---help--- + Reserve TIM12 to trigger DAC1 + +config STM32_TIM12_DAC2 + bool "TIM12 DAC channel 2" + ---help--- + Reserve TIM12 to trigger DAC2 + +endchoice + +choice + prompt "Select TIM13 DAC channel" + depends on STM32_TIM13_DAC + default STM32_TIM13_DAC1 + +config STM32_TIM13_DAC1 + bool "TIM13 DAC channel 1" + ---help--- + Reserve TIM13 to trigger DAC1 + +config STM32_TIM13_DAC2 + bool "TIM13 DAC channel 2" + ---help--- + Reserve TIM13 to trigger DAC2 + +endchoice + +choice + prompt "Select TIM14 DAC channel" + depends on STM32_TIM14_DAC + default STM32_TIM14_DAC1 + +config STM32_TIM14_DAC1 + bool "TIM14 DAC channel 1" + ---help--- + Reserve TIM14 to trigger DAC1 + +config STM32_TIM14_DAC2 + bool "TIM14 DAC channel 2" + ---help--- + Reserve TIM14 to trigger DAC2 + +endchoice + +config STM32_TIM1_DAC + bool "TIM1 DAC" + depends on STM32_HAVE_TIM_DAC_TRIGGER && STM32_TIM1 && STM32_DAC + ---help--- + Reserve timer 1 for use by DAC + + Timer devices may be used for different purposes. If STM32_TIM1 is + defined then the following may also be defined to indicate that the + timer is intended to be used for DAC conversion. Note that DAC usage + requires two definition: Not only do you have to assign the timer + for used by the DAC, but then you also have to configure which DAC + channel it is assigned to. + +config STM32_TIM2_DAC + bool "TIM2 DAC" + depends on STM32_HAVE_TIM_DAC_TRIGGER && STM32_TIM2 && STM32_DAC + ---help--- + Reserve timer 2 for use by DAC + + Timer devices may be used for different purposes. If STM32_TIM2 is + defined then the following may also be defined to indicate that the + timer is intended to be used for DAC conversion. Note that DAC usage + requires two definition: Not only do you have to assign the timer + for used by the DAC, but then you also have to configure which DAC + channel it is assigned to. + +config STM32_TIM3_DAC + bool "TIM3 DAC" + depends on STM32_HAVE_TIM_DAC_TRIGGER && STM32_TIM3 && STM32_DAC + ---help--- + Reserve timer 3 for use by DAC + + Timer devices may be used for different purposes. If STM32_TIM3 is + defined then the following may also be defined to indicate that the + timer is intended to be used for DAC conversion. Note that DAC usage + requires two definition: Not only do you have to assign the timer + for used by the DAC, but then you also have to configure which DAC + channel it is assigned to. + +config STM32_TIM4_DAC + bool "TIM4 DAC" + depends on STM32_HAVE_TIM_DAC_TRIGGER && STM32_TIM4 && STM32_DAC + ---help--- + Reserve timer 4 for use by DAC + + Timer devices may be used for different purposes. If STM32_TIM4 is + defined then the following may also be defined to indicate that the + timer is intended to be used for DAC conversion. Note that DAC usage + requires two definition: Not only do you have to assign the timer + for used by the DAC, but then you also have to configure which DAC + channel it is assigned to. + +config STM32_TIM5_DAC + bool "TIM5 DAC" + depends on STM32_HAVE_TIM_DAC_TRIGGER && STM32_TIM5 && STM32_DAC + ---help--- + Reserve timer 5 for use by DAC + + Timer devices may be used for different purposes. If STM32_TIM5 is + defined then the following may also be defined to indicate that the + timer is intended to be used for DAC conversion. Note that DAC usage + requires two definition: Not only do you have to assign the timer + for used by the DAC, but then you also have to configure which DAC + channel it is assigned to. + +config STM32_TIM6_DAC + bool "TIM6 DAC" + depends on STM32_HAVE_TIM_DAC_TRIGGER && STM32_TIM6 && STM32_DAC + ---help--- + Reserve timer 6 for use by DAC + + Timer devices may be used for different purposes. If STM32_TIM6 is + defined then the following may also be defined to indicate that the + timer is intended to be used for DAC conversion. Note that DAC usage + requires two definition: Not only do you have to assign the timer + for used by the DAC, but then you also have to configure which DAC + channel it is assigned to. + +config STM32_TIM7_DAC + bool "TIM7 DAC" + depends on STM32_HAVE_TIM_DAC_TRIGGER && STM32_TIM7 && STM32_DAC + ---help--- + Reserve timer 7 for use by DAC + + Timer devices may be used for different purposes. If STM32_TIM7 is + defined then the following may also be defined to indicate that the + timer is intended to be used for DAC conversion. Note that DAC usage + requires two definition: Not only do you have to assign the timer + for used by the DAC, but then you also have to configure which DAC + channel it is assigned to. + +config STM32_TIM8_DAC + bool "TIM8 DAC" + depends on STM32_HAVE_TIM_DAC_TRIGGER && STM32_TIM8 && STM32_DAC + ---help--- + Reserve timer 8 for use by DAC + + Timer devices may be used for different purposes. If STM32_TIM8 is + defined then the following may also be defined to indicate that the + timer is intended to be used for DAC conversion. Note that DAC usage + requires two definition: Not only do you have to assign the timer + for used by the DAC, but then you also have to configure which DAC + channel it is assigned to. + +config STM32_TIM9_DAC + bool "TIM9 DAC" + depends on STM32_HAVE_TIM_DAC_TRIGGER && STM32_TIM9 && STM32_DAC + ---help--- + Reserve timer 9 for use by DAC + + Timer devices may be used for different purposes. If STM32_TIM9 is + defined then the following may also be defined to indicate that the + timer is intended to be used for DAC conversion. Note that DAC usage + requires two definition: Not only do you have to assign the timer + for used by the DAC, but then you also have to configure which DAC + channel it is assigned to. + +config STM32_TIM10_DAC + bool "TIM10 DAC" + depends on STM32_HAVE_TIM_DAC_TRIGGER && STM32_TIM10 && STM32_DAC + ---help--- + Reserve timer 10 for use by DAC + + Timer devices may be used for different purposes. If STM32_TIM10 is + defined then the following may also be defined to indicate that the + timer is intended to be used for DAC conversion. Note that DAC usage + requires two definition: Not only do you have to assign the timer + for used by the DAC, but then you also have to configure which DAC + channel it is assigned to. + +config STM32_TIM11_DAC + bool "TIM11 DAC" + depends on STM32_HAVE_TIM_DAC_TRIGGER && STM32_TIM11 && STM32_DAC + ---help--- + Reserve timer 11 for use by DAC + + Timer devices may be used for different purposes. If STM32_TIM11 is + defined then the following may also be defined to indicate that the + timer is intended to be used for DAC conversion. Note that DAC usage + requires two definition: Not only do you have to assign the timer + for used by the DAC, but then you also have to configure which DAC + channel it is assigned to. + +config STM32_TIM12_DAC + bool "TIM12 DAC" + depends on STM32_HAVE_TIM_DAC_TRIGGER && STM32_TIM12 && STM32_DAC + ---help--- + Reserve timer 12 for use by DAC + + Timer devices may be used for different purposes. If STM32_TIM12 is + defined then the following may also be defined to indicate that the + timer is intended to be used for DAC conversion. Note that DAC usage + requires two definition: Not only do you have to assign the timer + for used by the DAC, but then you also have to configure which DAC + channel it is assigned to. + +config STM32_TIM13_DAC + bool "TIM13 DAC" + depends on STM32_HAVE_TIM_DAC_TRIGGER && STM32_TIM13 && STM32_DAC + ---help--- + Reserve timer 13 for use by DAC + + Timer devices may be used for different purposes. If STM32_TIM13 is + defined then the following may also be defined to indicate that the + timer is intended to be used for DAC conversion. Note that DAC usage + requires two definition: Not only do you have to assign the timer + for used by the DAC, but then you also have to configure which DAC + channel it is assigned to. + +config STM32_TIM14_DAC + bool "TIM14 DAC" + depends on STM32_HAVE_TIM_DAC_TRIGGER && STM32_TIM14 && STM32_DAC + ---help--- + Reserve timer 14 for use by DAC + + Timer devices may be used for different purposes. If STM32_TIM14 is + defined then the following may also be defined to indicate that the + timer is intended to be used for DAC conversion. Note that DAC usage + requires two definition: Not only do you have to assign the timer + for used by the DAC, but then you also have to configure which DAC + channel it is assigned to. + +choice + prompt "Input channel sampling frequency" + depends on STM32_QENCODER_FILTER + default STM32_QENCODER_SAMPLE_FDTS_4 + +config STM32_QENCODER_SAMPLE_FDTS + bool "fDTS" + +config STM32_QENCODER_SAMPLE_CKINT + bool "fCK_INT" + +config STM32_QENCODER_SAMPLE_FDTS_2 + bool "fDTS/2" + +config STM32_QENCODER_SAMPLE_FDTS_4 + bool "fDTS/4" + +config STM32_QENCODER_SAMPLE_FDTS_8 + bool "fDTS/8" + +config STM32_QENCODER_SAMPLE_FDTS_16 + bool "fDTS/16" + +config STM32_QENCODER_SAMPLE_FDTS_32 + bool "fDTS/32" + +endchoice + +choice + prompt "Input channel event count" + depends on STM32_QENCODER_FILTER + default STM32_QENCODER_SAMPLE_EVENT_6 + +config STM32_QENCODER_SAMPLE_EVENT_1 + bool "1" + depends on STM32_QENCODER_SAMPLE_FDTS + +config STM32_QENCODER_SAMPLE_EVENT_2 + bool "2" + depends on STM32_QENCODER_SAMPLE_CKINT + +config STM32_QENCODER_SAMPLE_EVENT_4 + bool "4" + depends on STM32_QENCODER_SAMPLE_CKINT + +config STM32_QENCODER_SAMPLE_EVENT_5 + bool "5" + depends on STM32_QENCODER_SAMPLE_FDTS_16 || STM32_QENCODER_SAMPLE_FDTS_32 + +config STM32_QENCODER_SAMPLE_EVENT_6 + bool "6" + depends on !STM32_QENCODER_SAMPLE_FDTS && !STM32_QENCODER_SAMPLE_CKINT + +config STM32_QENCODER_SAMPLE_EVENT_8 + bool "8" + depends on !STM32_QENCODER_SAMPLE_FDTS + +endchoice + +choice + prompt "LPTIM1 clock source" + default STM32_LPTIM1_CLK_APB1 + +config STM32_LPTIM1_CLK_APB1 + bool "Clock LPTIM1 from APB1" + +config STM32_LPTIM1_CLK_LSE + bool "Clock LPTIM1 from LSE" + +config STM32_LPTIM1_CLK_LSI + bool "Clock LPTIM1 from LSI" + +config STM32_LPTIM1_CLK_HSI + bool "Clock LPTIM1 from HSI" + +endchoice + +choice + prompt "LPTIM2 clock source" + default STM32_LPTIM2_CLK_APB1 + +config STM32_LPTIM2_CLK_APB1 + bool "Clock LPTIM2 from APB1" + +config STM32_LPTIM2_CLK_LSE + bool "Clock LPTIM2 from LSE" + +config STM32_LPTIM2_CLK_LSI + bool "Clock LPTIM2 from LSI" + +config STM32_LPTIM2_CLK_HSI + bool "Clock LPTIM2 from HSI" + +endchoice + +config STM32_ONESHOT + bool "TIM one-shot wrapper" + depends on (STM32_HAVE_IP_TIMERS && STM32_TIM) || STM32_COMMON_H7_H5 || ARCH_CHIP_STM32WB || STM32_COMMON_L4_L5_U5 + default y if STM32_COMMON_L4_L5_U5 && SCHED_TICKLESS + ---help--- + Enable a wrapper around the low level timer/counter functions to + support one-shot timer. + +config STM32_FREERUN + bool "TIM free-running wrapper" + depends on (STM32_HAVE_IP_TIMERS && STM32_TIM) || ARCH_CHIP_STM32WB || STM32_COMMON_L4_L5_U5 + default y if STM32_COMMON_L4_L5_U5 && SCHED_TICKLESS + ---help--- + Enable a wrapper around the low level timer/counter functions to + support a free-running timer. + +config STM32_ONESHOT_MAXTIMERS + int "Maximum number of oneshot timers" + depends on STM32_ONESHOT + depends on (STM32_HAVE_IP_TIMERS && STM32_TIM) || ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5 || ARCH_CHIP_STM32WB + default 1 + range 1 8 + ---help--- + Determines the maximum number of oneshot timers that can be + supported. This setting pre-allocates some minimal support for each + of the timers and places an upper limit on the number of oneshot + timers that you can use. + +config STM32_PWM_LL_OPS + bool "PWM low-level operations" + depends on (STM32_HAVE_IP_TIMERS && STM32_TIM) || STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5 + ---help--- + Enable low-level PWM ops. + +config STM32_TIM1_PWM + bool "TIM1 PWM" + depends on STM32_TIM1 + depends on STM32_HAVE_TIM_PWM + depends on !STM32_HAVE_IP_TIMERS || STM32_TIM + select STM32_PWM if STM32_HAVE_TIM_PWM_STM32PWM + select PWM if ARCH_CHIP_STM32L5 + select ARCH_HAVE_PWM_PULSECOUNT if ARCH_CHIP_STM32L5 + ---help--- + Reserve timer 1 for use by PWM + + Timer devices may be used for different purposes. One special purpose is + to generate modulated outputs for such things as motor control. If STM32_TIM1 + is defined then THIS following may also be defined to indicate that + the timer is intended to be used for pulsed output modulation. + +config STM32_TIM1_MODE + int "TIM1 Mode" + depends on STM32_TIM1_PWM + default 0 + range 0 4 + ---help--- + Specifies the timer mode. + +config STM32_TIM1_LOCK + int "TIM1 Lock Level Configuration" + depends on STM32_TIM1_PWM + depends on STM32_HAVE_TIM_PWM_ADVANCED + default 0 + range 0 3 + ---help--- + Timer 1 lock level configuration + +config STM32_TIM1_TDTS + int "TIM1 t_DTS Division" + depends on STM32_TIM1_PWM + depends on STM32_HAVE_TIM_PWM_ADVANCED + default 0 + range 0 2 + ---help--- + Timer 1 dead-time and sampling clock (t_DTS) division + +config STM32_TIM1_DEADTIME + int "TIM1 Initial Dead-time" + depends on STM32_TIM1_PWM + depends on STM32_HAVE_TIM_PWM_ADVANCED + default 0 + range 0 255 + ---help--- + Timer 1 initial dead-time + +config STM32_TIM1_CHANNEL1 + bool "TIM1 Channel 1" + depends on STM32_TIM1_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 1. + +config STM32_TIM1_CH1MODE + int "TIM1 Channel 1 Mode" + depends on STM32_TIM1_PWM && STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL1 + default 0 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + default 6 + range 0 11 if STM32_HAVE_TIM_PWM_CHMODE_EXTENDED + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY + range 0 5 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM1_CH1OUT + bool "TIM1 Channel 1 Output" + depends on STM32_TIM1_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL1) || (!STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL = 1 && STM32_HAVE_TIM_PWM_SINGLECHAN) + ---help--- + Enables channel 1 output. + +config STM32_TIM1_CH1NOUT + bool "TIM1 Channel 1 Complementary Output" + depends on STM32_TIM1_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL1) || (!STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL = 1 && STM32_HAVE_TIM_PWM_SINGLECHAN) + depends on STM32_HAVE_TIM_PWM_INTERNAL || STM32_TIM1_CH1OUT || !STM32_PWM_MULTICHAN + ---help--- + Enables channel 1 Complementary Output. + +config STM32_TIM1_CHANNEL2 + bool "TIM1 Channel 2" + depends on STM32_TIM1_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 2. + +config STM32_TIM1_CH2MODE + int "TIM1 Channel 2 Mode" + depends on STM32_TIM1_PWM && STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL2 + default 0 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + default 6 + range 0 11 if STM32_HAVE_TIM_PWM_CHMODE_EXTENDED + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY + range 0 5 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM1_CH2OUT + bool "TIM1 Channel 2 Output" + depends on STM32_TIM1_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL2) || (!STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL = 2 && STM32_HAVE_TIM_PWM_SINGLECHAN) + ---help--- + Enables channel 2 output. + +config STM32_TIM1_CH2NOUT + bool "TIM1 Channel 2 Complementary Output" + depends on STM32_TIM1_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL2) || (!STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL = 2 && STM32_HAVE_TIM_PWM_SINGLECHAN) + depends on STM32_HAVE_TIM_PWM_INTERNAL || STM32_TIM1_CH2OUT || !STM32_PWM_MULTICHAN + ---help--- + Enables channel 2 Complementary Output. + +config STM32_TIM1_CHANNEL3 + bool "TIM1 Channel 3" + depends on STM32_TIM1_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 3. + +config STM32_TIM1_CH3MODE + int "TIM1 Channel 3 Mode" + depends on STM32_TIM1_PWM && STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL3 + default 0 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + default 6 + range 0 11 if STM32_HAVE_TIM_PWM_CHMODE_EXTENDED + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY + range 0 5 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM1_CH3OUT + bool "TIM1 Channel 3 Output" + depends on STM32_TIM1_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL3) || (!STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL = 3 && STM32_HAVE_TIM_PWM_SINGLECHAN) + ---help--- + Enables channel 3 output. + +config STM32_TIM1_CH3NOUT + bool "TIM1 Channel 3 Complementary Output" + depends on STM32_TIM1_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL3) || (!STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL = 3 && STM32_HAVE_TIM_PWM_SINGLECHAN) + depends on STM32_HAVE_TIM_PWM_INTERNAL || STM32_TIM1_CH3OUT || !STM32_PWM_MULTICHAN + ---help--- + Enables channel 3 Complementary Output. + +config STM32_TIM1_CHANNEL4 + bool "TIM1 Channel 4" + depends on STM32_TIM1_PWM && STM32_PWM_MULTICHAN + depends on STM32_HAVE_IP_TIMERS || STM32_HAVE_TIM_PWM_ADVANCED + ---help--- + Enables channel 4. + +config STM32_TIM1_CH4MODE + int "TIM1 Channel 4 Mode" + depends on STM32_TIM1_PWM && STM32_PWM_MULTICHAN + depends on STM32_TIM1_CHANNEL4 || (STM32_COMMON_L5_U5 && STM32_TIM1_CHANNEL5) + default 0 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + default 6 + range 0 11 if STM32_HAVE_TIM_PWM_CHMODE_EXTENDED + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY + range 0 5 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM1_CH4OUT + bool "TIM1 Channel 4 Output" + depends on STM32_TIM1_PWM + depends on STM32_PWM_MULTICHAN || (STM32_TIM1_CHANNEL = 4 && STM32_HAVE_TIM_PWM_SINGLECHAN) + depends on !STM32_PWM_MULTICHAN || STM32_TIM1_CHANNEL4 || (STM32_COMMON_L5_U5 && STM32_TIM1_CHANNEL5) + ---help--- + Enables channel 4 output. + +config STM32_TIM1_CHANNEL5 + bool "TIM1 Channel 5 (internal)" + depends on STM32_TIM1_PWM && STM32_PWM_MULTICHAN + depends on (STM32_HAVE_IP_TIMERS && STM32_HAVE_IP_TIMERS_M3M4_V2) || STM32_COMMON_F7_H7_H5 || STM32_COMMON_L5_U5 + ---help--- + Enables channel 5 (not available externally) + +config STM32_TIM1_CH5MODE + int "TIM1 Channel 5 Mode" + depends on STM32_TIM1_PWM && STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL5 + depends on STM32_HAVE_TIM_PWM_INTERNAL + default 6 + range 0 11 + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM1_CH5OUT + bool "TIM1 Channel 5 Output" + depends on STM32_TIM1_PWM && STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL5 + depends on STM32_HAVE_TIM_PWM_INTERNAL + ---help--- + Enables channel 5 output. + +config STM32_TIM1_CHANNEL6 + bool "TIM1 Channel 6 (internal)" + depends on STM32_TIM1_PWM && STM32_PWM_MULTICHAN + depends on (STM32_HAVE_IP_TIMERS && STM32_HAVE_IP_TIMERS_M3M4_V2) || STM32_COMMON_F7_H7_H5 + ---help--- + Enables channel 6 (not available externally) + +config STM32_TIM1_CH6MODE + int "TIM1 Channel 6 Mode" + depends on STM32_TIM1_PWM && STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL6 + depends on STM32_HAVE_TIM_PWM_INTERNAL + default 6 + range 0 11 + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM1_CH6OUT + bool "TIM1 Channel 6 Output" + depends on STM32_TIM1_PWM && STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL6 + depends on STM32_HAVE_TIM_PWM_INTERNAL + ---help--- + Enables channel 6 output. + +config STM32_TIM1_CHANNEL + int "TIM1 PWM Output Channel" + depends on (STM32_TIM1_PWM && !STM32_PWM_MULTICHAN) || (STM32_TIM1_CAP && ((STM32_HAVE_IP_TIMERS && STM32_TIM) || ARCH_CHIP_STM32H7)) + default 1 + range 1 6 if ARCH_CHIP_STM32H7 && STM32_TIM1_CAP + range 1 4 if !ARCH_CHIP_STM32H7 || !STM32_TIM1_CAP + ---help--- + If TIM1 is enabled for PWM usage, you also need specifies the timer output + channel {1,..,4} + +config STM32_TIM1_CHMODE + int "TIM1 Channel Mode" + depends on STM32_TIM1_PWM && !STM32_PWM_MULTICHAN + default 0 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + default 6 + range 0 11 if STM32_HAVE_TIM_PWM_CHMODE_EXTENDED + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY + range 0 5 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM2_PWM + bool "TIM2 PWM" + depends on STM32_TIM2 + depends on STM32_HAVE_TIM_PWM + depends on !STM32_HAVE_IP_TIMERS || STM32_TIM + select STM32_PWM if STM32_HAVE_TIM_PWM_STM32PWM + select PWM if ARCH_CHIP_STM32L5 + select ARCH_HAVE_PWM_PULSECOUNT if ARCH_CHIP_STM32L5 + ---help--- + Reserve timer 2 for use by PWM + + Timer devices may be used for different purposes. One special purpose is + to generate modulated outputs for such things as motor control. If STM32_TIM2 + is defined then THIS following may also be defined to indicate that + the timer is intended to be used for pulsed output modulation. + +config STM32_TIM2_MODE + int "TIM2 Mode" + depends on STM32_TIM2_PWM + default 0 + range 0 4 + ---help--- + Specifies the timer mode. + +config STM32_TIM2_CHANNEL1 + bool "TIM2 Channel 1" + depends on STM32_TIM2_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 1. + +config STM32_TIM2_CH1MODE + int "TIM2 Channel 1 Mode" + depends on STM32_TIM2_PWM && STM32_PWM_MULTICHAN && STM32_TIM2_CHANNEL1 + default 0 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + default 6 + range 0 11 if STM32_HAVE_TIM_PWM_CHMODE_EXTENDED + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY + range 0 5 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM2_CH1OUT + bool "TIM2 Channel 1 Output" + depends on STM32_TIM2_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM2_CHANNEL1) || (!STM32_PWM_MULTICHAN && STM32_TIM2_CHANNEL = 1 && STM32_HAVE_TIM_PWM_SINGLECHAN) + ---help--- + Enables channel 1 output. + +config STM32_TIM2_CHANNEL2 + bool "TIM2 Channel 2" + depends on STM32_TIM2_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 2. + +config STM32_TIM2_CH2MODE + int "TIM2 Channel 2 Mode" + depends on STM32_TIM2_PWM && STM32_PWM_MULTICHAN && STM32_TIM2_CHANNEL2 + default 0 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + default 6 + range 0 11 if STM32_HAVE_TIM_PWM_CHMODE_EXTENDED + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY + range 0 5 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM2_CH2OUT + bool "TIM2 Channel 2 Output" + depends on STM32_TIM2_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM2_CHANNEL2) || (!STM32_PWM_MULTICHAN && STM32_TIM2_CHANNEL = 2 && STM32_HAVE_TIM_PWM_SINGLECHAN) + ---help--- + Enables channel 2 output. + +config STM32_TIM2_CHANNEL3 + bool "TIM2 Channel 3" + depends on STM32_TIM2_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 3. + +config STM32_TIM2_CH3MODE + int "TIM2 Channel 3 Mode" + depends on STM32_TIM2_PWM && STM32_PWM_MULTICHAN && STM32_TIM2_CHANNEL3 + default 0 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + default 6 + range 0 11 if STM32_HAVE_TIM_PWM_CHMODE_EXTENDED + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY + range 0 5 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM2_CH3OUT + bool "TIM2 Channel 3 Output" + depends on STM32_TIM2_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM2_CHANNEL3) || (!STM32_PWM_MULTICHAN && STM32_TIM2_CHANNEL = 3 && STM32_HAVE_TIM_PWM_SINGLECHAN) + ---help--- + Enables channel 3 output. + +config STM32_TIM2_CHANNEL4 + bool "TIM2 Channel 4" + depends on STM32_TIM2_PWM && STM32_PWM_MULTICHAN + depends on STM32_HAVE_IP_TIMERS || STM32_HAVE_TIM_PWM_ADVANCED + ---help--- + Enables channel 4. + +config STM32_TIM2_CH4MODE + int "TIM2 Channel 4 Mode" + depends on STM32_TIM2_PWM && STM32_PWM_MULTICHAN + depends on STM32_TIM2_CHANNEL4 || (STM32_COMMON_L5_U5 && STM32_TIM2_CHANNEL5) + default 0 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + default 6 + range 0 11 if STM32_HAVE_TIM_PWM_CHMODE_EXTENDED + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY + range 0 5 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM2_CH4OUT + bool "TIM2 Channel 4 Output" + depends on STM32_TIM2_PWM + depends on STM32_PWM_MULTICHAN || (STM32_TIM2_CHANNEL = 4 && STM32_HAVE_TIM_PWM_SINGLECHAN) + depends on !STM32_PWM_MULTICHAN || STM32_TIM2_CHANNEL4 || (STM32_COMMON_L5_U5 && STM32_TIM2_CHANNEL5) + ---help--- + Enables channel 4 output. + +config STM32_TIM2_CHANNEL + int "TIM2 PWM Output Channel" + depends on (STM32_TIM2_PWM && !STM32_PWM_MULTICHAN) || (STM32_TIM2_CAP && ((STM32_HAVE_IP_TIMERS && STM32_TIM) || ARCH_CHIP_STM32H7)) + default 1 + range 1 4 + ---help--- + If TIM2 is enabled for PWM usage, you also need specifies the timer output + channel {1,..,4} + +config STM32_TIM2_CHMODE + int "TIM2 Channel Mode" + depends on STM32_TIM2_PWM && !STM32_PWM_MULTICHAN + default 0 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + default 6 + range 0 11 if STM32_HAVE_TIM_PWM_CHMODE_EXTENDED + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY + range 0 5 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM3_PWM + bool "TIM3 PWM" + depends on STM32_TIM3 + depends on STM32_HAVE_TIM_PWM + depends on !STM32_HAVE_IP_TIMERS || STM32_TIM + select STM32_PWM if STM32_HAVE_TIM_PWM_STM32PWM + select PWM if ARCH_CHIP_STM32L5 + select ARCH_HAVE_PWM_PULSECOUNT if ARCH_CHIP_STM32L5 + ---help--- + Reserve timer 3 for use by PWM + + Timer devices may be used for different purposes. One special purpose is + to generate modulated outputs for such things as motor control. If STM32_TIM3 + is defined then THIS following may also be defined to indicate that + the timer is intended to be used for pulsed output modulation. + +config STM32_TIM3_MODE + int "TIM3 Mode" + depends on STM32_TIM3_PWM + default 0 + range 0 4 + ---help--- + Specifies the timer mode. + +config STM32_TIM3_CHANNEL1 + bool "TIM3 Channel 1" + depends on STM32_TIM3_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 1. + +config STM32_TIM3_CH1MODE + int "TIM3 Channel 1 Mode" + depends on STM32_TIM3_PWM && STM32_PWM_MULTICHAN && STM32_TIM3_CHANNEL1 + default 0 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + default 6 + range 0 11 if STM32_HAVE_TIM_PWM_CHMODE_EXTENDED + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY + range 0 5 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM3_CH1OUT + bool "TIM3 Channel 1 Output" + depends on STM32_TIM3_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM3_CHANNEL1) || (!STM32_PWM_MULTICHAN && STM32_TIM3_CHANNEL = 1 && STM32_HAVE_TIM_PWM_SINGLECHAN) + ---help--- + Enables channel 1 output. + +config STM32_TIM3_CHANNEL2 + bool "TIM3 Channel 2" + depends on STM32_TIM3_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 2. + +config STM32_TIM3_CH2MODE + int "TIM3 Channel 2 Mode" + depends on STM32_TIM3_PWM && STM32_PWM_MULTICHAN && STM32_TIM3_CHANNEL2 + default 0 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + default 6 + range 0 11 if STM32_HAVE_TIM_PWM_CHMODE_EXTENDED + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY + range 0 5 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM3_CH2OUT + bool "TIM3 Channel 2 Output" + depends on STM32_TIM3_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM3_CHANNEL2) || (!STM32_PWM_MULTICHAN && STM32_TIM3_CHANNEL = 2 && STM32_HAVE_TIM_PWM_SINGLECHAN) + ---help--- + Enables channel 2 output. + +config STM32_TIM3_CHANNEL3 + bool "TIM3 Channel 3" + depends on STM32_TIM3_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 3. + +config STM32_TIM3_CH3MODE + int "TIM3 Channel 3 Mode" + depends on STM32_TIM3_PWM && STM32_PWM_MULTICHAN && STM32_TIM3_CHANNEL3 + default 0 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + default 6 + range 0 11 if STM32_HAVE_TIM_PWM_CHMODE_EXTENDED + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY + range 0 5 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM3_CH3OUT + bool "TIM3 Channel 3 Output" + depends on STM32_TIM3_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM3_CHANNEL3) || (!STM32_PWM_MULTICHAN && STM32_TIM3_CHANNEL = 3 && STM32_HAVE_TIM_PWM_SINGLECHAN) + ---help--- + Enables channel 3 output. + +config STM32_TIM3_CHANNEL4 + bool "TIM3 Channel 4" + depends on STM32_TIM3_PWM && STM32_PWM_MULTICHAN + depends on STM32_HAVE_IP_TIMERS || STM32_HAVE_TIM_PWM_ADVANCED + ---help--- + Enables channel 4. + +config STM32_TIM3_CH4MODE + int "TIM3 Channel 4 Mode" + depends on STM32_TIM3_PWM && STM32_PWM_MULTICHAN + depends on STM32_TIM3_CHANNEL4 || (STM32_COMMON_L5_U5 && STM32_TIM3_CHANNEL5) + default 0 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + default 6 + range 0 11 if STM32_HAVE_TIM_PWM_CHMODE_EXTENDED + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY + range 0 5 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM3_CH4OUT + bool "TIM3 Channel 4 Output" + depends on STM32_TIM3_PWM + depends on STM32_PWM_MULTICHAN || (STM32_TIM3_CHANNEL = 4 && STM32_HAVE_TIM_PWM_SINGLECHAN) + depends on !STM32_PWM_MULTICHAN || STM32_TIM3_CHANNEL4 || (STM32_COMMON_L5_U5 && STM32_TIM3_CHANNEL5) + ---help--- + Enables channel 4 output. + +config STM32_TIM3_CHANNEL + int "TIM3 PWM Output Channel" + depends on (STM32_TIM3_PWM && !STM32_PWM_MULTICHAN) || (STM32_TIM3_CAP && ((STM32_HAVE_IP_TIMERS && STM32_TIM) || ARCH_CHIP_STM32H7)) + default 1 + range 1 4 + ---help--- + If TIM3 is enabled for PWM usage, you also need specifies the timer output + channel {1,..,4} + +config STM32_TIM3_CHMODE + int "TIM3 Channel Mode" + depends on STM32_TIM3_PWM && !STM32_PWM_MULTICHAN + default 0 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + default 6 + range 0 11 if STM32_HAVE_TIM_PWM_CHMODE_EXTENDED + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY + range 0 5 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM4_PWM + bool "TIM4 PWM" + depends on STM32_TIM4 + depends on STM32_HAVE_TIM_PWM_NO_F0 + depends on !STM32_HAVE_IP_TIMERS || STM32_TIM + select STM32_PWM if STM32_HAVE_TIM_PWM_STM32PWM + select PWM if ARCH_CHIP_STM32L5 + select ARCH_HAVE_PWM_PULSECOUNT if ARCH_CHIP_STM32L5 + ---help--- + Reserve timer 4 for use by PWM + + Timer devices may be used for different purposes. One special purpose is + to generate modulated outputs for such things as motor control. If STM32_TIM4 + is defined then THIS following may also be defined to indicate that + the timer is intended to be used for pulsed output modulation. + +config STM32_TIM4_MODE + int "TIM4 Mode" + depends on STM32_TIM4_PWM + default 0 + range 0 4 + ---help--- + Specifies the timer mode. + +config STM32_TIM4_CHANNEL1 + bool "TIM4 Channel 1" + depends on STM32_TIM4_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 1. + +config STM32_TIM4_CH1MODE + int "TIM4 Channel 1 Mode" + depends on STM32_TIM4_PWM && STM32_PWM_MULTICHAN && STM32_TIM4_CHANNEL1 + default 0 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + default 6 + range 0 11 if STM32_HAVE_TIM_PWM_CHMODE_EXTENDED + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY + range 0 5 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM4_CH1OUT + bool "TIM4 Channel 1 Output" + depends on STM32_TIM4_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM4_CHANNEL1) || (!STM32_PWM_MULTICHAN && STM32_TIM4_CHANNEL = 1 && STM32_HAVE_TIM_PWM_SINGLECHAN) + ---help--- + Enables channel 1 output. + +config STM32_TIM4_CHANNEL2 + bool "TIM4 Channel 2" + depends on STM32_TIM4_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 2. + +config STM32_TIM4_CH2MODE + int "TIM4 Channel 2 Mode" + depends on STM32_TIM4_PWM && STM32_PWM_MULTICHAN && STM32_TIM4_CHANNEL2 + default 0 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + default 6 + range 0 11 if STM32_HAVE_TIM_PWM_CHMODE_EXTENDED + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY + range 0 5 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM4_CH2OUT + bool "TIM4 Channel 2 Output" + depends on STM32_TIM4_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM4_CHANNEL2) || (!STM32_PWM_MULTICHAN && STM32_TIM4_CHANNEL = 2 && STM32_HAVE_TIM_PWM_SINGLECHAN) + ---help--- + Enables channel 2 output. + +config STM32_TIM4_CHANNEL3 + bool "TIM4 Channel 3" + depends on STM32_TIM4_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 3. + +config STM32_TIM4_CH3MODE + int "TIM4 Channel 3 Mode" + depends on STM32_TIM4_PWM && STM32_PWM_MULTICHAN && STM32_TIM4_CHANNEL3 + default 0 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + default 6 + range 0 11 if STM32_HAVE_TIM_PWM_CHMODE_EXTENDED + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY + range 0 5 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM4_CH3OUT + bool "TIM4 Channel 3 Output" + depends on STM32_TIM4_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM4_CHANNEL3) || (!STM32_PWM_MULTICHAN && STM32_TIM4_CHANNEL = 3 && STM32_HAVE_TIM_PWM_SINGLECHAN) + ---help--- + Enables channel 3 output. + +config STM32_TIM4_CHANNEL4 + bool "TIM4 Channel 4" + depends on STM32_TIM4_PWM && STM32_PWM_MULTICHAN + depends on STM32_HAVE_TIM_PWM_ADVANCED + ---help--- + Enables channel 4. + +config STM32_TIM4_CH4MODE + int "TIM4 Channel 4 Mode" + depends on STM32_TIM4_PWM && STM32_PWM_MULTICHAN + depends on STM32_TIM4_CHANNEL4 || (STM32_COMMON_L5_U5 && STM32_TIM4_CHANNEL5) + default 0 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + default 6 + range 0 11 if STM32_HAVE_TIM_PWM_CHMODE_EXTENDED + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY + range 0 5 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM4_CH4OUT + bool "TIM4 Channel 4 Output" + depends on STM32_TIM4_PWM + depends on STM32_PWM_MULTICHAN || (STM32_TIM4_CHANNEL = 4 && STM32_HAVE_TIM_PWM_SINGLECHAN) + depends on !STM32_PWM_MULTICHAN || STM32_TIM4_CHANNEL4 || (STM32_COMMON_L5_U5 && STM32_TIM4_CHANNEL5) + ---help--- + Enables channel 4 output. + +config STM32_TIM4_CHANNEL + int "TIM4 PWM Output Channel" + depends on (STM32_TIM4_PWM && !STM32_PWM_MULTICHAN) || (STM32_TIM4_CAP && ((STM32_HAVE_IP_TIMERS && STM32_TIM) || ARCH_CHIP_STM32H7)) + default 1 + range 1 4 + ---help--- + If TIM4 is enabled for PWM usage, you also need specifies the timer output + channel {1,..,4} + +config STM32_TIM4_CHMODE + int "TIM4 Channel Mode" + depends on STM32_TIM4_PWM && !STM32_PWM_MULTICHAN + default 0 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + default 6 + range 0 11 if STM32_HAVE_TIM_PWM_CHMODE_EXTENDED + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY + range 0 5 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM5_PWM + bool "TIM5 PWM" + depends on STM32_TIM5 + depends on STM32_HAVE_TIM_PWM_NO_F0 + depends on !STM32_HAVE_IP_TIMERS || STM32_TIM + select STM32_PWM if STM32_HAVE_TIM_PWM_STM32PWM + select PWM if ARCH_CHIP_STM32L5 + select ARCH_HAVE_PWM_PULSECOUNT if ARCH_CHIP_STM32L5 + ---help--- + Reserve timer 5 for use by PWM + + Timer devices may be used for different purposes. One special purpose is + to generate modulated outputs for such things as motor control. If STM32_TIM5 + is defined then THIS following may also be defined to indicate that + the timer is intended to be used for pulsed output modulation. + +config STM32_TIM5_MODE + int "TIM5 Mode" + depends on STM32_TIM5_PWM + default 0 + range 0 4 + ---help--- + Specifies the timer mode. + +config STM32_TIM5_CHANNEL1 + bool "TIM5 Channel 1" + depends on STM32_TIM5_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 1. + +config STM32_TIM5_CH1MODE + int "TIM5 Channel 1 Mode" + depends on STM32_TIM5_PWM && STM32_PWM_MULTICHAN && STM32_TIM5_CHANNEL1 + default 0 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + default 6 + range 0 11 if STM32_HAVE_TIM_PWM_CHMODE_EXTENDED + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY + range 0 5 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM5_CH1OUT + bool "TIM5 Channel 1 Output" + depends on STM32_TIM5_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM5_CHANNEL1) || (!STM32_PWM_MULTICHAN && STM32_TIM5_CHANNEL = 1 && STM32_HAVE_TIM_PWM_SINGLECHAN) + ---help--- + Enables channel 1 output. + +config STM32_TIM5_CHANNEL2 + bool "TIM5 Channel 2" + depends on STM32_TIM5_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 2. + +config STM32_TIM5_CH2MODE + int "TIM5 Channel 2 Mode" + depends on STM32_TIM5_PWM && STM32_PWM_MULTICHAN && STM32_TIM5_CHANNEL2 + default 0 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + default 6 + range 0 11 if STM32_HAVE_TIM_PWM_CHMODE_EXTENDED + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY + range 0 5 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM5_CH2OUT + bool "TIM5 Channel 2 Output" + depends on STM32_TIM5_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM5_CHANNEL2) || (!STM32_PWM_MULTICHAN && STM32_TIM5_CHANNEL = 2 && STM32_HAVE_TIM_PWM_SINGLECHAN) + ---help--- + Enables channel 2 output. + +config STM32_TIM5_CHANNEL3 + bool "TIM5 Channel 3" + depends on STM32_TIM5_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 3. + +config STM32_TIM5_CH3MODE + int "TIM5 Channel 3 Mode" + depends on STM32_TIM5_PWM && STM32_PWM_MULTICHAN && STM32_TIM5_CHANNEL3 + default 0 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + default 6 + range 0 11 if STM32_HAVE_TIM_PWM_CHMODE_EXTENDED + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY + range 0 5 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM5_CH3OUT + bool "TIM5 Channel 3 Output" + depends on STM32_TIM5_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM5_CHANNEL3) || (!STM32_PWM_MULTICHAN && STM32_TIM5_CHANNEL = 3 && STM32_HAVE_TIM_PWM_SINGLECHAN) + ---help--- + Enables channel 3 output. + +config STM32_TIM5_CHANNEL4 + bool "TIM5 Channel 4" + depends on STM32_TIM5_PWM && STM32_PWM_MULTICHAN + depends on STM32_HAVE_TIM_PWM_ADVANCED + ---help--- + Enables channel 4. + +config STM32_TIM5_CH4MODE + int "TIM5 Channel 4 Mode" + depends on STM32_TIM5_PWM && STM32_PWM_MULTICHAN + depends on STM32_TIM5_CHANNEL4 || (STM32_COMMON_L5_U5 && STM32_TIM5_CHANNEL5) + default 0 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + default 6 + range 0 11 if STM32_HAVE_TIM_PWM_CHMODE_EXTENDED + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY + range 0 5 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM5_CH4OUT + bool "TIM5 Channel 4 Output" + depends on STM32_TIM5_PWM + depends on STM32_PWM_MULTICHAN || (STM32_TIM5_CHANNEL = 4 && STM32_HAVE_TIM_PWM_SINGLECHAN) + depends on !STM32_PWM_MULTICHAN || STM32_TIM5_CHANNEL4 || (STM32_COMMON_L5_U5 && STM32_TIM5_CHANNEL5) + ---help--- + Enables channel 4 output. + +config STM32_TIM5_CHANNEL + int "TIM5 PWM Output Channel" + depends on (STM32_TIM5_PWM && !STM32_PWM_MULTICHAN) || (STM32_TIM5_CAP && ((STM32_HAVE_IP_TIMERS && STM32_TIM) || ARCH_CHIP_STM32H7)) + default 1 + range 1 4 + ---help--- + If TIM5 is enabled for PWM usage, you also need specifies the timer output + channel {1,..,4} + +config STM32_TIM5_CHMODE + int "TIM5 Channel Mode" + depends on STM32_TIM5_PWM && !STM32_PWM_MULTICHAN + default 0 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + default 6 + range 0 11 if STM32_HAVE_TIM_PWM_CHMODE_EXTENDED + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY + range 0 5 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM8_PWM + bool "TIM8 PWM" + depends on STM32_TIM8 + depends on STM32_HAVE_TIM_PWM_NO_F0 + depends on !STM32_HAVE_IP_TIMERS || STM32_TIM + select STM32_PWM if STM32_HAVE_TIM_PWM_STM32PWM + select PWM if ARCH_CHIP_STM32L5 + select ARCH_HAVE_PWM_PULSECOUNT if ARCH_CHIP_STM32L5 + ---help--- + Reserve timer 8 for use by PWM + + Timer devices may be used for different purposes. One special purpose is + to generate modulated outputs for such things as motor control. If STM32_TIM8 + is defined then THIS following may also be defined to indicate that + the timer is intended to be used for pulsed output modulation. + +config STM32_TIM8_MODE + int "TIM8 Mode" + depends on STM32_TIM8_PWM + default 0 + range 0 4 + ---help--- + Specifies the timer mode. + +config STM32_TIM8_LOCK + int "TIM8 Lock Level Configuration" + depends on STM32_TIM8_PWM + depends on STM32_HAVE_TIM_PWM_ADVANCED + default 0 + range 0 3 + ---help--- + Timer 8 lock level configuration + +config STM32_TIM8_DEADTIME + int "TIM8 Initial Dead-time" + depends on STM32_TIM8_PWM + depends on STM32_HAVE_TIM_PWM_ADVANCED + default 0 + range 0 255 + ---help--- + Timer 8 initial dead-time + +config STM32_TIM8_TDTS + int "TIM8 t_DTS Division" + depends on STM32_TIM8_PWM + depends on STM32_HAVE_TIM_PWM_ADVANCED + default 0 + range 0 2 + ---help--- + Timer 8 dead-time and sampling clock (t_DTS) division + +config STM32_TIM8_CHANNEL1 + bool "TIM8 Channel 1" + depends on STM32_TIM8_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 1. + +config STM32_TIM8_CH1MODE + int "TIM8 Channel 1 Mode" + depends on STM32_TIM8_PWM && STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL1 + default 0 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + default 6 + range 0 11 if STM32_HAVE_TIM_PWM_CHMODE_EXTENDED + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY + range 0 5 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM8_CH1OUT + bool "TIM8 Channel 1 Output" + depends on STM32_TIM8_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL1) || (!STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL = 1 && STM32_HAVE_TIM_PWM_SINGLECHAN) + ---help--- + Enables channel 1 output. + +config STM32_TIM8_CH1NOUT + bool "TIM8 Channel 1 Complementary Output" + depends on STM32_TIM8_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL1) || (!STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL = 1 && STM32_HAVE_TIM_PWM_SINGLECHAN) + depends on STM32_HAVE_TIM_PWM_INTERNAL || STM32_TIM8_CH1OUT || !STM32_PWM_MULTICHAN + ---help--- + Enables channel 1 Complementary Output. + +config STM32_TIM8_CHANNEL2 + bool "TIM8 Channel 2" + depends on STM32_TIM8_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 2. + +config STM32_TIM8_CH2MODE + int "TIM8 Channel 2 Mode" + depends on STM32_TIM8_PWM && STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL2 + default 0 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + default 6 + range 0 11 if STM32_HAVE_TIM_PWM_CHMODE_EXTENDED + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY + range 0 5 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM8_CH2OUT + bool "TIM8 Channel 2 Output" + depends on STM32_TIM8_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL2) || (!STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL = 2 && STM32_HAVE_TIM_PWM_SINGLECHAN) + ---help--- + Enables channel 2 output. + +config STM32_TIM8_CH2NOUT + bool "TIM8 Channel 2 Complementary Output" + depends on STM32_TIM8_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL2) || (!STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL = 2 && STM32_HAVE_TIM_PWM_SINGLECHAN) + depends on STM32_HAVE_TIM_PWM_INTERNAL || STM32_TIM8_CH2OUT || !STM32_PWM_MULTICHAN + ---help--- + Enables channel 2 Complementary Output. + +config STM32_TIM8_CHANNEL3 + bool "TIM8 Channel 3" + depends on STM32_TIM8_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 3. + +config STM32_TIM8_CH3MODE + int "TIM8 Channel 3 Mode" + depends on STM32_TIM8_PWM && STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL3 + default 0 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + default 6 + range 0 11 if STM32_HAVE_TIM_PWM_CHMODE_EXTENDED + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY + range 0 5 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM8_CH3OUT + bool "TIM8 Channel 3 Output" + depends on STM32_TIM8_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL3) || (!STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL = 3 && STM32_HAVE_TIM_PWM_SINGLECHAN) + ---help--- + Enables channel 3 output. + +config STM32_TIM8_CH3NOUT + bool "TIM8 Channel 3 Complementary Output" + depends on STM32_TIM8_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL3) || (!STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL = 3 && STM32_HAVE_TIM_PWM_SINGLECHAN) + depends on STM32_HAVE_TIM_PWM_INTERNAL || STM32_TIM8_CH3OUT || !STM32_PWM_MULTICHAN + ---help--- + Enables channel 3 Complementary Output. + +config STM32_TIM8_CHANNEL4 + bool "TIM8 Channel 4" + depends on STM32_TIM8_PWM && STM32_PWM_MULTICHAN + depends on STM32_HAVE_TIM_PWM_ADVANCED + ---help--- + Enables channel 4. + +config STM32_TIM8_CH4MODE + int "TIM8 Channel 4 Mode" + depends on STM32_TIM8_PWM && STM32_PWM_MULTICHAN + depends on STM32_TIM8_CHANNEL4 || (STM32_COMMON_L5_U5 && STM32_TIM8_CHANNEL5) + default 0 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + default 6 + range 0 11 if STM32_HAVE_TIM_PWM_CHMODE_EXTENDED + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY + range 0 5 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM8_CH4OUT + bool "TIM8 Channel 4 Output" + depends on STM32_TIM8_PWM + depends on STM32_PWM_MULTICHAN || (STM32_TIM8_CHANNEL = 4 && STM32_HAVE_TIM_PWM_SINGLECHAN) + depends on !STM32_PWM_MULTICHAN || STM32_TIM8_CHANNEL4 || (STM32_COMMON_L5_U5 && STM32_TIM8_CHANNEL5) + ---help--- + Enables channel 4 output. + +config STM32_TIM8_CHANNEL5 + bool "TIM8 Channel 5 (internal)" + depends on STM32_TIM8_PWM && STM32_PWM_MULTICHAN + depends on (STM32_HAVE_IP_TIMERS && STM32_HAVE_IP_TIMERS_M3M4_V2) || STM32_COMMON_F7_H7_H5 || STM32_COMMON_L5_U5 + ---help--- + Enables channel 5 (not available externally) + +config STM32_TIM8_CH5MODE + int "TIM8 Channel 5 Mode" + depends on STM32_TIM8_PWM && STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL5 + depends on STM32_HAVE_TIM_PWM_INTERNAL + default 6 + range 0 11 + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM8_CH5OUT + bool "TIM8 Channel 5 Output" + depends on STM32_TIM8_PWM && STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL5 + depends on STM32_HAVE_TIM_PWM_INTERNAL + ---help--- + Enables channel 5 output. + +config STM32_TIM8_CHANNEL6 + bool "TIM8 Channel 6 (internal)" + depends on STM32_TIM8_PWM && STM32_PWM_MULTICHAN + depends on (STM32_HAVE_IP_TIMERS && STM32_HAVE_IP_TIMERS_M3M4_V2) || STM32_COMMON_F7_H7_H5 + ---help--- + Enables channel 6 (not available externally) + +config STM32_TIM8_CH6MODE + int "TIM8 Channel 6 Mode" + depends on STM32_TIM8_PWM && STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL6 + depends on STM32_HAVE_TIM_PWM_INTERNAL + default 6 + range 0 11 + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM8_CH6OUT + bool "TIM8 Channel 6 Output" + depends on STM32_TIM8_PWM && STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL6 + depends on STM32_HAVE_TIM_PWM_INTERNAL + ---help--- + Enables channel 6 output. + +config STM32_TIM8_CHANNEL + int "TIM8 PWM Output Channel" + depends on (STM32_TIM8_PWM && !STM32_PWM_MULTICHAN) || (STM32_TIM8_CAP && ((STM32_HAVE_IP_TIMERS && STM32_TIM) || ARCH_CHIP_STM32H7)) + default 1 + range 1 6 if ARCH_CHIP_STM32H7 && STM32_TIM8_CAP + range 1 4 if !ARCH_CHIP_STM32H7 || !STM32_TIM8_CAP + ---help--- + If TIM8 is enabled for PWM usage, you also need specifies the timer output + channel {1,..,4} + +config STM32_TIM8_CHMODE + int "TIM8 Channel Mode" + depends on STM32_TIM8_PWM && !STM32_PWM_MULTICHAN + default 0 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + default 6 + range 0 11 if STM32_HAVE_TIM_PWM_CHMODE_EXTENDED + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY + range 0 5 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM9_PWM + bool "TIM9 PWM" + depends on (STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM9) || (ARCH_CHIP_STM32F7 && STM32_TIM9) + select STM32_PWM if STM32_HAVE_TIM_PWM_STM32PWM + ---help--- + Reserve timer 9 for use by PWM + + Timer devices may be used for different purposes. One special purpose is + to generate modulated outputs for such things as motor control. If STM32_TIM9 + is defined then THIS following may also be defined to indicate that + the timer is intended to be used for pulsed output modulation. + +config STM32_TIM9_CHANNEL1 + bool "TIM9 Channel 1" + depends on (STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM9_PWM && STM32_PWM_MULTICHAN) || (ARCH_CHIP_STM32F7 && STM32_TIM9_PWM && STM32_PWM_MULTICHAN) + ---help--- + Enables channel 1. + +config STM32_TIM9_CH1MODE + int "TIM9 Channel 1 Mode" + depends on STM32_TIM9_PWM && STM32_PWM_MULTICHAN && STM32_TIM9_CHANNEL1 + default 6 + range 0 11 if STM32_HAVE_IP_TIMERS && STM32_HAVE_IP_TIMERS_M3M4_V2 + range 0 9 if ARCH_CHIP_STM32F7 + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM9_CH1OUT + bool "TIM9 Channel 1 Output" + depends on STM32_TIM9_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM9_CHANNEL1) || (!STM32_PWM_MULTICHAN && STM32_TIM9_CHANNEL = 1) + ---help--- + Enables channel 1 output. + +config STM32_TIM9_CHANNEL2 + bool "TIM9 Channel 2" + depends on (STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM9_PWM && STM32_PWM_MULTICHAN) || (ARCH_CHIP_STM32F7 && STM32_TIM9_PWM && STM32_PWM_MULTICHAN) + ---help--- + Enables channel 2. + +config STM32_TIM9_CH2MODE + int "TIM9 Channel 2 Mode" + depends on STM32_TIM9_PWM && STM32_PWM_MULTICHAN && STM32_TIM9_CHANNEL2 + default 6 + range 0 11 if STM32_HAVE_IP_TIMERS && STM32_HAVE_IP_TIMERS_M3M4_V2 + range 0 9 if ARCH_CHIP_STM32F7 + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM9_CH2OUT + bool "TIM9 Channel 2 Output" + depends on STM32_TIM9_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM9_CHANNEL2) || (!STM32_PWM_MULTICHAN && STM32_TIM9_CHANNEL = 2) + ---help--- + Enables channel 2 output. + +config STM32_TIM9_CHANNEL + int "TIM9 PWM Output Channel" + depends on (STM32_TIM9_PWM && !STM32_PWM_MULTICHAN) || (STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM9_CAP) + default 1 + range 1 4 if STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM9_CAP + range 1 2 if !STM32_HAVE_IP_TIMERS || !STM32_TIM9_CAP + ---help--- + If TIM9 is enabled for PWM usage, you also need specifies the timer output + channel {1,2} + +config STM32_TIM9_CHMODE + int "TIM9 Channel Mode" + depends on (STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM9_PWM && !STM32_PWM_MULTICHAN) || (ARCH_CHIP_STM32F7 && STM32_TIM9_PWM && !STM32_PWM_MULTICHAN) + default 6 + range 0 11 if STM32_HAVE_IP_TIMERS && STM32_HAVE_IP_TIMERS_M3M4_V2 + range 0 9 if ARCH_CHIP_STM32F7 + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM10_PWM + bool "TIM10 PWM" + depends on (STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM10) || (ARCH_CHIP_STM32F7 && STM32_TIM10) + select STM32_PWM if STM32_HAVE_TIM_PWM_STM32PWM + ---help--- + Reserve timer 10 for use by PWM + + Timer devices may be used for different purposes. One special purpose is + to generate modulated outputs for such things as motor control. If STM32_TIM10 + is defined then THIS following may also be defined to indicate that + the timer is intended to be used for pulsed output modulation. + +config STM32_TIM10_CHANNEL1 + bool "TIM10 Channel 1" + depends on (STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM10_PWM && STM32_PWM_MULTICHAN) || (ARCH_CHIP_STM32F7 && STM32_TIM10_PWM && STM32_PWM_MULTICHAN) + ---help--- + Enables channel 1. + +config STM32_TIM10_CH1MODE + int "TIM10 Channel 1 Mode" + depends on STM32_TIM10_PWM && STM32_PWM_MULTICHAN && STM32_TIM10_CHANNEL1 + default 6 + range 0 11 if STM32_HAVE_IP_TIMERS && STM32_HAVE_IP_TIMERS_M3M4_V2 + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY || ARCH_CHIP_STM32F7 + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM10_CH1OUT + bool "TIM10 Channel 1 Output" + depends on STM32_TIM10_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM10_CHANNEL1) || (!STM32_PWM_MULTICHAN && STM32_TIM10_CHANNEL = 1) + ---help--- + Enables channel 1 output. + +config STM32_TIM10_CHANNEL + int "TIM10 PWM Output Channel" + depends on (STM32_TIM10_PWM && !STM32_PWM_MULTICHAN) || (STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM10_CAP) + default 1 + range 1 4 if STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM10_CAP + range 1 1 if !STM32_HAVE_IP_TIMERS || !STM32_TIM10_CAP + ---help--- + If TIM10 is enabled for PWM usage, you also need specifies the timer output + channel {1} + +config STM32_TIM10_CHMODE + int "TIM10 Channel Mode" + depends on (STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM10_PWM && !STM32_PWM_MULTICHAN) || (ARCH_CHIP_STM32F7 && STM32_TIM10_PWM && !STM32_PWM_MULTICHAN) + default 6 + range 0 11 if STM32_HAVE_IP_TIMERS && STM32_HAVE_IP_TIMERS_M3M4_V2 + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY || ARCH_CHIP_STM32F7 + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM11_PWM + bool "TIM11 PWM" + depends on (STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM11) || (ARCH_CHIP_STM32F7 && STM32_TIM11) + select STM32_PWM if STM32_HAVE_TIM_PWM_STM32PWM + ---help--- + Reserve timer 11 for use by PWM + + Timer devices may be used for different purposes. One special purpose is + to generate modulated outputs for such things as motor control. If STM32_TIM11 + is defined then THIS following may also be defined to indicate that + the timer is intended to be used for pulsed output modulation. + +config STM32_TIM11_CHANNEL1 + bool "TIM11 Channel 1" + depends on (STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM11_PWM && STM32_PWM_MULTICHAN) || (ARCH_CHIP_STM32F7 && STM32_TIM11_PWM && STM32_PWM_MULTICHAN) + ---help--- + Enables channel 1. + +config STM32_TIM11_CH1MODE + int "TIM11 Channel 1 Mode" + depends on STM32_TIM11_PWM && STM32_PWM_MULTICHAN && STM32_TIM11_CHANNEL1 + default 6 + range 0 11 if STM32_HAVE_IP_TIMERS && STM32_HAVE_IP_TIMERS_M3M4_V2 + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY || ARCH_CHIP_STM32F7 + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM11_CH1OUT + bool "TIM11 Channel 1 Output" + depends on STM32_TIM11_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM11_CHANNEL1) || (!STM32_PWM_MULTICHAN && STM32_TIM11_CHANNEL = 1) + ---help--- + Enables channel 1 output. + +config STM32_TIM11_CHANNEL + int "TIM11 PWM Output Channel" + depends on (STM32_TIM11_PWM && !STM32_PWM_MULTICHAN) || (STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM11_CAP) + default 1 + range 1 4 if STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM11_CAP + range 1 1 if !STM32_HAVE_IP_TIMERS || !STM32_TIM11_CAP + ---help--- + If TIM11 is enabled for PWM usage, you also need specifies the timer output + channel {1} + +config STM32_TIM11_CHMODE + int "TIM11 Channel Mode" + depends on (STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM11_PWM && !STM32_PWM_MULTICHAN) || (ARCH_CHIP_STM32F7 && STM32_TIM11_PWM && !STM32_PWM_MULTICHAN) + default 6 + range 0 11 if STM32_HAVE_IP_TIMERS && STM32_HAVE_IP_TIMERS_M3M4_V2 + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY || ARCH_CHIP_STM32F7 + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM12_PWM + bool "TIM12 PWM" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM12 || (STM32_COMMON_F7_H7_H5) && STM32_TIM12 + select STM32_PWM if STM32_HAVE_TIM_PWM_STM32PWM + ---help--- + Reserve timer 12 for use by PWM + + Timer devices may be used for different purposes. One special purpose is + to generate modulated outputs for such things as motor control. If STM32_TIM12 + is defined then THIS following may also be defined to indicate that + the timer is intended to be used for pulsed output modulation. + +config STM32_TIM12_CHANNEL1 + bool "TIM12 Channel 1" + depends on STM32_TIM12_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 1. + +config STM32_TIM12_CH1MODE + int "TIM12 Channel 1 Mode" + depends on STM32_TIM12_PWM && STM32_PWM_MULTICHAN && STM32_TIM12_CHANNEL1 + default 6 + range 0 11 if (STM32_HAVE_IP_TIMERS && STM32_HAVE_IP_TIMERS_M3M4_V2) || STM32_COMMON_H7_H5 + range 0 9 if ARCH_CHIP_STM32F7 + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM12_CH1OUT + bool "TIM12 Channel 1 Output" + depends on STM32_TIM12_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM12_CHANNEL1) || (!STM32_PWM_MULTICHAN && STM32_TIM12_CHANNEL = 1 && STM32_HAVE_TIM_PWM_INTERNAL) + ---help--- + Enables channel 1 output. + +config STM32_TIM12_CHANNEL2 + bool "TIM12 Channel 2" + depends on STM32_TIM12_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 2. + +config STM32_TIM12_CH2MODE + int "TIM12 Channel 2 Mode" + depends on STM32_TIM12_PWM && STM32_PWM_MULTICHAN && STM32_TIM12_CHANNEL2 + default 6 + range 0 11 if (STM32_HAVE_IP_TIMERS && STM32_HAVE_IP_TIMERS_M3M4_V2) || STM32_COMMON_H7_H5 + range 0 9 if ARCH_CHIP_STM32F7 + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM12_CH2OUT + bool "TIM12 Channel 2 Output" + depends on STM32_TIM12_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM12_CHANNEL2) || (!STM32_PWM_MULTICHAN && STM32_TIM12_CHANNEL = 2 && STM32_HAVE_TIM_PWM_INTERNAL) + ---help--- + Enables channel 2 output. + +config STM32_TIM12_CHANNEL + int "TIM12 PWM Output Channel" + depends on (STM32_TIM12_PWM && !STM32_PWM_MULTICHAN) || (STM32_TIM12_CAP && ((STM32_HAVE_IP_TIMERS && STM32_TIM) || ARCH_CHIP_STM32H7)) + default 1 + range 1 4 if STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM12_CAP + range 1 2 if !STM32_HAVE_IP_TIMERS || !STM32_TIM12_CAP + ---help--- + If TIM12 is enabled for PWM usage, you also need specifies the timer output + channel {1,2} + +config STM32_TIM12_CHMODE + int "TIM12 Channel Mode" + depends on STM32_TIM12_PWM && !STM32_PWM_MULTICHAN + default 6 + range 0 11 if (STM32_HAVE_IP_TIMERS && STM32_HAVE_IP_TIMERS_M3M4_V2) || STM32_COMMON_H7_H5 + range 0 9 if ARCH_CHIP_STM32F7 + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM13_PWM + bool "TIM13 PWM" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM13 || (STM32_COMMON_F7_H7_H5) && STM32_TIM13 + select STM32_PWM if STM32_HAVE_TIM_PWM_STM32PWM + ---help--- + Reserve timer 13 for use by PWM + + Timer devices may be used for different purposes. One special purpose is + to generate modulated outputs for such things as motor control. If STM32_TIM13 + is defined then THIS following may also be defined to indicate that + the timer is intended to be used for pulsed output modulation. + +config STM32_TIM13_CHANNEL1 + bool "TIM13 Channel 1" + depends on STM32_TIM13_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 1. + +config STM32_TIM13_CH1MODE + int "TIM13 Channel 1 Mode" + depends on STM32_TIM13_PWM && STM32_PWM_MULTICHAN && STM32_TIM13_CHANNEL1 + default 6 + range 0 11 if (STM32_HAVE_IP_TIMERS && STM32_HAVE_IP_TIMERS_M3M4_V2) || STM32_COMMON_H7_H5 + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY || ARCH_CHIP_STM32F7 + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM13_CH1OUT + bool "TIM13 Channel 1 Output" + depends on STM32_TIM13_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM13_CHANNEL1) || (!STM32_PWM_MULTICHAN && STM32_TIM13_CHANNEL = 1 && STM32_HAVE_TIM_PWM_INTERNAL) + ---help--- + Enables channel 1 output. + +config STM32_TIM13_CHANNEL + int "TIM13 PWM Output Channel" + depends on (STM32_TIM13_PWM && !STM32_PWM_MULTICHAN) || (STM32_TIM13_CAP && ((STM32_HAVE_IP_TIMERS && STM32_TIM) || ARCH_CHIP_STM32H7)) + default 1 + range 1 4 if STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM13_CAP + range 1 1 if !STM32_HAVE_IP_TIMERS || !STM32_TIM13_CAP + ---help--- + If TIM13 is enabled for PWM usage, you also need specifies the timer output + channel {1} + +config STM32_TIM13_CHMODE + int "TIM13 Channel Mode" + depends on STM32_TIM13_PWM && !STM32_PWM_MULTICHAN + default 6 + range 0 11 if (STM32_HAVE_IP_TIMERS && STM32_HAVE_IP_TIMERS_M3M4_V2) || STM32_COMMON_H7_H5 + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY || ARCH_CHIP_STM32F7 + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM14_PWM + bool "TIM14 PWM" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM14 || (STM32_HAVE_IP_TIMERS || STM32_COMMON_F7_H7_H5) && STM32_TIM14 + select STM32_PWM if STM32_HAVE_TIM_PWM_STM32PWM + ---help--- + Reserve timer 14 for use by PWM + + Timer devices may be used for different purposes. One special purpose is + to generate modulated outputs for such things as motor control. If STM32_TIM14 + is defined then THIS following may also be defined to indicate that + the timer is intended to be used for pulsed output modulation. + +config STM32_TIM14_CHANNEL1 + bool "TIM14 Channel 1" + depends on STM32_TIM14_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 1. + +config STM32_TIM14_CH1MODE + int "TIM14 Channel 1 Mode" + depends on STM32_TIM14_PWM && STM32_PWM_MULTICHAN && STM32_TIM14_CHANNEL1 + default 0 if STM32_HAVE_IP_TIMERS + default 6 + range 0 11 if (STM32_HAVE_IP_TIMERS && STM32_HAVE_IP_TIMERS_M3M4_V2) || STM32_COMMON_H7_H5 + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY || ARCH_CHIP_STM32F7 + range 0 1 if STM32_HAVE_IP_TIMERS + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM14_CH1OUT + bool "TIM14 Channel 1 Output" + depends on STM32_TIM14_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM14_CHANNEL1) || (!STM32_PWM_MULTICHAN && STM32_TIM14_CHANNEL = 1 && STM32_HAVE_TIM_PWM_INTERNAL) + ---help--- + Enables channel 1 output. + +config STM32_TIM14_CHANNEL + int "TIM14 PWM Output Channel" + depends on (STM32_TIM14_PWM && !STM32_PWM_MULTICHAN) || (STM32_TIM14_CAP && ((STM32_HAVE_IP_TIMERS && STM32_TIM) || ARCH_CHIP_STM32H7)) + default 1 + range 1 4 if STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM14_CAP + range 1 1 if !STM32_HAVE_IP_TIMERS || !STM32_TIM14_CAP + ---help--- + If TIM14 is enabled for PWM usage, you also need specifies the timer output + channel {1} + +config STM32_TIM14_CHMODE + int "TIM14 Channel Mode" + depends on STM32_TIM14_PWM && !STM32_PWM_MULTICHAN + default 0 if STM32_HAVE_IP_TIMERS + default 6 + range 0 11 if (STM32_HAVE_IP_TIMERS && STM32_HAVE_IP_TIMERS_M3M4_V2) || STM32_COMMON_H7_H5 + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY || ARCH_CHIP_STM32F7 + range 0 1 if STM32_HAVE_IP_TIMERS + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM15_PWM + bool "TIM15 PWM" + depends on STM32_TIM15 + depends on (STM32_HAVE_IP_TIMERS && STM32_TIM) || STM32_HAVE_IP_TIMERS || ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5 || STM32_COMMON_L5_U5 + select STM32_PWM if STM32_HAVE_TIM_PWM_STM32PWM + select PWM if ARCH_CHIP_STM32L5 + ---help--- + Reserve timer 15 for use by PWM + + Timer devices may be used for different purposes. One special purpose is + to generate modulated outputs for such things as motor control. If STM32_TIM15 + is defined then THIS following may also be defined to indicate that + the timer is intended to be used for pulsed output modulation. + +config STM32_TIM15_LOCK + int "TIM15 Lock Level Configuration" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM15_PWM || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM15_PWM + default 0 + range 0 3 + ---help--- + Timer 15 lock level configuration + +config STM32_TIM15_TDTS + int "TIM15 t_DTS Division" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM15_PWM || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM15_PWM + default 0 + range 0 2 + ---help--- + Timer 15 dead-time and sampling clock (t_DTS) division + +config STM32_TIM15_DEADTIME + int "TIM15 Initial Dead-time" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM15_PWM || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM15_PWM + default 0 + range 0 255 + ---help--- + Timer 15 initial dead-time + +config STM32_TIM15_CHANNEL1 + bool "TIM15 Channel 1" + depends on STM32_TIM15_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 1. + +config STM32_TIM15_CH1MODE + int "TIM15 Channel 1 Mode" + depends on STM32_TIM15_PWM && STM32_PWM_MULTICHAN && STM32_TIM15_CHANNEL1 + default 0 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + default 6 + range 0 11 if ARCH_CHIP_STM32L4 + range 0 9 if (STM32_HAVE_IP_TIMERS && STM32_HAVE_IP_TIMERS_M3M4_V2) || STM32_COMMON_H7_H5 + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY + range 0 3 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM15_CH1OUT + bool "TIM15 Channel 1 Output" + depends on STM32_TIM15_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM15_CHANNEL1) || (!STM32_PWM_MULTICHAN && STM32_TIM15_CHANNEL = 1 && STM32_HAVE_TIM_PWM_SINGLECHAN) + ---help--- + Enables channel 1 output. + +config STM32_TIM15_CH1NOUT + bool "TIM15 Channel 1 Complementary Output" + depends on STM32_TIM15_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM15_CHANNEL1) || (!STM32_PWM_MULTICHAN && STM32_TIM15_CHANNEL = 1 && STM32_HAVE_TIM_PWM_SINGLECHAN) + depends on STM32_HAVE_TIM_PWM_INTERNAL || STM32_TIM15_CH1OUT || !STM32_PWM_MULTICHAN + ---help--- + Enables channel 1 Complementary Output. + +config STM32_TIM15_CHANNEL2 + bool "TIM15 Channel 2" + depends on STM32_TIM15_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 2. + +config STM32_TIM15_CH2MODE + int "TIM15 Channel 2 Mode" + depends on STM32_TIM15_PWM && STM32_PWM_MULTICHAN && STM32_TIM15_CHANNEL2 + default 0 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + default 6 + range 0 11 if ARCH_CHIP_STM32L4 + range 0 9 if (STM32_HAVE_IP_TIMERS && STM32_HAVE_IP_TIMERS_M3M4_V2) || STM32_COMMON_H7_H5 + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY + range 0 3 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM15_CH2OUT + bool "TIM15 Channel 2 Output" + depends on STM32_TIM15_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM15_CHANNEL2) || (!STM32_PWM_MULTICHAN && STM32_TIM15_CHANNEL = 2 && STM32_HAVE_TIM_PWM_SINGLECHAN) + ---help--- + Enables channel 2 output. + +config STM32_TIM15_CHANNEL + int "TIM15 PWM Output Channel" + depends on (STM32_TIM15_PWM && !STM32_PWM_MULTICHAN) || (ARCH_CHIP_STM32H7 && STM32_TIM15_CAP) + default 1 + range 1 2 + ---help--- + If TIM15 is enabled for PWM usage, you also need specifies the timer output + channel {1,2} + +config STM32_TIM15_CH2NOUT + bool "TIM15 Channel 2 Complementary Output" + depends on STM32_TIM15_PWM && !STM32_PWM_MULTICHAN && STM32_TIM15_CHANNEL = 2 + depends on STM32_HAVE_TIM_PWM_SINGLECHAN + ---help--- + Enables channel 2 Complementary Output. + +config STM32_TIM15_CHMODE + int "TIM15 Channel Mode" + depends on STM32_TIM15_PWM && !STM32_PWM_MULTICHAN + default 0 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + default 6 + range 0 9 if (STM32_HAVE_IP_TIMERS && STM32_HAVE_IP_TIMERS_M3M4_V2) || ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5 + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY + range 0 3 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM16_PWM + bool "TIM16 PWM" + depends on STM32_TIM16 + depends on (STM32_HAVE_IP_TIMERS && STM32_TIM) || STM32_HAVE_IP_TIMERS || ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5 || STM32_COMMON_L5_U5 + select STM32_PWM if STM32_HAVE_TIM_PWM_STM32PWM + select PWM if ARCH_CHIP_STM32L5 + ---help--- + Reserve timer 16 for use by PWM + + Timer devices may be used for different purposes. One special purpose is + to generate modulated outputs for such things as motor control. If STM32_TIM16 + is defined then THIS following may also be defined to indicate that + the timer is intended to be used for pulsed output modulation. + +config STM32_TIM16_LOCK + int "TIM16 Lock Level Configuration" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM16_PWM || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM16_PWM + default 0 + range 0 3 + ---help--- + Timer 16 lock level configuration + +config STM32_TIM16_TDTS + int "TIM16 t_DTS division" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM16_PWM || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM16_PWM + default 0 + range 0 2 + ---help--- + Timer 16 dead-time and sampling clock (t_DTS) division + +config STM32_TIM16_DEADTIME + int "TIM16 Initial Dead-time" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM16_PWM || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM16_PWM + default 0 + range 0 255 + ---help--- + Timer 16 initial dead-time + +config STM32_TIM16_CHANNEL1 + bool "TIM16 Channel 1" + depends on STM32_TIM16_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 1. + +config STM32_TIM16_CH1MODE + int "TIM16 Channel 1 Mode" + depends on STM32_TIM16_PWM && STM32_PWM_MULTICHAN && STM32_TIM16_CHANNEL1 + default 0 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + default 6 + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_TIM16_17_EXTENDED + range 0 1 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM16_CH1OUT + bool "TIM16 Channel 1 Output" + depends on STM32_TIM16_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM16_CHANNEL1) || (!STM32_PWM_MULTICHAN && STM32_TIM16_CHANNEL = 1 && STM32_HAVE_TIM_PWM_SINGLECHAN) + ---help--- + Enables channel 1 output. + +config STM32_TIM16_CHANNEL + int "TIM16 PWM Output Channel" + depends on (STM32_TIM16_PWM && !STM32_PWM_MULTICHAN) || (ARCH_CHIP_STM32H7 && STM32_TIM16_CAP) + default 1 + range 1 1 + ---help--- + If TIM16 is enabled for PWM usage, you also need specifies the timer output + channel {1} + +config STM32_TIM16_CHMODE + int "TIM16 Channel Mode" + depends on STM32_TIM16_PWM && !STM32_PWM_MULTICHAN + default 0 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + default 6 + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_TIM16_17_EXTENDED + range 0 1 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM17_PWM + bool "TIM17 PWM" + depends on STM32_TIM17 + depends on (STM32_HAVE_IP_TIMERS && STM32_TIM) || STM32_HAVE_IP_TIMERS || ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5 || STM32_COMMON_L5_U5 + select STM32_PWM if STM32_HAVE_TIM_PWM_STM32PWM + select PWM if ARCH_CHIP_STM32L5 + ---help--- + Reserve timer 17 for use by PWM + + Timer devices may be used for different purposes. One special purpose is + to generate modulated outputs for such things as motor control. If STM32_TIM17 + is defined then THIS following may also be defined to indicate that + the timer is intended to be used for pulsed output modulation. + +config STM32_TIM17_LOCK + int "TIM17 Lock Level Configuration" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM17_PWM || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM17_PWM + default 0 + range 0 3 + ---help--- + Timer 17 lock level configuration + +config STM32_TIM17_TDTS + int "TIM17 t_DTS Division" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM17_PWM || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM17_PWM + default 0 + range 0 2 + ---help--- + Timer 17 dead-time and sampling clock (t_DTS) division + +config STM32_TIM17_DEADTIME + int "TIM17 Initial Dead-time" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM17_PWM || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM17_PWM + default 0 + range 0 255 + ---help--- + Timer 17 initial dead-time + +config STM32_TIM17_CHANNEL1 + bool "TIM17 Channel 1" + depends on STM32_TIM17_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 1. + +config STM32_TIM17_CH1MODE + int "TIM17 Channel 1 Mode" + depends on STM32_TIM17_PWM && STM32_PWM_MULTICHAN && STM32_TIM17_CHANNEL1 + default 0 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + default 6 + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_TIM16_17_EXTENDED + range 0 1 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM17_CH1OUT + bool "TIM17 Channel 1 Output" + depends on STM32_TIM17_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM17_CHANNEL1) || (!STM32_PWM_MULTICHAN && STM32_TIM17_CHANNEL = 1 && STM32_HAVE_TIM_PWM_SINGLECHAN) + ---help--- + Enables channel 1 output. + +config STM32_TIM17_CHANNEL + int "TIM17 PWM Output Channel" + depends on (STM32_TIM17_PWM && !STM32_PWM_MULTICHAN) || (ARCH_CHIP_STM32H7 && STM32_TIM17_CAP) + default 1 + range 1 1 + ---help--- + If TIM17 is enabled for PWM usage, you also need specifies the timer output + channel {1} + +config STM32_TIM17_CHMODE + int "TIM17 Channel Mode" + depends on STM32_TIM17_PWM && !STM32_PWM_MULTICHAN + default 0 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + default 6 + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_TIM16_17_EXTENDED + range 0 1 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_PWM_MULTICHAN + bool "PWM Multiple Output Channels" + depends on STM32_HAVE_PWM_MULTICHAN + ---help--- + Specifies that the PWM driver supports multiple output + channels per timer. + +config STM32_TIM1_PULSECOUNT + bool "TIM1 pulse count" + depends on STM32_TIM1 + depends on STM32_HAVE_IP_TIMERS || STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5 + select STM32_PULSECOUNT + ---help--- + Reserve timer 1 for pulse count output. + +if STM32_TIM1_PULSECOUNT + +config STM32_TIM1_PULSECOUNT_TDTS + int "TIM1 pulse count clock division" + default 0 + range 0 2 + depends on !STM32_HAVE_IP_TIMERS + +config STM32_TIM1_PULSECOUNT_CHANNEL + int "TIM1 pulse count channel" + default 1 + range 1 4 + ---help--- + Specifies the timer channel {1,..,4}. + +config STM32_TIM1_PULSECOUNT_POL + int "TIM1 pulse count output polarity" + default 0 + range 0 1 + depends on !STM32_HAVE_IP_TIMERS + +config STM32_TIM1_PULSECOUNT_IDLE + int "TIM1 pulse count idle state" + default 0 + range 0 1 + depends on !STM32_HAVE_IP_TIMERS + +endif # STM32_TIM1_PULSECOUNT + +config STM32_TIM8_PULSECOUNT + bool "TIM8 pulse count" + depends on STM32_TIM8 + depends on (STM32_HAVE_IP_TIMERS && STM32_TIM) || STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5 + select STM32_PULSECOUNT + ---help--- + Reserve timer 8 for pulse count output. + +if STM32_TIM8_PULSECOUNT + +config STM32_TIM8_PULSECOUNT_TDTS + int "TIM8 pulse count clock division" + default 0 + range 0 2 + +config STM32_TIM8_PULSECOUNT_CHANNEL + int "TIM8 pulse count channel" + default 1 + range 1 4 + ---help--- + Specifies the timer channel {1,..,4}. + +config STM32_TIM8_PULSECOUNT_POL + int "TIM8 pulse count output polarity" + default 0 + range 0 1 + +config STM32_TIM8_PULSECOUNT_IDLE + int "TIM8 pulse count idle state" + default 0 + range 0 1 + +endif # STM32_TIM8_PULSECOUNT + +config STM32_PWM_TRGO + bool "TIM PWM TRGO support" + depends on (STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_PWM) || (ARCH_CHIP_STM32F7 && STM32_PWM) + ---help--- + Enable TRGO support for PWM driver + +config STM32_TIM1_CAP + bool "TIM1 Capture" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM1 || (STM32_COMMON_F7_H7_H5) && STM32_TIM1 || STM32_COMMON_L4_L5_U5 && STM32_HAVE_TIM1 + select STM32_CAP if STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM1 + select STM32_TIMX_CAP if ARCH_CHIP_STM32H7 && STM32_TIM1 + ---help--- + Reserve timer 1 for use by Capture + + Timer devices may be used for different purposes. One special purpose is + to capture input. + +config STM32_TIM1_CLOCK + int "TIM1 work frequency for capture" + depends on (STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM1_CAP) || (ARCH_CHIP_STM32H7 && STM32_TIM1_CAP) + default 1000000 if STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM1_CAP + default 100000 if ARCH_CHIP_STM32H7 && STM32_TIM1_CAP + ---help--- + This clock frequency limiting the count rate at the expense of resolution. + +config STM32_TIM2_CAP + bool "TIM2 Capture" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM2 || (STM32_COMMON_F7_H7_H5) && STM32_TIM2 || STM32_COMMON_L4_L5_U5 && STM32_HAVE_TIM2 + select STM32_CAP if STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM2 + select STM32_TIMX_CAP if ARCH_CHIP_STM32H7 && STM32_TIM2 + ---help--- + Reserve timer 2 for use by Capture + + Timer devices may be used for different purposes. One special purpose is + to capture input. + +config STM32_TIM2_CLOCK + int "TIM2 work frequency for capture" + depends on (STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM2_CAP) || (ARCH_CHIP_STM32H7 && STM32_TIM2_CAP) + default 1000000 if STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM2_CAP + default 100000 if ARCH_CHIP_STM32H7 && STM32_TIM2_CAP + ---help--- + This clock frequency limiting the count rate at the expense of resolution. + +config STM32_TIM3_CAP + bool "TIM3 Capture" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM3 || (STM32_COMMON_F7_H7_H5) && STM32_TIM3 || STM32_COMMON_L4_L5_U5 && STM32_HAVE_TIM3 + select STM32_CAP if STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM3 + select STM32_TIMX_CAP if ARCH_CHIP_STM32H7 && STM32_TIM3 + ---help--- + Reserve timer 3 for use by Capture + + Timer devices may be used for different purposes. One special purpose is + to capture input. + +config STM32_TIM3_CLOCK + int "TIM3 work frequency for capture" + depends on (STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM3_CAP) || (ARCH_CHIP_STM32H7 && STM32_TIM3_CAP) + default 1000000 if STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM3_CAP + default 100000 if ARCH_CHIP_STM32H7 && STM32_TIM3_CAP + ---help--- + This clock frequency limiting the count rate at the expense of resolution. + +config STM32_TIM4_CAP + bool "TIM4 Capture" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM4 || (STM32_COMMON_F7_H7_H5) && STM32_TIM4 || STM32_COMMON_L4_L5_U5 && STM32_HAVE_TIM4 + select STM32_CAP if STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM4 + select STM32_TIMX_CAP if ARCH_CHIP_STM32H7 && STM32_TIM4 + ---help--- + Reserve timer 4 for use by Capture + + Timer devices may be used for different purposes. One special purpose is + to capture input. + +config STM32_TIM4_CLOCK + int "TIM4 work frequency for capture" + depends on (STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM4_CAP) || (ARCH_CHIP_STM32H7 && STM32_TIM4_CAP) + default 1000000 if STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM4_CAP + default 100000 if ARCH_CHIP_STM32H7 && STM32_TIM4_CAP + ---help--- + This clock frequency limiting the count rate at the expense of resolution. + +config STM32_TIM5_CAP + bool "TIM5 Capture" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM5 || (STM32_COMMON_F7_H7_H5) && STM32_TIM5 || STM32_COMMON_L4_L5_U5 && STM32_HAVE_TIM5 + select STM32_CAP if STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM5 + select STM32_TIMX_CAP if ARCH_CHIP_STM32H7 && STM32_TIM5 + ---help--- + Reserve timer 5 for use by Capture + + Timer devices may be used for different purposes. One special purpose is + to capture input. + +config STM32_TIM5_CLOCK + int "TIM5 work frequency for capture" + depends on (STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM5_CAP) || (ARCH_CHIP_STM32H7 && STM32_TIM5_CAP) + default 1000000 if STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM5_CAP + default 100000 if ARCH_CHIP_STM32H7 && STM32_TIM5_CAP + ---help--- + This clock frequency limiting the count rate at the expense of resolution. + +config STM32_TIM8_CAP + bool "TIM8 Capture" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM8 || (STM32_COMMON_F7_H7_H5) && STM32_TIM8 || STM32_COMMON_L4_L5_U5 && STM32_HAVE_TIM8 + select STM32_CAP if STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM8 + select STM32_TIMX_CAP if ARCH_CHIP_STM32H7 && STM32_TIM8 + ---help--- + Reserve timer 8 for use by Capture + + Timer devices may be used for different purposes. One special purpose is + to capture input. + +config STM32_TIM8_CLOCK + int "TIM8 work frequency for capture" + depends on (STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM8_CAP) || (ARCH_CHIP_STM32H7 && STM32_TIM8_CAP) + default 1000000 if STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM8_CAP + default 100000 if ARCH_CHIP_STM32H7 && STM32_TIM8_CAP + ---help--- + This clock frequency limiting the count rate at the expense of resolution. + +config STM32_TIM9_CAP + bool "TIM9 Capture" + depends on (STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM9) || (ARCH_CHIP_STM32F7 && STM32_TIM9) + select STM32_CAP if STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM9 + ---help--- + Reserve timer 9 for use by Capture + + Timer devices may be used for different purposes. One special purpose is + to capture input. + +config STM32_TIM10_CAP + bool "TIM10 Capture" + depends on (STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM10) || (ARCH_CHIP_STM32F7 && STM32_TIM10) + select STM32_CAP if STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM10 + ---help--- + Reserve timer 10 for use by Capture + + Timer devices may be used for different purposes. One special purpose is + to capture input. + +config STM32_TIM11_CAP + bool "TIM11 Capture" + depends on (STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM11) || (ARCH_CHIP_STM32F7 && STM32_TIM11) + select STM32_CAP if STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM11 + ---help--- + Reserve timer 11 for use by Capture + + Timer devices may be used for different purposes. One special purpose is + to capture input. + +config STM32_TIM12_CAP + bool "TIM12 Capture" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM12 || (STM32_COMMON_F7_H7_H5) && STM32_TIM12 + select STM32_CAP if STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM12 + select STM32_TIMX_CAP if ARCH_CHIP_STM32H7 && STM32_TIM12 + ---help--- + Reserve timer 12 for use by Capture + + Timer devices may be used for different purposes. One special purpose is + to capture input. + +config STM32_TIM12_CLOCK + int "TIM12 work frequency for capture" + depends on (STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM12_CAP) || (ARCH_CHIP_STM32H7 && STM32_TIM12_CAP) + default 1000000 if STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM12_CAP + default 100000 if ARCH_CHIP_STM32H7 && STM32_TIM12_CAP + ---help--- + This clock frequency limiting the count rate at the expense of resolution. + +config STM32_TIM13_CAP + bool "TIM13 Capture" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM13 || (STM32_COMMON_F7_H7_H5) && STM32_TIM13 + select STM32_CAP if STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM13 + select STM32_TIMX_CAP if ARCH_CHIP_STM32H7 && STM32_TIM13 + ---help--- + Reserve timer 13 for use by Capture + + Timer devices may be used for different purposes. One special purpose is + to capture input. + +config STM32_TIM13_CLOCK + int "TIM13 work frequency for capture" + depends on (STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM13_CAP) || (ARCH_CHIP_STM32H7 && STM32_TIM13_CAP) + default 1000000 if STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM13_CAP + default 100000 if ARCH_CHIP_STM32H7 && STM32_TIM13_CAP + ---help--- + This clock frequency limiting the count rate at the expense of resolution. + +config STM32_TIM14_CAP + bool "TIM14 Capture" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM14 || (STM32_COMMON_F7_H7_H5) && STM32_TIM14 + select STM32_CAP if STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM14 + select STM32_TIMX_CAP if ARCH_CHIP_STM32H7 && STM32_TIM14 + ---help--- + Reserve timer 14 for use by Capture + + Timer devices may be used for different purposes. One special purpose is + to capture input. + +config STM32_TIM14_CLOCK + int "TIM14 work frequency for capture" + depends on (STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM14_CAP) || (ARCH_CHIP_STM32H7 && STM32_TIM14_CAP) + default 1000000 if STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM14_CAP + default 100000 if ARCH_CHIP_STM32H7 && STM32_TIM14_CAP + ---help--- + This clock frequency limiting the count rate at the expense of resolution. + +config STM32_TIM1_CH1POL + int "TIM1 Channel 1 Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM1_CH1OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM1_CH1OUT + default 0 + range 0 1 + ---help--- + TIM1 Channel 1 output polarity + +config STM32_TIM1_CH1IDLE + int "TIM1 Channel 1 Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM1_CH1OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM1_CH1OUT + default 0 + range 0 1 + ---help--- + TIM1 Channel 1 output IDLE + +config STM32_TIM1_CH1NPOL + int "TIM1 Channel 1 Complementary Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM1_CH1NOUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM1_CH1NOUT + default 0 + range 0 1 + ---help--- + TIM1 Channel 1 Complementary Output polarity + +config STM32_TIM1_CH1NIDLE + int "TIM1 Channel 1 Complementary Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM1_CH1NOUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM1_CH1NOUT + default 0 + range 0 1 + ---help--- + TIM1 Channel 1 Complementary Output IDLE + +config STM32_TIM1_CH2POL + int "TIM1 Channel 2 Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM1_CH2OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM1_CH2OUT + default 0 + range 0 1 + ---help--- + TIM1 Channel 2 output polarity + +config STM32_TIM1_CH2IDLE + int "TIM1 Channel 2 Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM1_CH2OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM1_CH2OUT + default 0 + range 0 1 + ---help--- + TIM1 Channel 2 output IDLE + +config STM32_TIM1_CH2NPOL + int "TIM1 Channel 2 Complementary Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM1_CH2NOUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM1_CH2NOUT + default 0 + range 0 1 + ---help--- + TIM1 Channel 2 Complementary Output polarity + +config STM32_TIM1_CH2NIDLE + int "TIM1 Channel 2 Complementary Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM1_CH2NOUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM1_CH2NOUT + default 0 + range 0 1 + ---help--- + TIM1 Channel 2 Complementary Output IDLE + +config STM32_TIM1_CH3POL + int "TIM1 Channel 3 Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM1_CH3OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM1_CH3OUT + default 0 + range 0 1 + ---help--- + TIM1 Channel 3 output polarity + +config STM32_TIM1_CH3IDLE + int "TIM1 Channel 3 Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM1_CH3OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM1_CH3OUT + default 0 + range 0 1 + ---help--- + TIM1 Channel 3 output IDLE + +config STM32_TIM1_CH3NPOL + int "TIM1 Channel 3 Complementary Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM1_CH3NOUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM1_CH3NOUT + default 0 + range 0 1 + ---help--- + TIM1 Channel 3 Complementary Output polarity + +config STM32_TIM1_CH3NIDLE + int "TIM1 Channel 3 Complementary Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM1_CH3NOUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM1_CH3NOUT + default 0 + range 0 1 + ---help--- + TIM1 Channel 3 Complementary Output IDLE + +config STM32_TIM1_CH4POL + int "TIM1 Channel 4 Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM1_CH4OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM1_CH4OUT + default 0 + range 0 1 + ---help--- + TIM1 Channel 4 output polarity + +config STM32_TIM1_CH4IDLE + int "TIM1 Channel 4 Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM1_CH4OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM1_CH4OUT + default 0 + range 0 1 + ---help--- + TIM1 Channel 4 output IDLE + +config STM32_TIM1_CH5POL + int "TIM1 Channel 5 Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM1_CH5OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM1_CH5OUT + default 0 + range 0 1 + ---help--- + TIM1 Channel 5 output polarity + +config STM32_TIM1_CH5IDLE + int "TIM1 Channel 5 Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM1_CH5OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM1_CH5OUT + default 0 + range 0 1 + ---help--- + TIM1 Channel 5 output IDLE + +config STM32_TIM1_CH6POL + int "TIM1 Channel 6 Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM1_CH6OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM1_CH6OUT + default 0 + range 0 1 + ---help--- + TIM1 Channel 6 output polarity + +config STM32_TIM1_CH6IDLE + int "TIM1 Channel 6 Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM1_CH6OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM1_CH6OUT + default 0 + range 0 1 + ---help--- + TIM1 Channel 6 output IDLE + +config STM32_TIM2_CH1POL + int "TIM2 Channel 1 Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM2_CH1OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM2_CH1OUT + default 0 + range 0 1 + ---help--- + TIM2 Channel 1 output polarity + +config STM32_TIM2_CH1IDLE + int "TIM2 Channel 1 Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM2_CH1OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM2_CH1OUT + default 0 + range 0 1 + ---help--- + TIM2 Channel 1 output IDLE + +config STM32_TIM2_CH2POL + int "TIM2 Channel 2 Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM2_CH2OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM2_CH2OUT + default 0 + range 0 1 + ---help--- + TIM2 Channel 2 output polarity + +config STM32_TIM2_CH2IDLE + int "TIM2 Channel 2 Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM2_CH2OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM2_CH2OUT + default 0 + range 0 1 + ---help--- + TIM2 Channel 2 output IDLE + +config STM32_TIM2_CH3POL + int "TIM2 Channel 3 Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM2_CH3OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM2_CH3OUT + default 0 + range 0 1 + ---help--- + TIM2 Channel 3 output polarity + +config STM32_TIM2_CH3IDLE + int "TIM2 Channel 3 Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM2_CH3OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM2_CH3OUT + default 0 + range 0 1 + ---help--- + TIM2 Channel 3 output IDLE + +config STM32_TIM2_CH4POL + int "TIM2 Channel 4 Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM2_CH4OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM2_CH4OUT + default 0 + range 0 1 + ---help--- + TIM2 Channel 4 output polarity + +config STM32_TIM2_CH4IDLE + int "TIM2 Channel 4 Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM2_CH4OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM2_CH4OUT + default 0 + range 0 1 + ---help--- + TIM2 Channel 4 output IDLE + +config STM32_TIM3_CH1POL + int "TIM3 Channel 1 Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM3_CH1OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM3_CH1OUT + default 0 + range 0 1 + ---help--- + TIM3 Channel 1 output polarity + +config STM32_TIM3_CH1IDLE + int "TIM3 Channel 1 Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM3_CH1OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM3_CH1OUT + default 0 + range 0 1 + ---help--- + TIM3 Channel 1 output IDLE + +config STM32_TIM3_CH2POL + int "TIM3 Channel 2 Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM3_CH2OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM3_CH2OUT + default 0 + range 0 1 + ---help--- + TIM3 Channel 2 output polarity + +config STM32_TIM3_CH2IDLE + int "TIM3 Channel 2 Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM3_CH2OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM3_CH2OUT + default 0 + range 0 1 + ---help--- + TIM3 Channel 2 output IDLE + +config STM32_TIM3_CH3POL + int "TIM3 Channel 3 Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM3_CH3OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM3_CH3OUT + default 0 + range 0 1 + ---help--- + TIM3 Channel 3 output polarity + +config STM32_TIM3_CH3IDLE + int "TIM3 Channel 3 Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM3_CH3OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM3_CH3OUT + default 0 + range 0 1 + ---help--- + TIM3 Channel 3 output IDLE + +config STM32_TIM3_CH4POL + int "TIM3 Channel 4 Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM3_CH4OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM3_CH4OUT + default 0 + range 0 1 + ---help--- + TIM3 Channel 4 output polarity + +config STM32_TIM3_CH4IDLE + int "TIM3 Channel 4 Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM3_CH4OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM3_CH4OUT + default 0 + range 0 1 + ---help--- + TIM3 Channel 4 output IDLE + +config STM32_TIM4_CH1POL + int "TIM4 Channel 1 Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM4_CH1OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM4_CH1OUT + default 0 + range 0 1 + ---help--- + TIM4 Channel 1 output polarity + +config STM32_TIM4_CH1IDLE + int "TIM4 Channel 1 Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM4_CH1OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM4_CH1OUT + default 0 + range 0 1 + ---help--- + TIM4 Channel 1 output IDLE + +config STM32_TIM4_CH2POL + int "TIM4 Channel 2 Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM4_CH2OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM4_CH2OUT + default 0 + range 0 1 + ---help--- + TIM4 Channel 2 output polarity + +config STM32_TIM4_CH2IDLE + int "TIM4 Channel 2 Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM4_CH2OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM4_CH2OUT + default 0 + range 0 1 + ---help--- + TIM4 Channel 2 output IDLE + +config STM32_TIM4_CH3POL + int "TIM4 Channel 3 Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM4_CH3OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM4_CH3OUT + default 0 + range 0 1 + ---help--- + TIM4 Channel 3 output polarity + +config STM32_TIM4_CH3IDLE + int "TIM4 Channel 3 Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM4_CH3OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM4_CH3OUT + default 0 + range 0 1 + ---help--- + TIM4 Channel 3 output IDLE + +config STM32_TIM4_CH4POL + int "TIM4 Channel 4 Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM4_CH4OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM4_CH4OUT + default 0 + range 0 1 + ---help--- + TIM4 Channel 4 output polarity + +config STM32_TIM4_CH4IDLE + int "TIM4 Channel 4 Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM4_CH4OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM4_CH4OUT + default 0 + range 0 1 + ---help--- + TIM4 Channel 4 output IDLE + +config STM32_TIM5_CH1POL + int "TIM5 Channel 1 Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM5_CH1OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM5_CH1OUT + default 0 + range 0 1 + ---help--- + TIM5 Channel 1 output polarity + +config STM32_TIM5_CH1IDLE + int "TIM5 Channel 1 Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM5_CH1OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM5_CH1OUT + default 0 + range 0 1 + ---help--- + TIM5 Channel 1 output IDLE + +config STM32_TIM5_CH2POL + int "TIM5 Channel 2 Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM5_CH2OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM5_CH2OUT + default 0 + range 0 1 + ---help--- + TIM5 Channel 2 output polarity + +config STM32_TIM5_CH2IDLE + int "TIM5 Channel 2 Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM5_CH2OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM5_CH2OUT + default 0 + range 0 1 + ---help--- + TIM5 Channel 2 output IDLE + +config STM32_TIM5_CH3POL + int "TIM5 Channel 3 Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM5_CH3OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM5_CH3OUT + default 0 + range 0 1 + ---help--- + TIM5 Channel 3 output polarity + +config STM32_TIM5_CH3IDLE + int "TIM5 Channel 3 Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM5_CH3OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM5_CH3OUT + default 0 + range 0 1 + ---help--- + TIM5 Channel 3 output IDLE + +config STM32_TIM5_CH4POL + int "TIM5 Channel 4 Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM5_CH4OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM5_CH4OUT + default 0 + range 0 1 + ---help--- + TIM5 Channel 4 output polarity + +config STM32_TIM5_CH4IDLE + int "TIM5 Channel 4 Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM5_CH4OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM5_CH4OUT + default 0 + range 0 1 + ---help--- + TIM5 Channel 4 output IDLE + +config STM32_TIM8_CH1POL + int "TIM8 Channel 1 Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM8_CH1OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM8_CH1OUT + default 0 + range 0 1 + ---help--- + TIM8 Channel 1 output polarity + +config STM32_TIM8_CH1IDLE + int "TIM8 Channel 1 Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM8_CH1OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM8_CH1OUT + default 0 + range 0 1 + ---help--- + TIM8 Channel 1 output IDLE + +config STM32_TIM8_CH1NPOL + int "TIM8 Channel 1 Complementary Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM8_CH1NOUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM8_CH1NOUT + default 0 + range 0 1 + ---help--- + TIM8 Channel 1 Complementary Output polarity + +config STM32_TIM8_CH1NIDLE + int "TIM8 Channel 1 Complementary Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM8_CH1NOUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM8_CH1NOUT + default 0 + range 0 1 + ---help--- + TIM8 Channel 1 Complementary Output IDLE + +config STM32_TIM8_CH2POL + int "TIM8 Channel 2 Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM8_CH2OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM8_CH2OUT + default 0 + range 0 1 + ---help--- + TIM8 Channel 2 output polarity + +config STM32_TIM8_CH2IDLE + int "TIM8 Channel 2 Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM8_CH2OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM8_CH2OUT + default 0 + range 0 1 + ---help--- + TIM8 Channel 2 output IDLE + +config STM32_TIM8_CH2NPOL + int "TIM8 Channel 2 Complementary Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM8_CH2NOUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM8_CH2NOUT + default 0 + range 0 1 + ---help--- + TIM8 Channel 2 Complementary Output polarity + +config STM32_TIM8_CH2NIDLE + int "TIM8 Channel 2 Complementary Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM8_CH2NOUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM8_CH2NOUT + default 0 + range 0 1 + ---help--- + TIM8 Channel 2 Complementary Output IDLE + +config STM32_TIM8_CH3POL + int "TIM8 Channel 3 Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM8_CH3OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM8_CH3OUT + default 0 + range 0 1 + ---help--- + TIM8 Channel 3 output polarity + +config STM32_TIM8_CH3IDLE + int "TIM8 Channel 3 Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM8_CH3OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM8_CH3OUT + default 0 + range 0 1 + ---help--- + TIM8 Channel 3 output IDLE + +config STM32_TIM8_CH3NPOL + int "TIM8 Channel 3 Complementary Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM8_CH3NOUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM8_CH3NOUT + default 0 + range 0 1 + ---help--- + TIM8 Channel 3 Complementary Output polarity + +config STM32_TIM8_CH3NIDLE + int "TIM8 Channel 3 Complementary Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM8_CH3NOUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM8_CH3NOUT + default 0 + range 0 1 + ---help--- + TIM8 Channel 3 Complementary Output IDLE + +config STM32_TIM8_CH4POL + int "TIM8 Channel 4 Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM8_CH4OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM8_CH4OUT + default 0 + range 0 1 + ---help--- + TIM8 Channel 4 output polarity + +config STM32_TIM8_CH4IDLE + int "TIM8 Channel 4 Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM8_CH4OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM8_CH4OUT + default 0 + range 0 1 + ---help--- + TIM8 Channel 4 output IDLE + +config STM32_TIM8_CH5POL + int "TIM8 Channel 5 Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM8_CH5OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM8_CH5OUT + default 0 + range 0 1 + ---help--- + TIM8 Channel 5 output polarity + +config STM32_TIM8_CH5IDLE + int "TIM8 Channel 5 Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM8_CH5OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM8_CH5OUT + default 0 + range 0 1 + ---help--- + TIM8 Channel 5 output IDLE + +config STM32_TIM8_CH6POL + int "TIM8 Channel 6 Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM8_CH6OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM8_CH6OUT + default 0 + range 0 1 + ---help--- + TIM8 Channel 6 output polarity + +config STM32_TIM8_CH6IDLE + int "TIM8 Channel 6 Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM8_CH6OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM8_CH6OUT + default 0 + range 0 1 + ---help--- + TIM8 Channel 6 output IDLE + +config STM32_TIM9_CH1POL + int "TIM9 Channel 1 Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM9_CH1OUT || (ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4) && STM32_TIM9_CH1OUT + default 0 + range 0 1 + ---help--- + TIM9 Channel 1 output polarity + +config STM32_TIM9_CH1IDLE + int "TIM9 Channel 1 Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM9_CH1OUT || (ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4) && STM32_TIM9_CH1OUT + default 0 + range 0 1 + ---help--- + TIM9 Channel 1 output IDLE + +config STM32_TIM9_CH2POL + int "TIM9 Channel 2 Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM9_CH2OUT || (ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4) && STM32_TIM9_CH2OUT + default 0 + range 0 1 + ---help--- + TIM9 Channel 2 output polarity + +config STM32_TIM9_CH2IDLE + int "TIM9 Channel 2 Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM9_CH2OUT || (ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4) && STM32_TIM9_CH2OUT + default 0 + range 0 1 + ---help--- + TIM9 Channel 2 output IDLE + +config STM32_TIM10_CH1POL + int "TIM10 Channel 1 Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM10_CH1OUT || (ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4) && STM32_TIM10_CH1OUT + default 0 + range 0 1 + ---help--- + TIM10 Channel 1 output polarity + +config STM32_TIM10_CH1IDLE + int "TIM10 Channel 1 Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM10_CH1OUT || (ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4) && STM32_TIM10_CH1OUT + default 0 + range 0 1 + ---help--- + TIM10 Channel 1 output IDLE + +config STM32_TIM11_CH1POL + int "TIM11 Channel 1 Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM11_CH1OUT || (ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4) && STM32_TIM11_CH1OUT + default 0 + range 0 1 + ---help--- + TIM11 Channel 1 output polarity + +config STM32_TIM11_CH1IDLE + int "TIM11 Channel 1 Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM11_CH1OUT || (ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4) && STM32_TIM11_CH1OUT + default 0 + range 0 1 + ---help--- + TIM11 Channel 1 output IDLE + +config STM32_TIM12_CH1POL + int "TIM12 Channel 1 Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM12_CH1OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM12_CH1OUT + default 0 + range 0 1 + ---help--- + TIM12 Channel 1 output polarity + +config STM32_TIM12_CH1IDLE + int "TIM12 Channel 1 Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM12_CH1OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM12_CH1OUT + default 0 + range 0 1 + ---help--- + TIM12 Channel 1 output IDLE + +config STM32_TIM12_CH2POL + int "TIM12 Channel 2 Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM12_CH2OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM12_CH2OUT + default 0 + range 0 1 + ---help--- + TIM12 Channel 2 output polarity + +config STM32_TIM12_CH2IDLE + int "TIM12 Channel 2 Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM12_CH2OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM12_CH2OUT + default 0 + range 0 1 + ---help--- + TIM12 Channel 2 output IDLE + +config STM32_TIM13_CH1POL + int "TIM13 Channel 1 Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM13_CH1OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM13_CH1OUT + default 0 + range 0 1 + ---help--- + TIM13 Channel 1 output polarity + +config STM32_TIM13_CH1IDLE + int "TIM13 Channel 1 Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM13_CH1OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM13_CH1OUT + default 0 + range 0 1 + ---help--- + TIM13 Channel 1 output IDLE + +config STM32_TIM14_CH1POL + int "TIM14 Channel 1 Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM14_CH1OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM14_CH1OUT + default 0 + range 0 1 + ---help--- + TIM14 Channel 1 output polarity + +config STM32_TIM14_CH1IDLE + int "TIM14 Channel 1 Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM14_CH1OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM14_CH1OUT + default 0 + range 0 1 + ---help--- + TIM14 Channel 1 output IDLE + +config STM32_TIM15_CH1POL + int "TIM15 Channel 1 Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM15_CH1OUT || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM15_CH1OUT + default 0 + range 0 1 + ---help--- + TIM15 Channel 1 output polarity + +config STM32_TIM15_CH1IDLE + int "TIM15 Channel 1 Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM15_CH1OUT || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM15_CH1OUT + default 0 + range 0 1 + ---help--- + TIM15 Channel 1 output IDLE + +config STM32_TIM15_CH1NPOL + int "TIM15 Channel 1 Complementary Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM15_CH1NOUT || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM15_CH1NOUT + default 0 + range 0 1 + ---help--- + TIM15 Channel 1 Complementary Output polarity + +config STM32_TIM15_CH1NIDLE + int "TIM15 Channel 1 Complementary Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM15_CH1NOUT || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM15_CH1NOUT + default 0 + range 0 1 + ---help--- + TIM15 Channel 1 Complementary Output IDLE + +config STM32_TIM15_CH2POL + int "TIM15 Channel 2 Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM15_CH2OUT || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM15_CH2OUT + default 0 + range 0 1 + ---help--- + TIM15 Channel 2 output polarity + +config STM32_TIM15_CH2IDLE + int "TIM15 Channel 2 Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM15_CH2OUT || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM15_CH2OUT + default 0 + range 0 1 + ---help--- + TIM15 Channel 2 output IDLE + +config STM32_TIM15_CH2NPOL + int "TIM15 Channel 2 Complementary Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM15_CH2NOUT || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM15_CH2NOUT + default 0 + range 0 1 + ---help--- + TIM15 Channel 2 Complementary Output polarity + +config STM32_TIM15_CH2NIDLE + int "TIM15 Channel 2 Complementary Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM15_CH2NOUT || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM15_CH2NOUT + default 0 + range 0 1 + ---help--- + TIM15 Channel 2 Complementary Output IDLE + +config STM32_TIM16_CH1POL + int "TIM16 Channel 1 Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM16_CH1OUT || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM16_CH1OUT + default 0 + range 0 1 + ---help--- + TIM16 Channel 1 output polarity + +config STM32_TIM16_CH1IDLE + int "TIM16 Channel 1 Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM16_CH1OUT || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM16_CH1OUT + default 0 + range 0 1 + ---help--- + TIM16 Channel 1 output IDLE + +config STM32_TIM17_CH1POL + int "TIM17 Channel 1 Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM17_CH1OUT || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM17_CH1OUT + default 0 + range 0 1 + ---help--- + TIM17 Channel 1 output polarity + +config STM32_TIM17_CH1IDLE + int "TIM17 Channel 1 Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM17_CH1OUT || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM17_CH1OUT + default 0 + range 0 1 + ---help--- + TIM17 Channel 1 output IDLE + +config STM32_QENCODER_DISABLE_EXTEND16BTIMERS + bool "Disable QEncoder timers extension from 16-bit to 32-bit" + depends on STM32_HAVE_QENCODER_16BIT + ---help--- + Disable the extension of 16-bit timers to 32-bit via interrupt-based + overflow tracking. When enabled, timers will use their native hardware + counter width (16-bit or 32-bit). This reduces interrupt overhead but + limits the position range for 16-bit timers. + +config STM32_QENCODER_INDEX_PIN + bool "Enable QEncoder timers support for index pin" + depends on STM32_HAVE_QENCODER_16BIT + ---help--- + Enable support for quadrature encoder index pin. The index pin can be + used to reset the encoder position to a known value when the index + pulse is detected. + +config STM32_TIM1_QE + bool "TIM1 QE" + depends on (STM32_QENCODER_MAIN && STM32_TIM1) || (STM32_HAVE_IP_TIMERS && STM32_TIM1) + select STM32_QE if STM32_QENCODER_STM32 && STM32_TIM1 + ---help--- + Reserve TIM1 for use by QEncoder. + +config STM32_TIM1_QEPSC + int "TIM1 QE pulse prescaler" + depends on (STM32_QENCODER_MAIN || STM32_QENCODER_F0) && STM32_TIM1_QE + default 1 + ---help--- + This prescaler divides the number of recorded encoder pulses, + limiting the count rate at the expense of resolution. + +config STM32_TIM2_QE + bool "TIM2 QE" + depends on (STM32_QENCODER_MAIN && STM32_TIM2) || (STM32_HAVE_IP_TIMERS && STM32_TIM2) + select STM32_QE if STM32_QENCODER_STM32 && STM32_TIM2 + ---help--- + Reserve TIM2 for use by QEncoder. + +config STM32_TIM2_QEPSC + int "TIM2 QE pulse prescaler" + depends on (STM32_QENCODER_MAIN || STM32_QENCODER_F0) && STM32_TIM2_QE + default 1 + ---help--- + This prescaler divides the number of recorded encoder pulses, + limiting the count rate at the expense of resolution. + +config STM32_TIM3_QE + bool "TIM3 QE" + depends on (STM32_QENCODER_MAIN && STM32_TIM3) || (STM32_HAVE_IP_TIMERS && STM32_TIM3) + select STM32_QE if STM32_QENCODER_STM32 && STM32_TIM3 + ---help--- + Reserve TIM3 for use by QEncoder. + +config STM32_TIM3_QEPSC + int "TIM3 QE pulse prescaler" + depends on (STM32_QENCODER_MAIN || STM32_QENCODER_F0) && STM32_TIM3_QE + default 1 + ---help--- + This prescaler divides the number of recorded encoder pulses, + limiting the count rate at the expense of resolution. + +config STM32_TIM4_QE + bool "TIM4 QE" + depends on (STM32_QENCODER_MAIN && STM32_TIM4) || (STM32_HAVE_IP_TIMERS && STM32_TIM4) + select STM32_QE if STM32_QENCODER_STM32 && STM32_TIM4 + ---help--- + Reserve TIM4 for use by QEncoder. + +config STM32_TIM4_QEPSC + int "TIM4 QE pulse prescaler" + depends on (STM32_QENCODER_MAIN || STM32_QENCODER_F0) && STM32_TIM4_QE + default 1 + ---help--- + This prescaler divides the number of recorded encoder pulses, + limiting the count rate at the expense of resolution. + +config STM32_TIM5_QE + bool "TIM5 QE" + depends on STM32_QENCODER_MAIN && STM32_TIM5 + select STM32_QE if STM32_QENCODER_STM32 && STM32_TIM5 + ---help--- + Reserve TIM5 for use by QEncoder. + +config STM32_TIM5_QEPSC + int "TIM5 QE pulse prescaler" + depends on STM32_QENCODER_MAIN && STM32_TIM5_QE + default 1 + ---help--- + This prescaler divides the number of recorded encoder pulses, + limiting the count rate at the expense of resolution. + +config STM32_TIM8_QE + bool "TIM8 QE" + depends on STM32_QENCODER_MAIN && STM32_TIM8 + select STM32_QE if STM32_QENCODER_STM32 && STM32_TIM8 + ---help--- + Reserve TIM8 for use by QEncoder. + +config STM32_TIM8_QEPSC + int "TIM8 QE pulse prescaler" + depends on STM32_QENCODER_MAIN && STM32_TIM8_QE + default 1 + ---help--- + This prescaler divides the number of recorded encoder pulses, + limiting the count rate at the expense of resolution. + +config STM32_QENCODER_FILTER + bool "Enable filtering on STM32 QEncoder input" + depends on STM32_QENCODER_MAIN || STM32_QENCODER_F0 + default y + ---help--- + Enable input filtering on quadrature encoder channels to reduce noise. + +config STM32_TIM16_CH1NOUT + bool "TIM16 Channel 1 Complementary Output" + depends on (STM32_HAVE_IP_TIMERS || STM32_COMMON_L4_L5_U5) && STM32_TIM16_PWM && STM32_PWM_MULTICHAN && STM32_TIM16_CHANNEL1 && STM32_TIM16_CH1OUT + ---help--- + Enables channel 1 complementary output. + +config STM32_TIM17_CH1NOUT + bool "TIM17 Channel 1 Complementary Output" + depends on (STM32_HAVE_IP_TIMERS || STM32_COMMON_L4_L5_U5) && STM32_TIM17_PWM && STM32_PWM_MULTICHAN && STM32_TIM17_CHANNEL1 && STM32_TIM17_CH1OUT + ---help--- + Enables channel 1 complementary output. + +config STM32_TIM15_CAP + bool "TIM15 Capture" + depends on STM32_COMMON_H7_H5 && STM32_TIM15 + select STM32_TIMX_CAP if ARCH_CHIP_STM32H7 && STM32_TIM15 + ---help--- + Reserve timer 15 for use by the capture driver. + +config STM32_TIM16_CAP + bool "TIM16 Capture" + depends on STM32_COMMON_H7_H5 && STM32_TIM16 + select STM32_TIMX_CAP if ARCH_CHIP_STM32H7 && STM32_TIM16 + ---help--- + Reserve timer 16 for use by the capture driver. + +config STM32_TIM17_CAP + bool "TIM17 Capture" + depends on STM32_COMMON_H7_H5 && STM32_TIM17 + select STM32_TIMX_CAP if ARCH_CHIP_STM32H7 && STM32_TIM17 + ---help--- + Reserve timer 17 for use by the capture driver. + +config STM32_TIM15_CLOCK + int "TIM15 capture frequency (Hz)" + depends on ARCH_CHIP_STM32H7 && STM32_TIM15_CAP + default 100000 + ---help--- + This clock frequency determines the timer's counting rate. + +config STM32_TIM16_CLOCK + int "TIM16 capture frequency (Hz)" + depends on ARCH_CHIP_STM32H7 && STM32_TIM16_CAP + default 100000 + ---help--- + This clock frequency determines the timer's counting rate. + +config STM32_TIM17_CLOCK + int "TIM17 capture frequency (Hz)" + depends on ARCH_CHIP_STM32H7 && STM32_TIM17_CAP + default 100000 + ---help--- + This clock frequency determines the timer's counting rate. + +config STM32_LPTIM1_CAP + bool "LPTIM1 Capture" + depends on ARCH_CHIP_STM32H7 && STM32_LPTIM1 + default n + select STM32_TIMX_CAP + ---help--- + Reserve low-power timer 1 for use by the capture driver. + +config STM32_LPTIM1_CLOCK + int "LPTIM1 capture frequency (Hz)" + depends on ARCH_CHIP_STM32H7 && STM32_LPTIM1_CAP + default 100000 + ---help--- + This clock frequency determines the timer's counting rate. + +config STM32_LPTIM2_CAP + bool "LPTIM2 Capture" + depends on ARCH_CHIP_STM32H7 && STM32_LPTIM2 + default n + select STM32_TIMX_CAP + ---help--- + Reserve low-power timer 2 for use by the capture driver. + +config STM32_LPTIM2_CLOCK + int "LPTIM2 capture frequency (Hz)" + depends on ARCH_CHIP_STM32H7 && STM32_LPTIM2_CAP + default 100000 + ---help--- + This clock frequency determines the timer's counting rate. + +config STM32_LPTIM1_CHANNEL + int "LPTIM1 Capture Input Channel" + depends on (ARCH_CHIP_STM32H7 && STM32_LPTIM1_CAP) || (ARCH_CHIP_STM32L4 && STM32_LPTIM1_PWM && !STM32_PWM_MULTICHAN) + default 1 + range 1 2 if ARCH_CHIP_STM32H7 && STM32_LPTIM1_CAP + range 1 1 if ARCH_CHIP_STM32L4 && STM32_LPTIM1_PWM && !STM32_PWM_MULTICHAN + ---help--- + Specifies the timer input channel {1,2} for LPTIM1. + +config STM32_LPTIM2_CHANNEL + int "LPTIM2 Capture Input Channel" + depends on (ARCH_CHIP_STM32H7 && STM32_LPTIM2_CAP) || (ARCH_CHIP_STM32L4 && STM32_LPTIM2_PWM && !STM32_PWM_MULTICHAN) + default 1 + range 1 2 if ARCH_CHIP_STM32H7 && STM32_LPTIM2_CAP + range 1 1 if ARCH_CHIP_STM32L4 && STM32_LPTIM2_PWM && !STM32_PWM_MULTICHAN + ---help--- + Specifies the timer input channel {1,2} for LPTIM2. + +config STM32_LPTIM3_CAP + bool "LPTIM3 Capture" + depends on ARCH_CHIP_STM32H7 && STM32_LPTIM3 + default n + select STM32_TIMX_CAP + ---help--- + Reserve low-power timer 3 for use by the capture driver. + +config STM32_LPTIM3_CHANNEL + int "LPTIM3 Capture Input Channel" + depends on ARCH_CHIP_STM32H7 && STM32_LPTIM3_CAP + default 1 + range 1 2 + ---help--- + Specifies the timer input channel {1,2} for LPTIM3. + +config STM32_LPTIM3_CLOCK + int "LPTIM3 capture frequency (Hz)" + depends on ARCH_CHIP_STM32H7 && STM32_LPTIM3_CAP + default 100000 + ---help--- + This clock frequency determines the timer's counting rate. + +config STM32_LPTIM4_CAP + bool "LPTIM4 Capture" + depends on ARCH_CHIP_STM32H7 && STM32_LPTIM4 + default n + select STM32_TIMX_CAP + ---help--- + Reserve low-power timer 4 for use by the capture driver. + +config STM32_LPTIM4_CHANNEL + int "LPTIM4 Capture Input Channel" + depends on ARCH_CHIP_STM32H7 && STM32_LPTIM4_CAP + default 1 + range 1 2 + ---help--- + Specifies the timer input channel {1,2} for LPTIM4. + +config STM32_LPTIM4_CLOCK + int "LPTIM4 capture frequency (Hz)" + depends on ARCH_CHIP_STM32H7 && STM32_LPTIM4_CAP + default 100000 + ---help--- + This clock frequency determines the timer's counting rate. + +config STM32_LPTIM5_CAP + bool "LPTIM5 Capture" + depends on ARCH_CHIP_STM32H7 && STM32_LPTIM5 + default n + select STM32_TIMX_CAP + ---help--- + Reserve low-power timer 5 for use by the capture driver. + +config STM32_LPTIM5_CHANNEL + int "LPTIM5 Capture Input Channel" + depends on ARCH_CHIP_STM32H7 && STM32_LPTIM5_CAP + default 1 + range 1 2 + ---help--- + Specifies the timer input channel {1,2} for LPTIM5. + +config STM32_LPTIM5_CLOCK + int "LPTIM5 capture frequency (Hz)" + depends on ARCH_CHIP_STM32H7 && STM32_LPTIM5_CAP + default 100000 + ---help--- + This clock frequency determines the timer's counting rate. + +config STM32_TICKLESS_ONESHOT + int "Tickless one-shot timer channel" + depends on STM32_COMMON_L4_L5_U5 && SCHED_TICKLESS && STM32_ONESHOT + default 2 + range 1 8 + ---help--- + If the Tickless OS feature is enabled, then one clock must be + assigned to provide the one-shot timer needed by the OS. + +config STM32_TICKLESS_FREERUN + int "Tickless free-running timer channel" + depends on STM32_COMMON_L4_L5_U5 && SCHED_TICKLESS && STM32_FREERUN + default 5 + range 1 8 + ---help--- + If the Tickless OS feature is enabled, then one clock must be + assigned to provide the free-running timer needed by the OS. + +config STM32_LPTIM1_PWM + bool "LPTIM1 PWM" + depends on STM32_COMMON_L4_L5_U5 && STM32_LPTIM1 + select PWM + ---help--- + Reserve low-power timer 1 for use by PWM + + Timer devices may be used for different purposes. One special purpose is + to generate modulated outputs for such things as motor control. If STM32_LPTIM1 + is defined then THIS following may also be defined to indicate that + the timer is intended to be used for pulsed output modulation. + +config STM32_LPTIM2_PWM + bool "LPTIM2 PWM" + depends on STM32_COMMON_L4_L5_U5 && STM32_LPTIM2 + select PWM + ---help--- + Reserve low-power timer 2 for use by PWM + + Timer devices may be used for different purposes. One special purpose is + to generate modulated outputs for such things as motor control. If STM32_LPTIM2 + is defined then THIS following may also be defined to indicate that + the timer is intended to be used for pulsed output modulation. + +config STM32_LPTIM1_CH1OUT + bool "LPTIM1 Channel 1 Output" + depends on STM32_LPTIM1_HAVE_CH1OUT + ---help--- + Enables channel 1 output. + +config STM32_LPTIM1_CH1NOUT + bool "LPTIM1 Channel 1 Complementary Output" + depends on STM32_LPTIM1_HAVE_CH1NOUT + ---help--- + Enables channel 1 complementary output. + +config STM32_LPTIM2_CH1OUT + bool "LPTIM2 Channel 1 Output" + depends on STM32_LPTIM2_HAVE_CH1OUT + ---help--- + Enables channel 1 output. + +config STM32_LPTIM2_CH1NOUT + bool "LPTIM2 Channel 1 Complementary Output" + depends on STM32_LPTIM2_HAVE_CH1NOUT + ---help--- + Enables channel 1 complementary output. + +config STM32_TIM2_CHANNEL5 + bool "TIM2 Channel 4" + depends on STM32_COMMON_L5_U5 && STM32_TIM2_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 4. + +config STM32_TIM3_CHANNEL5 + bool "TIM3 Channel 4" + depends on STM32_COMMON_L5_U5 && STM32_TIM3_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 4. + +config STM32_TIM4_CHANNEL5 + bool "TIM4 Channel 4" + depends on STM32_COMMON_L5_U5 && STM32_TIM4_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 4. + +config STM32_TIM5_CHANNEL5 + bool "TIM5 Channel 4" + depends on STM32_COMMON_L5_U5 && STM32_TIM5_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 4. + +menu "Timer Configuration" + depends on STM32_TIM + +if STM32_TIM9_CAP + +config STM32_TIM9_CLOCK + int "TIM9 work frequency for capture" + default 1000000 + ---help--- + This clock frequency limiting the count rate at the expense of resolution. + +endif # STM32_TIM9_CAP + +if STM32_TIM10_CAP + +config STM32_TIM10_CLOCK + int "TIM10 work frequency for capture" + default 1000000 + ---help--- + This clock frequency limiting the count rate at the expense of resolution. + +endif # STM32_TIM10_CAP + +if STM32_TIM11_CAP + +config STM32_TIM11_CLOCK + int "TIM11 work frequency for capture" + default 1000000 + ---help--- + This clock frequency limiting the count rate at the expense of resolution. + +endif # STM32_TIM11_CAP + +endmenu # Timer Configuration diff --git a/arch/arm/src/common/stm32/Kconfig.uart b/arch/arm/src/common/stm32/Kconfig.uart new file mode 100644 index 0000000000000..55834acea4d7f --- /dev/null +++ b/arch/arm/src/common/stm32/Kconfig.uart @@ -0,0 +1,1250 @@ +# +# STM32 common SERIAL options. +# + +# STM32 USART/UART configuration options. + +# USART/UART per-instance capability flags +# (hidden; driven by default y if / peripheral selects, never by chip selectors) + +config STM32_USART1_HAVE_RXDMA + bool + default y if STM32_STM32C0 && (STM32_DMA2) + default y if STM32_STM32F0 && (STM32_DMA2) + default y if STM32_STM32F10XX && (STM32_DMA1) + default y if STM32_STM32F20XX && (STM32_DMA2) + default y if STM32_STM32F37XX && (STM32_DMA2) + default y if STM32_STM32F4XXX && (STM32_DMA2) + default y if STM32_STM32F779AX && (STM32_DMA2) + default y if STM32_STM32G0 && (STM32_DMA2) + default y if STM32_STM32G4XXX && (STM32_DMA1 || STM32_DMA2) + default y if STM32_STM32H56XXX && (STM32_DMA1 || STM32_DMA2) + default y if ARCH_CHIP_STM32H755XI && (STM32_DMA1 || STM32_DMA2) + default y if STM32_STM32L0 && (STM32_DMA2) + default y if STM32_STM32L15XX && (STM32_DMA1) + default y if STM32_STM32L4S9XX && (STM32_DMA1 || STM32_DMA2 || STM32_DMAMUX) + default y if STM32_STM32L562XX && (STM32_DMA1 || STM32_DMA2 || STM32_DMAMUX) + default y if STM32_STM32U585XX && (STM32_DMA1 || STM32_DMA2 || STM32_DMAMUX) + default y if STM32_WB_PERIPHERALS && (STM32_DMA) + +config STM32_USART1_HAVE_TXDMA + bool + default y if STM32_STM32C0 && (STM32_DMA2) + default y if STM32_STM32F0 && (STM32_DMA2) + default y if STM32_STM32F10XX && (STM32_DMA1) + default y if STM32_STM32F20XX && (STM32_DMA2) + default y if STM32_STM32F37XX && (STM32_DMA2) + default y if STM32_STM32F4XXX && (STM32_DMA2) + default y if STM32_STM32F779AX && (STM32_DMA2) + default y if STM32_STM32G0 && (STM32_DMA2) + default y if STM32_STM32G4XXX && (STM32_DMA1 || STM32_DMA2) + default y if ARCH_CHIP_STM32H755XI && (STM32_DMA1 || STM32_DMA2) + default y if STM32_STM32L0 && (STM32_DMA2) + default y if STM32_STM32L15XX && (STM32_DMA1) + +config STM32_USART2_HAVE_RXDMA + bool + default y if STM32_STM32C0 && (STM32_DMA1) + default y if STM32_STM32F0 && (STM32_DMA1) + default y if STM32_STM32F10XX && (STM32_DMA1) + default y if STM32_STM32F20XX && (STM32_DMA1) + default y if STM32_STM32F37XX && (STM32_DMA1) + default y if STM32_STM32F4XXX && (STM32_DMA1) + default y if STM32_STM32F779AX && (STM32_DMA1) + default y if STM32_STM32G0 && (STM32_DMA1) + default y if STM32_STM32G4XXX && (STM32_DMA1) + default y if STM32_STM32H56XXX && (STM32_DMA1 || STM32_DMA2) + default y if ARCH_CHIP_STM32H755XI && (STM32_DMA1 || STM32_DMA2) + default y if STM32_STM32L0 && (STM32_DMA1) + default y if STM32_STM32L15XX && (STM32_DMA1) + default y if STM32_STM32L4S9XX && (STM32_DMA1 || STM32_DMAMUX) + default y if STM32_STM32L562XX && (STM32_DMA1 || STM32_DMAMUX) + default y if STM32_STM32U585XX && (STM32_DMA1 || STM32_DMAMUX) + +config STM32_USART2_HAVE_TXDMA + bool + default y if STM32_STM32C0 && (STM32_DMA1) + default y if STM32_STM32F0 && (STM32_DMA1) + default y if STM32_STM32F10XX && (STM32_DMA1) + default y if STM32_STM32F20XX && (STM32_DMA1) + default y if STM32_STM32F37XX && (STM32_DMA1) + default y if STM32_STM32F4XXX && (STM32_DMA1) + default y if STM32_STM32F779AX && (STM32_DMA1) + default y if STM32_STM32G0 && (STM32_DMA1) + default y if STM32_STM32G4XXX && (STM32_DMA1) + default y if ARCH_CHIP_STM32H755XI && (STM32_DMA1) + default y if STM32_STM32L0 && (STM32_DMA1) + default y if STM32_STM32L15XX && (STM32_DMA1) + +config STM32_USART3_HAVE_RXDMA + bool + default y if STM32_STM32C0 && (STM32_DMA1) + default y if STM32_STM32F0 && (STM32_DMA1) + default y if STM32_STM32F10XX && (STM32_DMA1) + default y if STM32_STM32F20XX && (STM32_DMA1) + default y if STM32_STM32F37XX && (STM32_DMA1) + default y if STM32_STM32F4XXX && (STM32_DMA1) + default y if STM32_STM32F779AX && (STM32_DMA1) + default y if STM32_STM32G0 && (STM32_DMA1) + default y if STM32_STM32G4XXX && (STM32_DMA1) + default y if STM32_STM32H56XXX && (STM32_DMA1 || STM32_DMA2) + default y if ARCH_CHIP_STM32H755XI && (STM32_DMA1 || STM32_DMA2) + default y if STM32_STM32L0 && (STM32_DMA1) + default y if STM32_STM32L15XX && (STM32_DMA1) + default y if STM32_STM32L4S9XX && (STM32_DMA1 || STM32_DMAMUX) + default y if STM32_STM32L562XX && (STM32_DMA1 || STM32_DMAMUX) + default y if STM32_STM32U585XX && (STM32_DMA1 || STM32_DMAMUX) + +config STM32_USART3_HAVE_TXDMA + bool + default y if STM32_STM32C0 && (STM32_DMA1) + default y if STM32_STM32F0 && (STM32_DMA1) + default y if STM32_STM32F10XX && (STM32_DMA1) + default y if STM32_STM32F20XX && (STM32_DMA1) + default y if STM32_STM32F37XX && (STM32_DMA1) + default y if STM32_STM32F4XXX && (STM32_DMA1) + default y if STM32_STM32F779AX && (STM32_DMA1) + default y if STM32_STM32G0 && (STM32_DMA1) + default y if STM32_STM32G4XXX && (STM32_DMA1) + default y if ARCH_CHIP_STM32H755XI && (STM32_DMA1) + default y if STM32_STM32L0 && (STM32_DMA1) + default y if STM32_STM32L15XX && (STM32_DMA1) + +config STM32_UART4_HAVE_RXDMA + bool + default y if STM32_STM32C0 && (STM32_DMA1) + default y if STM32_STM32F0 && (STM32_DMA1) + default y if STM32_STM32F10XX && (STM32_DMA1) + default y if STM32_STM32F20XX && (STM32_DMA1) + default y if STM32_STM32F37XX && (STM32_DMA1) + default y if STM32_STM32F4XXX && (STM32_DMA1) + default y if STM32_STM32F779AX && (STM32_DMA1) + default y if STM32_STM32G0 && (STM32_DMA1) + default y if STM32_STM32G4XXX && (STM32_DMA1) + default y if STM32_STM32H56XXX && (STM32_DMA1 || STM32_DMA2) + default y if ARCH_CHIP_STM32H755XI && (STM32_DMA1 || STM32_DMA2) + default y if STM32_STM32L0 && (STM32_DMA1) + default y if STM32_STM32L15XX && (STM32_DMA1) + default y if STM32_STM32L4S9XX && (STM32_DMA2 || STM32_DMAMUX) + default y if STM32_STM32L562XX && (STM32_DMA2 || STM32_DMAMUX) + default y if STM32_STM32U585XX && (STM32_DMA2 || STM32_DMAMUX) + +config STM32_UART4_HAVE_TXDMA + bool + default y if STM32_STM32C0 && (STM32_DMA1) + default y if STM32_STM32F0 && (STM32_DMA1) + default y if STM32_STM32F10XX && (STM32_DMA1) + default y if STM32_STM32F20XX && (STM32_DMA1) + default y if STM32_STM32F37XX && (STM32_DMA1) + default y if STM32_STM32F4XXX && (STM32_DMA1) + default y if STM32_STM32F779AX && (STM32_DMA1) + default y if STM32_STM32G0 && (STM32_DMA1) + default y if STM32_STM32G4XXX && (STM32_DMA1) + default y if ARCH_CHIP_STM32H755XI && (STM32_DMA1) + default y if STM32_STM32L0 && (STM32_DMA1) + default y if STM32_STM32L15XX && (STM32_DMA1) + +config STM32_UART5_HAVE_RXDMA + bool + default y if STM32_STM32C0 && (STM32_DMA1) + default y if STM32_STM32F0 && (STM32_DMA1) + default y if STM32_STM32F10XX && (STM32_DMA1) + default y if STM32_STM32F20XX && (STM32_DMA1) + default y if STM32_STM32F37XX && (STM32_DMA1) + default y if STM32_STM32F4XXX && (STM32_DMA1) + default y if STM32_STM32F779AX && (STM32_DMA1) + default y if STM32_STM32G0 && (STM32_DMA1) + default y if STM32_STM32G4XXX && (STM32_DMA1) + default y if STM32_STM32H56XXX && (STM32_DMA1 || STM32_DMA2) + default y if ARCH_CHIP_STM32H755XI && (STM32_DMA1 || STM32_DMA2) + default y if STM32_STM32L0 && (STM32_DMA1) + default y if STM32_STM32L15XX && (STM32_DMA1) + default y if STM32_STM32L4S9XX && (STM32_DMA2 || STM32_DMAMUX) + default y if STM32_STM32L562XX && (STM32_DMA2 || STM32_DMAMUX) + default y if STM32_STM32U585XX && (STM32_DMA2 || STM32_DMAMUX) + +config STM32_UART5_HAVE_TXDMA + bool + default y if STM32_STM32C0 && (STM32_DMA1) + default y if STM32_STM32F0 && (STM32_DMA1) + default y if STM32_STM32F10XX && (STM32_DMA1) + default y if STM32_STM32F20XX && (STM32_DMA1) + default y if STM32_STM32F37XX && (STM32_DMA1) + default y if STM32_STM32F4XXX && (STM32_DMA1) + default y if STM32_STM32F779AX && (STM32_DMA1) + default y if STM32_STM32G0 && (STM32_DMA1) + default y if STM32_STM32G4XXX && (STM32_DMA1) + default y if ARCH_CHIP_STM32H755XI && (STM32_DMA1) + default y if STM32_STM32L0 && (STM32_DMA1) + default y if STM32_STM32L15XX && (STM32_DMA1) + +config STM32_USART6_HAVE_RXDMA + bool + default y if STM32_STM32C0 && (STM32_DMA2) + default y if STM32_STM32F0 && (STM32_DMA2) + default y if STM32_STM32F20XX && (STM32_DMA2) + default y if STM32_STM32F4XXX && (STM32_DMA2) + default y if STM32_STM32F779AX && (STM32_DMA2) + default y if STM32_STM32G0 && (STM32_DMA2) + default y if STM32_STM32H56XXX && (STM32_DMA1 || STM32_DMA2) + default y if ARCH_CHIP_STM32H755XI && (STM32_DMA1 || STM32_DMA2) + default y if STM32_STM32L0 && (STM32_DMA2) + +config STM32_USART6_HAVE_TXDMA + bool + default y if STM32_STM32C0 && (STM32_DMA2) + default y if STM32_STM32F0 && (STM32_DMA2) + default y if STM32_STM32F20XX && (STM32_DMA2) + default y if STM32_STM32F4XXX && (STM32_DMA2) + default y if STM32_STM32F779AX && (STM32_DMA2) + default y if STM32_STM32G0 && (STM32_DMA2) + default y if ARCH_CHIP_STM32H755XI && (STM32_DMA2) + default y if STM32_STM32L0 && (STM32_DMA2) + +config STM32_UART7_HAVE_RXDMA + bool + default y if STM32_STM32C0 && (STM32_DMA1) + default y if STM32_STM32F0 && (STM32_DMA1) + default y if STM32_STM32F779AX && (STM32_DMA1) + default y if STM32_STM32G0 && (STM32_DMA1) + default y if STM32_STM32H56XXX && (STM32_DMA1 || STM32_DMA2) + default y if ARCH_CHIP_STM32H755XI && (STM32_DMA1 || STM32_DMA2) + default y if STM32_STM32L0 && (STM32_DMA1) + +config STM32_UART7_HAVE_TXDMA + bool + default y if STM32_STM32C0 && (STM32_DMA1) + default y if STM32_STM32F0 && (STM32_DMA1) + default y if STM32_STM32F779AX && (STM32_DMA1) + default y if STM32_STM32G0 && (STM32_DMA1) + default y if ARCH_CHIP_STM32H755XI && (STM32_DMA1) + default y if STM32_STM32L0 && (STM32_DMA1) + +config STM32_UART8_HAVE_RXDMA + bool + default y if STM32_STM32C0 && (STM32_DMA1) + default y if STM32_STM32F0 && (STM32_DMA1) + default y if STM32_STM32F779AX && (STM32_DMA1) + default y if STM32_STM32G0 && (STM32_DMA1) + default y if STM32_STM32H56XXX && (STM32_DMA1 || STM32_DMA2) + default y if ARCH_CHIP_STM32H755XI && (STM32_DMA1 || STM32_DMA2) + default y if STM32_STM32L0 && (STM32_DMA1) + +config STM32_UART8_HAVE_TXDMA + bool + default y if STM32_STM32C0 && (STM32_DMA1) + default y if STM32_STM32F0 && (STM32_DMA1) + default y if STM32_STM32F779AX && (STM32_DMA1) + default y if STM32_STM32G0 && (STM32_DMA1) + default y if ARCH_CHIP_STM32H755XI && (STM32_DMA1) + default y if STM32_STM32L0 && (STM32_DMA1) + +config STM32_1WIREDRIVER + bool + +config USART1_RXDMA + bool + depends on STM32_USART1 && USART1_SERIALDRIVER && STM32_USART1_HAVE_RXDMA + ---help--- + In high data rate usage, Rx DMA may eliminate Rx overrun errors + +config USART1_TXDMA + bool + depends on STM32_USART1 && USART1_SERIALDRIVER && STM32_USART1_HAVE_TXDMA + ---help--- + In high data rate usage, Tx DMA may reduce CPU load + +config USART2_RXDMA + bool + depends on STM32_USART2 && USART2_SERIALDRIVER && STM32_USART2_HAVE_RXDMA + ---help--- + In high data rate usage, Rx DMA may eliminate Rx overrun errors + +config USART2_TXDMA + bool + depends on STM32_USART2 && USART2_SERIALDRIVER && STM32_USART2_HAVE_TXDMA + ---help--- + In high data rate usage, Tx DMA may reduce CPU load + +config USART3_RXDMA + bool + depends on STM32_USART3 && USART3_SERIALDRIVER && STM32_USART3_HAVE_RXDMA + ---help--- + In high data rate usage, Rx DMA may eliminate Rx overrun errors + +config USART3_TXDMA + bool + depends on STM32_USART3 && USART3_SERIALDRIVER && STM32_USART3_HAVE_TXDMA + ---help--- + In high data rate usage, Tx DMA may reduce CPU load + +config UART4_RXDMA + bool + depends on STM32_UART4 && UART4_SERIALDRIVER && STM32_UART4_HAVE_RXDMA + ---help--- + In high data rate usage, Rx DMA may eliminate Rx overrun errors + +config UART4_TXDMA + bool + depends on STM32_UART4 && UART4_SERIALDRIVER && STM32_UART4_HAVE_TXDMA + ---help--- + In high data rate usage, Tx DMA may reduce CPU load + +config UART5_RXDMA + bool + depends on STM32_UART5 && UART5_SERIALDRIVER && STM32_UART5_HAVE_RXDMA + ---help--- + In high data rate usage, Rx DMA may eliminate Rx overrun errors + +config UART5_TXDMA + bool + depends on STM32_UART5 && UART5_SERIALDRIVER && STM32_UART5_HAVE_TXDMA + ---help--- + In high data rate usage, Tx DMA may reduce CPU load + +config USART6_RXDMA + bool + depends on STM32_USART6 && USART6_SERIALDRIVER && STM32_USART6_HAVE_RXDMA + ---help--- + In high data rate usage, Rx DMA may eliminate Rx overrun errors + +config USART6_TXDMA + bool + depends on STM32_USART6 && USART6_SERIALDRIVER && STM32_USART6_HAVE_TXDMA + ---help--- + In high data rate usage, Tx DMA may reduce CPU load + +config UART7_RXDMA + bool + depends on STM32_UART7 && UART7_SERIALDRIVER && STM32_UART7_HAVE_RXDMA + ---help--- + In high data rate usage, Rx DMA may eliminate Rx overrun errors + +config UART7_TXDMA + bool + depends on STM32_UART7 && UART7_SERIALDRIVER && STM32_UART7_HAVE_TXDMA + ---help--- + In high data rate usage, Tx DMA may reduce CPU load + +config UART8_RXDMA + bool + depends on STM32_UART8 && UART8_SERIALDRIVER && STM32_UART8_HAVE_RXDMA + ---help--- + In high data rate usage, Rx DMA may eliminate Rx overrun errors + +config UART8_TXDMA + bool + depends on STM32_UART8 && UART8_SERIALDRIVER && STM32_UART8_HAVE_TXDMA + ---help--- + In high data rate usage, Tx DMA may reduce CPU load + +config STM32_SERIAL_DISABLE_REORDERING + bool "Disable reordering of ttySx devices." + depends on STM32_USART + ---help--- + NuttX per default reorders the serial ports (/dev/ttySx) so that the + console is always on /dev/ttyS0. If more than one UART is in use this + can, however, have the side-effect that all port mappings + (hardware USART1 -> /dev/ttyS0) change if the console is moved to another + UART. This is in particular relevant if a project uses the USB console + in some boards and a serial console in other boards, but does not + want the side effect of having all serial port names change when just + the console is moved from serial to USB. + +choice + prompt "USART1 Driver Configuration" + depends on STM32_USART1 + default STM32_USART1_SERIALDRIVER + +config STM32_USART1_SERIALDRIVER + bool "Standard serial driver" + select USART1_SERIALDRIVER + select ARCH_HAVE_SERIAL_TERMIOS + select STM32_SERIALDRIVER + +config STM32_USART1_1WIREDRIVER + bool "1-Wire driver" + select STM32_1WIREDRIVER + +config STM32_USART1_HCIUART + bool "Bluetooth HCI-UART" + select STM32_HCIUART + depends on WIRELESS_BLUETOOTH + +endchoice # USART1 Driver Configuration + +choice + prompt "USART2 Driver Configuration" + depends on STM32_USART2 + default STM32_USART2_SERIALDRIVER + +config STM32_USART2_SERIALDRIVER + bool "Standard serial driver" + select USART2_SERIALDRIVER + select ARCH_HAVE_SERIAL_TERMIOS + select STM32_SERIALDRIVER + +config STM32_USART2_1WIREDRIVER + bool "1-Wire driver" + select STM32_1WIREDRIVER + +config STM32_USART2_HCIUART + bool "Bluetooth HCI-UART" + select STM32_HCIUART + depends on WIRELESS_BLUETOOTH + +endchoice # USART2 Driver Configuration + +choice + prompt "USART3 Driver Configuration" + depends on STM32_USART3 + default STM32_USART3_SERIALDRIVER + +config STM32_USART3_SERIALDRIVER + bool "Standard serial driver" + select USART3_SERIALDRIVER + select ARCH_HAVE_SERIAL_TERMIOS + select STM32_SERIALDRIVER + +config STM32_USART3_1WIREDRIVER + bool "1-Wire driver" + select STM32_1WIREDRIVER + +config STM32_USART3_HCIUART + bool "Bluetooth HCI-UART" + select STM32_HCIUART + depends on WIRELESS_BLUETOOTH + +endchoice # USART3 Driver Configuration + +choice + prompt "UART4 Driver Configuration" + depends on STM32_UART4 + default STM32_UART4_SERIALDRIVER + +config STM32_UART4_SERIALDRIVER + bool "Standard serial driver" + select UART4_SERIALDRIVER + select ARCH_HAVE_SERIAL_TERMIOS + select STM32_SERIALDRIVER + +config STM32_UART4_1WIREDRIVER + bool "1-Wire driver" + select STM32_1WIREDRIVER + +endchoice # UART1 Driver Configuration + +choice + prompt "UART5 Driver Configuration" + depends on STM32_UART5 + default STM32_UART5_SERIALDRIVER + +config STM32_UART5_SERIALDRIVER + bool "Standard serial driver" + select UART5_SERIALDRIVER + select ARCH_HAVE_SERIAL_TERMIOS + select STM32_SERIALDRIVER + +config STM32_UART5_1WIREDRIVER + bool "1-Wire driver" + select STM32_1WIREDRIVER + +endchoice # UART5 Driver Configuration + +choice + prompt "USART6 Driver Configuration" + depends on STM32_USART6 + default STM32_USART6_SERIALDRIVER + +config STM32_USART6_SERIALDRIVER + bool "Standard serial driver" + select USART6_SERIALDRIVER + select ARCH_HAVE_SERIAL_TERMIOS + select STM32_SERIALDRIVER + +config STM32_USART6_1WIREDRIVER + bool "1-Wire driver" + select STM32_1WIREDRIVER + +config STM32_USART6_HCIUART + bool "Bluetooth HCI-UART" + select STM32_HCIUART + depends on WIRELESS_BLUETOOTH + +endchoice # USART6 Driver Configuration + +choice + prompt "USART4 Driver Configuration" + depends on STM32_USART4 + default STM32_USART4_SERIALDRIVER + +config STM32_USART4_SERIALDRIVER + bool "Standard serial driver" + select USART4_SERIALDRIVER + select ARCH_HAVE_SERIAL_TERMIOS + select STM32_SERIALDRIVER + +config STM32_USART4_1WIREDRIVER + bool "1-Wire driver" + select STM32_1WIREDRIVER + +endchoice # USART4 Driver Configuration + +choice + prompt "USART5 Driver Configuration" + depends on STM32_USART5 + default STM32_USART5_SERIALDRIVER + +config STM32_USART5_SERIALDRIVER + bool "Standard serial driver" + select USART5_SERIALDRIVER + select ARCH_HAVE_SERIAL_TERMIOS + select STM32_SERIALDRIVER + +config STM32_USART5_1WIREDRIVER + bool "1-Wire driver" + select STM32_1WIREDRIVER + +endchoice # USART5 Driver Configuration + +choice + prompt "USART7 Driver Configuration" + depends on STM32_USART7 + default STM32_USART7_SERIALDRIVER + +config STM32_USART7_SERIALDRIVER + bool "Standard serial driver" + select USART7_SERIALDRIVER + select ARCH_HAVE_SERIAL_TERMIOS + select STM32_SERIALDRIVER + +config STM32_USART7_1WIREDRIVER + bool "1-Wire driver" + select STM32_1WIREDRIVER + +endchoice # USART7 Driver Configuration + +choice + prompt "USART8 Driver Configuration" + depends on STM32_USART8 + default STM32_USART8_SERIALDRIVER + +config STM32_USART8_SERIALDRIVER + bool "Standard serial driver" + select USART8_SERIALDRIVER + select ARCH_HAVE_SERIAL_TERMIOS + select STM32_SERIALDRIVER + +config STM32_USART8_1WIREDRIVER + bool "1-Wire driver" + select STM32_1WIREDRIVER + +endchoice # USART8 Driver Configuration + +choice + prompt "UART7 Driver Configuration" + depends on STM32_HAVE_IP_USART && STM32_UART7 + default STM32_UART7_SERIALDRIVER + +config STM32_UART7_SERIALDRIVER + bool "Standard serial driver" + select UART7_SERIALDRIVER + select ARCH_HAVE_SERIAL_TERMIOS + select STM32_SERIALDRIVER + +config STM32_UART7_1WIREDRIVER + bool "1-Wire driver" + select STM32_1WIREDRIVER + +config STM32_UART7_HCIUART + bool "Bluetooth HCI-UART" + select STM32_HCIUART + depends on WIRELESS_BLUETOOTH + +endchoice # UART7 Driver Configuration + +choice + prompt "UART8 Driver Configuration" + depends on STM32_HAVE_IP_USART && STM32_UART8 + default STM32_UART8_SERIALDRIVER + +config STM32_UART8_SERIALDRIVER + bool "Standard serial driver" + select UART8_SERIALDRIVER + select ARCH_HAVE_SERIAL_TERMIOS + select STM32_SERIALDRIVER + +config STM32_UART8_1WIREDRIVER + bool "1-Wire driver" + select STM32_1WIREDRIVER + +config STM32_UART8_HCIUART + bool "Bluetooth HCI-UART" + select STM32_HCIUART + depends on WIRELESS_BLUETOOTH + +endchoice # UART8 Driver Configuration + +config USART1_RS485 + bool "RS-485 on USART1" + depends on STM32_USART1 && USART1_SERIALDRIVER + ---help--- + Enable RS-485 interface on USART1. Your board config will have to + provide GPIO_USART1_RS485_DIR pin definition. Currently it cannot be + used with USART1_RXDMA. + +if USART1_RS485 + +config USART1_RS485_DIR_POLARITY + int "USART1 RS-485 DIR pin polarity" + default 1 + range 0 1 + ---help--- + Polarity of DIR pin for RS-485 on USART1. Set to state on DIR pin which + enables TX (0 - low / nTXEN, 1 - high / TXEN). + +endif # USART1_RS485 + +config USART2_RS485 + bool "RS-485 on USART2" + depends on STM32_USART2 && USART2_SERIALDRIVER + ---help--- + Enable RS-485 interface on USART2. Your board config will have to + provide GPIO_USART2_RS485_DIR pin definition. Currently it cannot be + used with USART2_RXDMA. + +if USART2_RS485 + +config USART2_RS485_DIR_POLARITY + int "USART2 RS-485 DIR pin polarity" + default 1 + range 0 1 + ---help--- + Polarity of DIR pin for RS-485 on USART2. Set to state on DIR pin which + enables TX (0 - low / nTXEN, 1 - high / TXEN). + +endif # USART2_RS485 + +config USART3_RS485 + bool "RS-485 on USART3" + depends on STM32_USART3 && USART3_SERIALDRIVER + ---help--- + Enable RS-485 interface on USART3. Your board config will have to + provide GPIO_USART3_RS485_DIR pin definition. Currently it cannot be + used with USART3_RXDMA. + +if USART3_RS485 + +config USART3_RS485_DIR_POLARITY + int "USART3 RS-485 DIR pin polarity" + default 1 + range 0 1 + ---help--- + Polarity of DIR pin for RS-485 on USART3. Set to state on DIR pin which + enables TX (0 - low / nTXEN, 1 - high / TXEN). + +endif # USART3_RS485 + +config UART4_RS485 + bool "RS-485 on UART4" + depends on STM32_UART4 && UART4_SERIALDRIVER + ---help--- + Enable RS-485 interface on UART4. Your board config will have to + provide GPIO_UART4_RS485_DIR pin definition. Currently it cannot be + used with UART4_RXDMA. + +if UART4_RS485 + +config UART4_RS485_DIR_POLARITY + int "UART4 RS-485 DIR pin polarity" + default 1 + range 0 1 + ---help--- + Polarity of DIR pin for RS-485 on UART4. Set to state on DIR pin which + enables TX (0 - low / nTXEN, 1 - high / TXEN). + +endif # UART4_RS485 + +config UART5_RS485 + bool "RS-485 on UART5" + depends on STM32_UART5 && UART5_SERIALDRIVER + ---help--- + Enable RS-485 interface on UART5. Your board config will have to + provide GPIO_UART5_RS485_DIR pin definition. Currently it cannot be + used with UART5_RXDMA. + +if UART5_RS485 + +config UART5_RS485_DIR_POLARITY + int "UART5 RS-485 DIR pin polarity" + default 1 + range 0 1 + ---help--- + Polarity of DIR pin for RS-485 on UART5. Set to state on DIR pin which + enables TX (0 - low / nTXEN, 1 - high / TXEN). + +endif # UART5_RS485 + +config USART6_RS485 + bool "RS-485 on USART6" + depends on STM32_USART6 && USART6_SERIALDRIVER + ---help--- + Enable RS-485 interface on USART6. Your board config will have to + provide GPIO_USART6_RS485_DIR pin definition. Currently it cannot be + used with USART6_RXDMA. + +if USART6_RS485 + +config USART6_RS485_DIR_POLARITY + int "USART6 RS-485 DIR pin polarity" + default 1 + range 0 1 + ---help--- + Polarity of DIR pin for RS-485 on USART6. Set to state on DIR pin which + enables TX (0 - low / nTXEN, 1 - high / TXEN). + +endif # USART6_RS485 + +config UART7_RS485 + bool "RS-485 on UART7" + depends on STM32_UART7 && UART7_SERIALDRIVER + ---help--- + Enable RS-485 interface on UART7. Your board config will have to + provide GPIO_UART7_RS485_DIR pin definition. Currently it cannot be + used with UART7_RXDMA. + +if UART7_RS485 + +config UART7_RS485_DIR_POLARITY + int "UART7 RS-485 DIR pin polarity" + default 1 + range 0 1 + ---help--- + Polarity of DIR pin for RS-485 on UART7. Set to state on DIR pin which + enables TX (0 - low / nTXEN, 1 - high / TXEN). + +endif # UART7_RS485 + +config UART8_RS485 + bool "RS-485 on UART8" + depends on STM32_UART8 && UART8_SERIALDRIVER + ---help--- + Enable RS-485 interface on UART8. Your board config will have to + provide GPIO_UART8_RS485_DIR pin definition. Currently it cannot be + used with UART8_RXDMA. + +if UART8_RS485 + +config UART8_RS485_DIR_POLARITY + int "UART8 RS-485 DIR pin polarity" + default 1 + range 0 1 + ---help--- + Polarity of DIR pin for RS-485 on UART8. Set to state on DIR pin which + enables TX (0 - low / nTXEN, 1 - high / TXEN). + +endif # UART8_RS485 + +if UART9_SERIALDRIVER + +config UART9_RS485 + bool "RS-485 on UART9" + default n + depends on STM32_UART9 + ---help--- + Enable RS-485 interface on UART9. Your board config will have to + provide GPIO_UART9_RS485_DIR pin definition. Currently it cannot be + used with UART9_RXDMA. + +config UART9_RS485_DIR_POLARITY + int "UART9 RS-485 DIR pin polarity" + default 1 + range 0 1 + depends on UART9_RS485 + ---help--- + Polarity of DIR pin for RS-485 on UART9. Set to state on DIR pin which + enables TX (0 - low / nTXEN, 1 - high / TXEN). + +config UART9_RXDMA + bool "UART9 RX DMA" + default n + depends on STM32_UART9 && (STM32_DMA1 || STM32_DMA2) + ---help--- + In high data rate usage, Rx DMA may eliminate Rx overrun errors + +endif # UART9_SERIALDRIVER + +if USART10_SERIALDRIVER + +config USART10_RS485 + bool "RS-485 on USART10" + default n + depends on STM32_USART10 + ---help--- + Enable RS-485 interface on USART10. Your board config will have to + provide GPIO_USART10_RS485_DIR pin definition. Currently it cannot be + used with USART10_RXDMA. + +config USART10_RS485_DIR_POLARITY + int "USART10 RS-485 DIR pin polarity" + default 1 + range 0 1 + depends on USART10_RS485 + ---help--- + Polarity of DIR pin for RS-485 on USART10. Set to state on DIR pin which + enables TX (0 - low / nTXEN, 1 - high / TXEN). + +config USART10_RXDMA + bool "USART10 RX DMA" + default n + depends on STM32_USART10 && (STM32_DMA1 || STM32_DMA2) + ---help--- + In high data rate usage, Rx DMA may eliminate Rx overrun errors + +endif # USART10_SERIALDRIVER + +if USART11_SERIALDRIVER + +config USART11_RS485 + bool "RS-485 on USART11" + default n + depends on STM32_USART11 + ---help--- + Enable RS-485 interface on USART11. Your board config will have to + provide GPIO_USART11_RS485_DIR pin definition. Currently it cannot be + used with USART11_RXDMA. + +config USART11_RS485_DIR_POLARITY + int "USART11 RS-485 DIR pin polarity" + default 1 + range 0 1 + depends on USART11_RS485 + ---help--- + Polarity of DIR pin for RS-485 on USART11. Set to state on DIR pin which + enables TX (0 - low / nTXEN, 1 - high / TXEN). + +config USART11_RXDMA + bool "USART11 RX DMA" + default n + depends on STM32_USART11 && (STM32_DMA1 || STM32_DMA2) + ---help--- + In high data rate usage, Rx DMA may eliminate Rx overrun errors + +endif # USART11_SERIALDRIVER + +if UART12_SERIALDRIVER + +config UART12_RS485 + bool "RS-485 on UART12" + default n + depends on STM32_UART12 + ---help--- + Enable RS-485 interface on UART12. Your board config will have to + provide GPIO_UART12_RS485_DIR pin definition. Currently it cannot be + used with UART12_RXDMA. + +config UART12_RS485_DIR_POLARITY + int "UART12 RS-485 DIR pin polarity" + default 1 + range 0 1 + depends on UART12_RS485 + ---help--- + Polarity of DIR pin for RS-485 on UART12. Set to state on DIR pin which + enables TX (0 - low / nTXEN, 1 - high / TXEN). + +config UART12_RXDMA + bool "UART12 RX DMA" + default n + depends on STM32_UART12 && (STM32_DMA1 || STM32_DMA2) + ---help--- + In high data rate usage, Rx DMA may eliminate Rx overrun errors + +endif # UART12_SERIALDRIVER + +config STM32_SERIAL_RXDMA_BUFFER_SIZE + int "Rx DMA buffer size" + depends on STM32_USART && SERIAL_RXDMA + range 32 4096 + default 32 + ---help--- + The DMA buffer size when using RX DMA to emulate a FIFO. + + When streaming data, the generic serial layer will be called + every time the FIFO receives half or this number of bytes. + + Value given here will be rounded up to next multiple of 4 bytes. + +config STM32_FLOWCONTROL_BROKEN + bool "Use Software UART RTS flow control" + depends on STM32_USART + ---help--- + Enable UART RTS flow control using Software. Because STM + Current STM32 have broken HW based RTS behavior (they assert + nRTS after every byte received) Enable this setting workaround + this issue by using software based management of RTS + +config STM32_USART_BREAKS + bool "Add TIOxSBRK to support sending Breaks" + depends on STM32_USART + ---help--- + Add TIOCxBRK routines to send a line break per the STM32 manual, the + break will be a pulse based on the value M. This is not a BSD compatible + break. + +config STM32_SERIALBRK_BSDCOMPAT + bool "Use GPIO To send Break" + depends on STM32_USART_BREAKS + ---help--- + Enable using GPIO on the TX pin to send a BSD compatible break: + TIOCSBRK will start the break and TIOCCBRK will end the break. + The current STM32 U[S]ARTS have no way to leave the break on + (TX=LOW) because software starts the break and then the hardware + automatically clears the break. This makes it difficult to send + a long break. + +config STM32_USART_SINGLEWIRE + bool "Single Wire Support" + depends on STM32_USART + ---help--- + Enable single wire UART support. The option enables support for the + TIOCSSINGLEWIRE ioctl in the STM32 serial driver. + +config STM32_PM_SERIAL_ACTIVITY + int "PM serial activity" + depends on PM + depends on STM32_USART + default 10 + ---help--- + PM activity reported to power management logic on every serial + interrupt. + +config USART1_UNCONFIG_RX_ON_CLOSE + bool "Unconfigure USART1 RX pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && USART1_SERIALDRIVER + +config USART1_UNCONFIG_TX_ON_CLOSE + bool "Unconfigure USART1 TX pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && USART1_SERIALDRIVER + +config USART1_UNCONFIG_DIR_ON_CLOSE + bool "Unconfigure USART1 DIR pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && USART1_SERIALDRIVER && USART1_RS485 + +config USART2_UNCONFIG_RX_ON_CLOSE + bool "Unconfigure USART2 RX pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && USART2_SERIALDRIVER + +config USART2_UNCONFIG_TX_ON_CLOSE + bool "Unconfigure USART2 TX pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && USART2_SERIALDRIVER + +config USART2_UNCONFIG_DIR_ON_CLOSE + bool "Unconfigure USART2 DIR pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && USART2_SERIALDRIVER && USART2_RS485 + +config USART3_UNCONFIG_RX_ON_CLOSE + bool "Unconfigure USART3 RX pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && USART3_SERIALDRIVER + +config USART3_UNCONFIG_TX_ON_CLOSE + bool "Unconfigure USART3 TX pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && USART3_SERIALDRIVER + +config USART3_UNCONFIG_DIR_ON_CLOSE + bool "Unconfigure USART3 DIR pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && USART3_SERIALDRIVER && USART3_RS485 + +config UART4_UNCONFIG_RX_ON_CLOSE + bool "Unconfigure UART4 RX pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && UART4_SERIALDRIVER + +config UART4_UNCONFIG_TX_ON_CLOSE + bool "Unconfigure UART4 TX pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && UART4_SERIALDRIVER + +config UART4_UNCONFIG_DIR_ON_CLOSE + bool "Unconfigure UART4 DIR pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && UART4_SERIALDRIVER && UART4_RS485 + +config UART5_UNCONFIG_RX_ON_CLOSE + bool "Unconfigure UART5 RX pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && UART5_SERIALDRIVER + +config UART5_UNCONFIG_TX_ON_CLOSE + bool "Unconfigure UART5 TX pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && UART5_SERIALDRIVER + +config UART5_UNCONFIG_DIR_ON_CLOSE + bool "Unconfigure UART5 DIR pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && UART5_SERIALDRIVER && UART5_RS485 + +config USART6_UNCONFIG_RX_ON_CLOSE + bool "Unconfigure USART6 RX pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && USART6_SERIALDRIVER + +config USART6_UNCONFIG_TX_ON_CLOSE + bool "Unconfigure USART6 TX pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && USART6_SERIALDRIVER + +config USART6_UNCONFIG_DIR_ON_CLOSE + bool "Unconfigure USART6 DIR pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && USART6_SERIALDRIVER && USART6_RS485 + +config UART7_UNCONFIG_RX_ON_CLOSE + bool "Unconfigure UART7 RX pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && UART7_SERIALDRIVER + +config UART7_UNCONFIG_TX_ON_CLOSE + bool "Unconfigure UART7 TX pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && UART7_SERIALDRIVER + +config UART7_UNCONFIG_DIR_ON_CLOSE + bool "Unconfigure UART7 DIR pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && UART7_SERIALDRIVER && UART7_RS485 + +config UART8_UNCONFIG_RX_ON_CLOSE + bool "Unconfigure UART8 RX pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && UART8_SERIALDRIVER + +config UART8_UNCONFIG_TX_ON_CLOSE + bool "Unconfigure UART8 TX pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && UART8_SERIALDRIVER + +config UART8_UNCONFIG_DIR_ON_CLOSE + bool "Unconfigure UART8 DIR pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && UART8_SERIALDRIVER && UART8_RS485 + +config UART9_UNCONFIG_RX_ON_CLOSE + bool "Unconfigure UART9 RX pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && UART9_SERIALDRIVER + +config UART9_UNCONFIG_TX_ON_CLOSE + bool "Unconfigure UART9 TX pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && UART9_SERIALDRIVER + +config UART9_UNCONFIG_DIR_ON_CLOSE + bool "Unconfigure UART9 DIR pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && UART9_SERIALDRIVER && UART9_RS485 + +config USART10_UNCONFIG_RX_ON_CLOSE + bool "Unconfigure USART10 RX pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && USART10_SERIALDRIVER + +config USART10_UNCONFIG_TX_ON_CLOSE + bool "Unconfigure USART10 TX pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && USART10_SERIALDRIVER + +config USART10_UNCONFIG_DIR_ON_CLOSE + bool "Unconfigure USART10 DIR pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && USART10_SERIALDRIVER && USART10_RS485 + +config USART11_UNCONFIG_RX_ON_CLOSE + bool "Unconfigure USART11 RX pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && USART11_SERIALDRIVER + +config USART11_UNCONFIG_TX_ON_CLOSE + bool "Unconfigure USART11 TX pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && USART11_SERIALDRIVER + +config USART11_UNCONFIG_DIR_ON_CLOSE + bool "Unconfigure USART11 DIR pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && USART11_SERIALDRIVER && USART11_RS485 + +config UART12_UNCONFIG_RX_ON_CLOSE + bool "Unconfigure UART12 RX pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && UART12_SERIALDRIVER + +config UART12_UNCONFIG_TX_ON_CLOSE + bool "Unconfigure UART12 TX pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && UART12_SERIALDRIVER + +config UART12_UNCONFIG_DIR_ON_CLOSE + bool "Unconfigure UART12 DIR pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && UART12_SERIALDRIVER && UART12_RS485 + +config USART1_RXFIFO_THRES + int "USART1 Rx FIFO Threshold" + depends on STM32_HAVE_USART_RXFIFO_THRESHOLD && STM32_USART && STM32_USART1_SERIALDRIVER + default 3 + range 0 5 + ---help--- + Select the Rx FIFO threshold: + + 0 -> 1/8 full + 1 -> 1/4 full + 2 -> 1/2 full + 3 -> 3/4 full + 4 -> 7/8 full + 5 -> Full + + Higher values mean lower interrupt rates and better CPU performance. + Lower values may be needed at high BAUD rates to prevent Rx data + overrun errors. + +config USART2_RXFIFO_THRES + int "USART2 Rx FIFO Threshold" + depends on STM32_HAVE_USART_RXFIFO_THRESHOLD && STM32_USART && STM32_USART2_SERIALDRIVER + default 3 + range 0 5 + ---help--- + Select the Rx FIFO threshold: + + 0 -> 1/8 full + 1 -> 1/4 full + 2 -> 1/2 full + 3 -> 3/4 full + 4 -> 7/8 full + 5 -> Full + + Higher values mean lower interrupt rates and better CPU performance. + Lower values may be needed at high BAUD rates to prevent Rx data + overrun errors. + +if STM32_USART3 + +config USART3_RXFIFO_THRES + int "USART3 Rx FIFO Threshold" + default 3 + range 0 5 + ---help--- + Select the Rx FIFO threshold: + + 0 -> 1/8 full + 1 -> 1/4 full + 2 -> 1/2 full + 3 -> 3/4 full + 4 -> 7/8 full + 5 -> Full + + Higher values mean lower interrupt rates and better CPU performance. + Lower values may be needed at high BAUD rates to prevent Rx data + overrun errors. + +endif # STM32_USART3 + +if STM32_UART4 + +config UART4_RXFIFO_THRES + int "UART4 Rx FIFO Threshold" + default 3 + range 0 5 + ---help--- + Select the Rx FIFO threshold: + + 0 -> 1/8 full + 1 -> 1/4 full + 2 -> 1/2 full + 3 -> 3/4 full + 4 -> 7/8 full + 5 -> Full + + Higher values mean lower interrupt rates and better CPU performance. + Lower values may be needed at high BAUD rates to prevent Rx data + overrun errors. + +endif # STM32_UART4 + +if STM32_UART5 + +config UART5_RXFIFO_THRES + int "UART5 Rx FIFO Threshold" + default 3 + range 0 5 + ---help--- + Select the Rx FIFO threshold: + + 0 -> 1/8 full + 1 -> 1/4 full + 2 -> 1/2 full + 3 -> 3/4 full + 4 -> 7/8 full + 5 -> Full + + Higher values mean lower interrupt rates and better CPU performance. + Lower values may be needed at high BAUD rates to prevent Rx data + overrun errors. + +endif # STM32_UART5 + +if STM32_USART6 + +config USART6_RXFIFO_THRES + int "USART6 Rx FIFO Threshold" + default 3 + range 0 5 + ---help--- + Select the Rx FIFO threshold: + + 0 -> 1/8 full + 1 -> 1/4 full + 2 -> 1/2 full + 3 -> 3/4 full + 4 -> 7/8 full + 5 -> Full + + Higher values mean lower interrupt rates and better CPU performance. + Lower values may be needed at high BAUD rates to prevent Rx data + overrun errors. + +endif # STM32_USART + +if STM32_UART7 + +config UART7_RXFIFO_THRES + int "UART7 Rx FIFO Threshold" + default 3 + range 0 5 + ---help--- + Select the Rx FIFO threshold: + + 0 -> 1/8 full + 1 -> 1/4 full + 2 -> 1/2 full + 3 -> 3/4 full + 4 -> 7/8 full + 5 -> Full + + Higher values mean lower interrupt rates and better CPU performance. + Lower values may be needed at high BAUD rates to prevent Rx data + overrun errors. + +endif # STM32_UART7 + +if STM32_UART8 + +config UART8_RXFIFO_THRES + int "UART8 Rx FIFO Threshold" + default 3 + range 0 5 + ---help--- + Select the Rx FIFO threshold: + + 0 -> 1/8 full + 1 -> 1/4 full + 2 -> 1/2 full + 3 -> 3/4 full + 4 -> 7/8 full + 5 -> Full + + Higher values mean lower interrupt rates and better CPU performance. + Lower values may be needed at high BAUD rates to prevent Rx data + overrun errors. + +endif # STM32_UART8 + +config STM32_USART_INVERT + bool "Signal Invert Support" + depends on STM32_USART + ---help--- + Enable signal inversion UART support. The option enables support for the + TIOCSINVERT ioctl in the STM32F7 serial driver. + +config STM32_USART_SWAP + bool "Swap RX/TX pins support" + depends on STM32_USART + ---help--- + Enable RX/TX pin swapping support. The option enables support for the + TIOCSSWAP ioctl in the STM32F7 serial driver. + +source "arch/arm/src/common/stm32/Kconfig.lpuart" +source "arch/arm/src/common/stm32/Kconfig.hciuart" diff --git a/arch/arm/src/common/stm32/Kconfig.usb b/arch/arm/src/common/stm32/Kconfig.usb new file mode 100644 index 0000000000000..77093092736d0 --- /dev/null +++ b/arch/arm/src/common/stm32/Kconfig.usb @@ -0,0 +1,255 @@ +# +# STM32 common USB options. +# + +# STM32 USB configuration options. + +comment "USB Device Configuration" + +comment "USB Host Configuration" + +menu "USB Full Speed Host Configuration" + depends on STM32_HAVE_USBDRD_HOST && STM32_USBFS_HOST + +config STM32_USBDRD_NCHANNELS + int "Number of host channels" + default 8 + range 1 8 + depends on STM32_HAVE_USBDRD_HOST && STM32_USBFS_HOST + ---help--- + Number of USB host channels to use. + +config STM32_USBDRD_DESCSIZE + int "Descriptor buffer size" + default 128 + depends on STM32_HAVE_USBDRD_HOST && STM32_USBFS_HOST + ---help--- + Size of descriptor/request buffers. + +endmenu + +config STM32_OTG_SOFOUTPUT + bool "OTG SOF output" + depends on STM32_HAVE_OTG_H7 + default n + +config STM32_OTG_USBREGEN + bool "Enable USB voltage regulator" + depends on STM32_HAVE_OTG_H7 + default n + +config STM32_USBHOST_REGDEBUG + bool "Register-Level Debug" + depends on STM32_COMMON_LEGACY && STM32_USBHOST && STM32_USBHOST && DEBUG_USB_INFO || STM32_COMMON_F7_H7 && USBHOST + ---help--- + Enable very low-level register access debug. + +config STM32_USBHOST_PKTDUMP + bool "Packet Dump Debug" + depends on STM32_COMMON_LEGACY && STM32_USBHOST && STM32_USBHOST && DEBUG_USB_INFO || STM32_COMMON_F7_H7 && USBHOST + ---help--- + Dump all incoming and outgoing USB packets. + +config STM32_USBFS_REGDEBUG + bool "Register-Level Debug" + depends on (STM32_COMMON_LEGACY || ARCH_CHIP_STM32H5) && STM32_USBFS && STM32_USBFS && DEBUG_USB_INFO + ---help--- + Enable very low-level register access debug. + +config OTG_ID_GPIO_DISABLE + bool "Disable the use of GPIO_OTG_ID pin." + depends on (STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_OTGFS || ARCH_CHIP_STM32H7 && (STM32_OTGFS || STM32_OTGHS) + ---help--- + Disables/Enables the use of GPIO_OTG_ID pin. This allows non OTG use + cases to reuse this GPIO pin and ensure it is not set incorrectlty + during OS boot. + +menu "STM32_OTG_HS Configuration" + depends on ARCH_CHIP_STM32F7 && STM32_OTGFSHS + +choice + prompt "ULPI Selection" + default STM32_NO_ULPI + +config STM32_NO_ULPI + bool "No External ULPI" + ---help--- + Select to enable the presence of an external ULPI PHY + +config STM32_EXTERNAL_ULPI + bool "External ULPI" + depends on STM32_HAVE_EXTERNAL_ULPI + ---help--- + Select to enable the presence of an external ULPI PHY + +config STM32_INTERNAL_ULPI + bool "Internal ULPI PHY" + depends on STM32_HAVE_INTERNAL_ULPI + ---help--- + Select to enable the internal ULPI for USB HS + +endchoice # "ULPI Selection" + +endmenu # STM32_OTG_HS Configuration + +menu "OTG_HS Configuration" + depends on ARCH_CHIP_STM32H7 && STM32_OTGHS + +config STM32_OTGHS_FS + bool "OTGHS in FS mode" + default n + +choice + prompt "ULPI Selection" + default STM32_OTGHS_NO_ULPI + +config STM32_OTGHS_NO_ULPI + bool "No External ULPI on board." + ---help--- + Select to indicate that there is no external ULPI PHY. This means + the OTG_HS peripheral must use the internal full-speed PHY and will + be limited to full-speed mode. + +config STM32_OTGHS_EXTERNAL_ULPI + bool "External ULPI" + ---help--- + Select to indicate the presence of an external ULPI PHY and use it. + +endchoice # "ULPI Selection" + +endmenu # OTG_HS Configuration + +menu "OTG Configuration" + depends on ARCH_CHIP_STM32H7 && (STM32_OTGFS || STM32_OTGHS) + +choice + prompt "STM32H7 OTGFS role" + depends on STM32_OTGFS + default STM32_OTGFS_USBDEV if USBDEV + default STM32_OTGFS_HOST if !USBDEV && USBHOST + +config STM32_OTGFS_USBDEV + bool "OTGFS as USBDEV" + depends on USBDEV + +config STM32_OTGFS_HOST + bool "OTGFS as HOST" + depends on USBHOST + +endchoice # "STM32H7 OTGFS role" + +choice + prompt "STM32H7 OTGHS role (only USBDEV supported for now)" + depends on STM32_OTGHS + default STM32_OTGHS_USBDEV if USBDEV + +config STM32_OTGHS_USBDEV + bool "OTGHS as USBDEV" + depends on USBDEV + +endchoice # "STM32H7 OTGHS role" + +endmenu # OTG Configuration + +menu "USB FS Host Configuration" + depends on STM32_COMMON_LEGACY && STM32_OTGFS && STM32_USBHOST + +config STM32_OTGFS_RXFIFO_SIZE + int "Rx Packet Size" + default 128 + ---help--- + Size of the RX FIFO in 32-bit words. Default 128 (512 bytes) + +config STM32_OTGFS_NPTXFIFO_SIZE + int "Non-periodic Tx FIFO Size" + default 96 + ---help--- + Size of the non-periodic Tx FIFO in 32-bit words. Default 96 (384 bytes) + +config STM32_OTGFS_PTXFIFO_SIZE + int "Periodic Tx FIFO size" + default 128 + ---help--- + Size of the periodic Tx FIFO in 32-bit words. Default 96 (384 bytes) + +config STM32_OTGFS_DESCSIZE + int "Descriptor Size" + default 128 + ---help--- + Maximum size to allocate for descriptor memory descriptor. Default: 128 + +config STM32_OTGFS_SOFINTR + bool "Enable SOF interrupts" + default n + ---help--- + Enable SOF interrupts. Why would you ever want to do that? + +config STM32_OTGFS_VBUS_CONTROL + bool "Enable VBus Control" + default y + ---help--- + Enable VBus control. Used when the board has VBus sensing and + a power switch for the OTG FS USB port. Disable this config + if the board lacks this USB VBus control circuitry. + +endmenu # USB FS Host Configuration + +menu "USB HS Host Configuration" + depends on STM32_COMMON_LEGACY && STM32_OTGHS && STM32_USBHOST + +config STM32_OTGHS_RXFIFO_SIZE + int "Rx Packet Size" + default 128 + ---help--- + Size of the RX FIFO in 32-bit words. Default 128 (512 bytes) + +config STM32_OTGHS_NPTXFIFO_SIZE + int "Non-periodic Tx FIFO Size" + default 96 + ---help--- + Size of the non-periodic Tx FIFO in 32-bit words. Default 96 (384 bytes) + +config STM32_OTGHS_PTXFIFO_SIZE + int "Periodic Tx FIFO size" + default 128 + ---help--- + Size of the periodic Tx FIFO in 32-bit words. Default 96 (384 bytes) + +config STM32_OTGHS_DESCSIZE + int "Descriptor Size" + default 128 + ---help--- + Maximum size to allocate for descriptor memory descriptor. Default: 128 + +config STM32_OTGHS_SOFINTR + bool "Enable SOF interrupts" + default n + ---help--- + Enable SOF interrupts. Why would you ever want to do that? + +config STM32_OTGHS_VBUS_CONTROL + bool "Enable VBus Control" + default y + ---help--- + Enable VBus control. Used when the board has VBus sensing and + a power switch for the OTG HS USB port. Disable this config + if the board lacks this USB VBus control circuitry. + +endmenu # USB HS Host Configuration + +config STM32_USBDEV_REGDEBUG + bool "OTG USBDEV REGDEBUG" + depends on STM32_COMMON_F7_H7 && USBDEV + +comment "USB Device Configuration" + +config STM32_USB_ITRMP + bool "Re-map USB interrupt" + default STM32_CAN1 + depends on STM32_USB && STM32_STM32F30XX + ---help--- + The legacy USB in the F1 series shared interrupt lines with USB + device and CAN1. In the F3 series, a hardware options was added to + either retain the legacy F1 behavior or to map the USB interrupts to + their own dedicated vectors. The option is available only for the + F3 family and selects the use of the dedicated USB interrupts. diff --git a/arch/arm/src/common/stm32/Make.defs b/arch/arm/src/common/stm32/Make.defs new file mode 100644 index 0000000000000..e932e3a46033e --- /dev/null +++ b/arch/arm/src/common/stm32/Make.defs @@ -0,0 +1,547 @@ +############################################################################ +# arch/arm/src/common/stm32/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +STM32_COMMON_SRCDIR = $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)common$(DELIM)stm32 + +VPATH += common$(DELIM)stm32 +INCLUDES += ${INCDIR_PREFIX}$(STM32_COMMON_SRCDIR) +ARCHINCLUDES += ${INCDIR_PREFIX}$(STM32_COMMON_SRCDIR) +ARCHXXINCLUDES += ${INCDIR_PREFIX}$(STM32_COMMON_SRCDIR) + +# IP-core driver selection notes (see arch/arm/src/common/stm32/Kconfig.have): +# - Some peripherals use a "register-set" symbol that picks the hardware header +# plus a "driver-variant" symbol that picks the .c file below (e.g. FLASH: +# STM32_HAVE_IP_FLASH_M3M4_V1 header + STM32_HAVE_IP_FLASH_M3M4_F2F4 driver). +# - This file is split into a legacy Cortex-M3/M4 block (the F1/F2/F3/F4/G4/L1 +# families, STM32_COMMON_LEGACY) and a Cortex-M0 block (F0/L0/G0/C0, +# ARCH_CORTEXM0). STM32_COMMON_LEGACY -- not a plain Cortex symbol -- gates +# the M3/M4 block because the other Cortex-M4 families (L4/WB/WL5) include +# this file too but provide their own implementation. + +# Architecture-neutral sources used by every STM32 family + +CHIP_CSRCS += stm32_waste.c +CHIP_CSRCS += stm32_uid.c + +ifeq ($(CONFIG_STM32_COMMON_LEGACY),y) + +CHIP_CSRCS += stm32_allocateheap_m3m4_v1.c +CHIP_CSRCS += stm32_start_m3m4_v1.c +CHIP_CSRCS += stm32_lse_m3m4_v1.c +CHIP_CSRCS += stm32_lsi_m3m4_v1.c +CHIP_CSRCS += stm32_irq_m3m4_v1.c +ifneq ($(filter y,$(CONFIG_STM32_HAVE_IP_USART_V1) \ + $(CONFIG_STM32_HAVE_IP_USART_V2) \ + $(CONFIG_STM32_HAVE_IP_USART_V3) \ + $(CONFIG_STM32_HAVE_IP_USART_V4)),) +CHIP_CSRCS += stm32_lowputc_usart_m3m4_v1v2v3v4.c +endif +ifeq ($(CONFIG_STM32_HAVE_IP_GPIO_M3M4_V1),y) +CHIP_CSRCS += stm32_gpio_m3m4_v1v2.c +endif +ifneq ($(filter y,$(CONFIG_STM32_HAVE_IP_EXTI_V1) \ + $(CONFIG_STM32_HAVE_IP_EXTI_V2)),) +CHIP_CSRCS += stm32_exti_gpio_m3m4_v1v2.c +endif +ifeq ($(CONFIG_STM32_HAVE_IP_FLASH_M3M4_L1),y) +CHIP_CSRCS += stm32_flash_m3m4_l1.c +else ifeq ($(CONFIG_STM32_HAVE_IP_FLASH_M3M4_F1F3),y) +CHIP_CSRCS += stm32_flash_m3m4_f1f3.c +else ifeq ($(CONFIG_STM32_HAVE_IP_FLASH_M3M4_F2F4),y) +CHIP_CSRCS += stm32_flash_m3m4_f2f4.c +else ifeq ($(CONFIG_STM32_HAVE_IP_FLASH_M3M4_G4),y) +CHIP_CSRCS += stm32_flash_m3m4_g4.c +endif +ifneq ($(filter y,$(CONFIG_STM32_HAVE_IP_SPI_V1) \ + $(CONFIG_STM32_HAVE_IP_SPI_V2) \ + $(CONFIG_STM32_HAVE_IP_SPI_V3) \ + $(CONFIG_STM32_HAVE_IP_SPI_V4)),) +CHIP_CSRCS += stm32_spi_m3m4_v2v3v4.c +endif +ifeq ($(CONFIG_STM32_HAVE_IP_I2S_M3M4_V1),y) +CHIP_CSRCS += stm32_i2s_m3m4_v1.c +endif +ifeq ($(CONFIG_STM32_HAVE_IP_SDIO_M3M4_V1),y) +CHIP_CSRCS += stm32_sdio_m3m4_v1.c +endif +ifeq ($(CONFIG_STM32_HAVE_IP_TIMERS),y) +CHIP_CSRCS += stm32_tim_m3m4_v1v2v3.c +endif +ifeq ($(CONFIG_STM32_HAVE_IP_CCM_M3M4_V1),y) +CHIP_CSRCS += stm32_ccm_m3m4_v1.c +endif +CHIP_CSRCS += stm32_capture_m3m4_v1.c +ifeq ($(CONFIG_STM32_HAVE_IP_DFUMODE_M3M4_V1),y) +CHIP_CSRCS += stm32_dfumode_m3m4_v1.c +endif + +ifdef CONFIG_STM32_TICKLESS_TIMER +CHIP_CSRCS += stm32_tickless_m3m4_v1.c +else +ifeq ($(CONFIG_ARCH_ARMV6M),y) +CHIP_CSRCS += stm32_timerisr_armv6m.c +else +CHIP_CSRCS += stm32_timerisr_armv7m.c +endif +endif + +ifeq ($(CONFIG_BUILD_PROTECTED),y) +CHIP_CSRCS += stm32_userspace_m3m4_v1.c +CHIP_CSRCS += stm32_mpuinit_m3m4_v1.c +endif + +ifneq ($(CONFIG_ARCH_IDLE_CUSTOM),y) +CHIP_CSRCS += stm32_idle_m3m4_v1.c +endif + +CHIP_CSRCS += stm32_pmstop_m3m4_v1.c +CHIP_CSRCS += stm32_pmstandby_m3m4_v1.c +CHIP_CSRCS += stm32_pmsleep_m3m4_v1.c + +ifneq ($(CONFIG_ARCH_CUSTOM_PMINIT),y) +CHIP_CSRCS += stm32_pminitialize_m3m4_v1.c +endif + +ifeq ($(CONFIG_STM32_USART),y) +ifneq ($(filter y,$(CONFIG_STM32_HAVE_IP_USART_V1) \ + $(CONFIG_STM32_HAVE_IP_USART_V2) \ + $(CONFIG_STM32_HAVE_IP_USART_V3) \ + $(CONFIG_STM32_HAVE_IP_USART_V4)),) +CHIP_CSRCS += stm32_serial_m3m4_v1v2v3v4.c +endif +endif + +ifeq ($(CONFIG_STM32_DMA),y) +ifeq ($(CONFIG_STM32_HAVE_IP_DMA_V1_7CH_DMAMUX),y) +CHIP_CSRCS += stm32_dma_m0_v1_7ch_dmamux.c +else ifeq ($(CONFIG_STM32_HAVE_IP_DMA_V1_7CH),y) +CHIP_CSRCS += stm32_dma_m0_v1_7ch.c +else ifeq ($(CONFIG_STM32_HAVE_IP_DMA_V1_8CH_DMAMUX),y) +CHIP_CSRCS += stm32_dma_m3m4_v1_8ch_dmamux.c +else ifeq ($(CONFIG_STM32_HAVE_IP_DMA_V1_8CH),y) +CHIP_CSRCS += stm32_dma_m3m4_v1_8ch.c +else ifeq ($(CONFIG_STM32_HAVE_IP_DMA_V2_STREAM),y) +CHIP_CSRCS += stm32_dma_m3m4_v2_stream.c +endif +endif + +ifeq ($(CONFIG_TIMER)$(CONFIG_STM32_HAVE_IP_TIMERS),yy) +CHIP_CSRCS += stm32_tim_m3m4_v1v2v3_lowerhalf.c +endif + +ifeq ($(CONFIG_STM32_ONESHOT),y) +CHIP_CSRCS += stm32_oneshot_m3m4_v1.c +CHIP_CSRCS += stm32_oneshot_m3m4_v1_lowerhalf.c +endif + +ifeq ($(CONFIG_STM32_FREERUN),y) +CHIP_CSRCS += stm32_freerun_m3m4_v1.c +endif + +ifeq ($(CONFIG_STM32_HAVE_IP_I2C_M3M4_V1),y) +ifeq ($(CONFIG_STM32_I2C_ALT),y) +CHIP_CSRCS += stm32_i2c_m3m4_v1_alt.c +else ifeq ($(CONFIG_STM32_STM32F4XXX),y) +CHIP_CSRCS += stm32_i2c_m3m4_v1_f40xxx.c +else +CHIP_CSRCS += stm32_i2c_m3m4_v1.c +endif +else ifeq ($(CONFIG_STM32_HAVE_IP_I2C_M3M4_V2),y) +CHIP_CSRCS += stm32_i2c_m3m4_v2.c +ifeq ($(CONFIG_STM32_I2C_SLAVE),y) +CHIP_CSRCS += stm32_i2c_m3m4_v2_slave.c +endif +endif + +ifeq ($(CONFIG_USBDEV),y) +ifeq ($(CONFIG_STM32_USB),y) +ifeq ($(CONFIG_STM32_HAVE_IP_USBDEV_M3M4_V1),y) +CHIP_CSRCS += stm32_usbdev_m3m4_v1.c +endif +endif +ifeq ($(CONFIG_STM32_USBFS),y) +ifeq ($(CONFIG_STM32_HAVE_IP_USBFS_M3M4_V1),y) +CHIP_CSRCS += stm32_usbfs_m3m4_v1.c +endif +endif +ifeq ($(CONFIG_STM32_OTGFS),y) +ifeq ($(CONFIG_STM32_HAVE_IP_OTGFS_M3M4_V1),y) +CHIP_CSRCS += stm32_otgfsdev_m3m4_v1.c +endif +endif +ifeq ($(CONFIG_STM32_OTGHS),y) +ifeq ($(CONFIG_STM32_HAVE_IP_OTGHS_M3M4_V1),y) +CHIP_CSRCS += stm32_otghsdev_m3m4_v1.c +endif +endif +endif + +ifeq ($(CONFIG_STM32_USBHOST),y) +ifeq ($(CONFIG_STM32_OTGFS),y) +ifeq ($(CONFIG_STM32_HAVE_IP_OTGFS_M3M4_V1),y) +CHIP_CSRCS += stm32_otgfshost_m3m4_v1.c +endif +endif +ifeq ($(CONFIG_STM32_OTGHS),y) +ifeq ($(CONFIG_STM32_HAVE_IP_OTGHS_M3M4_V1),y) +CHIP_CSRCS += stm32_otghshost_m3m4_v1.c +endif +endif +ifeq ($(CONFIG_STM32_HAVE_COMMON_USBHOST_DEBUG),y) +ifeq ($(CONFIG_USBHOST_TRACE),y) +CHIP_CSRCS += stm32_usbhost_m3m4_v1.c +else +ifeq ($(CONFIG_DEBUG_USB),y) +CHIP_CSRCS += stm32_usbhost_m3m4_v1.c +endif +endif +endif +endif + +ifeq ($(CONFIG_STM32_ETHMAC),y) +ifeq ($(CONFIG_STM32_HAVE_IP_ETHMAC_M3M4_V1),y) +CHIP_CSRCS += stm32_eth_m3m4_v1.c +endif +endif + +ifeq ($(CONFIG_STM32_PWR)$(CONFIG_STM32_HAVE_IP_PWR_M3M4_V1),yy) +CHIP_CSRCS += stm32_pwr_m3m4_v1.c stm32_exti_pwr_m3m4_v1.c +endif + +ifeq ($(CONFIG_STM32_RTC),y) +ifeq ($(CONFIG_STM32_HAVE_IP_RTC_COUNTER_M3M4_V1),y) +CHIP_CSRCS += stm32_rtcounter_m3m4_v1.c +else ifeq ($(CONFIG_STM32_HAVE_IP_RTCC_M3M4_L1),y) +CHIP_CSRCS += stm32_rtcc_m3m4_l1.c +else ifeq ($(CONFIG_STM32_HAVE_IP_RTCC_M3M4_F4),y) +CHIP_CSRCS += stm32_rtcc_m3m4_f4.c +else ifeq ($(CONFIG_STM32_HAVE_IP_RTCC_M3M4_V1),y) +CHIP_CSRCS += stm32_rtcc_m3m4_v1.c +endif +ifeq ($(CONFIG_RTC_ALARM),y) +CHIP_CSRCS += stm32_exti_alarm_m3m4_v1.c +endif +ifeq ($(CONFIG_RTC_PERIODIC),y) +CHIP_CSRCS += stm32_exti_wakeup_m3m4_v1.c +endif +ifeq ($(CONFIG_RTC_DRIVER)$(CONFIG_STM32_HAVE_IP_RTC_M3M4_V1),yy) +CHIP_CSRCS += stm32_rtc_m3m4_v1_lowerhalf.c +endif +endif + +ifneq ($(filter y,$(CONFIG_STM32_HAVE_IP_ADC_M3M4_V1) \ + $(CONFIG_STM32_HAVE_IP_ADC_M3M4_V2)),) +ifeq ($(CONFIG_STM32_ADC),y) +CHIP_CSRCS += stm32_adc_m3m4_v1v2.c +endif +endif + +ifeq ($(CONFIG_STM32_SDADC),y) +ifeq ($(CONFIG_STM32_HAVE_IP_SDADC_M3M4_V1),y) +CHIP_CSRCS += stm32_sdadc_m3m4_v1.c +endif +endif + +ifneq ($(filter y,$(CONFIG_STM32_HAVE_IP_DAC_M3M4_V1) \ + $(CONFIG_STM32_HAVE_IP_DAC_M3M4_V2)),) +ifeq ($(CONFIG_STM32_DAC),y) +CHIP_CSRCS += stm32_dac_m3m4_v1.c +endif +endif + +ifeq ($(CONFIG_STM32_COMP),y) +ifeq ($(CONFIG_STM32_HAVE_IP_COMP_M3M4_V1),y) +CHIP_CSRCS += stm32_comp_m3m4_v1.c +else ifeq ($(CONFIG_STM32_HAVE_IP_COMP_M3M4_V2),y) +CHIP_CSRCS += stm32_comp_m3m4_v2.c +endif +endif + +ifeq ($(CONFIG_STM32_OPAMP)$(CONFIG_STM32_HAVE_IP_OPAMP_M3M4_V1),yy) +CHIP_CSRCS += stm32_opamp_m3m4_v1.c +endif + +ifeq ($(CONFIG_STM32_HRTIM),y) +ifeq ($(CONFIG_STM32_HAVE_IP_HRTIM_M3M4_V1),y) +CHIP_CSRCS += stm32_hrtim_m3m4_v1.c +endif +endif + +ifeq ($(CONFIG_STM32_1WIREDRIVER),y) +CHIP_CSRCS += stm32_1wire_m3m4_v1.c +endif + +ifeq ($(CONFIG_STM32_HCIUART),y) +CHIP_CSRCS += stm32_hciuart_m3m4_v1.c +endif + +ifeq ($(CONFIG_STM32_RNG)$(CONFIG_STM32_HAVE_IP_RNG_M3M4_V1),yy) +CHIP_CSRCS += stm32_rng_m3m4_v1.c +endif + +ifeq ($(CONFIG_STM32_LTDC),y) +ifeq ($(CONFIG_STM32_HAVE_IP_LTDC_M3M4_V1),y) +CHIP_CSRCS += stm32_ltdc_m3m4_v1.c +endif +endif + +ifeq ($(CONFIG_STM32_DMA2D),y) +ifeq ($(CONFIG_STM32_HAVE_IP_DMA2D_M3M4_V1),y) +CHIP_CSRCS += stm32_dma2d_m3m4_v1.c +endif +endif + +ifeq ($(CONFIG_STM32_PWM),y) +CHIP_CSRCS += stm32_pwm_m3m4_v1v2v3.c +endif + +ifeq ($(CONFIG_STM32_PULSECOUNT),y) +CHIP_CSRCS += stm32_pulsecount_m3m4_v1v2v3.c +endif + +ifeq ($(CONFIG_STM32_CAP),y) +CHIP_CSRCS += stm32_capture_m3m4_v1_lowerhalf.c +endif + +ifeq ($(CONFIG_SENSORS_QENCODER)$(CONFIG_STM32_QE),yy) +CHIP_CSRCS += stm32_qencoder_m3m4_v1v2v3.c +endif + +ifeq ($(CONFIG_STM32_CAN)$(CONFIG_STM32_HAVE_IP_CAN_BXCAN_M3M4_V1),yy) +ifeq ($(CONFIG_STM32_CAN_CHARDRIVER),y) +CHIP_CSRCS += stm32_can_m3m4_v1.c +endif +ifeq ($(CONFIG_STM32_CAN_SOCKET),y) +CHIP_CSRCS += stm32_can_m3m4_v1_sock.c +endif +endif + +ifeq ($(CONFIG_STM32_FDCAN),y) +ifeq ($(CONFIG_STM32_HAVE_IP_FDCAN_MCAN_M3M4_V1),y) +ifeq ($(CONFIG_STM32_FDCAN_CHARDRIVER),y) +CHIP_CSRCS += stm32_fdcan_m3m4_v1.c +endif +ifeq ($(CONFIG_STM32_FDCAN_SOCKET),y) +CHIP_CSRCS += stm32_fdcan_m3m4_v1_sock.c +endif +endif +endif + +ifeq ($(CONFIG_STM32_IWDG)$(CONFIG_STM32_HAVE_IP_WDG_M3M4_V1),yy) +CHIP_CSRCS += stm32_iwdg_m3m4_v1.c +endif + +ifeq ($(CONFIG_STM32_WWDG)$(CONFIG_STM32_HAVE_IP_WDG_M3M4_V1),yy) +CHIP_CSRCS += stm32_wwdg_m3m4_v1.c +endif + +ifeq ($(CONFIG_DEBUG_FEATURES),y) +ifneq ($(filter y,$(CONFIG_STM32_HAVE_IP_DBGMCU_M3M4_V1) \ + $(CONFIG_STM32_HAVE_IP_DBGMCU_M3M4_V2) \ + $(CONFIG_STM32_HAVE_IP_DBGMCU_M3M4_V3)),) +CHIP_CSRCS += stm32_dumpgpio_m3m4_v1.c +endif +endif + +ifeq ($(CONFIG_STM32_AES)$(CONFIG_STM32_HAVE_IP_AES_M3M4_V1),yy) +CHIP_CSRCS += stm32_aes_m3m4_v1.c +endif + +ifeq ($(CONFIG_CRYPTO_CRYPTODEV_HARDWARE)$(CONFIG_STM32_HAVE_IP_CRYPTO_M3M4_V1),yy) +CHIP_CSRCS += stm32_crypto_m3m4_v1.c +endif + +ifeq ($(CONFIG_STM32_BBSRAM),y) +ifeq ($(CONFIG_STM32_HAVE_IP_BBSRAM_M3M4_V1),y) +CHIP_CSRCS += stm32_bbsram_m3m4_v1.c +endif +endif + +ifeq ($(CONFIG_STM32_FMC),y) +ifeq ($(CONFIG_STM32_HAVE_IP_FMC_M3M4_V1),y) +CHIP_CSRCS += stm32_fmc_m3m4_v1.c +endif +endif + +ifeq ($(CONFIG_STM32_FSMC),y) +ifeq ($(CONFIG_STM32_HAVE_IP_FSMC_M3M4_V1),y) +CHIP_CSRCS += stm32_fsmc_m3m4_v1.c +endif +endif + +ifeq ($(CONFIG_STM32_FOC),y) +CHIP_CSRCS += stm32_foc_m3m4_v1.c +endif + +ifeq ($(CONFIG_STM32_CORDIC)$(CONFIG_STM32_HAVE_IP_CORDIC_M3M4_V1),yy) +CHIP_CSRCS += stm32_cordic_m3m4_v1.c +endif + +endif + +ifeq ($(CONFIG_ARCH_CORTEXM0),y) + +CHIP_CSRCS += stm32_irq_m0_v1.c +ifeq ($(CONFIG_STM32_HAVE_IP_USART_V3),y) +CHIP_CSRCS += stm32_lowputc_usart_m0_v3.c +else ifeq ($(CONFIG_STM32_HAVE_IP_USART_V4),y) +CHIP_CSRCS += stm32_lowputc_usart_m0_v4.c +endif +CHIP_CSRCS += stm32_start_m0_v1.c +CHIP_CSRCS += stm32_lsi_m0_v1.c +ifeq ($(CONFIG_STM32_HAVE_IP_GPIO_M0_V1),y) +CHIP_CSRCS += stm32_gpio_m0_v1.c +endif +ifneq ($(filter y,$(CONFIG_STM32_HAVE_IP_EXTI_V1) \ + $(CONFIG_STM32_HAVE_IP_EXTI_V2)),) +CHIP_CSRCS += stm32_exti_gpio_m0_v1.c +endif +ifeq ($(CONFIG_STM32_HAVE_IP_USART_V3),y) +CHIP_CSRCS += stm32_serial_m0_v3.c +else ifeq ($(CONFIG_STM32_HAVE_IP_USART_V4),y) +CHIP_CSRCS += stm32_serial_m0_v4.c +endif + +ifneq ($(CONFIG_STM32_RTC_LSECLOCK)$(CONFIG_LCD_LSECLOCK),) +CHIP_CSRCS += stm32_lse_m0_v1.c +endif + +ifneq ($(CONFIG_ARCH_IDLE_CUSTOM),y) +CHIP_CSRCS += stm32_idle_m0_v1.c +endif + +ifneq ($(CONFIG_SCHED_TICKLESS),y) +ifeq ($(CONFIG_ARCH_ARMV6M),y) +CHIP_CSRCS += stm32_timerisr_armv6m.c +else +CHIP_CSRCS += stm32_timerisr_armv7m.c +endif +endif + +ifeq ($(CONFIG_STM32_PWR),y) +ifeq ($(CONFIG_STM32_HAVE_IP_PWR_M0_V1),y) +CHIP_CSRCS += stm32_pwr_m0_v1.c +else ifeq ($(CONFIG_STM32_HAVE_IP_PWR_G0),y) +CHIP_CSRCS += stm32_pwr_m0_g0.c +endif +endif + +ifeq ($(CONFIG_STM32_DMA),y) +ifeq ($(CONFIG_STM32_HAVE_IP_DMA_V1_7CH_DMAMUX),y) +CHIP_CSRCS += stm32_dma_m0_v1_7ch_dmamux.c +else ifeq ($(CONFIG_STM32_HAVE_IP_DMA_V1_7CH),y) +CHIP_CSRCS += stm32_dma_m0_v1_7ch.c +else ifeq ($(CONFIG_STM32_HAVE_IP_DMA_V1_8CH_DMAMUX),y) +CHIP_CSRCS += stm32_dma_m3m4_v1_8ch_dmamux.c +else ifeq ($(CONFIG_STM32_HAVE_IP_DMA_V1_8CH),y) +CHIP_CSRCS += stm32_dma_m3m4_v1_8ch.c +else ifeq ($(CONFIG_STM32_HAVE_IP_DMA_V2_STREAM),y) +CHIP_CSRCS += stm32_dma_m3m4_v2_stream.c +endif +endif + +ifeq ($(CONFIG_STM32_PROGMEM),y) +ifeq ($(CONFIG_STM32_HAVE_IP_FLASH_M0_G0C0),y) +CHIP_CSRCS += stm32_flash_m0_g0c0.c +else ifeq ($(CONFIG_STM32_HAVE_IP_FLASH_M3M4_L1),y) +CHIP_CSRCS += stm32_flash_m3m4_l1.c +else ifeq ($(CONFIG_STM32_HAVE_IP_FLASH_M3M4_F1F3),y) +CHIP_CSRCS += stm32_flash_m3m4_f1f3.c +else ifeq ($(CONFIG_STM32_HAVE_IP_FLASH_M3M4_F2F4),y) +CHIP_CSRCS += stm32_flash_m3m4_f2f4.c +else ifeq ($(CONFIG_STM32_HAVE_IP_FLASH_M3M4_G4),y) +CHIP_CSRCS += stm32_flash_m3m4_g4.c +endif +endif + +ifeq ($(CONFIG_STM32_HAVE_HSI48),y) +CHIP_CSRCS += stm32_hsi48_m0_v1.c +endif + +ifeq ($(CONFIG_STM32_USB),y) +ifeq ($(CONFIG_STM32_HAVE_IP_USBDEV_M0_V1),y) +CHIP_CSRCS += stm32_usbdev_m0_v1.c +endif +endif + +ifeq ($(CONFIG_STM32_I2C),y) +CHIP_CSRCS += stm32_i2c_m0_v1.c +endif + +ifeq ($(CONFIG_STM32_SPI),y) +CHIP_CSRCS += stm32_spi_m0_v1.c +endif + +ifeq ($(CONFIG_STM32_PWM),y) +CHIP_CSRCS += stm32_pwm_m0_v1.c +endif + +ifeq ($(CONFIG_PULSECOUNT),y) +ifeq ($(CONFIG_STM32_TIM1_PULSECOUNT),y) +CHIP_CSRCS += stm32_pulsecount_m0_v1.c +endif +endif + +ifeq ($(CONFIG_STM32_ADC)$(CONFIG_STM32_HAVE_IP_ADC_M0_V1),yy) +CHIP_CSRCS += stm32_adc_m0_v1.c +endif + +ifeq ($(CONFIG_STM32_AES)$(CONFIG_STM32_HAVE_IP_AES_M0_V1),yy) +CHIP_CSRCS += stm32_aes_m0_v1.c +endif + +ifeq ($(CONFIG_STM32_RNG)$(CONFIG_STM32_HAVE_IP_RNG_M0_V1),yy) +CHIP_CSRCS += stm32_rng_m0_v1.c +endif + +ifeq ($(CONFIG_STM32_TIM)$(CONFIG_STM32_HAVE_IP_TIMERS_M0_V1),yy) +CHIP_CSRCS += stm32_tim_m0_v1.c stm32_tim_m0_v1_lowerhalf.c +endif + +ifeq ($(CONFIG_STM32_IWDG)$(CONFIG_STM32_HAVE_IP_WDG_M0_V1),yy) +CHIP_CSRCS += stm32_iwdg_m0_v1.c +endif + +ifeq ($(CONFIG_STM32_WWDG)$(CONFIG_STM32_HAVE_IP_WDG_M0_V1),yy) +CHIP_CSRCS += stm32_wwdg_m0_v1.c +endif + +ifeq ($(CONFIG_STM32_FDCAN),y) +ifeq ($(CONFIG_STM32_HAVE_IP_FDCAN_MCAN_M0_V1),y) +ifeq ($(CONFIG_STM32_FDCAN_CHARDRIVER),y) +CHIP_CSRCS += stm32_fdcan_m0_v1.c +endif +ifeq ($(CONFIG_STM32_FDCAN_SOCKET),y) +CHIP_CSRCS += stm32_fdcan_m0_v1_sock.c +endif +endif +endif + +ifeq ($(CONFIG_SENSORS_QENCODER),y) +CHIP_CSRCS += stm32_qencoder_m0_v1.c +endif + +endif + +ifeq ($(CONFIG_SENSORS_HALL3PHASE),y) +CHIP_CSRCS += stm32_hall3ph.c +endif diff --git a/arch/arm/src/common/stm32/hardware/stm32_adc.h b/arch/arm/src/common/stm32/hardware/stm32_adc.h new file mode 100644 index 0000000000000..9ad1291ad40eb --- /dev/null +++ b/arch/arm/src/common/stm32/hardware/stm32_adc.h @@ -0,0 +1,58 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/hardware/stm32_adc.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_ADC_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_ADC_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#if defined(CONFIG_STM32_HAVE_IP_ADC_M0_V1) +# include "hardware/stm32_adc_v2_m0.h" +#elif defined(CONFIG_STM32_HAVE_IP_ADC_M3M4_V1) || defined(CONFIG_STM32_HAVE_IP_ADC_M3M4_V2) + +#if defined(CONFIG_STM32_HAVE_IP_ADC_M3M4_V1) && \ + defined(CONFIG_STM32_HAVE_IP_ADC_M3M4_V2) +# error Only one STM32 ADC IP version must be selected +#endif + +#if defined(CONFIG_STM32_HAVE_IP_ADC_M3M4_V1) +# if defined(CONFIG_STM32_STM32L15XX) +# include "stm32_adc_v1l1.h" +# else +# include "stm32_adc_v1.h" +# endif +#elif defined(CONFIG_STM32_HAVE_IP_ADC_M3M4_V2) +# if defined(CONFIG_STM32_STM32G4XXX) +# include "stm32_adc_v2g4.h" +# else +# include "stm32_adc_v2.h" +# endif +#else +# error "STM32 ADC IP version not specified" +#endif +#else +# error "Unsupported STM32 ADC" +#endif + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_ADC_H */ diff --git a/arch/arm/src/stm32/hardware/stm32_adc_v1.h b/arch/arm/src/common/stm32/hardware/stm32_adc_v1.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32_adc_v1.h rename to arch/arm/src/common/stm32/hardware/stm32_adc_v1.h index 2d4432ca128ff..ef09aabbac86d 100644 --- a/arch/arm/src/stm32/hardware/stm32_adc_v1.h +++ b/arch/arm/src/common/stm32/hardware/stm32_adc_v1.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32_adc_v1.h + * arch/arm/src/common/stm32/hardware/stm32_adc_v1.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_ADC_V1_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_ADC_V1_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_ADC_V1_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_ADC_V1_H /**************************************************************************** * Included Files @@ -54,7 +54,7 @@ * - ... */ -#if defined(CONFIG_STM32_HAVE_IP_ADC_V1_BASIC) +#if defined(CONFIG_STM32_HAVE_IP_ADC_M3M4_V1_BASIC) # define HAVE_BASIC_ADC #else # undef HAVE_BASIC_ADC @@ -637,4 +637,4 @@ * Public Function Prototypes ****************************************************************************/ -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_ADC_V1_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_ADC_V1_H */ diff --git a/arch/arm/src/stm32/hardware/stm32_adc_v1l1.h b/arch/arm/src/common/stm32/hardware/stm32_adc_v1l1.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32_adc_v1l1.h rename to arch/arm/src/common/stm32/hardware/stm32_adc_v1l1.h index 68b5beacd860d..919c9f5791932 100644 --- a/arch/arm/src/stm32/hardware/stm32_adc_v1l1.h +++ b/arch/arm/src/common/stm32/hardware/stm32_adc_v1l1.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32_adc_v1l1.h + * arch/arm/src/common/stm32/hardware/stm32_adc_v1l1.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_ADC_V1L1_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_ADC_V1L1_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_ADC_V1L1_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_ADC_V1L1_H /**************************************************************************** * Included Files @@ -568,4 +568,4 @@ * Public Function Prototypes ****************************************************************************/ -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_ADC_V1L1_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_ADC_V1L1_H */ diff --git a/arch/arm/src/stm32/hardware/stm32_adc_v2.h b/arch/arm/src/common/stm32/hardware/stm32_adc_v2.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32_adc_v2.h rename to arch/arm/src/common/stm32/hardware/stm32_adc_v2.h index 09a83fa13bf4a..e8629afef8024 100644 --- a/arch/arm/src/stm32/hardware/stm32_adc_v2.h +++ b/arch/arm/src/common/stm32/hardware/stm32_adc_v2.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32_adc_v2.h + * arch/arm/src/common/stm32/hardware/stm32_adc_v2.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_ADC_V2_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_ADC_V2_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_ADC_V2_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_ADC_V2_H /**************************************************************************** * Included Files @@ -57,7 +57,7 @@ * TODO: definitions for basic STM32 ADC IPv2 (F0, L0) */ -#ifdef CONFIG_STM32_HAVE_IP_ADC_V2_BASIC +#ifdef CONFIG_STM32_HAVE_IP_ADC_M3M4_V2_BASIC # define HAVE_BASIC_ADC # error TODO #else @@ -732,4 +732,4 @@ * Public Function Prototypes ****************************************************************************/ -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_ADC_V2_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_ADC_V2_H */ diff --git a/arch/arm/src/common/stm32/hardware/stm32_adc_v2_m0.h b/arch/arm/src/common/stm32/hardware/stm32_adc_v2_m0.h new file mode 100644 index 0000000000000..645174f463703 --- /dev/null +++ b/arch/arm/src/common/stm32/hardware/stm32_adc_v2_m0.h @@ -0,0 +1,326 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/hardware/stm32_adc_v2_m0.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_ADC_V2_M0_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_ADC_V2_M0_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "chip.h" + +/* STM32 M0 ADC driver: + * - no injected channels + * - no offset registers + * - the F0/L0 family support one sampling time configuration for all + * channels + * - the G0 family support two sampling time configurations + */ + +/* Support for battery voltage */ + +#if 0 +# define HAVE_ADC_VBAT +#else +# undef HAVE_ADC_VBAT +#endif + +/* Support for ADC clock prescaler */ + +#if defined(CONFIG_STM32_STM32L0) || defined(CONFIG_STM32_STM32G0) +# define HAVE_ADC_PRE +#else +# undef HAVE_ADC_PRE +#endif + +/* Support for LCD voltage */ + +#ifdef CONFIG_STM32_HAVE_LCD +# define HAVE_ADC_VLCD +#else +# undef HAVE_ADC_VLCD +#endif + +/* Support for Low frequency mode */ + +#ifdef CONFIG_STM32_ENERGYLITE +# define HAVE_ADC_LFM +#else +# undef HAVE_ADC_LFM +#endif + +#undef ADC_HAVE_INJECTED + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define STM32_ADCCMN_OFFSET 0x0300 + +/* ADC1, ADC2 common - ADC2 not present on STM32 M0/M0+ devices */ + +#define STM32_ADC12CMN_BASE (STM32_ADCCMN_OFFSET+STM32_ADC1_BASE) + +/* Register Offsets *********************************************************/ + +#define STM32_ADC_ISR_OFFSET 0x0000 /* ADC interrupt and status register */ +#define STM32_ADC_IER_OFFSET 0x0004 /* ADC interrupt enable register */ +#define STM32_ADC_CR_OFFSET 0x0008 /* ADC control register */ +#define STM32_ADC_CFGR1_OFFSET 0x000c /* ADC configuration register 1 */ +#define STM32_ADC_CFGR2_OFFSET 0x0010 /* ADC configuration register 2 */ +#define STM32_ADC_SMPR_OFFSET 0x0014 /* ADC sample time register */ +#define STM32_ADC_TR_OFFSET 0x0020 /* ADC watchdog threshold register */ +#define STM32_ADC_AWD2TR_OFFSET 0x0024 /* ADC watchdog 2 threshold register */ +#define STM32_ADC_CHSELR_OFFSET 0x0028 /* ADC channel selection register */ +#define STM32_ADC_AWD3TR_OFFSET 0x002c /* ADC watchdog 3 threshold register */ +#define STM32_ADC_DR_OFFSET 0x0040 /* ADC regular data register */ +#define STM32_ADC_AWD2CR_OFFSET 0x00a0 /* ADC watchdog 2 control register */ +#define STM32_ADC_AWD3CR_OFFSET 0x00a4 /* ADC watchdog 2 control register */ +#define STM32_ADC_CALFACT_OFFSET 0x00b4 /* ADC Calibration factor register */ + +/* Master and Slave ADC Common Registers */ + +#define STM32_ADC_CCR_OFFSET 0x0008 /* Common control register */ + +/* Register Addresses *******************************************************/ + +#define STM32_ADC1_ISR (STM32_ADC1_BASE + STM32_ADC_ISR_OFFSET) +#define STM32_ADC1_IER (STM32_ADC1_BASE + STM32_ADC_IER_OFFSET) +#define STM32_ADC1_CR (STM32_ADC1_BASE + STM32_ADC_CR_OFFSET) +#define STM32_ADC1_CFGR1 (STM32_ADC1_BASE + STM32_ADC_CFGR1_OFFSET) +#define STM32_ADC1_CFGR2 (STM32_ADC1_BASE + STM32_ADC_CFGR2_OFFSET) +#define STM32_ADC1_SMPR (STM32_ADC1_BASE + STM32_ADC_SMPR_OFFSET) +#define STM32_ADC1_TR (STM32_ADC1_BASE + STM32_ADC_TR_OFFSET) +#define STM32_ADC1_AWD2TR (STM32_ADC1_BASE + STM32_ADC_AWD2TR_OFFSET) +#define STM32_ADC1_CHSELR (STM32_ADC1_BASE + STM32_ADC_CHSELR_OFFSET) +#define STM32_ADC1_AWD3TR (STM32_ADC1_BASE + STM32_ADC_AWD3TR_OFFSET) +#define STM32_ADC1_DR (STM32_ADC1_BASE + STM32_ADC_DR_OFFSET) +#define STM32_ADC1_AWD2CR (STM32_ADC1_BASE + STM32_ADC_AWD2CR_OFFSET) +#define STM32_ADC1_AWD3CR (STM32_ADC1_BASE + STM32_ADC_AWD3CR_OFFSET) +#define STM32_ADC1_CALFACT (STM32_ADC1_BASE + STM32_ADC_CALFACT_OFFSET) +#if defined(CONFIG_ARCH_CHIP_STM32G0) +# define STM32_ADC1_CCR (STM32_ADC1_BASE + STM32_ADC_CCR_OFFSET) +#endif + +/* Register Bitfield Definitions ********************************************/ + +/* ADC interrupt and status register (ISR) and + * ADC interrupt enable register (IER) + */ + +#define ADC_INT_ARDY (1 << 0) /* Bit 0: ADC ready */ +#define ADC_INT_EOSMP (1 << 1) /* Bit 1: End of sampling flag */ +#define ADC_INT_EOC (1 << 2) /* Bit 2: End of conversion */ +#define ADC_INT_EOS (1 << 3) /* Bit 3: End of regular sequence flag */ +#define ADC_INT_OVR (1 << 4) /* Bit 4: Overrun */ +#define ADC_INT_AWD (1 << 7) /* Bit 7: Analog watchdog flag */ +#define ADC_INT_EOCAL (1 << 11) /* Bit 11: End of calibration flag */ +#define ADC_INT_CCRDY (1 << 13) /* Bit 13: Channel configuration ready flag*/ + +/* ADC control register */ + +#define ADC_CR_ADEN (1 << 0) /* Bit 0: ADC enable control */ +#define ADC_CR_ADDIS (1 << 1) /* Bit 1: ADC disable command */ +#define ADC_CR_ADSTART (1 << 2) /* Bit 2: ADC start of regular conversion */ +#define ADC_CR_ADSTP (1 << 4) /* Bit 4: ADC stop of regular conversion command */ +#define ADC_CR_ADVREGEN (1 << 28) /* Bit 28: ADC Voltage Regulator Enable */ +#define ADC_CR_ADCAL (1 << 31) /* Bit 31: ADC calibration */ + +/* ADC configuration register 1 */ + +#define ADC_CFGR1_DMAEN (1 << 0) /* Bit 0: Direct memory access enable */ +#define ADC_CFGR1_DMACFG (1 << 1) /* Bit 1: Direct memory access configuration */ +#define ADC_CFGR1_SCANDIR (1 << 2) /* Bit 2: Scan sequence direction */ +#define ADC_CFGR1_RES_SHIFT (3) /* Bits 3-4: Data resolution */ +#define ADC_CFGR1_RES_MASK (3 << ADC_CFGR1_RES_SHIFT) +# define ADC_CFGR1_RES_12BIT (0 << ADC_CFGR1_RES_SHIFT) /* 15 ADCCLK clyes */ +# define ADC_CFGR1_RES_10BIT (1 << ADC_CFGR1_RES_SHIFT) /* 13 ADCCLK clyes */ +# define ADC_CFGR1_RES_8BIT (2 << ADC_CFGR1_RES_SHIFT) /* 11 ADCCLK clyes */ +# define ADC_CFGR1_RES_6BIT (3 << ADC_CFGR1_RES_SHIFT) /* 9 ADCCLK clyes */ + +#define ADC_CFGR1_ALIGN (1 << 5) /* Bit 5: Data Alignment */ +#define ADC_CFGR1_EXTSEL_SHIFT (6) /* Bits 6-8: External trigger selection */ +#define ADC_CFGR1_EXTSEL_MASK (7 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC12_CFGR1_EXTSEL_TRG0 (0 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC12_CFGR1_EXTSEL_TRG1 (1 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC12_CFGR1_EXTSEL_TRG2 (2 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC12_CFGR1_EXTSEL_TRG3 (3 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC12_CFGR1_EXTSEL_TRG4 (4 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC12_CFGR1_EXTSEL_TRG5 (5 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC12_CFGR1_EXTSEL_TRG6 (6 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC12_CFGR1_EXTSEL_TRG7 (7 << ADC_CFGR1_EXTSEL_SHIFT) +#define ADC_CFGR1_EXTEN_SHIFT (10) /* Bits 10-11: External trigger/polarity selection regular channels */ +#define ADC_CFGR1_EXTEN_MASK (3 << ADC_CFGR1_EXTEN_SHIFT) +# define ADC_CFGR1_EXTEN_NONE (0 << ADC_CFGR1_EXTEN_SHIFT) /* Trigger detection disabled */ +# define ADC_CFGR1_EXTEN_RISING (1 << ADC_CFGR1_EXTEN_SHIFT) /* Trigger detection on the rising edge */ +# define ADC_CFGR1_EXTEN_FALLING (2 << ADC_CFGR1_EXTEN_SHIFT) /* Trigger detection on the falling edge */ +# define ADC_CFGR1_EXTEN_BOTH (3 << ADC_CFGR1_EXTEN_SHIFT) /* Trigger detection on both edges */ + +#define ADC_CFGR1_OVRMOD (1 << 12) /* Bit 12: Overrun Mode */ +#define ADC_CFGR1_CONT (1 << 13) /* Bit 13: Continuous mode for regular conversions */ +#define ADC_CFGR1_WAIT (1 << 14) /* Bit 14: Wait conversion mode */ +#define ADC_CFGR1_AUTOFF (1 << 15) /* Bit 15: Auto-off mode */ +#define ADC_CFGR1_DISCEN (1 << 16) /* Bit 16: Discontinuous mode on regular channels */ +#define ADC_CFGR1_CHSELRMOD (1 << 21) /* Bit 21: Mode selection of ADC_CHSELR register */ +#define ADC_CFGR1_AWDSGL (1 << 22) /* Bit 22: Enable watchdog on single/all channels */ +#define ADC_CFGR1_AWDEN (1 << 23) /* Bit 23: Analog watchdog enable */ +#define ADC_CFGR1_AWDCH_SHIFT (26) /* Bits 26-30: Analog watchdog 1 channel select bits */ +#define ADC_CFGR1_AWDCH_MASK (31 << ADC_CFGR1_AWDCH_SHIFT) +# define ADC_CFGR1_AWDCH_DISABLED (0 << ADC_CFGR1_AWDCH_SHIFT) + +/* ADC configuration register 2 */ + +#define ADC_CFGR2_OVSE (1 << 0) /* Bit 1: Oversampler enable */ +#define ADC_CFGR2_OVSR_SHIFT (2) /* Bits 2-4: Oversampling ratio */ +#define ADC_CFGR2_OVSR_MASK (7 << ADC_CFGR2_OVSR_SHIFT) +# define ADC_CFGR2_OVSR_2X (0 << ADC_CFGR2_OVSR_SHIFT) +# define ADC_CFGR2_OVSR_4X (1 << ADC_CFGR2_OVSR_SHIFT) +# define ADC_CFGR2_OVSR_8X (2 << ADC_CFGR2_OVSR_SHIFT) +# define ADC_CFGR2_OVSR_16X (3 << ADC_CFGR2_OVSR_SHIFT) +# define ADC_CFGR2_OVSR_32X (4 << ADC_CFGR2_OVSR_SHIFT) +# define ADC_CFGR2_OVSR_64X (5 << ADC_CFGR2_OVSR_SHIFT) +# define ADC_CFGR2_OVSR_128X (6 << ADC_CFGR2_OVSR_SHIFT) +# define ADC_CFGR2_OVSR_256X (7 << ADC_CFGR2_OVSR_SHIFT) +#define ADC_CFGR2_OVSS_SHIFT (5) /* Bits 5-8: Oversampling shift */ +#define ADC_CFGR2_OVSS_MASK (0xf << ADC_CFGR2_OVSS_SHIFT) +#define ADC_CFGR2_OVSS(sb) ((sb) << ADC_CFGR2_OVSS_SHIFT) /* Shift sb bits */ +# define ADC_CFGR2_OVSS_NONE (0 << ADC_CFGR2_OVSS_SHIFT) +#define ADC_CFGR2_TOVS (1 << 9) /* Bit 9: Triggered oversampling */ + /* Bits 10-28: Reserved */ +#define ADC_CFGR2_LFTRIG (1 << 29) /* Bit 29: Low frequency trigger mode enable */ +#define ADC_CFGR2_CKMODE_SHIFT (30) /* Bits 30-31: ADC clock mode */ +#define ADC_CFGR2_CKMODE_MASK (3 << ADC_CFGR2_CKMODE_SHIFT) +# define ADC_CFGR2_CKMODE_ADCCLK (0 << ADC_CFGR2_CKMODE_SHIFT) /* 00: ADCCLK (Asynchronous) generated at product level */ +# define ADC_CFGR2_CKMODE_PCLKd2 (1 << ADC_CFGR2_CKMODE_SHIFT) /* 01: PCLK/2 (Synchronous clock mode) */ +# define ADC_CFGR2_CKMODE_PCLKd4 (2 << ADC_CFGR2_CKMODE_SHIFT) /* 10: PCLK/4 (Synchronous clock mode) */ + +/* ADC sample time register */ + +#if defined(CONFIG_ARCH_CHIP_STM32C0) || defined(CONFIG_ARCH_CHIP_STM32G0) +# define ADC_SMPR_1p5 (0) /* 000: 1.5 cycles */ +# define ADC_SMPR_3p5 (1) /* 001: 3.5 cycles */ +# define ADC_SMPR_7p5 (2) /* 010: 7.5 cycles */ +# define ADC_SMPR_12p5 (3) /* 011: 12.5 cycles */ +# define ADC_SMPR_19p5 (4) /* 100: 19.5 cycles */ +# define ADC_SMPR_39p5 (5) /* 101: 39.5 cycles */ +# define ADC_SMPR_79p5 (6) /* 110: 79.5 cycles */ +# define ADC_SMPR_160p5 (7) /* 111: 160.5 cycles */ +#else +# define ADC_SMPR_1p5 (0) /* 000: 1.5 cycles */ +# define ADC_SMPR_7p5 (1) /* 001: 7.5 cycles */ +# define ADC_SMPR_13p5 (2) /* 010: 13.5 cycles */ +# define ADC_SMPR_28p5 (3) /* 011: 28.5 cycles */ +# define ADC_SMPR_41p5 (4) /* 100: 41.5 cycles */ +# define ADC_SMPR_55p5 (5) /* 101: 55.5 cycles */ +# define ADC_SMPR_71p5 (6) /* 110: 71.5 cycles */ +# define ADC_SMPR_239p5 (7) /* 111: 239.5 cycles */ +#endif + +#define ADC_SMPR_SMP1_SHIFT (0) /* Bits 0-2: Sampling time selection 1 */ +#define ADC_SMPR_SMP1_MASK (7 << ADC_SMPR_SMP_SHIFT) +#define ADC_SMPR_SMP2_SHIFT (4) /* Bits 4-6: Sampling time selection 2 */ +#define ADC_SMPR_SMP2_MASK (7 << ADC_SMPR_SMP_SHIFT) +#define ADC_SMPR_SMPSEL_SHIFT (8) /* Bits 8-26: channel-x sampling time selection */ +#if defined(CONFIG_ARCH_CHIP_STM32G0) || defined(CONFIG_ARCH_CHIP_STM32C0) +# define ADC_SMPR_SMPSEL(ch, smp) ((smp) << (ADC_SMPR_SMPSEL_SHIFT + ch)) /* ch = [0..22] and smp = 0 or 1 */ +# define ADC_SMPSEL(ch, smp) ((smp) << (ch)) /* For use in adc_sampletime_set */ +#else +# define ADC_SMPR_SMPSEL(ch, smp) (smp << ADC_SMPR_SMPSEL_SHIFT) +#endif + +/* ADC watchdog threshold register */ + +#define ADC_TR_LT_SHIFT (0) /* Bits 0-11: Analog watchdog lower threshold */ +#define ADC_TR_LT_MASK (0x0fff << ADC_TR_LT_SHIFT) +#define ADC_TR_HT_SHIFT (16) /* Bits 16-27: Analog watchdog higher threshold */ +#define ADC_TR_HT_MASK (0x0fff << ADC_TR_HT_SHIFT) + +/* ADC channel selection register */ + +#define ADC_CHSELR_CHSEL0 (1 << 0) /* Select channel 0 */ +#define ADC_CHSELR_CHSEL1 (1 << 1) /* Select channel 1 */ +#define ADC_CHSELR_CHSEL2 (1 << 2) /* Select channel 2 */ +#define ADC_CHSELR_CHSEL3 (1 << 3) /* Select channel 3 */ +#define ADC_CHSELR_CHSEL4 (1 << 4) /* Select channel 4 */ +#define ADC_CHSELR_CHSEL5 (1 << 5) /* Select channel 5 */ +#define ADC_CHSELR_CHSEL6 (1 << 6) /* Select channel 6 */ +#define ADC_CHSELR_CHSEL7 (1 << 7) /* Select channel 7 */ +#define ADC_CHSELR_CHSEL8 (1 << 8) /* Select channel 8 */ +#define ADC_CHSELR_CHSEL9 (1 << 9) /* Select channel 9 */ +#define ADC_CHSELR_CHSEL10 (1 << 10) /* Select channel 10 */ +#define ADC_CHSELR_CHSEL11 (1 << 11) /* Select channel 11 */ +#define ADC_CHSELR_CHSEL12 (1 << 12) /* Select channel 12 */ +#define ADC_CHSELR_CHSEL13 (1 << 13) /* Select channel 13 */ +#define ADC_CHSELR_CHSEL14 (1 << 14) /* Select channel 14 */ +#define ADC_CHSELR_CHSEL15 (1 << 15) /* Select channel 15 */ +#define ADC_CHSELR_CHSEL16 (1 << 16) /* Select channel 16 */ +#define ADC_CHSELR_CHSEL17 (1 << 17) /* Select channel 17 */ +#define ADC_CHSELR_CHSEL18 (1 << 18) /* Select channel 18 */ +#define ADC_CHSELR_CHSEL(ch) (1 << (ch)) + +/* ADC channel selection alternate register + * Enabled when CHSELRMOD = 1 in ADC_CFGR1 + */ + +#if defined(CONFIG_ARCH_CHIP_STM32G0) +# define ADC_CHSELR_ALT_SQN(sqn, ch) ((ch) << (((sqn) - 1) * 4)) /* sqn = [0..8], ch = [0..14] */ +#endif + +#define ADC_DR_RDATA_SHIFT (0) +#define ADC_DR_RDATA_MASK (0xffff << ADC_DR_RDATA_SHIFT) + +/* Analog watchdog 2/3 configuration register */ + +#define ADC_AWDXCR_AWDXCHN(ch) (1 << (ch)) /* ch = [0..18] */ + +/* Calibration factor register */ + +#define ADC_CALFACT_CALFACT_SHIFT (0) +#define ADC_CALFACT_CALFACT_MASK (0x7f << ADC_CALFACT_CALFACT_SHIFT) + +/* Common configuration register */ + +#define ADC_CCR_PRESC_SHIFT (18) /* ADC Prescaler */ +#define ADC_CCR_PRESC_MASK (0xf << ADC_CCR_PRESC_SHIFT) +# define ADC_CCR_PRESC_NOT_DIV (0) +# define ADC_CCR_PRESC_DIV2 (1 << ADC_CCR_PRESC_SHIFT) +# define ADC_CCR_PRESC_DIV4 (2 << ADC_CCR_PRESC_SHIFT) +# define ADC_CCR_PRESC_DIV6 (3 << ADC_CCR_PRESC_SHIFT) +# define ADC_CCR_PRESC_DIV8 (4 << ADC_CCR_PRESC_SHIFT) +# define ADC_CCR_PRESC_DIV10 (5 << ADC_CCR_PRESC_SHIFT) +# define ADC_CCR_PRESC_DIV12 (6 << ADC_CCR_PRESC_SHIFT) +# define ADC_CCR_PRESC_DIV16 (7 << ADC_CCR_PRESC_SHIFT) +# define ADC_CCR_PRESC_DIV32 (8 << ADC_CCR_PRESC_SHIFT) +# define ADC_CCR_PRESC_DIV64 (9 << ADC_CCR_PRESC_SHIFT) +# define ADC_CCR_PRESC_DIV128 (10 << ADC_CCR_PRESC_SHIFT) +# define ADC_CCR_PRESC_DIV256 (11 << ADC_CCR_PRESC_SHIFT) + +#define ADC_CCR_VREFEN (1 << 22) /* Bit 22: VREFINT enable */ +#define ADC_CCR_TSEN (1 << 23) /* Bit 23: Temperature sensor enable */ +#define ADC_CCR_VBATEN (1 << 24) /* Bit 24: VBAT enable */ +#define ADC_CCR_VLCDEN (1 << 24) /* Bit 24: VLCD enable */ +#define ADC_CCR_LFMEN (1 << 25) /* Bit 25: Low Frequency Mode enable */ + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_ADC_V2_M0_H */ diff --git a/arch/arm/src/stm32/hardware/stm32_adc_v2g4.h b/arch/arm/src/common/stm32/hardware/stm32_adc_v2g4.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32_adc_v2g4.h rename to arch/arm/src/common/stm32/hardware/stm32_adc_v2g4.h index 211bff7fe43f5..314244086db37 100644 --- a/arch/arm/src/stm32/hardware/stm32_adc_v2g4.h +++ b/arch/arm/src/common/stm32/hardware/stm32_adc_v2g4.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32_adc_v2g4.h + * arch/arm/src/common/stm32/hardware/stm32_adc_v2g4.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_ADC_V2G4_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_ADC_V2G4_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_ADC_V2G4_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_ADC_V2G4_H /**************************************************************************** * Included Files @@ -866,4 +866,4 @@ #define ADC_CDR_RDATA_SLV_SHIFT (16) /* Bits 16-31: Regular data of the Slave ADC */ #define ADC_CDR_RDATA_SLV_MASK (0xffff << ADC_CDR_RDATA_SLV_SHIFT) -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_ADC_V2G4_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_ADC_V2G4_H */ diff --git a/arch/arm/src/common/stm32/hardware/stm32_aes.h b/arch/arm/src/common/stm32/hardware/stm32_aes.h new file mode 100644 index 0000000000000..2f1342a749235 --- /dev/null +++ b/arch/arm/src/common/stm32/hardware/stm32_aes.h @@ -0,0 +1,101 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/hardware/stm32_aes.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_AES_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_AES_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "chip.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* AES register offsets *****************************************************/ + +#define STM32_AES_CR_OFFSET 0x0000 /* Control Register */ +#define STM32_AES_SR_OFFSET 0x0004 /* Status Register */ +#define STM32_AES_DINR_OFFSET 0x0008 /* Data Input Register */ +#define STM32_AES_DOUTR_OFFSET 0x000C /* Data Output Register */ +#define STM32_AES_KEYR0_OFFSET 0x0010 /* AES Key Register 0 */ +#define STM32_AES_KEYR1_OFFSET 0x0014 /* AES Key Register 1 */ +#define STM32_AES_KEYR2_OFFSET 0x0018 /* AES Key Register 2 */ +#define STM32_AES_KEYR3_OFFSET 0x001C /* AES Key Register 3 */ +#define STM32_AES_IVR0_OFFSET 0x0020 /* AES Initialization Vector Register 0 */ +#define STM32_AES_IVR1_OFFSET 0x0024 /* AES Initialization Vector Register 1 */ +#define STM32_AES_IVR2_OFFSET 0x0028 /* AES Initialization Vector Register 2 */ +#define STM32_AES_IVR3_OFFSET 0x002C /* AES Initialization Vector Register 3 */ + +/* AES register addresses ***************************************************/ + +#define STM32_AES_CR (STM32_AES_BASE + STM32_AES_CR_OFFSET) +#define STM32_AES_SR (STM32_AES_BASE + STM32_AES_SR_OFFSET) +#define STM32_AES_DINR (STM32_AES_BASE + STM32_AES_DINR_OFFSET) +#define STM32_AES_DOUTR (STM32_AES_BASE + STM32_AES_DOUTR_OFFSET) +#define STM32_AES_KEYR0 (STM32_AES_BASE + STM32_AES_KEYR0_OFFSET) +#define STM32_AES_KEYR1 (STM32_AES_BASE + STM32_AES_KEYR1_OFFSET) +#define STM32_AES_KEYR2 (STM32_AES_BASE + STM32_AES_KEYR2_OFFSET) +#define STM32_AES_KEYR3 (STM32_AES_BASE + STM32_AES_KEYR3_OFFSET) +#define STM32_AES_IVR0 (STM32_AES_BASE + STM32_AES_IVR0_OFFSET) +#define STM32_AES_IVR1 (STM32_AES_BASE + STM32_AES_IVR1_OFFSET) +#define STM32_AES_IVR2 (STM32_AES_BASE + STM32_AES_IVR2_OFFSET) +#define STM32_AES_IVR3 (STM32_AES_BASE + STM32_AES_IVR3_OFFSET) + +/* AES register bit definitions *********************************************/ + +/* AES_CR register */ + +#define AES_CR_EN (1 << 0) /* AES Enable */ +#define AES_CR_DATATYPE (1 << 1) /* Data type selection */ +# define AES_CR_DATATYPE_LE (0x0 << 1) +# define AES_CR_DATATYPE_BE (0x2 << 1) + +#define AES_CR_MODE (1 << 3) /* AES Mode of operation */ +# define AES_CR_MODE_ENCRYPT (0x0 << 3) +# define AES_CR_MODE_KEYDERIV (0x1 << 3) +# define AES_CR_MODE_DECRYPT (0x2 << 3) +# define AES_CR_MODE_DECRYPT_KEYDERIV (0x3 << 3) + +#define AES_CR_CHMOD (1 << 5) /* AES Chaining Mode */ +# define AES_CR_CHMOD_ECB (0x0 << 5) +# define AES_CR_CHMOD_CBC (0x1 << 5) +# define AES_CR_CHMOD_CTR (0x2 << 5) + +#define AES_CR_CCFC (1 << 7) /* Computation Complete Flag Clear */ +#define AES_CR_ERRC (1 << 8) /* Error Clear */ +#define AES_CR_CCIE (1 << 9) /* Computation Complete Interrupt Enable */ +#define AES_CR_ERRIE (1 << 10) /* Error Interrupt Enable */ +#define AES_CR_DMAINEN (1 << 11) /* DMA Enable Input */ +#define AES_CR_DMAOUTEN (1 << 12) /* DMA Enable Output */ + +/* AES_SR register */ + +#define AES_SR_CCF (1 << 0) /* Computation Complete Flag */ +#define AES_SR_RDERR (1 << 1) /* Read Error Flag */ +#define AES_SR_WRERR (1 << 2) /* Write Error Flag */ + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_AES_H */ diff --git a/arch/arm/src/common/stm32/hardware/stm32_bkp.h b/arch/arm/src/common/stm32/hardware/stm32_bkp.h new file mode 100644 index 0000000000000..f37ffd14f1680 --- /dev/null +++ b/arch/arm/src/common/stm32/hardware/stm32_bkp.h @@ -0,0 +1,177 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/hardware/stm32_bkp.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_BKP_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_BKP_H + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#if defined(CONFIG_STM32_HIGHDENSITY) || defined(CONFIG_STM32_CONNECTIVITYLINE) +# define CONFIG_STM32_NBKP_BYTES 84 +# define CONFIG_STM32_NBKP_REGS 42 +#else +# define CONFIG_STM32_NBKP_BYTES 20 +# define CONFIG_STM32_NBKP_REGS 10 +#endif + +/* Register Offsets *********************************************************/ + +#if defined(CONFIG_STM32_HIGHDENSITY) || defined(CONFIG_STM32_CONNECTIVITYLINE) +# define STM32_BKP_DR_OFFSET(n) ((n) > 10 ? 0x0040+4*((n)-10) : 0x0004+4*(n)) +#else +# define STM32_BKP_DR_OFFSET(n) (0x0004+4*(n)) +#endif + +#define STM32_BKP_DR1_OFFSET 0x0004 /* Backup data register 1 */ +#define STM32_BKP_DR2_OFFSET 0x0008 /* Backup data register 2 */ +#define STM32_BKP_DR3_OFFSET 0x000c /* Backup data register 3 */ +#define STM32_BKP_DR4_OFFSET 0x0010 /* Backup data register 4 */ +#define STM32_BKP_DR5_OFFSET 0x0014 /* Backup data register 5 */ +#define STM32_BKP_DR6_OFFSET 0x0018 /* Backup data register 6 */ +#define STM32_BKP_DR7_OFFSET 0x001c /* Backup data register 7 */ +#define STM32_BKP_DR8_OFFSET 0x0020 /* Backup data register 8 */ +#define STM32_BKP_DR9_OFFSET 0x0024 /* Backup data register 9 */ +#define STM32_BKP_DR10_OFFSET 0x0028 /* Backup data register 10 */ + +#define STM32_BKP_RTCCR_OFFSET 0x002c /* RTC clock calibration register */ +#define STM32_BKP_CR_OFFSET 0x0030 /* Backup control register */ +#define STM32_BKP_CSR_OFFSET 0x0034 /* Backup control/status register */ + +#if defined(CONFIG_STM32_HIGHDENSITY) || defined(CONFIG_STM32_CONNECTIVITYLINE) +# define STM32_BKP_DR11_OFFSET 0x0040 /* Backup data register 11 */ +# define STM32_BKP_DR12_OFFSET 0x0044 /* Backup data register 12 */ +# define STM32_BKP_DR13_OFFSET 0x0048 /* Backup data register 13 */ +# define STM32_BKP_DR14_OFFSET 0x004c /* Backup data register 14 */ +# define STM32_BKP_DR15_OFFSET 0x0050 /* Backup data register 15 */ +# define STM32_BKP_DR16_OFFSET 0x0054 /* Backup data register 16 */ +# define STM32_BKP_DR17_OFFSET 0x0058 /* Backup data register 17 */ +# define STM32_BKP_DR18_OFFSET 0x005c /* Backup data register 18 */ +# define STM32_BKP_DR19_OFFSET 0x0060 /* Backup data register 19 */ +# define STM32_BKP_DR20_OFFSET 0x0064 /* Backup data register 20 */ +# define STM32_BKP_DR21_OFFSET 0x0068 /* Backup data register 21 */ +# define STM32_BKP_DR22_OFFSET 0x006c /* Backup data register 22 */ +# define STM32_BKP_DR23_OFFSET 0x0070 /* Backup data register 23 */ +# define STM32_BKP_DR24_OFFSET 0x0074 /* Backup data register 24 */ +# define STM32_BKP_DR25_OFFSET 0x0078 /* Backup data register 25 */ +# define STM32_BKP_DR26_OFFSET 0x007c /* Backup data register 26 */ +# define STM32_BKP_DR27_OFFSET 0x0080 /* Backup data register 27 */ +# define STM32_BKP_DR28_OFFSET 0x0084 /* Backup data register 28 */ +# define STM32_BKP_DR29_OFFSET 0x0088 /* Backup data register 29 */ +# define STM32_BKP_DR30_OFFSET 0x008c /* Backup data register 30 */ +# define STM32_BKP_DR31_OFFSET 0x0090 /* Backup data register 31 */ +# define STM32_BKP_DR32_OFFSET 0x0094 /* Backup data register 32 */ +# define STM32_BKP_DR33_OFFSET 0x0098 /* Backup data register 33 */ +# define STM32_BKP_DR34_OFFSET 0x009c /* Backup data register 34 */ +# define STM32_BKP_DR35_OFFSET 0x00a0 /* Backup data register 35 */ +# define STM32_BKP_DR36_OFFSET 0x00a4 /* Backup data register 36 */ +# define STM32_BKP_DR37_OFFSET 0x00a8 /* Backup data register 37 */ +# define STM32_BKP_DR38_OFFSET 0x00ac /* Backup data register 38 */ +# define STM32_BKP_DR39_OFFSET 0x00b0 /* Backup data register 39 */ +# define STM32_BKP_DR40_OFFSET 0x00b4 /* Backup data register 40 */ +# define STM32_BKP_DR41_OFFSET 0x00b8 /* Backup data register 41 */ +# define STM32_BKP_DR42_OFFSET 0x00bc /* Backup data register 42 */ +#endif + +/* Register Addresses *******************************************************/ + +#define STM32_BKP_RTCCR (STM32_BKP_BASE+STM32_BKP_RTCCR_OFFSET) +#define STM32_BKP_CR (STM32_BKP_BASE+STM32_BKP_CR_OFFSET) +#define STM32_BKP_CSR (STM32_BKP_BASE+STM32_BKP_CSR_OFFSET) + +#define STM32_BKP_DR(n) (STM32_BKP_BASE+STM32_BKP_DR_OFFSET(n)) +#define STM32_BKP_DR1 (STM32_BKP_BASE+STM32_BKP_DR1_OFFSET) +#define STM32_BKP_DR2 (STM32_BKP_BASE+STM32_BKP_DR2_OFFSET) +#define STM32_BKP_DR3 (STM32_BKP_BASE+STM32_BKP_DR3_OFFSET) +#define STM32_BKP_DR4 (STM32_BKP_BASE+STM32_BKP_DR4_OFFSET) +#define STM32_BKP_DR5 (STM32_BKP_BASE+STM32_BKP_DR5_OFFSET) +#define STM32_BKP_DR6 (STM32_BKP_BASE+STM32_BKP_DR6_OFFSET) +#define STM32_BKP_DR7 (STM32_BKP_BASE+STM32_BKP_DR7_OFFSET) +#define STM32_BKP_DR8 (STM32_BKP_BASE+STM32_BKP_DR8_OFFSET) +#define STM32_BKP_DR9 (STM32_BKP_BASE+STM32_BKP_DR9_OFFSET) +#define STM32_BKP_DR10 (STM32_BKP_BASE+STM32_BKP_DR10_OFFSET) + +#if defined(CONFIG_STM32_HIGHDENSITY) || defined(CONFIG_STM32_CONNECTIVITYLINE) +# define STM32_BKP_DR11 (STM32_BKP_BASE+STM32_BKP_DR11_OFFSET) +# define STM32_BKP_DR12 (STM32_BKP_BASE+STM32_BKP_DR12_OFFSET) +# define STM32_BKP_DR13 (STM32_BKP_BASE+STM32_BKP_DR13_OFFSET) +# define STM32_BKP_DR14 (STM32_BKP_BASE+STM32_BKP_DR14_OFFSET) +# define STM32_BKP_DR15 (STM32_BKP_BASE+STM32_BKP_DR15_OFFSET) +# define STM32_BKP_DR16 (STM32_BKP_BASE+STM32_BKP_DR16_OFFSET) +# define STM32_BKP_DR17 (STM32_BKP_BASE+STM32_BKP_DR17_OFFSET) +# define STM32_BKP_DR18 (STM32_BKP_BASE+STM32_BKP_DR18_OFFSET) +# define STM32_BKP_DR19 (STM32_BKP_BASE+STM32_BKP_DR19_OFFSET) +# define STM32_BKP_DR20 (STM32_BKP_BASE+STM32_BKP_DR20_OFFSET) +# define STM32_BKP_DR21 (STM32_BKP_BASE+STM32_BKP_DR21_OFFSET) +# define STM32_BKP_DR22 (STM32_BKP_BASE+STM32_BKP_DR22_OFFSET) +# define STM32_BKP_DR23 (STM32_BKP_BASE+STM32_BKP_DR23_OFFSET) +# define STM32_BKP_DR24 (STM32_BKP_BASE+STM32_BKP_DR24_OFFSET) +# define STM32_BKP_DR25 (STM32_BKP_BASE+STM32_BKP_DR25_OFFSET) +# define STM32_BKP_DR26 (STM32_BKP_BASE+STM32_BKP_DR26_OFFSET) +# define STM32_BKP_DR27 (STM32_BKP_BASE+STM32_BKP_DR27_OFFSET) +# define STM32_BKP_DR28 (STM32_BKP_BASE+STM32_BKP_DR28_OFFSET) +# define STM32_BKP_DR29 (STM32_BKP_BASE+STM32_BKP_DR29_OFFSET) +# define STM32_BKP_DR30 (STM32_BKP_BASE+STM32_BKP_DR30_OFFSET) +# define STM32_BKP_DR31 (STM32_BKP_BASE+STM32_BKP_DR31_OFFSET) +# define STM32_BKP_DR32 (STM32_BKP_BASE+STM32_BKP_DR32_OFFSET) +# define STM32_BKP_DR33 (STM32_BKP_BASE+STM32_BKP_DR33_OFFSET) +# define STM32_BKP_DR34 (STM32_BKP_BASE+STM32_BKP_DR34_OFFSET) +# define STM32_BKP_DR35 (STM32_BKP_BASE+STM32_BKP_DR35_OFFSET) +# define STM32_BKP_DR36 (STM32_BKP_BASE+STM32_BKP_DR36_OFFSET) +# define STM32_BKP_DR37 (STM32_BKP_BASE+STM32_BKP_DR37_OFFSET) +# define STM32_BKP_DR38 (STM32_BKP_BASE+STM32_BKP_DR38_OFFSET) +# define STM32_BKP_DR39 (STM32_BKP_BASE+STM32_BKP_DR39_OFFSET) +# define STM32_BKP_DR40 (STM32_BKP_BASE+STM32_BKP_DR40_OFFSET) +# define STM32_BKP_DR41 (STM32_BKP_BASE+STM32_BKP_DR41_OFFSET) +# define STM32_BKP_DR42 (STM32_BKP_BASE+STM32_BKP_DR42_OFFSET) +#endif + +/* Register Bitfield Definitions ********************************************/ + +/* RTC clock calibration register */ + +#define BKP_RTCCR_CAL_SHIFT (0) /* Bits 6-0: Calibration value */ +#define BKP_RTCCR_CAL_MASK (0x7f << BKP_RTCCR_CAL_SHIFT) +#define BKP_RTCCR_CCO (1 << 7) /* Bit 7: Calibration Clock Output */ +#define BKP_RTCCR_ASOE (1 << 8) /* Bit 8: Alarm or Second Output Enable */ +#define BKP_RTCCR_ASOS (1 << 9) /* Bit 9: Alarm or Second Output Selection */ + +/* Backup control register */ + +#define BKP_CR_TPE (1 << 0) /* Bit 0: TAMPER pin enable */ +#define BKP_CR_TPAL (1 << 1) /* Bit 1: TAMPER pin active level */ + +/* Backup control/status register */ + +#define BKP_CSR_CTE (1 << 0) /* Bit 0: Clear Tamper event */ +#define BKP_CSR_CTI (1 << 1) /* Bit 1: Clear Tamper Interrupt */ +#define BKP_CSR_TPIE (1 << 2) /* Bit 2: TAMPER Pin interrupt enable */ +#define BKP_CSR_TEF (1 << 8) /* Bit 8: Tamper Event Flag */ +#define BKP_CSR_TIF (1 << 9) /* Bit 9: Tamper Interrupt Flag */ + +/* Backup data register */ + +#define BKP_DR_SHIFT (0) /* Bits 1510: Backup data */ +#define BKP_DR_MASK (0xffff << BKP_DR_SHIFT) + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_BKP_H */ diff --git a/arch/arm/src/common/stm32/hardware/stm32_can.h b/arch/arm/src/common/stm32/hardware/stm32_can.h new file mode 100644 index 0000000000000..6f8bdc2d273ae --- /dev/null +++ b/arch/arm/src/common/stm32/hardware/stm32_can.h @@ -0,0 +1,43 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/hardware/stm32_can.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_CAN_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_CAN_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#if (defined(CONFIG_STM32_HAVE_IP_CAN_BXCAN_M0_V1) + \ + defined(CONFIG_STM32_HAVE_IP_CAN_BXCAN_M3M4_V1)) > 1 +# error Only one STM32 CAN IP version must be selected +#endif + +#if defined(CONFIG_STM32_HAVE_IP_CAN_BXCAN_M0_V1) +# include "hardware/stm32_can_bxcan_m0.h" +#elif defined(CONFIG_STM32_HAVE_IP_CAN_BXCAN_M3M4_V1) +# include "hardware/stm32_can_bxcan.h" +#else +# error "Unsupported STM32 CAN" +#endif + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_CAN_H */ diff --git a/arch/arm/src/common/stm32/hardware/stm32_can_bxcan.h b/arch/arm/src/common/stm32/hardware/stm32_can_bxcan.h new file mode 100644 index 0000000000000..0de8ea6e5bef5 --- /dev/null +++ b/arch/arm/src/common/stm32/hardware/stm32_can_bxcan.h @@ -0,0 +1,497 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/hardware/stm32_can_bxcan.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_CAN_BXCAN_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_CAN_BXCAN_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "chip.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* 3 TX mailboxes */ + +#define CAN_TXMBOX1 0 +#define CAN_TXMBOX2 1 +#define CAN_TXMBOX3 2 + +/* 2 RX mailboxes */ + +#define CAN_RXMBOX1 0 +#define CAN_RXMBOX2 1 + +/* Number of filters depends on silicon */ + +#if defined(CONFIG_STM32_CONNECTIVITYLINE) || defined(CONFIG_STM32_STM32F20XX) || \ + defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F4XXX) +# define CAN_NFILTERS 28 +#else +# define CAN_NFILTERS 14 +#endif + +/* Register Offsets *********************************************************/ + +/* CAN control and status registers */ + +#define STM32_CAN_MCR_OFFSET 0x0000 /* CAN master control register */ +#define STM32_CAN_MSR_OFFSET 0x0004 /* CAN master status register */ +#define STM32_CAN_TSR_OFFSET 0x0008 /* CAN transmit status register */ + +#define STM32_CAN_RFR_OFFSET(m) (0x000c+((m)<<2)) +#define STM32_CAN_RF0R_OFFSET 0x000c /* CAN receive FIFO 0 register */ +#define STM32_CAN_RF1R_OFFSET 0x0010 /* CAN receive FIFO 1 register */ + +#define STM32_CAN_IER_OFFSET 0x0014 /* CAN interrupt enable register */ +#define STM32_CAN_ESR_OFFSET 0x0018 /* CAN error status register */ +#define STM32_CAN_BTR_OFFSET 0x001c /* CAN bit timing register */ + +/* CAN mailbox registers (3 TX and 2 RX) */ + +#define STM32_CAN_TIR_OFFSET(m) (0x0180+((m)<<4)) +#define STM32_CAN_TI0R_OFFSET 0x0180 /* TX mailbox identifier register 0 */ +#define STM32_CAN_TI1R_OFFSET 0x0190 /* TX mailbox identifier register 1 */ +#define STM32_CAN_TI2R_OFFSET 0x01a0 /* TX mailbox identifier register 2 */ + +#define STM32_CAN_TDTR_OFFSET(m) (0x0184+((m)<<4)) +#define STM32_CAN_TDT0R_OFFSET 0x0184 /* Mailbox data length control and time stamp register 0 */ +#define STM32_CAN_TDT1R_OFFSET 0x0194 /* Mailbox data length control and time stamp register 1 */ +#define STM32_CAN_TDT2R_OFFSET 0x01a4 /* Mailbox data length control and time stamp register 2 */ + +#define STM32_CAN_TDLR_OFFSET(m) (0x0188+((m)<<4)) +#define STM32_CAN_TDL0R_OFFSET 0x0188 /* Mailbox data low register 0 */ +#define STM32_CAN_TDL1R_OFFSET 0x0198 /* Mailbox data low register 1 */ +#define STM32_CAN_TDL2R_OFFSET 0x01a8 /* Mailbox data low register 2 */ + +#define STM32_CAN_TDHR_OFFSET(m) (0x018c+((m)<<4)) +#define STM32_CAN_TDH0R_OFFSET 0x018c /* Mailbox data high register 0 */ +#define STM32_CAN_TDH1R_OFFSET 0x019c /* Mailbox data high register 1 */ +#define STM32_CAN_TDH2R_OFFSET 0x01ac /* Mailbox data high register 2 */ + +#define STM32_CAN_RIR_OFFSET(m) (0x01b0+((m)<<4)) +#define STM32_CAN_RI0R_OFFSET 0x01b0 /* Rx FIFO mailbox identifier register 0 */ +#define STM32_CAN_RI1R_OFFSET 0x01c0 /* Rx FIFO mailbox identifier register 1 */ + +#define STM32_CAN_RDTR_OFFSET(m) (0x01b4+((m)<<4)) +#define STM32_CAN_RDT0R_OFFSET 0x01b4 /* Rx FIFO mailbox data length control and time stamp register 0 */ +#define STM32_CAN_RDT1R_OFFSET 0x01c4 /* Rx FIFO mailbox data length control and time stamp register 1 */ + +#define STM32_CAN_RDLR_OFFSET(m) (0x01b8+((m)<<4)) +#define STM32_CAN_RDL0R_OFFSET 0x01b8 /* Receive FIFO mailbox data low register 0 */ +#define STM32_CAN_RDL1R_OFFSET 0x01c8 /* Receive FIFO mailbox data low register 1 */ + +#define STM32_CAN_RDHR_OFFSET(m) (0x01bc+((m)<<4)) +#define STM32_CAN_RDH0R_OFFSET 0x01bc /* Receive FIFO mailbox data high register 0 */ +#define STM32_CAN_RDH1R_OFFSET 0x01cc /* Receive FIFO mailbox data high register 1 */ + +/* CAN filter registers */ + +#define STM32_CAN_FMR_OFFSET 0x0200 /* CAN filter master register */ +#define STM32_CAN_FM1R_OFFSET 0x0204 /* CAN filter mode register */ +#define STM32_CAN_FS1R_OFFSET 0x020c /* CAN filter scale register */ +#define STM32_CAN_FFA1R_OFFSET 0x0214 /* CAN filter FIFO assignment register */ +#define STM32_CAN_FA1R_OFFSET 0x021c /* CAN filter activation register */ + +/* There are 14 or 28 filter banks (depending) on the device. + * Each filter bank is composed of two 32-bit registers, CAN_FiR: + * F0R1 Offset 0x240 + * F0R2 Offset 0x244 + * F1R1 Offset 0x248 + * F1R2 Offset 0x24c + * ... + */ + +#define STM32_CAN_FIR_OFFSET(f,i) (0x240+((f)<<3)+(((i)-1)<<2)) + +/* Register Addresses *******************************************************/ + +#if STM32_NCAN > 0 +# define STM32_CAN1_MCR (STM32_CAN1_BASE+STM32_CAN_MCR_OFFSET) +# define STM32_CAN1_MSR (STM32_CAN1_BASE+STM32_CAN_MSR_OFFSET) +# define STM32_CAN1_TSR (STM32_CAN1_BASE+STM32_CAN_TSR_OFFSET) +# define STM32_CAN1_RF0R (STM32_CAN1_BASE+STM32_CAN_RF0R_OFFSET) +# define STM32_CAN1_RF1R (STM32_CAN1_BASE+STM32_CAN_RF1R_OFFSET) +# define STM32_CAN1_IER (STM32_CAN1_BASE+STM32_CAN_IER_OFFSET) +# define STM32_CAN1_ESR (STM32_CAN1_BASE+STM32_CAN_ESR_OFFSET) +# define STM32_CAN1_BTR (STM32_CAN1_BASE+STM32_CAN_BTR_OFFSET) + +# define STM32_CAN1_TIR(m) (STM32_CAN1_BASE+STM32_CAN_TIR_OFFSET(m)) +# define STM32_CAN1_TI0R (STM32_CAN1_BASE+STM32_CAN_TI0R_OFFSET) +# define STM32_CAN1_TI1R (STM32_CAN1_BASE+STM32_CAN_TI1R_OFFSET) +# define STM32_CAN1_TI2R (STM32_CAN1_BASE+STM32_CAN_TI2R_OFFSET) + +# define STM32_CAN1_TDTR(m) (STM32_CAN1_BASE+STM32_CAN_TDTR_OFFSET(m)) +# define STM32_CAN1_TDT0R (STM32_CAN1_BASE+STM32_CAN_TDT0R_OFFSET) +# define STM32_CAN1_TDT1R (STM32_CAN1_BASE+STM32_CAN_TDT1R_OFFSET) +# define STM32_CAN1_TDT2R (STM32_CAN1_BASE+STM32_CAN_TDT2R_OFFSET) + +# define STM32_CAN1_TDLR(m) (STM32_CAN1_BASE+STM32_CAN_TDLR_OFFSET(m)) +# define STM32_CAN1_TDL0R (STM32_CAN1_BASE+STM32_CAN_TDL0R_OFFSET) +# define STM32_CAN1_TDL1R (STM32_CAN1_BASE+STM32_CAN_TDL1R_OFFSET) +# define STM32_CAN1_TDL2R (STM32_CAN1_BASE+STM32_CAN_TDL2R_OFFSET) + +# define STM32_CAN1_TDHR(m) (STM32_CAN1_BASE+STM32_CAN_TDHR_OFFSET(m)) +# define STM32_CAN1_TDH0R (STM32_CAN1_BASE+STM32_CAN_TDH0R_OFFSET) +# define STM32_CAN1_TDH1R (STM32_CAN1_BASE+STM32_CAN_TDH1R_OFFSET) +# define STM32_CAN1_TDH2R (STM32_CAN1_BASE+STM32_CAN_TDH2R_OFFSET) + +# define STM32_CAN1_RIR(m) (STM32_CAN1_BASE+STM32_CAN_RIR_OFFSET(m)) +# define STM32_CAN1_RI0R (STM32_CAN1_BASE+STM32_CAN_RI0R_OFFSET) +# define STM32_CAN1_RI1R (STM32_CAN1_BASE+STM32_CAN_RI1R_OFFSET) + +# define STM32_CAN1_RDTR(m) (STM32_CAN1_BASE+STM32_CAN_RDTR_OFFSET(m)) +# define STM32_CAN1_RDT0R (STM32_CAN1_BASE+STM32_CAN_RDT0R_OFFSET) +# define STM32_CAN1_RDT1R (STM32_CAN1_BASE+STM32_CAN_RDT1R_OFFSET) + +# define STM32_CAN1_RDLR(m) (STM32_CAN1_BASE+STM32_CAN_RDLR_OFFSET(m)) +# define STM32_CAN1_RDL0R (STM32_CAN1_BASE+STM32_CAN_RDL0R_OFFSET) +# define STM32_CAN1_RDL1R (STM32_CAN1_BASE+STM32_CAN_RDL1R_OFFSET) + +# define STM32_CAN1_RDHR(m) (STM32_CAN1_BASE+STM32_CAN_RDHR_OFFSET(m)) +# define STM32_CAN1_RDH0R (STM32_CAN1_BASE+STM32_CAN_RDH0R_OFFSET) +# define STM32_CAN1_RDH1R (STM32_CAN1_BASE+STM32_CAN_RDH1R_OFFSET) + +# define STM32_CAN1_FMR (STM32_CAN1_BASE+STM32_CAN_FMR_OFFSET) +# define STM32_CAN1_FM1R (STM32_CAN1_BASE+STM32_CAN_FM1R_OFFSET) +# define STM32_CAN1_FS1R (STM32_CAN1_BASE+STM32_CAN_FS1R_OFFSET) +# define STM32_CAN1_FFA1R (STM32_CAN1_BASE+STM32_CAN_FFA1R_OFFSET) +# define STM32_CAN1_FA1R (STM32_CAN1_BASE+STM32_CAN_FA1R_OFFSET) +# define STM32_CAN1_FIR(b,i) (STM32_CAN1_BASE+STM32_CAN_FIR_OFFSET(b,i)) +#endif + +#if STM32_NCAN > 1 +# define STM32_CAN2_MCR (STM32_CAN2_BASE+STM32_CAN_MCR_OFFSET) +# define STM32_CAN2_MSR (STM32_CAN2_BASE+STM32_CAN_MSR_OFFSET) +# define STM32_CAN2_TSR (STM32_CAN2_BASE+STM32_CAN_TSR_OFFSET) +# define STM32_CAN2_RF0R (STM32_CAN2_BASE+STM32_CAN_RF0R_OFFSET) +# define STM32_CAN2_RF1R (STM32_CAN2_BASE+STM32_CAN_RF1R_OFFSET) +# define STM32_CAN2_IER (STM32_CAN2_BASE+STM32_CAN_IER_OFFSET) +# define STM32_CAN2_ESR (STM32_CAN2_BASE+STM32_CAN_ESR_OFFSET) +# define STM32_CAN2_BTR (STM32_CAN2_BASE+STM32_CAN_BTR_OFFSET) + +# define STM32_CAN2_TIR(m) (STM32_CAN2_BASE+STM32_CAN_TIR_OFFSET(m)) +# define STM32_CAN2_TI0R (STM32_CAN2_BASE+STM32_CAN_TI0R_OFFSET) +# define STM32_CAN2_TI1R (STM32_CAN2_BASE+STM32_CAN_TI1R_OFFSET) +# define STM32_CAN2_TI2R (STM32_CAN2_BASE+STM32_CAN_TI2R_OFFSET) + +# define STM32_CAN2_TDTR(m) (STM32_CAN2_BASE+STM32_CAN_TDTR_OFFSET(m)) +# define STM32_CAN2_TDT0R (STM32_CAN2_BASE+STM32_CAN_TDT0R_OFFSET) +# define STM32_CAN2_TDT1R (STM32_CAN2_BASE+STM32_CAN_TDT1R_OFFSET) +# define STM32_CAN2_TDT2R (STM32_CAN2_BASE+STM32_CAN_TDT2R_OFFSET) + +# define STM32_CAN2_TDLR(m) (STM32_CAN2_BASE+STM32_CAN_TDLR_OFFSET(m)) +# define STM32_CAN2_TDL0R (STM32_CAN2_BASE+STM32_CAN_TDL0R_OFFSET) +# define STM32_CAN2_TDL1R (STM32_CAN2_BASE+STM32_CAN_TDL1R_OFFSET) +# define STM32_CAN2_TDL2R (STM32_CAN2_BASE+STM32_CAN_TDL2R_OFFSET) + +# define STM32_CAN2_TDHR(m) (STM32_CAN2_BASE+STM32_CAN_TDHR_OFFSET(m)) +# define STM32_CAN2_TDH0R (STM32_CAN2_BASE+STM32_CAN_TDH0R_OFFSET) +# define STM32_CAN2_TDH1R (STM32_CAN2_BASE+STM32_CAN_TDH1R_OFFSET) +# define STM32_CAN2_TDH2R (STM32_CAN2_BASE+STM32_CAN_TDH2R_OFFSET) + +# define STM32_CAN2_RIR(m) (STM32_CAN2_BASE+STM32_CAN_RIR_OFFSET(m)) +# define STM32_CAN2_RI0R (STM32_CAN2_BASE+STM32_CAN_RI0R_OFFSET) +# define STM32_CAN2_RI1R (STM32_CAN2_BASE+STM32_CAN_RI1R_OFFSET) + +# define STM32_CAN2_RDTR(m) (STM32_CAN2_BASE+STM32_CAN_RDTR_OFFSET(m)) +# define STM32_CAN2_RDT0R (STM32_CAN2_BASE+STM32_CAN_RDT0R_OFFSET) +# define STM32_CAN2_RDT1R (STM32_CAN2_BASE+STM32_CAN_RDT1R_OFFSET) + +# define STM32_CAN2_RDLR(m) (STM32_CAN2_BASE+STM32_CAN_RDLR_OFFSET(m)) +# define STM32_CAN2_RDL0R (STM32_CAN2_BASE+STM32_CAN_RDL0R_OFFSET) +# define STM32_CAN2_RDL1R (STM32_CAN2_BASE+STM32_CAN_RDL1R_OFFSET) + +# define STM32_CAN2_RDHR(m) (STM32_CAN2_BASE+STM32_CAN_RDHR_OFFSET(m)) +# define STM32_CAN2_RDH0R (STM32_CAN2_BASE+STM32_CAN_RDH0R_OFFSET) +# define STM32_CAN2_RDH1R (STM32_CAN2_BASE+STM32_CAN_RDH1R_OFFSET) + +# define STM32_CAN2_FMR (STM32_CAN2_BASE+STM32_CAN_FMR_OFFSET) +# define STM32_CAN2_FM1R (STM32_CAN2_BASE+STM32_CAN_FM1R_OFFSET) +# define STM32_CAN2_FS1R (STM32_CAN2_BASE+STM32_CAN_FS1R_OFFSET) +# define STM32_CAN2_FFA1R (STM32_CAN2_BASE+STM32_CAN_FFA1R_OFFSET) +# define STM32_CAN2_FA1R (STM32_CAN2_BASE+STM32_CAN_FA1R_OFFSET) +# define STM32_CAN2_FIR(b,i) (STM32_CAN2_BASE+STM32_CAN_FIR_OFFSET(b,i)) +#endif + +/* Register Bitfield Definitions ********************************************/ + +/* CAN master control register */ + +#define CAN_MCR_INRQ (1 << 0) /* Bit 0: Initialization Request */ +#define CAN_MCR_SLEEP (1 << 1) /* Bit 1: Sleep Mode Request */ +#define CAN_MCR_TXFP (1 << 2) /* Bit 2: Transmit FIFO Priority */ +#define CAN_MCR_RFLM (1 << 3) /* Bit 3: Receive FIFO Locked Mode */ +#define CAN_MCR_NART (1 << 4) /* Bit 4: No Automatic Retransmission */ +#define CAN_MCR_AWUM (1 << 5) /* Bit 5: Automatic Wakeup Mode */ +#define CAN_MCR_ABOM (1 << 6) /* Bit 6: Automatic Bus-Off Management */ +#define CAN_MCR_TTCM (1 << 7) /* Bit 7: Time Triggered Communication Mode Enable */ +#define CAN_MCR_RESET (1 << 15) /* Bit 15: bxCAN software master reset */ +#define CAN_MCR_DBF (1 << 16) /* Bit 16: Debug freeze */ + +/* CAN master status register */ + +#define CAN_MSR_INAK (1 << 0) /* Bit 0: Initialization Acknowledge */ +#define CAN_MSR_SLAK (1 << 1) /* Bit 1: Sleep Acknowledge */ +#define CAN_MSR_ERRI (1 << 2) /* Bit 2: Error Interrupt */ +#define CAN_MSR_WKUI (1 << 3) /* Bit 3: Wakeup Interrupt */ +#define CAN_MSR_SLAKI (1 << 4) /* Bit 4: Sleep acknowledge interrupt */ +#define CAN_MSR_TXM (1 << 8) /* Bit 8: Transmit Mode */ +#define CAN_MSR_RXM (1 << 9) /* Bit 9: Receive Mode */ +#define CAN_MSR_SAMP (1 << 10) /* Bit 10: Last Sample Point */ +#define CAN_MSR_RX (1 << 11) /* Bit 11: CAN Rx Signal */ + +/* CAN transmit status register */ + +#define CAN_TSR_RQCP0 (1 << 0) /* Bit 0: Request Completed Mailbox 0 */ +#define CAN_TSR_TXOK0 (1 << 1) /* Bit 1 : Transmission OK of Mailbox 0 */ +#define CAN_TSR_ALST0 (1 << 2) /* Bit 2 : Arbitration Lost for Mailbox 0 */ +#define CAN_TSR_TERR0 (1 << 3) /* Bit 3 : Transmission Error of Mailbox 0 */ +#define CAN_TSR_ABRQ0 (1 << 7) /* Bit 7 : Abort Request for Mailbox 0 */ +#define CAN_TSR_RQCP1 (1 << 8) /* Bit 8 : Request Completed Mailbox 1 */ +#define CAN_TSR_TXOK1 (1 << 9) /* Bit 9 : Transmission OK of Mailbox 1 */ +#define CAN_TSR_ALST1 (1 << 10) /* Bit 10 : Arbitration Lost for Mailbox 1 */ +#define CAN_TSR_TERR1 (1 << 11) /* Bit 11 : Transmission Error of Mailbox 1 */ +#define CAN_TSR_ABRQ1 (1 << 15) /* Bit 15 : Abort Request for Mailbox 1 */ +#define CAN_TSR_RQCP2 (1 << 16) /* Bit 16 : Request Completed Mailbox 2 */ +#define CAN_TSR_TXOK2 (1 << 17) /* Bit 17 : Transmission OK of Mailbox 2 */ +#define CAN_TSR_ALST2 (1 << 18) /* Bit 18: Arbitration Lost for Mailbox 2 */ +#define CAN_TSR_TERR2 (1 << 19) /* Bit 19: Transmission Error of Mailbox 2 */ +#define CAN_TSR_ABRQ2 (1 << 23) /* Bit 23: Abort Request for Mailbox 2 */ +#define CAN_TSR_CODE_SHIFT (24) /* Bits 25-24: Mailbox Code */ +#define CAN_TSR_CODE_MASK (3 << CAN_TSR_CODE_SHIFT) +#define CAN_TSR_TME0 (1 << 26) /* Bit 26: Transmit Mailbox 0 Empty */ +#define CAN_TSR_TME1 (1 << 27) /* Bit 27: Transmit Mailbox 1 Empty */ +#define CAN_TSR_TME2 (1 << 28) /* Bit 28: Transmit Mailbox 2 Empty */ +#define CAN_TSR_LOW0 (1 << 29) /* Bit 29: Lowest Priority Flag for Mailbox 0 */ +#define CAN_TSR_LOW1 (1 << 30) /* Bit 30: Lowest Priority Flag for Mailbox 1 */ +#define CAN_TSR_LOW2 (1 << 31) /* Bit 31: Lowest Priority Flag for Mailbox 2 */ + +/* CAN receive FIFO 0/1 registers */ + +#define CAN_RFR_FMP_SHIFT (0) /* Bits 1-0: FIFO Message Pending */ +#define CAN_RFR_FMP_MASK (3 << CAN_RFR_FMP_SHIFT) +#define CAN_RFR_FULL (1 << 3) /* Bit 3: FIFO 0 Full */ +#define CAN_RFR_FOVR (1 << 4) /* Bit 4: FIFO 0 Overrun */ +#define CAN_RFR_RFOM (1 << 5) /* Bit 5: Release FIFO 0 Output Mailbox */ + +/* CAN interrupt enable register */ + +#define CAN_IER_TMEIE (1 << 0) /* Bit 0: Transmit Mailbox Empty Interrupt Enable */ +#define CAN_IER_FMPIE0 (1 << 1) /* Bit 1: FIFO Message Pending Interrupt Enable */ +#define CAN_IER_FFIE0 (1 << 2) /* Bit 2: FIFO Full Interrupt Enable */ +#define CAN_IER_FOVIE0 (1 << 3) /* Bit 3: FIFO Overrun Interrupt Enable */ +#define CAN_IER_FMPIE1 (1 << 4) /* Bit 4: FIFO Message Pending Interrupt Enable */ +#define CAN_IER_FFIE1 (1 << 5) /* Bit 5: FIFO Full Interrupt Enable */ +#define CAN_IER_FOVIE1 (1 << 6) /* Bit 6: FIFO Overrun Interrupt Enable */ +#define CAN_IER_EWGIE (1 << 8) /* Bit 8: Error Warning Interrupt Enable */ +#define CAN_IER_EPVIE (1 << 9) /* Bit 9: Error Passive Interrupt Enable */ +#define CAN_IER_BOFIE (1 << 10) /* Bit 10: Bus-Off Interrupt Enable */ +#define CAN_IER_LECIE (1 << 11) /* Bit 11: Last Error Code Interrupt Enable */ +#define CAN_IER_ERRIE (1 << 15) /* Bit 15: Error Interrupt Enable */ +#define CAN_IER_WKUIE (1 << 16) /* Bit 16: Wakeup Interrupt Enable */ +#define CAN_IER_SLKIE (1 << 17) /* Bit 17: Sleep Interrupt Enable */ + +/* CAN error status register */ + +#define CAN_ESR_EWGF (1 << 0) /* Bit 0: Error Warning Flag */ +#define CAN_ESR_EPVF (1 << 1) /* Bit 1: Error Passive Flag */ +#define CAN_ESR_BOFF (1 << 2) /* Bit 2: Bus-Off Flag */ +#define CAN_ESR_LEC_SHIFT (4) /* Bits 6-4: Last Error Code */ +#define CAN_ESR_LEC_MASK (7 << CAN_ESR_LEC_SHIFT) +# define CAN_ESR_NOERROR (0 << CAN_ESR_LEC_SHIFT) /* 000: No Error */ +# define CAN_ESR_STUFFERROR (1 << CAN_ESR_LEC_SHIFT) /* 001: Stuff Error */ +# define CAN_ESR_FORMERROR (2 << CAN_ESR_LEC_SHIFT) /* 010: Form Error */ +# define CAN_ESR_ACKERROR (3 << CAN_ESR_LEC_SHIFT) /* 011: Acknowledgment Error */ +# define CAN_ESR_BRECERROR (4 << CAN_ESR_LEC_SHIFT) /* 100: Bit recessive Error */ +# define CAN_ESR_BDOMERROR (5 << CAN_ESR_LEC_SHIFT) /* 101: Bit dominant Error */ +# define CAN_ESR_CRCERRPR (6 << CAN_ESR_LEC_SHIFT) /* 110: CRC Error */ +# define CAN_ESR_SWERROR (7 << CAN_ESR_LEC_SHIFT) /* 111: Set by software */ + +#define CAN_ESR_TEC_SHIFT (16) /* Bits 23-16: LS byte of the 9-bit Transmit Error Counter */ +#define CAN_ESR_TEC_MASK (0xff << CAN_ESR_TEC_SHIF) +#define CAN_ESR_REC_SHIFT (24) /* Bits 31-24: Receive Error Counter */ +#define CAN_ESR_REC_MASK (0xff << CAN_ESR_REC_SHIFT) + +/* CAN bit timing register */ + +#define CAN_BTR_BRP_SHIFT (0) /* Bits 9-0: Baud Rate Prescaler */ +#define CAN_BTR_BRP_MASK (0x03ff << CAN_BTR_BRP_SHIFT) +#define CAN_BTR_TS1_SHIFT (16) /* Bits 19-16: Time Segment 1 */ +#define CAN_BTR_TS1_MASK (0x0f << CAN_BTR_TS1_SHIFT) +#define CAN_BTR_TS2_SHIFT (20) /* Bits 22-20: Time Segment 2 */ +#define CAN_BTR_TS2_MASK (7 << CAN_BTR_TS2_SHIFT) +#define CAN_BTR_SJW_SHIFT (24) /* Bits 25-24: Resynchronization Jump Width */ +#define CAN_BTR_SJW_MASK (3 << CAN_BTR_SJW_SHIFT) +#define CAN_BTR_LBKM (1 << 30) /* Bit 30: Loop Back Mode (Debug) */ +#define CAN_BTR_SILM (1ul << 31) /* Bit 31: Silent Mode (Debug) */ + +#define CAN_BTR_BRP_MAX (1024) /* Maximum BTR value (without decrement) */ +#define CAN_BTR_TSEG1_MAX (16) /* Maximum TSEG1 value (without decrement) */ +#define CAN_BTR_TSEG2_MAX (8) /* Maximum TSEG2 value (without decrement) */ + +/* TX mailbox identifier register */ + +#define CAN_TIR_TXRQ (1 << 0) /* Bit 0: Transmit Mailbox Request */ +#define CAN_TIR_RTR (1 << 1) /* Bit 1: Remote Transmission Request */ +#define CAN_TIR_IDE (1 << 2) /* Bit 2: Identifier Extension */ +#define CAN_TIR_EXID_SHIFT (3) /* Bit 3-31: Extended Identifier */ +#define CAN_TIR_EXID_MASK (0x1fffffff << CAN_TIR_EXID_SHIFT) +#define CAN_TIR_STID_SHIFT (21) /* Bits 21-31: Standard Identifier */ +#define CAN_TIR_STID_MASK (0x07ff << CAN_TIR_STID_SHIFT) + +/* Mailbox data length control and time stamp register */ + +#define CAN_TDTR_DLC_SHIFT (0) /* Bits 3:0: Data Length Code */ +#define CAN_TDTR_DLC_MASK (0x0f << CAN_TDTR_DLC_SHIFT) +#define CAN_TDTR_TGT (1 << 8) /* Bit 8: Transmit Global Time */ +#define CAN_TDTR_TIME_SHIFT (16) /* Bits 31:16: Message Time Stamp */ +#define CAN_TDTR_TIME_MASK (0xffff << CAN_TDTR_TIME_SHIFT) + +/* Mailbox data low register */ + +#define CAN_TDLR_DATA0_SHIFT (0) /* Bits 7-0: Data Byte 0 */ +#define CAN_TDLR_DATA0_MASK (0xff << CAN_TDLR_DATA0_SHIFT) +#define CAN_TDLR_DATA1_SHIFT (8) /* Bits 15-8: Data Byte 1 */ +#define CAN_TDLR_DATA1_MASK (0xff << CAN_TDLR_DATA1_SHIFT) +#define CAN_TDLR_DATA2_SHIFT (16) /* Bits 23-16: Data Byte 2 */ +#define CAN_TDLR_DATA2_MASK (0xff << CAN_TDLR_DATA2_SHIFT) +#define CAN_TDLR_DATA3_SHIFT (24) /* Bits 31-24: Data Byte 3 */ +#define CAN_TDLR_DATA3_MASK (0xff << CAN_TDLR_DATA3_SHIFT) + +/* Mailbox data high register */ + +#define CAN_TDHR_DATA4_SHIFT (0) /* Bits 7-0: Data Byte 4 */ +#define CAN_TDHR_DATA4_MASK (0xff << CAN_TDHR_DATA4_SHIFT) +#define CAN_TDHR_DATA5_SHIFT (8) /* Bits 15-8: Data Byte 5 */ +#define CAN_TDHR_DATA5_MASK (0xff << CAN_TDHR_DATA5_SHIFT) +#define CAN_TDHR_DATA6_SHIFT (16) /* Bits 23-16: Data Byte 6 */ +#define CAN_TDHR_DATA6_MASK (0xff << CAN_TDHR_DATA6_SHIFT) +#define CAN_TDHR_DATA7_SHIFT (24) /* Bits 31-24: Data Byte 7 */ +#define CAN_TDHR_DATA7_MASK (0xff << CAN_TDHR_DATA7_SHIFT) + +/* Rx FIFO mailbox identifier register */ + +#define CAN_RIR_RTR (1 << 1) /* Bit 1: Remote Transmission Request */ +#define CAN_RIR_IDE (1 << 2) /* Bit 2: Identifier Extension */ +#define CAN_RIR_EXID_SHIFT (3) /* Bit 3-31: Extended Identifier */ +#define CAN_RIR_EXID_MASK (0x1fffffff << CAN_RIR_EXID_SHIFT) +#define CAN_RIR_STID_SHIFT (21) /* Bits 21-31: Standard Identifier */ +#define CAN_RIR_STID_MASK (0x07ff << CAN_RIR_STID_SHIFT) + +/* Receive FIFO mailbox data length control and time stamp register */ + +#define CAN_RDTR_DLC_SHIFT (0) /* Bits 3:0: Data Length Code */ +#define CAN_RDTR_DLC_MASK (0x0f << CAN_RDTR_DLC_SHIFT) +#define CAN_RDTR_FM_SHIFT (8) /* Bits 15-8: Filter Match Index */ +#define CAN_RDTR_FM_MASK (0xff << CAN_RDTR_FM_SHIFT) +#define CAN_RDTR_TIME_SHIFT (16) /* Bits 31:16: Message Time Stamp */ +#define CAN_RDTR_TIME_MASK (0xffff << CAN_RDTR_TIME_SHIFT) + +/* Receive FIFO mailbox data low register */ + +#define CAN_RDLR_DATA0_SHIFT (0) /* Bits 7-0: Data Byte 0 */ +#define CAN_RDLR_DATA0_MASK (0xff << CAN_RDLR_DATA0_SHIFT) +#define CAN_RDLR_DATA1_SHIFT (8) /* Bits 15-8: Data Byte 1 */ +#define CAN_RDLR_DATA1_MASK (0xff << CAN_RDLR_DATA1_SHIFT) +#define CAN_RDLR_DATA2_SHIFT (16) /* Bits 23-16: Data Byte 2 */ +#define CAN_RDLR_DATA2_MASK (0xff << CAN_RDLR_DATA2_SHIFT) +#define CAN_RDLR_DATA3_SHIFT (24) /* Bits 31-24: Data Byte 3 */ +#define CAN_RDLR_DATA3_MASK (0xff << CAN_RDLR_DATA3_SHIFT) + +/* Receive FIFO mailbox data high register */ + +#define CAN_RDHR_DATA4_SHIFT (0) /* Bits 7-0: Data Byte 4 */ +#define CAN_RDHR_DATA4_MASK (0xff << CAN_RDHR_DATA4_SHIFT) +#define CAN_RDHR_DATA5_SHIFT (8) /* Bits 15-8: Data Byte 5 */ +#define CAN_RDHR_DATA5_MASK (0xff << CAN_RDHR_DATA5_SHIFT) +#define CAN_RDHR_DATA6_SHIFT (16) /* Bits 23-16: Data Byte 6 */ +#define CAN_RDHR_DATA6_MASK (0xff << CAN_RDHR_DATA6_SHIFT) +#define CAN_RDHR_DATA7_SHIFT (24) /* Bits 31-24: Data Byte 7 */ +#define CAN_RDHR_DATA7_MASK (0xff << CAN_RDHR_DATA7_SHIFT) + +/* CAN filter master register */ + +#define CAN_FMR_FINIT (1 << 0) /* Bit 0: Filter Init Mode */ +#if defined(CONFIG_STM32_HAVE_IP_CAN_BXCAN_M3M4_V1) +# define CAN_FMR_CAN2SB_SHIFT (8) /* Bits 13-8: CAN2 start bank */ +# define CAN_FMR_CAN2SB_MASK (0x3f << CAN_FMR_CAN2SB_SHIFT) +#endif + +/* CAN filter mode register */ + +#if defined(CONFIG_STM32_HAVE_IP_CAN_BXCAN_M3M4_V1) +# define CAN_FM1R_FBM_SHIFT (0) /* Bits 13:0: Filter Mode */ +# define CAN_FM1R_FBM_MASK (0x3fff << CAN_FM1R_FBM_SHIFT) +#else +# define CAN_FM1R_FBM_SHIFT (0) /* Bits 27:0: Filter Mode */ +# define CAN_FM1R_FBM_MASK (0x0fffffff << CAN_FM1R_FBM_SHIFT) +#endif + +/* CAN filter scale register */ + +#if defined(CONFIG_STM32_HAVE_IP_CAN_BXCAN_M3M4_V1) +# define CAN_FS1R_FSC_SHIFT (0) /* Bits 13:0: Filter Scale Configuration */ +# define CAN_FS1R_FSC_MASK (0x3fff << CAN_FS1R_FSC_SHIFT) +#else +# define CAN_FS1R_FSC_SHIFT (0) /* Bits 27:0: Filter Scale Configuration */ +# define CAN_FS1R_FSC_MASK (0x0fffffff << CAN_FS1R_FSC_SHIFT) +#endif + +/* CAN filter FIFO assignment register */ + +#if defined(CONFIG_STM32_HAVE_IP_CAN_BXCAN_M3M4_V1) +# define CAN_FFA1R_FFA_SHIFT (0) /* Bits 13:0: Filter FIFO Assignment */ +# define CAN_FFA1R_FFA_MASK (0x3fff << CAN_FFA1R_FFA_SHIFT) +#else +# define CAN_FFA1R_FFA_SHIFT (0) /* Bits 27:0: Filter FIFO Assignment */ +# define CAN_FFA1R_FFA_MASK (0x0fffffff << CAN_FFA1R_FFA_SHIFT) +#endif + +/* CAN filter activation register */ + +#if defined(CONFIG_STM32_HAVE_IP_CAN_BXCAN_M3M4_V1) +# define CAN_FA1R_FACT_SHIFT (0) /* Bits 13:0: Filter Active */ +# define CAN_FA1R_FACT_MASK (0x3fff << CAN_FA1R_FACT_SHIFT) +#else +# define CAN_FA1R_FACT_SHIFT (0) /* Bits 27:0: Filter Active */ +# define CAN_FA1R_FACT_MASK (0x0fffffff << CAN_FA1R_FACT_SHIFT) +#endif + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_CAN_BXCAN_H */ diff --git a/arch/arm/src/common/stm32/hardware/stm32_can_bxcan_m0.h b/arch/arm/src/common/stm32/hardware/stm32_can_bxcan_m0.h new file mode 100644 index 0000000000000..378e5a03df55d --- /dev/null +++ b/arch/arm/src/common/stm32/hardware/stm32_can_bxcan_m0.h @@ -0,0 +1,456 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/hardware/stm32_can_bxcan_m0.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_CAN_BXCAN_M0_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_CAN_BXCAN_M0_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "chip.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* 3 TX mailboxes */ + +#define CAN_TXMBOX1 0 +#define CAN_TXMBOX2 1 +#define CAN_TXMBOX3 2 + +/* 2 RX mailboxes */ + +#define CAN_RXMBOX1 0 +#define CAN_RXMBOX2 1 + +/* Number of filters depends on silicon */ + +#define CAN_NFILTERS 14 + +/* Register Offsets *********************************************************/ + +/* CAN control and status registers */ + +#define STM32_CAN_MCR_OFFSET 0x0000 /* CAN master control register */ +#define STM32_CAN_MSR_OFFSET 0x0004 /* CAN master status register */ +#define STM32_CAN_TSR_OFFSET 0x0008 /* CAN transmit status register */ + +#define STM32_CAN_RFR_OFFSET(m) (0x000c + ((m) << 2)) +#define STM32_CAN_RF0R_OFFSET 0x000c /* CAN receive FIFO 0 register */ +#define STM32_CAN_RF1R_OFFSET 0x0010 /* CAN receive FIFO 1 register */ + +#define STM32_CAN_IER_OFFSET 0x0014 /* CAN interrupt enable register */ +#define STM32_CAN_ESR_OFFSET 0x0018 /* CAN error status register */ +#define STM32_CAN_BTR_OFFSET 0x001c /* CAN bit timing register */ + +/* CAN mailbox registers (3 TX and 2 RX) */ + +#define STM32_CAN_TIR_OFFSET(m) (0x0180 + ((m) << 4)) +#define STM32_CAN_TI0R_OFFSET 0x0180 /* TX mailbox identifier register 0 */ +#define STM32_CAN_TI1R_OFFSET 0x0190 /* TX mailbox identifier register 1 */ +#define STM32_CAN_TI2R_OFFSET 0x01a0 /* TX mailbox identifier register 2 */ + +#define STM32_CAN_TDTR_OFFSET(m) (0x0184 + ((m) << 4)) +#define STM32_CAN_TDT0R_OFFSET 0x0184 /* Mailbox data length control and time stamp register 0 */ +#define STM32_CAN_TDT1R_OFFSET 0x0194 /* Mailbox data length control and time stamp register 1 */ +#define STM32_CAN_TDT2R_OFFSET 0x01a4 /* Mailbox data length control and time stamp register 2 */ + +#define STM32_CAN_TDLR_OFFSET(m) (0x0188 + ((m) << 4)) +#define STM32_CAN_TDL0R_OFFSET 0x0188 /* Mailbox data low register 0 */ +#define STM32_CAN_TDL1R_OFFSET 0x0198 /* Mailbox data low register 1 */ +#define STM32_CAN_TDL2R_OFFSET 0x01a8 /* Mailbox data low register 2 */ + +#define STM32_CAN_TDHR_OFFSET(m) (0x018c + ((m) << 4)) +#define STM32_CAN_TDH0R_OFFSET 0x018c /* Mailbox data high register 0 */ +#define STM32_CAN_TDH1R_OFFSET 0x019c /* Mailbox data high register 1 */ +#define STM32_CAN_TDH2R_OFFSET 0x01ac /* Mailbox data high register 2 */ + +#define STM32_CAN_RIR_OFFSET(m) (0x01b0 + ((m) << 4)) +#define STM32_CAN_RI0R_OFFSET 0x01b0 /* Rx FIFO mailbox identifier register 0 */ +#define STM32_CAN_RI1R_OFFSET 0x01c0 /* Rx FIFO mailbox identifier register 1 */ + +#define STM32_CAN_RDTR_OFFSET(m) (0x01b4 + ((m) << 4)) +#define STM32_CAN_RDT0R_OFFSET 0x01b4 /* Rx FIFO mailbox data length control and time stamp register 0 */ +#define STM32_CAN_RDT1R_OFFSET 0x01c4 /* Rx FIFO mailbox data length control and time stamp register 1 */ + +#define STM32_CAN_RDLR_OFFSET(m) (0x01b8 + ((m) << 4)) +#define STM32_CAN_RDL0R_OFFSET 0x01b8 /* Receive FIFO mailbox data low register 0 */ +#define STM32_CAN_RDL1R_OFFSET 0x01c8 /* Receive FIFO mailbox data low register 1 */ + +#define STM32_CAN_RDHR_OFFSET(m) (0x01bc + ((m) << 4)) +#define STM32_CAN_RDH0R_OFFSET 0x01bc /* Receive FIFO mailbox data high register 0 */ +#define STM32_CAN_RDH1R_OFFSET 0x01cc /* Receive FIFO mailbox data high register 1 */ + +/* CAN filter registers */ + +#define STM32_CAN_FMR_OFFSET 0x0200 /* CAN filter master register */ +#define STM32_CAN_FM1R_OFFSET 0x0204 /* CAN filter mode register */ +#define STM32_CAN_FS1R_OFFSET 0x020c /* CAN filter scale register */ +#define STM32_CAN_FFA1R_OFFSET 0x0214 /* CAN filter FIFO assignment register */ +#define STM32_CAN_FA1R_OFFSET 0x021c /* CAN filter activation register */ + +/* There are 14 or 28 filter banks (depending) on the device. + * Each filter bank is composed of two 32-bit registers, CAN_FiR: + * F0R1 Offset 0x240 + * F0R2 Offset 0x244 + * F1R1 Offset 0x248 + * F1R2 Offset 0x24c + * ... + */ + +#define STM32_CAN_FIR_OFFSET(f,i) (0x240 + ((f) << 3)+(((i) - 1) << 2)) + +/* Register Addresses *******************************************************/ + +#if STM32_NCAN > 0 +# define STM32_CAN1_MCR (STM32_CAN1_BASE + STM32_CAN_MCR_OFFSET) +# define STM32_CAN1_MSR (STM32_CAN1_BASE + STM32_CAN_MSR_OFFSET) +# define STM32_CAN1_TSR (STM32_CAN1_BASE + STM32_CAN_TSR_OFFSET) +# define STM32_CAN1_RF0R (STM32_CAN1_BASE + STM32_CAN_RF0R_OFFSET) +# define STM32_CAN1_RF1R (STM32_CAN1_BASE + STM32_CAN_RF1R_OFFSET) +# define STM32_CAN1_IER (STM32_CAN1_BASE + STM32_CAN_IER_OFFSET) +# define STM32_CAN1_ESR (STM32_CAN1_BASE + STM32_CAN_ESR_OFFSET) +# define STM32_CAN1_BTR (STM32_CAN1_BASE + STM32_CAN_BTR_OFFSET) + +# define STM32_CAN1_TIR(m) (STM32_CAN1_BASE + STM32_CAN_TIR_OFFSET(m)) +# define STM32_CAN1_TI0R (STM32_CAN1_BASE + STM32_CAN_TI0R_OFFSET) +# define STM32_CAN1_TI1R (STM32_CAN1_BASE + STM32_CAN_TI1R_OFFSET) +# define STM32_CAN1_TI2R (STM32_CAN1_BASE + STM32_CAN_TI2R_OFFSET) + +# define STM32_CAN1_TDTR(m) (STM32_CAN1_BASE + STM32_CAN_TDTR_OFFSET(m)) +# define STM32_CAN1_TDT0R (STM32_CAN1_BASE + STM32_CAN_TDT0R_OFFSET) +# define STM32_CAN1_TDT1R (STM32_CAN1_BASE + STM32_CAN_TDT1R_OFFSET) +# define STM32_CAN1_TDT2R (STM32_CAN1_BASE + STM32_CAN_TDT2R_OFFSET) + +# define STM32_CAN1_TDLR(m) (STM32_CAN1_BASE + STM32_CAN_TDLR_OFFSET(m)) +# define STM32_CAN1_TDL0R (STM32_CAN1_BASE + STM32_CAN_TDL0R_OFFSET) +# define STM32_CAN1_TDL1R (STM32_CAN1_BASE + STM32_CAN_TDL1R_OFFSET) +# define STM32_CAN1_TDL2R (STM32_CAN1_BASE + STM32_CAN_TDL2R_OFFSET) + +# define STM32_CAN1_TDHR(m) (STM32_CAN1_BASE + STM32_CAN_TDHR_OFFSET(m)) +# define STM32_CAN1_TDH0R (STM32_CAN1_BASE + STM32_CAN_TDH0R_OFFSET) +# define STM32_CAN1_TDH1R (STM32_CAN1_BASE + STM32_CAN_TDH1R_OFFSET) +# define STM32_CAN1_TDH2R (STM32_CAN1_BASE + STM32_CAN_TDH2R_OFFSET) + +# define STM32_CAN1_RIR(m) (STM32_CAN1_BASE + STM32_CAN_RIR_OFFSET(m)) +# define STM32_CAN1_RI0R (STM32_CAN1_BASE + STM32_CAN_RI0R_OFFSET) +# define STM32_CAN1_RI1R (STM32_CAN1_BASE + STM32_CAN_RI1R_OFFSET) + +# define STM32_CAN1_RDTR(m) (STM32_CAN1_BASE + STM32_CAN_RDTR_OFFSET(m)) +# define STM32_CAN1_RDT0R (STM32_CAN1_BASE + STM32_CAN_RDT0R_OFFSET) +# define STM32_CAN1_RDT1R (STM32_CAN1_BASE + STM32_CAN_RDT1R_OFFSET) + +# define STM32_CAN1_RDLR(m) (STM32_CAN1_BASE + STM32_CAN_RDLR_OFFSET(m)) +# define STM32_CAN1_RDL0R (STM32_CAN1_BASE + STM32_CAN_RDL0R_OFFSET) +# define STM32_CAN1_RDL1R (STM32_CAN1_BASE + STM32_CAN_RDL1R_OFFSET) + +# define STM32_CAN1_RDHR(m) (STM32_CAN1_BASE + STM32_CAN_RDHR_OFFSET(m)) +# define STM32_CAN1_RDH0R (STM32_CAN1_BASE + STM32_CAN_RDH0R_OFFSET) +# define STM32_CAN1_RDH1R (STM32_CAN1_BASE + STM32_CAN_RDH1R_OFFSET) + +# define STM32_CAN1_FMR (STM32_CAN1_BASE + STM32_CAN_FMR_OFFSET) +# define STM32_CAN1_FM1R (STM32_CAN1_BASE + STM32_CAN_FM1R_OFFSET) +# define STM32_CAN1_FS1R (STM32_CAN1_BASE + STM32_CAN_FS1R_OFFSET) +# define STM32_CAN1_FFA1R (STM32_CAN1_BASE + STM32_CAN_FFA1R_OFFSET) +# define STM32_CAN1_FA1R (STM32_CAN1_BASE + STM32_CAN_FA1R_OFFSET) +# define STM32_CAN1_FIR(b,i) (STM32_CAN1_BASE + STM32_CAN_FIR_OFFSET(b,i)) +#endif + +#if STM32_NCAN > 1 +# define STM32_CAN2_MCR (STM32_CAN2_BASE + STM32_CAN_MCR_OFFSET) +# define STM32_CAN2_MSR (STM32_CAN2_BASE + STM32_CAN_MSR_OFFSET) +# define STM32_CAN2_TSR (STM32_CAN2_BASE + STM32_CAN_TSR_OFFSET) +# define STM32_CAN2_RF0R (STM32_CAN2_BASE + STM32_CAN_RF0R_OFFSET) +# define STM32_CAN2_RF1R (STM32_CAN2_BASE + STM32_CAN_RF1R_OFFSET) +# define STM32_CAN2_IER (STM32_CAN2_BASE + STM32_CAN_IER_OFFSET) +# define STM32_CAN2_ESR (STM32_CAN2_BASE + STM32_CAN_ESR_OFFSET) +# define STM32_CAN2_BTR (STM32_CAN2_BASE + STM32_CAN_BTR_OFFSET) + +# define STM32_CAN2_TIR(m) (STM32_CAN2_BASE + STM32_CAN_TIR_OFFSET(m)) +# define STM32_CAN2_TI0R (STM32_CAN2_BASE + STM32_CAN_TI0R_OFFSET) +# define STM32_CAN2_TI1R (STM32_CAN2_BASE + STM32_CAN_TI1R_OFFSET) +# define STM32_CAN2_TI2R (STM32_CAN2_BASE + STM32_CAN_TI2R_OFFSET) + +# define STM32_CAN2_TDTR(m) (STM32_CAN2_BASE + STM32_CAN_TDTR_OFFSET(m)) +# define STM32_CAN2_TDT0R (STM32_CAN2_BASE + STM32_CAN_TDT0R_OFFSET) +# define STM32_CAN2_TDT1R (STM32_CAN2_BASE + STM32_CAN_TDT1R_OFFSET) +# define STM32_CAN2_TDT2R (STM32_CAN2_BASE + STM32_CAN_TDT2R_OFFSET) + +# define STM32_CAN2_TDLR(m) (STM32_CAN2_BASE + STM32_CAN_TDLR_OFFSET(m)) +# define STM32_CAN2_TDL0R (STM32_CAN2_BASE + STM32_CAN_TDL0R_OFFSET) +# define STM32_CAN2_TDL1R (STM32_CAN2_BASE + STM32_CAN_TDL1R_OFFSET) +# define STM32_CAN2_TDL2R (STM32_CAN2_BASE + STM32_CAN_TDL2R_OFFSET) + +# define STM32_CAN2_TDHR(m) (STM32_CAN2_BASE + STM32_CAN_TDHR_OFFSET(m)) +# define STM32_CAN2_TDH0R (STM32_CAN2_BASE + STM32_CAN_TDH0R_OFFSET) +# define STM32_CAN2_TDH1R (STM32_CAN2_BASE + STM32_CAN_TDH1R_OFFSET) +# define STM32_CAN2_TDH2R (STM32_CAN2_BASE + STM32_CAN_TDH2R_OFFSET) + +# define STM32_CAN2_RIR(m) (STM32_CAN2_BASE + STM32_CAN_RIR_OFFSET(m)) +# define STM32_CAN2_RI0R (STM32_CAN2_BASE + STM32_CAN_RI0R_OFFSET) +# define STM32_CAN2_RI1R (STM32_CAN2_BASE + STM32_CAN_RI1R_OFFSET) + +# define STM32_CAN2_RDTR(m) (STM32_CAN2_BASE + STM32_CAN_RDTR_OFFSET(m)) +# define STM32_CAN2_RDT0R (STM32_CAN2_BASE + STM32_CAN_RDT0R_OFFSET) +# define STM32_CAN2_RDT1R (STM32_CAN2_BASE + STM32_CAN_RDT1R_OFFSET) + +# define STM32_CAN2_RDLR(m) (STM32_CAN2_BASE + STM32_CAN_RDLR_OFFSET(m)) +# define STM32_CAN2_RDL0R (STM32_CAN2_BASE + STM32_CAN_RDL0R_OFFSET) +# define STM32_CAN2_RDL1R (STM32_CAN2_BASE + STM32_CAN_RDL1R_OFFSET) + +# define STM32_CAN2_RDHR(m) (STM32_CAN2_BASE + STM32_CAN_RDHR_OFFSET(m)) +# define STM32_CAN2_RDH0R (STM32_CAN2_BASE + STM32_CAN_RDH0R_OFFSET) +# define STM32_CAN2_RDH1R (STM32_CAN2_BASE + STM32_CAN_RDH1R_OFFSET) + +# define STM32_CAN2_FMR (STM32_CAN2_BASE + STM32_CAN_FMR_OFFSET) +# define STM32_CAN2_FM1R (STM32_CAN2_BASE + STM32_CAN_FM1R_OFFSET) +# define STM32_CAN2_FS1R (STM32_CAN2_BASE + STM32_CAN_FS1R_OFFSET) +# define STM32_CAN2_FFA1R (STM32_CAN2_BASE + STM32_CAN_FFA1R_OFFSET) +# define STM32_CAN2_FA1R (STM32_CAN2_BASE + STM32_CAN_FA1R_OFFSET) +# define STM32_CAN2_FIR(b,i) (STM32_CAN2_BASE + STM32_CAN_FIR_OFFSET(b,i)) +#endif + +/* Register Bitfield Definitions ********************************************/ + +/* CAN master control register */ + +#define CAN_MCR_INRQ (1 << 0) /* Bit 0: Initialization Request */ +#define CAN_MCR_SLEEP (1 << 1) /* Bit 1: Sleep Mode Request */ +#define CAN_MCR_TXFP (1 << 2) /* Bit 2: Transmit FIFO Priority */ +#define CAN_MCR_RFLM (1 << 3) /* Bit 3: Receive FIFO Locked Mode */ +#define CAN_MCR_NART (1 << 4) /* Bit 4: No Automatic Retransmission */ +#define CAN_MCR_AWUM (1 << 5) /* Bit 5: Automatic Wakeup Mode */ +#define CAN_MCR_ABOM (1 << 6) /* Bit 6: Automatic Bus-Off Management */ +#define CAN_MCR_TTCM (1 << 7) /* Bit 7: Time Triggered Communication Mode Enable */ +#define CAN_MCR_RESET (1 << 15) /* Bit 15: bxCAN software master reset */ +#define CAN_MCR_DBF (1 << 16) /* Bit 16: Debug freeze */ + +/* CAN master status register */ + +#define CAN_MSR_INAK (1 << 0) /* Bit 0: Initialization Acknowledge */ +#define CAN_MSR_SLAK (1 << 1) /* Bit 1: Sleep Acknowledge */ +#define CAN_MSR_ERRI (1 << 2) /* Bit 2: Error Interrupt */ +#define CAN_MSR_WKUI (1 << 3) /* Bit 3: Wakeup Interrupt */ +#define CAN_MSR_SLAKI (1 << 4) /* Bit 4: Sleep acknowledge interrupt */ +#define CAN_MSR_TXM (1 << 8) /* Bit 8: Transmit Mode */ +#define CAN_MSR_RXM (1 << 9) /* Bit 9: Receive Mode */ +#define CAN_MSR_SAMP (1 << 10) /* Bit 10: Last Sample Point */ +#define CAN_MSR_RX (1 << 11) /* Bit 11: CAN Rx Signal */ + +/* CAN transmit status register */ + +#define CAN_TSR_RQCP0 (1 << 0) /* Bit 0: Request Completed Mailbox 0 */ +#define CAN_TSR_TXOK0 (1 << 1) /* Bit 1 : Transmission OK of Mailbox 0 */ +#define CAN_TSR_ALST0 (1 << 2) /* Bit 2 : Arbitration Lost for Mailbox 0 */ +#define CAN_TSR_TERR0 (1 << 3) /* Bit 3 : Transmission Error of Mailbox 0 */ +#define CAN_TSR_ABRQ0 (1 << 7) /* Bit 7 : Abort Request for Mailbox 0 */ +#define CAN_TSR_RQCP1 (1 << 8) /* Bit 8 : Request Completed Mailbox 1 */ +#define CAN_TSR_TXOK1 (1 << 9) /* Bit 9 : Transmission OK of Mailbox 1 */ +#define CAN_TSR_ALST1 (1 << 10) /* Bit 10 : Arbitration Lost for Mailbox 1 */ +#define CAN_TSR_TERR1 (1 << 11) /* Bit 11 : Transmission Error of Mailbox 1 */ +#define CAN_TSR_ABRQ1 (1 << 15) /* Bit 15 : Abort Request for Mailbox 1 */ +#define CAN_TSR_RQCP2 (1 << 16) /* Bit 16 : Request Completed Mailbox 2 */ +#define CAN_TSR_TXOK2 (1 << 17) /* Bit 17 : Transmission OK of Mailbox 2 */ +#define CAN_TSR_ALST2 (1 << 18) /* Bit 18: Arbitration Lost for Mailbox 2 */ +#define CAN_TSR_TERR2 (1 << 19) /* Bit 19: Transmission Error of Mailbox 2 */ +#define CAN_TSR_ABRQ2 (1 << 23) /* Bit 23: Abort Request for Mailbox 2 */ +#define CAN_TSR_CODE_SHIFT (24) /* Bits 25-24: Mailbox Code */ +#define CAN_TSR_CODE_MASK (3 << CAN_TSR_CODE_SHIFT) +#define CAN_TSR_TME0 (1 << 26) /* Bit 26: Transmit Mailbox 0 Empty */ +#define CAN_TSR_TME1 (1 << 27) /* Bit 27: Transmit Mailbox 1 Empty */ +#define CAN_TSR_TME2 (1 << 28) /* Bit 28: Transmit Mailbox 2 Empty */ +#define CAN_TSR_LOW0 (1 << 29) /* Bit 29: Lowest Priority Flag for Mailbox 0 */ +#define CAN_TSR_LOW1 (1 << 30) /* Bit 30: Lowest Priority Flag for Mailbox 1 */ +#define CAN_TSR_LOW2 (1 << 31) /* Bit 31: Lowest Priority Flag for Mailbox 2 */ + +/* CAN receive FIFO 0/1 registers */ + +#define CAN_RFR_FMP_SHIFT (0) /* Bits 1-0: FIFO Message Pending */ +#define CAN_RFR_FMP_MASK (3 << CAN_RFR_FMP_SHIFT) +#define CAN_RFR_FULL (1 << 3) /* Bit 3: FIFO 0 Full */ +#define CAN_RFR_FOVR (1 << 4) /* Bit 4: FIFO 0 Overrun */ +#define CAN_RFR_RFOM (1 << 5) /* Bit 5: Release FIFO 0 Output Mailbox */ + +/* CAN interrupt enable register */ + +#define CAN_IER_TMEIE (1 << 0) /* Bit 0: Transmit Mailbox Empty Interrupt Enable */ +#define CAN_IER_FMPIE0 (1 << 1) /* Bit 1: FIFO Message Pending Interrupt Enable */ +#define CAN_IER_FFIE0 (1 << 2) /* Bit 2: FIFO Full Interrupt Enable */ +#define CAN_IER_FOVIE0 (1 << 3) /* Bit 3: FIFO Overrun Interrupt Enable */ +#define CAN_IER_FMPIE1 (1 << 4) /* Bit 4: FIFO Message Pending Interrupt Enable */ +#define CAN_IER_FFIE1 (1 << 5) /* Bit 5: FIFO Full Interrupt Enable */ +#define CAN_IER_FOVIE1 (1 << 6) /* Bit 6: FIFO Overrun Interrupt Enable */ +#define CAN_IER_EWGIE (1 << 8) /* Bit 8: Error Warning Interrupt Enable */ +#define CAN_IER_EPVIE (1 << 9) /* Bit 9: Error Passive Interrupt Enable */ +#define CAN_IER_BOFIE (1 << 10) /* Bit 10: Bus-Off Interrupt Enable */ +#define CAN_IER_LECIE (1 << 11) /* Bit 11: Last Error Code Interrupt Enable */ +#define CAN_IER_ERRIE (1 << 15) /* Bit 15: Error Interrupt Enable */ +#define CAN_IER_WKUIE (1 << 16) /* Bit 16: Wakeup Interrupt Enable */ +#define CAN_IER_SLKIE (1 << 17) /* Bit 17: Sleep Interrupt Enable */ + +/* CAN error status register */ + +#define CAN_ESR_EWGF (1 << 0) /* Bit 0: Error Warning Flag */ +#define CAN_ESR_EPVF (1 << 1) /* Bit 1: Error Passive Flag */ +#define CAN_ESR_BOFF (1 << 2) /* Bit 2: Bus-Off Flag */ +#define CAN_ESR_LEC_SHIFT (4) /* Bits 6-4: Last Error Code */ +#define CAN_ESR_LEC_MASK (7 << CAN_ESR_LEC_SHIFT) +# define CAN_ESR_NOERROR (0 << CAN_ESR_LEC_SHIFT) /* 000: No Error */ +# define CAN_ESR_STUFFERROR (1 << CAN_ESR_LEC_SHIFT) /* 001: Stuff Error */ +# define CAN_ESR_FORMERROR (2 << CAN_ESR_LEC_SHIFT) /* 010: Form Error */ +# define CAN_ESR_ACKERROR (3 << CAN_ESR_LEC_SHIFT) /* 011: Acknowledgment Error */ +# define CAN_ESR_BRECERROR (4 << CAN_ESR_LEC_SHIFT) /* 100: Bit recessive Error */ +# define CAN_ESR_BDOMERROR (5 << CAN_ESR_LEC_SHIFT) /* 101: Bit dominant Error */ +# define CAN_ESR_CRCERRPR (6 << CAN_ESR_LEC_SHIFT) /* 110: CRC Error */ +# define CAN_ESR_SWERROR (7 << CAN_ESR_LEC_SHIFT) /* 111: Set by software */ + +#define CAN_ESR_TEC_SHIFT (16) /* Bits 23-16: LS byte of the 9-bit Transmit Error Counter */ +#define CAN_ESR_TEC_MASK (0xff << CAN_ESR_TEC_SHIF) +#define CAN_ESR_REC_SHIFT (24) /* Bits 31-24: Receive Error Counter */ +#define CAN_ESR_REC_MASK (0xff << CAN_ESR_REC_SHIFT) + +/* CAN bit timing register */ + +#define CAN_BTR_BRP_SHIFT (0) /* Bits 9-0: Baud Rate Prescaler */ +#define CAN_BTR_BRP_MASK (0x03ff << CAN_BTR_BRP_SHIFT) +#define CAN_BTR_TS1_SHIFT (16) /* Bits 19-16: Time Segment 1 */ +#define CAN_BTR_TS1_MASK (0x0f << CAN_BTR_TS1_SHIFT) +#define CAN_BTR_TS2_SHIFT (20) /* Bits 22-20: Time Segment 2 */ +#define CAN_BTR_TS2_MASK (7 << CAN_BTR_TS2_SHIFT) +#define CAN_BTR_SJW_SHIFT (24) /* Bits 25-24: Resynchronization Jump Width */ +#define CAN_BTR_SJW_MASK (3 << CAN_BTR_SJW_SHIFT) +#define CAN_BTR_LBKM (1 << 30) /* Bit 30: Loop Back Mode (Debug) */ +#define CAN_BTR_SILM (1 << 31) /* Bit 31: Silent Mode (Debug) */ + +#define CAN_BTR_BRP_MAX (1024) /* Maximum BTR value (without decrement) */ +#define CAN_BTR_TSEG1_MAX (16) /* Maximum TSEG1 value (without decrement) */ +#define CAN_BTR_TSEG2_MAX (8) /* Maximum TSEG2 value (without decrement) */ + +/* TX mailbox identifier register */ + +#define CAN_TIR_TXRQ (1 << 0) /* Bit 0: Transmit Mailbox Request */ +#define CAN_TIR_RTR (1 << 1) /* Bit 1: Remote Transmission Request */ +#define CAN_TIR_IDE (1 << 2) /* Bit 2: Identifier Extension */ +#define CAN_TIR_EXID_SHIFT (3) /* Bit 3-31: Extended Identifier */ +#define CAN_TIR_EXID_MASK (0x1fffffff << CAN_TIR_EXID_SHIFT) +#define CAN_TIR_STID_SHIFT (21) /* Bits 21-31: Standard Identifier */ +#define CAN_TIR_STID_MASK (0x07ff << CAN_TIR_STID_SHIFT) + +/* Mailbox data length control and time stamp register */ + +#define CAN_TDTR_DLC_SHIFT (0) /* Bits 3:0: Data Length Code */ +#define CAN_TDTR_DLC_MASK (0x0f << CAN_TDTR_DLC_SHIFT) +#define CAN_TDTR_TGT (1 << 8) /* Bit 8: Transmit Global Time */ +#define CAN_TDTR_TIME_SHIFT (16) /* Bits 31:16: Message Time Stamp */ +#define CAN_TDTR_TIME_MASK (0xffff << CAN_TDTR_TIME_SHIFT) + +/* Mailbox data low register */ + +#define CAN_TDLR_DATA0_SHIFT (0) /* Bits 7-0: Data Byte 0 */ +#define CAN_TDLR_DATA0_MASK (0xff << CAN_TDLR_DATA0_SHIFT) +#define CAN_TDLR_DATA1_SHIFT (8) /* Bits 15-8: Data Byte 1 */ +#define CAN_TDLR_DATA1_MASK (0xff << CAN_TDLR_DATA1_SHIFT) +#define CAN_TDLR_DATA2_SHIFT (16) /* Bits 23-16: Data Byte 2 */ +#define CAN_TDLR_DATA2_MASK (0xff << CAN_TDLR_DATA2_SHIFT) +#define CAN_TDLR_DATA3_SHIFT (24) /* Bits 31-24: Data Byte 3 */ +#define CAN_TDLR_DATA3_MASK (0xff << CAN_TDLR_DATA3_SHIFT) + +/* Mailbox data high register */ + +#define CAN_TDHR_DATA4_SHIFT (0) /* Bits 7-0: Data Byte 4 */ +#define CAN_TDHR_DATA4_MASK (0xff << CAN_TDHR_DATA4_SHIFT) +#define CAN_TDHR_DATA5_SHIFT (8) /* Bits 15-8: Data Byte 5 */ +#define CAN_TDHR_DATA5_MASK (0xff << CAN_TDHR_DATA5_SHIFT) +#define CAN_TDHR_DATA6_SHIFT (16) /* Bits 23-16: Data Byte 6 */ +#define CAN_TDHR_DATA6_MASK (0xff << CAN_TDHR_DATA6_SHIFT) +#define CAN_TDHR_DATA7_SHIFT (24) /* Bits 31-24: Data Byte 7 */ +#define CAN_TDHR_DATA7_MASK (0xff << CAN_TDHR_DATA7_SHIFT) + +/* Rx FIFO mailbox identifier register */ + +#define CAN_RIR_RTR (1 << 1) /* Bit 1: Remote Transmission Request */ +#define CAN_RIR_IDE (1 << 2) /* Bit 2: Identifier Extension */ +#define CAN_RIR_EXID_SHIFT (3) /* Bit 3-31: Extended Identifier */ +#define CAN_RIR_EXID_MASK (0x1fffffff << CAN_RIR_EXID_SHIFT) +#define CAN_RIR_STID_SHIFT (21) /* Bits 21-31: Standard Identifier */ +#define CAN_RIR_STID_MASK (0x07ff << CAN_RIR_STID_SHIFT) + +/* Receive FIFO mailbox data length control and time stamp register */ + +#define CAN_RDTR_DLC_SHIFT (0) /* Bits 3:0: Data Length Code */ +#define CAN_RDTR_DLC_MASK (0x0f << CAN_RDTR_DLC_SHIFT) +#define CAN_RDTR_FMI_SHIFT (8) /* Bits 15-8: Filter Match Index */ +#define CAN_RDTR_FMI_MASK (0xff << CAN_RDTR_FM_SHIFT) +#define CAN_RDTR_TIME_SHIFT (16) /* Bits 31:16: Message Time Stamp */ +#define CAN_RDTR_TIME_MASK (0xffff << CAN_RDTR_TIME_SHIFT) + +/* Receive FIFO mailbox data low register */ + +#define CAN_RDLR_DATA0_SHIFT (0) /* Bits 7-0: Data Byte 0 */ +#define CAN_RDLR_DATA0_MASK (0xff << CAN_RDLR_DATA0_SHIFT) +#define CAN_RDLR_DATA1_SHIFT (8) /* Bits 15-8: Data Byte 1 */ +#define CAN_RDLR_DATA1_MASK (0xff << CAN_RDLR_DATA1_SHIFT) +#define CAN_RDLR_DATA2_SHIFT (16) /* Bits 23-16: Data Byte 2 */ +#define CAN_RDLR_DATA2_MASK (0xff << CAN_RDLR_DATA2_SHIFT) +#define CAN_RDLR_DATA3_SHIFT (24) /* Bits 31-24: Data Byte 3 */ +#define CAN_RDLR_DATA3_MASK (0xff << CAN_RDLR_DATA3_SHIFT) + +/* Receive FIFO mailbox data high register */ + +#define CAN_RDHR_DATA4_SHIFT (0) /* Bits 7-0: Data Byte 4 */ +#define CAN_RDHR_DATA4_MASK (0xff << CAN_RDHR_DATA4_SHIFT) +#define CAN_RDHR_DATA5_SHIFT (8) /* Bits 15-8: Data Byte 5 */ +#define CAN_RDHR_DATA5_MASK (0xff << CAN_RDHR_DATA5_SHIFT) +#define CAN_RDHR_DATA6_SHIFT (16) /* Bits 23-16: Data Byte 6 */ +#define CAN_RDHR_DATA6_MASK (0xff << CAN_RDHR_DATA6_SHIFT) +#define CAN_RDHR_DATA7_SHIFT (24) /* Bits 31-24: Data Byte 7 */ +#define CAN_RDHR_DATA7_MASK (0xff << CAN_RDHR_DATA7_SHIFT) + +/* CAN filter master register */ + +#define CAN_FMR_FINIT (1 << 0) /* Bit 0: Filter Init Mode */ + +/* CAN filter mode register */ + +#define CAN_FM1R_FBM_SHIFT (0) /* Bits 13:0: Filter Mode */ +#define CAN_FM1R_FBM_MASK (0x3fff << CAN_FM1R_FBM_SHIFT) + +/* CAN filter scale register */ + +#define CAN_FS1R_FSC_SHIFT (0) /* Bits 13:0: Filter Scale Configuration */ +#define CAN_FS1R_FSC_MASK (0x3fff << CAN_FS1R_FSC_SHIFT) + +/* CAN filter FIFO assignment register */ + +#define CAN_FFA1R_FFA_SHIFT (0) /* Bits 13:0: Filter FIFO Assignment */ +#define CAN_FFA1R_FFA_MASK (0x3fff << CAN_FFA1R_FFA_SHIFT) + +/* CAN filter activation register */ + +#define CAN_FA1R_FACT_SHIFT (0) /* Bits 13:0: Filter Active */ +#define CAN_FA1R_FACT_MASK (0x3fff << CAN_FA1R_FACT_SHIFT) + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_CAN_BXCAN_M0_H */ diff --git a/arch/arm/src/common/stm32/hardware/stm32_comp.h b/arch/arm/src/common/stm32/hardware/stm32_comp.h new file mode 100644 index 0000000000000..364b1f8a418a6 --- /dev/null +++ b/arch/arm/src/common/stm32/hardware/stm32_comp.h @@ -0,0 +1,45 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/hardware/stm32_comp.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_COMP_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_COMP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#if (defined(CONFIG_STM32_HAVE_IP_COMP_M0_V1) + \ + defined(CONFIG_STM32_HAVE_IP_COMP_M3M4_V1) + \ + defined(CONFIG_STM32_HAVE_IP_COMP_M3M4_V2)) > 1 +# error Only one STM32 COMP IP version must be selected +#endif + +#if defined(CONFIG_STM32_HAVE_IP_COMP_M0_V1) +# include "hardware/stm32_comp_m0.h" +#elif defined(CONFIG_STM32_HAVE_IP_COMP_M3M4_V1) || \ + defined(CONFIG_STM32_HAVE_IP_COMP_M3M4_V2) +# include "hardware/stm32_comp_v1v2.h" +#else +# error "Unsupported STM32 COMP" +#endif + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_COMP_H */ diff --git a/arch/arm/src/common/stm32/hardware/stm32_comp_m0.h b/arch/arm/src/common/stm32/hardware/stm32_comp_m0.h new file mode 100644 index 0000000000000..06672e2ff1dae --- /dev/null +++ b/arch/arm/src/common/stm32/hardware/stm32_comp_m0.h @@ -0,0 +1,124 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/hardware/stm32_comp_m0.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_COMP_M0_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_COMP_M0_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "chip.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Register Offsets *********************************************************/ + +#define STM32_COMP_CSR_OFFSET 0x001c /* COMP1/COMP2 Control register */ + +/* Register Addresses *******************************************************/ + +#define STM32_COMP_CSR (STM32_COMP_BASE + STM32_COMP_CSR_OFFSET) + +/* Register Bitfield Definitions ********************************************/ + +/* COMP control and status register */ + +#define COMP_CSR_COMP1EN (1 << 0) /* Bit 0: Comparator 1 enable */ +#define COMP_CSR_COMP1SW1 (1 << 1) /* Bit 1: Comparator 1 non inverting input DAC switch */ +#define COMP_CSR_COMP1MODE_SHIFT (2) /* Bits 2-3: Compator 1 mode */ +#define COMP_CSR_COMP1MODE_MASK (3 << COMP_CSR_COMP1MODE_SHIFT) +# define COMP_CSR_COMP1MODE_HIGH (0 << COMP_CSR_COMP1MODE_SHIFT) /* 00: High Speed / full power */ +# define COMP_CSR_COMP1MODE_MEDIUM (1 << COMP_CSR_COMP1MODE_SHIFT) /* 01: Medium Speed / medium power */ +# define COMP_CSR_COMP1MODE_LOW (2 << COMP_CSR_COMP1MODE_SHIFT) /* 10: Low Speed / low-power */ +# define COMP_CSR_COMP1MODE_VLOW (3 << COMP_CSR_COMP1MODE_SHIFT) /* 11: Very-low Speed / ultra-low power */ +#define COMP_CSR_COMP1INSEL_SHIFT (4) /* Bits 4-6: Comparator 1 inverting input selection */ +#define COMP_CSR_COMP1INSEL_MASK (7 << COMP_CSR_COMP1INSEL_SHIFT) +# define COMP_CSR_COMP1INSEL_1P4VREF (0 << COMP_CSR_COMP1INSEL_SHIFT) /* 000: 1/4 of Vrefint */ +# define COMP_CSR_COMP1INSEL_1P2VREF (1 << COMP_CSR_COMP1INSEL_SHIFT) /* 001: 1/2 of Vrefint */ +# define COMP_CSR_COMP1INSEL_3P4VREF (2 << COMP_CSR_COMP1INSEL_SHIFT) /* 010: 3/4 of Vrefint */ +# define COMP_CSR_COMP1INSEL_VREF (3 << COMP_CSR_COMP1INSEL_SHIFT) /* 011: Vrefint */ +# define COMP_CSR_COMP1INSEL_INM4 (4 << COMP_CSR_COMP1INSEL_SHIFT) /* 100: COMP1_INM4 (PA4 DAC_OUT1 if enabled) */ +# define COMP_CSR_COMP1INSEL_INM5 (5 << COMP_CSR_COMP1INSEL_SHIFT) /* 101: COMP1_INM5 (PA5 DAC_OUT2 if present and enabled) */ +# define COMP_CSR_COMP1INSEL_INM6 (6 << COMP_CSR_COMP1INSEL_SHIFT) /* 110: COMP1_INM6 (PA0) */ +#define COMP_CSR_COMP1OUTSEL_SHIFT (8) /* Bits 8-10: Comparator 1 output selection*/ +#define COMP_CSR_COMP1OUTSEL_MASK (7 << COMP_CSR_COMP1OUTSEL_MASK) +# define COMP_CSR_COMP1OUTSEL_NOSEL (0 << COMP_CSR_COMP1OUTSEL_MASK) /* 000: no selection */ +# define COMP_CSR_COMP1OUTSEL_T1BRK (1 << COMP_CSR_COMP1OUTSEL_MASK) /* 001: Timer 1 break input */ +# define COMP_CSR_COMP1OUTSEL_T1ICAP (2 << COMP_CSR_COMP1OUTSEL_MASK) /* 010: Timer 1 Input capture 1 */ +# define COMP_CSR_COMP1OUTSEL_T1OCRC (3 << COMP_CSR_COMP1OUTSEL_MASK) /* 011: Timer 1 OCrefclear input */ +# define COMP_CSR_COMP1OUTSEL_T2ICAP (4 << COMP_CSR_COMP1OUTSEL_MASK) /* 100: Timer 2 input capture 4 */ +# define COMP_CSR_COMP1OUTSEL_T2OCRC (5 << COMP_CSR_COMP1OUTSEL_MASK) /* 101: Timer 2 OCrefclear input */ +# define COMP_CSR_COMP1OUTSEL_T3ICAP (6 << COMP_CSR_COMP1OUTSEL_MASK) /* 110: Timer 3 input capture 1 */ +# define COMP_CSR_COMP1OUTSEL_T3OCRC (7 << COMP_CSR_COMP1OUTSEL_MASK) /* 111: Timer 3 OCrefclear input */ +#define COMP_CSR_COMP1POL (1 << 11) /* Bit 11: Comparator 1 output polarity */ +#define COMP_CSR_COMP1HYST_SHIFT (12) /* Bits 12-13: Comparator 1 hysteresis */ +#define COMP_CSR_COMP1HYST_MASK (3 << COMP_CSR_COMP1HYST_SHIFT) +# define COMP_CSR_COMP1HYST_NOHYST (0 << COMP_CSR_COMP1HYST_MASK) /* 00: No hysteresis */ +# define COMP_CSR_COMP1HYST_LOWHYST (1 << COMP_CSR_COMP1HYST_MASK) /* 01: Low hysteresis */ +# define COMP_CSR_COMP1HYST_MDHYST (2 << COMP_CSR_COMP1HYST_MASK) /* 10: Medium hysteresis */ +# define COMP_CSR_COMP1HYST_HIHYST (3 << COMP_CSR_COMP1HYST_MASK) /* 11: Low hysteresis */ +#define COMP_CSR_COMP1OUT (1 << 14) /* Bit 14: Comparator 1 output */ +#define COMP_CSR_COMP1LOCK (1 << 15) /* Bit 15: Comparator 1 lock */ + +#define COMP_CSR_COMP2EN (1 << 16) /* Bit 16: Comparator 2 enable */ +#define COMP_CSR_COMP2MODE_SHIFT (18) /* Bits 18-19: Compator 2 mode */ +#define COMP_CSR_COMP2MODE_MASK (3 << COMP_CSR_COMP2MODE_SHIFT) +# define COMP_CSR_COMP2MODE_HIGH (0 << COMP_CSR_COMP2MODE_SHIFT) /* 00: High Speed / full power */ +# define COMP_CSR_COMP2MODE_MEDIUM (1 << COMP_CSR_COMP2MODE_SHIFT) /* 01: Medium Speed / medium power */ +# define COMP_CSR_COMP2MODE_LOW (2 << COMP_CSR_COMP2MODE_SHIFT) /* 10: Low Speed / low-power */ +# define COMP_CSR_COMP2MODE_VLOW (3 << COMP_CSR_COMP2MODE_SHIFT) /* 11: Very-low Speed / ultra-low power */ +#define COMP_CSR_COMP2INSEL_SHIFT (20) /* Bits 20-22: Comparator 2 inverting input selection */ +#define COMP_CSR_COMP2INSEL_MASK (7 << COMP_CSR_COMP2INSEL_SHIFT) +# define COMP_CSR_COMP2INSEL_1P4VREF (0 << COMP_CSR_COMP2INSEL_SHIFT) /* 000: 1/4 of Vrefint */ +# define COMP_CSR_COMP2INSEL_1P2VREF (1 << COMP_CSR_COMP2INSEL_SHIFT) /* 001: 1/2 of Vrefint */ +# define COMP_CSR_COMP2INSEL_3P4VREF (2 << COMP_CSR_COMP2INSEL_SHIFT) /* 010: 3/4 of Vrefint */ +# define COMP_CSR_COMP2INSEL_VREF (3 << COMP_CSR_COMP2INSEL_SHIFT) /* 011: Vrefint */ +# define COMP_CSR_COMP2INSEL_INM4 (4 << COMP_CSR_COMP2INSEL_SHIFT) /* 100: COMP1_INM4 (PA4 DAC_OUT1 if enabled) */ +# define COMP_CSR_COMP2INSEL_INM5 (5 << COMP_CSR_COMP2INSEL_SHIFT) /* 101: COMP1_INM5 (PA5 DAC_OUT2 if present and enabled) */ +# define COMP_CSR_COMP2INSEL_INM6 (6 << COMP_CSR_COMP2INSEL_SHIFT) /* 110: COMP1_INM6 (PA2) */ +#define COMP_CSR_WNDWEN (1 << 23) /* Bit 23: Window mode enable */ +#define COMP_CSR_COMP2OUTSEL_SHIFT (24) /* Bits 24-26: Comparator 1 output selection*/ +#define COMP_CSR_COMP2OUTSEL_MASK (7 << COMP_CSR_COMP2OUTSEL_MASK) +# define COMP_CSR_COMP2OUTSEL_NOSEL (0 << COMP_CSR_COMP2OUTSEL_MASK) /* 000: no selection */ +# define COMP_CSR_COMP2OUTSEL_T1BRK (1 << COMP_CSR_COMP2OUTSEL_MASK) /* 001: Timer 1 break input */ +# define COMP_CSR_COMP2OUTSEL_T1ICAP (2 << COMP_CSR_COMP2OUTSEL_MASK) /* 010: Timer 1 Input capture 1 */ +# define COMP_CSR_COMP2OUTSEL_T1OCRC (3 << COMP_CSR_COMP2OUTSEL_MASK) /* 011: Timer 1 OCrefclear input */ +# define COMP_CSR_COMP2OUTSEL_T2ICAP (4 << COMP_CSR_COMP2OUTSEL_MASK) /* 100: Timer 2 input capture 4 */ +# define COMP_CSR_COMP2OUTSEL_T2OCRC (5 << COMP_CSR_COMP2OUTSEL_MASK) /* 101: Timer 2 OCrefclear input */ +# define COMP_CSR_COMP2OUTSEL_T3ICAP (6 << COMP_CSR_COMP2OUTSEL_MASK) /* 110: Timer 3 input capture 1 */ +# define COMP_CSR_COMP2OUTSEL_T3OCRC (7 << COMP_CSR_COMP2OUTSEL_MASK) /* 111: Timer 3 OCrefclear input */ +#define COMP_CSR_COMP2POL (1 << 27) /* Bit 27: Comparator 2 output polarity */ +#define COMP_CSR_COMP2HYST_SHIFT (12) /* Bits 12-13: Comparator 1 hysteresis */ +#define COMP_CSR_COMP2HYST_MASK (3 << COMP_CSR_COMP2HYST_SHIFT) +# define COMP_CSR_COMP2HYST_NOHYST (0 << COMP_CSR_COMP2HYST_MASK) /* 00: No hysteresis */ +# define COMP_CSR_COMP2HYST_LOWHYST (1 << COMP_CSR_COMP2HYST_MASK) /* 01: Low hysteresis */ +# define COMP_CSR_COMP2HYST_MDHYST (2 << COMP_CSR_COMP2HYST_MASK) /* 10: Medium hysteresis */ +# define COMP_CSR_COMP2HYST_HIHYST (3 << COMP_CSR_COMP2HYST_MASK) /* 11: Low hysteresis */ +#define COMP_CSR_COMP2OUT (1 << 14) /* Bit 14: Comparator 1 output */ +#define COMP_CSR_COMP2LOCK (1 << 15) /* Bit 15: Comparator 1 lock */ + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_COMP_M0_H */ diff --git a/arch/arm/src/common/stm32/hardware/stm32_comp_v1v2.h b/arch/arm/src/common/stm32/hardware/stm32_comp_v1v2.h new file mode 100644 index 0000000000000..94c93d429ba9a --- /dev/null +++ b/arch/arm/src/common/stm32/hardware/stm32_comp_v1v2.h @@ -0,0 +1,60 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/hardware/stm32_comp_v1v2.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_COMP_V1V2_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_COMP_V1V2_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "chip.h" + +#ifdef CONFIG_STM32_COMP + +/* Include the correct COMP register definitions for + * selected STM32 COMP IP core: + */ + +/* If more than one COMP IP ensure that only one is selected */ + +#if defined(CONFIG_STM32_HAVE_IP_COMP_M3M4_V1) +# if defined(CONFIG_STM32_STM32F33XX) +# include "hardware/stm32f33xxx_comp.h" +# else +# error "Device not supported." +# endif +#elif defined(CONFIG_STM32_HAVE_IP_COMP_M3M4_V2) +# if defined(CONFIG_STM32_STM32G4XXX) +# include "hardware/stm32g4xxxx_comp.h" +# else +# error "Device not supported." +# endif +#else +# error "STM32 COMP IP not supported." +#endif + +#endif /* CONFIG_STM32_COMP */ + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_COMP_V1V2_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32_crc.h b/arch/arm/src/common/stm32/hardware/stm32_crc.h similarity index 94% rename from arch/arm/src/stm32f0l0g0/hardware/stm32_crc.h rename to arch/arm/src/common/stm32/hardware/stm32_crc.h index 8aa180ded0e30..6b51ac8e12bdd 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32_crc.h +++ b/arch/arm/src/common/stm32/hardware/stm32_crc.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32_crc.h + * arch/arm/src/common/stm32/hardware/stm32_crc.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_CRC_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_CRC_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_CRC_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_CRC_H /**************************************************************************** * Included Files @@ -79,4 +79,4 @@ * Public Functions Prototypes ****************************************************************************/ -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_CRC_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_CRC_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32_crs.h b/arch/arm/src/common/stm32/hardware/stm32_crs.h similarity index 96% rename from arch/arm/src/stm32f0l0g0/hardware/stm32_crs.h rename to arch/arm/src/common/stm32/hardware/stm32_crs.h index 00e007a49cdd8..b544f9728c819 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32_crs.h +++ b/arch/arm/src/common/stm32/hardware/stm32_crs.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32_crs.h + * arch/arm/src/common/stm32/hardware/stm32_crs.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_CRS_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_CRS_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_CRS_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_CRS_H /**************************************************************************** * Pre-processor Definitions @@ -100,4 +100,4 @@ #define CRS_ICR_ERRC (1 << 2) /* Bit 2: Error clear flag */ #define CRS_ICR_ESYNCC (1 << 3) /* Bit 3: Expected SYNC clear flag */ -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_CRS_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_CRS_H */ diff --git a/arch/arm/src/common/stm32/hardware/stm32_dac.h b/arch/arm/src/common/stm32/hardware/stm32_dac.h new file mode 100644 index 0000000000000..dd8df7ed9b1bd --- /dev/null +++ b/arch/arm/src/common/stm32/hardware/stm32_dac.h @@ -0,0 +1,45 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/hardware/stm32_dac.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DAC_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DAC_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#if (defined(CONFIG_STM32_HAVE_IP_DAC_M0_V1) + \ + defined(CONFIG_STM32_HAVE_IP_DAC_M3M4_V1) + \ + defined(CONFIG_STM32_HAVE_IP_DAC_M3M4_V2)) > 1 +# error Only one STM32 DAC IP version must be selected +#endif + +#if defined(CONFIG_STM32_HAVE_IP_DAC_M0_V1) +# include "hardware/stm32_dac_m0.h" +#elif defined(CONFIG_STM32_HAVE_IP_DAC_M3M4_V1) || \ + defined(CONFIG_STM32_HAVE_IP_DAC_M3M4_V2) +# include "hardware/stm32_dac_v1v2.h" +#else +# error "Unsupported STM32 DAC" +#endif + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DAC_H */ diff --git a/arch/arm/src/common/stm32/hardware/stm32_dac_m0.h b/arch/arm/src/common/stm32/hardware/stm32_dac_m0.h new file mode 100644 index 0000000000000..f95f33e87c2f2 --- /dev/null +++ b/arch/arm/src/common/stm32/hardware/stm32_dac_m0.h @@ -0,0 +1,211 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/hardware/stm32_dac_m0.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DAC_M0_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DAC_M0_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include "chip.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Register Offsets *********************************************************/ + +#define STM32_DAC_CR_OFFSET 0x0000 /* DAC control register */ +#define STM32_DAC_SWTRIGR_OFFSET 0x0004 /* DAC software trigger register */ +#define STM32_DAC_DHR12R1_OFFSET 0x0008 /* DAC channel 1 12-bit right-aligned data holding register */ +#define STM32_DAC_DHR12L1_OFFSET 0x000c /* DAC channel 1 12-bit left aligned data holding register */ +#define STM32_DAC_DHR8R1_OFFSET 0x0010 /* DAC channel 1 8-bit right aligned data holding register */ +#define STM32_DAC_DHR12R2_OFFSET 0x0014 /* DAC channel 2 12-bit right aligned data holding register */ +#define STM32_DAC_DHR12L2_OFFSET 0x0018 /* DAC channel 2 12-bit left aligned data holding register */ +#define STM32_DAC_DHR8R2_OFFSET 0x001c /* DAC channel 2 8-bit right-aligned data holding register */ +#define STM32_DAC_DHR12RD_OFFSET 0x0020 /* Dual DAC 12-bit right-aligned data holding register */ +#define STM32_DAC_DHR12LD_OFFSET 0x0024 /* DUAL DAC 12-bit left aligned data holding register */ +#define STM32_DAC_DHR8RD_OFFSET 0x0028 /* DUAL DAC 8-bit right aligned data holding register */ +#define STM32_DAC_DOR1_OFFSET 0x002c /* DAC channel 1 data output register */ +#define STM32_DAC_DOR2_OFFSET 0x0030 /* DAC channel 2 data output register */ +#define STM32_DAC_SR_OFFSET 0x0034 /* DAC status register */ + +/* Register Addresses *******************************************************/ + +/* DAC */ + +#define STM32_DAC1_CR (STM32_DAC1_BASE + STM32_DAC_CR_OFFSET) +#define STM32_DAC1_SWTRIGR (STM32_DAC1_BASE + STM32_DAC_SWTRIGR_OFFSET) +#define STM32_DAC1_DHR12R1 (STM32_DAC1_BASE + STM32_DAC_DHR12R1_OFFSET) +#define STM32_DAC1_DHR12L1 (STM32_DAC1_BASE + STM32_DAC_DHR12L1_OFFSET) +#define STM32_DAC1_DHR8R1 (STM32_DAC1_BASE + STM32_DAC_DHR8R1_OFFSET) +#define STM32_DAC1_DHR12R2 (STM32_DAC1_BASE + STM32_DAC_DHR12R2_OFFSET) +#define STM32_DAC1_DHR12L2 (STM32_DAC1_BASE + STM32_DAC_DHR12L2_OFFSET) +#define STM32_DAC1_DHR8R2 (STM32_DAC1_BASE + STM32_DAC_DHR8R2_OFFSET) +#define STM32_DAC1_DHR12RD (STM32_DAC1_BASE + STM32_DAC_DHR12RD_OFFSET) +#define STM32_DAC1_DHR12LD (STM32_DAC1_BASE + STM32_DAC_DHR12LD_OFFSET) +#define STM32_DAC1_DHR8RD (STM32_DAC1_BASE + STM32_DAC_DHR8RD_OFFSET) +#define STM32_DAC1_DOR1 (STM32_DAC1_BASE + STM32_DAC_DOR1_OFFSET) +#define STM32_DAC1_DOR2 (STM32_DAC1_BASE + STM32_DAC_DOR2_OFFSET) +#define STM32_DAC1_SR (STM32_DAC1_BASE + STM32_DAC_SR_OFFSET) + +/* Register Bitfield Definitions ********************************************/ + +/* DAC control register */ + +/* These definitions may be used with the full, 32-bit register */ + +#define DAC_CR_EN1 (1 << 0) /* Bit 0: DAC channel 1 enable */ +#define DAC_CR_BOFF1 (1 << 1) /* Bit 1: DAC channel 1 output buffer disable */ +#define DAC_CR_TEN1 (1 << 2) /* Bit 2: DAC channel 1 trigger enable */ +#define DAC_CR_TSEL1_SHIFT (3) /* Bits 3-5: DAC channel 1 trigger selection */ +#define DAC_CR_TSEL1_MASK (7 << DAC_CR_TSEL1_SHIFT) +# define DAC_CR_TSEL1_TIM6 (0 << DAC_CR_TSEL1_SHIFT) /* Timer 6 TRGO event */ +# define DAC_CR_TSEL1_TIM3 (1 << DAC_CR_TSEL1_SHIFT) /* Timer 3 TRGO event */ +# define DAC_CR_TSEL1_TIM7 (2 << DAC_CR_TSEL1_SHIFT) /* Timer 7 TRGO event */ +# define DAC_CR_TSEL1_TIM15 (3 << DAC_CR_TSEL1_SHIFT) /* Timer 15 TRGO event, or */ +# define DAC_CR_TSEL1_TIM2 (4 << DAC_CR_TSEL1_SHIFT) /* Timer 2 TRGO event */ +# define DAC_CR_TSEL1_EXT9 (6 << DAC_CR_TSEL1_SHIFT) /* External line9 */ +# define DAC_CR_TSEL1_SW (7 << DAC_CR_TSEL1_SHIFT) /* Software trigger */ + +#define DAC_CR_WAVE1_SHIFT (6) /* Bits 6-7: DAC channel 1 noise/triangle wave generation */ +#define DAC_CR_WAVE1_MASK (3 << DAC_CR_WAVE1_SHIFT) +# define DAC_CR_WAVE1_DISABLED (0 << DAC_CR_WAVE1_SHIFT) /* Wave generation disabled */ +# define DAC_CR_WAVE1_NOISE (1 << DAC_CR_WAVE1_SHIFT) /* Noise wave generation enabled */ +# define DAC_CR_WAVE1_TRIANGLE (2 << DAC_CR_WAVE1_SHIFT) /* Triangle wave generation enabled */ + +#define DAC_CR_MAMP1_SHIFT (8) /* Bits 8-11: DAC channel 1 mask/amplitude selector */ +#define DAC_CR_MAMP1_MASK (15 << DAC_CR_MAMP1_SHIFT) +# define DAC_CR_MAMP1_AMP1 (0 << DAC_CR_MAMP1_SHIFT) /* Unmask bit0 of LFSR/triangle amplitude=1 */ +# define DAC_CR_MAMP1_AMP3 (1 << DAC_CR_MAMP1_SHIFT) /* Unmask bits[1:0] of LFSR/triangle amplitude=3 */ +# define DAC_CR_MAMP1_AMP7 (2 << DAC_CR_MAMP1_SHIFT) /* Unmask bits[2:0] of LFSR/triangle amplitude=7 */ +# define DAC_CR_MAMP1_AMP15 (3 << DAC_CR_MAMP1_SHIFT) /* Unmask bits[3:0] of LFSR/triangle amplitude=15 */ +# define DAC_CR_MAMP1_AMP31 (4 << DAC_CR_MAMP1_SHIFT) /* Unmask bits[4:0] of LFSR/triangle amplitude=31 */ +# define DAC_CR_MAMP1_AMP63 (5 << DAC_CR_MAMP1_SHIFT) /* Unmask bits[5:0] of LFSR/triangle amplitude=63 */ +# define DAC_CR_MAMP1_AMP127 (6 << DAC_CR_MAMP1_SHIFT) /* Unmask bits[6:0] of LFSR/triangle amplitude=127 */ +# define DAC_CR_MAMP1_AMP255 (7 << DAC_CR_MAMP1_SHIFT) /* Unmask bits[7:0] of LFSR/triangle amplitude=255 */ +# define DAC_CR_MAMP1_AMP511 (8 << DAC_CR_MAMP1_SHIFT) /* Unmask bits[8:0] of LFSR/triangle amplitude=511 */ +# define DAC_CR_MAMP1_AMP1023 (9 << DAC_CR_MAMP1_SHIFT) /* Unmask bits[9:0] of LFSR/triangle amplitude=1023 */ +# define DAC_CR_MAMP1_AMP2047 (10 << DAC_CR_MAMP1_SHIFT) /* Unmask bits[10:0] of LFSR/triangle amplitude=2047 */ +# define DAC_CR_MAMP1_AMP4095 (11 << DAC_CR_MAMP1_SHIFT) /* Unmask bits[11:0] of LFSR/triangle amplitude=4095 */ + +#define DAC_CR_DMAEN1 (1 << 12) /* Bit 12: DAC channel 1 DMA enable */ +#define DAC_CR_DMAUDRIE1 (1 << 13) /* Bit 13: DAC channel 1 DMA Underrun Interrupt enable */ + +#define DAC_CR_EN2 (1 << 16) /* Bit 16: DAC channel 2 enable */ +#define DAC_CR_BOFF2 (1 << 17) /* Bit 17: DAC channel 2 output buffer disable */ +#define DAC_CR_TEN2 (1 << 18) /* Bit 18: DAC channel 2 trigger enable */ +#define DAC_CR_TSEL2_SHIFT (19) /* Bits 19-21: DAC channel 2 trigger selection */ +#define DAC_CR_TSEL2_MASK (7 << DAC_CR_TSEL2_SHIFT) +# define DAC_CR_TSEL2_TIM6 (0 << DAC_CR_TSEL2_SHIFT) /* Timer 6 TRGO event */ +# define DAC_CR_TSEL2_TIM3 (1 << DAC_CR_TSEL2_SHIFT) /* Timer 3 TRGO event */ +# define DAC_CR_TSEL2_TIM7 (2 << DAC_CR_TSEL2_SHIFT) /* Timer 7 TRGO event */ +# define DAC_CR_TSEL2_TIM15 (3 << DAC_CR_TSEL2_SHIFT) /* Timer 15 TRGO event */ +# define DAC_CR_TSEL2_TIM2 (4 << DAC_CR_TSEL2_SHIFT) /* Timer 2 TRGO event */ +# define DAC_CR_TSEL2_EXT9 (6 << DAC_CR_TSEL2_SHIFT) /* External line9 */ +# define DAC_CR_TSEL2_SW (7 << DAC_CR_TSEL2_SHIFT) /* Software trigger */ + +#define DAC_CR_WAVE2_SHIFT (22) /* Bit 22-23: DAC channel 2 noise/triangle wave generation enable */ +#define DAC_CR_WAVE2_MASK (3 << DAC_CR_WAVE2_SHIFT) +# define DAC_CR_WAVE2_DISABLED (0 << DAC_CR_WAVE2_SHIFT) /* Wave generation disabled */ +# define DAC_CR_WAVE2_NOISE (1 << DAC_CR_WAVE2_SHIFT) /* Noise wave generation enabled */ +# define DAC_CR_WAVE2_TRIANGLE (2 << DAC_CR_WAVE2_SHIFT) /* Triangle wave generation enabled */ + +#define DAC_CR_MAMP2_SHIFT (24) /* Bit 24-27: DAC channel 2 mask/amplitude selector */ +#define DAC_CR_MAMP2_MASK (15 << DAC_CR_MAMP2_SHIFT) +# define DAC_CR_MAMP2_AMP1 (0 << DAC_CR_MAMP2_SHIFT) /* Unmask bit0 of LFSR/triangle amplitude=1 */ +# define DAC_CR_MAMP2_AMP3 (1 << DAC_CR_MAMP2_SHIFT) /* Unmask bits[1:0] of LFSR/triangle amplitude=3 */ +# define DAC_CR_MAMP2_AMP7 (2 << DAC_CR_MAMP2_SHIFT) /* Unmask bits[2:0] of LFSR/triangle amplitude=7 */ +# define DAC_CR_MAMP2_AMP15 (3 << DAC_CR_MAMP2_SHIFT) /* Unmask bits[3:0] of LFSR/triangle amplitude=15 */ +# define DAC_CR_MAMP2_AMP31 (4 << DAC_CR_MAMP2_SHIFT) /* Unmask bits[4:0] of LFSR/triangle amplitude=31 */ +# define DAC_CR_MAMP2_AMP63 (5 << DAC_CR_MAMP2_SHIFT) /* Unmask bits[5:0] of LFSR/triangle amplitude=63 */ +# define DAC_CR_MAMP2_AMP127 (6 << DAC_CR_MAMP2_SHIFT) /* Unmask bits[6:0] of LFSR/triangle amplitude=127 */ +# define DAC_CR_MAMP2_AMP255 (7 << DAC_CR_MAMP2_SHIFT) /* Unmask bits[7:0] of LFSR/triangle amplitude=255 */ +# define DAC_CR_MAMP2_AMP511 (8 << DAC_CR_MAMP2_SHIFT) /* Unmask bits[8:0] of LFSR/triangle amplitude=511 */ +# define DAC_CR_MAMP2_AMP1023 (9 << DAC_CR_MAMP2_SHIFT) /* Unmask bits[9:0] of LFSR/triangle amplitude=1023 */ +# define DAC_CR_MAMP2_AMP2047 (10 << DAC_CR_MAMP2_SHIFT) /* Unmask bits[10:0] of LFSR/triangle amplitude=2047 */ +# define DAC_CR_MAMP2_AMP4095 (11 << DAC_CR_MAMP2_SHIFT) /* Unmask bits[11:0] of LFSR/triangle amplitude=4095 */ + +#define DAC_CR_DMAEN2 (1 << 28) /* Bit 28: DAC channel 2 DMA enable */ +#define DAC_CR_DMAUDRIE2 (1 << 29) /* Bit 29: DAC channel 2 DMA underrun interrupt enable */ + +/* DAC software trigger register */ + +#define DAC_SWTRIGR_SWTRIG(n) (1 << ((n)-1)) +#define DAC_SWTRIGR_SWTRIG1 (1 << 0) /* Bit 0: DAC channel 1 software trigger */ +#define DAC_SWTRIGR_SWTRIG2 (1 << 1) /* Bit 1: DAC channel 2 software trigger */ + +/* DAC channel 1/2 12-bit right-aligned data holding register */ + +#define DAC_DHR12R_MASK (0x0fff) + +/* DAC channel 1/2 12-bit left aligned data holding register */ + +#define DAC_DHR12L_MASK (0xfff0) + +/* DAC channel 1/2 8-bit right aligned data holding register */ + +#define DAC_DHR8R_MASK (0x00ff) + +/* Dual DAC 12-bit right-aligned data holding register */ + +#define DAC_DHR12RD_DACC_SHIFT(n) (((n)-1) << 4) +#define DAC_DHR12RD_DACC_MASK(n) (0xfff << DAC_DHR12RD_DACC_SHIFT(n)) + +#define DAC_DHR12RD_DACC1_SHIFT (0) /* Bits 0-11: DAC channel 1 12-bit right-aligned data */ +#define DAC_DHR12RD_DACC1_MASK (0xfff << DAC_DHR12RD_DACC1_SHIFT) +#define DAC_DHR12RD_DACC2_SHIFT (16) /* Bits 16-27: DAC channel 2 12-bit right-aligned data */ +#define DAC_DHR12RD_DACC2_MASK (0xfff << DAC_DHR12RD_DACC2_SHIFT) + +/* Dual DAC 12-bit left-aligned data holding register */ + +#define DAC_DHR12LD_DACC_SHIFT(n) ((((n)-1) << 4) + 4) +#define DAC_DHR12LD_DACC_MASK(n) (0xfff << DAC_DHR12LD_DACC_SHIFT(n)) + +#define DAC_DHR12LD_DACC1_SHIFT (4) /* Bits 4-15: DAC channel 1 12-bit left-aligned data */ +#define DAC_DHR12LD_DACC1_MASK (0xfff << DAC_DHR12LD_DACC1_SHIFT) +#define DAC_DHR12LD_DACC2_SHIFT (20) /* Bits 20-31: DAC channel 2 12-bit left-aligned data */ +#define DAC_DHR12LD_DACC2_MASK (0xfff << DAC_DHR12LD_DACC2_SHIFT) + +/* DUAL DAC 8-bit right aligned data holding register */ + +#define DAC_DHR8RD_DACC_SHIFT(n) (((n)-1) << 3) +#define DAC_DHR8RD_DACC_MASK(n) (0xff << DAC_DHR8RD_DACC_SHIFT(n)) + +#define DAC_DHR8RD_DACC1_SHIFT (0) /* Bits 0-7: DAC channel 1 8-bit right-aligned data */ +#define DAC_DHR8RD_DACC1_MASK (0xff << DAC_DHR8RD_DACC1_SHIFT) +#define DAC_DHR8RD_DACC2_SHIFT (8) /* Bits 8-15: DAC channel 2 8-bit right-aligned data */ +#define DAC_DHR8RD_DACC2_MASK (0xff << DAC_DHR8RD_DACC2_SHIFT) + +/* DAC channel 1/2 data output register */ + +#define DAC_DOR_MASK (0x0fff) + +/* DAC status register */ + +#define DAC_SR_DMAUDR(n) (1 << ((((n)-1) << 4) + 13)) +#define DAC_SR_DMAUDR1 (1 << 13) /* Bit 13: DAC channel 1 DMA underrun flag */ +#define DAC_SR_DMAUDR2 (1 << 29) /* Bit 29: DAC channel 2 DMA underrun flag */ + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DAC_M0_H */ diff --git a/arch/arm/src/stm32/hardware/stm32_dac_v1.h b/arch/arm/src/common/stm32/hardware/stm32_dac_v1.h similarity index 98% rename from arch/arm/src/stm32/hardware/stm32_dac_v1.h rename to arch/arm/src/common/stm32/hardware/stm32_dac_v1.h index 74742ac2781c6..8e213a40b0588 100644 --- a/arch/arm/src/stm32/hardware/stm32_dac_v1.h +++ b/arch/arm/src/common/stm32/hardware/stm32_dac_v1.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32_dac_v1.h + * arch/arm/src/common/stm32/hardware/stm32_dac_v1.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_DAC_V1_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_DAC_V1_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DAC_V1_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DAC_V1_H /**************************************************************************** * Included Files @@ -312,4 +312,4 @@ #define DAC_SR_DMAUDR1 (1 << 13) /* Bit 13: DAC channel 1 DMA underrun flag */ #define DAC_SR_DMAUDR2 (1 << 29) /* Bit 29: DAC channel 2 DMA underrun flag */ -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_DAC_V1_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DAC_V1_H */ diff --git a/arch/arm/src/common/stm32/hardware/stm32_dac_v1v2.h b/arch/arm/src/common/stm32/hardware/stm32_dac_v1v2.h new file mode 100644 index 0000000000000..9c8587dd4af6b --- /dev/null +++ b/arch/arm/src/common/stm32/hardware/stm32_dac_v1v2.h @@ -0,0 +1,56 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/hardware/stm32_dac_v1v2.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DAC_V1V2_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DAC_V1V2_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "chip.h" + +/* There are 2 main types of DAC IP cores among STM32 chips: + * 1. STM32 DAC IPv1: F1, F2, F3, F4, F7, L1, L4 + * 2. STM32 DAC IPv2: G4 + */ + +#if defined(CONFIG_STM32_HAVE_IP_DAC_M3M4_V1) && \ + defined(CONFIG_STM32_HAVE_IP_DAC_M3M4_V2) +# error Only one STM32 DAC IP version must be selected +#endif + +#if defined(CONFIG_STM32_HAVE_IP_DAC_M3M4_V1) +# include "stm32_dac_v1.h" +#elif defined(CONFIG_STM32_HAVE_IP_DAC_M3M4_V2) +# if defined(CONFIG_STM32_STM32G4XXX) +# include "stm32gxxxxx_dac.h" /* Special case for G4 */ +# else +# error "STM32 DAC device not supported" +# endif +#else +# error "STM32 DAC IP version not specified" +#endif + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DAC_V1V2_H */ diff --git a/arch/arm/src/common/stm32/hardware/stm32_dbgmcu.h b/arch/arm/src/common/stm32/hardware/stm32_dbgmcu.h new file mode 100644 index 0000000000000..23ef2b1fd8d91 --- /dev/null +++ b/arch/arm/src/common/stm32/hardware/stm32_dbgmcu.h @@ -0,0 +1,47 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/hardware/stm32_dbgmcu.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DBGMCU_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DBGMCU_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#if (defined(CONFIG_STM32_HAVE_IP_DBGMCU_M0_V1) + \ + defined(CONFIG_STM32_HAVE_IP_DBGMCU_M3M4_V1) + \ + defined(CONFIG_STM32_HAVE_IP_DBGMCU_M3M4_V2) + \ + defined(CONFIG_STM32_HAVE_IP_DBGMCU_M3M4_V3)) > 1 +# error Only one STM32 DBGMCU IP version must be selected +#endif + +#if defined(CONFIG_STM32_HAVE_IP_DBGMCU_M0_V1) +# include "hardware/stm32_dbgmcu_m0.h" +#elif defined(CONFIG_STM32_HAVE_IP_DBGMCU_M3M4_V1) || \ + defined(CONFIG_STM32_HAVE_IP_DBGMCU_M3M4_V2) || \ + defined(CONFIG_STM32_HAVE_IP_DBGMCU_M3M4_V3) +# include "hardware/stm32_dbgmcu_v1.h" +#else +# error "Unsupported STM32 DBGMCU" +#endif + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DBGMCU_H */ diff --git a/arch/arm/src/common/stm32/hardware/stm32_dbgmcu_m0.h b/arch/arm/src/common/stm32/hardware/stm32_dbgmcu_m0.h new file mode 100644 index 0000000000000..d310e7c1ac7d8 --- /dev/null +++ b/arch/arm/src/common/stm32/hardware/stm32_dbgmcu_m0.h @@ -0,0 +1,80 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/hardware/stm32_dbgmcu_m0.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DBGMCU_M0_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DBGMCU_M0_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include "chip.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Register Offsets *********************************************************/ + +#define STM32_DBGMCU_IDCODE 0x40015800 /* MCU identifier */ +#define STM32_DBGMCU_CR 0x40015804 /* MCU debug */ +#define STM32_DBGMCU_APB1_FZ 0x40015808 /* Debug MCU APB1 freeze register */ +#define STM32_DBGMCU_APB2_FZ 0x4001580c /* Debug MCU APB2 freeze register */ + +/* Register Bitfield Definitions ********************************************/ + +/* MCU identifier */ + +#define DBGMCU_IDCODE_DEVID_SHIFT (0) /* Bits 11-0: Device Identifier */ +#define DBGMCU_IDCODE_DEVID_MASK (0x0fff << DBGMCU_IDCODE_DEVID_SHIFT) +#define DBGMCU_IDCODE_REVID_SHIFT (16) /* Bits 31-16: Revision Identifier */ +#define DBGMCU_IDCODE_REVID_MASK (0xffff << DBGMCU_IDCODE_REVID_SHIFT) + +/* MCU debug */ + +#define DBGMCU_CR_SLEEP (1 << 0) /* Bit 0: Debug Sleep Mode */ +#define DBGMCU_CR_STOP (1 << 1) /* Bit 1: Debug Stop Mode */ +#define DBGMCU_CR_STANDBY (1 << 2) /* Bit 2: Debug Standby mode */ + +/* Debug MCU APB freeze register 1 */ + +#ifdef CONFIG_ARCH_CHIP_STM32C0 +# define DBGMCU_APB1_TIM2STOP (1 << 0) /* Bit 0: TIM2 stopped when core is halted */ +# define DBGMCU_APB1_TIM3STOP (1 << 1) /* Bit 1: TIM3 stopped when core is halted */ +# define DBGMCU_APB1_RTCSTOP (1 << 10) /* Bit 10: RTC stopped when core is halted */ +# define DBGMCU_APB1_WWDGSTOP (1 << 11) /* Bit 11: WWDG stopped when core is halted */ +# define DBGMCU_APB1_IWDGSTOP (1 << 12) /* Bit 12: IWDG stopped when core is halted */ +# define DBGMCU_APB1_I2C1STOP (1 << 21) /* Bit 21: SMBUS timeout mode stopped when Core is halted */ +#endif + +/* Debug MCU APB freeze register 2 */ + +#ifdef CONFIG_ARCH_CHIP_STM32C0 +# define DBGMCU_APB1_TIM1STOP (1 << 11) /* Bit 1: TIM1 stopped when core is halted */ +# define DBGMCU_APB1_TIM14STOP (1 << 15) /* Bit 15: TIM14 stopped when core is halted */ +# define DBGMCU_APB1_TIM15STOP (1 << 16) /* Bit 16: TIM15 stopped when core is halted */ +# define DBGMCU_APB1_TIM16STOP (1 << 17) /* Bit 16: TIM16 stopped when core is halted */ +# define DBGMCU_APB1_TIM17STOP (1 << 18) /* Bit 16: TIM17 stopped when core is halted */ +#endif + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DBGMCU_M0_H */ diff --git a/arch/arm/src/common/stm32/hardware/stm32_dbgmcu_v1.h b/arch/arm/src/common/stm32/hardware/stm32_dbgmcu_v1.h new file mode 100644 index 0000000000000..12628ae6ed6df --- /dev/null +++ b/arch/arm/src/common/stm32/hardware/stm32_dbgmcu_v1.h @@ -0,0 +1,197 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/hardware/stm32_dbgmcu_v1.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DBGMCU_V1_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DBGMCU_V1_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "chip.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Register Addresses *******************************************************/ + +#define STM32_DBGMCU_IDCODE 0xe0042000 /* MCU identifier */ +#define STM32_DBGMCU_CR 0xe0042004 /* MCU debug */ +#ifdef CONFIG_STM32_HAVE_IP_DBGMCU_M3M4_V2 +# define STM32_DBGMCU_APB1_FZ 0xe0042008 /* Debug MCU APB1 freeze register */ +# define STM32_DBGMCU_APB2_FZ 0xe004200c /* Debug MCU APB2 freeze register */ +#endif +#ifdef CONFIG_STM32_HAVE_IP_DBGMCU_M3M4_V3 +# define STM32_DBGMCU_APB1_FZ1 0xe0042008 /* Debug MCU APB1 freeze 1 register */ +# define STM32_DBGMCU_APB1_FZ2 0xe004200c /* Debug MCU APB1 freeze 2 register */ +# define STM32_DBGMCU_APB2_FZ 0xe0042010 /* Debug MCU APB2 freeze register */ +#endif + +/* Register Bitfield Definitions ********************************************/ + +/* MCU identifier */ + +#define DBGMCU_IDCODE_DEVID_SHIFT (0) /* Bits 11-0: Device Identifier */ +#define DBGMCU_IDCODE_DEVID_MASK (0x0fff << DBGMCU_IDCODE_DEVID_SHIFT) +#define DBGMCU_IDCODE_REVID_SHIFT (16) /* Bits 31-16: Revision Identifier */ +#define DBGMCU_IDCODE_REVID_MASK (0xffff << DBGMCU_IDCODE_REVID_SHIFT) + +/* MCU debug */ + +#define DBGMCU_CR_SLEEP (1 << 0) /* Bit 0: Debug Sleep Mode */ +#define DBGMCU_CR_STOP (1 << 1) /* Bit 1: Debug Stop Mode */ +#define DBGMCU_CR_STANDBY (1 << 2) /* Bit 2: Debug Standby mode */ +#define DBGMCU_CR_TRACEIOEN (1 << 5) /* Bit 5: Trace enabled */ + +#define DBGMCU_CR_TRACEMODE_SHIFT (6) /* Bits 7-6: Trace mode pin assignment */ +#define DBGMCU_CR_TRACEMODE_MASK (3 << DBGMCU_CR_TRACEMODE_SHIFT) +# define DBGMCU_CR_ASYNCH (0 << DBGMCU_CR_TRACEMODE_SHIFT) /* Asynchronous Mode */ +# define DBGMCU_CR_SYNCH1 (1 << DBGMCU_CR_TRACEMODE_SHIFT) /* Synchronous Mode, TRACEDATA size=1 */ +# define DBGMCU_CR_SYNCH2 (2 << DBGMCU_CR_TRACEMODE_SHIFT) /* Synchronous Mode, TRACEDATA size=2 */ +# define DBGMCU_CR_SYNCH4 (3 << DBGMCU_CR_TRACEMODE_SHIFT) /* Synchronous Mode, TRACEDATA size=4 */ + +#ifdef CONFIG_STM32_HAVE_IP_DBGMCU_M3M4_V1 +# define DBGMCU_CR_IWDGSTOP (1 << 8) /* Bit 8: Independent Watchdog stopped when core is halted */ +# define DBGMCU_CR_WWDGSTOP (1 << 9) /* Bit 9: Window Watchdog stopped when core is halted */ +# define DBGMCU_CR_TIM1STOP (1 << 10) /* Bit 10: TIM1 stopped when core is halted */ +# define DBGMCU_CR_TIM2STOP (1 << 11) /* Bit 11: TIM2 stopped when core is halted */ +# define DBGMCU_CR_TIM3STOP (1 << 12) /* Bit 12: TIM3 stopped when core is halted */ +# define DBGMCU_CR_TIM4STOP (1 << 13) /* Bit 13: TIM4 stopped when core is halted */ +# define DBGMCU_CR_CAN1STOP (1 << 14) /* Bit 14: CAN1 stopped when core is halted */ +# define DBGMCU_CR_SMBUS1STOP (1 << 15) /* Bit 15: I2C1 SMBUS timeout mode stopped when core is halted */ +# define DBGMCU_CR_SMBUS2STOP (1 << 16) /* Bit 16: I2C2 SMBUS timeout mode stopped when core is halted */ +# define DBGMCU_CR_TIM8STOP (1 << 17) /* Bit 17: TIM8 stopped when core is halted */ +# define DBGMCU_CR_TIM5STOP (1 << 18) /* Bit 18: TIM5 stopped when core is halted */ +# define DBGMCU_CR_TIM6STOP (1 << 19) /* Bit 19: TIM6 stopped when core is halted */ +# define DBGMCU_CR_TIM7STOP (1 << 20) /* Bit 20: TIM7 stopped when core is halted */ +# define DBGMCU_CR_CAN2STOP (1 << 21) /* Bit 21: CAN2 stopped when core is halted */ +#endif /* CONFIG_STM32_HAVE_IP_DBGMCU_M3M4_V1 */ + +#ifdef CONFIG_STM32_HAVE_IP_DBGMCU_M3M4_V2 + +/* Debug MCU APB1 freeze register */ + +#if defined(CONFIG_STM32_HAVE_IP_DBGMCU_M3M4_V2) +# define DBGMCU_APB1_TIM2STOP (1 << 0) /* Bit 0: TIM2 stopped when core is halted */ +# define DBGMCU_APB1_TIM3STOP (1 << 1) /* Bit 1: TIM3 stopped when core is halted */ +# define DBGMCU_APB1_TIM4STOP (1 << 2) /* Bit 2: TIM4 stopped when core is halted */ +# define DBGMCU_APB1_TIM5STOP (1 << 3) /* Bit 3: TIM5 stopped when core is halted */ +# define DBGMCU_APB1_TIM6STOP (1 << 4) /* Bit 4: TIM6 stopped when core is halted */ +# define DBGMCU_APB1_TIM7STOP (1 << 5) /* Bit 5: TIM7 stopped when core is halted */ +# define DBGMCU_APB1_TIM12STOP (1 << 6) /* Bit 6: TIM12 stopped when core is halted */ +# define DBGMCU_APB1_TIM13STOP (1 << 7) /* Bit 7: TIM13 stopped when core is halted */ +# define DBGMCU_APB1_TIM14STOP (1 << 8) /* Bit 7: TIM14 stopped when core is halted */ +# define DBGMCU_APB1_RTCSTOP (1 << 10) /* Bit 10: RTC stopped when Core is halted */ +# define DBGMCU_APB1_WWDGSTOP (1 << 11) /* Bit 11: Window Watchdog stopped when core is halted */ +# define DBGMCU_APB1_IWDGSTOP (1 << 12) /* Bit 12: Independent Watchdog stopped when core is halted */ +# define DBGMCU_APB1_I2C1STOP (1 << 21) /* Bit 21: SMBUS timeout mode stopped when Core is halted */ +# define DBGMCU_APB1_I2C2STOP (1 << 22) /* Bit 22: SMBUS timeout mode stopped when Core is halted */ +# define DBGMCU_APB1_I2C3STOP (1 << 23) /* Bit 23: SMBUS timeout mode stopped when Core is halted */ +# define DBGMCU_APB1_CAN1STOP (1 << 25) /* Bit 25: CAN1 stopped when core is halted */ +# define DBGMCU_APB1_CAN2STOP (1 << 26) /* Bit 26: CAN2 stopped when core is halted */ +#elif defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) || \ + defined(CONFIG_STM32_STM32L15XX) +# define DBGMCU_APB1_TIM2STOP (1 << 0) /* Bit 0: TIM2 stopped when core is halted */ +# define DBGMCU_APB1_TIM3STOP (1 << 1) /* Bit 1: TIM3 stopped when core is halted */ +# define DBGMCU_APB1_TIM4STOP (1 << 2) /* Bit 2: TIM4 stopped when core is halted */ +# define DBGMCU_APB1_TIM6STOP (1 << 4) /* Bit 4: TIM6 stopped when core is halted */ +# define DBGMCU_APB1_TIM7STOP (1 << 5) /* Bit 5: TIM7 stopped when core is halted */ +# define DBGMCU_APB1_RTCSTOP (1 << 10) /* Bit 10: RTC stopped when Core is halted */ +# define DBGMCU_APB1_WWDGSTOP (1 << 11) /* Bit 11: Window Watchdog stopped when core is halted */ +# define DBGMCU_APB1_IWDGSTOP (1 << 12) /* Bit 12: Independent Watchdog stopped when core is halted */ +# define DBGMCU_APB1_I2C1STOP (1 << 21) /* Bit 21: SMBUS timeout mode stopped when Core is halted */ +# define DBGMCU_APB1_I2C2STOP (1 << 22) /* Bit 22: SMBUS timeout mode stopped when Core is halted */ +# if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) +# define DBGMCU_APB1_CAN1STOP (1 << 25) /* Bit 25: CAN1 stopped when core is halted */ +# endif +#endif + +/* Debug MCU APB2 freeze register */ + +#if defined(CONFIG_STM32_HAVE_IP_DBGMCU_M3M4_V2) +# define DBGMCU_APB2_TIM1STOP (1 << 0) /* Bit 0: TIM1 stopped when core is halted */ +# define DBGMCU_APB2_TIM8STOP (1 << 1) /* Bit 1: TIM8 stopped when core is halted */ +# define DBGMCU_APB2_TIM9STOP (1 << 16) /* Bit 16: TIM9 stopped when core is halted */ +# define DBGMCU_APB2_TIM10STOP (1 << 17) /* Bit 17: TIM10 stopped when core is halted */ +# define DBGMCU_APB2_TIM11STOP (1 << 18) /* Bit 18: TIM11 stopped when core is halted */ +#elif defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) +# define DBGMCU_APB2_TIM1STOP (1 << 0) /* Bit 0: TIM1 stopped when core is halted */ +# define DBGMCU_APB2_TIM8STOP (1 << 1) /* Bit 1: TIM8 stopped when core is halted */ +# define DBGMCU_APB2_TIM15STOP (1 << 2) /* Bit 2: TIM15 stopped when core is halted */ +# define DBGMCU_APB2_TIM16STOP (1 << 3) /* Bit 3: TIM16 stopped when core is halted */ +# define DBGMCU_APB2_TIM17STOP (1 << 4) /* Bit 4: TIM17 stopped when core is halted */ +#elif defined(CONFIG_STM32_STM32L15XX) +# define DBGMCU_APB2_TIM9STOP (1 << 2) /* Bit 2: TIM9 stopped when core is halted */ +# define DBGMCU_APB2_TIM10STOP (1 << 3) /* Bit 3: TIM10 stopped when core is halted */ +# define DBGMCU_APB2_TIM11STOP (1 << 4) /* Bit 4: TIM11 stopped when core is halted */ +#endif +#endif /* CONFIG_STM32_HAVE_IP_DBGMCU_M3M4_V2 */ + +#ifdef CONFIG_STM32_HAVE_IP_DBGMCU_M3M4_V3 + +/* Debug MCU APB1 freeze 1 register */ + +# define DBGMCU_APB1FZ1_TIM2STOP (1 << 0) /* Bit 0: TIM2 stopped when core is halted */ +# define DBGMCU_APB1FZ1_TIM3STOP (1 << 1) /* Bit 1: TIM3 stopped when core is halted */ +# define DBGMCU_APB1FZ1_TIM4STOP (1 << 2) /* Bit 2: TIM4 stopped when core is halted */ +# define DBGMCU_APB1FZ1_TIM6STOP (1 << 4) /* Bit 4: TIM6 stopped when core is halted */ +# define DBGMCU_APB1FZ1_TIM7STOP (1 << 5) /* Bit 5: TIM7 stopped when core is halted */ +# define DBGMCU_APB1FZ1_RTCSTOP (1 << 10) /* Bit 10: RTC stopped when Core is halted */ +# define DBGMCU_APB1FZ1_WWDGSTOP (1 << 11) /* Bit 11: Window Watchdog stopped when core is halted */ +# define DBGMCU_APB1FZ1_IWDGSTOP (1 << 12) /* Bit 12: Independent Watchdog stopped when core is halted */ +# define DBGMCU_APB1FZ1_I2C1STOP (1 << 21) /* Bit 21: SMBUS timeout mode stopped when Core is halted */ +# define DBGMCU_APB1FZ1_I2C2STOP (1 << 22) /* Bit 22: SMBUS timeout mode stopped when Core is halted */ +# define DBGMCU_APB1FZ1_I2C3STOP (1 << 30) /* Bit 30: SMBUS timeout mode stopped when Core is halted */ +# define DBGMCU_APB1FZ1_LPTIM1STOP (1 << 31) /* Bit 31: LPTIM1 counter stopped when Core is halted */ + +/* Debug MCU APB1 freeze 2 register */ + +# define DBGMCU_APB1FZ2_I2C4STOP (1 << 1) /* Bit 30: SMBUS timeout mode stopped when Core is halted */ + +/* Debug MCU APB2 freeze register */ + +# define DBGMCU_APB2_TIM1STOP (1 << 11) /* Bit 11: TIM1 stopped when core is halted */ +# define DBGMCU_APB2_TIM8STOP (1 << 13) /* Bit 14: TIM8 stopped when core is halted */ +# define DBGMCU_APB2_TIM15STOP (1 << 16) /* Bit 16: TIM15 stopped when core is halted */ +# define DBGMCU_APB2_TIM16STOP (1 << 17) /* Bit 17: TIM16 stopped when core is halted */ +# define DBGMCU_APB2_TIM17STOP (1 << 18) /* Bit 18: TIM17 stopped when core is halted */ +# define DBGMCU_APB2_TIM20STOP (1 << 20) /* Bit 20: TIM20 stopped when core is halted */ +# define DBGMCU_APB2_HRTIMSTOP (1 << 26) /* Bit 20: HRTIM stopped when core is halted */ + +#endif /* CONFIG_STM32_HAVE_IP_DBGMCU_M3M4_V3 */ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DBGMCU_V1_H */ diff --git a/arch/arm/src/common/stm32/hardware/stm32_dma.h b/arch/arm/src/common/stm32/hardware/stm32_dma.h new file mode 100644 index 0000000000000..ee43743cd57d4 --- /dev/null +++ b/arch/arm/src/common/stm32/hardware/stm32_dma.h @@ -0,0 +1,55 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/hardware/stm32_dma.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DMA_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DMA_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "chip.h" + +/* Include the correct DMA register definitions for + * selected STM32 DMA IP core: + * - STM32 DMA IP version 1 - F0, F1, F3, G4, L0, L1, L4 + * - STM32 DMA IP version 2 - F2, F4, F7, H7 + */ + +#if defined(CONFIG_STM32_HAVE_IP_DMA_V1) && defined(CONFIG_STM32_HAVE_IP_DMA_V2) +# error Only one STM32 DMA IP version must be selected +#endif + +#if defined(CONFIG_STM32_HAVE_IP_DMA_V1_7CH) || \ + defined(CONFIG_STM32_HAVE_IP_DMA_V1_7CH_DMAMUX) || \ + defined(CONFIG_STM32_HAVE_IP_DMA_V1_8CH) || \ + defined(CONFIG_STM32_HAVE_IP_DMA_V1_8CH_DMAMUX) +# include "stm32_dma_v1.h" +#elif defined(CONFIG_STM32_HAVE_IP_DMA_V2_STREAM) +# include "stm32_dma_v2.h" +#else +# error "STM32 DMA IP version not specified" +#endif + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DMA_H */ diff --git a/arch/arm/src/common/stm32/hardware/stm32_dma2d.h b/arch/arm/src/common/stm32/hardware/stm32_dma2d.h new file mode 100644 index 0000000000000..35abefb091516 --- /dev/null +++ b/arch/arm/src/common/stm32/hardware/stm32_dma2d.h @@ -0,0 +1,237 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/hardware/stm32_dma2d.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DMA2D_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DMA2D_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include "hardware/stm32_memorymap.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define STM32_DMA2D_NCLUT 256 /* Number of entries in the CLUT */ + +/* DMA2D Register Offsets ***************************************************/ + +#define STM32_DMA2D_CR_OFFSET 0x0000 /* DMA2D Control Register */ +#define STM32_DMA2D_ISR_OFFSET 0x0004 /* DMA2D Interrupt Status Register */ +#define STM32_DMA2D_IFCR_OFFSET 0x0008 /* DMA2D Interrupt Flag Clear Register */ +#define STM32_DMA2D_FGMAR_OFFSET 0x000c /* DMA2D Foreground Memory Address Register */ +#define STM32_DMA2D_FGOR_OFFSET 0x0010 /* DMA2D Foreground Offset Register */ +#define STM32_DMA2D_BGMAR_OFFSET 0x0014 /* DMA2D Background Memory Address Register */ +#define STM32_DMA2D_BGOR_OFFSET 0x0018 /* DMA2D Background Offset Register */ +#define STM32_DMA2D_FGPFCCR_OFFSET 0x001c /* DMA2D Foreground PFC Control Register */ +#define STM32_DMA2D_FGCOLR_OFFSET 0x0020 /* DMA2D Foreground Color Register */ +#define STM32_DMA2D_BGPFCCR_OFFSET 0x0024 /* DMA2D Background PFC Control Register */ +#define STM32_DMA2D_BGCOLR_OFFSET 0x0028 /* DMA2D Background Color Register */ +#define STM32_DMA2D_FGCMAR_OFFSET 0x002c /* DMA2D Foreground CLUT Memory Address Register */ +#define STM32_DMA2D_BGCMAR_OFFSET 0x0030 /* DMA2D Background CLUT Memory Address Register */ +#define STM32_DMA2D_OPFCCR_OFFSET 0x0034 /* DMA2D Output PFC Control Register */ +#define STM32_DMA2D_OCOLR_OFFSET 0x0038 /* DMA2D Output Color Register */ +#define STM32_DMA2D_OMAR_OFFSET 0x003c /* DMA2D Output Memory Address Register */ +#define STM32_DMA2D_OOR_OFFSET 0x0040 /* DMA2D Output Offset Register */ +#define STM32_DMA2D_NLR_OFFSET 0x0044 /* DMA2D Number Of Line Register */ +#define STM32_DMA2D_LWR_OFFSET 0x0048 /* DMA2D Line Watermark Register */ +#define STM32_DMA2D_AMTCR_OFFSET 0x004c /* DMA2D AHB Master Time Configuration Register */ + +/* DMA2D Register Addresses *************************************************/ + +#define STM32_DMA2D_CR (STM32_DMA2D_BASE + STM32_DMA2D_CR_OFFSET) +#define STM32_DMA2D_ISR (STM32_DMA2D_BASE + STM32_DMA2D_ISR_OFFSET) +#define STM32_DMA2D_IFCR (STM32_DMA2D_BASE + STM32_DMA2D_IFCR_OFFSET) +#define STM32_DMA2D_FGMAR (STM32_DMA2D_BASE + STM32_DMA2D_FGMAR_OFFSET) +#define STM32_DMA2D_FGOR (STM32_DMA2D_BASE + STM32_DMA2D_FGOR_OFFSET) +#define STM32_DMA2D_BGMAR (STM32_DMA2D_BASE + STM32_DMA2D_BGMAR_OFFSET) +#define STM32_DMA2D_BGOR (STM32_DMA2D_BASE + STM32_DMA2D_BGOR_OFFSET) +#define STM32_DMA2D_FGPFCCR (STM32_DMA2D_BASE + STM32_DMA2D_FGPFCCR_OFFSET) +#define STM32_DMA2D_FGCOLR (STM32_DMA2D_BASE + STM32_DMA2D_FGCOLR_OFFSET) +#define STM32_DMA2D_BGPFCCR (STM32_DMA2D_BASE + STM32_DMA2D_BGPFCCR_OFFSET) +#define STM32_DMA2D_BGCOLR (STM32_DMA2D_BASE + STM32_DMA2D_BGCOLR_OFFSET) +#define STM32_DMA2D_FGCMAR (STM32_DMA2D_BASE + STM32_DMA2D_FGCMAR_OFFSET) +#define STM32_DMA2D_BGCMAR (STM32_DMA2D_BASE + STM32_DMA2D_BGCMAR_OFFSET) +#define STM32_DMA2D_OPFCCR (STM32_DMA2D_BASE + STM32_DMA2D_OPFCCR_OFFSET) +#define STM32_DMA2D_OCOLR (STM32_DMA2D_BASE + STM32_DMA2D_OCOLR_OFFSET) +#define STM32_DMA2D_OMAR (STM32_DMA2D_BASE + STM32_DMA2D_OMAR_OFFSET) +#define STM32_DMA2D_OOR (STM32_DMA2D_BASE + STM32_DMA2D_OOR_OFFSET) +#define STM32_DMA2D_NLR (STM32_DMA2D_BASE + STM32_DMA2D_NLR_OFFSET) +#define STM32_DMA2D_LWR (STM32_DMA2D_BASE + STM32_DMA2D_LWR_OFFSET) + +/* DMA2D Register Bit Definitions *******************************************/ + +/* DMA2D Control Register */ + +#define DMA2D_CR_START (1 << 0) /* Start Bit */ +#define DMA2D_CR_SUSP (1 << 1) /* Suspend Bit */ +#define DMA2D_CR_ABORT (1 << 2) /* Abort Bit */ +#define DMA2D_CR_TEIE (1 << 8) /* Transfer Error Interrupt Enable Bit */ +#define DMA2D_CR_TCIE (1 << 9) /* Transfer Complete Interrupt Enable Bit */ +#define DMA2D_CR_TWIE (1 << 10) /* Transfer Watermark Interrupt Enable Bit */ +#define DMA2D_CR_CAEIE (1 << 11) /* CLUT Access Error Interrupt Enable Bit */ +#define DMA2D_CR_CTCIE (1 << 12) /* CLUT Transfer Complete Interrupt Enable Bit */ +#define DMA2D_CR_CEIE (1 << 13) /* Configuration Error Interrupt Enable Bit */ +#define DMA2D_CR_MODE_SHIFT (16) /* Bits 16-17 DMA2D mode Bits */ +#define DMA2D_CR_MODE_MASK (3 << DMA2D_CR_MODE_SHIFT) +#define DMA2D_CR_MODE(n) ((uint32_t)(n) << DMA2D_CR_MODE_SHIFT) + +/* DMA2D Interrupt Status Register */ + +#define DMA2D_ISR_TEIF (1 << 0) /* Transfer error interrupt flag */ +#define DMA2D_ISR_TCIF (1 << 1) /* Transfer Complete Interrupt flag */ +#define DMA2D_ISR_TWIF (1 << 2) /* Transfer Watermark Interrupt flag */ +#define DMA2D_ISR_CAEIF (1 << 3) /* CLUT Access Error Interrupt flag */ +#define DMA2D_ISR_CTCIF (1 << 4) /* CLUT Transfer Complete Interrupt flag */ +#define DMA2D_ISR_CEIF (1 << 5) /* Configuration Error Interrupt flag */ + +/* DMA2D Interrupt Flag Clear Register */ + +#define DMA2D_IFCR_CTEIF (1 << 0) /* Clear Transfer Interrupt Flag */ +#define DMA2D_IFCR_CTCIF (1 << 1) /* Clear Transfer Complete Interrupt Flag */ +#define DMA2D_IFCR_CTWIF (1 << 2) /* Clear Transfer Watermark Interrupt Flag */ +#define DMA2D_IFCR_CAECIF (1 << 3) /* Clear CLUT Access Error Interrupt Flag */ +#define DMA2D_IFCR_CCTCIF (1 << 4) /* Clear CLUT Transfer Complete Interrupt Flag */ +#define DMA2D_IFCR_CCEIF (1 << 5) /* Clear Configuration Error Interrupt Flag */ + +/* DMA2D Foreground Memory Access Register */ + +/* DMA2D Background Memory Access Register */ + +/* DMA2D Foreground/Background Offset Register */ + +#define DMA2D_XGOR_SHIFT (0) /* Bits 0-13 Line Offset */ +#define DMA2D_XGOR_MASK (0x3fff << DMA2D_XGOR_SHIFT) +#define DMA2D_XGOR(n) ((uint32_t)(n) << DMA2D_XGOR_SHIFT) + +/* DMA2D Foreground/Background PFC Control Register */ + +#define DMA2D_XGPFCCR_CM_SHIFT (0) /* Bits 0-3 Color Mode */ +#define DMA2D_XGPFCCR_CM_MASK (0xf << DMA2D_XGPFCCR_CM_SHIFT) +#define DMA2D_XGPFCCR_CM(n) ((uint32_t)(n) << DMA2D_XGPFCCR_CM_SHIFT) +#define DMA2D_XGPFCCR_CCM (1 << 4) /* CLUT Color Mode */ +#define DMA2D_XGPFCCR_START (1 << 5) /* Start */ +#define DMA2D_XGPFCCR_CS_SHIFT (8) /* Bits 8-15 CLUT Size */ +#define DMA2D_XGPFCCR_CS_MASK (0xff << DMA2D_XGPFCCR_CS_SHIFT) +#define DMA2D_XGPFCCR_CS(n) ((uint32_t)(n) << DMA2D_XGPFCCR_CS_SHIFT) +#define DMA2D_XGPFCCR_AM_SHIFT (16) /* Bits 16-17 Alpha Mode */ +#define DMA2D_XGPFCCR_AM_MASK (3 << DMA2D_XGPFCCR_AM_SHIFT) +#define DMA2D_XGPFCCR_AM(n) ((uint32_t)(n) << DMA2D_XGPFCCR_AM_SHIFT) +#define DMA2D_XGPFCCR_ALPHA_SHIFT (24) /* Bits 24-31 Alpha Value */ +#define DMA2D_XGPFCCR_ALPHA_MASK (0xff << DMA2D_XGPFCCR_ALPHA_SHIFT) +#define DMA2D_XGPFCCR_ALPHA(n) ((uint32_t)(n) << DMA2D_XGPFCCR_ALPHA_SHIFT) + +/* DMA2D PFC alpha mode */ + +#define STM32_DMA2D_PFCCR_AM_NONE 0 +#define STM32_DMA2D_PFCCR_AM_CONST 1 +#define STM32_DMA2D_PFCCR_AM_PIXEL 2 + +/* DMA2D Foreground/Background Color Register */ + +#define DMA2D_XGCOLR_BLUE_SHIFT (0) /* Bits 0-7 Blue Value */ +#define DMA2D_XGCOLR_BLUE_MASK (0xff << DMA2D_XGCOLR_BLUE_SHIFT) +#define DMA2D_XGCOLR_BLUE(n) ((uint32_t)(n) << DMA2D_XGCOLR_BLUE_SHIFT) +#define DMA2D_XGCOLR_GREEN_SHIFT (8) /* Bits 8-15 Green Value */ +#define DMA2D_XGCOLR_GREEN_MASK (0xff << DMA2D_XGCOLR_GREEN_SHIFT) +#define DMA2D_XGCOLR_GREEN(n) ((uint32_t)(n) << DMA2D_XGCOLR_GREEN_SHIFT) +#define DMA2D_XGCOLR_RED_SHIFT (16) /* Bits 16-23 Red Value */ +#define DMA2D_XGCOLR_RED_MASK (0xff << DMA2D_XGCOLR_RED_SHIFT) +#define DMA2D_XGCOLR_RED(n) ((uint32_t)(n) << DMA2D_XGCOLR_RED_SHIFT) + +/* DMA2D Foreground CLUT Memory Address Register */ + +/* DMA2D Background CLUT Memory Address Register */ + +/* DMA2D Output PFC Control Register */ + +#define DMA2D_OPFCCR_CM_SHIFT (0) /* Bits 0-2 Color Mode */ +#define DMA2D_OPFCCR_CM_MASK (7 << DMA2D_OPFCCR_CM_SHIFT) +#define DMA2D_OPFCCR_CM(n) ((uint32_t)(n) << DMA2D_OPFCCR_CM_SHIFT) + +/* DMA2D PFC Pixel Format */ + +#define DMA2D_PF_ARGB8888 0 +#define DMA2D_PF_RGB888 1 +#define DMA2D_PF_RGB565 2 +#define DMA2D_PF_ARGB1555 3 +#define DMA2D_PF_ARGB14444 4 +#define DMA2D_PF_L8 5 +#define DMA2D_PF_AL44 6 +#define DMA2D_PF_AL88 7 +#define DMA2D_PF_L4 8 +#define DMA2D_PF_A8 9 +#define DMA2D_PF_A4 10 + +/* DMA2D Output Color Register */ + +#define DMA2D_OCOLR_BLUE_SHIFT (0) /* Bits 0-7 Blue Value */ +#define DMA2D_OCOLR_BLUE_MASK (0xff << DMA2D_OCOLR_BLUE_SHIFT) +#define DMA2D_OCOLR_BLUE(n) ((uint32_t)(n) << DMA2D_OCOLR_BLUE_SHIFT) +#define DMA2D_OCOLR_GREEN_SHIFT (8) /* Bits 8-15 Green Value */ +#define DMA2D_OCOLR_GREEN_MASK (0xff << DMA2D_OCOLR_GREEN_SHIFT) +#define DMA2D_OCOLR_GREEN(n) ((uint32_t)(n) << DMA2D_OCOLR_GREEN_SHIFT) +#define DMA2D_OCOLR_RED_SHIFT (16) /* Bits 16-23 Red Value */ +#define DMA2D_OCOLR_RED_MASK (0xff << DMA2D_OCOLR_RED_SHIFT) +#define DMA2D_OCOLR_RED(n) ((uint32_t)(n) << DMA2D_OCOLR_RED_SHIFT) +#define DMA2D_OCOLR_ALPHA_SHIFT (24) /* Bits 24-31 Alpha Value */ +#define DMA2D_OCOLR_ALPHA_MASK (0xff << DMA2D_OCOLR_ALPHA_SHIFT) +#define DMA2D_OCOLR_ALPHA(n) ((uint32_t)(n) << DMA2D_OCOLR_ALPHA_SHIFT) + +/* DMA2D Output Memory Address Register */ + +/* DMA2D Output Offset Register */ + +#define DMA2D_OOR_LO_SHIFT (0) /* Bits 0-13 Line Offset */ +#define DMA2D_OOR_LO_MASK (0x3fff << DMA2D_OOR_LO_SHIFT) +#define DMA2D_OOR_LO(n) ((uint32_t)(n) << DMA2D_OOR_LO_SHIFT) + +/* DMA2D Number Of Line Register */ + +#define DMA2D_NLR_NL_SHIFT (0) /* Bits 0-15 Number Of Lines */ +#define DMA2D_NLR_NL_MASK (0xffff << DMA2D_NLR_NL_SHIFT) +#define DMA2D_NLR_NL(n) ((uint32_t)(n) << DMA2D_NLR_NL_SHIFT) +#define DMA2D_NLR_PL_SHIFT (16) /* Bits 16-29 Pixel per Lines */ +#define DMA2D_NLR_PL_MASK (0x3fff << DMA2D_NLR_PL_SHIFT) +#define DMA2D_NLR_PL(n) ((uint32_t)(n) << DMA2D_NLR_PL_SHIFT) + +/* DMA2D Line Watermark Register */ + +#define DMA2D_LWR_LW_SHIFT (0) /* Bits 0-15 Line Watermark */ +#define DMA2D_LWR_LW_MASK (0xffff << DMA2D_LWR_LW_SHIFT) +#define DMA2D_LWR_LW(n) ((uint32_t)(n) << DMA2D_LWR_LW_SHIFT) + +/* DMA2D AHB Master Timer Configuration Register */ + +#define DMA2D_AMTCR_EN (1 << 0) /* Enable */ +#define DMA2D_AMTCR_DT_SHIFT (0) /* Bits 8-15 Dead Time */ +#define DMA2D_AMTCR_DT_MASK (0xff << DMA2D_AMTCR_DT_SHIFT) +#define DMA2D_AMTCR_DT(n) ((uint32_t)(n) << DMA2D_AMTCR_DT_SHIFT) + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DMA2D_H */ diff --git a/arch/arm/src/common/stm32/hardware/stm32_dma_v1.h b/arch/arm/src/common/stm32/hardware/stm32_dma_v1.h new file mode 100644 index 0000000000000..1ddb8dcc46eef --- /dev/null +++ b/arch/arm/src/common/stm32/hardware/stm32_dma_v1.h @@ -0,0 +1,40 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/hardware/stm32_dma_v1.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DMA_V1_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DMA_V1_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#if defined(CONFIG_STM32_HAVE_IP_DMA_V1_7CH) || \ + defined(CONFIG_STM32_HAVE_IP_DMA_V1_7CH_DMAMUX) +# include "hardware/stm32_dma_v1_7ch.h" +#elif defined(CONFIG_STM32_HAVE_IP_DMA_V1_8CH) || \ + defined(CONFIG_STM32_HAVE_IP_DMA_V1_8CH_DMAMUX) +# include "hardware/stm32_dma_v1_8ch.h" +#else +# error "Unsupported STM32 DMA v1" +#endif + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DMA_V1_H */ diff --git a/arch/arm/src/common/stm32/hardware/stm32_dma_v1_7ch.h b/arch/arm/src/common/stm32/hardware/stm32_dma_v1_7ch.h new file mode 100644 index 0000000000000..6b3860db90359 --- /dev/null +++ b/arch/arm/src/common/stm32/hardware/stm32_dma_v1_7ch.h @@ -0,0 +1,548 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/hardware/stm32_dma_v1_7ch.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DMA_V1_7CH_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DMA_V1_7CH_H + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* This is implementation for + * STM32 DMA IP version 1 - F0, F1, F3, L0, L1, L4 + */ + +#define HAVE_IP_DMA_V1 1 +#undef HAVE_IP_DMA_V2 + +/* F0, L0, L4 have additional CSELR register */ + +#if defined(CONFIG_ARCH_CHIP_STM32L0) +# define DMA_HAVE_CSELR 1 +#endif + +/* 2 DMA controllers */ + +#define DMA1 (0) +#define DMA2 (1) + +/* 12 Channels Total: 7 DMA1 Channels(1-7) and 5 DMA2 channels (1-5) */ + +#define DMA_CHAN1 (0) +#define DMA_CHAN2 (1) +#define DMA_CHAN3 (2) +#define DMA_CHAN4 (3) +#define DMA_CHAN5 (4) +#define DMA_CHAN6 (5) +#define DMA_CHAN7 (6) + +/* Register Offsets *********************************************************/ + +#define STM32_DMA_ISR_OFFSET 0x0000 /* DMA interrupt status register */ +#define STM32_DMA_IFCR_OFFSET 0x0004 /* DMA interrupt flag clear register */ + +#define STM32_DMACHAN_OFFSET(n) (0x0014 * (n)) +#define STM32_DMACHAN1_OFFSET 0x0000 +#define STM32_DMACHAN2_OFFSET 0x0014 +#define STM32_DMACHAN3_OFFSET 0x0028 +#define STM32_DMACHAN4_OFFSET 0x003c +#define STM32_DMACHAN5_OFFSET 0x0050 +#define STM32_DMACHAN6_OFFSET 0x0064 +#define STM32_DMACHAN7_OFFSET 0x0078 + +#define STM32_DMACHAN_CCR_OFFSET 0x0008 /* DMA channel configuration register */ +#define STM32_DMACHAN_CNDTR_OFFSET 0x000c /* DMA channel number of data register */ +#define STM32_DMACHAN_CPAR_OFFSET 0x0010 /* DMA channel peripheral address register */ +#define STM32_DMACHAN_CMAR_OFFSET 0x0014 /* DMA channel 1 memory address register */ + +#define STM32_DMA_CCR_OFFSET(n) (STM32_DMACHAN_CCR_OFFSET + STM32_DMACHAN_OFFSET(n)) +#define STM32_DMA_CNDTR_OFFSET(n) (STM32_DMACHAN_CNDTR_OFFSET + STM32_DMACHAN_OFFSET(n)) +#define STM32_DMA_CPAR_OFFSET(n) (STM32_DMACHAN_CPAR_OFFSET + STM32_DMACHAN_OFFSET(n)) +#define STM32_DMA_CMAR_OFFSET(n) (STM32_DMACHAN_CMAR_OFFSET + STM32_DMACHAN_OFFSET(n)) + +#define STM32_DMA_CCR1_OFFSET 0x0008 /* DMA channel 1 configuration register */ +#define STM32_DMA_CCR2_OFFSET 0x001c /* DMA channel 2 configuration register */ +#define STM32_DMA_CCR3_OFFSET 0x0030 /* DMA channel 3 configuration register */ +#define STM32_DMA_CCR4_OFFSET 0x0044 /* DMA channel 4 configuration register */ +#define STM32_DMA_CCR5_OFFSET 0x0058 /* DMA channel 5 configuration register */ +#define STM32_DMA_CCR6_OFFSET 0x006c /* DMA channel 6 configuration register */ +#define STM32_DMA_CCR7_OFFSET 0x0080 /* DMA channel 7 configuration register */ + +#define STM32_DMA_CNDTR1_OFFSET 0x000c /* DMA channel 1 number of data register */ +#define STM32_DMA_CNDTR2_OFFSET 0x0020 /* DMA channel 2 number of data register */ +#define STM32_DMA_CNDTR3_OFFSET 0x0034 /* DMA channel 3 number of data register */ +#define STM32_DMA_CNDTR4_OFFSET 0x0048 /* DMA channel 4 number of data register */ +#define STM32_DMA_CNDTR5_OFFSET 0x005c /* DMA channel 5 number of data register */ +#define STM32_DMA_CNDTR6_OFFSET 0x0070 /* DMA channel 6 number of data register */ +#define STM32_DMA_CNDTR7_OFFSET 0x0084 /* DMA channel 7 number of data register */ + +#define STM32_DMA_CPAR1_OFFSET 0x0010 /* DMA channel 1 peripheral address register */ +#define STM32_DMA_CPAR2_OFFSET 0x0024 /* DMA channel 2 peripheral address register */ +#define STM32_DMA_CPAR3_OFFSET 0x0038 /* DMA channel 3 peripheral address register */ +#define STM32_DMA_CPAR4_OFFSET 0x004c /* DMA channel 4 peripheral address register */ +#define STM32_DMA_CPAR5_OFFSET 0x0060 /* DMA channel 5 peripheral address register */ +#define STM32_DMA_CPAR6_OFFSET 0x0074 /* DMA channel 6 peripheral address register */ +#define STM32_DMA_CPAR7_OFFSET 0x0088 /* DMA channel 7 peripheral address register */ + +#define STM32_DMA_CMAR1_OFFSET 0x0014 /* DMA channel 1 memory address register */ +#define STM32_DMA_CMAR2_OFFSET 0x0028 /* DMA channel 2 memory address register */ +#define STM32_DMA_CMAR3_OFFSET 0x003c /* DMA channel 3 memory address register */ +#define STM32_DMA_CMAR4_OFFSET 0x0050 /* DMA channel 4 memory address register */ +#define STM32_DMA_CMAR5_OFFSET 0x0064 /* DMA channel 5 memory address register */ +#define STM32_DMA_CMAR6_OFFSET 0x0078 /* DMA channel 6 memory address register */ +#define STM32_DMA_CMAR7_OFFSET 0x008c /* DMA channel 7 memory address register */ + +#ifdef DMA_HAVE_CSELR +# define STM32_DMA_CSELR_OFFSET 0x00a8 /* DMA channel selection register */ +#endif + +/* Register Addresses *******************************************************/ + +#define STM32_DMA1_ISRC (STM32_DMA1_BASE + STM32_DMA_ISR_OFFSET) +#define STM32_DMA1_IFCR (STM32_DMA1_BASE + STM32_DMA_IFCR_OFFSET) + +#define STM32_DMA1_CCR(n) (STM32_DMA1_BASE + STM32_DMA_CCR_OFFSET(n)) +#define STM32_DMA1_CCR1 (STM32_DMA1_BASE + STM32_DMA_CCR1_OFFSET) +#define STM32_DMA1_CCR2 (STM32_DMA1_BASE + STM32_DMA_CCR2_OFFSET) +#define STM32_DMA1_CCR3 (STM32_DMA1_BASE + STM32_DMA_CCR3_OFFSET) +#define STM32_DMA1_CCR4 (STM32_DMA1_BASE + STM32_DMA_CCR4_OFFSET) +#define STM32_DMA1_CCR5 (STM32_DMA1_BASE + STM32_DMA_CCR5_OFFSET) +#define STM32_DMA1_CCR6 (STM32_DMA1_BASE + STM32_DMA_CCR6_OFFSET) +#define STM32_DMA1_CCR7 (STM32_DMA1_BASE + STM32_DMA_CCR7_OFFSET) + +#define STM32_DMA1_CNDTR(n) (STM32_DMA1_BASE + STM32_DMA_CNDTR_OFFSET(n)) +#define STM32_DMA1_CNDTR1 (STM32_DMA1_BASE + STM32_DMA_CNDTR1_OFFSET) +#define STM32_DMA1_CNDTR2 (STM32_DMA1_BASE + STM32_DMA_CNDTR2_OFFSET) +#define STM32_DMA1_CNDTR3 (STM32_DMA1_BASE + STM32_DMA_CNDTR3_OFFSET) +#define STM32_DMA1_CNDTR4 (STM32_DMA1_BASE + STM32_DMA_CNDTR4_OFFSET) +#define STM32_DMA1_CNDTR5 (STM32_DMA1_BASE + STM32_DMA_CNDTR5_OFFSET) +#define STM32_DMA1_CNDTR6 (STM32_DMA1_BASE + STM32_DMA_CNDTR6_OFFSET) +#define STM32_DMA1_CNDTR7 (STM32_DMA1_BASE + STM32_DMA_CNDTR7_OFFSET) + +#define STM32_DMA1_CPAR(n) (STM32_DMA1_BASE + STM32_DMA_CPAR_OFFSET(n)) +#define STM32_DMA1_CPAR1 (STM32_DMA1_BASE + STM32_DMA_CPAR1_OFFSET) +#define STM32_DMA1_CPAR2 (STM32_DMA1_BASE + STM32_DMA_CPAR2_OFFSET) +#define STM32_DMA1_CPAR3 (STM32_DMA1_BASE + STM32_DMA_CPAR3_OFFSET) +#define STM32_DMA1_CPAR4 (STM32_DMA1_BASE + STM32_DMA_CPAR4_OFFSET) +#define STM32_DMA1_CPAR5 (STM32_DMA1_BASE + STM32_DMA_CPAR5_OFFSET) +#define STM32_DMA1_CPAR6 (STM32_DMA1_BASE + STM32_DMA_CPAR6_OFFSET) +#define STM32_DMA1_CPAR7 (STM32_DMA1_BASE + STM32_DMA_CPAR7_OFFSET) + +#define STM32_DMA1_CMAR(n) (STM32_DMA1_BASE + STM32_DMA_CMAR_OFFSET(n)) +#define STM32_DMA1_CMAR1 (STM32_DMA1_BASE + STM32_DMA_CMAR1_OFFSET) +#define STM32_DMA1_CMAR2 (STM32_DMA1_BASE + STM32_DMA_CMAR2_OFFSET) +#define STM32_DMA1_CMAR3 (STM32_DMA1_BASE + STM32_DMA_CMAR3_OFFSET) +#define STM32_DMA1_CMAR4 (STM32_DMA1_BASE + STM32_DMA_CMAR4_OFFSET) +#define STM32_DMA1_CMAR5 (STM32_DMA1_BASE + STM32_DMA_CMAR5_OFFSET) +#define STM32_DMA1_CMAR6 (STM32_DMA1_BASE + STM32_DMA_CMAR6_OFFSET) +#define STM32_DMA1_CMAR7 (STM32_DMA1_BASE + STM32_DMA_CMAR7_OFFSET) + +#define STM32_DMA2_ISRC (STM32_DMA2_BASE + STM32_DMA_ISR_OFFSET) +#define STM32_DMA2_IFCR (STM32_DMA2_BASE + STM32_DMA_IFCR_OFFSET) + +#define STM32_DMA2_CCR(n) (STM32_DMA2_BASE + STM32_DMA_CCR_OFFSET(n)) +#define STM32_DMA2_CCR1 (STM32_DMA2_BASE + STM32_DMA_CCR1_OFFSET) +#define STM32_DMA2_CCR2 (STM32_DMA2_BASE + STM32_DMA_CCR2_OFFSET) +#define STM32_DMA2_CCR3 (STM32_DMA2_BASE + STM32_DMA_CCR3_OFFSET) +#define STM32_DMA2_CCR4 (STM32_DMA2_BASE + STM32_DMA_CCR4_OFFSET) +#define STM32_DMA2_CCR5 (STM32_DMA2_BASE + STM32_DMA_CCR5_OFFSET) + +#define STM32_DMA2_CNDTR(n) (STM32_DMA2_BASE + STM32_DMA_CNDTR_OFFSET(n)) +#define STM32_DMA2_CNDTR1 (STM32_DMA2_BASE + STM32_DMA_CNDTR1_OFFSET) +#define STM32_DMA2_CNDTR2 (STM32_DMA2_BASE + STM32_DMA_CNDTR2_OFFSET) +#define STM32_DMA2_CNDTR3 (STM32_DMA2_BASE + STM32_DMA_CNDTR3_OFFSET) +#define STM32_DMA2_CNDTR4 (STM32_DMA2_BASE + STM32_DMA_CNDTR4_OFFSET) +#define STM32_DMA2_CNDTR5 (STM32_DMA2_BASE + STM32_DMA_CNDTR5_OFFSET) + +#define STM32_DMA2_CPAR(n) (STM32_DMA2_BASE + STM32_DMA_CPAR_OFFSET(n)) +#define STM32_DMA2_CPAR1 (STM32_DMA2_BASE + STM32_DMA_CPAR1_OFFSET) +#define STM32_DMA2_CPAR2 (STM32_DMA2_BASE + STM32_DMA_CPAR2_OFFSET) +#define STM32_DMA2_CPAR3 (STM32_DMA2_BASE + STM32_DMA_CPAR3_OFFSET) +#define STM32_DMA2_CPAR4 (STM32_DMA2_BASE + STM32_DMA_CPAR4_OFFSET) +#define STM32_DMA2_CPAR5 (STM32_DMA2_BASE + STM32_DMA_CPAR5_OFFSET) + +#define STM32_DMA2_CMAR(n) (STM32_DMA2_BASE + STM32_DMA_CMAR_OFFSET(n)) +#define STM32_DMA2_CMAR1 (STM32_DMA2_BASE + STM32_DMA_CMAR1_OFFSET) +#define STM32_DMA2_CMAR2 (STM32_DMA2_BASE + STM32_DMA_CMAR2_OFFSET) +#define STM32_DMA2_CMAR3 (STM32_DMA2_BASE + STM32_DMA_CMAR3_OFFSET) +#define STM32_DMA2_CMAR4 (STM32_DMA2_BASE + STM32_DMA_CMAR4_OFFSET) +#define STM32_DMA2_CMAR5 (STM32_DMA2_BASE + STM32_DMA_CMAR5_OFFSET) + +#ifdef DMA_HAVE_CSELR +# define STM32_DMA_CSELR (STM32_DMA2_BASE + STM32_DMA_CSELR_OFFSET) +#endif + +/* Register Bitfield Definitions ********************************************/ + +#define DMA_CHAN_SHIFT(n) ((n) << 2) +#define DMA_CHAN_MASK 0x0f +#define DMA_CHAN_GIF_BIT (1 << 0) /* Bit 0: Channel Global interrupt flag */ +#define DMA_CHAN_TCIF_BIT (1 << 1) /* Bit 1: Channel Transfer Complete flag */ +#define DMA_CHAN_HTIF_BIT (1 << 2) /* Bit 2: Channel Half Transfer flag */ +#define DMA_CHAN_TEIF_BIT (1 << 3) /* Bit 3: Channel Transfer Error flag */ + +/* DMA interrupt status register */ + +#define DMA_ISR_CHAN_SHIFT(n) DMA_CHAN_SHIFT(n) +#define DMA_ISR_CHAN_MASK(n) (DMA_CHAN_MASK << DMA_ISR_CHAN_SHIFT(n)) +#define DMA_ISR_CHAN1_SHIFT (0) /* Bits 3-0: DMA Channel 1 interrupt status */ +#define DMA_ISR_CHAN1_MASK (DMA_CHAN_MASK << DMA_ISR_CHAN1_SHIFT) +#define DMA_ISR_CHAN2_SHIFT (4) /* Bits 7-4: DMA Channel 2 interrupt status */ +#define DMA_ISR_CHAN2_MASK (DMA_CHAN_MASK << DMA_ISR_CHAN2_SHIFT) +#define DMA_ISR_CHAN3_SHIFT (8) /* Bits 11-8: DMA Channel 3 interrupt status */ +#define DMA_ISR_CHAN3_MASK (DMA_CHAN_MASK << DMA_ISR_CHAN3_SHIFT) +#define DMA_ISR_CHAN4_SHIFT (12) /* Bits 15-12: DMA Channel 4 interrupt status */ +#define DMA_ISR_CHAN4_MASK (DMA_CHAN_MASK << DMA_ISR_CHAN4_SHIFT) +#define DMA_ISR_CHAN5_SHIFT (16) /* Bits 19-16: DMA Channel 5 interrupt status */ +#define DMA_ISR_CHAN5_MASK (DMA_CHAN_MASK << DMA_ISR_CHAN5_SHIFT) +#define DMA_ISR_CHAN6_SHIFT (20) /* Bits 23-20: DMA Channel 6 interrupt status */ +#define DMA_ISR_CHAN6_MASK (DMA_CHAN_MASK << DMA_ISR_CHAN6_SHIFT) +#define DMA_ISR_CHAN7_SHIFT (24) /* Bits 27-24: DMA Channel 7 interrupt status */ +#define DMA_ISR_CHAN7_MASK (DMA_CHAN_MASK << DMA_ISR_CHAN7_SHIFT) + +#define DMA_ISR_GIF(n) (DMA_CHAN_GIF_BIT << DMA_ISR_CHAN_SHIFT(n)) +#define DMA_ISR_TCIF(n) (DMA_CHAN_TCIF_BIT << DMA_ISR_CHAN_SHIFT(n)) +#define DMA_ISR_HTIF(n) (DMA_CHAN_HTIF_BIT << DMA_ISR_CHAN_SHIFT(n)) +#define DMA_ISR_TEIF(n) (DMA_CHAN_TEIF_BIT << DMA_ISR_CHAN_SHIFT(n)) + +/* DMA interrupt flag clear register */ + +#define DMA_IFCR_CHAN_SHIFT(n) DMA_CHAN_SHIFT(n) +#define DMA_IFCR_CHAN_MASK(n) (DMA_CHAN_MASK << DMA_IFCR_CHAN_SHIFT(n)) +#define DMA_IFCR_CHAN1_SHIFT (0) /* Bits 3-0: DMA Channel 1 interrupt flag clear */ +#define DMA_IFCR_CHAN1_MASK (DMA_CHAN_MASK << DMA_IFCR_CHAN1_SHIFT) +#define DMA_IFCR_CHAN2_SHIFT (4) /* Bits 7-4: DMA Channel 2 interrupt flag clear */ +#define DMA_IFCR_CHAN2_MASK (DMA_CHAN_MASK << DMA_IFCR_CHAN2_SHIFT) +#define DMA_IFCR_CHAN3_SHIFT (8) /* Bits 11-8: DMA Channel 3 interrupt flag clear */ +#define DMA_IFCR_CHAN3_MASK (DMA_CHAN_MASK << DMA_IFCR_CHAN3_SHIFT) +#define DMA_IFCR_CHAN4_SHIFT (12) /* Bits 15-12: DMA Channel 4 interrupt flag clear */ +#define DMA_IFCR_CHAN4_MASK (DMA_CHAN_MASK << DMA_IFCR_CHAN4_SHIFT) +#define DMA_IFCR_CHAN5_SHIFT (16) /* Bits 19-16: DMA Channel 5 interrupt flag clear */ +#define DMA_IFCR_CHAN5_MASK (DMA_CHAN_MASK << DMA_IFCR_CHAN5_SHIFT) +#define DMA_IFCR_CHAN6_SHIFT (20) /* Bits 23-20: DMA Channel 6 interrupt flag clear */ +#define DMA_IFCR_CHAN6_MASK (DMA_CHAN_MASK << DMA_IFCR_CHAN6_SHIFT) +#define DMA_IFCR_CHAN7_SHIFT (24) /* Bits 27-24: DMA Channel 7 interrupt flag clear */ +#define DMA_IFCR_CHAN7_MASK (DMA_CHAN_MASK << DMA_IFCR_CHAN7_SHIFT) +#define DMA_IFCR_ALLCHANNELS (0x0fffffff) + +#define DMA_IFCR_CGIF(n) (DMA_CHAN_GIF_BIT << DMA_IFCR_CHAN_SHIFT(n)) +#define DMA_IFCR_CTCIF(n) (DMA_CHAN_TCIF_BIT << DMA_IFCR_CHAN_SHIFT(n)) +#define DMA_IFCR_CHTIF(n) (DMA_CHAN_HTIF_BIT << DMA_IFCR_CHAN_SHIFT(n)) +#define DMA_IFCR_CTEIF(n) (DMA_CHAN_TEIF_BIT << DMA_IFCR_CHAN_SHIFT(n)) + +/* DMA channel configuration register */ + +#define DMA_CCR_EN (1 << 0) /* Bit 0: Channel enable */ +#define DMA_CCR_TCIE (1 << 1) /* Bit 1: Transfer complete interrupt enable */ +#define DMA_CCR_HTIE (1 << 2) /* Bit 2: Half Transfer interrupt enable */ +#define DMA_CCR_TEIE (1 << 3) /* Bit 3: Transfer error interrupt enable */ +#define DMA_CCR_DIR (1 << 4) /* Bit 4: Data transfer direction */ +#define DMA_CCR_CIRC (1 << 5) /* Bit 5: Circular mode */ +#define DMA_CCR_PINC (1 << 6) /* Bit 6: Peripheral increment mode */ +#define DMA_CCR_MINC (1 << 7) /* Bit 7: Memory increment mode */ +#define DMA_CCR_PSIZE_SHIFT (8) /* Bits 8-9: Peripheral size */ +#define DMA_CCR_PSIZE_MASK (3 << DMA_CCR_PSIZE_SHIFT) +# define DMA_CCR_PSIZE_8BITS (0 << DMA_CCR_PSIZE_SHIFT) /* 00: 8-bits */ +# define DMA_CCR_PSIZE_16BITS (1 << DMA_CCR_PSIZE_SHIFT) /* 01: 16-bits */ +# define DMA_CCR_PSIZE_32BITS (2 << DMA_CCR_PSIZE_SHIFT) /* 10: 32-bits */ + +#define DMA_CCR_MSIZE_SHIFT (10) /* Bits 10-11: Memory size */ +#define DMA_CCR_MSIZE_MASK (3 << DMA_CCR_MSIZE_SHIFT) +# define DMA_CCR_MSIZE_8BITS (0 << DMA_CCR_MSIZE_SHIFT) /* 00: 8-bits */ +# define DMA_CCR_MSIZE_16BITS (1 << DMA_CCR_MSIZE_SHIFT) /* 01: 16-bits */ +# define DMA_CCR_MSIZE_32BITS (2 << DMA_CCR_MSIZE_SHIFT) /* 10: 32-bits */ + +#define DMA_CCR_PL_SHIFT (12) /* Bits 12-13: Channel Priority level */ +#define DMA_CCR_PL_MASK (3 << DMA_CCR_PL_SHIFT) +# define DMA_CCR_PRILO (0 << DMA_CCR_PL_SHIFT) /* 00: Low */ +# define DMA_CCR_PRIMED (1 << DMA_CCR_PL_SHIFT) /* 01: Medium */ +# define DMA_CCR_PRIHI (2 << DMA_CCR_PL_SHIFT) /* 10: High */ +# define DMA_CCR_PRIVERYHI (3 << DMA_CCR_PL_SHIFT) /* 11: Very high */ + +#define DMA_CCR_MEM2MEM (1 << 14) /* Bit 14: Memory to memory mode */ + +#define DMA_CCR_ALLINTS (DMA_CCR_TEIE|DMA_CCR_HTIE|DMA_CCR_TCIE) + +/* DMA channel number of data register */ + +#define DMA_CNDTR_NDT_SHIFT (0) /* Bits 15-0: Number of data to Transfer */ +#define DMA_CNDTR_NDT_MASK (0xffff << DMA_CNDTR_NDT_SHIFT) + +/* DMA Channel mapping. Each DMA channel has a mapping to several possible + * sources/sinks of data. The requests from peripherals assigned to a + * channel are simply OR'ed together before entering the DMA block. This + * means that only one request on a given channel can be enabled at once. + * + * Alternative DMA channel selections are provided with a numeric suffix like + * _1, _2, etc. Drivers, however, will use the pin selection without the + * numeric suffix. Additional definitions are required in the board.h file. + */ + +#define STM32_DMA1_CHAN1 (0) +#define STM32_DMA1_CHAN2 (1) +#define STM32_DMA1_CHAN3 (2) +#define STM32_DMA1_CHAN4 (3) +#define STM32_DMA1_CHAN5 (4) +#define STM32_DMA1_CHAN6 (5) +#define STM32_DMA1_CHAN7 (6) + +#define STM32_DMA2_CHAN1 (7) +#define STM32_DMA2_CHAN2 (8) +#define STM32_DMA2_CHAN3 (9) +#define STM32_DMA2_CHAN4 (10) +#define STM32_DMA2_CHAN5 (11) + +#ifdef DMA_HAVE_CSELR +# define DMACHAN_SETTING(chan, sel) ((((sel) & 0xff) << 8) | ((chan) & 0xff)) +# define DMACHAN_SETTING_CHANNEL_MASK 0x00ff +# define DMACHAN_SETTING_CHANNEL_SHIFT (0) +# define DMACHAN_SETTING_FUNCTION_MASK 0xff00 +# define DMACHAN_SETTING_FUNCTION_SHIFT (8) +#endif + +#if defined(CONFIG_ARCH_CHIP_STM32F0) +/* REVISIT: based on STM32L4 DMA Header */ + +/* ADC */ + +# define DMACHAN_ADC1_1 DMACHAN_SETTING(STM32_DMA1_CHAN1, 0) +# define DMACHAN_ADC1_2 DMACHAN_SETTING(STM32_DMA2_CHAN3, 0) + +# define DMACHAN_ADC2_1 DMACHAN_SETTING(STM32_DMA1_CHAN1, 0) +# define DMACHAN_ADC2_2 DMACHAN_SETTING(STM32_DMA2_CHAN4, 0) + +# define DMACHAN_ADC3_1 DMACHAN_SETTING(STM32_DMA1_CHAN1, 0) +# define DMACHAN_ADC3_2 DMACHAN_SETTING(STM32_DMA2_CHAN5, 0) + +/* AES */ + +# define DMACHAN_AES_IN_1 DMACHAN_SETTING(STM32_DMA2_CHAN1, 6) +# define DMACHAN_AES_IN_2 DMACHAN_SETTING(STM32_DMA2_CHAN5, 6) +# define DMACHAN_AES_OUT_1 DMACHAN_SETTING(STM32_DMA2_CHAN2, 6) +# define DMACHAN_AES_OUT_2 DMACHAN_SETTING(STM32_DMA2_CHAN3, 6) + +/* DAC */ + +# define DMACHAN_DAC1_1 DMACHAN_SETTING(STM32_DMA1_CHAN3, 6) +# define DMACHAN_DAC1_2 DMACHAN_SETTING(STM32_DMA1_CHAN4, 5) +# define DMACHAN_DAC1_3 DMACHAN_SETTING(STM32_DMA2_CHAN4, 3) + +# define DMACHAN_DAC2 DMACHAN_SETTING(STM32_DMA2_CHAN5, 3) + +/* I2C */ + +# define DMACHAN_I2C1_RX_1 DMACHAN_SETTING(STM32_DMA1_CHAN7, 3) +# define DMACHAN_I2C1_RX_2 DMACHAN_SETTING(STM32_DMA2_CHAN6, 5) +# define DMACHAN_I2C1_TX_1 DMACHAN_SETTING(STM32_DMA1_CHAN6, 3) +# define DMACHAN_I2C1_TX_2 DMACHAN_SETTING(STM32_DMA2_CHAN7, 5) + +# define DMACHAN_I2C2_RX DMACHAN_SETTING(STM32_DMA1_CHAN5, 3) +# define DMACHAN_I2C2_TX DMACHAN_SETTING(STM32_DMA1_CHAN4, 3) + +# define DMACHAN_I2C3_RX DMACHAN_SETTING(STM32_DMA1_CHAN3, 2) +# define DMACHAN_I2C3_TX DMACHAN_SETTING(STM32_DMA1_CHAN2, 3) + +/* QUADSPI */ + +# define DMACHAN_QUADSPI_1 DMACHAN_SETTING(STM32_DMA1_CHAN5, 5) +# define DMACHAN_QUADSPI_2 DMACHAN_SETTING(STM32_DMA2_CHAN7, 3) + +/* SPI */ + +# define DMACHAN_SPI1_RX_1 DMACHAN_SETTING(STM32_DMA1_CHAN2, 1) +# define DMACHAN_SPI1_RX_2 DMACHAN_SETTING(STM32_DMA2_CHAN3, 4) +# define DMACHAN_SPI1_TX_1 DMACHAN_SETTING(STM32_DMA1_CHAN3, 0) +# define DMACHAN_SPI1_TX_2 DMACHAN_SETTING(STM32_DMA2_CHAN4, 4) + +# define DMACHAN_SPI2_RX DMACHAN_SETTING(STM32_DMA1_CHAN4, 1) +# define DMACHAN_SPI2_TX DMACHAN_SETTING(STM32_DMA1_CHAN5, 1) + +# define DMACHAN_SPI3_RX DMACHAN_SETTING(STM32_DMA2_CHAN1, 3) +# define DMACHAN_SPI3_TX DMACHAN_SETTING(STM32_DMA2_CHAN2, 3) + +/* TIM */ + +# define DMACHAN_TIM1_CH1 DMACHAN_SETTING(STM32_DMA1_CHAN2, 7) +# define DMACHAN_TIM1_CH2 DMACHAN_SETTING(STM32_DMA1_CHAN3, 7) +# define DMACHAN_TIM1_CH3 DMACHAN_SETTING(STM32_DMA1_CHAN7, 7) +# define DMACHAN_TIM1_CH4 DMACHAN_SETTING(STM32_DMA1_CHAN4, 7) +# define DMACHAN_TIM1_COM DMACHAN_SETTING(STM32_DMA1_CHAN4, 7) +# define DMACHAN_TIM1_TRIG DMACHAN_SETTING(STM32_DMA1_CHAN4, 7) +# define DMACHAN_TIM1_UP DMACHAN_SETTING(STM32_DMA1_CHAN6, 7) + +# define DMACHAN_TIM2_CH1 DMACHAN_SETTING(STM32_DMA1_CHAN5, 4) +# define DMACHAN_TIM2_CH2 DMACHAN_SETTING(STM32_DMA1_CHAN7, 4) +# define DMACHAN_TIM2_CH3 DMACHAN_SETTING(STM32_DMA1_CHAN1, 4) +# define DMACHAN_TIM2_CH4 DMACHAN_SETTING(STM32_DMA1_CHAN7, 4) +# define DMACHAN_TIM2_UP DMACHAN_SETTING(STM32_DMA1_CHAN2, 4) + +# define DMACHAN_TIM3_CH1 DMACHAN_SETTING(STM32_DMA1_CHAN6, 5) +# define DMACHAN_TIM3_CH3 DMACHAN_SETTING(STM32_DMA1_CHAN2, 5) +# define DMACHAN_TIM3_CH4 DMACHAN_SETTING(STM32_DMA1_CHAN3, 5) +# define DMACHAN_TIM3_TRIG DMACHAN_SETTING(STM32_DMA1_CHAN6, 5) +# define DMACHAN_TIM3_UP DMACHAN_SETTING(STM32_DMA1_CHAN3, 5) + +# define DMACHAN_TIM4_CH1 DMACHAN_SETTING(STM32_DMA1_CHAN1, 6) +# define DMACHAN_TIM4_CH2 DMACHAN_SETTING(STM32_DMA1_CHAN4, 6) +# define DMACHAN_TIM4_CH3 DMACHAN_SETTING(STM32_DMA1_CHAN5, 6) +# define DMACHAN_TIM4_UP DMACHAN_SETTING(STM32_DMA1_CHAN7, 6) + +# define DMACHAN_TIM5_CH1 DMACHAN_SETTING(STM32_DMA2_CHAN5, 5) +# define DMACHAN_TIM5_CH2 DMACHAN_SETTING(STM32_DMA2_CHAN4, 5) +# define DMACHAN_TIM5_CH3 DMACHAN_SETTING(STM32_DMA2_CHAN2, 5) +# define DMACHAN_TIM5_CH4 DMACHAN_SETTING(STM32_DMA2_CHAN1, 5) +# define DMACHAN_TIM5_COM DMACHAN_SETTING(STM32_DMA2_CHAN1, 5) +# define DMACHAN_TIM5_TRIG DMACHAN_SETTING(STM32_DMA2_CHAN1, 5) +# define DMACHAN_TIM5_UP DMACHAN_SETTING(STM32_DMA2_CHAN2, 5) + +# define DMACHAN_TIM6_UP_1 DMACHAN_SETTING(STM32_DMA1_CHAN3, 6) +# define DMACHAN_TIM6_UP_2 DMACHAN_SETTING(STM32_DMA2_CHAN4, 3) + +# define DMACHAN_TIM7_UP_1 DMACHAN_SETTING(STM32_DMA1_CHAN4, 5) +# define DMACHAN_TIM7_UP_2 DMACHAN_SETTING(STM32_DMA2_CHAN5, 3) + +# define DMACHAN_TIM8_CH1 DMACHAN_SETTING(STM32_DMA2_CHAN6, 7) +# define DMACHAN_TIM8_CH2 DMACHAN_SETTING(STM32_DMA2_CHAN7, 7) +# define DMACHAN_TIM8_CH3 DMACHAN_SETTING(STM32_DMA2_CHAN1, 7) +# define DMACHAN_TIM8_CH4 DMACHAN_SETTING(STM32_DMA2_CHAN2, 7) +# define DMACHAN_TIM8_COM DMACHAN_SETTING(STM32_DMA2_CHAN2, 7) +# define DMACHAN_TIM8_TRIG DMACHAN_SETTING(STM32_DMA2_CHAN2, 7) +# define DMACHAN_TIM8_UP DMACHAN_SETTING(STM32_DMA2_CHAN1, 7) + +# define DMACHAN_TIM15_CH1 DMACHAN_SETTING(STM32_DMA1_CHAN5, 7) +# define DMACHAN_TIM15_COM DMACHAN_SETTING(STM32_DMA1_CHAN5, 7) +# define DMACHAN_TIM15_TRIG DMACHAN_SETTING(STM32_DMA1_CHAN5, 7) +# define DMACHAN_TIM15_UP DMACHAN_SETTING(STM32_DMA1_CHAN5, 7) + +# define DMACHAN_TIM16_CH1_1 DMACHAN_SETTING(STM32_DMA1_CHAN3, 4) +# define DMACHAN_TIM16_CH1_2 DMACHAN_SETTING(STM32_DMA1_CHAN6, 4) +# define DMACHAN_TIM16_UP_1 DMACHAN_SETTING(STM32_DMA1_CHAN3, 4) +# define DMACHAN_TIM16_UP_2 DMACHAN_SETTING(STM32_DMA1_CHAN6, 4) + +# define DMACHAN_TIM17_CH1_1 DMACHAN_SETTING(STM32_DMA1_CHAN1, 5) +# define DMACHAN_TIM17_CH1_2 DMACHAN_SETTING(STM32_DMA1_CHAN7, 5) +# define DMACHAN_TIM17_UP_1 DMACHAN_SETTING(STM32_DMA1_CHAN1, 5) +# define DMACHAN_TIM17_UP_2 DMACHAN_SETTING(STM32_DMA1_CHAN7, 5) + +/* USARTs */ + +# define DMACHAN_USART1_RX_1 DMACHAN_SETTING(STM32_DMA1_CHAN5, 2) +# define DMACHAN_USART1_RX_2 DMACHAN_SETTING(STM32_DMA2_CHAN7, 2) +# define DMACHAN_USART1_TX_1 DMACHAN_SETTING(STM32_DMA1_CHAN4, 2) +# define DMACHAN_USART1_TX_2 DMACHAN_SETTING(STM32_DMA2_CHAN6, 2) + +# define DMACHAN_USART2_RX DMACHAN_SETTING(STM32_DMA1_CHAN6, 2) +# define DMACHAN_USART2_TX DMACHAN_SETTING(STM32_DMA1_CHAN7, 2) + +# define DMACHAN_USART3_RX DMACHAN_SETTING(STM32_DMA1_CHAN3, 1) +# define DMACHAN_USART3_TX DMACHAN_SETTING(STM32_DMA1_CHAN2, 2) + +# define DMACHAN_USART4_RX DMACHAN_SETTING(STM32_DMA2_CHAN5, 2) +# define DMACHAN_USART4_TX DMACHAN_SETTING(STM32_DMA2_CHAN3, 2) + +# define DMACHAN_USART5_RX DMACHAN_SETTING(STM32_DMA2_CHAN2, 2) +# define DMACHAN_USART5_TX DMACHAN_SETTING(STM32_DMA2_CHAN1, 2) + +#elif defined(CONFIG_ARCH_CHIP_STM32L0) + +/* ADC */ + +# define DMACHAN_ADC1_1 DMACHAN_SETTING(STM32_DMA1_CHAN1, 0) +# define DMACHAN_ADC1_2 DMACHAN_SETTING(STM32_DMA1_CHAN2, 0) + +/* AES */ + +# define DMACHAN_AES_IN_1 DMACHAN_SETTING(STM32_DMA1_CHAN1, 11) +# define DMACHAN_AES_IN_2 DMACHAN_SETTING(STM32_DMA1_CHAN5, 11) +# define DMACHAN_AES_OUT_1 DMACHAN_SETTING(STM32_DMA1_CHAN2, 11) +# define DMACHAN_AES_OUT_2 DMACHAN_SETTING(STM32_DMA1_CHAN3, 11) + +/* DAC */ + +# define DMACHAN_DAC1CH1 DMACHAN_SETTING(STM32_DMA1_CHAN2, 9) +# define DMACHAN_DAC1CH2 DMACHAN_SETTING(STM32_DMA1_CHAN4, 15) + +/* I2C */ + +# define DMACHAN_I2C1_TX_1 DMACHAN_SETTING(STM32_DMA1_CHAN2, 6) +# define DMACHAN_I2C1_TX_2 DMACHAN_SETTING(STM32_DMA1_CHAN6, 6) +# define DMACHAN_I2C1_RX_1 DMACHAN_SETTING(STM32_DMA1_CHAN3, 6) +# define DMACHAN_I2C1_RX_2 DMACHAN_SETTING(STM32_DMA1_CHAN7, 6) +# define DMACHAN_I2C2_TX DMACHAN_SETTING(STM32_DMA1_CHAN4, 7) +# define DMACHAN_I2C2_RX DMACHAN_SETTING(STM32_DMA1_CHAN7, 7) +# define DMACHAN_I2C3_TX_1 DMACHAN_SETTING(STM32_DMA1_CHAN2, 14) +# define DMACHAN_I2C3_TX_2 DMACHAN_SETTING(STM32_DMA1_CHAN4, 14) +# define DMACHAN_I2C3_RX_1 DMACHAN_SETTING(STM32_DMA1_CHAN3, 14) +# define DMACHAN_I2C3_RX_2 DMACHAN_SETTING(STM32_DMA1_CHAN5, 14) + +/* SPI */ + +# define DMACHAN_SPI1_RX DMACHAN_SETTING(STM32_DMA1_CHAN2, 1) +# define DMACHAN_SPI1_TX DMACHAN_SETTING(STM32_DMA1_CHAN3, 1) +# define DMACHAN_SPI2_RX_1 DMACHAN_SETTING(STM32_DMA1_CHAN4, 2) +# define DMACHAN_SPI2_RX_2 DMACHAN_SETTING(STM32_DMA1_CHAN6, 2) +# define DMACHAN_SPI2_TX_1 DMACHAN_SETTING(STM32_DMA1_CHAN5, 2) +# define DMACHAN_SPI2_TX_2 DMACHAN_SETTING(STM32_DMA1_CHAN7, 2) + +/* TIM */ + +# define DMACHAN_TIM2_CH1 DMACHAN_SETTING(STM32_DMA1_CHAN5, 8) +# define DMACHAN_TIM2_CH2_1 DMACHAN_SETTING(STM32_DMA1_CHAN3, 8) +# define DMACHAN_TIM2_CH2_2 DMACHAN_SETTING(STM32_DMA1_CHAN7, 8) +# define DMACHAN_TIM2_CH3 DMACHAN_SETTING(STM32_DMA1_CHAN1, 8) +# define DMACHAN_TIM2_CH4_1 DMACHAN_SETTING(STM32_DMA1_CHAN4, 8) +# define DMACHAN_TIM2_CH4_2 DMACHAN_SETTING(STM32_DMA1_CHAN7, 8) +# define DMACHAN_TIM2_UP DMACHAN_SETTING(STM32_DMA1_CHAN2, 8) +# define DMACHAN_TIM6_UP DMACHAN_SETTING(STM32_DMA1_CHAN2, 9) +# define DMACHAN_TIM7_UP DMACHAN_SETTING(STM32_DMA1_CHAN4, 15) + +/* USART */ + +# define DMACHAN_USART1_TX_1 DMACHAN_SETTING(STM32_DMA1_CHAN2, 3) +# define DMACHAN_USART1_TX_2 DMACHAN_SETTING(STM32_DMA1_CHAN4, 3) +# define DMACHAN_USART1_RX_1 DMACHAN_SETTING(STM32_DMA1_CHAN3, 3) +# define DMACHAN_USART1_RX_2 DMACHAN_SETTING(STM32_DMA1_CHAN5, 3) +# define DMACHAN_USART2_TX_1 DMACHAN_SETTING(STM32_DMA1_CHAN4, 4) +# define DMACHAN_USART2_TX_2 DMACHAN_SETTING(STM32_DMA1_CHAN7, 4) +# define DMACHAN_USART2_RX_1 DMACHAN_SETTING(STM32_DMA1_CHAN5, 4) +# define DMACHAN_USART2_RX_2 DMACHAN_SETTING(STM32_DMA1_CHAN6, 4) +# define DMACHAN_LPUART1_TX_1 DMACHAN_SETTING(STM32_DMA1_CHAN2, 5) +# define DMACHAN_LPUART1_TX_2 DMACHAN_SETTING(STM32_DMA1_CHAN7, 5) +# define DMACHAN_LPUART1_RX_1 DMACHAN_SETTING(STM32_DMA1_CHAN3, 5) +# define DMACHAN_LPUART1_RX_2 DMACHAN_SETTING(STM32_DMA1_CHAN6, 5) +# define DMACHAN_USART4_RX_1 DMACHAN_SETTING(STM32_DMA1_CHAN2, 12) +# define DMACHAN_USART4_RX_2 DMACHAN_SETTING(STM32_DMA1_CHAN6, 12) +# define DMACHAN_USART4_TX_1 DMACHAN_SETTING(STM32_DMA1_CHAN7, 12) +# define DMACHAN_USART4_TX_2 DMACHAN_SETTING(STM32_DMA1_CHAN3, 12) +# define DMACHAN_USART5_RX_1 DMACHAN_SETTING(STM32_DMA1_CHAN2, 13) +# define DMACHAN_USART5_RX_2 DMACHAN_SETTING(STM32_DMA1_CHAN6, 13) +# define DMACHAN_USART5_TX_1 DMACHAN_SETTING(STM32_DMA1_CHAN7, 13) +# define DMACHAN_USART5_TX_2 DMACHAN_SETTING(STM32_DMA1_CHAN3, 13) + +#elif defined(CONFIG_ARCH_CHIP_STM32G0) || defined(CONFIG_ARCH_CHIP_STM32C0) +/* This family uses a DMAMUX */ + +#else +# error "Unknown DMA channel assignments" +#endif + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DMA_V1_7CH_H */ diff --git a/arch/arm/src/common/stm32/hardware/stm32_dma_v1_8ch.h b/arch/arm/src/common/stm32/hardware/stm32_dma_v1_8ch.h new file mode 100644 index 0000000000000..4d4cb3ed4e6a2 --- /dev/null +++ b/arch/arm/src/common/stm32/hardware/stm32_dma_v1_8ch.h @@ -0,0 +1,773 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/hardware/stm32_dma_v1_8ch.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DMA_V1_8CH_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DMA_V1_8CH_H + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* This is implementation for STM32 DMA IP + * version 1 - F0, F1, F3, G4, L0, L1, L4 + */ + +#define HAVE_IP_DMA_V1 1 +#undef HAVE_IP_DMA_V2 + +/* F0, L0, L4 have additional CSELR register */ + +#undef DMA_HAVE_CSELR + +/* 2 DMA controllers */ + +#define DMA1 (0) +#define DMA2 (1) + +/* These definitions apply to multiple STM32 families. + * + * The STM32 F1 and F3 families have 12 channels total: + * 7 DMA1 channels(1-7) and 5 DMA2 channels (1-5). + * + * The STM32 G4 family has 16 channels total: + * 8 DMA1 channels(1-8) and 8 DMA2 channels (1-8). + */ + +#define DMA_CHAN1 (0) +#define DMA_CHAN2 (1) +#define DMA_CHAN3 (2) +#define DMA_CHAN4 (3) +#define DMA_CHAN5 (4) +#define DMA_CHAN6 (5) +#define DMA_CHAN7 (6) +#define DMA_CHAN8 (7) + +/* Register Offsets *********************************************************/ + +#define STM32_DMA_ISR_OFFSET 0x0000 /* DMA interrupt status register */ +#define STM32_DMA_IFCR_OFFSET 0x0004 /* DMA interrupt flag clear register */ + +#define STM32_DMACHAN_OFFSET(n) (0x0014*(n)) +#define STM32_DMACHAN1_OFFSET 0x0000 +#define STM32_DMACHAN2_OFFSET 0x0014 +#define STM32_DMACHAN3_OFFSET 0x0028 +#define STM32_DMACHAN4_OFFSET 0x003c +#define STM32_DMACHAN5_OFFSET 0x0050 +#define STM32_DMACHAN6_OFFSET 0x0064 +#define STM32_DMACHAN7_OFFSET 0x0078 +#define STM32_DMACHAN8_OFFSET 0x008c + +#define STM32_DMACHAN_CCR_OFFSET 0x0008 /* DMA channel configuration register */ +#define STM32_DMACHAN_CNDTR_OFFSET 0x000c /* DMA channel number of data register */ +#define STM32_DMACHAN_CPAR_OFFSET 0x0010 /* DMA channel peripheral address register */ +#define STM32_DMACHAN_CMAR_OFFSET 0x0014 /* DMA channel 1 memory address register */ + +#define STM32_DMA_CCR_OFFSET(n) (STM32_DMACHAN_CCR_OFFSET+STM32_DMACHAN_OFFSET(n)) +#define STM32_DMA_CNDTR_OFFSET(n) (STM32_DMACHAN_CNDTR_OFFSET+STM32_DMACHAN_OFFSET(n)) +#define STM32_DMA_CPAR_OFFSET(n) (STM32_DMACHAN_CPAR_OFFSET+STM32_DMACHAN_OFFSET(n)) +#define STM32_DMA_CMAR_OFFSET(n) (STM32_DMACHAN_CMAR_OFFSET+STM32_DMACHAN_OFFSET(n)) + +#define STM32_DMA_CCR1_OFFSET 0x0008 /* DMA channel 1 configuration register */ +#define STM32_DMA_CCR2_OFFSET 0x001c /* DMA channel 2 configuration register */ +#define STM32_DMA_CCR3_OFFSET 0x0030 /* DMA channel 3 configuration register */ +#define STM32_DMA_CCR4_OFFSET 0x0044 /* DMA channel 4 configuration register */ +#define STM32_DMA_CCR5_OFFSET 0x0058 /* DMA channel 5 configuration register */ +#define STM32_DMA_CCR6_OFFSET 0x006c /* DMA channel 6 configuration register */ +#define STM32_DMA_CCR7_OFFSET 0x0080 /* DMA channel 7 configuration register */ +#define STM32_DMA_CCR8_OFFSET 0x0094 /* DMA channel 8 configuration register */ + +#define STM32_DMA_CNDTR1_OFFSET 0x000c /* DMA channel 1 number of data register */ +#define STM32_DMA_CNDTR2_OFFSET 0x0020 /* DMA channel 2 number of data register */ +#define STM32_DMA_CNDTR3_OFFSET 0x0034 /* DMA channel 3 number of data register */ +#define STM32_DMA_CNDTR4_OFFSET 0x0048 /* DMA channel 4 number of data register */ +#define STM32_DMA_CNDTR5_OFFSET 0x005c /* DMA channel 5 number of data register */ +#define STM32_DMA_CNDTR6_OFFSET 0x0070 /* DMA channel 6 number of data register */ +#define STM32_DMA_CNDTR7_OFFSET 0x0084 /* DMA channel 7 number of data register */ +#define STM32_DMA_CNDTR8_OFFSET 0x0098 /* DMA channel 8 number of data register */ + +#define STM32_DMA_CPAR1_OFFSET 0x0010 /* DMA channel 1 peripheral address register */ +#define STM32_DMA_CPAR2_OFFSET 0x0024 /* DMA channel 2 peripheral address register */ +#define STM32_DMA_CPAR3_OFFSET 0x0038 /* DMA channel 3 peripheral address register */ +#define STM32_DMA_CPAR4_OFFSET 0x004c /* DMA channel 4 peripheral address register */ +#define STM32_DMA_CPAR5_OFFSET 0x0060 /* DMA channel 5 peripheral address register */ +#define STM32_DMA_CPAR6_OFFSET 0x0074 /* DMA channel 6 peripheral address register */ +#define STM32_DMA_CPAR7_OFFSET 0x0088 /* DMA channel 7 peripheral address register */ +#define STM32_DMA_CPAR8_OFFSET 0x009c /* DMA channel 8 peripheral address register */ + +#define STM32_DMA_CMAR1_OFFSET 0x0014 /* DMA channel 1 memory address register */ +#define STM32_DMA_CMAR2_OFFSET 0x0028 /* DMA channel 2 memory address register */ +#define STM32_DMA_CMAR3_OFFSET 0x003c /* DMA channel 3 memory address register */ +#define STM32_DMA_CMAR4_OFFSET 0x0050 /* DMA channel 4 memory address register */ +#define STM32_DMA_CMAR5_OFFSET 0x0064 /* DMA channel 5 memory address register */ +#define STM32_DMA_CMAR6_OFFSET 0x0078 /* DMA channel 6 memory address register */ +#define STM32_DMA_CMAR7_OFFSET 0x008c /* DMA channel 7 memory address register */ +#define STM32_DMA_CMAR8_OFFSET 0x00a0 /* DMA channel 8 memory address register */ + +#ifdef DMA_HAVE_CSELR +# define STM32_DMA_CSELR_OFFSET 0x00a8 /* DMA channel selection register */ +#endif + +/* Register Addresses *******************************************************/ + +#define STM32_DMA1_ISRC (STM32_DMA1_BASE+STM32_DMA_ISR_OFFSET) +#define STM32_DMA1_IFCR (STM32_DMA1_BASE+STM32_DMA_IFCR_OFFSET) + +#define STM32_DMA1_CCR(n) (STM32_DMA1_BASE+STM32_DMA_CCR_OFFSET(n)) +#define STM32_DMA1_CCR1 (STM32_DMA1_BASE+STM32_DMA_CCR1_OFFSET) +#define STM32_DMA1_CCR2 (STM32_DMA1_BASE+STM32_DMA_CCR2_OFFSET) +#define STM32_DMA1_CCR3 (STM32_DMA1_BASE+STM32_DMA_CCR3_OFFSET) +#define STM32_DMA1_CCR4 (STM32_DMA1_BASE+STM32_DMA_CCR4_OFFSET) +#define STM32_DMA1_CCR5 (STM32_DMA1_BASE+STM32_DMA_CCR5_OFFSET) +#define STM32_DMA1_CCR6 (STM32_DMA1_BASE+STM32_DMA_CCR6_OFFSET) +#define STM32_DMA1_CCR7 (STM32_DMA1_BASE+STM32_DMA_CCR7_OFFSET) +#if defined(CONFIG_STM32_DMA1_HAVE_CHAN8) +# define STM32_DMA1_CCR8 (STM32_DMA1_BASE+STM32_DMA_CCR8_OFFSET) +#endif + +#define STM32_DMA1_CNDTR(n) (STM32_DMA1_BASE+STM32_DMA_CNDTR_OFFSET(n)) +#define STM32_DMA1_CNDTR1 (STM32_DMA1_BASE+STM32_DMA_CNDTR1_OFFSET) +#define STM32_DMA1_CNDTR2 (STM32_DMA1_BASE+STM32_DMA_CNDTR2_OFFSET) +#define STM32_DMA1_CNDTR3 (STM32_DMA1_BASE+STM32_DMA_CNDTR3_OFFSET) +#define STM32_DMA1_CNDTR4 (STM32_DMA1_BASE+STM32_DMA_CNDTR4_OFFSET) +#define STM32_DMA1_CNDTR5 (STM32_DMA1_BASE+STM32_DMA_CNDTR5_OFFSET) +#define STM32_DMA1_CNDTR6 (STM32_DMA1_BASE+STM32_DMA_CNDTR6_OFFSET) +#define STM32_DMA1_CNDTR7 (STM32_DMA1_BASE+STM32_DMA_CNDTR7_OFFSET) +#if defined(CONFIG_STM32_DMA1_HAVE_CHAN8) +# define STM32_DMA1_CNDTR8 (STM32_DMA1_BASE+STM32_DMA_CNDTR8_OFFSET) +#endif + +#define STM32_DMA1_CPAR(n) (STM32_DMA1_BASE+STM32_DMA_CPAR_OFFSET(n)) +#define STM32_DMA1_CPAR1 (STM32_DMA1_BASE+STM32_DMA_CPAR1_OFFSET) +#define STM32_DMA1_CPAR2 (STM32_DMA1_BASE+STM32_DMA_CPAR2_OFFSET) +#define STM32_DMA1_CPAR3 (STM32_DMA1_BASE+STM32_DMA_CPAR3_OFFSET) +#define STM32_DMA1_CPAR4 (STM32_DMA1_BASE+STM32_DMA_CPAR4_OFFSET) +#define STM32_DMA1_CPAR5 (STM32_DMA1_BASE+STM32_DMA_CPAR5_OFFSET) +#define STM32_DMA1_CPAR6 (STM32_DMA1_BASE+STM32_DMA_CPAR6_OFFSET) +#define STM32_DMA1_CPAR7 (STM32_DMA1_BASE+STM32_DMA_CPAR7_OFFSET) +#if defined(CONFIG_STM32_DMA1_HAVE_CHAN8) +# define STM32_DMA1_CPAR8 (STM32_DMA1_BASE+STM32_DMA_CPAR8_OFFSET) +#endif + +#define STM32_DMA1_CMAR(n) (STM32_DMA1_BASE+STM32_DMA_CMAR_OFFSET(n)) +#define STM32_DMA1_CMAR1 (STM32_DMA1_BASE+STM32_DMA_CMAR1_OFFSET) +#define STM32_DMA1_CMAR2 (STM32_DMA1_BASE+STM32_DMA_CMAR2_OFFSET) +#define STM32_DMA1_CMAR3 (STM32_DMA1_BASE+STM32_DMA_CMAR3_OFFSET) +#define STM32_DMA1_CMAR4 (STM32_DMA1_BASE+STM32_DMA_CMAR4_OFFSET) +#define STM32_DMA1_CMAR5 (STM32_DMA1_BASE+STM32_DMA_CMAR5_OFFSET) +#define STM32_DMA1_CMAR6 (STM32_DMA1_BASE+STM32_DMA_CMAR6_OFFSET) +#define STM32_DMA1_CMAR7 (STM32_DMA1_BASE+STM32_DMA_CMAR7_OFFSET) +#if defined(CONFIG_STM32_DMA1_HAVE_CHAN8) +# define STM32_DMA1_CMAR8 (STM32_DMA1_BASE+STM32_DMA_CMAR8_OFFSET) +#endif + +#define STM32_DMA2_ISRC (STM32_DMA2_BASE+STM32_DMA_ISR_OFFSET) +#define STM32_DMA2_IFCR (STM32_DMA2_BASE+STM32_DMA_IFCR_OFFSET) + +#define STM32_DMA2_CCR(n) (STM32_DMA2_BASE+STM32_DMA_CCR_OFFSET(n)) +#define STM32_DMA2_CCR1 (STM32_DMA2_BASE+STM32_DMA_CCR1_OFFSET) +#define STM32_DMA2_CCR2 (STM32_DMA2_BASE+STM32_DMA_CCR2_OFFSET) +#define STM32_DMA2_CCR3 (STM32_DMA2_BASE+STM32_DMA_CCR3_OFFSET) +#define STM32_DMA2_CCR4 (STM32_DMA2_BASE+STM32_DMA_CCR4_OFFSET) +#define STM32_DMA2_CCR5 (STM32_DMA2_BASE+STM32_DMA_CCR5_OFFSET) +#if defined(CONFIG_STM32_DMA2_HAVE_CHAN678) +# define STM32_DMA2_CCR6 (STM32_DMA2_BASE+STM32_DMA_CCR6_OFFSET) +# define STM32_DMA2_CCR7 (STM32_DMA2_BASE+STM32_DMA_CCR7_OFFSET) +# define STM32_DMA2_CCR8 (STM32_DMA2_BASE+STM32_DMA_CCR8_OFFSET) +#endif + +#define STM32_DMA2_CNDTR(n) (STM32_DMA2_BASE+STM32_DMA_CNDTR_OFFSET(n)) +#define STM32_DMA2_CNDTR1 (STM32_DMA2_BASE+STM32_DMA_CNDTR1_OFFSET) +#define STM32_DMA2_CNDTR2 (STM32_DMA2_BASE+STM32_DMA_CNDTR2_OFFSET) +#define STM32_DMA2_CNDTR3 (STM32_DMA2_BASE+STM32_DMA_CNDTR3_OFFSET) +#define STM32_DMA2_CNDTR4 (STM32_DMA2_BASE+STM32_DMA_CNDTR4_OFFSET) +#define STM32_DMA2_CNDTR5 (STM32_DMA2_BASE+STM32_DMA_CNDTR5_OFFSET) +#if defined(CONFIG_STM32_DMA2_HAVE_CHAN678) +# define STM32_DMA2_CNDTR6 (STM32_DMA2_BASE+STM32_DMA_CNDTR6_OFFSET) +# define STM32_DMA2_CNDTR7 (STM32_DMA2_BASE+STM32_DMA_CNDTR7_OFFSET) +# define STM32_DMA2_CNDTR8 (STM32_DMA2_BASE+STM32_DMA_CNDTR8_OFFSET) +#endif + +#define STM32_DMA2_CPAR(n) (STM32_DMA2_BASE+STM32_DMA_CPAR_OFFSET(n)) +#define STM32_DMA2_CPAR1 (STM32_DMA2_BASE+STM32_DMA_CPAR1_OFFSET) +#define STM32_DMA2_CPAR2 (STM32_DMA2_BASE+STM32_DMA_CPAR2_OFFSET) +#define STM32_DMA2_CPAR3 (STM32_DMA2_BASE+STM32_DMA_CPAR3_OFFSET) +#define STM32_DMA2_CPAR4 (STM32_DMA2_BASE+STM32_DMA_CPAR4_OFFSET) +#define STM32_DMA2_CPAR5 (STM32_DMA2_BASE+STM32_DMA_CPAR5_OFFSET) +#if defined(CONFIG_STM32_DMA2_HAVE_CHAN678) +# define STM32_DMA2_CPAR6 (STM32_DMA2_BASE+STM32_DMA_CPAR6_OFFSET) +# define STM32_DMA2_CPAR7 (STM32_DMA2_BASE+STM32_DMA_CPAR7_OFFSET) +# define STM32_DMA2_CPAR8 (STM32_DMA2_BASE+STM32_DMA_CPAR8_OFFSET) +#endif + +#define STM32_DMA2_CMAR(n) (STM32_DMA2_BASE+STM32_DMA_CMAR_OFFSET(n)) +#define STM32_DMA2_CMAR1 (STM32_DMA2_BASE+STM32_DMA_CMAR1_OFFSET) +#define STM32_DMA2_CMAR2 (STM32_DMA2_BASE+STM32_DMA_CMAR2_OFFSET) +#define STM32_DMA2_CMAR3 (STM32_DMA2_BASE+STM32_DMA_CMAR3_OFFSET) +#define STM32_DMA2_CMAR4 (STM32_DMA2_BASE+STM32_DMA_CMAR4_OFFSET) +#define STM32_DMA2_CMAR5 (STM32_DMA2_BASE+STM32_DMA_CMAR5_OFFSET) +#if defined(CONFIG_STM32_DMA2_HAVE_CHAN678) +# define STM32_DMA2_CMAR6 (STM32_DMA2_BASE+STM32_DMA_CMAR6_OFFSET) +# define STM32_DMA2_CMAR7 (STM32_DMA2_BASE+STM32_DMA_CMAR7_OFFSET) +# define STM32_DMA2_CMAR8 (STM32_DMA2_BASE+STM32_DMA_CMAR8_OFFSET) +#endif + +/* Register Bitfield Definitions ********************************************/ + +#define DMA_CHAN_SHIFT(n) ((n) << 2) +#define DMA_CHAN_MASK 0x0f +#define DMA_CHAN_GIF_BIT (1 << 0) /* Bit 0: Channel Global interrupt flag */ +#define DMA_CHAN_TCIF_BIT (1 << 1) /* Bit 1: Channel Transfer Complete flag */ +#define DMA_CHAN_HTIF_BIT (1 << 2) /* Bit 2: Channel Half Transfer flag */ +#define DMA_CHAN_TEIF_BIT (1 << 3) /* Bit 3: Channel Transfer Error flag */ + +/* DMA interrupt status register */ + +#define DMA_ISR_CHAN_SHIFT(n) DMA_CHAN_SHIFT(n) +#define DMA_ISR_CHAN_MASK(n) (DMA_CHAN_MASK << DMA_ISR_CHAN_SHIFT(n)) +#define DMA_ISR_CHAN1_SHIFT (0) /* Bits 3-0: DMA Channel 1 interrupt status */ +#define DMA_ISR_CHAN1_MASK (DMA_CHAN_MASK << DMA_ISR_CHAN1_SHIFT) +#define DMA_ISR_CHAN2_SHIFT (4) /* Bits 7-4: DMA Channel 2 interrupt status */ +#define DMA_ISR_CHAN2_MASK (DMA_CHAN_MASK << DMA_ISR_CHAN2_SHIFT) +#define DMA_ISR_CHAN3_SHIFT (8) /* Bits 11-8: DMA Channel 3 interrupt status */ +#define DMA_ISR_CHAN3_MASK (DMA_CHAN_MASK << DMA_ISR_CHAN3_SHIFT) +#define DMA_ISR_CHAN4_SHIFT (12) /* Bits 15-12: DMA Channel 4 interrupt status */ +#define DMA_ISR_CHAN4_MASK (DMA_CHAN_MASK << DMA_ISR_CHAN4_SHIFT) +#define DMA_ISR_CHAN5_SHIFT (16) /* Bits 19-16: DMA Channel 5 interrupt status */ +#define DMA_ISR_CHAN5_MASK (DMA_CHAN_MASK << DMA_ISR_CHAN5_SHIFT) +#define DMA_ISR_CHAN6_SHIFT (20) /* Bits 23-20: DMA Channel 6 interrupt status */ +#define DMA_ISR_CHAN6_MASK (DMA_CHAN_MASK << DMA_ISR_CHAN6_SHIFT) +#define DMA_ISR_CHAN7_SHIFT (24) /* Bits 27-24: DMA Channel 7 interrupt status */ +#define DMA_ISR_CHAN7_MASK (DMA_CHAN_MASK << DMA_ISR_CHAN7_SHIFT) +#define DMA_ISR_CHAN8_SHIFT (28) /* Bits 31-28: DMA Channel 8 interrupt status */ +#define DMA_ISR_CHAN8_MASK (DMA_CHAN_MASK << DMA_ISR_CHAN8_SHIFT) + +#define DMA_ISR_GIF(n) (DMA_CHAN_GIF_BIT << DMA_ISR_CHAN_SHIFT(n)) +#define DMA_ISR_TCIF(n) (DMA_CHAN_TCIF_BIT << DMA_ISR_CHAN_SHIFT(n)) +#define DMA_ISR_HTIF(n) (DMA_CHAN_HTIF_BIT << DMA_ISR_CHAN_SHIFT(n)) +#define DMA_ISR_TEIF(n) (DMA_CHAN_TEIF_BIT << DMA_ISR_CHAN_SHIFT(n)) + +/* DMA interrupt flag clear register */ + +#define DMA_IFCR_CHAN_SHIFT(n) DMA_CHAN_SHIFT(n) +#define DMA_IFCR_CHAN_MASK(n) (DMA_CHAN_MASK << DMA_IFCR_CHAN_SHIFT(n)) +#define DMA_IFCR_CHAN1_SHIFT (0) /* Bits 3-0: DMA Channel 1 interrupt flag clear */ +#define DMA_IFCR_CHAN1_MASK (DMA_CHAN_MASK << DMA_IFCR_CHAN1_SHIFT) +#define DMA_IFCR_CHAN2_SHIFT (4) /* Bits 7-4: DMA Channel 2 interrupt flag clear */ +#define DMA_IFCR_CHAN2_MASK (DMA_CHAN_MASK << DMA_IFCR_CHAN2_SHIFT) +#define DMA_IFCR_CHAN3_SHIFT (8) /* Bits 11-8: DMA Channel 3 interrupt flag clear */ +#define DMA_IFCR_CHAN3_MASK (DMA_CHAN_MASK << DMA_IFCR_CHAN3_SHIFT) +#define DMA_IFCR_CHAN4_SHIFT (12) /* Bits 15-12: DMA Channel 4 interrupt flag clear */ +#define DMA_IFCR_CHAN4_MASK (DMA_CHAN_MASK << DMA_IFCR_CHAN4_SHIFT) +#define DMA_IFCR_CHAN5_SHIFT (16) /* Bits 19-16: DMA Channel 5 interrupt flag clear */ +#define DMA_IFCR_CHAN5_MASK (DMA_CHAN_MASK << DMA_IFCR_CHAN5_SHIFT) +#define DMA_IFCR_CHAN6_SHIFT (20) /* Bits 23-20: DMA Channel 6 interrupt flag clear */ +#define DMA_IFCR_CHAN6_MASK (DMA_CHAN_MASK << DMA_IFCR_CHAN6_SHIFT) +#define DMA_IFCR_CHAN7_SHIFT (24) /* Bits 27-24: DMA Channel 7 interrupt flag clear */ +#define DMA_IFCR_CHAN7_MASK (DMA_CHAN_MASK << DMA_IFCR_CHAN7_SHIFT) +#define DMA_IFCR_CHAN8_SHIFT (28) /* Bits 31-28: DMA Channel 8 interrupt flag clear */ +#define DMA_IFCR_CHAN8_MASK (DMA_CHAN_MASK << DMA_IFCR_CHAN8_SHIFT) + +#if defined(CONFIG_STM32_DMA1_HAVE_CHAN8) || defined(CONFIG_STM32_DMA2_HAVE_CHAN678) +# define DMA_IFCR_ALLCHANNELS (0xffffffff) +#else +# define DMA_IFCR_ALLCHANNELS (0x0fffffff) +#endif + +#define DMA_IFCR_CGIF(n) (DMA_CHAN_GIF_BIT << DMA_IFCR_CHAN_SHIFT(n)) +#define DMA_IFCR_CTCIF(n) (DMA_CHAN_TCIF_BIT << DMA_IFCR_CHAN_SHIFT(n)) +#define DMA_IFCR_CHTIF(n) (DMA_CHAN_HTIF_BIT << DMA_IFCR_CHAN_SHIFT(n)) +#define DMA_IFCR_CTEIF(n) (DMA_CHAN_TEIF_BIT << DMA_IFCR_CHAN_SHIFT(n)) + +/* DMA channel configuration register */ + +#define DMA_CCR_EN (1 << 0) /* Bit 0: Channel enable */ +#define DMA_CCR_TCIE (1 << 1) /* Bit 1: Transfer complete interrupt enable */ +#define DMA_CCR_HTIE (1 << 2) /* Bit 2: Half Transfer interrupt enable */ +#define DMA_CCR_TEIE (1 << 3) /* Bit 3: Transfer error interrupt enable */ +#define DMA_CCR_DIR (1 << 4) /* Bit 4: Data transfer direction */ +#define DMA_CCR_CIRC (1 << 5) /* Bit 5: Circular mode */ +#define DMA_CCR_PINC (1 << 6) /* Bit 6: Peripheral increment mode */ +#define DMA_CCR_MINC (1 << 7) /* Bit 7: Memory increment mode */ +#define DMA_CCR_PSIZE_SHIFT (8) /* Bits 8-9: Peripheral size */ +#define DMA_CCR_PSIZE_MASK (3 << DMA_CCR_PSIZE_SHIFT) +# define DMA_CCR_PSIZE_8BITS (0 << DMA_CCR_PSIZE_SHIFT) /* 00: 8-bits */ +# define DMA_CCR_PSIZE_16BITS (1 << DMA_CCR_PSIZE_SHIFT) /* 01: 16-bits */ +# define DMA_CCR_PSIZE_32BITS (2 << DMA_CCR_PSIZE_SHIFT) /* 10: 32-bits */ +#define DMA_CCR_MSIZE_SHIFT (10) /* Bits 10-11: Memory size */ +#define DMA_CCR_MSIZE_MASK (3 << DMA_CCR_MSIZE_SHIFT) +# define DMA_CCR_MSIZE_8BITS (0 << DMA_CCR_MSIZE_SHIFT) /* 00: 8-bits */ +# define DMA_CCR_MSIZE_16BITS (1 << DMA_CCR_MSIZE_SHIFT) /* 01: 16-bits */ +# define DMA_CCR_MSIZE_32BITS (2 << DMA_CCR_MSIZE_SHIFT) /* 10: 32-bits */ +#define DMA_CCR_PL_SHIFT (12) /* Bits 12-13: Channel Priority level */ +#define DMA_CCR_PL_MASK (3 << DMA_CCR_PL_SHIFT) +# define DMA_CCR_PRILO (0 << DMA_CCR_PL_SHIFT) /* 00: Low */ +# define DMA_CCR_PRIMED (1 << DMA_CCR_PL_SHIFT) /* 01: Medium */ +# define DMA_CCR_PRIHI (2 << DMA_CCR_PL_SHIFT) /* 10: High */ +# define DMA_CCR_PRIVERYHI (3 << DMA_CCR_PL_SHIFT) /* 11: Very high */ +#define DMA_CCR_MEM2MEM (1 << 14) /* Bit 14: Memory to memory mode */ + +#define DMA_CCR_ALLINTS (DMA_CCR_TEIE|DMA_CCR_HTIE|DMA_CCR_TCIE) + +/* DMA channel number of data register */ + +#define DMA_CNDTR_NDT_SHIFT (0) /* Bits 15-0: Number of data to Transfer */ +#define DMA_CNDTR_NDT_MASK (0xffff << DMA_CNDTR_NDT_SHIFT) + +/* DMA Channel mapping. + * Each DMA channel has a mapping to several possible sources/sinks of data. + * The requests from peripherals assigned to a channel are simply OR'ed + * together before entering the DMA block. This means that onlyone request + * on a given channel can be enabled at once. + * + * Alternative DMA channel selections are provided with a numeric suffix like + * _1, _2, etc. Drivers, however, will use the pin selection without the + * numeric suffix. Additional definitions are required in the board.h file. + */ + +#define STM32_DMA1_CHAN1 (0) +#define STM32_DMA1_CHAN2 (1) +#define STM32_DMA1_CHAN3 (2) +#define STM32_DMA1_CHAN4 (3) +#define STM32_DMA1_CHAN5 (4) +#define STM32_DMA1_CHAN6 (5) +#define STM32_DMA1_CHAN7 (6) +#if defined(CONFIG_STM32_DMA1_HAVE_CHAN8) +# define STM32_DMA1_CHAN8 (7) +# define STM32_DMA2_CHAN1 (8) +# define STM32_DMA2_CHAN2 (9) +# define STM32_DMA2_CHAN3 (10) +# define STM32_DMA2_CHAN4 (11) +# define STM32_DMA2_CHAN5 (12) +# if defined(CONFIG_STM32_DMA2_HAVE_CHAN678) +# define STM32_DMA2_CHAN6 (13) +# define STM32_DMA2_CHAN7 (14) +# define STM32_DMA2_CHAN8 (15) +# endif +#else +# define STM32_DMA2_CHAN1 (7) +# define STM32_DMA2_CHAN2 (8) +# define STM32_DMA2_CHAN3 (9) +# define STM32_DMA2_CHAN4 (10) +# define STM32_DMA2_CHAN5 (11) +# if defined(CONFIG_STM32_DMA2_HAVE_CHAN678) +# define STM32_DMA2_CHAN6 (12) +# define STM32_DMA2_CHAN7 (13) +# define STM32_DMA2_CHAN8 (14) +# endif +#endif + +#ifdef DMA_HAVE_CSELR +# define DMACHAN_SETTING(chan, sel) ((((sel) & 0xff) << 8) | ((chan) & 0xff)) +# define DMACHAN_SETTING_CHANNEL_MASK 0x00ff +# define DMACHAN_SETTING_CHANNEL_SHIFT (0) +# define DMACHAN_SETTING_FUNCTION_MASK 0xff00 +# define DMACHAN_SETTING_FUNCTION_SHIFT (8) +#endif + +#if defined(CONFIG_STM32_STM32L15XX) + +# define DMACHAN_ADC1 STM32_DMA1_CHAN1 +# define DMACHAN_TIM2_CH3 STM32_DMA1_CHAN1 +# define DMACHAN_TIM4_CH1 STM32_DMA1_CHAN1 + +# define DMACHAN_SPI1_RX STM32_DMA1_CHAN2 +# define DMACHAN_USART3_TX STM32_DMA1_CHAN2 +# define DMACHAN_TIM2_UP STM32_DMA1_CHAN2 +# define DMACHAN_TIM3_CH3 STM32_DMA1_CHAN2 +# define DMACHAN_TIM6_UP STM32_DMA1_CHAN2 +# define DMACHAN_DAC1_CH1 STM32_DMA1_CHAN2 + +# define DMACHAN_SPI1_TX STM32_DMA1_CHAN3 +# define DMACHAN_USART3_RX STM32_DMA1_CHAN3 +# define DMACHAN_TIM3_CH4 STM32_DMA1_CHAN3 +# define DMACHAN_TIM3_UP STM32_DMA1_CHAN3 +# define DMACHAN_TIM7_UP STM32_DMA1_CHAN3 +# define DMACHAN_DAC1_CH2 STM32_DMA1_CHAN3 + +# define DMACHAN_SPI2_RX STM32_DMA1_CHAN4 +# define DMACHAN_USART1_TX STM32_DMA1_CHAN4 +# define DMACHAN_I2C2_TX STM32_DMA1_CHAN4 +# define DMACHAN_TIM4_CH2 STM32_DMA1_CHAN4 + +# define DMACHAN_SPI2_TX STM32_DMA1_CHAN5 +# define DMACHAN_USART1_RX STM32_DMA1_CHAN5 +# define DMACHAN_I2C2_RX STM32_DMA1_CHAN5 +# define DMACHAN_TIM2_CH1 STM32_DMA1_CHAN5 +# define DMACHAN_TIM4_CH3 STM32_DMA1_CHAN5 + +# define DMACHAN_USART2_RX STM32_DMA1_CHAN6 +# define DMACHAN_I2C1_TX STM32_DMA1_CHAN6 +# define DMACHAN_TIM3_CH1 STM32_DMA1_CHAN6 +# define DMACHAN_TIM3_TRIG STM32_DMA1_CHAN6 + +# define DMACHAN_USART2_TX STM32_DMA1_CHAN7 +# define DMACHAN_I2C1_RX STM32_DMA1_CHAN7 +# define DMACHAN_TIM2_CH2 STM32_DMA1_CHAN7 +# define DMACHAN_TIM2_CH4 STM32_DMA1_CHAN7 +# define DMACHAN_TIM4_UP STM32_DMA1_CHAN7 + +# define DMACHAN_SPI3_RX STM32_DMA2_CHAN1 +# define DMACHAN_UART5_TX STM32_DMA2_CHAN1 +# define DMACHAN_TIM5_CH4 STM32_DMA2_CHAN1 +# define DMACHAN_TIM5_TRIG STM32_DMA2_CHAN1 +# define DMACHAN_TIM5_COM STM32_DMA2_CHAN1 + +# define DMACHAN_SPI3_TX STM32_DMA2_CHAN2 +# define DMACHAN_UART5_RX STM32_DMA2_CHAN2 +# define DMACHAN_TIM5_CH3 STM32_DMA2_CHAN2 +# define DMACHAN_TIM5_UP STM32_DMA2_CHAN2 + +# define DMACHAN_UART4_RX STM32_DMA2_CHAN3 +# define DMACHAN_AES_OUT STM32_DMA2_CHAN3 + +# define DMACHAN_TIM5_CH2 STM32_DMA2_CHAN4 +# define DMACHAN_SDIO STM32_DMA2_CHAN4 + +# define DMACHAN_UART4_TX STM32_DMA2_CHAN5 +# define DMACHAN_TIM5_CH1 STM32_DMA2_CHAN5 +# define DMACHAN_AES_IN STM32_DMA2_CHAN5 + +#elif defined(CONFIG_STM32_STM32F10XX) + +# define DMACHAN_ADC1 STM32_DMA1_CHAN1 +# define DMACHAN_TIM2_CH3 STM32_DMA1_CHAN1 +# define DMACHAN_TIM4_CH1 STM32_DMA1_CHAN1 + +# define DMACHAN_SPI1_RX STM32_DMA1_CHAN2 +# define DMACHAN_USART3_TX STM32_DMA1_CHAN2 +# define DMACHAN_TIM1_CH1 STM32_DMA1_CHAN2 +# define DMACHAN_TIM2_UP STM32_DMA1_CHAN2 +# define DMACHAN_TIM3_CH3 STM32_DMA1_CHAN2 + +# define DMACHAN_SPI1_TX STM32_DMA1_CHAN3 +# define DMACHAN_USART3_RX STM32_DMA1_CHAN3 +# define DMACHAN_TIM1_CH2 STM32_DMA1_CHAN3 +# define DMACHAN_TIM3_CH4 STM32_DMA1_CHAN3 +# define DMACHAN_TIM3_UP STM32_DMA1_CHAN3 + +# define DMACHAN_SPI2_RX STM32_DMA1_CHAN4 +# define DMACHAN_I2S2_RX STM32_DMA1_CHAN4 +# define DMACHAN_USART1_TX STM32_DMA1_CHAN4 +# define DMACHAN_I2C2_TX STM32_DMA1_CHAN4 +# define DMACHAN_TIM1_CH4 STM32_DMA1_CHAN4 +# define DMACHAN_TIM1_TRIG STM32_DMA1_CHAN4 +# define DMACHAN_TIM1_COM STM32_DMA1_CHAN4 +# define DMACHAN_TIM4_CH2 STM32_DMA1_CHAN4 + +# define DMACHAN_SPI2_TX STM32_DMA1_CHAN5 +# define DMACHAN_I2S2_TX STM32_DMA1_CHAN5 +# define DMACHAN_USART1_RX STM32_DMA1_CHAN5 +# define DMACHAN_I2C2_RX STM32_DMA1_CHAN5 +# define DMACHAN_TIM1_UP STM32_DMA1_CHAN5 +# define DMACHAN_TIM2_CH1 STM32_DMA1_CHAN5 +# define DMACHAN_TIM4_CH3 STM32_DMA1_CHAN5 + +# define DMACHAN_USART2_RX STM32_DMA1_CHAN6 +# define DMACHAN_I2C1_TX STM32_DMA1_CHAN6 +# define DMACHAN_TIM1_CH3 STM32_DMA1_CHAN6 +# define DMACHAN_TIM3_CH1 STM32_DMA1_CHAN6 +# define DMACHAN_TIM3_TRIG STM32_DMA1_CHAN6 + +# define DMACHAN_USART2_TX STM32_DMA1_CHAN7 +# define DMACHAN_I2C1_RX STM32_DMA1_CHAN7 +# define DMACHAN_TIM2_CH2 STM32_DMA1_CHAN7 +# define DMACHAN_TIM2_CH4 STM32_DMA1_CHAN7 +# define DMACHAN_TIM4_UP STM32_DMA1_CHAN7 + +# define DMACHAN_SPI3_RX STM32_DMA2_CHAN1 +# define DMACHAN_I2S3_RX STM32_DMA2_CHAN1 +# define DMACHAN_TIM5_CH4 STM32_DMA2_CHAN1 +# define DMACHAN_TIM5_TRIG STM32_DMA2_CHAN1 +# define DMACHAN_TIM8_CH3 STM32_DMA2_CHAN1 +# define DMACHAN_TIM8_UP STM32_DMA2_CHAN1 + +# define DMACHAN_SPI3_TX STM32_DMA2_CHAN2 +# define DMACHAN_I2S3_TX STM32_DMA2_CHAN2 +# define DMACHAN_TIM5_CH3 STM32_DMA2_CHAN2 +# define DMACHAN_TIM5_UP STM32_DMA2_CHAN2 +# define DMACHAN_TIM8_TRIG STM32_DMA2_CHAN2 +# define DMACHAN_TIM8_COM STM32_DMA2_CHAN2 + +# define DMACHAN_UART4_RX STM32_DMA2_CHAN3 +# define DMACHAN_TIM6_UP STM32_DMA2_CHAN3 +# define DMACHAN_DAC1_CH1 STM32_DMA2_CHAN3 +# define DMACHAN_TIM8_CH1 STM32_DMA2_CHAN3 + +# define DMACHAN_SDIO STM32_DMA2_CHAN4 +# define DMACHAN_TIM5_CH2 STM32_DMA2_CHAN4 +# define DMACHAN_TIM7_UP STM32_DMA2_CHAN4 +# define DMACHAN_DAC1_CH2 STM32_DMA2_CHAN4 + +# define DMACHAN_ADC3 STM32_DMA2_CHAN5 +# define DMACHAN_UART4_TX STM32_DMA2_CHAN5 +# define DMACHAN_TIM5_CH1 STM32_DMA2_CHAN5 +# define DMACHAN_TIM8_CH2 STM32_DMA2_CHAN5 + +#elif defined(CONFIG_STM32_STM32F30XX) + +# define DMACHAN_ADC1 STM32_DMA1_CHAN1 +# define DMACHAN_TIM2_CH3 STM32_DMA1_CHAN1 +# define DMACHAN_TIM4_CH1 STM32_DMA1_CHAN1 +# define DMACHAN_TIM17_CH1 STM32_DMA1_CHAN1 +# define DMACHAN_TIM17_UP STM32_DMA1_CHAN1 + +# define DMACHAN_SPI1_RX STM32_DMA1_CHAN2 +# define DMACHAN_USART3_TX STM32_DMA1_CHAN2 +# define DMACHAN_TIM1_CH1 STM32_DMA1_CHAN2 +# define DMACHAN_TIM2_UP STM32_DMA1_CHAN2 +# define DMACHAN_TIM3_CH3 STM32_DMA1_CHAN2 + +# define DMACHAN_SPI1_TX STM32_DMA1_CHAN3 +# define DMACHAN_USART3_RX STM32_DMA1_CHAN3 +# define DMACHAN_TIM1_CH2_1 STM32_DMA1_CHAN3 +# define DMACHAN_TIM3_CH4 STM32_DMA1_CHAN3 +# define DMACHAN_TIM3_UP_2 STM32_DMA1_CHAN3 +# define DMACHAN_DAC1_CH1_1 STM32_DMA1_CHAN3 + +# define DMACHAN_SPI2_RX STM32_DMA1_CHAN4 +# define DMACHAN_I2S2_RX STM32_DMA1_CHAN4 +# define DMACHAN_USART1_TX STM32_DMA1_CHAN4 +# define DMACHAN_I2C2_TX STM32_DMA1_CHAN4 +# define DMACHAN_TIM1_CH4 STM32_DMA1_CHAN4 +# define DMACHAN_TIM1_TRIG STM32_DMA1_CHAN4 +# define DMACHAN_TIM1_COM STM32_DMA1_CHAN4 +# define DMACHAN_TIM4_CH2 STM32_DMA1_CHAN4 +# define DMACHAN_TIM7_UP_1 STM32_DMA1_CHAN4 +# define DMACHAN_DAC1_CH2_1 STM32_DMA1_CHAN4 /* NOTE: a typo in the ref manual */ + +# define DMACHAN_SPI2_TX STM32_DMA1_CHAN5 +# define DMACHAN_I2S2_TX STM32_DMA1_CHAN5 +# define DMACHAN_USART1_RX STM32_DMA1_CHAN5 +# define DMACHAN_I2C2_RX STM32_DMA1_CHAN5 +# define DMACHAN_TIM1_UP STM32_DMA1_CHAN5 +# define DMACHAN_TIM2_CH1 STM32_DMA1_CHAN5 +# define DMACHAN_TIM4_CH3 STM32_DMA1_CHAN5 +# define DMACHAN_TIM15_CH1 STM32_DMA1_CHAN5 +# define DMACHAN_TIM15_UP STM32_DMA1_CHAN5 +# define DMACHAN_TIM15_TRIG STM32_DMA1_CHAN5 +# define DMACHAN_TIM15_COM STM32_DMA1_CHAN5 +# define DMACHAN_DAC2_CH1 STM32_DMA1_CHAN5 + +# define DMACHAN_USART2_RX STM32_DMA1_CHAN6 +# define DMACHAN_I2C1_TX STM32_DMA1_CHAN6 +# define DMACHAN_TIM1_CH3 STM32_DMA1_CHAN6 +# define DMACHAN_TIM3_CH1 STM32_DMA1_CHAN6 +# define DMACHAN_TIM3_TRIG STM32_DMA1_CHAN6 +# define DMACHAN_TIM16_CH1 STM32_DMA1_CHAN6 +# define DMACHAN_TIM16_UP STM32_DMA1_CHAN6 + +# define DMACHAN_USART2_TX STM32_DMA1_CHAN7 +# define DMACHAN_I2C1_RX STM32_DMA1_CHAN7 +# define DMACHAN_TIM2_CH2 STM32_DMA1_CHAN7 +# define DMACHAN_TIM2_CH4 STM32_DMA1_CHAN7 +# define DMACHAN_TIM4_UP STM32_DMA1_CHAN7 +# define DMACHAN_TIM17_CH1_2 STM32_DMA1_CHAN7 +# define DMACHAN_TIM17_UP_2 STM32_DMA1_CHAN7 + +# define DMACHAN_ADC2_1 STM32_DMA2_CHAN1 +# define DMACHAN_SPI3_RX STM32_DMA2_CHAN1 +# define DMACHAN_I2S3_RX STM32_DMA2_CHAN1 +# define DMACHAN_TIM8_CH3 STM32_DMA2_CHAN1 +# define DMACHAN_TIM8_UP STM32_DMA2_CHAN1 + +# define DMACHAN_ADC4_1 STM32_DMA2_CHAN2 +# define DMACHAN_SPI3_TX STM32_DMA2_CHAN2 +# define DMACHAN_I2S3_TX STM32_DMA2_CHAN2 +# define DMACHAN_TIM8_CH4 STM32_DMA2_CHAN2 +# define DMACHAN_TIM8_TRIG STM32_DMA2_CHAN2 +# define DMACHAN_TIM8_COM STM32_DMA2_CHAN2 + +# define DMACHAN_ADC2_2 STM32_DMA2_CHAN3 +# define DMACHAN_UART4_RX STM32_DMA2_CHAN3 +# define DMACHAN_TIM6_UP STM32_DMA2_CHAN3 +# define DMACHAN_DAC1_CH1_2 STM32_DMA2_CHAN3 +# define DMACHAN_TIM8_CH1 STM32_DMA2_CHAN3 + +# define DMACHAN_ADC4_2 STM32_DMA2_CHAN4 +# define DMACHAN_TIM7_UP_2 STM32_DMA2_CHAN4 +# define DMACHAN_DAC1_CH2_2 STM32_DMA2_CHAN4 + +# define DMACHAN_ADC3 STM32_DMA2_CHAN5 +# define DMACHAN_UART4_TX STM32_DMA2_CHAN5 +# define DMACHAN_TIM8_CH2 STM32_DMA2_CHAN5 + +#elif defined(CONFIG_STM32_STM32F33XX) + +# define DMACHAN_ADC1 STM32_DMA1_CHAN1 +# define DMACHAN_TIM2_CH3 STM32_DMA1_CHAN1 +# define DMACHAN_TIM17_CH1_1 STM32_DMA1_CHAN1 +# define DMACHAN_TIM17_UP_1 STM32_DMA1_CHAN1 + +# define DMACHAN_ADC2_1 STM32_DMA1_CHAN2 +# define DMACHAN_SPI1_RX_1 STM32_DMA1_CHAN2 +# define DMACHAN_USART3_TX STM32_DMA1_CHAN2 +# define DMACHAN_I2C1_TX_3 STM32_DMA1_CHAN4 +# define DMACHAN_TIM1_CH1 STM32_DMA1_CHAN2 +# define DMACHAN_TIM2_UP STM32_DMA1_CHAN2 +# define DMACHAN_TIM3_CH3 STM32_DMA1_CHAN2 +# define DMACHAN_HRTIM1_M STM32_DMA1_CHAN2 + +# define DMACHAN_SPI1_TX_1 STM32_DMA1_CHAN3 +# define DMACHAN_USART3_RX STM32_DMA1_CHAN3 +# define DMACHAN_I2C1_RX_2 STM32_DMA1_CHAN3 +# define DMACHAN_TIM3_CH4 STM32_DMA1_CHAN3 +# define DMACHAN_TIM3_UP STM32_DMA1_CHAN3 +# define DMACHAN_TIM6_UP STM32_DMA1_CHAN3 +# define DMACHAN_DAC1_CH1 STM32_DMA1_CHAN3 +# define DMACHAN_TIM16_CH1_1 STM32_DMA1_CHAN3 +# define DMACHAN_TIM16_UP_1 STM32_DMA1_CHAN3 +# define DMACHAN_HRTIM1_A STM32_DMA1_CHAN3 + +# define DMACHAN_ADC2_2 STM32_DMA1_CHAN4 +# define DMACHAN_SPI1_RX_2 STM32_DMA1_CHAN4 +# define DMACHAN_USART1_TX STM32_DMA1_CHAN4 +# define DMACHAN_I2C1_TX_3 STM32_DMA1_CHAN4 +# define DMACHAN_TIM1_CH4 STM32_DMA1_CHAN4 +# define DMACHAN_TIM1_TRIG STM32_DMA1_CHAN4 +# define DMACHAN_TIM1_COM STM32_DMA1_CHAN4 +# define DMACHAN_TIM7_UP STM32_DMA1_CHAN4 +# define DMACHAN_DAC1_CH2 STM32_DMA1_CHAN4 +# define DMACHAN_HRTIM1_B STM32_DMA1_CHAN4 + +# define DMACHAN_SPI1_TX_2 STM32_DMA1_CHAN5 +# define DMACHAN_USART1_RX STM32_DMA1_CHAN5 +# define DMACHAN_I2C1_RX_3 STM32_DMA1_CHAN5 +# define DMACHAN_TIM1_UP STM32_DMA1_CHAN5 +# define DMACHAN_TIM2_CH1 STM32_DMA1_CHAN5 +# define DMACHAN_DAC2_CH1 STM32_DMA1_CHAN5 +# define DMACHAN_TIM15_CH1 STM32_DMA1_CHAN5 +# define DMACHAN_TIM15_UP STM32_DMA1_CHAN5 +# define DMACHAN_TIM15_TRIG STM32_DMA1_CHAN5 +# define DMACHAN_TIM15_COM STM32_DMA1_CHAN5 +# define DMACHAN_HRTIM1_C STM32_DMA1_CHAN5 + +# define DMACHAN_SPI1_RX_3 STM32_DMA1_CHAN6 +# define DMACHAN_USART2_RX STM32_DMA1_CHAN6 +# define DMACHAN_I2C1_TX_1 STM32_DMA1_CHAN6 +# define DMACHAN_TIM1_CH3 STM32_DMA1_CHAN6 +# define DMACHAN_TIM3_CH1 STM32_DMA1_CHAN6 +# define DMACHAN_TIM3_TRIG STM32_DMA1_CHAN6 +# define DMACHAN_TIM16_CH1_2 STM32_DMA1_CHAN6 +# define DMACHAN_TIM16_UP_2 STM32_DMA1_CHAN6 +# define DMACHAN_HRTIM1_D STM32_DMA1_CHAN6 + +# define DMACHAN_SPI1_TX_3 STM32_DMA1_CHAN7 +# define DMACHAN_USART2_TX STM32_DMA1_CHAN7 +# define DMACHAN_I2C1_RX_1 STM32_DMA1_CHAN7 +# define DMACHAN_TIM2_CH2 STM32_DMA1_CHAN7 +# define DMACHAN_TIM2_CH4 STM32_DMA1_CHAN7 +# define DMACHAN_TIM17_CH1_2 STM32_DMA1_CHAN7 +# define DMACHAN_TIM17_UP_2 STM32_DMA1_CHAN7 +# define DMACHAN_HRTIM1_E STM32_DMA1_CHAN7 + +#elif defined(CONFIG_STM32_STM32F37XX) + +# define DMACHAN_ADC1 STM32_DMA1_CHAN1 +# define DMACHAN_TIM2_CH3 STM32_DMA1_CHAN1 +# define DMACHAN_TIM4_CH1 STM32_DMA1_CHAN1 +# define DMACHAN_TIM17_CH1 STM32_DMA1_CHAN1 +# define DMACHAN_TIM17_UP STM32_DMA1_CHAN1 + +# define DMACHAN_SPI1_RX STM32_DMA1_CHAN2 +# define DMACHAN_USART3_TX STM32_DMA1_CHAN2 +# define DMACHAN_TIM2_UP STM32_DMA1_CHAN2 +# define DMACHAN_TIM3_CH3 STM32_DMA1_CHAN2 +# define DMACHAN_TIM19_CH1 STM32_DMA1_CHAN2 + +# define DMACHAN_SPI1_TX STM32_DMA1_CHAN3 +# define DMACHAN_USART3_RX STM32_DMA1_CHAN3 +# define DMACHAN_TIM3_CH4 STM32_DMA1_CHAN3 +# define DMACHAN_TIM3_UP STM32_DMA1_CHAN3 +# define DMACHAN_TIM6_UP STM32_DMA1_CHAN3 +# define DMACHAN_DAC1_CH1 STM32_DMA1_CHAN3 +# define DMACHAN_TIM16_CH1 STM32_DMA1_CHAN3 +# define DMACHAN_TIM16_UP STM32_DMA1_CHAN3 +# define DMACHAN_TIM19_CH2 STM32_DMA1_CHAN3 + +# define DMACHAN_SPI2_RX STM32_DMA1_CHAN4 +# define DMACHAN_USART1_TX STM32_DMA1_CHAN4 +# define DMACHAN_I2C2_TX STM32_DMA1_CHAN4 +# define DMACHAN_TIM4_CH2 STM32_DMA1_CHAN4 +# define DMACHAN_TIM7_UP STM32_DMA1_CHAN4 +# define DMACHAN_DAC1_CH2 STM32_DMA1_CHAN4 +# define DMACHAN_TIM19_UP STM32_DMA1_CHAN4 + +# define DMACHAN_SPI2_TX STM32_DMA1_CHAN5 +# define DMACHAN_USART1_RX STM32_DMA1_CHAN5 +# define DMACHAN_I2C2_RX STM32_DMA1_CHAN5 +# define DMACHAN_TIM2_CH1 STM32_DMA1_CHAN5 +# define DMACHAN_TIM4_CH3 STM32_DMA1_CHAN5 +# define DMACHAN_TIM18_UP STM32_DMA1_CHAN5 +# define DMACHAN_DAC2_CH1 STM32_DMA1_CHAN5 +# define DMACHAN_TIM15_CH1 STM32_DMA1_CHAN5 +# define DMACHAN_TIM15_UP STM32_DMA1_CHAN5 +# define DMACHAN_TIM15_TRIG STM32_DMA1_CHAN5 +# define DMACHAN_TIM15_COM STM32_DMA1_CHAN5 + +# define DMACHAN_USART2_RX STM32_DMA1_CHAN6 +# define DMACHAN_I2C1_TX STM32_DMA1_CHAN6 +# define DMACHAN_TIM3_CH1 STM32_DMA1_CHAN6 +# define DMACHAN_TIM3_TRIG STM32_DMA1_CHAN6 +# define DMACHAN_TIM16_CH1_2 STM32_DMA1_CHAN6 +# define DMACHAN_TIM16_UP_2 STM32_DMA1_CHAN6 + +# define DMACHAN_USART2_TX STM32_DMA1_CHAN7 +# define DMACHAN_I2C1_RX STM32_DMA1_CHAN6 +# define DMACHAN_TIM2_CH2 STM32_DMA1_CHAN6 +# define DMACHAN_TIM2_CH4 STM32_DMA1_CHAN6 +# define DMACHAN_TIM4_UP STM32_DMA1_CHAN6 +# define DMACHAN_TIM17_CH1_2 STM32_DMA1_CHAN6 +# define DMACHAN_TIM17_UP_2 STM32_DMA1_CHAN6 + +# define DMACHAN_SPI3_RX STM32_DMA2_CHAN1 +# define DMACHAN_TIM5_CH4 STM32_DMA2_CHAN1 +# define DMACHAN_TIM5_TRIG STM32_DMA2_CHAN1 + +# define DMACHAN_SPI3_TX STM32_DMA2_CHAN2 +# define DMACHAN_TIM5_CH3 STM32_DMA2_CHAN2 +# define DMACHAN_TIM5_UP STM32_DMA2_CHAN2 + +# define DMACHAN_SDADC1 STM32_DMA2_CHAN3 +# define DMACHAN_TIM6_UP_2 STM32_DMA2_CHAN3 +# define DMACHAN_DAC1_CH1_2 STM32_DMA2_CHAN3 + +# define DMACHAN_SDADC2 STM32_DMA2_CHAN4 +# define DMACHAN_TIM5_CH2 STM32_DMA2_CHAN4 +# define DMACHAN_TIM7_UP_2 STM32_DMA2_CHAN4 +# define DMACHAN_DAC1_CH2_2 STM32_DMA2_CHAN4 + +# define DMACHAN_SDADC3 STM32_DMA2_CHAN5 +# define DMACHAN_TIM5_CH1 STM32_DMA2_CHAN5 +# define DMACHAN_TIM18_UP_2 STM32_DMA2_CHAN5 +# define DMACHAN_DAC2_CH1_2 STM32_DMA2_CHAN5 + +#elif defined(CONFIG_STM32_STM32G4XXX) + +/* This family uses a DMAMUX. The code to support this needs to be ported + * to this family from STM32L4R. + */ + +#else +# error "Unknown DMA channel assignments" +#endif + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DMA_V1_8CH_H */ diff --git a/arch/arm/src/stm32/hardware/stm32_dma_v2.h b/arch/arm/src/common/stm32/hardware/stm32_dma_v2.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32_dma_v2.h rename to arch/arm/src/common/stm32/hardware/stm32_dma_v2.h index 916ddc1380461..cff6393fb1296 100644 --- a/arch/arm/src/stm32/hardware/stm32_dma_v2.h +++ b/arch/arm/src/common/stm32/hardware/stm32_dma_v2.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32_dma_v2.h + * arch/arm/src/common/stm32/hardware/stm32_dma_v2.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_DMA_V2_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_DMA_V2_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DMA_V2_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DMA_V2_H /**************************************************************************** * Pre-processor Definitions @@ -558,4 +558,4 @@ #define DMAMAP_TIM8_TRIG STM32_DMA_MAP(DMA2,DMA_STREAM7,DMA_CHAN7) #define DMAMAP_TIM8_COM STM32_DMA_MAP(DMA2,DMA_STREAM7,DMA_CHAN7) -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_DMA_V2_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DMA_V2_H */ diff --git a/arch/arm/src/common/stm32/hardware/stm32_dmamux.h b/arch/arm/src/common/stm32/hardware/stm32_dmamux.h new file mode 100644 index 0000000000000..1531e37123a7d --- /dev/null +++ b/arch/arm/src/common/stm32/hardware/stm32_dmamux.h @@ -0,0 +1,40 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/hardware/stm32_dmamux.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DMAMUX_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DMAMUX_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#if defined(CONFIG_STM32_HAVE_IP_DMA_V1_7CH_DMAMUX) +# include "hardware/stm32_dmamux_7ch.h" +#elif defined(CONFIG_STM32_HAVE_IP_DMA_V1_8CH_DMAMUX) +# include "hardware/stm32_dmamux_16ch.h" +#else +# error "Unsupported STM32 DMAMUX" +#endif + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DMAMUX_H */ diff --git a/arch/arm/src/common/stm32/hardware/stm32_dmamux_16ch.h b/arch/arm/src/common/stm32/hardware/stm32_dmamux_16ch.h new file mode 100644 index 0000000000000..bc0cc2d68321e --- /dev/null +++ b/arch/arm/src/common/stm32/hardware/stm32_dmamux_16ch.h @@ -0,0 +1,179 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/hardware/stm32_dmamux_16ch.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DMAMUX_16CH_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DMAMUX_16CH_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include "chip.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define DMAMUX1 0 + +/* Register Offsets *********************************************************/ + +#define STM32_DMAMUX_CXCR_OFFSET(x) (0x0000 + (0x0004 * (x))) /* DMAMUX1 request line multiplexer channel x configuration register */ +#define STM32_DMAMUX_C0CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(0) /* 0x000 */ +#define STM32_DMAMUX_C1CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(1) /* 0x004 */ +#define STM32_DMAMUX_C2CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(2) /* 0x008 */ +#define STM32_DMAMUX_C3CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(3) /* 0x00c */ +#define STM32_DMAMUX_C4CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(4) /* 0x010 */ +#define STM32_DMAMUX_C5CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(5) /* 0x014 */ +#define STM32_DMAMUX_C6CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(6) /* 0x018 */ +#define STM32_DMAMUX_C7CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(7) /* 0x01c */ +#define STM32_DMAMUX_C8CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(8) /* 0x020 */ +#define STM32_DMAMUX_C9CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(9) /* 0x024 */ +#define STM32_DMAMUX_C10CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(10) /* 0x028 */ +#define STM32_DMAMUX_C11CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(11) /* 0x02c */ +#define STM32_DMAMUX_C12CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(12) /* 0x030 */ +#define STM32_DMAMUX_C13CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(13) /* 0x034 */ +#define STM32_DMAMUX_C14CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(14) /* 0x038 */ +#define STM32_DMAMUX_C15CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(15) /* 0x03c */ + /* 0x040-0x07C: Reserved */ +#define STM32_DMAMUX_CSR_OFFSET 0x0080 /* DMAMUX1 request line multiplexer interrupt channel status register */ +#define STM32_DMAMUX_CFR_OFFSET 0x0084 /* DMAMUX1 request line multiplexer interrupt clear flag register */ + /* 0x088-0x0FC: Reserved */ +#define STM32_DMAMUX_RGXCR_OFFSET(x) (0x0100 + (0x004 * (x))) /* DMAMUX1 request generator channel x configuration register */ +#define STM32_DMAMUX_RG0CR_OFFSET STM32_DMAMUX_RGXCR_OFFSET(0) +#define STM32_DMAMUX_RG1CR_OFFSET STM32_DMAMUX_RGXCR_OFFSET(1) +#define STM32_DMAMUX_RG2CR_OFFSET STM32_DMAMUX_RGXCR_OFFSET(2) +#define STM32_DMAMUX_RG3CR_OFFSET STM32_DMAMUX_RGXCR_OFFSET(3) +#define STM32_DMAMUX_RGSR_OFFSET 0x0140 /* DMAMUX1 request generator interrupt status register */ +#define STM32_DMAMUX_RGCFR_OFFSET 0x0144 /* DMAMUX1 request generator interrupt clear flag register */ + /* 0x148-0x3FC: Reserved */ + +/* Register Addresses *******************************************************/ + +#define STM32_DMAMUX1_CXCR(x) (STM32_DMAMUX1_BASE + STM32_DMAMUX_CXCR_OFFSET(x)) +#define STM32_DMAMUX1_C0CR (STM32_DMAMUX1_BASE + STM32_DMAMUX_C0CR_OFFSET) +#define STM32_DMAMUX1_C1CR (STM32_DMAMUX1_BASE + STM32_DMAMUX_C1CR_OFFSET) +#define STM32_DMAMUX1_C2CR (STM32_DMAMUX1_BASE + STM32_DMAMUX_C2CR_OFFSET) +#define STM32_DMAMUX1_C3CR (STM32_DMAMUX1_BASE + STM32_DMAMUX_C3CR_OFFSET) +#define STM32_DMAMUX1_C4CR (STM32_DMAMUX1_BASE + STM32_DMAMUX_C4CR_OFFSET) +#define STM32_DMAMUX1_C5CR (STM32_DMAMUX1_BASE + STM32_DMAMUX_C5CR_OFFSET) +#define STM32_DMAMUX1_C6CR (STM32_DMAMUX1_BASE + STM32_DMAMUX_C6CR_OFFSET) +#define STM32_DMAMUX1_C7CR (STM32_DMAMUX1_BASE + STM32_DMAMUX_C7CR_OFFSET) +#define STM32_DMAMUX1_C8CR (STM32_DMAMUX1_BASE + STM32_DMAMUX_C8CR_OFFSET) +#define STM32_DMAMUX1_C9CR (STM32_DMAMUX1_BASE + STM32_DMAMUX_C9CR_OFFSET) +#define STM32_DMAMUX1_C10CR (STM32_DMAMUX1_BASE + STM32_DMAMUX_C10CR_OFFSET) +#define STM32_DMAMUX1_C11CR (STM32_DMAMUX1_BASE + STM32_DMAMUX_C11CR_OFFSET) +#define STM32_DMAMUX1_C12CR (STM32_DMAMUX1_BASE + STM32_DMAMUX_C12CR_OFFSET) +#define STM32_DMAMUX1_C13CR (STM32_DMAMUX1_BASE + STM32_DMAMUX_C13CR_OFFSET) +#define STM32_DMAMUX1_C14CR (STM32_DMAMUX1_BASE + STM32_DMAMUX_C14CR_OFFSET) +#define STM32_DMAMUX1_C15CR (STM32_DMAMUX1_BASE + STM32_DMAMUX_C15CR_OFFSET) + +#define STM32_DMAMUX1_CSR (STM32_DMAMUX1_BASE + STM32_DMAMUX_CSR_OFFSET) +#define STM32_DMAMUX1_CFR (STM32_DMAMUX1_BASE + STM32_DMAMUX_CFR_OFFSET) + +#define STM32_DMAMUX1_RGXCR(x) (STM32_DMAMUX1_BASE + STM32_DMAMUX_RGXCR_OFFSET(x)) +#define STM32_DMAMUX1_RG0CR (STM32_DMAMUX1_BASE + STM32_DMAMUX_RG0CR_OFFSET) +#define STM32_DMAMUX1_RG1CR (STM32_DMAMUX1_BASE + STM32_DMAMUX_RG1CR_OFFSET) +#define STM32_DMAMUX1_RG2CR (STM32_DMAMUX1_BASE + STM32_DMAMUX_RG2CR_OFFSET) +#define STM32_DMAMUX1_RG3CR (STM32_DMAMUX1_BASE + STM32_DMAMUX_RG3CR_OFFSET) + +#define STM32_DMAMUX1_RGSR (STM32_DMAMUX1_BASE + STM32_DMAMUX_RGSR_OFFSET) +#define STM32_DMAMUX1_RGCFR (STM32_DMAMUX1_BASE + STM32_DMAMUX_RGCFR_OFFSET) + +/* Register Bitfield Definitions ********************************************/ + +/* DMAMUX1 CxCR - request line multiplexer channel x configuration register */ + +#define DMAMUX_CCR_DMAREQID_SHIFT (0) /* Bits 0-6: DMA request identification */ +#define DMAMUX_CCR_DMAREQID_MASK (0x7f << DMAMUX_CCR_DMAREQID_SHIFT) +# define DMAMUX_CCR_DMAREQID(x) ((x) << DMAMUX_CCR_DMAREQID_SHIFT) +#define DMAMUX_CCR_SOIE (8) /* Bit 8: Synchronization overrun interrupt enable */ +#define DMAMUX_CCR_EGE (9) /* Bit 9: Event generation enable */ +#define DMAMUX_CCR_SE (16) /* Bit 16: Synchronization enable */ +#define DMAMUX_CCR_SPOL_SHIFT (17) /* Bits 17-18: Synchronization polarity */ +#define DMAMUX_CCR_SPOL_MASK (3 << DMAMUX_CCR_SPOL_SHIFT) +# define DMAMUX_CCR_SPOL_NONE (0x0 << DMAMUX_CCR_SPOL_SHIFT) /* No event: No trigger detection or generation */ +# define DMAMUX_CCR_SPOL_RISING (0x1 << DMAMUX_CCR_SPOL_SHIFT) /* Rising edge */ +# define DMAMUX_CCR_SPOL_FALLING (0x2 << DMAMUX_CCR_SPOL_SHIFT) /* Falling edge */ +# define DMAMUX_CCR_SPOL_BOTH (0x3 << DMAMUX_CCR_SPOL_SHIFT) /* Both rising and falling edges */ +#define DMAMUX_CCR_NBREQ_SHIFT (19) /* Bits 19-23: Number of DMA request - 1 to forward */ +#define DMAMUX_CCR_NBREQ_MASK (0x1f << DMAMUX_CCR_NBREQ_SHIFT) +#define DMAMUX_CCR_SYNCID_SHIFT (24) /* Bits 24-26: Synchronization identification */ +#define DMAMUX_CCR_SYNCID_MASK (7 << DMAMUX_CCR_SYNCID_SHIFT) + +/* DMAMUX1 CSR - request line multiplexer interrupt channel status register */ + +#define DMAMUX1_CSR_SOF(x) (1 << (x)) /* Synchronization overrun event flag */ + +/* DMAMUX1 CFR - request line multiplexer interrupt clear flag register */ + +#define DMAMUX1_CFR_SOF(x) (1 << (x)) /* Clear synchronization overrun event flag */ + +/* DMAMUX1 RGCR - request generator channel x configuration register */ + +#define DMAMUX_RGCR_SIGID_SHIFT (0) /* Bits 0-4: Signal identification */ +#define DMAMUX_RGCR_SIGID_MASK (0x1f << DMAMUX_RGCR_SIGID_SHIFT) +#define DMAMUX_RGCR_OIE (8) /* Bit 8: Trigger overrun interrupt enable */ +#define DMAMUX_RGCR_GE (16) /* Bit 16: DMA request generator channel X enable*/ +#define DMAMUX_RGCR_GPOL_SHIFT (17) /* Bits 17-18: DMA request generator trigger polarity */ +#define DMAMUX_RGCR_GPOL_MASK (0x3 << DMAMUX_RGCR_GPOL_SHIFT) +# define DMAMUX_RGCR_GPOL_NONE (0x0 << DMAMUX_RGCR_GPOL_SHIFT) /* No event: No trigger detection or generation */ +# define DMAMUX_RGCR_GPOL_RISING (0x1 << DMAMUX_RGCR_GPOL_SHIFT) /* Rising edge */ +# define DMAMUX_RGCR_GPOL_FALLING (0x2 << DMAMUX_RGCR_GPOL_SHIFT) /* Falling edge */ +# define DMAMUX_RGCR_GPOL_BOTH (0x3 << DMAMUX_RGCR_GPOL_SHIFT) /* Both rising and falling edges */ +#define DMAMUX_RGCR_GNBREQ_SHIFT (19) /* Bits 19-23: Number of DMA requests to be generated -1 */ +#define DMAMUX_RGCR_GNBREQ_MASK (0x1f << DMAMUX_RGCR_GNBREQ_SHIFT) + +/* DMAMUX1 RGSR - request generator interrupt status register */ + +#define DMAMUX1_RGSR_OF(x) (1 << (x)) /* Trigger overrun event flag */ + +/* DMAMUX1 RGCFR - request generator interrupt clear flag register */ + +#define DMAMUX1_RGCFR_COF(x) (1 << (x)) /* Clear trigger overrun event flag */ + +/* DMA channel mapping + * + * XXXXX.DDD.CCCCCCCC + * C - DMAMUX request + * D - DMA controller + * X - free bits + */ + +#define DMAMAP_MAP(d,c) ((d) << 8 | (c)) +#define DMAMAP_CONTROLLER(m) ((m) >> 8 & 0x07) +#define DMAMAP_REQUEST(m) ((m) >> 0 & 0xff) + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/* Import DMAMUX map */ + +#if defined(CONFIG_STM32_STM32G4XXX) +# include "hardware/stm32g4xxxx_dmamux.h" +#else +# error "Unsupported STM32 sub family" +#endif + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DMAMUX_16CH_H */ diff --git a/arch/arm/src/common/stm32/hardware/stm32_dmamux_7ch.h b/arch/arm/src/common/stm32/hardware/stm32_dmamux_7ch.h new file mode 100644 index 0000000000000..b7c36335c0add --- /dev/null +++ b/arch/arm/src/common/stm32/hardware/stm32_dmamux_7ch.h @@ -0,0 +1,162 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/hardware/stm32_dmamux_7ch.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DMAMUX_7CH_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DMAMUX_7CH_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include "chip.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define DMAMUX1 0 + +/* Register Offsets *********************************************************/ + +#define STM32_DMAMUX_CXCR_OFFSET(x) (0x0000+0x0004*(x)) /* DMAMUX1 request line multiplexer channel x configuration register */ +#define STM32_DMAMUX_C0CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(0) +#define STM32_DMAMUX_C1CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(1) +#define STM32_DMAMUX_C2CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(2) +#define STM32_DMAMUX_C3CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(3) +#define STM32_DMAMUX_C4CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(4) +#define STM32_DMAMUX_C5CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(5) +#define STM32_DMAMUX_C6CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(6) + /* 0x01C-0x07C: Reserved */ +#define STM32_DMAMUX_CSR_OFFSET 0x0080 /* DMAMUX1 request line multiplexer interrupt channel status register */ +#define STM32_DMAMUX_CFR_OFFSET 0x0084 /* DMAMUX1 request line multiplexer interrupt clear flag register */ + /* 0x088-0x0FC: Reserved */ +#define STM32_DMAMUX_RGXCR_OFFSET(x) (0x0100+0x004*(x)) /* DMAMUX1 request generator channel x configuration register */ +#define STM32_DMAMUX_RG0CR_OFFSET STM32_DMAMUX_RGXCR_OFFSET(0) +#define STM32_DMAMUX_RG1CR_OFFSET STM32_DMAMUX_RGXCR_OFFSET(1) +#define STM32_DMAMUX_RG2CR_OFFSET STM32_DMAMUX_RGXCR_OFFSET(2) +#define STM32_DMAMUX_RG3CR_OFFSET STM32_DMAMUX_RGXCR_OFFSET(3) +#define STM32_DMAMUX_RGSR_OFFSET 0x0140 /* DMAMUX1 request generator interrupt status register */ +#define STM32_DMAMUX_RGCFR_OFFSET 0x0144 /* DMAMUX1 request generator interrupt clear flag register */ + /* 0x148-0x3FC: Reserved */ + +/* Register Addresses *******************************************************/ + +#define STM32_DMAMUX1_CXCR(x) (STM32_DMAMUX1_BASE+STM32_DMAMUX_CXCR_OFFSET(x)) +#define STM32_DMAMUX1_C0CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_C0CR_OFFSET) +#define STM32_DMAMUX1_C1CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_C1CR_OFFSET) +#define STM32_DMAMUX1_C2CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_C2CR_OFFSET) +#define STM32_DMAMUX1_C3CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_C3CR_OFFSET) +#define STM32_DMAMUX1_C4CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_C4CR_OFFSET) +#define STM32_DMAMUX1_C5CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_C5CR_OFFSET) +#define STM32_DMAMUX1_C6CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_C6CR_OFFSET) + +#define STM32_DMAMUX1_CSR (STM32_DMAMUX1_BASE+STM32_DMAMUX_CSR_OFFSET) +#define STM32_DMAMUX1_CFR (STM32_DMAMUX1_BASE+STM32_DMAMUX_CFR_OFFSET) + +#define STM32_DMAMUX1_RGXCR(x) (STM32_DMAMUX1_BASE+STM32_DMAMUX_RGXCR_OFFSET(x)) +#define STM32_DMAMUX1_RG0CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_RG0CR_OFFSET) +#define STM32_DMAMUX1_RG1CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_RG1CR_OFFSET) +#define STM32_DMAMUX1_RG2CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_RG2CR_OFFSET) +#define STM32_DMAMUX1_RG3CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_RG3CR_OFFSET) + +#define STM32_DMAMUX1_RGSR (STM32_DMAMUX1_BASE+STM32_DMAMUX_RGSR_OFFSET) +#define STM32_DMAMUX1_RGCFR (STM32_DMAMUX1_BASE+STM32_DMAMUX_RGCFR_OFFSET) + +/* Register Bitfield Definitions ********************************************/ + +/* DMAMUX1 request line multiplexer channel x configuration register */ + +#define DMAMUX_CCR_DMAREQID_SHIFT (0) /* Bits 0-6: DMA request identification */ +#define DMAMUX_CCR_DMAREQID_MASK (0x7f << DMAMUX_CCR_DMAREQID_SHIFT) +#define DMAMUX_CCR_SOIE (8) /* Bit 8: Synchronization overrun interrupt enable */ +#define DMAMUX_CCR_EGE (9) /* Bit 9: Event generation enable */ +#define DMAMUX_CCR_SE (16) /* Bit 16: Synchronization enable */ +#define DMAMUX_CCR_SPOL_SHIFT (17) /* Bits 17-18: Synchronization polarity */ +#define DMAMUX_CCR_SPOL_MASK (0x3 << DMAMUX_CCR_SPOL_SHIFT) +# define DMAMUX_CCR_SPOL_NONE (0x0 << DMAMUX_CCR_SPOL_SHIFT) /* No event: No trigger detection or generation */ +# define DMAMUX_CCR_SPOL_RISING (0x1 << DMAMUX_CCR_SPOL_SHIFT) /* Rising edge */ +# define DMAMUX_CCR_SPOL_FALLING (0x2 << DMAMUX_CCR_SPOL_SHIFT) /* Falling edge */ +# define DMAMUX_CCR_SPOL_BOTH (0x3 << DMAMUX_CCR_SPOL_SHIFT) /* Both rising and falling edges */ +#define DMAMUX_CCR_NBREQ_SHIFT (19) /* Bits 19-23: Number of DMA request - 1 to forward */ +#define DMAMUX_CCR_NBREQ_MASK (0x1f << DMAMUX_CCR_NBREQ_SHIFT) +#define DMAMUX_CCR_SYNCID_SHIFT (24) /* Bits 24-28: Synchronization identification */ +#define DMAMUX_CCR_SYNCID_MASK (0x1f << DMAMUX_CCR_SYNCID_SHIFT) + +/* DMAMUX1 request line multiplexer interrupt channel status register */ + +#define DMAMUX1_CSR_SOF(x) (1 << (x)) /* Synchronization overrun event flag */ + +/* DMAMUX1 request line multiplexer interrupt clear flag register */ + +#define DMAMUX1_CFR_CSOF(x) (1 << (x)) /* Clear synchronization overrun event flag */ + +/* DMAMUX1 request generator channel x configuration register */ + +#define DMAMUX_RGCR_SIGID_SHIFT (0) /* Bits 0-4: Signal identification */ +#define DMAMUX_RGCR_SIGID_MASK (0x1f << DMAMUX_RGCR_SIGID_SHIFT) +#define DMAMUX_RGCR_OIE (8) /* Bit 8: Trigger overrun interrupt enable */ +#define DMAMUX_RGCR_GE (16) /* Bit 16: DMA request generator channel X enable*/ +#define DMAMUX_RGCR_GPOL_SHIFT (17) /* Bits 17-18: DMA request generator trigger polarity */ +#define DMAMUX_RGCR_GPOL_MASK (0x3 << DMAMUX_RGCR_GPOL_SHIFT) +# define DMAMUX_RGCR_GPOL_NONE (0x0 << DMAMUX_RGCR_GPOL_SHIFT) /* No event: No trigger detection or generation */ +# define DMAMUX_RGCR_GPOL_RISING (0x1 << DMAMUX_RGCR_GPOL_SHIFT) /* Rising edge */ +# define DMAMUX_RGCR_GPOL_FALLING (0x2 << DMAMUX_RGCR_GPOL_SHIFT) /* Falling edge */ +# define DMAMUX_RGCR_GPOL_BOTH (0x3 << DMAMUX_RGCR_GPOL_SHIFT) /* Both rising and falling edges */ +#define DMAMUX_RGCR_GNBREQ_SHIFT (19) /* Bits 19-23: Number of DMA requests to be generated -1 */ +#define DMAMUX_RGCR_GNBREQL_MASK (0x1f << DMAMUX_RGCR_GNBREQ_SHIFT) + +/* DMAMUX1 request generator interrupt status register */ + +#define DMAMUX1_RGSR_OF(x) (1 << (x)) /* Trigger overrun event flag */ + +/* DMAMUX1 request generator interrupt clear flag register */ + +#define DMAMUX1_RGCFR_COF(x) (1 << (x)) /* Clear trigger overrun event flag */ + +/* DMA channel mapping + * + * XXXXX.DDD.CCCCCCCC + * C - DMAMUX request + * D - DMA controller + * X - free bits + */ + +#define DMAMAP_MAP(d,c) ((d) << 8 | (c)) +#define DMAMAP_CONTROLLER(m) ((m) >> 8 & 0x07) +#define DMAMAP_REQUEST(m) ((m) >> 0 & 0xff) + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/* Import DMAMUX map */ + +#if defined(CONFIG_STM32_STM32G0) +# include "hardware/stm32g0_dmamux.h" +#elif defined(CONFIG_STM32_STM32C0) +# include "hardware/stm32c0_dmamux.h" +#else +# error "Unsupported STM32 M0 sub family" +#endif + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DMAMUX_7CH_H */ diff --git a/arch/arm/src/common/stm32/hardware/stm32_eth.h b/arch/arm/src/common/stm32/hardware/stm32_eth.h new file mode 100644 index 0000000000000..1d02920541ce2 --- /dev/null +++ b/arch/arm/src/common/stm32/hardware/stm32_eth.h @@ -0,0 +1,877 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/hardware/stm32_eth.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_ETH_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_ETH_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "chip.h" + +#if STM32_NETHERNET > 0 + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Register Offsets *********************************************************/ + +/* MAC Registers */ + +#define STM32_ETH_MACCR_OFFSET 0x0000 /* Ethernet MAC configuration register */ +#define STM32_ETH_MACFFR_OFFSET 0x0004 /* Ethernet MAC frame filter register */ +#define STM32_ETH_MACHTHR_OFFSET 0x0008 /* Ethernet MAC hash table high register */ +#define STM32_ETH_MACHTLR_OFFSET 0x000c /* Ethernet MAC hash table low register */ +#define STM32_ETH_MACMIIAR_OFFSET 0x0010 /* Ethernet MAC MII address register */ +#define STM32_ETH_MACMIIDR_OFFSET 0x0014 /* Ethernet MAC MII data register */ +#define STM32_ETH_MACFCR_OFFSET 0x0018 /* Ethernet MAC flow control register */ +#define STM32_ETH_MACVLANTR_OFFSET 0x001c /* Ethernet MAC VLAN tag register */ +#define STM32_ETH_MACRWUFFR_OFFSET 0x0028 /* Ethernet MAC remote wakeup frame filter reg */ +#define STM32_ETH_MACPMTCSR_OFFSET 0x002c /* Ethernet MAC PMT control and status register */ +#if defined(CONFIG_STM32_HAVE_IP_ETHMAC_M3M4_V1) +# define STM32_ETH_MACDBGR_OFFSET 0x0034 /* Ethernet MAC debug register */ +#endif +#define STM32_ETH_MACSR_OFFSET 0x0038 /* Ethernet MAC interrupt status register */ +#define STM32_ETH_MACIMR_OFFSET 0x003c /* Ethernet MAC interrupt mask register */ +#define STM32_ETH_MACA0HR_OFFSET 0x0040 /* Ethernet MAC address 0 high register */ +#define STM32_ETH_MACA0LR_OFFSET 0x0044 /* Ethernet MAC address 0 low register */ +#define STM32_ETH_MACA1HR_OFFSET 0x0048 /* Ethernet MAC address 1 high register */ +#define STM32_ETH_MACA1LR_OFFSET 0x004c /* Ethernet MAC address1 low register */ +#define STM32_ETH_MACA2HR_OFFSET 0x0050 /* Ethernet MAC address 2 high register */ +#define STM32_ETH_MACA2LR_OFFSET 0x0054 /* Ethernet MAC address 2 low register */ +#define STM32_ETH_MACA3HR_OFFSET 0x0058 /* Ethernet MAC address 3 high register */ +#define STM32_ETH_MACA3LR_OFFSET 0x005c /* Ethernet MAC address 3 low register */ + +/* MMC Registers */ + +#define STM32_ETH_MMCCR_OFFSET 0x0100 /* Ethernet MMC control register */ +#define STM32_ETH_MMCRIR_OFFSET 0x0104 /* Ethernet MMC receive interrupt register */ +#define STM32_ETH_MMCTIR_OFFSET 0x0108 /* Ethernet MMC transmit interrupt register */ +#define STM32_ETH_MMCRIMR_OFFSET 0x010c /* Ethernet MMC receive interrupt mask register */ +#define STM32_ETH_MMCTIMR_OFFSET 0x0110 /* Ethernet MMC transmit interrupt mask register */ +#define STM32_ETH_MMCTGFSCCR_OFFSET 0x014c /* Ethernet MMC transmitted good frames counter register (single collision) */ +#define STM32_ETH_MMCTGFMSCCR_OFFSET 0x0150 /* Ethernet MMC transmitted good frames counter register (multiple-collision) */ +#define STM32_ETH_MMCTGFCR_OFFSET 0x0168 /* Ethernet MMC transmitted good frames counter register */ +#define STM32_ETH_MMCRFCECR_OFFSET 0x0194 /* Ethernet MMC received frames with CRC error counter register */ +#define STM32_ETH_MMCRFAECR_OFFSET 0x0198 /* Ethernet MMC received frames with alignment error counter */ +#define STM32_ETH_MMCRGUFCR_OFFSET 0x01c4 /* MMC received good unicast frames counter register */ + +/* IEEE 1588 time stamp registers */ + +#define STM32_ETH_PTPTSCR_OFFSET 0x0700 /* Ethernet PTP time stamp control register */ +#define STM32_ETH_PTPSSIR_OFFSET 0x0704 /* Ethernet PTP subsecond increment register */ +#define STM32_ETH_PTPTSHR_OFFSET 0x0708 /* Ethernet PTP time stamp high register */ +#define STM32_ETH_PTPTSLR_OFFSET 0x070c /* Ethernet PTP time stamp low register */ +#define STM32_ETH_PTPTSHUR_OFFSET 0x0710 /* Ethernet PTP time stamp high update register */ +#define STM32_ETH_PTPTSLUR_OFFSET 0x0714 /* Ethernet PTP time stamp low update register */ +#define STM32_ETH_PTPTSAR_OFFSET 0x0718 /* Ethernet PTP time stamp addend register */ +#define STM32_ETH_PTPTTHR_OFFSET 0x071c /* Ethernet PTP target time high register */ +#define STM32_ETH_PTPTTLR_OFFSET 0x0720 /* Ethernet PTP target time low register */ +#define STM32_ETH_PTPTSSR_OFFSET 0x0728 /* Ethernet PTP time stamp status register */ +#define STM32_ETH_PTPPPSCR_OFFSET 0x072c /* Ethernet PTP PPS control register */ + +/* DMA Registers */ + +#define STM32_ETH_DMABMR_OFFSET 0x1000 /* Ethernet DMA bus mode register */ +#define STM32_ETH_DMATPDR_OFFSET 0x1004 /* Ethernet DMA transmit poll demand register */ +#define STM32_ETH_DMARPDR_OFFSET 0x1008 /* Ethernet DMA receive poll demand register */ +#define STM32_ETH_DMARDLAR_OFFSET 0x100c /* Ethernet DMA receive descriptor list address register */ +#define STM32_ETH_DMATDLAR_OFFSET 0x1010 /* Ethernet DMA transmit descriptor list address register */ +#define STM32_ETH_DMASR_OFFSET 0x1014 /* Ethernet DMA status register */ +#define STM32_ETH_DMAOMR_OFFSET 0x1018 /* Ethernet DMA operation mode register */ +#define STM32_ETH_DMAIER_OFFSET 0x101c /* Ethernet DMA interrupt enable register */ +#define STM32_ETH_DMAMFBOC_OFFSET 0x1020 /* Ethernet DMA missed frame and buffer overflow counter register */ +#define STM32_ETH_DMARSWTR_OFFSET 0x1024 /* Ethernet DMA receive status watchdog timer register */ +#define STM32_ETH_DMACHTDR_OFFSET 0x1048 /* Ethernet DMA current host transmit descriptor register */ +#define STM32_ETH_DMACHRDR_OFFSET 0x104c /* Ethernet DMA current host receive descriptor register */ +#define STM32_ETH_DMACHTBAR_OFFSET 0x1050 /* Ethernet DMA current host transmit buffer address register */ +#define STM32_ETH_DMACHRBAR_OFFSET 0x1054 /* Ethernet DMA current host receive buffer address register */ + +/* Register Base Addresses **************************************************/ + +/* MAC Registers */ + +#define STM32_ETH_MACCR (STM32_ETHERNET_BASE+STM32_ETH_MACCR_OFFSET) +#define STM32_ETH_MACFFR (STM32_ETHERNET_BASE+STM32_ETH_MACFFR_OFFSET) +#define STM32_ETH_MACHTHR (STM32_ETHERNET_BASE+STM32_ETH_MACHTHR_OFFSET) +#define STM32_ETH_MACHTLR (STM32_ETHERNET_BASE+STM32_ETH_MACHTLR_OFFSET) +#define STM32_ETH_MACMIIAR (STM32_ETHERNET_BASE+STM32_ETH_MACMIIAR_OFFSET) +#define STM32_ETH_MACMIIDR (STM32_ETHERNET_BASE+STM32_ETH_MACMIIDR_OFFSET) +#define STM32_ETH_MACFCR (STM32_ETHERNET_BASE+STM32_ETH_MACFCR_OFFSET) +#define STM32_ETH_MACVLANTR (STM32_ETHERNET_BASE+STM32_ETH_MACVLANTR_OFFSET) +#define STM32_ETH_MACRWUFFR (STM32_ETHERNET_BASE+STM32_ETH_MACRWUFFR_OFFSET) +#define STM32_ETH_MACPMTCSR (STM32_ETHERNET_BASE+STM32_ETH_MACPMTCSR_OFFSET) +#if defined(CONFIG_STM32_HAVE_IP_ETHMAC_M3M4_V1) +# define STM32_ETH_MACDBGR (STM32_ETHERNET_BASE+STM32_ETH_MACDBGR_OFFSET) +#endif +#define STM32_ETH_MACSR (STM32_ETHERNET_BASE+STM32_ETH_MACSR_OFFSET) +#define STM32_ETH_MACIMR (STM32_ETHERNET_BASE+STM32_ETH_MACIMR_OFFSET) +#define STM32_ETH_MACA0HR (STM32_ETHERNET_BASE+STM32_ETH_MACA0HR_OFFSET) +#define STM32_ETH_MACA0LR (STM32_ETHERNET_BASE+STM32_ETH_MACA0LR_OFFSET) +#define STM32_ETH_MACA1HR (STM32_ETHERNET_BASE+STM32_ETH_MACA1HR_OFFSET) +#define STM32_ETH_MACA1LR (STM32_ETHERNET_BASE+STM32_ETH_MACA1LR_OFFSET) +#define STM32_ETH_MACA2HR (STM32_ETHERNET_BASE+STM32_ETH_MACA2HR_OFFSET) +#define STM32_ETH_MACA2LR (STM32_ETHERNET_BASE+STM32_ETH_MACA2LR_OFFSET) +#define STM32_ETH_MACA3HR (STM32_ETHERNET_BASE+STM32_ETH_MACA3HR_OFFSET) +#define STM32_ETH_MACA3LR (STM32_ETHERNET_BASE+STM32_ETH_MACA3LR_OFFSET) + +/* MMC Registers */ + +#define STM32_ETH_MMCC (STM32_ETHERNET_BASE+STM32_ETH_MMCCR_OFFSET) +#define STM32_ETH_MMCRIR (STM32_ETHERNET_BASE+STM32_ETH_MMCRIR_OFFSET) +#define STM32_ETH_MMCTIR (STM32_ETHERNET_BASE+STM32_ETH_MMCTIR_OFFSET) +#define STM32_ETH_MMCRIMR (STM32_ETHERNET_BASE+STM32_ETH_MMCRIMR_OFFSET) +#define STM32_ETH_MMCTIMR (STM32_ETHERNET_BASE+STM32_ETH_MMCTIMR_OFFSET) +#define STM32_ETH_MMCTGFSCCR (STM32_ETHERNET_BASE+STM32_ETH_MMCTGFSCCR_OFFSET) +#define STM32_ETH_MMCTGFMSCCR (STM32_ETHERNET_BASE+STM32_ETH_MMCTGFMSCCR_OFFSET) +#define STM32_ETH_MMCTGFCR (STM32_ETHERNET_BASE+STM32_ETH_MMCTGFCR_OFFSET) +#define STM32_ETH_MMCRFCECR (STM32_ETHERNET_BASE+STM32_ETH_MMCRFCECR_OFFSET) +#define STM32_ETH_MMCRFAECR (STM32_ETHERNET_BASE+STM32_ETH_MMCRFAECR_OFFSET) +#define STM32_ETH_MMCRGUFCR (STM32_ETHERNET_BASE+STM32_ETH_MMCRGUFCR_OFFSET) + +/* IEEE 1588 time stamp registers */ + +#define STM32_ETH_PTPTSCR (STM32_ETHERNET_BASE+STM32_ETH_PTPTSCR_OFFSET) +#define STM32_ETH_PTPSSIR (STM32_ETHERNET_BASE+STM32_ETH_PTPSSIR_OFFSET) +#define STM32_ETH_PTPTSHR (STM32_ETHERNET_BASE+STM32_ETH_PTPTSHR_OFFSET) +#define STM32_ETH_PTPTSLR (STM32_ETHERNET_BASE+STM32_ETH_PTPTSLR_OFFSET) +#define STM32_ETH_PTPTSHUR (STM32_ETHERNET_BASE+STM32_ETH_PTPTSHUR_OFFSET) +#define STM32_ETH_PTPTSLUR (STM32_ETHERNET_BASE+STM32_ETH_PTPTSLUR_OFFSET) +#define STM32_ETH_PTPTSAR (STM32_ETHERNET_BASE+STM32_ETH_PTPTSAR_OFFSET) +#define STM32_ETH_PTPTTHR (STM32_ETHERNET_BASE+STM32_ETH_PTPTTHR_OFFSET) +#define STM32_ETH_PTPTTLR (STM32_ETHERNET_BASE+STM32_ETH_PTPTTLR_OFFSET) +#define STM32_ETH_PTPTSSR (STM32_ETHERNET_BASE+STM32_ETH_PTPTSSR_OFFSET) +#define STM32_ETH_PTPPPSCR (STM32_ETHERNET_BASE+STM32_ETH_PTPPPSCR_OFFSET) + +/* DMA Registers */ + +#define STM32_ETH_DMABMR (STM32_ETHERNET_BASE+STM32_ETH_DMABMR_OFFSET) +#define STM32_ETH_DMATPDR (STM32_ETHERNET_BASE+STM32_ETH_DMATPDR_OFFSET) +#define STM32_ETH_DMARPDR (STM32_ETHERNET_BASE+STM32_ETH_DMARPDR_OFFSET) +#define STM32_ETH_DMARDLAR (STM32_ETHERNET_BASE+STM32_ETH_DMARDLAR_OFFSET) +#define STM32_ETH_DMATDLAR (STM32_ETHERNET_BASE+STM32_ETH_DMATDLAR_OFFSET) +#define STM32_ETH_DMASR (STM32_ETHERNET_BASE+STM32_ETH_DMASR_OFFSET) +#define STM32_ETH_DMAOMR (STM32_ETHERNET_BASE+STM32_ETH_DMAOMR_OFFSET) +#define STM32_ETH_DMAIER (STM32_ETHERNET_BASE+STM32_ETH_DMAIER_OFFSET) +#define STM32_ETH_DMAMFBOC (STM32_ETHERNET_BASE+STM32_ETH_DMAMFBOC_OFFSET) +#define STM32_ETH_DMARSWTR (STM32_ETHERNET_BASE+STM32_ETH_DMARSWTR_OFFSET) +#define STM32_ETH_DMACHTDR (STM32_ETHERNET_BASE+STM32_ETH_DMACHTDR_OFFSET) +#define STM32_ETH_DMACHRDR (STM32_ETHERNET_BASE+STM32_ETH_DMACHRDR_OFFSET) +#define STM32_ETH_DMACHTBAR (STM32_ETHERNET_BASE+STM32_ETH_DMACHTBAR_OFFSET) +#define STM32_ETH_DMACHRBAR (STM32_ETHERNET_BASE+STM32_ETH_DMACHRBAR_OFFSET) + +/* Register Bit-Field Definitions *******************************************/ + +/* MAC Registers */ + +/* Ethernet MAC configuration register */ + +#define ETH_MACCR_RE (1 << 2) /* Bit 2: Receiver enable */ +#define ETH_MACCR_TE (1 << 3) /* Bit 3: Transmitter enable */ +#define ETH_MACCR_DC (1 << 4) /* Bit 4: Deferral check */ +#define ETH_MACCR_BL_SHIFT (5) /* Bits 5-6: Back-off limit */ +#define ETH_MACCR_BL_MASK (3 << ETH_MACCR_BL_SHIFT) +# define ETH_MACCR_BL_10 (0 << ETH_MACCR_BL_SHIFT) /* 00: k = min (n, 10) */ +# define ETH_MACCR_BL_8 (1 << ETH_MACCR_BL_SHIFT) /* 01: k = min (n, 8) */ +# define ETH_MACCR_BL_4 (2 << ETH_MACCR_BL_SHIFT) /* 10: k = min (n, 4) */ +# define ETH_MACCR_BL_1 (3 << ETH_MACCR_BL_SHIFT) /* 11: k = min (n, 1) */ + +#define ETH_MACCR_APCS (1 << 7) /* Bit 7: Automatic pad/CRC stripping */ +#define ETH_MACCR_RD (1 << 9) /* Bit 9: Retry disable */ +#define ETH_MACCR_IPCO (1 << 10) /* Bit 10: IPv4 checksum offload */ +#define ETH_MACCR_DM (1 << 11) /* Bit 11: Duplex mode */ +#define ETH_MACCR_LM (1 << 12) /* Bit 12: Loopback mode */ +#define ETH_MACCR_ROD (1 << 13) /* Bit 13: Receive own disable */ +#define ETH_MACCR_FES (1 << 14) /* Bit 14: Fast Ethernet speed */ +#define ETH_MACCR_CSD (1 << 16) /* Bit 16: Carrier sense disable */ +#define ETH_MACCR_IFG_SHIFT (17) /* Bits 17-19: Interframe gap */ +#define ETH_MACCR_IFG_MASK (7 << ETH_MACCR_IFG_SHIFT) +# define ETH_MACCR_IFG(n) ((12-((n) >> 3)) << ETH_MACCR_IFG_SHIFT) /* n bit times, n=40,48,..96 */ + +#define ETH_MACCR_JD (1 << 22) /* Bit 22: Jabber disable */ +#define ETH_MACCR_WD (1 << 23) /* Bit 23: Watchdog disable */ +#if defined(CONFIG_STM32_HAVE_IP_ETHMAC_M3M4_V1) +# define ETH_MACCR_CSTF (1 << 25) /* Bits 25: CRC stripping for Type frames */ +#endif + +/* Ethernet MAC frame filter register */ + +#define ETH_MACFFR_PM (1 << 0) /* Bit 0: Promiscuous mode */ +#define ETH_MACFFR_HU (1 << 1) /* Bit 1: Hash unicast */ +#define ETH_MACFFR_HM (1 << 2) /* Bit 2: Hash multicast */ +#define ETH_MACFFR_DAIF (1 << 3) /* Bit 3: Destination address inverse filtering */ +#define ETH_MACFFR_PAM (1 << 4) /* Bit 4: Pass all multicast */ +#define ETH_MACFFR_BFD (1 << 5) /* Bit 5: Broadcast frames disable */ +#define ETH_MACFFR_PCF_SHIFT (6) /* Bits 6-7: Pass control frames */ +#define ETH_MACFFR_PCF_MASK (3 << ETH_MACFFR_PCF_SHIFT) +# define ETH_MACFFR_PCF_NONE (0 << ETH_MACFFR_PCF_SHIFT) /* Prevents all control frames */ +# define ETH_MACFFR_PCF_PAUSE (1 << ETH_MACFFR_PCF_SHIFT) /* Prevents all except Pause control frames */ +# define ETH_MACFFR_PCF_ALL (2 << ETH_MACFFR_PCF_SHIFT) /* Forwards all control frames */ +# define ETH_MACFFR_PCF_FILTER (3 << ETH_MACFFR_PCF_SHIFT) /* Forwards all that pass address filter */ + +#define ETH_MACFFR_SAIF (1 << 8) /* Bit 8: Source address inverse filtering */ +#define ETH_MACFFR_SAF (1 << 9) /* Bit 9: Source address filter */ +#define ETH_MACFFR_HPF (1 << 10) /* Bit 10: Hash or perfect filter */ +#define ETH_MACFFR_RA (1 << 31) /* Bit 31: Receive all */ + +/* Ethernet MAC hash table high/low registers (32-bit values) */ + +/* Ethernet MAC MII address register */ + +#define ETH_MACMIIAR_MB (1 << 0) /* Bit 0: MII busy */ +#define ETH_MACMIIAR_MW (1 << 1) /* Bit 1: MII write */ +#define ETH_MACMIIAR_CR_SHIFT (2) /* Bits 2-4: Clock range */ +#define ETH_MACMIIAR_CR_MASK (7 << ETH_MACMIIAR_CR_SHIFT) +#if 0 /* Per the reference manual */ +# define ETH_MACMIIAR_CR_60_100 (0 << ETH_MACMIIAR_CR_SHIFT) /* 000 60-100 MHzHCLK/42 */ +# define ETH_MACMIIAR_CR_100_168 (1 << ETH_MACMIIAR_CR_SHIFT) /* 001 100-168 MHz HCLK/62 */ +# define ETH_MACMIIAR_CR_20_35 (2 << ETH_MACMIIAR_CR_SHIFT) /* 010 20-35 MHz HCLK/16 */ +# define ETH_MACMIIAR_CR_35_60 (3 << ETH_MACMIIAR_CR_SHIFT) /* 011 35-60 MHz HCLK/26 */ +#else /* Per the driver example */ +# define ETH_MACMIIAR_CR_60_100 (0 << ETH_MACMIIAR_CR_SHIFT) /* 000 60-100 MHz HCLK/42 */ +# define ETH_MACMIIAR_CR_100_150 (1 << ETH_MACMIIAR_CR_SHIFT) /* 001 100-150 MHz HCLK/62 */ +# define ETH_MACMIIAR_CR_20_35 (2 << ETH_MACMIIAR_CR_SHIFT) /* 010 20-35 MHz HCLK/16 */ +# define ETH_MACMIIAR_CR_35_60 (3 << ETH_MACMIIAR_CR_SHIFT) /* 011 35-60 MHz HCLK/26 */ +# define ETH_MACMIIAR_CR_150_180 (4 << ETH_MACMIIAR_CR_SHIFT) /* 100 150-180 MHz HCLK/102 */ +#endif +#define ETH_MACMIIAR_MR_SHIFT (6) /* Bits 6-10: MII register */ +#define ETH_MACMIIAR_MR_MASK (31 << ETH_MACMIIAR_MR_SHIFT) +#define ETH_MACMIIAR_PA_SHIFT (11) /* Bits 11-15: PHY address */ +#define ETH_MACMIIAR_PA_MASK (31 << ETH_MACMIIAR_PA_SHIFT) + +/* Ethernet MAC MII data register */ + +#define ETH_MACMIIDR_MASK (0xffff) + +/* Ethernet MAC flow control register */ + +#define ETH_MACFCR_FCB_BPA (1 << 0) /* Bit 0: Flow control busy/back pressure activate */ +#define ETH_MACFCR_TFCE (1 << 1) /* Bit 1: Transmit flow control enable */ +#define ETH_MACFCR_RFCE (1 << 2) /* Bit 2: Receive flow control enable */ +#define ETH_MACFCR_UPFD (1 << 3) /* Bit 3: Unicast pause frame detect */ +#define ETH_MACFCR_PLT_SHIFT (4) /* Bits 4-5: Pause low threshold */ +#define ETH_MACFCR_PLT_MASK (3 << ETH_MACFCR_PLT_SHIFT) +# define ETH_MACFCR_PLT_M4 (0 << ETH_MACFCR_PLT_SHIFT) /* 00 Pause - 4 slot times */ +# define ETH_MACFCR_PLT_M28 (1 << ETH_MACFCR_PLT_SHIFT) /* 01 Pause - 28 slot times */ +# define ETH_MACFCR_PLT_M144 (2 << ETH_MACFCR_PLT_SHIFT) /* 10 Pause - 144 slot times */ +# define ETH_MACFCR_PLT_M256 (3 << ETH_MACFCR_PLT_SHIFT) /* 11 Pause -s 256 slot times */ + +#define ETH_MACFCR_ZQPD (1 << 7) /* Bit 7: Zero-quanta pause disable */ +#define ETH_MACFCR_PT_SHIFT (16) /* Bits 16-31: Pause time */ +#define ETH_MACFCR_PT_MASK (0xffff << ETH_MACFCR_PT_SHIFT) + +/* Ethernet MAC VLAN tag register */ + +#define ETH_MACVLANTR_VLANTI_SHIFT (0) /* Bits 0-15: VLAN tag identifier (for receive frames) */ +#define ETH_MACVLANTR_VLANTI_MASK (0xffff << ETH_MACVLANTR_VLANTI_SHIFT) +#define ETH_MACVLANTR_VLANTC (1 << 16) /* Bit 16: 12-bit VLAN tag comparison */ + +/* Ethernet MAC remote wakeup frame filter reg. Provides 32-bit access to + * remote remote wake-up filters. + */ + +/* Ethernet MAC PMT control and status register */ + +#define ETH_MACPMTCSR_PD (1 << 0) /* Bit 0: Power down */ +#define ETH_MACPMTCSR_MPE (1 << 1) /* Bit 1: Magic Packet enable */ +#define ETH_MACPMTCSR_WFE (1 << 2) /* Bit 2: Wakeup frame enable */ +#define ETH_MACPMTCSR_MPR (1 << 5) /* Bit 5: Magic packet received */ +#define ETH_MACPMTCSR_WFR (1 << 6) /* Bit 6: Wakeup frame received */ +#define ETH_MACPMTCSR_GU (1 << 9) /* Bit 9: Global unicast */ + +/* Ethernet MAC debug register */ + +#if defined(CONFIG_STM32_HAVE_IP_ETHMAC_M3M4_V1) + +#define ETH_MACDBGR_MMRPEA (1 << 0) /* Bit 0: MAC MII receive protocol engine active */ +#define ETH_MACDBGR_MSFRWCS_SHIFT (1) /* Bits 1-2: MAC small FIFO read / write controllers status */ +#define ETH_MACDBGR_MSFRWCS_MASK (3 << ETH_MACDBGR_MSFRWCS_SHIFT) + +#define ETH_MACDBGR_RFWRA (1 << 4) /* Bit 4: Rx FIFO write controller active */ +#define ETH_MACDBGR_RFRCS_SHIFT (5) /* Bits 5-6: Rx FIFO read controller status */ +#define ETH_MACDBGR_RFRCS_MASK (3 << ETH_MACDBGR_RFRCS_SHIFT) +# define ETH_MACDBGR_RFRCS_IDLE (0 << ETH_MACDBGR_RFRCS_SHIFT) /* 00: IDLE state */ +# define ETH_MACDBGR_RFRCS_RFRAME (1 << ETH_MACDBGR_RFRCS_SHIFT) /* 01: Reading frame data */ +# define ETH_MACDBGR_RFRCS_RSTATUS (2 << ETH_MACDBGR_RFRCS_SHIFT) /* 10: Reading frame status (or time-stamp) */ +# define ETH_MACDBGR_RFRCS_FLUSHING (3 << ETH_MACDBGR_RFRCS_SHIFT) /* 11: Flushing the frame data and status */ + +#define ETH_MACDBGR_RFFL_SHIFT (8) /* Bits 8-9: Rx FIFO fill level */ +#define ETH_MACDBGR_RFFL_MASK (3 << ETH_MACDBGR_RFFL_SHIFT) +# define ETH_MACDBGR_RFFL_EMPTY (0 << ETH_MACDBGR_RFFL_SHIFT) /* 00: RxFIFO empty */ +# define ETH_MACDBGR_RFFL_DEACT (1 << ETH_MACDBGR_RFFL_SHIFT) /* 01: RxFIFO fill-level below flow-control de-activate threshold */ +# define ETH_MACDBGR_RFFL_ACTIV (2 << ETH_MACDBGR_RFFL_SHIFT) /* 10: RxFIFO fill-level above flow-control activate threshold */ +# define ETH_MACDBGR_RFFL_FULL (3 << ETH_MACDBGR_RFFL_SHIFT) /* 11: RxFIFO full */ + +#define ETH_MACDBGR_MMTEA (1 << 16) /* Bit 16: MAC MII transmit engine active */ +#define ETH_MACDBGR_MTFCS_SHIFT (17) /* Bits 17-18: MAC transmit frame controller status */ +#define ETH_MACDBGR_MTFCS_MASK (3 << ETH_MACDBGR_MTFCS_SHIFT) +# define ETH_MACDBGR_MTFCS_IDLE (0 << ETH_MACDBGR_MTFCS_SHIFT) /* 00: Idle */ +# define ETH_MACDBGR_MTFCS_WAITING (1 << ETH_MACDBGR_MTFCS_SHIFT) /* 01: Waiting for Status of previous frame or IFG/backoff period to be over */ +# define ETH_MACDBGR_MTFCS_PAUSE (2 << ETH_MACDBGR_MTFCS_SHIFT) /* 10: Generating and transmitting a Pause control frame */ +# define ETH_MACDBGR_MTFCS_FRAME (3 << ETH_MACDBGR_MTFCS_SHIFT) /* 11: Transferring input frame for transmission */ + +#define ETH_MACDBGR_MTP (1 << 19) /* Bit 19: MAC transmitter in pause */ +#define ETH_MACDBGR_TFRS_SHIFT (20) /* Bits 20-21: Tx FIFO read status */ +#define ETH_MACDBGR_TFRS_MASK (3 << ETH_MACDBGR_TFRS_SHIFT) +# define ETH_MACDBGR_TFRS_IDLE (0 << ETH_MACDBGR_TFRS_SHIFT) /* 00: Idle state */ +# define ETH_MACDBGR_TFRS_READ (1 << ETH_MACDBGR_TFRS_SHIFT) /* 01: Read state */ +# define ETH_MACDBGR_TFRS_WAITING (2 << ETH_MACDBGR_TFRS_SHIFT) /* 10: Waiting for TxStatus from MAC transmitter */ +# define ETH_MACDBGR_TFRS_WRITING (3 << ETH_MACDBGR_TFRS_SHIFT) /* 11: Writing the received TxStatus or flushing the TxFIFO */ + +#define ETH_MACDBGR_TFWA (1 << 22) /* Bit 22: Tx FIFO write active */ +#define ETH_MACDBGR_TFNE (1 << 24) /* Bit 24: Tx FIFO not empty */ +#define ETH_MACDBGR_TFF (1 << 25) /* Bit 25: Tx FIFO full */ + +#endif + +/* Ethernet MAC interrupt status register */ + +#define ETH_MACSR_PMTS (1 << 3) /* Bit 3: PMT status */ +#define ETH_MACSR_MMCS (1 << 4) /* Bit 4: MMC status */ +#define ETH_MACSR_MMCRS (1 << 5) /* Bit 5: MMC receive status */ +#define ETH_MACSR_MMCTS (1 << 6) /* Bit 6: MMC transmit status */ +#define ETH_MACSR_TSTS (1 << 9) /* Bit 9: Time stamp trigger status */ + +/* Ethernet MAC interrupt mask register */ + +#define ETH_MACIMR_PMTIM (1 << 3) /* Bit 3: PMT interrupt mask */ +#define ETH_MACIMR_TSTIM (1 << 9) /* Bit 9: Time stamp trigger interrupt mask */ +#define ETH_MACIMR_ALLINTS (ETH_MACIMR_PMTIM|ETH_MACIMR_TSTIM) + +/* Ethernet MAC address 0 high register */ + +#define ETH_MACA0HR_MACA0H_SHIFT (0) /* Bits 0-15: MAC address0 high [47:32] */ +#define ETH_MACA0HR_MACA0H_MASK (0xffff << ETH_MACA0HR_MACA0H_SHIFT) +#define ETH_MACA0HR_MO (1 << 31) /* Bit 31:Always */ + +/* Ethernet MAC address 0 low register (MAC address0 low [31:0]) */ + +/* Ethernet MAC address 1 high register */ + +#define ETH_MACA1HR_MACA1H_SHIFT (0) /* Bits 0-15: MAC address1 high [47:32] */ +#define ETH_MACA1HR_MACA1H_MASK (0xffff << ETH_MACA1HR_MACA1H_SHIFT) +#define ETH_MACA1HR_MBC_SHIFT (24) /* Bits 24-29: Mask byte control */ +#define ETH_MACA1HR_MBC_MASK (0x3f << ETH_MACA1HR_MBC_SHIFT) +# define ETH_MACA1HR_MBC_40_47 (0x20 << ETH_MACA1HR_MBC_SHIFT) /* Bit 29: ETH_MACA1HR [8-15] */ +# define ETH_MACA1HR_MBC_32_39 (0x10 << ETH_MACA1HR_MBC_SHIFT) /* Bit 28: ETH_MACA1HR [0-7] */ +# define ETH_MACA1HR_MBC_24_31 (0x08 << ETH_MACA1HR_MBC_SHIFT) /* Bit 27: ETH_MACA1LR [24-31] */ +# define ETH_MACA1HR_MBC_16_23 (0x04 << ETH_MACA1HR_MBC_SHIFT) /* Bit 26: ETH_MACA1LR [16-23] */ +# define ETH_MACA1HR_MBC_8_15 (0x02 << ETH_MACA1HR_MBC_SHIFT) /* Bit 25: ETH_MACA1LR [8-15] */ +# define ETH_MACA1HR_MBC_0_7 (0x01 << ETH_MACA1HR_MBC_SHIFT) /* Bit 24: ETH_MACA1LR [0-7] */ + +#define ETH_MACA1HR_SA (1 << 30) /* Bit 30: Source address */ +#define ETH_MACA1HR_AE (1 << 31) /* Bit 31: Address enable */ + +/* Ethernet MAC address1 low register (MAC address1 low [31:0]) */ + +/* Ethernet MAC address 2 high register */ + +#define ETH_MACA2HR_MACA2H_SHIFT (0) /* Bits 0-15: MAC address2 high [47:32] */ +#define ETH_MACA2HR_MACA2H_MASK (0xffff << ETH_MACA2HR_MACA2H_SHIFT) +#define ETH_MACA2HR_MBC_SHIFT (24) /* Bits 24-29: Mask byte control */ +#define ETH_MACA2HR_MBC_MASK (0x3f << ETH_MACA2HR_MBC_SHIFT) +# define ETH_MACA2HR_MBC_40_47 (0x20 << ETH_MACA2HR_MBC_SHIFT) /* Bit 29: ETH_MACA2HR [8-15] */ +# define ETH_MACA2HR_MBC_32_39 (0x10 << ETH_MACA2HR_MBC_SHIFT) /* Bit 28: ETH_MACA2HR [0-7] */ +# define ETH_MACA2HR_MBC_24_31 (0x08 << ETH_MACA2HR_MBC_SHIFT) /* Bit 27: ETH_MACA2LR [24-31] */ +# define ETH_MACA2HR_MBC_16_23 (0x04 << ETH_MACA2HR_MBC_SHIFT) /* Bit 26: ETH_MACA2LR [16-23] */ +# define ETH_MACA2HR_MBC_8_15 (0x02 << ETH_MACA2HR_MBC_SHIFT) /* Bit 25: ETH_MACA2LR [8-15] */ +# define ETH_MACA2HR_MBC_0_7 (0x01 << ETH_MACA2HR_MBC_SHIFT) /* Bit 24: ETH_MACA2LR [0-7] */ + +#define ETH_MACA2HR_SA (1 << 30) /* Bit 30: Source address */ +#define ETH_MACA2HR_AE (1 << 31) /* Bit 31: Address enable */ + +/* Ethernet MAC address 2 low register (MAC address2 low [31:0]) */ + +/* Ethernet MAC address 3 high register */ + +#define ETH_MACA3HR_MACA3H_SHIFT (0) /* Bits 0-15: MAC address3 high [47:32] */ +#define ETH_MACA3HR_MACA3H_MASK (0xffff << ETH_MACA3HR_MACA3H_SHIFT) +#define ETH_MACA3HR_MBC_SHIFT (24) /* Bits 24-29: Mask byte control */ +#define ETH_MACA3HR_MBC_MASK (0x3f << ETH_MACA3HR_MBC_SHIFT) +# define ETH_MACA3HR_MBC_40_47 (0x20 << ETH_MACA3HR_MBC_SHIFT) /* Bit 29: ETH_MACA3HR [8-15] */ +# define ETH_MACA3HR_MBC_32_39 (0x10 << ETH_MACA3HR_MBC_SHIFT) /* Bit 28: ETH_MACA3HR [0-7] */ +# define ETH_MACA3HR_MBC_24_31 (0x08 << ETH_MACA3HR_MBC_SHIFT) /* Bit 27: ETH_MACA3LR [24-31] */ +# define ETH_MACA3HR_MBC_16_23 (0x04 << ETH_MACA3HR_MBC_SHIFT) /* Bit 26: ETH_MACA3LR [16-23] */ +# define ETH_MACA3HR_MBC_8_15 (0x02 << ETH_MACA3HR_MBC_SHIFT) /* Bit 25: ETH_MACA3LR [8-15] */ +# define ETH_MACA3HR_MBC_0_7 (0x01 << ETH_MACA3HR_MBC_SHIFT) /* Bit 24: ETH_MACA3LR [0-7] */ + +#define ETH_MACA3HR_SA (1 << 30) /* Bit 30: Source address */ +#define ETH_MACA3HR_AE (1 << 31) /* Bit 31: Address enable */ + +/* Ethernet MAC address 3 low register (MAC address3 low [31:0]) */ + +/* MMC Registers */ + +/* Ethernet MMC control register */ + +#define ETH_MMCCR_CR (1 << 0) /* Bit 0: Counter reset */ +#define ETH_MMCCR_CSR (1 << 1) /* Bit 1: Counter stop rollover */ +#define ETH_MMCCR_ROR (1 << 2) /* Bit 2: Reset on read */ +#define ETH_MMCCR_MCF (1 << 3) /* Bit 3: MMC counter freeze */ +#define ETH_MMCCR_MCP (1 << 4) /* Bit 4: MMC counter preset */ +#if defined(CONFIG_STM32_HAVE_IP_ETHMAC_M3M4_V1) +# define ETH_MMCCR_MCFHP (1 << 5) /* Bit 5: MMC counter Full-Half preset */ +#endif + +/* Ethernet MMC receive interrupt and interrupt mask registers */ + +#define ETH_MMCRI_RFCE (1 << 5) /* Bit 5: Received frame CRC error */ +#define ETH_MMCRI_RFAE (1 << 6) /* Bit 6: Received frames alignment error */ +#define ETH_MMCRI_RGUF (1 << 17) /* Bit 17: Received good unicast frames */ + +/* Ethernet MMC transmit interrupt and interrupt mask register */ + +#define ETH_MMCTI_TGFSC (1 << 14) /* Bit 14: Transmitted good frames single collision */ +#define ETH_MMCTI_TGFMSC (1 << 15) /* Bit 15: Transmitted good frames more single collision */ +#define ETH_MMCTI_TGF (1 << 21) /* Bit 21: Transmitted good frames */ + +/* 32-bit counters: + * + * Ethernet MMC transmitted good frames counter register (single collision) + * Ethernet MMC transmitted good frames counter register (multiple-collision) + * Ethernet MMC transmitted good frames counter register + * Ethernet MMC received frames with CRC error counter register + * Ethernet MMC received frames with alignment error counter + * MMC received good unicast frames counter register + */ + +/* IEEE 1588 time stamp registers */ + +/* Ethernet PTP time stamp control register */ + +#define ETH_PTPTSCR_TSE (1 << 0) /* Bit 0: Time stamp enable */ +#define ETH_PTPTSCR_TSFCU (1 << 1) /* Bit 1: Time stamp fine or coarse update */ +#define ETH_PTPTSCR_TSSTI (1 << 2) /* Bit 2: Time stamp system time initialize */ +#define ETH_PTPTSCR_TSSTU (1 << 3) /* Bit 3: Time stamp system time update */ +#define ETH_PTPTSCR_TSITE (1 << 4) /* Bit 4: Time stamp interrupt trigger enable */ +#define ETH_PTPTSCR_TSARU (1 << 5) /* Bit 5: Time stamp addend register update */ + +#if defined(CONFIG_STM32_HAVE_IP_ETHMAC_M3M4_V1) +#define ETH_PTPTSCR_TSSARFE (1 << 8) /* Bit 8: Time stamp snapshot for all received frames enable */ +#define ETH_PTPTSCR_TSSSR (1 << 9) /* Bit 9: Time stamp subsecond rollover: digital or binary rollover control */ +#define ETH_PTPTSCR_TSPTPPSV2E (1 << 10) /* Bit 10: Time stamp PTP packet snooping for version2 format enable */ +#define ETH_PTPTSCR_TSSPTPOEFE (1 << 11) /* Bit 11: Time stamp snapshot for PTP over ethernet frames enable */ +#define ETH_PTPTSCR_TSSIPV6FE (1 << 12) /* Bit 12: Time stamp snapshot for IPv6 frames enable */ +#define ETH_PTPTSCR_TSSIPV4FE (1 << 13) /* Bit 13: Time stamp snapshot for IPv4 frames enable */ +#define ETH_PTPTSCR_TSSEME (1 << 14) /* Bit 14: Time stamp snapshot for event message enable */ +#define ETH_PTPTSCR_TSSMRME (1 << 15) /* Bit 15: Time stamp snapshot for message relevant to master enable */ +#define ETH_PTPTSCR_TSCNT_SHIFT (16) /* Bits 16-17: Time stamp clock node type */ +#define ETH_PTPTSCR_TSCNT_MASK (3 << ETH_PTPTSCR_TSCNT_SHIFT) +# define ETH_PTPTSCR_TSCNT_ORDINARY (0 << ETH_PTPTSCR_TSCNT_SHIFT) /* 00: Ordinary clock */ +# define ETH_PTPTSCR_TSCNT_BOUNDARY (1 << ETH_PTPTSCR_TSCNT_SHIFT) /* 01: Boundary clock */ +# define ETH_PTPTSCR_TSCNT_E2E (2 << ETH_PTPTSCR_TSCNT_SHIFT) /* 10: End-to-end transparent clock */ +# define ETH_PTPTSCR_TSCNT_P2P (3 << ETH_PTPTSCR_TSCNT_SHIFT) /* 11: Peer-to-peer transparent clock */ + +#define ETH_PTPTSCR_TSPFFMAE (1 << 18) /* Bit 18: Time stamp PTP frame filtering MAC address enable */ +#endif + +/* Ethernet PTP subsecond increment register */ + +#define ETH_PTPSSIR_MASK (0xff) + +/* Ethernet PTP time stamp high register (32-bit) */ + +/* Ethernet PTP time stamp low register */ + +#define ETH_PTPTSLR_STPNS (1 << 31) /* Bit 31: System time positive or negative sign */ +#define ETH_PTPTSLR_MASK (0x7fffffff) /* Bits 0-30: System time subseconds */ + +/* Ethernet PTP time stamp high update register (32-bit) */ + +/* Ethernet PTP time stamp low update register */ + +#define ETH_PTPTSLU_TSUPNS (1 << 31) /* Bit 31: System time positive or negative sign */ +#define ETH_PTPTSLU_MASK (0x7fffffff) /* Bits 0-30: Time stamp update subsecond */ + +/* Ethernet PTP time stamp addend register (32-bit) */ + +/* Ethernet PTP target time high register (32-bit) */ + +/* Ethernet PTP target time low register (32-bit) */ + +/* Ethernet PTP time stamp status register */ + +#define ETH_PTPTSSR_TSSO (1 << 0) /* Bit 0: Time stamp second overflow */ +#define ETH_PTPTSSR_TSTTR (1 << 1) /* Bit 1: Time stamp target time reached */ + +/* Ethernet PTP PPS control register */ + +#define ETH_PTPPPSCR_PPSFREQ_SHIFT (0) /* Bits 0-3: PPS frequency selection */ +#define ETH_PTPPPSCR_PPSFREQ_MASK (15 << ETH_PTPPPSCR_PPSFREQ_SHIFT) +# define ETH_PTPPPSCR_PPSFREQ_1HZ (0 << ETH_PTPPPSCR_PPSFREQ_SHIFT) /* 1 Hz with pulse width of 125/100 ms for binary/digital rollover */ +# define ETH_PTPPPSCR_PPSFREQ_2HZ (1 << ETH_PTPPPSCR_PPSFREQ_SHIFT) /* 2 Hz with 50% duty cycle */ +# define ETH_PTPPPSCR_PPSFREQ_4HZ (2 << ETH_PTPPPSCR_PPSFREQ_SHIFT) /* 4 Hz with 50% duty cycle */ +# define ETH_PTPPPSCR_PPSFREQ_8HZ (3 << ETH_PTPPPSCR_PPSFREQ_SHIFT) /* 8 Hz with 50% duty cycle */ +# define ETH_PTPPPSCR_PPSFREQ_16HZ (4 << ETH_PTPPPSCR_PPSFREQ_SHIFT) /* 16 Hz with 50% duty cycle */ +# define ETH_PTPPPSCR_PPSFREQ_32HZ (5 << ETH_PTPPPSCR_PPSFREQ_SHIFT) /* 32 Hz with 50% duty cycle */ +# define ETH_PTPPPSCR_PPSFREQ_64HZ (6 << ETH_PTPPPSCR_PPSFREQ_SHIFT) /* 64 Hz with 50% duty cycle */ +# define ETH_PTPPPSCR_PPSFREQ_128HZ (7 << ETH_PTPPPSCR_PPSFREQ_SHIFT) /* 128 Hz with 50% duty cycle */ +# define ETH_PTPPPSCR_PPSFREQ_256HZ (8 << ETH_PTPPPSCR_PPSFREQ_SHIFT) /* 256 Hz with 50% duty cycle */ +# define ETH_PTPPPSCR_PPSFREQ_512HZ (9 << ETH_PTPPPSCR_PPSFREQ_SHIFT) /* 512 Hz with 50% duty cycle */ +# define ETH_PTPPPSCR_PPSFREQ_1KHZ (10 << ETH_PTPPPSCR_PPSFREQ_SHIFT) /* 1024 Hz with 50% duty cycle */ +# define ETH_PTPPPSCR_PPSFREQ_2KHZ (11 << ETH_PTPPPSCR_PPSFREQ_SHIFT) /* 2048 Hz with 50% duty cycle */ +# define ETH_PTPPPSCR_PPSFREQ_4KHZ (12 << ETH_PTPPPSCR_PPSFREQ_SHIFT) /* 4096 Hz with 50% duty cycle */ +# define ETH_PTPPPSCR_PPSFREQ_8KHZ (13 << ETH_PTPPPSCR_PPSFREQ_SHIFT) /* 8192 Hz with 50% duty cycle */ +# define ETH_PTPPPSCR_PPSFREQ_16KHZ (14 << ETH_PTPPPSCR_PPSFREQ_SHIFT) /* 16384 Hz with 50% duty cycle */ +# define ETH_PTPPPSCR_PPSFREQ_32KHZ (15 << ETH_PTPPPSCR_PPSFREQ_SHIFT) /* 32768 Hz with 50% duty cycle */ + +/* DMA Registers */ + +/* Ethernet DMA bus mode register */ + +#define ETH_DMABMR_SR (1 << 0) /* Bit 0: Software reset */ +#define ETH_DMABMR_DA (1 << 1) /* Bit 1: DMA Arbitration */ +#define ETH_DMABMR_DSL_SHIFT (2) /* Bits 2-6: Descriptor skip length */ +#define ETH_DMABMR_DSL_MASK (31 << ETH_DMABMR_DSL_SHIFT) +# define ETH_DMABMR_DSL(n) ((n) << ETH_DMABMR_DSL_SHIFT) +#define ETH_DMABMR_EDFE (1 << 7) /* Bit 7: Enhanced descriptor format enable */ +#define ETH_DMABMR_PBL_SHIFT (8) /* Bits 8-13: Programmable burst length */ + +# define ETH_DMABMR_PBL(n) ((n) << ETH_DMABMR_PBL_SHIFT) /* n=1, 2, 4, 8, 16, 32 */ +#define ETH_DMABMR_PBL_MASK (0x3f << ETH_DMABMR_PBL_SHIFT) + +#define ETH_DMABMR_RTPR_SHIFT (14) /* Bits 14-15: Rx Tx priority ratio */ +#define ETH_DMABMR_RTPR_MASK (3 << ETH_DMABMR_RTPR_SHIFT) +# define ETH_DMABMR_RTPR_1TO1 (0 << ETH_DMABMR_RTPR_SHIFT) /* 00: 1:1 */ +# define ETH_DMABMR_RTPR_2TO1 (1 << ETH_DMABMR_RTPR_SHIFT) /* 01: 2:1 */ +# define ETH_DMABMR_RTPR_3TO1 (2 << ETH_DMABMR_RTPR_SHIFT) /* 10: 3:1 */ +# define ETH_DMABMR_RTPR_4TO1 (3 << ETH_DMABMR_RTPR_SHIFT) /* 11: 4:1 */ + +#define ETH_DMABMR_FB (1 << 16) /* Bit 16: Fixed burst */ +#define ETH_DMABMR_RDP_SHIFT (17) /* Bits 17-22: Rx DMA PBL */ +#define ETH_DMABMR_RDP_MASK (0x3f << ETH_DMABMR_RDP_SHIFT) +# define ETH_DMABMR_RDP(n) ((n) << ETH_DMABMR_RDP_SHIFT) /* n=1, 2, 4, 8, 16, 32 */ + +#define ETH_DMABMR_USP (1 << 23) /* Bit 23: Use separate PBL */ +#define ETH_DMABMR_FPM (1 << 24) /* Bit 24: 4xPBL mode */ +#define ETH_DMABMR_AAB (1 << 25) /* Bit 25: Address-aligned beats */ +#if defined(CONFIG_STM32_HAVE_IP_ETHMAC_M3M4_V1) +# define ETH_DMABMR_MB (1 << 26) /* Bit 26: Mixed burst */ +#endif + +/* Ethernet DMA transmit poll demand register (32-bit) */ + +/* Ethernet DMA receive poll demand register (32-bit) */ + +/* Ethernet DMA receive descriptor list address register (32-bit address) */ + +/* Ethernet DMA transmit descriptor list address register (32-bit address) */ + +/* Interrupt bit definitions common between the DMA status register (DMASR) + * and the DMA interrupt enable register (DMAIER). + */ + +#define ETH_DMAINT_TI (1 << 0) /* Bit 0: Transmit interrupt */ +#define ETH_DMAINT_TPSI (1 << 1) /* Bit 1: Transmit process stopped interrupt */ +#define ETH_DMAINT_TBUI (1 << 2) /* Bit 2: Transmit buffer unavailable interrupt */ +#define ETH_DMAINT_TJTI (1 << 3) /* Bit 3: Transmit jabber timeout interrupt */ +#define ETH_DMAINT_ROI (1 << 4) /* Bit 4: Overflow interrupt */ +#define ETH_DMAINT_TUI (1 << 5) /* Bit 5: Underflow interrupt */ +#define ETH_DMAINT_RI (1 << 6) /* Bit 6: Receive interrupt */ +#define ETH_DMAINT_RBUI (1 << 7) /* Bit 7: Receive buffer unavailable interrupt */ +#define ETH_DMAINT_RPSI (1 << 8) /* Bit 8: Receive process stopped interrupt */ +#define ETH_DMAINT_RWTI (1 << 9) /* Bit 9: Receive watchdog timeout interrupt */ +#define ETH_DMAINT_ETI (1 << 10) /* Bit 10: Early transmit interrupt */ +#define ETH_DMAINT_FBEI (1 << 13) /* Bit 13: Fatal bus error interrupt */ +#define ETH_DMAINT_ERI (1 << 14) /* Bit 14: Early receive interrupt */ +#define ETH_DMAINT_AIS (1 << 15) /* Bit 15: Abnormal interrupt summary */ +#define ETH_DMAINT_NIS (1 << 16) /* Bit 16: Normal interrupt summary */ + +/* Ethernet DMA status register (in addition to the interrupt bits above */ + +#define ETH_DMASR_RPS_SHIFT (17) /* Bits 17-19: Receive process state */ +#define ETH_DMASR_RPS_MASK (7 << ETH_DMASR_RPS_SHIFT) +# define ETH_DMASR_RPS_STOPPED (0 << ETH_DMASR_RPS_SHIFT) /* 000: Stopped: Reset or Stop Receive Command issued */ +# define ETH_DMASR_RPS_RXDESC (1 << ETH_DMASR_RPS_SHIFT) /* 001: Running: Fetching receive transfer descriptor */ +# define ETH_DMASR_RPS_WAITING (3 << ETH_DMASR_RPS_SHIFT) /* 011: Running: Waiting for receive packet */ +# define ETH_DMASR_RPS_SUSPENDED (4 << ETH_DMASR_RPS_SHIFT) /* 100: Suspended: Receive descriptor unavailable */ +# define ETH_DMASR_RPS_CLOSING (5 << ETH_DMASR_RPS_SHIFT) /* 101: Running: Closing receive descriptor */ +# define ETH_DMASR_RPS_TRANSFER (6 << ETH_DMASR_RPS_SHIFT) /* 111: Running: Transferring the receive data to memory */ + +#define ETH_DMASR_TPS_SHIFT (20) /* Bits 20-22: Transmit process state */ +#define ETH_DMASR_TPS_MASK (7 << ETH_DMASR_TPS_SHIFT) +# define ETH_DMASR_TPS_STOPPED (0 << ETH_DMASR_TPS_SHIFT) /* 000: Stopped; Reset or Stop Transmit Command issued */ +# define ETH_DMASR_TPS_TXDESC (1 << ETH_DMASR_TPS_SHIFT) /* 001: Running; Fetching transmit transfer descriptor */ +# define ETH_DMASR_TPS_WAITING (2 << ETH_DMASR_TPS_SHIFT) /* 010: Running; Waiting for status */ +# define ETH_DMASR_TPS_TRANSFER (3 << ETH_DMASR_TPS_SHIFT) /* 011: Running; Reading data and queuing to transmit (TxFIFO) */ +# define ETH_DMASR_TPS_SUSPENDED (6 << ETH_DMASR_TPS_SHIFT) /* 110: Suspended; Transmit descriptor unavailable or buffer underflow */ +# define ETH_DMASR_TPS_CLOSING (7 << ETH_DMASR_TPS_SHIFT) /* 111: Running; Closing transmit descriptor */ + +#define ETH_DMASR_EBS_SHIFT (23) /* Bits 23-25: Error bits status */ +#define ETH_DMASR_EBS_MASK (7 << ETH_DMASR_EBS_SHIFT) +#define ETH_DMASR_EBS_TXDMS (1 << ETH_DMASR_EBS_SHIFT) /* Bit 23 1 Error during data transfer by TxDMA */ +#define ETH_DMASR_EBS_READ (2 << ETH_DMASR_EBS_SHIFT) /* Bit 24 1 Error during read transfer */ +#define ETH_DMASR_EBS_DESC (4 << ETH_DMASR_EBS_SHIFT) /* Bit 25 1 Error during descriptor access */ + +#define ETH_DMASR_MMCS (1 << 27) /* Bit 27: MMC status */ +#define ETH_DMASR_PMTS (1 << 28) /* Bit 28: PMT status */ +#define ETH_DMASR_TSTS (1 << 29) /* Bit 29: Time stamp trigger status */ + +/* Ethernet DMA operation mode register */ + +#define ETH_DMAOMR_SR (1 << 1) /* Bit 1: Start/stop receive */ +#define ETH_DMAOMR_OSF (1 << 2) /* Bit 2: Operate on second frame */ +#define ETH_DMAOMR_RTC_SHIFT (3) /* Bits 3-4: Receive threshold control */ +#define ETH_DMAOMR_RTC_MASK (3 << ETH_DMAOMR_RTC_SHIFT) +# define ETH_DMAOMR_RTC_64 (0 << ETH_DMAOMR_RTC_SHIFT) +# define ETH_DMAOMR_RTC_32 (1 << ETH_DMAOMR_RTC_SHIFT) +# define ETH_DMAOMR_RTC_96 (2 << ETH_DMAOMR_RTC_SHIFT) +# define ETH_DMAOMR_RTC_128 (3 << ETH_DMAOMR_RTC_SHIFT) +#define ETH_DMAOMR_FUGF (1 << 6) /* Bit 6: Forward undersized good frames */ +#define ETH_DMAOMR_FEF (1 << 7) /* Bit 7: Forward error frames */ +#define ETH_DMAOMR_ST (1 << 13) /* Bit 13: Start/stop transmission */ +#define ETH_DMAOMR_TTC_SHIFT (14) /* Bits 14-16: Transmit threshold control */ +#define ETH_DMAOMR_TTC_MASK (7 << ETH_DMAOMR_TTC_SHIFT) +# define ETH_DMAOMR_TTC_64 (0 << ETH_DMAOMR_TTC_SHIFT) +# define ETH_DMAOMR_TTC_128 (1 << ETH_DMAOMR_TTC_SHIFT) +# define ETH_DMAOMR_TTC_192 (2 << ETH_DMAOMR_TTC_SHIFT) +# define ETH_DMAOMR_TTC_256 (3 << ETH_DMAOMR_TTC_SHIFT) +# define ETH_DMAOMR_TTC_40 (4 << ETH_DMAOMR_TTC_SHIFT) +# define ETH_DMAOMR_TTC_32 (5 << ETH_DMAOMR_TTC_SHIFT) +# define ETH_DMAOMR_TTC_24 (6 << ETH_DMAOMR_TTC_SHIFT) +# define ETH_DMAOMR_TTC_16 (7 << ETH_DMAOMR_TTC_SHIFT) +#define ETH_DMAOMR_FTF (1 << 20) /* Bit 20: Flush transmit FIFO */ +#define ETH_DMAOMR_TSF (1 << 21) /* Bit 21: Transmit store and forward */ +#define ETH_DMAOMR_DFRF (1 << 24) /* Bit 24: Disable flushing of received frames */ +#define ETH_DMAOMR_RSF (1 << 25) /* Bit 25: Receive store and forward */ +#define ETH_DMAOMR_DTCEFD (1 << 26) /* Bit 26: Dropping of TCP/IP checksum error frames disable */ + +/* Ethernet DMA missed frame and buffer overflow counter register */ + +#define ETH_DMAMFBOC_MFC_SHIFT (0) /* Bits 0-15: Missed frames by the controller */ +#define ETH_DMAMFBOC_MFC_MASK (0xffff << ETH_DMAMFBOC_MFC_SHIFT) +#define ETH_DMAMFBOC_OMFC (1 << 16) /* Bit 16: Overflow bit for missed frame counter */ +#define ETH_DMAMFBOC_MFA_SHIFT (17) /* Bits 17-27: Missed frames by the application */ +#define ETH_DMAMFBOC_MFA_MASK (0x7ff << ETH_DMAMFBOC_MFA_SHIFT) +#define ETH_DMAMFBOC_OFOC (1 << 28) /* Bit 28: Overflow bit for FIFO overflow counter */ + +/* Ethernet DMA receive status watchdog timer register */ + +#define ETH_DMARSWTR_MASK (0xff) + +/* Ethernet DMA current host transmit descriptor register + * (32-bit address) + */ + +/* Ethernet DMA current host receive descriptor register + * (32-bit address) + */ + +/* Ethernet DMA current host transmit buffer address register + * (32-bit address) + */ + +/* Ethernet DMA current host receive buffer address register + * (32-bit address) + */ + +/* DMA Descriptors **********************************************************/ + +/* TDES0: Transmit descriptor Word0 */ + +#define ETH_TDES0_DB (1 << 0) /* Bit 0: Deferred bit */ +#define ETH_TDES0_UF (1 << 1) /* Bit 1: Underflow error */ +#define ETH_TDES0_ED (1 << 2) /* Bit 2: Excessive deferral */ +#define ETH_TDES0_CC_SHIFT (3) /* Bits 3-6: Collision count */ +#define ETH_TDES0_CC_MASK (15 << ETH_TDES0_CC_SHIFT) +#define ETH_TDES0_VF (1 << 7) /* Bit 7: VLAN frame */ +#define ETH_TDES0_EC (1 << 8) /* Bit 8: Excessive collision */ +#define ETH_TDES0_LCO (1 << 9) /* Bit 9: Late collision */ +#define ETH_TDES0_NC (1 << 10) /* Bit 10: No carrier */ +#define ETH_TDES0_LCA (1 << 11) /* Bit 11: Loss of carrier */ +#define ETH_TDES0_IPE (1 << 12) /* Bit 12: IP payload error */ +#define ETH_TDES0_FF (1 << 13) /* Bit 13: Frame flushed */ +#define ETH_TDES0_JT (1 << 14) /* Bit 14: Jabber timeout */ +#define ETH_TDES0_ES (1 << 15) /* Bit 15: Error summary */ +#define ETH_TDES0_IHE (1 << 16) /* Bit 16: IP header error */ +#define ETH_TDES0_TTSS (1 << 17) /* Bit 17: Transmit time stamp status */ +#define ETH_TDES0_TCH (1 << 20) /* Bit 20: Second address chained */ +#define ETH_TDES0_TER (1 << 21) /* Bit 21: Transmit end of ring */ +#define ETH_TDES0_CIC_SHIFT (22) /* Bits 22-23: Checksum insertion control */ +#define ETH_TDES0_CIC_MASK (3 << ETH_TDES0_CIC_SHIFT) +# define ETH_TDES0_CIC_DISABLED (0 << ETH_TDES0_CIC_SHIFT) /* Checksum disabled */ +# define ETH_TDES0_CIC_IH (1 << ETH_TDES0_CIC_SHIFT) /* IP header checksum enabled */ +# define ETH_TDES0_CIC_IHPL (2 << ETH_TDES0_CIC_SHIFT) /* IP header and payload checksum enabled */ +# define ETH_TDES0_CIC_ALL (3 << ETH_TDES0_CIC_SHIFT) /* IP Header, payload, and pseudo-header checksum enabled */ + +#define ETH_TDES0_TTSE (1 << 25) /* Bit 25: Transmit time stamp enable */ +#define ETH_TDES0_DP (1 << 26) /* Bit 26: Disable pad */ +#define ETH_TDES0_DC (1 << 27) /* Bit 27: Disable CRC */ +#define ETH_TDES0_FS (1 << 28) /* Bit 28: First segment */ +#define ETH_TDES0_LS (1 << 29) /* Bit 29: Last segment */ +#define ETH_TDES0_IC (1 << 30) /* Bit 30: Interrupt on completion */ +#define ETH_TDES0_OWN (1 << 31) /* Bit 31: Own bit */ + +/* TDES1: Transmit descriptor Word1 */ + +#define ETH_TDES1_TBS1_SHIFT (0) /* Bits 0-12: Transmit buffer 1 size */ +#define ETH_TDES1_TBS1_MASK (0x1fff << ETH_TDES1_TBS1_SHIFT) +#define ETH_TDES1_TBS2_SHIFT (16) /* Bits 16-28: Transmit buffer 2 size */ +#define ETH_TDES1_TBS2_MASK (0x1fff << ETH_TDES1_TBS2_SHIFT) + +/* TDES2: Transmit descriptor Word2 (32-bit address) */ + +/* TDES3: Transmit descriptor Word3 (32-bit address) */ + +/* TDES6: Transmit descriptor Word6 (32-bit time stamp) */ + +/* TDES7: Transmit descriptor Word7 (32-bit time stamp) */ + +/* RDES0: Receive descriptor Word0 */ + +#define ETH_RDES0_PCE (1 << 0) /* Bit 0: Payload checksum error */ +#if defined(CONFIG_STM32_HAVE_IP_ETHMAC_M3M4_V1) +# define ETH_RDES0_ESA (1 << 0) /* Bit 0: Extended status available */ +#endif +#define ETH_RDES0_CE (1 << 1) /* Bit 1: CRC error */ +#define ETH_RDES0_DBE (1 << 2) /* Bit 2: Dribble bit error */ +#define ETH_RDES0_RE (1 << 3) /* Bit 3: Receive error */ +#define ETH_RDES0_RWT (1 << 4) /* Bit 4: Receive watchdog timeout */ +#define ETH_RDES0_FT (1 << 5) /* Bit 5: Frame type */ +#define ETH_RDES0_LCO (1 << 6) /* Bit 6: Late collision */ +#define ETH_RDES0_TSV (1 << 7) /* Bit 7: Time stamp valid */ +#define ETH_RDES0_IPHCE (1 << 7) /* Bit 7: IPv header checksum error */ +#define ETH_RDES0_LS (1 << 8) /* Bit 8: Last descriptor */ +#define ETH_RDES0_FS (1 << 9) /* Bit 9: First descriptor */ +#define ETH_RDES0_VLAN (1 << 10) /* Bit 10: VLAN tag */ +#define ETH_RDES0_OE (1 << 11) /* Bit 11: Overflow error */ +#define ETH_RDES0_LE (1 << 12) /* Bit 12: Length error */ +#define ETH_RDES0_SAF (1 << 13) /* Bit 13: Source address filter fail */ +#define ETH_RDES0_DE (1 << 14) /* Bit 14: Descriptor error */ +#define ETH_RDES0_ES (1 << 15) /* Bit 15: Error summary */ +#define ETH_RDES0_FL_SHIFT (16) /* Bits 16-29: Frame length */ +#define ETH_RDES0_FL_MASK (0x3fff << ETH_RDES0_FL_SHIFT) +#define ETH_RDES0_AFM (1 << 30) /* Bit 30: Destination address filter fail */ +#define ETH_RDES0_OWN (1 << 31) /* Bit 31: Own bit */ + +/* RDES1: Receive descriptor Word1 */ + +#define ETH_RDES1_RBS1_SHIFT (0) /* Bits 0-12: Receive buffer 1 size */ +#define ETH_RDES1_RBS1_MASK (0x1fff << ETH_RDES1_RBS1_SHIFT) + /* Bit 13: Reserved */ +#define ETH_RDES1_RCH (1 << 14) /* Bit 14: Second address chained */ +#define ETH_RDES1_RER (1 << 15) /* Bit 15: Receive end of ring */ +#define ETH_RDES1_RBS2_SHIFT (16) /* Bits 16-28: Receive buffer 2 size */ +#define ETH_RDES1_RBS2_MASK (0x1fff << ETH_RDES1_RBS2_SHIFT) +#define ETH_RDES1_DIC (1 << 31) /* Bit 31: Disable interrupt on completion */ + +/* RDES2: Receive descriptor Word2 (32-bit address) */ + +/* RDES3: Receive descriptor Word3 (32-bit address) */ + +/* RDES4: Receive descriptor Word4 */ + +#define ETH_RDES4_IPPT_SHIFT (0) /* Bits 0-2: IP payload type */ +#define ETH_RDES4_IPPT_MASK (7 << ETH_RDES4_IPPT_SHIFT) +# define ETH_RDES4_IPPT_UDP (1 << ETH_RDES4_IPPT_SHIFT) /* UDP payload in IP datagram */ +# define ETH_RDES4_IPPT_TCP (2 << ETH_RDES4_IPPT_SHIFT) /* TCP payload in IP datagram */ +# define ETH_RDES4_IPPT_ICMP (3 << ETH_RDES4_IPPT_SHIFT) /* ICMP payload in IP datagram */ + +#define ETH_RDES4_IPHE (1 << 3) /* Bit 3: IP header error */ +#define ETH_RDES4_IPPE (1 << 4) /* Bit 4: IP payload error */ +#define ETH_RDES4_IPCB (1 << 5) /* Bit 5: IP checksum bypassed */ +#define ETH_RDES4_IPV4PR (1 << 6) /* Bit 6: IPv4 packet received */ +#define ETH_RDES4_IPV6PR (1 << 7) /* Bit 7: IPv6 packet received */ +#define ETH_RDES4_PMT_SHIFT (8) /* Bits 8-11: PTP message type */ +#define ETH_RDES4_PMT_MASK (15 << ETH_RDES4_PMT_SHIFT) +# define ETH_RDES4_PMT_NONE (0 << ETH_RDES4_PMT_SHIFT) /* No PTP message received */ +# define ETH_RDES4_PMT_SYNC (1 << ETH_RDES4_PMT_SHIFT) /* SYNC (all clock types) */ +# define ETH_RDES4_PMT_FOLLOWUP (2 << ETH_RDES4_PMT_SHIFT) /* Follow_Up (all clock types) */ +# define ETH_RDES4_PMT_DELAYREQ (3 << ETH_RDES4_PMT_SHIFT) /* Delay_Req (all clock types) */ +# define ETH_RDES4_PMT_DELAYRESP (4 << ETH_RDES4_PMT_SHIFT) /* Delay_Resp (all clock types) */ +# define ETH_RDES4_PMT_PDELREQAM (5 << ETH_RDES4_PMT_SHIFT) /* Pdelay_Req (in peer-to-peer + * transparent clock) or Announce (in + * ordinary or boundary clock) */ +# define ETH_RDES4_PMT_PDELREQMM (6 << ETH_RDES4_PMT_SHIFT) /* Pdelay_Resp (in peer-to-peer + * transparent clock) or Management (in + * ordinary or boundary clock) */ +# define ETH_RDES4_PMT_PDELREQFUS (7 << ETH_RDES4_PMT_SHIFT) /* Pdelay_Resp_Follow_Up (in + * peer-to-peer transparent clock) or + * Signaling (for ordinary or boundary + * clock) */ + +#define ETH_RDES4_PFT (1 << 12) /* Bit 12: PTP frame type */ +#define ETH_RDES4_PV (1 << 13) /* Bit 13: PTP version */ + +/* RDES5: Receive descriptor Word5 - Reserved */ + +/* RDES6: Receive descriptor Word6 (32-bit time stamp) */ + +/* RDES7: Receive descriptor Word7 (32-bit time stamp) */ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +/* Ethernet TX DMA Descriptor */ + +struct eth_txdesc_s +{ + /* Normal DMA descriptor words */ + + volatile uint32_t tdes0; /* Status */ + volatile uint32_t tdes1; /* Control and buffer1/2 lengths */ + volatile uint32_t tdes2; /* Buffer1 address pointer */ + volatile uint32_t tdes3; /* Buffer2 or next descriptor address pointer */ + + /* Enhanced DMA descriptor words with time stamp */ + +#ifdef CONFIG_STM32_ETH_ENHANCEDDESC + volatile uint32_t tdes4; /* Reserved */ + volatile uint32_t tdes5; /* Reserved */ + volatile uint32_t tdes6; /* Time Stamp Low value for transmit and receive */ + volatile uint32_t tdes7; /* Time Stamp High value for transmit and receive */ +#endif +}; + +/* Ethernet RX DMA Descriptor */ + +struct eth_rxdesc_s +{ + volatile uint32_t rdes0; /* Status */ + volatile uint32_t rdes1; /* Control and buffer1/2 lengths */ + volatile uint32_t rdes2; /* Buffer1 address pointer */ + volatile uint32_t rdes3; /* Buffer2 or next descriptor address pointer */ + + /* Enhanced DMA descriptor words with time stamp and PTP support */ + +#ifdef CONFIG_STM32_ETH_ENHANCEDDESC + volatile uint32_t rdes4; /* Extended status for PTP receive descriptor */ + volatile uint32_t rdes5; /* Reserved */ + volatile uint32_t rdes6; /* Time Stamp Low value for transmit and receive */ + volatile uint32_t rdes7; /* Time Stamp High value for transmit and receive */ +#endif +}; + +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ + +#endif /* __ASSEMBLY__ */ +#endif /* STM32_NETHERNET > 0 */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_ETH_H */ diff --git a/arch/arm/src/common/stm32/hardware/stm32_exti.h b/arch/arm/src/common/stm32/hardware/stm32_exti.h new file mode 100644 index 0000000000000..8b22f1abf7045 --- /dev/null +++ b/arch/arm/src/common/stm32/hardware/stm32_exti.h @@ -0,0 +1,49 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/hardware/stm32_exti.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_EXTI_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_EXTI_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/* The EXTI IP version (V1/V2) is independent of the CPU core. The M0 and + * M3/M4 ports currently keep separate register headers, so the file is + * chosen by the standard NuttX core symbol (CONFIG_ARCH_CORTEXM0) while the + * version is core-agnostic. + */ + +#if (defined(CONFIG_STM32_HAVE_IP_EXTI_V1) + \ + defined(CONFIG_STM32_HAVE_IP_EXTI_V2)) > 1 +# error Only one STM32 EXTI IP version must be selected +#endif + +#if !(defined(CONFIG_STM32_HAVE_IP_EXTI_V1) || defined(CONFIG_STM32_HAVE_IP_EXTI_V2)) +# error "Unsupported STM32 EXTI" +#elif defined(CONFIG_ARCH_CORTEXM0) +# include "hardware/stm32_exti_v1v2_m0.h" +#else +# include "hardware/stm32_exti_v1v2.h" +#endif + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_EXTI_H */ diff --git a/arch/arm/src/common/stm32/hardware/stm32_exti_v1v2.h b/arch/arm/src/common/stm32/hardware/stm32_exti_v1v2.h new file mode 100644 index 0000000000000..66af0a47a616f --- /dev/null +++ b/arch/arm/src/common/stm32/hardware/stm32_exti_v1v2.h @@ -0,0 +1,231 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/hardware/stm32_exti_v1v2.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_EXTI_V1V2_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_EXTI_V1V2_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include "chip.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#if defined(CONFIG_STM32_STM32F10XX) +# ifdef CONFIG_STM32_CONNECTIVITYLINE +# define STM32_NEXTI 20 +# define STM32_EXTI_MASK 0x000fffff +# else +# define STM32_NEXTI 19 +# define STM32_EXTI_MASK 0x0007ffff +# endif +#elif defined(CONFIG_STM32_STM32L15XX) +# if defined(CONFIG_STM32_LOWDENSITY) || defined(CONFIG_STM32_MEDIUMDENSITY) +# define STM32_NEXTI 23 +# define STM32_EXTI_MASK 0x007fffff +# else +# define STM32_NEXTI 24 +# define STM32_EXTI_MASK 0x00ffffff +# endif +#elif defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) +# define STM32_NEXTI1 31 +# define STM32_EXTI1_MASK 0xffffffff +# define STM32_NEXTI2 4 +# define STM32_EXTI2_MASK 0x0000000f +#elif defined(CONFIG_STM32_HAVE_IP_EXTI_V1) +# define STM32_NEXTI 23 +# define STM32_EXTI_MASK 0x007fffff +#endif + +#define STM32_EXTI_BIT(n) (1 << (n)) + +/* Register Offsets *********************************************************/ + +#if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) +# define STM32_EXTI1_OFFSET 0x0000 /* Offset to EXTI1 registers */ +# define STM32_EXTI2_OFFSET 0x0020 /* Offset to EXTI2 registers */ +#endif + +#define STM32_EXTI_IMR_OFFSET 0x0000 /* Interrupt mask register */ +#define STM32_EXTI_EMR_OFFSET 0x0004 /* Event mask register */ +#define STM32_EXTI_RTSR_OFFSET 0x0008 /* Rising Trigger selection register */ +#define STM32_EXTI_FTSR_OFFSET 0x000c /* Falling Trigger selection register */ +#define STM32_EXTI_SWIER_OFFSET 0x0010 /* Software interrupt event register */ +#define STM32_EXTI_PR_OFFSET 0x0014 /* Pending register */ + +/* Register Addresses *******************************************************/ + +#if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) +# define STM32_EXTI1_BASE (STM32_EXTI_BASE+STM32_EXTI1_OFFSET) +# define STM32_EXTI2_BASE (STM32_EXTI_BASE+STM32_EXTI2_OFFSET) + +# define STM32_EXTI1_IMR (STM32_EXTI1_BASE+STM32_EXTI_IMR_OFFSET) +# define STM32_EXTI1_EMR (STM32_EXTI1_BASE+STM32_EXTI_EMR_OFFSET) +# define STM32_EXTI1_RTSR (STM32_EXTI1_BASE+STM32_EXTI_RTSR_OFFSET) +# define STM32_EXTI1_FTSR (STM32_EXTI1_BASE+STM32_EXTI_FTSR_OFFSET) +# define STM32_EXTI1_SWIER (STM32_EXTI1_BASE+STM32_EXTI_SWIER_OFFSET) +# define STM32_EXTI1_PR (STM32_EXTI1_BASE+STM32_EXTI_PR_OFFSET) + +# define STM32_EXTI2_IMR (STM32_EXTI2_BASE+STM32_EXTI_IMR_OFFSET) +# define STM32_EXTI2_EMR (STM32_EXTI2_BASE+STM32_EXTI_EMR_OFFSET) +# define STM32_EXTI2_RTSR (STM32_EXTI2_BASE+STM32_EXTI_RTSR_OFFSET) +# define STM32_EXTI2_FTSR (STM32_EXTI2_BASE+STM32_EXTI_FTSR_OFFSET) +# define STM32_EXTI2_SWIER (STM32_EXTI2_BASE+STM32_EXTI_SWIER_OFFSET) +# define STM32_EXTI2_PR (STM32_EXTI2_BASE+STM32_EXTI_PR_OFFSET) + +# define STM32_EXTI_IMR STM32_EXTI1_IMR +# define STM32_EXTI_EMR STM32_EXTI1_EMR +# define STM32_EXTI_RTSR STM32_EXTI1_RTSR +# define STM32_EXTI_FTSR STM32_EXTI1_FTSR +# define STM32_EXTI_SWIER STM32_EXTI1_SWIER +# define STM32_EXTI_PR STM32_EXTI1_PR + +#else +# define STM32_EXTI_IMR (STM32_EXTI_BASE+STM32_EXTI_IMR_OFFSET) +# define STM32_EXTI_EMR (STM32_EXTI_BASE+STM32_EXTI_EMR_OFFSET) +# define STM32_EXTI_RTSR (STM32_EXTI_BASE+STM32_EXTI_RTSR_OFFSET) +# define STM32_EXTI_FTSR (STM32_EXTI_BASE+STM32_EXTI_FTSR_OFFSET) +# define STM32_EXTI_SWIER (STM32_EXTI_BASE+STM32_EXTI_SWIER_OFFSET) +# define STM32_EXTI_PR (STM32_EXTI_BASE+STM32_EXTI_PR_OFFSET) +#endif + +/* Register Bitfield Definitions ********************************************/ + +/* EXTI lines > 15 are associated with internal devices: */ + +#if defined(CONFIG_STM32_STM32F10XX) +# define EXTI_PVD_LINE (1 << 16) /* EXTI line 16 is connected to the PVD output */ +# define EXTI_RTC_ALARM (1 << 17) /* EXTI line 17 is connected to the RTC Alarm event */ +# define EXTI_USB_WAKEUP (1 << 18) /* EXTI line 18 is connected to the USB Wakeup event */ +# ifdef CONFIG_STM32_CONNECTIVITYLINE +# define EXTI_ETH_WAKEUP (1 << 19) /* EXTI line 19 is connected to the Ethernet Wakeup event */ +# endif +#elif defined(CONFIG_STM32_STM32L15XX) +# define EXTI_PVD_LINE (1 << 16) /* EXTI line 16 is connected to the PVD output */ +# define EXTI_RTC_ALARM (1 << 17) /* EXTI line 17 is connected to the RTC Alarm event */ +# define EXTI_USB_WAKEUP (1 << 18) /* EXTI line 18 is connected to the USB Device FS Wakeup event */ +# define EXTI_RTC_TAMPER (1 << 19) /* EXTI line 19 is connected to the RTC Tamper and TimeStamp events */ +# define EXTI_RTC_WAKEUP (1 << 20) /* EXTI line 20 is connected to the RTC Wakeup event */ +# define EXTI_COMP1 (1 << 21) /* EXTI line 21 is connected to the Comparator 1 wakeup event */ +# define EXTI_COMP2 (1 << 22) /* EXTI line 22 is connected to the Comparator 2 wakeup event */ +# define EXTI_RTC_ACQUIRE (1 << 23) /* EXTI line 23 is connected to the channel acquisition interrupt */ +#elif defined(CONFIG_STM32_HAVE_IP_EXTI_V1) +# define EXTI_PVD_LINE (1 << 16) /* EXTI line 16 is connected to the PVD output */ +# define EXTI_RTC_ALARM (1 << 17) /* EXTI line 17 is connected to the RTC Alarm event */ +# define EXTI_OTGFS_WAKEUP (1 << 18) /* EXTI line 18 is connected to the USB OTG FS Wakeup event */ +# define EXTI_ETH_WAKEUP (1 << 19) /* EXTI line 19 is connected to the Ethernet Wakeup event */ +# define EXTI_OTGHS_WAKEUP (1 << 20) /* EXTI line 20 is connected to the USB OTG HS Wakeup event */ +# define EXTI_RTC_TAMPER (1 << 21) /* EXTI line 21 is connected to the RTC Tamper and TimeStamp events */ +# define EXTI_RTC_TIMESTAMP (1 << 21) /* EXTI line 21 is connected to the RTC Tamper and TimeStamp events */ +# define EXTI_RTC_WAKEUP (1 << 22) /* EXTI line 22 is connected to the RTC Wakeup event */ +#elif defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) || \ + defined(CONFIG_STM32_STM32F37XX) +# define EXTI_PVD_LINE (1 << 16) /* EXTI line 16 is connected to the PVD output */ +# define EXTI_RTC_ALARM (1 << 17) /* EXTI line 17 is connected to the RTC Alarm event */ +# define EXTI_OTGFS_WAKEUP (1 << 18) /* EXTI line 18 is connected to the USB OTG FS Wakeup event */ +# define EXTI_RTC_TAMPER (1 << 19) /* EXTI line 19 is connected to the RTC Tamper and TimeStamp events */ +# define EXTI_RTC_TIMESTAMP (1 << 19) /* EXTI line 19 is connected to the RTC Tamper and TimeStamp events */ +# define EXTI_RTC_WAKEUP (1 << 20) /* EXTI line 20 is connected to the RTC Wakeup event */ +#elif defined(CONFIG_STM32_STM32G47XX) +# define EXTI_PVD_LINE (1 << 16) /* EXTI line 16 is connected to the PVD output */ +# define EXTI_RTC_ALARM (1 << 17) /* EXTI line 17 is connected to the RTC Alarm event */ +# define EXTI_USB_WAKEUP (1 << 18) /* EXTI line 18 is connected to the USB Device FS Wakeup event */ +# define EXTI_RTC_TIMESTAMP (1 << 19) /* EXTI line 19 is connected to the Timestamp or CSS_LSE events */ +# define EXTI_CSS_LSE (1 << 19) /* EXTI line 19 is connected to the Timestamp or CSS_LSE events */ +# define EXTI_RTC_WAKEUP (1 << 20) /* EXTI line 20 is connected to the RTC Wakeup event */ +# define EXTI_COMP1 (1 << 21) /* EXTI line 21 is connected to the Comparator 1 wakeup event */ +# define EXTI_COMP2 (1 << 22) /* EXTI line 22 is connected to the Comparator 2 wakeup event */ +# define EXTI_I2C1 (1 << 23) /* EXTI line 23 is connected to the I2C1 wakeup event */ +# define EXTI_I2C2 (1 << 24) /* EXTI line 24 is connected to the I2C2 wakeup event */ +# define EXTI_USART1 (1 << 25) /* EXTI line 25 is connected to the USART1 wakeup event */ +# define EXTI_USART2 (1 << 26) /* EXTI line 26 is connected to the USART2 wakeup event */ +# define EXTI_I2C3 (1 << 27) /* EXTI line 27 is connected to the I2C3 wakeup event */ +# define EXTI_USART3 (1 << 28) /* EXTI line 28 is connected to the USART3 wakeup event */ +# define EXTI_COMP3 (1 << 29) /* EXTI line 29 is connected to the Comparator 3 wakeup event */ +# define EXTI_COMP4 (1 << 30) /* EXTI line 30 is connected to the Comparator 4 wakeup event */ +# define EXTI_COMP5 (1 << 31) /* EXTI line 31 is connected to the Comparator 5 wakeup event */ +# define EXTI_COMP6 (1 << 0) /* EXTI line 32 is connected to the Comparator 6 wakeup event */ +# define EXTI_COMP7 (1 << 1) /* EXTI line 33 is connected to the Comparator 7 wakeup event */ +# define EXTI_USART4 (1 << 2) /* EXTI line 34 is connected to the USART4 wakeup event */ +# define EXTI_USART5 (1 << 3) /* EXTI line 35 is connected to the USART5 wakeup event */ +# define EXTI_LPUART1 (1 << 4) /* EXTI line 36 is connected to the LPUART1 wakeup event */ +# define EXTI_LPTIM1 (1 << 5) /* EXTI line 37 is connected to the LPTIM1 wakeup event */ +# define EXTI_PVM1 (1 << 8) /* EXTI line 40 is connected to the PVM1 wakeup event */ +# define EXTI_PVM2 (1 << 9) /* EXTI line 41 is connected to the PVM2 wakeup event */ +# define EXTI_I2C4 (1 << 10) /* EXTI line 42 is connected to the I2C4 wakeup event */ +# define EXTI_UCPD1 (1 << 11) /* EXTI line 43 is connected to the UCPD1 wakeup event */ +#endif + +/* Interrupt mask register */ + +#define EXTI_IMR_BIT(n) STM32_EXTI_BIT(n) /* 1=Interrupt request from line x is not masked */ +#define EXTI_IMR_SHIFT (0) /* Bits 0-X: Interrupt Mask for all lines */ +#define EXTI_IMR_MASK STM32_EXTI_MASK + +/* Event mask register */ + +#define EXTI_EMR_BIT(n) STM32_EXTI_BIT(n) /* 1=Event request from line x is not mask */ +#define EXTI_EMR_SHIFT (0) /* Bits Bits 0-X: Event Mask for all lines */ +#define EXTI_EMR_MASK STM32_EXTI_MASK + +/* Rising Trigger selection register */ + +#define EXTI_RTSR_BIT(n) STM32_EXTI_BIT(n) /* 1=Rising trigger enabled (for Event and Interrupt) for input line */ +#define EXTI_RTSR_SHIFT (0) /* Bits 0-X: Rising trigger event configuration bit for all lines */ +#define EXTI_RTSR_MASK STM32_EXTI_MASK + +/* Falling Trigger selection register */ + +#define EXTI_FTSR_BIT(n) STM32_EXTI_BIT(n) /* 1=Falling trigger enabled (for Event and Interrupt) for input line */ +#define EXTI_FTSR_SHIFT (0) /* Bits 0-X: Falling trigger event configuration bitfor all lines */ +#define EXTI_FTSR_MASK STM32_EXTI_MASK + +/* Software interrupt event register */ + +#define EXTI_SWIER_BIT(n) STM32_EXTI_BIT(n) /* 1=Sets the corresponding pending bit in EXTI_PR */ +#define EXTI_SWIER_SHIFT (0) /* Bits 0-X: Software Interrupt for all lines */ +#define EXTI_SWIER_MASK STM32_EXTI_MASK + +/* Pending register */ + +#define EXTI_PR_BIT(n) STM32_EXTI_BIT(n) /* 1=Selected trigger request occurred */ +#define EXTI_PR_SHIFT (0) /* Bits 0-X: Pending bit for all lines */ +#define EXTI_PR_MASK STM32_EXTI_MASK + +/* Compatibility Definitions ************************************************/ + +#if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) +# define STM32_NEXTI STM32_NEXTI1 +# define STM32_EXTI_MASK STM32_EXTI1_MASK +# define STM32_EXTI_IMR STM32_EXTI1_IMR +# define STM32_EXTI_EMR STM32_EXTI1_EMR +# define STM32_EXTI_RTSR STM32_EXTI1_RTSR +# define STM32_EXTI_FTSR STM32_EXTI1_FTSR +# define STM32_EXTI_SWIER STM32_EXTI1_SWIER +# define STM32_EXTI_PR STM32_EXTI1_PR +#endif + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_EXTI_V1V2_H */ diff --git a/arch/arm/src/common/stm32/hardware/stm32_exti_v1v2_m0.h b/arch/arm/src/common/stm32/hardware/stm32_exti_v1v2_m0.h new file mode 100644 index 0000000000000..3f147d2a17f60 --- /dev/null +++ b/arch/arm/src/common/stm32/hardware/stm32_exti_v1v2_m0.h @@ -0,0 +1,45 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/hardware/stm32_exti_v1v2_m0.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_EXTI_V1V2_M0_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_EXTI_V1V2_M0_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include "chip.h" + +#if defined(CONFIG_ARCH_CHIP_STM32F0) +# include "hardware/stm32f0_exti.h" +#elif defined(CONFIG_ARCH_CHIP_STM32L0) +# include "hardware/stm32l0_exti.h" +#elif defined(CONFIG_ARCH_CHIP_STM32G0) +# include "hardware/stm32g0_exti.h" +#elif defined(CONFIG_ARCH_CHIP_STM32C0) +# include "hardware/stm32c0_exti.h" +#else +# error "Unrecognized STM32 M0 EXTI" +#endif + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_EXTI_V1V2_M0_H */ diff --git a/arch/arm/src/common/stm32/hardware/stm32_fdcan.h b/arch/arm/src/common/stm32/hardware/stm32_fdcan.h new file mode 100644 index 0000000000000..6ce5e34f2aae7 --- /dev/null +++ b/arch/arm/src/common/stm32/hardware/stm32_fdcan.h @@ -0,0 +1,43 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/hardware/stm32_fdcan.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_FDCAN_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_FDCAN_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#if (defined(CONFIG_STM32_HAVE_IP_FDCAN_MCAN_M0_V1) + \ + defined(CONFIG_STM32_HAVE_IP_FDCAN_MCAN_M3M4_V1)) > 1 +# error Only one STM32 FDCAN IP version must be selected +#endif + +#if defined(CONFIG_STM32_HAVE_IP_FDCAN_MCAN_M0_V1) +# include "hardware/stm32_fdcan_mcan_m0.h" +#elif defined(CONFIG_STM32_HAVE_IP_FDCAN_MCAN_M3M4_V1) +# include "hardware/stm32_fdcan_mcan.h" +#else +# error "Unsupported STM32 FDCAN" +#endif + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_FDCAN_H */ diff --git a/arch/arm/src/common/stm32/hardware/stm32_fdcan_mcan.h b/arch/arm/src/common/stm32/hardware/stm32_fdcan_mcan.h new file mode 100644 index 0000000000000..be1f77a5d3a78 --- /dev/null +++ b/arch/arm/src/common/stm32/hardware/stm32_fdcan_mcan.h @@ -0,0 +1,588 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/hardware/stm32_fdcan_mcan.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_FDCAN_MCAN_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_FDCAN_MCAN_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "chip.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Only for STM32G4 */ + +#ifndef CONFIG_STM32_STM32G4XXX +# error STM32 FDCAN was tested only for STM32G4 +#endif + +/* Register Offsets *********************************************************/ + +#define STM32_FDCAN_CREL_OFFSET 0x0000 /* FDCAN core release register */ +#define STM32_FDCAN_ENDN_OFFSET 0x0004 /* FDCAN endian register */ + /* 0x0008 Reserved */ +#define STM32_FDCAN_DBTP_OFFSET 0x000c /* FDCAN data bit timing and prescaler register */ +#define STM32_FDCAN_TEST_OFFSET 0x0010 /* FDCAN test register */ +#define STM32_FDCAN_RWD_OFFSET 0x0014 /* FDCAN RAM watchdog register */ +#define STM32_FDCAN_CCCR_OFFSET 0x0018 /* FDCAN CC control register */ +#define STM32_FDCAN_NBTP_OFFSET 0x001c /* FDCAN nominal bit timing and prescaler register */ +#define STM32_FDCAN_TSCC_OFFSET 0x0020 /* FDCAN timestamp counter configuration register */ +#define STM32_FDCAN_TSCV_OFFSET 0x0024 /* FDCAN timestamp counter value register */ +#define STM32_FDCAN_TOCC_OFFSET 0x0028 /* FDCAN timeout counter configuration register */ +#define STM32_FDCAN_TOCV_OFFSET 0x002c /* FDCAN timeout counter value register */ + /* 0x0030 to 0x003c Reserved */ +#define STM32_FDCAN_ECR_OFFSET 0x0040 /* FDCAN error counter register */ +#define STM32_FDCAN_PSR_OFFSET 0x0044 /* FDCAN protocol status register */ +#define STM32_FDCAN_TDCR_OFFSET 0x0048 /* FDCAN transmitter delay compensation register */ + /* 0x004c Reserved */ +#define STM32_FDCAN_IR_OFFSET 0x0050 /* FDCAN interrupt register */ +#define STM32_FDCAN_IE_OFFSET 0x0054 /* FDCAN interrupt enable register */ +#define STM32_FDCAN_ILS_OFFSET 0x0058 /* FDCAN interrupt line select register */ +#define STM32_FDCAN_ILE_OFFSET 0x005c /* FDCAN interrupt line enable register */ + /* 0x0060 to 0x007c Reserved */ +#define STM32_FDCAN_RXGFC_OFFSET 0x0080 /* FDCAN global filter configuration register */ +#define STM32_FDCAN_XIDAM_OFFSET 0x0084 /* FDCAN extended ID and mask register */ +#define STM32_FDCAN_HPMS_OFFSET 0x0088 /* FDCAN high-priority message status register */ +#define STM32_FDCAN_RXFS_OFFSET(f) (0x0090 + ((f) << 3) +#define STM32_FDCAN_RXFA_OFFSET(f) (0x0094 + ((f) << 3) +#define STM32_FDCAN_RXF0S_OFFSET 0x0090 /* FDCAN Rx FIFO 0 status register */ +#define STM32_FDCAN_RXF0A_OFFSET 0x0094 /* CAN Rx FIFO 0 acknowledge register */ +#define STM32_FDCAN_RXF1S_OFFSET 0x0098 /* FDCAN Rx FIFO 1 status register */ +#define STM32_FDCAN_RXF1A_OFFSET 0x009c /* FDCAN Rx FIFO 1 acknowledge register */ + /* 0x00a0 to 0x00bc Reserved */ +#define STM32_FDCAN_TXBC_OFFSET 0x00c0 /* FDCAN Tx buffer configuration register */ +#define STM32_FDCAN_TXFQS_OFFSET 0x00c4 /* FDCAN Tx FIFO/queue status register */ +#define STM32_FDCAN_TXBRP_OFFSET 0x00c8 /* FDCAN Tx buffer request pending register */ +#define STM32_FDCAN_TXBAR_OFFSET 0x00cc /* FDCAN Tx buffer add request register */ +#define STM32_FDCAN_TXBCR_OFFSET 0x00d0 /* FDCAN Tx buffer cancellation request register */ +#define STM32_FDCAN_TXBTO_OFFSET 0x00d4 /* FDCAN Tx buffer transmission occurred register */ +#define STM32_FDCAN_TXBCNF_OFFSET 0x00d8 /* FDCAN Tx buffer cancellation finished register */ +#define STM32_FDCAN_TXBTIE_OFFSET 0x00dc /* FDCAN Tx buffer transmission interrupt enable register */ +#define STM32_FDCAN_TXBCIE_OFFSET 0x00e0 /* FDCAN Tx buffer cancellation finished interrupt enable register */ +#define STM32_FDCAN_TXEFS_OFFSET 0x00e4 /* FDCAN Tx event FIFO status register */ +#define STM32_FDCAN_TXEFA_OFFSET 0x00e8 /* FDCAN Tx event FIFO acknowledge register */ +#define STM32_FDCAN_CKDIV_OFFSET 0x0100 /* FDCAN CFG clock divider register */ + +/* Register Bitfield Definitions ********************************************/ + +/* FDCAN core release register */ + +#define FDCAN_CREL_DAY_SHIFT (0) /* Bits 0-7: DAY */ +#define FDCAN_CREL_DAY_MASK (0xff << FDCAN_CREL_DAY_SHIFT) +#define FDCAN_CREL_MON_SHIFT (8) /* Bits 8-15: MON */ +#define FDCAN_CREL_MON_MASK (0xff << FDCAN_CREL_MON_SHIFT) +#define FDCAN_CREL_YEAR_SHIFT (16) /* Bits 8-15: YEAR */ +#define FDCAN_CREL_YEAR_MASK (0x0f << FDCAN_CREL_YEAR_SHIFT) +#define FDCAN_CREL_SUBSTEP_SHIFT (20) /* Bits 20-23: SUBSTEP */ +#define FDCAN_CREL_SUBSTEP_MASK (0x0f << FDCAN_CREL_SUBSTEP_SHIFT) +#define FDCAN_CREL_STEP_SHIFT (24) /* Bits 24-27: STEP */ +#define FDCAN_CREL_STEP_MASK (0x0f << FDCAN_CREL_STEP_SHIFT) +#define FDCAN_CREL_REL_SHIFT (28) /* Bits 28-31: REL */ +#define FDCAN_CREL_REL_MASK (0x0f << FDCAN_CREL_REL_SHIFT) + +/* FDCAN data bit timing and prescaler register */ + +#define FDCAN_DBTP_DSJW_SHIFT (0) /* Bits 0-3: Synchronization jump width */ +#define FDCAN_DBTP_DSJW_MASK (0x0f << FDCAN_DBTP_DSJW_SHIFT) +# define FDCAN_DBTP_DSJW(value) ((value) << FDCAN_DBTP_DSJW_SHIFT) +# define FDCAN_DBTP_DSJW_MAX (15) +#define FDCAN_DBTP_DTSEG2_SHIFT (4) /* Bits 4-7: Data time segment after sample point*/ +#define FDCAN_DBTP_DTSEG2_MASK (0x0f << FDCAN_DBTP_DTSEG2_SHIFT) +# define FDCAN_DBTP_DTSEG2(value) ((value) << FDCAN_DBTP_DTSEG2_SHIFT) +# define FDCAN_DBTP_DTSEG2_MAX (15) +#define FDCAN_DBTP_DTSEG1_SHIFT (8) /* Bits 8-12: Data time segment before sample point*/ +#define FDCAN_DBTP_DTSEG1_MASK (0x1f << FDCAN_DBTP_DTSEG1_SHIFT) +# define FDCAN_DBTP_DTSEG1(value) ((value) << FDCAN_DBTP_DTSEG1_SHIFT) +# define FDCAN_DBTP_DTSEG1_MAX (31) +#define FDCAN_DBTP_DBRP_SHIFT (16) /* Bits 16-20: Data bitrate prescaler */ +#define FDCAN_DBTP_DBRP_MASK (0x1f << FDCAN_DBTP_DBRP_SHIFT) +# define FDCAN_DBTP_DBRP(value) ((value) << FDCAN_DBTP_DBRP_SHIFT) +# define FDCAN_DBTP_DBRP_MAX (31) +#define FDCAN_DBTP_TDC_EN (1 << 23) /* Bit 23: Transceiver delay compensation enable */ + +/* FDCAN test register */ + +#define FDCAN_TEST_LBCK (1 << 4) /* Bit 4: Loop back mode */ +#define FDCAN_TEST_TX_SHIFT (5) /* Bits 5-6: Control of transmit pin */ +#define FDCAN_TEST_TX_MASK (0x3 << FDCAN_TEST_TX_SHIFT) +# define FDCAN_TEST_TX_RESET (0 << FDCAN_TEST_TX_SHIFT) /* 00: TX is controlled by CAN core */ +# define FDCAN_TEST_TX_SP (1 << FDCAN_TEST_TX_SHIFT) /* 01: Sample point can be monitored at TX pin */ +# define FDCAN_TEST_TX_DLVL (2 << FDCAN_TEST_TX_SHIFT) /* 10: Dominant (0) level at TX pin */ +# define FDCAN_TEST_TX_RLVL (3 << FDCAN_TEST_TX_SHIFT) /* 11: Recesive (1) level at TX pin */ +#define FDCAN_TEST_RX (1 << 7) /* Bit 7: Receive pin */ + +/* FDCAN RAM watchdog register */ + +#define FDCAN_RWD_WDC_SHIFT (0) /* Bits 0-7: RAM watchdog counter start value */ +#define FDCAN_RWD_WDC_MASK (0xff << FDCAN_RWD_WDC_SHIFT) +# define FDCAN_RWD_WDC_DIS (0 << FDCAN_RWD_WDC_SHIFT) /* Counter disabled */ +# define FDCAN_RWD_WDC(value) ((value) << FDCAN_RWD_WDC_SHIFT) +#define FDCAN_RWD_WDV_SHIFT (8) /* Bits 8-15: RAM watchdog counter value */ +#define FDCAN_RWD_WDV_MASK (0xff << FDCAN_RWD_WDV_SHIFT) + +/* FDCAN CC control register */ + +#define FDCAN_CCCR_INIT (1 << 0) /* Bit 0: Initialization */ +#define FDCAN_CCCR_CCE (1 << 1) /* Bit 1: Configuration change enable */ +#define FDCAN_CCCR_ASM (1 << 2) /* Bit 2: ASM restricted operation mode */ +#define FDCAN_CCCR_CSA (1 << 3) /* Bit 3: Clock stop acknowledge */ +#define FDCAN_CCCR_CSR (1 << 4) /* Bit 4: Clock stop request */ +#define FDCAN_CCCR_MON (1 << 5) /* Bit 5: Bus monitoring mode */ +#define FDCAN_CCCR_DAR (1 << 6) /* Bit 6: Disable automatic retransmission */ +#define FDCAN_CCCR_TEST (1 << 7) /* Bit 7: Test mode enable */ +#define FDCAN_CCCR_FDOE (1 << 8) /* Bit 8: FD operation enable */ +#define FDCAN_CCCR_BRSE (1 << 9) /* Bit 9: FDCAN Bitrate switching */ + /* Bits 10-11: Reserved */ +#define FDCAN_CCCR_PXHD (1 << 12) /* Bit 12: Protocol exception handling disable */ +#define FDCAN_CCCR_EFBI (1 << 13) /* Bit 13: Edge filtering during bus integration */ +#define FDCAN_CCCR_TXP (1 << 14) /* Bit 14: Tx pause */ +#define FDCAN_CCCR_NISO (1 << 15) /* Bit 15: Non ISO operation */ + +/* FDCAN nominal bit timing and prescaler register */ + +#define FDCAN_NBTP_NTSEG2_SHIFT (0) /* Bits 0-6: Nominal time segment after sample point */ +#define FDCAN_NBTP_NTSEG2_MASK (0x7f << FDCAN_NBTP_NTSEG2_SHIFT) +# define FDCAN_NBTP_NTSEG2(value) ((value) << FDCAN_NBTP_NTSEG2_SHIFT) +# define FDCAN_NBTP_NTSEG2_MAX (127) +#define FDCAN_NBTP_NTSEG1_SHIFT (8) /* Bits 8-15: Nominal time segment before sample point */ +#define FDCAN_NBTP_NTSEG1_MASK (0xff << FDCAN_NBTP_NTSEG1_SHIFT) +# define FDCAN_NBTP_NTSEG1(value) ((value) << FDCAN_NBTP_NTSEG1_SHIFT) +# define FDCAN_NBTP_NTSEG1_MAX (255) +#define FDCAN_NBTP_NBRP_SHIFT (16) /* Bits 16-24: Bitrate prescaler */ +#define FDCAN_NBTP_NBRP_MASK (0x1ff << FDCAN_NBTP_NBRP_SHIFT) +# define FDCAN_NBTP_NBRP(value) ((value) << FDCAN_NBTP_NBRP_SHIFT) +# define FDCAN_NBTP_NBRP_MAX (511) +#define FDCAN_NBTP_NSJW_SHIFT (25) /* Bits 25-31: Nominal (re)synchronization jump width */ +#define FDCAN_NBTP_NSJW_MASK (0x7f << FDCAN_NBTP_NSJW_SHIFT) +# define FDCAN_NBTP_NSJW(value) ((value) << FDCAN_NBTP_NSJW_SHIFT) +# define FDCAN_NBTP_NSJW_MAX (127) + +/* FDCAN timestamp counter configuration register */ + +#define FDCAN_TSCC_TSS_SHIFT (0) /* Bits 0-1: Timestamp counter select */ +#define FDCAN_TSCC_TSS_MASK (0x3 << FDCAN_TSCC_TSS_SHIFT) +# define FDCAN_TSCC_TSS_ZERO (0 << FDCAN_TSCC_TSS_SHIFT) /* 00: Always 0 */ +# define FDCAN_TSCC_TSS_TCP (1 << FDCAN_TSCC_TSS_SHIFT) /* 01: Incremented based on TCP */ +# define FDCAN_TSCC_TSS_TIM3 (2 << FDCAN_TSCC_TSS_SHIFT) /* 10: Value from TIM3 used */ +#define FDCAN_TSCC_TCP_SHIFT (16) /* Bits 16-19: Timestamp counter prescaler */ +#define FDCAN_TSCC_TCP_MASK (0x0f << FDCAN_TSCC_TCP_SHIFT) +# define FDCAN_TSCC_TCP(value) ((value) << FDCAN_TSCC_TCP_SHIFT) + +/* FDCAN timestamp counter value register */ + +#define FDCAN_TSCV_TSC_SHIFT (0) /* Bits 0-15: Timestamp counter */ +#define FDCAN_TSCV_TSC_MASK (0xffff << FDCAN_TSCV_TSC_SHIFT) + +/* FDCAN timeout counter configuration register */ + +#define FDCAN_TOCC_ETOC (1 << 0) /* Bit 0: Enable timeout counter */ +#define FDCAN_TOCC_TOS_SHIFT (1) /* Bits 1-2: Timeout select */ +#define FDCAN_TOCC_TOS_MASK (0x03 << FDCAN_TOCC_TOS_SHIFT) +# define FDCAN_TOCC_TOS_CONT (0 << FDCAN_TOCC_TOS_SHIFT) /* 00: Continuous operation */ +# define FDCAN_TOCC_TOS_TXFIFO (1 << FDCAN_TOCC_TOS_SHIFT) /* 01: Tx event FIFO */ +# define FDCAN_TOCC_TOS_RX_FIFO0 (2 << FDCAN_TOCC_TOS_SHIFT) /* 10: Rx FIFO 0 */ +# define FDCAN_TOCC_TOS_RX_FIFO1 (3 << FDCAN_TOCC_TOS_SHIFT) /* 11: Rx FIFO 1 */ +#define FDCAN_TOCC_TOP_SHIFT (16) /* Bits 16-31: Timeout period counter start value */ +#define FDCAN_TOCC_TOP_MASK (0xffff << FDCAN_TOCC_TOP_SHIFT) +# define FDCAN_TOCC_TOP(value) ((value) << FDCAN_TOCC_TOP_SHIFT) + +/* FDCAN timeout counter value register */ + +#define FDCAN_TOCV_TOC_SHIFT (0) /* Bits 0-15: Timestamp counter */ +#define FDCAN_TOCV_TOC_MASK (0xffff << FDCAN_TOCV_TOC_SHIFT) + +/* FDCAN error counter register */ + +#define FDCAN_ECR_TEC_SHIFT (0) /* Bits 0-7: Transmit error counter */ +#define FDCAN_CR_TEC_MASK (0xff << FDCAN_ECR_TEC_SHIFT) +#define FDCAN_ECR_REC_SHIFT (8) /* Bits 8-14: Receive error counter */ +#define FDCAN_ECR_REC_MASK (0x7f << FDCAN_ECR_REC_SHIFT) +#define FDCAN_ECR_RP (1 << 15) /* Bit 15: Receive error passive */ +#define FDCAN_ECR_CEL_SHIFT (16) /* Bits 16-23: CAN error logging */ +#define FDCAN_ECR_CEL_MASK (0xff << FDCAN_ECR_CEL_SHIFT) + +/* FDCAN protocol status register */ + +/* Error codes */ + +#define FDCAN_PSR_EC_NO_ERROR (0) /* No error occurred since LEC has been reset */ +#define FDCAN_PSR_EC_STUFF_ERROR (1) /* More than 5 equal bits in a sequence */ +#define FDCAN_PSR_EC_FORM_ERROR (2) /* Part of a received frame has wrong format */ +#define FDCAN_PSR_EC_ACK_ERROR (3) /* Message not acknowledged by another node */ +#define FDCAN_PSR_EC_BIT1_ERROR (4) /* Send with recessive level, but bus value was dominant */ +#define FDCAN_PSR_EC_BIT0_ERROR (5) /* Send with dominant level, but bus value was recessive */ +#define FDCAN_PSR_EC_CRC_ERROR (6) /* CRC received message incorrect */ +#define FDCAN_PSR_EC_NO_CHANGE (7) /* No CAN bus event was detected since last read */ + +#define FDCAN_PSR_LEC_SHIFT (0) /* Bits 0-2: Last error code */ +#define FDCAN_PSR_LEC_MASK (0x7 << FDCAN_PSR_LEC_SHIFT) +# define FDCAN_PSR_LEC(n) ((uint32_t)(n) << FDCAN_PSR_LEC_SHIFT) /* See error codes above */ +#define FDCAN_PSR_ACT_SHIFT (3) /* Bits 3-4: Activity */ +#define FDCAN_PSR_ACT_MASK (3 << FDCAN_PSR_ACT_SHIFT) +# define FDCAN_PSR_ACT_SYNC (0 << FDCAN_PSR_ACT_SHIFT) /* 00: Synchronizing */ +# define FDCAN_PSR_ACT_IDLE (1 << FDCAN_PSR_ACT_SHIFT) /* 01: Idle */ +# define FDCAN_PSR_ACT_RECV (2 << FDCAN_PSR_ACT_SHIFT) /* 10: Receiver */ +# define FDCAN_PSR_ACT_TRANS (3 << FDCAN_PSR_ACT_SHIFT) /* 11: Transmitter */ +#define FDCAN_PSR_EP (1 << 5) /* Bit 5: Error passive */ +#define FDCAN_PSR_EW (1 << 6) /* Bit 6: Warning status */ +#define FDCAN_PSR_BO (1 << 7) /* Bit 7: Bus_off status */ +#define FDCAN_PSR_DLEC_SHIFT (8) /* Bits 8-10: Data last error code */ +#define FDCAN_PSR_DLEC_MASK (0x7 << FDCAN_PSR_DLEC_SHIFT) +# define FDCAN_PSR_DLEC(n) ((uint32_t)(n) << FDCAN_PSR_DLEC_SHIFT) /* See error codes above */ +#define FDCAN_PSR_RESI (1 << 11) /* Bit 11: ESI flag of last message */ +#define FDCAN_PSR_RBRS (1 << 12) /* Bit 12: BRS flag of last message */ +#define FDCAN_PSR_REDL (1 << 13) /* Bit 13: Received message */ +#define FDCAN_PSR_PXE (1 << 14) /* Bit 14: Protocol exception event */ +#define FDCAN_PSR_TDCV_SHIFT (16) /* Bits 16-22: Transmitter delay compensation */ +#define FDCAN_PSR_TDCV_MASK (0x7f << FDCAN_PSR_TDCV_SHIFT) + +/* FDCAN transmitter delay compensation register */ + +#define FDCAN_TDCR_TDCF_SHIFT (0) /* Bits 0-6: Transmitter delay compensation filter window length */ +#define FDCAN_TDCR_TDCF_MASK (0x7f << FDCAN_TDCR_TDCF_SHIFT) +# define FDCAN_TDCR_TDCF(value) ((value) << FDCAN_TDCR_TDCF_SHIFT) +#define FDCAN_TDCR_TDCO_SHIFT (8) /* Bits 8-14: Transmiiter delay compensation offset */ +#define FDCAN_TDCR_TDCO_MASK (0x7f << FDCAN_TDCR_TDCO_SHIFT) +# define FDCAN_TDCR_TDCO(value) ((value) << FDCAN_TDCR_TDCO_SHIFT) + +/* FDCAN interrupt register and interrupt enable register */ + +#define FDCAN_INT_RF0N (1 << 0) /* Bit 0: Rx FIFO 0 new message */ +#define FDCAN_INT_RF0F (1 << 1) /* Bit 1: Rx FIFO 0 full */ +#define FDCAN_INT_RF0L (1 << 2) /* Bit 2: Rx FIFO 0 message lost */ +#define FDCAN_INT_RF1N (1 << 3) /* Bit 3: Rx FIFO 1 new message */ +#define FDCAN_INT_RF1F (1 << 4) /* Bit 4: Rx FIFO 1 full */ +#define FDCAN_INT_RF1L (1 << 5) /* Bit 5: Rx FIFO 1 message lost */ +#define FDCAN_INT_HPM (1 << 6) /* Bit 6: High priority message */ +#define FDCAN_INT_TC (1 << 7) /* Bit 7: Transmission completed */ +#define FDCAN_INT_TCF (1 << 8) /* Bit 8: Transmission cancellation finished */ +#define FDCAN_INT_TFE (1 << 9) /* Bit 9: Tx FIFO empty */ +#define FDCAN_INT_TEFN (1 << 10) /* Bit 10: Tx event FIFO new entry */ +#define FDCAN_INT_TEFF (1 << 11) /* Bit 11: Tx event FIFO full */ +#define FDCAN_INT_TEFL (1 << 12) /* Bit 12: Tx event FIFO element lost */ +#define FDCAN_INT_TSW (1 << 13) /* Bit 13: Timestamp wraparound */ +#define FDCAN_INT_MRAF (1 << 14) /* Bit 14: Message RAM access failure */ +#define FDCAN_INT_TOO (1 << 15) /* Bit 15: Timeout occurred */ +#define FDCAN_INT_ELO (1 << 16) /* Bit 16: Error logging overflow */ +#define FDCAN_INT_EP (1 << 17) /* Bit 17: Error_passive status */ +#define FDCAN_INT_EW (1 << 18) /* Bit 18: Error_warning status */ +#define FDCAN_INT_BO (1 << 19) /* Bit 19: Buss_off status */ +#define FDCAN_INT_WDI (1 << 20) /* Bit 20: Watchdog interrupt */ +#define FDCAN_INT_PEA (1 << 21) /* Bit 21: Protocol error arbitration phase */ +#define FDCAN_INT_PED (1 << 22) /* Bit 22: Protocol error data phase */ +#define FDCAN_INT_ARA (1 << 23) /* Bit 23: Access to reserved address */ + +/* FDCAN interrupt line select register */ + +#define FDCAN_ILS_RXFIFO0 (1 << 0) /* Bit 0: RXFIFO 0 */ +#define FDCAN_ILS_RXFIFO1 (1 << 1) /* Bit 1: RXFIFO 1 */ +#define FDCAN_ILS_SMG (1 << 2) /* Bit 2: SMSG */ +#define FDCAN_ILS_TFERR (1 << 3) /* Bit 3: TFERR */ +#define FDCAN_ILS_MISC (1 << 4) /* Bit 4: MISC */ +#define FDCAN_ILS_BERR (1 << 5) /* Bit 5: BERR */ +#define FDCAN_ILS_PERR (1 << 6) /* Bit 6: PERR */ + +/* FDCAN interrupt line enable register */ + +#define FDCAN_ILE_EINT0 (1 << 0) /* Bit 0: Enable interrupt line 0 */ +#define FDCAN_ILE_EINT1 (1 << 1) /* Bit 1: Enable interrupt line 1 */ + +/* FDCAN global filter configuration register */ + +#define FDCAN_RXGFC_RRFE (1 << 0) /* Bit 0: Reject remote frames ext */ +#define FDCAN_RXGFC_RRFS (1 << 1) /* Bit 1: Reject remote frames std */ +#define FDCAN_RXGFC_ANFE_SHIFT (2) /* Bits 2-3: Accept non-matching frames ext */ +#define FDCAN_RXGFC_ANFE_MASK (0x3 << FDCAN_RXGFC_ANFE_SHIFT) +# define FDCAN_RXGFC_ANFE_RX_FIFO0 (0 << FDCAN_RXGFC_ANFE_SHIFT) /* 00: Accept in Rx FIFO 0 */ +# define FDCAN_RXGFC_ANFE_RX_FIFO1 (1 << FDCAN_RXGFC_ANFE_SHIFT) /* 01: Accept in Rx FIFO 1 */ +# define FDCAN_RXGFC_ANFE_REJECTED (2 << FDCAN_RXGFC_ANFE_SHIFT) /* 10: Reject */ +#define FDCAN_RXGFC_ANFS_SHIFT (4) /* Bits 5-4: Accept non-matching frames std */ +#define FDCAN_RXGFC_ANFS_MASK (0x3 << FDCAN_RXGFC_ANFS_SHIFT) +# define FDCAN_RXGFC_ANFS_RX_FIFO0 (0 << FDCAN_RXGFC_ANFS_SHIFT) /* 00: Accept in Rx FIFO 0 */ +# define FDCAN_RXGFC_ANFS_RX_FIFO1 (1 << FDCAN_RXGFC_ANFS_SHIFT) /* 01: Accept in Rx FIFO 1 */ +# define FDCAN_RXGFC_ANFS_REJECTED (2 << FDCAN_RXGFC_ANFS_SHIFT) /* 10: Reject */ +#define FDCAN_RXGFC_F1OM (1 << 8) /* Bit 8: FIFO 1 operation mode */ +#define FDCAN_RXGFC_F0OM (1 << 9) /* Bit 9: FIFO 0 operation mode */ +#define FDCAN_RXGFC_LSS_SHIFT (16) /* Bits 16-20: List size std */ +#define FDCAN_RXGFC_LSS_MASK (0x1f << FDCAN_RXGFC_LSS_SHIFT) +# define FDCAN_RXGFC_LSS(value) ((value) << FDCAN_RXGFC_LSS_SHIFT) +# define FDCAN_RXGFC_LSS_MAX (28) +#define FDCAN_RXGFC_LSE_SHIFT (24) /* Bits 24-27: List size ext */ +#define FDCAN_RXGFC_LSE_MASK (0x1f << FDCAN_RXGFC_LSE_SHIFT) +# define FDCAN_RXGFC_LSE(value) ((value) << FDCAN_RXGFC_LSE_SHIFT) +# define FDCAN_RXGFC_LSE_MAX (8) + +/* FDCAN extended ID and mask register */ + +#define FDCAN_XIDAM_EIDM_SHIFT (0) /* Bits 0-28: Extended ID mask */ +#define FDCAN_XIDAM_EIDM_MASK (0x1fffffff << FDCAN_XIDAM_EIDM_SHIFT) + +/* FDCAN high-priority message status register */ + +#define FDCAN_HPMS_BIDX_SHIFT (0) /* Bits 0-2: Buffer index */ +#define FDCAN_HPMS_BIDX_MASK (0x7 << FDCAN_HPMS_BIDX_SHIFT) +# define FDCAN_HPMS_BIDX(value) ((value) << FDCAN_HPMS_BIDX_SHIFT) +#define FDCAN_HPMS_MSI_SHIFT (6) /* Bits 6-7: Message storage indicator */ +#define FDCAN_HPMS_MSI_MASK (0x3 << FDCAN_HPMS_MSI_SHIFT) +# define FDCAN_HPMS_MSI(value) ((value) << FDCAN_HPMS_MSI_SHIFT) +#define FDCAN_HPMS_FIDX_SHIFT (8) /* Bits 8-12: Filter index */ +#define FDCAN_HPMS_FIDX_MASK (0x1f << FDCAN_HPMS_FIDX_SHIFT) +# define FDCAN_HPMS_FIDX(value) ((value) << FDCAN_HPMS_FIDX_SHIFT) +#define FDCAN_HPMS_FLST (1 << 15) /* Bit 15: Filter list */ + +/* FDCAN Rx FIFO x status register */ + +#define FDCAN_RXFS_FFL_SHIFT (0) /* Bits 0-3: FIFO fill level */ +#define FDCAN_RXFS_FFL_MASK (0xf << FDCAN_RXFS_FFL_SHIFT) +# define FDCAN_RXFS_FFL(value) ((value) << FDCAN_RXFS_FFL_SHIFT) +#define FDCAN_RXFS_FGI_SHIFT (8) /* Bits 8-9: FIFO get index */ +#define FDCAN_RXFS_FGI_MASK (0x3 << FDCAN_RXFS_FGI_SHIFT) +# define FDCAN_RXFS_FGI(value) ((value) << FDCAN_RXFS_FGI_SHIFT) +#define FDCAN_RXFS_FPI_SHIFT (16) /* Bits 16-17: FIFO put index */ +#define FDCAN_RXFS_FPI_MASK (0x3 << FDCAN_RXFS_FPI_SHIFT) +# define FDCAN_RXFS_FPI(value) ((value) << FDCAN_RXFS_FPI_SHIFT) +#define FDCAN_RXFS_FF (1 << 24) /* Bit 24: FIFO full */ +#define FDCAN_RXFS_RFL (1 << 25) /* Bit 25: FIFO message lost */ + +/* FDCAN Rx FIFO x acknowledge register */ + +#define FDCAN_RXFA_FAI_SHIFT (0) /* Bits 0-2: FIFO 0 acknowledge index */ +#define FDCAN_RXFA_FAI_MASK (0x7 << FDCAN_RXFA_FAI_SHIFT) + +/* FDCAN Tx buffer configuration register */ + +#define FDCAN_TXBC_TFQM (1 << 24) /* Bit 24: FIFO/queue mode */ + +/* FDCAN Tx FIFO/queue status register */ + +#define FDCAN_TXFQS_TFFL_SHIFT (0) /* Bits 0-2: FIFO free level */ +#define FDCAN_TXFQS_TFFL_MASK (0x7 << FDCAN_TXFQS_TFFL_SHIFT) +#define FDCAN_TXFQS_TFGI_SHIFT (8) /* Bits 8-9: FIFO get index */ +#define FDCAN_TXFQS_TFGI_MASK (0x3 << FDCAN_TXFQS_TFGI_SHIFT) +#define FDCAN_TXFQS_TFQPI_SHIFT (16) /* Bits 20-16: FIFO/queue put index */ +#define FDCAN_TXFQS_TFQPI_MASK (0x3 << FDCAN_TXFQS_TFQPI_SHIFT) +#define FDCAN_TXFQS_TFQF (1 << 21) /* Bit 21: FIFO/queue full */ + +/* FDCAN Tx buffer request pending register */ + +#define FDCAN_TXBRP_TRP_SHIFT (0) /* Bits 0-2: Transmission request pending */ +#define FDCAN_TXBRP_TRP_MASK (0x7 << FDCAN_TXBRP_TRP_SHIFT) +# define FDCAN_TXBRP_TRP(value) ((value) << FDCAN_TXBRP_TRP_SHIFT) + +/* FDCAN Tx buffer add request register */ + +#define FDCAN_TXBAR_AR_SHIFT (0) /* Bits 0-2: Add request */ +#define FDCAN_TXBAR_AR_MASK (0x7 << FDCAN_TXBAR_AR_SHIFT) +# define FDCAN_TXBAR_AR(value) ((value) << FDCAN_TXBAR_AR_SHIFT) + +/* FDCAN Tx buffer cancellation request register */ + +#define FDCAN_TXBCR_CR_SHIFT (0) /* Bits 0-2: Cancellation request */ +#define FDCAN_TXBCR_CR_MASK (0x7 << FDCAN_TXBCR_CR_SHIFT) +# define FDCAN_TXBCR_CR(value) ((value) << FDCAN_TXBCR_CR_SHIFT) + +/* FDCAN Tx buffer transmission occurred register */ + +#define FDCAN_TXBTO_TO_SHIFT (0) /* Bits 0-2: Transmission occurred */ +#define FDCAN_TXBTO_TO_MASK (0x7 << FDCAN_TXBTO_TO_SHIFT) + +/* FDCAN Tx buffer cancellation finished register */ + +#define FDCAN_TXBCF_CF_SHIFT (0) /* Bits 0-2: Cancellation finished */ +#define FDCAN_TXBCF_CF_MASK (0x7 << FDCAN_TXBCF_CF_SHIFT) + +/* FDCAN Tx buffer transmission interrupt enable register */ + +#define FDCAN_TXBTIE_TIE_SHIFT (0) /* Bits 0-2: Transmission interrupt enable */ +#define FDCAN_TXBTIE_TIE_MASK (0x7 << FDCAN_TXBTIE_TIE_SHIFT) +# define FDCAN_TXBTIE_TIE(value) ((value) << FDCAN_TXBTIE_TIE_SHIFT) + +/* FDCAN Tx buffer cancellation finished interrupt enable register */ + +#define FDCAN_TXBCIE_CFIE_SHIFT (0) /* Bits 0-2: Cancellation finished interrupt enable */ +#define FDCAN_TXBCIE_CFIE_MASK (0x7 << FDCAN_TXBCIE_CFIE_SHIFT) +# define FDCAN_TXBCIE_CFIE(value) ((value) << FDCAN_TXBCIE_CFIE_SHIFT) + +/* FDCAN Tx event FIFO status register */ + +#define FDCAN_TXEFS_EFFL_SHIFT (2) /* Bits 0-2: Event FIFO fill level */ +#define FDCAN_TXEFS_EFFL_MASK (0x7 << FDCAN_TXEFC_EFFL_SHIFT) +# define FDCAN_TXEFC_EFFL(value) ((value) << FDCAN_TXEFC_EFFL_SHIFT) +#define FDCAN_TXEFS_EFGI_SHIFT (8) /* Bits 8-9: Event FIFO get index */ +#define FDCAN_TXEFS_EFGI_MASK (0x3 << FDCAN_TXEFS_EFGI_SHIFT) +# define FDCAN_TXEFS_EFGI(value) ((value) << FDCAN_TXEFS_EFGI_SHIFT) +#define FDCAN_TXEFS_EFPI_SHIFT (16) /* Bits 16-17: Event FIFO put index */ +#define FDCAN_TXEFS_EFPI_MASK (0x3 << FDCAN_TXEFS_EFPI_SHIFT) +# define FDCAN_TXEFS_EFPI(value) ((value) << FDCAN_TXEFS_EFPI_SHIFT) +#define FDCAN_TXEFS_EFF (1 << 24) /* Bit 24: Event FIFO full */ +#define FDCAN_TXEFS_TEFL (1 << 25) /* Bit 25: Tx Event FIFO element lost */ + /* Bits 26-31: Reserved */ + +/* FDCAN Tx event FIFO acknowledge register */ + +#define FDCAN_TXEFA_EFAI_SHIFT (0) /* Bits 0-3: Event FIFO acknowledge index */ +#define FDCAN_TXEFA_EFAI_MASK (0x3 << FDCAN_TXEFA_EFAI_SHIFT) + +/* FDCAN CFG clock divider register */ + +#define FDCAN_CKDIV_PDIV_SHIFT (0) /* Bits 0-3: Input clock divider */ +#define FDCAN_CKDIV_PDIV_MASK (0xf << FDCAN_CKDIV_PDIV_SHIFT) + +/* Message RAM Definitions **************************************************/ + +/* Common Buffer and FIFO element bit definitions: + * + * --------------- ------------------- -------------------------------- + * RESOURCE R0 R1 + * --------------- ------------------- -------------------------------- + * RX FIFO: ESI, XTD, RTR, ID, ANMF, FIDX, EDL, BRS, DLC, RXTS + * TX buffer: XTD, RTR, ID, MM, EFC, DLC + * TX Event FIFO: ESI, XTD, RTR, ID, MM, ET, EDL, BRS, DLC, TXTS + * --------------- ------------------- -------------------------------- + */ + +/* Common */ + +#define BUFFER_R0_EXTID_SHIFT (0) /* Bits 0-28: Extended identifier */ +#define BUFFER_R0_EXTID_MASK (0x1fffffff << BUFFER_R0_EXTID_SHIFT) +# define BUFFER_R0_EXTID(n) ((uint32_t)(n) << BUFFER_R0_EXTID_SHIFT) +#define BUFFER_R0_STDID_SHIFT (18) /* Bits 18-28: Standard identifier */ +#define BUFFER_R0_STDID_MASK (0x7ff << BUFFER_R0_STDID_SHIFT) +# define BUFFER_R0_STDID(n) ((uint32_t)(n) << BUFFER_R0_STDID_SHIFT) +#define BUFFER_R0_RTR (1 << 29) /* Bit 29: Remote Transmission Request */ +#define BUFFER_R0_XTD (1 << 30) /* Bit 30: Extended Identifier */ +#define BUFFER_R0_ESI (1 << 31) /* Bit 31: Error State Indicator */ + +/* Common */ + +#define BUFFER_R1_DLC_SHIFT (16) /* Bits 16-19: Date length code */ +#define BUFFER_R1_DLC_MASK (15 << BUFFER_R1_DLC_SHIFT) +# define BUFFER_R1_DLC(n) ((uint32_t)(n) << BUFFER_R1_DLC_SHIFT) +#define BUFFER_R1_BRS (1 << 20) /* Bit 20: Bit Rate Switch */ +#define BUFFER_R1_FDF (1 << 21) /* Bit 21: FD Format */ + +/* RX buffer/RX FIFOs */ + +#define BUFFER_R1_RXTS_SHIFT (0) /* Bits 0-15: RX Timestamp */ +#define BUFFER_R1_RXTS_MASK (0xffff << BUFFER_R1_RXTS_SHIFT) +# define BUFFER_R1_RXTS(n) ((uint32_t)(n) << BUFFER_R1_RXTS_SHIFT) +#define BUFFER_R1_FIDX_SHIFT (24) /* Bits 24-30: Filter index */ +#define BUFFER_R1_FIDX_MASK (0x7f << BUFFER_R1_FIDX_SHIFT) +# define BUFFER_R1_FIDX(n) ((uint32_t)(n) << BUFFER_R1_FIDX_SHIFT) +#define BUFFER_R1_ANMF (1 << 31) /* Bit 31: Accepted Non-matching Frame */ + +/* TX buffer/TX Event FIFO */ + +#define BUFFER_R1_MM_SHIFT (24) /* Bits 24-31: Message Marker */ +#define BUFFER_R1_MM_MASK (0xff << BUFFER_R1_MM_SHIFT) +# define BUFFER_R1_MM(n) ((uint32_t)(n) << BUFFER_R1_MM_SHIFT) + +/* TX buffer */ + +#define BUFFER_R1_EFC (1 << 23) /* Bit 23: Event FIFO Control */ + +/* TX Event FIFO */ + +#define BUFFER_R1_TXTS_SHIFT (0) /* Bits 0-15: TX Timestamp */ +#define BUFFER_R1_TXTS_MASK (0xffff << BUFFER_R1_TXTS_SHIFT) +# define BUFFER_R1_TXTS(n) ((uint32_t)(n) << BUFFER_R1_TXTS_SHIFT) +#define BUFFER_R1_EDL (1 << 21) /* Bit 21: Extended Data Length */ +#define BUFFER_R1_ET_SHIFT (22) /* Bits 22-23: Event Type */ +#define BUFFER_R1_ET_MASK (3 << BUFFER_R1_ET_SHIFT) +# define BUFFER_R1_ET_TXEVENT (1 << BUFFER_R1_ET_SHIFT) /* Tx event */ +# define BUFFER_R1_ET_TXCANCEL (2 << BUFFER_R1_ET_SHIFT) /* Transmission despite cancellation */ + +/* Standard Message ID Filter Element */ + +#define STDFILTER_S0_SFID2_SHIFT (0) /* Bits 0-10: Standard Filter ID 2 */ +#define STDFILTER_S0_SFID2_MASK (0x7ff << STDFILTER_S0_SFID2_SHIFT) +# define STDFILTER_S0_SFID2(n ) ((uint32_t)(n) << STDFILTER_S0_SFID2_SHIFT) +#define STDFILTER_S0_BUFFER_SHIFT (0) /* Bits 0-5: RX buffer start address */ +#define STDFILTER_S0_BUFFER_MASK (63 << STDFILTER_S0_BUFFER_SHIFT) +# define STDFILTER_S0_BUFFER(n) ((uint32_t)(n) << STDFILTER_S0_BUFFER_SHIFT) +#define STDFILTER_S0_ACTION_SHIFT (9) /* Bits 9-10: Action taken */ +#define STDFILTER_S0_ACTION_MASK (3 << STDFILTER_S0_ACTION_SHIFT) +# define STDFILTER_S0_RXBUFFER (0 << STDFILTER_S0_ACTION_SHIFT) /* Store message in a Rx buffer */ +# define STDFILTER_S0_DEBUGA (1 << STDFILTER_S0_ACTION_SHIFT) /* Debug Message A */ +# define STDFILTER_S0_DEBUGB (2 << STDFILTER_S0_ACTION_SHIFT) /* Debug Message B */ +# define STDFILTER_S0_DEBUGC (3 << STDFILTER_S0_ACTION_SHIFT) /* Debug Message C */ +#define STDFILTER_S0_SFID1_SHIFT (16) /* Bits 16-26: Standard Filter ID 2 */ +#define STDFILTER_S0_SFID1_MASK (0x7ff << STDFILTER_S0_SFID1_SHIFT) +# define STDFILTER_S0_SFID1(n) ((uint32_t)(n) << STDFILTER_S0_SFID1_SHIFT) +#define STDFILTER_S0_SFEC_SHIFT (27) /* Bits 27-29: Standard Filter Element Configuration */ +#define STDFILTER_S0_SFEC_MASK (7 << STDFILTER_S0_SFEC_SHIFT) +# define STDFILTER_S0_SFEC_DISABLE (0 << STDFILTER_S0_SFEC_SHIFT) /* Disable filter element */ +# define STDFILTER_S0_SFEC_FIFO0 (1 << STDFILTER_S0_SFEC_SHIFT) /* Store in Rx FIFO 0 on match */ +# define STDFILTER_S0_SFEC_FIFO1 (2 << STDFILTER_S0_SFEC_SHIFT) /* Store in Rx FIFO 1 on match */ +# define STDFILTER_S0_SFEC_REJECT (3 << STDFILTER_S0_SFEC_SHIFT) /* Reject ID on match */ +# define STDFILTER_S0_SFEC_PRIORITY (4 << STDFILTER_S0_SFEC_SHIFT) /* Set priority ion match */ +# define STDFILTER_S0_SFEC_PRIOFIFO0 (5 << STDFILTER_S0_SFEC_SHIFT) /* Set priority and store in FIFO 0 on match */ +# define STDFILTER_S0_SFEC_PRIOFIFO1 (6 << STDFILTER_S0_SFEC_SHIFT) /* Set priority and store in FIFO 1 on match */ +# define STDFILTER_S0_SFEC_BUFFER (7 << STDFILTER_S0_SFEC_SHIFT) /* Store into Rx Buffer or as debug message */ +#define STDFILTER_S0_SFT_SHIFT (30) /* Bits 30-31: Standard Filter Type */ +#define STDFILTER_S0_SFT_MASK (3 << STDFILTER_S0_SFT_SHIFT) +# define STDFILTER_S0_SFT_RANGE (0 << STDFILTER_S0_SFT_SHIFT) /* Range filter from SF1ID to SF2ID */ +# define STDFILTER_S0_SFT_DUAL (1 << STDFILTER_S0_SFT_SHIFT) /* Dual ID filter for SF1ID or SF2ID */ +# define STDFILTER_S0_SFT_CLASSIC (2 << STDFILTER_S0_SFT_SHIFT) /* Classic filter: SF1ID=filter SF2ID=mask */ + +/* Extended Message ID Filter Element */ + +#define EXTFILTER_F0_EFID1_SHIFT (0) /* Bits 0-28: Extended Filter ID 1 */ +#define EXTFILTER_F0_EFID1_MASK (0x1fffffff << EXTFILTER_F0_EFID1_SHIFT) +# define EXTFILTER_F0_EFID1(n) ((uint32_t)(n) << EXTFILTER_F0_EFID1_SHIFT) +#define EXTFILTER_F0_EFEC_SHIFT (29) /* Bits 29-31: Extended Filter Element Configuration */ +#define EXTFILTER_F0_EFEC_MASK (7 << EXTFILTER_F0_EFEC_SHIFT) +# define EXTFILTER_F0_EFEC_DISABLE (0 << EXTFILTER_F0_EFEC_SHIFT) /* Disable filter element */ +# define EXTFILTER_F0_EFEC_FIFO0 (1 << EXTFILTER_F0_EFEC_SHIFT) /* Store in Rx FIFO 0 on match */ +# define EXTFILTER_F0_EFEC_FIFO1 (2 << EXTFILTER_F0_EFEC_SHIFT) /* Store in Rx FIFO 1 on match */ +# define EXTFILTER_F0_EFEC_REJECT (3 << EXTFILTER_F0_EFEC_SHIFT) /* Reject ID on match */ +# define EXTFILTER_F0_EFEC_PRIORITY (4 << EXTFILTER_F0_EFEC_SHIFT) /* Set priority on match */ +# define EXTFILTER_F0_EFEC_PRIOFIFO0 (5 << EXTFILTER_F0_EFEC_SHIFT) /* Set priority and store in FIFO 0 on match */ +# define EXTFILTER_F0_EFEC_PRIOFIFO1 (6 << EXTFILTER_F0_EFEC_SHIFT) /* Set priority and store in FIFO 1 on match */ +# define EXTFILTER_F0_EFEC_BUFFER (7 << EXTFILTER_F0_EFEC_SHIFT) /* Store into Rx Buffer or as debug message */ + +#define EXTFILTER_F1_EFID2_SHIFT (0) /* Bits 0-28: Extended Filter ID 2 */ +#define EXTFILTER_F1_EFID2_MASK (0x1fffffff << EXTFILTER_F1_EFID2_SHIFT) +# define EXTFILTER_F1_EFID2(n) ((uint32_t)(n) << EXTFILTER_F1_EFID2_SHIFT) +#define EXTFILTER_F1_BUFFER_SHIFT (0) /* Bits 0-5: RX buffer start address */ +#define EXTFILTER_F1_BUFFER_MASK (63 << EXTFILTER_F1_BUFFER_SHIFT) +# define EXTFILTER_F1_BUFFER(n) ((uint32_t)(n) << EXTFILTER_F1_BUFFER_SHIFT) +#define EXTFILTER_F1_ACTION_SHIFT (9) /* Bits 9-10: Action taken */ +#define EXTFILTER_F1_ACTION_MASK (3 << EXTFILTER_F1_ACTION_SHIFT) +# define EXTFILTER_F1_RXBUFFER (0 << EXTFILTER_F1_ACTION_SHIFT) /* Store message in a Rx buffer */ +# define EXTFILTER_F1_DEBUGA (1 << EXTFILTER_F1_ACTION_SHIFT) /* Debug Message A */ +# define EXTFILTER_F1_DEBUGB (2 << EXTFILTER_F1_ACTION_SHIFT) /* Debug Message B */ +# define EXTFILTER_F1_DEBUGC (3 << EXTFILTER_F1_ACTION_SHIFT) /* Debug Message C */ +#define EXTFILTER_F1_EFT_SHIFT (30) /* Bits 30-31: Extended Filter Type */ +#define EXTFILTER_F1_EFT_MASK (3 << EXTFILTER_F1_EFT_SHIFT) +# define EXTFILTER_F1_EFT_RANGE (0 << EXTFILTER_F1_EFT_SHIFT) /* Range filter from SF1ID to SF2ID */ +# define EXTFILTER_F1_EFT_DUAL (1 << EXTFILTER_F1_EFT_SHIFT) /* Dual ID filter for SF1ID or SF2ID */ +# define EXTFILTER_F1_EFT_CLASSIC (2 << EXTFILTER_F1_EFT_SHIFT) /* Classic filter: SF1ID=filter SF2ID=mask */ +# define EXTFILTER_F1_EFT_NOXIDAM (3 << EXTFILTER_F1_EFT_SHIFT) /* Range filter from EF1ID to EF2ID, no XIDAM */ + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_FDCAN_MCAN_H */ diff --git a/arch/arm/src/common/stm32/hardware/stm32_fdcan_mcan_m0.h b/arch/arm/src/common/stm32/hardware/stm32_fdcan_mcan_m0.h new file mode 100644 index 0000000000000..c8a0eba38e3f5 --- /dev/null +++ b/arch/arm/src/common/stm32/hardware/stm32_fdcan_mcan_m0.h @@ -0,0 +1,582 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/hardware/stm32_fdcan_mcan_m0.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_FDCAN_MCAN_M0_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_FDCAN_MCAN_M0_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "chip.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Register Offsets *********************************************************/ + +#define STM32_FDCAN_CREL_OFFSET 0x0000 /* FDCAN core release register */ +#define STM32_FDCAN_ENDN_OFFSET 0x0004 /* FDCAN endian register */ + /* 0x0008 Reserved */ +#define STM32_FDCAN_DBTP_OFFSET 0x000c /* FDCAN data bit timing and prescaler register */ +#define STM32_FDCAN_TEST_OFFSET 0x0010 /* FDCAN test register */ +#define STM32_FDCAN_RWD_OFFSET 0x0014 /* FDCAN RAM watchdog register */ +#define STM32_FDCAN_CCCR_OFFSET 0x0018 /* FDCAN CC control register */ +#define STM32_FDCAN_NBTP_OFFSET 0x001c /* FDCAN nominal bit timing and prescaler register */ +#define STM32_FDCAN_TSCC_OFFSET 0x0020 /* FDCAN timestamp counter configuration register */ +#define STM32_FDCAN_TSCV_OFFSET 0x0024 /* FDCAN timestamp counter value register */ +#define STM32_FDCAN_TOCC_OFFSET 0x0028 /* FDCAN timeout counter configuration register */ +#define STM32_FDCAN_TOCV_OFFSET 0x002c /* FDCAN timeout counter value register */ + /* 0x0030 to 0x003c Reserved */ +#define STM32_FDCAN_ECR_OFFSET 0x0040 /* FDCAN error counter register */ +#define STM32_FDCAN_PSR_OFFSET 0x0044 /* FDCAN protocol status register */ +#define STM32_FDCAN_TDCR_OFFSET 0x0048 /* FDCAN transmitter delay compensation register */ + /* 0x004c Reserved */ +#define STM32_FDCAN_IR_OFFSET 0x0050 /* FDCAN interrupt register */ +#define STM32_FDCAN_IE_OFFSET 0x0054 /* FDCAN interrupt enable register */ +#define STM32_FDCAN_ILS_OFFSET 0x0058 /* FDCAN interrupt line select register */ +#define STM32_FDCAN_ILE_OFFSET 0x005c /* FDCAN interrupt line enable register */ + /* 0x0060 to 0x007c Reserved */ +#define STM32_FDCAN_RXGFC_OFFSET 0x0080 /* FDCAN global filter configuration register */ +#define STM32_FDCAN_XIDAM_OFFSET 0x0084 /* FDCAN extended ID and mask register */ +#define STM32_FDCAN_HPMS_OFFSET 0x0088 /* FDCAN high-priority message status register */ +#define STM32_FDCAN_RXFS_OFFSET(f) (0x0090 + ((f) << 3) +#define STM32_FDCAN_RXFA_OFFSET(f) (0x0094 + ((f) << 3) +#define STM32_FDCAN_RXF0S_OFFSET 0x0090 /* FDCAN Rx FIFO 0 status register */ +#define STM32_FDCAN_RXF0A_OFFSET 0x0094 /* CAN Rx FIFO 0 acknowledge register */ +#define STM32_FDCAN_RXF1S_OFFSET 0x0098 /* FDCAN Rx FIFO 1 status register */ +#define STM32_FDCAN_RXF1A_OFFSET 0x009c /* FDCAN Rx FIFO 1 acknowledge register */ + /* 0x00a0 to 0x00bc Reserved */ +#define STM32_FDCAN_TXBC_OFFSET 0x00c0 /* FDCAN Tx buffer configuration register */ +#define STM32_FDCAN_TXFQS_OFFSET 0x00c4 /* FDCAN Tx FIFO/queue status register */ +#define STM32_FDCAN_TXBRP_OFFSET 0x00c8 /* FDCAN Tx buffer request pending register */ +#define STM32_FDCAN_TXBAR_OFFSET 0x00cc /* FDCAN Tx buffer add request register */ +#define STM32_FDCAN_TXBCR_OFFSET 0x00d0 /* FDCAN Tx buffer cancellation request register */ +#define STM32_FDCAN_TXBTO_OFFSET 0x00d4 /* FDCAN Tx buffer transmission occurred register */ +#define STM32_FDCAN_TXBCNF_OFFSET 0x00d8 /* FDCAN Tx buffer cancellation finished register */ +#define STM32_FDCAN_TXBTIE_OFFSET 0x00dc /* FDCAN Tx buffer transmission interrupt enable register */ +#define STM32_FDCAN_TXBCIE_OFFSET 0x00e0 /* FDCAN Tx buffer cancellation finished interrupt enable register */ +#define STM32_FDCAN_TXEFS_OFFSET 0x00e4 /* FDCAN Tx event FIFO status register */ +#define STM32_FDCAN_TXEFA_OFFSET 0x00e8 /* FDCAN Tx event FIFO acknowledge register */ +#define STM32_FDCAN_CKDIV_OFFSET 0x0100 /* FDCAN CFG clock divider register */ + +/* Register Bitfield Definitions ********************************************/ + +/* FDCAN core release register */ + +#define FDCAN_CREL_DAY_SHIFT (0) /* Bits 0-7: DAY */ +#define FDCAN_CREL_DAY_MASK (0xff << FDCAN_CREL_DAY_SHIFT) +#define FDCAN_CREL_MON_SHIFT (8) /* Bits 8-15: MON */ +#define FDCAN_CREL_MON_MASK (0xff << FDCAN_CREL_MON_SHIFT) +#define FDCAN_CREL_YEAR_SHIFT (16) /* Bits 8-15: YEAR */ +#define FDCAN_CREL_YEAR_MASK (0x0f << FDCAN_CREL_YEAR_SHIFT) +#define FDCAN_CREL_SUBSTEP_SHIFT (20) /* Bits 20-23: SUBSTEP */ +#define FDCAN_CREL_SUBSTEP_MASK (0x0f << FDCAN_CREL_SUBSTEP_SHIFT) +#define FDCAN_CREL_STEP_SHIFT (24) /* Bits 24-27: STEP */ +#define FDCAN_CREL_STEP_MASK (0x0f << FDCAN_CREL_STEP_SHIFT) +#define FDCAN_CREL_REL_SHIFT (28) /* Bits 28-31: REL */ +#define FDCAN_CREL_REL_MASK (0x0f << FDCAN_CREL_REL_SHIFT) + +/* FDCAN data bit timing and prescaler register */ + +#define FDCAN_DBTP_DSJW_SHIFT (0) /* Bits 0-3: Synchronization jump width */ +#define FDCAN_DBTP_DSJW_MASK (0x0f << FDCAN_DBTP_DSJW_SHIFT) +# define FDCAN_DBTP_DSJW(value) ((value) << FDCAN_DBTP_DSJW_SHIFT) +# define FDCAN_DBTP_DSJW_MAX (15) +#define FDCAN_DBTP_DTSEG2_SHIFT (4) /* Bits 4-7: Data time segment after sample point*/ +#define FDCAN_DBTP_DTSEG2_MASK (0x0f << FDCAN_DBTP_DTSEG2_SHIFT) +# define FDCAN_DBTP_DTSEG2(value) ((value) << FDCAN_DBTP_DTSEG2_SHIFT) +# define FDCAN_DBTP_DTSEG2_MAX (15) +#define FDCAN_DBTP_DTSEG1_SHIFT (8) /* Bits 8-12: Data time segment before sample point*/ +#define FDCAN_DBTP_DTSEG1_MASK (0x1f << FDCAN_DBTP_DTSEG1_SHIFT) +# define FDCAN_DBTP_DTSEG1(value) ((value) << FDCAN_DBTP_DTSEG1_SHIFT) +# define FDCAN_DBTP_DTSEG1_MAX (31) +#define FDCAN_DBTP_DBRP_SHIFT (16) /* Bits 16-20: Data bitrate prescaler */ +#define FDCAN_DBTP_DBRP_MASK (0x1f << FDCAN_DBTP_DBRP_SHIFT) +# define FDCAN_DBTP_DBRP(value) ((value) << FDCAN_DBTP_DBRP_SHIFT) +# define FDCAN_DBTP_DBRP_MAX (31) +#define FDCAN_DBTP_TDC_EN (1 << 23) /* Bit 23: Transceiver delay compensation enable */ + +/* FDCAN test register */ + +#define FDCAN_TEST_LBCK (1 << 4) /* Bit 4: Loop back mode */ +#define FDCAN_TEST_TX_SHIFT (5) /* Bits 5-6: Control of transmit pin */ +#define FDCAN_TEST_TX_MASK (0x3 << FDCAN_TEST_TX_SHIFT) +# define FDCAN_TEST_TX_RESET (0 << FDCAN_TEST_TX_SHIFT) /* 00: TX is controlled by CAN core */ +# define FDCAN_TEST_TX_SP (1 << FDCAN_TEST_TX_SHIFT) /* 01: Sample point can be monitored at TX pin */ +# define FDCAN_TEST_TX_DLVL (2 << FDCAN_TEST_TX_SHIFT) /* 10: Dominant (0) level at TX pin */ +# define FDCAN_TEST_TX_RLVL (3 << FDCAN_TEST_TX_SHIFT) /* 11: Recesive (1) level at TX pin */ +#define FDCAN_TEST_RX (1 << 7) /* Bit 7: Receive pin */ + +/* FDCAN RAM watchdog register */ + +#define FDCAN_RWD_WDC_SHIFT (0) /* Bits 0-7: RAM watchdog counter start value */ +#define FDCAN_RWD_WDC_MASK (0xff << FDCAN_RWD_WDC_SHIFT) +# define FDCAN_RWD_WDC_DIS (0 << FDCAN_RWD_WDC_SHIFT) /* Counter disabled */ +# define FDCAN_RWD_WDC(value) ((value) << FDCAN_RWD_WDC_SHIFT) +#define FDCAN_RWD_WDV_SHIFT (8) /* Bits 8-15: RAM watchdog counter value */ +#define FDCAN_RWD_WDV_MASK (0xff << FDCAN_RWD_WDV_SHIFT) + +/* FDCAN CC control register */ + +#define FDCAN_CCCR_INIT (1 << 0) /* Bit 0: Initialization */ +#define FDCAN_CCCR_CCE (1 << 1) /* Bit 1: Configuration change enable */ +#define FDCAN_CCCR_ASM (1 << 2) /* Bit 2: ASM restricted operation mode */ +#define FDCAN_CCCR_CSA (1 << 3) /* Bit 3: Clock stop acknowledge */ +#define FDCAN_CCCR_CSR (1 << 4) /* Bit 4: Clock stop request */ +#define FDCAN_CCCR_MON (1 << 5) /* Bit 5: Bus monitoring mode */ +#define FDCAN_CCCR_DAR (1 << 6) /* Bit 6: Disable automatic retransmission */ +#define FDCAN_CCCR_TEST (1 << 7) /* Bit 7: Test mode enable */ +#define FDCAN_CCCR_FDOE (1 << 8) /* Bit 8: FD operation enable */ +#define FDCAN_CCCR_BRSE (1 << 9) /* Bit 9: FDCAN Bitrate switching */ + /* Bits 10-11: Reserved */ +#define FDCAN_CCCR_PXHD (1 << 12) /* Bit 12: Protocol exception handling disable */ +#define FDCAN_CCCR_EFBI (1 << 13) /* Bit 13: Edge filtering during bus integration */ +#define FDCAN_CCCR_TXP (1 << 14) /* Bit 14: Tx pause */ +#define FDCAN_CCCR_NISO (1 << 15) /* Bit 15: Non ISO operation */ + +/* FDCAN nominal bit timing and prescaler register */ + +#define FDCAN_NBTP_NTSEG2_SHIFT (0) /* Bits 0-6: Nominal time segment after sample point */ +#define FDCAN_NBTP_NTSEG2_MASK (0x7f << FDCAN_NBTP_NTSEG2_SHIFT) +# define FDCAN_NBTP_NTSEG2(value) ((value) << FDCAN_NBTP_NTSEG2_SHIFT) +# define FDCAN_NBTP_NTSEG2_MAX (127) +#define FDCAN_NBTP_NTSEG1_SHIFT (8) /* Bits 8-15: Nominal time segment before sample point */ +#define FDCAN_NBTP_NTSEG1_MASK (0xff << FDCAN_NBTP_NTSEG1_SHIFT) +# define FDCAN_NBTP_NTSEG1(value) ((value) << FDCAN_NBTP_NTSEG1_SHIFT) +# define FDCAN_NBTP_NTSEG1_MAX (255) +#define FDCAN_NBTP_NBRP_SHIFT (16) /* Bits 16-24: Bitrate prescaler */ +#define FDCAN_NBTP_NBRP_MASK (0x1ff << FDCAN_NBTP_NBRP_SHIFT) +# define FDCAN_NBTP_NBRP(value) ((value) << FDCAN_NBTP_NBRP_SHIFT) +# define FDCAN_NBTP_NBRP_MAX (511) +#define FDCAN_NBTP_NSJW_SHIFT (25) /* Bits 25-31: Nominal (re)synchronization jump width */ +#define FDCAN_NBTP_NSJW_MASK (0x7f << FDCAN_NBTP_NSJW_SHIFT) +# define FDCAN_NBTP_NSJW(value) ((value) << FDCAN_NBTP_NSJW_SHIFT) +# define FDCAN_NBTP_NSJW_MAX (127) + +/* FDCAN timestamp counter configuration register */ + +#define FDCAN_TSCC_TSS_SHIFT (0) /* Bits 0-1: Timestamp counter select */ +#define FDCAN_TSCC_TSS_MASK (0x3 << FDCAN_TSCC_TSS_SHIFT) +# define FDCAN_TSCC_TSS_ZERO (0 << FDCAN_TSCC_TSS_SHIFT) /* 00: Always 0 */ +# define FDCAN_TSCC_TSS_TCP (1 << FDCAN_TSCC_TSS_SHIFT) /* 01: Incremented based on TCP */ +# define FDCAN_TSCC_TSS_TIM3 (2 << FDCAN_TSCC_TSS_SHIFT) /* 10: Value from TIM3 used */ +#define FDCAN_TSCC_TCP_SHIFT (16) /* Bits 16-19: Timestamp counter prescaler */ +#define FDCAN_TSCC_TCP_MASK (0x0f << FDCAN_TSCC_TCP_SHIFT) +# define FDCAN_TSCC_TCP(value) ((value) << FDCAN_TSCC_TCP_SHIFT) + +/* FDCAN timestamp counter value register */ + +#define FDCAN_TSCV_TSC_SHIFT (0) /* Bits 0-15: Timestamp counter */ +#define FDCAN_TSCV_TSC_MASK (0xffff << FDCAN_TSCV_TSC_SHIFT) + +/* FDCAN timeout counter configuration register */ + +#define FDCAN_TOCC_ETOC (1 << 0) /* Bit 0: Enable timeout counter */ +#define FDCAN_TOCC_TOS_SHIFT (1) /* Bits 1-2: Timeout select */ +#define FDCAN_TOCC_TOS_MASK (0x03 << FDCAN_TOCC_TOS_SHIFT) +# define FDCAN_TOCC_TOS_CONT (0 << FDCAN_TOCC_TOS_SHIFT) /* 00: Continuous operation */ +# define FDCAN_TOCC_TOS_TXFIFO (1 << FDCAN_TOCC_TOS_SHIFT) /* 01: Tx event FIFO */ +# define FDCAN_TOCC_TOS_RX_FIFO0 (2 << FDCAN_TOCC_TOS_SHIFT) /* 10: Rx FIFO 0 */ +# define FDCAN_TOCC_TOS_RX_FIFO1 (3 << FDCAN_TOCC_TOS_SHIFT) /* 11: Rx FIFO 1 */ +#define FDCAN_TOCC_TOP_SHIFT (16) /* Bits 16-31: Timeout period counter start value */ +#define FDCAN_TOCC_TOP_MASK (0xffff << FDCAN_TOCC_TOP_SHIFT) +# define FDCAN_TOCC_TOP(value) ((value) << FDCAN_TOCC_TOP_SHIFT) + +/* FDCAN timeout counter value register */ + +#define FDCAN_TOCV_TOC_SHIFT (0) /* Bits 0-15: Timestamp counter */ +#define FDCAN_TOCV_TOC_MASK (0xffff << FDCAN_TOCV_TOC_SHIFT) + +/* FDCAN error counter register */ + +#define FDCAN_ECR_TEC_SHIFT (0) /* Bits 0-7: Transmit error counter */ +#define FDCAN_CR_TEC_MASK (0xff << FDCAN_ECR_TEC_SHIFT) +#define FDCAN_ECR_REC_SHIFT (8) /* Bits 8-14: Receive error counter */ +#define FDCAN_ECR_REC_MASK (0x7f << FDCAN_ECR_REC_SHIFT) +#define FDCAN_ECR_RP (1 << 15) /* Bit 15: Receive error passive */ +#define FDCAN_ECR_CEL_SHIFT (16) /* Bits 16-23: CAN error logging */ +#define FDCAN_ECR_CEL_MASK (0xff << FDCAN_ECR_CEL_SHIFT) + +/* FDCAN protocol status register */ + +/* Error codes */ + +#define FDCAN_PSR_EC_NO_ERROR (0) /* No error occurred since LEC has been reset */ +#define FDCAN_PSR_EC_STUFF_ERROR (1) /* More than 5 equal bits in a sequence */ +#define FDCAN_PSR_EC_FORM_ERROR (2) /* Part of a received frame has wrong format */ +#define FDCAN_PSR_EC_ACK_ERROR (3) /* Message not acknowledged by another node */ +#define FDCAN_PSR_EC_BIT1_ERROR (4) /* Send with recessive level, but bus value was dominant */ +#define FDCAN_PSR_EC_BIT0_ERROR (5) /* Send with dominant level, but bus value was recessive */ +#define FDCAN_PSR_EC_CRC_ERROR (6) /* CRC received message incorrect */ +#define FDCAN_PSR_EC_NO_CHANGE (7) /* No CAN bus event was detected since last read */ + +#define FDCAN_PSR_LEC_SHIFT (0) /* Bits 0-2: Last error code */ +#define FDCAN_PSR_LEC_MASK (0x7 << FDCAN_PSR_LEC_SHIFT) +# define FDCAN_PSR_LEC(n) ((uint32_t)(n) << FDCAN_PSR_LEC_SHIFT) /* See error codes above */ +#define FDCAN_PSR_ACT_SHIFT (3) /* Bits 3-4: Activity */ +#define FDCAN_PSR_ACT_MASK (3 << FDCAN_PSR_ACT_SHIFT) +# define FDCAN_PSR_ACT_SYNC (0 << FDCAN_PSR_ACT_SHIFT) /* 00: Synchronizing */ +# define FDCAN_PSR_ACT_IDLE (1 << FDCAN_PSR_ACT_SHIFT) /* 01: Idle */ +# define FDCAN_PSR_ACT_RECV (2 << FDCAN_PSR_ACT_SHIFT) /* 10: Receiver */ +# define FDCAN_PSR_ACT_TRANS (3 << FDCAN_PSR_ACT_SHIFT) /* 11: Transmitter */ +#define FDCAN_PSR_EP (1 << 5) /* Bit 5: Error passive */ +#define FDCAN_PSR_EW (1 << 6) /* Bit 6: Warning status */ +#define FDCAN_PSR_BO (1 << 7) /* Bit 7: Bus_off status */ +#define FDCAN_PSR_DLEC_SHIFT (8) /* Bits 8-10: Data last error code */ +#define FDCAN_PSR_DLEC_MASK (0x7 << FDCAN_PSR_DLEC_SHIFT) +# define FDCAN_PSR_DLEC(n) ((uint32_t)(n) << FDCAN_PSR_DLEC_SHIFT) /* See error codes above */ +#define FDCAN_PSR_RESI (1 << 11) /* Bit 11: ESI flag of last message */ +#define FDCAN_PSR_RBRS (1 << 12) /* Bit 12: BRS flag of last message */ +#define FDCAN_PSR_REDL (1 << 13) /* Bit 13: Received message */ +#define FDCAN_PSR_PXE (1 << 14) /* Bit 14: Protocol exception event */ +#define FDCAN_PSR_TDCV_SHIFT (16) /* Bits 16-22: Transmitter delay compensation */ +#define FDCAN_PSR_TDCV_MASK (0x7f << FDCAN_PSR_TDCV_SHIFT) + +/* FDCAN transmitter delay compensation register */ + +#define FDCAN_TDCR_TDCF_SHIFT (0) /* Bits 0-6: Transmitter delay compensation filter window length */ +#define FDCAN_TDCR_TDCF_MASK (0x7f << FDCAN_TDCR_TDCF_SHIFT) +# define FDCAN_TDCR_TDCF(value) ((value) << FDCAN_TDCR_TDCF_SHIFT) +#define FDCAN_TDCR_TDCO_SHIFT (8) /* Bits 8-14: Transmiiter delay compensation offset */ +#define FDCAN_TDCR_TDCO_MASK (0x7f << FDCAN_TDCR_TDCO_SHIFT) +# define FDCAN_TDCR_TDCO(value) ((value) << FDCAN_TDCR_TDCO_SHIFT) + +/* FDCAN interrupt register and interrupt enable register */ + +#define FDCAN_INT_RF0N (1 << 0) /* Bit 0: Rx FIFO 0 new message */ +#define FDCAN_INT_RF0F (1 << 1) /* Bit 1: Rx FIFO 0 full */ +#define FDCAN_INT_RF0L (1 << 2) /* Bit 2: Rx FIFO 0 message lost */ +#define FDCAN_INT_RF1N (1 << 3) /* Bit 3: Rx FIFO 1 new message */ +#define FDCAN_INT_RF1F (1 << 4) /* Bit 4: Rx FIFO 1 full */ +#define FDCAN_INT_RF1L (1 << 5) /* Bit 5: Rx FIFO 1 message lost */ +#define FDCAN_INT_HPM (1 << 6) /* Bit 6: High priority message */ +#define FDCAN_INT_TC (1 << 7) /* Bit 7: Transmission completed */ +#define FDCAN_INT_TCF (1 << 8) /* Bit 8: Transmission cancellation finished */ +#define FDCAN_INT_TFE (1 << 9) /* Bit 9: Tx FIFO empty */ +#define FDCAN_INT_TEFN (1 << 10) /* Bit 10: Tx event FIFO new entry */ +#define FDCAN_INT_TEFF (1 << 11) /* Bit 11: Tx event FIFO full */ +#define FDCAN_INT_TEFL (1 << 12) /* Bit 12: Tx event FIFO element lost */ +#define FDCAN_INT_TSW (1 << 13) /* Bit 13: Timestamp wraparound */ +#define FDCAN_INT_MRAF (1 << 14) /* Bit 14: Message RAM access failure */ +#define FDCAN_INT_TOO (1 << 15) /* Bit 15: Timeout occurred */ +#define FDCAN_INT_ELO (1 << 16) /* Bit 16: Error logging overflow */ +#define FDCAN_INT_EP (1 << 17) /* Bit 17: Error_passive status */ +#define FDCAN_INT_EW (1 << 18) /* Bit 18: Error_warning status */ +#define FDCAN_INT_BO (1 << 19) /* Bit 19: Buss_off status */ +#define FDCAN_INT_WDI (1 << 20) /* Bit 20: Watchdog interrupt */ +#define FDCAN_INT_PEA (1 << 21) /* Bit 21: Protocol error arbitration phase */ +#define FDCAN_INT_PED (1 << 22) /* Bit 22: Protocol error data phase */ +#define FDCAN_INT_ARA (1 << 23) /* Bit 23: Access to reserved address */ + +/* FDCAN interrupt line select register */ + +#define FDCAN_ILS_RXFIFO0 (1 << 0) /* Bit 0: RXFIFO 0 */ +#define FDCAN_ILS_RXFIFO1 (1 << 1) /* Bit 1: RXFIFO 1 */ +#define FDCAN_ILS_SMG (1 << 2) /* Bit 2: SMSG */ +#define FDCAN_ILS_TFERR (1 << 3) /* Bit 3: TFERR */ +#define FDCAN_ILS_MISC (1 << 4) /* Bit 4: MISC */ +#define FDCAN_ILS_BERR (1 << 5) /* Bit 5: BERR */ +#define FDCAN_ILS_PERR (1 << 6) /* Bit 6: PERR */ + +/* FDCAN interrupt line enable register */ + +#define FDCAN_ILE_EINT0 (1 << 0) /* Bit 0: Enable interrupt line 0 */ +#define FDCAN_ILE_EINT1 (1 << 1) /* Bit 1: Enable interrupt line 1 */ + +/* FDCAN global filter configuration register */ + +#define FDCAN_RXGFC_RRFE (1 << 0) /* Bit 0: Reject remote frames ext */ +#define FDCAN_RXGFC_RRFS (1 << 1) /* Bit 1: Reject remote frames std */ +#define FDCAN_RXGFC_ANFE_SHIFT (2) /* Bits 2-3: Accept non-matching frames ext */ +#define FDCAN_RXGFC_ANFE_MASK (0x3 << FDCAN_RXGFC_ANFE_SHIFT) +# define FDCAN_RXGFC_ANFE_RX_FIFO0 (0 << FDCAN_RXGFC_ANFE_SHIFT) /* 00: Accept in Rx FIFO 0 */ +# define FDCAN_RXGFC_ANFE_RX_FIFO1 (1 << FDCAN_RXGFC_ANFE_SHIFT) /* 01: Accept in Rx FIFO 1 */ +# define FDCAN_RXGFC_ANFE_REJECTED (2 << FDCAN_RXGFC_ANFE_SHIFT) /* 10: Reject */ +#define FDCAN_RXGFC_ANFS_SHIFT (4) /* Bits 5-4: Accept non-matching frames std */ +#define FDCAN_RXGFC_ANFS_MASK (0x3 << FDCAN_RXGFC_ANFS_SHIFT) +# define FDCAN_RXGFC_ANFS_RX_FIFO0 (0 << FDCAN_RXGFC_ANFS_SHIFT) /* 00: Accept in Rx FIFO 0 */ +# define FDCAN_RXGFC_ANFS_RX_FIFO1 (1 << FDCAN_RXGFC_ANFS_SHIFT) /* 01: Accept in Rx FIFO 1 */ +# define FDCAN_RXGFC_ANFS_REJECTED (2 << FDCAN_RXGFC_ANFS_SHIFT) /* 10: Reject */ +#define FDCAN_RXGFC_F1OM (1 << 8) /* Bit 8: FIFO 1 operation mode */ +#define FDCAN_RXGFC_F0OM (1 << 9) /* Bit 9: FIFO 0 operation mode */ +#define FDCAN_RXGFC_LSS_SHIFT (16) /* Bits 16-20: List size std */ +#define FDCAN_RXGFC_LSS_MASK (0x1f << FDCAN_RXGFC_LSS_SHIFT) +# define FDCAN_RXGFC_LSS(value) ((value) << FDCAN_RXGFC_LSS_SHIFT) +# define FDCAN_RXGFC_LSS_MAX (28) +#define FDCAN_RXGFC_LSE_SHIFT (24) /* Bits 24-27: List size ext */ +#define FDCAN_RXGFC_LSE_MASK (0x1f << FDCAN_RXGFC_LSE_SHIFT) +# define FDCAN_RXGFC_LSE(value) ((value) << FDCAN_RXGFC_LSE_SHIFT) +# define FDCAN_RXGFC_LSE_MAX (8) + +/* FDCAN extended ID and mask register */ + +#define FDCAN_XIDAM_EIDM_SHIFT (0) /* Bits 0-28: Extended ID mask */ +#define FDCAN_XIDAM_EIDM_MASK (0x1fffffff << FDCAN_XIDAM_EIDM_SHIFT) + +/* FDCAN high-priority message status register */ + +#define FDCAN_HPMS_BIDX_SHIFT (0) /* Bits 0-2: Buffer index */ +#define FDCAN_HPMS_BIDX_MASK (0x7 << FDCAN_HPMS_BIDX_SHIFT) +# define FDCAN_HPMS_BIDX(value) ((value) << FDCAN_HPMS_BIDX_SHIFT) +#define FDCAN_HPMS_MSI_SHIFT (6) /* Bits 6-7: Message storage indicator */ +#define FDCAN_HPMS_MSI_MASK (0x3 << FDCAN_HPMS_MSI_SHIFT) +# define FDCAN_HPMS_MSI(value) ((value) << FDCAN_HPMS_MSI_SHIFT) +#define FDCAN_HPMS_FIDX_SHIFT (8) /* Bits 8-12: Filter index */ +#define FDCAN_HPMS_FIDX_MASK (0x1f << FDCAN_HPMS_FIDX_SHIFT) +# define FDCAN_HPMS_FIDX(value) ((value) << FDCAN_HPMS_FIDX_SHIFT) +#define FDCAN_HPMS_FLST (1 << 15) /* Bit 15: Filter list */ + +/* FDCAN Rx FIFO x status register */ + +#define FDCAN_RXFS_FFL_SHIFT (0) /* Bits 0-3: FIFO fill level */ +#define FDCAN_RXFS_FFL_MASK (0xf << FDCAN_RXFS_FFL_SHIFT) +# define FDCAN_RXFS_FFL(value) ((value) << FDCAN_RXFS_FFL_SHIFT) +#define FDCAN_RXFS_FGI_SHIFT (8) /* Bits 8-9: FIFO get index */ +#define FDCAN_RXFS_FGI_MASK (0x3 << FDCAN_RXFS_FGI_SHIFT) +# define FDCAN_RXFS_FGI(value) ((value) << FDCAN_RXFS_FGI_SHIFT) +#define FDCAN_RXFS_FPI_SHIFT (16) /* Bits 16-17: FIFO put index */ +#define FDCAN_RXFS_FPI_MASK (0x3 << FDCAN_RXFS_FPI_SHIFT) +# define FDCAN_RXFS_FPI(value) ((value) << FDCAN_RXFS_FPI_SHIFT) +#define FDCAN_RXFS_FF (1 << 24) /* Bit 24: FIFO full */ +#define FDCAN_RXFS_RFL (1 << 25) /* Bit 25: FIFO message lost */ + +/* FDCAN Rx FIFO x acknowledge register */ + +#define FDCAN_RXFA_FAI_SHIFT (0) /* Bits 0-2: FIFO 0 acknowledge index */ +#define FDCAN_RXFA_FAI_MASK (0x7 << FDCAN_RXFA_FAI_SHIFT) + +/* FDCAN Tx buffer configuration register */ + +#define FDCAN_TXBC_TFQM (1 << 24) /* Bit 24: FIFO/queue mode */ + +/* FDCAN Tx FIFO/queue status register */ + +#define FDCAN_TXFQS_TFFL_SHIFT (0) /* Bits 0-2: FIFO free level */ +#define FDCAN_TXFQS_TFFL_MASK (0x7 << FDCAN_TXFQS_TFFL_SHIFT) +#define FDCAN_TXFQS_TFGI_SHIFT (8) /* Bits 8-9: FIFO get index */ +#define FDCAN_TXFQS_TFGI_MASK (0x3 << FDCAN_TXFQS_TFGI_SHIFT) +#define FDCAN_TXFQS_TFQPI_SHIFT (16) /* Bits 20-16: FIFO/queue put index */ +#define FDCAN_TXFQS_TFQPI_MASK (0x3 << FDCAN_TXFQS_TFQPI_SHIFT) +#define FDCAN_TXFQS_TFQF (1 << 21) /* Bit 21: FIFO/queue full */ + +/* FDCAN Tx buffer request pending register */ + +#define FDCAN_TXBRP_TRP_SHIFT (0) /* Bits 0-2: Transmission request pending */ +#define FDCAN_TXBRP_TRP_MASK (0x7 << FDCAN_TXBRP_TRP_SHIFT) +# define FDCAN_TXBRP_TRP(value) ((value) << FDCAN_TXBRP_TRP_SHIFT) + +/* FDCAN Tx buffer add request register */ + +#define FDCAN_TXBAR_AR_SHIFT (0) /* Bits 0-2: Add request */ +#define FDCAN_TXBAR_AR_MASK (0x7 << FDCAN_TXBAR_AR_SHIFT) +# define FDCAN_TXBAR_AR(value) ((value) << FDCAN_TXBAR_AR_SHIFT) + +/* FDCAN Tx buffer cancellation request register */ + +#define FDCAN_TXBCR_CR_SHIFT (0) /* Bits 0-2: Cancellation request */ +#define FDCAN_TXBCR_CR_MASK (0x7 << FDCAN_TXBCR_CR_SHIFT) +# define FDCAN_TXBCR_CR(value) ((value) << FDCAN_TXBCR_CR_SHIFT) + +/* FDCAN Tx buffer transmission occurred register */ + +#define FDCAN_TXBTO_TO_SHIFT (0) /* Bits 0-2: Transmission occurred */ +#define FDCAN_TXBTO_TO_MASK (0x7 << FDCAN_TXBTO_TO_SHIFT) + +/* FDCAN Tx buffer cancellation finished register */ + +#define FDCAN_TXBCF_CF_SHIFT (0) /* Bits 0-2: Cancellation finished */ +#define FDCAN_TXBCF_CF_MASK (0x7 << FDCAN_TXBCF_CF_SHIFT) + +/* FDCAN Tx buffer transmission interrupt enable register */ + +#define FDCAN_TXBTIE_TIE_SHIFT (0) /* Bits 0-2: Transmission interrupt enable */ +#define FDCAN_TXBTIE_TIE_MASK (0x7 << FDCAN_TXBTIE_TIE_SHIFT) +# define FDCAN_TXBTIE_TIE(value) ((value) << FDCAN_TXBTIE_TIE_SHIFT) + +/* FDCAN Tx buffer cancellation finished interrupt enable register */ + +#define FDCAN_TXBCIE_CFIE_SHIFT (0) /* Bits 0-2: Cancellation finished interrupt enable */ +#define FDCAN_TXBCIE_CFIE_MASK (0x7 << FDCAN_TXBCIE_CFIE_SHIFT) +# define FDCAN_TXBCIE_CFIE(value) ((value) << FDCAN_TXBCIE_CFIE_SHIFT) + +/* FDCAN Tx event FIFO status register */ + +#define FDCAN_TXEFS_EFFL_SHIFT (2) /* Bits 0-2: Event FIFO fill level */ +#define FDCAN_TXEFS_EFFL_MASK (0x7 << FDCAN_TXEFC_EFFL_SHIFT) +# define FDCAN_TXEFC_EFFL(value) ((value) << FDCAN_TXEFC_EFFL_SHIFT) +#define FDCAN_TXEFS_EFGI_SHIFT (8) /* Bits 8-9: Event FIFO get index */ +#define FDCAN_TXEFS_EFGI_MASK (0x3 << FDCAN_TXEFS_EFGI_SHIFT) +# define FDCAN_TXEFS_EFGI(value) ((value) << FDCAN_TXEFS_EFGI_SHIFT) +#define FDCAN_TXEFS_EFPI_SHIFT (16) /* Bits 16-17: Event FIFO put index */ +#define FDCAN_TXEFS_EFPI_MASK (0x3 << FDCAN_TXEFS_EFPI_SHIFT) +# define FDCAN_TXEFS_EFPI(value) ((value) << FDCAN_TXEFS_EFPI_SHIFT) +#define FDCAN_TXEFS_EFF (1 << 24) /* Bit 24: Event FIFO full */ +#define FDCAN_TXEFS_TEFL (1 << 25) /* Bit 25: Tx Event FIFO element lost */ + /* Bits 26-31: Reserved */ + +/* FDCAN Tx event FIFO acknowledge register */ + +#define FDCAN_TXEFA_EFAI_SHIFT (0) /* Bits 0-3: Event FIFO acknowledge index */ +#define FDCAN_TXEFA_EFAI_MASK (0x3 << FDCAN_TXEFA_EFAI_SHIFT) + +/* FDCAN CFG clock divider register */ + +#define FDCAN_CKDIV_PDIV_SHIFT (0) /* Bits 0-3: Input clock divider */ +#define FDCAN_CKDIV_PDIV_MASK (0xf << FDCAN_CKDIV_PDIV_SHIFT) + +/* Message RAM Definitions **************************************************/ + +/* Common Buffer and FIFO element bit definitions: + * + * --------------- ------------------- -------------------------------- + * RESOURCE R0 R1 + * --------------- ------------------- -------------------------------- + * RX FIFO: ESI, XTD, RTR, ID, ANMF, FIDX, EDL, BRS, DLC, RXTS + * TX buffer: XTD, RTR, ID, MM, EFC, DLC + * TX Event FIFO: ESI, XTD, RTR, ID, MM, ET, EDL, BRS, DLC, TXTS + * --------------- ------------------- -------------------------------- + */ + +/* Common */ + +#define BUFFER_R0_EXTID_SHIFT (0) /* Bits 0-28: Extended identifier */ +#define BUFFER_R0_EXTID_MASK (0x1fffffff << BUFFER_R0_EXTID_SHIFT) +# define BUFFER_R0_EXTID(n) ((uint32_t)(n) << BUFFER_R0_EXTID_SHIFT) +#define BUFFER_R0_STDID_SHIFT (18) /* Bits 18-28: Standard identifier */ +#define BUFFER_R0_STDID_MASK (0x7ff << BUFFER_R0_STDID_SHIFT) +# define BUFFER_R0_STDID(n) ((uint32_t)(n) << BUFFER_R0_STDID_SHIFT) +#define BUFFER_R0_RTR (1 << 29) /* Bit 29: Remote Transmission Request */ +#define BUFFER_R0_XTD (1 << 30) /* Bit 30: Extended Identifier */ +#define BUFFER_R0_ESI (1 << 31) /* Bit 31: Error State Indicator */ + +/* Common */ + +#define BUFFER_R1_DLC_SHIFT (16) /* Bits 16-19: Date length code */ +#define BUFFER_R1_DLC_MASK (15 << BUFFER_R1_DLC_SHIFT) +# define BUFFER_R1_DLC(n) ((uint32_t)(n) << BUFFER_R1_DLC_SHIFT) +#define BUFFER_R1_BRS (1 << 20) /* Bit 20: Bit Rate Switch */ +#define BUFFER_R1_FDF (1 << 21) /* Bit 21: FD Format */ + +/* RX buffer/RX FIFOs */ + +#define BUFFER_R1_RXTS_SHIFT (0) /* Bits 0-15: RX Timestamp */ +#define BUFFER_R1_RXTS_MASK (0xffff << BUFFER_R1_RXTS_SHIFT) +# define BUFFER_R1_RXTS(n) ((uint32_t)(n) << BUFFER_R1_RXTS_SHIFT) +#define BUFFER_R1_FIDX_SHIFT (24) /* Bits 24-30: Filter index */ +#define BUFFER_R1_FIDX_MASK (0x7f << BUFFER_R1_FIDX_SHIFT) +# define BUFFER_R1_FIDX(n) ((uint32_t)(n) << BUFFER_R1_FIDX_SHIFT) +#define BUFFER_R1_ANMF (1 << 31) /* Bit 31: Accepted Non-matching Frame */ + +/* TX buffer/TX Event FIFO */ + +#define BUFFER_R1_MM_SHIFT (24) /* Bits 24-31: Message Marker */ +#define BUFFER_R1_MM_MASK (0xff << BUFFER_R1_MM_SHIFT) +# define BUFFER_R1_MM(n) ((uint32_t)(n) << BUFFER_R1_MM_SHIFT) + +/* TX buffer */ + +#define BUFFER_R1_EFC (1 << 23) /* Bit 23: Event FIFO Control */ + +/* TX Event FIFO */ + +#define BUFFER_R1_TXTS_SHIFT (0) /* Bits 0-15: TX Timestamp */ +#define BUFFER_R1_TXTS_MASK (0xffff << BUFFER_R1_TXTS_SHIFT) +# define BUFFER_R1_TXTS(n) ((uint32_t)(n) << BUFFER_R1_TXTS_SHIFT) +#define BUFFER_R1_EDL (1 << 21) /* Bit 21: Extended Data Length */ +#define BUFFER_R1_ET_SHIFT (22) /* Bits 22-23: Event Type */ +#define BUFFER_R1_ET_MASK (3 << BUFFER_R1_ET_SHIFT) +# define BUFFER_R1_ET_TXEVENT (1 << BUFFER_R1_ET_SHIFT) /* Tx event */ +# define BUFFER_R1_ET_TXCANCEL (2 << BUFFER_R1_ET_SHIFT) /* Transmission despite cancellation */ + +/* Standard Message ID Filter Element */ + +#define STDFILTER_S0_SFID2_SHIFT (0) /* Bits 0-10: Standard Filter ID 2 */ +#define STDFILTER_S0_SFID2_MASK (0x7ff << STDFILTER_S0_SFID2_SHIFT) +# define STDFILTER_S0_SFID2(n ) ((uint32_t)(n) << STDFILTER_S0_SFID2_SHIFT) +#define STDFILTER_S0_BUFFER_SHIFT (0) /* Bits 0-5: RX buffer start address */ +#define STDFILTER_S0_BUFFER_MASK (63 << STDFILTER_S0_BUFFER_SHIFT) +# define STDFILTER_S0_BUFFER(n) ((uint32_t)(n) << STDFILTER_S0_BUFFER_SHIFT) +#define STDFILTER_S0_ACTION_SHIFT (9) /* Bits 9-10: Action taken */ +#define STDFILTER_S0_ACTION_MASK (3 << STDFILTER_S0_ACTION_SHIFT) +# define STDFILTER_S0_RXBUFFER (0 << STDFILTER_S0_ACTION_SHIFT) /* Store message in a Rx buffer */ +# define STDFILTER_S0_DEBUGA (1 << STDFILTER_S0_ACTION_SHIFT) /* Debug Message A */ +# define STDFILTER_S0_DEBUGB (2 << STDFILTER_S0_ACTION_SHIFT) /* Debug Message B */ +# define STDFILTER_S0_DEBUGC (3 << STDFILTER_S0_ACTION_SHIFT) /* Debug Message C */ +#define STDFILTER_S0_SFID1_SHIFT (16) /* Bits 16-26: Standard Filter ID 2 */ +#define STDFILTER_S0_SFID1_MASK (0x7ff << STDFILTER_S0_SFID1_SHIFT) +# define STDFILTER_S0_SFID1(n) ((uint32_t)(n) << STDFILTER_S0_SFID1_SHIFT) +#define STDFILTER_S0_SFEC_SHIFT (27) /* Bits 27-29: Standard Filter Element Configuration */ +#define STDFILTER_S0_SFEC_MASK (7 << STDFILTER_S0_SFEC_SHIFT) +# define STDFILTER_S0_SFEC_DISABLE (0 << STDFILTER_S0_SFEC_SHIFT) /* Disable filter element */ +# define STDFILTER_S0_SFEC_FIFO0 (1 << STDFILTER_S0_SFEC_SHIFT) /* Store in Rx FIFO 0 on match */ +# define STDFILTER_S0_SFEC_FIFO1 (2 << STDFILTER_S0_SFEC_SHIFT) /* Store in Rx FIFO 1 on match */ +# define STDFILTER_S0_SFEC_REJECT (3 << STDFILTER_S0_SFEC_SHIFT) /* Reject ID on match */ +# define STDFILTER_S0_SFEC_PRIORITY (4 << STDFILTER_S0_SFEC_SHIFT) /* Set priority ion match */ +# define STDFILTER_S0_SFEC_PRIOFIFO0 (5 << STDFILTER_S0_SFEC_SHIFT) /* Set priority and store in FIFO 0 on match */ +# define STDFILTER_S0_SFEC_PRIOFIFO1 (6 << STDFILTER_S0_SFEC_SHIFT) /* Set priority and store in FIFO 1 on match */ +# define STDFILTER_S0_SFEC_BUFFER (7 << STDFILTER_S0_SFEC_SHIFT) /* Store into Rx Buffer or as debug message */ +#define STDFILTER_S0_SFT_SHIFT (30) /* Bits 30-31: Standard Filter Type */ +#define STDFILTER_S0_SFT_MASK (3 << STDFILTER_S0_SFT_SHIFT) +# define STDFILTER_S0_SFT_RANGE (0 << STDFILTER_S0_SFT_SHIFT) /* Range filter from SF1ID to SF2ID */ +# define STDFILTER_S0_SFT_DUAL (1 << STDFILTER_S0_SFT_SHIFT) /* Dual ID filter for SF1ID or SF2ID */ +# define STDFILTER_S0_SFT_CLASSIC (2 << STDFILTER_S0_SFT_SHIFT) /* Classic filter: SF1ID=filter SF2ID=mask */ + +/* Extended Message ID Filter Element */ + +#define EXTFILTER_F0_EFID1_SHIFT (0) /* Bits 0-28: Extended Filter ID 1 */ +#define EXTFILTER_F0_EFID1_MASK (0x1fffffff << EXTFILTER_F0_EFID1_SHIFT) +# define EXTFILTER_F0_EFID1(n) ((uint32_t)(n) << EXTFILTER_F0_EFID1_SHIFT) +#define EXTFILTER_F0_EFEC_SHIFT (29) /* Bits 29-31: Extended Filter Element Configuration */ +#define EXTFILTER_F0_EFEC_MASK (7 << EXTFILTER_F0_EFEC_SHIFT) +# define EXTFILTER_F0_EFEC_DISABLE (0 << EXTFILTER_F0_EFEC_SHIFT) /* Disable filter element */ +# define EXTFILTER_F0_EFEC_FIFO0 (1 << EXTFILTER_F0_EFEC_SHIFT) /* Store in Rx FIFO 0 on match */ +# define EXTFILTER_F0_EFEC_FIFO1 (2 << EXTFILTER_F0_EFEC_SHIFT) /* Store in Rx FIFO 1 on match */ +# define EXTFILTER_F0_EFEC_REJECT (3 << EXTFILTER_F0_EFEC_SHIFT) /* Reject ID on match */ +# define EXTFILTER_F0_EFEC_PRIORITY (4 << EXTFILTER_F0_EFEC_SHIFT) /* Set priority on match */ +# define EXTFILTER_F0_EFEC_PRIOFIFO0 (5 << EXTFILTER_F0_EFEC_SHIFT) /* Set priority and store in FIFO 0 on match */ +# define EXTFILTER_F0_EFEC_PRIOFIFO1 (6 << EXTFILTER_F0_EFEC_SHIFT) /* Set priority and store in FIFO 1 on match */ +# define EXTFILTER_F0_EFEC_BUFFER (7 << EXTFILTER_F0_EFEC_SHIFT) /* Store into Rx Buffer or as debug message */ + +#define EXTFILTER_F1_EFID2_SHIFT (0) /* Bits 0-28: Extended Filter ID 2 */ +#define EXTFILTER_F1_EFID2_MASK (0x1fffffff << EXTFILTER_F1_EFID2_SHIFT) +# define EXTFILTER_F1_EFID2(n) ((uint32_t)(n) << EXTFILTER_F1_EFID2_SHIFT) +#define EXTFILTER_F1_BUFFER_SHIFT (0) /* Bits 0-5: RX buffer start address */ +#define EXTFILTER_F1_BUFFER_MASK (63 << EXTFILTER_F1_BUFFER_SHIFT) +# define EXTFILTER_F1_BUFFER(n) ((uint32_t)(n) << EXTFILTER_F1_BUFFER_SHIFT) +#define EXTFILTER_F1_ACTION_SHIFT (9) /* Bits 9-10: Action taken */ +#define EXTFILTER_F1_ACTION_MASK (3 << EXTFILTER_F1_ACTION_SHIFT) +# define EXTFILTER_F1_RXBUFFER (0 << EXTFILTER_F1_ACTION_SHIFT) /* Store message in a Rx buffer */ +# define EXTFILTER_F1_DEBUGA (1 << EXTFILTER_F1_ACTION_SHIFT) /* Debug Message A */ +# define EXTFILTER_F1_DEBUGB (2 << EXTFILTER_F1_ACTION_SHIFT) /* Debug Message B */ +# define EXTFILTER_F1_DEBUGC (3 << EXTFILTER_F1_ACTION_SHIFT) /* Debug Message C */ +#define EXTFILTER_F1_EFT_SHIFT (30) /* Bits 30-31: Extended Filter Type */ +#define EXTFILTER_F1_EFT_MASK (3 << EXTFILTER_F1_EFT_SHIFT) +# define EXTFILTER_F1_EFT_RANGE (0 << EXTFILTER_F1_EFT_SHIFT) /* Range filter from SF1ID to SF2ID */ +# define EXTFILTER_F1_EFT_DUAL (1 << EXTFILTER_F1_EFT_SHIFT) /* Dual ID filter for SF1ID or SF2ID */ +# define EXTFILTER_F1_EFT_CLASSIC (2 << EXTFILTER_F1_EFT_SHIFT) /* Classic filter: SF1ID=filter SF2ID=mask */ +# define EXTFILTER_F1_EFT_NOXIDAM (3 << EXTFILTER_F1_EFT_SHIFT) /* Range filter from EF1ID to EF2ID, no XIDAM */ + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_FDCAN_MCAN_M0_H */ diff --git a/arch/arm/src/common/stm32/hardware/stm32_flash.h b/arch/arm/src/common/stm32/hardware/stm32_flash.h new file mode 100644 index 0000000000000..acfe2f89b921a --- /dev/null +++ b/arch/arm/src/common/stm32/hardware/stm32_flash.h @@ -0,0 +1,43 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/hardware/stm32_flash.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_FLASH_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_FLASH_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#if (defined(CONFIG_STM32_HAVE_IP_FLASH_M0_V1) + \ + defined(CONFIG_STM32_HAVE_IP_FLASH_M3M4_V1)) > 1 +# error Only one STM32 flash IP version must be selected +#endif + +#if defined(CONFIG_STM32_HAVE_IP_FLASH_M0_V1) +# include "hardware/stm32_flash_m0.h" +#elif defined(CONFIG_STM32_HAVE_IP_FLASH_M3M4_V1) +# include "hardware/stm32_flash_v1v2.h" +#else +# error "Unsupported STM32 flash" +#endif + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_FLASH_H */ diff --git a/arch/arm/src/common/stm32/hardware/stm32_flash_m0.h b/arch/arm/src/common/stm32/hardware/stm32_flash_m0.h new file mode 100644 index 0000000000000..17f642f71e6b6 --- /dev/null +++ b/arch/arm/src/common/stm32/hardware/stm32_flash_m0.h @@ -0,0 +1,45 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/hardware/stm32_flash_m0.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_FLASH_M0_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_FLASH_M0_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include "chip.h" + +#if defined(CONFIG_ARCH_CHIP_STM32F0) +# include "hardware/stm32f0_flash.h" +#elif defined(CONFIG_ARCH_CHIP_STM32L0) +# include "hardware/stm32l0_flash.h" +#elif defined(CONFIG_ARCH_CHIP_STM32G0) +# include "hardware/stm32g0_flash.h" +#elif defined(CONFIG_ARCH_CHIP_STM32C0) +# include "hardware/stm32c0_flash.h" +#else +# error "Unsupported STM32 M0 FLASH" +#endif + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_FLASH_M0_H */ diff --git a/arch/arm/src/common/stm32/hardware/stm32_flash_v1v2.h b/arch/arm/src/common/stm32/hardware/stm32_flash_v1v2.h new file mode 100644 index 0000000000000..3a3a5c796b12f --- /dev/null +++ b/arch/arm/src/common/stm32/hardware/stm32_flash_v1v2.h @@ -0,0 +1,793 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/hardware/stm32_flash_v1v2.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_FLASH_V1V2_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_FLASH_V1V2_H + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define _K(x) ((x)*1024) + +#if !defined(CONFIG_STM32_FLASH_CONFIG_DEFAULT) && \ + !defined(CONFIG_STM32_FLASH_CONFIG_4) && \ + !defined(CONFIG_STM32_FLASH_CONFIG_6) && \ + !defined(CONFIG_STM32_FLASH_CONFIG_8) && \ + !defined(CONFIG_STM32_FLASH_CONFIG_B) && \ + !defined(CONFIG_STM32_FLASH_CONFIG_C) && \ + !defined(CONFIG_STM32_FLASH_CONFIG_D) && \ + !defined(CONFIG_STM32_FLASH_CONFIG_E) && \ + !defined(CONFIG_STM32_FLASH_CONFIG_F) && \ + !defined(CONFIG_STM32_FLASH_CONFIG_G) && \ + !defined(CONFIG_STM32_FLASH_CONFIG_I) +# define CONFIG_STM32_FLASH_CONFIG_DEFAULT +#endif + +#if defined(CONFIG_STM32_FLASH_CONFIG_DEFAULT) +# if defined(CONFIG_STM32_STM32L15XX) +# if defined(CONFIG_STM32L1_HIGHDENSITY) + +/* Different STM32L1xxx MCU version are now called by different 'categories' + * instead of 'densities'. Cat.5 MCU can have up to 512KB of FLASH. + * STM32L1xxx also have data EEPROM, up to 16KB. + */ + +# define STM32_FLASH_NPAGES 2048 +# define STM32_FLASH_PAGESIZE 256 +# else + +/* The STM32 (< Cat.5) L15xx/L16xx can support up to 384KB of FLASH. + * (In reality, most supported L15xx parts have no more than 128KB). + * The program memory block is divided into 96 sectors of 4 Kbytes each, + * and each sector is further split up into 16 pages of 256 bytes each. + * The sector is the write protection granularity. In total, the program + * memory block contains 1536 pages. + */ + +# define STM32_FLASH_NPAGES 1536 +# define STM32_FLASH_PAGESIZE 256 +# endif + +/* Maximum EEPROM size on Cat.5 MCU. TODO: this should be in chip config. */ + +# ifndef STM32_EEPROM_SIZE +# define STM32_EEPROM_SIZE (16 * 1024) +# endif + +# elif defined(CONFIG_STM32_LOWDENSITY) +# define STM32_FLASH_NPAGES 32 +# define STM32_FLASH_PAGESIZE 1024 + +# elif defined(CONFIG_STM32_MEDIUMDENSITY) +# define STM32_FLASH_NPAGES 128 +# define STM32_FLASH_PAGESIZE 1024 + +# elif defined(CONFIG_STM32_CONNECTIVITYLINE) +# define STM32_FLASH_NPAGES 128 +# define STM32_FLASH_PAGESIZE 2048 + +# elif defined(CONFIG_STM32_HIGHDENSITY) +# define STM32_FLASH_NPAGES 256 +# define STM32_FLASH_PAGESIZE 2048 + +# elif defined(CONFIG_STM32_STM32F30XX) +# define STM32_FLASH_NPAGES 128 +# define STM32_FLASH_PAGESIZE 2048 + +# elif defined(CONFIG_STM32_STM32F33XX) +# define STM32_FLASH_NPAGES 32 +# define STM32_FLASH_PAGESIZE 2048 + +# elif defined(CONFIG_STM32_STM32F37XX) +# define STM32_FLASH_NPAGES 128 +# define STM32_FLASH_PAGESIZE 2048 + +# elif defined(CONFIG_STM32_HAVE_IP_FLASH_M3M4_F2F4) +# define STM32_FLASH_NPAGES 8 +# define STM32_FLASH_SIZE _K((4 * 16) + (1 * 64) + (3 * 128)) +# define STM32_FLASH_SIZES {_K(16), _K(16), _K(16), _K(16), \ + _K(64),_K(128), _K(128), _K(128)} + + /* STM32F4 has mixed page size */ + +# undef STM32_FLASH_PAGESIZE + +# elif defined(CONFIG_STM32_STM32G4XXX) +# define STM32_FLASH_NPAGES 32 +# define STM32_FLASH_PAGESIZE 4096 + +# endif +#endif /* CONFIG_STM32_FLASH_CONFIG_DEFAULT */ + +/* Override of the Flash Has been Chosen */ + +#if !defined(CONFIG_STM32_FLASH_CONFIG_DEFAULT) + +/* Define the Valid Configuration the F2 and F4 */ + +# if defined(CONFIG_STM32_HAVE_IP_FLASH_M3M4_F2F4) + +# if defined(CONFIG_STM32_FLASH_CONFIG_B) +# define STM32_FLASH_NPAGES 5 +# define STM32_FLASH_SIZE _K((4 * 16) + (1 * 64)) +# define STM32_FLASH_SIZES {_K(16), _K(16), _K(16), _K(16), \ + _K(64)} + +# elif defined(CONFIG_STM32_FLASH_CONFIG_C) +# define STM32_FLASH_NPAGES 6 +# define STM32_FLASH_SIZE _K((4 * 16) + (1 * 64) + (1 * 128)) +# define STM32_FLASH_SIZES {_K(16), _K(16), _K(16), _K(16), \ + _K(64), _K(128)} + +# elif defined(CONFIG_STM32_FLASH_CONFIG_D) && defined(CONFIG_STM32_STM32F4XXX) +# define STM32_FLASH_NPAGES 7 +# define STM32_FLASH_SIZE _K((4 * 16) + (1 * 64) + (2 * 128)) +# define STM32_FLASH_SIZES {_K(16), _K(16), _K(16), _K(16), \ + _K(64), _K(128), _K(128)} + +# elif defined(CONFIG_STM32_FLASH_CONFIG_E) +# define STM32_FLASH_NPAGES 8 +# define STM32_FLASH_SIZE _K((4 * 16) + (1 * 64) + (3 * 128)) +# define STM32_FLASH_SIZES {_K(16), _K(16), _K(16), _K(16), \ + _K(64), _K(128), _K(128), _K(128)} + +# elif defined(CONFIG_STM32_FLASH_CONFIG_F) && defined(CONFIG_STM32_STM32F20XX) +# define STM32_FLASH_NPAGES 9 +# define STM32_FLASH_SIZE _K((4 * 16) + (1 * 64) + (4 * 128)) +# define STM32_FLASH_SIZES {_K(16), _K(16), _K(16), _K(16), \ + _K(64), _K(128), _K(128), _K(128), \ + _K(128)} + +# elif defined(CONFIG_STM32_FLASH_CONFIG_G) +# define STM32_FLASH_NPAGES 12 +# define STM32_FLASH_SIZE _K((4 * 16) + (1 * 64) + (7 * 128)) +# define STM32_FLASH_SIZES {_K(16), _K(16), _K(16), _K(16), \ + _K(64), _K(128), _K(128), _K(128), \ + _K(128), _K(128), _K(128), _K(128)} + +# elif defined(CONFIG_STM32_FLASH_CONFIG_I) && defined(CONFIG_STM32_STM32F4XXX) +# define STM32_FLASH_NPAGES 24 +# define STM32_FLASH_SIZE _K((4 * 16) + (1 * 64) + (7 * 128)) + \ + _K((4 * 16) + (1 * 64) + (7 * 128)) +# define STM32_FLASH_SIZES {_K(16), _K(16), _K(16), _K(16), \ + _K(64), _K(128), _K(128), _K(128), \ + _K(128), _K(128), _K(128), _K(128), \ + _K(16), _K(16), _K(16), _K(16), \ + _K(64), _K(128), _K(128), _K(128), \ + _K(128), _K(128), _K(128), _K(128)} +# endif + +/* Define the Valid Configuration the G4 */ + +# elif defined(CONFIG_STM32_STM32G4XXX) +# if defined(CONFIG_STM32_STM32G43XX) +# if defined(CONFIG_STM32_FLASH_CONFIG_6) +# define STM32_FLASH_NPAGES 16 +# define STM32_FLASH_PAGESIZE 2048 + +# elif defined(CONFIG_STM32_FLASH_CONFIG_8) +# define STM32_FLASH_NPAGES 32 +# define STM32_FLASH_PAGESIZE 2048 + +# elif defined(CONFIG_STM32_FLASH_CONFIG_B) +# define STM32_FLASH_NPAGES 64 +# define STM32_FLASH_PAGESIZE 2048 +# endif +# elif defined(CONFIG_STM32_STM32G47XX) || defined(CONFIG_STM32_STM32G48XX) +# if defined(CONFIG_STM32_FLASH_CONFIG_B) +# define STM32_FLASH_SIZE 32 * 4096 + +# elif defined(CONFIG_STM32_FLASH_CONFIG_C) +# define STM32_FLASH_SIZE 64 * 4096 + +# elif defined(CONFIG_STM32_FLASH_CONFIG_E) +# define STM32_FLASH_SIZE 128 * 4096 +# endif +# elif defined(CONFIG_STM32_STM32G49XX) +# elif defined(CONFIG_STM32_FLASH_CONFIG_C) +# define STM32_FLASH_NPAGES 128 +# define STM32_FLASH_PAGESIZE 2048 + +# elif defined(CONFIG_STM32_FLASH_CONFIG_E) +# define STM32_FLASH_NPAGES 256 +# define STM32_FLASH_PAGESIZE 2048 +# endif + +/* Define the Valid Configuration the F1 and F3 */ + +# else +# if defined(CONFIG_STM32_FLASH_CONFIG_4) +# define STM32_FLASH_NPAGES 16 +# define STM32_FLASH_PAGESIZE 1024 +# elif defined(CONFIG_STM32_FLASH_CONFIG_6) +# define STM32_FLASH_NPAGES 32 +# define STM32_FLASH_PAGESIZE 1024 +# elif defined(CONFIG_STM32_FLASH_CONFIG_8) +# define STM32_FLASH_NPAGES 64 +# define STM32_FLASH_PAGESIZE 1024 +# elif defined(CONFIG_STM32_FLASH_CONFIG_B) +# define STM32_FLASH_NPAGES 128 +# define STM32_FLASH_PAGESIZE 1024 +# elif defined(CONFIG_STM32_FLASH_CONFIG_C) +# define STM32_FLASH_NPAGES 128 +# define STM32_FLASH_PAGESIZE 2048 +# elif defined(CONFIG_STM32_FLASH_CONFIG_D) +# define STM32_FLASH_NPAGES 192 +# define STM32_FLASH_PAGESIZE 2048 +# elif defined(CONFIG_STM32_FLASH_CONFIG_E) +# define STM32_FLASH_NPAGES 256 +# define STM32_FLASH_PAGESIZE 2048 +# elif defined(CONFIG_STM32_FLASH_CONFIG_F) +# define STM32_FLASH_NPAGES 384 +# define STM32_FLASH_PAGESIZE 2048 +# elif defined(CONFIG_STM32_FLASH_CONFIG_G) +# define STM32_FLASH_NPAGES 512 +# define STM32_FLASH_PAGESIZE 2048 +# elif defined(CONFIG_STM32_FLASH_CONFIG_I) +# endif +# endif +#endif /* !defined(CONFIG_STM32_FLASH_CONFIG_DEFAULT) */ + +#ifdef STM32_FLASH_PAGESIZE +# define STM32_FLASH_SIZE (STM32_FLASH_NPAGES * STM32_FLASH_PAGESIZE) +#endif + +/* STM32F101 and STM32F103 with flash size > 512kB are dual-bank devices. + * where bank 0 contains pages 0..255 and bank 1 contains the rest. + */ + +#if defined(CONFIG_STM32_STM32F10XX) && (STM32_FLASH_NPAGES > 256) +# define STM32_FLASH_DUAL_BANK 1 +# define STM32_FLASH_BANK0_NPAGES 256 +# define STM32_FLASH_BANK1_NPAGES (STM32_FLASH_NPAGES - STM32_FLASH_BANK0_NPAGES) +# define STM32_FLASH_BANK0_BASE (STM32_FLASH_BASE) +# define STM32_FLASH_BANK1_BASE \ + (STM32_FLASH_BASE + STM32_FLASH_PAGESIZE * STM32_FLASH_BANK0_NPAGES) +#endif + +/* Register Offsets *********************************************************/ + +#define STM32_FLASH_ACR_OFFSET 0x0000 +#if defined(CONFIG_STM32_STM32L15XX) +# define STM32_FLASH_PECR_OFFSET 0x0004 +# define STM32_FLASH_PDKEYR_OFFSET 0x0008 +# define STM32_FLASH_PEKEYR_OFFSET 0x000c +# define STM32_FLASH_PRGKEYR_OFFSET 0x0010 +# define STM32_FLASH_OPTKEYR_OFFSET 0x0014 +# define STM32_FLASH_SR_OFFSET 0x0018 +# define STM32_FLASH_OBR_OFFSET 0x001c +# define STM32_FLASH_WRPR1_OFFSET 0x0020 +# define STM32_FLASH_WRPR2_OFFSET 0x0080 +# define STM32_FLASH_WRPR3_OFFSET 0x0084 +# define STM32_FLASH_WRPR4_OFFSET 0x0088 +#elif defined(CONFIG_STM32_STM32G4XXX) +# define STM32_FLASH_PDKEYR_OFFSET 0x0004 +# define STM32_FLASH_KEYR_OFFSET 0x0008 +# define STM32_FLASH_OPTKEYR_OFFSET 0x000c +# define STM32_FLASH_SR_OFFSET 0x0010 +# define STM32_FLASH_CR_OFFSET 0x0014 +# define STM32_FLASH_ECCR_OFFSET 0x0018 +# define STM32_FLASH_OPTR_OFFSET 0x0020 +# define STM32_FLASH_PCROP1SR_OFFSET 0x0024 +# define STM32_FLASH_PCROP1ER_OFFSET 0x0028 +# define STM32_FLASH_WRP1AR_OFFSET 0x002c +# define STM32_FLASH_WRP1BR_OFFSET 0x0030 +# define STM32_FLASH_PCROP2SR_OFFSET 0x0044 +# define STM32_FLASH_PCROP2ER_OFFSET 0x0048 +# define STM32_FLASH_WRP2AR_OFFSET 0x004c +# define STM32_FLASH_WRP2BR_OFFSET 0x0050 +# define STM32_FLASH_SEC1R_OFFSET 0x0070 +# define STM32_FLASH_SEC2R_OFFSET 0x0074 +#else +# define STM32_FLASH_KEYR_OFFSET 0x0004 +# define STM32_FLASH_OPTKEYR_OFFSET 0x0008 +# define STM32_FLASH_SR_OFFSET 0x000c +# define STM32_FLASH_CR_OFFSET 0x0010 +# if defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F30XX) || \ + defined(CONFIG_STM32_STM32F33XX) || defined(CONFIG_STM32_STM32F37XX) +# define STM32_FLASH_AR_OFFSET 0x0014 +# define STM32_FLASH_OBR_OFFSET 0x001c +# define STM32_FLASH_WRPR_OFFSET 0x0020 +# elif defined(CONFIG_STM32_HAVE_IP_FLASH_M3M4_F2F4) +# define STM32_FLASH_OPTCR_OFFSET 0x0014 +# endif +#endif + +#if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429) || \ + defined(CONFIG_STM32_STM32F469) +# define STM32_FLASH_OPTCR1_OFFSET 0x0018 +#endif + +#if defined(CONFIG_STM32_STM32F10XX) && defined(STM32_FLASH_DUAL_BANK) +# define STM32_FLASH_BANK0_REGS_OFFSET 0 +# define STM32_FLASH_BANK1_REGS_OFFSET 0x40 + +# define STM32_FLASH_KEYR1_OFFSET 0x0044 +# define STM32_FLASH_SR1_OFFSET 0x004c +# define STM32_FLASH_CR1_OFFSET 0x0050 +# define STM32_FLASH_AR2_OFFSET 0x0054 +#endif + +/* Register Addresses *******************************************************/ + +#define STM32_FLASH_ACR (STM32_FLASHIF_BASE+STM32_FLASH_ACR_OFFSET) +#if defined(CONFIG_STM32_STM32L15XX) +# define STM32_FLASH_PECR (STM32_FLASHIF_BASE+STM32_FLASH_PECR_OFFSET) +# define STM32_FLASH_PDKEYR (STM32_FLASHIF_BASE+STM32_FLASH_PDKEYR_OFFSET) +# define STM32_FLASH_PEKEYR (STM32_FLASHIF_BASE+STM32_FLASH_PEKEYR_OFFSET) +# define STM32_FLASH_PRGKEYR (STM32_FLASHIF_BASE+STM32_FLASH_PRGKEYR_OFFSET) +# define STM32_FLASH_OPTKEYR (STM32_FLASHIF_BASE+STM32_FLASH_OPTKEYR_OFFSET) +# define STM32_FLASH_SR (STM32_FLASHIF_BASE+STM32_FLASH_SR_OFFSET) +# define STM32_FLASH_OBR (STM32_FLASHIF_BASE+STM32_FLASH_OBR_OFFSET) +# define STM32_FLASH_WRPR1 (STM32_FLASHIF_BASE+STM32_FLASH_WRPR1_OFFSET) +# define STM32_FLASH_WRPR2 (STM32_FLASHIF_BASE+STM32_FLASH_WRPR2_OFFSET) +# define STM32_FLASH_WRPR3 (STM32_FLASHIF_BASE+STM32_FLASH_WRPR3_OFFSET) +# define STM32_FLASH_WRPR4 (STM32_FLASHIF_BASE+STM32_FLASH_WRPR4_OFFSET) +#elif defined(CONFIG_STM32_STM32G4XXX) +# define STM32_FLASH_PDKEYR (STM32_FLASHIF_BASE+STM32_FLASH_PDKEYR_OFFSET) +# define STM32_FLASH_KEYR (STM32_FLASHIF_BASE+STM32_FLASH_KEYR_OFFSET) +# define STM32_FLASH_OPTKEYR (STM32_FLASHIF_BASE+STM32_FLASH_OPTKEYR_OFFSET) +# define STM32_FLASH_SR (STM32_FLASHIF_BASE+STM32_FLASH_SR_OFFSET) +# define STM32_FLASH_CR (STM32_FLASHIF_BASE+STM32_FLASH_CR_OFFSET) +# define STM32_FLASH_ECCR (STM32_FLASHIF_BASE+STM32_FLASH_ECCR_OFFSET) +# define STM32_FLASH_OPTR (STM32_FLASHIF_BASE+STM32_FLASH_OPTR_OFFSET) +# define STM32_FLASH_PCROP1SR (STM32_FLASHIF_BASE+STM32_FLASH_PCROP1SR_OFFSET) +# define STM32_FLASH_PCROP1ER (STM32_FLASHIF_BASE+STM32_FLASH_PCROP1ER_OFFSET) +# define STM32_FLASH_WRP1AR (STM32_FLASHIF_BASE+STM32_FLASH_WRP1AR_OFFSET) +# define STM32_FLASH_WRP1BR (STM32_FLASHIF_BASE+STM32_FLASH_WRP1BR_OFFSET) +# define STM32_FLASH_PCROP2SR (STM32_FLASHIF_BASE+STM32_FLASH_PCROP2SR_OFFSET) +# define STM32_FLASH_PCROP2ER (STM32_FLASHIF_BASE+STM32_FLASH_PCROP2ER_OFFSET) +# define STM32_FLASH_WRP2AR (STM32_FLASHIF_BASE+STM32_FLASH_WRP2AR_OFFSET) +# define STM32_FLASH_WRP2BR (STM32_FLASHIF_BASE+STM32_FLASH_WRP2BR_OFFSET) +# define STM32_FLASH_SEC1R (STM32_FLASHIF_BASE+STM32_FLASH_SEC1R_OFFSET) +# define STM32_FLASH_SEC2R (STM32_FLASHIF_BASE+STM32_FLASH_SEC2R_OFFSET) +#else +# define STM32_FLASH_KEYR (STM32_FLASHIF_BASE+STM32_FLASH_KEYR_OFFSET) +# define STM32_FLASH_OPTKEYR (STM32_FLASHIF_BASE+STM32_FLASH_OPTKEYR_OFFSET) +# define STM32_FLASH_SR (STM32_FLASHIF_BASE+STM32_FLASH_SR_OFFSET) +# define STM32_FLASH_CR (STM32_FLASHIF_BASE+STM32_FLASH_CR_OFFSET) + +# if defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F30XX) || \ + defined(CONFIG_STM32_STM32F33XX) || defined(CONFIG_STM32_STM32F37XX) +# define STM32_FLASH_AR (STM32_FLASHIF_BASE+STM32_FLASH_AR_OFFSET) +# define STM32_FLASH_OBR (STM32_FLASHIF_BASE+STM32_FLASH_OBR_OFFSET) +# define STM32_FLASH_WRPR (STM32_FLASHIF_BASE+STM32_FLASH_WRPR_OFFSET) +# elif defined(CONFIG_STM32_HAVE_IP_FLASH_M3M4_F2F4) +# define STM32_FLASH_OPTCR (STM32_FLASHIF_BASE+STM32_FLASH_OPTCR_OFFSET) +# endif +# if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429) || \ + defined(CONFIG_STM32_STM32F469) +# define STM32_FLASH_OPTCR1 (STM32_FLASHIF_BASE+STM32_FLASH_OPTCR1_OFFSET) +# endif +#endif + +#if defined(CONFIG_STM32_STM32F10XX) && defined(STM32_FLASH_DUAL_BANK) +# define STM32_FLASH_KEYR1 (STM32_FLASHIF_BASE+STM32_FLASH_KEYR1_OFFSET) +# define STM32_FLASH_SR1 (STM32_FLASHIF_BASE+STM32_FLASH_SR1_OFFSET) +# define STM32_FLASH_CR1 (STM32_FLASHIF_BASE+STM32_FLASH_CR1_OFFSET) +# define STM32_FLASH_AR2 (STM32_FLASHIF_BASE+STM32_FLASH_AR1_OFFSET) +#endif + +/* Register Bitfield Definitions ********************************************/ + +/* Flash Access Control Register (ACR) */ + +#if defined(CONFIG_STM32_STM32L15XX) +# define FLASH_ACR_LATENCY (1 << 0) /* Bit 0: Latency */ +# define FLASH_ACR_PRFTEN (1 << 1) /* Bit 1: Prefetch enable */ +# define FLASH_ACR_ACC64 (1 << 2) /* Bit 2: 64-bit access */ +# define FLASH_ACR_SLEEP_PD (1 << 3) /* Bit 3: Flash mode during Sleep */ +# define FLASH_ACR_RUN_PD (1 << 4) /* Bit 4: Flash mode during Run */ +#elif defined(CONFIG_STM32_STM32G4XXX) +# define FLASH_ACR_LATENCY_SHIFT (0) +# define FLASH_ACR_LATENCY_MASK (0xf << FLASH_ACR_LATENCY_SHIFT) +# define FLASH_ACR_LATENCY(n) ((n) << FLASH_ACR_LATENCY_SHIFT) /* n wait states = 0..15 */ +# define FLASH_ACR_LATENCY_0 (0 << FLASH_ACR_LATENCY_SHIFT) /* 0000: Zero wait states */ +# define FLASH_ACR_LATENCY_1 (1 << FLASH_ACR_LATENCY_SHIFT) /* 0001: One wait state */ +# define FLASH_ACR_LATENCY_2 (2 << FLASH_ACR_LATENCY_SHIFT) /* 0010: Two wait states */ +# define FLASH_ACR_LATENCY_3 (3 << FLASH_ACR_LATENCY_SHIFT) /* 0011: Three wait states */ +# define FLASH_ACR_LATENCY_4 (4 << FLASH_ACR_LATENCY_SHIFT) /* 0100: Four wait states */ +# define FLASH_ACR_LATENCY_5 (5 << FLASH_ACR_LATENCY_SHIFT) /* 0101: Five wait states */ +# define FLASH_ACR_LATENCY_6 (6 << FLASH_ACR_LATENCY_SHIFT) /* 0110: Six wait states */ +# define FLASH_ACR_LATENCY_7 (7 << FLASH_ACR_LATENCY_SHIFT) /* 0111: Seven wait states */ +# define FLASH_ACR_LATENCY_8 (8 << FLASH_ACR_LATENCY_SHIFT) /* 1000: Eight wait states */ +# define FLASH_ACR_LATENCY_9 (9 << FLASH_ACR_LATENCY_SHIFT) /* 1001: Nine wait state */ +# define FLASH_ACR_LATENCY_10 (10 << FLASH_ACR_LATENCY_SHIFT) /* 1010: Ten wait states */ +# define FLASH_ACR_LATENCY_11 (11 << FLASH_ACR_LATENCY_SHIFT) /* 1011: Eleven wait states */ +# define FLASH_ACR_LATENCY_12 (12 << FLASH_ACR_LATENCY_SHIFT) /* 1100: Twelve wait states */ +# define FLASH_ACR_LATENCY_13 (13 << FLASH_ACR_LATENCY_SHIFT) /* 1101: Thirteen wait states */ +# define FLASH_ACR_LATENCY_14 (14 << FLASH_ACR_LATENCY_SHIFT) /* 1110: Fourteen wait states */ +# define FLASH_ACR_LATENCY_15 (15 << FLASH_ACR_LATENCY_SHIFT) /* 1111: Fifteen wait states */ +# define FLASH_ACR_PRFTEN (1 << 8) /* Bit 8: FLASH prefetch enable */ +# define FLASH_ACR_ICEN (1 << 9) /* Bit 9: Instruction cache enable */ +# define FLASH_ACR_DCEN (1 << 10) /* Bit 10: Data cache enable */ +# define FLASH_ACR_ICRST (1 << 11) /* Bit 11: Instruction cache reset */ +# define FLASH_ACR_DCRST (1 << 12) /* Bit 12: Data cache reset */ +# define FLASH_ACR_RUNPD (1 << 13) /* Bit 13: Flash Power Down Mode During Run or Low Power Run */ +# define FLASH_ACR_SLEEPPD (1 << 14) /* Bit 14: Flash Power Down Mode During Sleep or Low Power Sleep */ +# define FLASH_ACR_DBG_SWEN (1 << 18) /* Bit 18: Debug Software Enable */ +#else +# define FLASH_ACR_LATENCY_SHIFT (0) +# define FLASH_ACR_LATENCY_MASK (7 << FLASH_ACR_LATENCY_SHIFT) +# define FLASH_ACR_LATENCY(n) ((n) << FLASH_ACR_LATENCY_SHIFT) /* n wait states */ +# define FLASH_ACR_LATENCY_0 (0 << FLASH_ACR_LATENCY_SHIFT) /* 000: Zero wait states */ +# define FLASH_ACR_LATENCY_1 (1 << FLASH_ACR_LATENCY_SHIFT) /* 001: One wait state */ +# define FLASH_ACR_LATENCY_2 (2 << FLASH_ACR_LATENCY_SHIFT) /* 010: Two wait states */ +# define FLASH_ACR_LATENCY_3 (3 << FLASH_ACR_LATENCY_SHIFT) /* 011: Three wait states */ +# define FLASH_ACR_LATENCY_4 (4 << FLASH_ACR_LATENCY_SHIFT) /* 100: Four wait states */ +# define FLASH_ACR_LATENCY_5 (5 << FLASH_ACR_LATENCY_SHIFT) /* 101: Five wait states */ +# define FLASH_ACR_LATENCY_6 (6 << FLASH_ACR_LATENCY_SHIFT) /* 110: Six wait states */ +# define FLASH_ACR_LATENCY_7 (7 << FLASH_ACR_LATENCY_SHIFT) /* 111: Seven wait states */ + +# if defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F30XX) || \ + defined(CONFIG_STM32_STM32F33XX) || defined(CONFIG_STM32_STM32F37XX) +# define FLASH_ACR_HLFCYA (1 << 3) /* Bit 3: FLASH half cycle access */ +# define FLASH_ACR_PRTFBE (1 << 4) /* Bit 4: FLASH prefetch enable */ +# if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) || \ + defined(CONFIG_STM32_STM32F37XX) +# define FLASH_ACR_PRFTBS (1 << 5) /* Bit 5: FLASH prefetch buffer status */ +# endif +# elif defined(CONFIG_STM32_HAVE_IP_FLASH_M3M4_F2F4) +# define FLASH_ACR_PRFTEN (1 << 8) /* FLASH prefetch enable */ +# define FLASH_ACR_ICEN (1 << 9) /* Bit 9: Instruction cache enable */ +# define FLASH_ACR_DCEN (1 << 10) /* Bit 10: Data cache enable */ +# define FLASH_ACR_ICRST (1 << 11) /* Bit 11: Instruction cache reset */ +# define FLASH_ACR_DCRST (1 << 12) /* Bit 12: Data cache reset */ +# endif +#endif + +/* Flash Status Register (SR) */ + +#if defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F30XX) || \ + defined(CONFIG_STM32_STM32F33XX) || defined(CONFIG_STM32_STM32F37XX) +# define FLASH_SR_BSY (1 << 0) /* Busy */ +# define FLASH_SR_PGERR (1 << 2) /* Programming Error */ +# define FLASH_SR_WRPRT_ERR (1 << 4) /* Write Protection Error */ +# define FLASH_SR_EOP (1 << 5) /* End of Operation */ +#elif defined(CONFIG_STM32_HAVE_IP_FLASH_M3M4_F2F4) +# define FLASH_SR_EOP (1 << 0) /* Bit 0: End of operation */ +# define FLASH_SR_OPERR (1 << 1) /* Bit 1: Operation error */ +# define FLASH_SR_WRPERR (1 << 4) /* Bit 4: Write protection error */ +# define FLASH_SR_PGAERR (1 << 5) /* Bit 5: Programming alignment error */ +# define FLASH_SR_PGPERR (1 << 6) /* Bit 6: Programming parallelism error */ +# define FLASH_SR_PGSERR (1 << 7) /* Bit 7: Programming sequence error */ +# define FLASH_SR_BSY (1 << 16) /* Bit 16: Busy */ +#elif defined(CONFIG_STM32_STM32L15XX) +# define FLASH_SR_BSY (1 << 0) /* Bit 0: Busy */ +# define FLASH_SR_EOP (1 << 1) /* Bit 1: End of operation */ +# define FLASH_SR_ENDHV (1 << 2) /* Bit 2: End of high voltage */ +# define FLASH_SR_READY (1 << 3) /* Bit 3: Flash memory module ready after low power mode */ +# define FLASH_SR_WRPERR (1 << 8) /* Bit 8: Write protection error */ +# define FLASH_SR_PGAERR (1 << 9) /* Bit 9: Programming alignment error */ +# define FLASH_SR_SIZERR (1 << 10) /* Bit 10: Size error */ +# define FLASH_SR_OPTVERR (1 << 11) /* Bit 11: Option validity error */ +# define FLASH_SR_OPTVERRUSR (1 << 12) /* Bit 12: Option UserValidity Error */ +# define FLASH_SR_RDERR (1 << 13) /* Bit 13: Read protected error */ +#elif defined(CONFIG_STM32_STM32G4XXX) +# define FLASH_SR_EOP (1 << 0) /* Bit 0: End of operation */ +# define FLASH_SR_OPERR (1 << 1) /* Bit 1: Operation error */ +# define FLASH_SR_PROGERR (1 << 3) /* Bit 3: Programming error */ +# define FLASH_SR_WRPERR (1 << 4) /* Bit 4: Write protection error */ +# define FLASH_SR_PGAERR (1 << 5) /* Bit 5: Programming alignment error */ +# define FLASH_SR_SIZERR (1 << 6) /* Bit 6: Size error */ +# define FLASH_SR_PGSERR (1 << 7) /* Bit 7: Programming sequence error */ +# define FLASH_SR_MISERR (1 << 8) /* Bit 8: Fast programming data miss error */ +# define FLASH_SR_FASTERR (1 << 9) /* Bit 9: Fast programming error */ +# define FLASH_SR_RDERR (1 << 14) /* Bit 14: PCROP read error */ +# define FLASH_SR_OPTVERR (1 << 15) /* Bit 15: Option validity error */ +# define FLASH_SR_BSY (1 << 16) /* Bit 16: Busy */ +#endif + +/* Program/Erase Control Register (PECR) */ + +#if defined(CONFIG_STM32_STM32L15XX) +# define FLASH_PECR_PELOCK (1 << 0) /* Bit 0: PECR and data EEPROM lock */ +# define FLASH_PECR_PRGLOCK (1 << 1) /* Bit 1: Program memory lock */ +# define FLASH_PECR_OPTLOCK (1 << 2) /* Bit 2: Option bytes block lock */ +# define FLASH_PECR_PROG (1 << 3) /* Bit 3: Program memory selection */ +# define FLASH_PECR_DATA (1 << 4) /* Bit 4: Data EEPROM selection */ +# define FLASH_PECR_FTDW (1 << 8) /* Bit 8: Fixed time data write for Byte, Half Word and Word programming */ +# define FLASH_PECR_ERASE (1 << 9) /* Bit 9: Page or Double Word erase mode */ +# define FLASH_PECR_FPRG (1 << 10) /* Bit 10: Half Page/Double Word programming mode */ +# define FLASH_PECR_PARALLBANK (1 << 15) /* Bit 15: Parallel bank mode */ +# define FLASH_PECR_EOPIE (1 << 16) /* Bit 16: End of programming interrupt enable */ +# define FLASH_PECR_ERRIE (1 << 17) /* Bit 17: Error interrupt enable */ +# define FLASH_PECR_OBL_LAUNCH (1 << 18) /* Bit 18: Launch the option byte loading */ +#endif + +/* Flash Control Register (CR) */ + +#if defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F30XX) || \ + defined(CONFIG_STM32_STM32F33XX) || defined(CONFIG_STM32_STM32F37XX) +# define FLASH_CR_PG (1 << 0) /* Bit 0: Program Page */ +# define FLASH_CR_PER (1 << 1) /* Bit 1: Page Erase */ +# define FLASH_CR_MER (1 << 2) /* Bit 2: Mass Erase */ +# define FLASH_CR_OPTPG (1 << 4) /* Bit 4: Option Byte Programming */ +# define FLASH_CR_OPTER (1 << 5) /* Bit 5: Option Byte Erase */ +# define FLASH_CR_STRT (1 << 6) /* Bit 6: Start Erase */ +# define FLASH_CR_LOCK (1 << 7) /* Bit 7: Page Locked or Lock Page */ +# define FLASH_CR_OPTWRE (1 << 9) /* Bit 8: Option Bytes Write Enable */ +# define FLASH_CR_ERRIE (1 << 10) /* Bit 10: Error Interrupt Enable */ +# define FLASH_CR_EOPIE (1 << 12) /* Bit 12: End of Program Interrupt Enable */ +# if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) || \ + defined(CONFIG_STM32_STM32F37XX) +# define FLASH_CR_OBL_LAUNCH (1 << 13) /* Bit 13: Force option byte loading */ +# endif +#elif defined(CONFIG_STM32_HAVE_IP_FLASH_M3M4_F2F4) +# define FLASH_CR_PG (1 << 0) /* Bit 0: Programming */ +# define FLASH_CR_SER (1 << 1) /* Bit 1: Sector Erase */ +# define FLASH_CR_MER (1 << 2) /* Bit 2: Mass Erase sectors 0..11 */ +# define FLASH_CR_SNB_SHIFT (3) /* Bits 3-6: Sector number */ +# if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429) +# define FLASH_CR_SNB_MASK (31 << FLASH_CR_SNB_SHIFT) +# define FLASH_CR_SNB(n) (((n % 12) << FLASH_CR_SNB_SHIFT) | ((n / 12) << 7)) /* Sector n, n=0..23 */ +# else +# define FLASH_CR_SNB_MASK (15 << FLASH_CR_SNB_SHIFT) +# define FLASH_CR_SNB(n) ((n) << FLASH_CR_SNB_SHIFT) /* Sector n, n=0..11 */ +# endif +# define FLASH_CR_PSIZE_SHIFT (8) /* Bits 8-9: Program size */ +# define FLASH_CR_PSIZE_MASK (3 << FLASH_CR_PSIZE_SHIFT) +# define FLASH_CR_PSIZE_X8 (0 << FLASH_CR_PSIZE_SHIFT) /* 00 program x8 */ +# define FLASH_CR_PSIZE_X16 (1 << FLASH_CR_PSIZE_SHIFT) /* 01 program x16 */ +# define FLASH_CR_PSIZE_X32 (2 << FLASH_CR_PSIZE_SHIFT) /* 10 program x32 */ +# define FLASH_CR_PSIZE_X64 (3 << FLASH_CR_PSIZE_SHIFT) /* 11 program x64 */ +# define FLASH_CR_STRT (1 << 16) /* Bit 16: Start Erase */ +# define FLASH_CR_EOPIE (1 << 24) /* Bit 24: End of operation interrupt enable */ +# define FLASH_CR_ERRIE (1 << 25) /* Bit 25: Error interrupt enable */ +# define FLASH_CR_LOCK (1 << 31) /* Bit 31: Lock */ +#elif defined(CONFIG_STM32_STM32G4XXX) +# define FLASH_CR_PG (1 << 0) +# define FLASH_CR_PER (1 << 1) +# define FLASH_CR_MER1 (1 << 2) +# define FLASH_CR_PNB_SHIFT (3) +# if defined(CONFIG_STM32_STM32G43XX) +# define FLASH_CR_PNB_MASK (0x3f << FLASH_CR_PNB_SHIFT) +# elif defined(CONFIG_STM32_STM32G47XX) || defined (CONFIG_STM32_STM32G48XX) +# define FLASH_CR_PNB_MASK (0x7f << FLASH_CR_PNB_SHIFT) +# elif defined(CONFIG_STM32_STM32G49XX) +# define FLASH_CR_PNB_MASK (0xff << FLASH_CR_PNB_SHIFT) +# endif +# define FLASH_CR_PNB(n) (((n) << FLASH_CR_PNB_SHIFT) & FLASH_CR_PNB_MASK) +# if defined(CONFIG_STM32_STM32G47XX) || defined (CONFIG_STM32_STM32G48XX) +# define FLASH_CR_BKER (1 << 11) +# define FLASH_CR_MER2 (1 << 15) +# endif +# define FLASH_CR_START (1 << 16) +# define FLASH_CR_OPTSTRT (1 << 17) +# define FLASH_CR_FSTPG (1 << 18) +# define FLASH_CR_EOPIE (1 << 24) +# define FLASH_CR_ERRIE (1 << 25) +# define FLASH_CR_RDERRIE (1 << 26) +# define FLASH_CR_OBL_LAUNCH (1 << 27) +# define FLASH_CR_SEC_PROT1 (1 << 28) +# if defined(CONFIG_STM32_STM32G47XX) || defined (CONFIG_STM32_STM32G48XX) +# define FLASH_CR_SEC_PROT2 (1 << 29) +# endif +# define FLASH_CR_OPTLOCK (1 << 30) +# define FLASH_CR_LOCK (1 << 31) +#endif +#if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429) +# define FLASH_CR_MER1 (1 << 15) /* Bit 15: Mass Erase sectors 12..23 */ +#endif + +/* Flash ECC register (ECCR) */ + +#if defined(CONFIG_STM32_STM32G4XXX) +# define FLASH_ECCR_ADDR_ECC_SHIFT (0) +# define FLASH_ECCR_ADDR_ECC_MASK (0x7ffff << FLASH_ECCR_ADDR_ECC_SHIFT) +# define FLASH_ECCR_ADDR_ECC(n) (((n) << FLASH_ECCR_ADDR_ECC_SHIFT) & FLASH_ECCR_ADDR_ECC_MASK) + +# define FLASH_ECCR_BK_ECC (1 << 21) +# define FLASH_ECCR_SYSF_ECC (1 << 22) +# define FLASH_ECCR_ECCIE (1 << 24) +# if defined(CONFIG_STM32_STM32G47XX) || defined (CONFIG_STM32_STM32G48XX) +# define FLASH_ECCR_ECCC2 (1 << 28) +# define FLASH_ECCR_ECCD2 (1 << 29) +# endif +# define FLASH_ECCR_ECCC (1 << 30) +# define FLASH_ECCR_ECCD (1 << 31) +#endif + +/* Flash Option Control Register (OPTCR) */ + +#if defined(CONFIG_STM32_HAVE_IP_FLASH_M3M4_F2F4) +# define FLASH_OPTCR_OPTLOCK (1 << 0) /* Bit 0: Option lock */ +# define FLASH_OPTCR_OPTSTRT (1 << 1) /* Bit 1: Option start */ +# define FLASH_OPTCR_BORLEV_SHIFT (2) /* Bits 2-3: BOR reset Level */ +# define FLASH_OPTCR_BORLEV_MASK (3 << FLASH_OPTCR_BORLEV_SHIFT) +# define FLASH_OPTCR_VBOR3 (0 << FLASH_OPTCR_BORLEV_SHIFT) /* 00: BOR Level 3 */ +# define FLASH_OPTCR_VBOR2 (1 << FLASH_OPTCR_BORLEV_SHIFT) /* 01: BOR Level 2 */ +# define FLASH_OPTCR_VBOR1 (2 << FLASH_OPTCR_BORLEV_SHIFT) /* 10: BOR Level 1 */ +# define FLASH_OPTCR_VBOR0 (3 << FLASH_OPTCR_BORLEV_SHIFT) /* 11: BOR off */ +# define FLASH_OPTCR_USER_SHIFT (5) /* Bits 5-7: User option bytes */ +# define FLASH_OPTCR_USER_MASK (7 << FLASH_OPTCR_USER_SHIFT) +# define FLASH_OPTCR_NRST_STDBY (1 << 7) /* Bit 7: nRST_STDBY */ +# define FLASH_OPTCR_NRST_STOP (1 << 6) /* Bit 6: nRST_STOP */ +# define FLASH_OPTCR_WDG_SW (1 << 5) /* Bit 5: WDG_SW */ +# define FLASH_OPTCR_RDP_SHIFT (8) /* Bits 8-15: Read protect */ +# define FLASH_OPTCR_RDP_MASK (0xff << FLASH_OPTCR_RDP_SHIFT) +# define FLASH_OPTCR_RDP(n) ((uint32_t)(n) << FLASH_OPTCR_RDP_SHIFT) +# define FLASH_OPTCR_NWRP_SHIFT (16) /* Bits 16-27: Not write protect */ +# define FLASH_OPTCR_NWRP_MASK (0xfff << FLASH_OPTCR_NWRP_SHIFT) +#endif + +/* Flash Option Control Register (OPTCR1) */ + +#if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429) +# define FLASH_OPTCR1_NWRP_SHIFT (16) /* Bits 16-27: Not write protect (high bank) */ +# define FLASH_OPTCR1_NWRP_MASK (0xfff << FLASH_OPTCR_NWRP_SHIFT) + +# define FLASH_OPTCR1_BFB2_SHIFT (4) /* Bits 4: Dual-bank Boot option byte */ +# define FLASH_OPTCR1_BFB2_MASK (1 << FLASH_OPTCR_NWRP_SHIFT) +#endif + +#if defined(CONFIG_STM32_STM32F446) +# define FLASH_OPTCR1_NWRP_SHIFT (16) /* Bits 16-23: Not write protect (high bank) */ +# define FLASH_OPTCR1_NWRP_MASK (0xff << FLASH_OPTCR_NWRP_SHIFT) +#endif + +/* Flash option register (OPTR) */ + +#if defined(CONFIG_STM32_STM32G4XXX) +# define FLASH_OPTR_RDP_SHIFT (0) +# define FLASH_OPTR_RDP_MASK (0xff << FLASH_OPTR_RDP_SHIFT) +# define FLASH_OPTR_RDP (((n) << FLASH_OPTR_RDP_SHIFT) & FLASH_OPTR_RDP_MASK) +# define FLASH_OPTR_BOR_LEV_SHIFT (8) +# define FLASH_OPTR_BOR_LEV_MASK (0x7 << FLASH_OPTR_BOR_LEV_SHIFT) +# define FLASH_OPTR_BOR_LEV_1_7V (0x0 << FLASH_OPTR_BOR_LEV_SHIFT) +# define FLASH_OPTR_BOR_LEV_2_0V (0x1 << FLASH_OPTR_BOR_LEV_SHIFT) +# define FLASH_OPTR_BOR_LEV_2_2V (0x2 << FLASH_OPTR_BOR_LEV_SHIFT) +# define FLASH_OPTR_BOR_LEV_2_5V (0x3 << FLASH_OPTR_BOR_LEV_SHIFT) +# define FLASH_OPTR_BOR_LEV_2_8V (0x4 << FLASH_OPTR_BOR_LEV_SHIFT) +# define FLASH_OPTR_NRST_STOP (1 << 12) +# define FLASH_OPTR_NRST_STDBY (1 << 13) +# define FLASH_OPTR_NRST_SHDW (1 << 14) +# define FLASH_OPTR_IWDG_SW (1 << 16) +# define FLASH_OPTR_IWDG_STOP (1 << 17) +# define FLASH_OPTR_IWDG_STDBY (1 << 18) +# define FLASH_OPTR_WWDG_SW (1 << 19) +# define FLASH_OPTR_BFB2 (1 << 20) +# if defined(CONFIG_STM32_STM32G47XX) || defined (CONFIG_STM32_STM32G48XX) +# define FLASH_OPTR_DBANK (1 << 22) +# elif defined (CONFIG_STM32_STM32G49XX) +# define FLASH_OPTR_PB4_PUPEN (1 << 22) +# endif +# define FLASH_OPTR_NBOOT1 (1 << 23) +# define FLASH_OPTR_SRAM_PE (1 << 24) +# define FLASH_OPTR_CCMSRAM_RST (1 << 25) +# define FLASH_OPTR_NSWBOOT0 (1 << 26) +# define FLASH_OPTR_NBOOT0 (1 << 27) +# define FLASH_OPTR_NRST_MODE_SHIFT (28) +# define FLASH_OPTR_NRST_MODE_MASK (0x3 << FLASH_OPTR_NRST_MODE_SHIFT) +# define FLASH_OPTR_NRST_MODE_NRST (0x1 << FLASH_OPTR_NRST_MODE_SHIFT) +# define FLASH_OPTR_NRST_MODE_GPIO (0x2 << FLASH_OPTR_NRST_MODE_SHIFT) +# define FLASH_OPTR_NRST_MODE_BIDI_NRST (0x3 << FLASH_OPTR_NRST_MODE_SHIFT) +# define FLASH_OPTR_IRHEN (1 << 30) +#endif + +/* Flash PCROP1 Start Address Register (PCROP1SR) */ + +#if defined(CONFIG_STM32_STM32G4XXX) +# define FLASH_PCROP1SR_PCROP1_STRT_SHIFT (0) +# define FLASH_PCROP1SR_PCROP1_STRT_MASK (0x7fff << FLASH_PCROP1SR_PCROP1_STRT_SHIFT) +# define FLASH_PCROP1SR_PCROP1_STRT(n) (((n) << FLASH_PCROP1SR_PCROP1_STRT_SHIFT) & FLASH_PCROP1SR_PCROP1_STRT_MASK) +#endif + +/* Flash PCROP1 End Address Register (PCROP1ER) */ + +#if defined(CONFIG_STM32_STM32G4XXX) +# define FLASH_PCROP1ER_PCROP1_END_SHIFT (0) +# define FLASH_PCROP1ER_PCROP1_END_MASK (0x7fff << FLASH_PCROP1ER_PCROP1_END_SHIFT) +# define FLASH_PCROP1ER_PCROP1_END(n) (((n) << FLASH_PCROP1ER_PCROP1_END_SHIFT) & FLASH_PCROP1ER_PCROP1_END_MASK) +# define FLASH_PCROP1ER_PCROP_RDP (1 << 31) +#endif + +/* Flash Bank 1 WRP Area A Address Register (WRP1AR) */ + +#if defined(CONFIG_STM32_STM32G4XXX) +# define FLASH_WRP1AR_WRP1A_STRT_SHIFT (0) +# define FLASH_WRP1AR_WRP1A_STRT_MASK (0x7f << FLASH_WRP1AR_WRP1A_STRT_SHIFT) +# define FLASH_WRP1AR_WRP1A_STRT(n) (((n) << FLASH_WRP1AR_WRP1A_STRT_SHIFT) & FLASH_WRP1AR_WRP1A_STRT_MASK) +# define FLASH_WRP1AR_WRP1A_END_SHIFT (16) +# define FLASH_WRP1AR_WRP1A_END_MASK (0x7f << FLASH_WRP1AR_WRP1A_END_SHIFT) +# define FLASH_WRP1AR_WRP1A_END(n) (((n) << FLASH_WRP1AR_WRP1A_END_SHIFT) & FLASH_WRP1AR_WRP1A_END_MASK) +#endif + +/* Flash Bank 1 WRP Area B Address Register (WRPB1R) */ + +#if defined(CONFIG_STM32_STM32G4XXX) +# define FLASH_WRP1BR_WRP1B_STRT_SHIFT (0) +# define FLASH_WRP1BR_WRP1B_STRT_MASK (0x7f << FLASH_WRP1BR_WRP1B_STRT_SHIFT) +# define FLASH_WRP1BR_WRP1B_STRT(n) (((n) << FLASH_WRP1BR_WRP1B_STRT_SHIFT) & FLASH_WRP1BR_WRP1B_STRT_MASK) +# define FLASH_WRP1BR_WRP1B_END_SHIFT (16) +# define FLASH_WRP1BR_WRP1B_END_MASK (0x7f << FLASH_WRP1BR_WRP1B_END_SHIFT) +# define FLASH_WRP1BR_WRP1B_END(n) (((n) << FLASH_WRP1BR_WRP1B_END_SHIFT) & FLASH_WRP1BR_WRP1B_END_MASK) +#endif + +/* Flash PCROP2 Start Address Register (PCROP2SR) */ + +#if defined(CONFIG_STM32_STM32G4XXX) +# define FLASH_PCROP2SR_PCROP2_STRT_SHIFT (0) +# define FLASH_PCROP2SR_PCROP2_STRT_MASK (0x7fff << FLASH_PCROP2SR_PCROP2_STRT_SHIFT) +# define FLASH_PCROP2SR_PCROP2_STRT(n) (((n) << FLASH_PCROP2SR_PCROP2_STRT_SHIFT) & FLASH_PCROP2SR_PCROP2_STRT_MASK) +#endif + +/* Flash PCROP2 End Address Register (PCROP2ER) */ + +#if defined(CONFIG_STM32_STM32G4XXX) +# define FLASH_PCROP2ER_PCROP2_END_SHIFT (0) +# define FLASH_PCROP2ER_PCROP2_END_MASK (0x7fff << FLASH_PCROP2ER_PCROP2_END_SHIFT) +# define FLASH_PCROP2ER_PCROP2_END(n) (((n) << FLASH_PCROP2ER_PCROP2_END_SHIFT) & FLASH_PCROP2ER_PCROP2_END_MASK) +#endif + +/* Flash Bank 2 WRP Area A Address Register (WRP2AR) */ + +#if defined(CONFIG_STM32_STM32G4XXX) +# define FLASH_WRP2AR_WRP2A_STRT_SHIFT (0) +# define FLASH_WRP2AR_WRP2A_STRT_MASK (0x7f << FLASH_WRP2AR_WRP2A_STRT_SHIFT) +# define FLASH_WRP2AR_WRP2A_STRT(n) (((n) << FLASH_WRP2AR_WRP2A_STRT_SHIFT) & FLASH_WRP2AR_WRP2A_STRT_MASK) +# define FLASH_WRP2AR_WRP2A_END_SHIFT (16) +# define FLASH_WRP2AR_WRP2A_END_MASK (0x7f << FLASH_WRP2AR_WRP2A_END_SHIFT) +# define FLASH_WRP2AR_WRP2A_END(n) (((n) << FLASH_WRP2AR_WRP2A_END_SHIFT) & FLASH_WRP2AR_WRP2A_END_MASK) +#endif + +/* Flash Bank 2 WRP Area B Address Register (WRP2BR) */ + +#if defined(CONFIG_STM32_STM32G4XXX) +# define FLASH_WRP2BR_WRP2B_STRT_SHIFT (0) +# define FLASH_WRP2BR_WRP2B_STRT_MASK (0x7f << FLASH_WRP2BR_WRP2B_STRT_SHIFT) +# define FLASH_WRP2BR_WRP2B_STRT(n) (((n) << FLASH_WRP2BR_WRP2B_STRT_SHIFT) & FLASH_WRP2BR_WRP2B_STRT_SHIFT) +# define FLASH_WRP2BR_WRP2B_END_SHIFT (16) +# define FLASH_WRP2BR_WRP2B_END_MASK (0x7f << FLASH_WRP2BR_WRP2B_END_SHIFT) +# define FLASH_WRP2BR_WRP2B_END(n) (((n) << FLASH_WRP2BR_WRP2B_END_SHIFT) & FLASH_WRP2BR_WRP2B_END_MASK) +#endif + +/* Flash Securable Area Bank 1 Register (SEC1R) */ + +#if defined(CONFIG_STM32_STM32G4XXX) +# define FLASH_SEC1R_SEC_SIZE1_SHIFT (0) +# define FLASH_SEC1R_SEC_SIZE1_MASK (0xff << FLASH_SEC1R_SEC_SIZE1_SHIFT) +# define FLASH_SEC1R_SEC_SIZE1(n) (((n) << FLASH_SEC1R_SEC_SIZE1_SHIFT) & FLASH_SEC1R_SEC_SIZE1_MASK) +# define FLASH_SEC1R_BOOT_LOCK (1 << 16) +#endif + +/* Flash Securable Area Bank 2 Register (SEC2R) */ + +#if defined(CONFIG_STM32_STM32G4XXX) +# define FLASH_SEC2R_SEC_SIZE2_SHIFT (0) +# define FLASH_SEC2R_SEC_SIZE2_MASK (0xff << FLASH_SEC2R_SEC_SIZE2_SHIFT) +# define FLASH_SEC2R_SEC_SIZE2(n) (((n) << FLASH_SEC2R_SEC_SIZE2_SHIFT) & FLASH_SEC2R_SEC_SIZE2_MASK) +#endif + +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ + +int stm32_flash_lock(void); +int stm32_flash_unlock(void); + +#if defined(CONFIG_STM32_HAVE_IP_FLASH_M3M4_F2F4) +int stm32_flash_writeprotect(size_t page, bool enabled); +#endif + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_FLASH_V1V2_H */ diff --git a/arch/arm/src/common/stm32/hardware/stm32_fmc.h b/arch/arm/src/common/stm32/hardware/stm32_fmc.h new file mode 100644 index 0000000000000..4b72c82856ed3 --- /dev/null +++ b/arch/arm/src/common/stm32/hardware/stm32_fmc.h @@ -0,0 +1,392 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/hardware/stm32_fmc.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_FMC_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_FMC_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "chip.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Register Offsets *********************************************************/ + +#define STM32_FMC_BCR_OFFSET(n) (8 * ((n) - 1)) +#define STM32_FMC_BCR1_OFFSET 0x0000 /* SRAM/NOR-Flash chip-select control registers 1 */ +#define STM32_FMC_BCR2_OFFSET 0x0008 /* SRAM/NOR-Flash chip-select control registers 2 */ +#define STM32_FMC_BCR3_OFFSET 0x0010 /* SRAM/NOR-Flash chip-select control registers 3 */ +#define STM32_FMC_BCR4_OFFSET 0x0018 /* SRAM/NOR-Flash chip-select control registers 4 */ + +#define STM32_FMC_BTR_OFFSET(n) (8 * ((n) - 1) + 0x0004) +#define STM32_FMC_BTR1_OFFSET 0x0004 /* SRAM/NOR-Flash chip-select timing registers 1 */ +#define STM32_FMC_BTR2_OFFSET 0x000c /* SRAM/NOR-Flash chip-select timing registers 2 */ +#define STM32_FMC_BTR3_OFFSET 0x0014 /* SRAM/NOR-Flash chip-select timing registers 3 */ +#define STM32_FMC_BTR4_OFFSET 0x001c /* SRAM/NOR-Flash chip-select timing registers 4 */ + +#define STM32_FMC_BWTR_OFFSET(n) (8 * ((n) - 1) + 0x0104) +#define STM32_FMC_BWTR1_OFFSET 0x0104 /* SRAM/NOR-Flash write timing registers 1 */ +#define STM32_FMC_BWTR2_OFFSET 0x010c /* SRAM/NOR-Flash write timing registers 2 */ +#define STM32_FMC_BWTR3_OFFSET 0x0114 /* SRAM/NOR-Flash write timing registers 3 */ +#define STM32_FMC_BWTR4_OFFSET 0x011c /* SRAM/NOR-Flash write timing registers 4 */ + +#define STM32_FMC_PCR_OFFSET(n) (0x0020 * ((n) - 1) + 0x0040) +#define STM32_FMC_PCR2_OFFSET 0x0060 /* NAND Flash/PC Card controller register 2 */ +#define STM32_FMC_PCR3_OFFSET 0x0080 /* NAND Flash/PC Card controller register 3 */ +#define STM32_FMC_PCR4_OFFSET 0x00a0 /* NAND Flash/PC Card controller register 4 */ + +#define STM32_FMC_SR_OFFSET(n) (0x0020 * ((n) - 1) + 0x0044) +#define STM32_FMC_SR2_OFFSET 0x0064 /* NAND Flash/PC Card controller register 2 */ +#define STM32_FMC_SR3_OFFSET 0x0084 /* NAND Flash/PC Card controller register 3 */ +#define STM32_FMC_SR4_OFFSET 0x00a4 /* NAND Flash/PC Card controller register 4 */ + +#define STM32_FMC_PMEM_OFFSET(n) (0x0020 * ((n) - 1) + 0x0048) +#define STM32_FMC_PMEM2_OFFSET 0x0068 /* Common memory space timing register 2 */ +#define STM32_FMC_PMEM3_OFFSET 0x0088 /* Common memory space timing register 3 */ +#define STM32_FMC_PMEM4_OFFSET 0x00a8 /* Common memory space timing register 4 */ + +#define STM32_FMC_PATT_OFFSET(n) (0x0020 * ((n) - 1) + 0x004c) +#define STM32_FMC_PATT2_OFFSET 0x006c /* Attribute memory space timing register 2 */ +#define STM32_FMC_PATT3_OFFSET 0x008c /* Attribute memory space timing register 3 */ +#define STM32_FMC_PATT4_OFFSET 0x00ac /* Attribute memory space timing register 4 */ + +#define STM32_FMC_PIO4_OFFSET 0x00b0 /* I/O space timing register 4 */ + +#define STM32_FMC_ECCR_OFFSET(n) (0x0020 * ((n) - 1) + 0x0054) +#define STM32_FMC_ECCR2_OFFSET 0x0074 /* ECC result register 2 */ +#define STM32_FMC_ECCR3_OFFSET 0x0094 /* ECC result register 3 */ + +#define STM32_FMC_SDCR1_OFFSET 0x0140 /* SDRAM Control Register, Bank 1 */ +#define STM32_FMC_SDCR2_OFFSET 0x0144 /* SDRAM Control Register, Bank 2 */ + +#define STM32_FMC_SDTR1_OFFSET 0x0148 /* SDRAM Timing Register, Bank 1 */ +#define STM32_FMC_SDTR2_OFFSET 0x014c /* SDRAM Timing Register, Bank 2 */ + +#define STM32_FMC_SDCMR_OFFSET 0x0150 /* SDRAM Config Memory register */ +#define STM32_FMC_SDRTR_OFFSET 0x0154 /* SDRAM Refresh Timing Register maybe */ +#define STM32_FMC_SDSR_OFFSET 0x0158 /* SDRAM Status Register */ + +/* Register Addresses *******************************************************/ + +#define STM32_FMC_BCR(n) (STM32_FMC_BASE + STM32_FMC_BCR_OFFSET(n)) +#define STM32_FMC_BCR1 (STM32_FMC_BASE + STM32_FMC_BCR1_OFFSET) +#define STM32_FMC_BCR2 (STM32_FMC_BASE + STM32_FMC_BCR2_OFFSET) +#define STM32_FMC_BCR3 (STM32_FMC_BASE + STM32_FMC_BCR3_OFFSET) +#define STM32_FMC_BCR4 (STM32_FMC_BASE + STM32_FMC_BCR4_OFFSET) + +#define STM32_FMC_BTR(n) (STM32_FMC_BASE + STM32_FMC_BTR_OFFSET(n)) +#define STM32_FMC_BTR1 (STM32_FMC_BASE + STM32_FMC_BTR1_OFFSET) +#define STM32_FMC_BTR2 (STM32_FMC_BASE + STM32_FMC_BTR2_OFFSET) +#define STM32_FMC_BTR3 (STM32_FMC_BASE + STM32_FMC_BTR3_OFFSET) +#define STM32_FMC_BTR4 (STM32_FMC_BASE + STM32_FMC_BTR4_OFFSET) + +#define STM32_FMC_BWTR(n) (STM32_FMC_BASE + STM32_FMC_BWTR_OFFSET(n)) +#define STM32_FMC_BWTR1 (STM32_FMC_BASE + STM32_FMC_BWTR1_OFFSET) +#define STM32_FMC_BWTR2 (STM32_FMC_BASE + STM32_FMC_BWTR2_OFFSET) +#define STM32_FMC_BWTR3 (STM32_FMC_BASE + STM32_FMC_BWTR3_OFFSET) +#define STM32_FMC_BWTR4 (STM32_FMC_BASE + STM32_FMC_BWTR4_OFFSET) + +#define STM32_FMC_PCR(n) (STM32_FMC_BASE + STM32_FMC_PCR_OFFSET(n)) +#define STM32_FMC_PCR2 (STM32_FMC_BASE + STM32_FMC_PCR2_OFFSET) +#define STM32_FMC_PCR3 (STM32_FMC_BASE + STM32_FMC_PCR3_OFFSET) +#define STM32_FMC_PCR4 (STM32_FMC_BASE + STM32_FMC_PCR4_OFFSET) + +#define STM32_FMC_SR(n) (STM32_FMC_BASE + STM32_FMC_SR_OFFSET(n)) +#define STM32_FMC_SR2 (STM32_FMC_BASE + STM32_FMC_SR2_OFFSET) +#define STM32_FMC_SR3 (STM32_FMC_BASE + STM32_FMC_SR3_OFFSET) +#define STM32_FMC_SR4 (STM32_FMC_BASE + STM32_FMC_SR4_OFFSET) + +#define STM32_FMC_PMEM(n) (STM32_FMC_BASE + STM32_FMC_PMEM_OFFSET(n)) +#define STM32_FMC_PMEM2 (STM32_FMC_BASE + STM32_FMC_PMEM2_OFFSET) +#define STM32_FMC_PMEM3 (STM32_FMC_BASE + STM32_FMC_PMEM3_OFFSET) +#define STM32_FMC_PMEM4 (STM32_FMC_BASE + STM32_FMC_PMEM4_OFFSET) + +#define STM32_FMC_PATT(n) (STM32_FMC_BASE + STM32_FMC_PATT_OFFSET(n)) +#define STM32_FMC_PATT2 (STM32_FMC_BASE + STM32_FMC_PATT2_OFFSET) +#define STM32_FMC_PATT3 (STM32_FMC_BASE + STM32_FMC_PATT3_OFFSET) +#define STM32_FMC_PATT4 (STM32_FMC_BASE + STM32_FMC_PATT4_OFFSET) + +#define STM32_FMC_PIO4 (STM32_FMC_BASE + STM32_FMC_PIO4_OFFSET) + +#define STM32_FMC_ECCR(n) (STM32_FMC_BASE + STM32_FMC_ECCR_OFFSET(n)) +#define STM32_FMC_ECCR2 (STM32_FMC_BASE + STM32_FMC_ECCR2_OFFSET) +#define STM32_FMC_ECCR3 (STM32_FMC_BASE + STM32_FMC_ECCR3_OFFSET) + +#define STM32_FMC_SDCR1 (STM32_FMC_BASE + STM32_FMC_SDCR1_OFFSET) +#define STM32_FMC_SDCR2 (STM32_FMC_BASE + STM32_FMC_SDCR2_OFFSET) + +#define STM32_FMC_SDTR1 (STM32_FMC_BASE + STM32_FMC_SDTR1_OFFSET) +#define STM32_FMC_SDTR2 (STM32_FMC_BASE + STM32_FMC_SDTR2_OFFSET) + +#define STM32_FMC_SDCMR (STM32_FMC_BASE + STM32_FMC_SDCMR_OFFSET) +#define STM32_FMC_SDRTR (STM32_FMC_BASE + STM32_FMC_SDRTR_OFFSET) +#define STM32_FMC_SDSR (STM32_FMC_BASE + STM32_FMC_SDSR_OFFSET) + +/* Register Bitfield Definitions ********************************************/ + +#define FMC_BCR_MBKEN (1 << 0) /* Memory bank enable bit */ +#define FMC_BCR_MUXEN (1 << 1) /* Address/data multiplexing enable bit */ +#define FMC_BCR_MTYP_SHIFT (2) /* Memory type */ +#define FMC_BCR_MTYP_MASK (3 << FMC_BCR_MTYP_SHIFT) +# define FMC_BCR_SRAM (0 << FMC_BCR_MTYP_SHIFT) +# define FMC_BCR_ROM (0 << FMC_BCR_MTYP_SHIFT) +# define FMC_BCR_PSRAM (1 << FMC_BCR_MTYP_SHIFT) +# define FMC_BCR_CRAM (1 << FMC_BCR_MTYP_SHIFT) +# define FMC_BCR_NOR (2 << FMC_BCR_MTYP_SHIFT) +#define FMC_BCR_MWID_SHIFT (4) /* Memory data bus width */ +#define FMC_BCR_MWID_MASK (3 << FMC_BCR_MWID_SHIFT) +# define FMC_BCR_MWID8 (0 << FMC_BCR_MWID_SHIFT) +# define FMC_BCR_MWID16 (1 << FMC_BCR_MWID_SHIFT) +#define FMC_BCR_FACCEN (1 << 6) /* Flash access enable */ +#define FMC_BCR_BURSTEN (1 << 8) /* Burst enable bit */ +#define FMC_BCR_WAITPOL (1 << 9) /* Wait signal polarity bit */ +#define FMC_BCR_WRAPMOD (1 << 10) /* Wrapped burst mode support */ +#define FMC_BCR_WAITCFG (1 << 11) /* Wait timing configuration */ +#define FMC_BCR_WREN (1 << 12) /* Write enable bit */ +#define FMC_BCR_WAITEN (1 << 13) /* Wait enable bit */ +#define FMC_BCR_EXTMOD (1 << 14) /* Extended mode enable */ +#define FMC_BCR_ASYNCWAIT (1 << 15) /* Wait signal during asynchronous transfers */ +#define FMC_BCR_CBURSTRW (1 << 19) /* Write burst enable */ + +#define FMC_BCR_RSTVALUE 0x000003d2 + +#define FMC_BTR_ADDSET_SHIFT (0) /* Address setup phase duration */ +#define FMC_BTR_ADDSET_MASK (15 << FMC_BTR_ADDSET_SHIFT) +# define FMC_BTR_ADDSET(n) ((n-1) << FMC_BTR_ADDSET_SHIFT) /* (n)xHCLK n=1..16 */ + +#define FMC_BTR_ADDHLD_SHIFT (4) /* Address-hold phase duration */ +#define FMC_BTR_ADDHLD_MASK (15 << FMC_BTR_ADDHLD_SHIFT) +# define FMC_BTR_ADDHLD(n) ((n-1) << FMC_BTR_ADDHLD_SHIFT) /* (n)xHCLK n=2..16*/ + +#define FMC_BTR_DATAST_SHIFT (8) /* Data-phase duration */ +#define FMC_BTR_DATAST_MASK (255 << FMC_BTR_DATAST_SHIFT) +# define FMC_BTR_DATAST(n) ((n-1) << FMC_BTR_DATAST_SHIFT) /* (n)xHCLK n=2..256 */ + +#define FMC_BTR_BUSTURN_SHIFT (16) /* Bus turnaround phase duration */ +#define FMC_BTR_BUSTURN_MASK (15 << FMC_BTR1_BUSTURN_SHIFT) +# define FMC_BTR_BUSTURN(n) ((n-1) << FMC_BTR_BUSTURN_SHIFT) /* (n)xHCLK n=1..16 */ + +#define FMC_BTR_CLKDIV_SHIFT (20) /* Clock divide ratio */ +#define FMC_BTR_CLKDIV_MASK (15 << FMC_BTR_CLKDIV_SHIFT) +# define FMC_BTR_CLKDIV(n) ((n-1) << FMC_BTR_CLKDIV_SHIFT) /* (n)xHCLK n=2..16 */ + +#define FMC_BTR_DATLAT_SHIFT (24) /* Data latency */ +#define FMC_BTR_DATLAT_MASK (15 << FMC_BTR_DATLAT_SHIFT) +# define FMC_BTR_DATLAT(n) ((n-2) << FMC_BTR_DATLAT_SHIFT) /* (n)xHCLK n=2..17 */ + +#define FMC_BTR_ACCMOD_SHIFT (28) /* Access mode */ +#define FMC_BTR_ACCMOD_MASK (3 << FMC_BTR_ACCMOD_SHIFT) +# define FMC_BTR_ACCMODA (0 << FMC_BTR_ACCMOD_SHIFT) +# define FMC_BTR_ACCMODB (1 << FMC_BTR_ACCMOD_SHIFT) +# define FMC_BTR_ACCMODC (2 << FMC_BTR_ACCMOD_SHIFT) +# define FMC_BTR_ACCMODD (3 << FMC_BTR_ACCMOD_SHIFT) + +#define FMC_BTR_RSTVALUE 0xffffffff + +#define FMC_BWTR_ADDSET_SHIFT (0) /* Address setup phase duration */ +#define FMC_BWTR_ADDSET_MASK (15 << FMC_BWTR_ADDSET_SHIFT) +# define FMC_BWTR_ADDSET(n) ((n-1) << FMC_BWTR_ADDSET_SHIFT) /* (n)xHCLK n=1..16 */ + +#define FMC_BWTR_ADDHLD_SHIFT (4) /* Address-hold phase duration */ +#define FMC_BWTR_ADDHLD_MASK (15 << FMC_BWTR_ADDHLD_SHIFT) +# define FMC_BWTR_ADDHLD(n) ((n-1) << FMC_BWTR_ADDHLD_SHIFT) /* (n)xHCLK n=2..16*/ + +#define FMC_BWTR_DATAST_SHIFT (8) /* Data-phase duration */ +#define FMC_BWTR_DATAST_MASK (255 << FMC_BWTR_DATAST_SHIFT) +# define FMC_BWTR_DATAST(n) ((n-1) << FMC_BWTR_DATAST_SHIFT) /* (n)xHCLK n=2..256 */ + +#define FMC_BWTR_CLKDIV_SHIFT (20) /* Clock divide ratio */ +#define FMC_BWTR_CLKDIV_MASK (15 << FMC_BWTR_CLKDIV_SHIFT) +# define FMC_BWTR_CLKDIV(n) ((n-1) << FMC_BWTR_CLKDIV_SHIFT) /* (n)xHCLK n=2..16 */ + +#define FMC_BWTR_DATLAT_SHIFT (24) /* Data latency */ +#define FMC_BWTR_DATLAT_MASK (15 << FMC_BWTR_DATLAT_SHIFT) +# define FMC_BWTR_DATLAT(n) ((n-2) << FMC_BWTR_DATLAT_SHIFT) /* (n)xHCLK n=2..17 */ + +#define FMC_BWTR_ACCMOD_SHIFT (28) /* Access mode */ +#define FMC_BWTR_ACCMOD_MASK (3 << FMC_BWTR_ACCMOD_SHIFT) +# define FMC_BWTR_ACCMODA (0 << FMC_BWTR_ACCMOD_SHIFT) +# define FMC_BWTR_ACCMODB (1 << FMC_BWTR_ACCMOD_SHIFT) +# define FMC_BWTR_ACCMODC (2 << FMC_BWTR_ACCMOD_SHIFT) +# define FMC_BWTR_ACCMODD (3 << FMC_BTR_ACCMOD_SHIFT) + +#define FMC_PCR_PWAITEN (1 << 1) /* Wait feature enable bit */ +#define FMC_PCR_PBKEN (1 << 2) /* PC Card/NAND Flash memory bank enable bit */ +#define FMC_PCR_PTYP (1 << 3) /* Memory type */ +#define FMC_PCR_PWID_SHIFT (4) /* NAND Flash databus width */ +#define FMC_PCR_PWID_MASK (3 << FMC_PCR_PWID_SHIFT) +# define FMC_PCR_PWID8 (0 << FMC_PCR_PWID_SHIFT) +# define FMC_PCR_PWID16 (1 << FMC_PCR_PWID_SHIFT) +#define FMC_PCR_ECCEN (1 << 6) /* ECC computation logic enable bit */ +#define FMC_PCR_TCLR_SHIFT (9) /* CLE to RE delay */ +#define FMC_PCR_TCLR_MASK (15 << FMC_PCR_TCLR_SHIFT) +# define FMC_PCR_TCLR(n) ((n-1) << FMC_PCR_TCLR_SHIFT) /* (n)xHCLK n=1..16 */ + +#define FMC_PCR_TAR_SHIFT (13) /* ALE to RE delay */ +#define FMC_PCR_TAR_MASK (15 << FMC_PCR_TAR_MASK) +# define FMC_PCR_TAR(n) ((n-1) << FMC_PCR_TAR_SHIFT) /* (n)xHCLK n=1..16 */ + +#define FMC_PCR_ECCPS_SHIFT (17) /* ECC page size */ +#define FMC_PCR_ECCPS_MASK (7 << FMC_PCR_ECCPS_SHIFT) +# define FMC_PCR_ECCPS256 (0 << FMC_PCR_ECCPS_SHIFT) /* 256 bytes */ +# define FMC_PCR_ECCPS512 (1 << FMC_PCR_ECCPS_SHIFT) /* 512 bytes */ +# define FMC_PCR_ECCPS1024 (2 << FMC_PCR_ECCPS_SHIFT) /* 1024 bytes */ +# define FMC_PCR_ECCPS2048 (3 << FMC_PCR_ECCPS_SHIFT) /* 2048 bytes */ +# define FMC_PCR_ECCPS4096 (4 << FMC_PCR_ECCPS_SHIFT) /* 8192 bytes */ +# define FMC_PCR_ECCPS8192 (5 << FMC_PCR_ECCPS_SHIFT) /* 1024 bytes */ + +#define FMC_SR_IRS (1 << 0) /* Interrupt Rising Edge status */ +#define FMC_SR_ILS (1 << 1) /* Interrupt Level status */ +#define FMC_SR_IFS (1 << 2) /* Interrupt Falling Edge status */ +#define FMC_SR_IREN (1 << 3) /* Interrupt Rising Edge detection Enable bit */ +#define FMC_SR_ILEN (1 << 4) /* Interrupt Level detection Enable bit */ +#define FMC_SR_IFEN (1 << 5) /* Interrupt Falling Edge detection Enable bit */ +#define FMC_SR_FEMPT (1 << 6) /* FIFO empty */ + +#define FMC_PMEM_MEMSET_SHIFT (0) /* Common memory setup time */ +#define FMC_PMEM_MEMSET_MASK (255 << FMC_PMEM_MEMSET_SHIFT) +# define FMC_PMEM_MEMSET(n) ((n-1) << FMC_PMEM_MEMSET_SHIFT) /* (n)xHCLK n=1..256 */ + +#define FMC_PMEM_MEMWAIT_SHIFT (8) /* Common memory wait time */ +#define FMC_PMEM_MEMWAIT_MASK (255 << FMC_PMEM_MEMWAIT_SHIFT) +# define FMC_PMEM_MEMWAIT(n) ((n-1) << FMC_PMEM_MEMWAIT_SHIFT) /* (n)xHCLK n=2..256 */ + +#define FMC_PMEM_MEMHOLD_SHIFT (16) /* Common memoryhold time */ +#define FMC_PMEM_MEMHOLD_MASK (255 << FMC_PMEM_MEMHOLD_SHIFT) +# define FMC_PMEM_MEMHOLD(n) ((n) << FMC_PMEM_MEMHOLD_SHIFT) /* (n)xHCLK n=1..255 */ + +#define FMC_PMEM_MEMHIZ_SHIFT (24) /* Common memory databus HiZ time */ +#define FMC_PMEM_MEMHIZ_MASK (255 << FMC_PMEM_MEMHIZ_SHIFT) +# define FMC_PMEM_MEMHIZ(n) ((n) << FMC_PMEM_MEMHIZ_SHIFT) /* (n)xHCLK n=0..255 */ + +#define FMC_PATT_ATTSET_SHIFT (0) /* Attribute memory setup time */ +#define FMC_PATT_ATTSET_MASK (255 << FMC_PATT_ATTSET_SHIFT) +# define FMC_PATT_ATTSET(n) ((n-1) << FMC_PATT_ATTSET_SHIFT) /* (n)xHCLK n=1..256 */ + +#define FMC_PATT_ATTWAIT_SHIFT (8) /* Attribute memory wait time */ +#define FMC_PATT_ATTWAIT_MASK (255 << FMC_PATT_ATTWAIT_SHIFT) +# define FMC_PATT_ATTWAIT(n) ((n-1) << FMC_PATT_ATTWAIT_SHIFT) /* (n)xHCLK n=2..256 */ + +#define FMC_PATT_ATTHOLD_SHIFT (16) /* Attribute memory hold time */ +#define FMC_PATT_ATTHOLD_MASK (255 << FMC_PATT_ATTHOLD_SHIFT) +# define FMC_PATT_ATTHOLD(n) ((n) << FMC_PATT_ATTHOLD_SHIFT) /* (n)xHCLK n=1..255 */ + +#define FMC_PATT_ATTHIZ_SHIFT (24) /* Attribute memory databus HiZ time */ +#define FMC_PATT_ATTHIZ_MASK (255 << FMC_PATT_ATTHIZ_SHIFT) +# define FMC_PATT_ATTHIZ(n) ((n) << FMC_PATT_ATTHIZ_SHIFT) /* (n)xHCLK n=0..255 */ + +#define FMC_PIO4_IOSET_SHIFT (0) /* IO memory setup time */ +#define FMC_PIO4_IOSET_MASK (255 << FMC_PIO4_IOSET_SHIFT) +# define FMC_PIO4_IOSET(n) ((n-1) << FMC_PIO4_IOSET_SHIFT) /* (n)xHCLK n=1..256 */ + +#define FMC_PIO4_IOWAIT_SHIFT (8) /* IO memory wait time */ +#define FMC_PIO4_IOWAIT_MASK (255 << FMC_PIO4_IOWAIT_SHIFT) +# define FMC_PIO4_IOWAIT(n) ((n-1) << FMC_PIO4_IOWAIT_SHIFT) /* (n)xHCLK n=2..256 */ + +#define FMC_PIO4_IOHOLD_SHIFT (16) /* IO memory hold time */ +#define FMC_PIO4_IOHOLD_MASK (255 << FMC_PIO4_IOHOLD_SHIFT) +# define FMC_PIO4_IOHOLD(n) ((n) << FMC_PIO4_IOHOLD_SHIFT) /* (n)xHCLK n=1..255 */ + +#define FMC_PIO4_IOHIZ_SHIFT (24) /* IO memory databus HiZ time */ +#define FMC_PIO4_IOHIZ_MASK (255 << FMC_PIO4_IOHIZ_SHIFT) +# define FMC_PIO4_IOHIZ(n) ((n) << FMC_PIO4_IOHIZ_SHIFT) /* (n)xHCLK n=0..255 */ + +#define FMC_SDCR_RESERVED (0x1ffff << 15) /* reserved bits */ + +#define FMC_SDCR_RPIPE_0 (0 << 13) /* read pipe */ +#define FMC_SDCR_RPIPE_1 (1 << 13) +#define FMC_SDCR_RPIPE_2 (2 << 13) +#define FMC_SDCR_READBURST (1 << 12) /* read burst */ +#define FMC_SDCR_SDCLK_DISABLE (0 << 10) /* sdram clock */ +#define FMC_SDCR_SDCLK_2X (2 << 10) +#define FMC_SDCR_SDCLK_3X (3 << 10) +#define FMC_SDCR_WP (1 << 9) /* write protect */ +#define FMC_SDCR_CAS_LATENCY_1 (1 << 7) /* cas latency */ +#define FMC_SDCR_CAS_LATENCY_2 (2 << 7) +#define FMC_SDCR_CAS_LATENCY_3 (3 << 7) +#define FMC_SDCR_NBANKS_2 (0 << 6) /* number of internal banks */ +#define FMC_SDCR_NBANKS_4 (1 << 6) +#define FMC_SDCR_WIDTH_8 (0 << 4) /* memory width */ +#define FMC_SDCR_WIDTH_16 (1 << 4) +#define FMC_SDCR_WIDTH_32 (2 << 4) +#define FMC_SDCR_ROWS_11 (0 << 2) /* number of rows */ +#define FMC_SDCR_ROWS_12 (1 << 2) +#define FMC_SDCR_ROWS_13 (2 << 2) +#define FMC_SDCR_COLS_8 (0 << 0) /* number of columns */ +#define FMC_SDCR_COLS_9 (1 << 0) +#define FMC_SDCR_COLS_10 (2 << 0) +#define FMC_SDCR_COLS_11 (3 << 0) + +#define FMC_SDTR_RESERVED (15 << 28) /* reserved bits */ +#define FMC_SDTR_TMRD(n) (((n & 15) - 1) << 0) +#define FMC_SDTR_TXSR(n) (((n & 15) - 1) << 4) +#define FMC_SDTR_TRAS(n) (((n & 15) - 1) << 8) +#define FMC_SDTR_TRC(n) (((n & 15) - 1) << 12) +#define FMC_SDTR_TWR(n) (((n & 15) - 1) << 16) +#define FMC_SDTR_TRP(n) (((n & 15) - 1) << 20) +#define FMC_SDTR_TRCD(n) (((n & 15) - 1) << 24) + +/* Note: The FMC_SDCMR_MDR_x values can be found in the SDRAM datasheet. + * They should be standard, but it's probably a good idea to review + * the datasheet for your SDRAM device. + */ +#define FMC_SDCMR_RESERVED (0x3ff << 22) /* reserved bits */ +#define FMC_SDCMR_MDR_BURST_LENGTH_1 ((0 << 0) << 9) +#define FMC_SDCMR_MDR_BURST_LENGTH_2 ((1 << 0) << 9) +#define FMC_SDCMR_MDR_BURST_LENGTH_4 ((2 << 0) << 9) +#define FMC_SDCMR_MDR_BURST_LENGTH_8 ((3 << 0) << 9) +#define FMC_SDCMR_MDR_BURST_LENGTH_FULL ((7 << 0) << 9) +#define FMC_SDCMR_MDR_BURST_TYPE_SEQUENTIAL ((0 << 3) << 9) +#define FMC_SDCMR_MDR_BURST_TYPE_INTERLEAVE ((1 << 3) << 9) +#define FMC_SDCMR_MDR_CAS_LATENCY_1 ((1 << 4) << 9) +#define FMC_SDCMR_MDR_CAS_LATENCY_2 ((2 << 4) << 9) +#define FMC_SDCMR_MDR_CAS_LATENCY_3 ((3 << 4) << 9) +#define FMC_SDCMR_MDR_MODE_NORMAL ((0 << 7) << 9) +#define FMC_SDCMR_MDR_WBL_BURST ((0 << 9) << 9) +#define FMC_SDCMR_MDR_WBL_SINGLE ((1 << 9) << 9) +#define FMC_SDCMR_NRFS(n) (((n & 15) - 1) << 5) +#define FMC_SDCMR_BANK_1 (1 << 4) +#define FMC_SDCMR_BANK_2 (1 << 3) +#define FMC_SDCMR_CMD_NORMAL (0 << 0) +#define FMC_SDCMR_CMD_CLK_ENABLE (1 << 0) +#define FMC_SDCMR_CMD_PALL (2 << 0) +#define FMC_SDCMR_CMD_AUTO_REFRESH (3 << 0) +#define FMC_SDCMR_CMD_LOAD_MODE (4 << 0) +#define FMC_SDCMR_CMD_SELF_REFRESH (5 << 0) +#define FMC_SDCMR_CMD_POWER_DOWN (6 << 0) + +#define FMC_SDSR_RE (1 << 0) +#define FMC_SDSR_BUSY (1 << 5) +#define FMC_SDSR_MODES1_NORMAL (0 << 1) +#define FMC_SDSR_MODES1_SELF_REFRESH (1 << 1) +#define FMC_SDSR_MODES1_POWER_DOWN (2 << 1) +#define FMC_SDSR_MODES2_NORMAL (0 << 3) +#define FMC_SDSR_MODES2_SELF_REFRESH (1 << 3) +#define FMC_SDSR_MODES2_POWER_DOWN (2 << 3) + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_FMC_H */ diff --git a/arch/arm/src/common/stm32/hardware/stm32_fsmc.h b/arch/arm/src/common/stm32/hardware/stm32_fsmc.h new file mode 100644 index 0000000000000..703dbb1ab7f94 --- /dev/null +++ b/arch/arm/src/common/stm32/hardware/stm32_fsmc.h @@ -0,0 +1,301 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/hardware/stm32_fsmc.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_FSMC_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_FSMC_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "chip.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Register Offsets *********************************************************/ + +#define STM32_FSMC_BCR_OFFSET(n) (8 * ((n) - 1)) +#define STM32_FSMC_BCR1_OFFSET 0x0000 /* SRAM/NOR-Flash chip-select control registers 1 */ +#define STM32_FSMC_BCR2_OFFSET 0x0008 /* SRAM/NOR-Flash chip-select control registers 2 */ +#define STM32_FSMC_BCR3_OFFSET 0x0010 /* SRAM/NOR-Flash chip-select control registers 3 */ +#define STM32_FSMC_BCR4_OFFSET 0x0018 /* SRAM/NOR-Flash chip-select control registers 4 */ + +#define STM32_FSMC_BTR_OFFSET(n) (8 * ((n) - 1) + 0x0004) +#define STM32_FSMC_BTR1_OFFSET 0x0004 /* SRAM/NOR-Flash chip-select timing registers 1 */ +#define STM32_FSMC_BTR2_OFFSET 0x000c /* SRAM/NOR-Flash chip-select timing registers 2 */ +#define STM32_FSMC_BTR3_OFFSET 0x0014 /* SRAM/NOR-Flash chip-select timing registers 3 */ +#define STM32_FSMC_BTR4_OFFSET 0x001c /* SRAM/NOR-Flash chip-select timing registers 4 */ + +#define STM32_FSMC_BWTR_OFFSET(n) (8 * ((n) - 1) + 0x0104) +#define STM32_FSMC_BWTR1_OFFSET 0x0104 /* SRAM/NOR-Flash write timing registers 1 */ +#define STM32_FSMC_BWTR2_OFFSET 0x010c /* SRAM/NOR-Flash write timing registers 2 */ +#define STM32_FSMC_BWTR3_OFFSET 0x0114 /* SRAM/NOR-Flash write timing registers 3 */ +#define STM32_FSMC_BWTR4_OFFSET 0x011c /* SRAM/NOR-Flash write timing registers 4 */ + +#define STM32_FSMC_PCR_OFFSET(n) (0x0020 * ((n) - 1) + 0x0040) +#define STM32_FSMC_PCR2_OFFSET 0x0060 /* NAND Flash/PC Card controller register 2 */ +#define STM32_FSMC_PCR3_OFFSET 0x0080 /* NAND Flash/PC Card controller register 3 */ +#define STM32_FSMC_PCR4_OFFSET 0x00a0 /* NAND Flash/PC Card controller register 4 */ + +#define STM32_FSMC_SR_OFFSET(n) (0x0020 * ((n) - 1) + 0x0044) +#define STM32_FSMC_SR2_OFFSET 0x0064 /* NAND Flash/PC Card controller register 2 */ +#define STM32_FSMC_SR3_OFFSET 0x0084 /* NAND Flash/PC Card controller register 3 */ +#define STM32_FSMC_SR4_OFFSET 0x00a4 /* NAND Flash/PC Card controller register 4 */ + +#define STM32_FSMC_PMEM_OFFSET(n) (0x0020 * ((n) - 1) + 0x0048) +#define STM32_FSMC_PMEM2_OFFSET 0x0068 /* Common memory space timing register 2 */ +#define STM32_FSMC_PMEM3_OFFSET 0x0088 /* Common memory space timing register 3 */ +#define STM32_FSMC_PMEM4_OFFSET 0x00a8 /* Common memory space timing register 4 */ + +#define STM32_FSMC_PATT_OFFSET(n) (0x0020 * ((n) - 1) + 0x004c) +#define STM32_FSMC_PATT2_OFFSET 0x006c /* Attribute memory space timing register 2 */ +#define STM32_FSMC_PATT3_OFFSET 0x008c /* Attribute memory space timing register 3 */ +#define STM32_FSMC_PATT4_OFFSET 0x00ac /* Attribute memory space timing register 4 */ + +#define STM32_FSMC_PIO4_OFFSET 0x00b0 /* I/O space timing register 4 */ + +#define STM32_FSMC_ECCR_OFFSET(n) (0x0020 * ((n) - 1) + 0x0054) +#define STM32_FSMC_ECCR2_OFFSET 0x0074 /* ECC result register 2 */ +#define STM32_FSMC_ECCR3_OFFSET 0x0094 /* ECC result register 3 */ + +/* Register Addresses *******************************************************/ + +#define STM32_FSMC_BCR(n) (STM32_FSMC_BASE + STM32_FSMC_BCR_OFFSET(n)) +#define STM32_FSMC_BCR1 (STM32_FSMC_BASE + STM32_FSMC_BCR1_OFFSET) +#define STM32_FSMC_BCR2 (STM32_FSMC_BASE + STM32_FSMC_BCR2_OFFSET) +#define STM32_FSMC_BCR3 (STM32_FSMC_BASE + STM32_FSMC_BCR3_OFFSET) +#define STM32_FSMC_BCR4 (STM32_FSMC_BASE + STM32_FSMC_BCR4_OFFSET) + +#define STM32_FSMC_BTR(n) (STM32_FSMC_BASE + STM32_FSMC_BTR_OFFSET(n)) +#define STM32_FSMC_BTR1 (STM32_FSMC_BASE + STM32_FSMC_BTR1_OFFSET) +#define STM32_FSMC_BTR2 (STM32_FSMC_BASE + STM32_FSMC_BTR2_OFFSET) +#define STM32_FSMC_BTR3 (STM32_FSMC_BASE + STM32_FSMC_BTR3_OFFSET) +#define STM32_FSMC_BTR4 (STM32_FSMC_BASE + STM32_FSMC_BTR4_OFFSET) + +#define STM32_FSMC_BWTR(n) (STM32_FSMC_BASE + STM32_FSMC_BWTR_OFFSET(n)) +#define STM32_FSMC_BWTR1 (STM32_FSMC_BASE + STM32_FSMC_BWTR1_OFFSET) +#define STM32_FSMC_BWTR2 (STM32_FSMC_BASE + STM32_FSMC_BWTR2_OFFSET) +#define STM32_FSMC_BWTR3 (STM32_FSMC_BASE + STM32_FSMC_BWTR3_OFFSET) +#define STM32_FSMC_BWTR4 (STM32_FSMC_BASE + STM32_FSMC_BWTR4_OFFSET) + +#define STM32_FSMC_PCR(n) (STM32_FSMC_BASE + STM32_FSMC_PCR_OFFSET(n)) +#define STM32_FSMC_PCR2 (STM32_FSMC_BASE + STM32_FSMC_PCR2_OFFSET) +#define STM32_FSMC_PCR3 (STM32_FSMC_BASE + STM32_FSMC_PCR3_OFFSET) +#define STM32_FSMC_PCR4 (STM32_FSMC_BASE + STM32_FSMC_PCR4_OFFSET) + +#define STM32_FSMC_SR(n) (STM32_FSMC_BASE + STM32_FSMC_SR_OFFSET(n)) +#define STM32_FSMC_SR2 (STM32_FSMC_BASE + STM32_FSMC_SR2_OFFSET) +#define STM32_FSMC_SR3 (STM32_FSMC_BASE + STM32_FSMC_SR3_OFFSET) +#define STM32_FSMC_SR4 (STM32_FSMC_BASE + STM32_FSMC_SR4_OFFSET) + +#define STM32_FSMC_PMEM(n) (STM32_FSMC_BASE + STM32_FSMC_PMEM_OFFSET(n)) +#define STM32_FSMC_PMEM2 (STM32_FSMC_BASE + STM32_FSMC_PMEM2_OFFSET) +#define STM32_FSMC_PMEM3 (STM32_FSMC_BASE + STM32_FSMC_PMEM3_OFFSET) +#define STM32_FSMC_PMEM4 (STM32_FSMC_BASE + STM32_FSMC_PMEM4_OFFSET) + +#define STM32_FSMC_PATT(n) (STM32_FSMC_BASE + STM32_FSMC_PATT_OFFSET(n)) +#define STM32_FSMC_PATT2 (STM32_FSMC_BASE + STM32_FSMC_PATT2_OFFSET) +#define STM32_FSMC_PATT3 (STM32_FSMC_BASE + STM32_FSMC_PATT3_OFFSET) +#define STM32_FSMC_PATT4 (STM32_FSMC_BASE + STM32_FSMC_PATT4_OFFSET) + +#define STM32_FSMC_PIO4 (STM32_FSMC_BASE + STM32_FSMC_PIO4_OFFSET) + +#define STM32_FSMC_ECCR(n) (STM32_FSMC_BASE + STM32_FSMC_ECCR_OFFSET(n)) +#define STM32_FSMC_ECCR2 (STM32_FSMC_BASE + STM32_FSMC_ECCR2_OFFSET) +#define STM32_FSMC_ECCR3 (STM32_FSMC_BASE + STM32_FSMC_ECCR3_OFFSET) + +/* Register Bitfield Definitions ********************************************/ + +#define FSMC_BCR_MBKEN (1 << 0) /* Memory bank enable bit */ +#define FSMC_BCR_MUXEN (1 << 1) /* Address/data multiplexing enable bit */ +#define FSMC_BCR_MTYP_SHIFT (2) /* Memory type */ +#define FSMC_BCR_MTYP_MASK (3 << FSMC_BCR_MTYP_SHIFT) +# define FSMC_BCR_SRAM (0 << FSMC_BCR_MTYP_SHIFT) +# define FSMC_BCR_ROM (0 << FSMC_BCR_MTYP_SHIFT) +# define FSMC_BCR_PSRAM (1 << FSMC_BCR_MTYP_SHIFT) +# define FSMC_BCR_CRAM (1 << FSMC_BCR_MTYP_SHIFT) +# define FSMC_BCR_NOR (2 << FSMC_BCR_MTYP_SHIFT) +#define FSMC_BCR_MWID_SHIFT (4) /* Memory data bus width */ +#define FSMC_BCR_MWID_MASK (3 << FSMC_BCR_MWID_SHIFT) +# define FSMC_BCR_MWID8 (0 << FSMC_BCR_MWID_SHIFT) +# define FSMC_BCR_MWID16 (1 << FSMC_BCR_MWID_SHIFT) +#define FSMC_BCR_FACCEN (1 << 6) /* Flash access enable */ +#define FSMC_BCR_BURSTEN (1 << 8) /* Burst enable bit */ +#define FSMC_BCR_WAITPOL (1 << 9) /* Wait signal polarity bit */ +#define FSMC_BCR_WRAPMOD (1 << 10) /* Wrapped burst mode support */ +#define FSMC_BCR_WAITCFG (1 << 11) /* Wait timing configuration */ +#define FSMC_BCR_WREN (1 << 12) /* Write enable bit */ +#define FSMC_BCR_WAITEN (1 << 13) /* Wait enable bit */ +#define FSMC_BCR_EXTMOD (1 << 14) /* Extended mode enable */ +#if defined(CONFIG_STM32_HAVE_IP_FSMC_M3M4_V1) +# define FSMC_BCR_ASYNCWAIT (1 << 15) /* Wait signal during asynchronous transfers */ +#endif +#define FSMC_BCR_CBURSTRW (1 << 19) /* Write burst enable */ + +#define FSMC_BCR_RSTVALUE 0x000003d2 + +#define FSMC_BTR_ADDSET_SHIFT (0) /* Address setup phase duration */ +#define FSMC_BTR_ADDSET_MASK (15 << FSMC_BTR_ADDSET_SHIFT) +# define FSMC_BTR_ADDSET(n) ((n-1) << FSMC_BTR_ADDSET_SHIFT) /* (n)xHCLK n=1..16 */ + +#define FSMC_BTR_ADDHLD_SHIFT (4) /* Address-hold phase duration */ +#define FSMC_BTR_ADDHLD_MASK (15 << FSMC_BTR_ADDHLD_SHIFT) +# define FSMC_BTR_ADDHLD(n) ((n-1) << FSMC_BTR_ADDHLD_SHIFT) /* (n)xHCLK n=2..16*/ + +#define FSMC_BTR_DATAST_SHIFT (8) /* Data-phase duration */ +#define FSMC_BTR_DATAST_MASK (255 << FSMC_BTR_DATAST_SHIFT) +# define FSMC_BTR_DATAST(n) ((n-1) << FSMC_BTR_DATAST_SHIFT) /* (n)xHCLK n=2..256 */ + +#define FSMC_BTR_BUSTURN_SHIFT (16) /* Bus turnaround phase duration */ +#define FSMC_BTR_BUSTURN_MASK (15 << FSMC_BTR1_BUSTURN_SHIFT) +# define FSMC_BTR_BUSTURN(n) ((n-1) << FSMC_BTR_BUSTURN_SHIFT) /* (n)xHCLK n=1..16 */ + +#define FSMC_BTR_CLKDIV_SHIFT (20) /* Clock divide ratio */ +#define FSMC_BTR_CLKDIV_MASK (15 << FSMC_BTR_CLKDIV_SHIFT) +# define FSMC_BTR_CLKDIV(n) ((n-1) << FSMC_BTR_CLKDIV_SHIFT) /* (n)xHCLK n=2..16 */ + +#define FSMC_BTR_DATLAT_SHIFT (24) /* Data latency */ +#define FSMC_BTR_DATLAT_MASK (15 << FSMC_BTR_DATLAT_SHIFT) +# define FSMC_BTR_DATLAT(n) ((n-2) << FSMC_BTR_DATLAT_SHIFT) /* (n)xHCLK n=2..17 */ + +#define FSMC_BTR_ACCMOD_SHIFT (28) /* Access mode */ +#define FSMC_BTR_ACCMOD_MASK (3 << FSMC_BTR_ACCMOD_SHIFT) +# define FSMC_BTR_ACCMODA (0 << FSMC_BTR_ACCMOD_SHIFT) +# define FSMC_BTR_ACCMODB (1 << FSMC_BTR_ACCMOD_SHIFT) +# define FSMC_BTR_ACCMODC (2 << FSMC_BTR_ACCMOD_SHIFT) +# define FSMC_BTR_ACCMODD (3 << FSMC_BTR_ACCMOD_SHIFT) + +#define FSMC_BTR_RSTVALUE 0xffffffff + +#define FSMC_BWTR_ADDSET_SHIFT (0) /* Address setup phase duration */ +#define FSMC_BWTR_ADDSET_MASK (15 << FSMC_BWTR_ADDSET_SHIFT) +# define FSMC_BWTR_ADDSET(n) ((n-1) << FSMC_BWTR_ADDSET_SHIFT) /* (n)xHCLK n=1..16 */ + +#define FSMC_BWTR_ADDHLD_SHIFT (4) /* Address-hold phase duration */ +#define FSMC_BWTR_ADDHLD_MASK (15 << FSMC_BWTR_ADDHLD_SHIFT) +# define FSMC_BWTR_ADDHLD(n) ((n-1) << FSMC_BWTR_ADDHLD_SHIFT) /* (n)xHCLK n=2..16*/ + +#define FSMC_BWTR_DATAST_SHIFT (8) /* Data-phase duration */ +#define FSMC_BWTR_DATAST_MASK (255 << FSMC_BWTR_DATAST_SHIFT) +# define FSMC_BWTR_DATAST(n) ((n-1) << FSMC_BWTR_DATAST_SHIFT) /* (n)xHCLK n=2..256 */ + +#define FSMC_BWTR_CLKDIV_SHIFT (20) /* Clock divide ratio */ +#define FSMC_BWTR_CLKDIV_MASK (15 << FSMC_BWTR_CLKDIV_SHIFT) +# define FSMC_BWTR_CLKDIV(n) ((n-1) << FSMC_BWTR_CLKDIV_SHIFT) /* (n)xHCLK n=2..16 */ + +#define FSMC_BWTR_DATLAT_SHIFT (24) /* Data latency */ +#define FSMC_BWTR_DATLAT_MASK (15 << FSMC_BWTR_DATLAT_SHIFT) +# define FSMC_BWTR_DATLAT(n) ((n-2) << FSMC_BWTR_DATLAT_SHIFT) /* (n)xHCLK n=2..17 */ + +#define FSMC_BWTR_ACCMOD_SHIFT (28) /* Access mode */ +#define FSMC_BWTR_ACCMOD_MASK (3 << FSMC_BWTR_ACCMOD_SHIFT) +# define FSMC_BWTR_ACCMODA (0 << FSMC_BWTR_ACCMOD_SHIFT) +# define FSMC_BWTR_ACCMODB (1 << FSMC_BWTR_ACCMOD_SHIFT) +# define FSMC_BWTR_ACCMODC (2 << FSMC_BWTR_ACCMOD_SHIFT) +# define FSMC_BWTR_ACCMODD (3 << FSMC_BTR_ACCMOD_SHIFT) + +#define FSMC_PCR_PWAITEN (1 << 1) /* Wait feature enable bit */ +#define FSMC_PCR_PBKEN (1 << 2) /* PC Card/NAND Flash memory bank enable bit */ +#define FSMC_PCR_PTYP (1 << 3) /* Memory type */ +#define FSMC_PCR_PWID_SHIFT (4) /* NAND Flash databus width */ +#define FSMC_PCR_PWID_MASK (3 << FSMC_PCR_PWID_SHIFT) +# define FSMC_PCR_PWID8 (0 << FSMC_PCR_PWID_SHIFT) +# define FSMC_PCR_PWID16 (1 << FSMC_PCR_PWID_SHIFT) +#define FSMC_PCR_ECCEN (1 << 6) /* ECC computation logic enable bit */ +#define FSMC_PCR_TCLR_SHIFT (9) /* CLE to RE delay */ +#define FSMC_PCR_TCLR_MASK (15 << FSMC_PCR_TCLR_SHIFT) +# define FSMC_PCR_TCLR(n) ((n-1) << FSMC_PCR_TCLR_SHIFT) /* (n)xHCLK n=1..16 */ + +#define FSMC_PCR_TAR_SHIFT (13) /* ALE to RE delay */ +#define FSMC_PCR_TAR_MASK (15 << FSMC_PCR_TAR_MASK) +# define FSMC_PCR_TAR(n) ((n-1) << FSMC_PCR_TAR_SHIFT) /* (n)xHCLK n=1..16 */ + +#define FSMC_PCR_ECCPS_SHIFT (17) /* ECC page size */ +#define FSMC_PCR_ECCPS_MASK (7 << FSMC_PCR_ECCPS_SHIFT) +# define FSMC_PCR_ECCPS256 (0 << FSMC_PCR_ECCPS_SHIFT) /* 256 bytes */ +# define FSMC_PCR_ECCPS512 (1 << FSMC_PCR_ECCPS_SHIFT) /* 512 bytes */ +# define FSMC_PCR_ECCPS1024 (2 << FSMC_PCR_ECCPS_SHIFT) /* 1024 bytes */ +# define FSMC_PCR_ECCPS2048 (3 << FSMC_PCR_ECCPS_SHIFT) /* 2048 bytes */ +# define FSMC_PCR_ECCPS4096 (4 << FSMC_PCR_ECCPS_SHIFT) /* 8192 bytes */ +# define FSMC_PCR_ECCPS8192 (5 << FSMC_PCR_ECCPS_SHIFT) /* 1024 bytes */ + +#define FSMC_SR_IRS (1 << 0) /* Interrupt Rising Edge status */ +#define FSMC_SR_ILS (1 << 1) /* Interrupt Level status */ +#define FSMC_SR_IFS (1 << 2) /* Interrupt Falling Edge status */ +#define FSMC_SR_IREN (1 << 3) /* Interrupt Rising Edge detection Enable bit */ +#define FSMC_SR_ILEN (1 << 4) /* Interrupt Level detection Enable bit */ +#define FSMC_SR_IFEN (1 << 5) /* Interrupt Falling Edge detection Enable bit */ +#define FSMC_SR_FEMPT (1 << 6) /* FIFO empty */ + +#define FSMC_PMEM_MEMSET_SHIFT (0) /* Common memory setup time */ +#define FSMC_PMEM_MEMSET_MASK (255 << FSMC_PMEM_MEMSET_SHIFT) +# define FSMC_PMEM_MEMSET(n) ((n-1) << FSMC_PMEM_MEMSET_SHIFT) /* (n)xHCLK n=1..256 */ + +#define FSMC_PMEM_MEMWAIT_SHIFT (8) /* Common memory wait time */ +#define FSMC_PMEM_MEMWAIT_MASK (255 << FSMC_PMEM_MEMWAIT_SHIFT) +# define FSMC_PMEM_MEMWAIT(n) ((n-1) << FSMC_PMEM_MEMWAIT_SHIFT) /* (n)xHCLK n=2..256 */ + +#define FSMC_PMEM_MEMHOLD_SHIFT (16) /* Common memoryhold time */ +#define FSMC_PMEM_MEMHOLD_MASK (255 << FSMC_PMEM_MEMHOLD_SHIFT) +# define FSMC_PMEM_MEMHOLD(n) ((n) << FSMC_PMEM_MEMHOLD_SHIFT) /* (n)xHCLK n=1..255 */ + +#define FSMC_PMEM_MEMHIZ_SHIFT (24) /* Common memory databus HiZ time */ +#define FSMC_PMEM_MEMHIZ_MASK (255 << FSMC_PMEM_MEMHIZ_SHIFT) +# define FSMC_PMEM_MEMHIZ(n) ((n) << FSMC_PMEM_MEMHIZ_SHIFT) /* (n)xHCLK n=0..255 */ + +#define FSMC_PATT_ATTSET_SHIFT (0) /* Attribute memory setup time */ +#define FSMC_PATT_ATTSET_MASK (255 << FSMC_PATT_ATTSET_SHIFT) +# define FSMC_PATT_ATTSET(n) ((n-1) << FSMC_PATT_ATTSET_SHIFT) /* (n)xHCLK n=1..256 */ + +#define FSMC_PATT_ATTWAIT_SHIFT (8) /* Attribute memory wait time */ +#define FSMC_PATT_ATTWAIT_MASK (255 << FSMC_PATT_ATTWAIT_SHIFT) +# define FSMC_PATT_ATTWAIT(n) ((n-1) << FSMC_PATT_ATTWAIT_SHIFT) /* (n)xHCLK n=2..256 */ + +#define FSMC_PATT_ATTHOLD_SHIFT (16) /* Attribute memory hold time */ +#define FSMC_PATT_ATTHOLD_MASK (255 << FSMC_PATT_ATTHOLD_SHIFT) +# define FSMC_PATT_ATTHOLD(n) ((n) << FSMC_PATT_ATTHOLD_SHIFT) /* (n)xHCLK n=1..255 */ + +#define FSMC_PATT_ATTHIZ_SHIFT (24) /* Attribute memory databus HiZ time */ +#define FSMC_PATT_ATTHIZ_MASK (255 << FSMC_PATT_ATTHIZ_SHIFT) +# define FSMC_PATT_ATTHIZ(n) ((n) << FSMC_PATT_ATTHIZ_SHIFT) /* (n)xHCLK n=0..255 */ + +#define FSMC_PIO4_IOSET_SHIFT (0) /* IO memory setup time */ +#define FSMC_PIO4_IOSET_MASK (255 << FSMC_PIO4_IOSET_SHIFT) +# define FSMC_PIO4_IOSET(n) ((n-1) << FSMC_PIO4_IOSET_SHIFT) /* (n)xHCLK n=1..256 */ + +#define FSMC_PIO4_IOWAIT_SHIFT (8) /* IO memory wait time */ +#define FSMC_PIO4_IOWAIT_MASK (255 << FSMC_PIO4_IOWAIT_SHIFT) +# define FSMC_PIO4_IOWAIT(n) ((n-1) << FSMC_PIO4_IOWAIT_SHIFT) /* (n)xHCLK n=2..256 */ + +#define FSMC_PIO4_IOHOLD_SHIFT (16) /* IO memory hold time */ +#define FSMC_PIO4_IOHOLD_MASK (255 << FSMC_PIO4_IOHOLD_SHIFT) +# define FSMC_PIO4_IOHOLD(n) ((n) << FSMC_PIO4_IOHOLD_SHIFT) /* (n)xHCLK n=1..255 */ + +#define FSMC_PIO4_IOHIZ_SHIFT (24) /* IO memory databus HiZ time */ +#define FSMC_PIO4_IOHIZ_MASK (255 << FSMC_PIO4_IOHIZ_SHIFT) +# define FSMC_PIO4_IOHIZ(n) ((n) << FSMC_PIO4_IOHIZ_SHIFT) /* (n)xHCLK n=0..255 */ + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_FSMC_H */ diff --git a/arch/arm/src/common/stm32/hardware/stm32_gpio.h b/arch/arm/src/common/stm32/hardware/stm32_gpio.h new file mode 100644 index 0000000000000..ea028b5b22335 --- /dev/null +++ b/arch/arm/src/common/stm32/hardware/stm32_gpio.h @@ -0,0 +1,49 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/hardware/stm32_gpio.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_GPIO_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_GPIO_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#if defined(CONFIG_STM32_HAVE_IP_GPIO_M0_V1) +# include "hardware/stm32_gpio_v2_m0.h" +#elif defined(CONFIG_STM32_STM32L15XX) +# include "hardware/stm32l15xxx_gpio.h" +#elif defined(CONFIG_STM32_STM32F10XX) +# include "hardware/stm32f10xxx_gpio.h" +#elif defined(CONFIG_STM32_STM32F20XX) +# include "hardware/stm32f20xxx_gpio.h" +#elif defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) || \ + defined(CONFIG_STM32_STM32F37XX) +# include "hardware/stm32f30xxx_gpio.h" +#elif defined(CONFIG_STM32_STM32F4XXX) +# include "hardware/stm32f40xxx_gpio.h" +#elif defined(CONFIG_STM32_STM32G4XXX) +# include "hardware/stm32g4xxxx_gpio.h" +#else +# error "Unsupported STM32 GPIO" +#endif + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_GPIO_H */ diff --git a/arch/arm/src/common/stm32/hardware/stm32_gpio_v2_m0.h b/arch/arm/src/common/stm32/hardware/stm32_gpio_v2_m0.h new file mode 100644 index 0000000000000..94637dfc7a181 --- /dev/null +++ b/arch/arm/src/common/stm32/hardware/stm32_gpio_v2_m0.h @@ -0,0 +1,347 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/hardware/stm32_gpio_v2_m0.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_GPIO_V2_M0_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_GPIO_V2_M0_H + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#if defined(CONFIG_ARCH_CHIP_STM32F0) +# undef STM32_GPIO_VERY_LOW_SPEED /* No very low speed operation */ +#elif defined(CONFIG_ARCH_CHIP_STM32L0) +# define STM32_GPIO_VERY_LOW_SPEED 1 /* Have very low speed operation (400KHz) */ +#elif defined(CONFIG_ARCH_CHIP_STM32G0) +# define STM32_GPIO_VERY_LOW_SPEED 1 /* Have very low speed operation */ +#elif defined(CONFIG_ARCH_CHIP_STM32C0) +# define STM32_GPIO_VERY_LOW_SPEED 1 /* Have very low speed operation */ +#else +# error "Unsupported STM32 M0 family" +#endif + +/* Register Offsets *********************************************************/ + +#define STM32_GPIO_MODER_OFFSET 0x0000 /* GPIO port mode register */ +#define STM32_GPIO_OTYPER_OFFSET 0x0004 /* GPIO port output type register */ +#define STM32_GPIO_OSPEED_OFFSET 0x0008 /* GPIO port output speed register */ +#define STM32_GPIO_PUPDR_OFFSET 0x000c /* GPIO port pull-up/pull-down register */ +#define STM32_GPIO_IDR_OFFSET 0x0010 /* GPIO port input data register */ +#define STM32_GPIO_ODR_OFFSET 0x0014 /* GPIO port output data register */ +#define STM32_GPIO_BSRR_OFFSET 0x0018 /* GPIO port bit set/reset register */ +#define STM32_GPIO_LCKR_OFFSET 0x001c /* GPIO port configuration lock register */ +#define STM32_GPIO_AFRL_OFFSET 0x0020 /* GPIO alternate function low register */ +#define STM32_GPIO_AFRH_OFFSET 0x0024 /* GPIO alternate function high register */ +#define STM32_GPIO_BRR_OFFSET 0x0028 /* GPIO port bit reset register */ + +/* Register Addresses *******************************************************/ + +#if STM32_NPORTS > 0 +# define STM32_GPIOA_MODER (STM32_GPIOA_BASE+STM32_GPIO_MODER_OFFSET) +# define STM32_GPIOA_OTYPER (STM32_GPIOA_BASE+STM32_GPIO_OTYPER_OFFSET) +# define STM32_GPIOA_OSPEED (STM32_GPIOA_BASE+STM32_GPIO_OSPEED_OFFSET) +# define STM32_GPIOA_PUPDR (STM32_GPIOA_BASE+STM32_GPIO_PUPDR_OFFSET) +# define STM32_GPIOA_IDR (STM32_GPIOA_BASE+STM32_GPIO_IDR_OFFSET) +# define STM32_GPIOA_ODR (STM32_GPIOA_BASE+STM32_GPIO_ODR_OFFSET) +# define STM32_GPIOA_BSRR (STM32_GPIOA_BASE+STM32_GPIO_BSRR_OFFSET) +# define STM32_GPIOA_LCKR (STM32_GPIOA_BASE+STM32_GPIO_LCKR_OFFSET) +# define STM32_GPIOA_AFRL (STM32_GPIOA_BASE+STM32_GPIO_AFRL_OFFSET) +# define STM32_GPIOA_AFRH (STM32_GPIOA_BASE+STM32_GPIO_AFRH_OFFSET) +#endif + +#if STM32_NPORTS > 1 +# define STM32_GPIOB_MODER (STM32_GPIOB_BASE+STM32_GPIO_MODER_OFFSET) +# define STM32_GPIOB_OTYPER (STM32_GPIOB_BASE+STM32_GPIO_OTYPER_OFFSET) +# define STM32_GPIOB_OSPEED (STM32_GPIOB_BASE+STM32_GPIO_OSPEED_OFFSET) +# define STM32_GPIOB_PUPDR (STM32_GPIOB_BASE+STM32_GPIO_PUPDR_OFFSET) +# define STM32_GPIOB_IDR (STM32_GPIOB_BASE+STM32_GPIO_IDR_OFFSET) +# define STM32_GPIOB_ODR (STM32_GPIOB_BASE+STM32_GPIO_ODR_OFFSET) +# define STM32_GPIOB_BSRR (STM32_GPIOB_BASE+STM32_GPIO_BSRR_OFFSET) +# define STM32_GPIOB_LCKR (STM32_GPIOB_BASE+STM32_GPIO_LCKR_OFFSET) +# define STM32_GPIOB_AFRL (STM32_GPIOB_BASE+STM32_GPIO_AFRL_OFFSET) +# define STM32_GPIOB_AFRH (STM32_GPIOB_BASE+STM32_GPIO_AFRH_OFFSET) +#endif + +#if STM32_NPORTS > 2 +# define STM32_GPIOC_MODER (STM32_GPIOC_BASE+STM32_GPIO_MODER_OFFSET) +# define STM32_GPIOC_OTYPER (STM32_GPIOC_BASE+STM32_GPIO_OTYPER_OFFSET) +# define STM32_GPIOC_OSPEED (STM32_GPIOC_BASE+STM32_GPIO_OSPEED_OFFSET) +# define STM32_GPIOC_PUPDR (STM32_GPIOC_BASE+STM32_GPIO_PUPDR_OFFSET) +# define STM32_GPIOC_IDR (STM32_GPIOC_BASE+STM32_GPIO_IDR_OFFSET) +# define STM32_GPIOC_ODR (STM32_GPIOC_BASE+STM32_GPIO_ODR_OFFSET) +# define STM32_GPIOC_BSRR (STM32_GPIOC_BASE+STM32_GPIO_BSRR_OFFSET) +# define STM32_GPIOC_LCKR (STM32_GPIOC_BASE+STM32_GPIO_LCKR_OFFSET) +# define STM32_GPIOC_AFRL (STM32_GPIOC_BASE+STM32_GPIO_AFRL_OFFSET) +# define STM32_GPIOC_AFRH (STM32_GPIOC_BASE+STM32_GPIO_AFRH_OFFSET) +#endif + +#if STM32_NPORTS > 3 +# define STM32_GPIOD_MODER (STM32_GPIOD_BASE+STM32_GPIO_MODER_OFFSET) +# define STM32_GPIOD_OTYPER (STM32_GPIOD_BASE+STM32_GPIO_OTYPER_OFFSET) +# define STM32_GPIOD_OSPEED (STM32_GPIOD_BASE+STM32_GPIO_OSPEED_OFFSET) +# define STM32_GPIOD_PUPDR (STM32_GPIOD_BASE+STM32_GPIO_PUPDR_OFFSET) +# define STM32_GPIOD_IDR (STM32_GPIOD_BASE+STM32_GPIO_IDR_OFFSET) +# define STM32_GPIOD_ODR (STM32_GPIOD_BASE+STM32_GPIO_ODR_OFFSET) +# define STM32_GPIOD_BSRR (STM32_GPIOD_BASE+STM32_GPIO_BSRR_OFFSET) +# define STM32_GPIOD_LCKR (STM32_GPIOD_BASE+STM32_GPIO_LCKR_OFFSET) +# define STM32_GPIOD_AFRL (STM32_GPIOD_BASE+STM32_GPIO_AFRL_OFFSET) +# define STM32_GPIOD_AFRH (STM32_GPIOD_BASE+STM32_GPIO_AFRH_OFFSET) +#endif + +#if STM32_NPORTS > 4 +# define STM32_GPIOE_MODER (STM32_GPIOE_BASE+STM32_GPIO_MODER_OFFSET) +# define STM32_GPIOE_OTYPER (STM32_GPIOE_BASE+STM32_GPIO_OTYPER_OFFSET) +# define STM32_GPIOE_OSPEED (STM32_GPIOE_BASE+STM32_GPIO_OSPEED_OFFSET) +# define STM32_GPIOE_PUPDR (STM32_GPIOE_BASE+STM32_GPIO_PUPDR_OFFSET) +# define STM32_GPIOE_IDR (STM32_GPIOE_BASE+STM32_GPIO_IDR_OFFSET) +# define STM32_GPIOE_ODR (STM32_GPIOE_BASE+STM32_GPIO_ODR_OFFSET) +# define STM32_GPIOE_BSRR (STM32_GPIOE_BASE+STM32_GPIO_BSRR_OFFSET) +# define STM32_GPIOE_LCKR (STM32_GPIOE_BASE+STM32_GPIO_LCKR_OFFSET) +# define STM32_GPIOE_AFRL (STM32_GPIOE_BASE+STM32_GPIO_AFRL_OFFSET) +# define STM32_GPIOE_AFRH (STM32_GPIOE_BASE+STM32_GPIO_AFRH_OFFSET) +#endif + +#if STM32_NPORTS > 5 +# define STM32_GPIOH_MODER (STM32_GPIOH_BASE+STM32_GPIO_MODER_OFFSET) +# define STM32_GPIOH_OTYPER (STM32_GPIOH_BASE+STM32_GPIO_OTYPER_OFFSET) +# define STM32_GPIOH_OSPEED (STM32_GPIOH_BASE+STM32_GPIO_OSPEED_OFFSET) +# define STM32_GPIOH_PUPDR (STM32_GPIOH_BASE+STM32_GPIO_PUPDR_OFFSET) +# define STM32_GPIOH_IDR (STM32_GPIOH_BASE+STM32_GPIO_IDR_OFFSET) +# define STM32_GPIOH_ODR (STM32_GPIOH_BASE+STM32_GPIO_ODR_OFFSET) +# define STM32_GPIOH_BSRR (STM32_GPIOH_BASE+STM32_GPIO_BSRR_OFFSET) +# define STM32_GPIOH_LCKR (STM32_GPIOH_BASE+STM32_GPIO_LCKR_OFFSET) +# define STM32_GPIOH_AFRL (STM32_GPIOH_BASE+STM32_GPIO_AFRL_OFFSET) +# define STM32_GPIOH_AFRH (STM32_GPIOH_BASE+STM32_GPIO_AFRH_OFFSET) +#endif + +#if STM32_NPORTS > 6 +# define STM32_GPIOF_MODER (STM32_GPIOF_BASE+STM32_GPIO_MODER_OFFSET) +# define STM32_GPIOF_OTYPER (STM32_GPIOF_BASE+STM32_GPIO_OTYPER_OFFSET) +# define STM32_GPIOF_OSPEED (STM32_GPIOF_BASE+STM32_GPIO_OSPEED_OFFSET) +# define STM32_GPIOF_PUPDR (STM32_GPIOF_BASE+STM32_GPIO_PUPDR_OFFSET) +# define STM32_GPIOF_IDR (STM32_GPIOF_BASE+STM32_GPIO_IDR_OFFSET) +# define STM32_GPIOF_ODR (STM32_GPIOF_BASE+STM32_GPIO_ODR_OFFSET) +# define STM32_GPIOF_BSRR (STM32_GPIOF_BASE+STM32_GPIO_BSRR_OFFSET) +# define STM32_GPIOF_LCKR (STM32_GPIOF_BASE+STM32_GPIO_LCKR_OFFSET) +# define STM32_GPIOF_AFRL (STM32_GPIOF_BASE+STM32_GPIO_AFRL_OFFSET) +# define STM32_GPIOF_AFRH (STM32_GPIOF_BASE+STM32_GPIO_AFRH_OFFSET) +#endif + +#if STM32_NPORTS > 7 +# define STM32_GPIOG_MODER (STM32_GPIOG_BASE+STM32_GPIO_MODER_OFFSET) +# define STM32_GPIOG_OTYPER (STM32_GPIOG_BASE+STM32_GPIO_OTYPER_OFFSET) +# define STM32_GPIOG_OSPEED (STM32_GPIOG_BASE+STM32_GPIO_OSPEED_OFFSET) +# define STM32_GPIOG_PUPDR (STM32_GPIOG_BASE+STM32_GPIO_PUPDR_OFFSET) +# define STM32_GPIOG_IDR (STM32_GPIOG_BASE+STM32_GPIO_IDR_OFFSET) +# define STM32_GPIOG_ODR (STM32_GPIOG_BASE+STM32_GPIO_ODR_OFFSET) +# define STM32_GPIOG_BSRR (STM32_GPIOG_BASE+STM32_GPIO_BSRR_OFFSET) +# define STM32_GPIOG_LCKR (STM32_GPIOG_BASE+STM32_GPIO_LCKR_OFFSET) +# define STM32_GPIOG_AFRL (STM32_GPIOG_BASE+STM32_GPIO_AFRL_OFFSET) +# define STM32_GPIOG_AFRH (STM32_GPIOG_BASE+STM32_GPIO_AFRH_OFFSET) +#endif + +/* Register Bitfield Definitions ********************************************/ + +/* GPIO port mode register */ + +#define GPIO_MODER_INPUT (0) /* Input */ +#define GPIO_MODER_OUTPUT (1) /* General purpose output mode */ +#define GPIO_MODER_ALT (2) /* Alternate mode */ +#define GPIO_MODER_ANALOG (3) /* Analog mode */ + +#define GPIO_MODER_SHIFT(n) ((n) << 1) +#define GPIO_MODER_MASK(n) (3 << GPIO_MODER_SHIFT(n)) + +#define GPIO_MODER0_SHIFT (0) +#define GPIO_MODER0_MASK (3 << GPIO_MODER0_SHIFT) +#define GPIO_MODER1_SHIFT (2) +#define GPIO_MODER1_MASK (3 << GPIO_MODER1_SHIFT) +#define GPIO_MODER2_SHIFT (4) +#define GPIO_MODER2_MASK (3 << GPIO_MODER2_SHIFT) +#define GPIO_MODER3_SHIFT (6) +#define GPIO_MODER3_MASK (3 << GPIO_MODER3_SHIFT) +#define GPIO_MODER4_SHIFT (8) +#define GPIO_MODER4_MASK (3 << GPIO_MODER4_SHIFT) +#define GPIO_MODER5_SHIFT (10) +#define GPIO_MODER5_MASK (3 << GPIO_MODER5_SHIFT) +#define GPIO_MODER6_SHIFT (12) +#define GPIO_MODER6_MASK (3 << GPIO_MODER6_SHIFT) +#define GPIO_MODER7_SHIFT (14) +#define GPIO_MODER7_MASK (3 << GPIO_MODER7_SHIFT) +#define GPIO_MODER8_SHIFT (16) +#define GPIO_MODER8_MASK (3 << GPIO_MODER8_SHIFT) +#define GPIO_MODER9_SHIFT (18) +#define GPIO_MODER9_MASK (3 << GPIO_MODER9_SHIFT) +#define GPIO_MODER10_SHIFT (20) +#define GPIO_MODER10_MASK (3 << GPIO_MODER10_SHIFT) +#define GPIO_MODER11_SHIFT (22) +#define GPIO_MODER11_MASK (3 << GPIO_MODER11_SHIFT) +#define GPIO_MODER12_SHIFT (24) +#define GPIO_MODER12_MASK (3 << GPIO_MODER12_SHIFT) +#define GPIO_MODER13_SHIFT (26) +#define GPIO_MODER13_MASK (3 << GPIO_MODER13_SHIFT) +#define GPIO_MODER14_SHIFT (28) +#define GPIO_MODER14_MASK (3 << GPIO_MODER14_SHIFT) +#define GPIO_MODER15_SHIFT (30) +#define GPIO_MODER15_MASK (3 << GPIO_MODER15_SHIFT) + +/* GPIO port output type register */ + +#define GPIO_OTYPER_OD(n) (1 << (n)) /* 1=Output open-drain */ +#define GPIO_OTYPER_PP(n) (0) /* 0=Output push-pull */ + +/* GPIO port output speed register */ + +#if defined(STM32_GPIO_VERY_LOW_SPEED) +# define GPIO_OSPEED_VERYLOW (0) /* Very low speed */ +# define GPIO_OSPEED_LOW (1) /* Low speed */ +# define GPIO_OSPEED_MEDIUM (2) /* Medium speed */ +# define GPIO_OSPEED_HIGH (3) /* High speed */ +#else +# define GPIO_OSPEED_LOW (0) /* Low speed */ +# define GPIO_OSPEED_MEDIUM (1) /* Medium speed */ +# define GPIO_OSPEED_HIGH (3) /* High speed */ +#endif + +#define GPIO_OSPEED_SHIFT(n) ((n) << 1) +#define GPIO_OSPEED_MASK(n) (3 << GPIO_OSPEED_SHIFT(n)) + +#define GPIO_OSPEED0_SHIFT (0) +#define GPIO_OSPEED0_MASK (3 << GPIO_OSPEED0_SHIFT) +#define GPIO_OSPEED1_SHIFT (2) +#define GPIO_OSPEED1_MASK (3 << GPIO_OSPEED1_SHIFT) +#define GPIO_OSPEED2_SHIFT (4) +#define GPIO_OSPEED2_MASK (3 << GPIO_OSPEED2_SHIFT) +#define GPIO_OSPEED3_SHIFT (6) +#define GPIO_OSPEED3_MASK (3 << GPIO_OSPEED3_SHIFT) +#define GPIO_OSPEED4_SHIFT (8) +#define GPIO_OSPEED4_MASK (3 << GPIO_OSPEED4_SHIFT) +#define GPIO_OSPEED5_SHIFT (10) +#define GPIO_OSPEED5_MASK (3 << GPIO_OSPEED5_SHIFT) +#define GPIO_OSPEED6_SHIFT (12) +#define GPIO_OSPEED6_MASK (3 << GPIO_OSPEED6_SHIFT) +#define GPIO_OSPEED7_SHIFT (14) +#define GPIO_OSPEED7_MASK (3 << GPIO_OSPEED7_SHIFT) +#define GPIO_OSPEED8_SHIFT (16) +#define GPIO_OSPEED8_MASK (3 << GPIO_OSPEED8_SHIFT) +#define GPIO_OSPEED9_SHIFT (18) +#define GPIO_OSPEED9_MASK (3 << GPIO_OSPEED9_SHIFT) +#define GPIO_OSPEED10_SHIFT (20) +#define GPIO_OSPEED10_MASK (3 << GPIO_OSPEED10_SHIFT) +#define GPIO_OSPEED11_SHIFT (22) +#define GPIO_OSPEED11_MASK (3 << GPIO_OSPEED11_SHIFT) +#define GPIO_OSPEED12_SHIFT (24) +#define GPIO_OSPEED12_MASK (3 << GPIO_OSPEED12_SHIFT) +#define GPIO_OSPEED13_SHIFT (26) +#define GPIO_OSPEED13_MASK (3 << GPIO_OSPEED13_SHIFT) +#define GPIO_OSPEED14_SHIFT (28) +#define GPIO_OSPEED14_MASK (3 << GPIO_OSPEED14_SHIFT) +#define GPIO_OSPEED15_SHIFT (30) +#define GPIO_OSPEED15_MASK (3 << GPIO_OSPEED15_SHIFT) + +/* GPIO port pull-up/pull-down register */ + +#define GPIO_PUPDR_NONE (0) /* No pull-up, pull-down */ +#define GPIO_PUPDR_PULLUP (1) /* Pull-up */ +#define GPIO_PUPDR_PULLDOWN (2) /* Pull-down */ + +#define GPIO_PUPDR_SHIFT(n) ((n) << 1) +#define GPIO_PUPDR_MASK(n) (3 << GPIO_PUPDR_SHIFT(n)) + +#define GPIO_PUPDR0_SHIFT (0) +#define GPIO_PUPDR0_MASK (3 << GPIO_PUPDR0_SHIFT) +#define GPIO_PUPDR1_SHIFT (2) +#define GPIO_PUPDR1_MASK (3 << GPIO_PUPDR1_SHIFT) +#define GPIO_PUPDR2_SHIFT (4) +#define GPIO_PUPDR2_MASK (3 << GPIO_PUPDR2_SHIFT) +#define GPIO_PUPDR3_SHIFT (6) +#define GPIO_PUPDR3_MASK (3 << GPIO_PUPDR3_SHIFT) +#define GPIO_PUPDR4_SHIFT (8) +#define GPIO_PUPDR4_MASK (3 << GPIO_PUPDR4_SHIFT) +#define GPIO_PUPDR5_SHIFT (10) +#define GPIO_PUPDR5_MASK (3 << GPIO_PUPDR5_SHIFT) +#define GPIO_PUPDR6_SHIFT (12) +#define GPIO_PUPDR6_MASK (3 << GPIO_PUPDR6_SHIFT) +#define GPIO_PUPDR7_SHIFT (14) +#define GPIO_PUPDR7_MASK (3 << GPIO_PUPDR7_SHIFT) +#define GPIO_PUPDR8_SHIFT (16) +#define GPIO_PUPDR8_MASK (3 << GPIO_PUPDR8_SHIFT) +#define GPIO_PUPDR9_SHIFT (18) +#define GPIO_PUPDR9_MASK (3 << GPIO_PUPDR9_SHIFT) +#define GPIO_PUPDR10_SHIFT (20) +#define GPIO_PUPDR10_MASK (3 << GPIO_PUPDR10_SHIFT) +#define GPIO_PUPDR11_SHIFT (22) +#define GPIO_PUPDR11_MASK (3 << GPIO_PUPDR11_SHIFT) +#define GPIO_PUPDR12_SHIFT (24) +#define GPIO_PUPDR12_MASK (3 << GPIO_PUPDR12_SHIFT) +#define GPIO_PUPDR13_SHIFT (26) +#define GPIO_PUPDR13_MASK (3 << GPIO_PUPDR13_SHIFT) +#define GPIO_PUPDR14_SHIFT (28) +#define GPIO_PUPDR14_MASK (3 << GPIO_PUPDR14_SHIFT) +#define GPIO_PUPDR15_SHIFT (30) +#define GPIO_PUPDR15_MASK (3 << GPIO_PUPDR15_SHIFT) + +/* GPIO port input data register */ + +#define GPIO_IDR(n) (1 << (n)) + +/* GPIO port output data register */ + +#define GPIO_ODR(n) (1 << (n)) + +/* GPIO port bit set/reset register */ + +#define GPIO_BSRR_SET(n) (1 << (n)) +#define GPIO_BSRR_RESET(n) (1 << ((n) + 16)) + +/* GPIO port configuration lock register */ + +#define GPIO_LCKR(n) (1 << (n)) +#define GPIO_LCKK (1 << 16) /* Lock key */ + +/* GPIO alternate function low/high register */ + +#define GPIO_AFR_SHIFT(n) ((n) << 2) +#define GPIO_AFR_MASK(n) (15 << GPIO_AFR_SHIFT(n)) + +#define GPIO_AFRL0_SHIFT (0) +#define GPIO_AFRL0_MASK (15 << GPIO_AFRL0_SHIFT) +#define GPIO_AFRL1_SHIFT (4) +#define GPIO_AFRL1_MASK (15 << GPIO_AFRL1_SHIFT) +#define GPIO_AFRL2_SHIFT (8) +#define GPIO_AFRL2_MASK (15 << GPIO_AFRL2_SHIFT) +#define GPIO_AFRL3_SHIFT (12) +#define GPIO_AFRL3_MASK (15 << GPIO_AFRL3_SHIFT) +#define GPIO_AFRL4_SHIFT (16) +#define GPIO_AFRL4_MASK (15 << GPIO_AFRL4_SHIFT) +#define GPIO_AFRL5_SHIFT (20) +#define GPIO_AFRL5_MASK (15 << GPIO_AFRL5_SHIFT) +#define GPIO_AFRL6_SHIFT (24) +#define GPIO_AFRL6_MASK (15 << GPIO_AFRL6_SHIFT) +#define GPIO_AFRL7_SHIFT (28) +#define GPIO_AFRL7_MASK (15 << GPIO_AFRL7_SHIFT) + +/* GPIO port bit reset register */ + +#define GPIO_BRR(n) (1 << (n)) + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_GPIO_V2_M0_H */ diff --git a/arch/arm/src/common/stm32/hardware/stm32_i2c.h b/arch/arm/src/common/stm32/hardware/stm32_i2c.h new file mode 100644 index 0000000000000..879ec20a764f2 --- /dev/null +++ b/arch/arm/src/common/stm32/hardware/stm32_i2c.h @@ -0,0 +1,51 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/hardware/stm32_i2c.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_I2C_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_I2C_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#if (defined(CONFIG_STM32_HAVE_IP_I2C_M0_V1) + \ + defined(CONFIG_STM32_HAVE_IP_I2C_M3M4_V1) + \ + defined(CONFIG_STM32_HAVE_IP_I2C_M3M4_V2)) > 1 +# error Only one STM32 I2C IP version must be selected +#endif + +#if defined(CONFIG_STM32_HAVE_IP_I2C_M0_V1) +# include "hardware/stm32_i2c_v2_m0.h" +#elif defined(CONFIG_STM32_HAVE_IP_I2C_M3M4_V1) || defined(CONFIG_STM32_HAVE_IP_I2C_M3M4_V2) + +#if defined(CONFIG_STM32_HAVE_IP_I2C_M3M4_V1) +# include "stm32_i2c_v1.h" +#elif defined(CONFIG_STM32_HAVE_IP_I2C_M3M4_V2) +# include "stm32_i2c_v2.h" +#else +# error STM32 I2C IP version not specified +#endif +#else +# error "Unsupported STM32 I2C" +#endif + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_I2C_H */ diff --git a/arch/arm/src/stm32/hardware/stm32_i2c_v1.h b/arch/arm/src/common/stm32/hardware/stm32_i2c_v1.h similarity index 97% rename from arch/arm/src/stm32/hardware/stm32_i2c_v1.h rename to arch/arm/src/common/stm32/hardware/stm32_i2c_v1.h index 85ef897b18c1b..9f3bbda52a425 100644 --- a/arch/arm/src/stm32/hardware/stm32_i2c_v1.h +++ b/arch/arm/src/common/stm32/hardware/stm32_i2c_v1.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32_i2c_v1.h + * arch/arm/src/common/stm32/hardware/stm32_i2c_v1.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_I2C_V1_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_I2C_V1_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_I2C_V1_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_I2C_V1_H /* This file provide definitions for the STM32 I2C IP core 1 *(F1, F2, F4 and L1) @@ -200,4 +200,4 @@ # define I2C_FLTR_DNF_MASK (0xf << I2C_FLTR_DNF_SHIFT) #endif -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_I2C_V1_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_I2C_V1_H */ diff --git a/arch/arm/src/stm32/hardware/stm32_i2c_v2.h b/arch/arm/src/common/stm32/hardware/stm32_i2c_v2.h similarity index 98% rename from arch/arm/src/stm32/hardware/stm32_i2c_v2.h rename to arch/arm/src/common/stm32/hardware/stm32_i2c_v2.h index e1cf74909828d..5f3212b26c345 100644 --- a/arch/arm/src/stm32/hardware/stm32_i2c_v2.h +++ b/arch/arm/src/common/stm32/hardware/stm32_i2c_v2.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32_i2c_v2.h + * arch/arm/src/common/stm32/hardware/stm32_i2c_v2.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_I2C_V2_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_I2C_V2_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_I2C_V2_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_I2C_V2_H /* This file provide definitions for the STM32 I2C IP core 2 (F0, F3, F7, G0, * G4, H7, L0 and L4). @@ -238,4 +238,4 @@ #define I2C_TXDR_MASK (0xff) -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_I2C_V2_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_I2C_V2_H */ diff --git a/arch/arm/src/common/stm32/hardware/stm32_i2c_v2_m0.h b/arch/arm/src/common/stm32/hardware/stm32_i2c_v2_m0.h new file mode 100644 index 0000000000000..2f8d29fd1f9a5 --- /dev/null +++ b/arch/arm/src/common/stm32/hardware/stm32_i2c_v2_m0.h @@ -0,0 +1,227 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/hardware/stm32_i2c_v2_m0.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_I2C_V2_M0_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_I2C_V2_M0_H + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Register Offsets *********************************************************/ + +#define STM32_I2C_CR1_OFFSET 0x0000 /* Control register 1 (32-bit) */ +#define STM32_I2C_CR2_OFFSET 0x0004 /* Control register 2 (32-bit) */ +#define STM32_I2C_OAR1_OFFSET 0x0008 /* Own address register 1 (16-bit) */ +#define STM32_I2C_OAR2_OFFSET 0x000c /* Own address register 2 (16-bit) */ +#define STM32_I2C_TIMINGR_OFFSET 0x0010 /* Timing register */ +#define STM32_I2C_TIMEOUTR_OFFSET 0x0014 /* Timeout register */ +#define STM32_I2C_ISR_OFFSET 0x0018 /* Interrupt and Status register */ +#define STM32_I2C_ICR_OFFSET 0x001c /* Interrupt clear register */ +#define STM32_I2C_PECR_OFFSET 0x0020 /* Packet error checking register */ +#define STM32_I2C_RXDR_OFFSET 0x0024 /* Receive data register */ +#define STM32_I2C_TXDR_OFFSET 0x0028 /* Transmit data register */ + +/* Register Addresses *******************************************************/ + +#if STM32_NI2C > 0 +# define STM32_I2C1_CR1 (STM32_I2C1_BASE + STM32_I2C_CR1_OFFSET) +# define STM32_I2C1_CR2 (STM32_I2C1_BASE + STM32_I2C_CR2_OFFSET) +# define STM32_I2C1_OAR1 (STM32_I2C1_BASE + STM32_I2C_OAR1_OFFSET) +# define STM32_I2C1_OAR2 (STM32_I2C1_BASE + STM32_I2C_OAR2_OFFSET) +# define STM32_I2C1_TIMINGR (STM32_I2C1_BASE + STM32_I2C_TIMINGR_OFFSET) +# define STM32_I2C1_TIMEOUTR (STM32_I2C1_BASE + STM32_I2C_TIMEOUTR_OFFSET) +# define STM32_I2C1_ISR (STM32_I2C1_BASE + STM32_I2C_ISR_OFFSET) +# define STM32_I2C1_ICR (STM32_I2C1_BASE + STM32_I2C_ICR_OFFSET) +# define STM32_I2C1_PECR (STM32_I2C1_BASE + STM32_I2C_PECR_OFFSET) +# define STM32_I2C1_RXDR (STM32_I2C1_BASE + STM32_I2C_RXDR_OFFSET) +# define STM32_I2C1_TXDR (STM32_I2C1_BASE + STM32_I2C_TXDR_OFFSET) +#endif + +#if STM32_NI2C > 1 +# define STM32_I2C2_CR1 (STM32_I2C2_BASE + STM32_I2C_CR1_OFFSET) +# define STM32_I2C2_CR2 (STM32_I2C2_BASE + STM32_I2C_CR2_OFFSET) +# define STM32_I2C2_OAR1 (STM32_I2C2_BASE + STM32_I2C_OAR1_OFFSET) +# define STM32_I2C2_OAR2 (STM32_I2C2_BASE + STM32_I2C_OAR2_OFFSET) +# define STM32_I2C2_TIMINGR (STM32_I2C2_BASE + STM32_I2C_TIMINGR_OFFSET) +# define STM32_I2C2_TIMEOUTR (STM32_I2C2_BASE + STM32_I2C_TIMEOUTR_OFFSET) +# define STM32_I2C2_ISR (STM32_I2C2_BASE + STM32_I2C_ISR_OFFSET) +# define STM32_I2C2_ICR (STM32_I2C2_BASE + STM32_I2C_ICR_OFFSET) +# define STM32_I2C2_PECR (STM32_I2C2_BASE + STM32_I2C_PECR_OFFSET) +# define STM32_I2C2_RXDR (STM32_I2C2_BASE + STM32_I2C_RXDR_OFFSET) +# define STM32_I2C2_TXDR (STM32_I2C2_BASE + STM32_I2C_TXDR_OFFSET) +#endif + +/* Register Bitfield Definitions ********************************************/ + +/* Control register 1 */ + +#define I2C_CR1_PE (1 << 0) /* Bit 0: Peripheral Enable */ +#define I2C_CR1_TXIE (1 << 1) /* Bit 1: TX Interrupt enable */ +#define I2C_CR1_RXIE (1 << 2) /* Bit 2: RX Interrupt enable */ +#define I2C_CR1_ADDRIE (1 << 3) /* Bit 3: Address match interrupt enable (slave) */ +#define I2C_CR1_NACKIE (1 << 4) /* Bit 4: Not acknowledge received interrupt enable */ +#define I2C_CR1_STOPIE (1 << 5) /* Bit 5: STOP detection interrupt enable */ +#define I2C_CR1_TCIE (1 << 6) /* Bit 6: Transfer Complete interrupt enable */ +#define I2C_CR1_ERRIE (1 << 7) /* Bit 7: Error interrupts enable */ +#define I2C_CR1_DNF_SHIFT (8) /* Bits 8-11: Digital noise filter */ +#define I2C_CR1_DNF_MASK (15 << I2C_CR1_DNF_SHIFT) +# define I2C_CR1_DNF_DISABLE (0 << I2C_CR1_DNF_SHIFT) +# define I2C_CR1_DNF(n) ((n) << I2C_CR1_DNF_SHIFT) /* Up to n * Ti2cclk, n=1..15 */ + +#define I2C_CR1_ANFOFF (1 << 12) /* Bit 12: Analog noise filter OFF */ +#define I2C_CR1_TXDMAEN (1 << 14) /* Bit 14: DMA transmission requests enable */ +#define I2C_CR1_RXDMAEN (1 << 15) /* Bit 15: DMA reception requests enable */ +#define I2C_CR1_SBC (1 << 16) /* Bit 16: Slave byte control */ +#define I2C_CR1_NOSTRETCH (1 << 17) /* Bit 17: Clock stretching disable */ +#define I2C_CR1_WUPEN (1 << 18) /* Bit 18: Wakeup from STOP enable */ +#define I2C_CR1_GCEN (1 << 19) /* Bit 19: General call enable */ +#define I2C_CR1_SMBHEN (1 << 20) /* Bit 20: SMBus Host address enable */ +#define I2C_CR1_SMBDEN (1 << 21) /* Bit 21: SMBus Device Default address enable */ +#define I2C_CR1_ALERTEN (1 << 22) /* Bit 22: SMBus alert enable */ +#define I2C_CR1_PECEN (1 << 23) /* Bit 23: PEC enable */ + +/* Control register 2 */ + +#define I2C_CR2_SADD10_SHIFT (0) /* Bits 0-9: Slave 10-bit address (master) */ +#define I2C_CR2_SADD10_MASK (0x3ff << I2C_CR2_SADD10_SHIFT) +#define I2C_CR2_SADD7_SHIFT (1) /* Bits 1-7: Slave 7-bit address (master) */ +#define I2C_CR2_SADD7_MASK (0x7f << I2C_CR2_SADD7_SHIFT) +#define I2C_CR2_RD_WRN (1 << 10) /* Bit 10: Transfer direction (master) */ +#define I2C_CR2_ADD10 (1 << 11) /* Bit 11: 10-bit addressing mode (master) */ +#define I2C_CR2_HEAD10R (1 << 12) /* Bit 12: 10-bit address header only read direction (master) */ +#define I2C_CR2_START (1 << 13) /* Bit 13: Start generation */ +#define I2C_CR2_STOP (1 << 14) /* Bit 14: Stop generation (master) */ +#define I2C_CR2_NACK (1 << 15) /* Bit 15: NACK generation (slave) */ +#define I2C_CR2_NBYTES_SHIFT (16) /* Bits 16-23: Number of bytes */ +#define I2C_CR2_NBYTES_MASK (0xff << I2C_CR2_NBYTES_SHIFT) +#define I2C_CR2_RELOAD (1 << 24) /* Bit 24: NBYTES reload mode */ +#define I2C_CR2_AUTOEND (1 << 25) /* Bit 25: Automatic end mode (master) */ +#define I2C_CR2_PECBYTE (1 << 26) /* Bit 26: Packet error checking byte */ + +/* Own address register 1 */ + +#define I2C_OAR1_OA1_10_SHIFT (0) /* Bits 0-9: 10-bit interface address */ +#define I2C_OAR1_OA1_10_MASK (0x3ff << I2C_OAR1_OA1_10_SHIFT) +#define I2C_OAR1_OA1_7_SHIFT (1) /* Bits 1-7: 7-bit interface address */ +#define I2C_OAR1_OA1_7_MASK (0x7f << I2C_OAR1_OA1_7_SHIFT) +#define I2C_OAR1_OA1MODE (1 << 10) /* Bit 10: Own Address 1 10-bit mode */ +#define I2C_OAR1_OA1EN (1 << 15) /* Bit 15: Own Address 1 enable */ + +/* Own address register 2 */ + +#define I2C_OAR2_OA2_SHIFT (1) /* Bits 1-7: 7-bit interface address */ +#define I2C_OAR2_OA2_MASK (0x7f << I2C_OAR2_OA2_SHIFT) +#define I2C_OAR2_OA2MSK_SHIFT (8) /* Bits 8-10: Own Address 2 masks */ +#define I2C_OAR2_OA2MSK_MASK (7 << I2C_OAR2_OA2MSK_SHIFT) +# define I2C_OAR2_OA2MSK_NONE (0 << I2C_OAR2_OA2MSK_SHIFT) /* No mask */ +# define I2C_OAR2_OA2MSK_2_7 (1 << I2C_OAR2_OA2MSK_SHIFT) /* Only OA2[7:2] are compared */ +# define I2C_OAR2_OA2MSK_3_7 (2 << I2C_OAR2_OA2MSK_SHIFT) /* Only OA2[7:3] are compared */ +# define I2C_OAR2_OA2MSK_4_7 (3 << I2C_OAR2_OA2MSK_SHIFT) /* Only OA2[7:4] are compared */ +# define I2C_OAR2_OA2MSK_5_7 (4 << I2C_OAR2_OA2MSK_SHIFT) /* Only OA2[7:5] are compared */ +# define I2C_OAR2_OA2MSK_6_7 (5 << I2C_OAR2_OA2MSK_SHIFT) /* Only OA2[7:6] are compared */ +# define I2C_OAR2_OA2MSK_7 (6 << I2C_OAR2_OA2MSK_SHIFT) /* Only OA2[7] is compared */ +# define I2C_OAR2_OA2MSK_ALL (7 << I2C_OAR2_OA2MSK_SHIFT) /* All 7-bit addresses acknowledged */ + +#define I2C_OAR2_OA2EN (1 << 15) /* Bit 15: Own Address 2 enable */ + +/* Timing register */ + +#define I2C_TIMINGR_SCLL_SHIFT (0) /* Bits 0-7: SCL low period (master) */ +#define I2C_TIMINGR_SCLL_MASK (0xff << I2C_TIMINGR_SCLL_SHIFT) +# define I2C_TIMINGR_SCLL(n) (((n)-1) << I2C_TIMINGR_SCLL_SHIFT) /* tSCLL = n x tPRESC */ + +#define I2C_TIMINGR_SCLH_SHIFT (8) /* Bits 8-15: SCL high period (master) */ +#define I2C_TIMINGR_SCLH_MASK (0xff << I2C_TIMINGR_SCLH_SHIFT) +# define I2C_TIMINGR_SCLH(n) (((n)-1) << I2C_TIMINGR_SCLH_SHIFT) /* tSCLH = n x tPRESC */ + +#define I2C_TIMINGR_SDADEL_SHIFT (16) /* Bits 16-19: Data hold time */ +#define I2C_TIMINGR_SDADEL_MASK (15 << I2C_TIMINGR_SDADEL_SHIFT) +# define I2C_TIMINGR_SDADEL(n) ((n) << I2C_TIMINGR_SDADEL_SHIFT) /* tSDADEL= n x tPRESC */ + +#define I2C_TIMINGR_SCLDEL_SHIFT (20) /* Bits 20-23: Data setup time */ +#define I2C_TIMINGR_SCLDEL_MASK (15 << I2C_TIMINGR_SCLDEL_SHIFT) +# define I2C_TIMINGR_SCLDEL(n) (((n)-1) << I2C_TIMINGR_SCLDEL_SHIFT) /* tSCLDEL = n x tPRESC */ + +#define I2C_TIMINGR_PRESC_SHIFT (28) /* Bits 28-31: Timing prescaler */ +#define I2C_TIMINGR_PRESC_MASK (15 << I2C_TIMINGR_PRESC_SHIFT) +# define I2C_TIMINGR_PRESC(n) (((n)-1) << I2C_TIMINGR_PRESC_SHIFT) /* tPRESC = n x tI2CCLK */ + +/* Timeout register */ + +#define I2C_TIMEOUTR_A_SHIFT (0) /* Bits 0-11: Bus Timeout A */ +#define I2C_TIMEOUTR_A_MASK (0x0fff << I2C_TIMEOUTR_A_SHIFT) +# define I2C_TIMEOUTR_A(n) ((n) << I2C_TIMEOUTR_A_SHIFT) +#define I2C_TIMEOUTR_TIDLE (1 << 12) /* Bit 12: Idle clock timeout detection */ +#define I2C_TIMEOUTR_TIMOUTEN (1 << 15) /* Bit 15: Clock timeout enable */ +#define I2C_TIMEOUTR_B_SHIFT (16) /* Bits 16-27: Bus Timeout B */ +#define I2C_TIMEOUTR_B_MASK (0x0fff << I2C_TIMEOUTR_B_SHIFT) +# define I2C_TIMEOUTR_B(n) ((n) << I2C_TIMEOUTR_B_SHIFT) +#define I2C_TIMEOUTR_TEXTEN (1 << 31) /* Bits 31: Extended clock timeout enable */ + +/* Interrupt and Status register and interrupt clear register */ + +/* Common interrupt bits */ + +#define I2C_INT_ADDR (1 << 3) /* Bit 3: Address matched (slave) */ +#define I2C_INT_NACK (1 << 4) /* Bit 4: Not Acknowledge received flag */ +#define I2C_INT_STOP (1 << 5) /* Bit 5: Stop detection flag */ +#define I2C_INT_BERR (1 << 8) /* Bit 8: Bus error */ +#define I2C_INT_ARLO (1 << 9) /* Bit 9: Arbitration lost */ +#define I2C_INT_OVR (1 << 10) /* Bit 10: Overrun/Underrun (slave) */ +#define I2C_INT_PECERR (1 << 11) /* Bit 11: PEC Error in reception */ +#define I2C_INT_TIMEOUT (1 << 12) /* Bit 12: Timeout or tLOW detection flag */ +#define I2C_INT_ALERT (1 << 13) /* Bit 13: SMBus alert */ + +/* Fields unique to the Interrupt and Status register */ + +#define I2C_ISR_TXE (1 << 0) /* Bit 0: Transmit data register empty (transmitters) */ +#define I2C_ISR_TXIS (1 << 1) /* Bit 1: Transmit interrupt status (transmitters) */ +#define I2C_ISR_RXNE (1 << 2) /* Bit 2: Receive data register not empty (receivers) */ +#define I2C_ISR_ADDR (1 << 3) /* Bit 3: Address Match (slave mode) */ +#define I2C_ISR_NACKF (1 << 4) /* Bit 4: Not Acknowledge received flag */ +#define I2C_ISR_STOPF (1 << 5) /* Bit 5: Stop detection flag */ +#define I2C_ISR_TC (1 << 6) /* Bit 6: Transfer Complete (master) */ +#define I2C_ISR_TCR (1 << 7) /* Bit 7: Transfer Complete Reload */ +#define I2C_ISR_BUSY (1 << 15) /* Bit 15: Bus busy */ +#define I2C_ISR_DIR (1 << 16) /* Bit 16: Transfer direction (slave) */ +#define I2C_ISR_ADDCODE_SHIFT (17) /* Bits 17-23: Address match code (slave) */ +#define I2C_ISR_ADDCODE_MASK (0x7f << I2C_ISR_ADDCODE_SHIFT) + +#define I2C_ISR_ERRORMASK (I2C_INT_BERR | I2C_INT_ARLO | I2C_INT_OVR | I2C_INT_PECERR | I2C_INT_TIMEOUT) + +#define I2C_ICR_CLEARMASK (I2C_INT_ADDR | I2C_INT_NACK | I2C_INT_STOP | I2C_INT_BERR | I2C_INT_ARLO \ + | I2C_INT_OVR | I2C_INT_PECERR | I2C_INT_TIMEOUT | I2C_INT_ALERT) + +/* Packet error checking register */ + +#define I2C_PECR_MASK (0xff) + +/* Receive data register */ + +#define I2C_RXDR_MASK (0xff) + +/* Transmit data register */ + +#define I2C_TXDR_MASK (0xff) + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_I2C_V2_M0_H */ diff --git a/arch/arm/src/stm32/hardware/stm32_lcd.h b/arch/arm/src/common/stm32/hardware/stm32_lcd.h similarity index 98% rename from arch/arm/src/stm32/hardware/stm32_lcd.h rename to arch/arm/src/common/stm32/hardware/stm32_lcd.h index 806fbe38b5a60..d23ab4d41e72b 100644 --- a/arch/arm/src/stm32/hardware/stm32_lcd.h +++ b/arch/arm/src/common/stm32/hardware/stm32_lcd.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32_lcd.h + * arch/arm/src/common/stm32/hardware/stm32_lcd.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_LCD_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_LCD_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_LCD_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_LCD_H /**************************************************************************** * Included Files @@ -206,4 +206,4 @@ #define LCD_RAMH_S(n) (1 << ((n)-32)) #endif /* STM32_NLCD */ -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_LCD_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_LCD_H */ diff --git a/arch/arm/src/common/stm32/hardware/stm32_ltdc.h b/arch/arm/src/common/stm32/hardware/stm32_ltdc.h new file mode 100644 index 0000000000000..9d7be41f4390b --- /dev/null +++ b/arch/arm/src/common/stm32/hardware/stm32_ltdc.h @@ -0,0 +1,368 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/hardware/stm32_ltdc.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_LTDC_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_LTDC_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include "hardware/stm32_memorymap.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define STM32_LTDC_NCLUT 256 /* Number of entries in the CLUTs */ + +/* LCDC Register Offsets ****************************************************/ + +#define STM32_LTDC_SSCR_OFFSET 0x0008 /* LTDC Synchronization Size Config Register */ +#define STM32_LTDC_BPCR_OFFSET 0x000c /* LTDC Back Porch Configuration Register */ +#define STM32_LTDC_AWCR_OFFSET 0x0010 /* LTDC Active Width Configuration Register */ +#define STM32_LTDC_TWCR_OFFSET 0x0014 /* LTDC Total Width Configuration Register */ +#define STM32_LTDC_GCR_OFFSET 0x0018 /* LTDC Global Control Register */ + /* 0x0020 Reserved */ +#define STM32_LTDC_SRCR_OFFSET 0x0024 /* LTDC Shadow Reload Configuration Register */ + /* 0x0028 Reserved */ +#define STM32_LTDC_BCCR_OFFSET 0x002c /* LTDC Background Color Configuration Register */ + /* 0x0030 Reserved */ +#define STM32_LTDC_IER_OFFSET 0x0034 /* LTDC Interrupt Enable Register */ +#define STM32_LTDC_ISR_OFFSET 0x0038 /* LTDC Interrupt Status Register */ +#define STM32_LTDC_ICR_OFFSET 0x003c /* LTDC Interrupt Clear Register */ +#define STM32_LTDC_LIPCR_OFFSET 0x0040 /* LTDC Line Interrupt Position Config Register */ +#define STM32_LTDC_CPSR_OFFSET 0x0044 /* LTDC Current Position Status Register */ +#define STM32_LTDC_CDSR_OFFSET 0x0048 /* LTDC Current Display Status Register */ + /* 0x004c-0x0080 Reserved */ + +#define STM32_LTDC_L1CR_OFFSET 0x0084 /* LTDC Layer 1 Control Register */ +#define STM32_LTDC_L1WHPCR_OFFSET 0x0088 /* LTDC Layer 1 Window Horiz Pos Config Register */ +#define STM32_LTDC_L1WVPCR_OFFSET 0x008c /* LTDC Layer 1 Window Vert Pos Config Register */ +#define STM32_LTDC_L1CKCR_OFFSET 0x0090 /* LTDC Layer 1 Color Keying Config Register */ +#define STM32_LTDC_L1PFCR_OFFSET 0x0094 /* LTDC Layer 1 Pixel Format Configuration Register */ +#define STM32_LTDC_L1CACR_OFFSET 0x0098 /* LTDC Layer 1 Constant Alpha Config Register */ +#define STM32_LTDC_L1DCCR_OFFSET 0x009c /* LTDC Layer 1 Default Color Config Register */ +#define STM32_LTDC_L1BFCR_OFFSET 0x00a0 /* LTDC Layer 1 Blending Factors Config Register */ + /* 0x00A4-0x00A8 Reserved */ +#define STM32_LTDC_L1CFBAR_OFFSET 0x00ac /* LTDC Layer 1 Color Frame Buffer Address Register */ +#define STM32_LTDC_L1CFBLR_OFFSET 0x00b0 /* LTDC Layer 1 Color Frame Buffer Length Register */ +#define STM32_LTDC_L1CFBLNR_OFFSET 0x00b4 /* LTDC Layer 1 Color Frame Buffer Line Number Register */ + /* 0x00B8-0x00C0 Reserved */ +#define STM32_LTDC_L1CLUTWR_OFFSET 0x00c4 /* LTDC Layer 1 CLUT Write Register */ + /* 0x00C8-0x0100 Reserved */ +#define STM32_LTDC_L2CR_OFFSET 0x0104 /* LTDC Layer 2 Control Register */ +#define STM32_LTDC_L2WHPCR_OFFSET 0x0108 /* LTDC Layer 2 Window Horiz Pos Config Register */ +#define STM32_LTDC_L2WVPCR_OFFSET 0x010c /* LTDC Layer 2 Window Vert Pos Config Register */ +#define STM32_LTDC_L2CKCR_OFFSET 0x0110 /* LTDC Layer 2 Color Keying Config Register */ +#define STM32_LTDC_L2PFCR_OFFSET 0x0114 /* LTDC Layer 2 Pixel Format Configuration Register */ +#define STM32_LTDC_L2CACR_OFFSET 0x0118 /* LTDC Layer 2 Constant Alpha Config Register */ +#define STM32_LTDC_L2DCCR_OFFSET 0x011c /* LTDC Layer 2 Default Color Config Register */ +#define STM32_LTDC_L2BFCR_OFFSET 0x0120 /* LTDC Layer 2 Blending Factors Config Register */ + /* 0x0124-0x0128 Reserved */ +#define STM32_LTDC_L2CFBAR_OFFSET 0x012c /* LTDC Layer 2 Color Frame Buffer Address Register */ +#define STM32_LTDC_L2CFBLR_OFFSET 0x0130 /* LTDC Layer 2 Color Frame Buffer Length Register */ +#define STM32_LTDC_L2CFBLNR_OFFSET 0x0134 /* LTDC Layer 2 Color Frame Buffer Line Number Register */ + /* 0x0138-0x0130 Reserved */ +#define STM32_LTDC_L2CLUTWR_OFFSET 0x0144 /* LTDC Layer 2 CLUT Write Register */ + /* 0x0148-0x03ff Reserved */ + +/* LTDC Register Addresses **************************************************/ + +#define STM32_LTDC_SSCR (STM32_LTDC_BASE + STM32_LTDC_SSCR_OFFSET) +#define STM32_LTDC_BPCR (STM32_LTDC_BASE + STM32_LTDC_BPCR_OFFSET) +#define STM32_LTDC_AWCR (STM32_LTDC_BASE + STM32_LTDC_AWCR_OFFSET) +#define STM32_LTDC_TWCR (STM32_LTDC_BASE + STM32_LTDC_TWCR_OFFSET) +#define STM32_LTDC_GCR (STM32_LTDC_BASE + STM32_LTDC_GCR_OFFSET) +#define STM32_LTDC_SRCR (STM32_LTDC_BASE + STM32_LTDC_SRCR_OFFSET) +#define STM32_LTDC_BCCR (STM32_LTDC_BASE + STM32_LTDC_BCCR_OFFSET) +#define STM32_LTDC_IER (STM32_LTDC_BASE + STM32_LTDC_IER_OFFSET) +#define STM32_LTDC_ISR (STM32_LTDC_BASE + STM32_LTDC_ISR_OFFSET) +#define STM32_LTDC_ICR (STM32_LTDC_BASE + STM32_LTDC_ICR_OFFSET) +#define STM32_LTDC_LIPCR (STM32_LTDC_BASE + STM32_LTDC_LIPCR_OFFSET) +#define STM32_LTDC_CPSR (STM32_LTDC_BASE + STM32_LTDC_CPSR_OFFSET) +#define STM32_LTDC_CDSR (STM32_LTDC_BASE + STM32_LTDC_CDSR_OFFSET) + +#define STM32_LTDC_L1CR (STM32_LTDC_BASE + STM32_LTDC_L1CR_OFFSET) +#define STM32_LTDC_L1WHPCR (STM32_LTDC_BASE + STM32_LTDC_L1WHPCR_OFFSET) +#define STM32_LTDC_L1WVPCR (STM32_LTDC_BASE + STM32_LTDC_L1WVPCR_OFFSET) +#define STM32_LTDC_L1CKCR (STM32_LTDC_BASE + STM32_LTDC_L1CKCR_OFFSET) +#define STM32_LTDC_L1PFCR (STM32_LTDC_BASE + STM32_LTDC_L1PFCR_OFFSET) +#define STM32_LTDC_L1CACR (STM32_LTDC_BASE + STM32_LTDC_L1CACR_OFFSET) +#define STM32_LTDC_L1DCCR (STM32_LTDC_BASE + STM32_LTDC_L1DCCR_OFFSET) +#define STM32_LTDC_L1BFCR (STM32_LTDC_BASE + STM32_LTDC_L1BFCR_OFFSET) +#define STM32_LTDC_L1CFBAR (STM32_LTDC_BASE + STM32_LTDC_L1CFBAR_OFFSET) +#define STM32_LTDC_L1CFBLR (STM32_LTDC_BASE + STM32_LTDC_L1CFBLR_OFFSET) +#define STM32_LTDC_L1CFBLNR (STM32_LTDC_BASE + STM32_LTDC_L1CFBLNR_OFFSET) +#define STM32_LTDC_L1CLUTWR (STM32_LTDC_BASE + STM32_LTDC_L1CLUTWR_OFFSET) + +#define STM32_LTDC_L2CR (STM32_LTDC_BASE + STM32_LTDC_L2CR_OFFSET) +#define STM32_LTDC_L2WHPCR (STM32_LTDC_BASE + STM32_LTDC_L2WHPCR_OFFSET) +#define STM32_LTDC_L2WVPCR (STM32_LTDC_BASE + STM32_LTDC_L2WVPCR_OFFSET) +#define STM32_LTDC_L2CKCR (STM32_LTDC_BASE + STM32_LTDC_L2CKCR_OFFSET) +#define STM32_LTDC_L2PFCR (STM32_LTDC_BASE + STM32_LTDC_L2PFCR_OFFSET) +#define STM32_LTDC_L2CACR (STM32_LTDC_BASE + STM32_LTDC_L2CACR_OFFSET) +#define STM32_LTDC_L2DCCR (STM32_LTDC_BASE + STM32_LTDC_L2DCCR_OFFSET) +#define STM32_LTDC_L2BFCR (STM32_LTDC_BASE + STM32_LTDC_L2BFCR_OFFSET) +#define STM32_LTDC_L2CFBAR (STM32_LTDC_BASE + STM32_LTDC_L2CFBAR_OFFSET) +#define STM32_LTDC_L2CFBLR (STM32_LTDC_BASE + STM32_LTDC_L2CFBLR_OFFSET) +#define STM32_LTDC_L2CFBLNR (STM32_LTDC_BASE + STM32_LTDC_L2CFBLNR_OFFSET) +#define STM32_LTDC_L2CLUTWR (STM32_LTDC_BASE + STM32_LTDC_L2CLUTWR_OFFSET) + +/* LTDC Register Bit Definitions ********************************************/ + +/* LTDC Synchronization Size Configuration Register */ + +#define LTDC_SSCR_VSH_SHIFT (0) /* Bits 0-10: Vertical Sync Height (scan lines) */ +#define LTDC_SSCR_VSH_MASK (0x7ff << LTDC_SSCR_VSH_SHIFT) +# define LTDC_SSCR_VSH(n) ((uint32_t)(n) << LTDC_SSCR_VSH_SHIFT) +#define LTDC_SSCR_HSW_SHIFT (16) /* Bits 16-27: Horizontal Sync Width (pixel clocks) */ +#define LTDC_SSCR_HSW_MASK (0xfff << LTDC_SSCR_HSW_SHIFT) +# define LTDC_SSCR_HSW(n) ((uint32_t)(n) << LTDC_SSCR_HSW_SHIFT) + +/* LTDC Back Porch Configuration Register */ + +#define LTDC_BPCR_AVBP_SHIFT (0) /* Bits 0-10: Accumulated Vertical back porch (scan lines) */ +#define LTDC_BPCR_AVBP_MASK (0x7ff << LTDC_BPCR_AVBP_SHIFT) +# define LTDC_BPCR_AVBP(n) ((uint32_t)(n) << LTDC_BPCR_AVBP_SHIFT) +#define LTDC_BPCR_AHBP_SHIFT (16) /* Bits 16-27: Accumulated Horizontal back porch (pixel clocks) */ +#define LTDC_BPCR_AHBP_MASK (0xfff << LTDC_BPCR_AVBP_SHIFT) +# define LTDC_BPCR_AHBP(n) ((uint32_t)(n) << LTDC_BPCR_AHBP_SHIFT) + +/* LTDC Active Width Configuration Register */ + +#define LTDC_AWCR_AAH_SHIFT (0) /* Bits 0-10: Accumulated Active Height (scan lines) */ +#define LTDC_AWCR_AAH_MASK (0x7ff << LTDC_AWCR_AAH_SHIFT) +# define LTDC_AWCR_AAH(n) ((uint32_t)(n) << LTDC_AWCR_AAH_SHIFT) +#define LTDC_AWCR_AAW_SHIFT (16) /* Bits 16-27: Accumulated Active Width (pixel clocks) */ +#define LTDC_AWCR_AAW_MASK (0xfff << LTDC_AWCR_AAW_SHIFT) +# define LTDC_AWCR_AAW(n) ((uint32_t)(n) << LTDC_AWCR_AAW_SHIFT) + +/* LTDC Total Width Configuration Register */ + +#define LTDC_TWCR_TOTALH_SHIFT (0) /* Bits 0-10: Total Height (scan lines) */ +#define LTDC_TWCR_TOTALH_MASK (0x7ff << LTDC_TWCR_TOTALH_SHIFT) +# define LTDC_TWCR_TOTALH(n) ((uint32_t)(n) << LTDC_TWCR_TOTALH_SHIFT) +#define LTDC_TWCR_TOTALW_SHIFT (16) /* Bits 16-27: Total Width (pixel clocks) */ +#define LTDC_TWCR_TOTALW_MASK (0xfff << LTDC_TWCR_TOTALW_SHIFT) +# define LTDC_TWCR_TOTALW(n) ((uint32_t)(n) << LTDC_TWCR_TOTALW_SHIFT) + +/* LTDC Global Control Register */ + +#define LTDC_GCR_LTDCEN (1 << 0) /* Bit 0: LCD-TFT Controller Enable Bit */ +#define LTDC_GCR_DBW_SHIFT (4) /* Bits 4-6: Dither Blue Width */ +#define LTDC_GCR_DBW_MASK (0x7 << LTDC_GCR_DBW_SHIFT) +# define LTDC_GCR_DBW(n) ((uint32_t)(n) << LTDC_GCR_DBW_SHIFT) +#define LTDC_GCR_DGW_SHIFT (8) /* Bits 8-10: Dither Green Width */ +#define LTDC_GCR_DGW_MASK (0x7 << LTDC_GCR_DGW_SHIFT) +# define LTDC_GCR_DGW(n) ((uint32_t)(n) << LTDC_GCR_DGW_SHIFT) +#define LTDC_GCR_DRW_SHIFT (12) /* Bits 12-14: Dither Red Width */ +#define LTDC_GCR_DRW_MASK (0x7 << LTDC_GCR_DRW_SHIFT) +# define LTDC_GCR_DRW(n) ((uint32_t)(n) << LTDC_GCR_DRW_SHIFT) +#define LTDC_GCR_DEN (1 << 16) /* Bit 16: Dither Enable */ +#define LTDC_GCR_PCPOL (1 << 28) /* Bit 28: Pixel Clock Polarity */ +#define LTDC_GCR_DEPOL (1 << 29) /* Bit 29: Data Enable Polarity */ +#define LTDC_GCR_VSPOL (1 << 30) /* Bit 30: Vertical Sync Polarity */ +#define LTDC_GCR_HSPOL (1 << 31) /* Bit 31: Horizontal Sync Polarity */ + +/* LTDC Shadow Reload Configuration Register */ + +#define LTDC_SRCR_IMR (1 << 0) /* Bit 0: Immediate Reload */ +#define LTDC_SRCR_VBR (1 << 1) /* Bit 1: Vertical Blanking Reload */ + +/* LTDC Background Color Configuration Register */ + +#define LTDC_BCCR_BCBLUE_SHIFT (0) /* Bits 0-7: Background Color Blue Value */ +#define LTDC_BCCR_BCBLUE_MASK (0xff << LTDC_BCCR_BCBLUE_SHIFT) +# define LTDC_BCCR_BCBLUE(n) ((uint32_t)(n) << LTDC_BCCR_BCBLUE_SHIFT) +#define LTDC_BCCR_BCGREEN_SHIFT (8) /* Bits 8-15: Background Color Green Value */ +#define LTDC_BCCR_BCGREEN_MASK (0xff << LTDC_BCCR_BCGREEN_SHIFT) +# define LTDC_BCCR_BCGREEN(n) ((uint32_t)(n) << LTDC_BCCR_BCGREEN_SHIFT) +#define LTDC_BCCR_BCRED_SHIFT (16) /* Bits 16-23: Background Color Red Value */ +#define LTDC_BCCR_BCRED_MASK (0xff << LTDC_BCCR_BCRED_SHIFT) +# define LTDC_BCCR_BCRED(n) ((uint32_t)(n) << LTDC_BCCR_BCRED_SHIFT) + +/* LTDC Interrupt Enable Register */ + +#define LTDC_IER_LIE (1 << 0) /* Bit 0: Line Interrupt Enable */ +#define LTDC_IER_FUIE (1 << 1) /* Bit 1: FIFO Underrun Interrupt Enable */ +#define LTDC_IER_TERRIE (1 << 2) /* Bit 2: Transfer Error Interrupt Enable */ +#define LTDC_IER_RRIE (1 << 3) /* Bit 3: Register Reload Interrupt Enable */ + +/* LTDC Interrupt Status Register */ + +#define LTDC_ISR_LIF (1 << 0) /* Bit 0: Line Interrupt Flag */ +#define LTDC_ISR_FUIF (1 << 1) /* Bit 1: FIFO Underrun Interrupt Flag */ +#define LTDC_IER_TERRIF (1 << 2) /* Bit 2: Transfer Error Interrupt Flag */ +#define LTDC_ISR_RRIF (1 << 3) /* Bit 3: Register Reload Interrupt Flag */ + +/* LTDC Interrupt Clear Register */ + +#define LTDC_ICR_CLIF (1 << 0) /* Bit 0: Clear Line Interrupt Flag */ +#define LTDC_ICR_CFUIF (1 << 1) /* Bit 1: Clear FIFO Underrun Interrupt Flag */ +#define LTDC_ICR_CTERRIF (1 << 2) /* Bit 2: Clear Transfer Error Interrupt Flag */ +#define LTDC_ICR_CRRIF (1 << 3) /* Bit 3: Clear Register Reload Interrupt Flag */ + +/* LTDC Line Interrupt Posittion Configuration Register */ + +#define LTDC_LIPCR_LIPOS_SHIFT (0) /* Bits 0-10: Line Interrupt Position */ +#define LTDC_LIPCR_LIPOS_MASK (0x7ff << LTDC_LIPCR_LIPOS_SHIFT) +# define LTDC_LIPCR_LIPOS(n) ((uint32_t)(n) << LTDC_LIPCR_LIPOS_SHIFT) + +/* LTDC Current Position Status Register */ + +#define LTDC_CPSR_CYPOS_SHIFT (0) /* Bits 0-15: Current Y Position */ +#define LTDC_CPSR_CYPOS_MASK (0xffff << LTDC_CPSR_CYPOS_SHIFT) +# define LTDC_CPSR_CYPOS(n) ((uint32_t)(n) << LTDC_CPSR_CYPOS_SHIFT) +#define LTDC_CPSR_CXPOS_SHIFT (16) /* Bits 15-31: Current X Position */ +#define LTDC_CPSR_CXPOS_MASK (0xffff << LTDC_CPSR_CXPOS_SHIFT) +# define LTDC_CPSR_CXPOS(n) ((uint32_t)(n) << LTDC_CPSR_CXPOS_SHIFT) + +/* LTDC Current Display Status Register */ + +#define LTDC_CDSR_VDES (1 << 0) /* Bit 0: Vertical Data Enable display Status */ +#define LTDC_CDSR_HDES (1 << 1) /* Bit 1: Horizontal Data Enable display Status */ +#define LTDC_CDSR_VSYNCS (1 << 2) /* Bit 2: Vertical Sync display Status */ +#define LTDC_CDSR_HSYNCS (1 << 3) /* Bit 3: Horizontal Sync display Status */ + +/* LTDC Layer x Control Register */ + +#define LTDC_LXCR_LEN (1 << 0) /* Bit 0: Layer Enable */ +#define LTDC_LXCR_COLKEN (1 << 1) /* Bit 1: Color Keying Enable */ +#define LTDC_LXCR_CLUTEN (1 << 4) /* Bit 4: Color Look-Up Table Enable */ + +/* LTDC Layer x Window Horizontal Position Configuration Register */ + +#define LTDC_LXWHPCR_WHSTPOS_SHIFT (0) /* Bits 0-11: Window Horizontal Start Position */ +#define LTDC_LXWHPCR_WHSTPOS_MASK (0xFFF << LTDC_LXWHPCR_WHSTPOS_SHIFT) +# define LTDC_LXWHPCR_WHSTPOS(n) ((uint32_t)(n) << LTDC_LXWHPCR_WHSTPOS_SHIFT) +#define LTDC_LXWHPCR_WHSPPOS_SHIFT (16) /* Bits 16-27: Window Horizontal Stop Position */ +#define LTDC_LXWHPCR_WHSPPOS_MASK (0xFFF << LTDC_LXWHPCR_WHSPPOS_SHIFT) +# define LTDC_LXWHPCR_WHSPPOS(n) ((uint32_t)(n) << LTDC_LXWHPCR_WHSPPOS_SHIFT) + +/* LTDC Layer x Window Vertical Position Configuration Register */ + +#define LTDC_LXWVPCR_WVSTPOS_SHIFT (0) /* Bits 0-10: Window Vertical Start Position */ +#define LTDC_LXWVPCR_WVSTPOS_MASK (0x7ff << LTDC_LXWVPCR_WVSTPOS_SHIFT) +# define LTDC_LXWVPCR_WVSTPOS(n) ((uint32_t)(n) << LTDC_LXWVPCR_WVSTPOS_SHIFT) +#define LTDC_LXWVPCR_WVSPPOS_SHIFT (16) /* Bits 16-26: Window Vertical Stop Position */ +#define LTDC_LXWVPCR_WVSPPOS_MASK (0x7ff << LTDC_LXWVPCR_WVSPPOS_SHIFT) +# define LTDC_LXWVPCR_WVSPPOS(n) ((uint32_t)(n) << LTDC_LXWVPCR_WVSPPOS_SHIFT) + +/* LTDC Layer x Color Keying Configuration Register */ + +#define LTDC_LXCKCR_CKBLUE_SHIFT (0) /* Bits 0-7: Color Key Blue Value */ +#define LTDC_LXCKCR_CKBLUE_MASK (0xff << LTDC_LXCKCR_CKBLUE_SHIFT) +# define LTDC_LXCKCR_CKBLUE(n) ((uint32_t)(n) << LTDC_LXCKCR_CKBLUE_SHIFT) +#define LTDC_LXCKCR_CKGREEN_SHIFT (8) /* Bits 8-15: Color Key Green Value */ +#define LTDC_LXCKCR_CKGREEN_MASK (0xff << LTDC_LXCKCR_CKGREEN_SHIFT) +# define LTDC_LXCKCR_CKGREEN(n) ((uint32_t)(n) << LTDC_LXCKCR_CKGREEN_SHIFT) +#define LTDC_LXCKCR_CKRED_SHIFT (16) /* Bits 16-23: Color Key Red Value */ +#define LTDC_LXCKCR_CKRED_MASK (0xff << LTDC_LXCKCR_CKRED_SHIFT) +# define LTDC_LXCKCR_CKRED(n) ((uint32_t)(n) << LTDC_LXCKCR_CKRED_SHIFT) + +/* LTDC Layer x Pixel Format Configuration Register */ + +#define LTDC_LXPFCR_PF_SHIFT (0) /* Bits 0-2: Pixel Format */ +#define LTDC_LXPFCR_PF_MASK (0x7 << LTDC_LXPFCR_PF_SHIFT) +# define LTDC_LXPFCR_PF(n) ((uint32_t)(n) << LTDC_LXPFCR_PF_SHIFT) + +#define LTDC_PF_ARGB8888 0 +#define LTDC_PF_RGB888 1 +#define LTDC_PF_RGB565 2 +#define LTDC_PF_ARGB1555 3 +#define LTDC_PF_ARGB4444 4 +#define LTDC_PF_L8 5 /* 8-bit Luninance (CLUT lookup) */ +#define LTDC_PF_AL44 6 /* 4-bit Alpha, 4-bit Luminance */ +#define LTDC_PF_AL88 7 /* 8-bit Alpha, 8-bit Luminance */ + +/* LTDC Layer x Constant Alpha Configuration Register */ + +#define LTDC_LXCACR_CONSTA_SHIFT (0) /* Bits 0-7: Constant Alpha */ +#define LTDC_LXCACR_CONSTA_MASK (0x7 << LTDC_LXCACR_CONSTA_SHIFT) +# define LTDC_LXCACR_CONSTA(n) ((uint32_t)(n) << LTDC_LXCACR_CONSTA_SHIFT) + +/* LTDC Layer x Default Color Configuration Register */ + +#define LTDC_LXDCCR_DCBLUE_SHIFT (0) /* Bits 0-7: Default Color Blue Value */ +#define LTDC_LXDCCR_DCBLUE_MASK (0xff << LTDC_LXDCCR_DCBLUE_SHIFT) +# define LTDC_LXDCCR_DCBLUE(n) ((uint32_t)(n) << LTDC_LXDCCR_DCBLUE_SHIFT) +#define LTDC_LXDCCR_DCGREEN_SHIFT (8) /* Bits 8-15: Default Color Green Value */ +#define LTDC_LXDCCR_DCGREEN_MASK (0xff << LTDC_LXDCCR_DCGREEN_SHIFT) +# define LTDC_LXDCCR_DCGREEN(n) ((uint32_t)(n) << LTDC_LXDCCR_DCGREEN_SHIFT) +#define LTDC_LXDCCR_DCRED_SHIFT (16) /* Bits 16-23: Default Color Red Value */ +#define LTDC_LXDCCR_DCRED_MASK (0xff << LTDC_LXDCCR_DCRED_SHIFT) +# define LTDC_LXDCCR_DCRED(n) ((uint32_t)(n) << LTDC_LXDCCR_DCRED_SHIFT) +#define LTDC_LXDCCR_DCALPHA_SHIFT (24) /* Bits 24-31: Default Color Alpha Value */ +#define LTDC_LXDCCR_DCALPHA_MASK (0xff << LTDC_LXDCCR_DCALPHA_SHIFT) +# define LTDC_LXDCCR_DCALPHA(n) ((uint32_t)(n) << LTDC_LXDCCR_DCALPHA_SHIFT) + +/* LTDC Layer x Blending Factors Configuration Register */ + +#define LTDC_LXBFCR_BF2_SHIFT (0) /* Bits 0-2: Blending Factor 2 */ +#define LTDC_LXBFCR_BF2_MASK (0x7 << LTDC_LXBFCR_BF2_SHIFT) +# define LTDC_LXBFCR_BF2(n) ((uint32_t)(n) << LTDC_LXBFCR_BF2_SHIFT) +#define LTDC_LXBFCR_BF1_SHIFT (8) /* Bits 8-10: Blending Factor 1 */ +#define LTDC_LXBFCR_BF1_MASK (0x7 << LTDC_LXBFCR_BF1_SHIFT) +# define LTDC_LXBFCR_BF1(n) ((uint32_t)(n) << LTDC_LXBFCR_BF1_SHIFT) + +#define LTDC_BF1_CONST_ALPHA 0x04 /* Constant Alpha */ +#define LTDC_BF1_PIXEL_ALPHA 0x06 /* Pixel Alpha x Constant Alpha */ +#define LTDC_BF2_CONST_ALPHA 0x05 /* Constant Alpha */ +#define LTDC_BF2_PIXEL_ALPHA 0x07 /* Pixel Alpha x Constant Alpha */ + +/* LTDC Layer x Color Frame Buffer Length Configuration Register */ + +#define LTDC_LXCFBLR_CFBLL_SHIFT (0) /* Bits 0-12: Color Frame Buffer Line Length */ +#define LTDC_LXCFBLR_CFBLL_MASK (0x1fff << LTDC_LXCFBLR_CFBLL_SHIFT) +# define LTDC_LXCFBLR_CFBLL(n) ((uint32_t)(n) << LTDC_LXCFBLR_CFBLL_SHIFT) +#define LTDC_LXCFBLR_CFBP_SHIFT (16) /* Bits 16-28: Color Frame Buffer Pitch */ +#define LTDC_LXCFBLR_CFBP_MASK (0x1fff << LTDC_LXCFBLR_CFBP_SHIFT) +# define LTDC_LXCFBLR_CFBP(n) ((uint32_t)(n) << LTDC_LXCFBLR_CFBP_SHIFT) + +/* LTDC Layer x Color Frame Buffer Line Number Register */ + +#define LTDC_LXCFBLNR_LN_SHIFT (0) /* Bits 0-10: Color Frame Buffer Line Number */ +#define LTDC_LXCFBLNR_LN_MASK (0x7ff << LTDC_LXCFBLNR_LN_SHIFT) +# define LTDC_LXCFBLNR_LN(n) ((uint32_t)(n) << LTDC_LXCFBLNR_LN_SHIFT) + +/* LTDC Layer x CLUT Write Register */ + +#define LTDC_LXCLUTWR_BLUE_SHIFT (0) /* Bits 0-7: Default Color Blue Value */ +#define LTDC_LXCLUTWR_BLUE_MASK (0xff << LTDC_LXCLUTWR_BLUE_SHIFT) +# define LTDC_LXCLUTWR_BLUE(n) ((uint32_t)(n) << LTDC_LXCLUTWR_BLUE_SHIFT) +#define LTDC_LXCLUTWR_GREEN_SHIFT (8) /* Bits 8-15: Default Color Green Value */ +#define LTDC_LXCLUTWR_GREEN_MASK (0xff << LTDC_LXCLUTWR_GREEN_SHIFT) +# define LTDC_LXCLUTWR_GREEN(n) ((uint32_t)(n) << LTDC_LXCLUTWR_GREEN_SHIFT) +#define LTDC_LXCLUTWR_RED_SHIFT (16) /* Bits 16-23: Default Color Red Value */ +#define LTDC_LXCLUTWR_RED_MASK (0xff << LTDC_LXCLUTWR_RED_SHIFT) +# define LTDC_LXCLUTWR_RED(n) ((uint32_t)(n) << LTDC_LXCLUTWR_RED_SHIFT) +#define LTDC_LXCLUTWR_CLUTADD_SHIFT (24) /* Bits 24-31: CLUT Address */ +#define LTDC_LXCLUTWR_CLUTADD_MASK (0xff << LTDC_LXCLUTWR_CLUTADD_SHIFT) +# define LTDC_LXCLUTWR_CLUTADD(n) ((uint32_t)(n) << LTDC_LXCLUTWR_CLUTADD_SHIFT) + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_LTDC_H */ diff --git a/arch/arm/src/common/stm32/hardware/stm32_otghs.h b/arch/arm/src/common/stm32/hardware/stm32_otghs.h new file mode 100644 index 0000000000000..42e0fdab7c677 --- /dev/null +++ b/arch/arm/src/common/stm32/hardware/stm32_otghs.h @@ -0,0 +1,1111 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/hardware/stm32_otghs.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_OTGHS_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_OTGHS_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include "chip.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* General definitions */ + +#define OTGHS_EPTYPE_CTRL (0) /* Control */ +#define OTGHS_EPTYPE_ISOC (1) /* Isochronous */ +#define OTGHS_EPTYPE_BULK (2) /* Bulk */ +#define OTGHS_EPTYPE_INTR (3) /* Interrupt */ + +#define OTGHS_PID_DATA0 (0) +#define OTGHS_PID_DATA2 (1) +#define OTGHS_PID_DATA1 (2) +#define OTGHS_PID_MDATA (3) /* Non-control */ +#define OTGHS_PID_SETUP (3) /* Control */ + +/* Register Offsets *********************************************************/ + +/* Core global control and status registers */ + +#define STM32_OTGHS_GOTGCTL_OFFSET 0x0000 /* Control and status register */ +#define STM32_OTGHS_GOTGINT_OFFSET 0x0004 /* Interrupt register */ +#define STM32_OTGHS_GAHBCFG_OFFSET 0x0008 /* AHB configuration register */ +#define STM32_OTGHS_GUSBCFG_OFFSET 0x000c /* USB configuration register */ +#define STM32_OTGHS_GRSTCTL_OFFSET 0x0010 /* Reset register */ +#define STM32_OTGHS_GINTSTS_OFFSET 0x0014 /* Core interrupt register */ +#define STM32_OTGHS_GINTMSK_OFFSET 0x0018 /* Interrupt mask register */ +#define STM32_OTGHS_GRXSTSR_OFFSET 0x001c /* Receive status debug read/OTG status read register */ +#define STM32_OTGHS_GRXSTSP_OFFSET 0x0020 /* Receive status debug read/OTG status pop register */ +#define STM32_OTGHS_GRXFSIZ_OFFSET 0x0024 /* Receive FIFO size register */ +#define STM32_OTGHS_HNPTXFSIZ_OFFSET 0x0028 /* Host non-periodic transmit FIFO size register */ +#define STM32_OTGHS_DIEPTXF0_OFFSET 0x0028 /* Endpoint 0 Transmit FIFO size */ +#define STM32_OTGHS_HNPTXSTS_OFFSET 0x002c /* Non-periodic transmit FIFO/queue status register */ +#define STM32_OTGHS_GCCFG_OFFSET 0x0038 /* general core configuration register */ +#define STM32_OTGHS_CID_OFFSET 0x003c /* Core ID register */ +#define STM32_OTGHS_HPTXFSIZ_OFFSET 0x0100 /* Host periodic transmit FIFO size register */ + +#define STM32_OTGHS_DIEPTXF_OFFSET(n) (0x0104+(((n)-1) << 2)) +#define STM32_OTGHS_DIEPTXF1_OFFSET 0x0104 /* Device IN endpoint transmit FIFO1 size register */ +#define STM32_OTGHS_DIEPTXF2_OFFSET 0x0108 /* Device IN endpoint transmit FIFO2 size register */ +#define STM32_OTGHS_DIEPTXF3_OFFSET 0x010c /* Device IN endpoint transmit FIFO3 size register */ + +/* Host-mode control and status registers */ + +#define STM32_OTGHS_HCFG_OFFSET 0x0400 /* Host configuration register */ +#define STM32_OTGHS_HFIR_OFFSET 0x0404 /* Host frame interval register */ +#define STM32_OTGHS_HFNUM_OFFSET 0x0408 /* Host frame number/frame time remaining register */ +#define STM32_OTGHS_HPTXSTS_OFFSET 0x0410 /* Host periodic transmit FIFO/queue status register */ +#define STM32_OTGHS_HAINT_OFFSET 0x0414 /* Host all channels interrupt register */ +#define STM32_OTGHS_HAINTMSK_OFFSET 0x0418 /* Host all channels interrupt mask register */ +#define STM32_OTGHS_HPRT_OFFSET 0x0440 /* Host port control and status register */ + +#define STM32_OTGHS_CHAN_OFFSET(n) (0x500 + ((n) << 5) +#define STM32_OTGHS_HCCHAR_CHOFFSET 0x0000 /* Host channel characteristics register */ +#define STM32_OTGHS_HCINT_CHOFFSET 0x0008 /* Host channel interrupt register */ +#define STM32_OTGHS_HCINTMSK_CHOFFSET 0x000c /* Host channel interrupt mask register */ +#define STM32_OTGHS_HCTSIZ_CHOFFSET 0x0010 /* Host channel interrupt register */ + +#define STM32_OTGHS_HCCHAR_OFFSET(n) (0x500 + ((n) << 5)) +#define STM32_OTGHS_HCCHAR0_OFFSET 0x0500 /* Host channel-0 characteristics register */ +#define STM32_OTGHS_HCCHAR1_OFFSET 0x0520 /* Host channel-1 characteristics register */ +#define STM32_OTGHS_HCCHAR2_OFFSET 0x0540 /* Host channel-2 characteristics register */ +#define STM32_OTGHS_HCCHAR3_OFFSET 0x0560 /* Host channel-3 characteristics register */ +#define STM32_OTGHS_HCCHAR4_OFFSET 0x0580 /* Host channel-4 characteristics register */ +#define STM32_OTGHS_HCCHAR5_OFFSET 0x05a0 /* Host channel-5 characteristics register */ +#define STM32_OTGHS_HCCHAR6_OFFSET 0x05c0 /* Host channel-6 characteristics register */ +#define STM32_OTGHS_HCCHAR7_OFFSET 0x05e0 /* Host channel-7 characteristics register */ +#define STM32_OTGHS_HCCHAR8_OFFSET 0x0600 /* Host channel-8 characteristics register */ +#define STM32_OTGHS_HCCHAR9_OFFSET 0x0620 /* Host channel-9 characteristics register */ +#define STM32_OTGHS_HCCHAR10_OFFSET 0x0640 /* Host channel-10 characteristics register */ +#define STM32_OTGHS_HCCHAR11_OFFSET 0x0660 /* Host channel-11 characteristics register */ + +#define STM32_OTGHS_HCINT_OFFSET(n) (0x508 + ((n) << 5)) +#define STM32_OTGHS_HCINT0_OFFSET 0x0508 /* Host channel-0 interrupt register */ +#define STM32_OTGHS_HCINT1_OFFSET 0x0528 /* Host channel-1 interrupt register */ +#define STM32_OTGHS_HCINT2_OFFSET 0x0548 /* Host channel-2 interrupt register */ +#define STM32_OTGHS_HCINT3_OFFSET 0x0568 /* Host channel-3 interrupt register */ +#define STM32_OTGHS_HCINT4_OFFSET 0x0588 /* Host channel-4 interrupt register */ +#define STM32_OTGHS_HCINT5_OFFSET 0x05a8 /* Host channel-5 interrupt register */ +#define STM32_OTGHS_HCINT6_OFFSET 0x05c8 /* Host channel-6 interrupt register */ +#define STM32_OTGHS_HCINT7_OFFSET 0x05e8 /* Host channel-7 interrupt register */ +#define STM32_OTGHS_HCINT8_OFFSET 0x0608 /* Host channel-8 interrupt register */ +#define STM32_OTGHS_HCINT9_OFFSET 0x0628 /* Host channel-9 interrupt register */ +#define STM32_OTGHS_HCINT10_OFFSET 0x0648 /* Host channel-10 interrupt register */ +#define STM32_OTGHS_HCINT11_OFFSET 0x0668 /* Host channel-11 interrupt register */ + +#define STM32_OTGHS_HCINTMSK_OFFSET(n) (0x50c + ((n) << 5)) +#define STM32_OTGHS_HCINTMSK0_OFFSET 0x050c /* Host channel-0 interrupt mask register */ +#define STM32_OTGHS_HCINTMSK1_OFFSET 0x052c /* Host channel-1 interrupt mask register */ +#define STM32_OTGHS_HCINTMSK2_OFFSET 0x054c /* Host channel-2 interrupt mask register */ +#define STM32_OTGHS_HCINTMSK3_OFFSET 0x056c /* Host channel-3 interrupt mask register */ +#define STM32_OTGHS_HCINTMSK4_OFFSET 0x058c /* Host channel-4 interrupt mask register */ +#define STM32_OTGHS_HCINTMSK5_OFFSET 0x05ac /* Host channel-5 interrupt mask register */ +#define STM32_OTGHS_HCINTMSK6_OFFSET 0x05cc /* Host channel-6 interrupt mask register */ +#define STM32_OTGHS_HCINTMSK7_OFFSET 0x05ec /* Host channel-7 interrupt mask register */ +#define STM32_OTGHS_HCINTMSK8_OFFSET 0x060c /* Host channel-8 interrupt mask register */ +#define STM32_OTGHS_HCINTMSK9_OFFSET 0x062c /* Host channel-9 interrupt mask register */ +#define STM32_OTGHS_HCINTMSK10_OFFSET 0x064c /* Host channel-10 interrupt mask register */ +#define STM32_OTGHS_HCINTMSK11_OFFSET 0x068c /* Host channel-11 interrupt mask register */ + +#define STM32_OTGHS_HCTSIZ_OFFSET(n) (0x510 + ((n) << 5)) +#define STM32_OTGHS_HCTSIZ0_OFFSET 0x0510 /* Host channel-0 interrupt register */ +#define STM32_OTGHS_HCTSIZ1_OFFSET 0x0530 /* Host channel-1 interrupt register */ +#define STM32_OTGHS_HCTSIZ2_OFFSET 0x0550 /* Host channel-2 interrupt register */ +#define STM32_OTGHS_HCTSIZ3_OFFSET 0x0570 /* Host channel-3 interrupt register */ +#define STM32_OTGHS_HCTSIZ4_OFFSET 0x0590 /* Host channel-4 interrupt register */ +#define STM32_OTGHS_HCTSIZ5_OFFSET 0x05b0 /* Host channel-5 interrupt register */ +#define STM32_OTGHS_HCTSIZ6_OFFSET 0x05d0 /* Host channel-6 interrupt register */ +#define STM32_OTGHS_HCTSIZ7_OFFSET 0x06f0 /* Host channel-7 interrupt register */ +#define STM32_OTGHS_HCTSIZ8_OFFSET 0x0610 /* Host channel-8 interrupt register */ +#define STM32_OTGHS_HCTSIZ9_OFFSET 0x0630 /* Host channel-9 interrupt register */ +#define STM32_OTGHS_HCTSIZ10_OFFSET 0x0650 /* Host channel-10 interrupt register */ +#define STM32_OTGHS_HCTSIZ11_OFFSET 0x05f0 /* Host channel-11 interrupt register */ + +/* Device-mode control and status registers */ + +#define STM32_OTGHS_DCFG_OFFSET 0x0800 /* Device configuration register */ +#define STM32_OTGHS_DCTL_OFFSET 0x0804 /* Device control register */ +#define STM32_OTGHS_DSTS_OFFSET 0x0808 /* Device status register */ +#define STM32_OTGHS_DIEPMSK_OFFSET 0x0810 /* Device IN endpoint common interrupt mask register */ +#define STM32_OTGHS_DOEPMSK_OFFSET 0x0814 /* Device OUT endpoint common interrupt mask register */ +#define STM32_OTGHS_DAINT_OFFSET 0x0818 /* Device all endpoints interrupt register */ +#define STM32_OTGHS_DAINTMSK_OFFSET 0x081c /* All endpoints interrupt mask register */ +#define STM32_OTGHS_DVBUSDIS_OFFSET 0x0828 /* Device VBUS discharge time register */ +#define STM32_OTGHS_DVBUSPULSE_OFFSET 0x082c /* Device VBUS pulsing time register */ +#define STM32_OTGHS_DIEPEMPMSK_OFFSET 0x0834 /* Device IN endpoint FIFO empty interrupt mask register */ + +#define STM32_OTGHS_DIEP_OFFSET(n) (0x0900 + ((n) << 5)) +#define STM32_OTGHS_DIEPCTL_EPOFFSET 0x0000 /* Device endpoint control register */ +#define STM32_OTGHS_DIEPINT_EPOFFSET 0x0008 /* Device endpoint interrupt register */ +#define STM32_OTGHS_DIEPTSIZ_EPOFFSET 0x0010 /* Device IN endpoint transfer size register */ +#define STM32_OTGHS_DTXFSTS_EPOFFSET 0x0018 /* Device IN endpoint transmit FIFO status register */ + +#define STM32_OTGHS_DIEPCTL_OFFSET(n) (0x0900 + ((n) << 5)) +#define STM32_OTGHS_DIEPCTL0_OFFSET 0x0900 /* Device control IN endpoint 0 control register */ +#define STM32_OTGHS_DIEPCTL1_OFFSET 0x0920 /* Device control IN endpoint 2 control register */ +#define STM32_OTGHS_DIEPCTL2_OFFSET 0x0940 /* Device control IN endpoint 3 control register */ +#define STM32_OTGHS_DIEPCTL3_OFFSET 0x0960 /* Device control IN endpoint 4 control register */ + +#define STM32_OTGHS_DIEPINT_OFFSET(n) (0x0908 + ((n) << 5)) +#define STM32_OTGHS_DIEPINT0_OFFSET 0x0908 /* Device endpoint-0 interrupt register */ +#define STM32_OTGHS_DIEPINT1_OFFSET 0x0928 /* Device endpoint-1 interrupt register */ +#define STM32_OTGHS_DIEPINT2_OFFSET 0x0948 /* Device endpoint-2 interrupt register */ +#define STM32_OTGHS_DIEPINT3_OFFSET 0x0968 /* Device endpoint-3 interrupt register */ + +#define STM32_OTGHS_DIEPTSIZ_OFFSET(n) (0x910 + ((n) << 5)) +#define STM32_OTGHS_DIEPTSIZ0_OFFSET 0x0910 /* Device IN endpoint 0 transfer size register */ +#define STM32_OTGHS_DIEPTSIZ1_OFFSET 0x0930 /* Device IN endpoint 1 transfer size register */ +#define STM32_OTGHS_DIEPTSIZ2_OFFSET 0x0950 /* Device IN endpoint 2 transfer size register */ +#define STM32_OTGHS_DIEPTSIZ3_OFFSET 0x0970 /* Device IN endpoint 3 transfer size register */ + +#define STM32_OTGHS_DTXFSTS_OFFSET(n) (0x0918 + ((n) << 5)) +#define STM32_OTGHS_DTXFSTS0_OFFSET 0x0918 /* Device OUT endpoint-0 TxFIFO status register */ +#define STM32_OTGHS_DTXFSTS1_OFFSET 0x0938 /* Device OUT endpoint-1 TxFIFO status register */ +#define STM32_OTGHS_DTXFSTS2_OFFSET 0x0958 /* Device OUT endpoint-2 TxFIFO status register */ +#define STM32_OTGHS_DTXFSTS3_OFFSET 0x0978 /* Device OUT endpoint-3 TxFIFO status register */ + +#define STM32_OTGHS_DOEP_OFFSET(n) (0x0b00 + ((n) << 5)) +#define STM32_OTGHS_DOEPCTL_EPOFFSET 0x0000 /* Device control OUT endpoint 0 control register */ +#define STM32_OTGHS_DOEPINT_EPOFFSET 0x0008 /* Device endpoint-x interrupt register */ + +#define STM32_OTGHS_DOEPCTL_OFFSET(n) (0x0b00 + ((n) << 5)) +#define STM32_OTGHS_DOEPCTL0_OFFSET 0x00b00 /* Device OUT endpoint 0 control register */ +#define STM32_OTGHS_DOEPCTL1_OFFSET 0x00b20 /* Device OUT endpoint 1 control register */ +#define STM32_OTGHS_DOEPCTL2_OFFSET 0x00b40 /* Device OUT endpoint 2 control register */ +#define STM32_OTGHS_DOEPCTL3_OFFSET 0x00b60 /* Device OUT endpoint 3 control register */ + +#define STM32_OTGHS_DOEPINT_OFFSET(n) (0x0b08 + ((n) << 5)) +#define STM32_OTGHS_DOEPINT0_OFFSET 0x00b08 /* Device endpoint-0 interrupt register */ +#define STM32_OTGHS_DOEPINT1_OFFSET 0x00b28 /* Device endpoint-1 interrupt register */ +#define STM32_OTGHS_DOEPINT2_OFFSET 0x00b48 /* Device endpoint-2 interrupt register */ +#define STM32_OTGHS_DOEPINT3_OFFSET 0x00b68 /* Device endpoint-3 interrupt register */ + +#define STM32_OTGHS_DOEPTSIZ_OFFSET(n) (0x0b10 + ((n) << 5)) +#define STM32_OTGHS_DOEPTSIZ0_OFFSET 0x00b10 /* Device OUT endpoint-0 transfer size register */ +#define STM32_OTGHS_DOEPTSIZ1_OFFSET 0x00b30 /* Device OUT endpoint-1 transfer size register */ +#define STM32_OTGHS_DOEPTSIZ2_OFFSET 0x00b50 /* Device OUT endpoint-2 transfer size register */ +#define STM32_OTGHS_DOEPTSIZ3_OFFSET 0x00b70 /* Device OUT endpoint-3 transfer size register */ + +/* Power and clock gating registers */ + +#define STM32_OTGHS_PCGCCTL_OFFSET 0x0e00 /* Power and clock gating control register */ + +/* Data FIFO (DFIFO) access registers */ + +#define STM32_OTGHS_DFIFO_DEP_OFFSET(n) (0x1000 + ((n) << 12)) +#define STM32_OTGHS_DFIFO_HCH_OFFSET(n) (0x1000 + ((n) << 12)) + +#define STM32_OTGHS_DFIFO_DEP0_OFFSET 0x1000 /* 0x1000-0x1ffc Device IN/OUT Endpoint 0 DFIFO Write/Read Access */ +#define STM32_OTGHS_DFIFO_HCH0_OFFSET 0x1000 /* 0x1000-0x1ffc Host OUT/IN Channel 0 DFIFO Read/Write Access */ + +#define STM32_OTGHS_DFIFO_DEP1_OFFSET 0x2000 /* 0x2000-0x2ffc Device IN/OUT Endpoint 1 DFIFO Write/Read Access */ +#define STM32_OTGHS_DFIFO_HCH1_OFFSET 0x2000 /* 0x2000-0x2ffc Host OUT/IN Channel 1 DFIFO Read/Write Access */ + +#define STM32_OTGHS_DFIFO_DEP2_OFFSET 0x3000 /* 0x3000-0x3ffc Device IN/OUT Endpoint 2 DFIFO Write/Read Access */ +#define STM32_OTGHS_DFIFO_HCH2_OFFSET 0x3000 /* 0x3000-0x3ffc Host OUT/IN Channel 2 DFIFO Read/Write Access */ + +#define STM32_OTGHS_DFIFO_DEP3_OFFSET 0x4000 /* 0x4000-0x4ffc Device IN/OUT Endpoint 3 DFIFO Write/Read Access */ +#define STM32_OTGHS_DFIFO_HCH3_OFFSET 0x4000 /* 0x4000-0x4ffc Host OUT/IN Channel 3 DFIFO Read/Write Access */ + +/* Register Addresses *******************************************************/ + +#define STM32_OTGHS_GOTGCTL (STM32_OTGHS_BASE+STM32_OTGHS_GOTGCTL_OFFSET) +#define STM32_OTGHS_GOTGINT (STM32_OTGHS_BASE+STM32_OTGHS_GOTGINT_OFFSET) +#define STM32_OTGHS_GAHBCFG (STM32_OTGHS_BASE+STM32_OTGHS_GAHBCFG_OFFSET) +#define STM32_OTGHS_GUSBCFG (STM32_OTGHS_BASE+STM32_OTGHS_GUSBCFG_OFFSET) +#define STM32_OTGHS_GRSTCTL (STM32_OTGHS_BASE+STM32_OTGHS_GRSTCTL_OFFSET) +#define STM32_OTGHS_GINTSTS (STM32_OTGHS_BASE+STM32_OTGHS_GINTSTS_OFFSET) +#define STM32_OTGHS_GINTMSK (STM32_OTGHS_BASE+STM32_OTGHS_GINTMSK_OFFSET) +#define STM32_OTGHS_GRXSTSR (STM32_OTGHS_BASE+STM32_OTGHS_GRXSTSR_OFFSET) +#define STM32_OTGHS_GRXSTSP (STM32_OTGHS_BASE+STM32_OTGHS_GRXSTSP_OFFSET) +#define STM32_OTGHS_GRXFSIZ (STM32_OTGHS_BASE+STM32_OTGHS_GRXFSIZ_OFFSET) +#define STM32_OTGHS_HNPTXFSIZ (STM32_OTGHS_BASE+STM32_OTGHS_HNPTXFSIZ_OFFSET) +#define STM32_OTGHS_DIEPTXF0 (STM32_OTGHS_BASE+STM32_OTGHS_DIEPTXF0_OFFSET) +#define STM32_OTGHS_HNPTXSTS (STM32_OTGHS_BASE+STM32_OTGHS_HNPTXSTS_OFFSET) +#define STM32_OTGHS_GCCFG (STM32_OTGHS_BASE+STM32_OTGHS_GCCFG_OFFSET) +#define STM32_OTGHS_CID (STM32_OTGHS_BASE+STM32_OTGHS_CID_OFFSET) +#define STM32_OTGHS_HPTXFSIZ (STM32_OTGHS_BASE+STM32_OTGHS_HPTXFSIZ_OFFSET) + +#define STM32_OTGHS_DIEPTXF(n) (STM32_OTGHS_BASE+STM32_OTGHS_DIEPTXF_OFFSET(n)) +#define STM32_OTGHS_DIEPTXF1 (STM32_OTGHS_BASE+STM32_OTGHS_DIEPTXF1_OFFSET) +#define STM32_OTGHS_DIEPTXF2 (STM32_OTGHS_BASE+STM32_OTGHS_DIEPTXF2_OFFSET) +#define STM32_OTGHS_DIEPTXF3 (STM32_OTGHS_BASE+STM32_OTGHS_DIEPTXF3_OFFSET) + +/* Host-mode control and status registers */ + +#define STM32_OTGHS_HCFG (STM32_OTGHS_BASE+STM32_OTGHS_HCFG_OFFSET) +#define STM32_OTGHS_HFIR (STM32_OTGHS_BASE+STM32_OTGHS_HFIR_OFFSET) +#define STM32_OTGHS_HFNUM (STM32_OTGHS_BASE+STM32_OTGHS_HFNUM_OFFSET) +#define STM32_OTGHS_HPTXSTS (STM32_OTGHS_BASE+STM32_OTGHS_HPTXSTS_OFFSET) +#define STM32_OTGHS_HAINT (STM32_OTGHS_BASE+STM32_OTGHS_HAINT_OFFSET) +#define STM32_OTGHS_HAINTMSK (STM32_OTGHS_BASE+STM32_OTGHS_HAINTMSK_OFFSET) +#define STM32_OTGHS_HPRT (STM32_OTGHS_BASE+STM32_OTGHS_HPRT_OFFSET) + +#define STM32_OTGHS_CHAN(n) (STM32_OTGHS_BASE+STM32_OTGHS_CHAN_OFFSET(n)) + +#define STM32_OTGHS_HCCHAR(n) (STM32_OTGHS_BASE+STM32_OTGHS_HCCHAR_OFFSET(n)) +#define STM32_OTGHS_HCCHAR0 (STM32_OTGHS_BASE+STM32_OTGHS_HCCHAR0_OFFSET) +#define STM32_OTGHS_HCCHAR1 (STM32_OTGHS_BASE+STM32_OTGHS_HCCHAR1_OFFSET) +#define STM32_OTGHS_HCCHAR2 (STM32_OTGHS_BASE+STM32_OTGHS_HCCHAR2_OFFSET) +#define STM32_OTGHS_HCCHAR3 (STM32_OTGHS_BASE+STM32_OTGHS_HCCHAR3_OFFSET) +#define STM32_OTGHS_HCCHAR4 (STM32_OTGHS_BASE+STM32_OTGHS_HCCHAR4_OFFSET) +#define STM32_OTGHS_HCCHAR5 (STM32_OTGHS_BASE+STM32_OTGHS_HCCHAR5_OFFSET) +#define STM32_OTGHS_HCCHAR6 (STM32_OTGHS_BASE+STM32_OTGHS_HCCHAR6_OFFSET) +#define STM32_OTGHS_HCCHAR7 (STM32_OTGHS_BASE+STM32_OTGHS_HCCHAR7_OFFSET) +#define STM32_OTGHS_HCCHAR8 (STM32_OTGHS_BASE+STM32_OTGHS_HCCHAR8_OFFSET) +#define STM32_OTGHS_HCCHAR9 (STM32_OTGHS_BASE+STM32_OTGHS_HCCHAR9_OFFSET) +#define STM32_OTGHS_HCCHAR10 (STM32_OTGHS_BASE+STM32_OTGHS_HCCHAR10_OFFSET) +#define STM32_OTGHS_HCCHAR11 (STM32_OTGHS_BASE+STM32_OTGHS_HCCHAR11_OFFSET) + +#define STM32_OTGHS_HCINT(n) (STM32_OTGHS_BASE+STM32_OTGHS_HCINT_OFFSET(n)) +#define STM32_OTGHS_HCINT0 (STM32_OTGHS_BASE+STM32_OTGHS_HCINT0_OFFSET) +#define STM32_OTGHS_HCINT1 (STM32_OTGHS_BASE+STM32_OTGHS_HCINT1_OFFSET) +#define STM32_OTGHS_HCINT2 (STM32_OTGHS_BASE+STM32_OTGHS_HCINT2_OFFSET) +#define STM32_OTGHS_HCINT3 (STM32_OTGHS_BASE+STM32_OTGHS_HCINT3_OFFSET) +#define STM32_OTGHS_HCINT4 (STM32_OTGHS_BASE+STM32_OTGHS_HCINT4_OFFSET) +#define STM32_OTGHS_HCINT5 (STM32_OTGHS_BASE+STM32_OTGHS_HCINT5_OFFSET) +#define STM32_OTGHS_HCINT6 (STM32_OTGHS_BASE+STM32_OTGHS_HCINT6_OFFSET) +#define STM32_OTGHS_HCINT7 (STM32_OTGHS_BASE+STM32_OTGHS_HCINT7_OFFSET) +#define STM32_OTGHS_HCINT8 (STM32_OTGHS_BASE+STM32_OTGHS_HCINT8_OFFSET) +#define STM32_OTGHS_HCINT9 (STM32_OTGHS_BASE+STM32_OTGHS_HCINT9_OFFSET) +#define STM32_OTGHS_HCINT10 (STM32_OTGHS_BASE+STM32_OTGHS_HCINT10_OFFSET) +#define STM32_OTGHS_HCINT11 (STM32_OTGHS_BASE+STM32_OTGHS_HCINT11_OFFSET) + +#define STM32_OTGHS_HCINTMSK(n) (STM32_OTGHS_BASE+STM32_OTGHS_HCINTMSK_OFFSET(n)) +#define STM32_OTGHS_HCINTMSK0 (STM32_OTGHS_BASE+STM32_OTGHS_HCINTMSK0_OFFSET) +#define STM32_OTGHS_HCINTMSK1 (STM32_OTGHS_BASE+STM32_OTGHS_HCINTMSK1_OFFSET) +#define STM32_OTGHS_HCINTMSK2 (STM32_OTGHS_BASE+STM32_OTGHS_HCINTMSK2_OFFSET) +#define STM32_OTGHS_HCINTMSK3 (STM32_OTGHS_BASE+STM32_OTGHS_HCINTMSK3_OFFSET) +#define STM32_OTGHS_HCINTMSK4 (STM32_OTGHS_BASE+STM32_OTGHS_HCINTMSK4_OFFSET) +#define STM32_OTGHS_HCINTMSK5 (STM32_OTGHS_BASE+STM32_OTGHS_HCINTMSK5_OFFSET) +#define STM32_OTGHS_HCINTMSK6 (STM32_OTGHS_BASE+STM32_OTGHS_HCINTMSK6_OFFSET) +#define STM32_OTGHS_HCINTMSK7 (STM32_OTGHS_BASE+STM32_OTGHS_HCINTMSK7_OFFSET) +#define STM32_OTGHS_HCINTMSK8 (STM32_OTGHS_BASE+STM32_OTGHS_HCINTMSK8_OFFSET) +#define STM32_OTGHS_HCINTMSK9 (STM32_OTGHS_BASE+STM32_OTGHS_HCINTMSK9_OFFSET) +#define STM32_OTGHS_HCINTMSK10 (STM32_OTGHS_BASE+STM32_OTGHS_HCINTMSK10_OFFSET) +#define STM32_OTGHS_HCINTMSK11 (STM32_OTGHS_BASE+STM32_OTGHS_HCINTMSK11_OFFSET) + +#define STM32_OTGHS_HCTSIZ(n) (STM32_OTGHS_BASE+STM32_OTGHS_HCTSIZ_OFFSET(n)) +#define STM32_OTGHS_HCTSIZ0 (STM32_OTGHS_BASE+STM32_OTGHS_HCTSIZ0_OFFSET) +#define STM32_OTGHS_HCTSIZ1 (STM32_OTGHS_BASE+STM32_OTGHS_HCTSIZ1_OFFSET) +#define STM32_OTGHS_HCTSIZ2 (STM32_OTGHS_BASE+STM32_OTGHS_HCTSIZ2_OFFSET) +#define STM32_OTGHS_HCTSIZ3 (STM32_OTGHS_BASE+STM32_OTGHS_HCTSIZ3_OFFSET) +#define STM32_OTGHS_HCTSIZ4 (STM32_OTGHS_BASE+STM32_OTGHS_HCTSIZ4_OFFSET) +#define STM32_OTGHS_HCTSIZ5 (STM32_OTGHS_BASE+STM32_OTGHS_HCTSIZ5_OFFSET) +#define STM32_OTGHS_HCTSIZ6 (STM32_OTGHS_BASE+STM32_OTGHS_HCTSIZ6_OFFSET) +#define STM32_OTGHS_HCTSIZ7 (STM32_OTGHS_BASE+STM32_OTGHS_HCTSIZ7_OFFSET) +#define STM32_OTGHS_HCTSIZ8 (STM32_OTGHS_BASE+STM32_OTGHS_HCTSIZ8_OFFSET) +#define STM32_OTGHS_HCTSIZ9 (STM32_OTGHS_BASE+STM32_OTGHS_HCTSIZ9_OFFSET) +#define STM32_OTGHS_HCTSIZ10 (STM32_OTGHS_BASE+STM32_OTGHS_HCTSIZ10_OFFSET) +#define STM32_OTGHS_HCTSIZ11 (STM32_OTGHS_BASE+STM32_OTGHS_HCTSIZ11_OFFSET) + +/* Device-mode control and status registers */ + +#define STM32_OTGHS_DCFG (STM32_OTGHS_BASE+STM32_OTGHS_DCFG_OFFSET) +#define STM32_OTGHS_DCTL (STM32_OTGHS_BASE+STM32_OTGHS_DCTL_OFFSET) +#define STM32_OTGHS_DSTS (STM32_OTGHS_BASE+STM32_OTGHS_DSTS_OFFSET) +#define STM32_OTGHS_DIEPMSK (STM32_OTGHS_BASE+STM32_OTGHS_DIEPMSK_OFFSET) +#define STM32_OTGHS_DOEPMSK (STM32_OTGHS_BASE+STM32_OTGHS_DOEPMSK_OFFSET) +#define STM32_OTGHS_DAINT (STM32_OTGHS_BASE+STM32_OTGHS_DAINT_OFFSET) +#define STM32_OTGHS_DAINTMSK (STM32_OTGHS_BASE+STM32_OTGHS_DAINTMSK_OFFSET) +#define STM32_OTGHS_DVBUSDIS (STM32_OTGHS_BASE+STM32_OTGHS_DVBUSDIS_OFFSET) +#define STM32_OTGHS_DVBUSPULSE (STM32_OTGHS_BASE+STM32_OTGHS_DVBUSPULSE_OFFSET) +#define STM32_OTGHS_DIEPEMPMSK (STM32_OTGHS_BASE+STM32_OTGHS_DIEPEMPMSK_OFFSET) + +#define STM32_OTGHS_DIEP(n) (STM32_OTGHS_BASE+STM32_OTGHS_DIEP_OFFSET(n)) + +#define STM32_OTGHS_DIEPCTL(n) (STM32_OTGHS_BASE+STM32_OTGHS_DIEPCTL_OFFSET(n)) +#define STM32_OTGHS_DIEPCTL0 (STM32_OTGHS_BASE+STM32_OTGHS_DIEPCTL0_OFFSET) +#define STM32_OTGHS_DIEPCTL1 (STM32_OTGHS_BASE+STM32_OTGHS_DIEPCTL1_OFFSET) +#define STM32_OTGHS_DIEPCTL2 (STM32_OTGHS_BASE+STM32_OTGHS_DIEPCTL2_OFFSET) +#define STM32_OTGHS_DIEPCTL3 (STM32_OTGHS_BASE+STM32_OTGHS_DIEPCTL3_OFFSET) + +#define STM32_OTGHS_DIEPINT(n) (STM32_OTGHS_BASE+STM32_OTGHS_DIEPINT_OFFSET(n)) +#define STM32_OTGHS_DIEPINT0 (STM32_OTGHS_BASE+STM32_OTGHS_DIEPINT0_OFFSET) +#define STM32_OTGHS_DIEPINT1 (STM32_OTGHS_BASE+STM32_OTGHS_DIEPINT1_OFFSET) +#define STM32_OTGHS_DIEPINT2 (STM32_OTGHS_BASE+STM32_OTGHS_DIEPINT2_OFFSET) +#define STM32_OTGHS_DIEPINT3 (STM32_OTGHS_BASE+STM32_OTGHS_DIEPINT3_OFFSET) + +#define STM32_OTGHS_DIEPTSIZ(n) (STM32_OTGHS_BASE+STM32_OTGHS_DIEPTSIZ_OFFSET(n)) +#define STM32_OTGHS_DIEPTSIZ0 (STM32_OTGHS_BASE+STM32_OTGHS_DIEPTSIZ0_OFFSET) +#define STM32_OTGHS_DIEPTSIZ1 (STM32_OTGHS_BASE+STM32_OTGHS_DIEPTSIZ1_OFFSET) +#define STM32_OTGHS_DIEPTSIZ2 (STM32_OTGHS_BASE+STM32_OTGHS_DIEPTSIZ2_OFFSET) +#define STM32_OTGHS_DIEPTSIZ3 (STM32_OTGHS_BASE+STM32_OTGHS_DIEPTSIZ3_OFFSET) + +#define STM32_OTGHS_DTXFSTS(n) (STM32_OTGHS_BASE+STM32_OTGHS_DTXFSTS_OFFSET(n)) +#define STM32_OTGHS_DTXFSTS0 (STM32_OTGHS_BASE+STM32_OTGHS_DTXFSTS0_OFFSET) +#define STM32_OTGHS_DTXFSTS1 (STM32_OTGHS_BASE+STM32_OTGHS_DTXFSTS1_OFFSET) +#define STM32_OTGHS_DTXFSTS2 (STM32_OTGHS_BASE+STM32_OTGHS_DTXFSTS2_OFFSET) +#define STM32_OTGHS_DTXFSTS3 (STM32_OTGHS_BASE+STM32_OTGHS_DTXFSTS3_OFFSET) + +#define STM32_OTGHS_DOEP(n) (STM32_OTGHS_BASE+STM32_OTGHS_DOEP_OFFSET(n)) + +#define STM32_OTGHS_DOEPCTL(n) (STM32_OTGHS_BASE+STM32_OTGHS_DOEPCTL_OFFSET(n)) +#define STM32_OTGHS_DOEPCTL0 (STM32_OTGHS_BASE+STM32_OTGHS_DOEPCTL0_OFFSET) +#define STM32_OTGHS_DOEPCTL1 (STM32_OTGHS_BASE+STM32_OTGHS_DOEPCTL1_OFFSET) +#define STM32_OTGHS_DOEPCTL2 (STM32_OTGHS_BASE+STM32_OTGHS_DOEPCTL2_OFFSET) +#define STM32_OTGHS_DOEPCTL3 (STM32_OTGHS_BASE+STM32_OTGHS_DOEPCTL3_OFFSET) + +#define STM32_OTGHS_DOEPINT(n) (STM32_OTGHS_BASE+STM32_OTGHS_DOEPINT_OFFSET(n)) +#define STM32_OTGHS_DOEPINT0 (STM32_OTGHS_BASE+STM32_OTGHS_DOEPINT0_OFFSET) +#define STM32_OTGHS_DOEPINT1 (STM32_OTGHS_BASE+STM32_OTGHS_DOEPINT1_OFFSET) +#define STM32_OTGHS_DOEPINT2 (STM32_OTGHS_BASE+STM32_OTGHS_DOEPINT2_OFFSET) +#define STM32_OTGHS_DOEPINT3 (STM32_OTGHS_BASE+STM32_OTGHS_DOEPINT3_OFFSET) + +#define STM32_OTGHS_DOEPTSIZ(n) (STM32_OTGHS_BASE+STM32_OTGHS_DOEPTSIZ_OFFSET(n)) +#define STM32_OTGHS_DOEPTSIZ0 (STM32_OTGHS_BASE+STM32_OTGHS_DOEPTSIZ0_OFFSET) +#define STM32_OTGHS_DOEPTSIZ1 (STM32_OTGHS_BASE+STM32_OTGHS_DOEPTSIZ1_OFFSET) +#define STM32_OTGHS_DOEPTSIZ2 (STM32_OTGHS_BASE+STM32_OTGHS_DOEPTSIZ2_OFFSET) +#define STM32_OTGHS_DOEPTSIZ3 (STM32_OTGHS_BASE+STM32_OTGHS_DOEPTSIZ3_OFFSET) + +/* Power and clock gating registers */ + +#define STM32_OTGHS_PCGCCTL (STM32_OTGHS_BASE+STM32_OTGHS_PCGCCTL_OFFSET) + +/* Data FIFO (DFIFO) access registers */ + +#define STM32_OTGHS_DFIFO_DEP(n) (STM32_OTGHS_BASE+STM32_OTGHS_DFIFO_DEP_OFFSET(n)) +#define STM32_OTGHS_DFIFO_HCH(n) (STM32_OTGHS_BASE+STM32_OTGHS_DFIFO_HCH_OFFSET(n)) + +#define STM32_OTGHS_DFIFO_DEP0 (STM32_OTGHS_BASE+STM32_OTGHS_DFIFO_DEP0_OFFSET) +#define STM32_OTGHS_DFIFO_HCH0 (STM32_OTGHS_BASE+STM32_OTGHS_DFIFO_HCH0_OFFSET) + +#define STM32_OTGHS_DFIFO_DEP1 (STM32_OTGHS_BASE+STM32_OTGHS_DFIFO_DEP1_OFFSET) +#define STM32_OTGHS_DFIFO_HCH1 (STM32_OTGHS_BASE+STM32_OTGHS_DFIFO_HCH1_OFFSET) + +#define STM32_OTGHS_DFIFO_DEP2 (STM32_OTGHS_BASE+STM32_OTGHS_DFIFO_DEP2_OFFSET) +#define STM32_OTGHS_DFIFO_HCH2 (STM32_OTGHS_BASE+STM32_OTGHS_DFIFO_HCH2_OFFSET) + +#define STM32_OTGHS_DFIFO_DEP3 (STM32_OTGHS_BASE+STM32_OTGHS_DFIFO_DEP3_OFFSET) +#define STM32_OTGHS_DFIFO_HCH3 (STM32_OTGHS_BASE+STM32_OTGHS_DFIFO_HCH3_OFFSET) + +/* Register Bitfield Definitions ********************************************/ + +/* Core global control and status registers */ + +/* Control and status register */ + +#define OTGHS_GOTGCTL_SRQSCS (1 << 0) /* Bit 0: Session request success */ +#define OTGHS_GOTGCTL_SRQ (1 << 1) /* Bit 1: Session request */ + /* Bits 2-72 Reserved, must be kept at reset value */ +#define OTGHS_GOTGCTL_HNGSCS (1 << 8) /* Bit 8: Host negotiation success */ +#define OTGHS_GOTGCTL_HNPRQ (1 << 9) /* Bit 9: HNP request */ +#define OTGHS_GOTGCTL_HSHNPEN (1 << 10) /* Bit 10: host set HNP enable */ +#define OTGHS_GOTGCTL_DHNPEN (1 << 11) /* Bit 11: Device HNP enabled */ + /* Bits 12-15: Reserved, must be kept at reset value */ +#define OTGHS_GOTGCTL_CIDSTS (1 << 16) /* Bit 16: Connector ID status */ +#define OTGHS_GOTGCTL_DBCT (1 << 17) /* Bit 17: Long/short debounce time */ +#define OTGHS_GOTGCTL_ASVLD (1 << 18) /* Bit 18: A-session valid */ +#define OTGHS_GOTGCTL_BSVLD (1 << 19) /* Bit 19: B-session valid */ + /* Bits 20-31: Reserved, must be kept at reset value */ + +/* Interrupt register */ + +/* Bits 1:0 Reserved, + * must be kept at reset value + */ +#define OTGHS_GOTGINT_SEDET (1 << 2) /* Bit 2: Session end detected */ + /* Bits 3-7: Reserved, must be kept at reset value */ +#define OTGHS_GOTGINT_SRSSCHG (1 << 8) /* Bit 8: Session request success status change */ +#define OTGHS_GOTGINT_HNSSCHG (1 << 9) /* Bit 9: Host negotiation success status change */ + /* Bits 16:10 Reserved, must be kept at reset value */ +#define OTGHS_GOTGINT_HNGDET (1 << 17) /* Bit 17: Host negotiation detected */ +#define OTGHS_GOTGINT_ADTOCHG (1 << 18) /* Bit 18: A-device timeout change */ +#define OTGHS_GOTGINT_DBCDNE (1 << 19) /* Bit 19: Debounce done */ + /* Bits 2-31: Reserved, must be kept at reset value */ + +/* AHB configuration register */ + +#define OTGHS_GAHBCFG_GINTMSK (1 << 0) /* Bit 0: Global interrupt mask */ + /* Bits 1-6: Reserved, must be kept at reset value */ +#define OTGHS_GAHBCFG_TXFELVL (1 << 7) /* Bit 7: TxFIFO empty level */ +#define OTGHS_GAHBCFG_PTXFELVL (1 << 8) /* Bit 8: Periodic TxFIFO empty level */ + /* Bits 20-31: Reserved, must be kept at reset value */ + +/* USB configuration register */ + +#define OTGHS_GUSBCFG_TOCAL_SHIFT (0) /* Bits 0-2: FS timeout calibration */ +#define OTGHS_GUSBCFG_TOCAL_MASK (7 << OTGHS_GUSBCFG_TOCAL_SHIFT) + /* Bits 3-5: Reserved, must be kept at reset value */ +#define OTGHS_GUSBCFG_PHYSEL (1 << 6) /* Bit 6: Full Speed serial transceiver select */ + /* Bit 7: Reserved, must be kept at reset value */ +#define OTGHS_GUSBCFG_SRPCAP (1 << 8) /* Bit 8: SRP-capable */ +#define OTGHS_GUSBCFG_HNPCAP (1 << 9) /* Bit 9: HNP-capable */ +#define OTGHS_GUSBCFG_TRDT_SHIFT (10) /* Bits 10-13: USB turnaround time */ +#define OTGHS_GUSBCFG_TRDT_MASK (15 << OTGHS_GUSBCFG_TRDT_SHIFT) +# define OTGHS_GUSBCFG_TRDT(n) ((n) << OTGHS_GUSBCFG_TRDT_SHIFT) + /* Bits 14-28: Reserved, must be kept at reset value */ +#define OTGHS_GUSBCFG_FHMOD (1 << 29) /* Bit 29: Force host mode */ +#define OTGHS_GUSBCFG_FDMOD (1 << 30) /* Bit 30: Force device mode */ +#define OTGHS_GUSBCFG_CTXPKT (1 << 31) /* Bit 31: Corrupt Tx packet */ + /* Bits 20-31: Reserved, must be kept at reset value */ + +/* Reset register */ + +#define OTGHS_GRSTCTL_CSRST (1 << 0) /* Bit 0: Core soft reset */ +#define OTGHS_GRSTCTL_HSRST (1 << 1) /* Bit 1: HCLK soft reset */ +#define OTGHS_GRSTCTL_FCRST (1 << 2) /* Bit 2: Host frame counter reset */ + /* Bit 3 Reserved, must be kept at reset value */ +#define OTGHS_GRSTCTL_RXFFLSH (1 << 4) /* Bit 4: RxFIFO flush */ +#define OTGHS_GRSTCTL_TXFFLSH (1 << 5) /* Bit 5: TxFIFO flush */ +#define OTGHS_GRSTCTL_TXFNUM_SHIFT (10) /* Bits 6-10: TxFIFO number */ +#define OTGHS_GRSTCTL_TXFNUM_MASK (31 << OTGHS_GRSTCTL_TXFNUM_SHIFT) +# define OTGHS_GRSTCTL_TXFNUM_HNONPER (0 << OTGHS_GRSTCTL_TXFNUM_SHIFT) /* Non-periodic TxFIFO flush in host mode */ +# define OTGHS_GRSTCTL_TXFNUM_HPER (1 << OTGHS_GRSTCTL_TXFNUM_SHIFT) /* Periodic TxFIFO flush in host mode */ +# define OTGHS_GRSTCTL_TXFNUM_HALL (16 << OTGHS_GRSTCTL_TXFNUM_SHIFT) /* Flush all the transmit FIFOs in host mode.*/ +# define OTGHS_GRSTCTL_TXFNUM_D(n) ((n) << OTGHS_GRSTCTL_TXFNUM_SHIFT) /* TXFIFO n flush in device mode, n=0-15 */ +# define OTGHS_GRSTCTL_TXFNUM_DALL (16 << OTGHS_GRSTCTL_TXFNUM_SHIFT) /* Flush all the transmit FIFOs in device mode.*/ + +/* Bits 11-31: Reserved, + * must be kept at reset value + */ +#define OTGHS_GRSTCTL_AHBIDL (1 << 31) /* Bit 31: AHB master idle */ + +/* Core interrupt and Interrupt mask registers */ + +#define OTGHS_GINTSTS_CMOD (1 << 0) /* Bit 0: Current mode of operation */ +# define OTGHS_GINTSTS_DEVMODE (0) +# define OTGHS_GINTSTS_HOSTMODE (OTGHS_GINTSTS_CMOD) +#define OTGHS_GINT_MMIS (1 << 1) /* Bit 1: Mode mismatch interrupt */ +#define OTGHS_GINT_OTG (1 << 2) /* Bit 2: OTG interrupt */ +#define OTGHS_GINT_SOF (1 << 3) /* Bit 3: Start of frame */ +#define OTGHS_GINT_RXFLVL (1 << 4) /* Bit 4: RxFIFO non-empty */ +#define OTGHS_GINT_NPTXFE (1 << 5) /* Bit 5: Non-periodic TxFIFO empty */ +#define OTGHS_GINT_GINAKEFF (1 << 6) /* Bit 6: Global IN non-periodic NAK effective */ +#define OTGHS_GINT_GONAKEFF (1 << 7) /* Bit 7: Global OUT NAK effective */ + /* Bits 8-9: Reserved, must be kept at reset value */ +#define OTGHS_GINT_ESUSP (1 << 10) /* Bit 10: Early suspend */ +#define OTGHS_GINT_USBSUSP (1 << 11) /* Bit 11: USB suspend */ +#define OTGHS_GINT_USBRST (1 << 12) /* Bit 12: USB reset */ +#define OTGHS_GINT_ENUMDNE (1 << 13) /* Bit 13: Enumeration done */ +#define OTGHS_GINT_ISOODRP (1 << 14) /* Bit 14: Isochronous OUT packet dropped interrupt */ +#define OTGHS_GINT_EOPF (1 << 15) /* Bit 15: End of periodic frame interrupt */ + /* Bits 16 Reserved, must be kept at reset value */ +#define OTGHS_GINTMSK_EPMISM (1 << 17) /* Bit 17: Endpoint mismatch interrupt mask */ +#define OTGHS_GINT_IEP (1 << 18) /* Bit 18: IN endpoint interrupt */ +#define OTGHS_GINT_OEP (1 << 19) /* Bit 19: OUT endpoint interrupt */ +#define OTGHS_GINT_IISOIXFR (1 << 20) /* Bit 20: Incomplete isochronous IN transfer */ +#define OTGHS_GINT_IISOOXFR (1 << 21) /* Bit 21: Incomplete isochronous OUT transfer */ +#define OTGHS_GINT_IPXFR (1 << 21) /* Bit 21: Incomplete periodic transfer (host) */ + /* Bits 22-23: Reserved, must be kept at reset value */ +#define OTGHS_GINT_HPRT (1 << 24) /* Bit 24: Host port interrupt */ +#define OTGHS_GINT_HC (1 << 25) /* Bit 25: Host channels interrupt */ +#define OTGHS_GINT_PTXFE (1 << 26) /* Bit 26: Periodic TxFIFO empty */ + /* Bit 27 Reserved, must be kept at reset value */ +#define OTGHS_GINT_CIDSCHG (1 << 28) /* Bit 28: Connector ID status change */ +#define OTGHS_GINT_DISC (1 << 29) /* Bit 29: Disconnect detected interrupt */ +#define OTGHS_GINT_SRQ (1 << 30) /* Bit 30: Session request/new session detected interrupt */ +#define OTGHS_GINT_WKUP (1 << 31) /* Bit 31: Resume/remote wakeup detected interrupt */ + +/* Receive status debug read/OTG status read and pop registers (host mode) */ + +#define OTGHS_GRXSTSH_CHNUM_SHIFT (0) /* Bits 0-3: Channel number */ +#define OTGHS_GRXSTSH_CHNUM_MASK (15 << OTGHS_GRXSTSH_CHNUM_SHIFT) +#define OTGHS_GRXSTSH_BCNT_SHIFT (4) /* Bits 4-14: Byte count */ +#define OTGHS_GRXSTSH_BCNT_MASK (0x7ff << OTGHS_GRXSTSH_BCNT_SHIFT) +#define OTGHS_GRXSTSH_DPID_SHIFT (15) /* Bits 15-16: Data PID */ +#define OTGHS_GRXSTSH_DPID_MASK (3 << OTGHS_GRXSTSH_DPID_SHIFT) +# define OTGHS_GRXSTSH_DPID_DATA0 (0 << OTGHS_GRXSTSH_DPID_SHIFT) +# define OTGHS_GRXSTSH_DPID_DATA2 (1 << OTGHS_GRXSTSH_DPID_SHIFT) +# define OTGHS_GRXSTSH_DPID_DATA1 (2 << OTGHS_GRXSTSH_DPID_SHIFT) +# define OTGHS_GRXSTSH_DPID_MDATA (3 << OTGHS_GRXSTSH_DPID_SHIFT) +#define OTGHS_GRXSTSH_PKTSTS_SHIFT (17) /* Bits 17-20: Packet status */ +#define OTGHS_GRXSTSH_PKTSTS_MASK (15 << OTGHS_GRXSTSH_PKTSTS_SHIFT) +# define OTGHS_GRXSTSH_PKTSTS_INRECVD (2 << OTGHS_GRXSTSH_PKTSTS_SHIFT) /* IN data packet received */ +# define OTGHS_GRXSTSH_PKTSTS_INDONE (3 << OTGHS_GRXSTSH_PKTSTS_SHIFT) /* IN transfer completed */ +# define OTGHS_GRXSTSH_PKTSTS_DTOGERR (5 << OTGHS_GRXSTSH_PKTSTS_SHIFT) /* Data toggle error */ +# define OTGHS_GRXSTSH_PKTSTS_HALTED (7 << OTGHS_GRXSTSH_PKTSTS_SHIFT) /* Channel halted */ + +/* Bits 21-31: Reserved, + * must be kept at reset value + */ + +/* Receive status debug read/OTG status read and pop registers + * (device mode) + */ + +#define OTGHS_GRXSTSD_EPNUM_SHIFT (0) /* Bits 0-3: Endpoint number */ +#define OTGHS_GRXSTSD_EPNUM_MASK (15 << OTGHS_GRXSTSD_EPNUM_SHIFT) +#define OTGHS_GRXSTSD_BCNT_SHIFT (4) /* Bits 4-14: Byte count */ +#define OTGHS_GRXSTSD_BCNT_MASK (0x7ff << OTGHS_GRXSTSD_BCNT_SHIFT) +#define OTGHS_GRXSTSD_DPID_SHIFT (15) /* Bits 15-16: Data PID */ +#define OTGHS_GRXSTSD_DPID_MASK (3 << OTGHS_GRXSTSD_DPID_SHIFT) +# define OTGHS_GRXSTSD_DPID_DATA0 (0 << OTGHS_GRXSTSD_DPID_SHIFT) +# define OTGHS_GRXSTSD_DPID_DATA2 (1 << OTGHS_GRXSTSD_DPID_SHIFT) +# define OTGHS_GRXSTSD_DPID_DATA1 (2 << OTGHS_GRXSTSD_DPID_SHIFT) +# define OTGHS_GRXSTSD_DPID_MDATA (3 << OTGHS_GRXSTSD_DPID_SHIFT) +#define OTGHS_GRXSTSD_PKTSTS_SHIFT (17) /* Bits 17-20: Packet status */ +#define OTGHS_GRXSTSD_PKTSTS_MASK (15 << OTGHS_GRXSTSD_PKTSTS_SHIFT) +# define OTGHS_GRXSTSD_PKTSTS_OUTNAK (1 << OTGHS_GRXSTSD_PKTSTS_SHIFT) /* Global OUT NAK */ +# define OTGHS_GRXSTSD_PKTSTS_OUTRECVD (2 << OTGHS_GRXSTSD_PKTSTS_SHIFT) /* OUT data packet received */ +# define OTGHS_GRXSTSD_PKTSTS_OUTDONE (3 << OTGHS_GRXSTSD_PKTSTS_SHIFT) /* OUT transfer completed */ +# define OTGHS_GRXSTSD_PKTSTS_SETUPDONE (4 << OTGHS_GRXSTSD_PKTSTS_SHIFT) /* SETUP transaction completed */ +# define OTGHS_GRXSTSD_PKTSTS_SETUPRECVD (6 << OTGHS_GRXSTSD_PKTSTS_SHIFT) /* SETUP data packet received */ + +#define OTGHS_GRXSTSD_FRMNUM_SHIFT (21) /* Bits 21-24: Frame number */ +#define OTGHS_GRXSTSD_FRMNUM_MASK (15 << OTGHS_GRXSTSD_FRMNUM_SHIFT) + /* Bits 25-31: Reserved, must be kept at reset value */ + +/* Receive FIFO size register */ + +#define OTGHS_GRXFSIZ_MASK (0xffff) + +/* Host non-periodic transmit FIFO size register */ + +#define OTGHS_HNPTXFSIZ_NPTXFSA_SHIFT (0) /* Bits 0-15: Non-periodic transmit RAM start address */ +#define OTGHS_HNPTXFSIZ_NPTXFSA_MASK (0xffff << OTGHS_HNPTXFSIZ_NPTXFSA_SHIFT) +#define OTGHS_HNPTXFSIZ_NPTXFD_SHIFT (16) /* Bits 16-31: Non-periodic TxFIFO depth */ +#define OTGHS_HNPTXFSIZ_NPTXFD_MASK (0xffff << OTGHS_HNPTXFSIZ_NPTXFD_SHIFT) +# define OTGHS_HNPTXFSIZ_NPTXFD_MIN (16 << OTGHS_HNPTXFSIZ_NPTXFD_SHIFT) +# define OTGHS_HNPTXFSIZ_NPTXFD_MAX (256 << OTGHS_HNPTXFSIZ_NPTXFD_SHIFT) + +/* Endpoint 0 Transmit FIFO size */ + +#define OTGHS_DIEPTXF0_TX0FD_SHIFT (0) /* Bits 0-15: Endpoint 0 transmit RAM start address */ +#define OTGHS_DIEPTXF0_TX0FD_MASK (0xffff << OTGHS_DIEPTXF0_TX0FD_SHIFT) +#define OTGHS_DIEPTXF0_TX0FSA_SHIFT (16) /* Bits 16-31: Endpoint 0 TxFIFO depth */ +#define OTGHS_DIEPTXF0_TX0FSA_MASK (0xffff << OTGHS_DIEPTXF0_TX0FSA_SHIFT) +# define OTGHS_DIEPTXF0_TX0FSA_MIN (16 << OTGHS_DIEPTXF0_TX0FSA_SHIFT) +# define OTGHS_DIEPTXF0_TX0FSA_MAX (256 << OTGHS_DIEPTXF0_TX0FSA_SHIFT) + +/* Non-periodic transmit FIFO/queue status register */ + +#define OTGHS_HNPTXSTS_NPTXFSAV_SHIFT (0) /* Bits 0-15: Non-periodic TxFIFO space available */ +#define OTGHS_HNPTXSTS_NPTXFSAV_MASK (0xffff << OTGHS_HNPTXSTS_NPTXFSAV_SHIFT) +# define OTGHS_HNPTXSTS_NPTXFSAV_FULL (0 << OTGHS_HNPTXSTS_NPTXFSAV_SHIFT) +#define OTGHS_HNPTXSTS_NPTQXSAV_SHIFT (16) /* Bits 16-23: Non-periodic transmit request queue space available */ +#define OTGHS_HNPTXSTS_NPTQXSAV_MASK (0xff << OTGHS_HNPTXSTS_NPTQXSAV_SHIFT) +# define OTGHS_HNPTXSTS_NPTQXSAV_FULL (0 << OTGHS_HNPTXSTS_NPTQXSAV_SHIFT) +#define OTGHS_HNPTXSTS_NPTXQTOP_SHIFT (24) /* Bits 24-30: Top of the non-periodic transmit request queue */ +#define OTGHS_HNPTXSTS_NPTXQTOP_MASK (0x7f << OTGHS_HNPTXSTS_NPTXQTOP_SHIFT) +# define OTGHS_HNPTXSTS_TERMINATE (1 << 24) /* Bit 24: Terminate (last entry for selected channel/endpoint) */ +# define OTGHS_HNPTXSTS_TYPE_SHIFT (25) /* Bits 25-26: Status */ +# define OTGHS_HNPTXSTS_TYPE_MASK (3 << OTGHS_HNPTXSTS_TYPE_SHIFT) +# define OTGHS_HNPTXSTS_TYPE_INOUT (0 << OTGHS_HNPTXSTS_TYPE_SHIFT) /* IN/OUT token */ +# define OTGHS_HNPTXSTS_TYPE_ZLP (1 << OTGHS_HNPTXSTS_TYPE_SHIFT) /* Zero-length transmit packet (device IN/host OUT) */ +# define OTGHS_HNPTXSTS_TYPE_HALT (3 << OTGHS_HNPTXSTS_TYPE_SHIFT) /* Channel halt command */ + +# define OTGHS_HNPTXSTS_CHNUM_SHIFT (27) /* Bits 27-30: Channel number */ +# define OTGHS_HNPTXSTS_CHNUM_MASK (15 << OTGHS_HNPTXSTS_CHNUM_SHIFT) +# define OTGHS_HNPTXSTS_EPNUM_SHIFT (27) /* Bits 27-30: Endpoint number */ +# define OTGHS_HNPTXSTS_EPNUM_MASK (15 << OTGHS_HNPTXSTS_EPNUM_SHIFT) + /* Bit 31 Reserved, must be kept at reset value */ + +/* General core configuration register */ + +/* Bits 15:0 Reserved, + * must be kept at reset value + */ +#define OTGHS_GCCFG_PWRDWN (1 << 16) /* Bit 16: Power down */ + /* Bit 17 Reserved, must be kept at reset value */ +#define OTGHS_GCCFG_VBUSASEN (1 << 18) /* Bit 18: Enable the VBUS sensing “A” device */ +#define OTGHS_GCCFG_VBUSBSEN (1 << 19) /* Bit 19: Enable the VBUS sensing “B” device */ +#define OTGHS_GCCFG_SOFOUTEN (1 << 20) /* Bit 20: SOF output enable */ +#define OTGHS_GCCFG_NOVBUSSENS (1 << 21) /* Bit 21: VBUS sensing disable option */ + /* Bits 31:22 Reserved, must be kept at reset value */ + +/* Core ID register (32-bit product ID) */ + +/* Host periodic transmit FIFO size register */ + +#define OTGHS_HPTXFSIZ_PTXSA_SHIFT (0) /* Bits 0-15: Host periodic TxFIFO start address */ +#define OTGHS_HPTXFSIZ_PTXSA_MASK (0xffff << OTGHS_HPTXFSIZ_PTXSA_SHIFT) +#define OTGHS_HPTXFSIZ_PTXFD_SHIFT (16) /* Bits 16-31: Host periodic TxFIFO depth */ +#define OTGHS_HPTXFSIZ_PTXFD_MASK (0xffff << OTGHS_HPTXFSIZ_PTXFD_SHIFT) + +/* Device IN endpoint transmit FIFOn size register */ + +#define OTGHS_DIEPTXF_INEPTXSA_SHIFT (0) /* Bits 0-15: IN endpoint FIFOx transmit RAM start address */ +#define OTGHS_DIEPTXF_INEPTXSA_MASK (0xffff << OTGHS_DIEPTXF_INEPTXSA_SHIFT) +#define OTGHS_DIEPTXF_INEPTXFD_SHIFT (16) /* Bits 16-31: IN endpoint TxFIFO depth */ +#define OTGHS_DIEPTXF_INEPTXFD_MASK (0xffff << OTGHS_DIEPTXF_INEPTXFD_SHIFT) +# define OTGHS_DIEPTXF_INEPTXFD_MIN (16 << OTGHS_DIEPTXF_INEPTXFD_MASK) + +/* Host-mode control and status registers */ + +/* Host configuration register */ + +#define OTGHS_HCFG_FSLSPCS_SHIFT (0) /* Bits 0-1: FS/LS PHY clock select */ +#define OTGHS_HCFG_FSLSPCS_MASK (3 << OTGHS_HCFG_FSLSPCS_SHIFT) +# define OTGHS_HCFG_FSLSPCS_FS48MHz (1 << OTGHS_HCFG_FSLSPCS_SHIFT) /* FS host mode, PHY clock is running at 48 MHz */ +# define OTGHS_HCFG_FSLSPCS_LS48MHz (1 << OTGHS_HCFG_FSLSPCS_SHIFT) /* LS host mode, Select 48 MHz PHY clock frequency */ +# define OTGHS_HCFG_FSLSPCS_LS6MHz (2 << OTGHS_HCFG_FSLSPCS_SHIFT) /* LS host mode, Select 6 MHz PHY clock frequency */ + +#define OTGHS_HCFG_FSLSS (1 << 2) /* Bit 2: FS- and LS-only support */ + /* Bits 31:3 Reserved, must be kept at reset value */ + +/* Host frame interval register */ + +#define OTGHS_HFIR_MASK (0xffff) + +/* Host frame number/frame time remaining register */ + +#define OTGHS_HFNUM_FRNUM_SHIFT (0) /* Bits 0-15: Frame number */ +#define OTGHS_HFNUM_FRNUM_MASK (0xffff << OTGHS_HFNUM_FRNUM_SHIFT) +#define OTGHS_HFNUM_FTREM_SHIFT (16) /* Bits 16-31: Frame time remaining */ +#define OTGHS_HFNUM_FTREM_MASK (0xffff << OTGHS_HFNUM_FTREM_SHIFT) + +/* Host periodic transmit FIFO/queue status register */ + +#define OTGHS_HPTXSTS_PTXFSAVL_SHIFT (0) /* Bits 0-15: Periodic transmit data FIFO space available */ +#define OTGHS_HPTXSTS_PTXFSAVL_MASK (0xffff << OTGHS_HPTXSTS_PTXFSAVL_SHIFT) +# define OTGHS_HPTXSTS_PTXFSAVL_FULL (0 << OTGHS_HPTXSTS_PTXFSAVL_SHIFT) +#define OTGHS_HPTXSTS_PTXQSAV_SHIFT (16) /* Bits 16-23: Periodic transmit request queue space available */ +#define OTGHS_HPTXSTS_PTXQSAV_MASK (0xff << OTGHS_HPTXSTS_PTXQSAV_SHIFT) +# define OTGHS_HPTXSTS_PTXQSAV_FULL (0 << OTGHS_HPTXSTS_PTXQSAV_SHIFT) +#define OTGHS_HPTXSTS_PTXQTOP_SHIFT (24) /* Bits 24-31: Top of the periodic transmit request queue */ +#define OTGHS_HPTXSTS_PTXQTOP_MASK (0x7f << OTGHS_HPTXSTS_PTXQTOP_SHIFT) +# define OTGHS_HPTXSTS_TERMINATE (1 << 24) /* Bit 24: Terminate (last entry for selected channel/endpoint) */ +# define OTGHS_HPTXSTS_TYPE_SHIFT (25) /* Bits 25-26: Type */ +# define OTGHS_HPTXSTS_TYPE_MASK (3 << OTGHS_HPTXSTS_TYPE_SHIFT) +# define OTGHS_HPTXSTS_TYPE_INOUT (0 << OTGHS_HPTXSTS_TYPE_SHIFT) /* IN/OUT token */ +# define OTGHS_HPTXSTS_TYPE_ZLP (1 << OTGHS_HPTXSTS_TYPE_SHIFT) /* Zero-length transmit packet */ +# define OTGHS_HPTXSTS_TYPE_HALT (3 << OTGHS_HPTXSTS_TYPE_SHIFT) /* Disable channel command */ + +# define OTGHS_HPTXSTS_EPNUM_SHIFT (27) /* Bits 27-30: Endpoint number */ +# define OTGHS_HPTXSTS_EPNUM_MASK (15 << OTGHS_HPTXSTS_EPNUM_SHIFT) +# define OTGHS_HPTXSTS_CHNUM_SHIFT (27) /* Bits 27-30: Channel number */ +# define OTGHS_HPTXSTS_CHNUM_MASK (15 << OTGHS_HPTXSTS_CHNUM_SHIFT) +# define OTGHS_HPTXSTS_ODD (1 << 24) /* Bit 31: Send in odd (vs even) frame */ + +/* Host all channels interrupt and all channels interrupt mask registers */ + +#define OTGHS_HAINT(n) (1 << (n)) /* Bits 15:0 HAINTM: Channel interrupt */ + +/* Host port control and status register */ + +#define OTGHS_HPRT_PCSTS (1 << 0) /* Bit 0: Port connect status */ +#define OTGHS_HPRT_PCDET (1 << 1) /* Bit 1: Port connect detected */ +#define OTGHS_HPRT_PENA (1 << 2) /* Bit 2: Port enable */ +#define OTGHS_HPRT_PENCHNG (1 << 3) /* Bit 3: Port enable/disable change */ +#define OTGHS_HPRT_POCA (1 << 4) /* Bit 4: Port overcurrent active */ +#define OTGHS_HPRT_POCCHNG (1 << 5) /* Bit 5: Port overcurrent change */ +#define OTGHS_HPRT_PRES (1 << 6) /* Bit 6: Port resume */ +#define OTGHS_HPRT_PSUSP (1 << 7) /* Bit 7: Port suspend */ +#define OTGHS_HPRT_PRST (1 << 8) /* Bit 8: Port reset */ + /* Bit 9: Reserved, must be kept at reset value */ +#define OTGHS_HPRT_PLSTS_SHIFT (10) /* Bits 10-11: Port line status */ +#define OTGHS_HPRT_PLSTS_MASK (3 << OTGHS_HPRT_PLSTS_SHIFT) +# define OTGHS_HPRT_PLSTS_DP (1 << 10) /* Bit 10: Logic level of OTG_FS_FS_DP */ +# define OTGHS_HPRT_PLSTS_DM (1 << 11) /* Bit 11: Logic level of OTG_FS_FS_DM */ +#define OTGHS_HPRT_PPWR (1 << 12) /* Bit 12: Port power */ +#define OTGHS_HPRT_PTCTL_SHIFT (13) /* Bits 13-16: Port test control */ +#define OTGHS_HPRT_PTCTL_MASK (15 << OTGHS_HPRT_PTCTL_SHIFT) +# define OTGHS_HPRT_PTCTL_DISABLED (0 << OTGHS_HPRT_PTCTL_SHIFT) /* Test mode disabled */ +# define OTGHS_HPRT_PTCTL_J (1 << OTGHS_HPRT_PTCTL_SHIFT) /* Test_J mode */ +# define OTGHS_HPRT_PTCTL_L (2 << OTGHS_HPRT_PTCTL_SHIFT) /* Test_K mode */ +# define OTGHS_HPRT_PTCTL_SE0_NAK (3 << OTGHS_HPRT_PTCTL_SHIFT) /* Test_SE0_NAK mode */ +# define OTGHS_HPRT_PTCTL_PACKET (4 << OTGHS_HPRT_PTCTL_SHIFT) /* Test_Packet mode */ +# define OTGHS_HPRT_PTCTL_FORCE (5 << OTGHS_HPRT_PTCTL_SHIFT) /* Test_Force_Enable */ + +#define OTGHS_HPRT_PSPD_SHIFT (17) /* Bits 17-18: Port speed */ +#define OTGHS_HPRT_PSPD_MASK (3 << OTGHS_HPRT_PSPD_SHIFT) +# define OTGHS_HPRT_PSPD_FS (1 << OTGHS_HPRT_PSPD_SHIFT) /* Full speed */ +# define OTGHS_HPRT_PSPD_LS (2 << OTGHS_HPRT_PSPD_SHIFT) /* Low speed */ + +/* Bits 19-31: Reserved, + * must be kept at reset value + */ + +/* Host channel-n characteristics register */ + +#define OTGHS_HCCHAR_MPSIZ_SHIFT (0) /* Bits 0-10: Maximum packet size */ +#define OTGHS_HCCHAR_MPSIZ_MASK (0x7ff << OTGHS_HCCHAR_MPSIZ_SHIFT) +#define OTGHS_HCCHAR_EPNUM_SHIFT (11) /* Bits 11-14: Endpoint number */ +#define OTGHS_HCCHAR_EPNUM_MASK (15 << OTGHS_HCCHAR_EPNUM_SHIFT) +#define OTGHS_HCCHAR_EPDIR (1 << 15) /* Bit 15: Endpoint direction */ +# define OTGHS_HCCHAR_EPDIR_OUT (0) +# define OTGHS_HCCHAR_EPDIR_IN OTGHS_HCCHAR_EPDIR + /* Bit 16 Reserved, must be kept at reset value */ +#define OTGHS_HCCHAR_LSDEV (1 << 17) /* Bit 17: Low-speed device */ +#define OTGHS_HCCHAR_EPTYP_SHIFT (18) /* Bits 18-19: Endpoint type */ +#define OTGHS_HCCHAR_EPTYP_MASK (3 << OTGHS_HCCHAR_EPTYP_SHIFT) +# define OTGHS_HCCHAR_EPTYP_CTRL (0 << OTGHS_HCCHAR_EPTYP_SHIFT) /* Control */ +# define OTGHS_HCCHAR_EPTYP_ISOC (1 << OTGHS_HCCHAR_EPTYP_SHIFT) /* Isochronous */ +# define OTGHS_HCCHAR_EPTYP_BULK (2 << OTGHS_HCCHAR_EPTYP_SHIFT) /* Bulk */ +# define OTGHS_HCCHAR_EPTYP_INTR (3 << OTGHS_HCCHAR_EPTYP_SHIFT) /* Interrupt */ + +#define OTGHS_HCCHAR_MCNT_SHIFT (20) /* Bits 20-21: Multicount */ +#define OTGHS_HCCHAR_MCNT_MASK (3 << OTGHS_HCCHAR_MCNT_SHIFT) +#define OTGHS_HCCHAR_DAD_SHIFT (22) /* Bits 22-28: Device address */ +#define OTGHS_HCCHAR_DAD_MASK (0x7f << OTGHS_HCCHAR_DAD_SHIFT) +#define OTGHS_HCCHAR_ODDFRM (1 << 29) /* Bit 29: Odd frame */ +#define OTGHS_HCCHAR_CHDIS (1 << 30) /* Bit 30: Channel disable */ +#define OTGHS_HCCHAR_CHENA (1 << 31) /* Bit 31: Channel enable */ + +/* Host channel-n interrupt and Host channel-0 interrupt mask registers */ + +#define OTGHS_HCINT_XFRC (1 << 0) /* Bit 0: Transfer completed */ +#define OTGHS_HCINT_CHH (1 << 1) /* Bit 1: Channel halted */ + /* Bit 2: Reserved, must be kept at reset value */ +#define OTGHS_HCINT_STALL (1 << 3) /* Bit 3: STALL response received interrupt */ +#define OTGHS_HCINT_NAK (1 << 4) /* Bit 4: NAK response received interrupt */ +#define OTGHS_HCINT_ACK (1 << 5) /* Bit 5: ACK response received/transmitted interrupt */ +#define OTGHS_HCINT_NYET (1 << 6) /* Bit 6: Response received interrupt */ +#define OTGHS_HCINT_TXERR (1 << 7) /* Bit 7: Transaction error */ +#define OTGHS_HCINT_BBERR (1 << 8) /* Bit 8: Babble error */ +#define OTGHS_HCINT_FRMOR (1 << 9) /* Bit 9: Frame overrun */ +#define OTGHS_HCINT_DTERR (1 << 10) /* Bit 10: Data toggle error */ + /* Bits 11-31 Reserved, must be kept at reset value */ + +/* Host channel-n interrupt register */ + +#define OTGHS_HCTSIZ_XFRSIZ_SHIFT (0) /* Bits 0-18: Transfer size */ +#define OTGHS_HCTSIZ_XFRSIZ_MASK (0x7ffff << OTGHS_HCTSIZ_XFRSIZ_SHIFT) +#define OTGHS_HCTSIZ_PKTCNT_SHIFT (19) /* Bits 19-28: Packet count */ +#define OTGHS_HCTSIZ_PKTCNT_MASK (0x3ff << OTGHS_HCTSIZ_PKTCNT_SHIFT) +#define OTGHS_HCTSIZ_DPID_SHIFT (29) /* Bits 29-30: Data PID */ +#define OTGHS_HCTSIZ_DPID_MASK (3 << OTGHS_HCTSIZ_DPID_SHIFT) +# define OTGHS_HCTSIZ_DPID_DATA0 (0 << OTGHS_HCTSIZ_DPID_SHIFT) +# define OTGHS_HCTSIZ_DPID_DATA2 (1 << OTGHS_HCTSIZ_DPID_SHIFT) +# define OTGHS_HCTSIZ_DPID_DATA1 (2 << OTGHS_HCTSIZ_DPID_SHIFT) +# define OTGHS_HCTSIZ_DPID_MDATA (3 << OTGHS_HCTSIZ_DPID_SHIFT) /* Non-control */ +# define OTGHS_HCTSIZ_PID_SETUP (3 << OTGHS_HCTSIZ_DPID_SHIFT) /* Control */ + +/* Bit 31 Reserved, + * must be kept at reset value + */ + +/* Device-mode control and status registers */ + +/* Device configuration register */ + +#define OTGHS_DCFG_DSPD_SHIFT (0) /* Bits 0-1: Device speed */ +#define OTGHS_DCFG_DSPD_MASK (3 << OTGHS_DCFG_DSPD_SHIFT) +# define OTGHS_DCFG_DSPD_FS (3 << OTGHS_DCFG_DSPD_SHIFT) /* Full speed */ + +#define OTGHS_DCFG_NZLSOHSK (1 << 2) /* Bit 2: Non-zero-length status OUT handshake */ + /* Bit 3: Reserved, must be kept at reset value */ +#define OTGHS_DCFG_DAD_SHIFT (4) /* Bits 4-10: Device address */ +#define OTGHS_DCFG_DAD_MASK (0x7f << OTGHS_DCFG_DAD_SHIFT) +#define OTGHS_DCFG_PFIVL_SHIFT (11) /* Bits 11-12: Periodic frame interval */ +#define OTGHS_DCFG_PFIVL_MASK (3 << OTGHS_DCFG_PFIVL_SHIFT) +# define OTGHS_DCFG_PFIVL_80PCT (0 << OTGHS_DCFG_PFIVL_SHIFT) /* 80% of the frame interval */ +# define OTGHS_DCFG_PFIVL_85PCT (1 << OTGHS_DCFG_PFIVL_SHIFT) /* 85% of the frame interval */ +# define OTGHS_DCFG_PFIVL_90PCT (2 << OTGHS_DCFG_PFIVL_SHIFT) /* 90% of the frame interval */ +# define OTGHS_DCFG_PFIVL_95PCT (3 << OTGHS_DCFG_PFIVL_SHIFT) /* 95% of the frame interval */ + +/* Bits 13-31 Reserved, + * must be kept at reset value + */ + +/* Device control register */ + +#define OTGHS_TESTMODE_DISABLED (0) /* Test mode disabled */ +#define OTGHS_TESTMODE_J (1) /* Test_J mode */ +#define OTGHS_TESTMODE_K (2) /* Test_K mode */ +#define OTGHS_TESTMODE_SE0_NAK (3) /* Test_SE0_NAK mode */ +#define OTGHS_TESTMODE_PACKET (4) /* Test_Packet mode */ +#define OTGHS_TESTMODE_FORCE (5) /* Test_Force_Enable */ + +#define OTGHS_DCTL_RWUSIG (1 << 0) /* Bit 0: Remote wakeup signaling */ +#define OTGHS_DCTL_SDIS (1 << 1) /* Bit 1: Soft disconnect */ +#define OTGHS_DCTL_GINSTS (1 << 2) /* Bit 2: Global IN NAK status */ +#define OTGHS_DCTL_GONSTS (1 << 3) /* Bit 3: Global OUT NAK status */ +#define OTGHS_DCTL_TCTL_SHIFT (4) /* Bits 4-6: Test control */ +#define OTGHS_DCTL_TCTL_MASK (7 << OTGHS_DCTL_TCTL_SHIFT) +# define OTGHS_DCTL_TCTL_DISABLED (0 << OTGHS_DCTL_TCTL_SHIFT) /* Test mode disabled */ +# define OTGHS_DCTL_TCTL_J (1 << OTGHS_DCTL_TCTL_SHIFT) /* Test_J mode */ +# define OTGHS_DCTL_TCTL_K (2 << OTGHS_DCTL_TCTL_SHIFT) /* Test_K mode */ +# define OTGHS_DCTL_TCTL_SE0_NAK (3 << OTGHS_DCTL_TCTL_SHIFT) /* Test_SE0_NAK mode */ +# define OTGHS_DCTL_TCTL_PACKET (4 << OTGHS_DCTL_TCTL_SHIFT) /* Test_Packet mode */ +# define OTGHS_DCTL_TCTL_FORCE (5 << OTGHS_DCTL_TCTL_SHIFT) /* Test_Force_Enable */ + +#define OTGHS_DCTL_SGINAK (1 << 7) /* Bit 7: Set global IN NAK */ +#define OTGHS_DCTL_CGINAK (1 << 8) /* Bit 8: Clear global IN NAK */ +#define OTGHS_DCTL_SGONAK (1 << 9) /* Bit 9: Set global OUT NAK */ +#define OTGHS_DCTL_CGONAK (1 << 10) /* Bit 10: Clear global OUT NAK */ +#define OTGHS_DCTL_POPRGDNE (1 << 11) /* Bit 11: Power-on programming done */ + /* Bits 12-31: Reserved, must be kept at reset value */ + +/* Device status register */ + +#define OTGHS_DSTS_SUSPSTS (1 << 0) /* Bit 0: Suspend status */ +#define OTGHS_DSTS_ENUMSPD_SHIFT (1) /* Bits 1-2: Enumerated speed */ +#define OTGHS_DSTS_ENUMSPD_MASK (3 << OTGHS_DSTS_ENUMSPD_SHIFT) +# define OTGHS_DSTS_ENUMSPD_FS (3 << OTGHS_DSTS_ENUMSPD_MASK) /* Full speed */ + +/* Bits 4-7: Reserved, + * must be kept at reset value + */ +#define OTGHS_DSTS_EERR (1 << 3) /* Bit 3: Erratic error */ +#define OTGHS_DSTS_SOFFN_SHIFT (8) /* Bits 8-21: Frame number of the received SOF */ +#define OTGHS_DSTS_SOFFN_MASK (0x3fff << OTGHS_DSTS_SOFFN_SHIFT) +#define OTGHS_DSTS_SOFFN0 (1 << 8) /* Bits 8: Frame number even/odd bit */ +#define OTGHS_DSTS_SOFFN_EVEN 0 +#define OTGHS_DSTS_SOFFN_ODD OTGHS_DSTS_SOFFN0 + /* Bits 22-31: Reserved, must be kept at reset value */ + +/* Device IN endpoint common interrupt mask register */ + +#define OTGHS_DIEPMSK_XFRCM (1 << 0) /* Bit 0: Transfer completed interrupt mask */ +#define OTGHS_DIEPMSK_EPDM (1 << 1) /* Bit 1: Endpoint disabled interrupt mask */ + /* Bit 2: Reserved, must be kept at reset value */ +#define OTGHS_DIEPMSK_TOM (1 << 3) /* Bit 3: Timeout condition mask (Non-isochronous endpoints) */ +#define OTGHS_DIEPMSK_ITTXFEMSK (1 << 4) /* Bit 4: IN token received when TxFIFO empty mask */ +#define OTGHS_DIEPMSK_INEPNMM (1 << 5) /* Bit 5: IN token received with EP mismatch mask */ +#define OTGHS_DIEPMSK_INEPNEM (1 << 6) /* Bit 6: IN endpoint NAK effective mask */ + /* Bits 7-31: Reserved, must be kept at reset value */ + +/* Device OUT endpoint common interrupt mask register */ + +#define OTGHS_DOEPMSK_XFRCM (1 << 0) /* Bit 0: Transfer completed interrupt mask */ +#define OTGHS_DOEPMSK_EPDM (1 << 1) /* Bit 1: Endpoint disabled interrupt mask */ + /* Bit 2: Reserved, must be kept at reset value */ +#define OTGHS_DOEPMSK_STUPM (1 << 3) /* Bit 3: SETUP phase done mask */ +#define OTGHS_DOEPMSK_OTEPDM (1 << 4) /* Bit 4: OUT token received when endpoint disabled mask */ + /* Bits 5-31: Reserved, must be kept at reset value */ + +/* Device all endpoints interrupt and All endpoints interrupt + * mask registers + */ + +#define OTGHS_DAINT_IEP_SHIFT (0) /* Bits 0-15: IN endpoint interrupt bits */ +#define OTGHS_DAINT_IEP_MASK (0xffff << OTGHS_DAINT_IEP_SHIFT) +# define OTGHS_DAINT_IEP(n) (1 << (n)) +#define OTGHS_DAINT_OEP_SHIFT (16) /* Bits 16-31: OUT endpoint interrupt bits */ +#define OTGHS_DAINT_OEP_MASK (0xffff << OTGHS_DAINT_OEP_SHIFT) +# define OTGHS_DAINT_OEP(n) (1 << ((n)+16)) + +/* Device VBUS discharge time register */ + +#define OTGHS_DVBUSDIS_MASK (0xffff) + +/* Device VBUS pulsing time register */ + +#define OTGHS_DVBUSPULSE_MASK (0xfff) + +/* Device IN endpoint FIFO empty interrupt mask register */ + +#define OTGHS_DIEPEMPMSK(n) (1 << (n)) + +/* Device control IN endpoint 0 control register */ + +#define OTGHS_DIEPCTL0_MPSIZ_SHIFT (0) /* Bits 0-1: Maximum packet size */ +#define OTGHS_DIEPCTL0_MPSIZ_MASK (3 << OTGHS_DIEPCTL0_MPSIZ_SHIFT) +# define OTGHS_DIEPCTL0_MPSIZ_64 (0 << OTGHS_DIEPCTL0_MPSIZ_SHIFT) /* 64 bytes */ +# define OTGHS_DIEPCTL0_MPSIZ_32 (1 << OTGHS_DIEPCTL0_MPSIZ_SHIFT) /* 32 bytes */ +# define OTGHS_DIEPCTL0_MPSIZ_16 (2 << OTGHS_DIEPCTL0_MPSIZ_SHIFT) /* 16 bytes */ +# define OTGHS_DIEPCTL0_MPSIZ_8 (3 << OTGHS_DIEPCTL0_MPSIZ_SHIFT) /* 8 bytes */ + +/* Bits 2-14: Reserved, + * must be kept at reset value + */ +#define OTGHS_DIEPCTL0_USBAEP (1 << 15) /* Bit 15: USB active endpoint */ + /* Bit 16: Reserved, must be kept at reset value */ +#define OTGHS_DIEPCTL0_NAKSTS (1 << 17) /* Bit 17: NAK status */ +#define OTGHS_DIEPCTL0_EPTYP_SHIFT (18) /* Bits 18-19: Endpoint type */ +#define OTGHS_DIEPCTL0_EPTYP_MASK (3 << OTGHS_DIEPCTL0_EPTYP_SHIFT) +# define OTGHS_DIEPCTL0_EPTYP_CTRL (0 << OTGHS_DIEPCTL0_EPTYP_SHIFT) /* Control (hard-coded) */ + +/* Bit 20: Reserved, + * must be kept at reset value + */ +#define OTGHS_DIEPCTL0_STALL (1 << 21) /* Bit 21: STALL handshake */ +#define OTGHS_DIEPCTL0_TXFNUM_SHIFT (22) /* Bits 22-25: TxFIFO number */ +#define OTGHS_DIEPCTL0_TXFNUM_MASK (15 << OTGHS_DIEPCTL0_TXFNUM_SHIFT) +#define OTGHS_DIEPCTL0_CNAK (1 << 26) /* Bit 26: Clear NAK */ +#define OTGHS_DIEPCTL0_SNAK (1 << 27) /* Bit 27: Set NAK */ + /* Bits 28-29: Reserved, must be kept at reset value */ +#define OTGHS_DIEPCTL0_EPDIS (1 << 30) /* Bit 30: Endpoint disable */ +#define OTGHS_DIEPCTL0_EPENA (1 << 31) /* Bit 31: Endpoint enable */ + +/* Device control IN endpoint n control register */ + +#define OTGHS_DIEPCTL_MPSIZ_SHIFT (0) /* Bits 0-10: Maximum packet size */ +#define OTGHS_DIEPCTL_MPSIZ_MASK (0x7ff << OTGHS_DIEPCTL_MPSIZ_SHIFT) + /* Bits 11-14: Reserved, must be kept at reset value */ +#define OTGHS_DIEPCTL_USBAEP (1 << 15) /* Bit 15: USB active endpoint */ +#define OTGHS_DIEPCTL_EONUM (1 << 16) /* Bit 16: Even/odd frame */ +# define OTGHS_DIEPCTL_EVEN (0) +# define OTGHS_DIEPCTL_ODD OTGHS_DIEPCTL_EONUM +# define OTGHS_DIEPCTL_DATA0 (0) +# define OTGHS_DIEPCTL_DATA1 OTGHS_DIEPCTL_EONUM +#define OTGHS_DIEPCTL_NAKSTS (1 << 17) /* Bit 17: NAK status */ +#define OTGHS_DIEPCTL_EPTYP_SHIFT (18) /* Bits 18-19: Endpoint type */ +#define OTGHS_DIEPCTL_EPTYP_MASK (3 << OTGHS_DIEPCTL_EPTYP_SHIFT) +# define OTGHS_DIEPCTL_EPTYP_CTRL (0 << OTGHS_DIEPCTL_EPTYP_SHIFT) /* Control */ +# define OTGHS_DIEPCTL_EPTYP_ISOC (1 << OTGHS_DIEPCTL_EPTYP_SHIFT) /* Isochronous */ +# define OTGHS_DIEPCTL_EPTYP_BULK (2 << OTGHS_DIEPCTL_EPTYP_SHIFT) /* Bulk */ +# define OTGHS_DIEPCTL_EPTYP_INTR (3 << OTGHS_DIEPCTL_EPTYP_SHIFT) /* Interrupt */ + +/* Bit 20: Reserved, + * must be kept at reset value + */ +#define OTGHS_DIEPCTL_STALL (1 << 21) /* Bit 21: STALL handshake */ +#define OTGHS_DIEPCTL_TXFNUM_SHIFT (22) /* Bits 22-25: TxFIFO number */ +#define OTGHS_DIEPCTL_TXFNUM_MASK (15 << OTGHS_DIEPCTL_TXFNUM_SHIFT) +#define OTGHS_DIEPCTL_CNAK (1 << 26) /* Bit 26: Clear NAK */ +#define OTGHS_DIEPCTL_SNAK (1 << 27) /* Bit 27: Set NAK */ +#define OTGHS_DIEPCTL_SD0PID (1 << 28) /* Bit 28: Set DATA0 PID (interrupt/bulk) */ +#define OTGHS_DIEPCTL_SEVNFRM (1 << 28) /* Bit 28: Set even frame (isochronous)) */ +#define OTGHS_DIEPCTL_SODDFRM (1 << 29) /* Bit 29: Set odd frame (isochronous) */ +#define OTGHS_DIEPCTL_EPDIS (1 << 30) /* Bit 30: Endpoint disable */ +#define OTGHS_DIEPCTL_EPENA (1 << 31) /* Bit 31: Endpoint enable */ + +/* Device endpoint-n interrupt register */ + +#define OTGHS_DIEPINT_XFRC (1 << 0) /* Bit 0: Transfer completed interrupt */ +#define OTGHS_DIEPINT_EPDISD (1 << 1) /* Bit 1: Endpoint disabled interrupt */ + /* Bit 2: Reserved, must be kept at reset value */ +#define OTGHS_DIEPINT_TOC (1 << 3) /* Bit 3: Timeout condition */ +#define OTGHS_DIEPINT_ITTXFE (1 << 4) /* Bit 4: IN token received when TxFIFO is empty */ + /* Bit 5: Reserved, must be kept at reset value */ +#define OTGHS_DIEPINT_INEPNE (1 << 6) /* Bit 6: IN endpoint NAK effective */ +#define OTGHS_DIEPINT_TXFE (1 << 7) /* Bit 7: Transmit FIFO empty */ + /* Bits 8-31: Reserved, must be kept at reset value */ + +/* Device IN endpoint 0 transfer size register */ + +#define OTGHS_DIEPTSIZ0_XFRSIZ_SHIFT (0) /* Bits 0-6: Transfer size */ +#define OTGHS_DIEPTSIZ0_XFRSIZ_MASK (0x7f << OTGHS_DIEPTSIZ0_XFRSIZ_SHIFT) + /* Bits 7-18: Reserved, must be kept at reset value */ +#define OTGHS_DIEPTSIZ0_PKTCNT_SHIFT (19) /* Bits 19-20: Packet count */ +#define OTGHS_DIEPTSIZ0_PKTCNT_MASK (3 << OTGHS_DIEPTSIZ0_PKTCNT_SHIFT) + /* Bits 21-31: Reserved, must be kept at reset value */ + +/* Device IN endpoint n transfer size register */ + +#define OTGHS_DIEPTSIZ_XFRSIZ_SHIFT (0) /* Bits 0-18: Transfer size */ +#define OTGHS_DIEPTSIZ_XFRSIZ_MASK (0x7ffff << OTGHS_DIEPTSIZ_XFRSIZ_SHIFT) +#define OTGHS_DIEPTSIZ_PKTCNT_SHIFT (19) /* Bit 19-28: Packet count */ +#define OTGHS_DIEPTSIZ_PKTCNT_MASK (0x3ff << OTGHS_DIEPTSIZ_PKTCNT_SHIFT) +#define OTGHS_DIEPTSIZ_MCNT_SHIFT (29) /* Bits 29-30: Multi count */ +#define OTGHS_DIEPTSIZ_MCNT_MASK (3 << OTGHS_DIEPTSIZ_MCNT_SHIFT) + /* Bit 31: Reserved, must be kept at reset value */ + +/* Device OUT endpoint TxFIFO status register */ + +#define OTGHS_DTXFSTS_MASK (0xffff) + +/* Device OUT endpoint 0 control register */ + +#define OTGHS_DOEPCTL0_MPSIZ_SHIFT (0) /* Bits 0-1: Maximum packet size */ +#define OTGHS_DOEPCTL0_MPSIZ_MASK (3 << OTGHS_DOEPCTL0_MPSIZ_SHIFT) +# define OTGHS_DOEPCTL0_MPSIZ_64 (0 << OTGHS_DOEPCTL0_MPSIZ_SHIFT) /* 64 bytes */ +# define OTGHS_DOEPCTL0_MPSIZ_32 (1 << OTGHS_DOEPCTL0_MPSIZ_SHIFT) /* 32 bytes */ +# define OTGHS_DOEPCTL0_MPSIZ_16 (2 << OTGHS_DOEPCTL0_MPSIZ_SHIFT) /* 16 bytes */ +# define OTGHS_DOEPCTL0_MPSIZ_8 (3 << OTGHS_DOEPCTL0_MPSIZ_SHIFT) /* 8 bytes */ + +/* Bits 2-14: Reserved, + * must be kept at reset value + */ +#define OTGHS_DOEPCTL0_USBAEP (1 << 15) /* Bit 15: USB active endpoint */ + /* Bit 16: Reserved, must be kept at reset value */ +#define OTGHS_DOEPCTL0_NAKSTS (1 << 17) /* Bit 17: NAK status */ +#define OTGHS_DOEPCTL0_EPTYP_SHIFT (18) /* Bits 18-19: Endpoint type */ +#define OTGHS_DOEPCTL0_EPTYP_MASK (3 << OTGHS_DOEPCTL0_EPTYP_SHIFT) +# define OTGHS_DOEPCTL0_EPTYP_CTRL (0 << OTGHS_DOEPCTL0_EPTYP_SHIFT) /* Control (hard-coded) */ + +#define OTGHS_DOEPCTL0_SNPM (1 << 20) /* Bit 20: Snoop mode */ +#define OTGHS_DOEPCTL0_STALL (1 << 21) /* Bit 21: STALL handshake */ + /* Bits 22-25: Reserved, must be kept at reset value */ +#define OTGHS_DOEPCTL0_CNAK (1 << 26) /* Bit 26: Clear NAK */ +#define OTGHS_DOEPCTL0_SNAK (1 << 27) /* Bit 27: Set NAK */ + /* Bits 28-29: Reserved, must be kept at reset value */ +#define OTGHS_DOEPCTL0_EPDIS (1 << 30) /* Bit 30: Endpoint disable */ +#define OTGHS_DOEPCTL0_EPENA (1 << 31) /* Bit 31: Endpoint enable */ + +/* Device OUT endpoint n control register */ + +#define OTGHS_DOEPCTL_MPSIZ_SHIFT (0) /* Bits 0-10: Maximum packet size */ +#define OTGHS_DOEPCTL_MPSIZ_MASK (0x7ff << OTGHS_DOEPCTL_MPSIZ_SHIFT) + /* Bits 11-14: Reserved, must be kept at reset value */ +#define OTGHS_DOEPCTL_USBAEP (1 << 15) /* Bit 15: USB active endpoint */ +#define OTGHS_DOEPCTL_DPID (1 << 16) /* Bit 16: Endpoint data PID (interrupt/bulk) */ +# define OTGHS_DOEPCTL_DATA0 (0) +# define OTGHS_DOEPCTL_DATA1 OTGHS_DOEPCTL_DPID +#define OTGHS_DOEPCTL_EONUM (1 << 16) /* Bit 16: Even/odd frame (isochronous) */ +# define OTGHS_DOEPCTL_EVEN (0) +# define OTGHS_DOEPCTL_ODD OTGHS_DOEPCTL_EONUM +#define OTGHS_DOEPCTL_NAKSTS (1 << 17) /* Bit 17: NAK status */ +#define OTGHS_DOEPCTL_EPTYP_SHIFT (18) /* Bits 18-19: Endpoint type */ +#define OTGHS_DOEPCTL_EPTYP_MASK (3 << OTGHS_DOEPCTL_EPTYP_SHIFT) +# define OTGHS_DOEPCTL_EPTYP_CTRL (0 << OTGHS_DOEPCTL_EPTYP_SHIFT) /* Control */ +# define OTGHS_DOEPCTL_EPTYP_ISOC (1 << OTGHS_DOEPCTL_EPTYP_SHIFT) /* Isochronous */ +# define OTGHS_DOEPCTL_EPTYP_BULK (2 << OTGHS_DOEPCTL_EPTYP_SHIFT) /* Bulk */ +# define OTGHS_DOEPCTL_EPTYP_INTR (3 << OTGHS_DOEPCTL_EPTYP_SHIFT) /* Interrupt */ + +#define OTGHS_DOEPCTL_SNPM (1 << 20) /* Bit 20: Snoop mode */ +#define OTGHS_DOEPCTL_STALL (1 << 21) /* Bit 21: STALL handshake */ + /* Bits 22-25: Reserved, must be kept at reset value */ +#define OTGHS_DOEPCTL_CNAK (1 << 26) /* Bit 26: Clear NAK */ +#define OTGHS_DOEPCTL_SNAK (1 << 27) /* Bit 27: Set NAK */ +#define OTGHS_DOEPCTL_SD0PID (1 << 28) /* Bit 28: Set DATA0 PID (interrupt/bulk) */ +#define OTGHS_DOEPCTL_SEVNFRM (1 << 28) /* Bit 28: Set even frame (isochronous) */ +#define OTGHS_DOEPCTL_SD1PID (1 << 29) /* Bit 29: Set DATA1 PID (interrupt/bulk) */ +#define OTGHS_DOEPCTL_SODDFRM (1 << 29) /* Bit 29: Set odd frame (isochronous */ +#define OTGHS_DOEPCTL_EPDIS (1 << 30) /* Bit 30: Endpoint disable */ +#define OTGHS_DOEPCTL_EPENA (1 << 31) /* Bit 31: Endpoint enable */ + +/* Device endpoint-n interrupt register */ + +#define OTGHS_DOEPINT_XFRC (1 << 0) /* Bit 0: Transfer completed interrupt */ +#define OTGHS_DOEPINT_EPDISD (1 << 1) /* Bit 1: Endpoint disabled interrupt */ + /* Bit 2: Reserved, must be kept at reset value */ +#define OTGHS_DOEPINT_SETUP (1 << 3) /* Bit 3: SETUP phase done */ +#define OTGHS_DOEPINT_OTEPDIS (1 << 4) /* Bit 4: OUT token received when endpoint disabled */ + /* Bit 5: Reserved, must be kept at reset value */ +#define OTGHS_DOEPINT_B2BSTUP (1 << 6) /* Bit 6: Back-to-back SETUP packets received */ + /* Bits 7-31: Reserved, must be kept at reset value */ + +/* Device OUT endpoint-0 transfer size register */ + +#define OTGHS_DOEPTSIZ0_XFRSIZ_SHIFT (0) /* Bits 0-6: Transfer size */ +#define OTGHS_DOEPTSIZ0_XFRSIZ_MASK (0x7f << OTGHS_DOEPTSIZ0_XFRSIZ_SHIFT) + /* Bits 7-18: Reserved, must be kept at reset value */ +#define OTGHS_DOEPTSIZ0_PKTCNT (1 << 19) /* Bit 19 PKTCNT: Packet count */ + /* Bits 20-28: Reserved, must be kept at reset value */ +#define OTGHS_DOEPTSIZ0_STUPCNT_SHIFT (29) /* Bits 29-30: SETUP packet count */ +#define OTGHS_DOEPTSIZ0_STUPCNT_MASK (3 << OTGHS_DOEPTSIZ0_STUPCNT_SHIFT) + /* Bit 31: Reserved, must be kept at reset value */ + +/* Device OUT endpoint-n transfer size register */ + +#define OTGHS_DOEPTSIZ_XFRSIZ_SHIFT (0) /* Bits 0-18: Transfer size */ +#define OTGHS_DOEPTSIZ_XFRSIZ_MASK (0x7ffff << OTGHS_DOEPTSIZ_XFRSIZ_SHIFT) +#define OTGHS_DOEPTSIZ_PKTCNT_SHIFT (19) /* Bit 19-28: Packet count */ +#define OTGHS_DOEPTSIZ_PKTCNT_MASK (0x3ff << OTGHS_DOEPTSIZ_PKTCNT_SHIFT) +#define OTGHS_DOEPTSIZ_STUPCNT_SHIFT (29) /* Bits 29-30: SETUP packet count */ +#define OTGHS_DOEPTSIZ_STUPCNT_MASK (3 << OTGHS_DOEPTSIZ_STUPCNT_SHIFT) +#define OTGHS_DOEPTSIZ_RXDPID_SHIFT (29) /* Bits 29-30: Received data PID */ +#define OTGHS_DOEPTSIZ_RXDPID_MASK (3 << OTGHS_DOEPTSIZ_RXDPID_SHIFT) +# define OTGHS_DOEPTSIZ_RXDPID_DATA0 (0 << OTGHS_DOEPTSIZ_RXDPID_SHIFT) +# define OTGHS_DOEPTSIZ_RXDPID_DATA2 (1 << OTGHS_DOEPTSIZ_RXDPID_SHIFT) +# define OTGHS_DOEPTSIZ_RXDPID_DATA1 (2 << OTGHS_DOEPTSIZ_RXDPID_SHIFT) +# define OTGHS_DOEPTSIZ_RXDPID_MDATA (3 << OTGHS_DOEPTSIZ_RXDPID_SHIFT) + /* Bit 31: Reserved, must be kept at reset value */ + +/* Power and clock gating control register */ + +#define OTGHS_PCGCCTL_STPPCLK (1 << 0) /* Bit 0: Stop PHY clock */ +#define OTGHS_PCGCCTL_GATEHCLK (1 << 1) /* Bit 1: Gate HCLK */ + /* Bits 2-3: Reserved, must be kept at reset value */ +#define OTGHS_PCGCCTL_PHYSUSP (1 << 4) /* Bit 4: PHY Suspended */ + /* Bits 5-31: Reserved, must be kept at reset value */ + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_OTGHS_H */ diff --git a/arch/arm/src/common/stm32/hardware/stm32_pwr.h b/arch/arm/src/common/stm32/hardware/stm32_pwr.h new file mode 100644 index 0000000000000..cbd743564b821 --- /dev/null +++ b/arch/arm/src/common/stm32/hardware/stm32_pwr.h @@ -0,0 +1,45 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/hardware/stm32_pwr.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_PWR_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_PWR_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#if (defined(CONFIG_STM32_HAVE_IP_PWR_M0_V1) + \ + defined(CONFIG_STM32_HAVE_IP_PWR_G0) + \ + defined(CONFIG_STM32_HAVE_IP_PWR_M3M4_V1)) > 1 +# error Only one STM32 PWR IP version must be selected +#endif + +#if defined(CONFIG_STM32_HAVE_IP_PWR_M0_V1) || \ + defined(CONFIG_STM32_HAVE_IP_PWR_G0) +# include "hardware/stm32_pwr_v1_m0_g0.h" +#elif defined(CONFIG_STM32_HAVE_IP_PWR_M3M4_V1) +# include "hardware/stm32_pwr_v1.h" +#else +# error "Unsupported STM32 PWR" +#endif + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_PWR_H */ diff --git a/arch/arm/src/common/stm32/hardware/stm32_pwr_v1.h b/arch/arm/src/common/stm32/hardware/stm32_pwr_v1.h new file mode 100644 index 0000000000000..e2fc5e05621c2 --- /dev/null +++ b/arch/arm/src/common/stm32/hardware/stm32_pwr_v1.h @@ -0,0 +1,165 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/hardware/stm32_pwr_v1.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_PWR_V1_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_PWR_V1_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include "chip.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Register Offsets *********************************************************/ + +#define STM32_PWR_CR_OFFSET 0x0000 /* Power control register */ +#define STM32_PWR_CSR_OFFSET 0x0004 /* Power control/status register */ + +/* Register Addresses *******************************************************/ + +#define STM32_PWR_CR (STM32_PWR_BASE+STM32_PWR_CR_OFFSET) +#define STM32_PWR_CSR (STM32_PWR_BASE+STM32_PWR_CSR_OFFSET) + +/* Register Bitfield Definitions ********************************************/ + +/* Power control register */ + +#define PWR_CR_LPDS (1 << 0) /* Bit 0: Low-Power Deepsleep/sleep; low power run */ +#define PWR_CR_PDDS (1 << 1) /* Bit 1: Power Down Deepsleep */ +#define PWR_CR_CWUF (1 << 2) /* Bit 2: Clear Wakeup Flag */ +#define PWR_CR_CSBF (1 << 3) /* Bit 3: Clear Standby Flag */ +#define PWR_CR_PVDE (1 << 4) /* Bit 4: Power Voltage Detector Enable */ + +#define PWR_CR_PLS_SHIFT (5) /* Bits 7-5: PVD Level Selection */ +#define PWR_CR_PLS_MASK (7 << PWR_CR_PLS_SHIFT) +# if defined(CONFIG_STM32_STM32L15XX) +# define PWR_CR_1p9V (0 << PWR_CR_PLS_SHIFT) /* 000: 1.9 V */ +# define PWR_CR_2p1V (1 << PWR_CR_PLS_SHIFT) /* 001: 2.1 V */ +# define PWR_CR_2p3V (2 << PWR_CR_PLS_SHIFT) /* 010: 2.3 V */ +# define PWR_CR_2p5V (3 << PWR_CR_PLS_SHIFT) /* 011: 2.5 V */ +# define PWR_CR_2p7V (4 << PWR_CR_PLS_SHIFT) /* 100: 2.7 V */ +# define PWR_CR_2p9V (5 << PWR_CR_PLS_SHIFT) /* 101: 2.9 V */ +# define PWR_CR_3p1V (6 << PWR_CR_PLS_SHIFT) /* 110: 3.1 V */ +# define PWR_CR_EXT (7 << PWR_CR_PLS_SHIFT) /* 111: External input analog voltage */ +# else +# define PWR_CR_2p2V (0 << PWR_CR_PLS_SHIFT) /* 000: 2.2V */ +# define PWR_CR_2p3V (1 << PWR_CR_PLS_SHIFT) /* 001: 2.3V */ +# define PWR_CR_2p4V (2 << PWR_CR_PLS_SHIFT) /* 010: 2.4V */ +# define PWR_CR_2p5V (3 << PWR_CR_PLS_SHIFT) /* 011: 2.5V */ +# define PWR_CR_2p6V (4 << PWR_CR_PLS_SHIFT) /* 100: 2.6V */ +# define PWR_CR_2p7V (5 << PWR_CR_PLS_SHIFT) /* 101: 2.7V */ +# define PWR_CR_2p8V (6 << PWR_CR_PLS_SHIFT) /* 110: 2.8V */ +# define PWR_CR_2p9V (7 << PWR_CR_PLS_SHIFT) /* 111: 2.9V */ +# endif +#define PWR_CR_DBP (1 << 8) /* Bit 8: Disable Backup Domain write protection */ + +#if defined(CONFIG_STM32_HAVE_IP_PWR_M3M4_V1) +# define PWR_CR_FPDS (1 << 9) /* Bit 9: Flash power down in Stop mode */ +# if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429) || \ + defined(CONFIG_STM32_STM32F446) || defined(CONFIG_STM32_STM32F469) || \ + defined(CONFIG_STM32_STM32F412) +# define PWR_CR_ADCDC1 (1 << 13) /* Bit 13: see AN4073 for details */ +# define PWR_CR_VOS_MASK (3 << 14) /* Bits 14-15: Regulator voltage scaling output selection */ +# define PWR_CR_VOS_SCALE_1 (3 << 14) /* Fmax = 168MHz */ +# define PWR_CR_VOS_SCALE_2 (2 << 14) /* Fmax = 144MHz */ +# define PWR_CR_VOS_SCALE_3 (1 << 14) /* Fmax = 120MHz */ +# else +# define PWR_CR_VOS (1 << 14) /* Bit 14: Regulator voltage scaling output selection */ + /* 0: Fmax = 144MHz 1: Fmax = 168MHz */ +# endif +#endif + +#if defined(CONFIG_STM32_STM32F37XX) +#define PWR_CR_ENSD1 (1 << 9) /* Bit 9: Enable SDADC1 */ +#define PWR_CR_ENSD2 (1 << 10) /* Bit 10: Enable SDADC2 */ +#define PWR_CR_ENSD3 (1 << 11) /* Bit 11: Enable SDADC3 */ +#endif + +#if defined(CONFIG_STM32_STM32L15XX) +# define PWR_CR_ULP (1 << 9) /* Ultralow power mode */ +# define PWR_CR_FWU (1 << 10) /* Fast wake-up */ +# define PWR_CR_VOS_MASK (3 << 11) /* Bits 11-12: Regulator voltage scaling output selection */ +# define PWR_CR_VOS_SCALE_1 (1 << 11) /* 1.8 V (range 1) PLL VCO Max = 96MHz */ +# define PWR_CR_VOS_SCALE_2 (2 << 11) /* 1.5 V (range 2) PLL VCO Max = 64MHz */ +# define PWR_CR_VOS_SCALE_3 (3 << 11) /* 1.2 V (range 3) PLL VCO Max = 24MHz */ +# define PWR_CR_LPRUN (1 << 14) /* Low power run mode */ +#endif + +#if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429) || \ + defined(CONFIG_STM32_STM32F446) || defined(CONFIG_STM32_STM32F469) +# define PWR_CR_ODEN (1 << 16) /* Over Drive enable */ +# define PWR_CR_ODSWEN (1 << 17) /* Over Drive switch enabled */ +#endif + +#if defined(CONFIG_STM32_STM32F446) || defined(CONFIG_STM32_STM32F412) +# define PWR_CR_FMSSR (1 << 20) /* Flash Memory Stop while System Run */ +# define PWR_CR_FISSR (1 << 21) /* Flash Interface Stop while System Run*/ +#endif + +/* Power control/status register */ + +#define PWR_CSR_WUF (1 << 0) /* Bit 0: Wakeup Flag */ +#define PWR_CSR_SBF (1 << 1) /* Bit 1: Standby Flag */ +#define PWR_CSR_PVDO (1 << 2) /* Bit 2: PVD Output */ + +#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F37XX) || \ + defined(CONFIG_STM32_STM32F4XXX) +# define PWR_CSR_BRR (1 << 3) /* Bit 3: Backup regulator ready */ +#elif defined(CONFIG_STM32_STM32L15XX) +# define PWR_CSR_VREFINTRDYF (1 << 3) /* Bit 3: Internal voltage reference (VREFINT) ready flag */ +# define PWR_CSR_VOSF (1 << 4) /* Bit 4: Voltage Scaling select flag */ +# define PWR_CSR_REGLPF (1 << 5) /* Bit 5: Regulator LP flag */ +#endif + +#if defined(CONFIG_STM32_STM32F30XX) +# define PWR_CSR_EWUP1 (1 << 8) /* Bit 8: Enable WKUP1 pin */ +# define PWR_CSR_EWUP2 (1 << 9) /* Bit 9: Enable WKUP2 pin */ +#elif defined(CONFIG_STM32_STM32L15XX) || defined(CONFIG_STM32_STM32F33XX) || \ + defined(CONFIG_STM32_STM32F37XX) +# define PWR_CSR_EWUP1 (1 << 8) /* Bit 8: Enable WKUP1 pin */ +# define PWR_CSR_EWUP2 (1 << 9) /* Bit 9: Enable WKUP2 pin */ +# define PWR_CSR_EWUP3 (1 << 10) /* Bit 10: Enable WKUP3 pin */ +#elif defined(CONFIG_STM32_STM32F412) +# define PWR_CSR_EWUP3 (1 << 6) /* Bit 6: Enable WKUP3 pin */ +# define PWR_CSR_EWUP2 (1 << 7) /* Bit 7: Enable WKUP2 pin */ +# define PWR_CSR_EWUP1 (1 << 8) /* Bit 8: Enable WKUP1 pin */ +#else +# define PWR_CSR_EWUP (1 << 8) /* Bit 8: Enable WKUP pin */ +#endif + +#if defined(CONFIG_STM32_HAVE_IP_PWR_M3M4_V1) +# define PWR_CSR_BRE (1 << 9) /* Bit 9: Backup regulator enable */ +# define PWR_CSR_VOSRDY (1 << 14) /* Bit 14: Regulator voltage scaling output selection ready bite */ +#endif + +#if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429) || \ + defined(CONFIG_STM32_STM32F446) || defined(CONFIG_STM32_STM32F469) +# define PWR_CSR_ODRDY (1 << 16) /* Bit 16: Over Drive generator ready */ +# define PWR_CSR_ODSWRDY (1 << 17) /* Bit 17: Over Drive Switch ready */ +#endif + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_PWR_V1_H */ diff --git a/arch/arm/src/common/stm32/hardware/stm32_pwr_v1_m0_g0.h b/arch/arm/src/common/stm32/hardware/stm32_pwr_v1_m0_g0.h new file mode 100644 index 0000000000000..66a345f6d8296 --- /dev/null +++ b/arch/arm/src/common/stm32/hardware/stm32_pwr_v1_m0_g0.h @@ -0,0 +1,45 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/hardware/stm32_pwr_v1_m0_g0.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_PWR_V1_M0_G0_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_PWR_V1_M0_G0_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include "chip.h" + +#if defined(CONFIG_ARCH_CHIP_STM32F0) +# include "hardware/stm32f0_pwr.h" +#elif defined(CONFIG_ARCH_CHIP_STM32L0) +# include "hardware/stm32l0_pwr.h" +#elif defined(CONFIG_ARCH_CHIP_STM32G0) +# include "hardware/stm32g0_pwr.h" +#elif defined(CONFIG_ARCH_CHIP_STM32C0) +# include "hardware/stm32c0_pwr.h" +#else +# error "Unsupported STM32 M0 PWR" +#endif + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_PWR_V1_M0_G0_H */ diff --git a/arch/arm/src/common/stm32/hardware/stm32_rcc.h b/arch/arm/src/common/stm32/hardware/stm32_rcc.h new file mode 100644 index 0000000000000..308cd4d9df954 --- /dev/null +++ b/arch/arm/src/common/stm32/hardware/stm32_rcc.h @@ -0,0 +1,69 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/hardware/stm32_rcc.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_RCC_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_RCC_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include "chip.h" + +#if defined(CONFIG_ARCH_CHIP_STM32F0) +# include "hardware/stm32f0_rcc.h" +#elif defined(CONFIG_ARCH_CHIP_STM32L0) +# include "hardware/stm32l0_rcc.h" +#elif defined(CONFIG_ARCH_CHIP_STM32G0) +# include "hardware/stm32g0_rcc.h" +#elif defined(CONFIG_ARCH_CHIP_STM32C0) +# include "hardware/stm32c0_rcc.h" +#elif defined(CONFIG_ARCH_CHIP_STM32F1) +# include "hardware/stm32f10xxx_rcc.h" +#elif defined(CONFIG_ARCH_CHIP_STM32F2) +# include "hardware/stm32f20xxx_rcc.h" +#elif defined(CONFIG_ARCH_CHIP_STM32F3) +# if defined(CONFIG_STM32_STM32F30XX) || \ + defined(CONFIG_STM32_STM32F302X8) || \ + defined(CONFIG_STM32_STM32F302XC) || \ + defined(CONFIG_STM32_STM32F303XC) || \ + defined(CONFIG_STM32_STM32F303XE) +# include "hardware/stm32f30xxx_rcc.h" +# elif defined(CONFIG_STM32_STM32F33XX) +# include "hardware/stm32f33xxx_rcc.h" +# elif defined(CONFIG_STM32_STM32F37XX) +# include "hardware/stm32f37xxx_rcc.h" +# else +# error "Unsupported STM32F3 RCC" +# endif +#elif defined(CONFIG_ARCH_CHIP_STM32F4) +# include "hardware/stm32f40xxx_rcc.h" +#elif defined(CONFIG_ARCH_CHIP_STM32G4) +# include "hardware/stm32g4xxxx_rcc.h" +#elif defined(CONFIG_ARCH_CHIP_STM32L1) +# include "hardware/stm32l15xxx_rcc.h" +#else +# error "Unsupported STM32 RCC" +#endif + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_RCC_H */ diff --git a/arch/arm/src/common/stm32/hardware/stm32_rng.h b/arch/arm/src/common/stm32/hardware/stm32_rng.h new file mode 100644 index 0000000000000..5b81e5116b6b8 --- /dev/null +++ b/arch/arm/src/common/stm32/hardware/stm32_rng.h @@ -0,0 +1,43 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/hardware/stm32_rng.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_RNG_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_RNG_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#if (defined(CONFIG_STM32_HAVE_IP_RNG_M0_V1) + \ + defined(CONFIG_STM32_HAVE_IP_RNG_M3M4_V1)) > 1 +# error Only one STM32 RNG IP version must be selected +#endif + +#if defined(CONFIG_STM32_HAVE_IP_RNG_M0_V1) +# include "hardware/stm32_rng_m0.h" +#elif defined(CONFIG_STM32_HAVE_IP_RNG_M3M4_V1) +# include "hardware/stm32_rng_v1.h" +#else +# error "Unsupported STM32 RNG" +#endif + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_RNG_H */ diff --git a/arch/arm/src/common/stm32/hardware/stm32_rng_m0.h b/arch/arm/src/common/stm32/hardware/stm32_rng_m0.h new file mode 100644 index 0000000000000..1fc3c863998d1 --- /dev/null +++ b/arch/arm/src/common/stm32/hardware/stm32_rng_m0.h @@ -0,0 +1,65 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/hardware/stm32_rng_m0.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_RNG_M0_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_RNG_M0_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include "chip.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Register Offsets *********************************************************/ + +#define STM32_RNG_CR_OFFSET 0x0000 /* RNG Control Register */ +#define STM32_RNG_SR_OFFSET 0x0004 /* RNG Status Register */ +#define STM32_RNG_DR_OFFSET 0x0008 /* RNG Data Register */ + +/* Register Addresses *******************************************************/ + +#define STM32_RNG_CR (STM32_RNG_BASE+STM32_RNG_CR_OFFSET) +#define STM32_RNG_SR (STM32_RNG_BASE+STM32_RNG_SR_OFFSET) +#define STM32_RNG_DR (STM32_RNG_BASE+STM32_RNG_DR_OFFSET) + +/* Register Bitfield Definitions ********************************************/ + +/* RNG Control Register */ + +#define RNG_CR_RNGEN (1 << 2) /* Bit 2: RNG enable */ +#define RNG_CR_IE (1 << 3) /* Bit 3: Interrupt enable */ +#define RNG_CR_CE (1 << 5) /* Bit 5: Clock error detection */ + +/* RNG Status Register */ + +#define RNG_SR_DRDY (1 << 0) /* Bit 0: Data ready */ +#define RNG_SR_CECS (1 << 1) /* Bit 1: Clock error current status */ +#define RNG_SR_SECS (1 << 2) /* Bit 2: Seed error current status */ +#define RNG_SR_CEIS (1 << 5) /* Bit 5: Clock error interrupt status */ +#define RNG_SR_SEIS (1 << 6) /* Bit 6: Seed error interrupt status */ + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_RNG_M0_H */ diff --git a/arch/arm/src/common/stm32/hardware/stm32_rng_v1.h b/arch/arm/src/common/stm32/hardware/stm32_rng_v1.h new file mode 100644 index 0000000000000..51a829ed5dc91 --- /dev/null +++ b/arch/arm/src/common/stm32/hardware/stm32_rng_v1.h @@ -0,0 +1,64 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/hardware/stm32_rng_v1.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_RNG_V1_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_RNG_V1_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include "chip.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Register Offsets *********************************************************/ + +#define STM32_RNG_CR_OFFSET 0x0000 /* RNG Control Register */ +#define STM32_RNG_SR_OFFSET 0x0004 /* RNG Status Register */ +#define STM32_RNG_DR_OFFSET 0x0008 /* RNG Data Register */ + +/* Register Addresses *******************************************************/ + +#define STM32_RNG_CR (STM32_RNG_BASE+STM32_RNG_CR_OFFSET) +#define STM32_RNG_SR (STM32_RNG_BASE+STM32_RNG_SR_OFFSET) +#define STM32_RNG_DR (STM32_RNG_BASE+STM32_RNG_DR_OFFSET) + +/* Register Bitfield Definitions ********************************************/ + +/* RNG Control Register */ + +#define RNG_CR_RNGEN (1 << 2) /* Bit 2: RNG enable */ +#define RNG_CR_IE (1 << 3) /* Bit 3: Interrupt enable */ + +/* RNG Status Register */ + +#define RNG_SR_DRDY (1 << 0) /* Bit 0: Data ready */ +#define RNG_SR_CECS (1 << 1) /* Bit 1: Clock error current status */ +#define RNG_SR_SECS (1 << 2) /* Bit 2: Seed error current status */ +#define RNG_SR_CEIS (1 << 5) /* Bit 5: Clock error interrupt status */ +#define RNG_SR_SEIS (1 << 6) /* Bit 6: Seed error interrupt status */ + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_RNG_V1_H */ diff --git a/arch/arm/src/common/stm32/hardware/stm32_rtc.h b/arch/arm/src/common/stm32/hardware/stm32_rtc.h new file mode 100644 index 0000000000000..b80f73f118f07 --- /dev/null +++ b/arch/arm/src/common/stm32/hardware/stm32_rtc.h @@ -0,0 +1,83 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/hardware/stm32_rtc.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_RTC_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_RTC_H + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Register Offsets *********************************************************/ + +#define STM32_RTC_CRH_OFFSET 0x0000 /* RTC control register High (16-bit) */ +#define STM32_RTC_CRL_OFFSET 0x0004 /* RTC control register low (16-bit) */ +#define STM32_RTC_PRLH_OFFSET 0x0008 /* RTC prescaler load register high (16-bit) */ +#define STM32_RTC_PRLL_OFFSET 0x000c /* RTC prescaler load register low (16-bit) */ +#define STM32_RTC_DIVH_OFFSET 0x0010 /* RTC prescaler divider register high (16-bit) */ +#define STM32_RTC_DIVL_OFFSET 0x0014 /* RTC prescaler divider register low (16-bit) */ +#define STM32_RTC_CNTH_OFFSET 0x0018 /* RTC counter register high (16-bit) */ +#define STM32_RTC_CNTL_OFFSET 0x001c /* RTC counter register low (16-bit) */ +#define STM32_RTC_ALRH_OFFSET 0x0020 /* RTC alarm register high (16-bit) */ +#define STM32_RTC_ALRL_OFFSET 0x0024 /* RTC alarm register low (16-bit) */ + +/* Register Addresses *******************************************************/ + +#define STM32_RTC_CRH (STM32_RTC_BASE+STM32_RTC_CRH_OFFSET) +#define STM32_RTC_CRL (STM32_RTC_BASE+STM32_RTC_CRL_OFFSET) +#define STM32_RTC_PRLH (STM32_RTC_BASE+STM32_RTC_PRLH_OFFSET) +#define STM32_RTC_PRLL (STM32_RTC_BASE+STM32_RTC_PRLL_OFFSET) +#define STM32_RTC_DIVH (STM32_RTC_BASE+STM32_RTC_DIVH_OFFSET) +#define STM32_RTC_DIVL (STM32_RTC_BASE+STM32_RTC_DIVL_OFFSET) +#define STM32_RTC_CNTH (STM32_RTC_BASE+STM32_RTC_CNTH_OFFSET) +#define STM32_RTC_CNTL (STM32_RTC_BASE+STM32_RTC_CNTL_OFFSET) +#define STM32_RTC_ALRH (STM32_RTC_BASE+STM32_RTC_ALRH_OFFSET) +#define STM32_RTC_ALRL (STM32_RTC_BASE+STM32_RTC_ALRL_OFFSET) + +/* Register Bitfield Definitions ********************************************/ + +/* RTC control register High (16-bit) */ + +#define RTC_CRH_SECIE (1 << 0) /* Bit 0 : Second Interrupt Enable */ +#define RTC_CRH_ALRIE (1 << 1) /* Bit 1: Alarm Interrupt Enable */ +#define RTC_CRH_OWIE (1 << 2) /* Bit 2: OverfloW Interrupt Enable */ + +/* RTC control register low (16-bit) */ + +#define RTC_CRL_SECF (1 << 0) /* Bit 0: Second Flag */ +#define RTC_CRL_ALRF (1 << 1) /* Bit 1: Alarm Flag */ +#define RTC_CRL_OWF (1 << 2) /* Bit 2: Overflow Flag */ +#define RTC_CRL_RSF (1 << 3) /* Bit 3: Registers Synchronized Flag */ +#define RTC_CRL_CNF (1 << 4) /* Bit 4: Configuration Flag */ +#define RTC_CRL_RTOFF (1 << 5) /* Bit 5: RTC operation OFF */ + +/* RTC prescaler load register high (16-bit) */ + +#define RTC_PRLH_PRL_SHIFT (0) /* Bits 3-0: RTC Prescaler Reload Value High */ +#define RTC_PRLH_PRL_MASK (0x0f << RTC_PRLH_PRL_SHIFT) + +/* RTC prescaler divider register high (16-bit) */ + +#define RTC_DIVH_RTC_DIV_SHIFT (0) /* Bits 3-0: RTC Clock Divider High */ +#define RTC_DIVH_RTC_DIV_MASK (0x0f << RTC_DIVH_RTC_DIV_SHIFT) + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_RTC_H */ diff --git a/arch/arm/src/common/stm32/hardware/stm32_rtcc.h b/arch/arm/src/common/stm32/hardware/stm32_rtcc.h new file mode 100644 index 0000000000000..7431435f80fa7 --- /dev/null +++ b/arch/arm/src/common/stm32/hardware/stm32_rtcc.h @@ -0,0 +1,47 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/hardware/stm32_rtcc.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_RTCC_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_RTCC_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#if (defined(CONFIG_STM32_HAVE_IP_RTCC_M0_V1) + \ + defined(CONFIG_STM32_HAVE_IP_RTCC_M3M4_V1) + \ + defined(CONFIG_STM32_HAVE_IP_RTCC_M3M4_L1) + \ + defined(CONFIG_STM32_HAVE_IP_RTCC_M3M4_F4)) > 1 +# error Only one STM32 RTCC IP version must be selected +#endif + +#if defined(CONFIG_STM32_HAVE_IP_RTCC_M0_V1) +# include "hardware/stm32_rtcc_m0.h" +#elif defined(CONFIG_STM32_HAVE_IP_RTCC_M3M4_V1) || \ + defined(CONFIG_STM32_HAVE_IP_RTCC_M3M4_L1) || \ + defined(CONFIG_STM32_HAVE_IP_RTCC_M3M4_F4) +# include "hardware/stm32_rtcc_v1.h" +#else +# error "Unsupported STM32 RTCC" +#endif + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_RTCC_H */ diff --git a/arch/arm/src/common/stm32/hardware/stm32_rtcc_m0.h b/arch/arm/src/common/stm32/hardware/stm32_rtcc_m0.h new file mode 100644 index 0000000000000..e90b32708968b --- /dev/null +++ b/arch/arm/src/common/stm32/hardware/stm32_rtcc_m0.h @@ -0,0 +1,314 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/hardware/stm32_rtcc_m0.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_RTCC_M0_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_RTCC_M0_H + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Register Offsets *********************************************************/ + +#define STM32_RTC_TR_OFFSET 0x0000 /* RTC time register */ +#define STM32_RTC_DR_OFFSET 0x0004 /* RTC date register */ +#define STM32_RTC_CR_OFFSET 0x0008 /* RTC control register */ +#define STM32_RTC_ISR_OFFSET 0x000c /* RTC initialization and status register */ +#define STM32_RTC_PRER_OFFSET 0x0010 /* RTC prescaler register */ +#define STM32_RTC_WUTR_OFFSET 0x0014 /* RTC wakeup timer register */ +#define STM32_RTC_ALRMAR_OFFSET 0x001c /* RTC alarm A register */ +#define STM32_RTC_WPR_OFFSET 0x0024 /* RTC write protection register */ +#define STM32_RTC_SSR_OFFSET 0x0028 /* RTC sub second register */ +#define STM32_RTC_SHIFTR_OFFSET 0x002c /* RTC shift control register */ +#define STM32_RTC_TSTR_OFFSET 0x0030 /* RTC time stamp time register */ +#define STM32_RTC_TSDR_OFFSET 0x0034 /* RTC time stamp date register */ +#define STM32_RTC_TSSSR_OFFSET 0x0038 /* RTC timestamp sub second register */ +#define STM32_RTC_CALR_OFFSET 0x003c /* RTC calibration register */ +#define STM32_RTC_TAFCR_OFFSET 0x0040 /* RTC tamper and alternate function configuration register */ +#define STM32_RTC_ALRMASSR_OFFSET 0x0044 /* RTC alarm A sub second register */ + +#define STM32_RTC_BKR_OFFSET(n) (0x0050 + ((n) << 2)) +#define STM32_RTC_BK0R_OFFSET 0x0050 /* RTC backup register 0 */ +#define STM32_RTC_BK1R_OFFSET 0x0054 /* RTC backup register 1 */ +#define STM32_RTC_BK2R_OFFSET 0x0058 /* RTC backup register 2 */ +#define STM32_RTC_BK3R_OFFSET 0x005c /* RTC backup register 3 */ +#define STM32_RTC_BK4R_OFFSET 0x0060 /* RTC backup register 4 */ + +/* Register Addresses *******************************************************/ + +#define STM32_RTC_TR (STM32_RTC_BASE + STM32_RTC_TR_OFFSET) +#define STM32_RTC_DR (STM32_RTC_BASE + STM32_RTC_DR_OFFSET) +#define STM32_RTC_CR (STM32_RTC_BASE + STM32_RTC_CR_OFFSET) +#define STM32_RTC_ISR (STM32_RTC_BASE + STM32_RTC_ISR_OFFSET) +#define STM32_RTC_PRER (STM32_RTC_BASE + STM32_RTC_PRER_OFFSET) +#define STM32_RTC_WUTR (STM32_RTC_BASE + STM32_RTC_WUTR_OFFSET) +#define STM32_RTC_ALRMAR (STM32_RTC_BASE + STM32_RTC_ALRMAR_OFFSET) +#define STM32_RTC_WPR (STM32_RTC_BASE + STM32_RTC_WPR_OFFSET) +#define STM32_RTC_SSR (STM32_RTC_BASE + STM32_RTC_SSR_OFFSET) +#define STM32_RTC_SHIFTR (STM32_RTC_BASE + STM32_RTC_SHIFTR_OFFSET) +#define STM32_RTC_TSTR (STM32_RTC_BASE + STM32_RTC_TSTR_OFFSET) +#define STM32_RTC_TSDR (STM32_RTC_BASE + STM32_RTC_TSDR_OFFSET) +#define STM32_RTC_TSSSR (STM32_RTC_BASE + STM32_RTC_TSSSR_OFFSET) +#define STM32_RTC_CALR (STM32_RTC_BASE + STM32_RTC_CALR_OFFSET) +#define STM32_RTC_TAFCR (STM32_RTC_BASE + STM32_RTC_TAFCR_OFFSET) +#define STM32_RTC_ALRMASSR (STM32_RTC_BASE + STM32_RTC_ALRMASSR_OFFSET) + +#define STM32_RTC_BKR(n) (STM32_RTC_BASE + STM32_RTC_BKR_OFFSET(n)) +#define STM32_RTC_BK0R (STM32_RTC_BASE + STM32_RTC_BK0R_OFFSET) +#define STM32_RTC_BK1R (STM32_RTC_BASE + STM32_RTC_BK1R_OFFSET) +#define STM32_RTC_BK2R (STM32_RTC_BASE + STM32_RTC_BK2R_OFFSET) +#define STM32_RTC_BK3R (STM32_RTC_BASE + STM32_RTC_BK3R_OFFSET) +#define STM32_RTC_BK4R (STM32_RTC_BASE + STM32_RTC_BK4R_OFFSET) + +#define STM32_RTC_BKCOUNT 5 + +/* Register Bitfield Definitions ********************************************/ + +/* RTC time register */ + +#define RTC_TR_SU_SHIFT (0) /* Bits 0-3: Second units in BCD format */ +#define RTC_TR_SU_MASK (15 << RTC_TR_SU_SHIFT) +#define RTC_TR_ST_SHIFT (4) /* Bits 4-6: Second tens in BCD format */ +#define RTC_TR_ST_MASK (7 << RTC_TR_ST_SHIFT) +#define RTC_TR_MNU_SHIFT (8) /* Bit 8-11: Minute units in BCD format */ +#define RTC_TR_MNU_MASK (15 << RTC_TR_MNU_SHIFT) +#define RTC_TR_MNT_SHIFT (12) /* Bits 12-14: Minute tens in BCD format */ +#define RTC_TR_MNT_MASK (7 << RTC_TR_MNT_SHIFT) +#define RTC_TR_HU_SHIFT (16) /* Bit 16-19: Hour units in BCD format */ +#define RTC_TR_HU_MASK (15 << RTC_TR_HU_SHIFT) +#define RTC_TR_HT_SHIFT (20) /* Bits 20-21: Hour tens in BCD format */ +#define RTC_TR_HT_MASK (3 << RTC_TR_HT_SHIFT) +#define RTC_TR_PM (1 << 22) /* Bit 22: AM/PM notation */ +#define RTC_TR_RESERVED_BITS (0xff808080) + +/* RTC date register */ + +#define RTC_DR_DU_SHIFT (0) /* Bits 0-3: Date units in BCD format */ +#define RTC_DR_DU_MASK (15 << RTC_DR_DU_SHIFT) +#define RTC_DR_DT_SHIFT (4) /* Bits 4-5: Date tens in BCD format */ +#define RTC_DR_DT_MASK (3 << RTC_DR_DT_SHIFT) +#define RTC_DR_MU_SHIFT (8) /* Bits 8-11: Month units in BCD format */ +#define RTC_DR_MU_MASK (15 << RTC_DR_MU_SHIFT) +#define RTC_DR_MT (1 << 12) /* Bit 12: Month tens in BCD format */ +#define RTC_DR_WDU_SHIFT (13) /* Bits 13-15: Week day units */ +#define RTC_DR_WDU_MASK (7 << RTC_DR_WDU_SHIFT) +# define RTC_DR_WDU_MONDAY (1 << RTC_DR_WDU_SHIFT) +# define RTC_DR_WDU_TUESDAY (2 << RTC_DR_WDU_SHIFT) +# define RTC_DR_WDU_WEDNESDAY (3 << RTC_DR_WDU_SHIFT) +# define RTC_DR_WDU_THURSDAY (4 << RTC_DR_WDU_SHIFT) +# define RTC_DR_WDU_FRIDAY (5 << RTC_DR_WDU_SHIFT) +# define RTC_DR_WDU_SATURDAY (6 << RTC_DR_WDU_SHIFT) +# define RTC_DR_WDU_SUNDAY (7 << RTC_DR_WDU_SHIFT) +#define RTC_DR_YU_SHIFT (16) /* Bits 16-19: Year units in BCD format */ +#define RTC_DR_YU_MASK (15 << RTC_DR_YU_SHIFT) +#define RTC_DR_YT_SHIFT (20) /* Bits 20-23: Year tens in BCD format */ +#define RTC_DR_YT_MASK (15 << RTC_DR_YT_SHIFT) +#define RTC_DR_RESERVED_BITS (0xff0000c0) + +/* RTC control register */ + +#define RTC_CR_WUCKSEL_SHIFT (0) /* Bits 0-2: Wakeup clock selection */ +#define RTC_CR_WUCKSEL_MASK (7 << RTC_CR_WUCKSEL_SHIFT) +# define RTC_CR_WUCKSEL_RTCDIV16 (0 << RTC_CR_WUCKSEL_SHIFT) /* 000: RTC/16 clock is selected */ +# define RTC_CR_WUCKSEL_RTCDIV8 (1 << RTC_CR_WUCKSEL_SHIFT) /* 001: RTC/8 clock is selected */ +# define RTC_CR_WUCKSEL_RTCDIV4 (2 << RTC_CR_WUCKSEL_SHIFT) /* 010: RTC/4 clock is selected */ +# define RTC_CR_WUCKSEL_RTCDIV2 (3 << RTC_CR_WUCKSEL_SHIFT) /* 011: RTC/2 clock is selected */ +# define RTC_CR_WUCKSEL_CKSPRE (4 << RTC_CR_WUCKSEL_SHIFT) /* 10x: ck_spre clock is selected */ +# define RTC_CR_WUCKSEL_CKSPREADD (6 << RTC_CR_WUCKSEL_SHIFT) /* 11x: ck_spr clock and 216 added WUT counter */ + +#define RTC_CR_TSEDGE (1 << 3) /* Bit 3: Timestamp event active edge */ +#define RTC_CR_REFCKON (1 << 4) /* Bit 4: Reference clock detection enable (50 or 60 Hz) */ +#define RTC_CR_BYPSHAD (1 << 5) /* Bit 5: Bypass the shadow registers */ +#define RTC_CR_FMT (1 << 6) /* Bit 6: Hour format */ +#define RTC_CR_ALRAE (1 << 8) /* Bit 8: Alarm A enable */ +#define RTC_CR_WUTE (1 << 10) /* Bit 10: Wakeup timer enable */ +#define RTC_CR_TSE (1 << 11) /* Bit 11: Time stamp enable */ +#define RTC_CR_ALRAIE (1 << 12) /* Bit 12: Alarm A interrupt enable */ +#define RTC_CR_WUTIE (1 << 14) /* Bit 14: Wakeup timer interrupt enable */ +#define RTC_CR_TSIE (1 << 15) /* Bit 15: Timestamp interrupt enable */ +#define RTC_CR_ADD1H (1 << 16) /* Bit 16: Add 1 hour (summer time change) */ +#define RTC_CR_SUB1H (1 << 17) /* Bit 17: Subtract 1 hour (winter time change) */ +#define RTC_CR_BKP (1 << 18) /* Bit 18: Backup */ +#define RTC_CR_COSEL (1 << 19) /* Bit 19: Calibration output selection */ +#define RTC_CR_POL (1 << 20) /* Bit 20: Output polarity */ +#define RTC_CR_OSEL_SHIFT (21) /* Bits 21-22: Output selection */ +#define RTC_CR_OSEL_MASK (3 << RTC_CR_OSEL_SHIFT) +# define RTC_CR_OSEL_DISABLED (0 << RTC_CR_OSEL_SHIFT) /* 00: Output disabled */ +# define RTC_CR_OSEL_ALRMA (1 << RTC_CR_OSEL_SHIFT) /* 01: Alarm A output enabled */ +# define RTC_CR_OSEL_ALRMB (2 << RTC_CR_OSEL_SHIFT) /* 10: Alarm B output enabled */ +# define RTC_CR_OSEL_WUT (3 << RTC_CR_OSEL_SHIFT) /* 11: Wakeup output enabled */ + +#define RTC_CR_COE (1 << 23) /* Bit 23: Calibration output enable */ + +/* RTC initialization and status register */ + +#define RTC_ISR_ALRAWF (1 << 0) /* Bit 0: Alarm A write flag */ +#define RTC_ISR_WUTWF (1 << 2) /* Bit 2: Wakeup timer write flag */ +#define RTC_ISR_SHPF (1 << 3) /* Bit 3: Shift operation pending */ +#define RTC_ISR_INITS (1 << 4) /* Bit 4: Initialization status flag */ +#define RTC_ISR_RSF (1 << 5) /* Bit 5: Registers synchronization flag */ +#define RTC_ISR_INITF (1 << 6) /* Bit 6: Initialization flag */ +#define RTC_ISR_INIT (1 << 7) /* Bit 7: Initialization mode */ +#define RTC_ISR_ALRAF (1 << 8) /* Bit 8: Alarm A flag */ +#define RTC_ISR_WUTF (1 << 10) /* Bit 10: Wakeup timer flag */ +#define RTC_ISR_TSF (1 << 11) /* Bit 11: Timestamp flag */ +#define RTC_ISR_TSOVF (1 << 12) /* Bit 12: Timestamp overflow flag */ +#define RTC_ISR_TAMP1F (1 << 13) /* Bit 13: Tamper detection flag */ +#define RTC_ISR_TAMP2F (1 << 14) /* Bit 14: TAMPER2 detection flag */ +#define RTC_ISR_TAMP3F (1 << 15) /* Bit 15: TAMPER3 detection flag */ +#define RTC_ISR_RECALPF (1 << 16) /* Bit 16: Recalibration pending flag */ +#define RTC_ISR_ALLFLAGS (0x00017fff) + +/* RTC prescaler register */ + +#define RTC_PRER_PREDIV_S_SHIFT (0) /* Bits 0-14: Synchronous prescaler factor */ +#define RTC_PRER_PREDIV_S_MASK (0x7fff << RTC_PRER_PREDIV_S_SHIFT) +#define RTC_PRER_PREDIV_A_SHIFT (16) /* Bits 16-22: Asynchronous prescaler factor */ +#define RTC_PRER_PREDIV_A_MASK (0x7f << RTC_PRER_PREDIV_A_SHIFT) + +/* RTC wakeup timer register */ + +#define RTC_WUTR_MASK (0xffff) /* Bits 15:0 Wakeup auto-reload value bits */ + +/* RTC alarm A register */ + +#define RTC_ALRMR_SU_SHIFT (0) /* Bits 0-3: Second units in BCD format. */ +#define RTC_ALRMR_SU_MASK (15 << RTC_ALRMR_SU_SHIFT) +#define RTC_ALRMR_ST_SHIFT (4) /* Bits 4-6: Second tens in BCD format. */ +#define RTC_ALRMR_ST_MASK (7 << RTC_ALRMR_ST_SHIFT) +#define RTC_ALRMR_MSK1 (1 << 7) /* Bit 7 : Alarm A seconds mask */ +#define RTC_ALRMR_MNU_SHIFT (8) /* Bits 8-11: Minute units in BCD format. */ +#define RTC_ALRMR_MNU_MASK (15 << RTC_ALRMR_MNU_SHIFT) +#define RTC_ALRMR_MNT_SHIFT (12) /* Bits 12-14: Minute tens in BCD format. */ +#define RTC_ALRMR_MNT_MASK (7 << RTC_ALRMR_MNT_SHIFT) +#define RTC_ALRMR_MSK2 (1 << 15) /* Bit 15 : Alarm A minutes mask */ +#define RTC_ALRMR_HU_SHIFT (16) /* Bits 16-19: Hour units in BCD format. */ +#define RTC_ALRMR_HU_MASK (15 << RTC_ALRMR_HU_SHIFT) +#define RTC_ALRMR_HT_SHIFT (20) /* Bits 20-21: Hour tens in BCD format. */ +#define RTC_ALRMR_HT_MASK (3 << RTC_ALRMR_HT_SHIFT) +#define RTC_ALRMR_PM (1 << 22) /* Bit 22 : AM/PM notation */ +#define RTC_ALRMR_MSK3 (1 << 23) /* Bit 23 : Alarm A hours mask */ +#define RTC_ALRMR_DU_SHIFT (24) /* Bits 24-27: Date units or day in BCD format. */ +#define RTC_ALRMR_DU_MASK (15 << RTC_ALRMR_DU_SHIFT) +#define RTC_ALRMR_DT_SHIFT (28) /* Bits 28-29: Date tens in BCD format. */ +#define RTC_ALRMR_DT_MASK (3 << RTC_ALRMR_DT_SHIFT) +#define RTC_ALRMR_WDSEL (1 << 30) /* Bit 30: Week day selection */ +#define RTC_ALRMR_MSK4 (1 << 31) /* Bit 31: Alarm A date mask */ + +/* RTC write protection register */ + +#define RTC_WPR_MASK (0xff) /* Bits 0-7: Write protection key */ + +/* RTC sub second register */ + +#define RTC_SSR_MASK (0xffff) /* Bits 0-15: Sub second value */ + +/* RTC shift control register */ + +#define RTC_SHIFTR_SUBFS_SHIFT (0) /* Bits 0-14: Subtract a fraction of a second */ +#define RTC_SHIFTR_SUBFS_MASK (0x7fff << RTC_SHIFTR_SUBFS_SHIFT) +#define RTC_SHIFTR_ADD1S (1 << 31) /* Bit 31: Add one second */ + +/* RTC time stamp time register */ + +#define RTC_TSTR_SU_SHIFT (0) /* Bits 0-3: Second units in BCD format. */ +#define RTC_TSTR_SU_MASK (15 << RTC_TSTR_SU_SHIFT) +#define RTC_TSTR_ST_SHIFT (4) /* Bits 4-6: Second tens in BCD format. */ +#define RTC_TSTR_ST_MASK (7 << RTC_TSTR_ST_SHIFT) +#define RTC_TSTR_MNU_SHIFT (8) /* Bits 8-11: Minute units in BCD format. */ +#define RTC_TSTR_MNU_MASK (15 << RTC_TSTR_MNU_SHIFT) +#define RTC_TSTR_MNT_SHIFT (12) /* Bits 12-14: Minute tens in BCD format. */ +#define RTC_TSTR_MNT_MASK (7 << RTC_TSTR_MNT_SHIFT) +#define RTC_TSTR_HU_SHIFT (16) /* Bits 16-19: Hour units in BCD format. */ +#define RTC_TSTR_HU_MASK (15 << RTC_TSTR_HU_SHIFT) +#define RTC_TSTR_HT_SHIFT (20) /* Bits 20-21: Hour tens in BCD format. */ +#define RTC_TSTR_HT_MASK (3 << RTC_TSTR_HT_SHIFT) +#define RTC_TSTR_PM (1 << 22) /* Bit 22: AM/PM notation */ + +/* RTC time stamp date register */ + +#define RTC_TSDR_DU_SHIFT (0) /* Bit 0-3: Date units in BCD format */ +#define RTC_TSDR_DU_MASK (15 << RTC_TSDR_DU_SHIFT) +#define RTC_TSDR_DT_SHIFT (4) /* Bits 4-5: Date tens in BCD format */ +#define RTC_TSDR_DT_MASK (3 << RTC_TSDR_DT_SHIFT) +#define RTC_TSDR_MU_SHIFT (8) /* Bits 8-11: Month units in BCD format */ +#define RTC_TSDR_MU_MASK (15 << RTC_TSDR_MU_SHIFT) +#define RTC_TSDR_MT (1 << 12) /* Bit 12: Month tens in BCD format */ +#define RTC_TSDR_WDU_SHIFT (13) /* Bits 13-15: Week day units */ +#define RTC_TSDR_WDU_MASK (7 << RTC_TSDR_WDU_SHIFT) + +/* RTC timestamp sub second register */ + +#define RTC_TSSSR_MASK (0xffff) /* Bits 0-15: Sub second value */ + +/* RTC calibration register */ + +#define RTC_CALR_CALM_SHIFT (0) /* Bits 0-8: Calibration minus */ +#define RTC_CALR_CALM_MASK (0x1ff << RTC_CALR_CALM_SHIFT) +#define RTC_CALR_CALW16 (1 << 13) /* Bit 13: Use a 16-second calibration cycle period */ +#define RTC_CALR_CALW8 (1 << 14) /* Bit 14: Use an 8-second calibration cycle period */ +#define RTC_CALR_CALP (1 << 15) /* Bit 15: Increase frequency of RTC by 488.5 ppm */ + +/* RTC tamper and alternate function configuration register */ + +#define RTC_TAFCR_TAMP1E (1 << 0) /* Bit 0: RTC_TAMP1 input detection enable */ +#define RTC_TAFCR_TAMP1TRG (1 << 1) /* Bit 1: Active level for RTC_TAMP1 input */ +#define RTC_TAFCR_TAMPIE (1 << 2) /* Bit 2: Tamper interrupt enable */ +#define RTC_TAFCR_TAMP3E (1 << 5) /* Bit 5: RTC_TAMP3 detection enable */ +#define RTC_TAFCR_TAMP3TRG (1 << 6) /* Bit 6: Active level for RTC_TAMP3 input */ +#define RTC_TAFCR_TAMPTS (1 << 7) /* Bit 7: Activate timestamp on tamper detection event */ +#define RTC_TAFCR_TAMPFREQ_SHIFT (8) /* Bits 8-10: Tamper sampling frequency */ +#define RTC_TAFCR_TAMPFREQ_MASK (7 << RTC_TAFCR_TAMPFREQ_SHIFT) +# define RTC_TAFCR_TAMPFREQ_DIV32768 (0 << RTC_TAFCR_TAMPFREQ_SHIFT) /* RTCCLK / 32768 (1 Hz) */ +# define RTC_TAFCR_TAMPFREQ_DIV16384 (1 << RTC_TAFCR_TAMPFREQ_SHIFT) /* RTCCLK / 16384 (2 Hz) */ +# define RTC_TAFCR_TAMPFREQ_DIV8192 (2 << RTC_TAFCR_TAMPFREQ_SHIFT) /* RTCCLK / 8192 (4 Hz) */ +# define RTC_TAFCR_TAMPFREQ_DIV4096 (3 << RTC_TAFCR_TAMPFREQ_SHIFT) /* RTCCLK / 4096 (8 Hz) */ +# define RTC_TAFCR_TAMPFREQ_DIV2048 (4 << RTC_TAFCR_TAMPFREQ_SHIFT) /* RTCCLK / 2048 (16 Hz) */ +# define RTC_TAFCR_TAMPFREQ_DIV1024 (5 << RTC_TAFCR_TAMPFREQ_SHIFT) /* RTCCLK / 1024 (32 Hz) */ +# define RTC_TAFCR_TAMPFREQ_DIV512 (6 << RTC_TAFCR_TAMPFREQ_SHIFT) /* RTCCLK / 512 (64 Hz) */ +# define RTC_TAFCR_TAMPFREQ_DIV256 (7 << RTC_TAFCR_TAMPFREQ_SHIFT) /* RTCCLK / 256 (128 Hz) */ + +#define RTC_TAFCR_TAMPFLT_SHIFT (11) /* Bits 11-12: RTC_TAMPx filter count */ +#define RTC_TAFCR_TAMPFLT_MASK (3 << RTC_TAFCR_TAMPFLT_SHIFT) +#define RTC_TAFCR_TAMPPRCH_SHIFT (13) /* Bits 13-14: RTC_TAMPx precharge duration */ +#define RTC_TAFCR_TAMPPRCH_MASK (3 << RTC_TAFCR_TAMPPRCH_SHIFT) +# define RTC_TAFCR_TAMPPRCH_1CYCLE (0 << RTC_TAFCR_TAMPPRCH_SHIFT) /* 1 RTCCLK cycle */ +# define RTC_TAFCR_TAMPPRCH_2CYCLES (1 << RTC_TAFCR_TAMPPRCH_SHIFT) /* 2 RTCCLK cycles */ +# define RTC_TAFCR_TAMPPRCH_4CYCLES (2 << RTC_TAFCR_TAMPPRCH_SHIFT) /* 4 RTCCLK cycles */ +# define RTC_TAFCR_TAMPPRCH_5CYCLES (3 << RTC_TAFCR_TAMPPRCH_SHIFT) /* 8 RTCCLK cycles */ + +#define RTC_TAFCR_TAMPPUDIS (1 << 15) /* Bit 15: RTC_TAMPx pull-up disable */ +#define RTC_TAFCR_PC13VALUE (1 << 18) /* Bit 18: RTC_ALARM output type/PC13 value */ +#define RTC_TAFCR_PC13MODE (1 << 19) /* Bit 19: PC13 mode */ +#define RTC_TAFCR_PC14VALUE (1 << 20) /* Bit 20: PC14 value */ +#define RTC_TAFCR_PC14MODE (1 << 21) /* Bit 21: PC14 mode */ +#define RTC_TAFCR_PC15VALUE (1 << 22) /* Bit 22: PC15 value */ +#define RTC_TAFCR_PC15MODE (1 << 23) /* Bit 23: PC15 mode */ + +/* RTC alarm A sub second register */ + +#define RTC_ALRMSSR_SS_SHIFT (0) /* Bits 0-14: Sub second value */ +#define RTC_ALRMSSR_SS_MASK (0x7fff << RTC_ALRMSSR_SS_SHIFT) +#define RTC_ALRMSSR_MASKSS_SHIFT (24) /* Bits 24-27: Mask the most-significant bits starting at this bit */ +#define RTC_ALRMSSR_MASKSS_MASK (0xf << RTC_ALRMSSR_MASKSS_SHIFT) + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_RTCC_M0_H */ diff --git a/arch/arm/src/common/stm32/hardware/stm32_rtcc_v1.h b/arch/arm/src/common/stm32/hardware/stm32_rtcc_v1.h new file mode 100644 index 0000000000000..278f432ecd89e --- /dev/null +++ b/arch/arm/src/common/stm32/hardware/stm32_rtcc_v1.h @@ -0,0 +1,408 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/hardware/stm32_rtcc_v1.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_RTC_V1C_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_RTC_V1C_H + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Register Offsets *********************************************************/ + +#define STM32_RTC_TR_OFFSET 0x0000 /* RTC time register */ +#define STM32_RTC_DR_OFFSET 0x0004 /* RTC date register */ +#define STM32_RTC_CR_OFFSET 0x0008 /* RTC control register */ +#define STM32_RTC_ISR_OFFSET 0x000c /* RTC initialization and status register */ +#define STM32_RTC_PRER_OFFSET 0x0010 /* RTC prescaler register */ +#define STM32_RTC_WUTR_OFFSET 0x0014 /* RTC wakeup timer register */ +#ifndef CONFIG_STM32_STM32F30XX +# define STM32_RTC_CALIBR_OFFSET 0x0018 /* RTC calibration register */ +#endif +#define STM32_RTC_ALRMAR_OFFSET 0x001c /* RTC alarm A register */ +#define STM32_RTC_ALRMBR_OFFSET 0x0020 /* RTC alarm B register */ +#define STM32_RTC_WPR_OFFSET 0x0024 /* RTC write protection register */ +#define STM32_RTC_SSR_OFFSET 0x0028 /* RTC sub second register */ +#define STM32_RTC_SHIFTR_OFFSET 0x002c /* RTC shift control register */ +#define STM32_RTC_TSTR_OFFSET 0x0030 /* RTC time stamp time register */ +#define STM32_RTC_TSDR_OFFSET 0x0034 /* RTC time stamp date register */ +#define STM32_RTC_TSSSR_OFFSET 0x0038 /* RTC timestamp sub second register */ +#define STM32_RTC_CALR_OFFSET 0x003c /* RTC calibration register */ +#define STM32_RTC_TAFCR_OFFSET 0x0040 /* RTC tamper and alternate function configuration register */ +#define STM32_RTC_ALRMASSR_OFFSET 0x0044 /* RTC alarm A sub second register */ +#define STM32_RTC_ALRMBSSR_OFFSET 0x0048 /* RTC alarm B sub second register */ + +#define STM32_RTC_BKR_OFFSET(n) (0x0050+((n)<<2)) +#define STM32_RTC_BK0R_OFFSET 0x0050 /* RTC backup register 0 */ +#define STM32_RTC_BK1R_OFFSET 0x0054 /* RTC backup register 1 */ +#define STM32_RTC_BK2R_OFFSET 0x0058 /* RTC backup register 2 */ +#define STM32_RTC_BK3R_OFFSET 0x005c /* RTC backup register 3 */ +#define STM32_RTC_BK4R_OFFSET 0x0060 /* RTC backup register 4 */ +#define STM32_RTC_BK5R_OFFSET 0x0064 /* RTC backup register 5 */ +#define STM32_RTC_BK6R_OFFSET 0x0068 /* RTC backup register 6 */ +#define STM32_RTC_BK7R_OFFSET 0x006c /* RTC backup register 7 */ +#define STM32_RTC_BK8R_OFFSET 0x0070 /* RTC backup register 8 */ +#define STM32_RTC_BK9R_OFFSET 0x0074 /* RTC backup register 9 */ +#define STM32_RTC_BK10R_OFFSET 0x0078 /* RTC backup register 10 */ +#define STM32_RTC_BK11R_OFFSET 0x007c /* RTC backup register 11 */ +#define STM32_RTC_BK12R_OFFSET 0x0080 /* RTC backup register 12 */ +#define STM32_RTC_BK13R_OFFSET 0x0084 /* RTC backup register 13 */ +#define STM32_RTC_BK14R_OFFSET 0x0088 /* RTC backup register 14 */ +#define STM32_RTC_BK15R_OFFSET 0x008c /* RTC backup register 15 */ +#ifndef CONFIG_STM32_STM32F30XX +# define STM32_RTC_BK16R_OFFSET 0x0090 /* RTC backup register 16 */ +# define STM32_RTC_BK17R_OFFSET 0x0094 /* RTC backup register 17 */ +# define STM32_RTC_BK18R_OFFSET 0x0098 /* RTC backup register 18 */ +# define STM32_RTC_BK19R_OFFSET 0x009c /* RTC backup register 19 */ +#endif +#ifdef CONFIG_STM32_STM32L15XX +# define STM32_RTC_BK20R_OFFSET 0x00a0 /* RTC backup register 20 */ +# define STM32_RTC_BK21R_OFFSET 0x00a4 /* RTC backup register 21 */ +# define STM32_RTC_BK22R_OFFSET 0x00a8 /* RTC backup register 22 */ +# define STM32_RTC_BK23R_OFFSET 0x00ac /* RTC backup register 23 */ +# define STM32_RTC_BK24R_OFFSET 0x00b0 /* RTC backup register 24 */ +# define STM32_RTC_BK25R_OFFSET 0x00b4 /* RTC backup register 25 */ +# define STM32_RTC_BK26R_OFFSET 0x00b8 /* RTC backup register 26 */ +# define STM32_RTC_BK27R_OFFSET 0x00bc /* RTC backup register 27 */ +# define STM32_RTC_BK28R_OFFSET 0x00c0 /* RTC backup register 28 */ +# define STM32_RTC_BK29R_OFFSET 0x00c4 /* RTC backup register 29 */ +# define STM32_RTC_BK30R_OFFSET 0x00c8 /* RTC backup register 30 */ +# define STM32_RTC_BK31R_OFFSET 0x00cc /* RTC backup register 31 */ +#endif + +/* Register Addresses *******************************************************/ + +#define STM32_RTC_TR (STM32_RTC_BASE+STM32_RTC_TR_OFFSET) +#define STM32_RTC_DR (STM32_RTC_BASE+STM32_RTC_DR_OFFSET) +#define STM32_RTC_CR (STM32_RTC_BASE+STM32_RTC_CR_OFFSET) +#define STM32_RTC_ISR (STM32_RTC_BASE+STM32_RTC_ISR_OFFSET) +#define STM32_RTC_PRER (STM32_RTC_BASE+STM32_RTC_PRER_OFFSET) +#define STM32_RTC_WUTR (STM32_RTC_BASE+STM32_RTC_WUTR_OFFSET) +#ifndef CONFIG_STM32_STM32F30XX +# define STM32_RTC_CALIBR (STM32_RTC_BASE+STM32_RTC_CALIBR_OFFSET) +#endif +#define STM32_RTC_ALRMAR (STM32_RTC_BASE+STM32_RTC_ALRMAR_OFFSET) +#define STM32_RTC_ALRMBR (STM32_RTC_BASE+STM32_RTC_ALRMBR_OFFSET) +#define STM32_RTC_WPR (STM32_RTC_BASE+STM32_RTC_WPR_OFFSET) +#define STM32_RTC_SSR (STM32_RTC_BASE+STM32_RTC_SSR_OFFSET) +#define STM32_RTC_SHIFTR (STM32_RTC_BASE+STM32_RTC_SHIFTR_OFFSET) +#define STM32_RTC_TSTR (STM32_RTC_BASE+STM32_RTC_TSTR_OFFSET) +#define STM32_RTC_TSDR (STM32_RTC_BASE+STM32_RTC_TSDR_OFFSET) +#define STM32_RTC_TSSSR (STM32_RTC_BASE+STM32_RTC_TSSSR_OFFSET) +#define STM32_RTC_CALR (STM32_RTC_BASE+STM32_RTC_CALR_OFFSET) +#define STM32_RTC_TAFCR (STM32_RTC_BASE+STM32_RTC_TAFCR_OFFSET) +#define STM32_RTC_ALRMASSR (STM32_RTC_BASE+STM32_RTC_ALRMASSR_OFFSET) +#define STM32_RTC_ALRMBSSR (STM32_RTC_BASE+STM32_RTC_ALRMBSSR_OFFSET) + +#define STM32_RTC_BKR(n) (STM32_RTC_BASE+STM32_RTC_BKR_OFFSET(n)) +#define STM32_RTC_BK0R (STM32_RTC_BASE+STM32_RTC_BK0R_OFFSET) +#define STM32_RTC_BK1R (STM32_RTC_BASE+STM32_RTC_BK1R_OFFSET) +#define STM32_RTC_BK2R (STM32_RTC_BASE+STM32_RTC_BK2R_OFFSET) +#define STM32_RTC_BK3R (STM32_RTC_BASE+STM32_RTC_BK3R_OFFSET) +#define STM32_RTC_BK4R (STM32_RTC_BASE+STM32_RTC_BK4R_OFFSET) +#define STM32_RTC_BK5R (STM32_RTC_BASE+STM32_RTC_BK5R_OFFSET) +#define STM32_RTC_BK6R (STM32_RTC_BASE+STM32_RTC_BK6R_OFFSET) +#define STM32_RTC_BK7R (STM32_RTC_BASE+STM32_RTC_BK7R_OFFSET) +#define STM32_RTC_BK8R (STM32_RTC_BASE+STM32_RTC_BK8R_OFFSET) +#define STM32_RTC_BK9R (STM32_RTC_BASE+STM32_RTC_BK9R_OFFSET) +#define STM32_RTC_BK10R (STM32_RTC_BASE+STM32_RTC_BK10R_OFFSET) +#define STM32_RTC_BK11R (STM32_RTC_BASE+STM32_RTC_BK11R_OFFSET) +#define STM32_RTC_BK12R (STM32_RTC_BASE+STM32_RTC_BK12R_OFFSET) +#define STM32_RTC_BK13R (STM32_RTC_BASE+STM32_RTC_BK13R_OFFSET) +#define STM32_RTC_BK14R (STM32_RTC_BASE+STM32_RTC_BK14R_OFFSET) +#define STM32_RTC_BK15R (STM32_RTC_BASE+STM32_RTC_BK15R_OFFSET) +#ifndef CONFIG_STM32_STM32F30XX +# define STM32_RTC_BK16R (STM32_RTC_BASE+STM32_RTC_BK16R_OFFSET) +# define STM32_RTC_BK17R (STM32_RTC_BASE+STM32_RTC_BK17R_OFFSET) +# define STM32_RTC_BK18R (STM32_RTC_BASE+STM32_RTC_BK18R_OFFSET) +# define STM32_RTC_BK19R (STM32_RTC_BASE+STM32_RTC_BK19R_OFFSET) +#endif +#ifdef CONFIG_STM32_STM32L15XX +# define STM32_RTC_BK20R (STM32_RTC_BASE+STM32_RTC_BK20R_OFFSET) +# define STM32_RTC_BK21R (STM32_RTC_BASE+STM32_RTC_BK21R_OFFSET) +# define STM32_RTC_BK22R (STM32_RTC_BASE+STM32_RTC_BK22R_OFFSET) +# define STM32_RTC_BK23R (STM32_RTC_BASE+STM32_RTC_BK23R_OFFSET) +# define STM32_RTC_BK24R (STM32_RTC_BASE+STM32_RTC_BK24R_OFFSET) +# define STM32_RTC_BK25R (STM32_RTC_BASE+STM32_RTC_BK25R_OFFSET) +# define STM32_RTC_BK26R (STM32_RTC_BASE+STM32_RTC_BK26R_OFFSET) +# define STM32_RTC_BK27R (STM32_RTC_BASE+STM32_RTC_BK27R_OFFSET) +# define STM32_RTC_BK28R (STM32_RTC_BASE+STM32_RTC_BK28R_OFFSET) +# define STM32_RTC_BK29R (STM32_RTC_BASE+STM32_RTC_BK29R_OFFSET) +# define STM32_RTC_BK30R (STM32_RTC_BASE+STM32_RTC_BK30R_OFFSET) +# define STM32_RTC_BK31R (STM32_RTC_BASE+STM32_RTC_BK31R_OFFSET) +#endif + +#ifdef CONFIG_STM32_STM32F30XX +# define STM32_RTC_BKCOUNT 16 +#elif defined(CONFIG_STM32_STM32L15XX) +# define STM32_RTC_BKCOUNT 32 +#else +# define STM32_RTC_BKCOUNT 20 +#endif + +/* Register Bitfield Definitions ********************************************/ + +/* RTC time register */ + +#define RTC_TR_SU_SHIFT (0) /* Bits 0-3: Second units in BCD format */ +#define RTC_TR_SU_MASK (15 << RTC_TR_SU_SHIFT) +#define RTC_TR_ST_SHIFT (4) /* Bits 4-6: Second tens in BCD format */ +#define RTC_TR_ST_MASK (7 << RTC_TR_ST_SHIFT) +#define RTC_TR_MNU_SHIFT (8) /* Bit 8-11: Minute units in BCD format */ +#define RTC_TR_MNU_MASK (15 << RTC_TR_MNU_SHIFT) +#define RTC_TR_MNT_SHIFT (12) /* Bits 12-14: Minute tens in BCD format */ +#define RTC_TR_MNT_MASK (7 << RTC_TR_MNT_SHIFT) +#define RTC_TR_HU_SHIFT (16) /* Bit 16-19: Hour units in BCD format */ +#define RTC_TR_HU_MASK (15 << RTC_TR_HU_SHIFT) +#define RTC_TR_HT_SHIFT (20) /* Bits 20-21: Hour tens in BCD format */ +#define RTC_TR_HT_MASK (3 << RTC_TR_HT_SHIFT) +#define RTC_TR_PM (1 << 22) /* Bit 22: AM/PM notation */ +#define RTC_TR_RESERVED_BITS (0xff808080) + +/* RTC date register */ + +#define RTC_DR_DU_SHIFT (0) /* Bits 0-3: Date units in BCD format */ +#define RTC_DR_DU_MASK (15 << RTC_DR_DU_SHIFT) +#define RTC_DR_DT_SHIFT (4) /* Bits 4-5: Date tens in BCD format */ +#define RTC_DR_DT_MASK (3 << RTC_DR_DT_SHIFT) +#define RTC_DR_MU_SHIFT (8) /* Bits 8-11: Month units in BCD format */ +#define RTC_DR_MU_MASK (15 << RTC_DR_MU_SHIFT) +#define RTC_DR_MT (1 << 12) /* Bit 12: Month tens in BCD format */ +#define RTC_DR_WDU_SHIFT (13) /* Bits 13-15: Week day units */ +#define RTC_DR_WDU_MASK (7 << RTC_DR_WDU_SHIFT) +# define RTC_DR_WDU_MONDAY (1 << RTC_DR_WDU_SHIFT) +# define RTC_DR_WDU_TUESDAY (2 << RTC_DR_WDU_SHIFT) +# define RTC_DR_WDU_WEDNESDAY (3 << RTC_DR_WDU_SHIFT) +# define RTC_DR_WDU_THURSDAY (4 << RTC_DR_WDU_SHIFT) +# define RTC_DR_WDU_FRIDAY (5 << RTC_DR_WDU_SHIFT) +# define RTC_DR_WDU_SATURDAY (6 << RTC_DR_WDU_SHIFT) +# define RTC_DR_WDU_SUNDAY (7 << RTC_DR_WDU_SHIFT) +#define RTC_DR_YU_SHIFT (16) /* Bits 16-19: Year units in BCD format */ +#define RTC_DR_YU_MASK (15 << RTC_DR_YU_SHIFT) +#define RTC_DR_YT_SHIFT (20) /* Bits 20-23: Year tens in BCD format */ +#define RTC_DR_YT_MASK (15 << RTC_DR_YT_SHIFT) +#define RTC_DR_RESERVED_BITS (0xff0000c0) + +/* RTC control register */ + +#define RTC_CR_WUCKSEL_SHIFT (0) /* Bits 0-2: Wakeup clock selection */ +#define RTC_CR_WUCKSEL_MASK (7 << RTC_CR_WUCKSEL_SHIFT) +# define RTC_CR_WUCKSEL_RTCDIV16 (0 << RTC_CR_WUCKSEL_SHIFT) /* 000: RTC/16 clock is selected */ +# define RTC_CR_WUCKSEL_RTCDIV8 (1 << RTC_CR_WUCKSEL_SHIFT) /* 001: RTC/8 clock is selected */ +# define RTC_CR_WUCKSEL_RTCDIV4 (2 << RTC_CR_WUCKSEL_SHIFT) /* 010: RTC/4 clock is selected */ +# define RTC_CR_WUCKSEL_RTCDIV2 (3 << RTC_CR_WUCKSEL_SHIFT) /* 011: RTC/2 clock is selected */ +# define RTC_CR_WUCKSEL_CKSPRE (4 << RTC_CR_WUCKSEL_SHIFT) /* 10x: ck_spre clock is selected */ +# define RTC_CR_WUCKSEL_CKSPREADD (6 << RTC_CR_WUCKSEL_SHIFT) /* 11x: ck_spr clock and 216 added WUT counter */ + +#define RTC_CR_TSEDGE (1 << 3) /* Bit 3: Timestamp event active edge */ +#define RTC_CR_REFCKON (1 << 4) /* Bit 4: Reference clock detection enable (50 or 60 Hz) */ +#define RTC_CR_BYPSHAD (1 << 5) /* Bit 5: Bypass the shadow registers */ +#define RTC_CR_FMT (1 << 6) /* Bit 6: Hour format */ +#define RTC_CR_DCE (1 << 7) /* Bit 7: Coarse digital calibration enable */ +#define RTC_CR_ALRAE (1 << 8) /* Bit 8: Alarm A enable */ +#define RTC_CR_ALRBE (1 << 9) /* Bit 9: Alarm B enable */ +#define RTC_CR_WUTE (1 << 10) /* Bit 10: Wakeup timer enable */ +#define RTC_CR_TSE (1 << 11) /* Bit 11: Time stamp enable */ +#define RTC_CR_ALRAIE (1 << 12) /* Bit 12: Alarm A interrupt enable */ +#define RTC_CR_ALRBIE (1 << 13) /* Bit 13: Alarm B interrupt enable */ +#define RTC_CR_WUTIE (1 << 14) /* Bit 14: Wakeup timer interrupt enable */ +#define RTC_CR_TSIE (1 << 15) /* Bit 15: Timestamp interrupt enable */ +#define RTC_CR_ADD1H (1 << 16) /* Bit 16: Add 1 hour (summer time change) */ +#define RTC_CR_SUB1H (1 << 17) /* Bit 17: Subtract 1 hour (winter time change) */ +#define RTC_CR_BKP (1 << 18) /* Bit 18: Backup */ +#define RTC_CR_COSEL (1 << 19) /* Bit 19: Calibration output selection */ +#define RTC_CR_POL (1 << 20) /* Bit 20: Output polarity */ +#define RTC_CR_OSEL_SHIFT (21) /* Bits 21-22: Output selection */ +#define RTC_CR_OSEL_MASK (3 << RTC_CR_OSEL_SHIFT) +# define RTC_CR_OSEL_DISABLED (0 << RTC_CR_OSEL_SHIFT) /* 00: Output disabled */ +# define RTC_CR_OSEL_ALRMA (1 << RTC_CR_OSEL_SHIFT) /* 01: Alarm A output enabled */ +# define RTC_CR_OSEL_ALRMB (2 << RTC_CR_OSEL_SHIFT) /* 10: Alarm B output enabled */ +# define RTC_CR_OSEL_WUT (3 << RTC_CR_OSEL_SHIFT) /* 11: Wakeup output enabled */ + +#define RTC_CR_COE (1 << 23) /* Bit 23: Calibration output enable */ + +/* RTC initialization and status register */ + +#define RTC_ISR_ALRAWF (1 << 0) /* Bit 0: Alarm A write flag */ +#define RTC_ISR_ALRBWF (1 << 1) /* Bit 1: Alarm B write flag */ +#define RTC_ISR_WUTWF (1 << 2) /* Bit 2: Wakeup timer write flag */ +#define RTC_ISR_SHPF (1 << 3) /* Bit 3: Shift operation pending */ +#define RTC_ISR_INITS (1 << 4) /* Bit 4: Initialization status flag */ +#define RTC_ISR_RSF (1 << 5) /* Bit 5: Registers synchronization flag */ +#define RTC_ISR_INITF (1 << 6) /* Bit 6: Initialization flag */ +#define RTC_ISR_INIT (1 << 7) /* Bit 7: Initialization mode */ +#define RTC_ISR_ALRAF (1 << 8) /* Bit 8: Alarm A flag */ +#define RTC_ISR_ALRBF (1 << 9) /* Bit 9: Alarm B flag */ +#define RTC_ISR_WUTF (1 << 10) /* Bit 10: Wakeup timer flag */ +#define RTC_ISR_TSF (1 << 11) /* Bit 11: Timestamp flag */ +#define RTC_ISR_TSOVF (1 << 12) /* Bit 12: Timestamp overflow flag */ +#define RTC_ISR_TAMP1F (1 << 13) /* Bit 13: Tamper detection flag */ +#define RTC_ISR_TAMP2F (1 << 14) /* Bit 14: TAMPER2 detection flag */ +#ifdef CONFIG_STM32_STM32L15XX +# define RTC_ISR_TAMP3F (1 << 15) /* Bit 15: TAMPER3 detection flag */ +#endif +#define RTC_ISR_RECALPF (1 << 16) /* Bit 16: Recalibration pending flag */ +#define RTC_ISR_ALLFLAGS (0x00017fff) + +/* RTC prescaler register */ + +#define RTC_PRER_PREDIV_S_SHIFT (0) /* Bits 0-14: Synchronous prescaler factor */ +#define RTC_PRER_PREDIV_S_MASK (0x7fff << RTC_PRER_PREDIV_S_SHIFT) +#define RTC_PRER_PREDIV_A_SHIFT (16) /* Bits 16-22: Asynchronous prescaler factor */ +#define RTC_PRER_PREDIV_A_MASK (0x7f << RTC_PRER_PREDIV_A_SHIFT) + +/* RTC wakeup timer register */ + +#define RTC_WUTR_MASK (0xffff) /* Bits 15:0 Wakeup auto-reload value bits */ + +/* RTC calibration register */ + +#ifndef CONFIG_STM32_STM32F30XX +# define RTC_CALIBR_DCS (1 << 7) /* Bit 7 Digital calibration sign */ +# define RTC_CALIBR_DC_SHIFT (0) /* Bits 4:0 0-4: Digital calibration */ +# define RTC_CALIBR_DC_MASK (31 << RTC_CALIBR_DC_SHIFT) +# define RTC_CALIBR_DC(n) (((n) >> 2) << RTC_CALIBR_DC_SHIFT) /* n= 0, 4, 8, ... 126 */ +#endif + +/* RTC alarm A/B registers */ + +#define RTC_ALRMR_SU_SHIFT (0) /* Bits 0-3: Second units in BCD format. */ +#define RTC_ALRMR_SU_MASK (15 << RTC_ALRMR_SU_SHIFT) +#define RTC_ALRMR_ST_SHIFT (4) /* Bits 4-6: Second tens in BCD format. */ +#define RTC_ALRMR_ST_MASK (7 << RTC_ALRMR_ST_SHIFT) +#define RTC_ALRMR_MSK1 (1 << 7) /* Bit 7 : Alarm A seconds mask */ +#define RTC_ALRMR_MNU_SHIFT (8) /* Bits 8-11: Minute units in BCD format. */ +#define RTC_ALRMR_MNU_MASK (15 << RTC_ALRMR_MNU_SHIFT) +#define RTC_ALRMR_MNT_SHIFT (12) /* Bits 12-14: Minute tens in BCD format. */ +#define RTC_ALRMR_MNT_MASK (7 << RTC_ALRMR_MNT_SHIFT) +#define RTC_ALRMR_MSK2 (1 << 15) /* Bit 15 : Alarm A minutes mask */ +#define RTC_ALRMR_HU_SHIFT (16) /* Bits 16-19: Hour units in BCD format. */ +#define RTC_ALRMR_HU_MASK (15 << RTC_ALRMR_HU_SHIFT) +#define RTC_ALRMR_HT_SHIFT (20) /* Bits 20-21: Hour tens in BCD format. */ +#define RTC_ALRMR_HT_MASK (3 << RTC_ALRMR_HT_SHIFT) +#define RTC_ALRMR_PM (1 << 22) /* Bit 22 : AM/PM notation */ +#define RTC_ALRMR_MSK3 (1 << 23) /* Bit 23 : Alarm A hours mask */ +#define RTC_ALRMR_DU_SHIFT (24) /* Bits 24-27: Date units or day in BCD format. */ +#define RTC_ALRMR_DU_MASK (15 << RTC_ALRMR_DU_SHIFT) +#define RTC_ALRMR_DT_SHIFT (28) /* Bits 28-29: Date tens in BCD format. */ +#define RTC_ALRMR_DT_MASK (3 << RTC_ALRMR_DT_SHIFT) +#define RTC_ALRMR_WDSEL (1 << 30) /* Bit 30: Week day selection */ +#define RTC_ALRMR_MSK4 (1 << 31) /* Bit 31: Alarm A date mask */ + +/* RTC write protection register */ + +#define RTC_WPR_MASK (0xff) /* Bits 0-7: Write protection key */ + +/* RTC sub second register */ + +#define RTC_SSR_MASK (0xffff) /* Bits 0-15: Sub second value */ + +/* RTC shift control register */ + +#define RTC_SHIFTR_SUBFS_SHIFT (0) /* Bits 0-14: Subtract a fraction of a second */ +#define RTC_SHIFTR_SUBFS_MASK (0x7fff << RTC_SHIFTR_SUBFS_SHIFT) +#define RTC_SHIFTR_ADD1S (1 << 31) /* Bit 31: Add one second */ + +/* RTC time stamp time register */ + +#define RTC_TSTR_SU_SHIFT (0) /* Bits 0-3: Second units in BCD format. */ +#define RTC_TSTR_SU_MASK (15 << RTC_TSTR_SU_SHIFT) +#define RTC_TSTR_ST_SHIFT (4) /* Bits 4-6: Second tens in BCD format. */ +#define RTC_TSTR_ST_MASK (7 << RTC_TSTR_ST_SHIFT) +#define RTC_TSTR_MNU_SHIFT (8) /* Bits 8-11: Minute units in BCD format. */ +#define RTC_TSTR_MNU_MASK (15 << RTC_TSTR_MNU_SHIFT) +#define RTC_TSTR_MNT_SHIFT (12) /* Bits 12-14: Minute tens in BCD format. */ +#define RTC_TSTR_MNT_MASK (7 << RTC_TSTR_MNT_SHIFT) +#define RTC_TSTR_HU_SHIFT (16) /* Bits 16-19: Hour units in BCD format. */ +#define RTC_TSTR_HU_MASK (15 << RTC_TSTR_HU_SHIFT) +#define RTC_TSTR_HT_SHIFT (20) /* Bits 20-21: Hour tens in BCD format. */ +#define RTC_TSTR_HT_MASK (3 << RTC_TSTR_HT_SHIFT) +#define RTC_TSTR_PM (1 << 22) /* Bit 22: AM/PM notation */ + +/* RTC time stamp date register */ + +#define RTC_TSDR_DU_SHIFT (0) /* Bit 0-3: Date units in BCD format */ +#define RTC_TSDR_DU_MASK (15 << RTC_TSDR_DU_SHIFT) +#define RTC_TSDR_DT_SHIFT (4) /* Bits 4-5: Date tens in BCD format */ +#define RTC_TSDR_DT_MASK (3 << RTC_TSDR_DT_SHIFT) +#define RTC_TSDR_MU_SHIFT (8) /* Bits 8-11: Month units in BCD format */ +#define RTC_TSDR_MU_MASK (15 << RTC_TSDR_MU_SHIFT) +#define RTC_TSDR_MT (1 << 12) /* Bit 12: Month tens in BCD format */ +#define RTC_TSDR_WDU_SHIFT (13) /* Bits 13-15: Week day units */ +#define RTC_TSDR_WDU_MASK (7 << RTC_TSDR_WDU_SHIFT) + +/* RTC timestamp sub second register */ + +#define RTC_TSSSR_MASK (0xffff) /* Bits 0-15: Sub second value */ + +/* RTC calibration register */ + +#define RTC_CALR_CALM_SHIFT (0) /* Bits 0-8: Calibration minus */ +#define RTC_CALR_CALM_MASK (0x1ff << RTC_CALR_CALM_SHIFT) +#define RTC_CALR_CALW16 (1 << 13) /* Bit 13: Use a 16-second calibration cycle period */ +#define RTC_CALR_CALW8 (1 << 14) /* Bit 14: Use an 8-second calibration cycle period */ +#define RTC_CALR_CALP (1 << 15) /* Bit 15: Increase frequency of RTC by 488.5 ppm */ + +/* RTC tamper and alternate function configuration register */ + +#define RTC_TAFCR_TAMP1E (1 << 0) /* Bit 0: RTC_TAMP1 input detection enable */ +#define RTC_TAFCR_TAMP1TRG (1 << 1) /* Bit 1: Active level for RTC_TAMP1 input */ +#define RTC_TAFCR_TAMPIE (1 << 2) /* Bit 2: Tamper interrupt enable */ +#define RTC_TAFCR_TAMP3E (1 << 5) /* Bit 5: RTC_TAMP3 detection enable */ +#define RTC_TAFCR_TAMP3TRG (1 << 6) /* Bit 6: Active level for RTC_TAMP3 input */ +#define RTC_TAFCR_TAMPTS (1 << 7) /* Bit 7: Activate timestamp on tamper detection event */ +#define RTC_TAFCR_TAMPFREQ_SHIFT (8) /* Bits 8-10: Tamper sampling frequency */ +#define RTC_TAFCR_TAMPFREQ_MASK (7 << RTC_TAFCR_TAMPFREQ_SHIFT) +# define RTC_TAFCR_TAMPFREQ_DIV32768 (0 << RTC_TAFCR_TAMPFREQ_SHIFT) /* RTCCLK / 32768 (1 Hz) */ +# define RTC_TAFCR_TAMPFREQ_DIV16384 (1 << RTC_TAFCR_TAMPFREQ_SHIFT) /* RTCCLK / 16384 (2 Hz) */ +# define RTC_TAFCR_TAMPFREQ_DIV8192 (2 << RTC_TAFCR_TAMPFREQ_SHIFT) /* RTCCLK / 8192 (4 Hz) */ +# define RTC_TAFCR_TAMPFREQ_DIV4096 (3 << RTC_TAFCR_TAMPFREQ_SHIFT) /* RTCCLK / 4096 (8 Hz) */ +# define RTC_TAFCR_TAMPFREQ_DIV2048 (4 << RTC_TAFCR_TAMPFREQ_SHIFT) /* RTCCLK / 2048 (16 Hz) */ +# define RTC_TAFCR_TAMPFREQ_DIV1024 (5 << RTC_TAFCR_TAMPFREQ_SHIFT) /* RTCCLK / 1024 (32 Hz) */ +# define RTC_TAFCR_TAMPFREQ_DIV512 (6 << RTC_TAFCR_TAMPFREQ_SHIFT) /* RTCCLK / 512 (64 Hz) */ +# define RTC_TAFCR_TAMPFREQ_DIV256 (7 << RTC_TAFCR_TAMPFREQ_SHIFT) /* RTCCLK / 256 (128 Hz) */ + +#define RTC_TAFCR_TAMPFLT_SHIFT (11) /* Bits 11-12: RTC_TAMPx filter count */ +#define RTC_TAFCR_TAMPFLT_MASK (3 << RTC_TAFCR_TAMPFLT_SHIFT) +#define RTC_TAFCR_TAMPPRCH_SHIFT (13) /* Bits 13-14: RTC_TAMPx precharge duration */ +#define RTC_TAFCR_TAMPPRCH_MASK (3 << RTC_TAFCR_TAMPPRCH_SHIFT) +# define RTC_TAFCR_TAMPPRCH_1CYCLE (0 << RTC_TAFCR_TAMPPRCH_SHIFT) /* 1 RTCCLK cycle */ +# define RTC_TAFCR_TAMPPRCH_2CYCLES (1 << RTC_TAFCR_TAMPPRCH_SHIFT) /* 2 RTCCLK cycles */ +# define RTC_TAFCR_TAMPPRCH_4CYCLES (2 << RTC_TAFCR_TAMPPRCH_SHIFT) /* 4 RTCCLK cycles */ +# define RTC_TAFCR_TAMPPRCH_5CYCLES (3 << RTC_TAFCR_TAMPPRCH_SHIFT) /* 8 RTCCLK cycles */ + +#define RTC_TAFCR_TAMPPUDIS (1 << 15) /* Bit 15: RTC_TAMPx pull-up disable */ +#define RTC_TAFCR_PC13VALUE (1 << 18) /* Bit 18: RTC_ALARM output type/PC13 value */ +#define RTC_TAFCR_PC13MODE (1 << 19) /* Bit 19: PC13 mode */ +#define RTC_TAFCR_PC14VALUE (1 << 20) /* Bit 20: PC14 value */ +#define RTC_TAFCR_PC14MODE (1 << 21) /* Bit 21: PC14 mode */ +#define RTC_TAFCR_PC15VALUE (1 << 22) /* Bit 22: PC15 value */ +#define RTC_TAFCR_PC15MODE (1 << 23) /* Bit 23: PC15 mode */ + +/* RTC alarm A/B sub second register */ + +#define RTC_ALRMSSR_SS_SHIFT (0) /* Bits 0-14: Sub second value */ +#define RTC_ALRMSSR_SS_MASK (0x7fff << RTC_ALRMSSR_SS_SHIFT) +#define RTC_ALRMSSR_MASKSS_SHIFT (24) /* Bits 24-27: Mask the most-significant bits starting at this bit */ +#define RTC_ALRMSSR_MASKSS_MASK (0xf << RTC_ALRMSSR_MASKSS_SHIFT) + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_RTC_V1C_H */ diff --git a/arch/arm/src/common/stm32/hardware/stm32_sdio.h b/arch/arm/src/common/stm32/hardware/stm32_sdio.h new file mode 100644 index 0000000000000..d9c18c5b7d554 --- /dev/null +++ b/arch/arm/src/common/stm32/hardware/stm32_sdio.h @@ -0,0 +1,279 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/hardware/stm32_sdio.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_SDIO_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_SDIO_H + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Register Offsets *********************************************************/ + +#define STM32_SDIO_POWER_OFFSET 0x0000 /* SDIO power control register */ +#define STM32_SDIO_CLKCR_OFFSET 0x0004 /* SDI clock control register */ +#define STM32_SDIO_ARG_OFFSET 0x0008 /* SDIO argument register */ +#define STM32_SDIO_CMD_OFFSET 0x000c /* SDIO command register */ +#define STM32_SDIO_RESPCMD_OFFSET 0x0010 /* SDIO command response register */ +#define STM32_SDIO_RESP_OFFSET(n) (0x0010+4*(n)) +#define STM32_SDIO_RESP1_OFFSET 0x0014 /* SDIO response 1 register */ +#define STM32_SDIO_RESP2_OFFSET 0x0018 /* SDIO response 2 register */ +#define STM32_SDIO_RESP3_OFFSET 0x001c /* SDIO response 3 register */ +#define STM32_SDIO_RESP4_OFFSET 0x0020 /* SDIO response 4 register */ +#define STM32_SDIO_DTIMER_OFFSET 0x0024 /* SDIO data timer register */ +#define STM32_SDIO_DLEN_OFFSET 0x0028 /* SDIO data length register */ +#define STM32_SDIO_DCTRL_OFFSET 0x002c /* SDIO data control register */ +#define STM32_SDIO_DCOUNT_OFFSET 0x0030 /* SDIO data counter register */ +#define STM32_SDIO_STA_OFFSET 0x0034 /* SDIO status register */ +#define STM32_SDIO_ICR_OFFSET 0x0038 /* SDIO interrupt clear register */ +#define STM32_SDIO_MASK_OFFSET 0x003c /* SDIO mask register */ +#define STM32_SDIO_FIFOCNT_OFFSET 0x0048 /* SDIO FIFO counter register */ +#define STM32_SDIO_FIFO_OFFSET 0x0080 /* SDIO data FIFO register */ + +/* Register Addresses *******************************************************/ + +#define STM32_SDIO_POWER (STM32_SDIO_BASE+STM32_SDIO_POWER_OFFSET) +#define STM32_SDIO_CLKCR (STM32_SDIO_BASE+STM32_SDIO_CLKCR_OFFSET) +#define STM32_SDIO_ARG (STM32_SDIO_BASE+STM32_SDIO_ARG_OFFSET) +#define STM32_SDIO_CMD (STM32_SDIO_BASE+STM32_SDIO_CMD_OFFSET) +#define STM32_SDIO_RESPCMD (STM32_SDIO_BASE+STM32_SDIO_RESPCMD_OFFSET) +#define STM32_SDIO_RESP(n) (STM32_SDIO_BASE+STM32_SDIO_RESP_OFFSET(n)) +#define STM32_SDIO_RESP1 (STM32_SDIO_BASE+STM32_SDIO_RESP1_OFFSET) +#define STM32_SDIO_RESP2 (STM32_SDIO_BASE+STM32_SDIO_RESP2_OFFSET) +#define STM32_SDIO_RESP3 (STM32_SDIO_BASE+STM32_SDIO_RESP3_OFFSET) +#define STM32_SDIO_RESP4 (STM32_SDIO_BASE+STM32_SDIO_RESP4_OFFSET) +#define STM32_SDIO_DTIMER (STM32_SDIO_BASE+STM32_SDIO_DTIMER_OFFSET) +#define STM32_SDIO_DLEN (STM32_SDIO_BASE+STM32_SDIO_DLEN_OFFSET) +#define STM32_SDIO_DCTRL (STM32_SDIO_BASE+STM32_SDIO_DCTRL_OFFSET) +#define STM32_SDIO_DCOUNT (STM32_SDIO_BASE+STM32_SDIO_DCOUNT_OFFSET) +#define STM32_SDIO_STA (STM32_SDIO_BASE+STM32_SDIO_STA_OFFSET) +#define STM32_SDIO_ICR (STM32_SDIO_BASE+STM32_SDIO_ICR_OFFSET) +#define STM32_SDIO_MASK (STM32_SDIO_BASE+STM32_SDIO_MASK_OFFSET) +#define STM32_SDIO_FIFOCNT (STM32_SDIO_BASE+STM32_SDIO_FIFOCNT_OFFSET) +#define STM32_SDIO_FIFO (STM32_SDIO_BASE+STM32_SDIO_FIFO_OFFSET) + +/* Bit-band (BB) base addresses *********************************************/ + +#define STM32_SDIO_OFFSET (STM32_SDIO_BASE-STM32_PERIPH_BASE) + +#define STM32_SDIO_POWER_BB (STM32_PERIPHBB_BASE+((STM32_SDIO_OFFSET+STM32_SDIO_POWER_OFFSET)<<5)) +#define STM32_SDIO_CLKCR_BB (STM32_PERIPHBB_BASE+((STM32_SDIO_OFFSET+STM32_SDIO_CLKCR_OFFSET)<<5)) +#define STM32_SDIO_ARG_BB (STM32_PERIPHBB_BASE+((STM32_SDIO_OFFSET+STM32_SDIO_ARG_OFFSET)<<5)) +#define STM32_SDIO_CMD_BB (STM32_PERIPHBB_BASE+((STM32_SDIO_OFFSET+STM32_SDIO_CMD_OFFSET)<<5)) +#define STM32_SDIO_RESPCMD_BB (STM32_PERIPHBB_BASE+((STM32_SDIO_OFFSET+STM32_SDIO_RESPCMD_OFFSET)<<5)) +#define STM32_SDIO_RESP_BB(n) (STM32_PERIPHBB_BASE+((STM32_SDIO_OFFSET+STM32_SDIO_RESP_OFFSET(n))<<5)) +#define STM32_SDIO_RESP1_BB (STM32_PERIPHBB_BASE+((STM32_SDIO_OFFSET+STM32_SDIO_RESP1_OFFSET)<<5)) +#define STM32_SDIO_RESP2_BB (STM32_PERIPHBB_BASE+((STM32_SDIO_OFFSET+STM32_SDIO_RESP2_OFFSET)<<5)) +#define STM32_SDIO_RESP3_BB (STM32_PERIPHBB_BASE+((STM32_SDIO_OFFSET+STM32_SDIO_RESP3_OFFSET)<<5)) +#define STM32_SDIO_RESP4_BB (STM32_PERIPHBB_BASE+((STM32_SDIO_OFFSET+STM32_SDIO_RESP4_OFFSET)<<5)) +#define STM32_SDIO_DTIMER_BB (STM32_PERIPHBB_BASE+((STM32_SDIO_OFFSET+STM32_SDIO_DTIMER_OFFSET)<<5)) +#define STM32_SDIO_DLEN_BB (STM32_PERIPHBB_BASE+((STM32_SDIO_OFFSET+STM32_SDIO_DLEN_OFFSET)<<5)) +#define STM32_SDIO_DCTRL_BB (STM32_PERIPHBB_BASE+((STM32_SDIO_OFFSET+STM32_SDIO_DCTRL_OFFSET)<<5)) +#define STM32_SDIO_DCOUNT_BB (STM32_PERIPHBB_BASE+((STM32_SDIO_OFFSET+STM32_SDIO_DCOUNT_OFFSET)<<5)) +#define STM32_SDIO_STA_BB (STM32_PERIPHBB_BASE+((STM32_SDIO_OFFSET+STM32_SDIO_STA_OFFSET)<<5)) +#define STM32_SDIO_ICR_BB (STM32_PERIPHBB_BASE+((STM32_SDIO_OFFSET+STM32_SDIO_ICR_OFFSET)<<5)) +#define STM32_SDIO_MASK_BB (STM32_PERIPHBB_BASE+((STM32_SDIO_OFFSET+STM32_SDIO_MASK_OFFSET)<<5)) +#define STM32_SDIO_FIFOCNT_BB (STM32_PERIPHBB_BASE+((STM32_SDIO_OFFSET+STM32_SDIO_FIFOCNT_OFFSET)<<5)) +#define STM32_SDIO_FIFO_BB (STM32_PERIPHBB_BASE+((STM32_SDIO_OFFSET+STM32_SDIO_FIFO_OFFSET)<<5)) + +/* Register Bitfield Definitions ********************************************/ + +#define SDIO_POWER_PWRCTRL_SHIFT (0) /* Bits 0-1: Power supply control bits */ +#define SDIO_POWER_PWRCTRL_MASK (3 << SDIO_POWER_PWRCTRL_SHIFT) +# define SDIO_POWER_PWRCTRL_OFF (0 << SDIO_POWER_PWRCTRL_SHIFT) /* 00: Power-off: card clock stopped */ +# define SDIO_POWER_PWRCTRL_PWRUP (2 << SDIO_POWER_PWRCTRL_SHIFT) /* 10: Reserved power-up */ +# define SDIO_POWER_PWRCTRL_ON (3 << SDIO_POWER_PWRCTRL_SHIFT) /* 11: Power-on: card is clocked */ + +#define SDIO_POWER_RESET (0) /* Reset value */ + +#define SDIO_CLKCR_CLKDIV_SHIFT (0) /* Bits 7-0: Clock divide factor */ +#define SDIO_CLKCR_CLKDIV_MASK (0xff << SDIO_CLKCR_CLKDIV_SHIFT) +#define SDIO_CLKCR_CLKEN (1 << 8) /* Bit 8: Clock enable bit */ +#define SDIO_CLKCR_PWRSAV (1 << 9) /* Bit 9: Power saving configuration bit */ +#define SDIO_CLKCR_BYPASS (1 << 10) /* Bit 10: Clock divider bypass enable bit */ +#define SDIO_CLKCR_WIDBUS_SHIFT (11) /* Bits 12-11: Wide bus mode enable bits */ +#define SDIO_CLKCR_WIDBUS_MASK (3 << SDIO_CLKCR_WIDBUS_SHIFT) +# define SDIO_CLKCR_WIDBUS_D1 (0 << SDIO_CLKCR_WIDBUS_SHIFT) /* 00: Default (SDIO_D0) */ +# define SDIO_CLKCR_WIDBUS_D4 (1 << SDIO_CLKCR_WIDBUS_SHIFT) /* 01: 4-wide (SDIO_D[3:0]) */ +# define SDIO_CLKCR_WIDBUS_D8 (2 << SDIO_CLKCR_WIDBUS_SHIFT) /* 10: 8-wide (SDIO_D[7:0]) */ + +#define SDIO_CLKCR_NEGEDGE (1 << 13) /* Bit 13: SDIO_CK dephasing selection bit */ +#define SDIO_CLKCR_HWFC_EN (1 << 14) /* Bit 14: HW Flow Control enable */ + +#define SDIO_CLKCR_RESET (0) /* Reset value */ +#define SDIO_ARG_RESET (0) /* Reset value */ + +#define SDIO_CLKCR_CLKEN_BB (STM32_SDIO_CLKCR_BB + (8 * 4)) +#define SDIO_CLKCR_PWRSAV_BB (STM32_SDIO_CLKCR_BB + (9 * 4)) +#define SDIO_CLKCR_BYPASS_BB (STM32_SDIO_CLKCR_BB + (10 * 4)) +#define SDIO_CLKCR_NEGEDGE_BB (STM32_SDIO_CLKCR_BB + (13 * 4)) +#define SDIO_CLKCR_HWFC_EN_BB (STM32_SDIO_CLKCR_BB + (14 * 4)) + +#define SDIO_CMD_CMDINDEX_SHIFT (0) +#define SDIO_CMD_CMDINDEX_MASK (0x3f << SDIO_CMD_CMDINDEX_SHIFT) +#define SDIO_CMD_WAITRESP_SHIFT (6) /* Bits 7-6: Wait for response bits */ +#define SDIO_CMD_WAITRESP_MASK (3 << SDIO_CMD_WAITRESP_SHIFT) +# define SDIO_CMD_NORESPONSE (0 << SDIO_CMD_WAITRESP_SHIFT) /* 00/10: No response */ +# define SDIO_CMD_SHORTRESPONSE (1 << SDIO_CMD_WAITRESP_SHIFT) /* 01: Short response */ +# define SDIO_CMD_LONGRESPONSE (3 << SDIO_CMD_WAITRESP_SHIFT) /* 11: Long response */ + +#define SDIO_CMD_WAITINT (1 << 8) /* Bit 8: CPSM waits for interrupt request */ +#define SDIO_CMD_WAITPEND (1 << 9) /* Bit 9: CPSM Waits for ends of data transfer */ +#define SDIO_CMD_CPSMEN (1 << 10) /* Bit 10: Command path state machine enable */ +#define SDIO_CMD_SUSPEND (1 << 11) /* Bit 11: SD I/O suspend command */ +#define SDIO_CMD_ENDCMD (1 << 12) /* Bit 12: Enable CMD completion */ +#define SDIO_CMD_NIEN (1 << 13) /* Bit 13: not Interrupt Enable */ +#define SDIO_CMD_ATACMD (1 << 14) /* Bit 14: CE-ATA command */ + +#define SDIO_CMD_RESET (0) /* Reset value */ + +#define SDIO_CMD_WAITINT_BB (STM32_SDIO_CMD_BB + (8 * 4)) +#define SDIO_CMD_WAITPEND_BB (STM32_SDIO_CMD_BB + (9 * 4)) +#define SDIO_CMD_CPSMEN_BB (STM32_SDIO_CMD_BB + (10 * 4)) +#define SDIO_CMD_SUSPEND_BB (STM32_SDIO_CMD_BB + (11 * 4)) +#define SDIO_CMD_ENCMD_BB (STM32_SDIO_CMD_BB + (12 * 4)) +#define SDIO_CMD_NIEN_BB (STM32_SDIO_CMD_BB + (13 * 4)) +#define SDIO_CMD_ATACMD_BB (STM32_SDIO_CMD_BB + (14 * 4)) + +#define SDIO_RESPCMD_SHIFT (0) +#define SDIO_RESPCMD_MASK (0x3f << SDIO_RESPCMD_SHIFT) + +#define SDIO_DTIMER_RESET (0) /* Reset value */ + +#define SDIO_DLEN_SHIFT (0) +#define SDIO_DLEN_MASK (0x01ffffff << SDIO_DLEN_SHIFT) + +#define SDIO_DLEN_RESET (0) /* Reset value */ + +#define SDIO_DCTRL_DTEN (1 << 0) /* Bit 0: Data transfer enabled bit */ +#define SDIO_DCTRL_DTDIR (1 << 1) /* Bit 1: Data transfer direction */ +#define SDIO_DCTRL_DTMODE (1 << 2) /* Bit 2: Data transfer mode */ +#define SDIO_DCTRL_DMAEN (1 << 3) /* Bit 3: DMA enable bit */ +#define SDIO_DCTRL_DBLOCKSIZE_SHIFT (4) /* Bits 7-4: Data block size */ +#define SDIO_DCTRL_DBLOCKSIZE_MASK (15 << SDIO_DCTRL_DBLOCKSIZE_SHIFT) +# define SDIO_DCTRL_1BYTE (0 << SDIO_DCTRL_DBLOCKSIZE_SHIFT) +# define SDIO_DCTRL_2BYTES (1 << SDIO_DCTRL_DBLOCKSIZE_SHIFT) +# define SDIO_DCTRL_4BYTES (2 << SDIO_DCTRL_DBLOCKSIZE_SHIFT) +# define SDIO_DCTRL_8BYTES (3 << SDIO_DCTRL_DBLOCKSIZE_SHIFT) +# define SDIO_DCTRL_16BYTES (4 << SDIO_DCTRL_DBLOCKSIZE_SHIFT) +# define SDIO_DCTRL_32BYTES (5 << SDIO_DCTRL_DBLOCKSIZE_SHIFT) +# define SDIO_DCTRL_64BYTES (6 << SDIO_DCTRL_DBLOCKSIZE_SHIFT) +# define SDIO_DCTRL_128BYTES (7 << SDIO_DCTRL_DBLOCKSIZE_SHIFT) +# define SDIO_DCTRL_256BYTES (8 << SDIO_DCTRL_DBLOCKSIZE_SHIFT) +# define SDIO_DCTRL_512BYTES (9 << SDIO_DCTRL_DBLOCKSIZE_SHIFT) +# define SDIO_DCTRL_1KBYTE (10 << SDIO_DCTRL_DBLOCKSIZE_SHIFT) +# define SDIO_DCTRL_2KBYTES (11 << SDIO_DCTRL_DBLOCKSIZE_SHIFT) +# define SDIO_DCTRL_4KBYTES (12 << SDIO_DCTRL_DBLOCKSIZE_SHIFT) +# define SDIO_DCTRL_8KBYTES (13 << SDIO_DCTRL_DBLOCKSIZE_SHIFT) +# define SDIO_DCTRL_16KBYTES (14 << SDIO_DCTRL_DBLOCKSIZE_SHIFT) +#define SDIO_DCTRL_RWSTART (1 << 8) /* Bit 8: Read wait start */ +#define SDIO_DCTRL_RWSTOP (1 << 9) /* Bit 9: Read wait stop */ +#define SDIO_DCTRL_RWMOD (1 << 10) /* Bit 10: Read wait mode */ +#define SDIO_DCTRL_SDIOEN (1 << 11) /* Bit 11: SD I/O enable functions */ + +#define SDIO_DCTRL_RESET (0) /* Reset value */ + +#define SDIO_DCTRL_DTEN_BB (STM32_SDIO_DCTRL_BB + (0 * 4)) +#define SDIO_DCTRL_DTDIR_BB (STM32_SDIO_DCTRL_BB + (1 * 4)) +#define SDIO_DCTRL_DTMODE_BB (STM32_SDIO_DCTRL_BB + (2 * 4)) +#define SDIO_DCTRL_DMAEN_BB (STM32_SDIO_DCTRL_BB + (3 * 4)) +#define SDIO_DCTRL_RWSTART_BB (STM32_SDIO_DCTRL_BB + (8 * 4)) +#define SDIO_DCTRL_RWSTOP_BB (STM32_SDIO_DCTRL_BB + (9 * 4)) +#define SDIO_DCTRL_RWMOD_BB (STM32_SDIO_DCTRL_BB + (10 * 4)) +#define SDIO_DCTRL_SDIOEN_BB (STM32_SDIO_DCTRL_BB + (11 * 4)) + +#define SDIO_DATACOUNT_SHIFT (0) +#define SDIO_DATACOUNT_MASK (0x01ffffff << SDIO_DATACOUNT_SHIFT) + +#define SDIO_STA_CCRCFAIL (1 << 0) /* Bit 0: Command response CRC fail */ +#define SDIO_STA_DCRCFAIL (1 << 1) /* Bit 1: Data block CRC fail */ +#define SDIO_STA_CTIMEOUT (1 << 2) /* Bit 2: Command response timeout */ +#define SDIO_STA_DTIMEOUT (1 << 3) /* Bit 3: Data timeout */ +#define SDIO_STA_TXUNDERR (1 << 4) /* Bit 4: Transmit FIFO underrun error */ +#define SDIO_STA_RXOVERR (1 << 5) /* Bit 5: Received FIFO overrun error */ +#define SDIO_STA_CMDREND (1 << 6) /* Bit 6: Command response received */ +#define SDIO_STA_CMDSENT (1 << 7) /* Bit 7: Command sent */ +#define SDIO_STA_DATAEND (1 << 8) /* Bit 8: Data end */ +#define SDIO_STA_STBITERR (1 << 9) /* Bit 9: Start bit not detected */ +#define SDIO_STA_DBCKEND (1 << 10) /* Bit 10: Data block sent/received */ +#define SDIO_STA_CMDACT (1 << 11) /* Bit 11: Command transfer in progress */ +#define SDIO_STA_TXACT (1 << 12) /* Bit 12: Data transmit in progress */ +#define SDIO_STA_RXACT (1 << 13) /* Bit 13: Data receive in progress */ +#define SDIO_STA_TXFIFOHE (1 << 14) /* Bit 14: Transmit FIFO half empty */ +#define SDIO_STA_RXFIFOHF (1 << 15) /* Bit 15: Receive FIFO half full */ +#define SDIO_STA_TXFIFOF (1 << 16) /* Bit 16: Transmit FIFO full */ +#define SDIO_STA_RXFIFOF (1 << 17) /* Bit 17: Receive FIFO full */ +#define SDIO_STA_TXFIFOE (1 << 18) /* Bit 18: Transmit FIFO empty */ +#define SDIO_STA_RXFIFOE (1 << 19) /* Bit 19: Receive FIFO empty */ +#define SDIO_STA_TXDAVL (1 << 20) /* Bit 20: Data available in transmit FIFO */ +#define SDIO_STA_RXDAVL (1 << 21) /* Bit 21: Data available in receive FIFO */ +#define SDIO_STA_SDIOIT (1 << 22) /* Bit 22: SDIO interrupt received */ +#define SDIO_STA_CEATAEND (1 << 23) /* Bit 23: CMD6 CE-ATA command completion */ + +#define SDIO_ICR_CCRCFAILC (1 << 0) /* Bit 0: CCRCFAIL flag clear bit */ +#define SDIO_ICR_DCRCFAILC (1 << 1) /* Bit 1: DCRCFAIL flag clear bit */ +#define SDIO_ICR_CTIMEOUTC (1 << 2) /* Bit 2: CTIMEOUT flag clear bit */ +#define SDIO_ICR_DTIMEOUTC (1 << 3) /* Bit 3: DTIMEOUT flag clear bit */ +#define SDIO_ICR_TXUNDERRC (1 << 4) /* Bit 4: TXUNDERR flag clear bit */ +#define SDIO_ICR_RXOVERRC (1 << 5) /* Bit 5: RXOVERR flag clear bit */ +#define SDIO_ICR_CMDRENDC (1 << 6) /* Bit 6: CMDREND flag clear bit */ +#define SDIO_ICR_CMDSENTC (1 << 7) /* Bit 7: CMDSENT flag clear bit */ +#define SDIO_ICR_DATAENDC (1 << 8) /* Bit 8: DATAEND flag clear bit */ +#define SDIO_ICR_STBITERRC (1 << 9) /* Bit 9: STBITERR flag clear bit */ +#define SDIO_ICR_DBCKENDC (1 << 10) /* Bit 10: DBCKEND flag clear bit */ +#define SDIO_ICR_SDIOITC (1 << 22) /* Bit 22: SDIOIT flag clear bit */ +#define SDIO_ICR_CEATAENDC (1 << 23) /* Bit 23: CEATAEND flag clear bit */ + +#define SDIO_ICR_RESET 0x00c007ff +#define SDIO_ICR_STATICFLAGS 0x000005ff + +#define SDIO_MASK_CCRCFAILIE (1 << 0) /* Bit 0: Command CRC fail interrupt enable */ +#define SDIO_MASK_DCRCFAILIE (1 << 1) /* Bit 1: Data CRC fail interrupt enable */ +#define SDIO_MASK_CTIMEOUTIE (1 << 2) /* Bit 2: Command timeout interrupt enable */ +#define SDIO_MASK_DTIMEOUTIE (1 << 3) /* Bit 3: Data timeout interrupt enable */ +#define SDIO_MASK_TXUNDERRIE (1 << 4) /* Bit 4: Tx FIFO underrun error interrupt enable */ +#define SDIO_MASK_RXOVERRIE (1 << 5) /* Bit 5: Rx FIFO overrun error interrupt enable */ +#define SDIO_MASK_CMDRENDIE (1 << 6) /* Bit 6: Command response received interrupt enable */ +#define SDIO_MASK_CMDSENTIE (1 << 7) /* Bit 7: Command sent interrupt enable */ +#define SDIO_MASK_DATAENDIE (1 << 8) /* Bit 8: Data end interrupt enable */ +#define SDIO_MASK_STBITERRIE (1 << 9) /* Bit 9: Start bit error interrupt enable */ +#define SDIO_MASK_DBCKENDIE (1 << 10) /* Bit 10: Data block end interrupt enable */ +#define SDIO_MASK_CMDACTIE (1 << 11) /* Bit 11: Command acting interrupt enable */ +#define SDIO_MASK_TXACTIE (1 << 12) /* Bit 12: Data transmit acting interrupt enable */ +#define SDIO_MASK_RXACTIE (1 << 13) /* Bit 13: Data receive acting interrupt enable */ +#define SDIO_MASK_TXFIFOHEIE (1 << 14) /* Bit 14: Tx FIFO half empty interrupt enable */ +#define SDIO_MASK_RXFIFOHFIE (1 << 15) /* Bit 15: Rx FIFO half full interrupt enable */ +#define SDIO_MASK_TXFIFOFIE (1 << 16) /* Bit 16: Tx FIFO full interrupt enable */ +#define SDIO_MASK_RXFIFOFIE (1 << 17) /* Bit 17: Rx FIFO full interrupt enable */ +#define SDIO_MASK_TXFIFOEIE (1 << 18) /* Bit 18: Tx FIFO empty interrupt enable */ +#define SDIO_MASK_RXFIFOEIE (1 << 19) /* Bit 19: Rx FIFO empty interrupt enable */ +#define SDIO_MASK_TXDAVLIE (1 << 20) /* Bit 20: Data available in Tx FIFO interrupt enable */ +#define SDIO_MASK_RXDAVLIE (1 << 21) /* Bit 21: Data available in Rx FIFO interrupt enable */ +#define SDIO_MASK_SDIOITIE (1 << 22) /* Bit 22: SDIO mode interrupt received interrupt enable */ +#define SDIO_MASK_CEATAENDIE (1 << 23) /* Bit 23: CE-ATA command completion interrupt enable */ + +#define SDIO_MASK_RESET (0) + +#define SDIO_FIFOCNT_SHIFT (0) +#define SDIO_FIFOCNT_MASK (0x01ffffff << SDIO_FIFOCNT_SHIFT) + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_SDIO_H */ diff --git a/arch/arm/src/common/stm32/hardware/stm32_spi.h b/arch/arm/src/common/stm32/hardware/stm32_spi.h new file mode 100644 index 0000000000000..2d9836336efd0 --- /dev/null +++ b/arch/arm/src/common/stm32/hardware/stm32_spi.h @@ -0,0 +1,54 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/hardware/stm32_spi.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_SPI_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_SPI_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/* The SPI IP version (V1..V4) is independent of the CPU core. The register + * layout is the same, but the M0 and M3/M4 ports currently keep separate + * register headers, so the file is chosen by the standard NuttX core symbol + * (CONFIG_ARCH_CORTEXM0) while the version is core-agnostic. + */ + +#if (defined(CONFIG_STM32_HAVE_IP_SPI_V1) + \ + defined(CONFIG_STM32_HAVE_IP_SPI_V2) + \ + defined(CONFIG_STM32_HAVE_IP_SPI_V3) + \ + defined(CONFIG_STM32_HAVE_IP_SPI_V4)) > 1 +# error Only one STM32 SPI IP version must be selected +#endif + +#if !(defined(CONFIG_STM32_HAVE_IP_SPI_V1) || \ + defined(CONFIG_STM32_HAVE_IP_SPI_V2) || \ + defined(CONFIG_STM32_HAVE_IP_SPI_V3) || \ + defined(CONFIG_STM32_HAVE_IP_SPI_V4)) +# error "Unsupported STM32 SPI" +#elif defined(CONFIG_ARCH_CORTEXM0) +# include "hardware/stm32_spi_v1v2_m0.h" +#else +# include "hardware/stm32_spi_v2v3v4.h" +#endif + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_SPI_H */ diff --git a/arch/arm/src/common/stm32/hardware/stm32_spi_v1v2_m0.h b/arch/arm/src/common/stm32/hardware/stm32_spi_v1v2_m0.h new file mode 100644 index 0000000000000..8d730e7b21fd7 --- /dev/null +++ b/arch/arm/src/common/stm32/hardware/stm32_spi_v1v2_m0.h @@ -0,0 +1,230 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/hardware/stm32_spi_v1v2_m0.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_SPI_V1V2_M0_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_SPI_V1V2_M0_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include "chip.h" + +/* Select STM32 SPI IP core */ + +#if defined(CONFIG_STM32_HAVE_IP_SPI_V2) +# define HAVE_IP_SPI_V2 +#elif defined(CONFIG_STM32_HAVE_IP_SPI_V1) +# define HAVE_IP_SPI_V1 +#else +# error Unsupported STM32 F0/L0/G0/C0 SPI IP +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Maximum allowed speed as per data sheet for all SPIs + * (both pclk1 and pclk2) + */ + +#define STM32_SPI_CLK_MAX 50000000UL + +/* Register Offsets *********************************************************/ + +#define STM32_SPI_CR1_OFFSET 0x0000 /* SPI Control Register 1 (16-bit) */ +#define STM32_SPI_CR2_OFFSET 0x0004 /* SPI control register 2 (16-bit) */ +#define STM32_SPI_SR_OFFSET 0x0008 /* SPI status register (16-bit) */ +#define STM32_SPI_DR_OFFSET 0x000c /* SPI data register (16-bit) */ +#define STM32_SPI_CRCPR_OFFSET 0x0010 /* SPI CRC polynomial register (16-bit) */ +#define STM32_SPI_RXCRCR_OFFSET 0x0014 /* SPI Rx CRC register (16-bit) */ +#define STM32_SPI_TXCRCR_OFFSET 0x0018 /* SPI Tx CRC register (16-bit) */ +#define STM32_SPI_I2SCFGR_OFFSET 0x001c /* I2S configuration register */ +#define STM32_SPI_I2SPR_OFFSET 0x0020 /* I2S prescaler register */ + +/* Register Addresses *******************************************************/ + +#if STM32_NSPI > 0 +# define STM32_SPI1_CR1 (STM32_SPI1_BASE + STM32_SPI_CR1_OFFSET) +# define STM32_SPI1_CR2 (STM32_SPI1_BASE + STM32_SPI_CR2_OFFSET) +# define STM32_SPI1_SR (STM32_SPI1_BASE + STM32_SPI_SR_OFFSET) +# define STM32_SPI1_DR (STM32_SPI1_BASE + STM32_SPI_DR_OFFSET) +# define STM32_SPI1_CRCPR (STM32_SPI1_BASE + STM32_SPI_CRCPR_OFFSET) +# define STM32_SPI1_RXCRCR (STM32_SPI1_BASE + STM32_SPI_RXCRCR_OFFSET) +# define STM32_SPI1_TXCRCR (STM32_SPI1_BASE + STM32_SPI_TXCRCR_OFFSET) +#endif + +#if STM32_NSPI > 1 +# define STM32_SPI2_CR1 (STM32_SPI2_BASE + STM32_SPI_CR1_OFFSET) +# define STM32_SPI2_CR2 (STM32_SPI2_BASE + STM32_SPI_CR2_OFFSET) +# define STM32_SPI2_SR (STM32_SPI2_BASE + STM32_SPI_SR_OFFSET) +# define STM32_SPI2_DR (STM32_SPI2_BASE + STM32_SPI_DR_OFFSET) +# define STM32_SPI2_CRCPR (STM32_SPI2_BASE + STM32_SPI_CRCPR_OFFSET) +# define STM32_SPI2_RXCRCR (STM32_SPI2_BASE + STM32_SPI_RXCRCR_OFFSET) +# define STM32_SPI2_TXCRCR (STM32_SPI2_BASE + STM32_SPI_TXCRCR_OFFSET) +# define STM32_SPI2_I2SCFGR (STM32_SPI2_BASE + STM32_SPI_I2SCFGR_OFFSET) +# define STM32_SPI2_I2SPR (STM32_SPI2_BASE + STM32_SPI_I2SPR_OFFSET) +#endif + +#if STM32_NSPI > 2 +# define STM32_SPI3_CR1 (STM32_SPI3_BASE + STM32_SPI_CR1_OFFSET) +# define STM32_SPI3_CR2 (STM32_SPI3_BASE + STM32_SPI_CR2_OFFSET) +# define STM32_SPI3_SR (STM32_SPI3_BASE + STM32_SPI_SR_OFFSET) +# define STM32_SPI3_DR (STM32_SPI3_BASE + STM32_SPI_DR_OFFSET) +# define STM32_SPI3_CRCPR (STM32_SPI3_BASE + STM32_SPI_CRCPR_OFFSET) +# define STM32_SPI3_RXCRCR (STM32_SPI3_BASE + STM32_SPI_RXCRCR_OFFSET) +# define STM32_SPI3_TXCRCR (STM32_SPI3_BASE + STM32_SPI_TXCRCR_OFFSET) +# define STM32_SPI3_I2SCFGR (STM32_SPI3_BASE + STM32_SPI_I2SCFGR_OFFSET) +# define STM32_SPI3_I2SPR (STM32_SPI3_BASE + STM32_SPI_I2SPR_OFFSET) +#endif + +/* Register Bitfield Definitions ********************************************/ + +/* SPI Control Register 1 */ + +#define SPI_CR1_CPHA (1 << 0) /* Bit 0: Clock Phase */ +#define SPI_CR1_CPOL (1 << 1) /* Bit 1: Clock Polarity */ +#define SPI_CR1_MSTR (1 << 2) /* Bit 2: Master Selection */ +#define SPI_CR1_BR_SHIFT (3) /* Bits 5:3 Baud Rate Control */ +#define SPI_CR1_BR_MASK (7 << SPI_CR1_BR_SHIFT) +# define SPI_CR1_FPCLCKd2 (0 << SPI_CR1_BR_SHIFT) /* 000: fPCLK/2 */ +# define SPI_CR1_FPCLCKd4 (1 << SPI_CR1_BR_SHIFT) /* 001: fPCLK/4 */ +# define SPI_CR1_FPCLCKd8 (2 << SPI_CR1_BR_SHIFT) /* 010: fPCLK/8 */ +# define SPI_CR1_FPCLCKd16 (3 << SPI_CR1_BR_SHIFT) /* 011: fPCLK/16 */ +# define SPI_CR1_FPCLCKd32 (4 << SPI_CR1_BR_SHIFT) /* 100: fPCLK/32 */ +# define SPI_CR1_FPCLCKd64 (5 << SPI_CR1_BR_SHIFT) /* 101: fPCLK/64 */ +# define SPI_CR1_FPCLCKd128 (6 << SPI_CR1_BR_SHIFT) /* 110: fPCLK/128 */ +# define SPI_CR1_FPCLCKd256 (7 << SPI_CR1_BR_SHIFT) /* 111: fPCLK/256 */ + +#define SPI_CR1_SPE (1 << 6) /* Bit 6: SPI Enable */ +#define SPI_CR1_LSBFIRST (1 << 7) /* Bit 7: Frame Format */ +#define SPI_CR1_SSI (1 << 8) /* Bit 8: Internal slave select */ +#define SPI_CR1_SSM (1 << 9) /* Bit 9: Software slave management */ +#define SPI_CR1_RXONLY (1 << 10) /* Bit 10: Receive only */ +# ifdef HAVE_IP_SPI_V2 +# define SPI_CR1_CRCL (1 << 11) /* Bit 11: CRC length */ +#else +# define SPI_CR1_DFF (1 << 11) /* Bit 11: Data frame format */ +#endif +#define SPI_CR1_CRCNEXT (1 << 12) /* Bit 12: Transmit CRC next */ +#define SPI_CR1_CRCEN (1 << 13) /* Bit 13: Hardware CRC calculation enable */ +#define SPI_CR1_BIDIOE (1 << 14) /* Bit 14: Output enable in bidirectional mode */ +#define SPI_CR1_BIDIMODE (1 << 15) /* Bit 15: Bidirectional data mode enable */ + +/* SPI Control Register 2 */ + +#define SPI_CR2_RXDMAEN (1 << 0) /* Bit 0: Rx Buffer DMA Enable */ +#define SPI_CR2_TXDMAEN (1 << 1) /* Bit 1: Tx Buffer DMA Enable */ +#define SPI_CR2_SSOE (1 << 2) /* Bit 2: SS Output Enable */ +#ifdef HAVE_IP_SPI_V2 +# define SPI_CR2_NSSP (1 << 3) /* Bit 3 NSSP: NSS pulse management */ +#endif +#define SPI_CR2_FRF (1 << 4) /* Bit 4: Frame format */ +#define SPI_CR2_ERRIE (1 << 5) /* Bit 5: Error interrupt enable */ +#define SPI_CR2_RXNEIE (1 << 6) /* Bit 6: RX buffer not empty interrupt enable */ +#define SPI_CR2_TXEIE (1 << 7) /* Bit 7: Tx buffer empty interrupt enable */ +#ifdef HAVE_IP_SPI_V2 +# define SPI_CR2_DS_SHIFT (8) /* Bits 8-11: Data size */ +# define SPI_CR2_DS_MASK (0xf << SPI_CR2_DS_SHIFT) +# define SPI_CR2_DS_VAL(bits) (((bits)-1) << SPI_CR2_DS_SHIFT) +# define SPI_CR2_DS_4BIT SPI_CR2_DS_VAL(4) +# define SPI_CR2_DS_5BIT SPI_CR2_DS_VAL(5) +# define SPI_CR2_DS_6BIT SPI_CR2_DS_VAL(6) +# define SPI_CR2_DS_7BIT SPI_CR2_DS_VAL(7) +# define SPI_CR2_DS_8BIT SPI_CR2_DS_VAL(8) +# define SPI_CR2_DS_9BIT SPI_CR2_DS_VAL(9) +# define SPI_CR2_DS_10BIT SPI_CR2_DS_VAL(10) +# define SPI_CR2_DS_11BIT SPI_CR2_DS_VAL(11) +# define SPI_CR2_DS_12BIT SPI_CR2_DS_VAL(12) +# define SPI_CR2_DS_13BIT SPI_CR2_DS_VAL(13) +# define SPI_CR2_DS_14BIT SPI_CR2_DS_VAL(14) +# define SPI_CR2_DS_15BIT SPI_CR2_DS_VAL(15) +# define SPI_CR2_DS_16BIT SPI_CR2_DS_VAL(16) +# define SPI_CR2_FRXTH (1 << 12) /* Bit 12: FIFO reception threshold */ +# define SPI_CR2_LDMARX (1 << 13) /* Bit 13: Last DMA transfer for receptione */ +# define SPI_CR2_LDMATX (1 << 14) /* Bit 14: Last DMA transfer for transmission */ +#endif + +/* SPI status register */ + +#define SPI_SR_RXNE (1 << 0) /* Bit 0: Receive buffer not empty */ +#define SPI_SR_TXE (1 << 1) /* Bit 1: Transmit buffer empty */ +#define SPI_SR_CHSIDE (1 << 2) /* Bit 2: Channel side (i2s) */ +#define SPI_SR_UDR (1 << 3) /* Bit 3: Underrun flag (i2s) */ +#define SPI_SR_CRCERR (1 << 4) /* Bit 4: CRC error flag */ +#define SPI_SR_MODF (1 << 5) /* Bit 5: Mode fault */ +#define SPI_SR_OVR (1 << 6) /* Bit 6: Overrun flag */ +#define SPI_SR_BSY (1 << 7) /* Bit 7: Busy flag */ +#define SPI_SR_FRE (1 << 8) /* Bit 8: Frame format error */ +#ifdef HAVE_IP_SPI_V2 +# define SPI_SR_FRLVL_SHIFT (9) /* Bits 9-10: FIFO reception level */ +# define SPI_SR_FRLVL_MASK (3 << SPI_SR_FRLVL_SHIFT) +# define SPI_SR_FRLVL_EMPTY (0 << SPI_SR_FRLVL_SHIFT) /* FIFO empty */ +# define SPI_SR_FRLVL_QUARTER (1 << SPI_SR_FRLVL_SHIFT) /* 1/4 FIFO */ +# define SPI_SR_FRLVL_HALF (2 << SPI_SR_FRLVL_SHIFT) /* 1/2 FIFO */ +# define SPI_SR_FRLVL_FULL (3 << SPI_SR_FRLVL_SHIFT) /* FIFO full */ + +# define SPI_SR_FTLVL_SHIFT (11) /* Bits 11-12: FIFO transmission level */ +# define SPI_SR_FTLVL_MASK (3 << SPI_SR_FTLVL_SHIFT) +# define SPI_SR_FTLVL_EMPTY (0 << SPI_SR_FTLVL_SHIFT) /* FIFO empty */ +# define SPI_SR_FTLVL_QUARTER (1 << SPI_SR_FTLVL_SHIFT) /* 1/4 FIFO */ +# define SPI_SR_FTLVL_HALF (2 << SPI_SR_FTLVL_SHIFT) /* 1/2 FIFO */ +# define SPI_SR_FTLVL_FULL (3 << SPI_SR_FTLVL_SHIFT) /* FIFO full */ +#endif + +/* I2S configuration register */ + +#define SPI_I2SCFGR_CHLEN (1 << 0) /* Bit 0: Channel length (number of bits per audio channel) */ +#define SPI_I2SCFGR_DATLEN_SHIFT (1) /* Bit 1-2: Data length to be transferred */ +#define SPI_I2SCFGR_DATLEN_MASK (3 << SPI_I2SCFGR_DATLEN_SHIFT) +# define SPI_I2SCFGR_DATLEN_16BIT (0 << SPI_I2SCFGR_DATLEN_SHIFT) /* 00: 16-bit data length */ +# define SPI_I2SCFGR_DATLEN_24BIT (1 << SPI_I2SCFGR_DATLEN_SHIFT) /* 01: 24-bit data length */ +# define SPI_I2SCFGR_DATLEN_32BIT (2 << SPI_I2SCFGR_DATLEN_SHIFT) /* 10: 32-bit data length */ + +#define SPI_I2SCFGR_CKPOL (1 << 3) /* Bit 3: Steady state clock polarity */ +#define SPI_I2SCFGR_I2SSTD_SHIFT (4) /* Bit 4-5: I2S standard selection */ +#define SPI_I2SCFGR_I2SSTD_MASK (3 << SPI_I2SCFGR_I2SSTD_SHIFT) +# define SPI_I2SCFGR_I2SSTD_PHILLIPS (0 << SPI_I2SCFGR_I2SSTD_SHIFT) /* 00: I2S Phillips standard. */ +# define SPI_I2SCFGR_I2SSTD_MSB (1 << SPI_I2SCFGR_I2SSTD_SHIFT) /* 01: MSB justified standard (left justified) */ +# define SPI_I2SCFGR_I2SSTD_LSB (2 << SPI_I2SCFGR_I2SSTD_SHIFT) /* 10: LSB justified standard (right justified) */ +# define SPI_I2SCFGR_I2SSTD_PCM (3 << SPI_I2SCFGR_I2SSTD_SHIFT) /* 11: PCM standard */ + +#define SPI_I2SCFGR_PCMSYNC (1 << 7) /* Bit 7: PCM frame synchronization */ +#define SPI_I2SCFGR_I2SCFG_SHIFT (8) /* Bit 8-9: I2S configuration mode */ +#define SPI_I2SCFGR_I2SCFG_MASK (3 << SPI_I2SCFGR_I2SCFG_SHIFT) +# define SPI_I2SCFGR_I2SCFG_STX (0 << SPI_I2SCFGR_I2SCFG_SHIFT) /* 00: Slave - transmit */ +# define SPI_I2SCFGR_I2SCFG_SRX (1 << SPI_I2SCFGR_I2SCFG_SHIFT) /* 01: Slave - receive */ +# define SPI_I2SCFGR_I2SCFG_MTX (2 << SPI_I2SCFGR_I2SCFG_SHIFT) /* 10: Master - transmit */ +# define SPI_I2SCFGR_I2SCFG_MRX (3 << SPI_I2SCFGR_I2SCFG_SHIFT) /* 11: Master - receive */ + +#define SPI_I2SCFGR_I2SE (1 << 10) /* Bit 10: I2S Enable */ +#define SPI_I2SCFGR_I2SMOD (1 << 11) /* Bit 11: I2S mode selection */ + +/* I2S prescaler register */ + +#define SPI_I2SPR_I2SDIV_SHIFT (0) /* Bit 0-7: I2S Linear prescaler */ +#define SPI_I2SPR_I2SDIV_MASK (0xff << SPI_I2SPR_I2SDIV_SHIFT) +#define SPI_I2SPR_ODD (1 << 8) /* Bit 8: Odd factor for the prescaler */ +#define SPI_I2SPR_MCKOE (1 << 9) /* Bit 9: Master clock output enable */ + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_SPI_V1V2_M0_H */ diff --git a/arch/arm/src/common/stm32/hardware/stm32_spi_v2v3v4.h b/arch/arm/src/common/stm32/hardware/stm32_spi_v2v3v4.h new file mode 100644 index 0000000000000..187df078bf53f --- /dev/null +++ b/arch/arm/src/common/stm32/hardware/stm32_spi_v2v3v4.h @@ -0,0 +1,283 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/hardware/stm32_spi_v2v3v4.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_SPI_V2V3V4_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_SPI_V2V3V4_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include "chip.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* SPI version **************************************************************/ + +/* SPI IP v1 is default unless v2 or greater is specified for this chip */ + +#undef HAVE_SPI_I2S /* No I2S mode in the SPI peripheral */ +#undef HAVE_SPI_I2S_ASTRT /* No I2S asynchronous start capability */ +#undef HAVE_SPI_TI_MODE /* Motorola frame mode only; no TI mode */ +#undef HAVE_SPI_ARB_DATA_SIZE /* Data size 8 or 16 bit; not arbitrary 4-16 bit */ +#undef HAVE_SPI_FIFOS /* No Tx/Rx FIFOs */ +#undef HAVE_SPI_NSSP /* No NSS Pulse Management in master mode */ + +#if defined(CONFIG_STM32_HAVE_IP_SPI_V2) +# define HAVE_SPI_I2S /* Some SPI peripherals have I2S mode */ +# undef HAVE_SPI_I2S_ASTRT /* No I2S asynchronous start capability */ +# define HAVE_SPI_TI_MODE /* Have Motorola and TI frame modes */ +# undef HAVE_SPI_ARB_DATA_SIZE /* Data size 8 or 16 bit; not arbitrary 4-16 bit */ +# undef HAVE_SPI_FIFOS /* No Tx/Rx FIFOs */ +# undef HAVE_SPI_NSSP /* No NSS Pulse Management in master mode */ +#endif + +#if defined(CONFIG_STM32_HAVE_IP_SPI_V3) +# define HAVE_SPI_I2S /* Some SPI peripherals have I2S mode */ +# undef HAVE_SPI_I2S_ASTRT /* No I2S asynchronous start capability */ +# define HAVE_SPI_TI_MODE /* Have Motorola and TI frame modes */ +# define HAVE_SPI_ARB_DATA_SIZE /* Supports arbitrary data size from 4-16 bits */ +# define HAVE_SPI_FIFOS /* Have Tx/Rx FIFOs */ +# undef HAVE_SPI_NSSP /* No NSS Pulse Management in master mode */ +#endif + +#if defined(CONFIG_STM32_HAVE_IP_SPI_V4) +# define HAVE_SPI_I2S /* Some SPI peripherals have I2S mode */ +# define HAVE_SPI_I2S_ASTRT /* Supports I2S asynchronous start capability */ +# define HAVE_SPI_TI_MODE /* Have Motorola and TI frame modes */ +# define HAVE_SPI_ARB_DATA_SIZE /* Supports arbitrary data size from 4-16 bits */ +# define HAVE_SPI_FIFOS /* Have Tx/Rx FIFOs */ +# define HAVE_SPI_NSSP /* Have NSS Pulse Management in master mode */ +#endif + +/* Maximum allowed speed as per specifications for all SPIs */ + +#if defined(CONFIG_STM32_STM32F4XXX) +# define STM32_SPI_CLK_MAX 37500000UL +#else +# define STM32_SPI_CLK_MAX 18000000UL +#endif + +/* Register Offsets *********************************************************/ + +#define STM32_SPI_CR1_OFFSET 0x0000 /* SPI Control Register 1 (16-bit) */ +#define STM32_SPI_CR2_OFFSET 0x0004 /* SPI control register 2 (16-bit) */ +#define STM32_SPI_SR_OFFSET 0x0008 /* SPI status register (16-bit) */ +#define STM32_SPI_DR_OFFSET 0x000c /* SPI data register (16-bit) */ +#define STM32_SPI_CRCPR_OFFSET 0x0010 /* SPI CRC polynomial register (16-bit) */ +#define STM32_SPI_RXCRCR_OFFSET 0x0014 /* SPI Rx CRC register (16-bit) */ +#define STM32_SPI_TXCRCR_OFFSET 0x0018 /* SPI Tx CRC register (16-bit) */ + +#if defined(HAVE_SPI_I2S) +# define STM32_SPI_I2SCFGR_OFFSET 0x001c /* I2S configuration register */ +# define STM32_SPI_I2SPR_OFFSET 0x0020 /* I2S prescaler register */ +#endif + +/* Register Addresses *******************************************************/ + +#if STM32_NSPI > 0 +# define STM32_SPI1_CR1 (STM32_SPI1_BASE + STM32_SPI_CR1_OFFSET) +# define STM32_SPI1_CR2 (STM32_SPI1_BASE + STM32_SPI_CR2_OFFSET) +# define STM32_SPI1_SR (STM32_SPI1_BASE + STM32_SPI_SR_OFFSET) +# define STM32_SPI1_DR (STM32_SPI1_BASE + STM32_SPI_DR_OFFSET) +# define STM32_SPI1_CRCPR (STM32_SPI1_BASE + STM32_SPI_CRCPR_OFFSET) +# define STM32_SPI1_RXCRCR (STM32_SPI1_BASE + STM32_SPI_RXCRCR_OFFSET) +# define STM32_SPI1_TXCRCR (STM32_SPI1_BASE + STM32_SPI_TXCRCR_OFFSET) +#endif + +#if STM32_NSPI > 1 +# define STM32_SPI2_CR1 (STM32_SPI2_BASE + STM32_SPI_CR1_OFFSET) +# define STM32_SPI2_CR2 (STM32_SPI2_BASE + STM32_SPI_CR2_OFFSET) +# define STM32_SPI2_SR (STM32_SPI2_BASE + STM32_SPI_SR_OFFSET) +# define STM32_SPI2_DR (STM32_SPI2_BASE + STM32_SPI_DR_OFFSET) +# define STM32_SPI2_CRCPR (STM32_SPI2_BASE + STM32_SPI_CRCPR_OFFSET) +# define STM32_SPI2_RXCRCR (STM32_SPI2_BASE + STM32_SPI_RXCRCR_OFFSET) +# define STM32_SPI2_TXCRCR (STM32_SPI2_BASE + STM32_SPI_TXCRCR_OFFSET) +# if defined(HAVE_SPI_I2S) +# define STM32_SPI2_I2SCFGR (STM32_SPI2_BASE + STM32_SPI_I2SCFGR_OFFSET) +# define STM32_SPI2_I2SPR (STM32_SPI2_BASE + STM32_SPI_I2SPR_OFFSET) +# endif +#endif + +#if STM32_NSPI > 2 +# define STM32_SPI3_CR1 (STM32_SPI3_BASE + STM32_SPI_CR1_OFFSET) +# define STM32_SPI3_CR2 (STM32_SPI3_BASE + STM32_SPI_CR2_OFFSET) +# define STM32_SPI3_SR (STM32_SPI3_BASE + STM32_SPI_SR_OFFSET) +# define STM32_SPI3_DR (STM32_SPI3_BASE + STM32_SPI_DR_OFFSET) +# define STM32_SPI3_CRCPR (STM32_SPI3_BASE + STM32_SPI_CRCPR_OFFSET) +# define STM32_SPI3_RXCRCR (STM32_SPI3_BASE + STM32_SPI_RXCRCR_OFFSET) +# define STM32_SPI3_TXCRCR (STM32_SPI3_BASE + STM32_SPI_TXCRCR_OFFSET) +# if defined(HAVE_SPI_I2S) +# define STM32_SPI3_I2SCFGR (STM32_SPI3_BASE + STM32_SPI_I2SCFGR_OFFSET) +# define STM32_SPI3_I2SPR (STM32_SPI3_BASE + STM32_SPI_I2SPR_OFFSET) +# endif +#endif + +/* Register Bitfield Definitions ********************************************/ + +/* SPI Control Register 1 */ + +#define SPI_CR1_CPHA (1 << 0) /* Bit 0: Clock Phase */ +#define SPI_CR1_CPOL (1 << 1) /* Bit 1: Clock Polarity */ +#define SPI_CR1_MSTR (1 << 2) /* Bit 2: Master Selection */ +#define SPI_CR1_BR_SHIFT (3) /* Bits 5:3 Baud Rate Control */ +#define SPI_CR1_BR_MASK (7 << SPI_CR1_BR_SHIFT) +# define SPI_CR1_FPCLCKd2 (0 << SPI_CR1_BR_SHIFT) /* 000: fPCLK/2 */ +# define SPI_CR1_FPCLCKd4 (1 << SPI_CR1_BR_SHIFT) /* 001: fPCLK/4 */ +# define SPI_CR1_FPCLCKd8 (2 << SPI_CR1_BR_SHIFT) /* 010: fPCLK/8 */ +# define SPI_CR1_FPCLCKd16 (3 << SPI_CR1_BR_SHIFT) /* 011: fPCLK/16 */ +# define SPI_CR1_FPCLCKd32 (4 << SPI_CR1_BR_SHIFT) /* 100: fPCLK/32 */ +# define SPI_CR1_FPCLCKd64 (5 << SPI_CR1_BR_SHIFT) /* 101: fPCLK/64 */ +# define SPI_CR1_FPCLCKd128 (6 << SPI_CR1_BR_SHIFT) /* 110: fPCLK/128 */ +# define SPI_CR1_FPCLCKd256 (7 << SPI_CR1_BR_SHIFT) /* 111: fPCLK/256 */ +#define SPI_CR1_SPE (1 << 6) /* Bit 6: SPI Enable */ +#define SPI_CR1_LSBFIRST (1 << 7) /* Bit 7: Frame Format */ +#define SPI_CR1_SSI (1 << 8) /* Bit 8: Internal slave select */ +#define SPI_CR1_SSM (1 << 9) /* Bit 9: Software slave management */ +#define SPI_CR1_RXONLY (1 << 10) /* Bit 10: Receive only */ +#if defined(HAVE_SPI_ARB_DATA_SIZE) +# define SPI_CR1_CRCL (1 << 11) /* Bit 11: CRC length */ +#else +# define SPI_CR1_DFF (1 << 11) /* Bit 11: Data Frame Format */ +#endif +#define SPI_CR1_CRCNEXT (1 << 12) /* Bit 12: Transmit CRC next */ +#define SPI_CR1_CRCEN (1 << 13) /* Bit 13: Hardware CRC calculation enable */ +#define SPI_CR1_BIDIOE (1 << 14) /* Bit 14: Output enable in bidirectional mode */ +#define SPI_CR1_BIDIMODE (1 << 15) /* Bit 15: Bidirectional data mode enable */ + +/* SPI Control Register 2 */ + +#define SPI_CR2_RXDMAEN (1 << 0) /* Bit 0: Rx Buffer DMA Enable */ +#define SPI_CR2_TXDMAEN (1 << 1) /* Bit 1: Tx Buffer DMA Enable */ +#define SPI_CR2_SSOE (1 << 2) /* Bit 2: SS Output Enable */ + +#if defined(HAVE_SPI_NSSP) +# define SPI_CR2_NSSP (1 << 3) /* Bit 3: NSS Pulse Management (Master mode only) */ +#endif + +#if defined(HAVE_SPI_TI_MODE) +# define SPI_CR2_FRF (1 << 4) /* Bit 4: Frame format: 0=Motorola, 1=TI */ +#endif + +#define SPI_CR2_ERRIE (1 << 5) /* Bit 5: Error interrupt enable */ +#define SPI_CR2_RXNEIE (1 << 6) /* Bit 6: RX buffer not empty interrupt enable */ +#define SPI_CR2_TXEIE (1 << 7) /* Bit 7: Tx buffer empty interrupt enable */ + +#if defined(HAVE_SPI_ARB_DATA_SIZE) +# define SPI_CR2_DS_SHIFT (8) /* Bits 8-11: Data size */ +# define SPI_CR2_DS_MASK (15 << SPI_CR2_DS_SHIFT) +# define SPI_CR2_DS(n) ((uint32_t)((n) - 1) << SPI_CR2_DS_SHIFT) +# define SPI_CR2_DS_4BIT (3 << SPI_CR2_DS_SHIFT) +# define SPI_CR2_DS_5BIT (4 << SPI_CR2_DS_SHIFT) +# define SPI_CR2_DS_6BIT (5 << SPI_CR2_DS_SHIFT) +# define SPI_CR2_DS_7BIT (6 << SPI_CR2_DS_SHIFT) +# define SPI_CR2_DS_8BIT (7 << SPI_CR2_DS_SHIFT) +# define SPI_CR2_DS_9BIT (8 << SPI_CR2_DS_SHIFT) +# define SPI_CR2_DS_10BIT (9 << SPI_CR2_DS_SHIFT) +# define SPI_CR2_DS_11BIT (10 << SPI_CR2_DS_SHIFT) +# define SPI_CR2_DS_12BIT (11 << SPI_CR2_DS_SHIFT) +# define SPI_CR2_DS_13BIT (12 << SPI_CR2_DS_SHIFT) +# define SPI_CR2_DS_14BIT (13 << SPI_CR2_DS_SHIFT) +# define SPI_CR2_DS_15BIT (14 << SPI_CR2_DS_SHIFT) +# define SPI_CR2_DS_16BIT (15 << SPI_CR2_DS_SHIFT) +# define SPI_CR2_FRXTH (1 << 12) /* Bit 12: FIFO reception threshold */ +# define SPI_CR2_LDMARX (1 << 13) /* Bit 13: Last DMA transfer for reception */ +# define SPI_CR2_LDMATX (1 << 14) /* Bit 14: Last DMA transfer for transmission */ +#endif + +/* SPI status register */ + +#define SPI_SR_RXNE (1 << 0) /* Bit 0: Receive buffer not empty */ +#define SPI_SR_TXE (1 << 1) /* Bit 1: Transmit buffer empty */ + +#if defined(HAVE_SPI_I2S) +# define SPI_SR_CHSIDE (1 << 2) /* Bit 2: Channel side */ +# define SPI_SR_UDR (1 << 3) /* Bit 3: Underrun flag */ +#endif + +#define SPI_SR_CRCERR (1 << 4) /* Bit 4: CRC error flag */ +#define SPI_SR_MODF (1 << 5) /* Bit 5: Mode fault */ +#define SPI_SR_OVR (1 << 6) /* Bit 6: Overrun flag */ +#define SPI_SR_BSY (1 << 7) /* Bit 7: Busy flag */ + +#if defined(HAVE_SPI_I2S) || defined(HAVE_SPI_TI_MODE) +# define SPI_SR_FRE (1 << 8) /* Bit 8: TI frame format error */ +#endif + +#if defined(HAVE_SPI_FIFOS) +# define SPI_SR_FRLVL_SHIFT (9) /* Bits 9-10: FIFO reception level */ +# define SPI_SR_FRLVL_MASK (3 << SPI_SR_FRLVL_SHIFT) +# define SPI_SR_FRLVL_EMPTY (0 << SPI_SR_FRLVL_SHIFT) /* FIFO empty */ +# define SPI_SR_FRLVL_QUARTER (1 << SPI_SR_FRLVL_SHIFT) /* 1/4 FIFO */ +# define SPI_SR_FRLVL_HALF (2 << SPI_SR_FRLVL_SHIFT) /* 1/2 FIFO */ +# define SPI_SR_FRLVL_FULL (3 << SPI_SR_FRLVL_SHIFT) /* FIFO full */ +# define SPI_SR_FTLVL_SHIFT (11) /* Bits 11-12: FIFO transmission level */ +# define SPI_SR_FTLVL_MASK (3 << SPI_SR_FTLVL_SHIFT) +# define SPI_SR_FTLVL_EMPTY (0 << SPI_SR_FTLVL_SHIFT) /* FIFO empty */ +# define SPI_SR_FTLVL_QUARTER (1 << SPI_SR_FTLVL_SHIFT) /* 1/4 FIFO */ +# define SPI_SR_FTLVL_HALF (2 << SPI_SR_FTLVL_SHIFT) /* 1/2 FIFO */ +# define SPI_SR_FTLVL_FULL (3 << SPI_SR_FTLVL_SHIFT) /* FIFO full */ +#endif + +/* I2S configuration register */ + +#if defined(HAVE_SPI_I2S) +# define SPI_I2SCFGR_CHLEN (1 << 0) /* Bit 0: Channel length (number of bits per audio channel) */ +# define SPI_I2SCFGR_DATLEN_SHIFT (1) /* Bit 1-2: Data length to be transferred */ +# define SPI_I2SCFGR_DATLEN_MASK (3 << SPI_I2SCFGR_DATLEN_SHIFT) +# define SPI_I2SCFGR_DATLEN_16BIT (0 << SPI_I2SCFGR_DATLEN_SHIFT) /* 00: 16-bit data length */ +# define SPI_I2SCFGR_DATLEN_8BIT (1 << SPI_I2SCFGR_DATLEN_SHIFT) /* 01: 24-bit data length */ +# define SPI_I2SCFGR_DATLEN_32BIT (2 << SPI_I2SCFGR_DATLEN_SHIFT) /* 10: 32-bit data length */ +# define SPI_I2SCFGR_CKPOL (1 << 3) /* Bit 3: Steady state clock polarity */ +# define SPI_I2SCFGR_I2SSTD_SHIFT (4) /* Bit 4-5: I2S standard selection */ +# define SPI_I2SCFGR_I2SSTD_MASK (3 << SPI_I2SCFGR_I2SSTD_SHIFT) +# define SPI_I2SCFGR_I2SSTD_PHILLIPS (0 << SPI_I2SCFGR_I2SSTD_SHIFT) /* 00: I2S Phillips standard. */ +# define SPI_I2SCFGR_I2SSTD_MSB (1 << SPI_I2SCFGR_I2SSTD_SHIFT) /* 01: MSB justified standard (left justified) */ +# define SPI_I2SCFGR_I2SSTD_LSB (2 << SPI_I2SCFGR_I2SSTD_SHIFT) /* 10: LSB justified standard (right justified) */ +# define SPI_I2SCFGR_I2SSTD_PCM (3 << SPI_I2SCFGR_I2SSTD_SHIFT) /* 11: PCM standard */ +# define SPI_I2SCFGR_PCMSYNC (1 << 7) /* Bit 7: PCM frame synchronization */ +# define SPI_I2SCFGR_I2SCFG_SHIFT (8) /* Bit 8-9: I2S configuration mode */ +# define SPI_I2SCFGR_I2SCFG_MASK (3 << SPI_I2SCFGR_I2SCFG_SHIFT) +# define SPI_I2SCFGR_I2SCFG_STX (0 << SPI_I2SCFGR_I2SCFG_SHIFT) /* 00: Slave - transmit */ +# define SPI_I2SCFGR_I2SCFG_SRX (1 << SPI_I2SCFGR_I2SCFG_SHIFT) /* 01: Slave - receive */ +# define SPI_I2SCFGR_I2SCFG_MTX (2 << SPI_I2SCFGR_I2SCFG_SHIFT) /* 10: Master - transmit */ +# define SPI_I2SCFGR_I2SCFG_MRX (3 << SPI_I2SCFGR_I2SCFG_SHIFT) /* 11: Master - receive */ +# define SPI_I2SCFGR_I2SE (1 << 10) /* Bit 10: I2S Enable */ +# define SPI_I2SCFGR_I2SMOD (1 << 11) /* Bit 11: I2S mode selection */ +# if defined(HAVE_SPI_I2S_ASTRT) +# define SPI_I2SCFGR_ASTRTEN (1 << 12) /* Bit 12: Asynchronous start enable */ +# endif +#endif + +/* I2S prescaler register */ + +#if defined(HAVE_SPI_I2S) +# define SPI_I2SPR_I2SDIV_SHIFT (0) /* Bit 0-7: I2S Linear prescaler */ +# define SPI_I2SPR_I2SDIV_MASK (0xff << SPI_I2SPR_I2SDIV_SHIFT) +# define SPI_I2SPR_ODD (1 << 8) /* Bit 8: Odd factor for the prescaler */ +# define SPI_I2SPR_MCKOE (1 << 9) /* Bit 9: Master clock output enable */ +#endif + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_SPI_V2V3V4_H */ diff --git a/arch/arm/src/common/stm32/hardware/stm32_syscfg.h b/arch/arm/src/common/stm32/hardware/stm32_syscfg.h new file mode 100644 index 0000000000000..7ed634e52b2b6 --- /dev/null +++ b/arch/arm/src/common/stm32/hardware/stm32_syscfg.h @@ -0,0 +1,43 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/hardware/stm32_syscfg.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_SYSCFG_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_SYSCFG_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include "chip.h" + +#if defined(CONFIG_ARCH_CHIP_STM32F0) +# include "hardware/stm32f0_syscfg.h" +#elif defined(CONFIG_ARCH_CHIP_STM32L0) +# include "hardware/stm32l0_syscfg.h" +#elif defined(CONFIG_ARCH_CHIP_STM32G0) +# include "hardware/stm32g0_syscfg.h" +#else +# error "Unsupported STM32 M0 SYSCFG" +#endif + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_SYSCFG_H */ diff --git a/arch/arm/src/common/stm32/hardware/stm32_tim.h b/arch/arm/src/common/stm32/hardware/stm32_tim.h new file mode 100644 index 0000000000000..4db3706e8899e --- /dev/null +++ b/arch/arm/src/common/stm32/hardware/stm32_tim.h @@ -0,0 +1,55 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/hardware/stm32_tim.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_TIM_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_TIM_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#if (defined(CONFIG_STM32_HAVE_IP_TIMERS_M0_V1) + \ + defined(CONFIG_STM32_HAVE_IP_TIMERS_M3M4_V1) + \ + defined(CONFIG_STM32_HAVE_IP_TIMERS_M3M4_V2) + \ + defined(CONFIG_STM32_HAVE_IP_TIMERS_M3M4_V3)) > 1 +# error Only one STM32 TIMER IP version must be selected +#endif + +#if defined(CONFIG_STM32_HAVE_IP_TIMERS_M0_V1) +# include "hardware/stm32_tim_v3_m0.h" +#elif defined(CONFIG_STM32_HAVE_IP_TIMERS_M3M4_V1) || \ + defined(CONFIG_STM32_HAVE_IP_TIMERS_M3M4_V2) || \ + defined(CONFIG_STM32_HAVE_IP_TIMERS_M3M4_V3) + +#if defined(CONFIG_STM32_HAVE_IP_TIMERS_M3M4_V1) || \ + defined(CONFIG_STM32_HAVE_IP_TIMERS_M3M4_V2) +# include "stm32_tim_v1v2.h" +#elif defined(CONFIG_STM32_HAVE_IP_TIMERS_M3M4_V3) +# include "stm32_tim_v3.h" +#else +# error "STM32 TIMER IP version not specified" +#endif +#else +# error "Unsupported STM32 TIM" +#endif + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_TIM_H */ diff --git a/arch/arm/src/stm32/hardware/stm32_tim_v1v2.h b/arch/arm/src/common/stm32/hardware/stm32_tim_v1v2.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32_tim_v1v2.h rename to arch/arm/src/common/stm32/hardware/stm32_tim_v1v2.h index bc1408b48474a..d519a4df68ed8 100644 --- a/arch/arm/src/stm32/hardware/stm32_tim_v1v2.h +++ b/arch/arm/src/common/stm32/hardware/stm32_tim_v1v2.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32_tim_v1v2.h + * arch/arm/src/common/stm32/hardware/stm32_tim_v1v2.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_TIM_V1V2_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_TIM_V1V2_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_TIM_V1V2_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_TIM_V1V2_H /**************************************************************************** * Pre-processor Definitions @@ -42,9 +42,9 @@ * - 4-bit SMS in SMCR register */ -#if defined(CONFIG_STM32_HAVE_IP_TIMERS_V2) +#if defined(CONFIG_STM32_HAVE_IP_TIMERS_M3M4_V2) # define HAVE_IP_TIMERS_V2 -#elif defined(CONFIG_STM32_HAVE_IP_TIMERS_V1) +#elif defined(CONFIG_STM32_HAVE_IP_TIMERS_M3M4_V1) # define HAVE_IP_TIMERS_V1 #else # error @@ -1304,4 +1304,4 @@ #define BTIM_EGR_UG (1 << 0) /* Bit 0: Update generation */ -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_TIM_V1V2_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_TIM_V1V2_H */ diff --git a/arch/arm/src/stm32/hardware/stm32_tim_v3.h b/arch/arm/src/common/stm32/hardware/stm32_tim_v3.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32_tim_v3.h rename to arch/arm/src/common/stm32/hardware/stm32_tim_v3.h index eb6e5421394e8..d4bd858b59119 100644 --- a/arch/arm/src/stm32/hardware/stm32_tim_v3.h +++ b/arch/arm/src/common/stm32/hardware/stm32_tim_v3.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32_tim_v3.h + * arch/arm/src/common/stm32/hardware/stm32_tim_v3.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_TIM_V3_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_TIM_V3_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_TIM_V3_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_TIM_V3_H /**************************************************************************** * Included Files @@ -1437,4 +1437,4 @@ #define BTIM_ARR_MASK_16 (0xffff << BTIM_ARR_SHIFT) /* Bits 0-15: Auto reload register */ #define BTIM_ARR_MASK_20 (0xfffff << BTIM_ARR_SHIFT) /* Bits 0-19: Auto reload register when BTIM_CR1_DITHEN */ -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_TIM_V3_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_TIM_V3_H */ diff --git a/arch/arm/src/common/stm32/hardware/stm32_tim_v3_m0.h b/arch/arm/src/common/stm32/hardware/stm32_tim_v3_m0.h new file mode 100644 index 0000000000000..211e43f7d514e --- /dev/null +++ b/arch/arm/src/common/stm32/hardware/stm32_tim_v3_m0.h @@ -0,0 +1,1151 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/hardware/stm32_tim_v3_m0.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_TIM_V3_M0_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_TIM_V3_M0_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include "chip.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Timer Capabilities *******************************************************/ + +/* TIM2 is 16-bit on STM32L0, but 32-bit on STM32F0, STM32G0 and STM32C0 */ + +#if defined(CONFIG_ARCH_CHIP_STM32L0) +# define HAVE_TIM2_16BIT 1 +# undef HAVE_TIM2_32BIT +#elif defined(CONFIG_ARCH_CHIP_STM32G0) || defined(CONFIG_STM32_STM32F09X) +# define HAVE_TIM2_32BIT 1 +# undef HAVE_TIM2_16BIT +#else +# define HAVE_TIM2_32BIT 1 +# undef HAVE_TIM2_16BIT +#endif + +/* TODO Missing TIM2 definitions available on STM32G0x1 */ + +/* Register Offsets *********************************************************/ + +/* Basic Timers - TIM6 and TIM7 */ + +#define STM32_BTIM_CR1_OFFSET 0x0000 /* Control register 1 (16-bit) */ +#define STM32_BTIM_CR2_OFFSET 0x0004 /* Control register 2 (16-bit) */ +#define STM32_BTIM_DIER_OFFSET 0x000c /* DMA/Interrupt enable register (16-bit) */ +#define STM32_BTIM_SR_OFFSET 0x0010 /* Status register (16-bit) */ +#define STM32_BTIM_EGR_OFFSET 0x0014 /* Event generation register (16-bit) */ +#define STM32_BTIM_CNT_OFFSET 0x0024 /* Counter (16-bit) */ +#define STM32_BTIM_PSC_OFFSET 0x0028 /* Prescaler (16-bit) */ +#define STM32_BTIM_ARR_OFFSET 0x002c /* Auto-reload register (16-bit) */ + +/* 16-bit General-purpose Timers - TIM3 and TIM14-17 */ + +#define STM32_GTIM_CR1_OFFSET 0x0000 /* Control register 1 (16-bit) */ +#define STM32_GTIM_CR2_OFFSET 0x0004 /* Control register 2 (16-bit TIM3 and TIM15-17) */ +#define STM32_GTIM_SMCR_OFFSET 0x0008 /* Slave mode control register (32-bit TIM3 and TIM15 only) */ +#define STM32_GTIM_DIER_OFFSET 0x000c /* DMA/Interrupt enable register (16-bit) */ +#define STM32_GTIM_SR_OFFSET 0x0010 /* Status register (16-bit) */ +#define STM32_GTIM_EGR_OFFSET 0x0014 /* Event generation register (16-bit) */ +#define STM32_GTIM_CCMR1_OFFSET 0x0018 /* Capture/compare mode register 1 (32-bit) */ +#define STM32_GTIM_CCMR2_OFFSET 0x001c /* Capture/compare mode register 2 (32-bit TIM3 only) */ +#define STM32_GTIM_CCER_OFFSET 0x0020 /* Capture/compare enable register (16-bit) */ +#define STM32_GTIM_CNT_OFFSET 0x0024 /* Counter (16-bit) */ +#define STM32_GTIM_PSC_OFFSET 0x0028 /* Prescaler (16-bit) */ +#define STM32_GTIM_ARR_OFFSET 0x002c /* Auto-reload register (16-bit) */ +#define STM32_GTIM_RCR_OFFSET 0x0030 /* Repetition counter register (16-bit, TIM15-17) */ +#define STM32_GTIM_CCR1_OFFSET 0x0034 /* Capture/compare register 1 (16-bit) */ +#define STM32_GTIM_CCR2_OFFSET 0x0038 /* Capture/compare register 2 (16-bit TIM3 and TIM15 only) */ +#define STM32_GTIM_CCR3_OFFSET 0x003c /* Capture/compare register 3 (16-bit TIM3 only) */ +#define STM32_GTIM_CCR4_OFFSET 0x0040 /* Capture/compare register 4 (16-bit TIM3 only) */ +#define STM32_GTIM_BDTR_OFFSET 0x0044 /* Break and dead-time register (32-bit TIM15-17) */ +#define STM32_GTIM_DCR_OFFSET 0x0048 /* DMA control register (16-bit TIM3 and TIM15-17) */ +#define STM32_GTIM_DMAR_OFFSET 0x004c /* DMA address for burst mode (16-bit TIM3 and TIM15-17) */ +#define STM32_GTIM_AF1_OFFSET 0x0060 /* Alternate function option register 1 (16-bit TIM15-17 or 32-bit TIM3) */ +#define STM32_GTIM_TISEL_OFFSET 0x0068 /* Timer input selection register (16-bit TIM14-17 or 32-bit TIM3) */ + +/* Advanced Timers - TIM1 */ + +#define STM32_ATIM_CR1_OFFSET 0x0000 /* Control register 1 (16-bit) */ +#define STM32_ATIM_CR2_OFFSET 0x0004 /* Control register 2 (16-bit*) */ +#define STM32_ATIM_SMCR_OFFSET 0x0008 /* Slave mode control register (16-bit) */ +#define STM32_ATIM_DIER_OFFSET 0x000c /* DMA/Interrupt enable register (16-bit) */ +#define STM32_ATIM_SR_OFFSET 0x0010 /* Status register (16-bit*) */ +#define STM32_ATIM_EGR_OFFSET 0x0014 /* Event generation register (16-bit) */ +#define STM32_ATIM_CCMR1_OFFSET 0x0018 /* Capture/compare mode register 1 (16-bit*) */ +#define STM32_ATIM_CCMR2_OFFSET 0x001c /* Capture/compare mode register 2 (16-bit*) */ +#define STM32_ATIM_CCER_OFFSET 0x0020 /* Capture/compare enable register (16-bit*) */ +#define STM32_ATIM_CNT_OFFSET 0x0024 /* Counter (16-bit) */ +#define STM32_ATIM_PSC_OFFSET 0x0028 /* Prescaler (16-bit) */ +#define STM32_ATIM_ARR_OFFSET 0x002c /* Auto-reload register (16-bit) */ +#define STM32_ATIM_RCR_OFFSET 0x0030 /* Repetition counter register (16-bit) */ +#define STM32_ATIM_CCR1_OFFSET 0x0034 /* Capture/compare register 1 (16-bit) */ +#define STM32_ATIM_CCR2_OFFSET 0x0038 /* Capture/compare register 2 (16-bit) */ +#define STM32_ATIM_CCR3_OFFSET 0x003c /* Capture/compare register 3 (16-bit) */ +#define STM32_ATIM_CCR4_OFFSET 0x0040 /* Capture/compare register 4 (16-bit) */ +#define STM32_ATIM_BDTR_OFFSET 0x0044 /* Break and dead-time register (16-bit*) */ +#define STM32_ATIM_DCR_OFFSET 0x0048 /* DMA control register (16-bit) */ +#define STM32_ATIM_DMAR_OFFSET 0x004c /* DMA address for burst mode (16-bit) */ +#define STM32_ATIM_OR1_OFFSET 0x0050 /* Timer option register 1 (16-bit) */ +#define STM32_ATIM_CCMR3_OFFSET 0x0054 /* Capture/compare mode register 3 (32-bit) */ +#define STM32_ATIM_CCR5_OFFSET 0x0058 /* Capture/compare register 4 (16-bit) */ +#define STM32_ATIM_CCR6_OFFSET 0x005c /* Capture/compare register 4 (32-bit) */ +#define STM32_ATIM_AF1_OFFSET 0x0060 /* Alternate function option register 1 (32-bit) */ +#define STM32_ATIM_AF2_OFFSET 0x0064 /* Alternate function option register 2 (32-bit) */ +#define STM32_ATIM_TISEL_OFFSET 0x0068 /* Timer input selection register (32-bit) */ + +/* Register Addresses *******************************************************/ + +/* Advanced Timers - TIM1 */ + +#define STM32_TIM1_CR1 (STM32_TIM1_BASE+STM32_ATIM_CR1_OFFSET) +#define STM32_TIM1_CR2 (STM32_TIM1_BASE+STM32_ATIM_CR2_OFFSET) +#define STM32_TIM1_SMCR (STM32_TIM1_BASE+STM32_ATIM_SMCR_OFFSET) +#define STM32_TIM1_DIER (STM32_TIM1_BASE+STM32_ATIM_DIER_OFFSET) +#define STM32_TIM1_SR (STM32_TIM1_BASE+STM32_ATIM_SR_OFFSET) +#define STM32_TIM1_EGR (STM32_TIM1_BASE+STM32_ATIM_EGR_OFFSET) +#define STM32_TIM1_CCMR1 (STM32_TIM1_BASE+STM32_ATIM_CCMR1_OFFSET) +#define STM32_TIM1_CCMR2 (STM32_TIM1_BASE+STM32_ATIM_CCMR2_OFFSET) +#define STM32_TIM1_CCER (STM32_TIM1_BASE+STM32_ATIM_CCER_OFFSET) +#define STM32_TIM1_CNT (STM32_TIM1_BASE+STM32_ATIM_CNT_OFFSET) +#define STM32_TIM1_PSC (STM32_TIM1_BASE+STM32_ATIM_PSC_OFFSET) +#define STM32_TIM1_ARR (STM32_TIM1_BASE+STM32_ATIM_ARR_OFFSET) +#define STM32_TIM1_RCR (STM32_TIM1_BASE+STM32_ATIM_RCR_OFFSET) +#define STM32_TIM1_CCR1 (STM32_TIM1_BASE+STM32_ATIM_CCR1_OFFSET) +#define STM32_TIM1_CCR2 (STM32_TIM1_BASE+STM32_ATIM_CCR2_OFFSET) +#define STM32_TIM1_CCR3 (STM32_TIM1_BASE+STM32_ATIM_CCR3_OFFSET) +#define STM32_TIM1_CCR4 (STM32_TIM1_BASE+STM32_ATIM_CCR4_OFFSET) +#define STM32_TIM1_BDTR (STM32_TIM1_BASE+STM32_ATIM_BDTR_OFFSET) +#define STM32_TIM1_DCR (STM32_TIM1_BASE+STM32_ATIM_DCR_OFFSET) +#define STM32_TIM1_DMAR (STM32_TIM1_BASE+STM32_ATIM_DMAR_OFFSET) +#define STM32_TIM1_OR1 (STM32_TIM1_BASE+STM32_ATIM_OR1_OFFSET) +#define STM32_TIM1_CCMR3 (STM32_TIM1_BASE+STM32_ATIM_CCMR3_OFFSET) +#define STM32_TIM1_CCR5 (STM32_TIM1_BASE+STM32_ATIM_CCR5_OFFSET) +#define STM32_TIM1_CCR6 (STM32_TIM1_BASE+STM32_ATIM_CCR6_OFFSET) +#define STM32_TIM1_AF1 (STM32_TIM1_BASE+STM32_ATIM_AF1_OFFSET) +#define STM32_TIM1_AF2 (STM32_TIM1_BASE+STM32_ATIM_AF2_OFFSET) +#define STM32_TIM1_TISEL (STM32_TIM1_BASE+STM32_ATIM_TISEL_OFFSET) + +/* 16-bit General Timers TIM3 and TIM14-17 */ + +#define STM32_TIM3_CR1 (STM32_TIM3_BASE+STM32_GTIM_CR1_OFFSET) +#define STM32_TIM3_CR2 (STM32_TIM3_BASE+STM32_GTIM_CR2_OFFSET) +#define STM32_TIM3_SMCR (STM32_TIM3_BASE+STM32_GTIM_SMCR_OFFSET) +#define STM32_TIM3_DIER (STM32_TIM3_BASE+STM32_GTIM_DIER_OFFSET) +#define STM32_TIM3_SR (STM32_TIM3_BASE+STM32_GTIM_SR_OFFSET) +#define STM32_TIM3_EGR (STM32_TIM3_BASE+STM32_GTIM_EGR_OFFSET) +#define STM32_TIM3_CCMR1 (STM32_TIM3_BASE+STM32_GTIM_CCMR1_OFFSET) +#define STM32_TIM3_CCMR2 (STM32_TIM3_BASE+STM32_GTIM_CCMR2_OFFSET) +#define STM32_TIM3_CCER (STM32_TIM3_BASE+STM32_GTIM_CCER_OFFSET) +#define STM32_TIM3_CNT (STM32_TIM3_BASE+STM32_GTIM_CNT_OFFSET) +#define STM32_TIM3_PSC (STM32_TIM3_BASE+STM32_GTIM_PSC_OFFSET) +#define STM32_TIM3_ARR (STM32_TIM3_BASE+STM32_GTIM_ARR_OFFSET) +#define STM32_TIM3_CCR1 (STM32_TIM3_BASE+STM32_GTIM_CCR1_OFFSET) +#define STM32_TIM3_CCR2 (STM32_TIM3_BASE+STM32_GTIM_CCR2_OFFSET) +#define STM32_TIM3_CCR3 (STM32_TIM3_BASE+STM32_GTIM_CCR3_OFFSET) +#define STM32_TIM3_CCR4 (STM32_TIM3_BASE+STM32_GTIM_CCR4_OFFSET) +#define STM32_TIM3_DCR (STM32_TIM3_BASE+STM32_GTIM_DCR_OFFSET) +#define STM32_TIM3_DMAR (STM32_TIM3_BASE+STM32_GTIM_DMAR_OFFSET) +#define STM32_TIM3_AF1 (STM32_TIM3_BASE+STM32_GTIM_AF1_OFFSET) +#define STM32_TIM3_TISEL (STM32_TIM3_BASE+STM32_GTIM_TISEL_OFFSET) + +#define STM32_TIM14_CR1 (STM32_TIM14_BASE+STM32_GTIM_CR1_OFFSET) +#define STM32_TIM14_DIER (STM32_TIM14_BASE+STM32_GTIM_DIER_OFFSET) +#define STM32_TIM14_SR (STM32_TIM14_BASE+STM32_GTIM_SR_OFFSET) +#define STM32_TIM14_EGR (STM32_TIM14_BASE+STM32_GTIM_EGR_OFFSET) +#define STM32_TIM14_CCMR1 (STM32_TIM14_BASE+STM32_GTIM_CCMR1_OFFSET) +#define STM32_TIM14_CCER (STM32_TIM14_BASE+STM32_GTIM_CCER_OFFSET) +#define STM32_TIM14_CNT (STM32_TIM14_BASE+STM32_GTIM_CNT_OFFSET) +#define STM32_TIM14_PSC (STM32_TIM14_BASE+STM32_GTIM_PSC_OFFSET) +#define STM32_TIM14_ARR (STM32_TIM14_BASE+STM32_GTIM_ARR_OFFSET) +#define STM32_TIM14_CCR1 (STM32_TIM14_BASE+STM32_GTIM_CCR1_OFFSET) +#define STM32_TIM14_TISEL (STM32_TIM14_BASE+STM32_GTIM_TISEL_OFFSET) + +#define STM32_TIM15_CR1 (STM32_TIM15_BASE+STM32_GTIM_CR1_OFFSET) +#define STM32_TIM15_CR2 (STM32_TIM15_BASE+STM32_GTIM_CR2_OFFSET) +#define STM32_TIM15_SMCR (STM32_TIM15_BASE+STM32_GTIM_SMCR_OFFSET) +#define STM32_TIM15_DIER (STM32_TIM15_BASE+STM32_GTIM_DIER_OFFSET) +#define STM32_TIM15_SR (STM32_TIM15_BASE+STM32_GTIM_SR_OFFSET) +#define STM32_TIM15_EGR (STM32_TIM15_BASE+STM32_GTIM_EGR_OFFSET) +#define STM32_TIM15_CCMR1 (STM32_TIM15_BASE+STM32_GTIM_CCMR1_OFFSET) +#define STM32_TIM15_CCER (STM32_TIM15_BASE+STM32_GTIM_CCER_OFFSET) +#define STM32_TIM15_CNT (STM32_TIM15_BASE+STM32_GTIM_CNT_OFFSET) +#define STM32_TIM15_PSC (STM32_TIM15_BASE+STM32_GTIM_PSC_OFFSET) +#define STM32_TIM15_ARR (STM32_TIM15_BASE+STM32_GTIM_ARR_OFFSET) +#define STM32_TIM15_RCR (STM32_TIM15_BASE+STM32_GTIM_RCR_OFFSET) +#define STM32_TIM15_CCR1 (STM32_TIM15_BASE+STM32_GTIM_CCR1_OFFSET) +#define STM32_TIM15_CCR2 (STM32_TIM15_BASE+STM32_GTIM_CCR2_OFFSET) +#define STM32_TIM15_BDTR (STM32_TIM15_BASE+STM32_GTIM_BDTR_OFFSET) +#define STM32_TIM15_DCR (STM32_TIM15_BASE+STM32_GTIM_DCR_OFFSET) +#define STM32_TIM15_DMAR (STM32_TIM15_BASE+STM32_GTIM_DMAR_OFFSET) +#define STM32_TIM15_AF1 (STM32_TIM15_BASE+STM32_GTIM_AF1_OFFSET) +#define STM32_TIM15_TISEL (STM32_TIM15_BASE+STM32_GTIM_TISEL_OFFSET) + +#define STM32_TIM16_CR1 (STM32_TIM16_BASE+STM32_GTIM_CR1_OFFSET) +#define STM32_TIM16_CR2 (STM32_TIM16_BASE+STM32_GTIM_CR2_OFFSET) +#define STM32_TIM16_DIER (STM32_TIM16_BASE+STM32_GTIM_DIER_OFFSET) +#define STM32_TIM16_SR (STM32_TIM16_BASE+STM32_GTIM_SR_OFFSET) +#define STM32_TIM16_EGR (STM32_TIM16_BASE+STM32_GTIM_EGR_OFFSET) +#define STM32_TIM16_CCMR1 (STM32_TIM16_BASE+STM32_GTIM_CCMR1_OFFSET) +#define STM32_TIM16_CCER (STM32_TIM16_BASE+STM32_GTIM_CCER_OFFSET) +#define STM32_TIM16_CNT (STM32_TIM16_BASE+STM32_GTIM_CNT_OFFSET) +#define STM32_TIM16_PSC (STM32_TIM16_BASE+STM32_GTIM_PSC_OFFSET) +#define STM32_TIM16_ARR (STM32_TIM16_BASE+STM32_GTIM_ARR_OFFSET) +#define STM32_TIM16_RCR (STM32_TIM16_BASE+STM32_GTIM_RCR_OFFSET) +#define STM32_TIM16_CCR1 (STM32_TIM16_BASE+STM32_GTIM_CCR1_OFFSET) +#define STM32_TIM16_BDTR (STM32_TIM16_BASE+STM32_GTIM_BDTR_OFFSET) +#define STM32_TIM16_DCR (STM32_TIM16_BASE+STM32_GTIM_DCR_OFFSET) +#define STM32_TIM16_DMAR (STM32_TIM16_BASE+STM32_GTIM_DMAR_OFFSET) +#define STM32_TIM16_AF1 (STM32_TIM16_BASE+STM32_GTIM_AF1_OFFSET) +#define STM32_TIM16_TISEL (STM32_TIM16_BASE+STM32_GTIM_TISEL_OFFSET) + +#define STM32_TIM17_CR1 (STM32_TIM17_BASE+STM32_GTIM_CR1_OFFSET) +#define STM32_TIM17_CR2 (STM32_TIM17_BASE+STM32_GTIM_CR2_OFFSET) +#define STM32_TIM17_DIER (STM32_TIM17_BASE+STM32_GTIM_DIER_OFFSET) +#define STM32_TIM17_SR (STM32_TIM17_BASE+STM32_GTIM_SR_OFFSET) +#define STM32_TIM17_EGR (STM32_TIM17_BASE+STM32_GTIM_EGR_OFFSET) +#define STM32_TIM17_CCMR1 (STM32_TIM17_BASE+STM32_GTIM_CCMR1_OFFSET) +#define STM32_TIM17_CCER (STM32_TIM17_BASE+STM32_GTIM_CCER_OFFSET) +#define STM32_TIM17_CNT (STM32_TIM17_BASE+STM32_GTIM_CNT_OFFSET) +#define STM32_TIM17_PSC (STM32_TIM17_BASE+STM32_GTIM_PSC_OFFSET) +#define STM32_TIM17_ARR (STM32_TIM17_BASE+STM32_GTIM_ARR_OFFSET) +#define STM32_TIM17_RCR (STM32_TIM17_BASE+STM32_GTIM_RCR_OFFSET) +#define STM32_TIM17_CCR1 (STM32_TIM17_BASE+STM32_GTIM_CCR1_OFFSET) +#define STM32_TIM17_BDTR (STM32_TIM17_BASE+STM32_GTIM_BDTR_OFFSET) +#define STM32_TIM17_DCR (STM32_TIM17_BASE+STM32_GTIM_DCR_OFFSET) +#define STM32_TIM17_DMAR (STM32_TIM17_BASE+STM32_GTIM_DMAR_OFFSET) +#define STM32_TIM17_AF1 (STM32_TIM17_BASE+STM32_GTIM_AF1_OFFSET) +#define STM32_TIM17_TISEL (STM32_TIM17_BASE+STM32_GTIM_TISEL_OFFSET) + +/* Basic Timers - TIM6 and TIM7 */ + +#define STM32_TIM6_CR1 (STM32_TIM6_BASE+STM32_BTIM_CR1_OFFSET) +#define STM32_TIM6_CR2 (STM32_TIM6_BASE+STM32_BTIM_CR2_OFFSET) +#define STM32_TIM6_DIER (STM32_TIM6_BASE+STM32_BTIM_DIER_OFFSET) +#define STM32_TIM6_SR (STM32_TIM6_BASE+STM32_BTIM_SR_OFFSET) +#define STM32_TIM6_EGR (STM32_TIM6_BASE+STM32_BTIM_EGR_OFFSET) +#define STM32_TIM6_CNT (STM32_TIM6_BASE+STM32_BTIM_CNT_OFFSET) +#define STM32_TIM6_PSC (STM32_TIM6_BASE+STM32_BTIM_PSC_OFFSET) +#define STM32_TIM6_ARR (STM32_TIM6_BASE+STM32_BTIM_ARR_OFFSET) + +#define STM32_TIM7_CR1 (STM32_TIM7_BASE+STM32_BTIM_CR1_OFFSET) +#define STM32_TIM7_CR2 (STM32_TIM7_BASE+STM32_BTIM_CR2_OFFSET) +#define STM32_TIM7_DIER (STM32_TIM7_BASE+STM32_BTIM_DIER_OFFSET) +#define STM32_TIM7_SR (STM32_TIM7_BASE+STM32_BTIM_SR_OFFSET) +#define STM32_TIM7_EGR (STM32_TIM7_BASE+STM32_BTIM_EGR_OFFSET) +#define STM32_TIM7_CNT (STM32_TIM7_BASE+STM32_BTIM_CNT_OFFSET) +#define STM32_TIM7_PSC (STM32_TIM7_BASE+STM32_BTIM_PSC_OFFSET) +#define STM32_TIM7_ARR (STM32_TIM7_BASE+STM32_BTIM_ARR_OFFSET) + +/* Register Bitfield Definitions ********************************************/ + +/* Control register 1 */ + +#define ATIM_CR1_CEN (1 << 0) /* Bit 0: Counter enable */ +#define ATIM_CR1_UDIS (1 << 1) /* Bit 1: Update disable */ +#define ATIM_CR1_URS (1 << 2) /* Bit 2: Update request source */ +#define ATIM_CR1_OPM (1 << 3) /* Bit 3: One pulse mode */ +#define ATIM_CR1_DIR (1 << 4) /* Bit 4: Direction */ +#define ATIM_CR1_CMS_SHIFT (5) /* Bits 6-5: Center-aligned mode selection */ +#define ATIM_CR1_CMS_MASK (3 << ATIM_CR1_CMS_SHIFT) +# define ATIM_CR1_EDGE (0 << ATIM_CR1_CMS_SHIFT) /* 00: Edge-aligned mode */ +# define ATIM_CR1_CENTER1 (1 << ATIM_CR1_CMS_SHIFT) /* 01: Center-aligned mode 1 */ +# define ATIM_CR1_CENTER2 (2 << ATIM_CR1_CMS_SHIFT) /* 10: Center-aligned mode 2 */ +# define ATIM_CR1_CENTER3 (3 << ATIM_CR1_CMS_SHIFT) /* 11: Center-aligned mode 3 */ + +#define ATIM_CR1_ARPE (1 << 7) /* Bit 7: Auto-reload preload enable */ +#define ATIM_CR1_CKD_SHIFT (8) /* Bits 9-8: Clock division */ +#define ATIM_CR1_CKD_MASK (3 << ATIM_CR1_CKD_SHIFT) +# define ATIM_CR1_TCKINT (0 << ATIM_CR1_CKD_SHIFT) /* 00: tDTS=tCK_INT */ +# define ATIM_CR1_2TCKINT (1 << ATIM_CR1_CKD_SHIFT) /* 01: tDTS=2*tCK_INT */ +# define ATIM_CR1_4TCKINT (2 << ATIM_CR1_CKD_SHIFT) /* 10: tDTS=4*tCK_INT */ + +#define ATIM_CR1_UIFREMAP (1 << 11) /* Bit 11: UIF status bit remapping */ + +/* Control register 2 */ + +#define ATIM_CR2_CCPC (1 << 0) /* Bit 0: Capture/Compare Preloaded Control */ +#define ATIM_CR2_CCUS (1 << 2) /* Bit 2: Capture/Compare Control Update Selection */ +#define ATIM_CR2_CCDS (1 << 3) /* Bit 3: Capture/Compare DMA Selection */ +#define ATIM_CR2_MMS_SHIFT (4) /* Bits 6-4: Master Mode Selection */ +#define ATIM_CR2_MMS_MASK (7 << ATIM_CR2_MMS_SHIFT) +# define ATIM_CR2_MMS_RESET (0 << ATIM_CR2_MMS_SHIFT) /* 000: Reset - TIMx_EGR UG bit is TRGO */ +# define ATIM_CR2_MMS_ENABLE (1 << ATIM_CR2_MMS_SHIFT) /* 001: Enable - CNT_EN is TRGO */ +# define ATIM_CR2_MMS_UPDATE (2 << ATIM_CR2_MMS_SHIFT) /* 010: Update event is TRGO */ +# define ATIM_CR2_MMS_COMPP (3 << ATIM_CR2_MMS_SHIFT) /* 010: Compare Pulse - CC1IF flag */ +# define ATIM_CR2_MMS_OC1REF (4 << ATIM_CR2_MMS_SHIFT) /* 100: Compare OC1REF is TRGO */ +# define ATIM_CR2_MMS_OC2REF (5 << ATIM_CR2_MMS_SHIFT) /* 101: Compare OC2REF is TRGO */ +# define ATIM_CR2_MMS_OC3REF (6 << ATIM_CR2_MMS_SHIFT) /* 110: Compare OC3REF is TRGO */ +# define ATIM_CR2_MMS_OC4REF (7 << ATIM_CR2_MMS_SHIFT) /* 111: Compare OC4REF is TRGO */ + +#define ATIM_CR2_TI1S (1 << 7) /* Bit 7: TI1 Selection */ +#define ATIM_CR2_OIS1 (1 << 8) /* Bit 8: Output Idle state 1 (OC1 output) */ +#define ATIM_CR2_OIS1N (1 << 9) /* Bit 9: Output Idle state 1 (OC1N output) */ +#define ATIM_CR2_OIS2 (1 << 10) /* Bit 10: Output Idle state 2 (OC2 output) */ +#define ATIM_CR2_OIS2N (1 << 11) /* Bit 11: Output Idle state 2 (OC2N output) */ +#define ATIM_CR2_OIS3 (1 << 12) /* Bit 12: Output Idle state 3 (OC3 output) */ +#define ATIM_CR2_OIS3N (1 << 13) /* Bit 13: Output Idle state 3 (OC3N output) */ +#define ATIM_CR2_OIS4 (1 << 14) /* Bit 14: Output Idle state 4 (OC4 output) */ +#define ATIM_CR2_OIS5 (1 << 16) /* Bit 16: Output Idle state 5 (OC5 output) */ +#define ATIM_CR2_OIS6 (1 << 18) /* Bit 18: Output Idle state 6 (OC6 output) */ +#define ATIM_CR2_MMS2_SHIFT (20) /* Bits 20-23: Master Mode Selection 2 */ +#define ATIM_CR2_MMS2_MASK (15 << ATIM_CR2_MMS2_SHIFT) +# define ATIM_CR2_MMS2_RESET (0 << ATIM_CR2_MMS2_SHIFT) /* 0000: Reset - TIMx_EGR UG bit is TRG9 */ +# define ATIM_CR2_MMS2_ENABLE (1 << ATIM_CR2_MMS2_SHIFT) /* 0001: Enable - CNT_EN is TRGO2 */ +# define ATIM_CR2_MMS2_UPDATE (2 << ATIM_CR2_MMS2_SHIFT) /* 0010: Update event is TRGH0*/ +# define ATIM_CR2_MMS2_COMPP (3 << ATIM_CR2_MMS2_SHIFT) /* 0010: Compare Pulse - CC1IF flag */ +# define ATIM_CR2_MMS2_OC1REF (4 << ATIM_CR2_MMS2_SHIFT) /* 0100: Compare OC1REF is TRGO2 */ +# define ATIM_CR2_MMS2_OC2REF (5 << ATIM_CR2_MMS2_SHIFT) /* 0101: Compare OC2REF is TRGO2 */ +# define ATIM_CR2_MMS2_OC3REF (6 << ATIM_CR2_MMS2_SHIFT) /* 0110: Compare OC3REF is TRGO2 */ +# define ATIM_CR2_MMS2_OC4REF (7 << ATIM_CR2_MMS2_SHIFT) /* 0111: Compare OC4REF is TRGO2 */ +# define ATIM_CR2_MMS2_OC5REF (8 << ATIM_CR2_MMS2_SHIFT) /* 1000: Compare OC5REF is TRGO2 */ +# define ATIM_CR2_MMS2_OC6REF (9 << ATIM_CR2_MMS2_SHIFT) /* 1001: Compare OC6REF is TRGO2 */ +# define ATIM_CR2_MMS2_CMPOC4 (10 << ATIM_CR2_MMS2_SHIFT) /* 1010: Compare pulse - OC4REF edge is TRGO2 */ +# define ATIM_CR2_MMS2_CMPOC6 (11 << ATIM_CR2_MMS2_SHIFT) /* 1011: Compare pulse - OC6REF edge is TRGO2 */ +# define ATIM_CR2_MMS2_CMPOC4R6R (12 << ATIM_CR2_MMS2_SHIFT) /* 1100: Compare pulse - OC4REF/OC6REF rising */ +# define ATIM_CR2_MMS2_CMPOC4R6F (13 << ATIM_CR2_MMS2_SHIFT) /* 1101: Compare pulse - OC4REF rising/OC6REF falling */ +# define ATIM_CR2_MMS2_CMPOC5R6R (14 << ATIM_CR2_MMS2_SHIFT) /* 1110: Compare pulse - OC5REF/OC6REF rising */ +# define ATIM_CR2_MMS2_CMPOC5R6F (15 << ATIM_CR2_MMS2_SHIFT) /* 1111: Compare pulse - OC5REF rising/OC6REF falling */ + +/* Slave mode control register */ + +#define ATIM_SMCR_SMS_SHIFT (0) /* Bits 0-2: Slave mode selection */ +#define ATIM_SMCR_SMS_MASK (7 << ATIM_SMCR_SMS_SHIFT) +# define ATIM_SMCR_DISAB (0 << ATIM_SMCR_SMS_SHIFT) /* 000: Slave mode disabled */ +# define ATIM_SMCR_ENCMD1 (1 << ATIM_SMCR_SMS_SHIFT) /* 001: Encoder mode 1 */ +# define ATIM_SMCR_ENCMD2 (2 << ATIM_SMCR_SMS_SHIFT) /* 010: Encoder mode 2 */ +# define ATIM_SMCR_ENCMD3 (3 << ATIM_SMCR_SMS_SHIFT) /* 011: Encoder mode 3 */ +# define ATIM_SMCR_RESET (4 << ATIM_SMCR_SMS_SHIFT) /* 100: Reset Mode */ +# define ATIM_SMCR_GATED (5 << ATIM_SMCR_SMS_SHIFT) /* 101: Gated Mode */ +# define ATIM_SMCR_TRIGGER (6 << ATIM_SMCR_SMS_SHIFT) /* 110: Trigger Mode */ +# define ATIM_SMCR_EXTCLK1 (7 << ATIM_SMCR_SMS_SHIFT) /* 111: External Clock Mode 1 */ + +#define ATIM_SMCR_OCCS (1 << 3) /* Bit 3: OCREF clear selection */ +#define ATIM_SMCR_TS_SHIFT (4) /* Bits 4-6: Trigger selection */ +#define ATIM_SMCR_TS_MASK (7 << ATIM_SMCR_TS_SHIFT) +# define ATIM_SMCR_ITR0 (0 << ATIM_SMCR_TS_SHIFT) /* 000: Internal trigger 0 (ITR0) */ +# define ATIM_SMCR_ITR1 (1 << ATIM_SMCR_TS_SHIFT) /* 001: Internal trigger 1 (ITR1) */ +# define ATIM_SMCR_ITR2 (2 << ATIM_SMCR_TS_SHIFT) /* 010: Internal trigger 2 (ITR2) */ +# define ATIM_SMCR_ITR3 (3 << ATIM_SMCR_TS_SHIFT) /* 011: Internal trigger 3 (ITR3) */ +# define ATIM_SMCR_T1FED (4 << ATIM_SMCR_TS_SHIFT) /* 100: TI1 Edge Detector (TI1F_ED) */ +# define ATIM_SMCR_TI1FP1 (5 << ATIM_SMCR_TS_SHIFT) /* 101: Filtered Timer Input 1 (TI1FP1) */ +# define ATIM_SMCR_T12FP2 (6 << ATIM_SMCR_TS_SHIFT) /* 110: Filtered Timer Input 2 (TI2FP2) */ +# define ATIM_SMCR_ETRF (7 << ATIM_SMCR_TS_SHIFT) /* 111: External Trigger input (ETRF) */ + +#define ATIM_SMCR_MSM (1 << 7) /* Bit 7: Master/slave mode */ +#define ATIM_SMCR_ETF_SHIFT (8) /* Bits 8-11: External trigger filter */ +#define ATIM_SMCR_ETF_MASK (0x0f << ATIM_SMCR_ETF_SHIFT) +# define ATIM_SMCR_NOFILT (0 << ATIM_SMCR_ETF_SHIFT) /* 0000: No filter, sampling is done at fDTS */ +# define ATIM_SMCR_FCKINT2 (1 << ATIM_SMCR_ETF_SHIFT) /* 0001: fSAMPLING=fCK_INT, N=2 */ +# define ATIM_SMCR_FCKINT4 (2 << ATIM_SMCR_ETF_SHIFT) /* 0010: fSAMPLING=fCK_INT, N=4 */ +# define ATIM_SMCR_FCKINT8 (3 << ATIM_SMCR_ETF_SHIFT) /* 0011: fSAMPLING=fCK_INT, N=8 */ +# define ATIM_SMCR_FDTSd26 (4 << ATIM_SMCR_ETF_SHIFT) /* 0100: fSAMPLING=fDTS/2, N=6 */ +# define ATIM_SMCR_FDTSd28 (5 << ATIM_SMCR_ETF_SHIFT) /* 0101: fSAMPLING=fDTS/2, N=8 */ +# define ATIM_SMCR_FDTSd46 (6 << ATIM_SMCR_ETF_SHIFT) /* 0110: fSAMPLING=fDTS/4, N=6 */ +# define ATIM_SMCR_FDTSd48 (7 << ATIM_SMCR_ETF_SHIFT) /* 0111: fSAMPLING=fDTS/4, N=8 */ +# define ATIM_SMCR_FDTSd86 (8 << ATIM_SMCR_ETF_SHIFT) /* 1000: fSAMPLING=fDTS/8, N=6 */ +# define ATIM_SMCR_FDTSd88 (9 << ATIM_SMCR_ETF_SHIFT) /* 1001: fSAMPLING=fDTS/8, N=8 */ +# define ATIM_SMCR_FDTSd165 (10 << ATIM_SMCR_ETF_SHIFT) /* 1010: fSAMPLING=fDTS/16, N=5 */ +# define ATIM_SMCR_FDTSd166 (11 << ATIM_SMCR_ETF_SHIFT) /* 1011: fSAMPLING=fDTS/16, N=6 */ +# define ATIM_SMCR_FDTSd168 (12 << ATIM_SMCR_ETF_SHIFT) /* 1100: fSAMPLING=fDTS/16, N=8 */ +# define ATIM_SMCR_FDTSd325 (13 << ATIM_SMCR_ETF_SHIFT) /* 1101: fSAMPLING=fDTS/32, N=5 */ +# define ATIM_SMCR_FDTSd326 (14 << ATIM_SMCR_ETF_SHIFT) /* 1110: fSAMPLING=fDTS/32, N=6 */ +# define ATIM_SMCR_FDTSd328 (15 << ATIM_SMCR_ETF_SHIFT) /* 1111: fSAMPLING=fDTS/32, N=8 */ + +#define ATIM_SMCR_ETPS_SHIFT (12) /* Bits 12-13: External trigger prescaler */ +#define ATIM_SMCR_ETPS_MASK (3 << ATIM_SMCR_ETPS_SHIFT) +# define ATIM_SMCR_PSCOFF (0 << ATIM_SMCR_ETPS_SHIFT) /* 00: Prescaler OFF */ +# define ATIM_SMCR_ETRPd2 (1 << ATIM_SMCR_ETPS_SHIFT) /* 01: ETRP frequency divided by 2 */ +# define ATIM_SMCR_ETRPd4 (2 << ATIM_SMCR_ETPS_SHIFT) /* 10: ETRP frequency divided by 4 */ +# define ATIM_SMCR_ETRPd8 (3 << ATIM_SMCR_ETPS_SHIFT) /* 11: ETRP frequency divided by 8 */ + +#define ATIM_SMCR_ECE (1 << 14) /* Bit 14: External clock enable */ +#define ATIM_SMCR_ETP (1 << 15) /* Bit 15: External trigger polarity */ +#define ATIM_SMCR_SMS (1 << 16) /* Bit 16: Slave mode selection - bit 3 */ + +/* TS[3:4] (bits 20-21) are set to 00 for each valid option */ + +/* DMA/Interrupt enable register */ + +#define ATIM_DIER_UIE (1 << 0) /* Bit 0: Update interrupt enable */ +#define ATIM_DIER_CC1IE (1 << 1) /* Bit 1: Capture/Compare 1 interrupt enable */ +#define ATIM_DIER_CC2IE (1 << 2) /* Bit 2: Capture/Compare 2 interrupt enable */ +#define ATIM_DIER_CC3IE (1 << 3) /* Bit 3: Capture/Compare 3 interrupt enable */ +#define ATIM_DIER_CC4IE (1 << 4) /* Bit 4: Capture/Compare 4 interrupt enable */ +#define ATIM_DIER_COMIE (1 << 5) /* Bit 5: COM interrupt enable */ +#define ATIM_DIER_TIE (1 << 6) /* Bit 6: Trigger interrupt enable */ +#define ATIM_DIER_BIE (1 << 7) /* Bit 7: Break interrupt enable */ +#define ATIM_DIER_UDE (1 << 8) /* Bit 8: Update DMA request enable */ +#define ATIM_DIER_CC1DE (1 << 9) /* Bit 9: Capture/Compare 1 DMA request enable */ +#define ATIM_DIER_CC2DE (1 << 10) /* Bit 10: Capture/Compare 2 DMA request enable */ +#define ATIM_DIER_CC3DE (1 << 11) /* Bit 11: Capture/Compare 3 DMA request enable */ +#define ATIM_DIER_CC4DE (1 << 12) /* Bit 12: Capture/Compare 4 DMA request enable */ +#define ATIM_DIER_COMDE (1 << 13) /* Bit 13: COM DMA request enable */ +#define ATIM_DIER_TDE (1 << 14) /* Bit 14: Trigger DMA request enable */ + +/* Status register */ + +#define ATIM_SR_UIF (1 << 0) /* Bit 0: Update interrupt Flag */ +#define ATIM_SR_CC1IF (1 << 1) /* Bit 1: Capture/Compare 1 interrupt Flag */ +#define ATIM_SR_CC2IF (1 << 2) /* Bit 2: Capture/Compare 2 interrupt Flag */ +#define ATIM_SR_CC3IF (1 << 3) /* Bit 3: Capture/Compare 3 interrupt Flag */ +#define ATIM_SR_CC4IF (1 << 4) /* Bit 4: Capture/Compare 4 interrupt Flag */ +#define ATIM_SR_COMIF (1 << 5) /* Bit 5: COM interrupt Flag */ +#define ATIM_SR_TIF (1 << 6) /* Bit 6: Trigger interrupt Flag */ +#define ATIM_SR_BIF (1 << 7) /* Bit 7: Break interrupt Flag */ +#define ATIM_SR_B2IF (1 << 8) /* Bit 8: Break 2 interrupt Flag */ +#define ATIM_SR_CC1OF (1 << 9) /* Bit 9: Capture/Compare 1 Overcapture Flag */ +#define ATIM_SR_CC2OF (1 << 10) /* Bit 10: Capture/Compare 2 Overcapture Flag */ +#define ATIM_SR_CC3OF (1 << 11) /* Bit 11: Capture/Compare 3 Overcapture Flag */ +#define ATIM_SR_CC4OF (1 << 12) /* Bit 12: Capture/Compare 4 Overcapture Flag */ +#define ATIM_SR_SBIF (1 << 13) /* Bit 13: System break interrupt Flag */ +#define ATIM_SR_CC5IF (1 << 16) /* Bit 16: Compare 5 interrupt flag */ +#define ATIM_SR_CC6IF (1 << 17) /* Bit 17: Compare 6 interrupt flag */ + +/* Event generation register */ + +#define ATIM_EGR_UG (1 << 0) /* Bit 0: Update Generation */ +#define ATIM_EGR_CC1G (1 << 1) /* Bit 1: Capture/Compare 1 Generation */ +#define ATIM_EGR_CC2G (1 << 2) /* Bit 2: Capture/Compare 2 Generation */ +#define ATIM_EGR_CC3G (1 << 3) /* Bit 3: Capture/Compare 3 Generation */ +#define ATIM_EGR_CC4G (1 << 4) /* Bit 4: Capture/Compare 4 Generation */ +#define ATIM_EGR_COMG (1 << 5) /* Bit 5: Capture/Compare Control Update Generation */ +#define ATIM_EGR_TG (1 << 6) /* Bit 6: Trigger Generation */ +#define ATIM_EGR_BG (1 << 7) /* Bit 7: Break Generation */ +#define ATIM_EGR_B2G (1 << 8) /* Bit 8: Break 2 Generation */ + +/* Capture/compare mode register 1 -- Output compare mode */ + +#define ATIM_CCMR1_CC1S_SHIFT (0) /* Bits 1-0: Capture/Compare 1 Selection */ +#define ATIM_CCMR1_CC1S_MASK (3 << ATIM_CCMR1_CC1S_SHIFT) + /* (See common (unshifted) bit field definitions below) */ +#define ATIM_CCMR1_OC1FE (1 << 2) /* Bit 2: Output Compare 1 Fast enable */ +#define ATIM_CCMR1_OC1PE (1 << 3) /* Bit 3: Output Compare 1 Preload enable */ +#define ATIM_CCMR1_OC1M_SHIFT (4) /* Bits 6-4: Output Compare 1 Mode */ +#define ATIM_CCMR1_OC1M_MASK (7 << ATIM_CCMR1_OC1M_SHIFT) + /* (See common (unshifted) bit field definitions below) */ +#define ATIM_CCMR1_OC1CE (1 << 7) /* Bit 7: Output Compare 1Clear Enable */ +#define ATIM_CCMR1_CC2S_SHIFT (8) /* Bits 8-9: Capture/Compare 2 Selection */ +#define ATIM_CCMR1_CC2S_MASK (3 << ATIM_CCMR1_CC2S_SHIFT) + /* (See common (unshifted) bit field definitions below) */ +#define ATIM_CCMR1_OC2FE (1 << 10) /* Bit 10: Output Compare 2 Fast enable */ +#define ATIM_CCMR1_OC2PE (1 << 11) /* Bit 11: Output Compare 2 Preload enable */ +#define ATIM_CCMR1_OC2M_SHIFT (12) /* Bits 14-12: Output Compare 2 Mode */ +#define ATIM_CCMR1_OC2M_MASK (7 << ATIM_CCMR1_OC2M_SHIFT) + /* (See common (unshifted) bit field definitions below) */ +#define ATIM_CCMR1_OC2CE (1 << 15) /* Bit 15: Output Compare 2 Clear Enable */ +#define ATIM_CCMR1_OC1M (1 << 16) /* Bit 16: Output Compare 1 mode - bit 3 */ +#define ATIM_CCMR1_OC2M (1 << 24) /* Bit 24: Output Compare 2 mode - bit 3 */ + +/* Common CCMR (unshifted) Capture/Compare Selection bit-field definitions */ + +#define ATIM_CCMR_CCS_CCOUT (0) /* 00: CCx channel output */ +#define ATIM_CCMR_CCS_CCIN1 (1) /* 01: CCx channel input, ICx is TIx */ +#define ATIM_CCMR_CCS_CCIN2 (2) /* 10: CCx channel input, ICx is TIy */ +#define ATIM_CCMR_CCS_CCINTRC (3) /* 11: CCx channel input, ICx is TRC */ + +/* Common CCMR (unshifted) Compare Mode bit field definitions */ + +#define ATIM_CCMR_MODE_FRZN (0) /* 000: Frozen */ +#define ATIM_CCMR_MODE_CHACT (1) /* 001: Channel x active on match */ +#define ATIM_CCMR_MODE_CHINACT (2) /* 010: Channel x inactive on match */ +#define ATIM_CCMR_MODE_OCREFTOG (3) /* 011: OCxREF toggle ATIM_CNT=ATIM_CCRx */ +#define ATIM_CCMR_MODE_OCREFLO (4) /* 100: OCxREF forced low */ +#define ATIM_CCMR_MODE_OCREFHI (5) /* 101: OCxREF forced high */ +#define ATIM_CCMR_MODE_PWM1 (6) /* 110: PWM mode 1 */ +#define ATIM_CCMR_MODE_PWM2 (7) /* 111: PWM mode 2 */ +#define ATIM_CCMR_MODE_RETRIG1 (8) /* 1000: Retrigerrable OPM mode 1 */ +#define ATIM_CCMR_MODE_RETRIG2 (9) /* 1001: Retrigerrable OPM mode 2 */ +#define ATIM_CCMR_MODE_COMBINED1 (12) /* 1100: Combined PWM mode 1 */ +#define ATIM_CCMR_MODE_COMBINED2 (13) /* 1101: Combined PWM mode 2 */ +#define ATIM_CCMR_MODE_ASYMMETRIC1 (14) /* 1110: Asymmetric PWM mode 1 */ +#define ATIM_CCMR_MODE_ASYMMETRIC2 (15) /* 1111: Asymmetric PWM mode 2 */ + +/* Capture/compare mode register 1 -- Input capture mode */ + +/* Bits 1-0: + * same as output compare mode) + */ +#define ATIM_CCMR1_IC1PSC_SHIFT (2) /* Bits 3-2: Input Capture 1 Prescaler */ +#define ATIM_CCMR1_IC1PSC_MASK (3 << ATIM_CCMR1_IC1PSC_SHIFT) + /* (See common (unshifted) bit field definitions below) */ +#define ATIM_CCMR1_IC1F_SHIFT (4) /* Bits 7-4: Input Capture 1 Filter */ +#define ATIM_CCMR1_IC1F_MASK (0x0f << ATIM_CCMR1_IC1F_SHIFT) + /* (See common (unshifted) bit field definitions below) */ + /* Bits 9:8 (same as output compare mode) */ +#define ATIM_CCMR1_IC2PSC_SHIFT (10) /* Bits 11:10: Input Capture 2 Prescaler */ +#define ATIM_CCMR1_IC2PSC_MASK (3 << ATIM_CCMR1_IC2PSC_SHIFT) + /* (See common (unshifted) bit field definitions below) */ +#define ATIM_CCMR1_IC2F_SHIFT (12) /* Bits 15-12: Input Capture 2 Filter */ +#define ATIM_CCMR1_IC2F_MASK (0x0f << ATIM_CCMR1_IC2F_SHIFT) + /* (See common (unshifted) bit field definitions below) */ + +/* Common CCMR (unshifted) Input Capture Prescaler bit-field definitions */ + +#define ATIM_CCMR_ICPSC_NOPSC (0) /* 00: no prescaler, capture each edge */ +#define ATIM_CCMR_ICPSC_EVENTS2 (1) /* 01: capture once every 2 events */ +#define ATIM_CCMR_ICPSC_EVENTS4 (2) /* 10: capture once every 4 events */ +#define ATIM_CCMR_ICPSC_EVENTS8 (3) /* 11: capture once every 8 events */ + +/* Common CCMR (unshifted) Input Capture Filter bit-field definitions */ + +#define ATIM_CCMR_ICF_NOFILT (0) /* 0000: No filter, sampling at fDTS */ +#define ATIM_CCMR_ICF_FCKINT2 (1) /* 0001: fSAMPLING=fCK_INT, N=2 */ +#define ATIM_CCMR_ICF_FCKINT4 (2) /* 0010: fSAMPLING=fCK_INT, N=4 */ +#define ATIM_CCMR_ICF_FCKINT8 (3) /* 0011: fSAMPLING=fCK_INT, N=8 */ +#define ATIM_CCMR_ICF_FDTSd26 (4) /* 0100: fSAMPLING=fDTS/2, N=6 */ +#define ATIM_CCMR_ICF_FDTSd28 (5) /* 0101: fSAMPLING=fDTS/2, N=8 */ +#define ATIM_CCMR_ICF_FDTSd46 (6) /* 0110: fSAMPLING=fDTS/4, N=6 */ +#define ATIM_CCMR_ICF_FDTSd48 (7) /* 0111: fSAMPLING=fDTS/4, N=8 */ +#define ATIM_CCMR_ICF_FDTSd86 (8) /* 1000: fSAMPLING=fDTS/8, N=6 */ +#define ATIM_CCMR_ICF_FDTSd88 (9) /* 1001: fSAMPLING=fDTS/8, N=8 */ +#define ATIM_CCMR_ICF_FDTSd165 (10) /* 1010: fSAMPLING=fDTS/16, N=5 */ +#define ATIM_CCMR_ICF_FDTSd166 (11) /* 1011: fSAMPLING=fDTS/16, N=6 */ +#define ATIM_CCMR_ICF_FDTSd168 (12) /* 1100: fSAMPLING=fDTS/16, N=8 */ +#define ATIM_CCMR_ICF_FDTSd325 (13) /* 1101: fSAMPLING=fDTS/32, N=5 */ +#define ATIM_CCMR_ICF_FDTSd326 (14) /* 1110: fSAMPLING=fDTS/32, N=6 */ +#define ATIM_CCMR_ICF_FDTSd328 (15) /* 1111: fSAMPLING=fDTS/32, N=8 */ + +/* Capture/compare mode register 2 - Output Compare mode */ + +#define ATIM_CCMR2_CC3S_SHIFT (0) /* Bits 1-0: Capture/Compare 3 Selection */ +#define ATIM_CCMR2_CC3S_MASK (3 << ATIM_CCMR2_CC3S_SHIFT) + /* (See common (unshifted) bit field definitions above) */ +#define ATIM_CCMR2_OC3FE (1 << 2) /* Bit 2: Output Compare 3 Fast enable */ +#define ATIM_CCMR2_OC3PE (1 << 3) /* Bit 3: Output Compare 3 Preload enable */ +#define ATIM_CCMR2_OC3M_SHIFT (4) /* Bits 6-4: Output Compare 3 Mode */ +#define ATIM_CCMR2_OC3M_MASK (7 << ATIM_CCMR2_OC3M_SHIFT) + /* (See common (unshifted) bit field definitions above) */ +#define ATIM_CCMR2_OC3CE (1 << 7) /* Bit 7: Output Compare 3 Clear Enable */ +#define ATIM_CCMR2_CC4S_SHIFT (8) /* Bits 9-8: Capture/Compare 4 Selection */ +#define ATIM_CCMR2_CC4S_MASK (3 << ATIM_CCMR2_CC4S_SHIFT) + /* (See common (unshifted) bit field definitions above) */ +#define ATIM_CCMR2_OC4FE (1 << 10) /* Bit 10: Output Compare 4 Fast enable */ +#define ATIM_CCMR2_OC4PE (1 << 11) /* Bit 11: Output Compare 4 Preload enable */ +#define ATIM_CCMR2_OC4M_SHIFT (12) /* Bits 14-12: Output Compare 4 Mode */ +#define ATIM_CCMR2_OC4M_MASK (7 << ATIM_CCMR2_OC4M_SHIFT) + /* (See common (unshifted) bit field definitions above) */ +#define ATIM_CCMR2_OC4CE (1 << 15) /* Bit 15: Output Compare 4 Clear Enable */ +#define ATIM_CCMR2_OC3M (1 << 16) /* Bit 16: Output Compare 3 mode - bit 3 */ +#define ATIM_CCMR2_OC4M (1 << 24) /* Bit 24: Output Compare 4 mode - bit 3 */ + +/* Capture/compare mode register 2 - Input Capture Mode */ + +/* Bits 1-0: + * (same as output compare mode) + */ +#define ATIM_CCMR2_IC3PSC_SHIFT (2) /* Bits 3-2: Input Capture 3 Prescaler */ +#define ATIM_CCMR1_IC3PSC_MASK (3 << ATIM_CCMR2_IC3PSC_SHIFT) + /* (See common (unshifted) bit field definitions above) */ +#define ATIM_CCMR2_IC3F_SHIFT (4) /* Bits 7-4: Input Capture 3 Filter */ +#define ATIM_CCMR2_IC3F_MASK (0x0f << ATIM_CCMR2_IC3F_SHIFT) + /* (See common (unshifted) bit field definitions above) */ + /* Bits 9:8 (same as output compare mode) */ +#define ATIM_CCMR2_IC4PSC_SHIFT (10) /* Bits 11:10: Input Capture 4 Prescaler */ +#define ATIM_CCMR2_IC4PSC_MASK (3 << ATIM_CCMR2_IC4PSC_SHIFT) + /* (See common (unshifted) bit field definitions above) */ +#define ATIM_CCMR2_IC4F_SHIFT (12) /* Bits 15-12: Input Capture 4 Filter */ +#define ATIM_CCMR2_IC4F_MASK (0x0f << ATIM_CCMR2_IC4F_SHIFT) + /* (See common (unshifted) bit field definitions above) */ + +/* Capture/compare mode register 3 -- Output compare mode */ + +#define ATIM_CCMR3_OC5FE (1 << 2) /* Bit 2: Output Compare 5 Fast enable */ +#define ATIM_CCMR3_OC5PE (1 << 3) /* Bit 3: Output Compare 5 Preload enable */ +#define ATIM_CCMR3_OC5M_SHIFT (4) /* Bits 6-4: Output Compare 5 Mode */ +#define ATIM_CCMR3_OC5M_MASK (7 << ATIM_CCMR3_OC5M_SHIFT) + + /* (See common (unshifted) bit field definitions below) */ +#define ATIM_CCMR3_OC5CE (1 << 7) /* Bit 7: Output Compare 5 Clear Enable */ +#define ATIM_CCMR3_OC6FE (1 << 10) /* Bit 10: Output Compare 6 Fast enable */ +#define ATIM_CCMR3_OC6PE (1 << 11) /* Bit 11: Output Compare 6 Preload enable */ +#define ATIM_CCMR3_OC6M_SHIFT (12) /* Bits 14-12: Output Compare 7 Mode */ +#define ATIM_CCMR3_OC6M_MASK (7 << ATIM_CCMR3_OC6M_SHIFT) + + /* (See common (unshifted) bit field definitions below) */ +#define ATIM_CCMR3_OC6CE (1 << 15) /* Bit 15: Output Compare 7 Clear Enable */ + +#define ATIM_CCMR3_OC5M (1 << 16) /* Bit 16: Output Compare 5 mode - bit 3 */ +#define ATIM_CCMR3_OC6M (1 << 24) /* Bit 24: Output Compare 6 mode - bit 3 */ + +/* Capture/compare enable register */ + +#define ATIM_CCER_CC1E (1 << 0) /* Bit 0: Capture/Compare 1 output enable */ +#define ATIM_CCER_CC1P (1 << 1) /* Bit 1: Capture/Compare 1 output Polarity */ +#define ATIM_CCER_CC1NE (1 << 2) /* Bit 2: Capture/Compare 1 Complementary output enable */ +#define ATIM_CCER_CC1NP (1 << 3) /* Bit 3: Capture/Compare 1 Complementary output polarity */ +#define ATIM_CCER_CC2E (1 << 4) /* Bit 4: Capture/Compare 2 output enable */ +#define ATIM_CCER_CC2P (1 << 5) /* Bit 5: Capture/Compare 2 output Polarity */ +#define ATIM_CCER_CC2NE (1 << 6) /* Bit 6: Capture/Compare 2 Complementary output enable */ +#define ATIM_CCER_CC2NP (1 << 7) /* Bit 7: Capture/Compare 2 Complementary output polarity */ +#define ATIM_CCER_CC3E (1 << 8) /* Bit 8: Capture/Compare 3 output enable */ +#define ATIM_CCER_CC3P (1 << 9) /* Bit 9: Capture/Compare 3 output Polarity */ +#define ATIM_CCER_CC3NE (1 << 10) /* Bit 10: Capture/Compare 3 Complementary output enable */ +#define ATIM_CCER_CC3NP (1 << 11) /* Bit 11: Capture/Compare 3 Complementary output polarity */ +#define ATIM_CCER_CC4E (1 << 12) /* Bit 12: Capture/Compare 4 output enable */ +#define ATIM_CCER_CC4P (1 << 13) /* Bit 13: Capture/Compare 4 output Polarity */ +#define ATIM_CCER_CC4NP (1 << 15) /* Bit 15: Capture/Compare 4 Complementary output polarity */ +#define ATIM_CCER_CC5E (1 << 16) /* Bit 16: Capture/Compare 5 output enable */ +#define ATIM_CCER_CC5P (1 << 17) /* Bit 17: Capture/Compare 5 output Polarity */ +#define ATIM_CCER_CC6E (1 << 20) /* Bit 20: Capture/Compare 6 output enable */ +#define ATIM_CCER_CC6P (1 << 21) /* Bit 21: Capture/Compare 6 output Polarity */ +#define ATIM_CCER_CCXBASE(ch) (ch << 2) /* Each channel uses 4-bits */ + +/* 16-bit counter register */ + +#define ATIM_CNT_SHIFT (0) /* Bits 0-15: Timer counter value */ +#define ATIM_CNT_MASK (0xffff << ATIM_CNT_SHIFT) +#define ATIM_CCER_UIFCPY (1 << 31) /* Bit 31: UIF copy */ + +/* Repetition counter register */ + +#define ATIM_RCR_REP_SHIFT (0) /* Bits 0-15: Repetition Counter Value */ +#define ATIM_RCR_REP_MASK (0xffff << ATIM_RCR_REP_SHIFT) +#define ATIM_RCR_REP_MAX 65536 + +/* Capture/compare registers (CCR) */ + +#define ATIM_CCR5_GC5C1 (1 << 29) /* Bit 29: Group Channel 5 and Channel 1 */ +#define ATIM_CCR5_GC5C2 (1 << 30) /* Bit 30: Group Channel 5 and Channel 2 */ +#define ATIM_CCR5_GC5C3 (1 << 31) /* Bit 31: Group Channel 5 and Channel 3 */ + +#define ATIM_CCR_MASK (0xffff) + +/* Alternate function option register 1 (TIMx_AF1) */ + +#define ATIM_AF1_BKINE (1 << 0) /* Bit 0: BRK BKIN input enable */ +#define ATIM_AF1_BKINP (1 << 9) /* Bit 9: BRK BKIN input polarity */ + +#define ATIM_AF1_ETRSEL_SHIFT (14) /* Bits 14-17: ETR source selection */ +#define ATIM_AF1_ETRSEL_MASK (0xf << ATIM_AF1_ETRSEL_SHIFT) +# define ATIM_AF1_ETRLEGACY (0 << ATIM_AF1_ETRSEL_SHIFT) /* 0000: ETR legacy mode */ +# define ATIM_AF1_ADC1AWD1 (3 << ATIM_AF1_ETRSEL_SHIFT) /* 0011: ADC1 AWD1 */ +# define ATIM_AF1_ADC1AWD2 (4 << ATIM_AF1_ETRSEL_SHIFT) /* 0100: ADC1 AWD2 */ +# define ATIM_AF1_ADC1AWD3 (5 << ATIM_AF1_ETRSEL_SHIFT) /* 0101: ADC1 AWD3 */ + +/* Alternate function option register 2 (TIMx_AF2) */ + +#define ATIM_AF2_BK2INE (1 << 0) /* Bit 0: BRK2 BKIN input enable */ +#define ATIM_AF2_BK2INP (1 << 9) /* Bit 9: BRK2 BKIN2 input polarity */ + +/* Break and dead-time register */ + +#define ATIM_BDTR_DTG_SHIFT (0) /* Bits 7:0 [7:0]: Dead-Time Generator set-up */ +#define ATIM_BDTR_DTG_MASK (0xff << ATIM_BDTR_DTG_SHIFT) +#define ATIM_BDTR_LOCK_SHIFT (8) /* Bits 9:8 [1:0]: Lock Configuration */ +#define ATIM_BDTR_LOCK_MASK (3 << ATIM_BDTR_LOCK_SHIFT) +# define ATIM_BDTR_LOCKOFF (0 << ATIM_BDTR_LOCK_SHIFT) /* 00: LOCK OFF - No bit is write protected */ +# define ATIM_BDTR_LOCK1 (1 << ATIM_BDTR_LOCK_SHIFT) /* 01: LOCK Level 1 protection */ +# define ATIM_BDTR_LOCK2 (2 << ATIM_BDTR_LOCK_SHIFT) /* 10: LOCK Level 2 protection */ +# define ATIM_BDTR_LOCK3 (3 << ATIM_BDTR_LOCK_SHIFT) /* 11: LOCK Level 3 protection */ + +#define ATIM_BDTR_OSSI (1 << 10) /* Bit 10: Off-State Selection for Idle mode */ +#define ATIM_BDTR_OSSR (1 << 11) /* Bit 11: Off-State Selection for Run mode */ +#define ATIM_BDTR_BKE (1 << 12) /* Bit 12: Break enable */ +#define ATIM_BDTR_BKP (1 << 13) /* Bit 13: Break Polarity */ +#define ATIM_BDTR_AOE (1 << 14) /* Bit 14: Automatic Output enable */ +#define ATIM_BDTR_MOE (1 << 15) /* Bit 15: Main Output enable */ +#define ATIM_BDTR_BKF_SHIFT (16) /* Bits 16-19: Break filter */ +#define ATIM_BDTR_BKF_MASK (0xf << ATIM_BDTR_BKF_SHIFT) +# define ATIM_BDTR_BKF_NOFILT (0 << ATIM_BDTR_BKF_SHIFT) /* 0000: No filter, BRK acts asynchronously */ +# define ATIM_BDTR_BKF_FCKINT2 (1 << ATIM_BDTR_BKF_SHIFT) /* 0001: fSAMPLING=fCK_INT, N=2 */ +# define ATIM_BDTR_BKF_FCKINT4 (2 << ATIM_BDTR_BKF_SHIFT) /* 0010: fSAMPLING=fCK_INT, N=4 */ +# define ATIM_BDTR_BKF_FCKINT8 (3 << ATIM_BDTR_BKF_SHIFT) /* 0011: fSAMPLING=fCK_INT, N=8 */ +# define ATIM_BDTR_BKF_FDTSd26 (4 << ATIM_BDTR_BKF_SHIFT) /* 0100: fSAMPLING=fDTS/2, N=6 */ +# define ATIM_BDTR_BKF_FDTSd28 (5 << ATIM_BDTR_BKF_SHIFT) /* 0101: fSAMPLING=fDTS/2, N=8 */ +# define ATIM_BDTR_BKF_FDTSd36 (6 << ATIM_BDTR_BKF_SHIFT) /* 0110: fSAMPLING=fDTS/4, N=6 */ +# define ATIM_BDTR_BKF_FDTSd38 (7 << ATIM_BDTR_BKF_SHIFT) /* 0111: fSAMPLING=fDTS/4, N=8 */ +# define ATIM_BDTR_BKF_FDTSd86 (8 << ATIM_BDTR_BKF_SHIFT) /* 1000: fSAMPLING=fDTS/8, N=6 */ +# define ATIM_BDTR_BKF_FDTSd88 (9 << ATIM_BDTR_BKF_SHIFT) /* 1001: fSAMPLING=fDTS/8, N=8 */ +# define ATIM_BDTR_BKF_FDTSd165 (10 << ATIM_BDTR_BKF_SHIFT) /* 1010: fSAMPLING=fDTS/16, N=5 */ +# define ATIM_BDTR_BKF_FDTSd166 (11 << ATIM_BDTR_BKF_SHIFT) /* 1011: fSAMPLING=fDTS/16, N=6 */ +# define ATIM_BDTR_BKF_FDTSd168 (12 << ATIM_BDTR_BKF_SHIFT) /* 1100: fSAMPLING=fDTS/16, N=8 */ +# define ATIM_BDTR_BKF_FDTSd325 (13 << ATIM_BDTR_BKF_SHIFT) /* 1101: fSAMPLING=fDTS/32, N=5 */ +# define ATIM_BDTR_BKF_FDTSd326 (14 << ATIM_BDTR_BKF_SHIFT) /* 1110: fSAMPLING=fDTS/32, N=6 */ +# define ATIM_BDTR_BKF_FDTSd328 (15 << ATIM_BDTR_BKF_SHIFT) /* 1111: fSAMPLING=fDTS/32, N=8 */ + +#define ATIM_BDTR_BK2F_SHIFT (20) /* Bits 20-23: Break 2 filter */ +#define ATIM_BDTR_BK2F_MASK (0xf << ATIM_BDTR_BK2F_SHIFT) +# define ATIM_BDTR_BK2F_NOFILT (0 << ATIM_BDTR_BK2F_SHIFT) /* 0000: No filter, BRK 2 acts asynchronously */ +# define ATIM_BDTR_BK2F_FCKINT2 (1 << ATIM_BDTR_BK2F_SHIFT) /* 0001: fSAMPLING=fCK_INT, N=2 */ +# define ATIM_BDTR_BK2F_FCKINT4 (2 << ATIM_BDTR_BK2F_SHIFT) /* 0010: fSAMPLING=fCK_INT, N=4 */ +# define ATIM_BDTR_BK2F_FCKINT8 (3 << ATIM_BDTR_BK2F_SHIFT) /* 0011: fSAMPLING=fCK_INT, N=8 */ +# define ATIM_BDTR_BK2F_FDTSd26 (4 << ATIM_BDTR_BK2F_SHIFT) /* 0100: fSAMPLING=fDTS/2, N=6 */ +# define ATIM_BDTR_BK2F_FDTSd28 (5 << ATIM_BDTR_BK2F_SHIFT) /* 0101: fSAMPLING=fDTS/2, N=8 */ +# define ATIM_BDTR_BK2F_FDTSd36 (6 << ATIM_BDTR_BK2F_SHIFT) /* 0110: fSAMPLING=fDTS/4, N=6 */ +# define ATIM_BDTR_BK2F_FDTSd38 (7 << ATIM_BDTR_BK2F_SHIFT) /* 0111: fSAMPLING=fDTS/4, N=8 */ +# define ATIM_BDTR_BK2F_FDTSd86 (8 << ATIM_BDTR_BK2F_SHIFT) /* 1000: fSAMPLING=fDTS/8, N=6 */ +# define ATIM_BDTR_BK2F_FDTSd88 (9 << ATIM_BDTR_BK2F_SHIFT) /* 1001: fSAMPLING=fDTS/8, N=8 */ +# define ATIM_BDTR_BK2F_FDTSd165 (10 << ATIM_BDTR_BK2F_SHIFT) /* 1010: fSAMPLING=fDTS/16, N=5 */ +# define ATIM_BDTR_BK2F_FDTSd166 (11 << ATIM_BDTR_BK2F_SHIFT) /* 1011: fSAMPLING=fDTS/16, N=6 */ +# define ATIM_BDTR_BK2F_FDTSd168 (12 << ATIM_BDTR_BK2F_SHIFT) /* 1100: fSAMPLING=fDTS/16, N=8 */ +# define ATIM_BDTR_BK2F_FDTSd325 (13 << ATIM_BDTR_BK2F_SHIFT) /* 1101: fSAMPLING=fDTS/32, N=5 */ +# define ATIM_BDTR_BK2F_FDTSd326 (14 << ATIM_BDTR_BK2F_SHIFT) /* 1110: fSAMPLING=fDTS/32, N=6 */ +# define ATIM_BDTR_BK2F_FDTSd328 (15 << ATIM_BDTR_BK2F_SHIFT) /* 1111: fSAMPLING=fDTS/32, N=8 */ + +#define ATIM_BDTR_BK2E (1 << 24) /* Bit 24: Break2 enable */ +#define ATIM_BDTR_BK2P (1 << 25) /* Bit 25: Break2 polarity */ +#define ATIM_BDTR_BKDSRM (1 << 26) /* Bit 26: Break disarm */ +#define ATIM_BDTR_BK2DSRM (1 << 27) /* Bit 27: Break2 disarm */ +#define ATIM_BDTR_BKBID (1 << 28) /* Bit 28: Break bidirectional */ +#define ATIM_BDTR_BK2BID (1 << 29) /* Bit 29: Break 2 bidirectional */ + +/* DMA control register */ + +#define ATIM_DCR_DBA_SHIFT (0) /* Bits 4-0: DMA Base Address */ +#define ATIM_DCR_DBA_MASK (0x1f << ATIM_DCR_DBA_SHIFT) +#define ATIM_DCR_DBL_SHIFT (8) /* Bits 12-8: DMA Burst Length */ +#define ATIM_DCR_DBL_MASK (0x1f << ATIM_DCR_DBL_SHIFT) +# define ATIM_DCR_DBL(n) (((n)-1) << ATIM_DCR_DBL_SHIFT) /* n transfers, n = 1..18 */ + +/* Timer input selection register */ + +#define ATIM_TISEL_TI1SEL_SHIFT (0) /* Bits 3-0: Selects TI1[0] to TI1[15] input */ +#define ATIM_TISEL_TI1SEL_MASK (0xf << ATIM_TISEL_TI1SEL_SHIFT) +#define ATIM_TISEL_TI2SEL_SHIFT (8) /* Bits 11-8: Selects TI2[0] to TI2[15] input */ +#define ATIM_TISEL_TI2SEL_MASK (0xf << ATIM_TISEL_TI2SEL_SHIFT) +#define ATIM_TISEL_TI3SEL_SHIFT (16) /* Bits 19-16: Selects TI3[0] to TI3[15] input */ +#define ATIM_TISEL_TI3SEL_MASK (0xf << ATIM_TISEL_TI3SEL_SHIFT) +#define ATIM_TISEL_TI4SEL_SHIFT (24) /* Bits 27-24: Selects TI4[0] to TI4[15] input */ +#define ATIM_TISEL_TI4SEL_MASK (0xf << ATIM_TISEL_TI4SEL_SHIFT) + +/* Control register 1 */ + +#define GTIM_CR1_CEN (1 << 0) /* Bit 0: Counter enable */ +#define GTIM_CR1_UDIS (1 << 1) /* Bit 1: Update Disable */ +#define GTIM_CR1_URS (1 << 2) /* Bit 2: Update Request Source */ +#define GTIM_CR1_OPM (1 << 3) /* Bit 3: One Pulse Mode */ +#define GTIM_CR1_DIR (1 << 4) /* Bit 4: Direction (TIM3 only) */ +#define GTIM_CR1_CMS_SHIFT (5) /* Bits 6-5: Center-aligned Mode Selection (TIM3 only) */ +#define GTIM_CR1_CMS_MASK (3 << GTIM_CR1_CMS_SHIFT) +# define GTIM_CR1_EDGE (0 << GTIM_CR1_CMS_SHIFT) /* 00: Edge-aligned mode. */ +# define GTIM_CR1_CENTER1 (1 << GTIM_CR1_CMS_SHIFT) /* 01: Center-aligned mode 1 */ +# define GTIM_CR1_CENTER2 (2 << GTIM_CR1_CMS_SHIFT) /* 10: Center-aligned mode 2 */ +# define GTIM_CR1_CENTER3 (3 << GTIM_CR1_CMS_SHIFT) /* 11: Center-aligned mode 3 */ + +#define GTIM_CR1_ARPE (1 << 7) /* Bit 7: Auto-Reload Preload enable */ +#define GTIM_CR1_CKD_SHIFT (8) /* Bits 9-8: Clock Division */ +#define GTIM_CR1_CKD_MASK (3 << GTIM_CR1_CKD_SHIFT) +# define GTIM_CR1_TCKINT (0 << GTIM_CR1_CKD_SHIFT) /* 00: tDTS = tCK_INT */ +# define GTIM_CR1_2TCKINT (1 << GTIM_CR1_CKD_SHIFT) /* 01: tDTS = 2 x tCK_INT */ +# define GTIM_CR1_4TCKINT (2 << GTIM_CR1_CKD_SHIFT) /* 10: tDTS = 4 x tCK_INT */ + +#define GTIM_CR1_UIFREMAP (1 << 11) /* Bit 11: UIF status bit remapping */ + +/* Control register 2 (16-bit TIM3 and TIM15-17) */ + +#define GTIM_CR2_CCPC (1 << 0) /* Bit 0: Capture/compare preloaded control (TIM15-17 only) */ +#define GTIM_CR2_CCUS (1 << 2) /* Bit 2: Capture/compare control update selection (TIM15 only) */ +#define GTIM_CR2_CCDS (1 << 3) /* Bit 3: Capture/Compare DMA Selection */ +#define GTIM_CR2_MMS_SHIFT (4) /* Bits 6-4: Master Mode Selection (TIM3 and TIM15 only) */ +#define GTIM_CR2_MMS_MASK (7 << GTIM_CR2_MMS_SHIFT) +# define GTIM_CR2_MMS_RESET (0 << GTIM_CR2_MMS_SHIFT) /* 000: Reset */ +# define GTIM_CR2_MMS_ENABLE (1 << GTIM_CR2_MMS_SHIFT) /* 001: Enable */ +# define GTIM_CR2_MMS_UPDATE (2 << GTIM_CR2_MMS_SHIFT) /* 010: Update */ +# define GTIM_CR2_MMS_COMPP (3 << GTIM_CR2_MMS_SHIFT) /* 011: Compare Pulse */ +# define GTIM_CR2_MMS_OC1REF (4 << GTIM_CR2_MMS_SHIFT) /* 100: Compare - OC1REF signal is used as trigger output (TRGO) */ +# define GTIM_CR2_MMS_OC2REF (5 << GTIM_CR2_MMS_SHIFT) /* 101: Compare - OC2REF signal is used as trigger output (TRGO) */ +# define GTIM_CR2_MMS_OC3REF (6 << GTIM_CR2_MMS_SHIFT) /* 110: Compare - OC3REF signal is used as trigger output (TRGO, TIM3 only) */ +# define GTIM_CR2_MMS_OC4REF (7 << GTIM_CR2_MMS_SHIFT) /* 111: Compare - OC4REF signal is used as trigger output (TRGO, TIM3 only) */ + +#define GTIM_CR2_TI1S (1 << 7) /* Bit 7: TI1 Selection (TIM3 and TIM15 only) */ +#define GTIM_CR2_OIS1 (1 << 8) /* Bit 8: COutput Idle state 1 (OC1 output) (TIM15-17 only) */ +#define GTIM_CR2_OIS1N (1 << 9) /* Bit 9: Output Idle state 1 (OC1N output) (TIM15-17 only) */ +#define GTIM_CR2_OIS2 (1 << 10) /* Bit 10: Output idle state 2 (OC2 output) (TIM15 only) */ + +/* Slave mode control register (TIM3 and TIM15 only) */ + +#define GTIM_SMCR_SMS_SHIFT (0) /* Bits 2-0: Slave Mode Selection */ +#define GTIM_SMCR_SMS_MASK (7 << GTIM_SMCR_SMS_SHIFT) +# define GTIM_SMCR_DISAB (0 << GTIM_SMCR_SMS_SHIFT) /* 000: Slave mode disabled */ +# define GTIM_SMCR_ENCMD1 (1 << GTIM_SMCR_SMS_SHIFT) /* 001: Encoder mode 1 */ +# define GTIM_SMCR_ENCMD2 (2 << GTIM_SMCR_SMS_SHIFT) /* 010: Encoder mode 2 */ +# define GTIM_SMCR_ENCMD3 (3 << GTIM_SMCR_SMS_SHIFT) /* 011: Encoder mode 3 */ +# define GTIM_SMCR_RESET (4 << GTIM_SMCR_SMS_SHIFT) /* 100: Reset Mode */ +# define GTIM_SMCR_GATED (5 << GTIM_SMCR_SMS_SHIFT) /* 101: Gated Mode */ +# define GTIM_SMCR_TRIGGER (6 << GTIM_SMCR_SMS_SHIFT) /* 110: Trigger Mode */ +# define GTIM_SMCR_EXTCLK1 (7 << GTIM_SMCR_SMS_SHIFT) /* 111: External Clock Mode 1 */ + +#define GTIM_SMCR_OCCS (1 << 3) /* Bit 3: OCREF Clear Selection (TIM3 only) */ +#define GTIM_SMCR_TS_SHIFT (4) /* Bits 6-4: Trigger Selection. See TS2 below for more options. */ +#define GTIM_SMCR_TS_MASK (7 << GTIM_SMCR_TS_SHIFT) +# define GTIM_SMCR_ITR0 (0 << GTIM_SMCR_TS_SHIFT) /* 000: Internal Trigger 0 (ITR0). For TIM3: TIM1. */ +# define GTIM_SMCR_ITR1 (1 << GTIM_SMCR_TS_SHIFT) /* 001: Internal Trigger 1 (ITR1). For TIM15: TIM3*/ +# define GTIM_SMCR_ITR2 (2 << GTIM_SMCR_TS_SHIFT) /* 010: Internal Trigger 2 (ITR2). For TIM3: TIM15. For TIM15: TIM16_OC1 */ +# define GTIM_SMCR_ITR3 (3 << GTIM_SMCR_TS_SHIFT) /* 011: Internal Trigger 3 (ITR3). For TIM3: TIM14_OC1. For TIM15: TIM17_OC1 */ +# define GTIM_SMCR_TI1FED (4 << GTIM_SMCR_TS_SHIFT) /* 100: TI1 Edge Detector (TI1F_ED) */ +# define GTIM_SMCR_TI1FP1 (5 << GTIM_SMCR_TS_SHIFT) /* 101: Filtered Timer Input 1 (TI1FP1) */ +# define GTIM_SMCR_TI2FP2 (6 << GTIM_SMCR_TS_SHIFT) /* 110: Filtered Timer Input 2 (TI2FP2) */ +# define GTIM_SMCR_ETRF (7 << GTIM_SMCR_TS_SHIFT) /* 111: External Trigger input (ETRF) */ + +#define GTIM_SMCR_MSM (1 << 7) /* Bit 7: Master/Slave mode */ +#define GTIM_SMCR_ETF_SHIFT (8) /* Bits 11-8: External Trigger Filter (TIM3 only) */ +#define GTIM_SMCR_ETF_MASK (0x0f << GTIM_SMCR_ETF_SHIFT) +# define GTIM_SMCR_NOFILT (0 << GTIM_SMCR_ETF_SHIFT) /* 0000: No filter, sampling is done at fDTS */ +# define GTIM_SMCR_FCKINT2 (1 << GTIM_SMCR_ETF_SHIFT) /* 0001: fSAMPLING=fCK_INT, N=2 */ +# define GTIM_SMCR_FCKINT4 (2 << GTIM_SMCR_ETF_SHIFT) /* 0010: fSAMPLING=fCK_INT, N=4 */ +# define GTIM_SMCR_FCKINT8 (3 << GTIM_SMCR_ETF_SHIFT) /* 0011: fSAMPLING=fCK_INT, N=8 */ +# define GTIM_SMCR_FDTSd26 (4 << GTIM_SMCR_ETF_SHIFT) /* 0100: fSAMPLING=fDTS/2, N=6 */ +# define GTIM_SMCR_FDTSd28 (5 << GTIM_SMCR_ETF_SHIFT) /* 0101: fSAMPLING=fDTS/2, N=8 */ +# define GTIM_SMCR_FDTSd36 (6 << GTIM_SMCR_ETF_SHIFT) /* 0110: fSAMPLING=fDTS/4, N=6 */ +# define GTIM_SMCR_FDTSd38 (7 << GTIM_SMCR_ETF_SHIFT) /* 0111: fSAMPLING=fDTS/4, N=8 */ +# define GTIM_SMCR_FDTSd86 (8 << GTIM_SMCR_ETF_SHIFT) /* 1000: fSAMPLING=fDTS/8, N=6 */ +# define GTIM_SMCR_FDTSd88 (9 << GTIM_SMCR_ETF_SHIFT) /* 1001: fSAMPLING=fDTS/8, N=8 */ +# define GTIM_SMCR_FDTSd165 (10 << GTIM_SMCR_ETF_SHIFT) /* 1010: fSAMPLING=fDTS/16, N=5 */ +# define GTIM_SMCR_FDTSd166 (11 << GTIM_SMCR_ETF_SHIFT) /* 1011: fSAMPLING=fDTS/16, N=6 */ +# define GTIM_SMCR_FDTSd168 (12 << GTIM_SMCR_ETF_SHIFT) /* 1100: fSAMPLING=fDTS/16, N=8 */ +# define GTIM_SMCR_FDTSd325 (13 << GTIM_SMCR_ETF_SHIFT) /* 1101: fSAMPLING=fDTS/32, N=5 */ +# define GTIM_SMCR_FDTSd326 (14 << GTIM_SMCR_ETF_SHIFT) /* 1110: fSAMPLING=fDTS/32, N=6 */ +# define GTIM_SMCR_FDTSd328 (15 << GTIM_SMCR_ETF_SHIFT) /* 1111: fSAMPLING=fDTS/32, N=8 */ + +#define GTIM_SMCR_ETPS_SHIFT (12) /* Bits 13-12: External Trigger Prescaler (TIM3 only) */ +#define GTIM_SMCR_ETPS_MASK (3 << GTIM_SMCR_ETPS_SHIFT) +# define GTIM_SMCR_PSCOFF (0 << GTIM_SMCR_ETPS_SHIFT) /* 00: Prescaler OFF */ +# define GTIM_SMCR_ETRPd2 (1 << GTIM_SMCR_ETPS_SHIFT) /* 01: ETRP frequency divided by 2 */ +# define GTIM_SMCR_ETRPd4 (2 << GTIM_SMCR_ETPS_SHIFT) /* 10: ETRP frequency divided by 4 */ +# define GTIM_SMCR_ETRPd8 (3 << GTIM_SMCR_ETPS_SHIFT) /* 11: ETRP frequency divided by 8 */ + +#define GTIM_SMCR_ECE (1 << 14) /* Bit 14: External Clock enable (TIM3 only) */ +#define GTIM_SMCR_ETP (1 << 15) /* Bit 15: External Trigger Polarity (TIM3 only) */ +#define GTIM_SMCR_SMS (1 << 16) /* Bit 16: Slave mode selection - bit 3 */ +#define GTIM_SMCR_TS2_SHIFT (4) /* Bits 21-20: Trigger Selection - bits 3-4 + * Other values for TS (including bits 3-4): + * 01000: Internal Trigger 4 (ITR4) + * 01001: Internal Trigger 5 (ITR5) + * 01010: Internal Trigger 6 (ITR6) + * 01011: Internal Trigger 7 (ITR7) + * 01100: Internal Trigger 8 (ITR8) + */ +#define GTIM_SMCR_TS2_MASK (3 << GTIM_SMCR_TS_SHIFT) + +/* DMA/Interrupt enable register */ + +#define GTIM_DIER_UIE (1 << 0) /* Bit 0: Update interrupt enable */ +#define GTIM_DIER_CC1IE (1 << 1) /* Bit 1: Capture/Compare 1 interrupt enable */ +#define GTIM_DIER_CC2IE (1 << 2) /* Bit 2: Capture/Compare 2 interrupt enable (TIM3, TIM15 only) */ +#define GTIM_DIER_CC3IE (1 << 3) /* Bit 3: Capture/Compare 3 interrupt enable (TIM3 only) */ +#define GTIM_DIER_CC4IE (1 << 4) /* Bit 4: Capture/Compare 4 interrupt enable (TIM3 only) */ +#define GTIM_DIER_COMIE (1 << 5) /* Bit 5: COM interrupt enable (TIM15-17 only) */ +#define GTIM_DIER_TIE (1 << 6) /* Bit 6: Trigger interrupt enable (TIM3, TIM15 only) */ +#define GTIM_DIER_BIE (1 << 7) /* Bit 7: Break interrupt enable (TIM15-17 only) */ +#define GTIM_DIER_UDE (1 << 8) /* Bit 8: Update DMA request enable (TIM3, TIM15-17 only) */ +#define GTIM_DIER_CC1DE (1 << 9) /* Bit 9: Capture/Compare 1 DMA request enable (TIM3, TIM15-17 only) */ +#define GTIM_DIER_CC2DE (1 << 10) /* Bit 10: Capture/Compare 2 DMA request enable (TIM3, TIM15 only) */ +#define GTIM_DIER_CC3DE (1 << 11) /* Bit 11: Capture/Compare 3 DMA request enable (TIM3 only) */ +#define GTIM_DIER_CC4DE (1 << 12) /* Bit 12: Capture/Compare 4 DMA request enable (TIM3 only) */ +#define GTIM_DIER_COMDE (1 << 13) /* Bit 13: COM DMA request enable (TIM15 only) */ +#define GTIM_DIER_TDE (1 << 14) /* Bit 14: Trigger DMA request enable (TIM3, TIM15 only) */ + +/* Status register */ + +#define GTIM_SR_UIF (1 << 0) /* Bit 0: Update interrupt flag */ +#define GTIM_SR_CC1IF (1 << 1) /* Bit 1: Capture/compare 1 interrupt flag */ +#define GTIM_SR_CC2IF (1 << 2) /* Bit 2: Capture/Compare 2 interrupt flag (TIM3,15 only) */ +#define GTIM_SR_CC3IF (1 << 3) /* Bit 3: Capture/Compare 3 interrupt flag (TIM3,15 only) */ +#define GTIM_SR_CC4IF (1 << 4) /* Bit 4: Capture/Compare 4 interrupt flag (TIM3,15 only) */ +#define GTIM_SR_COMIF (1 << 5) /* Bit 5: COM interrupt flag (TIM15-17 only) */ +#define GTIM_SR_TIF (1 << 6) /* Bit 6: Trigger interrupt Flag (TIM3,15 only) */ +#define GTIM_SR_BIF (1 << 7) /* Bit 7: Break interrupt flag (TIM15-17 only) */ +#define GTIM_SR_CC1OF (1 << 9) /* Bit 9: Capture/Compare 1 Overcapture flag */ +#define GTIM_SR_CC2OF (1 << 10) /* Bit 10: Capture/Compare 2 Overcapture flag (TIM3,15 only) */ +#define GTIM_SR_CC3OF (1 << 11) /* Bit 11: Capture/Compare 3 Overcapture flag (TIM3 only) */ +#define GTIM_SR_CC4OF (1 << 12) /* Bit 12: Capture/Compare 4 Overcapture flag (TIM3 only) */ + +/* Event generation register */ + +#define GTIM_EGR_UG (1 << 0) /* Bit 0: Update generation */ +#define GTIM_EGR_CC1G (1 << 1) /* Bit 1: Capture/compare 1 generation */ +#define GTIM_EGR_CC2G (1 << 2) /* Bit 2: Capture/compare 2 generation (TIM3,15 only) */ +#define GTIM_EGR_CC3G (1 << 3) /* Bit 3: Capture/compare 3 generation (TIM3 only) */ +#define GTIM_EGR_CC4G (1 << 4) /* Bit 4: Capture/compare 4 generation (TIM3 only) */ +#define GTIM_EGR_COMIG (1 << 5) /* Bit 5: Capture/Compare control update generation (TIM15-17 only) */ +#define GTIM_EGR_TG (1 << 6) /* Bit 6: Trigger generation (TIM3,15 only) */ +#define GTIM_EGR_BG (1 << 7) /* Bit 7: Break generation (TIM15-17 only) */ + +/* Capture/compare mode register 1 - Output compare mode */ + +#define GTIM_CCMR1_CC1S_SHIFT (0) /* Bits 1-0: Capture/Compare 1 Selection */ +#define GTIM_CCMR1_CC1S_MASK (3 << GTIM_CCMR1_CC1S_SHIFT) + /* (See common CCMR Capture/Compare Selection definitions below) */ +#define GTIM_CCMR1_OC1FE (1 << 2) /* Bit 2: Output Compare 1 Fast enable */ +#define GTIM_CCMR1_OC1PE (1 << 3) /* Bit 3: Output Compare 1 Preload enable */ +#define GTIM_CCMR1_OC1M_SHIFT (4) /* Bits 6-4: Output Compare 1 Mode */ +#define GTIM_CCMR1_OC1M_MASK (7 << GTIM_CCMR1_OC1M_SHIFT) + /* (See common CCMR Output Compare Mode definitions below) */ +#define GTIM_CCMR1_OC1CE (1 << 7) /* Bit 7: Output Compare 1Clear Enable (TIM3 only) */ +#define GTIM_CCMR1_CC2S_SHIFT (8) /* Bits 9-8: Capture/Compare 2 Selection (TIM3,15 only) */ +#define GTIM_CCMR1_CC2S_MASK (3 << GTIM_CCMR1_CC2S_SHIFT) + /* (See common CCMR Capture/Compare Selection definitions below) */ +#define GTIM_CCMR1_OC2FE (1 << 10) /* Bit 10: Output Compare 2 Fast enable (TIM3,15 only) */ +#define GTIM_CCMR1_OC2PE (1 << 11) /* Bit 11: Output Compare 2 Preload enable (TIM3,15 only) */ +#define GTIM_CCMR1_OC2M_SHIFT (12) /* Bits 14-12: Output Compare 2 Mode (TIM3,15 only) */ +#define GTIM_CCMR1_OC2M_MASK (7 << GTIM_CCMR1_OC2M_SHIFT) + /* (See common CCMR Output Compare Mode definitions below) */ +#define GTIM_CCMR1_OC2CE (1 << 15) /* Bit 15: Output Compare 2 Clear Enable (TIM3 only) */ +#define GTIM_CCMR1_OC1M (1 << 16) /* Bit 16: Output Compare 1 mode - bit 3 */ +#define GTIM_CCMR1_OC2M (1 << 24) /* Bit 24: Output Compare 2 mode - bit 3 (TIM3,15 only) */ + +/* Common CCMR (unshifted) Capture/Compare Selection bit-field definitions */ + +#define GTIM_CCMR_CCS_CCOUT (0) /* 00: CCx channel output */ +#define GTIM_CCMR_CCS_CCIN1 (1) /* 01: CCx channel input, ICx is TIx */ +#define GTIM_CCMR_CCS_CCIN2 (2) /* 10: CCx channel input, ICx is TIy */ +#define GTIM_CCMR_CCS_CCINTRC (3) /* 11: CCx channel input, ICx is TRC */ + +/* Common CCMR (unshifted) Compare Mode bit field definitions */ + +#define GTIM_CCMR_MODE_FRZN (0) /* 000: Frozen */ +#define GTIM_CCMR_MODE_CHACT (1) /* 001: Channel x active on match */ +#define GTIM_CCMR_MODE_CHINACT (2) /* 010: Channel x inactive on match */ +#define GTIM_CCMR_MODE_OCREFTOG (3) /* 011: OCxREF toggle ATIM_CNT=ATIM_CCRx */ +#define GTIM_CCMR_MODE_OCREFLO (4) /* 100: OCxREF forced low */ +#define GTIM_CCMR_MODE_OCREFHI (5) /* 101: OCxREF forced high */ +#define GTIM_CCMR_MODE_PWM1 (6) /* 110: PWM mode 1 */ +#define GTIM_CCMR_MODE_PWM2 (7) /* 111: PWM mode 2 */ +#define GTIM_CCMR_MODE_RETRIG1 (8) /* 1000: Retrigerrable OPM mode 1 (TIM3,15 only) */ +#define GTIM_CCMR_MODE_RETRIG2 (9) /* 1001: Retrigerrable OPM mode 2 (TIM3,15 only) */ +#define GTIM_CCMR_MODE_COMBINED1 (12) /* 1100: Combined PWM mode 1 (TIM3,15 only) */ +#define GTIM_CCMR_MODE_COMBINED2 (13) /* 1101: Combined PWM mode 2 (TIM3,15 only) */ +#define GTIM_CCMR_MODE_ASYMMETRIC1 (14) /* 1110: Asymmetric PWM mode 1 (TIM3 only) */ +#define GTIM_CCMR_MODE_ASYMMETRIC2 (15) /* 1111: Asymmetric PWM mode 2 (TIM3 only) */ + +/* Capture/compare mode register 1 - Input capture mode */ + +/* Bits 1-0 + * (Same as Output Compare Mode) + */ +#define GTIM_CCMR1_IC1PSC_SHIFT (2) /* Bits 3-2: Input Capture 1 Prescaler */ +#define GTIM_CCMR1_IC1PSC_MASK (3 << GTIM_CCMR1_IC1PSC_SHIFT) + /* (See common CCMR Input Capture Prescaler definitions below) */ +#define GTIM_CCMR1_IC1F_SHIFT (4) /* Bits 7-4: Input Capture 1 Filter */ +#define GTIM_CCMR1_IC1F_MASK (0x0f << GTIM_CCMR1_IC1F_SHIFT) + /* (See common CCMR Input Capture Filter definitions below) */ + /* Bits 9-8: (Same as Output Compare Mode) (TIM3,15 only) */ +#define GTIM_CCMR1_IC2PSC_SHIFT (10) /* Bits 11-10: Input Capture 2 Prescaler (TIM3,15 only) */ +#define GTIM_CCMR1_IC2PSC_MASK (3 << GTIM_CCMR1_IC2PSC_SHIFT) + /* (See common CCMR Input Capture Prescaler definitions below) */ +#define GTIM_CCMR1_IC2F_SHIFT (12) /* Bits 15-12: Input Capture 2 Filter (TIM3,15 only) */ +#define GTIM_CCMR1_IC2F_MASK (0x0f << GTIM_CCMR1_IC2F_SHIFT) + /* (See common CCMR Input Capture Filter definitions below) */ + +/* Common CCMR (unshifted) Input Capture Prescaler bit-field definitions */ + +#define GTIM_CCMR_ICPSC_NOPSC (0) /* 00: no prescaler, capture each edge */ +#define GTIM_CCMR_ICPSC_EVENTS2 (1) /* 01: capture once every 2 events */ +#define GTIM_CCMR_ICPSC_EVENTS4 (2) /* 10: capture once every 4 events */ +#define GTIM_CCMR_ICPSC_EVENTS8 (3) /* 11: capture once every 8 events */ + +/* Common CCMR (unshifted) Input Capture Filter bit-field definitions */ + +#define GTIM_CCMR_ICF_NOFILT (0) /* 0000: No filter, sampling at fDTS */ +#define GTIM_CCMR_ICF_FCKINT2 (1) /* 0001: fSAMPLING=fCK_INT, N=2 */ +#define GTIM_CCMR_ICF_FCKINT4 (2) /* 0010: fSAMPLING=fCK_INT, N=4 */ +#define GTIM_CCMR_ICF_FCKINT8 (3) /* 0011: fSAMPLING=fCK_INT, N=8 */ +#define GTIM_CCMR_ICF_FDTSd26 (4) /* 0100: fSAMPLING=fDTS/2, N=6 */ +#define GTIM_CCMR_ICF_FDTSd28 (5) /* 0101: fSAMPLING=fDTS/2, N=8 */ +#define GTIM_CCMR_ICF_FDTSd46 (6) /* 0110: fSAMPLING=fDTS/4, N=6 */ +#define GTIM_CCMR_ICF_FDTSd48 (7) /* 0111: fSAMPLING=fDTS/4, N=8 */ +#define GTIM_CCMR_ICF_FDTSd86 (8) /* 1000: fSAMPLING=fDTS/8, N=6 */ +#define GTIM_CCMR_ICF_FDTSd88 (9) /* 1001: fSAMPLING=fDTS/8, N=8 */ +#define GTIM_CCMR_ICF_FDTSd165 (10) /* 1010: fSAMPLING=fDTS/16, N=5 */ +#define GTIM_CCMR_ICF_FDTSd166 (11) /* 1011: fSAMPLING=fDTS/16, N=6 */ +#define GTIM_CCMR_ICF_FDTSd168 (12) /* 1100: fSAMPLING=fDTS/16, N=8 */ +#define GTIM_CCMR_ICF_FDTSd325 (13) /* 1101: fSAMPLING=fDTS/32, N=5 */ +#define GTIM_CCMR_ICF_FDTSd326 (14) /* 1110: fSAMPLING=fDTS/32, N=6 */ +#define GTIM_CCMR_ICF_FDTSd328 (15) /* 1111: fSAMPLING=fDTS/32, N=8 */ + +/* Capture/compare mode register 2 - Output Compare mode (TIM3 only) */ + +#define GTIM_CCMR2_CC3S_SHIFT (0) /* Bits 1-0: Capture/Compare 3 Selection */ +#define GTIM_CCMR2_CC3S_MASK (3 << GTIM_CCMR2_CC3S_SHIFT) + /* (See common CCMR Capture/Compare Selection definitions above) */ +#define GTIM_CCMR2_OC3FE (1 << 2) /* Bit 2: Output Compare 3 Fast enable */ +#define GTIM_CCMR2_OC3PE (1 << 3) /* Bit 3: Output Compare 3 Preload enable */ +#define GTIM_CCMR2_OC3M_SHIFT (4) /* Bits 6-4: Output Compare 3 Mode */ +#define GTIM_CCMR2_OC3M_MASK (7 << GTIM_CCMR2_OC3M_SHIFT) + /* (See common CCMR Output Compare Mode definitions above) */ +#define GTIM_CCMR2_OC3CE (1 << 7) /* Bit 7: Output Compare 3 Clear Enable */ +#define GTIM_CCMR2_CC4S_SHIFT (8) /* Bits 9-8: Capture/Compare 4 Selection */ +#define GTIM_CCMR2_CC4S_MASK (3 << GTIM_CCMR2_CC4S_SHIFT) + /* (See common CCMR Capture/Compare Selection definitions above) */ +#define GTIM_CCMR2_OC4FE (1 << 10) /* Bit 10: Output Compare 4 Fast enable */ +#define GTIM_CCMR2_OC4PE (1 << 11) /* Bit 11: Output Compare 4 Preload enable */ +#define GTIM_CCMR2_OC4M_SHIFT (12) /* Bits 14-12: Output Compare 4 Mode */ +#define GTIM_CCMR2_OC4M_MASK (7 << GTIM_CCMR2_OC4M_SHIFT) + /* (See common CCMR Output Compare Mode definitions above) */ +#define GTIM_CCMR2_OC4CE (1 << 15) /* Bit 15: Output Compare 4 Clear Enable */ + +/* Capture/compare mode register 2 - Input capture mode (TIM3 only) */ + +/* Bits 1-0 + * (Same as Output Compare Mode) + */ +#define GTIM_CCMR2_IC3PSC_SHIFT (2) /* Bits 3-2: Input Capture 3 Prescaler */ +#define GTIM_CCMR2_IC3PSC_MASK (3 << GTIM_CCMR2_IC3PSC_SHIFT) + /* (See common CCMR Input Capture Prescaler definitions below) */ +#define GTIM_CCMR2_IC3F_SHIFT (4) /* Bits 7-4: Input Capture 3 Filter */ +#define GTIM_CCMR2_IC3F_MASK (0x0f << GTIM_CCMR2_IC3F_SHIFT) + /* (See common CCMR Input Capture Filter definitions below) */ + /* Bits 9-8: (Same as Output Compare Mode) */ +#define GTIM_CCMR2_IC4PSC_SHIFT (10) /* Bits 11-10: Input Capture 4 Prescaler */ +#define GTIM_CCMR2_IC4PSC_MASK (3 << GTIM_CCMR2_IC4PSC_SHIFT) + /* (See common CCMR Input Capture Prescaler definitions below) */ +#define GTIM_CCMR2_IC4F_SHIFT (12) /* Bits 15-12: Input Capture 4 Filter */ +#define GTIM_CCMR2_IC4F_MASK (0x0f << GTIM_CCMR2_IC4F_SHIFT) + /* (See common CCMR Input Capture Filter definitions below) */ + +/* Capture/compare enable register */ + +#define GTIM_CCER_CC1E (1 << 0) /* Bit 0: Capture/Compare 1 output enable */ +#define GTIM_CCER_CC1P (1 << 1) /* Bit 1: Capture/Compare 1 output polarity */ +#define GTIM_CCER_CC1NE (1 << 2) /* Bit 2: Capture/Compare 1 complementary output enable (TIM15-17 only) */ +#define GTIM_CCER_CC1NP (1 << 3) /* Bit 3: Capture/Compare 1 output Polarity (TIM3,14-17 only) */ +#define GTIM_CCER_CC2E (1 << 4) /* Bit 4: Capture/Compare 2 output enable (TIM3,15 only) */ +#define GTIM_CCER_CC2P (1 << 5) /* Bit 5: Capture/Compare 2 output polarity (TIM3,15 only) */ +#define GTIM_CCER_CC2NP (1 << 7) /* Bit 7: Capture/Compare 2 output Polarity (TIM3,15 only) */ +#define GTIM_CCER_CC3E (1 << 8) /* Bit 8: Capture/Compare 3 output enable (TIM3 only) */ +#define GTIM_CCER_CC3P (1 << 9) /* Bit 9: Capture/Compare 3 output Polarity (TIM3 only) */ +#define GTIM_CCER_CC3NP (1 << 11) /* Bit 11: Capture/Compare 3 output Polarity (TIM3 only) */ +#define GTIM_CCER_CC4E (1 << 12) /* Bit 12: Capture/Compare 4 output enable (TIM3 only) */ +#define GTIM_CCER_CC4P (1 << 13) /* Bit 13: Capture/Compare 4 output Polarity (TIM3 only) */ +#define GTIM_CCER_CC4NP (1 << 15) /* Bit 15: Capture/Compare 4 output Polarity (TIM3 only) */ +#define GTIM_CCER_CCXBASE(ch) (ch << 2) /* Each channel uses 4-bits */ + +/* 16-bit counter register */ + +#define GTIM_CNT_SHIFT (0) /* Bits 0-15: Timer counter value */ +#define GTIM_CNT_MASK (0xffff << ATIM_CNT_SHIFT) + +/* Repetition counter (TIM15-17 only) */ + +#define GTIM_RCR_REP_SHIFT (0) /* Bits 0-7: Repetition Counter Value */ +#define GTIM_RCR_REP_MASK (0xff << GTIM_RCR_REP_SHIFT) + +#define GTIM_RCR_REP_MAX 255 + +/* Break and dead-time register (TIM15-17 only) */ + +#define GTIM_BDTR_DTG_SHIFT (0) /* Bits 7:0 [7:0]: Dead-Time Generator set-up */ +#define GTIM_BDTR_DTG_MASK (0xff << GTIM_BDTR_DTG_SHIFT) +#define GTIM_BDTR_LOCK_SHIFT (8) /* Bits 9:8 [1:0]: Lock Configuration */ +#define GTIM_BDTR_LOCK_MASK (3 << GTIM_BDTR_LOCK_SHIFT) +# define GTIM_BDTR_LOCKOFF (0 << GTIM_BDTR_LOCK_SHIFT) /* 00: LOCK OFF - No bit is write protected */ +# define GTIM_BDTR_LOCK1 (1 << GTIM_BDTR_LOCK_SHIFT) /* 01: LOCK Level 1 protection */ +# define GTIM_BDTR_LOCK2 (2 << GTIM_BDTR_LOCK_SHIFT) /* 10: LOCK Level 2 protection */ +# define GTIM_BDTR_LOCK3 (3 << GTIM_BDTR_LOCK_SHIFT) /* 11: LOCK Level 3 protection */ + +#define GTIM_BDTR_OSSI (1 << 10) /* Bit 10: Off-State Selection for Idle mode */ +#define GTIM_BDTR_OSSR (1 << 11) /* Bit 11: Off-State Selection for Run mode */ +#define GTIM_BDTR_BKE (1 << 12) /* Bit 12: Break enable */ +#define GTIM_BDTR_BKP (1 << 13) /* Bit 13: Break Polarity */ +#define GTIM_BDTR_AOE (1 << 14) /* Bit 14: Automatic Output enable */ +#define GTIM_BDTR_MOE (1 << 15) /* Bit 15: Main Output enable */ +#define GTIM_BDTR_BKF_SHIFT (16) /* Bits 16-19: Break filter */ +#define GTIM_BDTR_BKF_MASK (0xf << GTIM_BDTR_BKF_SHIFT) +# define GTIM_BDTR_BKF_NOFILT (0 << GTIM_BDTR_BKF_SHIFT) /* 0000: No filter, BRK acts asynchronously */ +# define GTIM_BDTR_BKF_FCKINT2 (1 << GTIM_BDTR_BKF_SHIFT) /* 0001: fSAMPLING=fCK_INT, N=2 */ +# define GTIM_BDTR_BKF_FCKINT4 (2 << GTIM_BDTR_BKF_SHIFT) /* 0010: fSAMPLING=fCK_INT, N=4 */ +# define GTIM_BDTR_BKF_FCKINT8 (3 << GTIM_BDTR_BKF_SHIFT) /* 0011: fSAMPLING=fCK_INT, N=8 */ +# define GTIM_BDTR_BKF_FDTSd26 (4 << GTIM_BDTR_BKF_SHIFT) /* 0100: fSAMPLING=fDTS/2, N=6 */ +# define GTIM_BDTR_BKF_FDTSd28 (5 << GTIM_BDTR_BKF_SHIFT) /* 0101: fSAMPLING=fDTS/2, N=8 */ +# define GTIM_BDTR_BKF_FDTSd36 (6 << GTIM_BDTR_BKF_SHIFT) /* 0110: fSAMPLING=fDTS/4, N=6 */ +# define GTIM_BDTR_BKF_FDTSd38 (7 << GTIM_BDTR_BKF_SHIFT) /* 0111: fSAMPLING=fDTS/4, N=8 */ +# define GTIM_BDTR_BKF_FDTSd86 (8 << GTIM_BDTR_BKF_SHIFT) /* 1000: fSAMPLING=fDTS/8, N=6 */ +# define GTIM_BDTR_BKF_FDTSd88 (9 << GTIM_BDTR_BKF_SHIFT) /* 1001: fSAMPLING=fDTS/8, N=8 */ +# define GTIM_BDTR_BKF_FDTSd165 (10 << GTIM_BDTR_BKF_SHIFT) /* 1010: fSAMPLING=fDTS/16, N=5 */ +# define GTIM_BDTR_BKF_FDTSd166 (11 << GTIM_BDTR_BKF_SHIFT) /* 1011: fSAMPLING=fDTS/16, N=6 */ +# define GTIM_BDTR_BKF_FDTSd168 (12 << GTIM_BDTR_BKF_SHIFT) /* 1100: fSAMPLING=fDTS/16, N=8 */ +# define GTIM_BDTR_BKF_FDTSd325 (13 << GTIM_BDTR_BKF_SHIFT) /* 1101: fSAMPLING=fDTS/32, N=5 */ +# define GTIM_BDTR_BKF_FDTSd326 (14 << GTIM_BDTR_BKF_SHIFT) /* 1110: fSAMPLING=fDTS/32, N=6 */ +# define GTIM_BDTR_BKF_FDTSd328 (15 << GTIM_BDTR_BKF_SHIFT) /* 1111: fSAMPLING=fDTS/32, N=8 */ + +#define GTIM_BDTR_BKDSRM (1 << 26) /* Bit 26: Break disarm */ +#define GTIM_BDTR_BKBID (1 << 28) /* Bit 28: Break bidirectional */ + +/* DMA control register (16-bit TIM3 and TIM15-17) */ + +#define GTIM_DCR_DBA_SHIFT (0) /* Bits 4-0: DMA Base Address */ +#define GTIM_DCR_DBA_MASK (0x1f << GTIM_DCR_DBA_SHIFT) +#define GTIM_DCR_DBL_SHIFT (8) /* Bits 12-8: DMA Burst Length */ +#define GTIM_DCR_DBL_MASK (0x1f << GTIM_DCR_DBL_SHIFT) + +/* Alternate function option register 1 (16-bit TIM15-17 or 32-bit TIM3) */ + +#define GTIM_AF1_BKINE (1 << 0) /* Bit 0: BRK BKIN input enable (TIM15-17 only) */ +#define GTIM_AF1_BKINP (1 << 9) /* Bit 9: BRK BKIN input polarity (TIM15-17 only) */ + +#define GTIM_AF1_ETRSEL_SHIFT (14) /* Bits 14-17: ETR source selection (TIM3 only) */ +#define GTIM_AF1_ETRSEL_MASK (0xf << GTIM_AF1_ETRSEL_SHIFT) +# define GTIM_AF1_ETRLEGACY (0 << GTIM_AF1_ETRSEL_SHIFT) /* 0000: ETR legacy mode */ + +/* Timer input selection register (16-bit TIM14-17 or 32-bit TIM3) */ + +#define GTIM_TISEL_TI1SEL_SHIFT (0) /* Bits 3-0: Selects TI1[0] to TI1[15] input */ +#define GTIM_TISEL_TI1SEL_MASK (0xf << GTIM_TISEL_TI1SEL_SHIFT) +#define GTIM_TISEL_TI2SEL_SHIFT (8) /* Bits 11-8: Selects TI2[0] to TI2[15] input (TIM3,15 only) */ +#define GTIM_TISEL_TI2SEL_MASK (0xf << GTIM_TISEL_TI2SEL_SHIFT) +#define GTIM_TISEL_TI3SEL_SHIFT (16) /* Bits 19-16: Selects TI3[0] to TI3[15] input (TIM3 only) */ +#define GTIM_TISEL_TI3SEL_MASK (0xf << GTIM_TISEL_TI3SEL_SHIFT) +#define GTIM_TISEL_TI4SEL_SHIFT (24) /* Bits 27-24: Selects TI4[0] to TI4[15] input (TIM3 only) */ +#define GTIM_TISEL_TI4SEL_MASK (0xf << GTIM_TISEL_TI4SEL_SHIFT) + +/* Control register 1 */ + +#define BTIM_CR1_CEN (1 << 0) /* Bit 0: Counter enable */ +#define BTIM_CR1_UDIS (1 << 1) /* Bit 1: Update Disable */ +#define BTIM_CR1_URS (1 << 2) /* Bit 2: Update Request Source */ +#define BTIM_CR1_OPM (1 << 3) /* Bit 3: One Pulse Mode */ +#define BTIM_CR1_ARPE (1 << 7) /* Bit 7: Auto-Reload Preload enable */ +#define BTIM_CR1_UIFREMAP (1 << 11) /* Bit 11: UIF status bit remapping */ + +/* Control register 2 */ + +#define BTIM_CR2_MMS_SHIFT (4) /* Bits 6-4: Master Mode Selection */ +#define BTIM_CR2_MMS_MASK (7 << BTIM_CR2_MMS_SHIFT) +# define BTIM_CR2_RESET (0 << BTIM_CR2_MMS_SHIFT) /* 000: Reset */ +# define BTIM_CR2_ENAB (1 << BTIM_CR2_MMS_SHIFT) /* 001: Enable */ +# define BTIM_CR2_UPDT (2 << BTIM_CR2_MMS_SHIFT) /* 010: Update */ + +/* DMA/Interrupt enable register */ + +#define BTIM_DIER_UIE (1 << 0) /* Bit 0: Update interrupt enable */ +#define BTIM_DIER_UDE (1 << 8) /* Bit 8: Update DMA request enable */ + +/* Status register */ + +#define BTIM_SR_UIF (1 << 0) /* Bit 0: Update interrupt flag */ + +/* Event generation register */ + +#define BTIM_EGR_UG (1 << 0) /* Bit 0: Update generation */ + +/* Counter register */ + +#define BTIM_CNT_UIFCPY (1 << 31) /* Bit 31: UIF copy */ + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_TIM_V3_M0_H */ diff --git a/arch/arm/src/common/stm32/hardware/stm32_uart.h b/arch/arm/src/common/stm32/hardware/stm32_uart.h new file mode 100644 index 0000000000000..471eb707aefbb --- /dev/null +++ b/arch/arm/src/common/stm32/hardware/stm32_uart.h @@ -0,0 +1,52 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/hardware/stm32_uart.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_UART_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_UART_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include "chip.h" + +#if (defined(CONFIG_STM32_HAVE_IP_USART_V1) + \ + defined(CONFIG_STM32_HAVE_IP_USART_V2) + \ + defined(CONFIG_STM32_HAVE_IP_USART_V3) + \ + defined(CONFIG_STM32_HAVE_IP_USART_V4)) > 1 +# error Only one STM32 USART IP version must be selected +#endif + +#if defined(CONFIG_STM32_HAVE_IP_USART_V1) +# include "hardware/stm32_uart_v1.h" +#elif defined(CONFIG_STM32_HAVE_IP_USART_V2) +# include "hardware/stm32_uart_v2.h" +#elif defined(CONFIG_STM32_HAVE_IP_USART_V3) +# include "hardware/stm32_uart_v3.h" +#elif defined(CONFIG_STM32_HAVE_IP_USART_V4) +# include "hardware/stm32_uart_v4.h" +#else +# error "Unsupported STM32 USART core" +#endif + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_UART_H */ diff --git a/arch/arm/src/common/stm32/hardware/stm32_uart_v1.h b/arch/arm/src/common/stm32/hardware/stm32_uart_v1.h new file mode 100644 index 0000000000000..3938a7f13fdf8 --- /dev/null +++ b/arch/arm/src/common/stm32/hardware/stm32_uart_v1.h @@ -0,0 +1,206 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/hardware/stm32_uart_v1.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_UART_V1_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_UART_V1_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "chip.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Register Offsets *********************************************************/ + +#define STM32_USART_SR_OFFSET 0x0000 /* Status register (32-bits) */ +#define STM32_USART_DR_OFFSET 0x0004 /* Data register (32-bits) */ +#define STM32_USART_BRR_OFFSET 0x0008 /* Baud Rate Register (32-bits) */ +#define STM32_USART_CR1_OFFSET 0x000c /* Control register 1 (32-bits) */ +#define STM32_USART_CR2_OFFSET 0x0010 /* Control register 2 (32-bits) */ +#define STM32_USART_CR3_OFFSET 0x0014 /* Control register 3 (32-bits) */ +#define STM32_USART_GTPR_OFFSET 0x0018 /* Guard time and prescaler register (32-bits) */ + +/* Register Addresses *******************************************************/ + +#if STM32_NUSART > 0 +# define STM32_USART1_SR (STM32_USART1_BASE+STM32_USART_SR_OFFSET) +# define STM32_USART1_DR (STM32_USART1_BASE+STM32_USART_DR_OFFSET) +# define STM32_USART1_BRR (STM32_USART1_BASE+STM32_USART_BRR_OFFSET) +# define STM32_USART1_CR1 (STM32_USART1_BASE+STM32_USART_CR1_OFFSET) +# define STM32_USART1_CR2 (STM32_USART1_BASE+STM32_USART_CR2_OFFSET) +# define STM32_USART1_CR3 (STM32_USART1_BASE+STM32_USART_CR3_OFFSET) +# define STM32_USART1_GTPR (STM32_USART1_BASE+STM32_USART_GTPR_OFFSET) +#endif + +#if STM32_NUSART > 1 +# define STM32_USART2_SR (STM32_USART2_BASE+STM32_USART_SR_OFFSET) +# define STM32_USART2_DR (STM32_USART2_BASE+STM32_USART_DR_OFFSET) +# define STM32_USART2_BRR (STM32_USART2_BASE+STM32_USART_BRR_OFFSET) +# define STM32_USART2_CR1 (STM32_USART2_BASE+STM32_USART_CR1_OFFSET) +# define STM32_USART2_CR2 (STM32_USART2_BASE+STM32_USART_CR2_OFFSET) +# define STM32_USART2_CR3 (STM32_USART2_BASE+STM32_USART_CR3_OFFSET) +# define STM32_USART2_GTPR (STM32_USART2_BASE+STM32_USART_GTPR_OFFSET) +#endif + +#if STM32_NUSART > 2 +# define STM32_USART3_SR (STM32_USART3_BASE+STM32_USART_SR_OFFSET) +# define STM32_USART3_DR (STM32_USART3_BASE+STM32_USART_DR_OFFSET) +# define STM32_USART3_BRR (STM32_USART3_BASE+STM32_USART_BRR_OFFSET) +# define STM32_USART3_CR1 (STM32_USART3_BASE+STM32_USART_CR1_OFFSET) +# define STM32_USART3_CR2 (STM32_USART3_BASE+STM32_USART_CR2_OFFSET) +# define STM32_USART3_CR3 (STM32_USART3_BASE+STM32_USART_CR3_OFFSET) +# define STM32_USART3_GTPR (STM32_USART3_BASE+STM32_USART_GTPR_OFFSET) +#endif + +#if STM32_NUSART > 3 +# define STM32_UART4_SR (STM32_UART4_BASE+STM32_USART_SR_OFFSET) +# define STM32_UART4_DR (STM32_UART4_BASE+STM32_USART_DR_OFFSET) +# define STM32_UART4_BRR (STM32_UART4_BASE+STM32_USART_BRR_OFFSET) +# define STM32_UART4_CR1 (STM32_UART4_BASE+STM32_USART_CR1_OFFSET) +# define STM32_UART4_CR2 (STM32_UART4_BASE+STM32_USART_CR2_OFFSET) +# define STM32_UART4_CR3 (STM32_UART4_BASE+STM32_USART_CR3_OFFSET) +#endif + +#if STM32_NUSART > 4 +# define STM32_UART5_SR (STM32_UART5_BASE+STM32_USART_SR_OFFSET) +# define STM32_UART5_DR (STM32_UART5_BASE+STM32_USART_DR_OFFSET) +# define STM32_UART5_BRR (STM32_UART5_BASE+STM32_USART_BRR_OFFSET) +# define STM32_UART5_CR1 (STM32_UART5_BASE+STM32_USART_CR1_OFFSET) +# define STM32_UART5_CR2 (STM32_UART5_BASE+STM32_USART_CR2_OFFSET) +# define STM32_UART5_CR3 (STM32_UART5_BASE+STM32_USART_CR3_OFFSET) +#endif + +/* Register Bitfield Definitions ********************************************/ + +/* Status register */ + +#define USART_SR_PE (1 << 0) /* Bit 0: Parity Error */ +#define USART_SR_FE (1 << 1) /* Bit 1: Framing Error */ +#define USART_SR_NE (1 << 2) /* Bit 2: Noise Error Flag */ +#define USART_SR_ORE (1 << 3) /* Bit 3: OverRun Error */ +#define USART_SR_IDLE (1 << 4) /* Bit 4: IDLE line detected */ +#define USART_SR_RXNE (1 << 5) /* Bit 5: Read Data Register Not Empty */ +#define USART_SR_TC (1 << 6) /* Bit 6: Transmission Complete */ +#define USART_SR_TXE (1 << 7) /* Bit 7: Transmit Data Register Empty */ +#define USART_SR_LBD (1 << 8) /* Bit 8: LIN Break Detection Flag */ +#define USART_SR_CTS (1 << 9) /* Bit 9: CTS Flag */ + +#define USART_SR_ALLBITS (0x03ff) +#define USART_SR_CLRBITS (USART_SR_CTS|USART_SR_LBD) /* Cleared by SW write to SR */ + +/* Data register */ + +#define USART_DR_SHIFT (0) /* Bits 8:0: Data value */ +#define USART_DR_MASK (0xff << USART_DR_SHIFT) + +/* Baud Rate Register */ + +#define USART_BRR_FRAC_SHIFT (0) /* Bits 3-0: fraction of USARTDIV */ +#define USART_BRR_FRAC_MASK (0x0f << USART_BRR_FRAC_SHIFT) +#define USART_BRR_MANT_SHIFT (4) /* Bits 15-4: mantissa of USARTDIV */ +#define USART_BRR_MANT_MASK (0x0fff << USART_BRR_MANT_SHIFT) + +/* Control register 1 */ + +#define USART_CR1_SBK (1 << 0) /* Bit 0: Send Break */ +#define USART_CR1_RWU (1 << 1) /* Bit 1: Receiver wakeup */ +#define USART_CR1_RE (1 << 2) /* Bit 2: Receiver Enable */ +#define USART_CR1_TE (1 << 3) /* Bit 3: Transmitter Enable */ +#define USART_CR1_IDLEIE (1 << 4) /* Bit 4: IDLE Interrupt Enable */ +#define USART_CR1_RXNEIE (1 << 5) /* Bit 5: RXNE Interrupt Enable */ +#define USART_CR1_TCIE (1 << 6) /* Bit 6: Transmission Complete Interrupt Enable */ +#define USART_CR1_TXEIE (1 << 7) /* Bit 7: TXE Interrupt Enable */ +#define USART_CR1_PEIE (1 << 8) /* Bit 8: PE Interrupt Enable */ +#define USART_CR1_PS (1 << 9) /* Bit 9: Parity Selection */ +#define USART_CR1_PCE (1 << 10) /* Bit 10: Parity Control Enable */ +#define USART_CR1_WAKE (1 << 11) /* Bit 11: Wakeup method */ +#define USART_CR1_M (1 << 12) /* Bit 12: word length */ +#define USART_CR1_UE (1 << 13) /* Bit 13: USART Enable */ + +#define USART_CR1_ALLINTS (USART_CR1_IDLEIE|USART_CR1_RXNEIE|USART_CR1_TCIE|USART_CR1_PEIE) + +/* Control register 2 */ + +#define USART_CR2_ADD_SHIFT (0) /* Bits 3-0: Address of the USART node */ +#define USART_CR2_ADD_MASK (0x0f << USART_CR2_ADD_SHIFT) +#define USART_CR2_LBDL (1 << 5) /* Bit 5: LIN Break Detection Length */ +#define USART_CR2_LBDIE (1 << 6) /* Bit 6: LIN Break Detection Interrupt Enable */ +#define USART_CR2_LBCL (1 << 8) /* Bit 8: Last Bit Clock pulse */ +#define USART_CR2_CPHA (1 << 9) /* Bit 9: Clock Phase */ +#define USART_CR2_CPOL (1 << 10) /* Bit 10: Clock Polarity */ +#define USART_CR2_CLKEN (1 << 11) /* Bit 11: Clock Enable */ +#define USART_CR2_STOP_SHIFT (12) /* Bits 13-12: STOP bits */ +#define USART_CR2_STOP_MASK (3 << USART_CR2_STOP_SHIFT) +# define USART_CR2_STOP1 (0 << USART_CR2_STOP_SHIFT) /* 00: 1 Stop bit */ +# define USART_CR2_STOP0p5 (1 << USART_CR2_STOP_SHIFT) /* 01: 0.5 Stop bit */ +# define USART_CR2_STOP2 (2 << USART_CR2_STOP_SHIFT) /* 10: 2 Stop bits */ +# define USART_CR2_STOP1p5 (3 << USART_CR2_STOP_SHIFT) /* 11: 1.5 Stop bit */ + +#define USART_CR2_LINEN (1 << 14) /* Bit 14: LIN mode enable */ + +/* Control register 3 */ + +#define USART_CR3_EIE (1 << 0) /* Bit 0: Error Interrupt Enable */ +#define USART_CR3_IREN (1 << 1) /* Bit 1: IrDA mode Enable */ +#define USART_CR3_IRLP (1 << 2) /* Bit 2: IrDA Low-Power */ +#define USART_CR3_HDSEL (1 << 3) /* Bit 3: Half-Duplex Selection */ +#define USART_CR3_NACK (1 << 4) /* Bit 4: Smartcard NACK enable */ +#define USART_CR3_SCEN (1 << 5) /* Bit 5: Smartcard mode enable */ +#define USART_CR3_DMAR (1 << 6) /* Bit 6: DMA Enable Receiver */ +#define USART_CR3_DMAT (1 << 7) /* Bit 7: DMA Enable Transmitter */ +#define USART_CR3_RTSE (1 << 8) /* Bit 8: RTS Enable */ +#define USART_CR3_CTSE (1 << 9) /* Bit 9: CTS Enable */ +#define USART_CR3_CTSIE (1 << 10) /* Bit 10: CTS Interrupt Enable */ + +/* Guard time and prescaler register */ + +#define USART_GTPR_PSC_SHIFT (0) /* Bits 0-7: Prescaler value */ +#define USART_GTPR_PSC_MASK (0xff << USART_GTPR_PSC_SHIFT) +#define USART_GTPR_GT_SHIFT (8) /* Bits 8-15: Guard time value */ +#define USART_GTPR_GT_MASK (0xff << USART_GTPR_GT_SHIFT) + +/* Compatibility definitions ************************************************/ + +/* F3 Transmit/Read registers */ + +#define STM32_USART_RDR_OFFSET STM32_USART_DR_OFFSET /* Receive data register */ +#define STM32_USART_TDR_OFFSET STM32_USART_DR_OFFSET /* Transmit data register */ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_UART_V1_H */ diff --git a/arch/arm/src/common/stm32/hardware/stm32_uart_v2.h b/arch/arm/src/common/stm32/hardware/stm32_uart_v2.h new file mode 100644 index 0000000000000..02f3811c221a8 --- /dev/null +++ b/arch/arm/src/common/stm32/hardware/stm32_uart_v2.h @@ -0,0 +1,236 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/hardware/stm32_uart_v2.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_UART_V2_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_UART_V2_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "chip.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Register Offsets *********************************************************/ + +#define STM32_USART_SR_OFFSET 0x0000 /* Status register (32-bits) */ +#define STM32_USART_DR_OFFSET 0x0004 /* Data register (32-bits) */ +#define STM32_USART_BRR_OFFSET 0x0008 /* Baud Rate Register (32-bits) */ +#define STM32_USART_CR1_OFFSET 0x000c /* Control register 1 (32-bits) */ +#define STM32_USART_CR2_OFFSET 0x0010 /* Control register 2 (32-bits) */ +#define STM32_USART_CR3_OFFSET 0x0014 /* Control register 3 (32-bits) */ +#define STM32_USART_GTPR_OFFSET 0x0018 /* Guard time and prescaler register (32-bits) */ + +/* Register Addresses *******************************************************/ + +#if STM32_NUSART > 0 +# define STM32_USART1_SR (STM32_USART1_BASE+STM32_USART_SR_OFFSET) +# define STM32_USART1_DR (STM32_USART1_BASE+STM32_USART_DR_OFFSET) +# define STM32_USART1_BRR (STM32_USART1_BASE+STM32_USART_BRR_OFFSET) +# define STM32_USART1_CR1 (STM32_USART1_BASE+STM32_USART_CR1_OFFSET) +# define STM32_USART1_CR2 (STM32_USART1_BASE+STM32_USART_CR2_OFFSET) +# define STM32_USART1_CR3 (STM32_USART1_BASE+STM32_USART_CR3_OFFSET) +# define STM32_USART1_GTPR (STM32_USART1_BASE+STM32_USART_GTPR_OFFSET) +#endif + +#if STM32_NUSART > 1 +# define STM32_USART2_SR (STM32_USART2_BASE+STM32_USART_SR_OFFSET) +# define STM32_USART2_DR (STM32_USART2_BASE+STM32_USART_DR_OFFSET) +# define STM32_USART2_BRR (STM32_USART2_BASE+STM32_USART_BRR_OFFSET) +# define STM32_USART2_CR1 (STM32_USART2_BASE+STM32_USART_CR1_OFFSET) +# define STM32_USART2_CR2 (STM32_USART2_BASE+STM32_USART_CR2_OFFSET) +# define STM32_USART2_CR3 (STM32_USART2_BASE+STM32_USART_CR3_OFFSET) +# define STM32_USART2_GTPR (STM32_USART2_BASE+STM32_USART_GTPR_OFFSET) +#endif + +#if STM32_NUSART > 2 +# define STM32_USART3_SR (STM32_USART3_BASE+STM32_USART_SR_OFFSET) +# define STM32_USART3_DR (STM32_USART3_BASE+STM32_USART_DR_OFFSET) +# define STM32_USART3_BRR (STM32_USART3_BASE+STM32_USART_BRR_OFFSET) +# define STM32_USART3_CR1 (STM32_USART3_BASE+STM32_USART_CR1_OFFSET) +# define STM32_USART3_CR2 (STM32_USART3_BASE+STM32_USART_CR2_OFFSET) +# define STM32_USART3_CR3 (STM32_USART3_BASE+STM32_USART_CR3_OFFSET) +# define STM32_USART3_GTPR (STM32_USART3_BASE+STM32_USART_GTPR_OFFSET) +#endif + +#if STM32_NUSART > 3 +# define STM32_UART4_SR (STM32_UART4_BASE+STM32_USART_SR_OFFSET) +# define STM32_UART4_DR (STM32_UART4_BASE+STM32_USART_DR_OFFSET) +# define STM32_UART4_BRR (STM32_UART4_BASE+STM32_USART_BRR_OFFSET) +# define STM32_UART4_CR1 (STM32_UART4_BASE+STM32_USART_CR1_OFFSET) +# define STM32_UART4_CR2 (STM32_UART4_BASE+STM32_USART_CR2_OFFSET) +# define STM32_UART4_CR3 (STM32_UART4_BASE+STM32_USART_CR3_OFFSET) +#endif + +#if STM32_NUSART > 4 +# define STM32_UART5_SR (STM32_UART5_BASE+STM32_USART_SR_OFFSET) +# define STM32_UART5_DR (STM32_UART5_BASE+STM32_USART_DR_OFFSET) +# define STM32_UART5_BRR (STM32_UART5_BASE+STM32_USART_BRR_OFFSET) +# define STM32_UART5_CR1 (STM32_UART5_BASE+STM32_USART_CR1_OFFSET) +# define STM32_UART5_CR2 (STM32_UART5_BASE+STM32_USART_CR2_OFFSET) +# define STM32_UART5_CR3 (STM32_UART5_BASE+STM32_USART_CR3_OFFSET) +#endif + +#if STM32_NUSART > 5 +# define STM32_USART6_SR (STM32_USART6_BASE+STM32_USART_SR_OFFSET) +# define STM32_USART6_DR (STM32_USART6_BASE+STM32_USART_DR_OFFSET) +# define STM32_USART6_BRR (STM32_USART6_BASE+STM32_USART_BRR_OFFSET) +# define STM32_USART6_CR1 (STM32_USART6_BASE+STM32_USART_CR1_OFFSET) +# define STM32_USART6_CR2 (STM32_USART6_BASE+STM32_USART_CR2_OFFSET) +# define STM32_USART6_CR3 (STM32_USART6_BASE+STM32_USART_CR3_OFFSET) +# define STM32_USART6_GTPR (STM32_USART6_BASE+STM32_USART_GTPR_OFFSET) +#endif + +#if STM32_NUSART > 6 +# define STM32_UART7_SR (STM32_UART7_BASE+STM32_USART_SR_OFFSET) +# define STM32_UART7_DR (STM32_UART7_BASE+STM32_USART_DR_OFFSET) +# define STM32_UART7_BRR (STM32_UART7_BASE+STM32_USART_BRR_OFFSET) +# define STM32_UART7_CR1 (STM32_UART7_BASE+STM32_USART_CR1_OFFSET) +# define STM32_UART7_CR2 (STM32_UART7_BASE+STM32_USART_CR2_OFFSET) +# define STM32_UART7_CR3 (STM32_UART7_BASE+STM32_USART_CR3_OFFSET) +#endif + +#if STM32_NUSART > 7 +# define STM32_UART8_SR (STM32_UART8_BASE+STM32_USART_SR_OFFSET) +# define STM32_UART8_DR (STM32_UART8_BASE+STM32_USART_DR_OFFSET) +# define STM32_UART8_BRR (STM32_UART8_BASE+STM32_USART_BRR_OFFSET) +# define STM32_UART8_CR1 (STM32_UART8_BASE+STM32_USART_CR1_OFFSET) +# define STM32_UART8_CR2 (STM32_UART8_BASE+STM32_USART_CR2_OFFSET) +# define STM32_UART8_CR3 (STM32_UART8_BASE+STM32_USART_CR3_OFFSET) +#endif + +/* Register Bitfield Definitions ********************************************/ + +/* Status register */ + +#define USART_SR_PE (1 << 0) /* Bit 0: Parity Error */ +#define USART_SR_FE (1 << 1) /* Bit 1: Framing Error */ +#define USART_SR_NE (1 << 2) /* Bit 2: Noise Error Flag */ +#define USART_SR_ORE (1 << 3) /* Bit 3: OverRun Error */ +#define USART_SR_IDLE (1 << 4) /* Bit 4: IDLE line detected */ +#define USART_SR_RXNE (1 << 5) /* Bit 5: Read Data Register Not Empty */ +#define USART_SR_TC (1 << 6) /* Bit 6: Transmission Complete */ +#define USART_SR_TXE (1 << 7) /* Bit 7: Transmit Data Register Empty */ +#define USART_SR_LBD (1 << 8) /* Bit 8: LIN Break Detection Flag */ +#define USART_SR_CTS (1 << 9) /* Bit 9: CTS Flag */ + +#define USART_SR_ALLBITS (0x03ff) +#define USART_SR_CLRBITS (USART_SR_CTS|USART_SR_LBD) /* Cleared by SW write to SR */ + +/* Data register */ + +#define USART_DR_SHIFT (0) /* Bits 8:0: Data value */ +#define USART_DR_MASK (0xff << USART_DR_SHIFT) + +/* Baud Rate Register */ + +#define USART_BRR_FRAC_SHIFT (0) /* Bits 3-0: fraction of USARTDIV */ +#define USART_BRR_FRAC_MASK (0x0f << USART_BRR_FRAC_SHIFT) +#define USART_BRR_MANT_SHIFT (4) /* Bits 15-4: mantissa of USARTDIV */ +#define USART_BRR_MANT_MASK (0x0fff << USART_BRR_MANT_SHIFT) + +/* Control register 1 */ + +#define USART_CR1_SBK (1 << 0) /* Bit 0: Send Break */ +#define USART_CR1_RWU (1 << 1) /* Bit 1: Receiver wakeup */ +#define USART_CR1_RE (1 << 2) /* Bit 2: Receiver Enable */ +#define USART_CR1_TE (1 << 3) /* Bit 3: Transmitter Enable */ +#define USART_CR1_IDLEIE (1 << 4) /* Bit 4: IDLE Interrupt Enable */ +#define USART_CR1_RXNEIE (1 << 5) /* Bit 5: RXNE Interrupt Enable */ +#define USART_CR1_TCIE (1 << 6) /* Bit 6: Transmission Complete Interrupt Enable */ +#define USART_CR1_TXEIE (1 << 7) /* Bit 7: TXE Interrupt Enable */ +#define USART_CR1_PEIE (1 << 8) /* Bit 8: PE Interrupt Enable */ +#define USART_CR1_PS (1 << 9) /* Bit 9: Parity Selection */ +#define USART_CR1_PCE (1 << 10) /* Bit 10: Parity Control Enable */ +#define USART_CR1_WAKE (1 << 11) /* Bit 11: Wakeup method */ +#define USART_CR1_M (1 << 12) /* Bit 12: word length */ +#define USART_CR1_UE (1 << 13) /* Bit 13: USART Enable */ +#define USART_CR1_OVER8 (1 << 15) /* Bit 15: Oversampling mode */ + +#define USART_CR1_ALLINTS (USART_CR1_IDLEIE|USART_CR1_RXNEIE|USART_CR1_TCIE|USART_CR1_PEIE) + +/* Control register 2 */ + +#define USART_CR2_ADD_SHIFT (0) /* Bits 3-0: Address of the USART node */ +#define USART_CR2_ADD_MASK (0x0f << USART_CR2_ADD_SHIFT) +#define USART_CR2_LBDL (1 << 5) /* Bit 5: LIN Break Detection Length */ +#define USART_CR2_LBDIE (1 << 6) /* Bit 6: LIN Break Detection Interrupt Enable */ +#define USART_CR2_LBCL (1 << 8) /* Bit 8: Last Bit Clock pulse */ +#define USART_CR2_CPHA (1 << 9) /* Bit 9: Clock Phase */ +#define USART_CR2_CPOL (1 << 10) /* Bit 10: Clock Polarity */ +#define USART_CR2_CLKEN (1 << 11) /* Bit 11: Clock Enable */ +#define USART_CR2_STOP_SHIFT (12) /* Bits 13-12: STOP bits */ +#define USART_CR2_STOP_MASK (3 << USART_CR2_STOP_SHIFT) +# define USART_CR2_STOP1 (0 << USART_CR2_STOP_SHIFT) /* 00: 1 Stop bit */ +# define USART_CR2_STOP0p5 (1 << USART_CR2_STOP_SHIFT) /* 01: 0.5 Stop bit */ +# define USART_CR2_STOP2 (2 << USART_CR2_STOP_SHIFT) /* 10: 2 Stop bits */ +# define USART_CR2_STOP1p5 (3 << USART_CR2_STOP_SHIFT) /* 11: 1.5 Stop bit */ + +#define USART_CR2_LINEN (1 << 14) /* Bit 14: LIN mode enable */ + +/* Control register 3 */ + +#define USART_CR3_EIE (1 << 0) /* Bit 0: Error Interrupt Enable */ +#define USART_CR3_IREN (1 << 1) /* Bit 1: IrDA mode Enable */ +#define USART_CR3_IRLP (1 << 2) /* Bit 2: IrDA Low-Power */ +#define USART_CR3_HDSEL (1 << 3) /* Bit 3: Half-Duplex Selection */ +#define USART_CR3_NACK (1 << 4) /* Bit 4: Smartcard NACK enable */ +#define USART_CR3_SCEN (1 << 5) /* Bit 5: Smartcard mode enable */ +#define USART_CR3_DMAR (1 << 6) /* Bit 6: DMA Enable Receiver */ +#define USART_CR3_DMAT (1 << 7) /* Bit 7: DMA Enable Transmitter */ +#define USART_CR3_RTSE (1 << 8) /* Bit 8: RTS Enable */ +#define USART_CR3_CTSE (1 << 9) /* Bit 9: CTS Enable */ +#define USART_CR3_CTSIE (1 << 10) /* Bit 10: CTS Interrupt Enable */ +#define USART_CR3_ONEBIT (1 << 11) /* Bit 11: One sample bit method enable */ + +/* Guard time and prescaler register */ + +#define USART_GTPR_PSC_SHIFT (0) /* Bits 0-7: Prescaler value */ +#define USART_GTPR_PSC_MASK (0xff << USART_GTPR_PSC_SHIFT) +#define USART_GTPR_GT_SHIFT (8) /* Bits 8-15: Guard time value */ +#define USART_GTPR_GT_MASK (0xff << USART_GTPR_GT_SHIFT) + +/* Compatibility definitions ************************************************/ + +/* F3 Transmit/Read registers */ + +#define STM32_USART_RDR_OFFSET STM32_USART_DR_OFFSET /* Receive data register */ +#define STM32_USART_TDR_OFFSET STM32_USART_DR_OFFSET /* Transmit data register */ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_UART_V2_H */ diff --git a/arch/arm/src/common/stm32/hardware/stm32_uart_v3.h b/arch/arm/src/common/stm32/hardware/stm32_uart_v3.h new file mode 100644 index 0000000000000..be5e3970c9268 --- /dev/null +++ b/arch/arm/src/common/stm32/hardware/stm32_uart_v3.h @@ -0,0 +1,331 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/hardware/stm32_uart_v3.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_UART_V3_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_UART_V3_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include "chip.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Register Offsets *********************************************************/ + +#define STM32_USART_CR1_OFFSET 0x0000 /* Control register 1 */ +#define STM32_USART_CR2_OFFSET 0x0004 /* Control register 2 */ +#define STM32_USART_CR3_OFFSET 0x0008 /* Control register 3 */ +#define STM32_USART_BRR_OFFSET 0x000c /* Baud Rate register */ +#define STM32_USART_GTPR_OFFSET 0x0010 /* Guard time and prescaler register */ +#define STM32_USART_RTOR_OFFSET 0x0014 /* Receiver timeout register */ +#define STM32_USART_RQR_OFFSET 0x0018 /* Request register */ +#define STM32_USART_ISR_OFFSET 0x001c /* Interrupot and status register */ +#define STM32_USART_ICR_OFFSET 0x0020 /* Interrupt flag clear register */ +#define STM32_USART_RDR_OFFSET 0x0024 /* Receive Data register */ +#define STM32_USART_TDR_OFFSET 0x0028 /* Transmit Data register */ + +/* Register Addresses *******************************************************/ + +#if STM32_NUSART > 0 +# define STM32_USART1_CR1 (STM32_USART1_BASE + STM32_USART_CR1_OFFSET) +# define STM32_USART1_CR2 (STM32_USART1_BASE + STM32_USART_CR2_OFFSET) +# define STM32_USART1_CR3 (STM32_USART1_BASE + STM32_USART_CR3_OFFSET) +# define STM32_USART1_BRR (STM32_USART1_BASE + STM32_USART_BRR_OFFSET) +# define STM32_USART1_GTPR (STM32_USART1_BASE + STM32_USART_GTPR_OFFSET) +# define STM32_USART1_RTOR (STM32_USART1_BASE + STM32_USART_RTOR_OFFSET) +# define STM32_USART1_RQR (STM32_USART1_BASE + STM32_USART_RQR_OFFSET) +# define STM32_USART1_ISR (STM32_USART1_BASE + STM32_USART_ISR_OFFSET) +# define STM32_USART1_ICR (STM32_USART1_BASE + STM32_USART_ICR_OFFSET) +# define STM32_USART1_RDR (STM32_USART1_BASE + STM32_USART_RDR_OFFSET) +# define STM32_USART1_TDR (STM32_USART1_BASE + STM32_USART_TDR_OFFSET) +#endif + +#if STM32_NUSART > 1 +# define STM32_USART2_CR1 (STM32_USART2_BASE + STM32_USART_CR1_OFFSET) +# define STM32_USART2_CR2 (STM32_USART2_BASE + STM32_USART_CR2_OFFSET) +# define STM32_USART2_CR3 (STM32_USART2_BASE + STM32_USART_CR3_OFFSET) +# define STM32_USART2_BRR (STM32_USART2_BASE + STM32_USART_BRR_OFFSET) +# define STM32_USART2_GTPR (STM32_USART2_BASE + STM32_USART_GTPR_OFFSET) +# define STM32_USART2_RTOR (STM32_USART2_BASE + STM32_USART_RTOR_OFFSET) +# define STM32_USART2_RQR (STM32_USART2_BASE + STM32_USART_RQR_OFFSET) +# define STM32_USART2_ISR (STM32_USART2_BASE + STM32_USART_ISR_OFFSET) +# define STM32_USART2_ICR (STM32_USART2_BASE + STM32_USART_ICR_OFFSET) +# define STM32_USART2_RDR (STM32_USART2_BASE + STM32_USART_RDR_OFFSET) +# define STM32_USART2_TDR (STM32_USART2_BASE + STM32_USART_TDR_OFFSET) +#endif + +#if STM32_NUSART > 2 +# define STM32_USART3_CR1 (STM32_USART3_BASE + STM32_USART_CR1_OFFSET) +# define STM32_USART3_CR2 (STM32_USART3_BASE + STM32_USART_CR2_OFFSET) +# define STM32_USART3_CR3 (STM32_USART3_BASE + STM32_USART_CR3_OFFSET) +# define STM32_USART3_BRR (STM32_USART3_BASE + STM32_USART_BRR_OFFSET) +# define STM32_USART3_GTPR (STM32_USART3_BASE + STM32_USART_GTPR_OFFSET) +# define STM32_USART3_RTOR (STM32_USART3_BASE + STM32_USART_RTOR_OFFSET) +# define STM32_USART3_RQR (STM32_USART3_BASE + STM32_USART_RQR_OFFSET) +# define STM32_USART3_ISR (STM32_USART3_BASE + STM32_USART_ISR_OFFSET) +# define STM32_USART3_ICR (STM32_USART3_BASE + STM32_USART_ICR_OFFSET) +# define STM32_USART3_RDR (STM32_USART3_BASE + STM32_USART_RDR_OFFSET) +# define STM32_USART3_TDR (STM32_USART3_BASE + STM32_USART_TDR_OFFSET) +#endif + +#if STM32_NUSART > 3 +# define STM32_USART4_CR1 (STM32_USART4_BASE + STM32_USART_CR1_OFFSET) +# define STM32_USART4_CR2 (STM32_USART4_BASE + STM32_USART_CR2_OFFSET) +# define STM32_USART4_CR3 (STM32_USART4_BASE + STM32_USART_CR3_OFFSET) +# define STM32_USART4_BRR (STM32_USART4_BASE + STM32_USART_BRR_OFFSET) +# define STM32_USART4_GTPR (STM32_USART4_BASE + STM32_USART_GTPR_OFFSET) +# define STM32_USART4_RTOR (STM32_USART4_BASE + STM32_USART_RTOR_OFFSET) +# define STM32_USART4_RQR (STM32_USART4_BASE + STM32_USART_RQR_OFFSET) +# define STM32_USART4_ISR (STM32_USART4_BASE + STM32_USART_ISR_OFFSET) +# define STM32_USART4_ICR (STM32_USART4_BASE + STM32_USART_ICR_OFFSET) +# define STM32_USART4_RDR (STM32_USART4_BASE + STM32_USART_RDR_OFFSET) +# define STM32_USART4_TDR (STM32_USART4_BASE + STM32_USART_TDR_OFFSET) +#endif + +#if STM32_NUSART > 4 +# define STM32_USART5_CR1 (STM32_USART5_BASE + STM32_USART_CR1_OFFSET) +# define STM32_USART5_CR2 (STM32_USART5_BASE + STM32_USART_CR2_OFFSET) +# define STM32_USART5_CR3 (STM32_USART5_BASE + STM32_USART_CR3_OFFSET) +# define STM32_USART5_BRR (STM32_USART5_BASE + STM32_USART_BRR_OFFSET) +# define STM32_USART5_GTPR (STM32_USART5_BASE + STM32_USART_GTPR_OFFSET) +# define STM32_USART5_RTOR (STM32_USART5_BASE + STM32_USART_RTOR_OFFSET) +# define STM32_USART5_RQR (STM32_USART5_BASE + STM32_USART_RQR_OFFSET) +# define STM32_USART5_ISR (STM32_USART5_BASE + STM32_USART_ISR_OFFSET) +# define STM32_USART5_ICR (STM32_USART5_BASE + STM32_USART_ICR_OFFSET) +# define STM32_USART5_RDR (STM32_USART5_BASE + STM32_USART_RDR_OFFSET) +# define STM32_USART5_TDR (STM32_USART5_BASE + STM32_USART_TDR_OFFSET) +#endif + +/* Register Bitfield Definitions ********************************************/ + +/* Control register 1 */ + +#define USART_CR1_UE (1 << 0) /* Bit 0: USART Enable */ +#define USART_CR1_UESM (1 << 1) /* Bit 1: USART Enable in Stop mode*/ +#define USART_CR1_RE (1 << 2) /* Bit 2: Receiver Enable */ +#define USART_CR1_TE (1 << 3) /* Bit 3: Transmitter Enable */ +#define USART_CR1_IDLEIE (1 << 4) /* Bit 4: IDLE Interrupt Enable */ +#define USART_CR1_RXNEIE (1 << 5) /* Bit 5: RXNE Interrupt Enable */ +#define USART_CR1_TCIE (1 << 6) /* Bit 6: Transmission Complete Interrupt Enable */ +#define USART_CR1_TXEIE (1 << 7) /* Bit 7: TXE Interrupt Enable */ +#define USART_CR1_PEIE (1 << 8) /* Bit 8: PE Interrupt Enable */ +#define USART_CR1_PS (1 << 9) /* Bit 9: Parity Selection */ +#define USART_CR1_PCE (1 << 10) /* Bit 10: Parity Control Enable */ +#define USART_CR1_WAKE (1 << 11) /* Bit 11: Wakeup method */ +#define USART_CR1_M0 (1 << 12) /* Bit 12: Word length */ +#define USART_CR1_MME (1 << 13) /* Bit 13: Mute mode enable */ +#define USART_CR1_CMIE (1 << 14) /* Bit 14: Character match interrupt enable */ +#define USART_CR1_OVER8 (1 << 15) /* Bit 15: Oversampling mode */ + +#define USART_CR1_DEDT_SHIFT (16) /* Bits 16..20 DE deactivation delay */ +#define USART_CR1_DEDT_MASK (0x1f << USART_CR1_DEDT_SHIFT) + +#define USART_CR1_DEAT_SHIFT (21) /* Bits 21..25 DE activation delay */ +#define USART_CR1_DEAT_MASK (0x1f << USART_CR1_DEAT_SHIFT) + +#define USART_CR1_RTOIE (1 << 26) /* Bit 26: Receiver timeout interrupt enable */ +#define USART_CR1_EOBIE (1 << 27) /* Bit 27: End of block interrupt enable */ +#define USART_CR1_M1 (1 << 28) /* Bit 12: word length */ + +#define USART_CR1_ALLINTS (USART_CR1_IDLEIE | USART_CR1_RXNEIE | \ + USART_CR1_TCIE | USART_CR1_TXEIE | \ + USART_CR1_PEIE | USART_CR1_CMIE| \ + USART_CR1_RTOIE | USART_CR1_EOBIE) + +/* Control register 2 */ + +#define USART_CR2_ADDM7 (1 << 4) /* Bit 4: */ +#define USART_CR2_LBDL (1 << 5) /* Bit 5: LIN Break Detection Length */ +#define USART_CR2_LBDIE (1 << 6) /* Bit 6: LIN Break Detection Interrupt Enable */ +#define USART_CR2_LBCL (1 << 8) /* Bit 8: Last Bit Clock pulse */ +#define USART_CR2_CPHA (1 << 9) /* Bit 9: Clock Phase */ +#define USART_CR2_CPOL (1 << 10) /* Bit 10: Clock Polarity */ +#define USART_CR2_CLKEN (1 << 11) /* Bit 11: Clock Enable */ + +#define USART_CR2_STOP_SHIFT (12) /* Bits 13-12: STOP bits */ +#define USART_CR2_STOP_MASK (3 << USART_CR2_STOP_SHIFT) +# define USART_CR2_STOP1 (0 << USART_CR2_STOP_SHIFT) /* 00: 1 Stop bit */ +# define USART_CR2_STOP0p5 (1 << USART_CR2_STOP_SHIFT) /* 01: 0.5 Stop bit */ +# define USART_CR2_STOP2 (2 << USART_CR2_STOP_SHIFT) /* 10: 2 Stop bits */ +# define USART_CR2_STOP1p5 (3 << USART_CR2_STOP_SHIFT) /* 11: 1.5 Stop bit */ + +#define USART_CR2_LINEN (1 << 14) /* Bit 14: LIN mode enable */ +#define USART_CR2_SWAP (1 << 15) /* Bit 15: Swap TX/RX pins */ +#define USART_CR2_RXINV (1 << 16) /* Bit 16: RX pin active level inversion */ +#define USART_CR2_TXINV (1 << 17) /* Bit 17: TX pin active level inversion */ +#define USART_CR2_DATAINV (1 << 18) /* Bit 18: Binary data inversion */ +#define USART_CR2_MSBFIRST (1 << 19) /* Bit 19: Most significant bit first */ +#define USART_CR2_ABREN (1 << 20) /* Bit 20: Auto Baud rate enable */ + +#define USART_CR2_ABRMOD_SHIFT (21) /* Bits 21-22: Autobaud rate mode*/ +#define USART_CR2_ABRMOD_MASK (3 << USART_CR2_ABRMOD_SHIFT) +#define USART_CR2_ABRMOD_START (0 << USART_CR2_ABRMOD_SHIFT) /* 00: Start bit */ +#define USART_CR2_ABRMOD_EDGES (1 << USART_CR2_ABRMOD_SHIFT) /* 01: Falling-to-falling edge -> frame must start with 10xxxxxx */ +#define USART_CR2_ABRMOD_7F (2 << USART_CR2_ABRMOD_SHIFT) /* 10: 0x7F */ +#define USART_CR2_ABRMOD_55 (3 << USART_CR2_ABRMOD_SHIFT) /* 11: 0x55 */ + +#define USART_CR2_RTOEN (1 << 23) /* Bit 23: Receiver timeout enable */ + +#define USART_CR2_ADD_SHIFT (24) /* Bits 24-31: Address of the USART node */ +#define USART_CR2_ADD_MASK (0xff << USART_CR2_ADD_SHIFT) +#define USART_CR2_ADD8_SHIFT USART_CR2_ADD_SHIFT /* F1/F2/F4-compatible name */ +#define USART_CR2_ADD8_MASK USART_CR2_ADD_MASK + +/* Control register 3 */ + +#define USART_CR3_EIE (1 << 0) /* Bit 0: Error Interrupt Enable */ +#define USART_CR3_IREN (1 << 1) /* Bit 1: IrDA mode Enable */ +#define USART_CR3_IRLP (1 << 2) /* Bit 2: IrDA Low-Power */ +#define USART_CR3_HDSEL (1 << 3) /* Bit 3: Half-Duplex Selection */ +#define USART_CR3_NACK (1 << 4) /* Bit 4: Smartcard NACK enable */ +#define USART_CR3_SCEN (1 << 5) /* Bit 5: Smartcard mode enable */ +#define USART_CR3_DMAR (1 << 6) /* Bit 6: DMA Enable Receiver */ +#define USART_CR3_DMAT (1 << 7) /* Bit 7: DMA Enable Transmitter */ +#define USART_CR3_RTSE (1 << 8) /* Bit 8: RTS Enable */ +#define USART_CR3_CTSE (1 << 9) /* Bit 9: CTS Enable */ +#define USART_CR3_CTSIE (1 << 10) /* Bit 10: CTS Interrupt Enable */ +#define USART_CR3_ONEBIT (1 << 11) /* Bit 11: One sample bit method Enable */ +#define USART_CR3_OVRDIS (1 << 12) /* Bit 12: Overrun Disable */ +#define USART_CR3_DDRE (1 << 13) /* Bit 13: DMA disable on Reception error */ +#define USART_CR3_DEM (1 << 14) /* Bit 14: Driver Enable mode */ +#define USART_CR3_DEP (1 << 15) /* Bit 15: Driver Enable polarity selection */ +#define USART_CR3_SCARCNT_SHIFT (17) /* Bits 17-19: Smart card auto retry count */ +#define USART_CR3_SCARCNT_MASK (7 << USART_CR3_SCARCNT_SHIFT) +#define USART_CR3_WUS_SHIFT (20) /* Bits 20-21: Wakeup from Stop mode interrupt flag selection */ +#define USART_CR3_WUS_MASK (3 << USART_CR3_WUS_SHIFT) +#define USART_CR3_WUS_ADDRESS (0 << USART_CR3_WUS_SHIFT) /* 00: WUF active on address match */ +#define USART_CR3_WUS_START (2 << USART_CR3_WUS_SHIFT) /* 10: WUF active on Start bit detection */ +#define USART_CR3_WUS_RXNE (3 << USART_CR3_WUS_SHIFT) /* 11: WUF active on RXNE */ + +#define USART_CR3_WUFIE (1 << 22) /* Bit 22: Wakeup from Stop mode interrupt enable */ + +/* Baud Rate Register */ + +#define USART_BRR_FRAC_SHIFT (0) /* Bits 3-0: fraction of USARTDIV */ +#define USART_BRR_FRAC_MASK (0x0f << USART_BRR_FRAC_SHIFT) +#define USART_BRR_MANT_SHIFT (4) /* Bits 15-4: mantissa of USARTDIV */ +#define USART_BRR_MANT_MASK (0x0fff << USART_BRR_MANT_SHIFT) + +/* Guard time and prescaler register */ + +#define USART_GTPR_PSC_SHIFT (0) /* Bits 0-7: Prescaler value */ +#define USART_GTPR_PSC_MASK (0xff << USART_GTPR_PSC_SHIFT) +#define USART_GTPR_GT_SHIFT (8) /* Bits 8-15: Guard time value */ +#define USART_GTPR_GT_MASK (0xff << USART_GTPR_GT_SHIFT) + +/* Receiver timeout register */ + +#define USART_RTOR_RTO_SHIFT (0) /* Bits 0-23: Receiver timeout value */ +#define USART_RTOR_RTO_MASK (0xffffff << USART_RTOR_RTO_SHIFT) +#define USART_RTOR_BLEN_SHIFT (24) /* Bits 24-31: Block length */ +#define USART_RTOR_BLEN_MASK (0xff << USART_RTOR_BLEN_SHIFT) + +/* Request Register */ + +#define USART_RQR_ABRRQ (1 << 0) /* Bit 0: Auto baud rate request */ +#define USART_RQR_SBKRQ (1 << 1) /* Bit 1: Send Break */ +#define USART_RQR_MMRQ (1 << 2) /* Bit 2: Mute mode request */ +#define USART_RQR_RXFRQ (1 << 3) /* Bit 3: Receive data flush request */ +#define USART_RQR_TXFRQ (1 << 4) /* Bit 4: Transmit data flush request */ + +/* Interrupt and Status register */ + +#define USART_ISR_PE (1 << 0) /* Bit 0: Parity Error */ +#define USART_ISR_FE (1 << 1) /* Bit 1: Framing Error */ +#define USART_ISR_NF (1 << 2) /* Bit 2: Noise Error Flag */ +#define USART_ISR_ORE (1 << 3) /* Bit 3: OverRun Error */ +#define USART_ISR_IDLE (1 << 4) /* Bit 4: IDLE line detected */ +#define USART_ISR_RXNE (1 << 5) /* Bit 5: Read Data Register Not Empty */ +#define USART_ISR_TC (1 << 6) /* Bit 6: Transmission Complete */ +#define USART_ISR_TXE (1 << 7) /* Bit 7: Transmit Data Register Empty */ +#define USART_ISR_LBDF (1 << 8) /* Bit 8: LIN Break Detection Flag */ +#define USART_ISR_CTSIF (1 << 9) /* Bit 9: CTS Interrupt flag */ +#define USART_ISR_CTS (1 << 10) /* Bit 9: CTS Flag */ +#define USART_ISR_RTOF (1 << 11) /* Bit 10: Receiver timeout Flag */ +#define USART_ISR_EOBF (1 << 12) /* Bit 11: End of block Flag */ +#define USART_ISR_ABRE (1 << 13) /* Bit 12: Auto baud rate Error */ +#define USART_ISR_ABRF (1 << 15) /* Bit 14: Auto baud rate Flag */ +#define USART_ISR_BUSY (1 << 16) /* Bit 15: Busy Flag */ +#define USART_ISR_CMF (1 << 17) /* Bit 16: Character match Flag */ +#define USART_ISR_SBKF (1 << 18) /* Bit 17: Send break Flag */ +#define USART_ISR_RWU (1 << 19) /* Bit 18: Receiver wakeup from Mute mode */ +#define USART_ISR_WUF (1 << 20) /* Bit 19: Wakeup from Stop mode Flag */ +#define USART_ISR_TEACK (1 << 21) /* Bit 20: Transmit enable acknowledge Flag */ +#define USART_ISR_REACK (1 << 22) /* Bit 21: Receive enable acknowledge Flag */ + +#define USART_ISR_ALLBITS (0x007fdfff) + +/* ICR */ + +#define USART_ICR_PECF (1 << 0) /* Bit 0: Parity error clear flag */ +#define USART_ICR_FECF (1 << 1) /* Bit 1: Framing error clear flag */ +#define USART_ICR_NCF (1 << 2) /* Bit 2: Noise detected clear flag */ +#define USART_ICR_ORECF (1 << 3) /* Bit 3: Overrun error clear flag */ +#define USART_ICR_IDLECF (1 << 4) /* Bit 4: Idle line detected clear flag */ +#define USART_ICR_TCCF (1 << 6) /* Bit 6: Transmission complete clear flag */ +#define USART_ICR_LBDCF (1 << 8) /* Bit 8: LIN break detection clear flag */ +#define USART_ICR_CTSCF (1 << 9) /* Bit 9: CTS clear flag */ +#define USART_ICR_RTOCF (1 << 11) /* Bit 11: Receiver timeout clear flag */ +#define USART_ICR_EOBCF (1 << 12) /* Bit 12: End of block clear flag */ +#define USART_ICR_CMCF (1 << 17) /* Bit 17: Character match clear flag */ +#define USART_ICR_WUCF (1 << 20) /* Bit 20: Wakeup from Stop mode clear flag */ + +/* Receive Data register */ + +#define USART_RDR_SHIFT (0) /* Bits 8:0: Data value */ +#define USART_RDR_MASK (0xff << USART_RDR_SHIFT) + +/* Transmit Data register */ + +#define USART_TDR_SHIFT (0) /* Bits 8:0: Data value */ +#define USART_TDR_MASK (0xff << USART_TDR_SHIFT) + +/* Compatibility definitions ************************************************/ + +/* Compatibility with F1/F2/F4 Status Register names. This USART IP replaces + * the SR register with separate ISR/ICR registers; alias the legacy SR names + * so the shared M3/M4 serial driver keeps working on these parts. + */ + +#define STM32_USART_SR_OFFSET STM32_USART_ISR_OFFSET + +#define USART_SR_PE USART_ISR_PE /* Parity Error */ +#define USART_SR_FE USART_ISR_FE /* Framing error */ +#define USART_SR_NE USART_ISR_NF /* Noise detected flag */ +#define USART_SR_ORE USART_ISR_ORE /* Overrun error */ +#define USART_SR_IDLE USART_ISR_IDLE /* IDLE line detected */ +#define USART_SR_RXNE USART_ISR_RXNE /* Read Data Register Not Empty */ +#define USART_SR_TC USART_ISR_TC /* Transmission Complete */ +#define USART_SR_TXE USART_ISR_TXE /* Transmit Data Register Empty */ +#define USART_SR_LBD USART_ISR_LBDF /* LIN Break Detection Flag */ +#define USART_SR_CTS USART_ISR_CTS /* CTS Flag */ + +#define USART_SR_ALLBITS USART_ISR_ALLBITS + +#define USART_CR1_M USART_CR1_M0 + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_UART_V3_H */ diff --git a/arch/arm/src/common/stm32/hardware/stm32_uart_v4.h b/arch/arm/src/common/stm32/hardware/stm32_uart_v4.h new file mode 100644 index 0000000000000..8f8f0900c9334 --- /dev/null +++ b/arch/arm/src/common/stm32/hardware/stm32_uart_v4.h @@ -0,0 +1,390 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/hardware/stm32_uart_v4.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_UART_V4_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_UART_V4_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include "chip.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Register Offsets *********************************************************/ + +#define STM32_USART_CR1_OFFSET 0x0000 /* Control register 1 */ +#define STM32_USART_CR2_OFFSET 0x0004 /* Control register 2 */ +#define STM32_USART_CR3_OFFSET 0x0008 /* Control register 3 */ +#define STM32_USART_BRR_OFFSET 0x000c /* Baud Rate Register (32-bits) */ +#define STM32_USART_GTPR_OFFSET 0x0010 /* Guard time and prescaler register */ +#define STM32_USART_RTOR_OFFSET 0x0014 /* Receiver timeout register */ +#define STM32_USART_RQR_OFFSET 0x0018 /* Request register */ +#define STM32_USART_ISR_OFFSET 0x001c /* Interrupt & status register */ +#define STM32_USART_ICR_OFFSET 0x0020 /* Interrupt flag clear register */ +#define STM32_USART_RDR_OFFSET 0x0024 /* Receive data register */ +#define STM32_USART_TDR_OFFSET 0x0028 /* Transmit data register */ +#define STM32_USART_PRESC_OFFSET 0x002c /* Prescaler register */ + +/* Register Addresses *******************************************************/ + +#if STM32_NUSART > 0 +# define STM32_USART1_CR1 (STM32_USART1_BASE + STM32_USART_CR1_OFFSET) +# define STM32_USART1_CR2 (STM32_USART1_BASE + STM32_USART_CR2_OFFSET) +# define STM32_USART1_CR3 (STM32_USART1_BASE + STM32_USART_CR3_OFFSET) +# define STM32_USART1_BRR (STM32_USART1_BASE + STM32_USART_BRR_OFFSET) +# define STM32_USART1_GTPR (STM32_USART1_BASE + STM32_USART_GTPR_OFFSET) +# define STM32_USART1_RTOR (STM32_USART1_BASE + STM32_USART_RTOR_OFFSET) +# define STM32_USART1_RQR (STM32_USART1_BASE + STM32_USART_RQR_OFFSET) +# define STM32_USART1_GTPR (STM32_USART1_BASE + STM32_USART_GTPR_OFFSET) +# define STM32_USART1_ISR (STM32_USART1_BASE + STM32_USART_ISR_OFFSET) +# define STM32_USART1_ICR (STM32_USART1_BASE + STM32_USART_ICR_OFFSET) +# define STM32_USART1_RDR (STM32_USART1_BASE + STM32_USART_RDR_OFFSET) +# define STM32_USART1_TDR (STM32_USART1_BASE + STM32_USART_TDR_OFFSET) +# define STM32_USART1_PRESC (STM32_USART1_BASE + STM32_USART_PRESC_OFFSET) +#endif + +#if STM32_NUSART > 1 +# define STM32_USART2_CR1 (STM32_USART2_BASE + STM32_USART_CR1_OFFSET) +# define STM32_USART2_CR2 (STM32_USART2_BASE + STM32_USART_CR2_OFFSET) +# define STM32_USART2_CR3 (STM32_USART2_BASE + STM32_USART_CR3_OFFSET) +# define STM32_USART2_BRR (STM32_USART2_BASE + STM32_USART_BRR_OFFSET) +# define STM32_USART2_GTPR (STM32_USART2_BASE + STM32_USART_GTPR_OFFSET) +# define STM32_USART2_RTOR (STM32_USART2_BASE + STM32_USART_RTOR_OFFSET) +# define STM32_USART2_RQR (STM32_USART2_BASE + STM32_USART_RQR_OFFSET) +# define STM32_USART2_GTPR (STM32_USART2_BASE + STM32_USART_GTPR_OFFSET) +# define STM32_USART2_ISR (STM32_USART2_BASE + STM32_USART_ISR_OFFSET) +# define STM32_USART2_ICR (STM32_USART2_BASE + STM32_USART_ICR_OFFSET) +# define STM32_USART2_RDR (STM32_USART2_BASE + STM32_USART_RDR_OFFSET) +# define STM32_USART2_TDR (STM32_USART2_BASE + STM32_USART_TDR_OFFSET) +# define STM32_USART2_PRESC (STM32_USART2_BASE + STM32_USART_PRESC_OFFSET) +#endif + +#if STM32_NUSART > 2 +# define STM32_USART3_CR1 (STM32_USART3_BASE + STM32_USART_CR1_OFFSET) +# define STM32_USART3_CR2 (STM32_USART3_BASE + STM32_USART_CR2_OFFSET) +# define STM32_USART3_CR3 (STM32_USART3_BASE + STM32_USART_CR3_OFFSET) +# define STM32_USART3_BRR (STM32_USART3_BASE + STM32_USART_BRR_OFFSET) +# define STM32_USART3_GTPR (STM32_USART3_BASE + STM32_USART_GTPR_OFFSET) +# define STM32_USART3_RTOR (STM32_USART3_BASE + STM32_USART_RTOR_OFFSET) +# define STM32_USART3_RQR (STM32_USART3_BASE + STM32_USART_RQR_OFFSET) +# define STM32_USART3_GTPR (STM32_USART3_BASE + STM32_USART_GTPR_OFFSET) +# define STM32_USART3_ISR (STM32_USART3_BASE + STM32_USART_ISR_OFFSET) +# define STM32_USART3_ICR (STM32_USART3_BASE + STM32_USART_ICR_OFFSET) +# define STM32_USART3_RDR (STM32_USART3_BASE + STM32_USART_RDR_OFFSET) +# define STM32_USART3_TDR (STM32_USART3_BASE + STM32_USART_TDR_OFFSET) +# define STM32_USART3_PRESC (STM32_USART3_BASE + STM32_USART_PRESC_OFFSET) +#endif + +#if STM32_NUSART > 3 +# define STM32_USART4_CR1 (STM32_USART4_BASE + STM32_USART_CR1_OFFSET) +# define STM32_USART4_CR2 (STM32_USART4_BASE + STM32_USART_CR2_OFFSET) +# define STM32_USART4_CR3 (STM32_USART4_BASE + STM32_USART_CR3_OFFSET) +# define STM32_USART4_BRR (STM32_USART4_BASE + STM32_USART_BRR_OFFSET) +# define STM32_USART4_GTPR (STM32_USART4_BASE + STM32_USART_GTPR_OFFSET) +# define STM32_USART4_RTOR (STM32_USART4_BASE + STM32_USART_RTOR_OFFSET) +# define STM32_USART4_RQR (STM32_USART4_BASE + STM32_USART_RQR_OFFSET) +# define STM32_USART4_GTPR (STM32_USART4_BASE + STM32_USART_GTPR_OFFSET) +# define STM32_USART4_ISR (STM32_USART4_BASE + STM32_USART_ISR_OFFSET) +# define STM32_USART4_ICR (STM32_USART4_BASE + STM32_USART_ICR_OFFSET) +# define STM32_USART4_RDR (STM32_USART4_BASE + STM32_USART_RDR_OFFSET) +# define STM32_USART4_TDR (STM32_USART4_BASE + STM32_USART_TDR_OFFSET) +# define STM32_USART4_PRESC (STM32_USART4_BASE + STM32_USART_PRESC_OFFSET) +#endif + +/* Register Bitfield Definitions ********************************************/ + +/* Control register 1 */ + +#define USART_CR1_UE (1 << 0) /* Bit 0: USART enable */ +#define USART_CR1_UESM (1 << 1) /* Bit 1: USART enable in low-power mode */ +#define USART_CR1_RE (1 << 2) /* Bit 2: Receiver Enable */ +#define USART_CR1_TE (1 << 3) /* Bit 3: Transmitter Enable */ +#define USART_CR1_IDLEIE (1 << 4) /* Bit 4: IDLE Interrupt Enable */ +#define USART_CR1_RXNEIE (1 << 5) /* Bit 5: RXNE Interrupt Enable */ +#define USART_CR1_TCIE (1 << 6) /* Bit 6: Transmission Complete Interrupt Enable */ +#define USART_CR1_TXEIE (1 << 7) /* Bit 7: TXE Interrupt Enable */ +#define USART_CR1_PEIE (1 << 8) /* Bit 8: PE Interrupt Enable */ +#define USART_CR1_PS (1 << 9) /* Bit 9: Parity Selection */ +#define USART_CR1_PCE (1 << 10) /* Bit 10: Parity Control Enable */ +#define USART_CR1_WAKE (1 << 11) /* Bit 11: Receiver wakeup method */ +#define USART_CR1_M0 (1 << 12) /* Bit 12: Word length, bit 0 */ +#define USART_CR1_MME (1 << 13) /* Bit 13: Mute mode enable */ +#define USART_CR1_CMIE (1 << 14) /* Bit 14: Character match interrupt enable */ +#define USART_CR1_OVER8 (1 << 15) /* Bit 15: Oversampling mode */ +#define USART_CR1_DEDT_SHIFT (16) /* Bits 16-20: Driver Enable deassertion time */ +#define USART_CR1_DEDT_MASK (31 << USART_CR1_DEDT_SHIFT) +# define USART_CR1_DEDT(n) ((uint32_t)(n) << USART_CR1_DEDT_SHIFT) +#define USART_CR1_DEAT_SHIFT (21) /* Bits 21-25: Driver Enable assertion time */ +#define USART_CR1_DEAT_MASK (31 << USART_CR1_DEAT_SHIFT) +# define USART_CR1_DEAT(n) ((uint32_t)(n) << USART_CR1_DEAT_SHIFT) +#define USART_CR1_RTOIE (1 << 26) /* Bit 26: Receiver timeout interrupt enable */ +#define USART_CR1_EOBIE (1 << 27) /* Bit 27: End of Block interrupt enable */ +#define USART_CR1_M1 (1 << 28) /* Bit 28: Word length, bit 1 */ +#define USART_CR1_FIFOEN (1 << 29) /* Bit 29: FIFO mode enable */ +#define USART_CR1_TXFEIE (1 << 30) /* Bit 30: TXFIFO empty interrupt enable */ +#define USART_CR1_RXFFIE (1 << 31) /* Bit 31: RXFIFO Full interrupt enable */ + +#define USART_CR1_ALLINTS \ + (USART_CR1_IDLEIE | USART_CR1_RXNEIE | USART_CR1_TCIE | USART_CR1_TXEIE |\ + USART_CR1_PEIE | USART_CR1_CMIE |USART_CR1_RTOIE | USART_CR1_EOBIE |\ + USART_CR1_TXFEIE | USART_CR1_RXFFIE) + +/* LPUART shares the USART CR1 layout but has no receiver-timeout or + * end-of-block interrupts. + */ + +#define LPUART_CR1_ALLINTS \ + (USART_CR1_IDLEIE | USART_CR1_RXNEIE | USART_CR1_TCIE | USART_CR1_TXEIE |\ + USART_CR1_PEIE | USART_CR1_CMIE | USART_CR1_TXFEIE | USART_CR1_RXFFIE) + +/* Control register 2 */ + +#define USART_CR2_SLVEN (1 << 0) /* Bit 0: Synchronous Slave mode enable */ +#define USART_CR2_DISNSS (1 << 3) /* Bit 3: Ignore NSS pin input */ +#define USART_CR2_ADDM7 (1 << 4) /* Bit 4: 7-/4-bit Address Detection */ +#define USART_CR2_LBDL (1 << 5) /* Bit 5: LIN Break Detection Length */ +#define USART_CR2_LBDIE (1 << 6) /* Bit 6: LIN Break Detection Interrupt Enable */ +#define USART_CR2_LBCL (1 << 8) /* Bit 8: Last Bit Clock pulse */ +#define USART_CR2_CPHA (1 << 9) /* Bit 9: Clock Phase */ +#define USART_CR2_CPOL (1 << 10) /* Bit 10: Clock Polarity */ +#define USART_CR2_CLKEN (1 << 11) /* Bit 11: Clock Enable */ +#define USART_CR2_STOP_SHIFT (12) /* Bits 13-12: STOP bits */ +#define USART_CR2_STOP_MASK (3 << USART_CR2_STOP_SHIFT) +# define USART_CR2_STOP1 (0 << USART_CR2_STOP_SHIFT) /* 00: 1 Stop bit */ +# define USART_CR2_STOP2 (2 << USART_CR2_STOP_SHIFT) /* 10: 2 Stop bits */ +# define USART_CR2_STOP1p5 (3 << USART_CR2_STOP_SHIFT) /* 11: 1.5 Stop bit */ + +#define USART_CR2_LINEN (1 << 14) /* Bit 14: LIN mode enable */ +#define USART_CR2_SWAP (1 << 15) /* Bit 15: Swap TX/RX pins */ +#define USART_CR2_RXINV (1 << 16) /* Bit 16: RX pin active level inversion */ +#define USART_CR2_TXINV (1 << 17) /* Bit 17: TX pin active level inversion */ +#define USART_CR2_DATAINV (1 << 18) /* Bit 18: Binary data inversion */ +#define USART_CR2_MSBFIRST (1 << 19) /* Bit 19: Most significant bit first */ +#define USART_CR2_ABREN (1 << 20) /* Bit 20: Auto baud rate enable */ +#define USART_CR2_ABRMOD_SHIFT (21) /* Bits 21-22: Auto baud rate mode */ +#define USART_CR2_ABRMOD_MASK (3 << USART_CR2_ABRMOD_SHIFT) +# define USART_CR2_ABRMOD_START (0 << USART_CR2_ABRMOD_SHIFT) /* Start bit */ +# define USART_CR2_ABRMOD_FALL (1 << USART_CR2_ABRMOD_SHIFT) /* Falling edge measurement */ +# define USART_CR2_ABRMOD_7F (2 << USART_CR2_ABRMOD_SHIFT) /* 0x7F frame detection */ +# define USART_CR2_ABRMOD_55 (3 << USART_CR2_ABRMOD_SHIFT) /* 0x55 frame detection */ + +#define USART_CR2_RTOEN (1 << 23) /* Bit 23: Receiver timeout enable */ +#define USART_CR2_ADD4L_SHIFT (24) /* Bits 24-27: Address[3:0]:of the USART node */ +#define USART_CR2_ADD4L_MASK (15 << USART_CR2_ADD4L_SHIFT) +# define USART_CR2_ADD4L(n) ((uint32_t)(n) << USART_CR2_ADD4L_SHIFT) +#define USART_CR2_ADD4H_SHIFT (28) /* Bits 28-31: Address[4:0] of the USART node */ +#define USART_CR2_ADD4H_MASK (15 << USART_CR2_ADD4H_SHIFT) +# define USART_CR2_ADD4H(n) ((uint32_t)(n) << USART_CR2_ADD4H_SHIFT) +#define USART_CR2_ADD8_SHIFT (24) /* Bits 24-31: Address[7:0] of the USART node */ +#define USART_CR2_ADD8_MASK (255 << USART_CR2_ADD8_SHIFT) +# define USART_CR2_ADD8(n) ((uint32_t)(n) << USART_CR2_ADD8_SHIFT) + +/* Control register 3 */ + +#define USART_CR3_EIE (1 << 0) /* Bit 0: Error Interrupt Enable */ +#define USART_CR3_IREN (1 << 1) /* Bit 1: IrDA mode Enable */ +#define USART_CR3_IRLP (1 << 2) /* Bit 2: IrDA Low-Power */ +#define USART_CR3_HDSEL (1 << 3) /* Bit 3: Half-Duplex Selection */ +#define USART_CR3_NACK (1 << 4) /* Bit 4: Smartcard NACK enable */ +#define USART_CR3_SCEN (1 << 5) /* Bit 5: Smartcard mode enable */ +#define USART_CR3_DMAR (1 << 6) /* Bit 6: DMA Enable Receiver */ +#define USART_CR3_DMAT (1 << 7) /* Bit 7: DMA Enable Transmitter */ +#define USART_CR3_RTSE (1 << 8) /* Bit 8: RTS Enable */ +#define USART_CR3_CTSE (1 << 9) /* Bit 9: CTS Enable */ +#define USART_CR3_CTSIE (1 << 10) /* Bit 10: CTS Interrupt Enable */ +#define USART_CR3_ONEBIT (1 << 11) /* Bit 11: One sample bit method enable */ +#define USART_CR3_OVRDIS (1 << 12) /* Bit 12: Overrun Disable */ +#define USART_CR3_DDRE (1 << 13) /* Bit 13: DMA Disable on Reception Error */ +#define USART_CR3_DEM (1 << 14) /* Bit 14: Driver enable mode */ +#define USART_CR3_DEP (1 << 15) /* Bit 15: Driver enable polarity selection */ +#define USART_CR3_SCARCNT_SHIFT (17) /* Bit 17-19: Smartcard auto-retry count */ +#define USART_CR3_SCARCNT_MASK (7 << USART_CR3_SCARCNT_SHIFT) +# define USART_CR3_SCARCNT(n) ((uint32_t)(n) << USART_CR3_SCARCNT_SHIFT) +#define USART_CR3_WUS_SHIFT (20) /* Bit 20-21: Wakeup interrupt flag selection */ +#define USART_CR3_WUS_MASK (3 << USART_CR3_WUS_SHIFT) +# define USART_CR3_WUS_ADDR (0 << USART_CR3_WUS_SHIFT) +# define USART_CR3_WUS_STARTBIT (2 << USART_CR3_WUS_SHIFT) +# define USART_CR3_WUS_RXFNE (3 << USART_CR3_WUS_SHIFT) +#define USART_CR3_WUFIE (1 << 22) /* Bit 22: Wakeup interrupt enable */ +#define USART_CR3_RXFTCFG_SHIFT (25) /* Bit 25-27: Receive FIFO threshold configuration */ +#define USART_CR3_RXFTCFG_MASK (7 << USART_CR3_RXFTCFG_SHIFT) +# define USART_CR3_RXFTCFG(n) ((uint32_t)(n) << USART_CR3_RXFTCFG_SHIFT) +# define USART_CR3_RXFTCFG_12PCT (0 << USART_CR3_RXFTCFG_SHIFT) /* RXFIFO 1/8 full */ +# define USART_CR3_RXFTCFG_25PCT (1 << USART_CR3_RXFTCFG_SHIFT) /* RXFIFO 1/4 full */ +# define USART_CR3_RXFTCFG_50PCT (2 << USART_CR3_RXFTCFG_SHIFT) /* RXFIFO 1/2 full */ +# define USART_CR3_RXFTCFG_75PCT (3 << USART_CR3_RXFTCFG_SHIFT) /* RXFIFO 3/4 full */ +# define USART_CR3_RXFTCFG_88PCT (4 << USART_CR3_RXFTCFG_SHIFT) /* RXFIFO 7/8 full */ +# define USART_CR3_RXFTCFG_FULL (5 << USART_CR3_RXFTCFG_SHIFT) /* RXIFO full */ + +#define USART_CR3_RXFTIE (1 << 28) /* Bit 28: RXFIFO threshold interrupt enable */ +#define USART_CR3_TXFTCFG_SHIFT (29) /* Bits 29-31: TXFIFO threshold configuration */ +#define USART_CR3_TXFTCFG_MASK (7 << USART_CR3_TXFTCFG_SHIFT) +# define USART_CR3_TXFTCFG(n) ((uint32_t)(n) << USART_CR3_TXFTCFG_SHIFT) +# define USART_CR3_TXFTCFG_12PCT (0 << USART_CR3_TXFTCFG_SHIFT) /* TXFIFO 1/8 full */ +# define USART_CR3_TXFTCFG_24PCT (1 << USART_CR3_TXFTCFG_SHIFT) /* TXFIFO 1/4 full */ +# define USART_CR3_TXFTCFG_50PCT (2 << USART_CR3_TXFTCFG_SHIFT) /* TXFIFO 1/2 full */ +# define USART_CR3_TXFTCFG_75PCT (3 << USART_CR3_TXFTCFG_SHIFT) /* TXFIFO 3/4 full */ +# define USART_CR3_TXFTCFG_88PCT (4 << USART_CR3_TXFTCFG_SHIFT) /* TXFIFO 7/8 full */ +# define USART_CR3_TXFTCFG_EMPY (5 << USART_CR3_TXFTCFG_SHIFT) /* TXFIFO empty */ + +/* Baud Rate Register */ + +#define USART_BRR_SHIFT (0) /* Bits 0-15: USARTDIV[15:0] OVER8=0*/ +#define USART_BRR_MASK (0xffff << USART_BRR_SHIFT) +# define USART_BRR(n) ((uint32_t)(n) << USART_BRR_SHIFT) + +/* Guard time and prescaler register */ + +#define USART_GTPR_PSC_SHIFT (0) /* Bits 0-7: Prescaler value */ +#define USART_GTPR_PSC_MASK (0xff << USART_GTPR_PSC_SHIFT) +# define USART_GTPR_PSC(n) ((uint32_t)(n) << USART_GTPR_PSC_SHIFT) +#define USART_GTPR_GT_SHIFT (8) /* Bits 8-15: Guard time value */ +#define USART_GTPR_GT_MASK (0xff << USART_GTPR_GT_SHIFT) +# define USART_GTPR_GT(n) ((uint32_t)(n) << USART_GTPR_GT_SHIFT) + +/* Receiver timeout register */ + +#define USART_RTOR_RTO_SHIFT (0) /* Bits 0-23: Receiver timeout value */ +#define USART_RTOR_RTO_MASK (0xffffff << USART_RTOR_RTO_SHIFT) +# define USART_RTOR_RTO(n) ((uint32_t)(n) << USART_RTOR_RTO_SHIFT) +#define USART_RTOR_BLEN_SHIFT (24) /* Bits 24-31: Block Length */ +#define USART_RTOR_BLEN_MASK (0xff << USART_RTOR_BLEN_SHIFT) +# define USART_RTOR_BLEN(n) ((uint32_t)(n) << USART_RTOR_BLEN_SHIFT) + +/* Request register */ + +#define USART_RQR_ABRRQ (1 << 0) /* Bit 0: Auto baud rate request */ +#define USART_RQR_SBKRQ (1 << 1) /* Bit 1: Send break request */ +#define USART_RQR_MMRQ (1 << 2) /* Bit 2: Mute mode request */ +#define USART_RQR_RXFRQ (1 << 3) /* Bit 3: Receive data flush request */ +#define USART_RQR_TXFRQ (1 << 4) /* Bit 4: Transmit data flush request */ + +/* Interrupt & status register */ + +#define USART_ISR_PE (1 << 0) /* Bit 0: Parity error */ +#define USART_ISR_FE (1 << 1) /* Bit 1: Framing error */ +#define USART_ISR_NE (1 << 2) /* Bit 2: Noise detected flag */ +#define USART_ISR_ORE (1 << 3) /* Bit 3: Overrun error */ +#define USART_ISR_IDLE (1 << 4) /* Bit 4: Idle line detected */ +#define USART_ISR_RXNE (1 << 5) /* Bit 5: Read data register not empty */ +#define USART_ISR_TC (1 << 6) /* Bit 6: Transmission complete */ +#define USART_ISR_TXE (1 << 7) /* Bit 7: Transmit data register empty */ +#define USART_ISR_LBDF (1 << 8) /* Bit 8: LIN break detection flag */ +#define USART_ISR_CTSIF (1 << 9) /* Bit 9: CTS interrupt flag */ +#define USART_ISR_CTS (1 << 10) /* Bit 10: CTS flag */ +#define USART_ISR_RTOF (1 << 11) /* Bit 11: Receiver timeout */ +#define USART_ISR_EOBF (1 << 12) /* Bit 12: End of block flag */ +#define USART_ISR_UDR (1 << 13) /* Bit 13: SPI slave underrun error flag */ +#define USART_ISR_ABRE (1 << 14) /* Bit 14: Auto baud rate error */ +#define USART_ISR_ABRF (1 << 15) /* Bit 15: Auto baud rate flag */ +#define USART_ISR_BUSY (1 << 16) /* Bit 16: Busy flag */ +#define USART_ISR_CMF (1 << 17) /* Bit 17: Character match flag */ +#define USART_ISR_SBKF (1 << 18) /* Bit 18: Send break flag */ +#define USART_ISR_RWU (1 << 19) /* Bit 19: Receiver wakeup from Mute mode */ +#define USART_ISR_WUF (1 << 20) /* Bit 20: Wakeup from low-power mode flag */ +#define USART_ISR_TEACK (1 << 21) /* Bit 21: Transmit enable acknowledge flag */ +#define USART_ISR_REACK (1 << 22) /* Bit 22: Receive enable acknowledge flag */ +#define USART_ISR_TXFE (1 << 23) /* Bit 23: TXFIFO Empty */ +#define USART_ISR_RXFF (1 << 24) /* Bit 24: RXFIFO Full */ +#define USART_ISR_TCBGT (1 << 25) /* Bit 25: Transmission complete before guard time flag */ +#define USART_ISR_RXFT (1 << 26) /* Bit 26: RXFIFO threshold flag */ +#define USART_ISR_TXFT (1 << 27) /* Bit 27: TXFIFO threshold flag */ + +#define USART_ISR_ALLBITS (0x0fffffff) + +/* Interrupt flag clear register */ + +#define USART_ICR_PECF (1 << 0) /* Bit 0: Parity error clear flag */ +#define USART_ICR_FECF (1 << 1) /* Bit 1: Framing error clear flag */ +#define USART_ICR_NCF (1 << 2) /* Bit 2: Noise detected flag *clear flag */ +#define USART_ICR_ORECF (1 << 3) /* Bit 3: Overrun error clear flag */ +#define USART_ICR_IDLECF (1 << 4) /* Bit 4: Idle line detected clear flag */ +#define USART_ICR_TXFECF (1 << 5) /* Bit 5: TXFIFO empty clear flag */ +#define USART_ICR_TCCF (1 << 6) /* Bit 6: Transmission complete */ +#define USART_ICR_TCBGTCF (1 << 7) /* Bit 7: Transmission complete before Guard time clear flag */ +#define USART_ICR_LBDCF (1 << 8) /* Bit 8: LIN break detection clear flag */ +#define USART_ICR_CTSCF (1 << 9) /* Bit 9: CTS interrupt clear flag */ +#define USART_ICR_RTOCF (1 << 11) /* Bit 11: Receiver timeout clear flag */ +#define USART_ICR_EOBCF (1 << 12) /* Bit 12: End of block clear flag */ +#define USART_ICR_UDRCF (1 << 13) /* Bit 13:SPI slave underrun clear flag */ +#define USART_ICR_CMCF (1 << 17) /* Bit 17: Character match clear flag */ +#define USART_ICR_WUCF (1 << 20) /* Bit 20: Wakeup from low-power mode clear flag */ + +#define USART_ICR_ALLBITS (0x00123b7f) + +/* Receive data register */ + +#define USART_RDR_SHIFT (0) /* Bits 0-8: Receive data value */ +#define USART_RDR_MASK (0x1ff << USART_RDR_SHIFT) + +/* Transmit data register */ + +#define USART_TDR_SHIFT (0) /* Bits 0-8: Transmit data value */ +#define USART_TDR_MASK (0x1ff << USART_TDR_SHIFT) + +/* Prescaler register */ + +#define USART_PRESC_SHIFT (0) /* Bits 0-3: Clock prescaler */ +#define USART_PRESC_MASK (15 << USART_PRESC_SHIFT) +# define USART_PRESC_NODIV (0 << USART_PRESC_SHIFT) /* Input clock not divided */ +# define USART_PRESC_DIV1 (1 << USART_PRESC_SHIFT) /* Input clock divided by 2 */ +# define USART_PRESC_DIV4 (2 << USART_PRESC_SHIFT) /* Input clock divided by 4 */ +# define USART_PRESC_DIV6 (3 << USART_PRESC_SHIFT) /* Input clock divided by 6 */ +# define USART_PRESC_DIV8 (4 << USART_PRESC_SHIFT) /* Input clock divided by 8 */ +# define USART_PRESC_DIV10 (5 << USART_PRESC_SHIFT) /* Input clock divided by 10 */ +# define USART_PRESC_DIV12 (6 << USART_PRESC_SHIFT) /* Input clock divided by 12 */ +# define USART_PRESC_DIV16 (7 << USART_PRESC_SHIFT) /* Input clock divided by 16 */ +# define USART_PRESC_DIV32 (8 << USART_PRESC_SHIFT) /* Input clock divided by 32 */ +# define USART_PRESC_DIV64 (9 << USART_PRESC_SHIFT) /* Input clock divided by 64 */ +# define USART_PRESC_DIV128 (10 << USART_PRESC_SHIFT) /* Input clock divided by 128 */ +# define USART_PRESC_DIV256 (11 << USART_PRESC_SHIFT) /* Input clock divided by 256 */ + +/* Compatibility definitions ************************************************/ + +/* Compatibility with F1/F2/F4 Status Register names. This USART IP replaces + * the SR register with separate ISR/ICR registers; alias the legacy SR names + * so the shared M3/M4 serial driver keeps working on these parts. + */ + +#define STM32_USART_SR_OFFSET STM32_USART_ISR_OFFSET + +#define USART_SR_PE USART_ISR_PE /* Parity Error */ +#define USART_SR_FE USART_ISR_FE /* Framing error */ +#define USART_SR_NE USART_ISR_NE /* Noise detected flag */ +#define USART_SR_ORE USART_ISR_ORE /* Overrun error */ +#define USART_SR_IDLE USART_ISR_IDLE /* IDLE line detected */ +#define USART_SR_RXNE USART_ISR_RXNE /* Read Data Register Not Empty */ +#define USART_SR_TC USART_ISR_TC /* Transmission Complete */ +#define USART_SR_TXE USART_ISR_TXE /* Transmit Data Register Empty */ +#define USART_SR_LBD USART_ISR_LBDF /* LIN Break Detection Flag */ +#define USART_SR_CTS USART_ISR_CTS /* CTS Flag */ + +#define USART_SR_ALLBITS USART_ISR_ALLBITS + +#define USART_CR1_M USART_CR1_M0 + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_UART_V4_H */ diff --git a/arch/arm/src/common/stm32/hardware/stm32_usbdev.h b/arch/arm/src/common/stm32/hardware/stm32_usbdev.h new file mode 100644 index 0000000000000..ae78216c98a14 --- /dev/null +++ b/arch/arm/src/common/stm32/hardware/stm32_usbdev.h @@ -0,0 +1,43 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/hardware/stm32_usbdev.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_USBDEV_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_USBDEV_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#if (defined(CONFIG_STM32_HAVE_IP_USBDEV_M0_V1) + \ + defined(CONFIG_STM32_HAVE_IP_USBDEV_M3M4_V1)) > 1 +# error Only one STM32 USB device IP version must be selected +#endif + +#if defined(CONFIG_STM32_HAVE_IP_USBDEV_M0_V1) +# include "hardware/stm32_usbdev_m0.h" +#elif defined(CONFIG_STM32_HAVE_IP_USBDEV_M3M4_V1) +# include "hardware/stm32_usbdev_v1.h" +#else +# error "Unsupported STM32 USB device" +#endif + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_USBDEV_H */ diff --git a/arch/arm/src/common/stm32/hardware/stm32_usbdev_m0.h b/arch/arm/src/common/stm32/hardware/stm32_usbdev_m0.h new file mode 100644 index 0000000000000..d40fb53b23aba --- /dev/null +++ b/arch/arm/src/common/stm32/hardware/stm32_usbdev_m0.h @@ -0,0 +1,255 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/hardware/stm32_usbdev_m0.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_USBDEV_M0_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_USBDEV_M0_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#ifdef CONFIG_STM32_HAVE_USBDEV + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Register Offsets *********************************************************/ + +/* Endpoint Registers */ + +#define STM32_USB_EPR_OFFSET(n) ((n) << 2) /* USB endpoint n register (16-bits) */ + +#define STM32_USB_EP0R_OFFSET 0x0000 /* USB endpoint 0 register (16-bits) */ +#define STM32_USB_EP1R_OFFSET 0x0004 /* USB endpoint 1 register (16-bits) */ +#define STM32_USB_EP2R_OFFSET 0x0008 /* USB endpoint 2 register (16-bits) */ +#define STM32_USB_EP3R_OFFSET 0x000c /* USB endpoint 3 register (16-bits) */ +#define STM32_USB_EP4R_OFFSET 0x0010 /* USB endpoint 4 register (16-bits) */ +#define STM32_USB_EP5R_OFFSET 0x0014 /* USB endpoint 5 register (16-bits) */ +#define STM32_USB_EP6R_OFFSET 0x0018 /* USB endpoint 6 register (16-bits) */ +#define STM32_USB_EP7R_OFFSET 0x001c /* USB endpoint 7 register (16-bits) */ + +/* Common Registers */ + +#define STM32_USB_CNTR_OFFSET 0x0040 /* USB control register (16-bits) */ +#define STM32_USB_ISTR_OFFSET 0x0044 /* USB interrupt status register (16-bits) */ +#define STM32_USB_FNR_OFFSET 0x0048 /* USB frame number register (16-bits) */ +#define STM32_USB_DADDR_OFFSET 0x004c /* USB device address (16-bits) */ +#define STM32_USB_BTABLE_OFFSET 0x0050 /* Buffer table address (16-bits) */ +#define STM32_USB_LPMCSR_OFFSET 0x0054 /* LPM control and status register (16-bits) */ +#define STM32_USB_BCDR_OFFSET 0x0058 /* Battery charging detector (16-bits) */ + +/* Buffer Descriptor Table (Relatative to BTABLE address) */ + +#define STM32_USB_ADDR_TX_WOFFSET (0) /* Transmission buffer address n (16-bits) */ +#define STM32_USB_COUNT_TX_WOFFSET (2) /* Transmission byte count n (16-bits) */ +#define STM32_USB_ADDR_RX_WOFFSET (4) /* Reception buffer address n (16-bits) */ +#define STM32_USB_COUNT_RX_WOFFSET (6) /* Reception byte count n (16-bits) */ + +#define STM32_USB_BTABLE_RADDR(ep,o) ((((uint32_t)getreg16(STM32_USB_BTABLE) + ((ep) << 3)) + (o)) << 1) +#define STM32_USB_ADDR_TX_OFFSET(ep) STM32_USB_BTABLE_RADDR(ep,STM32_USB_ADDR_TX_WOFFSET) +#define STM32_USB_COUNT_TX_OFFSET(ep) STM32_USB_BTABLE_RADDR(ep,STM32_USB_COUNT_TX_WOFFSET) +#define STM32_USB_ADDR_RX_OFFSET(ep) STM32_USB_BTABLE_RADDR(ep,STM32_USB_ADDR_RX_WOFFSET) +#define STM32_USB_COUNT_RX_OFFSET(ep) STM32_USB_BTABLE_RADDR(ep,STM32_USB_COUNT_RX_WOFFSET) + +/* Register Addresses *******************************************************/ + +/* Endpoint Registers */ + +#define STM32_USB_EPR(n) (STM32_USB_BASE + STM32_USB_EPR_OFFSET(n)) +#define STM32_USB_EP0R (STM32_USB_BASE + STM32_USB_EP0R_OFFSET) +#define STM32_USB_EP1R (STM32_USB_BASE + STM32_USB_EP1R_OFFSET) +#define STM32_USB_EP2R (STM32_USB_BASE + STM32_USB_EP2R_OFFSET) +#define STM32_USB_EP3R (STM32_USB_BASE + STM32_USB_EP3R_OFFSET) +#define STM32_USB_EP4R (STM32_USB_BASE + STM32_USB_EP4R_OFFSET) +#define STM32_USB_EP5R (STM32_USB_BASE + STM32_USB_EP5R_OFFSET) +#define STM32_USB_EP6R (STM32_USB_BASE + STM32_USB_EP6R_OFFSET) +#define STM32_USB_EP7R (STM32_USB_BASE + STM32_USB_EP7R_OFFSET) + +/* Common Registers */ + +#define STM32_USB_CNTR (STM32_USB_BASE + STM32_USB_CNTR_OFFSET) +#define STM32_USB_ISTR (STM32_USB_BASE + STM32_USB_ISTR_OFFSET) +#define STM32_USB_FNR (STM32_USB_BASE + STM32_USB_FNR_OFFSET) +#define STM32_USB_DADDR (STM32_USB_BASE + STM32_USB_DADDR_OFFSET) +#define STM32_USB_BTABLE (STM32_USB_BASE + STM32_USB_BTABLE_OFFSET) +#define STM32_USB_LPMCSR (STM32_USB_BASE + STM32_USB_LPMCSR_OFFSET) +#define STM32_USB_BCDR (STM32_USB_BASE + STM32_USB_BCDR_OFFSET) + +/* Buffer Descriptor Table (Relative to BTABLE address) */ + +#define STM32_USB_BTABLE_ADDR(ep,o) (STM32_USBRAM_BASE + STM32_USB_BTABLE_RADDR(ep,o)) +#define STM32_USB_ADDR_TX(ep) STM32_USB_BTABLE_ADDR(ep,STM32_USB_ADDR_TX_WOFFSET) +#define STM32_USB_COUNT_TX(ep) STM32_USB_BTABLE_ADDR(ep,STM32_USB_COUNT_TX_WOFFSET) +#define STM32_USB_ADDR_RX(ep) STM32_USB_BTABLE_ADDR(ep,STM32_USB_ADDR_RX_WOFFSET) +#define STM32_USB_COUNT_RX(ep) STM32_USB_BTABLE_ADDR(ep,STM32_USB_COUNT_RX_WOFFSET) + +/* Register Bitfield Definitions ********************************************/ + +/* USB endpoint register */ + +#define USB_EPR_EA_SHIFT (0) /* Bits 3:0 [3:0]: Endpoint Address */ +#define USB_EPR_EA_MASK (0X0f << USB_EPR_EA_SHIFT) +#define USB_EPR_STATTX_SHIFT (4) /* Bits 5-4: Status bits, for transmission transfers */ +#define USB_EPR_STATTX_MASK (3 << USB_EPR_STATTX_SHIFT) +# define USB_EPR_STATTX_DIS (0 << USB_EPR_STATTX_SHIFT) /* EndPoint TX DISabled */ +# define USB_EPR_STATTX_STALL (1 << USB_EPR_STATTX_SHIFT) /* EndPoint TX STALLed */ +# define USB_EPR_STATTX_NAK (2 << USB_EPR_STATTX_SHIFT) /* EndPoint TX NAKed */ +# define USB_EPR_STATTX_VALID (3 << USB_EPR_STATTX_SHIFT) /* EndPoint TX VALID */ +# define USB_EPR_STATTX_DTOG1 (1 << USB_EPR_STATTX_SHIFT) /* EndPoint TX Data Toggle bit1 */ +# define USB_EPR_STATTX_DTOG2 (2 << USB_EPR_STATTX_SHIFT) /* EndPoint TX Data Toggle bit2 */ + +#define USB_EPR_DTOG_TX (1 << 6) /* Bit 6: Data Toggle, for transmission transfers */ +#define USB_EPR_CTR_TX (1 << 7) /* Bit 7: Correct Transfer for transmission */ +#define USB_EPR_EP_KIND (1 << 8) /* Bit 8: Endpoint Kind */ +#define USB_EPR_EPTYPE_SHIFT (9) /* Bits 10-9: Endpoint type */ +#define USB_EPR_EPTYPE_MASK (3 << USB_EPR_EPTYPE_SHIFT) +# define USB_EPR_EPTYPE_BULK (0 << USB_EPR_EPTYPE_SHIFT) /* EndPoint BULK */ +# define USB_EPR_EPTYPE_CONTROL (1 << USB_EPR_EPTYPE_SHIFT) /* EndPoint CONTROL */ +# define USB_EPR_EPTYPE_ISOC (2 << USB_EPR_EPTYPE_SHIFT) /* EndPoint ISOCHRONOUS */ +# define USB_EPR_EPTYPE_INTERRUPT (3 << USB_EPR_EPTYPE_SHIFT) /* EndPoint INTERRUPT */ + +#define USB_EPR_SETUP (1 << 11) /* Bit 11: Setup transaction completed */ +#define USB_EPR_STATRX_SHIFT (12) /* Bits 13-12: Status bits, for reception transfers */ +#define USB_EPR_STATRX_MASK (3 << USB_EPR_STATRX_SHIFT) +# define USB_EPR_STATRX_DIS (0 << USB_EPR_STATRX_SHIFT) /* EndPoint RX DISabled */ +# define USB_EPR_STATRX_STALL (1 << USB_EPR_STATRX_SHIFT) /* EndPoint RX STALLed */ +# define USB_EPR_STATRX_NAK (2 << USB_EPR_STATRX_SHIFT) /* EndPoint RX NAKed */ +# define USB_EPR_STATRX_VALID (3 << USB_EPR_STATRX_SHIFT) /* EndPoint RX VALID */ +# define USB_EPR_STATRX_DTOG1 (1 << USB_EPR_STATRX_SHIFT) /* EndPoint RX Data TOGgle bit1 */ +# define USB_EPR_STATRX_DTOG2 (2 << USB_EPR_STATRX_SHIFT) /* EndPoint RX Data TOGgle bit1 */ + +#define USB_EPR_DTOG_RX (1 << 14) /* Bit 14: Data Toggle, for reception transfers */ +#define USB_EPR_CTR_RX (1 << 15) /* Bit 15: Correct Transfer for reception */ + +/* USB control register */ + +#define USB_CNTR_FRES (1 << 0) /* Bit 0: Force USB Reset */ +#define USB_CNTR_PDWN (1 << 1) /* Bit 1: Power down */ +#define USB_CNTR_LPMODE (1 << 2) /* Bit 2: Low-power mode */ +#define USB_CNTR_FSUSP (1 << 3) /* Bit 3: Force suspend */ +#define USB_CNTR_RESUME (1 << 4) /* Bit 4: Resume request */ +#define USB_CNTR_L1RESUME (1 << 5) /* Bit 5: LPM L1 Resume request */ +#define USB_CNTR_L1REQ (1 << 7) /* Bit 7: LPM L1 state request interrupt mask */ +#define USB_CNTR_ESOFM (1 << 8) /* Bit 8: Expected Start Of Frame Interrupt Mask */ +#define USB_CNTR_SOFM (1 << 9) /* Bit 9: Start Of Frame Interrupt Mask */ +#define USB_CNTR_RESETM (1 << 10) /* Bit 10: USB Reset Interrupt Mask */ +#define USB_CNTR_SUSPM (1 << 11) /* Bit 11: Suspend mode Interrupt Mask */ +#define USB_CNTR_WKUPM (1 << 12) /* Bit 12: Wakeup Interrupt Mask */ +#define USB_CNTR_ERRM (1 << 13) /* Bit 13: Error Interrupt Mask */ +#define USB_CNTR_PMAOVRN (1 << 14) /* Bit 14: Packet Memory Area Over / Underrun Interrupt Mask */ +#define USB_CNTR_CTRM (1 << 15) /* Bit 15: Correct Transfer Interrupt Mask */ + +#define USB_CNTR_ALLINTS (USB_CNTR_L1REQ|USB_CNTR_ESOFM|USB_CNTR_SOFM|USB_CNTR_RESETM|\ + USB_CNTR_SUSPM|USB_CNTR_WKUPM|USB_CNTR_ERRM|USB_CNTR_PMAOVRN|\ + USB_CNTR_CTRM) + +/* USB interrupt status register */ + +#define USB_ISTR_EPID_SHIFT (0) /* Bits 3-0: Endpoint Identifier */ +#define USB_ISTR_EPID_MASK (0x0f << USB_ISTR_EPID_SHIFT) +#define USB_ISTR_DIR (1 << 4) /* Bit 4: Direction of transaction */ +#define USB_ISTR_L1REQ (1 << 7) /* Bit 7: LPM L1 state request */ +#define USB_ISTR_ESOF (1 << 8) /* Bit 8: Expected Start Of Frame */ +#define USB_ISTR_SOF (1 << 9) /* Bit 9: Start Of Frame */ +#define USB_ISTR_RESET (1 << 10) /* Bit 10: USB RESET request */ +#define USB_ISTR_SUSP (1 << 11) /* Bit 11: Suspend mode request */ +#define USB_ISTR_WKUP (1 << 12) /* Bit 12: Wake up */ +#define USB_ISTR_ERR (1 << 13) /* Bit 13: Error */ +#define USB_ISTR_PMAOVRN (1 << 14) /* Bit 14: Packet Memory Area Over / Underrun */ +#define USB_ISTR_CTR (1 << 15) /* Bit 15: Correct Transfer */ + +#define USB_ISTR_ALLINTS (USB_ISTR_L1REQ|USB_ISTR_ESOF|USB_ISTR_SOF|USB_ISTR_RESET|\ + USB_ISTR_SUSP|USB_ISTR_WKUP|USB_ISTR_ERR|USB_ISTR_PMAOVRN|\ + USB_ISTR_CTR) + +/* USB frame number register */ + +#define USB_FNR_FN_SHIFT (0) /* Bits 10-0: Frame Number */ +#define USB_FNR_FN_MASK (0x07ff << USB_FNR_FN_SHIFT) +#define USB_FNR_LSOF_SHIFT (11) /* Bits 12-11: Lost SOF */ +#define USB_FNR_LSOF_MASK (3 << USB_FNR_LSOF_SHIFT) +#define USB_FNR_LCK (1 << 13) /* Bit 13: Locked */ +#define USB_FNR_RXDM (1 << 14) /* Bit 14: Receive Data - Line Status */ +#define USB_FNR_RXDP (1 << 15) /* Bit 15: Receive Data + Line Status */ + +/* USB device address */ + +#define USB_DADDR_ADD_SHIFT (0) /* Bits 6-0: Device Address */ +#define USB_DADDR_ADD_MASK (0x7f << USB_DADDR_ADD_SHIFT) +#define USB_DADDR_EF (1 << 7) /* Bit 7: Enable Function */ + +/* Buffer table address */ + +#define USB_BTABLE_SHIFT (3) /* Bits 15:3: Buffer Table */ +#define USB_BTABLE_MASK (0x1fff << USB_BTABLE_SHIFT) + +/* LPM control and status register (16-bits) */ + +#define USB_LPMCSR_LPMEN (1 << 0) /* Bit 0: LPM support enable */ +#define USB_LPMCSR_LPMACK (1 << 1) /* Bit 1: LPM Token acknowledge enable */ +#define USB_LPMCSR_REMWAKE (1 << 3) /* Bit 3: bRemoteWake value */ +#define USB_LPMCSR_BESL_SHIFT (4) /* Bits 4-7: BESL value */ +#define USB_LPMCSR_BESL_MASK (15 << USB_LPMCSR_BESL_SHIFT) + +/* Battery charging detector (16-bits) */ + +#define USB_BCDR_BCDEN (1 << 0) /* Bit 0: Battery charging detector (BCD) enable */ +#define USB_BCDR_DCDEN (1 << 1) /* Bit 1: Data contact detection (DCD) mode enable */ +#define USB_BCDR_PDEN (1 << 2) /* Bit 2: Primary detection (PD) mode enable */ +#define USB_BCDR_SDEN (1 << 3) /* Bit 3: Secondary detection (SD) mode enable */ +#define USB_BCDR_DCDET (1 << 4) /* Bit 4: Data contact detection (DCD) status */ +#define USB_BCDR_PDET (1 << 5) /* Bit 5: Primary detection (PD) status */ +#define USB_BCDR_SDET (1 << 6) /* Bit 6: Secondary detection (SD) status */ +#define USB_BCDR_PS2DET (1 << 7) /* Bit 7: DM pull-up detection status */ +#define USB_BCDR_DPPU (1 << 15) /* Bit 15: DP pull-up control */ + +/* Transmission buffer address */ + +#define USB_ADDR_TX_ZERO (1 << 0) /* Bit 0 Must always be written as ‘0’ */ +#define USB_ADDR_TX_SHIFT (1) /* Bits 15-1: Transmission Buffer Address */ +#define USB_ADDR_TX_MASK (0x7fff << USB_ADDR_ADDR_TX_SHIFT) + +/* Transmission byte count */ + +#define USB_COUNT_TX_SHIFT (0) /* Bits 9-0: Transmission Byte Count */ +#define USB_COUNT_TX_MASK (0x03ff << USB_COUNT_COUNT_TX_SHIFT) + +/* Reception buffer address */ + +#define USB_ADDR_RX_ZERO (1 << 0) /* Bit 0 This bit must always be written as ‘0’ */ +#define USB_ADDR_RX_SHIFT (1) /* Bits 15:1 ADDRn_RX[15:1]: Reception Buffer Address */ +#define USB_ADDR_RX_MASK (0x7fff << USB_ADDR_RX_SHIFT) + +/* Reception byte count */ + +#define USB_COUNT_RX_BL_SIZE (1 << 15) /* Bit 15: BLock SIZE. */ +#define USB_COUNT_RX_NUM_BLOCK_SHIFT (10) /* Bits 14-10: Number of blocks */ +#define USB_COUNT_RX_NUM_BLOCK_MASK (0x1f << USB_COUNT_RX_NUM_BLOCK_SHIFT) +#define USB_COUNT_RX_SHIFT (0) /* Bits 9-0: Reception Byte Count */ +#define USB_COUNT_RX_MASK (0x03ff << USB_COUNT_RX_SHIFT) + +#endif /* CONFIG_STM32_HAVE_USBDEV */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_USBDEV_M0_H */ diff --git a/arch/arm/src/common/stm32/hardware/stm32_usbdev_v1.h b/arch/arm/src/common/stm32/hardware/stm32_usbdev_v1.h new file mode 100644 index 0000000000000..2a7b97f4936f4 --- /dev/null +++ b/arch/arm/src/common/stm32/hardware/stm32_usbdev_v1.h @@ -0,0 +1,227 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/hardware/stm32_usbdev_v1.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_USBDEV_V1_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_USBDEV_V1_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include "chip.h" + +#if defined(CONFIG_STM32_STM32L15XX) || defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F30XX) \ + || defined(CONFIG_STM32_STM32F37XX) + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Register Offsets *********************************************************/ + +/* Endpoint Registers */ + +#define STM32_USB_EPR_OFFSET(n) ((n) << 2) /* USB endpoint n register (16-bits) */ + +#define STM32_USB_EP0R_OFFSET 0x0000 /* USB endpoint 0 register (16-bits) */ +#define STM32_USB_EP1R_OFFSET 0x0004 /* USB endpoint 1 register (16-bits) */ +#define STM32_USB_EP2R_OFFSET 0x0008 /* USB endpoint 2 register (16-bits) */ +#define STM32_USB_EP3R_OFFSET 0x000c /* USB endpoint 3 register (16-bits) */ +#define STM32_USB_EP4R_OFFSET 0x0010 /* USB endpoint 4 register (16-bits) */ +#define STM32_USB_EP5R_OFFSET 0x0014 /* USB endpoint 5 register (16-bits) */ +#define STM32_USB_EP6R_OFFSET 0x0018 /* USB endpoint 6 register (16-bits) */ +#define STM32_USB_EP7R_OFFSET 0x001c /* USB endpoint 7 register (16-bits) */ + +/* Common Registers */ + +#define STM32_USB_CNTR_OFFSET 0x0040 /* USB control register (16-bits) */ +#define STM32_USB_ISTR_OFFSET 0x0044 /* USB interrupt status register (16-bits) */ +#define STM32_USB_FNR_OFFSET 0x0048 /* USB frame number register (16-bits) */ +#define STM32_USB_DADDR_OFFSET 0x004c /* USB device address (16-bits) */ +#define STM32_USB_BTABLE_OFFSET 0x0050 /* Buffer table address (16-bits) */ + +/* Buffer Descriptor Table (Relatative to BTABLE address) */ + +#define STM32_USB_ADDR_TX_WOFFSET (0) /* Transmission buffer address n (16-bits) */ +#define STM32_USB_COUNT_TX_WOFFSET (2) /* Transmission byte count n (16-bits) */ +#define STM32_USB_ADDR_RX_WOFFSET (4) /* Reception buffer address n (16-bits) */ +#define STM32_USB_COUNT_RX_WOFFSET (6) /* Reception byte count n (16-bits) */ + +#define STM32_USB_BTABLE_RADDR(ep,o) ((((uint32_t)getreg16(STM32_USB_BTABLE) + ((ep) << 3)) + (o)) << 1) +#define STM32_USB_ADDR_TX_OFFSET(ep) STM32_USB_BTABLE_RADDR(ep,STM32_USB_ADDR_TX_WOFFSET) +#define STM32_USB_COUNT_TX_OFFSET(ep) STM32_USB_BTABLE_RADDR(ep,STM32_USB_COUNT_TX_WOFFSET) +#define STM32_USB_ADDR_RX_OFFSET(ep) STM32_USB_BTABLE_RADDR(ep,STM32_USB_ADDR_RX_WOFFSET) +#define STM32_USB_COUNT_RX_OFFSET(ep) STM32_USB_BTABLE_RADDR(ep,STM32_USB_COUNT_RX_WOFFSET) + +/* Register Addresses *******************************************************/ + +/* Endpoint Registers */ + +#define STM32_USB_EPR(n) (STM32_USB_BASE+STM32_USB_EPR_OFFSET(n)) +#define STM32_USB_EP0R (STM32_USB_BASE+STM32_USB_EP0R_OFFSET) +#define STM32_USB_EP1R (STM32_USB_BASE+STM32_USB_EP1R_OFFSET) +#define STM32_USB_EP2R (STM32_USB_BASE+STM32_USB_EP2R_OFFSET) +#define STM32_USB_EP3R (STM32_USB_BASE+STM32_USB_EP3R_OFFSET) +#define STM32_USB_EP4R (STM32_USB_BASE+STM32_USB_EP4R_OFFSET) +#define STM32_USB_EP5R (STM32_USB_BASE+STM32_USB_EP5R_OFFSET) +#define STM32_USB_EP6R (STM32_USB_BASE+STM32_USB_EP6R_OFFSET) +#define STM32_USB_EP7R (STM32_USB_BASE+STM32_USB_EP7R_OFFSET) + +/* Common Registers */ + +#define STM32_USB_CNTR (STM32_USB_BASE+STM32_USB_CNTR_OFFSET) +#define STM32_USB_ISTR (STM32_USB_BASE+STM32_USB_ISTR_OFFSET) +#define STM32_USB_FNR (STM32_USB_BASE+STM32_USB_FNR_OFFSET) +#define STM32_USB_DADDR (STM32_USB_BASE+STM32_USB_DADDR_OFFSET) +#define STM32_USB_BTABLE (STM32_USB_BASE+STM32_USB_BTABLE_OFFSET) + +/* Buffer Descriptor Table (Relatative to BTABLE address) */ + +#define STM32_USB_BTABLE_ADDR(ep,o) (STM32_USBRAM_BASE+STM32_USB_BTABLE_RADDR(ep,o)) +#define STM32_USB_ADDR_TX(ep) STM32_USB_BTABLE_ADDR(ep,STM32_USB_ADDR_TX_WOFFSET) +#define STM32_USB_COUNT_TX(ep) STM32_USB_BTABLE_ADDR(ep,STM32_USB_COUNT_TX_WOFFSET) +#define STM32_USB_ADDR_RX(ep) STM32_USB_BTABLE_ADDR(ep,STM32_USB_ADDR_RX_WOFFSET) +#define STM32_USB_COUNT_RX(ep) STM32_USB_BTABLE_ADDR(ep,STM32_USB_COUNT_RX_WOFFSET) + +/* Register Bitfield Definitions ********************************************/ + +/* USB endpoint register */ + +#define USB_EPR_EA_SHIFT (0) /* Bits 3:0 [3:0]: Endpoint Address */ +#define USB_EPR_EA_MASK (0X0f << USB_EPR_EA_SHIFT) +#define USB_EPR_STATTX_SHIFT (4) /* Bits 5-4: Status bits, for transmission transfers */ +#define USB_EPR_STATTX_MASK (3 << USB_EPR_STATTX_SHIFT) +# define USB_EPR_STATTX_DIS (0 << USB_EPR_STATTX_SHIFT) /* EndPoint TX DISabled */ +# define USB_EPR_STATTX_STALL (1 << USB_EPR_STATTX_SHIFT) /* EndPoint TX STALLed */ +# define USB_EPR_STATTX_NAK (2 << USB_EPR_STATTX_SHIFT) /* EndPoint TX NAKed */ +# define USB_EPR_STATTX_VALID (3 << USB_EPR_STATTX_SHIFT) /* EndPoint TX VALID */ +# define USB_EPR_STATTX_DTOG1 (1 << USB_EPR_STATTX_SHIFT) /* EndPoint TX Data Toggle bit1 */ +# define USB_EPR_STATTX_DTOG2 (2 << USB_EPR_STATTX_SHIFT) /* EndPoint TX Data Toggle bit2 */ + +#define USB_EPR_DTOG_TX (1 << 6) /* Bit 6: Data Toggle, for transmission transfers */ +#define USB_EPR_CTR_TX (1 << 7) /* Bit 7: Correct Transfer for transmission */ +#define USB_EPR_EP_KIND (1 << 8) /* Bit 8: Endpoint Kind */ +#define USB_EPR_EPTYPE_SHIFT (9) /* Bits 10-9: Endpoint type */ +#define USB_EPR_EPTYPE_MASK (3 << USB_EPR_EPTYPE_SHIFT) +# define USB_EPR_EPTYPE_BULK (0 << USB_EPR_EPTYPE_SHIFT) /* EndPoint BULK */ +# define USB_EPR_EPTYPE_CONTROL (1 << USB_EPR_EPTYPE_SHIFT) /* EndPoint CONTROL */ +# define USB_EPR_EPTYPE_ISOC (2 << USB_EPR_EPTYPE_SHIFT) /* EndPoint ISOCHRONOUS */ +# define USB_EPR_EPTYPE_INTERRUPT (3 << USB_EPR_EPTYPE_SHIFT) /* EndPoint INTERRUPT */ + +#define USB_EPR_SETUP (1 << 11) /* Bit 11: Setup transaction completed */ +#define USB_EPR_STATRX_SHIFT (12) /* Bits 13-12: Status bits, for reception transfers */ +#define USB_EPR_STATRX_MASK (3 << USB_EPR_STATRX_SHIFT) +# define USB_EPR_STATRX_DIS (0 << USB_EPR_STATRX_SHIFT) /* EndPoint RX DISabled */ +# define USB_EPR_STATRX_STALL (1 << USB_EPR_STATRX_SHIFT) /* EndPoint RX STALLed */ +# define USB_EPR_STATRX_NAK (2 << USB_EPR_STATRX_SHIFT) /* EndPoint RX NAKed */ +# define USB_EPR_STATRX_VALID (3 << USB_EPR_STATRX_SHIFT) /* EndPoint RX VALID */ +# define USB_EPR_STATRX_DTOG1 (1 << USB_EPR_STATRX_SHIFT) /* EndPoint RX Data TOGgle bit1 */ +# define USB_EPR_STATRX_DTOG2 (2 << USB_EPR_STATRX_SHIFT) /* EndPoint RX Data TOGgle bit1 */ + +#define USB_EPR_DTOG_RX (1 << 14) /* Bit 14: Data Toggle, for reception transfers */ +#define USB_EPR_CTR_RX (1 << 15) /* Bit 15: Correct Transfer for reception */ + +/* USB control register */ + +#define USB_CNTR_FRES (1 << 0) /* Bit 0: Force USB Reset */ +#define USB_CNTR_PDWN (1 << 1) /* Bit 1: Power down */ +#define USB_CNTR_LPMODE (1 << 2) /* Bit 2: Low-power mode */ +#define USB_CNTR_FSUSP (1 << 3) /* Bit 3: Force suspend */ +#define USB_CNTR_RESUME (1 << 4) /* Bit 4: Resume request */ +#define USB_CNTR_ESOFM (1 << 8) /* Bit 8: Expected Start Of Frame Interrupt Mask */ +#define USB_CNTR_SOFM (1 << 9) /* Bit 9: Start Of Frame Interrupt Mask */ +#define USB_CNTR_RESETM (1 << 10) /* Bit 10: USB Reset Interrupt Mask */ +#define USB_CNTR_SUSPM (1 << 11) /* Bit 11: Suspend mode Interrupt Mask */ +#define USB_CNTR_WKUPM (1 << 12) /* Bit 12: Wakeup Interrupt Mask */ +#define USB_CNTR_ERRM (1 << 13) /* Bit 13: Error Interrupt Mask */ +#define USB_CNTR_DMAOVRNM (1 << 14) /* Bit 14: Packet Memory Area Over / Underrun Interrupt Mask */ +#define USB_CNTR_CTRM (1 << 15) /* Bit 15: Correct Transfer Interrupt Mask */ + +#define USB_CNTR_ALLINTS (USB_CNTR_ESOFM|USB_CNTR_SOFM|USB_CNTR_RESETM|USB_CNTR_SUSPM|\ + USB_CNTR_WKUPM|USB_CNTR_ERRM|USB_CNTR_DMAOVRNM|USB_CNTR_CTRM) + +/* USB interrupt status register */ + +#define USB_ISTR_EPID_SHIFT (0) /* Bits 3-0: Endpoint Identifier */ +#define USB_ISTR_EPID_MASK (0x0f << USB_ISTR_EPID_SHIFT) +#define USB_ISTR_DIR (1 << 4) /* Bit 4: Direction of transaction */ +#define USB_ISTR_ESOF (1 << 8) /* Bit 8: Expected Start Of Frame */ +#define USB_ISTR_SOF (1 << 9) /* Bit 9: Start Of Frame */ +#define USB_ISTR_RESET (1 << 10) /* Bit 10: USB RESET request */ +#define USB_ISTR_SUSP (1 << 11) /* Bit 11: Suspend mode request */ +#define USB_ISTR_WKUP (1 << 12) /* Bit 12: Wake up */ +#define USB_ISTR_ERR (1 << 13) /* Bit 13: Error */ +#define USB_ISTR_DMAOVRN (1 << 14) /* Bit 14: Packet Memory Area Over / Underrun */ +#define USB_ISTR_CTR (1 << 15) /* Bit 15: Correct Transfer */ + +#define USB_ISTR_ALLINTS (USB_ISTR_ESOF|USB_ISTR_SOF|USB_ISTR_RESET|USB_ISTR_SUSP|\ + USB_ISTR_WKUP|USB_ISTR_ERR|USB_ISTR_DMAOVRN|USB_ISTR_CTR) + +/* USB frame number register */ + +#define USB_FNR_FN_SHIFT (0) /* Bits 10-0: Frame Number */ +#define USB_FNR_FN_MASK (0x07ff << USB_FNR_FN_SHIFT) +#define USB_FNR_LSOF_SHIFT (11) /* Bits 12-11: Lost SOF */ +#define USB_FNR_LSOF_MASK (3 << USB_FNR_LSOF_SHIFT) +#define USB_FNR_LCK (1 << 13) /* Bit 13: Locked */ +#define USB_FNR_RXDM (1 << 14) /* Bit 14: Receive Data - Line Status */ +#define USB_FNR_RXDP (1 << 15) /* Bit 15: Receive Data + Line Status */ + +/* USB device address */ + +#define USB_DADDR_ADD_SHIFT (0) /* Bits 6-0: Device Address */ +#define USB_DADDR_ADD_MASK (0x7f << USB_DADDR_ADD_SHIFT) +#define USB_DADDR_EF (1 << 7) /* Bit 7: Enable Function */ + +/* Buffer table address */ + +#define USB_BTABLE_SHIFT (3) /* Bits 15:3: Buffer Table */ +#define USB_BTABLE_MASK (0x1fff << USB_BTABLE_SHIFT) + +/* Transmission buffer address */ + +#define USB_ADDR_TX_ZERO (1 << 0) /* Bit 0 Must always be written as ‘0’ */ +#define USB_ADDR_TX_SHIFT (1) /* Bits 15-1: Transmission Buffer Address */ +#define USB_ADDR_TX_MASK (0x7fff << USB_ADDR_ADDR_TX_SHIFT) + +/* Transmission byte count */ + +#define USB_COUNT_TX_SHIFT (0) /* Bits 9-0: Transmission Byte Count */ +#define USB_COUNT_TX_MASK (0x03ff << USB_COUNT_COUNT_TX_SHIFT) + +/* Reception buffer address */ + +#define USB_ADDR_RX_ZERO (1 << 0) /* Bit 0 This bit must always be written as ‘0’ */ +#define USB_ADDR_RX_SHIFT (1) /* Bits 15:1 ADDRn_RX[15:1]: Reception Buffer Address */ +#define USB_ADDR_RX_MASK (0x7fff << USB_ADDR_RX_SHIFT) + +/* Reception byte count */ + +#define USB_COUNT_RX_BL_SIZE (1 << 15) /* Bit 15: BLock SIZE. */ +#define USB_COUNT_RX_NUM_BLOCK_SHIFT (10) /* Bits 14-10: Number of blocks */ +#define USB_COUNT_RX_NUM_BLOCK_MASK (0x1f << USB_COUNT_RX_NUM_BLOCK_SHIFT) +#define USB_COUNT_RX_SHIFT (0) /* Bits 9-0: Reception Byte Count */ +#define USB_COUNT_RX_MASK (0x03ff << USB_COUNT_RX_SHIFT) + +#endif /* CONFIG_STM32_STM32F10XX || CONFIG_STM32_STM32F30XX || CONFIG_STM32_STM32F37XX */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_USBDEV_V1_H */ diff --git a/arch/arm/src/common/stm32/hardware/stm32_usbfs.h b/arch/arm/src/common/stm32/hardware/stm32_usbfs.h new file mode 100644 index 0000000000000..cd0fc28018445 --- /dev/null +++ b/arch/arm/src/common/stm32/hardware/stm32_usbfs.h @@ -0,0 +1,250 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/hardware/stm32_usbfs.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_USBFS_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_USBFS_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include "chip.h" + +#if defined(CONFIG_STM32_USBFS) + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Register Offsets *********************************************************/ + +/* Endpoint Registers */ + +#define STM32_USB_EPR_OFFSET(n) ((n) << 2) /* USB endpoint n register (16-bits) */ + +#define STM32_USB_EP0R_OFFSET 0x0000 /* USB endpoint 0 register (16-bits) */ +#define STM32_USB_EP1R_OFFSET 0x0004 /* USB endpoint 1 register (16-bits) */ +#define STM32_USB_EP2R_OFFSET 0x0008 /* USB endpoint 2 register (16-bits) */ +#define STM32_USB_EP3R_OFFSET 0x000c /* USB endpoint 3 register (16-bits) */ +#define STM32_USB_EP4R_OFFSET 0x0010 /* USB endpoint 4 register (16-bits) */ +#define STM32_USB_EP5R_OFFSET 0x0014 /* USB endpoint 5 register (16-bits) */ +#define STM32_USB_EP6R_OFFSET 0x0018 /* USB endpoint 6 register (16-bits) */ +#define STM32_USB_EP7R_OFFSET 0x001c /* USB endpoint 7 register (16-bits) */ + +/* Common Registers */ + +#define STM32_USB_CNTR_OFFSET 0x0040 /* USB control register (16-bits) */ +#define STM32_USB_ISTR_OFFSET 0x0044 /* USB interrupt status register (16-bits) */ +#define STM32_USB_FNR_OFFSET 0x0048 /* USB frame number register (16-bits) */ +#define STM32_USB_DADDR_OFFSET 0x004c /* USB device address (16-bits) */ +#define STM32_USB_BTABLE_OFFSET 0x0050 /* Buffer table address (16-bits) */ +#define STM32_USB_LPMCSR_OFFSET 0x0054 /* LPM control and status register */ +#define STM32_USB_BCDR_OFFSET 0x0058 /* Battery charging detector */ + +/* Buffer Descriptor Table (Relatative to BTABLE address) */ + +#define STM32_USB_ADDR_TX_WOFFSET (0) /* Transmission buffer address n (16-bits) */ +#define STM32_USB_COUNT_TX_WOFFSET (2) /* Transmission byte count n (16-bits) */ +#define STM32_USB_ADDR_RX_WOFFSET (4) /* Reception buffer address n (16-bits) */ +#define STM32_USB_COUNT_RX_WOFFSET (6) /* Reception byte count n (16-bits) */ + +#define STM32_USB_BTABLE_RADDR(ep,o) (((uint32_t)getreg16(STM32_USB_BTABLE) + ((ep) << 3)) + (o)) +#define STM32_USB_ADDR_TX_OFFSET(ep) STM32_USB_BTABLE_RADDR(ep,STM32_USB_ADDR_TX_WOFFSET) +#define STM32_USB_COUNT_TX_OFFSET(ep) STM32_USB_BTABLE_RADDR(ep,STM32_USB_COUNT_TX_WOFFSET) +#define STM32_USB_ADDR_RX_OFFSET(ep) STM32_USB_BTABLE_RADDR(ep,STM32_USB_ADDR_RX_WOFFSET) +#define STM32_USB_COUNT_RX_OFFSET(ep) STM32_USB_BTABLE_RADDR(ep,STM32_USB_COUNT_RX_WOFFSET) + +/* Register Addresses *******************************************************/ + +/* Endpoint Registers */ + +#define STM32_USB_EPR(n) (STM32_USB_BASE+STM32_USB_EPR_OFFSET(n)) +#define STM32_USB_EP0R (STM32_USB_BASE+STM32_USB_EP0R_OFFSET) +#define STM32_USB_EP1R (STM32_USB_BASE+STM32_USB_EP1R_OFFSET) +#define STM32_USB_EP2R (STM32_USB_BASE+STM32_USB_EP2R_OFFSET) +#define STM32_USB_EP3R (STM32_USB_BASE+STM32_USB_EP3R_OFFSET) +#define STM32_USB_EP4R (STM32_USB_BASE+STM32_USB_EP4R_OFFSET) +#define STM32_USB_EP5R (STM32_USB_BASE+STM32_USB_EP5R_OFFSET) +#define STM32_USB_EP6R (STM32_USB_BASE+STM32_USB_EP6R_OFFSET) +#define STM32_USB_EP7R (STM32_USB_BASE+STM32_USB_EP7R_OFFSET) + +/* Common Registers */ + +#define STM32_USB_CNTR (STM32_USB_BASE+STM32_USB_CNTR_OFFSET) +#define STM32_USB_ISTR (STM32_USB_BASE+STM32_USB_ISTR_OFFSET) +#define STM32_USB_FNR (STM32_USB_BASE+STM32_USB_FNR_OFFSET) +#define STM32_USB_DADDR (STM32_USB_BASE+STM32_USB_DADDR_OFFSET) +#define STM32_USB_BTABLE (STM32_USB_BASE+STM32_USB_BTABLE_OFFSET) +#define STM32_USB_LPMCSR (STM32_USB_BASE+STM32_USB_LPMCSR_OFFSET) +#define STM32_USB_BCDR (STM32_USB_BASE+STM32_USB_BCDR_OFFSET) + +/* Buffer Descriptor Table (Relatative to BTABLE address) */ + +#define STM32_USB_BTABLE_ADDR(ep,o) (STM32_USBRAM_BASE+STM32_USB_BTABLE_RADDR(ep,o)) +#define STM32_USB_ADDR_TX(ep) STM32_USB_BTABLE_ADDR(ep,STM32_USB_ADDR_TX_WOFFSET) +#define STM32_USB_COUNT_TX(ep) STM32_USB_BTABLE_ADDR(ep,STM32_USB_COUNT_TX_WOFFSET) +#define STM32_USB_ADDR_RX(ep) STM32_USB_BTABLE_ADDR(ep,STM32_USB_ADDR_RX_WOFFSET) +#define STM32_USB_COUNT_RX(ep) STM32_USB_BTABLE_ADDR(ep,STM32_USB_COUNT_RX_WOFFSET) + +/* Register Bitfield Definitions ********************************************/ + +/* USB endpoint register */ + +#define USB_EPR_EA_SHIFT (0) /* Bits 3:0 [3:0]: Endpoint Address */ +#define USB_EPR_EA_MASK (0X0f << USB_EPR_EA_SHIFT) +#define USB_EPR_STATTX_SHIFT (4) /* Bits 5-4: Status bits, for transmission transfers */ +#define USB_EPR_STATTX_MASK (3 << USB_EPR_STATTX_SHIFT) +# define USB_EPR_STATTX_DIS (0 << USB_EPR_STATTX_SHIFT) /* EndPoint TX DISabled */ +# define USB_EPR_STATTX_STALL (1 << USB_EPR_STATTX_SHIFT) /* EndPoint TX STALLed */ +# define USB_EPR_STATTX_NAK (2 << USB_EPR_STATTX_SHIFT) /* EndPoint TX NAKed */ +# define USB_EPR_STATTX_VALID (3 << USB_EPR_STATTX_SHIFT) /* EndPoint TX VALID */ +# define USB_EPR_STATTX_DTOG1 (1 << USB_EPR_STATTX_SHIFT) /* EndPoint TX Data Toggle bit1 */ +# define USB_EPR_STATTX_DTOG2 (2 << USB_EPR_STATTX_SHIFT) /* EndPoint TX Data Toggle bit2 */ + +#define USB_EPR_DTOG_TX (1 << 6) /* Bit 6: Data Toggle, for transmission transfers */ +#define USB_EPR_CTR_TX (1 << 7) /* Bit 7: Correct Transfer for transmission */ +#define USB_EPR_EP_KIND (1 << 8) /* Bit 8: Endpoint Kind */ +#define USB_EPR_EPTYPE_SHIFT (9) /* Bits 10-9: Endpoint type */ +#define USB_EPR_EPTYPE_MASK (3 << USB_EPR_EPTYPE_SHIFT) +# define USB_EPR_EPTYPE_BULK (0 << USB_EPR_EPTYPE_SHIFT) /* EndPoint BULK */ +# define USB_EPR_EPTYPE_CONTROL (1 << USB_EPR_EPTYPE_SHIFT) /* EndPoint CONTROL */ +# define USB_EPR_EPTYPE_ISOC (2 << USB_EPR_EPTYPE_SHIFT) /* EndPoint ISOCHRONOUS */ +# define USB_EPR_EPTYPE_INTERRUPT (3 << USB_EPR_EPTYPE_SHIFT) /* EndPoint INTERRUPT */ + +#define USB_EPR_SETUP (1 << 11) /* Bit 11: Setup transaction completed */ +#define USB_EPR_STATRX_SHIFT (12) /* Bits 13-12: Status bits, for reception transfers */ +#define USB_EPR_STATRX_MASK (3 << USB_EPR_STATRX_SHIFT) +# define USB_EPR_STATRX_DIS (0 << USB_EPR_STATRX_SHIFT) /* EndPoint RX DISabled */ +# define USB_EPR_STATRX_STALL (1 << USB_EPR_STATRX_SHIFT) /* EndPoint RX STALLed */ +# define USB_EPR_STATRX_NAK (2 << USB_EPR_STATRX_SHIFT) /* EndPoint RX NAKed */ +# define USB_EPR_STATRX_VALID (3 << USB_EPR_STATRX_SHIFT) /* EndPoint RX VALID */ +# define USB_EPR_STATRX_DTOG1 (1 << USB_EPR_STATRX_SHIFT) /* EndPoint RX Data TOGgle bit1 */ +# define USB_EPR_STATRX_DTOG2 (2 << USB_EPR_STATRX_SHIFT) /* EndPoint RX Data TOGgle bit1 */ + +#define USB_EPR_DTOG_RX (1 << 14) /* Bit 14: Data Toggle, for reception transfers */ +#define USB_EPR_CTR_RX (1 << 15) /* Bit 15: Correct Transfer for reception */ + +/* USB control register */ + +#define USB_CNTR_FRES (1 << 0) /* Bit 0: Force USB Reset */ +#define USB_CNTR_PDWN (1 << 1) /* Bit 1: Power down */ +#define USB_CNTR_LPMODE (1 << 2) /* Bit 2: Low-power mode */ +#define USB_CNTR_FSUSP (1 << 3) /* Bit 3: Force suspend */ +#define USB_CNTR_RESUME (1 << 4) /* Bit 4: Resume request */ +#define USB_CNTR_ESOFM (1 << 8) /* Bit 8: Expected Start Of Frame Interrupt Mask */ +#define USB_CNTR_SOFM (1 << 9) /* Bit 9: Start Of Frame Interrupt Mask */ +#define USB_CNTR_RESETM (1 << 10) /* Bit 10: USB Reset Interrupt Mask */ +#define USB_CNTR_SUSPM (1 << 11) /* Bit 11: Suspend mode Interrupt Mask */ +#define USB_CNTR_WKUPM (1 << 12) /* Bit 12: Wakeup Interrupt Mask */ +#define USB_CNTR_ERRM (1 << 13) /* Bit 13: Error Interrupt Mask */ +#define USB_CNTR_DMAOVRNM (1 << 14) /* Bit 14: Packet Memory Area Over / Underrun Interrupt Mask */ +#define USB_CNTR_CTRM (1 << 15) /* Bit 15: Correct Transfer Interrupt Mask */ + +#define USB_CNTR_ALLINTS (USB_CNTR_ESOFM|USB_CNTR_SOFM|USB_CNTR_RESETM|USB_CNTR_SUSPM|\ + USB_CNTR_WKUPM|USB_CNTR_ERRM|USB_CNTR_DMAOVRNM|USB_CNTR_CTRM) + +/* USB interrupt status register */ + +#define USB_ISTR_EPID_SHIFT (0) /* Bits 3-0: Endpoint Identifier */ +#define USB_ISTR_EPID_MASK (0x0f << USB_ISTR_EPID_SHIFT) +#define USB_ISTR_DIR (1 << 4) /* Bit 4: Direction of transaction */ +#define USB_ISTR_ESOF (1 << 8) /* Bit 8: Expected Start Of Frame */ +#define USB_ISTR_SOF (1 << 9) /* Bit 9: Start Of Frame */ +#define USB_ISTR_RESET (1 << 10) /* Bit 10: USB RESET request */ +#define USB_ISTR_SUSP (1 << 11) /* Bit 11: Suspend mode request */ +#define USB_ISTR_WKUP (1 << 12) /* Bit 12: Wake up */ +#define USB_ISTR_ERR (1 << 13) /* Bit 13: Error */ +#define USB_ISTR_DMAOVRN (1 << 14) /* Bit 14: Packet Memory Area Over / Underrun */ +#define USB_ISTR_CTR (1 << 15) /* Bit 15: Correct Transfer */ + +#define USB_ISTR_ALLINTS (USB_ISTR_ESOF|USB_ISTR_SOF|USB_ISTR_RESET|USB_ISTR_SUSP|\ + USB_ISTR_WKUP|USB_ISTR_ERR|USB_ISTR_DMAOVRN|USB_ISTR_CTR) + +/* USB frame number register */ + +#define USB_FNR_FN_SHIFT (0) /* Bits 10-0: Frame Number */ +#define USB_FNR_FN_MASK (0x07ff << USB_FNR_FN_SHIFT) +#define USB_FNR_LSOF_SHIFT (11) /* Bits 12-11: Lost SOF */ +#define USB_FNR_LSOF_MASK (3 << USB_FNR_LSOF_SHIFT) +#define USB_FNR_LCK (1 << 13) /* Bit 13: Locked */ +#define USB_FNR_RXDM (1 << 14) /* Bit 14: Receive Data - Line Status */ +#define USB_FNR_RXDP (1 << 15) /* Bit 15: Receive Data + Line Status */ + +/* USB device address */ + +#define USB_DADDR_ADD_SHIFT (0) /* Bits 6-0: Device Address */ +#define USB_DADDR_ADD_MASK (0x7f << USB_DADDR_ADD_SHIFT) +#define USB_DADDR_EF (1 << 7) /* Bit 7: Enable Function */ + +/* Buffer table address */ + +#define USB_BTABLE_SHIFT (3) /* Bits 15:3: Buffer Table */ +#define USB_BTABLE_MASK (0x1fff << USB_BTABLE_SHIFT) + +/* Transmission buffer address */ + +#define USB_ADDR_TX_ZERO (1 << 0) /* Bit 0 Must always be written as ‘0’ */ +#define USB_ADDR_TX_SHIFT (1) /* Bits 15-1: Transmission Buffer Address */ +#define USB_ADDR_TX_MASK (0x7fff << USB_ADDR_ADDR_TX_SHIFT) + +/* Transmission byte count */ + +#define USB_COUNT_TX_SHIFT (0) /* Bits 9-0: Transmission Byte Count */ +#define USB_COUNT_TX_MASK (0x03ff << USB_COUNT_COUNT_TX_SHIFT) + +/* Reception buffer address */ + +#define USB_ADDR_RX_ZERO (1 << 0) /* Bit 0 This bit must always be written as ‘0’ */ +#define USB_ADDR_RX_SHIFT (1) /* Bits 15:1 ADDRn_RX[15:1]: Reception Buffer Address */ +#define USB_ADDR_RX_MASK (0x7fff << USB_ADDR_RX_SHIFT) + +/* Reception byte count */ + +#define USB_COUNT_RX_BL_SIZE (1 << 15) /* Bit 15: BLock SIZE. */ +#define USB_COUNT_RX_NUM_BLOCK_SHIFT (10) /* Bits 14-10: Number of blocks */ +#define USB_COUNT_RX_NUM_BLOCK_MASK (0x1f << USB_COUNT_RX_NUM_BLOCK_SHIFT) +#define USB_COUNT_RX_SHIFT (0) /* Bits 9-0: Reception Byte Count */ +#define USB_COUNT_RX_MASK (0x03ff << USB_COUNT_RX_SHIFT) + +/* LPM control and status register */ + +#define USB_LPMCSR_LPMEN (1 << 0) /* Bit 0: LPM support enable */ +#define USB_LPMCSR_LPMACK (1 << 1) /* Bit 1: LPM Token acknowledge enable */ +#define USB_LPMCSR_REMWAKE (1 << 3) /* Bit 3: bRemoteWake value */ +#define USB_LPMCSR_BESL_SHIFT (4) /* Bits 7-4: BESL value */ +#define USB_LPMCSR_BESL_MASK (0x0f << USB_LPMCSR_BESL_SHIFT) + +/* Battery charging detector */ + +#define USB_BCDR_BCDEN (1 << 0) /* Bit 0: Battery charging detector (BCD) enable */ +#define USB_BCDR_DCDEN (1 << 1) /* Bit 1: Data contact detection (DCD) mode enable */ +#define USB_BCDR_PDEN (1 << 2) /* Bit 2: Primary detection (PD) mode enable */ +#define USB_BCDR_SDEN (1 << 3) /* Bit 3: Secondary detection (SD) mode enable */ +#define USB_BCDR_DCDET (1 << 4) /* Bit 4: Data contact detection (DCD) status */ +#define USB_BCDR_PDET (1 << 5) /* Bit 5: Primary detection (PD) status */ +#define USB_BCDR_SDET (1 << 6) /* Bit 6: Secondary detection (SD) status */ +#define USB_BCDR_PS2DET (1 << 7) /* Bit 7: DM pull-up detection status */ +#define USB_BCDR_DPPU (1 << 15) /* Bit 15: DP pull-up control */ + +#endif /* CONFIG_STM32_USBFS */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_USBFS_H */ diff --git a/arch/arm/src/common/stm32/hardware/stm32_wdg.h b/arch/arm/src/common/stm32/hardware/stm32_wdg.h new file mode 100644 index 0000000000000..2a24642f30780 --- /dev/null +++ b/arch/arm/src/common/stm32/hardware/stm32_wdg.h @@ -0,0 +1,43 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/hardware/stm32_wdg.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_WDG_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_WDG_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#if (defined(CONFIG_STM32_HAVE_IP_WDG_M0_V1) + \ + defined(CONFIG_STM32_HAVE_IP_WDG_M3M4_V1)) > 1 +# error Only one STM32 WDG IP version must be selected +#endif + +#if defined(CONFIG_STM32_HAVE_IP_WDG_M0_V1) +# include "hardware/stm32_wdg_m0.h" +#elif defined(CONFIG_STM32_HAVE_IP_WDG_M3M4_V1) +# include "hardware/stm32_wdg_v1v2.h" +#else +# error "Unsupported STM32 WDG" +#endif + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_WDG_H */ diff --git a/arch/arm/src/common/stm32/hardware/stm32_wdg_m0.h b/arch/arm/src/common/stm32/hardware/stm32_wdg_m0.h new file mode 100644 index 0000000000000..eb366fccc3706 --- /dev/null +++ b/arch/arm/src/common/stm32/hardware/stm32_wdg_m0.h @@ -0,0 +1,141 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/hardware/stm32_wdg_m0.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_WDG_M0_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_WDG_M0_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "chip.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Register Offsets *********************************************************/ + +#define STM32_IWDG_KR_OFFSET 0x0000 /* Key register (32-bit) */ +#define STM32_IWDG_PR_OFFSET 0x0004 /* Prescaler register (32-bit) */ +#define STM32_IWDG_RLR_OFFSET 0x0008 /* Reload register (32-bit) */ +#define STM32_IWDG_SR_OFFSET 0x000c /* Status register (32-bit) */ +#define STM32_IWDG_WINR_OFFSET 0x000c /* Window register (32-bit) */ + +#define STM32_WWDG_CR_OFFSET 0x0000 /* Control Register (32-bit) */ +#define STM32_WWDG_CFR_OFFSET 0x0004 /* Configuration register (32-bit) */ +#define STM32_WWDG_SR_OFFSET 0x0008 /* Status register (32-bit) */ + +/* Register Addresses *******************************************************/ + +#define STM32_IWDG_KR (STM32_IWDG_BASE+STM32_IWDG_KR_OFFSET) +#define STM32_IWDG_PR (STM32_IWDG_BASE+STM32_IWDG_PR_OFFSET) +#define STM32_IWDG_RLR (STM32_IWDG_BASE+STM32_IWDG_RLR_OFFSET) +#define STM32_IWDG_SR (STM32_IWDG_BASE+STM32_IWDG_SR_OFFSET) +#define STM32_IWDG_WINR (STM32_IWDG_BASE+STM32_IWDG_WINR_OFFSET) + +#define STM32_WWDG_CR (STM32_WWDG_BASE+STM32_WWDG_CR_OFFSET) +#define STM32_WWDG_CFR (STM32_WWDG_BASE+STM32_WWDG_CFR_OFFSET) +#define STM32_WWDG_SR (STM32_WWDG_BASE+STM32_WWDG_SR_OFFSET) + +/* Register Bitfield Definitions ********************************************/ + +/* Key register (32-bit) */ + +#define IWDG_KR_KEY_SHIFT (0) /* Bits 15-0: Key value (write only, read 0000h) */ +#define IWDG_KR_KEY_MASK (0xffff << IWDG_KR_KEY_SHIFT) + +#define IWDG_KR_KEY_ENABLE (0x5555) /* Enable register access */ +#define IWDG_KR_KEY_DISABLE (0x0000) /* Disable register access */ +#define IWDG_KR_KEY_RELOAD (0xaaaa) /* Reload the counter */ +#define IWDG_KR_KEY_START (0xcccc) /* Start the watchdog */ + +/* Prescaler register (32-bit) */ + +#define IWDG_PR_SHIFT (0) /* Bits 2-0: Prescaler divider */ +#define IWDG_PR_MASK (7 << IWDG_PR_SHIFT) +# define IWDG_PR_DIV4 (0 << IWDG_PR_SHIFT) /* 000: divider /4 */ +# define IWDG_PR_DIV8 (1 << IWDG_PR_SHIFT) /* 001: divider /8 */ +# define IWDG_PR_DIV16 (2 << IWDG_PR_SHIFT) /* 010: divider /16 */ +# define IWDG_PR_DIV32 (3 << IWDG_PR_SHIFT) /* 011: divider /32 */ +# define IWDG_PR_DIV64 (4 << IWDG_PR_SHIFT) /* 100: divider /64 */ +# define IWDG_PR_DIV128 (5 << IWDG_PR_SHIFT) /* 101: divider /128 */ +# define IWDG_PR_DIV256 (6 << IWDG_PR_SHIFT) /* 11x: divider /256 */ + +/* Reload register (32-bit) */ + +#define IWDG_RLR_RL_SHIFT (0) /* Bits11:0 RL[11:0]: Watchdog counter reload value */ +#define IWDG_RLR_RL_MASK (0x0fff << IWDG_RLR_RL_SHIFT) + +#define IWDG_RLR_MAX (0xfff) + +/* Status register (32-bit) */ + +#define IWDG_SR_PVU (1 << 0) /* Bit 0: Watchdog prescaler value update */ +#define IWDG_SR_RVU (1 << 1) /* Bit 1: Watchdog counter reload value update */ +#define IWDG_SR_WVU (1 << 2) /* Bit 2: */ + +/* Window register (32-bit) */ + +#define IWDG_WINR_SHIFT (0) +#define IWDG_WINR_MASK (0x0fff << IWDG_WINR_SHIFT) + +/* Control Register (32-bit) */ + +#define WWDG_CR_T_SHIFT (0) /* Bits 6:0 T[6:0]: 7-bit counter (MSB to LSB) */ +#define WWDG_CR_T_MASK (0x7f << WWDG_CR_T_SHIFT) +# define WWDG_CR_T_MAX (0x3f << WWDG_CR_T_SHIFT) +# define WWDG_CR_T_RESET (0x40 << WWDG_CR_T_SHIFT) +#define WWDG_CR_WDGA (1 << 7) /* Bit 7: Activation bit */ + +/* Configuration register (32-bit) */ + +#define WWDG_CFR_W_SHIFT (0) /* Bits 6:0 W[6:0] 7-bit window value */ +#define WWDG_CFR_W_MASK (0x7f << WWDG_CFR_W_SHIFT) +#define WWDG_CFR_WDGTB_SHIFT (7) /* Bits 8:7 [1:0]: Timer Base */ +#define WWDG_CFR_WDGTB_MASK (3 << WWDG_CFR_WDGTB_SHIFT) +# define WWDG_CFR_PCLK1 (0 << WWDG_CFR_WDGTB_SHIFT) /* 00: CK Counter Clock (PCLK1 div 4096) div 1 */ +# define WWDG_CFR_PCLK1d2 (1 << WWDG_CFR_WDGTB_SHIFT) /* 01: CK Counter Clock (PCLK1 div 4096) div 2 */ +# define WWDG_CFR_PCLK1d4 (2 << WWDG_CFR_WDGTB_SHIFT) /* 10: CK Counter Clock (PCLK1 div 4096) div 4 */ +# define WWDG_CFR_PCLK1d8 (3 << WWDG_CFR_WDGTB_SHIFT) /* 11: CK Counter Clock (PCLK1 div 4096) div 8 */ + +#define WWDG_CFR_EWI (1 << 9) /* Bit 9: Early Wakeup Interrupt */ + +/* Status register (32-bit) */ + +#define WWDG_SR_EWIF (1 << 0) /* Bit 0: Early Wakeup Interrupt Flag */ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_WDG_M0_H */ diff --git a/arch/arm/src/common/stm32/hardware/stm32_wdg_v1v2.h b/arch/arm/src/common/stm32/hardware/stm32_wdg_v1v2.h new file mode 100644 index 0000000000000..8febf5740cb0f --- /dev/null +++ b/arch/arm/src/common/stm32/hardware/stm32_wdg_v1v2.h @@ -0,0 +1,150 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/hardware/stm32_wdg_v1v2.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_WDG_V1V2_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_WDG_V1V2_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "chip.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Register Offsets *********************************************************/ + +#define STM32_IWDG_KR_OFFSET 0x0000 /* Key register (32-bit) */ +#define STM32_IWDG_PR_OFFSET 0x0004 /* Prescaler register (32-bit) */ +#define STM32_IWDG_RLR_OFFSET 0x0008 /* Reload register (32-bit) */ +#define STM32_IWDG_SR_OFFSET 0x000c /* Status register (32-bit) */ +#if defined(CONFIG_STM32_STM32F30XX) +# define STM32_IWDG_WINR_OFFSET 0x000c /* Window register (32-bit) */ +#endif + +#define STM32_WWDG_CR_OFFSET 0x0000 /* Control Register (32-bit) */ +#define STM32_WWDG_CFR_OFFSET 0x0004 /* Configuration register (32-bit) */ +#define STM32_WWDG_SR_OFFSET 0x0008 /* Status register (32-bit) */ + +/* Register Addresses *******************************************************/ + +#define STM32_IWDG_KR (STM32_IWDG_BASE+STM32_IWDG_KR_OFFSET) +#define STM32_IWDG_PR (STM32_IWDG_BASE+STM32_IWDG_PR_OFFSET) +#define STM32_IWDG_RLR (STM32_IWDG_BASE+STM32_IWDG_RLR_OFFSET) +#define STM32_IWDG_SR (STM32_IWDG_BASE+STM32_IWDG_SR_OFFSET) +#if defined(CONFIG_STM32_STM32F30XX) +# define STM32_IWDG_WINR (STM32_IWDG_BASE+STM32_IWDG_WINR_OFFSET) +#endif + +#define STM32_WWDG_CR (STM32_WWDG_BASE+STM32_WWDG_CR_OFFSET) +#define STM32_WWDG_CFR (STM32_WWDG_BASE+STM32_WWDG_CFR_OFFSET) +#define STM32_WWDG_SR (STM32_WWDG_BASE+STM32_WWDG_SR_OFFSET) + +/* Register Bitfield Definitions ********************************************/ + +/* Key register (32-bit) */ + +#define IWDG_KR_KEY_SHIFT (0) /* Bits 15-0: Key value (write only, read 0000h) */ +#define IWDG_KR_KEY_MASK (0xffff << IWDG_KR_KEY_SHIFT) + +#define IWDG_KR_KEY_ENABLE (0x5555) /* Enable register access */ +#define IWDG_KR_KEY_DISABLE (0x0000) /* Disable register access */ +#define IWDG_KR_KEY_RELOAD (0xaaaa) /* Reload the counter */ +#define IWDG_KR_KEY_START (0xcccc) /* Start the watchdog */ + +/* Prescaler register (32-bit) */ + +#define IWDG_PR_SHIFT (0) /* Bits 2-0: Prescaler divider */ +#define IWDG_PR_MASK (7 << IWDG_PR_SHIFT) +# define IWDG_PR_DIV4 (0 << IWDG_PR_SHIFT) /* 000: divider /4 */ +# define IWDG_PR_DIV8 (1 << IWDG_PR_SHIFT) /* 001: divider /8 */ +# define IWDG_PR_DIV16 (2 << IWDG_PR_SHIFT) /* 010: divider /16 */ +# define IWDG_PR_DIV32 (3 << IWDG_PR_SHIFT) /* 011: divider /32 */ +# define IWDG_PR_DIV64 (4 << IWDG_PR_SHIFT) /* 100: divider /64 */ +# define IWDG_PR_DIV128 (5 << IWDG_PR_SHIFT) /* 101: divider /128 */ +# define IWDG_PR_DIV256 (6 << IWDG_PR_SHIFT) /* 11x: divider /256 */ + +/* Reload register (32-bit) */ + +#define IWDG_RLR_RL_SHIFT (0) /* Bits11:0 RL[11:0]: Watchdog counter reload value */ +#define IWDG_RLR_RL_MASK (0x0fff << IWDG_RLR_RL_SHIFT) + +#define IWDG_RLR_MAX (0xfff) + +/* Status register (32-bit) */ + +#define IWDG_SR_PVU (1 << 0) /* Bit 0: Watchdog prescaler value update */ +#define IWDG_SR_RVU (1 << 1) /* Bit 1: Watchdog counter reload value update */ + +#if defined(CONFIG_STM32_STM32F30XX) +# define IWDG_SR_WVU (1 << 2) /* Bit 2: */ +#endif + +/* Window register (32-bit) */ + +#if defined(CONFIG_STM32_STM32F30XX) +# define IWDG_WINR_SHIFT (0) +# define IWDG_WINR_MASK (0x0fff << IWDG_WINR_SHIFT) +#endif + +/* Control Register (32-bit) */ + +#define WWDG_CR_T_SHIFT (0) /* Bits 6:0 T[6:0]: 7-bit counter (MSB to LSB) */ +#define WWDG_CR_T_MASK (0x7f << WWDG_CR_T_SHIFT) +# define WWDG_CR_T_MAX (0x3f << WWDG_CR_T_SHIFT) +# define WWDG_CR_T_RESET (0x40 << WWDG_CR_T_SHIFT) +#define WWDG_CR_WDGA (1 << 7) /* Bit 7: Activation bit */ + +/* Configuration register (32-bit) */ + +#define WWDG_CFR_W_SHIFT (0) /* Bits 6:0 W[6:0] 7-bit window value */ +#define WWDG_CFR_W_MASK (0x7f << WWDG_CFR_W_SHIFT) +#define WWDG_CFR_WDGTB_SHIFT (7) /* Bits 8:7 [1:0]: Timer Base */ +#define WWDG_CFR_WDGTB_MASK (3 << WWDG_CFR_WDGTB_SHIFT) +# define WWDG_CFR_PCLK1 (0 << WWDG_CFR_WDGTB_SHIFT) /* 00: CK Counter Clock (PCLK1 div 4096) div 1 */ +# define WWDG_CFR_PCLK1d2 (1 << WWDG_CFR_WDGTB_SHIFT) /* 01: CK Counter Clock (PCLK1 div 4096) div 2 */ +# define WWDG_CFR_PCLK1d4 (2 << WWDG_CFR_WDGTB_SHIFT) /* 10: CK Counter Clock (PCLK1 div 4096) div 4 */ +# define WWDG_CFR_PCLK1d8 (3 << WWDG_CFR_WDGTB_SHIFT) /* 11: CK Counter Clock (PCLK1 div 4096) div 8 */ + +#define WWDG_CFR_EWI (1 << 9) /* Bit 9: Early Wakeup Interrupt */ + +/* Status register (32-bit) */ + +#define WWDG_SR_EWIF (1 << 0) /* Bit 0: Early Wakeup Interrupt Flag */ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_WDG_V1V2_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32_wdt.h b/arch/arm/src/common/stm32/hardware/stm32_wdt.h similarity index 96% rename from arch/arm/src/stm32f0l0g0/hardware/stm32_wdt.h rename to arch/arm/src/common/stm32/hardware/stm32_wdt.h index 54c6a345b3aa6..d99695aa858f0 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32_wdt.h +++ b/arch/arm/src/common/stm32/hardware/stm32_wdt.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32_wdt.h + * arch/arm/src/common/stm32/hardware/stm32_wdt.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_WDG_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_WDG_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_WDT_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_WDT_H /**************************************************************************** * Included Files @@ -126,4 +126,4 @@ #define WWDG_SR_EWIF (1 << 0) /* Bit 0: Early Wakeup Interrupt Flag */ -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_WDG_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_WDT_H */ diff --git a/arch/arm/src/stm32/hardware/stm32fxxxxx_otgfs.h b/arch/arm/src/common/stm32/hardware/stm32fxxxxx_otgfs.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32fxxxxx_otgfs.h rename to arch/arm/src/common/stm32/hardware/stm32fxxxxx_otgfs.h index 199b4098af427..610531a01d818 100644 --- a/arch/arm/src/stm32/hardware/stm32fxxxxx_otgfs.h +++ b/arch/arm/src/common/stm32/hardware/stm32fxxxxx_otgfs.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32fxxxxx_otgfs.h + * arch/arm/src/common/stm32/hardware/stm32fxxxxx_otgfs.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32FXXXXX_OTGFS_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32FXXXXX_OTGFS_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32FXXXXX_OTGFS_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32FXXXXX_OTGFS_H /**************************************************************************** * Included Files @@ -1112,4 +1112,4 @@ #define OTGFS_PCGCCTL_PHYSUSP (1 << 4) /* Bit 4: PHY Suspended */ /* Bits 5-31: Reserved, must be kept at reset value */ -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32FXXXXX_OTGFS_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32FXXXXX_OTGFS_H */ diff --git a/arch/arm/src/stm32/hardware/stm32gxxxxx_dac.h b/arch/arm/src/common/stm32/hardware/stm32gxxxxx_dac.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32gxxxxx_dac.h rename to arch/arm/src/common/stm32/hardware/stm32gxxxxx_dac.h index 0b412885c978d..d48838484d9b7 100644 --- a/arch/arm/src/stm32/hardware/stm32gxxxxx_dac.h +++ b/arch/arm/src/common/stm32/hardware/stm32gxxxxx_dac.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32gxxxxx_dac.h + * arch/arm/src/common/stm32/hardware/stm32gxxxxx_dac.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32GXXXXX_DAC_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32GXXXXX_DAC_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32GXXXXX_DAC_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32GXXXXX_DAC_H /**************************************************************************** * Included Files @@ -522,4 +522,4 @@ #define DAC_STR_STINCDATA_SHIFT (16) /* DAC channel 1 Sawtooth increment value (12.4 bit format) */ #define DAC_STR_STINCDATA_MASK (0xffff << DAC_STR_STINCDATA_SHIFT) -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32GXXXXX_DAC_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32GXXXXX_DAC_H */ diff --git a/arch/arm/src/stm32/stm32_1wire.h b/arch/arm/src/common/stm32/stm32_1wire.h similarity index 92% rename from arch/arm/src/stm32/stm32_1wire.h rename to arch/arm/src/common/stm32/stm32_1wire.h index dbd2ed588d7c1..79f9f6d47e46f 100644 --- a/arch/arm/src/stm32/stm32_1wire.h +++ b/arch/arm/src/common/stm32/stm32_1wire.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_1wire.h + * arch/arm/src/common/stm32/stm32_1wire.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_STM32_1WIRE_H -#define __ARCH_ARM_SRC_STM32_STM32_1WIRE_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_1WIRE_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_1WIRE_H /**************************************************************************** * Included Files @@ -29,6 +29,8 @@ #include +#include + #include "stm32_uart.h" /**************************************************************************** @@ -71,4 +73,4 @@ struct onewire_dev_s *stm32_1wireinitialize(int port); int stm32_1wireuninitialize(struct onewire_dev_s *dev); -#endif /* __ARCH_ARM_SRC_STM32_STM32_1WIRE_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_1WIRE_H */ diff --git a/arch/arm/src/common/stm32/stm32_1wire_m3m4_v1.c b/arch/arm/src/common/stm32/stm32_1wire_m3m4_v1.c new file mode 100644 index 0000000000000..595136c6c65d0 --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_1wire_m3m4_v1.c @@ -0,0 +1,1293 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_1wire_m3m4_v1.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* Links: + * https://www.maximintegrated.com/en/app-notes/index.mvp/id/214 + */ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "arm_internal.h" +#include "stm32_rcc.h" +#include "stm32_1wire.h" +#include "stm32_rcc.h" + +#ifdef HAVE_1WIREDRIVER + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define BUS_TIMEOUT 5 /* tv_sec */ + +#define RESET_BAUD 9600 +#define RESET_TX 0xF0 +#define TIMESLOT_BAUD 115200 +#define READ_TX 0xFF +#define READ_RX1 0xFF +#define WRITE_TX0 0x00 +#define WRITE_TX1 0xFF + +#if defined(CONFIG_STM32_STM32F10XX) +# define PIN_OPENDRAIN(GPIO) ((GPIO) | GPIO_CNF_OUTOD) +#else +# define PIN_OPENDRAIN(GPIO) ((GPIO) | GPIO_OPENDRAIN) +#endif + +#if defined(CONFIG_STM32_STM32F10XX) +# define USART_CR3_ONEBIT (0) +#endif + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/* 1-Wire bus task */ + +enum stm32_1wire_msg_e +{ + ONEWIRETASK_NONE = 0, + ONEWIRETASK_RESET, + ONEWIRETASK_WRITE, + ONEWIRETASK_READ, + ONEWIRETASK_WRITEBIT, + ONEWIRETASK_READBIT +}; + +struct stm32_1wire_msg_s +{ + enum stm32_1wire_msg_e task; /* Task */ + uint8_t *buffer; /* Task buffer */ + int buflen; /* Buffer length */ +}; + +/* 1-Wire device hardware configuration */ + +struct stm32_1wire_config_s +{ + const uint32_t usartbase; /* Base address of USART registers */ + const uint32_t apbclock; /* PCLK 1 or 2 frequency */ + const uint32_t data_pin; /* GPIO configuration for DATA */ + const uint8_t irq; /* IRQ associated with this USART */ +}; + +/* 1-Wire device Private Data */ + +struct stm32_1wire_priv_s +{ + const struct stm32_1wire_config_s *config; /* Port configuration */ + volatile int refs; /* Reference count */ + mutex_t lock; /* Mutual exclusion mutex */ + sem_t sem_isr; /* Interrupt wait semaphore */ + int baud; /* Baud rate */ + const struct stm32_1wire_msg_s *msgs; /* Messages data */ + uint8_t *byte; /* Current byte */ + uint8_t bit; /* Current bit */ + volatile int result; /* Exchange result */ +}; + +/* 1-Wire device, Instance */ + +struct stm32_1wire_inst_s +{ + const struct onewire_ops_s *ops; /* Standard 1-Wire operations */ + struct stm32_1wire_priv_s *priv; /* Common driver private data structure */ +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +static inline uint32_t stm32_1wire_in(struct stm32_1wire_priv_s *priv, + int offset); +static inline void stm32_1wire_out(struct stm32_1wire_priv_s *priv, + int offset, uint32_t value); +static int stm32_1wire_recv(struct stm32_1wire_priv_s *priv); +static void stm32_1wire_send(struct stm32_1wire_priv_s *priv, int ch); +static void stm32_1wire_set_baud(struct stm32_1wire_priv_s *priv); +static void stm32_1wire_set_apb_clock(struct stm32_1wire_priv_s *priv, + bool on); +static int stm32_1wire_init(struct stm32_1wire_priv_s *priv); +static int stm32_1wire_deinit(struct stm32_1wire_priv_s *priv); +static int stm32_1wire_process(struct stm32_1wire_priv_s *priv, + const struct stm32_1wire_msg_s *msgs, + int count); +static int stm32_1wire_isr(int irq, void *context, void *arg); +static int stm32_1wire_reset(struct onewire_dev_s *dev); +static int stm32_1wire_write(struct onewire_dev_s *dev, + const uint8_t *buffer, int buflen); +static int stm32_1wire_read(struct onewire_dev_s *dev, uint8_t *buffer, + int buflen); +static int stm32_1wire_exchange(struct onewire_dev_s *dev, bool reset, + const uint8_t *txbuffer, int txbuflen, + uint8_t *rxbuffer, int rxbuflen); +static int stm32_1wire_writebit(struct onewire_dev_s *dev, + const uint8_t *bit); +static int stm32_1wire_readbit(struct onewire_dev_s *dev, uint8_t *bit); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* 1-Wire device structures */ + +#ifdef CONFIG_STM32_USART1_1WIREDRIVER + +static const struct stm32_1wire_config_s stm32_1wire1_config = +{ + .usartbase = STM32_USART1_BASE, + .apbclock = STM32_PCLK2_FREQUENCY, + .data_pin = PIN_OPENDRAIN(GPIO_USART1_TX), + .irq = STM32_IRQ_USART1, +}; + +static struct stm32_1wire_priv_s stm32_1wire1_priv = +{ + .config = &stm32_1wire1_config, + .refs = 0, + .lock = NXMUTEX_INITIALIZER, + .sem_isr = SEM_INITIALIZER(0), + .msgs = NULL +}; + +#endif + +#ifdef CONFIG_STM32_USART2_1WIREDRIVER + +static const struct stm32_1wire_config_s stm32_1wire2_config = +{ + .usartbase = STM32_USART2_BASE, + .apbclock = STM32_PCLK1_FREQUENCY, + .data_pin = PIN_OPENDRAIN(GPIO_USART2_TX), + .irq = STM32_IRQ_USART2, +}; + +static struct stm32_1wire_priv_s stm32_1wire2_priv = +{ + .config = &stm32_1wire2_config, + .refs = 0, + .lock = NXMUTEX_INITIALIZER, + .sem_isr = SEM_INITIALIZER(0), + .msgs = NULL +}; + +#endif + +#ifdef CONFIG_STM32_USART3_1WIREDRIVER + +static const struct stm32_1wire_config_s stm32_1wire3_config = +{ + .usartbase = STM32_USART3_BASE, + .apbclock = STM32_PCLK1_FREQUENCY, + .data_pin = PIN_OPENDRAIN(GPIO_USART3_TX), + .irq = STM32_IRQ_USART3, +}; + +static struct stm32_1wire_priv_s stm32_1wire3_priv = +{ + .config = &stm32_1wire3_config, + .refs = 0, + .lock = NXMUTEX_INITIALIZER, + .sem_isr = SEM_INITIALIZER(0), + .msgs = NULL +}; + +#endif + +#ifdef CONFIG_STM32_UART4_1WIREDRIVER + +static const struct stm32_1wire_config_s stm32_1wire4_config = +{ + .usartbase = STM32_UART4_BASE, + .apbclock = STM32_PCLK1_FREQUENCY, + .data_pin = PIN_OPENDRAIN(GPIO_UART4_TX), + .irq = STM32_IRQ_UART4, +}; + +static struct stm32_1wire_priv_s stm32_1wire4_priv = +{ + .config = &stm32_1wire4_config, + .refs = 0, + .lock = NXMUTEX_INITIALIZER, + .sem_isr = SEM_INITIALIZER(0), + .msgs = NULL +}; + +#endif + +#ifdef CONFIG_STM32_UART5_1WIREDRIVER + +static const struct stm32_1wire_config_s stm32_1wire5_config = +{ + .usartbase = STM32_UART5_BASE, + .apbclock = STM32_PCLK1_FREQUENCY, + .data_pin = PIN_OPENDRAIN(GPIO_UART5_TX), + .irq = STM32_IRQ_UART5, +}; + +static struct stm32_1wire_priv_s stm32_1wire5_priv = +{ + .config = &stm32_1wire5_config, + .refs = 0, + .lock = NXMUTEX_INITIALIZER, + .sem_isr = SEM_INITIALIZER(0), + .msgs = NULL +}; + +#endif + +#ifdef CONFIG_STM32_USART6_1WIREDRIVER + +static const struct stm32_1wire_config_s stm32_1wire6_config = +{ + .usartbase = STM32_USART6_BASE, + .apbclock = STM32_PCLK2_FREQUENCY, + .data_pin = PIN_OPENDRAIN(GPIO_USART6_TX), + .irq = STM32_IRQ_USART6, +}; + +static struct stm32_1wire_priv_s stm32_1wire6_priv = +{ + .config = &stm32_1wire6_config, + .refs = 0, + .lock = NXMUTEX_INITIALIZER, + .sem_isr = SEM_INITIALIZER(0), + .msgs = NULL +}; + +#endif + +#ifdef CONFIG_STM32_UART7_1WIREDRIVER + +static const struct stm32_1wire_config_s stm32_1wire7_config = +{ + .usartbase = STM32_UART7_BASE, + .apbclock = STM32_PCLK1_FREQUENCY, + .data_pin = PIN_OPENDRAIN(GPIO_UART7_TX), + .irq = STM32_IRQ_UART7, +}; + +static struct stm32_1wire_priv_s stm32_1wire7_priv = +{ + .config = &stm32_1wire7_config, + .refs = 0, + .lock = NXMUTEX_INITIALIZER, + .sem_isr = SEM_INITIALIZER(0), + .msgs = NULL +}; + +#endif + +#ifdef CONFIG_STM32_UART8_1WIREDRIVER + +static const struct stm32_1wire_config_s stm32_1wire8_config = +{ + .usartbase = STM32_UART8_BASE, + .apbclock = STM32_PCLK1_FREQUENCY, + .data_pin = PIN_OPENDRAIN(GPIO_UART8_TX), + .irq = STM32_IRQ_UART8, +}; + +static struct stm32_1wire_priv_s stm32_1wire8_priv = +{ + .config = &stm32_1wire8_config, + .refs = 0, + .lock = NXMUTEX_INITIALIZER, + .sem_isr = SEM_INITIALIZER(0), + .msgs = NULL +}; + +#endif + +/* Device Structures, Instantiation */ + +static const struct onewire_ops_s stm32_1wire_ops = +{ + .reset = stm32_1wire_reset, + .write = stm32_1wire_write, + .read = stm32_1wire_read, + .exchange = stm32_1wire_exchange, + .writebit = stm32_1wire_writebit, + .readbit = stm32_1wire_readbit +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_1wire_in + ****************************************************************************/ + +static inline uint32_t stm32_1wire_in(struct stm32_1wire_priv_s *priv, + int offset) +{ + return getreg32(priv->config->usartbase + offset); +} + +/**************************************************************************** + * Name: stm32_1wire_out + ****************************************************************************/ + +static inline void stm32_1wire_out(struct stm32_1wire_priv_s *priv, + int offset, uint32_t value) +{ + putreg32(value, priv->config->usartbase + offset); +} + +/**************************************************************************** + * Name: stm32_1wire_recv + * + * Description: + * This method will recv one byte on the USART + * + ****************************************************************************/ + +static int stm32_1wire_recv(struct stm32_1wire_priv_s *priv) +{ + return stm32_1wire_in(priv, STM32_USART_RDR_OFFSET) & 0xff; +} + +/**************************************************************************** + * Name: stm32_1wire_send + * + * Description: + * This method will send one byte on the USART + * + ****************************************************************************/ + +static void stm32_1wire_send(struct stm32_1wire_priv_s *priv, int ch) +{ + stm32_1wire_out(priv, STM32_USART_TDR_OFFSET, (uint32_t)(ch & 0xff)); +} + +/**************************************************************************** + * Name: stm32_1wire_set_baud + * + * Description: + * Set the serial line baud. + * + ****************************************************************************/ + +static void stm32_1wire_set_baud(struct stm32_1wire_priv_s *priv) +{ +#if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX) + /* This first implementation is for U[S]ARTs that support oversampling + * by 8 in additional to the standard oversampling by 16. + */ + + uint32_t usartdiv8; + uint32_t cr1; + uint32_t brr; + + /* In case of oversampling by 8, the equation is: + * + * baud = 2 * fCK / usartdiv8 + * usartdiv8 = 2 * fCK / baud + */ + + usartdiv8 = ((priv->config->apbclock << 1) + (priv->baud >> 1)) / + priv->baud; + + /* Baud rate for standard USART (SPI mode included): + * + * In case of oversampling by 16, the equation is: + * baud = fCK / usartdiv16 + * usartdiv16 = fCK / baud + * = 2 * usartdiv8 + */ + + /* Use oversamply by 8 only if the divisor is small. But what is small? */ + + cr1 = stm32_1wire_in(priv, STM32_USART_CR1_OFFSET); + if (usartdiv8 > 100) + { + /* Use usartdiv16 */ + + brr = (usartdiv8 + 1) >> 1; + + /* Clear oversampling by 8 to enable oversampling by 16 */ + + cr1 &= ~USART_CR1_OVER8; + } + else + { + DEBUGASSERT(usartdiv8 >= 8); + + /* Perform mysterious operations on bits 0-3 */ + + brr = ((usartdiv8 & 0xfff0) | ((usartdiv8 & 0x000f) >> 1)); + + /* Set oversampling by 8 */ + + cr1 |= USART_CR1_OVER8; + } + + stm32_1wire_out(priv, STM32_USART_CR1_OFFSET, cr1); + stm32_1wire_out(priv, STM32_USART_BRR_OFFSET, brr); + +#else + + /* This second implementation is for U[S]ARTs that support fractional + * dividers. + */ + + uint32_t usartdiv32; + uint32_t mantissa; + uint32_t fraction; + uint32_t brr; + + /* Configure the USART Baud Rate. The baud rate for the receiver and + * transmitter (Rx and Tx) are both set to the same value as programmed + * in the Mantissa and Fraction values of USARTDIV. + * + * baud = fCK / (16 * usartdiv) + * usartdiv = fCK / (16 * baud) + * + * Where fCK is the input clock to the peripheral (PCLK1 for USART2, 3, 4, + * 5 or PCLK2 for USART1) + * + * First calculate (NOTE: all stand baud values are even so dividing by two + * does not lose precision): + * + * usartdiv32 = 32 * usartdiv = fCK / (baud/2) + */ + + usartdiv32 = priv->config->apbclock / (priv->baud >> 1); + + /* The mantissa part is then */ + + mantissa = usartdiv32 >> 5; + brr = mantissa << USART_BRR_MANT_SHIFT; + + /* The fractional remainder (with rounding) */ + + fraction = (usartdiv32 - (mantissa << 5) + 1) >> 1; + brr |= fraction << USART_BRR_FRAC_SHIFT; + stm32_1wire_out(priv, STM32_USART_BRR_OFFSET, brr); +#endif +} + +/**************************************************************************** + * Name: stm32_1wire_set_apb_clock + * + * Description: + * Enable or disable APB clock for the USART peripheral + * + * Input Parameters: + * priv - A reference to the 1-Wire driver state structure + * on - Enable clock if 'on' is 'true' and disable if 'false' + * + ****************************************************************************/ + +static void stm32_1wire_set_apb_clock(struct stm32_1wire_priv_s *priv, + bool on) +{ + const struct stm32_1wire_config_s *config = priv->config; + uint32_t rcc_en; + uint32_t regaddr; + + /* Determine which USART to configure */ + + switch (config->usartbase) + { + default: + return; + +#ifdef CONFIG_STM32_USART1_1WIREDRIVER + case STM32_USART1_BASE: + rcc_en = RCC_APB2ENR_USART1EN; + regaddr = STM32_RCC_APB2ENR; + break; +#endif +#ifdef CONFIG_STM32_USART2_1WIREDRIVER + case STM32_USART2_BASE: + rcc_en = RCC_APB1ENR_USART2EN; + regaddr = STM32_RCC_APB1ENR; + break; +#endif +#ifdef CONFIG_STM32_USART3_1WIREDRIVER + case STM32_USART3_BASE: + rcc_en = RCC_APB1ENR_USART3EN; + regaddr = STM32_RCC_APB1ENR; + break; +#endif +#ifdef CONFIG_STM32_UART4_1WIREDRIVER + case STM32_UART4_BASE: + rcc_en = RCC_APB1ENR_UART4EN; + regaddr = STM32_RCC_APB1ENR; + break; +#endif +#ifdef CONFIG_STM32_UART5_1WIREDRIVER + case STM32_UART5_BASE: + rcc_en = RCC_APB1ENR_UART5EN; + regaddr = STM32_RCC_APB1ENR; + break; +#endif +#ifdef CONFIG_STM32_USART6_1WIREDRIVER + case STM32_USART6_BASE: + rcc_en = RCC_APB2ENR_USART6EN; + regaddr = STM32_RCC_APB2ENR; + break; +#endif +#ifdef CONFIG_STM32_UART7_1WIREDRIVER + case STM32_UART7_BASE: + rcc_en = RCC_APB1ENR_UART7EN; + regaddr = STM32_RCC_APB1ENR; + break; +#endif +#ifdef CONFIG_STM32_UART8_1WIREDRIVER + case STM32_UART8_BASE: + rcc_en = RCC_APB1ENR_UART8EN; + regaddr = STM32_RCC_APB1ENR; + break; +#endif + } + + /* Enable/disable APB 1/2 clock for USART */ + + if (on) + { + modifyreg32(regaddr, 0, rcc_en); + } + else + { + modifyreg32(regaddr, rcc_en, 0); + } +} + +/**************************************************************************** + * Name: stm32_1wire_init + * + * Description: + * Setup the 1-Wire hardware, ready for operation with defaults + * + ****************************************************************************/ + +static int stm32_1wire_init(struct stm32_1wire_priv_s *priv) +{ + const struct stm32_1wire_config_s *config = priv->config; + uint32_t regval; + int ret; + + /* Enable USART APB1/2 clock */ + + stm32_1wire_set_apb_clock(priv, true); + + /* Configure CR2 + * Clear STOP, CLKEN, CPOL, CPHA, LBCL, and interrupt enable bits + * Set LBDIE + */ + + regval = stm32_1wire_in(priv, STM32_USART_CR2_OFFSET); + regval &= ~(USART_CR2_STOP_MASK | USART_CR2_CLKEN | USART_CR2_CPOL | + USART_CR2_CPHA | USART_CR2_LBCL | USART_CR2_LBDIE); + regval |= USART_CR2_LBDIE; + stm32_1wire_out(priv, STM32_USART_CR2_OFFSET, regval); + + /* Configure CR1 + * Clear TE, REm, all interrupt enable bits, PCE, PS and M + * Set RXNEIE + */ + + regval = stm32_1wire_in(priv, STM32_USART_CR1_OFFSET); + regval &= ~(USART_CR1_TE | USART_CR1_RE | USART_CR1_ALLINTS | + USART_CR1_PCE | USART_CR1_PS | USART_CR1_M); + regval |= USART_CR1_RXNEIE; + stm32_1wire_out(priv, STM32_USART_CR1_OFFSET, regval); + + /* Configure CR3 + * Clear CTSE, RTSE, and all interrupt enable bits + * Set ONEBIT, HDSEL and EIE + */ + + regval = stm32_1wire_in(priv, STM32_USART_CR3_OFFSET); + regval &= ~(USART_CR3_CTSIE | USART_CR3_CTSE | USART_CR3_RTSE | + USART_CR3_EIE); + regval |= (USART_CR3_ONEBIT | USART_CR3_HDSEL | USART_CR3_EIE); + stm32_1wire_out(priv, STM32_USART_CR3_OFFSET, regval); + + /* Set baud rate */ + + priv->baud = RESET_BAUD; + stm32_1wire_set_baud(priv); + + /* Enable Rx, Tx, and the USART */ + + regval = stm32_1wire_in(priv, STM32_USART_CR1_OFFSET); + regval |= (USART_CR1_UE | USART_CR1_TE | USART_CR1_RE); + stm32_1wire_out(priv, STM32_USART_CR1_OFFSET, regval); + + /* Configure pins for USART use */ + + stm32_configgpio(config->data_pin); + + ret = irq_attach(config->irq, stm32_1wire_isr, priv); + if (ret == OK) + { + up_enable_irq(config->irq); + } + + return ret; +} + +/**************************************************************************** + * Name: stm32_1wire_deinit + * + * Description: + * Shutdown the 1-Wire hardware + * + ****************************************************************************/ + +static int stm32_1wire_deinit(struct stm32_1wire_priv_s *priv) +{ + const struct stm32_1wire_config_s *config = priv->config; + uint32_t regval; + + up_disable_irq(config->irq); + irq_detach(config->irq); + + /* Unconfigure GPIO pins */ + + stm32_unconfiggpio(config->data_pin); + + /* Disable RXNEIE, Rx, Tx, and the USART */ + + regval = stm32_1wire_in(priv, STM32_USART_CR1_OFFSET); + regval &= ~(USART_CR1_UE | USART_CR1_TE | USART_CR1_RE | USART_CR1_RXNEIE); + stm32_1wire_out(priv, STM32_USART_CR1_OFFSET, regval); + + /* Clear LBDIE */ + + regval = stm32_1wire_in(priv, STM32_USART_CR2_OFFSET); + regval &= ~USART_CR2_LBDIE; + stm32_1wire_out(priv, STM32_USART_CR2_OFFSET, regval); + + /* Clear ONEBIT, HDSEL and EIE */ + + regval = stm32_1wire_in(priv, STM32_USART_CR3_OFFSET); + regval &= ~(USART_CR3_ONEBIT | USART_CR3_HDSEL | USART_CR3_EIE); + stm32_1wire_out(priv, STM32_USART_CR3_OFFSET, regval); + + /* Disable USART APB1/2 clock */ + + stm32_1wire_set_apb_clock(priv, false); + + return OK; +} + +/**************************************************************************** + * Name: stm32_1wire_exec + * + * Description: + * Execute 1-Wire task + ****************************************************************************/ + +static int stm32_1wire_process(struct stm32_1wire_priv_s *priv, + const struct stm32_1wire_msg_s *msgs, + int count) +{ + irqstate_t irqs; + int index; + int ret; + + /* Lock out other clients */ + + ret = nxmutex_lock(&priv->lock); + if (ret < 0) + { + return ret; + } + + priv->result = ERROR; + + for (index = 0; index < count; index++) + { + switch (msgs[index].task) + { + case ONEWIRETASK_NONE: + priv->result = OK; + break; + + case ONEWIRETASK_RESET: + + /* Set baud rate */ + + priv->baud = RESET_BAUD; + stm32_1wire_set_baud(priv); + + /* Atomic */ + + irqs = enter_critical_section(); + priv->msgs = &msgs[index]; + stm32_1wire_send(priv, RESET_TX); + leave_critical_section(irqs); + + /* Wait. Break on timeout if TX line closed to GND */ + + nxsem_tickwait(&priv->sem_isr, SEC2TICK(BUS_TIMEOUT)); + break; + + case ONEWIRETASK_WRITE: + case ONEWIRETASK_WRITEBIT: + + /* Set baud rate */ + + priv->baud = TIMESLOT_BAUD; + stm32_1wire_set_baud(priv); + + /* Atomic */ + + irqs = enter_critical_section(); + priv->msgs = &msgs[index]; + priv->byte = priv->msgs->buffer; + priv->bit = 0; + stm32_1wire_send(priv, (*priv->byte & (1 << priv->bit)) ? + WRITE_TX1 : WRITE_TX0); + leave_critical_section(irqs); + + /* Wait. Break on timeout if TX line closed to GND */ + + nxsem_tickwait(&priv->sem_isr, SEC2TICK(BUS_TIMEOUT)); + break; + + case ONEWIRETASK_READ: + case ONEWIRETASK_READBIT: + + /* Set baud rate */ + + priv->baud = TIMESLOT_BAUD; + stm32_1wire_set_baud(priv); + + /* Atomic */ + + irqs = enter_critical_section(); + priv->msgs = &msgs[index]; + priv->byte = priv->msgs->buffer; + priv->bit = 0; + stm32_1wire_send(priv, READ_TX); + leave_critical_section(irqs); + + /* Wait. Break on timeout if TX line closed to GND */ + + nxsem_tickwait(&priv->sem_isr, SEC2TICK(BUS_TIMEOUT)); + break; + } + + if (priv->result != OK) /* break if error */ + { + break; + } + } + + /* Atomic */ + + irqs = enter_critical_section(); + priv->msgs = NULL; + ret = priv->result; + leave_critical_section(irqs); + + /* Release the port for reuse by other clients */ + + nxmutex_unlock(&priv->lock); + return ret; +} + +/**************************************************************************** + * Name: stm32_1wire_isr + * + * Description: + * Common Interrupt Service Routine + ****************************************************************************/ + +static int stm32_1wire_isr(int irq, void *context, void *arg) +{ + struct stm32_1wire_priv_s *priv = (struct stm32_1wire_priv_s *)arg; + uint32_t sr; + uint32_t dr; + + DEBUGASSERT(priv != NULL); + + /* Get the masked USART status word. */ + + sr = stm32_1wire_in(priv, STM32_USART_SR_OFFSET); + + /* Receive loop */ + + if ((sr & USART_SR_RXNE) != 0) + { + dr = stm32_1wire_recv(priv); + + if (priv->msgs != NULL) + { + switch (priv->msgs->task) + { + case ONEWIRETASK_NONE: + break; + + case ONEWIRETASK_RESET: + priv->msgs = NULL; + priv->result = (dr != RESET_TX) ? OK : -ENODEV; /* if read RESET_TX then no slave */ + nxsem_post(&priv->sem_isr); + break; + + case ONEWIRETASK_WRITE: + if (++priv->bit >= 8) + { + priv->bit = 0; + if (++priv->byte >= (priv->msgs->buffer + priv->msgs->buflen)) /* Done? */ + { + priv->msgs = NULL; + priv->result = OK; + nxsem_post(&priv->sem_isr); + break; + } + } + + /* Send next bit */ + + stm32_1wire_send(priv, (*priv->byte & (1 << priv->bit)) ? + WRITE_TX1 : WRITE_TX0); + break; + + case ONEWIRETASK_READ: + if (dr == READ_RX1) + { + *priv->byte |= (1 << priv->bit); + } + else + { + *priv->byte &= ~(1 << priv->bit); + } + + if (++priv->bit >= 8) + { + priv->bit = 0; + if (++priv->byte >= (priv->msgs->buffer + priv->msgs->buflen)) /* Done? */ + { + priv->msgs = NULL; + priv->result = OK; + nxsem_post(&priv->sem_isr); + break; + } + } + + /* Recv next bit */ + + stm32_1wire_send(priv, READ_TX); + break; + + case ONEWIRETASK_READBIT: + *priv->byte = (dr == READ_RX1) ? 1 : 0; + + /* Fall through */ + + case ONEWIRETASK_WRITEBIT: + priv->msgs = NULL; + priv->result = OK; + nxsem_post(&priv->sem_isr); + break; + } + } + } + + /* Bounce check. */ + + if ((sr & (USART_SR_ORE | USART_SR_NE | USART_SR_FE)) != 0) + { +#if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX) + /* These errors are cleared by writing the corresponding bit to the + * interrupt clear register (ICR). + */ + + stm32_1wire_out(priv, STM32_USART_ICR_OFFSET, + (USART_ICR_NCF | USART_ICR_ORECF | USART_ICR_FECF)); +#else + /* If an error occurs, read from DR to clear the error (data has + * been lost). If ORE is set along with RXNE then it tells you + * that the byte *after* the one in the data register has been + * lost, but the data register value is correct. That case will + * be handled above if interrupts are enabled. Otherwise, that + * good byte will be lost. + */ + + stm32_1wire_recv(priv); +#endif + + if (priv->msgs != NULL) + { + priv->msgs = NULL; + priv->result = ERROR; + nxsem_post(&priv->sem_isr); + } + } + + /* Bounce check. LIN break detection */ + + if ((sr & USART_SR_LBD) != 0) + { + sr &= ~USART_SR_LBD; + stm32_1wire_out(priv, STM32_USART_SR_OFFSET, sr); + + if (priv->msgs != NULL) + { + priv->msgs = NULL; + priv->result = ERROR; + nxsem_post(&priv->sem_isr); + } + } + + return OK; +} + +/**************************************************************************** + * Name: stm32_1wire_reset + * + * Description: + * 1-Wire reset pulse and presence detect. + * + ****************************************************************************/ + +static int stm32_1wire_reset(struct onewire_dev_s *dev) +{ + struct stm32_1wire_priv_s *priv = ((struct stm32_1wire_inst_s *)dev)->priv; + const struct stm32_1wire_msg_s msgs[1] = + { + [0].task = ONEWIRETASK_RESET + }; + + return stm32_1wire_process(priv, msgs, 1); +} + +/**************************************************************************** + * Name: stm32_1wire_write + * + * Description: + * Write 1-Wire data + * + ****************************************************************************/ + +static int stm32_1wire_write(struct onewire_dev_s *dev, + const uint8_t *buffer, int buflen) +{ + struct stm32_1wire_priv_s *priv = ((struct stm32_1wire_inst_s *)dev)->priv; + const struct stm32_1wire_msg_s msgs[1] = + { + [0].task = ONEWIRETASK_WRITE, + [0].buffer = (uint8_t *)buffer, + [0].buflen = buflen + }; + + return stm32_1wire_process(priv, msgs, 1); +} + +/**************************************************************************** + * Name: stm32_1wire_read + * + * Description: + * Read 1-Wire data + * + ****************************************************************************/ + +static int stm32_1wire_read(struct onewire_dev_s *dev, uint8_t *buffer, + int buflen) +{ + struct stm32_1wire_priv_s *priv = ((struct stm32_1wire_inst_s *)dev)->priv; + const struct stm32_1wire_msg_s msgs[1] = + { + [0].task = ONEWIRETASK_READ, + [0].buffer = buffer, + [0].buflen = buflen + }; + + return stm32_1wire_process(priv, msgs, 1); +} + +/**************************************************************************** + * Name: stm32_1wire_exchange + * + * Description: + * 1-Wire reset pulse and presence detect, + * Write 1-Wire data, + * Read 1-Wire data + * + ****************************************************************************/ + +static int stm32_1wire_exchange(struct onewire_dev_s *dev, bool reset, + const uint8_t *txbuffer, int txbuflen, + uint8_t *rxbuffer, int rxbuflen) +{ + int result = ERROR; + struct stm32_1wire_priv_s *priv = ((struct stm32_1wire_inst_s *)dev)->priv; + + if (reset) + { + const struct stm32_1wire_msg_s msgs[3] = + { + [0].task = ONEWIRETASK_RESET, + + [1].task = ONEWIRETASK_WRITE, + [1].buffer = (uint8_t *)txbuffer, + [1].buflen = txbuflen, + + [2].task = ONEWIRETASK_READ, + [2].buffer = rxbuffer, + [2].buflen = rxbuflen + }; + + result = stm32_1wire_process(priv, msgs, 3); + } + else + { + const struct stm32_1wire_msg_s msgs[2] = + { + [0].task = ONEWIRETASK_WRITE, + [0].buffer = (uint8_t *)txbuffer, + [0].buflen = txbuflen, + + [1].task = ONEWIRETASK_READ, + [1].buffer = rxbuffer, + [1].buflen = rxbuflen + }; + + result = stm32_1wire_process(priv, msgs, 2); + } + + return result; +} + +/**************************************************************************** + * Name: stm32_1wire_writebit + * + * Description: + * Write one bit of 1-Wire data + * + ****************************************************************************/ + +static int stm32_1wire_writebit(struct onewire_dev_s *dev, + const uint8_t *bit) +{ + struct stm32_1wire_priv_s *priv = ((struct stm32_1wire_inst_s *)dev)->priv; + const struct stm32_1wire_msg_s msgs[1] = + { + [0].task = ONEWIRETASK_WRITEBIT, + [0].buffer = (uint8_t *)bit, + [0].buflen = 1 + }; + + DEBUGASSERT(*bit == 0 || *bit == 1); + + return stm32_1wire_process(priv, msgs, 1); +} + +/**************************************************************************** + * Name: stm32_1wire_readbit + * + * Description: + * Sample one bit of 1-Wire data + * + ****************************************************************************/ + +static int stm32_1wire_readbit(struct onewire_dev_s *dev, uint8_t *bit) +{ + struct stm32_1wire_priv_s *priv = ((struct stm32_1wire_inst_s *)dev)->priv; + const struct stm32_1wire_msg_s msgs[1] = + { + [0].task = ONEWIRETASK_READBIT, + [0].buffer = bit, + [0].buflen = 1 + }; + + return stm32_1wire_process(priv, msgs, 1); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_1wireinitialize + * + * Description: + * Initialize the selected 1-Wire port. And return a unique instance of + * struct onewire_dev_s. This function may be called to obtain multiple + * instances of the interface, each of which may be set up with a + * different frequency and slave address. + * + * Input Parameters: + * Port number (for hardware that has multiple 1-Wire interfaces) + * + * Returned Value: + * Valid 1-Wire device structure reference on success; a NULL on failure + * + ****************************************************************************/ + +struct onewire_dev_s *stm32_1wireinitialize(int port) +{ + struct stm32_1wire_priv_s *priv = NULL; /* Private data of device with multiple instances */ + struct stm32_1wire_inst_s *inst = NULL; /* Device, single instance */ + + /* Get 1-Wire private structure */ + + switch (port) + { +#ifdef CONFIG_STM32_USART1_1WIREDRIVER + case 1: + priv = &stm32_1wire1_priv; + break; +#endif +#ifdef CONFIG_STM32_USART2_1WIREDRIVER + case 2: + priv = &stm32_1wire2_priv; + break; +#endif +#ifdef CONFIG_STM32_USART3_1WIREDRIVER + case 3: + priv = &stm32_1wire3_priv; + break; +#endif +#ifdef CONFIG_STM32_UART4_1WIREDRIVER + case 4: + priv = &stm32_1wire4_priv; + break; +#endif +#ifdef CONFIG_STM32_UART5_1WIREDRIVER + case 5: + priv = &stm32_1wire5_priv; + break; +#endif +#ifdef CONFIG_STM32_USART6_1WIREDRIVER + case 6: + priv = &stm32_1wire6_priv; + break; +#endif +#ifdef CONFIG_STM32_UART7_1WIREDRIVER + case 7: + priv = &stm32_1wire7_priv; + break; +#endif +#ifdef CONFIG_STM32_UART8_1WIREDRIVER + case 8: + priv = &stm32_1wire8_priv; + break; +#endif + default: + return NULL; + } + + /* Allocate instance */ + + inst = kmm_malloc(sizeof(*inst)); + if (inst == NULL) + { + return NULL; + } + + /* Initialize instance */ + + inst->ops = &stm32_1wire_ops; + inst->priv = priv; + + /* Initialize private data for the first time, increment reference count, + * power-up hardware and configure GPIOs. + */ + + nxmutex_lock(&priv->lock); + if (priv->refs++ == 0) + { + stm32_1wire_init(priv); + } + + nxmutex_unlock(&priv->lock); + return (struct onewire_dev_s *)inst; +} + +/**************************************************************************** + * Name: stm32_1wireuninitialize + * + * Description: + * De-initialize the selected 1-Wire port, and power down the device. + * + * Input Parameters: + * Device structure as returned by the stm32_1wireinitialize() + * + * Returned Value: + * OK on success, ERROR when internal reference count mismatch or dev + * points to invalid hardware device. + * + ****************************************************************************/ + +int stm32_1wireuninitialize(struct onewire_dev_s *dev) +{ + struct stm32_1wire_priv_s *priv = ((struct stm32_1wire_inst_s *)dev)->priv; + + DEBUGASSERT(priv); + + /* Decrement reference count and check for underflow */ + + if (priv->refs == 0) + { + return ERROR; + } + + nxmutex_lock(&priv->lock); + if (--priv->refs) + { + nxmutex_unlock(&priv->lock); + return OK; + } + + /* Disable power and other HW resource (GPIO's) */ + + stm32_1wire_deinit(priv); + nxmutex_unlock(&priv->lock); + + /* Free instance */ + + kmm_free(dev); + return OK; +} + +#endif /* HAVE_1WIREDRIVER */ diff --git a/arch/arm/src/common/stm32/stm32_adc.h b/arch/arm/src/common/stm32/stm32_adc.h new file mode 100644 index 0000000000000..fce412ef2ef38 --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_adc.h @@ -0,0 +1,40 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_adc.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_COMPAT_STM32_ADC_H +#define __ARCH_ARM_SRC_COMMON_COMPAT_STM32_ADC_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#if defined(CONFIG_STM32_HAVE_IP_ADC_M0_V1) +# include "stm32_adc_m0_v1.h" +#elif defined(CONFIG_STM32_HAVE_IP_ADC_M3M4_V1) || defined(CONFIG_STM32_HAVE_IP_ADC_M3M4_V2) +# include "stm32_adc_m3m4_v1v2.h" +#else +# error "Unsupported STM32 ADC" +#endif + +#endif /* __ARCH_ARM_SRC_COMMON_COMPAT_STM32_ADC_H */ diff --git a/arch/arm/src/common/stm32/stm32_adc_m0_v1.c b/arch/arm/src/common/stm32/stm32_adc_m0_v1.c new file mode 100644 index 0000000000000..cfa4e5c8cf1e4 --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_adc_m0_v1.c @@ -0,0 +1,2882 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_adc_m0_v1.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#include "arm_internal.h" +#include "chip.h" +#include "stm32.h" +#include "stm32_tim.h" +#include "stm32_dma.h" +#include "stm32_adc.h" + +/* STM32 ADC "lower-half" support must be enabled */ + +#ifdef CONFIG_STM32_ADC + +/* Some ADC peripheral must be enabled */ + +#if defined(CONFIG_STM32_ADC1) + +#if defined(CONFIG_STM32_STM32F0) +# error Not tested +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* RCC reset ****************************************************************/ + +#define STM32_RCC_RSTR STM32_RCC_APB2RSTR +#define RCC_RSTR_ADC1RST RCC_APB2RSTR_ADC1RST + +/* ADC Channels/DMA *********************************************************/ + +/* DMA values differs according to STM32 DMA IP core version */ + +#if defined(HAVE_IP_DMA_V1) +# define ADC_DMA_CONTROL_WORD (DMA_CCR_MSIZE_16BITS | \ + DMA_CCR_PSIZE_16BITS | \ + DMA_CCR_MINC | \ + DMA_CCR_CIRC) +#else +# error Not supported +#endif + +/* Sample time default configuration */ + +/* C0 and G0 support additional sample time selection 2 */ + +#if defined(CONFIG_STM32_STM32G0) || defined(CONFIG_STM32_STM32C0) +# define ADC_HAVE_SMPR_SMP2 +#endif + +#if defined(ADC_HAVE_DMA) || (CONFIG_STM32_ADC_MAX_SAMPLES == 1) +# if defined(CONFIG_ARCH_CHIP_STM32C0) || defined(CONFIG_ARCH_CHIP_STM32G0) +# define ADC_SMP1_DEFAULT ADC_SMPR_12p5 +# define ADC_SMP2_DEFAULT ADC_SMPR_12p5 +# else +# define ADC_SMP1_DEFAULT ADC_SMPR_13p5 +# endif +#else /* Slow down sampling frequency */ +# if defined(CONFIG_ARCH_CHIP_STM32C0) || defined(CONFIG_ARCH_CHIP_STM32G0) +# define ADC_SMP1_DEFAULT ADC_SMPR_160p5 +# define ADC_SMP2_DEFAULT ADC_SMPR_160p5 +# else +# define ADC_SMP1_DEFAULT ADC_SMPR_239p5 +# endif +#endif + +#ifdef ADC_HAVE_SMPR_SMP2 +# define ADC_SMPSEL_DEFAULT 0 /* For now we use only SMP1 */ +#endif + +/* Number of channels per ADC: + * - F0, L0, G0 - 19, but single SMP for all channels + * + * NOTE: this value can be obtained from SMPRx register description + * (ST manual) + */ + +#if defined(CONFIG_STM32_STM32F0) || \ + defined(CONFIG_STM32_STM32L0) || \ + defined(CONFIG_STM32_STM32C0) || \ + defined(CONFIG_STM32_STM32G0) +# define ADC_CHANNELS_NUMBER 19 +#else +# error "Not supported" +#endif + +/* ADC resolution */ + +#define HAVE_ADC_RESOLUTION + +/* ADC have common registers but only single ADC */ + +#define HAVE_ADC_CMN_REGS 1 + +/* ADCx_EXTSEL_VALUE */ + +#ifdef ADC1_EXTSEL_VALUE +# define ADC1_HAVE_EXTCFG 1 +# define ADC1_EXTCFG_VALUE (ADC1_EXTSEL_VALUE | ADC_EXTREG_EXTEN_DEFAULT) +#else +# undef ADC1_HAVE_EXTCFG +#endif + +#if defined(ADC1_HAVE_EXTCFG) +# define ADC_HAVE_EXTCFG +#endif + +/* ADC DMA configuration bit support */ + +#define ADC_HAVE_DMACFG 1 + +#if defined(CONFIG_STM32_STM32G0) || defined(CONFIG_STM32_STM32L0) +# ifndef ANIOC_SET_OVERSAMPLE +# define ANIOC_SET_OVERSAMPLE _ANIOC(0x0f) +# endif +#endif + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/* Data common to all ADC instances */ + +#ifdef HAVE_ADC_CMN_DATA +struct adccmn_data_s +{ + uint8_t initialized; /* How many ADC instances are currently in use */ + mutex_t lock; /* Exclusive access to common ADC data */ +}; +#endif + +/* This structure describes the state of one ADC block + * REVISIT: save some space with bit fields. + */ + +struct stm32_dev_s +{ +#ifdef CONFIG_STM32_ADC_LL_OPS + const struct stm32_adc_ops_s *llops; /* Low-level ADC ops */ +#endif +#if !defined(CONFIG_STM32_ADC_NOIRQ) | defined(ADC_HAVE_DMA) + const struct adc_callback_s *cb; + uint8_t irq; /* Interrupt generated by this ADC block */ +#endif +#ifdef HAVE_ADC_CMN_DATA + struct adccmn_data_s *cmn; /* Common ADC data */ +#endif + uint8_t rnchannels; /* Number of regular channels */ + uint8_t cr_channels; /* Number of configured regular channels */ + uint8_t intf; /* ADC interface number */ + uint8_t current; /* Current ADC channel being converted */ +#ifdef HAVE_ADC_RESOLUTION + uint8_t resolution; /* ADC resolution (0-3) */ +#endif +#ifdef ADC_HAVE_DMA + uint8_t dmachan; /* DMA channel needed by this ADC */ +# ifdef ADC_HAVE_DMACFG + uint8_t dmacfg; /* DMA channel configuration, only for ADC IPv2 */ +# endif + bool hasdma; /* True: This channel supports DMA */ + uint16_t dmabatch; /* Number of conversions for DMA batch */ +#endif +#ifdef CONFIG_STM32_ADC_CHANGE_SAMPLETIME + /* Sample time selection. These bits must be written only when ADON=0. */ + +# ifdef ADC_HAVE_SMPR_SMP2 + uint8_t sample_rate[2]; /* [0] for SMP1, [1] for SMP2 */ + uint32_t smpsel; /* ADC Sample Rate Selection Bits */ +# else + uint8_t sample_rate[1]; /* Only SMP1 is used */ +# endif +#endif +#ifdef ADC_HAVE_TIMER + uint8_t trigger; /* Timer trigger channel: 0=CC1, 1=CC2, 2=CC3, + * 3=CC4, 4=TRGO, 5=TRGO2 + */ +#endif + xcpt_t isr; /* Interrupt handler for this ADC block */ + uint32_t base; /* Base address of registers unique to this ADC + * block */ +#ifdef ADC_HAVE_EXTCFG + uint32_t extcfg; /* External event configuration for regular group */ +#endif +#ifdef ADC_HAVE_TIMER + uint32_t tbase; /* Base address of timer used by this ADC block */ + uint32_t pclck; /* The PCLK frequency that drives this timer */ + uint32_t freq; /* The desired frequency of conversions */ +#endif +#ifdef ADC_HAVE_DMA + DMA_HANDLE dma; /* Allocated DMA channel */ + + /* DMA transfer buffer */ + + uint16_t *r_dmabuffer; +#endif + + /* List of selected ADC channels to sample */ + + uint8_t r_chanlist[CONFIG_STM32_ADC_MAX_SAMPLES]; +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/* ADC Register access */ + +static void stm32_modifyreg32(unsigned int addr, uint32_t clrbits, + uint32_t setbits); +static uint32_t adc_getreg(struct stm32_dev_s *priv, int offset); +static void adc_putreg(struct stm32_dev_s *priv, int offset, + uint32_t value); +static void adc_modifyreg(struct stm32_dev_s *priv, int offset, + uint32_t clrbits, uint32_t setbits); +#ifdef HAVE_ADC_CMN_REGS +static uint32_t adccmn_base_get(struct stm32_dev_s *priv); +static void adccmn_modifyreg(struct stm32_dev_s *priv, uint32_t offset, + uint32_t clrbits, uint32_t setbits); +static uint32_t adccmn_getreg(struct stm32_dev_s *priv, uint32_t offset); +#endif +#ifdef ADC_HAVE_TIMER +static uint16_t tim_getreg(struct stm32_dev_s *priv, int offset); +static void tim_putreg(struct stm32_dev_s *priv, int offset, + uint16_t value); +static void tim_modifyreg(struct stm32_dev_s *priv, int offset, + uint16_t clrbits, uint16_t setbits); +static void tim_modifyreg32(struct stm32_dev_s *priv, int offset, + uint32_t clrbits, uint32_t setbits); +static void tim_dumpregs(struct stm32_dev_s *priv, + const char *msg); +#endif + +static void adc_rccreset(struct stm32_dev_s *priv, bool reset); + +/* ADC Interrupt Handler */ + +#ifndef CONFIG_STM32_ADC_NOIRQ +static int adc_interrupt(struct adc_dev_s *dev); +static int adc1_interrupt(int irq, void *context, void *arg); +#endif /* CONFIG_STM32_ADC_NOIRQ */ + +/* ADC Driver Methods */ + +static int adc_bind(struct adc_dev_s *dev, + const struct adc_callback_s *callback); +static void adc_reset(struct adc_dev_s *dev); +static int adc_setup(struct adc_dev_s *dev); +static void adc_shutdown(struct adc_dev_s *dev); +static void adc_rxint(struct adc_dev_s *dev, bool enable); +static int adc_ioctl(struct adc_dev_s *dev, int cmd, unsigned long arg); +static void adc_enable(struct stm32_dev_s *priv, bool enable); + +static int adc_set_ch(struct adc_dev_s *dev, uint8_t ch); + +static int adc_ioc_change_ints(struct adc_dev_s *dev, int cmd, + bool arg); + +#ifdef HAVE_ADC_RESOLUTION +static int adc_resolution_set(struct adc_dev_s *dev, uint8_t res); +#endif +#ifdef HAVE_ADC_VBAT +static void adc_enable_vbat_channel(struct adc_dev_s *dev, bool enable); +#endif +#ifdef HAVE_ADC_POWERDOWN +static int adc_ioc_change_sleep_between_opers(struct adc_dev_s *dev, + int cmd, bool arg); +static void adc_power_down_idle(struct stm32_dev_s *priv, + bool pdi_high); +static void adc_power_down_delay(struct stm32_dev_s *priv, + bool pdd_high); +#endif + +#ifdef ADC_HAVE_TIMER +static void adc_timstart(struct stm32_dev_s *priv, bool enable); +static int adc_timinit(struct stm32_dev_s *priv); +#endif + +#if defined(ADC_HAVE_DMA) +static void adc_dmaconvcallback(DMA_HANDLE handle, uint8_t isr, + void *arg); +#endif + +static void adc_reg_startconv(struct stm32_dev_s *priv, bool enable); + +#ifdef ADC_HAVE_EXTCFG +static int adc_extcfg_set(struct adc_dev_s *dev, uint32_t extcfg); +#endif + +static void adc_dumpregs(struct stm32_dev_s *priv); + +#ifdef CONFIG_STM32_ADC_LL_OPS +static void adc_llops_intack(struct stm32_adc_dev_s *dev, + uint32_t source); +static void adc_llops_inten(struct stm32_adc_dev_s *dev, + uint32_t source); +static void adc_llops_intdis(struct stm32_adc_dev_s *dev, + uint32_t source); +static uint32_t adc_llops_intget(struct stm32_adc_dev_s *dev); +static uint32_t adc_llops_regget(struct stm32_adc_dev_s *dev); +static void adc_llops_reg_startconv(struct stm32_adc_dev_s *dev, + bool enable); +# ifdef ADC_HAVE_DMA +static int adc_llops_regbufregister(struct stm32_adc_dev_s *dev, + uint16_t *buffer, uint8_t len); +# endif +# ifdef CONFIG_STM32_ADC_CHANGE_SAMPLETIME +static void adc_sampletime_set(struct stm32_adc_dev_s *dev, + struct adc_sample_time_s *time_samples); +static void adc_sampletime_write(struct stm32_adc_dev_s *dev); +# endif +static void adc_llops_dumpregs(struct stm32_adc_dev_s *dev); +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* ADC interface operations */ + +static const struct adc_ops_s g_adcops = +{ + .ao_bind = adc_bind, + .ao_reset = adc_reset, + .ao_setup = adc_setup, + .ao_shutdown = adc_shutdown, + .ao_rxint = adc_rxint, + .ao_ioctl = adc_ioctl, +}; + +/* Publicly visible ADC lower-half operations */ + +#ifdef CONFIG_STM32_ADC_LL_OPS +static const struct stm32_adc_ops_s g_adc_llops = +{ + .int_ack = adc_llops_intack, + .int_get = adc_llops_intget, + .int_en = adc_llops_inten, + .int_dis = adc_llops_intdis, + .val_get = adc_llops_regget, + .reg_startconv = adc_llops_reg_startconv, +# ifdef ADC_HAVE_DMA + .regbuf_reg = adc_llops_regbufregister, +# endif +# ifdef CONFIG_STM32_ADC_CHANGE_SAMPLETIME + .stime_set = adc_sampletime_set, + .stime_write = adc_sampletime_write, +# endif + .dump_regs = adc_llops_dumpregs +}; +#endif + +/* ADC1 state */ + +#ifdef CONFIG_STM32_ADC1 + +#ifdef ADC1_HAVE_DMA +static uint16_t g_adc1_dmabuffer[CONFIG_STM32_ADC_MAX_SAMPLES * + CONFIG_STM32_ADC1_DMA_BATCH]; +#endif + +static struct stm32_dev_s g_adcpriv1 = +{ +#ifdef CONFIG_STM32_ADC_LL_OPS + .llops = &g_adc_llops, +#endif +#ifndef CONFIG_STM32_ADC_NOIRQ + .irq = STM32_IRQ_ADC, + .isr = adc1_interrupt, +#endif /* CONFIG_STM32_ADC_NOIRQ */ +#ifdef HAVE_ADC_CMN_DATA + .cmn = &ADC1CMN_DATA, +#endif + .intf = 1, +#ifdef HAVE_ADC_RESOLUTION + .resolution = CONFIG_STM32_ADC1_RESOLUTION, +#endif + .base = STM32_ADC1_BASE, +#ifdef ADC1_HAVE_EXTCFG + .extcfg = ADC1_EXTCFG_VALUE, +#endif +#ifdef ADC1_HAVE_TIMER + .trigger = CONFIG_STM32_ADC1_TIMTRIG, + .tbase = ADC1_TIMER_BASE, + .pclck = ADC1_TIMER_PCLK_FREQUENCY, + .freq = CONFIG_STM32_ADC1_SAMPLE_FREQUENCY, +#endif +#ifdef ADC1_HAVE_DMA + .dmachan = ADC1_DMA_CHAN, +# ifdef ADC_HAVE_DMACFG + .dmacfg = CONFIG_STM32_ADC1_DMA_CFG, +# endif + .hasdma = true, + .r_dmabuffer = g_adc1_dmabuffer, + .dmabatch = CONFIG_STM32_ADC1_DMA_BATCH +#endif +}; + +static struct adc_dev_s g_adcdev1 = +{ + .ad_ops = &g_adcops, + .ad_priv = &g_adcpriv1, +}; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_modifyreg32 + * + * Description: + * Modify the value of a 32-bit register (not atomic). + * + * Input Parameters: + * addr - The address of the register + * clrbits - The bits to clear + * setbits - The bits to set + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void stm32_modifyreg32(unsigned int addr, uint32_t clrbits, + uint32_t setbits) +{ + putreg32((getreg32(addr) & ~clrbits) | setbits, addr); +} + +/**************************************************************************** + * Name: adc_getreg + * + * Description: + * Read the value of an ADC register. + * + * Input Parameters: + * priv - A reference to the ADC block status + * offset - The offset to the register to read + * + * Returned Value: + * The current contents of the specified register + * + ****************************************************************************/ + +static uint32_t adc_getreg(struct stm32_dev_s *priv, int offset) +{ + return getreg32(priv->base + offset); +} + +/**************************************************************************** + * Name: adc_putreg + * + * Description: + * Write a value to an ADC register. + * + * Input Parameters: + * priv - A reference to the ADC block status + * offset - The offset to the register to write to + * value - The value to write to the register + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void adc_putreg(struct stm32_dev_s *priv, int offset, + uint32_t value) +{ + putreg32(value, priv->base + offset); +} + +/**************************************************************************** + * Name: adc_modifyreg + * + * Description: + * Modify the value of an ADC register (not atomic). + * + * Input Parameters: + * priv - A reference to the ADC block status + * offset - The offset to the register to modify + * clrbits - The bits to clear + * setbits - The bits to set + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void adc_modifyreg(struct stm32_dev_s *priv, int offset, + uint32_t clrbits, uint32_t setbits) +{ + adc_putreg(priv, offset, (adc_getreg(priv, offset) & ~clrbits) | setbits); +} + +#ifdef HAVE_ADC_CMN_REGS + +/**************************************************************************** + * Name: adccmn_base_get + ****************************************************************************/ + +static uint32_t adccmn_base_get(struct stm32_dev_s *priv) +{ + uint32_t base = 0; + + if (priv->base == STM32_ADC1_BASE) + { + base = STM32_ADC12CMN_BASE; + } + + return base; +} + +/**************************************************************************** + * Name: adccmn_modifyreg + ****************************************************************************/ + +static void adccmn_modifyreg(struct stm32_dev_s *priv, uint32_t offset, + uint32_t clrbits, uint32_t setbits) +{ + uint32_t base = 0; + + /* Get base address for ADC common register */ + + base = adccmn_base_get(priv); + + /* Modify register */ + + stm32_modifyreg32(offset + base, clrbits, setbits); +} + +/**************************************************************************** + * Name: adccmn_getreg + ****************************************************************************/ + +static uint32_t adccmn_getreg(struct stm32_dev_s *priv, uint32_t offset) +{ + uint32_t base = 0; + + /* Get base address for ADC common register */ + + base = adccmn_base_get(priv); + + /* Return register value */ + + return getreg32(base + offset); +} +#endif /* HAVE_ADC_CMN_REGS */ + +#ifdef ADC_HAVE_TIMER +/**************************************************************************** + * Name: tim_getreg + * + * Description: + * Read the value of an ADC timer register. + * + * Input Parameters: + * priv - A reference to the ADC block status + * offset - The offset to the register to read + * + * Returned Value: + * The current contents of the specified register + * + ****************************************************************************/ + +static uint16_t tim_getreg(struct stm32_dev_s *priv, int offset) +{ + return getreg16(priv->tbase + offset); +} + +/**************************************************************************** + * Name: tim_putreg + * + * Description: + * Write a value to an ADC timer register. + * + * Input Parameters: + * priv - A reference to the ADC block status + * offset - The offset to the register to write to + * value - The value to write to the register + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void tim_putreg(struct stm32_dev_s *priv, int offset, + uint16_t value) +{ + putreg16(value, priv->tbase + offset); +} + +/**************************************************************************** + * Name: tim_modifyreg + * + * Description: + * Modify the value of an ADC timer register (not atomic). + * + * Input Parameters: + * priv - A reference to the ADC block status + * offset - The offset to the register to modify + * clrbits - The bits to clear + * setbits - The bits to set + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void tim_modifyreg(struct stm32_dev_s *priv, int offset, + uint16_t clrbits, uint16_t setbits) +{ + tim_putreg(priv, offset, (tim_getreg(priv, offset) & ~clrbits) | setbits); +} + +/**************************************************************************** + * Name: tim_modifyreg32 + * + * Description: + * Modify the value of an ADC timer register (not atomic). + * + * Input Parameters: + * priv - A reference to the ADC block status + * offset - The offset to the register to modify + * clrbits - The bits to clear + * setbits - The bits to set + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void tim_modifyreg32(struct stm32_dev_s *priv, int offset, + uint32_t clrbits, uint32_t setbits) +{ + uint32_t addr = priv->tbase + offset; + putreg32((getreg32(addr) & ~clrbits) | setbits, addr); +} + +/**************************************************************************** + * Name: tim_dumpregs + * + * Description: + * Dump all timer registers. + * + * Input Parameters: + * priv - A reference to the ADC block status + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void tim_dumpregs(struct stm32_dev_s *priv, const char *msg) +{ + ainfo("%s:\n", msg); + ainfo(" CR1: %04x CR2: %04x SMCR: %04x DIER: %04x\n", + tim_getreg(priv, STM32_GTIM_CR1_OFFSET), + tim_getreg(priv, STM32_GTIM_CR2_OFFSET), + tim_getreg(priv, STM32_GTIM_SMCR_OFFSET), + tim_getreg(priv, STM32_GTIM_DIER_OFFSET)); + ainfo(" SR: %04x EGR: 0000 CCMR1: %04x CCMR2: %04x\n", + tim_getreg(priv, STM32_GTIM_SR_OFFSET), + tim_getreg(priv, STM32_GTIM_CCMR1_OFFSET), + tim_getreg(priv, STM32_GTIM_CCMR2_OFFSET)); + ainfo(" CCER: %04x CNT: %04x PSC: %04x ARR: %04x\n", + tim_getreg(priv, STM32_GTIM_CCER_OFFSET), + tim_getreg(priv, STM32_GTIM_CNT_OFFSET), + tim_getreg(priv, STM32_GTIM_PSC_OFFSET), + tim_getreg(priv, STM32_GTIM_ARR_OFFSET)); + ainfo(" CCR1: %04x CCR2: %04x CCR3: %04x CCR4: %04x\n", + tim_getreg(priv, STM32_GTIM_CCR1_OFFSET), + tim_getreg(priv, STM32_GTIM_CCR2_OFFSET), + tim_getreg(priv, STM32_GTIM_CCR3_OFFSET), + tim_getreg(priv, STM32_GTIM_CCR4_OFFSET)); +#if STM32_NATIM > 0 + if (priv->tbase == STM32_TIM1_BASE) + { + ainfo(" RCR: %04x BDTR: %04x DCR: %04x DMAR: %04x\n", + tim_getreg(priv, STM32_ATIM_RCR_OFFSET), + tim_getreg(priv, STM32_ATIM_BDTR_OFFSET), + tim_getreg(priv, STM32_ATIM_DCR_OFFSET), + tim_getreg(priv, STM32_ATIM_DMAR_OFFSET)); + } + else +#endif + { + ainfo(" DCR: %04x DMAR: %04x\n", + tim_getreg(priv, STM32_GTIM_DCR_OFFSET), + tim_getreg(priv, STM32_GTIM_DMAR_OFFSET)); + } +} + +/**************************************************************************** + * Name: adc_timstart + * + * Description: + * Start (or stop) the timer counter + * + * Input Parameters: + * priv - A reference to the ADC block status + * enable - True: Start conversion + * + * Returned Value: + * + ****************************************************************************/ + +static void adc_timstart(struct stm32_dev_s *priv, bool enable) +{ + ainfo("enable: %d\n", enable ? 1 : 0); + + if (enable) + { + /* Start the counter */ + + tim_modifyreg(priv, STM32_GTIM_CR1_OFFSET, 0, GTIM_CR1_CEN); + } + else + { + /* Disable the counter */ + + tim_modifyreg(priv, STM32_GTIM_CR1_OFFSET, GTIM_CR1_CEN, 0); + } +} + +/**************************************************************************** + * Name: adc_timinit + * + * Description: + * Initialize the timer that drivers the ADC sampling for this channel + * using the pre-calculated timer divider definitions. + * + * Input Parameters: + * priv - A reference to the ADC block status + * + * Returned Value: + * Zero on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int adc_timinit(struct stm32_dev_s *priv) +{ + uint32_t prescaler; + uint32_t reload; + uint32_t timclk; + uint16_t clrbits = 0; + uint16_t setbits = 0; + uint16_t cr2; + uint16_t ccmr1; + uint16_t ccmr2; + uint16_t ocmode1; + uint16_t ocmode2; + uint16_t ccenable; + uint16_t ccer; + uint16_t egr; + + /* If the timer base address is zero, then this ADC was not configured to + * use a timer. + */ + + if (priv->tbase == 0) + { + return ERROR; + } + + /* NOTE: EXTSEL configuration is done in adc_reset function */ + + /* Configure the timer channel to drive the ADC */ + + /* Calculate optimal values for the timer prescaler and for the timer + * reload register. If freq is the desired frequency, then + * + * reload = timclk / freq + * reload = (pclck / prescaler) / freq + * + * There are many solutions to do this, but the best solution will be the + * one that has the largest reload value and the smallest prescaler value. + * That is the solution that should give us the most accuracy in the timer + * control. Subject to: + * + * 0 <= prescaler <= 65536 + * 1 <= reload <= 65535 + * + * So (prescaler = pclck / 65535 / freq) would be optimal. + */ + + prescaler = (priv->pclck / priv->freq + 65534) / 65535; + + /* We need to decrement the prescaler value by one, but only, the value + * does not underflow. + */ + + if (prescaler < 1) + { + awarn("WARNING: Prescaler underflowed.\n"); + prescaler = 1; + } + + /* Check for overflow */ + + else if (prescaler > 65536) + { + awarn("WARNING: Prescaler overflowed.\n"); + prescaler = 65536; + } + + timclk = priv->pclck / prescaler; + + reload = timclk / priv->freq; + if (reload < 1) + { + awarn("WARNING: Reload value underflowed.\n"); + reload = 1; + } + else if (reload > 65535) + { + awarn("WARNING: Reload value overflowed.\n"); + reload = 65535; + } + + /* Disable the timer until we get it configured */ + + adc_timstart(priv, false); + + /* Set up the timer CR1 register. + * + * Select the Counter Mode == count up: + * + * ATIM_CR1_EDGE: The counter counts up or down depending on the + * direction bit(DIR). + * ATIM_CR1_DIR: 0: count up, 1: count down + * + * Set the clock division to zero for all + */ + + clrbits = GTIM_CR1_DIR | GTIM_CR1_CMS_MASK | GTIM_CR1_CKD_MASK; + setbits = GTIM_CR1_EDGE; + tim_modifyreg(priv, STM32_GTIM_CR1_OFFSET, clrbits, setbits); + + /* Set the reload and prescaler values */ + + tim_putreg(priv, STM32_GTIM_PSC_OFFSET, prescaler - 1); + tim_putreg(priv, STM32_GTIM_ARR_OFFSET, reload); + + /* Clear the advanced timers repetition counter in TIM1 */ + + if (priv->tbase == STM32_TIM1_BASE) + { + tim_putreg(priv, STM32_ATIM_RCR_OFFSET, 0); + tim_putreg(priv, STM32_ATIM_BDTR_OFFSET, ATIM_BDTR_MOE); /* Check me */ + } + + /* TIMx event generation: Bit 0 UG: Update generation */ + + tim_putreg(priv, STM32_GTIM_EGR_OFFSET, GTIM_EGR_UG); + + /* Handle channel specific setup */ + + ocmode1 = 0; + ocmode2 = 0; + + switch (priv->trigger) + { + case 0: /* TimerX CC1 event */ + { + ccenable = ATIM_CCER_CC1E; + ocmode1 = (ATIM_CCMR_CCS_CCOUT << ATIM_CCMR1_CC1S_SHIFT) | + (ATIM_CCMR_MODE_PWM1 << ATIM_CCMR1_OC1M_SHIFT) | + ATIM_CCMR1_OC1PE; + + /* Set the event CC1 */ + + egr = ATIM_EGR_CC1G; + + /* Set the duty cycle by writing to the CCR register for this + * channel + */ + + tim_putreg(priv, STM32_GTIM_CCR1_OFFSET, (uint16_t)(reload >> 1)); + } + break; + + case 1: /* TimerX CC2 event */ + { + ccenable = ATIM_CCER_CC2E; + ocmode1 = (ATIM_CCMR_CCS_CCOUT << ATIM_CCMR1_CC2S_SHIFT) | + (ATIM_CCMR_MODE_PWM1 << ATIM_CCMR1_OC2M_SHIFT) | + ATIM_CCMR1_OC2PE; + + /* Set the event CC2 */ + + egr = ATIM_EGR_CC2G; + + /* Set the duty cycle by writing to the CCR register for this + * channel + */ + + tim_putreg(priv, STM32_GTIM_CCR2_OFFSET, (uint16_t)(reload >> 1)); + } + break; + + case 2: /* TimerX CC3 event */ + { + ccenable = ATIM_CCER_CC3E; + ocmode2 = (ATIM_CCMR_CCS_CCOUT << ATIM_CCMR2_CC3S_SHIFT) | + (ATIM_CCMR_MODE_PWM1 << ATIM_CCMR2_OC3M_SHIFT) | + ATIM_CCMR2_OC3PE; + + /* Set the event CC3 */ + + egr = ATIM_EGR_CC3G; + + /* Set the duty cycle by writing to the CCR register for this + * channel + */ + + tim_putreg(priv, STM32_GTIM_CCR3_OFFSET, (uint16_t)(reload >> 1)); + } + break; + + case 3: /* TimerX CC4 event */ + { + ccenable = ATIM_CCER_CC4E; + ocmode2 = (ATIM_CCMR_CCS_CCOUT << ATIM_CCMR2_CC4S_SHIFT) | + (ATIM_CCMR_MODE_PWM1 << ATIM_CCMR2_OC4M_SHIFT) | + ATIM_CCMR2_OC4PE; + + /* Set the event CC4 */ + + egr = ATIM_EGR_CC4G; + + /* Set the duty cycle by writing to the CCR register for this + * channel + */ + + tim_putreg(priv, STM32_GTIM_CCR4_OFFSET, (uint16_t)(reload >> 1)); + } + break; + + case 4: /* TimerX TRGO event */ + { + /* Set the event TRGO */ + + ccenable = 0; + egr = GTIM_EGR_TG; + + tim_modifyreg(priv, STM32_GTIM_CR2_OFFSET, clrbits, + GTIM_CR2_MMS_UPDATE); + } + break; + + case 5: /* TimerX TRGO2 event */ + { + /* Set the event TRGO2 */ + + ccenable = 0; + egr = GTIM_EGR_TG; + + tim_modifyreg32(priv, STM32_GTIM_CR2_OFFSET, clrbits, + ATIM_CR2_MMS2_UPDATE); + } + break; + + default: + aerr("ERROR: No such trigger: %d\n", priv->trigger); + return -EINVAL; + } + + /* Disable the Channel by resetting the CCxE Bit in the CCER register */ + + ccer = tim_getreg(priv, STM32_GTIM_CCER_OFFSET); + ccer &= ~ccenable; + tim_putreg(priv, STM32_GTIM_CCER_OFFSET, ccer); + + /* Fetch the CR2, CCMR1, and CCMR2 register (already have ccer) */ + + cr2 = tim_getreg(priv, STM32_GTIM_CR2_OFFSET); + ccmr1 = tim_getreg(priv, STM32_GTIM_CCMR1_OFFSET); + ccmr2 = tim_getreg(priv, STM32_GTIM_CCMR2_OFFSET); + + /* Reset the Output Compare Mode Bits and set the select output compare + * mode + */ + + ccmr1 &= ~(ATIM_CCMR1_CC1S_MASK | ATIM_CCMR1_OC1M_MASK | ATIM_CCMR1_OC1PE | + ATIM_CCMR1_CC2S_MASK | ATIM_CCMR1_OC2M_MASK | ATIM_CCMR1_OC2PE); + ccmr2 &= ~(ATIM_CCMR2_CC3S_MASK | ATIM_CCMR2_OC3M_MASK | ATIM_CCMR2_OC3PE | + ATIM_CCMR2_CC4S_MASK | ATIM_CCMR2_OC4M_MASK | ATIM_CCMR2_OC4PE); + ccmr1 |= ocmode1; + ccmr2 |= ocmode2; + + /* Reset the output polarity level of all channels (selects high + * polarity) + */ + + ccer &= ~(ATIM_CCER_CC1P | ATIM_CCER_CC2P | + ATIM_CCER_CC3P | ATIM_CCER_CC4P); + + /* Enable the output state of the selected channel (only) */ + + ccer &= ~(ATIM_CCER_CC1E | ATIM_CCER_CC2E | + ATIM_CCER_CC3E | ATIM_CCER_CC4E); + ccer |= ccenable; + + if (priv->tbase == STM32_TIM1_BASE) + { + /* Reset output N polarity level, output N state, output compare state, + * output compare N idle state. + */ + + ccer &= ~(ATIM_CCER_CC1NE | ATIM_CCER_CC1NP | + ATIM_CCER_CC2NE | ATIM_CCER_CC2NP | + ATIM_CCER_CC3NE | ATIM_CCER_CC3NP | + ATIM_CCER_CC4NP); + + /* Reset the output compare and output compare N IDLE State */ + + cr2 &= ~(ATIM_CR2_OIS1 | ATIM_CR2_OIS1N | + ATIM_CR2_OIS2 | ATIM_CR2_OIS2N | + ATIM_CR2_OIS3 | ATIM_CR2_OIS3N | + ATIM_CR2_OIS4); + } + else + { + ccer &= ~(GTIM_CCER_CC1NP | GTIM_CCER_CC2NP | GTIM_CCER_CC3NP); + } + + /* Reset the output compare and output compare N IDLE State */ + + if (priv->tbase >= STM32_TIM2_BASE && priv->tbase <= STM32_TIM3_BASE) + { + /* Reset output N polarity level, output N state, output compare state, + * output compare N idle state. + */ + + ccer &= ~(GTIM_CCER_CC1NE | GTIM_CCER_CC1NP | + GTIM_CCER_CC2NP | GTIM_CCER_CC3NP | + GTIM_CCER_CC4NP); + } + + /* Save the modified register values */ + + tim_putreg(priv, STM32_GTIM_CR2_OFFSET, cr2); + tim_putreg(priv, STM32_GTIM_CCMR1_OFFSET, ccmr1); + tim_putreg(priv, STM32_GTIM_CCMR2_OFFSET, ccmr2); + tim_putreg(priv, STM32_GTIM_CCER_OFFSET, ccer); + tim_putreg(priv, STM32_GTIM_EGR_OFFSET, egr); + + /* Set the ARR Preload Bit */ + + tim_modifyreg(priv, STM32_GTIM_CR1_OFFSET, 0, GTIM_CR1_ARPE); + + /* Enable the timer counter */ + + adc_timstart(priv, true); + + tim_dumpregs(priv, "After starting timers"); + + return OK; +} +#endif + +/**************************************************************************** + * Name: adc_reg_startconv + * + * Description: + * Start (or stop) the ADC regular conversion process + * + * Input Parameters: + * priv - A reference to the ADC block status + * enable - True: Start conversion + * + * Returned Value: + * + ****************************************************************************/ + +static void adc_reg_startconv(struct stm32_dev_s *priv, bool enable) +{ + uint32_t regval; + + ainfo("reg enable: %d\n", enable ? 1 : 0); + + if (enable) + { + /* Start the conversion of regular channels */ + + adc_modifyreg(priv, STM32_ADC_CR_OFFSET, 0, ADC_CR_ADSTART); + } + else + { + regval = adc_getreg(priv, STM32_ADC_CR_OFFSET); + + /* Is a conversion ongoing? */ + + if ((regval & ADC_CR_ADSTART) != 0) + { + /* Stop the conversion */ + + adc_putreg(priv, STM32_ADC_CR_OFFSET, regval | ADC_CR_ADSTP); + + /* Wait for the conversion to stop */ + + while ((adc_getreg(priv, STM32_ADC_CR_OFFSET) & + ADC_CR_ADSTP) != 0); + } + } +} + +/**************************************************************************** + * Name: adc_rccreset + * + * Description: + * Deinitializes the ADCx peripheral registers to their default + * reset values. It could set all the ADCs configured. + * + * Input Parameters: + * regaddr - The register to read + * reset - Condition, set or reset + * + * Returned Value: + * + ****************************************************************************/ + +static void adc_rccreset(struct stm32_dev_s *priv, bool reset) +{ + uint32_t adcbit; + + /* Pick the appropriate bit in the RCC reset register. + * For the STM32 ADC IPv2, there is an individual bit to reset each ADC + * block. + */ + + switch (priv->intf) + { +#if defined(CONFIG_STM32_ADC1) + case 1: + { + adcbit = RCC_RSTR_ADC1RST; + break; + } + +#endif + default: + { + return; + } + } + + /* Set or clear the selected bit in the RCC reset register */ + + if (reset) + { + /* Enable ADC reset state */ + + modifyreg32(STM32_RCC_RSTR, 0, adcbit); + } + else + { + /* Release ADC from reset state */ + + modifyreg32(STM32_RCC_RSTR, adcbit, 0); + } +} + +/**************************************************************************** + * Name: adc_enable + * + * Description: + * Enables or disables the specified ADC peripheral. Also, starts a + * conversion when the ADC is not triggered by timers + * + * Input Parameters: + * + * enable - true: enable ADC conversion + * false: disable ADC conversion + * + * Returned Value: + * + ****************************************************************************/ + +static void adc_enable(struct stm32_dev_s *priv, bool enable) +{ + uint32_t regval; + + ainfo("enable: %d\n", enable ? 1 : 0); + + regval = adc_getreg(priv, STM32_ADC_CR_OFFSET); + + if (enable) + { + /* Enable the ADC */ + + adc_putreg(priv, STM32_ADC_CR_OFFSET, regval | ADC_CR_ADEN); + + /* Wait for the ADC to be ready */ + + while ((adc_getreg(priv, STM32_ADC_ISR_OFFSET) & ADC_INT_ARDY) == 0); + } + else if ((regval & ADC_CR_ADEN) != 0 && (regval & ADC_CR_ADDIS) == 0) + { + /* Stop ongoing regular conversions */ + + adc_reg_startconv(priv, false); + + /* Disable the ADC */ + + adc_putreg(priv, STM32_ADC_CR_OFFSET, regval | ADC_CR_ADDIS); + + /* Wait for the ADC to be disabled */ + + while ((adc_getreg(priv, STM32_ADC_CR_OFFSET) & ADC_CR_ADEN) != 0); + } +} + +/**************************************************************************** + * Name: adc_dmaconvcallback + * + * Description: + * Callback for DMA. Called from the DMA transfer complete interrupt after + * all channels have been converted and transferred with DMA. + * + * Input Parameters: + * + * handle - handle to DMA + * isr - + * arg - adc device + * + * Returned Value: + * + ****************************************************************************/ + +#if defined(ADC_HAVE_DMA) +static void adc_dmaconvcallback(DMA_HANDLE handle, uint8_t isr, + void *arg) +{ + struct adc_dev_s *dev = (struct adc_dev_s *)arg; + struct stm32_dev_s *priv = (struct stm32_dev_s *)dev->ad_priv; + int i; + + /* Verify that the upper-half driver has bound its callback functions */ + + if (priv->cb != NULL) + { + DEBUGASSERT(priv->cb->au_receive != NULL); + + for (i = 0; i < priv->rnchannels * priv->dmabatch; i++) + { + priv->cb->au_receive(dev, priv->r_chanlist[priv->current], + priv->r_dmabuffer[i]); + priv->current++; + if (priv->current >= priv->rnchannels) + { + /* Restart the conversion sequence from the beginning */ + + priv->current = 0; + } + } + } + + /* Restart DMA for the next conversion series */ + + adc_modifyreg(priv, STM32_ADC_DMAREG_OFFSET, ADC_DMAREG_DMA, 0); + adc_modifyreg(priv, STM32_ADC_DMAREG_OFFSET, 0, ADC_DMAREG_DMA); +} +#endif + +/**************************************************************************** + * Name: adc_bind + * + * Description: + * Bind the upper-half driver callbacks to the lower-half implementation. + * This must be called early in order to receive ADC event notifications. + * + ****************************************************************************/ + +static int adc_bind(struct adc_dev_s *dev, + const struct adc_callback_s *callback) +{ +#ifndef CONFIG_STM32_ADC_NOIRQ + struct stm32_dev_s *priv = (struct stm32_dev_s *)dev->ad_priv; + + DEBUGASSERT(priv != NULL); + priv->cb = callback; +#endif + + return OK; +} + +/**************************************************************************** + * Name: adc_watchdog_cfg + ****************************************************************************/ + +static void adc_watchdog_cfg(struct stm32_dev_s *priv) +{ + uint32_t clrbits = 0; + uint32_t setbits = 0; + + uint32_t th = 0; + + /* Initialize the watchdog high threshold register */ + + th |= 0x0fff << ADC_TR_HT_SHIFT; + + /* Initialize the watchdog low threshold register */ + + th |= 0x0000 << ADC_TR_LT_SHIFT; + + /* Write threshold register */ + + adc_putreg(priv, STM32_ADC_TR_OFFSET, th); + + clrbits = ADC_CFGR1_AWDCH_MASK; + setbits = ADC_CFGR1_AWDEN | (priv->r_chanlist[0] << ADC_CFGR1_AWDCH_SHIFT); + + /* Modify CFGR1 configuration */ + + adc_modifyreg(priv, STM32_ADC_CFGR1_OFFSET, clrbits, setbits); +} + +/**************************************************************************** + * Name: adc_calibrate + ****************************************************************************/ + +static void adc_calibrate(struct stm32_dev_s *priv) +{ + /* Calibrate the ADC. + * 1. ADC must be disabled + * 2. the voltage regulator must be enabled + */ + + adc_modifyreg(priv, STM32_ADC_CR_OFFSET, 0, ADC_CR_ADCAL); + + /* Wait for the calibration to complete */ + + while ((adc_getreg(priv, STM32_ADC_CR_OFFSET) & ADC_CR_ADCAL) != 0); +} + +/**************************************************************************** + * Name: adc_mode_cfg + ****************************************************************************/ + +static void adc_mode_cfg(struct stm32_dev_s *priv) +{ + uint32_t clrbits = 0; + uint32_t setbits = 0; + + /* Disable continuous mode and set align to right */ + + clrbits = ADC_CFGR1_CONT | ADC_CFGR1_ALIGN; + + /* Disable external trigger for regular channels */ + + clrbits |= ADC_CFGR1_EXTEN_MASK; + setbits |= ADC_CFGR1_EXTEN_NONE; + +#ifdef CONFIG_STM32_ADC1_CONTINUOUS + setbits |= ADC_CFGR1_CONT; +#endif + + /* Set CFGR configuration */ + + adc_modifyreg(priv, STM32_ADC_CFGR1_OFFSET, clrbits, setbits); +} + +/**************************************************************************** + * Name: adc_voltreg_cfg + ****************************************************************************/ + +static void adc_voltreg_cfg(struct stm32_dev_s *priv) +{ + /* Enable voltage regulator - required by ADC calibration */ + + adc_putreg(priv, STM32_ADC_CR_OFFSET, ADC_CR_ADVREGEN); + + /* Wait for ADC voltage regulator start-up */ + + up_udelay(50); +} + +/**************************************************************************** + * Name: adc_sampletime_cfg + ****************************************************************************/ + +static void adc_sampletime_cfg(struct adc_dev_s *dev) +{ + /* Initialize the same sample time for each ADC. + * During sample cycles channel selection bits must remain unchanged. + */ +#ifdef CONFIG_STM32_ADC_CHANGE_SAMPLETIME + struct adc_sample_time_s time_samples = { +# ifdef STM32_ADC1_SMPR_SMP1 + .smp1 = STM32_ADC1_SMPR_SMP1, +# else + .smp1 = ADC_SMP1_DEFAULT, +# endif + +# ifdef ADC_HAVE_SMPR_SMP2 +# ifdef STM32_ADC1_SMPR_SMP2 + .smp2 = STM32_ADC1_SMPR_SMP2, +# else + .smp2 = ADC_SMP2_DEFAULT, +# endif + +# ifdef STM32_ADC1_SMPR_SMPSEL + .smpsel = STM32_ADC1_SMPR_SMPSEL +# else + .smpsel = ADC_SMPSEL_DEFAULT +# endif +# else + .smp2 = 0, + .smpsel = 0 +# endif + }; + + adc_sampletime_set((struct stm32_adc_dev_s *)dev, &time_samples); + adc_sampletime_write((struct stm32_adc_dev_s *)dev); +#else + struct stm32_dev_s *priv = (struct stm32_dev_s *)dev->ad_priv; + uint32_t setbits = 0; + + /* Configure sample time 1 */ + + setbits |= ADC_SMP1_DEFAULT << ADC_SMPR_SMP1_SHIFT; + +#ifdef ADC_HAVE_SMPR_SMP2 + /* Configure sample time 2 */ + + setbits |= ADC_SMP2_DEFAULT << ADC_SMPR_SMP2_SHIFT; + + /* Configure sample time selection */ + + setbits |= ADC_SMPSEL_DEFAULT << ADC_SMPR_SMPSEL_SHIFT; +#endif + + /* Write SMPR register */ + + adc_putreg(priv, STM32_ADC_SMPR_OFFSET, setbits); +#endif +} + +/**************************************************************************** + * Name: adc_ckmode_cfg + ****************************************************************************/ + +static void adc_ckmode_cfg(struct stm32_dev_s *priv) +{ + uint32_t setbits = 0; + uint32_t clearbits = ADC_CFGR2_CKMODE_MASK; + +#ifdef STM32_ADC_CFGR2_CKMODE + setbits |= STM32_ADC_CFGR2_CKMODE; +#endif + + adc_modifyreg(priv, STM32_ADC_CFGR2_OFFSET, clearbits, setbits); +} + +/**************************************************************************** + * Name: adc_common_cfg + ****************************************************************************/ + +static void adc_common_cfg(struct stm32_dev_s *priv) +{ + uint32_t clrbits = 0; + uint32_t setbits = 0; + +#ifdef STM32_ADC_CCR_PRESC + setbits |= STM32_ADC_CCR_PRESC; +#endif + + /* REVISIT: for now we reset all CCR bits */ + + clrbits |= ADC_CCR_PRESC_MASK | ADC_CCR_VREFEN | + ADC_CCR_TSEN; + +#ifdef HAVE_ADC_VBAT + clrbits |= ADC_CCR_VBATEN; +#endif + +#ifdef HAVE_ADC_VLCD + clrbits |= ADC_CCR_PRESC_MASK; +#endif + +#ifdef HAVE_ADC_VLCD + clrbits |= ADC_CCR_VLCDEN; +#endif + +#ifdef HAVE_ADC_LFM + clrbits |= ADC_CCR_LFMEN; +#endif + + adccmn_modifyreg(priv, STM32_ADC_CCR_OFFSET, clrbits, setbits); +} + +#ifdef ADC_HAVE_DMA +/**************************************************************************** + * Name: adc_dma_cfg + ****************************************************************************/ + +static void adc_dma_cfg(struct stm32_dev_s *priv) +{ + uint32_t clrbits = 0; + uint32_t setbits = 0; + + /* Set DMA mode */ + + if (priv->dmacfg == 0) + { + /* One Shot Mode */ + + clrbits |= ADC_CFGR1_DMACFG; + } + else + { + /* Circular Mode */ + + setbits |= ADC_CFGR1_DMACFG; + } + + /* Enable DMA */ + + setbits |= ADC_CFGR1_DMAEN; + + /* Modify CFGR configuration */ + + adc_modifyreg(priv, STM32_ADC_CFGR1_OFFSET, clrbits, setbits); +} + +/**************************************************************************** + * Name: adc_dma_start + ****************************************************************************/ + +static void adc_dma_start(struct adc_dev_s *dev) +{ + struct stm32_dev_s *priv = (struct stm32_dev_s *)dev->ad_priv; + + /* Stop and free DMA if it was started before */ + + if (priv->dma != NULL) + { + stm32_dmastop(priv->dma); + stm32_dmafree(priv->dma); + } + + priv->dma = stm32_dmachannel(priv->dmachan); + + stm32_dmasetup(priv->dma, + priv->base + STM32_ADC_DR_OFFSET, + (uint32_t)priv->r_dmabuffer, + priv->rnchannels * priv->dmabatch, + ADC_DMA_CONTROL_WORD); + + stm32_dmastart(priv->dma, adc_dmaconvcallback, dev, false); +} +#endif /* ADC_HAVE_DMA */ + +/**************************************************************************** + * Name: adc_configure + ****************************************************************************/ + +static void adc_configure(struct adc_dev_s *dev) +{ + struct stm32_dev_s *priv = (struct stm32_dev_s *)dev->ad_priv; + + /* Turn off the ADC before configuration */ + + adc_enable(priv, false); + + /* Configure voltage regulator if present */ + + adc_voltreg_cfg(priv); + + /* Calibrate ADC */ + + adc_calibrate(priv); + + /* Initialize the ADC watchdog */ + + adc_watchdog_cfg(priv); + + /* Initialize the ADC sample time */ + + adc_sampletime_cfg(dev); + + /* Set ADC working mode */ + + adc_mode_cfg(priv); + + /* Configuration of the channel conversions */ + + if (priv->cr_channels > 0) + { + adc_set_ch(dev, 0); + } + + /* ADC clock mode configuration */ + + adc_ckmode_cfg(priv); + + /* ADC common register configuration */ + + adc_common_cfg(priv); + +#ifdef ADC_HAVE_DMA + /* Configure ADC DMA if enabled */ + + if (priv->hasdma) + { + /* Configure ADC DMA */ + + adc_dma_cfg(priv); + + /* Start ADC DMA */ + + adc_dma_start(dev); + } +#endif + +#ifdef HAVE_ADC_RESOLUTION + /* Configure ADC resolution */ + + adc_resolution_set(dev, priv->resolution); +#endif + +#ifdef ADC_HAVE_EXTCFG + /* Configure external event for regular group */ + + adc_extcfg_set(dev, priv->extcfg); +#endif + + /* Enable ADC */ + + adc_enable(priv, true); + + /* Dump regs */ + + adc_dumpregs(priv); +} + + #ifdef CONFIG_STM32_ADC_OVERSAMPLE + +/**************************************************************************** + * Name: adc_oversample + ****************************************************************************/ + +static void adc_oversample(struct adc_dev_s *dev) +{ + struct stm32_dev_s *priv = (struct stm32_dev_s *)dev->ad_priv; + + uint32_t clrbits = ADC_CFGR2_OVSE | ADC_CFGR2_TOVS | + ADC_CFGR2_OVSR_MASK | ADC_CFGR2_OVSS_MASK; + + uint32_t setbits = ADC_CFGR2_OVSE | + (CONFIG_STM32_ADC_OVSR << ADC_CFGR2_OVSR_SHIFT) | + (CONFIG_STM32_ADC_OVSS << ADC_CFGR2_OVSS_SHIFT); + +# ifdef CONFIG_STM32_ADC_TOVS + setbits |= ADC_CFGR2_TOVS; +# endif + + adc_modifyreg(priv, STM32_ADC_CFGR2_OFFSET, clrbits, setbits); +} +#endif + +/**************************************************************************** + * Name: adc_reset + * + * Description: + * Reset the ADC device. Called early to initialize the hardware. + * This is called, before adc_setup() and on error conditions. + * + * Input Parameters: + * + * Returned Value: + * + ****************************************************************************/ + +static void adc_reset(struct adc_dev_s *dev) +{ + struct stm32_dev_s *priv = (struct stm32_dev_s *)dev->ad_priv; + irqstate_t flags; + + ainfo("intf: %d\n", priv->intf); + flags = enter_critical_section(); + +#if defined(HAVE_IP_ADC_V2) + /* Turn off the ADC so we can write the RCC bits */ + + adc_enable(priv, false); +#endif + + /* Only if this is the first initialzied ADC instance in the ADC block */ + +#ifdef HAVE_ADC_CMN_DATA + if (nxmutex_lock(&priv->cmn->lock) < 0) + { + leave_critical_section(flags); + return; + } + + if (priv->cmn->initialized == 0) +#endif + { + /* Enable ADC reset state */ + + adc_rccreset(priv, true); + + /* Release ADC from reset state */ + + adc_rccreset(priv, false); + } + +#ifdef HAVE_ADC_CMN_DATA + nxmutex_unlock(&priv->cmn->lock); +#endif + + leave_critical_section(flags); +} + +/**************************************************************************** + * Name: adc_setup + * + * Description: + * Configure the ADC. This method is called the first time that the ADC + * device is opened. This will occur when the port is first opened. + * This setup includes configuring and attaching ADC interrupts. + * Interrupts are all disabled upon return. + * + * Input Parameters: + * + * Returned Value: + * + ****************************************************************************/ + +static int adc_setup(struct adc_dev_s *dev) +{ +#if !defined(CONFIG_STM32_ADC_NOIRQ) || defined(HAVE_ADC_CMN_DATA) || \ + defined(ADC_HAVE_TIMER) || !defined(CONFIG_STM32_ADC_NO_STARTUP_CONV) + struct stm32_dev_s *priv = (struct stm32_dev_s *)dev->ad_priv; +#endif + int ret = OK; + + /* Attach the ADC interrupt */ + +#ifndef CONFIG_STM32_ADC_NOIRQ + ret = irq_attach(priv->irq, priv->isr, NULL); + if (ret < 0) + { + ainfo("irq_attach failed: %d\n", ret); + return ret; + } +#endif + + /* Make sure that the ADC device is in the powered up, reset state */ + + adc_reset(dev); + + /* Configure ADC device */ + + adc_configure(dev); + +#ifdef CONFIG_STM32_ADC_OVERSAMPLE + adc_oversample(dev); +#endif + +#ifdef ADC_HAVE_TIMER + /* Configure timer */ + + if (priv->tbase != 0) + { + ret = adc_timinit(priv); + if (ret < 0) + { + aerr("ERROR: adc_timinit failed: %d\n", ret); + } + } +#endif + + /* As default conversion is started here. + * + * NOTE: for ADC IPv2 (J)ADSTART bit must be set to start ADC conversion + * even if hardware trigger is selected. + * This can be done here during the opening of the ADC device + * or later with ANIOC_TRIGGER ioctl call. + */ + +#ifndef CONFIG_STM32_ADC_NO_STARTUP_CONV + /* Start regular conversion */ + + adc_reg_startconv(priv, true); + +#endif + + /* Enable the ADC interrupt */ + +#ifndef CONFIG_STM32_ADC_NOIRQ + ainfo("Enable the ADC interrupt: irq=%d\n", priv->irq); + up_enable_irq(priv->irq); +#endif + +#ifdef HAVE_ADC_CMN_DATA + /* Increase instances counter */ + + ret = nxmutex_lock(&priv->cmn->lock); + if (ret < 0) + { + return; + } + + priv->cmn->initialized += 1; + nxmutex_unlock(&priv->cmn->lock); +#endif + + return ret; +} + +/**************************************************************************** + * Name: adc_shutdown + * + * Description: + * Disable the ADC. This method is called when the ADC device is closed. + * This method reverses the operation the setup method. + * + * Input Parameters: + * + * Returned Value: + * + ****************************************************************************/ + +static void adc_shutdown(struct adc_dev_s *dev) +{ + struct stm32_dev_s *priv = (struct stm32_dev_s *)dev->ad_priv; + + /* Disable ADC */ + + adc_enable(priv, false); + +#ifndef CONFIG_STM32_ADC_NOIRQ + /* Disable ADC interrupts and detach the ADC interrupt handler */ + + up_disable_irq(priv->irq); + irq_detach(priv->irq); +#endif + +#ifdef HAVE_ADC_CMN_DATA + if (nxmutex_lock(&priv->cmn->lock) < 0) + { + return; + } + + if (priv->cmn->initialized <= 1) +#endif + { + /* Disable and reset the ADC module. + * + * NOTE: The ADC block will be reset to its reset state only if all + * ADC block instances are closed. This means that the closed ADC + * may not be reset which in turn may affect low-power + * applications. (But ADC is turned off here, is not that + * enough?) + */ + + adc_rccreset(priv, true); + } + +#ifdef ADC_HAVE_TIMER + /* Disable timer */ + + if (priv->tbase != 0) + { + adc_timstart(priv, false); + } +#endif + +#ifdef HAVE_ADC_CMN_DATA + /* Decrease instances counter */ + + priv->cmn->initialized -= 1; + nxmutex_unlock(&priv->cmn->lock); +#endif +} + +/**************************************************************************** + * Name: adc_rxint + * + * Description: + * Call to enable or disable RX interrupts. + * + * Input Parameters: + * + * Returned Value: + * + ****************************************************************************/ + +static void adc_rxint(struct adc_dev_s *dev, bool enable) +{ + struct stm32_dev_s *priv = (struct stm32_dev_s *)dev->ad_priv; + uint32_t regval; + + ainfo("intf: %d enable: %d\n", priv->intf, enable ? 1 : 0); + + if (enable) + { + /* Enable the analog watchdog / overrun interrupts, and if no DMA, + * end-of-conversion ADC. + */ + + regval = ADC_IER_ALLINTS; +#ifdef ADC_HAVE_DMA + if (priv->hasdma) + { + regval &= ~(ADC_IER_EOC); + } +#endif + + adc_modifyreg(priv, STM32_ADC_IER_OFFSET, 0, regval); + } + else + { + /* Disable all ADC interrupts */ + + adc_modifyreg(priv, STM32_ADC_IER_OFFSET, ADC_IER_ALLINTS, 0); + } +} + +/**************************************************************************** + * Name: adc_resolution_set + ****************************************************************************/ + +#ifdef HAVE_ADC_RESOLUTION +static int adc_resolution_set(struct adc_dev_s *dev, uint8_t res) +{ + struct stm32_dev_s *priv = (struct stm32_dev_s *)dev->ad_priv; + int ret = OK; + + /* Check input */ + + if (res > 3) + { + ret = -EINVAL; + goto errout; + } + + /* Modify appropriate register */ + + adc_modifyreg(priv, STM32_ADC_CFGR1_OFFSET, ADC_CFGR1_RES_MASK, + res << ADC_CFGR1_RES_SHIFT); + +errout: + return ret; +} +#endif + +/**************************************************************************** + * Name: adc_extsel_set + ****************************************************************************/ + +#ifdef ADC_HAVE_EXTCFG +static int adc_extcfg_set(struct adc_dev_s *dev, uint32_t extcfg) +{ + struct stm32_dev_s *priv = (struct stm32_dev_s *)dev->ad_priv; + uint32_t exten = 0; + uint32_t extsel = 0; + uint32_t setbits = 0; + uint32_t clrbits = 0; + + /* Get EXTEN and EXTSEL from input */ + + exten = (extcfg & ADC_EXTREG_EXTEN_MASK); + extsel = (extcfg & ADC_EXTREG_EXTSEL_MASK); + + /* EXTSEL selection: These bits select the external event used + * to trigger the start of conversion of a regular group. NOTE: + * + * - The position with of the EXTSEL field varies from one STM32 MCU + * to another. + * - The width of the EXTSEL field varies from one STM32 MCU to another. + */ + + if (exten > 0) + { + setbits = (extsel | exten); + clrbits = (ADC_EXTREG_EXTEN_MASK | ADC_EXTREG_EXTSEL_MASK); + + ainfo("Initializing extsel = 0x%" PRIx32 "\n", extsel); + + /* Write register */ + + adc_modifyreg(priv, STM32_ADC_EXTREG_OFFSET, clrbits, setbits); + } + + return OK; +} +#endif + +/**************************************************************************** + * Name: adc_dumpregs + ****************************************************************************/ + +static void adc_dumpregs(struct stm32_dev_s *priv) +{ + UNUSED(priv); + + ainfo("ISR: 0x%08" PRIx32 " IER: 0x%08" PRIx32 + " CR: 0x%08" PRIx32 " CFGR1: 0x%08" PRIx32 "\n", + adc_getreg(priv, STM32_ADC_ISR_OFFSET), + adc_getreg(priv, STM32_ADC_IER_OFFSET), + adc_getreg(priv, STM32_ADC_CR_OFFSET), + adc_getreg(priv, STM32_ADC_CFGR1_OFFSET)); + + ainfo("SMPR: 0x%08" PRIx32 " CHSELR: 0x%08" PRIx32 "\n", + adc_getreg(priv, STM32_ADC_SMPR_OFFSET), + adc_getreg(priv, STM32_ADC_CHSELR_OFFSET)); + + ainfo("CCR: 0x%08" PRIx32 "\n", + adccmn_getreg(priv, STM32_ADC_CCR_OFFSET)); +} + +/**************************************************************************** + * Name: adc_enable_vbat_channel + * + * Description: + * Enable/disable the Vbat voltage measurement channel. + * + * Input Parameters: + * dev - pointer to device structure used by the driver + * enable - true: Vbat input channel enabled (ch 18) + * false: Vbat input channel disabled (ch 18) + * + * Returned Value: + * None. + * + ****************************************************************************/ + +#ifdef HAVE_ADC_VBAT +static void adc_enable_vbat_channel(struct adc_dev_s *dev, bool enable) +{ + struct stm32_dev_s *priv = (struct stm32_dev_s *)dev->ad_priv; + + if (enable) + { + adccmn_modifyreg(priv, STM32_ADC_CCR_OFFSET, 0, ADC_CCR_VBATEN); + } + else + { + adccmn_modifyreg(priv, STM32_ADC_CCR_OFFSET, ADC_CCR_VBATEN, 0); + } + + ainfo("STM32_ADC_CCR value: 0x%08" PRIx32 "\n", + adccmn_getreg(priv, STM32_ADC_CCR_OFFSET)); +} +#endif + +/**************************************************************************** + * Name: adc_ioc_change_sleep_between_opers + * + * Description: + * Changes PDI and PDD bits to save battery. + * + * Input Parameters: + * dev - pointer to device structure used by the driver + * cmd - command + * arg - arguments passed with command + * + * Returned Value: + * + ****************************************************************************/ + +#ifdef HAVE_ADC_POWERDOWN +static int adc_ioc_change_sleep_between_opers(struct adc_dev_s *dev, + int cmd, bool arg) +{ + int ret = OK; + struct stm32_dev_s *priv = (struct stm32_dev_s *)dev->ad_priv; + + adc_enable(priv, false); + + switch (cmd) + { + case IO_ENABLE_DISABLE_PDI: + adc_power_down_idle(priv, arg); + break; + + case IO_ENABLE_DISABLE_PDD: + adc_power_down_delay(priv, arg); + break; + + case IO_ENABLE_DISABLE_PDD_PDI: + adc_power_down_idle(priv, arg); + adc_power_down_delay(priv, arg); + break; + + default: + ainfo("unknown cmd: %d\n", cmd); + break; + } + + adc_enable(priv, true); + + return ret; +} +#endif + +/**************************************************************************** + * Name: adc_ioc_enable_awd_int + * + * Description: + * Turns ON/OFF ADC analog watchdog interrupt. + * + * Input Parameters: + * dev - pointer to device structure used by the driver + * arg - true: Turn ON interrupt + * false: Turn OFF interrupt + * + * Returned Value: + * + ****************************************************************************/ + +static void adc_ioc_enable_awd_int(struct stm32_dev_s *priv, bool enable) +{ + if (enable) + { + adc_modifyreg(priv, STM32_ADC_IER_OFFSET, 0, ADC_IER_AWD); + } + else + { + adc_modifyreg(priv, STM32_ADC_IER_OFFSET, ADC_IER_AWD, 0); + } +} + +/**************************************************************************** + * Name: adc_ioc_enable_eoc_int + * + * Description: + * Turns ON/OFF ADC EOC interrupt. + * + * Input Parameters: + * dev - pointer to device structure used by the driver + * arg - true: Turn ON interrupt + * false: Turn OFF interrupt + * + * Returned Value: + * + ****************************************************************************/ + +static void adc_ioc_enable_eoc_int(struct stm32_dev_s *priv, bool enable) +{ + if (enable) + { + adc_modifyreg(priv, STM32_ADC_IER_OFFSET, 0, ADC_IER_EOC); + } + else + { + adc_modifyreg(priv, STM32_ADC_IER_OFFSET, ADC_IER_EOC, 0); + } +} + +/**************************************************************************** + * Name: adc_ioc_enable_ovr_int + * + * Description: + * Turns ON/OFF ADC overrun interrupt. + * + * Input Parameters: + * dev - pointer to device structure used by the driver + * arg - true: Turn ON interrupt + * false: Turn OFF interrupt + * + * Returned Value: + * + ****************************************************************************/ + +static void adc_ioc_enable_ovr_int(struct stm32_dev_s *priv, bool enable) +{ + if (enable) + { + adc_modifyreg(priv, STM32_ADC_IER_OFFSET, 0, ADC_IER_OVR); + } + else + { + adc_modifyreg(priv, STM32_ADC_IER_OFFSET, ADC_IER_OVR, 0); + } +} + +/**************************************************************************** + * Name: adc_ioc_change_ints + * + * Description: + * Turns ON/OFF ADC interrupts. + * + * Input Parameters: + * dev - pointer to device structure used by the driver + * cmd - command + * arg - arguments passed with command + * + * Returned Value: + * + ****************************************************************************/ + +static int adc_ioc_change_ints(struct adc_dev_s *dev, int cmd, bool arg) +{ + int ret = OK; + struct stm32_dev_s *priv = (struct stm32_dev_s *)dev->ad_priv; + + switch (cmd) + { + case IO_ENABLE_DISABLE_AWDIE: + adc_ioc_enable_awd_int(priv, arg); + break; + + case IO_ENABLE_DISABLE_EOCIE: + adc_ioc_enable_eoc_int(priv, arg); + break; + + case IO_ENABLE_DISABLE_OVRIE: + adc_ioc_enable_ovr_int(priv, arg); + break; + + case IO_ENABLE_DISABLE_ALL_INTS: + adc_ioc_enable_awd_int(priv, arg); + adc_ioc_enable_eoc_int(priv, arg); + adc_ioc_enable_ovr_int(priv, arg); + break; + + default: + ainfo("unknown cmd: %d\n", cmd); + break; + } + + return ret; +} +#ifdef CONFIG_STM32_ADC_OVERSAMPLE + +/**************************************************************************** + * Name: adc_ioc_set_oversample + * + * Description: + * For STM32G0 and STM32L0: Configure hardware oversampling via CFGR2. + * + * Input: + * dev - pointer to the ADC device + * arg - Packed 32-bit value that matches CFGR2 layout for OVSE, TOVS, + * OVSR[2:0] and OVSS[3:0]. + * + * Bit fields (match ADC_CFGR2 register layout): + * [0] = OVSE (enable oversampling) + * [1] = TOVS (triggered oversampling) + * [4:2] = OVSR (ratio: 000=2x, ..., 111=256x) + * [9:5] = OVSS (right shift: 00000=no shift, ..., 11111=31-bit) + * + * Returned Value: + * OK (0) on success + * + ****************************************************************************/ + +static int adc_ioc_set_oversample(struct adc_dev_s *dev, uint32_t arg) +{ + struct stm32_dev_s *priv = (struct stm32_dev_s *)dev->ad_priv; + uint32_t clrbits; + uint32_t setbits; + + /* Mask out the oversampling-related fields from CFGR2: + * OVSE | TOVS | OVSR[2:0] | OVSS[3:0] + */ + + clrbits = ADC_CFGR2_OVSE | + ADC_CFGR2_TOVS | + ADC_CFGR2_OVSR_MASK | + ADC_CFGR2_OVSS_MASK; + + setbits = arg & (ADC_CFGR2_OVSE | + ADC_CFGR2_TOVS | + ADC_CFGR2_OVSR_MASK | + ADC_CFGR2_OVSS_MASK); + + adc_modifyreg(priv, STM32_ADC_CFGR2_OFFSET, clrbits, setbits); + return OK; +} + +#endif /* G0 or L0 */ + +/**************************************************************************** + * Name: adc_set_ch + * + * Description: + * Sets the ADC channel. + * + * Input Parameters: + * dev - pointer to device structure used by the driver + * ch - ADC channel number + 1. 0 reserved for all configured channels + * + * Returned Value: + * int - errno + * + ****************************************************************************/ + +static int adc_set_ch(struct adc_dev_s *dev, uint8_t ch) +{ + struct stm32_dev_s *priv = (struct stm32_dev_s *)dev->ad_priv; + uint32_t bits = 0; + int i = 0; + + if (ch == 0) + { + priv->current = 0; + priv->rnchannels = priv->cr_channels; + } + else + { + for (i = 0; i < priv->cr_channels && priv->r_chanlist[i] != ch - 1; + i++); + + if (i >= priv->cr_channels) + { + return -ENODEV; + } + + priv->current = i; + priv->rnchannels = 1; + } + + for (i = 0; i < priv->rnchannels; i += 1) + { + bits |= ADC_CHSELR_CHSEL(priv->r_chanlist[i]); + } + + /* Write register */ + + adc_modifyreg(priv, STM32_ADC_CHSELR_OFFSET, 0, bits); + + return OK; +} + +/**************************************************************************** + * Name: adc_ioctl + * + * Description: + * All ioctl calls will be routed through this method. + * + * Input Parameters: + * dev - pointer to device structure used by the driver + * cmd - command + * arg - arguments passed with command + * + * Returned Value: + * + ****************************************************************************/ + +static int adc_ioctl(struct adc_dev_s *dev, int cmd, unsigned long arg) +{ + struct stm32_dev_s *priv = (struct stm32_dev_s *)dev->ad_priv; + int ret = OK; + + switch (cmd) + { + case ANIOC_TRIGGER: + { + /* Start regular conversion if regular channels configured */ + + if (priv->cr_channels > 0) + { + adc_reg_startconv(priv, true); + } + + break; + } + + case ANIOC_GET_NCHANNELS: + { + /* Return the number of configured channels */ + + ret = priv->cr_channels; + } + + break; + + case IO_TRIGGER_REG: + { + /* Start regular conversion if regular channels configured */ + + if (priv->cr_channels > 0) + { + adc_reg_startconv(priv, true); + } + + break; + } + + case IO_ENABLE_DISABLE_AWDIE: + case IO_ENABLE_DISABLE_EOCIE: + case IO_ENABLE_DISABLE_OVRIE: + case IO_ENABLE_DISABLE_ALL_INTS: + { + adc_ioc_change_ints(dev, cmd, *(bool *)arg); + break; + } + +#ifdef HAVE_ADC_VBAT + case IO_ENABLE_DISABLE_VBAT_CH: + { + adc_enable_vbat_channel(dev, *(bool *)arg); + break; + } +#endif + +#ifdef HAVE_ADC_POWERDOWN + case IO_ENABLE_DISABLE_PDI: + case IO_ENABLE_DISABLE_PDD: + case IO_ENABLE_DISABLE_PDD_PDI: + { + adc_ioc_change_sleep_between_opers(dev, cmd, *(bool *)arg); + break; + } +#endif + + case IO_STOP_ADC: + { + adc_enable(priv, false); + break; + } + + case IO_START_ADC: + { + adc_enable(priv, true); + break; + } + + case IO_START_CONV: + { + uint8_t ch = ((uint8_t)arg); + + ret = adc_set_ch(dev, ch); + if (ret < 0) + { + return ret; + } + +#ifdef CONFIG_ADC + if (ch) + { + /* Clear fifo if upper-half driver enabled */ + + dev->ad_recv.af_head = 0; + dev->ad_recv.af_tail = 0; + } +#endif + + adc_reg_startconv(priv, true); + break; + } + +#if defined(CONFIG_STM32_ADC_OVERSAMPLE) + case ANIOC_SET_OVERSAMPLE: + { + ret = adc_ioc_set_oversample(dev, arg); + break; + } +#endif + + default: + { + aerr("ERROR: Unknown cmd: %d\n", cmd); + ret = -ENOTTY; + break; + } + } + + return ret; +} + +#ifndef CONFIG_STM32_ADC_NOIRQ + +/**************************************************************************** + * Name: adc_interrupt + * + * Description: + * Common ADC interrupt handler. + * + * Input Parameters: + * + * Returned Value: + * + ****************************************************************************/ + +static int adc_interrupt(struct adc_dev_s *dev) +{ + struct stm32_dev_s *priv = (struct stm32_dev_s *)dev->ad_priv; + uint32_t regval; + uint32_t pending; + int32_t data; + + regval = adc_getreg(priv, STM32_ADC_ISR_OFFSET); + pending = regval & ADC_ISR_ALLINTS; + if (pending == 0) + { + return OK; + } + + /* Identifies the interruption AWD, OVR or EOC */ + + if ((regval & ADC_ISR_AWD) != 0) + { + awarn("WARNING: Analog Watchdog, Value converted out of range!\n"); + } + + if ((regval & ADC_ISR_OVR) != 0) + { + awarn("WARNING: Overrun has occurred!\n"); + } + + /* EOC: End of conversion */ + + if ((regval & ADC_ISR_EOC) != 0) + { + /* Read the converted value and clear EOC bit + * (It is cleared by reading the ADC_DR) + */ + + data = adc_getreg(priv, STM32_ADC_DR_OFFSET) & ADC_DR_RDATA_MASK; + + /* Verify that the upper-half driver has bound its callback functions */ + + if (priv->cb != NULL) + { + /* Give the ADC data to the ADC driver. The ADC receive() method + * accepts 3 parameters: + * + * 1) The first is the ADC device instance for this ADC block. + * 2) The second is the channel number for the data, and + * 3) The third is the converted data for the channel. + */ + + DEBUGASSERT(priv->cb->au_receive != NULL); + priv->cb->au_receive(dev, priv->r_chanlist[priv->current], data); + } + + /* Set the channel number of the next channel that will complete + * conversion. + */ + + priv->current++; + + if (priv->current >= priv->rnchannels) + { + /* Restart the conversion sequence from the beginning */ + + priv->current = 0; + } + } + + /* Clear pending interrupts */ + + adc_putreg(priv, STM32_ADC_ISR_OFFSET, pending); + + return OK; +} + +/**************************************************************************** + * Name: adc1_interrupt + * + * Description: + * ADC interrupt handler for the STM32 L15XX family. + * + * Input Parameters: + * irq - The IRQ number that generated the interrupt. + * context - Architecture specific register save information. + * + * Returned Value: + * + ****************************************************************************/ + +static int adc1_interrupt(int irq, void *context, void *arg) +{ + adc_interrupt(&g_adcdev1); + + return OK; +} +#endif /* CONFIG_STM32_ADC_NOIRQ */ + +#ifdef CONFIG_STM32_ADC_LL_OPS + +/**************************************************************************** + * Name: adc_llops_intack + ****************************************************************************/ + +static void adc_llops_intack(struct stm32_adc_dev_s *dev, + uint32_t source) +{ + struct stm32_dev_s *priv = (struct stm32_dev_s *)dev; + + /* Clear pending interrupts */ + +#ifdef HAVE_IP_ADC_V2 + /* Cleared by writing 1 to it */ + + adc_putreg(priv, STM32_ADC_ISR_OFFSET, (source & ADC_ISR_ALLINTS)); +#else + /* Cleared by writing 0 to it */ + + adc_modifyreg(priv, STM32_ADC_ISR_OFFSET, (source & ADC_ISR_ALLINTS), 0); +#endif +} + +/**************************************************************************** + * Name: adc_llops_inten + ****************************************************************************/ + +static void adc_llops_inten(struct stm32_adc_dev_s *dev, uint32_t source) +{ + struct stm32_dev_s *priv = (struct stm32_dev_s *)dev; + + /* Enable interrupts */ + + adc_modifyreg(priv, STM32_ADC_IER_OFFSET, 0, (source & ADC_IER_ALLINTS)); +} + +/**************************************************************************** + * Name: adc_llops_intdis + ****************************************************************************/ + +static void adc_llops_intdis(struct stm32_adc_dev_s *dev, + uint32_t source) +{ + struct stm32_dev_s *priv = (struct stm32_dev_s *)dev; + + /* Disable interrupts */ + + adc_modifyreg(priv, STM32_ADC_IER_OFFSET, (source & ADC_IER_ALLINTS), 0); +} + +/**************************************************************************** + * Name: adc_ackget + ****************************************************************************/ + +static uint32_t adc_llops_intget(struct stm32_adc_dev_s *dev) +{ + struct stm32_dev_s *priv = (struct stm32_dev_s *)dev; + uint32_t regval; + uint32_t pending; + + regval = adc_getreg(priv, STM32_ADC_ISR_OFFSET); + pending = regval & ADC_ISR_ALLINTS; + + return pending; +} + +/**************************************************************************** + * Name: adc_llops_regget + ****************************************************************************/ + +static uint32_t adc_llops_regget(struct stm32_adc_dev_s *dev) +{ + struct stm32_dev_s *priv = (struct stm32_dev_s *)dev; + + return adc_getreg(priv, STM32_ADC_DR_OFFSET) & ADC_DR_RDATA_MASK; +} + +/**************************************************************************** + * Name: adc_llops_reg_startconv + ****************************************************************************/ + +static void adc_llops_reg_startconv(struct stm32_adc_dev_s *dev, + bool enable) +{ + struct stm32_dev_s *priv = (struct stm32_dev_s *)dev; + + adc_reg_startconv(priv, enable); +} + +/**************************************************************************** + * Name: adc_llops_regbufregister + ****************************************************************************/ + +#ifdef ADC_HAVE_DMA +static int adc_llops_regbufregister(struct stm32_adc_dev_s *dev, + uint16_t *buffer, uint8_t len) +{ + struct stm32_dev_s *priv = (struct stm32_dev_s *)dev; + + stm32_dmasetup(priv->dma, + priv->base + STM32_ADC_DR_OFFSET, + (uint32_t)buffer, + len, + ADC_DMA_CONTROL_WORD); + + /* No DMA callback */ + + stm32_dmastart(priv->dma, NULL, dev, false); + + return OK; +} +#endif /* ADC_HAVE_DMA */ + +#ifdef CONFIG_STM32_ADC_CHANGE_SAMPLETIME +/**************************************************************************** + * Name: adc_sampletime_write + * + * Description: + * Writes previously defined values into ADC_SMPRx registers. + * + * Input Parameters: + * + * Returned Value: + * + ****************************************************************************/ + +static void adc_sampletime_write(struct stm32_adc_dev_s *dev) +{ + struct stm32_dev_s *priv = (struct stm32_dev_s *)dev; + uint32_t smpr = 0; + + smpr |= ((uint32_t)priv->sample_rate[0] << ADC_SMPR_SMP1_SHIFT); + +#ifdef ADC_HAVE_SMPR_SMP2 + smpr |= ((uint32_t)priv->sample_rate[1] << ADC_SMPR_SMP2_SHIFT); + smpr |= ((uint32_t)priv->smpsel << ADC_SMPR_SMPSEL_SHIFT); +#endif + + adc_putreg(priv, STM32_ADC_SMPR_OFFSET, smpr); +} + +/**************************************************************************** + * Name: adc_change_sample_time + * + * Description: + * Changes sample times for specified channels. This method + * doesn't make any register writing. So, it's only stores the information. + * Values provided by user will be written in registers only on the next + * ADC peripheral start, as it was told to do in manual. However, before + * very first start, user can call this method and override default values + * either for every channels or for only some predefined by user channel(s) + * + * Input Parameters: + * priv - pointer to the adc device structure + * pdi_high - true: The ADC is powered down when waiting for a start event + * false: The ADC is powered up when waiting for a start event + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void adc_sampletime_set(struct stm32_adc_dev_s *dev, + struct adc_sample_time_s *time_samples) +{ + struct stm32_dev_s *priv = (struct stm32_dev_s *)dev; + + priv->sample_rate[0] = time_samples->smp1; +#ifdef ADC_HAVE_SMPR_SMP2 + priv->sample_rate[1] = time_samples->smp2; + priv->smpsel = time_samples->smpsel; +#endif +} +#endif /* CONFIG_STM32_ADC_CHANGE_SAMPLETIME */ + +/**************************************************************************** + * Name: adc_llops_dumpregs + ****************************************************************************/ + +static void adc_llops_dumpregs(struct stm32_adc_dev_s *dev) +{ + struct stm32_dev_s *priv = (struct stm32_dev_s *)dev; + + adc_dumpregs(priv); +} + +#endif /* CONFIG_STM32_ADC_LL_OPS */ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_adc_initialize + * + * Description: + * Initialize the ADC. + * + * Input Parameters: + * intf - Could be {1} for ADC1 + * chanlist - The list of channels + * channels - Number of channels + * + * Returned Value: + * Valid ADC device structure reference on success; a NULL on failure + * + ****************************************************************************/ + +struct adc_dev_s *stm32_adcinitialize(int intf, const uint8_t *chanlist, + int channels) +{ + struct adc_dev_s *dev; + struct stm32_dev_s *priv; + + ainfo("intf: %d cchannels: %d\n", intf, channels); + + switch (intf) + { +#ifdef CONFIG_STM32_ADC1 + case 1: + { + ainfo("ADC1 selected\n"); + dev = &g_adcdev1; + break; + } + +#endif + default: + { + aerr("ERROR: No ADC interface defined\n"); + return NULL; + } + } + + /* Configure the selected ADC */ + + priv = (struct stm32_dev_s *)dev->ad_priv; + priv->cb = NULL; + + DEBUGASSERT(channels <= CONFIG_STM32_ADC_MAX_SAMPLES); + + priv->cr_channels = channels; + memcpy(priv->r_chanlist, chanlist, channels); + +#ifdef CONFIG_PM + if (pm_register(&priv->pm_callback) != OK) + { + aerr("Power management registration failed\n"); + return NULL; + } +#endif + + return dev; +} + +#endif /* CONFIG_STM32_ADC1 */ +#endif /* CONFIG_STM32_ADC */ diff --git a/arch/arm/src/common/stm32/stm32_adc_m0_v1.h b/arch/arm/src/common/stm32/stm32_adc_m0_v1.h new file mode 100644 index 0000000000000..1cd50f60f7c5b --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_adc_m0_v1.h @@ -0,0 +1,448 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_adc_m0_v1.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_ADC_V2_M0_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_ADC_V2_M0_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "chip.h" + +#include +#include + +#include "hardware/stm32_adc.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* Timer devices may be used for different purposes. One special purpose is + * to control periodic ADC sampling. If CONFIG_STM32_TIMn is defined + * then CONFIG_STM32_TIMn_ADC must also be defined to indicate that + * timer "n" is intended to be used for that purpose. Timers 1-6 and 8 may + * be used. + */ + +#ifndef CONFIG_STM32_TIM1 +# undef CONFIG_STM32_TIM1_ADC +# undef CONFIG_STM32_TIM1_ADC1 +#endif +#ifndef CONFIG_STM32_TIM2 +# undef CONFIG_STM32_TIM2_ADC +# undef CONFIG_STM32_TIM2_ADC1 +#endif +#ifndef CONFIG_STM32_TIM3 +# undef CONFIG_STM32_TIM3_ADC +# undef CONFIG_STM32_TIM3_ADC1 +#endif +#ifndef CONFIG_STM32_TIM15 +# undef CONFIG_STM32_TIM15_ADC +# undef CONFIG_STM32_TIM15_ADC1 +#endif + +/* Up to 1 ADC interfaces are supported */ + +#if STM32_NADC < 1 +# undef CONFIG_STM32_ADC1 +#endif + +#if defined(CONFIG_STM32_ADC1) + +/* DMA support */ + +#undef ADC_HAVE_DMA +#if defined(CONFIG_STM32_ADC1_DMA) +# define ADC_HAVE_DMA 1 +#endif + +#ifdef CONFIG_STM32_ADC1_DMA +# define ADC1_HAVE_DMA 1 +#else +# undef ADC1_HAVE_DMA +#endif + +/* Timer configuration: If a timer trigger is specified, then get + * information about the timer. + */ + +#if defined(CONFIG_STM32_TIM1_ADC1) +# define ADC1_HAVE_TIMER 1 +# define ADC1_TIMER_BASE STM32_TIM1_BASE +# define ADC1_TIMER_PCLK_FREQUENCY STM32_APB2_TIM1_CLKIN +#elif defined(CONFIG_STM32_TIM2_ADC1) +# define ADC1_HAVE_TIMER 1 +# define ADC1_TIMER_BASE STM32_TIM2_BASE +# define ADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM2_CLKIN +#elif defined(CONFIG_STM32_TIM3_ADC1) +# define ADC1_HAVE_TIMER 1 +# define ADC1_TIMER_BASE STM32_TIM3_BASE +# define ADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM3_CLKIN +#elif defined(CONFIG_STM32_TIM15_ADC1) +# define ADC1_HAVE_TIMER 1 +# define ADC1_TIMER_BASE STM32_TIM15_BASE +# define ADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM15_CLKIN +#else +# undef ADC1_HAVE_TIMER +#endif + +#ifdef ADC1_HAVE_TIMER +# ifndef CONFIG_STM32_ADC1_SAMPLE_FREQUENCY +# error "CONFIG_STM32_ADC1_SAMPLE_FREQUENCY not defined" +# endif +# ifndef CONFIG_STM32_ADC1_TIMTRIG +# error "CONFIG_STM32_ADC1_TIMTRIG not defined" +# warning "Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO 5:TRGO2" +# endif +#endif + +#if defined(ADC1_HAVE_TIMER) +# define ADC_HAVE_TIMER 1 +#else +# undef ADC_HAVE_TIMER +#endif + +/* EXTSEL */ + +#if defined(CONFIG_STM32_STM32F0) +# define ADC1_EXTSEL_T1TRGO ADC12_CFGR1_EXTSEL_TRG0 +# define ADC1_EXTSEL_T1CC4 ADC12_CFGR1_EXTSEL_TRG1 +# define ADC1_EXTSEL_T2TRGO ADC12_CFGR1_EXTSEL_TRG2 +# define ADC1_EXTSEL_T3TRGO ADC12_CFGR1_EXTSEL_TRG3 +# define ADC1_EXTSEL_T15TRGO ADC12_CFGR1_EXTSEL_TRG4 + /* TRG5 reserved + * TRG6 reserved + * TRG7 reserved + */ +#elif defined(CONFIG_STM32_STM32L0) + /* TRG0 reserved */ +# define ADC1_EXTSEL_T21CC2 ADC12_CFGR1_EXTSEL_TRG1 +# define ADC1_EXTSEL_T2TRGO ADC12_CFGR1_EXTSEL_TRG2 +# define ADC1_EXTSEL_T2CC4 ADC12_CFGR1_EXTSEL_TRG3 +# define ADC1_EXTSEL_T21TRGO ADC12_CFGR1_EXTSEL_TRG4 +# define ADC1_EXTSEL_T2CC3 ADC12_CFGR1_EXTSEL_TRG5 + /* TRG6 reserved */ +# define ADC1_EXTSEL_EXTI11 ADC12_CFGR1_EXTSEL_TRG7 +#elif defined(CONFIG_STM32_STM32G0) +# define ADC1_EXTSEL_T1TRGO2 ADC12_CFGR1_EXTSEL_TRG0 +# define ADC1_EXTSEL_T1CC4 ADC12_CFGR1_EXTSEL_TRG1 +# define ADC1_EXTSEL_T2TRGO ADC12_CFGR1_EXTSEL_TRG2 +# define ADC1_EXTSEL_T3TRGO ADC12_CFGR1_EXTSEL_TRG3 +# define ADC1_EXTSEL_T15TRGO ADC12_CFGR1_EXTSEL_TRG4 + /* TRG5 and TRG6 reserved */ +# define ADC1_EXTSEL_EXTI11 ADC12_CFGR1_EXTSEL_TRG7 +#elif defined(CONFIG_STM32_STM32C0) +# define ADC1_EXTSEL_T1TRGO2 ADC12_CFGR1_EXTSEL_TRG0 +# define ADC1_EXTSEL_T1CC4 ADC12_CFGR1_EXTSEL_TRG1 +# define ADC1_EXTSEL_T2TRGO ADC12_CFGR1_EXTSEL_TRG2 +# define ADC1_EXTSEL_T3TRGO ADC12_CFGR1_EXTSEL_TRG3 +# define ADC1_EXTSEL_T15TRGO ADC12_CFGR1_EXTSEL_TRG4 + /* TRG5 and TRG6 reserved */ +# define ADC1_EXTSEL_EXTI11 ADC12_CFGR1_EXTSEL_TRG7 +#else +# error "Unrecognized STM32 M0 sub-family for ADC EXTSEL" +#endif + +/* EXTSEL configuration *****************************************************/ + +/* NOTE: + * this configuration if used only if CONFIG_STM32_TIMx_ADCy is + * selected. + * You can still connect the ADC with a timer trigger using the + * CONFIG_STM32_ADCx_EXTSEL option. + */ + +#if defined(CONFIG_STM32_TIM1_ADC1) +# if CONFIG_STM32_ADC1_TIMTRIG == 3 +# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T1CC4 +# elif CONFIG_STM32_ADC1_TIMTRIG == 4 +# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T1TRGO +# elif CONFIG_STM32_ADC1_TIMTRIG == 5 +# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T1TRGO2 +# else +# error "CONFIG_STM32_ADC1_TIMTRIG is out of range" +# endif +#elif defined(CONFIG_STM32_TIM2_ADC1) +# if CONFIG_STM32_ADC1_TIMTRIG == 3 +# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T2CC4 +# elif CONFIG_STM32_ADC1_TIMTRIG == 4 +# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T2TRGO +# else +# error "CONFIG_STM32_ADC1_TIMTRIG is out of range" +# endif +#elif defined(CONFIG_STM32_TIM3_ADC1) +# if CONFIG_STM32_ADC1_TIMTRIG == 4 +# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T3TRGO +# else +# error "CONFIG_STM32_ADC1_TIMTRIG is out of range" +# endif +#elif defined(CONFIG_STM32_TIM15_ADC1) +# if CONFIG_STM32_ADC1_TIMTRIG == 4 +# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T15TRGO +# else +# error "CONFIG_STM32_ADC1_TIMTRIG is out of range" +# endif +#elif defined(CONFIG_STM32_TIM21_ADC1) +# if CONFIG_STM32_ADC1_TIMTRIG == 1 +# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T21CC2 +# elif CONFIG_STM32_ADC1_TIMTRIG == 4 +# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T21TRGO +# else +# error "CONFIG_STM32_ADC1_TIMTRIG is out of range" +# endif +#endif + +/* Regular channels external trigger support */ + +#ifdef ADC1_EXTSEL_VALUE +# define ADC1_HAVE_EXTCFG 1 +# define ADC1_EXTCFG_VALUE (ADC1_EXTSEL_VALUE | ADC_EXTREG_EXTEN_DEFAULT) +#elif defined(CONFIG_STM32_ADC1_EXTSEL) +# define ADC1_HAVE_EXTCFG 1 +# define ADC1_EXTCFG_VALUE 0 +#else +# undef ADC1_HAVE_EXTCFG +#endif + +#if defined(ADC1_HAVE_EXTCFG) +# define ADC_HAVE_EXTCFG +#endif + +/* ADC interrupts ***********************************************************/ + +#define ADC_ISR_EOC ADC_INT_EOC +#define ADC_IER_EOC ADC_INT_EOC +#define ADC_ISR_AWD ADC_INT_AWD +#define ADC_IER_AWD ADC_INT_AWD +#define ADC_ISR_OVR ADC_INT_OVR +#define ADC_IER_OVR ADC_INT_OVR + +#define ADC_ISR_ALLINTS (ADC_ISR_EOC | ADC_ISR_AWD | ADC_ISR_OVR) +#define ADC_IER_ALLINTS (ADC_IER_EOC | ADC_IER_AWD | ADC_IER_OVR) + +/* ADC registers ************************************************************/ + +#define STM32_ADC_DMAREG_OFFSET STM32_ADC_CFGR1_OFFSET +#define ADC_DMAREG_DMA ADC_CFGR1_DMAEN +#define STM32_ADC_EXTREG_OFFSET STM32_ADC_CFGR1_OFFSET +#define ADC_EXTREG_EXTSEL_MASK ADC_CFGR1_EXTSEL_MASK +#define ADC_EXTREG_EXTEN_MASK ADC_CFGR1_EXTEN_MASK +#define ADC_EXTREG_EXTEN_DEFAULT ADC_CFGR1_EXTEN_RISING + +/* Low-level ops helpers ****************************************************/ + +#define ADC_INT_ACK(adc, source) \ + (adc)->llops->int_ack(adc, source) +#define ADC_INT_GET(adc) \ + (adc)->llops->int_get(adc) +#define ADC_INT_ENABLE(adc, source) \ + (adc)->llops->int_en(adc, source) +#define ADC_INT_DISABLE(adc, source) \ + (adc)->llops->int_dis(adc, source) +#define ADC_REGDATA_GET(adc) \ + (adc)->llops->val_get(adc) +#define ADC_REGBUF_REGISTER(adc, buffer, len) \ + (adc)->llops->regbuf_reg(adc, buffer, len) +#define ADC_REG_STARTCONV(adc, state) \ + (adc)->llops->reg_startconv(adc, state) +#define ADC_SAMPLETIME_SET(adc, time_samples) \ + (adc)->llops->stime_set(adc, time_samples) +#define ADC_SAMPLETIME_WRITE(adc) \ + (adc)->llops->stime_write(adc) +#define ADC_DUMP_REGS(adc) \ + (adc)->llops->dump_regs(adc) + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/* On STM32F42xx and STM32F43xx devices,VBAT and temperature sensor are + * connected to the same ADC internal channel (ADC1_IN18). Only one + * conversion, either temperature sensor or VBAT, must be selected at a time. + * When both conversion are enabled simultaneously, only the VBAT conversion + * is performed. + */ + +enum adc_io_cmds_e +{ +#ifdef HAVE_ADC_VBAT + IO_ENABLE_DISABLE_VBAT_CH, +#endif + IO_ENABLE_DISABLE_AWDIE, + IO_ENABLE_DISABLE_EOCIE, + IO_ENABLE_DISABLE_JEOCIE, + IO_ENABLE_DISABLE_OVRIE, + IO_ENABLE_DISABLE_ALL_INTS, + IO_STOP_ADC, + IO_START_ADC, + IO_START_CONV, + IO_TRIGGER_REG, +#ifdef ADC_HAVE_INJECTED + IO_TRIGGER_INJ, +#endif +#ifdef HAVE_ADC_POWERDOWN + IO_ENABLE_DISABLE_PDI, + IO_ENABLE_DISABLE_PDD, + IO_ENABLE_DISABLE_PDD_PDI +#endif +}; + +/* ADC resolution can be reduced in order to perform faster conversion */ + +enum stm32_adc_resoluton_e +{ + ADC_RESOLUTION_12BIT = 0, /* 12 bit */ + ADC_RESOLUTION_10BIT = 1, /* 10 bit */ + ADC_RESOLUTION_8BIT = 2, /* 8 bit */ + ADC_RESOLUTION_6BIT = 3 /* 6 bit */ +}; + +#ifdef CONFIG_STM32_ADC_LL_OPS + +#ifdef CONFIG_STM32_ADC_CHANGE_SAMPLETIME + +struct adc_sample_time_s +{ + uint8_t smp1; /* Sample time for channels with SMPSEL bit = 0 */ + uint8_t smp2; /* Sample time for channels with SMPSEL bit = 1 */ + uint32_t smpsel; /* Bitmask for selecting which channels use SMP2 */ +}; +#endif /* CONFIG_STM32_ADC_CHANGE_SAMPLETIME */ + +/* This structure provides the publicly visible representation of the + * "lower-half" ADC driver structure. + */ + +struct stm32_adc_dev_s +{ + /* Publicly visible portion of the "lower-half" ADC driver structure */ + + const struct stm32_adc_ops_s *llops; + + /* Require cast-compatibility with private "lower-half" ADC structure */ +}; + +/* Low-level operations for ADC */ + +struct stm32_adc_ops_s +{ + /* Acknowledge interrupts */ + + void (*int_ack)(struct stm32_adc_dev_s *dev, uint32_t source); + + /* Get pending interrupts */ + + uint32_t (*int_get)(struct stm32_adc_dev_s *dev); + + /* Enable interrupts */ + + void (*int_en)(struct stm32_adc_dev_s *dev, uint32_t source); + + /* Disable interrupts */ + + void (*int_dis)(struct stm32_adc_dev_s *dev, uint32_t source); + + /* Get current ADC data register */ + + uint32_t (*val_get)(struct stm32_adc_dev_s *dev); + + /* Register buffer for ADC DMA transfer */ + + int (*regbuf_reg)(struct stm32_adc_dev_s *dev, uint16_t *buffer, + uint8_t len); + + /* Start/stop regular conversion */ + + void (*reg_startconv)(struct stm32_adc_dev_s *dev, bool state); + +#ifdef CONFIG_STM32_ADC_CHANGE_SAMPLETIME + /* Set ADC sample time */ + + void (*stime_set)(struct stm32_adc_dev_s *dev, + struct adc_sample_time_s *time_samples); + + /* Write ADC sample time */ + + void (*stime_write)(struct stm32_adc_dev_s *dev); +#endif + + void (*dump_regs)(struct stm32_adc_dev_s *dev); +}; + +#endif /* CONFIG_STM32_ADC_LL_OPS */ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#ifndef __ASSEMBLY__ +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Name: stm32_adcinitialize + * + * Description: + * Initialize the ADC. See stm32_adc.c for more details. + * + * Input Parameters: + * intf - Could be {1,2,3,4} for ADC1, ADC2, ADC3 or ADC4 + * chanlist - The list of channels (regular + injected) + * nchannels - Number of channels (regular + injected) + * + * Returned Value: + * Valid ADC device structure reference on success; a NULL on failure + * + ****************************************************************************/ + +struct adc_dev_s; +struct adc_dev_s *stm32_adcinitialize(int intf, const uint8_t *chanlist, + int channels); + +/**************************************************************************** + * Name: stm32_adc_llops_get + ****************************************************************************/ + +#ifdef CONFIG_STM32_ADC_LL_OPS +const struct stm32_adc_ops_s +*stm32_adc_llops_get(struct adc_dev_s *dev); +#endif + +#undef EXTERN +#ifdef __cplusplus +} +#endif +#endif /* __ASSEMBLY__ */ + +#endif /* CONFIG_STM32_ADC1 */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_ADC_V2_M0_H */ diff --git a/arch/arm/src/common/stm32/stm32_adc_m3m4_v1v2.c b/arch/arm/src/common/stm32/stm32_adc_m3m4_v1v2.c new file mode 100644 index 0000000000000..b53e2b6a07166 --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_adc_m3m4_v1v2.c @@ -0,0 +1,5001 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_adc_m3m4_v1v2.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#include "arm_internal.h" +#include "chip.h" +#include "stm32_rcc.h" +#include "stm32_tim.h" +#include "stm32_dma.h" +#include "stm32_adc.h" + +/* The STM32 ADC lower-half driver functionality overview: + * - one lower-half driver for all STM32 ADC IP cores, + * - general lower-half logic for the NuttX upper-half ADC driver, + * - lower-half ADC driver can be used not only with the upper-half ADC + * driver, but also in the lower-half logic for special-case custom + * drivers (eg. power-control, custom sensors), + * - ADC can be used in time-critical operations (eg. control loop for + * converters or motor drivers) therefore it is necessary to support the + * high performance, zero latency ADC interrupts, + * - ADC triggering from different sources (EXTSEL and JEXTSEL), + * - regular sequence conversion (supported in upper-half ADC driver) + * - injected sequence conversion (not supported in upper-half ADC driver) + */ + +/* STM32 ADC "lower-half" support must be enabled */ + +#ifdef CONFIG_STM32_ADC + +/* This implementation is for the STM32 ADC IP version 1 and 2 */ + +#if !defined(HAVE_IP_ADC_V1) && !defined(HAVE_IP_ADC_V2) +# error "STM32 ADC IP version not specified" +#endif + +/* Supported ADC modes: + * - SW triggering with/without DMA transfer + * - TIM triggering with/without DMA transfer + * - external triggering with/without DMA transfer + * + * (tested with ADC example app from NuttX apps repo). + */ + +/* At the moment there is no proper implementation for timers external + * trigger in STM32L15XX may be added later + */ + +#if defined(ADC_HAVE_TIMER) && defined(CONFIG_STM32_STM32L15XX) +# warning "There is no proper implementation for TIMER TRIGGERS at the moment" +#endif + +/* If ADC use HSI as clock-source and HSI is not used for PLL and system + * clock, then we can control it directly from ADC driver. + */ + +#if defined(HAVE_ADC_CLOCK_HSI) && \ + (STM32_CFGR_PLLSRC != 0 || STM32_SYSCLK_SW != RCC_CFGR_SW_HSI) +# define HAVE_HSI_CONTROL +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* RCC reset ****************************************************************/ + +#if defined(HAVE_IP_ADC_V1) +# ifdef HAVE_BASIC_ADC +# define STM32_RCC_RSTR STM32_RCC_APB2RSTR +# define RCC_RSTR_ADC1RST RCC_APB2RSTR_ADC1RST +# define RCC_RSTR_ADC2RST RCC_APB2RSTR_ADC2RST +# define RCC_RSTR_ADC3RST RCC_APB2RSTR_ADC3RST +# else +# define STM32_RCC_RSTR STM32_RCC_APB2RSTR +# define RCC_RSTR_ADC123RST RCC_APB2RSTR_ADCRST +# endif +#elif defined(HAVE_IP_ADC_V2) +# ifdef STM32_RCC_AHB2RSTR_OFFSET +# define STM32_RCC_RSTR STM32_RCC_AHB2RSTR +# define RCC_RSTR_ADC12RST RCC_AHB2RSTR_ADC12RST +# define RCC_RSTR_ADC34RST RCC_AHB2RSTR_ADC345RST +# else +# define STM32_RCC_RSTR STM32_RCC_AHBRSTR +# define RCC_RSTR_ADC12RST RCC_AHBRSTR_ADC12RST +# define RCC_RSTR_ADC34RST RCC_AHBRSTR_ADC34RST +# endif +#endif + +/* ADC Channels/DMA *********************************************************/ + +/* DMA values differs according to STM32 DMA IP core version */ + +#if defined(HAVE_IP_DMA_V2) +# define ADC_DMA_CONTROL_WORD (DMA_SCR_MSIZE_16BITS | \ + DMA_SCR_PSIZE_16BITS | \ + DMA_SCR_MINC | \ + DMA_SCR_CIRC | \ + DMA_SCR_DIR_P2M) +#elif defined(HAVE_IP_DMA_V1) +# define ADC_DMA_CONTROL_WORD (DMA_CCR_MSIZE_16BITS | \ + DMA_CCR_PSIZE_16BITS | \ + DMA_CCR_MINC | \ + DMA_CCR_CIRC) +#endif + +/* Sample time default configuration + * + * REVISIT: simplify this, use adc_sampletime_write() function. + * REVISIT: default SMPR configurable from Kconfig + */ + +#if defined(CONFIG_STM32_STM32F10XX) +# define ADC_SMPR_DEFAULT ADC_SMPR_55p5 +# define ADC_SMPR1_DEFAULT ((ADC_SMPR_DEFAULT << ADC_SMPR1_SMP10_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR1_SMP11_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR1_SMP12_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR1_SMP13_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR1_SMP14_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR1_SMP15_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR1_SMP16_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR1_SMP17_SHIFT)) +# define ADC_SMPR2_DEFAULT ((ADC_SMPR_DEFAULT << ADC_SMPR2_SMP0_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP1_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP2_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP3_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP4_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP5_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP6_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP7_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP8_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP9_SHIFT)) +#elif defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) +# if defined(ADC_HAVE_DMA) || (CONFIG_STM32_ADC_MAX_SAMPLES == 1) +# define ADC_SMPR_DEFAULT ADC_SMPR_61p5 +# else /* Slow down sampling frequency */ +# define ADC_SMPR_DEFAULT ADC_SMPR_601p5 +# endif +# define ADC_SMPR1_DEFAULT ((ADC_SMPR_DEFAULT << ADC_SMPR1_SMP1_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR1_SMP2_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR1_SMP3_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR1_SMP4_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR1_SMP5_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR1_SMP6_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR1_SMP7_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR1_SMP8_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR1_SMP9_SHIFT)) +# define ADC_SMPR2_DEFAULT ((ADC_SMPR_DEFAULT << ADC_SMPR2_SMP10_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP11_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP12_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP13_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP14_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP15_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP16_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP17_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP18_SHIFT)) +#elif defined(CONFIG_STM32_STM32G4XXX) +# if defined(ADC_HAVE_DMA) || (CONFIG_STM32_ADC_MAX_SAMPLES == 1) +# define ADC_SMPR_DEFAULT ADC_SMPR_47p5 +# else /* Slow down sampling frequency */ +# define ADC_SMPR_DEFAULT ADC_SMPR_640p5 +# endif +# define ADC_SMPR1_DEFAULT ((ADC_SMPR_DEFAULT << ADC_SMPR1_SMP0_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR1_SMP1_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR1_SMP2_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR1_SMP3_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR1_SMP4_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR1_SMP5_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR1_SMP6_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR1_SMP7_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR1_SMP8_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR1_SMP9_SHIFT)) +# define ADC_SMPR2_DEFAULT ((ADC_SMPR_DEFAULT << ADC_SMPR2_SMP10_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP11_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP12_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP13_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP14_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP15_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP16_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP17_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP18_SHIFT)) +#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F37XX) || \ + defined(CONFIG_STM32_STM32F4XXX) +# if defined(CONFIG_STM32_STM32F37XX) +# define ADC_SMPR_DEFAULT ADC_SMPR_239p5 /* TODO choose 1p5? */ +# else +# define ADC_SMPR_DEFAULT ADC_SMPR_112 +# endif +# define ADC_SMPR1_DEFAULT ((ADC_SMPR_DEFAULT << ADC_SMPR1_SMP10_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR1_SMP11_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR1_SMP12_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR1_SMP13_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR1_SMP14_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR1_SMP15_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR1_SMP16_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR1_SMP17_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR1_SMP18_SHIFT)) +# define ADC_SMPR2_DEFAULT ((ADC_SMPR_DEFAULT << ADC_SMPR2_SMP0_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP1_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP2_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP3_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP4_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP5_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP6_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP7_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP8_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP9_SHIFT)) +#elif defined(CONFIG_STM32_STM32L15XX) +# define ADC_SMPR_DEFAULT ADC_SMPR_384 +# define ADC_SMPR1_DEFAULT ((ADC_SMPR_DEFAULT << ADC_SMPR1_SMP20_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR1_SMP21_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR1_SMP22_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR1_SMP23_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR1_SMP24_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR1_SMP25_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR1_SMP26_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR1_SMP27_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR1_SMP28_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR1_SMP29_SHIFT)) +# define ADC_SMPR2_DEFAULT ((ADC_SMPR_DEFAULT << ADC_SMPR2_SMP10_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP11_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP12_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP13_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP14_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP15_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP16_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP17_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP18_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP19_SHIFT)) +# define ADC_SMPR3_DEFAULT ((ADC_SMPR_DEFAULT << ADC_SMPR3_SMP0_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR3_SMP1_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR3_SMP2_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR3_SMP3_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR3_SMP4_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR3_SMP5_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR3_SMP6_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR3_SMP7_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR3_SMP8_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR3_SMP9_SHIFT)) +# define ADC_SMPR0_DEFAULT ((ADC_SMPR_DEFAULT << ADC_SMPR0_SMP30_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR0_SMP31_SHIFT)) +#endif + +/* Number of channels per ADC: + * - F0, L0 - 19, but single SMP for all channels + * - F1 - 18 + * - F2,F3,F4,F7,L4,L4+ - 19 + * - H7 - 20 + * - L1 - 32 + * + * NOTE: this value can be obtained from SMPRx register description + * (ST manual) + */ + +#if defined(CONFIG_STM32_STM32F10XX) +# define ADC_CHANNELS_NUMBER 18 +#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F30XX) || \ + defined(CONFIG_STM32_STM32F33XX) || defined(CONFIG_STM32_STM32F4XXX) || \ + defined(CONFIG_STM32_STM32G4XXX) +# define ADC_CHANNELS_NUMBER 19 +#elif defined(CONFIG_STM32_STM32L15XX) +# define ADC_CHANNELS_NUMBER 32 +#else +# error "Not supported" +#endif + +/* ADC resolution. Not supported for basic STM32 ADC IPv1 */ + +#ifndef CONFIG_STM32_HAVE_IP_ADC_M3M4_V1_BASIC +# define HAVE_ADC_RESOLUTION +#else +# undef HAVE_ADC_RESOLUTION +#endif + +/* ADC have common registers for all cores except basic ADC IPv1 (F1, F37x) */ + +#ifdef CONFIG_STM32_HAVE_IP_ADC_M3M4_V1_BASIC +# undef HAVE_ADC_CMN_REGS +#else +# define HAVE_ADC_CMN_REGS +#endif +#if defined(HAVE_ADC_CMN_REGS) && STM32_NADC > 1 +# define HAVE_ADC_CMN_DATA +#else +# undef HAVE_ADC_CMN_DATA +#endif + +/* Max 4 injected channels */ + +#define ADC_INJ_MAX_SAMPLES 4 + +/* ADC DMA configuration bit support */ + +#ifndef CONFIG_STM32_HAVE_IP_ADC_M3M4_V1_BASIC +# define ADC_HAVE_DMACFG 1 +#else +# undef ADC_HAVE_DMACFG +#endif + +/* ADC scan mode support - only for ADCv1 */ + +#ifdef CONFIG_STM32_HAVE_IP_ADC_M3M4_V1 +# define ADC_HAVE_SCAN 1 +# ifndef CONFIG_STM32_ADC1_SCAN +# define CONFIG_STM32_ADC1_SCAN 0 +# endif +# ifndef CONFIG_STM32_ADC2_SCAN +# define CONFIG_STM32_ADC2_SCAN 0 +# endif +# ifndef CONFIG_STM32_ADC3_SCAN +# define CONFIG_STM32_ADC3_SCAN 0 +# endif +#else +# undef ADC_HAVE_SCAN +#endif + +/* We have to support ADC callbacks if default ADC interrupts or + * DMA transfer are enabled + */ + +#if !defined(CONFIG_STM32_ADC_NOIRQ) || defined(ADC_HAVE_DMA) +# define ADC_HAVE_CB +#else +# undef ADC_HAVE_CB +#endif + +/* ADC software trigger configuration */ + +#define ANIOC_TRIGGER_REGULAR (1 << 0) +#define ANIOC_TRIGGER_INJECTED (1 << 1) + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/* Data common to all ADC instances */ + +#ifdef HAVE_ADC_CMN_DATA +struct adccmn_data_s +{ + uint8_t refcount; /* How many ADC instances are currently in use */ + mutex_t lock; /* Exclusive access to common ADC data */ +}; +#endif + +/* This structure describes the state of one ADC block + * REVISIT: save some space with bit fields. + */ + +struct stm32_dev_s +{ +#ifdef CONFIG_STM32_ADC_LL_OPS + const struct stm32_adc_ops_s *llops; /* Low-level ADC ops */ + struct adc_dev_s *dev; /* Upper-half ADC reference */ +#endif +#ifdef ADC_HAVE_CB + const struct adc_callback_s *cb; + uint8_t irq; /* Interrupt generated by this ADC block */ +#endif +#ifdef HAVE_ADC_CMN_DATA + struct adccmn_data_s *cmn; /* Common ADC data */ +#endif + uint8_t rnchannels; /* Number of regular channels */ + uint8_t cr_channels; /* Number of configured regular channels */ +#ifdef ADC_HAVE_INJECTED + uint8_t cj_channels; /* Number of configured injected channels */ +#endif + uint8_t intf; /* ADC interface number */ + uint8_t initialized; /* ADC interface initialization counter */ + uint8_t current; /* Current ADC channel being converted */ + uint8_t anioc_trg; /* ANIOC_TRIGGER configuration */ +#ifdef HAVE_ADC_RESOLUTION + uint8_t resolution; /* ADC resolution (0-3) */ +#endif +#ifdef ADC_HAVE_DMA + uint8_t dmachan; /* DMA channel needed by this ADC */ +# ifdef ADC_HAVE_DMACFG + uint8_t dmacfg; /* DMA channel configuration, only for ADC IPv2 */ +# endif + bool hasdma; /* True: This channel supports DMA */ + uint16_t dmabatch; /* Number of conversions for DMA batch */ +#endif +#ifdef ADC_HAVE_SCAN + bool scan; /* True: Scan mode */ +#endif +#ifdef CONFIG_STM32_ADC_CHANGE_SAMPLETIME + /* Sample time selection. These bits must be written only when ADON=0. + * REVISIT: this takes too much space. We need only 3 bits per channel. + */ + + uint8_t sample_rate[ADC_CHANNELS_NUMBER]; + uint8_t adc_channels; /* ADC channels number */ +#endif +#ifdef ADC_HAVE_TIMER + uint8_t trigger; /* Timer trigger channel: 0=CC1, 1=CC2, 2=CC3, + * 3=CC4, 4=TRGO, 5=TRGO2 + */ +#endif + xcpt_t isr; /* Interrupt handler for this ADC block */ + uint32_t base; /* Base address of registers unique to this ADC + * block */ +#ifdef ADC_HAVE_EXTCFG + uint32_t extcfg; /* External event configuration for regular group */ +#endif +#ifdef ADC_HAVE_JEXTCFG + uint32_t jextcfg; /* External event configuration for injected group */ +#endif +#ifdef ADC_HAVE_TIMER + uint32_t tbase; /* Base address of timer used by this ADC block */ + uint32_t pclck; /* The PCLK frequency that drives this timer */ + uint32_t freq; /* The desired frequency of conversions */ +#endif +#ifdef ADC_HAVE_DMA + DMA_HANDLE dma; /* Allocated DMA channel */ + + /* DMA transfer buffer */ + + uint16_t *r_dmabuffer; +#endif + + /* List of selected ADC channels to sample */ + + uint8_t r_chanlist[CONFIG_STM32_ADC_MAX_SAMPLES]; + +#ifdef ADC_HAVE_INJECTED + /* List of selected ADC injected channels to sample */ + + uint8_t j_chanlist[ADC_INJ_MAX_SAMPLES]; +#endif +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/* ADC Register access */ + +#ifndef HAVE_BASIC_ADC +static void stm32_modifyreg32(unsigned int addr, uint32_t clrbits, + uint32_t setbits); +#endif +static uint32_t adc_getreg(struct stm32_dev_s *priv, int offset); +static void adc_putreg(struct stm32_dev_s *priv, int offset, + uint32_t value); +static void adc_modifyreg(struct stm32_dev_s *priv, int offset, + uint32_t clrbits, uint32_t setbits); +#ifdef HAVE_ADC_CMN_REGS +static uint32_t adccmn_base_get(struct stm32_dev_s *priv); +static void adccmn_modifyreg(struct stm32_dev_s *priv, uint32_t offset, + uint32_t clrbits, uint32_t setbits); +static uint32_t adccmn_getreg(struct stm32_dev_s *priv, uint32_t offset); +#endif +#ifdef ADC_HAVE_TIMER +static uint16_t tim_getreg(struct stm32_dev_s *priv, int offset); +static void tim_putreg(struct stm32_dev_s *priv, int offset, + uint16_t value); +static void tim_modifyreg(struct stm32_dev_s *priv, int offset, + uint16_t clrbits, uint16_t setbits); +#ifdef HAVE_IP_TIMERS_V2 +static void tim_modifyreg32(struct stm32_dev_s *priv, int offset, + uint32_t clrbits, uint32_t setbits); +#endif +static void tim_dumpregs(struct stm32_dev_s *priv, const char *msg); +#endif + +static void adc_rccreset(struct stm32_dev_s *priv, bool reset); + +/* ADC Interrupt Handler */ + +#ifndef CONFIG_STM32_ADC_NOIRQ +static int adc_interrupt(struct adc_dev_s *dev); +# if defined(STM32_IRQ_ADC1) && defined(CONFIG_STM32_ADC1) +static int adc1_interrupt(int irq, void *context, void *arg); +# endif +# if defined(STM32_IRQ_ADC12) && (defined(CONFIG_STM32_ADC1) || \ + defined(CONFIG_STM32_ADC2)) +static int adc12_interrupt(int irq, void *context, void *arg); +# endif +# if (defined(STM32_IRQ_ADC3) && defined(CONFIG_STM32_ADC3)) +static int adc3_interrupt(int irq, void *context, void *arg); +# endif +# if defined(STM32_IRQ_ADC4) && defined(CONFIG_STM32_ADC4) +static int adc4_interrupt(int irq, void *context, void *arg); +# endif +# if defined(STM32_IRQ_ADC) +static int adc123_interrupt(int irq, void *context, void *arg); +# endif +#endif /* CONFIG_STM32_ADC_NOIRQ */ + +/* ADC Driver Methods */ + +static int adc_bind(struct adc_dev_s *dev, + const struct adc_callback_s *callback); +static void adc_reset(struct adc_dev_s *dev); +static int adc_setup(struct adc_dev_s *dev); +static void adc_shutdown(struct adc_dev_s *dev); +static void adc_rxint(struct adc_dev_s *dev, bool enable); +static int adc_ioctl(struct adc_dev_s *dev, int cmd, unsigned long arg); +static void adc_enable(struct stm32_dev_s *priv, bool enable); + +static uint32_t adc_sqrbits(struct stm32_dev_s *priv, int first, + int last, int offset); +static int adc_set_ch(struct adc_dev_s *dev, uint8_t ch); + +static int adc_ioc_change_ints(struct adc_dev_s *dev, int cmd, + bool arg); + +#ifdef HAVE_ADC_RESOLUTION +static int adc_resolution_set(struct adc_dev_s *dev, uint8_t res); +#endif +#ifdef HAVE_ADC_VBAT +static void adc_enable_vbat_channel(struct adc_dev_s *dev, bool enable); +#endif +#ifdef HAVE_ADC_POWERDOWN +static int adc_ioc_change_sleep_between_opers(struct adc_dev_s *dev, + int cmd, bool arg); +static void adc_power_down_idle(struct stm32_dev_s *priv, + bool pdi_high); +static void adc_power_down_delay(struct stm32_dev_s *priv, + bool pdd_high); +#endif + +#ifdef CONFIG_STM32_STM32L15XX +static void adc_dels_after_conversion(struct stm32_dev_s *priv, + uint32_t delay); +static void adc_select_ch_bank(struct stm32_dev_s *priv, + bool chb_selected); +#endif + +#ifdef HAVE_HSI_CONTROL +static void adc_enable_hsi(bool enable); +static void adc_reset_hsi_disable(struct adc_dev_s *dev); +#endif + +#ifdef ADC_HAVE_TIMER +static void adc_timstart(struct stm32_dev_s *priv, bool enable); +static int adc_timinit(struct stm32_dev_s *priv); +#endif + +#if defined(ADC_HAVE_DMA) && !defined(CONFIG_STM32_ADC_NOIRQ) +static void adc_dmaconvcallback(DMA_HANDLE handle, uint8_t isr, + void *arg); +#endif + +static void adc_reg_startconv(struct stm32_dev_s *priv, bool enable); +#ifdef ADC_HAVE_INJECTED +static void adc_inj_startconv(struct stm32_dev_s *priv, bool enable); +static int adc_inj_set_ch(struct adc_dev_s *dev, uint8_t ch); +#endif + +#ifdef ADC_HAVE_EXTCFG +static int adc_extcfg_set(struct stm32_dev_s *priv, uint32_t extcfg); +#endif +#ifdef ADC_HAVE_JEXTCFG +static int adc_jextcfg_set(struct stm32_dev_s *priv, uint32_t jextcfg); +#endif + +static void adc_dumpregs(struct stm32_dev_s *priv); + +#ifdef CONFIG_STM32_ADC_LL_OPS +static int adc_llops_setup(struct stm32_adc_dev_s *dev); +static void adc_llops_shutdown(struct stm32_adc_dev_s *dev); +static void adc_intack(struct stm32_adc_dev_s *dev, uint32_t source); +static void adc_inten(struct stm32_adc_dev_s *dev, uint32_t source); +static void adc_intdis(struct stm32_adc_dev_s *dev, uint32_t source); +static uint32_t adc_intget(struct stm32_adc_dev_s *dev); +static uint32_t adc_regget(struct stm32_adc_dev_s *dev); +static void adc_llops_reg_startconv(struct stm32_adc_dev_s *dev, + bool enable); +static int adc_offset_set(struct stm32_adc_dev_s *dev, uint8_t ch, + uint8_t i, uint16_t offset); +# ifdef ADC_HAVE_EXTCFG +static void adc_llops_extcfg_set(struct stm32_adc_dev_s *dev, + uint32_t extcfg); +# endif +# ifdef ADC_HAVE_JEXTCFG +static void adc_llops_jextcfg_set(struct stm32_adc_dev_s *dev, + uint32_t jextcfg); +# endif +# ifdef ADC_HAVE_DMA +static int adc_regbufregister(struct stm32_adc_dev_s *dev, + uint16_t *buffer, uint8_t len); +# endif +# ifdef ADC_HAVE_INJECTED +static uint32_t adc_injget(struct stm32_adc_dev_s *dev, uint8_t chan); +static void adc_llops_inj_startconv(struct stm32_adc_dev_s *dev, + bool enable); +# endif +# ifdef CONFIG_STM32_ADC_CHANGE_SAMPLETIME +static void adc_sampletime_set(struct stm32_adc_dev_s *dev, + struct adc_sample_time_s *time_samples); +static void adc_sampletime_write(struct stm32_adc_dev_s *dev); +# endif +static void adc_llops_dumpregs(struct stm32_adc_dev_s *dev); +static int adc_llops_multicfg(struct stm32_adc_dev_s *dev, uint8_t mode); +static void adc_llops_enable(struct stm32_adc_dev_s *dev, bool enable); +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* ADC interface operations */ + +static const struct adc_ops_s g_adcops = +{ + .ao_bind = adc_bind, +#ifdef HAVE_HSI_CONTROL + .ao_reset = adc_reset_hsi_disable, +#else + .ao_reset = adc_reset, +#endif + .ao_setup = adc_setup, + .ao_shutdown = adc_shutdown, + .ao_rxint = adc_rxint, + .ao_ioctl = adc_ioctl, +}; + +/* Publicly visible ADC lower-half operations */ + +#ifdef CONFIG_STM32_ADC_LL_OPS +static const struct stm32_adc_ops_s g_adc_llops = +{ + .setup = adc_llops_setup, + .shutdown = adc_llops_shutdown, + .int_ack = adc_intack, + .int_get = adc_intget, + .int_en = adc_inten, + .int_dis = adc_intdis, + .val_get = adc_regget, + .reg_startconv = adc_llops_reg_startconv, + .offset_set = adc_offset_set, +# ifdef ADC_HAVE_DMA + .regbuf_reg = adc_regbufregister, +# endif +# ifdef ADC_HAVE_EXTCFG + .extcfg_set = adc_llops_extcfg_set, +# endif +# ifdef ADC_HAVE_JEXTCFG + .jextcfg_set = adc_llops_jextcfg_set, +# endif +# ifdef ADC_HAVE_INJECTED + .inj_get = adc_injget, + .inj_startconv = adc_llops_inj_startconv, +# endif +# ifdef CONFIG_STM32_ADC_CHANGE_SAMPLETIME + .stime_set = adc_sampletime_set, + .stime_write = adc_sampletime_write, +# endif + .dump_regs = adc_llops_dumpregs, + .multi_cfg = adc_llops_multicfg, + .enable = adc_llops_enable +}; +#endif + +/* ADC instances are coupled in blocks for all IP versions except + * basic ADC IPv1 (F1, F37x). + */ + +#ifdef HAVE_ADC_CMN_DATA +# ifdef HAVE_IP_ADC_V1 +# define ADC1CMN_DATA g_adc123_cmn +# define ADC2CMN_DATA g_adc123_cmn +# define ADC3CMN_DATA g_adc123_cmn + +/* ADC123 common data */ + +struct adccmn_data_s g_adc123_cmn = +{ + .refcount = 0, + .lock = NXMUTEX_INITIALIZER, +}; + +# elif defined(HAVE_IP_ADC_V2) +# define ADC1CMN_DATA g_adc12_cmn +# define ADC2CMN_DATA g_adc12_cmn +# define ADC3CMN_DATA g_adc34_cmn +# define ADC4CMN_DATA g_adc34_cmn +# if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) + +/* ADC12 common data */ + +struct adccmn_data_s g_adc12_cmn = +{ + .refcount = 0, + .lock = NXMUTEX_INITIALIZER, +}; + +# endif +# if defined(CONFIG_STM32_ADC3) || defined(CONFIG_STM32_ADC4) + +/* ADC34 common data */ + +struct adccmn_data_s g_adc34_cmn = +{ + .refcount = 0, + .lock = NXMUTEX_INITIALIZER, +}; + +# endif +# endif /* !HAVE_IP_ADC_V1 */ +#endif /* HAVE_ADC_CMN_DATA */ + +/* ADC1 state */ + +#ifdef CONFIG_STM32_ADC1 + +#ifdef ADC1_HAVE_DMA +static uint16_t g_adc1_dmabuffer[CONFIG_STM32_ADC_MAX_SAMPLES * + CONFIG_STM32_ADC1_DMA_BATCH]; +#endif + +static struct stm32_dev_s g_adcpriv1 = +{ +#ifdef CONFIG_STM32_ADC_LL_OPS + .llops = &g_adc_llops, +#endif +#ifndef CONFIG_STM32_ADC_NOIRQ +# if defined(STM32_IRQ_ADC1) + .irq = STM32_IRQ_ADC1, + .isr = adc1_interrupt, +# elif defined(STM32_IRQ_ADC12) + .irq = STM32_IRQ_ADC12, + .isr = adc12_interrupt, +# elif defined(STM32_IRQ_ADC) + .irq = STM32_IRQ_ADC, + .isr = adc123_interrupt, +# else +# error "No STM32_IRQ_ADC1 STM32_IRQ_ADC12 or STM32_IRQ_ADC defined for CONFIG_STM32_ADC1" +# endif +#endif /* CONFIG_STM32_ADC_NOIRQ */ +#ifdef HAVE_ADC_CMN_DATA + .cmn = &ADC1CMN_DATA, +#endif + .intf = 1, + .initialized = 0, + .anioc_trg = CONFIG_STM32_ADC1_ANIOC_TRIGGER, +#ifdef HAVE_ADC_RESOLUTION + .resolution = CONFIG_STM32_ADC1_RESOLUTION, +#endif + .base = STM32_ADC1_BASE, +#ifdef ADC1_HAVE_EXTCFG + .extcfg = ADC1_EXTCFG_VALUE, +#endif +#ifdef ADC1_HAVE_JEXTCFG + .jextcfg = ADC1_JEXTCFG_VALUE, +#endif +#ifdef ADC1_HAVE_TIMER + .trigger = CONFIG_STM32_ADC1_TIMTRIG, + .tbase = ADC1_TIMER_BASE, + .pclck = ADC1_TIMER_PCLK_FREQUENCY, + .freq = CONFIG_STM32_ADC1_SAMPLE_FREQUENCY, +#endif +#ifdef ADC1_HAVE_DMA + .dmachan = ADC1_DMA_CHAN, +# ifdef ADC_HAVE_DMACFG + .dmacfg = CONFIG_STM32_ADC1_DMA_CFG, +# endif + .hasdma = true, + .r_dmabuffer = g_adc1_dmabuffer, + .dmabatch = CONFIG_STM32_ADC1_DMA_BATCH, +#endif +#ifdef ADC_HAVE_SCAN + .scan = CONFIG_STM32_ADC1_SCAN, +#endif +}; + +static struct adc_dev_s g_adcdev1 = +{ + .ad_ops = &g_adcops, + .ad_priv = &g_adcpriv1, +}; +#endif + +/* ADC2 state */ + +#ifdef CONFIG_STM32_ADC2 + +#ifdef ADC2_HAVE_DMA +static uint16_t g_adc2_dmabuffer[CONFIG_STM32_ADC_MAX_SAMPLES * + CONFIG_STM32_ADC2_DMA_BATCH]; +#endif + +static struct stm32_dev_s g_adcpriv2 = +{ +#ifdef CONFIG_STM32_ADC_LL_OPS + .llops = &g_adc_llops, +#endif +#ifndef CONFIG_STM32_ADC_NOIRQ +# if defined(STM32_IRQ_ADC12) + .irq = STM32_IRQ_ADC12, + .isr = adc12_interrupt, +# elif defined(STM32_IRQ_ADC) + .irq = STM32_IRQ_ADC, + .isr = adc123_interrupt, +# else +# error "No STM32_IRQ_ADC12 or STM32_IRQ_ADC defined for CONFIG_STM32_ADC2" +# endif +#endif /* CONFIG_STM32_ADC_NOIRQ */ +#ifdef HAVE_ADC_CMN_DATA + .cmn = &ADC2CMN_DATA, +#endif + .intf = 2, + .initialized = 0, + .anioc_trg = CONFIG_STM32_ADC2_ANIOC_TRIGGER, +#ifdef HAVE_ADC_RESOLUTION + .resolution = CONFIG_STM32_ADC2_RESOLUTION, +#endif + .base = STM32_ADC2_BASE, +#ifdef ADC2_HAVE_EXTCFG + .extcfg = ADC2_EXTCFG_VALUE, +#endif +#ifdef ADC2_HAVE_JEXTCFG + .jextcfg = ADC2_JEXTCFG_VALUE, +#endif +#ifdef ADC2_HAVE_TIMER + .trigger = CONFIG_STM32_ADC2_TIMTRIG, + .tbase = ADC2_TIMER_BASE, + .pclck = ADC2_TIMER_PCLK_FREQUENCY, + .freq = CONFIG_STM32_ADC2_SAMPLE_FREQUENCY, +#endif +#ifdef ADC2_HAVE_DMA + .dmachan = ADC2_DMA_CHAN, +# ifdef ADC_HAVE_DMACFG + .dmacfg = CONFIG_STM32_ADC2_DMA_CFG, +# endif + .hasdma = true, + .r_dmabuffer = g_adc2_dmabuffer, + .dmabatch = CONFIG_STM32_ADC2_DMA_BATCH, +#endif +#ifdef ADC_HAVE_SCAN + .scan = CONFIG_STM32_ADC2_SCAN, +#endif +}; + +static struct adc_dev_s g_adcdev2 = +{ + .ad_ops = &g_adcops, + .ad_priv = &g_adcpriv2, +}; +#endif + +/* ADC3 state */ + +#ifdef CONFIG_STM32_ADC3 + +#ifdef ADC3_HAVE_DMA +static uint16_t g_adc3_dmabuffer[CONFIG_STM32_ADC_MAX_SAMPLES * + CONFIG_STM32_ADC3_DMA_BATCH]; +#endif + +static struct stm32_dev_s g_adcpriv3 = +{ +#ifdef CONFIG_STM32_ADC_LL_OPS + .llops = &g_adc_llops, +#endif +#ifndef CONFIG_STM32_ADC_NOIRQ +# if defined(STM32_IRQ_ADC3) + .irq = STM32_IRQ_ADC3, + .isr = adc3_interrupt, +# elif defined(STM32_IRQ_ADC) + .irq = STM32_IRQ_ADC, + .isr = adc123_interrupt, +# else +# error "No STM32_IRQ_ADC3 or STM32_IRQ_ADC defined for CONFIG_STM32_ADC3" +# endif +#endif /* CONFIG_STM32_ADC_NOIRQ */ +#ifdef HAVE_ADC_CMN_DATA + .cmn = &ADC3CMN_DATA, +#endif + .intf = 3, + .initialized = 0, + .anioc_trg = CONFIG_STM32_ADC3_ANIOC_TRIGGER, +#ifdef HAVE_ADC_RESOLUTION + .resolution = CONFIG_STM32_ADC3_RESOLUTION, +#endif + .base = STM32_ADC3_BASE, +#ifdef ADC3_HAVE_EXTCFG + .extcfg = ADC3_EXTCFG_VALUE, +#endif +#ifdef ADC3_HAVE_JEXTCFG + .jextcfg = ADC3_JEXTCFG_VALUE, +#endif +#ifdef ADC3_HAVE_TIMER + .trigger = CONFIG_STM32_ADC3_TIMTRIG, + .tbase = ADC3_TIMER_BASE, + .pclck = ADC3_TIMER_PCLK_FREQUENCY, + .freq = CONFIG_STM32_ADC3_SAMPLE_FREQUENCY, +#endif +#ifdef ADC3_HAVE_DMA + .dmachan = ADC3_DMA_CHAN, +# ifdef ADC_HAVE_DMACFG + .dmacfg = CONFIG_STM32_ADC3_DMA_CFG, +# endif + .hasdma = true, + .r_dmabuffer = g_adc3_dmabuffer, + .dmabatch = CONFIG_STM32_ADC3_DMA_BATCH, +#endif +#ifdef ADC_HAVE_SCAN + .scan = CONFIG_STM32_ADC3_SCAN, +#endif +}; + +static struct adc_dev_s g_adcdev3 = +{ + .ad_ops = &g_adcops, + .ad_priv = &g_adcpriv3, +}; +#endif + +/* ADC4 state */ + +#ifdef CONFIG_STM32_ADC4 + +#ifdef ADC4_HAVE_DMA +static uint16_t g_adc4_dmabuffer[CONFIG_STM32_ADC_MAX_SAMPLES * + CONFIG_STM32_ADC4_DMA_BATCH]; +#endif + +static struct stm32_dev_s g_adcpriv4 = +{ +#ifdef CONFIG_STM32_ADC_LL_OPS + .llops = &g_adc_llops, +#endif +#ifndef CONFIG_STM32_ADC_NOIRQ + .irq = STM32_IRQ_ADC4, + .isr = adc4_interrupt, +#endif +#ifdef HAVE_ADC_CMN_DATA + .cmn = &ADC4CMN_DATA, +#endif + .intf = 4, + .initialized = 0, + .anioc_trg = CONFIG_STM32_ADC4_ANIOC_TRIGGER, +#ifdef HAVE_ADC_RESOLUTION + .resolution = CONFIG_STM32_ADC4_RESOLUTION, +#endif + .base = STM32_ADC4_BASE, +#ifdef ADC4_HAVE_EXTCFG + .extcfg = ADC4_EXTCFG_VALUE, +#endif +#ifdef ADC4_HAVE_JEXTCFG + .jextcfg = ADC4_JEXTCFG_VALUE, +#endif +#ifdef ADC4_HAVE_TIMER + .trigger = CONFIG_STM32_ADC4_TIMTRIG, + .tbase = ADC4_TIMER_BASE, + .pclck = ADC4_TIMER_PCLK_FREQUENCY, + .freq = CONFIG_STM32_ADC4_SAMPLE_FREQUENCY, +#endif +#ifdef ADC4_HAVE_DMA + .dmachan = ADC4_DMA_CHAN, +# ifdef ADC_HAVE_DMACFG + .dmacfg = CONFIG_STM32_ADC4_DMA_CFG, +# endif + .hasdma = true, + .r_dmabuffer = g_adc4_dmabuffer, + .dmabatch = CONFIG_STM32_ADC4_DMA_BATCH +#endif +}; + +static struct adc_dev_s g_adcdev4 = +{ + .ad_ops = &g_adcops, + .ad_priv = &g_adcpriv4, +}; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_modifyreg32 + * + * Description: + * Modify the value of a 32-bit register (not atomic). + * + * Input Parameters: + * addr - The address of the register + * clrbits - The bits to clear + * setbits - The bits to set + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifndef HAVE_BASIC_ADC +static void stm32_modifyreg32(unsigned int addr, uint32_t clrbits, + uint32_t setbits) +{ + putreg32((getreg32(addr) & ~clrbits) | setbits, addr); +} +#endif + +/**************************************************************************** + * Name: adc_getreg + * + * Description: + * Read the value of an ADC register. + * + * Input Parameters: + * priv - A reference to the ADC block status + * offset - The offset to the register to read + * + * Returned Value: + * The current contents of the specified register + * + ****************************************************************************/ + +static uint32_t adc_getreg(struct stm32_dev_s *priv, int offset) +{ + return getreg32(priv->base + offset); +} + +/**************************************************************************** + * Name: adc_putreg + * + * Description: + * Write a value to an ADC register. + * + * Input Parameters: + * priv - A reference to the ADC block status + * offset - The offset to the register to write to + * value - The value to write to the register + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void adc_putreg(struct stm32_dev_s *priv, int offset, + uint32_t value) +{ + putreg32(value, priv->base + offset); +} + +/**************************************************************************** + * Name: adc_modifyreg + * + * Description: + * Modify the value of an ADC register (not atomic). + * + * Input Parameters: + * priv - A reference to the ADC block status + * offset - The offset to the register to modify + * clrbits - The bits to clear + * setbits - The bits to set + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void adc_modifyreg(struct stm32_dev_s *priv, int offset, + uint32_t clrbits, uint32_t setbits) +{ + adc_putreg(priv, offset, (adc_getreg(priv, offset) & ~clrbits) | setbits); +} + +#ifdef HAVE_ADC_CMN_REGS + +/**************************************************************************** + * Name: adccmn_base_get + ****************************************************************************/ + +static uint32_t adccmn_base_get(struct stm32_dev_s *priv) +{ + uint32_t base = 0; + +#if defined(HAVE_IP_ADC_V2) + if (priv->base == STM32_ADC1_BASE || priv->base == STM32_ADC2_BASE) + { + base = STM32_ADC12CMN_BASE; + } +# if defined(CONFIG_STM32_ADC3) || defined(CONFIG_STM32_ADC4) + else + { + base = STM32_ADC34CMN_BASE; + } +# endif + +#elif defined(HAVE_IP_ADC_V1) + base = STM32_ADCCMN_BASE; + UNUSED(priv); +#endif + + return base; +} + +/**************************************************************************** + * Name: adccmn_modifyreg + ****************************************************************************/ + +static void adccmn_modifyreg(struct stm32_dev_s *priv, uint32_t offset, + uint32_t clrbits, uint32_t setbits) +{ + uint32_t base = 0; + + /* Get base address for ADC common register */ + + base = adccmn_base_get(priv); + + /* Modify register */ + + stm32_modifyreg32(offset + base, clrbits, setbits); +} + +/**************************************************************************** + * Name: adccmn_getreg + ****************************************************************************/ + +static uint32_t adccmn_getreg(struct stm32_dev_s *priv, uint32_t offset) +{ + uint32_t base = 0; + + /* Get base address for ADC common register */ + + base = adccmn_base_get(priv); + + /* Return register value */ + + return getreg32(base + offset); +} +#endif /* HAVE_ADC_CMN_REGS */ + +#ifdef ADC_HAVE_TIMER +/**************************************************************************** + * Name: tim_getreg + * + * Description: + * Read the value of an ADC timer register. + * + * Input Parameters: + * priv - A reference to the ADC block status + * offset - The offset to the register to read + * + * Returned Value: + * The current contents of the specified register + * + ****************************************************************************/ + +static uint16_t tim_getreg(struct stm32_dev_s *priv, int offset) +{ + return getreg16(priv->tbase + offset); +} + +/**************************************************************************** + * Name: tim_putreg + * + * Description: + * Write a value to an ADC timer register. + * + * Input Parameters: + * priv - A reference to the ADC block status + * offset - The offset to the register to write to + * value - The value to write to the register + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void tim_putreg(struct stm32_dev_s *priv, int offset, + uint16_t value) +{ + putreg16(value, priv->tbase + offset); +} + +/**************************************************************************** + * Name: tim_modifyreg + * + * Description: + * Modify the value of an ADC timer register (not atomic). + * + * Input Parameters: + * priv - A reference to the ADC block status + * offset - The offset to the register to modify + * clrbits - The bits to clear + * setbits - The bits to set + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void tim_modifyreg(struct stm32_dev_s *priv, int offset, + uint16_t clrbits, uint16_t setbits) +{ + tim_putreg(priv, offset, (tim_getreg(priv, offset) & ~clrbits) | setbits); +} + +#ifdef HAVE_IP_TIMERS_V2 +/**************************************************************************** + * Name: tim_modifyreg32 + * + * Description: + * Modify the value of an ADC timer register (not atomic). + * + * Input Parameters: + * priv - A reference to the ADC block status + * offset - The offset to the register to modify + * clrbits - The bits to clear + * setbits - The bits to set + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void tim_modifyreg32(struct stm32_dev_s *priv, int offset, + uint32_t clrbits, uint32_t setbits) +{ + uint32_t addr = priv->tbase + offset; + putreg32((getreg32(addr) & ~clrbits) | setbits, addr); +} +#endif + +/**************************************************************************** + * Name: tim_dumpregs + * + * Description: + * Dump all timer registers. + * + * Input Parameters: + * priv - A reference to the ADC block status + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void tim_dumpregs(struct stm32_dev_s *priv, const char *msg) +{ + ainfo("%s:\n", msg); + ainfo(" CR1: %04x CR2: %04x SMCR: %04x DIER: %04x\n", + tim_getreg(priv, STM32_GTIM_CR1_OFFSET), + tim_getreg(priv, STM32_GTIM_CR2_OFFSET), + tim_getreg(priv, STM32_GTIM_SMCR_OFFSET), + tim_getreg(priv, STM32_GTIM_DIER_OFFSET)); + ainfo(" SR: %04x EGR: 0000 CCMR1: %04x CCMR2: %04x\n", + tim_getreg(priv, STM32_GTIM_SR_OFFSET), + tim_getreg(priv, STM32_GTIM_CCMR1_OFFSET), + tim_getreg(priv, STM32_GTIM_CCMR2_OFFSET)); + ainfo(" CCER: %04x CNT: %04x PSC: %04x ARR: %04x\n", + tim_getreg(priv, STM32_GTIM_CCER_OFFSET), + tim_getreg(priv, STM32_GTIM_CNT_OFFSET), + tim_getreg(priv, STM32_GTIM_PSC_OFFSET), + tim_getreg(priv, STM32_GTIM_ARR_OFFSET)); + ainfo(" CCR1: %04x CCR2: %04x CCR3: %04x CCR4: %04x\n", + tim_getreg(priv, STM32_GTIM_CCR1_OFFSET), + tim_getreg(priv, STM32_GTIM_CCR2_OFFSET), + tim_getreg(priv, STM32_GTIM_CCR3_OFFSET), + tim_getreg(priv, STM32_GTIM_CCR4_OFFSET)); +#if STM32_NATIM > 0 + if (priv->tbase == STM32_TIM1_BASE +# ifdef STM32_TIM8_BASE + || priv->tbase == STM32_TIM8_BASE +# endif + ) + { + ainfo(" RCR: %04x BDTR: %04x DCR: %04x DMAR: %04x\n", + tim_getreg(priv, STM32_ATIM_RCR_OFFSET), + tim_getreg(priv, STM32_ATIM_BDTR_OFFSET), + tim_getreg(priv, STM32_ATIM_DCR_OFFSET), + tim_getreg(priv, STM32_ATIM_DMAR_OFFSET)); + } + else +#endif + { + ainfo(" DCR: %04x DMAR: %04x\n", + tim_getreg(priv, STM32_GTIM_DCR_OFFSET), + tim_getreg(priv, STM32_GTIM_DMAR_OFFSET)); + } +} + +/**************************************************************************** + * Name: adc_timstart + * + * Description: + * Start (or stop) the timer counter + * + * Input Parameters: + * priv - A reference to the ADC block status + * enable - True: Start conversion + * + * Returned Value: + * + ****************************************************************************/ + +static void adc_timstart(struct stm32_dev_s *priv, bool enable) +{ + ainfo("enable: %d\n", enable ? 1 : 0); + + if (enable) + { + /* Start the counter */ + + tim_modifyreg(priv, STM32_GTIM_CR1_OFFSET, 0, GTIM_CR1_CEN); + } + else + { + /* Disable the counter */ + + tim_modifyreg(priv, STM32_GTIM_CR1_OFFSET, GTIM_CR1_CEN, 0); + } +} + +/**************************************************************************** + * Name: adc_timinit + * + * Description: + * Initialize the timer that drivers the ADC sampling for this channel + * using the pre-calculated timer divider definitions. + * + * Input Parameters: + * priv - A reference to the ADC block status + * + * Returned Value: + * Zero on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int adc_timinit(struct stm32_dev_s *priv) +{ + uint32_t prescaler; + uint32_t reload; + uint32_t timclk; + + uint16_t clrbits = 0; + uint16_t setbits = 0; + uint16_t cr2; + uint16_t ccmr1; + uint16_t ccmr2; + uint16_t ocmode1; + uint16_t ocmode2; + uint16_t ccenable; + uint16_t ccer; + uint16_t egr; + + /* If the timer base address is zero, then this ADC was not configured to + * use a timer. + */ + + if (priv->tbase == 0) + { + return ERROR; + } + + /* NOTE: EXTSEL configuration is done in adc_reset function */ + + /* Configure the timer channel to drive the ADC */ + + /* Calculate optimal values for the timer prescaler and for the timer + * reload register. If freq is the desired frequency, then + * + * reload = timclk / freq + * reload = (pclck / prescaler) / freq + * + * There are many solutions to do this, but the best solution will be the + * one that has the largest reload value and the smallest prescaler value. + * That is the solution that should give us the most accuracy in the timer + * control. Subject to: + * + * 0 <= prescaler <= 65536 + * 1 <= reload <= 65535 + * + * So (prescaler = pclck / 65535 / freq) would be optimal. + */ + + prescaler = (priv->pclck / priv->freq + 65534) / 65535; + + /* We need to decrement the prescaler value by one, but only, the value + * does not underflow. + */ + + if (prescaler < 1) + { + awarn("WARNING: Prescaler underflowed.\n"); + prescaler = 1; + } + + /* Check for overflow */ + + else if (prescaler > 65536) + { + awarn("WARNING: Prescaler overflowed.\n"); + prescaler = 65536; + } + + timclk = priv->pclck / prescaler; + + reload = timclk / priv->freq; + if (reload < 1) + { + awarn("WARNING: Reload value underflowed.\n"); + reload = 1; + } + else if (reload > 65535) + { + awarn("WARNING: Reload value overflowed.\n"); + reload = 65535; + } + + /* Disable the timer until we get it configured */ + + adc_timstart(priv, false); + + /* Set up the timer CR1 register. + * + * Select the Counter Mode == count up: + * + * ATIM_CR1_EDGE: The counter counts up or down depending on the + * direction bit(DIR). + * ATIM_CR1_DIR: 0: count up, 1: count down + * + * Set the clock division to zero for all + */ + + clrbits = GTIM_CR1_DIR | GTIM_CR1_CMS_MASK | GTIM_CR1_CKD_MASK; + setbits = GTIM_CR1_EDGE; + tim_modifyreg(priv, STM32_GTIM_CR1_OFFSET, clrbits, setbits); + + /* Set the reload and prescaler values */ + + tim_putreg(priv, STM32_GTIM_PSC_OFFSET, prescaler - 1); + tim_putreg(priv, STM32_GTIM_ARR_OFFSET, reload); + + /* Clear the advanced timers repetition counter in TIM1 */ + +#if STM32_NATIM > 0 + if (priv->tbase == STM32_TIM1_BASE +# ifdef STM32_TIM8_BASE + || priv->tbase == STM32_TIM8_BASE +# endif + ) + { + tim_putreg(priv, STM32_ATIM_RCR_OFFSET, 0); + tim_putreg(priv, STM32_ATIM_BDTR_OFFSET, ATIM_BDTR_MOE); /* Check me */ + } +#endif + + /* TIMx event generation: Bit 0 UG: Update generation */ + + tim_putreg(priv, STM32_GTIM_EGR_OFFSET, GTIM_EGR_UG); + + /* Handle channel specific setup */ + + ocmode1 = 0; + ocmode2 = 0; + + switch (priv->trigger) + { + case 0: /* TimerX CC1 event */ + { + ccenable = ATIM_CCER_CC1E; + ocmode1 = (ATIM_CCMR_CCS_CCOUT << ATIM_CCMR1_CC1S_SHIFT) | + (ATIM_CCMR_MODE_PWM1 << ATIM_CCMR1_OC1M_SHIFT) | + ATIM_CCMR1_OC1PE; + + /* Set the event CC1 */ + + egr = ATIM_EGR_CC1G; + + /* Set the duty cycle by writing to the CCR register for this + * channel + */ + + tim_putreg(priv, STM32_GTIM_CCR1_OFFSET, (uint16_t)(reload >> 1)); + } + break; + + case 1: /* TimerX CC2 event */ + { + ccenable = ATIM_CCER_CC2E; + ocmode1 = (ATIM_CCMR_CCS_CCOUT << ATIM_CCMR1_CC2S_SHIFT) | + (ATIM_CCMR_MODE_PWM1 << ATIM_CCMR1_OC2M_SHIFT) | + ATIM_CCMR1_OC2PE; + + /* Set the event CC2 */ + + egr = ATIM_EGR_CC2G; + + /* Set the duty cycle by writing to the CCR register for this + * channel + */ + + tim_putreg(priv, STM32_GTIM_CCR2_OFFSET, (uint16_t)(reload >> 1)); + } + break; + + case 2: /* TimerX CC3 event */ + { + ccenable = ATIM_CCER_CC3E; + ocmode2 = (ATIM_CCMR_CCS_CCOUT << ATIM_CCMR2_CC3S_SHIFT) | + (ATIM_CCMR_MODE_PWM1 << ATIM_CCMR2_OC3M_SHIFT) | + ATIM_CCMR2_OC3PE; + + /* Set the event CC3 */ + + egr = ATIM_EGR_CC3G; + + /* Set the duty cycle by writing to the CCR register for this + * channel + */ + + tim_putreg(priv, STM32_GTIM_CCR3_OFFSET, (uint16_t)(reload >> 1)); + } + break; + + case 3: /* TimerX CC4 event */ + { + ccenable = ATIM_CCER_CC4E; + ocmode2 = (ATIM_CCMR_CCS_CCOUT << ATIM_CCMR2_CC4S_SHIFT) | + (ATIM_CCMR_MODE_PWM1 << ATIM_CCMR2_OC4M_SHIFT) | + ATIM_CCMR2_OC4PE; + + /* Set the event CC4 */ + + egr = ATIM_EGR_CC4G; + + /* Set the duty cycle by writing to the CCR register for this + * channel + */ + + tim_putreg(priv, STM32_GTIM_CCR4_OFFSET, (uint16_t)(reload >> 1)); + } + break; + + case 4: /* TimerX TRGO event */ + { + /* Set the event TRGO */ + + ccenable = 0; + egr = GTIM_EGR_TG; + + tim_modifyreg(priv, STM32_GTIM_CR2_OFFSET, clrbits, + GTIM_CR2_MMS_UPDATE); + } + break; + +#ifdef HAVE_IP_TIMERS_V2 + case 5: /* TimerX TRGO2 event */ + { + /* Set the event TRGO2 */ + + ccenable = 0; + egr = GTIM_EGR_TG; + + tim_modifyreg32(priv, STM32_ATIM_CR2_OFFSET, clrbits, + ATIM_CR2_MMS2_UPDATE); + } + break; +#endif + + default: + aerr("ERROR: No such trigger: %d\n", priv->trigger); + return -EINVAL; + } + + /* Disable the Channel by resetting the CCxE Bit in the CCER register */ + + ccer = tim_getreg(priv, STM32_GTIM_CCER_OFFSET); + ccer &= ~ccenable; + tim_putreg(priv, STM32_GTIM_CCER_OFFSET, ccer); + + /* Fetch the CR2, CCMR1, and CCMR2 register (already have ccer) */ + + cr2 = tim_getreg(priv, STM32_GTIM_CR2_OFFSET); + ccmr1 = tim_getreg(priv, STM32_GTIM_CCMR1_OFFSET); + ccmr2 = tim_getreg(priv, STM32_GTIM_CCMR2_OFFSET); + + /* Reset the Output Compare Mode Bits and set the select output compare + * mode + */ + + ccmr1 &= ~(ATIM_CCMR1_CC1S_MASK | ATIM_CCMR1_OC1M_MASK | ATIM_CCMR1_OC1PE | + ATIM_CCMR1_CC2S_MASK | ATIM_CCMR1_OC2M_MASK | ATIM_CCMR1_OC2PE); + ccmr2 &= ~(ATIM_CCMR2_CC3S_MASK | ATIM_CCMR2_OC3M_MASK | ATIM_CCMR2_OC3PE | + ATIM_CCMR2_CC4S_MASK | ATIM_CCMR2_OC4M_MASK | ATIM_CCMR2_OC4PE); + ccmr1 |= ocmode1; + ccmr2 |= ocmode2; + + /* Reset the output polarity level of all channels (selects high + * polarity) + */ + + ccer &= ~(ATIM_CCER_CC1P | ATIM_CCER_CC2P | + ATIM_CCER_CC3P | ATIM_CCER_CC4P); + + /* Enable the output state of the selected channel (only) */ + + ccer &= ~(ATIM_CCER_CC1E | ATIM_CCER_CC2E | + ATIM_CCER_CC3E | ATIM_CCER_CC4E); + ccer |= ccenable; + + /* TODO: revisit and simplify logic below */ + +#if STM32_NATIM > 0 + if (priv->tbase == STM32_TIM1_BASE +# ifdef STM32_TIM8_BASE + || priv->tbase == STM32_TIM8_BASE +# endif + ) + { + /* Reset output N polarity level, output N state, output compare state, + * output compare N idle state. + */ + + ccer &= ~(ATIM_CCER_CC1NE | ATIM_CCER_CC1NP | + ATIM_CCER_CC2NE | ATIM_CCER_CC2NP | + ATIM_CCER_CC3NE | ATIM_CCER_CC3NP); + + /* Reset the output compare and output compare N IDLE State */ + + cr2 &= ~(ATIM_CR2_OIS1 | ATIM_CR2_OIS1N | + ATIM_CR2_OIS2 | ATIM_CR2_OIS2N | + ATIM_CR2_OIS3 | ATIM_CR2_OIS3N | + ATIM_CR2_OIS4); + } +# if defined(HAVE_GTIM_CCXNP) + else + { + ccer &= ~(GTIM_CCER_CC1NP | GTIM_CCER_CC2NP | GTIM_CCER_CC3NP | + GTIM_CCER_CC4NP); + } +# endif + +#else /* No ADV TIM */ + + /* For the STM32L15XX family only these timers can be used: 2-4, 6, 7, 9, + * 10. Reset the output compare and output compare N IDLE State + */ + + if (priv->tbase >= STM32_TIM2_BASE && priv->tbase <= STM32_TIM4_BASE) + { + /* Reset output N polarity level, output N state, output compare state, + * output compare N idle state. + */ + + ccer &= ~(GTIM_CCER_CC1NE | GTIM_CCER_CC1NP | + GTIM_CCER_CC2NE | GTIM_CCER_CC2NP | + GTIM_CCER_CC3NE | GTIM_CCER_CC3NP | + GTIM_CCER_CC4NP); + } +#endif + + /* Save the modified register values */ + + tim_putreg(priv, STM32_GTIM_CR2_OFFSET, cr2); + tim_putreg(priv, STM32_GTIM_CCMR1_OFFSET, ccmr1); + tim_putreg(priv, STM32_GTIM_CCMR2_OFFSET, ccmr2); + tim_putreg(priv, STM32_GTIM_CCER_OFFSET, ccer); + tim_putreg(priv, STM32_GTIM_EGR_OFFSET, egr); + + /* Set the ARR Preload Bit */ + + tim_modifyreg(priv, STM32_GTIM_CR1_OFFSET, 0, GTIM_CR1_ARPE); + + /* Enable the timer counter */ + + adc_timstart(priv, true); + + tim_dumpregs(priv, "After starting timers"); + + return OK; +} +#endif + +/**************************************************************************** + * Name: adc_reg_startconv + * + * Description: + * Start (or stop) the ADC regular conversion process + * + * Input Parameters: + * priv - A reference to the ADC block status + * enable - True: Start conversion + * + * Returned Value: + * + ****************************************************************************/ + +#if defined(HAVE_IP_ADC_V2) +static void adc_reg_startconv(struct stm32_dev_s *priv, bool enable) +{ + uint32_t regval; + + ainfo("reg enable: %d\n", enable ? 1 : 0); + + if (enable) + { + /* Start the conversion of regular channels */ + + adc_modifyreg(priv, STM32_ADC_CR_OFFSET, 0, ADC_CR_ADSTART); + } + else + { + regval = adc_getreg(priv, STM32_ADC_CR_OFFSET); + + /* Is a conversion ongoing? */ + + if ((regval & ADC_CR_ADSTART) != 0) + { + /* Stop the conversion */ + + adc_putreg(priv, STM32_ADC_CR_OFFSET, regval | ADC_CR_ADSTP); + + /* Wait for the conversion to stop */ + + while ((adc_getreg(priv, STM32_ADC_CR_OFFSET) & + ADC_CR_ADSTP) != 0); + } + } +} +#elif defined(HAVE_IP_ADC_V1) && !defined(HAVE_BASIC_ADC) +static void adc_reg_startconv(struct stm32_dev_s *priv, bool enable) +{ + ainfo("reg enable: %d\n", enable ? 1 : 0); + + if (enable) + { + /* Start the conversion of regular channels */ + + adc_modifyreg(priv, STM32_ADC_CR2_OFFSET, 0, ADC_CR2_SWSTART); + } + else + { + /* Stop the conversion */ + + adc_modifyreg(priv, STM32_ADC_CR2_OFFSET, ADC_CR2_SWSTART, 0); + } +} +#else /* ADV IPv1 BASIC */ +static void adc_reg_startconv(struct stm32_dev_s *priv, bool enable) +{ + ainfo("reg enable: %d\n", enable ? 1 : 0); + + if (!enable) + { + /* Clear ADON to stop the conversion and put the ADC in the + * power down state. + */ + + adc_enable(priv, false); + } + + /* If the ADC is already on, set ADON again to start the conversion. + * Otherwise, set ADON once to wake up the ADC from the power down state. + */ + + adc_enable(priv, true); +} +#endif + +#ifdef ADC_HAVE_INJECTED + +/**************************************************************************** + * Name: adc_inj_startconv + * + * Description: + * Start (or stop) the ADC injected conversion process + * + * Input Parameters: + * priv - A reference to the ADC block status + * enable - True: Start conversion + * + * Returned Value: + * + ****************************************************************************/ + +#if defined(HAVE_IP_ADC_V2) +static void adc_inj_startconv(struct stm32_dev_s *priv, bool enable) +{ + uint32_t regval; + + ainfo("inj enable: %d\n", enable ? 1 : 0); + + if (enable) + { + /* Start the conversion of regular channels */ + + adc_modifyreg(priv, STM32_ADC_CR_OFFSET, 0, ADC_CR_JADSTART); + } + else + { + regval = adc_getreg(priv, STM32_ADC_CR_OFFSET); + + /* Is a conversion ongoing? */ + + if ((regval & ADC_CR_JADSTART) != 0) + { + /* Stop the conversion */ + + adc_putreg(priv, STM32_ADC_CR_OFFSET, regval | ADC_CR_JADSTP); + + /* Wait for the conversion to stop */ + + while ((adc_getreg(priv, STM32_ADC_CR_OFFSET) & + ADC_CR_JADSTP) != 0); + } + } +} +#elif defined(HAVE_IP_ADC_V1) +static void adc_inj_startconv(struct stm32_dev_s *priv, bool enable) +{ + ainfo("inj enable: %d\n", enable ? 1 : 0); + + if (enable) + { + /* Start the conversion of injected channels */ + + adc_modifyreg(priv, STM32_ADC_CR2_OFFSET, 0, ADC_CR2_JSWSTART); + } + else + { + /* Stop the conversion */ + + adc_modifyreg(priv, STM32_ADC_CR2_OFFSET, ADC_CR2_JSWSTART, 0); + } +} +#endif + +#endif /* ADC_HAVE_INJECTED */ + +/**************************************************************************** + * Name: adc_rccreset + * + * Description: + * Deinitializes the ADCx peripheral registers to their default + * reset values. It could set all the ADCs configured. + * + * Input Parameters: + * priv - A reference to the ADC block status + * reset - Condition, set or reset + * + * Returned Value: + * + ****************************************************************************/ + +#if defined(HAVE_IP_ADC_V1) && defined(HAVE_BASIC_ADC) +static void adc_rccreset(struct stm32_dev_s *priv, bool reset) +{ + uint32_t adcbit; + + /* Pick the appropriate bit in the RCC reset register. + * For the basic STM32 ADC IPv1, there is an individual bit to reset + * each ADC (ADC12 and ADC34). + */ + + switch (priv->intf) + { +#ifdef CONFIG_STM32_ADC1 + case 1: + { + adcbit = RCC_RSTR_ADC1RST; + break; + } + +#endif +#ifdef CONFIG_STM32_ADC2 + case 2: + { + adcbit = RCC_RSTR_ADC2RST; + break; + } + +#endif +#ifdef CONFIG_STM32_ADC3 + case 3: + { + adcbit = RCC_RSTR_ADC3RST; + break; + } + +#endif +#ifdef CONFIG_STM32_ADC4 + case 4: + { + adcbit = RCC_RSTR_ADC4RST; + break; + } + +#endif + default: + { + return; + } + } + + /* Set or clear the selected bit in the RCC reset register */ + + if (reset) + { + /* Enable ADC reset state */ + + modifyreg32(STM32_RCC_RSTR, 0, adcbit); + } + else + { + /* Release ADC from reset state */ + + modifyreg32(STM32_RCC_RSTR, adcbit, 0); + } +} +#elif defined(HAVE_IP_ADC_V1) +static void adc_rccreset(struct stm32_dev_s *priv, bool reset) +{ + uint32_t adcbit; + + /* Pick the appropriate bit in the RCC reset register. + * For the STM32 ADC IPv1, there is one common reset for all ADCs. + */ + + switch (priv->intf) + { + case 1: + case 2: + case 3: + { + adcbit = RCC_RSTR_ADC123RST; + break; + } + + default: + { + return; + } + } + + /* Set or clear the selected bit in the RCC reset register */ + + if (reset) + { + /* Enable ADC reset state */ + + modifyreg32(STM32_RCC_RSTR, 0, adcbit); + } + else + { + /* Release ADC from reset state */ + + modifyreg32(STM32_RCC_RSTR, adcbit, 0); + } +} +#elif defined(HAVE_IP_ADC_V2) +static void adc_rccreset(struct stm32_dev_s *priv, bool reset) +{ + uint32_t adcbit; + + /* Pick the appropriate bit in the RCC reset register. + * For the STM32 ADC IPv2, there is an individual bit to reset each + * ADC block. + */ + + switch (priv->intf) + { +#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) + case 1: + case 2: + { + adcbit = RCC_RSTR_ADC12RST; + break; + } + +#endif +#if defined(CONFIG_STM32_ADC3) || defined(CONFIG_STM32_ADC4) + case 3: + case 4: + { + adcbit = RCC_RSTR_ADC34RST; + break; + } + +#endif + default: + { + return; + } + } + + /* Set or clear the selected bit in the RCC reset register */ + + if (reset) + { + /* Enable ADC reset state */ + + modifyreg32(STM32_RCC_RSTR, 0, adcbit); + } + else + { + /* Release ADC from reset state */ + + modifyreg32(STM32_RCC_RSTR, adcbit, 0); + } +} +#endif + +/**************************************************************************** + * Name: adc_power_down_idle + * + * Description: + * Enables or disables power down during the idle phase. + * + * Input Parameters: + * + * priv - pointer to the adc device structure + * pdi_high - true: The ADC is powered down when waiting for a start event + * false: The ADC is powered up when waiting for a start event + * + * Returned Value: + * None. + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_STM32L15XX +static void adc_power_down_idle(struct stm32_dev_s *priv, bool pdi_high) +{ + uint32_t regval; + + ainfo("PDI: %d\n", pdi_high ? 1 : 0); + + regval = adc_getreg(priv, STM32_ADC_CR1_OFFSET); + + if ((STM32_ADC1_CR2 & ADC_CR2_ADON) == 0) + { + if (pdi_high) + { + regval |= ADC_CR1_PDI; + } + else + { + regval &= ~ADC_CR1_PDI; + } + + adc_putreg(priv, STM32_ADC_CR1_OFFSET, regval); + } +} +#endif + +/**************************************************************************** + * Name: adc_power_down_delay + * + * Description: + * Enables or disables power down during the delay phase. + * + * Input Parameters: + * + * priv - pointer to the adc device structure + * pdd_high - true: The ADC is powered down when waiting for a start event + * false: The ADC is powered up when waiting for a start event + * + * Returned Value: + * None. + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_STM32L15XX +static void adc_power_down_delay(struct stm32_dev_s *priv, bool pdd_high) +{ + uint32_t regval; + + ainfo("PDD: %d\n", pdd_high ? 1 : 0); + + regval = adc_getreg(priv, STM32_ADC_CR1_OFFSET); + + if ((STM32_ADC1_CR2 & ADC_CR2_ADON) == 0) + { + if (pdd_high) + { + regval |= ADC_CR1_PDD; + } + else + { + regval &= ~ADC_CR1_PDD; + } + + adc_putreg(priv, STM32_ADC_CR1_OFFSET, regval); + } +} +#endif + +/**************************************************************************** + * Name: adc_dels_after_conversion + * + * Description: + * Defines the length of the delay which is applied after a conversion or + * a sequence of conversions. + * + * Input Parameters: + * + * priv - pointer to the adc device structure + * delay - delay selection (see definition in chip/chip/stm32_adc.h + * starting from line 284) + * + * Returned Value: + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_STM32L15XX +static void adc_dels_after_conversion(struct stm32_dev_s *priv, + uint32_t delay) +{ + ainfo("Delay selected: 0x%08" PRIx32 "\n", delay); + + adc_modifyreg(priv, STM32_ADC_CR2_OFFSET, ADC_CR2_DELS_MASK, delay); +} +#endif + +/**************************************************************************** + * Name: adc_select_ch_bank + * + * Description: + * Selects the bank of channels to be converted + * (! Must be modified only when no conversion is on going !) + * + * Input Parameters: + * + * priv - pointer to the adc device structure + * enable - true: bank of channels B selected + * false: bank of channels A selected + * + * Returned Value: + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_STM32L15XX +static void adc_select_ch_bank(struct stm32_dev_s *priv, + bool chb_selected) +{ + ainfo("Bank of channels selected: %c\n", chb_selected ? 'B' : 'A'); + + if (chb_selected) + { + adc_modifyreg(priv, STM32_ADC_CR2_OFFSET, 0, ADC_CR2_CFG); + } + else + { + adc_modifyreg(priv, STM32_ADC_CR2_OFFSET, ADC_CR2_CFG, 0); + } +} +#endif + +/**************************************************************************** + * Name: adc_enable + * + * Description: + * Enables or disables the specified ADC peripheral. Also, starts a + * conversion when the ADC is not triggered by timers + * + * Input Parameters: + * + * enable - true: enable ADC conversion + * false: disable ADC conversion + * + * Returned Value: + * + ****************************************************************************/ + +#if defined(HAVE_IP_ADC_V2) +static void adc_enable(struct stm32_dev_s *priv, bool enable) +{ + uint32_t regval; + + ainfo("enable: %d\n", enable ? 1 : 0); + + regval = adc_getreg(priv, STM32_ADC_CR_OFFSET); + + if (enable) + { + /* Enable the ADC */ + + adc_putreg(priv, STM32_ADC_CR_OFFSET, regval | ADC_CR_ADEN); + + /* Wait for the ADC to be ready */ + + while ((adc_getreg(priv, STM32_ADC_ISR_OFFSET) & ADC_INT_ARDY) == 0); + } + else if ((regval & ADC_CR_ADEN) != 0 && (regval & ADC_CR_ADDIS) == 0) + { + /* Stop ongoing regular conversions */ + + adc_reg_startconv(priv, false); + + /* Disable the ADC */ + + adc_putreg(priv, STM32_ADC_CR_OFFSET, regval | ADC_CR_ADDIS); + + /* Wait for the ADC to be disabled */ + + while ((adc_getreg(priv, STM32_ADC_CR_OFFSET) & ADC_CR_ADEN) != 0); + } +} +#else /* HAVE_IP_ADC_V1 */ +static void adc_enable(struct stm32_dev_s *priv, bool enable) +{ +#ifdef ADC_SR_ADONS + bool enabled = (adc_getreg(priv, STM32_ADC_SR_OFFSET) & ADC_SR_ADONS) != 0; +#else + bool enabled = false; +#endif + + ainfo("enable: %d\n", enable ? 1 : 0); + + if (!enabled && enable) + { + adc_modifyreg(priv, STM32_ADC_CR2_OFFSET, 0, ADC_CR2_ADON); + } + else if (enabled && !enable) + { + adc_modifyreg(priv, STM32_ADC_CR2_OFFSET, ADC_CR2_ADON, 0); + } +} +#endif + +/**************************************************************************** + * Name: adc_dmaconvcallback + * + * Description: + * Callback for DMA. Called from the DMA transfer complete interrupt after + * all channels have been converted and transferred with DMA. + * + * Input Parameters: + * + * handle - handle to DMA + * isr - + * arg - adc device + * + * Returned Value: + * + ****************************************************************************/ + +#if defined(ADC_HAVE_DMA) && !defined(CONFIG_STM32_ADC_NOIRQ) +static void adc_dmaconvcallback(DMA_HANDLE handle, uint8_t isr, + void *arg) +{ + struct adc_dev_s *dev = (struct adc_dev_s *)arg; + struct stm32_dev_s *priv = (struct stm32_dev_s *)dev->ad_priv; + int i; + + /* Verify that the upper-half driver has bound its callback functions */ + + if (priv->cb != NULL) + { + DEBUGASSERT(priv->cb->au_receive != NULL); + + for (i = 0; i < priv->rnchannels * priv->dmabatch; i++) + { + priv->cb->au_receive(dev, priv->r_chanlist[priv->current], + priv->r_dmabuffer[i]); + priv->current++; + if (priv->current >= priv->rnchannels) + { + /* Restart the conversion sequence from the beginning */ + + priv->current = 0; + } + } + } + + /* Restart DMA for the next conversion series */ + + adc_modifyreg(priv, STM32_ADC_DMAREG_OFFSET, ADC_DMAREG_DMA, 0); + adc_modifyreg(priv, STM32_ADC_DMAREG_OFFSET, 0, ADC_DMAREG_DMA); +} +#endif + +/**************************************************************************** + * Name: adc_bind + * + * Description: + * Bind the upper-half driver callbacks to the lower-half implementation. + * This must be called early in order to receive ADC event notifications. + * + ****************************************************************************/ + +static int adc_bind(struct adc_dev_s *dev, + const struct adc_callback_s *callback) +{ +#ifdef ADC_HAVE_CB + struct stm32_dev_s *priv = (struct stm32_dev_s *)dev->ad_priv; + + DEBUGASSERT(priv != NULL); + priv->cb = callback; +#else + UNUSED(dev); + UNUSED(callback); +#endif + + return OK; +} + +/**************************************************************************** + * Name: adc_watchdog_cfg + ****************************************************************************/ + +#if defined(HAVE_IP_ADC_V2) +static void adc_watchdog_cfg(struct stm32_dev_s *priv) +{ + uint32_t clrbits = 0; + uint32_t setbits = 0; + + /* Initialize the watchdog 1 threshold register */ + + adc_putreg(priv, STM32_ADC_TR1_OFFSET, 0x0fff0000); + + /* Enable the analog watchdog */ + + clrbits = ADC_CFGR1_AWD1CH_MASK; + setbits = ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL | + (priv->r_chanlist[0] << ADC_CFGR1_AWD1CH_SHIFT); + + /* Modify CFGR configuration */ + + adc_modifyreg(priv, STM32_ADC_CFGR1_OFFSET, clrbits, setbits); +} +#else +static void adc_watchdog_cfg(struct stm32_dev_s *priv) +{ + uint32_t clrbits = 0; + uint32_t setbits = 0; + + /* Initialize the watchdog high threshold register */ + + adc_putreg(priv, STM32_ADC_HTR_OFFSET, 0x00000fff); + + /* Initialize the watchdog low threshold register */ + + adc_putreg(priv, STM32_ADC_LTR_OFFSET, 0x00000000); + + clrbits = ADC_CR1_AWDCH_MASK; + setbits = ADC_CR1_AWDEN | (priv->r_chanlist[0] << ADC_CR1_AWDCH_SHIFT); + + /* Modify CR1 configuration */ + + adc_modifyreg(priv, STM32_ADC_CR1_OFFSET, clrbits, setbits); +} +#endif + +/**************************************************************************** + * Name: adc_calibrate + ****************************************************************************/ + +#if defined(HAVE_IP_ADC_V2) +static void adc_calibrate(struct stm32_dev_s *priv) +{ +#if 0 /* Doesn't work */ + /* Calibrate the ADC */ + + adc_modifyreg(priv, STM32_ADC_CR_OFFSET, ADC_CR_ADCALDIF, AD_CR_ADCAL); + + /* Wait for the calibration to complete */ + + while ((adc_getreg(priv, STM32_ADC_CR_OFFSET) & ADC_CR_ADCAL) != 0); + +#else + UNUSED(priv); +#endif +} +#elif defined(HAVE_IP_ADC_V1) && defined(HAVE_BASIC_ADC) +static void adc_calibrate(struct stm32_dev_s *priv) +{ + /* Power on the ADC */ + + adc_modifyreg(priv, STM32_ADC_CR2_OFFSET, 0, ADC_CR2_ADON); + + /* Wait for the ADC power on at least 2 ADCCLK cycles */ + + up_udelay(10); + + /* Reset calibration registers */ + + adc_modifyreg(priv, STM32_ADC_CR2_OFFSET, 0, ADC_CR2_RSTCAL); + + /* Wait for the calibration register reset to complete */ + + while ((adc_getreg(priv, STM32_ADC_CR2_OFFSET) & ADC_CR2_RSTCAL) != 0); + + /* Start ADC auto-calibration procedure */ + + adc_modifyreg(priv, STM32_ADC_CR2_OFFSET, 0, ADC_CR2_CAL); + + /* Wait for the calibration procedure to complete */ + + while ((adc_getreg(priv, STM32_ADC_CR2_OFFSET) & ADC_CR2_CAL) != 0); + + /* Power off the ADC */ + + adc_modifyreg(priv, STM32_ADC_CR2_OFFSET, ADC_CR2_ADON, 0); +} +#else +# define adc_calibrate(priv) +#endif + +/**************************************************************************** + * Name: adc_mode_cfg + ****************************************************************************/ + +#ifdef HAVE_IP_ADC_V2 +static void adc_mode_cfg(struct stm32_dev_s *priv) +{ + uint32_t clrbits = 0; + uint32_t setbits = 0; + + /* Disable continuous mode and set align to right */ + + clrbits = ADC_CFGR1_CONT | ADC_CFGR1_ALIGN; + + /* Disable external trigger for regular channels */ + + clrbits |= ADC_CFGR1_EXTEN_MASK; + setbits |= ADC_CFGR1_EXTEN_NONE; + + /* Set CFGR configuration */ + + adc_modifyreg(priv, STM32_ADC_CFGR1_OFFSET, clrbits, setbits); +} +#else +static void adc_mode_cfg(struct stm32_dev_s *priv) +{ + uint32_t clrbits = 0; + uint32_t setbits = 0; + +#ifdef HAVE_BASIC_ADC + /* Set independent mode */ + + clrbits |= ADC_CR1_DUALMOD_MASK; + setbits |= ADC_CR1_IND; +#endif + +#ifdef ADC_HAVE_SCAN + if (priv->scan == true) + { + setbits |= ADC_CR1_SCAN; + } +#endif + + /* Set CR1 configuration */ + + adc_modifyreg(priv, STM32_ADC_CR1_OFFSET, clrbits, setbits); + + /* REVISIT: */ + +#ifdef CONFIG_STM32_STM32L15XX + + /* Select the bank of channels A */ + + adc_select_ch_bank(priv, false); + +# ifdef HAVE_ADC_POWERDOWN + /* Disables power down during the delay phase */ + + adc_power_down_idle(priv, false); + adc_power_down_delay(priv, false); +# endif + + /* Delay until the converted data has been read */ + + adc_dels_after_conversion(priv, ADC_CR2_DELS_TILLRD); +#endif + + /* Disable continuous mode and set align to right */ + + clrbits = ADC_CR2_CONT | ADC_CR2_ALIGN; + setbits = 0; + + /* Disable external trigger for regular channels */ + + clrbits |= ADC_EXTREG_EXTEN_MASK; + setbits |= ADC_EXTREG_EXTEN_NONE; + + /* Enable software trigger for regular channels + * REVISIT: SWSTART must be set if no EXT trigger and basic ADC IPv1 + */ + +#ifdef CONFIG_STM32_STM32F37XX + clrbits |= ADC_CR2_EXTSEL_MASK; + setbits |= ADC_CR2_EXTSEL_SWSTART | ADC_CR2_EXTTRIG; /* SW is considered as external trigger */ +#endif + + /* Set CR2 configuration */ + + adc_modifyreg(priv, STM32_ADC_CR2_OFFSET, clrbits, setbits); +} +#endif + +/**************************************************************************** + * Name: adc_voltreg_cfg + ****************************************************************************/ + +#if defined(HAVE_IP_ADC_V2) +static void adc_voltreg_cfg(struct stm32_dev_s *priv) +{ + /* Set ADC voltage regulator to intermediate state */ + + adc_modifyreg(priv, STM32_ADC_CR_OFFSET, ADC_CR_ADVREGEN_MASK, + ADC_CR_ADVREGEN_INTER); + + /* Enable the ADC voltage regulator */ + + adc_modifyreg(priv, STM32_ADC_CR_OFFSET, ADC_CR_ADVREGEN_MASK, + ADC_CR_ADVREGEN_ENABLED); + + /* Wait for the ADC voltage regulator to startup */ + + up_udelay(10); +} +#else +static void adc_voltreg_cfg(struct stm32_dev_s *priv) +{ + /* Nothing to do here */ + + UNUSED(priv); +} +#endif + +/**************************************************************************** + * Name: adc_sampletime_cfg + ****************************************************************************/ + +static void adc_sampletime_cfg(struct adc_dev_s *dev) +{ + /* Initialize the same sample time for each ADC. + * During sample cycles channel selection bits must remain unchanged. + */ + +#ifdef CONFIG_STM32_ADC_CHANGE_SAMPLETIME + adc_sampletime_write((struct stm32_adc_dev_s *)dev->ad_priv); +#else + struct stm32_dev_s *priv = (struct stm32_dev_s *)dev->ad_priv; + + adc_putreg(priv, STM32_ADC_SMPR1_OFFSET, ADC_SMPR1_DEFAULT); + adc_putreg(priv, STM32_ADC_SMPR2_OFFSET, ADC_SMPR2_DEFAULT); +# ifdef STM32_ADC_SMPR3_OFFSET + adc_putreg(priv, STM32_ADC_SMPR3_OFFSET, ADC_SMPR3_DEFAULT); +# endif +# ifdef STM32_ADC_SMPR0_OFFSET + adc_putreg(priv, STM32_ADC_SMPR0_OFFSET, ADC_SMPR0_DEFAULT); +# endif +#endif +} + +/**************************************************************************** + * Name: adc_common_cfg + ****************************************************************************/ + +#if defined(HAVE_IP_ADC_V2) +static void adc_common_cfg(struct stm32_dev_s *priv) +{ + uint32_t clrbits = 0; + uint32_t setbits = 0; + + /* REVISIT: */ + + clrbits = ADC_CCR_DUAL_MASK | ADC_CCR_DELAY_MASK | ADC_CCR_DMACFG | + ADC_CCR_MDMA_MASK | ADC_CCR_CKMODE_MASK | ADC_CCR_VREFEN | + ADC_CCR_TSEN | ADC_CCR_VBATEN; + setbits = ADC_CCR_DUAL_IND | ADC_CCR_DELAY(1) | ADC_CCR_MDMA_DISABLED | + ADC_CCR_CKMODE_ASYNCH; + + adccmn_modifyreg(priv, STM32_ADC_CCR_OFFSET, clrbits, setbits); +} +#elif defined(HAVE_IP_ADC_V1) && !defined(HAVE_BASIC_ADC) +static void adc_common_cfg(struct stm32_dev_s *priv) +{ + uint32_t clrbits = 0; + uint32_t setbits = 0; + + clrbits = ADC_CCR_ADCPRE_MASK | ADC_CCR_TSVREFE; + setbits = ADC_CCR_ADCPRE_DIV2; + + /* REVISIT: */ + +#if !defined(CONFIG_STM32_STM32L15XX) + clrbits |= ADC_CCR_MULTI_MASK | ADC_CCR_DELAY_MASK | ADC_CCR_DDS | + ADC_CCR_DMA_MASK | ADC_CCR_VBATEN; + setbits |= ADC_CCR_MULTI_NONE | ADC_CCR_DMA_DISABLED; +#endif /* !defined(CONFIG_STM32_STM32L15XX) */ + + adccmn_modifyreg(priv, STM32_ADC_CCR_OFFSET, clrbits, setbits); +} +#else +static void adc_common_cfg(struct stm32_dev_s *priv) +{ + /* Do nothing here */ + + UNUSED(priv); +} +#endif + +#ifdef ADC_HAVE_DMA +/**************************************************************************** + * Name: adc_dma_cfg + ****************************************************************************/ + +#ifdef HAVE_IP_ADC_V2 +static void adc_dma_cfg(struct stm32_dev_s *priv) +{ + uint32_t clrbits = 0; + uint32_t setbits = 0; + + /* Set DMA mode */ + + if (priv->dmacfg == 0) + { + /* One Shot Mode */ + + clrbits |= ADC_CFGR1_DMACFG; + } + else + { + /* Circular Mode */ + + setbits |= ADC_CFGR1_DMACFG; + } + + /* Enable DMA */ + + setbits |= ADC_CFGR1_DMAEN; + + /* Modify CFGR configuration */ + + adc_modifyreg(priv, STM32_ADC_CFGR1_OFFSET, clrbits, setbits); +} +#else +static void adc_dma_cfg(struct stm32_dev_s *priv) +{ + uint32_t clrbits = 0; + uint32_t setbits = 0; + +#ifdef ADC_HAVE_DMACFG + /* Set DMA mode */ + + if (priv->dmacfg == 0) + { + /* One Shot Mode */ + + clrbits |= ADC_CR2_DDS; + } + else + { + /* Circular Mode */ + + setbits |= ADC_CR2_DDS; + } +#endif + + /* Enable DMA */ + + setbits |= ADC_CR2_DMA; + + /* Modify CR2 configuration */ + + adc_modifyreg(priv, STM32_ADC_CR2_OFFSET, clrbits, setbits); +} +#endif + +/**************************************************************************** + * Name: adc_dma_start + ****************************************************************************/ + +static void adc_dma_start(struct adc_dev_s *dev) +{ + struct stm32_dev_s *priv = (struct stm32_dev_s *)dev->ad_priv; + + /* Stop and free DMA if it was started before */ + + if (priv->dma != NULL) + { + stm32_dmastop(priv->dma); + stm32_dmafree(priv->dma); + } + + priv->dma = stm32_dmachannel(priv->dmachan); + +#ifndef CONFIG_STM32_ADC_NOIRQ + /* Start DMA only if standard ADC interrupts used */ + + stm32_dmasetup(priv->dma, + priv->base + STM32_ADC_DR_OFFSET, + (uint32_t)priv->r_dmabuffer, + priv->rnchannels * priv->dmabatch, + ADC_DMA_CONTROL_WORD); + + stm32_dmastart(priv->dma, adc_dmaconvcallback, dev, false); +#endif +} +#endif /* ADC_HAVE_DMA */ + +/**************************************************************************** + * Name: adc_configure + ****************************************************************************/ + +static void adc_configure(struct adc_dev_s *dev) +{ + struct stm32_dev_s *priv = (struct stm32_dev_s *)dev->ad_priv; + + /* Turn off the ADC before configuration */ + + adc_enable(priv, false); + + /* Configure voltage regulator if present */ + + adc_voltreg_cfg(priv); + + /* Calibrate ADC - doesn't work for now */ + + adc_calibrate(priv); + + /* Initialize the ADC watchdog */ + + adc_watchdog_cfg(priv); + + /* Initialize the ADC sample time */ + + adc_sampletime_cfg(dev); + + /* Set ADC working mode */ + + adc_mode_cfg(priv); + + /* Configuration of the channel conversions */ + + if (priv->cr_channels > 0) + { + adc_set_ch(dev, 0); + } + +#ifdef ADC_HAVE_INJECTED + /* Configuration of the injected channel conversions after adc enabled */ + + if (priv->cj_channels > 0) + { + adc_inj_set_ch(dev, 0); + } +#endif + + /* ADC common register configuration */ + + adc_common_cfg(priv); + +#ifdef ADC_HAVE_DMA + /* Configure ADC DMA if enabled */ + + if (priv->hasdma) + { + /* Configure ADC DMA */ + + adc_dma_cfg(priv); + + /* Start ADC DMA */ + + adc_dma_start(dev); + } +#endif + +#ifdef HAVE_ADC_RESOLUTION + /* Configure ADC resolution */ + + adc_resolution_set(dev, priv->resolution); +#endif + +#ifdef ADC_HAVE_EXTCFG + /* Configure external event for regular group */ + + adc_extcfg_set(priv, priv->extcfg); +#endif + + /* Enable ADC */ + + adc_enable(priv, true); + +#ifdef ADC_HAVE_JEXTCFG + /* Configure external event for injected group when ADC enabled */ + + adc_jextcfg_set(priv, priv->jextcfg); + +#if defined(HAVE_IP_ADC_V2) + /* For ADC IPv2 there is queue of context for injected conversion. + * JEXTCFG configuration is the second write to JSQR register which means + * configuration is stored on queue. + * We trigger single INJ conversion here to update context. + */ + + adc_inj_startconv(priv, true); +#endif +#endif + + /* Dump regs */ + + adc_dumpregs(priv); +} + +/**************************************************************************** + * Name: adc_reset + * + * Description: + * Reset the ADC device. Called early to initialize the hardware. + * This is called, before adc_setup() and on error conditions. + * + * Input Parameters: + * + * Returned Value: + * + ****************************************************************************/ + +static void adc_reset(struct adc_dev_s *dev) +{ + struct stm32_dev_s *priv = (struct stm32_dev_s *)dev->ad_priv; + irqstate_t flags; + + ainfo("intf: %d\n", priv->intf); + flags = enter_critical_section(); + + /* Do nothing if ADC instance is currently in use */ + + if (priv->initialized > 0) + { + goto out; + } + +#ifdef HAVE_HSI_CONTROL + /* The STM32L15XX family uses HSI as an independent clock-source + * for the ADC + */ + + adc_enable_hsi(true); +#endif + +#if defined(HAVE_IP_ADC_V2) + /* Turn off the ADC so we can write the RCC bits */ + + adc_enable(priv, false); +#endif + + /* Only if this is the first initialzied ADC instance in the ADC block */ + +#ifdef HAVE_ADC_CMN_DATA + if (nxmutex_lock(&priv->cmn->lock) < 0) + { + goto out; + } + + if (priv->cmn->refcount == 0) +#endif + { + /* Enable ADC reset state */ + + adc_rccreset(priv, true); + + /* Release ADC from reset state */ + + adc_rccreset(priv, false); + } + +#ifdef HAVE_ADC_CMN_DATA + nxmutex_unlock(&priv->cmn->lock); +#endif + +out: + leave_critical_section(flags); +} + +/**************************************************************************** + * Name: adc_reset_hsi_disable + * + * Description: + * Reset the ADC device with HSI and ADC shut down. Called early to + * initialize the hardware. This is called, before adc_setup() and on + * error conditions. In STM32L15XX case sometimes HSI must be shut + * down after the first initialization + * + * Input Parameters: + * + * Returned Value: + * + ****************************************************************************/ + +#ifdef HAVE_HSI_CONTROL +static void adc_reset_hsi_disable(struct adc_dev_s *dev) +{ + adc_reset(dev); + adc_shutdown(dev); +} +#endif + +/**************************************************************************** + * Name: adc_setup + * + * Description: + * Configure the ADC. This method is called the first time that the ADC + * device is opened. This will occur when the port is first opened. + * This setup includes configuring and attaching ADC interrupts. + * Interrupts are all disabled upon return. + * + * Input Parameters: + * + * Returned Value: + * + ****************************************************************************/ + +static int adc_setup(struct adc_dev_s *dev) +{ + struct stm32_dev_s *priv = (struct stm32_dev_s *)dev->ad_priv; + int ret = OK; + + /* Do nothing when the ADC device is already set up */ + + if (priv->initialized > 0) + { + priv->initialized += 1; + return OK; + } + + /* Make sure that the ADC device is in the powered up, reset state */ + + adc_reset(dev); + + /* Configure ADC device */ + + adc_configure(dev); + +#ifdef ADC_HAVE_TIMER + /* Configure timer */ + + if (priv->tbase != 0) + { + ret = adc_timinit(priv); + if (ret < 0) + { + aerr("ERROR: adc_timinit failed: %d\n", ret); + } + } +#endif + + /* As default conversion is started here. + * + * NOTE: for ADC IPv2 (J)ADSTART bit must be set to start ADC conversion + * even if hardware trigger is selected. + * This can be done here during the opening of the ADC device + * or later with ANIOC_TRIGGER ioctl call. + */ + +#ifndef CONFIG_STM32_ADC_NO_STARTUP_CONV + /* Start regular conversion */ + + adc_reg_startconv(priv, true); + +# ifdef ADC_HAVE_INJECTED + /* Start injected conversion */ + + adc_inj_startconv(priv, true); +# endif +#endif + +#ifdef HAVE_ADC_CMN_DATA + /* Increase instances counter */ + + ret = nxmutex_lock(&priv->cmn->lock); + if (ret < 0) + { + return ret; + } + + if (priv->cmn->refcount == 0) +#endif + { +#ifndef CONFIG_STM32_ADC_NOIRQ + /* Attach the ADC interrupt */ + + ret = irq_attach(priv->irq, priv->isr, NULL); + if (ret < 0) + { + ainfo("irq_attach failed: %d\n", ret); + return ret; + } + + /* Enable the ADC interrupt */ + + ainfo("Enable the ADC interrupt: irq=%d\n", priv->irq); + up_enable_irq(priv->irq); +#endif + } + +#ifdef HAVE_ADC_CMN_DATA + priv->cmn->refcount += 1; + nxmutex_unlock(&priv->cmn->lock); +#endif + + /* The ADC device is ready */ + + priv->initialized += 1; + + return ret; +} + +/**************************************************************************** + * Name: adc_shutdown + * + * Description: + * Disable the ADC. This method is called when the ADC device is closed. + * This method reverses the operation the setup method. + * + * Input Parameters: + * + * Returned Value: + * + ****************************************************************************/ + +static void adc_shutdown(struct adc_dev_s *dev) +{ + struct stm32_dev_s *priv = (struct stm32_dev_s *)dev->ad_priv; + + /* Decrement count only when ADC device is in use */ + + if (priv->initialized > 0) + { + priv->initialized -= 1; + } + + /* Shutdown the ADC device only when not in use */ + + if (priv->initialized > 0) + { + return; + } + + /* Disable ADC */ + + adc_enable(priv, false); + +#ifdef HAVE_HSI_CONTROL + adc_enable_hsi(false); +#endif + +#ifdef HAVE_ADC_CMN_DATA + if (nxmutex_lock(&priv->cmn->lock) < 0) + { + return; + } + + if (priv->cmn->refcount <= 1) +#endif + { +#ifndef CONFIG_STM32_ADC_NOIRQ + /* Disable ADC interrupts and detach the ADC interrupt handler */ + + up_disable_irq(priv->irq); + irq_detach(priv->irq); +#endif + + /* Disable and reset the ADC module. + * + * NOTE: The ADC block will be reset to its reset state only if all + * ADC block instances are closed. This means that the closed + * ADC may not be reset which in turn may affect low-power + * applications. (But ADC is turned off here, is not that + * enough?) + */ + + adc_rccreset(priv, true); + } + +#ifdef ADC_HAVE_TIMER + /* Disable timer */ + + if (priv->tbase != 0) + { + adc_timstart(priv, false); + } +#endif + +#ifdef HAVE_ADC_CMN_DATA + /* Decrease instances counter */ + + if (priv->cmn->refcount > 0) + { + priv->cmn->refcount -= 1; + } + + nxmutex_unlock(&priv->cmn->lock); +#endif +} + +/**************************************************************************** + * Name: adc_rxint + * + * Description: + * Call to enable or disable RX interrupts. + * + * Input Parameters: + * + * Returned Value: + * + ****************************************************************************/ + +static void adc_rxint(struct adc_dev_s *dev, bool enable) +{ + struct stm32_dev_s *priv = (struct stm32_dev_s *)dev->ad_priv; + uint32_t regval; + + ainfo("intf: %d enable: %d\n", priv->intf, enable ? 1 : 0); + + if (enable) + { + /* Enable the analog watchdog / overrun interrupts, and if no DMA, + * end-of-conversion ADC. + */ + + regval = ADC_IER_ALLINTS; +#ifdef ADC_HAVE_DMA + if (priv->hasdma) + { + regval &= ~(ADC_IER_EOC | ADC_IER_JEOC); + } +#endif + + adc_modifyreg(priv, STM32_ADC_IER_OFFSET, 0, regval); + } + else + { + /* Disable all ADC interrupts */ + + adc_modifyreg(priv, STM32_ADC_IER_OFFSET, ADC_IER_ALLINTS, 0); + } +} + +/**************************************************************************** + * Name: adc_enable_tvref_register + * + * Description: + * Enable/disable the temperature sensor and the VREFINT channel. + * + * Input Parameters: + * dev - pointer to device structure used by the driver + * enable - true: Temperature sensor and V REFINT channel enabled + * (ch 16 and 17) + * false: Temperature sensor and V REFINT channel disabled + * (ch 16 and 17) + * + * Returned Value: + * None. + * + ****************************************************************************/ + +#if defined(HAVE_IP_ADC_V1) +static void adc_ioc_enable_tvref_register(struct adc_dev_s *dev, + bool enable) +{ + struct stm32_dev_s *priv = (struct stm32_dev_s *)dev->ad_priv; + +#ifdef HAVE_BASIC_ADC +# if defined(CONFIG_STM32_ADC1) + /* TSVREF bit is only available in the STM32_ADC1_CR2 register. */ + + if (priv->intf == 1) + { + if (enable) + { + adc_modifyreg(priv, STM32_ADC_CR2_OFFSET, 0, ADC_CR2_TSVREFE); + } + else + { + adc_modifyreg(priv, STM32_ADC_CR2_OFFSET, ADC_CR2_TSVREFE, 0); + } + } + + ainfo("STM32_ADC_CR2 value: 0x%08" PRIx32 "\n", + adc_getreg(priv, STM32_ADC_CR2_OFFSET)); +# endif /* CONFIG_STM32_ADC1 */ +#else /* !HAVE_BASIC_ADC */ + if (enable) + { + adccmn_modifyreg(priv, STM32_ADC_CCR_OFFSET, 0, ADC_CCR_TSVREFE); + } + else + { + adccmn_modifyreg(priv, STM32_ADC_CCR_OFFSET, ADC_CCR_TSVREFE, 0); + } + + ainfo("STM32_ADC_CCR value: 0x%08" PRIx32 "\n", + adccmn_getreg(priv, STM32_ADC_CCR_OFFSET)); +#endif +} +#endif /* HAVE_IP_ADC_V1 */ + +/**************************************************************************** + * Name: adc_resolution_set + ****************************************************************************/ + +#ifdef HAVE_ADC_RESOLUTION +static int adc_resolution_set(struct adc_dev_s *dev, uint8_t res) +{ + struct stm32_dev_s *priv = (struct stm32_dev_s *)dev->ad_priv; + int ret = OK; + + /* Check input */ + + if (res > 3) + { + ret = -EINVAL; + goto errout; + } + + /* Modify appropriate register */ + +#if defined(HAVE_IP_ADC_V1) + adc_modifyreg(priv, STM32_ADC_CR1_OFFSET, ADC_CR1_RES_MASK, + res << ADC_CR1_RES_SHIFT); +#elif defined(HAVE_IP_ADC_V2) + adc_modifyreg(priv, STM32_ADC_CFGR1_OFFSET, ADC_CFGR1_RES_MASK, + res << ADC_CFGR1_RES_SHIFT); +#endif + +errout: + return ret; +} +#endif + +/**************************************************************************** + * Name: adc_extcfg_set + ****************************************************************************/ + +#ifdef ADC_HAVE_EXTCFG +static int adc_extcfg_set(struct stm32_dev_s *priv, uint32_t extcfg) +{ + uint32_t exten = 0; + uint32_t extsel = 0; + uint32_t setbits = 0; + uint32_t clrbits = 0; + + /* Get EXTEN and EXTSEL from input */ + + exten = extcfg & ADC_EXTREG_EXTEN_MASK; + extsel = extcfg & ADC_EXTREG_EXTSEL_MASK; + + /* EXTSEL selection: These bits select the external event used + * to trigger the start of conversion of a regular group. NOTE: + * + * - The position with of the EXTSEL field varies from one STM32 MCU + * to another. + * - The width of the EXTSEL field varies from one STM32 MCU to another. + */ + + if (exten > 0) + { + setbits = extsel | exten; + clrbits = ADC_EXTREG_EXTEN_MASK | ADC_EXTREG_EXTSEL_MASK; + + ainfo("Initializing extsel = 0x%08" PRIx32 "\n", extsel); + + /* Write register */ + + adc_modifyreg(priv, STM32_ADC_EXTREG_OFFSET, clrbits, setbits); + } + + return OK; +} +#endif + +/**************************************************************************** + * Name: adc_jextcfg_set + ****************************************************************************/ + +#ifdef ADC_HAVE_JEXTCFG +static int adc_jextcfg_set(struct stm32_dev_s *priv, uint32_t jextcfg) +{ + uint32_t jexten = 0; + uint32_t jextsel = 0; + uint32_t setbits = 0; + uint32_t clrbits = 0; + + /* Get JEXTEN and JEXTSEL from input */ + + jexten = jextcfg & ADC_JEXTREG_JEXTEN_MASK; + jextsel = jextcfg & ADC_JEXTREG_JEXTSEL_MASK; + + /* JEXTSEL selection: These bits select the external event used + * to trigger the start of conversion of a injected group. NOTE: + * + * - The position with of the JEXTSEL field varies from one STM32 MCU + * to another. + * - The width of the JEXTSEL field varies from one STM32 MCU to another. + */ + + if (jexten > 0) + { + setbits = jexten | jextsel; + clrbits = ADC_JEXTREG_JEXTEN_MASK | ADC_JEXTREG_JEXTSEL_MASK; + + ainfo("Initializing jextsel = 0x%08" PRIx32 "\n", jextsel); + + /* Write register */ + + adc_modifyreg(priv, STM32_ADC_JEXTREG_OFFSET, clrbits, setbits); + } + + return OK; +} +#endif + +/**************************************************************************** + * Name: adc_dumpregs + ****************************************************************************/ + +static void adc_dumpregs(struct stm32_dev_s *priv) +{ + UNUSED(priv); + +#if defined(HAVE_IP_ADC_V2) + ainfo("ISR: 0x%08" PRIx32 " IER: 0x%08" PRIx32 + " CR: 0x%08" PRIx32 " CFGR1: 0x%08" PRIx32 "\n", + adc_getreg(priv, STM32_ADC_ISR_OFFSET), + adc_getreg(priv, STM32_ADC_IER_OFFSET), + adc_getreg(priv, STM32_ADC_CR_OFFSET), + adc_getreg(priv, STM32_ADC_CFGR1_OFFSET)); +#else + ainfo("SR: 0x%08" PRIx32 " CR1: 0x%08" PRIx32 + " CR2: 0x%08" PRIx32 "\n", + adc_getreg(priv, STM32_ADC_SR_OFFSET), + adc_getreg(priv, STM32_ADC_CR1_OFFSET), + adc_getreg(priv, STM32_ADC_CR2_OFFSET)); +#endif + + ainfo("SQR1: 0x%08" PRIx32 " SQR2: 0x%08" PRIx32 + " SQR3: 0x%08" PRIx32 "\n", + adc_getreg(priv, STM32_ADC_SQR1_OFFSET), + adc_getreg(priv, STM32_ADC_SQR2_OFFSET), + adc_getreg(priv, STM32_ADC_SQR3_OFFSET)); + + ainfo("SMPR1: 0x%08" PRIx32 " SMPR2: 0x%08" PRIx32 "\n", + adc_getreg(priv, STM32_ADC_SMPR1_OFFSET), + adc_getreg(priv, STM32_ADC_SMPR2_OFFSET)); + +#if defined(STM32_ADC_SQR4_OFFSET) + ainfo("SQR4: 0x%08" PRIx32 "\n", + adc_getreg(priv, STM32_ADC_SQR4_OFFSET)); +#endif + +#if defined(STM32_ADC_SQR5_OFFSET) + ainfo("SQR5: 0x%08" PRIx32 "\n", + adc_getreg(priv, STM32_ADC_SQR5_OFFSET)); +#endif + +#ifdef ADC_HAVE_INJECTED + ainfo("JSQR: 0x%08" PRIx32 "\n", adc_getreg(priv, STM32_ADC_JSQR_OFFSET)); +#endif + +#if defined(HAVE_IP_ADC_V2) || (defined(HAVE_IP_ADC_V1) && !defined(HAVE_BASIC_ADC)) + ainfo("CCR: 0x%08" PRIx32 "\n", + adccmn_getreg(priv, STM32_ADC_CCR_OFFSET)); +#endif +} + +/**************************************************************************** + * Name: adc_enable_vbat_channel + * + * Description: + * Enable/disable the Vbat voltage measurement channel. + * + * Input Parameters: + * dev - pointer to device structure used by the driver + * enable - true: Vbat input channel enabled (ch 18) + * false: Vbat input channel disabled (ch 18) + * + * Returned Value: + * None. + * + ****************************************************************************/ + +#ifdef HAVE_ADC_VBAT +static void adc_enable_vbat_channel(struct adc_dev_s *dev, bool enable) +{ + struct stm32_dev_s *priv = (struct stm32_dev_s *)dev->ad_priv; + + if (enable) + { + adccmn_modifyreg(priv, STM32_ADC_CCR_OFFSET, 0, ADC_CCR_VBATEN); + } + else + { + adccmn_modifyreg(priv, STM32_ADC_CCR_OFFSET, ADC_CCR_VBATEN, 0); + } + + ainfo("STM32_ADC_CCR value: 0x%08" PRIx32 "\n", + adccmn_getreg(priv, STM32_ADC_CCR_OFFSET)); +} +#endif + +/**************************************************************************** + * Name: adc_ioc_change_sleep_between_opers + * + * Description: + * Changes PDI and PDD bits to save battery. + * + * Input Parameters: + * dev - pointer to device structure used by the driver + * cmd - command + * arg - arguments passed with command + * + * Returned Value: + * + ****************************************************************************/ + +#ifdef HAVE_ADC_POWERDOWN +static int adc_ioc_change_sleep_between_opers(struct adc_dev_s *dev, + int cmd, bool arg) +{ + struct stm32_dev_s *priv = (struct stm32_dev_s *)dev->ad_priv; + int ret = OK; + + adc_enable(priv, false); + + switch (cmd) + { + case IO_ENABLE_DISABLE_PDI: + adc_power_down_idle(priv, arg); + break; + + case IO_ENABLE_DISABLE_PDD: + adc_power_down_delay(priv, arg); + break; + + case IO_ENABLE_DISABLE_PDD_PDI: + adc_power_down_idle(priv, arg); + adc_power_down_delay(priv, arg); + break; + + default: + ainfo("unknown cmd: %d\n", cmd); + break; + } + + adc_enable(priv, true); + + return ret; +} +#endif + +/**************************************************************************** + * Name: adc_ioc_enable_awd_int + * + * Description: + * Turns ON/OFF ADC analog watchdog interrupt. + * + * Input Parameters: + * dev - pointer to device structure used by the driver + * arg - true: Turn ON interrupt + * false: Turn OFF interrupt + * + * Returned Value: + * + ****************************************************************************/ + +static void adc_ioc_enable_awd_int(struct stm32_dev_s *priv, bool enable) +{ + if (enable) + { + adc_modifyreg(priv, STM32_ADC_IER_OFFSET, 0, ADC_IER_AWD); + } + else + { + adc_modifyreg(priv, STM32_ADC_IER_OFFSET, ADC_IER_AWD, 0); + } +} + +/**************************************************************************** + * Name: adc_ioc_enable_eoc_int + * + * Description: + * Turns ON/OFF ADC EOC interrupt. + * + * Input Parameters: + * dev - pointer to device structure used by the driver + * arg - true: Turn ON interrupt + * false: Turn OFF interrupt + * + * Returned Value: + * + ****************************************************************************/ + +static void adc_ioc_enable_eoc_int(struct stm32_dev_s *priv, bool enable) +{ + if (enable) + { + adc_modifyreg(priv, STM32_ADC_IER_OFFSET, 0, ADC_IER_EOC); + } + else + { + adc_modifyreg(priv, STM32_ADC_IER_OFFSET, ADC_IER_EOC, 0); + } +} + +/**************************************************************************** + * Name: adc_ioc_enable_jeoc_int + * + * Description: + * Turns ON/OFF ADC injected channels interrupt. + * + * Input Parameters: + * dev - pointer to device structure used by the driver + * arg - true: Turn ON interrupt + * false: Turn OFF interrupt + * + * Returned Value: + * + ****************************************************************************/ + +static void adc_ioc_enable_jeoc_int(struct stm32_dev_s *priv, + bool enable) +{ + if (enable) + { + adc_modifyreg(priv, STM32_ADC_IER_OFFSET, 0, ADC_IER_JEOC); + } + else + { + adc_modifyreg(priv, STM32_ADC_IER_OFFSET, ADC_IER_JEOC, 0); + } +} + +/**************************************************************************** + * Name: adc_ioc_enable_ovr_int + * + * Description: + * Turns ON/OFF ADC overrun interrupt. + * + * Input Parameters: + * dev - pointer to device structure used by the driver + * arg - true: Turn ON interrupt + * false: Turn OFF interrupt + * + * Returned Value: + * + ****************************************************************************/ + +static void adc_ioc_enable_ovr_int(struct stm32_dev_s *priv, bool enable) +{ + if (enable) + { + adc_modifyreg(priv, STM32_ADC_IER_OFFSET, 0, ADC_IER_OVR); + } + else + { + adc_modifyreg(priv, STM32_ADC_IER_OFFSET, ADC_IER_OVR, 0); + } +} + +/**************************************************************************** + * Name: adc_ioc_change_ints + * + * Description: + * Turns ON/OFF ADC interrupts. + * + * Input Parameters: + * dev - pointer to device structure used by the driver + * cmd - command + * arg - arguments passed with command + * + * Returned Value: + * + ****************************************************************************/ + +static int adc_ioc_change_ints(struct adc_dev_s *dev, int cmd, bool arg) +{ + struct stm32_dev_s *priv = (struct stm32_dev_s *)dev->ad_priv; + int ret = OK; + + switch (cmd) + { + case IO_ENABLE_DISABLE_AWDIE: + adc_ioc_enable_awd_int(priv, arg); + break; + + case IO_ENABLE_DISABLE_EOCIE: + adc_ioc_enable_eoc_int(priv, arg); + break; + + case IO_ENABLE_DISABLE_JEOCIE: + adc_ioc_enable_jeoc_int(priv, arg); + break; + + case IO_ENABLE_DISABLE_OVRIE: + adc_ioc_enable_ovr_int(priv, arg); + break; + + case IO_ENABLE_DISABLE_ALL_INTS: + adc_ioc_enable_awd_int(priv, arg); + adc_ioc_enable_eoc_int(priv, arg); + adc_ioc_enable_jeoc_int(priv, arg); + adc_ioc_enable_ovr_int(priv, arg); + break; + + default: + ainfo("unknown cmd: %d\n", cmd); + break; + } + + return ret; +} + +/**************************************************************************** + * Name: adc_ioc_wait_rcnr_zeroed + * + * Description: + * For the STM3215XX-family the ADC_SR_RCNR bit must be zeroed, + * before next conversion. + * + * Input Parameters: + * dev - pointer to device structure used by the driver + * + * Returned Value: + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_STM32L15XX +static int adc_ioc_wait_rcnr_zeroed(struct stm32_dev_s *priv) +{ + int i; + + for (i = 0; i < 30000; i++) + { + if ((adc_getreg(priv, STM32_ADC_SR_OFFSET) & ADC_SR_RCNR) == 0) + { + return OK; + } + } + + return -ENODATA; +} +#endif + +/**************************************************************************** + * Name: adc_enable_hsi + * + * Description: + * Enable/Disable HSI clock + * + * Input Parameters: + * enable - true : HSI clock for ADC enabled + * false : HSI clock for ADC disabled + * + * Returned Value: + * + ****************************************************************************/ + +#ifdef HAVE_HSI_CONTROL +static void adc_enable_hsi(bool enable) +{ + if (enable) + { + /* Enable the HSI */ + + stm32_modifyreg32(STM32_RCC_CR, 0, RCC_CR_HSION); + while ((getreg32(STM32_RCC_CR) & RCC_CR_HSIRDY) == 0); + } + else + { + /* Disable the HSI */ + + stm32_modifyreg32(STM32_RCC_CR, RCC_CR_HSION, 0); + } +} +#endif + +/**************************************************************************** + * Name: adc_sqrbits + ****************************************************************************/ + +static uint32_t adc_sqrbits(struct stm32_dev_s *priv, int first, + int last, int offset) +{ + uint32_t bits = 0; + int i; + + for (i = first - 1; + i < priv->rnchannels && i < last; + i++, offset += ADC_SQ_OFFSET) + { + bits |= (uint32_t)priv->r_chanlist[i] << offset; + } + + return bits; +} + +/**************************************************************************** + * Name: adc_set_ch + * + * Description: + * Sets the ADC channel. + * + * Input Parameters: + * dev - pointer to device structure used by the driver + * ch - ADC channel number + 1. 0 reserved for all configured channels + * + * Returned Value: + * int - errno + * + ****************************************************************************/ + +static int adc_set_ch(struct adc_dev_s *dev, uint8_t ch) +{ + struct stm32_dev_s *priv = (struct stm32_dev_s *)dev->ad_priv; + uint32_t bits; + int i; + + if (ch == 0) + { + priv->current = 0; + priv->rnchannels = priv->cr_channels; + } + else + { + for (i = 0; i < priv->cr_channels && priv->r_chanlist[i] != ch - 1; + i++); + + if (i >= priv->cr_channels) + { + return -ENODEV; + } + + priv->current = i; + priv->rnchannels = 1; + } + +#ifdef STM32_ADC_SQR5_OFFSET + bits = adc_sqrbits(priv, ADC_SQR5_FIRST, ADC_SQR5_LAST, + ADC_SQR5_SQ_OFFSET); + adc_modifyreg(priv, STM32_ADC_SQR5_OFFSET, ~ADC_SQR5_RESERVED, bits); +#endif + +#ifdef STM32_ADC_SQR4_OFFSET + bits = adc_sqrbits(priv, ADC_SQR4_FIRST, ADC_SQR4_LAST, + ADC_SQR4_SQ_OFFSET); + adc_modifyreg(priv, STM32_ADC_SQR4_OFFSET, ~ADC_SQR4_RESERVED, bits); +#endif + + bits = adc_sqrbits(priv, ADC_SQR3_FIRST, ADC_SQR3_LAST, + ADC_SQR3_SQ_OFFSET); + adc_modifyreg(priv, STM32_ADC_SQR3_OFFSET, ~ADC_SQR3_RESERVED, bits); + + bits = adc_sqrbits(priv, ADC_SQR2_FIRST, ADC_SQR2_LAST, + ADC_SQR2_SQ_OFFSET); + adc_modifyreg(priv, STM32_ADC_SQR2_OFFSET, ~ADC_SQR2_RESERVED, bits); + + bits = ((uint32_t)priv->rnchannels - 1) << ADC_SQR1_L_SHIFT; + bits |= adc_sqrbits(priv, ADC_SQR1_FIRST, + ADC_SQR1_LAST, ADC_SQR1_SQ_OFFSET); + adc_modifyreg(priv, STM32_ADC_SQR1_OFFSET, ~ADC_SQR1_RESERVED, bits); + + return OK; +} + +#ifdef ADC_HAVE_INJECTED + +/**************************************************************************** + * Name: adc_inj_set_ch + ****************************************************************************/ + +static int adc_inj_set_ch(struct adc_dev_s *dev, uint8_t ch) +{ + struct stm32_dev_s *priv = (struct stm32_dev_s *)dev->ad_priv; + uint32_t clrbits; + uint32_t setbits; + int i; + + /* Configure injected sequence length */ + + setbits = ADC_JSQR_JL(priv->cj_channels); + clrbits = ADC_JEXTREG_JEXTSEL_MASK | ADC_JSQR_JL_MASK; + + /* Configure injected channels */ + + for (i = 0 ; i < priv->cj_channels; i += 1) + { +#if defined(HAVE_IP_ADC_V1) + /* Injected channels sequence for for ADC IPv1: + * + * 1 2 3 4 + * IL=1: JSQR4, + * IL=2: JSQR3, JSQR4 + * IL=3: JSQR2, JSQR3, JSQR4 + * IL=4: JSQR1, JSQR2, JSQR3, JSQR4 + */ + + setbits |= (priv->j_chanlist[priv->cj_channels - 1 - i] << + (ADC_JSQR_JSQ4_SHIFT - ADC_JSQR_JSQ_SHIFT * i)); +#else + setbits |= priv->j_chanlist[i] << (ADC_JSQR_JSQ1_SHIFT + + ADC_JSQR_JSQ_SHIFT * i); +#endif + } + + /* Write register */ + + adc_modifyreg(priv, STM32_ADC_JSQR_OFFSET, clrbits, setbits); + + return OK; +} +#endif + +/**************************************************************************** + * Name: adc_ioctl + * + * Description: + * All ioctl calls will be routed through this method. + * + * Input Parameters: + * dev - pointer to device structure used by the driver + * cmd - command + * arg - arguments passed with command + * + * Returned Value: + * + ****************************************************************************/ + +static int adc_ioctl(struct adc_dev_s *dev, int cmd, unsigned long arg) +{ + struct stm32_dev_s *priv = (struct stm32_dev_s *)dev->ad_priv; + int ret = OK; + + switch (cmd) + { + case ANIOC_TRIGGER: + { + /* Start regular conversion if regular channels configured */ + + if (priv->anioc_trg & ANIOC_TRIGGER_REGULAR) + { + if (priv->cr_channels > 0) + { + adc_reg_startconv(priv, true); + } + } + +#ifdef ADC_HAVE_INJECTED + /* Start injected conversion if injected channels configured */ + + if (priv->anioc_trg & ANIOC_TRIGGER_INJECTED) + { + if (priv->cj_channels > 0) + { + adc_inj_startconv(priv, true); + } + } +#endif + + break; + } + + case ANIOC_GET_NCHANNELS: + { + /* Return the number of configured channels */ + + ret = priv->rnchannels; + } + break; + + case IO_TRIGGER_REG: + { + /* Start regular conversion if regular channels configured */ + + if (priv->cr_channels > 0) + { + adc_reg_startconv(priv, true); + } + + break; + } + +#ifdef ADC_HAVE_INJECTED + case IO_TRIGGER_INJ: + { + /* Start injected conversion if injected channels configured */ + + if (priv->cj_channels > 0) + { + adc_inj_startconv(priv, true); + } + + break; + } +#endif + + case IO_ENABLE_DISABLE_AWDIE: + case IO_ENABLE_DISABLE_EOCIE: + case IO_ENABLE_DISABLE_JEOCIE: + case IO_ENABLE_DISABLE_OVRIE: + case IO_ENABLE_DISABLE_ALL_INTS: + { + adc_ioc_change_ints(dev, cmd, *(bool *)arg); + break; + } + +#if defined(HAVE_IP_ADC_V1) + case IO_ENABLE_TEMPER_VOLT_CH: + { + adc_ioc_enable_tvref_register(dev, *(bool *)arg); + break; + } +#endif + +#ifdef HAVE_ADC_VBAT + case IO_ENABLE_DISABLE_VBAT_CH: + { + adc_enable_vbat_channel(dev, *(bool *)arg); + break; + } +#endif + +#ifdef HAVE_ADC_POWERDOWN + case IO_ENABLE_DISABLE_PDI: + case IO_ENABLE_DISABLE_PDD: + case IO_ENABLE_DISABLE_PDD_PDI: + { + adc_ioc_change_sleep_between_opers(dev, cmd, *(bool *)arg); + break; + } +#endif + + case IO_STOP_ADC: + { + adc_enable(priv, false); +#ifdef HAVE_HSI_CONTROL + adc_enable_hsi(false); +#endif + break; + } + + case IO_START_ADC: + { +#ifdef HAVE_HSI_CONTROL + adc_enable_hsi(true); +#endif + adc_enable(priv, true); + break; + } + + case IO_START_CONV: + { + uint8_t ch = ((uint8_t)arg); + +#ifdef CONFIG_STM32_STM32L15XX + ret = adc_ioc_wait_rcnr_zeroed(priv); + if (ret < 0) + { + return ret; + } +#endif + + ret = adc_set_ch(dev, ch); + if (ret < 0) + { + return ret; + } + +#ifdef CONFIG_ADC + if (ch) + { + /* Clear fifo if upper-half driver enabled */ + + dev->ad_recv.af_head = 0; + dev->ad_recv.af_tail = 0; + } +#endif + + adc_reg_startconv(priv, true); + break; + } + + default: + { + aerr("ERROR: Unknown cmd: %d\n", cmd); + ret = -ENOTTY; + break; + } + } + + return ret; +} + +#ifndef CONFIG_STM32_ADC_NOIRQ + +/**************************************************************************** + * Name: adc_interrupt + * + * Description: + * Common ADC interrupt handler. + * + * Input Parameters: + * + * Returned Value: + * + ****************************************************************************/ + +static int adc_interrupt(struct adc_dev_s *dev) +{ + struct stm32_dev_s *priv = (struct stm32_dev_s *)dev->ad_priv; + uint32_t regval; + uint32_t pending; + int32_t data; + + regval = adc_getreg(priv, STM32_ADC_ISR_OFFSET); + pending = regval & ADC_ISR_ALLINTS; + if (pending == 0) + { + return OK; + } + + /* Identifies the interruption AWD, OVR or EOC */ + + if ((regval & ADC_ISR_AWD) != 0) + { + awarn("WARNING: Analog Watchdog, Value converted out of range!\n"); + } + + if ((regval & ADC_ISR_OVR) != 0) + { + awarn("WARNING: Overrun has occurred!\n"); + } + + /* EOC: End of conversion */ + + if ((regval & ADC_ISR_EOC) != 0) + { + /* Read the converted value and clear EOC bit + * (It is cleared by reading the ADC_DR) + */ + + data = adc_getreg(priv, STM32_ADC_DR_OFFSET) & ADC_DR_RDATA_MASK; + + /* Verify that the upper-half driver has bound its callback functions */ + + if (priv->cb != NULL) + { + /* Give the ADC data to the ADC driver. The ADC receive() method + * accepts 3 parameters: + * + * 1) The first is the ADC device instance for this ADC block. + * 2) The second is the channel number for the data, and + * 3) The third is the converted data for the channel. + */ + + DEBUGASSERT(priv->cb->au_receive != NULL); + priv->cb->au_receive(dev, priv->r_chanlist[priv->current], data); + } + + /* Set the channel number of the next channel that will complete + * conversion. + */ + + priv->current++; + + if (priv->current >= priv->rnchannels) + { + /* Restart the conversion sequence from the beginning */ + + priv->current = 0; + } + } + + /* Clear pending interrupts */ + + adc_putreg(priv, STM32_ADC_ISR_OFFSET, pending); + + return OK; +} + +/**************************************************************************** + * Name: adc1_interrupt + * + * Description: + * ADC interrupt handler for the STM32 L15XX family. + * + * Input Parameters: + * irq - The IRQ number that generated the interrupt. + * context - Architecture specific register save information. + * + * Returned Value: + * + ****************************************************************************/ + +#if defined(STM32_IRQ_ADC1) +static int adc1_interrupt(int irq, void *context, void *arg) +{ + adc_interrupt(&g_adcdev1); + + return OK; +} +#endif + +/**************************************************************************** + * Name: adc12_interrupt + * + * Description: + * ADC1/2 interrupt handler for the STM32 F1/F3 families. + * + * Input Parameters: + * + * Returned Value: + * + ****************************************************************************/ + +#if defined(STM32_IRQ_ADC12) && \ + (defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2)) +static int adc12_interrupt(int irq, void *context, void *arg) +{ +#ifdef CONFIG_STM32_ADC1 + adc_interrupt(&g_adcdev1); +#endif + +#ifdef CONFIG_STM32_ADC2 + adc_interrupt(&g_adcdev2); +#endif + + return OK; +} +#endif + +/**************************************************************************** + * Name: adc3_interrupt + * + * Description: + * ADC3 interrupt handler for the STM32 F1 family. + * + * Input Parameters: + * + * Returned Value: + * + ****************************************************************************/ + +#if defined(STM32_IRQ_ADC3) && defined(CONFIG_STM32_ADC3) +static int adc3_interrupt(int irq, void *context, void *arg) +{ + adc_interrupt(&g_adcdev3); + + return OK; +} +#endif + +/**************************************************************************** + * Name: adc4_interrupt + * + * Description: + * ADC4 interrupt handler for the STM32 F3 family. + * + * Input Parameters: + * + * Returned Value: + * + ****************************************************************************/ + +#if defined(STM32_IRQ_ADC4) && defined(CONFIG_STM32_ADC4) +static int adc4_interrupt(int irq, void *context, void *arg) +{ + adc_interrupt(&g_adcdev4); + + return OK; +} +#endif + +/**************************************************************************** + * Name: adc123_interrupt + * + * Description: + * ADC1/2/3 interrupt handler for the STM32 F2/F4 families. + * + * Input Parameters: + * + * Returned Value: + * + ****************************************************************************/ + +#if defined(STM32_IRQ_ADC) +static int adc123_interrupt(int irq, void *context, void *arg) +{ +#ifdef CONFIG_STM32_ADC1 + adc_interrupt(&g_adcdev1); +#endif + +#ifdef CONFIG_STM32_ADC2 + adc_interrupt(&g_adcdev2); +#endif + +#ifdef CONFIG_STM32_ADC3 + adc_interrupt(&g_adcdev3); +#endif + + return OK; +} +#endif +#endif /* CONFIG_STM32_ADC_NOIRQ */ + +#ifdef CONFIG_STM32_ADC_LL_OPS + +/**************************************************************************** + * Name: adc_llops_setup + ****************************************************************************/ + +static int adc_llops_setup(struct stm32_adc_dev_s *dev) +{ + struct stm32_dev_s *priv = (struct stm32_dev_s *)dev; + + return adc_setup(priv->dev); +} + +/**************************************************************************** + * Name: adc_llops_shutdown + ****************************************************************************/ + +static void adc_llops_shutdown(struct stm32_adc_dev_s *dev) +{ + struct stm32_dev_s *priv = (struct stm32_dev_s *)dev; + + adc_shutdown(priv->dev); +} + +/**************************************************************************** + * Name: adc_intack + ****************************************************************************/ + +static void adc_intack(struct stm32_adc_dev_s *dev, uint32_t source) +{ + struct stm32_dev_s *priv = (struct stm32_dev_s *)dev; + + /* Clear pending interrupts */ + +#ifdef HAVE_IP_ADC_V2 + /* Cleared by writing 1 to it */ + + adc_putreg(priv, STM32_ADC_ISR_OFFSET, (source & ADC_ISR_ALLINTS)); +#else + /* Cleared by writing 0 to it */ + + adc_modifyreg(priv, STM32_ADC_ISR_OFFSET, (source & ADC_ISR_ALLINTS), 0); +#endif +} + +/**************************************************************************** + * Name: adc_inten + ****************************************************************************/ + +static void adc_inten(struct stm32_adc_dev_s *dev, uint32_t source) +{ + struct stm32_dev_s *priv = (struct stm32_dev_s *)dev; + + /* Enable interrupts */ + + adc_modifyreg(priv, STM32_ADC_IER_OFFSET, 0, (source & ADC_IER_ALLINTS)); +} + +/**************************************************************************** + * Name: adc_intdis + ****************************************************************************/ + +static void adc_intdis(struct stm32_adc_dev_s *dev, uint32_t source) +{ + struct stm32_dev_s *priv = (struct stm32_dev_s *)dev; + + /* Disable interrupts */ + + adc_modifyreg(priv, STM32_ADC_IER_OFFSET, (source & ADC_IER_ALLINTS), 0); +} + +/**************************************************************************** + * Name: adc_ackget + ****************************************************************************/ + +static uint32_t adc_intget(struct stm32_adc_dev_s *dev) +{ + struct stm32_dev_s *priv = (struct stm32_dev_s *)dev; + uint32_t regval; + uint32_t pending; + + regval = adc_getreg(priv, STM32_ADC_ISR_OFFSET); + pending = regval & ADC_ISR_ALLINTS; + + return pending; +} + +/**************************************************************************** + * Name: adc_regget + ****************************************************************************/ + +static uint32_t adc_regget(struct stm32_adc_dev_s *dev) +{ + struct stm32_dev_s *priv = (struct stm32_dev_s *)dev; + + return adc_getreg(priv, STM32_ADC_DR_OFFSET) & ADC_DR_RDATA_MASK; +} + +/**************************************************************************** + * Name: adc_llops_reg_startconv + ****************************************************************************/ + +static void adc_llops_reg_startconv(struct stm32_adc_dev_s *dev, + bool enable) +{ + struct stm32_dev_s *priv = (struct stm32_dev_s *)dev; + + adc_reg_startconv(priv, enable); +} + +/**************************************************************************** + * Name: adc_offset_set + ****************************************************************************/ + +#ifdef HAVE_IP_ADC_V2 +static int adc_offset_set(struct stm32_adc_dev_s *dev, uint8_t ch, + uint8_t i, uint16_t offset) +{ + struct stm32_dev_s *priv = (struct stm32_dev_s *)dev; + uint32_t regval = 0; + uint32_t reg = 0; + int ret = OK; + + if (i >= 4) + { + /* There are only four offset registers. */ + + ret = -E2BIG; + goto errout; + } + + reg = STM32_ADC_OFR1_OFFSET + i * 4; + + regval = ADC_OFR_OFFSETY_EN; + adc_putreg(priv, reg, regval); + + regval |= ADC_OFR_OFFSETY_CH(ch) | ADC_OFR_OFFSETY(offset); + adc_putreg(priv, reg, regval); + +errout: + return ret; +} +#else /* HAVE_IP_ADC_V1 */ +static int adc_offset_set(struct stm32_adc_dev_s *dev, uint8_t ch, + uint8_t i, uint16_t offset) +{ + struct stm32_dev_s *priv = (struct stm32_dev_s *)dev; + uint32_t reg = 0; + int ret = OK; + + /* WARNING: Offset only for injected channels! */ + + UNUSED(ch); + + if (i >= 4) + { + /* There are only four offset registers. */ + + ret = -E2BIG; + goto errout; + } + + reg = STM32_ADC_JOFR1_OFFSET + i * 4; + + adc_putreg(priv, reg, offset); + +errout: + return ret; +} +#endif + +/**************************************************************************** + * Name: adc_llops_extcfg_set + ****************************************************************************/ + +#ifdef ADC_HAVE_EXTCFG +static void adc_llops_extcfg_set(struct stm32_adc_dev_s *dev, + uint32_t extcfg) +{ + struct stm32_dev_s *priv = (struct stm32_dev_s *)dev; + + adc_extcfg_set(priv, extcfg); +} +#endif + +/**************************************************************************** + * Name: adc_llops_jextcfg_set + ****************************************************************************/ + +#ifdef ADC_HAVE_JEXTCFG +static void adc_llops_jextcfg_set(struct stm32_adc_dev_s *dev, + uint32_t jextcfg) +{ + struct stm32_dev_s *priv = (struct stm32_dev_s *)dev; + + adc_jextcfg_set(priv, jextcfg); +} +#endif + +/**************************************************************************** + * Name: adc_regbufregister + ****************************************************************************/ + +#ifdef ADC_HAVE_DMA +static int adc_regbufregister(struct stm32_adc_dev_s *dev, + uint16_t *buffer, uint8_t len) +{ + struct stm32_dev_s *priv = (struct stm32_dev_s *)dev; + + stm32_dmasetup(priv->dma, + priv->base + STM32_ADC_DR_OFFSET, + (uint32_t)buffer, + len, + ADC_DMA_CONTROL_WORD); + + /* No DMA callback */ + + stm32_dmastart(priv->dma, NULL, dev, false); + + return OK; +} +#endif /* ADC_HAVE_DMA */ + +/**************************************************************************** + * Name: adc_injget + ****************************************************************************/ + +#ifdef ADC_HAVE_INJECTED +static uint32_t adc_injget(struct stm32_adc_dev_s *dev, uint8_t chan) +{ + struct stm32_dev_s *priv = (struct stm32_dev_s *)dev; + uint32_t regval = 0; + + if (chan > (priv->cj_channels - 1)) + { + /* REVISIT: return valute with MSB set to indicate error ? */ + + goto errout; + } + + regval = adc_getreg(priv, STM32_ADC_JDR1_OFFSET + 4 * (chan)) & + ADC_JDR_JDATA_MASK; + +errout: + return regval; +} + +/**************************************************************************** + * Name: adc_llops_inj_startconv + ****************************************************************************/ + +static void adc_llops_inj_startconv(struct stm32_adc_dev_s *dev, + bool enable) +{ + struct stm32_dev_s *priv = (struct stm32_dev_s *)dev; + + adc_inj_startconv(priv, enable); +} + +#endif /* ADC_HAVE_INJECTED */ + +/**************************************************************************** + * Name: adc_sampletime_write + * + * Description: + * Writes previously defined values into ADC_SMPRx registers. + * + * Input Parameters: + * + * Returned Value: + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_ADC_CHANGE_SAMPLETIME +static void adc_sampletime_write(struct stm32_adc_dev_s *dev) +{ + struct stm32_dev_s *priv = (struct stm32_dev_s *)dev; + uint32_t value = 0; + uint8_t i; + uint8_t shift; + + /* Sampling time individually for each channel. + * It's different for families. + */ + + for (i = 0, shift = 0; i < priv->adc_channels; i++) + { + value |= priv->sample_rate[i] << (shift * 3); + switch (i) + { +#if defined(STM32_ADC_SMPR0_OFFSET) && defined(STM32_ADC_SMPR3_OFFSET) + case 9: + { + adc_putreg(priv, STM32_ADC_SMPR3_OFFSET, value); + shift = 0; + value = 0; + break; + } + + case 19: + { + adc_putreg(priv, STM32_ADC_SMPR2_OFFSET, value); + shift = 0; + value = 0; + break; + } + + case 29: + { + adc_putreg(priv, STM32_ADC_SMPR1_OFFSET, value); + shift = 0; + value = 0; + break; + } + + case (ADC_CHANNELS_NUMBER - 1): + { + adc_putreg(priv, STM32_ADC_SMPR0_OFFSET, value); + shift = 0; + value = 0; + break; + } + +#elif defined(STM32_ADC_SMPR1_OFFSET) && defined(STM32_ADC_SMPR2_OFFSET) + case (ADC_CHANNELS_NUMBER - 1): + { + adc_putreg(priv, STM32_ADC_SMPR2_OFFSET, value); + shift = 0; + value = 0; + break; + } + + case 9: + { + adc_putreg(priv, STM32_ADC_SMPR1_OFFSET, value); + shift = 0; + value = 0; + break; + } +#else +# error "Not supported SMPRx configuration" +#endif + + default: + { + shift++; + break; + } + } + } +} + +/**************************************************************************** + * Name: adc_sampletime_set + * + * Description: + * Changes sample times for specified channels. This method + * doesn't make any register writing. So, it's only stores the information. + * Values provided by user will be written in registers only on the next + * ADC peripheral start, as it was told to do in manual. However, before + * very first start, user can call this method and override default values + * either for every channels or for only some predefined by user channel(s) + * + * Input Parameters: + * dev - pointer to the adc device structure + * time_samples - pointe to the adc sample time configuration data + * + * Returned Value: + * None + * + ****************************************************************************/ + +void adc_sampletime_set(struct stm32_adc_dev_s *dev, + struct adc_sample_time_s *time_samples) +{ + struct stm32_dev_s *priv = (struct stm32_dev_s *)dev; + uint8_t ch_index; + uint8_t i; + + /* Check if user wants to assign the same value for all channels + * or just wants to change sample time values for certain channels + */ + + if (time_samples->all_same) + { + memset(priv->sample_rate, time_samples->all_ch_sample_time, + ADC_CHANNELS_NUMBER); + } + else + { + for (i = 0; i < time_samples->channels_nbr; i++) + { + ch_index = time_samples->channel[i].channel; + if (ch_index >= ADC_CHANNELS_NUMBER) + { + break; + } + + priv->sample_rate[ch_index] = time_samples->channel[i].sample_time; + } + } +} +#endif /* CONFIG_STM32_ADC_CHANGE_SAMPLETIME */ + +/**************************************************************************** + * Name: adc_llops_dumpregs + ****************************************************************************/ + +static void adc_llops_dumpregs(struct stm32_adc_dev_s *dev) +{ + struct stm32_dev_s *priv = (struct stm32_dev_s *)dev; + + adc_dumpregs(priv); +} + +/**************************************************************************** + * Name: adc_llops_multicfg + * + * IMPORTANT: this interface is allowed only when the ADCs are disabled! + * + ****************************************************************************/ + +static int adc_llops_multicfg(struct stm32_adc_dev_s *dev, uint8_t mode) +#if defined(HAVE_IP_ADC_V2) +{ + struct stm32_dev_s *priv = (struct stm32_dev_s *)dev; + int ret = OK; + uint32_t setbits = 0; + uint32_t clrbits = 0; + + switch (mode) + { + case ADC_MULTIMODE_INDEP: + setbits = ADC_CCR_DUAL_IND; + break; + + case ADC_MULTIMODE_RSISM2: + setbits = ADC_CCR_DUAL_SIMALT; + break; + + case ADC_MULTIMODE_RSATM2: + setbits = ADC_CCR_DUAL_SIMALT; + break; + + case ADC_MULTIMODE_IMIS2: + setbits = ADC_CCR_DUAL_INTINJ; + break; + + case ADC_MULTIMODE_ISM2: + setbits = ADC_CCR_DUAL_INJECTED; + break; + + case ADC_MULTIMODE_RSM2: + setbits = ADC_CCR_DUAL_SIM; + break; + + case ADC_MULTIMODE_IM2: + setbits = ADC_CCR_DUAL_INTERLEAVE; + break; + + case ADC_MULTIMODE_ATM2: + setbits = ADC_CCR_DUAL_ALT; + break; + + default: + ret = -EINVAL; + goto errout; + } + + clrbits = ADC_CCR_DUAL_MASK; + adccmn_modifyreg(priv, STM32_ADC_CCR_OFFSET, clrbits, setbits); + +errout: + return ret; +} +#elif defined(HAVE_IP_ADC_V1) && !defined(HAVE_BASIC_ADC) +{ + struct stm32_dev_s *priv = (struct stm32_dev_s *)dev; + int ret = OK; + uint32_t setbits = 0; + uint32_t clrbits = 0; + + switch (mode) + { + case ADC_MULTIMODE_INDEP: + setbits = ADC_CCR_MULTI_NONE; + break; + + case ADC_MULTIMODE_RSISM2: + setbits = ADC_CCR_MULTI_RSISM2; + break; + + case ADC_MULTIMODE_RSATM2: + setbits = ADC_CCR_MULTI_RSATM2; + break; + + case ADC_MULTIMODE_ISM2: + setbits = ADC_CCR_MULTI_ISM2; + break; + + case ADC_MULTIMODE_RSM2: + setbits = ADC_CCR_MULTI_ISM2; + break; + + case ADC_MULTIMODE_IM2: + setbits = ADC_CCR_MULTI_IM2; + break; + + case ADC_MULTIMODE_ATM2: + setbits = ADC_CCR_MULTI_ATM2; + break; + + case ADC_MULTIMODE_RSISM3: + setbits = ADC_CCR_MULTI_RSISM3; + break; + + case ADC_MULTIMODE_RSATM3: + setbits = ADC_CCR_MULTI_RSATM3; + break; + + case ADC_MULTIMODE_ISM3: + setbits = ADC_CCR_MULTI_ISM3; + break; + + case ADC_MULTIMODE_RSM3: + setbits = ADC_CCR_MULTI_ISM3; + break; + + case ADC_MULTIMODE_IM3: + setbits = ADC_CCR_MULTI_IM3; + break; + + case ADC_MULTIMODE_ATM3: + setbits = ADC_CCR_MULTI_ATM3; + break; + + case ADC_MULTIMODE_IMIS2: + case ADC_MULTIMODE_IMIS3: + default: + ret = -EINVAL; + goto errout; + } + + clrbits = ADC_CCR_MULTI_MASK; + adccmn_modifyreg(priv, STM32_ADC_CCR_OFFSET, clrbits, setbits); + +errout: + return ret; +} +#else /* ADV IPv1 BASIC */ +{ + if (mode != ADC_MULTIMODE_INDEP) + { + return -EINVAL; + } + + return OK; +} +#endif + +/**************************************************************************** + * Name: adc_llops_enable + ****************************************************************************/ + +static void adc_llops_enable(struct stm32_adc_dev_s *dev, bool enable) +{ + struct stm32_dev_s *priv = (struct stm32_dev_s *)dev; + + adc_enable(priv, enable); +} + +#endif /* CONFIG_STM32_ADC_LL_OPS */ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_adcinitialize + * + * Description: + * Initialize the ADC. + * + * The logic allow initialize ADC regular and injected channels. + * + * The number of injected channels for given ADC is selected from Kconfig + * with CONFIG_STM32_ADCx_INJECTED_CHAN definitions + * + * The number of regular channels is obtained from the equation: + * + * cr_channels = channels - cj_channels + * + * where: + * cr_channels - regular channels + * cj_channels - injected channels + * channels - this function parameter + * + * The chanlist array store both regular channels and injected channels + * configuration so that regular channels are the first in order: + * + * # regular channels start from here + * chanlist[0] -> ADC_SQRx_SQ1 + * chanlist[1] -> ADC_SQRx_SQ2 + * ... + * # injected channels start from here + * chanlist[channels - (y - 1)] -> ADC_JSQR_JSQ1 + * ... + * chanlist[channels] -> ADC_JSQR_ISQy + * + * where: + * y = CONFIG_STM32_ADCx_INJECTED_CHAN, and y > 0 + * + * If CONFIG_STM32_ADCx_INJECTED_CHAN = 0, then all channels from chanlist + * are regular channels. + * + * Input Parameters: + * intf - Could be {1,2,3,4} for ADC1, ADC2, ADC3 or ADC4 + * chanlist - The list of channels (regular + injected) + * channels - Number of channels (regular + injected) + * + * Returned Value: + * Valid ADC device structure reference on success; a NULL on failure + * + ****************************************************************************/ + +struct adc_dev_s *stm32_adcinitialize(int intf, const uint8_t *chanlist, + int channels) +{ + struct adc_dev_s *dev; + struct stm32_dev_s *priv; + uint8_t cr_channels = 0; + uint8_t cj_channels = 0; +#ifdef ADC_HAVE_INJECTED + uint8_t *j_chanlist = NULL; +#endif + + switch (intf) + { +#ifdef CONFIG_STM32_ADC1 + case 1: + { + ainfo("ADC1 selected\n"); + dev = &g_adcdev1; + cj_channels = CONFIG_STM32_ADC1_INJECTED_CHAN; + cr_channels = channels - cj_channels; +# ifdef ADC_HAVE_INJECTED + if (cj_channels > 0) + { + j_chanlist = (uint8_t *)chanlist + cr_channels; + } +# endif + break; + } + +#endif /* CONFIG_STM32_ADC1 */ +#ifdef CONFIG_STM32_ADC2 + case 2: + { + ainfo("ADC2 selected\n"); + dev = &g_adcdev2; + cj_channels = CONFIG_STM32_ADC2_INJECTED_CHAN; + cr_channels = channels - cj_channels; +# ifdef ADC_HAVE_INJECTED + if (cj_channels > 0) + { + j_chanlist = (uint8_t *)chanlist + cr_channels; + } +# endif + break; + } + +#endif /* CONFIG_STM32_ADC2 */ +#ifdef CONFIG_STM32_ADC3 + case 3: + { + ainfo("ADC3 selected\n"); + dev = &g_adcdev3; + cj_channels = CONFIG_STM32_ADC3_INJECTED_CHAN; + cr_channels = channels - cj_channels; +# ifdef ADC_HAVE_INJECTED + if (cj_channels > 0) + { + j_chanlist = (uint8_t *)chanlist + cr_channels; + } +# endif + break; + } + +#endif /* CONFIG_STM32_ADC3 */ +#ifdef CONFIG_STM32_ADC4 + case 4: + { + ainfo("ADC4 selected\n"); + dev = &g_adcdev4; + cj_channels = CONFIG_STM32_ADC4_INJECTED_CHAN; + cr_channels = channels - cj_channels; +# ifdef ADC_HAVE_INJECTED + if (cj_channels > 0) + { + j_chanlist = (uint8_t *)chanlist + cr_channels; + } +# endif + break; + } + +#endif /* CONFIG_STM32_ADC4 */ + default: + { + aerr("ERROR: No ADC interface defined\n"); + return NULL; + } + } + + /* Configure the selected ADC */ + + priv = (struct stm32_dev_s *)dev->ad_priv; + + /* Configure regular channels */ + + DEBUGASSERT(cr_channels <= CONFIG_STM32_ADC_MAX_SAMPLES); + if (cr_channels > CONFIG_STM32_ADC_MAX_SAMPLES) + { + cr_channels = CONFIG_STM32_ADC_MAX_SAMPLES; + } + + priv->cr_channels = cr_channels; + memcpy(priv->r_chanlist, chanlist, cr_channels); + +#ifdef ADC_HAVE_INJECTED + /* Configure injected channels */ + + DEBUGASSERT(cj_channels <= ADC_INJ_MAX_SAMPLES); + if (cj_channels > ADC_INJ_MAX_SAMPLES) + { + cj_channels = ADC_INJ_MAX_SAMPLES; + } + + priv->cj_channels = cj_channels; + memcpy(priv->j_chanlist, j_chanlist, cj_channels); +#endif + +#ifdef CONFIG_STM32_ADC_CHANGE_SAMPLETIME + /* Assign default values for the sample time table */ + + memset(priv->sample_rate, ADC_SMPR_DEFAULT, ADC_CHANNELS_NUMBER); + priv->adc_channels = ADC_CHANNELS_NUMBER; +#endif + +#ifdef CONFIG_STM32_ADC_LL_OPS + /* Store reference to the upper-half ADC device */ + + priv->dev = dev; +#endif + +#ifdef ADC_HAVE_INJECTED + ainfo("intf: %d cr_channels: %d, cj_channels: %d\n", + intf, priv->cr_channels, priv->cj_channels); +#else + ainfo("intf: %d cr_channels: %d\n", intf, priv->cr_channels); +#endif + + return dev; +} + +#endif /* CONFIG_STM32_ADC */ diff --git a/arch/arm/src/common/stm32/stm32_adc_m3m4_v1v2.h b/arch/arm/src/common/stm32/stm32_adc_m3m4_v1v2.h new file mode 100644 index 0000000000000..b6317b5e32d5c --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_adc_m3m4_v1v2.h @@ -0,0 +1,2345 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_adc_m3m4_v1v2.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_ADC_V1V2_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_ADC_V1V2_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "chip.h" + +#include "hardware/stm32_adc.h" + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Generalized definitions for ADC *****************************************/ + +#if defined(HAVE_IP_ADC_V1) +# define STM32_ADC_DMAREG_OFFSET STM32_ADC_CR2_OFFSET +# define ADC_DMAREG_DMA ADC_CR2_DMA +# define STM32_ADC_EXTREG_OFFSET STM32_ADC_CR2_OFFSET +# define ADC_EXTREG_EXTSEL_MASK ADC_CR2_EXTSEL_MASK +# define ADC_EXTREG_EXTSEL_SHIFT ADC_CR2_EXTSEL_SHIFT +# define STM32_ADC_JEXTREG_OFFSET STM32_ADC_CR2_OFFSET +# define ADC_JEXTREG_JEXTSEL_MASK ADC_CR2_JEXTSEL_MASK +# define ADC_EXTREG_JEXTSEL_SHIFT ADC_CR2_JEXTSEL_SHIFT +# define STM32_ADC_ISR_OFFSET STM32_ADC_SR_OFFSET +# define STM32_ADC_IER_OFFSET STM32_ADC_CR1_OFFSET +# ifdef HAVE_BASIC_ADC +# define ADC_EXTREG_EXTEN_MASK ADC_CR2_EXTTRIG +# define ADC_EXTREG_EXTEN_NONE 0 +# define ADC_EXTREG_EXTEN_DEFAULT ADC_CR2_EXTTRIG +# define ADC_JEXTREG_JEXTEN_MASK ADC_CR2_JEXTTRIG +# define ADC_JEXTREG_JEXTEN_NONE 0 +# define ADC_JEXTREG_JEXTEN_DEFAULT ADC_CR2_JEXTTRIG +# else +# define ADC_EXTREG_EXTEN_MASK ADC_CR2_EXTEN_MASK +# define ADC_EXTREG_EXTEN_NONE ADC_CR2_EXTEN_NONE +# define ADC_EXTREG_EXTEN_DEFAULT ADC_CR2_EXTEN_RISING +# define ADC_JEXTREG_JEXTEN_MASK ADC_CR2_JEXTEN_MASK +# define ADC_JEXTREG_JEXTEN_NONE ADC_CR2_JEXTEN_NONE +# define ADC_JEXTREG_JEXTEN_DEFAULT ADC_CR2_JEXTEN_RISING +# endif +#elif defined(HAVE_IP_ADC_V2) +# define STM32_ADC_DMAREG_OFFSET STM32_ADC_CFGR1_OFFSET +# define ADC_DMAREG_DMA ADC_CFGR1_DMAEN +# define STM32_ADC_EXTREG_OFFSET STM32_ADC_CFGR1_OFFSET +# define ADC_EXTREG_EXTSEL_MASK ADC_CFGR1_EXTSEL_MASK +# define ADC_EXTREG_EXTSEL_SHIFT ADC_CFGR1_EXTSEL_SHIFT +# define ADC_EXTREG_EXTEN_MASK ADC_CFGR1_EXTEN_MASK +# define ADC_EXTREG_EXTEN_DEFAULT ADC_CFGR1_EXTEN_RISING +# define STM32_ADC_JEXTREG_OFFSET STM32_ADC_JSQR_OFFSET +# define ADC_JEXTREG_JEXTSEL_MASK ADC_JSQR_JEXTSEL_MASK +# define ADC_EXTREG_JEXTSEL_SHIFT ADC_JSQR_JEXTSEL_SHIFT +# define ADC_JEXTREG_JEXTEN_MASK ADC_JSQR_JEXTEN_MASK +# define ADC_JEXTREG_JEXTEN_DEFAULT ADC_JSQR_JEXTEN_RISING +#endif + +/* Configuration ************************************************************/ + +/* Timer devices may be used for different purposes. One special purpose is + * to control periodic ADC sampling. If CONFIG_STM32_TIMn is defined then + * CONFIG_STM32_TIMn_ADC must also be defined to indicate that timer "n" is + * intended to be used for that purpose. + */ + +/* For the STM32 F1 line, timers 1-4 may be used. + * For the STM32 F3 line, timers 1-4, 6-8, 15, 20 may be used. + * For the STM32 F2/F4 lines, timers 1-5 and 8 may be used. + * For the STM32L15XX line, timers 2-4, 6, 7, 9, 10 may be used. + */ + +#ifdef CONFIG_STM32_STM32L15XX +# undef CONFIG_STM32_TIM1_ADC +# undef CONFIG_STM32_TIM1_ADC1 +# undef CONFIG_STM32_TIM1_ADC2 +# undef CONFIG_STM32_TIM1_ADC3 +# undef CONFIG_STM32_TIM1_ADC4 +#else +# ifndef CONFIG_STM32_TIM1 +# undef CONFIG_STM32_TIM1_ADC +# undef CONFIG_STM32_TIM1_ADC1 +# undef CONFIG_STM32_TIM1_ADC2 +# undef CONFIG_STM32_TIM1_ADC3 +# undef CONFIG_STM32_TIM1_ADC4 +# endif +#endif + +#ifndef CONFIG_STM32_TIM2 +# undef CONFIG_STM32_TIM2_ADC +# undef CONFIG_STM32_TIM2_ADC1 +# undef CONFIG_STM32_TIM2_ADC2 +# undef CONFIG_STM32_TIM2_ADC3 +# undef CONFIG_STM32_TIM2_ADC4 +#endif +#ifndef CONFIG_STM32_TIM3 +# undef CONFIG_STM32_TIM3_ADC +# undef CONFIG_STM32_TIM3_ADC1 +# undef CONFIG_STM32_TIM3_ADC2 +# undef CONFIG_STM32_TIM3_ADC3 +# undef CONFIG_STM32_TIM3_ADC4 +#endif +#ifndef CONFIG_STM32_TIM4 +# undef CONFIG_STM32_TIM4_ADC +# undef CONFIG_STM32_TIM4_ADC1 +# undef CONFIG_STM32_TIM4_ADC2 +# undef CONFIG_STM32_TIM4_ADC3 +# undef CONFIG_STM32_TIM4_ADC4 +#endif + +#if defined(CONFIG_STM32_HAVE_IP_ADC_M3M4_V1) +# ifndef CONFIG_STM32_TIM5 +# undef CONFIG_STM32_TIM5_ADC +# undef CONFIG_STM32_TIM5_ADC1 +# undef CONFIG_STM32_TIM5_ADC2 +# undef CONFIG_STM32_TIM5_ADC3 +# undef CONFIG_STM32_TIM5_ADC4 +# endif +#else +# undef CONFIG_STM32_TIM5_ADC +# undef CONFIG_STM32_TIM5_ADC1 +# undef CONFIG_STM32_TIM5_ADC2 +# undef CONFIG_STM32_TIM5_ADC3 +# undef CONFIG_STM32_TIM5_ADC4 +#endif + +#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F30XX) || \ + defined(CONFIG_STM32_STM32F4XXX) +# ifndef CONFIG_STM32_TIM8 +# undef CONFIG_STM32_TIM8_ADC +# undef CONFIG_STM32_TIM8_ADC1 +# undef CONFIG_STM32_TIM8_ADC2 +# undef CONFIG_STM32_TIM8_ADC3 +# undef CONFIG_STM32_TIM8_ADC4 +# endif +#else +# undef CONFIG_STM32_TIM8_ADC +# undef CONFIG_STM32_TIM8_ADC1 +# undef CONFIG_STM32_TIM8_ADC2 +# undef CONFIG_STM32_TIM8_ADC3 +# undef CONFIG_STM32_TIM8_ADC4 +#endif + +/* Timers 6, 7, 9, 10 used by STM32L15XX family devices. Though there is only + * ADC presented in specification and in device as well, the ADC1 is used + * here in code. See definition of the STM32_NADC + */ + +#if defined(CONFIG_STM32_STM32L15XX) || defined(CONFIG_STM32_STM32F30XX) +# ifndef CONFIG_STM32_TIM6 +# undef CONFIG_STM32_TIM6_ADC +# undef CONFIG_STM32_TIM6_ADC1 +# undef CONFIG_STM32_TIM6_ADC2 +# undef CONFIG_STM32_TIM6_ADC3 +# undef CONFIG_STM32_TIM6_ADC4 +# endif +# ifndef CONFIG_STM32_TIM7 +# undef CONFIG_STM32_TIM7_ADC +# undef CONFIG_STM32_TIM7_ADC1 +# undef CONFIG_STM32_TIM7_ADC2 +# undef CONFIG_STM32_TIM7_ADC3 +# undef CONFIG_STM32_TIM7_ADC4 +# endif +#else +# undef CONFIG_STM32_TIM6_ADC +# undef CONFIG_STM32_TIM6_ADC1 +# undef CONFIG_STM32_TIM6_ADC2 +# undef CONFIG_STM32_TIM6_ADC3 +# undef CONFIG_STM32_TIM6_ADC4 +# undef CONFIG_STM32_TIM7_ADC +# undef CONFIG_STM32_TIM7_ADC1 +# undef CONFIG_STM32_TIM7_ADC2 +# undef CONFIG_STM32_TIM7_ADC3 +# undef CONFIG_STM32_TIM7_ADC4 +#endif + +#if defined(CONFIG_STM32_STM32L15XX) +# ifndef CONFIG_STM32_TIM9 +# undef CONFIG_STM32_TIM9_ADC +# undef CONFIG_STM32_TIM9_ADC1 +# undef CONFIG_STM32_TIM9_ADC2 +# undef CONFIG_STM32_TIM9_ADC3 +# undef CONFIG_STM32_TIM9_ADC4 +# endif +# ifndef CONFIG_STM32_TIM10 +# undef CONFIG_STM32_TIM10_ADC +# undef CONFIG_STM32_TIM10_ADC1 +# undef CONFIG_STM32_TIM10_ADC2 +# undef CONFIG_STM32_TIM10_ADC3 +# undef CONFIG_STM32_TIM10_ADC4 +# endif +#else +# undef CONFIG_STM32_TIM9_ADC +# undef CONFIG_STM32_TIM9_ADC1 +# undef CONFIG_STM32_TIM9_ADC2 +# undef CONFIG_STM32_TIM9_ADC3 +# undef CONFIG_STM32_TIM9_ADC4 +# undef CONFIG_STM32_TIM10_ADC +# undef CONFIG_STM32_TIM10_ADC1 +# undef CONFIG_STM32_TIM10_ADC2 +# undef CONFIG_STM32_TIM10_ADC3 +# undef CONFIG_STM32_TIM10_ADC4 +#endif + +/* Timers 6, 7, and 10-14 are not used with the ADC by any supported family + */ + +#undef CONFIG_STM32_TIM11_ADC +#undef CONFIG_STM32_TIM11_ADC1 +#undef CONFIG_STM32_TIM11_ADC2 +#undef CONFIG_STM32_TIM11_ADC3 +#undef CONFIG_STM32_TIM11_ADC4 +#undef CONFIG_STM32_TIM12_ADC +#undef CONFIG_STM32_TIM12_ADC1 +#undef CONFIG_STM32_TIM12_ADC2 +#undef CONFIG_STM32_TIM12_ADC3 +#undef CONFIG_STM32_TIM12_ADC4 +#undef CONFIG_STM32_TIM13_ADC +#undef CONFIG_STM32_TIM13_ADC1 +#undef CONFIG_STM32_TIM13_ADC2 +#undef CONFIG_STM32_TIM13_ADC3 +#undef CONFIG_STM32_TIM13_ADC4 +#undef CONFIG_STM32_TIM14_ADC +#undef CONFIG_STM32_TIM14_ADC1 +#undef CONFIG_STM32_TIM14_ADC2 +#undef CONFIG_STM32_TIM14_ADC3 +#undef CONFIG_STM32_TIM14_ADC4 + +#ifdef CONFIG_STM32_STM32F30XX +# ifndef CONFIG_STM32_TIM15 +# undef CONFIG_STM32_TIM15_ADC +# undef CONFIG_STM32_TIM15_ADC1 +# undef CONFIG_STM32_TIM15_ADC2 +# undef CONFIG_STM32_TIM15_ADC3 +# undef CONFIG_STM32_TIM15_ADC4 +# endif +# ifndef CONFIG_STM32_TIM20 +# undef CONFIG_STM32_TIM20_ADC +# undef CONFIG_STM32_TIM20_ADC1 +# undef CONFIG_STM32_TIM20_ADC2 +# undef CONFIG_STM32_TIM20_ADC3 +# undef CONFIG_STM32_TIM20_ADC4 +# endif +#else +# undef CONFIG_STM32_TIM15_ADC +# undef CONFIG_STM32_TIM15_ADC1 +# undef CONFIG_STM32_TIM15_ADC2 +# undef CONFIG_STM32_TIM15_ADC3 +# undef CONFIG_STM32_TIM15_ADC4 +# undef CONFIG_STM32_TIM20_ADC +# undef CONFIG_STM32_TIM20_ADC1 +# undef CONFIG_STM32_TIM20_ADC2 +# undef CONFIG_STM32_TIM20_ADC3 +# undef CONFIG_STM32_TIM20_ADC4 +#endif + +/* Up to 4 ADC interfaces are supported */ + +#if STM32_NADC < 4 +# undef CONFIG_STM32_ADC4 +#endif + +#if STM32_NADC < 3 +# undef CONFIG_STM32_ADC3 +#endif + +#if STM32_NADC < 2 +# undef CONFIG_STM32_ADC2 +#endif + +#if STM32_NADC < 1 +# undef CONFIG_STM32_ADC1 +#endif + +#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) || \ + defined(CONFIG_STM32_ADC3) || defined(CONFIG_STM32_ADC4) + +/* DMA support */ + +#undef ADC_HAVE_DMA +#if defined(CONFIG_STM32_ADC1_DMA) || defined(CONFIG_STM32_ADC2_DMA) || \ + defined(CONFIG_STM32_ADC3_DMA) || defined(CONFIG_STM32_ADC4_DMA) +# define ADC_HAVE_DMA 1 +#endif + +#ifdef CONFIG_STM32_ADC1_DMA +# define ADC1_HAVE_DMA 1 +#else +# undef ADC1_HAVE_DMA +#endif + +#ifdef CONFIG_STM32_ADC2_DMA +# define ADC2_HAVE_DMA 1 +#else +# undef ADC2_HAVE_DMA +#endif + +#ifdef CONFIG_STM32_ADC3_DMA +# define ADC3_HAVE_DMA 1 +#else +# undef ADC3_HAVE_DMA +#endif + +#ifdef CONFIG_STM32_ADC4_DMA +# define ADC4_HAVE_DMA 1 +#else +# undef ADC4_HAVE_DMA +#endif + +/* Injected channels support */ + +#if (defined(CONFIG_STM32_ADC1) && (CONFIG_STM32_ADC1_INJECTED_CHAN > 0)) || \ + (defined(CONFIG_STM32_ADC2) && (CONFIG_STM32_ADC2_INJECTED_CHAN > 0)) || \ + (defined(CONFIG_STM32_ADC3) && (CONFIG_STM32_ADC3_INJECTED_CHAN > 0)) || \ + (defined(CONFIG_STM32_ADC4) && (CONFIG_STM32_ADC4_INJECTED_CHAN > 0)) +# define ADC_HAVE_INJECTED +#endif + +/* Timer configuration: If a timer trigger is specified, then get + * information about the timer. + * + * STM32L15XX-family has only one ADC onboard, thus there is no definition + * for other 3 ADC's + */ + +#if defined(CONFIG_STM32_TIM1_ADC1) +# define ADC1_HAVE_TIMER 1 +# define ADC1_TIMER_BASE STM32_TIM1_BASE +# define ADC1_TIMER_PCLK_FREQUENCY STM32_APB2_TIM1_CLKIN +#elif defined(CONFIG_STM32_TIM2_ADC1) +# define ADC1_HAVE_TIMER 1 +# define ADC1_TIMER_BASE STM32_TIM2_BASE +# define ADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM2_CLKIN +#elif defined(CONFIG_STM32_TIM3_ADC1) +# define ADC1_HAVE_TIMER 1 +# define ADC1_TIMER_BASE STM32_TIM3_BASE +# define ADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM3_CLKIN +#elif defined(CONFIG_STM32_TIM4_ADC1) +# define ADC1_HAVE_TIMER 1 +# define ADC1_TIMER_BASE STM32_TIM4_BASE +# define ADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM4_CLKIN +#elif defined(CONFIG_STM32_TIM5_ADC1) +# define ADC1_HAVE_TIMER 1 +# define ADC1_TIMER_BASE STM32_TIM5_BASE +# define ADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM5_CLKIN +#elif defined(CONFIG_STM32_TIM6_ADC1) +# define ADC1_HAVE_TIMER 1 +# define ADC1_TIMER_BASE STM32_TIM6_BASE +# define ADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM6_CLKIN +#elif defined(CONFIG_STM32_TIM7_ADC1) +# define ADC1_HAVE_TIMER 1 +# define ADC1_TIMER_BASE STM32_TIM7_BASE +# define ADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM7_CLKIN +#elif defined(CONFIG_STM32_TIM8_ADC1) +# define ADC1_HAVE_TIMER 1 +# define ADC1_TIMER_BASE STM32_TIM8_BASE +# define ADC1_TIMER_PCLK_FREQUENCY STM32_APB2_TIM8_CLKIN +#elif defined(CONFIG_STM32_TIM9_ADC1) +# define ADC1_HAVE_TIMER 1 +# define ADC1_TIMER_BASE STM32_TIM9_BASE +# define ADC1_TIMER_PCLK_FREQUENCY STM32_APB2_TIM9_CLKIN +#elif defined(CONFIG_STM32_TIM10_ADC1) +# define ADC1_HAVE_TIMER 1 +# define ADC1_TIMER_BASE STM32_TIM10_BASE +# define ADC1_TIMER_PCLK_FREQUENCY STM32_APB2_TIM10_CLKIN +#elif defined(CONFIG_STM32_TIM15_ADC1) +# define ADC1_HAVE_TIMER 1 +# define ADC1_TIMER_BASE STM32_TIM15_BASE +# define ADC1_TIMER_PCLK_FREQUENCY STM32_APB2_TIM15_CLKIN +#else +# undef ADC1_HAVE_TIMER +#endif + +#ifdef ADC1_HAVE_TIMER +# ifndef CONFIG_STM32_ADC1_SAMPLE_FREQUENCY +# error "CONFIG_STM32_ADC1_SAMPLE_FREQUENCY not defined" +# endif +# ifndef CONFIG_STM32_ADC1_TIMTRIG +# error "CONFIG_STM32_ADC1_TIMTRIG not defined" +# warning "Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO 5:TRGO2" +# endif +#endif + +#if defined(CONFIG_STM32_HRTIM_ADC1_TRG1) || defined(CONFIG_STM32_HRTIM_ADC1_TRG2) || \ + defined(CONFIG_STM32_HRTIM_ADC3_TRG3) || defined(CONFIG_STM32_HRTIM_ADC4_TRG4) +# define ADC1_HAVE_HRTIM +#else +# undef ADC1_HAVE_HRTIM +#endif + +#if defined(CONFIG_STM32_TIM1_ADC2) +# define ADC2_HAVE_TIMER 1 +# define ADC2_TIMER_BASE STM32_TIM1_BASE +# define ADC2_TIMER_PCLK_FREQUENCY STM32_APB2_TIM1_CLKIN +#elif defined(CONFIG_STM32_TIM2_ADC2) +# define ADC2_HAVE_TIMER 1 +# define ADC2_TIMER_BASE STM32_TIM2_BASE +# define ADC2_TIMER_PCLK_FREQUENCY STM32_APB1_TIM2_CLKIN +#elif defined(CONFIG_STM32_TIM3_ADC2) +# define ADC2_HAVE_TIMER 1 +# define ADC2_TIMER_BASE STM32_TIM3_BASE +# define ADC2_TIMER_PCLK_FREQUENCY STM32_APB1_TIM3_CLKIN +#elif defined(CONFIG_STM32_TIM4_ADC2) +# define ADC2_HAVE_TIMER 1 +# define ADC2_TIMER_BASE STM32_TIM4_BASE +# define ADC2_TIMER_PCLK_FREQUENCY STM32_APB1_TIM4_CLKIN +#elif defined(CONFIG_STM32_TIM5_ADC2) +# define ADC2_HAVE_TIMER 1 +# define ADC2_TIMER_BASE STM32_TIM5_BASE +# define ADC2_TIMER_PCLK_FREQUENCY STM32_APB1_TIM5_CLKIN +#elif defined(CONFIG_STM32_TIM6_ADC2) +# define ADC2_HAVE_TIMER 1 +# define ADC2_TIMER_BASE STM32_TIM6_BASE +# define ADC2_TIMER_PCLK_FREQUENCY STM32_APB1_TIM6_CLKIN +#elif defined(CONFIG_STM32_TIM8_ADC2) +# define ADC2_HAVE_TIMER 1 +# define ADC2_TIMER_BASE STM32_TIM8_BASE +# define ADC2_TIMER_PCLK_FREQUENCY STM32_APB2_TIM8_CLKIN +#elif defined(CONFIG_STM32_TIM15_ADC2) +# define ADC2_HAVE_TIMER 1 +# define ADC2_TIMER_BASE STM32_TIM15_BASE +# define ADC2_TIMER_PCLK_FREQUENCY STM32_APB2_TIM15_CLKIN +#else +# undef ADC2_HAVE_TIMER +#endif + +#ifdef ADC2_HAVE_TIMER +# ifndef CONFIG_STM32_ADC2_SAMPLE_FREQUENCY +# error "CONFIG_STM32_ADC2_SAMPLE_FREQUENCY not defined" +# endif +# ifndef CONFIG_STM32_ADC2_TIMTRIG +# error "CONFIG_STM32_ADC2_TIMTRIG not defined" +# warning "Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO 5:TRGO2" +# endif +#endif + +#if defined(CONFIG_STM32_HRTIM_ADC2_TRG1) || defined(CONFIG_STM32_HRTIM_ADC2_TRG2) || \ + defined(CONFIG_STM32_HRTIM_ADC2_TRG3) || defined(CONFIG_STM32_HRTIM_ADC2_TRG4) +# define ADC2_HAVE_HRTIM +#else +# undef ADC2_HAVE_HRTIM +#endif + +#if defined(CONFIG_STM32_TIM1_ADC3) +# define ADC3_HAVE_TIMER 1 +# define ADC3_TIMER_BASE STM32_TIM1_BASE +# define ADC3_TIMER_PCLK_FREQUENCY STM32_APB2_TIM1_CLKIN +#elif defined(CONFIG_STM32_TIM2_ADC3) +# define ADC3_HAVE_TIMER 1 +# define ADC3_TIMER_BASE STM32_TIM2_BASE +# define ADC3_TIMER_PCLK_FREQUENCY STM32_APB1_TIM2_CLKIN +#elif defined(CONFIG_STM32_TIM3_ADC3) +# define ADC3_HAVE_TIMER 1 +# define ADC3_TIMER_BASE STM32_TIM3_BASE +# define ADC3_TIMER_PCLK_FREQUENCY STM32_APB1_TIM3_CLKIN +#elif defined(CONFIG_STM32_TIM4_ADC3) +# define ADC3_HAVE_TIMER 1 +# define ADC3_TIMER_BASE STM32_TIM4_BASE +# define ADC3_TIMER_PCLK_FREQUENCY STM32_APB1_TIM4_CLKIN +#elif defined(CONFIG_STM32_TIM5_ADC3) +# define ADC3_HAVE_TIMER 1 +# define ADC3_TIMER_BASE STM32_TIM5_BASE +# define ADC3_TIMER_PCLK_FREQUENCY STM32_APB1_TIM5_CLKIN +#elif defined(CONFIG_STM32_TIM7_ADC3) +# define ADC3_HAVE_TIMER 1 +# define ADC3_TIMER_BASE STM32_TIM7_BASE +# define ADC3_TIMER_PCLK_FREQUENCY STM32_APB1_TIM7_CLKIN +#elif defined(CONFIG_STM32_TIM8_ADC3) +# define ADC3_HAVE_TIMER 1 +# define ADC3_TIMER_BASE STM32_TIM8_BASE +# define ADC3_TIMER_PCLK_FREQUENCY STM32_APB2_TIM8_CLKIN +#elif defined(CONFIG_STM32_TIM15_ADC3) +# define ADC3_HAVE_TIMER 1 +# define ADC3_TIMER_BASE STM32_TIM15_BASE +# define ADC3_TIMER_PCLK_FREQUENCY STM32_APB2_TIM15_CLKIN +#elif defined(CONFIG_STM32_TIM20_ADC3) +# define ADC3_HAVE_TIMER 1 +# define ADC3_TIMER_BASE STM32_TIM20_BASE +# define ADC3_TIMER_PCLK_FREQUENCY STM32_APB2_TIM20_CLKIN +#else +# undef ADC3_HAVE_TIMER +#endif + +#ifdef ADC3_HAVE_TIMER +# ifndef CONFIG_STM32_ADC3_SAMPLE_FREQUENCY +# error "CONFIG_STM32_ADC3_SAMPLE_FREQUENCY not defined" +# endif +# ifndef CONFIG_STM32_ADC3_TIMTRIG +# error "CONFIG_STM32_ADC3_TIMTRIG not defined" +# warning "Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO 5:TRGO2" +# endif +#endif + +#if defined(CONFIG_STM32_TIM1_ADC4) +# define ADC4_HAVE_TIMER 1 +# define ADC4_TIMER_BASE STM32_TIM1_BASE +# define ADC4_TIMER_PCLK_FREQUENCY STM32_APB2_TIM1_CLKIN +#elif defined(CONFIG_STM32_TIM2_ADC4) +# define ADC4_HAVE_TIMER 1 +# define ADC4_TIMER_BASE STM32_TIM2_BASE +# define ADC4_TIMER_PCLK_FREQUENCY STM32_APB1_TIM2_CLKIN +#elif defined(CONFIG_STM32_TIM3_ADC4) +# define ADC4_HAVE_TIMER 1 +# define ADC4_TIMER_BASE STM32_TIM3_BASE +# define ADC4_TIMER_PCLK_FREQUENCY STM32_APB1_TIM3_CLKIN +#elif defined(CONFIG_STM32_TIM4_ADC4) +# define ADC4_HAVE_TIMER 1 +# define ADC4_TIMER_BASE STM32_TIM4_BASE +# define ADC4_TIMER_PCLK_FREQUENCY STM32_APB1_TIM4_CLKIN +#elif defined(CONFIG_STM32_TIM5_ADC4) +# define ADC4_HAVE_TIMER 1 +# define ADC4_TIMER_BASE STM32_TIM5_BASE +# define ADC4_TIMER_PCLK_FREQUENCY STM32_APB1_TIM5_CLKIN +#elif defined(CONFIG_STM32_TIM7_ADC4) +# define ADC4_HAVE_TIMER 1 +# define ADC4_TIMER_BASE STM32_TIM7_BASE +# define ADC4_TIMER_PCLK_FREQUENCY STM32_APB1_TIM7_CLKIN +#elif defined(CONFIG_STM32_TIM8_ADC4) +# define ADC4_HAVE_TIMER 1 +# define ADC4_TIMER_BASE STM32_TIM8_BASE +# define ADC4_TIMER_PCLK_FREQUENCY STM32_APB2_TIM8_CLKIN +#elif defined(CONFIG_STM32_TIM15_ADC4) +# define ADC4_HAVE_TIMER 1 +# define ADC4_TIMER_BASE STM32_TIM15_BASE +# define ADC4_TIMER_PCLK_FREQUENCY STM32_APB2_TIM15_CLKIN +#elif defined(CONFIG_STM32_TIM20_ADC4) +# define ADC4_HAVE_TIMER 1 +# define ADC4_TIMER_BASE STM32_TIM20_BASE +# define ADC4_TIMER_PCLK_FREQUENCY STM32_APB2_TIM20_CLKIN +#else +# undef ADC4_HAVE_TIMER +#endif + +#ifdef ADC4_HAVE_TIMER +# ifndef CONFIG_STM32_ADC4_SAMPLE_FREQUENCY +# error "CONFIG_STM32_ADC4_SAMPLE_FREQUENCY not defined" +# endif +# ifndef CONFIG_STM32_ADC4_TIMTRIG +# error "CONFIG_STM32_ADC4_TIMTRIG not defined" +# warning "Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO 5:TRGO2" +# endif +#endif + +#if defined(ADC1_HAVE_TIMER) || defined(ADC2_HAVE_TIMER) || \ + defined(ADC3_HAVE_TIMER) || defined(ADC4_HAVE_TIMER) +# define ADC_HAVE_TIMER 1 +# if defined(CONFIG_STM32_STM32F10XX) && !defined(CONFIG_STM32_FORCEPOWER) +# warning "CONFIG_STM32_FORCEPOWER must be defined to enable the timer(s)" +# endif +#else +# undef ADC_HAVE_TIMER +#endif + +#if defined(ADC1_HAVE_HRTIM) || defined(ADC2_HAVE_HRTIM) +# define ADC_HAVE_HRTIM +#else +# undef ADC_HAVE_HRTIM +#endif + +/* NOTE: + * The following assumes that all possible combinations of timers and + * values are support EXTSEL. That is not so and it varies from one STM32 + * to another. But this (wrong) assumptions keeps the logic as simple as + * possible. If unsupported combination is used, an error will show up + * later during compilation although it may be difficult to track it back + * to this simplification. + * + * STM32L15XX-family has only one ADC onboard, thus there is no definition + * for other 3 ADC's + */ + +#if defined(HAVE_IP_ADC_V2) +# define ADC1_EXTSEL_T1CC1 ADC12_CFGR1_EXTSEL_T1CC1 +# define ADC1_EXTSEL_T1CC2 ADC12_CFGR1_EXTSEL_T1CC2 +# define ADC1_EXTSEL_T1CC3 ADC12_CFGR1_EXTSEL_T1CC3 +# define ADC1_EXTSEL_T1CC4 ADC12_CFGR1_EXTSEL_T1CC4 +# define ADC1_EXTSEL_T1TRGO ADC12_CFGR1_EXTSEL_T1TRGO +# define ADC1_EXTSEL_T1TRGO2 ADC12_CFGR1_EXTSEL_T1TRGO2 +# define ADC2_EXTSEL_T1CC1 ADC12_CFGR1_EXTSEL_T1CC1 +# define ADC2_EXTSEL_T1CC2 ADC12_CFGR1_EXTSEL_T1CC2 +# define ADC2_EXTSEL_T1CC3 ADC12_CFGR1_EXTSEL_T1CC3 +# define ADC2_EXTSEL_T1CC4 ADC12_CFGR1_EXTSEL_T1CC4 +# define ADC2_EXTSEL_T1TRGO ADC12_CFGR1_EXTSEL_T1TRGO +# define ADC2_EXTSEL_T1TRGO2 ADC12_CFGR1_EXTSEL_T1TRGO2 +# define ADC3_EXTSEL_T1CC1 ADC34_CFGR1_EXTSEL_T1CC1 +# define ADC3_EXTSEL_T1CC2 ADC34_CFGR1_EXTSEL_T1CC2 +# define ADC3_EXTSEL_T1CC3 ADC34_CFGR1_EXTSEL_T1CC3 +# define ADC3_EXTSEL_T1CC4 ADC34_CFGR1_EXTSEL_T1CC4 +# define ADC3_EXTSEL_T1TRGO ADC34_CFGR1_EXTSEL_T1TRGO +# define ADC3_EXTSEL_T1TRGO2 ADC34_CFGR1_EXTSEL_T1TRGO2 +# define ADC4_EXTSEL_T1CC1 ADC34_CFGR1_EXTSEL_T1CC1 +# define ADC4_EXTSEL_T1CC2 ADC34_CFGR1_EXTSEL_T1CC2 +# define ADC4_EXTSEL_T1CC3 ADC34_CFGR1_EXTSEL_T1CC3 +# define ADC4_EXTSEL_T1CC4 ADC34_CFGR1_EXTSEL_T1CC4 +# define ADC4_EXTSEL_T1TRGO ADC34_CFGR1_EXTSEL_T1TRGO +# define ADC4_EXTSEL_T1TRGO2 ADC34_CFGR1_EXTSEL_T1TRGO2 +# define ADC1_EXTSEL_T2CC1 ADC12_CFGR1_EXTSEL_T2CC1 +# define ADC1_EXTSEL_T2CC2 ADC12_CFGR1_EXTSEL_T2CC2 +# define ADC1_EXTSEL_T2CC3 ADC12_CFGR1_EXTSEL_T2CC3 +# define ADC1_EXTSEL_T2CC4 ADC12_CFGR1_EXTSEL_T2CC4 +# define ADC1_EXTSEL_T2TRGO ADC12_CFGR1_EXTSEL_T2TRGO +# define ADC2_EXTSEL_T2CC1 ADC12_CFGR1_EXTSEL_T2CC1 +# define ADC2_EXTSEL_T2CC2 ADC12_CFGR1_EXTSEL_T2CC2 +# define ADC2_EXTSEL_T2CC3 ADC12_CFGR1_EXTSEL_T2CC3 +# define ADC2_EXTSEL_T2CC4 ADC12_CFGR1_EXTSEL_T2CC4 +# define ADC2_EXTSEL_T2TRGO ADC12_CFGR1_EXTSEL_T2TRGO +# define ADC3_EXTSEL_T2CC1 ADC34_CFGR1_EXTSEL_T2CC1 +# define ADC3_EXTSEL_T2CC2 ADC34_CFGR1_EXTSEL_T2CC2 +# define ADC3_EXTSEL_T2CC3 ADC34_CFGR1_EXTSEL_T2CC3 +# define ADC3_EXTSEL_T2CC4 ADC34_CFGR1_EXTSEL_T2CC4 +# define ADC3_EXTSEL_T2TRGO ADC34_CFGR1_EXTSEL_T2TRGO +# define ADC4_EXTSEL_T2CC1 ADC34_CFGR1_EXTSEL_T2CC1 +# define ADC4_EXTSEL_T2CC2 ADC34_CFGR1_EXTSEL_T2CC2 +# define ADC4_EXTSEL_T2CC3 ADC34_CFGR1_EXTSEL_T2CC3 +# define ADC4_EXTSEL_T2CC4 ADC34_CFGR1_EXTSEL_T2CC4 +# define ADC4_EXTSEL_T2TRGO ADC34_CFGR1_EXTSEL_T2TRGO +# define ADC1_EXTSEL_T3CC1 ADC12_CFGR1_EXTSEL_T3CC1 +# define ADC1_EXTSEL_T3CC2 ADC12_CFGR1_EXTSEL_T3CC2 +# define ADC1_EXTSEL_T3CC3 ADC12_CFGR1_EXTSEL_T3CC3 +# define ADC1_EXTSEL_T3CC4 ADC12_CFGR1_EXTSEL_T3CC4 +# define ADC1_EXTSEL_T3TRGO ADC12_CFGR1_EXTSEL_T3TRGO +# define ADC2_EXTSEL_T3CC1 ADC12_CFGR1_EXTSEL_T3CC1 +# define ADC2_EXTSEL_T3CC2 ADC12_CFGR1_EXTSEL_T3CC2 +# define ADC2_EXTSEL_T3CC3 ADC12_CFGR1_EXTSEL_T3CC3 +# define ADC2_EXTSEL_T3CC4 ADC12_CFGR1_EXTSEL_T3CC4 +# define ADC2_EXTSEL_T3TRGO ADC12_CFGR1_EXTSEL_T3TRGO +# define ADC3_EXTSEL_T3CC1 ADC34_CFGR1_EXTSEL_T3CC1 +# define ADC3_EXTSEL_T3CC2 ADC34_CFGR1_EXTSEL_T3CC2 +# define ADC3_EXTSEL_T3CC3 ADC34_CFGR1_EXTSEL_T3CC3 +# define ADC3_EXTSEL_T3CC4 ADC34_CFGR1_EXTSEL_T3CC4 +# define ADC3_EXTSEL_T3TRGO ADC34_CFGR1_EXTSEL_T3TRGO +# define ADC4_EXTSEL_T3CC1 ADC34_CFGR1_EXTSEL_T3CC1 +# define ADC4_EXTSEL_T3CC2 ADC34_CFGR1_EXTSEL_T3CC2 +# define ADC4_EXTSEL_T3CC3 ADC34_CFGR1_EXTSEL_T3CC3 +# define ADC4_EXTSEL_T3CC4 ADC34_CFGR1_EXTSEL_T3CC4 +# define ADC4_EXTSEL_T3TRGO ADC34_CFGR1_EXTSEL_T3TRGO +# define ADC1_EXTSEL_T4CC1 ADC12_CFGR1_EXTSEL_T4CC1 +# define ADC1_EXTSEL_T4CC2 ADC12_CFGR1_EXTSEL_T4CC2 +# define ADC1_EXTSEL_T4CC3 ADC12_CFGR1_EXTSEL_T4CC3 +# define ADC1_EXTSEL_T4CC4 ADC12_CFGR1_EXTSEL_T4CC4 +# define ADC1_EXTSEL_T4TRGO ADC12_CFGR1_EXTSEL_T4TRGO +# define ADC2_EXTSEL_T4CC1 ADC12_CFGR1_EXTSEL_T4CC1 +# define ADC2_EXTSEL_T4CC2 ADC12_CFGR1_EXTSEL_T4CC2 +# define ADC2_EXTSEL_T4CC3 ADC12_CFGR1_EXTSEL_T4CC3 +# define ADC2_EXTSEL_T4CC4 ADC12_CFGR1_EXTSEL_T4CC4 +# define ADC2_EXTSEL_T4TRGO ADC12_CFGR1_EXTSEL_T4TRGO +# define ADC3_EXTSEL_T4CC1 ADC34_CFGR1_EXTSEL_T4CC1 +# define ADC3_EXTSEL_T4CC2 ADC34_CFGR1_EXTSEL_T4CC2 +# define ADC3_EXTSEL_T4CC3 ADC34_CFGR1_EXTSEL_T4CC3 +# define ADC3_EXTSEL_T4CC4 ADC34_CFGR1_EXTSEL_T4CC4 +# define ADC3_EXTSEL_T4TRGO ADC34_CFGR1_EXTSEL_T4TRGO +# define ADC4_EXTSEL_T4CC1 ADC34_CFGR1_EXTSEL_T4CC1 +# define ADC4_EXTSEL_T4CC2 ADC34_CFGR1_EXTSEL_T4CC2 +# define ADC4_EXTSEL_T4CC3 ADC34_CFGR1_EXTSEL_T4CC3 +# define ADC4_EXTSEL_T4CC4 ADC34_CFGR1_EXTSEL_T4CC4 +# define ADC4_EXTSEL_T4TRGO ADC34_CFGR1_EXTSEL_T4TRGO +# define ADC1_EXTSEL_T5CC1 ADC12_CFGR1_EXTSEL_T5CC1 +# define ADC1_EXTSEL_T5CC2 ADC12_CFGR1_EXTSEL_T5CC2 +# define ADC1_EXTSEL_T5CC3 ADC12_CFGR1_EXTSEL_T5CC3 +# define ADC1_EXTSEL_T5CC4 ADC12_CFGR1_EXTSEL_T5CC4 +# define ADC1_EXTSEL_T5TRGO ADC12_CFGR1_EXTSEL_T5TRGO +# define ADC2_EXTSEL_T5CC1 ADC12_CFGR1_EXTSEL_T5CC1 +# define ADC2_EXTSEL_T5CC2 ADC12_CFGR1_EXTSEL_T5CC2 +# define ADC2_EXTSEL_T5CC3 ADC12_CFGR1_EXTSEL_T5CC3 +# define ADC2_EXTSEL_T5CC4 ADC12_CFGR1_EXTSEL_T5CC4 +# define ADC2_EXTSEL_T5TRGO ADC12_CFGR1_EXTSEL_T5TRGO +# define ADC3_EXTSEL_T5CC1 ADC34_CFGR1_EXTSEL_T5CC1 +# define ADC3_EXTSEL_T5CC2 ADC34_CFGR1_EXTSEL_T5CC2 +# define ADC3_EXTSEL_T5CC3 ADC34_CFGR1_EXTSEL_T5CC3 +# define ADC3_EXTSEL_T5CC4 ADC34_CFGR1_EXTSEL_T5CC4 +# define ADC3_EXTSEL_T5TRGO ADC34_CFGR1_EXTSEL_T5TRGO +# define ADC4_EXTSEL_T5CC1 ADC34_CFGR1_EXTSEL_T5CC1 +# define ADC4_EXTSEL_T5CC2 ADC34_CFGR1_EXTSEL_T5CC2 +# define ADC4_EXTSEL_T5CC3 ADC34_CFGR1_EXTSEL_T5CC3 +# define ADC4_EXTSEL_T5CC4 ADC34_CFGR1_EXTSEL_T5CC4 +# define ADC4_EXTSEL_T5TRGO ADC34_CFGR1_EXTSEL_T5TRGO +# define ADC1_EXTSEL_T6CC1 ADC12_CFGR1_EXTSEL_T6CC1 +# define ADC1_EXTSEL_T6CC2 ADC12_CFGR1_EXTSEL_T6CC2 +# define ADC1_EXTSEL_T6CC3 ADC12_CFGR1_EXTSEL_T6CC3 +# define ADC1_EXTSEL_T6CC4 ADC12_CFGR1_EXTSEL_T6CC4 +# define ADC1_EXTSEL_T6TRGO ADC12_CFGR1_EXTSEL_T6TRGO +# define ADC2_EXTSEL_T6CC1 ADC12_CFGR1_EXTSEL_T6CC1 +# define ADC2_EXTSEL_T6CC2 ADC12_CFGR1_EXTSEL_T6CC2 +# define ADC2_EXTSEL_T6CC3 ADC12_CFGR1_EXTSEL_T6CC3 +# define ADC2_EXTSEL_T6CC4 ADC12_CFGR1_EXTSEL_T6CC4 +# define ADC2_EXTSEL_T6TRGO ADC12_CFGR1_EXTSEL_T6TRGO +# define ADC3_EXTSEL_T6CC1 ADC34_CFGR1_EXTSEL_T6CC1 +# define ADC3_EXTSEL_T6CC2 ADC34_CFGR1_EXTSEL_T6CC2 +# define ADC3_EXTSEL_T6CC3 ADC34_CFGR1_EXTSEL_T6CC3 +# define ADC3_EXTSEL_T6CC4 ADC34_CFGR1_EXTSEL_T6CC4 +# define ADC3_EXTSEL_T6TRGO ADC34_CFGR1_EXTSEL_T6TRGO +# define ADC4_EXTSEL_T6CC1 ADC34_CFGR1_EXTSEL_T6CC1 +# define ADC4_EXTSEL_T6CC2 ADC34_CFGR1_EXTSEL_T6CC2 +# define ADC4_EXTSEL_T6CC3 ADC34_CFGR1_EXTSEL_T6CC3 +# define ADC4_EXTSEL_T6CC4 ADC34_CFGR1_EXTSEL_T6CC4 +# define ADC4_EXTSEL_T6TRGO ADC34_CFGR1_EXTSEL_T6TRGO +# define ADC1_EXTSEL_T7CC1 ADC12_CFGR1_EXTSEL_T7CC1 +# define ADC1_EXTSEL_T7CC2 ADC12_CFGR1_EXTSEL_T7CC2 +# define ADC1_EXTSEL_T7CC3 ADC12_CFGR1_EXTSEL_T7CC3 +# define ADC1_EXTSEL_T7CC4 ADC12_CFGR1_EXTSEL_T7CC4 +# define ADC1_EXTSEL_T7TRGO ADC12_CFGR1_EXTSEL_T7TRGO +# define ADC2_EXTSEL_T7CC1 ADC12_CFGR1_EXTSEL_T7CC1 +# define ADC2_EXTSEL_T7CC2 ADC12_CFGR1_EXTSEL_T7CC2 +# define ADC2_EXTSEL_T7CC3 ADC12_CFGR1_EXTSEL_T7CC3 +# define ADC2_EXTSEL_T7CC4 ADC12_CFGR1_EXTSEL_T7CC4 +# define ADC2_EXTSEL_T7TRGO ADC12_CFGR1_EXTSEL_T7TRGO +# define ADC3_EXTSEL_T7CC1 ADC34_CFGR1_EXTSEL_T7CC1 +# define ADC3_EXTSEL_T7CC2 ADC34_CFGR1_EXTSEL_T7CC2 +# define ADC3_EXTSEL_T7CC3 ADC34_CFGR1_EXTSEL_T7CC3 +# define ADC3_EXTSEL_T7CC4 ADC34_CFGR1_EXTSEL_T7CC4 +# define ADC3_EXTSEL_T7TRGO ADC34_CFGR1_EXTSEL_T7TRGO +# define ADC4_EXTSEL_T7CC1 ADC34_CFGR1_EXTSEL_T7CC1 +# define ADC4_EXTSEL_T7CC2 ADC34_CFGR1_EXTSEL_T7CC2 +# define ADC4_EXTSEL_T7CC3 ADC34_CFGR1_EXTSEL_T7CC3 +# define ADC4_EXTSEL_T7CC4 ADC34_CFGR1_EXTSEL_T7CC4 +# define ADC4_EXTSEL_T7TRGO ADC34_CFGR1_EXTSEL_T7TRGO +# define ADC1_EXTSEL_T8CC1 ADC12_CFGR1_EXTSEL_T8CC1 +# define ADC1_EXTSEL_T8CC2 ADC12_CFGR1_EXTSEL_T8CC2 +# define ADC1_EXTSEL_T8CC3 ADC12_CFGR1_EXTSEL_T8CC3 +# define ADC1_EXTSEL_T8CC4 ADC12_CFGR1_EXTSEL_T8CC4 +# define ADC1_EXTSEL_T8TRGO ADC12_CFGR1_EXTSEL_T8TRGO +# define ADC1_EXTSEL_T8TRGO2 ADC12_CFGR1_EXTSEL_T8TRGO2 +# define ADC2_EXTSEL_T8CC1 ADC12_CFGR1_EXTSEL_T8CC1 +# define ADC2_EXTSEL_T8CC2 ADC12_CFGR1_EXTSEL_T8CC2 +# define ADC2_EXTSEL_T8CC3 ADC12_CFGR1_EXTSEL_T8CC3 +# define ADC2_EXTSEL_T8CC4 ADC12_CFGR1_EXTSEL_T8CC4 +# define ADC2_EXTSEL_T8TRGO ADC12_CFGR1_EXTSEL_T8TRGO +# define ADC2_EXTSEL_T8TRGO2 ADC12_CFGR1_EXTSEL_T8TRGO2 +# define ADC3_EXTSEL_T8CC1 ADC34_CFGR1_EXTSEL_T8CC1 +# define ADC3_EXTSEL_T8CC2 ADC34_CFGR1_EXTSEL_T8CC2 +# define ADC3_EXTSEL_T8CC3 ADC34_CFGR1_EXTSEL_T8CC3 +# define ADC3_EXTSEL_T8CC4 ADC34_CFGR1_EXTSEL_T8CC4 +# define ADC3_EXTSEL_T8TRGO ADC34_CFGR1_EXTSEL_T8TRGO +# define ADC3_EXTSEL_T8TRGO2 ADC34_CFGR1_EXTSEL_T8TRGO2 +# define ADC4_EXTSEL_T8CC1 ADC34_CFGR1_EXTSEL_T8CC1 +# define ADC4_EXTSEL_T8CC2 ADC34_CFGR1_EXTSEL_T8CC2 +# define ADC4_EXTSEL_T8CC3 ADC34_CFGR1_EXTSEL_T8CC3 +# define ADC4_EXTSEL_T8CC4 ADC34_CFGR1_EXTSEL_T8CC4 +# define ADC4_EXTSEL_T8TRGO ADC34_CFGR1_EXTSEL_T8TRGO +# define ADC4_EXTSEL_T8TRGO2 ADC34_CFGR1_EXTSEL_T8TRGO2 +# define ADC1_EXTSEL_T9CC1 ADC12_CFGR1_EXTSEL_T9CC1 +# define ADC1_EXTSEL_T9CC2 ADC12_CFGR1_EXTSEL_T9CC2 +# define ADC1_EXTSEL_T9CC3 ADC12_CFGR1_EXTSEL_T9CC3 +# define ADC1_EXTSEL_T9CC4 ADC12_CFGR1_EXTSEL_T9CC4 +# define ADC1_EXTSEL_T9TRGO ADC12_CFGR1_EXTSEL_T9TRGO +# define ADC2_EXTSEL_T9CC1 ADC12_CFGR1_EXTSEL_T9CC1 +# define ADC2_EXTSEL_T9CC2 ADC12_CFGR1_EXTSEL_T9CC2 +# define ADC2_EXTSEL_T9CC3 ADC12_CFGR1_EXTSEL_T9CC3 +# define ADC2_EXTSEL_T9CC4 ADC12_CFGR1_EXTSEL_T9CC4 +# define ADC2_EXTSEL_T9TRGO ADC12_CFGR1_EXTSEL_T9TRGO +# define ADC3_EXTSEL_T9CC1 ADC34_CFGR1_EXTSEL_T9CC1 +# define ADC3_EXTSEL_T9CC2 ADC34_CFGR1_EXTSEL_T9CC2 +# define ADC3_EXTSEL_T9CC3 ADC34_CFGR1_EXTSEL_T9CC3 +# define ADC3_EXTSEL_T9CC4 ADC34_CFGR1_EXTSEL_T9CC4 +# define ADC3_EXTSEL_T9TRGO ADC34_CFGR1_EXTSEL_T9TRGO +# define ADC4_EXTSEL_T9CC1 ADC34_CFGR1_EXTSEL_T9CC1 +# define ADC4_EXTSEL_T9CC2 ADC34_CFGR1_EXTSEL_T9CC2 +# define ADC4_EXTSEL_T9CC3 ADC34_CFGR1_EXTSEL_T9CC3 +# define ADC4_EXTSEL_T9CC4 ADC34_CFGR1_EXTSEL_T9CC4 +# define ADC4_EXTSEL_T9TRGO ADC34_CFGR1_EXTSEL_T9TRGO +# define ADC1_EXTSEL_T10CC1 ADC12_CFGR1_EXTSEL_T10CC1 +# define ADC1_EXTSEL_T10CC2 ADC12_CFGR1_EXTSEL_T10CC2 +# define ADC1_EXTSEL_T10CC3 ADC12_CFGR1_EXTSEL_T10CC3 +# define ADC1_EXTSEL_T10CC4 ADC12_CFGR1_EXTSEL_T10CC4 +# define ADC1_EXTSEL_T10TRGO ADC12_CFGR1_EXTSEL_T10TRGO +# define ADC2_EXTSEL_T10CC1 ADC12_CFGR1_EXTSEL_T10CC1 +# define ADC2_EXTSEL_T10CC2 ADC12_CFGR1_EXTSEL_T10CC2 +# define ADC2_EXTSEL_T10CC3 ADC12_CFGR1_EXTSEL_T10CC3 +# define ADC2_EXTSEL_T10CC4 ADC12_CFGR1_EXTSEL_T10CC4 +# define ADC2_EXTSEL_T10TRGO ADC12_CFGR1_EXTSEL_T10TRGO +# define ADC3_EXTSEL_T10CC1 ADC34_CFGR1_EXTSEL_T10CC1 +# define ADC3_EXTSEL_T10CC2 ADC34_CFGR1_EXTSEL_T10CC2 +# define ADC3_EXTSEL_T10CC3 ADC34_CFGR1_EXTSEL_T10CC3 +# define ADC3_EXTSEL_T10CC4 ADC34_CFGR1_EXTSEL_T10CC4 +# define ADC3_EXTSEL_T10TRGO ADC34_CFGR1_EXTSEL_T10TRGO +# define ADC4_EXTSEL_T10CC1 ADC34_CFGR1_EXTSEL_T10CC1 +# define ADC4_EXTSEL_T10CC2 ADC34_CFGR1_EXTSEL_T10CC2 +# define ADC4_EXTSEL_T10CC3 ADC34_CFGR1_EXTSEL_T10CC3 +# define ADC4_EXTSEL_T10CC4 ADC34_CFGR1_EXTSEL_T10CC4 +# define ADC4_EXTSEL_T10TRGO ADC34_CFGR1_EXTSEL_T10TRGO +# define ADC1_EXTSEL_T15CC1 ADC12_CFGR1_EXTSEL_T15CC1 +# define ADC1_EXTSEL_T15CC2 ADC12_CFGR1_EXTSEL_T15CC2 +# define ADC1_EXTSEL_T15CC3 ADC12_CFGR1_EXTSEL_T15CC3 +# define ADC1_EXTSEL_T15CC4 ADC12_CFGR1_EXTSEL_T15CC4 +# define ADC1_EXTSEL_T15TRGO ADC12_CFGR1_EXTSEL_T15TRGO +# define ADC2_EXTSEL_T15CC1 ADC12_CFGR1_EXTSEL_T15CC1 +# define ADC2_EXTSEL_T15CC2 ADC12_CFGR1_EXTSEL_T15CC2 +# define ADC2_EXTSEL_T15CC3 ADC12_CFGR1_EXTSEL_T15CC3 +# define ADC2_EXTSEL_T15CC4 ADC12_CFGR1_EXTSEL_T15CC4 +# define ADC2_EXTSEL_T15TRGO ADC12_CFGR1_EXTSEL_T15TRGO +# define ADC3_EXTSEL_T15CC1 ADC34_CFGR1_EXTSEL_T15CC1 +# define ADC3_EXTSEL_T15CC2 ADC34_CFGR1_EXTSEL_T15CC2 +# define ADC3_EXTSEL_T15CC3 ADC34_CFGR1_EXTSEL_T15CC3 +# define ADC3_EXTSEL_T15CC4 ADC34_CFGR1_EXTSEL_T15CC4 +# define ADC3_EXTSEL_T15TRGO ADC34_CFGR1_EXTSEL_T15TRGO +# define ADC4_EXTSEL_T15CC1 ADC34_CFGR1_EXTSEL_T15CC1 +# define ADC4_EXTSEL_T15CC2 ADC34_CFGR1_EXTSEL_T15CC2 +# define ADC4_EXTSEL_T15CC3 ADC34_CFGR1_EXTSEL_T15CC3 +# define ADC4_EXTSEL_T15CC4 ADC34_CFGR1_EXTSEL_T15CC4 +# define ADC4_EXTSEL_T15TRGO ADC34_CFGR1_EXTSEL_T15TRGO +# define ADC1_EXTSEL_T20CC1 ADC12_CFGR1_EXTSEL_T20CC1 +# define ADC1_EXTSEL_T20CC2 ADC12_CFGR1_EXTSEL_T20CC2 +# define ADC1_EXTSEL_T20CC3 ADC12_CFGR1_EXTSEL_T20CC3 +# define ADC1_EXTSEL_T20CC4 ADC12_CFGR1_EXTSEL_T20CC4 +# define ADC1_EXTSEL_T20TRGO ADC12_CFGR1_EXTSEL_T20TRGO +# define ADC2_EXTSEL_T20CC1 ADC12_CFGR1_EXTSEL_T20CC1 +# define ADC2_EXTSEL_T20CC2 ADC12_CFGR1_EXTSEL_T20CC2 +# define ADC2_EXTSEL_T20CC3 ADC12_CFGR1_EXTSEL_T20CC3 +# define ADC2_EXTSEL_T20CC4 ADC12_CFGR1_EXTSEL_T20CC4 +# define ADC2_EXTSEL_T20TRGO ADC12_CFGR1_EXTSEL_T20TRGO +# define ADC3_EXTSEL_T20CC1 ADC34_CFGR1_EXTSEL_T20CC1 +# define ADC3_EXTSEL_T20CC2 ADC34_CFGR1_EXTSEL_T20CC2 +# define ADC3_EXTSEL_T20CC3 ADC34_CFGR1_EXTSEL_T20CC3 +# define ADC3_EXTSEL_T20CC4 ADC34_CFGR1_EXTSEL_T20CC4 +# define ADC3_EXTSEL_T20TRGO ADC34_CFGR1_EXTSEL_T20TRGO +# define ADC4_EXTSEL_T20CC1 ADC34_CFGR1_EXTSEL_T20CC1 +# define ADC4_EXTSEL_T20CC2 ADC34_CFGR1_EXTSEL_T20CC2 +# define ADC4_EXTSEL_T20CC3 ADC34_CFGR1_EXTSEL_T20CC3 +# define ADC4_EXTSEL_T20CC4 ADC34_CFGR1_EXTSEL_T20CC4 +# define ADC4_EXTSEL_T20TRGO ADC34_CFGR1_EXTSEL_T20TRGO +# define ADC1_EXTSEL_HRTTRG1 ADC12_CFGR1_EXTSEL_HRT1TRG1 +# define ADC1_EXTSEL_HRTTRG3 ADC12_CFGR1_EXTSEL_HRT1TRG3 +# define ADC2_EXTSEL_HRTTRG1 ADC12_CFGR1_EXTSEL_HRT1TRG1 +# define ADC2_EXTSEL_HRTTRG3 ADC12_CFGR1_EXTSEL_HRT1TRG3 +#else +# define ADC1_EXTSEL_T1CC1 ADC_CR2_EXTSEL_T1CC1 +# define ADC1_EXTSEL_T1CC2 ADC_CR2_EXTSEL_T1CC2 +# define ADC1_EXTSEL_T1CC3 ADC_CR2_EXTSEL_T1CC3 +# define ADC1_EXTSEL_T1CC4 ADC_CR2_EXTSEL_T1CC4 +# define ADC1_EXTSEL_T1TRGO ADC_CR2_EXTSEL_T1TRGO +# define ADC2_EXTSEL_T1CC1 ADC_CR2_EXTSEL_T1CC1 +# define ADC2_EXTSEL_T1CC2 ADC_CR2_EXTSEL_T1CC2 +# define ADC2_EXTSEL_T1CC3 ADC_CR2_EXTSEL_T1CC3 +# define ADC2_EXTSEL_T1CC4 ADC_CR2_EXTSEL_T1CC4 +# define ADC2_EXTSEL_T1TRGO ADC_CR2_EXTSEL_T1TRGO +# define ADC3_EXTSEL_T1CC1 ADC_CR2_EXTSEL_T1CC1 +# define ADC3_EXTSEL_T1CC2 ADC_CR2_EXTSEL_T1CC2 +# define ADC3_EXTSEL_T1CC3 ADC_CR2_EXTSEL_T1CC3 +# define ADC3_EXTSEL_T1CC4 ADC_CR2_EXTSEL_T1CC4 +# define ADC3_EXTSEL_T1TRGO ADC_CR2_EXTSEL_T1TRGO +# define ADC4_EXTSEL_T1CC1 ADC_CR2_EXTSEL_T1CC1 +# define ADC4_EXTSEL_T1CC2 ADC_CR2_EXTSEL_T1CC2 +# define ADC4_EXTSEL_T1CC3 ADC_CR2_EXTSEL_T1CC3 +# define ADC4_EXTSEL_T1CC4 ADC_CR2_EXTSEL_T1CC4 +# define ADC4_EXTSEL_T1TRGO ADC_CR2_EXTSEL_T1TRGO +# define ADC1_EXTSEL_T2CC1 ADC_CR2_EXTSEL_T2CC1 +# define ADC1_EXTSEL_T2CC2 ADC_CR2_EXTSEL_T2CC2 +# define ADC1_EXTSEL_T2CC3 ADC_CR2_EXTSEL_T2CC3 +# define ADC1_EXTSEL_T2CC4 ADC_CR2_EXTSEL_T2CC4 +# define ADC1_EXTSEL_T2TRGO ADC_CR2_EXTSEL_T2TRGO +# define ADC2_EXTSEL_T2CC1 ADC_CR2_EXTSEL_T2CC1 +# define ADC2_EXTSEL_T2CC2 ADC_CR2_EXTSEL_T2CC2 +# define ADC2_EXTSEL_T2CC3 ADC_CR2_EXTSEL_T2CC3 +# define ADC2_EXTSEL_T2CC4 ADC_CR2_EXTSEL_T2CC4 +# define ADC2_EXTSEL_T2TRGO ADC_CR2_EXTSEL_T2TRGO +# define ADC3_EXTSEL_T2CC1 ADC_CR2_EXTSEL_T2CC1 +# define ADC3_EXTSEL_T2CC2 ADC_CR2_EXTSEL_T2CC2 +# define ADC3_EXTSEL_T2CC3 ADC_CR2_EXTSEL_T2CC3 +# define ADC3_EXTSEL_T2CC4 ADC_CR2_EXTSEL_T2CC4 +# define ADC3_EXTSEL_T2TRGO ADC_CR2_EXTSEL_T2TRGO +# define ADC4_EXTSEL_T2CC1 ADC_CR2_EXTSEL_T2CC1 +# define ADC4_EXTSEL_T2CC2 ADC_CR2_EXTSEL_T2CC2 +# define ADC4_EXTSEL_T2CC3 ADC_CR2_EXTSEL_T2CC3 +# define ADC4_EXTSEL_T2CC4 ADC_CR2_EXTSEL_T2CC4 +# define ADC4_EXTSEL_T2TRGO ADC_CR2_EXTSEL_T2TRGO +# define ADC1_EXTSEL_T3CC1 ADC_CR2_EXTSEL_T3CC1 +# define ADC1_EXTSEL_T3CC2 ADC_CR2_EXTSEL_T3CC2 +# define ADC1_EXTSEL_T3CC3 ADC_CR2_EXTSEL_T3CC3 +# define ADC1_EXTSEL_T3CC4 ADC_CR2_EXTSEL_T3CC4 +# define ADC1_EXTSEL_T3TRGO ADC_CR2_EXTSEL_T3TRGO +# define ADC2_EXTSEL_T3CC1 ADC_CR2_EXTSEL_T3CC1 +# define ADC2_EXTSEL_T3CC2 ADC_CR2_EXTSEL_T3CC2 +# define ADC2_EXTSEL_T3CC3 ADC_CR2_EXTSEL_T3CC3 +# define ADC2_EXTSEL_T3CC4 ADC_CR2_EXTSEL_T3CC4 +# define ADC2_EXTSEL_T3TRGO ADC_CR2_EXTSEL_T3TRGO +# define ADC3_EXTSEL_T3CC1 ADC_CR2_EXTSEL_T3CC1 +# define ADC3_EXTSEL_T3CC2 ADC_CR2_EXTSEL_T3CC2 +# define ADC3_EXTSEL_T3CC3 ADC_CR2_EXTSEL_T3CC3 +# define ADC3_EXTSEL_T3CC4 ADC_CR2_EXTSEL_T3CC4 +# define ADC3_EXTSEL_T3TRGO ADC_CR2_EXTSEL_T3TRGO +# define ADC4_EXTSEL_T3CC1 ADC_CR2_EXTSEL_T3CC1 +# define ADC4_EXTSEL_T3CC2 ADC_CR2_EXTSEL_T3CC2 +# define ADC4_EXTSEL_T3CC3 ADC_CR2_EXTSEL_T3CC3 +# define ADC4_EXTSEL_T3CC4 ADC_CR2_EXTSEL_T3CC4 +# define ADC4_EXTSEL_T3TRGO ADC_CR2_EXTSEL_T3TRGO +# define ADC1_EXTSEL_T4CC1 ADC_CR2_EXTSEL_T4CC1 +# define ADC1_EXTSEL_T4CC2 ADC_CR2_EXTSEL_T4CC2 +# define ADC1_EXTSEL_T4CC3 ADC_CR2_EXTSEL_T4CC3 +# define ADC1_EXTSEL_T4CC4 ADC_CR2_EXTSEL_T4CC4 +# define ADC1_EXTSEL_T4TRGO ADC_CR2_EXTSEL_T4TRGO +# define ADC2_EXTSEL_T4CC1 ADC_CR2_EXTSEL_T4CC1 +# define ADC2_EXTSEL_T4CC2 ADC_CR2_EXTSEL_T4CC2 +# define ADC2_EXTSEL_T4CC3 ADC_CR2_EXTSEL_T4CC3 +# define ADC2_EXTSEL_T4CC4 ADC_CR2_EXTSEL_T4CC4 +# define ADC2_EXTSEL_T4TRGO ADC_CR2_EXTSEL_T4TRGO +# define ADC3_EXTSEL_T4CC1 ADC_CR2_EXTSEL_T4CC1 +# define ADC3_EXTSEL_T4CC2 ADC_CR2_EXTSEL_T4CC2 +# define ADC3_EXTSEL_T4CC3 ADC_CR2_EXTSEL_T4CC3 +# define ADC3_EXTSEL_T4CC4 ADC_CR2_EXTSEL_T4CC4 +# define ADC3_EXTSEL_T4TRGO ADC_CR2_EXTSEL_T4TRGO +# define ADC4_EXTSEL_T4CC1 ADC_CR2_EXTSEL_T4CC1 +# define ADC4_EXTSEL_T4CC2 ADC_CR2_EXTSEL_T4CC2 +# define ADC4_EXTSEL_T4CC3 ADC_CR2_EXTSEL_T4CC3 +# define ADC4_EXTSEL_T4CC4 ADC_CR2_EXTSEL_T4CC4 +# define ADC4_EXTSEL_T4TRGO ADC_CR2_EXTSEL_T4TRGO +# define ADC1_EXTSEL_T5CC1 ADC_CR2_EXTSEL_T5CC1 +# define ADC1_EXTSEL_T5CC2 ADC_CR2_EXTSEL_T5CC2 +# define ADC1_EXTSEL_T5CC3 ADC_CR2_EXTSEL_T5CC3 +# define ADC1_EXTSEL_T5CC4 ADC_CR2_EXTSEL_T5CC4 +# define ADC1_EXTSEL_T5TRGO ADC_CR2_EXTSEL_T5TRGO +# define ADC2_EXTSEL_T5CC1 ADC_CR2_EXTSEL_T5CC1 +# define ADC2_EXTSEL_T5CC2 ADC_CR2_EXTSEL_T5CC2 +# define ADC2_EXTSEL_T5CC3 ADC_CR2_EXTSEL_T5CC3 +# define ADC2_EXTSEL_T5CC4 ADC_CR2_EXTSEL_T5CC4 +# define ADC2_EXTSEL_T5TRGO ADC_CR2_EXTSEL_T5TRGO +# define ADC3_EXTSEL_T5CC1 ADC_CR2_EXTSEL_T5CC1 +# define ADC3_EXTSEL_T5CC2 ADC_CR2_EXTSEL_T5CC2 +# define ADC3_EXTSEL_T5CC3 ADC_CR2_EXTSEL_T5CC3 +# define ADC3_EXTSEL_T5CC4 ADC_CR2_EXTSEL_T5CC4 +# define ADC3_EXTSEL_T5TRGO ADC_CR2_EXTSEL_T5TRGO +# define ADC4_EXTSEL_T5CC1 ADC_CR2_EXTSEL_T5CC1 +# define ADC4_EXTSEL_T5CC2 ADC_CR2_EXTSEL_T5CC2 +# define ADC4_EXTSEL_T5CC3 ADC_CR2_EXTSEL_T5CC3 +# define ADC4_EXTSEL_T5CC4 ADC_CR2_EXTSEL_T5CC4 +# define ADC4_EXTSEL_T5TRGO ADC_CR2_EXTSEL_T5TRGO +# define ADC1_EXTSEL_T6CC1 ADC_CR2_EXTSEL_T6CC1 +# define ADC1_EXTSEL_T6CC2 ADC_CR2_EXTSEL_T6CC2 +# define ADC1_EXTSEL_T6CC3 ADC_CR2_EXTSEL_T6CC3 +# define ADC1_EXTSEL_T6CC4 ADC_CR2_EXTSEL_T6CC4 +# define ADC1_EXTSEL_T6TRGO ADC_CR2_EXTSEL_T6TRGO +# define ADC2_EXTSEL_T6CC1 ADC_CR2_EXTSEL_T6CC1 +# define ADC2_EXTSEL_T6CC2 ADC_CR2_EXTSEL_T6CC2 +# define ADC2_EXTSEL_T6CC3 ADC_CR2_EXTSEL_T6CC3 +# define ADC2_EXTSEL_T6CC4 ADC_CR2_EXTSEL_T6CC4 +# define ADC2_EXTSEL_T6TRGO ADC_CR2_EXTSEL_T6TRGO +# define ADC3_EXTSEL_T6CC1 ADC_CR2_EXTSEL_T6CC1 +# define ADC3_EXTSEL_T6CC2 ADC_CR2_EXTSEL_T6CC2 +# define ADC3_EXTSEL_T6CC3 ADC_CR2_EXTSEL_T6CC3 +# define ADC3_EXTSEL_T6CC4 ADC_CR2_EXTSEL_T6CC4 +# define ADC3_EXTSEL_T6TRGO ADC_CR2_EXTSEL_T6TRGO +# define ADC4_EXTSEL_T6CC1 ADC_CR2_EXTSEL_T6CC1 +# define ADC4_EXTSEL_T6CC2 ADC_CR2_EXTSEL_T6CC2 +# define ADC4_EXTSEL_T6CC3 ADC_CR2_EXTSEL_T6CC3 +# define ADC4_EXTSEL_T6CC4 ADC_CR2_EXTSEL_T6CC4 +# define ADC4_EXTSEL_T6TRGO ADC_CR2_EXTSEL_T6TRGO +# define ADC1_EXTSEL_T7CC1 ADC_CR2_EXTSEL_T7CC1 +# define ADC1_EXTSEL_T7CC2 ADC_CR2_EXTSEL_T7CC2 +# define ADC1_EXTSEL_T7CC3 ADC_CR2_EXTSEL_T7CC3 +# define ADC1_EXTSEL_T7CC4 ADC_CR2_EXTSEL_T7CC4 +# define ADC1_EXTSEL_T7TRGO ADC_CR2_EXTSEL_T7TRGO +# define ADC2_EXTSEL_T7CC1 ADC_CR2_EXTSEL_T7CC1 +# define ADC2_EXTSEL_T7CC2 ADC_CR2_EXTSEL_T7CC2 +# define ADC2_EXTSEL_T7CC3 ADC_CR2_EXTSEL_T7CC3 +# define ADC2_EXTSEL_T7CC4 ADC_CR2_EXTSEL_T7CC4 +# define ADC2_EXTSEL_T7TRGO ADC_CR2_EXTSEL_T7TRGO +# define ADC3_EXTSEL_T7CC1 ADC_CR2_EXTSEL_T7CC1 +# define ADC3_EXTSEL_T7CC2 ADC_CR2_EXTSEL_T7CC2 +# define ADC3_EXTSEL_T7CC3 ADC_CR2_EXTSEL_T7CC3 +# define ADC3_EXTSEL_T7CC4 ADC_CR2_EXTSEL_T7CC4 +# define ADC3_EXTSEL_T7TRGO ADC_CR2_EXTSEL_T7TRGO +# define ADC4_EXTSEL_T7CC1 ADC_CR2_EXTSEL_T7CC1 +# define ADC4_EXTSEL_T7CC2 ADC_CR2_EXTSEL_T7CC2 +# define ADC4_EXTSEL_T7CC3 ADC_CR2_EXTSEL_T7CC3 +# define ADC4_EXTSEL_T7CC4 ADC_CR2_EXTSEL_T7CC4 +# define ADC4_EXTSEL_T7TRGO ADC_CR2_EXTSEL_T7TRGO +# define ADC1_EXTSEL_T8CC1 ADC_CR2_EXTSEL_T8CC1 +# define ADC1_EXTSEL_T8CC2 ADC_CR2_EXTSEL_T8CC2 +# define ADC1_EXTSEL_T8CC3 ADC_CR2_EXTSEL_T8CC3 +# define ADC1_EXTSEL_T8CC4 ADC_CR2_EXTSEL_T8CC4 +# define ADC1_EXTSEL_T8TRGO ADC_CR2_EXTSEL_T8TRGO +# define ADC2_EXTSEL_T8CC1 ADC_CR2_EXTSEL_T8CC1 +# define ADC2_EXTSEL_T8CC2 ADC_CR2_EXTSEL_T8CC2 +# define ADC2_EXTSEL_T8CC3 ADC_CR2_EXTSEL_T8CC3 +# define ADC2_EXTSEL_T8CC4 ADC_CR2_EXTSEL_T8CC4 +# define ADC2_EXTSEL_T8TRGO ADC_CR2_EXTSEL_T8TRGO +# define ADC3_EXTSEL_T8CC1 ADC_CR2_EXTSEL_T8CC1 +# define ADC3_EXTSEL_T8CC2 ADC_CR2_EXTSEL_T8CC2 +# define ADC3_EXTSEL_T8CC3 ADC_CR2_EXTSEL_T8CC3 +# define ADC3_EXTSEL_T8CC4 ADC_CR2_EXTSEL_T8CC4 +# define ADC3_EXTSEL_T8TRGO ADC_CR2_EXTSEL_T8TRGO +# define ADC4_EXTSEL_T8CC1 ADC_CR2_EXTSEL_T8CC1 +# define ADC4_EXTSEL_T8CC2 ADC_CR2_EXTSEL_T8CC2 +# define ADC4_EXTSEL_T8CC3 ADC_CR2_EXTSEL_T8CC3 +# define ADC4_EXTSEL_T8CC4 ADC_CR2_EXTSEL_T8CC4 +# define ADC4_EXTSEL_T8TRGO ADC_CR2_EXTSEL_T8TRGO +# define ADC1_EXTSEL_T9CC1 ADC_CR2_EXTSEL_T9CC1 +# define ADC1_EXTSEL_T9CC2 ADC_CR2_EXTSEL_T9CC2 +# define ADC1_EXTSEL_T9CC3 ADC_CR2_EXTSEL_T9CC3 +# define ADC1_EXTSEL_T9CC4 ADC_CR2_EXTSEL_T9CC4 +# define ADC1_EXTSEL_T9TRGO ADC_CR2_EXTSEL_T9TRGO +# define ADC2_EXTSEL_T9CC1 ADC_CR2_EXTSEL_T9CC1 +# define ADC2_EXTSEL_T9CC2 ADC_CR2_EXTSEL_T9CC2 +# define ADC2_EXTSEL_T9CC3 ADC_CR2_EXTSEL_T9CC3 +# define ADC2_EXTSEL_T9CC4 ADC_CR2_EXTSEL_T9CC4 +# define ADC2_EXTSEL_T9TRGO ADC_CR2_EXTSEL_T9TRGO +# define ADC3_EXTSEL_T9CC1 ADC_CR2_EXTSEL_T9CC1 +# define ADC3_EXTSEL_T9CC2 ADC_CR2_EXTSEL_T9CC2 +# define ADC3_EXTSEL_T9CC3 ADC_CR2_EXTSEL_T9CC3 +# define ADC3_EXTSEL_T9CC4 ADC_CR2_EXTSEL_T9CC4 +# define ADC3_EXTSEL_T9TRGO ADC_CR2_EXTSEL_T9TRGO +# define ADC4_EXTSEL_T9CC1 ADC_CR2_EXTSEL_T9CC1 +# define ADC4_EXTSEL_T9CC2 ADC_CR2_EXTSEL_T9CC2 +# define ADC4_EXTSEL_T9CC3 ADC_CR2_EXTSEL_T9CC3 +# define ADC4_EXTSEL_T9CC4 ADC_CR2_EXTSEL_T9CC4 +# define ADC4_EXTSEL_T9TRGO ADC_CR2_EXTSEL_T9TRGO +# define ADC1_EXTSEL_T10CC1 ADC_CR2_EXTSEL_T10CC1 +# define ADC1_EXTSEL_T10CC2 ADC_CR2_EXTSEL_T10CC2 +# define ADC1_EXTSEL_T10CC3 ADC_CR2_EXTSEL_T10CC3 +# define ADC1_EXTSEL_T10CC4 ADC_CR2_EXTSEL_T10CC4 +# define ADC1_EXTSEL_T10TRGO ADC_CR2_EXTSEL_T10TRGO +# define ADC2_EXTSEL_T10CC1 ADC_CR2_EXTSEL_T10CC1 +# define ADC2_EXTSEL_T10CC2 ADC_CR2_EXTSEL_T10CC2 +# define ADC2_EXTSEL_T10CC3 ADC_CR2_EXTSEL_T10CC3 +# define ADC2_EXTSEL_T10CC4 ADC_CR2_EXTSEL_T10CC4 +# define ADC2_EXTSEL_T10TRGO ADC_CR2_EXTSEL_T10TRGO +# define ADC3_EXTSEL_T10CC1 ADC_CR2_EXTSEL_T10CC1 +# define ADC3_EXTSEL_T10CC2 ADC_CR2_EXTSEL_T10CC2 +# define ADC3_EXTSEL_T10CC3 ADC_CR2_EXTSEL_T10CC3 +# define ADC3_EXTSEL_T10CC4 ADC_CR2_EXTSEL_T10CC4 +# define ADC3_EXTSEL_T10TRGO ADC_CR2_EXTSEL_T10TRGO +# define ADC4_EXTSEL_T10CC1 ADC_CR2_EXTSEL_T10CC1 +# define ADC4_EXTSEL_T10CC2 ADC_CR2_EXTSEL_T10CC2 +# define ADC4_EXTSEL_T10CC3 ADC_CR2_EXTSEL_T10CC3 +# define ADC4_EXTSEL_T10CC4 ADC_CR2_EXTSEL_T10CC4 +# define ADC4_EXTSEL_T10TRGO ADC_CR2_EXTSEL_T10TRGO +# define ADC1_EXTSEL_T15CC1 ADC_CR2_EXTSEL_T15CC1 +# define ADC1_EXTSEL_T15CC2 ADC_CR2_EXTSEL_T15CC2 +# define ADC1_EXTSEL_T15CC3 ADC_CR2_EXTSEL_T15CC3 +# define ADC1_EXTSEL_T15CC4 ADC_CR2_EXTSEL_T15CC4 +# define ADC1_EXTSEL_T15TRGO ADC_CR2_EXTSEL_T15TRGO +# define ADC2_EXTSEL_T15CC1 ADC_CR2_EXTSEL_T15CC1 +# define ADC2_EXTSEL_T15CC2 ADC_CR2_EXTSEL_T15CC2 +# define ADC2_EXTSEL_T15CC3 ADC_CR2_EXTSEL_T15CC3 +# define ADC2_EXTSEL_T15CC4 ADC_CR2_EXTSEL_T15CC4 +# define ADC2_EXTSEL_T15TRGO ADC_CR2_EXTSEL_T15TRGO +# define ADC3_EXTSEL_T15CC1 ADC_CR2_EXTSEL_T15CC1 +# define ADC3_EXTSEL_T15CC2 ADC_CR2_EXTSEL_T15CC2 +# define ADC3_EXTSEL_T15CC3 ADC_CR2_EXTSEL_T15CC3 +# define ADC3_EXTSEL_T15CC4 ADC_CR2_EXTSEL_T15CC4 +# define ADC3_EXTSEL_T15TRGO ADC_CR2_EXTSEL_T15TRGO +# define ADC4_EXTSEL_T15CC1 ADC_CR2_EXTSEL_T15CC1 +# define ADC4_EXTSEL_T15CC2 ADC_CR2_EXTSEL_T15CC2 +# define ADC4_EXTSEL_T15CC3 ADC_CR2_EXTSEL_T15CC3 +# define ADC4_EXTSEL_T15CC4 ADC_CR2_EXTSEL_T15CC4 +# define ADC4_EXTSEL_T15TRGO ADC_CR2_EXTSEL_T15TRGO +# define ADC1_EXTSEL_T20CC1 ADC_CR2_EXTSEL_T20CC1 +# define ADC1_EXTSEL_T20CC2 ADC_CR2_EXTSEL_T20CC2 +# define ADC1_EXTSEL_T20CC3 ADC_CR2_EXTSEL_T20CC3 +# define ADC1_EXTSEL_T20CC4 ADC_CR2_EXTSEL_T20CC4 +# define ADC1_EXTSEL_T20TRGO ADC_CR2_EXTSEL_T20TRGO +# define ADC2_EXTSEL_T20CC1 ADC_CR2_EXTSEL_T20CC1 +# define ADC2_EXTSEL_T20CC2 ADC_CR2_EXTSEL_T20CC2 +# define ADC2_EXTSEL_T20CC3 ADC_CR2_EXTSEL_T20CC3 +# define ADC2_EXTSEL_T20CC4 ADC_CR2_EXTSEL_T20CC4 +# define ADC2_EXTSEL_T20TRGO ADC_CR2_EXTSEL_T20TRGO +# define ADC3_EXTSEL_T20CC1 ADC_CR2_EXTSEL_T20CC1 +# define ADC3_EXTSEL_T20CC2 ADC_CR2_EXTSEL_T20CC2 +# define ADC3_EXTSEL_T20CC3 ADC_CR2_EXTSEL_T20CC3 +# define ADC3_EXTSEL_T20CC4 ADC_CR2_EXTSEL_T20CC4 +# define ADC3_EXTSEL_T20TRGO ADC_CR2_EXTSEL_T20TRGO +# define ADC4_EXTSEL_T20CC1 ADC_CR2_EXTSEL_T20CC1 +# define ADC4_EXTSEL_T20CC2 ADC_CR2_EXTSEL_T20CC2 +# define ADC4_EXTSEL_T20CC3 ADC_CR2_EXTSEL_T20CC3 +# define ADC4_EXTSEL_T20CC4 ADC_CR2_EXTSEL_T20CC4 +# define ADC4_EXTSEL_T20TRGO ADC_CR2_EXTSEL_T20TRGO +#endif + +/* JEXTSEL definitions. + * NOTE: Assumptions like for EXTSEL definitions (look above) + */ + +#if defined(HAVE_IP_ADC_V2) +# define ADC1_JEXTSEL_T1CC1 ADC12_JSQR_JEXTSEL_T1CC1 +# define ADC1_JEXTSEL_T1CC2 ADC12_JSQR_JEXTSEL_T1CC2 +# define ADC1_JEXTSEL_T1CC3 ADC12_JSQR_JEXTSEL_T1CC3 +# define ADC1_JEXTSEL_T1CC4 ADC12_JSQR_JEXTSEL_T1CC4 +# define ADC1_JEXTSEL_T1TRGO ADC12_JSQR_JEXTSEL_T1TRGO +# define ADC2_JEXTSEL_T1CC1 ADC12_JSQR_JEXTSEL_T1CC1 +# define ADC2_JEXTSEL_T1CC2 ADC12_JSQR_JEXTSEL_T1CC2 +# define ADC2_JEXTSEL_T1CC3 ADC12_JSQR_JEXTSEL_T1CC3 +# define ADC2_JEXTSEL_T1CC4 ADC12_JSQR_JEXTSEL_T1CC4 +# define ADC2_JEXTSEL_T1TRGO ADC12_JSQR_JEXTSEL_T1TRGO +# define ADC3_JEXTSEL_T1CC1 ADC34_JSQR_JEXTSEL_T1CC1 +# define ADC3_JEXTSEL_T1CC2 ADC34_JSQR_JEXTSEL_T1CC2 +# define ADC3_JEXTSEL_T1CC3 ADC34_JSQR_JEXTSEL_T1CC3 +# define ADC3_JEXTSEL_T1CC4 ADC34_JSQR_JEXTSEL_T1CC4 +# define ADC3_JEXTSEL_T1TRGO ADC34_JSQR_JEXTSEL_T1TRGO +# define ADC4_JEXTSEL_T1CC1 ADC34_JSQR_JEXTSEL_T1CC1 +# define ADC4_JEXTSEL_T1CC2 ADC34_JSQR_JEXTSEL_T1CC2 +# define ADC4_JEXTSEL_T1CC3 ADC34_JSQR_JEXTSEL_T1CC3 +# define ADC4_JEXTSEL_T1CC4 ADC34_JSQR_JEXTSEL_T1CC4 +# define ADC4_JEXTSEL_T1TRGO ADC34_JSQR_JEXTSEL_T1TRGO +# define ADC1_JEXTSEL_T2CC1 ADC12_JSQR_JEXTSEL_T2CC1 +# define ADC1_JEXTSEL_T2CC2 ADC12_JSQR_JEXTSEL_T2CC2 +# define ADC1_JEXTSEL_T2CC3 ADC12_JSQR_JEXTSEL_T2CC3 +# define ADC1_JEXTSEL_T2CC4 ADC12_JSQR_JEXTSEL_T2CC4 +# define ADC1_JEXTSEL_T2TRGO ADC12_JSQR_JEXTSEL_T2TRGO +# define ADC2_JEXTSEL_T2CC1 ADC12_JSQR_JEXTSEL_T2CC1 +# define ADC2_JEXTSEL_T2CC2 ADC12_JSQR_JEXTSEL_T2CC2 +# define ADC2_JEXTSEL_T2CC3 ADC12_JSQR_JEXTSEL_T2CC3 +# define ADC2_JEXTSEL_T2CC4 ADC12_JSQR_JEXTSEL_T2CC4 +# define ADC2_JEXTSEL_T2TRGO ADC12_JSQR_JEXTSEL_T2TRGO +# define ADC3_JEXTSEL_T2CC1 ADC34_JSQR_JEXTSEL_T2CC1 +# define ADC3_JEXTSEL_T2CC2 ADC34_JSQR_JEXTSEL_T2CC2 +# define ADC3_JEXTSEL_T2CC3 ADC34_JSQR_JEXTSEL_T2CC3 +# define ADC3_JEXTSEL_T2CC4 ADC34_JSQR_JEXTSEL_T2CC4 +# define ADC3_JEXTSEL_T2TRGO ADC34_JSQR_JEXTSEL_T2TRGO +# define ADC4_JEXTSEL_T2CC1 ADC34_JSQR_JEXTSEL_T2CC1 +# define ADC4_JEXTSEL_T2CC2 ADC34_JSQR_JEXTSEL_T2CC2 +# define ADC4_JEXTSEL_T2CC3 ADC34_JSQR_JEXTSEL_T2CC3 +# define ADC4_JEXTSEL_T2CC4 ADC34_JSQR_JEXTSEL_T2CC4 +# define ADC4_JEXTSEL_T2TRGO ADC34_JSQR_JEXTSEL_T2TRGO +# define ADC1_JEXTSEL_T3CC1 ADC12_JSQR_JEXTSEL_T3CC1 +# define ADC1_JEXTSEL_T3CC2 ADC12_JSQR_JEXTSEL_T3CC2 +# define ADC1_JEXTSEL_T3CC3 ADC12_JSQR_JEXTSEL_T3CC3 +# define ADC1_JEXTSEL_T3CC4 ADC12_JSQR_JEXTSEL_T3CC4 +# define ADC1_JEXTSEL_T3TRGO ADC12_JSQR_JEXTSEL_T3TRGO +# define ADC2_JEXTSEL_T3CC1 ADC12_JSQR_JEXTSEL_T3CC1 +# define ADC2_JEXTSEL_T3CC2 ADC12_JSQR_JEXTSEL_T3CC2 +# define ADC2_JEXTSEL_T3CC3 ADC12_JSQR_JEXTSEL_T3CC3 +# define ADC2_JEXTSEL_T3CC4 ADC12_JSQR_JEXTSEL_T3CC4 +# define ADC2_JEXTSEL_T3TRGO ADC12_JSQR_JEXTSEL_T3TRGO +# define ADC3_JEXTSEL_T3CC1 ADC34_JSQR_JEXTSEL_T3CC1 +# define ADC3_JEXTSEL_T3CC2 ADC34_JSQR_JEXTSEL_T3CC2 +# define ADC3_JEXTSEL_T3CC3 ADC34_JSQR_JEXTSEL_T3CC3 +# define ADC3_JEXTSEL_T3CC4 ADC34_JSQR_JEXTSEL_T3CC4 +# define ADC3_JEXTSEL_T3TRGO ADC34_JSQR_JEXTSEL_T3TRGO +# define ADC4_JEXTSEL_T3CC1 ADC34_JSQR_JEXTSEL_T3CC1 +# define ADC4_JEXTSEL_T3CC2 ADC34_JSQR_JEXTSEL_T3CC2 +# define ADC4_JEXTSEL_T3CC3 ADC34_JSQR_JEXTSEL_T3CC3 +# define ADC4_JEXTSEL_T3CC4 ADC34_JSQR_JEXTSEL_T3CC4 +# define ADC4_JEXTSEL_T3TRGO ADC34_JSQR_JEXTSEL_T3TRGO +# define ADC1_JEXTSEL_T4CC1 ADC12_JSQR_JEXTSEL_T4CC1 +# define ADC1_JEXTSEL_T4CC2 ADC12_JSQR_JEXTSEL_T4CC2 +# define ADC1_JEXTSEL_T4CC3 ADC12_JSQR_JEXTSEL_T4CC3 +# define ADC1_JEXTSEL_T4CC4 ADC12_JSQR_JEXTSEL_T4CC4 +# define ADC1_JEXTSEL_T4TRGO ADC12_JSQR_JEXTSEL_T4TRGO +# define ADC2_JEXTSEL_T4CC1 ADC12_JSQR_JEXTSEL_T4CC1 +# define ADC2_JEXTSEL_T4CC2 ADC12_JSQR_JEXTSEL_T4CC2 +# define ADC2_JEXTSEL_T4CC3 ADC12_JSQR_JEXTSEL_T4CC3 +# define ADC2_JEXTSEL_T4CC4 ADC12_JSQR_JEXTSEL_T4CC4 +# define ADC2_JEXTSEL_T4TRGO ADC12_JSQR_JEXTSEL_T4TRGO +# define ADC3_JEXTSEL_T4CC1 ADC34_JSQR_JEXTSEL_T4CC1 +# define ADC3_JEXTSEL_T4CC2 ADC34_JSQR_JEXTSEL_T4CC2 +# define ADC3_JEXTSEL_T4CC3 ADC34_JSQR_JEXTSEL_T4CC3 +# define ADC3_JEXTSEL_T4CC4 ADC34_JSQR_JEXTSEL_T4CC4 +# define ADC3_JEXTSEL_T4TRGO ADC34_JSQR_JEXTSEL_T4TRGO +# define ADC4_JEXTSEL_T4CC1 ADC34_JSQR_JEXTSEL_T4CC1 +# define ADC4_JEXTSEL_T4CC2 ADC34_JSQR_JEXTSEL_T4CC2 +# define ADC4_JEXTSEL_T4CC3 ADC34_JSQR_JEXTSEL_T4CC3 +# define ADC4_JEXTSEL_T4CC4 ADC34_JSQR_JEXTSEL_T4CC4 +# define ADC4_JEXTSEL_T4TRGO ADC34_JSQR_JEXTSEL_T4TRGO +# define ADC1_JEXTSEL_T5CC1 ADC12_JSQR_JEXTSEL_T5CC1 +# define ADC1_JEXTSEL_T5CC2 ADC12_JSQR_JEXTSEL_T5CC2 +# define ADC1_JEXTSEL_T5CC3 ADC12_JSQR_JEXTSEL_T5CC3 +# define ADC1_JEXTSEL_T5CC4 ADC12_JSQR_JEXTSEL_T5CC4 +# define ADC1_JEXTSEL_T5TRGO ADC12_JSQR_JEXTSEL_T5TRGO +# define ADC2_JEXTSEL_T5CC1 ADC12_JSQR_JEXTSEL_T5CC1 +# define ADC2_JEXTSEL_T5CC2 ADC12_JSQR_JEXTSEL_T5CC2 +# define ADC2_JEXTSEL_T5CC3 ADC12_JSQR_JEXTSEL_T5CC3 +# define ADC2_JEXTSEL_T5CC4 ADC12_JSQR_JEXTSEL_T5CC4 +# define ADC2_JEXTSEL_T5TRGO ADC12_JSQR_JEXTSEL_T5TRGO +# define ADC3_JEXTSEL_T5CC1 ADC34_JSQR_JEXTSEL_T5CC1 +# define ADC3_JEXTSEL_T5CC2 ADC34_JSQR_JEXTSEL_T5CC2 +# define ADC3_JEXTSEL_T5CC3 ADC34_JSQR_JEXTSEL_T5CC3 +# define ADC3_JEXTSEL_T5CC4 ADC34_JSQR_JEXTSEL_T5CC4 +# define ADC3_JEXTSEL_T5TRGO ADC34_JSQR_JEXTSEL_T5TRGO +# define ADC4_JEXTSEL_T5CC1 ADC34_JSQR_JEXTSEL_T5CC1 +# define ADC4_JEXTSEL_T5CC2 ADC34_JSQR_JEXTSEL_T5CC2 +# define ADC4_JEXTSEL_T5CC3 ADC34_JSQR_JEXTSEL_T5CC3 +# define ADC4_JEXTSEL_T5CC4 ADC34_JSQR_JEXTSEL_T5CC4 +# define ADC4_JEXTSEL_T5TRGO ADC34_JSQR_JEXTSEL_T5TRGO +# define ADC1_JEXTSEL_T6CC1 ADC12_JSQR_JEXTSEL_T6CC1 +# define ADC1_JEXTSEL_T6CC2 ADC12_JSQR_JEXTSEL_T6CC2 +# define ADC1_JEXTSEL_T6CC3 ADC12_JSQR_JEXTSEL_T6CC3 +# define ADC1_JEXTSEL_T6CC4 ADC12_JSQR_JEXTSEL_T6CC4 +# define ADC1_JEXTSEL_T6TRGO ADC12_JSQR_JEXTSEL_T6TRGO +# define ADC2_JEXTSEL_T6CC1 ADC12_JSQR_JEXTSEL_T6CC1 +# define ADC2_JEXTSEL_T6CC2 ADC12_JSQR_JEXTSEL_T6CC2 +# define ADC2_JEXTSEL_T6CC3 ADC12_JSQR_JEXTSEL_T6CC3 +# define ADC2_JEXTSEL_T6CC4 ADC12_JSQR_JEXTSEL_T6CC4 +# define ADC2_JEXTSEL_T6TRGO ADC12_JSQR_JEXTSEL_T6TRGO +# define ADC3_JEXTSEL_T6CC1 ADC34_JSQR_JEXTSEL_T6CC1 +# define ADC3_JEXTSEL_T6CC2 ADC34_JSQR_JEXTSEL_T6CC2 +# define ADC3_JEXTSEL_T6CC3 ADC34_JSQR_JEXTSEL_T6CC3 +# define ADC3_JEXTSEL_T6CC4 ADC34_JSQR_JEXTSEL_T6CC4 +# define ADC3_JEXTSEL_T6TRGO ADC34_JSQR_JEXTSEL_T6TRGO +# define ADC4_JEXTSEL_T6CC1 ADC34_JSQR_JEXTSEL_T6CC1 +# define ADC4_JEXTSEL_T6CC2 ADC34_JSQR_JEXTSEL_T6CC2 +# define ADC4_JEXTSEL_T6CC3 ADC34_JSQR_JEXTSEL_T6CC3 +# define ADC4_JEXTSEL_T6CC4 ADC34_JSQR_JEXTSEL_T6CC4 +# define ADC4_JEXTSEL_T6TRGO ADC34_JSQR_JEXTSEL_T6TRGO +# define ADC1_JEXTSEL_T7CC1 ADC12_JSQR_JEXTSEL_T7CC1 +# define ADC1_JEXTSEL_T7CC2 ADC12_JSQR_JEXTSEL_T7CC2 +# define ADC1_JEXTSEL_T7CC3 ADC12_JSQR_JEXTSEL_T7CC3 +# define ADC1_JEXTSEL_T7CC4 ADC12_JSQR_JEXTSEL_T7CC4 +# define ADC1_JEXTSEL_T7TRGO ADC12_JSQR_JEXTSEL_T7TRGO +# define ADC2_JEXTSEL_T7CC1 ADC12_JSQR_JEXTSEL_T7CC1 +# define ADC2_JEXTSEL_T7CC2 ADC12_JSQR_JEXTSEL_T7CC2 +# define ADC2_JEXTSEL_T7CC3 ADC12_JSQR_JEXTSEL_T7CC3 +# define ADC2_JEXTSEL_T7CC4 ADC12_JSQR_JEXTSEL_T7CC4 +# define ADC2_JEXTSEL_T7TRGO ADC12_JSQR_JEXTSEL_T7TRGO +# define ADC3_JEXTSEL_T7CC1 ADC34_JSQR_JEXTSEL_T7CC1 +# define ADC3_JEXTSEL_T7CC2 ADC34_JSQR_JEXTSEL_T7CC2 +# define ADC3_JEXTSEL_T7CC3 ADC34_JSQR_JEXTSEL_T7CC3 +# define ADC3_JEXTSEL_T7CC4 ADC34_JSQR_JEXTSEL_T7CC4 +# define ADC3_JEXTSEL_T7TRGO ADC34_JSQR_JEXTSEL_T7TRGO +# define ADC4_JEXTSEL_T7CC1 ADC34_JSQR_JEXTSEL_T7CC1 +# define ADC4_JEXTSEL_T7CC2 ADC34_JSQR_JEXTSEL_T7CC2 +# define ADC4_JEXTSEL_T7CC3 ADC34_JSQR_JEXTSEL_T7CC3 +# define ADC4_JEXTSEL_T7CC4 ADC34_JSQR_JEXTSEL_T7CC4 +# define ADC4_JEXTSEL_T7TRGO ADC34_JSQR_JEXTSEL_T7TRGO +# define ADC1_JEXTSEL_T8CC1 ADC12_JSQR_JEXTSEL_T8CC1 +# define ADC1_JEXTSEL_T8CC2 ADC12_JSQR_JEXTSEL_T8CC2 +# define ADC1_JEXTSEL_T8CC3 ADC12_JSQR_JEXTSEL_T8CC3 +# define ADC1_JEXTSEL_T8CC4 ADC12_JSQR_JEXTSEL_T8CC4 +# define ADC1_JEXTSEL_T8TRGO ADC12_JSQR_JEXTSEL_T8TRGO +# define ADC2_JEXTSEL_T8CC1 ADC12_JSQR_JEXTSEL_T8CC1 +# define ADC2_JEXTSEL_T8CC2 ADC12_JSQR_JEXTSEL_T8CC2 +# define ADC2_JEXTSEL_T8CC3 ADC12_JSQR_JEXTSEL_T8CC3 +# define ADC2_JEXTSEL_T8CC4 ADC12_JSQR_JEXTSEL_T8CC4 +# define ADC2_JEXTSEL_T8TRGO ADC12_JSQR_JEXTSEL_T8TRGO +# define ADC3_JEXTSEL_T8CC1 ADC34_JSQR_JEXTSEL_T8CC1 +# define ADC3_JEXTSEL_T8CC2 ADC34_JSQR_JEXTSEL_T8CC2 +# define ADC3_JEXTSEL_T8CC3 ADC34_JSQR_JEXTSEL_T8CC3 +# define ADC3_JEXTSEL_T8CC4 ADC34_JSQR_JEXTSEL_T8CC4 +# define ADC3_JEXTSEL_T8TRGO ADC34_JSQR_JEXTSEL_T8TRGO +# define ADC4_JEXTSEL_T8CC1 ADC34_JSQR_JEXTSEL_T8CC1 +# define ADC4_JEXTSEL_T8CC2 ADC34_JSQR_JEXTSEL_T8CC2 +# define ADC4_JEXTSEL_T8CC3 ADC34_JSQR_JEXTSEL_T8CC3 +# define ADC4_JEXTSEL_T8CC4 ADC34_JSQR_JEXTSEL_T8CC4 +# define ADC4_JEXTSEL_T8TRGO ADC34_JSQR_JEXTSEL_T8TRGO +# define ADC1_JEXTSEL_T9CC1 ADC12_JSQR_JEXTSEL_T9CC1 +# define ADC1_JEXTSEL_T9CC2 ADC12_JSQR_JEXTSEL_T9CC2 +# define ADC1_JEXTSEL_T9CC3 ADC12_JSQR_JEXTSEL_T9CC3 +# define ADC1_JEXTSEL_T9CC4 ADC12_JSQR_JEXTSEL_T9CC4 +# define ADC1_JEXTSEL_T9TRGO ADC12_JSQR_JEXTSEL_T9TRGO +# define ADC2_JEXTSEL_T9CC1 ADC12_JSQR_JEXTSEL_T9CC1 +# define ADC2_JEXTSEL_T9CC2 ADC12_JSQR_JEXTSEL_T9CC2 +# define ADC2_JEXTSEL_T9CC3 ADC12_JSQR_JEXTSEL_T9CC3 +# define ADC2_JEXTSEL_T9CC4 ADC12_JSQR_JEXTSEL_T9CC4 +# define ADC2_JEXTSEL_T9TRGO ADC12_JSQR_JEXTSEL_T9TRGO +# define ADC3_JEXTSEL_T9CC1 ADC34_JSQR_JEXTSEL_T9CC1 +# define ADC3_JEXTSEL_T9CC2 ADC34_JSQR_JEXTSEL_T9CC2 +# define ADC3_JEXTSEL_T9CC3 ADC34_JSQR_JEXTSEL_T9CC3 +# define ADC3_JEXTSEL_T9CC4 ADC34_JSQR_JEXTSEL_T9CC4 +# define ADC3_JEXTSEL_T9TRGO ADC34_JSQR_JEXTSEL_T9TRGO +# define ADC4_JEXTSEL_T9CC1 ADC34_JSQR_JEXTSEL_T9CC1 +# define ADC4_JEXTSEL_T9CC2 ADC34_JSQR_JEXTSEL_T9CC2 +# define ADC4_JEXTSEL_T9CC3 ADC34_JSQR_JEXTSEL_T9CC3 +# define ADC4_JEXTSEL_T9CC4 ADC34_JSQR_JEXTSEL_T9CC4 +# define ADC4_JEXTSEL_T9TRGO ADC34_JSQR_JEXTSEL_T9TRGO +# define ADC1_JEXTSEL_T10CC1 ADC12_JSQR_JEXTSEL_T10CC1 +# define ADC1_JEXTSEL_T10CC2 ADC12_JSQR_JEXTSEL_T10CC2 +# define ADC1_JEXTSEL_T10CC3 ADC12_JSQR_JEXTSEL_T10CC3 +# define ADC1_JEXTSEL_T10CC4 ADC12_JSQR_JEXTSEL_T10CC4 +# define ADC1_JEXTSEL_T10TRGO ADC12_JSQR_JEXTSEL_T10TRGO +# define ADC2_JEXTSEL_T10CC1 ADC12_JSQR_JEXTSEL_T10CC1 +# define ADC2_JEXTSEL_T10CC2 ADC12_JSQR_JEXTSEL_T10CC2 +# define ADC2_JEXTSEL_T10CC3 ADC12_JSQR_JEXTSEL_T10CC3 +# define ADC2_JEXTSEL_T10CC4 ADC12_JSQR_JEXTSEL_T10CC4 +# define ADC2_JEXTSEL_T10TRGO ADC12_JSQR_JEXTSEL_T10TRGO +# define ADC3_JEXTSEL_T10CC1 ADC34_JSQR_JEXTSEL_T10CC1 +# define ADC3_JEXTSEL_T10CC2 ADC34_JSQR_JEXTSEL_T10CC2 +# define ADC3_JEXTSEL_T10CC3 ADC34_JSQR_JEXTSEL_T10CC3 +# define ADC3_JEXTSEL_T10CC4 ADC34_JSQR_JEXTSEL_T10CC4 +# define ADC3_JEXTSEL_T10TRGO ADC34_JSQR_JEXTSEL_T10TRGO +# define ADC4_JEXTSEL_T10CC1 ADC34_JSQR_JEXTSEL_T10CC1 +# define ADC4_JEXTSEL_T10CC2 ADC34_JSQR_JEXTSEL_T10CC2 +# define ADC4_JEXTSEL_T10CC3 ADC34_JSQR_JEXTSEL_T10CC3 +# define ADC4_JEXTSEL_T10CC4 ADC34_JSQR_JEXTSEL_T10CC4 +# define ADC4_JEXTSEL_T10TRGO ADC34_JSQR_JEXTSEL_T10TRGO +# define ADC1_JEXTSEL_T15CC1 ADC12_JSQR_JEXTSEL_T15CC1 +# define ADC1_JEXTSEL_T15CC2 ADC12_JSQR_JEXTSEL_T15CC2 +# define ADC1_JEXTSEL_T15CC3 ADC12_JSQR_JEXTSEL_T15CC3 +# define ADC1_JEXTSEL_T15CC4 ADC12_JSQR_JEXTSEL_T15CC4 +# define ADC1_JEXTSEL_T15TRGO ADC12_JSQR_JEXTSEL_T15TRGO +# define ADC2_JEXTSEL_T15CC1 ADC12_JSQR_JEXTSEL_T15CC1 +# define ADC2_JEXTSEL_T15CC2 ADC12_JSQR_JEXTSEL_T15CC2 +# define ADC2_JEXTSEL_T15CC3 ADC12_JSQR_JEXTSEL_T15CC3 +# define ADC2_JEXTSEL_T15CC4 ADC12_JSQR_JEXTSEL_T15CC4 +# define ADC2_JEXTSEL_T15TRGO ADC12_JSQR_JEXTSEL_T15TRGO +# define ADC3_JEXTSEL_T15CC1 ADC34_JSQR_JEXTSEL_T15CC1 +# define ADC3_JEXTSEL_T15CC2 ADC34_JSQR_JEXTSEL_T15CC2 +# define ADC3_JEXTSEL_T15CC3 ADC34_JSQR_JEXTSEL_T15CC3 +# define ADC3_JEXTSEL_T15CC4 ADC34_JSQR_JEXTSEL_T15CC4 +# define ADC3_JEXTSEL_T15TRGO ADC34_JSQR_JEXTSEL_T15TRGO +# define ADC4_JEXTSEL_T15CC1 ADC34_JSQR_JEXTSEL_T15CC1 +# define ADC4_JEXTSEL_T15CC2 ADC34_JSQR_JEXTSEL_T15CC2 +# define ADC4_JEXTSEL_T15CC3 ADC34_JSQR_JEXTSEL_T15CC3 +# define ADC4_JEXTSEL_T15CC4 ADC34_JSQR_JEXTSEL_T15CC4 +# define ADC4_JEXTSEL_T15TRGO ADC34_JSQR_JEXTSEL_T15TRGO +# define ADC1_JEXTSEL_T20CC1 ADC12_JSQR_JEXTSEL_T20CC1 +# define ADC1_JEXTSEL_T20CC2 ADC12_JSQR_JEXTSEL_T20CC2 +# define ADC1_JEXTSEL_T20CC3 ADC12_JSQR_JEXTSEL_T20CC3 +# define ADC1_JEXTSEL_T20CC4 ADC12_JSQR_JEXTSEL_T20CC4 +# define ADC1_JEXTSEL_T20TRGO ADC12_JSQR_JEXTSEL_T20TRGO +# define ADC2_JEXTSEL_T20CC1 ADC12_JSQR_JEXTSEL_T20CC1 +# define ADC2_JEXTSEL_T20CC2 ADC12_JSQR_JEXTSEL_T20CC2 +# define ADC2_JEXTSEL_T20CC3 ADC12_JSQR_JEXTSEL_T20CC3 +# define ADC2_JEXTSEL_T20CC4 ADC12_JSQR_JEXTSEL_T20CC4 +# define ADC2_JEXTSEL_T20TRGO ADC12_JSQR_JEXTSEL_T20TRGO +# define ADC3_JEXTSEL_T20CC1 ADC34_JSQR_JEXTSEL_T20CC1 +# define ADC3_JEXTSEL_T20CC2 ADC34_JSQR_JEXTSEL_T20CC2 +# define ADC3_JEXTSEL_T20CC3 ADC34_JSQR_JEXTSEL_T20CC3 +# define ADC3_JEXTSEL_T20CC4 ADC34_JSQR_JEXTSEL_T20CC4 +# define ADC3_JEXTSEL_T20TRGO ADC34_JSQR_JEXTSEL_T20TRGO +# define ADC4_JEXTSEL_T20CC1 ADC34_JSQR_JEXTSEL_T20CC1 +# define ADC4_JEXTSEL_T20CC2 ADC34_JSQR_JEXTSEL_T20CC2 +# define ADC4_JEXTSEL_T20CC3 ADC34_JSQR_JEXTSEL_T20CC3 +# define ADC4_JEXTSEL_T20CC4 ADC34_JSQR_JEXTSEL_T20CC4 +# define ADC4_JEXTSEL_T20TRGO ADC34_JSQR_JEXTSEL_T20TRGO +# define ADC1_JEXTSEL_HRTTRG2 ADC12_JSQR_JEXTSEL_HRT1TRG2 +# define ADC1_JEXTSEL_HRTTRG4 ADC12_JSQR_JEXTSEL_HRT1TRG4 +# define ADC2_JEXTSEL_HRTTRG2 ADC12_JSQR_JEXTSEL_HRT1TRG2 +# define ADC2_JEXTSEL_HRTTRG4 ADC12_JSQR_JEXTSEL_HRT1TRG4 +#endif + +/* EXTSEL configuration *****************************************************/ + +/* NOTE: + * this configuration if used only if CONFIG_STM32_TIMx_ADCy is selected. + * You can still connect the ADC with a timer trigger using the + * CONFIG_STM32_ADCx_EXTSEL option. + */ + +#if defined(CONFIG_STM32_TIM1_ADC1) +# if CONFIG_STM32_ADC1_TIMTRIG == 0 +# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T1CC1 +# elif CONFIG_STM32_ADC1_TIMTRIG == 1 +# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T1CC2 +# elif CONFIG_STM32_ADC1_TIMTRIG == 2 +# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T1CC3 +# elif CONFIG_STM32_ADC1_TIMTRIG == 3 +# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T1CC4 +# elif CONFIG_STM32_ADC1_TIMTRIG == 4 +# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T1TRGO +# elif CONFIG_STM32_ADC1_TIMTRIG == 5 +# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T1TRGO2 +# else +# error "CONFIG_STM32_ADC1_TIMTRIG is out of range" +# endif +#elif defined(CONFIG_STM32_TIM2_ADC1) +# if CONFIG_STM32_ADC1_TIMTRIG == 0 +# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T2CC1 +# elif CONFIG_STM32_ADC1_TIMTRIG == 1 +# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T2CC2 +# elif CONFIG_STM32_ADC1_TIMTRIG == 2 +# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T2CC3 +# elif CONFIG_STM32_ADC1_TIMTRIG == 3 +# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T2CC4 +# elif CONFIG_STM32_ADC1_TIMTRIG == 4 +# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T2TRGO +# else +# error "CONFIG_STM32_ADC1_TIMTRIG is out of range" +# endif +#elif defined(CONFIG_STM32_TIM3_ADC1) +# if CONFIG_STM32_ADC1_TIMTRIG == 0 +# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T3CC1 +# elif CONFIG_STM32_ADC1_TIMTRIG == 1 +# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T3CC2 +# elif CONFIG_STM32_ADC1_TIMTRIG == 2 +# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T3CC3 +# elif CONFIG_STM32_ADC1_TIMTRIG == 3 +# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T3CC4 +# elif CONFIG_STM32_ADC1_TIMTRIG == 4 +# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T3TRGO +# else +# error "CONFIG_STM32_ADC1_TIMTRIG is out of range" +# endif +#elif defined(CONFIG_STM32_TIM4_ADC1) +# if CONFIG_STM32_ADC1_TIMTRIG == 0 +# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T4CC1 +# elif CONFIG_STM32_ADC1_TIMTRIG == 1 +# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T4CC2 +# elif CONFIG_STM32_ADC1_TIMTRIG == 2 +# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T4CC3 +# elif CONFIG_STM32_ADC1_TIMTRIG == 3 +# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T4CC4 +# elif CONFIG_STM32_ADC1_TIMTRIG == 4 +# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T4TRGO +# else +# error "CONFIG_STM32_ADC1_TIMTRIG is out of range" +# endif +#elif defined(CONFIG_STM32_TIM5_ADC1) +# if CONFIG_STM32_ADC1_TIMTRIG == 0 +# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T5CC1 +# elif CONFIG_STM32_ADC1_TIMTRIG == 1 +# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T5CC2 +# elif CONFIG_STM32_ADC1_TIMTRIG == 2 +# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T5CC3 +# elif CONFIG_STM32_ADC1_TIMTRIG == 3 +# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T5CC4 +# elif CONFIG_STM32_ADC1_TIMTRIG == 4 +# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T5TRGO +# else +# error "CONFIG_STM32_ADC1_TIMTRIG is out of range" +# endif +#elif defined(CONFIG_STM32_TIM6_ADC1) +# if CONFIG_STM32_ADC1_TIMTRIG == 0 +# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T6CC1 +# elif CONFIG_STM32_ADC1_TIMTRIG == 1 +# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T6CC2 +# elif CONFIG_STM32_ADC1_TIMTRIG == 2 +# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T6CC3 +# elif CONFIG_STM32_ADC1_TIMTRIG == 3 +# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T6CC4 +# elif CONFIG_STM32_ADC1_TIMTRIG == 4 +# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T6TRGO +# else +# error "CONFIG_STM32_ADC1_TIMTRIG is out of range" +# endif +#elif defined(CONFIG_STM32_TIM7_ADC1) +# if CONFIG_STM32_ADC1_TIMTRIG == 0 +# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T7CC1 +# elif CONFIG_STM32_ADC1_TIMTRIG == 1 +# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T7CC2 +# elif CONFIG_STM32_ADC1_TIMTRIG == 2 +# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T7CC3 +# elif CONFIG_STM32_ADC1_TIMTRIG == 3 +# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T7CC4 +# elif CONFIG_STM32_ADC1_TIMTRIG == 4 +# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T7TRGO +# else +# error "CONFIG_STM32_ADC1_TIMTRIG is out of range" +# endif +#elif defined(CONFIG_STM32_TIM8_ADC1) +# if CONFIG_STM32_ADC1_TIMTRIG == 0 +# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T8CC1 +# elif CONFIG_STM32_ADC1_TIMTRIG == 1 +# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T8CC2 +# elif CONFIG_STM32_ADC1_TIMTRIG == 2 +# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T8CC3 +# elif CONFIG_STM32_ADC1_TIMTRIG == 3 +# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T8CC4 +# elif CONFIG_STM32_ADC1_TIMTRIG == 4 +# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T8TRGO +# elif CONFIG_STM32_ADC1_TIMTRIG == 5 +# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T8TRGO2 +# else +# error "CONFIG_STM32_ADC1_TIMTRIG is out of range" +# endif +#elif defined(CONFIG_STM32_TIM9_ADC1) +# if CONFIG_STM32_ADC1_TIMTRIG == 0 +# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T9CC1 +# elif CONFIG_STM32_ADC1_TIMTRIG == 1 +# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T9CC2 +# elif CONFIG_STM32_ADC1_TIMTRIG == 2 +# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T9CC3 +# elif CONFIG_STM32_ADC1_TIMTRIG == 3 +# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T9CC4 +# elif CONFIG_STM32_ADC1_TIMTRIG == 4 +# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T9TRGO +# else +# error "CONFIG_STM32_ADC1_TIMTRIG is out of range" +# endif +#elif defined(CONFIG_STM32_TIM10_ADC1) +# if CONFIG_STM32_ADC1_TIMTRIG == 0 +# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T10CC1 +# elif CONFIG_STM32_ADC1_TIMTRIG == 1 +# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T10CC2 +# elif CONFIG_STM32_ADC1_TIMTRIG == 2 +# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T10CC3 +# elif CONFIG_STM32_ADC1_TIMTRIG == 3 +# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T10CC4 +# elif CONFIG_STM32_ADC1_TIMTRIG == 4 +# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T10TRGO +# else +# error "CONFIG_STM32_ADC1_TIMTRIG is out of range" +# endif +#elif defined(CONFIG_STM32_TIM15_ADC1) +# if CONFIG_STM32_ADC1_TIMTRIG == 0 +# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T15CC1 +# elif CONFIG_STM32_ADC1_TIMTRIG == 1 +# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T15CC2 +# elif CONFIG_STM32_ADC1_TIMTRIG == 2 +# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T15CC3 +# elif CONFIG_STM32_ADC1_TIMTRIG == 3 +# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T15CC4 +# elif CONFIG_STM32_ADC1_TIMTRIG == 4 +# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T15TRGO +# else +# error "CONFIG_STM32_ADC1_TIMTRIG is out of range" +# endif +#elif defined(CONFIG_STM32_HRTIM_ADC1_TRG1) +# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_HRTTRG1 +#elif defined(CONFIG_STM32_HRTIM_ADC1_TRG3) +# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_HRTTRG3 +#endif + +#if defined(CONFIG_STM32_TIM1_ADC2) +# if CONFIG_STM32_ADC2_TIMTRIG == 0 +# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T1CC1 +# elif CONFIG_STM32_ADC2_TIMTRIG == 1 +# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T1CC2 +# elif CONFIG_STM32_ADC2_TIMTRIG == 2 +# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T1CC3 +# elif CONFIG_STM32_ADC2_TIMTRIG == 3 +# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T1CC4 +# elif CONFIG_STM32_ADC2_TIMTRIG == 4 +# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T1TRGO +# elif CONFIG_STM32_ADC2_TIMTRIG == 5 +# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T1TRGO2 +# else +# error "CONFIG_STM32_ADC2_TIMTRIG is out of range" +# endif +#elif defined(CONFIG_STM32_TIM2_ADC2) +# if CONFIG_STM32_ADC2_TIMTRIG == 0 +# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T2CC1 +# elif CONFIG_STM32_ADC2_TIMTRIG == 1 +# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T2CC2 +# elif CONFIG_STM32_ADC2_TIMTRIG == 2 +# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T2CC3 +# elif CONFIG_STM32_ADC2_TIMTRIG == 3 +# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T2CC4 +# elif CONFIG_STM32_ADC2_TIMTRIG == 4 +# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T2TRGO +# else +# error "CONFIG_STM32_ADC2_TIMTRIG is out of range" +# endif +#elif defined(CONFIG_STM32_TIM3_ADC2) +# if CONFIG_STM32_ADC2_TIMTRIG == 0 +# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T3CC1 +# elif CONFIG_STM32_ADC2_TIMTRIG == 1 +# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T3CC2 +# elif CONFIG_STM32_ADC2_TIMTRIG == 2 +# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T3CC3 +# elif CONFIG_STM32_ADC2_TIMTRIG == 3 +# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T3CC4 +# elif CONFIG_STM32_ADC2_TIMTRIG == 4 +# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T3TRGO +# else +# error "CONFIG_STM32_ADC2_TIMTRIG is out of range" +# endif +#elif defined(CONFIG_STM32_TIM4_ADC2) +# if CONFIG_STM32_ADC2_TIMTRIG == 0 +# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T4CC1 +# elif CONFIG_STM32_ADC2_TIMTRIG == 1 +# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T4CC2 +# elif CONFIG_STM32_ADC2_TIMTRIG == 2 +# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T4CC3 +# elif CONFIG_STM32_ADC2_TIMTRIG == 3 +# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T4CC4 +# elif CONFIG_STM32_ADC2_TIMTRIG == 4 +# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T4TRGO +# else +# error "CONFIG_STM32_ADC2_TIMTRIG is out of range" +# endif +#elif defined(CONFIG_STM32_TIM5_ADC2) +# if CONFIG_STM32_ADC2_TIMTRIG == 0 +# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T5CC1 +# elif CONFIG_STM32_ADC2_TIMTRIG == 1 +# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T5CC2 +# elif CONFIG_STM32_ADC2_TIMTRIG == 2 +# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T5CC3 +# elif CONFIG_STM32_ADC2_TIMTRIG == 3 +# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T5CC4 +# elif CONFIG_STM32_ADC2_TIMTRIG == 4 +# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T5TRGO +# else +# error "CONFIG_STM32_ADC2_TIMTRIG is out of range" +# endif +#elif defined(CONFIG_STM32_TIM6_ADC2) +# if CONFIG_STM32_ADC2_TIMTRIG == 0 +# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T6CC1 +# elif CONFIG_STM32_ADC2_TIMTRIG == 1 +# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T6CC2 +# elif CONFIG_STM32_ADC2_TIMTRIG == 2 +# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T6CC3 +# elif CONFIG_STM32_ADC2_TIMTRIG == 3 +# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T6CC4 +# elif CONFIG_STM32_ADC2_TIMTRIG == 4 +# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T6TRGO +# else +# error "CONFIG_STM32_ADC2_TIMTRIG is out of range" +# endif +#elif defined(CONFIG_STM32_TIM8_ADC2) +# if CONFIG_STM32_ADC2_TIMTRIG == 0 +# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T8CC1 +# elif CONFIG_STM32_ADC2_TIMTRIG == 1 +# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T8CC2 +# elif CONFIG_STM32_ADC2_TIMTRIG == 2 +# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T8CC3 +# elif CONFIG_STM32_ADC2_TIMTRIG == 3 +# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T8CC4 +# elif CONFIG_STM32_ADC2_TIMTRIG == 4 +# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T8TRGO +# elif CONFIG_STM32_ADC2_TIMTRIG == 5 +# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T8TRGO2 +# else +# error "CONFIG_STM32_ADC2_TIMTRIG is out of range" +# endif +#elif defined(CONFIG_STM32_TIM15_ADC2) +# if CONFIG_STM32_ADC2_TIMTRIG == 0 +# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T15CC1 +# elif CONFIG_STM32_ADC2_TIMTRIG == 1 +# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T15CC2 +# elif CONFIG_STM32_ADC2_TIMTRIG == 2 +# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T15CC3 +# elif CONFIG_STM32_ADC2_TIMTRIG == 3 +# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T15CC4 +# elif CONFIG_STM32_ADC2_TIMTRIG == 4 +# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T15TRGO +# else +# error "CONFIG_STM32_ADC2_TIMTRIG is out of range" +# endif +#elif defined(CONFIG_STM32_HRTIM_ADC2_TRG1) +# define ADC2_EXTSEL_VALUE ADC1_EXTSEL_HRTTRG1 +#elif defined(CONFIG_STM32_HRTIM_ADC1_TRG3) +# define ADC2_EXTSEL_VALUE ADC1_EXTSEL_HRTTRG3 +#endif + +#if defined(CONFIG_STM32_TIM1_ADC3) +# if CONFIG_STM32_ADC3_TIMTRIG == 0 +# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T1CC1 +# elif CONFIG_STM32_ADC3_TIMTRIG == 1 +# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T1CC2 +# elif CONFIG_STM32_ADC3_TIMTRIG == 2 +# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T1CC3 +# elif CONFIG_STM32_ADC3_TIMTRIG == 3 +# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T1CC4 +# elif CONFIG_STM32_ADC3_TIMTRIG == 4 +# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T1TRGO +# elif CONFIG_STM32_ADC3_TIMTRIG == 5 +# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T1TRGO2 +# else +# error "CONFIG_STM32_ADC3_TIMTRIG is out of range" +# endif +#elif defined(CONFIG_STM32_TIM2_ADC3) +# if CONFIG_STM32_ADC3_TIMTRIG == 0 +# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T2CC1 +# elif CONFIG_STM32_ADC3_TIMTRIG == 1 +# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T2CC2 +# elif CONFIG_STM32_ADC3_TIMTRIG == 2 +# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T2CC3 +# elif CONFIG_STM32_ADC3_TIMTRIG == 3 +# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T2CC4 +# elif CONFIG_STM32_ADC3_TIMTRIG == 4 +# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T2TRGO +# else +# error "CONFIG_STM32_ADC3_TIMTRIG is out of range" +# endif +#elif defined(CONFIG_STM32_TIM3_ADC3) +# if CONFIG_STM32_ADC3_TIMTRIG == 0 +# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T3CC1 +# elif CONFIG_STM32_ADC3_TIMTRIG == 1 +# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T3CC2 +# elif CONFIG_STM32_ADC3_TIMTRIG == 2 +# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T3CC3 +# elif CONFIG_STM32_ADC3_TIMTRIG == 3 +# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T3CC4 +# elif CONFIG_STM32_ADC3_TIMTRIG == 4 +# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T3TRGO +# else +# error "CONFIG_STM32_ADC3_TIMTRIG is out of range" +# endif +#elif defined(CONFIG_STM32_TIM4_ADC3) +# if CONFIG_STM32_ADC3_TIMTRIG == 0 +# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T4CC1 +# elif CONFIG_STM32_ADC3_TIMTRIG == 1 +# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T4CC2 +# elif CONFIG_STM32_ADC3_TIMTRIG == 2 +# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T4CC3 +# elif CONFIG_STM32_ADC3_TIMTRIG == 3 +# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T4CC4 +# elif CONFIG_STM32_ADC3_TIMTRIG == 4 +# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T4TRGO +# else +# error "CONFIG_STM32_ADC3_TIMTRIG is out of range" +# endif +#elif defined(CONFIG_STM32_TIM5_ADC3) +# if CONFIG_STM32_ADC3_TIMTRIG == 0 +# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T5CC1 +# elif CONFIG_STM32_ADC3_TIMTRIG == 1 +# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T5CC2 +# elif CONFIG_STM32_ADC3_TIMTRIG == 2 +# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T5CC3 +# elif CONFIG_STM32_ADC3_TIMTRIG == 3 +# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T5CC4 +# elif CONFIG_STM32_ADC3_TIMTRIG == 4 +# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T5TRGO +# else +# error "CONFIG_STM32_ADC3_TIMTRIG is out of range" +# endif +#elif defined(CONFIG_STM32_TIM7_ADC3) +# if CONFIG_STM32_ADC3_TIMTRIG == 0 +# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T7CC1 +# elif CONFIG_STM32_ADC3_TIMTRIG == 1 +# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T7CC2 +# elif CONFIG_STM32_ADC3_TIMTRIG == 2 +# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T7CC3 +# elif CONFIG_STM32_ADC3_TIMTRIG == 3 +# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T7CC4 +# elif CONFIG_STM32_ADC3_TIMTRIG == 4 +# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T7TRGO +# else +# error "CONFIG_STM32_ADC3_TIMTRIG is out of range" +# endif +#elif defined(CONFIG_STM32_TIM8_ADC3) +# if CONFIG_STM32_ADC3_TIMTRIG == 0 +# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T8CC1 +# elif CONFIG_STM32_ADC3_TIMTRIG == 1 +# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T8CC2 +# elif CONFIG_STM32_ADC3_TIMTRIG == 2 +# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T8CC3 +# elif CONFIG_STM32_ADC3_TIMTRIG == 3 +# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T8CC4 +# elif CONFIG_STM32_ADC3_TIMTRIG == 4 +# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T8TRGO +# elif CONFIG_STM32_ADC3_TIMTRIG == 5 +# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T8TRGO2 +# else +# error "CONFIG_STM32_ADC3_TIMTRIG is out of range" +# endif +#elif defined(CONFIG_STM32_TIM15_ADC3) +# if CONFIG_STM32_ADC3_TIMTRIG == 0 +# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T15CC1 +# elif CONFIG_STM32_ADC3_TIMTRIG == 1 +# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T15CC2 +# elif CONFIG_STM32_ADC3_TIMTRIG == 2 +# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T15CC3 +# elif CONFIG_STM32_ADC3_TIMTRIG == 3 +# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T15CC4 +# elif CONFIG_STM32_ADC3_TIMTRIG == 4 +# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T15TRGO +# else +# error "CONFIG_STM32_ADC3_TIMTRIG is out of range" +# endif +#elif defined(CONFIG_STM32_TIM20_ADC3) +# if CONFIG_STM32_ADC3_TIMTRIG == 0 +# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T20CC1 +# elif CONFIG_STM32_ADC3_TIMTRIG == 1 +# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T20CC2 +# elif CONFIG_STM32_ADC3_TIMTRIG == 2 +# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T20CC3 +# elif CONFIG_STM32_ADC3_TIMTRIG == 3 +# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T20CC4 +# elif CONFIG_STM32_ADC3_TIMTRIG == 4 +# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T20TRGO +# else +# error "CONFIG_STM32_ADC3_TIMTRIG is out of range" +# endif +#endif + +#if defined(CONFIG_STM32_TIM1_ADC4) +# if CONFIG_STM32_ADC4_TIMTRIG == 0 +# define ADC4_EXTSEL_VALUE ADC4_EXTSEL_T1CC1 +# elif CONFIG_STM32_ADC4_TIMTRIG == 1 +# define ADC4_EXTSEL_VALUE ADC4_EXTSEL_T1CC2 +# elif CONFIG_STM32_ADC4_TIMTRIG == 2 +# define ADC4_EXTSEL_VALUE ADC4_EXTSEL_T1CC3 +# elif CONFIG_STM32_ADC4_TIMTRIG == 3 +# define ADC4_EXTSEL_VALUE ADC4_EXTSEL_T1CC4 +# elif CONFIG_STM32_ADC4_TIMTRIG == 4 +# define ADC4_EXTSEL_VALUE ADC4_EXTSEL_T1TRGO +# elif CONFIG_STM32_ADC4_TIMTRIG == 5 +# define ADC4_EXTSEL_VALUE ADC4_EXTSEL_T1TRGO2 +# else +# error "CONFIG_STM32_ADC4_TIMTRIG is out of range" +# endif +#elif defined(CONFIG_STM32_TIM2_ADC4) +# if CONFIG_STM32_ADC4_TIMTRIG == 0 +# define ADC4_EXTSEL_VALUE ADC4_EXTSEL_T2CC1 +# elif CONFIG_STM32_ADC4_TIMTRIG == 1 +# define ADC4_EXTSEL_VALUE ADC4_EXTSEL_T2CC2 +# elif CONFIG_STM32_ADC4_TIMTRIG == 2 +# define ADC4_EXTSEL_VALUE ADC4_EXTSEL_T2CC3 +# elif CONFIG_STM32_ADC4_TIMTRIG == 3 +# define ADC4_EXTSEL_VALUE ADC4_EXTSEL_T2CC4 +# elif CONFIG_STM32_ADC4_TIMTRIG == 4 +# define ADC4_EXTSEL_VALUE ADC4_EXTSEL_T2TRGO +# else +# error "CONFIG_STM32_ADC4_TIMTRIG is out of range" +# endif +#elif defined(CONFIG_STM32_TIM3_ADC4) +# if CONFIG_STM32_ADC4_TIMTRIG == 0 +# define ADC4_EXTSEL_VALUE ADC4_EXTSEL_T3CC1 +# elif CONFIG_STM32_ADC4_TIMTRIG == 1 +# define ADC4_EXTSEL_VALUE ADC4_EXTSEL_T3CC2 +# elif CONFIG_STM32_ADC4_TIMTRIG == 2 +# define ADC4_EXTSEL_VALUE ADC4_EXTSEL_T3CC3 +# elif CONFIG_STM32_ADC4_TIMTRIG == 3 +# define ADC4_EXTSEL_VALUE ADC4_EXTSEL_T3CC4 +# elif CONFIG_STM32_ADC4_TIMTRIG == 4 +# define ADC4_EXTSEL_VALUE ADC4_EXTSEL_T3TRGO +# else +# error "CONFIG_STM32_ADC4_TIMTRIG is out of range" +# endif +#elif defined(CONFIG_STM32_TIM4_ADC4) +# if CONFIG_STM32_ADC4_TIMTRIG == 0 +# define ADC4_EXTSEL_VALUE ADC4_EXTSEL_T4CC1 +# elif CONFIG_STM32_ADC4_TIMTRIG == 1 +# define ADC4_EXTSEL_VALUE ADC4_EXTSEL_T4CC2 +# elif CONFIG_STM32_ADC4_TIMTRIG == 2 +# define ADC4_EXTSEL_VALUE ADC4_EXTSEL_T4CC3 +# elif CONFIG_STM32_ADC4_TIMTRIG == 3 +# define ADC4_EXTSEL_VALUE ADC4_EXTSEL_T4CC4 +# elif CONFIG_STM32_ADC4_TIMTRIG == 4 +# define ADC4_EXTSEL_VALUE ADC4_EXTSEL_T4TRGO +# else +# error "CONFIG_STM32_ADC4_TIMTRIG is out of range" +# endif +#elif defined(CONFIG_STM32_TIM5_ADC4) +# if CONFIG_STM32_ADC4_TIMTRIG == 0 +# define ADC4_EXTSEL_VALUE ADC4_EXTSEL_T5CC1 +# elif CONFIG_STM32_ADC4_TIMTRIG == 1 +# define ADC4_EXTSEL_VALUE ADC4_EXTSEL_T5CC2 +# elif CONFIG_STM32_ADC4_TIMTRIG == 2 +# define ADC4_EXTSEL_VALUE ADC4_EXTSEL_T5CC3 +# elif CONFIG_STM32_ADC4_TIMTRIG == 3 +# define ADC4_EXTSEL_VALUE ADC4_EXTSEL_T5CC4 +# elif CONFIG_STM32_ADC4_TIMTRIG == 4 +# define ADC4_EXTSEL_VALUE ADC4_EXTSEL_T5TRGO +# else +# error "CONFIG_STM32_ADC4_TIMTRIG is out of range" +# endif +#elif defined(CONFIG_STM32_TIM7_ADC4) +# if CONFIG_STM32_ADC4_TIMTRIG == 0 +# define ADC4_EXTSEL_VALUE ADC4_EXTSEL_T7CC1 +# elif CONFIG_STM32_ADC4_TIMTRIG == 1 +# define ADC4_EXTSEL_VALUE ADC4_EXTSEL_T7CC2 +# elif CONFIG_STM32_ADC4_TIMTRIG == 2 +# define ADC4_EXTSEL_VALUE ADC4_EXTSEL_T7CC3 +# elif CONFIG_STM32_ADC4_TIMTRIG == 3 +# define ADC4_EXTSEL_VALUE ADC4_EXTSEL_T7CC4 +# elif CONFIG_STM32_ADC4_TIMTRIG == 4 +# define ADC4_EXTSEL_VALUE ADC4_EXTSEL_T7TRGO +# else +# error "CONFIG_STM32_ADC4_TIMTRIG is out of range" +# endif +#elif defined(CONFIG_STM32_TIM8_ADC4) +# if CONFIG_STM32_ADC4_TIMTRIG == 0 +# define ADC4_EXTSEL_VALUE ADC4_EXTSEL_T8CC1 +# elif CONFIG_STM32_ADC4_TIMTRIG == 1 +# define ADC4_EXTSEL_VALUE ADC4_EXTSEL_T8CC2 +# elif CONFIG_STM32_ADC4_TIMTRIG == 2 +# define ADC4_EXTSEL_VALUE ADC4_EXTSEL_T8CC3 +# elif CONFIG_STM32_ADC4_TIMTRIG == 3 +# define ADC4_EXTSEL_VALUE ADC4_EXTSEL_T8CC4 +# elif CONFIG_STM32_ADC4_TIMTRIG == 4 +# define ADC4_EXTSEL_VALUE ADC4_EXTSEL_T8TRGO +# elif CONFIG_STM32_ADC4_TIMTRIG == 5 +# define ADC4_EXTSEL_VALUE ADC4_EXTSEL_T8TRGO2 +# else +# error "CONFIG_STM32_ADC4_TIMTRIG is out of range" +# endif +#elif defined(CONFIG_STM32_TIM15_ADC4) +# if CONFIG_STM32_ADC4_TIMTRIG == 0 +# define ADC4_EXTSEL_VALUE ADC4_EXTSEL_T15CC1 +# elif CONFIG_STM32_ADC4_TIMTRIG == 1 +# define ADC4_EXTSEL_VALUE ADC4_EXTSEL_T15CC2 +# elif CONFIG_STM32_ADC4_TIMTRIG == 2 +# define ADC4_EXTSEL_VALUE ADC4_EXTSEL_T15CC3 +# elif CONFIG_STM32_ADC4_TIMTRIG == 3 +# define ADC4_EXTSEL_VALUE ADC4_EXTSEL_T15CC4 +# elif CONFIG_STM32_ADC4_TIMTRIG == 4 +# define ADC4_EXTSEL_VALUE ADC4_EXTSEL_T15TRGO +# else +# error "CONFIG_STM32_ADC4_TIMTRIG is out of range" +# endif +#elif defined(CONFIG_STM32_TIM20_ADC4) +# if CONFIG_STM32_ADC4_TIMTRIG == 0 +# define ADC4_EXTSEL_VALUE ADC4_EXTSEL_T20CC1 +# elif CONFIG_STM32_ADC4_TIMTRIG == 1 +# define ADC4_EXTSEL_VALUE ADC4_EXTSEL_T20CC2 +# elif CONFIG_STM32_ADC4_TIMTRIG == 2 +# define ADC4_EXTSEL_VALUE ADC4_EXTSEL_T20CC3 +# elif CONFIG_STM32_ADC4_TIMTRIG == 3 +# define ADC4_EXTSEL_VALUE ADC4_EXTSEL_T20CC4 +# elif CONFIG_STM32_ADC4_TIMTRIG == 4 +# define ADC4_EXTSEL_VALUE ADC4_EXTSEL_T20TRGO +# else +# error "CONFIG_STM32_ADC4_TIMTRIG is out of range" +# endif +#endif + +/* Regular channels external trigger support */ + +#ifdef ADC1_EXTSEL_VALUE +# define ADC1_HAVE_EXTCFG 1 +# define ADC1_EXTCFG_VALUE (ADC1_EXTSEL_VALUE | ADC_EXTREG_EXTEN_DEFAULT) +#elif defined(CONFIG_STM32_ADC1_EXTSEL) +# define ADC1_HAVE_EXTCFG 1 +# define ADC1_EXTCFG_VALUE 0 +#else +# undef ADC1_HAVE_EXTCFG +#endif +#ifdef ADC2_EXTSEL_VALUE +# define ADC2_HAVE_EXTCFG 1 +# define ADC2_EXTCFG_VALUE (ADC2_EXTSEL_VALUE | ADC_EXTREG_EXTEN_DEFAULT) +#elif defined(CONFIG_STM32_ADC2_EXTSEL) +# define ADC2_HAVE_EXTCFG 1 +# define ADC2_EXTCFG_VALUE 0 +#else +# undef ADC2_HAVE_EXTCFG +#endif +#ifdef ADC3_EXTSEL_VALUE +# define ADC3_HAVE_EXTCFG 1 +# define ADC3_EXTCFG_VALUE (ADC3_EXTSEL_VALUE | ADC_EXTREG_EXTEN_DEFAULT) +#elif defined(CONFIG_STM32_ADC3_EXTSEL) +# define ADC3_HAVE_EXTCFG 1 +# define ADC3_EXTCFG_VALUE 0 +#else +# undef ADC3_HAVE_EXTCFG +#endif +#ifdef ADC4_EXTSEL_VALUE +# define ADC4_HAVE_EXTCFG 1 +# define ADC4_EXTCFG_VALUE (ADC4_EXTSEL_VALUE | ADC_EXTREG_EXTEN_DEFAULT) +#elif defined(CONFIG_STM32_ADC4_EXTSEL) +# define ADC4_HAVE_EXTCFG 1 +# define ADC4_EXTCFG_VALUE 0 +#else +# undef ADC4_HAVE_EXTCFG +#endif + +#if defined(ADC1_HAVE_EXTCFG) || defined(ADC2_HAVE_EXTCFG) || \ + defined(ADC3_HAVE_EXTCFG) || defined(ADC3_HAVE_EXTCFG) +# define ADC_HAVE_EXTCFG +#endif + +/* JEXTSEL configuration ****************************************************/ + +/* There is no automatic timer tirgger configuration from Kconfig for + * injected channels conversion. + */ + +/* ADC1 HRTIM JEXTSEL trigger */ + +#if defined(CONFIG_STM32_HRTIM_ADC1_TRG2) +# define ADC1_JEXTSEL_VALUE ADC1_JEXTSEL_HRTTRG2 +#elif defined(CONFIG_STM32_HRTIM_ADC1_TRG4) +# define ADC1_JEXTSEL_VALUE ADC1_JEXTSEL_HRTTRG4 +#endif + +/* ADC1 HRTIM JEXTSEL trigger */ + +#if defined(CONFIG_STM32_HRTIM_ADC2_TRG2) +# define ADC2_JEXTSEL_VALUE ADC2_JEXTSEL_HRTTRG2 +#elif defined(CONFIG_STM32_HRTIM_ADC2_TRG4) +# define ADC2_JEXTSEL_VALUE ADC2_JEXTSEL_HRTTRG4 +#endif + +/* Injected channels external trigger support */ + +#ifdef ADC1_JEXTSEL_VALUE +# define ADC1_HAVE_JEXTCFG 1 +# define ADC1_JEXTCFG_VALUE (ADC1_JEXTSEL_VALUE | ADC_JEXTREG_JEXTEN_DEFAULT) +#elif defined(CONFIG_STM32_ADC1_JEXTSEL) +# define ADC1_HAVE_JEXTCFG 1 +# define ADC1_JEXTCFG_VALUE 0 +#else +# undef ADC1_HAVE_JEXTCFG +#endif +#ifdef ADC2_JEXTSEL_VALUE +# define ADC2_HAVE_JEXTCFG 1 +# define ADC2_JEXTCFG_VALUE (ADC2_JEXTSEL_VALUE | ADC_JEXTREG_JEXTEN_DEFAULT) +#elif defined(CONFIG_STM32_ADC2_JEXTSEL) +# define ADC2_HAVE_JEXTCFG 1 +# define ADC2_JEXTCFG_VALUE 0 +#else +# undef ADC2_HAVE_JEXTCFG +#endif +#ifdef ADC3_JEXTSEL_VALUE +# define ADC3_HAVE_JEXTCFG 1 +# define ADC3_JEXTCFG_VALUE (ADC3_JEXTSEL_VALUE | ADC_JEXTREG_JEXTEN_DEFAULT) +#elif defined(CONFIG_STM32_ADC3_JEXTSEL) +# define ADC3_HAVE_JEXTCFG 1 +# define ADC3_JEXTCFG_VALUE 0 +#else +# undef ADC3_HAVE_JEXTCFG +#endif +#ifdef ADC4_JEXTSEL_VALUE +# define ADC4_HAVE_JEXTCFG 1 +# define ADC4_JEXTCFG_VALUE (ADC4_JEXTSEL_VALUE | ADC_JEXTREG_JEXTEN_DEFAULT) +#elif defined(CONFIG_STM32_ADC4_JEXTSEL) +# define ADC4_HAVE_JEXTCFG 1 +# define ADC4_JEXTCFG_VALUE 0 +#else +# undef ADC4_HAVE_JEXTCFG +#endif + +#if defined(ADC1_HAVE_JEXTCFG) || defined(ADC2_HAVE_JEXTCFG) || \ + defined(ADC3_HAVE_JEXTCFG) || defined(ADC4_HAVE_JEXTCFG) +# define ADC_HAVE_JEXTCFG +#endif + +/* ADC interrupts ***********************************************************/ + +#if defined(HAVE_IP_ADC_V1) +# define ADC_ISR_EOC ADC_SR_EOC +# define ADC_IER_EOC ADC_CR1_EOCIE +# define ADC_ISR_AWD ADC_SR_AWD +# define ADC_IER_AWD ADC_CR1_AWDIE +# define ADC_ISR_JEOC ADC_SR_JEOC +# define ADC_IER_JEOC ADC_CR1_JEOCIE +# define ADC_ISR_JEOS 0 /* No JEOS */ +# define ADC_IER_JEOS 0 /* No JEOS */ +# ifdef HAVE_BASIC_ADC +# define ADC_ISR_OVR 0 +# define ADC_IER_OVR 0 +# else +# define ADC_ISR_OVR ADC_SR_OVR +# define ADC_IER_OVR ADC_CR1_OVRIE +# endif +#elif defined(HAVE_IP_ADC_V2) +# define ADC_ISR_EOC ADC_INT_EOC +# define ADC_IER_EOC ADC_INT_EOC +# define ADC_ISR_AWD ADC_INT_AWD1 +# define ADC_IER_AWD ADC_INT_AWD1 +# define ADC_ISR_JEOC ADC_INT_JEOC +# define ADC_IER_JEOC ADC_INT_JEOC +# define ADC_ISR_OVR ADC_INT_OVR +# define ADC_IER_OVR ADC_INT_OVR +# define ADC_ISR_JEOS ADC_INT_JEOS +# define ADC_IER_JEOS ADC_INT_JEOS +#endif + +#define ADC_ISR_ALLINTS (ADC_ISR_EOC | ADC_ISR_AWD | ADC_ISR_JEOC | \ + ADC_ISR_JEOS | ADC_ISR_OVR) +#define ADC_IER_ALLINTS (ADC_IER_EOC | ADC_IER_AWD | ADC_IER_JEOC | \ + ADC_IER_JEOS | ADC_IER_OVR) + +/* Low-level ops helpers ****************************************************/ + +#define STM32_ADC_INT_ACK(adc, source) \ + (adc)->llops->int_ack(adc, source) +#define STM32_ADC_INT_GET(adc) \ + (adc)->llops->int_get(adc) +#define STM32_ADC_INT_ENABLE(adc, source) \ + (adc)->llops->int_en(adc, source) +#define STM32_ADC_INT_DISABLE(adc, source) \ + (adc)->llops->int_dis(adc, source) +#define STM32_ADC_REGDATA_GET(adc) \ + (adc)->llops->val_get(adc) +#define STM32_ADC_REGBUF_REGISTER(adc, buffer, len) \ + (adc)->llops->regbuf_reg(adc, buffer, len) +#define STM32_ADC_REG_STARTCONV(adc, state) \ + (adc)->llops->reg_startconv(adc, state) +#define STM32_ADC_OFFSET_SET(adc, ch, i, o) \ + (adc)->llops->offset_set(adc, ch, i, o) +#define STM32_ADC_EXTCFG_SET(adc, c) \ + (adc)->llops->extcfg_set(adc, c) +#define STM32_ADC_INJ_STARTCONV(adc, state) \ + (adc)->llops->inj_startconv(adc, state) +#define STM32_ADC_INJDATA_GET(adc, chan) \ + (adc)->llops->inj_get(adc, chan) +#define STM32_ADC_JEXTCFG_SET(adc, c) \ + (adc)->llops->jextcfg_set(adc, c) +#define STM32_ADC_SAMPLETIME_SET(adc, time_samples) \ + (adc)->llops->stime_set(adc, time_samples) +#define STM32_ADC_SAMPLETIME_WRITE(adc) \ + (adc)->llops->stime_write(adc) +#define STM32_ADC_DUMP_REGS(adc) \ + (adc)->llops->dump_regs(adc) +#define STM32_ADC_SETUP(adc) \ + (adc)->llops->setup(adc) +#define STM32_ADC_SHUTDOWN(adc) \ + (adc)->llops->shutdown(adc) +#define STM32_ADC_MULTICFG(adc, mode) \ + (adc)->llops->multi_cfg(adc, mode) +#define STM32_ADC_ENABLE(adc, en) \ + (adc)->llops->enable(adc, en) + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/* On STM32F42xx and STM32F43xx devices,VBAT and temperature sensor are + * connected to the same ADC internal channel (ADC1_IN18). + * Only one conversion, either temperature sensor or VBAT, must be selected + * at a time. When both conversion are enabled simultaneously, + * only the VBAT conversion is performed. + */ + +enum adc_io_cmds_e +{ +#if defined(HAVE_IP_ADC_V1) + IO_ENABLE_TEMPER_VOLT_CH, +#endif +#ifdef HAVE_ADC_VBAT + IO_ENABLE_DISABLE_VBAT_CH, +#endif + IO_ENABLE_DISABLE_AWDIE, + IO_ENABLE_DISABLE_EOCIE, + IO_ENABLE_DISABLE_JEOCIE, + IO_ENABLE_DISABLE_OVRIE, + IO_ENABLE_DISABLE_ALL_INTS, + IO_STOP_ADC, + IO_START_ADC, + IO_START_CONV, + IO_TRIGGER_REG, +#ifdef ADC_HAVE_INJECTED + IO_TRIGGER_INJ, +#endif +#ifdef HAVE_ADC_POWERDOWN + IO_ENABLE_DISABLE_PDI, + IO_ENABLE_DISABLE_PDD, + IO_ENABLE_DISABLE_PDD_PDI +#endif +}; + +/* ADC resolution can be reduced in order to perform faster conversion */ + +enum stm32_adc_resoluton_e +{ + ADC_RESOLUTION_12BIT = 0, /* 12 bit */ + ADC_RESOLUTION_10BIT = 1, /* 10 bit */ + ADC_RESOLUTION_8BIT = 2, /* 8 bit */ + ADC_RESOLUTION_6BIT = 3 /* 6 bit */ +}; + +/* ADC multi mode selection */ + +enum stm32_adc_multimode_e +{ + /* Independent mode */ + + ADC_MULTIMODE_INDEP = 0, /* Independent mode */ + + /* Dual mode */ + + ADC_MULTIMODE_RSISM2 = 1, /* Dual combined regular sim. + injected sim. */ + ADC_MULTIMODE_RSATM2 = 2, /* Dual combined regular sim. + alternate trigger */ + ADC_MULTIMODE_IMIS2 = 3, /* Dual combined interl. mode + injected sim. */ + ADC_MULTIMODE_ISM2 = 4, /* Dual injected simultaneous mode only */ + ADC_MULTIMODE_RSM2 = 5, /* Dual degular simultaneous mode only */ + ADC_MULTIMODE_IM2 = 6, /* Dual interleaved mode only */ + ADC_MULTIMODE_ATM2 = 7, /* Dual alternate trigger mode only */ + + /* Triple mode */ + + ADC_MULTIMODE_RSISM3 = 8, /* Triple combined regular sim. + injected sim. */ + ADC_MULTIMODE_RSATM3 = 9, /* Triple combined regular sim. + alternate trigger */ + ADC_MULTIMODE_IMIS3 = 10, /* Triple combined interl. mode + injected sim. */ + ADC_MULTIMODE_ISM3 = 11, /* Triple injected simultaneous mode only */ + ADC_MULTIMODE_RSM3 = 12, /* Triple degular simultaneous mode only */ + ADC_MULTIMODE_IM3 = 13, /* Triple interleaved mode only */ + ADC_MULTIMODE_ATM3 = 14, /* Triple alternate trigger mode only */ +}; + +#ifdef CONFIG_STM32_ADC_LL_OPS + +#ifdef CONFIG_STM32_ADC_CHANGE_SAMPLETIME + +/* Channel and sample time pair */ + +typedef struct adc_channel_s +{ + uint8_t channel:5; + + /* Sampling time individually for each channel. + * It differs between families + */ + + uint8_t sample_time:3; +} adc_channel_t; + +/* This structure will be used while setting channels to specified by the + * "channel-sample time" pairs' values + */ + +struct adc_sample_time_s +{ + adc_channel_t *channel; /* Array of channels */ + uint8_t channels_nbr:5; /* Number of channels in array */ + bool all_same:1; /* All channels will get the + * same value of the sample time */ + uint8_t all_ch_sample_time:3; /* Sample time for all channels */ +}; +#endif /* CONFIG_STM32_ADC_CHANGE_SAMPLETIME */ + +/* This structure provides the publicly visible representation of the + * "lower-half" ADC driver structure. + */ + +struct stm32_adc_dev_s +{ + /* Publicly visible portion of the "lower-half" ADC driver structure */ + + const struct stm32_adc_ops_s *llops; + + /* Require cast-compatibility with private "lower-half" ADC structure */ +}; + +/* Low-level operations for ADC */ + +struct stm32_adc_ops_s +{ + /* Low-level ADC setup */ + + int (*setup)(struct stm32_adc_dev_s *dev); + + /* Low-level ADC shutdown */ + + void (*shutdown)(struct stm32_adc_dev_s *dev); + + /* Acknowledge interrupts */ + + void (*int_ack)(struct stm32_adc_dev_s *dev, uint32_t source); + + /* Get pending interrupts */ + + uint32_t (*int_get)(struct stm32_adc_dev_s *dev); + + /* Enable interrupts */ + + void (*int_en)(struct stm32_adc_dev_s *dev, uint32_t source); + + /* Disable interrupts */ + + void (*int_dis)(struct stm32_adc_dev_s *dev, uint32_t source); + + /* Get current ADC data register */ + + uint32_t (*val_get)(struct stm32_adc_dev_s *dev); + + /* Register buffer for ADC DMA transfer */ + + int (*regbuf_reg)(struct stm32_adc_dev_s *dev, + uint16_t *buffer, uint8_t len); + + /* Start/stop regular conversion */ + + void (*reg_startconv)(struct stm32_adc_dev_s *dev, bool state); + + /* Set offset for channel */ + + int (*offset_set)(struct stm32_adc_dev_s *dev, uint8_t ch, uint8_t i, + uint16_t offset); + +#ifdef ADC_HAVE_EXTCFG + /* Configure the ADC external trigger for regular conversion */ + + void (*extcfg_set)(struct stm32_adc_dev_s *dev, uint32_t extcfg); +#endif + +#ifdef ADC_HAVE_JEXTCFG + /* Configure the ADC external trigger for injected conversion */ + + void (*jextcfg_set)(struct stm32_adc_dev_s *dev, uint32_t jextcfg); +#endif + +#ifdef ADC_HAVE_INJECTED + /* Get current ADC injected data register */ + + uint32_t (*inj_get)(struct stm32_adc_dev_s *dev, uint8_t chan); + + /* Start/stop injected conversion */ + + void (*inj_startconv)(struct stm32_adc_dev_s *dev, bool state); +#endif + +#ifdef CONFIG_STM32_ADC_CHANGE_SAMPLETIME + /* Set ADC sample time */ + + void (*stime_set)(struct stm32_adc_dev_s *dev, + struct adc_sample_time_s *time_samples); + + /* Write ADC sample time */ + + void (*stime_write)(struct stm32_adc_dev_s *dev); +#endif + + void (*dump_regs)(struct stm32_adc_dev_s *dev); + + /* Configure ADC multi mode */ + + int (*multi_cfg)(struct stm32_adc_dev_s *dev, uint8_t mode); + + /* Enable/disable ADC */ + + void (*enable)(struct stm32_adc_dev_s *dev, bool enable); +}; + +#endif /* CONFIG_STM32_ADC_LL_OPS */ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#ifndef __ASSEMBLY__ +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Name: stm32_adcinitialize + * + * Description: + * Initialize the ADC. See stm32_adc.c for more details. + * + * Input Parameters: + * intf - Could be {1,2,3,4} for ADC1, ADC2, ADC3 or ADC4 + * chanlist - The list of channels (regular + injected) + * nchannels - Number of channels (regular + injected) + * + * Returned Value: + * Valid ADC device structure reference on success; a NULL on failure + * + ****************************************************************************/ + +struct adc_dev_s; +struct adc_dev_s *stm32_adcinitialize(int intf, const uint8_t *chanlist, + int channels); + +#undef EXTERN +#ifdef __cplusplus +} +#endif +#endif /* __ASSEMBLY__ */ + +#endif /* CONFIG_STM32_ADC1 || CONFIG_STM32_ADC2 || + * CONFIG_STM32_ADC3 || CONFIG_STM32_ADC4 + */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_ADC_V1V2_H */ diff --git a/arch/arm/src/common/stm32/stm32_aes.h b/arch/arm/src/common/stm32/stm32_aes.h new file mode 100644 index 0000000000000..8e0a90c4424a5 --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_aes.h @@ -0,0 +1,58 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_aes.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_AES_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_AES_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include "chip.h" + +#if defined(CONFIG_STM32_HAVE_IP_AES_M0_V1) +# include "hardware/stm32_aes.h" +#elif defined(CONFIG_STM32_HAVE_IP_AES_M3M4_V1) +# ifdef CONFIG_STM32_STM32L15XX +# include "hardware/stm32l15xxx_aes.h" +# else +# error "Unknown chip for AES" +# endif +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/**************************************************************************** + * Inline Functions + ****************************************************************************/ + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_AES_H */ diff --git a/arch/arm/src/common/stm32/stm32_aes_m0_v1.c b/arch/arm/src/common/stm32/stm32_aes_m0_v1.c new file mode 100644 index 0000000000000..4348d1c4f0bb6 --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_aes_m0_v1.c @@ -0,0 +1,322 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_aes_m0_v1.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include "arm_internal.h" +#include "chip.h" +#include "stm32_rcc.h" +#include "stm32_aes.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define AES_BLOCK_SIZE 16 + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +static void stm32aes_enable(bool on); +static void stm32aes_ccfc(void); +static void stm32aes_setkey(const void *key, size_t key_len); +static void stm32aes_setiv(const void *iv); +static void stm32aes_encryptblock(void *block_out, + const void *block_in); +static int stm32aes_setup_cr(int mode, int encrypt); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static mutex_t g_stm32aes_lock = NXMUTEX_INITIALIZER; +static bool g_stm32aes_initdone = false; + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +static void stm32aes_enable(bool on) +{ + uint32_t regval; + + regval = getreg32(STM32_AES_CR); + if (on) + { + regval |= AES_CR_EN; + } + else + { + regval &= ~AES_CR_EN; + } + + putreg32(regval, STM32_AES_CR); +} + +/* Clear AES_SR_CCF status register bit */ + +static void stm32aes_ccfc(void) +{ + uint32_t regval; + + regval = getreg32(STM32_AES_CR); + regval |= AES_CR_CCFC; + putreg32(regval, STM32_AES_CR); +} + +/* TODO: Handle other AES key lengths or fail if length is not valid */ + +static void stm32aes_setkey(const void *key, size_t key_len) +{ + uint32_t *in = (uint32_t *)key; + + putreg32(__builtin_bswap32(*in), STM32_AES_KEYR3); + in++; + putreg32(__builtin_bswap32(*in), STM32_AES_KEYR2); + in++; + putreg32(__builtin_bswap32(*in), STM32_AES_KEYR1); + in++; + putreg32(__builtin_bswap32(*in), STM32_AES_KEYR0); +} + +static void stm32aes_setiv(const void *iv) +{ + uint32_t *in = (uint32_t *)iv; + + putreg32(__builtin_bswap32(*in), STM32_AES_IVR3); + in++; + putreg32(__builtin_bswap32(*in), STM32_AES_IVR2); + in++; + putreg32(__builtin_bswap32(*in), STM32_AES_IVR1); + in++; + putreg32(__builtin_bswap32(*in), STM32_AES_IVR0); +} + +static void stm32aes_encryptblock(void *block_out, + const void *block_in) +{ + uint32_t *in = (uint32_t *)block_in; + uint32_t *out = (uint32_t *)block_out; + + putreg32(*in, STM32_AES_DINR); + in++; + putreg32(*in, STM32_AES_DINR); + in++; + putreg32(*in, STM32_AES_DINR); + in++; + putreg32(*in, STM32_AES_DINR); + + while (!(getreg32(STM32_AES_SR) & AES_SR_CCF)); + stm32aes_ccfc(); + + *out = getreg32(STM32_AES_DOUTR); + out++; + *out = getreg32(STM32_AES_DOUTR); + out++; + *out = getreg32(STM32_AES_DOUTR); + out++; + *out = getreg32(STM32_AES_DOUTR); +} + +static int stm32aes_setup_cr(int mode, int encrypt) +{ + uint32_t regval = 0; + + regval |= AES_CR_DATATYPE_BE; + + switch (mode) + { + case AES_MODE_ECB: + regval |= AES_CR_CHMOD_ECB; + break; + + case AES_MODE_CBC: + regval |= AES_CR_CHMOD_CBC; + break; + + case AES_MODE_CTR: + regval |= AES_CR_CHMOD_CTR; + break; + + default: + return -EINVAL; + } + + if (encrypt) + { + regval |= AES_CR_MODE_ENCRYPT; + } + else + { + if (mode == AES_MODE_CTR) + { + regval |= AES_CR_MODE_DECRYPT; + } + else + { + regval |= AES_CR_MODE_DECRYPT_KEYDERIV; + } + } + + putreg32(regval, STM32_AES_CR); + return OK; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +int stm32_aesreset(void) +{ + irqstate_t flags; + uint32_t regval; + + flags = enter_critical_section(); + + regval = getreg32(STM32_RCC_AHBRSTR); + regval |= RCC_AHBRSTR_AESRST; + putreg32(regval, STM32_RCC_AHBRSTR); + regval &= ~RCC_AHBRSTR_AESRST; + putreg32(regval, STM32_RCC_AHBRSTR); + + leave_critical_section(flags); + + return OK; +} + +int stm32_aesinitialize(void) +{ + uint32_t regval; + + regval = getreg32(STM32_RCC_AHBENR); + regval |= RCC_AHBENR_AESEN; + putreg32(regval, STM32_RCC_AHBENR); + + stm32aes_enable(false); + + return OK; +} + +int stm32_aesuninitialize(void) +{ + uint32_t regval; + + stm32aes_enable(false); + + regval = getreg32(STM32_RCC_AHBENR); + regval &= ~RCC_AHBENR_AESEN; + putreg32(regval, STM32_RCC_AHBENR); + + return OK; +} + +int aes_cypher(void *out, const void *in, size_t size, + const void *iv, const void *key, size_t keysize, + int mode, int encrypt) +{ + int ret = OK; + + /* Ensure initialization was done */ + + if (!g_stm32aes_initdone) + { + ret = stm32_aesinitialize(); + if (ret < 0) + { + return ret; /* AES init failed */ + } + + g_stm32aes_initdone = true; + } + + if ((size & (AES_BLOCK_SIZE - 1)) != 0) + { + return -EINVAL; + } + + if (keysize != 16) + { + return -EINVAL; + } + + ret = nxmutex_lock(&g_stm32aes_lock); + if (ret < 0) + { + return ret; + } + + /* AES must be disabled before changing mode, key or IV. */ + + stm32aes_enable(false); + ret = stm32aes_setup_cr(mode, encrypt); + if (ret < 0) + { + goto out; + } + + stm32aes_setkey(key, keysize); + if (iv != NULL) + { + stm32aes_setiv(iv); + } + + stm32aes_enable(true); + while (size) + { + stm32aes_encryptblock(out, in); + out = (uint8_t *)out + AES_BLOCK_SIZE; + in = (uint8_t *)in + AES_BLOCK_SIZE; + size -= AES_BLOCK_SIZE; + } + + stm32aes_enable(false); + +out: + nxmutex_unlock(&g_stm32aes_lock); + return ret; +} diff --git a/arch/arm/src/common/stm32/stm32_aes_m3m4_v1.c b/arch/arm/src/common/stm32/stm32_aes_m3m4_v1.c new file mode 100644 index 0000000000000..96ff3b7cbf660 --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_aes_m3m4_v1.c @@ -0,0 +1,322 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_aes_m3m4_v1.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include "arm_internal.h" +#include "chip.h" +#include "stm32_rcc.h" +#include "stm32_aes.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define AES_BLOCK_SIZE 16 + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +static void stm32aes_enable(bool on); +static void stm32aes_ccfc(void); +static void stm32aes_setkey(const void *key, size_t key_len); +static void stm32aes_setiv(const void *iv); +static void stm32aes_encryptblock(void *block_out, + const void *block_in); +static int stm32aes_setup_cr(int mode, int encrypt); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static mutex_t g_stm32aes_lock = NXMUTEX_INITIALIZER; +static bool g_stm32aes_initdone = false; + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +static void stm32aes_enable(bool on) +{ + uint32_t regval; + + regval = getreg32(STM32_AES_CR); + if (on) + { + regval |= AES_CR_EN; + } + else + { + regval &= ~AES_CR_EN; + } + + putreg32(regval, STM32_AES_CR); +} + +/* Clear AES_SR_CCF status register bit */ + +static void stm32aes_ccfc(void) +{ + uint32_t regval; + + regval = getreg32(STM32_AES_CR); + regval |= AES_CR_CCFC; + putreg32(regval, STM32_AES_CR); +} + +/* TODO: Handle other AES key lengths or fail if length is not valid */ + +static void stm32aes_setkey(const void *key, size_t key_len) +{ + uint32_t *in = (uint32_t *)key; + + putreg32(__builtin_bswap32(*in), STM32_AES_KEYR3); + in++; + putreg32(__builtin_bswap32(*in), STM32_AES_KEYR2); + in++; + putreg32(__builtin_bswap32(*in), STM32_AES_KEYR1); + in++; + putreg32(__builtin_bswap32(*in), STM32_AES_KEYR0); +} + +static void stm32aes_setiv(const void *iv) +{ + uint32_t *in = (uint32_t *)iv; + + putreg32(__builtin_bswap32(*in), STM32_AES_IVR3); + in++; + putreg32(__builtin_bswap32(*in), STM32_AES_IVR2); + in++; + putreg32(__builtin_bswap32(*in), STM32_AES_IVR1); + in++; + putreg32(__builtin_bswap32(*in), STM32_AES_IVR0); +} + +static void stm32aes_encryptblock(void *block_out, + const void *block_in) +{ + uint32_t *in = (uint32_t *)block_in; + uint32_t *out = (uint32_t *)block_out; + + putreg32(*in, STM32_AES_DINR); + in++; + putreg32(*in, STM32_AES_DINR); + in++; + putreg32(*in, STM32_AES_DINR); + in++; + putreg32(*in, STM32_AES_DINR); + + while (!(getreg32(STM32_AES_SR) & AES_SR_CCF)); + stm32aes_ccfc(); + + *out = getreg32(STM32_AES_DOUTR); + out++; + *out = getreg32(STM32_AES_DOUTR); + out++; + *out = getreg32(STM32_AES_DOUTR); + out++; + *out = getreg32(STM32_AES_DOUTR); +} + +static int stm32aes_setup_cr(int mode, int encrypt) +{ + uint32_t regval = 0; + + regval |= AES_CR_DATATYPE_BE; + + switch (mode) + { + case AES_MODE_ECB: + regval |= AES_CR_CHMOD_ECB; + break; + + case AES_MODE_CBC: + regval |= AES_CR_CHMOD_CBC; + break; + + case AES_MODE_CTR: + regval |= AES_CR_CHMOD_CTR; + break; + + default: + return -EINVAL; + } + + if (encrypt) + { + regval |= AES_CR_MODE_ENCRYPT; + } + else + { + if (mode == AES_MODE_CTR) + { + regval |= AES_CR_MODE_DECRYPT; + } + else + { + regval |= AES_CR_MODE_DECRYPT_KEYDERIV; + } + } + + putreg32(regval, STM32_AES_CR); + return OK; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +int stm32_aesreset(void) +{ + irqstate_t flags; + uint32_t regval; + + flags = enter_critical_section(); + + regval = getreg32(STM32_RCC_AHBRSTR); + regval |= RCC_AHBRSTR_AESRST; + putreg32(regval, STM32_RCC_AHBRSTR); + regval &= ~RCC_AHBRSTR_AESRST; + putreg32(regval, STM32_RCC_AHBRSTR); + + leave_critical_section(flags); + + return OK; +} + +int stm32_aesinitialize(void) +{ + uint32_t regval; + + regval = getreg32(STM32_RCC_AHBENR); + regval |= RCC_AHBENR_AESEN; + putreg32(regval, STM32_RCC_AHBENR); + + stm32aes_enable(false); + + return OK; +} + +int stm32_aesuninitialize(void) +{ + uint32_t regval; + + stm32aes_enable(false); + + regval = getreg32(STM32_RCC_AHBENR); + regval &= ~RCC_AHBENR_AESEN; + putreg32(regval, STM32_RCC_AHBENR); + + return OK; +} + +int aes_cypher(void *out, const void *in, size_t size, + const void *iv, const void *key, size_t keysize, + int mode, int encrypt) +{ + int ret = OK; + + /* Ensure initialization was done */ + + if (!g_stm32aes_initdone) + { + ret = stm32_aesinitialize(); + if (ret < 0) + { + return ret; /* AES init failed */ + } + + g_stm32aes_initdone = true; + } + + if ((size & (AES_BLOCK_SIZE - 1)) != 0) + { + return -EINVAL; + } + + if (keysize != 16) + { + return -EINVAL; + } + + ret = nxmutex_lock(&g_stm32aes_lock); + if (ret < 0) + { + return ret; + } + + /* AES must be disabled before changing mode, key or IV. */ + + stm32aes_enable(false); + ret = stm32aes_setup_cr(mode, encrypt); + if (ret < 0) + { + goto out; + } + + stm32aes_setkey(key, keysize); + if (iv != NULL) + { + stm32aes_setiv(iv); + } + + stm32aes_enable(true); + while (size) + { + stm32aes_encryptblock(out, in); + out = (uint8_t *)out + AES_BLOCK_SIZE; + in = (uint8_t *)in + AES_BLOCK_SIZE; + size -= AES_BLOCK_SIZE; + } + + stm32aes_enable(false); + +out: + nxmutex_unlock(&g_stm32aes_lock); + return ret; +} diff --git a/arch/arm/src/stm32/stm32_alarm.h b/arch/arm/src/common/stm32/stm32_alarm.h similarity index 94% rename from arch/arm/src/stm32/stm32_alarm.h rename to arch/arm/src/common/stm32/stm32_alarm.h index 2660dfd8a059e..0d192e8e847c1 100644 --- a/arch/arm/src/stm32/stm32_alarm.h +++ b/arch/arm/src/common/stm32/stm32_alarm.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_alarm.h + * arch/arm/src/common/stm32/stm32_alarm.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_STM32_ALARM_H -#define __ARCH_ARM_SRC_STM32_STM32_ALARM_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_ALARM_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_ALARM_H /**************************************************************************** * Included Files @@ -121,4 +121,4 @@ int stm32_rtc_rdalarm(FAR struct alm_rdalarm_s *alminfo); #endif /* __ASSEMBLY__ */ #endif /* CONFIG_RTC_ALARM */ -#endif /* __ARCH_ARM_SRC_STM32_STM32_ALARM_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_ALARM_H */ diff --git a/arch/arm/src/common/stm32/stm32_allocateheap_m3m4_v1.c b/arch/arm/src/common/stm32/stm32_allocateheap_m3m4_v1.c new file mode 100644 index 0000000000000..010ede1eeb338 --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_allocateheap_m3m4_v1.c @@ -0,0 +1,803 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_allocateheap_m3m4_v1.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include + +#include "chip.h" + +#include "mpu.h" +#include "arm_internal.h" +#include "stm32_mpuinit.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Internal SRAM is available in all members of the STM32 family. The + * following definitions must be provided to specify the size and + * location of internal(system) SRAM: + * + * CONFIG_RAM_END : End address (+1) of SRAM (F1 family only, the + * : F4 family uses the a priori end of SRAM) + * + * The F4 family also contains internal CCM SRAM. This SRAM is different + * because it cannot be used for DMA. So if DMA needed, then the following + * should be defined to exclude CCM SRAM from the heap: + * + * CONFIG_STM32_CCMEXCLUDE : Exclude CCM SRAM from the HEAP + * + * In addition to internal SRAM, external RAM may also be available through + * the FMC/FSMC. To use external RAM, the following things need to be present + * in the NuttX configuration file: + * + * CONFIG_STM32_FSMC=y : Enables the FSMC + * CONFIG_STM32_FMC=y : Enables the FMC + * CONFIG_STM32_EXTERNAL_RAM=y : Indicates external RAM is available via the + * FMC/FSMC (as opposed to an LCD or FLASH). + * CONFIG_HEAP2_BASE : The base address of the external RAM + * CONFIG_HEAP2_SIZE : The size of the external RAM + * CONFIG_MM_REGIONS : Must be set to a large enough value to + * include the external RAM (as determined by + * the rules provided below) + */ + +#if !defined(CONFIG_STM32_FSMC) && !defined(CONFIG_STM32_FMC) +# undef CONFIG_STM32_EXTERNAL_RAM +#endif + +/* The STM32L15xxx family has only internal SRAM. The heap is in one + * contiguous block starting at g_idle_topstack and extending through + * CONFIG_RAM_END. + */ + +#if defined(CONFIG_STM32_STM32L15XX) + +/* Set the end of system SRAM */ + +# define SRAM1_END CONFIG_RAM_END + +/* There is no FSMC (Other EnergyLite STM32's do have an FSMC, but not + * the STM32L15X + */ + +# undef CONFIG_STM32_EXTERNAL_RAM + +/* The STM32L EnergyLite family has no CCM SRAM */ + +# undef CONFIG_STM32_CCMEXCLUDE +# define CONFIG_STM32_CCMEXCLUDE 1 + +/* Only one memory region can be support (internal SRAM) */ + +# if CONFIG_MM_REGIONS > 1 +# error "CONFIG_MM_REGIONS > 1. The STM32L15X has only one memory region." +# endif + +/* For the STM312F10xxx family, all internal SRAM is in one contiguous + * block starting at g_idle_topstack and extending through CONFIG_RAM_END + * (my apologies for the bad naming). In addition, external FSMC SRAM + * may be available. + */ + +#elif defined(CONFIG_STM32_STM32F10XX) + +/* Set the end of system SRAM */ + +# define SRAM1_END CONFIG_RAM_END + +/* Check if external FSMC SRAM is provided */ + +# ifdef CONFIG_STM32_EXTERNAL_RAM +# if CONFIG_MM_REGIONS < 2 +# warning "FSMC SRAM not included in the heap" +# undef CONFIG_STM32_EXTERNAL_RAM +# elif CONFIG_MM_REGIONS > 2 +# error "CONFIG_MM_REGIONS > 2 but I don't know what some of the region(s) are" +# undef CONFIG_MM_REGIONS +# define CONFIG_MM_REGIONS 2 +# endif +# elif CONFIG_MM_REGIONS > 1 +# error "CONFIG_MM_REGIONS > 1 but I don't know what the other region(s) are" +# endif + +/* The STM32 F1 has no CCM SRAM */ + +# undef CONFIG_STM32_CCMEXCLUDE +# define CONFIG_STM32_CCMEXCLUDE 1 + +/* Members of the STM32F30xxx family has a variable amount of SRAM from 24 + * to 40Kb plus 8KB if CCM SRAM. No external RAM is supported (the F3 family + * has no FSMC). + * + * As a complication, CCM SRAM cannot be used for DMA. So, if STM32 DMA is + * enabled, CCM SRAM should probably be excluded from the heap. + */ + +#elif defined(CONFIG_STM32_STM32F30XX) + +/* Set the end of system SRAM */ + +# define SRAM1_END CONFIG_RAM_END + +/* Set the range of CCM SRAM as well (although we may not use it) */ + +# define SRAM2_START 0x10000000 +# define SRAM2_END 0x10002000 + +/* There is no FSMC */ + +# undef CONFIG_STM32_EXTERNAL_RAM + +/* There are 2 possible SRAM configurations: + * + * Configuration 1. System SRAM (only) + * CONFIG_MM_REGIONS == 1 + * CONFIG_STM32_CCMEXCLUDE defined + * Configuration 2. System SRAM and CCM SRAM + * CONFIG_MM_REGIONS == 2 + * CONFIG_STM32_CCMEXCLUDE NOT defined + */ + +# if CONFIG_MM_REGIONS < 2 + +/* Only one memory region. Force Configuration 1 */ + +# ifndef CONFIG_STM32_CCMEXCLUDE +# ifdef CONFIG_STM32_HAVE_CCM +# warning "CCM SRAM excluded from the heap" +# endif +# define CONFIG_STM32_CCMEXCLUDE 1 +# endif + +/* CONFIG_MM_REGIONS may be 2 if CCM SRAM is included in the head */ + +# elif CONFIG_MM_REGIONS >= 2 +# if CONFIG_MM_REGIONS > 2 +# error "No more than two memory regions can be supported (CONFIG_MM_REGIONS)" +# undef CONFIG_MM_REGIONS +# define CONFIG_MM_REGIONS 2 +# endif + +/* Two memory regions is okay if CCM SRAM is not disabled. */ + +# ifdef CONFIG_STM32_CCMEXCLUDE + +/* Configuration 1: CONFIG_MM_REGIONS should have been 2 */ + +# error "CONFIG_MM_REGIONS >= 2 but but CCM SRAM is excluded (CONFIG_STM32_CCMEXCLUDE)" +# undef CONFIG_MM_REGIONS +# define CONFIG_MM_REGIONS 1 +# else + +/* Configuration 2: DMA should be disabled */ + +# ifdef CONFIG_ARCH_DMA +# warning "CCM SRAM is included in the heap AND DMA is enabled" +# endif +# endif +# endif + +/* All members of the STM32F33xxx families have 16 Kbi ram and 4 KB CCM SRAM. + * No external RAM is supported (the F3 family has no FSMC). + * + * As a complication, CCM SRAM cannot be used for DMA. So, if STM32 DMA is + * enabled, CCM SRAM should probably be excluded from the heap. + */ +#elif defined(CONFIG_STM32_STM32F33XX) + +/* Set the end of system SRAM */ + +# define SRAM1_END CONFIG_RAM_END + +/* Set the range of CCM SRAM as well (although we may not use it) */ + +# define SRAM2_START 0x10000000 +# define SRAM2_END 0x10001000 + +/* There is no FSMC */ + +# undef CONFIG_STM32_EXTERNAL_RAM + +/* There are 2 possible SRAM configurations: + * + * Configuration 1. System SRAM (only) + * CONFIG_MM_REGIONS == 1 + * CONFIG_STM32_CCMEXCLUDE defined + * Configuration 2. System SRAM and CCM SRAM + * CONFIG_MM_REGIONS == 2 + * CONFIG_STM32_CCMEXCLUDE NOT defined + */ + +# if CONFIG_MM_REGIONS < 2 + +/* Only one memory region. Force Configuration 1 */ + +# ifndef CONFIG_STM32_CCMEXCLUDE +# ifdef CONFIG_STM32_HAVE_CCM +# warning "CCM SRAM excluded from the heap" +# endif +# define CONFIG_STM32_CCMEXCLUDE 1 +# endif + +/* CONFIG_MM_REGIONS may be 2 if CCM SRAM is included in the head */ + +# elif CONFIG_MM_REGIONS >= 2 +# if CONFIG_MM_REGIONS > 2 +# error "No more than two memory regions can be supported (CONFIG_MM_REGIONS)" +# undef CONFIG_MM_REGIONS +# define CONFIG_MM_REGIONS 2 +# endif + +/* Two memory regions is okay if CCM SRAM is not disabled. */ + +# ifdef CONFIG_STM32_CCMEXCLUDE + +/* Configuration 1: CONFIG_MM_REGIONS should have been 2 */ + +# error "CONFIG_MM_REGIONS >= 2 but but CCM SRAM is excluded (CONFIG_STM32_CCMEXCLUDE)" +# undef CONFIG_MM_REGIONS +# define CONFIG_MM_REGIONS 1 +# else + +/* Configuration 2: DMA should be disabled */ + +# ifdef CONFIG_ARCH_DMA +# warning "CCM SRAM is included in the heap AND DMA is enabled" +# endif +# endif +# endif + +/* All members of the STM32F37xxx families have 16-32 Kib ram in a single + * bank. No external RAM is supported (the F3 family has no FSMC). + */ +#elif defined(CONFIG_STM32_STM32F37XX) + +/* Set the end of system SRAM */ + +# define SRAM1_END CONFIG_RAM_END + +/* There is no FSMC */ + +# undef CONFIG_STM32_EXTERNAL_RAM + +/* The STM32 F37xx has no CCM SRAM */ + +# undef CONFIG_STM32_CCMEXCLUDE +# define CONFIG_STM32_CCMEXCLUDE 1 + +/* Only one memory region can be support (internal SRAM) */ + +# if CONFIG_MM_REGIONS > 1 +# error "CONFIG_MM_REGIONS > 1. The STM32L15X has only one memory region." +# endif + +/* Most members of both the STM32F20xxx and STM32F40xxx families have 128Kib + * in two banks: + * + * 1) 112KiB of System SRAM beginning at address 0x2000:0000 + * 2) 16KiB of System SRAM beginning at address 0x2001:c000 + * + * The STM32F401 family is an exception and has only 64KiB or 96Kib total + * on one bank: + * + * 3) 64KiB (STM32F401xB/C) or 96KiB (STM32401xD/E) of System SRAM + * beginning at address 0x2000:0000 + * + * Members of the STM32F40xxx family have an additional 64Kib of CCM RAM + * for a total of 192KB. + * + * 4) 64Kib of CCM SRAM beginning at address 0x1000:0000 + * + * The STM32F427/437/429/439 parts have another 64KiB of System SRAM for + * a total of 256KiB. + * + * 5) 64Kib of System SRAM beginning at address 0x2002:0000 + * + * As determined by the linker script, g_heapbase lies in the 112KiB memory + * region and that extends to 0x2001:0000. But the first and second memory + * regions are contiguous and treated as one in this logic that extends to + * 0x2002:0000 (or 0x2003:0000 for the F427/F437/F429/F439). + * + * As a complication, CCM SRAM cannot be used for DMA. So, if STM32 DMA is + * enabled, CCM SRAM should probably be excluded from the heap or the + * application must take extra care to ensure that DMA buffers are not + * allocated in CCM SRAM. + * + * In addition, external FSMC SRAM may be available. + */ + +#elif defined(CONFIG_STM32_HAVE_IP_FLASH_M3M4_F2F4) + +/* The STM32 F2 and the STM32 F401/F411/F412 have no CCM SRAM */ + +# if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F401) || \ + defined(CONFIG_STM32_STM32F411) || defined(CONFIG_STM32_STM32F410) || \ + defined(CONFIG_STM32_STM32F412) +# undef CONFIG_STM32_CCMEXCLUDE +# define CONFIG_STM32_CCMEXCLUDE 1 +# endif + +/* Set the end of system SRAM */ + +# if defined(CONFIG_STM32_STM32F401xBC) +# define SRAM1_END 0x20010000 +# elif defined(CONFIG_STM32_STM32F401xDE) +# define SRAM1_END 0x20018000 +# elif defined(CONFIG_STM32_STM32F410) +# define SRAM1_END 0x20008000 +# elif defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429) +# define SRAM1_END 0x20030000 +# elif defined(CONFIG_STM32_STM32F446) +# define SRAM1_END 0x20020000 +# elif defined(CONFIG_STM32_STM32F469) +# define SRAM1_END 0x20050000 +# else +# define SRAM1_END 0x20020000 +# endif + +/* Set the range of CCM SRAM as well (although we may not use it) */ + +# define SRAM2_START 0x10000000 +# define SRAM2_END 0x10010000 + +/* There are 4 possible SRAM configurations: + * + * Configuration 1. System SRAM (only) + * CONFIG_MM_REGIONS == 1 + * CONFIG_STM32_EXTERNAL_RAM NOT defined + * CONFIG_STM32_CCMEXCLUDE defined + * Configuration 2. System SRAM and CCM SRAM + * CONFIG_MM_REGIONS == 2 + * CONFIG_STM32_EXTERNAL_RAM NOT defined + * CONFIG_STM32_CCMEXCLUDE NOT defined + * Configuration 3. System SRAM and FSMC SRAM + * CONFIG_MM_REGIONS == 2 + * CONFIG_STM32_EXTERNAL_RAM defined + * CONFIG_STM32_CCMEXCLUDE defined + * Configuration 4. System SRAM, CCM SRAM, and FSMC SRAM + * CONFIG_MM_REGIONS == 3 + * CONFIG_STM32_EXTERNAL_RAM defined + * CONFIG_STM32_CCMEXCLUDE NOT defined + * + * Let's make sure that all definitions are consistent before doing + * anything else + */ + +# if defined(CONFIG_STM32_EXTERNAL_RAM) + +/* Configuration 3 or 4. External SRAM is available. CONFIG_MM_REGIONS + * should be at least 2. + */ + +# if CONFIG_MM_REGIONS < 2 + +/* Only one memory region. Force Configuration 1 */ + +# warning "FSMC SRAM (and CCM SRAM) excluded from the heap" +# undef CONFIG_STM32_EXTERNAL_RAM +# undef CONFIG_STM32_CCMEXCLUDE +# define CONFIG_STM32_CCMEXCLUDE 1 + +/* CONFIG_MM_REGIONS may be 3 if CCM SRAM is included in the head */ + +# elif CONFIG_MM_REGIONS > 2 + +/* More than two memory regions. This is okay if CCM SRAM is not + * disabled. + */ + +# if defined(CONFIG_STM32_CCMEXCLUDE) + +/* Configuration 3: CONFIG_MM_REGIONS should have been 2 */ + +# error "CONFIG_MM_REGIONS > 2 but I don't know what some of the region(s) are" +# undef CONFIG_MM_REGIONS +# define CONFIG_MM_REGIONS 2 +# else + +/* Configuration 4: DMA should be disabled and CONFIG_MM_REGIONS + * should be 3. + */ + +# ifdef CONFIG_ARCH_DMA +# warning "CCM SRAM is included in the heap AND DMA is enabled" +# endif + +# if CONFIG_MM_REGIONS != 3 +# error "CONFIG_MM_REGIONS > 3 but I don't know what some of the region(s) are" +# undef CONFIG_MM_REGIONS +# define CONFIG_MM_REGIONS 3 +# endif +# endif + +/* CONFIG_MM_REGIONS is exactly 2. We cannot support both CCM SRAM and + * FSMC SRAM. + */ + +# elif !defined(CONFIG_STM32_CCMEXCLUDE) +# error "CONFIG_MM_REGIONS == 2, cannot support both CCM SRAM and FSMC SRAM" +# undef CONFIG_STM32_CCMEXCLUDE +# define CONFIG_STM32_CCMEXCLUDE 1 +# endif + +# elif !defined(CONFIG_STM32_CCMEXCLUDE) + +/* Configuration 2: FSMC SRAM is not used, but CCM SRAM is requested. + * DMA should be disabled and CONFIG_MM_REGIONS should be 2. + */ + +# ifdef CONFIG_ARCH_DMA +# warning "CCM SRAM is included in the heap AND DMA is enabled" +# endif + +# if CONFIG_MM_REGIONS < 2 +# ifdef CONFIG_STM32_HAVE_CCM +# warning "CCM SRAM excluded from the heap because CONFIG_MM_REGIONS < 2" +# endif +# undef CONFIG_STM32_CCMEXCLUDE +# define CONFIG_STM32_CCMEXCLUDE 1 +# elif CONFIG_MM_REGIONS > 2 +# error "CONFIG_MM_REGIONS > 2 but I don't know what some of the region(s) are" +# undef CONFIG_MM_REGIONS +# define CONFIG_MM_REGIONS 2 +# endif +# endif + +/* STM32G47xxx family P/Ns have 96KiB of internal RAM in 2 banks, plus 32 KiB + * of CCM SRAM (Routine Booster), and the possibility of external RAM via + * FSMC: + * + * All internal RAM is contiguous from address 0x2000:0000 thru 0x2001:FFFF, + * but consists of these separate regions: + * + * SRAM: + * + * 1) 80 KiB SRAM1 mapped at 0x2000:0000 thru 0x2001:3FFF. + * 2) 16 KiB SRAM2 mapped at 0x2001:4000 thru 0x2001:7FFF. + * + * CCM SRAM: + * + * 3) 32 KiB CCM SRAM mapped at 0x1000:0000 thru 0x1000:7FFF + * but also aliased at at 0x2001:8000 thru 0x2001:FFFF to be contiguous + * with the SRAM1 and SRAM2. + * + * Because SRAM1 and SRAM2 are contiguous, they are treated as one region + * by this logic. + * + * REVISIT: I believe that unlike other parts mentioned in this file, the + * CCM SRAM *is* accessible to DMA. See Reference Manual (RM0440 Rev 2) + * section 2.1.3, DMA-Bus: "This bus connects the AHB master interface of + * the DMA to the BusMatrix. The targets of this bus are the SRAM1, SRAM2 + * and CCM SRAM..." Then, should we exclude CCM SRAM from the heap? + * + * In addition, external FSMC SRAM may be available. + */ + +#elif defined(CONFIG_STM32_STM32G4XXX) + +/* Set the end of system SRAM */ + +#if defined(CONFIG_STM32_STM32G47XX) +# define SRAM1_END 0x20020000 +#elif defined(CONFIG_STM32_STM32G43XX) +# define SRAM1_END 0x20005800 +#else +# error "Unsupported STM32G4 chip" +#endif + +/* Set the range of CCM SRAM as well (although we may not use it) */ + +# define SRAM2_START 0x10000000 + +#if defined(CONFIG_STM32_STM32G47XX) +# define SRAM2_END 0x10008000 +#elif defined(CONFIG_STM32_STM32G43XX) +# define SRAM2_END 0x10002700 +#else +# error "Unsupported STM32G4 chip" +#endif + +/* There are 4 possible SRAM configurations: + * + * Configuration 1. System SRAM (only) + * CONFIG_MM_REGIONS == 1 + * CONFIG_STM32_EXTERNAL_RAM NOT defined + * CONFIG_STM32_CCMEXCLUDE defined + * Configuration 2. System SRAM and CCM SRAM + * CONFIG_MM_REGIONS == 2 + * CONFIG_STM32_EXTERNAL_RAM NOT defined + * CONFIG_STM32_CCMEXCLUDE NOT defined + * Configuration 3. System SRAM and FSMC SRAM + * CONFIG_MM_REGIONS == 2 + * CONFIG_STM32_EXTERNAL_RAM defined + * CONFIG_STM32_CCMEXCLUDE defined + * Configuration 4. System SRAM, CCM SRAM, and FSMC SRAM + * CONFIG_MM_REGIONS == 3 + * CONFIG_STM32_EXTERNAL_RAM defined + * CONFIG_STM32_CCMEXCLUDE NOT defined + * + * Let's make sure that all definitions are consistent before doing + * anything else + */ + +# if defined(CONFIG_STM32_EXTERNAL_RAM) +# if (CONFIG_MM_REGIONS == 2) +/* OK: This is Configuration 3: SRAM and FSMC */ + +# elif (CONFIG_MM_REGIONS == 3) +/* OK: This is Configuration 3: SRAM, CCM, and FSMC */ + +# else +# error "Expected CONFIG_MM_REGIONS to be either 2 (SRAM + FSMC) or 3 (SRAM + CCM + FSMC)!" + +# endif +# else +# if (CONFIG_MM_REGIONS == 1) +/* OK: Configuration 1: SRAM only. */ + +# elif (CONFIG_MM_REGIONS == 2) +/* OK: Configuration 2: SRAM and CCM SRAM. */ + +# else +# error "Expected CONFIG_MM_REGIONS to be either 1 (SRAM) or 2 (SRAM + CCM)!" + +# endif +# endif + +#else +# error "Unsupported STM32 chip" +#endif + +/* If FSMC SRAM is going to be used as heap, then verify that the starting + * address and size of the external SRAM region has been provided in the + * configuration (as CONFIG_HEAP2_BASE and CONFIG_HEAP2_SIZE). + */ + +#ifdef CONFIG_STM32_EXTERNAL_RAM +# if !defined(CONFIG_HEAP2_BASE) || !defined(CONFIG_HEAP2_SIZE) +# error "CONFIG_HEAP2_BASE and CONFIG_HEAP2_SIZE must be provided" +# undef CONFIG_STM32_EXTERNAL_RAM +# endif +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_heap_color + * + * Description: + * Set heap memory to a known, non-zero state to checking heap usage. + * + ****************************************************************************/ + +#ifdef CONFIG_HEAP_COLORATION +static inline void up_heap_color(void *start, size_t size) +{ + memset(start, HEAP_COLOR, size); +} +#else +# define up_heap_color(start,size) +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_allocate_heap + * + * Description: + * This function will be called to dynamically set aside the heap region. + * + * For the kernel build (CONFIG_BUILD_PROTECTED=y) with both kernel- and + * user-space heaps (CONFIG_MM_KERNEL_HEAP=y), this function provides the + * size of the unprotected, user-space heap. + * + * If a protected kernel-space heap is provided, the kernel heap must be + * allocated (and protected) by an analogous up_allocate_kheap(). + * + * The following memory map is assumed for the flat build: + * + * .data region. Size determined at link time. + * .bss region Size determined at link time. + * IDLE thread stack. Size determined by CONFIG_IDLETHREAD_STACKSIZE. + * Heap. Extends to the end of SRAM. + * + * The following memory map is assumed for the kernel build: + * + * Kernel .data region Size determined at link time + * Kernel .bss region Size determined at link time + * Kernel IDLE thread stack Size determined by + * CONFIG_IDLETHREAD_STACKSIZE + * Padding for alignment + * User .data region Size determined at link time + * User .bss region Size determined at link time + * Kernel heap Size determined by + * CONFIG_MM_KERNEL_HEAPSIZE + * User heap Extends to the end of SRAM + * + ****************************************************************************/ + +void up_allocate_heap(void **heap_start, size_t *heap_size) +{ +#if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP) + /* Get the unaligned size and position of the user-space heap. + * This heap begins after the user-space .bss section at an offset + * of CONFIG_MM_KERNEL_HEAPSIZE (subject to alignment). + */ + + uintptr_t ubase = (uintptr_t)USERSPACE->us_bssend + + CONFIG_MM_KERNEL_HEAPSIZE; + size_t usize = SRAM1_END - ubase; + int log2; + + DEBUGASSERT(ubase < (uintptr_t)SRAM1_END); + + /* Adjust that size to account for MPU alignment requirements. + * NOTE that there is an implicit assumption that the SRAM1_END + * is aligned to the MPU requirement. + */ + + log2 = (int)mpu_log2regionfloor(usize); + + usize = (1 << log2); + ubase = SRAM1_END - usize; + + /* Return the user-space heap settings */ + + board_autoled_on(LED_HEAPALLOCATE); + *heap_start = (void *)ubase; + *heap_size = usize; + + /* Colorize the heap for debug */ + + up_heap_color((void *)ubase, usize); + + /* Allow user-mode access to the user heap memory */ + + stm32_mpu_uheap((uintptr_t)ubase, usize); +#else + + /* Return the heap settings */ + + board_autoled_on(LED_HEAPALLOCATE); + *heap_start = (void *)g_idle_topstack; + *heap_size = SRAM1_END - g_idle_topstack; + + /* Colorize the heap for debug */ + + up_heap_color(*heap_start, *heap_size); +#endif +} + +/**************************************************************************** + * Name: up_allocate_kheap + * + * Description: + * For the kernel build (CONFIG_BUILD_PROTECTED=y) with both kernel- and + * user-space heaps (CONFIG_MM_KERNEL_HEAP=y), this function allocates + * (and protects) the kernel-space heap. + * + ****************************************************************************/ + +#if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP) +void up_allocate_kheap(void **heap_start, size_t *heap_size) +{ + /* Get the unaligned size and position of the user-space heap. + * This heap begins after the user-space .bss section at an offset + * of CONFIG_MM_KERNEL_HEAPSIZE (subject to alignment). + */ + + uintptr_t ubase = (uintptr_t)USERSPACE->us_bssend + + CONFIG_MM_KERNEL_HEAPSIZE; + size_t usize = SRAM1_END - ubase; + int log2; + + DEBUGASSERT(ubase < (uintptr_t)SRAM1_END); + + /* Adjust that size to account for MPU alignment requirements. + * NOTE that there is an implicit assumption that the SRAM1_END + * is aligned to the MPU requirement. + */ + + log2 = (int)mpu_log2regionfloor(usize); + + usize = (1 << log2); + ubase = SRAM1_END - usize; + + /* Return the kernel heap settings (i.e., the part of the heap region + * that was not dedicated to the user heap). + */ + + *heap_start = (void *)USERSPACE->us_bssend; + *heap_size = ubase - (uintptr_t)USERSPACE->us_bssend; +} +#endif + +/**************************************************************************** + * Name: arm_addregion + * + * Description: + * Memory may be added in non-contiguous chunks. Additional chunks are + * added by calling this function. + * + ****************************************************************************/ + +#if CONFIG_MM_REGIONS > 1 +void arm_addregion(void) +{ +#ifndef CONFIG_STM32_CCMEXCLUDE +#if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP) + + /* Allow user-mode access to the STM32F20xxx/STM32F40xxx CCM SRAM heap */ + + stm32_mpu_uheap((uintptr_t)SRAM2_START, SRAM2_END - SRAM2_START); + +#endif + + /* Colorize the heap for debug */ + + up_heap_color((void *)SRAM2_START, SRAM2_END - SRAM2_START); + + /* Add the STM32F20xxx/STM32F40xxx CCM SRAM user heap region. */ + + kumm_addregion((void *)SRAM2_START, SRAM2_END - SRAM2_START); +#endif + +#ifdef CONFIG_STM32_EXTERNAL_RAM +#if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP) + + /* Allow user-mode access to the FSMC SRAM user heap memory */ + + stm32_mpu_uheap((uintptr_t)CONFIG_HEAP2_BASE, CONFIG_HEAP2_SIZE); + +#endif + + /* Colorize the heap for debug */ + + up_heap_color((void *)CONFIG_HEAP2_BASE, CONFIG_HEAP2_SIZE); + + /* Add the external FSMC SRAM user heap region. */ + + kumm_addregion((void *)CONFIG_HEAP2_BASE, CONFIG_HEAP2_SIZE); +#endif +} +#endif diff --git a/arch/arm/src/common/stm32/stm32_bbsram.h b/arch/arm/src/common/stm32/stm32_bbsram.h new file mode 100644 index 0000000000000..8c8658f963fb5 --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_bbsram.h @@ -0,0 +1,38 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_bbsram.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_COMPAT_STM32BBSRAM_H +#define __ARCH_ARM_SRC_COMMON_COMPAT_STM32BBSRAM_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#if defined(CONFIG_STM32_HAVE_IP_BBSRAM_M3M4_V1) +# include "stm32_bbsram_m3m4_v1.h" +#else +# error "Unsupported STM32 stm32_bbsram" +#endif + +#endif /* __ARCH_ARM_SRC_COMMON_COMPAT_STM32BBSRAM_H */ diff --git a/arch/arm/src/common/stm32/stm32_bbsram_m3m4_v1.c b/arch/arm/src/common/stm32/stm32_bbsram_m3m4_v1.c new file mode 100644 index 0000000000000..14c132dc8ea45 --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_bbsram_m3m4_v1.c @@ -0,0 +1,858 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_bbsram_m3m4_v1.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* This will driver create a set of files in the STM32's Battery backed up + * SRAM. That can be used to store data retained across power cycles. + * + */ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "stm32_bbsram_m3m4_v1.h" +#include "chip.h" +#include "stm32_pwr.h" +#include "stm32_rtc.h" + +#ifdef CONFIG_STM32_BBSRAM + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#if !defined(CONFIG_STM32_BKPSRAM) +#error Driver Requires CONFIG_STM32_BKPSRAM to be enabled +#endif + +#define MAX_OPENCNT (255) /* Limit of uint8_t */ + +#ifndef CONFIG_DEBUG_INFO +# undef CONFIG_BBSRAM_DEBUG +#endif + +#if defined(CONFIG_BBSRAM_DEBUG) +# define BBSRAM_DEBUG_READ() stm32_bbsram_rd() +# define BBSRAM_DUMP(p,s) stm32_bbsram_dump(p,s) +#else +# define BBSRAM_DEBUG_READ() +# define BBSRAM_DUMP(p,s) +#endif + +#define BBSRAM_HEADER_SIZE (sizeof(struct bbsramfh_s)) +#define BBSRAM_CRCED_OFFSET (sizeof(((struct bbsramfh_s *)0)->crc)) +#define BBSRAM_CRCED_SIZE(l) (BBSRAM_HEADER_SIZE-(BBSRAM_CRCED_OFFSET)+(l)) +#define BBSRAM_ALIGNMENT (sizeof(((struct bbsramfh_s *)0)->crc)) +#define BBSRAM_ALIGNMENT_MASK (BBSRAM_ALIGNMENT-1) + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/* File Header */ + +struct bbsramfh_s +{ + uint32_t crc; /* CRC calculated over data and this struct + * starting at fileno */ + uint8_t fileno; /* The minor number */ + uint8_t dirty; /* Data has been written to the file */ + uint16_t len; /* Total Bytes in this file */ + struct timespec lastwrite; /* Last write time */ + uint8_t data[]; /* Data in the file */ +}; + +struct stm32_bbsram_s +{ + mutex_t lock; /* For atomic accesses to this structure */ + uint8_t refs; /* Number of references */ + struct bbsramfh_s *bbf; /* File in bbram */ +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +static int stm32_bbsram_open(struct file *filep); +static int stm32_bbsram_close(struct file *filep); +static off_t stm32_bbsram_seek(struct file *filep, off_t offset, + int whence); +static ssize_t stm32_bbsram_read(struct file *filep, char *buffer, + size_t len); +static ssize_t stm32_bbsram_write(struct file *filep, + const char *buffer, size_t len); +static int stm32_bbsram_ioctl(struct file *filep, int cmd, + unsigned long arg); +static int stm32_bbsram_poll(struct file *filep, + struct pollfd *fds, bool setup); +#ifndef CONFIG_DISABLE_PSEUDOFS_OPERATIONS +static int stm32_bbsram_unlink(struct inode *inode); +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#if defined(CONFIG_BBSRAM_DEBUG) +static uint8_t debug[STM32_BBSRAM_SIZE]; +#endif + +static const struct file_operations g_stm32_bbsram_fops = +{ + .open = stm32_bbsram_open, + .close = stm32_bbsram_close, + .read = stm32_bbsram_read, + .write = stm32_bbsram_write, + .seek = stm32_bbsram_seek, + .ioctl = stm32_bbsram_ioctl, + .poll = stm32_bbsram_poll, +#ifndef CONFIG_DISABLE_PSEUDOFS_OPERATIONS + .unlink = stm32_bbsram_unlink +#endif +}; + +static struct stm32_bbsram_s g_bbsram[CONFIG_STM32_BBSRAM_FILES]; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_bbsram_rd + ****************************************************************************/ + +#if defined(CONFIG_BBSRAM_DEBUG) +static void stm32_bbsram_rd(void) +{ + memcpy(&debug, (uint8_t *)STM32_BKPSRAM_BASE, sizeof debug); +} +#endif + +/**************************************************************************** + * Name: stm32_bbsram_rd + ****************************************************************************/ + +#if defined(CONFIG_BBSRAM_DEBUG) +static void stm32_bbsram_dump(struct bbsramfh_s *bbf, char *op) +{ + BBSRAM_DEBUG_READ(); + _info("%s:\n", op); + _info(" File Address:0x%8x\n", bbf); + _info(" crc:0x%8x\n", bbf->crc); + _info(" fileno:%d\n", (int) bbf->fileno); + _info(" dirty:%d\n", (int) bbf->dirty); + _info(" length:%d\n", (int) bbf->len); + _info(" time:%jd:%ld\n", (intmax_t)bbf->lastwrite.tv_sec, + bbf->lastwrite.tv_nsec); + _info(" data: 0x%2x 0x%2x 0x%2x 0x%2x 0x%2x\n", + bbf->data[0], bbf->data[1], bbf->data[2], bbf->data[3], bbf->data[4]); +} +#endif + +/**************************************************************************** + * Name: stm32_bbsram_unlock + * + * Description: + * Unprotects RTC registers, RTC backup data registers and backup SRAM + * against parasitic write access + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +static inline void stm32_bbsram_unlock(void) +{ + stm32_pwr_enablebkp(true); +} + +/**************************************************************************** + * Name: stm32_bbsram_lock + * + * Description: + * Protects RTC registers, RTC backup data registers and backup SRAM + * against parasitic write access + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +static inline void stm32_bbsram_lock(void) +{ + stm32_pwr_enablebkp(false); +} + +/**************************************************************************** + * Name: stm32_bbsram_crc + * + * Description: + * Calculates the CRC of the block + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +static uint32_t stm32_bbsram_crc(struct bbsramfh_s *pf) +{ + return crc32((uint8_t *)pf + BBSRAM_CRCED_OFFSET, + BBSRAM_CRCED_SIZE(pf->len)); +} + +/**************************************************************************** + * Name: stm32_bbsram_open + * + * Description: Open the device + * + ****************************************************************************/ + +static int stm32_bbsram_open(struct file *filep) +{ + struct inode *inode = filep->f_inode; + struct stm32_bbsram_s *bbr; + int ret; + + DEBUGASSERT(inode->i_private); + bbr = inode->i_private; + + /* Increment the reference count */ + + ret = nxmutex_lock(&bbr->lock); + if (ret < 0) + { + return ret; + } + + if (bbr->refs == MAX_OPENCNT) + { + return -EMFILE; + } + else + { + bbr->refs++; + } + + nxmutex_unlock(&bbr->lock); + return OK; +} + +/**************************************************************************** + * Name: stm32_bbsram_internal_close + * + * Description: + * Close BBSRAM entry; Recalculate the time and crc + * + ****************************************************************************/ + +static int stm32_bbsram_internal_close(struct bbsramfh_s *bbf) +{ + bbf->dirty = 0; + clock_gettime(CLOCK_REALTIME, &bbf->lastwrite); + bbf->crc = stm32_bbsram_crc(bbf); + + BBSRAM_DUMP(bbf, "close done"); + return bbf->len; +} + +/**************************************************************************** + * Name: stm32_bbsram_close + * + * Description: close the device + * + ****************************************************************************/ + +static int stm32_bbsram_close(struct file *filep) +{ + struct inode *inode = filep->f_inode; + struct stm32_bbsram_s *bbr; + int ret = OK; + + DEBUGASSERT(inode->i_private); + bbr = inode->i_private; + + ret = nxmutex_lock(&bbr->lock); + if (ret < 0) + { + return ret; + } + + BBSRAM_DUMP(bbr->bbf, "close"); + + if (bbr->refs == 0) + { + ret = -EIO; + } + else + { + bbr->refs--; + + if (bbr->refs == 0) + { + if (bbr->bbf->dirty) + { + /* Recalculate the time and crc */ + + stm32_bbsram_unlock(); + stm32_bbsram_internal_close(bbr->bbf); + stm32_bbsram_lock(); + } + } + } + + nxmutex_unlock(&bbr->lock); + return ret; +} + +/**************************************************************************** + * Name: stm32_bbsram_seek + ****************************************************************************/ + +static off_t stm32_bbsram_seek(struct file *filep, off_t offset, + int whence) +{ + struct inode *inode = filep->f_inode; + struct stm32_bbsram_s *bbr; + off_t newpos; + int ret; + + DEBUGASSERT(inode->i_private); + bbr = inode->i_private; + + ret = nxmutex_lock(&bbr->lock); + if (ret < 0) + { + return (off_t)ret; + } + + /* Determine the new, requested file position */ + + switch (whence) + { + case SEEK_CUR: + newpos = filep->f_pos + offset; + break; + + case SEEK_SET: + newpos = offset; + break; + + case SEEK_END: + newpos = bbr->bbf->len + offset; + break; + + default: + + /* Return EINVAL if the whence argument is invalid */ + + nxmutex_unlock(&bbr->lock); + return -EINVAL; + } + + /* Opengroup.org: + * + * "The lseek() function shall allow the file offset to be set beyond the + * end of the existing data in the file. If data is later written at this + * point, subsequent reads of data in the gap shall return bytes with the + * value 0 until data is actually written into the gap." + * + * We can conform to the first part, but not the second. But return -EINVAL + * if "...the resulting file offset would be negative for a regular file, + * block special file, or directory." + */ + + if (newpos >= 0) + { + filep->f_pos = newpos; + ret = newpos; + } + else + { + ret = -EINVAL; + } + + nxmutex_unlock(&bbr->lock); + return ret; +} + +/**************************************************************************** + * Name: stm32_bbsram_read + ****************************************************************************/ + +static ssize_t stm32_bbsram_read(struct file *filep, char *buffer, + size_t len) +{ + struct inode *inode = filep->f_inode; + struct stm32_bbsram_s *bbr; + int ret; + + DEBUGASSERT(inode->i_private); + bbr = inode->i_private; + + ret = nxmutex_lock(&bbr->lock); + if (ret < 0) + { + return (ssize_t)ret; + } + + /* Trim len if read would go beyond end of device */ + + if ((filep->f_pos + len) > bbr->bbf->len) + { + len = bbr->bbf->len - filep->f_pos; + } + + memcpy(buffer, &bbr->bbf->data[filep->f_pos], len); + filep->f_pos += len; + nxmutex_unlock(&bbr->lock); + return len; +} + +/**************************************************************************** + * Name: stm32_bbsram_internal_write + ****************************************************************************/ + +static ssize_t stm32_bbsram_internal_write(struct bbsramfh_s *bbf, + const char *buffer, + off_t offset, size_t len) +{ + bbf->dirty = 1; + memcpy(&bbf->data[offset], buffer, len); + return len; +} + +/**************************************************************************** + * Name: stm32_bbsram_write + ****************************************************************************/ + +static ssize_t stm32_bbsram_write(struct file *filep, + const char *buffer, size_t len) +{ + struct inode *inode = filep->f_inode; + struct stm32_bbsram_s *bbr; + int ret = -EFBIG; + + DEBUGASSERT(inode->i_private); + bbr = inode->i_private; + + /* Forbid writes past the end of the device */ + + if (filep->f_pos < bbr->bbf->len) + { + /* Clamp len to avoid crossing the end of the memory */ + + if ((filep->f_pos + len) > bbr->bbf->len) + { + len = bbr->bbf->len - filep->f_pos; + } + + ret = nxmutex_lock(&bbr->lock); + if (ret < 0) + { + return (ssize_t)ret; + } + + ret = len; /* save number of bytes written */ + + BBSRAM_DUMP(bbr->bbf, "write"); + stm32_bbsram_unlock(); + stm32_bbsram_internal_write(bbr->bbf, buffer, filep->f_pos, len); + stm32_bbsram_lock(); + filep->f_pos += len; + BBSRAM_DUMP(bbr->bbf, "write done"); + nxmutex_unlock(&bbr->lock); + } + + BBSRAM_DEBUG_READ(); + return ret; +} + +/**************************************************************************** + * Name: stm32_bbsram_poll + ****************************************************************************/ + +static int stm32_bbsram_poll(struct file *filep, struct pollfd *fds, + bool setup) +{ + if (setup) + { + poll_notify(&fds, 1, POLLIN | POLLOUT); + } + + return OK; +} + +/**************************************************************************** + * Name: stm32_bbsram_ioctl + * + * Description: Return device geometry + * + ****************************************************************************/ + +static int stm32_bbsram_ioctl(struct file *filep, int cmd, + unsigned long arg) +{ + struct inode *inode = filep->f_inode; + struct stm32_bbsram_s *bbr; + int ret = -ENOTTY; + + DEBUGASSERT(inode->i_private); + bbr = inode->i_private; + + if (cmd == STM32_BBSRAM_GETDESC_IOCTL) + { + struct bbsramd_s *bbrr = (struct bbsramd_s *)((uintptr_t)arg); + + ret = nxmutex_lock(&bbr->lock); + if (ret < 0) + { + return ret; + } + + if (!bbrr) + { + ret = -EINVAL; + } + else + { + bbrr->fileno = bbr->bbf->fileno; + bbrr->lastwrite = bbr->bbf->lastwrite; + bbrr->len = bbr->bbf->len; + bbrr->flags = ((bbr->bbf->crc == stm32_bbsram_crc(bbr->bbf)) + ? BBSRAM_CRC_VALID : 0); + bbrr->flags |= ((bbr->bbf->dirty) ? BBSRAM_DIRTY : 0); + ret = OK; + } + + nxmutex_unlock(&bbr->lock); + } + + return ret; +} + +/**************************************************************************** + * Name: stm32_bbsram_unlink + * + * Description: + * This function will remove the remove the file from the file system + * it will zero the contents and time stamp. It will leave the fileno + * and pointer to the BBSRAM intact. + * It should be called called on the file used for the crash dump + * to remove it from visibility in the file system after it is created or + * read thus arming it. + * + ****************************************************************************/ + +#ifndef CONFIG_DISABLE_PSEUDOFS_OPERATIONS +static int stm32_bbsram_unlink(struct inode *inode) +{ + struct stm32_bbsram_s *bbr; + int ret; + + DEBUGASSERT(inode->i_private); + bbr = inode->i_private; + + ret = nxmutex_lock(&bbr->lock); + if (ret < 0) + { + return ret; + } + + stm32_bbsram_unlock(); + memset(bbr->bbf->data, 0, bbr->bbf->len); + bbr->bbf->lastwrite.tv_nsec = 0; + bbr->bbf->lastwrite.tv_sec = 0; + bbr->bbf->crc = stm32_bbsram_crc(bbr->bbf); + stm32_bbsram_lock(); + bbr->refs = 0; + nxmutex_unlock(&bbr->lock); + nxmutex_destroy(&bbr->lock); + + return 0; +} +#endif + +/**************************************************************************** + * Name: stm32_bbsram_probe + * + * Description: Based on the number of files defined and their sizes + * Initializes the base pointers to the file entries. + * + ****************************************************************************/ + +static int stm32_bbsram_probe(int *ent, struct stm32_bbsram_s pdev[]) +{ + int i; + int avail = STM32_BBSRAM_SIZE; + int alloc; + int size; + int ret = -EFBIG; + struct bbsramfh_s *pf = (struct bbsramfh_s *) STM32_BKPSRAM_BASE; + + for (i = 0; (i < CONFIG_STM32_BBSRAM_FILES) && ent[i] && (avail > 0); i++) + { + /* Validate the actual allocations against what is in the BBSRAM */ + + size = ent[i]; + + /* Use all that is left */ + + if (size == -1) + { + size = avail - (BBSRAM_HEADER_SIZE + BBSRAM_ALIGNMENT_MASK); + } + + /* Add in header size and keep aligned */ + + alloc = size + BBSRAM_HEADER_SIZE + BBSRAM_ALIGNMENT_MASK; + alloc &= ~(BBSRAM_ALIGNMENT_MASK); + + /* Does it fit? */ + + if (alloc <= avail) + { + ret = i + 1; + BBSRAM_DUMP(pf, "probe"); + + if (pf->len != size || + pf->fileno != i || + pf->crc != stm32_bbsram_crc(pf)) + { + /* Not Valid so wipe the file in BBSRAM */ + + memset((uint8_t *)pf, 0, alloc); + pf->fileno = i; + pf->len = size; + pf->crc = stm32_bbsram_crc(pf); + BBSRAM_DUMP(pf, "probe reset"); + } + + pdev[i].bbf = pf; + pf = (struct bbsramfh_s *)((uint8_t *)pf + alloc); + nxmutex_init(&g_bbsram[i].lock); + } + + avail -= alloc; + } + + BBSRAM_DEBUG_READ(); + return ret; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Function: stm32_bbsraminitialize + * + * Description: + * Initialize the Battery Backed up SRAM driver. + * + * Input Parameters: + * devpath - the path to instantiate the files. + * sizes - Pointer to a any array of file sizes to create + * the last entry should be 0 + * A size of -1 will use all the remaining spaces + * + * If the length of sizes is greater then CONFIG_STM32_BBSRAM_FILES + * CONFIG_STM32_BBSRAM_FILES will be returned. + * + * Returned Value: + * Number of files created on success; Negated errno on failure. + * + * Assumptions: + * + ****************************************************************************/ + +int stm32_bbsraminitialize(char *devpath, int *sizes) +{ + int i; + int fcnt; + char devname[32]; + + int ret = OK; + + if (devpath == NULL) + { + return -EINVAL; + } + + i = strlen(devpath); + if (i == 0 || i > sizeof(devname) - 3) + { + return -EINVAL; + } + + memset(g_bbsram, 0, sizeof(g_bbsram)); + + /* Clocking for the PWR block must be provided. However, this is done + * unconditionally in stm32f40xxx_rcc.c on power up. This done + * unconditionally because the PWR block is also needed to set the + * internal voltage regulator for maximum performance. + */ + + /* Enable backup SRAM clock is done in rcc_enableahb1() when + * CONFIG_STM32_BKPSRAM is defined. + */ + + /* Allow Access */ + + stm32_bbsram_unlock(); + + /* Enable backup regulator so that the data is retained in Standby and + * VBAT modes + */ + + stm32_pwr_enablebreg(true); + + fcnt = stm32_bbsram_probe(sizes, g_bbsram); + + for (i = 0; i < fcnt && ret >= OK; i++) + { + snprintf(devname, sizeof(devname), "%s%d", devpath, i); + ret = register_driver(devname, &g_stm32_bbsram_fops, + 0666, &g_bbsram[i]); + } + + /* Disallow Access */ + + stm32_bbsram_lock(); + return ret < OK ? ret : fcnt; +} + +/**************************************************************************** + * Function: stm32_bbsram_savepanic + * + * Description: + * Saves the panic context in a previously allocated BBSRAM file + * + * Input Parameters: + * fileno - the value returned by the ioctl STM32_BBSRAM_GETDESC_IOCTL + * context - Pointer to a any array of bytes to save + * length - The length of the data pointed to byt context + * + * Returned Value: + * Length saved or negated errno. + * + * Assumptions: + * + ****************************************************************************/ + +#if defined(CONFIG_STM32_SAVE_CRASHDUMP) +int stm32_bbsram_savepanic(int fileno, uint8_t *context, int length) +{ + struct bbsramfh_s *bbf; + int fill; + int ret = -ENOSPC; + + /* On a bad day we could panic while panicking, (and we debug assert) + * this is a potential feeble attempt at only writing the first + * panic's context to the file + */ + + static bool once = false; + + if (!once) + { + once = true; + + DEBUGASSERT(fileno > 0 && fileno < CONFIG_STM32_BBSRAM_FILES); + + bbf = g_bbsram[fileno].bbf; + + DEBUGASSERT(bbf); + + /* If the g_bbsram has been nulled out we return ENXIO. + * + * As once ensures we will keep the first dump. Checking the time for + * 0 protects from over writing a previous crash dump that has not + * been saved to long term storage and erased. The dreaded reboot + * loop. + */ + + if (!bbf) + { + ret = -ENXIO; + } + else if ((bbf->lastwrite.tv_sec == 0 && bbf->lastwrite.tv_nsec == 0)) + { + /* Clamp length if too big */ + + if (length > bbf->len) + { + length = bbf->len; + } + + stm32_bbsram_unlock(); + + stm32_bbsram_internal_write(bbf, (char *) context, 0, length); + + /* Fill with 0 if data is less then file size */ + + fill = (int) bbf->len - length; + + if (fill > 0) + { + memset(&bbf->data[length], 0, fill); + } + + /* Seal the file */ + + stm32_bbsram_internal_close(bbf); + + stm32_bbsram_lock(); + ret = length; + } + } + + return ret; +} +#endif + +#endif /* CONFIG_BBSRAM_DRIVER */ diff --git a/arch/arm/src/common/stm32/stm32_bbsram_m3m4_v1.h b/arch/arm/src/common/stm32/stm32_bbsram_m3m4_v1.h new file mode 100644 index 0000000000000..3f8abefa83e4c --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_bbsram_m3m4_v1.h @@ -0,0 +1,152 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_bbsram_m3m4_v1.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_BBSRAM_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_BBSRAM_H + +/**************************************************************************** + * The purpose of this driver is to add battery backup file to the file + * system. There can be CONFIG_STM32_BBRSRAM_COUNT files defined. + * These files are of fixed size up to the maximum of the backing SRAM. + * In the care of the STM32F2 and STM32F4 this is a maximum of 4K Bytes. + * + * If CONFIG_SAVE_CRASHDUMP is defined The driver also supports a feature + * to save the context of a PANIC in one of these files. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#if defined(CONFIG_STM32_HAVE_IP_BBSRAM_M3M4_V1) +# define STM32_BBSRAM_SIZE 4096 +#else +# error No backup SRAM on this STM32 +#endif + +#if !defined(CONFIG_STM32_BBSRAM_FILES) +# define CONFIG_STM32_BBSRAM_FILES 4 +#endif + +/* REVISIT: What guarantees that STM32_BBSRAM_GETDESC_IOCTL has a unique + * value among all over _DIOC() values? + */ + +#define STM32_BBSRAM_GETDESC_IOCTL _DIOC(0x0010) /* Returns a bbsramd_s */ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +enum bbsramdf_e +{ + BBSRAM_CRC_VALID = 1, /* The crc is valid */ + BBSRAM_DIRTY = 2, /* The file was closed */ +}; + +struct bbsramd_s +{ + uint8_t flags; /* The crc is valid and the file was closed */ + uint8_t fileno; /* The minor number */ + uint16_t len; /* Total Bytes in this file */ + struct timespec lastwrite; /* Last write time */ +}; + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#undef EXTERN +#if defined(__cplusplus) +# define EXTERN extern "C" +extern "C" +{ +#else +# define EXTERN extern +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Function: stm32_bbsraminitialize + * + * Description: + * Initialize the Battery Backed up SRAM driver. + * + * Input Parameters: + * devpath - the path to instantiate the files. + * sizes - Pointer to a any array of file sizes to create + * the last entry should be 0 + * A size of -1 will use all the remaining spaces + * + * If the length of sizes is greater then CONFIG_STM32_BBSRAM_FILES + * CONFIG_STM32_BBSRAM_FILES will be returned. + * + * Returned Value: + * Number of files created on success; Negated errno on failure. + * + * Assumptions: + * + ****************************************************************************/ + +int stm32_bbsraminitialize(char *devpath, int *sizes); + +/**************************************************************************** + * Function: stm32_bbsram_savepanic + * + * Description: + * Saves the panic context in a previously allocated BBSRAM file + * + * Parameters: + * fileno - the value returned by the ioctl STM32_BBSRAM_GETDESC_IOCTL + * context - Pointer to a any array of bytes to save + * length - The length of the data pointed to byt context + * + * Returned Value: + * Length saved or negated errno. + * + * Assumptions: + * + ****************************************************************************/ + +#if defined(CONFIG_STM32_SAVE_CRASHDUMP) +int stm32_bbsram_savepanic(int fileno, uint8_t *context, int length); +#endif + +#undef EXTERN +#ifdef __cplusplus +} +#endif +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_BBSRAM_H */ diff --git a/arch/arm/src/common/stm32/stm32_bkp.h b/arch/arm/src/common/stm32/stm32_bkp.h new file mode 100644 index 0000000000000..ab84719310e1d --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_bkp.h @@ -0,0 +1,50 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_bkp.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_BKP_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_BKP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/* Only the STM32 F1 family has a dedicated address region for BKP memory. + * For F2, F3, and F4 parts, the bKP registers lie in the same address + * region as the RTCC and the definitions in chip/stm32_rtcc.h should be used + * to access backup registers. + * NOTE: These definitions are not interchangeable! + */ + +#include "chip.h" +#ifdef CONFIG_STM32_STM32F10XX +# include "hardware/stm32_bkp.h" +#else +# include "hardware/stm32_rtcc.h" +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_BKP_H */ diff --git a/arch/arm/src/common/stm32/stm32_can.h b/arch/arm/src/common/stm32/stm32_can.h new file mode 100644 index 0000000000000..ef931423e57bc --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_can.h @@ -0,0 +1,158 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_can.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32_STM32_CAN_H +#define __ARCH_ARM_SRC_STM32_STM32_CAN_H + +#if defined(CONFIG_STM32_HAVE_IP_CAN_BXCAN_M3M4_V1) + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +# include + +# include "chip.h" +# include "hardware/stm32_can.h" + +# include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* Up to 2 CAN interfaces are supported */ + +# if STM32_NCAN < 2 +# undef CONFIG_STM32_CAN2 +# endif + +# if STM32_NCAN < 1 +# undef CONFIG_STM32_CAN1 +# endif + +/* CAN BAUD */ + +# if defined(CONFIG_STM32_CAN1) && !defined(CONFIG_STM32_CAN1_BAUD) +# error "CONFIG_STM32_CAN1_BAUD is not defined" +# endif + +# if defined(CONFIG_STM32_CAN2) && !defined(CONFIG_STM32_CAN2_BAUD) +# error "CONFIG_STM32_CAN2_BAUD is not defined" +# endif + +/* User-defined TSEG1 and TSEG2 settings may be used. + * + * CONFIG_STM32_CAN_TSEG1 = the number of CAN time quanta in segment 1 + * CONFIG_STM32_CAN_TSEG2 = the number of CAN time quanta in segment 2 + * CAN_BIT_QUANTA = The number of CAN time quanta in on bit time + */ + +# ifndef CONFIG_STM32_CAN_TSEG1 +# define CONFIG_STM32_CAN_TSEG1 6 +# endif + +# if CONFIG_STM32_CAN_TSEG1 < 1 || CONFIG_STM32_CAN_TSEG1 > CAN_BTR_TSEG1_MAX +# error "CONFIG_STM32_CAN_TSEG1 is out of range" +# endif + +# ifndef CONFIG_STM32_CAN_TSEG2 +# define CONFIG_STM32_CAN_TSEG2 7 +# endif + +# if CONFIG_STM32_CAN_TSEG2 < 1 || CONFIG_STM32_CAN_TSEG2 > CAN_BTR_TSEG2_MAX +# error "CONFIG_STM32_CAN_TSEG2 is out of range" +# endif + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +# ifndef __ASSEMBLY__ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +# undef EXTERN +# if defined(__cplusplus) +# define EXTERN extern "C" +extern "C" +{ +# else +# define EXTERN extern +# endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +# ifdef CONFIG_STM32_CAN_CHARDRIVER + +/**************************************************************************** + * Name: stm32_caninitialize + * + * Description: + * Initialize the selected CAN port as character device + * + * Input Parameters: + * Port number (for hardware that has multiple CAN interfaces) + * + * Returned Value: + * Valid CAN device structure reference on success; a NULL on failure + * + ****************************************************************************/ + +struct can_dev_s; +struct can_dev_s *stm32_caninitialize(int port); +# endif + +# ifdef CONFIG_STM32_CAN_SOCKET + +/**************************************************************************** + * Name: stm32_cansockinitialize + * + * Description: + * Initialize the selected CAN port as SocketCAN interface + * + * Input Parameters: + * Port number (for hardware that has multiple CAN interfaces) + * + * Returned Value: + * OK on success; Negated errno on failure. + * + ****************************************************************************/ + +int stm32_cansockinitialize(int port); +# endif + +# undef EXTERN +# if defined(__cplusplus) +} +# endif + +# endif /* __ASSEMBLY__ */ +#endif + +#endif /* __ARCH_ARM_SRC_STM32_STM32_CAN_H */ diff --git a/arch/arm/src/common/stm32/stm32_can_m3m4_v1.c b/arch/arm/src/common/stm32/stm32_can_m3m4_v1.c new file mode 100644 index 0000000000000..90959870c4955 --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_can_m3m4_v1.c @@ -0,0 +1,2540 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_can_m3m4_v1.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include "arm_internal.h" +#include "chip.h" +#include "stm32.h" +#include "stm32_rcc.h" +#include "stm32_can.h" + +#if defined(CONFIG_CAN) && \ + (defined(CONFIG_STM32_CAN1) || defined(CONFIG_STM32_CAN2)) + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Delays *******************************************************************/ + +/* Time out for INAK bit */ + +#define INAK_TIMEOUT 65535 + +/* Bit timing ***************************************************************/ + +#define CAN_BIT_QUANTA (CONFIG_STM32_CAN_TSEG1 + CONFIG_STM32_CAN_TSEG2 + 1) + +#ifndef CONFIG_DEBUG_CAN_INFO +# undef CONFIG_STM32_CAN_REGDEBUG +#endif + +/* CAN error interrupts */ + +#ifdef CONFIG_CAN_ERRORS +# define STM32_CAN_ERRINT (CAN_IER_LECIE | CAN_IER_ERRIE | \ + CAN_IER_BOFIE | CAN_IER_EPVIE | \ + CAN_IER_EWGIE) +#endif + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +struct stm32_can_s +{ + uint8_t port; /* CAN port number (1 or 2) */ + uint8_t canrx[2]; /* CAN RX FIFO 0/1 IRQ number */ + uint8_t cantx; /* CAN TX IRQ number */ +#ifdef CONFIG_CAN_ERRORS + uint8_t cansce; /* CAN SCE IRQ number */ +#endif + uint8_t filter; /* Filter number */ + uint32_t base; /* Base address of the CAN control registers */ + uint32_t fbase; /* Base address of the CAN filter registers */ + uint32_t baud; /* Configured baud */ +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/* CAN Register access */ + +static uint32_t stm32can_getreg(struct stm32_can_s *priv, + int offset); +static uint32_t stm32can_getfreg(struct stm32_can_s *priv, + int offset); +static void stm32can_putreg(struct stm32_can_s *priv, int offset, + uint32_t value); +static void stm32can_putfreg(struct stm32_can_s *priv, int offset, + uint32_t value); +#ifdef CONFIG_STM32_CAN_REGDEBUG +static void stm32can_dumpctrlregs(struct stm32_can_s *priv, + const char *msg); +static void stm32can_dumpmbregs(struct stm32_can_s *priv, + const char *msg); +static void stm32can_dumpfiltregs(struct stm32_can_s *priv, + const char *msg); +#else +# define stm32can_dumpctrlregs(priv,msg) +# define stm32can_dumpmbregs(priv,msg) +# define stm32can_dumpfiltregs(priv,msg) +#endif + +/* Filtering (todo) */ + +#ifdef CONFIG_CAN_EXTID +static int stm32can_addextfilter(struct stm32_can_s *priv, + struct canioc_extfilter_s *arg); +static int stm32can_delextfilter(struct stm32_can_s *priv, + int arg); +#endif +static int stm32can_addstdfilter(struct stm32_can_s *priv, + struct canioc_stdfilter_s *arg); +static int stm32can_delstdfilter(struct stm32_can_s *priv, + int arg); + +/* CAN driver methods */ + +static void stm32can_reset(struct can_dev_s *dev); +static int stm32can_setup(struct can_dev_s *dev); +static void stm32can_shutdown(struct can_dev_s *dev); +static void stm32can_rxint(struct can_dev_s *dev, bool enable); +static void stm32can_txint(struct can_dev_s *dev, bool enable); +static int stm32can_ioctl(struct can_dev_s *dev, int cmd, + unsigned long arg); +static int stm32can_remoterequest(struct can_dev_s *dev, + uint16_t id); +static int stm32can_send(struct can_dev_s *dev, + struct can_msg_s *msg); +static bool stm32can_txready(struct can_dev_s *dev); +static bool stm32can_txempty(struct can_dev_s *dev); + +#ifdef CONFIG_CAN_ERRORS +static void stm32can_errint(struct can_dev_s *dev, bool enable); +#endif + +/* CAN interrupt handling */ + +static int stm32can_rxinterrupt(struct can_dev_s *dev, int rxmb); +static int stm32can_rx0interrupt(int irq, void *context, void *arg); +static int stm32can_rx1interrupt(int irq, void *context, void *arg); +static int stm32can_txinterrupt(int irq, void *context, void *arg); +#ifdef CONFIG_CAN_ERRORS +static int stm32can_sceinterrupt(int irq, void *context, void *arg); +#endif + +/* Initialization */ + +static int stm32can_enterinitmode(struct stm32_can_s *priv); +static int stm32can_exitinitmode(struct stm32_can_s *priv); +static int stm32can_bittiming(struct stm32_can_s *priv); +static int stm32can_cellinit(struct stm32_can_s *priv); +static int stm32can_filterinit(struct stm32_can_s *priv); + +/* TX mailbox status */ + +static bool stm32can_txmb0empty(uint32_t tsr_regval); +static bool stm32can_txmb1empty(uint32_t tsr_regval); +static bool stm32can_txmb2empty(uint32_t tsr_regval); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static const struct can_ops_s g_canops = +{ + .co_reset = stm32can_reset, + .co_setup = stm32can_setup, + .co_shutdown = stm32can_shutdown, + .co_rxint = stm32can_rxint, + .co_txint = stm32can_txint, + .co_ioctl = stm32can_ioctl, + .co_remoterequest = stm32can_remoterequest, + .co_send = stm32can_send, + .co_txready = stm32can_txready, + .co_txempty = stm32can_txempty, +}; + +#ifdef CONFIG_STM32_CAN1 +static struct stm32_can_s g_can1priv = +{ + .port = 1, + .canrx = + { + STM32_IRQ_CAN1RX0, + STM32_IRQ_CAN1RX1, + }, + .cantx = STM32_IRQ_CAN1TX, +#ifdef CONFIG_CAN_ERRORS + .cansce = STM32_IRQ_CAN1SCE, +#endif + .filter = 0, + .base = STM32_CAN1_BASE, + .fbase = STM32_CAN1_BASE, + .baud = CONFIG_STM32_CAN1_BAUD, +}; + +static struct can_dev_s g_can1dev = +{ + .cd_ops = &g_canops, + .cd_priv = &g_can1priv, +}; +#endif + +#ifdef CONFIG_STM32_CAN2 +static struct stm32_can_s g_can2priv = +{ + .port = 2, + .canrx = + { + STM32_IRQ_CAN2RX0, + STM32_IRQ_CAN2RX1, + }, + .cantx = STM32_IRQ_CAN2TX, +#ifdef CONFIG_CAN_ERRORS + .cansce = STM32_IRQ_CAN2SCE, +#endif + .filter = CAN_NFILTERS / 2, + .base = STM32_CAN2_BASE, + .fbase = STM32_CAN1_BASE, + .baud = CONFIG_STM32_CAN2_BAUD, +}; + +static struct can_dev_s g_can2dev = +{ + .cd_ops = &g_canops, + .cd_priv = &g_can2priv, +}; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32can_getreg + * Name: stm32can_getfreg + * + * Description: + * Read the value of a CAN register or filter block register. + * + * Input Parameters: + * priv - A reference to the CAN block status + * offset - The offset to the register to read + * + * Returned Value: + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_CAN_REGDEBUG +static uint32_t stm32can_vgetreg(uint32_t addr) +{ + static uint32_t prevaddr = 0; + static uint32_t preval = 0; + static uint32_t count = 0; + + /* Read the value from the register */ + + uint32_t val = getreg32(addr); + + /* Is this the same value that we read from the same register last time? + * Are we polling the register? If so, suppress some of the output. + */ + + if (addr == prevaddr && val == preval) + { + if (count == 0xffffffff || ++count > 3) + { + if (count == 4) + { + caninfo("...\n"); + } + + return val; + } + } + + /* No this is a new address or value */ + + else + { + /* Did we print "..." for the previous value? */ + + if (count > 3) + { + /* Yes.. then show how many times the value repeated */ + + caninfo("[repeats %" PRIu32 " more times]\n", count - 3); + } + + /* Save the new address, value, and count */ + + prevaddr = addr; + preval = val; + count = 1; + } + + /* Show the register value read */ + + caninfo("%08" PRIx32 "->%08" PRIx32 "\n", addr, val); + return val; +} + +static uint32_t stm32can_getreg(struct stm32_can_s *priv, int offset) +{ + return stm32can_vgetreg(priv->base + offset); +} + +static uint32_t stm32can_getfreg(struct stm32_can_s *priv, int offset) +{ + return stm32can_vgetreg(priv->fbase + offset); +} + +#else +static uint32_t stm32can_getreg(struct stm32_can_s *priv, int offset) +{ + return getreg32(priv->base + offset); +} + +static uint32_t stm32can_getfreg(struct stm32_can_s *priv, int offset) +{ + return getreg32(priv->fbase + offset); +} + +#endif + +/**************************************************************************** + * Name: stm32can_putreg + * Name: stm32can_putfreg + * + * Description: + * Set the value of a CAN register or filter block register. + * + * Input Parameters: + * priv - A reference to the CAN block status + * offset - The offset to the register to write + * value - The value to write to the register + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_CAN_REGDEBUG +static void stm32can_vputreg(uint32_t addr, uint32_t value) +{ + /* Show the register value being written */ + + caninfo("%08" PRIx32 "->%08" PRIx32 "\n", addr, value); + + /* Write the value */ + + putreg32(value, addr); +} + +static void stm32can_putreg(struct stm32_can_s *priv, int offset, + uint32_t value) +{ + stm32can_vputreg(priv->base + offset, value); +} + +static void stm32can_putfreg(struct stm32_can_s *priv, int offset, + uint32_t value) +{ + stm32can_vputreg(priv->fbase + offset, value); +} + +#else +static void stm32can_putreg(struct stm32_can_s *priv, int offset, + uint32_t value) +{ + putreg32(value, priv->base + offset); +} + +static void stm32can_putfreg(struct stm32_can_s *priv, int offset, + uint32_t value) +{ + putreg32(value, priv->fbase + offset); +} +#endif + +/**************************************************************************** + * Name: stm32can_dumpctrlregs + * + * Description: + * Dump the contents of all CAN control registers + * + * Input Parameters: + * priv - A reference to the CAN block status + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_CAN_REGDEBUG +static void stm32can_dumpctrlregs(struct stm32_can_s *priv, + const char *msg) +{ + if (msg) + { + caninfo("Control Registers: %s\n", msg); + } + else + { + caninfo("Control Registers:\n"); + } + + /* CAN control and status registers */ + + caninfo(" MCR: %08" PRIx32 " MSR: %08" PRIx32 " TSR: %08" PRIx32 "\n", + getreg32(priv->base + STM32_CAN_MCR_OFFSET), + getreg32(priv->base + STM32_CAN_MSR_OFFSET), + getreg32(priv->base + STM32_CAN_TSR_OFFSET)); + + caninfo(" RF0R: %08" PRIx32 " RF1R: %08" PRIx32 "\n", + getreg32(priv->base + STM32_CAN_RF0R_OFFSET), + getreg32(priv->base + STM32_CAN_RF1R_OFFSET)); + + caninfo(" IER: %08" PRIx32 " ESR: %08" PRIx32 " BTR: %08" PRIx32 "\n", + getreg32(priv->base + STM32_CAN_IER_OFFSET), + getreg32(priv->base + STM32_CAN_ESR_OFFSET), + getreg32(priv->base + STM32_CAN_BTR_OFFSET)); +} +#endif + +/**************************************************************************** + * Name: stm32can_dumpmbregs + * + * Description: + * Dump the contents of all CAN mailbox registers + * + * Input Parameters: + * priv - A reference to the CAN block status + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_CAN_REGDEBUG +static void stm32can_dumpmbregs(struct stm32_can_s *priv, + const char *msg) +{ + if (msg) + { + caninfo("Mailbox Registers: %s\n", msg); + } + else + { + caninfo("Mailbox Registers:\n"); + } + + /* CAN mailbox registers (3 TX and 2 RX) */ + + caninfo(" TI0R: %08" PRIx32 " TDT0R: %08" PRIx32 " TDL0R: %08" + PRIx32 " TDH0R: %08" PRIx32 "\n", + getreg32(priv->base + STM32_CAN_TI0R_OFFSET), + getreg32(priv->base + STM32_CAN_TDT0R_OFFSET), + getreg32(priv->base + STM32_CAN_TDL0R_OFFSET), + getreg32(priv->base + STM32_CAN_TDH0R_OFFSET)); + + caninfo(" TI1R: %08" PRIx32 " TDT1R: %08" PRIx32 " TDL1R: %08" + PRIx32 " TDH1R: %08" PRIx32 "\n", + getreg32(priv->base + STM32_CAN_TI1R_OFFSET), + getreg32(priv->base + STM32_CAN_TDT1R_OFFSET), + getreg32(priv->base + STM32_CAN_TDL1R_OFFSET), + getreg32(priv->base + STM32_CAN_TDH1R_OFFSET)); + + caninfo(" TI2R: %08" PRIx32 " TDT2R: %08" PRIx32 " TDL2R: %08" + PRIx32 " TDH2R: %08" PRIx32 "\n", + getreg32(priv->base + STM32_CAN_TI2R_OFFSET), + getreg32(priv->base + STM32_CAN_TDT2R_OFFSET), + getreg32(priv->base + STM32_CAN_TDL2R_OFFSET), + getreg32(priv->base + STM32_CAN_TDH2R_OFFSET)); + + caninfo(" RI0R: %08" PRIx32 " RDT0R: %08" PRIx32 " RDL0R: %08" + PRIx32 " RDH0R: %08" PRIx32 "\n", + getreg32(priv->base + STM32_CAN_RI0R_OFFSET), + getreg32(priv->base + STM32_CAN_RDT0R_OFFSET), + getreg32(priv->base + STM32_CAN_RDL0R_OFFSET), + getreg32(priv->base + STM32_CAN_RDH0R_OFFSET)); + + caninfo(" RI1R: %08" PRIx32 " RDT1R: %08" PRIx32 " RDL1R: %08" + PRIx32 " RDH1R: %08" PRIx32 "\n", + getreg32(priv->base + STM32_CAN_RI1R_OFFSET), + getreg32(priv->base + STM32_CAN_RDT1R_OFFSET), + getreg32(priv->base + STM32_CAN_RDL1R_OFFSET), + getreg32(priv->base + STM32_CAN_RDH1R_OFFSET)); +} +#endif + +/**************************************************************************** + * Name: stm32can_dumpfiltregs + * + * Description: + * Dump the contents of all CAN filter registers + * + * Input Parameters: + * priv - A reference to the CAN block status + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_CAN_REGDEBUG +static void stm32can_dumpfiltregs(struct stm32_can_s *priv, + const char *msg) +{ + int i; + + if (msg) + { + caninfo("Filter Registers: %s\n", msg); + } + else + { + caninfo("Filter Registers:\n"); + } + + caninfo(" FMR: %08" PRIx32 " FM1R: %08" PRIx32 " FS1R: %08" + PRIx32 " FFA1R: %08" PRIx32 " FA1R: %08" PRIx32 "\n", + getreg32(priv->base + STM32_CAN_FMR_OFFSET), + getreg32(priv->base + STM32_CAN_FM1R_OFFSET), + getreg32(priv->base + STM32_CAN_FS1R_OFFSET), + getreg32(priv->base + STM32_CAN_FFA1R_OFFSET), + getreg32(priv->base + STM32_CAN_FA1R_OFFSET)); + + for (i = 0; i < CAN_NFILTERS; i++) + { + caninfo(" F%dR1: %08" PRIx32 " F%dR2: %08" PRIx32 "\n", + i, getreg32(priv->base + STM32_CAN_FIR_OFFSET(i, 1)), + i, getreg32(priv->base + STM32_CAN_FIR_OFFSET(i, 2))); + } +} +#endif + +/**************************************************************************** + * Name: stm32can_reset + * + * Description: + * Reset the CAN device. Called early to initialize the hardware. This + * function is called, before stm32can_setup() and on error conditions. + * + * Input Parameters: + * dev - An instance of the "upper half" can driver state structure. + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void stm32can_reset(struct can_dev_s *dev) +{ + struct stm32_can_s *priv = dev->cd_priv; + uint32_t regval; + uint32_t regbit = 0; + irqstate_t flags; + + caninfo("CAN%" PRIu8 "\n", priv->port); + + /* Get the bits in the AHB1RSTR register needed to reset this CAN device */ + +#ifdef CONFIG_STM32_CAN1 + if (priv->port == 1) + { + regbit = RCC_APB1RSTR_CAN1RST; + } + else +#endif +#ifdef CONFIG_STM32_CAN2 + if (priv->port == 2) + { + regbit = RCC_APB1RSTR_CAN2RST; + } + else +#endif + { + canerr("ERROR: Unsupported port %d\n", priv->port); + return; + } + + /* Disable interrupts momentarily to stop any ongoing CAN event processing + * and to prevent any concurrent access to the AHB1RSTR register. + */ + + flags = enter_critical_section(); + + /* Reset the CAN */ + + regval = getreg32(STM32_RCC_APB1RSTR); + regval |= regbit; + putreg32(regval, STM32_RCC_APB1RSTR); + + regval &= ~regbit; + putreg32(regval, STM32_RCC_APB1RSTR); + leave_critical_section(flags); +} + +/**************************************************************************** + * Name: stm32can_setup + * + * Description: + * Configure the CAN. This method is called the first time that the CAN + * device is opened. This will occur when the port is first opened. + * This setup includes configuring and attaching CAN interrupts. + * All CAN interrupts are disabled upon return. + * + * Input Parameters: + * dev - An instance of the "upper half" can driver state structure. + * + * Returned Value: + * Zero on success; a negated errno on failure + * + ****************************************************************************/ + +static int stm32can_setup(struct can_dev_s *dev) +{ + struct stm32_can_s *priv = dev->cd_priv; + int ret; + +#ifdef CONFIG_CAN_ERRORS + ninfo("CAN%" PRIu8 " RX0 irq: %" PRIu8 " RX1 irq: %" PRIu8 + " TX irq: %" PRIu8 " SCE irq: %" PRIu8 "\n", + priv->port, priv->canrx[0], priv->canrx[1], priv->cantx, + priv->cansce); +#else + ninfo("CAN%" PRIu8 " RX0 irq: %" PRIu8 " RX1 irq: %" PRIu8 + " TX irq: %" PRIu8 "\n", + priv->port, priv->canrx[0], priv->canrx[1], priv->cantx); +#endif + + /* CAN cell initialization */ + + ret = stm32can_cellinit(priv); + if (ret < 0) + { + canerr("ERROR: CAN%" PRId8 " cell initialization failed: %d\n", + priv->port, ret); + return ret; + } + + stm32can_dumpctrlregs(priv, "After cell initialization"); + stm32can_dumpmbregs(priv, NULL); + + /* CAN filter initialization */ + + ret = stm32can_filterinit(priv); + if (ret < 0) + { + canerr("ERROR: CAN%" PRIu8 " filter initialization failed: %d\n", + priv->port, ret); + return ret; + } + + stm32can_dumpfiltregs(priv, "After filter initialization"); + + /* Attach the CAN RX FIFO 0/1 interrupts and TX interrupts. + * The others are not used. + */ + + ret = irq_attach(priv->canrx[0], stm32can_rx0interrupt, dev); + if (ret < 0) + { + canerr("ERROR: Failed to attach CAN%" PRIu8 " RX0 IRQ (%" PRIu8 ")", + priv->port, priv->canrx[0]); + return ret; + } + + ret = irq_attach(priv->canrx[1], stm32can_rx1interrupt, dev); + if (ret < 0) + { + canerr("ERROR: Failed to attach CAN%" PRIu8 " RX1 IRQ (%" PRIu8 ")", + priv->port, priv->canrx[1]); + return ret; + } + + ret = irq_attach(priv->cantx, stm32can_txinterrupt, dev); + if (ret < 0) + { + canerr("ERROR: Failed to attach CAN%" PRIu8 " TX IRQ (%" PRIu8 ")", + priv->port, priv->cantx); + return ret; + } + +#ifdef CONFIG_CAN_ERRORS + ret = irq_attach(priv->cansce, stm32can_sceinterrupt, dev); + if (ret < 0) + { + nerr("ERROR: Failed to attach CAN%" PRIu8 " SCE IRQ (%" PRIu8 ")", + priv->port, priv->cansce); + return ret; + } + + /* Enable CAN error interrupts */ + + stm32can_errint(dev, true); +#endif + + /* Enable the interrupts at the NVIC. Interrupts are still disabled in + * the CAN module. Since we coming out of reset here, there should be + * no pending interrupts. + */ + + up_enable_irq(priv->canrx[0]); + up_enable_irq(priv->canrx[1]); + up_enable_irq(priv->cantx); +#ifdef CONFIG_CAN_ERRORS + up_enable_irq(priv->cansce); +#endif + return OK; +} + +/**************************************************************************** + * Name: stm32can_shutdown + * + * Description: + * Disable the CAN. This method is called when the CAN device is closed. + * This method reverses the operation the setup method. + * + * Input Parameters: + * dev - An instance of the "upper half" can driver state structure. + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void stm32can_shutdown(struct can_dev_s *dev) +{ + struct stm32_can_s *priv = dev->cd_priv; + + caninfo("CAN%" PRIu8 "\n", priv->port); + + /* Disable the RX FIFO 0/1, TX and SCE interrupts */ + + up_disable_irq(priv->canrx[0]); + up_disable_irq(priv->canrx[1]); + up_disable_irq(priv->cantx); +#ifdef CONFIG_CAN_ERRORS + up_disable_irq(priv->cansce); +#endif + + /* Detach the RX FIFO 0/1, TX and SCE interrupts */ + + irq_detach(priv->canrx[0]); + irq_detach(priv->canrx[1]); + irq_detach(priv->cantx); +#ifdef CONFIG_CAN_ERRORS + irq_detach(priv->cansce); +#endif + + /* And reset the hardware */ + + stm32can_reset(dev); +} + +/**************************************************************************** + * Name: stm32can_rxint + * + * Description: + * Call to enable or disable RX interrupts. + * + * Input Parameters: + * dev - An instance of the "upper half" can driver state structure. + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void stm32can_rxint(struct can_dev_s *dev, bool enable) +{ + struct stm32_can_s *priv = dev->cd_priv; + uint32_t regval; + + caninfo("CAN%" PRIu8 " rxint enable: %d\n", priv->port, enable); + + /* Enable/disable the FIFO 0/1 message pending interrupt */ + + regval = stm32can_getreg(priv, STM32_CAN_IER_OFFSET); + if (enable) + { + regval |= CAN_IER_FMPIE0 | CAN_IER_FMPIE1; + } + else + { + regval &= ~(CAN_IER_FMPIE0 | CAN_IER_FMPIE1); + } + + stm32can_putreg(priv, STM32_CAN_IER_OFFSET, regval); +} + +/**************************************************************************** + * Name: stm32can_txint + * + * Description: + * Call to enable or disable TX interrupts. + * + * Input Parameters: + * dev - An instance of the "upper half" can driver state structure. + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void stm32can_txint(struct can_dev_s *dev, bool enable) +{ + struct stm32_can_s *priv = dev->cd_priv; + uint32_t regval; + + caninfo("CAN%" PRIu8 " txint enable: %d\n", priv->port, enable); + + /* Support only disabling the transmit mailbox interrupt */ + + if (!enable) + { + regval = stm32can_getreg(priv, STM32_CAN_IER_OFFSET); + regval &= ~CAN_IER_TMEIE; + stm32can_putreg(priv, STM32_CAN_IER_OFFSET, regval); + } +} + +#ifdef CONFIG_CAN_ERRORS +/**************************************************************************** + * Name: stm32can_errint + * + * Description: + * Call to enable or disable CAN error interrupts. + * + * Input Parameters: + * dev - An instance of the "upper half" can driver state structure. + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void stm32can_errint(struct can_dev_s *dev, bool enable) +{ + struct stm32_can_s *priv = dev->cd_priv; + uint32_t regval = 0; + + caninfo("CAN%" PRIu8 " errint enable: %d\n", priv->port, enable); + + /* Enable/disable the transmit mailbox interrupt */ + + regval = stm32can_getreg(priv, STM32_CAN_IER_OFFSET); + if (enable) + { + regval |= STM32_CAN_ERRINT; + } + else + { + regval &= ~STM32_CAN_ERRINT; + } + + stm32can_putreg(priv, STM32_CAN_IER_OFFSET, regval); +} +#endif + +/**************************************************************************** + * Name: stm32can_ioctl + * + * Description: + * All ioctl calls will be routed through this method + * + * Input Parameters: + * dev - An instance of the "upper half" can driver state structure. + * + * Returned Value: + * Zero on success; a negated errno on failure + * + ****************************************************************************/ + +static int stm32can_ioctl(struct can_dev_s *dev, int cmd, + unsigned long arg) +{ + struct stm32_can_s *priv; + int ret = -ENOTTY; + + caninfo("cmd=%04x arg=%lu\n", cmd, arg); + + DEBUGASSERT(dev && dev->cd_priv); + priv = dev->cd_priv; + + /* Handle the command */ + + switch (cmd) + { + /* CANIOC_GET_BITTIMING: + * Description: Return the current bit timing settings + * Argument: A pointer to a write-able instance of struct + * canioc_bittiming_s in which current bit timing + * values will be returned. + * Returned Value: Zero (OK) is returned on success. Otherwise -1 + * (ERROR) is returned with the errno variable set + * to indicate the nature of the error. + * Dependencies: None + */ + + case CANIOC_GET_BITTIMING: + { + struct canioc_bittiming_s *bt = + (struct canioc_bittiming_s *)arg; + uint32_t regval; + uint32_t brp; + + DEBUGASSERT(bt != NULL); + regval = stm32can_getreg(priv, STM32_CAN_BTR_OFFSET); + bt->bt_sjw = ((regval & CAN_BTR_SJW_MASK) >> + CAN_BTR_SJW_SHIFT) + 1; + bt->bt_tseg1 = ((regval & CAN_BTR_TS1_MASK) >> + CAN_BTR_TS1_SHIFT) + 1; + bt->bt_tseg2 = ((regval & CAN_BTR_TS2_MASK) >> + CAN_BTR_TS2_SHIFT) + 1; + + brp = ((regval & CAN_BTR_BRP_MASK) >> + CAN_BTR_BRP_SHIFT) + 1; + bt->bt_baud = STM32_PCLK1_FREQUENCY / + (brp * (bt->bt_tseg1 + bt->bt_tseg2 + 1)); + ret = OK; + } + break; + + /* CANIOC_SET_BITTIMING: + * Description: Set new current bit timing values + * Argument: A pointer to a read-able instance of struct + * canioc_bittiming_s in which the new bit timing + * values are provided. + * Returned Value: Zero (OK) is returned on success. Otherwise -1 + * (ERROR)is returned with the errno variable set + * to indicate thenature of the error. + * Dependencies: None + * + * REVISIT: There is probably a limitation here: If there are + * multiple threads trying to send CAN packets, when one of these + * threads reconfigures the bitrate, the MCAN hardware will be reset + * and the context of operation will be lost. Hence, this IOCTL can + * only safely be executed in quiescent time periods. + */ + + case CANIOC_SET_BITTIMING: + { + const struct canioc_bittiming_s *bt = + (const struct canioc_bittiming_s *)arg; + uint32_t brp; + uint32_t can_bit_quanta; + uint32_t tmp; + uint32_t regval; + + DEBUGASSERT(bt != NULL); + DEBUGASSERT(bt->bt_baud < STM32_PCLK1_FREQUENCY); + DEBUGASSERT(bt->bt_sjw > 0 && bt->bt_sjw <= 4); + DEBUGASSERT(bt->bt_tseg1 > 0 && bt->bt_tseg1 <= 16); + DEBUGASSERT(bt->bt_tseg2 > 0 && bt->bt_tseg2 <= 8); + + regval = stm32can_getreg(priv, STM32_CAN_BTR_OFFSET); + + /* Extract bit timing data + * tmp is in clocks per bit time + */ + + tmp = STM32_PCLK1_FREQUENCY / bt->bt_baud; + + /* This value is dynamic as requested by user */ + + can_bit_quanta = bt->bt_tseg1 + bt->bt_tseg2 + 1; + + if (tmp < can_bit_quanta) + { + /* This timing is not possible */ + + ret = -EINVAL; + break; + } + + /* Otherwise, nquanta is can_bit_quanta, ts1 and ts2 are + * provided by the user and we calculate brp to achieve + * can_bit_quanta quanta in the bit times + */ + + else + { + brp = (tmp + (can_bit_quanta / 2)) / can_bit_quanta; + DEBUGASSERT(brp >= 1 && brp <= CAN_BTR_BRP_MAX); + } + + caninfo("TS1: %"PRIu8 " TS2: %" PRIu8 " BRP: %" PRIu32 "\n", + bt->bt_tseg1, bt->bt_tseg2, brp); + + /* Configure bit timing. */ + + regval &= ~(CAN_BTR_BRP_MASK | CAN_BTR_TS1_MASK | + CAN_BTR_TS2_MASK | CAN_BTR_SJW_MASK); + regval |= ((brp - 1) << CAN_BTR_BRP_SHIFT) | + ((bt->bt_tseg1 - 1) << CAN_BTR_TS1_SHIFT) | + ((bt->bt_tseg2 - 1) << CAN_BTR_TS2_SHIFT) | + ((bt->bt_sjw - 1) << CAN_BTR_SJW_SHIFT); + + /* Bit timing can only be configured in init mode. */ + + ret = stm32can_enterinitmode(priv); + if (ret < 0) + { + break; + } + + stm32can_putreg(priv, STM32_CAN_BTR_OFFSET, regval); + + ret = stm32can_exitinitmode(priv); + if (ret >= 0) + { + priv->baud = STM32_PCLK1_FREQUENCY / + (brp * (bt->bt_tseg1 + bt->bt_tseg2 + 1)); + } + } + break; + + /* CANIOC_GET_CONNMODES: + * Description: Get the current bus connection modes + * Argument: A pointer to a write-able instance of struct + * canioc_connmodes_s in which the new bus modes will + * be returned. + * Returned Value: Zero (OK) is returned on success. Otherwise -1 + * (ERROR)is returned with the errno variable set + * to indicate the nature of the error. + * Dependencies: None + */ + + case CANIOC_GET_CONNMODES: + { + struct canioc_connmodes_s *bm = + (struct canioc_connmodes_s *)arg; + uint32_t regval; + + DEBUGASSERT(bm != NULL); + + regval = stm32can_getreg(priv, STM32_CAN_BTR_OFFSET); + + bm->bm_loopback = ((regval & CAN_BTR_LBKM) == CAN_BTR_LBKM); + bm->bm_silent = ((regval & CAN_BTR_SILM) == CAN_BTR_SILM); + ret = OK; + break; + } + + /* CANIOC_SET_CONNMODES: + * Description: Set new bus connection modes values + * Argument: A pointer to a read-able instance of struct + * canioc_connmodes_s in which the new bus modes + * are provided. + * Returned Value: Zero (OK) is returned on success. Otherwise -1 + * (ERROR) is returned with the errno variable set + * to indicate the nature of the error. + * Dependencies: None + */ + + case CANIOC_SET_CONNMODES: + { + struct canioc_connmodes_s *bm = + (struct canioc_connmodes_s *)arg; + uint32_t regval; + + DEBUGASSERT(bm != NULL); + + regval = stm32can_getreg(priv, STM32_CAN_BTR_OFFSET); + + if (bm->bm_loopback) + { + regval |= CAN_BTR_LBKM; + } + else + { + regval &= ~CAN_BTR_LBKM; + } + + if (bm->bm_silent) + { + regval |= CAN_BTR_SILM; + } + else + { + regval &= ~CAN_BTR_SILM; + } + + /* This register can only be configured in init mode. */ + + ret = stm32can_enterinitmode(priv); + if (ret < 0) + { + break; + } + + stm32can_putreg(priv, STM32_CAN_BTR_OFFSET, regval); + + ret = stm32can_exitinitmode(priv); + } + break; + +#ifdef CONFIG_CAN_EXTID + /* CANIOC_ADD_EXTFILTER: + * Description: Add an address filter for a extended 29 bit + * address. + * Argument: A reference to struct canioc_extfilter_s + * Returned Value: A non-negative filter ID is returned on success. + * Otherwise -1 (ERROR) is returned with the errno + * variable set to indicate the nature of the error. + */ + + case CANIOC_ADD_EXTFILTER: + { + DEBUGASSERT(arg != 0); + ret = stm32can_addextfilter(priv, + (struct canioc_extfilter_s *)arg); + } + break; + + /* CANIOC_DEL_EXTFILTER: + * Description: Remove an address filter for a standard 29 bit + * address. + * Argument: The filter index previously returned by the + * CANIOC_ADD_EXTFILTER command + * Returned Value: Zero (OK) is returned on success. Otherwise -1 + * (ERROR)is returned with the errno variable set + * to indicate the nature of the error. + */ + + case CANIOC_DEL_EXTFILTER: + { +#if 0 /* Unimplemented */ + DEBUGASSERT(arg <= priv->config->nextfilters); +#endif + ret = stm32can_delextfilter(priv, (int)arg); + } + break; +#endif + + /* CANIOC_ADD_STDFILTER: + * Description: Add an address filter for a standard 11 bit + * address. + * Argument: A reference to struct canioc_stdfilter_s + * Returned Value: A non-negative filter ID is returned on success. + * Otherwise -1 (ERROR) is returned with the errno + * variable set to indicate the nature of the error. + */ + + case CANIOC_ADD_STDFILTER: + { + DEBUGASSERT(arg != 0); + ret = stm32can_addstdfilter(priv, + (struct canioc_stdfilter_s *)arg); + } + break; + + /* CANIOC_DEL_STDFILTER: + * Description: Remove an address filter for a standard 11 bit + * address. + * Argument: The filter index previously returned by the + * CANIOC_ADD_STDFILTER command + * Returned Value: Zero (OK) is returned on success. Otherwise -1 + * (ERROR) is returned with the errno variable set + * to indicate the nature of the error. + */ + + case CANIOC_DEL_STDFILTER: + { +#if 0 /* Unimplemented */ + DEBUGASSERT(arg <= priv->config->nstdfilters); +#endif + ret = stm32can_delstdfilter(priv, (int)arg); + } + break; + + case CANIOC_SET_NART: + { + uint32_t regval; + + ret = stm32can_enterinitmode(priv); + if (ret != 0) + { + return ret; + } + + regval = stm32can_getreg(priv, STM32_CAN_MCR_OFFSET); + if (arg == 1) + { + regval |= CAN_MCR_NART; + } + else + { + regval &= ~CAN_MCR_NART; + } + + stm32can_putreg(priv, STM32_CAN_MCR_OFFSET, regval); + return stm32can_exitinitmode(priv); + } + break; + + case CANIOC_SET_ABOM: + { + uint32_t regval; + + ret = stm32can_enterinitmode(priv); + if (ret != 0) + { + return ret; + } + + regval = stm32can_getreg(priv, STM32_CAN_MCR_OFFSET); + if (arg == 1) + { + regval |= CAN_MCR_ABOM; + } + else + { + regval &= ~CAN_MCR_ABOM; + } + + stm32can_putreg(priv, STM32_CAN_MCR_OFFSET, regval); + return stm32can_exitinitmode(priv); + } + break; + + /* Unsupported/unrecognized command */ + + default: + canerr("ERROR: Unrecognized command: %04x\n", cmd); + break; + } + + return ret; +} + +/**************************************************************************** + * Name: stm32can_remoterequest + * + * Description: + * Send a remote request + * + * Input Parameters: + * dev - An instance of the "upper half" can driver state structure. + * + * Returned Value: + * Zero on success; a negated errno on failure + * + ****************************************************************************/ + +static int stm32can_remoterequest(struct can_dev_s *dev, uint16_t id) +{ +#warning "Remote request not implemented" + return -ENOSYS; +} + +/**************************************************************************** + * Name: stm32can_send + * + * Description: + * Send one can message. + * + * One CAN-message consists of a maximum of 10 bytes. A message is + * composed of at least the first 2 bytes (when there are no data bytes). + * + * Byte 0: Bits 0-7: Bits 3-10 of the 11-bit CAN identifier + * Byte 1: Bits 5-7: Bits 0-2 of the 11-bit CAN identifier + * Bit 4: Remote Transmission Request (RTR) + * Bits 0-3: Data Length Code (DLC) + * Bytes 2-10: CAN data + * + * Input Parameters: + * dev - An instance of the "upper half" can driver state structure. + * + * Returned Value: + * Zero on success; a negated errno on failure + * + ****************************************************************************/ + +static int stm32can_send(struct can_dev_s *dev, + struct can_msg_s *msg) +{ + struct stm32_can_s *priv = dev->cd_priv; + uint8_t *ptr; + uint32_t regval; + uint32_t tmp; + int dlc; + int txmb; + + caninfo("CAN%" PRIu8 " ID: %" PRIu32 " DLC: %" PRIu8 "\n", + priv->port, (uint32_t)msg->cm_hdr.ch_id, msg->cm_hdr.ch_dlc); + + /* Select one empty transmit mailbox */ + + regval = stm32can_getreg(priv, STM32_CAN_TSR_OFFSET); + if (stm32can_txmb0empty(regval)) + { + txmb = 0; + } + else if (stm32can_txmb1empty(regval)) + { + txmb = 1; + } + else if (stm32can_txmb2empty(regval)) + { + txmb = 2; + } + else + { + canerr("ERROR: No available mailbox\n"); + return -EBUSY; + } + + /* Clear TXRQ, RTR, IDE, EXID, and STID fields */ + + regval = stm32can_getreg(priv, STM32_CAN_TIR_OFFSET(txmb)); + regval &= ~(CAN_TIR_TXRQ | CAN_TIR_RTR | CAN_TIR_IDE | + CAN_TIR_EXID_MASK | CAN_TIR_STID_MASK); + stm32can_putreg(priv, STM32_CAN_TIR_OFFSET(txmb), regval); + + /* Set up the ID, standard 11-bit or extended 29-bit. */ + +#ifdef CONFIG_CAN_EXTID + regval &= ~CAN_TIR_EXID_MASK; + if (msg->cm_hdr.ch_extid) + { + DEBUGASSERT(msg->cm_hdr.ch_id < (1 << 29)); + regval |= (msg->cm_hdr.ch_id << CAN_TIR_EXID_SHIFT) | CAN_TIR_IDE; + } + else + { + DEBUGASSERT(msg->cm_hdr.ch_id < (1 << 11)); + regval |= msg->cm_hdr.ch_id << CAN_TIR_STID_SHIFT; + } + +#else + regval |= (((uint32_t) msg->cm_hdr.ch_id << CAN_TIR_STID_SHIFT) & + CAN_TIR_STID_MASK); + +#endif + +#ifdef CONFIG_CAN_USE_RTR + regval |= (msg->cm_hdr.ch_rtr ? CAN_TIR_RTR : 0); +#endif + + stm32can_putreg(priv, STM32_CAN_TIR_OFFSET(txmb), regval); + + /* Set up the DLC */ + + dlc = msg->cm_hdr.ch_dlc; + regval = stm32can_getreg(priv, STM32_CAN_TDTR_OFFSET(txmb)); + regval &= ~(CAN_TDTR_DLC_MASK | CAN_TDTR_TGT); + regval |= (uint32_t)dlc << CAN_TDTR_DLC_SHIFT; + stm32can_putreg(priv, STM32_CAN_TDTR_OFFSET(txmb), regval); + + /* Set up the data fields */ + + ptr = msg->cm_data; + regval = 0; + + if (dlc > 0) + { + tmp = (uint32_t)*ptr++; + regval = tmp << CAN_TDLR_DATA0_SHIFT; + + if (dlc > 1) + { + tmp = (uint32_t)*ptr++; + regval |= tmp << CAN_TDLR_DATA1_SHIFT; + + if (dlc > 2) + { + tmp = (uint32_t)*ptr++; + regval |= tmp << CAN_TDLR_DATA2_SHIFT; + + if (dlc > 3) + { + tmp = (uint32_t)*ptr++; + regval |= tmp << CAN_TDLR_DATA3_SHIFT; + } + } + } + } + + stm32can_putreg(priv, STM32_CAN_TDLR_OFFSET(txmb), regval); + + regval = 0; + if (dlc > 4) + { + tmp = (uint32_t)*ptr++; + regval = tmp << CAN_TDHR_DATA4_SHIFT; + + if (dlc > 5) + { + tmp = (uint32_t)*ptr++; + regval |= tmp << CAN_TDHR_DATA5_SHIFT; + + if (dlc > 6) + { + tmp = (uint32_t)*ptr++; + regval |= tmp << CAN_TDHR_DATA6_SHIFT; + + if (dlc > 7) + { + tmp = (uint32_t)*ptr++; + regval |= tmp << CAN_TDHR_DATA7_SHIFT; + } + } + } + } + + stm32can_putreg(priv, STM32_CAN_TDHR_OFFSET(txmb), regval); + + /* Enable the transmit mailbox empty interrupt (may already be enabled) */ + + regval = stm32can_getreg(priv, STM32_CAN_IER_OFFSET); + regval |= CAN_IER_TMEIE; + stm32can_putreg(priv, STM32_CAN_IER_OFFSET, regval); + + /* Request transmission */ + + regval = stm32can_getreg(priv, STM32_CAN_TIR_OFFSET(txmb)); + regval |= CAN_TIR_TXRQ; /* Transmit Mailbox Request */ + stm32can_putreg(priv, STM32_CAN_TIR_OFFSET(txmb), regval); + + stm32can_dumpmbregs(priv, "After send"); + return OK; +} + +/**************************************************************************** + * Name: stm32can_txready + * + * Description: + * Return true if the CAN hardware can accept another TX message. + * + * Input Parameters: + * dev - An instance of the "upper half" can driver state structure. + * + * Returned Value: + * True if the CAN hardware is ready to accept another TX message. + * + ****************************************************************************/ + +static bool stm32can_txready(struct can_dev_s *dev) +{ + struct stm32_can_s *priv = dev->cd_priv; + uint32_t regval; + + /* Return true if any mailbox is available */ + + regval = stm32can_getreg(priv, STM32_CAN_TSR_OFFSET); + caninfo("CAN%" PRIu8 " TSR: %08" PRIx32 "\n", priv->port, regval); + + return stm32can_txmb0empty(regval) || stm32can_txmb1empty(regval) || + stm32can_txmb2empty(regval); +} + +/**************************************************************************** + * Name: stm32can_txempty + * + * Description: + * Return true if all message have been sent. If for example, the CAN + * hardware implements FIFOs, then this would mean the transmit FIFO is + * empty. This method is called when the driver needs to make sure that + * all characters are "drained" from the TX hardware before calling + * co_shutdown(). + * + * Input Parameters: + * dev - An instance of the "upper half" can driver state structure. + * + * Returned Value: + * True if there are no pending TX transfers in the CAN hardware. + * + ****************************************************************************/ + +static bool stm32can_txempty(struct can_dev_s *dev) +{ + struct stm32_can_s *priv = dev->cd_priv; + uint32_t regval; + + /* Return true if all mailboxes are available */ + + regval = stm32can_getreg(priv, STM32_CAN_TSR_OFFSET); + caninfo("CAN%" PRIu8 " TSR: %08" PRIx32 "\n", priv->port, regval); + + return stm32can_txmb0empty(regval) && stm32can_txmb1empty(regval) && + stm32can_txmb2empty(regval); +} + +/**************************************************************************** + * Name: stm32can_rxinterrupt + * + * Description: + * CAN RX FIFO 0/1 interrupt handler + * + * Input Parameters: + * irq - The IRQ number of the interrupt. + * context - The register state save array at the time of the interrupt. + * rxmb - The RX mailbox number. + * + * Returned Value: + * Zero on success; a negated errno on failure + * + ****************************************************************************/ + +static int stm32can_rxinterrupt(struct can_dev_s *dev, int rxmb) +{ + struct stm32_can_s *priv; + struct can_hdr_s hdr; + uint8_t data[CAN_MAXDATALEN]; + uint32_t regval; + int npending; + int ret; + + DEBUGASSERT(dev != NULL && dev->cd_priv != NULL); + priv = dev->cd_priv; + + /* Verify that a message is pending in the FIFO */ + + regval = stm32can_getreg(priv, STM32_CAN_RFR_OFFSET(rxmb)); + npending = (regval & CAN_RFR_FMP_MASK) >> CAN_RFR_FMP_SHIFT; + if (npending < 1) + { + canwarn("WARNING: No messages pending\n"); + return OK; + } + + if (rxmb == 0) + { + stm32can_dumpmbregs(priv, "RX0 interrupt"); + } + else + { + stm32can_dumpmbregs(priv, "RX1 interrupt"); + } + + /* Get the CAN identifier. */ + + regval = stm32can_getreg(priv, STM32_CAN_RIR_OFFSET(rxmb)); + +#ifdef CONFIG_CAN_EXTID + if ((regval & CAN_RIR_IDE) != 0) + { + hdr.ch_id = (regval & CAN_RIR_EXID_MASK) >> CAN_RIR_EXID_SHIFT; + hdr.ch_extid = true; + } + else + { + hdr.ch_id = (regval & CAN_RIR_STID_MASK) >> CAN_RIR_STID_SHIFT; + hdr.ch_extid = false; + } +#else + if ((regval & CAN_RIR_IDE) != 0) + { + canerr("ERROR: Received message with extended identifier. Dropped\n"); + ret = -ENOSYS; + goto errout; + } + + hdr.ch_id = (regval & CAN_RIR_STID_MASK) >> CAN_RIR_STID_SHIFT; +#endif + + /* Clear the error indication and unused bits */ + +#ifdef CONFIG_CAN_ERRORS + hdr.ch_error = 0; /* Error reporting not supported */ +#endif + hdr.ch_tcf = 0; + + /* Extract the RTR bit */ + + hdr.ch_rtr = (regval & CAN_RIR_RTR) != 0; + + /* Get the DLC */ + + regval = stm32can_getreg(priv, STM32_CAN_RDTR_OFFSET(rxmb)); + hdr.ch_dlc = (regval & CAN_RDTR_DLC_MASK) >> CAN_RDTR_DLC_SHIFT; + + /* Save the message data */ + + regval = stm32can_getreg(priv, STM32_CAN_RDLR_OFFSET(rxmb)); + data[0] = (regval & CAN_RDLR_DATA0_MASK) >> CAN_RDLR_DATA0_SHIFT; + data[1] = (regval & CAN_RDLR_DATA1_MASK) >> CAN_RDLR_DATA1_SHIFT; + data[2] = (regval & CAN_RDLR_DATA2_MASK) >> CAN_RDLR_DATA2_SHIFT; + data[3] = (regval & CAN_RDLR_DATA3_MASK) >> CAN_RDLR_DATA3_SHIFT; + + regval = stm32can_getreg(priv, STM32_CAN_RDHR_OFFSET(rxmb)); + data[4] = (regval & CAN_RDHR_DATA4_MASK) >> CAN_RDHR_DATA4_SHIFT; + data[5] = (regval & CAN_RDHR_DATA5_MASK) >> CAN_RDHR_DATA5_SHIFT; + data[6] = (regval & CAN_RDHR_DATA6_MASK) >> CAN_RDHR_DATA6_SHIFT; + data[7] = (regval & CAN_RDHR_DATA7_MASK) >> CAN_RDHR_DATA7_SHIFT; + + /* Provide the data to the upper half driver */ + + ret = can_receive(dev, &hdr, data); + + /* Release the FIFO */ + +#ifndef CONFIG_CAN_EXTID +errout: +#endif + regval = stm32can_getreg(priv, STM32_CAN_RFR_OFFSET(rxmb)); + regval |= CAN_RFR_RFOM; + stm32can_putreg(priv, STM32_CAN_RFR_OFFSET(rxmb), regval); + return ret; +} + +/**************************************************************************** + * Name: stm32can_rx0interrupt + * + * Description: + * CAN RX FIFO 0 interrupt handler + * + * Input Parameters: + * irq - The IRQ number of the interrupt. + * context - The register state save array at the time of the interrupt. + * + * Returned Value: + * Zero on success; a negated errno on failure + * + ****************************************************************************/ + +static int stm32can_rx0interrupt(int irq, void *context, void *arg) +{ + struct can_dev_s *dev = (struct can_dev_s *)arg; + return stm32can_rxinterrupt(dev, 0); +} + +/**************************************************************************** + * Name: stm32can_rx1interrupt + * + * Description: + * CAN RX FIFO 1 interrupt handler + * + * Input Parameters: + * irq - The IRQ number of the interrupt. + * context - The register state save array at the time of the interrupt. + * + * Returned Value: + * Zero on success; a negated errno on failure + * + ****************************************************************************/ + +static int stm32can_rx1interrupt(int irq, void *context, void *arg) +{ + struct can_dev_s *dev = (struct can_dev_s *)arg; + return stm32can_rxinterrupt(dev, 1); +} + +/**************************************************************************** + * Name: stm32can_txinterrupt + * + * Description: + * CAN TX mailbox complete interrupt handler + * + * Input Parameters: + * irq - The IRQ number of the interrupt. + * context - The register state save array at the time of the interrupt. + * + * Returned Value: + * Zero on success; a negated errno on failure + * + ****************************************************************************/ + +static int stm32can_txinterrupt(int irq, void *context, void *arg) +{ + struct can_dev_s *dev = (struct can_dev_s *)arg; + struct stm32_can_s *priv; + uint32_t regval; + + DEBUGASSERT(dev != NULL && dev->cd_priv != NULL); + priv = dev->cd_priv; + + /* Get the transmit status */ + + regval = stm32can_getreg(priv, STM32_CAN_TSR_OFFSET); + + /* Check for RQCP0: Request completed mailbox 0 */ + + if ((regval & CAN_TSR_RQCP0) != 0) + { + /* Writing '1' to RCP0 clears RCP0 and all the status bits (TXOK0, + * ALST0 and TERR0) for Mailbox 0. + */ + + stm32can_putreg(priv, STM32_CAN_TSR_OFFSET, CAN_TSR_RQCP0); + + /* Tell the upper half that the transfer is finished. */ + + can_txdone(dev); + } + + /* Check for RQCP1: Request completed mailbox 1 */ + + if ((regval & CAN_TSR_RQCP1) != 0) + { + /* Writing '1' to RCP1 clears RCP1 and all the status bits (TXOK1, + * ALST1 and TERR1) for Mailbox 1. + */ + + stm32can_putreg(priv, STM32_CAN_TSR_OFFSET, CAN_TSR_RQCP1); + + /* Tell the upper half that the transfer is finished. */ + + can_txdone(dev); + } + + /* Check for RQCP2: Request completed mailbox 2 */ + + if ((regval & CAN_TSR_RQCP2) != 0) + { + /* Writing '1' to RCP2 clears RCP2 and all the status bits (TXOK2, + * ALST2 and TERR2) for Mailbox 2. + */ + + stm32can_putreg(priv, STM32_CAN_TSR_OFFSET, CAN_TSR_RQCP2); + + /* Tell the upper half that the transfer is finished. */ + + can_txdone(dev); + } + + return OK; +} + +#ifdef CONFIG_CAN_ERRORS +/**************************************************************************** + * Name: stm32can_sceinterrupt + * + * Description: + * CAN status change interrupt handler + * + * Input Parameters: + * irq - The IRQ number of the interrupt. + * context - The register state save array at the time of the interrupt. + * + * Returned Value: + * Zero on success; a negated errno on failure + * + ****************************************************************************/ + +static int stm32can_sceinterrupt(int irq, void *context, void *arg) +{ + struct can_dev_s *dev = (struct can_dev_s *)arg; + struct stm32_can_s *priv = NULL; + struct can_hdr_s hdr; + uint32_t regval = 0; + uint16_t errbits = 0; + uint8_t data[CAN_ERROR_DLC]; + int ret = OK; + + DEBUGASSERT(dev != NULL && dev->cd_priv != NULL); + priv = dev->cd_priv; + + /* Check Error Interrupt flag */ + + regval = stm32can_getreg(priv, STM32_CAN_MSR_OFFSET); + if (regval & CAN_MSR_ERRI) + { + /* Encode error bits */ + + errbits = 0; + memset(data, 0, sizeof(data)); + + /* Get Error statur register */ + + regval = stm32can_getreg(priv, STM32_CAN_ESR_OFFSET); + + if (regval & CAN_ESR_EWGF) + { + /* Error warning flag */ + + data[1] |= (CAN_ERROR1_RXWARNING | CAN_ERROR1_TXWARNING); + errbits |= CAN_ERROR_CONTROLLER; + } + + if (regval & CAN_ESR_EPVF) + { + /* Error passive flag */ + + data[1] |= (CAN_ERROR1_RXPASSIVE | CAN_ERROR1_TXPASSIVE); + errbits |= CAN_ERROR_CONTROLLER; + } + + if (regval & CAN_ESR_BOFF) + { + /* Bus-off flag */ + + errbits |= CAN_ERROR_BUSOFF; + } + + /* Last error code */ + + if (regval & CAN_ESR_LEC_MASK) + { + if (regval & CAN_ESR_STUFFERROR) + { + /* Stuff Error */ + + errbits |= CAN_ERROR_PROTOCOL; + data[2] |= CAN_ERROR2_STUFF; + } + else if (regval & CAN_ESR_FORMERROR) + { + /* Format Error */ + + errbits |= CAN_ERROR_PROTOCOL; + data[2] |= CAN_ERROR2_FORM; + } + else if (regval & CAN_ESR_ACKERROR) + { + /* Acknowledge Error */ + + errbits |= CAN_ERROR_NOACK; + } + else if (regval & CAN_ESR_BRECERROR) + { + /* Bit recessive Error */ + + errbits |= CAN_ERROR_PROTOCOL; + data[2] |= CAN_ERROR2_BIT1; + } + else if (regval & CAN_ESR_BDOMERROR) + { + /* Bit dominant Error */ + + errbits |= CAN_ERROR_PROTOCOL; + data[2] |= CAN_ERROR2_BIT0; + } + else if (regval & CAN_ESR_CRCERRPR) + { + /* Receive CRC Error */ + + errbits |= CAN_ERROR_PROTOCOL; + data[3] |= CAN_ERROR3_CRCSEQ; + } + } + + /* Get transmit status register */ + + regval = stm32can_getreg(priv, STM32_CAN_TSR_OFFSET); + + if (regval & CAN_TSR_ALST0 || regval & CAN_TSR_ALST1 || + regval & CAN_TSR_ALST2) + { + /* Lost arbitration Error */ + + errbits |= CAN_ERROR_LOSTARB; + } + + /* Clear TSR register */ + + stm32can_putreg(priv, STM32_CAN_TSR_OFFSET, regval); + + /* Clear ERRI flag */ + + stm32can_putreg(priv, STM32_CAN_MSR_OFFSET, CAN_MSR_ERRI); + } + + /* TODO: RX overflow and TX overflow */ + + /* Report a CAN error */ + + if (errbits != 0) + { + canerr("ERROR: errbits = %08" PRIx16 "\n", errbits); + + /* Format the CAN header for the error report. */ + + hdr.ch_id = errbits; + hdr.ch_dlc = CAN_ERROR_DLC; + hdr.ch_rtr = 0; + hdr.ch_error = 1; +#ifdef CONFIG_CAN_EXTID + hdr.ch_extid = 0; +#endif + hdr.ch_tcf = 0; + + /* And provide the error report to the upper half logic */ + + ret = can_receive(dev, &hdr, data); + if (ret < 0) + { + canerr("ERROR: can_receive failed: %d\n", ret); + } + } + + return ret; +} +#endif + +/**************************************************************************** + * Name: stm32can_bittiming + * + * Description: + * Set the CAN bit timing register (BTR) based on the configured BAUD. + * + * "The bit timing logic monitors the serial bus-line and performs sampling + * and adjustment of the sample point by synchronizing on the start-bit edge + * and resynchronizing on the following edges. + * + * "Its operation may be explained simply by splitting nominal bit time into + * three segments as follows: + * + * 1. "Synchronization segment (SYNC_SEG): a bit change is expected to occur + * within this time segment. It has a fixed length of one time quantum + * (1 x tCAN). + * 2. "Bit segment 1 (BS1): defines the location of the sample point. It + * includes the PROP_SEG and PHASE_SEG1 of the CAN standard. Its duration + * is programmable between 1 and 16 time quanta but may be automatically + * lengthened to compensate for positive phase drifts due to differences + * in the frequency of the various nodes of the network. + * 3. "Bit segment 2 (BS2): defines the location of the transmit point. It + * represents the PHASE_SEG2 of the CAN standard. Its duration is + * programmable between 1 and 8 time quanta but may also be automatically + * shortened to compensate for negative phase drifts." + * + * Pictorially: + * + * |<----------------- NOMINAL BIT TIME ----------------->| + * |<- SYNC_SEG ->|<------ BS1 ------>|<------ BS2 ------>| + * |<---- Tq ---->|<----- Tbs1 ------>|<----- Tbs2 ------>| + * + * Where + * Tbs1 is the duration of the BS1 segment + * Tbs2 is the duration of the BS2 segment + * Tq is the "Time Quantum" + * + * Relationships: + * + * baud = 1 / bit_time + * bit_time = Tq + Tbs1 + Tbs2 + * Tbs1 = Tq * ts1 + * Tbs2 = Tq * ts2 + * Tq = brp * Tpclk1 + * baud = Fpclk1 / (brp * (1 + ts1 + ts2)) + * + * Where: + * Tpclk1 is the period of the APB1 clock (PCLK1). + * + * Input Parameters: + * priv - A reference to the CAN block status + * + * Returned Value: + * Zero on success; a negated errno on failure + * + ****************************************************************************/ + +static int stm32can_bittiming(struct stm32_can_s *priv) +{ + uint32_t tmp; + uint32_t brp; + uint32_t ts1; + uint32_t ts2; + + caninfo("CAN%" PRIu8 " PCLK1: %lu baud: %" PRIu32 "\n", + priv->port, (unsigned long) STM32_PCLK1_FREQUENCY, priv->baud); + + /* Try to get CAN_BIT_QUANTA quanta in one bit_time. + * + * bit_time = Tq*(ts1 + ts2 + 1) + * nquanta = bit_time / Tq + * nquanta = (ts1 + ts2 + 1) + * + * bit_time = brp * Tpclk1 * (ts1 + ts2 + 1) + * nquanta = bit_time / brp / Tpclk1 + * = PCLK1 / baud / brp + * brp = PCLK1 / baud / nquanta; + * + * Example: + * PCLK1 = 42,000,000 baud = 1,000,000 nquanta = 14 : brp = 3 + * PCLK1 = 42,000,000 baud = 700,000 nquanta = 14 : brp = 4 + */ + + tmp = STM32_PCLK1_FREQUENCY / priv->baud; + if (tmp < CAN_BIT_QUANTA) + { + /* At the smallest brp value (1), there are already too few bit times + * (PCLCK1 / baud) to meet our goal. brp must be one and we need + * make some reasonable guesses about ts1 and ts2. + */ + + brp = 1; + + /* In this case, we have to guess a good value for ts1 and ts2 */ + + ts1 = (tmp - 1) >> 1; + ts2 = tmp - ts1 - 1; + if (ts1 == ts2 && ts1 > 1 && ts2 < CAN_BTR_TSEG2_MAX) + { + ts1--; + ts2++; + } + } + + /* Otherwise, nquanta is CAN_BIT_QUANTA, ts1 is CONFIG_STM32_CAN_TSEG1, + * ts2 is CONFIG_STM32_CAN_TSEG2 and we calculate brp to achieve + * CAN_BIT_QUANTA quanta in the bit time + */ + + else + { + ts1 = CONFIG_STM32_CAN_TSEG1; + ts2 = CONFIG_STM32_CAN_TSEG2; + brp = (tmp + (CAN_BIT_QUANTA / 2)) / CAN_BIT_QUANTA; + DEBUGASSERT(brp >= 1 && brp <= CAN_BTR_BRP_MAX); + } + + caninfo("TS1: %" PRIu32 " TS2: %" PRIu32 " BRP: %" PRIu32 "\n", + ts1, ts2, brp); + + /* Configure bit timing. This also does the following, less obvious + * things. Unless loopback mode is enabled, it: + * + * - Disables silent mode. + * - Disables loopback mode. + * + * NOTE that for the time being, SJW is set to 1 just because I don't + * know any better. + */ + + tmp = ((brp - 1) << CAN_BTR_BRP_SHIFT) | ((ts1 - 1) << CAN_BTR_TS1_SHIFT) | + ((ts2 - 1) << CAN_BTR_TS2_SHIFT) | ((1 - 1) << CAN_BTR_SJW_SHIFT); +#ifdef CONFIG_CAN_LOOPBACK + /* tmp |= (CAN_BTR_LBKM | CAN_BTR_SILM); */ + + tmp |= CAN_BTR_LBKM; +#endif + + stm32can_putreg(priv, STM32_CAN_BTR_OFFSET, tmp); + return OK; +} + +/**************************************************************************** + * Name: stm32can_enterinitmode + * + * Description: + * Put the CAN cell in Initialization mode. This only disconnects the CAN + * peripheral, no registers are changed. The initialization mode is + * required to change the baud rate. + * + * Input Parameters: + * priv - A pointer to the private data structure for this CAN block + * + * Returned Value: + * Zero on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int stm32can_enterinitmode(struct stm32_can_s *priv) +{ + uint32_t regval; + volatile uint32_t timeout; + + caninfo("CAN%" PRIu8 "\n", priv->port); + + /* Enter initialization mode */ + + regval = stm32can_getreg(priv, STM32_CAN_MCR_OFFSET); + regval |= CAN_MCR_INRQ; + stm32can_putreg(priv, STM32_CAN_MCR_OFFSET, regval); + + /* Wait until initialization mode is acknowledged */ + + for (timeout = INAK_TIMEOUT; timeout > 0; timeout--) + { + regval = stm32can_getreg(priv, STM32_CAN_MSR_OFFSET); + if ((regval & CAN_MSR_INAK) != 0) + { + /* We are in initialization mode */ + + break; + } + } + + /* Check for a timeout */ + + if (timeout < 1) + { + canerr("ERROR: Timed out waiting to enter initialization mode\n"); + return -ETIMEDOUT; + } + + return OK; +} + +/**************************************************************************** + * Name: stm32can_exitinitmode + * + * Description: + * Put the CAN cell out of the Initialization mode (to Normal mode) + * + * Input Parameters: + * priv - A pointer to the private data structure for this CAN block + * + * Returned Value: + * Zero on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int stm32can_exitinitmode(struct stm32_can_s *priv) +{ + uint32_t regval; + volatile uint32_t timeout; + + /* Exit Initialization mode, enter Normal mode */ + + regval = stm32can_getreg(priv, STM32_CAN_MCR_OFFSET); + regval &= ~CAN_MCR_INRQ; + stm32can_putreg(priv, STM32_CAN_MCR_OFFSET, regval); + + /* Wait until the initialization mode exit is acknowledged */ + + for (timeout = INAK_TIMEOUT; timeout > 0; timeout--) + { + regval = stm32can_getreg(priv, STM32_CAN_MSR_OFFSET); + if ((regval & CAN_MSR_INAK) == 0) + { + /* We are out of initialization mode */ + + break; + } + } + + /* Check for a timeout */ + + if (timeout < 1) + { + canerr("ERROR: Timed out waiting to exit initialization mode: %08" + PRIx32 "\n", regval); + return -ETIMEDOUT; + } + + return OK; +} + +/**************************************************************************** + * Name: stm32can_cellinit + * + * Description: + * CAN cell initialization + * + * Input Parameters: + * priv - A pointer to the private data structure for this CAN block + * + * Returned Value: + * Zero on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int stm32can_cellinit(struct stm32_can_s *priv) +{ + uint32_t regval; + int ret; + + caninfo("CAN%" PRIu8 "\n", priv->port); + + /* Exit from sleep mode */ + + regval = stm32can_getreg(priv, STM32_CAN_MCR_OFFSET); + regval &= ~CAN_MCR_SLEEP; + stm32can_putreg(priv, STM32_CAN_MCR_OFFSET, regval); + + ret = stm32can_enterinitmode(priv); + if (ret != 0) + { + return ret; + } + + /* Disable the following modes: + * + * - Time triggered communication mode + * - Automatic bus-off management + * - Automatic wake-up mode + * - No automatic retransmission + * - Receive FIFO locked mode + * + * Enable: + * + * - Transmit FIFO priority + */ + + regval = stm32can_getreg(priv, STM32_CAN_MCR_OFFSET); + regval &= ~(CAN_MCR_RFLM | CAN_MCR_NART | CAN_MCR_AWUM | + CAN_MCR_ABOM | CAN_MCR_TTCM); + regval |= CAN_MCR_TXFP; + stm32can_putreg(priv, STM32_CAN_MCR_OFFSET, regval); + + /* Configure bit timing. */ + + ret = stm32can_bittiming(priv); + if (ret < 0) + { + canerr("ERROR: Failed to set bit timing: %d\n", ret); + return ret; + } + + return stm32can_exitinitmode(priv); +} + +/**************************************************************************** + * Name: stm32can_filterinit + * + * Description: + * CAN filter initialization. CAN filters are not currently used by this + * driver. The CAN filters can be configured in a different way: + * + * 1. As a match of specific IDs in a list (IdList mode), or as + * 2. And ID and a mask (IdMask mode). + * + * Filters can also be configured as: + * + * 3. 16- or 32-bit. The advantage of 16-bit filters is that you get + * more filters; The advantage of 32-bit filters is that you get + * finer control of the filtering. + * + * One filter is set up for each CAN. The filter resources are shared + * between the two CAN modules: CAN1 uses only filter 0 (but reserves + * 0 through CAN_NFILTERS/2-1); CAN2 uses only filter CAN_NFILTERS/2 + * (but reserves CAN_NFILTERS/2 through CAN_NFILTERS-1). + * + * 32-bit IdMask mode is configured. However, both the ID and the MASK + * are set to zero thus suppressing all filtering because anything masked + * with zero matches zero. + * + * Input Parameters: + * priv - A pointer to the private data structure for this CAN block + * + * Returned Value: + * Zero on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int stm32can_filterinit(struct stm32_can_s *priv) +{ + uint32_t regval; + uint32_t bitmask; + + caninfo("CAN%" PRIu8 " filter: %" PRIu8 "\n", priv->port, priv->filter); + + /* Get the bitmask associated with the filter used by this CAN block */ + + bitmask = (uint32_t)1 << priv->filter; + + /* Enter filter initialization mode */ + + regval = stm32can_getfreg(priv, STM32_CAN_FMR_OFFSET); + regval |= CAN_FMR_FINIT; + stm32can_putfreg(priv, STM32_CAN_FMR_OFFSET, regval); + + /* Assign half the filters to CAN1, half to CAN2 */ + +#if defined(CONFIG_STM32_CONNECTIVITYLINE) || \ + defined(CONFIG_STM32_STM32F20XX) || \ + defined(CONFIG_STM32_STM32F4XXX) + regval = stm32can_getfreg(priv, STM32_CAN_FMR_OFFSET); + regval &= CAN_FMR_CAN2SB_MASK; + regval |= (CAN_NFILTERS / 2) << CAN_FMR_CAN2SB_SHIFT; + stm32can_putfreg(priv, STM32_CAN_FMR_OFFSET, regval); +#endif + + /* Disable the filter */ + + regval = stm32can_getfreg(priv, STM32_CAN_FA1R_OFFSET); + regval &= ~bitmask; + stm32can_putfreg(priv, STM32_CAN_FA1R_OFFSET, regval); + + /* Select the 32-bit scale for the filter */ + + regval = stm32can_getfreg(priv, STM32_CAN_FS1R_OFFSET); + regval |= bitmask; + stm32can_putfreg(priv, STM32_CAN_FS1R_OFFSET, regval); + + /* There are 14 or 28 filter banks (depending) on the device. + * Each filter bank is composed of two 32-bit registers, CAN_FiR: + */ + + stm32can_putfreg(priv, STM32_CAN_FIR_OFFSET(priv->filter, 1), 0); + stm32can_putfreg(priv, STM32_CAN_FIR_OFFSET(priv->filter, 2), 0); + + /* Set Id/Mask mode for the filter */ + + regval = stm32can_getfreg(priv, STM32_CAN_FM1R_OFFSET); + regval &= ~bitmask; + stm32can_putfreg(priv, STM32_CAN_FM1R_OFFSET, regval); + + /* Assign FIFO 0 for the filter */ + + regval = stm32can_getfreg(priv, STM32_CAN_FFA1R_OFFSET); + regval &= ~bitmask; + stm32can_putfreg(priv, STM32_CAN_FFA1R_OFFSET, regval); + + /* Enable the filter */ + + regval = stm32can_getfreg(priv, STM32_CAN_FA1R_OFFSET); + regval |= bitmask; + stm32can_putfreg(priv, STM32_CAN_FA1R_OFFSET, regval); + + /* Exit filter initialization mode */ + + regval = stm32can_getfreg(priv, STM32_CAN_FMR_OFFSET); + regval &= ~CAN_FMR_FINIT; + stm32can_putfreg(priv, STM32_CAN_FMR_OFFSET, regval); + return OK; +} + +/**************************************************************************** + * Name: stm32can_addextfilter + * + * Description: + * Add a filter for extended CAN IDs + * + * Input Parameters: + * priv - A pointer to the private data structure for this CAN block + * arg - A pointer to a structure describing the filter + * + * Returned Value: + * A non-negative filter ID is returned on success. + * Otherwise -1 (ERROR) is returned with the errno + * set to indicate the nature of the error. + * + ****************************************************************************/ + +#ifdef CONFIG_CAN_EXTID +static int stm32can_addextfilter(struct stm32_can_s *priv, + struct canioc_extfilter_s *arg) +{ + return -ENOTTY; +} +#endif + +/**************************************************************************** + * Name: stm32can_delextfilter + * + * Description: + * Remove a filter for extended CAN IDs + * + * Input Parameters: + * priv - A pointer to the private data structure for this CAN block + * arg - The filter index previously returned by the + * CANIOC_ADD_EXTFILTER command + * + * Returned Value: + * Zero (OK) is returned on success. Otherwise -1 (ERROR) + * returned with the errno variable set to indicate the + * of the error. + * + ****************************************************************************/ + +#ifdef CONFIG_CAN_EXTID +static int stm32can_delextfilter(struct stm32_can_s *priv, int arg) +{ + return -ENOTTY; +} +#endif + +/**************************************************************************** + * Name: stm32can_addstdfilter + * + * Description: + * Add a filter for standard CAN IDs + * + * Input Parameters: + * priv - A pointer to the private data structure for this CAN block + * arg - A pointer to a structure describing the filter + * + * Returned Value: + * A non-negative filter ID is returned on success. + * Otherwise -1 (ERROR) is returned with the errno + * set to indicate the nature of the error. + * + ****************************************************************************/ + +static int stm32can_addstdfilter(struct stm32_can_s *priv, + struct canioc_stdfilter_s *arg) +{ + return -ENOTTY; +} + +/**************************************************************************** + * Name: stm32can_delstdfilter + * + * Description: + * Remove a filter for standard CAN IDs + * + * Input Parameters: + * priv - A pointer to the private data structure for this CAN block + * arg - The filter index previously returned by the + * CANIOC_ADD_STDFILTER command + * + * Returned Value: + * Zero (OK) is returned on success. Otherwise -1 (ERROR) + * returned with the errno variable set to indicate the + * of the error. + * + ****************************************************************************/ + +static int stm32can_delstdfilter(struct stm32_can_s *priv, int arg) +{ + return -ENOTTY; +} + +/**************************************************************************** + * Name: stm32can_txmb0empty + * + * Input Parameters: + * tsr_regval - value of CAN transmit status register + * + * Returned Value: + * Returns true if mailbox 0 is empty and can be used for sending. + * + ****************************************************************************/ + +static bool stm32can_txmb0empty(uint32_t tsr_regval) +{ + return (tsr_regval & CAN_TSR_TME0) != 0 && + (tsr_regval & CAN_TSR_RQCP0) == 0; +} + +/**************************************************************************** + * Name: stm32can_txmb1empty + * + * Input Parameters: + * tsr_regval - value of CAN transmit status register + * + * Returned Value: + * Returns true if mailbox 1 is empty and can be used for sending. + * + ****************************************************************************/ + +static bool stm32can_txmb1empty(uint32_t tsr_regval) +{ + return (tsr_regval & CAN_TSR_TME1) != 0 && + (tsr_regval & CAN_TSR_RQCP1) == 0; +} + +/**************************************************************************** + * Name: stm32can_txmb2empty + * + * Input Parameters: + * tsr_regval - value of CAN transmit status register + * + * Returned Value: + * Returns true if mailbox 2 is empty and can be used for sending. + * + ****************************************************************************/ + +static bool stm32can_txmb2empty(uint32_t tsr_regval) +{ + return (tsr_regval & CAN_TSR_TME2) != 0 && + (tsr_regval & CAN_TSR_RQCP2) == 0; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_caninitialize + * + * Description: + * Initialize the selected CAN port + * + * Input Parameters: + * Port number (for hardware that has multiple CAN interfaces) + * + * Returned Value: + * Valid CAN device structure reference on success; a NULL on failure + * + ****************************************************************************/ + +struct can_dev_s *stm32_caninitialize(int port) +{ + struct can_dev_s *dev = NULL; + + caninfo("CAN%" PRIu8 "\n", port); + + /* NOTE: Peripherical clocking for CAN1 and/or CAN2 was already provided + * by stm32_clockconfig() early in the reset sequence. + */ + +#ifdef CONFIG_STM32_CAN1 + if (port == 1) + { + /* Select the CAN1 device structure */ + + dev = &g_can1dev; + + /* Configure CAN1 pins. The ambiguous settings in the stm32*_pinmap.h + * file must have been disambiguated in the board.h file. + */ + + stm32_configgpio(GPIO_CAN1_RX); + stm32_configgpio(GPIO_CAN1_TX); + } + else +#endif +#ifdef CONFIG_STM32_CAN2 + if (port == 2) + { + /* Select the CAN2 device structure */ + + dev = &g_can2dev; + + /* Configure CAN2 pins. The ambiguous settings in the stm32*_pinmap.h + * file must have been disambiguated in the board.h file. + */ + + stm32_configgpio(GPIO_CAN2_RX); + stm32_configgpio(GPIO_CAN2_TX); + } + else +#endif + { + canerr("ERROR: Unsupported port %d\n", port); + return NULL; + } + + return dev; +} + +#endif /* CONFIG_CAN && (CONFIG_STM32_CAN1 || CONFIG_STM32_CAN2) */ diff --git a/arch/arm/src/common/stm32/stm32_can_m3m4_v1_sock.c b/arch/arm/src/common/stm32/stm32_can_m3m4_v1_sock.c new file mode 100644 index 0000000000000..60561620cfa51 --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_can_m3m4_v1_sock.c @@ -0,0 +1,2490 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_can_m3m4_v1_sock.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include +#include +#include + +#include "arm_internal.h" +#include "chip.h" +#include "stm32.h" +#include "stm32_rcc.h" +#include "stm32_can.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Delays *******************************************************************/ + +/* Time out for INAK bit */ + +#define INAK_TIMEOUT 65535 + +/* Bit timing ***************************************************************/ + +#define CAN_BIT_QUANTA (CONFIG_STM32_CAN_TSEG1 + CONFIG_STM32_CAN_TSEG2 + 1) + +#ifndef CONFIG_DEBUG_CAN_INFO +# undef CONFIG_STM32_CAN_REGDEBUG +#endif + +/* Pool configuration *******************************************************/ + +#define POOL_SIZE (1) + +/* Work queue support is required. */ + +#if !defined(CONFIG_SCHED_WORKQUEUE) +# error Work queue support is required +#endif + +/* The low priority work queue is preferred. If it is not enabled, LPWORK + * will be the same as HPWORK. + * + * NOTE: However, the network should NEVER run on the high priority work + * queue! That queue is intended only to service short back end interrupt + * processing that never suspends. Suspending the high priority work queue + * may bring the system to its knees! + */ + +#define CANWORK LPWORK + +/* CAN error interrupts */ + +#ifdef CONFIG_NET_CAN_ERRORS +# define STM32_CAN_ERRINT (CAN_IER_LECIE | CAN_IER_ERRIE | \ + CAN_IER_BOFIE | CAN_IER_EPVIE | \ + CAN_IER_EWGIE) +#endif + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +struct stm32_can_s +{ + uint8_t port; /* CAN port number (1 or 2) */ + uint8_t canrx[2]; /* CAN RX FIFO 0/1 IRQ number */ + uint8_t cantx; /* CAN TX IRQ number */ +#ifdef CONFIG_NET_CAN_ERRORS + uint8_t cansce; /* CAN SCE IRQ number */ +#endif + uint8_t filter; /* Filter number */ + uint32_t base; /* Base address of the CAN control registers */ + uint32_t fbase; /* Base address of the CAN filter registers */ + uint32_t baud; /* Configured baud */ + + bool bifup; /* true:ifup false:ifdown */ + struct net_driver_s dev; /* Interface understood by the network */ + + struct work_s irqwork; /* For deferring interrupt work to the wq */ + struct work_s pollwork; /* For deferring poll work to the work wq */ + + /* A pointers to the list of TX/RX descriptors */ + + struct can_frame *txdesc; + struct can_frame *rxdesc; + + /* TX/RX pool */ + + uint8_t tx_pool[sizeof(struct can_frame)*POOL_SIZE]; + uint8_t rx_pool[sizeof(struct can_frame)*POOL_SIZE]; +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/* CAN Register access */ + +static uint32_t stm32can_getreg(struct stm32_can_s *priv, + int offset); +static uint32_t stm32can_getfreg(struct stm32_can_s *priv, + int offset); +static void stm32can_putreg(struct stm32_can_s *priv, int offset, + uint32_t value); +static void stm32can_putfreg(struct stm32_can_s *priv, int offset, + uint32_t value); +#ifdef CONFIG_STM32_CAN_REGDEBUG +static void stm32can_dumpctrlregs(struct stm32_can_s *priv, + const char *msg); +static void stm32can_dumpmbregs(struct stm32_can_s *priv, + const char *msg); +static void stm32can_dumpfiltregs(struct stm32_can_s *priv, + const char *msg); +#else +# define stm32can_dumpctrlregs(priv,msg) +# define stm32can_dumpmbregs(priv,msg) +# define stm32can_dumpfiltregs(priv,msg) +#endif + +/* CAN interrupt enable functions */ + +static void stm32can_rx0int(struct stm32_can_s *priv, bool enable); +static void stm32can_rx1int(struct stm32_can_s *priv, bool enable); +static void stm32can_txint(struct stm32_can_s *priv, bool enable); +#ifdef CONFIG_NET_CAN_ERRORS +static void stm32can_errint(struct stm32_can_s *priv, bool enable); +#endif + +/* Common TX logic */ + +static int stm32can_transmit(struct stm32_can_s *priv); +static bool stm32can_txready(struct stm32_can_s *priv); +static int stm32can_txpoll(struct net_driver_s *dev); + +/* CAN RX interrupt handling */ + +static int stm32can_rxinterrupt_work(struct stm32_can_s *priv, + int rxmb); + +static void stm32can_rx0interrupt_work(void *arg); +static void stm32can_rx1interrupt_work(void *arg); +static int stm32can_rxinterrupt(struct stm32_can_s *priv, int rxmb); + +static int stm32can_rx0interrupt(int irq, void *context, void *arg); +static int stm32can_rx1interrupt(int irq, void *context, void *arg); + +/* CAN TX interrupt handling */ + +static int stm32can_txinterrupt(int irq, void *context, void *arg); +static void stm32can_txdone_work(void *arg); +static void stm32can_txdone(struct stm32_can_s *priv); + +#ifdef CONFIG_NET_CAN_ERRORS +/* CAN errors interrupt handling */ + +static void stm32can_sceinterrupt_work(void *arg); +static int stm32can_sceinterrupt(int irq, void *context, void *arg); +#endif + +/* Initialization */ + +static int stm32can_setup(struct stm32_can_s *priv); +static void stm32can_shutdown(struct stm32_can_s *priv); +static void stm32can_reset(struct stm32_can_s *priv); +static int stm32can_enterinitmode(struct stm32_can_s *priv); +static int stm32can_exitinitmode(struct stm32_can_s *priv); +static int stm32can_bittiming(struct stm32_can_s *priv); +static int stm32can_cellinit(struct stm32_can_s *priv); +static int stm32can_filterinit(struct stm32_can_s *priv); + +/* TX mailbox status */ + +static bool stm32can_txmb0empty(uint32_t tsr_regval); +static bool stm32can_txmb1empty(uint32_t tsr_regval); +static bool stm32can_txmb2empty(uint32_t tsr_regval); + +/* NuttX callback functions */ + +static int stm32can_ifup(struct net_driver_s *dev); +static int stm32can_ifdown(struct net_driver_s *dev); + +static void stm32can_txavail_work(void *arg); +static int stm32can_txavail(struct net_driver_s *dev); + +#ifdef CONFIG_NETDEV_IOCTL +static int stm32can_netdev_ioctl(struct net_driver_s *dev, int cmd, + unsigned long arg); +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#ifdef CONFIG_STM32_CAN1 + +static struct stm32_can_s g_can1priv = +{ + .port = 1, + .canrx = + { + STM32_IRQ_CAN1RX0, + STM32_IRQ_CAN1RX1, + }, + .cantx = STM32_IRQ_CAN1TX, +#ifdef CONFIG_NET_CAN_ERRORS + .cansce = STM32_IRQ_CAN1SCE, +#endif + .filter = 0, + .base = STM32_CAN1_BASE, + .fbase = STM32_CAN1_BASE, + .baud = CONFIG_STM32_CAN1_BAUD, +}; + +#endif + +#ifdef CONFIG_STM32_CAN2 + +static struct stm32_can_s g_can2priv = +{ + .port = 2, + .canrx = + { + STM32_IRQ_CAN2RX0, + STM32_IRQ_CAN2RX1, + }, + .cantx = STM32_IRQ_CAN2TX, +#ifdef CONFIG_NET_CAN_ERRORS + .cansce = STM32_IRQ_CAN2SCE, +#endif + .filter = CAN_NFILTERS / 2, + .base = STM32_CAN2_BASE, + .fbase = STM32_CAN1_BASE, + .baud = CONFIG_STM32_CAN2_BAUD, +}; + +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32can_getreg + * Name: stm32can_getfreg + * + * Description: + * Read the value of a CAN register or filter block register. + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_CAN_REGDEBUG +static uint32_t stm32can_vgetreg(uint32_t addr) +{ + static uint32_t prevaddr = 0; + static uint32_t preval = 0; + static uint32_t count = 0; + + /* Read the value from the register */ + + uint32_t val = getreg32(addr); + + /* Is this the same value that we read from the same register last time? + * Are we polling the register? If so, suppress some of the output. + */ + + if (addr == prevaddr && val == preval) + { + if (count == 0xffffffff || ++count > 3) + { + if (count == 4) + { + ninfo("...\n"); + } + + return val; + } + } + + /* No this is a new address or value */ + + else + { + /* Did we print "..." for the previous value? */ + + if (count > 3) + { + /* Yes.. then show how many times the value repeated */ + + ninfo("[repeats %" PRIu32 " more times]\n", count - 3); + } + + /* Save the new address, value, and count */ + + prevaddr = addr; + preval = val; + count = 1; + } + + /* Show the register value read */ + + ninfo("%08" PRIx32 "->%08" PRIx32 "\n", addr, val); + return val; +} + +static uint32_t stm32can_getreg(struct stm32_can_s *priv, int offset) +{ + return stm32can_vgetreg(priv->base + offset); +} + +static uint32_t stm32can_getfreg(struct stm32_can_s *priv, int offset) +{ + return stm32can_vgetreg(priv->fbase + offset); +} + +#else +static uint32_t stm32can_getreg(struct stm32_can_s *priv, int offset) +{ + return getreg32(priv->base + offset); +} + +static uint32_t stm32can_getfreg(struct stm32_can_s *priv, int offset) +{ + return getreg32(priv->fbase + offset); +} + +#endif + +/**************************************************************************** + * Name: stm32can_putreg + * Name: stm32can_putfreg + * + * Description: + * Set the value of a CAN register or filter block register. + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_CAN_REGDEBUG +static void stm32can_vputreg(uint32_t addr, uint32_t value) +{ + /* Show the register value being written */ + + ninfo("%08" PRIx32 "->%08" PRIx32 "\n", addr, val); + + /* Write the value */ + + putreg32(value, addr); +} + +static void stm32can_putreg(struct stm32_can_s *priv, int offset, + uint32_t value) +{ + stm32can_vputreg(priv->base + offset, value); +} + +static void stm32can_putfreg(struct stm32_can_s *priv, int offset, + uint32_t value) +{ + stm32can_vputreg(priv->fbase + offset, value); +} + +#else +static void stm32can_putreg(struct stm32_can_s *priv, int offset, + uint32_t value) +{ + putreg32(value, priv->base + offset); +} + +static void stm32can_putfreg(struct stm32_can_s *priv, int offset, + uint32_t value) +{ + putreg32(value, priv->fbase + offset); +} +#endif + +/**************************************************************************** + * Name: stm32can_dumpctrlregs + * + * Description: + * Dump the contents of all CAN control registers + * + * Input Parameters: + * priv - reference to the private CAN driver state structure + * msg - message + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_CAN_REGDEBUG +static void stm32can_dumpctrlregs(struct stm32_can_s *priv, + const char *msg) +{ + if (msg) + { + ninfo("Control Registers: %s\n", msg); + } + else + { + ninfo("Control Registers:\n"); + } + + /* CAN control and status registers */ + + ninfo(" MCR: %08" PRIx32 " MSR: %08" PRIx32 " TSR: %08" PRIx32 "\n", + getreg32(priv->base + STM32_CAN_MCR_OFFSET), + getreg32(priv->base + STM32_CAN_MSR_OFFSET), + getreg32(priv->base + STM32_CAN_TSR_OFFSET)); + + ninfo(" RF0R: %08" PRIx32 " RF1R: %08" PRIx32 "\n", + getreg32(priv->base + STM32_CAN_RF0R_OFFSET), + getreg32(priv->base + STM32_CAN_RF1R_OFFSET)); + + ninfo(" IER: %08" PRIx32 " ESR: %08" PRIx32 " BTR: %08" PRIx32 "\n", + getreg32(priv->base + STM32_CAN_IER_OFFSET), + getreg32(priv->base + STM32_CAN_ESR_OFFSET), + getreg32(priv->base + STM32_CAN_BTR_OFFSET)); +} +#endif + +/**************************************************************************** + * Name: stm32can_dumpmbregs + * + * Description: + * Dump the contents of all CAN mailbox registers + * + * Input Parameters: + * priv - reference to the private CAN driver state structure + * msg - message + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_CAN_REGDEBUG +static void stm32can_dumpmbregs(struct stm32_can_s *priv, + const char *msg) +{ + if (msg) + { + ninfo("Mailbox Registers: %s\n", msg); + } + else + { + ninfo("Mailbox Registers:\n"); + } + + /* CAN mailbox registers (3 TX and 2 RX) */ + + ninfo(" TI0R: %08" PRIx32 " TDT0R: %08" PRIx32 " TDL0R: %08" + PRIx32 " TDH0R: %08" PRIx32 "\n", + getreg32(priv->base + STM32_CAN_TI0R_OFFSET), + getreg32(priv->base + STM32_CAN_TDT0R_OFFSET), + getreg32(priv->base + STM32_CAN_TDL0R_OFFSET), + getreg32(priv->base + STM32_CAN_TDH0R_OFFSET)); + + ninfo(" TI1R: %08" PRIx32 " TDT1R: %08" PRIx32 " TDL1R: %08" + PRIx32 " TDH1R: %08" PRIx32 "\n", + getreg32(priv->base + STM32_CAN_TI1R_OFFSET), + getreg32(priv->base + STM32_CAN_TDT1R_OFFSET), + getreg32(priv->base + STM32_CAN_TDL1R_OFFSET), + getreg32(priv->base + STM32_CAN_TDH1R_OFFSET)); + + ninfo(" TI2R: %08" PRIx32 " TDT2R: %08" PRIx32 " TDL2R: %08" + PRIx32 " TDH2R: %08" PRIx32 "\n", + getreg32(priv->base + STM32_CAN_TI2R_OFFSET), + getreg32(priv->base + STM32_CAN_TDT2R_OFFSET), + getreg32(priv->base + STM32_CAN_TDL2R_OFFSET), + getreg32(priv->base + STM32_CAN_TDH2R_OFFSET)); + + ninfo(" RI0R: %08" PRIx32 " RDT0R: %08" PRIx32 " RDL0R: %08" + PRIx32 " RDH0R: %08" PRIx32 "\n", + getreg32(priv->base + STM32_CAN_RI0R_OFFSET), + getreg32(priv->base + STM32_CAN_RDT0R_OFFSET), + getreg32(priv->base + STM32_CAN_RDL0R_OFFSET), + getreg32(priv->base + STM32_CAN_RDH0R_OFFSET)); + + ninfo(" RI1R: %08" PRIx32 " RDT1R: %08" PRIx32 " RDL1R: %08" + PRIx32 " RDH1R: %08" PRIx32 "\n", + getreg32(priv->base + STM32_CAN_RI1R_OFFSET), + getreg32(priv->base + STM32_CAN_RDT1R_OFFSET), + getreg32(priv->base + STM32_CAN_RDL1R_OFFSET), + getreg32(priv->base + STM32_CAN_RDH1R_OFFSET)); +} +#endif + +/**************************************************************************** + * Name: stm32can_dumpfiltregs + * + * Description: + * Dump the contents of all CAN filter registers + * + * Input Parameters: + * priv - reference to the private CAN driver state structure + * msg - message + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_CAN_REGDEBUG +static void stm32can_dumpfiltregs(struct stm32_can_s *priv, + const char *msg) +{ + int i; + + if (msg) + { + ninfo("Filter Registers: %s\n", msg); + } + else + { + ninfo("Filter Registers:\n"); + } + + ninfo(" FMR: %08" PRIx32 " FM1R: %08" PRIx32 " FS1R: %08" + PRIx32 " FFA1R: %08" PRIx32 " FA1R: %08" PRIx32 "\n", + getreg32(priv->base + STM32_CAN_FMR_OFFSET), + getreg32(priv->base + STM32_CAN_FM1R_OFFSET), + getreg32(priv->base + STM32_CAN_FS1R_OFFSET), + getreg32(priv->base + STM32_CAN_FFA1R_OFFSET), + getreg32(priv->base + STM32_CAN_FA1R_OFFSET)); + + for (i = 0; i < CAN_NFILTERS; i++) + { + ninfo(" F%dR1: %08" PRIx32 " F%dR2: %08" PRIx32 "\n", + i, getreg32(priv->base + STM32_CAN_FIR_OFFSET(i, 1)), + i, getreg32(priv->base + STM32_CAN_FIR_OFFSET(i, 2))); + } +} +#endif + +/**************************************************************************** + * Name: stm32can_rx0int + * + * Description: + * Call to enable or disable RX0 interrupts. + * + * Input Parameters: + * priv - reference to the private CAN driver state structure + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void stm32can_rx0int(struct stm32_can_s *priv, bool enable) +{ + uint32_t regval = 0; + + ninfo("CAN%" PRIu8 "RX0 enable: %d\n", priv->port, enable); + + /* Enable/disable the FIFO 0 message pending interrupt */ + + regval = stm32can_getreg(priv, STM32_CAN_IER_OFFSET); + if (enable) + { + regval |= CAN_IER_FMPIE0; + } + else + { + regval &= ~CAN_IER_FMPIE0; + } + + stm32can_putreg(priv, STM32_CAN_IER_OFFSET, regval); +} + +/**************************************************************************** + * Name: stm32can_rx1int + * + * Description: + * Call to enable or disable RX1 interrupts. + * + * Input Parameters: + * priv - reference to the private CAN driver state structure + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void stm32can_rx1int(struct stm32_can_s *priv, bool enable) +{ + uint32_t regval = 0; + + ninfo("CAN%" PRIu8 "RX1 enable: %d\n", priv->port, enable); + + /* Enable/disable the FIFO 1 message pending interrupt */ + + regval = stm32can_getreg(priv, STM32_CAN_IER_OFFSET); + if (enable) + { + regval |= CAN_IER_FMPIE1; + } + else + { + regval &= ~CAN_IER_FMPIE1; + } + + stm32can_putreg(priv, STM32_CAN_IER_OFFSET, regval); +} + +/**************************************************************************** + * Name: stm32can_txint + * + * Description: + * Call to enable or disable TX interrupts. + * + * Input Parameters: + * priv - reference to the private CAN driver state structure + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void stm32can_txint(struct stm32_can_s *priv, bool enable) +{ + uint32_t regval = 0; + + ninfo("CAN%" PRIu8 " txint enable: %d\n", priv->port, enable); + + /* Enable/disable the transmit mailbox interrupt */ + + regval = stm32can_getreg(priv, STM32_CAN_IER_OFFSET); + if (enable) + { + regval |= CAN_IER_TMEIE; + } + else + { + regval &= ~CAN_IER_TMEIE; + } + + stm32can_putreg(priv, STM32_CAN_IER_OFFSET, regval); +} + +#ifdef CONFIG_NET_CAN_ERRORS +/**************************************************************************** + * Name: stm32can_txint + * + * Description: + * Call to enable or disable CAN SCE interrupts. + * + * Input Parameters: + * priv - reference to the private CAN driver state structure + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void stm32can_errint(struct stm32_can_s *priv, bool enable) +{ + uint32_t regval = 0; + + /* Enable/disable the transmit mailbox interrupt */ + + regval = stm32can_getreg(priv, STM32_CAN_IER_OFFSET); + if (enable) + { + regval |= STM32_CAN_ERRINT; + } + else + { + regval &= ~STM32_CAN_ERRINT; + } + + stm32can_putreg(priv, STM32_CAN_IER_OFFSET, regval); +} +#endif + +/**************************************************************************** + * Function: stm32can_ifup + * + * Description: + * NuttX Callback: Bring up the Ethernet interface when an IP address is + * provided + * + * Input Parameters: + * dev - Reference to the NuttX driver state structure + * + * Returned Value: + * None + * + * Assumptions: + * + ****************************************************************************/ + +static int stm32can_ifup(struct net_driver_s *dev) +{ + struct stm32_can_s *priv = (struct stm32_can_s *)dev->d_private; + + /* Setup CAN */ + + stm32can_setup(priv); + + /* Enable interrupts */ + + stm32can_rx0int(priv, true); + stm32can_rx1int(priv, true); + stm32can_txint(priv, true); +#ifdef CONFIG_NET_CAN_ERRORS + stm32can_errint(priv, true); +#endif + + /* Enable the interrupts at the NVIC */ + + up_enable_irq(priv->canrx[0]); + up_enable_irq(priv->canrx[1]); + up_enable_irq(priv->cantx); +#ifdef CONFIG_NET_CAN_ERRORS + up_enable_irq(priv->cansce); +#endif + + priv->bifup = true; + + priv->txdesc = (struct can_frame *)priv->tx_pool; + priv->rxdesc = (struct can_frame *)priv->rx_pool; + + priv->dev.d_buf = (uint8_t *)priv->txdesc; + + netdev_carrier_on(dev); + + return OK; +} + +/**************************************************************************** + * Function: stm32can_ifdown + * + * Description: + * NuttX Callback: Stop the interface. + * + * Input Parameters: + * dev - Reference to the NuttX driver state structure + * + * Returned Value: + * None + * + * Assumptions: + * + ****************************************************************************/ + +static int stm32can_ifdown(struct net_driver_s *dev) +{ + struct stm32_can_s *priv = (struct stm32_can_s *)dev->d_private; + + /* Disable CAN interrupts */ + + stm32can_shutdown(priv); + + /* Reset CAN */ + + stm32can_reset(priv); + + netdev_carrier_off(dev); + + return OK; +} + +/**************************************************************************** + * Name: stm32can_txready + * + * Description: + * Return true if the CAN hardware can accept another TX message. + * + ****************************************************************************/ + +static bool stm32can_txready(struct stm32_can_s *priv) +{ + uint32_t regval; + + /* Return true if any mailbox is available */ + + regval = stm32can_getreg(priv, STM32_CAN_TSR_OFFSET); + ninfo("CAN%" PRIu8 " TSR: %08" PRIx32 "\n", priv->port, regval); + + return (stm32can_txmb0empty(regval) || stm32can_txmb1empty(regval) || + stm32can_txmb2empty(regval)); +} + +/**************************************************************************** + * Name: stm32can_transmit + * + * Description: + * Start hardware transmission. Called either from the txdone interrupt + * handling or from watchdog based polling. + * + * Input Parameters: + * priv - reference to the private CAN driver state structure + * + * Returned Value: + * OK on success; a negated errno on failure + * + * Assumptions: + * May or may not be called from an interrupt handler. In either case, + * global interrupts are disabled, either explicitly or indirectly through + * interrupt handling logic. + * + ****************************************************************************/ + +static int stm32can_transmit(struct stm32_can_s *priv) +{ + struct can_frame *frame = (struct can_frame *)priv->dev.d_buf; + uint8_t *ptr; + uint32_t regval; + uint32_t tmp; + int dlc; + int txmb; + + ninfo("CAN%" PRIu8 " ID: %" PRIu32 " DLC: %" PRIu8 "\n", + priv->port, (uint32_t)frame->can_id, frame->can_dlc); + + /* Select one empty transmit mailbox */ + + regval = stm32can_getreg(priv, STM32_CAN_TSR_OFFSET); + if (stm32can_txmb0empty(regval)) + { + txmb = 0; + } + else if (stm32can_txmb1empty(regval)) + { + txmb = 1; + } + else if (stm32can_txmb2empty(regval)) + { + txmb = 2; + } + else + { + canerr("ERROR: No available mailbox\n"); + return -EBUSY; + } + + /* Clear TXRQ, RTR, IDE, EXID, and STID fields */ + + regval = stm32can_getreg(priv, STM32_CAN_TIR_OFFSET(txmb)); + regval &= ~(CAN_TIR_TXRQ | CAN_TIR_RTR | CAN_TIR_IDE | + CAN_TIR_EXID_MASK | CAN_TIR_STID_MASK); + stm32can_putreg(priv, STM32_CAN_TIR_OFFSET(txmb), regval); + + /* Set up the ID, standard 11-bit or extended 29-bit. */ + +#ifdef CONFIG_NET_CAN_EXTID + regval &= ~CAN_TIR_EXID_MASK; + if (frame->can_id & CAN_EFF_FLAG) + { + DEBUGASSERT((frame->can_id ^ CAN_EFF_FLAG) < (1 << 29)); + regval |= (frame->can_id << CAN_TIR_EXID_SHIFT) | CAN_TIR_IDE; + } + else + { + DEBUGASSERT(frame->can_id < (1 << 11)); + regval |= frame->can_id << CAN_TIR_STID_SHIFT; + } + +#else + regval |= (((uint32_t) frame->can_id << CAN_TIR_STID_SHIFT) & + CAN_TIR_STID_MASK); + +#endif + +#ifdef CONFIG_CAN_USE_RTR + regval |= ((frame->can_id & CAN_RTR_FLAG) ? CAN_TIR_RTR : 0); +#endif + + stm32can_putreg(priv, STM32_CAN_TIR_OFFSET(txmb), regval); + + /* Set up the DLC */ + + dlc = frame->can_dlc; + regval = stm32can_getreg(priv, STM32_CAN_TDTR_OFFSET(txmb)); + regval &= ~(CAN_TDTR_DLC_MASK | CAN_TDTR_TGT); + regval |= (uint32_t)dlc << CAN_TDTR_DLC_SHIFT; + stm32can_putreg(priv, STM32_CAN_TDTR_OFFSET(txmb), regval); + + /* Set up the data fields */ + + ptr = frame->data; + regval = 0; + + if (dlc > 0) + { + tmp = (uint32_t)*ptr++; + regval = tmp << CAN_TDLR_DATA0_SHIFT; + + if (dlc > 1) + { + tmp = (uint32_t)*ptr++; + regval |= tmp << CAN_TDLR_DATA1_SHIFT; + + if (dlc > 2) + { + tmp = (uint32_t)*ptr++; + regval |= tmp << CAN_TDLR_DATA2_SHIFT; + + if (dlc > 3) + { + tmp = (uint32_t)*ptr++; + regval |= tmp << CAN_TDLR_DATA3_SHIFT; + } + } + } + } + + stm32can_putreg(priv, STM32_CAN_TDLR_OFFSET(txmb), regval); + + regval = 0; + if (dlc > 4) + { + tmp = (uint32_t)*ptr++; + regval = tmp << CAN_TDHR_DATA4_SHIFT; + + if (dlc > 5) + { + tmp = (uint32_t)*ptr++; + regval |= tmp << CAN_TDHR_DATA5_SHIFT; + + if (dlc > 6) + { + tmp = (uint32_t)*ptr++; + regval |= tmp << CAN_TDHR_DATA6_SHIFT; + + if (dlc > 7) + { + tmp = (uint32_t)*ptr++; + regval |= tmp << CAN_TDHR_DATA7_SHIFT; + } + } + } + } + + stm32can_putreg(priv, STM32_CAN_TDHR_OFFSET(txmb), regval); + + /* Enable the transmit mailbox empty interrupt (may already be enabled) */ + + regval = stm32can_getreg(priv, STM32_CAN_IER_OFFSET); + regval |= CAN_IER_TMEIE; + stm32can_putreg(priv, STM32_CAN_IER_OFFSET, regval); + + /* Request transmission */ + + regval = stm32can_getreg(priv, STM32_CAN_TIR_OFFSET(txmb)); + regval |= CAN_TIR_TXRQ; /* Transmit Mailbox Request */ + stm32can_putreg(priv, STM32_CAN_TIR_OFFSET(txmb), regval); + + stm32can_dumpmbregs(priv, "After send"); + return OK; +} + +/**************************************************************************** + * Function: stm32can_txpoll + * + * Description: + * The transmitter is available, check if the network has any outgoing + * packets ready to send. This is a callback from devif_poll(). + * devif_poll() may be called: + * + * 1. When the preceding TX packet send is complete, + * 2. When the preceding TX packet send timesout and the interface is reset + * 3. During normal TX polling + * + * Input Parameters: + * dev - Reference to the NuttX driver state structure + * + * Returned Value: + * OK on success; a negated errno on failure + * + * Assumptions: + * May or may not be called from an interrupt handler. In either case, + * global interrupts are disabled, either explicitly or indirectly through + * interrupt handling logic. + * + ****************************************************************************/ + +static int stm32can_txpoll(struct net_driver_s *dev) +{ + struct stm32_can_s *priv = (struct stm32_can_s *)dev->d_private; + + /* If the polling resulted in data that should be sent out on the network, + * the field d_len is set to a value > 0. + */ + + if (priv->dev.d_len > 0) + { + stm32can_txdone(priv); + + /* Send the packet */ + + stm32can_transmit(priv); + + /* Check if there is room in the device to hold another packet. If + * not, return a non-zero value to terminate the poll. + */ + + if (stm32can_txready(priv) == false) + { + return -EBUSY; + } + } + + /* If zero is returned, the polling will continue until all connections + * have been examined. + */ + + return 0; +} + +/**************************************************************************** + * Function: stm32can_txavail_work + * + * Description: + * Perform an out-of-cycle poll on the worker thread. + * + * Input Parameters: + * arg - Reference to the NuttX driver state structure (cast to void*) + * + * Returned Value: + * None + * + * Assumptions: + * Called on the higher priority worker thread. + * + ****************************************************************************/ + +static void stm32can_txavail_work(void *arg) +{ + struct stm32_can_s *priv = (struct stm32_can_s *)arg; + + /* Ignore the notification if the interface is not yet up */ + + net_lock(); + if (priv->bifup) + { + /* Check if there is room in the hardware to hold another outgoing + * packet. + */ + + if (stm32can_txready(priv)) + { + /* No, there is space for another transfer. Poll the network for + * new XMIT data. + */ + + devif_poll(&priv->dev, stm32can_txpoll); + } + } + + net_unlock(); +} + +/**************************************************************************** + * Function: stm32can_txavail + * + * Description: + * Driver callback invoked when new TX data is available. This is a + * stimulus perform an out-of-cycle poll and, thereby, reduce the TX + * latency. + * + * Input Parameters: + * dev - Reference to the NuttX driver state structure + * + * Returned Value: + * None + * + * Assumptions: + * Called in normal user mode + * + ****************************************************************************/ + +static int stm32can_txavail(struct net_driver_s *dev) +{ + struct stm32_can_s *priv = (struct stm32_can_s *)dev->d_private; + + /* Is our single work structure available? It may not be if there are + * pending interrupt actions and we will have to ignore the Tx + * availability action. + */ + + if (work_available(&priv->pollwork)) + { + /* Schedule to serialize the poll on the worker thread. */ + + stm32can_txavail_work(priv); + } + + return OK; +} + +/**************************************************************************** + * Function: stm32can_ioctl + * + * Description: + * PHY ioctl command handler + * + * Input Parameters: + * dev - Reference to the NuttX driver state structure + * cmd - ioctl command + * arg - Argument accompanying the command + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + * Assumptions: + * + ****************************************************************************/ + +#ifdef CONFIG_NETDEV_IOCTL +static int stm32can_netdev_ioctl(struct net_driver_s *dev, int cmd, + unsigned long arg) +{ + struct stm32_can_s *priv = (struct stm32_can_s *)dev->d_private; + int ret = OK; + + switch (cmd) + { + /* TODO */ + + default: + ret = -ENOTTY; + break; + } + + return ret; +} +#endif /* CONFIG_NETDEV_IOCTL */ + +/**************************************************************************** + * Name: stm32can_rxinterrupt_work + * + * Description: + * CAN RX FIFO 0/1 interrupt handler + * + * Input Parameters: + * irq - The IRQ number of the interrupt. + * context - The register state save array at the time of the interrupt. + * rxmb - The RX mailbox number. + * + * Returned Value: + * Zero on success; a negated errno on failure + * + ****************************************************************************/ + +static int stm32can_rxinterrupt_work(struct stm32_can_s *priv, int rxmb) +{ + struct can_frame *frame = (struct can_frame *)priv->rxdesc; + uint32_t regval; + int ret = OK; + + DEBUGASSERT(priv != NULL); + + if (rxmb == 0) + { + stm32can_dumpmbregs(priv, "RX0 interrupt"); + } + else + { + stm32can_dumpmbregs(priv, "RX1 interrupt"); + } + + /* Get the CAN identifier. */ + + regval = stm32can_getreg(priv, STM32_CAN_RIR_OFFSET(rxmb)); + +#ifdef CONFIG_NET_CAN_EXTID + if ((regval & CAN_RIR_IDE) != 0) + { + frame->can_id = (regval & CAN_RIR_EXID_MASK) >> CAN_RIR_EXID_SHIFT; + frame->can_id |= CAN_EFF_FLAG; + } + else + { + frame->can_id = (regval & CAN_RIR_STID_MASK) >> CAN_RIR_STID_SHIFT; + } +#else + if ((regval & CAN_RIR_IDE) != 0) + { + nerr("ERROR: Received message with extended identifier. Dropped\n"); + ret = -ENOSYS; + goto errout; + } + + frame->can_id = (regval & CAN_RIR_STID_MASK) >> CAN_RIR_STID_SHIFT; +#endif + + /* Extract the RTR bit */ + + if ((regval & CAN_RIR_RTR) != 0) + { + frame->can_id |= CAN_RTR_FLAG; + } + + /* Get the DLC */ + + regval = stm32can_getreg(priv, STM32_CAN_RDTR_OFFSET(rxmb)); + frame->can_dlc = (regval & CAN_RDTR_DLC_MASK) >> CAN_RDTR_DLC_SHIFT; + + /* Save the message data */ + + regval = stm32can_getreg(priv, STM32_CAN_RDLR_OFFSET(rxmb)); + frame->data[0] = (regval & CAN_RDLR_DATA0_MASK) >> CAN_RDLR_DATA0_SHIFT; + frame->data[1] = (regval & CAN_RDLR_DATA1_MASK) >> CAN_RDLR_DATA1_SHIFT; + frame->data[2] = (regval & CAN_RDLR_DATA2_MASK) >> CAN_RDLR_DATA2_SHIFT; + frame->data[3] = (regval & CAN_RDLR_DATA3_MASK) >> CAN_RDLR_DATA3_SHIFT; + + regval = stm32can_getreg(priv, STM32_CAN_RDHR_OFFSET(rxmb)); + frame->data[4] = (regval & CAN_RDHR_DATA4_MASK) >> CAN_RDHR_DATA4_SHIFT; + frame->data[5] = (regval & CAN_RDHR_DATA5_MASK) >> CAN_RDHR_DATA5_SHIFT; + frame->data[6] = (regval & CAN_RDHR_DATA6_MASK) >> CAN_RDHR_DATA6_SHIFT; + frame->data[7] = (regval & CAN_RDHR_DATA7_MASK) >> CAN_RDHR_DATA7_SHIFT; + + /* Copy the buffer pointer to priv->dev.. Set amount of data + * in priv->dev.d_len + */ + + priv->dev.d_len = sizeof(struct can_frame); + priv->dev.d_buf = (uint8_t *)frame; + + /* Send to socket interface */ + + NETDEV_RXPACKETS(&priv->dev); + + can_input(&priv->dev); + + /* Point the packet buffer back to the next Tx buffer that will be + * used during the next write. If the write queue is full, then + * this will point at an active buffer, which must not be written + * to. This is OK because devif_poll won't be called unless the + * queue is not full. + */ + + priv->dev.d_buf = (uint8_t *)priv->txdesc; + + /* Release the FIFO */ + +#ifndef CONFIG_NET_CAN_EXTID +errout: +#endif + regval = stm32can_getreg(priv, STM32_CAN_RFR_OFFSET(rxmb)); + regval |= CAN_RFR_RFOM; + stm32can_putreg(priv, STM32_CAN_RFR_OFFSET(rxmb), regval); + + /* Re-enable CAN RX interrupts */ + + if (rxmb == 0) + { + stm32can_rx0int(priv, true); + } + else if (rxmb == 1) + { + stm32can_rx1int(priv, true); + } + else + { + DEBUGPANIC(); + } + + return ret; +} + +/**************************************************************************** + * Name: stm32can_rx0interrupt_work + ****************************************************************************/ + +static void stm32can_rx0interrupt_work(void *arg) +{ + struct stm32_can_s *priv = (struct stm32_can_s *)arg; + stm32can_rxinterrupt_work(priv, 0); +} + +/**************************************************************************** + * Name: stm32can_rx1interrupt_work + ****************************************************************************/ + +static void stm32can_rx1interrupt_work(void *arg) +{ + struct stm32_can_s *priv = (struct stm32_can_s *)arg; + stm32can_rxinterrupt_work(priv, 1); +} + +/**************************************************************************** + * Name: stm32can_rxinterrupt + * + * Description: + * CAN RX FIFO common interrupt handler + * + ****************************************************************************/ + +static int stm32can_rxinterrupt(struct stm32_can_s *priv, int rxmb) +{ + uint32_t regval = 0; + int npending = 0; + + /* Verify that a message is pending in the FIFO */ + + regval = stm32can_getreg(priv, STM32_CAN_RFR_OFFSET(rxmb)); + npending = (regval & CAN_RFR_FMP_MASK) >> CAN_RFR_FMP_SHIFT; + if (npending < 1) + { + nwarn("WARNING: No messages pending\n"); + return OK; + } + + /* Disable further CAN RX interrupts and schedule to perform the + * interrupt processing on the worker thread + */ + + if (rxmb == 0) + { + stm32can_rx0int(priv, false); + work_queue(CANWORK, &priv->irqwork, + stm32can_rx0interrupt_work, priv, 0); + } + else if (rxmb == 1) + { + stm32can_rx1int(priv, false); + work_queue(CANWORK, &priv->irqwork, + stm32can_rx1interrupt_work, priv, 0); + } + else + { + DEBUGPANIC(); + } + + return OK; +} + +/**************************************************************************** + * Name: stm32can_rx0interrupt + * + * Description: + * CAN RX FIFO 0 interrupt handler + * + * Input Parameters: + * irq - The IRQ number of the interrupt. + * context - The register state save array at the time of the interrupt. + * + * Returned Value: + * Zero on success; a negated errno on failure + * + ****************************************************************************/ + +static int stm32can_rx0interrupt(int irq, void *context, void *arg) +{ + struct stm32_can_s *priv = (struct stm32_can_s *)arg; + return stm32can_rxinterrupt(priv, 0); +} + +/**************************************************************************** + * Name: stm32can_rx1interrupt + * + * Description: + * CAN RX FIFO 1 interrupt handler + * + * Input Parameters: + * irq - The IRQ number of the interrupt. + * context - The register state save array at the time of the interrupt. + * + * Returned Value: + * Zero on success; a negated errno on failure + * + ****************************************************************************/ + +static int stm32can_rx1interrupt(int irq, void *context, void *arg) +{ + struct stm32_can_s *priv = (struct stm32_can_s *)arg; + return stm32can_rxinterrupt(priv, 1); +} + +/**************************************************************************** + * Name: stm32can_txinterrupt + * + * Description: + * CAN TX mailbox complete interrupt handler + * + * Input Parameters: + * irq - The IRQ number of the interrupt. + * context - The register state save array at the time of the interrupt. + * + * Returned Value: + * Zero on success; a negated errno on failure + * + ****************************************************************************/ + +static int stm32can_txinterrupt(int irq, void *context, void *arg) +{ + struct stm32_can_s *priv = (struct stm32_can_s *)arg; + uint32_t regval; + + DEBUGASSERT(priv != NULL); + + /* Get the transmit status */ + + regval = stm32can_getreg(priv, STM32_CAN_TSR_OFFSET); + + /* Check for RQCP0: Request completed mailbox 0 */ + + if ((regval & CAN_TSR_RQCP0) != 0) + { + /* Writing '1' to RCP0 clears RCP0 and all the status bits (TXOK0, + * ALST0 and TERR0) for Mailbox 0. + */ + + stm32can_putreg(priv, STM32_CAN_TSR_OFFSET, CAN_TSR_RQCP0); + + /* Tell the upper half that the transfer is finished. */ + + /* Disable further TX CAN interrupts. here can be no race + * condition here. + */ + + stm32can_txint(priv, false); + work_queue(CANWORK, &priv->irqwork, stm32can_txdone_work, priv, 0); + } + + /* Check for RQCP1: Request completed mailbox 1 */ + + if ((regval & CAN_TSR_RQCP1) != 0) + { + /* Writing '1' to RCP1 clears RCP1 and all the status bits (TXOK1, + * ALST1 and TERR1) for Mailbox 1. + */ + + stm32can_putreg(priv, STM32_CAN_TSR_OFFSET, CAN_TSR_RQCP1); + + /* Tell the upper half that the transfer is finished. */ + + /* Disable further TX CAN interrupts. here can be no race + * condition here. + */ + + stm32can_txint(priv, false); + work_queue(CANWORK, &priv->irqwork, stm32can_txdone_work, priv, 0); + } + + /* Check for RQCP2: Request completed mailbox 2 */ + + if ((regval & CAN_TSR_RQCP2) != 0) + { + /* Writing '1' to RCP2 clears RCP2 and all the status bits (TXOK2, + * ALST2 and TERR2) for Mailbox 2. + */ + + stm32can_putreg(priv, STM32_CAN_TSR_OFFSET, CAN_TSR_RQCP2); + + /* Disable further TX CAN interrupts. here can be no race + * condition here. + */ + + stm32can_txint(priv, false); + work_queue(CANWORK, &priv->irqwork, stm32can_txdone_work, priv, 0); + } + + return OK; +} + +/**************************************************************************** + * Name: stm32can_txdone_work + ****************************************************************************/ + +static void stm32can_txdone_work(void *arg) +{ + struct stm32_can_s *priv = (struct stm32_can_s *)arg; + + stm32can_txdone(priv); + + /* There should be space for a new TX in any event. Poll the network for + * new XMIT data + */ + + net_lock(); + devif_poll(&priv->dev, stm32can_txpoll); + net_unlock(); +} + +/**************************************************************************** + * Name: stm32can_txdone + ****************************************************************************/ + +static void stm32can_txdone(struct stm32_can_s *priv) +{ + stm32can_txint(priv, true); + + NETDEV_TXDONE(&priv->dev); +} + +#ifdef CONFIG_NET_CAN_ERRORS + +/**************************************************************************** + * Name: stm32can_sceinterrupt_work + * + * Description: + * CAN status change interrupt work + * + * Input Parameters: + * arg - reference to the driver state structure + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void stm32can_sceinterrupt_work(void *arg) +{ + struct stm32_can_s *priv = (struct stm32_can_s *)arg; + struct can_frame *frame = (struct can_frame *)priv->rxdesc; + uint32_t regval = 0; + uint16_t errbits = 0; + uint8_t data[CAN_ERR_DLC]; + + DEBUGASSERT(priv != NULL); + + /* Check Error Interrupt flag */ + + regval = stm32can_getreg(priv, STM32_CAN_MSR_OFFSET); + if (regval & CAN_MSR_ERRI) + { + /* Encode error bits */ + + errbits = 0; + memset(data, 0, sizeof(data)); + + /* Get Error statur register */ + + regval = stm32can_getreg(priv, STM32_CAN_ESR_OFFSET); + + if (regval & CAN_ESR_EWGF) + { + /* Error warning flag */ + + data[1] |= (CAN_ERR_CRTL_RX_WARNING | CAN_ERR_CRTL_TX_WARNING); + errbits |= CAN_ERR_CRTL; + } + + if (regval & CAN_ESR_EPVF) + { + /* Error passive flag */ + + data[1] |= (CAN_ERR_CRTL_RX_PASSIVE | CAN_ERR_CRTL_TX_PASSIVE); + errbits |= CAN_ERR_CRTL; + } + + if (regval & CAN_ESR_BOFF) + { + /* Bus-off flag */ + + errbits |= CAN_ERR_BUSOFF; + } + + /* Last error code */ + + if (regval & CAN_ESR_LEC_MASK) + { + if (regval & CAN_ESR_STUFFERROR) + { + /* Stuff Error */ + + errbits |= CAN_ERR_PROT; + data[2] |= CAN_ERR_PROT_STUFF; + } + else if (regval & CAN_ESR_FORMERROR) + { + /* Format Error */ + + errbits |= CAN_ERR_PROT; + data[2] |= CAN_ERR_PROT_FORM; + } + else if (regval & CAN_ESR_ACKERROR) + { + /* Acknowledge Error */ + + errbits |= CAN_ERR_ACK; + } + else if (regval & CAN_ESR_BRECERROR) + { + /* Bit recessive Error */ + + errbits |= CAN_ERR_PROT; + data[2] |= CAN_ERR_PROT_BIT1; + } + else if (regval & CAN_ESR_BDOMERROR) + { + /* Bit dominant Error */ + + errbits |= CAN_ERR_PROT; + data[2] |= CAN_ERR_PROT_BIT0; + } + else if (regval & CAN_ESR_CRCERRPR) + { + /* Receive CRC Error */ + + errbits |= CAN_ERR_PROT; + data[3] |= CAN_ERR_PROT_LOC_CRC_SEQ; + } + } + + /* Get transmit status register */ + + regval = stm32can_getreg(priv, STM32_CAN_TSR_OFFSET); + + if (regval & CAN_TSR_ALST0 || regval & CAN_TSR_ALST1 || + regval & CAN_TSR_ALST2) + { + /* Lost arbitration Error */ + + errbits |= CAN_ERR_LOSTARB; + } + + /* Clear TSR register */ + + stm32can_putreg(priv, STM32_CAN_TSR_OFFSET, regval); + + /* Clear ERRI flag */ + + stm32can_putreg(priv, STM32_CAN_MSR_OFFSET, CAN_MSR_ERRI); + } + + /* Report a CAN error */ + + if (errbits != 0) + { + canerr("ERROR: errbits = %08" PRIx16 "\n", errbits); + + /* Copy frame */ + + frame->can_id = errbits; + frame->can_dlc = CAN_ERR_DLC; + + memcpy(frame->data, data, CAN_ERR_DLC); + + net_lock(); + + /* Copy the buffer pointer to priv->dev.. Set amount of data + * in priv->dev.d_len + */ + + priv->dev.d_len = sizeof(struct can_frame); + priv->dev.d_buf = (uint8_t *)frame; + + /* Send to socket interface */ + + NETDEV_ERRORS(&priv->dev); + + can_input(&priv->dev); + + /* Point the packet buffer back to the next Tx buffer that will be + * used during the next write. If the write queue is full, then + * this will point at an active buffer, which must not be written + * to. This is OK because devif_poll won't be called unless the + * queue is not full. + */ + + priv->dev.d_buf = (uint8_t *)priv->txdesc; + net_unlock(); + } + + /* Re-enable CAN SCE interrupts */ + + stm32can_errint(priv, true); +} + +/**************************************************************************** + * Name: stm32can_sceinterrupt + * + * Description: + * CAN status change interrupt handler + * + * Input Parameters: + * irq - The IRQ number of the interrupt. + * context - The register state save array at the time of the interrupt. + * + * Returned Value: + * Zero on success; a negated errno on failure + * + ****************************************************************************/ + +static int stm32can_sceinterrupt(int irq, void *context, void *arg) +{ + struct stm32_can_s *priv = (struct stm32_can_s *)arg; + + /* Disable further CAN SCE interrupts and schedule to perform the + * interrupt processing on the worker thread + */ + + stm32can_errint(priv, false); + work_queue(CANWORK, &priv->irqwork, + stm32can_sceinterrupt_work, priv, 0); + + return OK; +} +#endif + +/**************************************************************************** + * Name: stm32can_bittiming + * + * Description: + * Set the CAN bit timing register (BTR) based on the configured BAUD. + * + * "The bit timing logic monitors the serial bus-line and performs sampling + * and adjustment of the sample point by synchronizing on the start-bit edge + * and resynchronizing on the following edges. + * + * "Its operation may be explained simply by splitting nominal bit time into + * three segments as follows: + * + * 1. "Synchronization segment (SYNC_SEG): a bit change is expected to occur + * within this time segment. It has a fixed length of one time quantum + * (1 x tCAN). + * 2. "Bit segment 1 (BS1): defines the location of the sample point. It + * includes the PROP_SEG and PHASE_SEG1 of the CAN standard. Its duration + * is programmable between 1 and 16 time quanta but may be automatically + * lengthened to compensate for positive phase drifts due to differences + * in the frequency of the various nodes of the network. + * 3. "Bit segment 2 (BS2): defines the location of the transmit point. It + * represents the PHASE_SEG2 of the CAN standard. Its duration is + * programmable between 1 and 8 time quanta but may also be automatically + * shortened to compensate for negative phase drifts." + * + * Pictorially: + * + * |<----------------- NOMINAL BIT TIME ----------------->| + * |<- SYNC_SEG ->|<------ BS1 ------>|<------ BS2 ------>| + * |<---- Tq ---->|<----- Tbs1 ------>|<----- Tbs2 ------>| + * + * Where + * Tbs1 is the duration of the BS1 segment + * Tbs2 is the duration of the BS2 segment + * Tq is the "Time Quantum" + * + * Relationships: + * + * baud = 1 / bit_time + * bit_time = Tq + Tbs1 + Tbs2 + * Tbs1 = Tq * ts1 + * Tbs2 = Tq * ts2 + * Tq = brp * Tpclk1 + * baud = Fpclk1 / (brp * (1 + ts1 + ts2)) + * + * Where: + * Tpclk1 is the period of the APB1 clock (PCLK1). + * + * Input Parameters: + * priv - reference to the private CAN driver state structure + * + * Returned Value: + * Zero on success; a negated errno on failure + * + ****************************************************************************/ + +static int stm32can_bittiming(struct stm32_can_s *priv) +{ + uint32_t tmp; + uint32_t brp; + uint32_t ts1; + uint32_t ts2; + + ninfo("CAN%" PRIu8 " PCLK1: %lu baud: %" PRIu32 "\n", + priv->port, (unsigned long) STM32_PCLK1_FREQUENCY, priv->baud); + + /* Try to get CAN_BIT_QUANTA quanta in one bit_time. + * + * bit_time = Tq*(ts1 + ts2 + 1) + * nquanta = bit_time / Tq + * nquanta = (ts1 + ts2 + 1) + * + * bit_time = brp * Tpclk1 * (ts1 + ts2 + 1) + * nquanta = bit_time / brp / Tpclk1 + * = PCLK1 / baud / brp + * brp = PCLK1 / baud / nquanta; + * + * Example: + * PCLK1 = 42,000,000 baud = 1,000,000 nquanta = 14 : brp = 3 + * PCLK1 = 42,000,000 baud = 700,000 nquanta = 14 : brp = 4 + */ + + tmp = STM32_PCLK1_FREQUENCY / priv->baud; + if (tmp < CAN_BIT_QUANTA) + { + /* At the smallest brp value (1), there are already too few bit times + * (PCLCK1 / baud) to meet our goal. brp must be one and we need + * make some reasonable guesses about ts1 and ts2. + */ + + brp = 1; + + /* In this case, we have to guess a good value for ts1 and ts2 */ + + ts1 = (tmp - 1) >> 1; + ts2 = tmp - ts1 - 1; + if (ts1 == ts2 && ts1 > 1 && ts2 < CAN_BTR_TSEG2_MAX) + { + ts1--; + ts2++; + } + } + + /* Otherwise, nquanta is CAN_BIT_QUANTA, ts1 is CONFIG_STM32_CAN_TSEG1, + * ts2 is CONFIG_STM32_CAN_TSEG2 and we calculate brp to achieve + * CAN_BIT_QUANTA quanta in the bit time + */ + + else + { + ts1 = CONFIG_STM32_CAN_TSEG1; + ts2 = CONFIG_STM32_CAN_TSEG2; + brp = (tmp + (CAN_BIT_QUANTA / 2)) / CAN_BIT_QUANTA; + DEBUGASSERT(brp >= 1 && brp <= CAN_BTR_BRP_MAX); + } + + ninfo("TS1: %" PRIu32 " TS2: %" PRIu32 " BRP: %" PRIu32 "\n", + ts1, ts2, brp); + + /* Configure bit timing. This also does the following, less obvious + * things. Unless loopback mode is enabled, it: + * + * - Disables silent mode. + * - Disables loopback mode. + * + * NOTE that for the time being, SJW is set to 1 just because I don't + * know any better. + */ + + tmp = ((brp - 1) << CAN_BTR_BRP_SHIFT) | ((ts1 - 1) << CAN_BTR_TS1_SHIFT) | + ((ts2 - 1) << CAN_BTR_TS2_SHIFT) | ((1 - 1) << CAN_BTR_SJW_SHIFT); +#ifdef CONFIG_CAN_LOOPBACK + /* tmp |= (CAN_BTR_LBKM | CAN_BTR_SILM); */ + + tmp |= CAN_BTR_LBKM; +#endif + + stm32can_putreg(priv, STM32_CAN_BTR_OFFSET, tmp); + return OK; +} + +/**************************************************************************** + * Name: stm32can_setup + ****************************************************************************/ + +static int stm32can_setup(struct stm32_can_s *priv) +{ + int ret; + +#ifdef CONFIG_NET_CAN_ERRORS + ninfo("CAN%" PRIu8 " RX0 irq: %" PRIu8 " RX1 irq: %" PRIu8 + " TX irq: %" PRIu8 " SCE irq: %" PRIu8 "\n", + priv->port, priv->canrx[0], priv->canrx[1], priv->cantx, + priv->cansce); +#else + ninfo("CAN%" PRIu8 " RX0 irq: %" PRIu8 " RX1 irq: %" PRIu8 + " TX irq: %" PRIu8 "\n", + priv->port, priv->canrx[0], priv->canrx[1], priv->cantx); +#endif + + /* CAN cell initialization */ + + ret = stm32can_cellinit(priv); + if (ret < 0) + { + nerr("ERROR: CAN%" PRId8 " cell initialization failed: %d\n", + priv->port, ret); + return ret; + } + + stm32can_dumpctrlregs(priv, "After cell initialization"); + stm32can_dumpmbregs(priv, NULL); + + /* CAN filter initialization */ + + ret = stm32can_filterinit(priv); + if (ret < 0) + { + nerr("ERROR: CAN%" PRIu8 " filter initialization failed: %d\n", + priv->port, ret); + return ret; + } + + stm32can_dumpfiltregs(priv, "After filter initialization"); + + /* Attach the CAN RX FIFO 0/1 interrupts and TX interrupts. + * The others are not used. + */ + + ret = irq_attach(priv->canrx[0], stm32can_rx0interrupt, priv); + if (ret < 0) + { + nerr("ERROR: Failed to attach CAN%" PRIu8 " RX0 IRQ (%" PRIu8 ")", + priv->port, priv->canrx[0]); + return ret; + } + + ret = irq_attach(priv->canrx[1], stm32can_rx1interrupt, priv); + if (ret < 0) + { + nerr("ERROR: Failed to attach CAN%" PRIu8 " RX1 IRQ (%" PRIu8 ")", + priv->port, priv->canrx[1]); + return ret; + } + + ret = irq_attach(priv->cantx, stm32can_txinterrupt, priv); + if (ret < 0) + { + nerr("ERROR: Failed to attach CAN%" PRIu8 " TX IRQ (%" PRIu8 ")", + priv->port, priv->cantx); + return ret; + } + +#ifdef CONFIG_NET_CAN_ERRORS + ret = irq_attach(priv->cansce, stm32can_sceinterrupt, priv); + if (ret < 0) + { + nerr("ERROR: Failed to attach CAN%" PRIu8 " SCE IRQ (%" PRIu8 ")", + priv->port, priv->cansce); + return ret; + } +#endif + + return OK; +} + +/**************************************************************************** + * Name: stm32can_shutdown + ****************************************************************************/ + +static void stm32can_shutdown(struct stm32_can_s *priv) +{ + ninfo("CAN%" PRIu8 "\n", priv->port); + + /* Disable the RX FIFO 0/1 and TX interrupts */ + + up_disable_irq(priv->canrx[0]); + up_disable_irq(priv->canrx[1]); + up_disable_irq(priv->cantx); +#ifdef CONFIG_NET_CAN_ERRORS + up_disable_irq(priv->cansce); +#endif + + /* Detach the RX FIFO 0/1 and TX interrupts */ + + irq_detach(priv->canrx[0]); + irq_detach(priv->canrx[1]); + irq_detach(priv->cantx); +#ifdef CONFIG_NET_CAN_ERRORS + irq_detach(priv->cansce); +#endif +} + +/**************************************************************************** + * Name: stm32can_reset + * + * Description: + * Put the CAN device in the non-operational, reset state + * + * Input Parameters: + * priv - reference to the private CAN driver state structure + * + * Returned Value: + * None + * + * Assumptions: + * + ****************************************************************************/ + +static void stm32can_reset(struct stm32_can_s *priv) +{ + uint32_t regval; + uint32_t regbit = 0; + irqstate_t flags; + + ninfo("CAN%" PRIu8 "\n", priv->port); + + /* Get the bits in the AHB1RSTR register needed to reset this CAN device */ + +#ifdef CONFIG_STM32_CAN1 + if (priv->port == 1) + { + regbit = RCC_APB1RSTR_CAN1RST; + } + else +#endif +#ifdef CONFIG_STM32_CAN2 + if (priv->port == 2) + { + regbit = RCC_APB1RSTR_CAN2RST; + } + else +#endif + { + nerr("ERROR: Unsupported port %d\n", priv->port); + return; + } + + /* Disable interrupts momentarily to stop any ongoing CAN event processing + * and to prevent any concurrent access to the AHB1RSTR register. + */ + + flags = enter_critical_section(); + + /* Reset the CAN */ + + regval = getreg32(STM32_RCC_APB1RSTR); + regval |= regbit; + putreg32(regval, STM32_RCC_APB1RSTR); + + regval &= ~regbit; + putreg32(regval, STM32_RCC_APB1RSTR); + leave_critical_section(flags); +} + +/**************************************************************************** + * Name: stm32can_enterinitmode + * + * Description: + * Put the CAN cell in Initialization mode. This only disconnects the CAN + * peripheral, no registers are changed. The initialization mode is + * required to change the baud rate. + * + * Input Parameters: + * priv - reference to the private CAN driver state structure + * + * Returned Value: + * Zero on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int stm32can_enterinitmode(struct stm32_can_s *priv) +{ + uint32_t regval; + volatile uint32_t timeout; + + ninfo("CAN%" PRIu8 "\n", priv->port); + + /* Enter initialization mode */ + + regval = stm32can_getreg(priv, STM32_CAN_MCR_OFFSET); + regval |= CAN_MCR_INRQ; + stm32can_putreg(priv, STM32_CAN_MCR_OFFSET, regval); + + /* Wait until initialization mode is acknowledged */ + + for (timeout = INAK_TIMEOUT; timeout > 0; timeout--) + { + regval = stm32can_getreg(priv, STM32_CAN_MSR_OFFSET); + if ((regval & CAN_MSR_INAK) != 0) + { + /* We are in initialization mode */ + + break; + } + } + + /* Check for a timeout */ + + if (timeout < 1) + { + nerr("ERROR: Timed out waiting to enter initialization mode\n"); + return -ETIMEDOUT; + } + + return OK; +} + +/**************************************************************************** + * Name: stm32can_exitinitmode + * + * Description: + * Put the CAN cell out of the Initialization mode (to Normal mode) + * + * Input Parameters: + * priv - reference to the private CAN driver state structure + * + * Returned Value: + * Zero on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int stm32can_exitinitmode(struct stm32_can_s *priv) +{ + uint32_t regval; + volatile uint32_t timeout; + + /* Exit Initialization mode, enter Normal mode */ + + regval = stm32can_getreg(priv, STM32_CAN_MCR_OFFSET); + regval &= ~CAN_MCR_INRQ; + stm32can_putreg(priv, STM32_CAN_MCR_OFFSET, regval); + + /* Wait until the initialization mode exit is acknowledged */ + + for (timeout = INAK_TIMEOUT; timeout > 0; timeout--) + { + regval = stm32can_getreg(priv, STM32_CAN_MSR_OFFSET); + if ((regval & CAN_MSR_INAK) == 0) + { + /* We are out of initialization mode */ + + break; + } + } + + /* Check for a timeout */ + + if (timeout < 1) + { + nerr("ERROR: Timed out waiting to exit initialization mode: %08" + PRIx32 "\n", regval); + return -ETIMEDOUT; + } + + return OK; +} + +/**************************************************************************** + * Name: stm32can_cellinit + * + * Description: + * CAN cell initialization + * + * Input Parameters: + * priv - reference to the private CAN driver state structure + * + * Returned Value: + * Zero on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int stm32can_cellinit(struct stm32_can_s *priv) +{ + uint32_t regval; + int ret; + + ninfo("CAN%" PRIu8 "\n", priv->port); + + /* Exit from sleep mode */ + + regval = stm32can_getreg(priv, STM32_CAN_MCR_OFFSET); + regval &= ~CAN_MCR_SLEEP; + stm32can_putreg(priv, STM32_CAN_MCR_OFFSET, regval); + + ret = stm32can_enterinitmode(priv); + if (ret != 0) + { + return ret; + } + + /* Disable the following modes: + * + * - Time triggered communication mode + * - Automatic bus-off management + * - Automatic wake-up mode + * - No automatic retransmission + * - Receive FIFO locked mode + * + * Enable: + * + * - Transmit FIFO priority + */ + + regval = stm32can_getreg(priv, STM32_CAN_MCR_OFFSET); + regval &= ~(CAN_MCR_RFLM | CAN_MCR_NART | CAN_MCR_AWUM | + CAN_MCR_ABOM | CAN_MCR_TTCM); + regval |= CAN_MCR_TXFP; + stm32can_putreg(priv, STM32_CAN_MCR_OFFSET, regval); + + /* Configure bit timing. */ + + ret = stm32can_bittiming(priv); + if (ret < 0) + { + nerr("ERROR: Failed to set bit timing: %d\n", ret); + return ret; + } + + return stm32can_exitinitmode(priv); +} + +/**************************************************************************** + * Name: stm32can_filterinit + * + * Description: + * CAN filter initialization. CAN filters are not currently used by this + * driver. The CAN filters can be configured in a different way: + * + * 1. As a match of specific IDs in a list (IdList mode), or as + * 2. And ID and a mask (IdMask mode). + * + * Filters can also be configured as: + * + * 3. 16- or 32-bit. The advantage of 16-bit filters is that you get + * more filters; The advantage of 32-bit filters is that you get + * finer control of the filtering. + * + * One filter is set up for each CAN. The filter resources are shared + * between the two CAN modules: CAN1 uses only filter 0 (but reserves + * 0 through CAN_NFILTERS/2-1); CAN2 uses only filter CAN_NFILTERS/2 + * (but reserves CAN_NFILTERS/2 through CAN_NFILTERS-1). + * + * 32-bit IdMask mode is configured. However, both the ID and the MASK + * are set to zero thus suppressing all filtering because anything masked + * with zero matches zero. + * + * Input Parameters: + * priv - reference to the private CAN driver state structure + * + * Returned Value: + * Zero on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int stm32can_filterinit(struct stm32_can_s *priv) +{ + uint32_t regval; + uint32_t bitmask; + + ninfo("CAN%" PRIu8 " filter: %" PRIu8 "\n", priv->port, priv->filter); + + /* Get the bitmask associated with the filter used by this CAN block */ + + bitmask = (uint32_t)1 << priv->filter; + + /* Enter filter initialization mode */ + + regval = stm32can_getfreg(priv, STM32_CAN_FMR_OFFSET); + regval |= CAN_FMR_FINIT; + stm32can_putfreg(priv, STM32_CAN_FMR_OFFSET, regval); + + /* Assign half the filters to CAN1, half to CAN2 */ + +#if defined(CONFIG_STM32_CONNECTIVITYLINE) || \ + defined(CONFIG_STM32_STM32F20XX) || \ + defined(CONFIG_STM32_STM32F4XXX) + regval = stm32can_getfreg(priv, STM32_CAN_FMR_OFFSET); + regval &= CAN_FMR_CAN2SB_MASK; + regval |= (CAN_NFILTERS / 2) << CAN_FMR_CAN2SB_SHIFT; + stm32can_putfreg(priv, STM32_CAN_FMR_OFFSET, regval); +#endif + + /* Disable the filter */ + + regval = stm32can_getfreg(priv, STM32_CAN_FA1R_OFFSET); + regval &= ~bitmask; + stm32can_putfreg(priv, STM32_CAN_FA1R_OFFSET, regval); + + /* Select the 32-bit scale for the filter */ + + regval = stm32can_getfreg(priv, STM32_CAN_FS1R_OFFSET); + regval |= bitmask; + stm32can_putfreg(priv, STM32_CAN_FS1R_OFFSET, regval); + + /* There are 14 or 28 filter banks (depending) on the device. + * Each filter bank is composed of two 32-bit registers, CAN_FiR: + */ + + stm32can_putfreg(priv, STM32_CAN_FIR_OFFSET(priv->filter, 1), 0); + stm32can_putfreg(priv, STM32_CAN_FIR_OFFSET(priv->filter, 2), 0); + + /* Set Id/Mask mode for the filter */ + + regval = stm32can_getfreg(priv, STM32_CAN_FM1R_OFFSET); + regval &= ~bitmask; + stm32can_putfreg(priv, STM32_CAN_FM1R_OFFSET, regval); + + /* Assign FIFO 0 for the filter */ + + regval = stm32can_getfreg(priv, STM32_CAN_FFA1R_OFFSET); + regval &= ~bitmask; + stm32can_putfreg(priv, STM32_CAN_FFA1R_OFFSET, regval); + + /* Enable the filter */ + + regval = stm32can_getfreg(priv, STM32_CAN_FA1R_OFFSET); + regval |= bitmask; + stm32can_putfreg(priv, STM32_CAN_FA1R_OFFSET, regval); + + /* Exit filter initialization mode */ + + regval = stm32can_getfreg(priv, STM32_CAN_FMR_OFFSET); + regval &= ~CAN_FMR_FINIT; + stm32can_putfreg(priv, STM32_CAN_FMR_OFFSET, regval); + return OK; +} + +/**************************************************************************** + * Name: stm32can_txmb0empty + * + * Input Parameters: + * tsr_regval - value of CAN transmit status register + * + * Returned Value: + * Returns true if mailbox 0 is empty and can be used for sending. + * + ****************************************************************************/ + +static bool stm32can_txmb0empty(uint32_t tsr_regval) +{ + return (tsr_regval & CAN_TSR_TME0) != 0 && + (tsr_regval & CAN_TSR_RQCP0) == 0; +} + +/**************************************************************************** + * Name: stm32can_txmb1empty + * + * Input Parameters: + * tsr_regval - value of CAN transmit status register + * + * Returned Value: + * Returns true if mailbox 1 is empty and can be used for sending. + * + ****************************************************************************/ + +static bool stm32can_txmb1empty(uint32_t tsr_regval) +{ + return (tsr_regval & CAN_TSR_TME1) != 0 && + (tsr_regval & CAN_TSR_RQCP1) == 0; +} + +/**************************************************************************** + * Name: stm32can_txmb2empty + * + * Input Parameters: + * tsr_regval - value of CAN transmit status register + * + * Returned Value: + * Returns true if mailbox 2 is empty and can be used for sending. + * + ****************************************************************************/ + +static bool stm32can_txmb2empty(uint32_t tsr_regval) +{ + return (tsr_regval & CAN_TSR_TME2) != 0 && + (tsr_regval & CAN_TSR_RQCP2) == 0; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_cansockinitialize + * + * Description: + * Initialize the selected CAN port as CAN socket interface + * + * Input Parameters: + * Port number (for hardware that has multiple CAN interfaces) + * + * Returned Value: + * OK on success; Negated errno on failure. + * + ****************************************************************************/ + +int stm32_cansockinitialize(int port) +{ + struct stm32_can_s *priv = NULL; + int ret = OK; + + ninfo("CAN%" PRIu8 "\n", port); + + /* NOTE: Peripherical clocking for CAN1 and/or CAN2 was already provided + * by stm32_clockconfig() early in the reset sequence. + */ + +#ifdef CONFIG_STM32_CAN1 + if (port == 1) + { + /* Select the CAN1 device structure */ + + priv = &g_can1priv; + + /* Configure CAN1 pins. The ambiguous settings in the stm32*_pinmap.h + * file must have been disambiguated in the board.h file. + */ + + stm32_configgpio(GPIO_CAN1_RX); + stm32_configgpio(GPIO_CAN1_TX); + } + else +#endif +#ifdef CONFIG_STM32_CAN2 + if (port == 2) + { + /* Select the CAN2 device structure */ + + priv = &g_can2priv; + + /* Configure CAN2 pins. The ambiguous settings in the stm32*_pinmap.h + * file must have been disambiguated in the board.h file. + */ + + stm32_configgpio(GPIO_CAN2_RX); + stm32_configgpio(GPIO_CAN2_TX); + } + else +#endif + { + nerr("ERROR: Unsupported port %d\n", port); + ret = -EINVAL; + goto errout; + } + + /* Initialize the driver structure */ + + priv->dev.d_ifup = stm32can_ifup; + priv->dev.d_ifdown = stm32can_ifdown; + priv->dev.d_txavail = stm32can_txavail; +#ifdef CONFIG_NETDEV_IOCTL + priv->dev.d_ioctl = stm32can_netdev_ioctl; +#endif + priv->dev.d_private = priv; + + /* Put the interface in the down state. This usually amounts to resetting + * the device and/or calling stm32can_ifdown(). + */ + + ninfo("callbacks done\n"); + + stm32can_ifdown(&priv->dev); + + /* Register the device with the OS so that socket IOCTLs can be performed */ + + ret = netdev_register(&priv->dev, NET_LL_CAN); + +errout: + return ret; +} + +/**************************************************************************** + * Name: arm_netinitialize + * + * Description: + * Initialize the CAN device interfaces. If there is more than one device + * interface in the chip, then board-specific logic will have to provide + * this function to determine which, if any, CAN interfaces should be + * initialized. + * + ****************************************************************************/ + +#if !defined(CONFIG_NETDEV_LATEINIT) +void arm_netinitialize(void) +{ +#ifdef CONFIG_STM32_CAN1 + stm32_cansockinitialize(1); +#endif + +#ifdef CONFIG_STM32_CAN2 + stm32_cansockinitialize(2); +#endif +} +#endif diff --git a/arch/arm/src/stm32/stm32_capture.h b/arch/arm/src/common/stm32/stm32_capture.h similarity index 81% rename from arch/arm/src/stm32/stm32_capture.h rename to arch/arm/src/common/stm32/stm32_capture.h index 33f2a3157a13f..ab80b5c4c1ff9 100644 --- a/arch/arm/src/stm32/stm32_capture.h +++ b/arch/arm/src/common/stm32/stm32_capture.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_capture.h + * arch/arm/src/common/stm32/stm32_capture.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_STM32_CAPTURE_H -#define __ARCH_ARM_SRC_STM32_STM32_CAPTURE_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_CAPTURE_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_CAPTURE_H /**************************************************************************** * Included Files @@ -29,6 +29,12 @@ #include +#include +#include + +#include +#include + #include "chip.h" #include #include "hardware/stm32_tim.h" @@ -64,48 +70,28 @@ extern "C" #define EXTERN extern #endif -/* Capture Device Structure */ - struct stm32_cap_dev_s { struct stm32_cap_ops_s *ops; }; -/* Capture input EDGE sources */ - typedef enum { - /* Mapped */ - STM32_CAP_MAPPED_MASK = (GTIM_CCMR1_CC1S_MASK), STM32_CAP_MAPPED_TI1 = (GTIM_CCMR_CCS_CCIN1), STM32_CAP_MAPPED_TI2 = (GTIM_CCMR_CCS_CCIN2), STM32_CAP_MAPPED_TI3 = (GTIM_CCMR_CCS_CCIN1), STM32_CAP_MAPPED_TI4 = (GTIM_CCMR_CCS_CCIN2), - -/* TODO STM32_CAP_MAPPED_TRC = (GTIM_CCMR_CCS_CCINTRC), */ - - /* Event prescaler */ - STM32_CAP_INPSC_MASK = (GTIM_CCMR1_IC1PSC_MASK), STM32_CAP_INPSC_NO = (0 << GTIM_CCMR1_IC1PSC_SHIFT), STM32_CAP_INPSC_2EVENTS = (1 << GTIM_CCMR1_IC1PSC_SHIFT), STM32_CAP_INPSC_4EVENTS = (2 << GTIM_CCMR1_IC1PSC_SHIFT), STM32_CAP_INPSC_8EVENTS = (3 << GTIM_CCMR1_IC1PSC_SHIFT), - - /* Event prescaler */ - STM32_CAP_FILTER_MASK = (GTIM_CCMR1_IC1F_MASK), STM32_CAP_FILTER_NO = (0 << GTIM_CCMR1_IC1F_SHIFT), - - /* Internal clock with N time to confirm event */ - STM32_CAP_FILTER_INT_N2 = (1 << GTIM_CCMR1_IC1F_SHIFT), STM32_CAP_FILTER_INT_N4 = (2 << GTIM_CCMR1_IC1F_SHIFT), STM32_CAP_FILTER_INT_N8 = (3 << GTIM_CCMR1_IC1F_SHIFT), - - /* DTS clock div by D with N time to confirm event */ - STM32_CAP_FILTER_DTS_D2_N6 = (4 << GTIM_CCMR1_IC1F_SHIFT), STM32_CAP_FILTER_DTS_D2_N8 = (5 << GTIM_CCMR1_IC1F_SHIFT), STM32_CAP_FILTER_DTS_D4_N6 = (6 << GTIM_CCMR1_IC1F_SHIFT), @@ -118,9 +104,6 @@ typedef enum STM32_CAP_FILTER_DTS_D32_N5 = (13 << GTIM_CCMR1_IC1F_SHIFT), STM32_CAP_FILTER_DTS_D32_N6 = (14 << GTIM_CCMR1_IC1F_SHIFT), STM32_CAP_FILTER_DTS_D32_N8 = (15 << GTIM_CCMR1_IC1F_SHIFT), - - /* EDGE */ - STM32_CAP_EDGE_MASK = (3 << 8), STM32_CAP_EDGE_DISABLED = (0 << 8), STM32_CAP_EDGE_RISING = (1 << 8), @@ -128,12 +111,8 @@ typedef enum STM32_CAP_EDGE_BOTH = (3 << 8), } stm32_cap_ch_cfg_t; -/* Slave mode control configure */ - typedef enum { - /* Slave mode selection */ - STM32_CAP_SMS_MASK = (7 << GTIM_SMCR_SMS_SHIFT), STM32_CAP_SMS_INT = (0 << GTIM_SMCR_SMS_SHIFT), STM32_CAP_SMS_ENC1 = (1 << GTIM_SMCR_SMS_SHIFT), @@ -143,9 +122,6 @@ typedef enum STM32_CAP_SMS_GAT = (5 << GTIM_SMCR_SMS_SHIFT), STM32_CAP_SMS_TRG = (6 << GTIM_SMCR_SMS_SHIFT), STM32_CAP_SMS_EXT = (7 << GTIM_SMCR_SMS_SHIFT), - - /* Trigger selection */ - STM32_CAP_TS_MASK = (7 << GTIM_SMCR_TS_SHIFT), STM32_CAP_TS_ITR0 = (0 << GTIM_SMCR_TS_SHIFT), STM32_CAP_TS_ITR1 = (1 << GTIM_SMCR_TS_SHIFT), @@ -155,25 +131,16 @@ typedef enum STM32_CAP_TS_TI1FP1 = (5 << GTIM_SMCR_TS_SHIFT), STM32_CAP_TS_TI2FP2 = (6 << GTIM_SMCR_TS_SHIFT), STM32_CAP_TS_ETRF = (7 << GTIM_SMCR_TS_SHIFT), - - /* Master/Slave mode setting */ - STM32_CAP_MSM_MASK = (1 << 7) } stm32_cap_smc_cfg_t; -/* Capture flags */ - typedef enum { - /* One of the following */ - STM32_CAP_FLAG_IRQ_COUNTER = (GTIM_SR_UIF), - STM32_CAP_FLAG_IRQ_CH_1 = (GTIM_SR_CC1IF), STM32_CAP_FLAG_IRQ_CH_2 = (GTIM_SR_CC2IF), STM32_CAP_FLAG_IRQ_CH_3 = (GTIM_SR_CC3IF), STM32_CAP_FLAG_IRQ_CH_4 = (GTIM_SR_CC4IF), - STM32_CAP_FLAG_OF_CH_1 = (GTIM_SR_CC1OF), STM32_CAP_FLAG_OF_CH_2 = (GTIM_SR_CC2OF), STM32_CAP_FLAG_OF_CH_3 = (GTIM_SR_CC3OF), @@ -184,8 +151,6 @@ typedef enum #define STM32_CAP_FLAG_OF_CH(ch) (GTIM_SR_CC1OF<<((ch)-1)) #define STM32_CAP_CHANNEL_COUNTER 0 -/* Capture Operations */ - struct stm32_cap_ops_s { int (*setsmc)(struct stm32_cap_dev_s *dev, stm32_cap_smc_cfg_t cfg); @@ -202,38 +167,9 @@ struct stm32_cap_ops_s uint32_t (*rstcounter)(struct stm32_cap_dev_s *dev); }; -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/* Power-up timer and get its structure */ - struct stm32_cap_dev_s *stm32_cap_init(int timer); - -/* Power-down timer, mark it as unused */ - int stm32_cap_deinit(struct stm32_cap_dev_s *dev); - -/**************************************************************************** - * Name: stm32_cap_initialize - * - * Description: - * Initialize one timer for use with the upper_level capture driver. - * - * Input Parameters: - * timer - A number identifying the timer use. The number of valid timer - * IDs varies with the STM32 MCU and MCU family but is somewhere in - * the range of {1,..,5 8,...,14}. - * - * Returned Value: - * On success, a pointer to the STM32 lower half capture driver returned. - * NULL is returned on any failure. - * - ****************************************************************************/ - -#ifdef CONFIG_CAPTURE struct cap_lowerhalf_s *stm32_cap_initialize(int timer); -#endif #undef EXTERN #if defined(__cplusplus) @@ -241,4 +177,5 @@ struct cap_lowerhalf_s *stm32_cap_initialize(int timer); #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32_STM32_CAPTURE_H */ + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_CAPTURE_H */ diff --git a/arch/arm/src/common/stm32/stm32_capture_m3m4_v1.c b/arch/arm/src/common/stm32/stm32_capture_m3m4_v1.c new file mode 100644 index 0000000000000..48fcfe57c7390 --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_capture_m3m4_v1.c @@ -0,0 +1,1522 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_capture_m3m4_v1.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32.h" +#include "stm32_gpio.h" +#include "stm32_capture.h" + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/* Configuration ************************************************************/ + +#if defined(GPIO_TIM1_CH1IN) || defined(GPIO_TIM2_CH1IN) || defined(GPIO_TIM3_CH1IN) || \ + defined(GPIO_TIM4_CH1IN) || defined(GPIO_TIM5_CH1IN) || defined(GPIO_TIM8_CH1IN) || \ + defined(GPIO_TIM9_CH1IN) || defined(GPIO_TIM10_CH1IN) || defined(GPIO_TIM11_CH1IN) || \ + defined(GPIO_TIM12_CH1IN) || defined(GPIO_TIM13_CH1IN) || defined(GPIO_TIM14_CH1IN) +# define HAVE_CH1IN 1 +#endif + +#if defined(GPIO_TIM1_CH2IN) || defined(GPIO_TIM2_CH2IN) || defined(GPIO_TIM3_CH2IN) || \ + defined(GPIO_TIM4_CH2IN) || defined(GPIO_TIM5_CH2IN) || defined(GPIO_TIM8_CH2IN) || \ + defined(GPIO_TIM9_CH2IN) || defined(GPIO_TIM12_CH2IN) +# define HAVE_CH2IN 1 +#endif + +#if defined(GPIO_TIM1_CH3IN) || defined(GPIO_TIM2_CH3IN) || defined(GPIO_TIM3_CH3IN) || \ + defined(GPIO_TIM4_CH3IN) || defined(GPIO_TIM5_CH3IN) || defined(GPIO_TIM8_CH3IN) +# define HAVE_CH3IN 1 +#endif + +#if defined(GPIO_TIM1_CH4IN) || defined(GPIO_TIM2_CH4IN) || defined(GPIO_TIM3_CH4IN) || \ + defined(GPIO_TIM4_CH4IN) || defined(GPIO_TIM5_CH4IN) || defined(GPIO_TIM8_CH4IN) +# define HAVE_CH4IN 1 +#endif + +#if defined(CONFIG_STM32_TIM1_CAP) || defined(CONFIG_STM32_TIM8_CAP) +#define USE_ADVENCED_TIM 1 +#endif + +#if defined(GPIO_TIM1_EXT_CLK_IN) || defined(GPIO_TIM2_EXT_CLK_IN) || \ + defined(GPIO_TIM3_EXT_CLK_IN) || defined(GPIO_TIM4_EXT_CLK_IN) || \ + defined(GPIO_TIM5_EXT_CLK_IN) || defined(GPIO_TIM8_EXT_CLK_IN) || \ + defined(GPIO_TIM9_EXT_CLK_IN) || defined(GPIO_TIM12_EXT_CLK_IN) +# define USE_EXT_CLOCK 1 +#endif + +/* This module then only compiles if there are enabled timers that are not + * intended for some other purpose. + */ + +#if defined(CONFIG_STM32_TIM1_CAP) || defined(CONFIG_STM32_TIM2_CAP) || \ + defined(CONFIG_STM32_TIM3_CAP) || defined(CONFIG_STM32_TIM4_CAP) || \ + defined(CONFIG_STM32_TIM5_CAP) || defined(CONFIG_STM32_TIM8_CAP) || \ + defined(CONFIG_STM32_TIM9_CAP) || defined(CONFIG_STM32_TIM10_CAP) || \ + defined(CONFIG_STM32_TIM11_CAP) || defined(CONFIG_STM32_TIM12_CAP) || \ + defined(CONFIG_STM32_TIM13_CAP) || defined(CONFIG_STM32_TIM14_CAP) + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/* TIM Device Structure */ + +struct stm32_cap_priv_s +{ + const struct stm32_cap_ops_s *ops; + const uint32_t base; /* TIMn base address */ +#ifdef USE_EXT_CLOCK + const uint32_t gpio_clk; /* TIMn base address */ +#endif + const int irq; /* irq vector */ +#ifdef USE_ADVENCED_TIM + const int irq_of; /* irq timer overflow is deferent in advanced timer */ +#endif +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/* Get a 16-bit register value by offset */ + +static inline +uint16_t stm32_getreg16(const struct stm32_cap_priv_s *priv, + uint8_t offset) +{ + return getreg16(priv->base + offset); +} + +/* Put a 16-bit register value by offset */ + +static inline void stm32_putreg16(const struct stm32_cap_priv_s *priv, + uint8_t offset, uint16_t value) +{ + putreg16(value, priv->base + offset); +} + +/* Modify a 16-bit register value by offset */ + +static inline void stm32_modifyreg16(const struct stm32_cap_priv_s *priv, + uint8_t offset, uint16_t clearbits, + uint16_t setbits) +{ + modifyreg16(priv->base + offset, clearbits, setbits); +} + +/* Get a 32-bit register value by offset. This applies only for the STM32 F4 + * 32-bit registers (CNT, ARR, CRR1-4) in the 32-bit timers TIM2 and TIM5. + */ + +static inline +uint32_t stm32_getreg32(const struct stm32_cap_priv_s *priv, + uint8_t offset) +{ + return getreg32(priv->base + offset); +} + +/* Put a 32-bit register value by offset. This applies only for the STM32 F4 + * 32-bit registers (CNT, ARR, CRR1-4) in the 32-bit timers TIM2 and TIM5. + */ + +static inline void stm32_putreg32(const struct stm32_cap_priv_s *priv, + uint8_t offset, uint32_t value) +{ + putreg32(value, priv->base + offset); +} + +/**************************************************************************** + * gpio Functions + ****************************************************************************/ + +static inline +uint32_t stm32_cap_gpio(const struct stm32_cap_priv_s *priv, + int channel) +{ + switch (priv->base) + { +#ifdef CONFIG_STM32_TIM1_CAP + case STM32_TIM1_BASE: + switch (channel) + { +#ifdef GPIO_TIM1_EXT_CLK_IN + case STM32_CAP_CHANNEL_COUNTER: + return GPIO_TIM1_EXT_CLK_IN; +#endif +#ifdef GPIO_TIM1_CH1IN + case 1: + return GPIO_TIM1_CH1IN; +#endif +#ifdef GPIO_TIM1_CH2IN + case 2: + return GPIO_TIM1_CH2IN; +#endif +#ifdef GPIO_TIM1_CH3IN + case 3: + return GPIO_TIM1_CH3IN; +#endif +#ifdef GPIO_TIM1_CH4IN + case 4: + return GPIO_TIM1_CH4IN; +#endif + } + break; +#endif +#ifdef CONFIG_STM32_TIM2_CAP + case STM32_TIM2_BASE: + switch (channel) + { +#ifdef GPIO_TIM2_EXT_CLK_IN + case STM32_CAP_CHANNEL_COUNTER: + return GPIO_TIM2_EXT_CLK_IN; +#endif +#ifdef GPIO_TIM2_CH1IN + case 1: + return GPIO_TIM2_CH1IN; +#endif +#ifdef GPIO_TIM2_CH2IN + case 2: + return GPIO_TIM2_CH2IN; +#endif +#ifdef GPIO_TIM2_CH3IN + case 3: + return GPIO_TIM2_CH3IN; +#endif +#ifdef GPIO_TIM2_CH4IN + case 4: + return GPIO_TIM2_CH4IN; +#endif + } + break; +#endif +#ifdef CONFIG_STM32_TIM3_CAP + case STM32_TIM3_BASE: + switch (channel) + { +#ifdef GPIO_TIM3_EXT_CLK_IN + case STM32_CAP_CHANNEL_COUNTER: + return GPIO_TIM3_EXT_CLK_IN; +#endif +#ifdef GPIO_TIM3_CH1IN + case 1: + return GPIO_TIM3_CH1IN; +#endif +#ifdef GPIO_TIM3_CH2IN + case 2: + return GPIO_TIM3_CH2IN; +#endif +#ifdef GPIO_TIM3_CH3IN + case 3: + return GPIO_TIM3_CH3IN; +#endif +#ifdef GPIO_TIM3_CH4IN + case 4: + return GPIO_TIM3_CH4IN; +#endif + } + break; +#endif +#ifdef CONFIG_STM32_TIM4_CAP + case STM32_TIM4_BASE: + switch (channel) + { +#ifdef GPIO_TIM4_EXT_CLK_IN + case STM32_CAP_CHANNEL_COUNTER: + return GPIO_TIM4_EXT_CLK_IN; +#endif +#ifdef GPIO_TIM4_CH1IN + case 1: + return GPIO_TIM4_CH1IN; +#endif +#ifdef GPIO_TIM4_CH2IN + case 2: + return GPIO_TIM4_CH2IN; +#endif +#ifdef GPIO_TIM4_CH3IN + case 3: + return GPIO_TIM4_CH3IN; +#endif +#ifdef GPIO_TIM4_CH4IN + case 4: + return GPIO_TIM4_CH4IN; +#endif + } + break; +#endif +#ifdef CONFIG_STM32_TIM5_CAP + case STM32_TIM5_BASE: + switch (channel) + { +#ifdef GPIO_TIM5_EXT_CLK_IN + case STM32_CAP_CHANNEL_COUNTER: + return GPIO_TIM5_EXT_CLK_IN; +#endif +#ifdef GPIO_TIM5_CH1IN + case 1: + return GPIO_TIM5_CH1IN; +#endif +#ifdef GPIO_TIM5_CH2IN + case 2: + return GPIO_TIM5_CH2IN; +#endif +#ifdef GPIO_TIM5_CH3IN + case 3: + return GPIO_TIM5_CH3IN; +#endif +#ifdef GPIO_TIM5_CH4IN + case 4: + return GPIO_TIM5_CH4IN; +#endif + } + break; +#endif + + /* TIM6 and TIM7 cannot be used in capture */ + +#ifdef CONFIG_STM32_TIM8_CAP + case STM32_TIM8_BASE: + switch (channel) + { +#ifdef GPIO_TIM8_EXT_CLK_IN + case STM32_CAP_CHANNEL_COUNTER: + return GPIO_TIM8_EXT_CLK_IN; +#endif +#ifdef GPIO_TIM8_CH1IN + case 1: + return GPIO_TIM8_CH1IN; +#endif +#ifdef GPIO_TIM8_CH2IN + case 2: + return GPIO_TIM8_CH2IN; +#endif +#ifdef GPIO_TIM8_CH3IN + case 3: + return GPIO_TIM8_CH3IN; +#endif +#ifdef GPIO_TIM8_CH4IN + case 4: + return GPIO_TIM8_CH4IN; +#endif + } + break; +#endif + +#ifdef CONFIG_STM32_TIM9_CAP + case STM32_TIM9_BASE: + switch (channel) + { +#ifdef GPIO_TIM9_EXT_CLK_IN + case STM32_CAP_CHANNEL_COUNTER: + return GPIO_TIM9_EXT_CLK_IN; +#endif +#ifdef GPIO_TIM9_CH1IN + case 1: + return GPIO_TIM9_CH1IN; +#endif +#ifdef GPIO_TIM9_CH2IN + case 2: + return GPIO_TIM9_CH2IN; +#endif +#ifdef GPIO_TIM9_CH3IN + case 3: + return GPIO_TIM9_CH3IN; +#endif +#ifdef GPIO_TIM9_CH4IN + case 4: + return GPIO_TIM9_CH4IN; +#endif + } + break; +#endif + +#ifdef CONFIG_STM32_TIM10_CAP + case STM32_TIM10_BASE: + switch (channel) + { +#ifdef GPIO_TIM10_EXT_CLK_IN + case STM32_CAP_CHANNEL_COUNTER: + return GPIO_TIM10_EXT_CLK_IN; +#endif +#ifdef GPIO_TIM10_CH1IN + case 1: + return GPIO_TIM10_CH1IN; +#endif +#ifdef GPIO_TIM10_CH2IN + case 2: + return GPIO_TIM10_CH2IN; +#endif +#ifdef GPIO_TIM10_CH4IN + case 3: + return GPIO_TIM10_CH4IN; +#endif +#ifdef GPIO_TIM10_CH5IN + case 4: + return GPIO_TIM10_CH5IN; +#endif + } + break; +#endif + +#ifdef CONFIG_STM32_TIM11_CAP + case STM32_TIM11_BASE: + switch (channel) + { +#ifdef GPIO_TIM11_EXT_CLK_IN + case STM32_CAP_CHANNEL_COUNTER: + return GPIO_TIM11_EXT_CLK_IN; +#endif +#ifdef GPIO_TIM11_CH1IN + case 1: + return GPIO_TIM11_CH1IN; +#endif +#ifdef GPIO_TIM11_CH2IN + case 2: + return GPIO_TIM11_CH2IN; +#endif +#ifdef GPIO_TIM11_CH4IN + case 3: + return GPIO_TIM11_CH4IN; +#endif +#ifdef GPIO_TIM11_CH5IN + case 4: + return GPIO_TIM11_CH5IN; +#endif + } + break; +#endif + +#ifdef CONFIG_STM32_TIM12_CAP + case STM32_TIM12_BASE: + switch (channel) + { +#ifdef GPIO_TIM12_EXT_CLK_IN + case STM32_CAP_CHANNEL_COUNTER: + return GPIO_TIM12_EXT_CLK_IN; +#endif +#ifdef GPIO_TIM12_CH1IN + case 1: + return GPIO_TIM12_CH1IN; +#endif +#ifdef GPIO_TIM12_CH2IN + case 2: + return GPIO_TIM12_CH2IN; +#endif +#ifdef GPIO_TIM12_CH4IN + case 3: + return GPIO_TIM12_CH4IN; +#endif +#ifdef GPIO_TIM12_CH5IN + case 4: + return GPIO_TIM12_CH5IN; +#endif + } + break; +#endif + +#ifdef CONFIG_STM32_TIM13_CAP + case STM32_TIM13_BASE: + switch (channel) + { +#ifdef GPIO_TIM13_EXT_CLK_IN + case STM32_CAP_CHANNEL_COUNTER: + return GPIO_TIM13_EXT_CLK_IN; +#endif +#ifdef GPIO_TIM13_CH1IN + case 1: + return GPIO_TIM13_CH1IN; +#endif +#ifdef GPIO_TIM13_CH2IN + case 2: + return GPIO_TIM13_CH2IN; +#endif +#ifdef GPIO_TIM13_CH4IN + case 3: + return GPIO_TIM13_CH4IN; +#endif +#ifdef GPIO_TIM13_CH5IN + case 4: + return GPIO_TIM13_CH5IN; +#endif + } + break; +#endif + +#ifdef CONFIG_STM32_TIM14_CAP + case STM32_TIM14_BASE: + switch (channel) + { +#ifdef GPIO_TIM14_EXT_CLK_IN + case STM32_CAP_CHANNEL_COUNTER: + return GPIO_TIM14_EXT_CLK_IN; +#endif +#ifdef GPIO_TIM14_CH1IN + case 1: + return GPIO_TIM14_CH1IN; +#endif +#ifdef GPIO_TIM14_CH2IN + case 2: + return GPIO_TIM14_CH2IN; +#endif +#ifdef GPIO_TIM14_CH4IN + case 3: + return GPIO_TIM14_CH4IN; +#endif +#ifdef GPIO_TIM14_CH5IN + case 4: + return GPIO_TIM14_CH5IN; +#endif + } + break; +#endif + } + + return 0; +} + +static inline int stm32_cap_set_rcc(const struct stm32_cap_priv_s *priv, + bool on) +{ + uint32_t offset = 0; + uint32_t mask = 0; + + switch (priv->base) + { +#ifdef CONFIG_STM32_TIM1_CAP + case STM32_TIM1_BASE: + offset = STM32_RCC_APB2ENR; + mask = RCC_APB2ENR_TIM1EN; + break; +#endif +#ifdef CONFIG_STM32_TIM2_CAP + case STM32_TIM2_BASE: + offset = STM32_RCC_APB1ENR; + mask = RCC_APB1ENR_TIM2EN; + break; +#endif +#ifdef CONFIG_STM32_TIM3_CAP + case STM32_TIM3_BASE: + offset = STM32_RCC_APB1ENR; + mask = RCC_APB1ENR_TIM3EN; + break; +#endif +#ifdef CONFIG_STM32_TIM4_CAP + case STM32_TIM4_BASE: + offset = STM32_RCC_APB1ENR; + mask = RCC_APB1ENR_TIM4EN; + break; +#endif +#ifdef CONFIG_STM32_TIM5_CAP + case STM32_TIM5_BASE: + offset = STM32_RCC_APB1ENR; + mask = RCC_APB1ENR_TIM5EN; + break; +#endif + + /* TIM6 and TIM7 cannot be used in capture */ + +#ifdef CONFIG_STM32_TIM8_CAP + case STM32_TIM8_BASE: + offset = STM32_RCC_APB2ENR; + mask = RCC_APB2ENR_TIM8EN; + break; +#endif +#ifdef CONFIG_STM32_TIM9_CAP + case STM32_TIM9_BASE: + offset = STM32_RCC_APB2ENR; + mask = RCC_APB2ENR_TIM9EN; + break; +#endif +#ifdef CONFIG_STM32_TIM10_CAP + case STM32_TIM10_BASE: + offset = STM32_RCC_APB2ENR; + mask = RCC_APB2ENR_TIM10EN; + break; +#endif +#ifdef CONFIG_STM32_TIM11_CAP + case STM32_TIM11_BASE: + offset = STM32_RCC_APB2ENR; + mask = RCC_APB2ENR_TIM11EN; + break; +#endif +#ifdef CONFIG_STM32_TIM12_CAP + case STM32_TIM12_BASE: + offset = STM32_RCC_APB1ENR; + mask = RCC_APB1ENR_TIM12EN; + break; +#endif +#ifdef CONFIG_STM32_TIM13_CAP + case STM32_TIM13_BASE: + offset = STM32_RCC_APB1ENR; + mask = RCC_APB1ENR_TIM13EN; + break; +#endif +#ifdef CONFIG_STM32_TIM14_CAP + case STM32_TIM14_BASE: + offset = STM32_RCC_APB1ENR; + mask = RCC_APB1ENR_TIM14EN; + break; +#endif + } + + if (mask == 0) + { + return ERROR; + } + + if (on) + { + modifyreg32(offset, 0, mask); + } + else + { + modifyreg32(offset, mask, 0); + } + + return OK; +} + +/**************************************************************************** + * Basic Functions + ****************************************************************************/ + +static int stm32_cap_setclock(struct stm32_cap_dev_s *dev, + uint32_t freq, uint32_t max) +{ + const struct stm32_cap_priv_s *priv = (const struct stm32_cap_priv_s *)dev; + uint32_t freqin; + int prescaler; + + /* Disable Timer? */ + + if (freq == 0) + { + /* Disable Timer */ + + stm32_modifyreg16(priv, STM32_BTIM_CR1_OFFSET, ATIM_CR1_CEN, 0); + return 0; + } + + /* Get the input clock frequency for this timer. These vary with + * different timer clock sources, MCU-specific timer configuration, and + * board-specific clock configuration. The correct input clock frequency + * must be defined in the board.h header file. + */ + + switch (priv->base) + { +#ifdef CONFIG_STM32_TIM1 + case STM32_TIM1_BASE: + freqin = STM32_APB2_TIM1_CLKIN; + break; +#endif +#ifdef CONFIG_STM32_TIM2 + case STM32_TIM2_BASE: + freqin = STM32_APB1_TIM2_CLKIN; + break; +#endif +#ifdef CONFIG_STM32_TIM3 + case STM32_TIM3_BASE: + freqin = STM32_APB1_TIM3_CLKIN; + break; +#endif +#ifdef CONFIG_STM32_TIM4 + case STM32_TIM4_BASE: + freqin = STM32_APB1_TIM4_CLKIN; + break; +#endif +#ifdef CONFIG_STM32_TIM5 + case STM32_TIM5_BASE: + freqin = STM32_APB1_TIM5_CLKIN; + break; +#endif +#ifdef CONFIG_STM32_TIM8 + case STM32_TIM8_BASE: + freqin = STM32_APB2_TIM8_CLKIN; + break; +#endif +#ifdef CONFIG_STM32_TIM9 + case STM32_TIM9_BASE: + freqin = STM32_APB2_TIM9_CLKIN; + break; +#endif +#ifdef CONFIG_STM32_TIM10 + case STM32_TIM10_BASE: + freqin = STM32_APB2_TIM10_CLKIN; + break; +#endif +#ifdef CONFIG_STM32_TIM11 + case STM32_TIM11_BASE: + freqin = STM32_APB2_TIM11_CLKIN; + break; +#endif +#ifdef CONFIG_STM32_TIM12 + case STM32_TIM12_BASE: + freqin = STM32_APB1_TIM12_CLKIN; + break; +#endif +#ifdef CONFIG_STM32_TIM13 + case STM32_TIM13_BASE: + freqin = STM32_APB1_TIM13_CLKIN; + break; +#endif +#ifdef CONFIG_STM32_TIM14 + case STM32_TIM14_BASE: + freqin = STM32_APB1_TIM14_CLKIN; + break; +#endif + + default: + return -EINVAL; + } + + /* Select a pre-scaler value for this timer using the input clock + * frequency. + */ + + prescaler = freqin / freq; + + /* We need to decrement value for '1', but only, if we are allowed to + * not to cause underflow. Check for overflow. + */ + + if (prescaler > 0) + { + prescaler--; + } + + if (prescaler > 0xffff) + { + prescaler = 0xffff; + } + + /* Set Maximum */ + + stm32_putreg32(priv, STM32_BTIM_ARR_OFFSET, max); + + /* Set prescaler */ + + stm32_putreg16(priv, STM32_BTIM_PSC_OFFSET, prescaler); + + /* Reset counter timer */ + + stm32_modifyreg16(priv, STM32_BTIM_EGR_OFFSET, 0, BTIM_EGR_UG); + + /* Enable timer */ + + stm32_modifyreg16(priv, STM32_BTIM_CR1_OFFSET, 0, BTIM_CR1_CEN); + +#ifdef USE_ADVENCED_TIM + /* Advanced registers require Main Output Enable */ + + if (priv->base == STM32_TIM1_BASE || priv->base == STM32_TIM8_BASE) + { + stm32_modifyreg16(priv, STM32_ATIM_BDTR_OFFSET, 0, ATIM_BDTR_MOE); + } +#endif + + return prescaler; +} + +/**************************************************************************** + * Name: stm32_cap_setsmc + * + * Description: + * set slave mode control register + * + * Input Parameters: + * dev - A pointer of the stm32 capture device structure. + * cfg - Slave mode control register configure of timer. + * + * Returned Value: + * Zero on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int stm32_cap_setsmc(struct stm32_cap_dev_s *dev, + stm32_cap_smc_cfg_t cfg) +{ + const struct stm32_cap_priv_s *priv = (const struct stm32_cap_priv_s *)dev; + uint16_t regval = 0; + uint16_t mask = 0; + + switch (cfg & STM32_CAP_SMS_MASK) + { + case STM32_CAP_SMS_INT: + regval |= GTIM_SMCR_DISAB; + break; + + case STM32_CAP_SMS_ENC1: + regval |= GTIM_SMCR_ENCMD1; + break; + + case STM32_CAP_SMS_ENC2: + regval |= GTIM_SMCR_ENCMD2; + break; + + case STM32_CAP_SMS_ENC3: + regval |= GTIM_SMCR_ENCMD3; + break; + + case STM32_CAP_SMS_RST: + regval |= GTIM_SMCR_RESET; + break; + + case STM32_CAP_SMS_GAT: + regval |= GTIM_SMCR_GATED; + break; + + case STM32_CAP_SMS_TRG: + regval |= GTIM_SMCR_TRIGGER; + break; + + case STM32_CAP_SMS_EXT: + regval |= GTIM_SMCR_EXTCLK1; + break; + + default: + break; + } + + switch (cfg & STM32_CAP_TS_MASK) + { + case STM32_CAP_TS_ITR0: + regval |= GTIM_SMCR_ITR0; + break; + + case STM32_CAP_TS_ITR1: + regval |= GTIM_SMCR_ITR1; + break; + + case STM32_CAP_TS_ITR2: + regval |= GTIM_SMCR_ITR2; + break; + + case STM32_CAP_TS_ITR3: + regval |= GTIM_SMCR_ITR3; + break; + + case STM32_CAP_TS_TI1FED: + regval |= GTIM_SMCR_TI1FED; + break; + + case STM32_CAP_TS_TI1FP1: + regval |= GTIM_SMCR_TI1FP1; + break; + + case STM32_CAP_TS_TI2FP2: + regval |= GTIM_SMCR_TI2FP2; + break; + + case STM32_CAP_TS_ETRF: + regval |= GTIM_SMCR_ETRF; + break; + + default: + break; + } + + if (cfg & STM32_CAP_MSM_MASK) + { + regval |= STM32_CAP_MSM_MASK; + } + + mask = (STM32_CAP_SMS_MASK | STM32_CAP_TS_MASK | STM32_CAP_MSM_MASK); + stm32_modifyreg16(priv, STM32_GTIM_SMCR_OFFSET, mask, regval); + + return OK; +} + +static int stm32_cap_setisr(struct stm32_cap_dev_s *dev, xcpt_t handler, + void *arg) +{ + const struct stm32_cap_priv_s *priv = (const struct stm32_cap_priv_s *)dev; + int irq; +#ifdef USE_ADVENCED_TIM + int irq_of; +#endif + + DEBUGASSERT(dev != NULL); + + irq = priv->irq; +#ifdef USE_ADVENCED_TIM + irq_of = priv->irq_of; +#endif + + /* Disable interrupt when callback is removed */ + + if (!handler) + { + up_disable_irq(irq); + irq_detach(irq); + +#ifdef USE_ADVENCED_TIM + if (priv->irq_of) + { + up_disable_irq(irq_of); + irq_detach(irq_of); + } +#endif + + return OK; + } + + /* Otherwise set callback and enable interrupt */ + + irq_attach(irq, handler, arg); + up_enable_irq(irq); + +#ifdef USE_ADVENCED_TIM + if (priv->irq_of) + { + irq_attach(priv->irq_of, handler, arg); + up_enable_irq(priv->irq_of); + } +#endif + + return OK; +} + +static void stm32_cap_enableint(struct stm32_cap_dev_s *dev, + stm32_cap_flags_t src, bool on) +{ + const struct stm32_cap_priv_s *priv = (const struct stm32_cap_priv_s *)dev; + uint16_t mask = 0; + + DEBUGASSERT(dev != NULL); + + if (src & STM32_CAP_FLAG_IRQ_COUNTER) + { + mask |= ATIM_DIER_UIE; + } + + if (src & STM32_CAP_FLAG_IRQ_CH_1) + { + mask |= ATIM_DIER_CC1IE; + } + + if (src & STM32_CAP_FLAG_IRQ_CH_2) + { + mask |= ATIM_DIER_CC2IE; + } + + if (src & STM32_CAP_FLAG_IRQ_CH_3) + { + mask |= ATIM_DIER_CC3IE; + } + + if (src & STM32_CAP_FLAG_IRQ_CH_4) + { + mask |= ATIM_DIER_CC4IE; + } + + /* Not IRQ on channel overflow */ + + if (on) + { + stm32_modifyreg16(priv, STM32_BTIM_DIER_OFFSET, 0, mask); + } + else + { + stm32_modifyreg16(priv, STM32_BTIM_DIER_OFFSET, mask, 0); + } +} + +static void stm32_cap_ackflags(struct stm32_cap_dev_s *dev, int flags) +{ + const struct stm32_cap_priv_s *priv = (const struct stm32_cap_priv_s *)dev; + uint16_t mask = 0; + + if (flags & STM32_CAP_FLAG_IRQ_COUNTER) + { + mask |= ATIM_SR_UIF; + } + + if (flags & STM32_CAP_FLAG_IRQ_CH_1) + { + mask |= ATIM_SR_CC1IF; + } + + if (flags & STM32_CAP_FLAG_IRQ_CH_2) + { + mask |= ATIM_SR_CC2IF; + } + + if (flags & STM32_CAP_FLAG_IRQ_CH_3) + { + mask |= ATIM_SR_CC3IF; + } + + if (flags & STM32_CAP_FLAG_IRQ_CH_4) + { + mask |= ATIM_SR_CC4IF; + } + + if (flags & STM32_CAP_FLAG_OF_CH_1) + { + mask |= ATIM_SR_CC1OF; + } + + if (flags & STM32_CAP_FLAG_OF_CH_2) + { + mask |= ATIM_SR_CC2OF; + } + + if (flags & STM32_CAP_FLAG_OF_CH_3) + { + mask |= ATIM_SR_CC3OF; + } + + if (flags & STM32_CAP_FLAG_OF_CH_4) + { + mask |= ATIM_SR_CC4OF; + } + + stm32_putreg16(priv, STM32_BTIM_SR_OFFSET, ~mask); +} + +static stm32_cap_flags_t stm32_cap_getflags(struct stm32_cap_dev_s *dev) +{ + const struct stm32_cap_priv_s *priv = (const struct stm32_cap_priv_s *)dev; + uint16_t regval = 0; + stm32_cap_flags_t flags = 0; + + regval = stm32_getreg16(priv, STM32_BTIM_SR_OFFSET); + + if (regval & ATIM_SR_UIF) + { + flags |= STM32_CAP_FLAG_IRQ_COUNTER; + } + + if (regval & ATIM_SR_CC1IF) + { + flags |= STM32_CAP_FLAG_IRQ_CH_1; + } + + if (regval & ATIM_SR_CC2IF) + { + flags |= STM32_CAP_FLAG_IRQ_CH_2; + } + + if (regval & ATIM_SR_CC3IF) + { + flags |= STM32_CAP_FLAG_IRQ_CH_3; + } + + if (regval & ATIM_SR_CC4IF) + { + flags |= STM32_CAP_FLAG_IRQ_CH_4; + } + + if (regval & ATIM_SR_CC1OF) + { + flags |= STM32_CAP_FLAG_OF_CH_1; + } + + if (regval & ATIM_SR_CC2OF) + { + flags |= STM32_CAP_FLAG_OF_CH_2; + } + + if (regval & ATIM_SR_CC3OF) + { + flags |= STM32_CAP_FLAG_OF_CH_3; + } + + if (regval & ATIM_SR_CC4OF) + { + flags |= STM32_CAP_FLAG_OF_CH_4; + } + + return flags; +} + +/**************************************************************************** + * General Functions + ****************************************************************************/ + +static int stm32_cap_setchannel(struct stm32_cap_dev_s *dev, + uint8_t channel, + stm32_cap_ch_cfg_t cfg) +{ + const struct stm32_cap_priv_s *priv = (const struct stm32_cap_priv_s *)dev; + uint32_t gpio = 0; + uint16_t mask; + uint16_t regval; + uint16_t ccer_en_bit; + + DEBUGASSERT(dev != NULL); + + gpio = stm32_cap_gpio(priv, channel); + + if (gpio == 0) + { + return ERROR; + } + + if ((cfg & STM32_CAP_MAPPED_MASK) == 0) + { + return ERROR; /* MAPPED not selected */ + } + + /* Change to zero base index */ + + channel--; + + /* Set ccer : + * + * GTIM_CCER_CCxE Is written latter to allow writing CCxS bits. + * + */ + + switch (cfg & STM32_CAP_EDGE_MASK) + { + case STM32_CAP_EDGE_DISABLED: + ccer_en_bit = 0; + regval = 0; + break; + + case STM32_CAP_EDGE_RISING: + ccer_en_bit = GTIM_CCER_CC1E; + regval = 0; + break; + + case STM32_CAP_EDGE_FALLING: + ccer_en_bit = GTIM_CCER_CC1E; + regval = GTIM_CCER_CC1P; + break; + + case STM32_CAP_EDGE_BOTH: + ccer_en_bit = GTIM_CCER_CC1E; +#ifdef HAVE_GTIM_CCXNP + regval = GTIM_CCER_CC1P | GTIM_CCER_CC1NP; +#else + regval = GTIM_CCER_CC1P; +#endif + break; + + default: + return ERROR; + } + + /* Shift all CCER bits to corresponding channel */ +#ifdef HAVE_GTIM_CCXNP + mask = (GTIM_CCER_CC1E | GTIM_CCER_CC1P | GTIM_CCER_CC1NP); +#else + mask = (GTIM_CCER_CC1E | GTIM_CCER_CC1P); +#endif + mask <<= GTIM_CCER_CCXBASE(channel); + regval <<= GTIM_CCER_CCXBASE(channel); + ccer_en_bit <<= GTIM_CCER_CCXBASE(channel); + + stm32_modifyreg16(priv, STM32_GTIM_CCER_OFFSET, mask, regval); + + /* Set ccmr */ + + regval = cfg; + mask = (GTIM_CCMR1_IC1F_MASK | + GTIM_CCMR1_IC1PSC_MASK | + GTIM_CCMR1_CC1S_MASK); + regval &= mask; + + if (channel & 1) + { + regval <<= 8; + mask <<= 8; + } + + if (channel < 2) + { + stm32_modifyreg16(priv, STM32_GTIM_CCMR1_OFFSET, mask, regval); + } + else + { + stm32_modifyreg16(priv, STM32_GTIM_CCMR2_OFFSET, mask, regval); + } + + /* Set GPIO */ + + if ((cfg & STM32_CAP_EDGE_MASK) == STM32_CAP_EDGE_DISABLED) + { + stm32_unconfiggpio(gpio); + } + else + { + stm32_configgpio(gpio); + } + + /* Enable this channel timer */ + + stm32_modifyreg16(priv, STM32_GTIM_CCER_OFFSET, 0, ccer_en_bit); + return OK; +} + +static uint32_t stm32_cap_getcapture(struct stm32_cap_dev_s *dev, + uint8_t channel) +{ + const struct stm32_cap_priv_s *priv = (const struct stm32_cap_priv_s *)dev; + uint32_t offset; + + DEBUGASSERT(dev != NULL); + + switch (channel) + { + case STM32_CAP_CHANNEL_COUNTER: + offset = STM32_GTIM_CNT_OFFSET; + break; +#ifdef HAVE_CH1IN + case 1: + offset = STM32_GTIM_CCR1_OFFSET; + break; +#endif +#ifdef HAVE_CH2IN + case 2: + offset = STM32_GTIM_CCR2_OFFSET; + break; +#endif +#ifdef HAVE_CH3IN + case 3: + offset = STM32_GTIM_CCR3_OFFSET; + break; +#endif +#ifdef HAVE_CH4IN + case 4: + offset = STM32_GTIM_CCR4_OFFSET; + break; +#endif + default: + return ERROR; + } + + if (priv->base == STM32_TIM2_BASE || priv->base == STM32_TIM5_BASE) + { + return stm32_getreg32(priv, offset); + } + + return stm32_getreg16(priv, offset); +} + +static uint32_t stm32_cap_rstcounter(struct stm32_cap_dev_s *dev) +{ + const struct stm32_cap_priv_s *priv = (const struct stm32_cap_priv_s *)dev; + + stm32_modifyreg16(priv, STM32_BTIM_EGR_OFFSET, 0, BTIM_EGR_UG); + return OK; +} + +/**************************************************************************** + * Advanced Functions + ****************************************************************************/ + +/* TODO: Advanced functions for the STM32_ATIM */ + +/**************************************************************************** + * Device Structures, Instantiation + ****************************************************************************/ + +struct stm32_cap_ops_s stm32_cap_ops = +{ + .setsmc = &stm32_cap_setsmc, + .setclock = &stm32_cap_setclock, + .setchannel = &stm32_cap_setchannel, + .getcapture = &stm32_cap_getcapture, + .setisr = &stm32_cap_setisr, + .enableint = &stm32_cap_enableint, + .ackflags = &stm32_cap_ackflags, + .getflags = &stm32_cap_getflags, + .rstcounter = &stm32_cap_rstcounter, +}; + +#ifdef CONFIG_STM32_TIM1_CAP +const struct stm32_cap_priv_s stm32_tim1_priv = +{ + .ops = &stm32_cap_ops, + .base = STM32_TIM1_BASE, + .irq = STM32_IRQ_TIM1CC, +#ifdef USE_ADVENCED_TIM + .irq_of = STM32_IRQ_TIM1UP, +#endif +}; +#endif + +#ifdef CONFIG_STM32_TIM2_CAP +const struct stm32_cap_priv_s stm32_tim2_priv = +{ + .ops = &stm32_cap_ops, + .base = STM32_TIM2_BASE, + .irq = STM32_IRQ_TIM2, +#ifdef USE_ADVENCED_TIM + .irq_of = 0, +#endif +}; +#endif + +#ifdef CONFIG_STM32_TIM3_CAP +const struct stm32_cap_priv_s stm32_tim3_priv = +{ + .ops = &stm32_cap_ops, + .base = STM32_TIM3_BASE, + .irq = STM32_IRQ_TIM3, +#ifdef USE_ADVENCED_TIM + .irq_of = 0, +#endif +}; +#endif + +#ifdef CONFIG_STM32_TIM4_CAP +const struct stm32_cap_priv_s stm32_tim4_priv = +{ + .ops = &stm32_cap_ops, + .base = STM32_TIM4_BASE, + .irq = STM32_IRQ_TIM4, +#ifdef USE_ADVENCED_TIM + .irq_of = 0, +#endif +}; +#endif + +#ifdef CONFIG_STM32_TIM5_CAP +const struct stm32_cap_priv_s stm32_tim5_priv = +{ + .ops = &stm32_cap_ops, + .base = STM32_TIM5_BASE, + .irq = STM32_IRQ_TIM5, +#ifdef USE_ADVENCED_TIM + .irq_of = 0, +#endif +}; +#endif + +/* TIM6 and TIM7 cannot be used in capture */ + +#ifdef CONFIG_STM32_TIM8_CAP +const struct stm32_cap_priv_s stm32_tim8_priv = +{ + .ops = &stm32_cap_ops, + .base = STM32_TIM8_BASE, + .irq = STM32_IRQ_TIM8CC, +#ifdef USE_ADVENCED_TIM + .irq_of = STM32_IRQ_TIM8UP, +#endif +}; +#endif + +#ifdef CONFIG_STM32_TIM9_CAP +const struct stm32_cap_priv_s stm32_tim9_priv = +{ + .ops = &stm32_cap_ops, + .base = STM32_TIM9_BASE, + .irq = STM32_IRQ_TIM9, +#ifdef USE_ADVENCED_TIM + .irq_of = 0, +#endif +}; +#endif + +#ifdef CONFIG_STM32_TIM10_CAP +const struct stm32_cap_priv_s stm32_tim10_priv = +{ + .ops = &stm32_cap_ops, + .base = STM32_TIM10_BASE, + .irq = STM32_IRQ_TIM10, +#ifdef USE_ADVENCED_TIM + .irq_of = 0, +#endif +}; +#endif + +#ifdef CONFIG_STM32_TIM11_CAP +const struct stm32_cap_priv_s stm32_tim11_priv = +{ + .ops = &stm32_cap_ops, + .base = STM32_TIM11_BASE, + .irq = STM32_IRQ_TIM11, +#ifdef USE_ADVENCED_TIM + .irq_of = 0, +#endif +}; +#endif + +#ifdef CONFIG_STM32_TIM12_CAP +const struct stm32_cap_priv_s stm32_tim12_priv = +{ + .ops = &stm32_cap_ops, + .base = STM32_TIM12_BASE, + .irq = STM32_IRQ_TIM12, +#ifdef USE_ADVENCED_TIM + .irq_of = 0, +#endif +}; +#endif + +#ifdef CONFIG_STM32_TIM13_CAP +const struct stm32_cap_priv_s stm32_tim13_priv = +{ + .ops = &stm32_cap_ops, + .base = STM32_TIM13_BASE, + .irq = STM32_IRQ_TIM13, +#ifdef USE_ADVENCED_TIM + .irq_of = 0, +#endif +}; +#endif + +#ifdef CONFIG_STM32_TIM14_CAP +const struct stm32_cap_priv_s stm32_tim14_priv = +{ + .ops = &stm32_cap_ops, + .base = STM32_TIM14_BASE, + .irq = STM32_IRQ_TIM14, +#ifdef USE_ADVENCED_TIM + .irq_of = 0, +#endif +}; +#endif + +static inline const struct stm32_cap_priv_s * stm32_cap_get_priv(int timer) +{ + switch (timer) + { +#ifdef CONFIG_STM32_TIM1_CAP + case 1: + return &stm32_tim1_priv; +#endif +#ifdef CONFIG_STM32_TIM2_CAP + case 2: + return &stm32_tim2_priv; +#endif +#ifdef CONFIG_STM32_TIM3_CAP + case 3: + return &stm32_tim3_priv; +#endif +#ifdef CONFIG_STM32_TIM4_CAP + case 4: + return &stm32_tim4_priv; +#endif +#ifdef CONFIG_STM32_TIM5_CAP + case 5: + return &stm32_tim5_priv; +#endif + + /* TIM6 and TIM7 cannot be used in capture */ + +#ifdef CONFIG_STM32_TIM8_CAP + case 8: + return &stm32_tim8_priv; +#endif +#ifdef CONFIG_STM32_TIM9_CAP + case 9: + return &stm32_tim9_priv; +#endif +#ifdef CONFIG_STM32_TIM10_CAP + case 10: + return &stm32_tim10_priv; +#endif +#ifdef CONFIG_STM32_TIM11_CAP + case 11: + return &stm32_tim11_priv; +#endif +#ifdef CONFIG_STM32_TIM12_CAP + case 12: + return &stm32_tim12_priv; +#endif +#ifdef CONFIG_STM32_TIM13_CAP + case 13: + return &stm32_tim13_priv; +#endif +#ifdef CONFIG_STM32_TIM14_CAP + case 14: + return &stm32_tim14_priv; +#endif + } + + return NULL; +} + +/**************************************************************************** + * Public Function - Initialization + ****************************************************************************/ + +struct stm32_cap_dev_s *stm32_cap_init(int timer) +{ + const struct stm32_cap_priv_s *priv = stm32_cap_get_priv(timer); + uint32_t gpio; + + if (priv) + { + stm32_cap_set_rcc(priv, true); + + gpio = stm32_cap_gpio(priv, STM32_CAP_CHANNEL_COUNTER); + if (gpio) + { + stm32_configgpio(gpio); + } + + /* Disable timer while is not configured */ + + stm32_modifyreg16(priv, STM32_BTIM_CR1_OFFSET, ATIM_CR1_CEN, 0); + } + + return (struct stm32_cap_dev_s *)priv; +} + +int stm32_cap_deinit(struct stm32_cap_dev_s * dev) +{ + const struct stm32_cap_priv_s *priv = (struct stm32_cap_priv_s *)dev; + uint32_t gpio; + + DEBUGASSERT(dev != NULL); + + /* Disable timer while is not configured */ + + stm32_modifyreg16(priv, STM32_BTIM_CR1_OFFSET, ATIM_CR1_CEN, 0); + + gpio = stm32_cap_gpio(priv, STM32_CAP_CHANNEL_COUNTER); + if (gpio) + { + stm32_unconfiggpio(gpio); + } + + stm32_cap_set_rcc(priv, false); + return OK; +} + +#endif /* defined(CONFIG_STM32_TIM1 || ... || TIM14) */ diff --git a/arch/arm/src/common/stm32/stm32_capture_m3m4_v1_lowerhalf.c b/arch/arm/src/common/stm32/stm32_capture_m3m4_v1_lowerhalf.c new file mode 100644 index 0000000000000..ea4e0b174fbbd --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_capture_m3m4_v1_lowerhalf.c @@ -0,0 +1,577 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_capture_m3m4_v1_lowerhalf.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include +#include +#include + +#include +#include + +#include + +#include "stm32_capture.h" + +#if defined(CONFIG_STM32_CAP) + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define STM32_TIM1_RES 16 +#if defined(CONFIG_STM32_STM32L15XX) || defined(CONFIG_STM32_STM32F10XX) +# define STM32_TIM2_RES 16 +#else +# define STM32_TIM2_RES 32 +#endif +#define STM32_TIM3_RES 16 +#define STM32_TIM4_RES 16 +#if defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F30XX) +# define STM32_TIM5_RES 16 +#else +# define STM32_TIM5_RES 32 +#endif +#define STM32_TIM8_RES 16 +#define STM32_TIM9_RES 16 +#define STM32_TIM10_RES 16 +#define STM32_TIM11_RES 16 +#define STM32_TIM12_RES 16 +#define STM32_TIM13_RES 16 +#define STM32_TIM14_RES 16 + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/* This structure provides the private representation of the "lower-half" + * driver state structure. This structure must be cast-compatible with the + * cap_lowerhalf_s structure. + */ + +struct stm32_lowerhalf_s +{ + const struct cap_ops_s *ops; /* Lower half operations */ + struct stm32_cap_dev_s *cap; /* stm32 capture driver */ + bool started; /* True: Timer has been started */ + const uint8_t resolution; /* Number of bits in the timer */ + uint8_t channel; /* pwm input channel */ + uint32_t clock; /* Timer clock frequency */ + uint8_t duty; /* Result pwm frequency */ + uint32_t freq; /* Result pwm frequency */ +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +static int stm32_cap_handler(int irq, void * context, void * arg); + +/* "Lower half" driver methods **********************************************/ + +static int stm32_start(struct cap_lowerhalf_s *lower); +static int stm32_stop(struct cap_lowerhalf_s *lower); +static int stm32_getduty(struct cap_lowerhalf_s *lower, uint8_t *duty); +static int stm32_getfreq(struct cap_lowerhalf_s *lower, uint32_t *freq); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* "Lower half" driver methods */ + +static const struct cap_ops_s g_cap_ops = +{ + .start = stm32_start, + .stop = stm32_stop, + .getduty = stm32_getduty, + .getfreq = stm32_getfreq, +}; + +#ifdef CONFIG_STM32_TIM1_CAP +static struct stm32_lowerhalf_s g_cap1_lowerhalf = +{ + .ops = &g_cap_ops, + .resolution = STM32_TIM1_RES, + .channel = CONFIG_STM32_TIM1_CHANNEL, + .clock = CONFIG_STM32_TIM1_CLOCK, +}; +#endif + +#ifdef CONFIG_STM32_TIM2_CAP +static struct stm32_lowerhalf_s g_cap2_lowerhalf = +{ + .ops = &g_cap_ops, + .resolution = STM32_TIM2_RES, + .channel = CONFIG_STM32_TIM2_CHANNEL, + .clock = CONFIG_STM32_TIM2_CLOCK, +}; +#endif + +#ifdef CONFIG_STM32_TIM3_CAP +static struct stm32_lowerhalf_s g_cap3_lowerhalf = +{ + .ops = &g_cap_ops, + .resolution = STM32_TIM3_RES, + .channel = CONFIG_STM32_TIM3_CHANNEL, + .clock = CONFIG_STM32_TIM3_CLOCK, +}; +#endif + +#ifdef CONFIG_STM32_TIM4_CAP +static struct stm32_lowerhalf_s g_cap4_lowerhalf = +{ + .ops = &g_cap_ops, + .resolution = STM32_TIM4_RES, + .channel = CONFIG_STM32_TIM4_CHANNEL, + .clock = CONFIG_STM32_TIM4_CLOCK, +}; +#endif + +#ifdef CONFIG_STM32_TIM5_CAP +static struct stm32_lowerhalf_s g_cap5_lowerhalf = +{ + .ops = &g_cap_ops, + .resolution = STM32_TIM5_RES, + .channel = CONFIG_STM32_TIM5_CHANNEL, + .clock = CONFIG_STM32_TIM5_CLOCK, +}; +#endif + +#ifdef CONFIG_STM32_TIM8_CAP +static struct stm32_lowerhalf_s g_cap8_lowerhalf = +{ + .ops = &g_cap_ops, + .resolution = STM32_TIM8_RES, + .channel = CONFIG_STM32_TIM8_CHANNEL, + .clock = CONFIG_STM32_TIM8_CLOCK, +}; +#endif + +#ifdef CONFIG_STM32_TIM9_CAP +static struct stm32_lowerhalf_s g_cap9_lowerhalf = +{ + .ops = &g_cap_ops, + .resolution = STM32_TIM9_RES, + .channel = CONFIG_STM32_TIM9_CHANNEL, + .clock = CONFIG_STM32_TIM9_CLOCK, +}; +#endif + +#ifdef CONFIG_STM32_TIM10_CAP +static struct stm32_lowerhalf_s g_cap10_lowerhalf = +{ + .ops = &g_cap_ops, + .resolution = STM32_TIM10_RES, + .channel = CONFIG_STM32_TIM10_CHANNEL, + .clock = CONFIG_STM32_TIM10_CLOCK, +}; +#endif + +#ifdef CONFIG_STM32_TIM11_CAP +static struct stm32_lowerhalf_s g_cap11_lowerhalf = +{ + .ops = &g_cap_ops, + .resolution = STM32_TIM11_RES, + .channel = CONFIG_STM32_TIM11_CHANNEL, + .clock = CONFIG_STM32_TIM11_CLOCK, +}; +#endif + +#ifdef CONFIG_STM32_TIM12_CAP +static struct stm32_lowerhalf_s g_cap12_lowerhalf = +{ + .ops = &g_cap_ops, + .resolution = STM32_TIM12_RES, + .channel = CONFIG_STM32_TIM12_CHANNEL, + .clock = CONFIG_STM32_TIM12_CLOCK, +}; +#endif + +#ifdef CONFIG_STM32_TIM13_CAP +static struct stm32_lowerhalf_s g_cap13_lowerhalf = +{ + .ops = &g_cap_ops, + .resolution = STM32_TIM13_RES, + .channel = CONFIG_STM32_TIM13_CHANNEL, + .clock = CONFIG_STM32_TIM13_CLOCK, +}; +#endif + +#ifdef CONFIG_STM32_TIM14_CAP +static struct stm32_lowerhalf_s g_cap14_lowerhalf = +{ + .ops = &g_cap_ops, + .resolution = STM32_TIM14_RES, + .channel = CONFIG_STM32_TIM14_CHANNEL, + .clock = CONFIG_STM32_TIM14_CLOCK, +}; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_cap_handler + * + * Description: + * timer interrupt handler + * + * Input Parameters: + * + * Returned Value: + * + ****************************************************************************/ + +static int stm32_cap_handler(int irq, void * context, void * arg) +{ + struct stm32_lowerhalf_s *lower = (struct stm32_lowerhalf_s *) arg; + uint8_t ch = 0x3 & lower->channel; + int period = 0; + int flags = 0; + + flags = (int)STM32_CAP_GETFLAGS(lower->cap) ; + + STM32_CAP_ACKFLAGS(lower->cap, flags); + + period = STM32_CAP_GETCAPTURE(lower->cap, ch); + + if (period != 0) + { + lower->duty = (100 * STM32_CAP_GETCAPTURE(lower->cap, 0x3 & (~ch))) / + period; + } + else + { + lower->duty = 0; + } + + lower->freq = lower->clock / period; + + return OK; +} + +/**************************************************************************** + * Name: stm32_start + * + * Description: + * Start the timer, resetting the time to the current timeout, + * + * Input Parameters: + * lower - A pointer the publicly visible representation of the + * "lower-half" driver state structure. + * + * Returned Value: + * Zero on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int stm32_start(struct cap_lowerhalf_s *lower) +{ + struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; + int flags = 0; + uint32_t maxtimeout = (1 << priv->resolution) - 1; + + if (priv->started) + { + /* Return EBUSY to indicate that the timer was already running */ + + return -EBUSY; + } + + switch (priv->channel) + { + case 1: + STM32_CAP_SETSMC(priv->cap, STM32_CAP_SMS_RST | + STM32_CAP_TS_TI1FP1 | + STM32_CAP_MSM_MASK); + + STM32_CAP_SETCLOCK(priv->cap, priv->clock, maxtimeout); + + STM32_CAP_SETCHANNEL(priv->cap, 1, + STM32_CAP_EDGE_RISING | + STM32_CAP_MAPPED_TI1); + STM32_CAP_SETCHANNEL(priv->cap, 2, + STM32_CAP_EDGE_FALLING | + STM32_CAP_MAPPED_TI2); + + flags = (int)STM32_CAP_GETFLAGS(priv->cap); + STM32_CAP_ACKFLAGS(priv->cap, flags); + + STM32_CAP_SETISR(priv->cap, stm32_cap_handler, priv); + STM32_CAP_ENABLEINT(priv->cap, STM32_CAP_FLAG_IRQ_CH_1, true); + + priv->started = true; + break; + + case 2: + STM32_CAP_SETSMC(priv->cap, STM32_CAP_SMS_RST | + STM32_CAP_TS_TI2FP2 | + STM32_CAP_MSM_MASK); + + STM32_CAP_SETCLOCK(priv->cap, priv->clock, maxtimeout); + + STM32_CAP_SETCHANNEL(priv->cap, 2, + STM32_CAP_EDGE_RISING | + STM32_CAP_MAPPED_TI1); + STM32_CAP_SETCHANNEL(priv->cap, 1, + STM32_CAP_EDGE_FALLING | + STM32_CAP_MAPPED_TI2); + + flags = (int)STM32_CAP_GETFLAGS(priv->cap); + STM32_CAP_ACKFLAGS(priv->cap, flags); + + STM32_CAP_SETISR(priv->cap, stm32_cap_handler, priv); + STM32_CAP_ENABLEINT(priv->cap, STM32_CAP_FLAG_IRQ_CH_2, true); + + priv->started = true; + break; + + default: + return ERROR; + } + + return OK; +} + +/**************************************************************************** + * Name: stm32_stop + * + * Description: + * Stop the capture + * + * Input Parameters: + * lower - A pointer the publicly visible representation of the + * "lower-half" driver state structure. + * + * Returned Value: + * Zero on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int stm32_stop(struct cap_lowerhalf_s *lower) +{ + struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; + + if (priv->started) + { + STM32_CAP_SETCHANNEL(priv->cap, STM32_CAP_FLAG_IRQ_COUNTER, + STM32_CAP_EDGE_DISABLED); + switch (priv->channel) + { + case 1: + STM32_CAP_ENABLEINT(priv->cap, STM32_CAP_FLAG_IRQ_CH_1, false); + break; + + case 2: + STM32_CAP_ENABLEINT(priv->cap, STM32_CAP_FLAG_IRQ_CH_2, false); + break; + + default: + return ERROR; + } + + STM32_CAP_SETISR(priv->cap, NULL, NULL); + priv->started = false; + return OK; + } + + /* Return ENODEV to indicate that the timer was not running */ + + return -ENODEV; +} + +/**************************************************************************** + * Name: stm32_getduty + * + * Description: + * get result duty + * + * Input Parameters: + * lower - A pointer the publicly visible representation of the + * "lower-half" driver state structure. + * duty - DutyCycle * 100. + * + * Returned Value: + * Zero on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int stm32_getduty(struct cap_lowerhalf_s *lower, uint8_t *duty) +{ + struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; + + irqstate_t flags = enter_critical_section(); + + *duty = priv->duty; + + leave_critical_section(flags); + + return OK; +} + +/**************************************************************************** + * Name: stm32_getfreq + * + * Description: + * get result freq + * + * Input Parameters: + * lower - A pointer the publicly visible representation of the + * "lower-half" driver state structure. + * freq - Frequency in Hz. + * + * Returned Value: + * Zero on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int stm32_getfreq(struct cap_lowerhalf_s *lower, uint32_t *freq) +{ + struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; + + irqstate_t flags = enter_critical_section(); + + *freq = priv->freq; + + leave_critical_section(flags); + + return OK; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_cap_initialize + * + * Description: + * Initialize one timer for use with the upper_level capture driver. + * + * Input Parameters: + * timer - A number identifying the timer use. The number of valid timer + * IDs varies with the STM32 MCU and MCU family but is somewhere in + * the range of {1,..,5 8,...,14}. + * + * Returned Value: + * On success, a pointer to the STM32 lower half capture driver returned. + * NULL is returned on any failure. + * + ****************************************************************************/ + +struct cap_lowerhalf_s *stm32_cap_initialize(int timer) +{ + struct stm32_lowerhalf_s *lower = NULL; + + switch (timer) + { +#ifdef CONFIG_STM32_TIM1_CAP + case 1: + lower = &g_cap1_lowerhalf; + break; +#endif +#ifdef CONFIG_STM32_TIM2_CAP + case 2: + lower = &g_cap2_lowerhalf; + break; +#endif +#ifdef CONFIG_STM32_TIM3_CAP + case 3: + lower = &g_cap3_lowerhalf; + break; +#endif +#ifdef CONFIG_STM32_TIM4_CAP + case 4: + lower = &g_cap4_lowerhalf; + break; +#endif +#ifdef CONFIG_STM32_TIM5_CAP + case 5: + lower = &g_cap5_lowerhalf; + break; +#endif +#ifdef CONFIG_STM32_TIM6_CAP + case 6: + lower = &g_cap6_lowerhalf; + break; +#endif +#ifdef CONFIG_STM32_TIM9_CAP + case 9: + lower = &g_cap9_lowerhalf; + break; +#endif +#ifdef CONFIG_STM32_TIM10_CAP + case 10: + lower = &g_cap10_lowerhalf; + break; +#endif +#ifdef CONFIG_STM32_TIM11_CAP + case 11: + lower = &g_cap11_lowerhalf; + break; +#endif +#ifdef CONFIG_STM32_TIM12_CAP + case 12: + lower = &g_cap12_lowerhalf; + break; +#endif +#ifdef CONFIG_STM32_TIM13_CAP + case 13: + lower = &g_cap13_lowerhalf; + break; +#endif +#ifdef CONFIG_STM32_TIM14_CAP + case 14: + lower = &g_cap14_lowerhalf; + break; +#endif + default: + { + lower = NULL; + goto errout; + } + } + + /* Initialize the elements of lower half state structure */ + + lower->started = false; + lower->cap = stm32_cap_init(timer); + + if (lower->cap == NULL) + { + lower = NULL; + } + +errout: + return (struct cap_lowerhalf_s *)lower; +} + +#endif /* CONFIG_STM32_CAP */ diff --git a/arch/arm/src/common/stm32/stm32_ccm.h b/arch/arm/src/common/stm32/stm32_ccm.h new file mode 100644 index 0000000000000..432d3bf549269 --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_ccm.h @@ -0,0 +1,38 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_ccm.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_COMPAT_STM32CCM_H +#define __ARCH_ARM_SRC_COMMON_COMPAT_STM32CCM_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#if defined(CONFIG_STM32_HAVE_IP_CCM_M3M4_V1) +# include "stm32_ccm_m3m4_v1.h" +#else +# error "Unsupported STM32 stm32_ccm" +#endif + +#endif /* __ARCH_ARM_SRC_COMMON_COMPAT_STM32CCM_H */ diff --git a/arch/arm/src/common/stm32/stm32_ccm_m3m4_v1.c b/arch/arm/src/common/stm32/stm32_ccm_m3m4_v1.c new file mode 100644 index 0000000000000..fb4507e1d082c --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_ccm_m3m4_v1.c @@ -0,0 +1,43 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_ccm_m3m4_v1.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "stm32_ccm_m3m4_v1.h" + +#ifdef HAVE_CCM_HEAP + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +struct mm_heap_s *g_ccm_heap; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +#endif /* HAVE_CCM_HEAP */ diff --git a/arch/arm/src/common/stm32/stm32_ccm_m3m4_v1.h b/arch/arm/src/common/stm32/stm32_ccm_m3m4_v1.h new file mode 100644 index 0000000000000..705a58c08045e --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_ccm_m3m4_v1.h @@ -0,0 +1,125 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_ccm_m3m4_v1.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_CCM_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_CCM_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* Assume that we can support the CCM heap */ + +#define HAVE_CCM_HEAP 1 + +/* Only the STM32 F2, F3, and F4 have CCM memory */ + +#if defined(CONFIG_STM32_STM32F30XX) +# define CCM_START 0x10000000 +# define CCM_END 0x10002000 +#elif defined(CONFIG_STM32_HAVE_IP_CCM_M3M4_V1) || \ + defined(CONFIG_STM32_STM32F33XX) +# define CCM_START 0x10000000 +# define CCM_END 0x10010000 +#else +# undef HAVE_CCM_HEAP +#endif + +/* In order to use the CCM heap, it had to have been excluded from the main + * heap. + */ + +#ifndef CONFIG_STM32_CCMEXCLUDE +# undef HAVE_CCM_HEAP +#endif + +/* Can we support the CCM heap? */ + +#ifdef HAVE_CCM_HEAP + +/* ccm_initialize must be called early in initialization in order to + * initialize the CCM heap. + */ + +#define ccm_initialize() \ + g_ccm_heap = mm_initialize("ccm", (void *)CCM_START, CCM_END-CCM_START) + +/* The ccm_addregion interface could be used if, for example, you want to + * add some other memory region to the CCM heap. I don't really know why + * you might want to do that, but the functionality is essentially free. + */ + +#define ccm_addregion(b,s) mm_addregion(g_ccm_heap, b, s); + +/* Then, once g_ccm_heap has been setup by ccm_initialize(), these memory + * allocators can be used just like the standard memory allocators. + */ + +#define ccm_malloc(s) mm_malloc(g_ccm_heap, s) +#define ccm_zalloc(s) mm_zalloc(g_ccm_heap, s) +#define ccm_calloc(n,s) mm_calloc(g_ccm_heap, n,s) +#define ccm_free(p) mm_free(g_ccm_heap, p) +#define ccm_realloc(p,s) mm_realloc(g_ccm_heap, p, s) +#define ccm_memalign(a,s) mm_memalign(g_ccm_heap, a, s) + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +EXTERN struct mm_heap_s *g_ccm_heap; + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#undef EXTERN +#ifdef __cplusplus +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* HAVE_CCM_HEAP */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_CCM_H */ diff --git a/arch/arm/src/common/stm32/stm32_comp.h b/arch/arm/src/common/stm32/stm32_comp.h new file mode 100644 index 0000000000000..8178f55e6d486 --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_comp.h @@ -0,0 +1,269 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_comp.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_COMP_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_COMP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#if defined(CONFIG_STM32_HAVE_IP_COMP_M3M4_V1) || \ + defined(CONFIG_STM32_HAVE_IP_COMP_M3M4_V2) + +#include "chip.h" + +#include "hardware/stm32_comp.h" + +/**************************************************************************** + * Pre-processor definitions + ****************************************************************************/ + +#ifdef CONFIG_STM32_COMP +# if defined(CONFIG_STM32_HAVE_IP_COMP_M3M4_V1) +# define COMP_BLANKING_DEFAULT COMP_BLANKING_DIS +# define COMP_POL_DEFAULT COMP_POL_NONINVERT +# define COMP_INM_DEFAULT COMP_INMSEL_1P4VREF +# define COMP_OUTSEL_DEFAULT COMP_OUTSEL_NOSEL +# define COMP_LOCK_DEFAULT COMP_LOCK_RW + +# ifndef CONFIG_STM32_STM32F33XX +# define COMP_MODE_DEFAULT +# define COMP_HYST_DEFAULT +# define COMP_WINMODE_DEFAULT +# endif +# endif +#endif + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +#ifdef CONFIG_STM32_COMP +# if defined(CONFIG_STM32_HAVE_IP_COMP_M3M4_V1) + +/* Blanking source */ + +enum stm32_comp_blanking_e +{ + COMP_BLANKING_DIS, +# if defined(CONFIG_STM32_STM32F33XX) + COMP_BLANKING_T1OC5, + COMP_BLANKING_T3OC4, + COMP_BLANKING_T2OC3, + COMP_BLANKING_T3OC3, + COMP_BLANKING_T15OC1, + COMP_BLANKING_T2OC4, + COMP_BLANKING_T15OC2, +# endif +}; + +/* Output polarisation */ + +enum stm32_comp_pol_e +{ + COMP_POL_NONINVERT, + COMP_POL_INVERTED +}; + +/* Inverting input */ + +enum stm32_comp_inm_e +{ + COMP_INMSEL_1P4VREF, + COMP_INMSEL_1P2VREF, + COMP_INMSEL_3P4VREF, + COMP_INMSEL_VREF, + COMP_INMSEL_DAC1CH1, + COMP_INMSEL_DAC1CH2, + COMP_INMSEL_PIN +}; + +/* Output selection */ + +enum stm32_comp_outsel_e +{ + COMP_OUTSEL_NOSEL, +# if defined(CONFIG_STM32_STM32F33XX) + COMP_OUTSEL_BRKACTH, + COMP_OUTSEL_BRK2, + COMP_OUTSEL_T1OCC, /* COMP2 only */ + COMP_OUTSEL_T3CAP3, /* COMP4 only */ + COMP_OUTSEL_T2CAP2, /* COMP6 only */ + COMP_OUTSEL_T1CAP1, /* COMP2 only */ + COMP_OUTSEL_T2CAP4, /* COMP2 only */ + COMP_OUTSEL_T15CAP2, /* COMP4 only */ + COMP_OUTSEL_T2OCC, /* COMP6 only */ + COMP_OUTSEL_T16OCC, /* COMP2 only */ + COMP_OUTSEL_T3CAP1, /* COMP2 only */ + COMP_OUTSEL_T15OCC, /* COMP4 only */ + COMP_OUTSEL_T16CAP1, /* COMP6 only */ + COMP_OUTSEL_T3OCC, /* COMP2 and COMP4 only */ +# endif +}; + +/* CSR register lock state */ + +enum stm32_comp_lock_e +{ + COMP_LOCK_RW, + COMP_LOCK_RO +}; + +# ifndef CONFIG_STM32_STM32F33XX + +/* Hysteresis */ + +enum stm32_comp_hyst_e +{ + COMP_HYST_DIS, + COMP_HYST_LOW, + COMP_HYST_MEDIUM, + COMP_HYST_HIGH +}; + +/* Power/Speed Modes */ + +enum stm32_comp_mode_e +{ + COMP_MODE_HIGHSPEED, + COMP_MODE_MEDIUMSPEED, + COMP_MODE_LOWPOWER, + COMP_MODE_ULTRALOWPOWER +}; + +/* Window mode */ + +enum stm32_comp_winmode_e +{ + COMP_WINMODE_DIS, + COMP_WINMODE_EN +}; + +# endif +# elif defined(CONFIG_STM32_HAVE_IP_COMP_M3M4_V2) + +/* Inverting input. See Table 196 in RM0440 */ + +enum stm32_comp_inm_e +{ + COMP_INM_1_4_VREF, + COMP_INM_1_2_VREF, + COMP_INM_3_4_VREF, + COMP_INM_VREF, + COMP_INM_DAC_1, + COMP_INM_DAC_2, + COMP_INM_PIN_1, + COMP_INM_PIN_2, +}; + +/* Non-inverting input. See Table 195 in RM0440 */ + +enum stm32_comp_inp_e +{ + COMP_INP_PIN_1, + COMP_INP_PIN_2, +}; + +/* Output polarity */ + +enum stm32_comp_pol_e +{ + COMP_POL_NONINVERT, + COMP_POL_INVERTED +}; + +/* Hysteresis */ + +enum stm32_comp_hyst_e +{ + COMP_HYST_DIS, + COMP_HYST_10MV, + COMP_HYST_20MV, + COMP_HYST_30MV, + COMP_HYST_40MV, + COMP_HYST_50MV, + COMP_HYST_60MV, + COMP_HYST_70MV, +}; + +/* Blanking source */ + +enum stm32_comp_blanking_e +{ + COMP_BLANKING_DIS, + COMP_BLANKING_TIMX_OCY_1, + COMP_BLANKING_TIMX_OCY_2, + COMP_BLANKING_TIMX_OCY_3, + COMP_BLANKING_TIMX_OCY_4, + COMP_BLANKING_TIMX_OCY_5, + COMP_BLANKING_TIMX_OCY_6, + COMP_BLANKING_TIMX_OCY_7, +}; + +# endif +#endif /* CONFIG_STM32_COMP */ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#ifndef __ASSEMBLY__ +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Name: stm32_compinitialize + * + * Description: + * Initialize the COMP. + * + * Input Parameters: + * intf - The COMP interface number. + * + * Returned Value: + * Valid COMP device structure reference on success; a NULL on failure. + * + * Assumptions: + * 1. Clock to the COMP block has enabled, + * 2. Board-specific logic has already configured + * + ****************************************************************************/ + +struct comp_dev_s *stm32_compinitialize(int intf); + +#undef EXTERN +#ifdef __cplusplus +} +#endif +#endif /* __ASSEMBLY__ */ + +#endif /* CONFIG_STM32_HAVE_IP_COMP_M3M4_V1 || CONFIG_STM32_HAVE_IP_COMP_M3M4_V2 */ + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_COMP_H */ diff --git a/arch/arm/src/common/stm32/stm32_comp_m3m4_v1.c b/arch/arm/src/common/stm32/stm32_comp_m3m4_v1.c new file mode 100644 index 0000000000000..5af2ab5217701 --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_comp_m3m4_v1.c @@ -0,0 +1,1082 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_comp_m3m4_v1.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include +#include + +#include + +#include "arm_internal.h" +#include "chip.h" +#include "stm32_comp.h" +#include "stm32_gpio.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Some COMP peripheral must be enabled */ + +/* Up to 7 comparators in STM32F3 Series */ + +#if defined(CONFIG_STM32_COMP1) || defined(CONFIG_STM32_COMP2) || \ + defined(CONFIG_STM32_COMP3) || defined(CONFIG_STM32_COMP4) || \ + defined(CONFIG_STM32_COMP5) || defined(CONFIG_STM32_COMP6) || \ + defined(CONFIG_STM32_COMP7) + +#ifndef CONFIG_STM32_SYSCFG +# error "SYSCFG clock enable must be set" +#endif + +/* @TODO: support for STM32F30XX and STM32F37XX comparators */ + +#if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) || \ + defined(CONFIG_STM32_STM32F37XX) + +/* Currently only STM32F33XX supported */ + +#if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX) +# error "Not supported yet" +#endif + +#if defined(CONFIG_STM32_STM32F33XX) +# if defined(CONFIG_STM32_COMP1) || defined(CONFIG_STM32_COMP3) || \ + defined(CONFIG_STM32_COMP5) || defined(CONFIG_STM32_COMP7) +# error "STM32F33 supports only COMP2, COMP4 and COMP6" +# endif +#endif + +/* COMP2 default configuration **********************************************/ + +#ifdef CONFIG_STM32_COMP2 +# ifndef COMP2_BLANLKING +# define COMP2_BLANKING COMP_BLANKING_DEFAULT +# endif +# ifndef COMP2_POL +# define COMP2_POL COMP_BLANKING_DEFAULT +# endif +# ifndef COMP2_INM +# define COMP2_INM COMP_INM_DEFAULT +# endif +# ifndef COMP2_OUTSEL +# define COMP2_OUTSEL COMP_OUTSEL_DEFAULT +# endif +# ifndef COMP2_LOCK +# define COMP2_LOCK COMP_LOCK_DEFAULT +# endif +# ifndef GPIO_COMP2_INM +# warning "GPIO_COMP2_INM not selected. Set default value to GPIO_COMP2_INM1" +# define GPIO_COMP2_INM GPIO_COMP2_INM_1 +# endif +#endif + +/* COMP4 default configuration **********************************************/ + +#ifdef CONFIG_STM32_COMP4 +# ifndef COMP4_BLANLKING +# define COMP4_BLANKING COMP_BLANKING_DEFAULT +# endif +# ifndef COMP4_POL +# define COMP4_POL COMP_BLANKING_DEFAULT +# endif +# ifndef COMP4_INM +# define COMP4_INM COMP_INM_DEFAULT +# endif +# ifndef COMP4_OUTSEL +# define COMP4_OUTSEL COMP_OUTSEL_DEFAULT +# endif +# ifndef COMP4_LOCK +# define COMP4_LOCK COMP_LOCK_DEFAULT +# endif +# ifndef GPIO_COMP4_INM +# warning "GPIO_COMP4_INM not selected. Set default value to GPIO_COMP4_INM1" +# define GPIO_COMP4_INM GPIO_COMP4_INM_1 +# endif +#endif + +/* COMP6 default configuration **********************************************/ + +#ifdef CONFIG_STM32_COMP6 +# ifndef COMP6_BLANLKING +# define COMP6_BLANKING COMP_BLANKING_DEFAULT +# endif +# ifndef COMP6_POL +# define COMP6_POL COMP_BLANKING_DEFAULT +# endif +# ifndef COMP6_INM +# define COMP6_INM COMP_INM_DEFAULT +# endif +# ifndef COMP6_OUTSEL +# define COMP6_OUTSEL COMP_OUTSEL_DEFAULT +# endif +# ifndef COMP6_LOCK +# define COMP6_LOCK COMP_LOCK_DEFAULT +# endif +# ifndef GPIO_COMP6_INM +# warning "GPIO_COMP6_INM not selected. Set default value to GPIO_COMP6_INM1" +# define GPIO_COMP6_INM GPIO_COMP6_INM_1 +# endif +#endif + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/* This structure describes the configuration of one COMP device */ + +struct stm32_comp_s +{ + uint8_t blanking; /* Blanking source */ + uint8_t pol; /* Output polarity */ + uint8_t inm; /* Inverting input selection */ + uint8_t out; /* Comparator output */ + uint8_t lock; /* Comparator Lock */ + uint32_t csr; /* Control and status register */ +#ifndef CONFIG_STM32_STM32F33XX + uint8_t mode; /* Comparator mode */ + uint8_t hyst; /* Comparator hysteresis */ + /* @TODO: Window mode + INP selection */ +#endif +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/* COMP Register access */ + +static inline void comp_modify_csr(struct stm32_comp_s *priv, + uint32_t clearbits, uint32_t setbits); +static inline uint32_t comp_getreg_csr(struct stm32_comp_s *priv); +static inline void comp_putreg_csr(struct stm32_comp_s *priv, + uint32_t value); +static bool stm32_complock_get(struct stm32_comp_s *priv); +static int stm32_complock(struct stm32_comp_s *priv, bool lock); + +/* COMP Driver Methods */ + +static void comp_shutdown(struct comp_dev_s *dev); +static int comp_setup(struct comp_dev_s *dev); +static int comp_read(struct comp_dev_s *dev); +static int comp_ioctl(struct comp_dev_s *dev, int cmd, + unsigned long arg); + +/* Initialization */ + +static int stm32_compconfig(struct stm32_comp_s *priv); +static int stm32_compenable(struct stm32_comp_s *priv, bool enable); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static const struct comp_ops_s g_compops = +{ + .ao_shutdown = comp_shutdown, + .ao_setup = comp_setup, + .ao_read = comp_read, + .ao_ioctl = comp_ioctl, +}; + +#ifdef CONFIG_STM32_COMP1 +static struct stm32_comp_s g_comp1priv = +{ + .blanking = COMP1_BLANKING, + .pol = COMP1_POL, + .inm = COMP1_INM, + .out = COMP1_OUTSEL, + .lock = COMP1_LOCK, + .csr = STM32_COMP1_CSR, +#ifndef CONFIG_STM32_STM32F33XX + .mode = COMP1_MODE, + .hyst = COMP1_HYST, +#endif +}; + +static struct comp_dev_s g_comp1dev = +{ + .ad_ops = &g_compops, + .ad_priv = &g_comp1priv, +}; +#endif + +#ifdef CONFIG_STM32_COMP2 +static struct stm32_comp_s g_comp2priv = +{ + .blanking = COMP2_BLANKING, + .pol = COMP2_POL, + .inm = COMP2_INM, + .out = COMP2_OUTSEL, + .lock = COMP2_LOCK, + .csr = STM32_COMP2_CSR, +#ifndef CONFIG_STM32_STM32F33XX + .mode = COMP2_MODE, + .hyst = COMP2_HYST, +#endif +}; + +static struct comp_dev_s g_comp2dev = +{ + .ad_ops = &g_compops, + .ad_priv = &g_comp2priv, +}; +#endif + +#ifdef CONFIG_STM32_COMP3 +static struct stm32_comp_s g_comp3priv = +{ + .blanking = COMP3_BLANKING, + .pol = COMP3_POL, + .inm = COMP3_INM, + .out = COMP3_OUTSEL, + .lock = COMP3_LOCK, + .csr = STM32_COMP3_CSR, +#ifndef CONFIG_STM32_STM32F33XX + .mode = COMP3_MODE, + .hyst = COMP3_HYST, +#endif +}; + +static struct comp_dev_s g_comp3dev = +{ + .ad_ops = &g_compops, + .ad_priv = &g_comp3priv, +}; +#endif + +#ifdef CONFIG_STM32_COMP4 +static struct stm32_comp_s g_comp4priv = +{ + .blanking = COMP4_BLANKING, + .pol = COMP4_POL, + .inm = COMP4_INM, + .out = COMP4_OUTSEL, + .lock = COMP4_LOCK, + .csr = STM32_COMP4_CSR, +#ifndef CONFIG_STM32_STM32F33XX + .mode = COMP4_MODE, + .hyst = COMP4_HYST, +#endif +}; + +static struct comp_dev_s g_comp4dev = +{ + .ad_ops = &g_compops, + .ad_priv = &g_comp4priv, +}; +#endif + +#ifdef CONFIG_STM32_COMP5 +static struct stm32_comp_s g_comp5priv = +{ + .blanking = COMP5_BLANKING, + .pol = COMP5_POL, + .inm = COMP5_INM, + .out = COMP5_OUTSEL, + .lock = COMP5_LOCK, + .csr = STM32_COMP5_CSR, +#ifndef CONFIG_STM32_STM32F33XX + .mode = COMP5_MODE, + .hyst = COMP5_HYST, +#endif +}; + +static struct comp_dev_s g_comp5dev = +{ + .ad_ops = &g_compops, + .ad_priv = &g_comp5priv, +}; +#endif + +#ifdef CONFIG_STM32_COMP6 +static struct stm32_comp_s g_comp6priv = +{ + .blanking = COMP6_BLANKING, + .pol = COMP6_POL, + .inm = COMP6_INM, + .out = COMP6_OUTSEL, + .lock = COMP6_LOCK, + .csr = STM32_COMP6_CSR, +#ifndef CONFIG_STM32_STM32F33XX + .mode = COMP6_MODE, + .hyst = COMP6_HYST, +#endif +}; + +static struct comp_dev_s g_comp6dev = +{ + .ad_ops = &g_compops, + .ad_priv = &g_comp6priv, +}; +#endif + +#ifdef CONFIG_STM32_COMP7 +static struct stm32_comp_s g_comp7priv = +{ + .blanking = COMP7_BLANKING, + .pol = COMP7_POL, + .inm = COMP7_INM, + .out = COMP7_OUTSEL, + .lock = COMP7_LOCK, + .csr = STM32_COMP7_CSR, +#ifndef CONFIG_STM32_STM32F33XX + .mode = COMP7_MODE, + .hyst = COMP7_HYST, +#endif +}; + +static struct comp_dev_s g_comp7dev = +{ + .ad_ops = &g_compops, + .ad_priv = &g_comp7priv, +}; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: comp_modify_csr + * + * Description: + * Modify the value of a 32-bit COMP CSR register (not atomic). + * + * Input Parameters: + * priv - A reference to the COMP structure + * clrbits - The bits to clear + * setbits - The bits to set + * + * Returned Value: + * None + * + ****************************************************************************/ + +static inline void comp_modify_csr(struct stm32_comp_s *priv, + uint32_t clearbits, uint32_t setbits) +{ + uint32_t csr = priv->csr; + + modifyreg32(csr, clearbits, setbits); +} + +/**************************************************************************** + * Name: comp_getreg_csr + * + * Description: + * Read the value of an COMP CSR register + * + * Input Parameters: + * priv - A reference to the COMP structure + * + * Returned Value: + * The current contents of the COMP CSR register + * + ****************************************************************************/ + +static inline uint32_t comp_getreg_csr(struct stm32_comp_s *priv) +{ + uint32_t csr = priv->csr; + + return getreg32(csr); +} + +/**************************************************************************** + * Name: comp_putreg_csr + * + * Description: + * Write a value to an COMP register. + * + * Input Parameters: + * priv - A reference to the COMP structure + * value - The value to write to the COMP CSR register + * + * Returned Value: + * None + * + ****************************************************************************/ + +static inline void comp_putreg_csr(struct stm32_comp_s *priv, + uint32_t value) +{ + uint32_t csr = priv->csr; + + putreg32(value, csr); +} + +/**************************************************************************** + * Name: stm32_comp_complock_get + * + * Description: + * Get COMP lock bit state + * + * Input Parameters: + * priv - A reference to the COMP structure + * + * Returned Value: + * True if COMP locked, false if not locked + * + ****************************************************************************/ + +static bool stm32_complock_get(struct stm32_comp_s *priv) +{ + uint32_t regval; + + regval = comp_getreg_csr(priv); + + return (((regval & COMP_CSR_LOCK) == 0) ? false : true); +} + +/**************************************************************************** + * Name: stm32_complock + * + * Description: + * Lock comparator CSR register + * + * Input Parameters: + * priv - A reference to the COMP structure + * enable - lock flag + * + * Returned Value: + * 0 on success, a negated errno value on failure + * + ****************************************************************************/ + +static int stm32_complock(struct stm32_comp_s *priv, bool lock) +{ + bool current; + + current = stm32_complock_get(priv); + + if (current) + { + if (lock == false) + { + aerr("ERROR: COMP LOCK can be cleared only by a system reset\n"); + + return -EPERM; + } + } + else + { + if (lock == true) + { + comp_modify_csr(priv, 0, COMP_CSR_LOCK); + + priv->lock = COMP_LOCK_RO; + } + } + + return OK; +} + +/**************************************************************************** + * Name: stm32_compconfig + * + * Description: + * Configure comparator and used I/Os + * + * Input Parameters: + * priv - A reference to the COMP structure + * + * Returned Value: + * 0 on success, a negated errno value on failure + * + * REVISIT: Where to config comparator output pin ? + * + ****************************************************************************/ + +static int stm32_compconfig(struct stm32_comp_s *priv) +{ + uint32_t regval = 0; + int index; + + /* Get comparator index */ + + switch (priv->csr) + { +#ifdef CONFIG_STM32_COMP1 + case STM32_COMP1_CSR: + index = 1; + break; +#endif + +#ifdef CONFIG_STM32_COMP2 + case STM32_COMP2_CSR: + index = 2; + break; +#endif + +#ifdef CONFIG_STM32_COMP3 + case STM32_COMP3_CSR: + index = 3; + break; +#endif + +#ifdef CONFIG_STM32_COMP4 + case STM32_COMP4_CSR: + index = 4; + break; +#endif + +#ifdef CONFIG_STM32_COMP5 + case STM32_COMP5_CSR: + index = 5; + break; +#endif + +#ifdef CONFIG_STM32_COMP6 + case STM32_COMP6_CSR: + index = 6; + break; +#endif + +#ifdef CONFIG_STM32_COMP7 + case STM32_COMP7_CSR: + index = 7; + break; +#endif + + default: + return -EINVAL; + } + + /* Configure non inverting input */ + + switch (index) + { +#ifdef CONFIG_STM32_COMP1 + case 1: + stm32_configgpio(GPIO_COMP1_INP); + break; +#endif + +#ifdef CONFIG_STM32_COMP2 + case 2: + stm32_configgpio(GPIO_COMP2_INP); + break; +#endif + +#ifdef CONFIG_STM32_COMP3 + case 3: + stm32_configgpio(GPIO_COMP3_INP); + break; +#endif + +#ifdef CONFIG_STM32_COMP4 + case 4: + stm32_configgpio(GPIO_COMP4_INP); + break; +#endif + +#ifdef CONFIG_STM32_COMP5 + case 5: + stm32_configgpio(GPIO_COMP5_INP); + break; +#endif + +#ifdef CONFIG_STM32_COMP6 + case 6: + stm32_configgpio(GPIO_COMP6_INP); + break; +#endif + +#ifdef CONFIG_STM32_COMP7 + case 7: + stm32_configgpio(GPIO_COMP7_INP); + break; +#endif + + default: + return -EINVAL; + } + + /* Set Comparator inverting input */ + + switch (priv->inm) + { + case COMP_INMSEL_1P4VREF: + regval |= COMP_CSR_INMSEL_1P4VREF; + break; + + case COMP_INMSEL_1P2VREF: + regval |= COMP_CSR_INMSEL_1P2VREF; + break; + + case COMP_INMSEL_3P4VREF: + regval |= COMP_CSR_INMSEL_3P4VREF; + break; + + case COMP_INMSEL_VREF: + regval |= COMP_CSR_INMSEL_VREF; + break; + + case COMP_INMSEL_DAC1CH1: + regval |= COMP_CSR_INMSEL_DAC1CH1; + break; + + case COMP_INMSEL_DAC1CH2: + regval |= COMP_CSR_INMSEL_DAC1CH2; + break; + + case COMP_INMSEL_PIN: + { + /* INMSEL PIN configuration dependent on COMP index */ + + switch (index) + { + /* TODO: Inverting input pin configuration for COMP1/3/5/7 */ + +#ifdef CONFIG_STM32_COMP2 + case 2: + { + /* COMP2_INM can be PA2 or PA4 */ + + stm32_configgpio(GPIO_COMP2_INM); + regval |= (GPIO_COMP2_INM == GPIO_COMP2_INM_1 ? + COMP_CSR_INMSEL_PA2 : COMP_CSR_INMSEL_PA4); + break; + } +#endif + +#ifdef CONFIG_STM32_COMP4 + case 4: + { + /* COMP4_INM can be PB2 or PA4 */ + + stm32_configgpio(GPIO_COMP4_INM); + regval |= (GPIO_COMP4_INM == GPIO_COMP4_INM_1 ? + COMP_CSR_INMSEL_PB2 : COMP_CSR_INMSEL_PA4); + break; + } +#endif + +#ifdef CONFIG_STM32_COMP6 + case 6: + { + /* COMP6_INM can be PB15 or PA4 */ + + stm32_configgpio(GPIO_COMP6_INM); + regval |= (GPIO_COMP6_INM == GPIO_COMP6_INM_1 ? + COMP_CSR_INMSEL_PB15 : COMP_CSR_INMSEL_PA4); + break; + } +#endif + + default: + return -EINVAL; + } + + break; + } + + default: + return -EINVAL; + } + + /* Set Comparator output selection */ + + switch (priv->out) + { + case COMP_OUTSEL_NOSEL: + regval |= COMP_CSR_OUTSEL_NOSEL; + break; + + case COMP_OUTSEL_BRKACTH: + regval |= COMP_CSR_OUTSEL_BRKACTH; + break; + + case COMP_OUTSEL_BRK2: + regval |= COMP_CSR_OUTSEL_BRK2; + break; + + case COMP_OUTSEL_T1OCC: + regval |= COMP_CSR_OUTSEL_T1OCC; + break; + + case COMP_OUTSEL_T3CAP3: + regval |= COMP_CSR_OUTSEL_T3CAP3; + break; + + case COMP_OUTSEL_T2CAP2: + regval |= COMP_CSR_OUTSEL_T2CAP2; + break; + + case COMP_OUTSEL_T1CAP1: + regval |= COMP_CSR_OUTSEL_T1CAP1; + break; + + case COMP_OUTSEL_T2CAP4: + regval |= COMP_CSR_OUTSEL_T2CAP4; + break; + + case COMP_OUTSEL_T15CAP2: + regval |= COMP_CSR_OUTSEL_T15CAP2; + break; + + case COMP_OUTSEL_T2OCC: + if (index == 2) + { + regval |= COMP2_CSR_OUTSEL_T2OCC; + } + else if (index == 6) + { + regval |= COMP6_CSR_OUTSEL_T2OCC; + } + + break; + + case COMP_OUTSEL_T16OCC: + regval |= COMP_CSR_OUTSEL_T16OCC; + break; + + case COMP_OUTSEL_T3CAP1: + regval |= COMP_CSR_OUTSEL_T3CAP1; + break; + + case COMP_OUTSEL_T15OCC: + regval |= COMP_CSR_OUTSEL_T15OCC; + break; + + case COMP_OUTSEL_T16CAP1: + regval |= COMP_CSR_OUTSEL_T16CAP1; + break; + + case COMP_OUTSEL_T3OCC: + regval |= COMP_CSR_OUTSEL_T3OCC; + break; + + default: + return -EINVAL; + } + + /* Set Comparator output polarity */ + + regval |= (priv->pol == COMP_POL_INVERTED ? COMP_CSR_POL : 0); + + /* Set Comparator output blanking source */ + + switch (priv->blanking) + { + case COMP_BLANKING_DIS: + regval |= COMP_CSR_BLANKING_DIS; + break; + + case COMP_BLANKING_T1OC5: + regval |= COMP_CSR_BLANKING_T1OC5; + break; + + case COMP_BLANKING_T3OC4: + regval |= COMP_CSR_BLANKING_T3OC4; + break; + + case COMP_BLANKING_T2OC3: + regval |= COMP_CSR_BLANKING_T2OC3; + break; + + case COMP_BLANKING_T15OC1: + regval |= COMP_CSR_BLANKING_T15OC1; + break; + + case COMP_BLANKING_T2OC4: + regval |= COMP_CSR_BLANKING_T2OC4; + break; + + case COMP_BLANKING_T15OC2: + regval |= COMP_CSR_BLANKING_T15OC1; + break; + + default: + return -EINVAL; + } + + /* Save CSR register */ + + comp_putreg_csr(priv, regval); + + /* Enable Comparator */ + + stm32_compenable(priv, true); + + /* Lock Comparator if needed */ + + if (priv->lock == COMP_LOCK_RO) + { + stm32_complock(priv, true); + } + + return OK; +} + +/**************************************************************************** + * Name: stm32_compenable + * + * Description: + * Enable/disable comparator + * + * Input Parameters: + * priv - A reference to the COMP structure + * enable - enable/disable flag + * + * Returned Value: + * 0 on success, a negated errno value on failure + * + ****************************************************************************/ + +static int stm32_compenable(struct stm32_comp_s *priv, bool enable) +{ + bool lock; + + ainfo("enable: %d\n", enable ? 1 : 0); + + lock = stm32_complock_get(priv); + + if (lock) + { + aerr("ERROR: Comparator locked!\n"); + + return -EPERM; + } + else + { + if (enable) + { + /* Enable the COMP */ + + comp_modify_csr(priv, 0, COMP_CSR_COMPEN); + } + else + { + /* Disable the COMP */ + + comp_modify_csr(priv, COMP_CSR_COMPEN, 0); + } + } + + return OK; +} + +/**************************************************************************** + * Name: adc_setup + * + * Description: + * Configure the COMP. This method is called the first time that the COMP + * device is opened. This will occur when the port is first opened. + * This setup includes configuring and attaching COMP interrupts. + * Interrupts are all disabled upon return. + * + * Input Parameters: + * + * Returned Value: + * + ****************************************************************************/ + +static int comp_setup(struct comp_dev_s *dev) +{ +#warning "Missing logic" + + return OK; +} + +/**************************************************************************** + * Name: comp_shutdown + * + * Description: + * Disable the COMP. This method is called when the COMP device is closed. + * This method reverses the operation the setup method. + * Works only if COMP device is not locked. + * + * Input Parameters: + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void comp_shutdown(struct comp_dev_s *dev) +{ +#warning "Missing logic" +} + +/**************************************************************************** + * Name: comp_read + * + * Description: + * Get the COMP output state. + * + * Input Parameters: + * + * Returned Value: + * 0 if output is low (non-inverting input below inverting input), + * 1 if output is high (non inverting input above inverting input). + * + ****************************************************************************/ + +static int comp_read(struct comp_dev_s *dev) +{ + struct stm32_comp_s *priv; + uint32_t regval; + + priv = dev->ad_priv; + regval = comp_getreg_csr(priv); + + return (((regval & COMP_CSR_OUT) == 0) ? 0 : 1); +} + +/**************************************************************************** + * Name: comp_ioctl + * + * Description: + * All ioctl calls will be routed through this method. + * + * Input Parameters: + * dev - pointer to device structure used by the driver + * cmd - command + * arg - arguments passed with command + * + * Returned Value: + * Zero on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int comp_ioctl(struct comp_dev_s *dev, int cmd, unsigned long arg) +{ +#warning "Missing logic" + return -ENOTTY; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_compinitialize + * + * Description: + * Initialize the COMP. + * + * Input Parameters: + * intf - The COMP interface number. + * + * Returned Value: + * Valid COMP device structure reference on success; a NULL on failure. + * + * Assumptions: + * 1. Clock to the COMP block has enabled, + * 2. Board-specific logic has already configured + * + ****************************************************************************/ + +struct comp_dev_s *stm32_compinitialize(int intf) +{ + struct comp_dev_s *dev; + struct stm32_comp_s *comp; + int ret; + + switch (intf) + { +#ifdef CONFIG_STM32_COMP1 + case 1: + ainfo("COMP1 selected\n"); + dev = &g_comp1dev; + break; +#endif + +#ifdef CONFIG_STM32_COMP2 + case 2: + ainfo("COMP2 selected\n"); + dev = &g_comp2dev; + break; +#endif + +#ifdef CONFIG_STM32_COMP3 + case 3: + ainfo("COMP3 selected\n"); + dev = &g_comp3dev; + break; +#endif + +#ifdef CONFIG_STM32_COMP4 + case 4: + ainfo("COMP4 selected\n"); + dev = &g_comp4dev; + break; +#endif + +#ifdef CONFIG_STM32_COMP5 + case 5: + ainfo("COMP5 selected\n"); + dev = &g_comp5dev; + break; +#endif + +#ifdef CONFIG_STM32_COMP6 + case 6: + ainfo("COMP6 selected\n"); + dev = &g_comp6dev; + break; +#endif + +#ifdef CONFIG_STM32_COMP7 + case 7: + ainfo("COMP7 selected\n"); + dev = &g_comp7dev; + break; +#endif + + default: + aerr("ERROR: No COMP interface defined\n"); + return NULL; + } + + /* Configure selected comparator */ + + comp = dev->ad_priv; + + ret = stm32_compconfig(comp); + if (ret < 0) + { + aerr("ERROR: Failed to initialize COMP%d: %d\n", intf, ret); + return NULL; + } + + return dev; +} + +#endif /* CONFIG_STM32_STM32F30XX || CONFIG_STM32_STM32F33XX || + * CONFIG_STM32_STM32F37XX + */ + +#endif /* CONFIG_STM32_COMP2 || CONFIG_STM32_COMP4 || + * CONFIG_STM32_COMP6 + */ diff --git a/arch/arm/src/common/stm32/stm32_comp_m3m4_v2.c b/arch/arm/src/common/stm32/stm32_comp_m3m4_v2.c new file mode 100644 index 0000000000000..8939e4a6ce93c --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_comp_m3m4_v2.c @@ -0,0 +1,1024 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_comp_m3m4_v2.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include +#include + +#include + +#include "arm_internal.h" +#include "chip.h" +#include "stm32_comp.h" +#include "stm32_gpio.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Some COMP peripheral must be enabled and the device must be supported */ + +#define DEVICE_NOT_SUPPORTED + +#if defined(CONFIG_STM32_COMP) + +#ifndef CONFIG_STM32_SYSCFG +# error "SYSCFG clock enable must be set" +#endif + +#if defined(CONFIG_STM32_STM32G43XX) +# undef DEVICE_NOT_SUPPORTED +# if defined(CONFIG_STM32_COMP5) || defined(CONFIG_STM32_COMP6) || \ + defined(CONFIG_STM32_COMP7) +# error "STM32G43XX supports only COMP1, COMP2, COMP3 and COMP4" +# endif +#endif + +#if defined(DEVICE_NOT_SUPPORTED) +# error "Device not supported" +#endif + +#if defined(CONFIG_STM32_COMP1_OUT) || defined(CONFIG_STM32_COMP2_OUT) || \ + defined(CONFIG_STM32_COMP3_OUT) || defined(CONFIG_STM32_COMP4_OUT) || \ + defined(CONFIG_STM32_COMP5_OUT) || defined(CONFIG_STM32_COMP6_OUT) || \ + defined(CONFIG_STM32_COMP7_OUT) +# define COMP_OUT_GPIO +#endif + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/* This structure describes the configuration of one COMP device */ + +struct stm32_comp_s +{ + uint8_t inm; /* Inverting input selection */ + uint32_t gpio_inm; /* Inverting input pin */ + uint8_t inp; /* Non inverting input selection */ + uint32_t gpio_inp; /* Non-inverting input pin */ + uint8_t pol; /* Output polarity */ + uint8_t hyst; /* Comparator hysteresis */ + uint8_t blanking; /* Blanking source */ + uint8_t lock; /* Comparator Lock */ + uint32_t csr; /* Control and status register */ +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/* COMP Register access */ + +static inline void comp_modify_csr(struct stm32_comp_s *priv, + uint32_t clearbits, uint32_t setbits); +static inline uint32_t comp_getreg_csr(struct stm32_comp_s *priv); +static inline void comp_putreg_csr(struct stm32_comp_s *priv, + uint32_t value); + +/* COMP Driver Methods */ + +#if defined (CONFIG_COMP) +static void comp_shutdown(struct comp_dev_s *dev); +static int comp_setup(struct comp_dev_s *dev); +static int comp_read(struct comp_dev_s *dev); +static int comp_ioctl(struct comp_dev_s *dev, int cmd, + unsigned long arg); +#endif + +static int comp_config(struct stm32_comp_s *priv); +static int comp_enable(struct stm32_comp_s *priv, bool enable); +static bool comp_lock_get(struct stm32_comp_s *priv); +static int comp_lock_set(struct stm32_comp_s *priv, bool lock); + +static int comp_config_inmpin(struct stm32_comp_s *priv); +static int comp_config_inppin(struct stm32_comp_s *priv); +#if defined(COMP_OUT_GPIO) +static int comp_config_outpin(struct stm32_comp_s *priv); +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#ifdef CONFIG_COMP +static const struct comp_ops_s g_compops = +{ + .ao_shutdown = comp_shutdown, + .ao_setup = comp_setup, + .ao_read = comp_read, + .ao_ioctl = comp_ioctl, +}; +#endif + +#ifdef CONFIG_STM32_COMP1 +static struct stm32_comp_s g_comp1priv = +{ + .inm = CONFIG_STM32_COMP1_INM, + .inp = CONFIG_STM32_COMP1_INP, + .pol = CONFIG_STM32_COMP1_POL, + .hyst = CONFIG_STM32_COMP1_HYST, + .blanking = CONFIG_STM32_COMP1_BLANKSEL, + .lock = CONFIG_STM32_COMP1_LOCK, + .gpio_inp = GPIO_COMP1_INP, + .csr = STM32_COMP1_CSR +}; + +static struct comp_dev_s g_comp1dev = +{ +#ifdef CONFIG_COMP + .ad_ops = &g_compops, +#endif + .ad_priv = &g_comp1priv, +}; +#endif + +#ifdef CONFIG_STM32_COMP2 +static struct stm32_comp_s g_comp2priv = +{ + .inm = CONFIG_STM32_COMP2_INM, + .inp = CONFIG_STM32_COMP2_INP, + .pol = CONFIG_STM32_COMP2_POL, + .hyst = CONFIG_STM32_COMP2_HYST, + .blanking = CONFIG_STM32_COMP2_BLANKSEL, + .lock = CONFIG_STM32_COMP2_LOCK, + .gpio_inp = GPIO_COMP2_INP, + .csr = STM32_COMP2_CSR +}; + +static struct comp_dev_s g_comp2dev = +{ +#ifdef CONFIG_COMP + .ad_ops = &g_compops, +#endif + .ad_priv = &g_comp2priv, +}; +#endif + +#ifdef CONFIG_STM32_COMP3 +static struct stm32_comp_s g_comp3priv = +{ + .inm = CONFIG_STM32_COMP3_INM, + .inp = CONFIG_STM32_COMP3_INP, + .pol = CONFIG_STM32_COMP3_POL, + .hyst = CONFIG_STM32_COMP3_HYST, + .blanking = CONFIG_STM32_COMP3_BLANKSEL, + .lock = CONFIG_STM32_COMP3_LOCK, + .gpio_inp = GPIO_COMP3_INP, + .csr = STM32_COMP3_CSR +}; + +static struct comp_dev_s g_comp3dev = +{ +#ifdef CONFIG_COMP + .ad_ops = &g_compops, +#endif + .ad_priv = &g_comp3priv, +}; +#endif + +#ifdef CONFIG_STM32_COMP4 +static struct stm32_comp_s g_comp4priv = +{ + .inm = CONFIG_STM32_COMP4_INM, + .inp = CONFIG_STM32_COMP4_INP, + .pol = CONFIG_STM32_COMP4_POL, + .hyst = CONFIG_STM32_COMP4_HYST, + .blanking = CONFIG_STM32_COMP4_BLANKSEL, + .lock = CONFIG_STM32_COMP4_LOCK, + .gpio_inp = GPIO_COMP4_INP, + .csr = STM32_COMP4_CSR +}; + +static struct comp_dev_s g_comp4dev = +{ +#ifdef CONFIG_COMP + .ad_ops = &g_compops, +#endif + .ad_priv = &g_comp4priv, +}; +#endif + +#ifdef CONFIG_STM32_COMP5 +static struct stm32_comp_s g_comp5priv = +{ + .inm = CONFIG_STM32_COMP5_INM, + .inp = CONFIG_STM32_COMP5_INP, + .pol = CONFIG_STM32_COMP5_POL, + .hyst = CONFIG_STM32_COMP5_HYST, + .blanking = CONFIG_STM32_COMP5_BLANKSEL, + .lock = CONFIG_STM32_COMP5_LOCK, + .gpio_inp = GPIO_COMP5_INP, + .csr = STM32_COMP5_CSR +}; + +static struct comp_dev_s g_comp5dev = +{ +#ifdef CONFIG_COMP + .ad_ops = &g_compops, +#endif + .ad_priv = &g_comp5priv, +}; +#endif + +#ifdef CONFIG_STM32_COMP6 +static struct stm32_comp_s g_comp6priv = +{ + .inm = CONFIG_STM32_COMP6_INM, + .inp = CONFIG_STM32_COMP6_INP, + .pol = CONFIG_STM32_COMP6_POL, + .hyst = CONFIG_STM32_COMP6_HYST, + .blanking = CONFIG_STM32_COMP6_BLANKSEL, + .lock = CONFIG_STM32_COMP6_LOCK, + .gpio_inp = GPIO_COMP6_INP, + .csr = STM32_COMP6_CSR +}; + +static struct comp_dev_s g_comp6dev = +{ +#ifdef CONFIG_COMP + .ad_ops = &g_compops, +#endif + .ad_priv = &g_comp6priv, +}; +#endif + +#ifdef CONFIG_STM32_COMP7 +static struct stm32_comp_s g_comp7priv = +{ + .inm = CONFIG_STM32_COMP7_INM, + .inp = CONFIG_STM32_COMP7_INP, + .pol = CONFIG_STM32_COMP7_POL, + .hyst = CONFIG_STM32_COMP7_HYST, + .blanking = CONFIG_STM32_COMP7_BLANKSEL, + .lock = CONFIG_STM32_COMP7_LOCK, + .gpio_inp = GPIO_COMP7_INP, + .csr = STM32_COMP7_CSR +}; + +static struct comp_dev_s g_comp7dev = +{ +#ifdef CONFIG_COMP + .ad_ops = &g_compops, +#endif + .ad_priv = &g_comp7priv, +}; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: comp_modify_csr + * + * Description: + * Modify the value of a 32-bit COMP CSR register (not atomic). + * + * Input Parameters: + * priv - A reference to the COMP structure + * clrbits - The bits to clear + * setbits - The bits to set + * + * Returned Value: + * None + * + ****************************************************************************/ + +static inline void comp_modify_csr(struct stm32_comp_s *priv, + uint32_t clearbits, uint32_t setbits) +{ + uint32_t csr = priv->csr; + + modifyreg32(csr, clearbits, setbits); +} + +/**************************************************************************** + * Name: comp_getreg_csr + * + * Description: + * Read the value of an COMP CSR register + * + * Input Parameters: + * priv - A reference to the COMP structure + * + * Returned Value: + * The current contents of the COMP CSR register + * + ****************************************************************************/ + +static inline uint32_t comp_getreg_csr(struct stm32_comp_s *priv) +{ + uint32_t csr = priv->csr; + + return getreg32(csr); +} + +/**************************************************************************** + * Name: comp_putreg_csr + * + * Description: + * Write a value to an COMP register. + * + * Input Parameters: + * priv - A reference to the COMP structure + * value - The value to write to the COMP CSR register + * + * Returned Value: + * None + * + ****************************************************************************/ + +static inline void comp_putreg_csr(struct stm32_comp_s *priv, + uint32_t value) +{ + uint32_t csr = priv->csr; + + putreg32(value, csr); +} + +/**************************************************************************** + * Name: comp_lock_get + * + * Description: + * Get COMP lock bit state + * + * Input Parameters: + * priv - A reference to the COMP structure + * + * Returned Value: + * True if COMP locked, false if not locked + * + ****************************************************************************/ + +static bool comp_lock_get(struct stm32_comp_s *priv) +{ + uint32_t regval; + + regval = comp_getreg_csr(priv); + + return (((regval & COMP_CSR_LOCK) == 0) ? false : true); +} + +/**************************************************************************** + * Name: comp_lock_set + * + * Description: + * Lock comparator CSR register + * + * Input Parameters: + * priv - A reference to the COMP structure + * enable - lock flag + * + * Returned Value: + * 0 on success, a negated errno value on failure + * + ****************************************************************************/ + +static int comp_lock_set(struct stm32_comp_s *priv, bool lock) +{ + if (comp_lock_get(priv)) + { + if (lock == false) + { + aerr("ERROR: COMP LOCK can be cleared only by a system reset\n"); + + return -EPERM; + } + } + else + { + if (lock == true) + { + comp_modify_csr(priv, 0, COMP_CSR_LOCK); + + priv->lock = 1; + } + } + + return OK; +} + +/**************************************************************************** + * Name: comp_config_inmpin + * + * Description: + * Configure comparator inverting input pin. The GPIO that COMPx inverting + * input will be assigned is dependent of comparator number and must be + * defined in board.h file. See table 196 in RM0440. + * + * Input Parameters: + * priv - A reference to the COMP structure + * + * Returned Value: + * 0 on success, a negated errno value on failure + * + ****************************************************************************/ + +static int comp_config_inmpin(struct stm32_comp_s *priv) +{ +# if defined(CONFIG_STM32_COMP1) + if (priv->csr == STM32_COMP1_CSR) + { + stm32_configgpio(GPIO_COMP1_INM); + } +# endif + +# if defined(CONFIG_STM32_COMP2) + if (priv->csr == STM32_COMP2_CSR) + { + stm32_configgpio(GPIO_COMP2_INM); + } +# endif + +# if defined(CONFIG_STM32_COMP3) + if (priv->csr == STM32_COMP3_CSR) + { + stm32_configgpio(GPIO_COMP3_INM); + } +# endif + +# if defined(CONFIG_STM32_COMP4) + if (priv->csr == STM32_COMP4_CSR) + { + stm32_configgpio(GPIO_COMP4_INM); + } +# endif + +# if defined(CONFIG_STM32_COMP5) + if (priv->csr == STM32_COMP5_CSR) + { + stm32_configgpio(GPIO_COMP5_INM); + } +# endif + +# if defined(CONFIG_STM32_COMP6) + if (priv->csr == STM32_COMP6_CSR) + { + stm32_configgpio(GPIO_COMP6_INM); + } +# endif + +# if defined(CONFIG_STM32_COMP7) + if (priv->csr == STM32_COMP7_CSR) + { + stm32_configgpio(GPIO_COMP7_INM); + } +# endif + + return OK; +} + +/**************************************************************************** + * Name: comp_config_inppin + * + * Description: + * Configure comparator non-inverting input pin. The IO pin that COMPx + * non-inverting input will be assigned is dependent of comparator number + * and must be defined in board.h file. + * + * Input Parameters: + * priv - A reference to the COMP structure + * + * Returned Value: + * 0 on success, a negated errno value on failure + * + ****************************************************************************/ + +static int comp_config_inppin(struct stm32_comp_s *priv) +{ +# if defined(CONFIG_STM32_COMP1) + if (priv->csr == STM32_COMP1_CSR) + { + stm32_configgpio(GPIO_COMP1_INP); + } +# endif + +# if defined(CONFIG_STM32_COMP2) + if (priv->csr == STM32_COMP2_CSR) + { + stm32_configgpio(GPIO_COMP2_INP); + } +# endif + +# if defined(CONFIG_STM32_COMP3) + if (priv->csr == STM32_COMP3_CSR) + { + stm32_configgpio(GPIO_COMP3_INP); + } +# endif + +# if defined(CONFIG_STM32_COMP4) + if (priv->csr == STM32_COMP4_CSR) + { + stm32_configgpio(GPIO_COMP4_INP); + } +# endif + +# if defined(CONFIG_STM32_COMP5) + if (priv->csr == STM32_COMP5_CSR) + { + stm32_configgpio(GPIO_COMP5_INP); + } +# endif + +# if defined(CONFIG_STM32_COMP6) + if (priv->csr == STM32_COMP6_CSR) + { + stm32_configgpio(GPIO_COMP6_INP); + } +# endif + +# if defined(CONFIG_STM32_COMP7) + if (priv->csr == STM32_COMP7_CSR) + { + stm32_configgpio(GPIO_COMP7_INP); + } +# endif + + return OK; +} + +/**************************************************************************** + * Name: comp_config_outpin + * + * Description: + * Configure comparator output GPIO pin. + * + * Input Parameters: + * priv - A reference to the COMP structure + * + * Returned Value: + * 0 on success, a negated errno value on failure + * + ****************************************************************************/ + +#if defined(COMP_OUT_GPIO) +static int comp_config_outpin(struct stm32_comp_s *priv) +{ +# if defined(CONFIG_STM32_COMP1_OUT) + if (priv->csr == STM32_COMP1_CSR) + { + stm32_configgpio(GPIO_COMP1_OUT); + } +# endif + +# if defined(CONFIG_STM32_COMP2_OUT) + if (priv->csr == STM32_COMP2_CSR) + { + ainfo("\tOUT assigned to: GPIO\n"); + stm32_configgpio(GPIO_COMP2_OUT); + } +# endif + +# if defined(CONFIG_STM32_COMP3_OUT) + if (priv->csr == STM32_COMP3_CSR) + { + stm32_configgpio(GPIO_COMP3_OUT); + } +# endif + +# if defined(CONFIG_STM32_COMP4_OUT) + if (priv->csr == STM32_COMP4_CSR) + { + stm32_configgpio(GPIO_COMP4_OUT); + } +# endif + +# if defined(CONFIG_STM32_COMP5_OUT) + if (priv->csr == STM32_COMP5_CSR) + { + stm32_configgpio(GPIO_COMP5_OUT); + } +# endif + +# if defined(CONFIG_STM32_COMP6_OUT) + if (priv->csr == STM32_COMP6_CSR) + { + stm32_configgpio(GPIO_COMP6_OUT); + } +# endif + +# if defined(CONFIG_STM32_COMP7_OUT) + if (priv->csr == STM32_COMP7_CSR) + { + stm32_configgpio(GPIO_COMP7_OUT); + } +# endif + + return OK; +} +#endif /* COMP_OUT_GPIO */ + +/**************************************************************************** + * Name: comp_config + * + * Description: + * Configure comparator and used I/Os. The pin configuration and the input + * assignments are COMP index dependent. + * + * Input Parameters: + * priv - A reference to the COMP structure + * + * Returned Value: + * 0 on success, a negated errno value on failure + * + * REVISIT: Where to config comparator output pin ? + * + ****************************************************************************/ + +static int comp_config(struct stm32_comp_s *priv) +{ + uint32_t regval = 0; + uint32_t value = 0; + + /* Configure COMPx inverting input. */ + + value = priv->inm << COMP_CSR_INMSEL_SHIFT; + + switch (priv->inm) + { + case COMP_INM_1_4_VREF: + case COMP_INM_1_2_VREF: + case COMP_INM_3_4_VREF: + + value |= COMP_CSR_BRGEN; /* scaler resistor bridge enable */ + + case COMP_INM_VREF: + + value |= COMP_CSR_SCALEN; /* VREFINT scaler enable */ + break; + + case COMP_INM_DAC_1: + case COMP_INM_DAC_2: + + break; + + case COMP_INM_PIN_1: + case COMP_INM_PIN_2: + + comp_config_inmpin(priv); + break; + + default: + return -EINVAL; + } + + regval |= value; + + /* Configure COMPx non-inverting input. */ + + ainfo("\tINP assigned to GPIO%d\n", priv->inp); + + value = priv->inp << COMP_CSR_INPSEL_SHIFT; + regval |= value; + + comp_config_inppin(priv); + + /* Configure COMPx polarity */ + + if (priv->pol == COMP_POL_INVERTED) + { + value = COMP_CSR_POL; + regval |= value; + } + + /* Configure COMPx hysteresis */ + + switch (priv->hyst) + { + case COMP_HYST_DIS: + case COMP_HYST_10MV: + case COMP_HYST_20MV: + case COMP_HYST_30MV: + case COMP_HYST_40MV: + case COMP_HYST_50MV: + case COMP_HYST_60MV: + case COMP_HYST_70MV: + + value = priv->hyst << COMP_CSR_HYST_SHIFT; + regval |= value; + break; + + default: + return -EINVAL; + } + + /* Configure COMPx blanking signal source */ + + switch (priv->blanking) + { + case COMP_BLANKING_DIS: + case COMP_BLANKING_TIMX_OCY_1: + case COMP_BLANKING_TIMX_OCY_2: + case COMP_BLANKING_TIMX_OCY_3: + case COMP_BLANKING_TIMX_OCY_4: + case COMP_BLANKING_TIMX_OCY_5: + case COMP_BLANKING_TIMX_OCY_6: + case COMP_BLANKING_TIMX_OCY_7: + + value = priv->blanking << COMP_CSR_BLANKING_SHIFT; + regval |= value; + break; + + default: + return -EINVAL; + } + + /* Set Comparator output selection */ + +#if defined(COMP_OUT_GPIO) + comp_config_outpin(priv); +#endif + + /* Save CSR register */ + + comp_putreg_csr(priv, regval); + + /* Enable Comparator */ + + comp_enable(priv, true); + + /* Lock Comparator if needed */ + + if (priv->lock) + { + comp_lock_set(priv, true); + } + + return OK; +} + +/**************************************************************************** + * Name: comp_enable + * + * Description: + * Enable/disable comparator + * + * Input Parameters: + * priv - A reference to the COMP structure + * enable - enable/disable flag + * + * Returned Value: + * 0 on success, a negated errno value on failure + * + ****************************************************************************/ + +static int comp_enable(struct stm32_comp_s *priv, bool enable) +{ + bool lock; + + ainfo("enable: %d\n", enable ? 1 : 0); + + lock = comp_lock_get(priv); + + if (lock) + { + aerr("ERROR: Comparator locked!\n"); + + return -EPERM; + } + else + { + if (enable) + { + /* Enable the COMP */ + + comp_modify_csr(priv, 0, COMP_CSR_COMPEN); + } + else + { + /* Disable the COMP */ + + comp_modify_csr(priv, COMP_CSR_COMPEN, 0); + } + } + + return OK; +} + +/**************************************************************************** + * Name: comp_setup + * + * Description: + * Configure the COMP. This method is called the first time that the COMP + * device is opened. This will occur when the port is first opened. This + * setup includes configuring and attaching COMP interrupts. + * Interrupts are all disabled upon return. + * + * Input Parameters: + * + * Returned Value: + * + ****************************************************************************/ + +#ifdef CONFIG_COMP +static int comp_setup(struct comp_dev_s *dev) +{ +#warning "Missing logic" + + return OK; +} +#endif + +/**************************************************************************** + * Name: comp_shutdown + * + * Description: + * Disable the COMP. This method is called when the COMP device is closed. + * This method reverses the operation the setup method. + * Works only if COMP device is not locked. + * + * Input Parameters: + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_COMP +static void comp_shutdown(struct comp_dev_s *dev) +{ +# warning "Missing logic" +} +#endif + +/**************************************************************************** + * Name: comp_read + * + * Description: + * Get the COMP output state. + * + * Input Parameters: + * + * Returned Value: + * 0 if output is low (non-inverting input below inverting input), + * 1 if output is high (non inverting input above inverting input). + * + ****************************************************************************/ + +#ifdef CONFIG_COMP +static int comp_read(struct comp_dev_s *dev) +{ + struct stm32_comp_s *priv; + uint32_t regval; + + priv = dev->ad_priv; + regval = comp_getreg_csr(priv); + + return (((regval & COMP_CSR_VALUE) == 0) ? 0 : 1); +} +#endif + +/**************************************************************************** + * Name: comp_ioctl + * + * Description: + * All ioctl calls will be routed through this method. + * + * Input Parameters: + * dev - pointer to device structure used by the driver + * cmd - command + * arg - arguments passed with command + * + * Returned Value: + * Zero on success; a negated errno value on failure. + * + ****************************************************************************/ + +#ifdef CONFIG_COMP +static int comp_ioctl(struct comp_dev_s *dev, int cmd, unsigned long arg) +{ +#warning "Missing logic" + return -ENOTTY; +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_compinitialize + * + * Description: + * Initialize the COMP. + * + * Input Parameters: + * intf - The COMP interface number. + * + * Returned Value: + * Valid COMP device structure reference on success; a NULL on failure. + * + * Assumptions: + * 1. Clock to the COMP block has enabled, + * 2. Board-specific logic has already configured + * + ****************************************************************************/ + +struct comp_dev_s *stm32_compinitialize(int intf) +{ + struct comp_dev_s *dev; + struct stm32_comp_s *comp; + int ret; + + switch (intf) + { +#ifdef CONFIG_STM32_COMP1 + case 1: + ainfo("COMP1 selected\n"); + dev = &g_comp1dev; + break; +#endif + +#ifdef CONFIG_STM32_COMP2 + case 2: + ainfo("COMP2 selected\n"); + dev = &g_comp2dev; + break; +#endif + +#ifdef CONFIG_STM32_COMP3 + case 3: + ainfo("COMP3 selected\n"); + dev = &g_comp3dev; + break; +#endif + +#ifdef CONFIG_STM32_COMP4 + case 4: + ainfo("COMP4 selected\n"); + dev = &g_comp4dev; + break; +#endif + +#ifdef CONFIG_STM32_COMP5 + case 5: + ainfo("COMP5 selected\n"); + dev = &g_comp5dev; + break; +#endif + +#ifdef CONFIG_STM32_COMP6 + case 6: + ainfo("COMP6 selected\n"); + dev = &g_comp6dev; + break; +#endif + +#ifdef CONFIG_STM32_COMP7 + case 7: + ainfo("COMP7 selected\n"); + dev = &g_comp7dev; + break; +#endif + + default: + aerr("ERROR: No COMP interface defined\n"); + return NULL; + } + + /* Configure selected comparator */ + + comp = dev->ad_priv; + + ret = comp_config(comp); + if (ret < 0) + { + aerr("ERROR: Failed to initialize COMP%d: %d\n", intf, ret); + return NULL; + } + + return dev; +} + +#endif /* CONFIG_STM32_COMP */ diff --git a/arch/arm/src/common/stm32/stm32_cordic.h b/arch/arm/src/common/stm32/stm32_cordic.h new file mode 100644 index 0000000000000..aa536a50f26a7 --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_cordic.h @@ -0,0 +1,38 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_cordic.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_COMPAT_STM32CORDIC_H +#define __ARCH_ARM_SRC_COMMON_COMPAT_STM32CORDIC_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#if defined(CONFIG_STM32_HAVE_IP_CORDIC_M3M4_V1) +# include "stm32_cordic_m3m4_v1.h" +#else +# error "Unsupported STM32 stm32_cordic" +#endif + +#endif /* __ARCH_ARM_SRC_COMMON_COMPAT_STM32CORDIC_H */ diff --git a/arch/arm/src/common/stm32/stm32_cordic_m3m4_v1.c b/arch/arm/src/common/stm32/stm32_cordic_m3m4_v1.c new file mode 100644 index 0000000000000..e77afc841a1c4 --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_cordic_m3m4_v1.c @@ -0,0 +1,332 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_cordic_m3m4_v1.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include + +#include "arm_internal.h" +#include "chip.h" + +#include "hardware/stm32g4xxxx_cordic.h" + +#include "stm32_cordic_m3m4_v1.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define STM32_CORDIC_PRECISION (3) +#define STM32_CORDIC_ARGSIZE (0) /* Argument size is 32-bit */ +#define STM32_CORDIC_RESSIZE (0) /* Result size is 32-bit */ + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/* This structure represents the state of one PWM timer */ + +struct stm32_cordic_s +{ + const struct cordic_ops_s *ops; /* Lower half operations */ + uint32_t base; /* The base address of the CORDIC */ + bool inuse; /* True: driver is in-use */ +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/* Register access */ + +static uint32_t cordic_getreg(struct stm32_cordic_s *priv, int offset); +static void cordic_putreg(struct stm32_cordic_s *priv, int offset, + uint32_t value); + +/* Ops */ + +int cordic_calc(struct cordic_lowerhalf_s *lower, + struct cordic_calc_s *calc); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* STM32 specific CORDIC ops */ + +struct cordic_ops_s g_stm32_cordic_ops = +{ + .calc = cordic_calc +}; + +/* STM32 CORDIC device */ + +struct stm32_cordic_s g_stm32_cordic_dev = +{ + .ops = &g_stm32_cordic_ops, + .base = STM32_CORDIC_BASE, + .inuse = false +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: cordic_getreg + ****************************************************************************/ + +static uint32_t cordic_getreg(struct stm32_cordic_s *priv, int offset) +{ + return getreg32(priv->base + offset); +} + +/**************************************************************************** + * Name: cordic_putreg + ****************************************************************************/ + +static void cordic_putreg(struct stm32_cordic_s *priv, int offset, + uint32_t value) +{ + putreg32(value, priv->base + offset); +} + +/**************************************************************************** + * Name: cordic_calc + ****************************************************************************/ + +int cordic_calc(struct cordic_lowerhalf_s *lower, + struct cordic_calc_s *calc) +{ + struct stm32_cordic_s *priv = (struct stm32_cordic_s *)lower; + int ret = OK; + uint32_t csr = 0; + bool arg2_inc = false; + uint8_t scale = 0; + + DEBUGASSERT(lower); + DEBUGASSERT(calc); + + /* Configure CORDIC function */ + + switch (calc->func) + { + case CORDIC_CALC_FUNC_COS: + { + csr |= CORDIC_CSR_FUNC_COS; + arg2_inc = true; + scale = 0; + break; + } + + case CORDIC_CALC_FUNC_SIN: + { + csr |= CORDIC_CSR_FUNC_SIN; + arg2_inc = true; + scale = 0; + break; + } + + case CORDIC_CALC_FUNC_PHASE: + { + csr |= CORDIC_CSR_FUNC_PHASE; + arg2_inc = true; + scale = 0; + break; + } + + case CORDIC_CALC_FUNC_MOD: + { + csr |= CORDIC_CSR_FUNC_MOD; + arg2_inc = true; + scale = 0; + break; + } + + case CORDIC_CALC_FUNC_ARCTAN: + { + csr |= CORDIC_CSR_FUNC_ARCTAN; + arg2_inc = true; + scale = 0; + break; + } + + case CORDIC_CALC_FUNC_HCOS: + { + csr |= CORDIC_CSR_FUNC_HCOS; + arg2_inc = false; + scale = 1; + break; + } + + case CORDIC_CALC_FUNC_HSIN: + { + csr |= CORDIC_CSR_FUNC_HSIN; + arg2_inc = false; + scale = 1; + break; + } + + case CORDIC_CALC_FUNC_HARCTAN: + { + csr |= CORDIC_CSR_FUNC_HARCTAN; + arg2_inc = false; + scale = 1; + break; + } + + case CORDIC_CALC_FUNC_LN: + { + csr |= CORDIC_CSR_FUNC_LN; + arg2_inc = false; + scale = 1; + break; + } + + case CORDIC_CALC_FUNC_SQRT: + { + csr |= CORDIC_CSR_FUNC_SQRT; + arg2_inc = false; + scale = 1; + break; + } + + default: + { + ret = -EINVAL; + goto errout; + } + } + + /* Configure precision */ + + csr |= ((STM32_CORDIC_PRECISION << CORDIC_CSR_PRECISION_SHIFT) & + CORDIC_CSR_PRECISION_MASK); + + /* Configure scale */ + + csr |= ((scale << CORDIC_CSR_SCALE_SHIFT) & CORDIC_CSR_SCALE_MASK); + + /* Configure width of output data */ + + csr |= STM32_CORDIC_RESSIZE; + + /* Configure width of input data */ + + csr |= STM32_CORDIC_ARGSIZE; + + /* Include secondary argument */ + + if (arg2_inc == true) + { + csr |= CORDIC_CSR_NARGS; + } + + /* Include secondary result */ + + if (calc->res2_incl == true) + { + csr |= CORDIC_CSR_NRES; + } + + /* Write CSR */ + + cordic_putreg(priv, STM32_CORDIC_CSR_OFFSET, csr); + + /* Write arguments */ + + cordic_putreg(priv, STM32_CORDIC_WDATA_OFFSET, calc->arg1); + + if (arg2_inc == true) + { + cordic_putreg(priv, STM32_CORDIC_WDATA_OFFSET, calc->arg2); + } + + /* Read results - blocking. + * NOTE: We don't need to wait for RRDY flag as wait states are + * inserted automatically on RDATA read. + */ + + calc->res1 = cordic_getreg(priv, STM32_CORDIC_RDATA_OFFSET); + + if (calc->res2_incl == true) + { + calc->res2 = cordic_getreg(priv, STM32_CORDIC_RDATA_OFFSET); + } + else + { + calc->res2 = 0; + } + +errout: + return ret; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_cordicinitialize + * + * Description: + * Initialize a CORDIC device. This function must be called + * from board-specific logic. + * + * Returned Value: + * On success, a pointer to the lower half CORDIC driver is returned. + * NULL is returned on any failure. + * + ****************************************************************************/ + +struct cordic_lowerhalf_s *stm32_cordicinitialize(void) +{ + struct cordic_lowerhalf_s *lower = NULL; + + if (g_stm32_cordic_dev.inuse == true) + { + _err("STM32 CORDIC device already in use\n"); + set_errno(EBUSY); + goto errout; + } + + /* Get lower-half device */ + + lower = (struct cordic_lowerhalf_s *) &g_stm32_cordic_dev; + + /* The driver is now in-use */ + + g_stm32_cordic_dev.inuse = true; + +errout: + return lower; +} diff --git a/arch/arm/src/common/stm32/stm32_cordic_m3m4_v1.h b/arch/arm/src/common/stm32/stm32_cordic_m3m4_v1.h new file mode 100644 index 0000000000000..84328ab75c101 --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_cordic_m3m4_v1.h @@ -0,0 +1,57 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_cordic_m3m4_v1.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_CORDIC_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_CORDIC_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "chip.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_cordicinitialize + * + * Description: + * Initialize a CORDIC device. This function must be called + * from board-specific logic. + * + * Returned Value: + * On success, a pointer to the lower half CORDIC driver is returned. + * NULL is returned on any failure. + * + ****************************************************************************/ + +struct cordic_lowerhalf_s *stm32_cordicinitialize(void); + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_CORDIC_H */ diff --git a/arch/arm/src/common/stm32/stm32_crypto_m3m4_v1.c b/arch/arm/src/common/stm32/stm32_crypto_m3m4_v1.c new file mode 100644 index 0000000000000..8a88cff4803ae --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_crypto_m3m4_v1.c @@ -0,0 +1,154 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_crypto_m3m4_v1.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include +#include +#include + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static uint32_t g_stm32_sesnum = 0; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_newsession + * + * Description: + * create new session for crypto. + * + ****************************************************************************/ + +static int stm32_newsession(uint32_t *sid, struct cryptoini *cri) +{ + if (sid == NULL || cri == NULL) + { + return -EINVAL; + } + + switch (cri->cri_alg) + { + case CRYPTO_AES_CBC: + *sid = g_stm32_sesnum++; + break; + case CRYPTO_AES_CTR: + if ((cri->cri_klen / 8 - 4) != 16) + { + /* stm32 aes-ctr key bits just support 128 */ + + return -EINVAL; + } + + *sid = g_stm32_sesnum++; + break; + default: + return -EINVAL; + } + + return OK; +} + +/**************************************************************************** + * Name: stm32_freesession + * + * Description: + * free session. + * + ****************************************************************************/ + +static int stm32_freesession(uint64_t tid) +{ + return 0; +} + +/**************************************************************************** + * Name: stm32_process + * + * Description: + * process session to use hardware algorithm. + * + ****************************************************************************/ + +static int stm32_process(struct cryptop *crp) +{ + struct cryptodesc *crd; + uint8_t iv[AESCTR_BLOCKSIZE]; + + for (crd = crp->crp_desc; crd; crd = crd->crd_next) + { + switch (crd->crd_alg) + { + case CRYPTO_AES_CBC: + return aes_cypher(crp->crp_dst, crp->crp_buf, crd->crd_len, + crd->crd_iv, crd->crd_key, 16, + AES_MODE_CBC, crd->crd_flags & CRD_F_ENCRYPT); + case CRYPTO_AES_CTR: + + memcpy(iv, crd->crd_key + crd->crd_klen / 8 - AESCTR_NONCESIZE, + AESCTR_NONCESIZE); + memcpy(iv + AESCTR_NONCESIZE, crd->crd_iv, AESCTR_IVSIZE); + memset(iv + AESCTR_NONCESIZE + AESCTR_IVSIZE , 0, 4); + + return aes_cypher(crp->crp_dst, crp->crp_buf, crd->crd_len, + iv, crd->crd_key, crd->crd_klen / 8 - 4, + AES_MODE_CTR, crd->crd_flags & CRD_F_ENCRYPT); + default: + return -EINVAL; + } + } +} + +/**************************************************************************** + * Name: hwcr_init + * + * Description: + * register the hardware crypto driver. + * + ****************************************************************************/ + +void hwcr_init(void) +{ + int hwcr_id; + int algs[CRYPTO_ALGORITHM_MAX + 1]; + + hwcr_id = crypto_get_driverid(0); + DEBUGASSERT(hwcr_id >= 0); + + memset(algs, 0, sizeof(algs)); + + algs[CRYPTO_AES_CBC] = CRYPTO_ALG_FLAG_SUPPORTED; + algs[CRYPTO_AES_CTR] = CRYPTO_ALG_FLAG_SUPPORTED; + + crypto_register(hwcr_id, algs, stm32_newsession, + stm32_freesession, stm32_process); +} diff --git a/arch/arm/src/common/stm32/stm32_dac.h b/arch/arm/src/common/stm32/stm32_dac.h new file mode 100644 index 0000000000000..192a666ec9346 --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_dac.h @@ -0,0 +1,39 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_dac.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_COMPAT_STM32DAC_H +#define __ARCH_ARM_SRC_COMMON_COMPAT_STM32DAC_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#if defined(CONFIG_STM32_HAVE_IP_DAC_M3M4_V1) || \ + defined(CONFIG_STM32_HAVE_IP_DAC_M3M4_V2) +# include "stm32_dac_m3m4_v1.h" +#else +# error "Unsupported STM32 stm32_dac" +#endif + +#endif /* __ARCH_ARM_SRC_COMMON_COMPAT_STM32DAC_H */ diff --git a/arch/arm/src/common/stm32/stm32_dac_m3m4_v1.c b/arch/arm/src/common/stm32/stm32_dac_m3m4_v1.c new file mode 100644 index 0000000000000..c9cb731658fb6 --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_dac_m3m4_v1.c @@ -0,0 +1,1800 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_dac_m3m4_v1.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include "arm_internal.h" +#include "chip.h" +#include "stm32.h" +#include "stm32_dac_m3m4_v1.h" +#include "stm32_rcc.h" +#include "stm32_dma.h" +#include "stm32_syscfg.h" + +#ifdef CONFIG_DAC + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* RCC reset ****************************************************************/ + +#if defined(HAVE_IP_DAC_V1) +# define STM32_RCC_RSTR STM32_RCC_APB1RSTR +# define RCC_RSTR_DAC1RST RCC_APB1RSTR_DAC1RST +# define RCC_RSTR_DAC2RST RCC_APB1RSTR_DAC2RST +#elif defined(HAVE_IP_DAC_V2) +# define STM32_RCC_RSTR STM32_RCC_AHB2RSTR +# define RCC_RSTR_DAC1RST RCC_AHB2RSTR_DAC1RST +# define RCC_RSTR_DAC2RST RCC_AHB2RSTR_DAC2RST +# define RCC_RSTR_DAC3RST RCC_AHB2RSTR_DAC3RST +# define RCC_RSTR_DAC4RST RCC_AHB2RSTR_DAC4RST +#endif + +/* Configuration ************************************************************/ + +/* Up to 2 DAC interfaces for up to 3 channels are supported + * + * NOTE: STM32_NDAC tells how many channels chip supports. + * ST is not consistent in the naming of DAC interfaces, so we + * introduce our own naming convention. We distinguish DAC1 and DAC2 + * only if the chip has two separate areas in memory map to support DAC + * channels. + */ + +#if STM32_NDAC < 3 +# warning +# undef CONFIG_STM32_DAC2CH1 +# undef CONFIG_STM32_DAC2CH1_DMA +# undef CONFIG_STM32_DAC2CH1_TIMER +# undef CONFIG_STM32_DAC2CH1_TIMER_FREQUENCY +#endif + +#if STM32_NDAC < 2 +# warning +# undef CONFIG_STM32_DAC1CH2 +# undef CONFIG_STM32_DAC1CH2_DMA +# undef CONFIG_STM32_DAC1CH2_TIMER +# undef CONFIG_STM32_DAC1CH2_TIMER_FREQUENCY +#endif + +#if STM32_NDAC < 1 +# warning +# undef CONFIG_STM32_DAC1CH1 +# undef CONFIG_STM32_DAC1CH1_DMA +# undef CONFIG_STM32_DAC1CH1_TIMER +# undef CONFIG_STM32_DAC1CH1_TIMER_FREQUENCY +#endif + +/* Sanity checking */ + +#ifdef CONFIG_STM32_DAC1 +# if !defined(CONFIG_STM32_DAC1CH1) && !defined(CONFIG_STM32_DAC1CH2) +# error "DAC1 enabled but no channel was selected" +# endif +#endif + +#ifdef CONFIG_STM32_DAC2 +# if !defined(CONFIG_STM32_DAC2CH1) +# error "DAC2 enabled but no channel was selected" +# endif +#endif + +#ifdef CONFIG_STM32_DAC3 +# if !defined(CONFIG_STM32_DAC3CH1) && !defined(CONFIG_STM32_DAC3CH2) +# error "DAC3 enabled but no channel was selected" +# endif +#endif + +#ifdef CONFIG_STM32_DAC4 +# if !defined(CONFIG_STM32_DAC4CH1) && !defined(CONFIG_STM32_DAC4CH2) +# error "DAC4 enabled but no channel was selected" +# endif +#endif + +/* DMA configuration. */ + +#if defined(CONFIG_STM32_DAC1CH1_DMA) || defined(CONFIG_STM32_DAC1CH2_DMA) || \ + defined(CONFIG_STM32_DAC2CH1_DMA) +# if defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F30XX) +# ifndef CONFIG_STM32_DMA2 +# warning "STM32 F1/F3 DAC DMA support requires CONFIG_STM32_DMA2" +# undef CONFIG_STM32_DAC1CH1_DMA +# undef CONFIG_STM32_DAC1CH2_DMA +# undef CONFIG_STM32_DAC2CH1_DMA +# endif +# elif defined(CONFIG_STM32_STM32F33XX) +# ifndef CONFIG_STM32_DMA1 +# warning "STM32 F334 DAC DMA support requires CONFIG_STM32_DMA1" +# undef CONFIG_STM32_DAC1CH1_DMA +# undef CONFIG_STM32_DAC1CH2_DMA +# undef CONFIG_STM32_DAC2CH1_DMA +# endif +# elif defined(CONFIG_STM32_HAVE_IP_DAC_M3M4_V1) +# ifndef CONFIG_STM32_DMA1 +# warning "STM32 F4 DAC DMA support requires CONFIG_STM32_DMA1" +# undef CONFIG_STM32_DAC1CH1_DMA +# undef CONFIG_STM32_DAC1CH2_DMA +# undef CONFIG_STM32_DAC2CH1_DMA +# endif +# else +# warning "No DAC DMA information for this STM32 family" +# undef CONFIG_STM32_DAC1CH1_DMA +# undef CONFIG_STM32_DAC1CH2_DMA +# undef CONFIG_STM32_DAC2CH1_DMA +# endif +#endif + +#if defined(CONFIG_STM32_DAC1CH1_HRTIM_TRG1) || defined(CONFIG_STM32_DAC1CH1_HRTIM_TRG2) +# define DAC1CH1_HRTIM +#endif +#if defined(CONFIG_STM32_DAC1CH2_HRTIM_TRG1) || defined(CONFIG_STM32_DAC1CH2_HRTIM_TRG2) +# define DAC1CH2_HRTIM +#endif +#if defined(CONFIG_STM32_DAC2CH1_HRTIM_TRG3) +# define DAC2CH1_HRTIM +#endif + +/* If DMA is selected, then a timer and output frequency must also be + * provided to support the DMA transfer. The DMA transfer could be + * supported by and EXTI trigger, but this feature is not currently + * supported by the driver. + */ + +#if defined(CONFIG_STM32_DAC1CH1_DMA) && !defined(DAC1CH1_HRTIM) && \ + !defined(CONFIG_STM32_DAC1CH1_DMA_EXTERNAL) +# if !defined(CONFIG_STM32_DAC1CH1_TIMER) +# warning "A timer number must be specified in CONFIG_STM32_DAC1CH1_TIMER" +# undef CONFIG_STM32_DAC1CH1_DMA +# undef CONFIG_STM32_DAC1CH1_TIMER_FREQUENCY +# elif !defined(CONFIG_STM32_DAC1CH1_TIMER_FREQUENCY) +# warning "A timer frequency must be specified in CONFIG_STM32_DAC1CH1_TIMER_FREQUENCY" +# undef CONFIG_STM32_DAC1CH1_DMA +# undef CONFIG_STM32_DAC1CH1_TIMER +# endif +#endif + +#if defined(CONFIG_STM32_DAC1CH2_DMA) && !defined(DAC1CH2_HRTIM) && \ + !defined(CONFIG_STM32_DAC1CH2_DMA_EXTERNAL) +# if !defined(CONFIG_STM32_DAC1CH2_TIMER) +# warning "A timer number must be specified in CONFIG_STM32_DAC1CH2_TIMER" +# undef CONFIG_STM32_DAC1CH2_DMA +# undef CONFIG_STM32_DAC1CH2_TIMER_FREQUENCY +# elif !defined(CONFIG_STM32_DAC1CH2_TIMER_FREQUENCY) +# warning "A timer frequency must be specified in CONFIG_STM32_DAC1CH2_TIMER_FREQUENCY" +# undef CONFIG_STM32_DAC1CH2_DMA +# undef CONFIG_STM32_DAC1CH2_TIMER +# endif +#endif + +#if defined(CONFIG_STM32_DAC2CH1_DMA) && !defined(DAC2CH1_HRTIM) && \ + !defined(CONFIG_STM32_DAC2CH1_DMA_EXTERNAL) +# if !defined(CONFIG_STM32_DAC2CH1_TIMER) +# warning "A timer number must be specified in CONFIG_STM32_DAC2CH1_TIMER" +# undef CONFIG_STM32_DAC2CH1_DMA +# undef CONFIG_STM32_DAC2CH1_TIMER_FREQUENCY +# elif !defined(CONFIG_STM32_DAC2CH1_TIMER_FREQUENCY) +# warning "A timer frequency must be specified in CONFIG_STM32_DAC2CH1_TIMER_FREQUENCY" +# undef CONFIG_STM32_DAC2CH1_DMA +# undef CONFIG_STM32_DAC2CH1_TIMER +# endif +#endif + +/* DMA **********************************************************************/ + +/* DMA channels and interface values differ for the F1 and F4 families */ + +#undef HAVE_DMA +#if defined(CONFIG_STM32_DAC1CH1_DMA) || defined(CONFIG_STM32_DAC1CH2_DMA) || \ + defined(CONFIG_STM32_DAC2CH1_DMA) +# if defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F30XX) || \ + defined(CONFIG_STM32_STM32F33XX) +# define HAVE_DMA 1 +# define DAC_DMA 2 +# if defined(CONFIG_STM32_DAC1CH1) && !defined(CONFIG_STM32_DAC1CH1_DMA_EXTERNAL) +# define DAC1CH1_DMA_CHAN DMACHAN_DAC1_CH1 +# endif +# if defined(CONFIG_STM32_DAC1CH2) && !defined(CONFIG_STM32_DAC1CH2_DMA_EXTERNAL) +# define DAC1CH2_DMA_CHAN DMACHAN_DAC1_CH2 +# endif +# if defined(CONFIG_STM32_DAC2CH1) && !defined(CONFIG_STM32_DAC2CH1_DMA_EXTERNAL) +# define DAC2CH1_DMA_CHAN DMACHAN_DAC2_CH1 +# endif +# elif defined(CONFIG_STM32_HAVE_IP_DAC_M3M4_V1) +# define HAVE_DMA 1 +# define DAC_DMA 1 +# if defined(CONFIG_STM32_DAC1CH1) && !defined(CONFIG_STM32_DAC1CH1_DMA_EXTERNAL) +# define DAC1CH1_DMA_CHAN DMAMAP_DAC1 +# endif +# if defined(CONFIG_STM32_DAC1CH2) && !defined(CONFIG_STM32_DAC1CH2_DMA_EXTERNAL) +# define DAC1CH2_DMA_CHAN DMAMAP_DAC1 +# endif +# if defined(CONFIG_STM32_DAC2CH1) && !defined(CONFIG_STM32_DAC2CH1_DMA_EXTERNAL) +# define DAC2CH1_DMA_CHAN DMAMAP_DAC2 +# endif +# endif +#endif + +/* Timer configuration. The STM32 supports 8 different trigger for DAC + * output: + * + * TSEL SOURCE DEVICES + * ---- ----------------------- ------------------------------------- + * 000 Timer 6 TRGO event ALL + * 001 Timer 3 TRGO event STM32 F1 Connectivity Line and STM32 F3 + * Timer 8 TRGO event Other STM32 F1 and all STM32 F4 + * 010 Timer 7 TRGO event ALL + * 011 Timer 5 TRGO event ALL + * Timer 15 TRGO event STM32 F3 + * HRTIM1_DACTRG1 event STM32F33XX (DAC1 only) + * 100 Timer 2 TRGO event ALL + * 101 Timer 4 TRGO event ALL + * HRTIM1_DACTRG2 event STM32F33XX (DAC1 only) + * HRTIM1_DACTRG3 event STM32F33XX (DAC2 only) + * 110 EXTI line9 ALL + * 111 SWTRIG Software control ALL + * + * This driver does not support the EXTI trigger. + */ + +/* DMA transfer from DMA buffer to DAC register can also be triggered by an + * external to the DAC block events. In this case, the DAC trigger (TEN bit) + * must be reset and board configuration must provide DACxCHy_DMA_CHAN. + */ + +#undef NEED_TIM6 +#undef NEED_TIM3 +#undef NEED_TIM8 +#undef NEED_TIM7 +#undef NEED_TIM5 +#undef NEED_TIM2 +#undef NEED_TIM4 + +#ifdef CONFIG_STM32_DAC1CH1_DMA +# if defined(CONFIG_STM32_DAC1CH1_DMA_EXTERNAL) +# elif defined(CONFIG_STM32_DAC1CH1_HRTIM_TRG1) +# ifndef CONFIG_STM32_HRTIM_DAC +# error "CONFIG_STM32_HRTIM_DAC required for DAC1CH1" +# endif +# define DAC1CH1_TSEL_VALUE DAC_CR_TSEL_HRT1TRG1 +# elif defined(CONFIG_STM32_DAC1CH1_HRTIM_TRG2) +# ifndef CONFIG_STM32_HRTIM_DAC +# error "CONFIG_STM32_HRTIM_DAC required for DAC1CH2" +# endif +# define DAC1CH1_TSEL_VALUE DAC_CR_TSEL_HRT1TRG2 +# elif CONFIG_STM32_DAC1CH1_TIMER == 6 +# ifndef CONFIG_STM32_TIM6_DAC +# error "CONFIG_STM32_TIM6_DAC required for DAC1CH1" +# endif +# define NEED_TIM6 +# define DAC1CH1_TSEL_VALUE DAC_CR_TSEL_TIM6 +# define DAC1CH1_TIMER_BASE STM32_TIM6_BASE +# define DAC1CH1_TIMER_PCLK_FREQUENCY STM32_PCLK1_FREQUENCY +# elif CONFIG_STM32_DAC1CH1_TIMER == 3 && defined(CONFIG_STM32_CONNECTIVITYLINE) +# ifndef CONFIG_STM32_TIM3_DAC +# error "CONFIG_STM32_TIM3_DAC required for DAC1CH1" +# endif +# define NEED_TIM3 +# define DAC1CH1_TSEL_VALUE DAC_CR_TSEL_TIM3 +# define DAC1CH1_TIMER_BASE STM32_TIM3_BASE +# define DAC1CH1_TIMER_PCLK_FREQUENCY STM32_PCLK1_FREQUENCY +# elif CONFIG_STM32_DAC1CH1_TIMER == 8 && !defined(CONFIG_STM32_CONNECTIVITYLINE) +# ifndef CONFIG_STM32_TIM8_DAC +# error "CONFIG_STM32_TIM8_DAC required for DAC1CH1" +# endif +# define NEED_TIM8 +# define DAC1CH1_TSEL_VALUE DAC_CR_TSEL_TIM8 +# define DAC1CH1_TIMER_BASE STM32_TIM8_BASE +# define DAC1CH1_TIMER_PCLK_FREQUENCY STM32_PCLK2_FREQUENCY +# elif CONFIG_STM32_DAC1CH1_TIMER == 7 +# ifndef CONFIG_STM32_TIM7_DAC +# error "CONFIG_STM32_TIM7_DAC required for DAC1CH1" +# endif +# define NEED_TIM7 +# define DAC1CH1_TSEL_VALUE DAC_CR_TSEL_TIM7 +# define DAC1CH1_TIMER_BASE STM32_TIM7_BASE +# elif CONFIG_STM32_DAC1CH1_TIMER == 5 +# ifndef CONFIG_STM32_TIM5_DAC +# error "CONFIG_STM32_TIM5_DAC required for DAC1CH1" +# endif +# define NEED_TIM5 +# define DAC1CH1_TSEL_VALUE DAC_CR_TSEL_TIM5 +# define DAC1CH1_TIMER_BASE STM32_TIM5_BASE +# define DAC1CH1_TIMER_PCLK_FREQUENCY STM32_PCLK1_FREQUENCY +# elif CONFIG_STM32_DAC1CH1_TIMER == 2 +# ifndef CONFIG_STM32_TIM2_DAC +# error "CONFIG_STM32_TIM2_DAC required for DAC1CH1" +# endif +# define NEED_TIM2 +# define DAC1CH1_TSEL_VALUE DAC_CR_TSEL_TIM2 +# define DAC1CH1_TIMER_BASE STM32_TIM2_BASE +# define DAC1CH1_TIMER_PCLK_FREQUENCY STM32_PCLK1_FREQUENCY +# elif CONFIG_STM32_DAC1CH1_TIMER == 4 +# ifndef CONFIG_STM32_TIM4_DAC +# error "CONFIG_STM32_TIM4_DAC required for DAC1CH1" +# endif +# define NEED_TIM4 +# define DAC1CH1_TSEL_VALUE DAC_CR_TSEL_TIM4 +# define DAC1CH1_TIMER_BASE STM32_TIM4_BASE +# define DAC1CH1_TIMER_PCLK_FREQUENCY STM32_PCLK1_FREQUENCY +# else +# error "Unsupported CONFIG_STM32_DAC1CH1_TIMER" +# endif +#else +# define DAC1CH1_TSEL_VALUE DAC_CR_TSEL_SW +#endif + +#if defined(NEED_TIM2) || defined(NEED_TIM3) || defined(NEED_TIM4) || \ + defined(NEED_TIM5) || defined(NEED_TIM6) || defined(NEED_TIM7) || \ + defined(NEED_TIM8) +# define HAVE_TIMER +#endif + +#ifdef CONFIG_STM32_DAC1CH2_DMA +# if defined(CONFIG_STM32_DAC1CH2_DMA_EXTERNAL) +# elif defined(CONFIG_STM32_DAC1CH2_HRTIM_TRG1) +# ifndef CONFIG_STM32_HRTIM_DAC +# error "CONFIG_STM32_HRTIM_DAC required for DAC1CH2" +# endif +# define DAC1CH2_TSEL_VALUE DAC_CR_TSEL_HRT1TRG1 +# elif defined(CONFIG_STM32_DAC1CH2_HRTIM_TRG2) +# ifndef CONFIG_STM32_HRTIM_DAC +# error "CONFIG_STM32_HRTIM_DAC required for DAC1CH2" +# endif +# define DAC1CH2_TSEL_VALUE DAC_CR_TSEL_HRT1TRG2 +# elif CONFIG_STM32_DAC1CH2_TIMER == 6 +# ifndef CONFIG_STM32_TIM6_DAC +# error "CONFIG_STM32_TIM6_DAC required for DAC1CH2" +# endif +# define DAC1CH2_TSEL_VALUE DAC_CR_TSEL_TIM6 +# define DAC1CH2_TIMER_BASE STM32_TIM6_BASE +# define DAC1CH2_TIMER_PCLK_FREQUENCY STM32_PCLK1_FREQUENCY +# elif CONFIG_STM32_DAC1CH2_TIMER == 3 && defined(CONFIG_STM32_CONNECTIVITYLINE) +# ifndef CONFIG_STM32_TIM3_DAC +# error "CONFIG_STM32_TIM3_DAC required for DAC1CH2" +# endif +# define DAC1CH2_TSEL_VALUE DAC_CR_TSEL_TIM3 +# define DAC1CH2_TIMER_BASE STM32_TIM3_BASE +# define DAC1CH2_TIMER_PCLK_FREQUENCY STM32_PCLK1_FREQUENCY +# elif CONFIG_STM32_DAC1CH2_TIMER == 8 && !defined(CONFIG_STM32_CONNECTIVITYLINE) +# ifndef CONFIG_STM32_TIM8_DAC +# error "CONFIG_STM32_TIM8_DAC required for DAC1CH2" +# endif +# define DAC1CH2_TSEL_VALUE DAC_CR_TSEL_TIM8 +# define DAC1CH2_TIMER_BASE STM32_TIM8_BASE +# define DAC1CH2_TIMER_PCLK_FREQUENCY STM32_PCLK2_FREQUENCY +# elif CONFIG_STM32_DAC1CH2_TIMER == 7 +# ifndef CONFIG_STM32_TIM7_DAC +# error "CONFIG_STM32_TIM7_DAC required for DAC1CH2" +# endif +# define DAC1CH2_TSEL_VALUE DAC_CR_TSEL_TIM7 +# define DAC1CH2_TIMER_BASE STM32_TIM7_BASE +# define DAC1CH2_TIMER_PCLK_FREQUENCY STM32_PCLK1_FREQUENCY +# elif CONFIG_STM32_DAC1CH2_TIMER == 5 +# ifndef CONFIG_STM32_TIM5_DAC +# error "CONFIG_STM32_TIM5_DAC required for DAC1CH2" +# endif +# define DAC1CH2_TSEL_VALUE DAC_CR_TSEL_TIM5 +# define DAC1CH2_TIMER_BASE STM32_TIM5_BASE +# define DAC1CH2_TIMER_PCLK_FREQUENCY STM32_PCLK1_FREQUENCY +# elif CONFIG_STM32_DAC1CH2_TIMER == 2 +# ifndef CONFIG_STM32_TIM2_DAC +# error "CONFIG_STM32_TIM2_DAC required for DAC1CH2" +# endif +# define DAC1CH2_TSEL_VALUE DAC_CR_TSEL_TIM2 +# define DAC1CH2_TIMER_BASE STM32_TIM2_BASE +# define DAC1CH2_TIMER_PCLK_FREQUENCY STM32_PCLK1_FREQUENCY +# elif CONFIG_STM32_DAC1CH2_TIMER == 4 +# ifndef CONFIG_STM32_TIM4_DAC +# error "CONFIG_STM32_TIM4_DAC required for DAC1CH2" +# endif +# define DAC1CH2_TSEL_VALUE DAC_CR_TSEL_TIM4 +# define DAC1CH2_TIMER_BASE STM32_TIM4_BASE +# define DAC1CH2_TIMER_PCLK_FREQUENCY STM32_PCLK1_FREQUENCY +# else +# error "Unsupported CONFIG_STM32_DAC1CH2_TIMER" +# endif +#else +# define DAC1CH2_TSEL_VALUE DAC_CR_TSEL_SW +#endif + +#ifdef CONFIG_STM32_DAC2CH1_DMA +# if defined(CONFIG_STM32_DAC2CH1_DMA_EXTERNAL) +# elif defined(CONFIG_STM32_DAC2CH1_HRTIM_TRG3) +# ifndef CONFIG_STM32_HRTIM_DAC +# error "CONFIG_STM32_HRTIM_DAC required for DAC2CH1" +# endif +# define DAC2CH1_TSEL_VALUE DAC_CR_TSEL_HRT1TRG3 +# elif CONFIG_STM32_DAC2CH1_TIMER == 6 +# ifndef CONFIG_STM32_TIM6_DAC +# error "CONFIG_STM32_TIM6_DAC required for DAC2CH1" +# endif +# define DAC2CH1_TSEL_VALUE DAC_CR_TSEL_TIM6 +# define DAC2CH1_TIMER_BASE STM32_TIM6_BASE +# define DAC2CH1_TIMER_PCLK_FREQUENCY STM32_PCLK1_FREQUENCY +# elif CONFIG_STM32_DAC2CH1_TIMER == 3 && defined(CONFIG_STM32_CONNECTIVITYLINE) +# ifndef CONFIG_STM32_TIM3_DAC +# error "CONFIG_STM32_TIM3_DAC required for DAC2CH1" +# endif +# define DAC2CH1_TSEL_VALUE DAC_CR_TSEL_TIM3 +# define DAC2CH1_TIMER_BASE STM32_TIM3_BASE +# define DAC2CH1_TIMER_PCLK_FREQUENCY STM32_PCLK1_FREQUENCY +# elif CONFIG_STM32_DAC2CH1_TIMER == 8 && !defined(CONFIG_STM32_CONNECTIVITYLINE) +# ifndef CONFIG_STM32_TIM8_DAC +# error "CONFIG_STM32_TIM8_DAC required for DAC2CH1" +# endif +# define DAC2CH1_TSEL_VALUE DAC_CR_TSEL_TIM8 +# define DAC2CH1_TIMER_BASE STM32_TIM8_BASE +# define DAC2CH1_TIMER_PCLK_FREQUENCY STM32_PCLK2_FREQUENCY +# elif CONFIG_STM32_DAC2CH1_TIMER == 7 +# ifndef CONFIG_STM32_TIM7_DAC +# error "CONFIG_STM32_TIM7_DAC required for DAC2CH1" +# endif +# define DAC2CH1_TSEL_VALUE DAC_CR_TSEL_TIM7 +# define DAC2CH1_TIMER_BASE STM32_TIM7_BASE +# define DAC2CH1_TIMER_PCLK_FREQUENCY STM32_PCLK1_FREQUENCY +# elif CONFIG_STM32_DAC2CH1_TIMER == 5 +# ifndef CONFIG_STM32_TIM5_DAC +# error "CONFIG_STM32_TIM5_DAC required for DAC2CH1" +# endif +# define DAC2CH1_TSEL_VALUE DAC_CR_TSEL_TIM5 +# define DAC2CH1_TIMER_BASE STM32_TIM5_BASE +# define DAC2CH1_TIMER_PCLK_FREQUENCY STM32_PCLK1_FREQUENCY +# elif CONFIG_STM32_DAC2CH1_TIMER == 2 +# ifndef CONFIG_STM32_TIM2_DAC +# error "CONFIG_STM32_TIM2_DAC required for DAC2CH1" +# endif +# define DAC2CH1_TSEL_VALUE DAC_CR_TSEL_TIM2 +# define DAC2CH1_TIMER_BASE STM32_TIM2_BASE +# define DAC2CH1_TIMER_PCLK_FREQUENCY STM32_PCLK1_FREQUENCY +# elif CONFIG_STM32_DAC2CH1_TIMER == 4 +# ifndef CONFIG_STM32_TIM4_DAC +# error "CONFIG_STM32_TIM4_DAC required for DAC2CH1" +# endif +# define DAC2CH1_TSEL_VALUE DAC_CR_TSEL_TIM4 +# define DAC2CH1_TIMER_BASE STM32_TIM4_BASE +# define DAC2CH1_TIMER_PCLK_FREQUENCY STM32_PCLK1_FREQUENCY +# else +# error "Unsupported CONFIG_STM32_DAC2CH1_TIMER" +# endif +#else +# define DAC2CH1_TSEL_VALUE DAC_CR_TSEL_SW +#endif + +/* We need index which describes when HRTIM is selected as trigger. + * It will be used to skip timer configuration where needed. + */ + +#define TIM_INDEX_HRTIM 255 + +#if defined(DAC1CH1_HRTIM) || defined(DAC1CH2_HRTIM) || defined(DAC2CH1_HRTIM) +# define HAVE_HRTIM +#endif + +/* DMA buffers default size */ + +#if !defined(CONFIG_STM32_DAC1CH1_DMA_BUFFER_SIZE) && defined(CONFIG_STM32_DAC1CH1_DMA) +# error "DAC1CH1 buffer size must be provided" +#endif +#if !defined(CONFIG_STM32_DAC1CH2_DMA_BUFFER_SIZE) && defined(CONFIG_STM32_DAC1CH2_DMA) +# error "DAC1CH2 buffer size must be provided" +#endif +#if !defined(CONFIG_STM32_DAC2CH1_DMA_BUFFER_SIZE) && defined(CONFIG_STM32_DAC2CH1_DMA) +# error "DAC2CH1 buffer size must be provided" +#endif + +/* Calculate timer divider values based upon DACn_TIMER_PCLK_FREQUENCY and + * CONFIG_STM32_DACn_TIMER_FREQUENCY. + */ + +#warning "Missing Logic" + +/* DMA stream/channel configuration. The register layout depends on the DMA + * IP version, not the DAC IP version: stream DMA (IPv2) uses the SCR + * register fields, while channel DMA (IPv1) uses the CCR register fields. + */ + +#if defined(CONFIG_STM32_HAVE_IP_DMA_V2) +# define DAC_DMA_CONTROL_WORD (DMA_SCR_MSIZE_16BITS | \ + DMA_SCR_PSIZE_16BITS | \ + DMA_SCR_MINC | \ + DMA_SCR_CIRC | \ + DMA_SCR_DIR_M2P) +#else +# define DAC_DMA_CONTROL_WORD (DMA_CCR_MSIZE_16BITS | \ + DMA_CCR_PSIZE_16BITS | \ + DMA_CCR_MINC | \ + DMA_CCR_CIRC | \ + DMA_CCR_DIR) +#endif + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/* This structure represents the internal state of the single STM32 DAC + * block + */ + +struct stm32_dac_s +{ + uint8_t init : 1; /* True, the DAC block has been initialized */ +}; + +/* This structure represents the internal state of one STM32 DAC channel */ + +struct stm32_chan_s +{ + uint8_t inuse : 1; /* True, the driver is in use and not available */ +#ifdef HAVE_DMA + uint8_t hasdma : 1; /* True, this channel supports DMA */ + uint8_t text : 1; /* True, DMA triggering from external source */ + uint8_t timer; /* Timer number 2-8 */ +#endif + uint8_t intf; /* DAC zero-based interface number (0 or 1) */ + uint32_t pin; /* Pin configuration */ +#ifdef HAVE_IP_DAC_V2 + uint32_t mode; /* DAC channel mode */ +#endif + uint32_t dro; /* Data output register */ + uint32_t cr; /* Control register */ + uint32_t tsel; /* CR trigger select value */ +#ifdef HAVE_IP_DAC_V2 + uint32_t sr; /* Status register */ + uint32_t mcr; /* Mode Control register */ +#endif +#ifdef HAVE_DMA + uint16_t dmachan; /* DMA channel needed by this DAC */ + uint16_t buffer_len; /* DMA buffer length */ + DMA_HANDLE dma; /* Allocated DMA channel */ +# ifdef HAVE_TIMER + uint32_t tbase; /* Timer base address */ + uint32_t tfrequency; /* Timer frequency */ +# endif + uint16_t *dmabuffer; /* DMA transfer buffer */ +#endif +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/* DAC Register access */ + +#ifdef HAVE_TIMER +static uint32_t tim_getreg(struct stm32_chan_s *chan, int offset); +static void tim_putreg(struct stm32_chan_s *chan, int offset, + uint32_t value); +static void tim_modifyreg(struct stm32_chan_s *chan, int offset, + uint32_t clearbits, uint32_t setbits); +#endif + +/* Interrupt handler */ + +#if 0 /* defined(CONFIG_STM32_HAVE_IP_DAC_M3M4_V1) */ +static int dac_interrupt(int irq, void *context, void *arg); +#endif + +/* DAC methods */ + +static void dac_reset(struct dac_dev_s *dev); +static int dac_setup(struct dac_dev_s *dev); +static void dac_shutdown(struct dac_dev_s *dev); +static void dac_txint(struct dac_dev_s *dev, bool enable); +static int dac_send(struct dac_dev_s *dev, struct dac_msg_s *msg); +static int dac_ioctl(struct dac_dev_s *dev, int cmd, unsigned long arg); + +/* Initialization */ + +#ifdef HAVE_DMA +# ifdef HAVE_TIMER +static int dac_timinit(struct stm32_chan_s *chan); +# endif +static int dma_remap(struct stm32_chan_s *chan); +static void dma_bufferinit(struct stm32_chan_s *chan, uint16_t *buffer, + uint16_t len); +#endif +static int dac_chaninit(struct stm32_chan_s *chan); +static int dac_blockinit(void); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static const struct dac_ops_s g_dacops = +{ + .ao_reset = dac_reset, + .ao_setup = dac_setup, + .ao_shutdown = dac_shutdown, + .ao_txint = dac_txint, + .ao_send = dac_send, + .ao_ioctl = dac_ioctl, +}; + +#ifdef CONFIG_STM32_DAC1 +#ifdef CONFIG_STM32_DAC1CH1 +/* Channel 1: DAC1 channel 1 */ + +#ifdef CONFIG_STM32_DAC1CH1_DMA +uint16_t dac1ch1_buffer[CONFIG_STM32_DAC1CH1_DMA_BUFFER_SIZE]; +#endif + +static struct stm32_chan_s g_dac1ch1priv = +{ + .intf = 0, + .pin = GPIO_DAC1_OUT1, +#ifdef HAVE_IP_DAC_V2 + .mode = CONFIG_STM32_DAC1CH1_MODE; +#endif + .dro = STM32_DAC1_DHR12R1, + .cr = STM32_DAC1_CR, +#ifdef HAVE_IP_DAC_V2 + .sr = STM32_DAC1_SR, + .mcr = STM32_DAC1_MCR, +#endif +#ifdef CONFIG_STM32_DAC1CH1_DMA + .hasdma = 1, + .dmachan = DAC1CH1_DMA_CHAN, + .buffer_len = CONFIG_STM32_DAC1CH1_DMA_BUFFER_SIZE, + .dmabuffer = dac1ch1_buffer, +# ifdef CONFIG_STM32_DAC1CH1_DMA_EXTERNAL + .text = 1, +# else + .text = 0, + .tsel = DAC1CH1_TSEL_VALUE, +# ifdef DAC1CH1_HRTIM + .timer = TIM_INDEX_HRTIM, +# else + .timer = CONFIG_STM32_DAC1CH1_TIMER, + .tbase = DAC1CH1_TIMER_BASE, + .tfrequency = CONFIG_STM32_DAC1CH1_TIMER_FREQUENCY, +# endif +# endif +#endif +}; + +static struct dac_dev_s g_dac1ch1dev = +{ + .ad_ops = &g_dacops, + .ad_priv = &g_dac1ch1priv, +}; +#endif /* CONFIG_STM32_DAC1CH1 */ + +#ifdef CONFIG_STM32_DAC1CH2 +/* Channel 2: DAC1 channel 2 */ + +#ifdef CONFIG_STM32_DAC1CH2_DMA +uint16_t dac1ch2_buffer[CONFIG_STM32_DAC1CH2_DMA_BUFFER_SIZE]; +#endif + +static struct stm32_chan_s g_dac1ch2priv = +{ + .intf = 1, + .pin = GPIO_DAC1_OUT2, +#ifdef HAVE_IP_DAC_V2 + .mode = CONFIG_STM32_DAC1CH2_MODE << 16; +#endif + .dro = STM32_DAC1_DHR12R2, + .cr = STM32_DAC1_CR, +#ifdef HAVE_IP_DAC_V2 + .sr = STM32_DAC1_SR, + .mcr = STM32_DAC1_MCR, +#endif +#ifdef CONFIG_STM32_DAC1CH2_DMA + .hasdma = 1, + .dmachan = DAC1CH2_DMA_CHAN, + .buffer_len = CONFIG_STM32_DAC1CH2_DMA_BUFFER_SIZE, + .dmabuffer = dac1ch2_buffer, +# ifdef CONFIG_STM32_DAC1CH2_DMA_EXTERNAL + .text = 1, +# else + .text = 0, + .tsel = DAC1CH2_TSEL_VALUE, +# ifdef DAC1CH2_HRTIM + .timer = TIM_INDEX_HRTIM, +# else + .timer = CONFIG_STM32_DAC1CH2_TIMER, + .tbase = DAC1CH2_TIMER_BASE, + .tfrequency = CONFIG_STM32_DAC1CH2_TIMER_FREQUENCY, +# endif +# endif +#endif +}; + +static struct dac_dev_s g_dac1ch2dev = +{ + .ad_ops = &g_dacops, + .ad_priv = &g_dac1ch2priv, +}; +#endif /* CONFIG_STM32_DAC1CH2 */ + +#endif /* CONFIG_STM32_DAC1 */ + +#ifdef CONFIG_STM32_DAC2 +#ifdef CONFIG_STM32_DAC2CH1 +/* Channel 3: DAC2 channel 1 */ + +#ifdef CONFIG_STM32_DAC2CH1_DMA +uint16_t dac2ch1_buffer[CONFIG_STM32_DAC2CH1_DMA_BUFFER_SIZE]; +#endif + +static struct stm32_chan_s g_dac2ch1priv = +{ + .intf = 2, + .pin = GPIO_DAC2_OUT1, +#ifdef HAVE_IP_DAC_V2 + .mode = CONFIG_STM32_DAC2CH1_MODE; +#endif + .dro = STM32_DAC2_DHR12R1, + .cr = STM32_DAC2_CR, +#ifdef HAVE_IP_DAC_V2 + .sr = STM32_DAC2_SR, + .mcr = STM32_DAC2_MCR, +#endif +#ifdef CONFIG_STM32_DAC2CH1_DMA + .hasdma = 1, + .dmachan = DAC2CH1_DMA_CHAN, + .buffer_len = CONFIG_STM32_DAC2CH1_DMA_BUFFER_SIZE, + .dmabuffer = dac2ch1_buffer, +# ifdef CONFIG_STM32_DAC2CH1_DMA_EXTERNAL + .text = 1, +# else + .text = 0, + .tsel = DAC2CH1_TSEL_VALUE, +# ifdef DAC2CH1_HRTIM + .timer = TIM_INDEX_HRTIM, +# else + .timer = CONFIG_STM32_DAC2CH1_TIMER, + .tbase = DAC2CH1_TIMER_BASE, + .tfrequency = CONFIG_STM32_DAC2CH1_TIMER_FREQUENCY, +# endif +# endif +#endif +}; + +static struct dac_dev_s g_dac2ch1dev = +{ + .ad_ops = &g_dacops, + .ad_priv = &g_dac2ch1priv, +}; +#endif /* CONFIG_STM32_DAC2CH1 */ +#endif /* CONFIG_STM32_DAC2 */ + +#ifdef CONFIG_STM32_DAC3 +#ifdef CONFIG_STM32_DAC3CH1 +/* Channel 4: DAC3 channel 1 */ + +#ifdef CONFIG_STM32_DAC3CH1_DMA +# error "STM32_DAC3 DMA not supported" +#endif + +static struct stm32_chan_s g_dac3ch1priv = +{ + .intf = 4, + .dro = STM32_DAC3_DHR12R1, +#ifdef HAVE_IP_DAC_V2 + .mode = CONFIG_STM32_DAC3CH1_MODE; +#endif + .cr = STM32_DAC3_CR, +#ifdef HAVE_IP_DAC_V2 + .sr = STM32_DAC3_SR, + .mcr = STM32_DAC3_MCR, +#endif +}; + +static struct dac_dev_s g_dac3ch1dev = +{ + .ad_ops = &g_dacops, + .ad_priv = &g_dac3ch1priv, +}; +#endif /* CONFIG_STM32_DAC3CH1 */ + +#ifdef CONFIG_STM32_DAC3CH2 +/* Channel 5: DAC3 channel 1 */ + +#ifdef CONFIG_STM32_DAC3CH2_DMA +# error "STM32_DAC3 DMA not supported" +#endif + +static struct stm32_chan_s g_dac3ch2priv = +{ + .intf = 5, + .dro = STM32_DAC3_DHR12R2, +#ifdef HAVE_IP_DAC_V2 + .mode = CONFIG_STM32_DAC3CH2_MODE << 16, +#endif + .cr = STM32_DAC3_CR, +#ifdef HAVE_IP_DAC_V2 + .sr = STM32_DAC3_SR, + .mcr = STM32_DAC3_MCR, +#endif +}; + +static struct dac_dev_s g_dac3ch2dev = +{ + .ad_ops = &g_dacops, + .ad_priv = &g_dac3ch2priv, +}; +#endif /* CONFIG_STM32_DAC3CH2 */ +#endif /* CONFIG_STM32_DAC3 */ + +static struct stm32_dac_s g_dacblock; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_dac_modify_cr + * + * Description: + * Modify the contents of the DAC control register. + * + * Input Parameters: + * priv - Driver state instance + * clearbits - Bits in the control register to be cleared + * setbits - Bits in the control register to be set + * + * Returned Value: + * None + * + ****************************************************************************/ + +static inline void stm32_dac_modify_cr(struct stm32_chan_s *chan, + uint32_t clearbits, uint32_t setbits) +{ + unsigned int shift; + + /* DAC1 channels 1 and 2 share the STM32_DAC[1]_CR control register. DAC2 + * channel 1 (and perhaps channel 2) uses the STM32_DAC2_CR control + * register. In either case, bit 0 of the interface number provides the + * correct shift. + * + * Bit 0 = 0: Shift = 0 + * Bit 0 = 1: Shift = 16 + */ + + shift = (chan->intf & 1) << 4; + modifyreg32(chan->cr, clearbits << shift, setbits << shift); +} + +#ifdef HAVE_TIMER + +/**************************************************************************** + * Name: tim_getreg + * + * Description: + * Read the value of an DMA timer register. + * + * Input Parameters: + * chan - A reference to the DAC block status + * offset - The offset to the register to read + * + * Returned Value: + * The current contents of the specified register + * + ****************************************************************************/ + +static uint32_t tim_getreg(struct stm32_chan_s *chan, int offset) +{ + return getreg32(chan->tbase + offset); +} + +/**************************************************************************** + * Name: tim_putreg + * + * Description: + * Read the value of an DMA timer register. + * + * Input Parameters: + * chan - A reference to the DAC block status + * offset - The offset to the register to read + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void tim_putreg(struct stm32_chan_s *chan, int offset, + uint32_t value) +{ + putreg32(value, chan->tbase + offset); +} + +/**************************************************************************** + * Name: tim_modifyreg + * + * Description: + * Modify the value of an DMA timer register. + * + * Input Parameters: + * priv - Driver state instance + * offset - The timer register offset + * clearbits - Bits in the control register to be cleared + * setbits - Bits in the control register to be set + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void tim_modifyreg(struct stm32_chan_s *chan, int offset, + uint32_t clearbits, uint32_t setbits) +{ + modifyreg32(chan->tbase + offset, clearbits, setbits); +} +#endif /* HAVE_TIMER */ + +/**************************************************************************** + * Name: dac_interrupt + * + * Description: + * DAC interrupt handler. The STM32 F4 family supports a only a DAC + * underrun interrupt. + * + * Input Parameters: + * + * Returned Value: + * OK + * + ****************************************************************************/ + +#if 0 /* defined(CONFIG_STM32_HAVE_IP_DAC_M3M4_V1) */ +static int dac_interrupt(int irq, void *context, void *arg) +{ +#warning "Missing logic" + return OK; +} +#endif + +/**************************************************************************** + * Name: dac_reset + * + * Description: + * Reset the DAC channel. Called early to initialize the hardware. This + * is called, before dac_setup() and on error conditions. + * + * NOTE: DAC reset will reset both DAC channels! + * + * Input Parameters: + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void dac_reset(struct dac_dev_s *dev) +{ + irqstate_t flags; + + /* Reset only the selected DAC channel; the other DAC channel must remain + * functional. + */ + + flags = enter_critical_section(); + +#warning "Missing logic" + + leave_critical_section(flags); +} + +/**************************************************************************** + * Name: dac_setup + * + * Description: + * Configure the DAC. This method is called the first time that the DAC + * device is opened. This will occur when the port is first opened. + * This setup includes configuring and attaching DAC interrupts. + * Interrupts are all disabled upon return. + * + * Input Parameters: + * + * Returned Value: + * Zero on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int dac_setup(struct dac_dev_s *dev) +{ +#warning "Missing logic" + return OK; +} + +/**************************************************************************** + * Name: dac_shutdown + * + * Description: + * Disable the DAC. This method is called when the DAC device is closed. + * This method reverses the operation the setup method. + * + * Input Parameters: + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void dac_shutdown(struct dac_dev_s *dev) +{ +#warning "Missing logic" +} + +/**************************************************************************** + * Name: dac_txint + * + * Description: + * Call to enable or disable TX interrupts. + * + * Input Parameters: + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void dac_txint(struct dac_dev_s *dev, bool enable) +{ +#warning "Missing logic" +} + +/**************************************************************************** + * Name: dac_dmatxcallback + * + * Description: + * DMA callback function. + * + * Input Parameters: + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef HAVE_DMA +static void dac_dmatxcallback(DMA_HANDLE handle, uint8_t isr, void *arg) +{ +} +#endif + +/**************************************************************************** + * Name: dac_send + * + * Description: + * Set the DAC output. + * + * Input Parameters: + * + * Returned Value: + * Zero on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int dac_send(struct dac_dev_s *dev, struct dac_msg_s *msg) +{ + struct stm32_chan_s *chan = dev->ad_priv; + + /* Enable DAC Channel */ + +#if defined(CONFIG_STM32_STM32F33XX) + /* For STM32F33XX we have to set BOFF/OUTEN bit for DAC1CH2 and DAC2CH1 + * REVISIT: what if we connect DAC internally with comparator ? + */ + + if (chan->intf > 0) + { + stm32_dac_modify_cr(chan, 0, DAC_CR_EN | DAC_CR_BOFF); + } + else +#endif + { + stm32_dac_modify_cr(chan, 0, DAC_CR_EN); + } + +#if defined(HAVE_IP_DAC_V2) + /* Check channelx ready status bit */ + + uint32_t regval; + uint32_t dac = (chan->intf >> 1); + do + { + regval = getreg32(chan->sr); + } + while (!(regval & DAC_SR_DACRDY(dac))); +#endif + +#ifdef HAVE_DMA + if (chan->hasdma) + { + /* Configure the DMA stream/channel. + * + * - Channel number + * - Peripheral address + * - Direction: Memory to peripheral + * - Disable peripheral address increment + * - Enable memory address increment + * - Peripheral data size: half word + * - Mode: circular??? + * - Priority: ? + * - FIFO mode: disable + * - FIFO threshold: half full + * - Memory Burst: single + * - Peripheral Burst: single + */ + + stm32_dmasetup(chan->dma, chan->dro, (uint32_t)chan->dmabuffer, + chan->buffer_len, DAC_DMA_CONTROL_WORD); + + /* Enable DMA */ + + stm32_dmastart(chan->dma, dac_dmatxcallback, chan, false); + + /* Enable DMA for DAC Channel */ + + stm32_dac_modify_cr(chan, 0, DAC_CR_DMAEN); + } + else +#endif + { + /* Non-DMA transfer */ + +#if defined(HAVE_IP_DAC_V1) + putreg16(msg->am_data, chan->dro); +#else + putreg32(msg->am_data, chan->dro); +#endif + dac_txdone(dev); + } + + /* Reset counters (generate an update). Only when timer is not HRTIM */ + +#ifdef HAVE_TIMER + if (chan->timer != TIM_INDEX_HRTIM) + { + tim_modifyreg(chan, STM32_GTIM_EGR_OFFSET, 0, GTIM_EGR_UG); + } +#endif + + return OK; +} + +/**************************************************************************** + * Name: dac_ioctl + * + * Description: + * All ioctl calls will be routed through this method. + * + * Input Parameters: + * + * Returned Value: + * Zero on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int dac_ioctl(struct dac_dev_s *dev, int cmd, unsigned long arg) +{ + struct stm32_chan_s *chan = dev->ad_priv; + int ret = OK; + + switch (cmd) + { +#ifdef HAVE_DMA + case IO_DMABUFFER_INIT: + { + uint16_t *buffer = (uint16_t *)arg; + + /* The caller is responsible for providing buffer with + * suitable length equal to CONFIG_STM32_DACxCHy_DMA_BUFFER_SIZE + */ + + dma_bufferinit(chan, buffer, chan->buffer_len * sizeof(buffer)); + break; + } +#endif + + default: + { + aerr("ERROR: Unknown cmd: %d\n", cmd); + ret = -ENOTTY; + break; + } + } + + UNUSED(chan); + return ret; +} + +#ifdef HAVE_DMA + +/**************************************************************************** + * Name: dma_bufferinit + ****************************************************************************/ + +static void dma_bufferinit(struct stm32_chan_s *chan, uint16_t *buffer, + uint16_t len) +{ + memcpy(chan->dmabuffer, buffer, len); +} + +/**************************************************************************** + * Name: dma_remap + ****************************************************************************/ + +static int dma_remap(struct stm32_chan_s *chan) +{ +#if defined(CONFIG_STM32_STM32F33XX) || defined(CONFIG_STM32_STM32F30XX) || \ + defined(CONFIG_STM32_STM32F37XX) + uint32_t regval = 0; + + switch (chan->intf) + { + case 0: + { + /* Remap DMA1CH3 to DAC1CH1 */ + + regval |= SYSCFG_CFGR1_DAC1CH1_DMARMP; + + /* Remap DAC trigger for STM32F33XX if needed */ + +# ifdef CONFIG_STM32_STM32F33XX +# if defined(CONFIG_STM32_DAC1CH1_HRTIM_TRG1) + modifyreg32(STM32_SYSCFG_CFGR3, 0, SYSCFG_CFGR3_DAC1_TRIG3_RMP); +# elif defined(CONFIG_STM32_DAC1CH1_HRTIM_TRG2) + modifyreg32(STM32_SYSCFG_CFGR3, 0, SYSCFG_CFGR3_DAC1_TRIG5_RMP); +# endif +# endif + break; + } + + case 1: + { + /* Remap DMA1CH4 to DAC1CH2 */ + + regval |= SYSCFG_CFGR1_DAC1CH2_DMARMP; + + /* Remap DAC trigger for STM32F33XX if needed */ + +# ifdef CONFIG_STM32_STM32F33XX +# if defined(CONFIG_STM32_DAC1CH2_HRTIM_TRG1) + modifyreg32(STM32_SYSCFG_CFGR3, 0, SYSCFG_CFGR3_DAC1_TRIG3_RMP); +# elif defined(CONFIG_STM32_DAC1CH2_HRTIM_TRG2) + modifyreg32(STM32_SYSCFG_CFGR3, 0, SYSCFG_CFGR3_DAC1_TRIG5_RMP); +# endif +# endif + break; + } + + case 2: + { + /* Remap DMA1CH5 to DAC2CH1 */ + + regval |= SYSCFG_CFGR1_DAC2CH1_DMARMP; + break; + } + + default: + { + return -EINVAL; + } + } + + modifyreg32(STM32_SYSCFG_BASE, 0, regval); + +#endif + + return OK; +} + +/**************************************************************************** + * Name: dac_timinit + * + * Description: + * Initialize the timer that drivers the DAC DMA for this channel using + * the pre-calculated timer divider definitions. + * + * Input Parameters: + * chan - A reference to the DAC channel state data + * + * Returned Value: + * Zero on success; a negated errno value on failure. + * + ****************************************************************************/ + +#ifdef HAVE_TIMER +static int dac_timinit(struct stm32_chan_s *chan) +{ + uint32_t pclk; + uint32_t prescaler; + uint32_t timclk; + uint32_t reload; + uint32_t regaddr; + uint32_t setbits; + + /* Configure the time base: Timer period, prescaler, clock division, + * counter mode (up). + */ + + /* Enable the timer. At most, two of the following cases (pulse the + * default) will be enabled + */ + + regaddr = STM32_RCC_APB1ENR; + + switch (chan->timer) + { +#ifdef NEED_TIM2 + case 2: + setbits = RCC_APB1ENR_TIM2EN; + pclk = BOARD_TIM2_FREQUENCY; + break; +#endif +#ifdef NEED_TIM3 + case 3: + setbits = RCC_APB1ENR_TIM3EN; + pclk = BOARD_TIM3_FREQUENCY; + break; +#endif +#ifdef NEED_TIM4 + case 4: + setbits = RCC_APB1ENR_TIM4EN; + pclk = BOARD_TIM4_FREQUENCY; + break; +#endif +#ifdef NEED_TIM5 + case 5: + setbits = RCC_APB1ENR_TIM5EN; + pclk = BOARD_TIM5_FREQUENCY; + break; +#endif +#ifdef NEED_TIM6 + case 6: + setbits = RCC_APB1ENR_TIM6EN; + pclk = BOARD_TIM6_FREQUENCY; + break; +#endif +#ifdef NEED_TIM7 + case 7: + setbits = RCC_APB1ENR_TIM7EN; + pclk = BOARD_TIM7_FREQUENCY; + break; +#endif +#ifdef NEED_TIM8 + case 8: + regaddr = STM32_RCC_APB2ENR; + setbits = RCC_APB2ENR_TIM8EN; + pclk = BOARD_TIM8_FREQUENCY; + break; +#endif + default: + aerr("ERROR: Could not enable timer\n"); + return -EINVAL; + } + + /* Enable the timer. */ + + modifyreg32(regaddr, 0, setbits); + + /* Calculate optimal values for the timer prescaler and for the timer + * reload register. If 'frequency' is the desired frequency, then + * + * reload = timclk / frequency + * timclk = pclk / presc + * + * Or, + * + * reload = pclk / presc / frequency + * + * There are many solutions to this, but the best solution will be the one + * that has the largest reload value and the smallest prescaler value. + * That is the solution that should give us the most accuracy in the timer + * control. Subject to: + * + * 0 <= presc <= 65536 + * 1 <= reload <= 65535 + * + * So presc = pclk / 65535 / frequency would be optimal. + * + * Example: + * + * pclk = 42 MHz + * frequency = 100 Hz + * + * prescaler = 42,000,000 / 65,535 / 100 + * = 6.4 (or 7 -- taking the ceiling always) + * timclk = 42,000,000 / 7 + * = 6,000,000 + * reload = 6,000,000 / 100 + * = 60,000 + */ + + prescaler = (pclk / chan->tfrequency + 65534) / 65535; + if (prescaler < 1) + { + prescaler = 1; + } + else if (prescaler > 65536) + { + prescaler = 65536; + } + + timclk = pclk / prescaler; + + reload = timclk / chan->tfrequency; + if (reload < 1) + { + reload = 1; + } + else if (reload > 65535) + { + reload = 65535; + } + + /* Set the reload and prescaler values */ + + tim_putreg(chan, STM32_GTIM_ARR_OFFSET, (uint16_t)reload); + tim_putreg(chan, STM32_GTIM_PSC_OFFSET, (uint16_t)(prescaler - 1)); + + /* Count mode up, auto reload */ + + tim_modifyreg(chan, STM32_GTIM_CR1_OFFSET, 0, GTIM_CR1_ARPE); + + /* Selection TRGO selection: update */ + + tim_modifyreg(chan, STM32_GTIM_CR2_OFFSET, GTIM_CR2_MMS_MASK, + GTIM_CR2_MMS_UPDATE); + + /* Update DMA request enable ???? */ +#if 0 + tim_modifyreg(chan, STM32_GTIM_DIER_OFFSET, 0, GTIM_DIER_UDE); +#endif + + /* Enable the counter */ + + tim_modifyreg(chan, STM32_GTIM_CR1_OFFSET, 0, GTIM_CR1_CEN); + return OK; +} +#endif +#endif /* HAVE_DMA */ + +/**************************************************************************** + * Name: dac_chaninit + * + * Description: + * Initialize the DAC channel. + * + * Input Parameters: + * chan - A reference to the DAC channel state data + * + * Returned Value: + * Zero on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int dac_chaninit(struct stm32_chan_s *chan) +{ + uint16_t clearbits; + uint16_t setbits; +#if defined(HAVE_IP_DAC_V2) + uint32_t regval; +#endif +#ifdef HAVE_TIMER + int ret; +#endif + + /* Is the selected channel already in-use? */ + + if (chan->inuse) + { + /* Yes.. then return EBUSY */ + + return -EBUSY; + } + + /* Configure the DAC output pin: + * + * DAC -" Once the DAC channelx is enabled, the corresponding GPIO pin + * (PA4 or PA5) is automatically connected to the analog converter output + * (DAC_OUTx). In order to avoid parasitic consumption, the PA4 or PA5 pin + * should first be configured to analog (AIN)". + */ + + /* Only DAC1 and DAC2 have external pins */ + + if (chan->intf < 4) + { + stm32_configgpio(chan->pin); + } + + /* DAC channel configuration: + * + * - Set the trigger selection based upon the configuration. + * - Set wave generation == None. + * - Enable the output buffer. + */ + + /* Disable before change */ + + stm32_dac_modify_cr(chan, DAC_CR_EN, 0); + + clearbits = DAC_CR_TSEL_MASK | + DAC_CR_MAMP_MASK | + DAC_CR_WAVE_MASK; +#if defined (HAVE_IP_DAC_V1) + clearbits |= DAC_CR_BOFF; +#endif + + setbits = + chan->tsel | /* Set trigger source (SW or timer TRGO event) */ + DAC_CR_MAMP_AMP1 | /* Set waveform characteristics */ + DAC_CR_WAVE_DISABLED; /* Set wave generation disabled */ +#if defined (HAVE_IP_DAC_V1) + setbits |= DAC_CR_BOFF_EN; /* Enable output buffer */ +#endif + + stm32_dac_modify_cr(chan, clearbits, setbits); + +#if defined(HAVE_IP_DAC_V2) + /* High frequency interface mode selection */ + + if (STM32_SYSCLK_FREQUENCY > 160000000) + { + regval = DAC_MCR_HFSEL_AHB_160MHz; + } + else if (STM32_SYSCLK_FREQUENCY > 80000000) + { + regval = DAC_MCR_HFSEL_AHB_80MHz; + } + else + { + regval = DAC_MCR_HFSEL_DISABLED; + } + + /* DAC mode selection */ + + regval |= chan->mode; + + putreg32(regval, chan->mcr); +#endif + +#ifdef HAVE_DMA + /* Determine if DMA is supported by this channel */ + + if (chan->hasdma) + { + /* Remap DMA request if necessary */ + + dma_remap(chan); + + /* DAC trigger enable if not external triggering */ + + if (!chan->text) + { + stm32_dac_modify_cr(chan, 0, DAC_CR_TEN); + } + + /* Allocate a DMA channel */ + + chan->dma = stm32_dmachannel(chan->dmachan); + if (!chan->dma) + { + aerr("ERROR: Failed to allocate a DMA channel\n"); + return -EBUSY; + } + + /* Configure the timer that supports the DMA operation + * Do nothing if HRTIM is selected as trigger. + * All necessary configuration is done in the HRTIM driver. + */ + +#ifdef HAVE_TIMER + if (chan->timer != TIM_INDEX_HRTIM) + { + ret = dac_timinit(chan); + if (ret < 0) + { + aerr("ERROR: Failed to initialize the DMA timer: %d\n", ret); + return ret; + } + } +#endif + } +#endif + + /* Mark the DAC channel "in-use" */ + + chan->inuse = 1; + return OK; +} + +/**************************************************************************** + * Name: dac_blockinit + * + * Description: + * Initialize the DAC block. + * + * Input Parameters: + * + * Returned Value: + * Zero on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int dac_blockinit(void) +{ + irqstate_t flags; + uint32_t regval; + + /* Has the DAC block already been initialized? */ + + if (g_dacblock.init) + { + /* Yes.. then return success We only have to do this once */ + + return OK; + } + + /* Put the entire DAC block in reset state */ + + flags = enter_critical_section(); + regval = getreg32(STM32_RCC_RSTR); +#ifdef CONFIG_STM32_DAC1 + regval |= RCC_RSTR_DAC1RST; +#endif +#ifdef CONFIG_STM32_DAC2 + regval |= RCC_RSTR_DAC2RST; +#endif +#ifdef CONFIG_STM32_DAC3 + regval |= RCC_RSTR_DAC3RST; +#endif + putreg32(regval, STM32_RCC_RSTR); + + /* Take the DAC out of reset state */ + +#ifdef CONFIG_STM32_DAC1 + regval &= ~RCC_RSTR_DAC1RST; +#endif +#ifdef CONFIG_STM32_DAC2 + regval &= ~RCC_RSTR_DAC2RST; +#endif +#ifdef CONFIG_STM32_DAC3 + regval &= ~RCC_RSTR_DAC3RST; +#endif + putreg32(regval, STM32_RCC_RSTR); + leave_critical_section(flags); + + /* Mark the DAC block as initialized */ + + g_dacblock.init = 1; + return OK; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_dacinitialize + * + * Description: + * Initialize the DAC. + * + * Input Parameters: + * intf - The DAC interface number. + * + * Returned Value: + * Valid DAC device structure reference on success; a NULL on failure. + * + * Assumptions: + * 1. Clock to the DAC block has enabled, + * 2. Board-specific logic has already configured + * + ****************************************************************************/ + +struct dac_dev_s *stm32_dacinitialize(int intf) +{ + struct dac_dev_s *dev; + struct stm32_chan_s *chan; + int ret; + +#ifdef CONFIG_STM32_DAC1CH1 + if (intf == 1) + { + ainfo("DAC1-1 Selected\n"); + dev = &g_dac1ch1dev; + } + else +#endif /* CONFIG_STM32_DAC1CH1 */ +#ifdef CONFIG_STM32_DAC1CH2 + if (intf == 2) + { + ainfo("DAC1-2 Selected\n"); + dev = &g_dac1ch2dev; + } + else +#endif /* CONFIG_STM32_DAC1CH2 */ +#ifdef CONFIG_STM32_DAC2CH1 + if (intf == 3) + { + ainfo("DAC2-1 Selected\n"); + dev = &g_dac2ch1dev; + } + else +#endif /* CONFIG_STM32_DAC2CH1 */ +#ifdef CONFIG_STM32_DAC3CH1 + if (intf == 4) + { + ainfo("DAC3-1 Selected\n"); + dev = &g_dac3ch1dev; + } + else +#endif /* CONFIG_STM32_DAC3CH1 */ +#ifdef CONFIG_STM32_DAC3CH2 + if (intf == 5) + { + ainfo("DAC3-2 Selected\n"); + dev = &g_dac3ch2dev; + } + else +#endif /* CONFIG_STM32_DAC3CH2 */ + { + aerr("ERROR: No such DAC interface: %d\n", intf); + return NULL; + } + + /* Make sure that the DAC block has been initialized */ + + ret = dac_blockinit(); + if (ret < 0) + { + aerr("ERROR: Failed to initialize the DAC block: %d\n", ret); + return NULL; + } + + /* Configure the selected DAC channel */ + + chan = dev->ad_priv; + ret = dac_chaninit(chan); + if (ret < 0) + { + aerr("ERROR: Failed to initialize DAC channel %d: %d\n", intf, ret); + return NULL; + } + + return dev; +} + +#endif /* CONFIG_DAC */ diff --git a/arch/arm/src/common/stm32/stm32_dac_m3m4_v1.h b/arch/arm/src/common/stm32/stm32_dac_m3m4_v1.h new file mode 100644 index 0000000000000..9683dab6d8884 --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_dac_m3m4_v1.h @@ -0,0 +1,144 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_dac_m3m4_v1.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_DAC_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_DAC_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#if defined(CONFIG_STM32_HAVE_IP_DAC_M3M4_V1) || \ + defined(CONFIG_STM32_HAVE_IP_DAC_M3M4_V2) + +#include "chip.h" +#include "hardware/stm32_dac.h" + +#include + +/**************************************************************************** + * Pre-processor definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* Timer devices may be used for different purposes. One special purpose is + * to control periodic DAC outputs. If CONFIG_STM32_TIMn is defined then + * CONFIG_STM32_TIMn_DAC must also be defined to indicate that timer "n" is + * intended to be used for that purpose. + */ + +#ifndef CONFIG_STM32_TIM1 +# undef CONFIG_STM32_TIM1_DAC +#endif +#ifndef CONFIG_STM32_TIM2 +# undef CONFIG_STM32_TIM2_DAC +#endif +#ifndef CONFIG_STM32_TIM3 +# undef CONFIG_STM32_TIM3_DAC +#endif +#ifndef CONFIG_STM32_TIM4 +# undef CONFIG_STM32_TIM4_DAC +#endif +#ifndef CONFIG_STM32_TIM5 +# undef CONFIG_STM32_TIM5_DAC +#endif +#ifndef CONFIG_STM32_TIM6 +# undef CONFIG_STM32_TIM6_DAC +#endif +#ifndef CONFIG_STM32_TIM7 +# undef CONFIG_STM32_TIM7_DAC +#endif +#ifndef CONFIG_STM32_TIM8 +# undef CONFIG_STM32_TIM8_DAC +#endif +#ifndef CONFIG_STM32_TIM9 +# undef CONFIG_STM32_TIM9_DAC +#endif +#ifndef CONFIG_STM32_TIM10 +# undef CONFIG_STM32_TIM10_DAC +#endif +#ifndef CONFIG_STM32_TIM11 +# undef CONFIG_STM32_TIM11_DAC +#endif +#ifndef CONFIG_STM32_TIM12 +# undef CONFIG_STM32_TIM12_DAC +#endif +#ifndef CONFIG_STM32_TIM13 +# undef CONFIG_STM32_TIM13_DAC +#endif +#ifndef CONFIG_STM32_TIM14 +# undef CONFIG_STM32_TIM14_DAC +#endif + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/* IOCTL commands specific to this driver */ + +enum dac_io_cmds +{ + IO_DMABUFFER_INIT = 0, +}; + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#ifndef __ASSEMBLY__ +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Name: stm32_dacinitialize + * + * Description: + * Initialize the DAC + * + * Input Parameters: + * intf - The DAC interface number. + * + * Returned Value: + * Valid DAC device structure reference on success; a NULL on failure + * + ****************************************************************************/ + +struct dac_dev_s; +struct dac_dev_s *stm32_dacinitialize(int intf); + +#undef EXTERN +#ifdef __cplusplus +} +#endif +#endif /* __ASSEMBLY__ */ + +#endif /* CONFIG_STM32_HAVE_IP_DAC_M3M4_V1 || CONFIG_STM32_HAVE_IP_DAC_M3M4_V2 */ + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_DAC_H */ diff --git a/arch/arm/src/common/stm32/stm32_dbgmcu.h b/arch/arm/src/common/stm32/stm32_dbgmcu.h new file mode 100644 index 0000000000000..4b1b2f81ee37d --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_dbgmcu.h @@ -0,0 +1,57 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_dbgmcu.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_DBGMCU_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_DBGMCU_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#if defined(CONFIG_STM32_HAVE_IP_DBGMCU_M3M4_V1) || \ + defined(CONFIG_STM32_HAVE_IP_DBGMCU_M3M4_V2) || \ + defined(CONFIG_STM32_HAVE_IP_DBGMCU_M3M4_V3) + +#include "chip.h" +#include "hardware/stm32_dbgmcu.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#endif /* CONFIG_STM32_HAVE_IP_DBGMCU_M3M4_V1 || ... */ + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_DBGMCU_H */ diff --git a/arch/arm/src/common/stm32/stm32_dfumode.h b/arch/arm/src/common/stm32/stm32_dfumode.h new file mode 100644 index 0000000000000..593c06fad90ad --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_dfumode.h @@ -0,0 +1,38 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_dfumode.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_COMPAT_STM32DFUMODE_H +#define __ARCH_ARM_SRC_COMMON_COMPAT_STM32DFUMODE_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#if defined(CONFIG_STM32_HAVE_IP_DFUMODE_M3M4_V1) +# include "stm32_dfumode_m3m4_v1.h" +#else +# error "Unsupported STM32 stm32_dfumode" +#endif + +#endif /* __ARCH_ARM_SRC_COMMON_COMPAT_STM32DFUMODE_H */ diff --git a/arch/arm/src/common/stm32/stm32_dfumode_m3m4_v1.c b/arch/arm/src/common/stm32/stm32_dfumode_m3m4_v1.c new file mode 100644 index 0000000000000..40bb4b28ad07d --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_dfumode_m3m4_v1.c @@ -0,0 +1,80 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_dfumode_m3m4_v1.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include + +#include "stm32_dfumode_m3m4_v1.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_dfumode + * + * Description: + * Reboot the part in DFU mode (GCC only). + * + * https://community.st.com/s/question/ + * 0D50X00009XkhAzSAJ/calling-stm32429ieval-bootloader + * + * REVISIT: STM32_SYSMEM_BASE is not 0x1fff000 for all STM32's. For F3's + * The SYSMEM base is at 0x1fffd800 + * + * REVISIT: RCC_APB2ENR_SYSCFGEN is not bit 14 for all STM32's. For F3's + * and L15's, it is bit 0. + * + * REVISIT: STM32 F3's do not support the SYSCFG_MEMRMP register. + * + ****************************************************************************/ + +#if defined(CONFIG_STM32_HAVE_IP_DFUMODE_M3M4_V1) +void stm32_dfumode(void) +{ +#ifdef CONFIG_DEBUG_WARN + _warn("Entering DFU mode...\n"); + nxsched_sleep(1); +#endif + + asm("ldr r0, =0x40023844\n\t" /* RCC_APB2ENR */ + "ldr r1, =0x00004000\n\t" /* Enable SYSCFG clock */ + "str r1, [r0, #0]\n\t" + "ldr r0, =0x40013800\n\t" /* SYSCFG_MEMRMP */ + "ldr r1, =0x00000001\n\t" /* Map ROM at zero */ + "str r1, [r0, #0]\n\t" + "ldr r0, =0x1fff0000\n\t" /* ROM base */ + "ldr sp,[r0, #0]\n\t" /* SP @ 0 */ + "ldr r0,[r0, #4]\n\t" /* PC @ 4 */ + "bx r0\n"); + + __builtin_unreachable(); /* Tell compiler we will not return */ +} +#endif /* CONFIG_STM32_HAVE_IP_DFUMODE_M3M4_V1 */ diff --git a/arch/arm/src/common/stm32/stm32_dfumode_m3m4_v1.h b/arch/arm/src/common/stm32/stm32_dfumode_m3m4_v1.h new file mode 100644 index 0000000000000..5a3c639fc129c --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_dfumode_m3m4_v1.h @@ -0,0 +1,51 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_dfumode_m3m4_v1.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_DFUMODE_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_DFUMODE_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_dfumode + * + * Description: + * Reboot the part in DFU mode. + * + * https://community.st.com/s/question/0D50X00009XkhAzSAJ/ + * calling-stm32429ieval-bootloader + * + ****************************************************************************/ + +#if defined(CONFIG_STM32_HAVE_IP_DFUMODE_M3M4_V1) +void stm32_dfumode(void) noreturn_function; +#endif + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_DFUMODE_H */ diff --git a/arch/arm/src/common/stm32/stm32_dma.h b/arch/arm/src/common/stm32/stm32_dma.h new file mode 100644 index 0000000000000..16124d4a4b73f --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_dma.h @@ -0,0 +1,39 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_dma.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_DMA_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_DMA_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#if defined(CONFIG_STM32_HAVE_IP_DMA_V1) || \ + defined(CONFIG_STM32_HAVE_IP_DMA_V2) +# include "stm32_dma_channel_stream.h" +#else +# error "Unsupported STM32 DMA" +#endif + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_DMA_H */ diff --git a/arch/arm/src/common/stm32/stm32_dma2d.h b/arch/arm/src/common/stm32/stm32_dma2d.h new file mode 100644 index 0000000000000..548dd220034ea --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_dma2d.h @@ -0,0 +1,38 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_dma2d.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_COMPAT_STM32DMA2D_H +#define __ARCH_ARM_SRC_COMMON_COMPAT_STM32DMA2D_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#if defined(CONFIG_STM32_COMMON_LEGACY) +# include "stm32_dma2d_m3m4_v1.h" +#else +# error "Unsupported STM32 stm32_dma2d" +#endif + +#endif /* __ARCH_ARM_SRC_COMMON_COMPAT_STM32DMA2D_H */ diff --git a/arch/arm/src/common/stm32/stm32_dma2d_m3m4_v1.c b/arch/arm/src/common/stm32/stm32_dma2d_m3m4_v1.c new file mode 100644 index 0000000000000..f1c195a43cd0c --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_dma2d_m3m4_v1.c @@ -0,0 +1,1168 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_dma2d_m3m4_v1.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* References: + * STM32F429 Technical Reference Manual + */ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include + +#include "arm_internal.h" +#include "stm32.h" +#include "hardware/stm32_ltdc.h" +#include "hardware/stm32_dma2d.h" +#include "stm32_dma2d_m3m4_v1.h" +#include "stm32_dma2d_m3m4_v1.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* DMA2D supported operation layer (output, foreground, background) */ + +#define DMA2D_NLAYERS 3 + +/* DMA2D blender control */ + +#define STM32_DMA2D_CR_MODE_BLIT DMA2D_CR_MODE(0) +#define STM32_DMA2D_CR_MODE_BLITPFC DMA2D_CR_MODE(1) +#define STM32_DMA2D_CR_MODE_BLEND DMA2D_CR_MODE(2) +#define STM32_DMA2D_CR_MODE_COLOR DMA2D_CR_MODE(3) +#define STM32_DMA2D_CR_MODE_CLEAR STM32_DMA2D_CR_MODE_BLITPFC | \ + STM32_DMA2D_CR_MODE_BLEND | \ + STM32_DMA2D_CR_MODE_COLOR + +/* Only 8 bit per pixel overall supported */ + +#define DMA2D_PF_BYPP(n) ((n) / 8) + +/* CC clut size */ + +#define DMA2D_CLUT_SIZE STM32_DMA2D_NCLUT - 1 + +/* Layer argb cmap conversion */ + +#define DMA2D_CLUT_ALPHA(n) ((uint32_t)(n) << 24) +#define DMA2D_CLUT_RED(n) ((uint32_t)(n) << 16) +#define DMA2D_CLUT_GREEN(n) ((uint32_t)(n) << 8) +#define DMA2D_CLUT_BLUE(n) ((uint32_t)(n) << 0) + +#define DMA2D_CMAP_ALPHA(n) ((uint32_t)(n) >> 24) +#define DMA2D_CMAP_RED(n) ((uint32_t)(n) >> 16) +#define DMA2D_CMAP_GREEN(n) ((uint32_t)(n) >> 8) +#define DMA2D_CMAP_BLUE(n) ((uint32_t)(n) >> 0) + +/* Debug option */ + +#ifdef CONFIG_STM32_DMA2D_REGDEBUG +# define regerr lcderr +# define reginfo lcdinfo +#else +# define regerr(x...) +# define reginfo(x...) +#endif + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/* DMA2D General layer information */ + +struct stm32_dma2d_s +{ + struct dma2d_layer_s dma2d; /* Public dma2d interface */ + +#ifdef CONFIG_STM32_FB_CMAP + uint32_t *clut; /* Color lookup table */ +#endif + mutex_t *lock; /* Ensure mutually exclusive access */ +}; + +/* Interrupt handling */ + +struct stm32_interrupt_s +{ + int irq; /* irq number */ + int error; /* Interrupt error */ + sem_t *sem; /* Semaphore for waiting for irq */ +}; + +/* This enumeration foreground and background layer supported by the dma2d + * controller + */ + +enum stm32_layer_e +{ + DMA2D_LAYER_LFORE = 0, /* Foreground Layer */ + DMA2D_LAYER_LBACK, /* Background Layer */ + DMA2D_LAYER_LOUT, /* Output Layer */ +}; + +/* DMA2D memory address register */ + +static const uintptr_t stm32_mar_layer_t[DMA2D_NLAYERS] = +{ + STM32_DMA2D_FGMAR, + STM32_DMA2D_BGMAR, + STM32_DMA2D_OMAR +}; + +/* DMA2D offset register */ + +static const uintptr_t stm32_or_layer_t[DMA2D_NLAYERS] = +{ + STM32_DMA2D_FGOR, + STM32_DMA2D_BGOR, + STM32_DMA2D_OOR +}; + +/* DMA2D pfc control register */ + +static const uintptr_t stm32_pfccr_layer_t[DMA2D_NLAYERS] = +{ + STM32_DMA2D_FGPFCCR, + STM32_DMA2D_BGPFCCR, + STM32_DMA2D_OPFCCR +}; + +/* DMA2D color register */ + +static const uintptr_t stm32_color_layer_t[DMA2D_NLAYERS] = +{ + STM32_DMA2D_FGCOLR, + STM32_DMA2D_BGCOLR, + STM32_DMA2D_OCOLR +}; + +/* DMA2D clut memory address register */ + +#ifdef CONFIG_STM32_FB_CMAP +static const uintptr_t stm32_cmar_layer_t[DMA2D_NLAYERS - 1] = +{ + STM32_DMA2D_FGCMAR, + STM32_DMA2D_BGCMAR +}; +#endif + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/* Private functions */ + +static void stm32_dma2d_control(uint32_t setbits, uint32_t clrbits); +static int stm32_dma2dirq(int irq, void *context, void *arg); +static int stm32_dma2d_waitforirq(void); +static int stm32_dma2d_start(void); +#ifdef CONFIG_STM32_FB_CMAP +static int stm32_dma2d_loadclut(uintptr_t reg); +#endif +static uint32_t stm32_dma2d_memaddress( + struct stm32_dma2d_overlay_s *oinfo, + uint32_t xpos, uint32_t ypos); +static uint32_t stm32_dma2d_lineoffset( + struct stm32_dma2d_overlay_s *oinfo, + const struct fb_area_s *area); +static void stm32_dma2d_lfifo(struct stm32_dma2d_overlay_s *oinfo, + int lid, + uint32_t xpos, uint32_t ypos, + const struct fb_area_s *area); +static void stm32_dma2d_lcolor(int lid, uint32_t argb); +static void stm32_dma2d_llnr(const struct fb_area_s *area); +static int stm32_dma2d_loutpfc(uint8_t fmt); +static void stm32_dma2d_lpfc(int lid, uint32_t blendmode, uint8_t alpha, + uint8_t fmt); + +/* Public Functions */ + +#ifdef CONFIG_STM32_FB_CMAP +static int stm32_dma2d_setclut(const struct fb_cmap_s *cmap); +#endif +static int stm32_dma2d_fillcolor(struct stm32_dma2d_overlay_s *oinfo, + const struct fb_area_s *area, + uint32_t argb); +static int stm32_dma2d_blit(struct stm32_dma2d_overlay_s *doverlay, + uint32_t destxpos, uint32_t destypos, + struct stm32_dma2d_overlay_s *soverlay, + const struct fb_area_s *sarea); +static int stm32_dma2d_blend(struct stm32_dma2d_overlay_s *doverlay, + uint32_t destxpos, uint32_t destypos, + struct stm32_dma2d_overlay_s *foverlay, + uint32_t forexpos, uint32_t foreypos, + struct stm32_dma2d_overlay_s *boverlay, + const struct fb_area_s *barea); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* The initialized state of the driver */ + +static bool g_initialized; + +/* Allocate clut */ + +#ifdef CONFIG_STM32_FB_CMAP +static uint32_t g_clut[STM32_DMA2D_NCLUT * +# ifdef CONFIG_STM32_FB_TRANSPARENCY + 4 +# else + 3 +# endif + / 4]; +#endif /* CONFIG_STM32_FB_CMAP */ + +/* The DMA2D mutex that enforces mutually exclusive access */ + +static mutex_t g_lock = NXMUTEX_INITIALIZER; + +/* Semaphore for interrupt handling */ + +static sem_t g_semirq = SEM_INITIALIZER(0); + +/* This structure provides irq handling */ + +static struct stm32_interrupt_s g_interrupt = +{ + .irq = STM32_IRQ_DMA2D, + .error = OK, + .sem = &g_semirq +}; + +static struct stm32_dma2d_s g_dma2ddev = +{ + .dma2d = + { +#ifdef CONFIG_STM32_FB_CMAP + .setclut = stm32_dma2d_setclut, +#endif + .fillcolor = stm32_dma2d_fillcolor, + .blit = stm32_dma2d_blit, + .blend = stm32_dma2d_blend + }, +#ifdef CONFIG_STM32_FB_CMAP + .clut = g_clut, +#endif + .lock = &g_lock +}; + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_dma2d_control + * + * Description: + * Change the DMA2D control register + * + * Input Parameters: + * setbits - The bits to set + * clrbits - The bits to clear + * + ****************************************************************************/ + +static void stm32_dma2d_control(uint32_t setbits, uint32_t clrbits) +{ + uint32_t cr; + + lcdinfo("setbits=%08" PRIx32 ", clrbits=%08" PRIx32 "\n", + setbits, clrbits); + + cr = getreg32(STM32_DMA2D_CR); + cr &= ~clrbits; + cr |= setbits; + + lcdinfo("cr=%08" PRIx32 "\n", cr); + putreg32(cr, STM32_DMA2D_CR); +} + +/**************************************************************************** + * Name: stm32_dma2dirq + * + * Description: + * DMA2D interrupt handler + * + ****************************************************************************/ + +static int stm32_dma2dirq(int irq, void *context, void *arg) +{ + int ret; + uint32_t regval = getreg32(STM32_DMA2D_ISR); + struct stm32_interrupt_s *priv = &g_interrupt; + + reginfo("irq = %d, regval = %08" PRIx32 "\n", irq, regval); + + if (regval & DMA2D_ISR_TCIF) + { + /* Transfer complete interrupt */ + + /* Clear the interrupt status register */ + + reginfo("DMA transfer complete\n"); + putreg32(DMA2D_IFCR_CTCIF, STM32_DMA2D_IFCR); + priv->error = OK; + } +#ifdef CONFIG_STM32_DMA2D_L8 + else if (regval & DMA2D_ISR_CTCIF) + { + /* CLUT transfer complete interrupt */ + + /* Clear the interrupt status register */ + + reginfo("CLUT transfer complete\n"); + putreg32(DMA2D_IFCR_CCTCIF, STM32_DMA2D_IFCR); + priv->error = OK; + } +#endif + else if (regval & DMA2D_ISR_TWIF) + { + /* Watermark transfer complete interrupt */ + + /* Clear the interrupt status register */ + + reginfo("Watermark transfer complete\n"); + putreg32(DMA2D_IFCR_CTWIF, STM32_DMA2D_IFCR); + priv->error = OK; + } + else if (regval & DMA2D_ISR_TEIF) + { + /* Transfer error interrupt */ + + /* Clear the interrupt status register */ + + reginfo("ERROR: transfer\n"); + putreg32(DMA2D_IFCR_CTEIF, STM32_DMA2D_IFCR); + priv->error = -ECANCELED; + } + else if (regval & DMA2D_ISR_CAEIF) + { + /* CLUT access error interrupt */ + + /* Clear the interrupt status register */ + + reginfo("ERROR: clut access\n"); + putreg32(DMA2D_IFCR_CAECIF, STM32_DMA2D_IFCR); + priv->error = -ECANCELED; + } + else if (regval & DMA2D_ISR_CEIF) + { + /* Configuration error interrupt */ + + /* Clear the interrupt status register */ + + reginfo("ERROR: configuration\n"); + putreg32(DMA2D_IFCR_CCEIF, STM32_DMA2D_IFCR); + priv->error = -ECANCELED; + } + else + { + /* Unknown irq, should not occur */ + + DEBUGASSERT("Unknown interrupt error\n"); + } + + /* Unlock the semaphore if locked */ + + ret = nxsem_post(priv->sem); + + if (ret < 0) + { + lcderr("ERROR: nxsem_post() failed\n"); + } + + return OK; +} + +/**************************************************************************** + * Name: stm32_dma2d_waitforirq + * + * Description: + * Helper waits until the dma2d irq occurs. That means that an ongoing clut + * loading or dma transfer was completed. + * Note! The caller must use this function within a critical section. + * + * Returned Value: + * On success OK otherwise ERROR + * + ****************************************************************************/ + +static int stm32_dma2d_waitforirq(void) +{ + int ret; + struct stm32_interrupt_s *priv = &g_interrupt; + + ret = nxsem_wait(priv->sem); + + if (ret < 0) + { + lcderr("ERROR: nxsem_wait() failed\n"); + return ret; + } + + ret = priv->error; + + return ret; +} + +/**************************************************************************** + * Name: stm32_dma2d_loadclut + * + * Description: + * Starts clut loading but doesn't wait until loading is complete! + * + * Input Parameters: + * pfcreg - PFC control Register + * + * Returned Value: + * On success - OK + * On error - -EINVAL + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_DMA2D_L8 +static int stm32_dma2d_loadclut(uintptr_t pfcreg) +{ + int ret; + uint32_t regval; + + /* Start clut loading */ + + regval = getreg32(pfcreg); + regval |= DMA2D_XGPFCCR_START; + reginfo("set regval=%08" PRIx32 "\n", regval); + putreg32(regval, pfcreg); + reginfo("configured regval=%08" PRIx32 "\n", getreg32(pfcreg)); + + /* Wait until clut is finished */ + + ret = stm32_dma2d_waitforirq(); + + return ret; +} +#endif + +/**************************************************************************** + * Name: stm32_dma2d_start + * + * Description: + * Starts the dma transfer and waits until completed. + * + * Input Parameters: + * reg - Register to set the start + * startflag - The related flag to start the dma transfer + * irqflag - The interrupt enable flag in the DMA2D_CR register + * + ****************************************************************************/ + +static int stm32_dma2d_start(void) +{ + int ret; + + /* Start dma transfer */ + + stm32_dma2d_control(DMA2D_CR_START, 0); + + /* wait until transfer is complete */ + + ret = stm32_dma2d_waitforirq(); + + return ret; +} + +/**************************************************************************** + * Name: stm32_dma2d_memaddress + * + * Description: + * Helper to calculate the layer memory address + * + * Input Parameters: + * oinfo - Reference to overlay information + * xpos - x-Offset + * ypos - y-Offset + * + * Returned Value: + * memory address + * + ****************************************************************************/ + +static uint32_t stm32_dma2d_memaddress( + struct stm32_dma2d_overlay_s *oinfo, + uint32_t xpos, uint32_t ypos) +{ + uint32_t offset; + struct fb_overlayinfo_s *poverlay = oinfo->oinfo; + + offset = xpos * DMA2D_PF_BYPP(poverlay->bpp) + poverlay->stride * ypos; + + lcdinfo("%" PRIx32 ", offset=%" PRId32 "\n", + ((uint32_t) poverlay->fbmem) + offset, offset); + return ((uint32_t) poverlay->fbmem) + offset; +} + +/**************************************************************************** + * Name: stm32_dma2d_lineoffset + * + * Description: + * Helper to calculate the layer line offset + * + * Input Parameters: + * oinfo - Reference to overlay information + * + * Returned Value: + * line offset + * + ****************************************************************************/ + +static uint32_t stm32_dma2d_lineoffset( + struct stm32_dma2d_overlay_s *oinfo, + const struct fb_area_s *area) +{ + uint32_t loffset; + + /* offset at the end of each line in the context to the area layer */ + + loffset = oinfo->xres - area->w; + + lcdinfo("%" PRId32 "\n", loffset); + return loffset; +} + +/**************************************************************************** + * Name: stm32_dma2d_lfifo + * + * Description: + * Set the fifo for the foreground, background and output layer + * Configures the memory address register + * Configures the line offset register + * + * Input Parameters: + * layer - Reference to the common layer state structure + * + ****************************************************************************/ + +static void stm32_dma2d_lfifo(struct stm32_dma2d_overlay_s *oinfo, + int lid, uint32_t xpos, uint32_t ypos, + const struct fb_area_s *area) +{ + lcdinfo("oinfo=%p, lid=%d, xpos=%" PRId32 ", ypos=%" PRId32 ", area=%p\n", + oinfo, lid, xpos, ypos, area); + + putreg32(stm32_dma2d_memaddress(oinfo, xpos, ypos), + stm32_mar_layer_t[lid]); + putreg32(stm32_dma2d_lineoffset(oinfo, area), stm32_or_layer_t[lid]); +} + +/**************************************************************************** + * Name: stm32_dma2d_lcolor + * + * Description: + * Set the color for the layer + * + * Input Parameters: + * lid - Layer type (output, foreground, background) + * argb - argb8888 color + * + ****************************************************************************/ + +static void stm32_dma2d_lcolor(int lid, uint32_t argb) +{ + lcdinfo("lid=%d, argb=%08" PRIx32 "\n", lid, argb); + putreg32(argb, stm32_color_layer_t[lid]); +} + +/**************************************************************************** + * Name: stm32_dma2d_llnr + * + * Description: + * Set the number of line register + * + * Input Parameters: + * area - Reference to area information + * + ****************************************************************************/ + +static void stm32_dma2d_llnr(const struct fb_area_s *area) +{ + uint32_t nlrreg; + + lcdinfo("pixel per line: %d, number of lines: %d\n", area->w, area->h); + + nlrreg = getreg32(STM32_DMA2D_NLR); + nlrreg = (DMA2D_NLR_PL(area->w) | DMA2D_NLR_NL(area->h)); + putreg32(nlrreg, STM32_DMA2D_NLR); +} + +/**************************************************************************** + * Name: stm32_dma2d_loutpfc + * + * Description: + * Set the output PFC control register + * + * Input Parameters: + * fmt - DMA2D pixel format + * + ****************************************************************************/ + +static int stm32_dma2d_loutpfc(uint8_t fmt) +{ + lcdinfo("pixel format: %d\n", fmt); + + /* Set the mapped pixel format of the destination layer */ + + putreg32(DMA2D_OPFCCR_CM(fmt), STM32_DMA2D_OPFCCR); + + return OK; +} + +/**************************************************************************** + * Name: stm32_dma2d_lpfc + * + * Description: + * Configure foreground and background layer PFC control register + * + * Input Parameters: + * lid - Layer id (output, foreground, background) + * blendmode - Layer blendmode (dma2d register values) + * alpha - Transparency + * + ****************************************************************************/ + +static void stm32_dma2d_lpfc(int lid, uint32_t blendmode, uint8_t alpha, + uint8_t fmt) +{ + uint32_t pfccrreg; + + lcdinfo("lid=%d, blendmode=%08" PRIx32 ", alpha=%02x, fmt=%d\n", + lid, blendmode, alpha, fmt); + + /* Set color format */ + + pfccrreg = DMA2D_XGPFCCR_CM(fmt); + +#ifdef CONFIG_STM32_FB_CMAP + if (fmt == DMA2D_PF_L8) + { + struct stm32_dma2d_s *layer = &g_dma2ddev; + + /* Load CLUT automatically */ + + pfccrreg |= DMA2D_XGPFCCR_START; + + /* Set the CLUT color mode */ + +# ifndef CONFIG_STM32_FB_TRANSPARENCY + pfccrreg |= DMA2D_XGPFCCR_CCM; +# endif + + /* Set CLUT size */ + + pfccrreg |= DMA2D_XGPFCCR_CS(DMA2D_CLUT_SIZE); + + /* Set the CLUT memory address */ + + putreg32((uint32_t) layer->clut, stm32_cmar_layer_t[lid]); + + /* Start async clut loading */ + + stm32_dma2d_loadclut(stm32_pfccr_layer_t[lid]); + } +#endif /* CONFIG_STM32_FB_CMAP */ + + /* Set alpha blend mode */ + + pfccrreg |= DMA2D_XGPFCCR_AM(blendmode); + + if (blendmode == STM32_DMA2D_PFCCR_AM_CONST || + blendmode == STM32_DMA2D_PFCCR_AM_PIXEL) + { + /* Set alpha value */ + + pfccrreg |= DMA2D_XGPFCCR_ALPHA(alpha); + } + + putreg32(pfccrreg, stm32_pfccr_layer_t[lid]); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_dma2d_setclut + * + * Description: + * Configure layer clut (color lookup table). + * + * Input Parameters: + * cmap - Color lookup table with up the 256 entries + * + * Returned Value: + * On success - OK + * On error - -EINVAL + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_FB_CMAP +static int stm32_dma2d_setclut(const struct fb_cmap_s *cmap) +{ + int n; + struct stm32_dma2d_s *priv = &g_dma2ddev; + + lcdinfo("cmap=%p\n", cmap); + + nxmutex_lock(priv->lock); + + for (n = cmap->first; n < cmap->len - 1 && n < STM32_DMA2D_NCLUT; n++) + { + /* Update the layer clut entry, will be automatically loaded before + * blit operation becomes active + */ + +# ifndef CONFIG_STM32_FB_TRANSPARENCY + uint8_t *clut = (uint8_t *)g_dma2ddev.clut; + uint16_t offset = 3 * n; + + clut[offset] = cmap->blue[n]; + clut[offset + 1] = cmap->green[n]; + clut[offset + 2] = cmap->red[n]; + + reginfo("n=%d, red=%02x, green=%02x, blue=%02x\n", n, clut[offset], + clut[offset + 1], clut[offset + 2]); +# else + uint32_t *clut = g_dma2ddev.clut; + + clut[n] = (uint32_t)DMA2D_CLUT_ALPHA(cmap->transp[n]) | + (uint32_t)DMA2D_CLUT_RED(cmap->red[n]) | + (uint32_t)DMA2D_CLUT_GREEN(cmap->green[n]) | + (uint32_t)DMA2D_CLUT_BLUE(cmap->blue[n]); + + reginfo("n=%d, alpha=%02x, red=%02x, green=%02x, blue=%02x\n", n, + DMA2D_CLUT_ALPHA(cmap->transp[n]), + DMA2D_CLUT_RED(cmap->red[n]), + DMA2D_CLUT_GREEN(cmap->green[n]), + DMA2D_CLUT_BLUE(cmap->blue[n])); +# endif + } + + nxmutex_unlock(priv->lock); + return OK; +} +#endif /* CONFIG_STM32_FB_CMAP */ + +/**************************************************************************** + * Name: stm32_dma2d_fillcolor + * + * Description: + * Fill the selected area of the whole overlay with a specific color. + * The caller must ensure that the area is within the entire overlay. + * + * Input Parameters: + * oinfo - Overlay to fill + * area - Reference to the valid area structure select the area + * argb - Color to fill the selected area. Color must be argb8888 + * formatted. + * + * Returned Value: + * OK - On success + * -EINVAL - If one of the parameter invalid or if the size of the + * selected area outside the visible area of the layer. + * -ECANCELED - Operation cancelled, something goes wrong. + * + ****************************************************************************/ + +static int stm32_dma2d_fillcolor(struct stm32_dma2d_overlay_s *oinfo, + const struct fb_area_s *area, + uint32_t argb) +{ + int ret; + struct stm32_dma2d_s *priv = &g_dma2ddev; + DEBUGASSERT(oinfo != NULL && oinfo->oinfo != NULL && area != NULL); + + lcdinfo("oinfo=%p, argb=%08" PRIx32 "\n", oinfo, argb); + +#ifdef CONFIG_STM32_FB_CMAP + if (oinfo->fmt == DMA2D_PF_L8) + { + /* CLUT output not supported */ + + lcderr("ERROR: Returning ENOSYS, " + "output to layer with CLUT format not supported.\n"); + return -ENOSYS; + } +#endif + + nxmutex_lock(priv->lock); + + /* Set output pfc */ + + stm32_dma2d_loutpfc(oinfo->fmt); + + /* Set output fifo */ + + stm32_dma2d_lfifo(oinfo, DMA2D_LAYER_LOUT, area->x, area->y, area); + + /* Set the output color register */ + + stm32_dma2d_lcolor(DMA2D_LAYER_LOUT, argb); + + /* Set number of lines and pixel per line */ + + stm32_dma2d_llnr(area); + + /* Set register to memory transfer */ + + stm32_dma2d_control(STM32_DMA2D_CR_MODE_COLOR, STM32_DMA2D_CR_MODE_CLEAR); + + /* Start DMA2D and wait until completed */ + + ret = stm32_dma2d_start(); + + if (ret != OK) + { + ret = -ECANCELED; + lcderr("ERROR: Returning ECANCELED\n"); + } + + nxmutex_unlock(priv->lock); + return ret; +} + +/**************************************************************************** + * Name: stm32_dma2d_blit + * + * Description: + * Copy memory from a source overlay (defined by sarea) to destination + * overlay position (defined by destxpos and destypos). + * + * Input Parameters: + * doverlay - Valid reference to the destination overlay + * destxpos - Valid selected x position of the destination overlay + * destypos - Valid selected y position of the destination overlay + * soverlay - Valid reference to the source overlay + * sarea - Valid reference to the selected area of the source overlay + * + * Returned Value: + * OK - On success + * -EINVAL - If one of the parameter invalid or if the size of the + * selected source area outside the visible area of the + * destination layer. + * (The visible area usually represents the display size) + * -ECANCELED - Operation cancelled, something goes wrong. + * + ****************************************************************************/ + +static int stm32_dma2d_blit(struct stm32_dma2d_overlay_s *doverlay, + uint32_t destxpos, uint32_t destypos, + struct stm32_dma2d_overlay_s *soverlay, + const struct fb_area_s *sarea) +{ + int ret; + uint32_t mode; + struct stm32_dma2d_s *priv = &g_dma2ddev; + + lcdinfo("doverlay=%p, destxpos=%" PRId32 ", destypos=%" PRId32 + ", soverlay=%p, sarea=%p\n", + doverlay, destxpos, destypos, soverlay, sarea); + + nxmutex_lock(priv->lock); + + /* Set output pfc */ + + stm32_dma2d_loutpfc(doverlay->fmt); + + /* Set foreground pfc */ + + stm32_dma2d_lpfc(DMA2D_LAYER_LFORE, STM32_DMA2D_PFCCR_AM_NONE, 0, + soverlay->fmt); + + /* Set foreground fifo */ + + stm32_dma2d_lfifo(soverlay, DMA2D_LAYER_LFORE, sarea->x, sarea->y, sarea); + + /* Set output fifo */ + + stm32_dma2d_lfifo(doverlay, DMA2D_LAYER_LOUT, destxpos, destypos, sarea); + + /* Set number of lines and pixel per line */ + + stm32_dma2d_llnr(sarea); + + /* Set dma2d mode for blit operation */ + + if (doverlay->fmt == soverlay->fmt) + { + /* Blit without pfc */ + + mode = STM32_DMA2D_CR_MODE_BLIT; + } + else + { + /* Blit with pfc */ + + mode = STM32_DMA2D_CR_MODE_BLITPFC; + } + + stm32_dma2d_control(mode, STM32_DMA2D_CR_MODE_CLEAR); + + /* Start DMA2D and wait until completed */ + + ret = stm32_dma2d_start(); + + if (ret != OK) + { + ret = -ECANCELED; + lcderr("ERROR: Returning ECANCELED\n"); + } + + nxmutex_unlock(priv->lock); + return ret; +} + +/**************************************************************************** + * Name: stm32_dma2d_blend + * + * Description: + * Blends the selected area from a background layer with selected position + * of the foreground layer. Copies the result to the selected position of + * the destination layer. Note! The content of the foreground and + * background layer keeps unchanged as long destination layer is unequal to + * the foreground and background layer. + * + * Input Parameters: + * doverlay - Destination overlay + * destxpos - x-Offset destination overlay + * destypos - y-Offset destination overlay + * foverlay - Foreground overlay + * forexpos - x-Offset foreground overlay + * foreypos - y-Offset foreground overlay + * boverlay - Background overlay + * barea - x-Offset, y-Offset, x-resolution and y-resolution of + * background overlay + * + * Returned Value: + * OK - On success + * -EINVAL - If one of the parameter invalid or if the size of the + * selected source area outside the visible area of the + * destination layer. + * (The visible area usually represents the display size) + * -ECANCELED - Operation cancelled, something goes wrong. + * + ****************************************************************************/ + +static int stm32_dma2d_blend(struct stm32_dma2d_overlay_s *doverlay, + uint32_t destxpos, uint32_t destypos, + struct stm32_dma2d_overlay_s *foverlay, + uint32_t forexpos, uint32_t foreypos, + struct stm32_dma2d_overlay_s *boverlay, + const struct fb_area_s *barea) +{ + int ret; + struct stm32_dma2d_s *priv = &g_dma2ddev; + + lcdinfo("doverlay=%p, destxpos=%" PRId32 ", destypos=%" PRId32 ", " + "foverlay=%p, forexpos=%" PRId32 ", foreypos=%" PRId32 ", " + "boverlay=%p, barea=%p, barea.x=%d, barea.y=%d, barea.w=%d, " + "barea.h=%d\n", doverlay, destxpos, destypos, foverlay, forexpos, + foreypos, boverlay, barea, barea->x, barea->y, barea->w, barea->h); + +#ifdef CONFIG_STM32_FB_CMAP + if (doverlay->fmt == DMA2D_PF_L8) + { + /* CLUT output not supported */ + + lcderr("ERROR: Returning ENOSYS, " + "output to layer with CLUT format not supported.\n"); + return -ENOSYS; + } +#endif + + nxmutex_lock(priv->lock); + + /* Set output pfc */ + + stm32_dma2d_loutpfc(doverlay->fmt); + + /* Set background pfc */ + + stm32_dma2d_lpfc(DMA2D_LAYER_LBACK, boverlay->transp_mode, + boverlay->oinfo->transp.transp, boverlay->fmt); + + /* Set foreground pfc */ + + stm32_dma2d_lpfc(DMA2D_LAYER_LFORE, foverlay->transp_mode, + foverlay->oinfo->transp.transp, foverlay->fmt); + + /* Set background fifo */ + + stm32_dma2d_lfifo(boverlay, DMA2D_LAYER_LBACK, barea->x, barea->y, barea); + + /* Set foreground fifo */ + + stm32_dma2d_lfifo(foverlay, DMA2D_LAYER_LFORE, forexpos, foreypos, barea); + + /* Set output fifo */ + + stm32_dma2d_lfifo(doverlay, DMA2D_LAYER_LOUT, destxpos, destypos, barea); + + /* Set number of lines and pixel per line */ + + stm32_dma2d_llnr(barea); + + /* Set watermark */ + + /* Enable DMA2D blender */ + + stm32_dma2d_control(STM32_DMA2D_CR_MODE_BLEND, STM32_DMA2D_CR_MODE_CLEAR); + + /* Start DMA2D and wait until completed */ + + ret = stm32_dma2d_start(); + + if (ret != OK) + { + ret = -ECANCELED; + lcderr("ERROR: Returning ECANCELED\n"); + } + + nxmutex_unlock(priv->lock); + return ret; +} + +/**************************************************************************** + * Name: stm32_dma2dinitialize + * + * Description: + * Initialize the dma2d controller + * + * Returned Value: + * OK - On success + * An error if initializing failed. + * + ****************************************************************************/ + +int stm32_dma2dinitialize(void) +{ + lcdinfo("Initialize DMA2D driver\n"); + + if (g_initialized == false) + { + /* Abort current dma2d data transfer */ + + stm32_dma2duninitialize(); + + /* Enable dma2d is done in rcc_enableahb1, see + * arch/arm/src/stm32f4/stm32_rcc.c + */ + +#ifdef CONFIG_STM32_FB_CMAP + /* Enable dma2d transfer and clut loading interrupts only */ + + stm32_dma2d_control(DMA2D_CR_TCIE | DMA2D_CR_CTCIE, DMA2D_CR_TEIE | + DMA2D_CR_TWIE | DMA2D_CR_CAEIE | DMA2D_CR_CEIE); +#else + /* Enable dma transfer interrupt only */ + + stm32_dma2d_control(DMA2D_CR_TCIE, DMA2D_CR_TEIE | DMA2D_CR_TWIE | + DMA2D_CR_CAEIE | DMA2D_CR_CTCIE | DMA2D_CR_CEIE); +#endif + + stm32_dma2d_control(DMA2D_CR_TCIE | DMA2D_CR_CTCIE | DMA2D_CR_TEIE | + DMA2D_CR_CAEIE | DMA2D_CR_CTCIE | DMA2D_CR_CEIE, + 0); + + /* Attach DMA2D interrupt vector */ + + irq_attach(g_interrupt.irq, stm32_dma2dirq, NULL); + + /* Enable the IRQ at the NVIC */ + + up_enable_irq(g_interrupt.irq); + + g_initialized = true; + } + + return OK; +} + +/**************************************************************************** + * Name: stm32_dma2duninitialize + * + * Description: + * Uninitialize the dma2d controller + * + ****************************************************************************/ + +void stm32_dma2duninitialize(void) +{ + /* Disable DMA2D interrupts */ + + up_disable_irq(g_interrupt.irq); + irq_detach(g_interrupt.irq); + + /* Abort current dma2d transfer */ + + stm32_dma2d_control(DMA2D_CR_ABORT, 0); + + /* Set initialized state */ + + g_initialized = false; +} + +/**************************************************************************** + * Name: stm32_dma2ddev + * + * Description: + * Get a reference to the dma2d controller. + * + * Returned Value: + * On success - A valid dma2d layer reference + * On error - NULL + * + ****************************************************************************/ + +struct dma2d_layer_s *stm32_dma2ddev(void) +{ + return &g_dma2ddev.dma2d; +} diff --git a/arch/arm/src/common/stm32/stm32_dma2d_m3m4_v1.h b/arch/arm/src/common/stm32/stm32_dma2d_m3m4_v1.h new file mode 100644 index 0000000000000..5bc43e6da99f8 --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_dma2d_m3m4_v1.h @@ -0,0 +1,192 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_dma2d_m3m4_v1.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_DMA2D_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_DMA2D_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#ifdef CONFIG_FB_OVERLAY + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/* This structure describes DMA2D overlay information */ + +struct stm32_dma2d_overlay_s +{ + uint8_t fmt; /* DMA2D pixel format */ + uint8_t transp_mode; /* DMA2D transparency mode */ + fb_coord_t xres; /* X-resolution overlay */ + fb_coord_t yres; /* Y-resolution overlay */ + struct fb_overlayinfo_s *oinfo; /* Framebuffer overlay information */ +}; + +/* DMA2D is controlled by the following interface */ + +struct dma2d_layer_s +{ + /* Name: setclut + * + * Description: + * Set the cmap table for both foreground and background layer. + * Up to 256 colors supported. + * + * Parameter: + * cmap - Reference to the cmap table + * + * Returned Value: + * On success - OK + * On error - -EINVAL + */ + +#ifdef CONFIG_STM32_FB_CMAP + int (*setclut)(const struct fb_cmap_s * cmap); +#endif + + /* Name: fillcolor + * + * Description: + * Fill a specific memory region with a color. + * The caller must ensure that the memory region (area) is within the + * entire overlay. + * + * Parameter: + * oinfo - Reference to overlay information + * area - Reference to the area to fill + * argb - argb8888 color + * + * Returned Value: + * On success - OK + * On error - -EINVAL + */ + + int (*fillcolor)(struct stm32_dma2d_overlay_s *oinfo, + const struct fb_area_s *area, uint32_t argb); + + /* Name: blit + * + * Description: + * Copies memory from a source overlay (defined by sarea) to destination + * overlay position (defined by destxpos and destypos) without + * pixelformat conversion. The caller must ensure that the memory region + * (area) is within the entire overlay. + * + * Parameter: + * doverlay - Reference destination overlay + * destxpos - x-Offset destination overlay + * destypos - y-Offset destination overlay + * soverlay - Reference source overlay + * sarea - Reference source area + * + * Returned Value: + * On success - OK + * On error - -EINVAL + */ + + int (*blit)(struct stm32_dma2d_overlay_s *doverlay, + uint32_t destxpos, uint32_t destypos, + struct stm32_dma2d_overlay_s *soverlay, + const struct fb_area_s *sarea); + + /* Name: blend + * + * Description: + * Blends two source memory areas to a destination memory area with + * pixelformat conversion if necessary. The caller must ensure that the + * memory region (area) is within the entire overlays. + * + * Parameter: + * doverlay - Destination overlay + * destxpos - x-Offset destination overlay + * destypos - y-Offset destination overlay + * foverlay - Foreground overlay + * forexpos - x-Offset foreground overlay + * foreypos - y-Offset foreground overlay + * boverlay - Background overlay + * barea - x-Offset, y-Offset, x-resolution and y-resolution of + * background overlay + * + * Returned Value: + * On success - OK + * On error - -EINVAL or -ECANCELED + */ + + int (*blend)(struct stm32_dma2d_overlay_s *doverlay, + uint32_t destxpos, uint32_t destypos, + struct stm32_dma2d_overlay_s *foverlay, + uint32_t forexpos, uint32_t foreypos, + struct stm32_dma2d_overlay_s *boverlay, + const struct fb_area_s *barea); +}; + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_dma2ddev + * + * Description: + * Get a reference to the DMA2D controller. + * + * Returned Value: + * On success - A valid DMA2D controller reference + * On error - NULL and errno is set to + * -EINVAL if one of the parameter is invalid + * + ****************************************************************************/ + +struct dma2d_layer_s *stm32_dma2ddev(void); + +/**************************************************************************** + * Name: up_dma2dinitialize + * + * Description: + * Initialize the DMA2D controller + * + * Returned Value: + * OK - On success + * An error if initializing failed. + * + ****************************************************************************/ + +int stm32_dma2dinitialize(void); + +/**************************************************************************** + * Name: up_dma2duninitialize + * + * Description: + * Uninitialize the DMA2D controller + * + ****************************************************************************/ + +void stm32_dma2duninitialize(void); + +#endif /* CONFIG_FB_OVERLAY */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_DMA2D_H */ diff --git a/arch/arm/src/common/stm32/stm32_dma_channel_stream.h b/arch/arm/src/common/stm32/stm32_dma_channel_stream.h new file mode 100644 index 0000000000000..aec408a552764 --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_dma_channel_stream.h @@ -0,0 +1,352 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_dma_channel_stream.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_DMA_CHANNEL_STREAM_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_DMA_CHANNEL_STREAM_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include "chip.h" + +#include "hardware/stm32_dma.h" + +#ifdef CONFIG_STM32_HAVE_DMAMUX +# include "hardware/stm32_dmamux.h" +#endif + +/* These definitions provide the bit encoding of the 'status' parameter + * passed to the DMA callback function (see dma_callback_t). + */ + +#if defined(HAVE_IP_DMA_V1) +# define DMA_STATUS_FEIF 0 /* (Not available in F1) */ +# define DMA_STATUS_DMEIF 0 /* (Not available in F1) */ +# define DMA_STATUS_TEIF DMA_CHAN_TEIF_BIT /* Channel Transfer Error */ +# define DMA_STATUS_HTIF DMA_CHAN_HTIF_BIT /* Channel Half Transfer */ +# define DMA_STATUS_TCIF DMA_CHAN_TCIF_BIT /* Channel Transfer Complete */ +#elif defined(HAVE_IP_DMA_V2) +# define DMA_STATUS_FEIF 0 /* Stream FIFO error (ignored) */ +# define DMA_STATUS_DMEIF DMA_STREAM_DMEIF_BIT /* Stream direct mode error */ +# define DMA_STATUS_TEIF DMA_STREAM_TEIF_BIT /* Stream Transfer Error */ +# define DMA_STATUS_HTIF DMA_STREAM_HTIF_BIT /* Stream Half Transfer */ +# define DMA_STATUS_TCIF DMA_STREAM_TCIF_BIT /* Stream Transfer Complete */ +#endif + +#define DMA_STATUS_ERROR (DMA_STATUS_FEIF | DMA_STATUS_DMEIF | DMA_STATUS_TEIF) +#define DMA_STATUS_SUCCESS (DMA_STATUS_TCIF | DMA_STATUS_HTIF) + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/* DMA_HANDLE provides an opaque reference that can be used to represent a + * DMA channel (F1) or a DMA stream (F4). + */ + +typedef void *DMA_HANDLE; + +/* Description: + * This is the type of the callback that is used to inform the user of the + * completion of the DMA. + * + * Input Parameters: + * handle - Refers to the DMA channel or stream + * status - A bit encoded value that provides the completion status. See + * the DMASTATUS_* definitions above. + * arg - A user-provided value that was provided when stm32_dmastart() + * was called. + */ + +typedef void (*dma_callback_t)(DMA_HANDLE handle, uint8_t status, void *arg); + +#ifdef CONFIG_DEBUG_DMA_INFO + +#if defined(HAVE_IP_DMA_V1) +struct stm32_dmaregs_s +{ + uint32_t isr; + uint32_t ccr; + uint32_t cndtr; + uint32_t cpar; + uint32_t cmar; +}; +#elif defined(HAVE_IP_DMA_V2) +struct stm32_dmaregs_s +{ + uint32_t lisr; + uint32_t hisr; + uint32_t scr; + uint32_t sndtr; + uint32_t spar; + uint32_t sm0ar; + uint32_t sm1ar; + uint32_t sfcr; +}; +#else +# error "Unknown STM32 DMA" +#endif +#endif + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_dmachannel + * + * Description: + * Allocate a DMA channel. This function gives the caller mutually + * exclusive access to the DMA channel specified by the 'chan' argument. + * DMA channels are shared on the STM32: Devices sharing the same DMA + * channel cannot do DMA concurrently! See the DMACHAN_* definitions in + * stm32_dma.h. + * + * If the DMA channel is not available, then stm32_dmachannel() will wait + * until the holder of the channel relinquishes the channel by calling + * stm32_dmafree(). WARNING: If you have two devices sharing a DMA + * channel and the code never releases the channel, the stm32_dmachannel + * call for the other will hang forever in this function! Don't let your + * design do that! + * + * Hmm.. I suppose this interface could be extended to make a non-blocking + * version. Feel free to do that if that is what you need. + * + * Input Parameters: + * chan - Identifies the stream/channel resource + * For the STM32 F1, this is simply the channel number as provided by + * the DMACHAN_* definitions in chip/stm32f10xxx_dma.h. + * For the STM32 F4, this is a bit encoded value as provided by the + * the DMAMAP_* definitions in chip/stm32f40xxx_dma.h + * + * Returned Value: + * Provided that 'chan' is valid, this function ALWAYS returns a non-NULL, + * void* DMA channel handle. (If 'chan' is invalid, the function will + * assert if debug is enabled or do something ignorant otherwise). + * + * Assumptions: + * - The caller does not hold he DMA channel. + * - The caller can wait for the DMA channel to be freed if it is no + * available. + * + ****************************************************************************/ + +DMA_HANDLE stm32_dmachannel(unsigned int chan); + +/**************************************************************************** + * Name: stm32_dmafree + * + * Description: + * Release a DMA channel. If another thread is waiting for this DMA + * channel in a call to stm32_dmachannel, then this function will re- + * assign the DMA channel to that thread and wake it up. + * + * NOTE: The 'handle' used in this argument must NEVER be used again + * until stm32_dmachannel() is called again to re-gain access to the + * channel. + * + * Returned Value: + * None + * + * Assumptions: + * - The caller holds the DMA channel. + * - There is no DMA in progress + * + ****************************************************************************/ + +void stm32_dmafree(DMA_HANDLE handle); + +/**************************************************************************** + * Name: stm32_dmasetup + * + * Description: + * Configure DMA before using + * + ****************************************************************************/ + +void stm32_dmasetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr, + size_t ntransfers, uint32_t ccr); + +/**************************************************************************** + * Name: stm32_dmastart + * + * Description: + * Start the DMA transfer + * + * Assumptions: + * - DMA handle allocated by stm32_dmachannel() + * - No DMA in progress + * + ****************************************************************************/ + +void stm32_dmastart(DMA_HANDLE handle, dma_callback_t callback, void *arg, + bool half); + +/**************************************************************************** + * Name: stm32_dmastop + * + * Description: + * Cancel the DMA. After stm32_dmastop() is called, the DMA channel is + * reset and stm32_dmasetup() must be called before stm32_dmastart() can be + * called again + * + * Assumptions: + * - DMA handle allocated by stm32_dmachannel() + * + ****************************************************************************/ + +void stm32_dmastop(DMA_HANDLE handle); + +/**************************************************************************** + * Name: stm32_dmaresidual + * + * Description: + * Returns the number of bytes remaining to be transferred + * + * Assumptions: + * - DMA handle allocated by stm32_dmachannel() + * + ****************************************************************************/ + +size_t stm32_dmaresidual(DMA_HANDLE handle); + +/**************************************************************************** + * Name: stm32_dmacapable + * + * Description: + * Check if the DMA controller can transfer data to/from given memory + * address with the given configuration. This depends on the internal + * connections in the ARM bus matrix of the processor. Note that this only + * applies to memory addresses, it will return false for any peripheral + * address. + * + * Returned Value: + * True, if transfer is possible. + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_DMACAPABLE +bool stm32_dmacapable(uintptr_t maddr, uint32_t count, uint32_t ccr); +#else +# define stm32_dmacapable(maddr, count, ccr) (true) +#endif + +/**************************************************************************** + * Name: stm32_dmasample + * + * Description: + * Sample DMA register contents + * + * Assumptions: + * - DMA handle allocated by stm32_dmachannel() + * + ****************************************************************************/ + +#ifdef CONFIG_DEBUG_DMA_INFO +void stm32_dmasample(DMA_HANDLE handle, struct stm32_dmaregs_s *regs); +#else +# define stm32_dmasample(handle,regs) +#endif + +/**************************************************************************** + * Name: stm32_dmadump + * + * Description: + * Dump previously sampled DMA register contents + * + * Assumptions: + * - DMA handle allocated by stm32_dmachannel() + * + ****************************************************************************/ + +#ifdef CONFIG_DEBUG_DMA_INFO +void stm32_dmadump(DMA_HANDLE handle, const struct stm32_dmaregs_s *regs, + const char *msg); +#else +# define stm32_dmadump(handle,regs,msg) +#endif + +/* High performance, zero latency DMA interrupts need some additional + * interfaces. + * + * TODO: For now the interface is different for STM32 DMAv1 and STM32 DMAv2. + * It should be unified somehow. + */ + +#ifdef CONFIG_ARCH_HIPRI_INTERRUPT + +/**************************************************************************** + * Name: stm32_dma_intack + * + * Description: + * Public visible interface to acknowledge interrupts on DMA channel + * + ****************************************************************************/ + +#if defined(HAVE_IP_DMA_V1) +void stm32_dma_intack(unsigned int chndx, uint32_t isr); +#elif defined(HAVE_IP_DMA_V2) +void stm32_dma_intack(unsigned int controller, uint8_t stream, uint32_t isr); +#endif + +/**************************************************************************** + * Name: stm32_dma_intget + * + * Description: + * Public visible interface to get pending interrupts from DMA channel + * + ****************************************************************************/ + +#if defined(HAVE_IP_DMA_V1) +uint32_t stm32_dma_intget(unsigned int chndx); +#elif defined(HAVE_IP_DMA_V2) +uint8_t stm32_dma_intget(unsigned int controller, uint8_t stream); +#endif + +#endif /* CONFIG_ARCH_HIPRI_INTERRUPT */ + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_DMA_CHANNEL_STREAM_H */ diff --git a/arch/arm/src/common/stm32/stm32_dma_m0_v1_7ch.c b/arch/arm/src/common/stm32/stm32_dma_m0_v1_7ch.c new file mode 100644 index 0000000000000..06ae4eaf7ea15 --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_dma_m0_v1_7ch.c @@ -0,0 +1,796 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_dma_m0_v1_7ch.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include + +#include +#include +#include + +#include + +#include "arm_internal.h" +#include "sched/sched.h" +#include "chip.h" +#include "stm32_dma.h" +#include "stm32.h" + +/* This file supports the STM32 DMA IP core version 1 - F0, F1, F3, L0, L1, + * L4 + * + * F0, L0 and L4 have the additional CSELR register which is used to remap + * the DMA requests for each channel. + */ + +#ifdef CONFIG_STM32_HAVE_DMAMUX +# error DMAMUX not supported here. Look at stm32_dma_v1mux.c +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define DMA1_NCHANNELS 7 + +#if STM32_NDMA > 1 +# define DMA2_NCHANNELS 5 +# define DMA_NCHANNELS (DMA1_NCHANNELS+DMA2_NCHANNELS) +#else +# define DMA_NCHANNELS DMA1_NCHANNELS +#endif + +/* Convert the DMA channel base address to the DMA register block address */ + +#define DMA_BASE(ch) (ch & 0xfffffc00) + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/* This structure describes one DMA channel */ + +struct stm32_dma_s +{ + uint8_t chan; /* DMA channel number (0-6) */ +#ifdef DMA_HAVE_CSELR + uint8_t function; /* DMA peripheral connected to this channel (0-7) */ +#endif + uint8_t irq; /* DMA channel IRQ number */ + sem_t sem; /* Used to wait for DMA channel to become available */ + uint32_t base; /* DMA register channel base address */ + dma_callback_t callback; /* Callback invoked when the DMA completes */ + void *arg; /* Argument passed to callback function */ +}; + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* This array describes the state of each DMA */ + +static struct stm32_dma_s g_dma[DMA_NCHANNELS] = +{ + { + .chan = 0, + .irq = STM32_IRQ_DMA1CH1, + .sem = SEM_INITIALIZER(1), + .base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(0), + }, + { + .chan = 1, + .irq = STM32_IRQ_DMA1CH2, + .sem = SEM_INITIALIZER(1), + .base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(1), + }, + { + .chan = 2, + .irq = STM32_IRQ_DMA1CH3, + .sem = SEM_INITIALIZER(1), + .base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(2), + }, + { + .chan = 3, + .irq = STM32_IRQ_DMA1CH4, + .sem = SEM_INITIALIZER(1), + .base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(3), + }, + { + .chan = 4, + .irq = STM32_IRQ_DMA1CH5, + .sem = SEM_INITIALIZER(1), + .base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(4), + }, + { + .chan = 5, + .irq = STM32_IRQ_DMA1CH6, + .sem = SEM_INITIALIZER(1), + .base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(5), + }, + { + .chan = 6, + .irq = STM32_IRQ_DMA1CH7, + .sem = SEM_INITIALIZER(1), + .base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(6), + }, +#if STM32_NDMA > 1 + { + .chan = 0, + .irq = STM32_IRQ_DMA2CH1, + .sem = SEM_INITIALIZER(1), + .base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(0), + }, + { + .chan = 1, + .irq = STM32_IRQ_DMA2CH2, + .sem = SEM_INITIALIZER(1), + .base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(1), + }, + { + .chan = 2, + .irq = STM32_IRQ_DMA2CH3, + .sem = SEM_INITIALIZER(1), + .base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(2), + }, + { + .chan = 3, + .irq = STM32_IRQ_DMA2CH4, + .sem = SEM_INITIALIZER(1), + .base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(3), + }, + { + .chan = 4, + .irq = STM32_IRQ_DMA2CH5, + .sem = SEM_INITIALIZER(1), + .base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(4), + }, +#endif +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * DMA register access functions + ****************************************************************************/ + +/* Get non-channel register from DMA1 or DMA2 */ + +static inline uint32_t dmabase_getreg(struct stm32_dma_s *dmach, + uint32_t offset) +{ + return getreg32(DMA_BASE(dmach->base) + offset); +} + +/* Write to non-channel register in DMA1 or DMA2 */ + +static inline void dmabase_putreg(struct stm32_dma_s *dmach, uint32_t offset, + uint32_t value) +{ + putreg32(value, DMA_BASE(dmach->base) + offset); +} + +/* Get channel register from DMA1 or DMA2 */ + +static inline uint32_t dmachan_getreg(struct stm32_dma_s *dmach, + uint32_t offset) +{ + return getreg32(dmach->base + offset); +} + +/* Write to channel register in DMA1 or DMA2 */ + +static inline void dmachan_putreg(struct stm32_dma_s *dmach, + uint32_t offset, uint32_t value) +{ + putreg32(value, dmach->base + offset); +} + +/**************************************************************************** + * Name: stm32_dmachandisable + * + * Description: + * Disable the DMA channel + * + ****************************************************************************/ + +static void stm32_dmachandisable(struct stm32_dma_s *dmach) +{ + uint32_t regval; + + /* Disable all interrupts at the DMA controller */ + + regval = dmachan_getreg(dmach, STM32_DMACHAN_CCR_OFFSET); + regval &= ~DMA_CCR_ALLINTS; + + /* Disable the DMA channel */ + + regval &= ~DMA_CCR_EN; + dmachan_putreg(dmach, STM32_DMACHAN_CCR_OFFSET, regval); + + /* Clear pending channel interrupts */ + + dmabase_putreg(dmach, STM32_DMA_IFCR_OFFSET, + DMA_ISR_CHAN_MASK(dmach->chan)); +} + +/**************************************************************************** + * Name: stm32_dmainterrupt + * + * Description: + * DMA interrupt handler + * + ****************************************************************************/ + +static int stm32_dmainterrupt(int irq, void *context, void *arg) +{ + struct stm32_dma_s *dmach; + uint32_t isr; + int chndx = 0; + + /* Get the channel structure from the interrupt number */ + + if (irq >= STM32_IRQ_DMA1CH1 && irq <= STM32_IRQ_DMA1CH7) + { + chndx = irq - STM32_IRQ_DMA1CH1; + } + else +#if STM32_NDMA > 1 + if (irq >= STM32_IRQ_DMA2CH1 && irq <= STM32_IRQ_DMA2CH5) + { + chndx = irq - STM32_IRQ_DMA2CH1 + DMA1_NCHANNELS; + } + else +#endif + { + DEBUGPANIC(); + } + + dmach = &g_dma[chndx]; + + /* Get the interrupt status (for this channel only) */ + + isr = dmabase_getreg(dmach, STM32_DMA_ISR_OFFSET) & + DMA_ISR_CHAN_MASK(dmach->chan); + + /* Clear the interrupts we are handling */ + + dmabase_putreg(dmach, STM32_DMA_IFCR_OFFSET, isr); + + /* Invoke the callback */ + + if (dmach->callback) + { + dmach->callback(dmach, isr >> DMA_ISR_CHAN_SHIFT(dmach->chan), + dmach->arg); + } + + return OK; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_dmainitialize + * + * Description: + * Initialize the DMA subsystem + * + * Returned Value: + * None + * + ****************************************************************************/ + +void weak_function arm_dma_initialize(void) +{ + struct stm32_dma_s *dmach; + int chndx; + + /* Initialize each DMA channel */ + + for (chndx = 0; chndx < DMA_NCHANNELS; chndx++) + { + dmach = &g_dma[chndx]; + + /* Attach DMA interrupt vectors */ + + irq_attach(dmach->irq, stm32_dmainterrupt, NULL); + + /* Disable the DMA channel */ + + stm32_dmachandisable(dmach); + + /* Enable the IRQ at the NVIC (still disabled at the DMA controller) */ + + up_enable_irq(dmach->irq); + } +} + +/**************************************************************************** + * Name: stm32_dmachannel + * + * Description: + * Allocate a DMA channel. This function gives the caller mutually + * exclusive access to the DMA channel specified by the 'chndx' argument. + * DMA channels are shared on the STM32: Devices sharing the same DMA + * channel cannot do DMA concurrently! See the DMACHAN_* definitions in + * stm32_dma.h. + * + * If the DMA channel is not available, then stm32_dmachannel() will wait + * until the holder of the channel relinquishes the channel by calling + * stm32_dmafree(). WARNING: If you have two devices sharing a DMA + * channel and the code never releases the channel, the stm32_dmachannel + * call for the other will hang forever in this function! Don't let your + * design do that! + * + * Hmm.. I suppose this interface could be extended to make a non-blocking + * version. Feel free to do that if that is what you need. + * + * Input Parameters: + * chndx - Identifies the stream/channel resource. For the STM32 F1, this + * is simply the channel number as provided by the DMACHAN_* definitions + * in chip/stm32f10xxx_dma.h. + * + * Returned Value: + * Provided that 'chndx' is valid, this function ALWAYS returns a non-NULL, + * void* DMA channel handle. (If 'chndx' is invalid, the function will + * assert if debug is enabled or do something ignorant otherwise). + * + * Assumptions: + * - The caller does not hold he DMA channel. + * - The caller can wait for the DMA channel to be freed if it is no + * available. + * + ****************************************************************************/ + +DMA_HANDLE stm32_dmachannel(unsigned int chndef) +{ + int chndx = 0; + struct stm32_dma_s *dmach = NULL; + int ret; + +#ifdef DMA_HAVE_CSELR + chndx = (chndef & DMACHAN_SETTING_CHANNEL_MASK) >> + DMACHAN_SETTING_CHANNEL_SHIFT; +#else + chndx = chndef; +#endif + + dmach = &g_dma[chndx]; + + DEBUGASSERT(chndx < DMA_NCHANNELS); + + /* Get exclusive access to the DMA channel -- OR wait until the channel + * is available if it is currently being used by another driver + */ + + ret = nxsem_wait_uninterruptible(&dmach->sem); + if (ret < 0) + { + return NULL; + } + + /* The caller now has exclusive use of the DMA channel */ + +#ifdef DMA_HAVE_CSELR + /* Define the peripheral that will use the channel. This is stored until + * dmasetup is called. + */ + + dmach->function = (chndef & DMACHAN_SETTING_FUNCTION_MASK) >> + DMACHAN_SETTING_FUNCTION_SHIFT; +#endif + + return (DMA_HANDLE)dmach; +} + +/**************************************************************************** + * Name: stm32_dmafree + * + * Description: + * Release a DMA channel. If another thread is waiting for this DMA + * channel in a call to stm32_dmachannel, then this function will re-assign + * the DMA channel to that thread and wake it up. NOTE: The 'handle' used + * in this argument must NEVER be used again until stm32_dmachannel() is + * called again to re-gain access to the channel. + * + * Returned Value: + * None + * + * Assumptions: + * - The caller holds the DMA channel. + * - There is no DMA in progress + * + ****************************************************************************/ + +void stm32_dmafree(DMA_HANDLE handle) +{ + struct stm32_dma_s *dmach = (struct stm32_dma_s *)handle; + + DEBUGASSERT(handle != NULL); + + /* Release the channel */ + + nxsem_post(&dmach->sem); +} + +/**************************************************************************** + * Name: stm32_dmasetup + * + * Description: + * Configure DMA before using + * + ****************************************************************************/ + +void stm32_dmasetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr, + size_t ntransfers, uint32_t ccr) +{ + struct stm32_dma_s *dmach = (struct stm32_dma_s *)handle; + uint32_t regval; + + /* Then DMA_CNDTRx register can only be modified if the DMA channel is + * disabled. + */ + + regval = dmachan_getreg(dmach, STM32_DMACHAN_CCR_OFFSET); + regval &= ~(DMA_CCR_EN); + dmachan_putreg(dmach, STM32_DMACHAN_CCR_OFFSET, regval); + + /* Set the peripheral register address in the DMA_CPARx register. The data + * will be moved from/to this address to/from the memory after the + * peripheral event. + */ + + dmachan_putreg(dmach, STM32_DMACHAN_CPAR_OFFSET, paddr); + + /* Set the memory address in the DMA_CMARx register. The data will be + * written to or read from this memory after the peripheral event. + */ + + dmachan_putreg(dmach, STM32_DMACHAN_CMAR_OFFSET, maddr); + + /* Configure the total number of data to be transferred in the DMA_CNDTRx + * register. After each peripheral event, this value will be decremented. + */ + + dmachan_putreg(dmach, STM32_DMACHAN_CNDTR_OFFSET, ntransfers); + + /* Configure the channel priority using the PL[1:0] bits in the DMA_CCRx + * register. Configure data transfer direction, circular mode, peripheral + * and memory incremented mode, peripheral & memory data size, and + * interrupt after half and/or full transfer in the DMA_CCRx register. + */ + + regval = dmachan_getreg(dmach, STM32_DMACHAN_CCR_OFFSET); + regval &= ~(DMA_CCR_MEM2MEM | DMA_CCR_PL_MASK | DMA_CCR_MSIZE_MASK | + DMA_CCR_PSIZE_MASK | DMA_CCR_MINC | DMA_CCR_PINC | + DMA_CCR_CIRC | DMA_CCR_DIR); + ccr &= (DMA_CCR_MEM2MEM | DMA_CCR_PL_MASK | DMA_CCR_MSIZE_MASK | + DMA_CCR_PSIZE_MASK | DMA_CCR_MINC | DMA_CCR_PINC | + DMA_CCR_CIRC | DMA_CCR_DIR); + regval |= ccr; + dmachan_putreg(dmach, STM32_DMACHAN_CCR_OFFSET, regval); + +#ifdef DMA_HAVE_CSELR + /* Define peripheral indicated in dmach->function */ + + regval = dmabase_getreg(dmach, STM32_DMA_CSELR_OFFSET); + regval &= ~(0x0f << (dmach->chan << 2)); + regval |= (dmach->function << (dmach->chan << 2)); + dmabase_putreg(dmach, STM32_DMA_CSELR_OFFSET, regval); +#endif +} + +/**************************************************************************** + * Name: stm32_dmastart + * + * Description: + * Start the DMA transfer + * + * Assumptions: + * - DMA handle allocated by stm32_dmachannel() + * - No DMA in progress + * + ****************************************************************************/ + +void stm32_dmastart(DMA_HANDLE handle, dma_callback_t callback, + void *arg, bool half) +{ + struct stm32_dma_s *dmach = (struct stm32_dma_s *)handle; + uint32_t ccr; + + DEBUGASSERT(handle != NULL); + + /* Save the callback info. This will be invoked when the DMA completes. */ + + dmach->callback = callback; + dmach->arg = arg; + + /* Activate the channel by setting the ENABLE bit in the DMA_CCRx register. + * As soon as the channel is enabled, it can serve any DMA request from the + * peripheral connected on the channel. + */ + + ccr = dmachan_getreg(dmach, STM32_DMACHAN_CCR_OFFSET); + ccr |= DMA_CCR_EN; + + /* In normal mode, interrupt at either half or full completion. In circular + * mode, always interrupt on buffer wrap, and optionally interrupt at the + * halfway point. + */ + + if ((ccr & DMA_CCR_CIRC) == 0) + { + /* Once half of the bytes are transferred, the half-transfer flag + * (HTIF) is set and an interrupt is generated if the Half-Transfer + * Interrupt Enable bit (HTIE) is set. At the end of the transfer, the + * Transfer Complete Flag (TCIF) is set and an interrupt is generated + * if the Transfer Complete Interrupt Enable bit (TCIE) is set. + */ + + ccr |= (half ? (DMA_CCR_HTIE | DMA_CCR_TEIE) : + (DMA_CCR_TCIE | DMA_CCR_TEIE)); + } + else + { + /* In nonstop mode, when the transfer completes it immediately resets + * and starts again. The transfer-complete interrupt is thus always + * enabled, and the half-complete interrupt can be used in circular + * mode to determine when the buffer is half-full or in double-buffered + * mode to determine when one of the two buffers is full. + */ + + ccr |= (half ? DMA_CCR_HTIE : 0) | DMA_CCR_TCIE | DMA_CCR_TEIE; + } + + dmachan_putreg(dmach, STM32_DMACHAN_CCR_OFFSET, ccr); +} + +/**************************************************************************** + * Name: stm32_dmastop + * + * Description: + * Cancel the DMA. After stm32_dmastop() is called, the DMA channel is + * reset and stm32_dmasetup() must be called before stm32_dmastart() can be + * called again + * + * Assumptions: + * - DMA handle allocated by stm32_dmachannel() + * + ****************************************************************************/ + +void stm32_dmastop(DMA_HANDLE handle) +{ + struct stm32_dma_s *dmach = (struct stm32_dma_s *)handle; + stm32_dmachandisable(dmach); +} + +/**************************************************************************** + * Name: stm32_dmaresidual + * + * Description: + * Returns the number of bytes remaining to be transferred + * + * Assumptions: + * - DMA handle allocated by stm32_dmachannel() + * + ****************************************************************************/ + +size_t stm32_dmaresidual(DMA_HANDLE handle) +{ + struct stm32_dma_s *dmach = (struct stm32_dma_s *)handle; + + return dmachan_getreg(dmach, STM32_DMACHAN_CNDTR_OFFSET); +} + +/**************************************************************************** + * Name: stm32_dmacapable + * + * Description: + * Check if the DMA controller can transfer data to/from given memory + * address. This depends on the internal connections in the ARM bus matrix + * of the processor. Note that this only applies to memory addresses, it + * will return false for any peripheral address. + * + * Returned Value: + * True, if transfer is possible. + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_DMACAPABLE +bool stm32_dmacapable(uintptr_t maddr, uint32_t count, uint32_t ccr) +{ + uint32_t transfer_size; + uint32_t mend; + + /* Verify that the address conforms to the memory transfer size. + * Transfers to/from memory performed by the DMA controller are + * required to be aligned to their size. + * + * See ST RM0090 rev4, section 9.3.11 + * + * Compute mend inline to avoid a possible non-constant integer + * multiply. + */ + + switch (ccr & DMA_CCR_MSIZE_MASK) + { + case DMA_CCR_MSIZE_8BITS: + transfer_size = 1; + mend = maddr + count - 1; + break; + + case DMA_CCR_MSIZE_16BITS: + transfer_size = 2; + mend = maddr + (count << 1) - 1; + break; + + case DMA_CCR_MSIZE_32BITS: + transfer_size = 4; + mend = maddr + (count << 2) - 1; + break; + + default: + return false; + } + + if ((maddr & (transfer_size - 1)) != 0) + { + return false; + } + + /* Verify that the transfer is to a memory region that supports DMA. */ + + if ((maddr & STM32_REGION_MASK) != (mend & STM32_REGION_MASK)) + { + return false; + } + + switch (maddr & STM32_REGION_MASK) + { + case STM32_SRAM_BASE: + case STM32_CODE_BASE: + + /* All RAM and flash is supported */ + + return true; + + default: + + /* Everything else is unsupported by DMA */ + + return false; + } +} +#endif + +/**************************************************************************** + * Name: stm32_dmasample + * + * Description: + * Sample DMA register contents + * + * Assumptions: + * - DMA handle allocated by stm32_dmachannel() + * + ****************************************************************************/ + +#ifdef CONFIG_DEBUG_DMA_INFO +void stm32_dmasample(DMA_HANDLE handle, struct stm32_dmaregs_s *regs) +{ + struct stm32_dma_s *dmach = (struct stm32_dma_s *)handle; + irqstate_t flags; + + flags = enter_critical_section(); + regs->isr = dmabase_getreg(dmach, STM32_DMA_ISR_OFFSET); +#ifdef DMA_HAVE_CSELR + regs->cselr = dmabase_getreg(dmach, STM32_DMA_CSELR_OFFSET); +#endif + regs->ccr = dmachan_getreg(dmach, STM32_DMACHAN_CCR_OFFSET); + regs->cndtr = dmachan_getreg(dmach, STM32_DMACHAN_CNDTR_OFFSET); + regs->cpar = dmachan_getreg(dmach, STM32_DMACHAN_CPAR_OFFSET); + regs->cmar = dmachan_getreg(dmach, STM32_DMACHAN_CMAR_OFFSET); + leave_critical_section(flags); +} +#endif + +/**************************************************************************** + * Name: stm32_dmadump + * + * Description: + * Dump previously sampled DMA register contents + * + * Assumptions: + * - DMA handle allocated by stm32_dmachannel() + * + ****************************************************************************/ + +#ifdef CONFIG_DEBUG_DMA_INFO +void stm32_dmadump(DMA_HANDLE handle, const struct stm32_dmaregs_s *regs, + const char *msg) +{ + struct stm32_dma_s *dmach = (struct stm32_dma_s *)handle; + uint32_t dmabase = DMA_BASE(dmach->base); + + dmainfo("DMA Registers: %s\n", msg); + dmainfo(" ISRC[%08" PRIx32 "]: %08" PRIx32 "\n", + dmabase + STM32_DMA_ISR_OFFSET, regs->isr); +#ifdef DMA_HAVE_CSELR + dmainfo(" CSELR[%08" PRIx32 "]: %08" PRIx32 "\n", + dmabase + STM32_DMA_CSELR_OFFSET, regs->cselr); +#endif + dmainfo(" CCR[%08" PRIx32 "]: %08" PRIx32 "\n", + dmach->base + STM32_DMACHAN_CCR_OFFSET, regs->ccr); + dmainfo(" CNDTR[%08" PRIx32 "]: %08" PRIx32 "\n", + dmach->base + STM32_DMACHAN_CNDTR_OFFSET, regs->cndtr); + dmainfo(" CPAR[%08" PRIx32 "]: %08" PRIx32 "\n", + dmach->base + STM32_DMACHAN_CPAR_OFFSET, regs->cpar); + dmainfo(" CMAR[%08" PRIx32 "]: %08" PRIx32 "\n", + dmach->base + STM32_DMACHAN_CMAR_OFFSET, regs->cmar); +} +#endif + +#ifdef CONFIG_ARCH_HIPRI_INTERRUPT + +/**************************************************************************** + * Name: stm32_dma_intack + * + * Description: + * Public visible interface to acknowledge interrupts on DMA channel + * + ****************************************************************************/ + +void stm32_dma_intack(unsigned int chndx, uint32_t isr) +{ + struct stm32_dma_s *dmach = &g_dma[chndx]; + + dmabase_putreg(dmach, STM32_DMA_IFCR_OFFSET, isr); +} + +/**************************************************************************** + * Name: stm32_dma_intget + * + * Description: + * Public visible interface to get pending interrupts from DMA channel + * + ****************************************************************************/ + +uint32_t stm32_dma_intget(unsigned int chndx) +{ + struct stm32_dma_s *dmach = &g_dma[chndx]; + + return dmabase_getreg(dmach, STM32_DMA_ISR_OFFSET) & + DMA_ISR_CHAN_MASK(dmach->chan); +} +#endif /* CONFIG_ARCH_HIPRI_INTERRUPT */ diff --git a/arch/arm/src/common/stm32/stm32_dma_m0_v1_7ch_dmamux.c b/arch/arm/src/common/stm32/stm32_dma_m0_v1_7ch_dmamux.c new file mode 100644 index 0000000000000..756c7031663f7 --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_dma_m0_v1_7ch_dmamux.c @@ -0,0 +1,1463 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_dma_m0_v1_7ch_dmamux.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* Ported from arch/arm/src/common/stm32/stm32_dma_m0_v1_7ch_dmamux.c */ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include "arm_internal.h" +#include "sched/sched.h" +#include "stm32_dma.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define DMAMUX_NUM 1 +#define DMA_CONTROLLERS 2 + +#ifdef CONFIG_STM32_DMA1 +# if defined(CONFIG_ARCH_CHIP_STM32C0) || \ + defined(CONFIG_STM32_STM32G03X) || \ + defined(CONFIG_STM32_STM32G041) +# define DMA1_NCHAN 5 +# define DMA2_NCHAN 0 +# elif defined(CONFIG_STM32_STM32G05X) || \ + defined(CONFIG_STM32_STM32G061) || \ + defined(CONFIG_STM32_STM32G07X) || \ + defined(CONFIG_STM32_STM32G081) +# define DMA1_NCHAN 7 +# define DMA2_NCHAN 0 +# elif defined(CONFIG_STM32_STM32G0BX) || \ + defined(CONFIG_STM32_STM32G0C1) +# define DMA1_NCHAN 7 +# define DMA2_NCHAN 5 +# else +# error "Unsupported STM32F0L0G0 subfamily" +# endif +#else +# define DMA1_NCHAN 0 +# define DMA2_NCHAN 0 +#endif + +#define DMA1_FIRST (0) +#define DMA1_LAST (DMA1_FIRST+DMA1_NCHAN) +#define DMA2_FIRST (DMA1_LAST) +#define DMA2_LAST (DMA2_FIRST+DMA2_NCHAN) + +/* All available DMA channels */ + +#define DMA_NCHANNELS (DMA1_NCHAN + DMA2_NCHAN) + +/* DMAMUX channels */ + +#if defined(CONFIG_ARCH_CHIP_STM32C0) || \ + defined(CONFIG_STM32_STM32G03X) || \ + defined(CONFIG_STM32_STM32G041) +# define DMAMUX_NCHANNELS 5 +#elif defined(CONFIG_STM32_STM32G05X) || \ + defined(CONFIG_STM32_STM32G061) || \ + defined(CONFIG_STM32_STM32G07X) || \ + defined(CONFIG_STM32_STM32G081) +# define DMAMUX_NCHANNELS 7 +#elif defined(CONFIG_STM32_STM32G0BX) || \ + defined(CONFIG_STM32_STM32G0C1) +# define DMAMUX_NCHANNELS 12 +#else +# error "Unknown chip for DMAMUX channel count" +#endif + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/* This structure described one DMAMUX device */ + +struct stm32_dmamux_s +{ + uint8_t id; /* DMAMUX id */ + uint8_t nchan; /* DMAMUX channels */ + uint32_t base; /* DMAMUX base address */ +}; + +typedef const struct stm32_dmamux_s *DMA_MUX; + +/* This structure describes one DMA controller */ + +struct stm32_dma_s +{ + uint8_t first; /* Offset in stm32_dmach_s array */ + uint8_t nchan; /* Number of channels */ + uint8_t dmamux_offset; /* DMAMUX channel offset */ + uint32_t base; /* Base address */ + DMA_MUX dmamux; /* DMAMUX associated with controller */ +}; + +/* This structure describes one DMA channel (DMA1, DMA2) */ + +struct stm32_dmach_s +{ + bool used; /* Channel in use */ + uint8_t dmamux_req; /* Configured DMAMUX input request */ + uint8_t ctrl; /* DMA controller */ + uint8_t chan; /* DMA channel channel id */ + uint8_t irq; /* DMA channel IRQ number */ + uint8_t shift; /* IFCR bit shift value */ + uint32_t base; /* DMA register channel base address */ + dma_callback_t callback; /* Callback invoked when the DMA completes */ + void *arg; /* Argument passed to callback function */ +}; + +typedef struct stm32_dmach_s *DMA_CHANNEL; + +/* DMA operations */ + +struct stm32_dma_ops_s +{ + /* Disable the DMA transfer */ + + void (*dma_disable)(DMA_CHANNEL dmachan); + + /* DMA interrupt */ + + int (*dma_interrupt)(int irq, void *context, void *arg); + + /* Setup the DMA */ + + void (*dma_setup)(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr, + size_t ntransfers, uint32_t ccr); + + /* Start the DMA */ + + void (*dma_start)(DMA_HANDLE handle, dma_callback_t callback, + void *arg, bool half); + + /* Read remaining DMA bytes */ + + size_t (*dma_residual)(DMA_HANDLE handle); + + /* Check the DMA configuration */ + + bool (*dma_capable)(uint32_t maddr, uint32_t count, uint32_t ccr); + +#ifdef CONFIG_DEBUG_DMA_INFO + /* Sample the DMA registers */ + + void (*dma_sample)(DMA_HANDLE handle, struct stm32_dmaregs_s *regs); + + /* Dump the DMA registers */ + + void (*dma_dump)(DMA_HANDLE handle, + const struct stm32_dmaregs_s *regs, + const char *msg); +#endif +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +#if defined(CONFIG_STM32_DMA1) || defined(CONFIG_STM32_DMA2) +static void stm32_dma12_disable(DMA_CHANNEL dmachan); +static int stm32_dma12_interrupt(int irq, void *context, void *arg); +static void stm32_dma12_setup(DMA_HANDLE handle, uint32_t paddr, + uint32_t maddr, size_t ntransfers, + uint32_t ccr); +static void stm32_dma12_start(DMA_HANDLE handle, dma_callback_t callback, + void *arg, bool half); +static size_t stm32_dma12_residual(DMA_HANDLE handle); +#ifdef CONFIG_DEBUG_DMA_INFO +static void stm32_dma12_sample(DMA_HANDLE handle, + struct stm32_dmaregs_s *regs); +static void stm32_dma12_dump(DMA_HANDLE handle, + const struct stm32_dmaregs_s *regs, + const char *msg); +#endif +#endif + +static uint32_t dmachan_getbase(DMA_CHANNEL dmachan); +static uint32_t dmabase_getreg(DMA_CHANNEL dmachan, uint32_t offset); +static void dmabase_putreg(DMA_CHANNEL dmachan, uint32_t offset, + uint32_t value); +static uint32_t dmachan_getreg(DMA_CHANNEL dmachan, uint32_t offset); +static void dmachan_putreg(DMA_CHANNEL dmachan, uint32_t offset, + uint32_t value); +static void dmamux_putreg(DMA_MUX dmamux, uint32_t offset, uint32_t value); +#ifdef CONFIG_DEBUG_DMA_INFO +static uint32_t dmamux_getreg(DMA_MUX dmamux, uint32_t offset); +static void stm32_dmamux_sample(DMA_MUX dmamux, uint8_t chan, + struct stm32_dmaregs_s *regs); +static void stm32_dmamux_dump(DMA_MUX dmamux, uint8_t channel, + const struct stm32_dmaregs_s *regs); +#endif +static DMA_CHANNEL stm32_dma_channel_get(uint8_t channel, + uint8_t controller); +static void stm32_gdma_limits_get(uint8_t controller, uint8_t *first, + uint8_t *last); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* Operations specific to DMA controller */ + +static const struct stm32_dma_ops_s g_dma_ops[DMA_CONTROLLERS] = +{ +#ifdef CONFIG_STM32_DMA1 + /* 0 - DMA1 */ + + { + .dma_disable = stm32_dma12_disable, + .dma_interrupt = stm32_dma12_interrupt, + .dma_setup = stm32_dma12_setup, + .dma_start = stm32_dma12_start, + .dma_residual = stm32_dma12_residual, +#ifdef CONFIG_DEBUG_DMA_INFO + .dma_sample = stm32_dma12_sample, + .dma_dump = stm32_dma12_dump, +#endif + }, +#else + { + NULL + }, +#endif + +#ifdef CONFIG_STM32_DMA2 + /* 1 - DMA2 */ + + { + .dma_disable = stm32_dma12_disable, + .dma_interrupt = stm32_dma12_interrupt, + .dma_setup = stm32_dma12_setup, + .dma_start = stm32_dma12_start, + .dma_residual = stm32_dma12_residual, +#ifdef CONFIG_DEBUG_DMA_INFO + .dma_sample = stm32_dma12_sample, + .dma_dump = stm32_dma12_dump, +#endif + } +#else + { + NULL + } +#endif +}; + +/* This array describes the state of DMAMUX controller */ + +static const struct stm32_dmamux_s g_dmamux[DMAMUX_NUM] = +{ + { + .id = 1, + .nchan = DMAMUX_NCHANNELS, + .base = STM32_DMAMUX1_BASE + } +}; + +/* This array describes the state of each controller */ + +static const struct stm32_dma_s g_dma[DMA_NCHANNELS] = +{ +#ifdef CONFIG_STM32_DMA1 + /* 0 - DMA1 */ + + { + .base = STM32_DMA1_BASE, + .first = DMA1_FIRST, + .nchan = DMA1_NCHAN, + .dmamux = &g_dmamux[DMAMUX1], /* DMAMUX1 channels 0-6 */ + .dmamux_offset = 0 + }, +#endif + +#ifdef CONFIG_STM32_DMA2 + /* 1 - DMA2 */ + + { + .base = STM32_DMA2_BASE, + .first = DMA2_FIRST, + .nchan = DMA2_NCHAN, + .dmamux = &g_dmamux[DMAMUX1], /* DMAMUX1 channels 7-13 */ + .dmamux_offset = 7 + } +#endif +}; + +/* This array describes the state of each DMA channel. */ + +static struct stm32_dmach_s g_dmach[DMA_NCHANNELS] = +{ +#ifdef CONFIG_STM32_DMA1 + /* DMA1 */ + + { + .ctrl = DMA1, + .chan = 0, + .irq = STM32_IRQ_DMA1CH1, + .shift = DMA_CHAN_SHIFT(0), + .base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(0), + }, + + { + .ctrl = DMA1, + .chan = 1, + .irq = STM32_IRQ_DMA1CH2, + .shift = DMA_CHAN_SHIFT(1), + .base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(1), + }, + + { + .ctrl = DMA1, + .chan = 2, + .irq = STM32_IRQ_DMA1CH3, + .shift = DMA_CHAN_SHIFT(2), + .base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(2), + }, + + { + .ctrl = DMA1, + .chan = 3, + .irq = STM32_IRQ_DMA1CH4, + .shift = DMA_CHAN_SHIFT(3), + .base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(3), + }, + + { + .ctrl = DMA1, + .chan = 4, + .irq = STM32_IRQ_DMA1CH5, + .shift = DMA_CHAN_SHIFT(4), + .base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(4), + }, + +# if DMA1_NCHAN > 5 + { + .ctrl = DMA1, + .chan = 5, + .irq = STM32_IRQ_DMA1CH6, + .shift = DMA_CHAN_SHIFT(5), + .base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(5), + }, +# endif + +# if DMA1_NCHAN > 6 + { + .ctrl = DMA1, + .chan = 6, + .irq = STM32_IRQ_DMA1CH7, + .shift = DMA_CHAN_SHIFT(6), + .base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(6), + }, +# endif + +# if DMA1_NCHAN > 7 + { + .ctrl = DMA1, + .chan = 7, + .irq = STM32_IRQ_DMA1CH8, + .shift = DMA_CHAN_SHIFT(7), + .base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(7), + }, +# endif +#endif + +#ifdef CONFIG_STM32_DMA2 + /* DMA2 */ + + { + .ctrl = DMA2, + .chan = 0, + .irq = STM32_IRQ_DMA2CH1, + .shift = DMA_CHAN_SHIFT(0), + .base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(0), + }, + + { + .ctrl = DMA2, + .chan = 1, + .irq = STM32_IRQ_DMA2CH2, + .shift = DMA_CHAN_SHIFT(1), + .base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(1), + }, + + { + .ctrl = DMA2, + .chan = 2, + .irq = STM32_IRQ_DMA2CH3, + .shift = DMA_CHAN_SHIFT(2), + .base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(2), + }, + + { + .ctrl = DMA2, + .chan = 3, + .irq = STM32_IRQ_DMA2CH4, + .shift = DMA_CHAN_SHIFT(3), + .base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(3), + }, + + { + .ctrl = DMA2, + .chan = 4, + .irq = STM32_IRQ_DMA2CH5, + .shift = DMA_CHAN_SHIFT(4), + .base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(4), + }, + +# if DMA2_NCHAN > 5 + { + .ctrl = DMA2, + .chan = 5, + .irq = STM32_IRQ_DMA2CH6, + .shift = DMA_CHAN_SHIFT(5), + .base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(5), + }, +# endif + +# if DMA2_NCHAN > 6 + { + .ctrl = DMA2, + .chan = 6, + .irq = STM32_IRQ_DMA2CH7, + .shift = DMA_CHAN_SHIFT(6), + .base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(6), + }, +# endif + +# if DMA2_NCHAN > 7 + { + .ctrl = DMA2, + .chan = 7, + .irq = STM32_IRQ_DMA2CH8, + .shift = DMA_CHAN_SHIFT(7), + .base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(7), + }, +# endif +#endif +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * DMA register access functions + ****************************************************************************/ + +/**************************************************************************** + * Name: dmachan_getbase + * + * Description: + * Get base DMA address for dmachan + * + ****************************************************************************/ + +static uint32_t dmachan_getbase(DMA_CHANNEL dmachan) +{ + uint8_t controller = dmachan->ctrl; + + return g_dma[controller].base; +} + +/**************************************************************************** + * Name: dmabase_getreg + * + * Description: + * Get non-channel register from DMA controller + * + ****************************************************************************/ + +static uint32_t dmabase_getreg(DMA_CHANNEL dmachan, uint32_t offset) +{ + uint32_t dmabase = dmachan_getbase(dmachan); + + return getreg32(dmabase + offset); +} + +/**************************************************************************** + * Name: dmabase_putreg + * + * Description: + * Write to non-channel register in DMA controller + * + ****************************************************************************/ + +static void dmabase_putreg(DMA_CHANNEL dmachan, uint32_t offset, + uint32_t value) +{ + uint32_t dmabase = dmachan_getbase(dmachan); + + putreg32(value, dmabase + offset); +} + +/**************************************************************************** + * Name: dmachan_getreg + * + * Description: + * Get channel register. + * + ****************************************************************************/ + +static uint32_t dmachan_getreg(DMA_CHANNEL dmachan, uint32_t offset) +{ + return getreg32(dmachan->base + offset); +} + +/**************************************************************************** + * Name: dmachan_putreg + * + * Description: + * Write to channel register. + * + ****************************************************************************/ + +static void dmachan_putreg(DMA_CHANNEL dmachan, uint32_t offset, + uint32_t value) +{ + putreg32(value, dmachan->base + offset); +} + +/**************************************************************************** + * Name: dmamux_getreg + * + * Description: + * Write to DMAMUX + * + ****************************************************************************/ + +static void dmamux_putreg(DMA_MUX dmamux, uint32_t offset, uint32_t value) +{ + putreg32(value, dmamux->base + offset); +} + +/**************************************************************************** + * Name: dmamux_getreg + * + * Description: + * Get DMAMUX register. + * + ****************************************************************************/ + +#ifdef CONFIG_DEBUG_DMA_INFO +static uint32_t dmamux_getreg(DMA_MUX dmamux, uint32_t offset) +{ + return getreg32(dmamux->base + offset); +} +#endif + +/**************************************************************************** + * Name: stm32_dma_channel_get + * + * Description: + * Get the g_dmach table entry associated with a given DMA controller + * and channel number. + * + ****************************************************************************/ + +static DMA_CHANNEL stm32_dma_channel_get(uint8_t channel, + uint8_t controller) +{ + uint8_t first = 0; + uint8_t nchan = 0; + + /* Get limits for g_dma array */ + + stm32_gdma_limits_get(controller, &first, &nchan); + + DEBUGASSERT(channel <= nchan); + + return &g_dmach[first + channel]; +} + +/**************************************************************************** + * Name: stm32_gdma_limits_get + * + * Description: + * Get g_dma array limits for a given DMA controller. + * + ****************************************************************************/ + +static void stm32_gdma_limits_get(uint8_t controller, uint8_t *first, + uint8_t *nchan) +{ + DEBUGASSERT(first != NULL); + DEBUGASSERT(nchan != NULL); + + DEBUGASSERT(controller >= DMA1 && controller <= DMA2); + + *first = g_dma[controller].first; + *nchan = g_dma[controller].nchan; +} + +/**************************************************************************** + * DMA controller functions + ****************************************************************************/ + +#if defined(CONFIG_STM32_DMA1) || defined(CONFIG_STM32_DMA2) + +/**************************************************************************** + * Name: stm32_dma12_disable + * + * Description: + * Disable DMA channel (DMA1/DMA2) + * + ****************************************************************************/ + +static void stm32_dma12_disable(DMA_CHANNEL dmachan) +{ + uint32_t regval; + + DEBUGASSERT(dmachan->ctrl == DMA1 || dmachan->ctrl == DMA2); + + /* Disable all interrupts at the DMA controller */ + + regval = dmachan_getreg(dmachan, STM32_DMACHAN_CCR_OFFSET); + regval &= ~DMA_CCR_ALLINTS; + + /* Disable the DMA channel */ + + regval &= ~DMA_CCR_EN; + dmachan_putreg(dmachan, STM32_DMACHAN_CCR_OFFSET, regval); + + /* Clear pending channel interrupts */ + + dmabase_putreg(dmachan, STM32_DMA_IFCR_OFFSET, + DMA_ISR_CHAN_MASK(dmachan->chan)); +} + +/**************************************************************************** + * Name: stm32_dma12_interrupt + * + * Description: + * DMA channel interrupt handler + * + ****************************************************************************/ + +static int stm32_dma12_interrupt(int irq, void *context, void *arg) +{ + DMA_CHANNEL dmachan; + uint32_t isr; + uint8_t channel; + uint8_t controller; + + /* Get the channel and the controller that generated the interrupt */ + + if (0) + { + } +#ifdef CONFIG_STM32_DMA1 + else if (irq >= STM32_IRQ_DMA1CH1 && irq <= STM32_IRQ_DMA1CH7) + { + channel = irq - STM32_IRQ_DMA1CH1; + controller = DMA1; + } +#endif +#ifdef CONFIG_STM32_DMA2 + else if (irq >= STM32_IRQ_DMA2CH1 && irq <= STM32_IRQ_DMA2CH5) + { + channel = irq - STM32_IRQ_DMA2CH1; + controller = DMA2; + } + else if (irq >= STM32_IRQ_DMA2CH6 && irq <= STM32_IRQ_DMA2CH7) + { + channel = irq - STM32_IRQ_DMA2CH6 + (6 - 1); + controller = DMA2; + } +#endif + else + { + DEBUGPANIC(); + return OK; + } + + /* Get the channel structure from the stream and controller numbers */ + + dmachan = stm32_dma_channel_get(channel, controller); + + /* Get the interrupt status (for this channel only) */ + + isr = dmabase_getreg(dmachan, STM32_DMA_ISR_OFFSET) & + DMA_ISR_CHAN_MASK(dmachan->chan); + + /* Invoke the callback */ + + if (dmachan->callback) + { + dmachan->callback(dmachan, isr >> DMA_ISR_CHAN_SHIFT(dmachan->chan), + dmachan->arg); + } + + /* Clear the interrupts we are handling */ + + dmabase_putreg(dmachan, STM32_DMA_IFCR_OFFSET, isr); + + return OK; +} + +/**************************************************************************** + * Name: stm32_dma12_setup + * + * Description: + * Configure DMA before using + * + ****************************************************************************/ + +static void stm32_dma12_setup(DMA_HANDLE handle, uint32_t paddr, + uint32_t maddr, size_t ntransfers, + uint32_t ccr) +{ + DMA_CHANNEL dmachan = (DMA_CHANNEL)handle; + uint32_t regval; + + DEBUGASSERT(handle != NULL); + DEBUGASSERT(ntransfers < 65536); + + DEBUGASSERT(dmachan->ctrl == DMA1 || dmachan->ctrl == DMA2); + + dmainfo("paddr: %08" PRIx32 " maddr: %08" PRIx32 + " ntransfers: %zd ccr: %08" PRIx32 "\n", + paddr, maddr, ntransfers, ccr); + +#ifdef CONFIG_STM32_DMACAPABLE + DEBUGASSERT(g_dma_ops[dmachan->ctrl].dma_capable(maddr, ntransfers, ccr)); +#endif + + /* Then DMA_CNDTRx register can only be modified if the DMA channel is + * disabled. + */ + + regval = dmachan_getreg(dmachan, STM32_DMACHAN_CCR_OFFSET); + regval &= ~(DMA_CCR_EN); + dmachan_putreg(dmachan, STM32_DMACHAN_CCR_OFFSET, regval); + + /* Set the peripheral register address in the DMA_CPARx register. The data + * will be moved from/to this address to/from the memory after the + * peripheral event. + */ + + dmachan_putreg(dmachan, STM32_DMACHAN_CPAR_OFFSET, paddr); + + /* Set the memory address in the DMA_CMARx register. The data will be + * written to or read from this memory after the peripheral event. + */ + + dmachan_putreg(dmachan, STM32_DMACHAN_CMAR_OFFSET, maddr); + + /* Configure the total number of data to be transferred in the DMA_CNDTRx + * register. After each peripheral event, this value will be decremented. + */ + + dmachan_putreg(dmachan, STM32_DMACHAN_CNDTR_OFFSET, ntransfers); + + /* Configure the channel priority using the PL[1:0] bits in the DMA_CCRx + * register. Configure data transfer direction, circular mode, peripheral + * & memory incremented mode, peripheral & memory data size, and interrupt + * after half and/or full transfer in the DMA_CCRx register. + */ + + regval = dmachan_getreg(dmachan, STM32_DMACHAN_CCR_OFFSET); + regval &= ~(DMA_CCR_MEM2MEM | DMA_CCR_PL_MASK | DMA_CCR_MSIZE_MASK | + DMA_CCR_PSIZE_MASK | DMA_CCR_MINC | DMA_CCR_PINC | + DMA_CCR_CIRC | DMA_CCR_DIR); + ccr &= (DMA_CCR_MEM2MEM | DMA_CCR_PL_MASK | DMA_CCR_MSIZE_MASK | + DMA_CCR_PSIZE_MASK | DMA_CCR_MINC | DMA_CCR_PINC | + DMA_CCR_CIRC | DMA_CCR_DIR); + regval |= ccr; + dmachan_putreg(dmachan, STM32_DMACHAN_CCR_OFFSET, regval); +} + +/**************************************************************************** + * Name: stm32_dma12_start + * + * Description: + * Start the standard DMA transfer + ****************************************************************************/ + +static void stm32_dma12_start(DMA_HANDLE handle, dma_callback_t callback, + void *arg, bool half) +{ + DMA_CHANNEL dmachan = (DMA_CHANNEL)handle; + uint32_t ccr; + + DEBUGASSERT(dmachan->ctrl == DMA1 || dmachan->ctrl == DMA2); + + /* Save the callback info. This will be invoked when the DMA completes */ + + dmachan->callback = callback; + dmachan->arg = arg; + + /* Activate the channel by setting the ENABLE bit in the DMA_CCRx register. + * As soon as the channel is enabled, it can serve any DMA request from the + * peripheral connected on the channel. + */ + + ccr = dmachan_getreg(dmachan, STM32_DMACHAN_CCR_OFFSET); + ccr |= DMA_CCR_EN; + + /* In normal mode, interrupt at either half or full completion. In circular + * mode, always interrupt on buffer wrap, and optionally interrupt at the + * halfway point. + */ + + if ((ccr & DMA_CCR_CIRC) == 0) + { + /* Once half of the bytes are transferred, the half-transfer flag + * (HTIF) is set and an interrupt is generated if the Half-Transfer + * Interrupt Enable bit (HTIE) is set. At the end of the transfer, + * the Transfer Complete Flag (TCIF) is set and an interrupt is + * generated if the Transfer Complete Interrupt Enable bit (TCIE) + * is set. + */ + + ccr |= (half ? (DMA_CCR_HTIE | DMA_CCR_TEIE) : + (DMA_CCR_TCIE | DMA_CCR_TEIE)); + } + else + { + /* In nonstop mode, when the transfer completes it immediately resets + * and starts again. The transfer-complete interrupt is thus always + * enabled, and the half-complete interrupt can be used in circular + * mode to determine when the buffer is half-full, or in + * double-buffered mode to determine when one of the two buffers + * is full. + */ + + ccr |= (half ? DMA_CCR_HTIE : 0) | DMA_CCR_TCIE | DMA_CCR_TEIE; + } + + dmachan_putreg(dmachan, STM32_DMACHAN_CCR_OFFSET, ccr); +} + +/**************************************************************************** + * Name: stm32_dma12_residual + ****************************************************************************/ + +static size_t stm32_dma12_residual(DMA_HANDLE handle) +{ + DMA_CHANNEL dmachan = (DMA_CHANNEL)handle; + + DEBUGASSERT(dmachan->ctrl == DMA1 || dmachan->ctrl == DMA2); + + return dmachan_getreg(dmachan, STM32_DMACHAN_CNDTR_OFFSET); +} + +/**************************************************************************** + * Name: stm32_dma12_sample + ****************************************************************************/ + +#ifdef CONFIG_DEBUG_DMA_INFO +void stm32_dma12_sample(DMA_HANDLE handle, struct stm32_dmaregs_s *regs) +{ + DMA_CHANNEL dmachan = (DMA_CHANNEL)handle; + irqstate_t flags; + + flags = enter_critical_section(); + + regs->isr = dmabase_getreg(dmachan, STM32_DMA_ISR_OFFSET); + regs->ccr = dmachan_getreg(dmachan, STM32_DMACHAN_CCR_OFFSET); + regs->cndtr = dmachan_getreg(dmachan, STM32_DMACHAN_CNDTR_OFFSET); + regs->cpar = dmachan_getreg(dmachan, STM32_DMACHAN_CPAR_OFFSET); + regs->cmar = dmachan_getreg(dmachan, STM32_DMACHAN_CMAR_OFFSET); + + stm32_dmamux_sample(g_dma[dmachan->ctrl].dmamux, + dmachan->chan + g_dma[dmachan->ctrl].dmamux_offset, + regs); + + leave_critical_section(flags); +} +#endif + +/**************************************************************************** + * Name: stm32_dma12_dump + ****************************************************************************/ + +#ifdef CONFIG_DEBUG_DMA_INFO +static void stm32_dma12_dump(DMA_HANDLE handle, + const struct stm32_dmaregs_s *regs, + const char *msg) +{ + DMA_CHANNEL dmachan = (DMA_CHANNEL)handle; + + DEBUGASSERT(dmachan->ctrl == DMA1 || dmachan->ctrl == DMA2); + + uint32_t dmabase = dmachan_getbase(dmachan); + + dmainfo("DMA%d Registers: %s\n", + dmachan->ctrl + 1, + msg); + dmainfo(" ISR[%08x]: %08x\n", + dmabase + STM32_DMA_ISR_OFFSET, + regs->isr); + dmainfo(" CCR[%08x]: %08x\n", + dmachan->base + STM32_DMACHAN_CCR_OFFSET, + regs->ccr); + dmainfo(" CNDTR[%08x]: %08x\n", + dmachan->base + STM32_DMACHAN_CNDTR_OFFSET, + regs->cndtr); + dmainfo(" CPAR[%08x]: %08x\n", + dmachan->base + STM32_DMACHAN_CPAR_OFFSET, + regs->cpar); + dmainfo(" CMAR[%08x]: %08x\n", + dmachan->base + STM32_DMACHAN_CMAR_OFFSET, + regs->cmar); + + stm32_dmamux_dump(g_dma[dmachan->ctrl].dmamux, + dmachan->chan + g_dma[dmachan->ctrl].dmamux_offset, + regs); +} +#endif + +#endif /* CONFIG_STM32_DMA1 || CONFIG_STM32_DMA2 */ + +/**************************************************************************** + * Name: stm32_dmamux_sample + ****************************************************************************/ + +#ifdef CONFIG_DEBUG_DMA_INFO +static void stm32_dmamux_sample(DMA_MUX dmamux, uint8_t chan, + struct stm32_dmaregs_s *regs) +{ + regs->dmamux.ccr = dmamux_getreg(dmamux, STM32_DMAMUX_CXCR_OFFSET(chan)); + regs->dmamux.csr = dmamux_getreg(dmamux, STM32_DMAMUX_CSR_OFFSET); + regs->dmamux.rg0cr = dmamux_getreg(dmamux, STM32_DMAMUX_RG0CR_OFFSET); + regs->dmamux.rg1cr = dmamux_getreg(dmamux, STM32_DMAMUX_RG1CR_OFFSET); + regs->dmamux.rg2cr = dmamux_getreg(dmamux, STM32_DMAMUX_RG2CR_OFFSET); + regs->dmamux.rg3cr = dmamux_getreg(dmamux, STM32_DMAMUX_RG3CR_OFFSET); + regs->dmamux.rgsr = dmamux_getreg(dmamux, STM32_DMAMUX_RGSR_OFFSET); +} +#endif + +/**************************************************************************** + * Name: stm32_dmamux_dump + ****************************************************************************/ + +#ifdef CONFIG_DEBUG_DMA_INFO +static void stm32_dmamux_dump(DMA_MUX dmamux, uint8_t channel, + const struct stm32_dmaregs_s *regs) +{ + dmainfo("DMAMUX%d CH=%d\n", dmamux->id, channel); + dmainfo(" CCR[%08" PRIx32 "]: %08" PRIx32 "\n", + dmamux->base + STM32_DMAMUX_CXCR_OFFSET(channel), + regs->dmamux.ccr); + dmainfo(" CSR[%08" PRIx32 "]: %08" PRIx32 "\n", + dmamux->base + STM32_DMAMUX_CSR_OFFSET, regs->dmamux.csr); + dmainfo(" RG0CR[%08" PRIx32 "]: %08" PRIx32 "\n", + dmamux->base + STM32_DMAMUX_RG0CR_OFFSET, regs->dmamux.rg0cr); + dmainfo(" RG1CR[%08" PRIx32 "]: %08" PRIx32 "\n", + dmamux->base + STM32_DMAMUX_RG1CR_OFFSET, regs->dmamux.rg1cr); + dmainfo(" RG2CR[%08" PRIx32 "]: %08" PRIx32 "\n", + dmamux->base + STM32_DMAMUX_RG2CR_OFFSET, regs->dmamux.rg2cr); + dmainfo(" RG3CR[%08" PRIx32 "]: %08" PRIx32 "\n", + dmamux->base + STM32_DMAMUX_RG3CR_OFFSET, regs->dmamux.rg3cr); + dmainfo(" RGSR[%08" PRIx32 "]: %08" PRIx32 "\n", + dmamux->base + STM32_DMAMUX_RGSR_OFFSET, regs->dmamux.rgsr); +}; +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: arm_dma_initialize + * + * Description: + * Initialize the DMA subsystem (DMA1, DMA2) + * + * Returned Value: + * None + * + ****************************************************************************/ + +void weak_function arm_dma_initialize(void) +{ + DMA_CHANNEL dmachan; + uint8_t controller; + int channel; + + dmainfo("Initialize DMA\n"); + + /* Initialize DMA channels */ + + for (channel = 0; channel < DMA_NCHANNELS; channel++) + { + dmachan = &g_dmach[channel]; + + /* Initialize flag */ + + dmachan->used = false; + + /* Get DMA controller associated with channel */ + + controller = dmachan->ctrl; + + DEBUGASSERT(controller >= DMA1 && controller <= DMA2); + + /* Attach standard DMA interrupt vectors */ + + irq_attach(dmachan->irq, g_dma_ops[controller].dma_interrupt, + dmachan); + + /* Disable the DMA channel */ + + g_dma_ops[controller].dma_disable(dmachan); + + /* Enable the IRQ at the NVIC (still disabled at the DMA controller) */ + + up_enable_irq(dmachan->irq); + } +} + +/**************************************************************************** + * Name: stm32_dmachannel + * + * Description: + * Allocate a DMA channel. This function gives the caller mutually + * exclusive access to the DMA channel specified by the 'dmamap' argument. + * It is common for both DMA controllers (DMA1 and DMA2). + * + * Input Parameters: + * dmamap - Identifies the stream/channel resource. For the STM32+, this + * is a bit-encoded value as provided by the DMAMAP_* definitions + * in hardware/stm32g4xxxx_dmamux.h + * + * Returned Value: + * On success, this function returns a non-NULL, void* DMA channel handle. + * NULL is returned on any failure. This function can fail only if no DMA + * channel is available. + * + * Assumptions: + * - The caller does not hold he DMA channel. + * - The caller can wait for the DMA channel to be freed if it is not + * available. + * + ****************************************************************************/ + +DMA_HANDLE stm32_dmachannel(unsigned int dmamap) +{ + DMA_CHANNEL dmachan; + uint8_t dmamux_req; + irqstate_t flags; + uint8_t controller; + uint8_t first = 0; + uint8_t nchan = 0; + int item = -1; + int i; + + /* Get DMA controller from encoded DMAMAP value */ + + controller = DMAMAP_CONTROLLER(dmamap); + DEBUGASSERT(controller >= DMA1 && controller <= DMA2); + + /* Get DMAMUX channel from encoded DMAMAP value */ + + dmamux_req = DMAMAP_REQUEST(dmamap); + + /* Get g_dma array limits for given controller */ + + stm32_gdma_limits_get(controller, &first, &nchan); + + /* Find available channel for given controller */ + + flags = enter_critical_section(); + for (i = first; i < first + nchan; i += 1) + { + if (g_dmach[i].used == false) + { + item = i; + g_dmach[i].used = true; + g_dmach[i].dmamux_req = dmamux_req; + break; + } + } + + leave_critical_section(flags); + + dmainfo("ctrl=%d item=%d\n", controller, item); + + if (item == -1) + { + dmainfo("No available DMA chan for CTRL=%d\n", + controller); + + /* No available channel */ + + return NULL; + } + + /* Assign DMA item */ + + dmachan = &g_dmach[item]; + + dmainfo("Get g_dmach[%d] CTRL=%d CH=%d\n", i, controller, dmachan->chan); + + /* Be sure that we have proper DMA controller */ + + DEBUGASSERT(dmachan->ctrl == controller); + + return (DMA_HANDLE)dmachan; +} + +/**************************************************************************** + * Name: stm32_dmafree + * + * Description: + * Release a DMA channel and unmap DMAMUX if required. + * + * NOTE: The 'handle' used in this argument must NEVER be used again + * until stm32_dmachannel() is called again to re-gain access to the + * channel. + * + * Returned Value: + * None + * + * Assumptions: + * - The caller holds the DMA channel. + * - There is no DMA in progress + * + ****************************************************************************/ + +void stm32_dmafree(DMA_HANDLE handle) +{ + DMA_CHANNEL dmachan = (DMA_CHANNEL)handle; + uint8_t controller; + irqstate_t flags; + + DEBUGASSERT(handle != NULL); + + /* Get DMA controller */ + + controller = dmachan->ctrl; + DEBUGASSERT(controller >= DMA1 && controller <= DMA2); + + dmainfo("Free g_dmach[%d] CTRL=%d CH=%d\n", dmachan - g_dmach, controller, + dmachan->chan); + UNUSED(controller); + + /* Release the channel */ + + flags = enter_critical_section(); + dmachan->used = false; + dmachan->dmamux_req = 0; + leave_critical_section(flags); +} + +/**************************************************************************** + * Name: stm32_dmasetup + * + * Description: + * Configure DMA before using + * + ****************************************************************************/ + +void stm32_dmasetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr, + size_t ntransfers, uint32_t ccr) +{ + DMA_CHANNEL dmachan = (DMA_CHANNEL)handle; + uint8_t controller; + + DEBUGASSERT(handle != NULL); + + /* Get DMA controller */ + + controller = dmachan->ctrl; + DEBUGASSERT(controller >= DMA1 && controller <= DMA2); + + g_dma_ops[controller].dma_setup(handle, paddr, maddr, ntransfers, ccr); +} + +/**************************************************************************** + * Name: stm32_dmastart + * + * Description: + * Start the DMA transfer + * + * Assumptions: + * - DMA handle allocated by stm32_dmachannel() + * - No DMA in progress + * + ****************************************************************************/ + +void stm32_dmastart(DMA_HANDLE handle, dma_callback_t callback, void *arg, + bool half) +{ + DMA_CHANNEL dmachan = (DMA_CHANNEL)handle; + DMA_MUX dmamux; + uint32_t regval; + uint8_t dmamux_chan; + uint8_t controller; + + DEBUGASSERT(handle != NULL); + + /* Get DMA controller */ + + controller = dmachan->ctrl; + DEBUGASSERT(controller >= DMA1 && controller <= DMA2); + + /* Recommended channel configure procedure in reference manual: + * 1. Set and configure the DMA channel y, except enabling the channel y. + * 2. Set and configure the related DMAMUX y channel. + * 3. Last, activate the DMA channel y. + */ + + /* Get DMAMUX associated with DMA controller */ + + dmamux = g_dma[controller].dmamux; + dmamux_chan = dmachan->chan + g_dma[controller].dmamux_offset; + + /* DMAMUX Set DMA channel source */ + + regval = dmachan->dmamux_req << DMAMUX_CCR_DMAREQID_SHIFT; + dmamux_putreg(dmamux, STM32_DMAMUX_CXCR_OFFSET(dmamux_chan), regval); + + /* Enable DMA channel */ + + g_dma_ops[controller].dma_start(handle, callback, arg, half); +} + +/**************************************************************************** + * Name: stm32_dmastop + * + * Description: + * Cancel the DMA. After stm32_dmastop() is called, the DMA channel is + * reset and stm32_dmasetup() must be called before stm32_dmastart() + * can be called again + * + * Assumptions: + * - DMA handle allocated by stm32_dmachannel() + * + ****************************************************************************/ + +void stm32_dmastop(DMA_HANDLE handle) +{ + DMA_CHANNEL dmachan = (DMA_CHANNEL)handle; + DMA_MUX dmamux; + uint8_t dmamux_chan; + uint8_t controller; + + DEBUGASSERT(handle != NULL); + + /* Get DMA controller */ + + controller = dmachan->ctrl; + DEBUGASSERT(controller >= DMA1 && controller <= DMA2); + + /* Get DMAMUX associated with DMA controller */ + + dmamux = g_dma[controller].dmamux; + dmamux_chan = dmachan->chan + g_dma[controller].dmamux_offset; + + /* Disable DMA channel */ + + g_dma_ops[controller].dma_disable(dmachan); + + /* DMAMUX Clear DMA channel source */ + + dmamux_putreg(dmamux, STM32_DMAMUX_CXCR_OFFSET(dmamux_chan), 0); +} + +/**************************************************************************** + * Name: stm32_dmaresidual + * + * Description: + * Read the DMA bytes-remaining register. + * + * Assumptions: + * - DMA handle allocated by stm32_dmachannel() + * + ****************************************************************************/ + +size_t stm32_dmaresidual(DMA_HANDLE handle) +{ + DMA_CHANNEL dmachan = (DMA_CHANNEL)handle; + uint8_t controller; + + DEBUGASSERT(handle != NULL); + + /* Get DMA controller */ + + controller = dmachan->ctrl; + DEBUGASSERT(controller >= DMA1 && controller <= DMA2); + + return g_dma_ops[controller].dma_residual(handle); +} + +/**************************************************************************** + * Name: stm32_dmacapable + * + * Description: + * Check if the DMA controller can transfer data to/from given memory + * address. This depends on the internal connections in the ARM bus matrix + * of the processor. Note that this only applies to memory addresses, it + * will return false for any peripheral address. + * + * Input Parameters: + * cfg - DMA transfer configuration + * + * Returned Value: + * True, if transfer is possible. + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_DMACAPABLE +bool stm32_dmacapable(uint32_t maddr, uint32_t count, uint32_t ccr) +{ + unsigned int msize_shift; + uint32_t transfer_size; + uint32_t mend; + + /* Verify that the address conforms to the memory transfer size. + * Transfers to/from memory performed by the DMA controller are + * required to be aligned to their size. + * + * Datasheet 3.13 claims + * "Access to Flash, SRAM, APB and AHB peripherals as source + * and destination" + */ + + switch (ccr & DMA_CCR_MSIZE_MASK) + { + case DMA_CCR_MSIZE_8BITS: + msize_shift = 0; + break; + + case DMA_CCR_MSIZE_16BITS: + msize_shift = 1; + break; + + case DMA_CCR_MSIZE_32BITS: + msize_shift = 2; + break; + + default: + return false; + } + + transfer_size = 1 << msize_shift; + + if ((maddr & (transfer_size - 1)) != 0) + { + return false; + } + + /* Verify that the transfer is to a memory region that supports DMA. */ + + mend = maddr + (count << msize_shift) - 1; + + if ((maddr & STM32_REGION_MASK) != (mend & STM32_REGION_MASK)) + { + return false; + } + + switch (maddr & STM32_REGION_MASK) + { + case STM32_PERIPH_BASE: + case STM32_SRAM_BASE: + case STM32_CODE_BASE: + + /* All RAM and flash is supported */ + + return true; + + default: + + /* Everything else is unsupported by DMA */ + + return false; + } +} +#endif + +/**************************************************************************** + * Name: stm32_dmasample + * + * Description: + * Sample DMA register contents + * + * Assumptions: + * - DMA handle allocated by stm32_dmachannel() + * + ****************************************************************************/ + +#ifdef CONFIG_DEBUG_DMA_INFO +void stm32_dmasample(DMA_HANDLE handle, struct stm32_dmaregs_s *regs) +{ + DMA_CHANNEL dmachan = (DMA_CHANNEL)handle; + uint8_t controller; + + DEBUGASSERT(handle != NULL); + + /* Get DMA controller */ + + controller = dmachan->ctrl; + DEBUGASSERT(controller >= DMA1 && controller <= DMA2); + + g_dma_ops[controller].dma_sample(handle, regs); +} +#endif + +/**************************************************************************** + * Name: stm32_dmadump + * + * Description: + * Dump previously sampled DMA register contents + * + * Assumptions: + * - DMA handle allocated by stm32_dmachannel() + * + ****************************************************************************/ + +#ifdef CONFIG_DEBUG_DMA_INFO +void stm32_dmadump(DMA_HANDLE handle, const struct stm32_dmaregs_s *regs, + const char *msg) +{ + DMA_CHANNEL dmachan = (DMA_CHANNEL)handle; + uint8_t controller; + + DEBUGASSERT(handle != NULL); + + /* Get DMA controller */ + + controller = dmachan->ctrl; + DEBUGASSERT(controller >= DMA1 && controller <= DMA2); + + dmainfo("DMA %d CH%d Registers: %s\n", dmachan->ctrl, dmachan->ctrl, msg); + + g_dma_ops[controller].dma_dump(handle, regs, msg); +} +#endif diff --git a/arch/arm/src/common/stm32/stm32_dma_m3m4_v1_8ch.c b/arch/arm/src/common/stm32/stm32_dma_m3m4_v1_8ch.c new file mode 100644 index 0000000000000..2d18d541a1a09 --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_dma_m3m4_v1_8ch.c @@ -0,0 +1,899 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_dma_m3m4_v1_8ch.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include + +#include +#include +#include + +#include "arm_internal.h" +#include "sched/sched.h" +#include "chip.h" +#include "stm32_dma.h" +#include "stm32.h" + +/* This file supports the STM32 DMA IP core version 1 - F0, F1, F3, G4, L0, + * L1, L4. + * + * F0, L0 and L4 have the additional CSELR register which is used to remap + * the DMA requests for each channel. + * + * G4 has additional channels in DMA1 and DMA2. + */ + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#if defined(CONFIG_STM32_DMA1_HAVE_CHAN8) +# define DMA1_NCHANNELS 8 +#else +# define DMA1_NCHANNELS 7 +#endif + +#if STM32_NDMA > 1 +# if defined(CONFIG_STM32_DMA2_HAVE_CHAN678) +# define DMA2_NCHANNELS 8 +# else +# define DMA2_NCHANNELS 5 +# endif +# define DMA_NCHANNELS (DMA1_NCHANNELS + DMA2_NCHANNELS) +#else +# define DMA_NCHANNELS DMA1_NCHANNELS +#endif + +/* Convert the DMA channel base address to the DMA register block address */ + +#define DMA_BASE(ch) (ch & 0xfffffc00) + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/* This structure describes one DMA channel */ + +struct stm32_dma_s +{ + uint8_t chan; /* DMA channel number (0-6) */ +#ifdef DMA_HAVE_CSELR + uint8_t function; /* DMA peripheral connected to this channel (0-7) */ +#endif + uint8_t irq; /* DMA channel IRQ number */ + sem_t sem; /* Used to wait for DMA channel to become available */ + uint32_t base; /* DMA register channel base address */ + dma_callback_t callback; /* Callback invoked when the DMA completes */ + void *arg; /* Argument passed to callback function */ +}; + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* This array describes the state of each DMA */ + +static struct stm32_dma_s g_dma[DMA_NCHANNELS] = +{ +#if DMA1_NCHANNELS > 0 + { + .chan = 0, + .irq = STM32_IRQ_DMA1CH1, + .sem = SEM_INITIALIZER(1), + .base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(0), + }, +#endif /* DMA1_NCHANNELS > 0 */ +#if DMA1_NCHANNELS > 1 + { + .chan = 1, + .irq = STM32_IRQ_DMA1CH2, + .sem = SEM_INITIALIZER(1), + .base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(1), + }, +#endif /* DMA1_NCHANNELS > 1 */ +#if DMA1_NCHANNELS > 2 + { + .chan = 2, + .irq = STM32_IRQ_DMA1CH3, + .sem = SEM_INITIALIZER(1), + .base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(2), + }, +#endif /* DMA1_NCHANNELS > 2 */ +#if DMA1_NCHANNELS > 3 + { + .chan = 3, + .irq = STM32_IRQ_DMA1CH4, + .sem = SEM_INITIALIZER(1), + .base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(3), + }, +#endif /* DMA1_NCHANNELS > 3 */ +#if DMA1_NCHANNELS > 4 + { + .chan = 4, + .irq = STM32_IRQ_DMA1CH5, + .sem = SEM_INITIALIZER(1), + .base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(4), + }, +#endif /* DMA1_NCHANNELS > 4 */ +#if DMA1_NCHANNELS > 5 + { + .chan = 5, + .irq = STM32_IRQ_DMA1CH6, + .sem = SEM_INITIALIZER(1), + .base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(5), + }, +#endif /* DMA1_NCHANNELS > 5 */ +#if DMA1_NCHANNELS > 6 + { + .chan = 6, + .irq = STM32_IRQ_DMA1CH7, + .sem = SEM_INITIALIZER(1), + .base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(6), + }, +#endif /* DMA1_NCHANNELS > 6 */ +#if DMA1_NCHANNELS > 7 + { + .chan = 7, + .irq = STM32_IRQ_DMA1CH8, + .sem = SEM_INITIALIZER(1), + .base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(7), + }, +#endif /* DMA1_NCHANNELS > 7 */ +#if STM32_NDMA > 1 +#if DMA2_NCHANNELS > 0 + { + .chan = 0, + .irq = STM32_IRQ_DMA2CH1, + .sem = SEM_INITIALIZER(1), + .base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(0), + }, +#endif /* DMA2_NCHANNELS > 0 */ +#if DMA2_NCHANNELS > 1 + { + .chan = 1, + .irq = STM32_IRQ_DMA2CH2, + .sem = SEM_INITIALIZER(1), + .base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(1), + }, +#endif /* DMA2_NCHANNELS > 1 */ +#if DMA2_NCHANNELS > 2 + { + .chan = 2, + .irq = STM32_IRQ_DMA2CH3, + .sem = SEM_INITIALIZER(1), + .base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(2), + }, +#endif /* DMA2_NCHANNELS > 2 */ +#if DMA2_NCHANNELS > 3 + { + .chan = 3, +#if defined(CONFIG_STM32_CONNECTIVITYLINE) || \ + defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX) || \ + defined(CONFIG_STM32_STM32G4XXX) || defined(CONFIG_STM32_STM32L15XX) + .irq = STM32_IRQ_DMA2CH4, +#else + .irq = STM32_IRQ_DMA2CH45, +#endif + .sem = SEM_INITIALIZER(1), + .base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(3), + }, +#endif /* DMA2_NCHANNELS > 3 */ +#if DMA2_NCHANNELS > 4 + { + .chan = 4, +#if defined(CONFIG_STM32_CONNECTIVITYLINE) || \ + defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX) || \ + defined(CONFIG_STM32_STM32G4XXX) || defined(CONFIG_STM32_STM32L15XX) + .irq = STM32_IRQ_DMA2CH5, +#else + .irq = STM32_IRQ_DMA2CH45, +#endif + .sem = SEM_INITIALIZER(1), + .base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(4), + }, +#endif /* DMA2_NCHANNELS > 4 */ +#if DMA2_NCHANNELS > 5 + { + .chan = 5, + .irq = STM32_IRQ_DMA2CH5, + .sem = SEM_INITIALIZER(1), + .base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(5), + }, +#endif /* DMA2_NCHANNELS > 5 */ +#if DMA2_NCHANNELS > 6 + { + .chan = 6, + .irq = STM32_IRQ_DMA2CH6, + .sem = SEM_INITIALIZER(1), + .base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(6), + }, +#endif /* DMA2_NCHANNELS > 6 */ +#if DMA2_NCHANNELS > 7 + { + .chan = 7, + .irq = STM32_IRQ_DMA2CH7, + .sem = SEM_INITIALIZER(1), + .base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(7), + }, +#endif /* DMA2_NCHANNELS > 7 */ +#endif /* STM32_NDMA > 1 */ +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * DMA register access functions + ****************************************************************************/ + +/* Get non-channel register from DMA1 or DMA2 */ + +static inline uint32_t dmabase_getreg(struct stm32_dma_s *dmach, + uint32_t offset) +{ + return getreg32(DMA_BASE(dmach->base) + offset); +} + +/* Write to non-channel register in DMA1 or DMA2 */ + +static inline void dmabase_putreg(struct stm32_dma_s *dmach, + uint32_t offset, uint32_t value) +{ + putreg32(value, DMA_BASE(dmach->base) + offset); +} + +/* Get channel register from DMA1 or DMA2 */ + +static inline uint32_t dmachan_getreg(struct stm32_dma_s *dmach, + uint32_t offset) +{ + return getreg32(dmach->base + offset); +} + +/* Write to channel register in DMA1 or DMA2 */ + +static inline void dmachan_putreg(struct stm32_dma_s *dmach, + uint32_t offset, uint32_t value) +{ + putreg32(value, dmach->base + offset); +} + +/**************************************************************************** + * Name: stm32_dmachandisable + * + * Description: + * Disable the DMA channel + * + ****************************************************************************/ + +static void stm32_dmachandisable(struct stm32_dma_s *dmach) +{ + uint32_t regval; + + /* Disable all interrupts at the DMA controller */ + + regval = dmachan_getreg(dmach, STM32_DMACHAN_CCR_OFFSET); + regval &= ~DMA_CCR_ALLINTS; + + /* Disable the DMA channel */ + + regval &= ~DMA_CCR_EN; + dmachan_putreg(dmach, STM32_DMACHAN_CCR_OFFSET, regval); + + /* Clear pending channel interrupts */ + + dmabase_putreg(dmach, STM32_DMA_IFCR_OFFSET, + DMA_ISR_CHAN_MASK(dmach->chan)); +} + +/**************************************************************************** + * Name: irq_to_channel_index + * + * Description: + * Given an IRQ number, find the channel index in the g_dma array. + * + * Parameters: + * irq: IRQ number as passed to stm32_dmainterrupt. + * + * Returned Value: + * On success (IRQ matches a DMA channel), returns index in the g_dma + * array from 0 to DMA_NCHANNELS - 1. On failure (IRQ does not match + * a DMA channel), returns -1. + * + ****************************************************************************/ + +static int irq_to_channel_index(int irq) +{ + int chndx; + + /* Find the DMA channel that matches this IRQ */ + + for (chndx = 0; chndx < DMA_NCHANNELS; chndx++) + { + if (irq == g_dma[chndx].irq) + { + return chndx; + } + } + + /* Failed to find the DMA channel for this IRQ */ + + return -1; +} + +/**************************************************************************** + * Name: stm32_dmainterrupt + * + * Description: + * DMA interrupt handler + * + ****************************************************************************/ + +static int stm32_dmainterrupt(int irq, void *context, void *arg) +{ + struct stm32_dma_s *dmach; + uint32_t isr; + int chndx = 0; + + /* Get the channel structure from the interrupt number */ + + chndx = irq_to_channel_index(irq); + if (chndx < 0) + { + DEBUGPANIC(); + } + + dmach = &g_dma[chndx]; + + /* Get the interrupt status (for this channel only) */ + + isr = dmabase_getreg(dmach, STM32_DMA_ISR_OFFSET) & + DMA_ISR_CHAN_MASK(dmach->chan); + + /* Clear the interrupts we are handling */ + + dmabase_putreg(dmach, STM32_DMA_IFCR_OFFSET, isr); + + /* Invoke the callback */ + + if (dmach->callback) + { + dmach->callback(dmach, isr >> DMA_ISR_CHAN_SHIFT(dmach->chan), + dmach->arg); + } + + return OK; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_dmainitialize + * + * Description: + * Initialize the DMA subsystem + * + * Returned Value: + * None + * + ****************************************************************************/ + +void weak_function arm_dma_initialize(void) +{ + struct stm32_dma_s *dmach; + int chndx; + + /* Initialize each DMA channel */ + + for (chndx = 0; chndx < DMA_NCHANNELS; chndx++) + { + dmach = &g_dma[chndx]; + + /* Attach DMA interrupt vectors */ + + irq_attach(dmach->irq, stm32_dmainterrupt, NULL); + + /* Disable the DMA channel */ + + stm32_dmachandisable(dmach); + + /* Enable the IRQ at the NVIC (still disabled at the DMA controller) */ + + up_enable_irq(dmach->irq); + } +} + +/**************************************************************************** + * Name: stm32_dmachannel + * + * Description: + * Allocate a DMA channel. This function gives the caller mutually + * exclusive access to the DMA channel specified by the 'chndx' argument. + * DMA channels are shared on the STM32: Devices sharing the same DMA + * channel cannot do DMA concurrently! See the DMACHAN_* definitions in + * stm32_dma.h. + * + * If the DMA channel is not available, then stm32_dmachannel() will wait + * until the holder of the channel relinquishes the channel by calling + * stm32_dmafree(). WARNING: If you have two devices sharing a DMA + * channel and the code never releases the channel, the stm32_dmachannel + * call for the other will hang forever in this function! Don't let your + * design do that! + * + * Hmm.. I suppose this interface could be extended to make a non-blocking + * version. Feel free to do that if that is what you need. + * + * Input Parameters: + * chndx - Identifies the stream/channel resource. For the STM32 F1, this + * is simply the channel number as provided by the DMACHAN_* definitions + * in chip/stm32f10xxx_dma.h. + * + * Returned Value: + * Provided that 'chndx' is valid, this function ALWAYS returns a non-NULL, + * void* DMA channel handle. (If 'chndx' is invalid, the function will + * assert if debug is enabled or do something ignorant otherwise). + * + * Assumptions: + * - The caller does not hold he DMA channel. + * - The caller can wait for the DMA channel to be freed if it is no + * available. + * + ****************************************************************************/ + +DMA_HANDLE stm32_dmachannel(unsigned int chndef) +{ + int chndx = 0; + struct stm32_dma_s *dmach = NULL; + int ret; + +#ifdef DMA_HAVE_CSELR + chndx = (chndef & DMACHAN_SETTING_CHANNEL_MASK) >> + DMACHAN_SETTING_CHANNEL_SHIFT; +#else + chndx = chndef; +#endif + + dmach = &g_dma[chndx]; + + DEBUGASSERT(chndx < DMA_NCHANNELS); + + /* Get exclusive access to the DMA channel -- OR wait until the channel + * is available if it is currently being used by another driver + */ + + ret = nxsem_wait_uninterruptible(&dmach->sem); + if (ret < 0) + { + return NULL; + } + + /* The caller now has exclusive use of the DMA channel */ + +#ifdef DMA_HAVE_CSELR + /* Define the peripheral that will use the channel. This is stored until + * dmasetup is called. + */ + + dmach->function = (chndef & DMACHAN_SETTING_FUNCTION_MASK) >> + DMACHAN_SETTING_FUNCTION_SHIFT; +#endif + + return (DMA_HANDLE)dmach; +} + +/**************************************************************************** + * Name: stm32_dmafree + * + * Description: + * Release a DMA channel. If another thread is waiting for this DMA channel + * in a call to stm32_dmachannel, then this function will re-assign the + * DMA channel to that thread and wake it up. NOTE: The 'handle' used + * in this argument must NEVER be used again until stm32_dmachannel() is + * called again to re-gain access to the channel. + * + * Returned Value: + * None + * + * Assumptions: + * - The caller holds the DMA channel. + * - There is no DMA in progress + * + ****************************************************************************/ + +void stm32_dmafree(DMA_HANDLE handle) +{ + struct stm32_dma_s *dmach = (struct stm32_dma_s *)handle; + + DEBUGASSERT(handle != NULL); + + /* Release the channel */ + + nxsem_post(&dmach->sem); +} + +/**************************************************************************** + * Name: stm32_dmasetup + * + * Description: + * Configure DMA before using + * + ****************************************************************************/ + +void stm32_dmasetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr, + size_t ntransfers, uint32_t ccr) +{ + struct stm32_dma_s *dmach = (struct stm32_dma_s *)handle; + uint32_t regval; + + /* Then DMA_CNDTRx register can only be modified if the DMA channel is + * disabled. + */ + + regval = dmachan_getreg(dmach, STM32_DMACHAN_CCR_OFFSET); + regval &= ~(DMA_CCR_EN); + dmachan_putreg(dmach, STM32_DMACHAN_CCR_OFFSET, regval); + + /* Set the peripheral register address in the DMA_CPARx register. The data + * will be moved from/to this address to/from the memory after the + * peripheral event. + */ + + dmachan_putreg(dmach, STM32_DMACHAN_CPAR_OFFSET, paddr); + + /* Set the memory address in the DMA_CMARx register. The data will be + * written to or read from this memory after the peripheral event. + */ + + dmachan_putreg(dmach, STM32_DMACHAN_CMAR_OFFSET, maddr); + + /* Configure the total number of data to be transferred in the DMA_CNDTRx + * register. After each peripheral event, this value will be decremented. + */ + + dmachan_putreg(dmach, STM32_DMACHAN_CNDTR_OFFSET, ntransfers); + + /* Configure the channel priority using the PL[1:0] bits in the DMA_CCRx + * register. Configure data transfer direction, circular mode, + * peripheral & memory incremented mode, peripheral & memory data size, + * and interrupt after half and/or full transfer in the DMA_CCRx register. + */ + + regval = dmachan_getreg(dmach, STM32_DMACHAN_CCR_OFFSET); + regval &= ~(DMA_CCR_MEM2MEM | DMA_CCR_PL_MASK | DMA_CCR_MSIZE_MASK | + DMA_CCR_PSIZE_MASK | DMA_CCR_MINC | DMA_CCR_PINC | + DMA_CCR_CIRC | DMA_CCR_DIR); + ccr &= (DMA_CCR_MEM2MEM | DMA_CCR_PL_MASK | DMA_CCR_MSIZE_MASK | + DMA_CCR_PSIZE_MASK | DMA_CCR_MINC | DMA_CCR_PINC | + DMA_CCR_CIRC | DMA_CCR_DIR); + regval |= ccr; + dmachan_putreg(dmach, STM32_DMACHAN_CCR_OFFSET, regval); + +#ifdef DMA_HAVE_CSELR + /* Define peripheral indicated in dmach->function */ + + regval = dmabase_getreg(dmach, STM32_DMA_CSELR_OFFSET); + regval &= ~(0x0f << (dmach->chan << 2)); + regval |= (dmach->function << (dmach->chan << 2)); + dmabase_putreg(dmach, STM32_DMA_CSELR_OFFSET, regval); +#endif +} + +/**************************************************************************** + * Name: stm32_dmastart + * + * Description: + * Start the DMA transfer + * + * Assumptions: + * - DMA handle allocated by stm32_dmachannel() + * - No DMA in progress + * + ****************************************************************************/ + +void stm32_dmastart(DMA_HANDLE handle, dma_callback_t callback, + void *arg, bool half) +{ + struct stm32_dma_s *dmach = (struct stm32_dma_s *)handle; + uint32_t ccr; + + DEBUGASSERT(handle != NULL); + + /* Save the callback info. This will be invoked when the DMA completes. */ + + dmach->callback = callback; + dmach->arg = arg; + + /* Activate the channel by setting the ENABLE bit in the DMA_CCRx register. + * As soon as the channel is enabled, it can serve any DMA request from the + * peripheral connected on the channel. + */ + + ccr = dmachan_getreg(dmach, STM32_DMACHAN_CCR_OFFSET); + ccr |= DMA_CCR_EN; + + /* In normal mode, interrupt at either half or full completion. In circular + * mode, always interrupt on buffer wrap, and optionally interrupt at the + * halfway point. + */ + + if ((ccr & DMA_CCR_CIRC) == 0) + { + /* Once half of the bytes are transferred, the half-transfer flag + * (HTIF) is set and an interrupt is generated if the Half-Transfer + * Interrupt Enable bit (HTIE) is set. At the end of the transfer, the + * Transfer Complete Flag (TCIF) is set and an interrupt is generated + * if the Transfer Complete Interrupt Enable bit (TCIE) is set. + */ + + ccr |= (half ? + (DMA_CCR_HTIE | DMA_CCR_TEIE) : (DMA_CCR_TCIE | DMA_CCR_TEIE)); + } + else + { + /* In nonstop mode, when the transfer completes it immediately resets + * and starts again. The transfer-complete interrupt is thus always + * enabled, and the half-complete interrupt can be used in circular + * mode to determine when the buffer is half-full or in double-buffered + * mode to determine when one of the two buffers is full. + */ + + ccr |= (half ? DMA_CCR_HTIE : 0) | DMA_CCR_TCIE | DMA_CCR_TEIE; + } + + dmachan_putreg(dmach, STM32_DMACHAN_CCR_OFFSET, ccr); +} + +/**************************************************************************** + * Name: stm32_dmastop + * + * Description: + * Cancel the DMA. After stm32_dmastop() is called, the DMA channel is + * reset and stm32_dmasetup() must be called before stm32_dmastart() can be + * called again + * + * Assumptions: + * - DMA handle allocated by stm32_dmachannel() + * + ****************************************************************************/ + +void stm32_dmastop(DMA_HANDLE handle) +{ + struct stm32_dma_s *dmach = (struct stm32_dma_s *)handle; + stm32_dmachandisable(dmach); +} + +/**************************************************************************** + * Name: stm32_dmaresidual + * + * Description: + * Returns the number of bytes remaining to be transferred + * + * Assumptions: + * - DMA handle allocated by stm32_dmachannel() + * + ****************************************************************************/ + +size_t stm32_dmaresidual(DMA_HANDLE handle) +{ + struct stm32_dma_s *dmach = (struct stm32_dma_s *)handle; + + return dmachan_getreg(dmach, STM32_DMACHAN_CNDTR_OFFSET); +} + +/**************************************************************************** + * Name: stm32_dmacapable + * + * Description: + * Check if the DMA controller can transfer data to/from given memory + * address. This depends on the internal connections in the ARM bus matrix + * of the processor. Note that this only applies to memory addresses, it + * will return false for any peripheral address. + * + * Returned Value: + * True, if transfer is possible. + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_DMACAPABLE +bool stm32_dmacapable(uintptr_t maddr, uint32_t count, uint32_t ccr) +{ + uint32_t transfer_size; + uint32_t mend; + + /* Verify that the address conforms to the memory transfer size. + * Transfers to/from memory performed by the DMA controller are + * required to be aligned to their size. + * + * See ST RM0090 rev4, section 9.3.11 + * + * Compute mend inline to avoid a possible non-constant integer + * multiply. + */ + + switch (ccr & DMA_CCR_MSIZE_MASK) + { + case DMA_CCR_MSIZE_8BITS: + transfer_size = 1; + mend = maddr + count - 1; + break; + + case DMA_CCR_MSIZE_16BITS: + transfer_size = 2; + mend = maddr + (count << 1) - 1; + break; + + case DMA_CCR_MSIZE_32BITS: + transfer_size = 4; + mend = maddr + (count << 2) - 1; + break; + + default: + return false; + } + + if ((maddr & (transfer_size - 1)) != 0) + { + return false; + } + + /* Verify that the transfer is to a memory region that supports DMA. */ + + if ((maddr & STM32_REGION_MASK) != (mend & STM32_REGION_MASK)) + { + return false; + } + + switch (maddr & STM32_REGION_MASK) + { +#if defined(CONFIG_STM32_STM32F10XX) + case STM32_FSMC_BANK1: + case STM32_FSMC_BANK2: + case STM32_FSMC_BANK3: + case STM32_FSMC_BANK4: +#endif + case STM32_SRAM_BASE: + case STM32_CODE_BASE: + + /* All RAM and flash is supported */ + + return true; + + default: + + /* Everything else is unsupported by DMA */ + + return false; + } +} +#endif + +/**************************************************************************** + * Name: stm32_dmasample + * + * Description: + * Sample DMA register contents + * + * Assumptions: + * - DMA handle allocated by stm32_dmachannel() + * + ****************************************************************************/ + +#ifdef CONFIG_DEBUG_DMA_INFO +void stm32_dmasample(DMA_HANDLE handle, struct stm32_dmaregs_s *regs) +{ + struct stm32_dma_s *dmach = (struct stm32_dma_s *)handle; + irqstate_t flags; + + flags = enter_critical_section(); + regs->isr = dmabase_getreg(dmach, STM32_DMA_ISR_OFFSET); +#ifdef DMA_HAVE_CSELR + regs->cselr = dmabase_getreg(dmach, STM32_DMA_CSELR_OFFSET); +#endif + regs->ccr = dmachan_getreg(dmach, STM32_DMACHAN_CCR_OFFSET); + regs->cndtr = dmachan_getreg(dmach, STM32_DMACHAN_CNDTR_OFFSET); + regs->cpar = dmachan_getreg(dmach, STM32_DMACHAN_CPAR_OFFSET); + regs->cmar = dmachan_getreg(dmach, STM32_DMACHAN_CMAR_OFFSET); + leave_critical_section(flags); +} +#endif + +/**************************************************************************** + * Name: stm32_dmadump + * + * Description: + * Dump previously sampled DMA register contents + * + * Assumptions: + * - DMA handle allocated by stm32_dmachannel() + * + ****************************************************************************/ + +#ifdef CONFIG_DEBUG_DMA_INFO +void stm32_dmadump(DMA_HANDLE handle, const struct stm32_dmaregs_s *regs, + const char *msg) +{ + struct stm32_dma_s *dmach = (struct stm32_dma_s *)handle; + uint32_t dmabase = DMA_BASE(dmach->base); + + dmainfo("DMA Registers: %s\n", msg); + dmainfo(" ISRC[%08" PRIx32 "]: %08" PRIx32 "\n", + dmabase + STM32_DMA_ISR_OFFSET, regs->isr); +#ifdef DMA_HAVE_CSELR + dmainfo(" CSELR[%08" PRIx32 "]: %08" PRIx32 "\n", + dmabase + STM32_DMA_CSELR_OFFSET, regs->cselr); +#endif + dmainfo(" CCR[%08" PRIx32 "]: %08" PRIx32 "\n", + dmach->base + STM32_DMACHAN_CCR_OFFSET, regs->ccr); + dmainfo(" CNDTR[%08" PRIx32 "]: %08" PRIx32 "\n", + dmach->base + STM32_DMACHAN_CNDTR_OFFSET, regs->cndtr); + dmainfo(" CPAR[%08" PRIx32 "]: %08" PRIx32 "\n", + dmach->base + STM32_DMACHAN_CPAR_OFFSET, regs->cpar); + dmainfo(" CMAR[%08" PRIx32 "]: %08" PRIx32 "\n", + dmach->base + STM32_DMACHAN_CMAR_OFFSET, regs->cmar); +} +#endif + +#ifdef CONFIG_ARCH_HIPRI_INTERRUPT + +/**************************************************************************** + * Name: stm32_dma_intack + * + * Description: + * Public visible interface to acknowledge interrupts on DMA channel + * + ****************************************************************************/ + +void stm32_dma_intack(unsigned int chndx, uint32_t isr) +{ + struct stm32_dma_s *dmach = &g_dma[chndx]; + + dmabase_putreg(dmach, STM32_DMA_IFCR_OFFSET, isr); +} + +/**************************************************************************** + * Name: stm32_dma_intget + * + * Description: + * Public visible interface to get pending interrupts from DMA channel + * + ****************************************************************************/ + +uint32_t stm32_dma_intget(unsigned int chndx) +{ + struct stm32_dma_s *dmach = &g_dma[chndx]; + + return dmabase_getreg(dmach, STM32_DMA_ISR_OFFSET) & + DMA_ISR_CHAN_MASK(dmach->chan); +} +#endif /* CONFIG_ARCH_HIPRI_INTERRUPT */ diff --git a/arch/arm/src/common/stm32/stm32_dma_m3m4_v1_8ch_dmamux.c b/arch/arm/src/common/stm32/stm32_dma_m3m4_v1_8ch_dmamux.c new file mode 100644 index 0000000000000..dd8892f0f6502 --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_dma_m3m4_v1_8ch_dmamux.c @@ -0,0 +1,1457 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_dma_m3m4_v1_8ch_dmamux.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include "arm_internal.h" +#include "sched/sched.h" +#include "stm32_dma.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifndef CONFIG_STM32_DMAMUX +# error "Configuration error, CONFIG_STM32_DMAMUX not defined!" +#endif + +#ifndef CONFIG_STM32_DMAMUX1 +# error "Configuration error, CONFIG_STM32_DMAMUX1 not defined!" +#endif + +#define DMAMUX_NUM 1 +#define DMA_CONTROLLERS 2 + +#ifdef CONFIG_STM32_DMA1 +# if defined(CONFIG_STM32_STM32G4_CAT2) +# define DMA1_NCHAN 7 +# elif defined(CONFIG_STM32_STM32G4_CAT3) || defined(CONFIG_STM32_STM32G4_CAT4) +# define DMA1_NCHAN 8 +# else +# error +# endif +#else +# define DMA1_NCHAN 0 +#endif +#ifdef CONFIG_STM32_DMA2 +# if defined(CONFIG_STM32_STM32G4_CAT2) +# define DMA2_NCHAN 6 +# elif defined(CONFIG_STM32_STM32G4_CAT3) || defined(CONFIG_STM32_STM32G4_CAT4) +# define DMA2_NCHAN 8 +# else +# error +# endif +#else +# define DMA2_NCHAN 0 +#endif + +#define DMA1_FIRST (0) +#define DMA1_LAST (DMA1_FIRST+DMA1_NCHAN) +#define DMA2_FIRST (DMA1_LAST) +#define DMA2_LAST (DMA2_FIRST+DMA2_NCHAN) + +/* All available DMA channels */ + +#define DMA_NCHANNELS (DMA1_NCHAN + DMA2_NCHAN) + +/* DMAMUX channels */ + +#if defined(CONFIG_STM32_STM32G4_CAT2) +# define DMAMUX_NCHANNELS 12 +#elif defined(CONFIG_STM32_STM32G4_CAT3) || defined(CONFIG_STM32_STM32G4_CAT4) +# define DMAMUX_NCHANNELS 16 +#else +# error +#endif + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/* This structure described one DMAMUX device */ + +struct stm32_dmamux_s +{ + uint8_t id; /* DMAMUX id */ + uint8_t nchan; /* DMAMUX channels */ + uint32_t base; /* DMAMUX base address */ +}; + +typedef const struct stm32_dmamux_s *DMA_MUX; + +/* This structure describes one DMA controller */ + +struct stm32_dma_s +{ + uint8_t first; /* Offset in stm32_dmach_s array */ + uint8_t nchan; /* Number of channels */ + uint8_t dmamux_offset; /* DMAMUX channel offset */ + uint32_t base; /* Base address */ + DMA_MUX dmamux; /* DMAMUX associated with controller */ +}; + +/* This structure describes one DMA channel (DMA1, DMA2) */ + +struct stm32_dmach_s +{ + bool used; /* Channel in use */ + uint8_t dmamux_req; /* Configured DMAMUX input request */ + uint8_t ctrl; /* DMA controller */ + uint8_t chan; /* DMA channel channel id */ + uint8_t irq; /* DMA channel IRQ number */ + uint8_t shift; /* IFCR bit shift value */ + uint32_t base; /* DMA register channel base address */ + dma_callback_t callback; /* Callback invoked when the DMA completes */ + void *arg; /* Argument passed to callback function */ +}; + +typedef struct stm32_dmach_s *DMA_CHANNEL; + +/* DMA operations */ + +struct stm32_dma_ops_s +{ + /* Disable the DMA transfer */ + + void (*dma_disable)(DMA_CHANNEL dmachan); + + /* DMA interrupt */ + + int (*dma_interrupt)(int irq, void *context, void *arg); + + /* Setup the DMA */ + + void (*dma_setup)(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr, + size_t ntransfers, uint32_t ccr); + + /* Start the DMA */ + + void (*dma_start)(DMA_HANDLE handle, dma_callback_t callback, + void *arg, bool half); + + /* Read remaining DMA bytes */ + + size_t (*dma_residual)(DMA_HANDLE handle); + + /* Check the DMA configuration */ + + bool (*dma_capable)(uint32_t maddr, uint32_t count, uint32_t ccr); + +#ifdef CONFIG_DEBUG_DMA_INFO + /* Sample the DMA registers */ + + void (*dma_sample)(DMA_HANDLE handle, struct stm32_dmaregs_s *regs); + + /* Dump the DMA registers */ + + void (*dma_dump)(DMA_HANDLE handle, + const struct stm32_dmaregs_s *regs, + const char *msg); +#endif +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +#if defined(CONFIG_STM32_DMA1) || defined(CONFIG_STM32_DMA2) +static void stm32_dma12_disable(DMA_CHANNEL dmachan); +static int stm32_dma12_interrupt(int irq, void *context, void *arg); +static void stm32_dma12_setup(DMA_HANDLE handle, uint32_t paddr, + uint32_t maddr, size_t ntransfers, + uint32_t ccr); +static void stm32_dma12_start(DMA_HANDLE handle, dma_callback_t callback, + void *arg, bool half); +static size_t stm32_dma12_residual(DMA_HANDLE handle); +#ifdef CONFIG_DEBUG_DMA_INFO +static void stm32_dma12_sample(DMA_HANDLE handle, + struct stm32_dmaregs_s *regs); +static void stm32_dma12_dump(DMA_HANDLE handle, + const struct stm32_dmaregs_s *regs, + const char *msg); +#endif +#endif + +static uint32_t dmachan_getbase(DMA_CHANNEL dmachan); +static uint32_t dmabase_getreg(DMA_CHANNEL dmachan, uint32_t offset); +static void dmabase_putreg(DMA_CHANNEL dmachan, uint32_t offset, + uint32_t value); +static uint32_t dmachan_getreg(DMA_CHANNEL dmachan, uint32_t offset); +static void dmachan_putreg(DMA_CHANNEL dmachan, uint32_t offset, + uint32_t value); +static void dmamux_putreg(DMA_MUX dmamux, uint32_t offset, uint32_t value); +#ifdef CONFIG_DEBUG_DMA_INFO +static uint32_t dmamux_getreg(DMA_MUX dmamux, uint32_t offset); +static void stm32_dmamux_sample(DMA_MUX dmamux, uint8_t chan, + struct stm32_dmaregs_s *regs); +static void stm32_dmamux_dump(DMA_MUX dmamux, uint8_t channel, + const struct stm32_dmaregs_s *regs); +#endif +static DMA_CHANNEL stm32_dma_channel_get(uint8_t channel, + uint8_t controller); +static void stm32_gdma_limits_get(uint8_t controller, uint8_t *first, + uint8_t *last); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* Operations specific to DMA controller */ + +static const struct stm32_dma_ops_s g_dma_ops[DMA_CONTROLLERS] = +{ +#ifdef CONFIG_STM32_DMA1 + /* 0 - DMA1 */ + + { + .dma_disable = stm32_dma12_disable, + .dma_interrupt = stm32_dma12_interrupt, + .dma_setup = stm32_dma12_setup, + .dma_start = stm32_dma12_start, + .dma_residual = stm32_dma12_residual, +#ifdef CONFIG_DEBUG_DMA_INFO + .dma_sample = stm32_dma12_sample, + .dma_dump = stm32_dma12_dump, +#endif + }, +#else + { + NULL + }, +#endif + +#ifdef CONFIG_STM32_DMA2 + /* 1 - DMA2 */ + + { + .dma_disable = stm32_dma12_disable, + .dma_interrupt = stm32_dma12_interrupt, + .dma_setup = stm32_dma12_setup, + .dma_start = stm32_dma12_start, + .dma_residual = stm32_dma12_residual, +#ifdef CONFIG_DEBUG_DMA_INFO + .dma_sample = stm32_dma12_sample, + .dma_dump = stm32_dma12_dump, +#endif + } +#else + { + NULL + } +#endif +}; + +/* This array describes the state of DMAMUX controller */ + +static const struct stm32_dmamux_s g_dmamux[DMAMUX_NUM] = +{ + { + .id = 1, + .nchan = DMAMUX_NCHANNELS, + .base = STM32_DMAMUX1_BASE + } +}; + +/* This array describes the state of each controller */ + +static const struct stm32_dma_s g_dma[DMA_NCHANNELS] = +{ + /* 0 - DMA1 */ + + { + .base = STM32_DMA1_BASE, + .first = DMA1_FIRST, + .nchan = DMA1_NCHAN, + .dmamux = &g_dmamux[DMAMUX1], /* DMAMUX1 channels 0-6 */ + .dmamux_offset = 0 + }, + + /* 1 - DMA2 */ + + { + .base = STM32_DMA2_BASE, + .first = DMA2_FIRST, + .nchan = DMA2_NCHAN, + .dmamux = &g_dmamux[DMAMUX1], /* DMAMUX1 channels 7-13 */ + .dmamux_offset = 7 + } +}; + +/* This array describes the state of each DMA channel. */ + +static struct stm32_dmach_s g_dmach[DMA_NCHANNELS] = +{ +#ifdef CONFIG_STM32_DMA1 + /* DMA1 */ + + { + .ctrl = DMA1, + .chan = 0, + .irq = STM32_IRQ_DMA1CH1, + .shift = DMA_CHAN_SHIFT(0), + .base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(0), + }, + + { + .ctrl = DMA1, + .chan = 1, + .irq = STM32_IRQ_DMA1CH2, + .shift = DMA_CHAN_SHIFT(1), + .base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(1), + }, + + { + .ctrl = DMA1, + .chan = 2, + .irq = STM32_IRQ_DMA1CH3, + .shift = DMA_CHAN_SHIFT(2), + .base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(2), + }, + + { + .ctrl = DMA1, + .chan = 3, + .irq = STM32_IRQ_DMA1CH4, + .shift = DMA_CHAN_SHIFT(3), + .base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(3), + }, + + { + .ctrl = DMA1, + .chan = 4, + .irq = STM32_IRQ_DMA1CH5, + .shift = DMA_CHAN_SHIFT(4), + .base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(4), + }, + + { + .ctrl = DMA1, + .chan = 5, + .irq = STM32_IRQ_DMA1CH6, + .shift = DMA_CHAN_SHIFT(5), + .base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(5), + }, + + { + .ctrl = DMA1, + .chan = 6, + .irq = STM32_IRQ_DMA1CH7, + .shift = DMA_CHAN_SHIFT(6), + .base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(6), + }, + +# if DMA1_NCHAN > 7 + { + .ctrl = DMA1, + .chan = 7, + .irq = STM32_IRQ_DMA1CH8, + .shift = DMA_CHAN_SHIFT(7), + .base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(7), + }, +# endif +#endif + +#ifdef CONFIG_STM32_DMA2 + /* DMA2 */ + + { + .ctrl = DMA2, + .chan = 0, + .irq = STM32_IRQ_DMA2CH1, + .shift = DMA_CHAN_SHIFT(0), + .base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(0), + }, + + { + .ctrl = DMA2, + .chan = 1, + .irq = STM32_IRQ_DMA2CH2, + .shift = DMA_CHAN_SHIFT(1), + .base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(1), + }, + + { + .ctrl = DMA2, + .chan = 2, + .irq = STM32_IRQ_DMA2CH3, + .shift = DMA_CHAN_SHIFT(2), + .base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(2), + }, + + { + .ctrl = DMA2, + .chan = 3, + .irq = STM32_IRQ_DMA2CH4, + .shift = DMA_CHAN_SHIFT(3), + .base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(3), + }, + + { + .ctrl = DMA2, + .chan = 4, + .irq = STM32_IRQ_DMA2CH5, + .shift = DMA_CHAN_SHIFT(4), + .base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(4), + }, + + { + .ctrl = DMA2, + .chan = 5, + .irq = STM32_IRQ_DMA2CH6, + .shift = DMA_CHAN_SHIFT(5), + .base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(5), + }, + +# if DMA2_NCHAN > 6 + { + .ctrl = DMA2, + .chan = 6, + .irq = STM32_IRQ_DMA2CH7, + .shift = DMA_CHAN_SHIFT(6), + .base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(6), + }, +# endif + +# if DMA2_NCHAN > 7 + { + .ctrl = DMA2, + .chan = 7, + .irq = STM32_IRQ_DMA2CH8, + .shift = DMA_CHAN_SHIFT(7), + .base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(7), + }, +# endif +#endif +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * DMA register access functions + ****************************************************************************/ + +/**************************************************************************** + * Name: dmachan_getbase + * + * Description: + * Get base DMA address for dmachan + * + ****************************************************************************/ + +static uint32_t dmachan_getbase(DMA_CHANNEL dmachan) +{ + uint8_t controller = dmachan->ctrl; + + return g_dma[controller].base; +} + +/**************************************************************************** + * Name: dmabase_getreg + * + * Description: + * Get non-channel register from DMA controller + * + ****************************************************************************/ + +static uint32_t dmabase_getreg(DMA_CHANNEL dmachan, uint32_t offset) +{ + uint32_t dmabase = dmachan_getbase(dmachan); + + return getreg32(dmabase + offset); +} + +/**************************************************************************** + * Name: dmabase_putreg + * + * Description: + * Write to non-channel register in DMA controller + * + ****************************************************************************/ + +static void dmabase_putreg(DMA_CHANNEL dmachan, uint32_t offset, + uint32_t value) +{ + uint32_t dmabase = dmachan_getbase(dmachan); + + putreg32(value, dmabase + offset); +} + +/**************************************************************************** + * Name: dmachan_getreg + * + * Description: + * Get channel register. + * + ****************************************************************************/ + +static uint32_t dmachan_getreg(DMA_CHANNEL dmachan, uint32_t offset) +{ + return getreg32(dmachan->base + offset); +} + +/**************************************************************************** + * Name: dmachan_putreg + * + * Description: + * Write to channel register. + * + ****************************************************************************/ + +static void dmachan_putreg(DMA_CHANNEL dmachan, uint32_t offset, + uint32_t value) +{ + putreg32(value, dmachan->base + offset); +} + +/**************************************************************************** + * Name: dmamux_getreg + * + * Description: + * Write to DMAMUX + * + ****************************************************************************/ + +static void dmamux_putreg(DMA_MUX dmamux, uint32_t offset, uint32_t value) +{ + putreg32(value, dmamux->base + offset); +} + +/**************************************************************************** + * Name: dmamux_getreg + * + * Description: + * Get DMAMUX register. + * + ****************************************************************************/ + +#ifdef CONFIG_DEBUG_DMA_INFO +static uint32_t dmamux_getreg(DMA_MUX dmamux, uint32_t offset) +{ + return getreg32(dmamux->base + offset); +} +#endif + +/**************************************************************************** + * Name: stm32_dma_channel_get + * + * Description: + * Get the g_dmach table entry associated with a given DMA controller + * and channel number. + * + ****************************************************************************/ + +static DMA_CHANNEL stm32_dma_channel_get(uint8_t channel, + uint8_t controller) +{ + uint8_t first = 0; + uint8_t nchan = 0; + + /* Get limits for g_dma array */ + + stm32_gdma_limits_get(controller, &first, &nchan); + + DEBUGASSERT(channel <= nchan); + + return &g_dmach[first + channel]; +} + +/**************************************************************************** + * Name: stm32_gdma_limits_get + * + * Description: + * Get g_dma array limits for a given DMA controller. + * + ****************************************************************************/ + +static void stm32_gdma_limits_get(uint8_t controller, uint8_t *first, + uint8_t *nchan) +{ + DEBUGASSERT(first != NULL); + DEBUGASSERT(nchan != NULL); + + DEBUGASSERT(controller >= DMA1 && controller <= DMA2); + + *first = g_dma[controller].first; + *nchan = g_dma[controller].nchan; +} + +/**************************************************************************** + * DMA controller functions + ****************************************************************************/ + +#if defined(CONFIG_STM32_DMA1) || defined(CONFIG_STM32_DMA2) + +/**************************************************************************** + * Name: stm32_dma12_disable + * + * Description: + * Disable DMA channel (DMA1/DMA2) + * + ****************************************************************************/ + +static void stm32_dma12_disable(DMA_CHANNEL dmachan) +{ + uint32_t regval; + + DEBUGASSERT(dmachan->ctrl == DMA1 || dmachan->ctrl == DMA2); + + /* Disable all interrupts at the DMA controller */ + + regval = dmachan_getreg(dmachan, STM32_DMACHAN_CCR_OFFSET); + regval &= ~DMA_CCR_ALLINTS; + + /* Disable the DMA channel */ + + regval &= ~DMA_CCR_EN; + dmachan_putreg(dmachan, STM32_DMACHAN_CCR_OFFSET, regval); + + /* Clear pending channel interrupts */ + + dmabase_putreg(dmachan, STM32_DMA_IFCR_OFFSET, + DMA_ISR_CHAN_MASK(dmachan->chan)); +} + +/**************************************************************************** + * Name: stm32_dma12_interrupt + * + * Description: + * DMA channel interrupt handler + * + ****************************************************************************/ + +static int stm32_dma12_interrupt(int irq, void *context, void *arg) +{ + DMA_CHANNEL dmachan; + uint32_t isr; + uint8_t channel; + uint8_t controller; + + /* Get the channel and the controller that generated the interrupt */ + + if (0) + { + } +#ifdef CONFIG_STM32_DMA1 + else if (irq >= STM32_IRQ_DMA1CH1 && irq <= STM32_IRQ_DMA1CH7) + { + channel = irq - STM32_IRQ_DMA1CH1; + controller = DMA1; + } +#endif +#ifdef CONFIG_STM32_DMA2 + else if (irq >= STM32_IRQ_DMA2CH1 && irq <= STM32_IRQ_DMA2CH5) + { + channel = irq - STM32_IRQ_DMA2CH1; + controller = DMA2; + } + else if (irq >= STM32_IRQ_DMA2CH6 && irq <= STM32_IRQ_DMA2CH7) + { + channel = irq - STM32_IRQ_DMA2CH6 + (6 - 1); + controller = DMA2; + } +#endif + else + { + DEBUGPANIC(); + return OK; + } + + /* Get the channel structure from the stream and controller numbers */ + + dmachan = stm32_dma_channel_get(channel, controller); + + /* Get the interrupt status (for this channel only) */ + + isr = dmabase_getreg(dmachan, STM32_DMA_ISR_OFFSET) & + DMA_ISR_CHAN_MASK(dmachan->chan); + + /* Invoke the callback */ + + if (dmachan->callback) + { + dmachan->callback(dmachan, isr >> DMA_ISR_CHAN_SHIFT(dmachan->chan), + dmachan->arg); + } + + /* Clear the interrupts we are handling */ + + dmabase_putreg(dmachan, STM32_DMA_IFCR_OFFSET, isr); + + return OK; +} + +/**************************************************************************** + * Name: stm32_dma12_setup + * + * Description: + * Configure DMA before using + * + ****************************************************************************/ + +static void stm32_dma12_setup(DMA_HANDLE handle, uint32_t paddr, + uint32_t maddr, size_t ntransfers, + uint32_t ccr) +{ + DMA_CHANNEL dmachan = (DMA_CHANNEL)handle; + uint32_t regval; + + DEBUGASSERT(handle != NULL); + DEBUGASSERT(ntransfers < 65536); + + DEBUGASSERT(dmachan->ctrl == DMA1 || dmachan->ctrl == DMA2); + + dmainfo("paddr: %08" PRIx32 " maddr: %08" PRIx32 + " ntransfers: %zd ccr: %08" PRIx32 "\n", + paddr, maddr, ntransfers, ccr); + +#ifdef CONFIG_STM32_DMACAPABLE + DEBUGASSERT(g_dma_ops[dmachan->ctrl].dma_capable(maddr, ntransfers, ccr)); +#endif + + /* Then DMA_CNDTRx register can only be modified if the DMA channel is + * disabled. + */ + + regval = dmachan_getreg(dmachan, STM32_DMACHAN_CCR_OFFSET); + regval &= ~(DMA_CCR_EN); + dmachan_putreg(dmachan, STM32_DMACHAN_CCR_OFFSET, regval); + + /* Set the peripheral register address in the DMA_CPARx register. The data + * will be moved from/to this address to/from the memory after the + * peripheral event. + */ + + dmachan_putreg(dmachan, STM32_DMACHAN_CPAR_OFFSET, paddr); + + /* Set the memory address in the DMA_CMARx register. The data will be + * written to or read from this memory after the peripheral event. + */ + + dmachan_putreg(dmachan, STM32_DMACHAN_CMAR_OFFSET, maddr); + + /* Configure the total number of data to be transferred in the DMA_CNDTRx + * register. After each peripheral event, this value will be decremented. + */ + + dmachan_putreg(dmachan, STM32_DMACHAN_CNDTR_OFFSET, ntransfers); + + /* Configure the channel priority using the PL[1:0] bits in the DMA_CCRx + * register. Configure data transfer direction, circular mode, peripheral + * & memory incremented mode, peripheral & memory data size, and interrupt + * after half and/or full transfer in the DMA_CCRx register. + */ + + regval = dmachan_getreg(dmachan, STM32_DMACHAN_CCR_OFFSET); + regval &= ~(DMA_CCR_MEM2MEM | DMA_CCR_PL_MASK | DMA_CCR_MSIZE_MASK | + DMA_CCR_PSIZE_MASK | DMA_CCR_MINC | DMA_CCR_PINC | + DMA_CCR_CIRC | DMA_CCR_DIR); + ccr &= (DMA_CCR_MEM2MEM | DMA_CCR_PL_MASK | DMA_CCR_MSIZE_MASK | + DMA_CCR_PSIZE_MASK | DMA_CCR_MINC | DMA_CCR_PINC | + DMA_CCR_CIRC | DMA_CCR_DIR); + regval |= ccr; + dmachan_putreg(dmachan, STM32_DMACHAN_CCR_OFFSET, regval); +} + +/**************************************************************************** + * Name: stm32_dma12_start + * + * Description: + * Start the standard DMA transfer + ****************************************************************************/ + +static void stm32_dma12_start(DMA_HANDLE handle, dma_callback_t callback, + void *arg, bool half) +{ + DMA_CHANNEL dmachan = (DMA_CHANNEL)handle; + uint32_t ccr; + + DEBUGASSERT(dmachan->ctrl == DMA1 || dmachan->ctrl == DMA2); + + /* Save the callback info. This will be invoked when the DMA completes */ + + dmachan->callback = callback; + dmachan->arg = arg; + + /* Activate the channel by setting the ENABLE bit in the DMA_CCRx register. + * As soon as the channel is enabled, it can serve any DMA request from the + * peripheral connected on the channel. + */ + + ccr = dmachan_getreg(dmachan, STM32_DMACHAN_CCR_OFFSET); + ccr |= DMA_CCR_EN; + + /* In normal mode, interrupt at either half or full completion. In circular + * mode, always interrupt on buffer wrap, and optionally interrupt at the + * halfway point. + */ + + if ((ccr & DMA_CCR_CIRC) == 0) + { + /* Once half of the bytes are transferred, the half-transfer flag + * (HTIF) is set and an interrupt is generated if the Half-Transfer + * Interrupt Enable bit (HTIE) is set. At the end of the transfer, + * the Transfer Complete Flag (TCIF) is set and an interrupt is + * generated if the Transfer Complete Interrupt Enable bit (TCIE) + * is set. + */ + + ccr |= (half ? (DMA_CCR_HTIE | DMA_CCR_TEIE) : + (DMA_CCR_TCIE | DMA_CCR_TEIE)); + } + else + { + /* In nonstop mode, when the transfer completes it immediately resets + * and starts again. The transfer-complete interrupt is thus always + * enabled, and the half-complete interrupt can be used in circular + * mode to determine when the buffer is half-full, or in + * double-buffered mode to determine when one of the two buffers + * is full. + */ + + ccr |= (half ? DMA_CCR_HTIE : 0) | DMA_CCR_TCIE | DMA_CCR_TEIE; + } + + dmachan_putreg(dmachan, STM32_DMACHAN_CCR_OFFSET, ccr); +} + +/**************************************************************************** + * Name: stm32_dma12_residual + ****************************************************************************/ + +static size_t stm32_dma12_residual(DMA_HANDLE handle) +{ + DMA_CHANNEL dmachan = (DMA_CHANNEL)handle; + + DEBUGASSERT(dmachan->ctrl == DMA1 || dmachan->ctrl == DMA2); + + return dmachan_getreg(dmachan, STM32_DMACHAN_CNDTR_OFFSET); +} + +/**************************************************************************** + * Name: stm32_dma12_sample + ****************************************************************************/ + +#ifdef CONFIG_DEBUG_DMA_INFO +void stm32_dma12_sample(DMA_HANDLE handle, struct stm32_dmaregs_s *regs) +{ + DMA_CHANNEL dmachan = (DMA_CHANNEL)handle; + irqstate_t flags; + + flags = enter_critical_section(); + + regs->isr = dmabase_getreg(dmachan, STM32_DMA_ISR_OFFSET); + regs->ccr = dmachan_getreg(dmachan, STM32_DMACHAN_CCR_OFFSET); + regs->cndtr = dmachan_getreg(dmachan, STM32_DMACHAN_CNDTR_OFFSET); + regs->cpar = dmachan_getreg(dmachan, STM32_DMACHAN_CPAR_OFFSET); + regs->cmar = dmachan_getreg(dmachan, STM32_DMACHAN_CMAR_OFFSET); + + stm32_dmamux_sample(g_dma[dmachan->ctrl].dmamux, + dmachan->chan + g_dma[dmachan->ctrl].dmamux_offset, + regs); + + leave_critical_section(flags); +} +#endif + +/**************************************************************************** + * Name: stm32_dma12_dump + ****************************************************************************/ + +#ifdef CONFIG_DEBUG_DMA_INFO +static void stm32_dma12_dump(DMA_HANDLE handle, + const struct stm32_dmaregs_s *regs, + const char *msg) +{ + DMA_CHANNEL dmachan = (DMA_CHANNEL)handle; + + DEBUGASSERT(dmachan->ctrl == DMA1 || dmachan->ctrl == DMA2); + + uint32_t dmabase = dmachan_getbase(dmachan); + + dmainfo("DMA%d Registers: %s\n", + dmachan->ctrl + 1, + msg); + dmainfo(" ISR[%08" PRIx32 "]: %08" PRIx32 "\n", + dmabase + STM32_DMA_ISR_OFFSET, + regs->isr); + dmainfo(" CCR[%08" PRIx32 "]: %08" PRIx32 "\n", + dmachan->base + STM32_DMACHAN_CCR_OFFSET, + regs->ccr); + dmainfo(" CNDTR[%08" PRIx32 "]: %08" PRIx32 "\n", + dmachan->base + STM32_DMACHAN_CNDTR_OFFSET, + regs->cndtr); + dmainfo(" CPAR[%08" PRIx32 "]: %08" PRIx32 "\n", + dmachan->base + STM32_DMACHAN_CPAR_OFFSET, + regs->cpar); + dmainfo(" CMAR[%08" PRIx32 "]: %08" PRIx32 "\n", + dmachan->base + STM32_DMACHAN_CMAR_OFFSET, + regs->cmar); + + stm32_dmamux_dump(g_dma[dmachan->ctrl].dmamux, + dmachan->chan + g_dma[dmachan->ctrl].dmamux_offset, + regs); +} +#endif + +#endif /* CONFIG_STM32_DMA1 || CONFIG_STM32_DMA2 */ + +/**************************************************************************** + * Name: stm32_dmamux_sample + ****************************************************************************/ + +#ifdef CONFIG_DEBUG_DMA_INFO +static void stm32_dmamux_sample(DMA_MUX dmamux, uint8_t chan, + struct stm32_dmaregs_s *regs) +{ + regs->dmamux.ccr = dmamux_getreg(dmamux, STM32_DMAMUX_CXCR_OFFSET(chan)); + regs->dmamux.csr = dmamux_getreg(dmamux, STM32_DMAMUX_CSR_OFFSET); + regs->dmamux.rg0cr = dmamux_getreg(dmamux, STM32_DMAMUX_RG0CR_OFFSET); + regs->dmamux.rg1cr = dmamux_getreg(dmamux, STM32_DMAMUX_RG1CR_OFFSET); + regs->dmamux.rg2cr = dmamux_getreg(dmamux, STM32_DMAMUX_RG2CR_OFFSET); + regs->dmamux.rg3cr = dmamux_getreg(dmamux, STM32_DMAMUX_RG3CR_OFFSET); + regs->dmamux.rgsr = dmamux_getreg(dmamux, STM32_DMAMUX_RGSR_OFFSET); +} +#endif + +/**************************************************************************** + * Name: stm32_dmamux_dump + ****************************************************************************/ + +#ifdef CONFIG_DEBUG_DMA_INFO +static void stm32_dmamux_dump(DMA_MUX dmamux, uint8_t channel, + const struct stm32_dmaregs_s *regs) +{ + dmainfo("DMAMUX%d CH=%d\n", dmamux->id, channel); + dmainfo(" CCR[%08" PRIx32 "]: %08" PRIx32 "\n", + dmamux->base + STM32_DMAMUX_CXCR_OFFSET(channel), + regs->dmamux.ccr); + dmainfo(" CSR[%08" PRIx32 "]: %08" PRIx32 "\n", + dmamux->base + STM32_DMAMUX_CSR_OFFSET, regs->dmamux.csr); + dmainfo(" RG0CR[%08" PRIx32 "]: %08" PRIx32 "\n", + dmamux->base + STM32_DMAMUX_RG0CR_OFFSET, regs->dmamux.rg0cr); + dmainfo(" RG1CR[%08" PRIx32 "]: %08" PRIx32 "\n", + dmamux->base + STM32_DMAMUX_RG1CR_OFFSET, regs->dmamux.rg1cr); + dmainfo(" RG2CR[%08" PRIx32 "]: %08" PRIx32 "\n", + dmamux->base + STM32_DMAMUX_RG2CR_OFFSET, regs->dmamux.rg2cr); + dmainfo(" RG3CR[%08" PRIx32 "]: %08" PRIx32 "\n", + dmamux->base + STM32_DMAMUX_RG3CR_OFFSET, regs->dmamux.rg3cr); + dmainfo(" RGSR[%08" PRIx32 "]: %08" PRIx32 "\n", + dmamux->base + STM32_DMAMUX_RGSR_OFFSET, regs->dmamux.rgsr); +}; +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: arm_dma_initialize + * + * Description: + * Initialize the DMA subsystem (DMA1, DMA2) + * + * Returned Value: + * None + * + ****************************************************************************/ + +void weak_function arm_dma_initialize(void) +{ + DMA_CHANNEL dmachan; + uint8_t controller; + int channel; + + dmainfo("Initialize DMA\n"); + + /* Initialize DMA channels */ + + for (channel = 0; channel < DMA_NCHANNELS; channel++) + { + dmachan = &g_dmach[channel]; + + /* Initialize flag */ + + dmachan->used = false; + + /* Get DMA controller associated with channel */ + + controller = dmachan->ctrl; + + DEBUGASSERT(controller >= DMA1 && controller <= DMA2); + + /* Attach standard DMA interrupt vectors */ + + irq_attach(dmachan->irq, g_dma_ops[controller].dma_interrupt, + dmachan); + + /* Disable the DMA channel */ + + g_dma_ops[controller].dma_disable(dmachan); + + /* Enable the IRQ at the NVIC (still disabled at the DMA controller) */ + + up_enable_irq(dmachan->irq); + } +} + +/**************************************************************************** + * Name: stm32_dmachannel + * + * Description: + * Allocate a DMA channel. This function gives the caller mutually + * exclusive access to the DMA channel specified by the 'dmamap' argument. + * It is common for both DMA controllers (DMA1 and DMA2). + * + * Input Parameters: + * dmamap - Identifies the stream/channel resource. For the STM32+, this + * is a bit-encoded value as provided by the DMAMAP_* definitions + * in hardware/stm32g4xxxx_dmamux.h + * + * Returned Value: + * On success, this function returns a non-NULL, void* DMA channel handle. + * NULL is returned on any failure. This function can fail only if no DMA + * channel is available. + * + * Assumptions: + * - The caller does not hold he DMA channel. + * - The caller can wait for the DMA channel to be freed if it is not + * available. + * + ****************************************************************************/ + +DMA_HANDLE stm32_dmachannel(unsigned int dmamap) +{ + DMA_CHANNEL dmachan; + uint8_t dmamux_req; + irqstate_t flags; + uint8_t controller; + uint8_t first = 0; + uint8_t nchan = 0; + int item = -1; + int i; + + /* Get DMA controller from encoded DMAMAP value */ + + controller = DMAMAP_CONTROLLER(dmamap); + DEBUGASSERT(controller >= DMA1 && controller <= DMA2); + + /* Get DMAMUX channel from encoded DMAMAP value */ + + dmamux_req = DMAMAP_REQUEST(dmamap); + + /* Get g_dma array limits for given controller */ + + stm32_gdma_limits_get(controller, &first, &nchan); + + /* Find available channel for given controller */ + + flags = enter_critical_section(); + for (i = first; i < first + nchan; i += 1) + { + if (g_dmach[i].used == false) + { + item = i; + g_dmach[i].used = true; + g_dmach[i].dmamux_req = dmamux_req; + break; + } + } + + leave_critical_section(flags); + + dmainfo("ctrl=%d item=%d\n", controller, item); + + if (item == -1) + { + dmainfo("No available DMA chan for CTRL=%d\n", + controller); + + /* No available channel */ + + return NULL; + } + + /* Assign DMA item */ + + dmachan = &g_dmach[item]; + + dmainfo("Get g_dmach[%d] CTRL=%d CH=%d\n", i, controller, dmachan->chan); + + /* Be sure that we have proper DMA controller */ + + DEBUGASSERT(dmachan->ctrl == controller); + + return (DMA_HANDLE)dmachan; +} + +/**************************************************************************** + * Name: stm32_dmafree + * + * Description: + * Release a DMA channel and unmap DMAMUX if required. + * + * NOTE: The 'handle' used in this argument must NEVER be used again + * until stm32_dmachannel() is called again to re-gain access to the + * channel. + * + * Returned Value: + * None + * + * Assumptions: + * - The caller holds the DMA channel. + * - There is no DMA in progress + * + ****************************************************************************/ + +void stm32_dmafree(DMA_HANDLE handle) +{ + DMA_CHANNEL dmachan = (DMA_CHANNEL)handle; + uint8_t controller; + irqstate_t flags; + + DEBUGASSERT(handle != NULL); + + /* Get DMA controller */ + + controller = dmachan->ctrl; + DEBUGASSERT(controller >= DMA1 && controller <= DMA2); + + dmainfo("Free g_dmach[%d] CTRL=%d CH=%d\n", dmachan - g_dmach, controller, + dmachan->chan); + UNUSED(controller); + + /* Release the channel */ + + flags = enter_critical_section(); + dmachan->used = false; + dmachan->dmamux_req = 0; + leave_critical_section(flags); +} + +/**************************************************************************** + * Name: stm32_dmasetup + * + * Description: + * Configure DMA before using + * + ****************************************************************************/ + +void stm32_dmasetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr, + size_t ntransfers, uint32_t ccr) +{ + DMA_CHANNEL dmachan = (DMA_CHANNEL)handle; + uint8_t controller; + + DEBUGASSERT(handle != NULL); + + /* Get DMA controller */ + + controller = dmachan->ctrl; + DEBUGASSERT(controller >= DMA1 && controller <= DMA2); + + g_dma_ops[controller].dma_setup(handle, paddr, maddr, ntransfers, ccr); +} + +/**************************************************************************** + * Name: stm32_dmastart + * + * Description: + * Start the DMA transfer + * + * Assumptions: + * - DMA handle allocated by stm32_dmachannel() + * - No DMA in progress + * + ****************************************************************************/ + +void stm32_dmastart(DMA_HANDLE handle, dma_callback_t callback, void *arg, + bool half) +{ + DMA_CHANNEL dmachan = (DMA_CHANNEL)handle; + DMA_MUX dmamux; + uint32_t regval; + uint8_t dmamux_chan; + uint8_t controller; + + DEBUGASSERT(handle != NULL); + + /* Get DMA controller */ + + controller = dmachan->ctrl; + DEBUGASSERT(controller >= DMA1 && controller <= DMA2); + + /* Recommended channel configure procedure in reference manual: + * 1. Set and configure the DMA channel y, except enabling the channel y. + * 2. Set and configure the related DMAMUX y channel. + * 3. Last, activate the DMA channel y. + */ + + /* Get DMAMUX associated with DMA controller */ + + dmamux = g_dma[controller].dmamux; + dmamux_chan = dmachan->chan + g_dma[controller].dmamux_offset; + + /* DMAMUX Set DMA channel source */ + + regval = dmachan->dmamux_req << DMAMUX_CCR_DMAREQID_SHIFT; + dmamux_putreg(dmamux, STM32_DMAMUX_CXCR_OFFSET(dmamux_chan), regval); + + /* Enable DMA channel */ + + g_dma_ops[controller].dma_start(handle, callback, arg, half); +} + +/**************************************************************************** + * Name: stm32_dmastop + * + * Description: + * Cancel the DMA. After stm32_dmastop() is called, the DMA channel is + * reset and stm32_dmasetup() must be called before stm32_dmastart() + * can be called again + * + * Assumptions: + * - DMA handle allocated by stm32_dmachannel() + * + ****************************************************************************/ + +void stm32_dmastop(DMA_HANDLE handle) +{ + DMA_CHANNEL dmachan = (DMA_CHANNEL)handle; + DMA_MUX dmamux; + uint8_t dmamux_chan; + uint8_t controller; + + DEBUGASSERT(handle != NULL); + + /* Get DMA controller */ + + controller = dmachan->ctrl; + DEBUGASSERT(controller >= DMA1 && controller <= DMA2); + + /* Get DMAMUX associated with DMA controller */ + + dmamux = g_dma[controller].dmamux; + dmamux_chan = dmachan->chan + g_dma[controller].dmamux_offset; + + /* Disable DMA channel */ + + g_dma_ops[controller].dma_disable(dmachan); + + /* DMAMUX Clear DMA channel source */ + + dmamux_putreg(dmamux, STM32_DMAMUX_CXCR_OFFSET(dmamux_chan), 0); +} + +/**************************************************************************** + * Name: stm32_dmaresidual + * + * Description: + * Read the DMA bytes-remaining register. + * + * Assumptions: + * - DMA handle allocated by stm32_dmachannel() + * + ****************************************************************************/ + +size_t stm32_dmaresidual(DMA_HANDLE handle) +{ + DMA_CHANNEL dmachan = (DMA_CHANNEL)handle; + uint8_t controller; + + DEBUGASSERT(handle != NULL); + + /* Get DMA controller */ + + controller = dmachan->ctrl; + DEBUGASSERT(controller >= DMA1 && controller <= DMA2); + + return g_dma_ops[controller].dma_residual(handle); +} + +/**************************************************************************** + * Name: stm32_dmacapable + * + * Description: + * Check if the DMA controller can transfer data to/from given memory + * address. This depends on the internal connections in the ARM bus matrix + * of the processor. Note that this only applies to memory addresses, it + * will return false for any peripheral address. + * + * Input Parameters: + * cfg - DMA transfer configuration + * + * Returned Value: + * True, if transfer is possible. + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_DMACAPABLE +bool stm32_dmacapable(uint32_t maddr, uint32_t count, uint32_t ccr) +{ + unsigned int msize_shift; + uint32_t transfer_size; + uint32_t mend; + + /* Verify that the address conforms to the memory transfer size. + * Transfers to/from memory performed by the DMA controller are + * required to be aligned to their size. + * + * Datasheet 3.13 claims + * "Access to Flash, SRAM, APB and AHB peripherals as source + * and destination" + */ + + switch (ccr & DMA_CCR_MSIZE_MASK) + { + case DMA_CCR_MSIZE_8BITS: + msize_shift = 0; + break; + + case DMA_CCR_MSIZE_16BITS: + msize_shift = 1; + break; + + case DMA_CCR_MSIZE_32BITS: + msize_shift = 2; + break; + + default: + return false; + } + + transfer_size = 1 << msize_shift; + + if ((maddr & (transfer_size - 1)) != 0) + { + return false; + } + + /* Verify that the transfer is to a memory region that supports DMA. */ + + mend = maddr + (count << msize_shift) - 1; + + if ((maddr & STM32_REGION_MASK) != (mend & STM32_REGION_MASK)) + { + return false; + } + + switch (maddr & STM32_REGION_MASK) + { + case STM32_PERIPH_BASE: + case STM32_FSMC_BASE: + case STM32_FSMC_BANK1: + case STM32_FSMC_BANK2: + case STM32_FSMC_BANK3: + case STM32_QSPI_BANK: + case STM32_SRAM_BASE: + case STM32_SRAM2_BASE: + case STM32_SRAM3_BASE: + case STM32_CODE_BASE: + + /* All RAM and flash is supported */ + + return true; + + default: + + /* Everything else is unsupported by DMA */ + + return false; + } +} +#endif + +/**************************************************************************** + * Name: stm32_dmasample + * + * Description: + * Sample DMA register contents + * + * Assumptions: + * - DMA handle allocated by stm32_dmachannel() + * + ****************************************************************************/ + +#ifdef CONFIG_DEBUG_DMA_INFO +void stm32_dmasample(DMA_HANDLE handle, struct stm32_dmaregs_s *regs) +{ + DMA_CHANNEL dmachan = (DMA_CHANNEL)handle; + uint8_t controller; + + DEBUGASSERT(handle != NULL); + + /* Get DMA controller */ + + controller = dmachan->ctrl; + DEBUGASSERT(controller >= DMA1 && controller <= DMA2); + + g_dma_ops[controller].dma_sample(handle, regs); +} +#endif + +/**************************************************************************** + * Name: stm32_dmadump + * + * Description: + * Dump previously sampled DMA register contents + * + * Assumptions: + * - DMA handle allocated by stm32_dmachannel() + * + ****************************************************************************/ + +#ifdef CONFIG_DEBUG_DMA_INFO +void stm32_dmadump(DMA_HANDLE handle, const struct stm32_dmaregs_s *regs, + const char *msg) +{ + DMA_CHANNEL dmachan = (DMA_CHANNEL)handle; + uint8_t controller; + + DEBUGASSERT(handle != NULL); + + /* Get DMA controller */ + + controller = dmachan->ctrl; + DEBUGASSERT(controller >= DMA1 && controller <= DMA2); + + dmainfo("DMA %d CH%d Registers: %s\n", dmachan->ctrl, dmachan->ctrl, msg); + + g_dma_ops[controller].dma_dump(handle, regs, msg); +} +#endif diff --git a/arch/arm/src/common/stm32/stm32_dma_m3m4_v2_stream.c b/arch/arm/src/common/stm32/stm32_dma_m3m4_v2_stream.c new file mode 100644 index 0000000000000..0fadcf45a61b9 --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_dma_m3m4_v2_stream.c @@ -0,0 +1,1166 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_dma_m3m4_v2_stream.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include "arm_internal.h" +#include "sched/sched.h" +#include "chip.h" +#include "stm32_dma.h" +#include "stm32.h" + +/* This file supports the STM32 DMA IP core version 2 - F2, F4, F7, H7 + * NOTE: F7 and H7 need support for DCACHE which is not implemented here + * but otherwise DMA IP cores look the same. + */ + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define DMA1_NSTREAMS 8 +#if STM32_NDMA > 1 +# define DMA2_NSTREAMS 8 +# define DMA_NSTREAMS (DMA1_NSTREAMS+DMA2_NSTREAMS) +#else +# define DMA_NSTREAMS DMA1_NSTREAMS +#endif + +/* Convert the DMA stream base address to the DMA register block address */ + +#define DMA_BASE(ch) (ch & 0xfffffc00) + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/* This structure describes one DMA channel */ + +struct stm32_dma_s +{ + uint8_t stream; /* DMA stream number (0-7) */ + uint8_t irq; /* DMA stream IRQ number */ + uint8_t shift; /* ISR/IFCR bit shift value */ + uint8_t channel; /* DMA channel number (0-7) */ + sem_t sem; /* Used to wait for DMA channel to become available */ + uint32_t base; /* DMA register channel base address */ + dma_callback_t callback; /* Callback invoked when the DMA completes */ + void *arg; /* Argument passed to callback function */ +}; + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* This array describes the state of each DMA */ + +static struct stm32_dma_s g_dma[DMA_NSTREAMS] = +{ + { + .stream = 0, + .irq = STM32_IRQ_DMA1S0, + .shift = DMA_INT_STREAM0_SHIFT, + .sem = SEM_INITIALIZER(1), + .base = STM32_DMA1_BASE + STM32_DMA_OFFSET(0), + }, + { + .stream = 1, + .irq = STM32_IRQ_DMA1S1, + .shift = DMA_INT_STREAM1_SHIFT, + .sem = SEM_INITIALIZER(1), + .base = STM32_DMA1_BASE + STM32_DMA_OFFSET(1), + }, + { + .stream = 2, + .irq = STM32_IRQ_DMA1S2, + .shift = DMA_INT_STREAM2_SHIFT, + .sem = SEM_INITIALIZER(1), + .base = STM32_DMA1_BASE + STM32_DMA_OFFSET(2), + }, + { + .stream = 3, + .irq = STM32_IRQ_DMA1S3, + .shift = DMA_INT_STREAM3_SHIFT, + .sem = SEM_INITIALIZER(1), + .base = STM32_DMA1_BASE + STM32_DMA_OFFSET(3), + }, + { + .stream = 4, + .irq = STM32_IRQ_DMA1S4, + .shift = DMA_INT_STREAM4_SHIFT, + .sem = SEM_INITIALIZER(1), + .base = STM32_DMA1_BASE + STM32_DMA_OFFSET(4), + }, + { + .stream = 5, + .irq = STM32_IRQ_DMA1S5, + .shift = DMA_INT_STREAM5_SHIFT, + .sem = SEM_INITIALIZER(1), + .base = STM32_DMA1_BASE + STM32_DMA_OFFSET(5), + }, + { + .stream = 6, + .irq = STM32_IRQ_DMA1S6, + .shift = DMA_INT_STREAM6_SHIFT, + .sem = SEM_INITIALIZER(1), + .base = STM32_DMA1_BASE + STM32_DMA_OFFSET(6), + }, + { + .stream = 7, + .irq = STM32_IRQ_DMA1S7, + .shift = DMA_INT_STREAM7_SHIFT, + .sem = SEM_INITIALIZER(1), + .base = STM32_DMA1_BASE + STM32_DMA_OFFSET(7), + }, +#if STM32_NDMA > 1 + { + .stream = 0, + .irq = STM32_IRQ_DMA2S0, + .shift = DMA_INT_STREAM0_SHIFT, + .sem = SEM_INITIALIZER(1), + .base = STM32_DMA2_BASE + STM32_DMA_OFFSET(0), + }, + { + .stream = 1, + .irq = STM32_IRQ_DMA2S1, + .shift = DMA_INT_STREAM1_SHIFT, + .sem = SEM_INITIALIZER(1), + .base = STM32_DMA2_BASE + STM32_DMA_OFFSET(1), + }, + { + .stream = 2, + .irq = STM32_IRQ_DMA2S2, + .shift = DMA_INT_STREAM2_SHIFT, + .sem = SEM_INITIALIZER(1), + .base = STM32_DMA2_BASE + STM32_DMA_OFFSET(2), + }, + { + .stream = 3, + .irq = STM32_IRQ_DMA2S3, + .shift = DMA_INT_STREAM3_SHIFT, + .sem = SEM_INITIALIZER(1), + .base = STM32_DMA2_BASE + STM32_DMA_OFFSET(3), + }, + { + .stream = 4, + .irq = STM32_IRQ_DMA2S4, + .sem = SEM_INITIALIZER(1), + .base = STM32_DMA2_BASE + STM32_DMA_OFFSET(4), + }, + { + .stream = 5, + .irq = STM32_IRQ_DMA2S5, + .shift = DMA_INT_STREAM5_SHIFT, + .sem = SEM_INITIALIZER(1), + .base = STM32_DMA2_BASE + STM32_DMA_OFFSET(5), + }, + { + .stream = 6, + .irq = STM32_IRQ_DMA2S6, + .shift = DMA_INT_STREAM6_SHIFT, + .sem = SEM_INITIALIZER(1), + .base = STM32_DMA2_BASE + STM32_DMA_OFFSET(6), + }, + { + .stream = 7, + .irq = STM32_IRQ_DMA2S7, + .shift = DMA_INT_STREAM7_SHIFT, + .sem = SEM_INITIALIZER(1), + .base = STM32_DMA2_BASE + STM32_DMA_OFFSET(7), + }, +#endif +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * DMA register access functions + ****************************************************************************/ + +/* Get non-channel register from DMA1 or DMA2 */ + +static inline uint32_t dmabase_getreg(struct stm32_dma_s *dmast, + uint32_t offset) +{ + return getreg32(DMA_BASE(dmast->base) + offset); +} + +/* Write to non-channel register in DMA1 or DMA2 */ + +static inline void dmabase_putreg(struct stm32_dma_s *dmast, uint32_t offset, + uint32_t value) +{ + putreg32(value, DMA_BASE(dmast->base) + offset); +} + +/* Get channel register from DMA1 or DMA2 */ + +static inline uint32_t dmast_getreg(struct stm32_dma_s *dmast, + uint32_t offset) +{ + return getreg32(dmast->base + offset); +} + +/* Write to channel register in DMA1 or DMA2 */ + +static inline void dmast_putreg(struct stm32_dma_s *dmast, uint32_t offset, + uint32_t value) +{ + putreg32(value, dmast->base + offset); +} + +static inline void dmast_modifyreg32(struct stm32_dma_s *dmast, + uint32_t offset, uint32_t clrbits, + uint32_t setbits) +{ + modifyreg32(dmast->base + offset, clrbits, setbits); +} + +/**************************************************************************** + * Name: stm32_dmastream + * + * Description: + * Get the g_dma table entry associated with a DMA controller and a stream + * number + * + ****************************************************************************/ + +static inline struct stm32_dma_s *stm32_dmastream(unsigned int stream, + unsigned int controller) +{ + int index; + + DEBUGASSERT(stream < DMA_NSTREAMS && controller < STM32_NDMA); + + /* Convert the controller + stream based on the fact that there are + * 8 streams per controller. + */ + +#if STM32_NDMA > 1 + index = controller << 3 | stream; +#else + index = stream; +#endif + + /* Then return the stream structure associated with the stream index */ + + return &g_dma[index]; +} + +/**************************************************************************** + * Name: stm32_dmamap + * + * Description: + * Get the g_dma table entry associated with a bit-encoded DMA selection + * + ****************************************************************************/ + +static inline struct stm32_dma_s *stm32_dmamap(unsigned long dmamap) +{ + /* Extract the DMA controller number from the bit encoded value */ + + unsigned int controller = STM32_DMA_CONTROLLER(dmamap); + + /* Extract the stream number from the bit encoded value */ + + unsigned int stream = STM32_DMA_STREAM(dmamap); + + /* Return the table entry associated with the controller + stream */ + + return stm32_dmastream(stream, controller); +} + +/**************************************************************************** + * Name: stm32_dmastreamdisable + * + * Description: + * Disable the DMA stream + * + ****************************************************************************/ + +static void stm32_dmastreamdisable(struct stm32_dma_s *dmast) +{ + uint32_t regoffset; + uint32_t regval; + + /* Disable all interrupts at the DMA controller */ + + regval = dmast_getreg(dmast, STM32_DMA_SCR_OFFSET); + regval &= ~DMA_SCR_ALLINTS; + + /* Disable the DMA stream */ + + regval &= ~DMA_SCR_EN; + dmast_putreg(dmast, STM32_DMA_SCR_OFFSET, regval); + + /* Clear pending stream interrupts by setting bits in the upper or lower + * IFCR register. + */ + + if (dmast->stream < 4) + { + regoffset = STM32_DMA_LIFCR_OFFSET; + } + else + { + regoffset = STM32_DMA_HIFCR_OFFSET; + } + + dmabase_putreg(dmast, regoffset, (DMA_STREAM_MASK << dmast->shift)); +} + +/**************************************************************************** + * Name: stm32_dmainterrupt + * + * Description: + * DMA interrupt handler + * + ****************************************************************************/ + +static int stm32_dmainterrupt(int irq, void *context, void *arg) +{ + struct stm32_dma_s *dmast; + uint32_t status; + uint32_t regoffset = 0; + unsigned int stream = 0; + unsigned int controller = 0; + + /* Get the stream and the controller that generated the interrupt */ + + if (irq >= STM32_IRQ_DMA1S0 && irq <= STM32_IRQ_DMA1S6) + { + stream = irq - STM32_IRQ_DMA1S0; + controller = DMA1; + } + else if (irq == STM32_IRQ_DMA1S7) + { + stream = 7; + controller = DMA1; + } + else +#if STM32_NDMA > 1 + if (irq >= STM32_IRQ_DMA2S0 && irq <= STM32_IRQ_DMA2S4) + { + stream = irq - STM32_IRQ_DMA2S0; + controller = DMA2; + } + else if (irq >= STM32_IRQ_DMA2S5 && irq <= STM32_IRQ_DMA2S7) + { + stream = irq - STM32_IRQ_DMA2S5 + 5; + controller = DMA2; + } + else +#endif + { + DEBUGPANIC(); + } + + /* Get the stream structure from the stream and controller numbers */ + + dmast = stm32_dmastream(stream, controller); + + /* Select the interrupt status register (either the LISR or HISR) + * based on the stream number that caused the interrupt. + */ + + if (stream < 4) + { + regoffset = STM32_DMA_LISR_OFFSET; + } + else + { + regoffset = STM32_DMA_HISR_OFFSET; + } + + /* Get the interrupt status for this stream */ + + status = (dmabase_getreg(dmast, regoffset) >> dmast->shift) & + DMA_STREAM_MASK; + + /* Clear fetched stream interrupts by setting bits in the upper or lower + * IFCR register. + */ + + if (stream < 4) + { + regoffset = STM32_DMA_LIFCR_OFFSET; + } + else + { + regoffset = STM32_DMA_HIFCR_OFFSET; + } + + dmabase_putreg(dmast, regoffset, (status << dmast->shift)); + + /* Invoke the callback */ + + if (dmast->callback) + { + dmast->callback(dmast, status, dmast->arg); + } + + return OK; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_dmainitialize + * + * Description: + * Initialize the DMA subsystem + * + * Returned Value: + * None + * + ****************************************************************************/ + +void weak_function arm_dma_initialize(void) +{ + struct stm32_dma_s *dmast; + int stream; + + /* Initialize each DMA stream */ + + for (stream = 0; stream < DMA_NSTREAMS; stream++) + { + dmast = &g_dma[stream]; + + /* Attach DMA interrupt vectors */ + + irq_attach(dmast->irq, stm32_dmainterrupt, dmast); + + /* Disable the DMA stream */ + + stm32_dmastreamdisable(dmast); + + /* Enable the IRQ at the NVIC (still disabled at the DMA controller) */ + + up_enable_irq(dmast->irq); + } +} + +/**************************************************************************** + * Name: stm32_dmachannel + * + * Description: + * Allocate a DMA channel. This function gives the caller mutually + * exclusive access to the DMA channel specified by the 'dmamap' argument. + * DMA channels are shared on the STM32: Devices sharing the same DMA + * channel cannot do DMA concurrently! See the DMACHAN_* definitions in + * stm32_dma.h. + * + * If the DMA channel is not available, then stm32_dmachannel() will wait + * until the holder of the channel relinquishes the channel by calling + * stm32_dmafree(). WARNING: If you have two devices sharing a DMA + * channel and the code never releases the channel, the stm32_dmachannel + * call for the other will hang forever in this function! Don't let your + * design do that! + * + * Hmm.. I suppose this interface could be extended to make a non-blocking + * version. Feel free to do that if that is what you need. + * + * Input Parameters: + * dmamap - Identifies the stream/channel resource. For the STM32 F4, this + * is a bit-encoded value as provided by the DMAMAP_* definitions + * in chip/stm32f40xxx_dma.h + * + * Returned Value: + * Provided that 'dmamap' is valid, this function ALWAYS returns a non-NULL + * void* DMA channel handle. (If 'dmamap' is invalid, the function will + * assert if debug is enabled or do something ignorant otherwise). + * + * Assumptions: + * - The caller does not hold he DMA channel. + * - The caller can wait for the DMA channel to be freed if it is no + * available. + * + ****************************************************************************/ + +DMA_HANDLE stm32_dmachannel(unsigned int dmamap) +{ + struct stm32_dma_s *dmast; + int ret; + + /* Get the stream index from the bit-encoded channel value */ + + dmast = stm32_dmamap(dmamap); + DEBUGASSERT(dmast != NULL); + + /* Get exclusive access to the DMA channel -- OR wait until the channel + * is available if it is currently being used by another driver + */ + + ret = nxsem_wait_uninterruptible(&dmast->sem); + if (ret < 0) + { + return NULL; + } + + /* The caller now has exclusive use of the DMA channel. Assign the + * channel to the stream and return an opaque reference to the stream + * structure. + */ + + dmast->channel = STM32_DMA_CHANNEL(dmamap); + return (DMA_HANDLE)dmast; +} + +/**************************************************************************** + * Name: stm32_dmafree + * + * Description: + * Release a DMA channel. If another thread is waiting for this DMA + * channel in a call to stm32_dmachannel, then this function will re-assign + * the DMA channel to that thread and wake it up. NOTE: The 'handle' used + * in this argument must NEVER be used again until stm32_dmachannel() is + * called again to re-gain access to the channel. + * + * Returned Value: + * None + * + * Assumptions: + * - The caller holds the DMA channel. + * - There is no DMA in progress + * + ****************************************************************************/ + +void stm32_dmafree(DMA_HANDLE handle) +{ + struct stm32_dma_s *dmast = (struct stm32_dma_s *)handle; + + DEBUGASSERT(handle != NULL); + + /* Release the channel */ + + nxsem_post(&dmast->sem); +} + +/**************************************************************************** + * Name: stm32_dmasetup + * + * Description: + * Configure DMA before using + * + ****************************************************************************/ + +void stm32_dmasetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr, + size_t ntransfers, uint32_t scr) +{ + struct stm32_dma_s *dmast = (struct stm32_dma_s *)handle; + uint32_t regoffset; + uint32_t regval; + uint32_t timeout; + + dmainfo("paddr: %08" PRIx32 " maddr: %08" PRIx32 + " ntransfers: %zu scr: %08" PRIx32 "\n", + paddr, maddr, ntransfers, scr); + +#ifdef CONFIG_STM32_DMACAPABLE + DEBUGASSERT(stm32_dmacapable(maddr, ntransfers, scr)); +#endif + + /* "If the stream is enabled, disable it by resetting the EN bit in the + * DMA_SxCR register, then read this bit in order to confirm that there is + * no ongoing stream operation. Writing this bit to 0 is not immediately + * effective since it is actually written to 0 once all the current + * transfers have finished. When the EN bit is read as 0, this means that + * the stream is ready to be configured. It is therefore necessary to wait + * for the EN bit to be cleared before starting any stream + * configuration. ..." + */ + + /* Drivers using DMA should manage the streams. If a DMA request + * is not made on an error or an abort occurs. The driver should + * stop the DMA. If it fails to do so we can not just hang waiting + * on the HW that will not change state. + * + * If at the end of waiting the HW is still not ready there is a HW problem + * or a SW usage problem. + * + * Enable DEBUGASSERT to detect this. + */ + + if ((dmast_getreg(dmast, STM32_DMA_SCR_OFFSET) & DMA_SCR_EN) != 0) + { + /* Attempt to disable the DMA stream and wait up to a 100 us for it + * to stop. + */ + + dmast_modifyreg32(dmast, STM32_DMA_SCR_OFFSET, DMA_SCR_EN, 0); + timeout = 100; + while (timeout != 0 && + (dmast_getreg(dmast, STM32_DMA_SCR_OFFSET) & DMA_SCR_EN) != 0) + { + up_udelay(1); + timeout--; + } + + DEBUGASSERT(timeout != 0 && + (dmast_getreg(dmast, STM32_DMA_SCR_OFFSET) & + DMA_SCR_EN) == 0); + } + + /* "... All the stream dedicated bits set in the status register (DMA_LISR + * and DMA_HISR) from the previous data block DMA transfer should be + * cleared before the stream can be re-enabled." + * + * Clear pending stream interrupts by setting bits in the upper or lower + * IFCR register. + */ + + if (dmast->stream < 4) + { + regoffset = STM32_DMA_LIFCR_OFFSET; + } + else + { + regoffset = STM32_DMA_HIFCR_OFFSET; + } + + dmabase_putreg(dmast, regoffset, (DMA_STREAM_MASK << dmast->shift)); + + /* "Set the peripheral register address in the DMA_SPARx register. The data + * will be moved from/to this address to/from the memory after the + * peripheral event. + */ + + dmast_putreg(dmast, STM32_DMA_SPAR_OFFSET, paddr); + + /* "Set the memory address in the DMA_SM0ARx ... register. The data will be + * written to or read from this memory after the peripheral event." + * + * Note that in double-buffered mode it is explicitly assumed that the + * second buffer immediately follows the first. + */ + + dmast_putreg(dmast, STM32_DMA_SM0AR_OFFSET, maddr); + if (scr & DMA_SCR_DBM) + { + dmast_putreg(dmast, STM32_DMA_SM1AR_OFFSET, maddr + ntransfers); + } + + /* "Configure the total number of data items to be transferred in the + * DMA_SNDTRx register. After each peripheral event, this value will be + * decremented." + * + * "When the peripheral flow controller is used for a given stream, + * the value written into the DMA_SxNDTR has no effect on the DMA + * transfer. Actually, whatever the value written, it will be forced by + * hardware to 0xFFFF as soon as the stream is enabled..." + */ + + dmast_putreg(dmast, STM32_DMA_SNDTR_OFFSET, ntransfers); + + /* "Select the DMA channel (request) using CHSEL[2:0] in the DMA_SxCR + * register." + * + * "Configure the stream priority using the PL[1:0] bits in the DMA_SCRx" + * register." + */ + + regval = dmast_getreg(dmast, STM32_DMA_SCR_OFFSET); + regval &= ~(DMA_SCR_PL_MASK | DMA_SCR_CHSEL_MASK); + regval |= scr & DMA_SCR_PL_MASK; + regval |= (uint32_t)dmast->channel << DMA_SCR_CHSEL_SHIFT; + dmast_putreg(dmast, STM32_DMA_SCR_OFFSET, regval); + + /* "Configure the FIFO usage (enable or disable, threshold in transmission + * and reception)" + * + * "Caution is required when choosing the FIFO threshold (bits FTH[1:0] of + * the DMA_SxFCR register) and the size of the memory burst (MBURST[1:0] + * of the DMA_SxCR register): The content pointed by the FIFO threshold + * must exactly match to an integer number of memory burst transfers. + * If this is not in the case, a FIFO error (flag FEIFx of the DMA_HISR + * or DMA_LISR register) will be generated when the stream is enabled, + * then the stream will be automatically disabled." + * + * The FIFO is disabled in circular mode when transferring data from a + * peripheral to memory, as in this case it is usually desirable to know + * that every byte from the peripheral is transferred immediately to memory + * It is not practical to flush the DMA FIFO, as this requires disabling + * the channel which triggers the transfer-complete interrupt. + * + * NOTE: The FEIFx error interrupt is not enabled because the FEIFx seems + * to be reported spuriously causing good transfers to be marked as + * failures. + */ + + regval = dmast_getreg(dmast, STM32_DMA_SFCR_OFFSET); + regval &= ~(DMA_SFCR_FTH_MASK | DMA_SFCR_FS_MASK | DMA_SFCR_FEIE); + if (!((scr & (DMA_SCR_CIRC | DMA_SCR_DIR_MASK)) == + (DMA_SCR_CIRC | DMA_SCR_DIR_P2M))) + { + regval |= (DMA_SFCR_FTH_FULL | DMA_SFCR_DMDIS); + } + + dmast_putreg(dmast, STM32_DMA_SFCR_OFFSET, regval); + + /* "Configure data transfer direction, circular mode, peripheral & memory + * incremented mode, peripheral & memory data size, and interrupt after + * half and/or full transfer in the DMA_CCRx register." + * + * Note: The CT bit is always reset. + */ + + regval = dmast_getreg(dmast, STM32_DMA_SCR_OFFSET); + regval &= ~(DMA_SCR_PFCTRL | DMA_SCR_DIR_MASK | DMA_SCR_PINC | + DMA_SCR_MINC | DMA_SCR_PSIZE_MASK | DMA_SCR_MSIZE_MASK | + DMA_SCR_PINCOS | DMA_SCR_CIRC | DMA_SCR_DBM | DMA_SCR_CT | + DMA_SCR_PBURST_MASK | DMA_SCR_MBURST_MASK); + scr &= (DMA_SCR_PFCTRL | DMA_SCR_DIR_MASK | DMA_SCR_PINC | + DMA_SCR_MINC | DMA_SCR_PSIZE_MASK | DMA_SCR_MSIZE_MASK | + DMA_SCR_PINCOS | DMA_SCR_DBM | DMA_SCR_CIRC | + DMA_SCR_PBURST_MASK | DMA_SCR_MBURST_MASK); + regval |= scr; + dmast_putreg(dmast, STM32_DMA_SCR_OFFSET, regval); +} + +/**************************************************************************** + * Name: stm32_dmastart + * + * Description: + * Start the DMA transfer + * + * Assumptions: + * - DMA handle allocated by stm32_dmachannel() + * - No DMA in progress + * + ****************************************************************************/ + +void stm32_dmastart(DMA_HANDLE handle, dma_callback_t callback, void *arg, + bool half) +{ + struct stm32_dma_s *dmast = (struct stm32_dma_s *)handle; + uint32_t scr; + + DEBUGASSERT(handle != NULL); + + /* Save the callback info. This will be invoked when the DMA completes. */ + + dmast->callback = callback; + dmast->arg = arg; + + /* Activate the stream by setting the ENABLE bit in the DMA_SCRx register. + * As soon as the stream is enabled, it can serve any DMA request from the + * peripheral connected on the stream. + */ + + scr = dmast_getreg(dmast, STM32_DMA_SCR_OFFSET); + scr |= DMA_SCR_EN; + + /* In normal mode, interrupt at either half or full completion. In circular + * and double-buffered modes, always interrupt on buffer wrap, and + * optionally interrupt at the halfway point. + */ + + if ((scr & (DMA_SCR_DBM | DMA_SCR_CIRC)) == 0) + { + /* Once half of the bytes are transferred, the half-transfer flag + * (HTIF) is set and an interrupt is generated if the Half-Transfer + * Interrupt Enable bit (HTIE) is set. At the end of the transfer, + * the Transfer Complete Flag (TCIF) is set and an interrupt is + * generated if the Transfer Complete Interrupt Enable bit (TCIE) + * is set. + */ + + scr |= (half ? + (DMA_SCR_HTIE | DMA_SCR_TEIE) : (DMA_SCR_TCIE | DMA_SCR_TEIE)); + } + else + { + /* In non-stop modes, when the transfer completes it immediately resets + * and starts again. The transfer-complete interrupt is thus always + * enabled, and the half-complete interrupt can be used in circular + * mode to determine when the buffer is half-full or in double-buffered + * mode to determine when one of the two buffers is full. + */ + + scr |= (half ? DMA_SCR_HTIE : 0) | DMA_SCR_TCIE | DMA_SCR_TEIE; + } + + dmast_putreg(dmast, STM32_DMA_SCR_OFFSET, scr); +} + +/**************************************************************************** + * Name: stm32_dmastop + * + * Description: + * Cancel the DMA. After stm32_dmastop() is called, the DMA channel is + * reset and stm32_dmasetup() must be called before stm32_dmastart() can be + * called again + * + * Assumptions: + * - DMA handle allocated by stm32_dmachannel() + * + ****************************************************************************/ + +void stm32_dmastop(DMA_HANDLE handle) +{ + struct stm32_dma_s *dmast = (struct stm32_dma_s *)handle; + stm32_dmastreamdisable(dmast); +} + +/**************************************************************************** + * Name: stm32_dmaresidual + * + * Description: + * Read the DMA bytes-remaining register. + * + * Assumptions: + * - DMA handle allocated by stm32_dmachannel() + * + ****************************************************************************/ + +size_t stm32_dmaresidual(DMA_HANDLE handle) +{ + struct stm32_dma_s *dmast = (struct stm32_dma_s *)handle; + uint32_t residual; + + /* Fetch the count of bytes remaining to be transferred. + * + * If the FIFO is enabled, this count may be inaccurate. ST don't + * appear to document whether this counts the peripheral or the memory + * side of the channel, and they don't make the memory pointer + * available either. + * + * For reception in circular mode the FIFO is disabled in order that + * this value can be useful. + */ + + residual = dmast_getreg(dmast, STM32_DMA_SNDTR_OFFSET); + + return (size_t)residual; +} + +/**************************************************************************** + * Name: stm32_dmacapable + * + * Description: + * Check if the DMA controller can transfer data to/from given memory + * address. This depends on the internal connections in the ARM bus matrix + * of the processor. Note that this only applies to memory addresses, it + * will return false for any peripheral address. + * + * Returned Value: + * True, if transfer is possible. + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_DMACAPABLE +bool stm32_dmacapable(uintptr_t maddr, uint32_t count, uint32_t ccr) +{ + uint32_t transfer_size; + uint32_t burst_length; + uint32_t mend; + + dmainfo("stm32_dmacapable: 0x%08" PRIxPTR "/%" PRIu32 " 0x%08" PRIx32 "\n", + maddr, count, ccr); + + /* Verify that the address conforms to the memory transfer size. + * Transfers to/from memory performed by the DMA controller are + * required to be aligned to their size. + * + * See ST RM0090 rev4, section 9.3.11 + * + * Compute mend inline to avoid a possible non-constant integer + * multiply. + */ + + switch (ccr & DMA_SCR_MSIZE_MASK) + { + case DMA_SCR_MSIZE_8BITS: + transfer_size = 1; + mend = maddr + count - 1; + break; + + case DMA_SCR_MSIZE_16BITS: + transfer_size = 2; + mend = maddr + (count << 1) - 1; + break; + + case DMA_SCR_MSIZE_32BITS: + transfer_size = 4; + mend = maddr + (count << 2) - 1; + break; + + default: + dmainfo("stm32_dmacapable: bad transfer size in CCR\n"); + return false; + } + + if ((maddr & (transfer_size - 1)) != 0) + { + dmainfo("stm32_dmacapable: transfer unaligned\n"); + return false; + } + + /* Verify that burst transfers do not cross a 1KiB boundary. */ + + if ((maddr / 1024) != (mend / 1024)) + { + /* The transfer as a whole crosses a 1KiB boundary. + * Verify that no burst does by asserting that the address + * is aligned to the burst length. + */ + + switch (ccr & DMA_SCR_MBURST_MASK) + { + case DMA_SCR_MBURST_SINGLE: + burst_length = transfer_size; + break; + + case DMA_SCR_MBURST_INCR4: + burst_length = transfer_size << 2; + break; + + case DMA_SCR_MBURST_INCR8: + burst_length = transfer_size << 3; + break; + + case DMA_SCR_MBURST_INCR16: + burst_length = transfer_size << 4; + break; + + default: + dmainfo("stm32_dmacapable: bad burst size in CCR\n"); + return false; + } + + if ((maddr & (burst_length - 1)) != 0) + { + dmainfo("stm32_dmacapable: burst crosses 1KiB\n"); + return false; + } + } + + /* Verify that the transfer is to a memory region that supports DMA. */ + + if ((maddr & STM32_REGION_MASK) != (mend & STM32_REGION_MASK)) + { + dmainfo("stm32_dmacapable: transfer crosses memory region\n"); + return false; + } + + switch (maddr & STM32_REGION_MASK) + { + case STM32_FSMC_BANK1: + case STM32_FSMC_BANK2: + case STM32_FSMC_BANK3: + case STM32_FSMC_BANK4: + case STM32_SRAM_BASE: + + /* All RAM is supported */ + + break; + + case STM32_CODE_BASE: + + /* Everything except the CCM ram is supported */ + + if (maddr >= STM32_CCMRAM_BASE && + (maddr - STM32_CCMRAM_BASE) < 65536) + { + dmainfo("stm32_dmacapable: transfer targets CCMRAM\n"); + return false; + } + + break; + + default: + + /* Everything else is unsupported by DMA */ + + dmainfo("stm32_dmacapable:" + " transfer targets unknown/unsupported region\n"); + return false; + } + + dmainfo("stm32_dmacapable: transfer OK\n"); + return true; +} +#endif + +/**************************************************************************** + * Name: stm32_dmasample + * + * Description: + * Sample DMA register contents + * + * Assumptions: + * - DMA handle allocated by stm32_dmachannel() + * + ****************************************************************************/ + +#ifdef CONFIG_DEBUG_DMA_INFO +void stm32_dmasample(DMA_HANDLE handle, struct stm32_dmaregs_s *regs) +{ + struct stm32_dma_s *dmast = (struct stm32_dma_s *)handle; + irqstate_t flags; + + flags = enter_critical_section(); + regs->lisr = dmabase_getreg(dmast, STM32_DMA_LISR_OFFSET); + regs->hisr = dmabase_getreg(dmast, STM32_DMA_HISR_OFFSET); + regs->scr = dmast_getreg(dmast, STM32_DMA_SCR_OFFSET); + regs->sndtr = dmast_getreg(dmast, STM32_DMA_SNDTR_OFFSET); + regs->spar = dmast_getreg(dmast, STM32_DMA_SPAR_OFFSET); + regs->sm0ar = dmast_getreg(dmast, STM32_DMA_SM0AR_OFFSET); + regs->sm1ar = dmast_getreg(dmast, STM32_DMA_SM1AR_OFFSET); + regs->sfcr = dmast_getreg(dmast, STM32_DMA_SFCR_OFFSET); + leave_critical_section(flags); +} +#endif + +/**************************************************************************** + * Name: stm32_dmadump + * + * Description: + * Dump previously sampled DMA register contents + * + * Assumptions: + * - DMA handle allocated by stm32_dmachannel() + * + ****************************************************************************/ + +#ifdef CONFIG_DEBUG_DMA_INFO +void stm32_dmadump(DMA_HANDLE handle, const struct stm32_dmaregs_s *regs, + const char *msg) +{ + struct stm32_dma_s *dmast = (struct stm32_dma_s *)handle; + uint32_t dmabase = DMA_BASE(dmast->base); + + dmainfo("DMA Registers: %s\n", msg); + dmainfo(" LISR[%08" PRIx32 "]: %08" PRIx32 "\n", + dmabase + STM32_DMA_LISR_OFFSET, regs->lisr); + dmainfo(" HISR[%08" PRIx32 "]: %08" PRIx32 "\n", + dmabase + STM32_DMA_HISR_OFFSET, regs->hisr); + dmainfo(" SCR[%08" PRIx32 "]: %08" PRIx32 "\n", + dmast->base + STM32_DMA_SCR_OFFSET, regs->scr); + dmainfo(" SNDTR[%08" PRIx32 "]: %08" PRIx32 "\n", + dmast->base + STM32_DMA_SNDTR_OFFSET, regs->sndtr); + dmainfo(" SPAR[%08" PRIx32 "]: %08" PRIx32 "\n", + dmast->base + STM32_DMA_SPAR_OFFSET, regs->spar); + dmainfo(" SM0AR[%08" PRIx32 "]: %08" PRIx32 "\n", + dmast->base + STM32_DMA_SM0AR_OFFSET, regs->sm0ar); + dmainfo(" SM1AR[%08" PRIx32 "]: %08" PRIx32 "\n", + dmast->base + STM32_DMA_SM1AR_OFFSET, regs->sm1ar); + dmainfo(" SFCR[%08" PRIx32 "]: %08" PRIx32 "\n", + dmast->base + STM32_DMA_SFCR_OFFSET, regs->sfcr); +} +#endif + +#ifdef CONFIG_ARCH_HIPRI_INTERRUPT + +/**************************************************************************** + * Name: stm32_dma_intack + * + * Description: + * Public visible interface to acknowledge interrupts on DMA stream + * + ****************************************************************************/ + +void stm32_dma_intack(unsigned int controller, uint8_t stream, uint32_t isr) +{ + struct stm32_dma_s *dmast = stm32_dmastream(stream, controller); + uint32_t regval = 0; + uint32_t offset = 0; + + /* Select the interrupt flag clear register (either the LIFCR or HIFCR) + * based on the stream number + */ + + if (stream < 4) + { + offset = STM32_DMA_LIFCR_OFFSET; + } + else + { + offset = STM32_DMA_HIFCR_OFFSET; + } + + /* Get value to write */ + + regval |= ((isr & DMA_STREAM_MASK) << dmast->shift); + + /* Write register */ + + dmabase_putreg(dmast, offset, regval); +} + +/**************************************************************************** + * Name: stm32_dma_intget + * + * Description: + * Public visible interface to get pending interrupts from DMA stream + * + ****************************************************************************/ + +uint8_t stm32_dma_intget(unsigned int controller, uint8_t stream) +{ + struct stm32_dma_s *dmast = stm32_dmastream(stream, controller); + uint32_t regval = 0; + uint32_t offset = 0; + + /* Select the interrupt status register (either the LISR or HISR) + * based on the stream number + */ + + if (stream < 4) + { + offset = STM32_DMA_LISR_OFFSET; + } + else + { + offset = STM32_DMA_HISR_OFFSET; + } + + /* Get register value */ + + regval = dmabase_getreg(dmast, offset); + + /* Get stream status */ + + regval = ((regval >> dmast->shift) & DMA_STREAM_MASK); + + return (uint8_t)regval; +} +#endif /* CONFIG_ARCH_HIPRI_INTERRUPT */ diff --git a/arch/arm/src/common/stm32/stm32_dumpgpio_m3m4_v1.c b/arch/arm/src/common/stm32/stm32_dumpgpio_m3m4_v1.c new file mode 100644 index 0000000000000..429e3e70a16d4 --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_dumpgpio_m3m4_v1.c @@ -0,0 +1,263 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_dumpgpio_m3m4_v1.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/* Output debug info even if debug output is not selected. */ + +#undef CONFIG_DEBUG_INFO +#define CONFIG_DEBUG_INFO 1 + +#include +#include + +#include +#include + +#include "arm_internal.h" +#include "chip.h" +#include "stm32_gpio.h" +#include "stm32_rcc.h" + +#ifdef CONFIG_DEBUG_FEATURES + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* Port letters for prettier debug output */ + +static const char g_portchar[STM32_NGPIO_PORTS] = +{ +#if STM32_NGPIO_PORTS > 11 +# error "Additional support required for this number of GPIOs" +#elif STM32_NGPIO_PORTS > 10 + 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 'I', 'J', 'K' +#elif STM32_NGPIO_PORTS > 9 + 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 'I', 'J' +#elif STM32_NGPIO_PORTS > 8 + 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 'I' +#elif STM32_NGPIO_PORTS > 7 + 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H' +#elif STM32_NGPIO_PORTS > 6 + 'A', 'B', 'C', 'D', 'E', 'F', 'G' +#elif STM32_NGPIO_PORTS > 5 + 'A', 'B', 'C', 'D', 'E', 'F' +#elif STM32_NGPIO_PORTS > 4 + 'A', 'B', 'C', 'D', 'E' +#elif STM32_NGPIO_PORTS > 3 + 'A', 'B', 'C', 'D' +#elif STM32_NGPIO_PORTS > 2 + 'A', 'B', 'C' +#elif STM32_NGPIO_PORTS > 1 + 'A', 'B' +#elif STM32_NGPIO_PORTS > 0 + 'A' +#else +# error "Bad number of GPIOs" +#endif +}; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Function: stm32_dumpgpio + * + * Description: + * Dump all GPIO registers associated with the provided base address + * + ****************************************************************************/ + +int stm32_dumpgpio(uint32_t pinset, const char *msg) +{ + irqstate_t flags; + uint32_t base; + unsigned int port; + + /* Get the base address associated with the GPIO port */ + + port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; + base = g_gpiobase[port]; + + /* The following requires exclusive access to the GPIO registers */ + + flags = enter_critical_section(); + +#if defined(CONFIG_STM32_STM32F10XX) + _info("GPIO%c pinset: %08" PRIx32 " base: %08" PRIx32 " -- %s\n", + g_portchar[port], pinset, base, msg); + + if ((getreg32(STM32_RCC_APB2ENR) & RCC_APB2ENR_IOPEN(port)) != 0) + { + _info(" CR: %08" PRIx32 " %08" PRIx32 " IDR: %04" PRIx32 + " ODR: %04" PRIx32 " LCKR: %04" PRIx32 "\n", + getreg32(base + STM32_GPIO_CRH_OFFSET), + getreg32(base + STM32_GPIO_CRL_OFFSET), + getreg32(base + STM32_GPIO_IDR_OFFSET), + getreg32(base + STM32_GPIO_ODR_OFFSET), + getreg32(base + STM32_GPIO_LCKR_OFFSET)); + _info(" EVCR: %02" PRIx32 " MAPR: %08" PRIx32 " CR: %04" PRIx32 + " %04" PRIx32 " %04" PRIx32 " %04" PRIx32 "\n", + getreg32(STM32_AFIO_EVCR), getreg32(STM32_AFIO_MAPR), + getreg32(STM32_AFIO_EXTICR1), + getreg32(STM32_AFIO_EXTICR2), + getreg32(STM32_AFIO_EXTICR3), + getreg32(STM32_AFIO_EXTICR4)); + } + else + { + _info(" GPIO%c not enabled: APB2ENR: %08" PRIx32 "\n", + g_portchar[port], getreg32(STM32_RCC_APB2ENR)); + } + +#elif defined(CONFIG_STM32_STM32L15XX) + DEBUGASSERT(port < STM32_NGPIO_PORTS); + + _info("GPIO%c pinset: %08" PRIx32 " base: %08" PRIx32 " -- %s\n", + g_portchar[port], pinset, base, msg); + + if ((getreg32(STM32_RCC_AHBENR) & RCC_AHBENR_GPIOEN(port)) != 0) + { + _info(" MODE: %08" PRIx32 " OTYPE: %04" PRIx32 + " OSPEED: %08" PRIx32 " PUPDR: %08" PRIx32 "\n", + getreg32(base + STM32_GPIO_MODER_OFFSET), + getreg32(base + STM32_GPIO_OTYPER_OFFSET), + getreg32(base + STM32_GPIO_OSPEED_OFFSET), + getreg32(base + STM32_GPIO_PUPDR_OFFSET)); + _info(" IDR: %04" PRIx32 " ODR: %04" PRIx32 + " BSRR: %08" PRIx32 " LCKR: %04" PRIx32 "\n", + getreg32(base + STM32_GPIO_IDR_OFFSET), + getreg32(base + STM32_GPIO_ODR_OFFSET), + getreg32(base + STM32_GPIO_BSRR_OFFSET), + getreg32(base + STM32_GPIO_LCKR_OFFSET)); + _info(" AFRH: %08" PRIx32 " AFRL: %08" PRIx32 "\n", + getreg32(base + STM32_GPIO_AFRH_OFFSET), + getreg32(base + STM32_GPIO_AFRL_OFFSET)); + } + else + { + _info(" GPIO%c not enabled: AHBENR: %08" PRIx32 "\n", + g_portchar[port], getreg32(STM32_RCC_AHBENR)); + } + +#elif defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX) || \ + defined(CONFIG_STM32_STM32F33XX) + DEBUGASSERT(port < STM32_NGPIO_PORTS); + + _info("GPIO%c pinset: %08" PRIx32 " base: %08" PRIx32 " -- %s\n", + g_portchar[port], pinset, base, msg); + + /* GPIOs are always enabled */ + + _info(" MODE: %08" PRIx32 " OTYPE: %04" PRIx32 + " OSPEED: %08" PRIx32 " PUPDR: %08" PRIx32 "\n", + getreg32(base + STM32_GPIO_MODER_OFFSET), + getreg32(base + STM32_GPIO_OTYPER_OFFSET), + getreg32(base + STM32_GPIO_OSPEED_OFFSET), + getreg32(base + STM32_GPIO_PUPDR_OFFSET)); + _info(" IDR: %04" PRIx32 " ODR: %04" PRIx32 + " BSRR: %08" PRIx32 " LCKR: %04" PRIx32 "\n", + getreg32(base + STM32_GPIO_IDR_OFFSET), + getreg32(base + STM32_GPIO_ODR_OFFSET), + getreg32(base + STM32_GPIO_BSRR_OFFSET), + getreg32(base + STM32_GPIO_LCKR_OFFSET)); + _info(" AFRH: %08" PRIx32 " AFRL: %08" PRIx32 " BRR: %04" PRIx32 "\n", + getreg32(base + STM32_GPIO_AFRH_OFFSET), + getreg32(base + STM32_GPIO_AFRL_OFFSET), + getreg32(base + STM32_GPIO_BRR_OFFSET)); + +#elif defined(CONFIG_STM32_HAVE_IP_EXTI_V1) + DEBUGASSERT(port < STM32_NGPIO_PORTS); + + _info("GPIO%c pinset: %08" PRIx32 " base: %08" PRIx32 " -- %s\n", + g_portchar[port], pinset, base, msg); + + if ((getreg32(STM32_RCC_AHB1ENR) & RCC_AHB1ENR_GPIOEN(port)) != 0) + { + _info(" MODE: %08" PRIx32 " OTYPE: %04" PRIx32 + " OSPEED: %08" PRIx32 " PUPDR: %08" PRIx32 "\n", + getreg32(base + STM32_GPIO_MODER_OFFSET), + getreg32(base + STM32_GPIO_OTYPER_OFFSET), + getreg32(base + STM32_GPIO_OSPEED_OFFSET), + getreg32(base + STM32_GPIO_PUPDR_OFFSET)); + _info(" IDR: %04" PRIx32 " ODR: %04" PRIx32 + " BSRR: %08" PRIx32 " LCKR: %04" PRIx32 "\n", + getreg32(base + STM32_GPIO_IDR_OFFSET), + getreg32(base + STM32_GPIO_ODR_OFFSET), + getreg32(base + STM32_GPIO_BSRR_OFFSET), + getreg32(base + STM32_GPIO_LCKR_OFFSET)); + _info(" AFRH: %08" PRIx32 " AFRL: %08" PRIx32 "\n", + getreg32(base + STM32_GPIO_AFRH_OFFSET), + getreg32(base + STM32_GPIO_AFRL_OFFSET)); + } + else + { + _info(" GPIO%c not enabled: AHB1ENR: %08" PRIx32 "\n", + g_portchar[port], getreg32(STM32_RCC_AHB1ENR)); + } + +#elif defined(CONFIG_STM32_STM32G4XXX) + DEBUGASSERT(port < STM32_NGPIO_PORTS); + + _info("GPIO%c pinset: %08" PRIx32 " base: %08" PRIx32 " -- %s\n", + g_portchar[port], pinset, base, msg); + + if ((getreg32(STM32_RCC_AHB2ENR) & RCC_AHB2ENR_GPIOEN(port)) != 0) + { + _info(" MODE: %08" PRIx32 " OTYPE: %04" PRIx32 + " OSPEED: %08" PRIx32 " PUPDR: %08" PRIx32 "\n", + getreg32(base + STM32_GPIO_MODER_OFFSET), + getreg32(base + STM32_GPIO_OTYPER_OFFSET), + getreg32(base + STM32_GPIO_OSPEED_OFFSET), + getreg32(base + STM32_GPIO_PUPDR_OFFSET)); + _info(" IDR: %04" PRIx32 " ODR: %04" PRIx32 + " BSRR: %08" PRIx32 " LCKR: %04" PRIx32 "\n", + getreg32(base + STM32_GPIO_IDR_OFFSET), + getreg32(base + STM32_GPIO_ODR_OFFSET), + getreg32(base + STM32_GPIO_BSRR_OFFSET), + getreg32(base + STM32_GPIO_LCKR_OFFSET)); + _info(" AFRH: %08" PRIx32 " AFRL: %08" PRIx32 + " BRR: %04" PRIx32 "\n", + getreg32(base + STM32_GPIO_AFRH_OFFSET), + getreg32(base + STM32_GPIO_AFRL_OFFSET), + getreg32(base + STM32_GPIO_BRR_OFFSET)); + } + else + { + _info(" GPIO%c not enabled: AHB2ENR: %08" PRIx32 "\n", + g_portchar[port], getreg32(STM32_RCC_AHB2ENR)); + } + +#else +# error "Unsupported STM32 chip" +#endif + leave_critical_section(flags); + return OK; +} + +#endif /* CONFIG_DEBUG_FEATURES */ diff --git a/arch/arm/src/common/stm32/stm32_eth.h b/arch/arm/src/common/stm32/stm32_eth.h new file mode 100644 index 0000000000000..6e77273239630 --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_eth.h @@ -0,0 +1,38 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_eth.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_COMPAT_STM32ETH_H +#define __ARCH_ARM_SRC_COMMON_COMPAT_STM32ETH_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#if defined(CONFIG_STM32_HAVE_IP_ETHMAC_M3M4_V1) +# include "stm32_eth_m3m4_v1.h" +#else +# error "Unsupported STM32 stm32_eth" +#endif + +#endif /* __ARCH_ARM_SRC_COMMON_COMPAT_STM32ETH_H */ diff --git a/arch/arm/src/common/stm32/stm32_eth_m3m4_v1.c b/arch/arm/src/common/stm32/stm32_eth_m3m4_v1.c new file mode 100644 index 0000000000000..3fc669d3ff79d --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_eth_m3m4_v1.c @@ -0,0 +1,4412 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_eth_m3m4_v1.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#if defined(CONFIG_NET) && defined(CONFIG_STM32_ETHMAC) + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#if defined(CONFIG_NET_PKT) +# include +#endif + +#include "arm_internal.h" +#include "chip.h" +#include "stm32_gpio.h" +#include "stm32_eth_m3m4_v1.h" +#include "stm32_rcc.h" +#include "stm32_syscfg.h" +#include "stm32_gpio.h" +#include "stm32_eth_m3m4_v1.h" + +#include + +/* STM32_NETHERNET determines the number of physical interfaces + * that will be supported. + */ + +#if STM32_NETHERNET > 0 + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +#if STM32_NETHERNET > 1 +# error "Logic to support multiple Ethernet interfaces is incomplete" +#endif + +/* Work queue support is required. */ + +#if !defined(CONFIG_SCHED_WORKQUEUE) +# error Work queue support is required +#endif + +/* The low priority work queue is preferred. If it is not enabled, LPWORK + * will be the same as HPWORK. + * + * NOTE: However, the network should NEVER run on the high priority work + * queue! That queue is intended only to service short back end interrupt + * processing that never suspends. Suspending the high priority work queue + * may bring the system to its knees! + */ + +#define ETHWORK LPWORK + +#if !defined(CONFIG_STM32_SYSCFG) && !defined(CONFIG_STM32_CONNECTIVITYLINE) +# error "CONFIG_STM32_SYSCFG must be defined in the NuttX configuration" +#endif + +#ifndef CONFIG_STM32_PHYADDR +# error "CONFIG_STM32_PHYADDR must be defined in the NuttX configuration" +#endif + +#if !defined(CONFIG_STM32_MII) && !defined(CONFIG_STM32_RMII) +# warning "Neither CONFIG_STM32_MII nor CONFIG_STM32_RMII defined" +#endif + +#if defined(CONFIG_STM32_MII) && defined(CONFIG_STM32_RMII) +# error "Both CONFIG_STM32_MII and CONFIG_STM32_RMII defined" +#endif + +#ifdef CONFIG_STM32_MII +# if defined(CONFIG_STM32_HAVE_IP_ETHMAC_M3M4_V1) +# if !defined(CONFIG_STM32_MII_MCO1) && !defined(CONFIG_STM32_MII_MCO2) && !defined(CONFIG_STM32_MII_EXTCLK) +# warning "Neither CONFIG_STM32_MII_MCO1, CONFIG_STM32_MII_MCO2, nor CONFIG_STM32_MII_EXTCLK defined" +# endif +# if defined(CONFIG_STM32_MII_MCO1) && defined(CONFIG_STM32_MII_MCO2) +# error "Both CONFIG_STM32_MII_MCO1 and CONFIG_STM32_MII_MCO2 defined" +# endif +# elif defined(CONFIG_STM32_CONNECTIVITYLINE) +# if !defined(CONFIG_STM32_MII_MCO) && !defined(CONFIG_STM32_MII_EXTCLK) +# warning "Neither CONFIG_STM32_MII_MCO nor CONFIG_STM32_MII_EXTCLK defined" +# endif +# endif +#endif + +#ifdef CONFIG_STM32_RMII +# if defined(CONFIG_STM32_HAVE_IP_ETHMAC_M3M4_V1) +# if !defined(CONFIG_STM32_RMII_MCO1) && !defined(CONFIG_STM32_RMII_MCO2) && !defined(CONFIG_STM32_RMII_EXTCLK) +# warning "Neither CONFIG_STM32_RMII_MCO1, CONFIG_STM32_RMII_MCO2, nor CONFIG_STM32_RMII_EXTCLK defined" +# endif +# if defined(CONFIG_STM32_RMII_MCO1) && defined(CONFIG_STM32_RMII_MCO2) +# error "Both CONFIG_STM32_RMII_MCO1 and CONFIG_STM32_RMII_MCO2 defined" +# endif +# elif defined(CONFIG_STM32_CONNECTIVITYLINE) +# if !defined(CONFIG_STM32_RMII_MCO) && !defined(CONFIG_STM32_RMII_EXTCLK) +# warning "Neither CONFIG_STM32_RMII_MCO nor CONFIG_STM32_RMII_EXTCLK defined" +# endif +# endif +#endif + +#ifdef CONFIG_STM32_AUTONEG +# ifndef CONFIG_STM32_PHYSR +# error "CONFIG_STM32_PHYSR must be defined in the NuttX configuration" +# endif +# ifdef CONFIG_STM32_PHYSR_ALTCONFIG +# ifndef CONFIG_STM32_PHYSR_ALTMODE +# error "CONFIG_STM32_PHYSR_ALTMODE must be defined in the NuttX configuration" +# endif +# ifndef CONFIG_STM32_PHYSR_10HD +# error "CONFIG_STM32_PHYSR_10HD must be defined in the NuttX configuration" +# endif +# ifndef CONFIG_STM32_PHYSR_100HD +# error "CONFIG_STM32_PHYSR_100HD must be defined in the NuttX configuration" +# endif +# ifndef CONFIG_STM32_PHYSR_10FD +# error "CONFIG_STM32_PHYSR_10FD must be defined in the NuttX configuration" +# endif +# ifndef CONFIG_STM32_PHYSR_100FD +# error "CONFIG_STM32_PHYSR_100FD must be defined in the NuttX configuration" +# endif +# else +# ifndef CONFIG_STM32_PHYSR_SPEED +# error "CONFIG_STM32_PHYSR_SPEED must be defined in the NuttX configuration" +# endif +# ifndef CONFIG_STM32_PHYSR_100MBPS +# error "CONFIG_STM32_PHYSR_100MBPS must be defined in the NuttX configuration" +# endif +# ifndef CONFIG_STM32_PHYSR_MODE +# error "CONFIG_STM32_PHYSR_MODE must be defined in the NuttX configuration" +# endif +# ifndef CONFIG_STM32_PHYSR_FULLDUPLEX +# error "CONFIG_STM32_PHYSR_FULLDUPLEX must be defined in the NuttX configuration" +# endif +# endif +#endif + +/* These definitions are used to enable the PHY interrupts */ + +#if defined(CONFIG_NETDEV_PHY_IOCTL) && defined(CONFIG_ARCH_PHY_INTERRUPT) +# if defined( CONFIG_ETH0_PHY_AM79C874) +# error missing logic +# elif defined( CONFIG_ETH0_PHY_KS8721) +# error missing logic +# elif defined( CONFIG_ETH0_PHY_KSZ8041) +# error missing logic +# elif defined( CONFIG_ETH0_PHY_KSZ8051) +# error missing logic +# elif defined( CONFIG_ETH0_PHY_KSZ8061) +# error missing logic +# elif defined( CONFIG_ETH0_PHY_KSZ8081) +# define MII_INT_REG MII_KSZ8081_INT +# define MII_INT_SETEN MII_KSZ80X1_INT_LDEN | MII_KSZ80X1_INT_LUEN +# define MII_INT_CLREN 0 +# elif defined( CONFIG_ETH0_PHY_KSZ90x1) +# error missing logic +# elif defined( CONFIG_ETH0_PHY_DP83848C) +# define MII_INT_REG MII_DP83848C_MISR +# define MII_INT_SETEN MII_DP83848C_LINK_INT_EN +# define MII_INT_CLREN 0 +# elif defined( CONFIG_ETH0_PHY_LAN8720) +# error missing logic +# elif defined( CONFIG_ETH0_PHY_LAN8740) +# error missing logic +# elif defined( CONFIG_ETH0_PHY_LAN8740A) +# error missing logic +# elif defined( CONFIG_ETH0_PHY_LAN8742A) +# error missing logic +# elif defined( CONFIG_ETH0_PHY_DM9161) +# error missing logic +# else +# error unknown PHY +# endif +#endif + +/* This driver does not use IPv4 checksum offloading. */ + +#undef CONFIG_STM32_ETH_HWCHECKSUM + +/* Add 4 to the configured buffer size to account for the 2 byte checksum + * memory needed at the end of the maximum size packet. Buffer sizes must + * be an even multiple of 4, 8, or 16 bytes (depending on buswidth). We + * will use the 16-byte alignment in all cases. + */ + +#define OPTIMAL_ETH_BUFSIZE ((CONFIG_NET_ETH_PKTSIZE + 4 + 15) & ~15) + +#ifndef CONFIG_STM32_ETH_BUFSIZE +# define CONFIG_STM32_ETH_BUFSIZE OPTIMAL_ETH_BUFSIZE +#endif + +#if CONFIG_STM32_ETH_BUFSIZE > ETH_TDES1_TBS1_MASK +# error "CONFIG_STM32_ETH_BUFSIZE is too large" +#endif + +#if (CONFIG_STM32_ETH_BUFSIZE & 15) != 0 +# error "CONFIG_STM32_ETH_BUFSIZE must be aligned" +#endif + +#if CONFIG_STM32_ETH_BUFSIZE != OPTIMAL_ETH_BUFSIZE +# warning "You using an incomplete/untested configuration" +#endif + +#ifndef CONFIG_STM32_ETH_NRXDESC +# define CONFIG_STM32_ETH_NRXDESC 8 +#endif +#ifndef CONFIG_STM32_ETH_NTXDESC +# define CONFIG_STM32_ETH_NTXDESC 4 +#endif + +/* We need at least one more free buffer than transmit buffers */ + +#define STM32_ETH_NFREEBUFFERS (CONFIG_STM32_ETH_NTXDESC+1) + +/* Extremely detailed register debug that you would normally never want + * enabled. + */ + +#ifndef CONFIG_DEBUG_NET_INFO +# undef CONFIG_STM32_ETHMAC_REGDEBUG +#endif + +/* Clocking *****************************************************************/ + +/* Set MACMIIAR CR bits depending on HCLK setting */ + +#if STM32_HCLK_FREQUENCY >= 20000000 && STM32_HCLK_FREQUENCY < 35000000 +# define ETH_MACMIIAR_CR ETH_MACMIIAR_CR_20_35 +#elif STM32_HCLK_FREQUENCY >= 35000000 && STM32_HCLK_FREQUENCY < 60000000 +# define ETH_MACMIIAR_CR ETH_MACMIIAR_CR_35_60 +#elif STM32_HCLK_FREQUENCY >= 60000000 && STM32_HCLK_FREQUENCY < 100000000 +# define ETH_MACMIIAR_CR ETH_MACMIIAR_CR_60_100 +#elif STM32_HCLK_FREQUENCY >= 100000000 && STM32_HCLK_FREQUENCY < 150000000 +# define ETH_MACMIIAR_CR ETH_MACMIIAR_CR_100_150 +#elif STM32_HCLK_FREQUENCY >= 150000000 && STM32_HCLK_FREQUENCY <= 180000000 +# define ETH_MACMIIAR_CR ETH_MACMIIAR_CR_150_180 +#else +# error "STM32_HCLK_FREQUENCY not supportable" +#endif + +/* Timing *******************************************************************/ + +/* TX timeout = 1 minute */ + +#define STM32_TXTIMEOUT (60*CLK_TCK) + +/* PHY reset/configuration delays in milliseconds */ + +#define PHY_RESET_DELAY (65) +#define PHY_CONFIG_DELAY (1000) + +/* PHY read/write delays in loop counts */ + +#define PHY_READ_TIMEOUT (0x0004ffff) +#define PHY_WRITE_TIMEOUT (0x0004ffff) +#define PHY_RETRY_TIMEOUT (0x0004ffff) + +/* Register values **********************************************************/ + +/* Clear the MACCR bits that will be setup during MAC initialization (or that + * are cleared unconditionally). Per the reference manual, all reserved bits + * must be retained at their reset value. + * + * ETH_MACCR_RE Bit 2: Receiver enable + * ETH_MACCR_TE Bit 3: Transmitter enable + * ETH_MACCR_DC Bit 4: Deferral check + * ETH_MACCR_BL Bits 5-6: Back-off limit + * ETH_MACCR_APCS Bit 7: Automatic pad/CRC stripping + * ETH_MACCR_RD Bit 9: Retry disable + * ETH_MACCR_IPCO Bit 10: IPv4 checksum offload + * ETH_MACCR_DM Bit 11: Duplex mode + * ETH_MACCR_LM Bit 12: Loopback mode + * ETH_MACCR_ROD Bit 13: Receive own disable + * ETH_MACCR_FES Bit 14: Fast Ethernet speed + * ETH_MACCR_CSD Bit 16: Carrier sense disable + * ETH_MACCR_IFG Bits 17-19: Interframe gap + * ETH_MACCR_JD Bit 22: Jabber disable + * ETH_MACCR_WD Bit 23: Watchdog disable + * ETH_MACCR_CSTF Bits 25: CRC stripping for Type frames (F2/F4 only) + */ + +#if defined(CONFIG_STM32_HAVE_IP_ETHMAC_M3M4_V1) +#define MACCR_CLEAR_BITS \ + (ETH_MACCR_RE | ETH_MACCR_TE | ETH_MACCR_DC | ETH_MACCR_BL_MASK | \ + ETH_MACCR_APCS | ETH_MACCR_RD | ETH_MACCR_IPCO | ETH_MACCR_DM | \ + ETH_MACCR_LM | ETH_MACCR_ROD | ETH_MACCR_FES | ETH_MACCR_CSD | \ + ETH_MACCR_IFG_MASK | ETH_MACCR_JD | ETH_MACCR_WD | ETH_MACCR_CSTF) +#else +#define MACCR_CLEAR_BITS \ + (ETH_MACCR_RE | ETH_MACCR_TE | ETH_MACCR_DC | ETH_MACCR_BL_MASK | \ + ETH_MACCR_APCS | ETH_MACCR_RD | ETH_MACCR_IPCO | ETH_MACCR_DM | \ + ETH_MACCR_LM | ETH_MACCR_ROD | ETH_MACCR_FES | ETH_MACCR_CSD | \ + ETH_MACCR_IFG_MASK | ETH_MACCR_JD | ETH_MACCR_WD) +#endif + +/* The following bits are set or left zero unconditionally in all modes. + * + * ETH_MACCR_RE Receiver enable 0 (disabled) + * ETH_MACCR_TE Transmitter enable 0 (disabled) + * ETH_MACCR_DC Deferral check 0 (disabled) + * ETH_MACCR_BL Back-off limit 0 (10) + * ETH_MACCR_APCS Automatic pad/CRC stripping 0 (disabled) + * ETH_MACCR_RD Retry disable 1 (disabled) + * ETH_MACCR_IPCO IPv4 checksum offload Depends on + * CONFIG_STM32_ETH_HWCHECKSUM + * ETH_MACCR_LM Loopback mode 0 (disabled) + * ETH_MACCR_ROD Receive own disable 0 (enabled) + * ETH_MACCR_CSD Carrier sense disable 0 (enabled) + * ETH_MACCR_IFG Interframe gap 0 (96 bits) + * ETH_MACCR_JD Jabber disable 0 (enabled) + * ETH_MACCR_WD Watchdog disable 0 (enabled) + * ETH_MACCR_CSTF CRC stripping for Type frames 0 (disabled, F2/F4 only) + * + * The following are set conditioinally based on mode and speed. + * + * ETH_MACCR_DM Duplex mode Depends on priv->fduplex + * ETH_MACCR_FES Fast Ethernet speed Depends on priv->mbps100 + */ + +#ifdef CONFIG_STM32_ETH_HWCHECKSUM +# define MACCR_SET_BITS \ + (ETH_MACCR_BL_10 | ETH_MACCR_RD | ETH_MACCR_IPCO | ETH_MACCR_IFG(96)) +#else +# define MACCR_SET_BITS \ + (ETH_MACCR_BL_10 | ETH_MACCR_RD | ETH_MACCR_IFG(96)) +#endif + +/* Clear the MACCR bits that will be setup during MAC initialization (or that + * are cleared unconditionally). Per the reference manual, all reserved bits + * must be retained at their reset value. + * + * ETH_MACFFR_PM Bit 0: Promiscuous mode + * ETH_MACFFR_HU Bit 1: Hash unicast + * ETH_MACFFR_HM Bit 2: Hash multicast + * ETH_MACFFR_DAIF Bit 3: Destination address inverse filtering + * ETH_MACFFR_PAM Bit 4: Pass all multicast + * ETH_MACFFR_BFD Bit 5: Broadcast frames disable + * ETH_MACFFR_PCF Bits 6-7: Pass control frames + * ETH_MACFFR_SAIF Bit 8: Source address inverse filtering + * ETH_MACFFR_SAF Bit 9: Source address filter + * ETH_MACFFR_HPF Bit 10: Hash or perfect filter + * ETH_MACFFR_RA Bit 31: Receive all + */ + +#define MACFFR_CLEAR_BITS \ + (ETH_MACFFR_PM | ETH_MACFFR_HU | ETH_MACFFR_HM | ETH_MACFFR_DAIF | \ + ETH_MACFFR_PAM | ETH_MACFFR_BFD | ETH_MACFFR_PCF_MASK | ETH_MACFFR_SAIF | \ + ETH_MACFFR_SAF | ETH_MACFFR_HPF | ETH_MACFFR_RA) + +/* The following bits are set or left zero unconditionally in all modes. + * + * ETH_MACFFR_HU Hash unicast 0 (perfect dest filtering) + * ETH_MACFFR_HM Hash multicast 0 (perfect dest filtering) + * ETH_MACFFR_DAIF Destination address 0 (normal) + * inverse filtering + * ETH_MACFFR_PAM Pass all multicast 0 (Depends on HM bit) + * ETH_MACFFR_BFD Broadcast frames disable 0 (enabled) + * ETH_MACFFR_PCF Pass control frames 1 (block all but PAUSE) + * ETH_MACFFR_SAIF Source address inverse 0 (not used) + * filtering + * ETH_MACFFR_SAF Source address filter 0 (disabled) + * ETH_MACFFR_HPF Hash or perfect filter 0 (Only matching frames passed) + * ETH_MACFFR_RA Receive all 0 (disabled) + */ + +#ifdef CONFIG_NET_PROMISCUOUS +# define MACFFR_SET_BITS (ETH_MACFFR_PCF_PAUSE | ETH_MACFFR_PM) +#else +# define MACFFR_SET_BITS (ETH_MACFFR_PCF_PAUSE) +#endif + +/* Clear the MACFCR bits that will be setup during MAC initialization (or + * that are cleared unconditionally). Per the reference manual, all reserved + * bits must be retained at their reset value. + * + * ETH_MACFCR_FCB_BPA Bit 0: Flow control busy/back pressure activate + * ETH_MACFCR_TFCE Bit 1: Transmit flow control enable + * ETH_MACFCR_RFCE Bit 2: Receive flow control enable + * ETH_MACFCR_UPFD Bit 3: Unicast pause frame detect + * ETH_MACFCR_PLT Bits 4-5: Pause low threshold + * ETH_MACFCR_ZQPD Bit 7: Zero-quanta pause disable + * ETH_MACFCR_PT Bits 16-31: Pause time + */ + +#define MACFCR_CLEAR_MASK \ + (ETH_MACFCR_FCB_BPA | ETH_MACFCR_TFCE | ETH_MACFCR_RFCE | ETH_MACFCR_UPFD | \ + ETH_MACFCR_PLT_MASK | ETH_MACFCR_ZQPD | ETH_MACFCR_PT_MASK) + +/* The following bits are set or left zero unconditionally in all modes. + * + * ETH_MACFCR_FCB_BPA Flow control busy/back 0 (no pause control frame) + * activate pressure + * ETH_MACFCR_TFCE Transmit flow control enable 0 (disabled) + * ETH_MACFCR_RFCE Receive flow control enable 0 (disabled) + * ETH_MACFCR_UPFD Unicast pause frame detect 0 (disabled) + * ETH_MACFCR_PLT Pause low threshold 0 (pause time - 4) + * ETH_MACFCR_ZQPD Zero-quanta pause disable 1 (disabled) + * ETH_MACFCR_PT Pause time 0 + */ + +#define MACFCR_SET_MASK (ETH_MACFCR_PLT_M4 | ETH_MACFCR_ZQPD) + +/* Clear the DMAOMR bits that will be setup during MAC initialization (or + * that are cleared unconditionally). Per the reference manual, all reserved + * bits must be retained at their reset value. + * + * ETH_DMAOMR_SR Bit 1: Start/stop receive + * TH_DMAOMR_OSF Bit 2: Operate on second frame + * ETH_DMAOMR_RTC Bits 3-4: Receive threshold control + * ETH_DMAOMR_FUGF Bit 6: Forward undersized good frames + * ETH_DMAOMR_FEF Bit 7: Forward error frames + * ETH_DMAOMR_ST Bit 13: Start/stop transmission + * ETH_DMAOMR_TTC Bits 14-16: Transmit threshold control + * ETH_DMAOMR_FTF Bit 20: Flush transmit FIFO + * ETH_DMAOMR_TSF Bit 21: Transmit store and forward + * ETH_DMAOMR_DFRF Bit 24: Disable flushing of received frames + * ETH_DMAOMR_RSF Bit 25: Receive store and forward + * TH_DMAOMR_DTCEFD Bit 26: Dropping of TCP/IP checksum error frames disable + */ + +#define DMAOMR_CLEAR_MASK \ + (ETH_DMAOMR_SR | ETH_DMAOMR_OSF | ETH_DMAOMR_RTC_MASK | ETH_DMAOMR_FUGF | \ + ETH_DMAOMR_FEF | ETH_DMAOMR_ST | ETH_DMAOMR_TTC_MASK | ETH_DMAOMR_FTF | \ + ETH_DMAOMR_TSF | ETH_DMAOMR_DFRF | ETH_DMAOMR_RSF | ETH_DMAOMR_DTCEFD) + +/* The following bits are set or left zero unconditionally in all modes. + * + * ETH_DMAOMR_SR Start/stop receive 0 (not running) + * TH_DMAOMR_OSF Operate on second frame 1 (enabled) + * ETH_DMAOMR_RTC Receive threshold control 0 (64 bytes) + * ETH_DMAOMR_FUGF Forward undersized good 0 (disabled) + * frames + * ETH_DMAOMR_FEF Forward error frames 0 (disabled) + * ETH_DMAOMR_ST Start/stop transmission 0 (not running) + * ETH_DMAOMR_TTC Transmit threshold control 0 (64 bytes) + * ETH_DMAOMR_FTF Flush transmit FIFO 0 (no flush) + * ETH_DMAOMR_TSF Transmit store and forward 1 (enabled) + * ETH_DMAOMR_DFRF Disable flushing of received 0 (enabled) + * frames + * ETH_DMAOMR_RSF Receive store and forward 1 (enabled) + * TH_DMAOMR_DTCEFD Dropping of TCP/IP checksum Depends on + * error frames disable CONFIG_STM32_ETH_HWCHECKSUM + * + * When the checksum offload feature is enabled, we need to enable the Store + * and Forward mode: the store and forward guarantee that a whole frame is + * stored in the FIFO, so the MAC can insert/verify the checksum, if the + * checksum is OK the DMA can handle the frame otherwise the frame is dropped + */ + +#ifdef CONFIG_STM32_ETH_HWCHECKSUM +# define DMAOMR_SET_MASK \ + (ETH_DMAOMR_OSF | ETH_DMAOMR_RTC_64 | ETH_DMAOMR_TTC_64 | \ + ETH_DMAOMR_TSF | ETH_DMAOMR_RSF) +#else +# define DMAOMR_SET_MASK \ + (ETH_DMAOMR_OSF | ETH_DMAOMR_RTC_64 | ETH_DMAOMR_TTC_64 | \ + ETH_DMAOMR_TSF | ETH_DMAOMR_RSF | ETH_DMAOMR_DTCEFD) +#endif + +/* Clear the DMABMR bits that will be setup during MAC initialization (or + * that are cleared unconditionally). Per the reference manual, all reserved + * bits must be retained at their reset value. + * + * ETH_DMABMR_SR Bit 0: Software reset + * ETH_DMABMR_DA Bit 1: DMA Arbitration + * ETH_DMABMR_DSL Bits 2-6: Descriptor skip length + * ETH_DMABMR_EDFE Bit 7: Enhanced descriptor format enable + * ETH_DMABMR_PBL Bits 8-13: Programmable burst length + * ETH_DMABMR_RTPR Bits 14-15: RX TX priority ratio + * ETH_DMABMR_FB Bit 16: Fixed burst + * ETH_DMABMR_RDP Bits 17-22: RX DMA PBL + * ETH_DMABMR_USP Bit 23: Use separate PBL + * ETH_DMABMR_FPM Bit 24: 4xPBL mode + * ETH_DMABMR_AAB Bit 25: Address-aligned beats + * ETH_DMABMR_MB Bit 26: Mixed burst (F2/F4 only) + */ + +#if defined(CONFIG_STM32_HAVE_IP_ETHMAC_M3M4_V1) +#define DMABMR_CLEAR_MASK \ + (ETH_DMABMR_SR | ETH_DMABMR_DA | ETH_DMABMR_DSL_MASK | ETH_DMABMR_EDFE | \ + ETH_DMABMR_PBL_MASK | ETH_DMABMR_RTPR_MASK | ETH_DMABMR_FB | ETH_DMABMR_RDP_MASK | \ + ETH_DMABMR_USP | ETH_DMABMR_FPM | ETH_DMABMR_AAB | ETH_DMABMR_MB) +#else +#define DMABMR_CLEAR_MASK \ + (ETH_DMABMR_SR | ETH_DMABMR_DA | ETH_DMABMR_DSL_MASK | ETH_DMABMR_EDFE | \ + ETH_DMABMR_PBL_MASK | ETH_DMABMR_RTPR_MASK | ETH_DMABMR_FB | ETH_DMABMR_RDP_MASK | \ + ETH_DMABMR_USP | ETH_DMABMR_FPM | ETH_DMABMR_AAB) +#endif + +/* The following bits are set or left zero unconditionally in all modes. + * + * + * ETH_DMABMR_SR Software reset 0 (no reset) + * ETH_DMABMR_DA DMA Arbitration 0 (round robin) + * ETH_DMABMR_DSL Descriptor skip length 0 + * ETH_DMABMR_EDFE Enhanced descriptor format Depends on + * enable CONFIG_STM32_ETH_ENHANCEDDESC + * ETH_DMABMR_PBL Programmable burst length 32 beats + * ETH_DMABMR_RTPR RX TX priority ratio 2:1 + * ETH_DMABMR_FB Fixed burst 1 (enabled) + * ETH_DMABMR_RDP RX DMA PBL 32 beats + * ETH_DMABMR_USP Use separate PBL 1 (enabled) + * ETH_DMABMR_FPM 4xPBL mode 0 (disabled) + * ETH_DMABMR_AAB Address-aligned beats 1 (enabled) + * ETH_DMABMR_MB Mixed burst 0 (disabled, F2/F4 only) + */ + +#ifdef CONFIG_STM32_ETH_ENHANCEDDESC +# define DMABMR_SET_MASK \ + (ETH_DMABMR_DSL(0) | ETH_DMABMR_PBL(32) | ETH_DMABMR_EDFE | ETH_DMABMR_RTPR_2TO1 | \ + ETH_DMABMR_FB | ETH_DMABMR_RDP(32) | ETH_DMABMR_USP | ETH_DMABMR_AAB) +#else +# define DMABMR_SET_MASK \ + (ETH_DMABMR_DSL(0) | ETH_DMABMR_PBL(32) | ETH_DMABMR_RTPR_2TO1 | ETH_DMABMR_FB | \ + ETH_DMABMR_RDP(32) | ETH_DMABMR_USP | ETH_DMABMR_AAB) +#endif + +/* Interrupt bit sets *******************************************************/ + +/* All interrupts in the normal and abnormal interrupt summary. Early + * transmit interrupt (ETI) is excluded from the abnormal set because it + * causes too many interrupts and is not interesting. + */ + +#define ETH_DMAINT_NORMAL \ + (ETH_DMAINT_TI | ETH_DMAINT_TBUI | ETH_DMAINT_RI | ETH_DMAINT_ERI) + +#define ETH_DMAINT_ABNORMAL \ + (ETH_DMAINT_TPSI | ETH_DMAINT_TJTI | ETH_DMAINT_ROI | ETH_DMAINT_TUI | \ + ETH_DMAINT_RBUI | ETH_DMAINT_RPSI | ETH_DMAINT_RWTI | /* ETH_DMAINT_ETI | */ \ + ETH_DMAINT_FBEI) + +/* Normal receive, transmit, error interrupt enable bit sets */ + +#define ETH_DMAINT_RECV_ENABLE (ETH_DMAINT_NIS | ETH_DMAINT_RI) +#define ETH_DMAINT_XMIT_ENABLE (ETH_DMAINT_NIS | ETH_DMAINT_TI) +#define ETH_DMAINT_XMIT_DISABLE (ETH_DMAINT_TI) + +#define ETH_DMAINT_ERROR_ENABLE (ETH_DMAINT_AIS | ETH_DMAINT_ABNORMAL) + +/* Helpers ******************************************************************/ + +/* This is a helper pointer for accessing the contents of the Ethernet + * header + */ + +#define BUF ((struct eth_hdr_s *)priv->dev.d_buf) + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/* The stm32_ethmac_s encapsulates all state information for a single + * hardware interface + */ + +struct stm32_ethmac_s +{ + uint8_t ifup : 1; /* true:ifup false:ifdown */ + uint8_t mbps100 : 1; /* 100MBps operation (vs 10 MBps) */ + uint8_t fduplex : 1; /* Full (vs. half) duplex */ + struct wdog_s txtimeout; /* TX timeout timer */ + struct work_s irqwork; /* For deferring interrupt work to the work queue */ + struct work_s pollwork; /* For deferring poll work to the work queue */ + + /* This holds the information visible to the NuttX network */ + + struct net_driver_s dev; /* Interface understood by the network */ + + /* Used to track transmit and receive descriptors */ + + struct eth_txdesc_s *txhead; /* Next available TX descriptor */ + struct eth_rxdesc_s *rxhead; /* Next available RX descriptor */ + + struct eth_txdesc_s *txtail; /* First "in_flight" TX descriptor */ + struct eth_rxdesc_s *rxcurr; /* First RX descriptor of the segment */ + uint16_t segments; /* RX segment count */ + uint16_t inflight; /* Number of TX transfers "in_flight" */ + sq_queue_t freeb; /* The free buffer list */ + +#ifdef CONFIG_STM32_ETH_TIMESTAMP_RX + uint32_t rxtimelow; /* Received packet timestamp subsecond */ + uint32_t rxtimehigh; /* Received packet timestamp seconds */ +#endif +}; + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* Descriptor allocations */ + +static struct eth_rxdesc_s g_rxtable[CONFIG_STM32_ETH_NRXDESC] + aligned_data(4); +static struct eth_txdesc_s g_txtable[CONFIG_STM32_ETH_NTXDESC] + aligned_data(4); + +/* Buffer allocations */ + +static uint8_t g_rxbuffer[CONFIG_STM32_ETH_NRXDESC * + CONFIG_STM32_ETH_BUFSIZE] aligned_data(4); +static uint8_t g_alloc[STM32_ETH_NFREEBUFFERS * + CONFIG_STM32_ETH_BUFSIZE] aligned_data(4); + +static struct stm32_ethmac_s g_stm32ethmac[STM32_NETHERNET]; + +#ifdef CONFIG_STM32_ETH_PTP_RTC_HIRES +static spinlock_t g_rtc_lock = SP_UNLOCKED; +volatile bool g_rtc_enabled; +static struct timespec g_stm32_eth_ptp_basetime; +#endif + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/* Register operations ******************************************************/ + +#if defined(CONFIG_STM32_ETHMAC_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES) +static uint32_t stm32_getreg(uint32_t addr); +static void stm32_putreg(uint32_t val, uint32_t addr); +static void stm32_checksetup(void); +#else +# define stm32_getreg(addr) getreg32(addr) +# define stm32_putreg(val,addr) putreg32(val,addr) +# define stm32_checksetup() +#endif + +/* Free buffer management */ + +static void stm32_initbuffer(struct stm32_ethmac_s *priv, uint8_t *alloc); +static inline uint8_t *stm32_allocbuffer(struct stm32_ethmac_s *priv); +static inline void stm32_freebuffer(struct stm32_ethmac_s *priv, + uint8_t *buffer); +static inline bool stm32_isfreebuffer(struct stm32_ethmac_s *priv); + +/* Common TX logic */ + +static int stm32_transmit(struct stm32_ethmac_s *priv); +static int stm32_txpoll(struct net_driver_s *dev); +static void stm32_dopoll(struct stm32_ethmac_s *priv); + +/* Interrupt handling */ + +static void stm32_enableint(struct stm32_ethmac_s *priv, + uint32_t ierbit); +static void stm32_disableint(struct stm32_ethmac_s *priv, + uint32_t ierbit); + +static void stm32_freesegment(struct stm32_ethmac_s *priv, + struct eth_rxdesc_s *rxfirst, int segments); +static int stm32_recvframe(struct stm32_ethmac_s *priv); +static void stm32_receive(struct stm32_ethmac_s *priv); +static void stm32_freeframe(struct stm32_ethmac_s *priv); +static void stm32_txdone(struct stm32_ethmac_s *priv); + +static void stm32_interrupt_work(void *arg); +static int stm32_interrupt(int irq, void *context, void *arg); + +/* Watchdog timer expirations */ + +static void stm32_txtimeout_work(void *arg); +static void stm32_txtimeout_expiry(wdparm_t arg); + +/* NuttX callback functions */ + +static int stm32_ifup(struct net_driver_s *dev); +static int stm32_ifdown(struct net_driver_s *dev); + +static void stm32_txavail_work(void *arg); +static int stm32_txavail(struct net_driver_s *dev); + +#if defined(CONFIG_NET_MCASTGROUP) || defined(CONFIG_NET_ICMPv6) +static int stm32_addmac(struct net_driver_s *dev, const uint8_t *mac); +#endif +#ifdef CONFIG_NET_MCASTGROUP +static int stm32_rmmac(struct net_driver_s *dev, const uint8_t *mac); +#endif +#ifdef CONFIG_NETDEV_IOCTL +static int stm32_ioctl(struct net_driver_s *dev, int cmd, + unsigned long arg); +#endif + +/* Descriptor Initialization */ + +static void stm32_txdescinit(struct stm32_ethmac_s *priv, + struct eth_txdesc_s *txtable); +static void stm32_rxdescinit(struct stm32_ethmac_s *priv, + struct eth_rxdesc_s *rxtable, + uint8_t *rxbuffer); + +/* PHY Initialization */ + +#if defined(CONFIG_NETDEV_PHY_IOCTL) && defined(CONFIG_ARCH_PHY_INTERRUPT) +static int stm32_phyintenable(struct stm32_ethmac_s *priv); +#endif +#if defined(CONFIG_STM32_AUTONEG) || defined(CONFIG_NETDEV_PHY_IOCTL) || \ + defined(CONFIG_ETH0_PHY_DM9161) +static int stm32_phyread(uint16_t phydevaddr, uint16_t phyregaddr, + uint16_t *value); +#endif +static int stm32_phywrite(uint16_t phydevaddr, uint16_t phyregaddr, + uint16_t value); +#ifdef CONFIG_ETH0_PHY_DM9161 +static inline int stm32_dm9161(struct stm32_ethmac_s *priv); +#endif +static int stm32_phyinit(struct stm32_ethmac_s *priv); + +/* MAC/DMA Initialization */ + +#ifdef CONFIG_STM32_MII +static inline void stm32_selectmii(void); +#endif +#ifdef CONFIG_STM32_RMII +static inline void stm32_selectrmii(void); +#endif +static inline void stm32_ethgpioconfig(struct stm32_ethmac_s *priv); +static int stm32_ethreset(struct stm32_ethmac_s *priv); +static int stm32_macconfig(struct stm32_ethmac_s *priv); +static void stm32_macaddress(struct stm32_ethmac_s *priv); +static int stm32_macenable(struct stm32_ethmac_s *priv); +static int stm32_ethconfig(struct stm32_ethmac_s *priv); + +/* PTP initialization and access */ + +#ifdef CONFIG_STM32_ETH_PTP +static int stm32_eth_ptp_adjust(long ppb); +static void stm32_eth_ptp_init(uint64_t timestamp); +static uint64_t stm32_eth_ptp_gettime(void); +#endif + +#ifdef CONFIG_STM32_ETH_TIMESTAMP_RX +static void stm32_eth_ptp_convert_rxtime(struct stm32_ethmac_s *priv); +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_getreg + * + * Description: + * This function may to used to intercept an monitor all register accesses. + * Clearly this is nothing you would want to do unless you are debugging + * this driver. + * + * Input Parameters: + * addr - The register address to read + * + * Returned Value: + * The value read from the register + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_ETHMAC_REGDEBUG +static uint32_t stm32_getreg(uint32_t addr) +{ + static uint32_t prevaddr = 0; + static uint32_t preval = 0; + static uint32_t count = 0; + + /* Read the value from the register */ + + uint32_t val = getreg32(addr); + + /* Is this the same value that we read from the same register last time? + * Are we polling the register? If so, suppress some of the output. + */ + + if (addr == prevaddr && val == preval) + { + if (count == 0xffffffff || ++count > 3) + { + if (count == 4) + { + ninfo("...\n"); + } + + return val; + } + } + + /* No this is a new address or value */ + + else + { + /* Did we print "..." for the previous value? */ + + if (count > 3) + { + /* Yes.. then show how many times the value repeated */ + + ninfo("[repeats %d more times]\n", count - 3); + } + + /* Save the new address, value, and count */ + + prevaddr = addr; + preval = val; + count = 1; + } + + /* Show the register value read */ + + ninfo("%08" PRIx32 "->%08" PRIx32 "\n", addr, val); + return val; +} +#endif + +/**************************************************************************** + * Name: stm32_putreg + * + * Description: + * This function may to used to intercept an monitor all register accesses. + * Clearly this is nothing you would want to do unless you are debugging + * this driver. + * + * Input Parameters: + * val - The value to write to the register + * addr - The register address to read + * + * Returned Value: + * None + * + ****************************************************************************/ + +#if defined(CONFIG_STM32_ETHMAC_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES) +static void stm32_putreg(uint32_t val, uint32_t addr) +{ + /* Show the register value being written */ + + ninfo("%08" PRIx32 "<-%08" PRIx32 "\n", addr, val); + + /* Write the value */ + + putreg32(val, addr); +} +#endif + +/**************************************************************************** + * Name: stm32_checksetup + * + * Description: + * Show the state of critical configuration registers. + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_ETHMAC_REGDEBUG +static void stm32_checksetup(void) +{ +} +#endif + +/**************************************************************************** + * Function: stm32_initbuffer + * + * Description: + * Initialize the free buffer list. + * + * Input Parameters: + * priv - Reference to the driver state structure + * + * Returned Value: + * None + * + * Assumptions: + * Called during early driver initialization before Ethernet interrupts + * are enabled. + * + ****************************************************************************/ + +static void stm32_initbuffer(struct stm32_ethmac_s *priv, uint8_t *alloc) +{ + uint8_t *buffer; + int i; + + /* Initialize the head of the free buffer list */ + + sq_init(&priv->freeb); + + /* Add all of the pre-allocated buffers to the free buffer list */ + + for (i = 0, buffer = alloc; + i < STM32_ETH_NFREEBUFFERS; + i++, buffer += CONFIG_STM32_ETH_BUFSIZE) + { + sq_addlast((sq_entry_t *)buffer, &priv->freeb); + } +} + +/**************************************************************************** + * Function: stm32_allocbuffer + * + * Description: + * Allocate one buffer from the free buffer list. + * + * Input Parameters: + * priv - Reference to the driver state structure + * + * Returned Value: + * Pointer to the allocated buffer on success; NULL on failure + * + * Assumptions: + * May or may not be called from an interrupt handler. In either case, + * global interrupts are disabled, either explicitly or indirectly through + * interrupt handling logic. + * + ****************************************************************************/ + +static inline uint8_t *stm32_allocbuffer(struct stm32_ethmac_s *priv) +{ + /* Allocate a buffer by returning the head of the free buffer list */ + + return (uint8_t *)sq_remfirst(&priv->freeb); +} + +/**************************************************************************** + * Function: stm32_freebuffer + * + * Description: + * Return a buffer to the free buffer list. + * + * Input Parameters: + * priv - Reference to the driver state structure + * buffer - A pointer to the buffer to be freed + * + * Returned Value: + * None + * + * Assumptions: + * May or may not be called from an interrupt handler. In either case, + * global interrupts are disabled, either explicitly or indirectly through + * interrupt handling logic. + * + ****************************************************************************/ + +static inline void stm32_freebuffer(struct stm32_ethmac_s *priv, + uint8_t *buffer) +{ + /* Free the buffer by adding it to the end of the free buffer list */ + + sq_addlast((sq_entry_t *)buffer, &priv->freeb); +} + +/**************************************************************************** + * Function: stm32_isfreebuffer + * + * Description: + * Return TRUE if the free buffer list is not empty. + * + * Input Parameters: + * priv - Reference to the driver state structure + * + * Returned Value: + * True if there are one or more buffers in the free buffer list; + * false if the free buffer list is empty + * + * Assumptions: + * None. + * + ****************************************************************************/ + +static inline bool stm32_isfreebuffer(struct stm32_ethmac_s *priv) +{ + /* Return TRUE if the free buffer list is not empty */ + + return !sq_empty(&priv->freeb); +} + +/**************************************************************************** + * Function: stm32_transmit + * + * Description: + * Start hardware transmission. Called either from the txdone interrupt + * handling or from watchdog based polling. + * + * Input Parameters: + * priv - Reference to the driver state structure + * + * Returned Value: + * OK on success; a negated errno on failure + * + * Assumptions: + * May or may not be called from an interrupt handler. In either case, + * global interrupts are disabled, either explicitly or indirectly through + * interrupt handling logic. + * + ****************************************************************************/ + +static int stm32_transmit(struct stm32_ethmac_s *priv) +{ + struct eth_txdesc_s *txdesc; + struct eth_txdesc_s *txfirst; + + /* The internal (optimal) network buffer size may be configured to be + * larger than the Ethernet buffer size. + */ + +#if OPTIMAL_ETH_BUFSIZE > CONFIG_STM32_ETH_BUFSIZE + uint8_t *buffer; + int bufcount; + int lastsize; + int i; +#endif + + /* Verify that the hardware is ready to send another packet. If we get + * here, then we are committed to sending a packet; Higher level logic + * must have assured that there is no transmission in progress. + */ + + txdesc = priv->txhead; + txfirst = txdesc; + + ninfo("d_len: %d d_buf: %p txhead: %p tdes0: %08" PRIx32 "\n", + priv->dev.d_len, priv->dev.d_buf, txdesc, txdesc->tdes0); + + DEBUGASSERT(txdesc && (txdesc->tdes0 & ETH_TDES0_OWN) == 0); + + /* Is the size to be sent greater than the size of the Ethernet buffer? */ + + DEBUGASSERT(priv->dev.d_len > 0 && priv->dev.d_buf != NULL); + +#if OPTIMAL_ETH_BUFSIZE > CONFIG_STM32_ETH_BUFSIZE + if (priv->dev.d_len > CONFIG_STM32_ETH_BUFSIZE) + { + /* Yes... how many buffers will be need to send the packet? */ + + bufcount = (priv->dev.d_len + (CONFIG_STM32_ETH_BUFSIZE - 1)) / + CONFIG_STM32_ETH_BUFSIZE; + lastsize = priv->dev.d_len - (bufcount - 1) * CONFIG_STM32_ETH_BUFSIZE; + + ninfo("bufcount: %d lastsize: %d\n", bufcount, lastsize); + + /* Set the first segment bit in the first TX descriptor */ + + txdesc->tdes0 |= ETH_TDES0_FS; + + /* Set up all but the last TX descriptor */ + + buffer = priv->dev.d_buf; + + for (i = 0; i < bufcount; i++) + { + /* This could be a normal event but the design does not handle it */ + + DEBUGASSERT((txdesc->tdes0 & ETH_TDES0_OWN) == 0); + + /* Set the Buffer1 address pointer */ + + txdesc->tdes2 = (uint32_t)buffer; + + /* Set the buffer size in all TX descriptors */ + + if (i == (bufcount - 1)) + { + /* This is the last segment. Set the last segment bit in the + * last TX descriptor and ask for an interrupt when this + * segment transfer completes. + */ + + txdesc->tdes0 |= (ETH_TDES0_LS | ETH_TDES0_IC); + + /* This segment is, most likely, of fractional buffersize */ + + txdesc->tdes1 = lastsize; + buffer += lastsize; + } + else + { + /* This is not the last segment. We don't want an interrupt + * when this segment transfer completes. + */ + + txdesc->tdes0 &= ~ETH_TDES0_IC; + + /* The size of the transfer is the whole buffer */ + + txdesc->tdes1 = CONFIG_STM32_ETH_BUFSIZE; + buffer += CONFIG_STM32_ETH_BUFSIZE; + } + + /* Give the descriptor to DMA */ + + txdesc->tdes0 |= ETH_TDES0_OWN; + txdesc = (struct eth_txdesc_s *)txdesc->tdes3; + } + } + else +#endif + { + /* The single descriptor is both the first and last segment. And we do + * want an interrupt when the transfer completes. + */ + + txdesc->tdes0 |= (ETH_TDES0_FS | ETH_TDES0_LS | ETH_TDES0_IC); + + /* Set frame size */ + + DEBUGASSERT(priv->dev.d_len <= CONFIG_STM32_ETH_BUFSIZE); + txdesc->tdes1 = priv->dev.d_len; + + /* Set the Buffer1 address pointer */ + + txdesc->tdes2 = (uint32_t)priv->dev.d_buf; + + /* Set OWN bit of the TX descriptor tdes0. This gives the buffer to + * Ethernet DMA + */ + + txdesc->tdes0 |= ETH_TDES0_OWN; + + /* Point to the next available TX descriptor */ + + txdesc = (struct eth_txdesc_s *)txdesc->tdes3; + } + + /* Remember where we left off in the TX descriptor chain */ + + priv->txhead = txdesc; + + /* Detach the buffer from priv->dev structure. That buffer is now + * "in-flight". + */ + + priv->dev.d_buf = NULL; + priv->dev.d_len = 0; + + /* If there is no other TX buffer, in flight, then remember the location + * of the TX descriptor. This is the location to check for TX done events. + */ + + if (!priv->txtail) + { + DEBUGASSERT(priv->inflight == 0); + priv->txtail = txfirst; + } + + /* Increment the number of TX transfer in-flight */ + + priv->inflight++; + + ninfo("txhead: %p txtail: %p inflight: %d\n", + priv->txhead, priv->txtail, priv->inflight); + + /* If all TX descriptors are in-flight, then we have to disable receive + * interrupts too. This is because receive events can trigger more + * un-stoppable transmit events. + */ + + if (priv->inflight >= CONFIG_STM32_ETH_NTXDESC) + { + stm32_disableint(priv, ETH_DMAINT_RI); + } + + /* Check if the TX Buffer unavailable flag is set */ + + if ((stm32_getreg(STM32_ETH_DMASR) & ETH_DMAINT_TBUI) != 0) + { + /* Clear TX Buffer unavailable flag */ + + stm32_putreg(ETH_DMAINT_TBUI, STM32_ETH_DMASR); + + /* Resume DMA transmission */ + + stm32_putreg(0, STM32_ETH_DMATPDR); + } + + /* Enable TX interrupts */ + + stm32_enableint(priv, ETH_DMAINT_TI); + + /* Setup the TX timeout watchdog (perhaps restarting the timer) */ + + wd_start(&priv->txtimeout, STM32_TXTIMEOUT, + stm32_txtimeout_expiry, (wdparm_t)priv); + return OK; +} + +/**************************************************************************** + * Function: stm32_txpoll + * + * Description: + * The transmitter is available, check if the network has any outgoing + * packets ready to send. This is a callback from devif_poll(). + * devif_poll() may be called: + * + * 1. When the preceding TX packet send is complete, + * 2. When the preceding TX packet send timesout and the interface is reset + * 3. During normal TX polling + * + * Input Parameters: + * dev - Reference to the NuttX driver state structure + * + * Returned Value: + * OK on success; a negated errno on failure + * + * Assumptions: + * May or may not be called from an interrupt handler. In either case, + * global interrupts are disabled, either explicitly or indirectly through + * interrupt handling logic. + * + ****************************************************************************/ + +static int stm32_txpoll(struct net_driver_s *dev) +{ + struct stm32_ethmac_s *priv = + (struct stm32_ethmac_s *)dev->d_private; + + DEBUGASSERT(priv->dev.d_buf != NULL); + + /* Send the packet */ + + stm32_transmit(priv); + DEBUGASSERT(dev->d_len == 0 && dev->d_buf == NULL); + + /* Check if the next TX descriptor is owned by the Ethernet DMA or + * CPU. We cannot perform the TX poll if we are unable to accept + * another packet for transmission. + * + * In a race condition, ETH_TDES0_OWN may be cleared BUT still + * not available because stm32_freeframe() has not yet run. If + * stm32_freeframe() has run, the buffer1 pointer (tdes2) will be + * nullified (and inflight should be < CONFIG_STM32_ETH_NTXDESC). + */ + + if ((priv->txhead->tdes0 & ETH_TDES0_OWN) != 0 || + priv->txhead->tdes2 != 0) + { + /* We have to terminate the poll if we have no more descriptors + * available for another transfer. + */ + + return -EBUSY; + } + + /* We have the descriptor, we can continue the poll. Allocate a new + * buffer for the poll. + */ + + dev->d_buf = stm32_allocbuffer(priv); + + /* We can't continue the poll if we have no buffers */ + + if (dev->d_buf == NULL) + { + /* Terminate the poll. */ + + return -ENOMEM; + } + + /* If zero is returned, the polling will continue until all connections + * have been examined. + */ + + return 0; +} + +/**************************************************************************** + * Function: stm32_dopoll + * + * Description: + * The function is called in order to perform an out-of-sequence TX poll. + * This is done: + * + * 1. After completion of a transmission (stm32_txdone), + * 2. When new TX data is available (stm32_txavail_process), and + * 3. After a TX timeout to restart the sending process + * (stm32_txtimeout_process). + * + * Input Parameters: + * priv - Reference to the driver state structure + * + * Returned Value: + * None + * + * Assumptions: + * Global interrupts are disabled by interrupt handling logic. + * + ****************************************************************************/ + +static void stm32_dopoll(struct stm32_ethmac_s *priv) +{ + struct net_driver_s *dev = &priv->dev; + + /* Check if the next TX descriptor is owned by the Ethernet DMA or + * CPU. We cannot perform the TX poll if we are unable to accept + * another packet for transmission. + * + * In a race condition, ETH_TDES0_OWN may be cleared BUT still + * not available because stm32_freeframe() has not yet run. If + * stm32_freeframe() has run, the buffer1 pointer (tdes2) will be + * nullified (and inflight should be < CONFIG_STM32_ETH_NTXDESC). + */ + + if ((priv->txhead->tdes0 & ETH_TDES0_OWN) == 0 && + priv->txhead->tdes2 == 0) + { + /* If we have the descriptor, then poll the network for new XMIT data. + * Allocate a buffer for the poll. + */ + + DEBUGASSERT(dev->d_len == 0 && dev->d_buf == NULL); + dev->d_buf = stm32_allocbuffer(priv); + + /* We can't poll if we have no buffers */ + + if (dev->d_buf) + { + devif_poll(dev, stm32_txpoll); + + /* We will, most likely end up with a buffer to be freed. But it + * might not be the same one that we allocated above. + */ + + if (dev->d_buf) + { + DEBUGASSERT(dev->d_len == 0); + stm32_freebuffer(priv, dev->d_buf); + dev->d_buf = NULL; + } + } + } +} + +/**************************************************************************** + * Function: stm32_enableint + * + * Description: + * Enable a "normal" interrupt + * + * Input Parameters: + * priv - Reference to the driver state structure + * + * Returned Value: + * None + * + * Assumptions: + * Global interrupts are disabled by interrupt handling logic. + * + ****************************************************************************/ + +static void stm32_enableint(struct stm32_ethmac_s *priv, + uint32_t ierbit) +{ + uint32_t regval; + + /* Enable the specified "normal" interrupt */ + + regval = stm32_getreg(STM32_ETH_DMAIER); + regval |= (ETH_DMAINT_NIS | ierbit); + stm32_putreg(regval, STM32_ETH_DMAIER); +} + +/**************************************************************************** + * Function: stm32_disableint + * + * Description: + * Disable a normal interrupt. + * + * Input Parameters: + * priv - Reference to the driver state structure + * + * Returned Value: + * None + * + * Assumptions: + * Global interrupts are disabled by interrupt handling logic. + * + ****************************************************************************/ + +static void stm32_disableint(struct stm32_ethmac_s *priv, + uint32_t ierbit) +{ + uint32_t regval; + + /* Disable the "normal" interrupt */ + + regval = stm32_getreg(STM32_ETH_DMAIER); + regval &= ~ierbit; + + /* Are all "normal" interrupts now disabled? */ + + if ((regval & ETH_DMAINT_NORMAL) == 0) + { + /* Yes.. disable normal interrupts */ + + regval &= ~ETH_DMAINT_NIS; + } + + stm32_putreg(regval, STM32_ETH_DMAIER); +} + +/**************************************************************************** + * Function: stm32_freesegment + * + * Description: + * The function is called when a frame is received using the DMA receive + * interrupt. It scans the RX descriptors to the received frame. + * + * Input Parameters: + * priv - Reference to the driver state structure + * + * Returned Value: + * None + * + * Assumptions: + * Global interrupts are disabled by interrupt handling logic. + * + ****************************************************************************/ + +static void stm32_freesegment(struct stm32_ethmac_s *priv, + struct eth_rxdesc_s *rxfirst, int segments) +{ + struct eth_rxdesc_s *rxdesc; + int i; + + ninfo("rxfirst: %p segments: %d\n", rxfirst, segments); + + /* Set OWN bit in RX descriptors. This gives the buffers back to DMA */ + + rxdesc = rxfirst; + for (i = 0; i < segments; i++) + { + rxdesc->rdes0 = ETH_RDES0_OWN; + rxdesc = (struct eth_rxdesc_s *)rxdesc->rdes3; + } + + /* Reset the segment management logic */ + + priv->rxcurr = NULL; + priv->segments = 0; + + /* Check if the RX Buffer unavailable flag is set */ + + if ((stm32_getreg(STM32_ETH_DMASR) & ETH_DMAINT_RBUI) != 0) + { + /* Clear RBUS Ethernet DMA flag */ + + stm32_putreg(ETH_DMAINT_RBUI, STM32_ETH_DMASR); + + /* Resume DMA reception */ + + stm32_putreg(0, STM32_ETH_DMARPDR); + } +} + +/**************************************************************************** + * Function: stm32_recvframe + * + * Description: + * The function is called when a frame is received using the DMA receive + * interrupt. It scans the RX descriptors of the received frame. + * + * NOTE: This function will silently discard any packets containing errors. + * + * Input Parameters: + * priv - Reference to the driver state structure + * + * Returned Value: + * OK if a packet was successfully returned; -EAGAIN if there are no + * further packets available + * + * Assumptions: + * Global interrupts are disabled by interrupt handling logic. + * + ****************************************************************************/ + +static int stm32_recvframe(struct stm32_ethmac_s *priv) +{ + struct eth_rxdesc_s *rxdesc; + struct eth_rxdesc_s *rxcurr; + uint8_t *buffer; + int i; + + ninfo("rxhead: %p rxcurr: %p segments: %d\n", + priv->rxhead, priv->rxcurr, priv->segments); + + /* Check if there are free buffers. We cannot receive new frames in this + * design unless there is at least one free buffer. + */ + + if (!stm32_isfreebuffer(priv)) + { + nerr("ERROR: No free buffers\n"); + return -ENOMEM; + } + + /* Scan descriptors owned by the CPU. Scan until: + * + * 1) We find a descriptor still owned by the DMA, + * 2) We have examined all of the RX descriptors, or + * 3) All of the TX descriptors are in flight. + * + * This last case is obscure. It is due to that fact that each packet + * that we receive can generate an unstoppable transmission. So we have + * to stop receiving when we can not longer transmit. In this case, the + * transmit logic should also have disabled further RX interrupts. + */ + + rxdesc = priv->rxhead; + for (i = 0; + (rxdesc->rdes0 & ETH_RDES0_OWN) == 0 && + i < CONFIG_STM32_ETH_NRXDESC && + priv->inflight < CONFIG_STM32_ETH_NTXDESC; + i++) + { + /* Check if this is the first segment in the frame */ + + if ((rxdesc->rdes0 & ETH_RDES0_FS) != 0 && + (rxdesc->rdes0 & ETH_RDES0_LS) == 0) + { + priv->rxcurr = rxdesc; + priv->segments = 1; + } + + /* Check if this is an intermediate segment in the frame */ + + else if (((rxdesc->rdes0 & ETH_RDES0_LS) == 0) && + ((rxdesc->rdes0 & ETH_RDES0_FS) == 0)) + { + priv->segments++; + } + + /* Otherwise, it is the last segment in the frame */ + + else + { + priv->segments++; + + /* Check if there is only one segment in the frame */ + + if (priv->segments == 1) + { + rxcurr = rxdesc; + } + else + { + rxcurr = priv->rxcurr; + } + + ninfo("rxhead: %p rxcurr: %p segments: %d\n", + priv->rxhead, priv->rxcurr, priv->segments); + + /* Check if any errors are reported in the frame */ + + if ((rxdesc->rdes0 & ETH_RDES0_ES) == 0) + { + struct net_driver_s *dev = &priv->dev; + + /* Get the Frame Length of the received packet: substruct 4 + * bytes of the CRC + */ + + dev->d_len = ((rxdesc->rdes0 & ETH_RDES0_FL_MASK) >> + ETH_RDES0_FL_SHIFT) - 4; + + if (priv->segments > 1 || + dev->d_len > CONFIG_STM32_ETH_BUFSIZE) + { + /* The Frame is to big, it spans segments */ + + nerr("ERROR: Dropped, RX descriptor Too big: %d in %d " + "segments\n", dev->d_len, priv->segments); + + stm32_freesegment(priv, rxcurr, priv->segments); + } + + else + { + /* Get a buffer from the free list. We don't even check if + * this is successful because we already assure the free + * list is not empty above. + */ + + buffer = stm32_allocbuffer(priv); + + /* Take the buffer from the RX descriptor of the first free + * segment, put it into the network device structure, then + * replace the buffer in the RX descriptor with the newly + * allocated buffer. + */ + + DEBUGASSERT(dev->d_buf == NULL); + dev->d_buf = (uint8_t *)rxcurr->rdes2; + rxcurr->rdes2 = (uint32_t)buffer; + +#ifdef CONFIG_STM32_ETH_TIMESTAMP_RX + priv->rxtimelow = rxcurr->rdes6; + priv->rxtimehigh = rxcurr->rdes7; +#endif + + /* Return success, remembering where we should re-start + * scanning and resetting the segment scanning logic + */ + + priv->rxhead = (struct eth_rxdesc_s *)rxdesc->rdes3; + stm32_freesegment(priv, rxcurr, priv->segments); + + ninfo("rxhead: %p d_buf: %p d_len: %d\n", + priv->rxhead, dev->d_buf, dev->d_len); + + return OK; + } + } + else + { + /* Drop the frame that contains the errors, reset the segment + * scanning logic, and continue scanning with the next frame. + */ + + nerr("ERROR: Dropped, RX descriptor errors: %08" PRIx32 "\n", + rxdesc->rdes0); + stm32_freesegment(priv, rxcurr, priv->segments); + } + } + + /* Try the next descriptor */ + + rxdesc = (struct eth_rxdesc_s *)rxdesc->rdes3; + } + + /* We get here after all of the descriptors have been scanned or when + * rxdesc points to the first descriptor owned by the DMA. Remember + * where we left off. + */ + + priv->rxhead = rxdesc; + + ninfo("rxhead: %p rxcurr: %p segments: %d\n", + priv->rxhead, priv->rxcurr, priv->segments); + + return -EAGAIN; +} + +/**************************************************************************** + * Function: stm32_receive + * + * Description: + * An interrupt was received indicating the availability of a new RX packet + * + * Input Parameters: + * priv - Reference to the driver state structure + * + * Returned Value: + * None + * + * Assumptions: + * Global interrupts are disabled by interrupt handling logic. + * + ****************************************************************************/ + +static void stm32_receive(struct stm32_ethmac_s *priv) +{ + struct net_driver_s *dev = &priv->dev; + + /* Loop while while stm32_recvframe() successfully retrieves valid + * Ethernet frames. + */ + + while (stm32_recvframe(priv) == OK) + { +#ifdef CONFIG_NET_PKT + /* When packet sockets are enabled, feed the frame into the tap */ + + pkt_input(&priv->dev); +#endif + + /* Check if the packet is a valid size for the network buffer + * configuration (this should not happen) + */ + + if (dev->d_len > CONFIG_NET_ETH_PKTSIZE) + { + nwarn("WARNING: DROPPED Too big: %d\n", dev->d_len); + + /* Free dropped packet buffer */ + + if (dev->d_buf) + { + stm32_freebuffer(priv, dev->d_buf); + dev->d_buf = NULL; + dev->d_len = 0; + } + + continue; + } + +#ifdef CONFIG_STM32_ETH_TIMESTAMP_RX + stm32_eth_ptp_convert_rxtime(priv); +#endif + + /* We only accept IP packets of the configured type and ARP packets */ + +#ifdef CONFIG_NET_IPv4 + if (BUF->type == HTONS(ETHTYPE_IP)) + { + ninfo("IPv4 frame\n"); + + /* Receive an IPv4 packet from the network device */ + + ipv4_input(&priv->dev); + + /* If the above function invocation resulted in data that should be + * sent out on the network, d_len field will set to a value > 0. + */ + + if (priv->dev.d_len > 0) + { + /* And send the packet */ + + stm32_transmit(priv); + } + } + else +#endif +#ifdef CONFIG_NET_IPv6 + if (BUF->type == HTONS(ETHTYPE_IP6)) + { + ninfo("IPv6 frame\n"); + + /* Give the IPv6 packet to the network layer */ + + ipv6_input(&priv->dev); + + /* If the above function invocation resulted in data that should be + * sent out on the network, d_len field will set to a value > 0. + */ + + if (priv->dev.d_len > 0) + { + /* And send the packet */ + + stm32_transmit(priv); + } + } + else +#endif +#ifdef CONFIG_NET_ARP + if (BUF->type == HTONS(ETHTYPE_ARP)) + { + ninfo("ARP frame\n"); + + /* Handle ARP packet */ + + arp_input(&priv->dev); + + /* If the above function invocation resulted in data that should be + * sent out on the network, d_len field will set to a value > 0. + */ + + if (priv->dev.d_len > 0) + { + stm32_transmit(priv); + } + } + else +#endif + { + nerr("ERROR: Dropped, Unknown type: %04x\n", BUF->type); + } + + /* We are finished with the RX buffer. NOTE: If the buffer is + * reused for transmission, the dev->d_buf field will have been + * nullified. + */ + + if (dev->d_buf) + { + /* Free the receive packet buffer */ + + stm32_freebuffer(priv, dev->d_buf); + dev->d_buf = NULL; + dev->d_len = 0; + } + } +} + +/**************************************************************************** + * Function: stm32_freeframe + * + * Description: + * Scans the TX descriptors and frees the buffers of completed transfers. + * + * Input Parameters: + * priv - Reference to the driver state structure + * + * Returned Value: + * None. + * + * Assumptions: + * Global interrupts are disabled by interrupt handling logic. + * + ****************************************************************************/ + +static void stm32_freeframe(struct stm32_ethmac_s *priv) +{ + struct eth_txdesc_s *txdesc; + + ninfo("txhead: %p txtail: %p inflight: %d\n", + priv->txhead, priv->txtail, priv->inflight); + + /* Scan for "in-flight" descriptors owned by the CPU */ + + txdesc = priv->txtail; + if (txdesc) + { + DEBUGASSERT(priv->inflight > 0); + + while ((txdesc->tdes0 & ETH_TDES0_OWN) == 0) + { + /* There should be a buffer assigned to all in-flight + * TX descriptors. + */ + + ninfo("txtail: %p tdes0: %08" PRIx32 + " tdes2: %08" PRIx32 " tdes3: %08" PRIx32 "\n", + txdesc, txdesc->tdes0, txdesc->tdes2, txdesc->tdes3); + + DEBUGASSERT(txdesc->tdes2 != 0); + + /* Check if this is the first segment of a TX frame. */ + + if ((txdesc->tdes0 & ETH_TDES0_FS) != 0) + { + /* Yes.. Free the buffer */ + + stm32_freebuffer(priv, (uint8_t *)txdesc->tdes2); + } + + /* In any event, make sure that TDES2 is nullified. */ + + txdesc->tdes2 = 0; + + /* Check if this is the last segment of a TX frame */ + + if ((txdesc->tdes0 & ETH_TDES0_LS) != 0) + { + /* Yes.. Decrement the number of frames "in-flight". */ + + priv->inflight--; + + /* If all of the TX descriptors were in-flight, + * then RX interrupts may have been disabled... + * we can re-enable them now. + */ + + stm32_enableint(priv, ETH_DMAINT_RI); + + /* If there are no more frames in-flight, then bail. */ + + if (priv->inflight <= 0) + { + priv->txtail = NULL; + priv->inflight = 0; + return; + } + } + + /* Try the next descriptor in the TX chain */ + + txdesc = (struct eth_txdesc_s *)txdesc->tdes3; + } + + /* We get here if (1) there are still frames "in-flight". Remember + * where we left off. + */ + + priv->txtail = txdesc; + + ninfo("txhead: %p txtail: %p inflight: %d\n", + priv->txhead, priv->txtail, priv->inflight); + } +} + +/**************************************************************************** + * Function: stm32_txdone + * + * Description: + * An interrupt was received indicating that the last TX packet + * transfer(s) are complete. + * + * Input Parameters: + * priv - Reference to the driver state structure + * + * Returned Value: + * None + * + * Assumptions: + * Global interrupts are disabled by the watchdog logic. + * + ****************************************************************************/ + +static void stm32_txdone(struct stm32_ethmac_s *priv) +{ + DEBUGASSERT(priv->txtail != NULL); + + /* Scan the TX descriptor change, returning buffers to free list */ + + stm32_freeframe(priv); + + /* If no further xmits are pending, then cancel the TX timeout */ + + if (priv->inflight <= 0) + { + /* Cancel the TX timeout */ + + wd_cancel(&priv->txtimeout); + + /* And disable further TX interrupts. */ + + stm32_disableint(priv, ETH_DMAINT_TI); + } + + /* Then poll the network for new XMIT data */ + + stm32_dopoll(priv); +} + +/**************************************************************************** + * Function: stm32_interrupt_work + * + * Description: + * Perform interrupt related work from the worker thread + * + * Input Parameters: + * arg - The argument passed when work_queue() was called. + * + * Returned Value: + * OK on success + * + * Assumptions: + * Ethernet interrupts are disabled + * + ****************************************************************************/ + +static void stm32_interrupt_work(void *arg) +{ + struct stm32_ethmac_s *priv = (struct stm32_ethmac_s *)arg; + uint32_t dmasr; + + DEBUGASSERT(priv); + + /* Process pending Ethernet interrupts */ + + net_lock(); + + /* Get the DMA interrupt status bits (no MAC interrupts are expected) */ + + dmasr = stm32_getreg(STM32_ETH_DMASR); + + /* Mask only enabled interrupts. This depends on the fact that the + * interrupt related bits (0-16) correspond in these two registers. + */ + + dmasr &= stm32_getreg(STM32_ETH_DMAIER); + + /* Check if there are pending "normal" interrupts */ + + if ((dmasr & ETH_DMAINT_NIS) != 0) + { + /* Yes.. Check if we received an incoming packet, if so, call + * stm32_receive() + */ + + if ((dmasr & ETH_DMAINT_RI) != 0) + { + /* Clear the pending receive interrupt */ + + stm32_putreg(ETH_DMAINT_RI, STM32_ETH_DMASR); + + /* Handle the received package */ + + stm32_receive(priv); + } + + /* Check if a packet transmission just completed. If so, call + * stm32_txdone(). This may disable further TX interrupts if there + * are no pending transmissions. + */ + + if ((dmasr & ETH_DMAINT_TI) != 0) + { + /* Clear the pending receive interrupt */ + + stm32_putreg(ETH_DMAINT_TI, STM32_ETH_DMASR); + + /* Check if there are pending transmissions */ + + stm32_txdone(priv); + } + + /* Clear the pending normal summary interrupt */ + + stm32_putreg(ETH_DMAINT_NIS, STM32_ETH_DMASR); + } + + /* Check if there are pending "abnormal" interrupts */ + + if ((dmasr & ETH_DMAINT_AIS) != 0) + { + /* Just let the user know what happened */ + + nerr("ERROR: Abnormal event(s): %08" PRIx32 "\n", dmasr); + + /* Clear all pending abnormal events */ + + stm32_putreg(ETH_DMAINT_ABNORMAL, STM32_ETH_DMASR); + + /* Clear the pending abnormal summary interrupt */ + + stm32_putreg(ETH_DMAINT_AIS, STM32_ETH_DMASR); + + /* In case of any error that stops the DMA, reset the MAC. */ + + if (dmasr & (ETH_DMAINT_FBEI | ETH_DMAINT_RPSI | + ETH_DMAINT_TJTI | ETH_DMAINT_TPSI)) + { + /* As per the datasheet's recommendation, the MAC + * needs to be reset for all fatal errors. The + * scheduled job will take the interface down and + * up again. + */ + + work_queue(ETHWORK, &priv->irqwork, stm32_txtimeout_work, priv, 0); + + /* Interrupts need to remain disabled, no other + * processing will take place. After reset + * everything will be restored. + */ + + net_unlock(); + return; + } + } + + net_unlock(); + + /* Re-enable Ethernet interrupts at the NVIC */ + + up_enable_irq(STM32_IRQ_ETH); +} + +/**************************************************************************** + * Function: stm32_interrupt + * + * Description: + * Hardware interrupt handler + * + * Input Parameters: + * irq - Number of the IRQ that generated the interrupt + * context - Interrupt register state save info (architecture-specific) + * + * Returned Value: + * OK on success + * + * Assumptions: + * + ****************************************************************************/ + +static int stm32_interrupt(int irq, void *context, void *arg) +{ + struct stm32_ethmac_s *priv = &g_stm32ethmac[0]; + uint32_t dmasr; + + /* Get the DMA interrupt status bits (no MAC interrupts are expected) */ + + dmasr = stm32_getreg(STM32_ETH_DMASR); + if (dmasr != 0) + { + /* Disable further Ethernet interrupts. Because Ethernet interrupts + * are also disabled if the TX timeout event occurs, there can be no + * race condition here. + */ + + up_disable_irq(STM32_IRQ_ETH); + + /* Check if a packet transmission just completed. */ + + if ((dmasr & ETH_DMAINT_TI) != 0) + { + /* If a TX transfer just completed, then cancel the TX timeout so + * there will be no race condition between any subsequent timeout + * expiration and the deferred interrupt processing. + */ + + wd_cancel(&priv->txtimeout); + } + + /* Schedule to perform the interrupt processing on the worker thread. */ + + work_queue(ETHWORK, &priv->irqwork, stm32_interrupt_work, priv, 0); + } + + return OK; +} + +/**************************************************************************** + * Function: stm32_txtimeout_work + * + * Description: + * Perform TX timeout related work from the worker thread + * + * Input Parameters: + * arg - The argument passed when work_queue() as called. + * + * Returned Value: + * OK on success + * + * Assumptions: + * Ethernet interrupts are disabled + * + ****************************************************************************/ + +static void stm32_txtimeout_work(void *arg) +{ + struct stm32_ethmac_s *priv = (struct stm32_ethmac_s *)arg; + + /* Reset the hardware. Just take the interface down, then back up again. */ + + net_lock(); + stm32_ifdown(&priv->dev); + stm32_ifup(&priv->dev); + + /* Then poll for new XMIT data */ + + stm32_dopoll(priv); + net_unlock(); +} + +/**************************************************************************** + * Function: stm32_txtimeout_expiry + * + * Description: + * Our TX watchdog timed out. Called from the timer interrupt handler. + * The last TX never completed. Reset the hardware and start again. + * + * Input Parameters: + * arg - The argument + * + * Returned Value: + * None + * + * Assumptions: + * Global interrupts are disabled by the watchdog logic. + * + ****************************************************************************/ + +static void stm32_txtimeout_expiry(wdparm_t arg) +{ + struct stm32_ethmac_s *priv = (struct stm32_ethmac_s *)arg; + + nerr("ERROR: Timeout!\n"); + + /* Disable further Ethernet interrupts. This will prevent some race + * conditions with interrupt work. There is still a potential race + * condition with interrupt work that is already queued and in progress. + * + * Interrupts will be re-enabled when stm32_ifup() is called. + */ + + up_disable_irq(STM32_IRQ_ETH); + + /* Schedule to perform the TX timeout processing on the worker thread, + * perhaps canceling any pending IRQ processing. + */ + + work_queue(ETHWORK, &priv->irqwork, stm32_txtimeout_work, priv, 0); +} + +/**************************************************************************** + * Function: stm32_ifup + * + * Description: + * NuttX Callback: Bring up the Ethernet interface when an IP address is + * provided + * + * Input Parameters: + * dev - Reference to the NuttX driver state structure + * + * Returned Value: + * Zero is returned on success; a negated errno value is returned on any + * failure. + * + * Assumptions: + * + ****************************************************************************/ + +static int stm32_ifup(struct net_driver_s *dev) +{ + struct stm32_ethmac_s *priv = + (struct stm32_ethmac_s *)dev->d_private; + int ret; + +#ifdef CONFIG_NET_IPv4 + ninfo("Bringing up: %u.%u.%u.%u\n", + ip4_addr1(dev->d_ipaddr), ip4_addr2(dev->d_ipaddr), + ip4_addr3(dev->d_ipaddr), ip4_addr4(dev->d_ipaddr)); +#endif +#ifdef CONFIG_NET_IPv6 + ninfo("Bringing up: %04x:%04x:%04x:%04x:%04x:%04x:%04x:%04x\n", + dev->d_ipv6addr[0], dev->d_ipv6addr[1], dev->d_ipv6addr[2], + dev->d_ipv6addr[3], dev->d_ipv6addr[4], dev->d_ipv6addr[5], + dev->d_ipv6addr[6], dev->d_ipv6addr[7]); +#endif + + /* Configure the Ethernet interface for DMA operation. */ + + ret = stm32_ethconfig(priv); + if (ret < 0) + { + return ret; + } + +#ifdef CONFIG_STM32_ETH_PTP + /* Enable PTP timer */ + + stm32_eth_ptp_init(0); + +#ifdef CONFIG_STM32_ETH_PTP_RTC_HIRES + if (!g_rtc_enabled) + { + /* Transfer time from system low-resolution timer to PTP basetime */ + + struct timespec ts; + clock_gettime(CLOCK_REALTIME, &ts); + up_rtc_settime(&ts); + g_rtc_enabled = true; + } +#endif /* CONFIG_STM32_ETH_PTP_RTC_HIRES */ + +#endif /* CONFIG_STM32_ETH_PTP */ + + /* Enable the Ethernet interrupt */ + + priv->ifup = true; + up_enable_irq(STM32_IRQ_ETH); + + stm32_checksetup(); + netdev_carrier_on(dev); + return OK; +} + +/**************************************************************************** + * Function: stm32_ifdown + * + * Description: + * NuttX Callback: Stop the interface. + * + * Input Parameters: + * dev - Reference to the NuttX driver state structure + * + * Returned Value: + * Returns zero on success; a negated errno value is returned on any + * failure. + * + * Assumptions: + * + ****************************************************************************/ + +static int stm32_ifdown(struct net_driver_s *dev) +{ + struct stm32_ethmac_s *priv = + (struct stm32_ethmac_s *)dev->d_private; + irqstate_t flags; + int ret = OK; + + ninfo("Taking the network down\n"); + + /* Disable the Ethernet interrupt */ + + flags = enter_critical_section(); + up_disable_irq(STM32_IRQ_ETH); + + /* Cancel the TX timeout timers */ + + wd_cancel(&priv->txtimeout); + +#ifdef CONFIG_STM32_ETH_PTP_RTC_HIRES + if (g_rtc_enabled) + { + /* Transfer back to system low-resolution timer */ + + struct timespec ts; + up_rtc_gettime(&ts); + g_rtc_enabled = false; + clock_settime(CLOCK_REALTIME, &ts); + } +#endif + + /* Put the EMAC in its reset, non-operational state. This should be + * a known configuration that will guarantee the stm32_ifup() always + * successfully brings the interface back up. + */ + + ret = stm32_ethreset(priv); + if (ret < 0) + { + nerr("ERROR: stm32_ethreset failed (timeout), " + "still assuming it's going down.\n"); + } + + /* Mark the device "down" */ + + priv->ifup = false; + netdev_carrier_off(dev); + leave_critical_section(flags); + return ret; +} + +/**************************************************************************** + * Function: stm32_txavail_work + * + * Description: + * Perform an out-of-cycle poll on the worker thread. + * + * Input Parameters: + * arg - Reference to the NuttX driver state structure (cast to void*) + * + * Returned Value: + * None + * + * Assumptions: + * Called on the higher priority worker thread. + * + ****************************************************************************/ + +static void stm32_txavail_work(void *arg) +{ + struct stm32_ethmac_s *priv = (struct stm32_ethmac_s *)arg; + + ninfo("ifup: %d\n", priv->ifup); + + /* Ignore the notification if the interface is not yet up */ + + net_lock(); + if (priv->ifup) + { + /* Poll the network for new XMIT data */ + + stm32_dopoll(priv); + } + + net_unlock(); +} + +/**************************************************************************** + * Function: stm32_txavail + * + * Description: + * Driver callback invoked when new TX data is available. This is a + * stimulus perform an out-of-cycle poll and, thereby, reduce the TX + * latency. + * + * Input Parameters: + * dev - Reference to the NuttX driver state structure + * + * Returned Value: + * None + * + * Assumptions: + * Called in normal user mode + * + ****************************************************************************/ + +static int stm32_txavail(struct net_driver_s *dev) +{ + struct stm32_ethmac_s *priv = + (struct stm32_ethmac_s *)dev->d_private; + + /* Is our single work structure available? It may not be if there are + * pending interrupt actions and we will have to ignore the Tx + * availability action. + */ + + if (work_available(&priv->pollwork)) + { + /* Schedule to serialize the poll on the worker thread. */ + + work_queue(ETHWORK, &priv->pollwork, stm32_txavail_work, priv, 0); + } + + return OK; +} + +/**************************************************************************** + * Function: stm32_calcethcrc + * + * Description: + * Function to calculate the CRC used by STM32 to check an ethernet frame + * + * Input Parameters: + * data - the data to be checked + * length - length of the data + * + * Returned Value: + * None + * + * Assumptions: + * + ****************************************************************************/ + +#if defined(CONFIG_NET_MCASTGROUP) || defined(CONFIG_NET_ICMPv6) +static uint32_t stm32_calcethcrc(const uint8_t *data, size_t length) +{ + uint32_t crc = 0xffffffff; + size_t i; + int j; + + for (i = 0; i < length; i++) + { + for (j = 0; j < 8; j++) + { + if (((crc >> 31) ^ (data[i] >> j)) & 0x01) + { + /* x^26+x^23+x^22+x^16+x^12+x^11+x^10+x^8+x^7+x^5+x^4+x^2+x+1 */ + + crc = (crc << 1) ^ 0x04c11db7; + } + else + { + crc = crc << 1; + } + } + } + + return ~crc; +} +#endif + +/**************************************************************************** + * Function: stm32_addmac + * + * Description: + * NuttX Callback: Add the specified MAC address to the hardware multicast + * address filtering + * + * Input Parameters: + * dev - Reference to the NuttX driver state structure + * mac - The MAC address to be added + * + * Returned Value: + * None + * + * Assumptions: + * + ****************************************************************************/ + +#if defined(CONFIG_NET_MCASTGROUP) || defined(CONFIG_NET_ICMPv6) +static int stm32_addmac(struct net_driver_s *dev, const uint8_t *mac) +{ + uint32_t crc; + uint32_t hashindex; + uint32_t temp; + uint32_t registeraddress; + + ninfo("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n", + mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]); + + /* Add the MAC address to the hardware multicast hash table */ + + crc = stm32_calcethcrc(mac, 6); + + hashindex = (crc >> 26) & 0x3f; + + if (hashindex > 31) + { + registeraddress = STM32_ETH_MACHTHR; + hashindex -= 32; + } + else + { + registeraddress = STM32_ETH_MACHTLR; + } + + temp = stm32_getreg(registeraddress); + temp |= 1 << hashindex; + stm32_putreg(temp, registeraddress); + + temp = stm32_getreg(STM32_ETH_MACFFR); + temp |= (ETH_MACFFR_HM | ETH_MACFFR_HPF); + stm32_putreg(temp, STM32_ETH_MACFFR); + + return OK; +} +#endif /* CONFIG_NET_MCASTGROUP || CONFIG_NET_ICMPv6 */ + +/**************************************************************************** + * Function: stm32_rmmac + * + * Description: + * NuttX Callback: Remove the specified MAC address from the hardware + * multicast address filtering + * + * Input Parameters: + * dev - Reference to the NuttX driver state structure + * mac - The MAC address to be removed + * + * Returned Value: + * None + * + * Assumptions: + * + ****************************************************************************/ + +#ifdef CONFIG_NET_MCASTGROUP +static int stm32_rmmac(struct net_driver_s *dev, const uint8_t *mac) +{ + uint32_t crc; + uint32_t hashindex; + uint32_t temp; + uint32_t registeraddress; + + ninfo("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n", + mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]); + + /* Remove the MAC address to the hardware multicast hash table */ + + crc = stm32_calcethcrc(mac, 6); + + hashindex = (crc >> 26) & 0x3f; + + if (hashindex > 31) + { + registeraddress = STM32_ETH_MACHTHR; + hashindex -= 32; + } + else + { + registeraddress = STM32_ETH_MACHTLR; + } + + temp = stm32_getreg(registeraddress); + temp &= ~(1 << hashindex); + stm32_putreg(temp, registeraddress); + + /* If there is no address registered any more, delete multicast filtering */ + + if (stm32_getreg(STM32_ETH_MACHTHR) == 0 && + stm32_getreg(STM32_ETH_MACHTLR) == 0) + { + temp = stm32_getreg(STM32_ETH_MACFFR); + temp &= ~(ETH_MACFFR_HM | ETH_MACFFR_HPF); + stm32_putreg(temp, STM32_ETH_MACFFR); + } + + return OK; +} +#endif + +/**************************************************************************** + * Function: stm32_txdescinit + * + * Description: + * Initializes the DMA TX descriptors in chain mode. + * + * Input Parameters: + * priv - Reference to the driver state structure + * + * Returned Value: + * None + * + * Assumptions: + * + ****************************************************************************/ + +static void stm32_txdescinit(struct stm32_ethmac_s *priv, + struct eth_txdesc_s *txtable) +{ + struct eth_txdesc_s *txdesc; + int i; + + /* priv->txhead point to the first, available TX descriptor in the chain. + * Set the priv->txhead pointer to the first descriptor in the table. + */ + + priv->txhead = txtable; + + /* priv->txtail will point to the first segment of the oldest pending + * "in-flight" TX transfer. NULL means that there are no active TX + * transfers. + */ + + priv->txtail = NULL; + priv->inflight = 0; + + /* Initialize each TX descriptor */ + + for (i = 0; i < CONFIG_STM32_ETH_NTXDESC; i++) + { + txdesc = &txtable[i]; + + /* Set Second Address Chained bit */ + + txdesc->tdes0 = ETH_TDES0_TCH; + +#ifdef CHECKSUM_BY_HARDWARE + /* Enable the checksum insertion for the TX frames */ + + txdesc->tdes0 |= ETH_TDES0_CIC_ALL; +#endif + + /* Clear Buffer1 address pointer (buffers will be assigned as they + * are used) + */ + + txdesc->tdes2 = 0; + + /* Initialize the next descriptor with + * the Next Descriptor Polling Enable + */ + + if (i < (CONFIG_STM32_ETH_NTXDESC - 1)) + { + /* Set next descriptor address register with next descriptor base + * address + */ + + txdesc->tdes3 = (uint32_t)&txtable[i + 1]; + } + else + { + /* For last descriptor, set next descriptor address register equal + * to the first descriptor base address + */ + + txdesc->tdes3 = (uint32_t)txtable; + } + } + + /* Set Transmit Descriptor List Address Register */ + + stm32_putreg((uint32_t)txtable, STM32_ETH_DMATDLAR); +} + +/**************************************************************************** + * Function: stm32_rxdescinit + * + * Description: + * Initializes the DMA RX descriptors in chain mode. + * + * Input Parameters: + * priv - Reference to the driver state structure + * + * Returned Value: + * None + * + * Assumptions: + * + ****************************************************************************/ + +static void stm32_rxdescinit(struct stm32_ethmac_s *priv, + struct eth_rxdesc_s *rxtable, + uint8_t *rxbuffer) +{ + struct eth_rxdesc_s *rxdesc; + int i; + + /* priv->rxhead will point to the first, RX descriptor in the chain. + * This will be where we receive the first incomplete frame. + */ + + priv->rxhead = rxtable; + + /* If we accumulate the frame in segments, priv->rxcurr points to the + * RX descriptor of the first segment in the current TX frame. + */ + + priv->rxcurr = NULL; + priv->segments = 0; + + /* Initialize each TX descriptor */ + + for (i = 0; i < CONFIG_STM32_ETH_NRXDESC; i++) + { + rxdesc = &rxtable[i]; + + /* Set Own bit of the RX descriptor rdes0 */ + + rxdesc->rdes0 = ETH_RDES0_OWN; + + /* Set Buffer1 size and Second Address Chained bit and enabled DMA + * RX desc receive interrupt + */ + + rxdesc->rdes1 = ETH_RDES1_RCH | (uint32_t)CONFIG_STM32_ETH_BUFSIZE; + + /* Set Buffer1 address pointer */ + + rxdesc->rdes2 = (uint32_t)&rxbuffer[i * CONFIG_STM32_ETH_BUFSIZE]; + + /* Initialize the next descriptor with + * the Next Descriptor Polling Enable + */ + + if (i < (CONFIG_STM32_ETH_NRXDESC - 1)) + { + /* Set next descriptor address register with next descriptor base + * address + */ + + rxdesc->rdes3 = (uint32_t)&rxtable[i + 1]; + } + else + { + /* For last descriptor, set next descriptor address register equal + * to the first descriptor base address + */ + + rxdesc->rdes3 = (uint32_t)rxtable; + } + } + + /* Set Receive Descriptor List Address Register */ + + stm32_putreg((uint32_t)rxtable, STM32_ETH_DMARDLAR); +} + +/**************************************************************************** + * Function: stm32_ioctl + * + * Description: + * Executes the SIOCxMIIxxx command and responds using the request struct + * that must be provided as its 2nd parameter. + * + * When called with SIOCGMIIPHY it will get the PHY address for the device + * and write it to the req->phy_id field of the request struct. + * + * When called with SIOCGMIIREG it will read a register of the PHY that is + * specified using the req->reg_no struct field and then write its output + * to the req->val_out field. + * + * When called with SIOCSMIIREG it will write to a register of the PHY that + * is specified using the req->reg_no struct field and use req->val_in as + * its input. + * + * Input Parameters: + * dev - Ethernet device structure + * cmd - SIOCxMIIxxx command code + * arg - Request structure also used to return values + * + * Returned Value: Negated errno on failure. + * + * Assumptions: + * + ****************************************************************************/ + +#ifdef CONFIG_NETDEV_IOCTL +static int stm32_ioctl(struct net_driver_s *dev, int cmd, unsigned long arg) +{ +#if defined(CONFIG_NETDEV_PHY_IOCTL) && defined(CONFIG_ARCH_PHY_INTERRUPT) + struct stm32_ethmac_s *priv = + (struct stm32_ethmac_s *)dev->d_private; +#endif + int ret; + + switch (cmd) + { +#ifdef CONFIG_NETDEV_PHY_IOCTL +#ifdef CONFIG_ARCH_PHY_INTERRUPT + case SIOCMIINOTIFY: /* Set up for PHY event notifications */ + { + struct mii_ioctl_notify_s *req = + (struct mii_ioctl_notify_s *)((uintptr_t)arg); + + ret = phy_notify_subscribe(dev->d_ifname, req->pid, &req->event); + if (ret == OK) + { + /* Enable PHY link up/down interrupts */ + + ret = stm32_phyintenable(priv); + } + } + break; +#endif + + case SIOCGMIIPHY: /* Get MII PHY address */ + { + struct mii_ioctl_data_s *req = + (struct mii_ioctl_data_s *)((uintptr_t)arg); + req->phy_id = CONFIG_STM32_PHYADDR; + ret = OK; + } + break; + + case SIOCGMIIREG: /* Get register from MII PHY */ + { + struct mii_ioctl_data_s *req = + (struct mii_ioctl_data_s *)((uintptr_t)arg); + ret = stm32_phyread(req->phy_id, req->reg_num, &req->val_out); + } + break; + + case SIOCSMIIREG: /* Set register in MII PHY */ + { + struct mii_ioctl_data_s *req = + (struct mii_ioctl_data_s *)((uintptr_t)arg); + ret = stm32_phywrite(req->phy_id, req->reg_num, req->val_in); + } + break; +#endif /* CONFIG_NETDEV_PHY_IOCTL */ + + default: + ret = -ENOTTY; + break; + } + + return ret; +} +#endif /* CONFIG_NETDEV_IOCTL */ + +/**************************************************************************** + * Function: stm32_phyintenable + * + * Description: + * Enable link up/down PHY interrupts. The interrupt protocol is like this: + * + * - Interrupt status is cleared when the interrupt is enabled. + * - Interrupt occurs. Interrupt is disabled (at the processor level) when + * is received. + * - Interrupt status is cleared when the interrupt is re-enabled. + * + * Input Parameters: + * priv - A reference to the private driver state structure + * + * Returned Value: + * OK on success; Negated errno (-ETIMEDOUT) on failure. + * + ****************************************************************************/ + +#if defined(CONFIG_NETDEV_PHY_IOCTL) && defined(CONFIG_ARCH_PHY_INTERRUPT) +static int stm32_phyintenable(struct stm32_ethmac_s *priv) +{ + uint16_t phyval; + int ret; + + ret = stm32_phyread(CONFIG_STM32_PHYADDR, MII_INT_REG, &phyval); + if (ret == OK) + { + /* Enable link up/down interrupts */ + +#ifdef CONFIG_ETH0_PHY_DP83848C + ret = stm32_phywrite(CONFIG_STM32_PHYADDR, MII_DP83848C_MICR, + MII_DP83848C_INT_EN | MII_DP83848C_INT_OEN); +#endif + ret = stm32_phywrite(CONFIG_STM32_PHYADDR, MII_INT_REG, + (phyval & ~MII_INT_CLREN) | MII_INT_SETEN); + } + + return ret; +} +#endif + +/**************************************************************************** + * Function: stm32_phyread + * + * Description: + * Read a PHY register. + * + * Input Parameters: + * phydevaddr - The PHY device address + * phyregaddr - The PHY register address + * value - The location to return the 16-bit PHY register value. + * + * Returned Value: + * OK on success; Negated errno on failure. + * + * Assumptions: + * + ****************************************************************************/ + +#if defined(CONFIG_STM32_AUTONEG) || defined(CONFIG_NETDEV_PHY_IOCTL) || \ + defined(CONFIG_ETH0_PHY_DM9161) +static int stm32_phyread(uint16_t phydevaddr, + uint16_t phyregaddr, uint16_t *value) +{ + volatile uint32_t timeout; + uint32_t regval; + + regval = stm32_getreg(STM32_ETH_MACMIIAR); + + /* Clear the busy bit before accessing the MACMIIAR register. */ + + regval &= ~ETH_MACMIIAR_MB; + stm32_putreg(regval, STM32_ETH_MACMIIAR); + + /* Configure the MACMIIAR register, + * preserving CSR Clock Range CR[2:0] bits + */ + + regval &= ETH_MACMIIAR_CR_MASK; + + /* Set the PHY device address, PHY register address, and set the busy bit. + * the ETH_MACMIIAR_MW is clear, indicating a read operation. + */ + + regval |= (phydevaddr << ETH_MACMIIAR_PA_SHIFT) & ETH_MACMIIAR_PA_MASK; + regval |= (phyregaddr << ETH_MACMIIAR_MR_SHIFT) & ETH_MACMIIAR_MR_MASK; + regval |= ETH_MACMIIAR_MB; + + stm32_putreg(regval, STM32_ETH_MACMIIAR); + + /* Wait for the transfer to complete */ + + for (timeout = 0; timeout < PHY_READ_TIMEOUT; timeout++) + { + if ((stm32_getreg(STM32_ETH_MACMIIAR) & ETH_MACMIIAR_MB) == 0) + { + *value = (uint16_t)stm32_getreg(STM32_ETH_MACMIIDR); + return OK; + } + } + + nerr("ERROR: MII transfer timed out: phydevaddr: %04x phyregaddr: %04x\n", + phydevaddr, phyregaddr); + + return -ETIMEDOUT; +} +#endif + +/**************************************************************************** + * Function: stm32_phywrite + * + * Description: + * Write to a PHY register. + * + * Input Parameters: + * phydevaddr - The PHY device address + * phyregaddr - The PHY register address + * value - The 16-bit value to write to the PHY register value. + * + * Returned Value: + * OK on success; Negated errno on failure. + * + * Assumptions: + * + ****************************************************************************/ + +static int stm32_phywrite(uint16_t phydevaddr, + uint16_t phyregaddr, uint16_t value) +{ + volatile uint32_t timeout; + uint32_t regval; + + regval = stm32_getreg(STM32_ETH_MACMIIAR); + + /* Clear the busy bit before accessing the MACMIIAR register. */ + + regval &= ~ETH_MACMIIAR_MB; + stm32_putreg(regval, STM32_ETH_MACMIIAR); + + /* Configure the MACMIIAR register, + * preserving CSR Clock Range CR[2:0] bits + */ + + regval &= ETH_MACMIIAR_CR_MASK; + + /* Set the PHY device address, PHY register address, and set the busy bit. + * the ETH_MACMIIAR_MW is set, indicating a write operation. + */ + + regval |= (phydevaddr << ETH_MACMIIAR_PA_SHIFT) & ETH_MACMIIAR_PA_MASK; + regval |= (phyregaddr << ETH_MACMIIAR_MR_SHIFT) & ETH_MACMIIAR_MR_MASK; + regval |= (ETH_MACMIIAR_MB | ETH_MACMIIAR_MW); + + /* Write the value into the MACIIDR register before setting the new + * MACMIIAR register value. + */ + + stm32_putreg(value, STM32_ETH_MACMIIDR); + stm32_putreg(regval, STM32_ETH_MACMIIAR); + + /* Wait for the transfer to complete */ + + for (timeout = 0; timeout < PHY_WRITE_TIMEOUT; timeout++) + { + if ((stm32_getreg(STM32_ETH_MACMIIAR) & ETH_MACMIIAR_MB) == 0) + { + return OK; + } + } + + nerr("ERROR: MII transfer timed out: " + "phydevaddr: %04x phyregaddr: %04x value: %04x\n", + phydevaddr, phyregaddr, value); + + return -ETIMEDOUT; +} + +/**************************************************************************** + * Function: stm32_dm9161 + * + * Description: + * Special workaround for the Davicom DM9161 PHY is required. On power, + * up, the PHY is not usually configured correctly but will work after + * a powered-up reset. This is really a workaround for some more + * fundamental issue with the PHY clocking initialization, but the + * root cause has not been studied (nor will it be with this workaround). + * + * Input Parameters: + * priv - A reference to the private driver state structure + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_ETH0_PHY_DM9161 +static inline int stm32_dm9161(struct stm32_ethmac_s *priv) +{ + uint16_t phyval; + int ret; + + /* Read the PHYID1 register; A failure to read the PHY ID is one + * indication that check if the DM9161 PHY CHIP is not ready. + */ + + ret = stm32_phyread(CONFIG_STM32_PHYADDR, MII_PHYID1, &phyval); + if (ret < 0) + { + nerr("ERROR: Failed to read the PHY ID1: %d\n", ret); + return ret; + } + + /* If we failed to read the PHY ID1 register, + * then reset the MCU to recover + */ + + else if (phyval == 0xffff) + { + up_systemreset(); + } + + ninfo("PHY ID1: 0x%04X\n", phyval); + + /* Now check the "DAVICOM Specified Configuration Register (DSCR)"(16) */ + + ret = stm32_phyread(CONFIG_STM32_PHYADDR, 16, &phyval); + if (ret < 0) + { + nerr("ERROR: Failed to read the PHY Register 0x10: %d\n", ret); + return ret; + } + + /* Bit 8 of the DSCR register is zero, then the DM9161 has not selected + * RMII. If RMII is not selected, then reset the MCU to recover. + */ + + else if ((phyval & (1 << 8)) == 0) + { + up_systemreset(); + } + + return OK; +} +#endif + +/**************************************************************************** + * Function: stm32_phyinit + * + * Description: + * Configure the PHY and determine the link speed/duplex. + * + * Input Parameters: + * priv - A reference to the private driver state structure + * + * Returned Value: + * OK on success; Negated errno on failure. + * + * Assumptions: + * + ****************************************************************************/ + +static int stm32_phyinit(struct stm32_ethmac_s *priv) +{ +#ifdef CONFIG_STM32_AUTONEG + volatile uint32_t timeout; +#endif + + uint32_t regval; + uint16_t phyval; + int ret; + + /* Assume 10MBps and half duplex */ + + priv->mbps100 = 0; + priv->fduplex = 0; + + /* Setup up PHY clocking by setting the SR field in the MACMIIAR register */ + + regval = stm32_getreg(STM32_ETH_MACMIIAR); + regval &= ~ETH_MACMIIAR_CR_MASK; + regval |= ETH_MACMIIAR_CR; + stm32_putreg(regval, STM32_ETH_MACMIIAR); + + /* Put the PHY in reset mode */ + + ret = stm32_phywrite(CONFIG_STM32_PHYADDR, MII_MCR, MII_MCR_RESET); + if (ret < 0) + { + nerr("ERROR: Failed to reset the PHY: %d\n", ret); + return ret; + } + + up_mdelay(PHY_RESET_DELAY); + + /* Perform any necessary, board-specific PHY initialization */ + +#ifdef CONFIG_STM32_PHYINIT + ret = stm32_phy_boardinitialize(0); + if (ret < 0) + { + nerr("ERROR: Failed to initialize the PHY: %d\n", ret); + return ret; + } +#endif + + /* Special workaround for the Davicom DM9161 PHY is required. */ + +#ifdef CONFIG_ETH0_PHY_DM9161 + ret = stm32_dm9161(priv); + if (ret < 0) + { + return ret; + } +#endif + + /* Perform auto-negotiation if so configured */ + +#ifdef CONFIG_STM32_AUTONEG + /* Wait for link status */ + + for (timeout = 0; timeout < PHY_RETRY_TIMEOUT; timeout++) + { + ret = stm32_phyread(CONFIG_STM32_PHYADDR, MII_MSR, &phyval); + if (ret < 0) + { + nerr("ERROR: Failed to read the PHY MSR: %d\n", ret); + return ret; + } + else if ((phyval & MII_MSR_LINKSTATUS) != 0) + { + break; + } + } + + if (timeout >= PHY_RETRY_TIMEOUT) + { + nerr("ERROR: Timed out waiting for link status: %04x\n", phyval); + return -ETIMEDOUT; + } + + /* Enable auto-gegotiation */ + + ret = stm32_phywrite(CONFIG_STM32_PHYADDR, MII_MCR, MII_MCR_ANENABLE); + if (ret < 0) + { + nerr("ERROR: Failed to enable auto-negotiation: %d\n", ret); + return ret; + } + + /* Wait until auto-negotiation completes */ + + for (timeout = 0; timeout < PHY_RETRY_TIMEOUT; timeout++) + { + ret = stm32_phyread(CONFIG_STM32_PHYADDR, MII_MSR, &phyval); + if (ret < 0) + { + nerr("ERROR: Failed to read the PHY MSR: %d\n", ret); + return ret; + } + else if ((phyval & MII_MSR_ANEGCOMPLETE) != 0) + { + break; + } + } + + if (timeout >= PHY_RETRY_TIMEOUT) + { + nerr("ERROR: Timed out waiting for auto-negotiation\n"); + return -ETIMEDOUT; + } + + /* Read the result of the auto-negotiation from the PHY-specific register */ + + ret = stm32_phyread(CONFIG_STM32_PHYADDR, CONFIG_STM32_PHYSR, &phyval); + if (ret < 0) + { + nerr("ERROR: Failed to read PHY status register\n"); + return ret; + } + + /* Remember the selected speed and duplex modes */ + + ninfo("PHYSR[%d]: %04x\n", CONFIG_STM32_PHYSR, phyval); + + /* Different PHYs present speed and mode information in different ways. + * IF This CONFIG_STM32_PHYSR_ALTCONFIG is selected, this indicates that + * the PHY represents speed and mode information are combined, for example, + * with separate bits for 10HD, 100HD, 10FD and 100FD. + */ + +#ifdef CONFIG_STM32_PHYSR_ALTCONFIG + switch (phyval & CONFIG_STM32_PHYSR_ALTMODE) + { + default: + case CONFIG_STM32_PHYSR_10HD: + priv->fduplex = 0; + priv->mbps100 = 0; + break; + + case CONFIG_STM32_PHYSR_100HD: + priv->fduplex = 0; + priv->mbps100 = 1; + break; + + case CONFIG_STM32_PHYSR_10FD: + priv->fduplex = 1; + priv->mbps100 = 0; + break; + + case CONFIG_STM32_PHYSR_100FD: + priv->fduplex = 1; + priv->mbps100 = 1; + break; + } + + /* Different PHYs present speed and mode information in different ways. + * Some will present separate information for speed and mode (this is the + * default). Those PHYs, for example, may provide a 10/100 Mbps indication + * and a separate full/half duplex indication. + */ + +#else + if ((phyval & CONFIG_STM32_PHYSR_MODE) == CONFIG_STM32_PHYSR_FULLDUPLEX) + { + priv->fduplex = 1; + } + + if ((phyval & CONFIG_STM32_PHYSR_SPEED) == CONFIG_STM32_PHYSR_100MBPS) + { + priv->mbps100 = 1; + } +#endif + +#else /* Auto-negotiation not selected */ + + phyval = 0; +#ifdef CONFIG_STM32_ETHFD + phyval |= MII_MCR_FULLDPLX; +#endif +#ifdef CONFIG_STM32_ETH100MBPS + phyval |= MII_MCR_SPEED100; +#endif + + ret = stm32_phywrite(CONFIG_STM32_PHYADDR, MII_MCR, phyval); + if (ret < 0) + { + nerr("ERROR: Failed to write the PHY MCR: %d\n", ret); + return ret; + } + + up_mdelay(PHY_CONFIG_DELAY); + + /* Remember the selected speed and duplex modes */ + +#ifdef CONFIG_STM32_ETHFD + priv->fduplex = 1; +#endif +#ifdef CONFIG_STM32_ETH100MBPS + priv->mbps100 = 1; +#endif +#endif + + ninfo("Duplex: %s Speed: %d MBps\n", + priv->fduplex ? "FULL" : "HALF", + priv->mbps100 ? 100 : 10); + + return OK; +} + +/**************************************************************************** + * Name: stm32_selectmii + * + * Description: + * Selects the MII interface. + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_MII +static inline void stm32_selectmii(void) +{ + uint32_t regval; + +#ifdef CONFIG_STM32_CONNECTIVITYLINE + regval = getreg32(STM32_AFIO_MAPR); + regval &= ~AFIO_MAPR_MII_RMII_SEL; + putreg32(regval, STM32_AFIO_MAPR); +#else + regval = getreg32(STM32_SYSCFG_PMC); + regval &= ~SYSCFG_PMC_MII_RMII_SEL; + putreg32(regval, STM32_SYSCFG_PMC); +#endif +} +#endif + +/**************************************************************************** + * Name: stm32_selectrmii + * + * Description: + * Selects the RMII interface. + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_RMII +static inline void stm32_selectrmii(void) +{ + uint32_t regval; + +#ifdef CONFIG_STM32_CONNECTIVITYLINE + regval = getreg32(STM32_AFIO_MAPR); + regval |= AFIO_MAPR_MII_RMII_SEL; + putreg32(regval, STM32_AFIO_MAPR); +#else + regval = getreg32(STM32_SYSCFG_PMC); + regval |= SYSCFG_PMC_MII_RMII_SEL; + putreg32(regval, STM32_SYSCFG_PMC); +#endif +} +#endif + +/**************************************************************************** + * Function: stm32_ethgpioconfig + * + * Description: + * Configure GPIOs for the Ethernet interface. + * + * Input Parameters: + * priv - A reference to the private driver state structure + * + * Returned Value: + * None. + * + * Assumptions: + * + ****************************************************************************/ + +static inline void stm32_ethgpioconfig(struct stm32_ethmac_s *priv) +{ + /* Configure GPIO pins to support Ethernet */ + +#if defined(CONFIG_STM32_MII) || defined(CONFIG_STM32_RMII) + + /* MDC and MDIO are common to both modes */ + + stm32_configgpio(GPIO_ETH_MDC); + stm32_configgpio(GPIO_ETH_MDIO); + + /* Set up the MII interface */ + +# if defined(CONFIG_STM32_MII) + + /* Select the MII interface */ + + stm32_selectmii(); + + /* Provide clocking via MCO, MCO1 or MCO2: + * + * "MCO1 (microcontroller clock output), used to output HSI, LSE, HSE or + * PLL clock (through a configurable prescaler) on PA8 pin." + * + * "MCO2 (microcontroller clock output), used to output HSE, PLL, SYSCLK or + * PLLI2S clock (through a configurable prescaler) on PC9 pin." + */ + +# if defined(CONFIG_STM32_MII_MCO1) + /* Configure MC01 to drive the PHY. Board logic must provide MC01 clocking + * info. + */ + + stm32_configgpio(GPIO_MCO1); + stm32_mco1config(BOARD_CFGR_MC01_SOURCE, BOARD_CFGR_MC01_DIVIDER); + +# elif defined(CONFIG_STM32_MII_MCO2) + /* Configure MC02 to drive the PHY. Board logic must provide MC02 clocking + * info. + */ + + stm32_configgpio(GPIO_MCO2); + stm32_mco2config(BOARD_CFGR_MC02_SOURCE, BOARD_CFGR_MC02_DIVIDER); + +# elif defined(CONFIG_STM32_MII_MCO) + /* Setup MCO pin for alternative usage */ + + stm32_configgpio(GPIO_MCO); + stm32_mcoconfig(BOARD_CFGR_MCO_SOURCE); +# endif + + /* MII interface pins (17): + * + * MII_TX_CLK, MII_TXD[3:0], MII_TX_EN, MII_RX_CLK, MII_RXD[3:0], + * MII_RX_ER, MII_RX_DV, MII_CRS, MII_COL, MDC, MDIO + */ + + stm32_configgpio(GPIO_ETH_MII_COL); + stm32_configgpio(GPIO_ETH_MII_CRS); + stm32_configgpio(GPIO_ETH_MII_RXD0); + stm32_configgpio(GPIO_ETH_MII_RXD1); + stm32_configgpio(GPIO_ETH_MII_RXD2); + stm32_configgpio(GPIO_ETH_MII_RXD3); + stm32_configgpio(GPIO_ETH_MII_RX_CLK); + stm32_configgpio(GPIO_ETH_MII_RX_DV); + stm32_configgpio(GPIO_ETH_MII_RX_ER); + stm32_configgpio(GPIO_ETH_MII_TXD0); + stm32_configgpio(GPIO_ETH_MII_TXD1); + stm32_configgpio(GPIO_ETH_MII_TXD2); + stm32_configgpio(GPIO_ETH_MII_TXD3); + stm32_configgpio(GPIO_ETH_MII_TX_CLK); + stm32_configgpio(GPIO_ETH_MII_TX_EN); + + /* Set up the RMII interface. */ + +# elif defined(CONFIG_STM32_RMII) + + /* Select the RMII interface */ + + stm32_selectrmii(); + + /* Provide clocking via MCO, MCO1 or MCO2: + * + * "MCO1 (microcontroller clock output), used to output HSI, LSE, HSE or + * PLL clock (through a configurable prescaler) on PA8 pin." + * + * "MCO2 (microcontroller clock output), used to output HSE, PLL, SYSCLK or + * PLLI2S clock (through a configurable prescaler) on PC9 pin." + */ + +# if defined(CONFIG_STM32_RMII_MCO1) + /* Configure MC01 to drive the PHY. Board logic must provide MC01 clocking + * info. + */ + + stm32_configgpio(GPIO_MCO1); + stm32_mco1config(BOARD_CFGR_MC01_SOURCE, BOARD_CFGR_MC01_DIVIDER); + +# elif defined(CONFIG_STM32_RMII_MCO2) + /* Configure MC02 to drive the PHY. Board logic must provide MC02 clocking + * info. + */ + + stm32_configgpio(GPIO_MCO2); + stm32_mco2config(BOARD_CFGR_MC02_SOURCE, BOARD_CFGR_MC02_DIVIDER); + +# elif defined(CONFIG_STM32_RMII_MCO) + /* Setup MCO pin for alternative usage */ + + stm32_configgpio(GPIO_MCO); + stm32_mcoconfig(BOARD_CFGR_MCO_SOURCE); +# endif + + /* RMII interface pins (7): + * + * RMII_TXD[1:0], RMII_TX_EN, RMII_RXD[1:0], RMII_CRS_DV, MDC, MDIO, + * RMII_REF_CLK + */ + + stm32_configgpio(GPIO_ETH_RMII_CRS_DV); + stm32_configgpio(GPIO_ETH_RMII_REF_CLK); + stm32_configgpio(GPIO_ETH_RMII_RXD0); + stm32_configgpio(GPIO_ETH_RMII_RXD1); + stm32_configgpio(GPIO_ETH_RMII_TXD0); + stm32_configgpio(GPIO_ETH_RMII_TXD1); + stm32_configgpio(GPIO_ETH_RMII_TX_EN); + +# endif +#endif + +#ifdef CONFIG_STM32_ETH_PTP_GPIO + /* Enable pulse-per-second (PPS) output signal */ + + stm32_configgpio(GPIO_ETH_PPS_OUT); +#endif +} + +#ifdef CONFIG_STM32_ETH_PTP + +/**************************************************************************** + * Function: stm32_eth_ptp_adjust + * + * Description: + * Adjust PTP timer run rate. + * + * Input Parameters: + * ppb - Adjustment in parts per billion (nanoseconds per second). + * Zero is default rate, positive value makes clock run faster + * and negative value slower. + * + * Returned Value: + * OK on success, negated errno on failure. + * + * Assumptions: + * Adjustment is between -0.5e9 and +0.5e9 (+- 50%) + * + ****************************************************************************/ + +static int stm32_eth_ptp_adjust(long ppb) +{ + uint32_t regval; + uint64_t addend; + uint32_t increment; + + /* Compute addend value to achieve nominal timer rate. + * Increment is set by stm32_eth_ptp_init() and remains constants after + * that. + */ + + increment = stm32_getreg(STM32_ETH_PTPSSIR) & ETH_PTPSSIR_MASK; + addend = ((uint64_t)1 << (32 + 31)) / (STM32_SYSCLK_FREQUENCY * increment); + + /* Apply rate adjustment, if any */ + + if (ppb != 0) + { + addend += addend * ppb / NSEC_PER_SEC; + } + + /* Check for overflows */ + + if (addend == 0 || (uint32_t)addend != addend) + { + nerr("PTP adjustment out of range: ppb=%ld, addend=%lld\n", + ppb, addend); + return -EINVAL; + } + + /* Perform addend register update */ + + stm32_putreg((uint32_t)addend, STM32_ETH_PTPTSAR); + regval = stm32_getreg(STM32_ETH_PTPTSCR); + stm32_putreg(regval | ETH_PTPTSCR_TSARU, STM32_ETH_PTPTSCR); + up_udelay(1); + if (stm32_getreg(STM32_ETH_PTPTSCR) & ETH_PTPTSCR_TSARU) + { + /* This can happen if Ethernet PHY clock is stopped */ + + nerr("PTP addend update failed\n"); + return -EBUSY; + } + + return OK; +} + +/**************************************************************************** + * Function: stm32_eth_ptp_init + * + * Description: + * Configure the PTP timestamp counter of the Ethernet peripheral. + * + * Input Parameters: + * timestamp: Initial timestamp + * + * Returned Value: + * None + * + * Assumptions: + * + ****************************************************************************/ + +static void stm32_eth_ptp_init(uint64_t timestamp) +{ + uint32_t regval; + uint32_t increment; + + /* The PPS timestamp counter consists of a 32-bit seconds counter and + * 31-bit subsecond counter. The PTP input clock (SYSCLK) is divided by + * 2^32 / ADDEND and multiplied by INCREMENT. This calculation aims for + * ADDEND of 2^31 to provide +- 50% rate adjustment range. + * + * ADDEND value is then adjusted to compensate for rounding errors in + * the 8-bit INCREMENT value. The final rounding error will be less than + * 1 ppb. The timer frequency is approximately half of SYSCLK frequency, + * with phase jitter of one SYSCLK period. + */ + + increment = ((uint32_t)1 << 31) / (STM32_SYSCLK_FREQUENCY / 2); + DEBUGASSERT(increment > 0 && (increment & ETH_PTPSSIR_MASK) == increment); + + /* Timestamp counter initialization process + * (STM32F407 reference manual section 33.5.9 + * "Programming steps for system time generation initialization") + */ + + regval = ETH_PTPTSCR_TSE; + stm32_putreg(regval, STM32_ETH_PTPTSCR); + stm32_putreg(increment, STM32_ETH_PTPSSIR); + + /* Update addend value to default rate */ + + stm32_eth_ptp_adjust(0); + + /* Enable fine update mode */ + + regval |= ETH_PTPTSCR_TSFCU; + stm32_putreg(regval, STM32_ETH_PTPTSCR); + + /* Initialize counter value */ + + stm32_putreg((uint32_t)(timestamp >> 32), STM32_ETH_PTPTSHUR); + stm32_putreg((uint32_t)(timestamp >> 1), STM32_ETH_PTPTSLUR); + stm32_putreg(regval | ETH_PTPTSCR_TSSTI, STM32_ETH_PTPTSCR); + up_udelay(1); + + /* Initialization should complete within a few clock cycles. + * If not, there is probably something wrong with the PHY clock domain. + */ + + if (stm32_getreg(STM32_ETH_PTPTSCR) & ETH_PTPTSCR_TSSTI) + { + nerr("PTP timestamp initialization failed\n"); + } + + /* Enable packet timestamping */ + +#ifdef CONFIG_STM32_ETH_TIMESTAMP_RX + regval |= ETH_PTPTSCR_TSSARFE; + stm32_putreg(regval, STM32_ETH_PTPTSCR); +#endif +} + +/**************************************************************************** + * Name: stm32_eth_ptp_gettime + * + * Description: + * Read PTP timestamp registers. The 64-bit timestamp consists of two + * registers that are updated continuously. This function employs + * double-read pattern to correctly handle overflow of the lower register. + * + * Input Parameters: + * None + * + * Returned Value: + * 64-bit timestamp, where upper 32 bits are the second count and lower + * 32-bits are the subsecond count. + * If timer is not yet initialized, returns 0. + * + * Assumptions: + * Can be called from interrupt or task context. + * + ****************************************************************************/ + +static uint64_t stm32_eth_ptp_gettime(void) +{ + uint32_t high1; + uint32_t low; + uint32_t high2; + + high1 = getreg32(STM32_ETH_PTPTSHR); + low = getreg32(STM32_ETH_PTPTSLR); + high2 = getreg32(STM32_ETH_PTPTSHR); + + if (high1 == high2) + { + return ((uint64_t)high2 << 32) | ((low & ETH_PTPTSLR_MASK) << 1); + } + else + { + /* Lower counter overflowed between the two register reads. + * Take its value as 0. + */ + + return ((uint64_t)high2 << 32); + } +} + +static inline void ptp_to_timespec(uint64_t timestamp, struct timespec *ts) +{ + ts->tv_sec = (timestamp >> 32); + ts->tv_nsec = ((uint32_t)timestamp * (uint64_t)NSEC_PER_SEC) >> 32; +} + +/* Convert RX timestamp to CLOCK_REALTIME */ +#ifdef CONFIG_STM32_ETH_TIMESTAMP_RX +static void stm32_eth_ptp_convert_rxtime(struct stm32_ethmac_s *priv) +{ + uint64_t timestamp; + struct timespec rxtime; + + timestamp = ((uint64_t)priv->rxtimehigh << 32) + | ((priv->rxtimelow & ETH_PTPTSLR_MASK) << 1); + + /* Timestamp of 0 indicates that Ethernet peripheral didn't store the + * timestamp. Timestamp of all ones indicates "corrupt timestamp" + * according to reference manual. In either case, we pass along + * a timestamp of all zeros to application. + */ + + if (timestamp == 0 || timestamp >= UINT64_MAX - 1) + { + nerr("Packet RX timestamp is invalid\n"); + priv->dev.d_rxtime.tv_sec = 0; + priv->dev.d_rxtime.tv_nsec = 0; + return; + } + +#ifdef CONFIG_STM32_ETH_PTP_RTC_HIRES + /* PTP is the system time reference, just add the base time */ + + ptp_to_timespec(timestamp, &rxtime); + clock_timespec_add(&rxtime, &g_stm32_eth_ptp_basetime, + &priv->dev.d_rxtime); + +#else + { + struct timespec realtime; + uint64_t ptptime; + irqstate_t flags; + + /* Sample PTP and CLOCK_REALTIME close to each other */ + + clock_gettime(CLOCK_REALTIME, &realtime); + flags = spin_lock_irqsave(&g_rtc_lock); + ptptime = stm32_eth_ptp_gettime(); + spin_unlock_irqrestore(&g_rtc_lock, flags); + + /* Compute how much time has elapsed since packet reception + * and add that to current time. + */ + + timestamp = ptptime - timestamp; + ptp_to_timespec(timestamp, &rxtime); + clock_timespec_add(&rxtime, &realtime, &priv->dev.d_rxtime); + } +#endif /* CONFIG_STM32_ETH_PTP_RTC_HIRES */ +} +#endif /* CONFIG_STM32_ETH_TIMESTAMP_RX */ + +#endif /* CONFIG_STM32_ETH_PTP */ + +/**************************************************************************** + * Function: stm32_ethreset + * + * Description: + * Reset the Ethernet block. + * + * Input Parameters: + * priv - A reference to the private driver state structure + * + * Returned Value: + * Zero on success, or a negated errno value on any failure. + * + * Assumptions: + * + ****************************************************************************/ + +static int stm32_ethreset(struct stm32_ethmac_s *priv) +{ + uint32_t regval; + uint32_t retries; + + /* Reset the Ethernet on the AHB bus (F1 Connectivity Line) or AHB1 bus (F2 + * and F4) + */ + +#if defined(CONFIG_STM32_CONNECTIVITYLINE) + regval = stm32_getreg(STM32_RCC_AHBRSTR); + regval |= RCC_AHBRSTR_ETHMACRST; + stm32_putreg(regval, STM32_RCC_AHBRSTR); + + regval &= ~RCC_AHBRSTR_ETHMACRST; + stm32_putreg(regval, STM32_RCC_AHBRSTR); +#else + regval = stm32_getreg(STM32_RCC_AHB1RSTR); + regval |= RCC_AHB1RSTR_ETHMACRST; + stm32_putreg(regval, STM32_RCC_AHB1RSTR); + + regval &= ~RCC_AHB1RSTR_ETHMACRST; + stm32_putreg(regval, STM32_RCC_AHB1RSTR); +#endif + + /* Perform a software reset by setting the SR bit in the DMABMR register. + * This Resets all MAC subsystem internal registers and logic. After this + * reset all the registers holds their reset values. + */ + + regval = stm32_getreg(STM32_ETH_DMABMR); + regval |= ETH_DMABMR_SR; + stm32_putreg(regval, STM32_ETH_DMABMR); + + /* Wait for software reset to complete. The SR bit is cleared automatically + * after the reset operation has completed in all core clock domains. + * Should take at most a few clock ticks of the 50 MHz domain. + */ + + retries = 10; + while (((stm32_getreg(STM32_ETH_DMABMR) & ETH_DMABMR_SR) != 0) && + retries > 0) + { + retries--; + up_udelay(1); + } + + if (retries == 0) + { + return -ETIMEDOUT; + } + + return 0; +} + +/**************************************************************************** + * Function: stm32_macconfig + * + * Description: + * Configure the Ethernet MAC for DMA operation. + * + * Input Parameters: + * priv - A reference to the private driver state structure + * + * Returned Value: + * OK on success; Negated errno on failure. + * + * Assumptions: + * + ****************************************************************************/ + +static int stm32_macconfig(struct stm32_ethmac_s *priv) +{ + uint32_t regval; + + /* Set up the MACCR register */ + + regval = stm32_getreg(STM32_ETH_MACCR); + regval &= ~MACCR_CLEAR_BITS; + regval |= MACCR_SET_BITS; + + if (priv->fduplex) + { + /* Set the DM bit for full duplex support */ + + regval |= ETH_MACCR_DM; + } + + if (priv->mbps100) + { + /* Set the FES bit for 100Mbps fast ethernet support */ + + regval |= ETH_MACCR_FES; + } + + stm32_putreg(regval, STM32_ETH_MACCR); + + /* Set up the MACFFR register */ + + regval = stm32_getreg(STM32_ETH_MACFFR); + regval &= ~MACFFR_CLEAR_BITS; + regval |= MACFFR_SET_BITS; + stm32_putreg(regval, STM32_ETH_MACFFR); + + /* Set up the MACHTHR and MACHTLR registers */ + + stm32_putreg(0, STM32_ETH_MACHTHR); + stm32_putreg(0, STM32_ETH_MACHTLR); + + /* Setup up the MACFCR register */ + + regval = stm32_getreg(STM32_ETH_MACFCR); + regval &= ~MACFCR_CLEAR_MASK; + regval |= MACFCR_SET_MASK; + stm32_putreg(regval, STM32_ETH_MACFCR); + + /* Setup up the MACVLANTR register */ + + stm32_putreg(0, STM32_ETH_MACVLANTR); + + /* DMA Configuration */ + + /* Set up the DMAOMR register */ + + regval = stm32_getreg(STM32_ETH_DMAOMR); + regval &= ~DMAOMR_CLEAR_MASK; + regval |= DMAOMR_SET_MASK; + stm32_putreg(regval, STM32_ETH_DMAOMR); + + /* Set up the DMABMR register */ + + regval = stm32_getreg(STM32_ETH_DMABMR); + regval &= ~DMABMR_CLEAR_MASK; + regval |= DMABMR_SET_MASK; + stm32_putreg(regval, STM32_ETH_DMABMR); + + return OK; +} + +/**************************************************************************** + * Function: stm32_macaddress + * + * Description: + * Configure the selected MAC address. + * + * Input Parameters: + * priv - A reference to the private driver state structure + * + * Returned Value: + * OK on success; Negated errno on failure. + * + * Assumptions: + * + ****************************************************************************/ + +static void stm32_macaddress(struct stm32_ethmac_s *priv) +{ + struct net_driver_s *dev = &priv->dev; + uint32_t regval; + + ninfo("%s MAC: %02x:%02x:%02x:%02x:%02x:%02x\n", + dev->d_ifname, + dev->d_mac.ether.ether_addr_octet[0], + dev->d_mac.ether.ether_addr_octet[1], + dev->d_mac.ether.ether_addr_octet[2], + dev->d_mac.ether.ether_addr_octet[3], + dev->d_mac.ether.ether_addr_octet[4], + dev->d_mac.ether.ether_addr_octet[5]); + + /* Set the MAC address high register */ + + regval = ((uint32_t)dev->d_mac.ether.ether_addr_octet[5] << 8) | + (uint32_t)dev->d_mac.ether.ether_addr_octet[4]; + stm32_putreg(regval, STM32_ETH_MACA0HR); + + /* Set the MAC address low register */ + + regval = ((uint32_t)dev->d_mac.ether.ether_addr_octet[3] << 24) | + ((uint32_t)dev->d_mac.ether.ether_addr_octet[2] << 16) | + ((uint32_t)dev->d_mac.ether.ether_addr_octet[1] << 8) | + (uint32_t)dev->d_mac.ether.ether_addr_octet[0]; + stm32_putreg(regval, STM32_ETH_MACA0LR); +} + +/**************************************************************************** + * Function: stm32_macenable + * + * Description: + * Enable normal MAC operation. + * + * Input Parameters: + * priv - A reference to the private driver state structure + * + * Returned Value: + * OK on success; Negated errno on failure. + * + * Assumptions: + * + ****************************************************************************/ + +static int stm32_macenable(struct stm32_ethmac_s *priv) +{ + uint32_t regval; + + /* Set the MAC address */ + + stm32_macaddress(priv); + + /* Enable transmit state machine of the MAC for transmission on the MII */ + + regval = stm32_getreg(STM32_ETH_MACCR); + regval |= ETH_MACCR_TE; + stm32_putreg(regval, STM32_ETH_MACCR); + + /* Flush Transmit FIFO */ + + regval = stm32_getreg(STM32_ETH_DMAOMR); + regval |= ETH_DMAOMR_FTF; + stm32_putreg(regval, STM32_ETH_DMAOMR); + + /* Enable receive state machine of the MAC for reception from the MII */ + + /* Enables or disables the MAC reception. */ + + regval = stm32_getreg(STM32_ETH_MACCR); + regval |= ETH_MACCR_RE; + stm32_putreg(regval, STM32_ETH_MACCR); + + /* Start DMA transmission */ + + regval = stm32_getreg(STM32_ETH_DMAOMR); + regval |= ETH_DMAOMR_ST; + stm32_putreg(regval, STM32_ETH_DMAOMR); + + /* Start DMA reception */ + + regval = stm32_getreg(STM32_ETH_DMAOMR); + regval |= ETH_DMAOMR_SR; + stm32_putreg(regval, STM32_ETH_DMAOMR); + + /* Enable Ethernet DMA interrupts. + * + * The STM32 hardware supports two interrupts: (1) one dedicated to normal + * Ethernet operations and the other, used only for the Ethernet wakeup + * event. The wake-up interrupt is not used by this driver. + * + * The first Ethernet vector is reserved for interrupts generated by the + * MAC and the DMA. The MAC provides PMT and time stamp trigger interrupts, + * neither of which are used by this driver. + */ + + stm32_putreg(ETH_MACIMR_ALLINTS, STM32_ETH_MACIMR); + + /* Ethernet DMA supports two classes of interrupts: Normal interrupt + * summary (NIS) and Abnormal interrupt summary (AIS) with a variety + * individual normal and abnormal interrupting events. Here only + * the normal receive event is enabled (unless DEBUG is enabled). Transmit + * events will only be enabled when a transmit interrupt is expected. + */ + + stm32_putreg(ETH_DMAINT_RECV_ENABLE | ETH_DMAINT_ERROR_ENABLE, + STM32_ETH_DMAIER); + return OK; +} + +/**************************************************************************** + * Function: stm32_ethconfig + * + * Description: + * Configure the Ethernet interface for DMA operation. + * + * Input Parameters: + * priv - A reference to the private driver state structure + * + * Returned Value: + * OK on success; Negated errno on failure. + * + * Assumptions: + * + ****************************************************************************/ + +static int stm32_ethconfig(struct stm32_ethmac_s *priv) +{ + int ret; + + /* NOTE: The Ethernet clocks were initialized early in the boot-up + * sequence in stm32_rcc.c. + */ + + /* Reset the Ethernet block */ + + ninfo("Reset the Ethernet block\n"); + ret = stm32_ethreset(priv); + if (ret < 0) + { + nerr("ERROR: Reset of Ethernet block failed\n"); + return ret; + } + + /* Initialize the PHY */ + + ninfo("Initialize the PHY\n"); + ret = stm32_phyinit(priv); + if (ret < 0) + { + return ret; + } + + /* Initialize the MAC and DMA */ + + ninfo("Initialize the MAC and DMA\n"); + ret = stm32_macconfig(priv); + if (ret < 0) + { + return ret; + } + + /* Initialize the free buffer list */ + + stm32_initbuffer(priv, g_alloc); + + /* Initialize TX Descriptors list: Chain Mode */ + + stm32_txdescinit(priv, g_txtable); + + /* Initialize RX Descriptors list: Chain Mode */ + + stm32_rxdescinit(priv, g_rxtable, g_rxbuffer); + + /* Enable normal MAC operation */ + + ninfo("Enable normal operation\n"); + return stm32_macenable(priv); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Function: stm32_ethinitialize + * + * Description: + * Initialize the Ethernet driver for one interface. If the STM32 chip + * supports multiple Ethernet controllers, then board specific logic + * must implement arm_netinitialize() and call this function to initialize + * the desired interfaces. + * + * Input Parameters: + * intf - In the case where there are multiple EMACs, this value + * identifies which EMAC is to be initialized. + * + * Returned Value: + * OK on success; Negated errno on failure. + * + * Assumptions: + * + ****************************************************************************/ + +#if STM32_NETHERNET == 1 || defined(CONFIG_NETDEV_LATEINIT) +static inline +#endif +int stm32_ethinitialize(int intf) +{ + struct stm32_ethmac_s *priv; + int ret; + + ninfo("intf: %d\n", intf); + + /* Get the interface structure associated with this interface number. */ + + DEBUGASSERT(intf < STM32_NETHERNET); + priv = &g_stm32ethmac[intf]; + + /* Initialize the driver structure */ + + memset(priv, 0, sizeof(struct stm32_ethmac_s)); + priv->dev.d_ifup = stm32_ifup; /* I/F up (new IP address) callback */ + priv->dev.d_ifdown = stm32_ifdown; /* I/F down callback */ + priv->dev.d_txavail = stm32_txavail; /* New TX data callback */ +#ifdef CONFIG_NET_MCASTGROUP + priv->dev.d_addmac = stm32_addmac; /* Add multicast MAC address */ + priv->dev.d_rmmac = stm32_rmmac; /* Remove multicast MAC address */ +#endif +#ifdef CONFIG_NETDEV_IOCTL + priv->dev.d_ioctl = stm32_ioctl; /* Support PHY ioctl() calls */ +#endif + priv->dev.d_private = g_stm32ethmac; /* Used to recover private state from dev */ + + /* Configure GPIO pins to support Ethernet */ + + stm32_ethgpioconfig(priv); + + /* Attach the IRQ to the driver */ + + if (irq_attach(STM32_IRQ_ETH, stm32_interrupt, NULL)) + { + /* We could not attach the ISR to the interrupt */ + + return -EAGAIN; + } + + /* Put the interface in the down state. */ + + ret = stm32_ifdown(&priv->dev); + if (ret < 0) + { + nerr("ERROR: Initialization of Ethernet block failed: %d\n", ret); + return ret; + } + + /* Register the device with the OS so that socket IOCTLs can be performed */ + + netdev_register(&priv->dev, NET_LL_ETHERNET); + return OK; +} + +/**************************************************************************** + * Function: arm_netinitialize + * + * Description: + * This is the "standard" network initialization logic called from the + * low-level initialization logic in arm_initialize.c. If STM32_NETHERNET + * greater than one, then board specific logic will have to supply a + * version of arm_netinitialize() that calls stm32_ethinitialize() with + * the appropriate interface number. + * + * Input Parameters: + * None. + * + * Returned Value: + * None. + * + * Assumptions: + * + ****************************************************************************/ + +#if STM32_NETHERNET == 1 && !defined(CONFIG_NETDEV_LATEINIT) +void arm_netinitialize(void) +{ + stm32_ethinitialize(0); +} +#endif + +#ifdef CONFIG_STM32_ETH_PTP_RTC_HIRES + +/**************************************************************************** + * Name: up_rtc_initialize + * + * Description: + * Initialize the builtin, MCU hardware RTC per the selected + * configuration. This function is called once very early in the OS + * initialization sequence. + * + * NOTE that initialization of external RTC hardware that depends on the + * availability of OS resources (such as SPI or I2C) must be deferred + * until the system has fully booted. Other, RTC-specific initialization + * functions are used in that case. + * + * Input Parameters: + * None + * + * Returned Value: + * Zero (OK) on success; a negated errno on failure + * + ****************************************************************************/ + +int up_rtc_initialize(void) +{ + /* Nothing to do, the PTP RTC is not available until Ethernet peripheral + * is enabled. + */ + + return OK; +} + +/**************************************************************************** + * Name: up_rtc_gettime + * + * Description: + * Get the current time from the high resolution RTC clock/counter. This + * interface is only supported by the high-resolution RTC/counter hardware + * implementation. + * It is used to replace the system timer. + * + * Input Parameters: + * tp - The location to return the high resolution time value. + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +int up_rtc_gettime(struct timespec *tp) +{ + irqstate_t flags; + uint64_t timestamp; + + flags = spin_lock_irqsave(&g_rtc_lock); + timestamp = stm32_eth_ptp_gettime(); + + if (timestamp == 0) + { + /* PTP timer is not initialized yet. + * Normally we shouldn't end up here because g_rtc_enabled is false. + */ + + spin_unlock_irqrestore(&g_rtc_lock, flags); + DEBUGASSERT(!g_rtc_enabled); + return -EBUSY; + } + + ptp_to_timespec(timestamp, tp); + clock_timespec_add(tp, &g_stm32_eth_ptp_basetime, tp); + spin_unlock_irqrestore(&g_rtc_lock, flags); + + return OK; +} + +/**************************************************************************** + * Name: up_rtc_settime + * + * Description: + * Set the RTC to the provided time. All RTC implementations must be able + * to set their time based on a standard timespec. + * + * Input Parameters: + * tp - the time to use + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +int up_rtc_settime(const struct timespec *tp) +{ + struct timespec ptptime; + uint64_t timestamp; + irqstate_t flags; + + flags = spin_lock_irqsave(&g_rtc_lock); + timestamp = stm32_eth_ptp_gettime(); + + if (timestamp == 0) + { + /* PTP timer is not initialized yet. + * Normally we shouldn't end up here because g_rtc_enabled is false. + */ + + spin_unlock_irqrestore(&g_rtc_lock, flags); + DEBUGASSERT(!g_rtc_enabled); + return -EBUSY; + } + + /* Compute new basetime to get from PTP timestamp to wall clock time. + * We keep the PTP timer 0-based to avoid 32-bit seconds count + * overflow issues. + */ + + ptp_to_timespec(timestamp, &ptptime); + clock_timespec_subtract(tp, &ptptime, &g_stm32_eth_ptp_basetime); + spin_unlock_irqrestore(&g_rtc_lock, flags); + + return OK; +} + +/**************************************************************************** + * Name: up_rtc_adjtime + * + * Description: + * Adjust RTC frequency (running rate). Used by adjtime() when RTC is used + * as system time source. + * + * Input Parameters: + * ppb - Adjustment in parts per billion (nanoseconds per second). + * Zero is default rate, positive value makes clock run faster + * and negative value slower. + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + * Assumptions: + * Called from within a critical section. + * + ****************************************************************************/ + +int up_rtc_adjtime(long ppb) +{ + return stm32_eth_ptp_adjust(ppb); +} + +#endif /* CONFIG_STM32_ETH_PTP_RTC_HIRES */ + +#endif /* STM32_NETHERNET > 0 */ +#endif /* CONFIG_NET && CONFIG_STM32_ETHMAC */ diff --git a/arch/arm/src/common/stm32/stm32_eth_m3m4_v1.h b/arch/arm/src/common/stm32/stm32_eth_m3m4_v1.h new file mode 100644 index 0000000000000..e2cfbdefe70cd --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_eth_m3m4_v1.h @@ -0,0 +1,109 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_eth_m3m4_v1.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_ETH_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_ETH_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "chip.h" + +#if STM32_NETHERNET > 0 + +#include "hardware/stm32_eth.h" + +#ifndef __ASSEMBLY__ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Function: stm32_ethinitialize + * + * Description: + * Initialize the Ethernet driver for one interface. If the STM32 chip + * supports multiple Ethernet controllers, then board specific logic must + * implement arm_netinitialize() and call this function to initialize the + * desired interfaces. + * + * Input Parameters: + * intf - In the case where there are multiple EMACs, this value + * identifies which EMAC is to be initialized. + * + * Returned Value: + * OK on success; Negated errno on failure. + * + * Assumptions: + * + ****************************************************************************/ + +#if STM32_NETHERNET > 1 || defined(CONFIG_NETDEV_LATEINIT) +int stm32_ethinitialize(int intf); +#endif + +/**************************************************************************** + * Function: stm32_phy_boardinitialize + * + * Description: + * Some boards require specialized initialization of the PHY before it can + * be used. This may include such things as configuring GPIOs, resetting + * the PHY, etc. If CONFIG_STM32_PHYINIT is defined in the configuration + * then the board specific logic must provide stm32_phyinitialize(); The + * STM32 Ethernet driver will call this function one time before it first + * uses the PHY. + * + * Input Parameters: + * intf - Always zero for now. + * + * Returned Value: + * OK on success; Negated errno on failure. + * + * Assumptions: + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_PHYINIT +int stm32_phy_boardinitialize(int intf); +#endif + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* STM32_NETHERNET > 0 */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_ETH_H */ diff --git a/arch/arm/src/common/stm32/stm32_exti.h b/arch/arm/src/common/stm32/stm32_exti.h new file mode 100644 index 0000000000000..8e301cf999700 --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_exti.h @@ -0,0 +1,134 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_exti.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_COMPAT_STM32_EXTI_H +#define __ARCH_ARM_SRC_COMMON_COMPAT_STM32_EXTI_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include +#include + +#include "chip.h" +#include "hardware/stm32_exti.h" + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_gpiosetevent + * + * Description: + * Sets/clears GPIO based event and interrupt triggers. + * + * Input Parameters: + * - pinset: gpio pin configuration + * - rising/falling edge: enables + * - event: generate event when set + * - func: when non-NULL, generate interrupt + * - arg: Argument passed to the interrupt callback + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure indicating the + * nature of the failure. + * + ****************************************************************************/ + +int stm32_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, + bool event, xcpt_t func, void *arg); + +/**************************************************************************** + * Name: stm32_exti_alarm + * + * Description: + * Sets/clears EXTI alarm interrupt. + * + * Input Parameters: + * - rising/falling edge: enables interrupt on rising/falling edges + * - event: generate event when set + * - func: when non-NULL, generate interrupt + * - arg: Argument passed to the interrupt callback + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure indicating the + * nature of the failure. + * + ****************************************************************************/ + +#ifdef CONFIG_RTC_ALARM +int stm32_exti_alarm(bool risingedge, bool fallingedge, bool event, + xcpt_t func, void *arg); +#endif + +/**************************************************************************** + * Name: stm32_exti_wakeup + * + * Description: + * Sets/clears EXTI wakeup interrupt. + * + * Input Parameters: + * - rising/falling edge: enables interrupt on rising/falling edges + * - event: generate event when set + * - func: when non-NULL, generate interrupt + * - arg: Argument passed to the interrupt callback + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure indicating the + * nature of the failure. + * + ****************************************************************************/ + +#ifdef CONFIG_RTC_PERIODIC +int stm32_exti_wakeup(bool risingedge, bool fallingedge, bool event, + xcpt_t func, void *arg); +#endif + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ + +#endif /* __ARCH_ARM_SRC_COMMON_COMPAT_STM32_EXTI_H */ diff --git a/arch/arm/src/common/stm32/stm32_exti_alarm_m3m4_v1.c b/arch/arm/src/common/stm32/stm32_exti_alarm_m3m4_v1.c new file mode 100644 index 0000000000000..e7b7d07cf8117 --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_exti_alarm_m3m4_v1.c @@ -0,0 +1,140 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_exti_alarm_m3m4_v1.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include + +#include +#include +#include + +#include + +#include "arm_internal.h" +#include "chip.h" +#include "stm32_gpio.h" +#include "stm32_exti.h" + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* Interrupt handlers attached to the ALARM EXTI */ + +static xcpt_t g_alarm_callback; +static void *g_callback_arg; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_exti_alarm_isr + * + * Description: + * EXTI ALARM interrupt service routine/dispatcher + * + ****************************************************************************/ + +static int stm32_exti_alarm_isr(int irq, void *context, void *arg) +{ + int ret = OK; + + /* Clear the pending EXTI interrupt */ + + putreg32(EXTI_RTC_ALARM, STM32_EXTI_PR); + + /* And dispatch the interrupt to the handler */ + + if (g_alarm_callback) + { + ret = g_alarm_callback(irq, context, g_callback_arg); + } + + return ret; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_exti_alarm + * + * Description: + * Sets/clears EXTI alarm interrupt. + * + * Input Parameters: + * - rising/falling edge: enables interrupt on rising/falling edge + * - event: generate event when set + * - func: when non-NULL, generate interrupt + * - arg: Argument passed to the interrupt callback + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure indicating the + * nature of the failure. + * + ****************************************************************************/ + +int stm32_exti_alarm(bool risingedge, bool fallingedge, bool event, + xcpt_t func, void *arg) +{ + g_alarm_callback = func; + g_callback_arg = arg; + + /* Install external interrupt handlers (if not already attached) */ + + if (func) + { + irq_attach(STM32_IRQ_RTCALRM, stm32_exti_alarm_isr, NULL); + up_enable_irq(STM32_IRQ_RTCALRM); + } + else + { + up_disable_irq(STM32_IRQ_RTCALRM); + } + + /* Configure rising/falling edges */ + + modifyreg32(STM32_EXTI_RTSR, + risingedge ? 0 : EXTI_RTC_ALARM, + risingedge ? EXTI_RTC_ALARM : 0); + modifyreg32(STM32_EXTI_FTSR, + fallingedge ? 0 : EXTI_RTC_ALARM, + fallingedge ? EXTI_RTC_ALARM : 0); + + /* Enable Events and Interrupts */ + + modifyreg32(STM32_EXTI_EMR, + event ? 0 : EXTI_RTC_ALARM, + event ? EXTI_RTC_ALARM : 0); + modifyreg32(STM32_EXTI_IMR, + func ? 0 : EXTI_RTC_ALARM, + func ? EXTI_RTC_ALARM : 0); + + return OK; +} diff --git a/arch/arm/src/common/stm32/stm32_exti_gpio_m0_v1.c b/arch/arm/src/common/stm32/stm32_exti_gpio_m0_v1.c new file mode 100644 index 0000000000000..00b9158085c57 --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_exti_gpio_m0_v1.c @@ -0,0 +1,311 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_exti_gpio_m0_v1.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include + +#include +#include +#include +#include + +#include + +#include "arm_internal.h" +#include "chip.h" +#include "stm32_gpio.h" +#include "stm32_exti.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#if defined(CONFIG_STM32_HAVE_IP_EXTI_V2) +# define STM32_EXTI_FTSR STM32_EXTI_FTSR1 +# define STM32_EXTI_RTSR STM32_EXTI_RTSR1 +# define STM32_EXTI_IMR STM32_EXTI_IMR1 +# define STM32_EXTI_EMR STM32_EXTI_EMR1 +#endif + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +struct gpio_callback_s +{ + xcpt_t callback; + void *arg; +}; + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* Interrupt handlers attached to each EXTI */ + +static struct gpio_callback_s g_gpio_callbacks[16]; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Interrupt Service Routines - Dispatchers + ****************************************************************************/ + +#if defined(CONFIG_STM32_HAVE_IP_EXTI_V1) +static int stm32_exti_multiisr(int irq, void *context, void *arg, + int first, int last) +{ + uint32_t pr; + int pin; + int ret = OK; + + /* Examine the state of each pin in the group */ + + pr = getreg32(STM32_EXTI_PR); + + /* And dispatch the interrupt to the handler */ + + for (pin = first; pin <= last; pin++) + { + /* Is an interrupt pending on this pin? */ + + uint32_t mask = (1 << pin); + if ((pr & mask) != 0) + { + /* Clear the pending interrupt */ + + putreg32(mask, STM32_EXTI_PR); + + /* And dispatch the interrupt to the handler */ + + if (g_gpio_callbacks[pin].callback != NULL) + { + xcpt_t callback = g_gpio_callbacks[pin].callback; + void *cbarg = g_gpio_callbacks[pin].arg; + int tmp; + + tmp = callback(irq, context, cbarg); + if (tmp < 0) + { + ret = tmp; + } + } + } + } + + return ret; +} +#elif defined(CONFIG_STM32_HAVE_IP_EXTI_V2) +static int stm32_exti_multiisr(int irq, void *context, void *arg, + int first, int last) +{ + uint32_t rpr; + uint32_t fpr; + int pin; + int ret = OK; + + /* Examine the state of each pin in the group. + * NOTE: We don't distinguish rising/falling edge! + */ + + rpr = getreg32(STM32_EXTI_RPR1); + fpr = getreg32(STM32_EXTI_FPR1); + + /* And dispatch the interrupt to the handler */ + + for (pin = first; pin <= last; pin++) + { + /* Is an interrupt pending on this pin? */ + + uint32_t mask = (1 << pin); + if (((rpr & mask) != 0) || ((fpr & mask) != 0)) + { + /* Clear the pending interrupt */ + + putreg32(mask, STM32_EXTI_RPR1); + putreg32(mask, STM32_EXTI_FPR1); + + /* And dispatch the interrupt to the handler */ + + if (g_gpio_callbacks[pin].callback != NULL) + { + xcpt_t callback = g_gpio_callbacks[pin].callback; + void *cbarg = g_gpio_callbacks[pin].arg; + int tmp; + + tmp = callback(irq, context, cbarg); + if (tmp < 0) + { + ret = tmp; + } + } + } + } + + return ret; +} +#endif + +static int stm32_exti01_isr(int irq, void *context, void *arg) +{ + return stm32_exti_multiisr(irq, context, arg, 0, 1); +} + +static int stm32_exti23_isr(int irq, void *context, void *arg) +{ + return stm32_exti_multiisr(irq, context, arg, 2, 3); +} + +static int stm32_exti415_isr(int irq, void *context, void *arg) +{ + return stm32_exti_multiisr(irq, context, arg, 4, 15); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_gpiosetevent + * + * Description: + * Sets/clears GPIO based event and interrupt triggers. + * + * Input Parameters: + * - pinset: GPIO pin configuration + * - risingedge: Enables interrupt on rising edges + * - fallingedge: Enables interrupt on falling edges + * - event: Generate event when set + * - func: When non-NULL, generate interrupt + * - arg: Argument passed to the interrupt callback + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure indicating the + * nature of the failure. + * + ****************************************************************************/ + +int stm32_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, + bool event, xcpt_t func, void *arg) +{ + struct gpio_callback_s *shared_cbs; + uint32_t pin = pinset & GPIO_PIN_MASK; + uint32_t exti = STM32_EXTI_BIT(pin); + int irq; + xcpt_t handler; + int nshared; + int i; + + /* Select the interrupt handler for this EXTI pin */ + + if (pin < 2) + { + irq = STM32_IRQ_EXTI0_1; + handler = stm32_exti01_isr; + shared_cbs = &g_gpio_callbacks[0]; + nshared = 2; + } + else if (pin < 4) + { + irq = STM32_IRQ_EXTI2_3; + handler = stm32_exti23_isr; + shared_cbs = &g_gpio_callbacks[2]; + nshared = 2; + } + else + { + irq = STM32_IRQ_EXTI4_15; + handler = stm32_exti415_isr; + shared_cbs = &g_gpio_callbacks[4]; + nshared = 12; + } + + /* Get the previous GPIO IRQ handler; Save the new IRQ handler. */ + + g_gpio_callbacks[pin].callback = func; + g_gpio_callbacks[pin].arg = arg; + + /* Install external interrupt handlers */ + + if (func) + { + irq_attach(irq, handler, NULL); + up_enable_irq(irq); + } + else + { + /* Only disable IRQ if shared handler does not have any active + * callbacks. + */ + + for (i = 0; i < nshared; i++) + { + if (shared_cbs[i].callback != NULL) + { + break; + } + } + + if (i == nshared) + { + up_disable_irq(irq); + } + } + + /* Configure GPIO, enable EXTI line enabled if event or interrupt is + * enabled. + */ + + if (event || func) + { + pinset |= GPIO_EXTI; + } + + stm32_configgpio(pinset); + + /* Configure rising/falling edges */ + + modifyreg32(STM32_EXTI_RTSR, + risingedge ? 0 : exti, + risingedge ? exti : 0); + modifyreg32(STM32_EXTI_FTSR, + fallingedge ? 0 : exti, + fallingedge ? exti : 0); + + /* Enable Events and Interrupts */ + + modifyreg32(STM32_EXTI_EMR, + event ? 0 : exti, + event ? exti : 0); + modifyreg32(STM32_EXTI_IMR, + func ? 0 : exti, + func ? exti : 0); + + return OK; +} diff --git a/arch/arm/src/common/stm32/stm32_exti_gpio_m3m4_v1v2.c b/arch/arm/src/common/stm32/stm32_exti_gpio_m3m4_v1v2.c new file mode 100644 index 0000000000000..db62fac13f669 --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_exti_gpio_m3m4_v1v2.c @@ -0,0 +1,370 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_exti_gpio_m3m4_v1v2.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include + +#include +#include +#include +#include + +#include + +#include "arm_internal.h" +#include "chip.h" +#include "stm32_gpio.h" +#include "stm32_exti.h" + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +struct gpio_callback_s +{ + xcpt_t callback; + void *arg; +}; + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* Interrupt handlers attached to each EXTI */ + +static struct gpio_callback_s g_gpio_callbacks[16]; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Interrupt Service Routines - Dispatchers + ****************************************************************************/ + +static int stm32_exti0_isr(int irq, void *context, void *arg) +{ + int ret = OK; + + /* Clear the pending interrupt */ + + putreg32(0x0001, STM32_EXTI_PR); + + /* And dispatch the interrupt to the handler */ + + if (g_gpio_callbacks[0].callback != NULL) + { + xcpt_t callback = g_gpio_callbacks[0].callback; + void *cbarg = g_gpio_callbacks[0].arg; + + ret = callback(irq, context, cbarg); + } + + return ret; +} + +static int stm32_exti1_isr(int irq, void *context, void *arg) +{ + int ret = OK; + + /* Clear the pending interrupt */ + + putreg32(0x0002, STM32_EXTI_PR); + + /* And dispatch the interrupt to the handler */ + + if (g_gpio_callbacks[1].callback != NULL) + { + xcpt_t callback = g_gpio_callbacks[1].callback; + void *cbarg = g_gpio_callbacks[1].arg; + + ret = callback(irq, context, cbarg); + } + + return ret; +} + +static int stm32_exti2_isr(int irq, void *context, void *arg) +{ + int ret = OK; + + /* Clear the pending interrupt */ + + putreg32(0x0004, STM32_EXTI_PR); + + /* And dispatch the interrupt to the handler */ + + if (g_gpio_callbacks[2].callback != NULL) + { + xcpt_t callback = g_gpio_callbacks[2].callback; + void *cbarg = g_gpio_callbacks[2].arg; + + ret = callback(irq, context, cbarg); + } + + return ret; +} + +static int stm32_exti3_isr(int irq, void *context, void * arg) +{ + int ret = OK; + + /* Clear the pending interrupt */ + + putreg32(0x0008, STM32_EXTI_PR); + + /* And dispatch the interrupt to the handler */ + + if (g_gpio_callbacks[3].callback != NULL) + { + xcpt_t callback = g_gpio_callbacks[3].callback; + void *cbarg = g_gpio_callbacks[3].arg; + + ret = callback(irq, context, cbarg); + } + + return ret; +} + +static int stm32_exti4_isr(int irq, void *context, void *arg) +{ + int ret = OK; + + /* Clear the pending interrupt */ + + putreg32(0x0010, STM32_EXTI_PR); + + /* And dispatch the interrupt to the handler */ + + if (g_gpio_callbacks[4].callback != NULL) + { + xcpt_t callback = g_gpio_callbacks[4].callback; + void *cbarg = g_gpio_callbacks[4].arg; + + ret = callback(irq, context, cbarg); + } + + return ret; +} + +static int stm32_exti_multiisr(int irq, void *context, void *arg, + int first, int last) +{ + uint32_t pr; + int pin; + int ret = OK; + + /* Examine the state of each pin in the group */ + + pr = getreg32(STM32_EXTI_PR); + + /* And dispatch the interrupt to the handler */ + + for (pin = first; pin <= last; pin++) + { + /* Is an interrupt pending on this pin? */ + + uint32_t mask = (1 << pin); + if ((pr & mask) != 0) + { + /* Clear the pending interrupt */ + + putreg32(mask, STM32_EXTI_PR); + + /* And dispatch the interrupt to the handler */ + + if (g_gpio_callbacks[pin].callback != NULL) + { + xcpt_t callback = g_gpio_callbacks[pin].callback; + void *cbarg = g_gpio_callbacks[pin].arg; + int tmp; + + tmp = callback(irq, context, cbarg); + if (tmp < 0) + { + ret = tmp; + } + } + } + } + + return ret; +} + +static int stm32_exti95_isr(int irq, void *context, void *arg) +{ + return stm32_exti_multiisr(irq, context, arg, 5, 9); +} + +static int stm32_exti1510_isr(int irq, void *context, void *arg) +{ + return stm32_exti_multiisr(irq, context, arg, 10, 15); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_gpiosetevent + * + * Description: + * Sets/clears GPIO based event and interrupt triggers. + * + * Input Parameters: + * - pinset: GPIO pin configuration + * - risingedge: Enables interrupt on rising edges + * - fallingedge: Enables interrupt on falling edges + * - event: Generate event when set + * - func: When non-NULL, generate interrupt + * - arg: Argument passed to the interrupt callback + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure indicating the + * nature of the failure. + * + ****************************************************************************/ + +int stm32_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, + bool event, xcpt_t func, void *arg) +{ + struct gpio_callback_s *shared_cbs; + uint32_t pin = pinset & GPIO_PIN_MASK; + uint32_t exti = STM32_EXTI_BIT(pin); + int irq; + xcpt_t handler; + int nshared; + int i; + + /* Select the interrupt handler for this EXTI pin */ + + if (pin < 5) + { + irq = pin + STM32_IRQ_EXTI0; + nshared = 1; + shared_cbs = &g_gpio_callbacks[pin]; + switch (pin) + { + case 0: + handler = stm32_exti0_isr; + break; + + case 1: + handler = stm32_exti1_isr; + break; + + case 2: + handler = stm32_exti2_isr; + break; + + case 3: + handler = stm32_exti3_isr; + break; + + default: + handler = stm32_exti4_isr; + break; + } + } + else if (pin < 10) + { + irq = STM32_IRQ_EXTI95; + handler = stm32_exti95_isr; + shared_cbs = &g_gpio_callbacks[5]; + nshared = 5; + } + else + { + irq = STM32_IRQ_EXTI1510; + handler = stm32_exti1510_isr; + shared_cbs = &g_gpio_callbacks[10]; + nshared = 6; + } + + /* Get the previous GPIO IRQ handler; Save the new IRQ handler. */ + + g_gpio_callbacks[pin].callback = func; + g_gpio_callbacks[pin].arg = arg; + + /* Install external interrupt handlers */ + + if (func) + { + irq_attach(irq, handler, NULL); + up_enable_irq(irq); + } + else + { + /* Only disable IRQ if shared handler does not have any active + * callbacks. + */ + + for (i = 0; i < nshared; i++) + { + if (shared_cbs[i].callback != NULL) + { + break; + } + } + + if (i == nshared) + { + up_disable_irq(irq); + } + } + + /* Configure GPIO, enable EXTI line enabled if event or interrupt is + * enabled. + */ + + if (event || func) + { + pinset |= GPIO_EXTI; + } + + stm32_configgpio(pinset); + + /* Configure rising/falling edges */ + + modifyreg32(STM32_EXTI_RTSR, + risingedge ? 0 : exti, + risingedge ? exti : 0); + modifyreg32(STM32_EXTI_FTSR, + fallingedge ? 0 : exti, + fallingedge ? exti : 0); + + /* Enable Events and Interrupts */ + + modifyreg32(STM32_EXTI_EMR, + event ? 0 : exti, + event ? exti : 0); + modifyreg32(STM32_EXTI_IMR, + func ? 0 : exti, + func ? exti : 0); + + return OK; +} diff --git a/arch/arm/src/common/stm32/stm32_exti_pwr.h b/arch/arm/src/common/stm32/stm32_exti_pwr.h new file mode 100644 index 0000000000000..f99225e585032 --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_exti_pwr.h @@ -0,0 +1,38 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_exti_pwr.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_COMPAT_STM32EXTIPWR_H +#define __ARCH_ARM_SRC_COMMON_COMPAT_STM32EXTIPWR_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#if defined(CONFIG_STM32_COMMON_LEGACY) +# include "stm32_exti_pwr_m3m4_v1.h" +#else +# error "Unsupported STM32 stm32_exti_pwr" +#endif + +#endif /* __ARCH_ARM_SRC_COMMON_COMPAT_STM32EXTIPWR_H */ diff --git a/arch/arm/src/common/stm32/stm32_exti_pwr_m3m4_v1.c b/arch/arm/src/common/stm32/stm32_exti_pwr_m3m4_v1.c new file mode 100644 index 0000000000000..0b83b171c19ea --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_exti_pwr_m3m4_v1.c @@ -0,0 +1,149 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_exti_pwr_m3m4_v1.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include + +#include +#include +#include + +#include + +#include "arm_internal.h" +#include "chip.h" +#include "stm32_gpio.h" +#include "stm32_exti_pwr_m3m4_v1.h" +#include "stm32_exti.h" +#include "stm32_gpio.h" +#include "stm32_exti_pwr_m3m4_v1.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* Interrupt handlers attached to the PVD EXTI */ + +static xcpt_t g_pvd_callback; +static void *g_callback_arg; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_exti_pvd_isr + * + * Description: + * EXTI PVD interrupt service routine/dispatcher + * + ****************************************************************************/ + +static int stm32_exti_pvd_isr(int irq, void *context, void *arg) +{ + int ret = OK; + + /* Clear the pending EXTI interrupt */ + + putreg32(EXTI_PVD_LINE, STM32_EXTI_PR); + + /* And dispatch the interrupt to the handler */ + + if (g_pvd_callback != NULL) + { + ret = g_pvd_callback(irq, context, g_callback_arg); + } + + return ret; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_exti_pvd + * + * Description: + * Sets/clears EXTI PVD interrupt. + * + * Input Parameters: + * - rising/falling edge: enables interrupt on rising/falling edge + * - event: generate event when set + * - func: when non-NULL, generate interrupt + * - arg: Argument passed to the interrupt callback + * + * Returned Value: + * Zero (OK) returned on success; a negated errno value is returned on + * failure. + * + ****************************************************************************/ + +int stm32_exti_pvd(bool risingedge, bool fallingedge, bool event, + xcpt_t func, void *arg) +{ + /* Get the previous GPIO IRQ handler; Save the new IRQ handler. */ + + g_pvd_callback = func; + g_callback_arg = arg; + + /* Install external interrupt handlers (if not already attached) */ + + if (func) + { + irq_attach(STM32_IRQ_PVD, stm32_exti_pvd_isr, NULL); + up_enable_irq(STM32_IRQ_PVD); + } + else + { + up_disable_irq(STM32_IRQ_PVD); + } + + /* Configure rising/falling edges */ + + modifyreg32(STM32_EXTI_RTSR, + risingedge ? 0 : EXTI_PVD_LINE, + risingedge ? EXTI_PVD_LINE : 0); + modifyreg32(STM32_EXTI_FTSR, + fallingedge ? 0 : EXTI_PVD_LINE, + fallingedge ? EXTI_PVD_LINE : 0); + + /* Enable Events and Interrupts */ + + modifyreg32(STM32_EXTI_EMR, + event ? 0 : EXTI_PVD_LINE, + event ? EXTI_PVD_LINE : 0); + modifyreg32(STM32_EXTI_IMR, + func ? 0 : EXTI_PVD_LINE, + func ? EXTI_PVD_LINE : 0); + + return OK; +} diff --git a/arch/arm/src/common/stm32/stm32_exti_pwr_m3m4_v1.h b/arch/arm/src/common/stm32/stm32_exti_pwr_m3m4_v1.h new file mode 100644 index 0000000000000..41058ed24aab6 --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_exti_pwr_m3m4_v1.h @@ -0,0 +1,58 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_exti_pwr_m3m4_v1.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_EXTI_PWR_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_EXTI_PWR_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_exti_pvd + * + * Description: + * Sets/clears EXTI PVD interrupt. + * + * Input Parameters: + * - rising/falling edge: enables interrupt on rising/falling edge + * - event: generate event when set + * - func: when non-NULL, generate interrupt + * - arg: Argument passed to the interrupt callback + * + * Returned Value: + * Zero (OK) returned on success; a negated errno value is returned on + * failure. + * + ****************************************************************************/ + +int stm32_exti_pvd(bool risingedge, bool fallingedge, bool event, + xcpt_t func, void *arg); + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_EXTI_PWR_H */ diff --git a/arch/arm/src/common/stm32/stm32_exti_wakeup_m3m4_v1.c b/arch/arm/src/common/stm32/stm32_exti_wakeup_m3m4_v1.c new file mode 100644 index 0000000000000..f3baba30545f5 --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_exti_wakeup_m3m4_v1.c @@ -0,0 +1,139 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_exti_wakeup_m3m4_v1.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include + +#include +#include +#include + +#include + +#include "arm_internal.h" +#include "chip.h" +#include "stm32_gpio.h" +#include "stm32_exti.h" + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* Interrupt handlers attached to the RTC WAKEUP EXTI */ + +static xcpt_t g_wakeup_callback; +static void *g_callback_arg; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_exti_wakeup_isr + * + * Description: + * EXTI periodic WAKEUP interrupt service routine/dispatcher + * + ****************************************************************************/ + +static int stm32_exti_wakeup_isr(int irq, void *context, void *arg) +{ + int ret = OK; + + /* Dispatch the interrupt to the handler */ + + if (g_wakeup_callback != NULL) + { + ret = g_wakeup_callback(irq, context, g_callback_arg); + } + + /* Clear the pending EXTI interrupt */ + + putreg32(EXTI_RTC_WAKEUP, STM32_EXTI_PR); + + return ret; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_exti_wakeup + * + * Description: + * Sets/clears EXTI wakeup interrupt. + * + * Input Parameters: + * - rising/falling edge: enables interrupt on rising/falling edges + * - event: generate event when set + * - func: when non-NULL, generate interrupt + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure indicating the + * nature of the failure. + * + ****************************************************************************/ + +int stm32_exti_wakeup(bool risingedge, bool fallingedge, bool event, + xcpt_t func, void *arg) +{ + g_wakeup_callback = func; + g_callback_arg = arg; + + /* Install external interrupt handlers (if not already attached) */ + + if (func) + { + irq_attach(STM32_IRQ_RTC_WKUP, stm32_exti_wakeup_isr, NULL); + up_enable_irq(STM32_IRQ_RTC_WKUP); + } + else + { + up_disable_irq(STM32_IRQ_RTC_WKUP); + } + + /* Configure rising/falling edges */ + + modifyreg32(STM32_EXTI_RTSR, + risingedge ? 0 : EXTI_RTC_WAKEUP, + risingedge ? EXTI_RTC_WAKEUP : 0); + modifyreg32(STM32_EXTI_FTSR, + fallingedge ? 0 : EXTI_RTC_WAKEUP, + fallingedge ? EXTI_RTC_WAKEUP : 0); + + /* Enable Events and Interrupts */ + + modifyreg32(STM32_EXTI_EMR, + event ? 0 : EXTI_RTC_WAKEUP, + event ? EXTI_RTC_WAKEUP : 0); + modifyreg32(STM32_EXTI_IMR, + func ? 0 : EXTI_RTC_WAKEUP, + func ? EXTI_RTC_WAKEUP : 0); + + return OK; +} diff --git a/arch/arm/src/common/stm32/stm32_fdcan.h b/arch/arm/src/common/stm32/stm32_fdcan.h new file mode 100644 index 0000000000000..8a2dc52c68a33 --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_fdcan.h @@ -0,0 +1,80 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_fdcan.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_COMPAT_STM32_FDCAN_H +#define __ARCH_ARM_SRC_COMMON_COMPAT_STM32_FDCAN_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "chip.h" +#include "hardware/stm32_fdcan.h" + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Port numbers for use with stm32_fdcan_initialize() */ + +#define FDCAN1 1 + +#if defined(CONFIG_STM32_HAVE_IP_FDCAN_MCAN_M3M4_V1) +# define FDCAN2 2 +# define FDCAN3 3 +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +# define EXTERN extern "C" +extern "C" +{ +#else +# define EXTERN extern +#endif + +#ifdef CONFIG_STM32_FDCAN_CHARDRIVER +struct can_dev_s *stm32_fdcaninitialize(int port); +#endif + +#ifdef CONFIG_STM32_FDCAN_SOCKET +int stm32_fdcansockinitialize(int port); +#endif + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ + +#endif /* __ARCH_ARM_SRC_COMMON_COMPAT_STM32_FDCAN_H */ diff --git a/arch/arm/src/common/stm32/stm32_fdcan_m0_v1.c b/arch/arm/src/common/stm32/stm32_fdcan_m0_v1.c new file mode 100644 index 0000000000000..8c72dd6b209ac --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_fdcan_m0_v1.c @@ -0,0 +1,3224 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_fdcan_m0_v1.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + *s + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include "arm_internal.h" +#include "stm32_fdcan.h" +#include "hardware/stm32_pinmap.h" +#include "stm32_gpio.h" +#include "stm32_rcc.h" + +/* Ported from arch/arm/src/common/stm32/stm32_fdcan_m0_v1.c */ + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Clock source *************************************************************/ + +#define FDCANCLK_PDIV (0) + +#if FDCANCLK_PDIV == 0 +# define STM32_FDCANCLK_FREQUENCY (STM32_FDCAN_FREQUENCY / (1)) +#else +# define STM32_FDCANCLK_FREQUENCY (STM32_FDCAN_FREQUENCY / (2 * FDCANCLK_PDIV)) +#endif + +/* General Configuration ****************************************************/ + +#if defined(CONFIG_ARCH_CHIP_STM32C0) + +/* FDCAN Message RAM */ + +# define FDCAN_MSGRAM_WORDS (212) +# define STM32_CANRAM1_BASE (STM32_CANRAM_BASE + 0x0000) + +# ifdef CONFIG_STM32_FDCAN1 +# define FDCAN1_STDFILTER_SIZE (28) +# define FDCAN1_EXTFILTER_SIZE (8) +# define FDCAN1_RXFIFO0_SIZE (3) +# define FDCAN1_RXFIFO1_SIZE (3) +# define FDCAN1_TXEVENTFIFO_SIZE (3) +# define FDCAN1_TXFIFIOQ_SIZE (3) + +# define FDCAN1_STDFILTER_WORDS (28) +# define FDCAN1_EXTFILTER_WORDS (16) +# define FDCAN1_RXFIFO0_WORDS (54) +# define FDCAN1_RXFIFO1_WORDS (54) +# define FDCAN1_TXEVENTFIFO_WORDS (6) +# define FDCAN1_TXFIFIOQ_WORDS (54) +# endif +#else +# error +#endif + +/* FDCAN1 Configuration *****************************************************/ + +#ifdef CONFIG_STM32_FDCAN1 + +/* Bit timing */ + +# define FDCAN1_NTSEG1 (CONFIG_STM32_FDCAN1_NTSEG1 - 1) +# define FDCAN1_NTSEG2 (CONFIG_STM32_FDCAN1_NTSEG2 - 1) +# define FDCAN1_NBRP ((STM32_FDCANCLK_FREQUENCY / \ + ((FDCAN1_NTSEG1 + FDCAN1_NTSEG2 + 3) * \ + CONFIG_STM32_FDCAN1_BITRATE)) - 1) +# define FDCAN1_NSJW (CONFIG_STM32_FDCAN1_NSJW - 1) + +# if FDCAN1_NTSEG1 > FDCAN_NBTP_NTSEG1_MAX +# error Invalid FDCAN1 NTSEG1 +# endif +# if FDCAN1_NTSEG2 > FDCAN_NBTP_NTSEG2_MAX +# error Invalid FDCAN1 NTSEG2 +# endif +# if FDCAN1_NSJW > FDCAN_NBTP_NSJW_MAX +# error Invalid FDCAN1 NSJW +# endif +# if FDCAN1_NBRP > FDCAN_NBTP_NBRP_MAX +# error Invalid FDCAN1 NBRP +# endif + +# ifdef CONFIG_STM32_FDCAN1_FD_BRS +# define FDCAN1_DTSEG1 (CONFIG_STM32_FDCAN1_DTSEG1 - 1) +# define FDCAN1_DTSEG2 (CONFIG_STM32_FDCAN1_DTSEG2 - 1) +# define FDCAN1_DBRP ((STM32_FDCANCLK_FREQUENCY / \ + ((FDCAN1_DTSEG1 + FDCAN1_DTSEG2 + 3) * \ + CONFIG_STM32_FDCAN1_DBITRATE)) - 1) +# define FDCAN1_DSJW (CONFIG_STM32_FDCAN1_DSJW - 1) +# else +# define FDCAN1_DTSEG1 1 +# define FDCAN1_DTSEG2 1 +# define FDCAN1_DBRP 1 +# define FDCAN1_DSJW 1 +# endif /* CONFIG_STM32_FDCAN1_FD_BRS */ + +# if FDCAN1_DTSEG1 > FDCAN_DBTP_DTSEG1_MAX +# error Invalid FDCAN1 DTSEG1 +# endif +# if FDCAN1_DTSEG2 > FDCAN_DBTP_DTSEG2_MAX +# error Invalid FDCAN1 DTSEG2 +# endif +# if FDCAN1_DBRP > FDCAN_DBTP_DBRP_MAX +# error Invalid FDCAN1 DBRP +# endif +# if FDCAN1_DSJW > FDCAN_DBTP_DSJW_MAX +# error Invalid FDCAN1 DSJW +# endif + +/* FDCAN1 Message RAM Configuration *****************************************/ + +/* FDCAN1 Message RAM Layout */ + +# define FDCAN1_STDFILTER_INDEX 0 +# define FDCAN1_EXTFILTERS_INDEX (FDCAN1_STDFILTER_INDEX + FDCAN1_STDFILTER_WORDS) +# define FDCAN1_RXFIFO0_INDEX (FDCAN1_EXTFILTERS_INDEX + FDCAN1_EXTFILTER_WORDS) +# define FDCAN1_RXFIFO1_INDEX (FDCAN1_RXFIFO0_INDEX + FDCAN1_RXFIFO0_WORDS) +# define FDCAN1_TXEVENTFIFO_INDEX (FDCAN1_RXFIFO1_INDEX + FDCAN1_RXFIFO1_WORDS) +# define FDCAN1_TXFIFOQ_INDEX (FDCAN1_TXEVENTFIFO_INDEX + FDCAN1_TXEVENTFIFO_WORDS) +# define FDCAN1_MSGRAM_WORDS (FDCAN1_TXFIFOQ_INDEX + FDCAN1_TXFIFIOQ_WORDS) + +#endif /* CONFIG_STM32_FDCAN1 */ + +/* Loopback mode */ + +#undef STM32_FDCAN_LOOPBACK +#if defined(CONFIG_STM32_FDCAN1_LOOPBACK) +# define STM32_FDCAN_LOOPBACK 1 +#endif + +/* Interrupts ***************************************************************/ + +/* Common interrupts + * + * FDCAN_INT_TSW - Timestamp Wraparound + * FDCAN_INT_MRAF - Message RAM Access Failure + * FDCAN_INT_TOO - Timeout Occurred + * FDCAN_INT_ELO - Error Logging Overflow + * FDCAN_INT_EP - Error Passive + * FDCAN_INT_EW - Warning Status + * FDCAN_INT_BO - Bus_Off Status + * FDCAN_INT_WDI - Watchdog Interrupt + * FDCAN_INT_PEA - Protocol Error in Arbritration Phase + * FDCAN_INT_PED - Protocol Error in Data Phase + */ + +#define FDCAN_CMNERR_INTS (FDCAN_INT_MRAF | FDCAN_INT_TOO | FDCAN_INT_EP | \ + FDCAN_INT_BO | FDCAN_INT_WDI | FDCAN_INT_PEA | \ + FDCAN_INT_PED) +#define FDCAN_COMMON_INTS FDCAN_CMNERR_INTS + +/* RXFIFO mode interrupts + * + * FDCAN_INT_RF0N - Receive FIFO 0 New Message + * FDCAN_INT_RF0F - Receive FIFO 0 Full + * FDCAN_INT_RF0L - Receive FIFO 0 Message Lost + * FDCAN_INT_RF1N - Receive FIFO 1 New Message + * FDCAN_INT_RF1F - Receive FIFO 1 Full + * FDCAN_INT_RF1L - Receive FIFO 1 Message Lost + * FDCAN_INT_HPM - High Priority Message Received + * + */ + +#define FDCAN_RXCOMMON_INTS 0 +#define FDCAN_RXFIFO0_INTS (FDCAN_INT_RF0N | FDCAN_INT_RF0L) +#define FDCAN_RXFIFO1_INTS (FDCAN_INT_RF1N | FDCAN_INT_RF1L) +#define FDCAN_RXFIFO_INTS (FDCAN_RXFIFO0_INTS | FDCAN_RXFIFO1_INTS | \ + FDCAN_INT_HPM | FDCAN_RXCOMMON_INTS) + +#define FDCAN_RXERR_INTS (FDCAN_INT_RF0L | FDCAN_INT_RF1L) + +/* TX FIFOQ mode interrupts + * + * FDCAN_INT_TFE - Tx FIFO Empty + * + * TX Event FIFO interrupts + * + * FDCAN_INT_TEFN - Tx Event FIFO New Entry + * FDCAN_INT_TEFF - Tx Event FIFO Full + * FDCAN_INT_TEFL - Tx Event FIFO Element Lost + * + * Mode-independent TX-related interrupts + * + * FDCAN_INT_TC - Transmission Completed + * FDCAN_INT_TCF - Transmission Cancellation Finished + */ + +#define FDCAN_TXCOMMON_INTS (FDCAN_INT_TC | FDCAN_INT_TCF) +#define FDCAN_TXFIFOQ_INTS (FDCAN_INT_TFE | FDCAN_TXCOMMON_INTS) +#define FDCAN_TXEVFIFO_INTS (FDCAN_INT_TEFN | FDCAN_INT_TEFF | \ + FDCAN_INT_TEFL) +#define FDCAN_TXDEDBUF_INTS FDCAN_TXCOMMON_INTS + +#define FDCAN_TXERR_INTS (FDCAN_INT_TEFL | FDCAN_INT_PEA | FDCAN_INT_PED) + +/* Common-, TX- and RX-Error-Mask */ + +#define FDCAN_ANYERR_INTS (FDCAN_CMNERR_INTS | FDCAN_RXERR_INTS | FDCAN_TXERR_INTS) + +/* Convenience macro for clearing all interrupts */ + +#define FDCAN_INT_ALL 0x3fcfffff + +/* Debug ********************************************************************/ + +/* Debug configurations that may be enabled just for testing FDCAN */ + +#ifndef CONFIG_DEBUG_CAN_INFO +# undef CONFIG_STM32_FDCAN_REGDEBUG +#endif + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/* CAN frame format */ + +enum stm32_frameformat_e +{ + FDCAN_ISO11898_1_FORMAT = 0, /* Frame format according to ISO11898-1 */ + FDCAN_NONISO_BOSCH_V1_FORMAT = 1 /* Frame format according to Bosch CAN FD V1.0 */ +}; + +/* CAN mode of operation */ + +enum stm32_canmode_e +{ + FDCAN_CLASSIC_MODE = 0, /* Classic CAN operation */ +#ifdef CONFIG_CAN_FD + FDCAN_FD_MODE = 1, /* CAN FD operation */ + FDCAN_FD_BRS_MODE = 2 /* CAN FD operation with bit rate switching */ +#endif +}; + +/* CAN driver state */ + +enum can_state_s +{ + FDCAN_STATE_UNINIT = 0, /* Not yet initialized */ + FDCAN_STATE_RESET, /* Initialized, reset state */ + FDCAN_STATE_SETUP, /* fdcan_setup() has been called */ + FDCAN_STATE_DISABLED /* Disabled by a fdcan_shutdown() */ +}; + +/* This structure describes the FDCAN message RAM layout */ + +struct stm32_msgram_s +{ + volatile uint32_t *stdfilters; /* Standard filters */ + volatile uint32_t *extfilters; /* Extended filters */ + volatile uint32_t *rxfifo0; /* RX FIFO0 */ + volatile uint32_t *rxfifo1; /* RX FIFO1 */ + volatile uint32_t *txeventfifo; /* TX event FIFO */ + volatile uint32_t *txfifoq; /* TX FIFO queue */ +}; + +/* This structure provides the constant configuration of a FDCAN peripheral */ + +struct stm32_config_s +{ + uint32_t rxpinset; /* RX pin configuration */ + uint32_t txpinset; /* TX pin configuration */ + uintptr_t base; /* Base address of the FDCAN registers */ + uint32_t baud; /* Configured baud */ + uint32_t nbtp; /* Nominal bit timing/prescaler register setting */ + uint32_t dbtp; /* Data bit timing/prescaler register setting */ + uint8_t port; /* FDCAN port number (1 or 2) */ + uint8_t irq0; /* FDCAN peripheral IRQ number for interrupt line 0 */ + uint8_t irq1; /* FDCAN peripheral IRQ number for interrupt line 1 */ + uint8_t mode; /* See enum stm32_canmode_e */ + uint8_t format; /* See enum stm32_frameformat_e */ + uint8_t nstdfilters; /* Number of standard filters */ + uint8_t nextfilters; /* Number of extended filters */ + uint8_t nrxfifo0; /* Number of RX FIFO0 elements */ + uint8_t nrxfifo1; /* Number of RX FIFO1 elements */ + uint8_t ntxeventfifo; /* Number of TXevent FIFO elements */ + uint8_t ntxfifoq; /* Number of TX FIFO queue elements */ + uint8_t rxfifo0esize; /* RX FIFO0 element size (words) */ + uint8_t rxfifo1esize; /* RX FIFO1 element size (words) */ + uint8_t txeventesize; /* TXevent element size (words) */ + uint8_t txbufferesize; /* TX buffer element size (words) */ +#ifdef STM32_FDCAN_LOOPBACK + bool loopback; /* True: Loopback mode */ +#endif + + /* FDCAN message RAM layout */ + + struct stm32_msgram_s msgram; +}; + +/* This structure provides the current state of a FDCAN peripheral */ + +struct stm32_fdcan_s +{ + /* The constant configuration */ + + const struct stm32_config_s *config; + + uint8_t state; /* See enum can_state_s */ +#ifdef CONFIG_CAN_EXTID + uint8_t nextalloc; /* Number of allocated extended filters */ +#endif + uint8_t nstdalloc; /* Number of allocated standard filters */ + uint32_t nbtp; /* Current nominal bit timing */ + uint32_t dbtp; /* Current data bit timing */ + uint32_t rxints; /* Configured RX interrupts */ + uint32_t txints; /* Configured TX interrupts */ + +#ifdef CONFIG_CAN_EXTID + uint32_t extfilters[2]; /* Extended filter bit allocator. 2*32=64 */ +#endif + uint32_t stdfilters[4]; /* Standard filter bit allocator. 4*32=128 */ + +#ifdef CONFIG_STM32_FDCAN_REGDEBUG + uintptr_t regaddr; /* Last register address read */ + uint32_t regval; /* Last value read from the register */ + unsigned int count; /* Number of times that the value was read */ +#endif +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/* FDCAN Register access */ + +static uint32_t fdcan_getreg(struct stm32_fdcan_s *priv, int offset); +static void fdcan_putreg(struct stm32_fdcan_s *priv, int offset, + uint32_t regval); +#ifdef CONFIG_STM32_FDCAN_REGDEBUG +static void fdcan_dumpregs(struct stm32_fdcan_s *priv, + const char *msg); +static void fdcan_dumprxregs(struct stm32_fdcan_s *priv, + const char *msg); +static void fdcan_dumptxregs(struct stm32_fdcan_s *priv, + const char *msg); +static void fdcan_dumpramlayout(struct stm32_fdcan_s *priv); +#else +# define fdcan_dumpregs(priv,msg) +# define fdcan_dumprxregs(priv,msg) +# define fdcan_dumptxregs(priv,msg) +# define fdcan_dumpramlayout(priv) +#endif + +/* FDCAN helpers */ + +static uint8_t fdcan_dlc2bytes(struct stm32_fdcan_s *priv, uint8_t dlc); + +#ifdef CONFIG_CAN_EXTID +static int fdcan_add_extfilter(struct stm32_fdcan_s *priv, + struct canioc_extfilter_s *extconfig); +static int fdcan_del_extfilter(struct stm32_fdcan_s *priv, int ndx); +#endif +static int fdcan_add_stdfilter(struct stm32_fdcan_s *priv, + struct canioc_stdfilter_s *stdconfig); +static int fdcan_del_stdfilter(struct stm32_fdcan_s *priv, int ndx); + +static int +fdcan_start_busoff_recovery_sequence(struct stm32_fdcan_s *priv); + +/* CAN driver methods */ + +static void fdcan_reset(struct can_dev_s *dev); +static int fdcan_setup(struct can_dev_s *dev); +static void fdcan_shutdown(struct can_dev_s *dev); +static void fdcan_rxint(struct can_dev_s *dev, bool enable); +static void fdcan_txint(struct can_dev_s *dev, bool enable); +static int fdcan_ioctl(struct can_dev_s *dev, int cmd, + unsigned long arg); +static int fdcan_remoterequest(struct can_dev_s *dev, uint16_t id); +static int fdcan_send(struct can_dev_s *dev, struct can_msg_s *msg); +static bool fdcan_txready(struct can_dev_s *dev); +static bool fdcan_txempty(struct can_dev_s *dev); + +/* FDCAN interrupt handling */ + +#ifdef CONFIG_CAN_ERRORS +static void fdcan_error(struct can_dev_s *dev, uint32_t status); +#endif +static void fdcan_receive(struct can_dev_s *dev, + volatile uint32_t *rxbuffer, + unsigned long nwords); +static int fdcan_interrupt(int irq, void *context, void *arg); + +/* Hardware initialization */ + +static int fdcan_hw_initialize(struct stm32_fdcan_s *priv); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static const struct can_ops_s g_fdcanops = +{ + .co_reset = fdcan_reset, + .co_setup = fdcan_setup, + .co_shutdown = fdcan_shutdown, + .co_rxint = fdcan_rxint, + .co_txint = fdcan_txint, + .co_ioctl = fdcan_ioctl, + .co_remoterequest = fdcan_remoterequest, + .co_send = fdcan_send, + .co_txready = fdcan_txready, + .co_txempty = fdcan_txempty, +}; + +#ifdef CONFIG_STM32_FDCAN1 +/* Message RAM allocation */ + +/* Constant configuration */ + +static const struct stm32_config_s g_fdcan1const = +{ + .rxpinset = GPIO_FDCAN1_RX, + .txpinset = GPIO_FDCAN1_TX, + .base = STM32_FDCAN1_BASE, + .baud = CONFIG_STM32_FDCAN1_BITRATE, + .nbtp = FDCAN_NBTP_NBRP(FDCAN1_NBRP) | + FDCAN_NBTP_NTSEG1(FDCAN1_NTSEG1) | + FDCAN_NBTP_NTSEG2(FDCAN1_NTSEG2) | + FDCAN_NBTP_NSJW(FDCAN1_NSJW), + .dbtp = FDCAN_DBTP_DBRP(FDCAN1_DBRP) | + FDCAN_DBTP_DTSEG1(FDCAN1_DTSEG1) | + FDCAN_DBTP_DTSEG2(FDCAN1_DTSEG2) | + FDCAN_DBTP_DSJW(FDCAN1_DSJW), + .port = 1, + .irq0 = STM32_IRQ_FDCAN1_0, + .irq1 = STM32_IRQ_FDCAN1_1, +#if defined(CONFIG_STM32_FDCAN1_CLASSIC) + .mode = FDCAN_CLASSIC_MODE, +#elif defined(CONFIG_STM32_FDCAN1_FD) + .mode = FDCAN_FD_MODE, +#else + .mode = FDCAN_FD_BRS_MODE, +#endif +#if defined(CONFIG_STM32_FDCAN1_NONISO_FORMAT) + .format = FDCAN_NONISO_BOSCH_V1_FORMAT, +#else + .format = FDCAN_ISO11898_1_FORMAT, +#endif + .nstdfilters = FDCAN1_STDFILTER_SIZE, + .nextfilters = FDCAN1_EXTFILTER_SIZE, + .nrxfifo0 = FDCAN1_RXFIFO0_SIZE, + .nrxfifo1 = FDCAN1_RXFIFO1_SIZE, + .ntxeventfifo = FDCAN1_TXEVENTFIFO_SIZE, + .ntxfifoq = FDCAN1_TXFIFIOQ_SIZE, + .rxfifo0esize = (FDCAN1_RXFIFO0_WORDS / FDCAN1_RXFIFO0_SIZE), + .rxfifo1esize = (FDCAN1_RXFIFO1_WORDS / FDCAN1_RXFIFO1_SIZE), + .txeventesize = (FDCAN1_TXEVENTFIFO_WORDS / FDCAN1_TXEVENTFIFO_SIZE), + .txbufferesize = (FDCAN1_TXFIFIOQ_WORDS / FDCAN1_TXFIFIOQ_SIZE), + +#ifdef CONFIG_STM32_FDCAN1_LOOPBACK + .loopback = true, +#endif + + /* FDCAN1 Message RAM */ + + .msgram = + { + (uint32_t *)(STM32_CANRAM1_BASE + (FDCAN1_STDFILTER_INDEX << 2)), + (uint32_t *)(STM32_CANRAM1_BASE + (FDCAN1_EXTFILTERS_INDEX << 2)), + (uint32_t *)(STM32_CANRAM1_BASE + (FDCAN1_RXFIFO0_INDEX << 2)), + (uint32_t *)(STM32_CANRAM1_BASE + (FDCAN1_RXFIFO1_INDEX << 2)), + (uint32_t *)(STM32_CANRAM1_BASE + (FDCAN1_TXEVENTFIFO_INDEX << 2)), + (uint32_t *)(STM32_CANRAM1_BASE + (FDCAN1_TXFIFOQ_INDEX << 2)) + } +}; + +/* FDCAN1 variable driver state */ + +static struct stm32_fdcan_s g_fdcan1priv; +static struct can_dev_s g_fdcan1dev; + +#endif /* CONFIG_STM32_FDCAN1 */ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: fdcan_getreg + * + * Description: + * Read the value of a FDCAN register. + * + * Input Parameters: + * priv - A reference to the FDCAN peripheral state + * offset - The offset to the register to read + * + * Returned Value: + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_FDCAN_REGDEBUG +static uint32_t fdcan_getreg(struct stm32_fdcan_s *priv, int offset) +{ + const struct stm32_config_s *config = priv->config; + uintptr_t regaddr = 0; + uint32_t regval = 0; + + /* Read the value from the register */ + + regaddr = config->base + offset; + regval = getreg32(regaddr); + + /* Is this the same value that we read from the same register last time? + * Are we polling the register? If so, suppress some of the output. + */ + + if (regaddr == priv->regaddr && regval == priv->regval) + { + if (priv->count == 0xffffffff || ++priv->count > 3) + { + if (priv->count == 4) + { + caninfo("...\n"); + } + + return regval; + } + } + + /* No this is a new address or value */ + + else + { + /* Did we print "..." for the previous value? */ + + if (priv->count > 3) + { + /* Yes.. then show how many times the value repeated */ + + caninfo("[repeats %d more times]\n", priv->count - 3); + } + + /* Save the new address, value, and count */ + + priv->regaddr = regaddr; + priv->regval = regval; + priv->count = 1; + } + + /* Show the register value read */ + + caninfo("%08" PRIx32 "->%08" PRIx32 "\n", regaddr, regval); + return regval; +} + +#else +static uint32_t fdcan_getreg(struct stm32_fdcan_s *priv, int offset) +{ + const struct stm32_config_s *config = priv->config; + return getreg32(config->base + offset); +} + +#endif + +/**************************************************************************** + * Name: fdcan_putreg + * + * Description: + * Set the value of a FDCAN register. + * + * Input Parameters: + * priv - A reference to the FDCAN peripheral state + * offset - The offset to the register to write + * regval - The value to write to the register + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_FDCAN_REGDEBUG +static void fdcan_putreg(struct stm32_fdcan_s *priv, int offset, + uint32_t regval) +{ + const struct stm32_config_s *config = priv->config; + uintptr_t regaddr = config->base + offset; + + /* Show the register value being written */ + + caninfo("%08" PRIx32 "->%08" PRIx32 "\n", regaddr, regval); + + /* Write the value */ + + putreg32(regval, regaddr); +} + +#else +static void fdcan_putreg(struct stm32_fdcan_s *priv, int offset, + uint32_t regval) +{ + const struct stm32_config_s *config = priv->config; + putreg32(regval, config->base + offset); +} + +#endif + +/**************************************************************************** + * Name: fdcan_dumpctrlregs + * + * Description: + * Dump the contents of all CAN control registers + * + * Input Parameters: + * priv - A reference to the CAN block status + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_FDCAN_REGDEBUG +static void fdcan_dumpregs(struct stm32_fdcan_s *priv, + const char *msg) +{ + const struct stm32_config_s *config = priv->config; + + caninfo("CAN%d Control and Status Registers: %s\n", config->port, msg); + caninfo(" Base: %08" PRIx32 "\n", config->base); + + /* CAN control and status registers */ + + caninfo(" CCCR: %08" PRIx32 " TEST: %08" PRIx32 "\n", + getreg32(config->base + STM32_FDCAN_CCCR_OFFSET), + getreg32(config->base + STM32_FDCAN_TEST_OFFSET)); + + caninfo(" NBTP: %08" PRIx32 " DBTP: %08" PRIx32 "\n", + getreg32(config->base + STM32_FDCAN_NBTP_OFFSET), + getreg32(config->base + STM32_FDCAN_DBTP_OFFSET)); + + caninfo(" IE: %08" PRIx32 " TIE: %08" PRIx32 "\n", + getreg32(config->base + STM32_FDCAN_IE_OFFSET), + getreg32(config->base + STM32_FDCAN_TXBTIE_OFFSET)); + + caninfo(" ILE: %08" PRIx32 " ILS: %08" PRIx32 "\n", + getreg32(config->base + STM32_FDCAN_ILE_OFFSET), + getreg32(config->base + STM32_FDCAN_ILS_OFFSET)); + + caninfo(" TXBC: %08" PRIx32 "\n", + getreg32(config->base + STM32_FDCAN_TXBC_OFFSET)); +} +#endif + +/**************************************************************************** + * Name: stm32can_dumprxregs + * + * Description: + * Dump the contents of all Rx status registers + * + * Input Parameters: + * priv - A reference to the CAN block status + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_FDCAN_REGDEBUG +static void fdcan_dumprxregs(struct stm32_fdcan_s *priv, + const char *msg) +{ + const struct stm32_config_s *config = priv->config; + + caninfo("CAN%d Rx Registers: %s\n", config->port, msg); + caninfo(" Base: %08" PRIx32 "\n", config->base); + + caninfo(" PSR: %08" PRIx32 " ECR: %08" PRIx32 + " HPMS: %08" PRIx32 "\n", + getreg32(config->base + STM32_FDCAN_PSR_OFFSET), + getreg32(config->base + STM32_FDCAN_ECR_OFFSET), + getreg32(config->base + STM32_FDCAN_HPMS_OFFSET)); + + caninfo(" RXF0S: %08" PRIx32 " RXF0A: %08" PRIx32 "\n", + getreg32(config->base + STM32_FDCAN_RXF0S_OFFSET), + getreg32(config->base + STM32_FDCAN_RXF0A_OFFSET)); + + caninfo(" RXF1S: %08" PRIx32 " RXF1A: %08" PRIx32 "\n", + getreg32(config->base + STM32_FDCAN_RXF1S_OFFSET), + getreg32(config->base + STM32_FDCAN_RXF1A_OFFSET)); + + caninfo(" IR: %08" PRIx32 " IE: %08" PRIx32 "\n", + getreg32(config->base + STM32_FDCAN_IR_OFFSET), + getreg32(config->base + STM32_FDCAN_IE_OFFSET)); +} +#endif + +/**************************************************************************** + * Name: stm32can_dumptxregs + * + * Description: + * Dump the contents of all Tx buffer registers + * + * Input Parameters: + * priv - A reference to the CAN block status + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_FDCAN_REGDEBUG +static void fdcan_dumptxregs(struct stm32_fdcan_s *priv, + const char *msg) +{ + const struct stm32_config_s *config = priv->config; + + caninfo("CAN%d Tx Registers: %s\n", config->port, msg); + caninfo(" Base: %08" PRIx32 "\n", config->base); + + caninfo(" PSR: %08" PRIx32 " ECR: %08" PRIx32 "\n", + getreg32(config->base + STM32_FDCAN_PSR_OFFSET), + getreg32(config->base + STM32_FDCAN_ECR_OFFSET)); + + caninfo(" TXQFS: %08" PRIx32 " TXBAR: %08" PRIx32 + " TXBRP: %08" PRIx32 "\n", + getreg32(config->base + STM32_FDCAN_TXFQS_OFFSET), + getreg32(config->base + STM32_FDCAN_TXBAR_OFFSET), + getreg32(config->base + STM32_FDCAN_TXBRP_OFFSET)); + + caninfo(" TXBTO: %08" PRIx32 " TXBCR: %08" PRIx32 "\n", + getreg32(config->base + STM32_FDCAN_TXBTO_OFFSET), + getreg32(config->base + STM32_FDCAN_TXBCR_OFFSET)); + + caninfo(" TXEFS: %08" PRIx32 " TXEFA: %08" PRIx32 "\n", + getreg32(config->base + STM32_FDCAN_TXEFS_OFFSET), + getreg32(config->base + STM32_FDCAN_TXEFA_OFFSET)); + + caninfo(" IR: %08" PRIx32 " IE: %08" PRIx32 + " TIE: %08" PRIx32 "\n", + getreg32(config->base + STM32_FDCAN_IR_OFFSET), + getreg32(config->base + STM32_FDCAN_IE_OFFSET), + getreg32(config->base + STM32_FDCAN_TXBTIE_OFFSET)); +} +#endif + +/**************************************************************************** + * Name: stm32can_dumpramlayout + * + * Description: + * Print the layout of the message RAM + * + * Input Parameters: + * priv - A reference to the CAN block status + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_FDCAN_REGDEBUG +static void fdcan_dumpramlayout(struct stm32_fdcan_s *priv) +{ + const struct stm32_config_s *config = priv->config; + + caninfo(" ******* FDCAN%d Message RAM layout *******\n", config->port); + caninfo(" Start # Elmnt Elmnt size (words)\n"); + + if (config->nstdfilters > 0) + { + caninfo("STD filters %p %4d %2d\n", + config->msgram.stdfilters, + config->nstdfilters, + 1); + } + + if (config->nextfilters > 0) + { + caninfo("EXT filters %p %4d %2d\n", + config->msgram.extfilters, + config->nextfilters, + 2); + } + + if (config->nrxfifo0 > 0) + { + caninfo("RX FIFO 0 %p %4d %2d\n", + config->msgram.rxfifo0, + config->nrxfifo0, + config->rxfifo0esize); + } + + if (config->nrxfifo1 > 0) + { + caninfo("RX FIFO 1 %p %4d %2d\n", + config->msgram.rxfifo1, + config->nrxfifo1, + config->rxfifo1esize); + } + + if (config->ntxeventfifo > 0) + { + caninfo("TX EVENT %p %4d %2d\n", + config->msgram.txeventfifo, + config->ntxeventfifo, + config->txeventesize); + } + + if (config->ntxfifoq > 0) + { + caninfo("TX FIFO %p %4d %2d\n", + config->msgram.txfifoq, + config->ntxfifoq, + config->txbufferesize); + } +} +#endif + +/**************************************************************************** + * Name: fdcan_dlc2bytes + * + * Description: + * In the CAN FD format, the coding of the DLC differs from the standard + * CAN format. The DLC codes 0 to 8 have the same coding as in standard + * CAN. But the codes 9 to 15 all imply a data field of 8 bytes with + * standard CAN. In CAN FD mode, the values 9 to 15 are encoded to values + * in the range 12 to 64. + * + * Input Parameters: + * dlc - the DLC value to convert to a byte count + * + * Returned Value: + * The number of bytes corresponding to the DLC value. + * + ****************************************************************************/ + +static uint8_t fdcan_dlc2bytes(struct stm32_fdcan_s *priv, uint8_t dlc) +{ + if (dlc > 8) + { +#ifdef CONFIG_CAN_FD + if (priv->config->mode == FDCAN_CLASSIC_MODE) + { + return 8; + } + else + { + switch (dlc) + { + case 9: + return 12; + case 10: + return 16; + case 11: + return 20; + case 12: + return 24; + case 13: + return 32; + case 14: + return 48; + default: + case 15: + return 64; + } + } +#else + return 8; +#endif + } + + return dlc; +} + +/**************************************************************************** + * Name: fdcan_add_extfilter + * + * Description: + * Add an address filter for a extended 29 bit address. + * + * Input Parameters: + * priv - An instance of the FDCAN driver state structure. + * extconfig - The configuration of the extended filter + * + * Returned Value: + * A non-negative filter ID is returned on success. Otherwise a negated + * errno value is returned to indicate the nature of the error. + * + ****************************************************************************/ + +#ifdef CONFIG_CAN_EXTID +static int fdcan_add_extfilter(struct stm32_fdcan_s *priv, + struct canioc_extfilter_s *extconfig) +{ + const struct stm32_config_s *config = NULL; + volatile uint32_t *extfilter = NULL; + uint32_t regval = 0; + int word = 0; + int bit = 0; + int ndx = 0; + + DEBUGASSERT(priv != NULL && priv->config != NULL && extconfig != NULL); + config = priv->config; + + /* Find an unused standard filter */ + + for (ndx = 0; ndx < config->nextfilters; ndx++) + { + /* Is this filter assigned? */ + + word = ndx >> 5; + bit = ndx & 0x1f; + + if ((priv->extfilters[word] & (1 << bit)) == 0) + { + /* No, assign the filter */ + + DEBUGASSERT(priv->nextalloc < priv->config->nstdfilters); + priv->extfilters[word] |= (1 << bit); + priv->nextalloc++; + + extfilter = config->msgram.extfilters + (ndx << 1); + + /* Format and write filter word F0 */ + + DEBUGASSERT(extconfig->xf_id1 <= CAN_MAX_EXTMSGID); + regval = EXTFILTER_F0_EFID1(extconfig->xf_id1); + + if (extconfig->xf_prio == 0) + { + regval |= EXTFILTER_F0_EFEC_FIFO0; + } + else + { + regval |= EXTFILTER_F0_EFEC_FIFO1; + } + + extfilter[0] = regval; + + /* Format and write filter word F1 */ + + DEBUGASSERT(extconfig->xf_id2 <= CAN_MAX_EXTMSGID); + regval = EXTFILTER_F1_EFID2(extconfig->xf_id2); + + switch (extconfig->xf_type) + { + case CAN_FILTER_DUAL: + { + regval |= EXTFILTER_F1_EFT_DUAL; + break; + } + + case CAN_FILTER_MASK: + { + regval |= EXTFILTER_F1_EFT_CLASSIC; + break; + } + + case CAN_FILTER_RANGE: + { + regval |= EXTFILTER_F1_EFT_RANGE; + break; + } + + default: + { + return -EINVAL; + } + } + + extfilter[1] = regval; + + /* Is this the first extended filter? */ + + if (priv->nextalloc == 1) + { + /* Enable the Initialization state */ + + regval = fdcan_getreg(priv, STM32_FDCAN_CCCR_OFFSET); + regval |= FDCAN_CCCR_INIT; + fdcan_putreg(priv, STM32_FDCAN_CCCR_OFFSET, regval); + + /* Wait for initialization mode to take effect */ + + while ((fdcan_getreg(priv, STM32_FDCAN_CCCR_OFFSET) & + FDCAN_CCCR_INIT) == 0); + + /* Enable writing to configuration registers */ + + regval = fdcan_getreg(priv, STM32_FDCAN_CCCR_OFFSET); + regval |= (FDCAN_CCCR_INIT | FDCAN_CCCR_CCE); + fdcan_putreg(priv, STM32_FDCAN_CCCR_OFFSET, regval); + + /* Update the Global Filter Configuration so that received + * messages are rejected if they do not match the acceptance + * filter. + * + * ANFE=2: Discard all rejected frames + */ + + regval = fdcan_getreg(priv, STM32_FDCAN_RXGFC_OFFSET); + regval &= ~FDCAN_RXGFC_ANFE_MASK; + regval |= FDCAN_RXGFC_ANFE_REJECTED; + fdcan_putreg(priv, STM32_FDCAN_RXGFC_OFFSET, regval); + + /* Disable writing to configuration registers */ + + regval = fdcan_getreg(priv, STM32_FDCAN_CCCR_OFFSET); + regval &= ~(FDCAN_CCCR_INIT | FDCAN_CCCR_CCE); + fdcan_putreg(priv, STM32_FDCAN_CCCR_OFFSET, regval); + } + + return ndx; + } + } + + DEBUGASSERT(priv->nextalloc == priv->config->nextfilters); + + return -EAGAIN; +} +#endif + +/**************************************************************************** + * Name: fdcan_del_extfilter + * + * Description: + * Remove an address filter for a standard 29 bit address. + * + * Input Parameters: + * priv - An instance of the FDCAN driver state structure. + * ndx - The filter index previously returned by the + * fdcan_add_extfilter(). + * + * Returned Value: + * Zero (OK) is returned on success. Otherwise a negated errno value is + * returned to indicate the nature of the error. + * + ****************************************************************************/ + +#ifdef CONFIG_CAN_EXTID +static int fdcan_del_extfilter(struct stm32_fdcan_s *priv, int ndx) +{ + const struct stm32_config_s *config = NULL; + volatile uint32_t *extfilter = NULL; + uint32_t regval = 0; + int word = 0; + int bit = 0; + + DEBUGASSERT(priv != NULL && priv->config != NULL); + config = priv->config; + + /* Check user Parameters */ + + DEBUGASSERT(ndx >= 0 || ndx < config->nextfilters); + + if (ndx < 0 || ndx >= config->nextfilters) + { + return -EINVAL; + } + + word = ndx >> 5; + bit = ndx & 0x1f; + + /* Check if this filter is really assigned */ + + if ((priv->extfilters[word] & (1 << bit)) == 0) + { + /* No, error out */ + + return -ENOENT; + } + + /* Release the filter */ + + priv->extfilters[word] &= ~(1 << bit); + + DEBUGASSERT(priv->nextalloc > 0); + priv->nextalloc--; + + /* Was that the last extended filter? */ + + if (priv->nextalloc == 0) + { + /* Enable the Initialization state */ + + regval = fdcan_getreg(priv, STM32_FDCAN_CCCR_OFFSET); + regval |= FDCAN_CCCR_INIT; + fdcan_putreg(priv, STM32_FDCAN_CCCR_OFFSET, regval); + + /* Wait for initialization mode to take effect */ + + while ((fdcan_getreg(priv, STM32_FDCAN_CCCR_OFFSET) & + FDCAN_CCCR_INIT) == 0); + + /* Enable writing to configuration registers */ + + regval = fdcan_getreg(priv, STM32_FDCAN_CCCR_OFFSET); + regval |= (FDCAN_CCCR_INIT | FDCAN_CCCR_CCE); + fdcan_putreg(priv, STM32_FDCAN_CCCR_OFFSET, regval); + + /* If there are no extended filters, then modify Global Filter + * Configuration so that all rejected messages are places in RX + * FIFO0. + * + * ANFE=0: Store all rejected extended frame in RX FIFO0 + */ + + regval = fdcan_getreg(priv, STM32_FDCAN_RXGFC_OFFSET); + regval &= ~FDCAN_RXGFC_ANFE_MASK; + regval |= FDCAN_RXGFC_ANFE_RX_FIFO0; + fdcan_putreg(priv, STM32_FDCAN_RXGFC_OFFSET, regval); + + /* Disable writing to configuration registers */ + + regval = fdcan_getreg(priv, STM32_FDCAN_CCCR_OFFSET); + regval &= ~(FDCAN_CCCR_INIT | FDCAN_CCCR_CCE); + fdcan_putreg(priv, STM32_FDCAN_CCCR_OFFSET, regval); + } + + /* Deactivate the filter last so that no messages are lost. */ + + extfilter = config->msgram.extfilters + (ndx << 1); + *extfilter++ = 0; + *extfilter = 0; + + return OK; +} +#endif + +/**************************************************************************** + * Name: fdcan_add_stdfilter + * + * Description: + * Add an address filter for a standard 11 bit address. + * + * Input Parameters: + * priv - An instance of the FDCAN driver state structure. + * stdconfig - The configuration of the standard filter + * + * Returned Value: + * A non-negative filter ID is returned on success. Otherwise a negated + * errno value is returned to indicate the nature of the error. + * + ****************************************************************************/ + +static int fdcan_add_stdfilter(struct stm32_fdcan_s *priv, + struct canioc_stdfilter_s *stdconfig) +{ + const struct stm32_config_s *config = NULL; + volatile uint32_t *stdfilter = NULL; + uint32_t regval = 0; + int word = 0; + int bit = 0; + int ndx = 0; + + DEBUGASSERT(priv != NULL && priv->config != NULL); + config = priv->config; + + /* Find an unused standard filter */ + + for (ndx = 0; ndx < config->nstdfilters; ndx++) + { + /* Is this filter assigned? */ + + word = ndx >> 5; + bit = ndx & 0x1f; + + if ((priv->stdfilters[word] & (1 << bit)) == 0) + { + /* No, assign the filter */ + + DEBUGASSERT(priv->nstdalloc < priv->config->nstdfilters); + priv->stdfilters[word] |= (1 << bit); + priv->nstdalloc++; + + /* Format and write filter word S0 */ + + stdfilter = config->msgram.stdfilters + ndx; + + DEBUGASSERT(stdconfig->sf_id1 <= CAN_MAX_STDMSGID); + regval = STDFILTER_S0_SFID1(stdconfig->sf_id1); + + DEBUGASSERT(stdconfig->sf_id2 <= CAN_MAX_STDMSGID); + regval |= STDFILTER_S0_SFID2(stdconfig->sf_id2); + + if (stdconfig->sf_prio == 0) + { + regval |= STDFILTER_S0_SFEC_FIFO0; + } + else + { + regval |= STDFILTER_S0_SFEC_FIFO1; + } + + switch (stdconfig->sf_type) + { + case CAN_FILTER_DUAL: + { + regval |= STDFILTER_S0_SFT_DUAL; + break; + } + + case CAN_FILTER_MASK: + { + regval |= STDFILTER_S0_SFT_CLASSIC; + break; + } + + case CAN_FILTER_RANGE: + { + regval |= STDFILTER_S0_SFT_RANGE; + break; + } + + default: + { + return -EINVAL; + } + } + + *stdfilter = regval; + + /* Is this the first standard filter? */ + + if (priv->nstdalloc == 1) + { + /* Enable the Initialization state */ + + regval = fdcan_getreg(priv, STM32_FDCAN_CCCR_OFFSET); + regval |= FDCAN_CCCR_INIT; + fdcan_putreg(priv, STM32_FDCAN_CCCR_OFFSET, regval); + + /* Wait for initialization mode to take effect */ + + while ((fdcan_getreg(priv, STM32_FDCAN_CCCR_OFFSET) & + FDCAN_CCCR_INIT) == 0); + + /* Enable writing to configuration registers */ + + regval = fdcan_getreg(priv, STM32_FDCAN_CCCR_OFFSET); + regval |= (FDCAN_CCCR_INIT | FDCAN_CCCR_CCE); + fdcan_putreg(priv, STM32_FDCAN_CCCR_OFFSET, regval); + + /* Update the Global Filter Configuration so that received + * messages are rejected if they do not match the acceptance + * filter. + * + * ANFS=2: Discard all rejected frames + */ + + regval = fdcan_getreg(priv, STM32_FDCAN_RXGFC_OFFSET); + regval &= ~FDCAN_RXGFC_ANFS_MASK; + regval |= FDCAN_RXGFC_ANFS_REJECTED; + fdcan_putreg(priv, STM32_FDCAN_RXGFC_OFFSET, regval); + + /* Disable writing to configuration registers */ + + regval = fdcan_getreg(priv, STM32_FDCAN_CCCR_OFFSET); + regval &= ~(FDCAN_CCCR_INIT | FDCAN_CCCR_CCE); + fdcan_putreg(priv, STM32_FDCAN_CCCR_OFFSET, regval); + } + + return ndx; + } + } + + DEBUGASSERT(priv->nstdalloc == priv->config->nstdfilters); + return -EAGAIN; +} + +/**************************************************************************** + * Name: fdcan_del_stdfilter + * + * Description: + * Remove an address filter for a standard 29 bit address. + * + * Input Parameters: + * priv - An instance of the FDCAN driver state structure. + * ndx - The filter index previously returned by the + * fdcan_add_stdfilter(). + * + * Returned Value: + * Zero (OK) is returned on success. Otherwise a negated errno value is + * returned to indicate the nature of the error. + * + ****************************************************************************/ + +static int fdcan_del_stdfilter(struct stm32_fdcan_s *priv, int ndx) +{ + const struct stm32_config_s *config = NULL; + volatile uint32_t *stdfilter = NULL; + uint32_t regval = 0; + int word = 0; + int bit = 0; + + DEBUGASSERT(priv != NULL && priv->config != NULL); + config = priv->config; + + /* Check Userspace Parameters */ + + DEBUGASSERT(ndx >= 0 || ndx < config->nstdfilters); + + if (ndx < 0 || ndx >= config->nstdfilters) + { + return -EINVAL; + } + + word = ndx >> 5; + bit = ndx & 0x1f; + + /* Check if this filter is really assigned */ + + if ((priv->stdfilters[word] & (1 << bit)) == 0) + { + /* No, error out */ + + return -ENOENT; + } + + /* Release the filter */ + + priv->stdfilters[word] &= ~(1 << bit); + + DEBUGASSERT(priv->nstdalloc > 0); + priv->nstdalloc--; + + /* Was that the last standard filter? */ + + if (priv->nstdalloc == 0) + { + /* Enable the Initialization state */ + + regval = fdcan_getreg(priv, STM32_FDCAN_CCCR_OFFSET); + regval |= FDCAN_CCCR_INIT; + fdcan_putreg(priv, STM32_FDCAN_CCCR_OFFSET, regval); + + /* Wait for initialization mode to take effect */ + + while ((fdcan_getreg(priv, STM32_FDCAN_CCCR_OFFSET) & + FDCAN_CCCR_INIT) == 0); + + /* Enable writing to configuration registers */ + + regval = fdcan_getreg(priv, STM32_FDCAN_CCCR_OFFSET); + regval |= (FDCAN_CCCR_INIT | FDCAN_CCCR_CCE); + fdcan_putreg(priv, STM32_FDCAN_CCCR_OFFSET, regval); + + /* If there are no standard filters, then modify Global Filter + * Configuration so that all rejected messages are places in RX + * FIFO0. + * + * ANFS=0: Store all rejected extended frame in RX FIFO0 + */ + + regval = fdcan_getreg(priv, STM32_FDCAN_RXGFC_OFFSET); + regval &= ~FDCAN_RXGFC_ANFS_MASK; + regval |= FDCAN_RXGFC_ANFS_RX_FIFO0; + fdcan_putreg(priv, STM32_FDCAN_RXGFC_OFFSET, regval); + + /* Disable writing to configuration registers */ + + regval = fdcan_getreg(priv, STM32_FDCAN_CCCR_OFFSET); + regval &= ~(FDCAN_CCCR_INIT | FDCAN_CCCR_CCE); + fdcan_putreg(priv, STM32_FDCAN_CCCR_OFFSET, regval); + } + + /* Deactivate the filter last so that no messages are lost. */ + + stdfilter = config->msgram.stdfilters + ndx; + *stdfilter = 0; + + return OK; +} + +/**************************************************************************** + * Name: fdcan_start_busoff_recovery_sequence + * + * Description: + * This function initiates the BUS-OFF recovery sequence. + * CAN Specification Rev. 2.0 or ISO11898-1:2015. + * According the STM32G4 datasheet section 44.3.2 Software initialziation. + * + * Input Parameters: + * priv - An instance of the FDCAN driver state structure. + * + * Returned Value: + * Zero (OK) is returned on success. Otherwise a negated errno value is + * returned to indicate the nature of the error. + * + ****************************************************************************/ + +static int +fdcan_start_busoff_recovery_sequence(struct stm32_fdcan_s *priv) +{ + uint32_t regval = 0; + + DEBUGASSERT(priv); + + /* Only start BUS-OFF recovery if we are in BUS-OFF state */ + + regval = fdcan_getreg(priv, STM32_FDCAN_PSR_OFFSET); + if ((regval & FDCAN_PSR_BO) == 0) + { + return -EPERM; + } + + /* Disable initialization mode to issue the recovery sequence */ + + regval = fdcan_getreg(priv, STM32_FDCAN_CCCR_OFFSET); + regval &= ~FDCAN_CCCR_INIT; + fdcan_putreg(priv, STM32_FDCAN_CCCR_OFFSET, regval); + + return OK; +} + +/**************************************************************************** + * Name: fdcan_reset + * + * Description: + * Reset the FDCAN device. Called early to initialize the hardware. This + * function is called, before fdcan_setup() and on error conditions. + * + * Input Parameters: + * dev - An instance of the "upper half" can driver state structure. + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void fdcan_reset(struct can_dev_s *dev) +{ + struct stm32_fdcan_s *priv = NULL; + const struct stm32_config_s *config = NULL; + uint32_t regval = 0; + irqstate_t flags; + + DEBUGASSERT(dev); + priv = dev->cd_priv; + DEBUGASSERT(priv); + config = priv->config; + DEBUGASSERT(config); + + caninfo("FDCAN%d\n", config->port); + UNUSED(config); + + /* Disable all interrupts */ + + fdcan_putreg(priv, STM32_FDCAN_IE_OFFSET, 0); + fdcan_putreg(priv, STM32_FDCAN_TXBTIE_OFFSET, 0); + + /* Make sure that all buffers are released. + * + * REVISIT: What if a thread is waiting for a buffer? The following + * will not wake up any waiting threads. + */ + + /* Disable the FDCAN controller. + * REVISIT: Should fdcan_shutdown() be called here? + */ + + /* Reset the FD CAN. + * REVISIT: Since there is only a single reset for both FDCAN + * controllers, do we really want to use the RCC reset here? + * This will nuke operation of the second controller if another + * device is registered. + */ + + flags = enter_critical_section(); + regval = getreg32(STM32_RCC_APB1RSTR); + regval |= RCC_APB1RSTR_FDCANRST; + putreg32(regval, STM32_RCC_APB1RSTR); + + regval &= ~RCC_APB1RSTR_FDCANRST; + putreg32(regval, STM32_RCC_APB1RSTR); + leave_critical_section(flags); + + priv->state = FDCAN_STATE_RESET; +} + +/**************************************************************************** + * Name: fdcan_setup + * + * Description: + * Configure the FDCAN. This method is called the first time that the FDCAN + * device is opened. This will occur when the port is first opened. + * This setup includes configuring and attaching FDCAN interrupts. + * All FDCAN interrupts are disabled upon return. + * + * Input Parameters: + * dev - An instance of the "upper half" can driver state structure. + * + * Returned Value: + * Zero on success; a negated errno on failure + * + ****************************************************************************/ + +static int fdcan_setup(struct can_dev_s *dev) +{ + struct stm32_fdcan_s *priv = NULL; + const struct stm32_config_s *config = NULL; + int ret = 0; + + DEBUGASSERT(dev); + priv = dev->cd_priv; + DEBUGASSERT(priv); + config = priv->config; + DEBUGASSERT(config); + + caninfo("FDCAN%d\n", config->port); + + /* FDCAN hardware initialization */ + + ret = fdcan_hw_initialize(priv); + if (ret < 0) + { + canerr("ERROR: FDCAN%d H/W initialization failed: %d\n", + config->port, ret); + return ret; + } + + fdcan_dumpregs(priv, "After hardware initialization"); + + /* Attach the FDCAN interrupt handlers */ + + ret = irq_attach(config->irq0, fdcan_interrupt, dev); + if (ret < 0) + { + canerr("ERROR: Failed to attach FDCAN%d line 0 IRQ (%d)", + config->port, config->irq0); + return ret; + } + + ret = irq_attach(config->irq1, fdcan_interrupt, dev); + if (ret < 0) + { + canerr("ERROR: Failed to attach FDCAN%d line 1 IRQ (%d)", + config->port, config->irq1); + return ret; + } + + priv->state = FDCAN_STATE_SETUP; + + /* Enable the interrupts at the NVIC (they are still disabled at the FDCAN + * peripheral). + */ + + up_enable_irq(config->irq0); + up_enable_irq(config->irq1); + + return OK; +} + +/**************************************************************************** + * Name: fdcan_shutdown + * + * Description: + * Disable the FDCAN. This method is called when the FDCAN device + * is closed. This method reverses the operation the setup method. + * + * Input Parameters: + * dev - An instance of the "upper half" can driver state structure. + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void fdcan_shutdown(struct can_dev_s *dev) +{ + struct stm32_fdcan_s *priv = NULL; + const struct stm32_config_s *config = NULL; + uint32_t regval = 0; + + DEBUGASSERT(dev); + priv = dev->cd_priv; + DEBUGASSERT(priv); + config = priv->config; + DEBUGASSERT(config); + + caninfo("FDCAN%d\n", config->port); + + /* Disable FDCAN interrupts at the NVIC */ + + up_disable_irq(config->irq0); + up_disable_irq(config->irq1); + + /* Disable all interrupts from the FDCAN peripheral */ + + fdcan_putreg(priv, STM32_FDCAN_IE_OFFSET, 0); + fdcan_putreg(priv, STM32_FDCAN_TXBTIE_OFFSET, 0); + + /* Detach the FDCAN interrupt handler */ + + irq_detach(config->irq0); + irq_detach(config->irq1); + + /* Disable device by setting the Clock Stop Request bit */ + + regval = fdcan_getreg(priv, STM32_FDCAN_CCCR_OFFSET); + regval |= FDCAN_CCCR_CSR; + fdcan_putreg(priv, STM32_FDCAN_CCCR_OFFSET, regval); + + /* Wait for Init and Clock Stop Acknowledge bits to verify + * device is in the powered down state + */ + + while ((fdcan_getreg(priv, STM32_FDCAN_CCCR_OFFSET) & FDCAN_CCCR_INIT) + == 0); + while ((fdcan_getreg(priv, STM32_FDCAN_CCCR_OFFSET) & FDCAN_CCCR_CSA) + == 0); + priv->state = FDCAN_STATE_DISABLED; +} + +/**************************************************************************** + * Name: fdcan_rxint + * + * Description: + * Call to enable or disable RX interrupts. + * + * Input Parameters: + * dev - An instance of the "upper half" can driver state structure. + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void fdcan_rxint(struct can_dev_s *dev, bool enable) +{ + struct stm32_fdcan_s *priv = dev->cd_priv; + uint32_t regval = 0; + + DEBUGASSERT(priv && priv->config); + + caninfo("FDCAN%d enable: %d\n", priv->config->port, enable); + + /* Enable/disable the receive interrupts */ + + regval = fdcan_getreg(priv, STM32_FDCAN_IE_OFFSET); + + if (enable) + { + regval |= priv->rxints | FDCAN_COMMON_INTS; + } + else + { + regval &= ~priv->rxints; + } + + fdcan_putreg(priv, STM32_FDCAN_IE_OFFSET, regval); +} + +/**************************************************************************** + * Name: fdcan_txint + * + * Description: + * Call to enable or disable TX interrupts. + * + * Input Parameters: + * dev - An instance of the "upper half" can driver state structure. + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void fdcan_txint(struct can_dev_s *dev, bool enable) +{ + struct stm32_fdcan_s *priv = dev->cd_priv; + uint32_t regval = 0; + + DEBUGASSERT(priv && priv->config); + + caninfo("FDCAN%d enable: %d\n", priv->config->port, enable); + + /* Enable/disable the receive interrupts */ + + regval = fdcan_getreg(priv, STM32_FDCAN_IE_OFFSET); + + if (enable) + { + regval |= priv->txints | FDCAN_COMMON_INTS; + } + else + { + regval &= ~priv->txints; + } + + fdcan_putreg(priv, STM32_FDCAN_IE_OFFSET, regval); +} + +/**************************************************************************** + * Name: fdcan_ioctl + * + * Description: + * All ioctl calls will be routed through this method + * + * Input Parameters: + * dev - An instance of the "upper half" can driver state structure. + * + * Returned Value: + * Zero on success; a negated errno on failure + * + ****************************************************************************/ + +static int fdcan_ioctl(struct can_dev_s *dev, int cmd, unsigned long arg) +{ + struct stm32_fdcan_s *priv = NULL; + int ret = -ENOTTY; + + caninfo("cmd=%04x arg=%lu\n", cmd, arg); + + DEBUGASSERT(dev && dev->cd_priv); + priv = dev->cd_priv; + + /* Handle the command */ + + switch (cmd) + { + /* CANIOC_GET_BITTIMING: + * Description: Return the current bit timing settings + * Argument: A pointer to a write-able instance of struct + * canioc_bittiming_s in which current bit timing + * values will be returned. + * Returned Value: Zero (OK) is returned on success. Otherwise -1 + * (ERROR) is returned with the errno variable set + * to indicate the nature of the error. + * Dependencies: None + */ + + case CANIOC_GET_BITTIMING: + { + struct canioc_bittiming_s *bt = + (struct canioc_bittiming_s *)arg; + uint32_t regval; + uint32_t nbrp; + + DEBUGASSERT(bt != NULL); + +#ifdef CONFIG_CAN_FD + if (bt->type == CAN_BITTIMING_DATA) + { + regval = fdcan_getreg(priv, STM32_FDCAN_DBTP_OFFSET); + bt->bt_sjw = ((regval & FDCAN_DBTP_DSJW_MASK) >> + FDCAN_DBTP_DSJW_SHIFT) + 1; + bt->bt_tseg1 = ((regval & FDCAN_DBTP_DTSEG1_MASK) >> + FDCAN_DBTP_DTSEG1_SHIFT) + 1; + bt->bt_tseg2 = ((regval & FDCAN_DBTP_DTSEG2_MASK) >> + FDCAN_DBTP_DTSEG2_SHIFT) + 1; + + nbrp = ((regval & FDCAN_DBTP_DBRP_MASK) >> + FDCAN_DBTP_DBRP_SHIFT) + 1; + bt->bt_baud = STM32_FDCANCLK_FREQUENCY / nbrp / + (bt->bt_tseg1 + bt->bt_tseg2 + 1); + } + else +#endif + { + regval = fdcan_getreg(priv, STM32_FDCAN_NBTP_OFFSET); + bt->bt_sjw = ((regval & FDCAN_NBTP_NSJW_MASK) >> + FDCAN_NBTP_NSJW_SHIFT) + 1; + bt->bt_tseg1 = ((regval & FDCAN_NBTP_NTSEG1_MASK) >> + FDCAN_NBTP_NTSEG1_SHIFT) + 1; + bt->bt_tseg2 = ((regval & FDCAN_NBTP_NTSEG2_MASK) >> + FDCAN_NBTP_NTSEG2_SHIFT) + 1; + + nbrp = ((regval & FDCAN_NBTP_NBRP_MASK) >> + FDCAN_NBTP_NBRP_SHIFT) + 1; + bt->bt_baud = STM32_FDCANCLK_FREQUENCY / nbrp / + (bt->bt_tseg1 + bt->bt_tseg2 + 1); + } + + ret = OK; + } + break; + + /* CANIOC_SET_BITTIMING: + * Description: Set new current bit timing values + * Argument: A pointer to a read-able instance of struct + * canioc_bittiming_s in which the new bit timing + * values are provided. + * Returned Value: Zero (OK) is returned on success. Otherwise -1 + * (ERROR) is returned with the errno variable set + * to indicate the nature of the error. + * Dependencies: None + * + * REVISIT: There is probably a limitation here: If there are + * multiple threads trying to send CAN packets, when one of these + * threads reconfigures the bitrate, the FDCAN hardware will be reset + * and the context of operation will be lost. Hence, this IOCTL can + * only safely be executed in quiescent time periods. + */ + + case CANIOC_SET_BITTIMING: + { + const struct canioc_bittiming_s *bt = + (const struct canioc_bittiming_s *)arg; + uint32_t nbrp; + uint32_t ntseg1; + uint32_t ntseg2; + uint32_t nsjw; + uint32_t ie; + uint8_t state; + + DEBUGASSERT(bt != NULL); + DEBUGASSERT(bt->bt_baud < STM32_FDCANCLK_FREQUENCY); + DEBUGASSERT(bt->bt_sjw > 0 && bt->bt_sjw <= 16); + DEBUGASSERT(bt->bt_tseg1 > 1 && bt->bt_tseg1 <= 64); + DEBUGASSERT(bt->bt_tseg2 > 0 && bt->bt_tseg2 <= 16); + + /* Extract bit timing data */ + + ntseg1 = bt->bt_tseg1 - 1; + ntseg2 = bt->bt_tseg2 - 1; + nsjw = bt->bt_sjw - 1; + + nbrp = (uint32_t) + (((float) STM32_FDCANCLK_FREQUENCY / + ((float)(ntseg1 + ntseg2 + 3) * (float)bt->bt_baud)) - 1); + + /* Save the value of the new bit timing register */ + +#ifdef CONFIG_CAN_FD + if (bt->type == CAN_BITTIMING_DATA) + { + priv->dbtp = FDCAN_NBTP_DBRP(nbrp) | + FDCAN_NBTP_DTSEG1(ntseg1) | + FDCAN_DBTP_DTSEG2(ntseg2) | + FDCAN_DBTP_DSJW(nsjw); + } + else +#endif + { + priv->nbtp = FDCAN_NBTP_NBRP(nbrp) | + FDCAN_NBTP_NTSEG1(ntseg1) | + FDCAN_NBTP_NTSEG2(ntseg2) | + FDCAN_NBTP_NSJW(nsjw); + } + + /* We need to reset to instantiate the new timing. Save + * current state information so that recover to this + * state. + */ + + ie = fdcan_getreg(priv, STM32_FDCAN_IE_OFFSET); + state = priv->state; + + /* Reset the FDCAN */ + + fdcan_reset(dev); + ret = OK; + + /* If we have previously been setup, then setup again */ + + if (state == FDCAN_STATE_SETUP) + { + ret = fdcan_setup(dev); + } + + /* We we have successfully re-initialized, then restore the + * interrupt state. + * + * REVISIT: Since the hardware was reset, any pending TX + * activity was lost. Should we disable TX interrupts? + */ + + if (ret == OK) + { + fdcan_putreg(priv, STM32_FDCAN_IE_OFFSET, ie & ~priv->txints); + } + } + break; + +#ifdef CONFIG_CAN_EXTID + /* CANIOC_ADD_EXTFILTER: + * Description: Add an address filter for a extended 29 bit + * address. + * Argument: A reference to struct canioc_extfilter_s + * Returned Value: A non-negative filter ID is returned on success. + * Otherwise -1 (ERROR) is returned with the errno + * variable set to indicate the nature of the error. + */ + + case CANIOC_ADD_EXTFILTER: + { + DEBUGASSERT(arg != 0); + + ret = fdcan_add_extfilter(priv, + (struct canioc_extfilter_s *)arg); + } + break; + + /* CANIOC_DEL_EXTFILTER: + * Description: Remove an address filter for a standard 29 bit + * address. + * Argument: The filter index previously returned by the + * CANIOC_ADD_EXTFILTER command + * Returned Value: Zero (OK) is returned on success. Otherwise -1 + * (ERROR) is returned with the errno variable set + * to indicate the nature of the error. + */ + + case CANIOC_DEL_EXTFILTER: + { + DEBUGASSERT(arg <= priv->config->nextfilters); + ret = fdcan_del_extfilter(priv, (int)arg); + } + break; +#endif + + /* CANIOC_ADD_STDFILTER: + * Description: Add an address filter for a standard 11 bit + * address. + * Argument: A reference to struct canioc_stdfilter_s + * Returned Value: A non-negative filter ID is returned on success. + * Otherwise -1 (ERROR) is returned with the errno + * variable set to indicate the nature of the error. + */ + + case CANIOC_ADD_STDFILTER: + { + DEBUGASSERT(arg != 0); + + ret = fdcan_add_stdfilter(priv, + (struct canioc_stdfilter_s *)arg); + } + break; + + /* CANIOC_DEL_STDFILTER: + * Description: Remove an address filter for a standard 11 bit + * address. + * Argument: The filter index previously returned by the + * CANIOC_ADD_STDFILTER command + * Returned Value: Zero (OK) is returned on success. Otherwise -1 + * (ERROR) is returned with the errno variable set + * to indicate the nature of the error. + */ + + case CANIOC_DEL_STDFILTER: + { + DEBUGASSERT(arg <= priv->config->nstdfilters); + ret = fdcan_del_stdfilter(priv, (int)arg); + } + break; + + /* CANIOC_BUSOFF_RECOVERY: + * Description : Initiates the BUS - OFF recovery sequence + * Argument : None + * Returned Value : Zero (OK) is returned on success. Otherwise -1 + * (ERROR) is returned with the errno variable set + * to indicate the nature of the error. + * Dependencies : None + */ + + case CANIOC_BUSOFF_RECOVERY: + { + ret = fdcan_start_busoff_recovery_sequence(priv); + } + break; + + /* Unsupported/unrecognized command */ + + default: + canerr("ERROR: Unrecognized command: %04x\n", cmd); + break; + } + + return ret; +} + +/**************************************************************************** + * Name: fdcan_remoterequest + * + * Description: + * Send a remote request + * + * Input Parameters: + * dev - An instance of the "upper half" can driver state structure. + * + * Returned Value: + * Zero on success; a negated errno on failure + * + ****************************************************************************/ + +static int fdcan_remoterequest(struct can_dev_s *dev, uint16_t id) +{ + /* REVISIT: Remote request not implemented */ + + return -ENOSYS; +} + +/**************************************************************************** + * Name: fdcan_send + * + * Description: + * Send one can message. + * + * One CAN-message consists of a maximum of 10 bytes. A message is + * composed of at least the first 2 bytes (when there are no data bytes). + * + * Byte 0: Bits 0-7: Bits 3-10 of the 11-bit CAN identifier + * Byte 1: Bits 5-7: Bits 0-2 of the 11-bit CAN identifier + * Bit 4: Remote Transmission Request (RTR) + * Bits 0-3: Data Length Code (DLC) + * Bytes 2-10: CAN data + * + * Input Parameters: + * dev - An instance of the "upper half" can driver state structure. + * + * Returned Value: + * Zero on success; a negated errno on failure + * + ****************************************************************************/ + +static int fdcan_send(struct can_dev_s *dev, struct can_msg_s *msg) +{ + struct stm32_fdcan_s *priv = NULL; + const struct stm32_config_s *config = NULL; + volatile uint32_t *txbuffer = NULL; + const uint8_t *src = NULL; + uint32_t *dest = NULL; + uint32_t regval = 0; + unsigned int ndx = 0; + unsigned int nbytes = 0; + uint32_t wordbuffer = 0; + unsigned int i = 0; + + DEBUGASSERT(dev); + priv = dev->cd_priv; + DEBUGASSERT(priv && priv->config); + config = priv->config; + + caninfo("CAN%" PRIu8 " ID: %" PRIu32 " DLC: %" PRIu8 "\n", + config->port, (uint32_t)msg->cm_hdr.ch_id, msg->cm_hdr.ch_dlc); + + fdcan_dumptxregs(priv, "Before send"); + + /* That that FIFO elements were configured */ + + DEBUGASSERT(config->ntxfifoq > 0); + + /* Get our reserved Tx FIFO/queue put index */ + + regval = fdcan_getreg(priv, STM32_FDCAN_TXFQS_OFFSET); + DEBUGASSERT((regval & FDCAN_TXFQS_TFQF) == 0); + + ndx = (regval & FDCAN_TXFQS_TFQPI_MASK) >> FDCAN_TXFQS_TFQPI_SHIFT; + + /* And the TX buffer corresponding to this index */ + + txbuffer = (config->msgram.txfifoq + ndx * config->txbufferesize); + + /* Format the TX FIFOQ entry + * + * Format word T0: + * Transfer message ID (ID) - Value from message structure + * Remote Transmission Request (RTR) - Value from message structure + * Extended Identifier (XTD) - Depends on configuration. + * Error state indicator (ESI) - ESI bit in CAN FD + * + * Format word T1: + * Data Length Code (DLC) - Value from message structure + * Bit Rate Switch (BRS) - Bit rate switching for CAN FD + * FD format (FDF) - Frame transmitted in CAN FD format + * Event FIFO Control (EFC) - Do not store events. + * Message Marker (MM) - Always zero + */ + + txbuffer[0] = 0; + txbuffer[1] = 0; + +#ifdef CONFIG_CAN_EXTID + if (msg->cm_hdr.ch_extid == 1) + { + DEBUGASSERT(msg->cm_hdr.ch_id <= CAN_MAX_EXTMSGID); + + txbuffer[0] |= BUFFER_R0_EXTID(msg->cm_hdr.ch_id) | BUFFER_R0_XTD; + } + else +#endif + { + DEBUGASSERT(msg->cm_hdr.ch_id <= CAN_MAX_STDMSGID); + + txbuffer[0] |= BUFFER_R0_STDID(msg->cm_hdr.ch_id); + } + + if (msg->cm_hdr.ch_rtr == 1) + { + txbuffer[0] |= BUFFER_R0_RTR; + } + + txbuffer[1] |= BUFFER_R1_DLC(msg->cm_hdr.ch_dlc); + +#ifdef CONFIG_CAN_FD + /* CAN FD Format */ + + if (msg->cm_hdr.ch_edl == 1) + { + txbuffer[1] |= BUFFER_R1_FDF; + + if (msg->cm_hdr.ch_brs == 1) + { + txbuffer[1] |= BUFFER_R1_BRS; + } + + if (msg->cm_hdr.ch_esi == 1) + { + txbuffer[0] |= BUFFER_R0_ESI; + } + } + else +#else + { + txbuffer[0] &= ~BUFFER_R0_ESI; + txbuffer[1] &= ~BUFFER_R1_FDF; + txbuffer[1] &= ~BUFFER_R1_BRS; + } +#endif + + /* Followed by the amount of data corresponding to the DLC (T2..) */ + + dest = (uint32_t *)&txbuffer[2]; + src = msg->cm_data; + nbytes = fdcan_dlc2bytes(priv, msg->cm_hdr.ch_dlc); + + /* Writes must be word length */ + + for (i = 0; i < nbytes; i += 4) + { + /* Little endian is assumed */ + + wordbuffer = src[0] | + (src[1] << 8) | + (src[2] << 16) | + (src[3] << 24); + src += 4; + + *dest++ = wordbuffer; + } + + /* Enable transmit interrupts from the TX FIFOQ buffer by setting TC + * interrupt bit in IR (also requires that the TC interrupt is enabled) + */ + + fdcan_putreg(priv, STM32_FDCAN_TXBTIE_OFFSET, (1 << ndx)); + + /* And request to send the packet */ + + fdcan_putreg(priv, STM32_FDCAN_TXBAR_OFFSET, (1 << ndx)); + + return OK; +} + +/**************************************************************************** + * Name: fdcan_txready + * + * Description: + * Return true if the FDCAN hardware can accept another TX message. + * + * Input Parameters: + * dev - An instance of the "upper half" can driver state structure. + * + * Returned Value: + * True if the FDCAN hardware is ready to accept another TX message. + * + ****************************************************************************/ + +static bool fdcan_txready(struct can_dev_s *dev) +{ + struct stm32_fdcan_s *priv = dev->cd_priv; + uint32_t regval = 0; + bool notfull = false; + + /* Return the state of the TX FIFOQ. Return TRUE if the TX FIFO/Queue is + * not full. + */ + + regval = fdcan_getreg(priv, STM32_FDCAN_TXFQS_OFFSET); + notfull = ((regval & FDCAN_TXFQS_TFQF) == 0); + + return notfull; +} + +/**************************************************************************** + * Name: fdcan_txempty + * + * Description: + * Return true if all message have been sent. If for example, the FDCAN + * hardware implements FIFOs, then this would mean the transmit FIFO is + * empty. This method is called when the driver needs to make sure that + * all characters are "drained" from the TX hardware before calling + * co_shutdown(). + * + * Input Parameters: + * dev - An instance of the "upper half" can driver state structure. + * + * Returned Value: + * True if there are no pending TX transfers in the FDCAN hardware. + * + ****************************************************************************/ + +static bool fdcan_txempty(struct can_dev_s *dev) +{ + struct stm32_fdcan_s *priv = dev->cd_priv; + uint32_t regval = 0; + int tffl = 0; + bool empty = false; + + DEBUGASSERT(priv != NULL && priv->config != NULL); + + /* Return the state of the TX FIFOQ. Return TRUE if the TX FIFO/Queue is + * empty. We don't have a reliable indication that the FIFO is empty, so + * we have to use some heuristics. + */ + + regval = fdcan_getreg(priv, STM32_FDCAN_TXFQS_OFFSET); + if ((regval & FDCAN_TXFQS_TFQF) != 0) + { + return false; + } + + /* Tx FIFO Free Level */ + + tffl = (regval & FDCAN_TXFQS_TFFL_MASK) >> FDCAN_TXFQS_TFFL_SHIFT; + empty = (tffl >= priv->config->ntxfifoq); + + return empty; +} + +/**************************************************************************** + * Name: fdcan_error + * + * Description: + * Report a CAN error + * + * Input Parameters: + * dev - CAN-common state data + * status - Interrupt status with error bits set + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_CAN_ERRORS +static void fdcan_error(struct can_dev_s *dev, uint32_t status) +{ + struct stm32_fdcan_s *priv = dev->cd_priv; + struct can_hdr_s hdr; + uint32_t psr = 0; + uint16_t errbits = 0; + uint8_t data[CAN_ERROR_DLC]; + int ret = 0; + + /* Encode error bits */ + + errbits = 0; + memset(data, 0, sizeof(data)); + + /* Always fill in "static" error conditions, but set the signaling bit + * only if the condition has changed (see IRQ-Flags below) + * They have to be filled in every time CAN_ERROR_CONTROLLER is set. + */ + + psr = fdcan_getreg(priv, STM32_FDCAN_PSR_OFFSET); + if ((psr & FDCAN_PSR_EP) != 0) + { + data[1] |= (CAN_ERROR1_RXPASSIVE | CAN_ERROR1_TXPASSIVE); + } + + if ((psr & FDCAN_PSR_EW) != 0) + { + data[1] |= (CAN_ERROR1_RXWARNING | CAN_ERROR1_TXWARNING); + } + + if ((status & (FDCAN_INT_EP | FDCAN_INT_EW)) != 0) + { + /* "Error Passive" or "Error Warning" status changed */ + + errbits |= CAN_ERROR_CONTROLLER; + } + + if ((status & FDCAN_INT_PEA) != 0) + { + /* Protocol Error in Arbitration Phase */ + + if ((psr & FDCAN_PSR_LEC_MASK) != 0) + { + /* Error code present */ + + if ((psr & FDCAN_PSR_LEC(FDCAN_PSR_EC_STUFF_ERROR)) != 0) + { + /* Stuff Error */ + + errbits |= CAN_ERROR_PROTOCOL; + data[2] |= CAN_ERROR2_STUFF; + } + + if ((psr & FDCAN_PSR_LEC(FDCAN_PSR_EC_FORM_ERROR)) != 0) + { + /* Format Error */ + + errbits |= CAN_ERROR_PROTOCOL; + data[2] |= CAN_ERROR2_FORM; + } + + if ((psr & FDCAN_PSR_LEC(FDCAN_PSR_EC_ACK_ERROR)) != 0) + { + /* Acknowledge Error */ + + errbits |= CAN_ERROR_NOACK; + } + + if ((psr & FDCAN_PSR_LEC(FDCAN_PSR_EC_BIT0_ERROR)) != 0) + { + /* Bit0 Error */ + + errbits |= CAN_ERROR_PROTOCOL; + data[2] |= CAN_ERROR2_BIT0; + } + + if ((psr & FDCAN_PSR_LEC(FDCAN_PSR_EC_BIT1_ERROR)) != 0) + { + /* Bit1 Error */ + + errbits |= CAN_ERROR_PROTOCOL; + data[2] |= CAN_ERROR2_BIT1; + } + + if ((psr & FDCAN_PSR_LEC(FDCAN_PSR_EC_CRC_ERROR)) != 0) + { + /* Receive CRC Error */ + + errbits |= CAN_ERROR_PROTOCOL; + data[3] |= (CAN_ERROR3_CRCSEQ | CAN_ERROR3_CRCDEL); + } + + if ((psr & FDCAN_PSR_LEC(FDCAN_PSR_EC_NO_CHANGE)) != 0) + { + /* No Change in Error */ + + errbits |= CAN_ERROR_PROTOCOL; + data[2] |= CAN_ERROR2_UNSPEC; + } + } + } + + if ((status & FDCAN_INT_PED) != 0) + { + /* Protocol Error in Data Phase */ + + if ((psr & FDCAN_PSR_DLEC_MASK) != 0) + { + /* Error code present */ + + if ((psr & FDCAN_PSR_DLEC(FDCAN_PSR_EC_STUFF_ERROR)) != 0) + { + /* Stuff Error */ + + errbits |= CAN_ERROR_PROTOCOL; + data[2] |= CAN_ERROR2_STUFF; + } + + if ((psr & FDCAN_PSR_DLEC(FDCAN_PSR_EC_FORM_ERROR)) != 0) + { + /* Format Error */ + + errbits |= CAN_ERROR_PROTOCOL; + data[2] |= CAN_ERROR2_FORM; + } + + if ((psr & FDCAN_PSR_DLEC(FDCAN_PSR_EC_ACK_ERROR)) != 0) + { + /* Acknowledge Error */ + + errbits |= CAN_ERROR_NOACK; + } + + if ((psr & FDCAN_PSR_DLEC(FDCAN_PSR_EC_BIT0_ERROR)) != 0) + { + /* Bit0 Error */ + + errbits |= CAN_ERROR_PROTOCOL; + data[2] |= CAN_ERROR2_BIT0; + } + + if ((psr & FDCAN_PSR_DLEC(FDCAN_PSR_EC_BIT1_ERROR)) != 0) + { + /* Bit1 Error */ + + errbits |= CAN_ERROR_PROTOCOL; + data[2] |= CAN_ERROR2_BIT1; + } + + if ((psr & FDCAN_PSR_DLEC(FDCAN_PSR_EC_CRC_ERROR)) != 0) + { + /* Receive CRC Error */ + + errbits |= CAN_ERROR_PROTOCOL; + data[3] |= (CAN_ERROR3_CRCSEQ | CAN_ERROR3_CRCDEL); + } + + if ((psr & FDCAN_PSR_DLEC(FDCAN_PSR_EC_NO_CHANGE)) != 0) + { + /* No Change in Error */ + + errbits |= CAN_ERROR_PROTOCOL; + data[2] |= CAN_ERROR2_UNSPEC; + } + } + } + + if ((status & FDCAN_INT_BO) != 0) + { + /* Bus_Off Status changed */ + + if ((psr & FDCAN_PSR_BO) != 0) + { + errbits |= CAN_ERROR_BUSOFF; + } + else + { + errbits |= CAN_ERROR_RESTARTED; + } + } + + if ((status & (FDCAN_INT_RF0L | FDCAN_INT_RF1L)) != 0) + { + /* Receive FIFO 0/1 Message Lost + * Receive FIFO 1 Message Lost + */ + + errbits |= CAN_ERROR_CONTROLLER; + data[1] |= CAN_ERROR1_RXOVERFLOW; + } + + if ((status & FDCAN_INT_TEFL) != 0) + { + /* Tx Event FIFO Element Lost */ + + errbits |= CAN_ERROR_CONTROLLER; + data[1] |= CAN_ERROR1_TXOVERFLOW; + } + + if ((status & FDCAN_INT_TOO) != 0) + { + /* Timeout Occurred */ + + errbits |= CAN_ERROR_TXTIMEOUT; + } + + if ((status & (FDCAN_INT_MRAF | FDCAN_INT_ELO)) != 0) + { + /* Message RAM Access Failure + * Error Logging Overflow + */ + + errbits |= CAN_ERROR_CONTROLLER; + data[1] |= CAN_ERROR1_UNSPEC; + } + + if (errbits != 0) + { + /* Format the CAN header for the error report. */ + + hdr.ch_id = errbits; + hdr.ch_dlc = CAN_ERROR_DLC; + hdr.ch_rtr = 0; + hdr.ch_error = 1; +#ifdef CONFIG_CAN_EXTID + hdr.ch_extid = 0; +#endif + hdr.ch_tcf = 0; + + /* And provide the error report to the upper half logic */ + + ret = can_receive(dev, &hdr, data); + if (ret < 0) + { + canerr("ERROR: can_receive failed: %d\n", ret); + } + } +} +#endif /* CONFIG_CAN_ERRORS */ + +/**************************************************************************** + * Name: fdcan_receive + * + * Description: + * Receive an FDCAN messages + * + * Input Parameters: + * dev - CAN-common state data + * rxbuffer - The RX buffer containing the received messages + * nwords - The length of the RX buffer (element size in words). + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void fdcan_receive(struct can_dev_s *dev, + volatile uint32_t *rxbuffer, + unsigned long nwords) +{ + struct can_hdr_s hdr; + int ret = 0; + + fdcan_dumprxregs(dev->cd_priv, "Before receive"); + + /* Format the CAN header */ + + /* Word R0 contains the CAN ID */ + +#ifdef CONFIG_CAN_ERRORS + hdr.ch_error = 0; +#endif + hdr.ch_tcf = 0; + + /* Extract the RTR bit */ + + hdr.ch_rtr = ((rxbuffer[0] & BUFFER_R0_RTR) != 0); + +#ifdef CONFIG_CAN_EXTID + if ((rxbuffer[0] & BUFFER_R0_XTD) != 0) + { + /* Save the extended ID of the newly received message */ + + hdr.ch_id = (rxbuffer[0] & BUFFER_R0_EXTID_MASK) >> + BUFFER_R0_EXTID_SHIFT; + hdr.ch_extid = 1; + } + else + { + hdr.ch_id = (rxbuffer[0] & BUFFER_R0_STDID_MASK) >> + BUFFER_R0_STDID_SHIFT; + hdr.ch_extid = 0; + } + +#else + if ((rxbuffer[0] & BUFFER_R0_XTD) != 0) + { + /* Drop any messages with extended IDs */ + + canerr("ERROR: Received message with extended identifier. Dropped\n"); + + return; + } + + /* Save the standard ID of the newly received message */ + + hdr.ch_id = (rxbuffer[0] & BUFFER_R0_STDID_MASK) >> BUFFER_R0_STDID_SHIFT; +#endif + + /* Word R1 contains the DLC and timestamp */ + + hdr.ch_dlc = (rxbuffer[1] & BUFFER_R1_DLC_MASK) >> BUFFER_R1_DLC_SHIFT; + +#ifdef CONFIG_CAN_FD + /* CAN FD format */ + + hdr.ch_esi = ((rxbuffer[0] & BUFFER_R0_ESI) != 0); + hdr.ch_edl = ((rxbuffer[1] & BUFFER_R1_FDF) != 0); + hdr.ch_brs = ((rxbuffer[1] & BUFFER_R1_BRS) != 0); +#else + if ((rxbuffer[1] & BUFFER_R1_FDF) != 0) + { + /* Drop any FD CAN messages if not supported */ + + canerr("ERROR: Received CAN FD message. Dropped\n"); + + return; + } +#endif + + /* And provide the CAN message to the upper half logic */ + + ret = can_receive(dev, &hdr, (uint8_t *)&rxbuffer[2]); + if (ret < 0) + { + canerr("ERROR: can_receive failed: %d\n", ret); + } +} + +/**************************************************************************** + * Name: fdcan_interrupt + * + * Description: + * Common FDCAN interrupt handler + * + * Input Parameters: + * dev - CAN-common state data + * + * Returned Value: + * None + * + ****************************************************************************/ + +static int fdcan_interrupt(int irq, void *context, void *arg) +{ + struct can_dev_s *dev = (struct can_dev_s *)arg; + struct stm32_fdcan_s *priv = NULL; + const struct stm32_config_s *config = NULL; + uint32_t ir = 0; + uint32_t ie = 0; + uint32_t pending = 0; + uint32_t regval = 0; + uint32_t psr = 0; + unsigned int nelem = 0; + unsigned int ndx = 0; + + DEBUGASSERT(dev != NULL); + priv = dev->cd_priv; + DEBUGASSERT(priv && priv->config); + config = priv->config; + + /* Get the set of pending interrupts. */ + + ir = fdcan_getreg(priv, STM32_FDCAN_IR_OFFSET); + ie = fdcan_getreg(priv, STM32_FDCAN_IE_OFFSET); + + pending = (ir & ie); + + /* Check for any errors */ + + if ((pending & FDCAN_ANYERR_INTS) != 0) + { + /* Check for common errors */ + + if ((pending & FDCAN_CMNERR_INTS) != 0) + { + canerr("ERROR: Common %08" PRIx32 "\n", + pending & FDCAN_CMNERR_INTS); + + /* When a protocol error occurs, the problem is recorded in + * the LEC/DLEC fields of the PSR register. In lieu of + * separate interrupt flags for each error, the hardware + * groups protocol errors under a single interrupt each for + * arbitration and data phases. + * + * These errors have a tendency to flood the system with + * interrupts, so they are disabled here until we get a + * successful transfer/receive on the hardware + */ + + psr = fdcan_getreg(priv, STM32_FDCAN_PSR_OFFSET); + + if ((psr & FDCAN_PSR_LEC_MASK) != 0) + { + canerr("ERROR: PSR %08" PRIx32 "\n", psr); + ie &= ~(FDCAN_INT_PEA | FDCAN_INT_PED); + fdcan_putreg(priv, STM32_FDCAN_IE_OFFSET, ie); + caninfo("disabled protocol error interrupts\n"); + } + + /* Clear the error indications */ + + fdcan_putreg(priv, STM32_FDCAN_IR_OFFSET, FDCAN_CMNERR_INTS); + } + + /* Check for transmission errors */ + + if ((pending & FDCAN_TXERR_INTS) != 0) + { + canerr("ERROR: TX %08" PRIx32 "\n", + pending & FDCAN_TXERR_INTS); + + /* An Acknowledge-Error will occur if for example the device + * is not connected to the bus. + * + * The CAN-Standard states that the Chip has to retry the + * message forever, which will produce an ACKE every time. + * To prevent this Interrupt-Flooding and the high CPU-Load + * we disable the ACKE here as long we didn't transfer at + * least one message successfully (see FDCAN_INT_TC below). + */ + + /* Clear the error indications */ + + fdcan_putreg(priv, STM32_FDCAN_IR_OFFSET, FDCAN_TXERR_INTS); + } + + /* Check for reception errors */ + + if ((pending & FDCAN_RXERR_INTS) != 0) + { + canerr("ERROR: RX %08" PRIx32 "\n", + pending & FDCAN_RXERR_INTS); + + /* To prevent Interrupt-Flooding the current active + * RX error interrupts are disabled. After successfully + * receiving at least one CAN packet all RX error interrupts + * are turned back on. + * + * The Interrupt-Flooding can for example occur if the + * configured CAN speed does not match the speed of the other + * CAN nodes in the network. + */ + + ie &= ~(pending & FDCAN_RXERR_INTS); + fdcan_putreg(priv, STM32_FDCAN_IE_OFFSET, ie); + + /* Clear the error indications */ + + fdcan_putreg(priv, STM32_FDCAN_IR_OFFSET, FDCAN_RXERR_INTS); + } + +#ifdef CONFIG_CAN_ERRORS + /* Report errors */ + + fdcan_error(dev, pending & FDCAN_ANYERR_INTS); +#endif + } + + /* Check for successful completion of a transmission */ + + if ((pending & FDCAN_INT_TC) != 0) + { + /* Check if we have disabled the ACKE in the error-handling above + * (see FDCAN_TXERR_INTS) to prevent Interrupt-Flooding and + * re-enable the error interrupt here again. + */ + + if ((ie & (FDCAN_INT_PEA | FDCAN_INT_PED)) == 0) + { + ie |= (FDCAN_INT_PEA | FDCAN_INT_PED); + fdcan_putreg(priv, STM32_FDCAN_IE_OFFSET, ie); + caninfo("Re-enabled protocol error interrupts\n"); + } + + /* Clear the pending TX completion interrupt (and all + * other TX-related interrupts) + */ + + fdcan_putreg(priv, STM32_FDCAN_IR_OFFSET, priv->txints); + + /* Check all TX buffers */ + + regval = fdcan_getreg(priv, STM32_FDCAN_TXBTO_OFFSET); + for (ndx = 0; ndx < config->ntxfifoq; ndx++) + { + if ((regval & (1 << ndx)) != 0) + { + /* Tell the upper half that the transfer is finished. */ + + can_txdone(dev); + } + } + } + else if ((pending & priv->txints) != 0) + { + /* Clear unhandled TX events */ + + fdcan_putreg(priv, STM32_FDCAN_IR_OFFSET, priv->txints); + } + + /* Clear the RX FIFO1 new message interrupt */ + + fdcan_putreg(priv, STM32_FDCAN_IR_OFFSET, FDCAN_INT_RF1N); + pending &= ~FDCAN_INT_RF1N; + + /* We treat RX FIFO1 as the "high priority" queue: We will process + * all messages in RX FIFO1 before processing any message from RX + * FIFO0. + */ + + for (; ; ) + { + /* Check if there is anything in RX FIFO1 */ + + regval = fdcan_getreg(priv, STM32_FDCAN_RXF1S_OFFSET); + nelem = (regval & FDCAN_RXFS_FFL_MASK) >> FDCAN_RXFS_FFL_SHIFT; + if (nelem == 0) + { + /* Break out of the loop if RX FIFO1 is empty */ + + break; + } + + /* Clear the RX FIFO1 interrupt (and all other FIFO1-related + * interrupts) + */ + + /* Handle the newly received message in FIFO1 */ + + ndx = (regval & FDCAN_RXFS_FGI_MASK) >> FDCAN_RXFS_FGI_SHIFT; + + if ((regval & FDCAN_RXFS_RFL) != 0) + { + canerr("ERROR: Message lost: %08" PRIx32 "\n", regval); + } + else + { + fdcan_receive(dev, + config->msgram.rxfifo1 + + (ndx * priv->config->rxfifo1esize), + priv->config->rxfifo1esize); + + /* Turning back on all configured RX error interrupts */ + + ie |= (priv->rxints & FDCAN_RXERR_INTS); + fdcan_putreg(priv, STM32_FDCAN_IE_OFFSET, ie); + } + + /* Acknowledge reading the FIFO entry */ + + fdcan_putreg(priv, STM32_FDCAN_RXF1A_OFFSET, ndx); + } + + /* Check for successful reception of a new message in RX FIFO0 */ + + /* Clear the RX FIFO0 new message interrupt */ + + fdcan_putreg(priv, STM32_FDCAN_IR_OFFSET, FDCAN_INT_RF0N); + pending &= ~FDCAN_INT_RF0N; + + /* Check if there is anything in RX FIFO0 */ + + regval = fdcan_getreg(priv, STM32_FDCAN_RXF0S_OFFSET); + nelem = (regval & FDCAN_RXFS_FFL_MASK) >> FDCAN_RXFS_FFL_SHIFT; + if (nelem > 0) + { + /* Handle the newly received message in FIFO0 */ + + ndx = (regval & FDCAN_RXFS_FGI_MASK) >> FDCAN_RXFS_FGI_SHIFT; + + if ((regval & FDCAN_RXFS_RFL) != 0) + { + canerr("ERROR: Message lost: %08" PRIx32 "\n", regval); + } + else + { + fdcan_receive(dev, + config->msgram.rxfifo0 + + (ndx * priv->config->rxfifo0esize), + priv->config->rxfifo0esize); + + /* Turning back on all configured RX error interrupts */ + + ie |= (priv->rxints & FDCAN_RXERR_INTS); + fdcan_putreg(priv, STM32_FDCAN_IE_OFFSET, ie); + } + + /* Acknowledge reading the FIFO entry */ + + fdcan_putreg(priv, STM32_FDCAN_RXF0A_OFFSET, ndx); + } + + /* Clear unhandled RX interrupts */ + + if ((pending & priv->rxints) != 0) + { + fdcan_putreg(priv, STM32_FDCAN_IR_OFFSET, priv->rxints); + } + + return OK; +} + +/**************************************************************************** + * Name: fdcan_hw_initialize + * + * Description: + * FDCAN hardware initialization + * + * Input Parameters: + * priv - A pointer to the private data structure for this FDCAN peripheral + * + * Returned Value: + * Zero on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int fdcan_hw_initialize(struct stm32_fdcan_s *priv) +{ + const struct stm32_config_s *config = priv->config; + volatile uint32_t *msgram = NULL; + uint32_t regval = 0; + uint32_t cntr = 0; + + caninfo("FDCAN%d\n", config->port); + + /* Clean message RAM */ + + msgram = config->msgram.stdfilters; + cntr = (FDCAN_MSGRAM_WORDS + 1); + while (cntr > 0) + { + *msgram++ = 0; + cntr--; + } + + /* Configure FDCAN pins */ + + stm32_configgpio(config->rxpinset); + stm32_configgpio(config->txpinset); + + /* Re-enabled device if previously disabled in fdcan_shutdown() */ + + if (priv->state == FDCAN_STATE_DISABLED) + { + /* Reset Clock Stop Request bit */ + + regval = fdcan_getreg(priv, STM32_FDCAN_CCCR_OFFSET); + regval &= ~FDCAN_CCCR_CSR; + fdcan_putreg(priv, STM32_FDCAN_CCCR_OFFSET, regval); + + /* Wait for Clock Stop Acknowledge bit reset to indicate + * device is operational + */ + + while ((fdcan_getreg(priv, STM32_FDCAN_CCCR_OFFSET) & FDCAN_CCCR_CSA) + != 0); + } + + /* Enable the Initialization state */ + + regval = fdcan_getreg(priv, STM32_FDCAN_CCCR_OFFSET); + regval |= FDCAN_CCCR_INIT; + fdcan_putreg(priv, STM32_FDCAN_CCCR_OFFSET, regval); + + /* Wait for initialization mode to take effect */ + + while ((fdcan_getreg(priv, STM32_FDCAN_CCCR_OFFSET) & FDCAN_CCCR_INIT) + == 0); + + /* Enable writing to configuration registers */ + + regval = fdcan_getreg(priv, STM32_FDCAN_CCCR_OFFSET); + regval |= FDCAN_CCCR_CCE; + fdcan_putreg(priv, STM32_FDCAN_CCCR_OFFSET, regval); + + /* Global Filter Configuration: + * + * ANFS=0: Store all non matching standard frame in RX FIFO0 + * ANFE=0: Store all non matching extended frame in RX FIFO0 + */ + + regval = FDCAN_RXGFC_ANFE_RX_FIFO0 | FDCAN_RXGFC_ANFS_RX_FIFO0; + fdcan_putreg(priv, STM32_FDCAN_RXGFC_OFFSET, regval); + + /* Extended ID Filter AND mask */ + + fdcan_putreg(priv, STM32_FDCAN_XIDAM_OFFSET, 0x1fffffff); + + /* Disable all interrupts */ + + fdcan_putreg(priv, STM32_FDCAN_IE_OFFSET, 0); + fdcan_putreg(priv, STM32_FDCAN_TXBTIE_OFFSET, 0); + + /* All interrupts directed to Line 0. But disable both interrupt lines 0 + * and 1 for now. + * + * REVISIT: Only interrupt line 0 is used by this driver. + */ + + fdcan_putreg(priv, STM32_FDCAN_ILS_OFFSET, 0); + fdcan_putreg(priv, STM32_FDCAN_ILE_OFFSET, 0); + + /* Clear all pending interrupts. */ + + fdcan_putreg(priv, STM32_FDCAN_IR_OFFSET, FDCAN_INT_ALL); + + /* Configure FDCAN bit timing */ + + fdcan_putreg(priv, STM32_FDCAN_NBTP_OFFSET, priv->nbtp); + fdcan_putreg(priv, STM32_FDCAN_DBTP_OFFSET, priv->dbtp); + + /* Configure message RAM starting addresses and sizes. */ + + regval = FDCAN_RXGFC_LSS(config->nstdfilters); + regval |= FDCAN_RXGFC_LSE(config->nextfilters); + fdcan_putreg(priv, STM32_FDCAN_RXGFC_OFFSET, regval); + + /* Dump RAM layout */ + + fdcan_dumpramlayout(priv); + + /* Configure Message Filters */ + + /* Disable all standard filters */ + + msgram = config->msgram.stdfilters; + cntr = config->nstdfilters; + while (cntr > 0) + { + *msgram++ = STDFILTER_S0_SFEC_DISABLE; + cntr--; + } + + /* Disable all extended filters */ + + msgram = config->msgram.extfilters; + cntr = config->nextfilters; + while (cntr > 0) + { + *msgram = EXTFILTER_F0_EFEC_DISABLE; + msgram = msgram + 2; + cntr--; + } + + /* Input clock divider configuration */ + + regval = FDCANCLK_PDIV; + fdcan_putreg(priv, STM32_FDCAN_CKDIV_OFFSET, regval); + + /* CC control register */ + + regval = fdcan_getreg(priv, STM32_FDCAN_CCCR_OFFSET); + regval &= ~(FDCAN_CCCR_NISO | FDCAN_CCCR_FDOE | FDCAN_CCCR_BRSE); + + /* Select ISO11898-1 or Non ISO Bosch CAN FD Specification V1.0 */ + + switch (config->format) + { + case FDCAN_ISO11898_1_FORMAT: + { + break; + } + + case FDCAN_NONISO_BOSCH_V1_FORMAT: + { + regval |= FDCAN_CCCR_NISO; + break; + } + + default: + { + return -EINVAL; + } + } + + /* Select Classic CAN mode or FD mode with or without fast bit rate + * switching + */ + + switch (config->mode) + { + case FDCAN_CLASSIC_MODE: + { + break; + } + +#ifdef CONFIG_CAN_FD + case FDCAN_FD_MODE: + { + regval |= FDCAN_CCCR_FDOE; + break; + } + + case FDCAN_FD_BRS_MODE: + { + regval |= (FDCAN_CCCR_FDOE | FDCAN_CCCR_BRSE); + break; + } +#endif + + default: + { + return -EINVAL; + } + } + + /* Set the initial CAN mode */ + + fdcan_putreg(priv, STM32_FDCAN_CCCR_OFFSET, regval); + + /* Enable FIFO/Queue mode */ + + regval = fdcan_getreg(priv, STM32_FDCAN_TXBC_OFFSET); +#ifdef CONFIG_STM32_FDCAN_QUEUE_MODE + regval |= FDCAN_TXBC_TFQM; +#else + regval &= ~FDCAN_TXBC_TFQM; +#endif + fdcan_putreg(priv, STM32_FDCAN_TXBC_OFFSET, regval); + +#ifdef STM32_FDCAN_LOOPBACK + /* Is loopback mode selected for this peripheral? */ + + if (config->loopback) + { + /* FDCAN_CCCR_TEST - Test mode enable + * FDCAN_CCCR_MON - Bus monitoring mode (for internal loopback) + * FDCAN_TEST_LBCK - Loopback mode + */ + + regval = fdcan_getreg(priv, STM32_FDCAN_CCCR_OFFSET); + regval |= (FDCAN_CCCR_TEST | FDCAN_CCCR_MON); + fdcan_putreg(priv, STM32_FDCAN_CCCR_OFFSET, regval); + + regval = fdcan_getreg(priv, STM32_FDCAN_TEST_OFFSET); + regval |= FDCAN_TEST_LBCK; + fdcan_putreg(priv, STM32_FDCAN_TEST_OFFSET, regval); + } +#endif + + /* Configure interrupt lines */ + + /* Select RX-related interrupts */ + + priv->rxints = FDCAN_RXFIFO_INTS; + + /* Select TX-related interrupts */ + + priv->txints = FDCAN_TXFIFOQ_INTS; + + /* Direct all interrupts to Line 0. + * + * Bits in the ILS register correspond to each FDCAN interrupt; A bit + * set to '1' is directed to interrupt line 1; a bit cleared to '0' + * is directed interrupt line 0. + * + * REVISIT: Nothing is done here. Only interrupt line 0 is used by + * this driver and ILS was already cleared above. + */ + + /* Enable only interrupt line 0. */ + + fdcan_putreg(priv, STM32_FDCAN_ILE_OFFSET, FDCAN_ILE_EINT0); + + /* Disable initialization mode to enable normal operation */ + + regval = fdcan_getreg(priv, STM32_FDCAN_CCCR_OFFSET); + regval &= ~FDCAN_CCCR_INIT; + fdcan_putreg(priv, STM32_FDCAN_CCCR_OFFSET, regval); + + return OK; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_fdcaninitialize + * + * Description: + * Initialize the selected FDCAN port + * + * Input Parameters: + * port - Port number (for hardware that has multiple FDCAN interfaces), + * 1=FDCAN1. + * + * Returned Value: + * Valid CAN device structure reference on success; a NULL on failure + * + ****************************************************************************/ + +struct can_dev_s *stm32_fdcaninitialize(int port) +{ + struct can_dev_s *dev = NULL; + struct stm32_fdcan_s *priv = NULL; + const struct stm32_config_s *config = NULL; + + caninfo("FDCAN%d\n", port); + + /* Select FDCAN peripheral to be initialized */ + +#ifdef CONFIG_STM32_FDCAN1 + if (port == FDCAN1) + { + /* Select the FDCAN1 device structure */ + + dev = &g_fdcan1dev; + priv = &g_fdcan1priv; + config = &g_fdcan1const; + } + else +#endif + { + canerr("ERROR: Unsupported port %d\n", port); + return NULL; + } + + /* Perform one time data initialization */ + + memset(priv, 0, sizeof(struct stm32_fdcan_s)); + priv->config = config; + + /* Set the initial bit timing. This might change subsequently + * due to IOCTL command processing. + */ + + priv->nbtp = config->nbtp; + priv->dbtp = config->dbtp; + + dev->cd_ops = &g_fdcanops; + dev->cd_priv = (void *)priv; + + /* And put the hardware in the initial state */ + + fdcan_reset(dev); + + return dev; +} diff --git a/arch/arm/src/common/stm32/stm32_fdcan_m0_v1_sock.c b/arch/arm/src/common/stm32/stm32_fdcan_m0_v1_sock.c new file mode 100644 index 0000000000000..d118271cf97dd --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_fdcan_m0_v1_sock.c @@ -0,0 +1,2991 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_fdcan_m0_v1_sock.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include +#include +#include + +#include "arm_internal.h" +#include "stm32_fdcan.h" +#include "hardware/stm32_pinmap.h" +#include "stm32_gpio.h" +#include "stm32_rcc.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Pool configuration *******************************************************/ + +#define POOL_SIZE (1) + +/* Work queue support is required. */ + +#if !defined(CONFIG_SCHED_WORKQUEUE) +# error Work queue support is required +#endif + +/* The low priority work queue is preferred. If it is not enabled, LPWORK + * will be the same as HPWORK. + * + * NOTE: However, the network should NEVER run on the high priority work + * queue! That queue is intended only to service short back end interrupt + * processing that never suspends. Suspending the high priority work queue + * may bring the system to its knees! + */ + +#define CANWORK LPWORK + +/* Clock source *************************************************************/ + +#define FDCANCLK_PDIV (0) + +#if FDCANCLK_PDIV == 0 +# define STM32_FDCANCLK_FREQUENCY (STM32_FDCAN_FREQUENCY / (1)) +#else +# define STM32_FDCANCLK_FREQUENCY (STM32_FDCAN_FREQUENCY / (2 * FDCANCLK_PDIV)) +#endif + +/* General Configuration ****************************************************/ + +#if defined(CONFIG_ARCH_CHIP_STM32C0) + +/* FDCAN Message RAM */ + +# define FDCAN_MSGRAM_WORDS (212) +# define STM32_CANRAM1_BASE (STM32_CANRAM_BASE + 0x0000) + +# ifdef CONFIG_STM32_FDCAN1 +# define FDCAN1_STDFILTER_SIZE (28) +# define FDCAN1_EXTFILTER_SIZE (8) +# define FDCAN1_RXFIFO0_SIZE (3) +# define FDCAN1_RXFIFO1_SIZE (3) +# define FDCAN1_TXEVENTFIFO_SIZE (3) +# define FDCAN1_TXFIFIOQ_SIZE (3) + +# define FDCAN1_STDFILTER_WORDS (28) +# define FDCAN1_EXTFILTER_WORDS (16) +# define FDCAN1_RXFIFO0_WORDS (54) +# define FDCAN1_RXFIFO1_WORDS (54) +# define FDCAN1_TXEVENTFIFO_WORDS (6) +# define FDCAN1_TXFIFIOQ_WORDS (54) +# endif +#else +# error +#endif + +/* FDCAN1 Configuration *****************************************************/ + +#ifdef CONFIG_STM32_FDCAN1 + +/* Bit timing */ + +# define FDCAN1_NTSEG1 (CONFIG_STM32_FDCAN1_NTSEG1 - 1) +# define FDCAN1_NTSEG2 (CONFIG_STM32_FDCAN1_NTSEG2 - 1) +# define FDCAN1_NBRP ((STM32_FDCANCLK_FREQUENCY / \ + ((FDCAN1_NTSEG1 + FDCAN1_NTSEG2 + 3) * \ + CONFIG_STM32_FDCAN1_BITRATE)) - 1) +# define FDCAN1_NSJW (CONFIG_STM32_FDCAN1_NSJW - 1) + +# if FDCAN1_NTSEG1 > FDCAN_NBTP_NTSEG1_MAX +# error Invalid FDCAN1 NTSEG1 +# endif +# if FDCAN1_NTSEG2 > FDCAN_NBTP_NTSEG2_MAX +# error Invalid FDCAN1 NTSEG2 +# endif +# if FDCAN1_NSJW > FDCAN_NBTP_NSJW_MAX +# error Invalid FDCAN1 NSJW +# endif +# if FDCAN1_NBRP > FDCAN_NBTP_NBRP_MAX +# error Invalid FDCAN1 NBRP +# endif + +# ifdef CONFIG_STM32_FDCAN1_FD_BRS +# define FDCAN1_DTSEG1 (CONFIG_STM32_FDCAN1_DTSEG1 - 1) +# define FDCAN1_DTSEG2 (CONFIG_STM32_FDCAN1_DTSEG2 - 1) +# define FDCAN1_DBRP ((STM32_FDCANCLK_FREQUENCY / \ + ((FDCAN1_DTSEG1 + FDCAN1_DTSEG2 + 3) * \ + CONFIG_STM32_FDCAN1_DBITRATE)) - 1) +# define FDCAN1_DSJW (CONFIG_STM32_FDCAN1_DSJW - 1) +# else +# define FDCAN1_DTSEG1 1 +# define FDCAN1_DTSEG2 1 +# define FDCAN1_DBRP 1 +# define FDCAN1_DSJW 1 +# endif /* CONFIG_STM32_FDCAN1_FD_BRS */ + +# if FDCAN1_DTSEG1 > FDCAN_DBTP_DTSEG1_MAX +# error Invalid FDCAN1 DTSEG1 +# endif +# if FDCAN1_DTSEG2 > FDCAN_DBTP_DTSEG2_MAX +# error Invalid FDCAN1 DTSEG2 +# endif +# if FDCAN1_DBRP > FDCAN_DBTP_DBRP_MAX +# error Invalid FDCAN1 DBRP +# endif +# if FDCAN1_DSJW > FDCAN_DBTP_DSJW_MAX +# error Invalid FDCAN1 DSJW +# endif + +/* FDCAN1 Message RAM Configuration *****************************************/ + +/* FDCAN1 Message RAM Layout */ + +# define FDCAN1_STDFILTER_INDEX 0 +# define FDCAN1_EXTFILTERS_INDEX (FDCAN1_STDFILTER_INDEX + FDCAN1_STDFILTER_WORDS) +# define FDCAN1_RXFIFO0_INDEX (FDCAN1_EXTFILTERS_INDEX + FDCAN1_EXTFILTER_WORDS) +# define FDCAN1_RXFIFO1_INDEX (FDCAN1_RXFIFO0_INDEX + FDCAN1_RXFIFO0_WORDS) +# define FDCAN1_TXEVENTFIFO_INDEX (FDCAN1_RXFIFO1_INDEX + FDCAN1_RXFIFO1_WORDS) +# define FDCAN1_TXFIFOQ_INDEX (FDCAN1_TXEVENTFIFO_INDEX + FDCAN1_TXEVENTFIFO_WORDS) +# define FDCAN1_MSGRAM_WORDS (FDCAN1_TXFIFOQ_INDEX + FDCAN1_TXFIFIOQ_WORDS) + +#endif /* CONFIG_STM32_FDCAN1 */ + +/* Loopback mode */ + +#undef STM32_FDCAN_LOOPBACK +#if defined(CONFIG_STM32_FDCAN1_LOOPBACK) +# define STM32_FDCAN_LOOPBACK 1 +#endif + +/* Interrupts ***************************************************************/ + +/* Common interrupts + * + * FDCAN_INT_TSW - Timestamp Wraparound + * FDCAN_INT_MRAF - Message RAM Access Failure + * FDCAN_INT_TOO - Timeout Occurred + * FDCAN_INT_ELO - Error Logging Overflow + * FDCAN_INT_EP - Error Passive + * FDCAN_INT_EW - Warning Status + * FDCAN_INT_BO - Bus_Off Status + * FDCAN_INT_WDI - Watchdog Interrupt + * FDCAN_INT_PEA - Protocol Error in Arbritration Phase + * FDCAN_INT_PED - Protocol Error in Data Phase + */ + +#define FDCAN_CMNERR_INTS (FDCAN_INT_MRAF | FDCAN_INT_TOO | FDCAN_INT_EP | \ + FDCAN_INT_BO | FDCAN_INT_WDI | FDCAN_INT_PEA | \ + FDCAN_INT_PED) + +/* RXFIFO mode interrupts + * + * FDCAN_INT_RF0N - Receive FIFO 0 New Message + * FDCAN_INT_RF0F - Receive FIFO 0 Full + * FDCAN_INT_RF0L - Receive FIFO 0 Message Lost + * FDCAN_INT_RF1N - Receive FIFO 1 New Message + * FDCAN_INT_RF1F - Receive FIFO 1 Full + * FDCAN_INT_RF1L - Receive FIFO 1 Message Lost + * FDCAN_INT_HPM - High Priority Message Received + * + */ + +#define FDCAN_RXFIFO0_INTS (FDCAN_INT_RF0N | FDCAN_INT_RF0L) +#define FDCAN_RXFIFO1_INTS (FDCAN_INT_RF1N | FDCAN_INT_RF1L) + +#define FDCAN_RXERR_INTS (FDCAN_INT_RF0L | FDCAN_INT_RF1L) + +/* TX FIFOQ mode interrupts + * + * FDCAN_INT_TFE - Tx FIFO Empty + * + * TX Event FIFO interrupts + * + * FDCAN_INT_TEFN - Tx Event FIFO New Entry + * FDCAN_INT_TEFF - Tx Event FIFO Full + * FDCAN_INT_TEFL - Tx Event FIFO Element Lost + * + * Mode-independent TX-related interrupts + * + * FDCAN_INT_TC - Transmission Completed + * FDCAN_INT_TCF - Transmission Cancellation Finished + */ + +#define FDCAN_TXCOMMON_INTS (FDCAN_INT_TC | FDCAN_INT_TCF) +#define FDCAN_TXFIFOQ_INTS (FDCAN_INT_TFE | FDCAN_TXCOMMON_INTS) +#define FDCAN_TXEVFIFO_INTS (FDCAN_INT_TEFN | FDCAN_INT_TEFF | \ + FDCAN_INT_TEFL) + +#define FDCAN_TXERR_INTS (FDCAN_INT_TEFL | FDCAN_INT_PEA | FDCAN_INT_PED) + +/* Common-, TX- and RX-Error-Mask */ + +#define FDCAN_ANYERR_INTS (FDCAN_CMNERR_INTS | FDCAN_RXERR_INTS | FDCAN_TXERR_INTS) + +/* Convenience macro for clearing all interrupts */ + +#define FDCAN_INT_ALL 0x3fcfffff + +/* Debug ********************************************************************/ + +/* Debug configurations that may be enabled just for testing FDCAN */ + +#ifndef CONFIG_DEBUG_NET_INFO +# undef CONFIG_STM32_FDCAN_REGDEBUG +#endif + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/* CAN frame format */ + +enum stm32_frameformat_e +{ + FDCAN_ISO11898_1_FORMAT = 0, /* Frame format according to ISO11898-1 */ + FDCAN_NONISO_BOSCH_V1_FORMAT = 1 /* Frame format according to Bosch CAN FD V1.0 */ +}; + +/* CAN mode of operation */ + +enum stm32_canmode_e +{ + FDCAN_CLASSIC_MODE = 0, /* Classic CAN operation */ +#ifdef CONFIG_NET_CAN_CANFD + FDCAN_FD_MODE = 1, /* CAN FD operation */ + FDCAN_FD_BRS_MODE = 2 /* CAN FD operation with bit rate switching */ +#endif +}; + +/* CAN driver state */ + +enum can_state_s +{ + FDCAN_STATE_UNINIT = 0, /* Not yet initialized */ + FDCAN_STATE_RESET, /* Initialized, reset state */ + FDCAN_STATE_SETUP, /* fdcan_setup() has been called */ + FDCAN_STATE_DISABLED /* Disabled by a fdcan_shutdown() */ +}; + +/* This structure describes the FDCAN message RAM layout */ + +struct stm32_msgram_s +{ + volatile uint32_t *stdfilters; /* Standard filters */ + volatile uint32_t *extfilters; /* Extended filters */ + volatile uint32_t *rxfifo0; /* RX FIFO0 */ + volatile uint32_t *rxfifo1; /* RX FIFO1 */ + volatile uint32_t *txeventfifo; /* TX event FIFO */ + volatile uint32_t *txfifoq; /* TX FIFO queue */ +}; + +/* This structure provides the constant configuration of a FDCAN peripheral */ + +struct stm32_config_s +{ + uint32_t rxpinset; /* RX pin configuration */ + uint32_t txpinset; /* TX pin configuration */ + uintptr_t base; /* Base address of the FDCAN registers */ + uint32_t baud; /* Configured baud */ + uint32_t nbtp; /* Nominal bit timing/prescaler register setting */ + uint32_t dbtp; /* Data bit timing/prescaler register setting */ + uint8_t port; /* FDCAN port number (1 or 2) */ + uint8_t irq0; /* FDCAN peripheral IRQ number for interrupt line 0 */ + uint8_t irq1; /* FDCAN peripheral IRQ number for interrupt line 1 */ + uint8_t mode; /* See enum stm32_canmode_e */ + uint8_t format; /* See enum stm32_frameformat_e */ + uint8_t nstdfilters; /* Number of standard filters */ + uint8_t nextfilters; /* Number of extended filters */ + uint8_t nrxfifo0; /* Number of RX FIFO0 elements */ + uint8_t nrxfifo1; /* Number of RX FIFO1 elements */ + uint8_t ntxeventfifo; /* Number of TXevent FIFO elements */ + uint8_t ntxfifoq; /* Number of TX FIFO queue elements */ + uint8_t rxfifo0esize; /* RX FIFO0 element size (words) */ + uint8_t rxfifo1esize; /* RX FIFO1 element size (words) */ + uint8_t txeventesize; /* TXevent element size (words) */ + uint8_t txbufferesize; /* TX buffer element size (words) */ +#ifdef STM32_FDCAN_LOOPBACK + bool loopback; /* True: Loopback mode */ +#endif + + /* FDCAN message RAM layout */ + + struct stm32_msgram_s msgram; +}; + +/* This structure provides the current state of a FDCAN peripheral */ + +struct stm32_fdcan_s +{ + /* The constant configuration */ + + const struct stm32_config_s *config; + + uint8_t state; /* See enum can_state_s */ +#ifdef CONFIG_NET_CAN_EXTID + uint8_t nextalloc; /* Number of allocated extended filters */ +#endif + uint8_t nstdalloc; /* Number of allocated standard filters */ + uint32_t nbtp; /* Current nominal bit timing */ + uint32_t dbtp; /* Current data bit timing */ + +#ifdef CONFIG_NET_CAN_EXTID + uint32_t extfilters[2]; /* Extended filter bit allocator. 2*32=64 */ +#endif + uint32_t stdfilters[4]; /* Standard filter bit allocator. 4*32=128 */ + +#ifdef CONFIG_STM32_FDCAN_REGDEBUG + uintptr_t regaddr; /* Last register address read */ + uint32_t regval; /* Last value read from the register */ + unsigned int count; /* Number of times that the value was read */ +#endif + + bool bifup; /* true:ifup false:ifdown */ + struct net_driver_s dev; /* Interface understood by the network */ + + struct work_s irqwork; /* For deferring interrupt work to the wq */ + struct work_s pollwork; /* For deferring poll work to the work wq */ + + /* A pointers to the list of TX/RX descriptors */ + + struct can_frame *txdesc; + struct can_frame *rxdesc; + + /* TX/RX pool */ + +#ifdef CONFIG_NET_CAN_CANFD + uint8_t tx_pool[sizeof(struct canfd_frame)*POOL_SIZE]; + uint8_t rx_pool[sizeof(struct canfd_frame)*POOL_SIZE]; +#else + uint8_t tx_pool[sizeof(struct can_frame)*POOL_SIZE]; + uint8_t rx_pool[sizeof(struct can_frame)*POOL_SIZE]; +#endif +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/* FDCAN Register access */ + +static uint32_t fdcan_getreg(struct stm32_fdcan_s *priv, int offset); +static void fdcan_putreg(struct stm32_fdcan_s *priv, int offset, + uint32_t regval); +#ifdef CONFIG_STM32_FDCAN_REGDEBUG +static void fdcan_dumpregs(struct stm32_fdcan_s *priv, + const char *msg); +static void fdcan_dumprxregs(struct stm32_fdcan_s *priv, + const char *msg); +static void fdcan_dumptxregs(struct stm32_fdcan_s *priv, + const char *msg); +static void fdcan_dumpramlayout(struct stm32_fdcan_s *priv); +#else +# define fdcan_dumpregs(priv,msg) +# define fdcan_dumprxregs(priv,msg) +# define fdcan_dumptxregs(priv,msg) +# define fdcan_dumpramlayout(priv) +#endif + +/* CAN interrupt enable functions */ + +static void fdcan_rx0int(struct stm32_fdcan_s *priv, bool enable); +static void fdcan_rx1int(struct stm32_fdcan_s *priv, bool enable); +static void fdcan_txint(struct stm32_fdcan_s *priv, bool enable); +#ifdef CONFIG_NET_CAN_ERRORS +static void fdcan_errint(struct stm32_fdcan_s *priv, bool enable); +#endif + +/* Common TX logic */ + +static int fdcan_send(struct stm32_fdcan_s *priv); +static bool fdcan_txready(struct stm32_fdcan_s *priv); +static int fdcan_txpoll(struct net_driver_s *dev); + +/* CAN RX interrupt handling */ + +static void fdcan_rx0interrupt_work(void *arg); +static void fdcan_rx1interrupt_work(void *arg); + +/* CAN TX interrupt handling */ + +static void fdcan_txdone_work(void *arg); +static void fdcan_txdone(struct stm32_fdcan_s *priv); + +#ifdef CONFIG_NET_CAN_ERRORS +/* CAN errors interrupt handling */ + +static void fdcan_error_work(void *arg); +#endif + +/* FDCAN interrupt handling */ + +#ifdef CONFIG_NET_CAN_ERRORS +static void fdcan_error(struct stm32_fdcan_s *priv, uint32_t status); +#endif +static void fdcan_receive(struct stm32_fdcan_s *priv, + volatile uint32_t *rxbuffer, + unsigned long nwords); +static int fdcan_interrupt(int irq, void *context, void *arg); + +/* Initialization */ + +static void fdcan_reset(struct stm32_fdcan_s *priv); +static int fdcan_setup(struct stm32_fdcan_s *priv); +static void fdcan_shutdown(struct stm32_fdcan_s *priv); + +/* FDCAN helpers */ + +#if 0 /* not used for now */ +static int +fdcan_start_busoff_recovery_sequence(struct stm32_fdcan_s *priv); +#endif + +/* Hardware initialization */ + +static int fdcan_hw_initialize(struct stm32_fdcan_s *priv); + +/* NuttX callback functions */ + +static int fdcan_ifup(struct net_driver_s *dev); +static int fdcan_ifdown(struct net_driver_s *dev); + +static void fdcan_txavail_work(void *arg); +static int fdcan_txavail(struct net_driver_s *dev); + +#ifdef CONFIG_NETDEV_IOCTL +static int fdcan_netdev_ioctl(struct net_driver_s *dev, int cmd, + unsigned long arg); +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#ifdef CONFIG_STM32_FDCAN1 +/* Message RAM allocation */ + +/* Constant configuration */ + +static const struct stm32_config_s g_fdcan1const = +{ + .rxpinset = GPIO_FDCAN1_RX, + .txpinset = GPIO_FDCAN1_TX, + .base = STM32_FDCAN1_BASE, + .baud = CONFIG_STM32_FDCAN1_BITRATE, + .nbtp = FDCAN_NBTP_NBRP(FDCAN1_NBRP) | + FDCAN_NBTP_NTSEG1(FDCAN1_NTSEG1) | + FDCAN_NBTP_NTSEG2(FDCAN1_NTSEG2) | + FDCAN_NBTP_NSJW(FDCAN1_NSJW), + .dbtp = FDCAN_DBTP_DBRP(FDCAN1_DBRP) | + FDCAN_DBTP_DTSEG1(FDCAN1_DTSEG1) | + FDCAN_DBTP_DTSEG2(FDCAN1_DTSEG2) | + FDCAN_DBTP_DSJW(FDCAN1_DSJW), + .port = 1, + .irq0 = STM32_IRQ_FDCAN1_0, + .irq1 = STM32_IRQ_FDCAN1_1, +#if defined(CONFIG_STM32_FDCAN1_CLASSIC) + .mode = FDCAN_CLASSIC_MODE, +#elif defined(CONFIG_STM32_FDCAN1_FD) + .mode = FDCAN_FD_MODE, +#else + .mode = FDCAN_FD_BRS_MODE, +#endif +#if defined(CONFIG_STM32_FDCAN1_NONISO_FORMAT) + .format = FDCAN_NONISO_BOSCH_V1_FORMAT, +#else + .format = FDCAN_ISO11898_1_FORMAT, +#endif + .nstdfilters = FDCAN1_STDFILTER_SIZE, + .nextfilters = FDCAN1_EXTFILTER_SIZE, + .nrxfifo0 = FDCAN1_RXFIFO0_SIZE, + .nrxfifo1 = FDCAN1_RXFIFO1_SIZE, + .ntxeventfifo = FDCAN1_TXEVENTFIFO_SIZE, + .ntxfifoq = FDCAN1_TXFIFIOQ_SIZE, + .rxfifo0esize = (FDCAN1_RXFIFO0_WORDS / FDCAN1_RXFIFO0_SIZE), + .rxfifo1esize = (FDCAN1_RXFIFO1_WORDS / FDCAN1_RXFIFO1_SIZE), + .txeventesize = (FDCAN1_TXEVENTFIFO_WORDS / FDCAN1_TXEVENTFIFO_SIZE), + .txbufferesize = (FDCAN1_TXFIFIOQ_WORDS / FDCAN1_TXFIFIOQ_SIZE), + +#ifdef CONFIG_STM32_FDCAN1_LOOPBACK + .loopback = true, +#endif + + /* FDCAN1 Message RAM */ + + .msgram = + { + (uint32_t *)(STM32_CANRAM1_BASE + (FDCAN1_STDFILTER_INDEX << 2)), + (uint32_t *)(STM32_CANRAM1_BASE + (FDCAN1_EXTFILTERS_INDEX << 2)), + (uint32_t *)(STM32_CANRAM1_BASE + (FDCAN1_RXFIFO0_INDEX << 2)), + (uint32_t *)(STM32_CANRAM1_BASE + (FDCAN1_RXFIFO1_INDEX << 2)), + (uint32_t *)(STM32_CANRAM1_BASE + (FDCAN1_TXEVENTFIFO_INDEX << 2)), + (uint32_t *)(STM32_CANRAM1_BASE + (FDCAN1_TXFIFOQ_INDEX << 2)) + } +}; + +/* FDCAN1 variable driver state */ + +static struct stm32_fdcan_s g_fdcan1priv; + +#endif /* CONFIG_STM32_FDCAN1 */ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: fdcan_getreg + * + * Description: + * Read the value of a FDCAN register. + * + * Input Parameters: + * priv - A reference to the FDCAN peripheral state + * offset - The offset to the register to read + * + * Returned Value: + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_FDCAN_REGDEBUG +static uint32_t fdcan_getreg(struct stm32_fdcan_s *priv, int offset) +{ + const struct stm32_config_s *config = priv->config; + uintptr_t regaddr = 0; + uint32_t regval = 0; + + /* Read the value from the register */ + + regaddr = config->base + offset; + regval = getreg32(regaddr); + + /* Is this the same value that we read from the same register last time? + * Are we polling the register? If so, suppress some of the output. + */ + + if (regaddr == priv->regaddr && regval == priv->regval) + { + if (priv->count == 0xffffffff || ++priv->count > 3) + { + if (priv->count == 4) + { + ninfo("...\n"); + } + + return regval; + } + } + + /* No this is a new address or value */ + + else + { + /* Did we print "..." for the previous value? */ + + if (priv->count > 3) + { + /* Yes.. then show how many times the value repeated */ + + ninfo("[repeats %d more times]\n", priv->count - 3); + } + + /* Save the new address, value, and count */ + + priv->regaddr = regaddr; + priv->regval = regval; + priv->count = 1; + } + + /* Show the register value read */ + + ninfo("%08" PRIx32 "->%08" PRIx32 "\n", regaddr, regval); + return regval; +} + +#else +static uint32_t fdcan_getreg(struct stm32_fdcan_s *priv, int offset) +{ + const struct stm32_config_s *config = priv->config; + return getreg32(config->base + offset); +} + +#endif + +/**************************************************************************** + * Name: fdcan_putreg + * + * Description: + * Set the value of a FDCAN register. + * + * Input Parameters: + * priv - A reference to the FDCAN peripheral state + * offset - The offset to the register to write + * regval - The value to write to the register + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_FDCAN_REGDEBUG +static void fdcan_putreg(struct stm32_fdcan_s *priv, int offset, + uint32_t regval) +{ + const struct stm32_config_s *config = priv->config; + uintptr_t regaddr = config->base + offset; + + /* Show the register value being written */ + + ninfo("%08" PRIx32 "->%08" PRIx32 "\n", regaddr, regval); + + /* Write the value */ + + putreg32(regval, regaddr); +} + +#else +static void fdcan_putreg(struct stm32_fdcan_s *priv, int offset, + uint32_t regval) +{ + const struct stm32_config_s *config = priv->config; + putreg32(regval, config->base + offset); +} + +#endif + +/**************************************************************************** + * Name: fdcan_dumpctrlregs + * + * Description: + * Dump the contents of all CAN control registers + * + * Input Parameters: + * priv - A reference to the CAN block status + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_FDCAN_REGDEBUG +static void fdcan_dumpregs(struct stm32_fdcan_s *priv, + const char *msg) +{ + const struct stm32_config_s *config = priv->config; + + ninfo("CAN%d Control and Status Registers: %s\n", config->port, msg); + ninfo(" Base: %08" PRIx32 "\n", config->base); + + /* CAN control and status registers */ + + ninfo(" CCCR: %08" PRIx32 " TEST: %08" PRIx32 "\n", + getreg32(config->base + STM32_FDCAN_CCCR_OFFSET), + getreg32(config->base + STM32_FDCAN_TEST_OFFSET)); + + ninfo(" NBTP: %08" PRIx32 " DBTP: %08" PRIx32 "\n", + getreg32(config->base + STM32_FDCAN_NBTP_OFFSET), + getreg32(config->base + STM32_FDCAN_DBTP_OFFSET)); + + ninfo(" IE: %08" PRIx32 " TIE: %08" PRIx32 "\n", + getreg32(config->base + STM32_FDCAN_IE_OFFSET), + getreg32(config->base + STM32_FDCAN_TXBTIE_OFFSET)); + + ninfo(" ILE: %08" PRIx32 " ILS: %08" PRIx32 "\n", + getreg32(config->base + STM32_FDCAN_ILE_OFFSET), + getreg32(config->base + STM32_FDCAN_ILS_OFFSET)); + + ninfo(" TXBC: %08" PRIx32 "\n", + getreg32(config->base + STM32_FDCAN_TXBC_OFFSET)); +} +#endif + +/**************************************************************************** + * Name: fdcan_dumprxregs + * + * Description: + * Dump the contents of all Rx status registers + * + * Input Parameters: + * priv - A reference to the CAN block status + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_FDCAN_REGDEBUG +static void fdcan_dumprxregs(struct stm32_fdcan_s *priv, + const char *msg) +{ + const struct stm32_config_s *config = priv->config; + + ninfo("CAN%d Rx Registers: %s\n", config->port, msg); + ninfo(" Base: %08" PRIx32 "\n", config->base); + + ninfo(" PSR: %08" PRIx32 " ECR: %08" PRIx32 + " HPMS: %08" PRIx32 "\n", + getreg32(config->base + STM32_FDCAN_PSR_OFFSET), + getreg32(config->base + STM32_FDCAN_ECR_OFFSET), + getreg32(config->base + STM32_FDCAN_HPMS_OFFSET)); + + ninfo(" RXF0S: %08" PRIx32 " RXF0A: %08" PRIx32 "\n", + getreg32(config->base + STM32_FDCAN_RXF0S_OFFSET), + getreg32(config->base + STM32_FDCAN_RXF0A_OFFSET)); + + ninfo(" RXF1S: %08" PRIx32 " RXF1A: %08" PRIx32 "\n", + getreg32(config->base + STM32_FDCAN_RXF1S_OFFSET), + getreg32(config->base + STM32_FDCAN_RXF1A_OFFSET)); + + ninfo(" IR: %08" PRIx32 " IE: %08" PRIx32 "\n", + getreg32(config->base + STM32_FDCAN_IR_OFFSET), + getreg32(config->base + STM32_FDCAN_IE_OFFSET)); +} +#endif + +/**************************************************************************** + * Name: fdcan_dumptxregs + * + * Description: + * Dump the contents of all Tx buffer registers + * + * Input Parameters: + * priv - A reference to the CAN block status + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_FDCAN_REGDEBUG +static void fdcan_dumptxregs(struct stm32_fdcan_s *priv, + const char *msg) +{ + const struct stm32_config_s *config = priv->config; + + ninfo("CAN%d Tx Registers: %s\n", config->port, msg); + ninfo(" Base: %08" PRIx32 "\n", config->base); + + ninfo(" PSR: %08" PRIx32 " ECR: %08" PRIx32 "\n", + getreg32(config->base + STM32_FDCAN_PSR_OFFSET), + getreg32(config->base + STM32_FDCAN_ECR_OFFSET)); + + ninfo(" TXQFS: %08" PRIx32 " TXBAR: %08" PRIx32 + " TXBRP: %08" PRIx32 "\n", + getreg32(config->base + STM32_FDCAN_TXFQS_OFFSET), + getreg32(config->base + STM32_FDCAN_TXBAR_OFFSET), + getreg32(config->base + STM32_FDCAN_TXBRP_OFFSET)); + + ninfo(" TXBTO: %08" PRIx32 " TXBCR: %08" PRIx32 "\n", + getreg32(config->base + STM32_FDCAN_TXBTO_OFFSET), + getreg32(config->base + STM32_FDCAN_TXBCR_OFFSET)); + + ninfo(" TXEFS: %08" PRIx32 " TXEFA: %08" PRIx32 "\n", + getreg32(config->base + STM32_FDCAN_TXEFS_OFFSET), + getreg32(config->base + STM32_FDCAN_TXEFA_OFFSET)); + + ninfo(" IR: %08" PRIx32 " IE: %08" PRIx32 + " TIE: %08" PRIx32 "\n", + getreg32(config->base + STM32_FDCAN_IR_OFFSET), + getreg32(config->base + STM32_FDCAN_IE_OFFSET), + getreg32(config->base + STM32_FDCAN_TXBTIE_OFFSET)); +} +#endif + +/**************************************************************************** + * Name: fdcan_dumpramlayout + * + * Description: + * Print the layout of the message RAM + * + * Input Parameters: + * priv - A reference to the CAN block status + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_FDCAN_REGDEBUG +static void fdcan_dumpramlayout(struct stm32_fdcan_s *priv) +{ + const struct stm32_config_s *config = priv->config; + + ninfo(" ******* FDCAN%d Message RAM layout *******\n", config->port); + ninfo(" Start # Elmnt Elmnt size (words)\n"); + + if (config->nstdfilters > 0) + { + ninfo("STD filters %p %4d %2d\n", + config->msgram.stdfilters, + config->nstdfilters, + 1); + } + + if (config->nextfilters > 0) + { + ninfo("EXT filters %p %4d %2d\n", + config->msgram.extfilters, + config->nextfilters, + 2); + } + + if (config->nrxfifo0 > 0) + { + ninfo("RX FIFO 0 %p %4d %2d\n", + config->msgram.rxfifo0, + config->nrxfifo0, + config->rxfifo0esize); + } + + if (config->nrxfifo1 > 0) + { + ninfo("RX FIFO 1 %p %4d %2d\n", + config->msgram.rxfifo1, + config->nrxfifo1, + config->rxfifo1esize); + } + + if (config->ntxeventfifo > 0) + { + ninfo("TX EVENT %p %4d %2d\n", + config->msgram.txeventfifo, + config->ntxeventfifo, + config->txeventesize); + } + + if (config->ntxfifoq > 0) + { + ninfo("TX FIFO %p %4d %2d\n", + config->msgram.txfifoq, + config->ntxfifoq, + config->txbufferesize); + } +} +#endif + +/**************************************************************************** + * Name: fdcan_start_busoff_recovery_sequence + * + * Description: + * This function initiates the BUS-OFF recovery sequence. + * CAN Specification Rev. 2.0 or ISO11898-1:2015. + * According the STM32G4 datasheet section 44.3.2 Software initialziation. + * + * Input Parameters: + * priv - An instance of the FDCAN driver state structure. + * + * Returned Value: + * Zero (OK) is returned on success. Otherwise a negated errno value is + * returned to indicate the nature of the error. + * + ****************************************************************************/ + +#if 0 /* not used for now */ +static int +fdcan_start_busoff_recovery_sequence(struct stm32_fdcan_s *priv) +{ + uint32_t regval = 0; + + DEBUGASSERT(priv); + + /* Only start BUS-OFF recovery if we are in BUS-OFF state */ + + regval = fdcan_getreg(priv, STM32_FDCAN_PSR_OFFSET); + if ((regval & FDCAN_PSR_BO) == 0) + { + return -EPERM; + } + + /* Disable initialization mode to issue the recovery sequence */ + + regval = fdcan_getreg(priv, STM32_FDCAN_CCCR_OFFSET); + regval &= ~FDCAN_CCCR_INIT; + fdcan_putreg(priv, STM32_FDCAN_CCCR_OFFSET, regval); + + return OK; +} +#endif + +/**************************************************************************** + * Name: fdcan_reset + * + * Description: + * Reset the FDCAN device. Called early to initialize the hardware. This + * function is called, before fdcan_setup() and on error conditions. + * + * Input Parameters: + * dev - An instance of the "upper half" can driver state structure. + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void fdcan_reset(struct stm32_fdcan_s *priv) +{ + const struct stm32_config_s *config = NULL; + uint32_t regval = 0; + irqstate_t flags; + + DEBUGASSERT(priv); + config = priv->config; + DEBUGASSERT(config); + + ninfo("FDCAN%d\n", config->port); + UNUSED(config); + + /* Disable all interrupts */ + + fdcan_putreg(priv, STM32_FDCAN_IE_OFFSET, 0); + fdcan_putreg(priv, STM32_FDCAN_TXBTIE_OFFSET, 0); + + /* Make sure that all buffers are released. + * + * REVISIT: What if a thread is waiting for a buffer? The following + * will not wake up any waiting threads. + */ + + /* Disable the FDCAN controller. + * REVISIT: Should fdcan_shutdown() be called here? + */ + + /* Reset the FD CAN. + * REVISIT: Since there is only a single reset for both FDCAN + * controllers, do we really want to use the RCC reset here? + * This will nuke operation of the second controller if another + * device is registered. + */ + + flags = enter_critical_section(); + regval = getreg32(STM32_RCC_APB1RSTR); + regval |= RCC_APB1RSTR_FDCANRST; + putreg32(regval, STM32_RCC_APB1RSTR); + + regval &= ~RCC_APB1RSTR_FDCANRST; + putreg32(regval, STM32_RCC_APB1RSTR); + leave_critical_section(flags); + + priv->state = FDCAN_STATE_RESET; +} + +/**************************************************************************** + * Name: fdcan_setup + * + * Description: + * Configure the FDCAN. This method is called the first time that the FDCAN + * device is opened. This will occur when the port is first opened. + * This setup includes configuring and attaching FDCAN interrupts. + * All FDCAN interrupts are disabled upon return. + * + * Input Parameters: + * dev - An instance of the "upper half" can driver state structure. + * + * Returned Value: + * Zero on success; a negated errno on failure + * + ****************************************************************************/ + +static int fdcan_setup(struct stm32_fdcan_s *priv) +{ + const struct stm32_config_s *config = NULL; + int ret = 0; + + DEBUGASSERT(priv); + config = priv->config; + DEBUGASSERT(config); + + ninfo("FDCAN%d\n", config->port); + + /* FDCAN hardware initialization */ + + ret = fdcan_hw_initialize(priv); + if (ret < 0) + { + nerr("ERROR: FDCAN%d H/W initialization failed: %d\n", + config->port, ret); + return ret; + } + + fdcan_dumpregs(priv, "After hardware initialization"); + + /* Attach the FDCAN interrupt handlers */ + + ret = irq_attach(config->irq0, fdcan_interrupt, priv); + if (ret < 0) + { + nerr("ERROR: Failed to attach FDCAN%d line 0 IRQ (%d)", + config->port, config->irq0); + return ret; + } + + ret = irq_attach(config->irq1, fdcan_interrupt, priv); + if (ret < 0) + { + nerr("ERROR: Failed to attach FDCAN%d line 1 IRQ (%d)", + config->port, config->irq1); + return ret; + } + + priv->state = FDCAN_STATE_SETUP; + + /* Enable the interrupts at the NVIC (they are still disabled at the FDCAN + * peripheral). + */ + + up_enable_irq(config->irq0); + up_enable_irq(config->irq1); + + return OK; +} + +/**************************************************************************** + * Name: fdcan_shutdown + * + * Description: + * Disable the FDCAN. This method is called when the FDCAN device + * is closed. This method reverses the operation the setup method. + * + * Input Parameters: + * dev - An instance of the "upper half" can driver state structure. + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void fdcan_shutdown(struct stm32_fdcan_s *priv) +{ + const struct stm32_config_s *config = NULL; + uint32_t regval = 0; + + DEBUGASSERT(priv); + config = priv->config; + DEBUGASSERT(config); + + ninfo("FDCAN%d\n", config->port); + + /* Disable FDCAN interrupts at the NVIC */ + + up_disable_irq(config->irq0); + up_disable_irq(config->irq1); + + /* Disable all interrupts from the FDCAN peripheral */ + + fdcan_putreg(priv, STM32_FDCAN_IE_OFFSET, 0); + fdcan_putreg(priv, STM32_FDCAN_TXBTIE_OFFSET, 0); + + /* Detach the FDCAN interrupt handler */ + + irq_detach(config->irq0); + irq_detach(config->irq1); + + /* Disable device by setting the Clock Stop Request bit */ + + regval = fdcan_getreg(priv, STM32_FDCAN_CCCR_OFFSET); + regval |= FDCAN_CCCR_CSR; + fdcan_putreg(priv, STM32_FDCAN_CCCR_OFFSET, regval); + + /* Wait for Init and Clock Stop Acknowledge bits to verify + * device is in the powered down state + */ + + while ((fdcan_getreg(priv, STM32_FDCAN_CCCR_OFFSET) & FDCAN_CCCR_INIT) + == 0); + while ((fdcan_getreg(priv, STM32_FDCAN_CCCR_OFFSET) & FDCAN_CCCR_CSA) + == 0); + priv->state = FDCAN_STATE_DISABLED; +} + +/**************************************************************************** + * Name: fdcan_rx0int + * + * Description: + * Call to enable or disable RX0 interrupts. + * + * Input Parameters: + * priv - reference to the private CAN driver state structure + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void fdcan_rx0int(struct stm32_fdcan_s *priv, bool enable) +{ + const struct stm32_config_s *config = NULL; + uint32_t regval = 0; + + DEBUGASSERT(priv); + config = priv->config; + DEBUGASSERT(config); + + ninfo("CAN%" PRIu8 "RX0 enable: %d\n", config->port, enable); + + /* Enable/disable the FIFO 0 message pending interrupt */ + + regval = fdcan_getreg(priv, STM32_FDCAN_IE_OFFSET); + + if (enable) + { + regval |= FDCAN_RXFIFO0_INTS; + } + else + { + regval &= ~FDCAN_RXFIFO0_INTS; + } + + fdcan_putreg(priv, STM32_FDCAN_IE_OFFSET, regval); +} + +/**************************************************************************** + * Name: fdcan_rx1int + * + * Description: + * Call to enable or disable RX1 interrupts. + * + * Input Parameters: + * priv - reference to the private CAN driver state structure + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void fdcan_rx1int(struct stm32_fdcan_s *priv, bool enable) +{ + const struct stm32_config_s *config = NULL; + uint32_t regval = 0; + + DEBUGASSERT(priv); + config = priv->config; + DEBUGASSERT(config); + + ninfo("CAN%" PRIu8 "RX1 enable: %d\n", config->port, enable); + + /* Enable/disable the FIFO 1 message pending interrupt */ + + regval = fdcan_getreg(priv, STM32_FDCAN_IE_OFFSET); + + if (enable) + { + regval |= FDCAN_RXFIFO1_INTS; + } + else + { + regval &= ~FDCAN_RXFIFO1_INTS; + } + + fdcan_putreg(priv, STM32_FDCAN_IE_OFFSET, regval); +} + +/**************************************************************************** + * Name: fdcan_txint + * + * Description: + * Call to enable or disable TX interrupts. + * + * Input Parameters: + * dev - An instance of the "upper half" can driver state structure. + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void fdcan_txint(struct stm32_fdcan_s *priv, bool enable) +{ + const struct stm32_config_s *config = NULL; + uint32_t regval = 0; + + DEBUGASSERT(priv); + config = priv->config; + DEBUGASSERT(config); + + ninfo("CAN%" PRIu8 "TX enable: %d\n", config->port, enable); + + /* Enable/disable the receive interrupts */ + + regval = fdcan_getreg(priv, STM32_FDCAN_IE_OFFSET); + + if (enable) + { + regval |= FDCAN_TXFIFOQ_INTS; + } + else + { + regval &= ~FDCAN_TXFIFOQ_INTS; + } + + fdcan_putreg(priv, STM32_FDCAN_IE_OFFSET, regval); +} + +#ifdef CONFIG_NET_CAN_ERRORS +/**************************************************************************** + * Name: fdcan_txint + * + * Description: + * Call to enable or disable CAN SCE interrupts. + * + * Input Parameters: + * priv - reference to the private CAN driver state structure + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void fdcan_errint(struct stm32_fdcan_s *priv, bool enable) +{ + const struct stm32_config_s *config = NULL; + uint32_t regval = 0; + + DEBUGASSERT(priv); + config = priv->config; + DEBUGASSERT(config); + + ninfo("CAN%" PRIu8 "ERR enable: %d\n", config->port, enable); + + /* Enable/disable the transmit mailbox interrupt */ + + regval = fdcan_getreg(priv, STM32_FDCAN_IE_OFFSET); + if (enable) + { + regval |= FDCAN_ANYERR_INTS; + } + else + { + regval &= ~FDCAN_ANYERR_INTS; + } + + fdcan_putreg(priv, STM32_FDCAN_IE_OFFSET, regval); +} +#endif + +/**************************************************************************** + * Name: fdcan_send + * + * Description: + * Send one can message. + * + * One CAN-message consists of a maximum of 10 bytes. A message is + * composed of at least the first 2 bytes (when there are no data bytes). + * + * Byte 0: Bits 0-7: Bits 3-10 of the 11-bit CAN identifier + * Byte 1: Bits 5-7: Bits 0-2 of the 11-bit CAN identifier + * Bit 4: Remote Transmission Request (RTR) + * Bits 0-3: Data Length Code (DLC) + * Bytes 2-10: CAN data + * + * Input Parameters: + * dev - An instance of the "upper half" can driver state structure. + * + * Returned Value: + * Zero on success; a negated errno on failure + * + ****************************************************************************/ + +static int fdcan_send(struct stm32_fdcan_s *priv) +{ + const struct stm32_config_s *config = NULL; + volatile uint32_t *txbuffer = NULL; + const uint8_t *src = NULL; + uint32_t *dest = NULL; + uint32_t regval = 0; + unsigned int ndx = 0; + unsigned int nbytes = 0; + uint32_t wordbuffer = 0; + unsigned int i = 0; + + DEBUGASSERT(priv); + config = priv->config; + DEBUGASSERT(config); + + fdcan_dumptxregs(priv, "Before send"); + + /* That that FIFO elements were configured */ + + DEBUGASSERT(config->ntxfifoq > 0); + + /* Get our reserved Tx FIFO/queue put index */ + + regval = fdcan_getreg(priv, STM32_FDCAN_TXFQS_OFFSET); + DEBUGASSERT((regval & FDCAN_TXFQS_TFQF) == 0); + + ndx = (regval & FDCAN_TXFQS_TFQPI_MASK) >> FDCAN_TXFQS_TFQPI_SHIFT; + + /* And the TX buffer corresponding to this index */ + + txbuffer = (config->msgram.txfifoq + ndx * config->txbufferesize); + + /* Format the TX FIFOQ entry + * + * Format word T0: + * Transfer message ID (ID) - Value from message structure + * Remote Transmission Request (RTR) - Value from message structure + * Extended Identifier (XTD) - Depends on configuration. + * Error state indicator (ESI) - ESI bit in CAN FD + * + * Format word T1: + * Data Length Code (DLC) - Value from message structure + * Bit Rate Switch (BRS) - Bit rate switching for CAN FD + * FD format (FDF) - Frame transmitted in CAN FD format + * Event FIFO Control (EFC) - Do not store events. + * Message Marker (MM) - Always zero + */ + + txbuffer[0] = 0; + txbuffer[1] = 0; + + /* CAN 2.0 or CAN FD */ + + if (priv->dev.d_len == sizeof(struct can_frame)) + { + struct can_frame *frame = NULL; + + frame = (struct can_frame *)priv->dev.d_buf; + + ninfo("CAN%" PRIu8 " 2.0 ID: %" PRIu32 " DLC: %" PRIu8 "\n", + config->port, (uint32_t)frame->can_id, frame->can_dlc); + + /* Extended or standard ID */ + +#ifdef CONFIG_NET_CAN_EXTID + if ((frame->can_id & CAN_EFF_FLAG) != 0) + { + DEBUGASSERT((frame->can_id ^ CAN_EFF_FLAG) < (1 << 29)); + + txbuffer[0] |= BUFFER_R0_EXTID(frame->can_id) | BUFFER_R0_XTD; + } + else +#endif + { + DEBUGASSERT(frame->can_id < (1 << 11)); + + txbuffer[0] |= BUFFER_R0_STDID(frame->can_id); + } + + /* Set DLC */ + + txbuffer[1] |= BUFFER_R1_DLC(frame->can_dlc); + + /* Set flags */ + + if ((frame->can_id & CAN_RTR_FLAG) != 0) + { + txbuffer[0] |= BUFFER_R0_RTR; + } + + /* Reset CAN FD bits */ + + txbuffer[0] &= ~BUFFER_R0_ESI; + txbuffer[1] &= ~BUFFER_R1_FDF; + txbuffer[1] &= ~BUFFER_R1_BRS; + + /* Followed by the amount of data corresponding to the DLC (T2..) */ + + src = frame->data; + nbytes = frame->can_dlc; + } +#ifdef CONFIG_NET_CAN_CANFD + else /* CAN FD frame */ + { + struct canfd_frame *frame = (struct canfd_frame *)priv->dev.d_buf; + + frame = (struct canfd_frame *)priv->dev.d_buf; + + ninfo("CAN%" PRIu8 " FD ID: %" PRIu32 " len: %" PRIu8 "\n", + config->port, (uint32_t)frame->can_id, frame->len); + + /* Extended or standard ID */ + +#ifdef CONFIG_NET_CAN_EXTID + if ((frame->can_id & CAN_EFF_FLAG) != 0) + { + DEBUGASSERT(frame->can_id < (1 << 29)); + + txbuffer[0] |= BUFFER_R0_EXTID(frame->can_id) | BUFFER_R0_XTD; + } + else +#endif + { + DEBUGASSERT(frame->can_id < (1 << 11)); + + txbuffer[0] |= BUFFER_R0_STDID(frame->can_id); + } + + /* CANFD frame */ + + txbuffer[1] |= BUFFER_R1_FDF; + + /* Set DLC */ + + txbuffer[1] |= BUFFER_R1_DLC(g_len_to_can_dlc[frame->len]); + + /* Set flags */ + + if ((frame->can_id & CAN_RTR_FLAG) != 0) + { + txbuffer[0] |= BUFFER_R0_RTR; + } + + if ((frame->flags & CANFD_BRS) != 0) + { + txbuffer[1] |= BUFFER_R1_BRS; + } + + if ((frame->flags & CANFD_ESI) != 0) + { + txbuffer[0] |= BUFFER_R0_ESI; + } + + /* Followed by the amount of data corresponding to the DLC (T2..) */ + + src = frame->data; + nbytes = frame->len; + } +#endif + + dest = (uint32_t *)&txbuffer[2]; + + /* Writes must be word length */ + + for (i = 0; i < nbytes; i += 4) + { + /* Little endian is assumed */ + + wordbuffer = src[0] | + (src[1] << 8) | + (src[2] << 16) | + (src[3] << 24); + src += 4; + + *dest++ = wordbuffer; + } + + /* Enable transmit interrupts from the TX FIFOQ buffer by setting TC + * interrupt bit in IR (also requires that the TC interrupt is enabled) + */ + + fdcan_putreg(priv, STM32_FDCAN_TXBTIE_OFFSET, (1 << ndx)); + + /* And request to send the packet */ + + fdcan_putreg(priv, STM32_FDCAN_TXBAR_OFFSET, (1 << ndx)); + + return OK; +} + +/**************************************************************************** + * Name: fdcan_txready + * + * Description: + * Return true if the FDCAN hardware can accept another TX message. + * + * Input Parameters: + * dev - An instance of the "upper half" can driver state structure. + * + * Returned Value: + * True if the FDCAN hardware is ready to accept another TX message. + * + ****************************************************************************/ + +static bool fdcan_txready(struct stm32_fdcan_s *priv) +{ + uint32_t regval = 0; + bool notfull = false; + + /* Return the state of the TX FIFOQ. Return TRUE if the TX FIFO/Queue is + * not full. + */ + + regval = fdcan_getreg(priv, STM32_FDCAN_TXFQS_OFFSET); + notfull = ((regval & FDCAN_TXFQS_TFQF) == 0); + + return notfull; +} + +/**************************************************************************** + * Name: fdcan_rx0interrupt_work + * + * Description: + * CAN RX FIFO 0 worker + * + ****************************************************************************/ + +static void fdcan_rx0interrupt_work(void *arg) +{ + struct stm32_fdcan_s *priv = (struct stm32_fdcan_s *)arg; + const struct stm32_config_s *config = NULL; + uint32_t regval = 0; + unsigned int nelem = 0; + unsigned int ndx = 0; + + DEBUGASSERT(priv); + config = priv->config; + DEBUGASSERT(config); + + /* Clear the RX FIFO0 new message interrupt */ + + fdcan_putreg(priv, STM32_FDCAN_IR_OFFSET, FDCAN_INT_RF0N); + + regval = fdcan_getreg(priv, STM32_FDCAN_RXF0S_OFFSET); + nelem = (regval & FDCAN_RXFS_FFL_MASK) >> FDCAN_RXFS_FFL_SHIFT; + if (nelem > 0) + { + /* Handle the newly received message in FIFO0 */ + + ndx = (regval & FDCAN_RXFS_FGI_MASK) >> FDCAN_RXFS_FGI_SHIFT; + + if ((regval & FDCAN_RXFS_RFL) != 0) + { + nerr("ERROR: Message lost: %08" PRIx32 "\n", regval); + } + else + { + fdcan_receive(priv, + config->msgram.rxfifo0 + + (ndx * priv->config->rxfifo0esize), + priv->config->rxfifo0esize); + +#ifdef CONFIG_NET_CAN_ERRORS + /* Turning back on all configured RX error interrupts */ + + regval = fdcan_getreg(priv, STM32_FDCAN_IE_OFFSET); + regval |= FDCAN_RXERR_INTS; + fdcan_putreg(priv, STM32_FDCAN_IE_OFFSET, regval); +#endif + } + + /* Acknowledge reading the FIFO entry */ + + fdcan_putreg(priv, STM32_FDCAN_RXF0A_OFFSET, ndx); + } + + /* Re-enable CAN RX interrupts */ + + fdcan_rx0int(priv, true); +} + +/**************************************************************************** + * Name: fdcan_rx1interrupt_work + * + * Description: + * CAN RX FIFO 1 worker + * + ****************************************************************************/ + +static void fdcan_rx1interrupt_work(void *arg) +{ + struct stm32_fdcan_s *priv = (struct stm32_fdcan_s *)arg; + const struct stm32_config_s *config = NULL; + uint32_t regval = 0; + unsigned int nelem = 0; + unsigned int ndx = 0; + + DEBUGASSERT(priv); + config = priv->config; + DEBUGASSERT(config); + + /* Clear the RX FIFO1 new message interrupt */ + + fdcan_putreg(priv, STM32_FDCAN_IR_OFFSET, FDCAN_INT_RF1N); + + /* Check if there is anything in RX FIFO1 */ + + regval = fdcan_getreg(priv, STM32_FDCAN_RXF1S_OFFSET); + nelem = (regval & FDCAN_RXFS_FFL_MASK) >> FDCAN_RXFS_FFL_SHIFT; + if (nelem == 0) + { + /* Clear the RX FIFO1 interrupt (and all other FIFO1-related + * interrupts) + */ + + /* Handle the newly received message in FIFO1 */ + + ndx = (regval & FDCAN_RXFS_FGI_MASK) >> FDCAN_RXFS_FGI_SHIFT; + + if ((regval & FDCAN_RXFS_RFL) != 0) + { + nerr("ERROR: Message lost: %08" PRIx32 "\n", regval); + } + else + { + fdcan_receive(priv, + config->msgram.rxfifo1 + + (ndx * priv->config->rxfifo1esize), + priv->config->rxfifo1esize); + +#ifdef CONFIG_NET_CAN_ERRORS + /* Turning back on all configured RX error interrupts */ + + regval = fdcan_getreg(priv, STM32_FDCAN_IE_OFFSET); + regval |= FDCAN_RXERR_INTS; + fdcan_putreg(priv, STM32_FDCAN_IE_OFFSET, regval); +#endif + } + + /* Acknowledge reading the FIFO entry */ + + fdcan_putreg(priv, STM32_FDCAN_RXF1A_OFFSET, ndx); + } + + /* Re-enable CAN RX interrupts */ + + fdcan_rx1int(priv, true); +} + +/**************************************************************************** + * Name: fdcan_txdone_work + ****************************************************************************/ + +static void fdcan_txdone_work(void *arg) +{ + struct stm32_fdcan_s *priv = (struct stm32_fdcan_s *)arg; + + fdcan_txdone(priv); + + /* There should be space for a new TX in any event. Poll the network for + * new XMIT data + */ + + net_lock(); + devif_poll(&priv->dev, fdcan_txpoll); + net_unlock(); +} + +/**************************************************************************** + * Name: fdcan_txdone + ****************************************************************************/ + +static void fdcan_txdone(struct stm32_fdcan_s *priv) +{ + const struct stm32_config_s *config = NULL; + unsigned int ndx = 0; + uint32_t regval = 0; + + DEBUGASSERT(priv); + config = priv->config; + DEBUGASSERT(config); + + /* Clear the pending TX completion interrupt (and all + * other TX-related interrupts) + */ + + fdcan_putreg(priv, STM32_FDCAN_IR_OFFSET, FDCAN_TXFIFOQ_INTS); + + /* Check all TX buffers */ + + regval = fdcan_getreg(priv, STM32_FDCAN_TXBTO_OFFSET); + for (ndx = 0; ndx < config->ntxfifoq; ndx++) + { + if ((regval & (1 << ndx)) != 0) + { + /* Tell the upper half that the transfer is finished. */ + + NETDEV_TXDONE(&priv->dev); + } + } + +#ifdef CONFIG_NET_CAN_ERRORS + /* Turning back on PEA and PED error interrupts */ + + regval = fdcan_getreg(priv, STM32_FDCAN_IE_OFFSET); + regval |= (FDCAN_INT_PEA | FDCAN_INT_PED); + fdcan_putreg(priv, STM32_FDCAN_IE_OFFSET, regval); +#endif + + /* Re-enable TX interrupts */ + + fdcan_txint(priv, true); +} + +#ifdef CONFIG_NET_CAN_ERRORS +/**************************************************************************** + * Name: fdcan_error_work + ****************************************************************************/ + +static void fdcan_error_work(void *arg) +{ + struct stm32_fdcan_s *priv = (struct stm32_fdcan_s *)arg; + uint32_t pending = 0; + uint32_t ir = 0; + uint32_t ie = 0; + uint32_t psr = 0; + + /* Get the set of pending interrupts. */ + + ir = fdcan_getreg(priv, STM32_FDCAN_IR_OFFSET); + ie = fdcan_getreg(priv, STM32_FDCAN_IE_OFFSET); + + pending = (ir & ie); + ie |= FDCAN_ANYERR_INTS; + + /* Check for common errors */ + + if ((pending & FDCAN_CMNERR_INTS) != 0) + { + /* When a protocol error occurs, the problem is recorded in + * the LEC/DLEC fields of the PSR register. In lieu of + * separate interrupt flags for each error, the hardware + * groups protocol errors under a single interrupt each for + * arbitration and data phases. + * + * These errors have a tendency to flood the system with + * interrupts, so they are disabled here until we get a + * successful transfer/receive on the hardware + */ + + psr = fdcan_getreg(priv, STM32_FDCAN_PSR_OFFSET); + + if ((psr & FDCAN_PSR_LEC_MASK) != 0) + { + ie &= ~(FDCAN_INT_PEA | FDCAN_INT_PED); + } + + /* Clear the error indications */ + + fdcan_putreg(priv, STM32_FDCAN_IR_OFFSET, FDCAN_CMNERR_INTS); + } + + /* Check for transmission errors */ + + if ((pending & FDCAN_TXERR_INTS) != 0) + { + /* An Acknowledge-Error will occur if for example the device + * is not connected to the bus. + * + * The CAN-Standard states that the Chip has to retry the + * message forever, which will produce an ACKE every time. + * To prevent this Interrupt-Flooding and the high CPU-Load + * we disable the ACKE here as long we didn't transfer at + * least one message successfully (see FDCAN_INT_TC below). + */ + + /* Clear the error indications */ + + fdcan_putreg(priv, STM32_FDCAN_IR_OFFSET, FDCAN_TXERR_INTS); + } + + /* Check for reception errors */ + + if ((pending & FDCAN_RXERR_INTS) != 0) + { + /* To prevent Interrupt-Flooding the current active + * RX error interrupts are disabled. After successfully + * receiving at least one CAN packet all RX error interrupts + * are turned back on. + * + * The Interrupt-Flooding can for example occur if the + * configured CAN speed does not match the speed of the other + * CAN nodes in the network. + */ + + ie &= ~(pending & FDCAN_RXERR_INTS); + + /* Clear the error indications */ + + fdcan_putreg(priv, STM32_FDCAN_IR_OFFSET, FDCAN_RXERR_INTS); + } + + /* Report errors */ + + net_lock(); + fdcan_error(priv, pending & FDCAN_ANYERR_INTS); + net_unlock(); + + /* Re-enable ERROR interrupts */ + + fdcan_putreg(priv, STM32_FDCAN_IE_OFFSET, ie); +} + +/**************************************************************************** + * Name: fdcan_error + * + * Description: + * Report a CAN error + * + * Input Parameters: + * dev - CAN-common state data + * status - Interrupt status with error bits set + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void fdcan_error(struct stm32_fdcan_s *priv, uint32_t status) +{ + struct can_frame *frame = (struct can_frame *)priv->rxdesc; + uint32_t psr = 0; + uint16_t errbits = 0; + uint8_t data[CAN_ERR_DLC]; + + DEBUGASSERT(priv != NULL); + + /* Encode error bits */ + + errbits = 0; + memset(data, 0, sizeof(data)); + + /* Always fill in "static" error conditions, but set the signaling bit + * only if the condition has changed (see IRQ-Flags below) + * They have to be filled in every time CAN_ERROR_CONTROLLER is set. + */ + + psr = fdcan_getreg(priv, STM32_FDCAN_PSR_OFFSET); + if ((psr & FDCAN_PSR_EP) != 0) + { + data[1] |= (CAN_ERR_CRTL_RX_PASSIVE | CAN_ERR_CRTL_TX_PASSIVE); + } + + if ((psr & FDCAN_PSR_EW) != 0) + { + data[1] |= (CAN_ERR_CRTL_RX_WARNING | CAN_ERR_CRTL_TX_WARNING); + } + + if ((status & (FDCAN_INT_EP | FDCAN_INT_EW)) != 0) + { + /* "Error Passive" or "Error Warning" status changed */ + + errbits |= CAN_ERR_CRTL; + } + + if ((status & FDCAN_INT_PEA) != 0) + { + /* Protocol Error in Arbitration Phase */ + + if ((psr & FDCAN_PSR_LEC_MASK) != 0) + { + /* Error code present */ + + if ((psr & FDCAN_PSR_LEC(FDCAN_PSR_EC_STUFF_ERROR)) != 0) + { + /* Stuff Error */ + + errbits |= CAN_ERR_PROT; + data[2] |= CAN_ERR_PROT_STUFF; + } + + if ((psr & FDCAN_PSR_LEC(FDCAN_PSR_EC_FORM_ERROR)) != 0) + { + /* Format Error */ + + errbits |= CAN_ERR_PROT; + data[2] |= CAN_ERR_PROT_FORM; + } + + if ((psr & FDCAN_PSR_LEC(FDCAN_PSR_EC_ACK_ERROR)) != 0) + { + /* Acknowledge Error */ + + errbits |= CAN_ERR_ACK; + } + + if ((psr & FDCAN_PSR_LEC(FDCAN_PSR_EC_BIT0_ERROR)) != 0) + { + /* Bit0 Error */ + + errbits |= CAN_ERR_PROT; + data[2] |= CAN_ERR_PROT_BIT0; + } + + if ((psr & FDCAN_PSR_LEC(FDCAN_PSR_EC_BIT1_ERROR)) != 0) + { + /* Bit1 Error */ + + errbits |= CAN_ERR_PROT; + data[2] |= CAN_ERR_PROT_BIT1; + } + + if ((psr & FDCAN_PSR_LEC(FDCAN_PSR_EC_CRC_ERROR)) != 0) + { + /* Receive CRC Error */ + + errbits |= CAN_ERR_PROT; + data[3] |= (CAN_ERR_PROT_LOC_CRC_SEQ | + CAN_ERR_PROT_LOC_CRC_DEL); + } + + if ((psr & FDCAN_PSR_LEC(FDCAN_PSR_EC_NO_CHANGE)) != 0) + { + /* No Change in Error */ + + errbits |= CAN_ERR_PROT; + data[2] |= CAN_ERR_PROT_UNSPEC; + } + } + } + + if ((status & FDCAN_INT_PED) != 0) + { + /* Protocol Error in Data Phase */ + + if ((psr & FDCAN_PSR_DLEC_MASK) != 0) + { + /* Error code present */ + + if ((psr & FDCAN_PSR_DLEC(FDCAN_PSR_EC_STUFF_ERROR)) != 0) + { + /* Stuff Error */ + + errbits |= CAN_ERR_PROT; + data[2] |= CAN_ERR_PROT_STUFF; + } + + if ((psr & FDCAN_PSR_DLEC(FDCAN_PSR_EC_FORM_ERROR)) != 0) + { + /* Format Error */ + + errbits |= CAN_ERR_PROT; + data[2] |= CAN_ERR_PROT_FORM; + } + + if ((psr & FDCAN_PSR_DLEC(FDCAN_PSR_EC_ACK_ERROR)) != 0) + { + /* Acknowledge Error */ + + errbits |= CAN_ERR_ACK; + } + + if ((psr & FDCAN_PSR_DLEC(FDCAN_PSR_EC_BIT0_ERROR)) != 0) + { + /* Bit0 Error */ + + errbits |= CAN_ERR_PROT; + data[2] |= CAN_ERR_PROT_BIT0; + } + + if ((psr & FDCAN_PSR_DLEC(FDCAN_PSR_EC_BIT1_ERROR)) != 0) + { + /* Bit1 Error */ + + errbits |= CAN_ERR_PROT; + data[2] |= CAN_ERR_PROT_BIT1; + } + + if ((psr & FDCAN_PSR_DLEC(FDCAN_PSR_EC_CRC_ERROR)) != 0) + { + /* Receive CRC Error */ + + errbits |= CAN_ERR_PROT; + data[3] |= (CAN_ERR_PROT_LOC_CRC_SEQ | + CAN_ERR_PROT_LOC_CRC_DEL); + } + + if ((psr & FDCAN_PSR_DLEC(FDCAN_PSR_EC_NO_CHANGE)) != 0) + { + /* No Change in Error */ + + errbits |= CAN_ERR_PROT; + data[2] |= CAN_ERR_PROT_UNSPEC; + } + } + } + + if ((status & FDCAN_INT_BO) != 0) + { + /* Bus_Off Status changed */ + + if ((psr & FDCAN_PSR_BO) != 0) + { + errbits |= CAN_ERR_BUSOFF; + } + else + { + errbits |= CAN_ERR_RESTARTED; + } + } + + if ((status & (FDCAN_INT_RF0L | FDCAN_INT_RF1L)) != 0) + { + /* Receive FIFO 0/1 Message Lost + * Receive FIFO 1 Message Lost + */ + + errbits |= CAN_ERR_CRTL; + data[1] |= CAN_ERR_CRTL_RX_OVERFLOW; + } + + if ((status & FDCAN_INT_TEFL) != 0) + { + /* Tx Event FIFO Element Lost */ + + errbits |= CAN_ERR_CRTL; + data[1] |= CAN_ERR_CRTL_TX_OVERFLOW; + } + + if ((status & FDCAN_INT_TOO) != 0) + { + /* Timeout Occurred */ + + errbits |= CAN_ERR_TX_TIMEOUT; + } + + if ((status & (FDCAN_INT_MRAF | FDCAN_INT_ELO)) != 0) + { + /* Message RAM Access Failure + * Error Logging Overflow + */ + + errbits |= CAN_ERR_CRTL; + data[1] |= CAN_ERR_CRTL_UNSPEC; + } + + if (errbits != 0) + { + nerr("ERROR: errbits = %08" PRIx16 "\n", errbits); + + /* Copy frame */ + + frame->can_id = errbits; + frame->can_dlc = CAN_ERR_DLC; + + memcpy(frame->data, data, CAN_ERR_DLC); + + /* Copy the buffer pointer to priv->dev.. Set amount of data + * in priv->dev.d_len + */ + + priv->dev.d_len = sizeof(struct can_frame); + priv->dev.d_buf = (uint8_t *)frame; + + /* Send to socket interface */ + + NETDEV_ERRORS(&priv->dev); + + can_input(&priv->dev); + + /* Point the packet buffer back to the next Tx buffer that will be + * used during the next write. If the write queue is full, then + * this will point at an active buffer, which must not be written + * to. This is OK because devif_poll won't be called unless the + * queue is not full. + */ + + priv->dev.d_buf = (uint8_t *)priv->txdesc; + } +} +#endif /* CONFIG_NET_CAN_ERRORS */ + +/**************************************************************************** + * Name: fdcan_receive + * + * Description: + * Receive an FDCAN messages + * + * Input Parameters: + * dev - CAN-common state data + * rxbuffer - The RX buffer containing the received messages + * nwords - The length of the RX buffer (element size in words). + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void fdcan_receive(struct stm32_fdcan_s *priv, + volatile uint32_t *rxbuffer, + unsigned long nwords) +{ + fdcan_dumprxregs(dev->cd_priv, "Before receive"); + + /* CAN 2.0 or CAN FD */ + +#ifdef CONFIG_NET_CAN_CANFD + if ((rxbuffer[1] & BUFFER_R1_FDF) != 0) + { + struct canfd_frame *frame = (struct canfd_frame *)priv->rxdesc; + + /* Format the CAN FD header */ + + /* Extract the RTR bit */ + + if ((rxbuffer[0] & BUFFER_R0_RTR) != 0) + { + frame->can_id |= CAN_RTR_FLAG; + } + +#ifdef CONFIG_NET_CAN_EXTID + if ((rxbuffer[0] & BUFFER_R0_XTD) != 0) + { + /* Save the extended ID of the newly received message */ + + frame->can_id = ((rxbuffer[0] & BUFFER_R0_EXTID_MASK) >> + BUFFER_R0_EXTID_SHIFT); + frame->can_id |= CAN_EFF_FLAG; + } + else + { + frame->can_id = ((rxbuffer[0] & BUFFER_R0_STDID_MASK) >> + BUFFER_R0_STDID_SHIFT); + frame->can_id &= ~CAN_EFF_FLAG; + } +#else + if ((rxbuffer[0] & BUFFER_R0_XTD) != 0) + { + /* Drop any messages with extended IDs */ + + return; + } + + /* Save the standard ID of the newly received message */ + + frame->can_id = ((rxbuffer[0] & BUFFER_R0_STDID_MASK) >> + BUFFER_R0_STDID_SHIFT); +#endif + + /* Word R1 contains the DLC and timestamp */ + + frame->len = g_can_dlc_to_len[((rxbuffer[1] & BUFFER_R1_DLC_MASK) >> + BUFFER_R1_DLC_SHIFT)]; + + /* Get CANFD flags */ + + frame->flags = 0; + + if ((rxbuffer[0] & BUFFER_R0_ESI) != 0) + { + frame->flags |= CANFD_ESI; + } + + if ((rxbuffer[1] & BUFFER_R1_BRS) != 0) + { + frame->flags |= CANFD_BRS; + } + + /* Save the message data */ + + memcpy(frame->data, (void *)&rxbuffer[2], frame->len); + + /* Copy the buffer pointer to priv->dev.. Set amount of data + * in priv->dev.d_len + */ + + priv->dev.d_len = sizeof(struct canfd_frame); + priv->dev.d_buf = (uint8_t *)frame; + } + else +#endif + { + struct can_frame *frame = (struct can_frame *)priv->rxdesc; + + /* Format the CAN header */ + + /* Extract the RTR bit */ + + if ((rxbuffer[0] & BUFFER_R0_RTR) != 0) + { + frame->can_id |= CAN_RTR_FLAG; + } + +#ifdef CONFIG_NET_CAN_EXTID + if ((rxbuffer[0] & BUFFER_R0_XTD) != 0) + { + /* Save the extended ID of the newly received message */ + + frame->can_id = ((rxbuffer[0] & BUFFER_R0_EXTID_MASK) >> + BUFFER_R0_EXTID_SHIFT); + frame->can_id |= CAN_EFF_FLAG; + } + else + { + frame->can_id = ((rxbuffer[0] & BUFFER_R0_STDID_MASK) >> + BUFFER_R0_STDID_SHIFT); + frame->can_id &= ~CAN_EFF_FLAG; + } +#else + if ((rxbuffer[0] & BUFFER_R0_XTD) != 0) + { + /* Drop any messages with extended IDs */ + + return; + } + + /* Save the standard ID of the newly received message */ + + frame->can_id = ((rxbuffer[0] & BUFFER_R0_STDID_MASK) >> + BUFFER_R0_STDID_SHIFT); +#endif + + /* Word R1 contains the DLC and timestamp */ + + frame->can_dlc = ((rxbuffer[1] & BUFFER_R1_DLC_MASK) >> + BUFFER_R1_DLC_SHIFT); + + /* Save the message data */ + + memcpy(frame->data, (void *)&rxbuffer[2], frame->can_dlc); + + /* Copy the buffer pointer to priv->dev.. Set amount of data + * in priv->dev.d_len + */ + + priv->dev.d_len = sizeof(struct can_frame); + priv->dev.d_buf = (uint8_t *)frame; + } + + /* Send to socket interface */ + + NETDEV_RXPACKETS(&priv->dev); + + can_input(&priv->dev); + + /* Point the packet buffer back to the next Tx buffer that will be + * used during the next write. If the write queue is full, then + * this will point at an active buffer, which must not be written + * to. This is OK because devif_poll won't be called unless the + * queue is not full. + */ + + priv->dev.d_buf = (uint8_t *)priv->txdesc; +} + +/**************************************************************************** + * Name: fdcan_interrupt + * + * Description: + * Common FDCAN interrupt handler + * + * irq - The IRQ number of the interrupt. + * context - The register state save array at the time of the interrupt. + * + * Returned Value: + * Zero on success; a negated errno on failure + * + ****************************************************************************/ + +static int fdcan_interrupt(int irq, void *context, void *arg) +{ + struct stm32_fdcan_s *priv = (struct stm32_fdcan_s *)arg; + uint32_t pending = 0; + + DEBUGASSERT(priv != NULL); + + /* Get the set of pending interrupts. */ + + pending = fdcan_getreg(priv, STM32_FDCAN_IR_OFFSET); + +#ifdef CONFIG_NET_CAN_ERRORS + /* Check for any errors */ + + if ((pending & FDCAN_ANYERR_INTS) != 0) + { + /* Disable further CAN ERROR interrupts and schedule to perform the + * interrupt processing on the worker thread + */ + + fdcan_errint(priv, false); + work_queue(CANWORK, &priv->irqwork, fdcan_error_work, priv, 0); + } +#endif + + /* Check for successful completion of a transmission */ + + if ((pending & FDCAN_INT_TC) != 0) + { + /* Disable further TX CAN interrupts. here can be no race + * condition here. + */ + + fdcan_txint(priv, false); + work_queue(CANWORK, &priv->irqwork, fdcan_txdone_work, priv, 0); + } + else if ((pending & FDCAN_TXFIFOQ_INTS) != 0) + { + /* Clear unhandled TX events */ + + fdcan_putreg(priv, STM32_FDCAN_IR_OFFSET, FDCAN_TXFIFOQ_INTS); + } + + if (pending & FDCAN_INT_RF1N) + { + /* Disable further CAN RX interrupts and schedule to perform the + * interrupt processing on the worker thread + */ + + fdcan_rx1int(priv, false); + work_queue(CANWORK, &priv->irqwork, + fdcan_rx1interrupt_work, priv, 0); + } + + /* Clear the RX FIFO0 new message interrupt */ + + if (pending & FDCAN_INT_RF0N) + { + /* Disable further CAN RX interrupts and schedule to perform the + * interrupt processing on the worker thread + */ + + fdcan_rx0int(priv, false); + work_queue(CANWORK, &priv->irqwork, + fdcan_rx0interrupt_work, priv, 0); + } + + return OK; +} + +/**************************************************************************** + * Name: fdcan_hw_initialize + * + * Description: + * FDCAN hardware initialization + * + * Input Parameters: + * priv - A pointer to the private data structure for this FDCAN peripheral + * + * Returned Value: + * Zero on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int fdcan_hw_initialize(struct stm32_fdcan_s *priv) +{ + const struct stm32_config_s *config = NULL; + volatile uint32_t *msgram = NULL; + uint32_t regval = 0; + uint32_t cntr = 0; + + DEBUGASSERT(priv); + config = priv->config; + DEBUGASSERT(config); + + ninfo("FDCAN%d\n", config->port); + + /* Clean message RAM */ + + msgram = config->msgram.stdfilters; + cntr = (FDCAN_MSGRAM_WORDS + 1); + while (cntr > 0) + { + *msgram++ = 0; + cntr--; + } + + /* Configure FDCAN pins */ + + stm32_configgpio(config->rxpinset); + stm32_configgpio(config->txpinset); + + /* Re-enable device if previously disabled in fdcan_shutdown() */ + + if (priv->state == FDCAN_STATE_DISABLED) + { + /* Reset Clock Stop Request bit */ + + regval = fdcan_getreg(priv, STM32_FDCAN_CCCR_OFFSET); + regval &= ~FDCAN_CCCR_CSR; + fdcan_putreg(priv, STM32_FDCAN_CCCR_OFFSET, regval); + + /* Wait for Clock Stop Acknowledge bit reset to indicate + * device is operational + */ + + while ((fdcan_getreg(priv, STM32_FDCAN_CCCR_OFFSET) & FDCAN_CCCR_CSA) + != 0); + } + + /* Enable the Initialization state */ + + regval = fdcan_getreg(priv, STM32_FDCAN_CCCR_OFFSET); + regval |= FDCAN_CCCR_INIT; + fdcan_putreg(priv, STM32_FDCAN_CCCR_OFFSET, regval); + + /* Wait for initialization mode to take effect */ + + while ((fdcan_getreg(priv, STM32_FDCAN_CCCR_OFFSET) & FDCAN_CCCR_INIT) + == 0); + + /* Enable writing to configuration registers */ + + regval = fdcan_getreg(priv, STM32_FDCAN_CCCR_OFFSET); + regval |= FDCAN_CCCR_CCE; + fdcan_putreg(priv, STM32_FDCAN_CCCR_OFFSET, regval); + + /* Global Filter Configuration: + * + * ANFS=0: Store all non matching standard frame in RX FIFO0 + * ANFE=0: Store all non matching extended frame in RX FIFO0 + */ + + regval = FDCAN_RXGFC_ANFE_RX_FIFO0 | FDCAN_RXGFC_ANFS_RX_FIFO0; + fdcan_putreg(priv, STM32_FDCAN_RXGFC_OFFSET, regval); + + /* Extended ID Filter AND mask */ + + fdcan_putreg(priv, STM32_FDCAN_XIDAM_OFFSET, 0x1fffffff); + + /* Disable all interrupts */ + + fdcan_putreg(priv, STM32_FDCAN_IE_OFFSET, 0); + fdcan_putreg(priv, STM32_FDCAN_TXBTIE_OFFSET, 0); + + /* All interrupts directed to Line 0. But disable both interrupt lines 0 + * and 1 for now. + * + * REVISIT: Only interrupt line 0 is used by this driver. + */ + + fdcan_putreg(priv, STM32_FDCAN_ILS_OFFSET, 0); + fdcan_putreg(priv, STM32_FDCAN_ILE_OFFSET, 0); + + /* Clear all pending interrupts. */ + + fdcan_putreg(priv, STM32_FDCAN_IR_OFFSET, FDCAN_INT_ALL); + + /* Configure FDCAN bit timing */ + + fdcan_putreg(priv, STM32_FDCAN_NBTP_OFFSET, priv->nbtp); + fdcan_putreg(priv, STM32_FDCAN_DBTP_OFFSET, priv->dbtp); + + /* Configure message RAM starting addresses and sizes. */ + + regval = FDCAN_RXGFC_LSS(config->nstdfilters); + regval |= FDCAN_RXGFC_LSE(config->nextfilters); + fdcan_putreg(priv, STM32_FDCAN_RXGFC_OFFSET, regval); + + /* Dump RAM layout */ + + fdcan_dumpramlayout(priv); + + /* Configure Message Filters */ + + /* Disable all standard filters */ + + msgram = config->msgram.stdfilters; + cntr = config->nstdfilters; + while (cntr > 0) + { + *msgram++ = STDFILTER_S0_SFEC_DISABLE; + cntr--; + } + + /* Disable all extended filters */ + + msgram = config->msgram.extfilters; + cntr = config->nextfilters; + while (cntr > 0) + { + *msgram = EXTFILTER_F0_EFEC_DISABLE; + msgram = msgram + 2; + cntr--; + } + + /* Input clock divider configuration */ + + regval = FDCANCLK_PDIV; + fdcan_putreg(priv, STM32_FDCAN_CKDIV_OFFSET, regval); + + /* CC control register */ + + regval = fdcan_getreg(priv, STM32_FDCAN_CCCR_OFFSET); + regval &= ~(FDCAN_CCCR_NISO | FDCAN_CCCR_FDOE | FDCAN_CCCR_BRSE); + + /* Select ISO11898-1 or Non ISO Bosch CAN FD Specification V1.0 */ + + switch (config->format) + { + case FDCAN_ISO11898_1_FORMAT: + { + break; + } + + case FDCAN_NONISO_BOSCH_V1_FORMAT: + { + regval |= FDCAN_CCCR_NISO; + break; + } + + default: + { + return -EINVAL; + } + } + + /* Select Classic CAN mode or FD mode with or without fast bit rate + * switching + */ + + switch (config->mode) + { + case FDCAN_CLASSIC_MODE: + { + break; + } + +#ifdef CONFIG_NET_CAN_CANFD + case FDCAN_FD_MODE: + { + regval |= FDCAN_CCCR_FDOE; + break; + } + + case FDCAN_FD_BRS_MODE: + { + regval |= (FDCAN_CCCR_FDOE | FDCAN_CCCR_BRSE); + break; + } +#endif + + default: + { + return -EINVAL; + } + } + + /* Set the initial CAN mode */ + + fdcan_putreg(priv, STM32_FDCAN_CCCR_OFFSET, regval); + + /* Enable FIFO/Queue mode */ + + regval = fdcan_getreg(priv, STM32_FDCAN_TXBC_OFFSET); +#ifdef CONFIG_STM32_FDCAN_QUEUE_MODE + regval |= FDCAN_TXBC_TFQM; +#else + regval &= ~FDCAN_TXBC_TFQM; +#endif + fdcan_putreg(priv, STM32_FDCAN_TXBC_OFFSET, regval); + +#ifdef STM32_FDCAN_LOOPBACK + /* Is loopback mode selected for this peripheral? */ + + if (config->loopback) + { + /* FDCAN_CCCR_TEST - Test mode enable + * FDCAN_CCCR_MON - Bus monitoring mode (for internal loopback) + * FDCAN_TEST_LBCK - Loopback mode + */ + + regval = fdcan_getreg(priv, STM32_FDCAN_CCCR_OFFSET); + regval |= (FDCAN_CCCR_TEST | FDCAN_CCCR_MON); + fdcan_putreg(priv, STM32_FDCAN_CCCR_OFFSET, regval); + + regval = fdcan_getreg(priv, STM32_FDCAN_TEST_OFFSET); + regval |= FDCAN_TEST_LBCK; + fdcan_putreg(priv, STM32_FDCAN_TEST_OFFSET, regval); + } +#endif + + /* Configure interrupt lines */ + + /* Direct all interrupts to Line 0. + * + * Bits in the ILS register correspond to each FDCAN interrupt; A bit + * set to '1' is directed to interrupt line 1; a bit cleared to '0' + * is directed interrupt line 0. + * + * REVISIT: Nothing is done here. Only interrupt line 0 is used by + * this driver and ILS was already cleared above. + */ + + /* Enable only interrupt line 0. */ + + fdcan_putreg(priv, STM32_FDCAN_ILE_OFFSET, FDCAN_ILE_EINT0); + + /* Disable initialization mode to enable normal operation */ + + regval = fdcan_getreg(priv, STM32_FDCAN_CCCR_OFFSET); + regval &= ~FDCAN_CCCR_INIT; + fdcan_putreg(priv, STM32_FDCAN_CCCR_OFFSET, regval); + + return OK; +} + +/**************************************************************************** + * Function: fdcan_ifup + * + * Description: + * NuttX Callback: Bring up the Ethernet interface when an IP address is + * provided + * + * Input Parameters: + * dev - Reference to the NuttX driver state structure + * + * Returned Value: + * None + * + * Assumptions: + * + ****************************************************************************/ + +static int fdcan_ifup(struct net_driver_s *dev) +{ + struct stm32_fdcan_s *priv = + (struct stm32_fdcan_s *)dev->d_private; + const struct stm32_config_s *config = NULL; + + DEBUGASSERT(priv); + config = priv->config; + DEBUGASSERT(config); + + /* Setup CAN */ + + fdcan_setup(priv); + + /* Enable interrupts */ + + fdcan_rx0int(priv, true); + fdcan_rx1int(priv, true); + fdcan_txint(priv, true); +#ifdef CONFIG_NET_CAN_ERRORS + fdcan_errint(priv, true); +#endif + + /* Enable the interrupts at the NVIC */ + + up_enable_irq(config->irq0); + up_enable_irq(config->irq1); + + priv->bifup = true; + + priv->txdesc = (struct can_frame *)priv->tx_pool; + priv->rxdesc = (struct can_frame *)priv->rx_pool; + + priv->dev.d_buf = (uint8_t *)priv->txdesc; + + return OK; +} + +/**************************************************************************** + * Function: fdcan_ifdown + * + * Description: + * NuttX Callback: Stop the interface. + * + * Input Parameters: + * dev - Reference to the NuttX driver state structure + * + * Returned Value: + * None + * + * Assumptions: + * + ****************************************************************************/ + +static int fdcan_ifdown(struct net_driver_s *dev) +{ + struct stm32_fdcan_s *priv = + (struct stm32_fdcan_s *)dev->d_private; + + /* Disable CAN interrupts */ + + fdcan_shutdown(priv); + + /* Reset CAN */ + + fdcan_reset(priv); + + return OK; +} + +/**************************************************************************** + * Function: fdcan_txpoll + * + * Description: + * The transmitter is available, check if the network has any outgoing + * packets ready to send. This is a callback from devif_poll(). + * devif_poll() may be called: + * + * 1. When the preceding TX packet send is complete, + * 2. When the preceding TX packet send timesout and the interface is reset + * 3. During normal TX polling + * + * Input Parameters: + * dev - Reference to the NuttX driver state structure + * + * Returned Value: + * OK on success; a negated errno on failure + * + * Assumptions: + * May or may not be called from an interrupt handler. In either case, + * global interrupts are disabled, either explicitly or indirectly through + * interrupt handling logic. + * + ****************************************************************************/ + +static int fdcan_txpoll(struct net_driver_s *dev) +{ + struct stm32_fdcan_s *priv = + (struct stm32_fdcan_s *)dev->d_private; + + /* If the polling resulted in data that should be sent out on the network, + * the field d_len is set to a value > 0. + */ + + if (priv->dev.d_len > 0) + { + fdcan_txdone(priv); + + /* Send the packet */ + + fdcan_send(priv); + + /* Check if there is room in the device to hold another packet. If + * not, return a non-zero value to terminate the poll. + */ + + if (fdcan_txready(priv) == false) + { + return -EBUSY; + } + } + + /* If zero is returned, the polling will continue until all connections + * have been examined. + */ + + return 0; +} + +/**************************************************************************** + * Function: fdcan_txavail_work + * + * Description: + * Perform an out-of-cycle poll on the worker thread. + * + * Input Parameters: + * arg - Reference to the NuttX driver state structure (cast to void*) + * + * Returned Value: + * None + * + * Assumptions: + * Called on the higher priority worker thread. + * + ****************************************************************************/ + +static void fdcan_txavail_work(void *arg) +{ + struct stm32_fdcan_s *priv = (struct stm32_fdcan_s *)arg; + + /* Ignore the notification if the interface is not yet up */ + + net_lock(); + if (priv->bifup) + { + /* Check if there is room in the hardware to hold another outgoing + * packet. + */ + + if (fdcan_txready(priv)) + { + /* No, there is space for another transfer. Poll the network for + * new XMIT data. + */ + + devif_poll(&priv->dev, fdcan_txpoll); + } + } + + net_unlock(); +} + +/**************************************************************************** + * Function: fdcan_txavail + * + * Description: + * Driver callback invoked when new TX data is available. This is a + * stimulus perform an out-of-cycle poll and, thereby, reduce the TX + * latency. + * + * Input Parameters: + * dev - Reference to the NuttX driver state structure + * + * Returned Value: + * None + * + * Assumptions: + * Called in normal user mode + * + ****************************************************************************/ + +static int fdcan_txavail(struct net_driver_s *dev) +{ + struct stm32_fdcan_s *priv = + (struct stm32_fdcan_s *)dev->d_private; + + /* Is our single work structure available? It may not be if there are + * pending interrupt actions and we will have to ignore the Tx + * availability action. + */ + + if (work_available(&priv->pollwork)) + { + /* Schedule to serialize the poll on the worker thread. */ + + fdcan_txavail_work(priv); + } + + return OK; +} + +/**************************************************************************** + * Function: fdcan_ioctl + * + * Description: + * PHY ioctl command handler + * + * Input Parameters: + * dev - Reference to the NuttX driver state structure + * cmd - ioctl command + * arg - Argument accompanying the command + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + * Assumptions: + * + ****************************************************************************/ + +#ifdef CONFIG_NETDEV_IOCTL +static int fdcan_netdev_ioctl(struct net_driver_s *dev, int cmd, + unsigned long arg); +{ + struct stm32_fdcan_s *priv = + (struct stm32_fdcan_s *)dev->d_private; + int ret = OK; + + DEBUGASSERT(priv); + + switch (cmd) + { + /* TODO */ + + default: + ret = -ENOTTY; + break; + } + + return ret; +} +#endif /* CONFIG_NETDEV_IOCTL */ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_cansockinitialize + * + * Description: + * Initialize the selected FDCAN port as CAN socket interface + * + * Input Parameters: + * Port number (for hardware that has multiple FDCAN interfaces) + * + * Returned Value: + * OK on success; Negated errno on failure. + * + ****************************************************************************/ + +int stm32_fdcansockinitialize(int port) +{ + struct stm32_fdcan_s *priv = NULL; + const struct stm32_config_s *config = NULL; + int ret = OK; + + ninfo("FDCAN%d\n", port); + + /* Select FDCAN peripheral to be initialized */ + +#ifdef CONFIG_STM32_FDCAN1 + if (port == FDCAN1) + { + /* Select the FDCAN1 device structure */ + + priv = &g_fdcan1priv; + config = &g_fdcan1const; + } + else +#endif + { + nerr("ERROR: Unsupported port %d\n", port); + ret = -EINVAL; + goto errout; + } + + /* Perform one time data initialization */ + + memset(priv, 0, sizeof(struct stm32_fdcan_s)); + priv->config = config; + + /* Set the initial bit timing. This might change subsequently + * due to IOCTL command processing. + */ + + priv->nbtp = config->nbtp; + priv->dbtp = config->dbtp; + + /* Initialize the driver structure */ + + priv->dev.d_ifup = fdcan_ifup; + priv->dev.d_ifdown = fdcan_ifdown; + priv->dev.d_txavail = fdcan_txavail; +#ifdef CONFIG_NETDEV_IOCTL + priv->dev.d_ioctl = fdcan_netdev_ioctl; +#endif + priv->dev.d_private = priv; + + /* Put the interface in the down state. This usually amounts to resetting + * the device and/or calling fdcan_ifdown(). + */ + + ninfo("callbacks done\n"); + + fdcan_ifdown(&priv->dev); + + /* Register the device with the OS so that socket IOCTLs can be performed */ + + ret = netdev_register(&priv->dev, NET_LL_CAN); + +errout: + return ret; +} + +/**************************************************************************** + * Name: arm_netinitialize + * + * Description: + * Initialize the CAN device interfaces. If there is more than one device + * interface in the chip, then board-specific logic will have to provide + * this function to determine which, if any, CAN interfaces should be + * initialized. + * + ****************************************************************************/ + +#if !defined(CONFIG_NETDEV_LATEINIT) +void arm_netinitialize(void) +{ +#ifdef CONFIG_STM32_CAN1 + stm32_fdcansockinitialize(FDCAN1); +#endif +} +#endif diff --git a/arch/arm/src/common/stm32/stm32_fdcan_m3m4_v1.c b/arch/arm/src/common/stm32/stm32_fdcan_m3m4_v1.c new file mode 100644 index 0000000000000..4e23a563b1c91 --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_fdcan_m3m4_v1.c @@ -0,0 +1,3550 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_fdcan_m3m4_v1.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + *s + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include "arm_internal.h" +#include "stm32_fdcan.h" +#include "hardware/stm32_pinmap.h" +#include "stm32_gpio.h" +#include "stm32_rcc.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Clock source *************************************************************/ + +#define FDCANCLK_PDIV (0) + +#if FDCANCLK_PDIV == 0 +# define STM32_FDCANCLK_FREQUENCY (STM32_FDCAN_FREQUENCY / (1)) +#else +# define STM32_FDCANCLK_FREQUENCY (STM32_FDCAN_FREQUENCY / (2 * FDCANCLK_PDIV)) +#endif + +/* General Configuration ****************************************************/ + +#if defined(CONFIG_STM32_STM32G4XXX) + +/* FDCAN Message RAM */ + +# define FDCAN_MSGRAM_WORDS (212) +# define STM32_CANRAM1_BASE (STM32_CANRAM_BASE + 0x0000) +# define STM32_CANRAM2_BASE (STM32_CANRAM_BASE + 1*(FDCAN_MSGRAM_WORDS * 4) + 4) +# define STM32_CANRAM3_BASE (STM32_CANRAM_BASE + 2*(FDCAN_MSGRAM_WORDS * 4) + 4) + +# ifdef CONFIG_STM32_FDCAN1 +# define FDCAN1_STDFILTER_SIZE (28) +# define FDCAN1_EXTFILTER_SIZE (8) +# define FDCAN1_RXFIFO0_SIZE (3) +# define FDCAN1_RXFIFO1_SIZE (3) +# define FDCAN1_TXEVENTFIFO_SIZE (3) +# define FDCAN1_TXFIFIOQ_SIZE (3) + +# define FDCAN1_STDFILTER_WORDS (28) +# define FDCAN1_EXTFILTER_WORDS (16) +# define FDCAN1_RXFIFO0_WORDS (54) +# define FDCAN1_RXFIFO1_WORDS (54) +# define FDCAN1_TXEVENTFIFO_WORDS (6) +# define FDCAN1_TXFIFIOQ_WORDS (54) +# endif +# ifdef CONFIG_STM32_FDCAN2 +# define FDCAN2_STDFILTER_SIZE (28) +# define FDCAN2_EXTFILTER_SIZE (8) +# define FDCAN2_RXFIFO0_SIZE (3) +# define FDCAN2_RXFIFO1_SIZE (3) +# define FDCAN2_TXEVENTFIFO_SIZE (3) +# define FDCAN2_TXFIFIOQ_SIZE (3) + +# define FDCAN2_STDFILTER_WORDS (28) +# define FDCAN2_EXTFILTER_WORDS (16) +# define FDCAN2_RXFIFO0_WORDS (54) +# define FDCAN2_RXFIFO1_WORDS (54) +# define FDCAN2_TXEVENTFIFO_WORDS (6) +# define FDCAN2_TXFIFIOQ_WORDS (54) +# endif +# ifdef CONFIG_STM32_FDCAN3 +# define FDCAN3_STDFILTER_SIZE (28) +# define FDCAN3_EXTFILTER_SIZE (8) +# define FDCAN3_RXFIFO0_SIZE (3) +# define FDCAN3_RXFIFO1_SIZE (3) +# define FDCAN3_TXEVENTFIFO_SIZE (3) +# define FDCAN3_TXFIFIOQ_SIZE (3) + +# define FDCAN3_STDFILTER_WORDS (28) +# define FDCAN3_EXTFILTER_WORDS (16) +# define FDCAN3_RXFIFO0_WORDS (54) +# define FDCAN3_RXFIFO1_WORDS (54) +# define FDCAN3_TXEVENTFIFO_WORDS (6) +# define FDCAN3_TXFIFIOQ_WORDS (54) +# endif +#else +# error +#endif + +/* FDCAN1 Configuration *****************************************************/ + +#ifdef CONFIG_STM32_FDCAN1 + +/* Bit timing */ + +# define FDCAN1_NTSEG1 (CONFIG_STM32_FDCAN1_NTSEG1 - 1) +# define FDCAN1_NTSEG2 (CONFIG_STM32_FDCAN1_NTSEG2 - 1) +# define FDCAN1_NBRP ((STM32_FDCANCLK_FREQUENCY / \ + ((FDCAN1_NTSEG1 + FDCAN1_NTSEG2 + 3) * \ + CONFIG_STM32_FDCAN1_BITRATE)) - 1) +# define FDCAN1_NSJW (CONFIG_STM32_FDCAN1_NSJW - 1) + +# if FDCAN1_NTSEG1 > FDCAN_NBTP_NTSEG1_MAX +# error Invalid FDCAN1 NTSEG1 +# endif +# if FDCAN1_NTSEG2 > FDCAN_NBTP_NTSEG2_MAX +# error Invalid FDCAN1 NTSEG2 +# endif +# if FDCAN1_NSJW > FDCAN_NBTP_NSJW_MAX +# error Invalid FDCAN1 NSJW +# endif +# if FDCAN1_NBRP > FDCAN_NBTP_NBRP_MAX +# error Invalid FDCAN1 NBRP +# endif + +# ifdef CONFIG_STM32_FDCAN1_FD_BRS +# define FDCAN1_DTSEG1 (CONFIG_STM32_FDCAN1_DTSEG1 - 1) +# define FDCAN1_DTSEG2 (CONFIG_STM32_FDCAN1_DTSEG2 - 1) +# define FDCAN1_DBRP ((STM32_FDCANCLK_FREQUENCY / \ + ((FDCAN1_DTSEG1 + FDCAN1_DTSEG2 + 3) * \ + CONFIG_STM32_FDCAN1_DBITRATE)) - 1) +# define FDCAN1_DSJW (CONFIG_STM32_FDCAN1_DSJW - 1) +# else +# define FDCAN1_DTSEG1 1 +# define FDCAN1_DTSEG2 1 +# define FDCAN1_DBRP 1 +# define FDCAN1_DSJW 1 +# endif /* CONFIG_STM32_FDCAN1_FD_BRS */ + +# if FDCAN1_DTSEG1 > FDCAN_DBTP_DTSEG1_MAX +# error Invalid FDCAN1 DTSEG1 +# endif +# if FDCAN1_DTSEG2 > FDCAN_DBTP_DTSEG2_MAX +# error Invalid FDCAN1 DTSEG2 +# endif +# if FDCAN1_DBRP > FDCAN_DBTP_DBRP_MAX +# error Invalid FDCAN1 DBRP +# endif +# if FDCAN1_DSJW > FDCAN_DBTP_DSJW_MAX +# error Invalid FDCAN1 DSJW +# endif + +/* FDCAN1 Message RAM Configuration *****************************************/ + +/* FDCAN1 Message RAM Layout */ + +# define FDCAN1_STDFILTER_INDEX 0 +# define FDCAN1_EXTFILTERS_INDEX (FDCAN1_STDFILTER_INDEX + FDCAN1_STDFILTER_WORDS) +# define FDCAN1_RXFIFO0_INDEX (FDCAN1_EXTFILTERS_INDEX + FDCAN1_EXTFILTER_WORDS) +# define FDCAN1_RXFIFO1_INDEX (FDCAN1_RXFIFO0_INDEX + FDCAN1_RXFIFO0_WORDS) +# define FDCAN1_TXEVENTFIFO_INDEX (FDCAN1_RXFIFO1_INDEX + FDCAN1_RXFIFO1_WORDS) +# define FDCAN1_TXFIFOQ_INDEX (FDCAN1_TXEVENTFIFO_INDEX + FDCAN1_TXEVENTFIFO_WORDS) +# define FDCAN1_MSGRAM_WORDS (FDCAN1_TXFIFOQ_INDEX + FDCAN1_TXFIFIOQ_WORDS) + +#endif /* CONFIG_STM32_FDCAN1 */ + +/* FDCAN2 Configuration *****************************************************/ + +#ifdef CONFIG_STM32_FDCAN2 + +/* Bit timing */ + +# define FDCAN2_NTSEG1 (CONFIG_STM32_FDCAN2_NTSEG1 - 1) +# define FDCAN2_NTSEG2 (CONFIG_STM32_FDCAN2_NTSEG2 - 1) +# define FDCAN2_NBRP (((STM32_FDCANCLK_FREQUENCY / \ + ((FDCAN2_NTSEG1 + FDCAN2_NTSEG2 + 3) * \ + CONFIG_STM32_FDCAN2_BITRATE)) - 1)) +# define FDCAN2_NSJW (CONFIG_STM32_FDCAN2_NSJW - 1) + +# if FDCAN2_NTSEG1 > FDCAN_NBTP_NTSEG1_MAX +# error Invalid FDCAN2 NTSEG1 +# endif +# if FDCAN2_NTSEG2 > FDCAN_NBTP_NTSEG2_MAX +# error Invalid FDCAN2 NTSEG2 +# endif +# if FDCAN2_NSJW > FDCAN_NBTP_NSJW_MAX +# error Invalid FDCAN2 NSJW +# endif +# if FDCAN2_NBRP > FDCAN_NBTP_NBRP_MAX +# error Invalid FDCAN1 NBRP +# endif + +# ifdef CONFIG_STM32_FDCAN2_FD_BRS +# define FDCAN2_DTSEG1 (CONFIG_STM32_FDCAN2_DTSEG1 - 1) +# define FDCAN2_DTSEG2 (CONFIG_STM32_FDCAN2_DTSEG2 - 1) +# define FDCAN2_DBRP (((STM32_FDCANCLK_FREQUENCY / \ + ((FDCAN2_DTSEG1 + FDCAN2_DTSEG2 + 3) * \ + CONFIG_STM32_FDCAN2_DBITRATE)) - 1)) +# define FDCAN2_DSJW (CONFIG_STM32_FDCAN2_DSJW - 1) +# else +# define FDCAN2_DTSEG1 1 +# define FDCAN2_DTSEG2 1 +# define FDCAN2_DBRP 1 +# define FDCAN2_DSJW 1 +# endif /* CONFIG_STM32_FDCAN2_FD_BRS */ + +# if FDCAN2_DTSEG1 > FDCAN_DBTP_DTSEG1_MAX +# error Invalid FDCAN2 DTSEG1 +# endif +# if FDCAN2_DTSEG2 > FDCAN_DBTP_DTSEG2_MAX +# error Invalid FDCAN2 DTSEG2 +# endif +# if FDCAN2_DBRP > FDCAN_DBTP_DBRP_MAX +# error Invalid FDCAN2 DBRP +# endif +# if FDCAN2_DSJW > FDCAN_DBTP_DSJW_MAX +# error Invalid FDCAN2 DSJW +# endif + +/* FDCAN2 Message RAM Configuration *****************************************/ + +/* FDCAN2 Message RAM Layout */ + +# define FDCAN2_STDFILTER_INDEX 0 +# define FDCAN2_EXTFILTERS_INDEX (FDCAN2_STDFILTER_INDEX + FDCAN2_STDFILTER_WORDS) +# define FDCAN2_RXFIFO0_INDEX (FDCAN2_EXTFILTERS_INDEX + FDCAN2_EXTFILTER_WORDS) +# define FDCAN2_RXFIFO1_INDEX (FDCAN2_RXFIFO0_INDEX + FDCAN2_RXFIFO0_WORDS) +# define FDCAN2_TXEVENTFIFO_INDEX (FDCAN2_RXFIFO1_INDEX + FDCAN2_RXFIFO1_WORDS) +# define FDCAN2_TXFIFOQ_INDEX (FDCAN2_TXEVENTFIFO_INDEX + FDCAN2_TXEVENTFIFO_WORDS) +# define FDCAN2_MSGRAM_WORDS (FDCAN2_TXFIFOQ_INDEX + FDCAN2_TXFIFIOQ_WORDS) + +#endif /* CONFIG_STM32_FDCAN2 */ + +/* FDCAN3 Configuration *****************************************************/ + +#ifdef CONFIG_STM32_FDCAN3 + +/* Bit timing */ + +# define FDCAN3_NTSEG1 (CONFIG_STM32_FDCAN3_NTSEG1 - 1) +# define FDCAN3_NTSEG2 (CONFIG_STM32_FDCAN3_NTSEG2 - 1) +# define FDCAN3_NBRP (((STM32_FDCANCLK_FREQUENCY / \ + ((FDCAN3_NTSEG1 + FDCAN3_NTSEG2 + 3) * \ + CONFIG_STM32_FDCAN3_BITRATE)) - 1)) +# define FDCAN3_NSJW (CONFIG_STM32_FDCAN3_NSJW - 1) + +# if FDCAN3_NTSEG1 > FDCAN_NBTP_NTSEG1_MAX +# error Invalid FDCAN3 NTSEG1 +# endif +# if FDCAN3_NTSEG2 > FDCAN_NBTP_NTSEG2_MAX +# error Invalid FDCAN3 NTSEG2 +# endif +# if FDCAN3_NSJW > FDCAN_NBTP_NSJW_MAX +# error Invalid FDCAN3 NSJW +# endif +# if FDCAN3_NBRP > FDCAN_NBTP_NBRP_MAX +# error Invalid FDCAN1 NBRP +# endif + +# ifdef CONFIG_STM32_FDCAN3_FD_BRS +# define FDCAN3_DTSEG1 (CONFIG_STM32_FDCAN3_DTSEG1 - 1) +# define FDCAN3_DTSEG2 (CONFIG_STM32_FDCAN3_DTSEG2 - 1) +# define FDCAN3_DBRP (((STM32_FDCANCLK_FREQUENCY / \ + ((FDCAN3_DTSEG1 + FDCAN3_DTSEG2 + 3) * \ + CONFIG_STM32_FDCAN3_DBITRATE)) - 1)) +# define FDCAN3_DSJW (CONFIG_STM32_FDCAN3_DSJW - 1) +# else +# define FDCAN3_DTSEG1 1 +# define FDCAN3_DTSEG2 1 +# define FDCAN3_DBRP 1 +# define FDCAN3_DSJW 1 +# endif /* CONFIG_STM32_FDCAN3_FD_BRS */ + +# if FDCAN3_DTSEG1 > FDCAN_DBTP_DTSEG1_MAX +# error Invalid FDCAN3 DTSEG1 +# endif +# if FDCAN3_DTSEG2 > FDCAN_DBTP_DTSEG2_MAX +# error Invalid FDCAN3 DTSEG2 +# endif +# if FDCAN3_DBRP > FDCAN_DBTP_DBRP_MAX +# error Invalid FDCAN3 DBRP +# endif +# if FDCAN3_DSJW > FDCAN_DBTP_DSJW_MAX +# error Invalid FDCAN3 DSJW +# endif + +/* FDCAN3 Message RAM Configuration *****************************************/ + +/* FDCAN3 Message RAM Layout */ + +# define FDCAN3_STDFILTER_INDEX 0 +# define FDCAN3_EXTFILTERS_INDEX (FDCAN3_STDFILTER_INDEX + FDCAN3_STDFILTER_WORDS) +# define FDCAN3_RXFIFO0_INDEX (FDCAN3_EXTFILTERS_INDEX + FDCAN3_EXTFILTER_WORDS) +# define FDCAN3_RXFIFO1_INDEX (FDCAN3_RXFIFO0_INDEX + FDCAN3_RXFIFO0_WORDS) +# define FDCAN3_TXEVENTFIFO_INDEX (FDCAN3_RXFIFO1_INDEX + FDCAN3_RXFIFO1_WORDS) +# define FDCAN3_TXFIFOQ_INDEX (FDCAN3_TXEVENTFIFO_INDEX + FDCAN3_TXEVENTFIFO_WORDS) +# define FDCAN3_MSGRAM_WORDS (FDCAN3_TXFIFOQ_INDEX + FDCAN3_TXFIFIOQ_WORDS) + +#endif /* CONFIG_STM32_FDCAN3 */ + +/* Loopback mode */ + +#undef STM32_FDCAN_LOOPBACK +#if defined(CONFIG_STM32_FDCAN1_LOOPBACK) || \ + defined(CONFIG_STM32_FDCAN2_LOOPBACK) || \ + defined(CONFIG_STM32_FDCAN3_LOOPBACK) +# define STM32_FDCAN_LOOPBACK 1 +#endif + +/* Interrupts ***************************************************************/ + +/* Common interrupts + * + * FDCAN_INT_TSW - Timestamp Wraparound + * FDCAN_INT_MRAF - Message RAM Access Failure + * FDCAN_INT_TOO - Timeout Occurred + * FDCAN_INT_ELO - Error Logging Overflow + * FDCAN_INT_EP - Error Passive + * FDCAN_INT_EW - Warning Status + * FDCAN_INT_BO - Bus_Off Status + * FDCAN_INT_WDI - Watchdog Interrupt + * FDCAN_INT_PEA - Protocol Error in Arbritration Phase + * FDCAN_INT_PED - Protocol Error in Data Phase + */ + +#define FDCAN_CMNERR_INTS (FDCAN_INT_MRAF | FDCAN_INT_TOO | FDCAN_INT_EP | \ + FDCAN_INT_BO | FDCAN_INT_WDI | FDCAN_INT_PEA | \ + FDCAN_INT_PED) +#define FDCAN_COMMON_INTS FDCAN_CMNERR_INTS + +/* RXFIFO mode interrupts + * + * FDCAN_INT_RF0N - Receive FIFO 0 New Message + * FDCAN_INT_RF0F - Receive FIFO 0 Full + * FDCAN_INT_RF0L - Receive FIFO 0 Message Lost + * FDCAN_INT_RF1N - Receive FIFO 1 New Message + * FDCAN_INT_RF1F - Receive FIFO 1 Full + * FDCAN_INT_RF1L - Receive FIFO 1 Message Lost + * FDCAN_INT_HPM - High Priority Message Received + * + */ + +#define FDCAN_RXCOMMON_INTS 0 +#define FDCAN_RXFIFO0_INTS (FDCAN_INT_RF0N | FDCAN_INT_RF0L) +#define FDCAN_RXFIFO1_INTS (FDCAN_INT_RF1N | FDCAN_INT_RF1L) +#define FDCAN_RXFIFO_INTS (FDCAN_RXFIFO0_INTS | FDCAN_RXFIFO1_INTS | \ + FDCAN_INT_HPM | FDCAN_RXCOMMON_INTS) + +#define FDCAN_RXERR_INTS (FDCAN_INT_RF0L | FDCAN_INT_RF1L) + +/* TX FIFOQ mode interrupts + * + * FDCAN_INT_TFE - Tx FIFO Empty + * + * TX Event FIFO interrupts + * + * FDCAN_INT_TEFN - Tx Event FIFO New Entry + * FDCAN_INT_TEFF - Tx Event FIFO Full + * FDCAN_INT_TEFL - Tx Event FIFO Element Lost + * + * Mode-independent TX-related interrupts + * + * FDCAN_INT_TC - Transmission Completed + * FDCAN_INT_TCF - Transmission Cancellation Finished + */ + +#define FDCAN_TXCOMMON_INTS (FDCAN_INT_TC | FDCAN_INT_TCF) +#define FDCAN_TXFIFOQ_INTS (FDCAN_INT_TFE | FDCAN_TXCOMMON_INTS) +#define FDCAN_TXEVFIFO_INTS (FDCAN_INT_TEFN | FDCAN_INT_TEFF | \ + FDCAN_INT_TEFL) +#define FDCAN_TXDEDBUF_INTS FDCAN_TXCOMMON_INTS + +#define FDCAN_TXERR_INTS (FDCAN_INT_TEFL | FDCAN_INT_PEA | FDCAN_INT_PED) + +/* Common-, TX- and RX-Error-Mask */ + +#define FDCAN_ANYERR_INTS (FDCAN_CMNERR_INTS | FDCAN_RXERR_INTS | FDCAN_TXERR_INTS) + +/* Convenience macro for clearing all interrupts */ + +#define FDCAN_INT_ALL 0x3fcfffff + +/* Debug ********************************************************************/ + +/* Debug configurations that may be enabled just for testing FDCAN */ + +#ifndef CONFIG_DEBUG_CAN_INFO +# undef CONFIG_STM32_FDCAN_REGDEBUG +#endif + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/* CAN frame format */ + +enum stm32_frameformat_e +{ + FDCAN_ISO11898_1_FORMAT = 0, /* Frame format according to ISO11898-1 */ + FDCAN_NONISO_BOSCH_V1_FORMAT = 1 /* Frame format according to Bosch CAN FD V1.0 */ +}; + +/* CAN mode of operation */ + +enum stm32_canmode_e +{ + FDCAN_CLASSIC_MODE = 0, /* Classic CAN operation */ +#ifdef CONFIG_CAN_FD + FDCAN_FD_MODE = 1, /* CAN FD operation */ + FDCAN_FD_BRS_MODE = 2 /* CAN FD operation with bit rate switching */ +#endif +}; + +/* CAN driver state */ + +enum can_state_s +{ + FDCAN_STATE_UNINIT = 0, /* Not yet initialized */ + FDCAN_STATE_RESET, /* Initialized, reset state */ + FDCAN_STATE_SETUP, /* fdcan_setup() has been called */ + FDCAN_STATE_DISABLED /* Disabled by a fdcan_shutdown() */ +}; + +/* This structure describes the FDCAN message RAM layout */ + +struct stm32_msgram_s +{ + volatile uint32_t *stdfilters; /* Standard filters */ + volatile uint32_t *extfilters; /* Extended filters */ + volatile uint32_t *rxfifo0; /* RX FIFO0 */ + volatile uint32_t *rxfifo1; /* RX FIFO1 */ + volatile uint32_t *txeventfifo; /* TX event FIFO */ + volatile uint32_t *txfifoq; /* TX FIFO queue */ +}; + +/* This structure provides the constant configuration of a FDCAN peripheral */ + +struct stm32_config_s +{ + uint32_t rxpinset; /* RX pin configuration */ + uint32_t txpinset; /* TX pin configuration */ + uintptr_t base; /* Base address of the FDCAN registers */ + uint32_t baud; /* Configured baud */ + uint32_t nbtp; /* Nominal bit timing/prescaler register setting */ + uint32_t dbtp; /* Data bit timing/prescaler register setting */ + uint8_t port; /* FDCAN port number (1 or 2) */ + uint8_t irq0; /* FDCAN peripheral IRQ number for interrupt line 0 */ + uint8_t irq1; /* FDCAN peripheral IRQ number for interrupt line 1 */ + uint8_t mode; /* See enum stm32_canmode_e */ + uint8_t format; /* See enum stm32_frameformat_e */ + uint8_t nstdfilters; /* Number of standard filters */ + uint8_t nextfilters; /* Number of extended filters */ + uint8_t nrxfifo0; /* Number of RX FIFO0 elements */ + uint8_t nrxfifo1; /* Number of RX FIFO1 elements */ + uint8_t ntxeventfifo; /* Number of TXevent FIFO elements */ + uint8_t ntxfifoq; /* Number of TX FIFO queue elements */ + uint8_t rxfifo0esize; /* RX FIFO0 element size (words) */ + uint8_t rxfifo1esize; /* RX FIFO1 element size (words) */ + uint8_t txeventesize; /* TXevent element size (words) */ + uint8_t txbufferesize; /* TX buffer element size (words) */ +#ifdef STM32_FDCAN_LOOPBACK + bool loopback; /* True: Loopback mode */ +#endif + + /* FDCAN message RAM layout */ + + struct stm32_msgram_s msgram; +}; + +/* This structure provides the current state of a FDCAN peripheral */ + +struct stm32_fdcan_s +{ + /* The constant configuration */ + + const struct stm32_config_s *config; + + uint8_t state; /* See enum can_state_s */ +#ifdef CONFIG_CAN_EXTID + uint8_t nextalloc; /* Number of allocated extended filters */ +#endif + uint8_t nstdalloc; /* Number of allocated standard filters */ + uint32_t nbtp; /* Current nominal bit timing */ + uint32_t dbtp; /* Current data bit timing */ + uint32_t rxints; /* Configured RX interrupts */ + uint32_t txints; /* Configured TX interrupts */ + +#ifdef CONFIG_CAN_EXTID + uint32_t extfilters[2]; /* Extended filter bit allocator. 2*32=64 */ +#endif + uint32_t stdfilters[4]; /* Standard filter bit allocator. 4*32=128 */ + +#ifdef CONFIG_STM32_FDCAN_REGDEBUG + uintptr_t regaddr; /* Last register address read */ + uint32_t regval; /* Last value read from the register */ + unsigned int count; /* Number of times that the value was read */ +#endif +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/* FDCAN Register access */ + +static uint32_t fdcan_getreg(struct stm32_fdcan_s *priv, int offset); +static void fdcan_putreg(struct stm32_fdcan_s *priv, int offset, + uint32_t regval); +#ifdef CONFIG_STM32_FDCAN_REGDEBUG +static void fdcan_dumpregs(struct stm32_fdcan_s *priv, + const char *msg); +static void fdcan_dumprxregs(struct stm32_fdcan_s *priv, + const char *msg); +static void fdcan_dumptxregs(struct stm32_fdcan_s *priv, + const char *msg); +static void fdcan_dumpramlayout(struct stm32_fdcan_s *priv); +#else +# define fdcan_dumpregs(priv,msg) +# define fdcan_dumprxregs(priv,msg) +# define fdcan_dumptxregs(priv,msg) +# define fdcan_dumpramlayout(priv) +#endif + +/* FDCAN helpers */ + +static uint8_t fdcan_dlc2bytes(struct stm32_fdcan_s *priv, uint8_t dlc); + +#ifdef CONFIG_CAN_EXTID +static int fdcan_add_extfilter(struct stm32_fdcan_s *priv, + struct canioc_extfilter_s *extconfig); +static int fdcan_del_extfilter(struct stm32_fdcan_s *priv, int ndx); +#endif +static int fdcan_add_stdfilter(struct stm32_fdcan_s *priv, + struct canioc_stdfilter_s *stdconfig); +static int fdcan_del_stdfilter(struct stm32_fdcan_s *priv, int ndx); + +static int +fdcan_start_busoff_recovery_sequence(struct stm32_fdcan_s *priv); + +/* CAN driver methods */ + +static void fdcan_reset(struct can_dev_s *dev); +static int fdcan_setup(struct can_dev_s *dev); +static void fdcan_shutdown(struct can_dev_s *dev); +static void fdcan_rxint(struct can_dev_s *dev, bool enable); +static void fdcan_txint(struct can_dev_s *dev, bool enable); +static int fdcan_ioctl(struct can_dev_s *dev, int cmd, + unsigned long arg); +static int fdcan_remoterequest(struct can_dev_s *dev, uint16_t id); +static int fdcan_send(struct can_dev_s *dev, struct can_msg_s *msg); +static bool fdcan_txready(struct can_dev_s *dev); +static bool fdcan_txempty(struct can_dev_s *dev); + +/* FDCAN interrupt handling */ + +#ifdef CONFIG_CAN_ERRORS +static void fdcan_error(struct can_dev_s *dev, uint32_t status); +#endif +static void fdcan_receive(struct can_dev_s *dev, + volatile uint32_t *rxbuffer, + unsigned long nwords); +static int fdcan_interrupt(int irq, void *context, void *arg); + +/* Hardware initialization */ + +static int fdcan_hw_initialize(struct stm32_fdcan_s *priv); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static const struct can_ops_s g_fdcanops = +{ + .co_reset = fdcan_reset, + .co_setup = fdcan_setup, + .co_shutdown = fdcan_shutdown, + .co_rxint = fdcan_rxint, + .co_txint = fdcan_txint, + .co_ioctl = fdcan_ioctl, + .co_remoterequest = fdcan_remoterequest, + .co_send = fdcan_send, + .co_txready = fdcan_txready, + .co_txempty = fdcan_txempty, +}; + +#ifdef CONFIG_STM32_FDCAN1 +/* Message RAM allocation */ + +/* Constant configuration */ + +static const struct stm32_config_s g_fdcan1const = +{ + .rxpinset = GPIO_FDCAN1_RX, + .txpinset = GPIO_FDCAN1_TX, + .base = STM32_FDCAN1_BASE, + .baud = CONFIG_STM32_FDCAN1_BITRATE, + .nbtp = FDCAN_NBTP_NBRP(FDCAN1_NBRP) | + FDCAN_NBTP_NTSEG1(FDCAN1_NTSEG1) | + FDCAN_NBTP_NTSEG2(FDCAN1_NTSEG2) | + FDCAN_NBTP_NSJW(FDCAN1_NSJW), + .dbtp = FDCAN_DBTP_DBRP(FDCAN1_DBRP) | + FDCAN_DBTP_DTSEG1(FDCAN1_DTSEG1) | + FDCAN_DBTP_DTSEG2(FDCAN1_DTSEG2) | + FDCAN_DBTP_DSJW(FDCAN1_DSJW), + .port = 1, + .irq0 = STM32_IRQ_FDCAN1_0, + .irq1 = STM32_IRQ_FDCAN1_1, +#if defined(CONFIG_STM32_FDCAN1_CLASSIC) + .mode = FDCAN_CLASSIC_MODE, +#elif defined(CONFIG_STM32_FDCAN1_FD) + .mode = FDCAN_FD_MODE, +#else + .mode = FDCAN_FD_BRS_MODE, +#endif +#if defined(CONFIG_STM32_FDCAN1_NONISO_FORMAT) + .format = FDCAN_NONISO_BOSCH_V1_FORMAT, +#else + .format = FDCAN_ISO11898_1_FORMAT, +#endif + .nstdfilters = FDCAN1_STDFILTER_SIZE, + .nextfilters = FDCAN1_EXTFILTER_SIZE, + .nrxfifo0 = FDCAN1_RXFIFO0_SIZE, + .nrxfifo1 = FDCAN1_RXFIFO1_SIZE, + .ntxeventfifo = FDCAN1_TXEVENTFIFO_SIZE, + .ntxfifoq = FDCAN1_TXFIFIOQ_SIZE, + .rxfifo0esize = (FDCAN1_RXFIFO0_WORDS / FDCAN1_RXFIFO0_SIZE), + .rxfifo1esize = (FDCAN1_RXFIFO1_WORDS / FDCAN1_RXFIFO1_SIZE), + .txeventesize = (FDCAN1_TXEVENTFIFO_WORDS / FDCAN1_TXEVENTFIFO_SIZE), + .txbufferesize = (FDCAN1_TXFIFIOQ_WORDS / FDCAN1_TXFIFIOQ_SIZE), + +#ifdef CONFIG_STM32_FDCAN1_LOOPBACK + .loopback = true, +#endif + + /* FDCAN1 Message RAM */ + + .msgram = + { + (uint32_t *)(STM32_CANRAM1_BASE + (FDCAN1_STDFILTER_INDEX << 2)), + (uint32_t *)(STM32_CANRAM1_BASE + (FDCAN1_EXTFILTERS_INDEX << 2)), + (uint32_t *)(STM32_CANRAM1_BASE + (FDCAN1_RXFIFO0_INDEX << 2)), + (uint32_t *)(STM32_CANRAM1_BASE + (FDCAN1_RXFIFO1_INDEX << 2)), + (uint32_t *)(STM32_CANRAM1_BASE + (FDCAN1_TXEVENTFIFO_INDEX << 2)), + (uint32_t *)(STM32_CANRAM1_BASE + (FDCAN1_TXFIFOQ_INDEX << 2)) + } +}; + +/* FDCAN1 variable driver state */ + +static struct stm32_fdcan_s g_fdcan1priv; +static struct can_dev_s g_fdcan1dev; + +#endif /* CONFIG_STM32_FDCAN1 */ + +#ifdef CONFIG_STM32_FDCAN2 +/* FDCAN2 message RAM allocation */ + +/* FDCAN2 constant configuration */ + +static const struct stm32_config_s g_fdcan2const = +{ + .rxpinset = GPIO_FDCAN2_RX, + .txpinset = GPIO_FDCAN2_TX, + .base = STM32_FDCAN2_BASE, + .baud = CONFIG_STM32_FDCAN2_BITRATE, + .nbtp = FDCAN_NBTP_NBRP(FDCAN2_NBRP) | + FDCAN_NBTP_NTSEG1(FDCAN2_NTSEG1) | + FDCAN_NBTP_NTSEG2(FDCAN2_NTSEG2) | + FDCAN_NBTP_NSJW(FDCAN2_NSJW), + .dbtp = FDCAN_DBTP_DBRP(FDCAN2_DBRP) | + FDCAN_DBTP_DTSEG1(FDCAN2_DTSEG1) | + FDCAN_DBTP_DTSEG2(FDCAN2_DTSEG2) | + FDCAN_DBTP_DSJW(FDCAN2_DSJW), + .port = 2, + .irq0 = STM32_IRQ_FDCAN2_0, + .irq1 = STM32_IRQ_FDCAN2_1, +#if defined(CONFIG_STM32_FDCAN2_CLASSIC) + .mode = FDCAN_CLASSIC_MODE, +#elif defined(CONFIG_STM32_FDCAN2_FD) + .mode = FDCAN_FD_MODE, +#else + .mode = FDCAN_FD_BRS_MODE, +#endif +#if defined(CONFIG_STM32_FDCAN2_NONISO_FORMAT) + .format = FDCAN_NONISO_BOSCH_V1_FORMAT, +#else + .format = FDCAN_ISO11898_1_FORMAT, +#endif + .nstdfilters = FDCAN2_STDFILTER_SIZE, + .nextfilters = FDCAN2_EXTFILTER_SIZE, + .nrxfifo0 = FDCAN2_RXFIFO0_SIZE, + .nrxfifo1 = FDCAN2_RXFIFO1_SIZE, + .ntxeventfifo = FDCAN2_TXEVENTFIFO_SIZE, + .ntxfifoq = FDCAN2_TXFIFIOQ_SIZE, + .rxfifo0esize = (FDCAN2_RXFIFO0_WORDS / FDCAN2_RXFIFO0_SIZE), + .rxfifo1esize = (FDCAN2_RXFIFO1_WORDS / FDCAN2_RXFIFO1_SIZE), + .txeventesize = (FDCAN2_TXEVENTFIFO_WORDS / FDCAN2_TXEVENTFIFO_SIZE), + .txbufferesize = (FDCAN2_TXFIFIOQ_WORDS / FDCAN2_TXFIFIOQ_SIZE), + +#ifdef CONFIG_STM32_FDCAN2_LOOPBACK + .loopback = true, +#endif + + /* FDCAN2 Message RAM */ + + .msgram = + { + (uint32_t *)(STM32_CANRAM2_BASE + (FDCAN2_STDFILTER_INDEX << 2)), + (uint32_t *)(STM32_CANRAM2_BASE + (FDCAN2_EXTFILTERS_INDEX << 2)), + (uint32_t *)(STM32_CANRAM2_BASE + (FDCAN2_RXFIFO0_INDEX << 2)), + (uint32_t *)(STM32_CANRAM2_BASE + (FDCAN2_RXFIFO1_INDEX << 2)), + (uint32_t *)(STM32_CANRAM2_BASE + (FDCAN2_TXEVENTFIFO_INDEX << 2)), + (uint32_t *)(STM32_CANRAM2_BASE + (FDCAN2_TXFIFOQ_INDEX << 2)) + } +}; + +/* FDCAN2 variable driver state */ + +static struct stm32_fdcan_s g_fdcan2priv; +static struct can_dev_s g_fdcan2dev; + +#endif /* CONFIG_STM32_FDCAN2 */ + +#ifdef CONFIG_STM32_FDCAN3 +/* FDCAN3 message RAM allocation */ + +/* FDCAN3 constant configuration */ + +static const struct stm32_config_s g_fdcan3const = +{ + .rxpinset = GPIO_FDCAN3_RX, + .txpinset = GPIO_FDCAN3_TX, + .base = STM32_FDCAN3_BASE, + .baud = CONFIG_STM32_FDCAN3_BITRATE, + .nbtp = FDCAN_NBTP_NBRP(FDCAN3_NBRP) | + FDCAN_NBTP_NTSEG1(FDCAN3_NTSEG1) | + FDCAN_NBTP_NTSEG2(FDCAN3_NTSEG2) | + FDCAN_NBTP_NSJW(FDCAN3_NSJW), + .dbtp = FDCAN_DBTP_DBRP(FDCAN3_DBRP) | + FDCAN_DBTP_DTSEG1(FDCAN3_DTSEG1) | + FDCAN_DBTP_DTSEG2(FDCAN3_DTSEG2) | + FDCAN_DBTP_DSJW(FDCAN3_DSJW), + .port = 3, + .irq0 = STM32_IRQ_FDCAN3_0, + .irq1 = STM32_IRQ_FDCAN3_1, +#if defined(CONFIG_STM32_FDCAN3_CLASSIC) + .mode = FDCAN_CLASSIC_MODE, +#elif defined(CONFIG_STM32_FDCAN3_FD) + .mode = FDCAN_FD_MODE, +#else + .mode = FDCAN_FD_BRS_MODE, +#endif +#if defined(CONFIG_STM32_FDCAN3_NONISO_FORMAT) + .format = FDCAN_NONISO_BOSCH_V1_FORMAT, +#else + .format = FDCAN_ISO11898_1_FORMAT, +#endif + .nstdfilters = FDCAN3_STDFILTER_SIZE, + .nextfilters = FDCAN3_EXTFILTER_SIZE, + .nrxfifo0 = FDCAN3_RXFIFO0_SIZE, + .nrxfifo1 = FDCAN3_RXFIFO1_SIZE, + .ntxeventfifo = FDCAN3_TXEVENTFIFO_SIZE, + .ntxfifoq = FDCAN3_TXFIFIOQ_SIZE, + .rxfifo0esize = (FDCAN3_RXFIFO0_WORDS / FDCAN3_RXFIFO0_SIZE), + .rxfifo1esize = (FDCAN3_RXFIFO1_WORDS / FDCAN3_RXFIFO1_SIZE), + .txeventesize = (FDCAN3_TXEVENTFIFO_WORDS / FDCAN3_TXEVENTFIFO_SIZE), + .txbufferesize = (FDCAN3_TXFIFIOQ_WORDS / FDCAN3_TXFIFIOQ_SIZE), + +#ifdef CONFIG_STM32_FDCAN3_LOOPBACK + .loopback = true, +#endif + + /* FDCAN3 Message RAM */ + + .msgram = + { + (uint32_t *)(STM32_CANRAM3_BASE + (FDCAN3_STDFILTER_INDEX << 2)), + (uint32_t *)(STM32_CANRAM3_BASE + (FDCAN3_EXTFILTERS_INDEX << 2)), + (uint32_t *)(STM32_CANRAM3_BASE + (FDCAN3_RXFIFO0_INDEX << 2)), + (uint32_t *)(STM32_CANRAM3_BASE + (FDCAN3_RXFIFO1_INDEX << 2)), + (uint32_t *)(STM32_CANRAM3_BASE + (FDCAN3_TXEVENTFIFO_INDEX << 2)), + (uint32_t *)(STM32_CANRAM3_BASE + (FDCAN3_TXFIFOQ_INDEX << 2)) + } +}; + +/* FDCAN3 variable driver state */ + +static struct stm32_fdcan_s g_fdcan3priv; +static struct can_dev_s g_fdcan3dev; + +#endif /* CONFIG_STM32_FDCAN3 */ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: fdcan_getreg + * + * Description: + * Read the value of a FDCAN register. + * + * Input Parameters: + * priv - A reference to the FDCAN peripheral state + * offset - The offset to the register to read + * + * Returned Value: + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_FDCAN_REGDEBUG +static uint32_t fdcan_getreg(struct stm32_fdcan_s *priv, int offset) +{ + const struct stm32_config_s *config = priv->config; + uintptr_t regaddr = 0; + uint32_t regval = 0; + + /* Read the value from the register */ + + regaddr = config->base + offset; + regval = getreg32(regaddr); + + /* Is this the same value that we read from the same register last time? + * Are we polling the register? If so, suppress some of the output. + */ + + if (regaddr == priv->regaddr && regval == priv->regval) + { + if (priv->count == 0xffffffff || ++priv->count > 3) + { + if (priv->count == 4) + { + caninfo("...\n"); + } + + return regval; + } + } + + /* No this is a new address or value */ + + else + { + /* Did we print "..." for the previous value? */ + + if (priv->count > 3) + { + /* Yes.. then show how many times the value repeated */ + + caninfo("[repeats %d more times]\n", priv->count - 3); + } + + /* Save the new address, value, and count */ + + priv->regaddr = regaddr; + priv->regval = regval; + priv->count = 1; + } + + /* Show the register value read */ + + caninfo("%08" PRIx32 "->%08" PRIx32 "\n", regaddr, regval); + return regval; +} + +#else +static uint32_t fdcan_getreg(struct stm32_fdcan_s *priv, int offset) +{ + const struct stm32_config_s *config = priv->config; + return getreg32(config->base + offset); +} + +#endif + +/**************************************************************************** + * Name: fdcan_putreg + * + * Description: + * Set the value of a FDCAN register. + * + * Input Parameters: + * priv - A reference to the FDCAN peripheral state + * offset - The offset to the register to write + * regval - The value to write to the register + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_FDCAN_REGDEBUG +static void fdcan_putreg(struct stm32_fdcan_s *priv, int offset, + uint32_t regval) +{ + const struct stm32_config_s *config = priv->config; + uintptr_t regaddr = config->base + offset; + + /* Show the register value being written */ + + caninfo("%08" PRIx32 "->%08" PRIx32 "\n", regaddr, regval); + + /* Write the value */ + + putreg32(regval, regaddr); +} + +#else +static void fdcan_putreg(struct stm32_fdcan_s *priv, int offset, + uint32_t regval) +{ + const struct stm32_config_s *config = priv->config; + putreg32(regval, config->base + offset); +} + +#endif + +/**************************************************************************** + * Name: fdcan_dumpctrlregs + * + * Description: + * Dump the contents of all CAN control registers + * + * Input Parameters: + * priv - A reference to the CAN block status + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_FDCAN_REGDEBUG +static void fdcan_dumpregs(struct stm32_fdcan_s *priv, + const char *msg) +{ + const struct stm32_config_s *config = priv->config; + + caninfo("CAN%d Control and Status Registers: %s\n", config->port, msg); + caninfo(" Base: %08" PRIx32 "\n", config->base); + + /* CAN control and status registers */ + + caninfo(" CCCR: %08" PRIx32 " TEST: %08" PRIx32 "\n", + getreg32(config->base + STM32_FDCAN_CCCR_OFFSET), + getreg32(config->base + STM32_FDCAN_TEST_OFFSET)); + + caninfo(" NBTP: %08" PRIx32 " DBTP: %08" PRIx32 "\n", + getreg32(config->base + STM32_FDCAN_NBTP_OFFSET), + getreg32(config->base + STM32_FDCAN_DBTP_OFFSET)); + + caninfo(" IE: %08" PRIx32 " TIE: %08" PRIx32 "\n", + getreg32(config->base + STM32_FDCAN_IE_OFFSET), + getreg32(config->base + STM32_FDCAN_TXBTIE_OFFSET)); + + caninfo(" ILE: %08" PRIx32 " ILS: %08" PRIx32 "\n", + getreg32(config->base + STM32_FDCAN_ILE_OFFSET), + getreg32(config->base + STM32_FDCAN_ILS_OFFSET)); + + caninfo(" TXBC: %08" PRIx32 "\n", + getreg32(config->base + STM32_FDCAN_TXBC_OFFSET)); +} +#endif + +/**************************************************************************** + * Name: stm32can_dumprxregs + * + * Description: + * Dump the contents of all Rx status registers + * + * Input Parameters: + * priv - A reference to the CAN block status + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_FDCAN_REGDEBUG +static void fdcan_dumprxregs(struct stm32_fdcan_s *priv, + const char *msg) +{ + const struct stm32_config_s *config = priv->config; + + caninfo("CAN%d Rx Registers: %s\n", config->port, msg); + caninfo(" Base: %08" PRIx32 "\n", config->base); + + caninfo(" PSR: %08" PRIx32 " ECR: %08" PRIx32 + " HPMS: %08" PRIx32 "\n", + getreg32(config->base + STM32_FDCAN_PSR_OFFSET), + getreg32(config->base + STM32_FDCAN_ECR_OFFSET), + getreg32(config->base + STM32_FDCAN_HPMS_OFFSET)); + + caninfo(" RXF0S: %08" PRIx32 " RXF0A: %08" PRIx32 "\n", + getreg32(config->base + STM32_FDCAN_RXF0S_OFFSET), + getreg32(config->base + STM32_FDCAN_RXF0A_OFFSET)); + + caninfo(" RXF1S: %08" PRIx32 " RXF1A: %08" PRIx32 "\n", + getreg32(config->base + STM32_FDCAN_RXF1S_OFFSET), + getreg32(config->base + STM32_FDCAN_RXF1A_OFFSET)); + + caninfo(" IR: %08" PRIx32 " IE: %08" PRIx32 "\n", + getreg32(config->base + STM32_FDCAN_IR_OFFSET), + getreg32(config->base + STM32_FDCAN_IE_OFFSET)); +} +#endif + +/**************************************************************************** + * Name: stm32can_dumptxregs + * + * Description: + * Dump the contents of all Tx buffer registers + * + * Input Parameters: + * priv - A reference to the CAN block status + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_FDCAN_REGDEBUG +static void fdcan_dumptxregs(struct stm32_fdcan_s *priv, + const char *msg) +{ + const struct stm32_config_s *config = priv->config; + + caninfo("CAN%d Tx Registers: %s\n", config->port, msg); + caninfo(" Base: %08" PRIx32 "\n", config->base); + + caninfo(" PSR: %08" PRIx32 " ECR: %08" PRIx32 "\n", + getreg32(config->base + STM32_FDCAN_PSR_OFFSET), + getreg32(config->base + STM32_FDCAN_ECR_OFFSET)); + + caninfo(" TXQFS: %08" PRIx32 " TXBAR: %08" PRIx32 + " TXBRP: %08" PRIx32 "\n", + getreg32(config->base + STM32_FDCAN_TXFQS_OFFSET), + getreg32(config->base + STM32_FDCAN_TXBAR_OFFSET), + getreg32(config->base + STM32_FDCAN_TXBRP_OFFSET)); + + caninfo(" TXBTO: %08" PRIx32 " TXBCR: %08" PRIx32 "\n", + getreg32(config->base + STM32_FDCAN_TXBTO_OFFSET), + getreg32(config->base + STM32_FDCAN_TXBCR_OFFSET)); + + caninfo(" TXEFS: %08" PRIx32 " TXEFA: %08" PRIx32 "\n", + getreg32(config->base + STM32_FDCAN_TXEFS_OFFSET), + getreg32(config->base + STM32_FDCAN_TXEFA_OFFSET)); + + caninfo(" IR: %08" PRIx32 " IE: %08" PRIx32 + " TIE: %08" PRIx32 "\n", + getreg32(config->base + STM32_FDCAN_IR_OFFSET), + getreg32(config->base + STM32_FDCAN_IE_OFFSET), + getreg32(config->base + STM32_FDCAN_TXBTIE_OFFSET)); +} +#endif + +/**************************************************************************** + * Name: stm32can_dumpramlayout + * + * Description: + * Print the layout of the message RAM + * + * Input Parameters: + * priv - A reference to the CAN block status + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_FDCAN_REGDEBUG +static void fdcan_dumpramlayout(struct stm32_fdcan_s *priv) +{ + const struct stm32_config_s *config = priv->config; + + caninfo(" ******* FDCAN%d Message RAM layout *******\n", config->port); + caninfo(" Start # Elmnt Elmnt size (words)\n"); + + if (config->nstdfilters > 0) + { + caninfo("STD filters %p %4d %2d\n", + config->msgram.stdfilters, + config->nstdfilters, + 1); + } + + if (config->nextfilters > 0) + { + caninfo("EXT filters %p %4d %2d\n", + config->msgram.extfilters, + config->nextfilters, + 2); + } + + if (config->nrxfifo0 > 0) + { + caninfo("RX FIFO 0 %p %4d %2d\n", + config->msgram.rxfifo0, + config->nrxfifo0, + config->rxfifo0esize); + } + + if (config->nrxfifo1 > 0) + { + caninfo("RX FIFO 1 %p %4d %2d\n", + config->msgram.rxfifo1, + config->nrxfifo1, + config->rxfifo1esize); + } + + if (config->ntxeventfifo > 0) + { + caninfo("TX EVENT %p %4d %2d\n", + config->msgram.txeventfifo, + config->ntxeventfifo, + config->txeventesize); + } + + if (config->ntxfifoq > 0) + { + caninfo("TX FIFO %p %4d %2d\n", + config->msgram.txfifoq, + config->ntxfifoq, + config->txbufferesize); + } +} +#endif + +/**************************************************************************** + * Name: fdcan_dlc2bytes + * + * Description: + * In the CAN FD format, the coding of the DLC differs from the standard + * CAN format. The DLC codes 0 to 8 have the same coding as in standard + * CAN. But the codes 9 to 15 all imply a data field of 8 bytes with + * standard CAN. In CAN FD mode, the values 9 to 15 are encoded to values + * in the range 12 to 64. + * + * Input Parameters: + * dlc - the DLC value to convert to a byte count + * + * Returned Value: + * The number of bytes corresponding to the DLC value. + * + ****************************************************************************/ + +static uint8_t fdcan_dlc2bytes(struct stm32_fdcan_s *priv, uint8_t dlc) +{ + if (dlc > 8) + { +#ifdef CONFIG_CAN_FD + if (priv->config->mode == FDCAN_CLASSIC_MODE) + { + return 8; + } + else + { + switch (dlc) + { + case 9: + return 12; + case 10: + return 16; + case 11: + return 20; + case 12: + return 24; + case 13: + return 32; + case 14: + return 48; + default: + case 15: + return 64; + } + } +#else + return 8; +#endif + } + + return dlc; +} + +/**************************************************************************** + * Name: fdcan_add_extfilter + * + * Description: + * Add an address filter for a extended 29 bit address. + * + * Input Parameters: + * priv - An instance of the FDCAN driver state structure. + * extconfig - The configuration of the extended filter + * + * Returned Value: + * A non-negative filter ID is returned on success. Otherwise a negated + * errno value is returned to indicate the nature of the error. + * + ****************************************************************************/ + +#ifdef CONFIG_CAN_EXTID +static int fdcan_add_extfilter(struct stm32_fdcan_s *priv, + struct canioc_extfilter_s *extconfig) +{ + const struct stm32_config_s *config = NULL; + volatile uint32_t *extfilter = NULL; + uint32_t regval = 0; + int word = 0; + int bit = 0; + int ndx = 0; + + DEBUGASSERT(priv != NULL && priv->config != NULL && extconfig != NULL); + config = priv->config; + + /* Find an unused standard filter */ + + for (ndx = 0; ndx < config->nextfilters; ndx++) + { + /* Is this filter assigned? */ + + word = ndx >> 5; + bit = ndx & 0x1f; + + if ((priv->extfilters[word] & (1 << bit)) == 0) + { + /* No, assign the filter */ + + DEBUGASSERT(priv->nextalloc < priv->config->nstdfilters); + priv->extfilters[word] |= (1 << bit); + priv->nextalloc++; + + extfilter = config->msgram.extfilters + (ndx << 1); + + /* Format and write filter word F0 */ + + DEBUGASSERT(extconfig->xf_id1 <= CAN_MAX_EXTMSGID); + regval = EXTFILTER_F0_EFID1(extconfig->xf_id1); + + if (extconfig->xf_prio == 0) + { + regval |= EXTFILTER_F0_EFEC_FIFO0; + } + else + { + regval |= EXTFILTER_F0_EFEC_FIFO1; + } + + extfilter[0] = regval; + + /* Format and write filter word F1 */ + + DEBUGASSERT(extconfig->xf_id2 <= CAN_MAX_EXTMSGID); + regval = EXTFILTER_F1_EFID2(extconfig->xf_id2); + + switch (extconfig->xf_type) + { + case CAN_FILTER_DUAL: + { + regval |= EXTFILTER_F1_EFT_DUAL; + break; + } + + case CAN_FILTER_MASK: + { + regval |= EXTFILTER_F1_EFT_CLASSIC; + break; + } + + case CAN_FILTER_RANGE: + { + regval |= EXTFILTER_F1_EFT_RANGE; + break; + } + + default: + { + return -EINVAL; + } + } + + extfilter[1] = regval; + + /* Is this the first extended filter? */ + + if (priv->nextalloc == 1) + { + /* Enable the Initialization state */ + + regval = fdcan_getreg(priv, STM32_FDCAN_CCCR_OFFSET); + regval |= FDCAN_CCCR_INIT; + fdcan_putreg(priv, STM32_FDCAN_CCCR_OFFSET, regval); + + /* Wait for initialization mode to take effect */ + + while ((fdcan_getreg(priv, STM32_FDCAN_CCCR_OFFSET) & + FDCAN_CCCR_INIT) == 0); + + /* Enable writing to configuration registers */ + + regval = fdcan_getreg(priv, STM32_FDCAN_CCCR_OFFSET); + regval |= (FDCAN_CCCR_INIT | FDCAN_CCCR_CCE); + fdcan_putreg(priv, STM32_FDCAN_CCCR_OFFSET, regval); + + /* Update the Global Filter Configuration so that received + * messages are rejected if they do not match the acceptance + * filter. + * + * ANFE=2: Discard all rejected frames + */ + + regval = fdcan_getreg(priv, STM32_FDCAN_RXGFC_OFFSET); + regval &= ~FDCAN_RXGFC_ANFE_MASK; + regval |= FDCAN_RXGFC_ANFE_REJECTED; + fdcan_putreg(priv, STM32_FDCAN_RXGFC_OFFSET, regval); + + /* Disable writing to configuration registers */ + + regval = fdcan_getreg(priv, STM32_FDCAN_CCCR_OFFSET); + regval &= ~(FDCAN_CCCR_INIT | FDCAN_CCCR_CCE); + fdcan_putreg(priv, STM32_FDCAN_CCCR_OFFSET, regval); + } + + return ndx; + } + } + + DEBUGASSERT(priv->nextalloc == priv->config->nextfilters); + + return -EAGAIN; +} +#endif + +/**************************************************************************** + * Name: fdcan_del_extfilter + * + * Description: + * Remove an address filter for a standard 29 bit address. + * + * Input Parameters: + * priv - An instance of the FDCAN driver state structure. + * ndx - The filter index previously returned by the + * fdcan_add_extfilter(). + * + * Returned Value: + * Zero (OK) is returned on success. Otherwise a negated errno value is + * returned to indicate the nature of the error. + * + ****************************************************************************/ + +#ifdef CONFIG_CAN_EXTID +static int fdcan_del_extfilter(struct stm32_fdcan_s *priv, int ndx) +{ + const struct stm32_config_s *config = NULL; + volatile uint32_t *extfilter = NULL; + uint32_t regval = 0; + int word = 0; + int bit = 0; + + DEBUGASSERT(priv != NULL && priv->config != NULL); + config = priv->config; + + /* Check user Parameters */ + + DEBUGASSERT(ndx >= 0 || ndx < config->nextfilters); + + if (ndx < 0 || ndx >= config->nextfilters) + { + return -EINVAL; + } + + word = ndx >> 5; + bit = ndx & 0x1f; + + /* Check if this filter is really assigned */ + + if ((priv->extfilters[word] & (1 << bit)) == 0) + { + /* No, error out */ + + return -ENOENT; + } + + /* Release the filter */ + + priv->extfilters[word] &= ~(1 << bit); + + DEBUGASSERT(priv->nextalloc > 0); + priv->nextalloc--; + + /* Was that the last extended filter? */ + + if (priv->nextalloc == 0) + { + /* Enable the Initialization state */ + + regval = fdcan_getreg(priv, STM32_FDCAN_CCCR_OFFSET); + regval |= FDCAN_CCCR_INIT; + fdcan_putreg(priv, STM32_FDCAN_CCCR_OFFSET, regval); + + /* Wait for initialization mode to take effect */ + + while ((fdcan_getreg(priv, STM32_FDCAN_CCCR_OFFSET) & + FDCAN_CCCR_INIT) == 0); + + /* Enable writing to configuration registers */ + + regval = fdcan_getreg(priv, STM32_FDCAN_CCCR_OFFSET); + regval |= (FDCAN_CCCR_INIT | FDCAN_CCCR_CCE); + fdcan_putreg(priv, STM32_FDCAN_CCCR_OFFSET, regval); + + /* If there are no extended filters, then modify Global Filter + * Configuration so that all rejected messages are places in RX + * FIFO0. + * + * ANFE=0: Store all rejected extended frame in RX FIFO0 + */ + + regval = fdcan_getreg(priv, STM32_FDCAN_RXGFC_OFFSET); + regval &= ~FDCAN_RXGFC_ANFE_MASK; + regval |= FDCAN_RXGFC_ANFE_RX_FIFO0; + fdcan_putreg(priv, STM32_FDCAN_RXGFC_OFFSET, regval); + + /* Disable writing to configuration registers */ + + regval = fdcan_getreg(priv, STM32_FDCAN_CCCR_OFFSET); + regval &= ~(FDCAN_CCCR_INIT | FDCAN_CCCR_CCE); + fdcan_putreg(priv, STM32_FDCAN_CCCR_OFFSET, regval); + } + + /* Deactivate the filter last so that no messages are lost. */ + + extfilter = config->msgram.extfilters + (ndx << 1); + *extfilter++ = 0; + *extfilter = 0; + + return OK; +} +#endif + +/**************************************************************************** + * Name: fdcan_add_stdfilter + * + * Description: + * Add an address filter for a standard 11 bit address. + * + * Input Parameters: + * priv - An instance of the FDCAN driver state structure. + * stdconfig - The configuration of the standard filter + * + * Returned Value: + * A non-negative filter ID is returned on success. Otherwise a negated + * errno value is returned to indicate the nature of the error. + * + ****************************************************************************/ + +static int fdcan_add_stdfilter(struct stm32_fdcan_s *priv, + struct canioc_stdfilter_s *stdconfig) +{ + const struct stm32_config_s *config = NULL; + volatile uint32_t *stdfilter = NULL; + uint32_t regval = 0; + int word = 0; + int bit = 0; + int ndx = 0; + + DEBUGASSERT(priv != NULL && priv->config != NULL); + config = priv->config; + + /* Find an unused standard filter */ + + for (ndx = 0; ndx < config->nstdfilters; ndx++) + { + /* Is this filter assigned? */ + + word = ndx >> 5; + bit = ndx & 0x1f; + + if ((priv->stdfilters[word] & (1 << bit)) == 0) + { + /* No, assign the filter */ + + DEBUGASSERT(priv->nstdalloc < priv->config->nstdfilters); + priv->stdfilters[word] |= (1 << bit); + priv->nstdalloc++; + + /* Format and write filter word S0 */ + + stdfilter = config->msgram.stdfilters + ndx; + + DEBUGASSERT(stdconfig->sf_id1 <= CAN_MAX_STDMSGID); + regval = STDFILTER_S0_SFID1(stdconfig->sf_id1); + + DEBUGASSERT(stdconfig->sf_id2 <= CAN_MAX_STDMSGID); + regval |= STDFILTER_S0_SFID2(stdconfig->sf_id2); + + if (stdconfig->sf_prio == 0) + { + regval |= STDFILTER_S0_SFEC_FIFO0; + } + else + { + regval |= STDFILTER_S0_SFEC_FIFO1; + } + + switch (stdconfig->sf_type) + { + case CAN_FILTER_DUAL: + { + regval |= STDFILTER_S0_SFT_DUAL; + break; + } + + case CAN_FILTER_MASK: + { + regval |= STDFILTER_S0_SFT_CLASSIC; + break; + } + + case CAN_FILTER_RANGE: + { + regval |= STDFILTER_S0_SFT_RANGE; + break; + } + + default: + { + return -EINVAL; + } + } + + *stdfilter = regval; + + /* Is this the first standard filter? */ + + if (priv->nstdalloc == 1) + { + /* Enable the Initialization state */ + + regval = fdcan_getreg(priv, STM32_FDCAN_CCCR_OFFSET); + regval |= FDCAN_CCCR_INIT; + fdcan_putreg(priv, STM32_FDCAN_CCCR_OFFSET, regval); + + /* Wait for initialization mode to take effect */ + + while ((fdcan_getreg(priv, STM32_FDCAN_CCCR_OFFSET) & + FDCAN_CCCR_INIT) == 0); + + /* Enable writing to configuration registers */ + + regval = fdcan_getreg(priv, STM32_FDCAN_CCCR_OFFSET); + regval |= (FDCAN_CCCR_INIT | FDCAN_CCCR_CCE); + fdcan_putreg(priv, STM32_FDCAN_CCCR_OFFSET, regval); + + /* Update the Global Filter Configuration so that received + * messages are rejected if they do not match the acceptance + * filter. + * + * ANFS=2: Discard all rejected frames + */ + + regval = fdcan_getreg(priv, STM32_FDCAN_RXGFC_OFFSET); + regval &= ~FDCAN_RXGFC_ANFS_MASK; + regval |= FDCAN_RXGFC_ANFS_REJECTED; + fdcan_putreg(priv, STM32_FDCAN_RXGFC_OFFSET, regval); + + /* Disable writing to configuration registers */ + + regval = fdcan_getreg(priv, STM32_FDCAN_CCCR_OFFSET); + regval &= ~(FDCAN_CCCR_INIT | FDCAN_CCCR_CCE); + fdcan_putreg(priv, STM32_FDCAN_CCCR_OFFSET, regval); + } + + return ndx; + } + } + + DEBUGASSERT(priv->nstdalloc == priv->config->nstdfilters); + return -EAGAIN; +} + +/**************************************************************************** + * Name: fdcan_del_stdfilter + * + * Description: + * Remove an address filter for a standard 29 bit address. + * + * Input Parameters: + * priv - An instance of the FDCAN driver state structure. + * ndx - The filter index previously returned by the + * fdcan_add_stdfilter(). + * + * Returned Value: + * Zero (OK) is returned on success. Otherwise a negated errno value is + * returned to indicate the nature of the error. + * + ****************************************************************************/ + +static int fdcan_del_stdfilter(struct stm32_fdcan_s *priv, int ndx) +{ + const struct stm32_config_s *config = NULL; + volatile uint32_t *stdfilter = NULL; + uint32_t regval = 0; + int word = 0; + int bit = 0; + + DEBUGASSERT(priv != NULL && priv->config != NULL); + config = priv->config; + + /* Check Userspace Parameters */ + + DEBUGASSERT(ndx >= 0 || ndx < config->nstdfilters); + + if (ndx < 0 || ndx >= config->nstdfilters) + { + return -EINVAL; + } + + word = ndx >> 5; + bit = ndx & 0x1f; + + /* Check if this filter is really assigned */ + + if ((priv->stdfilters[word] & (1 << bit)) == 0) + { + /* No, error out */ + + return -ENOENT; + } + + /* Release the filter */ + + priv->stdfilters[word] &= ~(1 << bit); + + DEBUGASSERT(priv->nstdalloc > 0); + priv->nstdalloc--; + + /* Was that the last standard filter? */ + + if (priv->nstdalloc == 0) + { + /* Enable the Initialization state */ + + regval = fdcan_getreg(priv, STM32_FDCAN_CCCR_OFFSET); + regval |= FDCAN_CCCR_INIT; + fdcan_putreg(priv, STM32_FDCAN_CCCR_OFFSET, regval); + + /* Wait for initialization mode to take effect */ + + while ((fdcan_getreg(priv, STM32_FDCAN_CCCR_OFFSET) & + FDCAN_CCCR_INIT) == 0); + + /* Enable writing to configuration registers */ + + regval = fdcan_getreg(priv, STM32_FDCAN_CCCR_OFFSET); + regval |= (FDCAN_CCCR_INIT | FDCAN_CCCR_CCE); + fdcan_putreg(priv, STM32_FDCAN_CCCR_OFFSET, regval); + + /* If there are no standard filters, then modify Global Filter + * Configuration so that all rejected messages are places in RX + * FIFO0. + * + * ANFS=0: Store all rejected extended frame in RX FIFO0 + */ + + regval = fdcan_getreg(priv, STM32_FDCAN_RXGFC_OFFSET); + regval &= ~FDCAN_RXGFC_ANFS_MASK; + regval |= FDCAN_RXGFC_ANFS_RX_FIFO0; + fdcan_putreg(priv, STM32_FDCAN_RXGFC_OFFSET, regval); + + /* Disable writing to configuration registers */ + + regval = fdcan_getreg(priv, STM32_FDCAN_CCCR_OFFSET); + regval &= ~(FDCAN_CCCR_INIT | FDCAN_CCCR_CCE); + fdcan_putreg(priv, STM32_FDCAN_CCCR_OFFSET, regval); + } + + /* Deactivate the filter last so that no messages are lost. */ + + stdfilter = config->msgram.stdfilters + ndx; + *stdfilter = 0; + + return OK; +} + +/**************************************************************************** + * Name: fdcan_start_busoff_recovery_sequence + * + * Description: + * This function initiates the BUS-OFF recovery sequence. + * CAN Specification Rev. 2.0 or ISO11898-1:2015. + * According the STM32G4 datasheet section 44.3.2 Software initialziation. + * + * Input Parameters: + * priv - An instance of the FDCAN driver state structure. + * + * Returned Value: + * Zero (OK) is returned on success. Otherwise a negated errno value is + * returned to indicate the nature of the error. + * + ****************************************************************************/ + +static int +fdcan_start_busoff_recovery_sequence(struct stm32_fdcan_s *priv) +{ + uint32_t regval = 0; + + DEBUGASSERT(priv); + + /* Only start BUS-OFF recovery if we are in BUS-OFF state */ + + regval = fdcan_getreg(priv, STM32_FDCAN_PSR_OFFSET); + if ((regval & FDCAN_PSR_BO) == 0) + { + return -EPERM; + } + + /* Disable initialization mode to issue the recovery sequence */ + + regval = fdcan_getreg(priv, STM32_FDCAN_CCCR_OFFSET); + regval &= ~FDCAN_CCCR_INIT; + fdcan_putreg(priv, STM32_FDCAN_CCCR_OFFSET, regval); + + return OK; +} + +/**************************************************************************** + * Name: fdcan_reset + * + * Description: + * Reset the FDCAN device. Called early to initialize the hardware. This + * function is called, before fdcan_setup() and on error conditions. + * + * Input Parameters: + * dev - An instance of the "upper half" can driver state structure. + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void fdcan_reset(struct can_dev_s *dev) +{ + struct stm32_fdcan_s *priv = NULL; + const struct stm32_config_s *config = NULL; + uint32_t regval = 0; + irqstate_t flags; + + DEBUGASSERT(dev); + priv = dev->cd_priv; + DEBUGASSERT(priv); + config = priv->config; + DEBUGASSERT(config); + + caninfo("FDCAN%d\n", config->port); + UNUSED(config); + + /* Disable all interrupts */ + + fdcan_putreg(priv, STM32_FDCAN_IE_OFFSET, 0); + fdcan_putreg(priv, STM32_FDCAN_TXBTIE_OFFSET, 0); + + /* Make sure that all buffers are released. + * + * REVISIT: What if a thread is waiting for a buffer? The following + * will not wake up any waiting threads. + */ + + /* Disable the FDCAN controller. + * REVISIT: Should fdcan_shutdown() be called here? + */ + + /* Reset the FD CAN. + * REVISIT: Since there is only a single reset for both FDCAN + * controllers, do we really want to use the RCC reset here? + * This will nuke operation of the second controller if another + * device is registered. + */ + + flags = enter_critical_section(); + regval = getreg32(STM32_RCC_APB1RSTR1); + regval |= RCC_APB1RSTR1_FDCANRST; + putreg32(regval, STM32_RCC_APB1RSTR1); + + regval &= ~RCC_APB1RSTR1_FDCANRST; + putreg32(regval, STM32_RCC_APB1RSTR1); + leave_critical_section(flags); + + priv->state = FDCAN_STATE_RESET; +} + +/**************************************************************************** + * Name: fdcan_setup + * + * Description: + * Configure the FDCAN. This method is called the first time that the FDCAN + * device is opened. This will occur when the port is first opened. + * This setup includes configuring and attaching FDCAN interrupts. + * All FDCAN interrupts are disabled upon return. + * + * Input Parameters: + * dev - An instance of the "upper half" can driver state structure. + * + * Returned Value: + * Zero on success; a negated errno on failure + * + ****************************************************************************/ + +static int fdcan_setup(struct can_dev_s *dev) +{ + struct stm32_fdcan_s *priv = NULL; + const struct stm32_config_s *config = NULL; + int ret = 0; + + DEBUGASSERT(dev); + priv = dev->cd_priv; + DEBUGASSERT(priv); + config = priv->config; + DEBUGASSERT(config); + + caninfo("FDCAN%d\n", config->port); + + /* FDCAN hardware initialization */ + + ret = fdcan_hw_initialize(priv); + if (ret < 0) + { + canerr("ERROR: FDCAN%d H/W initialization failed: %d\n", + config->port, ret); + return ret; + } + + fdcan_dumpregs(priv, "After hardware initialization"); + + /* Attach the FDCAN interrupt handlers */ + + ret = irq_attach(config->irq0, fdcan_interrupt, dev); + if (ret < 0) + { + canerr("ERROR: Failed to attach FDCAN%d line 0 IRQ (%d)", + config->port, config->irq0); + return ret; + } + + ret = irq_attach(config->irq1, fdcan_interrupt, dev); + if (ret < 0) + { + canerr("ERROR: Failed to attach FDCAN%d line 1 IRQ (%d)", + config->port, config->irq1); + return ret; + } + + priv->state = FDCAN_STATE_SETUP; + + /* Enable the interrupts at the NVIC (they are still disabled at the FDCAN + * peripheral). + */ + + up_enable_irq(config->irq0); + up_enable_irq(config->irq1); + + return OK; +} + +/**************************************************************************** + * Name: fdcan_shutdown + * + * Description: + * Disable the FDCAN. This method is called when the FDCAN device + * is closed. This method reverses the operation the setup method. + * + * Input Parameters: + * dev - An instance of the "upper half" can driver state structure. + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void fdcan_shutdown(struct can_dev_s *dev) +{ + struct stm32_fdcan_s *priv = NULL; + const struct stm32_config_s *config = NULL; + uint32_t regval = 0; + + DEBUGASSERT(dev); + priv = dev->cd_priv; + DEBUGASSERT(priv); + config = priv->config; + DEBUGASSERT(config); + + caninfo("FDCAN%d\n", config->port); + + /* Disable FDCAN interrupts at the NVIC */ + + up_disable_irq(config->irq0); + up_disable_irq(config->irq1); + + /* Disable all interrupts from the FDCAN peripheral */ + + fdcan_putreg(priv, STM32_FDCAN_IE_OFFSET, 0); + fdcan_putreg(priv, STM32_FDCAN_TXBTIE_OFFSET, 0); + + /* Detach the FDCAN interrupt handler */ + + irq_detach(config->irq0); + irq_detach(config->irq1); + + /* Disable device by setting the Clock Stop Request bit */ + + regval = fdcan_getreg(priv, STM32_FDCAN_CCCR_OFFSET); + regval |= FDCAN_CCCR_CSR; + fdcan_putreg(priv, STM32_FDCAN_CCCR_OFFSET, regval); + + /* Wait for Init and Clock Stop Acknowledge bits to verify + * device is in the powered down state + */ + + while ((fdcan_getreg(priv, STM32_FDCAN_CCCR_OFFSET) & FDCAN_CCCR_INIT) + == 0); + while ((fdcan_getreg(priv, STM32_FDCAN_CCCR_OFFSET) & FDCAN_CCCR_CSA) + == 0); + priv->state = FDCAN_STATE_DISABLED; +} + +/**************************************************************************** + * Name: fdcan_rxint + * + * Description: + * Call to enable or disable RX interrupts. + * + * Input Parameters: + * dev - An instance of the "upper half" can driver state structure. + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void fdcan_rxint(struct can_dev_s *dev, bool enable) +{ + struct stm32_fdcan_s *priv = dev->cd_priv; + uint32_t regval = 0; + + DEBUGASSERT(priv && priv->config); + + caninfo("FDCAN%d enable: %d\n", priv->config->port, enable); + + /* Enable/disable the receive interrupts */ + + regval = fdcan_getreg(priv, STM32_FDCAN_IE_OFFSET); + + if (enable) + { + regval |= priv->rxints | FDCAN_COMMON_INTS; + } + else + { + regval &= ~priv->rxints; + } + + fdcan_putreg(priv, STM32_FDCAN_IE_OFFSET, regval); +} + +/**************************************************************************** + * Name: fdcan_txint + * + * Description: + * Call to enable or disable TX interrupts. + * + * Input Parameters: + * dev - An instance of the "upper half" can driver state structure. + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void fdcan_txint(struct can_dev_s *dev, bool enable) +{ + struct stm32_fdcan_s *priv = dev->cd_priv; + uint32_t regval = 0; + + DEBUGASSERT(priv && priv->config); + + caninfo("FDCAN%d enable: %d\n", priv->config->port, enable); + + /* Enable/disable the receive interrupts */ + + regval = fdcan_getreg(priv, STM32_FDCAN_IE_OFFSET); + + if (enable) + { + regval |= priv->txints | FDCAN_COMMON_INTS; + } + else + { + regval &= ~priv->txints; + } + + fdcan_putreg(priv, STM32_FDCAN_IE_OFFSET, regval); +} + +/**************************************************************************** + * Name: fdcan_ioctl + * + * Description: + * All ioctl calls will be routed through this method + * + * Input Parameters: + * dev - An instance of the "upper half" can driver state structure. + * + * Returned Value: + * Zero on success; a negated errno on failure + * + ****************************************************************************/ + +static int fdcan_ioctl(struct can_dev_s *dev, int cmd, unsigned long arg) +{ + struct stm32_fdcan_s *priv = NULL; + int ret = -ENOTTY; + + caninfo("cmd=%04x arg=%lu\n", cmd, arg); + + DEBUGASSERT(dev && dev->cd_priv); + priv = dev->cd_priv; + + /* Handle the command */ + + switch (cmd) + { + /* CANIOC_GET_BITTIMING: + * Description: Return the current bit timing settings + * Argument: A pointer to a write-able instance of struct + * canioc_bittiming_s in which current bit timing + * values will be returned. + * Returned Value: Zero (OK) is returned on success. Otherwise -1 + * (ERROR) is returned with the errno variable set + * to indicate the nature of the error. + * Dependencies: None + */ + + case CANIOC_GET_BITTIMING: + { + struct canioc_bittiming_s *bt = + (struct canioc_bittiming_s *)arg; + uint32_t regval; + uint32_t nbrp; + + DEBUGASSERT(bt != NULL); + +#ifdef CONFIG_CAN_FD + if (bt->type == CAN_BITTIMING_DATA) + { + regval = fdcan_getreg(priv, STM32_FDCAN_DBTP_OFFSET); + bt->bt_sjw = ((regval & FDCAN_DBTP_DSJW_MASK) >> + FDCAN_DBTP_DSJW_SHIFT) + 1; + bt->bt_tseg1 = ((regval & FDCAN_DBTP_DTSEG1_MASK) >> + FDCAN_DBTP_DTSEG1_SHIFT) + 1; + bt->bt_tseg2 = ((regval & FDCAN_DBTP_DTSEG2_MASK) >> + FDCAN_DBTP_DTSEG2_SHIFT) + 1; + + nbrp = ((regval & FDCAN_DBTP_DBRP_MASK) >> + FDCAN_DBTP_DBRP_SHIFT) + 1; + bt->bt_baud = STM32_FDCANCLK_FREQUENCY / nbrp / + (bt->bt_tseg1 + bt->bt_tseg2 + 1); + } + else +#endif + { + regval = fdcan_getreg(priv, STM32_FDCAN_NBTP_OFFSET); + bt->bt_sjw = ((regval & FDCAN_NBTP_NSJW_MASK) >> + FDCAN_NBTP_NSJW_SHIFT) + 1; + bt->bt_tseg1 = ((regval & FDCAN_NBTP_NTSEG1_MASK) >> + FDCAN_NBTP_NTSEG1_SHIFT) + 1; + bt->bt_tseg2 = ((regval & FDCAN_NBTP_NTSEG2_MASK) >> + FDCAN_NBTP_NTSEG2_SHIFT) + 1; + + nbrp = ((regval & FDCAN_NBTP_NBRP_MASK) >> + FDCAN_NBTP_NBRP_SHIFT) + 1; + bt->bt_baud = STM32_FDCANCLK_FREQUENCY / nbrp / + (bt->bt_tseg1 + bt->bt_tseg2 + 1); + } + + ret = OK; + } + break; + + /* CANIOC_SET_BITTIMING: + * Description: Set new current bit timing values + * Argument: A pointer to a read-able instance of struct + * canioc_bittiming_s in which the new bit timing + * values are provided. + * Returned Value: Zero (OK) is returned on success. Otherwise -1 + * (ERROR) is returned with the errno variable set + * to indicate the nature of the error. + * Dependencies: None + * + * REVISIT: There is probably a limitation here: If there are + * multiple threads trying to send CAN packets, when one of these + * threads reconfigures the bitrate, the FDCAN hardware will be reset + * and the context of operation will be lost. Hence, this IOCTL can + * only safely be executed in quiescent time periods. + */ + + case CANIOC_SET_BITTIMING: + { + const struct canioc_bittiming_s *bt = + (const struct canioc_bittiming_s *)arg; + uint32_t nbrp; + uint32_t ntseg1; + uint32_t ntseg2; + uint32_t nsjw; + uint32_t ie; + uint8_t state; + + DEBUGASSERT(bt != NULL); + DEBUGASSERT(bt->bt_baud < STM32_FDCANCLK_FREQUENCY); + DEBUGASSERT(bt->bt_sjw > 0 && bt->bt_sjw <= 16); + DEBUGASSERT(bt->bt_tseg1 > 1 && bt->bt_tseg1 <= 64); + DEBUGASSERT(bt->bt_tseg2 > 0 && bt->bt_tseg2 <= 16); + + /* Extract bit timing data */ + + ntseg1 = bt->bt_tseg1 - 1; + ntseg2 = bt->bt_tseg2 - 1; + nsjw = bt->bt_sjw - 1; + + nbrp = (uint32_t) + (((float) STM32_FDCANCLK_FREQUENCY / + ((float)(ntseg1 + ntseg2 + 3) * (float)bt->bt_baud)) - 1); + + /* Save the value of the new bit timing register */ + +#ifdef CONFIG_CAN_FD + if (bt->type == CAN_BITTIMING_DATA) + { + priv->dbtp = FDCAN_NBTP_DBRP(nbrp) | + FDCAN_NBTP_DTSEG1(ntseg1) | + FDCAN_DBTP_DTSEG2(ntseg2) | + FDCAN_DBTP_DSJW(nsjw); + } + else +#endif + { + priv->nbtp = FDCAN_NBTP_NBRP(nbrp) | + FDCAN_NBTP_NTSEG1(ntseg1) | + FDCAN_NBTP_NTSEG2(ntseg2) | + FDCAN_NBTP_NSJW(nsjw); + } + + /* We need to reset to instantiate the new timing. Save + * current state information so that recover to this + * state. + */ + + ie = fdcan_getreg(priv, STM32_FDCAN_IE_OFFSET); + state = priv->state; + + /* Reset the FDCAN */ + + fdcan_reset(dev); + ret = OK; + + /* If we have previously been setup, then setup again */ + + if (state == FDCAN_STATE_SETUP) + { + ret = fdcan_setup(dev); + } + + /* We we have successfully re-initialized, then restore the + * interrupt state. + * + * REVISIT: Since the hardware was reset, any pending TX + * activity was lost. Should we disable TX interrupts? + */ + + if (ret == OK) + { + fdcan_putreg(priv, STM32_FDCAN_IE_OFFSET, ie & ~priv->txints); + } + } + break; + +#ifdef CONFIG_CAN_EXTID + /* CANIOC_ADD_EXTFILTER: + * Description: Add an address filter for a extended 29 bit + * address. + * Argument: A reference to struct canioc_extfilter_s + * Returned Value: A non-negative filter ID is returned on success. + * Otherwise -1 (ERROR) is returned with the errno + * variable set to indicate the nature of the error. + */ + + case CANIOC_ADD_EXTFILTER: + { + DEBUGASSERT(arg != 0); + + ret = fdcan_add_extfilter(priv, + (struct canioc_extfilter_s *)arg); + } + break; + + /* CANIOC_DEL_EXTFILTER: + * Description: Remove an address filter for a standard 29 bit + * address. + * Argument: The filter index previously returned by the + * CANIOC_ADD_EXTFILTER command + * Returned Value: Zero (OK) is returned on success. Otherwise -1 + * (ERROR) is returned with the errno variable set + * to indicate the nature of the error. + */ + + case CANIOC_DEL_EXTFILTER: + { + DEBUGASSERT(arg <= priv->config->nextfilters); + ret = fdcan_del_extfilter(priv, (int)arg); + } + break; +#endif + + /* CANIOC_ADD_STDFILTER: + * Description: Add an address filter for a standard 11 bit + * address. + * Argument: A reference to struct canioc_stdfilter_s + * Returned Value: A non-negative filter ID is returned on success. + * Otherwise -1 (ERROR) is returned with the errno + * variable set to indicate the nature of the error. + */ + + case CANIOC_ADD_STDFILTER: + { + DEBUGASSERT(arg != 0); + + ret = fdcan_add_stdfilter(priv, + (struct canioc_stdfilter_s *)arg); + } + break; + + /* CANIOC_DEL_STDFILTER: + * Description: Remove an address filter for a standard 11 bit + * address. + * Argument: The filter index previously returned by the + * CANIOC_ADD_STDFILTER command + * Returned Value: Zero (OK) is returned on success. Otherwise -1 + * (ERROR) is returned with the errno variable set + * to indicate the nature of the error. + */ + + case CANIOC_DEL_STDFILTER: + { + DEBUGASSERT(arg <= priv->config->nstdfilters); + ret = fdcan_del_stdfilter(priv, (int)arg); + } + break; + + /* CANIOC_BUSOFF_RECOVERY: + * Description : Initiates the BUS - OFF recovery sequence + * Argument : None + * Returned Value : Zero (OK) is returned on success. Otherwise -1 + * (ERROR) is returned with the errno variable set + * to indicate the nature of the error. + * Dependencies : None + */ + + case CANIOC_BUSOFF_RECOVERY: + { + ret = fdcan_start_busoff_recovery_sequence(priv); + } + break; + + /* Unsupported/unrecognized command */ + + default: + canerr("ERROR: Unrecognized command: %04x\n", cmd); + break; + } + + return ret; +} + +/**************************************************************************** + * Name: fdcan_remoterequest + * + * Description: + * Send a remote request + * + * Input Parameters: + * dev - An instance of the "upper half" can driver state structure. + * + * Returned Value: + * Zero on success; a negated errno on failure + * + ****************************************************************************/ + +static int fdcan_remoterequest(struct can_dev_s *dev, uint16_t id) +{ + /* REVISIT: Remote request not implemented */ + + return -ENOSYS; +} + +/**************************************************************************** + * Name: fdcan_send + * + * Description: + * Send one can message. + * + * One CAN-message consists of a maximum of 10 bytes. A message is + * composed of at least the first 2 bytes (when there are no data bytes). + * + * Byte 0: Bits 0-7: Bits 3-10 of the 11-bit CAN identifier + * Byte 1: Bits 5-7: Bits 0-2 of the 11-bit CAN identifier + * Bit 4: Remote Transmission Request (RTR) + * Bits 0-3: Data Length Code (DLC) + * Bytes 2-10: CAN data + * + * Input Parameters: + * dev - An instance of the "upper half" can driver state structure. + * + * Returned Value: + * Zero on success; a negated errno on failure + * + ****************************************************************************/ + +static int fdcan_send(struct can_dev_s *dev, struct can_msg_s *msg) +{ + struct stm32_fdcan_s *priv = NULL; + const struct stm32_config_s *config = NULL; + volatile uint32_t *txbuffer = NULL; + const uint8_t *src = NULL; + uint32_t *dest = NULL; + uint32_t regval = 0; + unsigned int ndx = 0; + unsigned int nbytes = 0; + uint32_t wordbuffer = 0; + unsigned int i = 0; + + DEBUGASSERT(dev); + priv = dev->cd_priv; + DEBUGASSERT(priv && priv->config); + config = priv->config; + + caninfo("CAN%" PRIu8 " ID: %" PRIu32 " DLC: %" PRIu8 "\n", + config->port, (uint32_t)msg->cm_hdr.ch_id, msg->cm_hdr.ch_dlc); + + fdcan_dumptxregs(priv, "Before send"); + + /* That that FIFO elements were configured */ + + DEBUGASSERT(config->ntxfifoq > 0); + + /* Get our reserved Tx FIFO/queue put index */ + + regval = fdcan_getreg(priv, STM32_FDCAN_TXFQS_OFFSET); + DEBUGASSERT((regval & FDCAN_TXFQS_TFQF) == 0); + + ndx = (regval & FDCAN_TXFQS_TFQPI_MASK) >> FDCAN_TXFQS_TFQPI_SHIFT; + + /* And the TX buffer corresponding to this index */ + + txbuffer = (config->msgram.txfifoq + ndx * config->txbufferesize); + + /* Format the TX FIFOQ entry + * + * Format word T0: + * Transfer message ID (ID) - Value from message structure + * Remote Transmission Request (RTR) - Value from message structure + * Extended Identifier (XTD) - Depends on configuration. + * Error state indicator (ESI) - ESI bit in CAN FD + * + * Format word T1: + * Data Length Code (DLC) - Value from message structure + * Bit Rate Switch (BRS) - Bit rate switching for CAN FD + * FD format (FDF) - Frame transmitted in CAN FD format + * Event FIFO Control (EFC) - Do not store events. + * Message Marker (MM) - Always zero + */ + + txbuffer[0] = 0; + txbuffer[1] = 0; + +#ifdef CONFIG_CAN_EXTID + if (msg->cm_hdr.ch_extid == 1) + { + DEBUGASSERT(msg->cm_hdr.ch_id <= CAN_MAX_EXTMSGID); + + txbuffer[0] |= BUFFER_R0_EXTID(msg->cm_hdr.ch_id) | BUFFER_R0_XTD; + } + else +#endif + { + DEBUGASSERT(msg->cm_hdr.ch_id <= CAN_MAX_STDMSGID); + + txbuffer[0] |= BUFFER_R0_STDID(msg->cm_hdr.ch_id); + } + + if (msg->cm_hdr.ch_rtr == 1) + { + txbuffer[0] |= BUFFER_R0_RTR; + } + + txbuffer[1] |= BUFFER_R1_DLC(msg->cm_hdr.ch_dlc); + +#ifdef CONFIG_CAN_FD + /* CAN FD Format */ + + if (msg->cm_hdr.ch_edl == 1) + { + txbuffer[1] |= BUFFER_R1_FDF; + + if (msg->cm_hdr.ch_brs == 1) + { + txbuffer[1] |= BUFFER_R1_BRS; + } + + if (msg->cm_hdr.ch_esi == 1) + { + txbuffer[0] |= BUFFER_R0_ESI; + } + } + else +#else + { + txbuffer[0] &= ~BUFFER_R0_ESI; + txbuffer[1] &= ~BUFFER_R1_FDF; + txbuffer[1] &= ~BUFFER_R1_BRS; + } +#endif + + /* Followed by the amount of data corresponding to the DLC (T2..) */ + + dest = (uint32_t *)&txbuffer[2]; + src = msg->cm_data; + nbytes = fdcan_dlc2bytes(priv, msg->cm_hdr.ch_dlc); + + /* Writes must be word length */ + + for (i = 0; i < nbytes; i += 4) + { + /* Little endian is assumed */ + + wordbuffer = src[0] | + (src[1] << 8) | + (src[2] << 16) | + (src[3] << 24); + src += 4; + + *dest++ = wordbuffer; + } + + /* Enable transmit interrupts from the TX FIFOQ buffer by setting TC + * interrupt bit in IR (also requires that the TC interrupt is enabled) + */ + + fdcan_putreg(priv, STM32_FDCAN_TXBTIE_OFFSET, (1 << ndx)); + + /* And request to send the packet */ + + fdcan_putreg(priv, STM32_FDCAN_TXBAR_OFFSET, (1 << ndx)); + + return OK; +} + +/**************************************************************************** + * Name: fdcan_txready + * + * Description: + * Return true if the FDCAN hardware can accept another TX message. + * + * Input Parameters: + * dev - An instance of the "upper half" can driver state structure. + * + * Returned Value: + * True if the FDCAN hardware is ready to accept another TX message. + * + ****************************************************************************/ + +static bool fdcan_txready(struct can_dev_s *dev) +{ + struct stm32_fdcan_s *priv = dev->cd_priv; + uint32_t regval = 0; + bool notfull = false; + + /* Return the state of the TX FIFOQ. Return TRUE if the TX FIFO/Queue is + * not full. + */ + + regval = fdcan_getreg(priv, STM32_FDCAN_TXFQS_OFFSET); + notfull = ((regval & FDCAN_TXFQS_TFQF) == 0); + + return notfull; +} + +/**************************************************************************** + * Name: fdcan_txempty + * + * Description: + * Return true if all message have been sent. If for example, the FDCAN + * hardware implements FIFOs, then this would mean the transmit FIFO is + * empty. This method is called when the driver needs to make sure that + * all characters are "drained" from the TX hardware before calling + * co_shutdown(). + * + * Input Parameters: + * dev - An instance of the "upper half" can driver state structure. + * + * Returned Value: + * True if there are no pending TX transfers in the FDCAN hardware. + * + ****************************************************************************/ + +static bool fdcan_txempty(struct can_dev_s *dev) +{ + struct stm32_fdcan_s *priv = dev->cd_priv; + uint32_t regval = 0; + int tffl = 0; + bool empty = false; + + DEBUGASSERT(priv != NULL && priv->config != NULL); + + /* Return the state of the TX FIFOQ. Return TRUE if the TX FIFO/Queue is + * empty. We don't have a reliable indication that the FIFO is empty, so + * we have to use some heuristics. + */ + + regval = fdcan_getreg(priv, STM32_FDCAN_TXFQS_OFFSET); + if ((regval & FDCAN_TXFQS_TFQF) != 0) + { + return false; + } + + /* Tx FIFO Free Level */ + + tffl = (regval & FDCAN_TXFQS_TFFL_MASK) >> FDCAN_TXFQS_TFFL_SHIFT; + empty = (tffl >= priv->config->ntxfifoq); + + return empty; +} + +/**************************************************************************** + * Name: fdcan_error + * + * Description: + * Report a CAN error + * + * Input Parameters: + * dev - CAN-common state data + * status - Interrupt status with error bits set + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_CAN_ERRORS +static void fdcan_error(struct can_dev_s *dev, uint32_t status) +{ + struct stm32_fdcan_s *priv = dev->cd_priv; + struct can_hdr_s hdr; + uint32_t psr = 0; + uint16_t errbits = 0; + uint8_t data[CAN_ERROR_DLC]; + int ret = 0; + + /* Encode error bits */ + + errbits = 0; + memset(data, 0, sizeof(data)); + + /* Always fill in "static" error conditions, but set the signaling bit + * only if the condition has changed (see IRQ-Flags below) + * They have to be filled in every time CAN_ERROR_CONTROLLER is set. + */ + + psr = fdcan_getreg(priv, STM32_FDCAN_PSR_OFFSET); + if ((psr & FDCAN_PSR_EP) != 0) + { + data[1] |= (CAN_ERROR1_RXPASSIVE | CAN_ERROR1_TXPASSIVE); + } + + if ((psr & FDCAN_PSR_EW) != 0) + { + data[1] |= (CAN_ERROR1_RXWARNING | CAN_ERROR1_TXWARNING); + } + + if ((status & (FDCAN_INT_EP | FDCAN_INT_EW)) != 0) + { + /* "Error Passive" or "Error Warning" status changed */ + + errbits |= CAN_ERROR_CONTROLLER; + } + + if ((status & FDCAN_INT_PEA) != 0) + { + /* Protocol Error in Arbitration Phase */ + + if ((psr & FDCAN_PSR_LEC_MASK) != 0) + { + /* Error code present */ + + if ((psr & FDCAN_PSR_LEC(FDCAN_PSR_EC_STUFF_ERROR)) != 0) + { + /* Stuff Error */ + + errbits |= CAN_ERROR_PROTOCOL; + data[2] |= CAN_ERROR2_STUFF; + } + + if ((psr & FDCAN_PSR_LEC(FDCAN_PSR_EC_FORM_ERROR)) != 0) + { + /* Format Error */ + + errbits |= CAN_ERROR_PROTOCOL; + data[2] |= CAN_ERROR2_FORM; + } + + if ((psr & FDCAN_PSR_LEC(FDCAN_PSR_EC_ACK_ERROR)) != 0) + { + /* Acknowledge Error */ + + errbits |= CAN_ERROR_NOACK; + } + + if ((psr & FDCAN_PSR_LEC(FDCAN_PSR_EC_BIT0_ERROR)) != 0) + { + /* Bit0 Error */ + + errbits |= CAN_ERROR_PROTOCOL; + data[2] |= CAN_ERROR2_BIT0; + } + + if ((psr & FDCAN_PSR_LEC(FDCAN_PSR_EC_BIT1_ERROR)) != 0) + { + /* Bit1 Error */ + + errbits |= CAN_ERROR_PROTOCOL; + data[2] |= CAN_ERROR2_BIT1; + } + + if ((psr & FDCAN_PSR_LEC(FDCAN_PSR_EC_CRC_ERROR)) != 0) + { + /* Receive CRC Error */ + + errbits |= CAN_ERROR_PROTOCOL; + data[3] |= (CAN_ERROR3_CRCSEQ | CAN_ERROR3_CRCDEL); + } + + if ((psr & FDCAN_PSR_LEC(FDCAN_PSR_EC_NO_CHANGE)) != 0) + { + /* No Change in Error */ + + errbits |= CAN_ERROR_PROTOCOL; + data[2] |= CAN_ERROR2_UNSPEC; + } + } + } + + if ((status & FDCAN_INT_PED) != 0) + { + /* Protocol Error in Data Phase */ + + if ((psr & FDCAN_PSR_DLEC_MASK) != 0) + { + /* Error code present */ + + if ((psr & FDCAN_PSR_DLEC(FDCAN_PSR_EC_STUFF_ERROR)) != 0) + { + /* Stuff Error */ + + errbits |= CAN_ERROR_PROTOCOL; + data[2] |= CAN_ERROR2_STUFF; + } + + if ((psr & FDCAN_PSR_DLEC(FDCAN_PSR_EC_FORM_ERROR)) != 0) + { + /* Format Error */ + + errbits |= CAN_ERROR_PROTOCOL; + data[2] |= CAN_ERROR2_FORM; + } + + if ((psr & FDCAN_PSR_DLEC(FDCAN_PSR_EC_ACK_ERROR)) != 0) + { + /* Acknowledge Error */ + + errbits |= CAN_ERROR_NOACK; + } + + if ((psr & FDCAN_PSR_DLEC(FDCAN_PSR_EC_BIT0_ERROR)) != 0) + { + /* Bit0 Error */ + + errbits |= CAN_ERROR_PROTOCOL; + data[2] |= CAN_ERROR2_BIT0; + } + + if ((psr & FDCAN_PSR_DLEC(FDCAN_PSR_EC_BIT1_ERROR)) != 0) + { + /* Bit1 Error */ + + errbits |= CAN_ERROR_PROTOCOL; + data[2] |= CAN_ERROR2_BIT1; + } + + if ((psr & FDCAN_PSR_DLEC(FDCAN_PSR_EC_CRC_ERROR)) != 0) + { + /* Receive CRC Error */ + + errbits |= CAN_ERROR_PROTOCOL; + data[3] |= (CAN_ERROR3_CRCSEQ | CAN_ERROR3_CRCDEL); + } + + if ((psr & FDCAN_PSR_DLEC(FDCAN_PSR_EC_NO_CHANGE)) != 0) + { + /* No Change in Error */ + + errbits |= CAN_ERROR_PROTOCOL; + data[2] |= CAN_ERROR2_UNSPEC; + } + } + } + + if ((status & FDCAN_INT_BO) != 0) + { + /* Bus_Off Status changed */ + + if ((psr & FDCAN_PSR_BO) != 0) + { + errbits |= CAN_ERROR_BUSOFF; + } + else + { + errbits |= CAN_ERROR_RESTARTED; + } + } + + if ((status & (FDCAN_INT_RF0L | FDCAN_INT_RF1L)) != 0) + { + /* Receive FIFO 0/1 Message Lost + * Receive FIFO 1 Message Lost + */ + + errbits |= CAN_ERROR_CONTROLLER; + data[1] |= CAN_ERROR1_RXOVERFLOW; + } + + if ((status & FDCAN_INT_TEFL) != 0) + { + /* Tx Event FIFO Element Lost */ + + errbits |= CAN_ERROR_CONTROLLER; + data[1] |= CAN_ERROR1_TXOVERFLOW; + } + + if ((status & FDCAN_INT_TOO) != 0) + { + /* Timeout Occurred */ + + errbits |= CAN_ERROR_TXTIMEOUT; + } + + if ((status & (FDCAN_INT_MRAF | FDCAN_INT_ELO)) != 0) + { + /* Message RAM Access Failure + * Error Logging Overflow + */ + + errbits |= CAN_ERROR_CONTROLLER; + data[1] |= CAN_ERROR1_UNSPEC; + } + + if (errbits != 0) + { + /* Format the CAN header for the error report. */ + + hdr.ch_id = errbits; + hdr.ch_dlc = CAN_ERROR_DLC; + hdr.ch_rtr = 0; + hdr.ch_error = 1; +#ifdef CONFIG_CAN_EXTID + hdr.ch_extid = 0; +#endif + hdr.ch_tcf = 0; + + /* And provide the error report to the upper half logic */ + + ret = can_receive(dev, &hdr, data); + if (ret < 0) + { + canerr("ERROR: can_receive failed: %d\n", ret); + } + } +} +#endif /* CONFIG_CAN_ERRORS */ + +/**************************************************************************** + * Name: fdcan_receive + * + * Description: + * Receive an FDCAN messages + * + * Input Parameters: + * dev - CAN-common state data + * rxbuffer - The RX buffer containing the received messages + * nwords - The length of the RX buffer (element size in words). + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void fdcan_receive(struct can_dev_s *dev, + volatile uint32_t *rxbuffer, + unsigned long nwords) +{ + struct can_hdr_s hdr; + int ret = 0; + + fdcan_dumprxregs(dev->cd_priv, "Before receive"); + + /* Format the CAN header */ + + /* Word R0 contains the CAN ID */ + +#ifdef CONFIG_CAN_ERRORS + hdr.ch_error = 0; +#endif + hdr.ch_tcf = 0; + + /* Extract the RTR bit */ + + hdr.ch_rtr = ((rxbuffer[0] & BUFFER_R0_RTR) != 0); + +#ifdef CONFIG_CAN_EXTID + if ((rxbuffer[0] & BUFFER_R0_XTD) != 0) + { + /* Save the extended ID of the newly received message */ + + hdr.ch_id = (rxbuffer[0] & BUFFER_R0_EXTID_MASK) >> + BUFFER_R0_EXTID_SHIFT; + hdr.ch_extid = 1; + } + else + { + hdr.ch_id = (rxbuffer[0] & BUFFER_R0_STDID_MASK) >> + BUFFER_R0_STDID_SHIFT; + hdr.ch_extid = 0; + } + +#else + if ((rxbuffer[0] & BUFFER_R0_XTD) != 0) + { + /* Drop any messages with extended IDs */ + + canerr("ERROR: Received message with extended identifier. Dropped\n"); + + return; + } + + /* Save the standard ID of the newly received message */ + + hdr.ch_id = (rxbuffer[0] & BUFFER_R0_STDID_MASK) >> BUFFER_R0_STDID_SHIFT; +#endif + + /* Word R1 contains the DLC and timestamp */ + + hdr.ch_dlc = (rxbuffer[1] & BUFFER_R1_DLC_MASK) >> BUFFER_R1_DLC_SHIFT; + +#ifdef CONFIG_CAN_FD + /* CAN FD format */ + + hdr.ch_esi = ((rxbuffer[0] & BUFFER_R0_ESI) != 0); + hdr.ch_edl = ((rxbuffer[1] & BUFFER_R1_FDF) != 0); + hdr.ch_brs = ((rxbuffer[1] & BUFFER_R1_BRS) != 0); +#else + if ((rxbuffer[1] & BUFFER_R1_FDF) != 0) + { + /* Drop any FD CAN messages if not supported */ + + canerr("ERROR: Received CAN FD message. Dropped\n"); + + return; + } +#endif + + /* And provide the CAN message to the upper half logic */ + + ret = can_receive(dev, &hdr, (uint8_t *)&rxbuffer[2]); + if (ret < 0) + { + canerr("ERROR: can_receive failed: %d\n", ret); + } +} + +/**************************************************************************** + * Name: fdcan_interrupt + * + * Description: + * Common FDCAN interrupt handler + * + * Input Parameters: + * dev - CAN-common state data + * + * Returned Value: + * None + * + ****************************************************************************/ + +static int fdcan_interrupt(int irq, void *context, void *arg) +{ + struct can_dev_s *dev = (struct can_dev_s *)arg; + struct stm32_fdcan_s *priv = NULL; + const struct stm32_config_s *config = NULL; + uint32_t ir = 0; + uint32_t ie = 0; + uint32_t pending = 0; + uint32_t regval = 0; + uint32_t psr = 0; + unsigned int nelem = 0; + unsigned int ndx = 0; + + DEBUGASSERT(dev != NULL); + priv = dev->cd_priv; + DEBUGASSERT(priv && priv->config); + config = priv->config; + + /* Get the set of pending interrupts. */ + + ir = fdcan_getreg(priv, STM32_FDCAN_IR_OFFSET); + ie = fdcan_getreg(priv, STM32_FDCAN_IE_OFFSET); + + pending = (ir & ie); + + /* Check for any errors */ + + if ((pending & FDCAN_ANYERR_INTS) != 0) + { + /* Check for common errors */ + + if ((pending & FDCAN_CMNERR_INTS) != 0) + { + canerr("ERROR: Common %08" PRIx32 "\n", + pending & FDCAN_CMNERR_INTS); + + /* When a protocol error occurs, the problem is recorded in + * the LEC/DLEC fields of the PSR register. In lieu of + * separate interrupt flags for each error, the hardware + * groups protocol errors under a single interrupt each for + * arbitration and data phases. + * + * These errors have a tendency to flood the system with + * interrupts, so they are disabled here until we get a + * successful transfer/receive on the hardware + */ + + psr = fdcan_getreg(priv, STM32_FDCAN_PSR_OFFSET); + + if ((psr & FDCAN_PSR_LEC_MASK) != 0) + { + canerr("ERROR: PSR %08" PRIx32 "\n", psr); + ie &= ~(FDCAN_INT_PEA | FDCAN_INT_PED); + fdcan_putreg(priv, STM32_FDCAN_IE_OFFSET, ie); + caninfo("disabled protocol error interrupts\n"); + } + + /* Clear the error indications */ + + fdcan_putreg(priv, STM32_FDCAN_IR_OFFSET, FDCAN_CMNERR_INTS); + } + + /* Check for transmission errors */ + + if ((pending & FDCAN_TXERR_INTS) != 0) + { + canerr("ERROR: TX %08" PRIx32 "\n", + pending & FDCAN_TXERR_INTS); + + /* An Acknowledge-Error will occur if for example the device + * is not connected to the bus. + * + * The CAN-Standard states that the Chip has to retry the + * message forever, which will produce an ACKE every time. + * To prevent this Interrupt-Flooding and the high CPU-Load + * we disable the ACKE here as long we didn't transfer at + * least one message successfully (see FDCAN_INT_TC below). + */ + + /* Clear the error indications */ + + fdcan_putreg(priv, STM32_FDCAN_IR_OFFSET, FDCAN_TXERR_INTS); + } + + /* Check for reception errors */ + + if ((pending & FDCAN_RXERR_INTS) != 0) + { + canerr("ERROR: RX %08" PRIx32 "\n", + pending & FDCAN_RXERR_INTS); + + /* To prevent Interrupt-Flooding the current active + * RX error interrupts are disabled. After successfully + * receiving at least one CAN packet all RX error interrupts + * are turned back on. + * + * The Interrupt-Flooding can for example occur if the + * configured CAN speed does not match the speed of the other + * CAN nodes in the network. + */ + + ie &= ~(pending & FDCAN_RXERR_INTS); + fdcan_putreg(priv, STM32_FDCAN_IE_OFFSET, ie); + + /* Clear the error indications */ + + fdcan_putreg(priv, STM32_FDCAN_IR_OFFSET, FDCAN_RXERR_INTS); + } + +#ifdef CONFIG_CAN_ERRORS + /* Report errors */ + + fdcan_error(dev, pending & FDCAN_ANYERR_INTS); +#endif + } + + /* Check for successful completion of a transmission */ + + if ((pending & FDCAN_INT_TC) != 0) + { + /* Check if we have disabled the ACKE in the error-handling above + * (see FDCAN_TXERR_INTS) to prevent Interrupt-Flooding and + * re-enable the error interrupt here again. + */ + + if ((ie & (FDCAN_INT_PEA | FDCAN_INT_PED)) == 0) + { + ie |= (FDCAN_INT_PEA | FDCAN_INT_PED); + fdcan_putreg(priv, STM32_FDCAN_IE_OFFSET, ie); + caninfo("Re-enabled protocol error interrupts\n"); + } + + /* Clear the pending TX completion interrupt (and all + * other TX-related interrupts) + */ + + fdcan_putreg(priv, STM32_FDCAN_IR_OFFSET, priv->txints); + + /* Check all TX buffers */ + + regval = fdcan_getreg(priv, STM32_FDCAN_TXBTO_OFFSET); + for (ndx = 0; ndx < config->ntxfifoq; ndx++) + { + if ((regval & (1 << ndx)) != 0) + { + /* Tell the upper half that the transfer is finished. */ + + can_txdone(dev); + } + } + } + else if ((pending & priv->txints) != 0) + { + /* Clear unhandled TX events */ + + fdcan_putreg(priv, STM32_FDCAN_IR_OFFSET, priv->txints); + } + + /* Clear the RX FIFO1 new message interrupt */ + + fdcan_putreg(priv, STM32_FDCAN_IR_OFFSET, FDCAN_INT_RF1N); + pending &= ~FDCAN_INT_RF1N; + + /* We treat RX FIFO1 as the "high priority" queue: We will process + * all messages in RX FIFO1 before processing any message from RX + * FIFO0. + */ + + for (; ; ) + { + /* Check if there is anything in RX FIFO1 */ + + regval = fdcan_getreg(priv, STM32_FDCAN_RXF1S_OFFSET); + nelem = (regval & FDCAN_RXFS_FFL_MASK) >> FDCAN_RXFS_FFL_SHIFT; + if (nelem == 0) + { + /* Break out of the loop if RX FIFO1 is empty */ + + break; + } + + /* Clear the RX FIFO1 interrupt (and all other FIFO1-related + * interrupts) + */ + + /* Handle the newly received message in FIFO1 */ + + ndx = (regval & FDCAN_RXFS_FGI_MASK) >> FDCAN_RXFS_FGI_SHIFT; + + if ((regval & FDCAN_RXFS_RFL) != 0) + { + canerr("ERROR: Message lost: %08" PRIx32 "\n", regval); + } + else + { + fdcan_receive(dev, + config->msgram.rxfifo1 + + (ndx * priv->config->rxfifo1esize), + priv->config->rxfifo1esize); + + /* Turning back on all configured RX error interrupts */ + + ie |= (priv->rxints & FDCAN_RXERR_INTS); + fdcan_putreg(priv, STM32_FDCAN_IE_OFFSET, ie); + } + + /* Acknowledge reading the FIFO entry */ + + fdcan_putreg(priv, STM32_FDCAN_RXF1A_OFFSET, ndx); + } + + /* Check for successful reception of a new message in RX FIFO0 */ + + /* Clear the RX FIFO0 new message interrupt */ + + fdcan_putreg(priv, STM32_FDCAN_IR_OFFSET, FDCAN_INT_RF0N); + pending &= ~FDCAN_INT_RF0N; + + /* Check if there is anything in RX FIFO0 */ + + regval = fdcan_getreg(priv, STM32_FDCAN_RXF0S_OFFSET); + nelem = (regval & FDCAN_RXFS_FFL_MASK) >> FDCAN_RXFS_FFL_SHIFT; + if (nelem > 0) + { + /* Handle the newly received message in FIFO0 */ + + ndx = (regval & FDCAN_RXFS_FGI_MASK) >> FDCAN_RXFS_FGI_SHIFT; + + if ((regval & FDCAN_RXFS_RFL) != 0) + { + canerr("ERROR: Message lost: %08" PRIx32 "\n", regval); + } + else + { + fdcan_receive(dev, + config->msgram.rxfifo0 + + (ndx * priv->config->rxfifo0esize), + priv->config->rxfifo0esize); + + /* Turning back on all configured RX error interrupts */ + + ie |= (priv->rxints & FDCAN_RXERR_INTS); + fdcan_putreg(priv, STM32_FDCAN_IE_OFFSET, ie); + } + + /* Acknowledge reading the FIFO entry */ + + fdcan_putreg(priv, STM32_FDCAN_RXF0A_OFFSET, ndx); + } + + /* Clear unhandled RX interrupts */ + + if ((pending & priv->rxints) != 0) + { + fdcan_putreg(priv, STM32_FDCAN_IR_OFFSET, priv->rxints); + } + + return OK; +} + +/**************************************************************************** + * Name: fdcan_hw_initialize + * + * Description: + * FDCAN hardware initialization + * + * Input Parameters: + * priv - A pointer to the private data structure for this FDCAN peripheral + * + * Returned Value: + * Zero on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int fdcan_hw_initialize(struct stm32_fdcan_s *priv) +{ + const struct stm32_config_s *config = priv->config; + volatile uint32_t *msgram = NULL; + uint32_t regval = 0; + uint32_t cntr = 0; + + caninfo("FDCAN%d\n", config->port); + + /* Clean message RAM */ + + msgram = config->msgram.stdfilters; + cntr = (FDCAN_MSGRAM_WORDS + 1); + while (cntr > 0) + { + *msgram++ = 0; + cntr--; + } + + /* Configure FDCAN pins */ + + stm32_configgpio(config->rxpinset); + stm32_configgpio(config->txpinset); + + /* Re-enable device if previously disabled in fdcan_shutdown() */ + + if (priv->state == FDCAN_STATE_DISABLED) + { + /* Reset Clock Stop Request bit */ + + regval = fdcan_getreg(priv, STM32_FDCAN_CCCR_OFFSET); + regval &= ~FDCAN_CCCR_CSR; + fdcan_putreg(priv, STM32_FDCAN_CCCR_OFFSET, regval); + + /* Wait for Clock Stop Acknowledge bit reset to indicate + * device is operational + */ + + while ((fdcan_getreg(priv, STM32_FDCAN_CCCR_OFFSET) & FDCAN_CCCR_CSA) + != 0); + } + + /* Enable the Initialization state */ + + regval = fdcan_getreg(priv, STM32_FDCAN_CCCR_OFFSET); + regval |= FDCAN_CCCR_INIT; + fdcan_putreg(priv, STM32_FDCAN_CCCR_OFFSET, regval); + + /* Wait for initialization mode to take effect */ + + while ((fdcan_getreg(priv, STM32_FDCAN_CCCR_OFFSET) & FDCAN_CCCR_INIT) + == 0); + + /* Enable writing to configuration registers */ + + regval = fdcan_getreg(priv, STM32_FDCAN_CCCR_OFFSET); + regval |= FDCAN_CCCR_CCE; + fdcan_putreg(priv, STM32_FDCAN_CCCR_OFFSET, regval); + + /* Global Filter Configuration: + * + * ANFS=0: Store all non matching standard frame in RX FIFO0 + * ANFE=0: Store all non matching extended frame in RX FIFO0 + */ + + regval = FDCAN_RXGFC_ANFE_RX_FIFO0 | FDCAN_RXGFC_ANFS_RX_FIFO0; + fdcan_putreg(priv, STM32_FDCAN_RXGFC_OFFSET, regval); + + /* Extended ID Filter AND mask */ + + fdcan_putreg(priv, STM32_FDCAN_XIDAM_OFFSET, 0x1fffffff); + + /* Disable all interrupts */ + + fdcan_putreg(priv, STM32_FDCAN_IE_OFFSET, 0); + fdcan_putreg(priv, STM32_FDCAN_TXBTIE_OFFSET, 0); + + /* All interrupts directed to Line 0. But disable both interrupt lines 0 + * and 1 for now. + * + * REVISIT: Only interrupt line 0 is used by this driver. + */ + + fdcan_putreg(priv, STM32_FDCAN_ILS_OFFSET, 0); + fdcan_putreg(priv, STM32_FDCAN_ILE_OFFSET, 0); + + /* Clear all pending interrupts. */ + + fdcan_putreg(priv, STM32_FDCAN_IR_OFFSET, FDCAN_INT_ALL); + + /* Configure FDCAN bit timing */ + + fdcan_putreg(priv, STM32_FDCAN_NBTP_OFFSET, priv->nbtp); + fdcan_putreg(priv, STM32_FDCAN_DBTP_OFFSET, priv->dbtp); + + /* Configure message RAM starting addresses and sizes. */ + + regval = FDCAN_RXGFC_LSS(config->nstdfilters); + regval |= FDCAN_RXGFC_LSE(config->nextfilters); + fdcan_putreg(priv, STM32_FDCAN_RXGFC_OFFSET, regval); + + /* Dump RAM layout */ + + fdcan_dumpramlayout(priv); + + /* Configure Message Filters */ + + /* Disable all standard filters */ + + msgram = config->msgram.stdfilters; + cntr = config->nstdfilters; + while (cntr > 0) + { + *msgram++ = STDFILTER_S0_SFEC_DISABLE; + cntr--; + } + + /* Disable all extended filters */ + + msgram = config->msgram.extfilters; + cntr = config->nextfilters; + while (cntr > 0) + { + *msgram = EXTFILTER_F0_EFEC_DISABLE; + msgram = msgram + 2; + cntr--; + } + + /* Input clock divider configuration */ + + regval = FDCANCLK_PDIV; + fdcan_putreg(priv, STM32_FDCAN_CKDIV_OFFSET, regval); + + /* CC control register */ + + regval = fdcan_getreg(priv, STM32_FDCAN_CCCR_OFFSET); + regval &= ~(FDCAN_CCCR_NISO | FDCAN_CCCR_FDOE | FDCAN_CCCR_BRSE); + + /* Select ISO11898-1 or Non ISO Bosch CAN FD Specification V1.0 */ + + switch (config->format) + { + case FDCAN_ISO11898_1_FORMAT: + { + break; + } + + case FDCAN_NONISO_BOSCH_V1_FORMAT: + { + regval |= FDCAN_CCCR_NISO; + break; + } + + default: + { + return -EINVAL; + } + } + + /* Select Classic CAN mode or FD mode with or without fast bit rate + * switching + */ + + switch (config->mode) + { + case FDCAN_CLASSIC_MODE: + { + break; + } + +#ifdef CONFIG_CAN_FD + case FDCAN_FD_MODE: + { + regval |= FDCAN_CCCR_FDOE; + break; + } + + case FDCAN_FD_BRS_MODE: + { + regval |= (FDCAN_CCCR_FDOE | FDCAN_CCCR_BRSE); + break; + } +#endif + + default: + { + return -EINVAL; + } + } + + /* Set the initial CAN mode */ + + fdcan_putreg(priv, STM32_FDCAN_CCCR_OFFSET, regval); + + /* Enable FIFO/Queue mode */ + + regval = fdcan_getreg(priv, STM32_FDCAN_TXBC_OFFSET); +#ifdef CONFIG_STM32_FDCAN_QUEUE_MODE + regval |= FDCAN_TXBC_TFQM; +#else + regval &= ~FDCAN_TXBC_TFQM; +#endif + fdcan_putreg(priv, STM32_FDCAN_TXBC_OFFSET, regval); + +#ifdef STM32_FDCAN_LOOPBACK + /* Is loopback mode selected for this peripheral? */ + + if (config->loopback) + { + /* FDCAN_CCCR_TEST - Test mode enable + * FDCAN_CCCR_MON - Bus monitoring mode (for internal loopback) + * FDCAN_TEST_LBCK - Loopback mode + */ + + regval = fdcan_getreg(priv, STM32_FDCAN_CCCR_OFFSET); + regval |= (FDCAN_CCCR_TEST | FDCAN_CCCR_MON); + fdcan_putreg(priv, STM32_FDCAN_CCCR_OFFSET, regval); + + regval = fdcan_getreg(priv, STM32_FDCAN_TEST_OFFSET); + regval |= FDCAN_TEST_LBCK; + fdcan_putreg(priv, STM32_FDCAN_TEST_OFFSET, regval); + } +#endif + + /* Configure interrupt lines */ + + /* Select RX-related interrupts */ + + priv->rxints = FDCAN_RXFIFO_INTS; + + /* Select TX-related interrupts */ + + priv->txints = FDCAN_TXFIFOQ_INTS; + + /* Direct all interrupts to Line 0. + * + * Bits in the ILS register correspond to each FDCAN interrupt; A bit + * set to '1' is directed to interrupt line 1; a bit cleared to '0' + * is directed interrupt line 0. + * + * REVISIT: Nothing is done here. Only interrupt line 0 is used by + * this driver and ILS was already cleared above. + */ + + /* Enable only interrupt line 0. */ + + fdcan_putreg(priv, STM32_FDCAN_ILE_OFFSET, FDCAN_ILE_EINT0); + + /* Disable initialization mode to enable normal operation */ + + regval = fdcan_getreg(priv, STM32_FDCAN_CCCR_OFFSET); + regval &= ~FDCAN_CCCR_INIT; + fdcan_putreg(priv, STM32_FDCAN_CCCR_OFFSET, regval); + + return OK; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_fdcaninitialize + * + * Description: + * Initialize the selected FDCAN port + * + * Input Parameters: + * port - Port number (for hardware that has multiple FDCAN interfaces), + * 1=FDCAN1, 2=FDCAN2, 3=FDCAN3 + * + * Returned Value: + * Valid CAN device structure reference on success; a NULL on failure + * + ****************************************************************************/ + +struct can_dev_s *stm32_fdcaninitialize(int port) +{ + struct can_dev_s *dev = NULL; + struct stm32_fdcan_s *priv = NULL; + const struct stm32_config_s *config = NULL; + + caninfo("FDCAN%d\n", port); + + /* Select FDCAN peripheral to be initialized */ + +#ifdef CONFIG_STM32_FDCAN1 + if (port == FDCAN1) + { + /* Select the FDCAN1 device structure */ + + dev = &g_fdcan1dev; + priv = &g_fdcan1priv; + config = &g_fdcan1const; + } + else +#endif +#ifdef CONFIG_STM32_FDCAN2 + if (port == FDCAN2) + { + /* Select the FDCAN2 device structure */ + + dev = &g_fdcan2dev; + priv = &g_fdcan2priv; + config = &g_fdcan2const; + } + else +#endif +#ifdef CONFIG_STM32_FDCAN3 + if (port == FDCAN3) + { + /* Select the FDCAN3 device structure */ + + dev = &g_fdcan3dev; + priv = &g_fdcan3priv; + config = &g_fdcan3const; + } + else +#endif + { + canerr("ERROR: Unsupported port %d\n", port); + return NULL; + } + + /* Perform one time data initialization */ + + memset(priv, 0, sizeof(struct stm32_fdcan_s)); + priv->config = config; + + /* Set the initial bit timing. This might change subsequently + * due to IOCTL command processing. + */ + + priv->nbtp = config->nbtp; + priv->dbtp = config->dbtp; + + dev->cd_ops = &g_fdcanops; + dev->cd_priv = (void *)priv; + + /* And put the hardware in the initial state */ + + fdcan_reset(dev); + + return dev; +} diff --git a/arch/arm/src/common/stm32/stm32_fdcan_m3m4_v1_sock.c b/arch/arm/src/common/stm32/stm32_fdcan_m3m4_v1_sock.c new file mode 100644 index 0000000000000..55d16f4234960 --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_fdcan_m3m4_v1_sock.c @@ -0,0 +1,3327 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_fdcan_m3m4_v1_sock.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include +#include +#include + +#include "arm_internal.h" +#include "stm32_fdcan.h" +#include "hardware/stm32_pinmap.h" +#include "stm32_gpio.h" +#include "stm32_rcc.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Pool configuration *******************************************************/ + +#define POOL_SIZE (1) + +/* Work queue support is required. */ + +#if !defined(CONFIG_SCHED_WORKQUEUE) +# error Work queue support is required +#endif + +/* The low priority work queue is preferred. If it is not enabled, LPWORK + * will be the same as HPWORK. + * + * NOTE: However, the network should NEVER run on the high priority work + * queue! That queue is intended only to service short back end interrupt + * processing that never suspends. Suspending the high priority work queue + * may bring the system to its knees! + */ + +#define CANWORK LPWORK + +/* Clock source *************************************************************/ + +#define FDCANCLK_PDIV (0) + +#if FDCANCLK_PDIV == 0 +# define STM32_FDCANCLK_FREQUENCY (STM32_FDCAN_FREQUENCY / (1)) +#else +# define STM32_FDCANCLK_FREQUENCY (STM32_FDCAN_FREQUENCY / (2 * FDCANCLK_PDIV)) +#endif + +/* General Configuration ****************************************************/ + +#if defined(CONFIG_STM32_STM32G4XXX) + +/* FDCAN Message RAM */ + +# define FDCAN_MSGRAM_WORDS (212) +# define STM32_CANRAM1_BASE (STM32_CANRAM_BASE + 0x0000) +# define STM32_CANRAM2_BASE (STM32_CANRAM_BASE + 1*(FDCAN_MSGRAM_WORDS * 4) + 4) +# define STM32_CANRAM3_BASE (STM32_CANRAM_BASE + 2*(FDCAN_MSGRAM_WORDS * 4) + 4) + +# ifdef CONFIG_STM32_FDCAN1 +# define FDCAN1_STDFILTER_SIZE (28) +# define FDCAN1_EXTFILTER_SIZE (8) +# define FDCAN1_RXFIFO0_SIZE (3) +# define FDCAN1_RXFIFO1_SIZE (3) +# define FDCAN1_TXEVENTFIFO_SIZE (3) +# define FDCAN1_TXFIFIOQ_SIZE (3) + +# define FDCAN1_STDFILTER_WORDS (28) +# define FDCAN1_EXTFILTER_WORDS (16) +# define FDCAN1_RXFIFO0_WORDS (54) +# define FDCAN1_RXFIFO1_WORDS (54) +# define FDCAN1_TXEVENTFIFO_WORDS (6) +# define FDCAN1_TXFIFIOQ_WORDS (54) +# endif +# ifdef CONFIG_STM32_FDCAN2 +# define FDCAN2_STDFILTER_SIZE (28) +# define FDCAN2_EXTFILTER_SIZE (8) +# define FDCAN2_RXFIFO0_SIZE (3) +# define FDCAN2_RXFIFO1_SIZE (3) +# define FDCAN2_TXEVENTFIFO_SIZE (3) +# define FDCAN2_TXFIFIOQ_SIZE (3) + +# define FDCAN2_STDFILTER_WORDS (28) +# define FDCAN2_EXTFILTER_WORDS (16) +# define FDCAN2_RXFIFO0_WORDS (54) +# define FDCAN2_RXFIFO1_WORDS (54) +# define FDCAN2_TXEVENTFIFO_WORDS (6) +# define FDCAN2_TXFIFIOQ_WORDS (54) +# endif +# ifdef CONFIG_STM32_FDCAN3 +# define FDCAN3_STDFILTER_SIZE (28) +# define FDCAN3_EXTFILTER_SIZE (8) +# define FDCAN3_RXFIFO0_SIZE (3) +# define FDCAN3_RXFIFO1_SIZE (3) +# define FDCAN3_TXEVENTFIFO_SIZE (3) +# define FDCAN3_TXFIFIOQ_SIZE (3) + +# define FDCAN3_STDFILTER_WORDS (28) +# define FDCAN3_EXTFILTER_WORDS (16) +# define FDCAN3_RXFIFO0_WORDS (54) +# define FDCAN3_RXFIFO1_WORDS (54) +# define FDCAN3_TXEVENTFIFO_WORDS (6) +# define FDCAN3_TXFIFIOQ_WORDS (54) +# endif +#else +# error +#endif + +/* FDCAN1 Configuration *****************************************************/ + +#ifdef CONFIG_STM32_FDCAN1 + +/* Bit timing */ + +# define FDCAN1_NTSEG1 (CONFIG_STM32_FDCAN1_NTSEG1 - 1) +# define FDCAN1_NTSEG2 (CONFIG_STM32_FDCAN1_NTSEG2 - 1) +# define FDCAN1_NBRP ((STM32_FDCANCLK_FREQUENCY / \ + ((FDCAN1_NTSEG1 + FDCAN1_NTSEG2 + 3) * \ + CONFIG_STM32_FDCAN1_BITRATE)) - 1) +# define FDCAN1_NSJW (CONFIG_STM32_FDCAN1_NSJW - 1) + +# if FDCAN1_NTSEG1 > FDCAN_NBTP_NTSEG1_MAX +# error Invalid FDCAN1 NTSEG1 +# endif +# if FDCAN1_NTSEG2 > FDCAN_NBTP_NTSEG2_MAX +# error Invalid FDCAN1 NTSEG2 +# endif +# if FDCAN1_NSJW > FDCAN_NBTP_NSJW_MAX +# error Invalid FDCAN1 NSJW +# endif +# if FDCAN1_NBRP > FDCAN_NBTP_NBRP_MAX +# error Invalid FDCAN1 NBRP +# endif + +# ifdef CONFIG_STM32_FDCAN1_FD_BRS +# define FDCAN1_DTSEG1 (CONFIG_STM32_FDCAN1_DTSEG1 - 1) +# define FDCAN1_DTSEG2 (CONFIG_STM32_FDCAN1_DTSEG2 - 1) +# define FDCAN1_DBRP ((STM32_FDCANCLK_FREQUENCY / \ + ((FDCAN1_DTSEG1 + FDCAN1_DTSEG2 + 3) * \ + CONFIG_STM32_FDCAN1_DBITRATE)) - 1) +# define FDCAN1_DSJW (CONFIG_STM32_FDCAN1_DSJW - 1) +# else +# define FDCAN1_DTSEG1 1 +# define FDCAN1_DTSEG2 1 +# define FDCAN1_DBRP 1 +# define FDCAN1_DSJW 1 +# endif /* CONFIG_STM32_FDCAN1_FD_BRS */ + +# if FDCAN1_DTSEG1 > FDCAN_DBTP_DTSEG1_MAX +# error Invalid FDCAN1 DTSEG1 +# endif +# if FDCAN1_DTSEG2 > FDCAN_DBTP_DTSEG2_MAX +# error Invalid FDCAN1 DTSEG2 +# endif +# if FDCAN1_DBRP > FDCAN_DBTP_DBRP_MAX +# error Invalid FDCAN1 DBRP +# endif +# if FDCAN1_DSJW > FDCAN_DBTP_DSJW_MAX +# error Invalid FDCAN1 DSJW +# endif + +/* FDCAN1 Message RAM Configuration *****************************************/ + +/* FDCAN1 Message RAM Layout */ + +# define FDCAN1_STDFILTER_INDEX 0 +# define FDCAN1_EXTFILTERS_INDEX (FDCAN1_STDFILTER_INDEX + FDCAN1_STDFILTER_WORDS) +# define FDCAN1_RXFIFO0_INDEX (FDCAN1_EXTFILTERS_INDEX + FDCAN1_EXTFILTER_WORDS) +# define FDCAN1_RXFIFO1_INDEX (FDCAN1_RXFIFO0_INDEX + FDCAN1_RXFIFO0_WORDS) +# define FDCAN1_TXEVENTFIFO_INDEX (FDCAN1_RXFIFO1_INDEX + FDCAN1_RXFIFO1_WORDS) +# define FDCAN1_TXFIFOQ_INDEX (FDCAN1_TXEVENTFIFO_INDEX + FDCAN1_TXEVENTFIFO_WORDS) +# define FDCAN1_MSGRAM_WORDS (FDCAN1_TXFIFOQ_INDEX + FDCAN1_TXFIFIOQ_WORDS) + +#endif /* CONFIG_STM32_FDCAN1 */ + +/* FDCAN2 Configuration *****************************************************/ + +#ifdef CONFIG_STM32_FDCAN2 + +/* Bit timing */ + +# define FDCAN2_NTSEG1 (CONFIG_STM32_FDCAN2_NTSEG1 - 1) +# define FDCAN2_NTSEG2 (CONFIG_STM32_FDCAN2_NTSEG2 - 1) +# define FDCAN2_NBRP (((STM32_FDCANCLK_FREQUENCY / \ + ((FDCAN2_NTSEG1 + FDCAN2_NTSEG2 + 3) * \ + CONFIG_STM32_FDCAN2_BITRATE)) - 1)) +# define FDCAN2_NSJW (CONFIG_STM32_FDCAN2_NSJW - 1) + +# if FDCAN2_NTSEG1 > FDCAN_NBTP_NTSEG1_MAX +# error Invalid FDCAN2 NTSEG1 +# endif +# if FDCAN2_NTSEG2 > FDCAN_NBTP_NTSEG2_MAX +# error Invalid FDCAN2 NTSEG2 +# endif +# if FDCAN2_NSJW > FDCAN_NBTP_NSJW_MAX +# error Invalid FDCAN2 NSJW +# endif +# if FDCAN2_NBRP > FDCAN_NBTP_NBRP_MAX +# error Invalid FDCAN1 NBRP +# endif + +# ifdef CONFIG_STM32_FDCAN2_FD_BRS +# define FDCAN2_DTSEG1 (CONFIG_STM32_FDCAN2_DTSEG1 - 1) +# define FDCAN2_DTSEG2 (CONFIG_STM32_FDCAN2_DTSEG2 - 1) +# define FDCAN2_DBRP (((STM32_FDCANCLK_FREQUENCY / \ + ((FDCAN2_DTSEG1 + FDCAN2_DTSEG2 + 3) * \ + CONFIG_STM32_FDCAN2_DBITRATE)) - 1)) +# define FDCAN2_DSJW (CONFIG_STM32_FDCAN2_DSJW - 1) +# else +# define FDCAN2_DTSEG1 1 +# define FDCAN2_DTSEG2 1 +# define FDCAN2_DBRP 1 +# define FDCAN2_DSJW 1 +# endif /* CONFIG_STM32_FDCAN2_FD_BRS */ + +# if FDCAN2_DTSEG1 > FDCAN_DBTP_DTSEG1_MAX +# error Invalid FDCAN2 DTSEG1 +# endif +# if FDCAN2_DTSEG2 > FDCAN_DBTP_DTSEG2_MAX +# error Invalid FDCAN2 DTSEG2 +# endif +# if FDCAN2_DBRP > FDCAN_DBTP_DBRP_MAX +# error Invalid FDCAN2 DBRP +# endif +# if FDCAN2_DSJW > FDCAN_DBTP_DSJW_MAX +# error Invalid FDCAN2 DSJW +# endif + +/* FDCAN2 Message RAM Configuration *****************************************/ + +/* FDCAN2 Message RAM Layout */ + +# define FDCAN2_STDFILTER_INDEX 0 +# define FDCAN2_EXTFILTERS_INDEX (FDCAN2_STDFILTER_INDEX + FDCAN2_STDFILTER_WORDS) +# define FDCAN2_RXFIFO0_INDEX (FDCAN2_EXTFILTERS_INDEX + FDCAN2_EXTFILTER_WORDS) +# define FDCAN2_RXFIFO1_INDEX (FDCAN2_RXFIFO0_INDEX + FDCAN2_RXFIFO0_WORDS) +# define FDCAN2_TXEVENTFIFO_INDEX (FDCAN2_RXFIFO1_INDEX + FDCAN2_RXFIFO1_WORDS) +# define FDCAN2_TXFIFOQ_INDEX (FDCAN2_TXEVENTFIFO_INDEX + FDCAN2_TXEVENTFIFO_WORDS) +# define FDCAN2_MSGRAM_WORDS (FDCAN2_TXFIFOQ_INDEX + FDCAN2_TXFIFIOQ_WORDS) + +#endif /* CONFIG_STM32_FDCAN2 */ + +/* FDCAN3 Configuration *****************************************************/ + +#ifdef CONFIG_STM32_FDCAN3 + +/* Bit timing */ + +# define FDCAN3_NTSEG1 (CONFIG_STM32_FDCAN3_NTSEG1 - 1) +# define FDCAN3_NTSEG2 (CONFIG_STM32_FDCAN3_NTSEG2 - 1) +# define FDCAN3_NBRP (((STM32_FDCANCLK_FREQUENCY / \ + ((FDCAN3_NTSEG1 + FDCAN3_NTSEG2 + 3) * \ + CONFIG_STM32_FDCAN3_BITRATE)) - 1)) +# define FDCAN3_NSJW (CONFIG_STM32_FDCAN3_NSJW - 1) + +# if FDCAN3_NTSEG1 > FDCAN_NBTP_NTSEG1_MAX +# error Invalid FDCAN3 NTSEG1 +# endif +# if FDCAN3_NTSEG2 > FDCAN_NBTP_NTSEG2_MAX +# error Invalid FDCAN3 NTSEG2 +# endif +# if FDCAN3_NSJW > FDCAN_NBTP_NSJW_MAX +# error Invalid FDCAN3 NSJW +# endif +# if FDCAN3_NBRP > FDCAN_NBTP_NBRP_MAX +# error Invalid FDCAN1 NBRP +# endif + +# ifdef CONFIG_STM32_FDCAN3_FD_BRS +# define FDCAN3_DTSEG1 (CONFIG_STM32_FDCAN3_DTSEG1 - 1) +# define FDCAN3_DTSEG2 (CONFIG_STM32_FDCAN3_DTSEG2 - 1) +# define FDCAN3_DBRP (((STM32_FDCANCLK_FREQUENCY / \ + ((FDCAN3_DTSEG1 + FDCAN3_DTSEG2 + 3) * \ + CONFIG_STM32_FDCAN3_DBITRATE)) - 1)) +# define FDCAN3_DSJW (CONFIG_STM32_FDCAN3_DSJW - 1) +# else +# define FDCAN3_DTSEG1 1 +# define FDCAN3_DTSEG2 1 +# define FDCAN3_DBRP 1 +# define FDCAN3_DSJW 1 +# endif /* CONFIG_STM32_FDCAN3_FD_BRS */ + +# if FDCAN3_DTSEG1 > FDCAN_DBTP_DTSEG1_MAX +# error Invalid FDCAN3 DTSEG1 +# endif +# if FDCAN3_DTSEG2 > FDCAN_DBTP_DTSEG2_MAX +# error Invalid FDCAN3 DTSEG2 +# endif +# if FDCAN3_DBRP > FDCAN_DBTP_DBRP_MAX +# error Invalid FDCAN3 DBRP +# endif +# if FDCAN3_DSJW > FDCAN_DBTP_DSJW_MAX +# error Invalid FDCAN3 DSJW +# endif + +/* FDCAN3 Message RAM Configuration *****************************************/ + +/* FDCAN3 Message RAM Layout */ + +# define FDCAN3_STDFILTER_INDEX 0 +# define FDCAN3_EXTFILTERS_INDEX (FDCAN3_STDFILTER_INDEX + FDCAN3_STDFILTER_WORDS) +# define FDCAN3_RXFIFO0_INDEX (FDCAN3_EXTFILTERS_INDEX + FDCAN3_EXTFILTER_WORDS) +# define FDCAN3_RXFIFO1_INDEX (FDCAN3_RXFIFO0_INDEX + FDCAN3_RXFIFO0_WORDS) +# define FDCAN3_TXEVENTFIFO_INDEX (FDCAN3_RXFIFO1_INDEX + FDCAN3_RXFIFO1_WORDS) +# define FDCAN3_TXFIFOQ_INDEX (FDCAN3_TXEVENTFIFO_INDEX + FDCAN3_TXEVENTFIFO_WORDS) +# define FDCAN3_MSGRAM_WORDS (FDCAN3_TXFIFOQ_INDEX + FDCAN3_TXFIFIOQ_WORDS) + +#endif /* CONFIG_STM32_FDCAN3 */ + +/* Loopback mode */ + +#undef STM32_FDCAN_LOOPBACK +#if defined(CONFIG_STM32_FDCAN1_LOOPBACK) || \ + defined(CONFIG_STM32_FDCAN2_LOOPBACK) || \ + defined(CONFIG_STM32_FDCAN3_LOOPBACK) +# define STM32_FDCAN_LOOPBACK 1 +#endif + +/* Interrupts ***************************************************************/ + +/* Common interrupts + * + * FDCAN_INT_TSW - Timestamp Wraparound + * FDCAN_INT_MRAF - Message RAM Access Failure + * FDCAN_INT_TOO - Timeout Occurred + * FDCAN_INT_ELO - Error Logging Overflow + * FDCAN_INT_EP - Error Passive + * FDCAN_INT_EW - Warning Status + * FDCAN_INT_BO - Bus_Off Status + * FDCAN_INT_WDI - Watchdog Interrupt + * FDCAN_INT_PEA - Protocol Error in Arbritration Phase + * FDCAN_INT_PED - Protocol Error in Data Phase + */ + +#define FDCAN_CMNERR_INTS (FDCAN_INT_MRAF | FDCAN_INT_TOO | FDCAN_INT_EP | \ + FDCAN_INT_BO | FDCAN_INT_WDI | FDCAN_INT_PEA | \ + FDCAN_INT_PED) + +/* RXFIFO mode interrupts + * + * FDCAN_INT_RF0N - Receive FIFO 0 New Message + * FDCAN_INT_RF0F - Receive FIFO 0 Full + * FDCAN_INT_RF0L - Receive FIFO 0 Message Lost + * FDCAN_INT_RF1N - Receive FIFO 1 New Message + * FDCAN_INT_RF1F - Receive FIFO 1 Full + * FDCAN_INT_RF1L - Receive FIFO 1 Message Lost + * FDCAN_INT_HPM - High Priority Message Received + * + */ + +#define FDCAN_RXFIFO0_INTS (FDCAN_INT_RF0N | FDCAN_INT_RF0L) +#define FDCAN_RXFIFO1_INTS (FDCAN_INT_RF1N | FDCAN_INT_RF1L) + +#define FDCAN_RXERR_INTS (FDCAN_INT_RF0L | FDCAN_INT_RF1L) + +/* TX FIFOQ mode interrupts + * + * FDCAN_INT_TFE - Tx FIFO Empty + * + * TX Event FIFO interrupts + * + * FDCAN_INT_TEFN - Tx Event FIFO New Entry + * FDCAN_INT_TEFF - Tx Event FIFO Full + * FDCAN_INT_TEFL - Tx Event FIFO Element Lost + * + * Mode-independent TX-related interrupts + * + * FDCAN_INT_TC - Transmission Completed + * FDCAN_INT_TCF - Transmission Cancellation Finished + */ + +#define FDCAN_TXCOMMON_INTS (FDCAN_INT_TC | FDCAN_INT_TCF) +#define FDCAN_TXFIFOQ_INTS (FDCAN_INT_TFE | FDCAN_TXCOMMON_INTS) +#define FDCAN_TXEVFIFO_INTS (FDCAN_INT_TEFN | FDCAN_INT_TEFF | \ + FDCAN_INT_TEFL) + +#define FDCAN_TXERR_INTS (FDCAN_INT_TEFL | FDCAN_INT_PEA | FDCAN_INT_PED) + +/* Common-, TX- and RX-Error-Mask */ + +#define FDCAN_ANYERR_INTS (FDCAN_CMNERR_INTS | FDCAN_RXERR_INTS | FDCAN_TXERR_INTS) + +/* Convenience macro for clearing all interrupts */ + +#define FDCAN_INT_ALL 0x3fcfffff + +/* Debug ********************************************************************/ + +/* Debug configurations that may be enabled just for testing FDCAN */ + +#ifndef CONFIG_DEBUG_NET_INFO +# undef CONFIG_STM32_FDCAN_REGDEBUG +#endif + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/* CAN frame format */ + +enum stm32_frameformat_e +{ + FDCAN_ISO11898_1_FORMAT = 0, /* Frame format according to ISO11898-1 */ + FDCAN_NONISO_BOSCH_V1_FORMAT = 1 /* Frame format according to Bosch CAN FD V1.0 */ +}; + +/* CAN mode of operation */ + +enum stm32_canmode_e +{ + FDCAN_CLASSIC_MODE = 0, /* Classic CAN operation */ +#ifdef CONFIG_NET_CAN_CANFD + FDCAN_FD_MODE = 1, /* CAN FD operation */ + FDCAN_FD_BRS_MODE = 2 /* CAN FD operation with bit rate switching */ +#endif +}; + +/* CAN driver state */ + +enum can_state_s +{ + FDCAN_STATE_UNINIT = 0, /* Not yet initialized */ + FDCAN_STATE_RESET, /* Initialized, reset state */ + FDCAN_STATE_SETUP, /* fdcan_setup() has been called */ + FDCAN_STATE_DISABLED /* Disabled by a fdcan_shutdown() */ +}; + +/* This structure describes the FDCAN message RAM layout */ + +struct stm32_msgram_s +{ + volatile uint32_t *stdfilters; /* Standard filters */ + volatile uint32_t *extfilters; /* Extended filters */ + volatile uint32_t *rxfifo0; /* RX FIFO0 */ + volatile uint32_t *rxfifo1; /* RX FIFO1 */ + volatile uint32_t *txeventfifo; /* TX event FIFO */ + volatile uint32_t *txfifoq; /* TX FIFO queue */ +}; + +/* This structure provides the constant configuration of a FDCAN peripheral */ + +struct stm32_config_s +{ + uint32_t rxpinset; /* RX pin configuration */ + uint32_t txpinset; /* TX pin configuration */ + uintptr_t base; /* Base address of the FDCAN registers */ + uint32_t baud; /* Configured baud */ + uint32_t nbtp; /* Nominal bit timing/prescaler register setting */ + uint32_t dbtp; /* Data bit timing/prescaler register setting */ + uint8_t port; /* FDCAN port number (1 or 2) */ + uint8_t irq0; /* FDCAN peripheral IRQ number for interrupt line 0 */ + uint8_t irq1; /* FDCAN peripheral IRQ number for interrupt line 1 */ + uint8_t mode; /* See enum stm32_canmode_e */ + uint8_t format; /* See enum stm32_frameformat_e */ + uint8_t nstdfilters; /* Number of standard filters */ + uint8_t nextfilters; /* Number of extended filters */ + uint8_t nrxfifo0; /* Number of RX FIFO0 elements */ + uint8_t nrxfifo1; /* Number of RX FIFO1 elements */ + uint8_t ntxeventfifo; /* Number of TXevent FIFO elements */ + uint8_t ntxfifoq; /* Number of TX FIFO queue elements */ + uint8_t rxfifo0esize; /* RX FIFO0 element size (words) */ + uint8_t rxfifo1esize; /* RX FIFO1 element size (words) */ + uint8_t txeventesize; /* TXevent element size (words) */ + uint8_t txbufferesize; /* TX buffer element size (words) */ +#ifdef STM32_FDCAN_LOOPBACK + bool loopback; /* True: Loopback mode */ +#endif + + /* FDCAN message RAM layout */ + + struct stm32_msgram_s msgram; +}; + +/* This structure provides the current state of a FDCAN peripheral */ + +struct stm32_fdcan_s +{ + /* The constant configuration */ + + const struct stm32_config_s *config; + + uint8_t state; /* See enum can_state_s */ +#ifdef CONFIG_NET_CAN_EXTID + uint8_t nextalloc; /* Number of allocated extended filters */ +#endif + uint8_t nstdalloc; /* Number of allocated standard filters */ + uint32_t nbtp; /* Current nominal bit timing */ + uint32_t dbtp; /* Current data bit timing */ + +#ifdef CONFIG_NET_CAN_EXTID + uint32_t extfilters[2]; /* Extended filter bit allocator. 2*32=64 */ +#endif + uint32_t stdfilters[4]; /* Standard filter bit allocator. 4*32=128 */ + +#ifdef CONFIG_STM32_FDCAN_REGDEBUG + uintptr_t regaddr; /* Last register address read */ + uint32_t regval; /* Last value read from the register */ + unsigned int count; /* Number of times that the value was read */ +#endif + + bool bifup; /* true:ifup false:ifdown */ + struct net_driver_s dev; /* Interface understood by the network */ + + struct work_s irqwork; /* For deferring interrupt work to the wq */ + struct work_s pollwork; /* For deferring poll work to the work wq */ + + /* A pointers to the list of TX/RX descriptors */ + + struct can_frame *txdesc; + struct can_frame *rxdesc; + + /* TX/RX pool */ + +#ifdef CONFIG_NET_CAN_CANFD + uint8_t tx_pool[sizeof(struct canfd_frame)*POOL_SIZE]; + uint8_t rx_pool[sizeof(struct canfd_frame)*POOL_SIZE]; +#else + uint8_t tx_pool[sizeof(struct can_frame)*POOL_SIZE]; + uint8_t rx_pool[sizeof(struct can_frame)*POOL_SIZE]; +#endif +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/* FDCAN Register access */ + +static uint32_t fdcan_getreg(struct stm32_fdcan_s *priv, int offset); +static void fdcan_putreg(struct stm32_fdcan_s *priv, int offset, + uint32_t regval); +#ifdef CONFIG_STM32_FDCAN_REGDEBUG +static void fdcan_dumpregs(struct stm32_fdcan_s *priv, + const char *msg); +static void fdcan_dumprxregs(struct stm32_fdcan_s *priv, + const char *msg); +static void fdcan_dumptxregs(struct stm32_fdcan_s *priv, + const char *msg); +static void fdcan_dumpramlayout(struct stm32_fdcan_s *priv); +#else +# define fdcan_dumpregs(priv,msg) +# define fdcan_dumprxregs(priv,msg) +# define fdcan_dumptxregs(priv,msg) +# define fdcan_dumpramlayout(priv) +#endif + +/* CAN interrupt enable functions */ + +static void fdcan_rx0int(struct stm32_fdcan_s *priv, bool enable); +static void fdcan_rx1int(struct stm32_fdcan_s *priv, bool enable); +static void fdcan_txint(struct stm32_fdcan_s *priv, bool enable); +#ifdef CONFIG_NET_CAN_ERRORS +static void fdcan_errint(struct stm32_fdcan_s *priv, bool enable); +#endif + +/* Common TX logic */ + +static int fdcan_send(struct stm32_fdcan_s *priv); +static bool fdcan_txready(struct stm32_fdcan_s *priv); +static int fdcan_txpoll(struct net_driver_s *dev); + +/* CAN RX interrupt handling */ + +static void fdcan_rx0interrupt_work(void *arg); +static void fdcan_rx1interrupt_work(void *arg); + +/* CAN TX interrupt handling */ + +static void fdcan_txdone_work(void *arg); +static void fdcan_txdone(struct stm32_fdcan_s *priv); + +#ifdef CONFIG_NET_CAN_ERRORS +/* CAN errors interrupt handling */ + +static void fdcan_error_work(void *arg); +#endif + +/* FDCAN interrupt handling */ + +#ifdef CONFIG_NET_CAN_ERRORS +static void fdcan_error(struct stm32_fdcan_s *priv, uint32_t status); +#endif +static void fdcan_receive(struct stm32_fdcan_s *priv, + volatile uint32_t *rxbuffer, + unsigned long nwords); +static int fdcan_interrupt(int irq, void *context, void *arg); + +/* Initialization */ + +static void fdcan_reset(struct stm32_fdcan_s *priv); +static int fdcan_setup(struct stm32_fdcan_s *priv); +static void fdcan_shutdown(struct stm32_fdcan_s *priv); + +/* FDCAN helpers */ + +#if 0 /* not used for now */ +static int +fdcan_start_busoff_recovery_sequence(struct stm32_fdcan_s *priv); +#endif + +/* Hardware initialization */ + +static int fdcan_hw_initialize(struct stm32_fdcan_s *priv); + +/* NuttX callback functions */ + +static int fdcan_ifup(struct net_driver_s *dev); +static int fdcan_ifdown(struct net_driver_s *dev); + +static void fdcan_txavail_work(void *arg); +static int fdcan_txavail(struct net_driver_s *dev); + +#ifdef CONFIG_NETDEV_IOCTL +static int fdcan_netdev_ioctl(struct net_driver_s *dev, int cmd, + unsigned long arg); +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#ifdef CONFIG_STM32_FDCAN1 +/* Message RAM allocation */ + +/* Constant configuration */ + +static const struct stm32_config_s g_fdcan1const = +{ + .rxpinset = GPIO_FDCAN1_RX, + .txpinset = GPIO_FDCAN1_TX, + .base = STM32_FDCAN1_BASE, + .baud = CONFIG_STM32_FDCAN1_BITRATE, + .nbtp = FDCAN_NBTP_NBRP(FDCAN1_NBRP) | + FDCAN_NBTP_NTSEG1(FDCAN1_NTSEG1) | + FDCAN_NBTP_NTSEG2(FDCAN1_NTSEG2) | + FDCAN_NBTP_NSJW(FDCAN1_NSJW), + .dbtp = FDCAN_DBTP_DBRP(FDCAN1_DBRP) | + FDCAN_DBTP_DTSEG1(FDCAN1_DTSEG1) | + FDCAN_DBTP_DTSEG2(FDCAN1_DTSEG2) | + FDCAN_DBTP_DSJW(FDCAN1_DSJW), + .port = 1, + .irq0 = STM32_IRQ_FDCAN1_0, + .irq1 = STM32_IRQ_FDCAN1_1, +#if defined(CONFIG_STM32_FDCAN1_CLASSIC) + .mode = FDCAN_CLASSIC_MODE, +#elif defined(CONFIG_STM32_FDCAN1_FD) + .mode = FDCAN_FD_MODE, +#else + .mode = FDCAN_FD_BRS_MODE, +#endif +#if defined(CONFIG_STM32_FDCAN1_NONISO_FORMAT) + .format = FDCAN_NONISO_BOSCH_V1_FORMAT, +#else + .format = FDCAN_ISO11898_1_FORMAT, +#endif + .nstdfilters = FDCAN1_STDFILTER_SIZE, + .nextfilters = FDCAN1_EXTFILTER_SIZE, + .nrxfifo0 = FDCAN1_RXFIFO0_SIZE, + .nrxfifo1 = FDCAN1_RXFIFO1_SIZE, + .ntxeventfifo = FDCAN1_TXEVENTFIFO_SIZE, + .ntxfifoq = FDCAN1_TXFIFIOQ_SIZE, + .rxfifo0esize = (FDCAN1_RXFIFO0_WORDS / FDCAN1_RXFIFO0_SIZE), + .rxfifo1esize = (FDCAN1_RXFIFO1_WORDS / FDCAN1_RXFIFO1_SIZE), + .txeventesize = (FDCAN1_TXEVENTFIFO_WORDS / FDCAN1_TXEVENTFIFO_SIZE), + .txbufferesize = (FDCAN1_TXFIFIOQ_WORDS / FDCAN1_TXFIFIOQ_SIZE), + +#ifdef CONFIG_STM32_FDCAN1_LOOPBACK + .loopback = true, +#endif + + /* FDCAN1 Message RAM */ + + .msgram = + { + (uint32_t *)(STM32_CANRAM1_BASE + (FDCAN1_STDFILTER_INDEX << 2)), + (uint32_t *)(STM32_CANRAM1_BASE + (FDCAN1_EXTFILTERS_INDEX << 2)), + (uint32_t *)(STM32_CANRAM1_BASE + (FDCAN1_RXFIFO0_INDEX << 2)), + (uint32_t *)(STM32_CANRAM1_BASE + (FDCAN1_RXFIFO1_INDEX << 2)), + (uint32_t *)(STM32_CANRAM1_BASE + (FDCAN1_TXEVENTFIFO_INDEX << 2)), + (uint32_t *)(STM32_CANRAM1_BASE + (FDCAN1_TXFIFOQ_INDEX << 2)) + } +}; + +/* FDCAN1 variable driver state */ + +static struct stm32_fdcan_s g_fdcan1priv; + +#endif /* CONFIG_STM32_FDCAN1 */ + +#ifdef CONFIG_STM32_FDCAN2 +/* FDCAN2 message RAM allocation */ + +/* FDCAN2 constant configuration */ + +static const struct stm32_config_s g_fdcan2const = +{ + .rxpinset = GPIO_FDCAN2_RX, + .txpinset = GPIO_FDCAN2_TX, + .base = STM32_FDCAN2_BASE, + .baud = CONFIG_STM32_FDCAN2_BITRATE, + .nbtp = FDCAN_NBTP_NBRP(FDCAN2_NBRP) | + FDCAN_NBTP_NTSEG1(FDCAN2_NTSEG1) | + FDCAN_NBTP_NTSEG2(FDCAN2_NTSEG2) | + FDCAN_NBTP_NSJW(FDCAN2_NSJW), + .dbtp = FDCAN_DBTP_DBRP(FDCAN2_DBRP) | + FDCAN_DBTP_DTSEG1(FDCAN2_DTSEG1) | + FDCAN_DBTP_DTSEG2(FDCAN2_DTSEG2) | + FDCAN_DBTP_DSJW(FDCAN2_DSJW), + .port = 2, + .irq0 = STM32_IRQ_FDCAN2_0, + .irq1 = STM32_IRQ_FDCAN2_1, +#if defined(CONFIG_STM32_FDCAN2_CLASSIC) + .mode = FDCAN_CLASSIC_MODE, +#elif defined(CONFIG_STM32_FDCAN2_FD) + .mode = FDCAN_FD_MODE, +#else + .mode = FDCAN_FD_BRS_MODE, +#endif +#if defined(CONFIG_STM32_FDCAN2_NONISO_FORMAT) + .format = FDCAN_NONISO_BOSCH_V1_FORMAT, +#else + .format = FDCAN_ISO11898_1_FORMAT, +#endif + .nstdfilters = FDCAN2_STDFILTER_SIZE, + .nextfilters = FDCAN2_EXTFILTER_SIZE, + .nrxfifo0 = FDCAN2_RXFIFO0_SIZE, + .nrxfifo1 = FDCAN2_RXFIFO1_SIZE, + .ntxeventfifo = FDCAN2_TXEVENTFIFO_SIZE, + .ntxfifoq = FDCAN2_TXFIFIOQ_SIZE, + .rxfifo0esize = (FDCAN2_RXFIFO0_WORDS / FDCAN2_RXFIFO0_SIZE), + .rxfifo1esize = (FDCAN2_RXFIFO1_WORDS / FDCAN2_RXFIFO1_SIZE), + .txeventesize = (FDCAN2_TXEVENTFIFO_WORDS / FDCAN2_TXEVENTFIFO_SIZE), + .txbufferesize = (FDCAN2_TXFIFIOQ_WORDS / FDCAN2_TXFIFIOQ_SIZE), + +#ifdef CONFIG_STM32_FDCAN2_LOOPBACK + .loopback = true, +#endif + + /* FDCAN2 Message RAM */ + + .msgram = + { + (uint32_t *)(STM32_CANRAM2_BASE + (FDCAN2_STDFILTER_INDEX << 2)), + (uint32_t *)(STM32_CANRAM2_BASE + (FDCAN2_EXTFILTERS_INDEX << 2)), + (uint32_t *)(STM32_CANRAM2_BASE + (FDCAN2_RXFIFO0_INDEX << 2)), + (uint32_t *)(STM32_CANRAM2_BASE + (FDCAN2_RXFIFO1_INDEX << 2)), + (uint32_t *)(STM32_CANRAM2_BASE + (FDCAN2_TXEVENTFIFO_INDEX << 2)), + (uint32_t *)(STM32_CANRAM2_BASE + (FDCAN2_TXFIFOQ_INDEX << 2)) + } +}; + +/* FDCAN2 variable driver state */ + +static struct stm32_fdcan_s g_fdcan2priv; + +#endif /* CONFIG_STM32_FDCAN2 */ + +#ifdef CONFIG_STM32_FDCAN3 +/* FDCAN3 message RAM allocation */ + +/* FDCAN3 constant configuration */ + +static const struct stm32_config_s g_fdcan3const = +{ + .rxpinset = GPIO_FDCAN3_RX, + .txpinset = GPIO_FDCAN3_TX, + .base = STM32_FDCAN3_BASE, + .baud = CONFIG_STM32_FDCAN3_BITRATE, + .nbtp = FDCAN_NBTP_NBRP(FDCAN3_NBRP) | + FDCAN_NBTP_NTSEG1(FDCAN3_NTSEG1) | + FDCAN_NBTP_NTSEG2(FDCAN3_NTSEG2) | + FDCAN_NBTP_NSJW(FDCAN3_NSJW), + .dbtp = FDCAN_DBTP_DBRP(FDCAN3_DBRP) | + FDCAN_DBTP_DTSEG1(FDCAN3_DTSEG1) | + FDCAN_DBTP_DTSEG2(FDCAN3_DTSEG2) | + FDCAN_DBTP_DSJW(FDCAN3_DSJW), + .port = 3, + .irq0 = STM32_IRQ_FDCAN3_0, + .irq1 = STM32_IRQ_FDCAN3_1, +#if defined(CONFIG_STM32_FDCAN3_CLASSIC) + .mode = FDCAN_CLASSIC_MODE, +#elif defined(CONFIG_STM32_FDCAN3_FD) + .mode = FDCAN_FD_MODE, +#else + .mode = FDCAN_FD_BRS_MODE, +#endif +#if defined(CONFIG_STM32_FDCAN3_NONISO_FORMAT) + .format = FDCAN_NONISO_BOSCH_V1_FORMAT, +#else + .format = FDCAN_ISO11898_1_FORMAT, +#endif + .nstdfilters = FDCAN3_STDFILTER_SIZE, + .nextfilters = FDCAN3_EXTFILTER_SIZE, + .nrxfifo0 = FDCAN3_RXFIFO0_SIZE, + .nrxfifo1 = FDCAN3_RXFIFO1_SIZE, + .ntxeventfifo = FDCAN3_TXEVENTFIFO_SIZE, + .ntxfifoq = FDCAN3_TXFIFIOQ_SIZE, + .rxfifo0esize = (FDCAN3_RXFIFO0_WORDS / FDCAN3_RXFIFO0_SIZE), + .rxfifo1esize = (FDCAN3_RXFIFO1_WORDS / FDCAN3_RXFIFO1_SIZE), + .txeventesize = (FDCAN3_TXEVENTFIFO_WORDS / FDCAN3_TXEVENTFIFO_SIZE), + .txbufferesize = (FDCAN3_TXFIFIOQ_WORDS / FDCAN3_TXFIFIOQ_SIZE), + +#ifdef CONFIG_STM32_FDCAN3_LOOPBACK + .loopback = true, +#endif + + /* FDCAN3 Message RAM */ + + .msgram = + { + (uint32_t *)(STM32_CANRAM3_BASE + (FDCAN3_STDFILTER_INDEX << 2)), + (uint32_t *)(STM32_CANRAM3_BASE + (FDCAN3_EXTFILTERS_INDEX << 2)), + (uint32_t *)(STM32_CANRAM3_BASE + (FDCAN3_RXFIFO0_INDEX << 2)), + (uint32_t *)(STM32_CANRAM3_BASE + (FDCAN3_RXFIFO1_INDEX << 2)), + (uint32_t *)(STM32_CANRAM3_BASE + (FDCAN3_TXEVENTFIFO_INDEX << 2)), + (uint32_t *)(STM32_CANRAM3_BASE + (FDCAN3_TXFIFOQ_INDEX << 2)) + } +}; + +/* FDCAN3 variable driver state */ + +static struct stm32_fdcan_s g_fdcan3priv; + +#endif /* CONFIG_STM32_FDCAN3 */ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: fdcan_getreg + * + * Description: + * Read the value of a FDCAN register. + * + * Input Parameters: + * priv - A reference to the FDCAN peripheral state + * offset - The offset to the register to read + * + * Returned Value: + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_FDCAN_REGDEBUG +static uint32_t fdcan_getreg(struct stm32_fdcan_s *priv, int offset) +{ + const struct stm32_config_s *config = priv->config; + uintptr_t regaddr = 0; + uint32_t regval = 0; + + /* Read the value from the register */ + + regaddr = config->base + offset; + regval = getreg32(regaddr); + + /* Is this the same value that we read from the same register last time? + * Are we polling the register? If so, suppress some of the output. + */ + + if (regaddr == priv->regaddr && regval == priv->regval) + { + if (priv->count == 0xffffffff || ++priv->count > 3) + { + if (priv->count == 4) + { + ninfo("...\n"); + } + + return regval; + } + } + + /* No this is a new address or value */ + + else + { + /* Did we print "..." for the previous value? */ + + if (priv->count > 3) + { + /* Yes.. then show how many times the value repeated */ + + ninfo("[repeats %d more times]\n", priv->count - 3); + } + + /* Save the new address, value, and count */ + + priv->regaddr = regaddr; + priv->regval = regval; + priv->count = 1; + } + + /* Show the register value read */ + + ninfo("%08" PRIx32 "->%08" PRIx32 "\n", regaddr, regval); + return regval; +} + +#else +static uint32_t fdcan_getreg(struct stm32_fdcan_s *priv, int offset) +{ + const struct stm32_config_s *config = priv->config; + return getreg32(config->base + offset); +} + +#endif + +/**************************************************************************** + * Name: fdcan_putreg + * + * Description: + * Set the value of a FDCAN register. + * + * Input Parameters: + * priv - A reference to the FDCAN peripheral state + * offset - The offset to the register to write + * regval - The value to write to the register + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_FDCAN_REGDEBUG +static void fdcan_putreg(struct stm32_fdcan_s *priv, int offset, + uint32_t regval) +{ + const struct stm32_config_s *config = priv->config; + uintptr_t regaddr = config->base + offset; + + /* Show the register value being written */ + + ninfo("%08" PRIx32 "->%08" PRIx32 "\n", regaddr, regval); + + /* Write the value */ + + putreg32(regval, regaddr); +} + +#else +static void fdcan_putreg(struct stm32_fdcan_s *priv, int offset, + uint32_t regval) +{ + const struct stm32_config_s *config = priv->config; + putreg32(regval, config->base + offset); +} + +#endif + +/**************************************************************************** + * Name: fdcan_dumpctrlregs + * + * Description: + * Dump the contents of all CAN control registers + * + * Input Parameters: + * priv - A reference to the CAN block status + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_FDCAN_REGDEBUG +static void fdcan_dumpregs(struct stm32_fdcan_s *priv, + const char *msg) +{ + const struct stm32_config_s *config = priv->config; + + ninfo("CAN%d Control and Status Registers: %s\n", config->port, msg); + ninfo(" Base: %08" PRIx32 "\n", config->base); + + /* CAN control and status registers */ + + ninfo(" CCCR: %08" PRIx32 " TEST: %08" PRIx32 "\n", + getreg32(config->base + STM32_FDCAN_CCCR_OFFSET), + getreg32(config->base + STM32_FDCAN_TEST_OFFSET)); + + ninfo(" NBTP: %08" PRIx32 " DBTP: %08" PRIx32 "\n", + getreg32(config->base + STM32_FDCAN_NBTP_OFFSET), + getreg32(config->base + STM32_FDCAN_DBTP_OFFSET)); + + ninfo(" IE: %08" PRIx32 " TIE: %08" PRIx32 "\n", + getreg32(config->base + STM32_FDCAN_IE_OFFSET), + getreg32(config->base + STM32_FDCAN_TXBTIE_OFFSET)); + + ninfo(" ILE: %08" PRIx32 " ILS: %08" PRIx32 "\n", + getreg32(config->base + STM32_FDCAN_ILE_OFFSET), + getreg32(config->base + STM32_FDCAN_ILS_OFFSET)); + + ninfo(" TXBC: %08" PRIx32 "\n", + getreg32(config->base + STM32_FDCAN_TXBC_OFFSET)); +} +#endif + +/**************************************************************************** + * Name: fdcan_dumprxregs + * + * Description: + * Dump the contents of all Rx status registers + * + * Input Parameters: + * priv - A reference to the CAN block status + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_FDCAN_REGDEBUG +static void fdcan_dumprxregs(struct stm32_fdcan_s *priv, + const char *msg) +{ + const struct stm32_config_s *config = priv->config; + + ninfo("CAN%d Rx Registers: %s\n", config->port, msg); + ninfo(" Base: %08" PRIx32 "\n", config->base); + + ninfo(" PSR: %08" PRIx32 " ECR: %08" PRIx32 + " HPMS: %08" PRIx32 "\n", + getreg32(config->base + STM32_FDCAN_PSR_OFFSET), + getreg32(config->base + STM32_FDCAN_ECR_OFFSET), + getreg32(config->base + STM32_FDCAN_HPMS_OFFSET)); + + ninfo(" RXF0S: %08" PRIx32 " RXF0A: %08" PRIx32 "\n", + getreg32(config->base + STM32_FDCAN_RXF0S_OFFSET), + getreg32(config->base + STM32_FDCAN_RXF0A_OFFSET)); + + ninfo(" RXF1S: %08" PRIx32 " RXF1A: %08" PRIx32 "\n", + getreg32(config->base + STM32_FDCAN_RXF1S_OFFSET), + getreg32(config->base + STM32_FDCAN_RXF1A_OFFSET)); + + ninfo(" IR: %08" PRIx32 " IE: %08" PRIx32 "\n", + getreg32(config->base + STM32_FDCAN_IR_OFFSET), + getreg32(config->base + STM32_FDCAN_IE_OFFSET)); +} +#endif + +/**************************************************************************** + * Name: fdcan_dumptxregs + * + * Description: + * Dump the contents of all Tx buffer registers + * + * Input Parameters: + * priv - A reference to the CAN block status + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_FDCAN_REGDEBUG +static void fdcan_dumptxregs(struct stm32_fdcan_s *priv, + const char *msg) +{ + const struct stm32_config_s *config = priv->config; + + ninfo("CAN%d Tx Registers: %s\n", config->port, msg); + ninfo(" Base: %08" PRIx32 "\n", config->base); + + ninfo(" PSR: %08" PRIx32 " ECR: %08" PRIx32 "\n", + getreg32(config->base + STM32_FDCAN_PSR_OFFSET), + getreg32(config->base + STM32_FDCAN_ECR_OFFSET)); + + ninfo(" TXQFS: %08" PRIx32 " TXBAR: %08" PRIx32 + " TXBRP: %08" PRIx32 "\n", + getreg32(config->base + STM32_FDCAN_TXFQS_OFFSET), + getreg32(config->base + STM32_FDCAN_TXBAR_OFFSET), + getreg32(config->base + STM32_FDCAN_TXBRP_OFFSET)); + + ninfo(" TXBTO: %08" PRIx32 " TXBCR: %08" PRIx32 "\n", + getreg32(config->base + STM32_FDCAN_TXBTO_OFFSET), + getreg32(config->base + STM32_FDCAN_TXBCR_OFFSET)); + + ninfo(" TXEFS: %08" PRIx32 " TXEFA: %08" PRIx32 "\n", + getreg32(config->base + STM32_FDCAN_TXEFS_OFFSET), + getreg32(config->base + STM32_FDCAN_TXEFA_OFFSET)); + + ninfo(" IR: %08" PRIx32 " IE: %08" PRIx32 + " TIE: %08" PRIx32 "\n", + getreg32(config->base + STM32_FDCAN_IR_OFFSET), + getreg32(config->base + STM32_FDCAN_IE_OFFSET), + getreg32(config->base + STM32_FDCAN_TXBTIE_OFFSET)); +} +#endif + +/**************************************************************************** + * Name: fdcan_dumpramlayout + * + * Description: + * Print the layout of the message RAM + * + * Input Parameters: + * priv - A reference to the CAN block status + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_FDCAN_REGDEBUG +static void fdcan_dumpramlayout(struct stm32_fdcan_s *priv) +{ + const struct stm32_config_s *config = priv->config; + + ninfo(" ******* FDCAN%d Message RAM layout *******\n", config->port); + ninfo(" Start # Elmnt Elmnt size (words)\n"); + + if (config->nstdfilters > 0) + { + ninfo("STD filters %p %4d %2d\n", + config->msgram.stdfilters, + config->nstdfilters, + 1); + } + + if (config->nextfilters > 0) + { + ninfo("EXT filters %p %4d %2d\n", + config->msgram.extfilters, + config->nextfilters, + 2); + } + + if (config->nrxfifo0 > 0) + { + ninfo("RX FIFO 0 %p %4d %2d\n", + config->msgram.rxfifo0, + config->nrxfifo0, + config->rxfifo0esize); + } + + if (config->nrxfifo1 > 0) + { + ninfo("RX FIFO 1 %p %4d %2d\n", + config->msgram.rxfifo1, + config->nrxfifo1, + config->rxfifo1esize); + } + + if (config->ntxeventfifo > 0) + { + ninfo("TX EVENT %p %4d %2d\n", + config->msgram.txeventfifo, + config->ntxeventfifo, + config->txeventesize); + } + + if (config->ntxfifoq > 0) + { + ninfo("TX FIFO %p %4d %2d\n", + config->msgram.txfifoq, + config->ntxfifoq, + config->txbufferesize); + } +} +#endif + +/**************************************************************************** + * Name: fdcan_start_busoff_recovery_sequence + * + * Description: + * This function initiates the BUS-OFF recovery sequence. + * CAN Specification Rev. 2.0 or ISO11898-1:2015. + * According the STM32G4 datasheet section 44.3.2 Software initialziation. + * + * Input Parameters: + * priv - An instance of the FDCAN driver state structure. + * + * Returned Value: + * Zero (OK) is returned on success. Otherwise a negated errno value is + * returned to indicate the nature of the error. + * + ****************************************************************************/ + +#if 0 /* not used for now */ +static int +fdcan_start_busoff_recovery_sequence(struct stm32_fdcan_s *priv) +{ + uint32_t regval = 0; + + DEBUGASSERT(priv); + + /* Only start BUS-OFF recovery if we are in BUS-OFF state */ + + regval = fdcan_getreg(priv, STM32_FDCAN_PSR_OFFSET); + if ((regval & FDCAN_PSR_BO) == 0) + { + return -EPERM; + } + + /* Disable initialization mode to issue the recovery sequence */ + + regval = fdcan_getreg(priv, STM32_FDCAN_CCCR_OFFSET); + regval &= ~FDCAN_CCCR_INIT; + fdcan_putreg(priv, STM32_FDCAN_CCCR_OFFSET, regval); + + return OK; +} +#endif + +/**************************************************************************** + * Name: fdcan_reset + * + * Description: + * Reset the FDCAN device. Called early to initialize the hardware. This + * function is called, before fdcan_setup() and on error conditions. + * + * Input Parameters: + * dev - An instance of the "upper half" can driver state structure. + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void fdcan_reset(struct stm32_fdcan_s *priv) +{ + const struct stm32_config_s *config = NULL; + uint32_t regval = 0; + irqstate_t flags; + + DEBUGASSERT(priv); + config = priv->config; + DEBUGASSERT(config); + + ninfo("FDCAN%d\n", config->port); + UNUSED(config); + + /* Disable all interrupts */ + + fdcan_putreg(priv, STM32_FDCAN_IE_OFFSET, 0); + fdcan_putreg(priv, STM32_FDCAN_TXBTIE_OFFSET, 0); + + /* Make sure that all buffers are released. + * + * REVISIT: What if a thread is waiting for a buffer? The following + * will not wake up any waiting threads. + */ + + /* Disable the FDCAN controller. + * REVISIT: Should fdcan_shutdown() be called here? + */ + + /* Reset the FD CAN. + * REVISIT: Since there is only a single reset for both FDCAN + * controllers, do we really want to use the RCC reset here? + * This will nuke operation of the second controller if another + * device is registered. + */ + + flags = enter_critical_section(); + regval = getreg32(STM32_RCC_APB1RSTR1); + regval |= RCC_APB1RSTR1_FDCANRST; + putreg32(regval, STM32_RCC_APB1RSTR1); + + regval &= ~RCC_APB1RSTR1_FDCANRST; + putreg32(regval, STM32_RCC_APB1RSTR1); + leave_critical_section(flags); + + priv->state = FDCAN_STATE_RESET; +} + +/**************************************************************************** + * Name: fdcan_setup + * + * Description: + * Configure the FDCAN. This method is called the first time that the FDCAN + * device is opened. This will occur when the port is first opened. + * This setup includes configuring and attaching FDCAN interrupts. + * All FDCAN interrupts are disabled upon return. + * + * Input Parameters: + * dev - An instance of the "upper half" can driver state structure. + * + * Returned Value: + * Zero on success; a negated errno on failure + * + ****************************************************************************/ + +static int fdcan_setup(struct stm32_fdcan_s *priv) +{ + const struct stm32_config_s *config = NULL; + int ret = 0; + + DEBUGASSERT(priv); + config = priv->config; + DEBUGASSERT(config); + + ninfo("FDCAN%d\n", config->port); + + /* FDCAN hardware initialization */ + + ret = fdcan_hw_initialize(priv); + if (ret < 0) + { + nerr("ERROR: FDCAN%d H/W initialization failed: %d\n", + config->port, ret); + return ret; + } + + fdcan_dumpregs(priv, "After hardware initialization"); + + /* Attach the FDCAN interrupt handlers */ + + ret = irq_attach(config->irq0, fdcan_interrupt, priv); + if (ret < 0) + { + nerr("ERROR: Failed to attach FDCAN%d line 0 IRQ (%d)", + config->port, config->irq0); + return ret; + } + + ret = irq_attach(config->irq1, fdcan_interrupt, priv); + if (ret < 0) + { + nerr("ERROR: Failed to attach FDCAN%d line 1 IRQ (%d)", + config->port, config->irq1); + return ret; + } + + priv->state = FDCAN_STATE_SETUP; + + /* Enable the interrupts at the NVIC (they are still disabled at the FDCAN + * peripheral). + */ + + up_enable_irq(config->irq0); + up_enable_irq(config->irq1); + + return OK; +} + +/**************************************************************************** + * Name: fdcan_shutdown + * + * Description: + * Disable the FDCAN. This method is called when the FDCAN device + * is closed. This method reverses the operation the setup method. + * + * Input Parameters: + * dev - An instance of the "upper half" can driver state structure. + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void fdcan_shutdown(struct stm32_fdcan_s *priv) +{ + const struct stm32_config_s *config = NULL; + uint32_t regval = 0; + + DEBUGASSERT(priv); + config = priv->config; + DEBUGASSERT(config); + + ninfo("FDCAN%d\n", config->port); + + /* Disable FDCAN interrupts at the NVIC */ + + up_disable_irq(config->irq0); + up_disable_irq(config->irq1); + + /* Disable all interrupts from the FDCAN peripheral */ + + fdcan_putreg(priv, STM32_FDCAN_IE_OFFSET, 0); + fdcan_putreg(priv, STM32_FDCAN_TXBTIE_OFFSET, 0); + + /* Detach the FDCAN interrupt handler */ + + irq_detach(config->irq0); + irq_detach(config->irq1); + + /* Disable device by setting the Clock Stop Request bit */ + + regval = fdcan_getreg(priv, STM32_FDCAN_CCCR_OFFSET); + regval |= FDCAN_CCCR_CSR; + fdcan_putreg(priv, STM32_FDCAN_CCCR_OFFSET, regval); + + /* Wait for Init and Clock Stop Acknowledge bits to verify + * device is in the powered down state + */ + + while ((fdcan_getreg(priv, STM32_FDCAN_CCCR_OFFSET) & FDCAN_CCCR_INIT) + == 0); + while ((fdcan_getreg(priv, STM32_FDCAN_CCCR_OFFSET) & FDCAN_CCCR_CSA) + == 0); + priv->state = FDCAN_STATE_DISABLED; +} + +/**************************************************************************** + * Name: fdcan_rx0int + * + * Description: + * Call to enable or disable RX0 interrupts. + * + * Input Parameters: + * priv - reference to the private CAN driver state structure + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void fdcan_rx0int(struct stm32_fdcan_s *priv, bool enable) +{ + const struct stm32_config_s *config = NULL; + uint32_t regval = 0; + + DEBUGASSERT(priv); + config = priv->config; + DEBUGASSERT(config); + + ninfo("CAN%" PRIu8 "RX0 enable: %d\n", config->port, enable); + + /* Enable/disable the FIFO 0 message pending interrupt */ + + regval = fdcan_getreg(priv, STM32_FDCAN_IE_OFFSET); + + if (enable) + { + regval |= FDCAN_RXFIFO0_INTS; + } + else + { + regval &= ~FDCAN_RXFIFO0_INTS; + } + + fdcan_putreg(priv, STM32_FDCAN_IE_OFFSET, regval); +} + +/**************************************************************************** + * Name: fdcan_rx1int + * + * Description: + * Call to enable or disable RX1 interrupts. + * + * Input Parameters: + * priv - reference to the private CAN driver state structure + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void fdcan_rx1int(struct stm32_fdcan_s *priv, bool enable) +{ + const struct stm32_config_s *config = NULL; + uint32_t regval = 0; + + DEBUGASSERT(priv); + config = priv->config; + DEBUGASSERT(config); + + ninfo("CAN%" PRIu8 "RX1 enable: %d\n", config->port, enable); + + /* Enable/disable the FIFO 1 message pending interrupt */ + + regval = fdcan_getreg(priv, STM32_FDCAN_IE_OFFSET); + + if (enable) + { + regval |= FDCAN_RXFIFO1_INTS; + } + else + { + regval &= ~FDCAN_RXFIFO1_INTS; + } + + fdcan_putreg(priv, STM32_FDCAN_IE_OFFSET, regval); +} + +/**************************************************************************** + * Name: fdcan_txint + * + * Description: + * Call to enable or disable TX interrupts. + * + * Input Parameters: + * dev - An instance of the "upper half" can driver state structure. + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void fdcan_txint(struct stm32_fdcan_s *priv, bool enable) +{ + const struct stm32_config_s *config = NULL; + uint32_t regval = 0; + + DEBUGASSERT(priv); + config = priv->config; + DEBUGASSERT(config); + + ninfo("CAN%" PRIu8 "TX enable: %d\n", config->port, enable); + + /* Enable/disable the receive interrupts */ + + regval = fdcan_getreg(priv, STM32_FDCAN_IE_OFFSET); + + if (enable) + { + regval |= FDCAN_TXFIFOQ_INTS; + } + else + { + regval &= ~FDCAN_TXFIFOQ_INTS; + } + + fdcan_putreg(priv, STM32_FDCAN_IE_OFFSET, regval); +} + +#ifdef CONFIG_NET_CAN_ERRORS +/**************************************************************************** + * Name: fdcan_txint + * + * Description: + * Call to enable or disable CAN SCE interrupts. + * + * Input Parameters: + * priv - reference to the private CAN driver state structure + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void fdcan_errint(struct stm32_fdcan_s *priv, bool enable) +{ + const struct stm32_config_s *config = NULL; + uint32_t regval = 0; + + DEBUGASSERT(priv); + config = priv->config; + DEBUGASSERT(config); + + ninfo("CAN%" PRIu8 "ERR enable: %d\n", config->port, enable); + + /* Enable/disable the transmit mailbox interrupt */ + + regval = fdcan_getreg(priv, STM32_FDCAN_IE_OFFSET); + if (enable) + { + regval |= FDCAN_ANYERR_INTS; + } + else + { + regval &= ~FDCAN_ANYERR_INTS; + } + + fdcan_putreg(priv, STM32_FDCAN_IE_OFFSET, regval); +} +#endif + +/**************************************************************************** + * Name: fdcan_send + * + * Description: + * Send one can message. + * + * One CAN-message consists of a maximum of 10 bytes. A message is + * composed of at least the first 2 bytes (when there are no data bytes). + * + * Byte 0: Bits 0-7: Bits 3-10 of the 11-bit CAN identifier + * Byte 1: Bits 5-7: Bits 0-2 of the 11-bit CAN identifier + * Bit 4: Remote Transmission Request (RTR) + * Bits 0-3: Data Length Code (DLC) + * Bytes 2-10: CAN data + * + * Input Parameters: + * dev - An instance of the "upper half" can driver state structure. + * + * Returned Value: + * Zero on success; a negated errno on failure + * + ****************************************************************************/ + +static int fdcan_send(struct stm32_fdcan_s *priv) +{ + const struct stm32_config_s *config = NULL; + volatile uint32_t *txbuffer = NULL; + const uint8_t *src = NULL; + uint32_t *dest = NULL; + uint32_t regval = 0; + unsigned int ndx = 0; + unsigned int nbytes = 0; + uint32_t wordbuffer = 0; + unsigned int i = 0; + + DEBUGASSERT(priv); + config = priv->config; + DEBUGASSERT(config); + + fdcan_dumptxregs(priv, "Before send"); + + /* That that FIFO elements were configured */ + + DEBUGASSERT(config->ntxfifoq > 0); + + /* Get our reserved Tx FIFO/queue put index */ + + regval = fdcan_getreg(priv, STM32_FDCAN_TXFQS_OFFSET); + DEBUGASSERT((regval & FDCAN_TXFQS_TFQF) == 0); + + ndx = (regval & FDCAN_TXFQS_TFQPI_MASK) >> FDCAN_TXFQS_TFQPI_SHIFT; + + /* And the TX buffer corresponding to this index */ + + txbuffer = (config->msgram.txfifoq + ndx * config->txbufferesize); + + /* Format the TX FIFOQ entry + * + * Format word T0: + * Transfer message ID (ID) - Value from message structure + * Remote Transmission Request (RTR) - Value from message structure + * Extended Identifier (XTD) - Depends on configuration. + * Error state indicator (ESI) - ESI bit in CAN FD + * + * Format word T1: + * Data Length Code (DLC) - Value from message structure + * Bit Rate Switch (BRS) - Bit rate switching for CAN FD + * FD format (FDF) - Frame transmitted in CAN FD format + * Event FIFO Control (EFC) - Do not store events. + * Message Marker (MM) - Always zero + */ + + txbuffer[0] = 0; + txbuffer[1] = 0; + + /* CAN 2.0 or CAN FD */ + + if (priv->dev.d_len == sizeof(struct can_frame)) + { + struct can_frame *frame = NULL; + + frame = (struct can_frame *)priv->dev.d_buf; + + ninfo("CAN%" PRIu8 " 2.0 ID: %" PRIu32 " DLC: %" PRIu8 "\n", + config->port, (uint32_t)frame->can_id, frame->can_dlc); + + /* Extended or standard ID */ + +#ifdef CONFIG_NET_CAN_EXTID + if ((frame->can_id & CAN_EFF_FLAG) != 0) + { + DEBUGASSERT((frame->can_id ^ CAN_EFF_FLAG) < (1 << 29)); + + txbuffer[0] |= BUFFER_R0_EXTID(frame->can_id) | BUFFER_R0_XTD; + } + else +#endif + { + DEBUGASSERT(frame->can_id < (1 << 11)); + + txbuffer[0] |= BUFFER_R0_STDID(frame->can_id); + } + + /* Set DLC */ + + txbuffer[1] |= BUFFER_R1_DLC(frame->can_dlc); + + /* Set flags */ + + if ((frame->can_id & CAN_RTR_FLAG) != 0) + { + txbuffer[0] |= BUFFER_R0_RTR; + } + + /* Reset CAN FD bits */ + + txbuffer[0] &= ~BUFFER_R0_ESI; + txbuffer[1] &= ~BUFFER_R1_FDF; + txbuffer[1] &= ~BUFFER_R1_BRS; + + /* Followed by the amount of data corresponding to the DLC (T2..) */ + + src = frame->data; + nbytes = frame->can_dlc; + } +#ifdef CONFIG_NET_CAN_CANFD + else /* CAN FD frame */ + { + struct canfd_frame *frame = (struct canfd_frame *)priv->dev.d_buf; + + frame = (struct canfd_frame *)priv->dev.d_buf; + + ninfo("CAN%" PRIu8 " FD ID: %" PRIu32 " len: %" PRIu8 "\n", + config->port, (uint32_t)frame->can_id, frame->len); + + /* Extended or standard ID */ + +#ifdef CONFIG_NET_CAN_EXTID + if ((frame->can_id & CAN_EFF_FLAG) != 0) + { + DEBUGASSERT(frame->can_id < (1 << 29)); + + txbuffer[0] |= BUFFER_R0_EXTID(frame->can_id) | BUFFER_R0_XTD; + } + else +#endif + { + DEBUGASSERT(frame->can_id < (1 << 11)); + + txbuffer[0] |= BUFFER_R0_STDID(frame->can_id); + } + + /* CANFD frame */ + + txbuffer[1] |= BUFFER_R1_FDF; + + /* Set DLC */ + + txbuffer[1] |= BUFFER_R1_DLC(g_len_to_can_dlc[frame->len]); + + /* Set flags */ + + if ((frame->can_id & CAN_RTR_FLAG) != 0) + { + txbuffer[0] |= BUFFER_R0_RTR; + } + + if ((frame->flags & CANFD_BRS) != 0) + { + txbuffer[1] |= BUFFER_R1_BRS; + } + + if ((frame->flags & CANFD_ESI) != 0) + { + txbuffer[0] |= BUFFER_R0_ESI; + } + + /* Followed by the amount of data corresponding to the DLC (T2..) */ + + src = frame->data; + nbytes = frame->len; + } +#endif + + dest = (uint32_t *)&txbuffer[2]; + + /* Writes must be word length */ + + for (i = 0; i < nbytes; i += 4) + { + /* Little endian is assumed */ + + wordbuffer = src[0] | + (src[1] << 8) | + (src[2] << 16) | + (src[3] << 24); + src += 4; + + *dest++ = wordbuffer; + } + + /* Enable transmit interrupts from the TX FIFOQ buffer by setting TC + * interrupt bit in IR (also requires that the TC interrupt is enabled) + */ + + fdcan_putreg(priv, STM32_FDCAN_TXBTIE_OFFSET, (1 << ndx)); + + /* And request to send the packet */ + + fdcan_putreg(priv, STM32_FDCAN_TXBAR_OFFSET, (1 << ndx)); + + return OK; +} + +/**************************************************************************** + * Name: fdcan_txready + * + * Description: + * Return true if the FDCAN hardware can accept another TX message. + * + * Input Parameters: + * dev - An instance of the "upper half" can driver state structure. + * + * Returned Value: + * True if the FDCAN hardware is ready to accept another TX message. + * + ****************************************************************************/ + +static bool fdcan_txready(struct stm32_fdcan_s *priv) +{ + uint32_t regval = 0; + bool notfull = false; + + /* Return the state of the TX FIFOQ. Return TRUE if the TX FIFO/Queue is + * not full. + */ + + regval = fdcan_getreg(priv, STM32_FDCAN_TXFQS_OFFSET); + notfull = ((regval & FDCAN_TXFQS_TFQF) == 0); + + return notfull; +} + +/**************************************************************************** + * Name: fdcan_rx0interrupt_work + * + * Description: + * CAN RX FIFO 0 worker + * + ****************************************************************************/ + +static void fdcan_rx0interrupt_work(void *arg) +{ + struct stm32_fdcan_s *priv = (struct stm32_fdcan_s *)arg; + const struct stm32_config_s *config = NULL; + uint32_t regval = 0; + unsigned int nelem = 0; + unsigned int ndx = 0; + + DEBUGASSERT(priv); + config = priv->config; + DEBUGASSERT(config); + + /* Clear the RX FIFO0 new message interrupt */ + + fdcan_putreg(priv, STM32_FDCAN_IR_OFFSET, FDCAN_INT_RF0N); + + regval = fdcan_getreg(priv, STM32_FDCAN_RXF0S_OFFSET); + nelem = (regval & FDCAN_RXFS_FFL_MASK) >> FDCAN_RXFS_FFL_SHIFT; + if (nelem > 0) + { + /* Handle the newly received message in FIFO0 */ + + ndx = (regval & FDCAN_RXFS_FGI_MASK) >> FDCAN_RXFS_FGI_SHIFT; + + if ((regval & FDCAN_RXFS_RFL) != 0) + { + nerr("ERROR: Message lost: %08" PRIx32 "\n", regval); + } + else + { + fdcan_receive(priv, + config->msgram.rxfifo0 + + (ndx * priv->config->rxfifo0esize), + priv->config->rxfifo0esize); + +#ifdef CONFIG_NET_CAN_ERRORS + /* Turning back on all configured RX error interrupts */ + + regval = fdcan_getreg(priv, STM32_FDCAN_IE_OFFSET); + regval |= FDCAN_RXERR_INTS; + fdcan_putreg(priv, STM32_FDCAN_IE_OFFSET, regval); +#endif + } + + /* Acknowledge reading the FIFO entry */ + + fdcan_putreg(priv, STM32_FDCAN_RXF0A_OFFSET, ndx); + } + + /* Re-enable CAN RX interrupts */ + + fdcan_rx0int(priv, true); +} + +/**************************************************************************** + * Name: fdcan_rx1interrupt_work + * + * Description: + * CAN RX FIFO 1 worker + * + ****************************************************************************/ + +static void fdcan_rx1interrupt_work(void *arg) +{ + struct stm32_fdcan_s *priv = (struct stm32_fdcan_s *)arg; + const struct stm32_config_s *config = NULL; + uint32_t regval = 0; + unsigned int nelem = 0; + unsigned int ndx = 0; + + DEBUGASSERT(priv); + config = priv->config; + DEBUGASSERT(config); + + /* Clear the RX FIFO1 new message interrupt */ + + fdcan_putreg(priv, STM32_FDCAN_IR_OFFSET, FDCAN_INT_RF1N); + + /* Check if there is anything in RX FIFO1 */ + + regval = fdcan_getreg(priv, STM32_FDCAN_RXF1S_OFFSET); + nelem = (regval & FDCAN_RXFS_FFL_MASK) >> FDCAN_RXFS_FFL_SHIFT; + if (nelem == 0) + { + /* Clear the RX FIFO1 interrupt (and all other FIFO1-related + * interrupts) + */ + + /* Handle the newly received message in FIFO1 */ + + ndx = (regval & FDCAN_RXFS_FGI_MASK) >> FDCAN_RXFS_FGI_SHIFT; + + if ((regval & FDCAN_RXFS_RFL) != 0) + { + nerr("ERROR: Message lost: %08" PRIx32 "\n", regval); + } + else + { + fdcan_receive(priv, + config->msgram.rxfifo1 + + (ndx * priv->config->rxfifo1esize), + priv->config->rxfifo1esize); + +#ifdef CONFIG_NET_CAN_ERRORS + /* Turning back on all configured RX error interrupts */ + + regval = fdcan_getreg(priv, STM32_FDCAN_IE_OFFSET); + regval |= FDCAN_RXERR_INTS; + fdcan_putreg(priv, STM32_FDCAN_IE_OFFSET, regval); +#endif + } + + /* Acknowledge reading the FIFO entry */ + + fdcan_putreg(priv, STM32_FDCAN_RXF1A_OFFSET, ndx); + } + + /* Re-enable CAN RX interrupts */ + + fdcan_rx1int(priv, true); +} + +/**************************************************************************** + * Name: fdcan_txdone_work + ****************************************************************************/ + +static void fdcan_txdone_work(void *arg) +{ + struct stm32_fdcan_s *priv = (struct stm32_fdcan_s *)arg; + + fdcan_txdone(priv); + + /* There should be space for a new TX in any event. Poll the network for + * new XMIT data + */ + + net_lock(); + devif_poll(&priv->dev, fdcan_txpoll); + net_unlock(); +} + +/**************************************************************************** + * Name: fdcan_txdone + ****************************************************************************/ + +static void fdcan_txdone(struct stm32_fdcan_s *priv) +{ + const struct stm32_config_s *config = NULL; + unsigned int ndx = 0; + uint32_t regval = 0; + + DEBUGASSERT(priv); + config = priv->config; + DEBUGASSERT(config); + + /* Clear the pending TX completion interrupt (and all + * other TX-related interrupts) + */ + + fdcan_putreg(priv, STM32_FDCAN_IR_OFFSET, FDCAN_TXFIFOQ_INTS); + + /* Check all TX buffers */ + + regval = fdcan_getreg(priv, STM32_FDCAN_TXBTO_OFFSET); + for (ndx = 0; ndx < config->ntxfifoq; ndx++) + { + if ((regval & (1 << ndx)) != 0) + { + /* Tell the upper half that the transfer is finished. */ + + NETDEV_TXDONE(&priv->dev); + } + } + +#ifdef CONFIG_NET_CAN_ERRORS + /* Turning back on PEA and PED error interrupts */ + + regval = fdcan_getreg(priv, STM32_FDCAN_IE_OFFSET); + regval |= (FDCAN_INT_PEA | FDCAN_INT_PED); + fdcan_putreg(priv, STM32_FDCAN_IE_OFFSET, regval); +#endif + + /* Re-enable TX interrupts */ + + fdcan_txint(priv, true); +} + +#ifdef CONFIG_NET_CAN_ERRORS +/**************************************************************************** + * Name: fdcan_error_work + ****************************************************************************/ + +static void fdcan_error_work(void *arg) +{ + struct stm32_fdcan_s *priv = (struct stm32_fdcan_s *)arg; + uint32_t pending = 0; + uint32_t ir = 0; + uint32_t ie = 0; + uint32_t psr = 0; + + /* Get the set of pending interrupts. */ + + ir = fdcan_getreg(priv, STM32_FDCAN_IR_OFFSET); + ie = fdcan_getreg(priv, STM32_FDCAN_IE_OFFSET); + + pending = (ir & ie); + ie |= FDCAN_ANYERR_INTS; + + /* Check for common errors */ + + if ((pending & FDCAN_CMNERR_INTS) != 0) + { + /* When a protocol error occurs, the problem is recorded in + * the LEC/DLEC fields of the PSR register. In lieu of + * separate interrupt flags for each error, the hardware + * groups protocol errors under a single interrupt each for + * arbitration and data phases. + * + * These errors have a tendency to flood the system with + * interrupts, so they are disabled here until we get a + * successful transfer/receive on the hardware + */ + + psr = fdcan_getreg(priv, STM32_FDCAN_PSR_OFFSET); + + if ((psr & FDCAN_PSR_LEC_MASK) != 0) + { + ie &= ~(FDCAN_INT_PEA | FDCAN_INT_PED); + } + + /* Clear the error indications */ + + fdcan_putreg(priv, STM32_FDCAN_IR_OFFSET, FDCAN_CMNERR_INTS); + } + + /* Check for transmission errors */ + + if ((pending & FDCAN_TXERR_INTS) != 0) + { + /* An Acknowledge-Error will occur if for example the device + * is not connected to the bus. + * + * The CAN-Standard states that the Chip has to retry the + * message forever, which will produce an ACKE every time. + * To prevent this Interrupt-Flooding and the high CPU-Load + * we disable the ACKE here as long we didn't transfer at + * least one message successfully (see FDCAN_INT_TC below). + */ + + /* Clear the error indications */ + + fdcan_putreg(priv, STM32_FDCAN_IR_OFFSET, FDCAN_TXERR_INTS); + } + + /* Check for reception errors */ + + if ((pending & FDCAN_RXERR_INTS) != 0) + { + /* To prevent Interrupt-Flooding the current active + * RX error interrupts are disabled. After successfully + * receiving at least one CAN packet all RX error interrupts + * are turned back on. + * + * The Interrupt-Flooding can for example occur if the + * configured CAN speed does not match the speed of the other + * CAN nodes in the network. + */ + + ie &= ~(pending & FDCAN_RXERR_INTS); + + /* Clear the error indications */ + + fdcan_putreg(priv, STM32_FDCAN_IR_OFFSET, FDCAN_RXERR_INTS); + } + + /* Report errors */ + + net_lock(); + fdcan_error(priv, pending & FDCAN_ANYERR_INTS); + net_unlock(); + + /* Re-enable ERROR interrupts */ + + fdcan_putreg(priv, STM32_FDCAN_IE_OFFSET, ie); +} + +/**************************************************************************** + * Name: fdcan_error + * + * Description: + * Report a CAN error + * + * Input Parameters: + * dev - CAN-common state data + * status - Interrupt status with error bits set + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void fdcan_error(struct stm32_fdcan_s *priv, uint32_t status) +{ + struct can_frame *frame = (struct can_frame *)priv->rxdesc; + uint32_t psr = 0; + uint16_t errbits = 0; + uint8_t data[CAN_ERR_DLC]; + + DEBUGASSERT(priv != NULL); + + /* Encode error bits */ + + errbits = 0; + memset(data, 0, sizeof(data)); + + /* Always fill in "static" error conditions, but set the signaling bit + * only if the condition has changed (see IRQ-Flags below) + * They have to be filled in every time CAN_ERROR_CONTROLLER is set. + */ + + psr = fdcan_getreg(priv, STM32_FDCAN_PSR_OFFSET); + if ((psr & FDCAN_PSR_EP) != 0) + { + data[1] |= (CAN_ERR_CRTL_RX_PASSIVE | CAN_ERR_CRTL_TX_PASSIVE); + } + + if ((psr & FDCAN_PSR_EW) != 0) + { + data[1] |= (CAN_ERR_CRTL_RX_WARNING | CAN_ERR_CRTL_TX_WARNING); + } + + if ((status & (FDCAN_INT_EP | FDCAN_INT_EW)) != 0) + { + /* "Error Passive" or "Error Warning" status changed */ + + errbits |= CAN_ERR_CRTL; + } + + if ((status & FDCAN_INT_PEA) != 0) + { + /* Protocol Error in Arbitration Phase */ + + if ((psr & FDCAN_PSR_LEC_MASK) != 0) + { + /* Error code present */ + + if ((psr & FDCAN_PSR_LEC(FDCAN_PSR_EC_STUFF_ERROR)) != 0) + { + /* Stuff Error */ + + errbits |= CAN_ERR_PROT; + data[2] |= CAN_ERR_PROT_STUFF; + } + + if ((psr & FDCAN_PSR_LEC(FDCAN_PSR_EC_FORM_ERROR)) != 0) + { + /* Format Error */ + + errbits |= CAN_ERR_PROT; + data[2] |= CAN_ERR_PROT_FORM; + } + + if ((psr & FDCAN_PSR_LEC(FDCAN_PSR_EC_ACK_ERROR)) != 0) + { + /* Acknowledge Error */ + + errbits |= CAN_ERR_ACK; + } + + if ((psr & FDCAN_PSR_LEC(FDCAN_PSR_EC_BIT0_ERROR)) != 0) + { + /* Bit0 Error */ + + errbits |= CAN_ERR_PROT; + data[2] |= CAN_ERR_PROT_BIT0; + } + + if ((psr & FDCAN_PSR_LEC(FDCAN_PSR_EC_BIT1_ERROR)) != 0) + { + /* Bit1 Error */ + + errbits |= CAN_ERR_PROT; + data[2] |= CAN_ERR_PROT_BIT1; + } + + if ((psr & FDCAN_PSR_LEC(FDCAN_PSR_EC_CRC_ERROR)) != 0) + { + /* Receive CRC Error */ + + errbits |= CAN_ERR_PROT; + data[3] |= (CAN_ERR_PROT_LOC_CRC_SEQ | + CAN_ERR_PROT_LOC_CRC_DEL); + } + + if ((psr & FDCAN_PSR_LEC(FDCAN_PSR_EC_NO_CHANGE)) != 0) + { + /* No Change in Error */ + + errbits |= CAN_ERR_PROT; + data[2] |= CAN_ERR_PROT_UNSPEC; + } + } + } + + if ((status & FDCAN_INT_PED) != 0) + { + /* Protocol Error in Data Phase */ + + if ((psr & FDCAN_PSR_DLEC_MASK) != 0) + { + /* Error code present */ + + if ((psr & FDCAN_PSR_DLEC(FDCAN_PSR_EC_STUFF_ERROR)) != 0) + { + /* Stuff Error */ + + errbits |= CAN_ERR_PROT; + data[2] |= CAN_ERR_PROT_STUFF; + } + + if ((psr & FDCAN_PSR_DLEC(FDCAN_PSR_EC_FORM_ERROR)) != 0) + { + /* Format Error */ + + errbits |= CAN_ERR_PROT; + data[2] |= CAN_ERR_PROT_FORM; + } + + if ((psr & FDCAN_PSR_DLEC(FDCAN_PSR_EC_ACK_ERROR)) != 0) + { + /* Acknowledge Error */ + + errbits |= CAN_ERR_ACK; + } + + if ((psr & FDCAN_PSR_DLEC(FDCAN_PSR_EC_BIT0_ERROR)) != 0) + { + /* Bit0 Error */ + + errbits |= CAN_ERR_PROT; + data[2] |= CAN_ERR_PROT_BIT0; + } + + if ((psr & FDCAN_PSR_DLEC(FDCAN_PSR_EC_BIT1_ERROR)) != 0) + { + /* Bit1 Error */ + + errbits |= CAN_ERR_PROT; + data[2] |= CAN_ERR_PROT_BIT1; + } + + if ((psr & FDCAN_PSR_DLEC(FDCAN_PSR_EC_CRC_ERROR)) != 0) + { + /* Receive CRC Error */ + + errbits |= CAN_ERR_PROT; + data[3] |= (CAN_ERR_PROT_LOC_CRC_SEQ | + CAN_ERR_PROT_LOC_CRC_DEL); + } + + if ((psr & FDCAN_PSR_DLEC(FDCAN_PSR_EC_NO_CHANGE)) != 0) + { + /* No Change in Error */ + + errbits |= CAN_ERR_PROT; + data[2] |= CAN_ERR_PROT_UNSPEC; + } + } + } + + if ((status & FDCAN_INT_BO) != 0) + { + /* Bus_Off Status changed */ + + if ((psr & FDCAN_PSR_BO) != 0) + { + errbits |= CAN_ERR_BUSOFF; + } + else + { + errbits |= CAN_ERR_RESTARTED; + } + } + + if ((status & (FDCAN_INT_RF0L | FDCAN_INT_RF1L)) != 0) + { + /* Receive FIFO 0/1 Message Lost + * Receive FIFO 1 Message Lost + */ + + errbits |= CAN_ERR_CRTL; + data[1] |= CAN_ERR_CRTL_RX_OVERFLOW; + } + + if ((status & FDCAN_INT_TEFL) != 0) + { + /* Tx Event FIFO Element Lost */ + + errbits |= CAN_ERR_CRTL; + data[1] |= CAN_ERR_CRTL_TX_OVERFLOW; + } + + if ((status & FDCAN_INT_TOO) != 0) + { + /* Timeout Occurred */ + + errbits |= CAN_ERR_TX_TIMEOUT; + } + + if ((status & (FDCAN_INT_MRAF | FDCAN_INT_ELO)) != 0) + { + /* Message RAM Access Failure + * Error Logging Overflow + */ + + errbits |= CAN_ERR_CRTL; + data[1] |= CAN_ERR_CRTL_UNSPEC; + } + + if (errbits != 0) + { + nerr("ERROR: errbits = %08" PRIx16 "\n", errbits); + + /* Copy frame */ + + frame->can_id = errbits; + frame->can_dlc = CAN_ERR_DLC; + + memcpy(frame->data, data, CAN_ERR_DLC); + + /* Copy the buffer pointer to priv->dev.. Set amount of data + * in priv->dev.d_len + */ + + priv->dev.d_len = sizeof(struct can_frame); + priv->dev.d_buf = (uint8_t *)frame; + + /* Send to socket interface */ + + NETDEV_ERRORS(&priv->dev); + + can_input(&priv->dev); + + /* Point the packet buffer back to the next Tx buffer that will be + * used during the next write. If the write queue is full, then + * this will point at an active buffer, which must not be written + * to. This is OK because devif_poll won't be called unless the + * queue is not full. + */ + + priv->dev.d_buf = (uint8_t *)priv->txdesc; + } +} +#endif /* CONFIG_NET_CAN_ERRORS */ + +/**************************************************************************** + * Name: fdcan_receive + * + * Description: + * Receive an FDCAN messages + * + * Input Parameters: + * dev - CAN-common state data + * rxbuffer - The RX buffer containing the received messages + * nwords - The length of the RX buffer (element size in words). + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void fdcan_receive(struct stm32_fdcan_s *priv, + volatile uint32_t *rxbuffer, + unsigned long nwords) +{ + fdcan_dumprxregs(dev->cd_priv, "Before receive"); + + /* CAN 2.0 or CAN FD */ + +#ifdef CONFIG_NET_CAN_CANFD + if ((rxbuffer[1] & BUFFER_R1_FDF) != 0) + { + struct canfd_frame *frame = (struct canfd_frame *)priv->rxdesc; + + /* Format the CAN FD header */ + + /* Extract the RTR bit */ + + if ((rxbuffer[0] & BUFFER_R0_RTR) != 0) + { + frame->can_id |= CAN_RTR_FLAG; + } + +#ifdef CONFIG_NET_CAN_EXTID + if ((rxbuffer[0] & BUFFER_R0_XTD) != 0) + { + /* Save the extended ID of the newly received message */ + + frame->can_id = ((rxbuffer[0] & BUFFER_R0_EXTID_MASK) >> + BUFFER_R0_EXTID_SHIFT); + frame->can_id |= CAN_EFF_FLAG; + } + else + { + frame->can_id = ((rxbuffer[0] & BUFFER_R0_STDID_MASK) >> + BUFFER_R0_STDID_SHIFT); + frame->can_id &= ~CAN_EFF_FLAG; + } +#else + if ((rxbuffer[0] & BUFFER_R0_XTD) != 0) + { + /* Drop any messages with extended IDs */ + + return; + } + + /* Save the standard ID of the newly received message */ + + frame->can_id = ((rxbuffer[0] & BUFFER_R0_STDID_MASK) >> + BUFFER_R0_STDID_SHIFT); +#endif + + /* Word R1 contains the DLC and timestamp */ + + frame->len = g_can_dlc_to_len[((rxbuffer[1] & BUFFER_R1_DLC_MASK) >> + BUFFER_R1_DLC_SHIFT)]; + + /* Get CANFD flags */ + + frame->flags = 0; + + if ((rxbuffer[0] & BUFFER_R0_ESI) != 0) + { + frame->flags |= CANFD_ESI; + } + + if ((rxbuffer[1] & BUFFER_R1_BRS) != 0) + { + frame->flags |= CANFD_BRS; + } + + /* Save the message data */ + + memcpy(frame->data, (void *)&rxbuffer[2], frame->len); + + /* Copy the buffer pointer to priv->dev.. Set amount of data + * in priv->dev.d_len + */ + + priv->dev.d_len = sizeof(struct canfd_frame); + priv->dev.d_buf = (uint8_t *)frame; + } + else +#endif + { + struct can_frame *frame = (struct can_frame *)priv->rxdesc; + + /* Format the CAN header */ + + /* Extract the RTR bit */ + + if ((rxbuffer[0] & BUFFER_R0_RTR) != 0) + { + frame->can_id |= CAN_RTR_FLAG; + } + +#ifdef CONFIG_NET_CAN_EXTID + if ((rxbuffer[0] & BUFFER_R0_XTD) != 0) + { + /* Save the extended ID of the newly received message */ + + frame->can_id = ((rxbuffer[0] & BUFFER_R0_EXTID_MASK) >> + BUFFER_R0_EXTID_SHIFT); + frame->can_id |= CAN_EFF_FLAG; + } + else + { + frame->can_id = ((rxbuffer[0] & BUFFER_R0_STDID_MASK) >> + BUFFER_R0_STDID_SHIFT); + frame->can_id &= ~CAN_EFF_FLAG; + } +#else + if ((rxbuffer[0] & BUFFER_R0_XTD) != 0) + { + /* Drop any messages with extended IDs */ + + return; + } + + /* Save the standard ID of the newly received message */ + + frame->can_id = ((rxbuffer[0] & BUFFER_R0_STDID_MASK) >> + BUFFER_R0_STDID_SHIFT); +#endif + + /* Word R1 contains the DLC and timestamp */ + + frame->can_dlc = ((rxbuffer[1] & BUFFER_R1_DLC_MASK) >> + BUFFER_R1_DLC_SHIFT); + + /* Save the message data */ + + memcpy(frame->data, (void *)&rxbuffer[2], frame->can_dlc); + + /* Copy the buffer pointer to priv->dev.. Set amount of data + * in priv->dev.d_len + */ + + priv->dev.d_len = sizeof(struct can_frame); + priv->dev.d_buf = (uint8_t *)frame; + } + + /* Send to socket interface */ + + NETDEV_RXPACKETS(&priv->dev); + + can_input(&priv->dev); + + /* Point the packet buffer back to the next Tx buffer that will be + * used during the next write. If the write queue is full, then + * this will point at an active buffer, which must not be written + * to. This is OK because devif_poll won't be called unless the + * queue is not full. + */ + + priv->dev.d_buf = (uint8_t *)priv->txdesc; +} + +/**************************************************************************** + * Name: fdcan_interrupt + * + * Description: + * Common FDCAN interrupt handler + * + * irq - The IRQ number of the interrupt. + * context - The register state save array at the time of the interrupt. + * + * Returned Value: + * Zero on success; a negated errno on failure + * + ****************************************************************************/ + +static int fdcan_interrupt(int irq, void *context, void *arg) +{ + struct stm32_fdcan_s *priv = (struct stm32_fdcan_s *)arg; + uint32_t pending = 0; + + DEBUGASSERT(priv != NULL); + + /* Get the set of pending interrupts. */ + + pending = fdcan_getreg(priv, STM32_FDCAN_IR_OFFSET); + +#ifdef CONFIG_NET_CAN_ERRORS + /* Check for any errors */ + + if ((pending & FDCAN_ANYERR_INTS) != 0) + { + /* Disable further CAN ERROR interrupts and schedule to perform the + * interrupt processing on the worker thread + */ + + fdcan_errint(priv, false); + work_queue(CANWORK, &priv->irqwork, fdcan_error_work, priv, 0); + } +#endif + + /* Check for successful completion of a transmission */ + + if ((pending & FDCAN_INT_TC) != 0) + { + /* Disable further TX CAN interrupts. here can be no race + * condition here. + */ + + fdcan_txint(priv, false); + work_queue(CANWORK, &priv->irqwork, fdcan_txdone_work, priv, 0); + } + else if ((pending & FDCAN_TXFIFOQ_INTS) != 0) + { + /* Clear unhandled TX events */ + + fdcan_putreg(priv, STM32_FDCAN_IR_OFFSET, FDCAN_TXFIFOQ_INTS); + } + + if (pending & FDCAN_INT_RF1N) + { + /* Disable further CAN RX interrupts and schedule to perform the + * interrupt processing on the worker thread + */ + + fdcan_rx1int(priv, false); + work_queue(CANWORK, &priv->irqwork, + fdcan_rx1interrupt_work, priv, 0); + } + + /* Clear the RX FIFO0 new message interrupt */ + + if (pending & FDCAN_INT_RF0N) + { + /* Disable further CAN RX interrupts and schedule to perform the + * interrupt processing on the worker thread + */ + + fdcan_rx0int(priv, false); + work_queue(CANWORK, &priv->irqwork, + fdcan_rx0interrupt_work, priv, 0); + } + + return OK; +} + +/**************************************************************************** + * Name: fdcan_hw_initialize + * + * Description: + * FDCAN hardware initialization + * + * Input Parameters: + * priv - A pointer to the private data structure for this FDCAN peripheral + * + * Returned Value: + * Zero on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int fdcan_hw_initialize(struct stm32_fdcan_s *priv) +{ + const struct stm32_config_s *config = NULL; + volatile uint32_t *msgram = NULL; + uint32_t regval = 0; + uint32_t cntr = 0; + + DEBUGASSERT(priv); + config = priv->config; + DEBUGASSERT(config); + + ninfo("FDCAN%d\n", config->port); + + /* Clean message RAM */ + + msgram = config->msgram.stdfilters; + cntr = (FDCAN_MSGRAM_WORDS + 1); + while (cntr > 0) + { + *msgram++ = 0; + cntr--; + } + + /* Configure FDCAN pins */ + + stm32_configgpio(config->rxpinset); + stm32_configgpio(config->txpinset); + + /* Re-enable device if previously disabled in fdcan_shutdown() */ + + if (priv->state == FDCAN_STATE_DISABLED) + { + /* Reset Clock Stop Request bit */ + + regval = fdcan_getreg(priv, STM32_FDCAN_CCCR_OFFSET); + regval &= ~FDCAN_CCCR_CSR; + fdcan_putreg(priv, STM32_FDCAN_CCCR_OFFSET, regval); + + /* Wait for Clock Stop Acknowledge bit reset to indicate + * device is operational + */ + + while ((fdcan_getreg(priv, STM32_FDCAN_CCCR_OFFSET) & FDCAN_CCCR_CSA) + != 0); + } + + /* Enable the Initialization state */ + + regval = fdcan_getreg(priv, STM32_FDCAN_CCCR_OFFSET); + regval |= FDCAN_CCCR_INIT; + fdcan_putreg(priv, STM32_FDCAN_CCCR_OFFSET, regval); + + /* Wait for initialization mode to take effect */ + + while ((fdcan_getreg(priv, STM32_FDCAN_CCCR_OFFSET) & FDCAN_CCCR_INIT) + == 0); + + /* Enable writing to configuration registers */ + + regval = fdcan_getreg(priv, STM32_FDCAN_CCCR_OFFSET); + regval |= FDCAN_CCCR_CCE; + fdcan_putreg(priv, STM32_FDCAN_CCCR_OFFSET, regval); + + /* Global Filter Configuration: + * + * ANFS=0: Store all non matching standard frame in RX FIFO0 + * ANFE=0: Store all non matching extended frame in RX FIFO0 + */ + + regval = FDCAN_RXGFC_ANFE_RX_FIFO0 | FDCAN_RXGFC_ANFS_RX_FIFO0; + fdcan_putreg(priv, STM32_FDCAN_RXGFC_OFFSET, regval); + + /* Extended ID Filter AND mask */ + + fdcan_putreg(priv, STM32_FDCAN_XIDAM_OFFSET, 0x1fffffff); + + /* Disable all interrupts */ + + fdcan_putreg(priv, STM32_FDCAN_IE_OFFSET, 0); + fdcan_putreg(priv, STM32_FDCAN_TXBTIE_OFFSET, 0); + + /* All interrupts directed to Line 0. But disable both interrupt lines 0 + * and 1 for now. + * + * REVISIT: Only interrupt line 0 is used by this driver. + */ + + fdcan_putreg(priv, STM32_FDCAN_ILS_OFFSET, 0); + fdcan_putreg(priv, STM32_FDCAN_ILE_OFFSET, 0); + + /* Clear all pending interrupts. */ + + fdcan_putreg(priv, STM32_FDCAN_IR_OFFSET, FDCAN_INT_ALL); + + /* Configure FDCAN bit timing */ + + fdcan_putreg(priv, STM32_FDCAN_NBTP_OFFSET, priv->nbtp); + fdcan_putreg(priv, STM32_FDCAN_DBTP_OFFSET, priv->dbtp); + + /* Configure message RAM starting addresses and sizes. */ + + regval = FDCAN_RXGFC_LSS(config->nstdfilters); + regval |= FDCAN_RXGFC_LSE(config->nextfilters); + fdcan_putreg(priv, STM32_FDCAN_RXGFC_OFFSET, regval); + + /* Dump RAM layout */ + + fdcan_dumpramlayout(priv); + + /* Configure Message Filters */ + + /* Disable all standard filters */ + + msgram = config->msgram.stdfilters; + cntr = config->nstdfilters; + while (cntr > 0) + { + *msgram++ = STDFILTER_S0_SFEC_DISABLE; + cntr--; + } + + /* Disable all extended filters */ + + msgram = config->msgram.extfilters; + cntr = config->nextfilters; + while (cntr > 0) + { + *msgram = EXTFILTER_F0_EFEC_DISABLE; + msgram = msgram + 2; + cntr--; + } + + /* Input clock divider configuration */ + + regval = FDCANCLK_PDIV; + fdcan_putreg(priv, STM32_FDCAN_CKDIV_OFFSET, regval); + + /* CC control register */ + + regval = fdcan_getreg(priv, STM32_FDCAN_CCCR_OFFSET); + regval &= ~(FDCAN_CCCR_NISO | FDCAN_CCCR_FDOE | FDCAN_CCCR_BRSE); + + /* Select ISO11898-1 or Non ISO Bosch CAN FD Specification V1.0 */ + + switch (config->format) + { + case FDCAN_ISO11898_1_FORMAT: + { + break; + } + + case FDCAN_NONISO_BOSCH_V1_FORMAT: + { + regval |= FDCAN_CCCR_NISO; + break; + } + + default: + { + return -EINVAL; + } + } + + /* Select Classic CAN mode or FD mode with or without fast bit rate + * switching + */ + + switch (config->mode) + { + case FDCAN_CLASSIC_MODE: + { + break; + } + +#ifdef CONFIG_NET_CAN_CANFD + case FDCAN_FD_MODE: + { + regval |= FDCAN_CCCR_FDOE; + break; + } + + case FDCAN_FD_BRS_MODE: + { + regval |= (FDCAN_CCCR_FDOE | FDCAN_CCCR_BRSE); + break; + } +#endif + + default: + { + return -EINVAL; + } + } + + /* Set the initial CAN mode */ + + fdcan_putreg(priv, STM32_FDCAN_CCCR_OFFSET, regval); + + /* Enable FIFO/Queue mode */ + + regval = fdcan_getreg(priv, STM32_FDCAN_TXBC_OFFSET); +#ifdef CONFIG_STM32_FDCAN_QUEUE_MODE + regval |= FDCAN_TXBC_TFQM; +#else + regval &= ~FDCAN_TXBC_TFQM; +#endif + fdcan_putreg(priv, STM32_FDCAN_TXBC_OFFSET, regval); + +#ifdef STM32_FDCAN_LOOPBACK + /* Is loopback mode selected for this peripheral? */ + + if (config->loopback) + { + /* FDCAN_CCCR_TEST - Test mode enable + * FDCAN_CCCR_MON - Bus monitoring mode (for internal loopback) + * FDCAN_TEST_LBCK - Loopback mode + */ + + regval = fdcan_getreg(priv, STM32_FDCAN_CCCR_OFFSET); + regval |= (FDCAN_CCCR_TEST | FDCAN_CCCR_MON); + fdcan_putreg(priv, STM32_FDCAN_CCCR_OFFSET, regval); + + regval = fdcan_getreg(priv, STM32_FDCAN_TEST_OFFSET); + regval |= FDCAN_TEST_LBCK; + fdcan_putreg(priv, STM32_FDCAN_TEST_OFFSET, regval); + } +#endif + + /* Configure interrupt lines */ + + /* Direct all interrupts to Line 0. + * + * Bits in the ILS register correspond to each FDCAN interrupt; A bit + * set to '1' is directed to interrupt line 1; a bit cleared to '0' + * is directed interrupt line 0. + * + * REVISIT: Nothing is done here. Only interrupt line 0 is used by + * this driver and ILS was already cleared above. + */ + + /* Enable only interrupt line 0. */ + + fdcan_putreg(priv, STM32_FDCAN_ILE_OFFSET, FDCAN_ILE_EINT0); + + /* Disable initialization mode to enable normal operation */ + + regval = fdcan_getreg(priv, STM32_FDCAN_CCCR_OFFSET); + regval &= ~FDCAN_CCCR_INIT; + fdcan_putreg(priv, STM32_FDCAN_CCCR_OFFSET, regval); + + return OK; +} + +/**************************************************************************** + * Function: fdcan_ifup + * + * Description: + * NuttX Callback: Bring up the Ethernet interface when an IP address is + * provided + * + * Input Parameters: + * dev - Reference to the NuttX driver state structure + * + * Returned Value: + * None + * + * Assumptions: + * + ****************************************************************************/ + +static int fdcan_ifup(struct net_driver_s *dev) +{ + struct stm32_fdcan_s *priv = + (struct stm32_fdcan_s *)dev->d_private; + const struct stm32_config_s *config = NULL; + + DEBUGASSERT(priv); + config = priv->config; + DEBUGASSERT(config); + + /* Setup CAN */ + + fdcan_setup(priv); + + /* Enable interrupts */ + + fdcan_rx0int(priv, true); + fdcan_rx1int(priv, true); + fdcan_txint(priv, true); +#ifdef CONFIG_NET_CAN_ERRORS + fdcan_errint(priv, true); +#endif + + /* Enable the interrupts at the NVIC */ + + up_enable_irq(config->irq0); + up_enable_irq(config->irq1); + + priv->bifup = true; + + priv->txdesc = (struct can_frame *)priv->tx_pool; + priv->rxdesc = (struct can_frame *)priv->rx_pool; + + priv->dev.d_buf = (uint8_t *)priv->txdesc; + + netdev_carrier_on(dev); + + return OK; +} + +/**************************************************************************** + * Function: fdcan_ifdown + * + * Description: + * NuttX Callback: Stop the interface. + * + * Input Parameters: + * dev - Reference to the NuttX driver state structure + * + * Returned Value: + * None + * + * Assumptions: + * + ****************************************************************************/ + +static int fdcan_ifdown(struct net_driver_s *dev) +{ + struct stm32_fdcan_s *priv = + (struct stm32_fdcan_s *)dev->d_private; + + /* Disable CAN interrupts */ + + fdcan_shutdown(priv); + + /* Reset CAN */ + + fdcan_reset(priv); + + netdev_carrier_off(dev); + + return OK; +} + +/**************************************************************************** + * Function: fdcan_txpoll + * + * Description: + * The transmitter is available, check if the network has any outgoing + * packets ready to send. This is a callback from devif_poll(). + * devif_poll() may be called: + * + * 1. When the preceding TX packet send is complete, + * 2. When the preceding TX packet send timesout and the interface is reset + * 3. During normal TX polling + * + * Input Parameters: + * dev - Reference to the NuttX driver state structure + * + * Returned Value: + * OK on success; a negated errno on failure + * + * Assumptions: + * May or may not be called from an interrupt handler. In either case, + * global interrupts are disabled, either explicitly or indirectly through + * interrupt handling logic. + * + ****************************************************************************/ + +static int fdcan_txpoll(struct net_driver_s *dev) +{ + struct stm32_fdcan_s *priv = + (struct stm32_fdcan_s *)dev->d_private; + + /* If the polling resulted in data that should be sent out on the network, + * the field d_len is set to a value > 0. + */ + + if (priv->dev.d_len > 0) + { + fdcan_txdone(priv); + + /* Send the packet */ + + fdcan_send(priv); + + /* Check if there is room in the device to hold another packet. If + * not, return a non-zero value to terminate the poll. + */ + + if (fdcan_txready(priv) == false) + { + return -EBUSY; + } + } + + /* If zero is returned, the polling will continue until all connections + * have been examined. + */ + + return 0; +} + +/**************************************************************************** + * Function: fdcan_txavail_work + * + * Description: + * Perform an out-of-cycle poll on the worker thread. + * + * Input Parameters: + * arg - Reference to the NuttX driver state structure (cast to void*) + * + * Returned Value: + * None + * + * Assumptions: + * Called on the higher priority worker thread. + * + ****************************************************************************/ + +static void fdcan_txavail_work(void *arg) +{ + struct stm32_fdcan_s *priv = (struct stm32_fdcan_s *)arg; + + /* Ignore the notification if the interface is not yet up */ + + net_lock(); + if (priv->bifup) + { + /* Check if there is room in the hardware to hold another outgoing + * packet. + */ + + if (fdcan_txready(priv)) + { + /* No, there is space for another transfer. Poll the network for + * new XMIT data. + */ + + devif_poll(&priv->dev, fdcan_txpoll); + } + } + + net_unlock(); +} + +/**************************************************************************** + * Function: fdcan_txavail + * + * Description: + * Driver callback invoked when new TX data is available. This is a + * stimulus perform an out-of-cycle poll and, thereby, reduce the TX + * latency. + * + * Input Parameters: + * dev - Reference to the NuttX driver state structure + * + * Returned Value: + * None + * + * Assumptions: + * Called in normal user mode + * + ****************************************************************************/ + +static int fdcan_txavail(struct net_driver_s *dev) +{ + struct stm32_fdcan_s *priv = + (struct stm32_fdcan_s *)dev->d_private; + + /* Is our single work structure available? It may not be if there are + * pending interrupt actions and we will have to ignore the Tx + * availability action. + */ + + if (work_available(&priv->pollwork)) + { + /* Schedule to serialize the poll on the worker thread. */ + + fdcan_txavail_work(priv); + } + + return OK; +} + +/**************************************************************************** + * Function: fdcan_ioctl + * + * Description: + * PHY ioctl command handler + * + * Input Parameters: + * dev - Reference to the NuttX driver state structure + * cmd - ioctl command + * arg - Argument accompanying the command + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + * Assumptions: + * + ****************************************************************************/ + +#ifdef CONFIG_NETDEV_IOCTL +static int fdcan_netdev_ioctl(struct net_driver_s *dev, int cmd, + unsigned long arg); +{ + struct stm32_fdcan_s *priv = + (struct stm32_fdcan_s *)dev->d_private; + int ret = OK; + + DEBUGASSERT(priv); + + switch (cmd) + { + /* TODO */ + + default: + ret = -ENOTTY; + break; + } + + return ret; +} +#endif /* CONFIG_NETDEV_IOCTL */ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_cansockinitialize + * + * Description: + * Initialize the selected FDCAN port as CAN socket interface + * + * Input Parameters: + * Port number (for hardware that has multiple FDCAN interfaces) + * + * Returned Value: + * OK on success; Negated errno on failure. + * + ****************************************************************************/ + +int stm32_fdcansockinitialize(int port) +{ + struct stm32_fdcan_s *priv = NULL; + const struct stm32_config_s *config = NULL; + int ret = OK; + + ninfo("FDCAN%d\n", port); + + /* Select FDCAN peripheral to be initialized */ + +#ifdef CONFIG_STM32_FDCAN1 + if (port == FDCAN1) + { + /* Select the FDCAN1 device structure */ + + priv = &g_fdcan1priv; + config = &g_fdcan1const; + } + else +#endif +#ifdef CONFIG_STM32_FDCAN2 + if (port == FDCAN2) + { + /* Select the FDCAN2 device structure */ + + priv = &g_fdcan2priv; + config = &g_fdcan2const; + } + else +#endif +#ifdef CONFIG_STM32_FDCAN3 + if (port == FDCAN3) + { + /* Select the FDCAN3 device structure */ + + priv = &g_fdcan3priv; + config = &g_fdcan3const; + } + else +#endif + { + nerr("ERROR: Unsupported port %d\n", port); + ret = -EINVAL; + goto errout; + } + + /* Perform one time data initialization */ + + memset(priv, 0, sizeof(struct stm32_fdcan_s)); + priv->config = config; + + /* Set the initial bit timing. This might change subsequently + * due to IOCTL command processing. + */ + + priv->nbtp = config->nbtp; + priv->dbtp = config->dbtp; + + /* Initialize the driver structure */ + + priv->dev.d_ifup = fdcan_ifup; + priv->dev.d_ifdown = fdcan_ifdown; + priv->dev.d_txavail = fdcan_txavail; +#ifdef CONFIG_NETDEV_IOCTL + priv->dev.d_ioctl = fdcan_netdev_ioctl; +#endif + priv->dev.d_private = priv; + + /* Put the interface in the down state. This usually amounts to resetting + * the device and/or calling fdcan_ifdown(). + */ + + ninfo("callbacks done\n"); + + fdcan_ifdown(&priv->dev); + + /* Register the device with the OS so that socket IOCTLs can be performed */ + + ret = netdev_register(&priv->dev, NET_LL_CAN); + +errout: + return ret; +} + +/**************************************************************************** + * Name: arm_netinitialize + * + * Description: + * Initialize the CAN device interfaces. If there is more than one device + * interface in the chip, then board-specific logic will have to provide + * this function to determine which, if any, CAN interfaces should be + * initialized. + * + ****************************************************************************/ + +#if !defined(CONFIG_NETDEV_LATEINIT) +void arm_netinitialize(void) +{ +#ifdef CONFIG_STM32_CAN1 + stm32_fdcansockinitialize(FDCAN1); +#endif + +#ifdef CONFIG_STM32_CAN2 + stm32_fdcansockinitialize(FDCAN2); +#endif + +#ifdef CONFIG_STM32_CAN3 + stm32_fdcansockinitialize(FDCAN3); +#endif +} +#endif diff --git a/arch/arm/src/common/stm32/stm32_flash.h b/arch/arm/src/common/stm32/stm32_flash.h new file mode 100644 index 0000000000000..9050b255d6bc1 --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_flash.h @@ -0,0 +1,66 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_flash.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_COMPAT_STM32_FLASH_H +#define __ARCH_ARM_SRC_COMMON_COMPAT_STM32_FLASH_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include +#include + +#include "chip.h" +#include "hardware/stm32_flash.h" + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +#if defined(CONFIG_STM32_HAVE_IP_FLASH_M0_V1) + +void stm32_flash_getopt(uint32_t *opt); +int stm32_flash_optmodify(uint32_t clear, uint32_t set); +void stm32_flash_lock(void); +void stm32_flash_unlock(void); + +#elif defined(CONFIG_STM32_HAVE_IP_FLASH_M3M4_V1) + +int stm32_flash_lock(void); +int stm32_flash_unlock(void); +uint32_t stm32_flash_users_optbytes(uint32_t clrbits, uint32_t setbits); +size_t stm32_eeprom_size(void); +size_t stm32_eeprom_getaddress(void); +ssize_t stm32_eeprom_write(size_t addr, const void *buf, size_t buflen); +ssize_t stm32_eeprom_erase(size_t addr, size_t eraselen); + +#endif + +#endif /* __ASSEMBLY__ */ + +#endif /* __ARCH_ARM_SRC_COMMON_COMPAT_STM32_FLASH_H */ diff --git a/arch/arm/src/common/stm32/stm32_flash_m0_g0c0.c b/arch/arm/src/common/stm32/stm32_flash_m0_g0c0.c new file mode 100644 index 0000000000000..ec3a06037fbd5 --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_flash_m0_g0c0.c @@ -0,0 +1,901 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_flash_m0_g0c0.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* Provides standard flash access functions, to be used by the flash mtd + * driver. The interface is defined in the include/nuttx/progmem.h + * + * Notes: + * - Terminology: the G0xx reference manual [RM0444] refers to erase blocks + * as 'pages'. In this file, erase blocks are referred to as 'blocks' and + * the smallest write allowed is referred to as a 'page'. The STMicro + * reference manuals are not consistent in naming convention. + * - Blocking Nature: up_progmem_write() and up_progmem_eraseblock() will + * both block without releasing (up_udelay) while waiting for flash + * operations to complete. Take this into account for applications + * that use these functions. + */ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "stm32_flash.h" + +#include +#include +#include +#include +#include + +#include + +#include +#include +#include + +#include "hardware/stm32_flash.h" +#include "hardware/stm32_memorymap.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define _K(x) ((x)*1024) +#define FLASH_BLOCK_SIZE _K(2) +#define FLASH_PAGE_SIZE 8 + +#if !defined(CONFIG_STM32_FLASH_CONFIG_4) && \ + !defined(CONFIG_STM32_FLASH_CONFIG_6) && \ + !defined(CONFIG_STM32_FLASH_CONFIG_8) && \ + !defined(CONFIG_STM32_FLASH_CONFIG_B) && \ + !defined(CONFIG_STM32_FLASH_CONFIG_C) && \ + !defined(CONFIG_STM32_FLASH_CONFIG_E) && \ + !defined(CONFIG_STM32_FLASH_OVERRIDE) +# error "No valid flash configuration was defined." +#endif + +#ifdef CONFIG_STM32_FLASH_OVERRIDE +# undef CONFIG_STM32_FLASH_CONFIG_4 +# undef CONFIG_STM32_FLASH_CONFIG_6 +# undef CONFIG_STM32_FLASH_CONFIG_8 +# undef CONFIG_STM32_FLASH_CONFIG_B +# undef CONFIG_STM32_FLASH_CONFIG_C +# undef CONFIG_STM32_FLASH_CONFIG_E +# if defined(CONFIG_STM32_FLASH_OVERRIDE_4) +# define CONFIG_STM32_FLASH_CONFIG_4 +# elif defined(CONFIG_STM32_FLASH_OVERRIDE_6) +# define CONFIG_STM32_FLASH_CONFIG_6 +# elif defined(CONFIG_STM32_FLASH_OVERRIDE_8) +# define CONFIG_STM32_FLASH_CONFIG_8 +# elif defined(CONFIG_STM32_FLASH_OVERRIDE_B) +# define CONFIG_STM32_FLASH_CONFIG_B +# elif defined(CONFIG_STM32_FLASH_OVERRIDE_C) +# define CONFIG_STM32_FLASH_CONFIG_C +# elif defined(CONFIG_STM32_FLASH_OVERRIDE_E) +# define CONFIG_STM32_FLASH_CONFIG_E +# else +# error "Invalid flash configuration override provided" +# endif +#endif + +#if defined(CONFIG_STM32_FLASH_CONFIG_4) +# define FLASH_NBLOCKS 8 +#elif defined(CONFIG_STM32_FLASH_CONFIG_6) +# define FLASH_NBLOCKS 16 +#elif defined(CONFIG_STM32_FLASH_CONFIG_8) +# define FLASH_NBLOCKS 32 +#elif defined(CONFIG_STM32_FLASH_CONFIG_B) +# define FLASH_NBLOCKS 64 +#elif defined(CONFIG_STM32_FLASH_CONFIG_C) +# define FLASH_NBLOCKS 128 +# ifdef CONFIG_ARCH_CHIP_STM32G0 +# define FLASH_DUAL_BANK 1 +# define FLASH_BANK2_BASE 0x08020000 +# endif +#elif defined(CONFIG_STM32_FLASH_CONFIG_E) +# define FLASH_NBLOCKS 256 +# ifdef CONFIG_ARCH_CHIP_STM32G0 +# define FLASH_DUAL_BANK 1 +# define FLASH_BANK2_BASE 0x08040000 +# endif +#else +# error "Invalid flash configuration defined" +#endif + +#ifdef FLASH_DUAL_BANK +# define FLASH_BANKSIZE (FLASH_NBLOCKS * FLASH_BLOCK_SIZE / 2) +# define FLASH_SR_BSY (FLASH_SR_BSY1 | FLASH_SR_BSY2) +#else +# define FLASH_BANKSIZE (FLASH_NBLOCKS * FLASH_BLOCK_SIZE) +# define FLASH_SR_BSY (FLASH_SR_BSY1) +#endif + +/* Dual bank G0B1 MCUs have a non-linear mapping of block number between + * banks. Bank 2 starts at block number 256, even if bank 1 ends at 63 + * or 127. + */ + +#define FLASH_BANK2_START_BLOCKNUM 256 + +#define FLASH_TOTALSIZE (FLASH_NBLOCKS * FLASH_BLOCK_SIZE) +#define FLASH_NPAGES (FLASH_NBLOCKS * FLASH_BLOCK_SIZE / FLASH_PAGE_SIZE) +#define FLASH_KEY1 0x45670123 +#define FLASH_KEY2 0xcdef89ab +#define FLASH_OPTKEY1 0x08192a3b +#define FLASH_OPTKEY2 0x4c5d6e7f +#define FLASH_ERASEDVALUE 0xffu +#define FLASH_ERASEDVALUE_DW 0xffffffffu + +#define FLASH_TIMEOUT 5000000 /* 5s */ + +#define FLASH_SR_CLEAR_ERROR_FLAGS (FLASH_SR_OPERR|FLASH_SR_PROGERR|FLASH_SR_WRPERR|\ + FLASH_SR_PGAERR|FLASH_SR_SIZERR|FLASH_SR_PGSERR|\ + FLASH_SR_MISSERR|FLASH_SR_FASTERR|FLASH_SR_RDERR|FLASH_SR_OPTVERR) + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +struct stm32_flash_priv_s +{ + uint32_t base; /* FLASH base address */ + uint32_t stblock; /* The first block number */ + uint32_t stpage; /* The first page number */ +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +static void flash_unlock_cr(void); +static void flash_lock_cr(void); +static bool flash_unlock_opt(void); +static void flash_lock_opt(void); +static int flash_israngeerased(size_t startaddress, size_t size); +static inline struct stm32_flash_priv_s *flash_bank(size_t address); +static int flash_wait_for_operation(void); +static int flash_verify_blocknum(size_t block); +static uint32_t flash_block_address(size_t block); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static struct stm32_flash_priv_s flash_bank1_priv = +{ + .base = STM32_FLASH_BASE, + .stblock = 0, + .stpage = 0 +}; + +#ifdef FLASH_DUAL_BANK +static struct stm32_flash_priv_s flash_bank2_priv = +{ + .base = FLASH_BANK2_BASE, + .stblock = FLASH_BANK2_START_BLOCKNUM, + .stpage = (FLASH_NPAGES / 2) +}; +#endif + +static mutex_t g_lock = NXMUTEX_INITIALIZER; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: flash_bank + * + * Description: + * Returns the priv pointer to the correct bank + * + ****************************************************************************/ + +static inline struct stm32_flash_priv_s *flash_bank(size_t address) +{ + struct stm32_flash_priv_s *priv = NULL; + + if (address >= flash_bank1_priv.base && + address < flash_bank1_priv.base + FLASH_BANKSIZE) + { + priv = &flash_bank1_priv; + } +#ifdef FLASH_DUAL_BANK + else if (address >= flash_bank2_priv.base && + address < flash_bank2_priv.base + FLASH_BANKSIZE) + { + priv = &flash_bank2_priv; + } +#endif + + return priv; +} + +/**************************************************************************** + * Name: flash_israngeerased + * + * Description: + * Returns count of non-erased words + * + ****************************************************************************/ + +static int flash_israngeerased(size_t startaddress, size_t size) +{ + uint32_t *addr; + uint8_t *baddr; + size_t count = 0; + size_t bwritten = 0; + + if (!flash_bank(startaddress) || !flash_bank(startaddress + size - 1)) + { + return -EIO; + } + + addr = (uint32_t *)startaddress; + + while (count + 4 <= size) + { + if (getreg32(addr) != FLASH_ERASEDVALUE_DW) + { + bwritten++; + } + + addr++; + count += 4; + } + + baddr = (uint8_t *)addr; + + while (count < size) + { + if (getreg8(baddr) != FLASH_ERASEDVALUE) + { + /* Technically counting more than once per word but OK since + * anything that is non-zero is a failure anyways. + */ + + bwritten++; + } + + baddr++; + count++; + } + + return bwritten; +} + +/**************************************************************************** + * Name: flash_wait_for_operation() + * + * Description: + * Wait for last write/erase operation to finish + * Return error in case of timeout + * + * Returned Value: + * Zero or error value + * + * -EBUSY: Timeout while waiting for previous write/erase operation to + * complete + * + ****************************************************************************/ + +static int flash_wait_for_operation(void) +{ + int i; + bool timeout = true; + + UP_DSB(); + + for (i = 0; i < FLASH_TIMEOUT; i += 10) + { + if (!(getreg32(STM32_FLASH_SR) & (FLASH_SR_CFGBSY | FLASH_SR_BSY))) + { + timeout = false; + break; + } + + up_udelay(10); + } + + if (timeout) + { + return -EBUSY; + } + + return 0; +} + +/**************************************************************************** + * Name: flash_unlock_cr + * + * Description: + * Unlock flash control register, if it is not already unlocked. + * + ****************************************************************************/ + +static void flash_unlock_cr(void) +{ + /* FLASH_CR cannot be written when BSY1 flag set */ + + while (getreg32(STM32_FLASH_SR) & (FLASH_SR_BSY1 | FLASH_SR_CFGBSY)) + { + } + + if (getreg32(STM32_FLASH_CR) & FLASH_CR_LOCK) + { + putreg32(FLASH_KEY1, STM32_FLASH_KEYR); + putreg32(FLASH_KEY2, STM32_FLASH_KEYR); + } + + DEBUGASSERT((getreg32(STM32_FLASH_CR) & FLASH_CR_LOCK) == 0); +} + +/**************************************************************************** + * Name: flash_lock_cr + * + * Description: + * Lock flash control register. + * + ****************************************************************************/ + +static void flash_lock_cr(void) +{ + modifyreg32(STM32_FLASH_CR, 0, FLASH_CR_LOCK); +} + +/**************************************************************************** + * Name: flash_unlock_opt + * + * Description: + * Unlock flash option bytes register, if it is not already unlocked. + * + ****************************************************************************/ + +static bool flash_unlock_opt(void) +{ + bool was_locked = false; + flash_unlock_cr(); + + if (getreg32(STM32_FLASH_CR) & FLASH_CR_OPTLOCK) + { + was_locked = true; + + putreg32(FLASH_OPTKEY1, STM32_FLASH_OPTKEYR); + putreg32(FLASH_OPTKEY2, STM32_FLASH_OPTKEYR); + } + + DEBUGASSERT((getreg32(STM32_FLASH_CR) & FLASH_CR_OPTLOCK) == 0); + + return was_locked; +} + +/**************************************************************************** + * Name: flash_lock_opt + * + * Description: + * Lock flash option bytes register. + * + ****************************************************************************/ + +static void flash_lock_opt(void) +{ + modifyreg32(STM32_FLASH_CR, 0, FLASH_CR_OPTLOCK); +} + +/**************************************************************************** + * Name: flash_verify_blocknum + * + * Description: + * Verify the provided block number is valid based on the flash + * configuration. This is done because the reference implementation and + * reference manual refer to non-contiguous block (page) numbers for the + * flash layout on dual-bank devices. + * + * Returned Value: + * Zero or negated errno value. + * + * -EFAULT: Block number provided falls outside of the ranges specified in + * reference manual. + * + ****************************************************************************/ + +static int flash_verify_blocknum(size_t block) +{ +#ifdef FLASH_DUAL_BANK +#if defined(CONFIG_STM32_FLASH_CONFIG_C) + if ((block < 0 || block > 63) && (block < 256 || block > 319)) + { + return -EFAULT; + } +#elif defined(CONFIG_STM32_FLASH_CONFIG_E) + if ((block < 0 || block > 127) && (block < 256 || block > 383)) + { + return -EFAULT; + } +#else +# error "Dual bank flash config not supported by flash driver" +#endif +#else + if (block > FLASH_NBLOCKS) + { + return -EFAULT; + } +#endif + + return 0; +} + +/**************************************************************************** + * Name: flash_block_address + * + * Description: + * Find the start address for the given block number. + * + * Returned Value: + * Memory address corresponding to given block number. + * + * Assumptions: + * This function assumes the block number has already been verified. Take + * care to make sure the block number is valid for the specific chip using + * flash_verify_blocknum() first. + * + ****************************************************************************/ + +static uint32_t flash_block_address(size_t block) +{ + uint32_t addr; +#ifdef FLASH_DUAL_BANK + if (block >= flash_bank2_priv.stblock) + { + addr = flash_bank2_priv.base + + (block - flash_bank2_priv.stblock) * FLASH_BLOCK_SIZE; + } + else + { + addr = flash_bank1_priv.base + block * FLASH_BLOCK_SIZE; + } +#else + addr = flash_bank1_priv.base + block * FLASH_BLOCK_SIZE; +#endif + return addr; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_flash_unlock + * + * Description: + * Unlock flash control register (FLASH_CR) + * + ****************************************************************************/ + +void stm32_flash_unlock(void) +{ + nxmutex_lock(&g_lock); + flash_unlock_cr(); + nxmutex_unlock(&g_lock); +} + +/**************************************************************************** + * Name: stm32_flash_lock + * + * Description: + * Lock flash control register (FLASH_CR) + * + ****************************************************************************/ + +void stm32_flash_lock(void) +{ + nxmutex_lock(&g_lock); + flash_lock_cr(); + nxmutex_unlock(&g_lock); +} + +/**************************************************************************** + * Name: stm32_flash_getopt + * + * Description: + * Read the current flash option bytes from FLASH_OPTR + * + * Input Parameters: + * opt - location to store read of FLASH_OPTR + * + ****************************************************************************/ + +void stm32_flash_getopt(uint32_t *opt) +{ + *opt = getreg32(STM32_FLASH_OPTR); +} + +/**************************************************************************** + * Name: stm32_flash_optmodify + * + * Description: + * Modifies the current flash option bytes, given bits to set and clear. + * + * Input Parameters: + * clear - clear bits for FLASH_OPTR + * set - set bits for FLASH_OPTR + * + * Returned Value: + * Zero or error value + * + * -EBUSY: Timeout waiting for previous FLASH operation to occur, or + * there was data in the flash data buffer. + * + * Notes: + * This function WILL BLOCK and NOT release the thread. This is a sensitive + * operation with the potential to brick the device if interrupted. So, for + * the actual opt modify start, this function uses a tight while loop to + * wait for completion. + * + ****************************************************************************/ + +int stm32_flash_optmodify(uint32_t clear, uint32_t set) +{ + int ret; + bool was_locked; + + ret = flash_wait_for_operation(); + if (ret != 0) + { + return -EBUSY; + } + + was_locked = flash_unlock_opt(); + modifyreg32(STM32_FLASH_SR, 0, FLASH_SR_CLEAR_ERROR_FLAGS); + + modifyreg32(STM32_FLASH_OPTR, clear, set); + + while (getreg32(STM32_FLASH_SR) & FLASH_SR_BSY1) + { + } + + modifyreg32(STM32_FLASH_CR, 0, FLASH_CR_OPTSTRT); + + while (getreg32(STM32_FLASH_SR) & FLASH_SR_BSY1) + { + } + + if (was_locked) + { + flash_lock_opt(); + } + + return 0; +} + +#ifdef CONFIG_ARCH_HAVE_PROGMEM + +/* up_progmem_x functions defined in nuttx/include/nuttx/progmem.h + * + * Notes on Implementation: + * - The driver implementations DO NOT enforce memory address boundaries. + * For processors with less than 2MB flash, the user is responsible for + * not writing to memory between banks. + * + */ + +size_t up_progmem_pagesize(size_t page) +{ + return FLASH_PAGE_SIZE; +} + +ssize_t up_progmem_getpage(size_t addr) +{ + struct stm32_flash_priv_s *priv; + + priv = flash_bank(addr); + + if (priv == NULL) + { + return -EFAULT; + } + + return priv->stpage + ((addr - priv->base) / FLASH_PAGE_SIZE); +} + +size_t up_progmem_getaddress(size_t page) +{ + struct stm32_flash_priv_s *priv; + + if (page >= FLASH_NPAGES) + { + return SIZE_MAX; + } + + priv = flash_bank(STM32_FLASH_BASE + (page * FLASH_PAGE_SIZE)); + + if (!priv) + { + return SIZE_MAX; + } + + return priv->base + (page - priv->stpage) * FLASH_PAGE_SIZE; +} + +size_t up_progmem_neraseblocks(void) +{ + return FLASH_NBLOCKS; +} + +bool up_progmem_isuniform(void) +{ + /* So... Every other implementation of this in STM chips returns this as + * true. However, the description in include/nuttx/progmem.h states this to + * mean "does size of erase 'page' == size of read/write 'page'". Which is + * NOT true for most of these chips. + * + * On the G0, erase blocks are 2K and read/write page is 64 bit. + */ + + return false; +} + +ssize_t up_progmem_ispageerased(size_t page) +{ + size_t addr; + size_t count; + size_t bwritten = 0; + + if (page >= FLASH_NPAGES) + { + return -EFAULT; + } + + /* Verify */ + + for (addr = up_progmem_getaddress(page), count = up_progmem_pagesize(page); + count; count--, addr++) + { + if (getreg8(addr) != FLASH_ERASEDVALUE) + { + bwritten++; + } + } + + return bwritten; +} + +size_t up_progmem_erasesize(size_t block) +{ + return FLASH_BLOCK_SIZE; +} + +ssize_t up_progmem_eraseblock(size_t block) +{ + int ret; + size_t block_address; + + ret = flash_verify_blocknum(block); + if (ret < 0) + { + return -EFAULT; + } + + block_address = flash_block_address(block); + + ret = nxmutex_lock(&g_lock); + if (ret < 0) + { + return (ssize_t)ret; + } + + if (flash_wait_for_operation()) + { + ret = -EIO; + goto exit_with_lock; + } + + /* Get flash ready and begin erasing single block */ + + flash_unlock_cr(); + + modifyreg32(STM32_FLASH_SR, 0, FLASH_SR_CLEAR_ERROR_FLAGS); + + /* By now, know that the block number is valid and corresponds to a + * bank (if dual bank). So, don't need to verify that it is in bounds. + */ + +#ifdef FLASH_DUAL_BANK + + /* Note to future developers: The CR register definition in the reference + * manual [RM0444] is not clear on if bank selection is necessary. The PNB + * definition seems to imply that writing block numbers corresponding to + * bank 2 should just work. This is NOT the case. Writing 256 to PNB will + * cause block (page) 0 to be erased. Therefore, must switch BKER bit to + * match the correct bank. + */ + + if (block >= flash_bank2_priv.stblock) + { + modifyreg32(STM32_FLASH_CR, 0, FLASH_CR_BKER); + } + else + { + modifyreg32(STM32_FLASH_CR, FLASH_CR_BKER, 0); + } +#endif + + /* Setup erase parameters and start */ + + modifyreg32(STM32_FLASH_CR, FLASH_CR_PNB_MASK, + FLASH_CR_PER | (block << FLASH_CR_PNB_SHIFT)); + modifyreg32(STM32_FLASH_CR, 0, FLASH_CR_STRT); + + /* Wait for erase operation to complete */ + + if (flash_wait_for_operation()) + { + ret = -EIO; + goto exit_with_unlock; + } + + modifyreg32(STM32_FLASH_CR, FLASH_CR_PNB_MASK | FLASH_CR_PER, 0); + + ret = 0; + up_invalidate_dcache(block_address, block_address + FLASH_BLOCK_SIZE); + +exit_with_unlock: + flash_lock_cr(); + +exit_with_lock: + nxmutex_unlock(&g_lock); + + if (ret == 0 && + flash_israngeerased(block_address, up_progmem_erasesize(block)) == 0) + { + ret = up_progmem_erasesize(block); /* Success */ + } + else + { + ret = -EIO; + } + + return ret; +} + +ssize_t up_progmem_write(size_t addr, const void *buf, size_t count) +{ + struct stm32_flash_priv_s *priv; + uint32_t *fp; + uint32_t *rp; + uint32_t *ll = (uint32_t *)buf; + size_t faddr; + size_t written = count; + int ret; + const size_t pagesize = up_progmem_pagesize(0); /* 64-bit, 8 bytes per page */ + const size_t llperpage = pagesize / sizeof(uint32_t); + size_t pcount = count / pagesize; + + priv = flash_bank(addr); + + if (priv == NULL) + { + return -EFAULT; + } + + /* Check for valid address range */ + + if (addr < priv->base || + addr + count > priv->base + (FLASH_BANKSIZE)) + { + return -EFAULT; + } + + ret = nxmutex_lock(&g_lock); + if (ret < 0) + { + return (ssize_t)ret; + } + + /* Check address and count alignment */ + + DEBUGASSERT(!(addr % pagesize)); + DEBUGASSERT(!(count % pagesize)); + + if (flash_wait_for_operation()) + { + written = -EIO; + goto exit_with_lock; + } + + /* Get flash ready for write */ + + flash_unlock_cr(); + + modifyreg32(STM32_FLASH_SR, 0, FLASH_SR_CLEAR_ERROR_FLAGS); + modifyreg32(STM32_FLASH_CR, 0, FLASH_CR_PG); + + /* Write */ + + for (ll = (uint32_t *)buf, faddr = addr; pcount; + pcount -= 1, ll += llperpage, faddr += pagesize) + { + fp = (uint32_t *)faddr; + rp = ll; + + UP_MB(); + + /* Write 2 32 bit word and wait to complete */ + + *fp++ = *rp++; + *fp++ = *rp++; + + /* Data synchronous Barrier (DSB) just after the write operation. This + * will force the CPU to respect the sequence of instruction (no + * optimization). + */ + + UP_MB(); + + if (flash_wait_for_operation()) + { + written = -EIO; + goto exit_with_unlock; + } + + /* Future improvements may add ECC checking here (STM32G0 only). */ + } + + modifyreg32(STM32_FLASH_CR, FLASH_CR_PG, 0); + +exit_with_unlock: + flash_lock_cr(); + + if (written > 0) + { + for (ll = (uint32_t *)buf, faddr = addr, pcount = count / pagesize; + pcount; pcount -= 1, ll += llperpage, faddr += pagesize) + { + fp = (uint32_t *)faddr; + rp = ll; + + modifyreg32(STM32_FLASH_SR, 0, FLASH_SR_CLEAR_ERROR_FLAGS); + + if ((*fp++ != *rp++) || + (*fp++ != *rp++)) + { + written = -EIO; + break; + } + + /* Future improvements may add ECC checking here (STM32G0 only). */ + } + + modifyreg32(STM32_FLASH_SR, 0, FLASH_SR_CLEAR_ERROR_FLAGS); + } + +exit_with_lock: + nxmutex_unlock(&g_lock); + return written; +} + +uint8_t up_progmem_erasestate(void) +{ + return FLASH_ERASEDVALUE; +} + +#endif /* CONFIG_ARCH_HAVE_PROGMEM */ diff --git a/arch/arm/src/common/stm32/stm32_flash_m3m4_f1f3.c b/arch/arm/src/common/stm32/stm32_flash_m3m4_f1f3.c new file mode 100644 index 0000000000000..5bdb27b1ddc35 --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_flash_m3m4_f1f3.c @@ -0,0 +1,387 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_flash_m3m4_f1f3.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* Provides standard flash access functions, to be used by the flash mtd + * driver. The interface is defined in the include/nuttx/progmem.h + * + * Requirements during write/erase operations on FLASH: + * - HSI must be ON. + * - Low Power Modes are not permitted during write/erase + */ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include + +#include +#include +#include + +#include "stm32_flash.h" +#include "stm32_rcc.h" +#include "stm32_waste.h" +#include "arm_internal.h" + +/* Only for the STM32F[1|3]0xx family. */ + +#if defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F30XX) + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define FLASH_KEY1 0x45670123 +#define FLASH_KEY2 0xcdef89ab +#define FLASH_OPTKEY1 0x08192a3b +#define FLASH_OPTKEY2 0x4c5d6e7f +#define FLASH_ERASEDVALUE 0xffu + +#if defined(STM32_FLASH_DUAL_BANK) +/* Bank 0 is 512Kb; Bank 1 is up to 512Kb */ + +# define STM32_FLASH_BANK0_NPAGES (512 * 1024 / STM32_FLASH_PAGESIZE) +# define STM32_FLASH_BANK1_NPAGES (STM32_FLASH_NPAGES - STM32_FLASH_BANK0_NPAGES) +#else +/* Bank 0 is up to 512Kb; Bank 1 is not present */ + +# define STM32_FLASH_BANK0_NPAGES STM32_FLASH_NPAGES +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static mutex_t g_lock = NXMUTEX_INITIALIZER; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +static void flash_unlock(uintptr_t base) +{ + while ((getreg32(base + STM32_FLASH_SR_OFFSET) & FLASH_SR_BSY) != 0) + { + stm32_waste(); + } + + if ((getreg32(base + STM32_FLASH_CR_OFFSET) & FLASH_CR_LOCK) != 0) + { + /* Unlock sequence */ + + putreg32(FLASH_KEY1, base + STM32_FLASH_KEYR_OFFSET); + putreg32(FLASH_KEY2, base + STM32_FLASH_KEYR_OFFSET); + } +} + +static void flash_lock(uintptr_t base) +{ + modifyreg32(base + STM32_FLASH_CR_OFFSET, 0, FLASH_CR_LOCK); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +int stm32_flash_unlock(void) +{ + int ret; + + ret = nxmutex_lock(&g_lock); + if (ret < 0) + { + return ret; + } + + flash_unlock(STM32_FLASHIF_BASE); +#if defined(STM32_FLASH_DUAL_BANK) + flash_unlock(STM32_FLASHIF1_BASE); +#endif + nxmutex_unlock(&g_lock); + + return ret; +} + +int stm32_flash_lock(void) +{ + int ret; + + ret = nxmutex_lock(&g_lock); + if (ret < 0) + { + return ret; + } + + flash_lock(STM32_FLASHIF_BASE); +#if defined(STM32_FLASH_DUAL_BANK) + flash_lock(STM32_FLASHIF1_BASE); +#endif + nxmutex_unlock(&g_lock); + + return ret; +} + +size_t up_progmem_pagesize(size_t page) +{ + return STM32_FLASH_PAGESIZE; +} + +size_t up_progmem_erasesize(size_t block) +{ + return STM32_FLASH_PAGESIZE; +} + +ssize_t up_progmem_getpage(size_t addr) +{ + if (addr >= STM32_FLASH_BASE) + { + addr -= STM32_FLASH_BASE; + } + + if (addr >= STM32_FLASH_SIZE) + { + return -EFAULT; + } + + return addr / STM32_FLASH_PAGESIZE; +} + +size_t up_progmem_getaddress(size_t page) +{ + if (page >= STM32_FLASH_NPAGES) + { + return SIZE_MAX; + } + + return page * STM32_FLASH_PAGESIZE + STM32_FLASH_BASE; +} + +size_t up_progmem_neraseblocks(void) +{ + return STM32_FLASH_NPAGES; +} + +bool up_progmem_isuniform(void) +{ +#ifdef STM32_FLASH_PAGESIZE + return true; +#else + return false; +#endif +} + +ssize_t up_progmem_ispageerased(size_t page) +{ + size_t addr; + size_t count; + size_t bwritten = 0; + + if (page >= STM32_FLASH_NPAGES) + { + return -EFAULT; + } + + /* Verify */ + + for (addr = up_progmem_getaddress(page), count = up_progmem_pagesize(page); + count; count--, addr++) + { + if (getreg8(addr) != FLASH_ERASEDVALUE) + { + bwritten++; + } + } + + return bwritten; +} + +ssize_t up_progmem_eraseblock(size_t block) +{ + uintptr_t base; + size_t page_address; + int ret; + + if (block >= STM32_FLASH_NPAGES) + { + return -EFAULT; + } + +#if defined(STM32_FLASH_DUAL_BANK) + /* Handle paged FLASH */ + + if (block >= STM32_FLASH_BANK0_NPAGES) + { + base = STM32_FLASHIF1_BASE; + } + else +#endif + { + base = STM32_FLASHIF_BASE; + } + + ret = nxmutex_lock(&g_lock); + if (ret < 0) + { + return (ssize_t)ret; + } + + if ((getreg32(STM32_RCC_CR) & RCC_CR_HSION) == 0) + { + nxmutex_unlock(&g_lock); + return -EPERM; + } + + /* Get flash ready and begin erasing single page */ + + flash_unlock(base); + + modifyreg32(base + STM32_FLASH_CR_OFFSET, 0, FLASH_CR_PER); + + /* Must be valid - page index checked above */ + + page_address = up_progmem_getaddress(block); + putreg32(page_address, base + STM32_FLASH_AR_OFFSET); + + modifyreg32(base + STM32_FLASH_CR_OFFSET, 0, FLASH_CR_STRT); + + while ((getreg32(base + STM32_FLASH_SR_OFFSET) & FLASH_SR_BSY) != 0) + { + stm32_waste(); + } + + modifyreg32(base + STM32_FLASH_CR_OFFSET, FLASH_CR_PER, 0); + nxmutex_unlock(&g_lock); + + /* Verify */ + + if (up_progmem_ispageerased(block) == 0) + { + return up_progmem_erasesize(block); /* success */ + } + else + { + return -EIO; /* failure */ + } +} + +ssize_t up_progmem_write(size_t addr, const void *buf, size_t count) +{ + uintptr_t base; + uint16_t *hword = (uint16_t *)buf; + size_t written = count; + int ret; + + /* STM32 requires half-word access */ + + if (count & 1) + { + return -EINVAL; + } + + /* Check for valid address range */ + + if (addr >= STM32_FLASH_BASE) + { + addr -= STM32_FLASH_BASE; + } + + if ((addr + count) > STM32_FLASH_SIZE) + { + return -EFAULT; + } + +#if defined(STM32_FLASH_DUAL_BANK) + /* Handle paged FLASH */ + + size_t page = addr / STM32_FLASH_PAGESIZE; + + if (page >= STM32_FLASH_BANK0_NPAGES) + { + base = STM32_FLASHIF1_BASE; + } + else +#endif + { + base = STM32_FLASHIF_BASE; + } + + ret = nxmutex_lock(&g_lock); + if (ret < 0) + { + return (ssize_t)ret; + } + + if ((getreg32(STM32_RCC_CR) & RCC_CR_HSION) == 0) + { + nxmutex_unlock(&g_lock); + return -EPERM; + } + + /* Get flash ready and begin flashing */ + + flash_unlock(base); + + modifyreg32(base + STM32_FLASH_CR_OFFSET, 0, FLASH_CR_PG); + + for (addr += STM32_FLASH_BASE; count; count -= 2, hword++, addr += 2) + { + /* Write half-word and wait to complete */ + + putreg16(*hword, addr); + + while ((getreg32(base + STM32_FLASH_SR_OFFSET) & FLASH_SR_BSY) != 0) + { + stm32_waste(); + } + + /* Verify */ + + if ((getreg32(base + STM32_FLASH_SR_OFFSET) & FLASH_SR_WRPRT_ERR) != 0) + { + modifyreg32(base + STM32_FLASH_CR_OFFSET, FLASH_CR_PG, 0); + nxmutex_unlock(&g_lock); + return -EROFS; + } + + if (getreg16(addr) != *hword) + { + modifyreg32(base + STM32_FLASH_CR_OFFSET, FLASH_CR_PG, 0); + nxmutex_unlock(&g_lock); + return -EIO; + } + } + + modifyreg32(base + STM32_FLASH_CR_OFFSET, FLASH_CR_PG, 0); + + nxmutex_unlock(&g_lock); + return written; +} + +uint8_t up_progmem_erasestate(void) +{ + return FLASH_ERASEDVALUE; +} + +#endif /* defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F30XX) */ diff --git a/arch/arm/src/common/stm32/stm32_flash_m3m4_f2f4.c b/arch/arm/src/common/stm32/stm32_flash_m3m4_f2f4.c new file mode 100644 index 0000000000000..afd7300dda0f3 --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_flash_m3m4_f2f4.c @@ -0,0 +1,452 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_flash_m3m4_f2f4.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* Provides standard flash access functions, to be used by the flash mtd + * driver. The interface is defined in the include/nuttx/progmem.h + * + * Requirements during write/erase operations on FLASH: + * - HSI must be ON. + * - Low Power Modes are not permitted during write/erase + */ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include + +#include +#include +#include + +#include "stm32_flash.h" +#include "stm32_rcc.h" +#include "stm32_waste.h" +#include "arm_internal.h" + +/* Only for the STM32F[2|4]0xx family. */ + +#if defined(CONFIG_STM32_HAVE_IP_FLASH_M3M4_F2F4) + +#if defined(CONFIG_STM32_FLASH_CONFIG_DEFAULT) +# warning "Default Flash Configuration Used - See Override Flash Size Designator" +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define FLASH_KEY1 0x45670123 +#define FLASH_KEY2 0xcdef89ab +#define FLASH_OPTKEY1 0x08192a3b +#define FLASH_OPTKEY2 0x4c5d6e7f +#define FLASH_ERASEDVALUE 0xff + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static mutex_t g_lock = NXMUTEX_INITIALIZER; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +static void flash_unlock(void) +{ + while (getreg32(STM32_FLASH_SR) & FLASH_SR_BSY) + { + stm32_waste(); + } + + if (getreg32(STM32_FLASH_CR) & FLASH_CR_LOCK) + { + /* Unlock sequence */ + + putreg32(FLASH_KEY1, STM32_FLASH_KEYR); + putreg32(FLASH_KEY2, STM32_FLASH_KEYR); + } +} + +static void flash_lock(void) +{ + modifyreg32(STM32_FLASH_CR, 0, FLASH_CR_LOCK); +} + +#if defined(CONFIG_STM32_FLASH_WORKAROUND_DATA_CACHE_CORRUPTION_ON_RWW) +static void data_cache_disable(void) +{ + modifyreg32(STM32_FLASH_ACR, FLASH_ACR_DCEN, 0); +} + +static void data_cache_enable(void) +{ + /* Reset data cache */ + + modifyreg32(STM32_FLASH_ACR, 0, FLASH_ACR_DCRST); + + /* Enable data cache */ + + modifyreg32(STM32_FLASH_ACR, 0, FLASH_ACR_DCEN); +} +#endif /* defined(CONFIG_STM32_FLASH_WORKAROUND_DATA_CACHE_CORRUPTION_ON_RWW) */ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +int stm32_flash_unlock(void) +{ + int ret; + + ret = nxmutex_lock(&g_lock); + if (ret < 0) + { + return ret; + } + + flash_unlock(); + nxmutex_unlock(&g_lock); + + return ret; +} + +int stm32_flash_lock(void) +{ + int ret; + + ret = nxmutex_lock(&g_lock); + if (ret < 0) + { + return ret; + } + + flash_lock(); + nxmutex_unlock(&g_lock); + + return ret; +} + +/**************************************************************************** + * Name: stm32_flash_writeprotect + * + * Description: + * Enable or disable the write protection of a flash sector. + * + ****************************************************************************/ + +int stm32_flash_writeprotect(size_t page, bool enabled) +{ + uint32_t reg; + uint32_t val; + + if (page >= STM32_FLASH_NPAGES) + { + return -EFAULT; + } + + /* Select the register that contains the bit to be changed */ + + if (page < 12) + { + reg = STM32_FLASH_OPTCR; + } +#if defined(CONFIG_STM32_FLASH_CONFIG_I) + else + { + reg = STM32_FLASH_OPTCR1; + page -= 12; + } +#else + else + { + return -EFAULT; + } +#endif + + /* Read the option status */ + + val = getreg32(reg); + + /* Set or clear the protection */ + + if (enabled) + { + val &= ~(1 << (16 + page)); + } + else + { + val |= (1 << (16 + page)); + } + + /* Unlock options */ + + putreg32(FLASH_OPTKEY1, STM32_FLASH_OPTKEYR); + putreg32(FLASH_OPTKEY2, STM32_FLASH_OPTKEYR); + + /* Write options */ + + putreg32(val, reg); + + /* Trigger programming */ + + modifyreg32(STM32_FLASH_OPTCR, 0, FLASH_OPTCR_OPTSTRT); + + /* Wait for completion */ + + while (getreg32(STM32_FLASH_SR) & FLASH_SR_BSY) + { + stm32_waste(); + } + + /* Relock options */ + + modifyreg32(STM32_FLASH_OPTCR, 0, FLASH_OPTCR_OPTLOCK); + return 0; +} + +size_t up_progmem_pagesize(size_t page) +{ + static const size_t page_sizes[STM32_FLASH_NPAGES] = STM32_FLASH_SIZES; + + if (page >= sizeof(page_sizes) / sizeof(*page_sizes)) + { + return 0; + } + else + { + return page_sizes[page]; + } +} + +size_t up_progmem_erasesize(size_t block) +{ + return up_progmem_pagesize(block); +} + +ssize_t up_progmem_getpage(size_t addr) +{ + size_t page_end = 0; + size_t i; + + if (addr >= STM32_FLASH_BASE) + { + addr -= STM32_FLASH_BASE; + } + + if (addr >= STM32_FLASH_SIZE) + { + return -EFAULT; + } + + for (i = 0; i < STM32_FLASH_NPAGES; ++i) + { + page_end += up_progmem_pagesize(i); + if (page_end > addr) + { + return i; + } + } + + return -EFAULT; +} + +size_t up_progmem_getaddress(size_t page) +{ + size_t base_address = STM32_FLASH_BASE; + size_t i; + + if (page >= STM32_FLASH_NPAGES) + { + return SIZE_MAX; + } + + for (i = 0; i < page; ++i) + { + base_address += up_progmem_pagesize(i); + } + + return base_address; +} + +size_t up_progmem_neraseblocks(void) +{ + return STM32_FLASH_NPAGES; +} + +bool up_progmem_isuniform(void) +{ +#ifdef STM32_FLASH_PAGESIZE + return true; +#else + return false; +#endif +} + +ssize_t up_progmem_ispageerased(size_t page) +{ + size_t addr; + size_t count; + size_t bwritten = 0; + + if (page >= STM32_FLASH_NPAGES) + { + return -EFAULT; + } + + /* Verify */ + + for (addr = up_progmem_getaddress(page), count = up_progmem_pagesize(page); + count; count--, addr++) + { + if (getreg8(addr) != FLASH_ERASEDVALUE) + { + bwritten++; + } + } + + return bwritten; +} + +ssize_t up_progmem_eraseblock(size_t block) +{ + if (block >= STM32_FLASH_NPAGES) + { + return -EFAULT; + } + + nxmutex_lock(&g_lock); + + /* Get flash ready and begin erasing single block */ + + flash_unlock(); + + modifyreg32(STM32_FLASH_CR, 0, FLASH_CR_SER); + modifyreg32(STM32_FLASH_CR, FLASH_CR_SNB_MASK, FLASH_CR_SNB(block)); + modifyreg32(STM32_FLASH_CR, 0, FLASH_CR_STRT); + + while (getreg32(STM32_FLASH_SR) & FLASH_SR_BSY) + { + stm32_waste(); + } + + modifyreg32(STM32_FLASH_CR, FLASH_CR_SER, 0); + nxmutex_unlock(&g_lock); + + /* Verify */ + + if (up_progmem_ispageerased(block) == 0) + { + return up_progmem_pagesize(block); /* success */ + } + else + { + return -EIO; /* failure */ + } +} + +ssize_t up_progmem_write(size_t addr, const void *buf, size_t count) +{ + uint16_t *hword = (uint16_t *)buf; + size_t written = count; + + /* STM32 requires half-word access */ + + if (count & 1) + { + return -EINVAL; + } + + /* Check for valid address range */ + + if (addr >= STM32_FLASH_BASE) + { + addr -= STM32_FLASH_BASE; + } + + if ((addr + count) > STM32_FLASH_SIZE) + { + return -EFAULT; + } + + nxmutex_lock(&g_lock); + + /* Get flash ready and begin flashing */ + + flash_unlock(); + +#if defined(CONFIG_STM32_FLASH_WORKAROUND_DATA_CACHE_CORRUPTION_ON_RWW) + data_cache_disable(); +#endif + + modifyreg32(STM32_FLASH_CR, 0, FLASH_CR_PG); + + /* TODO: implement up_progmem_write() to support other sizes than 16-bits */ + + modifyreg32(STM32_FLASH_CR, FLASH_CR_PSIZE_MASK, FLASH_CR_PSIZE_X16); + + for (addr += STM32_FLASH_BASE; count; count -= 2, hword++, addr += 2) + { + /* Write half-word and wait to complete */ + + putreg16(*hword, addr); + + while (getreg32(STM32_FLASH_SR) & FLASH_SR_BSY) + { + stm32_waste(); + } + + /* Verify */ + + if (getreg32(STM32_FLASH_SR) & FLASH_CR_SER) + { + modifyreg32(STM32_FLASH_CR, FLASH_CR_PG, 0); + nxmutex_unlock(&g_lock); + return -EROFS; + } + + if (getreg16(addr) != *hword) + { + modifyreg32(STM32_FLASH_CR, FLASH_CR_PG, 0); + nxmutex_unlock(&g_lock); + return -EIO; + } + } + + modifyreg32(STM32_FLASH_CR, FLASH_CR_PG, 0); + +#if defined(CONFIG_STM32_FLASH_WORKAROUND_DATA_CACHE_CORRUPTION_ON_RWW) + data_cache_enable(); +#endif + + nxmutex_unlock(&g_lock); + return written; +} + +uint8_t up_progmem_erasestate(void) +{ + return FLASH_ERASEDVALUE; +} + +#endif /* defined(CONFIG_STM32_HAVE_IP_FLASH_M3M4_F2F4) */ diff --git a/arch/arm/src/common/stm32/stm32_flash_m3m4_g4.c b/arch/arm/src/common/stm32/stm32_flash_m3m4_g4.c new file mode 100644 index 0000000000000..f2d722e4799d2 --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_flash_m3m4_g4.c @@ -0,0 +1,618 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_flash_m3m4_g4.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* Provides standard flash access functions, to be used by the flash mtd + * driver. The interface is defined in the include/nuttx/progmem.h + * + * Notes about this implementation: + * - HSI16 is automatically turned ON by MCU, if not enabled beforehand + * - Only Standard Programming is supported, no Fast Programming. + * - Low Power Modes are not permitted during write/erase + */ + +/* Differences vs STM32L4 (used as template): + * 1. FLASH_CR - Bits (29:28) (SEC_PROT2, SEC_PROT1) added. + * 2. FLASH_ECCR - Bits (29:28) (ECCD2, ECCC2) added. + * Note: Bits are set by hardware. Nothing to do + * 3. FLASH_OPTR - + * a. DUALBANK moved from bit 21 to 22. + * b. NRST_MODE added - Bits 29:28 + * c. IRHEN added - Bit 30 + * 4. FLASH_SEC1R - (New) Secure Area Bank 1 Register + * a. BOOT_LOCK - Forces boot from user flash area + * b. SEC_SIZE1[7:0] - Starts at 0x80000000, size = SEC_SIZE1 * page_size + * 5. FLASH_SEC2R - (New) Secure Area Bank 2 Register + * a. BOOT_LOCK - Forces boot from user flash area + * b. SEC_SIZE1[7:0] - Starts at 0x80000000, size = SEC_SIZE1 * page_size + * 6. FLASH_PAGE_SIZE - The page size of the STM32G47XX and STM32G48XX + * is dependent on the DBANK bit. If Dual Banks are used, the page size + * is 2K. If a single bank is used, the page size is 4K. + */ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#include "stm32_rcc.h" +#include "stm32_waste.h" +#include "stm32_flash.h" +#include "arm_internal.h" + +#if !(defined(CONFIG_STM32_STM32G43XX) || defined(CONFIG_STM32_STM32G47XX) || \ + defined(CONFIG_STM32_STM32G48XX) || defined(CONFIG_STM32_STM32G49XX)) +# error "Unrecognized STM32 chip" +#endif + +#if !defined(CONFIG_STM32_FLASH_CONFIG_DEFAULT) +# warning "Flash Configuration has been overridden - make sure it is correct" +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define FLASH_KEY1 0x45670123 +#define FLASH_KEY2 0xCDEF89AB +#define FLASH_ERASEDVALUE 0xffu + +#define OPTBYTES_KEY1 0x08192A3B +#define OPTBYTES_KEY2 0x4C5D6E7F + +#define FLASH_CR_PAGE_ERASE FLASH_CR_PER +#define FLASH_SR_WRITE_PROTECTION_ERROR FLASH_SR_WRPERR + +/* All errors for Standard Programming, not for other operations. */ + +#define FLASH_SR_ALLERRS (FLASH_SR_PGSERR | FLASH_SR_SIZERR | \ + FLASH_SR_PGAERR | FLASH_SR_WRPERR | \ + FLASH_SR_PROGERR) + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static mutex_t g_lock = NXMUTEX_INITIALIZER; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +static uint32_t get_flash_page_size(void) +{ +#if defined(CONFIG_STM32_STM32G47XX) || defined(CONFIG_STM32_STM32G48XX) + if (getreg32(STM32_FLASH_OPTR) & FLASH_OPTR_DBANK) + { + return 2048; + } + else + { + return 4096; + } +#else + return STM32_FLASH_PAGESIZE; +#endif +} + +static uint32_t get_flash_npages(void) +{ +#if defined(CONFIG_STM32_STM32G47XX) || defined(CONFIG_STM32_STM32G48XX) + if (getreg32(STM32_FLASH_OPTR) & FLASH_OPTR_DBANK) + { + return STM32_FLASH_SIZE / 2048; + } + else + { + return STM32_FLASH_SIZE / 4096; + } +#else + return STM32_FLASH_NPAGES; +#endif +} + +static void flash_unlock(void) +{ + while (getreg32(STM32_FLASH_SR) & FLASH_SR_BSY) + { + stm32_waste(); + } + + if (getreg32(STM32_FLASH_CR) & FLASH_CR_LOCK) + { + /* Unlock sequence */ + + putreg32(FLASH_KEY1, STM32_FLASH_KEYR); + putreg32(FLASH_KEY2, STM32_FLASH_KEYR); + } +} + +static void flash_lock(void) +{ + modifyreg32(STM32_FLASH_CR, 0, FLASH_CR_LOCK); +} + +static void flash_optbytes_unlock(void) +{ + flash_unlock(); + + if (getreg32(STM32_FLASH_CR) & FLASH_CR_OPTLOCK) + { + /* Unlock Option Bytes sequence */ + + putreg32(OPTBYTES_KEY1, STM32_FLASH_OPTKEYR); + putreg32(OPTBYTES_KEY2, STM32_FLASH_OPTKEYR); + } +} + +static inline void flash_optbytes_lock(void) +{ + /* We don't need to set OPTLOCK here as it is automatically + * set by MCU when flash_lock() sets LOCK. + */ + + flash_lock(); +} + +static inline void flash_erase(size_t page) +{ + finfo("erase page %u\n", page); + + modifyreg32(STM32_FLASH_CR, 0, FLASH_CR_PAGE_ERASE); + + modifyreg32(STM32_FLASH_CR, FLASH_CR_PNB_MASK, + FLASH_CR_PNB(page)); + +#if (defined(CONFIG_STM32_STM32G47XX) || \ + defined(CONFIG_STM32_STM32G48XX)) + uint32_t half_npages = get_flash_npages() / 2; + + if (getreg32(STM32_FLASH_OPTR) & FLASH_OPTR_DBANK) + { + if (page < half_npages) + { + /* Select bank 1 */ + + modifyreg32(STM32_FLASH_CR, FLASH_CR_BKER, 0); + } + else + { + /* Select bank 2 */ + + modifyreg32(STM32_FLASH_CR, 0, FLASH_CR_BKER); + } + } +#endif + + modifyreg32(STM32_FLASH_CR, 0, FLASH_CR_START); + + while (getreg32(STM32_FLASH_SR) & FLASH_SR_BSY) + { + stm32_waste(); + } + + modifyreg32(STM32_FLASH_CR, FLASH_CR_PAGE_ERASE, 0); +} + +#if defined(CONFIG_STM32_FLASH_WORKAROUND_DATA_CACHE_CORRUPTION_ON_RWW) +static void data_cache_disable(void) +{ + modifyreg32(STM32_FLASH_ACR, FLASH_ACR_DCEN, 0); +} + +static void data_cache_enable(void) +{ + /* Reset data cache */ + + modifyreg32(STM32_FLASH_ACR, 0, FLASH_ACR_DCRST); + + /* Enable data cache */ + + modifyreg32(STM32_FLASH_ACR, 0, FLASH_ACR_DCEN); +} +#endif /* defined(CONFIG_STM32_FLASH_WORKAROUND_DATA_CACHE_CORRUPTION_ON_RWW) */ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +int stm32_flash_unlock(void) +{ + int ret; + + ret = nxmutex_lock(&g_lock); + if (ret < 0) + { + return ret; + } + + flash_unlock(); + nxmutex_unlock(&g_lock); + + return ret; +} + +int stm32_flash_lock(void) +{ + int ret; + + ret = nxmutex_lock(&g_lock); + if (ret < 0) + { + return ret; + } + + flash_lock(); + nxmutex_unlock(&g_lock); + + return ret; +} + +uint32_t stm32_flash_user_optbytes(uint32_t clrbits, uint32_t setbits) +{ + uint32_t regval; + int ret; + + /* To avoid accidents, do not allow setting RDP via this function. + * Remove these asserts if want to enable changing the protection level. + * WARNING: level 2 protection is permanent! + */ + + DEBUGASSERT((clrbits & FLASH_OPTR_RDP_MASK) == 0); + DEBUGASSERT((setbits & FLASH_OPTR_RDP_MASK) == 0); + + ret = nxmutex_lock(&g_lock); + if (ret < 0) + { + return 0; + } + + flash_optbytes_unlock(); + + /* Modify Option Bytes in register. */ + + regval = getreg32(STM32_FLASH_OPTR); + + finfo("Flash option bytes before: 0x%" PRIx32 "\n", regval); + + regval = (regval & ~clrbits) | setbits; + + putreg32(regval, STM32_FLASH_OPTR); + + finfo("Flash option bytes after: 0x%" PRIx32 "\n", regval); + + /* Start Option Bytes programming and wait for completion. */ + + modifyreg32(STM32_FLASH_CR, 0, FLASH_CR_OPTSTRT); + + while (getreg32(STM32_FLASH_SR) & FLASH_SR_BSY) + { + stm32_waste(); + } + + flash_optbytes_lock(); + nxmutex_unlock(&g_lock); + + return regval; +} + +size_t up_progmem_pagesize(size_t page) +{ + return get_flash_page_size(); +} + +size_t up_progmem_erasesize(size_t block) +{ + return get_flash_page_size(); +} + +ssize_t up_progmem_getpage(size_t addr) +{ + if (addr >= STM32_FLASH_BASE) + { + addr -= STM32_FLASH_BASE; + } + + if (addr >= STM32_FLASH_SIZE) + { + return -EFAULT; + } + + return addr / get_flash_page_size(); +} + +size_t up_progmem_getaddress(size_t page) +{ + if (page >= get_flash_npages()) + { + return SIZE_MAX; + } + + return page * get_flash_page_size() + STM32_FLASH_BASE; +} + +size_t up_progmem_neraseblocks(void) +{ + return get_flash_npages(); +} + +bool up_progmem_isuniform(void) +{ + return true; +} + +ssize_t up_progmem_eraseblock(size_t block) +{ + int ret; + + if (block >= get_flash_npages()) + { + return -EFAULT; + } + + /* Erase single block */ + + ret = nxmutex_lock(&g_lock); + if (ret < 0) + { + return (ssize_t)ret; + } + + flash_unlock(); + + flash_erase(block); + + flash_lock(); + nxmutex_unlock(&g_lock); + + /* Verify */ + + if (up_progmem_ispageerased(block) == 0) + { + return up_progmem_erasesize(block); + } + else + { + return -EIO; + } +} + +ssize_t up_progmem_ispageerased(size_t page) +{ + size_t addr; + size_t count; + size_t bwritten = 0; + + if (page >= get_flash_npages()) + { + return -EFAULT; + } + + /* Verify */ + + for (addr = up_progmem_getaddress(page), count = up_progmem_pagesize(page); + count; count--, addr++) + { + if (getreg8(addr) != FLASH_ERASEDVALUE) + { + bwritten++; + } + } + + return bwritten; +} + +ssize_t up_progmem_write(size_t addr, const void *buf, size_t buflen) +{ + uint32_t *dest; + const uint32_t *src; + size_t written; + size_t xfrsize; + size_t offset; + size_t page; + bool set_pg_bit = false; + int i; + int ret = OK; + const uint32_t flash_page_size = get_flash_page_size(); + const uint32_t flash_page_words = flash_page_size / 4; + const uint32_t flash_page_mask = flash_page_size - 1; + uint32_t *page_buffer = NULL; + + /* Check for valid address range. */ + + offset = addr; + if (addr >= STM32_FLASH_BASE) + { + offset -= STM32_FLASH_BASE; + } + + if (offset + buflen > STM32_FLASH_SIZE) + { + return -EFAULT; + } + + /* Get the page number corresponding to the flash offset and the byte + * offset into the page. Align write destination to page boundary. + */ + + if (flash_page_size == 4096) + { + page = ((uint32_t)offset >> 12); + } + else + { + page = ((uint32_t)offset >> 11); + } + + offset &= flash_page_mask; + + dest = (uint32_t *)((uint8_t *)addr - offset); + written = 0; + + ret = nxmutex_lock(&g_lock); + if (ret < 0) + { + return (ssize_t)ret; + } + + /* Get flash ready and begin flashing. */ + + flash_unlock(); + + /* Loop until all of the data has been written */ + + while (buflen > 0) + { + /* How much can we write into this page? */ + + xfrsize = MIN((size_t) flash_page_size - offset, buflen); + + /* Do we need to use the intermediate buffer? */ + + if (offset == 0 && xfrsize == flash_page_size) + { + /* No, we can take the data directly from the user buffer */ + + src = (const uint32_t *)buf; + } + else + { + /* Yes, copy data into the page buffer */ + + page_buffer = malloc(flash_page_size); + + if (offset > 0) + { + memcpy(page_buffer, dest, offset); + } + + memcpy((uint8_t *)page_buffer + offset, buf, xfrsize); + + if (offset + xfrsize < flash_page_size) + { + memcpy((uint8_t *)page_buffer + offset + xfrsize, + (const uint8_t *)dest + offset + xfrsize, + flash_page_size - offset - xfrsize); + } + + src = page_buffer; + } + + /* Erase the page. Unlike most flash chips, STM32 is unable to + * write back existing data read from page without erase. + */ + + flash_erase(page); + + /* Write the page. Must be with double-words. */ + +#if defined(CONFIG_STM32_FLASH_WORKAROUND_DATA_CACHE_CORRUPTION_ON_RWW) + data_cache_disable(); +#endif + + modifyreg32(STM32_FLASH_CR, 0, FLASH_CR_PG); + set_pg_bit = true; + + for (i = 0; i < flash_page_words; i += 2) + { + *dest++ = *src++; + *dest++ = *src++; + + while (getreg32(STM32_FLASH_SR) & FLASH_SR_BSY) + { + stm32_waste(); + } + + /* Verify */ + + if (getreg32(STM32_FLASH_SR) & FLASH_SR_WRITE_PROTECTION_ERROR) + { + ret = -EROFS; + goto out; + } + + if (getreg32(dest -1) != *(src - 1) || + getreg32(dest - 2) != *(src - 2)) + { + ret = -EIO; + goto out; + } + } + + modifyreg32(STM32_FLASH_CR, FLASH_CR_PG, 0); + set_pg_bit = false; + +#if defined(CONFIG_STM32_FLASH_WORKAROUND_DATA_CACHE_CORRUPTION_ON_RWW) + data_cache_enable(); +#endif + + /* Adjust pointers and counts for the next time through the loop */ + + written += xfrsize; + addr += xfrsize; + dest = (uint32_t *)addr; + buf = (void *)((uintptr_t)buf + xfrsize); + buflen -= xfrsize; + page++; + } + +out: + if (set_pg_bit) + { + modifyreg32(STM32_FLASH_CR, FLASH_CR_PG, 0); +#if defined(CONFIG_STM32_FLASH_WORKAROUND_DATA_CACHE_CORRUPTION_ON_RWW) + data_cache_enable(); +#endif + } + + /* If there was an error, clear all error flags in status register (rc_w1 + * register so do this by writing the error bits). + */ + + if (ret != OK) + { + ferr("flash write error: %d, status: 0x%" PRIx32 "\n", + ret, getreg32(STM32_FLASH_SR)); + + modifyreg32(STM32_FLASH_SR, 0, FLASH_SR_ALLERRS); + } + + free(page_buffer); + flash_lock(); + nxmutex_unlock(&g_lock); + return (ret == OK) ? written : ret; +} + +uint8_t up_progmem_erasestate(void) +{ + return FLASH_ERASEDVALUE; +} diff --git a/arch/arm/src/common/stm32/stm32_flash_m3m4_l1.c b/arch/arm/src/common/stm32/stm32_flash_m3m4_l1.c new file mode 100644 index 0000000000000..ec1379498f4a7 --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_flash_m3m4_l1.c @@ -0,0 +1,558 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_flash_m3m4_l1.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* Provides standard flash access functions, to be used by the + * flash mtd driver. + * The interface is defined in the include/nuttx/progmem.h + * + * Requirements during write/erase operations on FLASH: + * - HSI must be ON. + * - Low Power Modes are not permitted during write/erase + */ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include + +#include +#include +#include +#include +#include + +#include "stm32_flash.h" +#include "stm32_rcc.h" +#include "stm32_waste.h" +#include "arm_internal.h" + +/* Only for the STM32L15xx family. */ + +#if defined(CONFIG_STM32_STM32L15XX) + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define FLASH_KEY1 0x8c9daebf +#define FLASH_KEY2 0x13141516 +#define FLASH_OPTKEY1 0xfbead9c8 +#define FLASH_OPTKEY2 0x24252627 +#define EEPROM_KEY1 0x89abcdef +#define EEPROM_KEY2 0x02030405 + +#define FLASH_SR_WRITE_PROTECTION_ERROR FLASH_SR_WRPERR +#define FLASH_SR_ALLERRS (FLASH_SR_RDERR | FLASH_SR_SIZERR | \ + FLASH_SR_PGAERR | FLASH_SR_WRPERR) + +/* STM32L1 internal flash is based on EEPROM-technology while most others + * are NOR-flash, thus many things are different including the erase value. + */ + +#define FLASH_ERASEDVALUE 0x00 + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static mutex_t g_lock = NXMUTEX_INITIALIZER; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +static void stm32_eeprom_unlock(void) +{ + while (getreg32(STM32_FLASH_SR) & FLASH_SR_BSY) + { + stm32_waste(); + } + + if (getreg32(STM32_FLASH_PECR) & FLASH_PECR_PELOCK) + { + /* Unlock sequence */ + + putreg32(EEPROM_KEY1, STM32_FLASH_PEKEYR); + putreg32(EEPROM_KEY2, STM32_FLASH_PEKEYR); + } +} + +static void stm32_eeprom_lock(void) +{ + modifyreg32(STM32_FLASH_PECR, 0, FLASH_PECR_PELOCK); +} + +static void flash_unlock(void) +{ + if (getreg32(STM32_FLASH_PECR) & FLASH_PECR_PRGLOCK) + { + stm32_eeprom_unlock(); + + /* Unlock sequence */ + + putreg32(FLASH_KEY1, STM32_FLASH_PRGKEYR); + putreg32(FLASH_KEY2, STM32_FLASH_PRGKEYR); + } +} + +static void flash_lock(void) +{ + modifyreg32(STM32_FLASH_PECR, 0, FLASH_PECR_PRGLOCK); + stm32_eeprom_lock(); +} + +static ssize_t stm32_eeprom_erase_write(size_t addr, const void *buf, + size_t buflen) +{ + const char *cbuf = buf; + size_t i; + + if (buflen == 0) + { + return 0; + } + + /* Check for valid address range */ + + if (addr >= STM32_EEPROM_BASE) + { + addr -= STM32_EEPROM_BASE; + } + + if (addr >= STM32_EEPROM_SIZE) + { + return -EINVAL; + } + + /* TODO: Voltage range must be range 1 or 2. Erase/program not allowed in + * range 3. + */ + + stm32_eeprom_unlock(); + + /* Clear pending status flags. */ + + putreg32(FLASH_SR_WRPERR | FLASH_SR_PGAERR | + FLASH_SR_SIZERR | FLASH_SR_OPTVERR | + FLASH_SR_OPTVERRUSR | FLASH_SR_RDERR, STM32_FLASH_SR); + + /* Enable automatic erasing (by disabling 'fixed time' programming). */ + + modifyreg32(STM32_FLASH_PECR, FLASH_PECR_FTDW, 0); + + /* Write buffer to EEPROM data memory. */ + + addr += STM32_EEPROM_BASE; + i = 0; + while (i < buflen) + { + uint32_t writeval; + size_t left = buflen - i; + + if ((addr & 0x03) == 0x00 && left >= 4) + { + /* Read/erase/write word */ + + writeval = cbuf ? *(uint32_t *)cbuf : 0; + putreg32(writeval, addr); + } + else if ((addr & 0x01) == 0x00 && left >= 2) + { + /* Read/erase/write half-word */ + + writeval = cbuf ? *(uint16_t *)cbuf : 0; + putreg16(writeval, addr); + } + else + { + /* Read/erase/write byte */ + + writeval = cbuf ? *(uint8_t *)cbuf : 0; + putreg8(writeval, addr); + } + + /* ... and wait to complete. */ + + while (getreg32(STM32_FLASH_SR) & FLASH_SR_BSY) + { + stm32_waste(); + } + + /* Verify */ + + /* We do not check Options Byte invalid flags FLASH_SR_OPTVERR + * and FLASH_SR_OPTVERRUSR for EEPROM erase/write. They are unrelated + * and STM32L standard library does not check for these either. + */ + + if (getreg32(STM32_FLASH_SR) & (FLASH_SR_WRPERR | FLASH_SR_PGAERR | + FLASH_SR_SIZERR | FLASH_SR_RDERR)) + { + stm32_eeprom_lock(); + return -EROFS; + } + + if ((addr & 0x03) == 0x00 && left >= 4) + { + if (getreg32(addr) != writeval) + { + stm32_eeprom_lock(); + return -EIO; + } + + addr += 4; + i += 4; + cbuf += !!(cbuf) * 4; + } + else if ((addr & 0x01) == 0x00 && left >= 2) + { + if (getreg16(addr) != writeval) + { + stm32_eeprom_lock(); + return -EIO; + } + + addr += 2; + i += 2; + cbuf += !!(cbuf) * 2; + } + else + { + if (getreg8(addr) != writeval) + { + stm32_eeprom_lock(); + return -EIO; + } + + addr += 1; + i += 1; + cbuf += !!(cbuf) * 1; + } + } + + stm32_eeprom_lock(); + return buflen; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +int stm32_flash_unlock(void) +{ + int ret; + + ret = nxmutex_lock(&g_lock); + if (ret < 0) + { + return ret; + } + + flash_unlock(); + nxmutex_unlock(&g_lock); + + return ret; +} + +int stm32_flash_lock(void) +{ + int ret; + + ret = nxmutex_lock(&g_lock); + if (ret < 0) + { + return ret; + } + + flash_lock(); + nxmutex_unlock(&g_lock); + + return ret; +} + +size_t stm32_eeprom_size(void) +{ + return STM32_EEPROM_SIZE; +} + +size_t stm32_eeprom_getaddress(void) +{ + return STM32_EEPROM_BASE; +} + +ssize_t stm32_eeprom_write(size_t addr, const void *buf, size_t buflen) +{ + ssize_t outlen; + int ret; + + if (!buf) + { + return -EINVAL; + } + + ret = nxmutex_lock(&g_lock); + if (ret < 0) + { + return (ssize_t)ret; + } + + outlen = stm32_eeprom_erase_write(addr, buf, buflen); + nxmutex_unlock(&g_lock); + + return outlen; +} + +ssize_t stm32_eeprom_erase(size_t addr, size_t eraselen) +{ + ssize_t outlen; + int ret; + + ret = nxmutex_lock(&g_lock); + if (ret < 0) + { + return (ssize_t)ret; + } + + outlen = stm32_eeprom_erase_write(addr, NULL, eraselen); + nxmutex_unlock(&g_lock); + + return outlen; +} + +size_t up_progmem_pagesize(size_t page) +{ + return STM32_FLASH_PAGESIZE; +} + +size_t up_progmem_erasesize(size_t block) +{ + return STM32_FLASH_PAGESIZE; +} + +ssize_t up_progmem_getpage(size_t addr) +{ + if (addr >= STM32_FLASH_BASE) + { + addr -= STM32_FLASH_BASE; + } + + if (addr >= STM32_FLASH_SIZE) + { + return -EFAULT; + } + + return addr / STM32_FLASH_PAGESIZE; +} + +size_t up_progmem_getaddress(size_t page) +{ + if (page >= STM32_FLASH_NPAGES) + { + return SIZE_MAX; + } + + return page * STM32_FLASH_PAGESIZE + STM32_FLASH_BASE; +} + +size_t up_progmem_neraseblocks(void) +{ + return STM32_FLASH_NPAGES; +} + +bool up_progmem_isuniform(void) +{ +#ifdef STM32_FLASH_PAGESIZE + return true; +#else + return false; +#endif +} + +ssize_t up_progmem_ispageerased(size_t page) +{ + size_t addr; + size_t count; + size_t bwritten = 0; + + if (page >= STM32_FLASH_NPAGES) + { + return -EFAULT; + } + + /* Verify */ + + for (addr = up_progmem_getaddress(page), count = up_progmem_pagesize(page); + count; count--, addr++) + { + if (getreg8(addr) != FLASH_ERASEDVALUE) + { + bwritten++; + } + } + + return bwritten; +} + +ssize_t up_progmem_eraseblock(size_t block) +{ + size_t page_address; + int ret; + + if (block >= STM32_FLASH_NPAGES) + { + return -EFAULT; + } + + page_address = up_progmem_getaddress(block); + + /* Get flash ready and begin erasing single page */ + + ret = nxmutex_lock(&g_lock); + if (ret < 0) + { + return (ssize_t)ret; + } + + flash_unlock(); + + modifyreg32(STM32_FLASH_PECR, 0, FLASH_PECR_ERASE); + modifyreg32(STM32_FLASH_PECR, 0, FLASH_PECR_PROG); + + /* Erase is started by writing 0x00000000 to the first word + * of the program page. + */ + + putreg32(0x00, page_address); + + while (getreg32(STM32_FLASH_SR) & FLASH_SR_BSY) + { + stm32_waste(); + } + + flash_lock(); + nxmutex_unlock(&g_lock); + + /* Verify */ + + if (up_progmem_ispageerased(block) == 0) + { + return up_progmem_erasesize(block); + } + else + { + return -EIO; + } +} + +ssize_t up_progmem_write(size_t addr, const void *buf, size_t count) +{ + uint32_t *word = (uint32_t *)buf; + size_t written = count; + int ret = OK; + + /* STM32L1 requires word access and alignment. */ + + if (addr & 3) + { + return -EINVAL; + } + + if (count & 3) + { + return -EINVAL; + } + + /* Check for valid address range */ + + if (addr >= STM32_FLASH_BASE) + { + addr -= STM32_FLASH_BASE; + } + + if ((addr + count) > STM32_FLASH_SIZE) + { + return -EFAULT; + } + + /* Get flash ready and begin flashing */ + + ret = nxmutex_lock(&g_lock); + if (ret < 0) + { + return (ssize_t)ret; + } + + flash_unlock(); + + for (addr += STM32_FLASH_BASE; count; count -= 4, word++, addr += 4) + { + /* Write word and wait to complete */ + + putreg32(*word, addr); + + while (getreg32(STM32_FLASH_SR) & FLASH_SR_BSY) + { + stm32_waste(); + } + + /* Verify */ + + if (getreg32(STM32_FLASH_SR) & FLASH_SR_WRITE_PROTECTION_ERROR) + { + ret = -EROFS; + goto out; + } + + if (getreg32(addr) != *word) + { + ret = -EIO; + goto out; + } + } + +out: + /* If there was an error, clear all error flags in status + * register (rc_w1 register so do this by writing the + * error bits). + */ + + if (ret != OK) + { + ferr("flash write error: %d, status: 0x%" PRIx32 "\n", + ret, getreg32(STM32_FLASH_SR)); + modifyreg32(STM32_FLASH_SR, 0, FLASH_SR_ALLERRS); + } + + flash_lock(); + nxmutex_unlock(&g_lock); + return (ret == OK) ? written : ret; +} + +uint8_t up_progmem_erasestate(void) +{ + return FLASH_ERASEDVALUE; +} + +#endif /* defined(CONFIG_STM32_STM32L15XX) */ diff --git a/arch/arm/src/common/stm32/stm32_fmc.h b/arch/arm/src/common/stm32/stm32_fmc.h new file mode 100644 index 0000000000000..c113a7995414d --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_fmc.h @@ -0,0 +1,38 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_fmc.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_COMPAT_STM32FMC_H +#define __ARCH_ARM_SRC_COMMON_COMPAT_STM32FMC_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#if defined(CONFIG_STM32_HAVE_IP_FMC_M3M4_V1) +# include "stm32_fmc_m3m4_v1.h" +#else +# error "Unsupported STM32 stm32_fmc" +#endif + +#endif /* __ARCH_ARM_SRC_COMMON_COMPAT_STM32FMC_H */ diff --git a/arch/arm/src/common/stm32/stm32_fmc_m3m4_v1.c b/arch/arm/src/common/stm32/stm32_fmc_m3m4_v1.c new file mode 100644 index 0000000000000..aa91d1824b297 --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_fmc_m3m4_v1.c @@ -0,0 +1,212 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_fmc_m3m4_v1.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include "stm32.h" + +#if defined(CONFIG_STM32_FMC) + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_fmc_sdram_wait + * + * Description: + * Wait for the SDRAM controller to be ready. + * + ****************************************************************************/ + +void stm32_fmc_sdram_wait(void) +{ + int timeout = 0xffff; + while (timeout > 0) + { + if ((getreg32(STM32_FMC_SDSR) & FMC_SDSR_BUSY) == 0) + { + break; + } + + timeout--; + } + + DEBUGASSERT(timeout > 0); +} + +/**************************************************************************** + * Name: stm32_fmc_enable + * + * Description: + * Enable clocking to the FMC. + * + ****************************************************************************/ + +void stm32_fmc_enable(void) +{ + modifyreg32(STM32_RCC_AHB3ENR, 0, RCC_AHB3ENR_FMCEN); +} + +/**************************************************************************** + * Name: stm32_fmc_disable + * + * Description: + * Disable clocking to the FMC. + * + ****************************************************************************/ + +void stm32_fmc_disable(void) +{ + modifyreg32(STM32_RCC_AHB3ENR, RCC_AHB3ENR_FMCEN, 0); +} + +/**************************************************************************** + * Name: stm32_fmc_sdram_write_protect + * + * Description: + * Enable/Disable writes to an SDRAM. + * + ****************************************************************************/ + +void stm32_fmc_sdram_write_protect(int bank, bool state) +{ + uint32_t val; + uint32_t sdcr; + + DEBUGASSERT(bank == 1 || bank == 2); + sdcr = (bank == 1) ? STM32_FMC_SDCR1 : STM32_FMC_SDCR2; + + stm32_fmc_sdram_wait(); + + val = getreg32(sdcr); + if (state) + { + val |= FMC_SDCR_WP; /* wp == 1 */ + } + else + { + val &= ~FMC_SDCR_WP; /* wp == 0 */ + } + + putreg32(val, sdcr); +} + +/**************************************************************************** + * Name: stm32_fmc_sdram_set_refresh_rate + * + * Description: + * Set the SDRAM refresh rate. + * + ****************************************************************************/ + +void stm32_fmc_sdram_set_refresh_rate(int count) +{ + uint32_t val; + + DEBUGASSERT(count <= 0x1fff && count >= 0x29); + + stm32_fmc_sdram_wait(); + + val = getreg32(STM32_FMC_SDRTR); + val &= ~(0x1fff << 1); /* preserve non-count bits */ + val |= (count << 1); + putreg32(val, STM32_FMC_SDRTR); +} + +/**************************************************************************** + * Name: stm32_fmc_sdram_set_timing + * + * Description: + * Set the SDRAM timing parameters. + * + ****************************************************************************/ + +void stm32_fmc_sdram_set_timing(int bank, uint32_t timing) +{ + uint32_t val; + uint32_t sdtr; + + DEBUGASSERT((bank == 1) || (bank == 2)); + DEBUGASSERT((timing & FMC_SDTR_RESERVED) == 0); + + sdtr = (bank == 1) ? STM32_FMC_SDTR1 : STM32_FMC_SDTR2; + val = getreg32(sdtr); + val &= FMC_SDTR_RESERVED; /* preserve reserved bits */ + val |= timing; + putreg32(val, sdtr); +} + +/**************************************************************************** + * Name: stm32_fmc_sdram_set_control + * + * Description: + * Set the SDRAM control parameters. + * + ****************************************************************************/ + +void stm32_fmc_sdram_set_control(int bank, uint32_t ctrl) +{ + uint32_t val; + uint32_t sdcr; + + DEBUGASSERT((bank == 1) || (bank == 2)); + DEBUGASSERT((ctrl & FMC_SDCR_RESERVED) == 0); + + sdcr = (bank == 1) ? STM32_FMC_SDCR1 : STM32_FMC_SDCR2; + val = getreg32(sdcr); + val &= FMC_SDCR_RESERVED; /* preserve reserved bits */ + val |= ctrl; + putreg32(val, sdcr); +} + +/**************************************************************************** + * Name: stm32_fmc_sdram_command + * + * Description: + * Send a command to the SDRAM. + * + ****************************************************************************/ + +void stm32_fmc_sdram_command(uint32_t cmd) +{ + uint32_t val; + + DEBUGASSERT((cmd & FMC_SDCMR_RESERVED) == 0); + + /* Wait for the controller to be ready */ + + stm32_fmc_sdram_wait(); + + val = getreg32(STM32_FMC_SDCMR); + val &= FMC_SDCMR_RESERVED; /* Preserve reserved bits */ + val |= cmd; + putreg32(val, STM32_FMC_SDCMR); +} + +#endif /* CONFIG_STM32_FMC */ diff --git a/arch/arm/src/common/stm32/stm32_fmc_m3m4_v1.h b/arch/arm/src/common/stm32/stm32_fmc_m3m4_v1.h new file mode 100644 index 0000000000000..a29da3062fe8a --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_fmc_m3m4_v1.h @@ -0,0 +1,140 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_fmc_m3m4_v1.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_FMC_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_FMC_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#if defined(CONFIG_STM32_HAVE_IP_FMC_M3M4_V1) + +#include "chip.h" +#include "hardware/stm32_fmc.h" + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Name: stm32_fmc_sdram_wait + * + * Description: + * Wait for the SDRAM controller to be ready. + * + ****************************************************************************/ + +void stm32_fmc_sdram_wait(void); + +/**************************************************************************** + * Name: stm32_fmc_enable + * + * Description: + * Enable clocking to the FMC. + * + ****************************************************************************/ + +void stm32_fmc_enable(void); + +/**************************************************************************** + * Name: stm32_fmc_disable + * + * Description: + * Disable clocking to the FMC. + * + ****************************************************************************/ + +void stm32_fmc_disable(void); + +/**************************************************************************** + * Name: stm32_fmc_sdram_write_protect + * + * Description: + * Enable/Disable writes to an SDRAM. + * + ****************************************************************************/ + +void stm32_fmc_sdram_write_protect(int bank, bool state); + +/**************************************************************************** + * Name: stm32_fmc_sdram_set_refresh_rate + * + * Description: + * Set the SDRAM refresh rate. + * + ****************************************************************************/ + +void stm32_fmc_sdram_set_refresh_rate(int count); + +/**************************************************************************** + * Name: stm32_fmc_sdram_set_timing + * + * Description: + * Set the SDRAM timing parameters. + * + ****************************************************************************/ + +void stm32_fmc_sdram_set_timing(int bank, uint32_t timing); + +/**************************************************************************** + * Name: stm32_fmc_sdram_set_control + * + * Description: + * Set the SDRAM control parameters. + * + ****************************************************************************/ + +void stm32_fmc_sdram_set_control(int bank, uint32_t ctrl); + +/**************************************************************************** + * Name: stm32_fmc_sdram_command + * + * Description: + * Send a command to the SDRAM. + * + ****************************************************************************/ + +void stm32_fmc_sdram_command(uint32_t cmd); + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ + +#endif /* CONFIG_STM32_HAVE_IP_FMC_M3M4_V1 */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_FMC_H */ diff --git a/arch/arm/src/common/stm32/stm32_foc.h b/arch/arm/src/common/stm32/stm32_foc.h new file mode 100644 index 0000000000000..4f1b673f5674c --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_foc.h @@ -0,0 +1,38 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_foc.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_COMPAT_STM32FOC_H +#define __ARCH_ARM_SRC_COMMON_COMPAT_STM32FOC_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#if defined(CONFIG_STM32_HAVE_COMMON_FOC) +# include "stm32_foc_m3m4_v1.h" +#else +# error "Unsupported STM32 stm32_foc" +#endif + +#endif /* __ARCH_ARM_SRC_COMMON_COMPAT_STM32FOC_H */ diff --git a/arch/arm/src/common/stm32/stm32_foc_m3m4_v1.c b/arch/arm/src/common/stm32/stm32_foc_m3m4_v1.c new file mode 100644 index 0000000000000..a50572a8bc570 --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_foc_m3m4_v1.c @@ -0,0 +1,2750 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_foc_m3m4_v1.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include + +#include +#include + +#include "arm_internal.h" +#include "stm32_pwm.h" +#include "stm32_foc_m3m4_v1.h" +#include "stm32_adc.h" +#include "stm32_dma.h" + +#include +#include + +#include "stm32_pwm.h" +#include "stm32_foc_m3m4_v1.h" + +#include "hardware/stm32_dbgmcu.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Verify peripheral configuration ******************************************/ + +/* This is the lower-half implementation for the STM32 FOC devices. + * + * We currently support a current sensing topology with two and three shunts. + * Configuration with a single-shunt is not supported at the moment and will + * require additional current reconstruction logic. + * + * A single FOC device uses one advanced timer to generate a center-aligned + * PWM which control phase switches bridge. Phase currents must be sampled + * at vector 0 (all low-side switches are on and the current flows through + * current sensors). + * + * This implementation uses one ADC per controller and we only use injected + * conversion to sample currents. ADC regular conversion is not used + * and can be used to other tasks with the help of DMA transfer. + * For ADC regular conversion, only DMA transfer is possible since ADC + * interrupt handler is reserved for the FOC only. + * + * The ADC conversion trigger is configurable. Available options are: + * 1. TRGO events generated on update event + * 2. CCR4 events + * + * There are some differences in implementation depending on the peripherals + * supported by the chip. + * + * There is no differences according to TIMER IPv1 and IPv2 affecting + * this implementation. + * + * For STM32 ADC cores there are some dissimilarities that had to be taken + * into account. It is: + * + * 1. For ADC IPv1 (F2, F4, F7, L1) + * - all ADC instances coupled in single block + * - single entry point for ADC123 interrupts + * + * 2. For ADC IPv1 basic (F1, F37x) + * - ADC instances are no coupled in blocks + * - common interrupts for ADC1 and ADC2 + * + * 3. For ADC IPv2 (F3 (without F37x), H7, L4, L4+, G4) + * - ADC grouped in slave-master configuration (ADC12, ADC34) + * + * This code will not work for chips with ADC IPv2 basic (F0, L0, G0). + * For these, only regular channels are available and we cannot use injected + * conversion. + * + * Currently, up to two FOC instances are supported. + */ + +/* Verify system configuration **********************************************/ + +/* This is not for ADC IPv2 basic */ + +#if defined(CONFIG_STM32_HAVE_IP_ADC_M3M4_V2) && defined(HAVE_BASIC_ADC) +# error Not supported ADC IP core +#endif + +/* Multi instances support tested only on IP_ADC_V1 */ + +#if CONFIG_MOTOR_FOC_INST > 1 +# if defined(CONFIG_STM32_HAVE_IP_ADC_M3M4_V2) +# error Not tested yet +# endif +#endif + +/* PWM lower-half ops and ADC lower-half ops must be enabled */ + +#ifndef CONFIG_STM32_PWM_LL_OPS +# error PWM low-level operations interface must be enabled +#endif +#ifndef CONFIG_STM32_ADC_LL_OPS +# error ADC low-level operations interface must be enabled +#endif + +/* We don't want start conversion during ADC setup */ + +#ifndef CONFIG_STM32_ADC_NO_STARTUP_CONV +# error ADC startup conversion must be disabled +#endif + +/* We need interface to change ADC sample-time */ + +#ifndef CONFIG_STM32_ADC_CHANGE_SAMPLETIME +# error ADC sample-time configuration interface must be enabled +#endif + +/* Debug register for PWM timers */ + +#if defined(CONFIG_STM32_DBGMCU_HAVE_TIM_FZ_IN_APB2_FZ) +# define FOC_PWM_FZ_REG (STM32_DBGMCU_APB2_FZ) +#elif defined(CONFIG_STM32_DBGMCU_HAVE_TIM_FZ_IN_CR) +# define FOC_PWM_FZ_REG (STM32_DBGMCU_CR) +#endif + +/* FOC0 always use TIMER1 for PWM */ + +#ifdef CONFIG_STM32_FOC_FOC0 +# define FOC0_PWM (1) +# define FOC0_PWM_NCHANNELS (PWM_TIM1_NCHANNELS) +# define FOC0_PWM_BASE (STM32_TIM1_BASE) +# if defined(CONFIG_STM32_DBGMCU_HAVE_TIM_FZ_IN_APB2_FZ) +# define FOC0_PWM_FZ_BIT (DBGMCU_APB2_TIM1STOP) +# elif defined(CONFIG_STM32_DBGMCU_HAVE_TIM_FZ_IN_CR) +# define FOC0_PWM_FZ_BIT (DBGMCU_CR_TIM1STOP) +# endif +# if CONFIG_STM32_TIM1_MODE != 2 +# error TIM1 must be configured in center-aligned mode 1 +# endif +#endif /* CONFIG_STM32_FOC_FOC0 */ + +/* FOC1 always use TIMER8 for PWM */ + +#ifdef CONFIG_STM32_FOC_FOC1 +# define FOC1_PWM (8) +# define FOC1_PWM_NCHANNELS (PWM_TIM8_NCHANNELS) +# define FOC1_PWM_BASE (STM32_TIM8_BASE) +# if defined(CONFIG_STM32_DBGMCU_HAVE_TIM_FZ_IN_APB2_FZ) +# define FOC1_PWM_FZ_BIT (DBGMCU_APB2_TIM8STOP) +# elif defined(CONFIG_STM32_DBGMCU_HAVE_TIM_FZ_IN_CR) +# define FOC1_PWM_FZ_BIT (DBGMCU_CR_TIM8STOP) +# endif +# if CONFIG_STM32_TIM8_MODE != 2 +# error TIM8 must be configured in center-aligned mode 1 +# endif +#endif + +/* The maximum supported number of phases depends on the ADC trigger */ + +#if defined(CONFIG_STM32_FOC_ADC_CCR4) +# if CONFIG_MOTOR_FOC_PHASES > 3 +# error max 3 phases supported +# endif +#elif defined(CONFIG_STM32_FOC_ADC_TRGO) +# if CONFIG_MOTOR_FOC_PHASES > 4 +# error max 4 phases supported +# endif +#else +# error +#endif + +/* Tested only for 3-phase devices */ + +#if CONFIG_MOTOR_FOC_PHASES != 3 +# error Tested only for 3-phase devices +#endif + +/* Only one ADC trigger must be selected */ + +#if defined(CONFIG_STM32_FOC_ADC_CCR4) && defined(CONFIG_STM32_FOC_ADC_TRGO) +# error Invalid ADC trigger configuration +#endif + +/* Phase currents can only be sampled when all low-side switches are off. + * This is only valid for the V0 vector in the SVM. + * + * For PWM mode 1: + * V7 for CNTR = 0 + * V0 for CNTR = ARR + * + * For PWM mode 2: + * V7 for CNTR = ARR + * V0 for CNTR = 0 + */ + +#if defined(CONFIG_STM32_FOC_ADC_CCR4) + +/* FOC ADC trigger on CCR4 **************************************************/ + +/* PWM channels configuration: + * - 3 channels for phases PWM (CCR1, CCR2, CCR3) + * - 1 channel for ADC injection sequence trigger (CCR4) + */ + +# if defined(CONFIG_STM32_FOC_FOC0) +# if FOC0_PWM_NCHANNELS != (CONFIG_MOTOR_FOC_PHASES + 1) +# error Invalid channels configuration +# endif +# endif +# if defined(CONFIG_STM32_FOC_FOC1) +# if FOC1_PWM_NCHANNELS != (CONFIG_MOTOR_FOC_PHASES + 1) +# error Invalid channels configuration +# endif +# endif + +/* Generalize JEXTSEL bits for CCR4 trigger. + * + * ADC trigger event on PWM timer CCR4 (rising edge). + * + * This implementation uses PWM mode 1 so: + * TIMx CCR4 = (ARR - trigger_offset) + */ + +# if defined(CONFIG_STM32_HAVE_IP_ADC_M3M4_V2) +# ifdef CONFIG_STM32_FOC_USE_TIM1 +# define ADC_JEXTSEL_T1CC4 (ADC12_JSQR_JEXTSEL_T1CC4) +# endif +# ifdef CONFIG_STM32_FOC_USE_TIM8 +# define ADC_JEXTSEL_T8CC4 (ADC12_JSQR_JEXTSEL_T8CC4) +# endif +# elif defined(CONFIG_STM32_HAVE_IP_ADC_M3M4_V1) +# ifdef CONFIG_STM32_FOC_USE_TIM1 +# define ADC_JEXTSEL_T1CC4 (ADC_CR2_JEXTSEL_T1CC4) +# endif +# ifdef CONFIG_STM32_FOC_USE_TIM8 +# define ADC_JEXTSEL_T8CC4 (ADC_CR2_JEXTSEL_T8CC4) +# endif +# else +# error Not supported +# endif + +/* ADC trigger offset - must be greater than 0! */ + +# define ADC_TRIGGER_OFFSET (1) + +# ifdef CONFIG_STM32_FOC_FOC0 +# define FOC0_ADC_JEXTSEL (ADC_JEXTSEL_T1CC4) +# endif +# ifdef CONFIG_STM32_FOC_FOC1 +# define FOC1_ADC_JEXTSEL (ADC_JEXTSEL_T8CC4) +# endif + +#elif defined(CONFIG_STM32_FOC_ADC_TRGO) + +/* FOC ADC trigger on TRGO **************************************************/ + +/* PWM TRGO support must be enabled */ + +# ifndef CONFIG_STM32_PWM_TRGO +# error PWM TRGO support must be enabled +# endif + +/* TRGO on update event = ATIM_CR2_MMS_UPDATE (2) */ + +# define FOC_PWM_TRGO (2) + +/* PWM channels configuration: + * - n channels for phases PWM (CCR1, CCR2, CCR3, CCR4) + */ + +# if defined(CONFIG_STM32_FOC_FOC0) +# if FOC0_PWM_NCHANNELS != (CONFIG_MOTOR_FOC_PHASES) +# error Invalid channels configuration +# endif +# endif +# if defined(CONFIG_STM32_FOC_FOC1) +# if FOC1_PWM_NCHANNELS != (CONFIG_MOTOR_FOC_PHASES) +# error Invalid channels configuration +# endif +# endif + +/* Generalize JEXTSEL bits for TRGO trigger. + * + * ADC trigger event on PWM timer TRGO (rising edge). + * + * This implementation uses PWM mode 1 so: + * TIMx TRGO = (ARR) + */ + +# if defined(CONFIG_STM32_HAVE_IP_ADC_M3M4_V2) +# ifdef CONFIG_STM32_FOC_USE_TIM1 +# define ADC_JEXTSEL_T1TRGO (ADC12_JSQR_JEXTSEL_T1TRGO) +# endif +# ifdef CONFIG_STM32_FOC_USE_TIM8 +# define ADC_JEXTSEL_T8TRGO (ADC12_JSQR_JEXTSEL_T8TRGO) +# endif +# elif defined(CONFIG_STM32_HAVE_IP_ADC_M3M4_V1) +# ifdef CONFIG_STM32_FOC_USE_TIM1 +# define ADC_JEXTSEL_T1TRGO (ADC_CR2_JEXTSEL_T1TRGO) +# endif +# ifdef CONFIG_STM32_FOC_USE_TIM8 +# error TIM8 and TRGO trigger not supported for ADC IPv1 +# endif +# else +# error Not supported +# endif + +# ifdef CONFIG_STM32_FOC_FOC0 +# define FOC0_ADC_JEXTSEL (ADC_JEXTSEL_T1TRGO) +# endif +# ifdef CONFIG_STM32_FOC_FOC1 +# define FOC1_ADC_JEXTSEL (ADC_JEXTSEL_T8TRGO) +# endif + +#else + +/* No trigger selected ******************************************************/ + +# error Invalid FOC ADC trigger +#endif + +/* Phase current samples for FOC0 */ + +#ifdef CONFIG_STM32_FOC_FOC0 +# ifdef CONFIG_STM32_FOC_FOC0_ADC1 +# define FOC0_ADC 1 +# endif +# ifdef CONFIG_STM32_FOC_FOC0_ADC2 +# define FOC0_ADC 2 +# endif +# ifdef CONFIG_STM32_FOC_FOC0_ADC3 +# define FOC0_ADC 3 +# endif +# ifdef CONFIG_STM32_FOC_FOC0_ADC4 +# define FOC0_ADC 4 +# endif +#endif + +/* Phase current samples for FOC1 */ + +#ifdef CONFIG_STM32_FOC_FOC1 +# ifdef CONFIG_STM32_FOC_FOC1_ADC1 +# define FOC1_ADC 1 +# endif +# ifdef CONFIG_STM32_FOC_FOC1_ADC2 +# define FOC1_ADC 2 +# endif +# ifdef CONFIG_STM32_FOC_FOC1_ADC3 +# define FOC1_ADC 3 +# endif +# ifdef CONFIG_STM32_FOC_FOC1_ADC4 +# define FOC1_ADC 4 +# endif +#endif + +/* The number of required injected channels */ + +#ifdef CONFIG_STM32_FOC_G4_ADCCHAN0_WORKAROUND +# define FOC_ADC_INJ_CHAN_REQUIRED (CONFIG_MOTOR_FOC_SHUNTS + 1) +#else +# define FOC_ADC_INJ_CHAN_REQUIRED (CONFIG_MOTOR_FOC_SHUNTS) +#endif + +/* Validate ADC configuration: + * 1. ADC must be supported by chip, + * 2. ADC support for injected channels must be enabled, + * 3. ADC software trigger starts only regular conversion. + */ + +#ifdef CONFIG_STM32_FOC_USE_ADC1 +# ifndef CONFIG_STM32_ADC1 +# error ADC1 not supported ! +# endif +# ifndef ADC1_HAVE_JEXTCFG +# error ADC1 must support JEXTCFG +# endif +# if CONFIG_STM32_ADC1_ANIOC_TRIGGER != 1 +# error CONFIG_STM32_ADC1_ANIOC_TRIGGER must be 1 +# endif +# if CONFIG_STM32_ADC1_INJECTED_CHAN != FOC_ADC_INJ_CHAN_REQUIRED +# error Invalid configuration for ADC1 injected channels +# endif +#endif +#ifdef CONFIG_STM32_FOC_USE_ADC2 +# ifndef CONFIG_STM32_ADC2 +# error ADC2 not supported ! +# endif +# ifndef ADC2_HAVE_JEXTCFG +# error ADC2 must support JEXTCFG +# endif +# if CONFIG_STM32_ADC2_ANIOC_TRIGGER != 1 +# error CONFIG_STM32_ADC2_ANIOC_TRIGGER must be 1 +# endif +# if CONFIG_STM32_ADC2_INJECTED_CHAN != FOC_ADC_INJ_CHAN_REQUIRED +# error Invalid configuration for ADC2 injected channels +# endif +#endif +#ifdef CONFIG_STM32_FOC_USE_ADC3 +# ifndef CONFIG_STM32_ADC3 +# error ADC3 not supported ! +# endif +# ifndef ADC3_HAVE_JEXTCFG +# error ADC3 must support JEXTCFG +# endif +# if CONFIG_STM32_ADC3_ANIOC_TRIGGER != 1 +# error CONFIG_STM32_ADC3_ANIOC_TRIGGER must be 1 +# endif +# if CONFIG_STM32_ADC3_INJECTED_CHAN != FOC_ADC_INJ_CHAN_REQUIRED +# error Invalid configuration for ADC3 injected channels +# endif +#endif +#ifdef CONFIG_STM32_FOC_USE_ADC4 +# ifndef CONFIG_STM32_ADC4 +# error ADC4 not supported ! +# endif +# ifndef ADC4_HAVE_JEXTCFG +# error ADC4 must support JEXTCFG +# endif +# if CONFIG_STM32_ADC4_ANIOC_TRIGGER != 1 +# error CONFIG_STM32_ADC4_ANIOC_TRIGGER must be 1 +# endif +# if CONFIG_STM32_ADC4_INJECTED_CHAN != FOC_ADC_INJ_CHAN_REQUIRED +# error Invalid configuration for ADC4 injected channels +# endif +#endif + +/* Max 3 shunts supported if STM32G4 ADC CHAN0 workaround enabled */ + +#ifdef CONFIG_STM32_FOC_G4_ADCCHAN0_WORKAROUND +# if CONFIG_MOTOR_FOC_SHUNTS > 3 +# error +# endif +#endif + +/* Combine JEXTSEL with JEXTEN default */ + +#ifdef CONFIG_STM32_FOC_FOC0 +# define FOC0_ADC_JEXT (ADC_JEXTREG_JEXTEN_DEFAULT | FOC0_ADC_JEXTSEL) +#endif +#ifdef CONFIG_STM32_FOC_FOC1 +# define FOC1_ADC_JEXT (ADC_JEXTREG_JEXTEN_DEFAULT | FOC1_ADC_JEXTSEL) +#endif + +/* Generalize ADC interrupt flags */ + +#if defined(CONFIG_STM32_HAVE_IP_ADC_M3M4_V2) +# define FOC_ADC_ISR_FOC ADC_ISR_JEOS +# define FOC_ADC_IER_FOC ADC_IER_JEOS +# define FOC_ADC_ISR_OVR ADC_INT_OVR +#elif defined(CONFIG_STM32_HAVE_IP_ADC_M3M4_V1) +# define FOC_ADC_ISR_FOC ADC_ISR_JEOC +# define FOC_ADC_IER_FOC ADC_IER_JEOC +# define FOC_ADC_ISR_OVR ADC_SR_OVR +#else +# error Not supported +#endif + +/* We have 3 possible ADC IRQ configuration */ + +#if defined(STM32_IRQ_ADC1) + +/* Only ADC1 supported */ + +# define STM32_IRQ_ADC1_FOC STM32_IRQ_ADC1 + +#elif defined(STM32_IRQ_ADC12) + +/* ADC1 + ADC2 interrupt */ + +# define STM32_IRQ_ADC1_FOC STM32_IRQ_ADC12 +# define STM32_IRQ_ADC2_FOC STM32_IRQ_ADC12 + +/* ADC3 + ADC4 interrupt */ + +# define STM32_IRQ_ADC3_FOC STM32_IRQ_ADC34 +# define STM32_IRQ_ADC4_FOC STM32_IRQ_ADC34 + +#elif defined(STM32_IRQ_ADC) + +/* ADC1 + ADC2 + ADC3 interrupt */ + +# define STM32_IRQ_ADC1_FOC STM32_IRQ_ADC +# define STM32_IRQ_ADC2_FOC STM32_IRQ_ADC +# define STM32_IRQ_ADC3_FOC STM32_IRQ_ADC +#endif + +/* ADC common ***************************************************************/ + +/* Common for ADCv1 */ + +#if defined(CONFIG_STM32_HAVE_IP_ADC_M3M4_V1) && !defined(HAVE_BASIC_ADC) +# define FOC_ADC_HAVE_CMN (1) +# ifdef CONFIG_STM32_FOC_USE_ADC1 +# define FOC_ADC1_CMN (&g_stm32_foc_adccmn123) +# endif +# ifdef CONFIG_STM32_FOC_USE_ADC2 +# define FOC_ADC2_CMN (&g_stm32_foc_adccmn123) +# endif +# ifdef CONFIG_STM32_FOC_USE_ADC3 +# define FOC_ADC3_CMN (&g_stm32_foc_adccmn123) +# endif +#endif + +/* Common for ADCv1 basic */ + +#if defined(CONFIG_STM32_HAVE_IP_ADC_M3M4_V1) && defined(HAVE_BASIC_ADC) +# undef FOC_ADC_HAVE_CMN +# ifdef CONFIG_STM32_FOC_USE_ADC1 +# define FOC_ADC1_CMN (0) +# endif +# ifdef CONFIG_STM32_FOC_USE_ADC2 +# define FOC_ADC2_CMN (0) +# endif +# ifdef CONFIG_STM32_FOC_USE_ADC3 +# define FOC_ADC3_CMN (0) +# endif +#endif + +/* Common for ADCv2 */ + +#ifdef CONFIG_STM32_HAVE_IP_ADC_M3M4_V2 +# define FOC_ADC_HAVE_CMN (1) +# ifdef CONFIG_STM32_FOC_USE_ADC1 +# define FOC_ADC1_CMN (&g_stm32_foc_adccmn12) +# endif +# ifdef CONFIG_STM32_FOC_USE_ADC2 +# define FOC_ADC2_CMN (&g_stm32_foc_adccmn12) +# endif +# ifdef CONFIG_STM32_FOC_USE_ADC3 +# define FOC_ADC3_CMN (&g_stm32_foc_adccmn34) +# endif +# ifdef CONFIG_STM32_FOC_USE_ADC4 +# define FOC_ADC4_CMN (&g_stm32_foc_adccmn34) +# endif +#endif + +/* FOC ADC configuration ****************************************************/ + +#ifdef CONFIG_STM32_FOC_FOC0 +# ifdef CONFIG_STM32_FOC_FOC0_ADC1 +# define FOC0_ADC_IRQ STM32_IRQ_ADC1_FOC +# define FOC0_ADC_CMN FOC_ADC1_CMN +# endif +# ifdef CONFIG_STM32_FOC_FOC0_ADC2 +# define FOC0_ADC_IRQ STM32_IRQ_ADC2_FOC +# define FOC0_ADC_CMN FOC_ADC2_CMN +# endif +# ifdef CONFIG_STM32_FOC_FOC0_ADC3 +# define FOC0_ADC_IRQ STM32_IRQ_ADC3_FOC +# define FOC0_ADC_CMN FOC_ADC3_CMN +# endif +# ifdef CONFIG_STM32_FOC_FOC0_ADC4 +# define FOC0_ADC_IRQ STM32_IRQ_ADC4_FOC +# define FOC0_ADC_CMN FOC_ADC4_CMN +# endif +#endif + +#ifdef CONFIG_STM32_FOC_FOC1 +# ifdef CONFIG_STM32_FOC_FOC1_ADC1 +# define FOC1_ADC_IRQ STM32_IRQ_ADC1_FOC +# define FOC1_ADC_CMN FOC_ADC1_CMN +# endif +# ifdef CONFIG_STM32_FOC_FOC1_ADC2 +# define FOC1_ADC_IRQ STM32_IRQ_ADC2_FOC +# define FOC1_ADC_CMN FOC_ADC2_CMN +# endif +# ifdef CONFIG_STM32_FOC_FOC1_ADC3 +# define FOC1_ADC_IRQ STM32_IRQ_ADC3_FOC +# define FOC1_ADC_CMN FOC_ADC3_CMN +# endif +# ifdef CONFIG_STM32_FOC_FOC1_ADC4 +# define FOC1_ADC_IRQ STM32_IRQ_ADC4_FOC +# define FOC1_ADC_CMN FOC_ADC4_CMN +# endif +#endif + +#ifdef CONFIG_MOTOR_FOC_BEMF_SENSE + +/* Additional checks for BEMF sensing */ + +# if defined(CONFIG_STM32_FOC_FOC0) && defined(CONFIG_STM32_FOC_FOC1) +# error BEMF sensing supported only for one FOC instance enabled +# endif + +# if defined(CONFIG_STM32_FOC_FOC0_ADC2) || defined(CONFIG_STM32_FOC_FOC0_ADC3) +# error FOC must use ADC master +# endif +# if defined(CONFIG_STM32_FOC_FOC1_ADC2) || defined(CONFIG_STM32_FOC_FOC1_ADC3) +# error FOC must use ADC master +# endif + +/* Additional ADC slave in use */ + +# if defined(CONFIG_STM32_FOC_FOC0_ADC1) || defined(CONFIG_STM32_FOC_FOC1_ADC1) +# define CONFIG_STM32_FOC_USE_ADC2 +# endif +# if defined(CONFIG_STM32_FOC_FOC0_ADC3) || defined(CONFIG_STM32_FOC_FOC1_ADC3) +# define CONFIG_STM32_FOC_USE_ADC4 +# endif + +/* The number of required injected channels */ + +# ifdef CONFIG_STM32_FOC_G4_ADCCHAN0_WORKAROUND +# define FOC_VADC_INJ_CHAN_REQUIRED (CONFIG_MOTOR_FOC_PHASES + 1) +# else +# define FOC_VADC_INJ_CHAN_REQUIRED (CONFIG_MOTOR_FOC_PHASES) +# endif + +/* Slave ADC2 */ + +# ifdef CONFIG_STM32_FOC_USE_ADC2 +# ifndef CONFIG_STM32_ADC2 +# error ADC2 not supported ! +# endif +# ifndef ADC2_HAVE_JEXTCFG +# error ADC2 must support JEXTCFG +# endif +# if CONFIG_STM32_ADC2_ANIOC_TRIGGER != 1 +# error CONFIG_STM32_ADC2_ANIOC_TRIGGER must be 1 +# endif +# if CONFIG_STM32_ADC2_INJECTED_CHAN != FOC_VADC_INJ_CHAN_REQUIRED +# error Invalid configuration for ADC2 injected channels +# endif +# endif + +/* Slave ADC4 */ + +# ifdef CONFIG_STM32_FOC_USE_ADC4 +# ifndef CONFIG_STM32_ADC4 +# error ADC4 not supported ! +# endif +# ifndef ADC4_HAVE_JEXTCFG +# error ADC4 must support JEXTCFG +# endif +# if CONFIG_STM32_ADC4_ANIOC_TRIGGER != 1 +# error CONFIG_STM32_ADC4_ANIOC_TRIGGER must be 1 +# endif +# if CONFIG_STM32_ADC4_INJECTED_CHAN != FOC_VADC_INJ_CHAN_REQUIRED +# error Invalid configuration for ADC4 injected channels +# endif +# endif + +#endif + +/* Helper macros ************************************************************/ + +/* Get arch-specific FOC private part */ + +#define STM32_FOCPIRV_FROM_DEV_GET(d) \ + ((struct stm32_foc_priv_s *)(d)->lower->data) + +/* Get board-specific FOC data */ + +#define STM32_FOCBOARD_FROM_DEV_GET(d) \ + ((STM32_FOCPIRV_FROM_DEV_GET(d))->board) + +/* Get arch-specific FOC devices */ + +#define STM32_FOCDEV_FROM_DEV_GET(d) \ + ((STM32_FOCPIRV_FROM_DEV_GET(d))->dev) + +/* Get PWM device */ + +#define PWM_FROM_FOC_DEV_GET(d) (STM32_FOCDEV_FROM_DEV_GET(d)->pwm) + +/* Get ADC device */ + +#define ADC_FROM_FOC_DEV_GET(d) (STM32_FOCDEV_FROM_DEV_GET(d)->adc) +#define VADC_FROM_FOC_DEV_GET(d) (STM32_FOCDEV_FROM_DEV_GET(d)->vadc) + +/* Define PWM all outputs */ + +#ifdef CONFIG_STM32_FOC_HAS_PWM_COMPLEMENTARY +# define PMW_OUTPUTS_ALL_COMP (STM32_PWM_OUT1N| \ + STM32_PWM_OUT2N| \ + STM32_PWM_OUT3N) +#else +# define PMW_OUTPUTS_ALL_COMP (0) +#endif + +#if defined(CONFIG_STM32_FOC_ADC_CCR4) || (CONFIG_MOTOR_FOC_PHASES > 3) +# define PMW_OUTPUTS_ALL_OUT4 (STM32_PWM_OUT4) +#else +# define PMW_OUTPUTS_ALL_OUT4 (0) +#endif + +#define PWM_OUTPUTS_ALL (STM32_PWM_OUT1| \ + STM32_PWM_OUT2| \ + STM32_PWM_OUT3| \ + PMW_OUTPUTS_ALL_COMP| \ + PMW_OUTPUTS_ALL_OUT4) + +/* Enable all PWM outputs at once (include CHAN4 for ADC trigger) */ + +#define PWM_ALL_OUTPUTS_ENABLE(pwm, state) \ + PWM_OUTPUTS_ENABLE(pwm, PWM_OUTPUTS_ALL, state); + +/* Enable/disable ADC interrupts (FOC worker loop) */ + +#define STM32_ADC_ENABLEINT(adc) STM32_ADC_INT_ENABLE(adc, FOC_ADC_IER_FOC) +#define STM32_ADC_DISABLEINT(adc) STM32_ADC_INT_DISABLE(adc, FOC_ADC_IER_FOC) + +/* ADC calibration samples */ + +#define CAL_SAMPLES (5000) + +/* ADC calibration frequency */ + +#define CAL_FREQ (10000) + +/* Define PWM modes to control H-bridge. + * + * Any H-bridge specific configuration can be done with PWM_CHxPOL + * and PWM_CHxIDLE configuration options + */ + +#define PWM_MODE_FOC STM32_CHANMODE_PWM1 +#define PWM_MODE_ADC_TRG STM32_CHANMODE_PWM1 +#define PWM_MODE_HSLO_LSHI STM32_CHANMODE_OCREFHI +#define PWM_MODE_HSHI_LSLO STM32_CHANMODE_OCREFLO + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/* STM32 FOC devices. + * This structure gathers all low level drivers required by FOC device. + */ + +struct stm32_foc_dev_s +{ + uint8_t pwm_inst; /* PWM timer instance */ + uint8_t adc_inst; /* ADC timer instance */ + uint32_t pwm_base; /* PWM timer base */ + uint32_t adc_irq; /* ADC irq */ + uint32_t jextval; /* JEXT configuration */ + + struct stm32_pwm_dev_s *pwm; /* PWM device reference */ + struct adc_dev_s *adc_dev; /* ADC device reference */ + struct stm32_adc_dev_s *adc; /* STM32 ADC device reference */ + + /* Interrupt handler for FOC device */ + + int (*adc_isr)(struct foc_dev_s *dev); + +#ifdef CONFIG_MOTOR_FOC_BEMF_SENSE + struct adc_dev_s *vadc_dev; /* ADC device reference (voltage ) */ + struct stm32_adc_dev_s *vadc; /* STM32 ADC device reference (voltage) */ +#endif +}; + +/* STM32 FOC common data */ + +struct stm32_foc_adccmn_s +{ + uint8_t cntr; /* ADC common counter */ + mutex_t lock; /* Lock data */ +}; + +/* STM32 FOC volatile data */ + +struct stm32_foc_data_s +{ + foc_current_t curr[CONFIG_MOTOR_FOC_PHASES]; /* Current */ + uint8_t notifier_div; /* FOC notifier prescaler */ + uint32_t adc_freq; /* ADC interrupts frequency */ + uint32_t per; /* PWM timer period (ARR) */ + uint32_t adcint_cntr; /* ADC interrupt counter */ + uint32_t curr_offset[CONFIG_MOTOR_FOC_SHUNTS]; /* ADC current offset */ + int16_t curr_raw[CONFIG_MOTOR_FOC_SHUNTS]; /* ADC current RAW */ +#ifdef CONFIG_MOTOR_FOC_BEMF_SENSE + foc_voltage_t volt[CONFIG_MOTOR_FOC_PHASES]; /* Voltage */ + uint32_t volt_offset[CONFIG_MOTOR_FOC_PHASES]; /* ADC voltage offset */ + int16_t volt_raw[CONFIG_MOTOR_FOC_PHASES]; /* ADC voltage RAW */ +#endif +}; + +/* STM32 FOC private */ + +struct stm32_foc_priv_s +{ + /* Volatile data */ + + struct stm32_foc_data_s data; + + /* ADC calbration done */ + + sem_t cal_done_sem; + + /* STM32 FOC devices */ + + struct stm32_foc_dev_s *dev; + + /* Board-specific data */ + + struct stm32_foc_board_s *board; + + /* Upper-half FOC controller callbacks */ + + const struct foc_callbacks_s *cb; + +#ifdef FOC_ADC_HAVE_CMN + /* Common data */ + + struct stm32_foc_adccmn_s *adc_cmn; +#endif +}; + +/**************************************************************************** + * Private Function Protototypes + ****************************************************************************/ + +/* FOC lower-half operations */ + +static int stm32_foc_configure(struct foc_dev_s *dev, + struct foc_cfg_s *cfg); +static int stm32_foc_setup(struct foc_dev_s *dev); +static int stm32_foc_shutdown(struct foc_dev_s *dev); +static int stm32_foc_start(struct foc_dev_s *dev, bool state); +static int stm32_foc_pwm_duty_set(struct foc_dev_s *dev, + foc_duty_t *duty); +static int stm32_foc_pwm_off(struct foc_dev_s *dev, bool off); +static int stm32_foc_info_get(struct foc_dev_s *dev, + struct foc_info_s *info); +static int stm32_foc_ioctl(struct foc_dev_s *dev, int cmd, + unsigned long arg); +static int stm32_foc_bind(struct foc_dev_s *dev, + struct foc_callbacks_s *cb); +static int stm32_foc_fault_clear(struct foc_dev_s *dev); +#ifdef CONFIG_MOTOR_FOC_TRACE +int stm32_foc_trace_init(struct foc_dev_s *dev); +void stm32_foc_trace(struct foc_dev_s *dev, int type, bool state); +#endif + +/* ADC handlers */ + +static int stm32_foc_adc_handler(int irq, void *context, void *arg); +static int stm32_foc_adc_calibration_handler(struct foc_dev_s *dev); +static int stm32_foc_worker_handler(struct foc_dev_s *dev); + +/* Helpers */ + +static void stm32_foc_curr_get(struct foc_dev_s *dev, + int16_t *curr, int shunts); +#ifdef CONFIG_MOTOR_FOC_BEMF_SENSE +static void stm32_foc_volt_get(struct foc_dev_s *dev, int16_t *volt); +#endif +static int stm32_foc_notifier_cfg(struct foc_dev_s *dev, uint32_t freq); +static int stm32_foc_pwm_cfg(struct foc_dev_s *dev, uint32_t freq); +static int stm32_foc_adc_cfg(struct foc_dev_s *dev); +static int stm32_foc_pwm_start(struct foc_dev_s *dev, bool state); +static int stm32_foc_adc_start(struct foc_dev_s *dev, bool state); +static int stm32_foc_calibration_start(struct foc_dev_s *dev); +static int stm32_foc_pwm_freq_set(struct foc_dev_s *dev, uint32_t freq); + +#if defined(CONFIG_STM32_FOC_ADC_CCR4) +static void stm32_foc_adc_ccr4_trg_set(struct foc_dev_s *dev, + uint32_t offset); +#elif defined(CONFIG_STM32_FOC_ADC_TRGO) +static void stm32_foc_adc_trgo_trg_set(struct foc_dev_s *dev, + uint8_t rcr); +#else +# error Invalid FOC ADC trigger +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#ifdef FOC_ADC_HAVE_CMN +# ifdef CONFIG_STM32_HAVE_IP_ADC_M3M4_V1 +/* Common for ADC123 */ + +static struct stm32_foc_adccmn_s g_stm32_foc_adccmn123 = +{ + .cntr = 0, + .lock = NXMUTEX_INITIALIZER, +}; +# endif /* CONFIG_STM32_HAVE_IP_ADC_M3M4_V1 */ + +# ifdef CONFIG_STM32_HAVE_IP_ADC_M3M4_V2 +# if defined(CONFIG_STM32_HAVE_ADC1) || defined(CONFIG_STM32_HAVE_ADC2) +/* Common for ADC12 */ + +static struct stm32_foc_adccmn_s g_stm32_foc_adccmn12 = +{ + .cntr = 0, + .lock = NXMUTEX_INITIALIZER, +}; +# endif /* CONFIG_STM32_HAVE_ADC1 || CONFIG_STM32_HAVE_ADC2 */ +# if defined(CONFIG_STM32_HAVE_ADC3) || defined(CONFIG_STM32_HAVE_ADC4) +/* Common for ADC34 */ + +static struct stm32_foc_adccmn_s g_stm32_foc_adccmn34 = +{ + .cntr = 0, + .lock = NXMUTEX_INITIALIZER, +}; +# endif /* CONFIG_STM32_HAVE_ADC3 || CONFIG_STM32_HAVE_ADC4 */ +# endif /* CONFIG_STM32_HAVE_IP_ADC_M3M4_V2 */ +#endif /* FOC_ADC_HAVE_CMN */ + +/* STM32 specific FOC data */ + +static struct stm32_foc_dev_s g_stm32_foc_dev[CONFIG_MOTOR_FOC_INST]; +static struct stm32_foc_priv_s g_stm32_foc_priv[CONFIG_MOTOR_FOC_INST]; + +/* STM32 specific FOC ops */ + +static struct foc_lower_ops_s g_stm32_foc_ops = +{ + .configure = stm32_foc_configure, + .setup = stm32_foc_setup, + .shutdown = stm32_foc_shutdown, + .start = stm32_foc_start, + .pwm_duty_set = stm32_foc_pwm_duty_set, + .pwm_off = stm32_foc_pwm_off, + .info_get = stm32_foc_info_get, + .ioctl = stm32_foc_ioctl, + .bind = stm32_foc_bind, + .fault_clear = stm32_foc_fault_clear, +#ifdef CONFIG_MOTOR_FOC_TRACE + .trace = stm32_foc_trace +#endif +}; + +/* FOC lower-half */ + +static struct foc_lower_s g_stm32_foc_lower[CONFIG_MOTOR_FOC_INST]; + +/* FOC upper-half device data */ + +static struct foc_dev_s g_foc_dev[CONFIG_MOTOR_FOC_INST]; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +#if (CONFIG_MOTOR_FOC_INST > 1) + +/**************************************************************************** + * Name: stm32_foc_sync_all + * + * Description: + * Synchronise all FOC PWM timers + * + ****************************************************************************/ + +void stm32_foc_sync_all(void) +{ + struct foc_dev_s *dev = NULL; + struct stm32_foc_dev_s *foc_dev = NULL; + uint32_t egr_reg[CONFIG_MOTOR_FOC_INST]; + int i = 0; + + /* Get registers to write */ + + for (i = 0; i < CONFIG_MOTOR_FOC_INST; i += 1) + { + /* Get FOC device */ + + dev = &g_foc_dev[i]; + + /* Get FOC lower half devices */ + + foc_dev = STM32_FOCDEV_FROM_DEV_GET(dev); + + /* Store EGR register address */ + + egr_reg[i] = foc_dev->pwm_base + STM32_GTIM_EGR_OFFSET; + } + + /* Write all registers at once */ + + for (i = 0; i < CONFIG_MOTOR_FOC_INST; i += 1) + { + /* Force update event to reset CNTR */ + + putreg32(GTIM_EGR_UG, egr_reg[i]); + } +} +#endif + +/**************************************************************************** + * Name: stm32_foc_pwm_cfg + * + * Description: + * PWM configuration for the FOC device + * + ****************************************************************************/ + +static int stm32_foc_pwm_cfg(struct foc_dev_s *dev, uint32_t freq) +{ + struct stm32_foc_board_s *board = STM32_FOCBOARD_FROM_DEV_GET(dev); + struct stm32_pwm_dev_s *pwm = PWM_FROM_FOC_DEV_GET(dev); + int ret = OK; + + DEBUGASSERT(dev); + DEBUGASSERT(board); + DEBUGASSERT(pwm); + DEBUGASSERT(freq > 0); + + /* Set phases PWM frequency */ + + ret = stm32_foc_pwm_freq_set(dev, freq); + if (ret < 0) + { + goto errout; + } + +#ifdef CONFIG_STM32_FOC_HAS_PWM_COMPLEMENTARY + /* Configure deadtime */ + + PWM_DT_UPDATE(pwm, (uint8_t)board->data->pwm_dt); +#else + UNUSED(board); +#endif + + /* Configure PWM mode for PWM outputs */ + + PWM_MODE_UPDATE(pwm, STM32_PWM_CHAN1, PWM_MODE_FOC); + PWM_MODE_UPDATE(pwm, STM32_PWM_CHAN2, PWM_MODE_FOC); +#if CONFIG_MOTOR_FOC_PHASES > 2 + PWM_MODE_UPDATE(pwm, STM32_PWM_CHAN3, PWM_MODE_FOC); +#endif +#if CONFIG_MOTOR_FOC_PHASES > 3 + PWM_MODE_UPDATE(pwm, STM32_PWM_CHAN4, PWM_MODE_FOC); +#endif + + /* Dump PWM regs */ + + PWM_DUMP_REGS(pwm, NULL); + +errout: + return ret; +} + +/**************************************************************************** + * Name: stm32_foc_pwm_freq_set + * + * Description: + * Configure the PWM frequency for the FOC device + * + ****************************************************************************/ + +static int stm32_foc_pwm_freq_set(struct foc_dev_s *dev, uint32_t freq) +{ + struct stm32_foc_priv_s *priv = STM32_FOCPIRV_FROM_DEV_GET(dev); + struct stm32_pwm_dev_s *pwm = PWM_FROM_FOC_DEV_GET(dev); + int ret = OK; + + DEBUGASSERT(dev); + DEBUGASSERT(priv); + DEBUGASSERT(pwm); + DEBUGASSERT(freq > 0); + + /* Update the PWM frequency. + * IMPORTANT: must be x2 as the PWM is in center-aligned mode. + */ + + ret = PWM_FREQ_UPDATE(pwm, (freq * 2)); + if (ret < 0) + { + goto errout; + } + + /* Store the PWM period to improve some future calculations */ + + priv->data.per = PWM_ARR_GET(pwm); + +errout: + return ret; +} + +/**************************************************************************** + * Name: stm32_foc_start + * + * Description: + * Start or stop the FOC lower-half operations + * + ****************************************************************************/ + +static int stm32_foc_start(struct foc_dev_s *dev, bool state) +{ + int ret = OK; + + DEBUGASSERT(dev); + + /* Start PWM */ + + ret = stm32_foc_pwm_start(dev, state); + if (ret < 0) + { + mtrerr("stm32_foc_pwm_start failed %d\n", ret); + goto errout; + } + + /* Start ADC */ + + ret = stm32_foc_adc_start(dev, state); + if (ret < 0) + { + mtrerr("stm32_foc_adc_start failed %d\n", ret); + goto errout; + } + +errout: + return ret; +} + +/**************************************************************************** + * Name: stm32_foc_pwm_start + * + * Description: + * Start or stop PWM + * + ****************************************************************************/ + +static int stm32_foc_pwm_start(struct foc_dev_s *dev, bool state) +{ + struct stm32_foc_board_s *board = STM32_FOCBOARD_FROM_DEV_GET(dev); + struct stm32_pwm_dev_s *pwm = PWM_FROM_FOC_DEV_GET(dev); + + DEBUGASSERT(dev); + DEBUGASSERT(board); + DEBUGASSERT(pwm); + + if (!dev->state.pwm_off) + { + /* Enable PWM outputs */ + + PWM_ALL_OUTPUTS_ENABLE(pwm, state); + } + + /* Call board-specific logic */ + + board->ops->pwm_start(dev, state); + + return OK; +} + +/**************************************************************************** + * Name: stm32_foc_adc_start + * + * Description: + * Start or stop ADC + * + ****************************************************************************/ + +static int stm32_foc_adc_start(struct foc_dev_s *dev, bool state) +{ + struct stm32_foc_dev_s *foc_dev = STM32_FOCDEV_FROM_DEV_GET(dev); + struct stm32_adc_dev_s *adc = ADC_FROM_FOC_DEV_GET(dev); + + DEBUGASSERT(dev); + DEBUGASSERT(foc_dev); + DEBUGASSERT(adc); + + if (state == false) + { + /* Disable ADC interrupts */ + + STM32_ADC_DISABLEINT(adc); + + /* Disable ADC injected conversion */ + + STM32_ADC_INJ_STARTCONV(adc, false); + + /* Reset ADC injected trigger */ + + STM32_ADC_JEXTCFG_SET(adc, foc_dev->jextval); + } + else + { + /* Configure ADC injected trigger */ + + STM32_ADC_JEXTCFG_SET(adc, foc_dev->jextval); + + /* Enable ADC interrupts */ + + STM32_ADC_ENABLEINT(adc); + + /* Enable ADC injected conversion */ + + STM32_ADC_INJ_STARTCONV(adc, true); + } + + return OK; +} + +/**************************************************************************** + * Name: stm32_foc_adc_cfg + * + * Description: + * Configure ADC for FOC worker + * + ****************************************************************************/ + +static int stm32_foc_adc_cfg(struct foc_dev_s *dev) +{ + struct stm32_foc_dev_s *foc_dev = STM32_FOCDEV_FROM_DEV_GET(dev); + + DEBUGASSERT(dev); + DEBUGASSERT(foc_dev); + + /* Set ADC interrupt handler to FOC worker */ + + foc_dev->adc_isr = stm32_foc_worker_handler; + + return OK; +} + +#if defined(CONFIG_STM32_FOC_ADC_CCR4) + +/**************************************************************************** + * Name: stm32_foc_adc_ccr4_trg_set + * + * Description: + * Configure ADC CCR4 trigger for FOC controller + * + ****************************************************************************/ + +static void stm32_foc_adc_ccr4_trg_set(struct foc_dev_s *dev, + uint32_t offset) +{ + struct stm32_pwm_dev_s *pwm = PWM_FROM_FOC_DEV_GET(dev); + + DEBUGASSERT(dev); + DEBUGASSERT(pwm); + DEBUGASSERT(offset > 0); + + /* Configure PWM mode for ADC trigger + * NOTE: + * For PWM mode 1 we have V7 when CRR=0 and V0 when CRR = ARR + * For PWM mode 2 we have V7 when CRR=ARR and V0 when CRR = 0 + */ + + PWM_MODE_UPDATE(pwm, STM32_PWM_CHAN4, PWM_MODE_ADC_TRG); + + /* Set CCR4 */ + + PWM_CCR_UPDATE(pwm, STM32_PWM_CHAN4, offset); +} + +#elif defined(CONFIG_STM32_FOC_ADC_TRGO) + +/**************************************************************************** + * Name: stm32_foc_adc_trgo_trg_set + * + * Description: + * Configure ADC TRGO trigger for FOC controller + * + ****************************************************************************/ + +static void stm32_foc_adc_trgo_trg_set(struct foc_dev_s *dev, + uint8_t rcr) +{ + struct stm32_pwm_dev_s *pwm = PWM_FROM_FOC_DEV_GET(dev); + + DEBUGASSERT(dev); + DEBUGASSERT(pwm); + + /* We want TRGO on update events only if overflow (ARR): + * 1. RCR must be configured when timer is enabled + * 2. RCR must be odd value + */ + + if (rcr % 2 == 0) + { + rcr -= 1; + } + + /* Configure RCR */ + + PWM_RCR_UPDATE(pwm, rcr); + + /* Configure TRGO */ + + PWM_TRGO_SET(pwm, FOC_PWM_TRGO); +} +#else +# error Invalid FOC ADC trigger +#endif + +/**************************************************************************** + * Name: stm32_foc_configure + * + * Description: + * Arch-specific FOC device configuration + * + ****************************************************************************/ + +static int stm32_foc_configure(struct foc_dev_s *dev, + struct foc_cfg_s *cfg) +{ + struct stm32_foc_priv_s *priv = STM32_FOCPIRV_FROM_DEV_GET(dev); + struct stm32_foc_board_s *board = STM32_FOCBOARD_FROM_DEV_GET(dev); + int ret = OK; + + DEBUGASSERT(dev); + DEBUGASSERT(cfg); + DEBUGASSERT(priv); + DEBUGASSERT(board); + DEBUGASSERT(cfg->pwm_freq > 0); + DEBUGASSERT(cfg->notifier_freq > 0); + + /* Configure ADC */ + + ret = stm32_foc_adc_cfg(dev); + if (ret < 0) + { + mtrerr("stm32_foc_adc_cfg failed %d\n", ret); + goto errout; + } + + /* Configure PWM */ + + ret = stm32_foc_pwm_cfg(dev, cfg->pwm_freq); + if (ret < 0) + { + mtrerr("stm32_foc_pwm_cfg failed %d\n", ret); + goto errout; + } + + /* Configure FOC notifier */ + + ret = stm32_foc_notifier_cfg(dev, cfg->notifier_freq); + if (ret < 0) + { + mtrerr("stm32_foc_notifier_cfg failed %d\n", ret); + goto errout; + } + + /* Configure ADC trigger - must be after PWM frequency set */ + + DEBUGASSERT(priv->data.per != 0); + +#if defined(CONFIG_STM32_FOC_ADC_CCR4) + stm32_foc_adc_ccr4_trg_set(dev, (priv->data.per - ADC_TRIGGER_OFFSET)); +#elif defined(CONFIG_STM32_FOC_ADC_TRGO) + stm32_foc_adc_trgo_trg_set(dev, (dev->cfg.pwm_freq / + priv->data.adc_freq) * 2); +#else +# error Invalid FOC ADC trigger +#endif + + /* Reset ADC interrupts counter */ + + priv->data.adcint_cntr = 0; + + /* REVISIT: synchronise instances if TRGO trigger selected */ + +#if (CONFIG_MOTOR_FOC_INST > 1) +# if defined(CONFIG_STM32_FOC_ADC_TRGO) +# error stm32_foc_sync_all breaks TRGO event on V0 vector +# endif + + /* Sync all FOC PWM timers instances. + * IMPORTANT: This must be done after PWM frequency update ! + */ + + stm32_foc_sync_all(); +#endif + +errout: + return ret; +} + +/**************************************************************************** + * Name: stm32_foc_setup + * + * Description: + * Arch-specific FOC device setup + * + ****************************************************************************/ + +static int stm32_foc_setup(struct foc_dev_s *dev) +{ + struct stm32_foc_dev_s *foc_dev = STM32_FOCDEV_FROM_DEV_GET(dev); + struct stm32_foc_board_s *board = STM32_FOCBOARD_FROM_DEV_GET(dev); + struct stm32_foc_priv_s *priv = STM32_FOCPIRV_FROM_DEV_GET(dev); + struct stm32_adc_dev_s *adc = ADC_FROM_FOC_DEV_GET(dev); +#ifdef CONFIG_MOTOR_FOC_BEMF_SENSE + struct stm32_adc_dev_s *vadc = VADC_FROM_FOC_DEV_GET(dev); +#endif + struct adc_sample_time_s stime; + int ret = OK; + + DEBUGASSERT(dev); + DEBUGASSERT(foc_dev); + DEBUGASSERT(board); + DEBUGASSERT(priv); + DEBUGASSERT(adc); +#ifdef FOC_ADC_HAVE_CMN + DEBUGASSERT(priv->adc_cmn); +#endif + + /* Call board-specific setup - must be done before TIM enable */ + + ret = board->ops->setup(dev); + if (ret < 0) + { + mtrerr("board->setup failed %d\n", ret); + goto errout; + } + + /* Setup ADC */ + + STM32_ADC_SETUP(foc_dev->adc); + +#ifdef CONFIG_MOTOR_FOC_BEMF_SENSE + /* Setup slave ADC */ + + STM32_ADC_SETUP(foc_dev->vadc); + + /* Disable interrupts for slave ADC */ + + STM32_ADC_DISABLEINT(foc_dev->vadc); + + /* Disable master and slave ADC */ + + STM32_ADC_ENABLE(foc_dev->adc, false); + STM32_ADC_ENABLE(foc_dev->vadc, false); + + /* Configure dual injected simultaneous only mode */ + + STM32_ADC_MULTICFG(foc_dev->vadc, ADC_MULTIMODE_ISM2); + + /* Enable master and slave ADC */ + + STM32_ADC_ENABLE(foc_dev->adc, true); + STM32_ADC_ENABLE(foc_dev->vadc, true); +#endif + +#ifdef FOC_ADC_HAVE_CMN + /* Lock ADC common data */ + + ret = nxmutex_lock(&priv->adc_cmn->lock); + if (ret < 0) + { + goto errout; + } + + /* Only if first device */ + + if (priv->adc_cmn->cntr == 0) + { + /* Enable ADC interrupts */ + + up_enable_irq(foc_dev->adc_irq); + } + + /* Increase counter */ + + priv->adc_cmn->cntr += 1; + + /* Unlock ADC common data */ + + nxmutex_unlock(&priv->adc_cmn->lock); +#endif + + /* Setup PWM */ + + PWM_SETUP(foc_dev->pwm); + PWM_TIM_ENABLE(foc_dev->pwm, true); + + /* Stop ADC and PWM */ + + stm32_foc_pwm_start(dev, false); + stm32_foc_adc_start(dev, false); + + /* Reset ADC handler */ + + foc_dev->adc_isr = NULL; + + /* Configure sample times for ADC channels */ + + memset(&stime, 0, sizeof(struct adc_sample_time_s)); + + stime.channels_nbr = board->data->adc_cfg->nchan; + stime.channel = board->data->adc_cfg->stime; + + STM32_ADC_SAMPLETIME_SET(adc, &stime); + STM32_ADC_SAMPLETIME_WRITE(adc); + +#ifdef CONFIG_MOTOR_FOC_BEMF_SENSE + /* Configure sample times for BEMF channels */ + + memset(&stime, 0, sizeof(struct adc_sample_time_s)); + + stime.channels_nbr = board->data->vadc_cfg->nchan; + stime.channel = board->data->vadc_cfg->stime; + + STM32_ADC_SAMPLETIME_SET(vadc, &stime); + STM32_ADC_SAMPLETIME_WRITE(vadc); +#endif + + /* Set the priority of the ADC interrupt vector */ + + ret = up_prioritize_irq(foc_dev->adc_irq, NVIC_SYSH_PRIORITY_DEFAULT); + if (ret < 0) + { + mtrerr("up_prioritize_irq failed: %d\n", ret); + goto errout; + } + + /* Attach the ADC interrupt handler */ + + ret = irq_attach(foc_dev->adc_irq, stm32_foc_adc_handler, NULL); + if (ret < 0) + { + mtrerr("irq_attach failed: %d\n", ret); + goto errout; + } + +#ifdef CONFIG_MOTOR_FOC_TRACE + /* Initialize trace interface */ + + ret = stm32_foc_trace_init(dev); + if (ret < 0) + { + mtrerr("stm32_foc_trace_init failed %d\n", ret); + goto errout; + } +#endif + + /* Start hardware calibration */ + + ret = stm32_foc_calibration_start(dev); + if (ret < 0) + { + mtrerr("stm32_foc_calibration_start failed %d\n", ret); + goto errout; + } + + /* Dump ADC regs */ + + STM32_ADC_DUMP_REGS(adc); +#ifdef CONFIG_MOTOR_FOC_BEMF_SENSE + STM32_ADC_DUMP_REGS(vadc); +#endif + +errout: + return ret; +} + +/**************************************************************************** + * Name: stm32_foc_shutdown + * + * Description: + * Arch-specific FOC device shutdown + * + ****************************************************************************/ + +static int stm32_foc_shutdown(struct foc_dev_s *dev) +{ + struct stm32_foc_dev_s *foc_dev = STM32_FOCDEV_FROM_DEV_GET(dev); + struct stm32_foc_board_s *board = STM32_FOCBOARD_FROM_DEV_GET(dev); + struct stm32_foc_priv_s *priv = STM32_FOCPIRV_FROM_DEV_GET(dev); + int ret = OK; + + DEBUGASSERT(dev); + DEBUGASSERT(foc_dev); + DEBUGASSERT(board); + DEBUGASSERT(priv); + + /* Disable PWM */ + + PWM_TIM_ENABLE(foc_dev->pwm, false); + PWM_SHUTDOWN(foc_dev->pwm); + + /* Reset ADC interrupt handler */ + + foc_dev->adc_isr = NULL; + + /* Deinitialize ADC */ + + STM32_ADC_SHUTDOWN(foc_dev->adc); + +#ifdef FOC_ADC_HAVE_CMN + /* Lock ADC common data */ + + ret = nxmutex_lock(&priv->adc_cmn->lock); + if (ret < 0) + { + goto errout; + } + + /* Decrease counter */ + + priv->adc_cmn->cntr -= 1; + + /* Deinitialize ADC only if last device */ + + if (priv->adc_cmn->cntr == 0) +#endif + { + /* Disable ADC interrupts */ + + up_disable_irq(foc_dev->adc_irq); + } + +#ifdef FOC_ADC_HAVE_CMN + /* Unlock ADC common data */ + + nxmutex_unlock(&priv->adc_cmn->lock); +#endif + + /* Call board-specific shutdown */ + + board->ops->shutdown(dev); + + /* Reset STM32 FOC volatile data */ + + memset(&priv->data, 0, sizeof(struct stm32_foc_data_s)); + +#ifdef FOC_ADC_HAVE_CMN +errout: +#endif + return ret; +} + +/**************************************************************************** + * Name: stm32_foc_ioctl + * + * Description: + * Arch-specific FOC device IOCTL + * + ****************************************************************************/ + +static int stm32_foc_ioctl(struct foc_dev_s *dev, int cmd, + unsigned long arg) +{ + struct stm32_foc_board_s *board = STM32_FOCBOARD_FROM_DEV_GET(dev); + + if (board->ops->ioctl != NULL) + { + return board->ops->ioctl(dev, cmd, arg); + } + + return -ENOTTY; +} + +/**************************************************************************** + * Name: stm32_foc_calibration_handler + * + * Description: + * ADC interrupt handler for FOC calibration + * + ****************************************************************************/ + +static int stm32_foc_adc_calibration_handler(struct foc_dev_s *dev) +{ + struct stm32_foc_priv_s *priv = STM32_FOCPIRV_FROM_DEV_GET(dev); + int i = 0; + + DEBUGASSERT(dev); + DEBUGASSERT(priv); + + if (priv->data.adcint_cntr < CAL_SAMPLES) + { + /* Get raw current samples */ + + stm32_foc_curr_get(dev, priv->data.curr_raw, CONFIG_MOTOR_FOC_SHUNTS); + + /* Get sum */ + + for (i = 0; i < CONFIG_MOTOR_FOC_SHUNTS; i += 1) + { + priv->data.curr_offset[i] += priv->data.curr_raw[i]; + } + } + + else if (priv->data.adcint_cntr == CAL_SAMPLES) + { + /* Get average offset */ + + for (i = 0; i < CONFIG_MOTOR_FOC_SHUNTS; i += 1) + { + priv->data.curr_offset[i] = + (priv->data.curr_offset[i] / CAL_SAMPLES); + } + + /* Post semaphore that calibration is done */ + + nxsem_post(&priv->cal_done_sem); + } + else + { + /* Calibration completed */ + } + + return OK; +} + +/**************************************************************************** + * Name: stm32_foc_adc_handler + * + * Description: + * ADC interrupt handler + * + ****************************************************************************/ + +static int stm32_foc_adc_handler(int irq, void *context, void *arg) +{ + struct foc_dev_s *dev = NULL; + struct stm32_foc_priv_s *priv = NULL; +#ifdef CONFIG_MOTOR_FOC_TRACE + struct stm32_foc_board_s *board = NULL; +#endif + struct stm32_adc_dev_s *adc = NULL; + struct stm32_foc_dev_s *foc_dev = NULL; + uint32_t pending = 0; + int ret = OK; + int i = 0; + + UNUSED(irq); + UNUSED(context); + UNUSED(arg); + + /* Loop through all FOC instances to prevent context switching if + * all instances are synchronized. + */ + + for (i = 0; i < CONFIG_MOTOR_FOC_INST; i += 1) + { + /* Reset pointer to a device */ + + dev = NULL; + + /* Get ADC device associated with FOC device */ + + adc = ADC_FROM_FOC_DEV_GET(&g_foc_dev[i]); + DEBUGASSERT(adc); + + /* Get ADC pending interrupts */ + + pending = STM32_ADC_INT_GET(adc); + + /* Only if end of injected sequence */ + + if (pending & FOC_ADC_ISR_FOC) + { + /* Found device with penidng ADC interrupt */ + + dev = &g_foc_dev[i]; + } + + /* Handle pending interrupt for device */ + + if (dev != NULL) + { + priv = STM32_FOCPIRV_FROM_DEV_GET(dev); + DEBUGASSERT(priv); + + foc_dev = STM32_FOCDEV_FROM_DEV_GET(dev); + DEBUGASSERT(foc_dev); + +#ifdef CONFIG_MOTOR_FOC_TRACE + board = STM32_FOCBOARD_FROM_DEV_GET(dev); + DEBUGASSERT(board); + + board->ops->trace(dev, FOC_TRACE_LOWER, true); +#endif + /* Clear pending */ + + STM32_ADC_INT_ACK(adc, pending); + + /* Call interrupt handler if registered */ + + if (foc_dev->adc_isr != NULL) + { + ret = foc_dev->adc_isr(dev); + if (ret < 0) + { + DEBUGPANIC(); + } + } + + /* Increase interrupt counter */ + + priv->data.adcint_cntr += 1; + +#ifdef CONFIG_MOTOR_FOC_TRACE + board->ops->trace(dev, FOC_TRACE_LOWER, false); +#endif + } + } + + return ret; +} + +/**************************************************************************** + * Name: stm32_foc_worker_handler + * + * Description: + * Handle ADC conversion and do FOC device work. + * + ****************************************************************************/ + +static int stm32_foc_worker_handler(struct foc_dev_s *dev) +{ + struct stm32_foc_priv_s *priv = STM32_FOCPIRV_FROM_DEV_GET(dev); + struct stm32_foc_board_s *board = STM32_FOCBOARD_FROM_DEV_GET(dev); + struct stm32_adc_dev_s *adc = ADC_FROM_FOC_DEV_GET(dev); + int ret = OK; + + DEBUGASSERT(dev); + DEBUGASSERT(priv); + DEBUGASSERT(adc); + DEBUGASSERT(board); + DEBUGASSERT(priv->cb); + DEBUGASSERT(priv->cb->notifier); + + if (priv->data.adcint_cntr % priv->data.notifier_div == 0) + { + /* Get raw current samples */ + + stm32_foc_curr_get(dev, priv->data.curr_raw, CONFIG_MOTOR_FOC_SHUNTS); + + /* Get phase currents */ + + ret = board->ops->current_get(dev, + priv->data.curr_raw, + priv->data.curr); + +#ifdef CONFIG_MOTOR_FOC_BEMF_SENSE + /* Get raw voltage samples */ + + stm32_foc_volt_get(dev, priv->data.volt_raw); + + /* Get BEMF voltages */ + + ret = board->ops->voltage_get(dev, + priv->data.volt_raw, + priv->data.volt); +#endif + + /* Call upper-half worker callback */ + +#ifdef CONFIG_MOTOR_FOC_BEMF_SENSE + priv->cb->notifier(dev, priv->data.curr, priv->data.volt); +#else + priv->cb->notifier(dev, priv->data.curr, NULL); +#endif + } + + return ret; +} + +/**************************************************************************** + * Name: stm32_foc_calibration_start + * + * Description: + * Start FOC hardware calibration (ADC offsets) + * + ****************************************************************************/ + +static int stm32_foc_calibration_start(struct foc_dev_s *dev) +{ + struct stm32_foc_dev_s *foc_dev = STM32_FOCDEV_FROM_DEV_GET(dev); + struct stm32_foc_priv_s *priv = STM32_FOCPIRV_FROM_DEV_GET(dev); + struct stm32_foc_board_s *board = STM32_FOCBOARD_FROM_DEV_GET(dev); + struct stm32_pwm_dev_s *pwm = PWM_FROM_FOC_DEV_GET(dev); + struct stm32_adc_dev_s *adc = ADC_FROM_FOC_DEV_GET(dev); +#ifdef CONFIG_MOTOR_FOC_BEMF_SENSE + struct stm32_adc_dev_s *vadc = VADC_FROM_FOC_DEV_GET(dev); +#endif + uint8_t i = 0; + uint8_t ch = 0; + int ret = OK; + + DEBUGASSERT(dev); + DEBUGASSERT(foc_dev); + DEBUGASSERT(priv); + DEBUGASSERT(board); + DEBUGASSERT(pwm); + DEBUGASSERT(adc); + + /* Call board-specific */ + + board->ops->calibration(dev, true); + + /* Force high side transistors to low state and + * low side tranisstors to high state + */ + + PWM_MODE_UPDATE(pwm, STM32_PWM_CHAN1, PWM_MODE_HSLO_LSHI); + PWM_MODE_UPDATE(pwm, STM32_PWM_CHAN2, PWM_MODE_HSLO_LSHI); +#if CONFIG_MOTOR_FOC_PHASES > 2 + PWM_MODE_UPDATE(pwm, STM32_PWM_CHAN3, PWM_MODE_HSLO_LSHI); +#endif +#if CONFIG_MOTOR_FOC_PHASES > 3 + PWM_MODE_UPDATE(pwm, STM32_PWM_CHAN4, PWM_MODE_HSLO_LSHI); +#endif + + /* Set PWM to trigger ADC */ + + ret = stm32_foc_pwm_freq_set(dev, CAL_FREQ); + if (ret < 0) + { + goto errout; + } + + /* Configure ADC interrupt handler to calibration */ + + foc_dev->adc_isr = stm32_foc_adc_calibration_handler; + + /* Configure ADC trigger - must be after PWM frequency set */ + + DEBUGASSERT(priv->data.per != 0); + +#if defined(CONFIG_STM32_FOC_ADC_CCR4) + stm32_foc_adc_ccr4_trg_set(dev, (priv->data.per - ADC_TRIGGER_OFFSET)); +#elif defined(CONFIG_STM32_FOC_ADC_TRGO) + stm32_foc_adc_trgo_trg_set(dev, 1); +#else +# error Invalid FOC ADC trigger +#endif + + /* Reset ADC interrupts counter */ + + priv->data.adcint_cntr = 0; + + /* Start ADC and PWM */ + + stm32_foc_adc_start(dev, true); + stm32_foc_pwm_start(dev, true); + + /* Wait for calibration done semaphore + * All work is done in adc_calibration_handler + */ + + ret = nxsem_wait_uninterruptible(&priv->cal_done_sem); + if (ret < 0) + { + goto errout; + } + + /* Stop ADC and PWM */ + + stm32_foc_pwm_start(dev, false); + stm32_foc_adc_start(dev, false); + + /* Reset ADC interrupt handler */ + + foc_dev->adc_isr = NULL; + + /* Clear last ADC data */ + + for (i = 0; i < CONFIG_MOTOR_FOC_SHUNTS; i += 1) + { + priv->data.curr_raw[i] = 0; + } + + /* Set ADC hardware offset for current channels (only injected channels) */ + + for (i = 0; i < CONFIG_MOTOR_FOC_SHUNTS; i += 1) + { + /* Get channel */ + + ch = board->data->adc_cfg->chan[board->data->adc_cfg->regch + i]; + + /* Write offset */ + + STM32_ADC_OFFSET_SET(adc, ch, i, priv->data.curr_offset[i]); + } + +#ifdef CONFIG_MOTOR_FOC_BEMF_SENSE + + /* TODO: BEMF sensing calibartion */ + + for (i = 0; i < CONFIG_MOTOR_FOC_PHASES; i += 1) + { + priv->data.volt_offset[i] = 0; + } + + /* Clear last ADC data */ + + for (i = 0; i < CONFIG_MOTOR_FOC_PHASES; i += 1) + { + priv->data.volt_raw[i] = 0; + } + + /* Set ADC hardware offset for voltage channels (only injected channels) */ + + for (i = 0; i < CONFIG_MOTOR_FOC_PHASES; i += 1) + { + /* Get channel */ + + ch = board->data->vadc_cfg->chan[board->data->vadc_cfg->regch + i]; + + /* Write offset */ + + STM32_ADC_OFFSET_SET(vadc, ch, i, priv->data.volt_offset[i]); + } +#endif + + mtrinfo("ADC offset calibration - DONE!\n"); + +errout: + + /* Call board-specific */ + + board->ops->calibration(dev, false); + + /* Reset ADC interrupts counter */ + + priv->data.adcint_cntr = 0; + + return ret; +} + +/**************************************************************************** + * Name: stm32_foc_pwm_duty_set + * + * Description: + * Set the 3-phase PWM duty cycle + * + ****************************************************************************/ + +static int stm32_foc_pwm_duty_set(struct foc_dev_s *dev, + foc_duty_t *duty) +{ + struct stm32_foc_priv_s *priv = STM32_FOCPIRV_FROM_DEV_GET(dev); + struct stm32_foc_dev_s *foc_dev = STM32_FOCDEV_FROM_DEV_GET(dev); + uint16_t ccr[CONFIG_MOTOR_FOC_PHASES]; + + DEBUGASSERT(dev); + DEBUGASSERT(duty); + DEBUGASSERT(priv); + DEBUGASSERT(foc_dev); + DEBUGASSERT(priv->data.per != 0); + + /* Get the CCR for a given duty cycle */ + + DEBUGASSERT(duty[0] >= 0); + DEBUGASSERT(duty[1] >= 0); +#if CONFIG_MOTOR_FOC_PHASES > 2 + DEBUGASSERT(duty[2] >= 0); +#endif +#if CONFIG_MOTOR_FOC_PHASES > 3 + DEBUGASSERT(duty[3] >= 0); +#endif + + ccr[0] = (uint16_t)b16toi(b16muli(duty[0], priv->data.per)); + ccr[1] = (uint16_t)b16toi(b16muli(duty[1], priv->data.per)); +#if CONFIG_MOTOR_FOC_PHASES > 2 + ccr[2] = (uint16_t)b16toi(b16muli(duty[2], priv->data.per)); +#endif +#if CONFIG_MOTOR_FOC_PHASES > 3 + ccr[3] = (uint16_t)b16toi(b16muli(duty[3], priv->data.per)); +#endif + + /* Write directly to timer registers. + * We are not using the PWM_CCR_UPDATE interface as it is too slow + */ + + putreg32(ccr[0], (foc_dev->pwm_base + STM32_GTIM_CCR1_OFFSET)); + putreg32(ccr[1], (foc_dev->pwm_base + STM32_GTIM_CCR2_OFFSET)); +#if CONFIG_MOTOR_FOC_PHASES > 2 + putreg32(ccr[2], (foc_dev->pwm_base + STM32_GTIM_CCR3_OFFSET)); +#endif +#if CONFIG_MOTOR_FOC_PHASES > 3 + putreg32(ccr[3], (foc_dev->pwm_base + STM32_GTIM_CCR4_OFFSET)); +#endif + + return OK; +} + +/**************************************************************************** + * Name: stm32_foc_pwm_off + * + * Description: + * Set the 3-phase bridge switches in off state. + * + ****************************************************************************/ + +static int stm32_foc_pwm_off(struct foc_dev_s *dev, bool off) +{ + struct stm32_pwm_dev_s *pwm = PWM_FROM_FOC_DEV_GET(dev); + + if (off) + { + /* Force all transistors to low state */ + + PWM_MODE_UPDATE(pwm, STM32_PWM_CHAN1, PWM_MODE_HSHI_LSLO); + PWM_MODE_UPDATE(pwm, STM32_PWM_CHAN2, PWM_MODE_HSHI_LSLO); +#if CONFIG_MOTOR_FOC_PHASES > 2 + PWM_MODE_UPDATE(pwm, STM32_PWM_CHAN3, PWM_MODE_HSHI_LSLO); +#endif +#if CONFIG_MOTOR_FOC_PHASES > 3 + PWM_MODE_UPDATE(pwm, STM32_PWM_CHAN4, PWM_MODE_HSHI_LSLO); +#endif + + /* Disable complementary outputs */ + + PWM_OUTPUTS_ENABLE(pwm, PMW_OUTPUTS_ALL_COMP, false); + } + else + { + /* Restore FOC operation modes */ + + PWM_ALL_OUTPUTS_ENABLE(pwm, true); + + PWM_MODE_UPDATE(pwm, STM32_PWM_CHAN1, PWM_MODE_FOC); + PWM_MODE_UPDATE(pwm, STM32_PWM_CHAN2, PWM_MODE_FOC); +#if CONFIG_MOTOR_FOC_PHASES > 2 + PWM_MODE_UPDATE(pwm, STM32_PWM_CHAN3, PWM_MODE_FOC); +#endif +#if CONFIG_MOTOR_FOC_PHASES > 3 + PWM_MODE_UPDATE(pwm, STM32_PWM_CHAN4, PWM_MODE_FOC); +#endif + } + + return OK; +} + +/**************************************************************************** + * Name: stm32_foc_info_get + * + * Description: + * Get HW configuration for FOC device + * + ****************************************************************************/ + +static int stm32_foc_info_get(struct foc_dev_s *dev, struct foc_info_s *info) +{ + struct stm32_foc_board_s *board = STM32_FOCBOARD_FROM_DEV_GET(dev); + + DEBUGASSERT(dev); + DEBUGASSERT(board); + + /* Get data from board configuration */ + + return board->ops->info_get(dev, info); +} + +/**************************************************************************** + * Name: stm32_foc_curr_get + * + * Description: + * Get current samples from ADC + * + ****************************************************************************/ + +static void stm32_foc_curr_get(struct foc_dev_s *dev, + int16_t *curr, int shunts) +{ + struct stm32_foc_priv_s *priv = STM32_FOCPIRV_FROM_DEV_GET(dev); + struct stm32_adc_dev_s *adc = ADC_FROM_FOC_DEV_GET(dev); + int i = 0; + + DEBUGASSERT(dev); + DEBUGASSERT(priv); + DEBUGASSERT(adc); + DEBUGASSERT(curr); + + for (i = 0; i < shunts; i += 1) + { + /* Get raw current samples. + * We have ADC offset enabled for injected channels so this + * gives us signed values. + * NOTE: ADC value is 11 bits + sign. + */ + +#ifdef CONFIG_STM32_FOC_G4_ADCCHAN0_WORKAROUND + /* Ignore first channel */ + + curr[i] = (int16_t)STM32_ADC_INJDATA_GET(adc, (i + 1)); +#else + curr[i] = (int16_t)STM32_ADC_INJDATA_GET(adc, i); +#endif + } +} + +#ifdef CONFIG_MOTOR_FOC_BEMF_SENSE +/**************************************************************************** + * Name: stm32_foc_volt_get + * + * Description: + * Get voltage samples from ADC + * + ****************************************************************************/ + +static void stm32_foc_volt_get(struct foc_dev_s *dev, int16_t *volt) +{ + struct stm32_foc_priv_s *priv = STM32_FOCPIRV_FROM_DEV_GET(dev); + struct stm32_adc_dev_s *vadc = VADC_FROM_FOC_DEV_GET(dev); + int i = 0; + + DEBUGASSERT(dev); + DEBUGASSERT(priv); + DEBUGASSERT(vadc); + DEBUGASSERT(volt); + + /* Make sure the conversion is complete. + * It is possible that the ADC master sequence will end in front of + * the slave sequence. In that case we just busy-wait. + * In the worst case scenario the slave conversion is one channel behind + * the master conversion (2 current channels vs 3 voltage channels). + * + * Another solution is to make sure that both conversions has the same + * length, but this makes the code much more complex. + */ + + while ((FOC_ADC_ISR_FOC & STM32_ADC_INT_GET(vadc)) == 0); + + /* Clear status */ + + STM32_ADC_INT_ACK(vadc, FOC_ADC_ISR_FOC); + + for (i = 0; i < CONFIG_MOTOR_FOC_PHASES; i += 1) + { + /* Get raw voltage samples. + * We have ADC offset enabled for injected channels so this + * gives us signed values. + * NOTE: ADC value is 11 bits + sign. + */ + +#ifdef CONFIG_STM32_FOC_G4_ADCCHAN0_WORKAROUND + /* Ignore first channel */ + + volt[i] = (int16_t)STM32_ADC_INJDATA_GET(vadc, (i + 1)); +#else + volt[i] = (int16_t)STM32_ADC_INJDATA_GET(vadc, i); +#endif + } +} +#endif + +/**************************************************************************** + * Name: stm32_foc_notifier_cfg + * + * Description: + * Configure FOC notifier + * + ****************************************************************************/ + +static int stm32_foc_notifier_cfg(struct foc_dev_s *dev, uint32_t freq) +{ + struct stm32_foc_priv_s *priv = STM32_FOCPIRV_FROM_DEV_GET(dev); + int ret = OK; + + DEBUGASSERT(dev); + DEBUGASSERT(priv); + DEBUGASSERT(freq > 0); + DEBUGASSERT(dev->cfg.pwm_freq > 0); + + /* Validate input: + * 1. must be fraction of PWM frequency + */ + + if (dev->cfg.pwm_freq % freq != 0) + { + ret = -EINVAL; + goto errout; + } + +#if defined(CONFIG_STM32_FOC_ADC_CCR4) + /* ADC interrupts frequency is PWM frequency */ + + priv->data.adc_freq = dev->cfg.pwm_freq; + + /* Get worker divider */ + + priv->data.notifier_div = (dev->cfg.pwm_freq / freq); + +#elif defined(CONFIG_STM32_FOC_ADC_TRGO) + /* Call work on every ADC interrupt */ + + priv->data.notifier_div = 1; + + /* ADC interrupts frequency is notifier frequency */ + + priv->data.adc_freq = freq; +#else +# error Invalid FOC ADC trigger +#endif + +errout: + return ret; +} + +/**************************************************************************** + * Name: stm32_foc_bind + * + * Description: + * Bind lower-half FOC device with upper-half FOC logic + * + ****************************************************************************/ + +static int stm32_foc_bind(struct foc_dev_s *dev, + struct foc_callbacks_s *cb) +{ + struct stm32_foc_priv_s *priv = STM32_FOCPIRV_FROM_DEV_GET(dev); + int ret = OK; + + DEBUGASSERT(dev); + DEBUGASSERT(cb); + DEBUGASSERT(priv); + + /* Validate callbacks */ + + DEBUGASSERT(cb->notifier); + + /* Bind upper-half FOC device callbacks */ + + priv->cb = cb; + return ret; +} + +/**************************************************************************** + * Name: stm32_foc_fault_clear + * + * Description: + * Arch-specific fault clear + * + ****************************************************************************/ + +static int stm32_foc_fault_clear(struct foc_dev_s *dev) +{ + struct stm32_foc_board_s *board = STM32_FOCBOARD_FROM_DEV_GET(dev); + + DEBUGASSERT(dev); + DEBUGASSERT(board); + + return board->ops->fault_clear(dev); +} + +#ifdef CONFIG_MOTOR_FOC_TRACE + +/**************************************************************************** + * Name: stm32_foc_trace + * + * Description: + * Arch-specific trace initialization + * + ****************************************************************************/ + +int stm32_foc_trace_init(struct foc_dev_s *dev) +{ + struct stm32_foc_board_s *board = STM32_FOCBOARD_FROM_DEV_GET(dev); + + DEBUGASSERT(dev); + DEBUGASSERT(board); + + /* Call board-specific logic */ + + return board->ops->trace_init(dev); +} + +/**************************************************************************** + * Name: stm32_foc_trace + * + * Description: + * Arch-specific trace + * + ****************************************************************************/ + +void stm32_foc_trace(struct foc_dev_s *dev, int type, bool state) +{ + struct stm32_foc_board_s *board = STM32_FOCBOARD_FROM_DEV_GET(dev); + + DEBUGASSERT(dev); + DEBUGASSERT(board); + + /* Call board-specific logic */ + + board->ops->trace(dev, type, state); +} +#endif + +/**************************************************************************** + * Name: stm32_foc_adc_init + * + * Description: + * Initialize ADC instance + * + ****************************************************************************/ + +struct adc_dev_s *stm32_foc_adc_init(struct stm32_foc_adc_s *adc_cfg) +{ + struct adc_dev_s *adc_dev = NULL; + int i = 0; +#ifdef CONFIG_STM32_FOC_G4_ADCCHAN0_WORKAROUND + uint8_t *adc_chan = NULL; + uint8_t adc_nchan = 0; +#endif + + DEBUGASSERT(adc_cfg); + DEBUGASSERT(adc_cfg != NULL); + DEBUGASSERT(adc_cfg->pins != NULL); + DEBUGASSERT(adc_cfg->chan != NULL); + + /* Configure pins as analog inputs for the selected channels */ + + for (i = 0; i < adc_cfg->nchan; i++) + { + stm32_configgpio(adc_cfg->pins[i]); + } + + /* STM32G4 ADC channel 0 unwanted conversion workaround */ + +#ifdef CONFIG_STM32_FOC_G4_ADCCHAN0_WORKAROUND + /* Add one dummy channel to conversion */ + + adc_nchan = (adc_cfg->nchan + 1); + + /* Allocate memory for the extended list of channels */ + + adc_chan = zalloc(adc_nchan); + if (adc_chan == NULL) + { + goto errout; + } + + /* Copy regular channels first */ + + for (i = 0; i < adc_cfg->regch; i += 1) + { + adc_chan[i] = adc_cfg->chan[i]; + } + + /* Add dummy channel at the beginning of injected channels */ + + adc_chan[adc_cfg->regch] = 0; + + /* Copy injected channels */ + + for (i = (adc_cfg->regch + 1); i < adc_nchan; i += 1) + { + adc_chan[i] = adc_cfg->chan[i - 1]; + } +#endif /* CONFIG_STM32_FOC_G4_ADCCHAN0_WORKAROUND */ + + /* Get the ADC interface */ + +#ifdef CONFIG_STM32_FOC_G4_ADCCHAN0_WORKAROUND + adc_dev = stm32_adcinitialize(adc_cfg->intf, + adc_chan, + adc_nchan); + + free(adc_chan); +#else + adc_dev = stm32_adcinitialize(adc_cfg->intf, + adc_cfg->chan, + adc_cfg->nchan); +#endif + + return adc_dev; + +#ifdef CONFIG_STM32_FOC_G4_ADCCHAN0_WORKAROUND +errout: + return NULL; +#endif +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_foc_initialize + * + * Description: + * Initialize the FOC lower-half. + * + * Input Parameters: + * inst - FOC instance number + * board - FOC board-specific data + * + * Returned Value: + * Valid lower-half FOC controller structure reference on success; + * NULL on failure + * + ****************************************************************************/ + +struct foc_dev_s * +stm32_foc_initialize(int inst, struct stm32_foc_board_s *board) +{ + struct foc_dev_s *dev = NULL; + struct stm32_foc_adc_s *adc_cfg = NULL; + struct foc_lower_s *foc_lower = NULL; + struct stm32_foc_dev_s *foc_dev = NULL; + struct stm32_foc_priv_s *foc_priv = NULL; +#ifdef FOC_ADC_HAVE_CMN + struct stm32_foc_adccmn_s *adc_cmn = NULL; +#endif + uint32_t adc_irq = 0; + uint32_t pwm_base = 0; + uint32_t jextval = 0; + uint8_t pwm_inst = 0; + uint8_t adc_inst = 0; + uint32_t pwmfzbit = 0; + + DEBUGASSERT(board != NULL); + DEBUGASSERT(board->ops != NULL); + DEBUGASSERT(board->data != NULL); + + /* Assert board-specific ops */ + + DEBUGASSERT(board->ops->setup); + DEBUGASSERT(board->ops->shutdown); + DEBUGASSERT(board->ops->calibration); + DEBUGASSERT(board->ops->fault_clear); + DEBUGASSERT(board->ops->pwm_start); + DEBUGASSERT(board->ops->current_get); + DEBUGASSERT(board->ops->info_get); +#ifdef CONFIG_MOTOR_FOC_TRACE + DEBUGASSERT(board->ops->trace_init); + DEBUGASSERT(board->ops->trace); +#endif + + /* Get FOC instance configuration */ + + switch (inst) + { +#ifdef CONFIG_STM32_FOC_FOC0 + case 0: + { + pwm_inst = FOC0_PWM; + adc_inst = FOC0_ADC; + adc_irq = FOC0_ADC_IRQ; + pwm_base = FOC0_PWM_BASE; + jextval = FOC0_ADC_JEXT; + pwmfzbit = FOC0_PWM_FZ_BIT; +#ifdef FOC_ADC_HAVE_CMN + adc_cmn = FOC0_ADC_CMN; +#endif + break; + } +#endif + +#ifdef CONFIG_STM32_FOC_FOC1 + case 1: + { + pwm_inst = FOC1_PWM; + adc_inst = FOC1_ADC; + adc_irq = FOC1_ADC_IRQ; + pwm_base = FOC1_PWM_BASE; + jextval = FOC1_ADC_JEXT; + pwmfzbit = FOC1_PWM_FZ_BIT; +#ifdef FOC_ADC_HAVE_CMN + adc_cmn = FOC1_ADC_CMN; +#endif + break; + } +#endif + + default: + { + mtrerr("Unsupported STM32 FOC instance %d\n", inst); + set_errno(EINVAL); + goto errout; + } + } + + /* Get STM32 FOC lower-half */ + + foc_lower = &g_stm32_foc_lower[inst]; + + /* Connect STM32 FOC private data with ops and data */ + + foc_lower->data = &g_stm32_foc_priv[inst]; + foc_lower->ops = &g_stm32_foc_ops; + foc_priv = foc_lower->data; + + /* Reset STM32 FOC private data */ + + memset(foc_lower->data, 0, sizeof(struct stm32_foc_priv_s)); + + /* Connect STM32 FOC devices */ + + foc_priv->dev = &g_stm32_foc_dev[inst]; + + /* Connect board data */ + + foc_priv->board = board; + +#ifdef FOC_ADC_HAVE_CMN + /* Connect ADC common data */ + + foc_priv->adc_cmn = adc_cmn; +#endif + + /* Get arch-specific device */ + + foc_dev = (struct stm32_foc_dev_s *)foc_priv->dev; + DEBUGASSERT(foc_dev); + + /* Store STM32 FOC devices data */ + + foc_dev->adc_inst = adc_inst; + foc_dev->pwm_inst = pwm_inst; + foc_dev->pwm_base = pwm_base; + foc_dev->jextval = jextval; + foc_dev->adc_irq = adc_irq; + + /* Get the advanced timer PWM interface */ + + foc_dev->pwm = (struct stm32_pwm_dev_s *)stm32_pwminitialize(pwm_inst); + if (foc_dev->pwm == NULL) + { + mtrerr("Failed to get PWM%d interface\n", pwm_inst); + set_errno(EINVAL); + goto errout; + } + + /* Get ADC configuration */ + + adc_cfg = board->data->adc_cfg; + + /* Make sure that we are using the appropriate ADC interface */ + + if (adc_inst != adc_cfg->intf) + { + mtrerr("FOC ADC configuration doesn't match %d, %d\n", + adc_inst, adc_cfg->intf); + set_errno(EINVAL); + goto errout; + } + + /* Get ADC instance */ + + foc_dev->adc_dev = stm32_foc_adc_init(adc_cfg); + if (foc_dev->adc_dev == NULL) + { + mtrerr("Failed to initialize FOC ADC%d interface\n", adc_cfg->intf); + set_errno(EINVAL); + goto errout; + } + + /* Get ADC private part */ + + foc_dev->adc = (struct stm32_adc_dev_s *)foc_dev->adc_dev->ad_priv; + +#ifdef CONFIG_MOTOR_FOC_BEMF_SENSE + /* Get ADC configuration */ + + adc_cfg = board->data->vadc_cfg; + + /* Make sure that we are using the slave ADC */ + + if (adc_inst != adc_cfg->intf - 1) + { + mtrerr("BEMF ADC must be the first slave instance of the main ADC!"); + set_errno(EINVAL); + goto errout; + } + + /* Get ADC instance */ + + foc_dev->vadc_dev = stm32_foc_adc_init(adc_cfg); + if (foc_dev->vadc_dev == NULL) + { + mtrerr("Failed to initialize BEMF ADC%d interface\n", adc_cfg->intf); + set_errno(EINVAL); + goto errout; + } + + /* Get ADC private part */ + + foc_dev->vadc = (struct stm32_adc_dev_s *)foc_dev->vadc_dev->ad_priv; +#endif + + /* Froze timer and reset outputs when core is halted. + * TODO: move this to stm32_pwm.c and configure from Kconfig + */ + + modifyreg32(FOC_PWM_FZ_REG, 0, pwmfzbit); + + /* Initialize calibration semaphore */ + + nxsem_init(&foc_priv->cal_done_sem, 0, 0); + + /* Get FOC device */ + + dev = &g_foc_dev[inst]; + + /* Connect the lower-half device with the upper-half device */ + + dev->lower = (void *)foc_lower; + + /* Return upper-half driver instance */ + + return dev; + +errout: + return NULL; +} + +/**************************************************************************** + * Name: stm32_foc_adcget + * + * Description: + * Get a handler for ADC device associated with a given FOC device. + * + * The FOC lower-half logic uses only injected ADC channels for operations. + * We are using a custom ADC interrupt logic that cannot handle + * additional regular channels conversion. This limitation can be overcome + * with the DMA transfer. + * With this function we can get a handler to the ADC device and use it + * to register a standard ADC character device. + * + * Input Parameters: + * lower - a pointer to the uperr-half FOC device + * + * Returned Value: + * Valid ADC device structure reference on success; a NULL on failure + * + ****************************************************************************/ + +struct adc_dev_s *stm32_foc_adcget(struct foc_dev_s *dev) +{ + struct stm32_foc_dev_s *foc_dev = STM32_FOCDEV_FROM_DEV_GET(dev); + + DEBUGASSERT(dev); + DEBUGASSERT(foc_dev); + + /* Return STM32 ADC device */ + + return foc_dev->adc_dev; +} diff --git a/arch/arm/src/common/stm32/stm32_foc_m3m4_v1.h b/arch/arm/src/common/stm32/stm32_foc_m3m4_v1.h new file mode 100644 index 0000000000000..58cddf08b2b45 --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_foc_m3m4_v1.h @@ -0,0 +1,203 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_foc_m3m4_v1.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_FOC_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_FOC_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include "stm32_adc.h" + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/* ADC configuration for the FOC device */ + +struct stm32_foc_adc_s +{ + /* ADC interface used by the FOC */ + + uint8_t intf; + + /* The number of ADC channels (regular + injected) */ + + uint8_t nchan; + + /* The number of auxiliary regular channels (only for DMA transfer) */ + + uint8_t regch; + + /* The list of ADC channels (regular first, then injected) */ + + uint8_t *chan; + + /* The list of ADC pins */ + + uint32_t *pins; + + /* The list of ADC channels sample time configuration */ + + adc_channel_t *stime; +}; + +/* Board-specific operations. + * + * These are calls from the lower-half to the board-specific logic. + * They must be provided by board-specific logic even if not used. + */ + +struct stm32_foc_board_ops_s +{ + /* Board-specific setup */ + + int (*setup)(struct foc_dev_s *dev); + + /* Board-specific shutdown */ + + int (*shutdown)(struct foc_dev_s *dev); + + /* Board-specific ioctl (optional) */ + + int (*ioctl)(struct foc_dev_s *dev, int cmd, unsigned long arg); + + /* Board-specific calibration setup */ + + int (*calibration)(struct foc_dev_s *dev, bool state); + + /* Board-specific fault clear */ + + int (*fault_clear)(struct foc_dev_s *dev); + + /* Board-specific PWM start */ + + int (*pwm_start)(struct foc_dev_s *dev, bool state); + + /* Get phase currents */ + + int (*current_get)(struct foc_dev_s *dev, int16_t *curr_raw, + foc_current_t *curr); + + /* Board-specific info */ + + int (*info_get)(struct foc_dev_s *dev, struct foc_info_s *cfg); + +#ifdef CONFIG_MOTOR_FOC_BEMF_SENSE + /* Get BEMF voltage */ + + int (*voltage_get)(struct foc_dev_s *dev, int16_t *volt_raw, + foc_voltage_t *volt); +#endif + +#ifdef CONFIG_MOTOR_FOC_TRACE + /* FOC trace interface setup */ + + int (*trace_init)(struct foc_dev_s *dev); + + /* FOC trace */ + + void (*trace)(struct foc_dev_s *dev, int type, bool state); +#endif +}; + +/* Board-specific FOC data */ + +struct stm32_foc_board_data_s +{ + /* ADC configuration */ + + struct stm32_foc_adc_s *adc_cfg; + +#ifdef CONFIG_MOTOR_FOC_BEMF_SENSE + /* BEMF voltage ADC configuration */ + + struct stm32_foc_adc_s *vadc_cfg; +#endif + + /* PWM deadtime register value */ + + uint8_t pwm_dt; +}; + +/* Board-specific FOC configuration */ + +struct stm32_foc_board_s +{ + /* Board-specific FOC operations */ + + struct stm32_foc_board_ops_s *ops; + + /* Board-specific FOC data */ + + struct stm32_foc_board_data_s *data; +}; + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Name: stm32_foc_initialize + ****************************************************************************/ + +struct foc_dev_s * +stm32_foc_initialize(int inst, struct stm32_foc_board_s *board); + +/**************************************************************************** + * Name: stm32_foc_adcget + ****************************************************************************/ + +struct adc_dev_s *stm32_foc_adcget(struct foc_dev_s *dev); + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_FOC_H */ diff --git a/arch/arm/src/common/stm32/stm32_freerun.h b/arch/arm/src/common/stm32/stm32_freerun.h new file mode 100644 index 0000000000000..155917f7ea3af --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_freerun.h @@ -0,0 +1,81 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_freerun.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_FREERUN_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_FREERUN_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include "stm32_tim.h" + +#ifdef CONFIG_STM32_FREERUN + +struct stm32_freerun_s +{ + uint8_t chan; + uint8_t width; + struct stm32_tim_dev_s *tch; + uint32_t frequency; +#ifndef CONFIG_CLOCK_TIMEKEEPING + uint32_t overflow; +#endif +#ifdef CONFIG_CLOCK_TIMEKEEPING + uint64_t counter_mask; +#endif +}; + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +int stm32_freerun_initialize(struct stm32_freerun_s *freerun, int chan, + uint16_t resolution); +#ifndef CONFIG_CLOCK_TIMEKEEPING +int stm32_freerun_counter(struct stm32_freerun_s *freerun, + struct timespec *ts); +#else +int stm32_freerun_counter(struct stm32_freerun_s *freerun, + uint64_t *counter); +#endif +int stm32_freerun_uninitialize(struct stm32_freerun_s *freerun); + +#undef EXTERN +#ifdef __cplusplus +} +#endif + +#endif /* CONFIG_STM32_FREERUN */ + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_FREERUN_H */ diff --git a/arch/arm/src/common/stm32/stm32_freerun_m3m4_v1.c b/arch/arm/src/common/stm32/stm32_freerun_m3m4_v1.c new file mode 100644 index 0000000000000..e8122d5ef413c --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_freerun_m3m4_v1.c @@ -0,0 +1,301 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_freerun_m3m4_v1.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include + +#include +#include + +#include "stm32_freerun.h" + +#ifdef CONFIG_STM32_FREERUN + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_freerun_handler + * + * Description: + * Timer interrupt callback. When the freerun timer counter overflows, + * this interrupt will occur. We will just increment an overflow count. + * + * Input Parameters: + * tch - The handle that represents the timer state + * arg - An opaque argument provided when the interrupt was registered + * sr - The value of the timer interrupt status register at the time + * that the interrupt occurred. + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifndef CONFIG_CLOCK_TIMEKEEPING +static int stm32_freerun_handler(int irq, void *context, void *arg) +{ + struct stm32_freerun_s *freerun = (struct stm32_freerun_s *) arg; + + DEBUGASSERT(freerun != NULL && freerun->overflow < UINT32_MAX); + freerun->overflow++; + + STM32_TIM_ACKINT(freerun->tch, GTIM_SR_UIF); + return OK; +} +#endif /* CONFIG_CLOCK_TIMEKEEPING */ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_freerun_initialize + * + * Description: + * Initialize the freerun timer wrapper + * + * Input Parameters: + * freerun Caller allocated instance of the freerun state structure + * chan Timer counter channel to be used. + * resolution The required resolution of the timer in units of + * microseconds. NOTE that the range is restricted to the + * range of uint16_t (excluding zero). + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned + * on failure. + * + ****************************************************************************/ + +int stm32_freerun_initialize(struct stm32_freerun_s *freerun, int chan, + uint16_t resolution) +{ + uint32_t frequency; + + tmrinfo("chan=%d resolution=%d usec\n", chan, resolution); + DEBUGASSERT(freerun != NULL && resolution > 0); + + /* Get the TC frequency the corresponds to the requested resolution */ + + frequency = USEC_PER_SEC / (uint32_t)resolution; + freerun->frequency = frequency; + + freerun->tch = stm32_tim_init(chan); + if (!freerun->tch) + { + tmrerr("ERROR: Failed to allocate TIM%d\n", chan); + return -EBUSY; + } + + STM32_TIM_SETCLOCK(freerun->tch, frequency); + + /* Initialize the remaining fields in the state structure and return + * success. + */ + + freerun->chan = chan; + freerun->width = STM32_TIM_GETWIDTH(freerun->tch); + +#ifdef CONFIG_CLOCK_TIMEKEEPING + freerun->counter_mask = 0xffffffffull; +#endif + +#ifndef CONFIG_CLOCK_TIMEKEEPING + freerun->overflow = 0; + + /* Set up to receive the callback when the counter overflow occurs */ + + STM32_TIM_SETISR(freerun->tch, stm32_freerun_handler, freerun, 0); +#endif + + /* Set timer period */ + + STM32_TIM_SETPERIOD(freerun->tch, + (uint32_t)((1ull << freerun->width) - 1)); + + /* Start the counter */ + + STM32_TIM_SETMODE(freerun->tch, STM32_TIM_MODE_UP); + +#ifndef CONFIG_CLOCK_TIMEKEEPING + STM32_TIM_ACKINT(freerun->tch, GTIM_SR_UIF); + STM32_TIM_ENABLEINT(freerun->tch, GTIM_DIER_UIE); +#endif + + return OK; +} + +/**************************************************************************** + * Name: stm32_freerun_counter + * + * Description: + * Read the counter register of the free-running timer. + * + * Input Parameters: + * freerun Caller allocated instance of the freerun state structure. This + * structure must have been previously initialized via a call to + * stm32_freerun_initialize(); + * ts The location in which to return the time from the free-running + * timer. + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned + * on failure. + * + ****************************************************************************/ + +#ifndef CONFIG_CLOCK_TIMEKEEPING + +int stm32_freerun_counter(struct stm32_freerun_s *freerun, + struct timespec *ts) +{ + uint64_t usec; + uint32_t counter; + uint32_t verify; + uint32_t overflow; + uint32_t sec; + int pending; + irqstate_t flags; + + DEBUGASSERT(freerun && freerun->tch && ts); + + /* Temporarily disable the overflow counter. NOTE that we have to be + * careful here because stm32_tc_getpending() will reset the pending + * interrupt status. If we do not handle the overflow here then, it will + * be lost. + */ + + flags = enter_critical_section(); + + overflow = freerun->overflow; + counter = STM32_TIM_GETCOUNTER(freerun->tch); + pending = STM32_TIM_CHECKINT(freerun->tch, 0); + verify = STM32_TIM_GETCOUNTER(freerun->tch); + + /* If an interrupt was pending before we re-enabled interrupts, + * then the overflow needs to be incremented. + */ + + if (pending) + { + STM32_TIM_ACKINT(freerun->tch, GTIM_SR_UIF); + + /* Increment the overflow count and use the value of the + * guaranteed to be AFTER the overflow occurred. + */ + + overflow++; + counter = verify; + + /* Update freerun overflow counter. */ + + freerun->overflow = overflow; + } + + leave_critical_section(flags); + + tmrinfo("counter=%" PRIu32 " (%" PRIu32 ") overflow=%" PRIu32 + ", pending=%i\n", + counter, verify, overflow, pending); + tmrinfo("frequency=%" PRIu32 "\n", freerun->frequency); + + /* Convert the whole thing to units of microseconds. + * + * frequency = ticks / second + * seconds = ticks * frequency + * usecs = (ticks * USEC_PER_SEC) / frequency; + */ + + usec = ((((uint64_t)overflow << freerun->width) + + (uint64_t)counter) * USEC_PER_SEC) / + freerun->frequency; + + /* And return the value of the timer */ + + sec = (uint32_t)(usec / USEC_PER_SEC); + ts->tv_sec = sec; + ts->tv_nsec = (usec - (sec * USEC_PER_SEC)) * NSEC_PER_USEC; + + tmrinfo("usec=%llu ts=(%jd, %ld)\n", + usec, (intmax_t)ts->tv_sec, ts->tv_nsec); + + return OK; +} + +#else /* CONFIG_CLOCK_TIMEKEEPING */ + +int stm32_freerun_counter(struct stm32_freerun_s *freerun, uint64_t *counter) +{ + *counter = STM32_TIM_GETCOUNTER(freerun->tch); + return OK; +} + +#endif /* CONFIG_CLOCK_TIMEKEEPING */ + +/**************************************************************************** + * Name: stm32_freerun_uninitialize + * + * Description: + * Stop the free-running timer and release all resources that it uses. + * + * Input Parameters: + * freerun Caller allocated instance of the freerun state structure. This + * structure must have been previously initialized via a call to + * stm32_freerun_initialize(); + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned + * on failure. + * + ****************************************************************************/ + +int stm32_freerun_uninitialize(struct stm32_freerun_s *freerun) +{ + DEBUGASSERT(freerun && freerun->tch); + + /* Now we can disable the timer interrupt and disable the timer. */ + + STM32_TIM_DISABLEINT(freerun->tch, GTIM_DIER_UIE); + STM32_TIM_SETMODE(freerun->tch, STM32_TIM_MODE_DISABLED); + STM32_TIM_SETISR(freerun->tch, NULL, NULL, 0); + + /* Free the timer */ + + stm32_tim_deinit(freerun->tch); + freerun->tch = NULL; + + return OK; +} + +#endif /* CONFIG_STM32_ONESHOT */ diff --git a/arch/arm/src/common/stm32/stm32_fsmc.h b/arch/arm/src/common/stm32/stm32_fsmc.h new file mode 100644 index 0000000000000..15951027c411a --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_fsmc.h @@ -0,0 +1,38 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_fsmc.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_COMPAT_STM32FSMC_H +#define __ARCH_ARM_SRC_COMMON_COMPAT_STM32FSMC_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#if defined(CONFIG_STM32_HAVE_IP_FSMC_M3M4_V1) +# include "stm32_fsmc_m3m4_v1.h" +#else +# error "Unsupported STM32 stm32_fsmc" +#endif + +#endif /* __ARCH_ARM_SRC_COMMON_COMPAT_STM32FSMC_H */ diff --git a/arch/arm/src/common/stm32/stm32_fsmc_m3m4_v1.c b/arch/arm/src/common/stm32/stm32_fsmc_m3m4_v1.c new file mode 100644 index 0000000000000..c72cf09477f2b --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_fsmc_m3m4_v1.c @@ -0,0 +1,85 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_fsmc_m3m4_v1.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "stm32.h" + +#if defined(CONFIG_STM32_FSMC) + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_fsmc_enable + * + * Description: + * Enable clocking to the FSMC. + * + ****************************************************************************/ + +#if defined(CONFIG_STM32_STM32L15XX) || defined(CONFIG_STM32_STM32F10XX) + +void stm32_fsmc_enable(void) +{ + modifyreg32(STM32_RCC_AHBENR, 0, RCC_AHBENR_FSMCEN); +} + +#elif defined(CONFIG_STM32_HAVE_IP_FSMC_M3M4_V1) + +void stm32_fsmc_enable(void) +{ + modifyreg32(STM32_RCC_AHB3ENR, 0, RCC_AHB3ENR_FSMCEN); +} + +#endif + +/**************************************************************************** + * Name: stm32_fsmc_disable + * + * Description: + * Disable clocking to the FSMC. + * + ****************************************************************************/ + +#if defined(CONFIG_STM32_STM32L15XX) || defined(CONFIG_STM32_STM32F10XX) + +void stm32_fsmc_disable(void) +{ + modifyreg32(STM32_RCC_AHBENR, RCC_AHBENR_FSMCEN, 0); +} + +#elif defined(CONFIG_STM32_HAVE_IP_FSMC_M3M4_V1) + +void stm32_fsmc_disable(void) +{ + modifyreg32(STM32_RCC_AHB3ENR, RCC_AHB3ENR_FSMCEN, 0); +} + +#endif + +#endif /* CONFIG_STM32_FSMC */ diff --git a/arch/arm/src/common/stm32/stm32_fsmc_m3m4_v1.h b/arch/arm/src/common/stm32/stm32_fsmc_m3m4_v1.h new file mode 100644 index 0000000000000..215ce47c016f7 --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_fsmc_m3m4_v1.h @@ -0,0 +1,80 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_fsmc_m3m4_v1.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_FSMC_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_FSMC_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#if defined(CONFIG_STM32_HAVE_IP_FSMC_M3M4_V1) + +#include "chip.h" +#include "hardware/stm32_fsmc.h" + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Name: stm32_fsmc_enable + * + * Description: + * Enable clocking to the FSMC. + * + ****************************************************************************/ + +void stm32_fsmc_enable(void); + +/**************************************************************************** + * Name: stm32_fsmc_disable + * + * Description: + * Disable clocking to the FSMC. + * + ****************************************************************************/ + +void stm32_fsmc_disable(void); + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ + +#endif /* CONFIG_STM32_HAVE_IP_FSMC_M3M4_V1 */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_FSMC_H */ diff --git a/arch/arm/src/common/stm32/stm32_gpio.h b/arch/arm/src/common/stm32/stm32_gpio.h new file mode 100644 index 0000000000000..f4910cabef1de --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_gpio.h @@ -0,0 +1,40 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_gpio.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_COMPAT_STM32_GPIO_H +#define __ARCH_ARM_SRC_COMMON_COMPAT_STM32_GPIO_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#if defined(CONFIG_STM32_HAVE_IP_GPIO_M0_V1) +# include "stm32_gpio_m0_v1.h" +#elif defined(CONFIG_STM32_HAVE_IP_GPIO_M3M4_V1) +# include "stm32_gpio_m3m4_v1v2.h" +#else +# error "Unsupported STM32 GPIO" +#endif + +#endif /* __ARCH_ARM_SRC_COMMON_COMPAT_STM32_GPIO_H */ diff --git a/arch/arm/src/common/stm32/stm32_gpio_m0_v1.c b/arch/arm/src/common/stm32/stm32_gpio_m0_v1.c new file mode 100644 index 0000000000000..3313cba03cdd7 --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_gpio_m0_v1.c @@ -0,0 +1,451 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_gpio_m0_v1.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include + +#include +#include +#include + +#include "arm_internal.h" +#include "chip.h" +#include "stm32_gpio.h" + +#if defined(CONFIG_STM32_HAVE_IP_EXTI_V1) +# include "hardware/stm32_syscfg.h" +#elif defined(CONFIG_STM32_HAVE_IP_EXTI_V2) +# include "hardware/stm32_exti.h" +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static spinlock_t g_configgpio_lock = SP_UNLOCKED; + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/* Base addresses for each GPIO block */ + +const uint32_t g_gpiobase[STM32_NPORTS] = +{ +#if STM32_NPORTS > 0 + STM32_GPIOA_BASE, /* One GPIO ports, GPIOA */ +#endif +#if STM32_NPORTS > 1 + STM32_GPIOB_BASE, /* Two GPIO ports, GPIOA-B */ +#endif +#if STM32_NPORTS > 2 + STM32_GPIOC_BASE, /* Three GPIO ports, GPIOA-C */ +#endif +#if STM32_NPORTS > 3 + STM32_GPIOD_BASE, /* Four GPIO ports, GPIOA-D */ +#endif +#if defined(STM32_GPIOE_BASE) + STM32_GPIOE_BASE, /* GPIOE */ +#endif +#if defined(STM32_GPIOF_BASE) + STM32_GPIOF_BASE, /* GPIOF */ +#endif +#if defined(STM32_GPIOH_BASE) + STM32_GPIOH_BASE, /* GPIOH */ +#endif +}; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Function: stm32_gpioinit + * + * Description: + * Based on configuration within the .config file, it does: + * - Remaps positions of alternative functions. + * + * Typically called from stm32_start(). + * + * Assumptions: + * This function is called early in the initialization sequence so that + * no mutual exclusion is necessary. + * + ****************************************************************************/ + +void stm32_gpioinit(void) +{ +} + +/**************************************************************************** + * Name: stm32_configgpio + * + * Description: + * Configure a GPIO pin based on bit-encoded description of the pin. + * Once it is configured as Alternative (GPIO_ALT|GPIO_CNF_AFPP|...) + * function, it must be unconfigured with stm32_unconfiggpio() with + * the same cfgset first before it can be set to non-alternative function. + * + * Returned Value: + * OK on success + * A negated errno value on invalid port, or when pin is locked as ALT + * function. + * + * To-Do: Auto Power Enable + ****************************************************************************/ + +int stm32_configgpio(uint32_t cfgset) +{ + uintptr_t base; + uint32_t regval; + uint32_t setting; + unsigned int regoffset; + unsigned int port; + unsigned int pin; + unsigned int pos; + unsigned int pinmode; + irqstate_t flags; + + /* Verify that this hardware supports the select GPIO port */ + + port = (cfgset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; + if (port >= STM32_NPORTS) + { + return -EINVAL; + } + + /* Get the port base address */ + + base = g_gpiobase[port]; + + /* Get the pin number and select the port configuration register for that + * pin + */ + + pin = (cfgset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT; + + /* Set up the mode register (and remember whether the pin mode) */ + + switch (cfgset & GPIO_MODE_MASK) + { + default: + case GPIO_INPUT: /* Input mode */ + pinmode = GPIO_MODER_INPUT; + break; + + case GPIO_OUTPUT: /* General purpose output mode */ + stm32_gpiowrite(cfgset, + (cfgset & GPIO_OUTPUT_SET) != 0); /* Set the initial output value */ + pinmode = GPIO_MODER_OUTPUT; + break; + + case GPIO_ALT: /* Alternate function mode */ + pinmode = GPIO_MODER_ALT; + break; + + case GPIO_ANALOG: /* Analog mode */ + pinmode = GPIO_MODER_ANALOG; + break; + } + + /* Interrupts must be disabled from here on out so that we have mutually + * exclusive access to all of the GPIO configuration registers. + */ + + flags = spin_lock_irqsave(&g_configgpio_lock); + + /* Now apply the configuration to the mode register */ + + regval = getreg32(base + STM32_GPIO_MODER_OFFSET); + regval &= ~GPIO_MODER_MASK(pin); + regval |= ((uint32_t)pinmode << GPIO_MODER_SHIFT(pin)); + putreg32(regval, base + STM32_GPIO_MODER_OFFSET); + + /* Set up the pull-up/pull-down configuration (all but analog pins) */ + + setting = GPIO_PUPDR_NONE; + if (pinmode != GPIO_MODER_ANALOG) + { + switch (cfgset & GPIO_PUPD_MASK) + { + default: + case GPIO_FLOAT: /* No pull-up, pull-down */ + break; + + case GPIO_PULLUP: /* Pull-up */ + setting = GPIO_PUPDR_PULLUP; + break; + + case GPIO_PULLDOWN: /* Pull-down */ + setting = GPIO_PUPDR_PULLDOWN; + break; + } + } + + regval = getreg32(base + STM32_GPIO_PUPDR_OFFSET); + regval &= ~GPIO_PUPDR_MASK(pin); + regval |= (setting << GPIO_PUPDR_SHIFT(pin)); + putreg32(regval, base + STM32_GPIO_PUPDR_OFFSET); + + /* Set the alternate function (Only alternate function pins) */ + + if (pinmode == GPIO_MODER_ALT) + { + setting = (cfgset & GPIO_AF_MASK) >> GPIO_AF_SHIFT; + } + else + { + setting = 0; + } + + if (pin < 8) + { + regoffset = STM32_GPIO_AFRL_OFFSET; + pos = pin; + } + else + { + regoffset = STM32_GPIO_AFRH_OFFSET; + pos = pin - 8; + } + + regval = getreg32(base + regoffset); + regval &= ~GPIO_AFR_MASK(pos); + regval |= (setting << GPIO_AFR_SHIFT(pos)); + putreg32(regval, base + regoffset); + + /* Set speed (Only outputs and alternate function pins) */ + + if (pinmode == GPIO_MODER_OUTPUT || pinmode == GPIO_MODER_ALT) + { + switch (cfgset & GPIO_SPEED_MASK) + { + default: +#if defined(STM32_GPIO_VERY_LOW_SPEED) + case GPIO_SPPED_VERYLOW: /* Very Low speed output */ + setting = GPIO_OSPEED_VERYLOW; + break; + + case GPIO_SPEED_LOW: /* Low speed output */ + setting = GPIO_OSPEED_LOW; + break; + + case GPIO_SPEED_MEDIUM: /* Medium speed output */ + setting = GPIO_OSPEED_MEDIUM; + break; + + case GPIO_SPEED_HIGH: /* High speed output */ + setting = GPIO_OSPEED_HIGH; + break; +#else + case GPIO_SPEED_LOW: /* Low speed output */ + setting = GPIO_OSPEED_LOW; + break; + + case GPIO_SPEED_MEDIUM: /* Medium speed output */ + setting = GPIO_OSPEED_MEDIUM; + break; + + case GPIO_SPEED_HIGH: /* High speed output */ + setting = GPIO_OSPEED_HIGH; + break; +#endif + } + } + else + { + setting = 0; + } + + regval = getreg32(base + STM32_GPIO_OSPEED_OFFSET); + regval &= ~GPIO_OSPEED_MASK(pin); + regval |= (setting << GPIO_OSPEED_SHIFT(pin)); + putreg32(regval, base + STM32_GPIO_OSPEED_OFFSET); + + /* Set push-pull/open-drain (Only outputs and alternate function pins) */ + + regval = getreg32(base + STM32_GPIO_OTYPER_OFFSET); + setting = GPIO_OTYPER_OD(pin); + + if ((pinmode == GPIO_MODER_OUTPUT || pinmode == GPIO_MODER_ALT) && + (cfgset & GPIO_OPENDRAIN) != 0) + { + regval |= setting; + } + else + { + regval &= ~setting; + } + + putreg32(regval, base + STM32_GPIO_OTYPER_OFFSET); + + /* Otherwise, it is an input pin. + * Should it configured as an EXTI interrupt? + */ + + if ((pinmode != GPIO_MODER_OUTPUT) && ((cfgset & GPIO_EXTI) != 0)) + { + uint32_t regaddr; + int shift; + +#if defined(CONFIG_STM32_HAVE_IP_EXTI_V1) + /* Set the bits in the SYSCFG EXTICR register */ + + regaddr = STM32_SYSCFG_EXTICR(pin); + regval = getreg32(regaddr); + shift = SYSCFG_EXTICR_EXTI_SHIFT(pin); + regval &= ~(SYSCFG_EXTICR_PORT_MASK << shift); + regval |= (((uint32_t)port) << shift); + + putreg32(regval, regaddr); +#elif defined(CONFIG_STM32_HAVE_IP_EXTI_V2) + /* Set the bits in the EXTI EXTICR register */ + + regaddr = STM32_EXTI_EXTICR(pin); + regval = getreg32(regaddr); + shift = EXTI_EXTICR_EXTI_SHIFT(pin); + regval &= ~(EXTI_EXTICR_PORT_MASK << shift); + regval |= (((uint32_t)port) << shift); + + putreg32(regval, regaddr); +#else +# error unknown EXTI IP core +#endif + } + + spin_unlock_irqrestore(&g_configgpio_lock, flags); + return OK; +} + +/**************************************************************************** + * Name: stm32_unconfiggpio + * + * Description: + * Unconfigure a GPIO pin based on bit-encoded description of the pin, set + * it into default HiZ state (and possibly mark it's unused) and unlock it + * whether it was previously selected as alternative function + * (GPIO_ALT|GPIO_CNF_AFPP|...). + * + * This is a safety function and prevents hardware from shocks, as + * unexpected write to the Timer Channel Output GPIO to fixed '1' or '0' + * while it should operate in PWM mode could produce excessive on-board + * currents and trigger over-current/alarm function. + * + * Returned Value: + * OK on success + * A negated errno value on invalid port + * + * To-Do: Auto Power Disable + ****************************************************************************/ + +int stm32_unconfiggpio(uint32_t cfgset) +{ + /* Reuse port and pin number and set it to default HiZ INPUT */ + + cfgset &= GPIO_PORT_MASK | GPIO_PIN_MASK; + cfgset |= GPIO_INPUT | GPIO_FLOAT; + + /* To-Do: Mark its unuse for automatic power saving options */ + + return stm32_configgpio(cfgset); +} + +/**************************************************************************** + * Name: stm32_gpiowrite + * + * Description: + * Write one or zero to the selected GPIO pin + * + ****************************************************************************/ + +void stm32_gpiowrite(uint32_t pinset, bool value) +{ + uint32_t base; + uint32_t bit; + unsigned int port; + unsigned int pin; + + port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; + if (port < STM32_NPORTS) + { + /* Get the port base address */ + + base = g_gpiobase[port]; + + /* Get the pin number */ + + pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT; + + /* Set or clear the output on the pin */ + + if (value) + { + bit = GPIO_BSRR_SET(pin); + } + else + { + bit = GPIO_BSRR_RESET(pin); + } + + putreg32(bit, base + STM32_GPIO_BSRR_OFFSET); + } +} + +/**************************************************************************** + * Name: stm32_gpioread + * + * Description: + * Read one or zero from the selected GPIO pin + * + ****************************************************************************/ + +bool stm32_gpioread(uint32_t pinset) +{ + uint32_t base; + unsigned int port; + unsigned int pin; + + port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; + if (port < STM32_NPORTS) + { + /* Get the port base address */ + + base = g_gpiobase[port]; + + /* Get the pin number and return the input state of that pin */ + + pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT; + return ((getreg32(base + STM32_GPIO_IDR_OFFSET) & (1 << pin)) != 0); + } + + return 0; +} diff --git a/arch/arm/src/common/stm32/stm32_gpio_m0_v1.h b/arch/arm/src/common/stm32/stm32_gpio_m0_v1.h new file mode 100644 index 0000000000000..43990a8514a6e --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_gpio_m0_v1.h @@ -0,0 +1,367 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_gpio_m0_v1.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_GPIO_V2_M0_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_GPIO_V2_M0_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#ifndef __ASSEMBLY__ +# include +# include +#endif + +#include +#include + +#include "chip.h" +#include "hardware/stm32_gpio.h" +#include "hardware/stm32_pinmap.h" + +/**************************************************************************** + * Pre-Processor Declarations + ****************************************************************************/ + +/* Bit-encoded input to stm32_configgpio() */ + +/* Each port bit of the general-purpose I/O (GPIO) ports can be individually + * configured by software in several modes: + * + * - Input floating + * - Input pull-up + * - Input-pull-down + * - Output open-drain with pull-up or pull-down capability + * - Output push-pull with pull-up or pull-down capability + * - Alternate function push-pull with pull-up or pull-down capability + * - Alternate function open-drain with pull-up or pull-down capability + * - Analog + * + * 20-bit Encoding: 1111 1111 1100 0000 0000 + * 9876 5432 1098 7654 3210 + * ---- ---- ---- ---- ---- + * Inputs: MMUU .... ...X PPPP BBBB + * Outputs: MMUU .... FFOV PPPP BBBB + * Alternate Functions: MMUU .AAA FFO. PPPP BBBB + * Analog: MM.. .... .... PPPP BBBB + */ + +/* Mode: + * + * 1111 1111 1100 0000 0000 + * 9876 5432 1098 7654 3210 + * ---- ---- ---- ---- ---- + * MM.. .... .... .... .... + */ + +#define GPIO_MODE_SHIFT (18) /* Bits 18-19: GPIO port mode */ +#define GPIO_MODE_MASK (3 << GPIO_MODE_SHIFT) +# define GPIO_INPUT (0 << GPIO_MODE_SHIFT) /* Input mode */ +# define GPIO_OUTPUT (1 << GPIO_MODE_SHIFT) /* General purpose output mode */ +# define GPIO_ALT (2 << GPIO_MODE_SHIFT) /* Alternate function mode */ +# define GPIO_ANALOG (3 << GPIO_MODE_SHIFT) /* Analog mode */ + +/* Input/output pull-ups/downs (not used with analog): + * + * 1111 1111 1100 0000 0000 + * 9876 5432 1098 7654 3210 + * ---- ---- ---- ---- ---- + * ..UU .... .... .... .... + */ + +#define GPIO_PUPD_SHIFT (16) /* Bits 16-17: Pull-up/pull down */ +#define GPIO_PUPD_MASK (3 << GPIO_PUPD_SHIFT) +# define GPIO_FLOAT (0 << GPIO_PUPD_SHIFT) /* No pull-up, pull-down */ +# define GPIO_PULLUP (1 << GPIO_PUPD_SHIFT) /* Pull-up */ +# define GPIO_PULLDOWN (2 << GPIO_PUPD_SHIFT) /* Pull-down */ + +/* Alternate Functions: + * + * 1111 1111 1100 0000 0000 + * 9876 5432 1098 7654 3210 + * ---- ---- ---- ---- ---- + * .... .AAA .... .... .... + */ + +#define GPIO_AF_SHIFT (12) /* Bits 12-14: Alternate function */ +#define GPIO_AF_MASK (7 << GPIO_AF_SHIFT) +# define GPIO_AF(n) ((n) << GPIO_AF_SHIFT) +# define GPIO_AF0 (0 << GPIO_AF_SHIFT) +# define GPIO_AF1 (1 << GPIO_AF_SHIFT) +# define GPIO_AF2 (2 << GPIO_AF_SHIFT) +# define GPIO_AF3 (3 << GPIO_AF_SHIFT) +# define GPIO_AF4 (4 << GPIO_AF_SHIFT) +# define GPIO_AF5 (5 << GPIO_AF_SHIFT) +# define GPIO_AF6 (6 << GPIO_AF_SHIFT) +# define GPIO_AF7 (7 << GPIO_AF_SHIFT) + +/* Output/Alt function frequency selection: + * + * 1111 1111 1100 0000 0000 + * 9876 5432 1098 7654 3210 + * ---- ---- ---- ---- ---- + * .... .... FF.. .... .... + */ + +#define GPIO_SPEED_SHIFT (10) /* Bits 10-11: GPIO frequency selection */ +#define GPIO_SPEED_MASK (3 << GPIO_SPEED_SHIFT) + +#if defined(STM32_GPIO_VERY_LOW_SPEED) +# define GPIO_SPPED_VERYLOW (0 << GPIO_SPEED_SHIFT) /* 400 kHz Very low speed */ +# define GPIO_SPEED_LOW (1 << GPIO_SPEED_SHIFT) /* 2 MHz Low speed output */ +# define GPIO_SPEED_MEDIUM (2 << GPIO_SPEED_SHIFT) /* 10 MHz Medium speed output */ +# define GPIO_SPEED_HIGH (3 << GPIO_SPEED_SHIFT) /* 40 MHz High speed output */ +#else +# define GPIO_SPEED_LOW (0 << GPIO_SPEED_SHIFT) /* 2 MHz Low speed output */ +# define GPIO_SPEED_MEDIUM (1 << GPIO_SPEED_SHIFT) /* 10 MHz Medium speed output */ +# define GPIO_SPEED_HIGH (3 << GPIO_SPEED_SHIFT) /* 50 MHz High speed output */ +#endif + +/* Output/Alt function type selection: + * + * 1111 1111 1100 0000 0000 + * 9876 5432 1098 7654 3210 + * ---- ---- ---- ---- ---- + * .... .... ..O. .... .... + */ + +#define GPIO_OPENDRAIN (1 << 9) /* Bit9: 1=Open-drain output */ +#define GPIO_PUSHPULL (0) /* Bit9: 0=Push-pull output */ + +/* If the pin is a GPIO digital output, then this identifies the initial + * output value. + * If the pin is an input, this bit is overloaded to provide the qualifier + * to distinguish input pull-up and -down: + * + * 1111 1111 1100 0000 0000 + * 9876 5432 1098 7654 3210 + * ---- ---- ---- ---- ---- + * .... .... ...V .... .... + */ + +#define GPIO_OUTPUT_SET (1 << 8) /* Bit 8: If output, initial value of output */ +#define GPIO_OUTPUT_CLEAR (0) + +/* External interrupt selection (GPIO inputs only): + * + * 1111 1111 1100 0000 0000 + * 9876 5432 1098 7654 3210 + * ---- ---- ---- ---- ---- + * .... .... ...X .... .... + */ + +#define GPIO_EXTI (1 << 8) /* Bit 8: Configure as EXTI interrupt */ + +/* This identifies the GPIO port: + * + * 1111 1111 1100 0000 0000 + * 9876 5432 1098 7654 3210 + * ---- ---- ---- ---- ---- + * .... .... .... PPPP .... + */ + +#define GPIO_PORT_SHIFT (4) /* Bit 4-7: Port number */ +#define GPIO_PORT_MASK (15 << GPIO_PORT_SHIFT) +# define GPIO_PORTA (0 << GPIO_PORT_SHIFT) /* GPIOA */ +# define GPIO_PORTB (1 << GPIO_PORT_SHIFT) /* GPIOB */ +# define GPIO_PORTC (2 << GPIO_PORT_SHIFT) /* GPIOC */ +# define GPIO_PORTD (3 << GPIO_PORT_SHIFT) /* GPIOD */ +#if defined (CONFIG_STM32_STM32F03X) +# define GPIO_PORTF (4 << GPIO_PORT_SHIFT) /* GPIOF */ +#else +# define GPIO_PORTE (4 << GPIO_PORT_SHIFT) /* GPIOE */ +#if defined (CONFIG_ARCH_CHIP_STM32L0) +# define GPIO_PORTH (5 << GPIO_PORT_SHIFT) /* GPIOH */ +#else +# define GPIO_PORTF (5 << GPIO_PORT_SHIFT) /* GPIOF */ +#endif +#endif + +/* This identifies the bit in the port: + * + * 1111 1111 1100 0000 0000 + * 9876 5432 1098 7654 3210 + * ---- ---- ---- ---- ---- + * .... .... .... .... BBBB + */ + +#define GPIO_PIN_SHIFT (0) /* Bits 0-3: GPIO number: 0-15 */ +#define GPIO_PIN_MASK (15 << GPIO_PIN_SHIFT) +# define GPIO_PIN0 (0 << GPIO_PIN_SHIFT) +# define GPIO_PIN1 (1 << GPIO_PIN_SHIFT) +# define GPIO_PIN2 (2 << GPIO_PIN_SHIFT) +# define GPIO_PIN3 (3 << GPIO_PIN_SHIFT) +# define GPIO_PIN4 (4 << GPIO_PIN_SHIFT) +# define GPIO_PIN5 (5 << GPIO_PIN_SHIFT) +# define GPIO_PIN6 (6 << GPIO_PIN_SHIFT) +# define GPIO_PIN7 (7 << GPIO_PIN_SHIFT) +# define GPIO_PIN8 (8 << GPIO_PIN_SHIFT) +# define GPIO_PIN9 (9 << GPIO_PIN_SHIFT) +# define GPIO_PIN10 (10 << GPIO_PIN_SHIFT) +# define GPIO_PIN11 (11 << GPIO_PIN_SHIFT) +# define GPIO_PIN12 (12 << GPIO_PIN_SHIFT) +# define GPIO_PIN13 (13 << GPIO_PIN_SHIFT) +# define GPIO_PIN14 (14 << GPIO_PIN_SHIFT) +# define GPIO_PIN15 (15 << GPIO_PIN_SHIFT) + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/* Base addresses for each GPIO block */ + +EXTERN const uint32_t g_gpiobase[STM32_NPORTS]; + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_configgpio + * + * Description: + * Configure a GPIO pin based on bit-encoded description of the pin. + * Once it is configured as Alternative (GPIO_ALT|GPIO_CNF_AFPP|...) + * function, it must be unconfigured with stm32_unconfiggpio() with + * the same cfgset first before it can be set to non-alternative function. + * + * Returned Value: + * OK on success + * ERROR on invalid port, or when pin is locked as ALT function. + * + ****************************************************************************/ + +int stm32_configgpio(uint32_t cfgset); + +/**************************************************************************** + * Name: stm32_unconfiggpio + * + * Description: + * Unconfigure a GPIO pin based on bit-encoded description of the pin, set + * it into default HiZ state (and possibly mark it's unused) and unlock it + * whether it was previously selected as alternative function + * (GPIO_ALT|GPIO_CNF_AFPP|...). + * + * This is a safety function and prevents hardware from shocks, as + * unexpected write to the Timer Channel Output GPIO to fixed '1' or '0' + * while it should operate in PWM mode could produce excessive on-board + * currents and trigger over-current/alarm function. + * + * Returned Value: + * OK on success + * ERROR on invalid port + * + ****************************************************************************/ + +int stm32_unconfiggpio(uint32_t cfgset); + +/**************************************************************************** + * Name: stm32_gpiowrite + * + * Description: + * Write one or zero to the selected GPIO pin + * + ****************************************************************************/ + +void stm32_gpiowrite(uint32_t pinset, bool value); + +/**************************************************************************** + * Name: stm32_gpioread + * + * Description: + * Read one or zero from the selected GPIO pin + * + ****************************************************************************/ + +bool stm32_gpioread(uint32_t pinset); + +/**************************************************************************** + * Name: stm32_gpiosetevent + * + * Description: + * Sets/clears GPIO based event and interrupt triggers. + * + * Input Parameters: + * pinset - GPIO pin configuration + * risingedge - Enables interrupt on rising edges + * fallingedge - Enables interrupt on falling edges + * event - Generate event when set + * func - When non-NULL, generate interrupt + * arg - Argument passed to the interrupt callback + * + * Returned Value: + * Zero (OK) is returned on success, otherwise a negated errno value is + * returned to indicate the nature of the failure. + * + ****************************************************************************/ + +int stm32_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, + bool event, xcpt_t func, void *arg); + +/**************************************************************************** + * Function: stm32_dumpgpio + * + * Description: + * Dump all GPIO registers associated with the provided base address + * + ****************************************************************************/ + +#ifdef CONFIG_DEBUG_FEATURES +int stm32_dumpgpio(uint32_t pinset, const char *msg); +#else +# define stm32_dumpgpio(p,m) +#endif + +/**************************************************************************** + * Function: stm32_gpioinit + * + * Description: + * Based on configuration within the .config file, it does: + * - Remaps positions of alternative functions. + * + * Typically called from stm32_start(). + * + ****************************************************************************/ + +void stm32_gpioinit(void); + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_GPIO_V2_M0_H */ diff --git a/arch/arm/src/common/stm32/stm32_gpio_m3m4_v1v2.c b/arch/arm/src/common/stm32/stm32_gpio_m3m4_v1v2.c new file mode 100644 index 0000000000000..14fe1654baad8 --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_gpio_m3m4_v1v2.c @@ -0,0 +1,877 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_gpio_m3m4_v1v2.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include +#include + +#include "arm_internal.h" +#include "chip.h" +#include "stm32_syscfg.h" +#include "stm32_gpio.h" + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static spinlock_t g_configgpio_lock = SP_UNLOCKED; + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/* Base addresses for each GPIO block */ + +const uint32_t g_gpiobase[STM32_NGPIO_PORTS] = +{ +#if STM32_NGPIO_PORTS > 0 + STM32_GPIOA_BASE, +#endif +#if STM32_NGPIO_PORTS > 1 + STM32_GPIOB_BASE, +#endif +#if STM32_NGPIO_PORTS > 2 + STM32_GPIOC_BASE, +#endif +#if STM32_NGPIO_PORTS > 3 + STM32_GPIOD_BASE, +#endif +#if STM32_NGPIO_PORTS > 4 + STM32_GPIOE_BASE, +#endif + +#if defined(CONFIG_STM32_STM32L15XX) + +#if STM32_NGPIO_PORTS > 5 + STM32_GPIOH_BASE, +#endif +#if STM32_NGPIO_PORTS > 6 + STM32_GPIOF_BASE, +#endif +#if STM32_NGPIO_PORTS > 7 + STM32_GPIOG_BASE, +#endif + +#else + +#if STM32_NGPIO_PORTS > 5 + STM32_GPIOF_BASE, +#endif +#if STM32_NGPIO_PORTS > 6 + STM32_GPIOG_BASE, +#endif +#if STM32_NGPIO_PORTS > 7 + STM32_GPIOH_BASE, +#endif +#if STM32_NGPIO_PORTS > 8 + STM32_GPIOI_BASE, +#endif +#if STM32_NGPIO_PORTS > 9 + STM32_GPIOJ_BASE, +#endif +#if STM32_NGPIO_PORTS > 10 + STM32_GPIOK_BASE, +#endif + +#endif /* CONFIG_STM32_STM32L15XX */ +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Function: stm32_gpioremap + * + * Description: + * + * Based on configuration within the .config file, this function will + * remaps positions of alternative functions. + * + ****************************************************************************/ + +static inline void stm32_gpioremap(void) +{ +#if defined(CONFIG_STM32_STM32F10XX) + + /* Remap according to the configuration within .config file */ + + uint32_t val = 0; + +#ifdef CONFIG_STM32_SPI1_REMAP + val |= AFIO_MAPR_SPI1_REMAP; +#endif +#ifdef CONFIG_STM32_SPI3_REMAP + val |= AFIO_MAPR_SPI3_REMAP; +#endif + +#ifdef CONFIG_STM32_I2C1_REMAP + val |= AFIO_MAPR_I2C1_REMAP; +#endif + +#ifdef CONFIG_STM32_USART1_REMAP + val |= AFIO_MAPR_USART1_REMAP; +#endif +#ifdef CONFIG_STM32_USART2_REMAP + val |= AFIO_MAPR_USART2_REMAP; +#endif +#ifdef CONFIG_STM32_USART3_FULL_REMAP + val |= AFIO_MAPR_USART3_FULLREMAP; +#endif +#ifdef CONFIG_STM32_USART3_PARTIAL_REMAP + val |= AFIO_MAPR_USART3_PARTREMAP; +#endif + +#ifdef CONFIG_STM32_TIM1_FULL_REMAP + val |= AFIO_MAPR_TIM1_FULLREMAP; +#endif +#ifdef CONFIG_STM32_TIM1_PARTIAL_REMAP + val |= AFIO_MAPR_TIM1_PARTREMAP; +#endif +#ifdef CONFIG_STM32_TIM2_FULL_REMAP + val |= AFIO_MAPR_TIM2_FULLREMAP; +#endif +#ifdef CONFIG_STM32_TIM2_PARTIAL_REMAP_1 + val |= AFIO_MAPR_TIM2_PARTREMAP1; +#endif +#ifdef CONFIG_STM32_TIM2_PARTIAL_REMAP_2 + val |= AFIO_MAPR_TIM2_PARTREMAP2; +#endif +#ifdef CONFIG_STM32_TIM3_FULL_REMAP + val |= AFIO_MAPR_TIM3_FULLREMAP; +#endif +#ifdef CONFIG_STM32_TIM3_PARTIAL_REMAP + val |= AFIO_MAPR_TIM3_PARTREMAP; +#endif +#ifdef CONFIG_STM32_TIM4_REMAP + val |= AFIO_MAPR_TIM4_REMAP; +#endif + +#ifdef CONFIG_STM32_CAN1_REMAP1 + val |= AFIO_MAPR_PB89; +#endif +#ifdef CONFIG_STM32_CAN1_REMAP2 + val |= AFIO_MAPR_PD01; +#endif +#ifdef CONFIG_STM32_CAN2_REMAP /* Connectivity line only */ + val |= AFIO_MAPR_CAN2_REMAP; +#endif + +#ifdef CONFIG_STM32_ETH_REMAP /* Connectivity line only */ + val |= AFIO_MAPR_ETH_REMAP; +#endif + +#ifdef CONFIG_STM32_JTAG_FULL_ENABLE + /* The reset default */ +#elif defined(CONFIG_STM32_JTAG_NOJNTRST_ENABLE) + val |= AFIO_MAPR_SWJ; /* enabled but without JNTRST */ +#elif defined(CONFIG_STM32_JTAG_SW_ENABLE) + val |= AFIO_MAPR_SWDP; /* set JTAG-DP disabled and SW-DP enabled */ +#else + val |= AFIO_MAPR_DISAB; /* set JTAG-DP and SW-DP Disabled */ +#endif + + putreg32(val, STM32_AFIO_MAPR); +#endif +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Function: stm32_gpioinit + * + * Description: + * Based on configuration within the .config file, it does: + * - Remaps positions of alternative functions. + * + * Typically called from stm32_start(). + * + * Assumptions: + * This function is called early in the initialization sequence so that + * no mutual exclusion is necessary. + * + ****************************************************************************/ + +void stm32_gpioinit(void) +{ + /* Remap according to the configuration within .config file */ + + stm32_gpioremap(); +} + +/**************************************************************************** + * Name: stm32_configgpio + * + * Description: + * Configure a GPIO pin based on bit-encoded description of the pin. + * Once it is configured as Alternative (GPIO_ALT|GPIO_CNF_AFPP|...) + * function, it must be unconfigured with stm32_unconfiggpio() with + * the same cfgset first before it can be set to non-alternative function. + * + * Returned Value: + * OK on success + * A negated errno value on invalid port, or when pin is locked as ALT + * function. + * + * To-Do: Auto Power Enable + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_configgpio (for the STM32F10xxx family) + ****************************************************************************/ + +#if defined(CONFIG_STM32_STM32F10XX) +int stm32_configgpio(uint32_t cfgset) +{ + uint32_t base; + uint32_t cr; + uint32_t regval; + uint32_t regaddr; + unsigned int port; + unsigned int pin; + unsigned int pos; + unsigned int modecnf; + irqstate_t flags; + bool input; + + /* Verify that this hardware supports the select GPIO port */ + + port = (cfgset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; + if (port >= STM32_NGPIO_PORTS) + { + return -EINVAL; + } + + /* Get the port base address */ + + base = g_gpiobase[port]; + + /* Get the pin number and select the port configuration register for that + * pin + */ + + pin = (cfgset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT; + if (pin < 8) + { + cr = base + STM32_GPIO_CRL_OFFSET; + pos = pin; + } + else + { + cr = base + STM32_GPIO_CRH_OFFSET; + pos = pin - 8; + } + + /* Input or output? */ + + input = ((cfgset & GPIO_INPUT) != 0); + + /* Interrupts must be disabled from here on out so that we have mutually + * exclusive access to all of the GPIO configuration registers. + */ + + flags = spin_lock_irqsave(&g_configgpio_lock); + + /* Decode the mode and configuration */ + + regval = getreg32(cr); + + if (input) + { + /* Input.. force mode = INPUT */ + + modecnf = 0; + } + else + { + /* Output or alternate function */ + + modecnf = (cfgset & GPIO_MODE_MASK) >> GPIO_MODE_SHIFT; + } + + modecnf |= ((cfgset & GPIO_CNF_MASK) >> GPIO_CNF_SHIFT) << 2; + + /* Set the port configuration register */ + + regval &= ~(GPIO_CR_MODECNF_MASK(pos)); + regval |= (modecnf << GPIO_CR_MODECNF_SHIFT(pos)); + putreg32(regval, cr); + + /* Set or reset the corresponding BRR/BSRR bit */ + + if (!input) + { + /* It is an output or an alternate function. We have to look at + * the CNF bits to know which. + */ + + unsigned int cnf = (cfgset & GPIO_CNF_MASK); + if (cnf != GPIO_CNF_OUTPP && cnf != GPIO_CNF_OUTOD) + { + /* Its an alternate function pin... we can return early */ + + spin_unlock_irqrestore(&g_configgpio_lock, flags); + return OK; + } + } + else + { + /* It is an input pin... Should it configured as an EXTI interrupt? */ + + if ((cfgset & GPIO_EXTI) != 0) + { + int shift; + + /* Yes.. Set the bits in the EXTI CR register */ + + regaddr = STM32_AFIO_EXTICR(pin); + regval = getreg32(regaddr); + shift = AFIO_EXTICR_EXTI_SHIFT(pin); + regval &= ~(AFIO_EXTICR_PORT_MASK << shift); + regval |= (((uint32_t)port) << shift); + + putreg32(regval, regaddr); + } + + if ((cfgset & GPIO_CNF_MASK) != GPIO_CNF_INPULLUD) + { + /* Neither... we can return early */ + + spin_unlock_irqrestore(&g_configgpio_lock, flags); + return OK; + } + } + + /* If it is an output... set the pin to the correct initial state. + * If it is pull-down or pull up, then we need to set the ODR + * appropriately for that function. + */ + + if ((cfgset & GPIO_OUTPUT_SET) != 0) + { + /* Use the BSRR register to set the output */ + + regaddr = base + STM32_GPIO_BSRR_OFFSET; + } + else + { + /* Use the BRR register to clear */ + + regaddr = base + STM32_GPIO_BRR_OFFSET; + } + + regval = getreg32(regaddr); + regval |= (1 << pin); + putreg32(regval, regaddr); + + spin_unlock_irqrestore(&g_configgpio_lock, flags); + return OK; +} +#endif + +/**************************************************************************** + * Name: stm32_configgpio (for the STM32L15xxx, STM32F20xxx, STM32F40xxx, + * and STM32G4XXX families). + ****************************************************************************/ + +#if defined(CONFIG_STM32_STM32L15XX) || defined(CONFIG_STM32_STM32F20XX) || \ + defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) || \ + defined(CONFIG_STM32_STM32F37XX) || defined(CONFIG_STM32_STM32F4XXX) || \ + defined(CONFIG_STM32_STM32G4XXX) +int stm32_configgpio(uint32_t cfgset) +{ + uintptr_t base; + uint32_t regval; + uint32_t setting; + uint32_t alt_setting; + unsigned int regoffset; + unsigned int port; + unsigned int pin; + unsigned int pos; + unsigned int pinmode; + irqstate_t flags; + + /* Verify that this hardware supports the select GPIO port */ + + port = (cfgset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; + if (port >= STM32_NGPIO_PORTS) + { + return -EINVAL; + } + + /* Get the port base address */ + + base = g_gpiobase[port]; + + /* Get the pin number and select the port configuration register for that + * pin + */ + + pin = (cfgset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT; + + /* Set up the mode register (and remember whether the pin mode) */ + + switch (cfgset & GPIO_MODE_MASK) + { + default: + case GPIO_INPUT: /* Input mode */ + pinmode = GPIO_MODER_INPUT; + break; + + case GPIO_OUTPUT: /* General purpose output mode */ + + /* Set the initial output value */ + + stm32_gpiowrite(cfgset, (cfgset & GPIO_OUTPUT_SET) != 0); + pinmode = GPIO_MODER_OUTPUT; + break; + + case GPIO_ALT: /* Alternate function mode */ + pinmode = GPIO_MODER_ALT; + break; + + case GPIO_ANALOG: /* Analog mode */ + pinmode = GPIO_MODER_ANALOG; + break; + } + + /* Interrupts must be disabled from here on out so that we have mutually + * exclusive access to all of the GPIO configuration registers. + */ + + flags = spin_lock_irqsave(&g_configgpio_lock); + + /* Determine the alternate function (Only alternate function pins) */ + + if (pinmode == GPIO_MODER_ALT) + { + alt_setting = (cfgset & GPIO_AF_MASK) >> GPIO_AF_SHIFT; + } + else + { + alt_setting = 0; + } + + /* Set the alternate function (Only alternate function pins) + * This is done before configuring the Outputs on a change to + * an Alternate function. + */ + + if (alt_setting != 0) + { + if (pin < 8) + { + regoffset = STM32_GPIO_AFRL_OFFSET; + pos = pin; + } + else + { + regoffset = STM32_GPIO_AFRH_OFFSET; + pos = pin - 8; + } + + regval = getreg32(base + regoffset); + regval &= ~GPIO_AFR_MASK(pos); + regval |= (alt_setting << GPIO_AFR_SHIFT(pos)); + putreg32(regval, base + regoffset); + } + + /* Now apply the configuration to the mode register */ + + regval = getreg32(base + STM32_GPIO_MODER_OFFSET); + regval &= ~GPIO_MODER_MASK(pin); + regval |= ((uint32_t)pinmode << GPIO_MODER_SHIFT(pin)); + putreg32(regval, base + STM32_GPIO_MODER_OFFSET); + + /* Set up the pull-up/pull-down configuration (all but analog pins) */ + + setting = GPIO_PUPDR_NONE; + if (pinmode != GPIO_MODER_ANALOG) + { + switch (cfgset & GPIO_PUPD_MASK) + { + default: + case GPIO_FLOAT: /* No pull-up, pull-down */ + break; + + case GPIO_PULLUP: /* Pull-up */ + setting = GPIO_PUPDR_PULLUP; + break; + + case GPIO_PULLDOWN: /* Pull-down */ + setting = GPIO_PUPDR_PULLDOWN; + break; + } + } + + regval = getreg32(base + STM32_GPIO_PUPDR_OFFSET); + regval &= ~GPIO_PUPDR_MASK(pin); + regval |= (setting << GPIO_PUPDR_SHIFT(pin)); + putreg32(regval, base + STM32_GPIO_PUPDR_OFFSET); + + /* Set the alternate function (Only alternate function pins) + * This is done after configuring the pin's connection + * on a change away from an Alternate function. + */ + + if (alt_setting == 0) + { + if (pin < 8) + { + regoffset = STM32_GPIO_AFRL_OFFSET; + pos = pin; + } + else + { + regoffset = STM32_GPIO_AFRH_OFFSET; + pos = pin - 8; + } + + regval = getreg32(base + regoffset); + regval &= ~GPIO_AFR_MASK(pos); + regval |= (alt_setting << GPIO_AFR_SHIFT(pos)); + putreg32(regval, base + regoffset); + } + + /* Set speed (Only outputs and alternate function pins) */ + + if (pinmode == GPIO_MODER_OUTPUT || pinmode == GPIO_MODER_ALT) + { + switch (cfgset & GPIO_SPEED_MASK) + { +#if defined(CONFIG_STM32_STM32L15XX) + default: + case GPIO_SPEED_400KHz: /* 400 kHz Very low speed output */ + setting = GPIO_OSPEED_400KHz; + break; + + case GPIO_SPEED_2MHz: /* 2 MHz Low speed output */ + setting = GPIO_OSPEED_2MHz; + break; + + case GPIO_SPEED_10MHz: /* 10 MHz Medium speed output */ + setting = GPIO_OSPEED_10MHz; + break; + + case GPIO_SPEED_40MHz: /* 40 MHz High speed output */ + setting = GPIO_OSPEED_40MHz; + break; +#elif defined(CONFIG_STM32_STM32G4XXX) + default: + case GPIO_SPEED_5MHz: /* 5 MHz Low speed output */ + setting = GPIO_OSPEED_5MHz; + break; + + case GPIO_SPEED_25MHz: /* 25 MHz Medium speed output */ + setting = GPIO_OSPEED_25MHz; + break; + + case GPIO_SPEED_50MHz: /* 50 MHz Fast speed output */ + setting = GPIO_OSPEED_50MHz; + break; + + case GPIO_SPEED_120MHz: /* 120 MHz High speed output */ + setting = GPIO_OSPEED_120MHz; + break; +#else + default: + case GPIO_SPEED_2MHz: /* 2 MHz Low speed output */ + setting = GPIO_OSPEED_2MHz; + break; + + case GPIO_SPEED_25MHz: /* 25 MHz Medium speed output */ + setting = GPIO_OSPEED_25MHz; + break; + + case GPIO_SPEED_50MHz: /* 50 MHz Fast speed output */ + setting = GPIO_OSPEED_50MHz; + break; + +#if !defined(CONFIG_STM32_STM32F30XX) && !defined(CONFIG_STM32_STM32F33XX) && \ + !defined(CONFIG_STM32_STM32F37XX) + case GPIO_SPEED_100MHz: /* 100 MHz High speed output */ + setting = GPIO_OSPEED_100MHz; + break; +#endif +#endif + } + } + else + { + setting = 0; + } + + regval = getreg32(base + STM32_GPIO_OSPEED_OFFSET); + regval &= ~GPIO_OSPEED_MASK(pin); + regval |= (setting << GPIO_OSPEED_SHIFT(pin)); + putreg32(regval, base + STM32_GPIO_OSPEED_OFFSET); + + /* Set push-pull/open-drain (Only outputs and alternate function pins) */ + + regval = getreg32(base + STM32_GPIO_OTYPER_OFFSET); + setting = GPIO_OTYPER_OD(pin); + + if ((pinmode == GPIO_MODER_OUTPUT || pinmode == GPIO_MODER_ALT) && + (cfgset & GPIO_OPENDRAIN) != 0) + { + regval |= setting; + } + else + { + regval &= ~setting; + } + + putreg32(regval, base + STM32_GPIO_OTYPER_OFFSET); + + /* Otherwise, it is an input pin. Should it configured as an EXTI + * interrupt? + */ + + if (pinmode != GPIO_MODER_OUTPUT && (cfgset & GPIO_EXTI) != 0) + { + /* "In STM32 F1 the selection of the EXTI line source is performed + * through the EXTIx bits in the AFIO_EXTICRx registers, while in F2 + * series this selection is done through the EXTIx bits in the + * SYSCFG_EXTICRx registers. + * + * "Only the mapping of the EXTICRx registers has been changed, + * without any changes to the meaning of the EXTIx bits. However, + * the range of EXTI bits values has been extended to 0b1000 to + * support the two ports added in F2, port H and I (in F1 series + * the maximum value is 0b0110)." + */ + + uint32_t regaddr; + int shift; + + /* Set the bits in the SYSCFG EXTICR register */ + + regaddr = STM32_SYSCFG_EXTICR(pin); + regval = getreg32(regaddr); + shift = SYSCFG_EXTICR_EXTI_SHIFT(pin); + regval &= ~(SYSCFG_EXTICR_PORT_MASK << shift); + regval |= (((uint32_t)port) << shift); + + putreg32(regval, regaddr); + } + + spin_unlock_irqrestore(&g_configgpio_lock, flags); + return OK; +} +#endif + +/**************************************************************************** + * Name: stm32_unconfiggpio + * + * Description: + * Unconfigure a GPIO pin based on bit-encoded description of the pin, set + * it into default HiZ state (and possibly mark it's unused) and unlock it + * whether it was previously selected as an alternative function + * (GPIO_ALT | GPIO_CNF_AFPP | ...). + * + * This is a safety function and prevents hardware from shocks, as + * unexpected write to the Timer Channel Output GPIO to fixed '1' or '0' + * while it should operate in PWM mode could produce excessive on-board + * currents and trigger over-current/alarm function. + * + * Returned Value: + * OK on success + * A negated errno value on invalid port + * + * To-Do: Auto Power Disable + ****************************************************************************/ + +int stm32_unconfiggpio(uint32_t cfgset) +{ + /* Reuse port and pin number and set it to default HiZ INPUT */ + + cfgset &= GPIO_PORT_MASK | GPIO_PIN_MASK; +#if defined(CONFIG_STM32_STM32F10XX) + cfgset |= GPIO_INPUT | GPIO_CNF_INFLOAT | GPIO_MODE_INPUT; +#elif defined(CONFIG_STM32_STM32L15XX) || defined(CONFIG_STM32_STM32F20XX) || \ + defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) || \ + defined(CONFIG_STM32_STM32F37XX) || defined(CONFIG_STM32_STM32F4XXX) || \ + defined(CONFIG_STM32_STM32G4XXX) + cfgset |= GPIO_INPUT | GPIO_FLOAT; +#else +# error "Unsupported STM32 chip" +#endif + + /* To-Do: Mark its unuse for automatic power saving options */ + + return stm32_configgpio(cfgset); +} + +/**************************************************************************** + * Name: stm32_gpiowrite + * + * Description: + * Write one or zero to the selected GPIO pin + * + ****************************************************************************/ + +void stm32_gpiowrite(uint32_t pinset, bool value) +{ + uint32_t base; +#if defined(CONFIG_STM32_STM32F10XX) + uint32_t offset; +#elif defined(CONFIG_STM32_STM32L15XX) || defined(CONFIG_STM32_STM32F20XX) || \ + defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) || \ + defined(CONFIG_STM32_STM32F37XX) || defined(CONFIG_STM32_STM32F4XXX) || \ + defined(CONFIG_STM32_STM32G4XXX) + uint32_t bit; +#endif + unsigned int port; + unsigned int pin; + + port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; + if (port < STM32_NGPIO_PORTS) + { + /* Get the port base address */ + + base = g_gpiobase[port]; + + /* Get the pin number */ + + pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT; + + /* Set or clear the output on the pin */ + +#if defined(CONFIG_STM32_STM32F10XX) + + if (value) + { + offset = STM32_GPIO_BSRR_OFFSET; + } + else + { + offset = STM32_GPIO_BRR_OFFSET; + } + + putreg32((1 << pin), base + offset); + +#elif defined(CONFIG_STM32_STM32L15XX) || defined(CONFIG_STM32_STM32F20XX) || \ + defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) || \ + defined(CONFIG_STM32_STM32F37XX) || defined(CONFIG_STM32_STM32F4XXX) || \ + defined(CONFIG_STM32_STM32G4XXX) + + if (value) + { + bit = GPIO_BSRR_SET(pin); + } + else + { + bit = GPIO_BSRR_RESET(pin); + } + + putreg32(bit, base + STM32_GPIO_BSRR_OFFSET); + +#else +# error "Unsupported STM32 chip" +#endif + } +} + +/**************************************************************************** + * Name: stm32_gpioread + * + * Description: + * Read one or zero from the selected GPIO pin + * + ****************************************************************************/ + +bool stm32_gpioread(uint32_t pinset) +{ + uint32_t base; + unsigned int port; + unsigned int pin; + + port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; + if (port < STM32_NGPIO_PORTS) + { + /* Get the port base address */ + + base = g_gpiobase[port]; + + /* Get the pin number and return the input state of that pin */ + + pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT; + return ((getreg32(base + STM32_GPIO_IDR_OFFSET) & (1 << pin)) != 0); + } + + return 0; +} + +/**************************************************************************** + * Name: stm32_iocompensation + * + * Description: + * Enable I/O compensation. + * + * By default the I/O compensation cell is not used. However when the I/O + * output buffer speed is configured in 50 MHz or 100 MHz mode, it is + * recommended to use the compensation cell for slew rate control on I/O + * tf(IO)out)/tr(IO)out commutation to reduce the I/O noise on power + * supply. + * + * The I/O compensation cell can be used only when the supply voltage + * ranges from 2.4 to 3.6 V. + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_HAVE_IOCOMPENSATION +void stm32_iocompensation(void) +{ +#ifdef STM32_SYSCFG_CMPCR + /* Enable I/O Compensation. Writing '1' to the CMPCR power-down bit + * enables the I/O compensation cell. + */ + + putreg32(SYSCFG_CMPCR_CMPPD, STM32_SYSCFG_CMPCR); + + /* Wait for compensation cell to become ready */ + + while ((getreg32(STM32_SYSCFG_CMPCR) & SYSCFG_CMPCR_READY) == 0) + { + } +#endif +} +#endif diff --git a/arch/arm/src/common/stm32/stm32_gpio_m3m4_v1v2.h b/arch/arm/src/common/stm32/stm32_gpio_m3m4_v1v2.h new file mode 100644 index 0000000000000..17689d672d9b2 --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_gpio_m3m4_v1v2.h @@ -0,0 +1,562 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_gpio_m3m4_v1v2.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_GPIO_V1V2_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_GPIO_V1V2_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#ifndef __ASSEMBLY__ +# include +# include +#endif + +#include + +#include "chip.h" + +#if defined(CONFIG_STM32_STM32L15XX) +# include "hardware/stm32l15xxx_gpio.h" +#elif defined(CONFIG_STM32_STM32F10XX) +# include "hardware/stm32f10xxx_gpio.h" +#elif defined(CONFIG_STM32_STM32F20XX) +# include "hardware/stm32f20xxx_gpio.h" +#elif defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) || \ + defined(CONFIG_STM32_STM32F37XX) +# include "hardware/stm32f30xxx_gpio.h" +#elif defined(CONFIG_STM32_STM32F4XXX) +# include "hardware/stm32f40xxx_gpio.h" +#elif defined(CONFIG_STM32_STM32G4XXX) +# include "hardware/stm32g4xxxx_gpio.h" +#else +# error "Unrecognized STM32 chip" +#endif + +/**************************************************************************** + * Pre-Processor Declarations + ****************************************************************************/ + +/* Bit-encoded input to stm32_configgpio() */ + +#if defined(CONFIG_STM32_STM32F10XX) + +/* 16-bit Encoding: + * + * 1111 1100 0000 0000 + * 5432 1098 7654 3210 + * ---- ---- ---- ---- + * OFFS SX.. VPPP BBBB + */ + +/* Output mode: + * + * 1111 1100 0000 0000 + * 5432 1098 7654 3210 + * ---- ---- ---- ---- + * O... .... .... .... + */ + +#define GPIO_INPUT (1 << 15) /* Bit 15: 1=Input mode */ +#define GPIO_OUTPUT (0) /* 0=Output or alternate function */ +#define GPIO_ALT (0) + +/* If the pin is a GPIO digital output, then this identifies the initial + * output value. If the pin is an input, this bit is overloaded to + * provide the qualifier to\ distinguish input pull-up and -down: + * + * 1111 1100 0000 0000 + * 5432 1098 7654 3210 + * ---- ---- ---- ---- + * .... .... V... .... + */ + +#define GPIO_OUTPUT_SET (1 << 7) /* Bit 7: If output, initial value of output */ +#define GPIO_OUTPUT_CLEAR (0) + +/* These bits set the primary function of the pin: + * + * 1111 1100 0000 0000 + * 5432 1098 7654 3210 + * ---- ---- ---- ---- + * .FF. .... .... .... + */ + +#define GPIO_CNF_SHIFT 13 /* Bits 13-14: GPIO function */ +#define GPIO_CNF_MASK (3 << GPIO_CNF_SHIFT) + +# define GPIO_CNF_ANALOGIN (0 << GPIO_CNF_SHIFT) /* Analog input */ +# define GPIO_CNF_INFLOAT (1 << GPIO_CNF_SHIFT) /* Input floating */ +# define GPIO_CNF_INPULLUD (2 << GPIO_CNF_SHIFT) /* Input pull-up/down general bit, since up is composed of two parts */ +# define GPIO_CNF_INPULLDWN (2 << GPIO_CNF_SHIFT) /* Input pull-down */ +# define GPIO_CNF_INPULLUP ((2 << GPIO_CNF_SHIFT) \ + | GPIO_OUTPUT_SET) /* Input pull-up */ + +# define GPIO_CNF_OUTPP (0 << GPIO_CNF_SHIFT) /* Output push-pull */ +# define GPIO_CNF_OUTOD (1 << GPIO_CNF_SHIFT) /* Output open-drain */ +# define GPIO_CNF_AFPP (2 << GPIO_CNF_SHIFT) /* Alternate function push-pull */ +# define GPIO_CNF_AFOD (3 << GPIO_CNF_SHIFT) /* Alternate function open-drain */ + +/* Maximum frequency selection: + * + * 1111 1100 0000 0000 + * 5432 1098 7654 3210 + * ---- ---- ---- ---- + * ...S S... .... .... + */ + +#define GPIO_MODE_SHIFT 11 /* Bits 11-12: GPIO frequency selection */ +#define GPIO_MODE_MASK (3 << GPIO_MODE_SHIFT) +# define GPIO_MODE_INPUT (0 << GPIO_MODE_SHIFT) /* Input mode (reset state) */ +# define GPIO_MODE_10MHz (1 << GPIO_MODE_SHIFT) /* Output mode, max speed 10 MHz */ +# define GPIO_MODE_2MHz (2 << GPIO_MODE_SHIFT) /* Output mode, max speed 2 MHz */ +# define GPIO_MODE_50MHz (3 << GPIO_MODE_SHIFT) /* Output mode, max speed 50 MHz */ + +#define GPIO_ADJUST_MODE(p, m) (((p) & ~GPIO_MODE_MASK) | (m)) + +/* External interrupt selection (GPIO inputs only): + * + * 1111 1100 0000 0000 + * 5432 1098 7654 3210 + * ---- ---- ---- ---- + * .... .X.. .... .... + */ + +#define GPIO_EXTI (1 << 10) /* Bit 10: Configure as EXTI interrupt */ + +/* This identifies the GPIO port: + * + * 1111 1100 0000 0000 + * 5432 1098 7654 3210 + * ---- ---- ---- ---- + * .... .... .PPP .... + */ + +#define GPIO_PORT_SHIFT 4 /* Bit 4-6: Port number */ +#define GPIO_PORT_MASK (7 << GPIO_PORT_SHIFT) +# define GPIO_PORTA (0 << GPIO_PORT_SHIFT) /* GPIOA */ +# define GPIO_PORTB (1 << GPIO_PORT_SHIFT) /* GPIOB */ +# define GPIO_PORTC (2 << GPIO_PORT_SHIFT) /* GPIOC */ +# define GPIO_PORTD (3 << GPIO_PORT_SHIFT) /* GPIOD */ +# define GPIO_PORTE (4 << GPIO_PORT_SHIFT) /* GPIOE */ +# define GPIO_PORTF (5 << GPIO_PORT_SHIFT) /* GPIOF */ +# define GPIO_PORTG (6 << GPIO_PORT_SHIFT) /* GPIOG */ + +/* This identifies the bit in the port: + * + * 1111 1100 0000 0000 + * 5432 1098 7654 3210 + * ---- ---- ---- ---- + * .... .... .... BBBB + */ + +#define GPIO_PIN_SHIFT 0 /* Bits 0-3: GPIO number: 0-15 */ +#define GPIO_PIN_MASK (15 << GPIO_PIN_SHIFT) +#define GPIO_PIN0 (0 << GPIO_PIN_SHIFT) +#define GPIO_PIN1 (1 << GPIO_PIN_SHIFT) +#define GPIO_PIN2 (2 << GPIO_PIN_SHIFT) +#define GPIO_PIN3 (3 << GPIO_PIN_SHIFT) +#define GPIO_PIN4 (4 << GPIO_PIN_SHIFT) +#define GPIO_PIN5 (5 << GPIO_PIN_SHIFT) +#define GPIO_PIN6 (6 << GPIO_PIN_SHIFT) +#define GPIO_PIN7 (7 << GPIO_PIN_SHIFT) +#define GPIO_PIN8 (8 << GPIO_PIN_SHIFT) +#define GPIO_PIN9 (9 << GPIO_PIN_SHIFT) +#define GPIO_PIN10 (10 << GPIO_PIN_SHIFT) +#define GPIO_PIN11 (11 << GPIO_PIN_SHIFT) +#define GPIO_PIN12 (12 << GPIO_PIN_SHIFT) +#define GPIO_PIN13 (13 << GPIO_PIN_SHIFT) +#define GPIO_PIN14 (14 << GPIO_PIN_SHIFT) +#define GPIO_PIN15 (15 << GPIO_PIN_SHIFT) + +#elif defined(CONFIG_STM32_STM32L15XX) || defined(CONFIG_STM32_STM32F20XX) || \ + defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) || \ + defined(CONFIG_STM32_STM32F37XX) || defined(CONFIG_STM32_STM32F4XXX) || \ + defined(CONFIG_STM32_STM32G4XXX) +/* Each port bit of the general-purpose I/O (GPIO) ports can be + * individually configured by software in several modes: + * + * - Input floating + * - Input pull-up + * - Input-pull-down + * - Output open-drain with pull-up or pull-down capability + * - Output push-pull with pull-up or pull-down capability + * - Alternate function push-pull with pull-up or pull-down capability + * - Alternate function open-drain with pull-up or pull-down capability + * - Analog + * + * 20-bit Encoding: 1111 1111 1100 0000 0000 + * 9876 5432 1098 7654 3210 + * ---- ---- ---- ---- ---- + * Inputs: MMUU .... ...X PPPP BBBB + * Outputs: MMUU .... FFOV PPPP BBBB + * Alternate Functions: MMUU AAAA FFO. PPPP BBBB + * Analog: MM.. .... .... PPPP BBBB + */ + +/* Mode: + * + * 1111 1111 1100 0000 0000 + * 9876 5432 1098 7654 3210 + * ---- ---- ---- ---- ---- + * MM.. .... .... .... .... + */ + +#define GPIO_MODE_SHIFT (18) /* Bits 18-19: GPIO port mode */ +#define GPIO_MODE_MASK (3 << GPIO_MODE_SHIFT) +# define GPIO_INPUT (0 << GPIO_MODE_SHIFT) /* Input mode */ +# define GPIO_OUTPUT (1 << GPIO_MODE_SHIFT) /* General purpose output mode */ +# define GPIO_ALT (2 << GPIO_MODE_SHIFT) /* Alternate function mode */ +# define GPIO_ANALOG (3 << GPIO_MODE_SHIFT) /* Analog mode */ + +/* Input/output pull-ups/downs (not used with analog): + * + * 1111 1111 1100 0000 0000 + * 9876 5432 1098 7654 3210 + * ---- ---- ---- ---- ---- + * ..UU .... .... .... .... + */ + +#define GPIO_PUPD_SHIFT (16) /* Bits 16-17: Pull-up/pull down */ +#define GPIO_PUPD_MASK (3 << GPIO_PUPD_SHIFT) +# define GPIO_FLOAT (0 << GPIO_PUPD_SHIFT) /* No pull-up, pull-down */ +# define GPIO_PULLUP (1 << GPIO_PUPD_SHIFT) /* Pull-up */ +# define GPIO_PULLDOWN (2 << GPIO_PUPD_SHIFT) /* Pull-down */ + +/* Alternate Functions: + * + * 1111 1111 1100 0000 0000 + * 9876 5432 1098 7654 3210 + * ---- ---- ---- ---- ---- + * .... AAAA .... .... .... + */ + +#define GPIO_AF_SHIFT (12) /* Bits 12-15: Alternate function */ +#define GPIO_AF_MASK (15 << GPIO_AF_SHIFT) +# define GPIO_AF(n) ((n) << GPIO_AF_SHIFT) +# define GPIO_AF0 (0 << GPIO_AF_SHIFT) +# define GPIO_AF1 (1 << GPIO_AF_SHIFT) +# define GPIO_AF2 (2 << GPIO_AF_SHIFT) +# define GPIO_AF3 (3 << GPIO_AF_SHIFT) +# define GPIO_AF4 (4 << GPIO_AF_SHIFT) +# define GPIO_AF5 (5 << GPIO_AF_SHIFT) +# define GPIO_AF6 (6 << GPIO_AF_SHIFT) +# define GPIO_AF7 (7 << GPIO_AF_SHIFT) +# define GPIO_AF8 (8 << GPIO_AF_SHIFT) +# define GPIO_AF9 (9 << GPIO_AF_SHIFT) +# define GPIO_AF10 (10 << GPIO_AF_SHIFT) +# define GPIO_AF11 (11 << GPIO_AF_SHIFT) +# define GPIO_AF12 (12 << GPIO_AF_SHIFT) +# define GPIO_AF13 (13 << GPIO_AF_SHIFT) +# define GPIO_AF14 (14 << GPIO_AF_SHIFT) +# define GPIO_AF15 (15 << GPIO_AF_SHIFT) + +/* Output/Alt function frequency selection: + * + * 1111 1111 1100 0000 0000 + * 9876 5432 1098 7654 3210 + * ---- ---- ---- ---- ---- + * .... .... FF.. .... .... + */ + +#define GPIO_SPEED_SHIFT (10) /* Bits 10-11: GPIO frequency selection */ +#define GPIO_SPEED_MASK (3 << GPIO_SPEED_SHIFT) +#if defined(CONFIG_STM32_STM32L15XX) +# define GPIO_SPEED_400KHz (0 << GPIO_SPEED_SHIFT) /* 400 kHz Very low speed output */ +# define GPIO_SPEED_2MHz (1 << GPIO_SPEED_SHIFT) /* 2 MHz Low speed output */ +# define GPIO_SPEED_10MHz (2 << GPIO_SPEED_SHIFT) /* 10 MHz Medium speed output */ +# define GPIO_SPEED_40MHz (3 << GPIO_SPEED_SHIFT) /* 40 MHz High speed output */ +#elif defined(CONFIG_STM32_STM32G4XXX) /* With C=50pF, 2.7 + +#include + +enum hciuart_devno_e +{ + HCIUART1 = 0, + HCIUART2 = 1, + HCIUART3 = 2, + HCIUART5 = 5, + HCIUART6 = 6, + HCIUART7 = 7 +}; + +const struct btuart_lowerhalf_s * +hciuart_instantiate(enum hciuart_devno_e uart); +void hciuart_initialize(void); + +#ifdef CONFIG_STM32_HCIUART_RXDMA +void stm32_serial_dma_poll(void); +#endif + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_HCIUART_H */ diff --git a/arch/arm/src/common/stm32/stm32_hciuart_m3m4_v1.c b/arch/arm/src/common/stm32/stm32_hciuart_m3m4_v1.c new file mode 100644 index 0000000000000..5f77bdc28997d --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_hciuart_m3m4_v1.c @@ -0,0 +1,2692 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_hciuart_m3m4_v1.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#include "arm_internal.h" +#include "chip.h" +#include "stm32_uart.h" +#include "stm32_hciuart.h" +#include "stm32_dma.h" +#include "stm32_rcc.h" +#include "stm32_uart.h" + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Some sanity checks *******************************************************/ + +/* DMA configuration */ + +/* If DMA is enabled on any USART, then very that other pre-requisites + * have also been selected. + */ + +#ifdef CONFIG_STM32_HCIUART_RXDMA + +# if defined(CONFIG_STM32_HAVE_IP_DMA_V2) +/* Verify that DMA has been enabled and the DMA channel has been defined. + */ + +# if defined(CONFIG_STM32_HCIUART1_RXDMA) || defined(CONFIG_STM32_HCIUART6_RXDMA) +# ifndef CONFIG_STM32_DMA2 +# error STM32 USART1/6 receive DMA requires CONFIG_STM32_DMA2 +# endif +# endif + +# if defined(CONFIG_STM32_HCIUART2_RXDMA) || defined(CONFIG_STM32_HCIUART3_RXDMA) || \ + defined(CONFIG_STM32_HCIUART7_RXDMA) || defined(CONFIG_STM32_HCIUART8_RXDMA) +# ifndef CONFIG_STM32_DMA1 +# error STM32 USART2/3/4/5/7/8 receive DMA requires CONFIG_STM32_DMA1 +# endif +# endif + +/* For the F4, there are alternate DMA channels for USART1 and 6. + * Logic in the board.h file make the DMA channel selection by defining + * the following in the board.h file. + */ + +# if defined(CONFIG_STM32_HCIUART1_RXDMA) && !defined(DMAMAP_USART1_RX) +# error "USART1 DMA channel not defined (DMAMAP_USART1_RX)" +# endif + +# if defined(CONFIG_STM32_HCIUART2_RXDMA) && !defined(DMAMAP_USART2_RX) +# error "USART2 DMA channel not defined (DMAMAP_USART2_RX)" +# endif + +# if defined(CONFIG_STM32_HCIUART3_RXDMA) && !defined(DMAMAP_USART3_RX) +# error "USART3 DMA channel not defined (DMAMAP_USART3_RX)" +# endif + +# if defined(CONFIG_STM32_HCIUART6_RXDMA) && !defined(DMAMAP_USART6_RX) +# error "USART6 DMA channel not defined (DMAMAP_USART6_RX)" +# endif + +# if defined(CONFIG_STM32_HCIUART7_RXDMA) && !defined(DMAMAP_UART7_RX) +# error "UART7 DMA channel not defined (DMAMAP_UART7_RX)" +# endif + +# if defined(CONFIG_STM32_HCIUART8_RXDMA) && !defined(DMAMAP_UART8_RX) +# error "UART8 DMA channel not defined (DMAMAP_UART8_RX)" +# endif + +# elif defined(CONFIG_STM32_STM32L15XX) || defined(CONFIG_STM32_STM32F10XX) || \ + defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) || \ + defined(CONFIG_STM32_STM32F37XX) + +# if defined(CONFIG_STM32_HCIUART1_RXDMA) || defined(CONFIG_STM32_HCIUART2_RXDMA) || \ + defined(CONFIG_STM32_HCIUART3_RXDMA) +# ifndef CONFIG_STM32_DMA1 +# error STM32 USART1/2/3 receive DMA requires CONFIG_STM32_DMA1 +# endif +# endif + +/* There are no optional DMA channel assignments for the F1 */ + +# define DMAMAP_USART1_RX DMACHAN_USART1_RX +# define DMAMAP_USART2_RX DMACHAN_USART2_RX +# define DMAMAP_USART3_RX DMACHAN_USART3_RX + +# endif + +/* The DMA buffer size when using RX DMA to emulate a FIFO. + * + * When streaming data, the generic serial layer will be called + * every time the FIFO receives half this number of bytes. + */ + +# if !defined(CONFIG_STM32_HCIUART_RXDMA_BUFSIZE) +# define CONFIG_STM32_HCIUART_RXDMA_BUFSIZE 32 +# endif +# define RXDMA_MULTIPLE 4 +# define RXDMA_MULTIPLE_MASK (RXDMA_MULTIPLE -1) +# define RXDMA_BUFFER_SIZE ((CONFIG_STM32_HCIUART_RXDMA_BUFSIZE + \ + RXDMA_MULTIPLE_MASK) & ~RXDMA_MULTIPLE_MASK) + +/* DMA priority */ + +# ifndef CONFIG_STM32_HCIUART_RXDMAPRIO +# if defined(CONFIG_STM32_STM32L15XX) || defined(CONFIG_STM32_STM32F10XX) || \ + defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) || \ + defined(CONFIG_STM32_STM32F37XX) +# define CONFIG_STM32_HCIUART_RXDMAPRIO DMA_CCR_PRIMED +# elif defined(CONFIG_STM32_HAVE_IP_DMA_V2) +# define CONFIG_STM32_HCIUART_RXDMAPRIO DMA_SCR_PRIMED +# else +# error "Unknown STM32 DMA" +# endif +# endif +# if defined(CONFIG_STM32_STM32L15XX) || defined(CONFIG_STM32_STM32F10XX) || \ + defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) || \ + defined(CONFIG_STM32_STM32F37XX) +# if (CONFIG_STM32_HCIUART_RXDMAPRIO & ~DMA_CCR_PL_MASK) != 0 +# error "Illegal value for CONFIG_STM32_HCIUART_RXDMAPRIO" +# endif +# elif defined(CONFIG_STM32_HAVE_IP_DMA_V2) +# if (CONFIG_STM32_HCIUART_RXDMAPRIO & ~DMA_SCR_PL_MASK) != 0 +# error "Illegal value for CONFIG_STM32_HCIUART_RXDMAPRIO" +# endif +# else +# error "Unknown STM32 DMA" +# endif + +/* DMA control word */ + +# if defined(CONFIG_STM32_HAVE_IP_DMA_V2) +# define SERIAL_DMA_CONTROL_WORD \ + (DMA_SCR_DIR_P2M | \ + DMA_SCR_CIRC | \ + DMA_SCR_MINC | \ + DMA_SCR_PSIZE_8BITS | \ + DMA_SCR_MSIZE_8BITS | \ + CONFIG_STM32_HCIUART_RXDMAPRIO | \ + DMA_SCR_PBURST_SINGLE | \ + DMA_SCR_MBURST_SINGLE) +# else +# define SERIAL_DMA_CONTROL_WORD \ + (DMA_CCR_CIRC | \ + DMA_CCR_MINC | \ + DMA_CCR_PSIZE_8BITS | \ + DMA_CCR_MSIZE_8BITS | \ + CONFIG_STM32_HCIUART_RXDMAPRIO) +# endif +#endif + +/* All interrupts */ + +#define HCIUART_ALLINTS (USART_CR1_USED_INTS | USART_CR3_EIE) +#define HCIUART_RXHANDLED (1 << 0) +#define HCIUART_TXHANDLED (1 << 1) + +/* Software flow control */ + +#ifdef CONFIG_STM32_HCIUART_SW_RXFLOW +# if (CONFIG_STM32_HCIUART_UPPER_WATERMARK < CONFIG_STM32_HCIUART_LOWER_WATERMARK) +# error The upper Rx flow control watermark is belong the lower watermake +# endif + +# define RXFLOW_UPPER(a) ((CONFIG_STM32_HCIUART_UPPER_WATERMARK * (a)) / 100) +# define RXFLOW_LOWER(a) ((CONFIG_STM32_HCIUART_LOWER_WATERMARK * (a)) / 100) +#endif + +/* Power management definitions */ + +#if defined(CONFIG_PM) && !defined(CONFIG_STM32_PM_SERIAL_ACTIVITY) +# define CONFIG_STM32_PM_SERIAL_ACTIVITY 10 +#endif + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/* This structure is the variable state of the HCI UART */ + +struct hciuart_state_s +{ + /* Registered Rx callback */ + + btuart_rxcallback_t callback; /* Rx callback function */ + void *arg; /* Rx callback argument */ + + /* Rx/Tx circular buffer management */ + + sem_t rxwait; /* Supports wait for more Rx data */ + sem_t txwait; /* Supports wait for space in Tx buffer */ + + uint32_t baud; /* Current BAUD selection */ + volatile uint16_t rxhead; /* Head and tail index of the Rx buffer */ + uint16_t rxtail; + uint16_t txhead; /* Head and tail index of the Tx buffer */ + volatile uint16_t txtail; + volatile bool rxwaiting; /* A thread is waiting for more Rx data */ + volatile bool txwaiting; /* A thread is waiting for space in the Tx buffer */ +#ifdef CONFIG_STM32_HCIUART_SW_RXFLOW + bool rxflow; /* True: software flow control is enable */ +#endif + + /* RX DMA state */ + +#ifdef CONFIG_STM32_HCIUART_RXDMA + uint16_t dmatail; /* Tail index of the Rx DMA buffer */ + bool rxenable; /* DMA-based reception en/disable */ + DMA_HANDLE rxdmastream; /* currently-open receive DMA stream */ +#endif +}; + +/* This structure is the constant configuration of the HCI UART */ + +struct hciuart_config_s +{ + struct btuart_lowerhalf_s lower; /* Generic HCI-UART lower half */ + struct hciuart_state_s *state; /* Reference to variable state */ + uint8_t *rxbuffer; /* Rx buffer start */ + uint8_t *txbuffer; /* Tx buffer start */ +#ifdef CONFIG_STM32_HCIUART_RXDMA + uint8_t *rxdmabuffer; /* Rx DMA buffer start */ +#endif + uint16_t rxbufsize; /* Size of the Rx buffer */ + uint16_t txbufsize; /* Size of the tx buffer */ +#ifdef CONFIG_STM32_HCIUART_SW_RXFLOW + uint16_t rxupper; /* Upper watermark to enable Rx flow control */ + uint16_t rxlower; /* Lower watermark to disable Rx flow control */ +#endif +#ifdef CONFIG_STM32_HCIUART_RXDMA + uint8_t rxdmachan; /* Rx DMA channel */ +#endif + uint8_t irq; /* IRQ associated with this USART */ + uint32_t baud; /* Configured baud */ + uint32_t apbclock; /* PCLK 1 or 2 frequency */ + uint32_t usartbase; /* Base address of USART registers */ + uint32_t tx_gpio; /* U[S]ART TX GPIO pin configuration */ + uint32_t rx_gpio; /* U[S]ART RX GPIO pin configuration */ + uint32_t cts_gpio; /* U[S]ART CTS GPIO pin configuration */ + uint32_t rts_gpio; /* U[S]ART RTS GPIO pin configuration */ + spinlock_t lock; /* Spinlock */ +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +static inline uint32_t hciuart_getreg32( + const struct hciuart_config_s *config, unsigned int offset); +static inline void hciuart_putreg32(const struct hciuart_config_s *config, + unsigned int offset, uint32_t value); +static void hciuart_enableints(const struct hciuart_config_s *config, + uint32_t intset); +static void hciuart_disableints(const struct hciuart_config_s *config, + uint32_t intset); +static bool hciuart_isenabled(const struct hciuart_config_s *config, + uint32_t intset); +static inline bool hciuart_rxenabled(const struct hciuart_config_s *config); +#ifdef CONFIG_STM32_HCIUART_RXDMA +static int hciuart_dma_nextrx(const struct hciuart_config_s *config); +#endif + +static uint16_t hciuart_rxinuse(const struct hciuart_config_s *config); +static void hciuart_rxflow_enable(const struct hciuart_config_s *config); +static void hciuart_rxflow_disable(const struct hciuart_config_s *config); +static ssize_t hciuart_copytorxbuffer(const struct hciuart_config_s *config); +static ssize_t hciuart_copyfromrxbuffer( + const struct hciuart_config_s *config, uint8_t *dest, + size_t destlen); +static ssize_t hciuart_copytotxfifo(const struct hciuart_config_s *config); +static void hciuart_line_configure(const struct hciuart_config_s *config); +static void hciuart_apbclock_enable(const struct hciuart_config_s *config); +static int hciuart_configure(const struct hciuart_config_s *config); +static int hciuart_interrupt(int irq, void *context, void *arg); + +/* HCI-UART Lower-Half Methods */ + +static void hciuart_rxattach(const struct btuart_lowerhalf_s *lower, + btuart_rxcallback_t callback, void *arg); +static void hciuart_rxenable(const struct btuart_lowerhalf_s *lower, + bool enable); +static int hciuart_setbaud(const struct btuart_lowerhalf_s *lower, + uint32_t baud); +static ssize_t hciuart_read(const struct btuart_lowerhalf_s *lower, + void *buffer, size_t buflen); +static ssize_t hciuart_write(const struct btuart_lowerhalf_s *lower, + const void *buffer, size_t buflen); +static ssize_t hciuart_rxdrain(const struct btuart_lowerhalf_s *lower); + +#ifdef CONFIG_STM32_HCIUART_RXDMA +static void hciuart_dma_rxcallback(DMA_HANDLE handle, uint8_t status, + void *arg); +#endif + +#ifdef CONFIG_PM +static void hciuart_pm_notify(struct pm_callback_s *cb, int dowmin, + enum pm_state_e pmstate); +static int hciuart_pm_prepare(struct pm_callback_s *cb, int domain, + enum pm_state_e pmstate); +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* This describes the state of the STM32 USART1 ports. */ + +#ifdef CONFIG_STM32_USART1_HCIUART +/* I/O buffers */ + +static uint8_t g_usart1_rxbuffer[CONFIG_STM32_HCIUART1_RXBUFSIZE]; +static uint8_t g_usart1_txbuffer[CONFIG_STM32_HCIUART1_TXBUFSIZE]; +# ifdef CONFIG_STM32_HCIUART1_RXDMA +static uint8_t g_usart1_rxdmabuffer[RXDMA_BUFFER_SIZE]; +# endif + +/* HCI USART1 variable state information */ + +static struct hciuart_state_s g_hciusart1_state = +{ + .rxwait = SEM_INITIALIZER(0), + .txwait = SEM_INITIALIZER(0), +}; + +/* HCI USART1 constant configuration information */ + +static const struct hciuart_config_s g_hciusart1_config = +{ + .lower = + { + .rxattach = hciuart_rxattach, + .rxenable = hciuart_rxenable, + .setbaud = hciuart_setbaud, + .read = hciuart_read, + .write = hciuart_write, + .rxdrain = hciuart_rxdrain, + }, + .state = &g_hciusart1_state, + + .rxbuffer = g_usart1_rxbuffer, + .txbuffer = g_usart1_txbuffer, +# ifdef CONFIG_STM32_HCIUART1_RXDMA + .rxdmabuffer = g_usart1_rxdmabuffer, +# endif + .rxbufsize = CONFIG_STM32_HCIUART1_RXBUFSIZE, + .txbufsize = CONFIG_STM32_HCIUART1_TXBUFSIZE, +# ifdef CONFIG_STM32_HCIUART_SW_RXFLOW + .rxupper = RXFLOW_UPPER(CONFIG_STM32_HCIUART1_RXBUFSIZE), + .rxlower = RXFLOW_LOWER(CONFIG_STM32_HCIUART1_RXBUFSIZE), +# endif +# ifdef CONFIG_STM32_HCIUART_RXDMA + .rxdmachan = DMAMAP_USART1_RX, +# endif + + .irq = STM32_IRQ_USART1, + .baud = CONFIG_STM32_HCIUART1_BAUD, +# if defined(CONFIG_STM32_STM32F33XX) + .apbclock = STM32_PCLK1_FREQUENCY, /* Errata 2.5.1 */ +# else + .apbclock = STM32_PCLK2_FREQUENCY, +# endif + .usartbase = STM32_USART1_BASE, + .tx_gpio = GPIO_USART1_TX, + .rx_gpio = GPIO_USART1_RX, + .cts_gpio = GPIO_USART1_CTS, + .rts_gpio = GPIO_USART1_RTS, + .lock = SP_UNLOCKED +}; +#endif + +/* This describes the state of the STM32 USART2 port. */ + +#ifdef CONFIG_STM32_USART2_HCIUART +/* I/O buffers */ + +static uint8_t g_usart2_rxbuffer[CONFIG_STM32_HCIUART2_RXBUFSIZE]; +static uint8_t g_usart2_txbuffer[CONFIG_STM32_HCIUART2_TXBUFSIZE]; +# ifdef CONFIG_STM32_HCIUART2_RXDMA +static uint8_t g_usart2_rxdmabuffer[RXDMA_BUFFER_SIZE]; +# endif + +/* HCI USART2 variable state information */ + +static struct hciuart_state_s g_hciusart2_state = +{ + .rxwait = SEM_INITIALIZER(0), + .txwait = SEM_INITIALIZER(0), +}; + +/* HCI USART2 constant configuration information */ + +static const struct hciuart_config_s g_hciusart2_config = +{ + .lower = + { + .rxattach = hciuart_rxattach, + .rxenable = hciuart_rxenable, + .setbaud = hciuart_setbaud, + .read = hciuart_read, + .write = hciuart_write, + .rxdrain = hciuart_rxdrain, + }, + .state = &g_hciusart2_state, + + .rxbuffer = g_usart2_rxbuffer, + .txbuffer = g_usart2_txbuffer, +# ifdef CONFIG_STM32_HCIUART2_RXDMA + .rxdmabuffer = g_usart2_rxdmabuffer, +# endif + .rxbufsize = CONFIG_STM32_HCIUART2_RXBUFSIZE, + .txbufsize = CONFIG_STM32_HCIUART2_TXBUFSIZE, +# ifdef CONFIG_STM32_HCIUART_SW_RXFLOW + .rxupper = RXFLOW_UPPER(CONFIG_STM32_HCIUART2_RXBUFSIZE), + .rxlower = RXFLOW_LOWER(CONFIG_STM32_HCIUART2_RXBUFSIZE), +# endif +# ifdef CONFIG_STM32_HCIUART_RXDMA + .rxdmachan = DMAMAP_USART2_RX, +# endif + + .irq = STM32_IRQ_USART2, + .baud = CONFIG_STM32_HCIUART2_BAUD, + .apbclock = STM32_PCLK1_FREQUENCY, + .usartbase = STM32_USART2_BASE, + .tx_gpio = GPIO_USART2_TX, + .rx_gpio = GPIO_USART2_RX, + .cts_gpio = GPIO_USART2_CTS, + .rts_gpio = GPIO_USART2_RTS, + .lock = SP_UNLOCKED +}; +#endif + +/* This describes the state of the STM32 USART3 port. */ + +#ifdef CONFIG_STM32_USART3_HCIUART +/* I/O buffers */ + +static uint8_t g_usart3_rxbuffer[CONFIG_STM32_HCIUART3_RXBUFSIZE]; +static uint8_t g_usart3_txbuffer[CONFIG_STM32_HCIUART3_TXBUFSIZE]; +# ifdef CONFIG_STM32_HCIUART3_RXDMA +static uint8_t g_usart3_rxdmabuffer[RXDMA_BUFFER_SIZE]; +# endif + +/* HCI USART3 variable state information */ + +static struct hciuart_state_s g_hciusart3_state = +{ + .rxwait = SEM_INITIALIZER(0), + .txwait = SEM_INITIALIZER(0), +}; + +/* HCI USART3 constant configuration information */ + +static const struct hciuart_config_s g_hciusart3_config = +{ + .lower = + { + .rxattach = hciuart_rxattach, + .rxenable = hciuart_rxenable, + .setbaud = hciuart_setbaud, + .read = hciuart_read, + .write = hciuart_write, + .rxdrain = hciuart_rxdrain, + }, + .state = &g_hciusart3_state, + + .rxbuffer = g_usart3_rxbuffer, + .txbuffer = g_usart3_txbuffer, +# ifdef CONFIG_STM32_HCIUART3_RXDMA + .rxdmabuffer = g_usart3_rxdmabuffer, +# endif + .rxbufsize = CONFIG_STM32_HCIUART3_RXBUFSIZE, + .txbufsize = CONFIG_STM32_HCIUART3_TXBUFSIZE, +# ifdef CONFIG_STM32_HCIUART_SW_RXFLOW + .rxupper = RXFLOW_UPPER(CONFIG_STM32_HCIUART3_RXBUFSIZE), + .rxlower = RXFLOW_LOWER(CONFIG_STM32_HCIUART3_RXBUFSIZE), +# endif +# ifdef CONFIG_STM32_HCIUART_RXDMA + .rxdmachan = DMAMAP_USART3_RX, +# endif + + .irq = STM32_IRQ_USART3, + .baud = CONFIG_STM32_HCIUART3_BAUD, + .apbclock = STM32_PCLK1_FREQUENCY, + .usartbase = STM32_USART3_BASE, + .tx_gpio = GPIO_USART3_TX, + .rx_gpio = GPIO_USART3_RX, + .cts_gpio = GPIO_USART3_CTS, + .rts_gpio = GPIO_USART3_RTS, + .lock = SP_UNLOCKED +}; +#endif + +/* This describes the state of the STM32 USART6 port. */ + +#ifdef CONFIG_STM32_USART6_HCIUART +/* I/O buffers */ + +static uint8_t g_usart6_rxbuffer[CONFIG_STM32_HCIUART6_RXBUFSIZE]; +static uint8_t g_usart6_txbuffer[CONFIG_STM32_HCIUART6_TXBUFSIZE]; +# ifdef CONFIG_STM32_HCIUART6_RXDMA +static uint8_t g_usart6_rxdmabuffer[RXDMA_BUFFER_SIZE]; +# endif + +/* HCI USART6 variable state information */ + +static struct hciuart_state_s g_hciusart6_state = +{ + .rxwait = SEM_INITIALIZER(0), + .txwait = SEM_INITIALIZER(0), +}; + +/* HCI USART6 constant configuration information */ + +static const struct hciuart_config_s g_hciusart6_config = +{ + .lower = + { + .rxattach = hciuart_rxattach, + .rxenable = hciuart_rxenable, + .setbaud = hciuart_setbaud, + .read = hciuart_read, + .write = hciuart_write, + .rxdrain = hciuart_rxdrain, + }, + .state = &g_hciusart6_state, + + .rxbuffer = g_usart6_rxbuffer, + .txbuffer = g_usart6_txbuffer, +# ifdef CONFIG_STM32_HCIUART6_RXDMA + .rxdmabuffer = g_usart6_rxdmabuffer, +# endif + .rxbufsize = CONFIG_STM32_HCIUART6_RXBUFSIZE, + .txbufsize = CONFIG_STM32_HCIUART6_TXBUFSIZE, +# ifdef CONFIG_STM32_HCIUART_SW_RXFLOW + .rxupper = RXFLOW_UPPER(CONFIG_STM32_HCIUART6_RXBUFSIZE), + .rxlower = RXFLOW_LOWER(CONFIG_STM32_HCIUART6_RXBUFSIZE), +# endif +# ifdef CONFIG_STM32_HCIUART_RXDMA + .rxdmachan = DMAMAP_USART6_RX, +# endif + + .irq = STM32_IRQ_USART6, + .baud = CONFIG_STM32_HCIUART6_BAUD, + .apbclock = STM32_PCLK2_FREQUENCY, + .usartbase = STM32_USART6_BASE, + .tx_gpio = GPIO_USART6_TX, + .rx_gpio = GPIO_USART6_RX, + .cts_gpio = GPIO_USART6_CTS, + .rts_gpio = GPIO_USART6_RTS, + .lock = SP_UNLOCKED +}; +#endif + +/* This describes the state of the STM32 UART7 port. */ + +#ifdef CONFIG_STM32_UART7_HCIUART +/* I/O buffers */ + +static uint8_t g_uart7_rxbuffer[CONFIG_STM32_HCIUART7_RXBUFSIZE]; +static uint8_t g_uart7_txbuffer[CONFIG_STM32_HCIUART7_TXBUFSIZE]; +# ifdef CONFIG_STM32_HCIUART7_RXDMA +static uint8_t g_uart7_rxdmabuffer[RXDMA_BUFFER_SIZE]; +# endif + +/* HCI UART7 variable state information */ + +static struct hciuart_state_s g_hciuart7_state = +{ + .rxwait = SEM_INITIALIZER(0), + .txwait = SEM_INITIALIZER(0), +}; + +/* HCI UART7 constant configuration information */ + +static const struct hciuart_config_s g_hciuart7_config = +{ + .lower = + { + .rxattach = hciuart_rxattach, + .rxenable = hciuart_rxenable, + .setbaud = hciuart_setbaud, + .read = hciuart_read, + .write = hciuart_write, + .rxdrain = hciuart_rxdrain, + }, + .state = &g_hciuart7_state, + + .rxbuffer = g_uart7_rxbuffer, + .txbuffer = g_uart7_txbuffer, +# ifdef CONFIG_STM32_HCIUART7_RXDMA + .rxdmabuffer = g_uart7_rxdmabuffer, +# endif + .rxbufsize = CONFIG_STM32_HCIUART7_RXBUFSIZE, + .txbufsize = CONFIG_STM32_HCIUART7_TXBUFSIZE, +# ifdef CONFIG_STM32_HCIUART_SW_RXFLOW + .rxupper = RXFLOW_UPPER(CONFIG_STM32_HCIUART7_RXBUFSIZE), + .rxlower = RXFLOW_LOWER(CONFIG_STM32_HCIUART7_RXBUFSIZE), +# endif +# ifdef CONFIG_STM32_HCIUART_RXDMA + .rxdmachan = DMAMAP_UART7_RX, +# endif + + .irq = STM32_IRQ_UART7, + .baud = CONFIG_STM32_HCIUART7_BAUD, + .apbclock = STM32_PCLK1_FREQUENCY, + .usartbase = STM32_UART7_BASE, + .tx_gpio = GPIO_UART7_TX, + .rx_gpio = GPIO_UART7_RX, + .cts_gpio = GPIO_UART7_CTS, + .rts_gpio = GPIO_UART7_RTS, + .lock = SP_UNLOCKED +}; +#endif + +/* This describes the state of the STM32 UART8 port. */ + +#ifdef CONFIG_STM32_UART8_HCIUART +/* I/O buffers */ + +static uint8_t g_uart8_rxbuffer[CONFIG_STM32_HCIUART8_RXBUFSIZE]; +static uint8_t g_uart8_txbuffer[CONFIG_STM32_HCIUART8_TXBUFSIZE]; +# ifdef CONFIG_STM32_HCIUART8_RXDMA +static uint8_t g_uart8_rxdmabuffer[RXDMA_BUFFER_SIZE]; +# endif + +/* HCI UART8 variable state information */ + +static struct hciuart_state_s g_hciuart8_state = +{ + .rxwait = SEM_INITIALIZER(0), + .txwait = SEM_INITIALIZER(0), +}; + +/* HCI UART8 constant configuration information */ + +static const struct hciuart_config_s g_hciuart8_config = +{ + .lower = + { + .rxattach = hciuart_rxattach, + .rxenable = hciuart_rxenable, + .setbaud = hciuart_setbaud, + .read = hciuart_read, + .write = hciuart_write, + .rxdrain = hciuart_rxdrain, + }, + .state = &g_hciuart8_state, + + .rxbuffer = g_uart8_rxbuffer, + .txbuffer = g_uart8_txbuffer, +# ifdef CONFIG_STM32_HCIUART8_RXDMA + .rxdmabuffer = g_uart8_rxdmabuffer, +# endif + .rxbufsize = CONFIG_STM32_HCIUART8_RXBUFSIZE, + .txbufsize = CONFIG_STM32_HCIUART8_TXBUFSIZE, +# ifdef CONFIG_STM32_HCIUART_SW_RXFLOW + .rxupper = RXFLOW_UPPER(CONFIG_STM32_HCIUART8_RXBUFSIZE), + .rxlower = RXFLOW_LOWER(CONFIG_STM32_HCIUART8_RXBUFSIZE), +# endif +# ifdef CONFIG_STM32_HCIUART_RXDMA + .rxdmachan = DMAMAP_UART8_RX, +# endif + + .irq = STM32_IRQ_UART8, + .baud = CONFIG_STM32_HCIUART8_BAUD, + .apbclock = STM32_PCLK1_FREQUENCY, + .usartbase = STM32_UART8_BASE, + .tx_gpio = GPIO_UART8_TX, + .rx_gpio = GPIO_UART8_RX, + .cts_gpio = GPIO_UART8_CTS, + .rts_gpio = GPIO_UART8_RTS, + .lock = SP_UNLOCKED +}; +#endif + +/* This table lets us iterate over the configured USARTs */ + +static const struct hciuart_config_s * const g_hciuarts[STM32_NUSART] = +{ +#ifdef CONFIG_STM32_USART1_HCIUART + [0] = &g_hciusart1_config, +#endif +#ifdef CONFIG_STM32_USART2_HCIUART + [1] = &g_hciusart2_config, +#endif +#ifdef CONFIG_STM32_USART3_HCIUART + [2] = &g_hciusart3_config, +#endif +#ifdef CONFIG_STM32_USART6_HCIUART + [4] = &g_hciusart6_config, +#endif +#ifdef CONFIG_STM32_UART7_HCIUART + [5] = &g_hciuart7_config, +#endif +#ifdef CONFIG_STM32_UART8_HCIUART + [6] = &g_hciuart8_config, +#endif +}; + +#ifdef CONFIG_PM +static struct pm_callback_s g_serialcb = +{ + .notify = hciuart_pm_notify, + .prepare = hciuart_pm_prepare, +}; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: hciuart_getreg32 + ****************************************************************************/ + +static inline uint32_t + hciuart_getreg32(const struct hciuart_config_s *config, + unsigned int offset) +{ + return getreg32(config->usartbase + offset); +} + +/**************************************************************************** + * Name: hciuart_putreg32 + ****************************************************************************/ + +static inline void hciuart_putreg32(const struct hciuart_config_s *config, + unsigned int offset, uint32_t value) +{ + putreg32(value, config->usartbase + offset); +} + +/**************************************************************************** + * Name: hciuart_enableints + * + * Description: + * Enable interrupts as specified by bits in the 'intset' argument + * + * NOTE: This operation is not atomic. This function should be called + * only from within a critical section. + * + ****************************************************************************/ + +static void hciuart_enableints(const struct hciuart_config_s *config, + uint32_t intset) +{ + uint32_t cr1; + uint32_t cr2; + + /* And restore the interrupt state (see the interrupt enable/usage table + * above) + */ + + cr1 = hciuart_getreg32(config, STM32_USART_CR1_OFFSET); + cr1 |= (intset & USART_CR1_USED_INTS); + hciuart_putreg32(config, STM32_USART_CR1_OFFSET, cr1); + + cr2 = hciuart_getreg32(config, STM32_USART_CR3_OFFSET); + cr2 |= (intset & USART_CR3_EIE); + hciuart_putreg32(config, STM32_USART_CR3_OFFSET, cr2); + + wlinfo("CR1 %08" PRIx32 " CR2 %08" PRIx32 "\n", cr1, cr2); +} + +/**************************************************************************** + * Name: hciuart_disableints + * + * Description: + * Disable interrupts as specified by bits in the 'intset' argument + * + * NOTE: This operation is not atomic. This function should be called + * only from within a critical section. + * + ****************************************************************************/ + +static void hciuart_disableints(const struct hciuart_config_s *config, + uint32_t intset) +{ + uint32_t cr1; + uint32_t cr2; + + /* And restore the interrupt state (see the interrupt enable/usage table + * above) + */ + + cr1 = hciuart_getreg32(config, STM32_USART_CR1_OFFSET); + cr1 &= ~(intset & USART_CR1_USED_INTS); + hciuart_putreg32(config, STM32_USART_CR1_OFFSET, cr1); + + cr2 = hciuart_getreg32(config, STM32_USART_CR3_OFFSET); + cr2 &= ~(intset & USART_CR3_EIE); + hciuart_putreg32(config, STM32_USART_CR3_OFFSET, cr2); + + wlinfo("CR1 %08" PRIx32 " CR2 %08" PRIx32 "\n", cr1, cr2); +} + +/**************************************************************************** + * Name: hciuart_isenabled + * + * Description: + * Return true if any any of the interrupts specified in the 'intset' + * argument are enabled. + * + ****************************************************************************/ + +static bool hciuart_isenabled(const struct hciuart_config_s *config, + uint32_t intset) +{ + uint32_t regval; + + /* And restore the interrupt state (see the interrupt enable/usage table + * above) + */ + + regval = hciuart_getreg32(config, STM32_USART_CR1_OFFSET); + regval &= USART_CR1_USED_INTS; + if ((regval & intset) != 0) + { + return true; + } + + regval = hciuart_getreg32(config, STM32_USART_CR3_OFFSET); + regval &= USART_CR3_EIE; + if ((regval & intset) != 0) + { + return true; + } + + return false; +} + +/**************************************************************************** + * Name: hciuart_rxenabled + * + * Description: + * Check if Rx interrupts are enabled. + * + ****************************************************************************/ + +static inline bool hciuart_rxenabled(const struct hciuart_config_s *config) +{ +#ifdef CONFIG_STM32_HCIUART_RXDMA + const struct hciuart_config_s *state = config->state; + + if (config->rxdmabuffer != NULL) + { + return state->rxenabled; + } + else +#endif + { + return hciuart_isenabled(config, USART_CR1_RXNEIE); + } +} + +/**************************************************************************** + * Name: hciuart_dma_nextrx + * + * Description: + * Returns the index into the RX FIFO where the DMA will place the next + * byte that it receives. + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_HCIUART_RXDMA +static int hciuart_dma_nextrx(const struct hciuart_config_s *config) +{ + struct hciuart_state_s *state = config->state; + size_t dmaresidual; + + dmaresidual = stm32_dmaresidual(state->rxdmastream); + + return (RXDMA_BUFFER_SIZE - (int)dmaresidual); +} +#endif + +/**************************************************************************** + * Name: hciuart_rxinuse + * + * Description: + * Return the number of bytes in the Rx buffer + * + * Example: rxbufsize=4, rxhead = 0, rxtail = 2 + * + * +---+---+---+---+ + * | X | X | | | X = inuse + * +---+---+---+---+ + * | `- rxtail = 2 + * `- rxhead = 0 + * + * inuse = 2 - 0 = 2 + * + * Example: rxbufsize=4, rxhead = 2, rxtail = 0 + * + * +---+---+---+---+ + * | | | X | X | X = inuse + * +---+---+---+---+ + * | `- rxhead = 2 + * `- rxtail = 0 + * + * inuse = (0 + 4) - 2 = 2 + * + ****************************************************************************/ + +static uint16_t hciuart_rxinuse(const struct hciuart_config_s *config) +{ + struct hciuart_state_s *state; + size_t inuse; + + DEBUGASSERT(config != NULL && config->state != NULL); + state = config->state; + + /* Keep track of how much is discarded */ + + if (state->rxtail >= state->rxhead) + { + inuse = state->rxtail - state->rxhead; + } + else + { + inuse = (state->rxtail + config->rxbufsize) - state->rxhead; + } + + wlinfo("inuse %lu\n", (unsigned long)inuse); + return inuse; +} + +/**************************************************************************** + * Name: hciuart_rxflow_enable + * + * Description: + * Enable software Rx flow control, i.e., deassert the RTS output. This + * will be seen as CTS on the other end of the cable and the HCI UART + * device must stop sending data. + * + * NOTE: RTS is logic low + * + ****************************************************************************/ + +static void hciuart_rxflow_enable(const struct hciuart_config_s *config) +{ +#ifdef CONFIG_STM32_HCIUART_SW_RXFLOW + struct hciuart_state_s *state; + + DEBUGASSERT(config != NULL && config->state != NULL); + state = config->state; + + /* Is Rx flow control already enable? */ + + if (!state->rxflow) + { + uint16_t inused = hciuart_rxinuse(config); + + if (inused >= config->rxupper) + { + wlinfo("Enable RTS flow control\n"); + + stm32_gpiowrite(config->rts_gpio, true); + state->rxflow = true; + } + } +#endif +} + +/**************************************************************************** + * Name: hciuart_rxflow_disable + * + * Description: + * Disable software Rx flow control, i.e., assert the RTS output. This + * will be seen as CTS on the other end of the cable and the HCI UART + * device can resume sending data. + * + * NOTE: RTS is logic low + * + ****************************************************************************/ + +static void hciuart_rxflow_disable(const struct hciuart_config_s *config) +{ +#ifdef CONFIG_STM32_HCIUART_SW_RXFLOW + struct hciuart_state_s *state; + + DEBUGASSERT(config != NULL && config->state != NULL); + state = config->state; + + if (state->rxflow) + { + uint16_t inused = hciuart_rxinuse(config); + + if (inused <= config->rxlower) + { + wlinfo("Disable RTS flow control\n"); + + stm32_gpiowrite(config->rts_gpio, false); + state->rxflow = false; + } + } +#endif +} + +/**************************************************************************** + * Name: hciuart_copytorxbuffer + * + * Description: + * Copy data to the driver Rx buffer. The source is either the U[S]ART + * Rx FIFO or the Rx DMA buffer, depending upon the configuration. + * + ****************************************************************************/ + +static ssize_t hciuart_copytorxbuffer(const struct hciuart_config_s *config) +{ + struct hciuart_state_s *state; + ssize_t nbytes = 0; + uint16_t rxhead; + uint16_t rxtail; + uint16_t rxnext; +#ifdef CONFIG_STM32_HCIUART_RXDMA + uint16_t dmatail; +#endif + uint8_t rxbyte; + + /* Get a copy of the rxhead and rxtail indices of the Rx buffer */ + + state = config->state; + rxhead = state->rxhead; + rxtail = state->rxtail; + +#ifdef CONFIG_STM32_HCIUART_RXDMA + if (config->rxdmabuffer != NULL) + { + /* Get a copy of the dmatail index of the Rx DMA buffer */ + + dmatail = state->dmatail; + + /* Compare dmatail to the current DMA pointer, if they do notmatch, + * then there is new Rx data available in the Rx DMA buffer. + */ + + while ((hciuart_dma_nextrx(config) != dmatail)) + { + /* Compare the Rx buffer head and tail indices. If the + * incremented tail index would make the Rx buffer appear empty, + * then we must stop the copy. If there is data pending in the Rx + * DMA buffer, this could be very bad because a data overrun + * condition is likely to occur. + */ + + rxnext = rxtail + 1; + if (rxnext >= config->rxbufsize) + { + rxnext = 0 + } + + /* Would this make the Rx buffer appear full? */ + + if (rxnext == rxhead) + { + /* Yes, stop the copy and update the indices */ + + break; + } + + /* Get a byte from the Rx DMA buffer */ + + rxbyte = config->rxdmabuffer[dmatail]; + + if (++dmatail >= RXDMA_BUFFER_SIZE) + { + dmatail = 0; + } + + /* And add it to the tail of the Rx buffer */ + + config->rxbuffer[rxtail] = rxbyte; + rxtail = rxnext; + nbytes++; + } + + state->dmatail = dmatail; + } + else +#endif + { + /* Is there data available in the Rx FIFO? */ + + while ((hciuart_getreg32(config, STM32_USART_SR_OFFSET) & + USART_SR_RXNE) != 0) + { + /* Compare the Rx buffer head and tail indices. If the + * incremented tail index would make the Rx buffer appear empty, + * then we must stop the copy. If there is data pending in the Rx + * FIFO, this could be very bad because a data overrun condition + * is likely to* occur. + */ + + rxnext = rxtail + 1; + if (rxnext >= config->rxbufsize) + { + rxnext = 0; + } + + /* Would this make the Rx buffer appear full? */ + + if (rxnext == rxhead) + { + /* Yes, stop the copy and update the indices */ + + break; + } + + /* Get a byte from the Rx FIFO buffer */ + + rxbyte = hciuart_getreg32(config, STM32_USART_RDR_OFFSET) & 0xff; + + /* And add it to the tail of the Rx buffer */ + + config->rxbuffer[rxtail] = rxbyte; + rxtail = rxnext; + nbytes++; + } + } + + /* Save the updated Rx buffer tail index */ + + state->rxtail = rxtail; + + /* Check if we need to enable Rx flow control */ + + hciuart_rxflow_enable(config); + + /* Notify any waiting threads that new Rx data is available */ + + if (nbytes > 0 && state->rxwaiting) + { + state->rxwaiting = false; + nxsem_post(&state->rxwait); + } + + wlinfo("rxhead %u rxtail %u nbytes %ld\n", rxhead, rxtail, (long)nbytes); + return nbytes; +} + +/**************************************************************************** + * Name: hciuart_copyfromrxbuffer + * + * Description: + * Copy data from the driver Rx buffer to the caller provided destination + * buffer. + * + ****************************************************************************/ + +static ssize_t + hciuart_copyfromrxbuffer(const struct hciuart_config_s *config, + uint8_t *dest, size_t destlen) +{ + struct hciuart_state_s *state; + ssize_t nbytes; + uint16_t rxhead; + uint16_t rxtail; + uint8_t rxbyte; + + /* Get a copy of the rxhead and rxtail indices of the Rx buffer */ + + state = config->state; + rxhead = state->rxhead; + rxtail = state->rxtail; + nbytes = 0; + + /* Is there data available in the Rx buffer? Is there space in the user + * buffer? + */ + + while (rxhead != rxtail && nbytes < destlen) + { + /* Get a byte from the head of the Rx buffer */ + + rxbyte = config->rxbuffer[rxhead]; + + /* And add it to the caller's buffer buffer */ + + dest[nbytes] = rxbyte; + + /* Update indices and counts */ + + nbytes++; + + if (++rxhead >= config->rxbufsize) + { + rxhead = 0; + } + + /* Check if we need to disable Rx flow control */ + + hciuart_rxflow_disable(config); + } + + /* Save the updated Rx buffer head index */ + + state->rxhead = rxhead; + + wlinfo("rxhead %u rxtail %u nbytes %ld\n", rxhead, rxtail, (long)nbytes); + return nbytes; +} + +/**************************************************************************** + * Name: hciuart_copytotxfifo + * + * Description: + * Copy data from the Tx buffer to the Tx FIFO + * + ****************************************************************************/ + +static ssize_t hciuart_copytotxfifo(const struct hciuart_config_s *config) +{ + struct hciuart_state_s *state; + ssize_t nbytes; + uint16_t txhead; + uint16_t txtail; + uint8_t txbyte; + + /* Get a copy of the txhead and txtail indices of the Rx buffer */ + + state = config->state; + txhead = state->txhead; + txtail = state->txtail; + nbytes = 0; + + /* Compare the Tx buffer head and tail indices. If the Tx buffer is + * empty, then we finished with the copy. + */ + + while (txhead != txtail) + { + /* Is the transmit data register empty? + * + * TXE: Transmit data register empty + * This bit is set by hardware when the content of the TDR register + * has been transferred into the shift register. + */ + + if ((hciuart_getreg32(config, STM32_USART_SR_OFFSET) & + USART_SR_TXE) == 0) + { + break; + } + + /* Get a byte from the head of the Tx buffer */ + + txbyte = config->txbuffer[txhead]; + if (++txhead >= config->txbufsize) + { + txhead = 0; + } + + /* And add it to the of the Tx FIFO */ + + hciuart_putreg32(config, STM32_USART_TDR_OFFSET, (uint32_t)txbyte); + nbytes++; + } + + wlinfo("txhead %u txtail %u nbytes %ld\n", txhead, txtail, (long)nbytes); + state->txhead = txhead; + return nbytes; +} + +/**************************************************************************** + * Name: hciuart_line_configure + * + * Description: + * Set the serial line format and speed. + * + * Per "Specification of the Bluetooth System, Wireless connections made + * easy, Host Controller Interface [Transport Layer]", Volume 4, Revision + * 1.2 or later, 1 January 2006, HCI UART transport uses these settings: + * + * 8 data bits, no parity, 1 stop, RTS/CTS flow control + * + * BAUD and flow control response time are manufacturer specific. + * + ****************************************************************************/ + +static void hciuart_line_configure(const struct hciuart_config_s *config) +{ +#if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) || \ + defined(CONFIG_STM32_STM32F37XX) + uint32_t usartdiv8; +#else + uint32_t usartdiv32; + uint32_t mantissa; + uint32_t fraction; +#endif + uint32_t baud; + uint32_t regval; + uint32_t brr; + + /* The current BAUD selection is part of the variable state data */ + + DEBUGASSERT(config != NULL && config->state != NULL); + baud = config->state->baud; + + wlinfo("baud %lu\n", (unsigned long)baud); + + /* Load CR1 */ + + regval = hciuart_getreg32(config, STM32_USART_CR1_OFFSET); + +#if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX)|| \ + defined(CONFIG_STM32_STM32F37XX) + /* This first implementation is for U[S]ARTs that support oversampling + * by 8 in additional to the standard oversampling by 16. + * With baud rate of fCK / Divider for oversampling by 16. + * and baud rate of 2 * fCK / Divider for oversampling by 8 + * + * In case of oversampling by 8, the equation is: + * + * baud = 2 * fCK / usartdiv8 + * usartdiv8 = 2 * fCK / baud + */ + + usartdiv8 = ((config->apbclock << 1) + (baud >> 1)) / baud; + + /* Baud rate for standard USART (SPI mode included): + * + * In case of oversampling by 16, the equation is: + * baud = fCK / usartdiv16 + * usartdiv16 = fCK / baud + * = 2 * usartdiv8 + * + * Use oversamply by 8 only if the divisor is small. But what is small? + */ + + if (usartdiv8 > 100) + { + /* Use usartdiv16 */ + + brr = (usartdiv8 + 1) >> 1; + + /* Clear oversampling by 8 to enable oversampling by 16 */ + + regval &= ~USART_CR1_OVER8; + } + else + { + DEBUGASSERT(usartdiv8 >= 8); + + /* Perform mysterious operations on bits 0-3 */ + + brr = ((usartdiv8 & 0xfff0) | ((usartdiv8 & 0x000f) >> 1)); + + /* Set oversampling by 8 */ + + regval |= USART_CR1_OVER8; + } + +#else + /* This second implementation is for U[S]ARTs that support fractional + * dividers. + * + * Configure the USART Baud Rate. The baud rate for the receiver and + * transmitter (Rx and Tx) are both set to the same value as programmed + * in the Mantissa and Fraction values of USARTDIV. + * + * baud = fCK / (16 * usartdiv) + * usartdiv = fCK / (16 * baud) + * + * Where fCK is the input clock to the peripheral (PCLK1 for USART2, 3, + * 4, 5 or PCLK2 for USART1) + * + * First calculate (NOTE: all stand baud values are even so dividing by + * two does not lose precision): + * + * usartdiv32 = 32 * usartdiv = fCK / (baud/2) + */ + + usartdiv32 = config->apbclock / (baud >> 1); + + /* The mantissa part is then */ + + mantissa = usartdiv32 >> 5; + + /* The fractional remainder (with rounding) */ + + fraction = (usartdiv32 - (mantissa << 5) + 1) >> 1; + +#if defined(CONFIG_STM32_STM32F4XXX) + /* The F4 supports 8 X in oversampling additional to the + * standard oversampling by 16. + * + * With baud rate of fCK / (16 * Divider) for oversampling by 16. + * and baud rate of fCK / (8 * Divider) for oversampling by 8 + */ + + /* Check if 8x oversampling is necessary */ + + if (mantissa == 0) + { + regval |= USART_CR1_OVER8; + + /* Rescale the mantissa */ + + mantissa = usartdiv32 >> 4; + + /* The fractional remainder (with rounding) */ + + fraction = (usartdiv32 - (mantissa << 4) + 1) >> 1; + } + else + { + /* Use 16x Oversampling */ + + regval &= ~USART_CR1_OVER8; + } +#endif + + brr = mantissa << USART_BRR_MANT_SHIFT; + brr |= fraction << USART_BRR_FRAC_SHIFT; +#endif + + hciuart_putreg32(config, STM32_USART_CR1_OFFSET, regval); + hciuart_putreg32(config, STM32_USART_BRR_OFFSET, brr); + + /* Configure parity mode and word length + * + * HCI UART spec requires: 8 data bits, No parity + */ + + regval &= ~(USART_CR1_PCE | USART_CR1_PS | USART_CR1_M); + hciuart_putreg32(config, STM32_USART_CR1_OFFSET, regval); + + /* Configure STOP bits + * + * HCI UART spec requires: 1 stop bit + */ + + regval = hciuart_getreg32(config, STM32_USART_CR2_OFFSET); + regval &= ~(USART_CR2_STOP_MASK); + hciuart_putreg32(config, STM32_USART_CR2_OFFSET, regval); + + /* Configure hardware flow control */ + + regval = hciuart_getreg32(config, STM32_USART_CR3_OFFSET); + regval &= ~(USART_CR3_CTSE | USART_CR3_RTSE); + + /* Use software controlled RTS flow control. Because STM current STM32 + * have broken HW based RTS behavior (they assert nRTS after every byte + * received) Enable this setting workaround this issue by using software + * based management of RTS. + */ + +#ifndef CONFIG_STM32_HCIUART_SW_RXFLOW + regval |= USART_CR3_RTSE; +#endif + regval |= USART_CR3_CTSE; + + hciuart_putreg32(config, STM32_USART_CR3_OFFSET, regval); +} + +/**************************************************************************** + * Name: hciuart_apbclock_enable + * + * Description: + * Enable or disable APB clock for the USART peripheral + * + * Input Parameters: + * lower - A reference to the UART driver state structure + * on - Enable clock if 'on' is 'true' and disable if 'false' + * + ****************************************************************************/ + +static void hciuart_apbclock_enable(const struct hciuart_config_s *config) +{ + uint32_t rcc_en; + uint32_t regaddr; + + /* Determine which USART to configure */ + + switch (config->usartbase) + { +#ifdef CONFIG_STM32_USART1_HCIUART + case STM32_USART1_BASE: + rcc_en = RCC_APB2ENR_USART1EN; + regaddr = STM32_RCC_APB2ENR; + break; +#endif + +#ifdef CONFIG_STM32_USART2_HCIUART + case STM32_USART2_BASE: + rcc_en = RCC_APB1ENR_USART2EN; + regaddr = STM32_RCC_APB1ENR; + break; +#endif + +#ifdef CONFIG_STM32_USART3_HCIUART + case STM32_USART3_BASE: + rcc_en = RCC_APB1ENR_USART3EN; + regaddr = STM32_RCC_APB1ENR; + break; +#endif + +#ifdef CONFIG_STM32_USART6_HCIUART + case STM32_USART6_BASE: + rcc_en = RCC_APB2ENR_USART6EN; + regaddr = STM32_RCC_APB2ENR; + break; +#endif + +#ifdef CONFIG_STM32_UART7_HCIUART + case STM32_UART7_BASE: + rcc_en = RCC_APB1ENR_UART7EN; + regaddr = STM32_RCC_APB1ENR; + break; +#endif + +#ifdef CONFIG_STM32_UART8_HCIUART + case STM32_UART8_BASE: + rcc_en = RCC_APB1ENR_UART8EN; + regaddr = STM32_RCC_APB1ENR; + break; +#endif + + default: + return; + } + + /* Enable/disable APB 1/2 clock for USART */ + + modifyreg32(regaddr, 0, rcc_en); +} + +/**************************************************************************** + * Name: hciuart_configure + * + * Description: + * Configure the USART clocking, GPIO pins, baud, bits, parity, etc. + * + * Per "Specification of the Bluetooth System, Wireless connections made + * easy, Host Controller Interface [Transport Layer]", Volume 4, Revision + * 1.2 or later, 1 January 2006, HCI UART transport uses these settings: + * + * 8 data bits, no parity, 1 stop, RTS/CTS flow control + * + * BAUD and flow control response time are manufacturer specific. + * + ****************************************************************************/ + +static int hciuart_configure(const struct hciuart_config_s *config) +{ + uint32_t regval; + uint32_t pinset; + + /* Note: The logic here depends on the fact that that the USART module + * was enabled in stm32_lowsetup(). + */ + + wlinfo("config %p\n", config); + + /* Enable USART APB1/2 clock */ + + hciuart_apbclock_enable(config); + + /* Configure pins for USART use */ + + stm32_configgpio(config->tx_gpio); + stm32_configgpio(config->rx_gpio); + stm32_configgpio(config->cts_gpio); + + pinset = config->rts_gpio; + +#ifdef CONFIG_STM32_HCIUART_SW_RXFLOW + /* Use software controlled RTS flow control. Because STM current STM32 + * have broken HW based RTS behavior (they assert nRTS after every byte + * received) Enable this setting workaround this issue by using software + * based management of RTS. + * + * Convert the RTS alternate function pin to a push-pull output with + * initial output value of one, i.e., rx flow control enabled. The HCI + * UART device should not send data until we assert RTS. + */ + + regval = GPIO_MODE_MASK | GPIO_PUPD_MASK | GPIO_OPENDRAIN | GPIO_EXTI; + pinset = (config->rts_gpio & ~regval) | GPIO_OUTPUT | GPIO_OUTPUT_SET; +#endif + stm32_configgpio(pinset); + + /* Configure CR2 */ + + /* Clear STOP, CLKEN, CPOL, CPHA, LBCL, and interrupt enable bits */ + + /* HCI UART spec: 1 stop bit */ + + regval = hciuart_getreg32(config, STM32_USART_CR2_OFFSET); + regval &= ~(USART_CR2_STOP_MASK | USART_CR2_CLKEN | USART_CR2_CPOL | + USART_CR2_CPHA | USART_CR2_LBCL | USART_CR2_LBDIE); + hciuart_putreg32(config, STM32_USART_CR2_OFFSET, regval); + + /* Configure CR1 */ + + /* Clear TE, REm and all interrupt enable bits */ + + regval = hciuart_getreg32(config, STM32_USART_CR1_OFFSET); + regval &= ~(USART_CR1_TE | USART_CR1_RE | USART_CR1_ALLINTS); + + hciuart_putreg32(config, STM32_USART_CR1_OFFSET, regval); + + /* Configure CR3 */ + + /* Clear CTSE, RTSE, and all interrupt enable bits */ + + regval = hciuart_getreg32(config, STM32_USART_CR3_OFFSET); + regval &= ~(USART_CR3_CTSIE | USART_CR3_CTSE | USART_CR3_RTSE | + USART_CR3_EIE); + + hciuart_putreg32(config, STM32_USART_CR3_OFFSET, regval); + + /* Configure the USART line format and speed. Start with the configured + * initial BAUD. + */ + + DEBUGASSERT(config->state != NULL); + config->state->baud = config->baud; + hciuart_line_configure(config); + + /* Enable Rx, Tx, and the USART */ + + regval = hciuart_getreg32(config, STM32_USART_CR1_OFFSET); + regval |= (USART_CR1_UE | USART_CR1_TE | USART_CR1_RE); + hciuart_putreg32(config, STM32_USART_CR1_OFFSET, regval); + +#ifdef CONFIG_STM32_HCIUART_RXDMA + /* Acquire the DMA channel. This should always succeed. */ + + state->rxdmastream = stm32_dmachannel(config->rxdmachan); + + /* Configure for circular DMA reception into the RX fifo */ + + stm32_dmasetup(state->rxdmastream, + config->usartbase + STM32_USART_RDR_OFFSET, + (uint32_t)config->rxdmabuffer, + RXDMA_BUFFER_SIZE, + SERIAL_DMA_CONTROL_WORD); + + /* Reset our DMA shadow pointer to match the address just + * programmed above. + */ + + state->dmatail = 0; + + /* Enable receive DMA for the UART */ + + regval = hciuart_getreg32(config, STM32_USART_CR3_OFFSET); + regval |= USART_CR3_DMAR; + hciuart_putreg32(config, STM32_USART_CR3_OFFSET, regval); + + /* Start the DMA channel, and arrange for callbacks at the half and + * full points in the FIFO. This ensures that we have half a FIFO + * worth of time to claim bytes before they are overwritten. + */ + + stm32_dmastart(state->rxdmastream, hciuart_dma_rxcallback, + (void *)config, true); +#endif + + /* Disable Rx flow control, i.e, assert RTS. */ + + hciuart_rxflow_disable(config); + return OK; +} + +/**************************************************************************** + * Name: hciuart_interrupt + * + * Description: + * This is the HCIUART interrupt handler. It will be invoked when an + * interrupt is received on the 'irq'. It should call + * hciuart_copytotxfifo or hciuart_copytorxbuffer to perform the + * appropriate data transfers. The interrupt handling logic must be able + * to map the 'arg' to the appropriate hciuart_lowerhalf_s structure in + * order to call these functions. + * + ****************************************************************************/ + +static int hciuart_interrupt(int irq, void *context, void *arg) +{ + const struct hciuart_config_s *config = + (const struct hciuart_config_s *)arg; + struct hciuart_state_s *state; + uint32_t status; + uint8_t handled; + int passes; + + DEBUGASSERT(config != NULL && config->state != NULL); + state = config->state; + + /* Report serial activity to the power management logic */ + +#if defined(CONFIG_PM) && CONFIG_STM32_PM_SERIAL_ACTIVITY > 0 + pm_activity(PM_IDLE_DOMAIN, CONFIG_STM32_PM_SERIAL_ACTIVITY); +#endif + + /* Loop until there are no characters to be transferred or, + * until we have been looping for a long time. + */ + + handled = (HCIUART_RXHANDLED | HCIUART_TXHANDLED); + for (passes = 0; passes < 256 && handled != 0; passes++) + { + handled = 0; + + /* Get the masked USART status word. */ + + status = hciuart_getreg32(config, STM32_USART_SR_OFFSET); + wlinfo("status %08" PRIx32 "\n", status); + + /* USART interrupts: + * + * Enable Status Meaning Usage + * ---------------- ------------- ----------------------- ---------- + * USART_CR1_IDLEIE USART_SR_IDLE Idle Line Detected (not used) + * USART_CR1_RXNEIE USART_SR_RXNE Received Data Ready to + * be Read + * " " USART_SR_ORE Overrun Error Detected + * USART_CR1_TCIE USART_SR_TC Transmission Complete (only for + * RS-485) + * USART_CR1_TXEIE USART_SR_TXE Transmit Data Register + * Empty + * USART_CR1_PEIE USART_SR_PE Parity Error (No parity) + * + * USART_CR2_LBDIE USART_SR_LBD Break Flag (not used) + * USART_CR3_EIE USART_SR_FE Framing Error + * " " USART_SR_NE Noise Error + * " " USART_SR_ORE Overrun Error Detected + * USART_CR3_CTSIE USART_SR_CTS CTS flag (not used) + * + * NOTE: Some of these status bits must be cleared by explicitly + * writing zero to the SR register: USART_SR_CTS, USART_SR_LBD. Note + * of those are currently being used. + */ + + /* Handle incoming, receive bytes (non-DMA only) */ + + if ((status & USART_SR_RXNE) != 0 && hciuart_rxenabled(config)) + { + ssize_t nbytes; + + /* Received data ready... copy data from the Rx FIFO to the Rx + * buffer. + */ + + nbytes = hciuart_copytorxbuffer(config); + UNUSED(nbytes); + + /* Is there anything in the Rx buffer? Has the user registered an + * Rx callback function? + */ + + if (state->rxhead != state->rxtail && state->callback != NULL) + { + state->callback(&config->lower, state->arg); + handled = HCIUART_RXHANDLED; + } + } + + /* We may still have to read from the DR register to clear any pending + * error conditions. + */ + + else if ((status & (USART_SR_ORE | USART_SR_NE | USART_SR_FE)) != 0) + { +#if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) || \ + defined(CONFIG_STM32_STM32F37XX) + /* These errors are cleared by writing the corresponding bit to the + * interrupt clear register (ICR). + */ + + hciuart_putreg32(config, STM32_USART_ICR_OFFSET, + (USART_ICR_NCF | USART_ICR_ORECF | USART_ICR_FECF)); +#else + /* If an error occurs, read from DR to clear the error (data has + * been lost). If ORE is set along with RXNE then it tells you + * that the byte *after* the one in the data register has been + * lost, but the data register value is correct. That case will + * be handled above if interrupts are enabled. Otherwise, that + * good byte will be lost. + */ + + hciuart_getreg32(config, STM32_USART_RDR_OFFSET); +#endif + } + + /* Handle outgoing, transmit bytes + * + * TXE: Transmit data register empty + * This bit is set by hardware when the content of the TDR register + * has been transferred into the shift register. + */ + + if ((status & USART_SR_TXE) != 0 && + hciuart_isenabled(config, USART_CR1_TXEIE)) + { + ssize_t nbytes; + uint8_t txhandled; + + /* Transmit data register empty ... copy data from the Tx buffer + * to the Tx FIFO. + */ + + nbytes = hciuart_copytotxfifo(config); + UNUSED(nbytes); + + /* If the Tx buffer is now empty, then disable further Tx + * interrupts. Tx interrupts will only be enabled in the + * following circumstances: + * + * 1. The user is waiting in hciuart_write() for space to become + * available in the Tx FIFO. + * 2. The full, outgoing message has been placed into the Tx + * buffer by hciuart_write(). + * + * In either case, no more Tx interrupts will be needed until more + * data is added to the Tx buffer. + */ + + txhandled = HCIUART_TXHANDLED; + if (state->txhead == state->txtail) + { + /* Disable Tx interrupts and treat the event as unhandled in + * order to terminate looping. + */ + + hciuart_disableints(config, USART_CR1_TXEIE); + txhandled = 0; + } + + /* This copy will free up space in the Tx FIFO. Wake up any + * threads that may have been waiting for space in the Tx + * buffer. + */ + + if (state->txwaiting) + { + state->txwaiting = false; + nxsem_post(&state->txwait); + } + + handled |= txhandled; + } + } + + return OK; +} + +/**************************************************************************** + * Name: hciuart_rxattach + * + * Description: + * Attach/detach the upper half Rx callback. + * + * rxattach() allows the upper half logic to attach a callback function + * that will be used to inform the upper half that an Rx frame is + * available. This callback will, most likely, be invoked in the + * context of an interrupt callback. The receive() method should then + * be invoked in order to receive the obtain the Rx frame data. + * + ****************************************************************************/ + +static void hciuart_rxattach(const struct btuart_lowerhalf_s *lower, + btuart_rxcallback_t callback, void *arg) +{ + const struct hciuart_config_s *config = + (const struct hciuart_config_s *)lower; + struct hciuart_state_s *state; + irqstate_t flags; + + wlinfo("config %p callback %p arg %p\n", config, callback, arg); + + DEBUGASSERT(config != NULL && config->state != NULL); + state = config->state; + + /* If the callback is NULL, then we are detaching */ + + flags = spin_lock_irqsave(&config->lock); + if (callback == NULL) + { + uint32_t intset; + + /* Disable Rx callbacks and detach the Rx callback */ + + intset = USART_CR1_RXNEIE | USART_CR3_EIE; + hciuart_disableints(config, intset); + + state->callback = NULL; + state->arg = NULL; + } + + /* Otherwise, we are attaching */ + + else + { + state->callback = NULL; + state->arg = arg; + state->callback = callback; + } + + spin_unlock_irqrestore(&config->lock, flags); +} + +/**************************************************************************** + * Name: hciuart_rxenable + * + * Description: + * Enable/disable RX callbacks from the HCI UART. + * + * hciuart_rxenable() may be used to enable or disable callback events. + * This probably translates to enabling and disabled Rx interrupts at + * the UART. NOTE: Rx event notification should be done sparingly: + * Rx data overrun may occur when Rx events are disabled! + * + ****************************************************************************/ + +static void hciuart_rxenable(const struct btuart_lowerhalf_s *lower, + bool enable) +{ + const struct hciuart_config_s *config = + (const struct hciuart_config_s *)lower; + + DEBUGASSERT(config != NULL && config->state != NULL); + +#ifdef CONFIG_STM32_HCIUART_RXDMA + struct hciuart_state_s *state = config->state; + + if (config->rxdmabuffer != NULL) + { + wlinfo("config %p enable %u (DMA)\n", config, enable); + + /* En/disable DMA reception. + * + * Note that it is not safe to check for available bytes and + * immediately pass them to uart_recvchars as that could potentially + * recurse back to us again. Instead, bytes must wait until the next + * up_dma_poll or DMA event. + */ + + state->rxenable = enable; + } + else +#else + { + uint32_t intset; + irqstate_t flags; + + wlinfo("config %p enable %u (non-DMA)\n", config, enable); + + /* USART receive interrupts: + * + * Enable Status Meaning Usage + * ---------------- ------------- ----------------------- ---------- + * USART_CR1_IDLEIE USART_SR_IDLE Idle Line Detected (not used) + * USART_CR1_RXNEIE USART_SR_RXNE Received Data Ready to + * be Read + * " " USART_SR_ORE Overrun Error Detected + * USART_CR1_PEIE USART_SR_PE Parity Error (No parity) + * + * USART_CR2_LBDIE USART_SR_LBD Break Flag (not used) + * USART_CR3_EIE USART_SR_FE Framing Error + * " " USART_SR_NE Noise Error + * " " USART_SR_ORE Overrun Error Detected + */ + + flags = spin_lock_irqsave(&config->lock); + if (enable) + { + /* Receive an interrupt when their is anything in the Rx data + * register (or an Rx timeout occurs). + */ + + intset = USART_CR1_RXNEIE | USART_CR3_EIE; + hciuart_enableints(config, intset); + } + else + { + intset = USART_CR1_RXNEIE | USART_CR3_EIE; + hciuart_disableints(config, intset); + } + + spin_unlock_irqrestore(&config->lock, flags); + } +#endif +} + +/**************************************************************************** + * Name: hciuart_setbaud + * + * Description: + * The HCI UART comes up with some initial BAUD rate. Some support + * auto-BAUD detection, some support writing a configuration file to + * select the initial BAUD. The simplest strategy, however, is simply + * to use the HCI UART's default initial BAUD to perform the basic + * bring up, then send a vendor-specific command to increase the HCI + * UARTs BAUD. This method then may be used to adjust the lower half + * driver to the new HCI UART BAUD. + * + ****************************************************************************/ + +static int hciuart_setbaud(const struct btuart_lowerhalf_s *lower, + uint32_t baud) +{ + const struct hciuart_config_s *config = + (const struct hciuart_config_s *)lower; + + DEBUGASSERT(config != NULL && config->state != NULL); + + config->state->baud = baud; + hciuart_line_configure(config); + return OK; +} + +/**************************************************************************** + * Name: hciuart_read + * + * Description: + * Read UART data. + * + * hciuart_read() after receipt of a callback notifying the upper half of + * the availability of Rx frame, the upper half may call the receive() + * method in order to obtain the buffered Rx frame data. + * + ****************************************************************************/ + +static ssize_t hciuart_read(const struct btuart_lowerhalf_s *lower, + void *buffer, size_t buflen) +{ + const struct hciuart_config_s *config = + (const struct hciuart_config_s *)lower; + struct hciuart_state_s *state; + uint8_t *dest; + size_t remaining; + ssize_t ntotal; + ssize_t nbytes; + bool rxenable; + int ret; + + wlinfo("config %p buffer %p buflen %lu\n", + config, buffer, (unsigned long)buflen); + + /* NOTE: This assumes that the caller has exclusive access to the Rx + * buffer, i.e., one lower half instance can server only one upper half! + */ + + DEBUGASSERT(config != NULL && config->state != NULL); + state = config->state; + + /* Read any pending data to the Rx buffer */ + + nbytes = hciuart_copytorxbuffer(config); + UNUSED(nbytes); + + /* Loop copying data to the user buffer while the Rx buffer is not empty + * and the callers buffer is not full. + */ + + dest = (uint8_t *)buffer; + remaining = buflen; + ntotal = 0; + + rxenable = hciuart_rxenabled(config); + hciuart_rxenable(lower, false); + + while (state->rxtail != state->rxhead && ntotal < buflen) + { + nbytes = hciuart_copyfromrxbuffer(config, dest, remaining); + if (nbytes <= 0) + { + DEBUGASSERT(nbytes == 0); + + /* If no data has been received, then we must wait for the arrival + * of new Rx data and try again. + */ + + if (ntotal == 0) + { + DEBUGASSERT(!state->rxwaiting); + state->rxwaiting = true; + do + { + ret = nxsem_wait_uninterruptible(&state->rxwait); + if (ret < 0) + { + ntotal = (ssize_t)ret; + break; + } + } + while (state->rxwaiting); + } + + /* Otherwise, this must be the end of the packet. Just break out + * and return what we have. + */ + + else + { + break; + } + } + else + { + /* More data has been copied. Update pointers, counts, and + * indices. + */ + + ntotal += nbytes; + dest += nbytes; + remaining -= nbytes; + + /* Read any additional pending data into the Rx buffer that may + * have accumulated while we were copying. + */ + + nbytes = hciuart_copytorxbuffer(config); + if (nbytes < 0) + { + /* An error occurred.. this should not really happen */ + + return nbytes; + } + + /* Otherwise, continue looping */ + } + } + + hciuart_rxenable(lower, rxenable); + return ntotal; +} + +/**************************************************************************** + * Name: hciuart_write + * + * Description: + * Write UART data. + * + * hciuart_write() will add the outgoing frame to the Tx buffer and will + * return immediately. This function may block only in the event that + * there is insufficient buffer space to hold the Tx frame data. In that + * case the lower half will block until there is sufficient to buffer + * the entire outgoing packet. + * + ****************************************************************************/ + +static ssize_t hciuart_write(const struct btuart_lowerhalf_s *lower, + const void *buffer, size_t buflen) +{ + const struct hciuart_config_s *config = + (const struct hciuart_config_s *)lower; + struct hciuart_state_s *state; + const uint8_t *src; + ssize_t nbytes = 0; + uint16_t txhead; + uint16_t txtail; + uint16_t txnext; + ssize_t ntotal; + irqstate_t flags; + int ret; + + wlinfo("config %p buffer %p buflen %lu\n", + config, buffer, (unsigned long)buflen); + + DEBUGASSERT(config != NULL && config->state != NULL); + state = config->state; + + /* NOTE: This assumes that the caller has exclusive access to the Tx + * buffer, i.e., one lower half instance can server only one upper half! + */ + + /* Make sure that the Tx Interrupts are disabled. + * USART transmit interrupts: + * + * Enable Status Meaning Usage + * ---------------- ------------- ---------------------- ---------- + * USART_CR1_TCIE USART_SR_TC Transmission Complete (only for RS-485) + * USART_CR1_TXEIE USART_SR_TXE Transmit Data Register + * Empty + * USART_CR3_CTSIE USART_SR_CTS CTS flag (not used) + */ + + flags = spin_lock_irqsave(&config->lock); + hciuart_disableints(config, USART_CR1_TXEIE); + spin_unlock_irqrestore(&config->lock, flags); + + /* Loop until all of the user data have been moved to the Tx buffer */ + + src = buffer; + ntotal = 0; + + while (ntotal < (ssize_t)buflen) + { + /* Copy bytes to the tail of the Tx buffer */ + + /* Get a copy of the rxhead and rxtail indices of the Tx buffer */ + + txhead = state->txhead; + txtail = state->txtail; + + txnext = txtail + 1; + if (txnext >= config->txbufsize) + { + txnext = 0; + } + + /* Is there space available in the Tx buffer? Do have more bytes to + * copy? + */ + + while (txhead != txnext && ntotal < (ssize_t)buflen) + { + /* Yes.. copy one byte to the Tx buffer */ + + config->txbuffer[txtail] = *src++; + + txtail = txnext; + if (++txnext >= config->txbufsize) + { + txnext = 0; + } + + ntotal++; + } + + /* Save the updated Tx buffer tail index */ + + state->txtail = txtail; + + /* Copy bytes from the Tx buffer to the Tx FIFO */ + + nbytes = hciuart_copytotxfifo(config); + + /* If nothing could be copied to the Tx FIFO and we still have user + * data that we have not added to the Tx buffer, then we must wait for + * space in the Tx* buffer then try again. + */ + + if (nbytes <= 0 && ntotal < (ssize_t)buflen) + { + DEBUGASSERT(nbytes == 0); + + /* Enable the Tx interrupt and wait for space open up in the Tx + * buffer. + */ + + flags = enter_critical_section(); + hciuart_enableints(config, USART_CR1_TXEIE); + + DEBUGASSERT(!state->txwaiting); + state->txwaiting = true; + do + { + ret = nxsem_wait_uninterruptible(&state->txwait); + if (ret < 0) + { + if (ntotal == 0) + { + ntotal = (ssize_t)ret; + } + + break; + } + } + while (state->txwaiting); + + /* Disable Tx interrupts again */ + + hciuart_disableints(config, USART_CR1_TXEIE); + leave_critical_section(flags); + } + } + + /* If Tx buffer is not empty, then exit with Tx interrupts enabled. */ + + if (state->txhead != state->txtail) + { + flags = spin_lock_irqsave(&config->lock); + hciuart_enableints(config, USART_CR1_TXEIE); + spin_unlock_irqrestore(&config->lock, flags); + } + + return ntotal; +} + +/**************************************************************************** + * Name: hciuart_rxdrain + * + * Description: + * Flush/drain all buffered RX data + * + ****************************************************************************/ + +static ssize_t hciuart_rxdrain(const struct btuart_lowerhalf_s *lower) +{ + const struct hciuart_config_s *config = + (const struct hciuart_config_s *)lower; + struct hciuart_state_s *state; + size_t ntotal; + ssize_t nbytes; + bool rxenable; + + wlinfo("config %p\n", config); + + DEBUGASSERT(config != NULL && config->state != NULL); + state = config->state; + + /* Read any pending data to the Rx buffer */ + + nbytes = hciuart_copytorxbuffer(config); + UNUSED(nbytes); + + /* Loop discarding in the Rx buffer until the Rx buffer is empty */ + + ntotal = 0; + + rxenable = hciuart_rxenabled(config); + hciuart_rxenable(lower, false); + + while (state->rxtail != state->rxhead) + { + /* Keep track of how much is discarded */ + + ntotal += hciuart_rxinuse(config); + + /* Discard the data in the Rx buffer */ + + state->rxhead = 0; + state->rxtail = 0; + + /* Read any additional pending data into the Rx buffer that may + * have accumulated while we were discarding. + */ + + nbytes = hciuart_copytorxbuffer(config); + UNUSED(nbytes); + } + + hciuart_rxenable(lower, rxenable); + return ntotal; +} + +/**************************************************************************** + * Name: hciuart_dma_rxcallback + * + * Description: + * This function checks the current DMA state and calls the generic + * serial stack when bytes appear to be available. + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_HCIUART_RXDMA +static void hciuart_dma_rxcallback(DMA_HANDLE handle, uint8_t status, + void *arg) +{ + const struct hciuart_config_s *config = + (const struct hciuart_config_s *)arg; + struct hciuart_state_s *state; + irqstate_t flags; + ssize_t nbytes; + + flags = spin_lock_irqsave_nopreempt(&config->lock); + + if (config.state->rxdmastream == NULL) + { + spin_unlock_irqrestore_nopreempt(&config->lock, flags); + return; + } + + wlinfo("status %u config %p\n", status, config); + + DEBUGASSERT(config != NULL && config->state != NULL); + state = config->state; + + /* Received data ready... copy and data from the Rx DMA buffer to the Rx + * buffer. + */ + + nbytes = hciuart_copytorxbuffer(config); + UNUSED(nbytes); + + /* Is there anything in the Rx buffer? Has the user registered an Rx + * callback function? + */ + + if (state->rxhead != state->rxtail && state->callback != NULL) + { + state->callback(config->lower, state->arg); + handled = true; + } + + spin_unlock_irqrestore_nopreempt(&config->lock, flags); +} +#endif + +/**************************************************************************** + * Name: hciuart_pm_notify + * + * Description: + * Notify the driver of new power state. This callback is called after + * all drivers have had the opportunity to prepare for the new power state. + * + * Input Parameters: + * + * cb - Returned to the driver. The driver version of the callback + * structure may include additional, driver-specific state data at + * the end of the structure. + * + * pmstate - Identifies the new PM state + * + * Returned Value: + * None - The driver already agreed to transition to the low power + * consumption state when when it returned OK to the prepare() call. + * + * + ****************************************************************************/ + +#ifdef CONFIG_PM +static void hciuart_pm_notify(struct pm_callback_s *cb, int domain, + enum pm_state_e pmstate) +{ + switch (pmstate) + { + case (PM_NORMAL): + { + /* Logic for PM_NORMAL goes here */ + } + break; + + case (PM_IDLE): + { + /* Logic for PM_IDLE goes here */ + } + break; + + case (PM_STANDBY): + { + /* Logic for PM_STANDBY goes here */ + } + break; + + case (PM_SLEEP): + { + /* Logic for PM_SLEEP goes here */ + } + break; + + default: + + /* Should not get here */ + + break; + } +} +#endif + +/**************************************************************************** + * Name: hciuart_pm_prepare + * + * Description: + * Request the driver to prepare for a new power state. This is a warning + * that the system is about to enter into a new power state. The driver + * should begin whatever operations that may be required to enter power + * state. The driver may abort the state change mode by returning a + * non-zero value from the callback function. + * + * Input Parameters: + * + * cb - Returned to the driver. The driver version of the callback + * structure may include additional, driver-specific state data at + * the end of the structure. + * + * pmstate - Identifies the new PM state + * + * Returned Value: + * Zero - (OK) means the event was successfully processed and that the + * driver is prepared for the PM state change. + * + * Non-zero - means that the driver is not prepared to perform the tasks + * needed achieve this power setting and will cause the state + * change to be aborted. NOTE: The prepare() method will also + * be called when reverting from lower back to higher power + * consumption modes (say because another driver refused a + * lower power state change). Drivers are not permitted to + * return non-zero values when reverting back to higher power + * consumption modes! + * + * + ****************************************************************************/ + +#ifdef CONFIG_PM +static int hciuart_pm_prepare(struct pm_callback_s *cb, int domain, + enum pm_state_e pmstate) +{ + /* Logic to prepare for a reduced power state goes here. */ + + return OK; +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: hciuart_instantiate + * + * Description: + * Obtain an instance of the HCI UART interface for the specified HCI UART + * This assumes that hciuart_initialize was called previously. + * + * Input Parameters: + * uart - Identifies the HCI UART to be configured + * + * Returned Value: + * On success, a reference to the HCI UART lower driver for the associated + * U[S]ART + * + ****************************************************************************/ + +const struct btuart_lowerhalf_s * + hciuart_instantiate(enum hciuart_devno_e uart) +{ + const struct hciuart_config_s *config; +#ifdef CONFIG_PM + int ret; +#endif + + wlinfo("Instantiating HCIUART%d\n", (int)uart + 1); + DEBUGASSERT((int)uart >= 0 && (int)uart < 8); + + /* Check if this uart is available in the configuration */ + + config = g_hciuarts[(int)uart]; + if (config == NULL) + { + wlerr("ERROR: UART%d not configured\n", uart + 1); + return NULL; + } + + /* Register to receive power management callbacks */ + +#ifdef CONFIG_PM + ret = pm_register(&g_serialcb); + DEBUGASSERT(ret == OK); + UNUSED(ret); +#endif + + /* Configure and enable the UART */ + + hciuart_configure(config); + return &config->lower; +} + +/**************************************************************************** + * Name: hciuart_initialize + * + * Description: + * Performs the low-level, one-time USART initialization. This must be + * called before hciuart_instantiate. + * + ****************************************************************************/ + +void hciuart_initialize(void) +{ + const struct hciuart_config_s *config; + struct hciuart_state_s *state; + int ret; + int i; + + /* Configure all USARTs */ + + for (i = 0; i < STM32_NUSART; i++) + { + config = g_hciuarts[i]; + if (config != NULL) + { + state = config->state; + + wlinfo("Initializing HCIUART%d\n", i + 1); + + /* Disable U[S]ART interrupts */ + + hciuart_disableints(config, HCIUART_ALLINTS); + + /* Attach and enable the HCI UART IRQ */ + + ret = irq_attach(config->irq, hciuart_interrupt, (void *)config); + if (ret == OK) + { + /* Enable the interrupt (RX and TX interrupts are still + * disabled in the USART) + */ + + up_enable_irq(config->irq); + } + } + } +} + +/**************************************************************************** + * Name: stm32_serial_dma_poll + * + * Description: + * Checks receive DMA buffers for received bytes that have not accumulated + * to the point where the DMA half/full interrupt has triggered. + * + * This function should be called from a timer or other periodic context. + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_HCIUART_RXDMA +void stm32_serial_dma_poll(void) +{ +#ifdef CONFIG_STM32_HCIUART1_RXDMA + hciuart_dma_rxcallback(g_hciusart1_config.state->rxdmastream, 0, + &g_hciusart1_config); +#endif + +#ifdef CONFIG_STM32_HCIUART2_RXDMA + hciuart_dma_rxcallback(g_hciusart2_config.state->rxdmastream, 0, + &g_hciusart2_config); +#endif + +#ifdef CONFIG_STM32_HCIUART3_RXDMA + hciuart_dma_rxcallback(g_hciusart3_config.state->rxdmastream, 0, + &g_hciusart3_config); +#endif + +#ifdef CONFIG_STM32_HCIUART6_RXDMA + hciuart_dma_rxcallback(g_hciusart6_config.state->rxdmastream, 0, + &g_hciusart6_config); +#endif + +#ifdef CONFIG_STM32_HCIUART7_RXDMA + hciuart_dma_rxcallback(g_hciuart7_config.state->rxdmastream, + 0, + &g_hciuart7_config); +#endif + +#ifdef CONFIG_STM32_HCIUART8_RXDMA + hciuart_dma_rxcallback(g_hciuart8.state->rxdmastream, 0, + &g_hciuart8_config); +#endif +} +#endif diff --git a/arch/arm/src/common/stm32/stm32_hrtim.h b/arch/arm/src/common/stm32/stm32_hrtim.h new file mode 100644 index 0000000000000..0be3fcfe2f701 --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_hrtim.h @@ -0,0 +1,38 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_hrtim.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_COMPAT_STM32HRTIM_H +#define __ARCH_ARM_SRC_COMMON_COMPAT_STM32HRTIM_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#if defined(CONFIG_STM32_HAVE_IP_HRTIM_M3M4_V1) +# include "stm32_hrtim_m3m4_v1.h" +#else +# error "Unsupported STM32 stm32_hrtim" +#endif + +#endif /* __ARCH_ARM_SRC_COMMON_COMPAT_STM32HRTIM_H */ diff --git a/arch/arm/src/common/stm32/stm32_hrtim_m3m4_v1.c b/arch/arm/src/common/stm32/stm32_hrtim_m3m4_v1.c new file mode 100644 index 0000000000000..73791c4c21fc8 --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_hrtim_m3m4_v1.c @@ -0,0 +1,6045 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_hrtim_m3m4_v1.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include + +#include + +#include "chip.h" +#include "stm32.h" +#include "stm32_gpio.h" +#include "stm32_hrtim_m3m4_v1.h" +#include "stm32_gpio.h" +#include "stm32_hrtim_m3m4_v1.h" + +#if defined(CONFIG_STM32_HRTIM1) + +/* Only STM32F33XXX and STM32G47XXX */ + +#if defined(CONFIG_STM32_STM32F33XX) || defined(CONFIG_STM32_STM32G47XX) + +#if defined(CONFIG_STM32_HRTIM_TIMA_PWM) || defined(CONFIG_STM32_HRTIM_TIMA_DAC) || \ + defined(CONFIG_STM32_HRTIM_TIMA_CAP) || defined(CONFIG_STM32_HRTIM_TIMA_IRQ) || \ + defined(CONFIG_STM32_HRTIM_TIMA_DT) || defined(CONFIG_STM32_HRTIM_TIMA_CHOP) +# ifndef CONFIG_STM32_HRTIM_TIMA +# error "CONFIG_STM32_HRTIM_TIMA must be set" +# endif +#endif +#if defined(CONFIG_STM32_HRTIM_TIMB_PWM) || defined(CONFIG_STM32_HRTIM_TIMB_DAC) || \ + defined(CONFIG_STM32_HRTIM_TIMB_CAP) || defined(CONFIG_STM32_HRTIM_TIMB_IRQ) || \ + defined(CONFIG_STM32_HRTIM_TIMB_DT) || defined(CONFIG_STM32_HRTIM_TIMB_CHOP) +# ifndef CONFIG_STM32_HRTIM_TIMB +# error "CONFIG_STM32_HRTIM_TIMB must be set" +# endif +#endif +#if defined(CONFIG_STM32_HRTIM_TIMC_PWM) || defined(CONFIG_STM32_HRTIM_TIMC_DAC) || \ + defined(CONFIG_STM32_HRTIM_TIMC_CAP) || defined(CONFIG_STM32_HRTIM_TIMC_IRQ) || \ + defined(CONFIG_STM32_HRTIM_TIMC_DT) || defined(CONFIG_STM32_HRTIM_TIMC_CHOP) +# ifndef CONFIG_STM32_HRTIM_TIMC +# error "CONFIG_STM32_HRTIM_TIMC must be set" +# endif +#endif +#if defined(CONFIG_STM32_HRTIM_TIMD_PWM) || defined(CONFIG_STM32_HRTIM_TIMD_DAC) || \ + defined(CONFIG_STM32_HRTIM_TIMD_CAP) || defined(CONFIG_STM32_HRTIM_TIMD_IRQ) || \ + defined(CONFIG_STM32_HRTIM_TIMD_DT) || defined(CONFIG_STM32_HRTIM_TIMD_CHOP) +# ifndef CONFIG_STM32_HRTIM_TIMD +# error "CONFIG_STM32_HRTIM_TIMD must be set" +# endif +#endif +#if defined(CONFIG_STM32_HRTIM_TIME_PWM) || defined(CONFIG_STM32_HRTIM_TIME_DAC) || \ + defined(CONFIG_STM32_HRTIM_TIME_CAP) || defined(CONFIG_STM32_HRTIM_TIME_IRQ) || \ + defined(CONFIG_STM32_HRTIM_TIME_DT) || defined(CONFIG_STM32_HRTIM_TIME_CHOP) +# ifndef CONFIG_STM32_HRTIM_TIME +# error "CONFIG_STM32_HRTIM_TIME must be set" +# endif +#endif + +#if defined(CONFIG_STM32_HRTIM_PWM) +#if !defined(CONFIG_STM32_HRTIM_TIMA_PWM) && !defined(CONFIG_STM32_HRTIM_TIMB_PWM) && \ + !defined(CONFIG_STM32_HRTIM_TIMC_PWM) && !defined(CONFIG_STM32_HRTIM_TIMD_PWM) && \ + !defined(CONFIG_STM32_HRTIM_TIME_PWM) +# warning "CONFIG_STM32_HRTIM_PWM enabled but no timer selected" +# endif +#endif +#if defined(CONFIG_STM32_HRTIM_DAC) +#if !defined(CONFIG_STM32_HRTIM_MASTER_DAC) && !defined(CONFIG_STM32_HRTIM_TIMA_DAC) && \ + !defined(CONFIG_STM32_HRTIM_TIMB_DAC) && !defined(CONFIG_STM32_HRTIM_TIMC_DAC) && \ + !defined(CONFIG_STM32_HRTIM_TIMD_DAC) && !defined(CONFIG_STM32_HRTIM_TIME_DAC) +# warning "CONFIG_STM32_HRTIM_DAC enabled but no timer selected" +# endif +#endif +#if defined(CONFIG_STM32_HRTIM_CAPTURE) +#if !defined(CONFIG_STM32_HRTIM_TIMA_CAP) && !defined(CONFIG_STM32_HRTIM_TIMB_CAP) && \ + !defined(CONFIG_STM32_HRTIM_TIMC_CAP) && !defined(CONFIG_STM32_HRTIM_TIMD_CAP) && \ + !defined(CONFIG_STM32_HRTIM_TIME_CAP) +# warning "CONFIG_STM32_HRTIM_CAPTURE enabled but no timer selected" +# endif +#endif +#if defined(CONFIG_STM32_HRTIM_INTERRUPTS) +#if !defined(CONFIG_STM32_HRTIM_MASTER_IRQ) && !defined(CONFIG_STM32_HRTIM_TIMA_IRQ) && \ + !defined(CONFIG_STM32_HRTIM_TIMB_IRQ) && !defined(CONFIG_STM32_HRTIM_TIMC_IRQ) && \ + !defined(CONFIG_STM32_HRTIM_TIMD_IRQ) && !defined(CONFIG_STM32_HRTIM_TIME_IRQ) && \ + !defined(CONFIG_STM32_HRTIM_COMMON_IRQ) +# warning "CONFIG_STM32_HRTIM_INTERRUPTS enabled but no timer selected" +# endif +#endif +#if defined(CONFIG_STM32_HRTIM_DEADTIME) +#if !defined(CONFIG_STM32_HRTIM_TIMA_DT) && !defined(CONFIG_STM32_HRTIM_TIMB_DT) && \ + !defined(CONFIG_STM32_HRTIM_TIMC_DT) && !defined(CONFIG_STM32_HRTIM_TIMD_DT) && \ + !defined(CONFIG_STM32_HRTIM_TIME_DT) +# warning "CONFIG_STM32_HRTIM_DEADTIME enabled but no timer selected" +# endif +#endif +#if defined(CONFIG_STM32_HRTIM_CHOPPER) +#if !defined(CONFIG_STM32_HRTIM_TIMA_CHOP) && !defined(CONFIG_STM32_HRTIM_TIMB_CHOP) && \ + !defined(CONFIG_STM32_HRTIM_TIMC_CHOP) && !defined(CONFIG_STM32_HRTIM_TIMD_CHOP) && \ + !defined(CONFIG_STM32_HRTIM_TIME_CHOP) +# warning "CONFIG_STM32_HRTIM_CHOPPER enabled but no timer selected" +# endif +#endif + +#if defined(CONFIG_STM32_HRTIM_TIMA_PWM) || defined(CONFIG_STM32_HRTIM_TIMB_PWM) || \ + defined(CONFIG_STM32_HRTIM_TIMC_PWM) || defined(CONFIG_STM32_HRTIM_TIMD_PWM) || \ + defined(CONFIG_STM32_HRTIM_TIME_PWM) +# ifndef CONFIG_STM32_HRTIM_PWM +# error "CONFIG_STM32_HRTIM_PWM must be set" +# endif +#endif +#if defined(CONFIG_STM32_HRTIM_MASTER_DAC) || defined(CONFIG_STM32_HRTIM_TIMA_DAC) || \ + defined(CONFIG_STM32_HRTIM_TIMB_DAC) || defined(CONFIG_STM32_HRTIM_TIMC_DAC) || \ + defined(CONFIG_STM32_HRTIM_TIMD_DAC) || defined(CONFIG_STM32_HRTIM_TIME_DAC) +# ifndef CONFIG_STM32_HRTIM_DAC +# error "CONFIG_STM32_HRTIM_DAC must be set" +# endif +#endif +#if defined(CONFIG_STM32_HRTIM_TIMA_CAP) || defined(CONFIG_STM32_HRTIM_TIMB_CAP) || \ + defined(CONFIG_STM32_HRTIM_TIMC_CAP) || defined(CONFIG_STM32_HRTIM_TIMD_CAP) || \ + defined(CONFIG_STM32_HRTIM_TIME_CAP) +# ifndef CONFIG_STM32_HRTIM_CAPTURE +# error "CONFIG_STM32_HRTIM_CAPTURE must be set" +# endif +#endif +#if defined(CONFIG_STM32_HRTIM_TIMA_IRQ) || defined(CONFIG_STM32_HRTIM_TIMB_IRQ) || \ + defined(CONFIG_STM32_HRTIM_TIMC_IRQ) || defined(CONFIG_STM32_HRTIM_TIMD_IRQ) || \ + defined(CONFIG_STM32_HRTIM_TIME_IRQ) +# ifndef CONFIG_STM32_HRTIM_INTERRUPTS +# error "CONFIG_STM32_HRTIM_INTERRUPTS must be set" +# endif +#endif +#if defined(CONFIG_STM32_HRTIM_TIMA_DT) || defined(CONFIG_STM32_HRTIM_TIMB_DT) || \ + defined(CONFIG_STM32_HRTIM_TIMC_DT) || defined(CONFIG_STM32_HRTIM_TIMD_DT) || \ + defined(CONFIG_STM32_HRTIM_TIME_DT) +# ifndef CONFIG_STM32_HRTIM_DEADTIME +# error "CONFIG_STM32_HRTIM_DEADTIME must be set" +# endif +#endif +#if defined(CONFIG_STM32_HRTIM_TIMA_CHOP) || defined(CONFIG_STM32_HRTIM_TIMB_CHOP) || \ + defined(CONFIG_STM32_HRTIM_TIMC_CHOP) || defined(CONFIG_STM32_HRTIM_TIMD_CHOP) || \ + defined(CONFIG_STM32_HRTIM_TIME_CHOP) +# ifndef CONFIG_STM32_HRTIM_CHOPPER +# error "CONFIG_STM32_HRTIM_CHOPPER must be set" +# endif +#endif +#if defined(CONFIG_STM32_HRTIM_TIMA_PSHPLL) || defined(CONFIG_STM32_HRTIM_TIMB_PSHPLL) || \ + defined(CONFIG_STM32_HRTIM_TIMC_PSHPLL) || defined(CONFIG_STM32_HRTIM_TIMD_PSHPLL) || \ + defined(CONFIG_STM32_HRTIM_TIME_PSHPLL) +# ifndef CONFIG_STM32_HRTIM_PUSHPULL +# error "CONFIG_STM32_HRTIM_PUSHPULL must be set" +# endif +#endif + +#if defined(CONFIG_STM32_HRTIM_TIMA_DT) && defined(CONFIG_STM32_HRTIM_TIMA_PSHPLL) +# error "The deadtime cannot be used simultaneously with the push-pull mode" +#endif +#if defined(CONFIG_STM32_HRTIM_TIMB_DT) && defined(CONFIG_STM32_HRTIM_TIMB_PSHPLL) +# error "The deadtime cannot be used simultaneously with the push-pull mode" +#endif +#if defined(CONFIG_STM32_HRTIM_TIMC_DT) && defined(CONFIG_STM32_HRTIM_TIMC_PSHPLL) +# error "The deadtime cannot be used simultaneously with the push-pull mode" +#endif +#if defined(CONFIG_STM32_HRTIM_TIMD_DT) && defined(CONFIG_STM32_HRTIM_TIMD_PSHPLL) +# error "The deadtime cannot be used simultaneously with the push-pull mode" +#endif +#if defined(CONFIG_STM32_HRTIM_TIME_DT) && defined(CONFIG_STM32_HRTIM_TIME_PSHPLL) +# error "The deadtime cannot be used simultaneously with the push-pull mode" +#endif + +#if defined(CONFIG_STM32_HRTIM_ADC1_TRG1) || defined(CONFIG_STM32_HRTIM_ADC1_TRG2) || \ + defined(CONFIG_STM32_HRTIM_ADC1_TRG3) || defined(CONFIG_STM32_HRTIM_ADC1_TRG4) || \ + defined(CONFIG_STM32_HRTIM_ADC2_TRG1) || defined(CONFIG_STM32_HRTIM_ADC2_TRG2) || \ + defined(CONFIG_STM32_HRTIM_ADC2_TRG3) || defined(CONFIG_STM32_HRTIM_ADC2_TRG4) +# define HRTIM_HAVE_ADC +#endif + +#if defined(CONFIG_STM32_HRTIM_ADC1_TRG1) || defined(CONFIG_STM32_HRTIM_ADC2_TRG1) +# define HRTIM_HAVE_ADC_TRG1 +#endif +#if defined(CONFIG_STM32_HRTIM_ADC1_TRG2) || defined(CONFIG_STM32_HRTIM_ADC2_TRG2) +# define HRTIM_HAVE_ADC_TRG2 +#endif +#if defined(CONFIG_STM32_HRTIM_ADC1_TRG3) || defined(CONFIG_STM32_HRTIM_ADC2_TRG3) +# define HRTIM_HAVE_ADC_TRG3 +#endif +#if defined(CONFIG_STM32_HRTIM_ADC1_TRG4) || defined(CONFIG_STM32_HRTIM_ADC2_TRG4) +# define HRTIM_HAVE_ADC_TRG4 +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* HRTIM default configuration **********************************************/ + +#if defined(CONFIG_STM32_HRTIM_MASTER) && !defined(HRTIM_MASTER_MODE) +# warning "HRTIM_MASTER_MODE is not set. Set the default value 0" +# define HRTIM_MASTER_MODE 0 +#endif +#if defined(CONFIG_STM32_HRTIM_TIMA) && !defined( HRTIM_TIMA_MODE) +# warning "HRTIM_TIMA_MODE is not set. Set the default value 0" +# define HRTIM_TIMA_MODE 0 +#endif +#if defined(CONFIG_STM32_HRTIM_TIMB) && !defined(HRTIM_TIMB_MODE) +# warning "HRTIM_TIMB_MODE is not set. Set the default value 0" +# define HRTIM_TIMB_MODE 0 +#endif +#if defined(CONFIG_STM32_HRTIM_TIMC) && !defined(HRTIM_TIMC_MODE) +# warning "HRTIM_TIMC_MODE is not set. Set the default value 0" +# define HRTIM_TIMC_MODE 0 +#endif +#if defined(CONFIG_STM32_HRTIM_TIMD) && !defined(HRTIM_TIMD_MODE) +# warning "HRTIM_TIMD_MODE is not set. Set the default value 0" +# define HRTIM_TIMD_MODE 0 +#endif +#if defined(CONFIG_STM32_HRTIM_TIME) && !defined(HRTIM_TIME_MODE) +# warning "HRTIM_TIME_MODE is not set. Set the default value 0" +# define HRTIM_TIME_MODE 0 +#endif + +#if defined(CONFIG_STM32_HRTIM_TIMA) && !defined(HRTIM_TIMA_UPDATE) +# warning "HRTIM_TIMA_UPDATE is not set. Set the default value 0" +# define HRTIM_TIMA_UPDATE 0 +#endif +#if defined(CONFIG_STM32_HRTIM_TIMB) && !defined(HRTIM_TIMB_UPDATE) +# warning "HRTIM_TIMB_UPDATE is not set. Set the default value 0" +# define HRTIM_TIMB_UPDATE 0 +#endif +#if defined(CONFIG_STM32_HRTIM_TIMC) && !defined(HRTIM_TIMC_UPDATE) +# warning "HRTIM_TIMC_UPDATE is not set. Set the default value 0" +# define HRTIM_TIMC_UPDATE 0 +#endif +#if defined(CONFIG_STM32_HRTIM_TIMD) && !defined(HRTIM_TIMD_UPDATE) +# warning "HRTIM_TIMD_UPDATE is not set. Set the default value 0" +# define HRTIM_TIMD_UPDATE 0 +#endif +#if defined(CONFIG_STM32_HRTIM_TIME) && !defined(HRTIM_TIME_UPDATE) +# warning "HRTIM_TIME_UPDATE is not set. Set the default value 0" +# define HRTIM_TIME_UPDATE 0 +#endif + +#if defined(CONFIG_STM32_HRTIM_TIMA) && !defined( HRTIM_TIMA_RESET) +# warning "HRTIM_TIMA_RESET is not set. Set the default value 0" +# define HRTIM_TIMA_RESET 0 +#endif +#if defined(CONFIG_STM32_HRTIM_TIMB) && !defined(HRTIM_TIMB_RESET) +# warning "HRTIM_TIMB_RESET is not set. Set the default value 0" +# define HRTIM_TIMB_RESET 0 +#endif +#if defined(CONFIG_STM32_HRTIM_TIMC) && !defined(HRTIM_TIMC_RESET) +# warning "HRTIM_TIMC_RESET is not set. Set the default value 0" +# define HRTIM_TIMC_RESET 0 +#endif +#if defined(CONFIG_STM32_HRTIM_TIMD) && !defined(HRTIM_TIMD_RESET) +# warning "HRTIM_TIMD_RESET is not set. Set the default value 0" +# define HRTIM_TIMD_RESET 0 +#endif +#if defined(CONFIG_STM32_HRTIM_TIME) && !defined(HRTIM_TIME_RESET) +# warning "HRTIM_TIME_RESET is not set. Set the default value 0" +# define HRTIM_TIME_RESET 0 +#endif + +#ifndef HRTIM_IRQ_COMMON +# define HRTIM_IRQ_COMMON 0 +#endif + +#if defined(CONFIG_STM32_HRTIM_TIMA) && !defined(HRTIM_TIMA_CH1_POL) +# define HRTIM_TIMA_CH1_POL HRTIM_OUT_POL_POS +#endif +#if defined(CONFIG_STM32_HRTIM_TIMA) && !defined(HRTIM_TIMA_CH2_POL) +# define HRTIM_TIMA_CH2_POL HRTIM_OUT_POL_POS +#endif +#if defined(CONFIG_STM32_HRTIM_TIMB) && !defined(HRTIM_TIMB_CH1_POL) +# define HRTIM_TIMB_CH1_POL HRTIM_OUT_POL_POS +#endif +#if defined(CONFIG_STM32_HRTIM_TIMB) && !defined(HRTIM_TIMB_CH2_POL) +# define HRTIM_TIMB_CH2_POL HRTIM_OUT_POL_POS +#endif +#if defined(CONFIG_STM32_HRTIM_TIMC) && !defined(HRTIM_TIMC_CH1_POL) +# define HRTIM_TIMC_CH1_POL HRTIM_OUT_POL_POS +#endif +#if defined(CONFIG_STM32_HRTIM_TIMC) && !defined(HRTIM_TIMC_CH2_POL) +# define HRTIM_TIMC_CH2_POL HRTIM_OUT_POL_POS +#endif +#if defined(CONFIG_STM32_HRTIM_TIMD) && !defined(HRTIM_TIMD_CH1_POL) +# define HRTIM_TIMD_CH1_POL HRTIM_OUT_POL_POS +#endif +#if defined(CONFIG_STM32_HRTIM_TIMD) && !defined(HRTIM_TIMD_CH2_POL) +# define HRTIM_TIMD_CH2_POL HRTIM_OUT_POL_POS +#endif +#if defined(CONFIG_STM32_HRTIM_TIME) && !defined(HRTIM_TIME_CH1_POL) +# define HRTIM_TIME_CH1_POL HRTIM_OUT_POL_POS +#endif +#if defined(CONFIG_STM32_HRTIM_TIME) && !defined(HRTIM_TIME_CH2_POL) +# define HRTIM_TIME_CH2_POL HRTIM_OUT_POL_POS +#endif + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +#ifdef CONFIG_STM32_HRTIM_PWM +/* HRTIM Slave Timer Single Output Set/Reset Configuration */ + +struct stm32_hrtim_timout_s +{ + uint32_t set; /* Set events */ + uint32_t rst; /* Reset events */ + uint8_t pol:1; /* Output polarisation */ +}; + +/* HRTIM Slave Timer Chopper Configuration */ + +#ifdef CONFIG_STM32_HRTIM_CHOPPER +struct stm32_hrtim_chopper_s +{ + uint16_t start_pulse:4; /* Chopper start pulsewidth */ + uint16_t freq:4; /* Chopper carrier frequency value */ + uint16_t duty:3; /* Chopper duty cycle */ + uint16_t _res:5; /* Reserved */ +}; +#endif + +/* HRTIM Slave Timer Deadtime Configuration */ + +#ifdef CONFIG_STM32_HRTIM_DEADTIME +struct stm32_hrtim_deadtime_s +{ + uint8_t en:1; /* Enable deadtime for timer */ + uint8_t fsign_lock:1; /* Deadtime falling sing lock */ + uint8_t rsign_lock:1; /* Deadtime rising sing lock */ + uint8_t falling_lock:1; /* Deadtime falling value lock */ + uint8_t rising_lock:1; /* Deadtime rising value lock */ + uint8_t fsign:1; /* Deadtime falling sign */ + uint8_t rsign:1; /* Deadtime rising sign */ + uint8_t prescaler:3; /* Deadtime prescaler */ + uint16_t rising:9; /* Deadtime rising value */ + uint16_t falling:9; /* Deadtime falling value */ +}; +#endif + +/* HRTIM Timer Burst Mode Configuration */ + +struct stm32_hrtim_tim_burst_s +{ + uint8_t ch1_en:1; /* Enable burst mode operation for CH1 */ + uint8_t ch1_state:1; /* CH1 IDLE state */ + uint8_t ch2_en:1; /* Enable burst mode operation for CH2 */ + uint8_t ch2_state:1; /* CH2 IDLE state */ + uint8_t res:4; +}; + +/* HRTIM Timer PWM structure */ + +struct stm32_hrtim_pwm_s +{ + uint8_t pushpull:1; + uint8_t res:7; + struct stm32_hrtim_timout_s ch1; /* Channel 1 Set/Reset configuration */ + struct stm32_hrtim_timout_s ch2; /* Channel 2 Set/Reset configuration */ + +#ifdef CONFIG_STM32_HRTIM_BURST + struct stm32_hrtim_tim_burst_s burst; +#endif +#ifdef CONFIG_STM32_HRTIM_CHOPPER + struct stm32_hrtim_chopper_s chp; +#endif +#ifdef CONFIG_STM32_HRTIM_DEADTIME + struct stm32_hrtim_deadtime_s dt; +#endif +}; +#endif + +/* HRTIM TIMER Capture structure */ + +#ifdef CONFIG_STM32_HRTIM_CAPTURE +struct stm32_hrtim_capture_s +{ + uint32_t cap1; /* Capture 1 configuration */ + uint32_t cap2; /* Capture 2 configuration */ +}; +#endif + +/* Common data structure for Master Timer and Slave Timers */ + +struct stm32_hrtim_timcmn_s +{ + uint32_t base; /* The base address of the timer */ + uint64_t fclk; /* The frequency of the peripheral clock + * that drives the timer module. + */ + uint8_t prescaler:3; /* Prescaler */ + uint8_t mode; /* Timer mode */ + uint8_t dac:2; /* DAC triggering */ + uint8_t reserved:3; +#ifdef CONFIG_STM32_HRTIM_INTERRUPTS + uint16_t irq; /* interrupts configuration */ +#endif +#ifdef CONFIG_STM32_HRTIM_DMA + uint16_t dma; +#endif +#ifdef CONFIG_STM32_HRTIM_DMABURST + uint32_t dmaburst; +#endif +}; + +/* Master Timer and Slave Timers structure */ + +struct stm32_hrtim_tim_s +{ + struct stm32_hrtim_timcmn_s tim; /* Common Timer data */ + void *priv; /* Timer private data */ +}; + +/* Master Timer private data structure */ + +struct stm32_hrtim_master_priv_s +{ + uint32_t reserved; /* reserved for future use */ +}; + +/* Slave Timer (A-E) private data structure */ + +struct stm32_hrtim_slave_priv_s +{ +#ifdef CONFIG_STM32_HRTIM_FAULTS + uint8_t flt; /* Faults configuration. + * First five bits are fault sources, + * last bit is lock configuration. + */ +#ifdef CONFIG_STM32_HRTIM_AUTODELAYED + uint8_t auto_delayed; /* Auto-delayed mode configuration */ +#endif +#endif + uint16_t update; /* Update configuration */ + uint64_t reset; /* Timer reset events */ +#ifdef CONFIG_STM32_HRTIM_PWM + struct stm32_hrtim_pwm_s pwm; /* PWM configuration */ +#endif +#ifdef CONFIG_STM32_HRTIM_CAPTURE + struct stm32_hrtim_capture_s cap; /* Capture configuration */ +#endif +}; + +#ifdef CONFIG_STM32_HRTIM_FAULTS +/* Structure describes single HRTIM Fault configuration */ + +struct stm32_hrtim_fault_cfg_s +{ + uint8_t pol:1; /* Fault polarity */ + uint8_t src:1; /* Fault source */ + uint8_t filter:4; /* Fault filter */ + uint8_t lock:1; /* Fault lock */ + uint8_t _res:1; /* Reserved */ +}; + +/* Structure describes HRTIM Faults configuration */ + +struct stm32_hrtim_faults_s +{ +#ifdef CONFIG_STM32_HRTIM_FAULT1 + struct stm32_hrtim_fault_cfg_s flt1; +#endif +#ifdef CONFIG_STM32_HRTIM_FAULT2 + struct stm32_hrtim_fault_cfg_s flt2; +#endif +#ifdef CONFIG_STM32_HRTIM_FAULT3 + struct stm32_hrtim_fault_cfg_s flt3; +#endif +#ifdef CONFIG_STM32_HRTIM_FAULT4 + struct stm32_hrtim_fault_cfg_s flt4; +#endif +#ifdef CONFIG_STM32_HRTIM_FAULT5 + struct stm32_hrtim_fault_cfg_s flt5; +#endif +}; +#endif + +#ifdef CONFIG_STM32_HRTIM_EVENTS +/* Structure describes single HRTIM External Event configuration */ + +struct stm32_hrtim_eev_cfg_s +{ + uint8_t filter:4; /* External Event filter */ + uint8_t src:4; /* External Event source */ + uint8_t pol:1; /* External Event polarity */ + uint8_t sen:1; /* External Event sensitivity */ + uint8_t mode:1; /* External Event mode */ + uint8_t _res:5; +}; + +/* Structure describes HRTIM External Events configuration */ + +struct stm32_hrtim_eev_s +{ +#ifdef CONFIG_STM32_HRTIM_EEV1 + struct stm32_hrtim_eev_cfg_s eev1; +#endif +#ifdef CONFIG_STM32_HRTIM_EEV2 + struct stm32_hrtim_eev_cfg_s eev2; +#endif +#ifdef CONFIG_STM32_HRTIM_EEV3 + struct stm32_hrtim_eev_cfg_s eev3; +#endif +#ifdef CONFIG_STM32_HRTIM_EEV4 + struct stm32_hrtim_eev_cfg_s eev4; +#endif +#ifdef CONFIG_STM32_HRTIM_EEV5 + struct stm32_hrtim_eev_cfg_s eev5; +#endif +#ifdef CONFIG_STM32_HRTIM_EEV6 + struct stm32_hrtim_eev_cfg_s eev6; +#endif +#ifdef CONFIG_STM32_HRTIM_EEV7 + struct stm32_hrtim_eev_cfg_s eev7; +#endif +#ifdef CONFIG_STM32_HRTIM_EEV8 + struct stm32_hrtim_eev_cfg_s eev8; +#endif +#ifdef CONFIG_STM32_HRTIM_EEV9 + struct stm32_hrtim_eev_cfg_s eev9; +#endif +#ifdef CONFIG_STM32_HRTIM_EEV10 + struct stm32_hrtim_eev_cfg_s eev10; +#endif +}; +#endif + +#ifdef HRTIM_HAVE_ADC +/* Structure describes HRTIM ADC triggering configuration */ + +struct stm32_hrtim_adc_s +{ +#ifdef HRTIM_HAVE_ADC_TRG1 + uint32_t trg1; +#endif +#ifdef HRTIM_HAVE_ADC_TRG2 + uint32_t trg2; +#endif +#ifdef HRTIM_HAVE_ADC_TRG3 + uint32_t trg3; +#endif +#ifdef HRTIM_HAVE_ADC_TRG4 + uint32_t trg4; +#endif +}; +#endif + +/* Structure describes HRTIM Burst mode configuratione */ + +#ifdef CONFIG_STM32_HRTIM_BURST +struct stm32_hrtim_burst_s +{ + uint8_t clk:4; /* Burst mode clock source */ + uint8_t presc:4; /* Prescaler for f_HRTIM clock */ + uint32_t trg; /* Burst mode triggers */ +}; +#endif + +/* This structure describes the configuration of HRTIM device */ + +struct stm32_hrtim_s +{ + uint32_t base; /* Base address of HRTIM block */ + struct stm32_hrtim_tim_s *master; /* Master Timer */ +#ifdef CONFIG_STM32_HRTIM_TIMA + struct stm32_hrtim_tim_s *tima; /* HRTIM Timer A */ +#endif +#ifdef CONFIG_STM32_HRTIM_TIMB + struct stm32_hrtim_tim_s *timb; /* HRTIM Timer B */ +#endif +#ifdef CONFIG_STM32_HRTIM_TIMC + struct stm32_hrtim_tim_s *timc; /* HRTIM Timer C */ +#endif +#ifdef CONFIG_STM32_HRTIM_TIMD + struct stm32_hrtim_tim_s *timd; /* HRTIM Timer D */ +#endif +#ifdef CONFIG_STM32_HRTIM_TIME + struct stm32_hrtim_tim_s *time; /* HRTIM Timer E */ +#endif +#ifdef CONFIG_STM32_HRTIM_FAULTS + struct stm32_hrtim_faults_s *flt; /* Faults configuration */ +#endif +#ifdef CONFIG_STM32_HRTIM_EVENTS + struct stm32_hrtim_eev_s *eev; /* External Events configuration */ +#endif +#ifdef HRTIM_HAVE_ADC + struct stm32_hrtim_adc_s *adc; /* ADC triggering configuration */ +#endif +#ifdef CONFIG_STM32_HRTIM_BURST + struct stm32_hrtim_burst_s *burst; /* Burst mode configuration */ +#endif +#ifdef CONFIG_STM32_HRTIM_INTERRUPTS + uint32_t irq; /* Common interrupts configuration */ +#endif +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +#ifndef CONFIG_STM32_HRTIM_DISABLE_CHARDRV + +/* HRTIM Driver Methods */ + +static int stm32_hrtim_open(struct file *filep); +static int stm32_hrtim_close(struct file *filep); +static int stm32_hrtim_ioctl(struct file *filep, int cmd, + unsigned long arg); +#endif + +/* HRTIM Register access */ + +static uint32_t hrtim_cmn_getreg(struct stm32_hrtim_s *priv, + uint32_t offset); +static void hrtim_cmn_putreg(struct stm32_hrtim_s *priv, uint32_t offset, + uint32_t value); +#ifdef CONFIG_STM32_HRTIM_BURST +static void hrtim_cmn_modifyreg(struct stm32_hrtim_s *priv, + uint32_t offset, uint32_t clrbits, + uint32_t setbits); +#endif +static void hrtim_tim_putreg(struct stm32_hrtim_s *priv, uint8_t timer, + uint32_t offset, uint32_t value); +static void hrtim_tim_modifyreg(struct stm32_hrtim_s *priv, + uint8_t timer, uint32_t offset, + uint32_t clrbits, uint32_t setbits); + +#ifdef CONFIG_DEBUG_TIMER_INFO +static void hrtim_dumpregs(struct stm32_hrtim_s *priv, uint8_t timer, + const char *msg); +#else +# define hrtim_dumpregs(priv, timer, msg) +#endif + +/* HRTIM helper */ + +static uint32_t hrtim_tim_getreg(struct stm32_hrtim_s *priv, + uint8_t timer, uint32_t offset); +static struct stm32_hrtim_tim_s * + hrtim_tim_get(struct stm32_hrtim_s *priv, + uint8_t timer); +#if defined(CONFIG_STM32_HRTIM_PWM) || defined(CONFIG_STM32_HRTIM_FAULTS) +static struct stm32_hrtim_slave_priv_s * + hrtim_slave_get(struct stm32_hrtim_s *priv, uint8_t timer); +#endif +static uint32_t hrtim_base_get(struct stm32_hrtim_s *priv, + uint8_t timer); + +/* Configuration */ + +static int hrtim_dll_cal(struct stm32_hrtim_s *priv); +static int hrtim_tim_clock_config(struct stm32_hrtim_s *priv, + uint8_t timer, uint8_t pre); +static int hrtim_tim_clocks_config(struct stm32_hrtim_s *priv); +#if defined(CONFIG_STM32_HRTIM_PWM) || defined(CONFIG_STM32_HRTIM_SYNC) +static int hrtim_gpios_config(struct stm32_hrtim_s *priv); +#endif +#if defined(CONFIG_STM32_HRTIM_CAPTURE) +static int hrtim_capture_config(struct stm32_hrtim_s *priv); +static uint16_t hrtim_capture_get(struct hrtim_dev_s *dev, uint8_t timer, + uint8_t index); +static int hrtim_soft_capture(struct hrtim_dev_s *dev, uint8_t timer, + uint8_t index); +#endif +#if defined(CONFIG_STM32_HRTIM_SYNC) +static int hrtim_synch_config(struct stm32_hrtim_s *priv); +#endif +#if defined(CONFIG_STM32_HRTIM_PWM) +static int hrtim_outputs_config(struct stm32_hrtim_s *priv); +static int hrtim_outputs_enable(struct hrtim_dev_s *dev, + uint16_t outputs, bool state); +static int hrtim_output_set_set(struct hrtim_dev_s *dev, uint16_t output, + uint32_t set); +static int hrtim_output_rst_set(struct hrtim_dev_s *dev, uint16_t output, + uint32_t rst); +#endif +#ifdef HRTIM_HAVE_ADC +static int hrtim_adc_config(struct stm32_hrtim_s *priv); +#endif +#ifdef CONFIG_STM32_HRTIM_DAC +static int hrtim_dac_config(struct stm32_hrtim_s *priv); +#endif +#ifdef CONFIG_STM32_HRTIM_DMA +static int hrtim_dma_cfg(struct stm32_hrtim_s *priv); +static int hrtim_tim_dma_cfg(struct stm32_hrtim_s *priv, uint8_t timer, + uint16_t dma); +#endif +#ifdef CONFIG_STM32_HRTIM_DEADTIME +static int hrtim_deadtime_update(struct hrtim_dev_s *dev, uint8_t timer, + uint8_t dt, uint16_t value); +static uint16_t hrtim_deadtime_get(struct hrtim_dev_s *dev, + uint8_t timer, uint8_t dt); +static int hrtim_tim_deadtime_cfg(struct stm32_hrtim_s *priv, + uint8_t timer); +static int hrtim_deadtime_config(struct stm32_hrtim_s *priv); +#endif +#ifdef CONFIG_STM32_HRTIM_CHOPPER +static int hrtim_chopper_enable(struct hrtim_dev_s *dev, uint8_t timer, + uint8_t chan, bool state); +static int hrtim_tim_chopper_cfg(struct stm32_hrtim_s *priv, + uint8_t timer); +static int hrtim_chopper_config(struct stm32_hrtim_s *priv); +#endif +#ifdef CONFIG_STM32_HRTIM_BURST +static int hrtim_burst_enable(struct hrtim_dev_s *dev, bool state); +static int hrtim_burst_cmp_update(struct hrtim_dev_s *dev, uint16_t cmp); +static int hrtim_burst_per_update(struct hrtim_dev_s *dev, uint16_t per); +static uint16_t hrtim_burst_cmp_get(struct hrtim_dev_s *dev); +static uint16_t hrtim_burst_per_get(struct hrtim_dev_s *dev); +static int hrtim_burst_pre_update(struct hrtim_dev_s *dev, uint8_t pre); +static int hrtim_burst_pre_get(struct hrtim_dev_s *dev); +static int hrtim_burst_config(struct stm32_hrtim_s *priv); +#endif +#ifdef CONFIG_STM32_HRTIM_FAULTS +static int hrtim_faults_config(struct stm32_hrtim_s *priv); +static int hrtim_flt_cfg(struct stm32_hrtim_s *priv, uint8_t index); +static int hrtim_tim_faults_cfg(struct stm32_hrtim_s *priv, + uint8_t timer); +#endif +#ifdef CONFIG_STM32_HRTIM_EVENTS +static int hrtim_events_config(struct stm32_hrtim_s *priv); +static int hrtim_eev_cfg(struct stm32_hrtim_s *priv, uint8_t index); +#endif +#ifdef CONFIG_STM32_HRTIM_INTERRUPTS +static int hrtim_irq_config(struct stm32_hrtim_s *priv); +static uint16_t hrtim_irq_get(struct hrtim_dev_s *dev, uint8_t timer); +static int hrtim_irq_ack(struct hrtim_dev_s *dev, uint8_t timer, + int source); +#endif +static int hrtim_cmp_update(struct hrtim_dev_s *dev, uint8_t timer, + uint8_t index, uint16_t cmp); +static int hrtim_per_update(struct hrtim_dev_s *dev, uint8_t timer, + uint16_t per); +static int hrtim_rep_update(struct hrtim_dev_s *dev, uint8_t timer, + uint8_t rep); +static uint16_t hrtim_per_get(struct hrtim_dev_s *dev, uint8_t timer); +static uint16_t hrtim_cmp_get(struct hrtim_dev_s *dev, uint8_t timer, + uint8_t index); +static uint64_t hrtim_fclk_get(struct hrtim_dev_s *dev, uint8_t timer); +static int hrtim_soft_update(struct hrtim_dev_s *dev, uint8_t timer); +static int hrtim_soft_reset(struct hrtim_dev_s *dev, uint8_t timer); +static int hrtim_tim_freq_set(struct hrtim_dev_s *dev, uint8_t timer, + uint64_t freq); +static int hrtim_tim_enable(struct hrtim_dev_s *dev, uint8_t timers, + bool state); +static int hrtim_tim_reset_set(struct stm32_hrtim_s *priv, + uint8_t timer, uint64_t reset); +static int hrtim_reset_config(struct stm32_hrtim_s *priv); +static int hrtim_tim_update_set(struct stm32_hrtim_s *priv, + uint8_t timer, + uint16_t update); +static int hrtim_update_config(struct stm32_hrtim_s *priv); + +static void hrtim_tim_mode_set(struct stm32_hrtim_s *priv, uint8_t timer, + uint8_t mode); +static void hrtim_mode_config(struct stm32_hrtim_s *priv); + +/* Initialization */ + +static int stm32_hrtimconfig(struct stm32_hrtim_s *priv); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#ifndef CONFIG_STM32_HRTIM_DISABLE_CHARDRV +static const struct file_operations g_hrtim_fops = +{ + stm32_hrtim_open, /* open */ + stm32_hrtim_close, /* close */ + NULL, /* read */ + NULL, /* write */ + NULL, /* seek */ + stm32_hrtim_ioctl, /* ioctl */ +}; +#endif /* CONFIG_STM32_HRTIM_DISABLE_CHARDRV */ + +/* Master Timer data */ + +static struct stm32_hrtim_tim_s g_master = +{ + .tim = + { + .base = STM32_HRTIM1_MASTER_BASE, + + /* If MASTER is disabled, we need only MASTER base */ + +#ifdef CONFIG_STM32_HRTIM_MASTER + .fclk = HRTIM_CLOCK / (1 << HRTIM_MASTER_PRESCALER), + .prescaler = HRTIM_MASTER_PRESCALER, + .mode = HRTIM_MASTER_MODE, +# ifdef CONFIG_STM32_HRTIM_MASTER_DAC + .dac = HRTIM_MASTER_DAC, +# endif +# ifdef CONFIG_STM32_HRTIM_MASTER_IRQ + .irq = HRTIM_MASTER_IRQ +# endif +# ifdef CONFIG_STM32_HRTIM_MASTER_DMA + .dma = HRTIM_MASTER_DMA +# endif +#endif + }, + .priv = NULL, +}; + +#ifdef CONFIG_STM32_HRTIM_TIMA + +/* Timer A private data */ + +static struct stm32_hrtim_slave_priv_s g_tima_priv = +{ + .update = HRTIM_TIMA_UPDATE, + .reset = HRTIM_TIMA_RESET, +#ifdef CONFIG_STM32_HRTIM_TIMA_PWM + .pwm = + { +#ifdef CONFIG_STM32_HRTIM_TIMA_PSHPLL + .pushpull = 1, +#endif +#ifdef CONFIG_STM32_HRTIM_TIMA_PWM_CH1 + .ch1 = + { + .set = HRTIM_TIMA_CH1_SET, + .rst = HRTIM_TIMA_CH1_RST, + .pol = HRTIM_TIMA_CH1_POL + }, +#endif +#ifdef CONFIG_STM32_HRTIM_TIMA_PWM_CH2 + .ch2 = + { + .set = HRTIM_TIMA_CH2_SET, + .rst = HRTIM_TIMA_CH2_RST, + .pol = HRTIM_TIMA_CH2_POL + }, +#endif +#ifdef CONFIG_STM32_HRTIM_TIMA_BURST + .burst = + { +# ifdef CONFIG_STM32_HRTIM_TIMA_BURST_CH1 + .ch1_en = 1, + .ch1_state = HRTIM_TIMA_CH1_IDLE_STATE, +# else + .ch1_en = 0, +# endif +# ifdef CONFIG_STM32_HRTIM_TIMA_BURST_CH2 + .ch2_en = 1, + .ch2_state = HRTIM_TIMA_CH2_IDLE_STATE +# else + .ch2_en = 0, +# endif + }, +#endif +#ifdef CONFIG_STM32_HRTIM_TIMA_CHOP + .chp = + { + .start_pulse = HRTIM_TIMA_CHOP_START, + .duty = HRTIM_TIMA_CHOP_DUTY, + .freq = HRTIM_TIMA_CHOP_FREQ + }, +#endif +#ifdef CONFIG_STM32_HRTIM_TIMA_DT + .dt = + { + .en = 1, + .fsign_lock = HRTIM_TIMA_DT_FSLOCK, + .rsign_lock = HRTIM_TIMA_DT_RSLOCK, + .falling_lock = HRTIM_TIMA_DT_FVLOCK, + .rising_lock = HRTIM_TIMA_DT_RVLOCK, + .fsign = HRTIM_TIMA_DT_FSIGN, + .rsign = HRTIM_TIMA_DT_RSIGN, + .prescaler = HRTIM_TIMA_DT_PRESCALER + } +#endif + }, +#endif +#ifdef CONFIG_STM32_HRTIM_TIMA_CAP + .cap = + { + .cap1 = HRTIM_TIMA_CAPTURE1, + .cap2 = HRTIM_TIMA_CAPTURE2, + } +#endif +}; + +/* Timer A data */ + +static struct stm32_hrtim_tim_s g_tima = +{ + .tim = + { + .base = STM32_HRTIM1_TIMERA_BASE, + .fclk = HRTIM_CLOCK / (1 << HRTIM_TIMA_PRESCALER), + .prescaler = HRTIM_TIMA_PRESCALER, + .mode = HRTIM_TIMA_MODE, +#ifdef CONFIG_STM32_HRTIM_TIMA_DAC + .dac = HRTIM_TIMA_DAC, +#endif +#ifdef CONFIG_STM32_HRTIM_TIMA_IRQ + .irq = HRTIM_TIMA_IRQ, +#endif +#ifdef CONFIG_STM32_HRTIM_TIMA_DMA + .dma = HRTIM_TIMA_DMA +#endif + }, + .priv = &g_tima_priv +}; +#endif + +#ifdef CONFIG_STM32_HRTIM_TIMB +/* Timer B private data */ + +static struct stm32_hrtim_slave_priv_s g_timb_priv = +{ + .update = HRTIM_TIMB_UPDATE, + .reset = HRTIM_TIMB_RESET, +#ifdef CONFIG_STM32_HRTIM_TIMB_PWM + .pwm = + { +#ifdef CONFIG_STM32_HRTIM_TIMB_PSHPLL + .pushpull = 1, +#endif +#ifdef CONFIG_STM32_HRTIM_TIMB_PWM_CH1 + .ch1 = + { + .set = HRTIM_TIMB_CH1_SET, + .rst = HRTIM_TIMB_CH1_RST, + .pol = HRTIM_TIMB_CH1_POL + }, +#endif +#ifdef CONFIG_STM32_HRTIM_TIMB_PWM_CH2 + .ch2 = + { + .set = HRTIM_TIMB_CH2_SET, + .rst = HRTIM_TIMB_CH2_RST, + .pol = HRTIM_TIMB_CH2_POL + }, +#endif +#ifdef CONFIG_STM32_HRTIM_TIMB_BURST + .burst = + { +# ifdef CONFIG_STM32_HRTIM_TIMB_BURST_CH1 + .ch1_en = 1, + .ch1_state = HRTIM_TIMB_CH1_IDLE_STATE, +# else + .ch1_en = 0, +# endif +# ifdef CONFIG_STM32_HRTIM_TIMB_BURST_CH2 + .ch2_en = 1, + .ch2_state = HRTIM_TIMB_CH2_IDLE_STATE +# else + .ch2_en = 0, +# endif + }, +#endif +#ifdef CONFIG_STM32_HRTIM_TIMB_CHOP + .chp = + { + .start_pulse = HRTIM_TIMB_CHOP_START, + .duty = HRTIM_TIMB_CHOP_DUTY, + .freq = HRTIM_TIMB_CHOP_FREQ + }, +#endif +#ifdef CONFIG_STM32_HRTIM_TIMB_DT + .dt = + { + .en = 1, + .fsign_lock = HRTIM_TIMB_DT_FSLOCK, + .rsign_lock = HRTIM_TIMB_DT_RSLOCK, + .falling_lock = HRTIM_TIMB_DT_FVLOCK, + .rising_lock = HRTIM_TIMB_DT_RVLOCK, + .fsign = HRTIM_TIMB_DT_FSIGN, + .rsign = HRTIM_TIMB_DT_RSIGN, + .prescaler = HRTIM_TIMB_DT_PRESCALER + } +#endif + }, +#endif +#ifdef CONFIG_STM32_HRTIM_TIMB_CAP + .cap = + { + .cap1 = HRTIM_TIMB_CAPTURE1, + .cap2 = HRTIM_TIMB_CAPTURE2, + } +#endif +}; + +/* Timer B data */ + +static struct stm32_hrtim_tim_s g_timb = +{ + .tim = + { + .base = STM32_HRTIM1_TIMERB_BASE, + .fclk = HRTIM_CLOCK / (1 << HRTIM_TIMB_PRESCALER), + .prescaler = HRTIM_TIMB_PRESCALER, + .mode = HRTIM_TIMB_MODE, +#ifdef CONFIG_STM32_HRTIM_TIMB_DAC + .dac = HRTIM_TIMB_DAC, +#endif +#ifdef CONFIG_STM32_HRTIM_TIMB_IRQ + .irq = HRTIM_TIMB_IRQ, +#endif +#ifdef CONFIG_STM32_HRTIM_TIMB_DMA + .dma = HRTIM_TIMB_DMA +#endif + }, + .priv = &g_timb_priv +}; +#endif + +#ifdef CONFIG_STM32_HRTIM_TIMC +/* Timer C private data */ + +static struct stm32_hrtim_slave_priv_s g_timc_priv = +{ + .update = HRTIM_TIMC_UPDATE, + .reset = HRTIM_TIMC_RESET, +#ifdef CONFIG_STM32_HRTIM_TIMC_PWM + .pwm = + { +#ifdef CONFIG_STM32_HRTIM_TIMC_PSHPLL + .pushpull = 1, +#endif +#ifdef CONFIG_STM32_HRTIM_TIMC_PWM_CH1 + .ch1 = + { + .set = HRTIM_TIMC_CH1_SET, + .rst = HRTIM_TIMC_CH1_RST, + .pol = HRTIM_TIMC_CH1_POL + }, +#endif +#ifdef CONFIG_STM32_HRTIM_TIMC_PWM_CH2 + .ch2 = + { + .set = HRTIM_TIMC_CH2_SET, + .rst = HRTIM_TIMC_CH2_RST, + .pol = HRTIM_TIMC_CH2_POL + }, +#endif +#ifdef CONFIG_STM32_HRTIM_TIMC_BURST + .burst = + { +# ifdef CONFIG_STM32_HRTIM_TIMC_BURST_CH1 + .ch1_en = 1, + .ch1_state = HRTIM_TIMC_CH1_IDLE_STATE, +# else + .ch1_en = 0, +# endif +# ifdef CONFIG_STM32_HRTIM_TIMC_BURST_CH2 + .ch2_en = 1, + .ch2_state = HRTIM_TIMC_CH2_IDLE_STATE +# else + .ch2_en = 0, +# endif + }, +#endif +#ifdef CONFIG_STM32_HRTIM_TIMC_CHOP + .chp = + { + .start_pulse = HRTIM_TIMC_CHOP_START, + .duty = HRTIM_TIMC_CHOP_DUTY, + .freq = HRTIM_TIMC_CHOP_FREQ + }, +#endif +#ifdef CONFIG_STM32_HRTIM_TIMC_DT + .dt = + { + .en = 1, + .fsign_lock = HRTIM_TIMC_DT_FSLOCK, + .rsign_lock = HRTIM_TIMC_DT_RSLOCK, + .falling_lock = HRTIM_TIMC_DT_FVLOCK, + .rising_lock = HRTIM_TIMC_DT_RVLOCK, + .fsign = HRTIM_TIMC_DT_FSIGN, + .rsign = HRTIM_TIMC_DT_RSIGN, + .prescaler = HRTIM_TIMC_DT_PRESCALER + } +#endif + }, +#endif +#ifdef CONFIG_STM32_HRTIM_TIMC_CAP + .cap = + { + .cap1 = HRTIM_TIMC_CAPTURE1, + .cap2 = HRTIM_TIMC_CAPTURE2, + } +#endif +}; + +/* Timer C data */ + +static struct stm32_hrtim_tim_s g_timc = +{ + .tim = + { + .base = STM32_HRTIM1_TIMERC_BASE, + .fclk = HRTIM_CLOCK / (1 << HRTIM_TIMC_PRESCALER), + .prescaler = HRTIM_TIMC_PRESCALER, + .mode = HRTIM_TIMC_MODE, +#ifdef CONFIG_STM32_HRTIM_TIMC_DAC + .dac = HRTIM_TIMC_DAC, +#endif +#ifdef CONFIG_STM32_HRTIM_TIMC_IRQ + .irq = HRTIM_TIMC_IRQ, +#endif +#ifdef CONFIG_STM32_HRTIM_TIMC_DMA + .dma = HRTIM_TIMC_DMA +#endif + }, + .priv = &g_timc_priv +}; +#endif + +#ifdef CONFIG_STM32_HRTIM_TIMD +/* Timer D private data */ + +static struct stm32_hrtim_slave_priv_s g_timd_priv = +{ + .update = HRTIM_TIMD_UPDATE, + .reset = HRTIM_TIMD_RESET, +#ifdef CONFIG_STM32_HRTIM_TIMD_PWM + .pwm = + { +#ifdef CONFIG_STM32_HRTIM_TIMD_PSHPLL + .pushpull = 1, +#endif +#ifdef CONFIG_STM32_HRTIM_TIMD_PWM_CH1 + .ch1 = + { + .set = HRTIM_TIMD_CH1_SET, + .rst = HRTIM_TIMD_CH1_RST, + .pol = HRTIM_TIMD_CH1_POL + }, +#endif +#ifdef CONFIG_STM32_HRTIM_TIMD_PWM_CH2 + .ch2 = + { + .set = HRTIM_TIMD_CH2_SET, + .rst = HRTIM_TIMD_CH2_RST, + .pol = HRTIM_TIMD_CH2_POL + }, +#endif +#ifdef CONFIG_STM32_HRTIM_TIMD_BURST + .burst = + { +# ifdef CONFIG_STM32_HRTIM_TIMD_BURST_CH1 + .ch1_en = 1, + .ch1_state = HRTIM_TIMD_CH1_IDLE_STATE, +# else + .ch1_en = 0, +# endif +# ifdef CONFIG_STM32_HRTIM_TIMD_BURST_CH2 + .ch2_en = 1, + .ch2_state = HRTIM_TIMD_CH2_IDLE_STATE +# else + .ch2_en = 0, +# endif + }, +#endif +#ifdef CONFIG_STM32_HRTIM_TIMD_CHOP + .chp = + { + .start_pulse = HRTIM_TIMD_CHOP_START, + .duty = HRTIM_TIMD_CHOP_DUTY, + .freq = HRTIM_TIMD_CHOP_FREQ + }, +#endif +#ifdef CONFIG_STM32_HRTIM_TIMD_DT + .dt = + { + .en = 1, + .fsign_lock = HRTIM_TIMD_DT_FSLOCK, + .rsign_lock = HRTIM_TIMD_DT_RSLOCK, + .falling_lock = HRTIM_TIMD_DT_FVLOCK, + .rising_lock = HRTIM_TIMD_DT_RVLOCK, + .fsign = HRTIM_TIMD_DT_FSIGN, + .rsign = HRTIM_TIMD_DT_RSIGN, + .prescaler = HRTIM_TIMD_DT_PRESCALER + } +#endif + }, +#endif +#ifdef CONFIG_STM32_HRTIM_TIMD_CAP + .cap = + { + .cap1 = HRTIM_TIMD_CAPTURE1, + .cap2 = HRTIM_TIMD_CAPTURE2, + } +#endif +}; + +/* Timer D data */ + +static struct stm32_hrtim_tim_s g_timd = +{ + .tim = + { + .base = STM32_HRTIM1_TIMERD_BASE, + .fclk = HRTIM_CLOCK / (1 << HRTIM_TIMD_PRESCALER), + .prescaler = HRTIM_TIMD_PRESCALER, + .mode = HRTIM_TIMD_MODE, +#ifdef CONFIG_STM32_HRTIM_TIMD_DAC + .dac = HRTIM_TIMD_DAC, +#endif +#ifdef CONFIG_STM32_HRTIM_TIMD_IRQ + .irq = HRTIM_TIMD_IRQ, +#endif +#ifdef CONFIG_STM32_HRTIM_TIMD_DMA + .dma = HRTIM_TIMD_DMA +#endif + }, + .priv = &g_timd_priv +}; +#endif + +#ifdef CONFIG_STM32_HRTIM_TIME +/* Timer E private data */ + +static struct stm32_hrtim_slave_priv_s g_time_priv = +{ + .update = HRTIM_TIME_UPDATE, + .reset = HRTIM_TIME_RESET, +#ifdef CONFIG_STM32_HRTIM_TIME_PWM + .pwm = + { +#ifdef CONFIG_STM32_HRTIM_TIME_PSHPLL + .pushpull = 1, +#endif +#ifdef CONFIG_STM32_HRTIM_TIME_PWM_CH1 + .ch1 = + { + .set = HRTIM_TIME_CH1_SET, + .rst = HRTIM_TIME_CH1_RST, + .pol = HRTIM_TIME_CH1_POL + }, +#endif +#ifdef CONFIG_STM32_HRTIM_TIME_PWM_CH2 + .ch2 = + { + .set = HRTIM_TIME_CH2_SET, + .rst = HRTIM_TIME_CH2_RST, + .pol = HRTIM_TIME_CH1_POL + }, +#endif +#ifdef CONFIG_STM32_HRTIM_TIME_BURST + .burst = + { +# ifdef CONFIG_STM32_HRTIM_TIME_BURST_CH1 + .ch1_en = 1, + .ch1_state = HRTIM_TIME_CH1_IDLE_STATE, +# else + .ch1_en = 0, +# endif +# ifdef CONFIG_STM32_HRTIM_TIME_BURST_CH2 + .ch2_en = 1, + .ch2_state = HRTIM_TIME_CH2_IDLE_STATE +# else + .ch2_en = 0, +# endif + }, +#endif +#ifdef CONFIG_STM32_HRTIM_TIME_CHOP + .chp = + { + .start_pulse = HRTIM_TIME_CHOP_START, + .duty = HRTIM_TIME_CHOP_DUTY, + .freq = HRTIM_TIME_CHOP_FREQ + }, +#endif +#ifdef CONFIG_STM32_HRTIM_TIME_DT + .dt = + { + .en = 1, + .fsign_lock = HRTIM_TIME_DT_FSLOCK, + .rsign_lock = HRTIM_TIME_DT_RSLOCK, + .falling_lock = HRTIM_TIME_DT_FVLOCK, + .rising_lock = HRTIM_TIME_DT_RVLOCK, + .fsign = HRTIM_TIME_DT_FSIGN, + .rsign = HRTIM_TIME_DT_RSIGN, + .prescaler = HRTIM_TIME_DT_PRESCALER + } +#endif + }, +#endif +#ifdef CONFIG_STM32_HRTIM_TIME_CAP + .cap = + { + .cap1 = HRTIM_TIME_CAPTURE1, + .cap2 = HRTIM_TIME_CAPTURE2, + } +#endif +}; + +/* Timer E data */ + +static struct stm32_hrtim_tim_s g_time = +{ + .tim = + { + .base = STM32_HRTIM1_TIMERE_BASE, + .fclk = HRTIM_CLOCK / (1 << HRTIM_TIME_PRESCALER), + .prescaler = HRTIM_TIME_PRESCALER, + .mode = HRTIM_TIME_MODE, +#ifdef CONFIG_STM32_HRTIM_TIME_DAC + .dac = HRTIM_TIME_DAC, +#endif +#ifdef CONFIG_STM32_HRTIM_TIME_IRQ + .irq = HRTIM_TIME_IRQ, +#endif +#ifdef CONFIG_STM32_HRTIM_TIME_DMA + .dma = HRTIM_TIME_DMA +#endif + }, + .priv = &g_time_priv +}; +#endif + +/* Faults data */ + +#ifdef CONFIG_STM32_HRTIM_FAULTS +struct stm32_hrtim_faults_s g_flt = +{ +#ifdef CONFIG_STM32_HRTIM_FAULT1 + .flt1 = + { + .pol = HRTIM_FAULT1_POL, + .src = HRTIM_FAULT1_SRC, + .filter = HRTIM_FAULT1_FILTER, + .lock = HRTIM_FAULT1_LOCK, + }, +#endif +#ifdef CONFIG_STM32_HRTIM_FAULT2 + .flt2 = + { + .pol = HRTIM_FAULT2_POL, + .src = HRTIM_FAULT2_SRC, + .filter = HRTIM_FAULT2_FILTER, + .lock = HRTIM_FAULT2_LOCK, + }, +#endif +#ifdef CONFIG_STM32_HRTIM_FAULT3 + .flt3 = + { + .pol = HRTIM_FAULT3_POL, + .src = HRTIM_FAULT3_SRC, + .filter = HRTIM_FAULT3_FILTER, + .lock = HRTIM_FAULT3_LOCK, + }, +#endif +#ifdef CONFIG_STM32_HRTIM_FAULT4 + .flt2 = + { + .pol = HRTIM_FAULT4_POL, + .src = HRTIM_FAULT4_SRC, + .filter = HRTIM_FAULT4_FILTER, + .lock = HRTIM_FAULT4_LOCK, + }, +#endif +#ifdef CONFIG_STM32_HRTIM_FAULT5 + .flt2 = + { + .pol = HRTIM_FAULT5_POL, + .src = HRTIM_FAULT5_SRC, + .filter = HRTIM_FAULT5_FILTER, + .lock = HRTIM_FAULT5_LOCK, + }, +#endif +}; +#endif + +/* External Events data */ + +#ifdef CONFIG_STM32_HRTIM_EVENTS +struct stm32_hrtim_eev_s g_eev = +{ +#ifdef CONFIG_STM32_HRTIM_EEV1 + .eev1 = + { + .filter = HRTIM_EEV1_FILTER, + .src = HRTIM_EEV1_SRC, + .pol = HRTIM_EEV1_POL, + .sen = HRTIM_EEV1_SEN, + .mode = HRTIM_EEV1_MODE, + } +#endif +#ifdef CONFIG_STM32_HRTIM_EEV2 + .eev2 = + { + .filter = HRTIM_EEV2_FILTER, + .src = HRTIM_EEV2_SRC, + .pol = HRTIM_EEV2_POL, + .sen = HRTIM_EEV2_SEN, + .mode = HRTIM_EEV2_MODE, + } +#endif +#ifdef CONFIG_STM32_HRTIM_EEV3 + .eev3 = + { + .filter = HRTIM_EEV3_FILTER, + .src = HRTIM_EEV3_SRC, + .pol = HRTIM_EEV3_POL, + .sen = HRTIM_EEV3_SEN, + .mode = HRTIM_EEV3_MODE, + } +#endif +#ifdef CONFIG_STM32_HRTIM_EEV4 + .eev4 = + { + .filter = HRTIM_EEV4_FILTER, + .src = HRTIM_EEV4_SRC, + .pol = HRTIM_EEV4_POL, + .sen = HRTIM_EEV4_SEN, + .mode = HRTIM_EEV4_MODE, + } +#endif +#ifdef CONFIG_STM32_HRTIM_EEV5 + .eev5 = + { + .filter = HRTIM_EEV5_FILTER, + .src = HRTIM_EEV5_SRC, + .pol = HRTIM_EEV5_POL, + .sen = HRTIM_EEV5_SEN, + .mode = HRTIM_EEV5_MODE, + } +#endif +#ifdef CONFIG_STM32_HRTIM_EEV6 + .eev6 = + { + .filter = HRTIM_EEV6_FILTER, + .src = HRTIM_EEV6_SRC, + .pol = HRTIM_EEV6_POL, + .sen = HRTIM_EEV6_SEN, + .mode = HRTIM_EEV6_MODE, + } +#endif +#ifdef CONFIG_STM32_HRTIM_EEV7 + .eev7 = + { + .filter = HRTIM_EEV7_FILTER, + .src = HRTIM_EEV7_SRC, + .pol = HRTIM_EEV7_POL, + .sen = HRTIM_EEV7_SEN, + .mode = HRTIM_EEV7_MODE, + } +#endif +#ifdef CONFIG_STM32_HRTIM_EEV8 + .eev8 = + { + .filter = HRTIM_EEV8_FILTER, + .src = HRTIM_EEV8_SRC, + .pol = HRTIM_EEV8_POL, + .sen = HRTIM_EEV8_SEN, + .mode = HRTIM_EEV8_MODE, + } +#endif +#ifdef CONFIG_STM32_HRTIM_EEV9 + .eev9 = + { + .filter = HRTIM_EEV9_FILTER, + .src = HRTIM_EEV9_SRC, + .pol = HRTIM_EEV9_POL, + .sen = HRTIM_EEV9_SEN, + .mode = HRTIM_EEV9_MODE, + } +#endif +#ifdef CONFIG_STM32_HRTIM_EEV10 + .eev10 = + { + .filter = HRTIM_EEV10_FILTER, + .src = HRTIM_EEV10_SRC, + .pol = HRTIM_EEV10_POL, + .sen = HRTIM_EEV10_SEN, + .mode = HRTIM_EEV10_MODE, + } +#endif +}; +#endif + +/* ADC triggering data */ + +#ifdef HRTIM_HAVE_ADC +struct stm32_hrtim_adc_s g_adc = +{ +#ifdef HRTIM_HAVE_ADC_TRG1 + .trg1 = HRTIM_ADC_TRG1, +#endif +#ifdef HRTIM_HAVE_ADC_TRG2 + .trg2 = HRTIM_ADC_TRG2, +#endif +#ifdef HRTIM_HAVE_ADC_TRG3 + .trg3 = HRTIM_ADC_TRG3, +#endif +#ifdef HRTIM_HAVE_ADC_TRG4 + .trg4 = HRTIM_ADC_TRG4 +#endif +}; +#endif + +/* Burst mode data */ + +#ifdef CONFIG_STM32_HRTIM_BURST +struct stm32_hrtim_burst_s g_burst = +{ + .clk = HRTIM_BURST_CLOCK, + .presc = HRTIM_BURST_PRESCALER, + .trg = HRTIM_BURST_TRIGGERS +}; +#endif + +/* HRTIM1 private data */ + +static struct stm32_hrtim_s g_hrtim1priv = +{ + .master = &g_master, + .base = STM32_HRTIM1_BASE, +#ifdef CONFIG_STM32_HRTIM_TIMA + .tima = &g_tima, +#endif +#ifdef CONFIG_STM32_HRTIM_TIMB + .timb = &g_timb, +#endif +#ifdef CONFIG_STM32_HRTIM_TIMC + .timc = &g_timc, +#endif +#ifdef CONFIG_STM32_HRTIM_TIMD + .timd = &g_timd, +#endif +#ifdef CONFIG_STM32_HRTIM_TIME + .time = &g_time, +#endif +#ifdef CONFIG_STM32_HRTIM_FAULTS + .flt = &g_flt, +#endif +#ifdef CONFIG_STM32_HRTIM_EVENTS + .eev = &g_eev, +#endif +#ifdef HRTIM_HAVE_ADC + .adc = &g_adc, +#endif +#ifdef CONFIG_STM32_HRTIM_BURST + .burst = &g_burst, +#endif +#ifdef CONFIG_STM32_HRTIM_COMMON_IRQ + .irq = HRTIM_IRQ_COMMON, +#endif +}; + +/* HRTIM interface */ + +static const struct stm32_hrtim_ops_s g_hrtim1ops = +{ + .cmp_update = hrtim_cmp_update, + .per_update = hrtim_per_update, + .rep_update = hrtim_rep_update, + .per_get = hrtim_per_get, + .cmp_get = hrtim_cmp_get, + .fclk_get = hrtim_fclk_get, + .soft_update = hrtim_soft_update, + .soft_reset = hrtim_soft_reset, + .freq_set = hrtim_tim_freq_set, + .tim_enable = hrtim_tim_enable, +#ifdef CONFIG_STM32_HRTIM_INTERRUPTS + .irq_ack = hrtim_irq_ack, + .irq_get = hrtim_irq_get, +#endif +#ifdef CONFIG_STM32_HRTIM_PWM + .outputs_enable = hrtim_outputs_enable, + .output_rst_set = hrtim_output_rst_set, + .output_set_set = hrtim_output_set_set, +#endif +#ifdef CONFIG_STM32_HRTIM_BURST + .burst_enable = hrtim_burst_enable, + .burst_cmp_set = hrtim_burst_cmp_update, + .burst_per_set = hrtim_burst_per_update, + .burst_pre_set = hrtim_burst_pre_update, + .burst_cmp_get = hrtim_burst_cmp_get, + .burst_per_get = hrtim_burst_per_get, + .burst_pre_get = hrtim_burst_pre_get, +#endif +#ifdef CONFIG_STM32_HRTIM_CHOPPER + .chopper_enable = hrtim_chopper_enable, +#endif +#ifdef CONFIG_STM32_HRTIM_DEADTIME + .deadtime_update = hrtim_deadtime_update, + .deadtime_get = hrtim_deadtime_get, +#endif +#ifdef CONFIG_STM32_HRTIM_CAPTURE + .capture_get = hrtim_capture_get, + .soft_capture = hrtim_soft_capture, +#endif +}; + +/* HRTIM device structure */ + +struct hrtim_dev_s g_hrtim1dev = +{ + .hd_ops = &g_hrtim1ops, + .hd_priv = &g_hrtim1priv, + .initialized = false, +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +#ifndef CONFIG_STM32_HRTIM_DISABLE_CHARDRV + +/**************************************************************************** + * Name: stm32_hrtim_open + * + * Description: + * This function is called whenever the HRTIM device is opened. + * + ****************************************************************************/ + +static int stm32_hrtim_open(struct file *filep) +{ +#warning "stm32_hrtim_open: missing logic" + return OK; +} + +/**************************************************************************** + * Name: stm32_hrtim_close + * + * Description: + * This function is called when the HRTIM device is closed. + * + ****************************************************************************/ + +static int stm32_hrtim_close(struct file *filep) +{ +#warning "smt32_hrtim_close: missing logic" + return OK; +} + +/**************************************************************************** + * Name: stm32_hrtim_ioctl + * + * Description: + * The standard ioctl method. This is where ALL of the HRTIM work is done. + * + ****************************************************************************/ + +static int stm32_hrtim_ioctl(struct file *filep, int cmd, + unsigned long arg) +{ + struct inode *inode = filep->f_inode; + struct hrtim_dev_s *dev; + struct stm32_hrtim_s *hrtim; + int ret; + + tmrinfo("cmd: %d arg: %ld\n", cmd, arg); + dev = inode->i_private; + DEBUGASSERT(dev != NULL); + hrtim = dev->hd_priv; + + UNUSED(hrtim); + +#warning "smt32_hrtim_ioctl: missing logic" + + /* Handle HRTIM ioctl commands */ + + switch (cmd) + { + default: + { + ret = -ENOTTY; + break; + } + } + + return ret; +} + +#endif /* CONFIG_STM32_HRTIM_DISABLE_CHARDRV */ + +/**************************************************************************** + * Name: hrtim_cmn_getreg + * + * Description: + * Read the value of an HRTIM register. + * + * Input Parameters: + * priv - A reference to the HRTIM block + * offset - The offset to the register to read + * + * Returned Value: + * The current contents of the specified register + * + ****************************************************************************/ + +static uint32_t hrtim_cmn_getreg(struct stm32_hrtim_s *priv, + uint32_t offset) +{ + return getreg32(priv->base + STM32_HRTIM_CMN_OFFSET + offset); +} + +/**************************************************************************** + * Name: hrtim_cmn_putreg + * + * Description: + * Write a value to an HRTIM register. + * + * Input Parameters: + * priv - A reference to the HRTIM block + * offset - The offset to the register to write to + * value - The value to write to the register + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void hrtim_cmn_putreg(struct stm32_hrtim_s *priv, uint32_t offset, + uint32_t value) +{ + putreg32(value, priv->base + STM32_HRTIM_CMN_OFFSET + offset); +} + +/**************************************************************************** + * Name: hrtim__modifyreg + * + * Description: + * Modify the value of an HRTIM register (not atomic). + * + * Input Parameters: + * priv - A reference to the HRTIM block + * offset - The offset to the register to modify + * clrbits - The bits to clear + * setbits - The bits to set + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_HRTIM_BURST +static void hrtim_cmn_modifyreg(struct stm32_hrtim_s *priv, + uint32_t offset, uint32_t clrbits, + uint32_t setbits) +{ + hrtim_cmn_putreg(priv, offset, + (hrtim_cmn_getreg(priv, offset) & ~clrbits) | setbits); +} +#endif + +/**************************************************************************** + * Name: hrtim_tim_get + * + * Description: + * Get Timer data structure for given HRTIM Timer index + * + * Input Parameters: + * priv - A reference to the HRTIM block + * timer - An HRTIM Timer index to get + * + * Returned Value: + * Pointer to timer structure on success, NULL on failure + * + ****************************************************************************/ + +static struct stm32_hrtim_tim_s * +hrtim_tim_get(struct stm32_hrtim_s *priv, uint8_t timer) +{ + struct stm32_hrtim_tim_s *tim; + + switch (timer) + { + case HRTIM_TIMER_MASTER: + { + tim = priv->master; + break; + } + +#ifdef CONFIG_STM32_HRTIM_TIMA + case HRTIM_TIMER_TIMA: + { + tim = priv->tima; + break; + } +#endif + +#ifdef CONFIG_STM32_HRTIM_TIMB + case HRTIM_TIMER_TIMB: + { + tim = priv->timb; + break; + } +#endif + +#ifdef CONFIG_STM32_HRTIM_TIMC + case HRTIM_TIMER_TIMC: + { + tim = priv->timc; + break; + } +#endif + +#ifdef CONFIG_STM32_HRTIM_TIMD + case HRTIM_TIMER_TIMD: + { + tim = priv->timd; + break; + } +#endif + +#ifdef CONFIG_STM32_HRTIM_TIME + case HRTIM_TIMER_TIME: + { + tim = priv->time; + break; + } +#endif + + default: + { + tmrerr("ERROR: No such timer index: %d\n", timer); + tim = NULL; + } + } + + return tim; +} + +/**************************************************************************** + * Name: hrtim_slave_get + * + * Description: + * Get Slave private data structure for given HRTIM Timer index + * + * Input Parameters: + * priv - A reference to the HRTIM block + * timer - An HRTIM Slave Timer index to get + * + * Returned Value: + * Pointer to slave structure success, NULL on failure + * + ****************************************************************************/ + +#if defined(CONFIG_STM32_HRTIM_PWM) || defined(CONFIG_STM32_HRTIM_FAULTS) +static struct stm32_hrtim_slave_priv_s * +hrtim_slave_get(struct stm32_hrtim_s *priv, uint8_t timer) +{ + struct stm32_hrtim_tim_s *tim; + struct stm32_hrtim_slave_priv_s *slave; + + /* Sanity checking */ + + if (timer == HRTIM_TIMER_MASTER || timer == HRTIM_TIMER_COMMON) + { + slave = NULL; + goto errout; + } + + /* Get Timer data structure */ + + tim = hrtim_tim_get(priv, timer); + if (tim == NULL) + { + slave = NULL; + goto errout; + } + + /* Get Slave Timer data */ + + slave = (struct stm32_hrtim_slave_priv_s *)tim->priv; + +errout: + return slave; +} +#endif + +/**************************************************************************** + * Name: hrtim_base_get + * + * Description: + * Get base address offset for given HRTIM Timer index + * + * Input Parameters: + * priv - A reference to the HRTIM block + * timer - An HRTIM Timer index to get + * + * Returned Value: + * Base address offset for given Timer index + * + ****************************************************************************/ + +static uint32_t hrtim_base_get(struct stm32_hrtim_s *priv, uint8_t timer) +{ + struct stm32_hrtim_tim_s *tim; + uint32_t base = 0; + + tim = hrtim_tim_get(priv, timer); + if (tim == NULL) + { + base = 0; + goto errout; + } + + base = tim->tim.base; + +errout: + return base; +} + +/**************************************************************************** + * Name: hrtim_tim_getreg + * + * Description: + * Read the value of an HRTIM Timer register. + * + * Input Parameters: + * priv - A reference to the HRTIM block + * tim - An HRTIM timer index + * offset - The offset to the register to read + * + * Returned Value: + * The current contents of the specified register + * + ****************************************************************************/ + +static uint32_t hrtim_tim_getreg(struct stm32_hrtim_s *priv, + uint8_t timer, uint32_t offset) +{ + uint32_t base = 0; + + base = hrtim_base_get(priv, timer); + if (base < 0) + { + return 0; + } + + return getreg32(base + offset); +} + +/**************************************************************************** + * Name: hrtim_tim_putreg + * + * Description: + * Write a value to an HRTIM Timer register. + * + * Input Parameters: + * priv - A reference to the HRTIM block + * timer - An HRTIM Timer index + * offset - The offset to the register to write to + * value - The value to write to the register + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void hrtim_tim_putreg(struct stm32_hrtim_s *priv, uint8_t timer, + uint32_t offset, uint32_t value) +{ + uint32_t base = 0; + + base = hrtim_base_get(priv, timer); + if (base > 0) + { + putreg32(value, base + offset); + } +} + +/**************************************************************************** + * Name: hrtim_tim_modifyreg + * + * Description: + * Modify the value of an HRTIM Timer register (not atomic). + * + * Input Parameters: + * priv - A reference to the HRTIM block + * timer - An HRTIM Timer index + * offset - The offset to the register to modify + * clrbits - The bits to clear + * setbits - The bits to set + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void hrtim_tim_modifyreg(struct stm32_hrtim_s *priv, + uint8_t timer, uint32_t offset, + uint32_t clrbits, uint32_t setbits) +{ + hrtim_tim_putreg(priv, timer, offset, + (hrtim_tim_getreg(priv, timer, offset) & ~clrbits) | + setbits); +} + +#ifdef CONFIG_DEBUG_TIMER_INFO +static void hrtim_dumpregs(struct stm32_hrtim_s *priv, uint8_t timer, + const char *msg) +{ + tmrinfo("%s:\n", msg); + + switch (timer) + { + case HRTIM_TIMER_MASTER: + { + tmrinfo("\tCR:\t0x%08" PRIx32 "\tISR:\t0x%08" PRIx32 + "\tICR:\t0x%08" PRIx32 "\n", + hrtim_tim_getreg(priv, timer, STM32_HRTIM_TIM_CR_OFFSET), + hrtim_tim_getreg(priv, timer, STM32_HRTIM_TIM_ISR_OFFSET), + hrtim_tim_getreg(priv, timer, STM32_HRTIM_TIM_ICR_OFFSET)); + + tmrinfo("\tDIER:\t0x%08" PRIx32 "\tCNTR:\t0x%08" PRIx32 + "\tPER:\t0x%08" PRIx32 "\n", + hrtim_tim_getreg(priv, timer, STM32_HRTIM_TIM_DIER_OFFSET), + hrtim_tim_getreg(priv, timer, STM32_HRTIM_TIM_CNTR_OFFSET), + hrtim_tim_getreg(priv, timer, STM32_HRTIM_TIM_PER_OFFSET)); + + tmrinfo("\tREP:\t0x%08" PRIx32 "\tCMP1:\t0x%08" PRIx32 + "\tCMP2:\t0x%08" PRIx32 "\n", + hrtim_tim_getreg(priv, timer, STM32_HRTIM_TIM_REPR_OFFSET), + hrtim_tim_getreg(priv, timer, + STM32_HRTIM_TIM_CMP1R_OFFSET), + hrtim_tim_getreg(priv, timer, + STM32_HRTIM_TIM_CMP2R_OFFSET)); + + tmrinfo("\tCMP3:\t0x%08" PRIx32 "\tCMP4:\t0x%08" PRIx32 "\n", + hrtim_tim_getreg(priv, timer, + STM32_HRTIM_TIM_CMP3R_OFFSET), + hrtim_tim_getreg(priv, timer, + STM32_HRTIM_TIM_CMP4R_OFFSET)); + break; + } + +#ifdef CONFIG_STM32_HRTIM_TIMA + case HRTIM_TIMER_TIMA: +#endif +#ifdef CONFIG_STM32_HRTIM_TIMB + case HRTIM_TIMER_TIMB: +#endif +#ifdef CONFIG_STM32_HRTIM_TIMC + case HRTIM_TIMER_TIMC: +#endif +#ifdef CONFIG_STM32_HRTIM_TIMD + case HRTIM_TIMER_TIMD: +#endif +#ifdef CONFIG_STM32_HRTIM_TIME + case HRTIM_TIMER_TIME: +#endif + { + tmrinfo("\tCR:\t0x%08" PRIx32 "\tISR:\t0x%08" PRIx32 + "\tICR:\t0x%08" PRIx32 "\n", + hrtim_tim_getreg(priv, timer, STM32_HRTIM_TIM_CR_OFFSET), + hrtim_tim_getreg(priv, timer, STM32_HRTIM_TIM_ISR_OFFSET), + hrtim_tim_getreg(priv, timer, STM32_HRTIM_TIM_ICR_OFFSET)); + + tmrinfo("\tDIER:\t0x%08" PRIx32 "\tCNTR:\t0x%08" PRIx32 + "\tPER:\t0x%08" PRIx32 "\n", + hrtim_tim_getreg(priv, timer, STM32_HRTIM_TIM_DIER_OFFSET), + hrtim_tim_getreg(priv, timer, STM32_HRTIM_TIM_CNTR_OFFSET), + hrtim_tim_getreg(priv, timer, STM32_HRTIM_TIM_PER_OFFSET)); + + tmrinfo("\tREP:\t0x%08" PRIx32 "\tCMP1:\t0x%08" PRIx32 + "\tCMP1C:\t0x%08" PRIx32 "\n", + hrtim_tim_getreg(priv, timer, STM32_HRTIM_TIM_REPR_OFFSET), + hrtim_tim_getreg(priv, timer, + STM32_HRTIM_TIM_CMP1R_OFFSET), + hrtim_tim_getreg(priv, timer, + STM32_HRTIM_TIM_CMP1CR_OFFSET)); + + tmrinfo("\tCMP2:\t0x%08" PRIx32 "\tCMP3:\t0x%08" PRIx32 + "\tCMP4:\t0x%08" PRIx32 "\n", + hrtim_tim_getreg(priv, timer, + STM32_HRTIM_TIM_CMP2R_OFFSET), + hrtim_tim_getreg(priv, timer, + STM32_HRTIM_TIM_CMP3R_OFFSET), + hrtim_tim_getreg(priv, timer, + STM32_HRTIM_TIM_CMP4R_OFFSET)); + + tmrinfo("\tCPT1:\t0x%08" PRIx32 "\tCPT2:\t0x%08" PRIx32 + "\tDTR:\t0x%08" PRIx32 "\n", + hrtim_tim_getreg(priv, timer, + STM32_HRTIM_TIM_CPT1R_OFFSET), + hrtim_tim_getreg(priv, timer, + STM32_HRTIM_TIM_CPT2R_OFFSET), + hrtim_tim_getreg(priv, timer, STM32_HRTIM_TIM_DTR_OFFSET)); + + tmrinfo("\tSET1:\t0x%08" PRIx32 "\tRST1:\t0x%08" PRIx32 + "\tSET2:\t0x%08" PRIx32 "\n", + hrtim_tim_getreg(priv, timer, + STM32_HRTIM_TIM_SET1R_OFFSET), + hrtim_tim_getreg(priv, timer, + STM32_HRTIM_TIM_RST1R_OFFSET), + hrtim_tim_getreg(priv, timer, + STM32_HRTIM_TIM_SET2R_OFFSET)); + + tmrinfo("\tRST2:\t0x%08" PRIx32 "\tEEF1:\t0x%08" PRIx32 + "\tEEF2:\t0x%08" PRIx32 "\n", + hrtim_tim_getreg(priv, timer, + STM32_HRTIM_TIM_RST2R_OFFSET), + hrtim_tim_getreg(priv, timer, + STM32_HRTIM_TIM_EEFR1_OFFSET), + hrtim_tim_getreg(priv, timer, + STM32_HRTIM_TIM_EEFR2_OFFSET)); + + tmrinfo("\tRSTR:\t0x%08" PRIx32 "\tCHPR:\t0x%08" PRIx32 + "\tCPT1C:\t0x%08" PRIx32 "\n", + hrtim_tim_getreg(priv, timer, STM32_HRTIM_TIM_RSTR_OFFSET), + hrtim_tim_getreg(priv, timer, STM32_HRTIM_TIM_CHPR_OFFSET), + hrtim_tim_getreg(priv, timer, + STM32_HRTIM_TIM_CPT1CR_OFFSET)); + + tmrinfo("\tCPT2C:\t0x%08" PRIx32 "\tOUT:\t0x%08" PRIx32 + "\tFLT:\t0x%08" PRIx32 "\n", + hrtim_tim_getreg(priv, timer, + STM32_HRTIM_TIM_CPT2CR_OFFSET), + hrtim_tim_getreg(priv, timer, STM32_HRTIM_TIM_OUTR_OFFSET), + hrtim_tim_getreg(priv, timer, + STM32_HRTIM_TIM_FLTR_OFFSET)); + + break; + } + + case HRTIM_TIMER_COMMON: + { + tmrinfo("\tCR1:\t0x%08" PRIx32 "\tCR2:\t0x%08" PRIx32 + "\tISR:\t0x%08" PRIx32 "\n", + hrtim_cmn_getreg(priv, STM32_HRTIM_CMN_CR1_OFFSET), + hrtim_cmn_getreg(priv, STM32_HRTIM_CMN_CR2_OFFSET), + hrtim_cmn_getreg(priv, STM32_HRTIM_CMN_ISR_OFFSET)); + + tmrinfo("\tICR:\t0x%08" PRIx32 "\tIER:\t0x%08" PRIx32 + "\tOENR:\t0x%08" PRIx32 "\n", + hrtim_cmn_getreg(priv, STM32_HRTIM_CMN_ICR_OFFSET), + hrtim_cmn_getreg(priv, STM32_HRTIM_CMN_IER_OFFSET), + hrtim_cmn_getreg(priv, STM32_HRTIM_CMN_OENR_OFFSET)); + + tmrinfo("\tODISR:\t0x%08" PRIx32 "\tODSR:\t0x%08" PRIx32 + "\tBMCR:\t0x%08" PRIx32 "\n", + hrtim_cmn_getreg(priv, STM32_HRTIM_CMN_ODISR_OFFSET), + hrtim_cmn_getreg(priv, STM32_HRTIM_CMN_ODSR_OFFSET), + hrtim_cmn_getreg(priv, STM32_HRTIM_CMN_BMCR_OFFSET)); + + tmrinfo("\tBMTRG:\t0x%08" PRIx32 "\tBMCMPR:\t0x%08" PRIx32 + "\tBMPER:\t0x%08" PRIx32 "\n", + hrtim_cmn_getreg(priv, STM32_HRTIM_CMN_BMTRGR_OFFSET), + hrtim_cmn_getreg(priv, STM32_HRTIM_CMN_BMCMPR_OFFSET), + hrtim_cmn_getreg(priv, STM32_HRTIM_CMN_BMPER_OFFSET)); + + tmrinfo("\tADC1R:\t0x%08" PRIx32 "\tADC2R:\t0x%08" PRIx32 + "\tADC3R:\t0x%08" PRIx32 "\n", + hrtim_cmn_getreg(priv, STM32_HRTIM_CMN_ADC1R_OFFSET), + hrtim_cmn_getreg(priv, STM32_HRTIM_CMN_ADC2R_OFFSET), + hrtim_cmn_getreg(priv, STM32_HRTIM_CMN_ADC3R_OFFSET)); + + tmrinfo("\tADC4R:\t0x%08" PRIx32 "\tDLLCR:\t0x%08" PRIx32 + "\tFLTIN1:\t0x%08" PRIx32 "\n", + hrtim_cmn_getreg(priv, STM32_HRTIM_CMN_ADC4R_OFFSET), + hrtim_cmn_getreg(priv, STM32_HRTIM_CMN_DLLCR_OFFSET), + hrtim_cmn_getreg(priv, STM32_HRTIM_CMN_FLTINR1_OFFSET)); + + tmrinfo("\tFLTIN2:\t0x%08" PRIx32 "\tBDMUPD:\t0x%08" PRIx32 + "\tBDTAUP:\t0x%08" PRIx32 "\n", + hrtim_cmn_getreg(priv, STM32_HRTIM_CMN_FLTINR2_OFFSET), + hrtim_cmn_getreg(priv, STM32_HRTIM_CMN_BDMUPDR_OFFSET), + hrtim_cmn_getreg(priv, STM32_HRTIM_CMN_BDTAUPR_OFFSET)); + + tmrinfo("\tBDTBUP: 0x%08" PRIx32 "\tBDTCUP:\t0x%08" PRIx32 + "\tBDTDUP:\t0x%08" PRIx32 "\n", + hrtim_cmn_getreg(priv, STM32_HRTIM_CMN_BDTBUPR_OFFSET), + hrtim_cmn_getreg(priv, STM32_HRTIM_CMN_BDTCUPR_OFFSET), + hrtim_cmn_getreg(priv, STM32_HRTIM_CMN_BDTDUPR_OFFSET)); + + tmrinfo("\tBDTEUP:\t0x%08" PRIx32 "\tBDMAD:\t0x%08" PRIx32 "\n", + hrtim_cmn_getreg(priv, STM32_HRTIM_CMN_BDTEUPR_OFFSET), + hrtim_cmn_getreg(priv, STM32_HRTIM_CMN_BDMADR_OFFSET)); + + break; + } + + default: + { + tmrerr("ERROR: No such timer index: %d\n", timer); + break; + } + } +} +#endif + +/**************************************************************************** + * Name: hrtim_dll_cal + * + * Description: + * Calibrate HRTIM DLL + * + * Input Parameters: + * priv - A reference to the HRTIM structure + * + * Returned Value: + * 0 on success, a negated errno value on failure + * + ****************************************************************************/ + +static int hrtim_dll_cal(struct stm32_hrtim_s *priv) +{ + uint32_t regval = 0; + +#ifdef CONFIG_STM32_HRTIM_PERIODIC_CAL + /* Configure calibration rate */ + + regval |= HRTIM_DLLCR_CAL_RATE; + + /* Enable Periodic calibration */ + + regval |= HRTIM_DLLCR_CALEN; + + /* CALEN must not be set simultaneously with CAL bit */ + + hrtim_cmn_putreg(priv, STM32_HRTIM_CMN_DLLCR_OFFSET, regval); +#endif + + /* DLL Calibration Start */ + + regval |= HRTIM_DLLCR_CAL; + + hrtim_cmn_putreg(priv, STM32_HRTIM_CMN_DLLCR_OFFSET, regval); + + while ((hrtim_cmn_getreg(priv, STM32_HRTIM_CMN_ISR_OFFSET) & + HRTIM_ISR_DLLRDY) == 0); + + return OK; +} + +/**************************************************************************** + * Name: hrtim_tim_clock_config + * + * Description: + * Configure HRTIM Timer clock + * + * Input Parameters: + * priv - A reference to the HRTIM structure + * timer - An HRTIM Timer index + * + * Returned Value: + * 0 on success, a negated errno value on failure + * + ****************************************************************************/ + +static int hrtim_tim_clock_config(struct stm32_hrtim_s *priv, + uint8_t timer, uint8_t pre) +{ + int ret = OK; + uint32_t regval = 0; + + regval = hrtim_tim_getreg(priv, timer, STM32_HRTIM_TIM_CR_OFFSET); + + switch (pre) + { + case HRTIM_PRESCALER_1: + { + regval |= HRTIM_CMNCR_CKPSC_NODIV; + break; + } + + case HRTIM_PRESCALER_2: + { + regval |= HRTIM_CMNCR_CKPSC_d2; + break; + } + + case HRTIM_PRESCALER_4: + { + regval |= HRTIM_CMNCR_CKPSC_d4; + break; + } + + case HRTIM_PRESCALER_8: + { + regval |= HRTIM_CMNCR_CKPSC_d8; + break; + } + + case HRTIM_PRESCALER_16: + { + regval |= HRTIM_CMNCR_CKPSC_d16; + break; + } + + case HRTIM_PRESCALER_32: + { + regval |= HRTIM_CMNCR_CKPSC_d32; + break; + } + + case HRTIM_PRESCALER_64: + { + regval |= HRTIM_CMNCR_CKPSC_d64; + break; + } + + case HRTIM_PRESCALER_128: + { + regval |= HRTIM_CMNCR_CKPSC_d128; + break; + } + + default: + { + tmrerr("ERROR: invalid prescaler value %d for timer %d\n", timer, + pre); + ret = -EINVAL; + goto errout; + } + } + + /* Write prescaler configuration */ + + hrtim_tim_putreg(priv, timer, STM32_HRTIM_TIM_CR_OFFSET, regval); + +errout: + return ret; +} + +/**************************************************************************** + * Name: hrtim_tim_clocks_config + * + * Description: + * Configure HRTIM Timers Clocks + * + * Input Parameters: + * priv - A reference to the HRTIM structure + * + * Returned Value: + * 0 on success, a negated errno value on failure + * + ****************************************************************************/ + +static int hrtim_tim_clocks_config(struct stm32_hrtim_s *priv) +{ + int ret = OK; + + /* Configure Master Timer clock */ + +#ifdef CONFIG_STM32_HRTIM_MASTER + ret = hrtim_tim_clock_config(priv, HRTIM_TIMER_MASTER, + HRTIM_MASTER_PRESCALER); + if (ret < 0) + { + goto errout; + } +#endif + + /* Configure Timer A clock */ + +#ifdef CONFIG_STM32_HRTIM_TIMA + ret = hrtim_tim_clock_config(priv, HRTIM_TIMER_TIMA, HRTIM_TIMA_PRESCALER); + if (ret < 0) + { + goto errout; + } +#endif + + /* Configure Timer B clock */ + +#ifdef CONFIG_STM32_HRTIM_TIMB + ret = hrtim_tim_clock_config(priv, HRTIM_TIMER_TIMB, HRTIM_TIMB_PRESCALER); + if (ret < 0) + { + goto errout; + } +#endif + + /* Configure Timer C clock */ + +#ifdef CONFIG_STM32_HRTIM_TIMC + ret = hrtim_tim_clock_config(priv, HRTIM_TIMER_TIMC, HRTIM_TIMC_PRESCALER); + if (ret < 0) + { + goto errout; + } +#endif + + /* Configure Timer D clock */ + +#ifdef CONFIG_STM32_HRTIM_TIMD + ret = hrtim_tim_clock_config(priv, HRTIM_TIMER_TIMD, HRTIM_TIMD_PRESCALER); + if (ret < 0) + { + goto errout; + } +#endif + + /* Configure Timer E clock */ + +#ifdef CONFIG_STM32_HRTIM_TIME + ret = hrtim_tim_clock_config(priv, HRTIM_TIMER_TIME, HRTIM_TIME_PRESCALER); + if (ret < 0) + { + goto errout; + } +#endif + +errout: + return ret; +} + +/**************************************************************************** + * Name: hrtim_gpios_config + * + * Description: + * Configure HRTIM GPIO + * + * Input Parameters: + * priv - A reference to the HRTIM structure + * + * Returned Value: + * 0 on success, a negated errno value on failure + * + ****************************************************************************/ + +#if defined(CONFIG_STM32_HRTIM_PWM) || defined(CONFIG_STM32_HRTIM_SYNC) +static int hrtim_gpios_config(struct stm32_hrtim_s *priv) +{ +#ifdef CONFIG_STM32_HRTIM_EVENTS + struct stm32_hrtim_eev_s *eev = priv->eev; +#endif +#ifdef CONFIG_STM32_HRTIM_FAULTS + struct stm32_hrtim_faults_s *flt = priv->flt; +#endif + + /* Configure Timer A Outputs */ + +#ifdef CONFIG_STM32_HRTIM_TIMA_PWM_CH1 + stm32_configgpio(GPIO_HRTIM1_CHA1); +#endif + +#ifdef CONFIG_STM32_HRTIM_TIMA_PWM_CH2 + stm32_configgpio(GPIO_HRTIM1_CHA2); +#endif + + /* Configure Timer B Outputs */ + +#ifdef CONFIG_STM32_HRTIM_TIMB_PWM_CH1 + stm32_configgpio(GPIO_HRTIM1_CHB1); +#endif + +#ifdef CONFIG_STM32_HRTIM_TIMB_PWM_CH2 + stm32_configgpio(GPIO_HRTIM1_CHB2); +#endif + + /* Configure Timer C Outputs */ + +#ifdef CONFIG_STM32_HRTIM_TIMC_PWM_CH1 + stm32_configgpio(GPIO_HRTIM1_CHC1); +#endif + +#ifdef CONFIG_STM32_HRTIM_TIMC_PWM_CH2 + stm32_configgpio(GPIO_HRTIM1_CHC2); +#endif + + /* Configure Timer D Outputs */ + +#ifdef CONFIG_STM32_HRTIM_TIMD_PWM_CH1 + stm32_configgpio(GPIO_HRTIM1_CHD1); +#endif + +#ifdef CONFIG_STM32_HRTIM_TIMD_PWM_CH2 + stm32_configgpio(GPIO_HRTIM1_CHD2); +#endif + + /* Configure Timer E Outputs */ + +#ifdef CONFIG_STM32_HRTIM_TIME_PWM_CH1 + stm32_configgpio(GPIO_HRTIM1_CHE1); +#endif + +#ifdef CONFIG_STM32_HRTIM_TIME_PWM_CH2 + stm32_configgpio(GPIO_HRTIM1_CHE2); +#endif + + /* Configure SCOUT */ + +#ifdef CONFIG_STM32_HRTIM_SCOUT + stm32_configgpio(GPIO_HRTIM1_SCOUT); +#endif + + /* Configure SCIN */ + +#ifdef CONFIG_STM32_HRTIM_SCIN + stm32_configgpio(GPIO_HRTIM1_SCIN); +#endif + + /* Configure Faults Inputs */ + +#ifdef CONFIG_STM32_HRTIM_FAULT1 + if (flt->flt1.src == HRTIM_FAULT_SRC_PIN) + { + stm32_configgpio(GPIO_HRTIM1_FLT1); + } +#endif + +#ifdef CONFIG_STM32_HRTIM_FAULT2 + if (flt->flt2.src == HRTIM_FAULT_SRC_PIN) + { + stm32_configgpio(GPIO_HRTIM1_FLT2); + } +#endif + +#ifdef CONFIG_STM32_HRTIM_FAULT3 + if (flt->flt3.src == HRTIM_FAULT_SRC_PIN) + { + stm32_configgpio(GPIO_HRTIM1_FLT3); + } +#endif + +#ifdef CONFIG_STM32_HRTIM_FAULT4 + if (flt->flt4.src == HRTIM_FAULT_SRC_PIN) + { + stm32_configgpio(GPIO_HRTIM1_FLT4); + } +#endif + +#ifdef CONFIG_STM32_HRTIM_FAULT5 + if (flt->flt5.src == HRTIM_FAULT_SRC_PIN) + { + stm32_configgpio(GPIO_HRTIM1_FLT5); + } +#endif + + /* Configure External Events Inputs */ + +#ifdef CONFIG_STM32_HRTIM_EEV1 + if (eev->eev1.src == HRTIM_EEV_SRC_PIN) + { + stm32_configgpio(GPIO_HRTIM1_EEV1); + } +#endif + +#ifdef CONFIG_STM32_HRTIM_EEV2 + if (eev->eev2.src == HRTIM_EEV_SRC_PIN) + { + stm32_configgpio(GPIO_HRTIM1_EEV2); + } +#endif + +#ifdef CONFIG_STM32_HRTIM_EEV3 + if (eev->eev3.src == HRTIM_EEV_SRC_PIN) + { + stm32_configgpio(GPIO_HRTIM1_EEV3); + } +#endif + +#ifdef CONFIG_STM32_HRTIM_EEV4 + if (eev->eev4.src == HRTIM_EEV_SRC_PIN) + { + stm32_configgpio(GPIO_HRTIM1_EEV4); + } +#endif + +#ifdef CONFIG_STM32_HRTIM_EEV5 + if (eev->eev5.src == HRTIM_EEV_SRC_PIN) + { + stm32_configgpio(GPIO_HRTIM1_EEV5); + } +#endif + +#ifdef CONFIG_STM32_HRTIM_EEV6 + if (eev->eev6.src == HRTIM_EEV_SRC_PIN) + { + stm32_configgpio(GPIO_HRTIM1_EEV6); + } +#endif + +#ifdef CONFIG_STM32_HRTIM_EEV7 + if (eev->eev7.src == HRTIM_EEV_SRC_PIN) + { + stm32_configgpio(GPIO_HRTIM1_EEV7); + } +#endif + +#ifdef CONFIG_STM32_HRTIM_EEV8 + if (eev->eev8.src == HRTIM_EEV_SRC_PIN) + { + stm32_configgpio(GPIO_HRTIM1_EEV8); + } +#endif + +#ifdef CONFIG_STM32_HRTIM_EEV9 + if (eev->eev9.src == HRTIM_EEV_SRC_PIN) + { + stm32_configgpio(GPIO_HRTIM1_EEV9); + } +#endif + +#ifdef CONFIG_STM32_HRTIM_EEV10 + if (eev->eev10.src == HRTIM_EEV_SRC_PIN) + { + stm32_configgpio(GPIO_HRTIM1_EEV10); + } +#endif + + return OK; +} +#endif + +#if defined(CONFIG_STM32_HRTIM_CAPTURE) + +/**************************************************************************** + * Name: hrtim_tim_capture_cfg + * + * Description: + * Configure HRTIM Captures + * + * Input Parameters: + * priv - A reference to the HRTIM block + * timer - HRTIM Timer index + * capture - capture triggers configuration + * + * Returned Value: + * 0 on success, a negated errno value on failure + * + ****************************************************************************/ + +static int hrtim_tim_capture_cfg(struct stm32_hrtim_s *priv, + uint8_t timer, uint8_t index, + uint32_t capture) +{ + int ret = OK; + uint32_t offset = 0; + + /* Sanity checking */ + + if (timer == HRTIM_TIMER_MASTER || timer == HRTIM_TIMER_COMMON) + { + ret = -EINVAL; + goto errout; + } + + switch (index) + { + case HRTIM_CAPTURE1: + { + offset = STM32_HRTIM_TIM_CPT1CR_OFFSET; + break; + } + + case HRTIM_CAPTURE2: + { + offset = STM32_HRTIM_TIM_CPT2CR_OFFSET; + break; + } + + default: + { + ret = -EINVAL; + goto errout; + } + } + + hrtim_tim_putreg(priv, timer, offset, capture); + +errout: + return ret; +} + +/**************************************************************************** + * Name: hrtim_capture_config + * + * Description: + * Configure HRTIM Captures + * + * Input Parameters: + * priv - A reference to the HRTIM block + * + * Returned Value: + * 0 on success, a negated errno value on failure + * + ****************************************************************************/ + +static int hrtim_capture_config(struct stm32_hrtim_s *priv) +{ + struct stm32_hrtim_slave_priv_s *slave; + +#ifdef CONFIG_STM32_HRTIM_TIMA_CAP + slave = (struct stm32_hrtim_slave_priv_s *)priv->tima->priv; + hrtim_tim_capture_cfg(priv, HRTIM_TIMER_TIMA, HRTIM_CAPTURE1, + slave->cap.cap1); + hrtim_tim_capture_cfg(priv, HRTIM_TIMER_TIMA, HRTIM_CAPTURE2, + slave->cap.cap2); +#endif + +#ifdef CONFIG_STM32_HRTIM_TIMB_CAP + slave = (struct stm32_hrtim_slave_priv_s *)priv->timb->priv; + hrtim_tim_capture_cfg(priv, HRTIM_TIMER_TIMB, HRTIM_CAPTURE1, + slave->cap.cap1); + hrtim_tim_capture_cfg(priv, HRTIM_TIMER_TIMB, HRTIM_CAPTURE2, + slave->cap.cap2); +#endif + +#ifdef CONFIG_STM32_HRTIM_TIMC_CAP + slave = (struct stm32_hrtim_slave_priv_s *)priv->timc->priv; + hrtim_tim_capture_cfg(priv, HRTIM_TIMER_TIMC, HRTIM_CAPTURE1, + slave->cap.cap1); + hrtim_tim_capture_cfg(priv, HRTIM_TIMER_TIMC, HRTIM_CAPTURE2, + slave->cap.cap2); +#endif + +#ifdef CONFIG_STM32_HRTIM_TIMD_CAP + slave = (struct stm32_hrtim_slave_priv_s *)priv->timd->priv; + hrtim_tim_capture_cfg(priv, HRTIM_TIMER_TIMD, HRTIM_CAPTURE1, + slave->cap.cap1); + hrtim_tim_capture_cfg(priv, HRTIM_TIMER_TIMD, HRTIM_CAPTURE2, + slave->cap.cap2); +#endif + +#ifdef CONFIG_STM32_HRTIM_TIME_CAP + slave = (struct stm32_hrtim_slave_priv_s *)priv->time->priv; + hrtim_tim_capture_cfg(priv, HRTIM_TIMER_TIME, HRTIM_CAPTURE1, + slave->cap.cap1); + hrtim_tim_capture_cfg(priv, HRTIM_TIMER_TIME, HRTIM_CAPTURE2, + slave->cap.cap2); +#endif + + return OK; +} + +/**************************************************************************** + * Name: hrtim_capture_get + * + * Description: + * Get HRTIM Timer Capture register + * + * Input Parameters: + * priv - A reference to the HRTIM block + * timer - HRTIM Timer index + * index - Capture register index + * + * Returned Value: + * Timer Capture value on success, 0 on failure + * + ****************************************************************************/ + +static uint16_t hrtim_capture_get(struct hrtim_dev_s *dev, uint8_t timer, + uint8_t index) +{ + struct stm32_hrtim_s *priv = (struct stm32_hrtim_s *)dev->hd_priv; + uint32_t regval = 0; + uint32_t offset = 0; + + switch (index) + { + case HRTIM_CAPTURE1: + { + offset = STM32_HRTIM_TIM_CPT1R_OFFSET; + break; + } + + case HRTIM_CAPTURE2: + { + offset = STM32_HRTIM_TIM_CPT2R_OFFSET; + break; + } + + default: + { + regval = 0; + goto errout; + } + } + + regval = (uint16_t)hrtim_tim_getreg(priv, timer, offset); + +errout: + return regval; +} + +/**************************************************************************** + * Name: hrtim_soft_capture + * + * Description: + * HRTIM Timer software capture tirgger. + * + * Input Parameters: + * dev - HRTIM device structure + * timer - HRTIM Timer indexes + * index - HRTIM capture index + * + * Returned Value: + * 0 on success; a negated errno value on failure + * + ****************************************************************************/ + +static int hrtim_soft_capture(struct hrtim_dev_s *dev, uint8_t timer, + uint8_t index) +{ + struct stm32_hrtim_s *priv = (struct stm32_hrtim_s *)dev->hd_priv; + uint32_t offset = 0; + + switch (index) + { + case HRTIM_CAPTURE1: + { + offset = STM32_HRTIM_TIM_CPT1CR_OFFSET; + break; + } + + case HRTIM_CAPTURE2: + { + offset = STM32_HRTIM_TIM_CPT2CR_OFFSET; + break; + } + + default: + { + goto errout; + } + } + + /* Modify register */ + + hrtim_tim_modifyreg(priv, timer, offset, 0, HRTIM_TIMCPT12CR_SWCPT); + +errout: + return OK; +} + +#endif + +/**************************************************************************** + * Name: hrtim_synch_config + * + * Description: + * Configure HRTIM Synchronization Input/Output + * + * Input Parameters: + * priv - A reference to the HRTIM structure + * + * Returned Value: + * 0 on success, a negated errno value on failure + * + ****************************************************************************/ + +#if defined(CONFIG_STM32_HRTIM_SYNC) +static int hrtim_synch_config(struct stm32_hrtim_s *priv) +{ +#warning "hrtim_synch_config: missing logic" + return OK; +} +#endif + +/**************************************************************************** + * Name: hrtim_tim_outputs_config + * + * Description: + * Configure HRTIM Slave Timer Outputs (CH1 and CH2) + * + * Input Parameters: + * priv - A reference to the HRTIM structure + * + * Returned Value: + * 0 on success, a negated errno value on failure + * + ****************************************************************************/ + +#if defined(CONFIG_STM32_HRTIM_PWM) +static int hrtim_tim_outputs_config(struct stm32_hrtim_s *priv, + uint8_t timer) +{ + struct stm32_hrtim_slave_priv_s *slave; + uint32_t regval = 0; + int ret = OK; + + /* Get Slave Timer data structure */ + + slave = hrtim_slave_get(priv, timer); + if (slave == NULL) + { + ret = -EINVAL; + goto errout; + } + + /* Configure CH1 SET events */ + + regval = slave->pwm.ch1.set; + hrtim_tim_putreg(priv, timer, STM32_HRTIM_TIM_SET1R_OFFSET, regval); + + /* Configure CH1 RESET events */ + + regval = slave->pwm.ch1.rst; + hrtim_tim_putreg(priv, timer, STM32_HRTIM_TIM_RST1R_OFFSET, regval); + + /* Configure CH2 SET events */ + + regval = slave->pwm.ch2.set; + hrtim_tim_putreg(priv, timer, STM32_HRTIM_TIM_SET2R_OFFSET, regval); + + /* Configure CH2 RESET events */ + + regval = slave->pwm.ch2.rst; + hrtim_tim_putreg(priv, timer, STM32_HRTIM_TIM_RST2R_OFFSET, regval); + + /* Now we configure OUT register */ + + regval = 0; + +#ifdef CONFIG_STM32_HRTIM_BURST + /* Configure IDLE state for output 1 */ + + if (slave->pwm.burst.ch1_en) + { + /* Set IDLE mode */ + + regval |= HRTIM_TIMOUT_IDLEM1; + + /* Set Idle state */ + + regval |= ((slave->pwm.burst.ch1_state & HRTIM_IDLE_ACTIVE) ? + HRTIM_TIMOUT_IDLES1 : 0); + } + + /* Configure IDLE state for output 2 */ + + if (slave->pwm.burst.ch2_en) + { + /* Set IDLE mode */ + + regval |= HRTIM_TIMOUT_IDLEM1; + + /* Set Idle state */ + + regval |= ((slave->pwm.burst.ch2_state & HRTIM_IDLE_ACTIVE) ? + HRTIM_TIMOUT_IDLES1 : 0); + } +#endif + +#ifdef CONFIG_STM32_HRTIM_DEADTIME + if (slave->pwm.dt.en == 1) + { + /* Set deadtime enable */ + + regval |= HRTIM_TIMOUT_DTEN; + + /* TODO: deadtime upon burst mode Idle entry */ + } +#endif + + /* Configure Output 1 polarisation */ + + regval |= ((slave->pwm.ch1.pol & HRTIM_OUT_POL_NEG) ? + HRTIM_TIMOUT_POL1 : 0); + + /* Configure Output 2 polarisation */ + + regval |= ((slave->pwm.ch2.pol & HRTIM_OUT_POL_NEG) ? + HRTIM_TIMOUT_POL2 : 0); + + /* Write HRTIM Slave Timer Output register */ + + hrtim_tim_modifyreg(priv, timer, STM32_HRTIM_TIM_OUTR_OFFSET, 0, regval); + +#ifdef CONFIG_STM32_HRTIM_PUSHPULL + if (slave->pwm.pushpull == 1) + { + /* Enable push-pull mode */ + + hrtim_tim_modifyreg(priv, timer, STM32_HRTIM_TIM_CR_OFFSET, 0, + HRTIM_TIMCR_PSHPLL); + } +#endif + +errout: + return ret; +} +#endif + +/**************************************************************************** + * Name: hrtim_outputs_config + * + * Description: + * Configure HRTIM Outputs + * + * Input Parameters: + * priv - A reference to the HRTIM structure + * + * Returned Value: + * 0 on success, a negated errno value on failure + * + ****************************************************************************/ + +#if defined(CONFIG_STM32_HRTIM_PWM) +static int hrtim_outputs_config(struct stm32_hrtim_s *priv) +{ + int ret = OK; + + /* Configure HRTIM TIMER A Outputs */ + +#ifdef CONFIG_STM32_HRTIM_TIMA_PWM + ret = hrtim_tim_outputs_config(priv, HRTIM_TIMER_TIMA); + if (ret < 0) + { + goto errout; + } +#endif + + /* Configure HRTIM TIMER B Outputs */ + +#ifdef CONFIG_STM32_HRTIM_TIMB_PWM + ret = hrtim_tim_outputs_config(priv, HRTIM_TIMER_TIMB); + if (ret < 0) + { + goto errout; + } +#endif + + /* Configure HRTIM TIMER C Outputs */ + +#ifdef CONFIG_STM32_HRTIM_TIMC_PWM + ret = hrtim_tim_outputs_config(priv, HRTIM_TIMER_TIMC); + if (ret < 0) + { + goto errout; + } +#endif + + /* Configure HRTIM TIMER D Outputs */ + +#ifdef CONFIG_STM32_HRTIM_TIMD_PWM + ret = hrtim_tim_outputs_config(priv, HRTIM_TIMER_TIMD); + if (ret < 0) + { + goto errout; + } +#endif + + /* Configure HRTIM TIMER E Outputs */ + +#ifdef CONFIG_STM32_HRTIM_TIME_PWM + ret = hrtim_tim_outputs_config(priv, HRTIM_TIMER_TIME); + if (ret < 0) + { + goto errout; + } +#endif + +errout: + return ret; +} + +/**************************************************************************** + * Name: hrtim_outputs_enable + * + * Description: + * Enable/disable HRTIM outputs (bulk operation) + * + * Input Parameters: + * dev - HRTIM device structure + * outputs - outputs to set + * state - Enable/disable operation + * + * Returned Value: + * 0 on success, a negated errno value on failure + * + ****************************************************************************/ + +static int hrtim_outputs_enable(struct hrtim_dev_s *dev, + uint16_t outputs, bool state) +{ + struct stm32_hrtim_s *priv = (struct stm32_hrtim_s *)dev->hd_priv; + uint32_t offset = 0; + + /* Get register offset */ + + if (state == true) + { + offset = STM32_HRTIM_CMN_OENR_OFFSET; + } + else + { + offset = STM32_HRTIM_CMN_ODISR_OFFSET; + } + + /* Write register */ + + hrtim_cmn_putreg(priv, offset, outputs); + + return OK; +} + +/**************************************************************************** + * Name: output_tim_index_get + ****************************************************************************/ + +static uint8_t output_tim_index_get(uint16_t output) +{ + uint8_t timer = 0; + + switch (output) + { +#ifdef CONFIG_STM32_HRTIM_TIMA + case HRTIM_OUT_TIMA_CH1: + case HRTIM_OUT_TIMA_CH2: + { + timer = HRTIM_TIMER_TIMA; + break; + } +#endif + +#ifdef CONFIG_STM32_HRTIM_TIMB + case HRTIM_OUT_TIMB_CH1: + case HRTIM_OUT_TIMB_CH2: + { + timer = HRTIM_TIMER_TIMB; + break; + } +#endif + +#ifdef CONFIG_STM32_HRTIM_TIMC + case HRTIM_OUT_TIMC_CH1: + case HRTIM_OUT_TIMC_CH2: + { + timer = HRTIM_TIMER_TIMC; + break; + } +#endif + +#ifdef CONFIG_STM32_HRTIM_TIMD + case HRTIM_OUT_TIMD_CH1: + case HRTIM_OUT_TIMD_CH2: + { + timer = HRTIM_TIMER_TIMD; + break; + } +#endif + +#ifdef CONFIG_STM32_HRTIM_TIME + case HRTIM_OUT_TIME_CH1: + case HRTIM_OUT_TIME_CH2: + { + timer = HRTIM_TIMER_TIME; + break; + } +#endif + + default: + { + timer = 0; + break; + } + } + + return timer; +} + +/**************************************************************************** + * Name: output_tim_ch_get + ****************************************************************************/ + +static uint8_t output_tim_ch_get(uint16_t output) +{ + uint8_t ch = 0; + + switch (output) + { +#ifdef CONFIG_STM32_HRTIM_TIMA + case HRTIM_OUT_TIMA_CH1: +#endif +#ifdef CONFIG_STM32_HRTIM_TIMB + case HRTIM_OUT_TIMB_CH1: +#endif +#ifdef CONFIG_STM32_HRTIM_TIMC + case HRTIM_OUT_TIMC_CH1: +#endif +#ifdef CONFIG_STM32_HRTIM_TIMD + case HRTIM_OUT_TIMD_CH1: +#endif +#ifdef CONFIG_STM32_HRTIM_TIME + case HRTIM_OUT_TIME_CH1: +#endif + { + ch = HRTIM_OUT_CH1; + break; + } + +#ifdef CONFIG_STM32_HRTIM_TIMA + case HRTIM_OUT_TIMA_CH2: +#endif +#ifdef CONFIG_STM32_HRTIM_TIMB + case HRTIM_OUT_TIMB_CH2: +#endif +#ifdef CONFIG_STM32_HRTIM_TIMC + case HRTIM_OUT_TIMC_CH2: +#endif +#ifdef CONFIG_STM32_HRTIM_TIMD + case HRTIM_OUT_TIMD_CH2: +#endif +#ifdef CONFIG_STM32_HRTIM_TIME + case HRTIM_OUT_TIME_CH2: +#endif + { + ch = HRTIM_OUT_CH2; + break; + } + + default: + { + ch = 0; + break; + } + } + + return ch; +} + +/**************************************************************************** + * Name: hrtim_output_set_set + ****************************************************************************/ + +static int hrtim_output_set_set(struct hrtim_dev_s *dev, uint16_t output, + uint32_t set) +{ + struct stm32_hrtim_s *priv = (struct stm32_hrtim_s *)dev->hd_priv; + struct stm32_hrtim_slave_priv_s *slave; + uint8_t timer = 0; + int ret = OK; + + /* Get timer index from output */ + + timer = output_tim_index_get(output); + + /* Get Slave Timer data structure */ + + slave = hrtim_slave_get(priv, timer); + if (slave == NULL) + { + ret = -EINVAL; + goto errout; + } + + /* Set new SET value */ + + switch (output_tim_ch_get(output)) + { + case HRTIM_OUT_CH1: + { + slave->pwm.ch1.set = set; + hrtim_tim_putreg(priv, timer, STM32_HRTIM_TIM_SET1R_OFFSET, set); + break; + } + + case HRTIM_OUT_CH2: + { + slave->pwm.ch2.set = set; + hrtim_tim_putreg(priv, timer, STM32_HRTIM_TIM_SET2R_OFFSET, set); + break; + } + + default: + { + ret = -EINVAL; + goto errout; + } + } + +errout: + return ret; +} + +/**************************************************************************** + * Name: hrtim_output_rst_set + ****************************************************************************/ + +static int hrtim_output_rst_set(struct hrtim_dev_s *dev, uint16_t output, + uint32_t rst) +{ + struct stm32_hrtim_s *priv = (struct stm32_hrtim_s *)dev->hd_priv; + struct stm32_hrtim_slave_priv_s *slave; + uint8_t timer = 0; + int ret = OK; + + /* Get timer index from output */ + + timer = output_tim_index_get(output); + + /* Get Salve Timer data structure */ + + slave = hrtim_slave_get(priv, timer); + if (slave == NULL) + { + ret = -EINVAL; + goto errout; + } + + /* Set new RST value */ + + switch (output_tim_ch_get(output)) + { + case HRTIM_OUT_CH1: + { + slave->pwm.ch1.rst = rst; + hrtim_tim_putreg(priv, timer, STM32_HRTIM_TIM_RST1R_OFFSET, rst); + } + + case HRTIM_OUT_CH2: + { + slave->pwm.ch2.rst = rst; + hrtim_tim_putreg(priv, timer, STM32_HRTIM_TIM_RST2R_OFFSET, rst); + } + + default: + { + ret = -EINVAL; + goto errout; + } + } + +errout: + return ret; +} + +#endif + +/**************************************************************************** + * Name: hrtim_adc_config + * + * Description: + * Configure HRTIM ADC triggers + * + * Input Parameters: + * priv - A reference to the HRTIM structure + * + * Returned Value: + * 0 on success, a negated errno value on failure + * + ****************************************************************************/ + +#ifdef HRTIM_HAVE_ADC +static int hrtim_adc_config(struct stm32_hrtim_s *priv) +{ + /* Configure ADC Trigger 1 */ + +#ifdef HRTIM_HAVE_ADC_TRG1 + hrtim_cmn_putreg(priv, STM32_HRTIM_CMN_ADC1R_OFFSET, priv->adc->trg1); +#endif + + /* Configure ADC Trigger 2 */ + +#ifdef HRTIM_HAVE_ADC_TRG2 + hrtim_cmn_putreg(priv, STM32_HRTIM_CMN_ADC2R_OFFSET, priv->adc->trg2); +#endif + + /* Configure ADC Trigger 3 */ + +#ifdef HRTIM_HAVE_ADC_TRG3 + hrtim_cmn_putreg(priv, STM32_HRTIM_CMN_ADC3R_OFFSET, priv->adc->trg3); +#endif + + /* Configure ADC Trigger 4 */ + +#ifdef HRTIM_HAVE_ADC_TRG4 + hrtim_cmn_putreg(priv, STM32_HRTIM_CMN_ADC4R_OFFSET, priv->adc->trg4); +#endif + + return OK; +} +#endif + +#ifdef CONFIG_STM32_HRTIM_DAC +/**************************************************************************** + * Name: hrtim_tim_dac_cfg + * + * Description: + * Configure single HRTIM Timer DAC synchronization event + * + * Input Parameters: + * priv - A reference to the HRTIM structure + * timer - Timer index + * dac - DAC synchronisation event configuration + * + * Returned Value: + * 0 on success, a negated errno value on failure + * + ****************************************************************************/ + +static int hrtim_tim_dac_cfg(struct stm32_hrtim_s *priv, uint8_t timer, + uint8_t dac) +{ + struct stm32_hrtim_tim_s *tim; + uint32_t regval = 0; + + tim = hrtim_tim_get(priv, timer); + + regval = hrtim_tim_getreg(priv, timer, STM32_HRTIM_TIM_CR_OFFSET); + + regval |= (dac << HRTIM_CMNCR_DACSYNC_SHIFT); + + hrtim_tim_putreg(priv, timer, STM32_HRTIM_TIM_CR_OFFSET, regval); + + return OK; +} + +/**************************************************************************** + * Name: hrtim_dac_config + * + * Description: + * Configure HRTIM DAC synchronization + * + * Input Parameters: + * priv - A reference to the HRTIM structure + * + * Returned Value: + * 0 on success, a negated errno value on failure + * + ****************************************************************************/ + +static int hrtim_dac_config(struct stm32_hrtim_s *priv) +{ + struct stm32_hrtim_timcmn_s *tim; + + /* Configure DAC synchronization for Master Timer */ + +#ifdef CONFIG_STM32_HRTIM_MASTER_DAC + tim = (struct stm32_hrtim_timcmn_s *)priv->master; + hrtim_tim_dac_cfg(priv, HRTIM_TIMER_MASTER, tim->dac); +#endif + + /* Configure DAC synchronization for Timer A */ + +#ifdef CONFIG_STM32_HRTIM_TIMA_DAC + tim = (struct stm32_hrtim_timcmn_s *)priv->tima; + hrtim_tim_dac_cfg(priv, HRTIM_TIMER_TIMA, tim->dac); +#endif + + /* Configure DAC synchronization for Timer B */ + +#ifdef CONFIG_STM32_HRTIM_TIMB_DAC + tim = (struct stm32_hrtim_timcmn_s *)priv->timb; + hrtim_tim_dac_cfg(priv, HRTIM_TIMER_TIMB, tim->dac); +#endif + + /* Configure DAC synchronization for Timer C */ + +#ifdef CONFIG_STM32_HRTIM_TIMC_DAC + tim = (struct stm32_hrtim_timcmn_s *)priv->timc; + hrtim_tim_dac_cfg(priv, HRTIM_TIMER_TIMC, tim->dac); +#endif + + /* Configure DAC synchronization for Timer D */ + +#ifdef CONFIG_STM32_HRTIM_TIMD_DAC + tim = (struct stm32_hrtim_timcmn_s *)priv->timd; + hrtim_tim_dac_cfg(priv, HRTIM_TIMER_TIMD, tim->dac); +#endif + + /* Configure DAC synchronization for Timer E */ + +#ifdef CONFIG_STM32_HRTIM_TIME_DAC + tim = (struct stm32_hrtim_timcmn_s *)priv->time; + hrtim_tim_dac_cfg(priv, HRTIM_TIMER_TIME, tim->dac); +#endif + + return OK; +} +#endif + +#ifdef CONFIG_STM32_HRTIM_DMA +/**************************************************************************** + * Name: hrtim_dma_cfg + ****************************************************************************/ + +static int hrtim_tim_dma_cfg(struct stm32_hrtim_s *priv, uint8_t timer, + uint16_t dma) +{ + int ret = OK; + uint32_t regval = 0; + + /* Sanity checking */ + + if (timer == HRTIM_TIMER_COMMON) + { + ret = -EINVAL; + goto errout; + } + + if (timer == HRTIM_TIMER_MASTER) + { + /* Master support first 7 DMA requests */ + + if (dma > 0x7f) + { + tmrerr("ERROR: invalid DMA requests 0x%04X for timer %d\n", dma, + timer); + ret = -EINVAL; + goto errout; + } + } + else + { + if (dma & HRTIM_DMA_SYNC) + { + tmrerr("ERROR: timer %d does not support 0x%04X DMA request\n", + timer, HRTIM_DMA_SYNC); + ret = -EINVAL; + goto errout; + } + } + + /* DMA configuration occupies upper half of the DIER register */ + + regval = dma << 16; + + hrtim_tim_putreg(priv, timer, STM32_HRTIM_TIM_DIER_OFFSET, regval); + +errout: + return ret; +} + +/**************************************************************************** + * Name: hrtim_dma_cfg + ****************************************************************************/ + +static int hrtim_dma_cfg(struct stm32_hrtim_s *priv) +{ +#ifdef CONFIG_STM32_HRTIM_MASTER_DMA + hrtim_tim_dma_cfg(priv, HRTIM_TIMER_MASTER, priv->master->tim.dma); +#endif + +#ifdef CONFIG_STM32_HRTIM_TIMA_DMA + hrtim_tim_dma_cfg(priv, HRTIM_TIMER_TIMA, priv->tima->tim.dma); +#endif + +#ifdef CONFIG_STM32_HRTIM_TIMB_DMA + hrtim_tim_dma_cfg(priv, HRTIM_TIMER_TIMB, priv->timb->tim.dma); +#endif + +#ifdef CONFIG_STM32_HRTIM_TIMC_DMA + hrtim_tim_dma_cfg(priv, HRTIM_TIMER_TIMC, priv->timc->tim.dma); +#endif + +#ifdef CONFIG_STM32_HRTIM_TIMD_DMA + hrtim_tim_dma_cfg(priv, HRTIM_TIMER_TIMD, priv->timd->tim.dma); +#endif + +#ifdef CONFIG_STM32_HRTIM_TIME_DMA + hrtim_tim_dma_cfg(priv, HRTIM_TIMER_TIME, priv->time->tim.dma); +#endif + + return OK; +} +#endif /* CONFIG_STM32_HRTIM_DAM */ + +#ifdef CONFIG_STM32_HRTIM_DEADTIME +/**************************************************************************** + * Name: hrtim_deadtime_update + ****************************************************************************/ + +static int hrtim_deadtime_update(struct hrtim_dev_s *dev, uint8_t timer, + uint8_t dt, uint16_t value) +{ + struct stm32_hrtim_s *priv = (struct stm32_hrtim_s *)dev->hd_priv; + int ret = OK; + uint32_t regval = 0; + uint32_t shift = 0; + uint32_t mask = 0; + + /* For safety reasons we saturate deadtime value if it exceeds + * the acceptable range. + */ + + if (value > 0x1ff) + { + value = 0x1ff; + } + + /* Get shift value */ + + switch (dt) + { + case HRTIM_DT_EDGE_RISING: + { + shift = HRTIM_TIMDT_DTR_SHIFT; + mask = HRTIM_TIMDT_DTR_MASK; + break; + } + + case HRTIM_DT_EDGE_FALLING: + { + shift = HRTIM_TIMDT_DTF_SHIFT; + mask = HRTIM_TIMDT_DTF_MASK; + break; + } + + default: + { + ret = -EINVAL; + goto errout; + } + } + + regval = value << shift; + + /* Update register */ + + hrtim_tim_modifyreg(priv, timer, STM32_HRTIM_TIM_DTR_OFFSET, mask, regval); + +errout: + return ret; +} + +/**************************************************************************** + * Name: hrtim_deadtime_get + ****************************************************************************/ + +static uint16_t hrtim_deadtime_get(struct hrtim_dev_s *dev, + uint8_t timer, uint8_t dt) +{ + struct stm32_hrtim_s *priv = (struct stm32_hrtim_s *)dev->hd_priv; + uint16_t regval = 0; + uint32_t shift = 0; + uint32_t mask = 0; + + /* Get shift value */ + + switch (dt) + { + case HRTIM_DT_EDGE_RISING: + { + shift = HRTIM_TIMDT_DTR_SHIFT; + mask = HRTIM_TIMDT_DTR_MASK; + break; + } + + case HRTIM_DT_EDGE_FALLING: + { + shift = HRTIM_TIMDT_DTF_SHIFT; + mask = HRTIM_TIMDT_DTF_MASK; + break; + } + + default: + { + regval = 0; + goto errout; + } + } + + /* Get Deadtime Register */ + + regval = hrtim_tim_getreg(priv, timer, STM32_HRTIM_TIM_DTR_OFFSET); + + /* Get Deadtime value */ + + regval = (regval & mask) >> shift; + +errout: + return regval; +} + +/**************************************************************************** + * Name: hrtim_tim_deadtime_cfg + ****************************************************************************/ + +static int hrtim_tim_deadtime_cfg(struct stm32_hrtim_s *priv, + uint8_t timer) +{ + struct stm32_hrtim_slave_priv_s *slave; + uint32_t regval = 0; + int ret = OK; + + /* Sanity checking */ + + if (timer == HRTIM_TIMER_MASTER || timer == HRTIM_TIMER_COMMON) + { + ret = -EINVAL; + goto errout; + } + + /* Get Slave Timer data structure */ + + slave = hrtim_slave_get(priv, timer); + if (slave == NULL) + { + ret = -EINVAL; + goto errout; + } + + /* Configure deadtime prescaler */ + + regval |= slave->pwm.dt.prescaler << HRTIM_TIMDT_DTPRSC_SHIFT; + + /* Configure rising deadtime */ + + regval |= slave->pwm.dt.rising << HRTIM_TIMDT_DTR_SHIFT; + + /* Configure falling deadtime */ + + regval |= slave->pwm.dt.falling << HRTIM_TIMDT_DTF_SHIFT; + + /* Configure falling deadtime sign */ + + if (slave->pwm.dt.fsign == HRTIM_DT_SIGN_NEGATIVE) + { + regval |= HRTIM_TIMDT_SDTF; + } + + /* Configure risign deadtime sign */ + + if (slave->pwm.dt.rsign == HRTIM_DT_SIGN_NEGATIVE) + { + regval |= HRTIM_TIMDT_SDTR; + } + + /* Configure falling sing lock */ + + if (slave->pwm.dt.fsign_lock == HRTIM_DT_LOCK) + { + regval |= HRTIM_TIMDT_DTFSLK; + } + + /* Configure rising sing lock */ + + if (slave->pwm.dt.rsign_lock == HRTIM_DT_LOCK) + { + regval |= HRTIM_TIMDT_DTRSLK; + } + + /* Configure rising value lock */ + + if (slave->pwm.dt.rising_lock == HRTIM_DT_LOCK) + { + regval |= HRTIM_TIMDT_DTRLK; + } + + /* Configure falling value lock */ + + if (slave->pwm.dt.falling_lock == HRTIM_DT_LOCK) + { + regval |= HRTIM_TIMDT_DTFLK; + } + + /* TODO: configure default deadtime values */ + + /* Write register */ + + hrtim_tim_putreg(priv, timer, STM32_HRTIM_TIM_DTR_OFFSET, regval); + +errout: + return ret; +} + +/**************************************************************************** + * Name: hrtim_deadtime_config + ****************************************************************************/ + +static int hrtim_deadtime_config(struct stm32_hrtim_s *priv) +{ + /* Configure Timer A deadtime */ + +#ifdef CONFIG_STM32_HRTIM_TIMA_DT + hrtim_tim_deadtime_cfg(priv, HRTIM_TIMER_TIMA); +#endif + + /* Configure Timer B deadtime */ + +#ifdef CONFIG_STM32_HRTIM_TIMB_DT + hrtim_tim_deadtime_cfg(priv, HRTIM_TIMER_TIMB); +#endif + + /* Configure Timer C deadtime */ + +#ifdef CONFIG_STM32_HRTIM_TIMC_DT + hrtim_tim_deadtime_cfg(priv, HRTIM_TIMER_TIMC); +#endif + + /* Configure Timer D deadtime */ + +#ifdef CONFIG_STM32_HRTIM_TIMD_DT + hrtim_tim_deadtime_cfg(priv, HRTIM_TIMER_TIMD); +#endif + + /* Configure Timer E deadtime */ + +#ifdef CONFIG_STM32_HRTIM_TIME_DT + hrtim_tim_deadtime_cfg(priv, HRTIM_TIMER_TIME); +#endif + + return OK; +} +#endif /* CONFIG_STM32_HRTIM_DEADTIME */ + +#ifdef CONFIG_STM32_HRTIM_CHOPPER +/**************************************************************************** + * Name: hrtim_chopper_enable + * + * Description: + * Enable/disable HRTIM outputs (bulk operation) + * + * Input Parameters: + * dev - HRTIM device structure + * timer - An HRTIM Timer index + * chan - Output channel + * state - Enable/disable operation + * + * Returned Value: + * 0 on success, a negated errno value on failure + * + ****************************************************************************/ + +static int hrtim_chopper_enable(struct hrtim_dev_s *dev, uint8_t timer, + uint8_t chan, bool state) +{ + struct stm32_hrtim_s *priv = (struct stm32_hrtim_s *)dev->hd_priv; + uint32_t val = 0; + int ret = OK; + + /* Get bit to change */ + + switch (chan) + { + case HRTIM_OUT_CH1: + { + val = HRTIM_TIMOUT_CHP1; + break; + } + + case HRTIM_OUT_CH2: + { + val = HRTIM_TIMOUT_CHP2; + break; + } + + default: + { + ret = -EINVAL; + goto errout; + } + } + + /* Update register */ + + if (state == true) + { + /* Set enable bit */ + + hrtim_tim_modifyreg(priv, timer, STM32_HRTIM_TIM_OUTR_OFFSET, 0, val); + } + else + { + /* Clear enable bit */ + + hrtim_tim_modifyreg(priv, timer, STM32_HRTIM_TIM_OUTR_OFFSET, val, 0); + } + +errout: + return ret; +} + +/**************************************************************************** + * Name: hrtim_chopper_cfg + ****************************************************************************/ + +static int hrtim_tim_chopper_cfg(struct stm32_hrtim_s *priv, + uint8_t timer) +{ + struct stm32_hrtim_slave_priv_s *slave; + + int ret = OK; + uint32_t regval = 0; + + /* Sanity checking */ + + if (timer == HRTIM_TIMER_MASTER || timer == HRTIM_TIMER_COMMON) + { + ret = -EINVAL; + goto errout; + } + + /* Get Slave Timer data structure */ + + slave = hrtim_slave_get(priv, timer); + if (slave == NULL) + { + ret = -EINVAL; + goto errout; + } + + /* Configure start pulsewidth */ + + regval |= slave->pwm.chp.start_pulse << HRTIM_TIMCHP_STRTPW_SHIFT; + + /* Configure chopper duty cycle */ + + regval |= slave->pwm.chp.duty << HRTIM_TIMCHP_CARDTY_SHIFT; + + /* Configure carrier frequency */ + + regval |= slave->pwm.chp.freq << HRTIM_TIMCHP_CARFRQ_SHIFT; + + /* Write register */ + + hrtim_tim_putreg(priv, timer, STM32_HRTIM_TIM_CHPR_OFFSET, regval); + +errout: + return OK; +} + +/**************************************************************************** + * Name: hrtim_chopper_config + ****************************************************************************/ + +static int hrtim_chopper_config(struct stm32_hrtim_s *priv) +{ + /* Configure chopper for Timer A */ + +#ifdef CONFIG_STM32_HRTIM_TIMA_CHOP + hrtim_tim_chopper_cfg(priv, HRTIM_TIMER_TIMA); +#endif + + /* Configure chopper for Timer B */ + +#ifdef CONFIG_STM32_HRTIM_TIMB_CHOP + hrtim_tim_chopper_cfg(priv, HRTIM_TIMER_TIMB); +#endif + + /* Configure chopper for Timer C */ + +#ifdef CONFIG_STM32_HRTIM_TIMC_CHOP + hrtim_tim_chopper_cfg(priv, HRTIM_TIMER_TIMC); +#endif + + /* Configure chopper for Timer D */ + +#ifdef CONFIG_STM32_HRTIM_TIMD_CHOP + hrtim_tim_chopper_cfg(priv, HRTIM_TIMER_TIMD); +#endif + + /* Configure chopper for Timer E */ + +#ifdef CONFIG_STM32_HRTIM_TIME_CHOP + hrtim_tim_chopper_cfg(priv, HRTIM_TIMER_TIME); +#endif + + return OK; +} +#endif + +#ifdef CONFIG_STM32_HRTIM_BURST +/**************************************************************************** + * Name: hrtim_burst_enable + ****************************************************************************/ + +static int hrtim_burst_enable(struct hrtim_dev_s *dev, bool state) +{ + struct stm32_hrtim_s *priv = (struct stm32_hrtim_s *)dev->hd_priv; + + if (state) + { + /* Enable Burst mode */ + + hrtim_cmn_modifyreg(priv, STM32_HRTIM_CMN_BMCR_OFFSET, 0, + HRTIM_BMCR_BME); + + /* Software start */ + + hrtim_cmn_modifyreg(priv, STM32_HRTIM_CMN_BMTRGR_OFFSET, 0, + HRTIM_BMTRGR_SW); + } + else + { + /* Disable Burst mode */ + + hrtim_cmn_modifyreg(priv, STM32_HRTIM_CMN_BMCR_OFFSET, + HRTIM_BMCR_BME, 0); + } + + return OK; +} + +/**************************************************************************** + * Name: hrtim_burst_cmp_update + ****************************************************************************/ + +static int hrtim_burst_cmp_update(struct hrtim_dev_s *dev, uint16_t cmp) +{ + struct stm32_hrtim_s *priv = (struct stm32_hrtim_s *)dev->hd_priv; + + hrtim_cmn_putreg(priv, STM32_HRTIM_CMN_BMCMPR_OFFSET, cmp); + + return OK; +} + +/**************************************************************************** + * Name: hrtim_burst_per_update + ****************************************************************************/ + +static int hrtim_burst_per_update(struct hrtim_dev_s *dev, uint16_t per) +{ + struct stm32_hrtim_s *priv = (struct stm32_hrtim_s *)dev->hd_priv; + + hrtim_cmn_putreg(priv, STM32_HRTIM_CMN_BMPER_OFFSET, per); + + return OK; +} + +/**************************************************************************** + * Name: hrtim_burst_cmp_get + ****************************************************************************/ + +static uint16_t hrtim_burst_cmp_get(struct hrtim_dev_s *dev) +{ + struct stm32_hrtim_s *priv = (struct stm32_hrtim_s *)dev->hd_priv; + + return (uint16_t)hrtim_cmn_getreg(priv, STM32_HRTIM_CMN_BMCMPR_OFFSET); +} + +/**************************************************************************** + * Name: hrtim_burst_per_get + ****************************************************************************/ + +static uint16_t hrtim_burst_per_get(struct hrtim_dev_s *dev) +{ + struct stm32_hrtim_s *priv = (struct stm32_hrtim_s *)dev->hd_priv; + + return (uint16_t)hrtim_cmn_getreg(priv, STM32_HRTIM_CMN_BMPER_OFFSET); +} + +/**************************************************************************** + * Name: hrtim_burst_pre_update + ****************************************************************************/ + +static int hrtim_burst_pre_update(struct hrtim_dev_s *dev, uint8_t pre) +{ + struct stm32_hrtim_s *priv = (struct stm32_hrtim_s *)dev->hd_priv; + int ret = OK; + uint32_t regval = 0; + + /* Sanity checking */ + + if (priv->burst->clk != HRTIM_BURST_CLOCK_HRTIM) + { + ret = -EPERM; + goto errout; + } + + if (pre > HRTIM_BURST_PRESCALER_32768) + { + ret = -EINVAL; + goto errout; + } + + /* Make sure that Burst mode is disabled */ + + hrtim_burst_enable(dev, false); + + /* Change prescaler */ + + priv->burst->presc = pre; + regval = pre << HRTIM_BMCR_BMPRSC_SHIFT; + + hrtim_cmn_modifyreg(priv, STM32_HRTIM_CMN_BMCR_OFFSET, + HRTIM_BMCR_BMPRSC_MASK, regval); + +errout: + return ret; +} + +/**************************************************************************** + * Name: hrtim_burst_pre_get + ****************************************************************************/ + +static int hrtim_burst_pre_get(struct hrtim_dev_s *dev) +{ + struct stm32_hrtim_s *priv = (struct stm32_hrtim_s *)dev->hd_priv; + int ret = OK; + + if (priv->burst->clk != HRTIM_BURST_CLOCK_HRTIM) + { + ret = -EPERM; + goto errout; + } + + ret = priv->burst->presc; + +errout: + return ret; +} + +/**************************************************************************** + * Name: hrtim_burst_config + ****************************************************************************/ + +static int hrtim_burst_config(struct stm32_hrtim_s *priv) +{ + struct stm32_hrtim_burst_s *burst = priv->burst; + uint32_t regval = 0; + + /* Configure triggers */ + + regval = burst->trg; + + /* Write triggers register */ + + hrtim_cmn_putreg(priv, STM32_HRTIM_CMN_BMTRGR_OFFSET, regval); + + /* TODO: timers mode configuration */ + + regval = 0; + + /* Configure burst mode clock source */ + + regval |= (burst->clk << HRTIM_BMCR_BMCLK_SHIFT); + + /* Configure burst mode prescaler if f_HRTIM clock */ + + if (burst->clk == HRTIM_BURST_CLOCK_HRTIM) + { + regval |= (burst->presc << HRTIM_BMCR_BMPRSC_SHIFT); + } + + /* Set continuous mode */ + + regval |= HRTIM_BMCR_BMOM; + + /* Write Burst Mode CR */ + + hrtim_cmn_putreg(priv, STM32_HRTIM_CMN_BMCR_OFFSET, regval); + + return OK; +} +#endif + +#ifdef CONFIG_STM32_HRTIM_FAULTS +/**************************************************************************** + * Name: hrtim_tim_faults_cfg + * + * Description: + * Configure HRTIM Slave Timer faults sources. + * + * Input Parameters: + * priv - A reference to the HRTIM structure + * timer - timer index + * + * Returned Value: + * 0 on success, a negated errno value on failure + * + ****************************************************************************/ + +static int hrtim_tim_faults_cfg(struct stm32_hrtim_s *priv, + uint8_t timer) +{ + struct stm32_hrtim_slave_priv_s *slave; + uint32_t regval = 0; + int ret = OK; + + slave = hrtim_slave_get(priv, timer); + if (slave == NULL) + { + ret = -EINVAL; + goto errout; + } + + /* Get lock configuration */ + + regval = ((slave->flt & HRTIM_TIM_FAULT_LOCK) ? HRTIM_TIMFLT_FLTLCK : 0); + + /* Get sources configuration */ + + regval |= slave->flt & 0x1f; + + /* Write register */ + + hrtim_tim_putreg(priv, timer, STM32_HRTIM_TIM_FLTR_OFFSET, regval); + +errout: + return ret; +} + +/**************************************************************************** + * Name: hrtim_faults_config + * + * Description: + * Configure single HRTIM Fault + * + * Input Parameters: + * priv - A reference to the HRTIM structure + * index - Fault index + * + * Returned Value: + * 0 on success, a negated errno value on failure + * + ****************************************************************************/ + +static int hrtim_flt_cfg(struct stm32_hrtim_s *priv, uint8_t index) +{ + struct stm32_hrtim_fault_cfg_s *flt; + int ret = OK; + uint32_t regval = 0; + + /* Get fault configuration */ + + switch (index) + { +#ifdef CONFIG_STM32_HRTIM_FAULT1 + case 1: + { + flt = &priv->flt->flt1; + break; + } + +#endif +#ifdef CONFIG_STM32_HRTIM_FAULT2 + case 2: + { + flt = &priv->flt->flt2; + break; + } + +#endif +#ifdef CONFIG_STM32_HRTIM_FAULT3 + case 3: + { + flt = &priv->flt->flt3; + break; + } + +#endif +#ifdef CONFIG_STM32_HRTIM_FAULT4 + case 4: + { + flt = &priv->flt->flt4; + break; + } + +#endif +#ifdef CONFIG_STM32_HRTIM_FAULT5 + case 5: + { + flt = &priv->flt->flt5; + break; + } + +#endif + default: + { + ret = -EINVAL; + goto errout; + } + } + + /* Configure fault */ + + switch (index) + { + /* Fault 1-4 Configuration is located in first common fault register */ + + case 1: + case 2: + case 3: + case 4: + { + regval = hrtim_cmn_getreg(priv, STM32_HRTIM_CMN_FLTINR1_OFFSET); + + /* Configure polarity */ + + regval |= (((flt->pol & HRTIM_FAULT_POL_HIGH) ? + HRTIM_FLTINR1_FLT1P : 0) << (index - 1) * 8); + + /* Config source */ + + regval |= (((flt->src & HRTIM_FAULT_SRC_PIN) ? + HRTIM_FLTINR1_FLT1SRC : 0) << (index - 1) * 8); + + /* Config filter */ + + regval |= ((flt->filter << HRTIM_FLTINR1_FLT1F_SHIFT) << + (index - 1) * 8); + + /* Fault enable */ + + regval |= (HRTIM_FLTINR1_FLT1E << (index - 1) * 8); + + /* Write register */ + + hrtim_cmn_putreg(priv, STM32_HRTIM_CMN_FLTINR1_OFFSET, regval); + + break; + } + + /* Fault 5 configuration is located in second common fault + * register + */ + + case 5: + { + regval = hrtim_cmn_getreg(priv, STM32_HRTIM_CMN_FLTINR2_OFFSET); + + /* Configure polarity */ + + regval |= ((flt->pol & HRTIM_FAULT_POL_HIGH) ? + HRTIM_FLTINR2_FLT5P : 0); + + /* Config source */ + + regval |= ((flt->src & HRTIM_FAULT_SRC_PIN) ? + HRTIM_FLTINR2_FLT5SRC : 0); + + /* Config filter */ + + regval |= ((flt->filter << HRTIM_FLTINR2_FLT5F_SHIFT)); + + /* Fault enable */ + + regval |= HRTIM_FLTINR2_FLT5E; + + /* Write register */ + + hrtim_cmn_putreg(priv, STM32_HRTIM_CMN_FLTINR2_OFFSET, regval); + + break; + } + + default: + { + ret = -EINVAL; + goto errout; + } + } + +errout: + return ret; +} + +/**************************************************************************** + * Name: hrtim_faults_config + * + * Description: + * Configure HRTIM Faults + * + * Input Parameters: + * priv - A reference to the HRTIM structure + * + * Returned Value: + * 0 on success, a negated errno value on failure + * + ****************************************************************************/ + +static int hrtim_faults_config(struct stm32_hrtim_s *priv) +{ + uint32_t regval = 0; + + /* Configure faults */ + +#ifdef CONFIG_STM32_HRTIM_FAULT1 + hrtim_flt_cfg(priv, 1); +#endif + +#ifdef CONFIG_STM32_HRTIM_FAULT2 + hrtim_flt_cfg(priv, 2); +#endif + +#ifdef CONFIG_STM32_HRTIM_FAULT3 + hrtim_flt_cfg(priv, 3); +#endif + +#ifdef CONFIG_STM32_HRTIM_FAULT4 + hrtim_flt_cfg(priv, 4); +#endif + +#ifdef CONFIG_STM32_HRTIM_FAULT5 + hrtim_flt_cfg(priv, 5); +#endif + + /* Configure fault sources in Slave Timers */ + +#ifdef CONFIG_STM32_HRTIM_TIMA_FLT + hrtim_tim_faults_cfg(priv, HRTIM_TIMER_TIMA); +#endif + +#ifdef CONFIG_STM32_HRTIM_TIMB_FLT + hrtim_tim_faults_cfg(priv, HRTIM_TIMER_TIMA); +#endif + +#ifdef CONFIG_STM32_HRTIM_TIMC_FLT + hrtim_tim_faults_cfg(priv, HRTIM_TIMER_TIMA); +#endif + +#ifdef CONFIG_STM32_HRTIM_TIMD_FLT + hrtim_tim_faults_cfg(priv, HRTIM_TIMER_TIMA); +#endif + +#ifdef CONFIG_STM32_HRTIM_TIME_FLT + hrtim_tim_faults_cfg(priv, HRTIM_TIMER_TIMA); +#endif + + /* Configure fault sampling clock division */ + + regval = hrtim_cmn_getreg(priv, STM32_HRTIM_CMN_FLTINR2_OFFSET); + regval |= HRTIM_FAULT_SAMPLING << HRTIM_FLTINR1_FLT1F_SHIFT; + hrtim_cmn_putreg(priv, STM32_HRTIM_CMN_FLTINR2_OFFSET, regval); + + return OK; +} +#endif + +#ifdef CONFIG_STM32_HRTIM_EVENTS +/**************************************************************************** + * Name: hrtim_eev_cfg + * + * Description: + * Configure single HRTIM External Event + * + * Input Parameters: + * priv - A reference to the HRTIM structure + * index - External Event index + * + * Returned Value: + * 0 on success, a negated errno value on failure + * + ****************************************************************************/ + +static int hrtim_eev_cfg(struct stm32_hrtim_s *priv, uint8_t index) +{ + struct stm32_hrtim_eev_cfg_s *eev; + int ret = OK; + uint32_t regval = 0; + + /* Get External Event configuration */ + + switch (index) + { +#ifdef CONFIG_STM32_HRTIM_EEV1 + case 1: + { + eev = &priv->eev->eev1; + break; + } + +#endif +#ifdef CONFIG_STM32_HRTIM_EEV2 + case 2: + { + eev = &priv->eev->eev2; + break; + } + +#endif +#ifdef CONFIG_STM32_HRTIM_EEV3 + case 3: + { + eev = &priv->eev->eev3; + break; + } + +#endif +#ifdef CONFIG_STM32_HRTIM_EEV4 + case 4: + { + eev = &priv->eev->eev4; + break; + } + +#endif +#ifdef CONFIG_STM32_HRTIM_EEV5 + case 5: + { + eev = &priv->eev->eev5; + break; + } + +#endif +#ifdef CONFIG_STM32_HRTIM_EEV6 + case 6: + { + eev = &priv->eev->eev6; + break; + } + +#endif +#ifdef CONFIG_STM32_HRTIM_EEV7 + case 7: + { + eev = &priv->eev->eev7; + break; + } + +#endif +#ifdef CONFIG_STM32_HRTIM_EEV8 + case 8: + { + eev = &priv->eev->eev8; + break; + } + +#endif +#ifdef CONFIG_STM32_HRTIM_EEV8 + case 9: + { + eev = &priv->eev->eev9; + break; + } + +#endif +#ifdef CONFIG_STM32_HRTIM_EEV10 + case 10: + { + eev = &priv->eev->eev10; + break; + } + +#endif + default: + { + ret = -EINVAL; + goto errout; + } + } + + switch (index) + { + case 1: + case 2: + case 3: + case 4: + case 5: + case 6: + { + regval = hrtim_cmn_getreg(priv, STM32_HRTIM_CMN_EECR1_OFFSET); + + /* Configure source */ + + regval |= ((eev->src << HRTIM_EECR1_EE1SRC_SHIFT) << + (index - 1) * 6); + + /* Configure polarity */ + + regval |= ((eev->pol & HRTIM_FAULT_POL_HIGH ? + HRTIM_EECR1_EE1POL : 0) << (index - 1) * 6); + + /* Configure sensitivity */ + + regval |= (((eev->sen) << HRTIM_EECR1_EE1SNS_SHIFT) << + (index - 1) * 6); + + /* Configure mode */ + + regval |= (((eev->mode & HRTIM_EEV_MODE_FAST) ? + HRTIM_EECR1_EE1FAST : 0) << (index - 1) * 6); + + /* Write register */ + + hrtim_cmn_putreg(priv, STM32_HRTIM_CMN_EECR1_OFFSET, regval); + + break; + } + + case 7: + case 8: + case 9: + case 10: + { + regval = hrtim_cmn_getreg(priv, STM32_HRTIM_CMN_EECR2_OFFSET); + + /* Configure source */ + + regval |= ((eev->src << HRTIM_EECR2_EE6SRC_SHIFT) << + (index - 6) * 6); + + /* Configure polarity */ + + regval |= ((eev->pol & HRTIM_FAULT_POL_HIGH ? + HRTIM_EECR2_EE6POL : 0) << (index - 6) * 6); + + /* Configure sensitivity */ + + regval |= (((eev->sen) << HRTIM_EECR2_EE6SNS_SHIFT) << + (index - 6) * 6); + + /* Configure External Event filter, only EEV6-10 */ + + regval |= (((eev->filter) << HRTIM_EECR2_EE6SNS_SHIFT) << + (index - 6) * 6); + + /* Write register */ + + hrtim_cmn_putreg(priv, STM32_HRTIM_CMN_EECR2_OFFSET, regval); + + break; + } + + default: + { + ret = -EINVAL; + goto errout; + } + } + +errout: + return ret; +} + +/**************************************************************************** + * Name: hrtim_events_config + * + * Description: + * Configure HRTIM External Events + * + * Input Parameters: + * priv - A reference to the HRTIM structure + * + * Returned Value: + * 0 on success, a negated errno value on failure + * + ****************************************************************************/ + +static int hrtim_events_config(struct stm32_hrtim_s *priv) +{ + uint32_t regval = 0; + + /* Configure Events sources */ + +#ifdef CONFIG_STM32_HRTIM_EEV1 + hrtim_eev_cfg(priv, 1); +#endif + +#ifdef CONFIG_STM32_HRTIM_EEV2 + hrtim_eev_cfg(priv, 2); +#endif + +#ifdef CONFIG_STM32_HRTIM_EEV3 + hrtim_eev_cfg(priv, 3); +#endif + +#ifdef CONFIG_STM32_HRTIM_EEV4 + hrtim_eev_cfg(priv, 4); +#endif + +#ifdef CONFIG_STM32_HRTIM_EEV5 + hrtim_eev_cfg(priv, 5); +#endif + +#ifdef CONFIG_STM32_HRTIM_EEV6 + hrtim_eev_cfg(priv, 6); +#endif + +#ifdef CONFIG_STM32_HRTIM_EEV7 + hrtim_eev_cfg(priv, 7); +#endif + +#ifdef CONFIG_STM32_HRTIM_EEV8 + hrtim_eev_cfg(priv, 8); +#endif + +#ifdef CONFIG_STM32_HRTIM_EEV9 + hrtim_eev_cfg(priv, 9); +#endif + +#ifdef CONFIG_STM32_HRTIM_EEV10 + hrtim_eev_cfg(priv, 10); +#endif + + /* External Event Sampling clock */ + + regval = hrtim_cmn_getreg(priv, STM32_HRTIM_CMN_EECR3_OFFSET); + regval |= (HRTIM_EEV_SAMPLING << HRTIM_EECR3_EEVSD_SHIFT); + hrtim_cmn_putreg(priv, STM32_HRTIM_CMN_EECR3_OFFSET, regval); + + return OK; +} +#endif /* CONFIG_STM32_HRTIM_FAULTS */ + +#ifdef CONFIG_STM32_HRTIM_INTERRUPTS + +/**************************************************************************** + * Name: hrtim_irq_cfg + ****************************************************************************/ + +static int hrtim_irq_cfg(struct stm32_hrtim_s *priv, uint8_t timer, + uint16_t irq) +{ + int ret = OK; + + if (timer == HRTIM_TIMER_COMMON) + { + hrtim_cmn_putreg(priv, STM32_HRTIM_CMN_IER_OFFSET, irq); + } + else + { + hrtim_tim_putreg(priv, timer, STM32_HRTIM_TIM_DIER_OFFSET, irq); + } + + return ret; +} + +/**************************************************************************** + * Name: hrtim_irq_config + * + * Description: + * Configure HRTIM interrupts + * + * Input Parameters: + * priv - A reference to the HRTIM structure + * + * Returned Value: + * 0 on success, a negated errno value on failure + * + ****************************************************************************/ + +static int hrtim_irq_config(struct stm32_hrtim_s *priv) +{ +#ifdef CONFIG_STM32_HRTIM_MASTER_IRQ + hrtim_irq_cfg(priv, HRTIM_TIMER_MASTER, priv->master->tim.irq); +#endif + +#ifdef CONFIG_STM32_HRTIM_TIMA_IRQ + hrtim_irq_cfg(priv, HRTIM_TIMER_TIMA, priv->tima->tim.irq); +#endif + +#ifdef CONFIG_STM32_HRTIM_TIMB_IRQ + hrtim_irq_cfg(priv, HRTIM_TIMER_TIMB, priv->timb->tim.irq); +#endif + +#ifdef CONFIG_STM32_HRTIM_TIMB_IRQ + hrtim_irq_cfg(priv, HRTIM_TIMER_TIMB, priv->timc->tim.irq); +#endif + +#ifdef CONFIG_STM32_HRTIM_TIMB_IRQ + hrtim_irq_cfg(priv, HRTIM_TIMER_TIMB, priv->timd->tim.irq); +#endif + +#ifdef CONFIG_STM32_HRTIM_TIMB_IRQ + hrtim_irq_cfg(priv, HRTIM_TIMER_TIMB, priv->time->tim.irq); +#endif + +#ifdef CONFIG_STM32_HRTIM_COMMON_IRQ + hrtim_irq_cfg(priv, HRTIM_TIMER_COMMON, priv->irq); +#endif + + return OK; +} + +/**************************************************************************** + * Name: hrtim_irq_ack + ****************************************************************************/ + +static int hrtim_irq_ack(struct hrtim_dev_s *dev, uint8_t timer, + int source) +{ + struct stm32_hrtim_s *priv = (struct stm32_hrtim_s *)dev->hd_priv; + + if (timer == HRTIM_TIMER_COMMON) + { + /* Write to the HRTIM common clear interrupt register */ + + hrtim_cmn_putreg(priv, STM32_HRTIM_CMN_ICR_OFFSET, source); + } + else + { + /* Each timer has its own ICR register */ + + hrtim_tim_putreg(priv, timer, STM32_HRTIM_TIM_ICR_OFFSET, source); + } + + return OK; +} + +/**************************************************************************** + * Name: hrtim_irq_get + ****************************************************************************/ + +static uint16_t hrtim_irq_get(struct hrtim_dev_s *dev, uint8_t timer) +{ + struct stm32_hrtim_s *priv = (struct stm32_hrtim_s *)dev->hd_priv; + uint32_t regval = 0; + + if (timer == HRTIM_TIMER_COMMON) + { + /* Get HRTIM common status interrupt register */ + + regval = hrtim_cmn_getreg(priv, STM32_HRTIM_CMN_ISR_OFFSET); + } + else + { + /* Each timer has its own ISR register */ + + regval = hrtim_tim_getreg(priv, timer, STM32_HRTIM_TIM_ISR_OFFSET); + } + + return (uint16_t)regval; +} +#endif /* CONFIG_STM32_HRTIM_INTERRUPTS */ + +/**************************************************************************** + * Name: hrtim_tim_mode_set + * + * Description: + * Set HRTIM Timer mode + * + * Input Parameters: + * priv - A reference to the HRTIM block + * timer - HRTIM Timer index + * mode - Timer mode configuration + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void hrtim_tim_mode_set(struct stm32_hrtim_s *priv, uint8_t timer, + uint8_t mode) +{ + uint32_t regval = 0; + + regval = hrtim_tim_getreg(priv, timer, STM32_HRTIM_TIM_CR_OFFSET); + + /* Configure preload */ + + if (mode & HRTIM_MODE_PRELOAD) + { + regval |= HRTIM_CMNCR_PREEN; + } + + /* Configure half mode */ + + if (mode & HRTIM_MODE_HALF) + { + regval |= HRTIM_CMNCR_HALF; + } + + /* Configure re-triggerable mode */ + + if (mode & HRTIM_MODE_RETRIG) + { + regval |= HRTIM_CMNCR_RETRIG; + } + + /* Configure continuous mode */ + + if (mode & HRTIM_MODE_CONT) + { + regval |= HRTIM_CMNCR_CONT; + } + + /* Write register */ + + hrtim_tim_putreg(priv, timer, STM32_HRTIM_TIM_CR_OFFSET, regval); +} + +/**************************************************************************** + * Name: hrtim_mode_config + * + * Description: + * Configure HRTIM Timers mode + * + * Input Parameters: + * priv - A reference to the HRTIM structure + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void hrtim_mode_config(struct stm32_hrtim_s *priv) +{ +#ifdef CONFIG_STM32_HRTIM_MASTER + hrtim_tim_mode_set(priv, HRTIM_TIMER_MASTER, priv->master->tim.mode); +#endif + +#ifdef CONFIG_STM32_HRTIM_TIMA + hrtim_tim_mode_set(priv, HRTIM_TIMER_TIMA, priv->tima->tim.mode); +#endif + +#ifdef CONFIG_STM32_HRTIM_TIMB + hrtim_tim_mode_set(priv, HRTIM_TIMER_TIMB, priv->timb->tim.mode); +#endif + +#ifdef CONFIG_STM32_HRTIM_TIMC + hrtim_tim_mode_set(priv, HRTIM_TIMER_TIMC, priv->timc->tim.mode); +#endif + +#ifdef CONFIG_STM32_HRTIM_TIMD + hrtim_tim_mode_set(priv, HRTIM_TIMER_TIMD, priv->timd->tim.mode); +#endif + +#ifdef CONFIG_STM32_HRTIM_TIME + hrtim_tim_mode_set(priv, HRTIM_TIMER_TIME, priv->time->tim.mode); +#endif +} + +/**************************************************************************** + * Name: hrtim_cmpcap_mask_get + * + * Description: + * This function returns not significant bits in counter/capture + * registers for given HRTIM Timer index. + * + * Input Parameters: + * priv - A reference to the HRTIM structure + * timer - HRTIM Timer index + * + * Returned Value: + * Not significant bits for counter/capture registers + * + ****************************************************************************/ + +static uint8_t hrtim_cmpcap_mask_get(struct stm32_hrtim_s *priv, + uint8_t timer) +{ + struct stm32_hrtim_tim_s *tim; + uint8_t mask = 0; + + /* Get Timer data structure */ + + tim = hrtim_tim_get(priv, timer); + if (tim == NULL) + { + mask = 0; + goto errout; + } + + /* Not significant bits depens on timer prescaler */ + + switch (tim->tim.prescaler) + { + case HRTIM_PRESCALER_1: + { + mask = 0b11111; + break; + } + + case HRTIM_PRESCALER_2: + { + mask = 0b1111; + break; + } + + case HRTIM_PRESCALER_4: + { + mask = 0b111; + break; + } + + case HRTIM_PRESCALER_8: + { + mask = 0b11; + break; + } + + case HRTIM_PRESCALER_16: + { + mask = 0b1; + break; + } + + default: + { + mask = 0; + break; + } + } + +errout: + return mask; +} + +/**************************************************************************** + * Name: hrtim_cmp_update + * + * Description: + * Try update HRTIM Timer compare register. + * + * Input Parameters: + * dev - HRTIM device structure + * timer - HRTIM Timer index + * index - Compare register timer + * cmp - New compare register value + * + * Returned Value: + * 0 on success, a negated errno value on failure + * + ****************************************************************************/ + +static int hrtim_cmp_update(struct hrtim_dev_s *dev, uint8_t timer, + uint8_t index, uint16_t cmp) +{ + struct stm32_hrtim_s *priv = (struct stm32_hrtim_s *)dev->hd_priv; + int ret = OK; + uint32_t offset = 0; + uint8_t mask = 0; + + switch (index) + { + case HRTIM_CMP1: + { + offset = STM32_HRTIM_TIM_CMP1R_OFFSET; + break; + } + + case HRTIM_CMP2: + { + offset = STM32_HRTIM_TIM_CMP2R_OFFSET; + break; + } + + case HRTIM_CMP3: + { + offset = STM32_HRTIM_TIM_CMP3R_OFFSET; + break; + } + + case HRTIM_CMP4: + { + offset = STM32_HRTIM_TIM_CMP4R_OFFSET; + break; + } + + default: + { + ret = -EINVAL; + goto errout; + } + } + + /* REVISIT: what should we do if cmp value is not significant ? + * At this moment we set compare register to the nearest significant value. + */ + + mask = hrtim_cmpcap_mask_get(priv, timer); + if (cmp <= mask) + { + cmp = mask + 1; + } + + hrtim_tim_putreg(priv, timer, offset, cmp); + +errout: + return ret; +} + +/**************************************************************************** + * Name: hrtim_per_update + * + * Description: + * Try update HRTIM Timer period register. + * + * Input Parameters: + * dev - HRTIM device structure + * timer - HRTIM Timer index + * per - New period register value + * + * Returned Value: + * 0 on success; a negated errno value on failure + * + ****************************************************************************/ + +static int hrtim_per_update(struct hrtim_dev_s *dev, uint8_t timer, + uint16_t per) +{ + struct stm32_hrtim_s *priv = (struct stm32_hrtim_s *)dev->hd_priv; + hrtim_tim_putreg(priv, timer, STM32_HRTIM_TIM_PER_OFFSET, per); + + return OK; +} + +/**************************************************************************** + * Name: hrtim_per_get + * + * Description: + * Get HRTIM Timer period value + * + * Input Parameters: + * dev - HRTIM device structure + * timer - HRTIM Timer index + * + * Returned Value: + * Timer period value + * + ****************************************************************************/ + +static uint16_t hrtim_per_get(struct hrtim_dev_s *dev, uint8_t timer) +{ + struct stm32_hrtim_s *priv = (struct stm32_hrtim_s *)dev->hd_priv; + + return (uint16_t)hrtim_tim_getreg(priv, timer, STM32_HRTIM_TIM_PER_OFFSET); +} + +/**************************************************************************** + * Name: hrtim_rep_update + * + * Description: + * Try update HRTIM Timer repetition register. + * + * Input Parameters: + * dev - HRTIM device structure + * timer - HRTIM Timer index + * rep - New repetition register value + * + * Returned Value: + * 0 on success; a negated errno value on failure + * + ****************************************************************************/ + +static int hrtim_rep_update(struct hrtim_dev_s *dev, uint8_t timer, + uint8_t rep) +{ + struct stm32_hrtim_s *priv = (struct stm32_hrtim_s *)dev->hd_priv; + hrtim_tim_putreg(priv, timer, STM32_HRTIM_TIM_REPR_OFFSET, rep); + + return OK; +} + +/**************************************************************************** + * Name: hrtim_cmp_update + * + * Description: + * Get HRTIM Timer compare register + * + * Input Parameters: + * priv - A reference to the HRTIM block + * timer - HRTIM Timer index + * index - Compare register timer + * + * Returned Value: + * Timer compare value + * + ****************************************************************************/ + +static uint16_t hrtim_cmp_get(struct hrtim_dev_s *dev, uint8_t timer, + uint8_t index) +{ + struct stm32_hrtim_s *priv = (struct stm32_hrtim_s *)dev->hd_priv; + uint16_t cmpx = 0; + uint32_t offset = 0; + + switch (index) + { + case HRTIM_CMP1: + { + offset = STM32_HRTIM_TIM_CMP1R_OFFSET; + break; + } + + case HRTIM_CMP2: + { + offset = STM32_HRTIM_TIM_CMP2R_OFFSET; + break; + } + + case HRTIM_CMP3: + { + offset = STM32_HRTIM_TIM_CMP3R_OFFSET; + break; + } + + case HRTIM_CMP4: + { + offset = STM32_HRTIM_TIM_CMP4R_OFFSET; + break; + } + + default: + { + cmpx = 0; + goto errout; + } + } + + cmpx = (uint16_t)hrtim_tim_getreg(priv, timer, offset); + +errout: + return cmpx; +} + +/**************************************************************************** + * Name: hrtim_fclk_get + * + * Description: + * Get HRTIM Timer clock value + * + * Input Parameters: + * dev - HRTIM device structure + * timer - HRTIM Timer index + * + * Returned Value: + * Timer clock value + * + ****************************************************************************/ + +static uint64_t hrtim_fclk_get(struct hrtim_dev_s *dev, uint8_t timer) +{ + struct stm32_hrtim_s *priv = (struct stm32_hrtim_s *)dev->hd_priv; + struct stm32_hrtim_tim_s *tim; + uint64_t fclk = 0; + + /* Get Timer data structure */ + + tim = hrtim_tim_get(priv, timer); + if (tim == NULL) + { + fclk = 0; + goto errout; + } + + fclk = tim->tim.fclk; + +errout: + return fclk; +} + +/**************************************************************************** + * Name: hrtim_soft_update + * + * Description: + * HRTIM Timer software update. + * This is bulk operation, so we can update many registers at the same + * time. + * + * Input Parameters: + * dev - HRTIM device structure + * timer - HRTIM Timer indexes + * + * Returned Value: + * 0 on success; a negated errno value on failure + * + ****************************************************************************/ + +static int hrtim_soft_update(struct hrtim_dev_s *dev, uint8_t timer) +{ + struct stm32_hrtim_s *priv = (struct stm32_hrtim_s *)dev->hd_priv; + uint32_t regval = 0; + + regval |= (timer & HRTIM_TIMER_MASTER ? HRTIM_CR2_MSWU : 0); +#ifdef CONFIG_STM32_HRTIM_TIMA + regval |= (timer & HRTIM_TIMER_TIMA ? HRTIM_CR2_TASWU : 0); +#endif +#ifdef CONFIG_STM32_HRTIM_TIMB + regval |= (timer & HRTIM_TIMER_TIMB ? HRTIM_CR2_TBSWU : 0); +#endif +#ifdef CONFIG_STM32_HRTIM_TIMC + regval |= (timer & HRTIM_TIMER_TIMC ? HRTIM_CR2_TCSWU : 0); +#endif +#ifdef CONFIG_STM32_HRTIM_TIMD + regval |= (timer & HRTIM_TIMER_TIMD ? HRTIM_CR2_TDSWU : 0); +#endif +#ifdef CONFIG_STM32_HRTIM_TIME + regval |= (timer & HRTIM_TIMER_TIME ? HRTIM_CR2_TESWU : 0); +#endif + + /* Bits in HRTIM CR2 common register are automatically reset, + * so we can just write to it. + */ + + hrtim_cmn_putreg(priv, STM32_HRTIM_CMN_CR2_OFFSET, regval); + + return OK; +} + +/**************************************************************************** + * Name: hrtim_soft_reset + * + * Description: + * HRTIM Timer software reset. + * This is bulk operation, so we can update many registers at the same + * time. + * + * Input Parameters: + * dev - HRTIM device structure + * timer - HRTIM Timer indexes + * + * Returned Value: + * 0 on success; a negated errno value on failure + * + ****************************************************************************/ + +static int hrtim_soft_reset(struct hrtim_dev_s *dev, uint8_t timer) +{ + struct stm32_hrtim_s *priv = (struct stm32_hrtim_s *)dev->hd_priv; + uint32_t regval = 0; + + regval |= (timer & HRTIM_TIMER_MASTER ? HRTIM_CR2_MRST : 0); +#ifdef CONFIG_STM32_HRTIM_TIMA + regval |= (timer & HRTIM_TIMER_TIMA ? HRTIM_CR2_TARST : 0); +#endif +#ifdef CONFIG_STM32_HRTIM_TIMB + regval |= (timer & HRTIM_TIMER_TIMB ? HRTIM_CR2_TBRST : 0); +#endif +#ifdef CONFIG_STM32_HRTIM_TIMC + regval |= (timer & HRTIM_TIMER_TIMC ? HRTIM_CR2_TCRST : 0); +#endif +#ifdef CONFIG_STM32_HRTIM_TIMD + regval |= (timer & HRTIM_TIMER_TIMD ? HRTIM_CR2_TDRST : 0); +#endif +#ifdef CONFIG_STM32_HRTIM_TIME + regval |= (timer & HRTIM_TIMER_TIME ? HRTIM_CR2_TERST : 0); +#endif + + /* Bits in HRTIM CR2 common register are automatically reset, + * so we can just write to it. + */ + + hrtim_cmn_putreg(priv, STM32_HRTIM_CMN_CR2_OFFSET, regval); + + return OK; +} + +/**************************************************************************** + * Name: hrtim_tim_freq_set + * + * Description: + * Set HRTIM Timer frequency + * + * Returned Value: + * 0 on success, a negated errno value on failure + * + ****************************************************************************/ + +static int hrtim_tim_freq_set(struct hrtim_dev_s *dev, uint8_t timer, + uint64_t freq) +{ + uint64_t per = 0; + uint64_t fclk = 0; + int ret = OK; + + /* Get Timer period value for given frequency */ + + fclk = HRTIM_FCLK_GET(dev, timer); + per = fclk / freq; + if (per > HRTIM_PER_MAX) + { + tmrerr("ERROR: can not achieve timer pwm " + "freq=%" PRIu64 " if fclk=%" PRIu64 "\n", + freq, fclk); + ret = -EINVAL; + goto errout; + } + + /* Set Timer period value */ + + HRTIM_PER_SET(dev, timer, (uint16_t)per); + +errout: + return ret; +} + +/**************************************************************************** + * Name: hrtim_tim_enable + * + * Description: + * Enable/disable HRTIM timer counter (bulk operation) + * + * Returned Value: + * 0 on success, a negated errno value on failure + * + ****************************************************************************/ + +static int hrtim_tim_enable(struct hrtim_dev_s *dev, uint8_t timers, + bool state) +{ + struct stm32_hrtim_s *priv = (struct stm32_hrtim_s *)dev->hd_priv; + uint32_t regval = 0; + + regval |= (timers & HRTIM_TIMERS_MASK) << HRTIM_MCR_TCEN_SHIFT; + + if (state == true) + { + /* Set bits */ + + hrtim_tim_modifyreg(priv, HRTIM_TIMER_MASTER, + STM32_HRTIM_TIM_CR_OFFSET, + 0, regval); + } + else + { + /* Clear bits */ + + hrtim_tim_modifyreg(priv, HRTIM_TIMER_MASTER, + STM32_HRTIM_TIM_CR_OFFSET, + regval, 0); + } + + return OK; +} + +/**************************************************************************** + * Name: hrtim_tim_reset_set + * + * Description: + * Set HRTIM Timer Reset events + * + * Input Parameters: + * priv - A reference to the HRTIM block + * timer - HRTIM Timer index + * reset - Reset configuration + * + * Returned Value: + * Zero on success; a negated errno value on failure + * + ****************************************************************************/ + +static int hrtim_tim_reset_set(struct stm32_hrtim_s *priv, uint8_t timer, + uint64_t reset) +{ + int ret = OK; + uint32_t regval = 0; + + /* Sanity checking */ + + if (timer == HRTIM_TIMER_MASTER || timer == HRTIM_TIMER_COMMON) + { + ret = -EINVAL; + goto errout; + } + + /* First 18 bits can be written directly */ + + regval |= (reset & 0x3ffff); + + /* TimerX reset events differ for individual timers */ + + switch (timer) + { +#ifdef CONFIG_STM32_HRTIM_TIMA + case HRTIM_TIMER_TIMA: + { + regval |= ((reset & HRTIM_RST_TBCMP1) ? + HRTIM_TIMARST_TIMBCMP1 : 0); + regval |= ((reset & HRTIM_RST_TBCMP2) ? + HRTIM_TIMARST_TIMBCMP2 : 0); + regval |= ((reset & HRTIM_RST_TBCMP4) ? + HRTIM_TIMARST_TIMBCMP4 : 0); + regval |= ((reset & HRTIM_RST_TCCMP1) ? + HRTIM_TIMARST_TIMCCMP1 : 0); + regval |= ((reset & HRTIM_RST_TCCMP2) ? + HRTIM_TIMARST_TIMCCMP2 : 0); + regval |= ((reset & HRTIM_RST_TCCMP4) ? + HRTIM_TIMARST_TIMCCMP4 : 0); + regval |= ((reset & HRTIM_RST_TDCMP1) ? + HRTIM_TIMARST_TIMDCMP1 : 0); + regval |= ((reset & HRTIM_RST_TDCMP2) ? + HRTIM_TIMARST_TIMDCMP2 : 0); + regval |= ((reset & HRTIM_RST_TDCMP4) ? + HRTIM_TIMARST_TIMDCMP4 : 0); + regval |= ((reset & HRTIM_RST_TECMP1) ? + HRTIM_TIMARST_TIMECMP1 : 0); + regval |= ((reset & HRTIM_RST_TECMP2) ? + HRTIM_TIMARST_TIMECMP2 : 0); + regval |= ((reset & HRTIM_RST_TECMP4) ? + HRTIM_TIMARST_TIMECMP4 : 0); + break; + } +#endif + +#ifdef CONFIG_STM32_HRTIM_TIMB + case HRTIM_TIMER_TIMB: + { + regval |= ((reset & HRTIM_RST_TACMP1) ? + HRTIM_TIMBRST_TIMACMP1 : 0); + regval |= ((reset & HRTIM_RST_TACMP2) ? + HRTIM_TIMBRST_TIMACMP2 : 0); + regval |= ((reset & HRTIM_RST_TACMP4) ? + HRTIM_TIMBRST_TIMACMP4 : 0); + regval |= ((reset & HRTIM_RST_TCCMP1) ? + HRTIM_TIMBRST_TIMCCMP1 : 0); + regval |= ((reset & HRTIM_RST_TCCMP2) ? + HRTIM_TIMBRST_TIMCCMP2 : 0); + regval |= ((reset & HRTIM_RST_TCCMP4) ? + HRTIM_TIMBRST_TIMCCMP4 : 0); + regval |= ((reset & HRTIM_RST_TDCMP1) ? + HRTIM_TIMBRST_TIMDCMP1 : 0); + regval |= ((reset & HRTIM_RST_TDCMP2) ? + HRTIM_TIMBRST_TIMDCMP2 : 0); + regval |= ((reset & HRTIM_RST_TDCMP4) ? + HRTIM_TIMBRST_TIMDCMP4 : 0); + regval |= ((reset & HRTIM_RST_TECMP1) ? + HRTIM_TIMBRST_TIMECMP1 : 0); + regval |= ((reset & HRTIM_RST_TECMP2) ? + HRTIM_TIMBRST_TIMECMP2 : 0); + regval |= ((reset & HRTIM_RST_TECMP4) ? + HRTIM_TIMBRST_TIMECMP4 : 0); + break; + } +#endif + +#ifdef CONFIG_STM32_HRTIM_TIMC + case HRTIM_TIMER_TIMC: + { + regval |= ((reset & HRTIM_RST_TACMP1) ? + HRTIM_TIMCRST_TIMACMP1 : 0); + regval |= ((reset & HRTIM_RST_TACMP2) ? + HRTIM_TIMCRST_TIMACMP2 : 0); + regval |= ((reset & HRTIM_RST_TACMP4) ? + HRTIM_TIMCRST_TIMACMP4 : 0); + regval |= ((reset & HRTIM_RST_TBCMP1) ? + HRTIM_TIMCRST_TIMBCMP1 : 0); + regval |= ((reset & HRTIM_RST_TBCMP2) ? + HRTIM_TIMCRST_TIMBCMP2 : 0); + regval |= ((reset & HRTIM_RST_TBCMP4) ? + HRTIM_TIMCRST_TIMBCMP4 : 0); + regval |= ((reset & HRTIM_RST_TDCMP1) ? + HRTIM_TIMCRST_TIMDCMP1 : 0); + regval |= ((reset & HRTIM_RST_TDCMP2) ? + HRTIM_TIMCRST_TIMDCMP2 : 0); + regval |= ((reset & HRTIM_RST_TDCMP4) ? + HRTIM_TIMCRST_TIMDCMP4 : 0); + regval |= ((reset & HRTIM_RST_TECMP1) ? + HRTIM_TIMCRST_TIMECMP1 : 0); + regval |= ((reset & HRTIM_RST_TECMP2) ? + HRTIM_TIMCRST_TIMECMP2 : 0); + regval |= ((reset & HRTIM_RST_TECMP4) ? + HRTIM_TIMCRST_TIMECMP4 : 0); + break; + } +#endif + +#ifdef CONFIG_STM32_HRTIM_TIMD + case HRTIM_TIMER_TIMD: + { + regval |= ((reset & HRTIM_RST_TACMP1) ? + HRTIM_TIMDRST_TIMACMP1 : 0); + regval |= ((reset & HRTIM_RST_TACMP2) ? + HRTIM_TIMDRST_TIMACMP2 : 0); + regval |= ((reset & HRTIM_RST_TACMP4) ? + HRTIM_TIMDRST_TIMACMP4 : 0); + regval |= ((reset & HRTIM_RST_TBCMP1) ? + HRTIM_TIMDRST_TIMBCMP1 : 0); + regval |= ((reset & HRTIM_RST_TBCMP2) ? + HRTIM_TIMDRST_TIMBCMP2 : 0); + regval |= ((reset & HRTIM_RST_TBCMP4) ? + HRTIM_TIMDRST_TIMBCMP4 : 0); + regval |= ((reset & HRTIM_RST_TCCMP1) ? + HRTIM_TIMDRST_TIMCCMP1 : 0); + regval |= ((reset & HRTIM_RST_TCCMP2) ? + HRTIM_TIMDRST_TIMCCMP2 : 0); + regval |= ((reset & HRTIM_RST_TCCMP4) ? + HRTIM_TIMDRST_TIMCCMP4 : 0); + regval |= ((reset & HRTIM_RST_TECMP1) ? + HRTIM_TIMDRST_TIMECMP1 : 0); + regval |= ((reset & HRTIM_RST_TECMP2) ? + HRTIM_TIMDRST_TIMECMP2 : 0); + regval |= ((reset & HRTIM_RST_TECMP4) ? + HRTIM_TIMDRST_TIMECMP4 : 0); + break; + } +#endif + +#ifdef CONFIG_STM32_HRTIM_TIME + case HRTIM_TIMER_TIME: + { + regval |= ((reset & HRTIM_RST_TACMP1) ? + HRTIM_TIMERST_TIMACMP1 : 0); + regval |= ((reset & HRTIM_RST_TACMP2) ? + HRTIM_TIMERST_TIMACMP2 : 0); + regval |= ((reset & HRTIM_RST_TACMP4) ? + HRTIM_TIMERST_TIMACMP4 : 0); + regval |= ((reset & HRTIM_RST_TBCMP1) ? + HRTIM_TIMERST_TIMBCMP1 : 0); + regval |= ((reset & HRTIM_RST_TBCMP2) ? + HRTIM_TIMERST_TIMBCMP2 : 0); + regval |= ((reset & HRTIM_RST_TBCMP4) ? + HRTIM_TIMERST_TIMBCMP4 : 0); + regval |= ((reset & HRTIM_RST_TCCMP1) ? + HRTIM_TIMERST_TIMCCMP1 : 0); + regval |= ((reset & HRTIM_RST_TCCMP2) ? + HRTIM_TIMERST_TIMCCMP2 : 0); + regval |= ((reset & HRTIM_RST_TCCMP4) ? + HRTIM_TIMERST_TIMCCMP4 : 0); + regval |= ((reset & HRTIM_RST_TDCMP1) ? + HRTIM_TIMERST_TIMDCMP1 : 0); + regval |= ((reset & HRTIM_RST_TDCMP2) ? + HRTIM_TIMERST_TIMDCMP2 : 0); + regval |= ((reset & HRTIM_RST_TDCMP4) ? + HRTIM_TIMERST_TIMDCMP4 : 0); + break; + } +#endif + + default: + { + ret = -EINVAL; + goto errout; + } + } + + hrtim_tim_putreg(priv, timer, STM32_HRTIM_TIM_RSTR_OFFSET, regval); + +errout: + return ret; +} + +static int hrtim_reset_config(struct stm32_hrtim_s *priv) +{ + struct stm32_hrtim_slave_priv_s *slave; + +#ifdef CONFIG_STM32_HRTIM_TIMA + slave = (struct stm32_hrtim_slave_priv_s *)priv->tima->priv; + hrtim_tim_reset_set(priv, HRTIM_TIMER_TIMA, slave->reset); +#endif + +#ifdef CONFIG_STM32_HRTIM_TIMB + slave = (struct stm32_hrtim_slave_priv_s *)priv->timb->priv; + hrtim_tim_reset_set(priv, HRTIM_TIMER_TIMB, slave->reset); +#endif + +#ifdef CONFIG_STM32_HRTIM_TIMC + slave = (struct stm32_hrtim_slave_priv_s *)priv->timc->priv; + hrtim_tim_reset_set(priv, HRTIM_TIMER_TIMC, slave->reset); +#endif + +#ifdef CONFIG_STM32_HRTIM_TIMD + slave = (struct stm32_hrtim_slave_priv_s *)priv->timd->priv; + hrtim_tim_reset_set(priv, HRTIM_TIMER_TIMD, slave->reset); +#endif + +#ifdef CONFIG_STM32_HRTIM_TIME + slave = (struct stm32_hrtim_slave_priv_s *)priv->time->priv; + hrtim_tim_reset_set(priv, HRTIM_TIMER_TIME, slave->reset); +#endif + + return OK; +} + +static int hrtim_tim_update_set(struct stm32_hrtim_s *priv, + uint8_t timer, + uint16_t update) +{ + uint32_t regval = 0; + + regval = hrtim_tim_getreg(priv, timer, STM32_HRTIM_TIM_CR_OFFSET); + + /* Configure update events */ + + regval |= (update & HRTIM_UPDATE_MSTU ? HRTIM_TIMCR_MSTU : 0); + regval |= (update & HRTIM_UPDATE_RSTU ? HRTIM_TIMCR_RSTU : 0); + regval |= (update & HRTIM_UPDATE_REPU ? HRTIM_TIMCR_REPU : 0); + +#ifdef CONFIG_STM32_HRTIM_TIMA + regval |= (update & HRTIM_UPDATE_TAU ? HRTIM_TIMCR_TAU : 0); +#endif + +#ifdef CONFIG_STM32_HRTIM_TIMB + regval |= (update & HRTIM_UPDATE_TBU ? HRTIM_TIMCR_TBU : 0); +#endif + +#ifdef CONFIG_STM32_HRTIM_TIMC + regval |= (update & HRTIM_UPDATE_TCU ? HRTIM_TIMCR_TCU : 0); +#endif + +#ifdef CONFIG_STM32_HRTIM_TIMD + regval |= (update & HRTIM_UPDATE_TDU ? HRTIM_TIMCR_TDU : 0); +#endif + +#ifdef CONFIG_STM32_HRTIM_TIME + regval |= (update & HRTIM_UPDATE_TEU ? HRTIM_TIMCR_TEU : 0); +#endif + + /* TODO: Configure update gating */ + + /* Write register */ + + hrtim_tim_putreg(priv, timer, STM32_HRTIM_TIM_CR_OFFSET, regval); + + return OK; +} + +static int hrtim_update_config(struct stm32_hrtim_s *priv) +{ + struct stm32_hrtim_slave_priv_s *slave; + +#ifdef CONFIG_STM32_HRTIM_TIMA + slave = (struct stm32_hrtim_slave_priv_s *)priv->tima->priv; + hrtim_tim_update_set(priv, HRTIM_TIMER_TIMA, slave->update); +#endif + +#ifdef CONFIG_STM32_HRTIM_TIMB + slave = (struct stm32_hrtim_slave_priv_s *)priv->timb->priv; + hrtim_tim_update_set(priv, HRTIM_TIMER_TIMB, slave->update); +#endif + +#ifdef CONFIG_STM32_HRTIM_TIMC + slave = (struct stm32_hrtim_slave_priv_s *)priv->timc->priv; + hrtim_tim_update_set(priv, HRTIM_TIMER_TIMC, slave->update); +#endif + +#ifdef CONFIG_STM32_HRTIM_TIMD + slave = (struct stm32_hrtim_slave_priv_s *)priv->timd->priv; + hrtim_tim_update_set(priv, HRTIM_TIMER_TIMD, slave->update); +#endif + +#ifdef CONFIG_STM32_HRTIM_TIME + slave = (struct stm32_hrtim_slave_priv_s *)priv->time->priv; + hrtim_tim_update_set(priv, HRTIM_TIMER_TIME, slave->update); +#endif + + return OK; +} + +/**************************************************************************** + * Name: stm32_hrtimconfig + * + * Description: + * Configure HRTIM + * + * Input Parameters: + * priv - A reference to the HRTIM structure + * + * Returned Value: + * 0 on success, a negated errno value on failure + * + ****************************************************************************/ + +static int stm32_hrtimconfig(struct stm32_hrtim_s *priv) +{ + int ret; + uint32_t regval = 0; + + /* HRTIM DLL calibration */ + + ret = hrtim_dll_cal(priv); + if (ret != OK) + { + tmrerr("ERROR: HRTIM DLL calibration failed!\n"); + goto errout; + } + + /* Configure Timers Clocks */ + + ret = hrtim_tim_clocks_config(priv); + if (ret != OK) + { + tmrerr("ERROR: HRTIM timers clock configuration failed!\n"); + goto errout; + } + + /* Configure Timers reset events */ + + hrtim_reset_config(priv); + + /* Configure Timers update events */ + + hrtim_update_config(priv); + + /* Configure Timers mode */ + + hrtim_mode_config(priv); + + /* Configure auto-delayed mode */ + +#ifdef CONFIG_STM32_HRTIM_AUTODELAYED + hrtim_autodelayed_config(priv); +#endif + + /* Configure HRTIM GPIOs */ + +#if defined(CONFIG_STM32_HRTIM_PWM) || defined(CONFIG_STM32_HRTIM_SYNC) + ret = hrtim_gpios_config(priv); + if (ret != OK) + { + tmrerr("ERROR: HRTIM GPIOs configuration failed!\n"); + goto errout; + } +#endif + + /* Configure HRTIM capture */ + +#if defined(CONFIG_STM32_HRTIM_CAPTURE) + ret = hrtim_capture_config(priv); + if (ret != OK) + { + tmrerr("ERROR: HRTIM capture configuration failed!\n"); + goto errout; + } +#endif + + /* Configure Synchronisation IOs */ + +#if defined(CONFIG_STM32_HRTIM_SYNC) + ret = hrtim_synch_config(priv); + if (ret != OK) + { + tmrerr("ERROR: HRTIM synchronisation configuration failed!\n"); + goto errout; + } +#endif + + /* Configure HRTIM outputs deadtime */ + +#if defined(CONFIG_STM32_HRTIM_DEADTIME) + ret = hrtim_deadtime_config(priv); + if (ret != OK) + { + tmrerr("ERROR: HRTIM deadtime configuration failed!\n"); + goto errout; + } +#endif + + /* Configure HRTIM outputs GPIOs */ + +#if defined(CONFIG_STM32_HRTIM_PWM) + ret = hrtim_outputs_config(priv); + if (ret != OK) + { + tmrerr("ERROR: HRTIM outputs configuration failed!\n"); + goto errout; + } +#endif + + /* Configure ADC triggers */ + +#ifdef HRTIM_HAVE_ADC + ret = hrtim_adc_config(priv); + if (ret != OK) + { + tmrerr("ERROR: HRTIM ADC configuration failed!\n"); + goto errout; + } +#endif + + /* Configure DAC synchronization */ + +#ifdef CONFIG_STM32_HRTIM_DAC + ret = hrtim_dac_config(priv); + if (ret != OK) + { + tmrerr("ERROR: HRTIM ADC configuration failed!\n"); + goto errout; + } +#endif + + /* Configure Faults */ + +#ifdef CONFIG_STM32_HRTIM_FAULTS + ret = hrtim_faults_config(priv); + if (ret != OK) + { + tmrerr("ERROR: HRTIM faults configuration failed!\n"); + goto errout; + } +#endif + + /* Configure External Events */ + +#ifdef CONFIG_STM32_HRTIM_EVENTS + ret = hrtim_events_config(priv); + if (ret != OK) + { + tmrerr("ERROR: HRTIM EEV configuration failed!\n"); + goto errout; + } +#endif + + /* Configure interrupts */ + +#ifdef CONFIG_STM32_HRTIM_INTERRUPTS + ret = hrtim_irq_config(priv); + if (ret != OK) + { + tmrerr("ERROR: HRTIM IRQ configuration failed!\n"); + goto errout; + } +#endif + + /* Configure DMA */ + +#ifdef CONFIG_STM32_HRTIM_DMA + ret = hrtim_dma_cfg(priv); + if (ret != OK) + { + tmrerr("ERROR: HRTIM DMA configuration failed!\n"); + goto errout; + } +#endif + + /* Configure burst mode */ + +#ifdef CONFIG_STM32_HRTIM_BURST + ret = hrtim_burst_config(priv); + if (ret != OK) + { + tmrerr("ERROR: HRTIM burst mode configuration failed!\n"); + goto errout; + } +#endif + +#ifndef CONFIG_STM32_HRTIM_NO_ENABLE_TIMERS + /* Enable Master Timer */ + +# ifdef CONFIG_STM32_HRTIM_MASTER + regval |= HRTIM_MCR_MCEN; +# endif + + /* Enable Slave Timers */ + +# ifdef CONFIG_STM32_HRTIM_TIMA + regval |= HRTIM_MCR_TACEN; +# endif + +# ifdef CONFIG_STM32_HRTIM_TIMB + regval |= HRTIM_MCR_TBCEN; +# endif + +# ifdef CONFIG_STM32_HRTIM_TIMC + regval |= HRTIM_MCR_TCCEN; +# endif + +# ifdef CONFIG_STM32_HRTIM_TIMD + regval |= HRTIM_MCR_TDCEN; +# endif + +# ifdef CONFIG_STM32_HRTIM_TIME + regval |= HRTIM_MCR_TECEN; +# endif + +#endif /* CONFIG_STM32_HRTIM_NO_ENABLE_TIMERS */ + + /* Write enable bits at once */ + + hrtim_tim_modifyreg(priv, HRTIM_TIMER_MASTER, STM32_HRTIM_TIM_CR_OFFSET, + 0, regval); + + /* Dump registers for Master */ + + hrtim_dumpregs(priv, HRTIM_TIMER_MASTER, "Master after configuration"); + + /* Dump registers for Timer A */ + +#ifdef CONFIG_STM32_HRTIM_TIMA + hrtim_dumpregs(priv, HRTIM_TIMER_TIMA, "Timer A after configuration"); +#endif + + /* Dump registers for Timer B */ + +#ifdef CONFIG_STM32_HRTIM_TIMB + hrtim_dumpregs(priv, HRTIM_TIMER_TIMB, "Timer B after configuration"); +#endif + + /* Dump registers for Timer C */ + +#ifdef CONFIG_STM32_HRTIM_TIMC + hrtim_dumpregs(priv, HRTIM_TIMER_TIMC, "Timer C after configuration"); +#endif + + /* Dump registers for Timer D */ + +#ifdef CONFIG_STM32_HRTIM_TIMD + hrtim_dumpregs(priv, HRTIM_TIMER_TIMD, "Timer D after configuration"); +#endif + + /* Dump registers for Timer E */ + +#ifdef CONFIG_STM32_HRTIM_TIME + hrtim_dumpregs(priv, HRTIM_TIMER_TIME, "Timer E after configuration"); +#endif + + /* Dump common registers */ + + hrtim_dumpregs(priv, HRTIM_TIMER_COMMON, "Common after configuration"); + +errout: + return ret; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_hrtiminitialize + * + * Description: + * Initialize the HRTIM. + * + * Returned Value: + * Valid HRTIM device structure reference on success; a NULL on failure. + * + * Assumptions: + * 1. Clock to the HRTIM block has enabled, + * 2. Board-specific logic has already configured + * + ****************************************************************************/ + +struct hrtim_dev_s *stm32_hrtiminitialize(void) +{ + struct hrtim_dev_s *dev; + struct stm32_hrtim_s *hrtim; + int ret; + + dev = &g_hrtim1dev; + + hrtim = dev->hd_priv; + + /* configure HRTIM only once */ + + if (!dev->initialized) + { + ret = stm32_hrtimconfig(hrtim); + if (ret < 0) + { + tmrerr("ERROR: Failed to initialize HRTIM1: %d\n", ret); + return NULL; + } + + dev->initialized = true; + } + + return dev; +} + +/**************************************************************************** + * Name: hrtim_register + ****************************************************************************/ + +#ifndef CONFIG_STM32_HRTIM_DISABLE_CHARDRV +int hrtim_register(const char *path, struct hrtim_dev_s *dev) +{ + /* Initialize the HRTIM device structure */ + + dev->hd_ocount = 0; + + /* Register the HRTIM character driver */ + + return register_driver(path, &g_hrtim_fops, 0444, dev); +} +#endif /* CONFIG_STM32_HRTIM_DISABLE_CHARDRV */ + +#endif /* CONFIG_STM32_STM32F33XX || CONFIG_STM32_STM32G47XX */ +#endif /* CONFIG_STM32_HRTIM1 */ diff --git a/arch/arm/src/common/stm32/stm32_hrtim_m3m4_v1.h b/arch/arm/src/common/stm32/stm32_hrtim_m3m4_v1.h new file mode 100644 index 0000000000000..026c6e2e7f310 --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_hrtim_m3m4_v1.h @@ -0,0 +1,1139 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_hrtim_m3m4_v1.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_HRTIM_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_HRTIM_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include "chip.h" + +#ifdef CONFIG_STM32_HRTIM1 + +#if defined(CONFIG_STM32_STM32F33XX) +# include "hardware/stm32f33xxx_hrtim.h" +# include "hardware/stm32f33xxx_rcc.h" +#elif defined(CONFIG_STM32_STM32G47XX) +# include "hardware/stm32g47xxx_hrtim.h" +# include "hardware/stm32g4xxxx_rcc.h" +#else +# error +#endif + +/**************************************************************************** + * Pre-processor definitions + ****************************************************************************/ + +#if defined(CONFIG_STM32_HRTIM_TIMA) || defined(CONFIG_STM32_HRTIM_TIMB) || \ + defined(CONFIG_STM32_HRTIM_TIMC) || defined(CONFIG_STM32_HRTIM_TIMD) || \ + defined(CONFIG_STM32_HRTIM_TIME) +# define HRTIM_HAVE_SLAVE 1 +#endif + +#if defined(CONFIG_STM32_HRTIM_TIMA_PWM) || defined(CONFIG_STM32_HRTIM_TIMB_PWM) || \ + defined(CONFIG_STM32_HRTIM_TIMC_PWM) || defined(CONFIG_STM32_HRTIM_TIMD_PWM) || \ + defined(CONFIG_STM32_HRTIM_TIME_PWM) +# ifndef CONFIG_STM32_HRTIM_PWM +# error "CONFIG_STM32_HRTIM_PWM must be set" +# endif +#endif + +#if defined(CONFIG_STM32_HRTIM_TIMA_CAP) || defined(CONFIG_STM32_HRTIM_TIMB_CAP) || \ + defined(CONFIG_STM32_HRTIM_TIMC_CAP) || defined(CONFIG_STM32_HRTIM_TIMD_CAP) || \ + defined(CONFIG_STM32_HRTIM_TIME_CAP) +# ifndef CONFIG_STM32_HRTIM_CAPTURE +# error "CONFIG_STM32_HRTIM_CAPTURE must be set" +# endif +#endif + +#if defined(CONFIG_STM32_HRTIM_TIMA_DT) || defined(CONFIG_STM32_HRTIM_TIMB_DT) || \ + defined(CONFIG_STM32_HRTIM_TIMC_DT) || defined(CONFIG_STM32_HRTIM_TIMD_DT) || \ + defined(CONFIG_STM32_HRTIM_TIME_DT) +# ifndef CONFIG_STM32_HRTIM_DEADTIME +# error "CONFIG_STM32_HRTIM_DEADTIME must be set" +# endif +#endif + +#if defined(CONFIG_STM32_HRTIM_TIMA_CHOP) || defined(CONFIG_STM32_HRTIM_TIMB_CHOP) || \ + defined(CONFIG_STM32_HRTIM_TIMC_CHOP) || defined(CONFIG_STM32_HRTIM_TIMD_CHOP) || \ + defined(CONFIG_STM32_HRTIM_TIME_CHOP) +# ifndef CONFIG_STM32_HRTIM_CHOPPER +# error "CONFIG_STM32_HRTIM_CHOPPER must be set" +# endif +#endif + +#if defined(CONFIG_STM32_HRTIM_TIMA_BURST) || defined(CONFIG_STM32_HRTIM_TIMB_BURST) || \ + defined(CONFIG_STM32_HRTIM_TIMC_BURST) || defined(CONFIG_STM32_HRTIM_TIMD_BURST) || \ + defined(CONFIG_STM32_HRTIM_TIME_BURST) +# ifndef CONFIG_STM32_HRTIM_BURST +# error "CONFIG_STM32_HRTIM_BURST must be set" +# endif +#endif + +#if defined(CONFIG_STM32_HRTIM_SCOUT) || defined(CONFIG_STM32_HRTIM_SCIN) +# ifndef CONFIG_STM32_HRTIM_SYNC +# error "CONFIG_STM32_HRTIM_SYNC must be set" +# endif +#endif + +#if defined(CONFIG_STM32_HRTIM_FAULT1) || defined(CONFIG_STM32_HRTIM_FAULT2) || \ + defined(CONFIG_STM32_HRTIM_FAULT3) || defined(CONFIG_STM32_HRTIM_FAULT4) || \ + defined(CONFIG_STM32_HRTIM_FAULT5) +# ifndef CONFIG_STM32_HRTIM_FAULTS +# error "CONFIG_STM32_HRTIM_FAULTS must be set" +# endif +#endif + +#if defined(CONFIG_STM32_HRTIM_EEV1) || defined(CONFIG_STM32_HRTIM_EEV2) || \ + defined(CONFIG_STM32_HRTIM_EEV3) || defined(CONFIG_STM32_HRTIM_EEV4) || \ + defined(CONFIG_STM32_HRTIM_EEV5) || defined(CONFIG_STM32_HRTIM_EEV6) || \ + defined(CONFIG_STM32_HRTIM_EEV7) || defined(CONFIG_STM32_HRTIM_EEV8) || \ + defined(CONFIG_STM32_HRTIM_EEV9) || defined(CONFIG_STM32_HRTIM_EEV10) +# ifndef CONFIG_STM32_HRTIM_EVENTS +# error "CONFIG_STM32_HRTIM_EVENTS must be set" +# endif +#endif + +#if defined(CONFIG_STM32_HRTIM_MASTER_IRQ) || defined(CONFIG_STM32_HRTIM_TIMA_IRQ) || \ + defined(CONFIG_STM32_HRTIM_TIMB_IRQ) || defined(CONFIG_STM32_HRTIM_TIMC_IRQ) || \ + defined(CONFIG_STM32_HRTIM_TIMD_IRQ) || defined(CONFIG_STM32_HRTIM_TIME_IRQ) || \ + defined(CONFIG_STM32_HRTIM_CMN_IRQ) +# ifndef CONFIG_STM32_HRTIM_INTERRUPTS +# error "CONFIG_STM32_HRTIM_INTERRUPTS must be set" +# endif +#endif + +#if defined(CONFIG_STM32_HRTIM_ADC_TRG1) || defined(CONFIG_STM32_HRTIM_ADC_TRG2) || \ + defined(CONFIG_STM32_HRTIM_ADC_TRG3) || defined(CONFIG_STM32_HRTIM_ADC_TRG4) +# ifndef CONFIG_STM32_HRTIM_ADC +# error "CONFIG_STM32_HRTIM_ADC must be set" +# endif +#endif + +/* TIMX PWM configuration checking */ + +#ifdef CONFIG_STM32_HRTIM_TIMA_PWM +# if !defined(CONFIG_STM32_HRTIM_TIMA_PWM_CH1) && \ + !defined(CONFIG_STM32_HRTIM_TIMA_PWM_CH2) +# error "HRTIM TIMA PWM set but no channel selected" +# endif +#endif +#ifdef CONFIG_STM32_HRTIM_TIMB_PWM +# if !defined(CONFIG_STM32_HRTIM_TIMB_PWM_CH1) && \ + !defined(CONFIG_STM32_HRTIM_TIMB_PWM_CH2) +# error "HRTIM TIMB PWM set but no channel selected" +# endif +#endif +#ifdef CONFIG_STM32_HRTIM_TIMC_PWM +# if !defined(CONFIG_STM32_HRTIM_TIMC_PWM_CH1) && \ + !defined(CONFIG_STM32_HRTIM_TIMC_PWM_CH2) +# error "HRTIM TIMC PWM set but no channel selected" +# endif +#endif +#ifdef CONFIG_STM32_HRTIM_TIMD_PWM +# if !defined(CONFIG_STM32_HRTIM_TIMD_PWM_CH1) && \ + !defined(CONFIG_STM32_HRTIM_TIMD_PWM_CH2) +# error "HRTIM TIMD PWM set but no channel selected" +# endif +#endif +#ifdef CONFIG_STM32_HRTIM_TIME_PWM +# if !defined(CONFIG_STM32_HRTIM_TIME_PWM_CH1) && \ + !defined(CONFIG_STM32_HRTIM_TIME_PWM_CH2) +# error "HRTIM TIME PWM set but no channel selected" +# endif +#endif + +/* HRTIM clock source configuration */ + +#ifdef CONFIG_STM32_HRTIM_CLK_FROM_PLL +# if STM32_SYSCLK_SW == RCC_CFGR_SW_PLL +# if (STM32_RCC_CFGR_PPRE2 != RCC_CFGR_PPRE2_HCLK) && \ + (STM32_RCC_CFGR_PPRE2 != RCC_CFGR_PPRE2_HCLKd2) +# error "APB2 prescaler factor can not be greater than 2" +# else +# define HRTIM_HAVE_CLK_FROM_PLL 1 +# define HRTIM_MAIN_CLOCK 2*STM32_PLL_FREQUENCY +# endif +# else +# error "Clock system must be set to PLL" +# endif +#else +# define HRTIM_HAVE_CLK_FROM_APB2 1 +# if STM32_RCC_CFGR_PPRE2 == RCC_CFGR_PPRE2_HCLK +# define HRTIM_MAIN_CLOCK STM32_PCLK2_FREQUENCY +# else +# error "Not supported yet." +# define HRTIM_MAIN_CLOCK 2*STM32_PCLK2_FREQUENCY +# endif +#endif + +/* High-resolution equivalent clock */ + +#define HRTIM_CLOCK (HRTIM_MAIN_CLOCK*32ull) + +/* Helpers ******************************************************************/ + +#define HRTIM_CMP_SET(hrtim, tim, index, cmp) \ + (hrtim)->hd_ops->cmp_update(hrtim, tim, index, cmp) +#define HRTIM_PER_SET(hrtim, tim, per) \ + (hrtim)->hd_ops->per_update(hrtim, tim, per) +#define HRTIM_REP_SET(hrtim, tim, per) \ + (hrtim)->hd_ops->rep_update(hrtim, tim, per) +#define HRTIM_PER_GET(hrtim, tim) \ + (hrtim)->hd_ops->per_get(hrtim, tim) +#define HRTIM_FCLK_GET(hrtim, tim) \ + (hrtim)->hd_ops->fclk_get(hrtim, tim) +#define HRTIM_IRQ_GET(hrtim, irq) \ + (hrtim)->hd_ops->irq_get(hrtim, irq) +#define HRTIM_CAPTURE_GET(hrtim, timer, cap) \ + (hrtim)->hd_ops->capture_get(hrtim, timer, cap) +#define HRTIM_IRQ_ACK(hrtim, irq, ack) \ + (hrtim)->hd_ops->irq_ack(hrtim, irq, ack) +#define HRTIM_SOFT_UPDATE(hrtim, timer) \ + (hrtim)->hd_ops->soft_update(hrtim, timer) +#define HRTIM_SOFT_CAPTURE(hrtim, timer, index) \ + (hrtim)->hd_ops->soft_capture(hrtim, timer, index) +#define HRTIM_SOFT_RESET(hrtim, timer) \ + (hrtim)->hd_ops->soft_reset(hrtim, timer) +#define HRTIM_FREQ_SET(hrtim, timer,freq) \ + (hrtim)->hd_ops->freq_set(hrtim, timer, freq) +#define HRTIM_TIM_ENABLE(hrtim, timers, state) \ + (hrtim)->hd_ops->tim_enable(hrtim, timers, state) +#define HRTIM_OUTPUTS_ENABLE(hrtim, outputs, state) \ + (hrtim)->hd_ops->outputs_enable(hrtim, outputs, state) +#define HRTIM_OUTPUT_SET_SET(hrtim, output, set) \ + (hrtim)->hd_ops->output_set_set(hrtim, output, set) +#define HRTIM_OUTPUT_RST_SET(hrtim, output, rst) \ + (hrtim)->hd_ops->output_rst_set(hrtim, output, rst) +#define HRTIM_BURST_CMP_SET(hrtim, cmp) \ + (hrtim)->hd_ops->burst_cmp_set(hrtim, cmp) +#define HRTIM_BURST_PER_SET(hrtim, per) \ + (hrtim)->hd_ops->burst_per_set(hrtim, per) +#define HRTIM_BURST_PRE_SET(hrtim, pre) \ + (hrtim)->hd_ops->burst_pre_set(hrtim, pre) +#define HRTIM_BURST_ENABLE(hrtim, state) \ + (hrtim)->hd_ops->burst_enable(hrtim, state) +#define HRTIM_DEADTIME_UPDATE(hrtim, tim, dt, val) \ + (hrtim)->hd_ops->deadtime_update(hrtim, tim, dt, val) + +#define HRTIM_PER_MAX 0xFFFF +#define HRTIM_CMP_MAX 0xFFFF +#define HRTIM_CPT_MAX 0xFFFF +#define HRTIM_REP_MAX 0xFF + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/* HRTIM Timer X index */ + +enum stm32_hrtim_tim_e +{ + HRTIM_TIMER_MASTER = (1 << 0), +#ifdef CONFIG_STM32_HRTIM_TIMA + HRTIM_TIMER_TIMA = (1 << 1), +#endif +#ifdef CONFIG_STM32_HRTIM_TIMB + HRTIM_TIMER_TIMB = (1 << 2), +#endif +#ifdef CONFIG_STM32_HRTIM_TIMC + HRTIM_TIMER_TIMC = (1 << 3), +#endif +#ifdef CONFIG_STM32_HRTIM_TIMD + HRTIM_TIMER_TIMD = (1 << 4), +#endif +#ifdef CONFIG_STM32_HRTIM_TIME + HRTIM_TIMER_TIME = (1 << 5), +#endif + HRTIM_TIMER_COMMON = (1 << 6), + + HRTIM_TIMERS_MASK = 0x3f +}; + +/* Source which can force the Tx1/Tx2 output to its inactive state */ + +enum stm32_hrtim_out_rst_e +{ + HRTIM_OUT_RST_NONE = 0, + HRTIM_OUT_RST_SOFT = (1 << 0), + HRTIM_OUT_RST_RESYNC = (1 << 1), + HRTIM_OUT_RST_PER = (1 << 2), + HRTIM_OUT_RST_CMP1 = (1 << 3), + HRTIM_OUT_RST_CMP2 = (1 << 4), + HRTIM_OUT_RST_CMP3 = (1 << 5), + HRTIM_OUT_RST_CMP4 = (1 << 6), + HRTIM_OUT_RST_MSTPER = (1 << 7), + HRTIM_OUT_RST_MSTCMP1 = (1 << 8), + HRTIM_OUT_RST_MSTCMP2 = (1 << 9), + HRTIM_OUT_RST_MSTCMP3 = (1 << 10), + HRTIM_OUT_RST_MSTCMP4 = (1 << 11), + HRTIM_OUT_RST_TIMEVNT1 = (1 << 12), + HRTIM_OUT_RST_TIMEVNT2 = (1 << 13), + HRTIM_OUT_RST_TIMEVNT3 = (1 << 14), + HRTIM_OUT_RST_TIMEVNT4 = (1 << 15), + HRTIM_OUT_RST_TIMEVNT5 = (1 << 16), + HRTIM_OUT_RST_TIMEVNT6 = (1 << 17), + HRTIM_OUT_RST_TIMEVNT7 = (1 << 18), + HRTIM_OUT_RST_TIMEVNT8 = (1 << 19), + HRTIM_OUT_RST_TIMEVNT9 = (1 << 20), + HRTIM_OUT_RST_EXTEVNT1 = (1 << 21), + HRTIM_OUT_RST_EXTEVNT2 = (1 << 22), + HRTIM_OUT_RST_EXTEVNT3 = (1 << 23), + HRTIM_OUT_RST_EXTEVNT4 = (1 << 24), + HRTIM_OUT_RST_EXTEVNT5 = (1 << 25), + HRTIM_OUT_RST_EXTEVNT6 = (1 << 26), + HRTIM_OUT_RST_EXTEVNT7 = (1 << 27), + HRTIM_OUT_RST_EXTEVNT8 = (1 << 28), + HRTIM_OUT_RST_EXTEVNT9 = (1 << 29), + HRTIM_OUT_RST_EXTEVNT10 = (1 << 30), + HRTIM_OUT_RST_UPDATE = (1 << 31), +}; + +/* Source which can force the Tx1/Tx2 output to its active state */ + +enum stm32_hrtim_out_set_e +{ + HRTIM_OUT_SET_NONE = 0, + HRTIM_OUT_SET_SOFT = (1 << 0), + HRTIM_OUT_SET_RESYNC = (1 << 1), + HRTIM_OUT_SET_PER = (1 << 2), + HRTIM_OUT_SET_CMP1 = (1 << 3), + HRTIM_OUT_SET_CMP2 = (1 << 4), + HRTIM_OUT_SET_CMP3 = (1 << 5), + HRTIM_OUT_SET_CMP4 = (1 << 6), + HRTIM_OUT_SET_MSTPER = (1 << 7), + HRTIM_OUT_SET_MSTCMP1 = (1 << 8), + HRTIM_OUT_SET_MSTCMP2 = (1 << 9), + HRTIM_OUT_SET_MSTCMP3 = (1 << 10), + HRTIM_OUT_SET_MSTCMP4 = (1 << 11), + HRTIM_OUT_SET_TIMEVNT1 = (1 << 12), + HRTIM_OUT_SET_TIMEVNT2 = (1 << 13), + HRTIM_OUT_SET_TIMEVNT3 = (1 << 14), + HRTIM_OUT_SET_TIMEVNT4 = (1 << 15), + HRTIM_OUT_SET_TIMEVNT5 = (1 << 16), + HRTIM_OUT_SET_TIMEVNT6 = (1 << 17), + HRTIM_OUT_SET_TIMEVNT7 = (1 << 18), + HRTIM_OUT_SET_TIMEVNT8 = (1 << 19), + HRTIM_OUT_SET_TIMEVNT9 = (1 << 20), + HRTIM_OUT_SET_EXTEVNT1 = (1 << 21), + HRTIM_OUT_SET_EXTEVNT2 = (1 << 22), + HRTIM_OUT_SET_EXTEVNT3 = (1 << 23), + HRTIM_OUT_SET_EXTEVNT4 = (1 << 24), + HRTIM_OUT_SET_EXTEVNT5 = (1 << 25), + HRTIM_OUT_SET_EXTEVNT6 = (1 << 26), + HRTIM_OUT_SET_EXTEVNT7 = (1 << 27), + HRTIM_OUT_SET_EXTEVNT8 = (1 << 28), + HRTIM_OUT_SET_EXTEVNT9 = (1 << 29), + HRTIM_OUT_SET_EXTEVNT10 = (1 << 30), + HRTIM_OUT_SET_UPDATE = (1 << 31), +}; + +/* Events that can reset TimerX Counter */ + +enum stm32_hrtim_tim_rst_e +{ + /* Timer owns events */ + + HRTIM_RST_UPDT = (1 << 1), + HRTIM_RST_CMP4 = (1 << 2), + HRTIM_RST_CMP2 = (1 << 3), + + /* Master Timer Events */ + + HRTIM_RST_MSTPER = (1 << 4), + HRTIM_RST_MSTCMP1 = (1 << 5), + HRTIM_RST_MSTCMP2 = (1 << 6), + HRTIM_RST_MSTCMP3 = (1 << 7), + HRTIM_RST_MSTCMP4 = (1 << 8), + + /* External Events */ + + HRTIM_RST_EXTEVNT1 = (1 << 9), + HRTIM_RST_EXTEVNT2 = (1 << 10), + HRTIM_RST_EXTEVNT3 = (1 << 11), + HRTIM_RST_EXTEVNT4 = (1 << 12), + HRTIM_RST_EXTEVNT5 = (1 << 13), + HRTIM_RST_EXTEVNT6 = (1 << 14), + HRTIM_RST_EXTEVNT7 = (1 << 15), + HRTIM_RST_EXTEVNT8 = (1 << 16), + HRTIM_RST_EXTEVNT9 = (1 << 17), + HRTIM_RST_EXTEVNT10 = (1 << 18), + + /* TimerX events */ + + HRTIM_RST_TACMP1 = (1 << 19), + HRTIM_RST_TACMP2 = (1 << 20), + HRTIM_RST_TACMP4 = (1 << 21), + HRTIM_RST_TBCMP1 = (1 << 22), + HRTIM_RST_TBCMP2 = (1 << 23), + HRTIM_RST_TBCMP4 = (1 << 24), + HRTIM_RST_TCCMP1 = (1 << 25), + HRTIM_RST_TCCMP2 = (1 << 26), + HRTIM_RST_TCCMP4 = (1 << 27), + HRTIM_RST_TDCMP1 = (1 << 28), + HRTIM_RST_TDCMP2 = (1 << 29), + HRTIM_RST_TDCMP4 = (1 << 30), + HRTIM_RST_TECMP1 = (1 << 31), +}; + +/* This definitions does not fit to the above 32 bit enum */ + +#define HRTIM_RST_TECMP2 (1ull << 32) +#define HRTIM_RST_TECMP4 (1ull << 33) + +/* HRTIM Timer X prescaler */ + +enum stm32_hrtim_tim_prescaler_e +{ + HRTIM_PRESCALER_1, /* CKPSC = 0 */ + HRTIM_PRESCALER_2, /* CKPSC = 1 */ + HRTIM_PRESCALER_4, /* CKPSC = 2 */ + HRTIM_PRESCALER_8, /* CKPSC = 3 */ + HRTIM_PRESCALER_16, /* CKPSC = 4 */ + HRTIM_PRESCALER_32, /* CKPSC = 5 */ + HRTIM_PRESCALER_64, /* CKPSC = 6 */ + HRTIM_PRESCALER_128 /* CKPSC = 7 */ +}; + +/* HRTIM Timer Master/Slave mode */ + +enum stm32_hrtim_mode_e +{ + HRTIM_MODE_PRELOAD = (1 << 0), /* Preload enable */ + HRTIM_MODE_HALF = (1 << 1), /* Half mode */ + HRTIM_MODE_RETRIG = (1 << 2), /* Re-triggerable mode */ + HRTIM_MODE_CONT = (1 << 3), /* Continuous mode */ +}; + +/* HRTIM Slave Timer auto-delayed mode + * NOTE: details in STM32F334 Manual + */ + +enum stm32_hrtim_autodelayed_e +{ + /* CMP2 auto-delayed mode */ + + HRTIM_AUTODELAYED_CMP2_MODE1 = 1, /* DELCMP2 = 01 */ + HRTIM_AUTODELAYED_CMP2_MODE2 = 2, /* DELCMP2 = 10 */ + HRTIM_AUTODELAYED_CMP2_MODE3 = 3, /* DELCMP2 = 11 */ + + /* CMP4 auto-delayed mode */ + + HRTIM_AUTODELAYED_CMP4_MODE1 = (1 << 2), /* DELCMP4 = 01 */ + HRTIM_AUTODELAYED_CMP4_MODE2 = (2 << 2), /* DELCMP4 = 10 */ + HRTIM_AUTODELAYED_CMP4_MODE3 = (3 << 2), /* DELCMP4 = 11 */ +}; + +/* HRTIM Slave Timer fault sources Lock */ + +enum stm32_hrtim_tim_fault_lock_e +{ + HRTIM_TIM_FAULT_RW = 0, /* Slave Timer fault source are read/write */ + HRTIM_TIM_FAULT_LOCK = (1 << 7) /* Slave Timer fault source are read only */ +}; + +/* HRTIM Slave Timer Fault configuration */ + +enum stm32_hrtim_tim_fault_src_e +{ + HRTIM_TIM_FAULT1 = (1 << 0), + HRTIM_TIM_FAULT2 = (1 << 2), + HRTIM_TIM_FAULT3 = (1 << 3), + HRTIM_TIM_FAULT4 = (1 << 4), + HRTIM_TIM_FAULT5 = (1 << 5) +}; + +/* HRTIM Fault Source */ + +enum stm32_hrtim_fault_src_e +{ + HRTIM_FAULT_SRC_PIN = 0, + HRTIM_FAULT_SRC_INTERNAL = 1 +}; + +/* HRTIM External Event Source + * NOTE: according to Table 82 from STM32F334XX Manual. + */ + +enum stm32_hrtim_eev_src_e +{ + HRTIM_EEV_SRC_PIN = 0, + HRTIM_EEV_SRC_ANALOG = 1, + HRTIM_EEV_SRC_TRGO = 2, + HRTIM_EEV_SRC_ADC = 3 +}; + +/* HRTIM Fault Polarity */ + +enum stm32_hrtim_fault_pol_e +{ + HRTIM_FAULT_POL_LOW = 0, + HRTIM_FAULT_POL_HIGH = 1 +}; + +/* HRTIM External Event Polarity */ + +enum stm32_hrtim_eev_pol_e +{ + HRTIM_EEV_POL_HIGH = 0, /* External Event is active high */ + HRTIM_EEV_POL_LOW = 1 /* External Event is active low */ +}; + +/* HRTIM External Event sensitivity */ + +enum stm32_hrtim_eev_sen_e +{ + HRTIM_EEV_SEN_LEVEL = 0, /* On active level defined by polarity */ + HRTIM_EEV_SEN_RISING = 1, /* Rising edgne */ + HRTIM_EEV_SEN_FALLING = 2, /* Falling edge */ + HRTIM_EEV_SEN_BOTH = 3 /* Both edges */ +}; + +/* External Event Sampling clock division */ + +enum stm32_hrtim_eev_sampling_e +{ + HRTIM_EEV_SAMPLING_d1 = 0, + HRTIM_EEV_SAMPLING_d2 = 1, + HRTIM_EEV_SAMPLING_d4 = 2, + HRTIM_EEV_SAMPLING_d8 = 3 +}; + +/* HRTIM External Event Mode. + * NOTE: supported only for EEV1-5. + */ + +enum stm32_hrtim_eev_mode_e +{ + HRTIM_EEV_MODE_NORMAL = 0, + HRTIM_EEV_MODE_FAST = 1 /* low latency mode */ +}; + +/* External Event filter. + * NOTE: supported only for EEV6-10. + */ + +enum stm32_hrtim_eev_filter_e +{ + HRTIM_EEV_DISABLE = 0, + HRTIM_EEV_HRT_N2 = 1, + HRTIM_EEV_HRT_N4 = 2, + HRTIM_EEV_HRT_N8 = 3, + HRTIM_EEV_EEVSd2_N6 = 4, + HRTIM_EEV_EEVSd2_N8 = 5, + HRTIM_EEV_EEVSd4_N6 = 6, + HRTIM_EEV_EEVSd4_N8 = 7, + HRTIM_EEV_EEVSd8_N6 = 8, + HRTIM_EEV_EEVSd8_N8 = 9, + HRTIM_EEV_EEVSd16_N5 = 10, + HRTIM_EEV_EEVSd16_N6 = 11, + HRTIM_EEV_EEVSd16_N8 = 12, + HRTIM_EEV_EEVSd32_N5 = 13, + HRTIM_EEV_EEVSd32_N6 = 14, + HRTIM_EEV_EEVSd32_N8 = 15 +}; + +/* Compare register index */ + +enum stm32_hrtim_cmp_index_e +{ + HRTIM_CMP1, + HRTIM_CMP2, + HRTIM_CMP3, + HRTIM_CMP4 +}; + +/* HRTIM Slave Timer Outputs index */ + +enum stm32_output_s +{ + HRTIM_OUT_CH1 = (1 << 0), + HRTIM_OUT_CH2 = (1 << 1) +}; + +/* HRTIM Slave Timers Outputs */ + +enum stm32_outputs_e +{ + HRTIM_OUT_TIMA_CH1 = (1 << 0), + HRTIM_OUT_TIMA_CH2 = (1 << 1), + HRTIM_OUT_TIMB_CH1 = (1 << 2), + HRTIM_OUT_TIMB_CH2 = (1 << 3), + HRTIM_OUT_TIMC_CH1 = (1 << 4), + HRTIM_OUT_TIMC_CH2 = (1 << 5), + HRTIM_OUT_TIMD_CH1 = (1 << 6), + HRTIM_OUT_TIMD_CH2 = (1 << 7), + HRTIM_OUT_TIME_CH1 = (1 << 8), + HRTIM_OUT_TIME_CH2 = (1 << 9) +}; + +/* HRTIM Output polarisation */ + +enum stm32_output_polarisation_e +{ + HRTIM_OUT_POL_POS = 0, + HRTIM_OUT_POL_NEG = 1 +}; + +/* HRTIM Deadtime sign */ + +enum stm32_hrtim_deadtime_sign_e +{ + HRTIM_DT_SIGN_POSITIVE = 0, + HRTIM_DT_SIGN_NEGATIVE = 1 +}; + +/* HRTIM Deadtime types */ + +enum stm32_hrtim_deadtime_edge_e +{ + HRTIM_DT_EDGE_RISING = 0, + HRTIM_DT_EDGE_FALLING = 1 +}; + +/* HRTIM Deadtime lock */ + +enum stm32_hrtim_deadtime_lock_e +{ + HRTIM_DT_RW = 0, + HRTIM_DT_LOCK = 1 +}; + +/* HRTIM Deadtime prescaler */ + +enum stm32_hrtim_deadtime_prescaler_e +{ + HRTIM_DEADTIME_PRESCALER_1 = 0, + HRTIM_DEADTIME_PRESCALER_2 = 1, + HRTIM_DEADTIME_PRESCALER_4 = 2, + HRTIM_DEADTIME_PRESCALER_8 = 3, + HRTIM_DEADTIME_PRESCALER_16 = 4, + HRTIM_DEADTIME_PRESCALER_32 = 5, + HRTIM_DEADTIME_PRESCALER_64 = 6, + HRTIM_DEADTIME_PRESCALER_128 = 7 +}; + +/* Chopper start pulsewidth */ + +enum stm32_hrtim_chopper_start_e +{ + HRTIM_CHP_START_16, + HRTIM_CHP_START_32, + HRTIM_CHP_START_48, + HRTIM_CHP_START_64, + HRTIM_CHP_START_80, + HRTIM_CHP_START_96, + HRTIM_CHP_START_112, + HRTIM_CHP_START_128, + HRTIM_CHP_START_144, + HRTIM_CHP_START_160, + HRTIM_CHP_START_176, + HRTIM_CHP_START_192, + HRTIM_CHP_START_208, + HRTIM_CHP_START_224, + HRTIM_CHP_START_256 +}; + +/* Chopper duty cycle */ + +enum stm32_hrtim_chopper_duty_e +{ + HRTIM_CHP_DUTY_0, + HRTIM_CHP_DUTY_1, + HRTIM_CHP_DUTY_2, + HRTIM_CHP_DUTY_3, + HRTIM_CHP_DUTY_4, + HRTIM_CHP_DUTY_5, + HRTIM_CHP_DUTY_6, + HRTIM_CHP_DUTY_7 +}; + +/* Chopper carrier frequency */ + +enum stm32_hrtim_chopper_freq_e +{ + HRTIM_CHP_FREQ_d16, + HRTIM_CHP_FREQ_d32, + HRTIM_CHP_FREQ_d48, + HRTIM_CHP_FREQ_d64, + HRTIM_CHP_FREQ_d80, + HRTIM_CHP_FREQ_d96, + HRTIM_CHP_FREQ_d112, + HRTIM_CHP_FREQ_d128, + HRTIM_CHP_FREQ_d144, + HRTIM_CHP_FREQ_d160, + HRTIM_CHP_FREQ_d176, + HRTIM_CHP_FREQ_d192, + HRTIM_CHP_FREQ_d208, + HRTIM_CHP_FREQ_d224, + HRTIM_CHP_FREQ_d240, + HRTIM_CHP_FREQ_d256 +}; + +/* HRTIM ADC Trigger 1/3 */ + +enum stm32_hrtim_adc_trq13_e +{ + HRTIM_ADCTRG13_NONE = 0, /* No trigger */ + HRTIM_ADCTRG13_MC1 = (1 << 0), /* Trigger on Master Compare 1 */ + HRTIM_ADCTRG13_MC2 = (1 << 1), /* Trigger on Master Compare 2 */ + HRTIM_ADCTRG13_MC3 = (1 << 2), /* Trigger on Master Compare 3 */ + HRTIM_ADCTRG13_MC4 = (1 << 3), /* Trigger on Master Compare 4 */ + HRTIM_ADCTRG13_MPER = (1 << 4), /* Trigger on Master Period */ + + HRTIM_ADCTRG13_EEV1 = (1 << 5), /* Trigger on External Event 1 */ + HRTIM_ADCTRG13_EEV2 = (1 << 6), /* Trigger on External Event 2 */ + HRTIM_ADCTRG13_EEV3 = (1 << 7), /* Trigger on External Event 3 */ + HRTIM_ADCTRG13_EEV4 = (1 << 8), /* Trigger on External Event 4 */ + HRTIM_ADCTRG13_EEV5 = (1 << 9), /* Trigger on External Event 5 */ + + HRTIM_ADCTRG13_AC2 = (1 << 10), /* Trigger on Timer A Compare 2 */ + HRTIM_ADCTRG13_AC3 = (1 << 11), /* Trigger on Timer A Compare 3 */ + HRTIM_ADCTRG13_AC4 = (1 << 12), /* Trigger on Timer A Compare 4 */ + HRTIM_ADCTRG13_APER = (1 << 13), /* Trigger on Timer A Period */ + HRTIM_ADCTRG13_ARST = (1 << 14), /* Trigger on Timer A Reset */ + + HRTIM_ADCTRG13_BC2 = (1 << 15), /* Trigger on Timer B Compare 2 */ + HRTIM_ADCTRG13_BC3 = (1 << 16), /* Trigger on Timer B Compare 3 */ + HRTIM_ADCTRG13_BC4 = (1 << 17), /* Trigger on Timer B Compare 4 */ + HRTIM_ADCTRG13_BPER = (1 << 18), /* Trigger on Timer B Period */ + HRTIM_ADCTRG13_BRST = (1 << 19), /* Trigger on Timer B Reset */ + + HRTIM_ADCTRG13_CC2 = (1 << 20), /* Trigger on Timer C Compare 2 */ + HRTIM_ADCTRG13_CC3 = (1 << 21), /* Trigger on Timer C Compare 3 */ + HRTIM_ADCTRG13_CC4 = (1 << 22), /* Trigger on Timer C Compare 4 */ + HRTIM_ADCTRG13_CPER = (1 << 23), /* Trigger on Timer C Period */ + + HRTIM_ADCTRG13_DC2 = (1 << 24), /* Trigger on Timer D Compare 2 */ + HRTIM_ADCTRG13_DC3 = (1 << 25), /* Trigger on Timer D Compare 3 */ + HRTIM_ADCTRG13_DC4 = (1 << 26), /* Trigger on Timer D Compare 4 */ + HRTIM_ADCTRG13_DPER = (1 << 27), /* Trigger on Timer D Period */ + + HRTIM_ADCTRG13_EC2 = (1 << 28), /* Trigger on Timer E Compare 2 */ + HRTIM_ADCTRG13_EC3 = (1 << 29), /* Trigger on Timer E Compare 3 */ + HRTIM_ADCTRG13_EC4 = (1 << 30), /* Trigger on Timer E Compare 4 */ + HRTIM_ADCTRG13_EPER = (1 << 31), /* Trigger on Timer E Period */ +}; + +/* HRTIM ADC Trigger 2/4 */ + +enum stm32_hrtim_adc_trq24_e +{ + HRTIM_ADCTRG24_NONE = 0, /* No trigger */ + HRTIM_ADCTRG24_MC1 = (1 << 0), /* Trigger on Master Compare 1 */ + HRTIM_ADCTRG24_MC2 = (1 << 1), /* Trigger on Master Compare 2 */ + HRTIM_ADCTRG24_MC3 = (1 << 2), /* Trigger on Master Compare 3 */ + HRTIM_ADCTRG24_MC4 = (1 << 3), /* Trigger on Master Compare 4 */ + HRTIM_ADCTRG24_MPER = (1 << 4), /* Trigger on Master Period */ + + HRTIM_ADCTRG24_EEV6 = (1 << 5), /* Trigger on External Event 6 */ + HRTIM_ADCTRG24_EEV7 = (1 << 6), /* Trigger on External Event 7 */ + HRTIM_ADCTRG24_EEV8 = (1 << 7), /* Trigger on External Event 8 */ + HRTIM_ADCTRG24_EEV9 = (1 << 8), /* Trigger on External Event 9 */ + HRTIM_ADCTRG24_EEV10 = (1 << 9), /* Trigger on External Event 10 */ + + HRTIM_ADCTRG24_AC2 = (1 << 10), /* Trigger on Timer A Compare 2 */ + HRTIM_ADCTRG24_AC3 = (1 << 11), /* Trigger on Timer A Compare 3 */ + HRTIM_ADCTRG24_AC4 = (1 << 12), /* Trigger on Timer A Compare 4 */ + HRTIM_ADCTRG24_APER = (1 << 13), /* Trigger on Timer A Period */ + + HRTIM_ADCTRG24_BC2 = (1 << 14), /* Trigger on Timer B Compare 2 */ + HRTIM_ADCTRG24_BC3 = (1 << 15), /* Trigger on Timer B Compare 3 */ + HRTIM_ADCTRG24_BC4 = (1 << 16), /* Trigger on Timer B Compare 4 */ + HRTIM_ADCTRG24_BPER = (1 << 17), /* Trigger on Timer B Period */ + + HRTIM_ADCTRG24_CC2 = (1 << 18), /* Trigger on Timer C Compare 2 */ + HRTIM_ADCTRG24_CC3 = (1 << 19), /* Trigger on Timer C Compare 3 */ + HRTIM_ADCTRG24_CC4 = (1 << 20), /* Trigger on Timer C Compare 4 */ + HRTIM_ADCTRG24_CPER = (1 << 21), /* Trigger on Timer C Period */ + HRTIM_ADCTRG24_CRST = (1 << 22), /* Trigger on Timer C Reset */ + + HRTIM_ADCTRG24_DC2 = (1 << 23), /* Trigger on Timer D Compare 2 */ + HRTIM_ADCTRG24_DC3 = (1 << 24), /* Trigger on Timer D Compare 3 */ + HRTIM_ADCTRG24_DC4 = (1 << 25), /* Trigger on Timer D Compare 4 */ + HRTIM_ADCTRG24_DPER = (1 << 26), /* Trigger on Timer D Period */ + HRTIM_ADCTRG24_DRST = (1 << 27), /* Trigger on Timer D Reset */ + + HRTIM_ADCTRG24_EC2 = (1 << 28), /* Trigger on Timer E Compare 2 */ + HRTIM_ADCTRG24_EC3 = (1 << 29), /* Trigger on Timer E Compare 3 */ + HRTIM_ADCTRG24_EC4 = (1 << 30), /* Trigger on Timer E Compare 4 */ + HRTIM_ADCTRG24_ERST = (1 << 31), /* Trigger on Timer E Reset */ +}; + +/* HRTIM DAC synchronization events */ + +enum stm32_hrtim_dac_e +{ + HRTIM_DAC_TRIG_DIS = 0, + HRTIM_DAC_TRIG1 = 1, + HRTIM_DAC_TRIG2 = 2, + HRTIM_DAC_TRIG3 = 3 +}; + +/* HRTIM Timer update events */ + +enum stm32_tim_update_e +{ + HRTIM_UPDATE_NONE = 0, + HRTIM_UPDATE_MSTU = (1 << 0), + HRTIM_UPDATE_TAU = (1 << 2), + HRTIM_UPDATE_TBU = (1 << 3), + HRTIM_UPDATE_TCU = (1 << 4), + HRTIM_UPDATE_TDU = (1 << 5), + HRTIM_UPDATE_TEU = (1 << 6), + HRTIM_UPDATE_RSTU = (1 << 7), + HRTIM_UPDATE_REPU = (1 << 8), +}; + +/* HRTIM Master Timer interrupts */ + +enum stm32_irq_master_e +{ + HRTIM_IRQ_MCMP1 = (1 << 0), /* Master Compare 1 Interrupt */ + HRTIM_IRQ_MCMP2 = (1 << 1), /* Master Compare 2 Interrupt */ + HRTIM_IRQ_MCMP3 = (1 << 2), /* Master Compare 3 Interrupt */ + HRTIM_IRQ_MCMP4 = (1 << 3), /* Master Compare 4 Interrupt */ + HRTIM_IRQ_MREP = (1 << 4), /* Master Repetition Interrupt */ + HRTIM_IRQ_MSYNC = (1 << 5), /* Sync Input Interrupt */ + HRTIM_IRQ_MUPD = (1 << 6) /* Master Update Interrupt */ +}; + +/* HRTIM Slave Timer interrupts */ + +enum stm32_irq_slave_e +{ + HRTIM_IRQ_CMP1 = (1 << 0), /* Slave Compare 1 Interrupt */ + HRTIM_IRQ_CMP2 = (1 << 1), /* Slave Compare 2 Interrupt */ + HRTIM_IRQ_CMP3 = (1 << 2), /* Slave Compare 3 Interrupt */ + HRTIM_IRQ_CMP4 = (1 << 3), /* Slave Compare 4 Interrupt */ + HRTIM_IRQ_REP = (1 << 4), /* Slave Repetition Interrupt */ + HRTIM_IRQ_UPD = (1 << 6), /* Slave Update Interrupt */ + HRTIM_IRQ_CPT1 = (1 << 7), /* Slave Capture 1 Interrupt */ + HRTIM_IRQ_CPT2 = (1 << 8), /* Slave Capture 2 Interrupt */ + HRTIM_IRQ_SETX1 = (1 << 9), /* Slave Output 1 Set Interrupt */ + HRTIM_IRQ_RSTX1 = (1 << 10), /* Slave Output 1 Reset Interrupt */ + HRTIM_IRQ_SETX2 = (1 << 11), /* Slave Output 2 Set Interrupt */ + HRTIM_IRQ_RSTX2 = (1 << 12), /* Slave Output 2 Reset Interrupt */ + HRTIM_IRQ_RST = (1 << 13), /* Slave Reset/roll-over Interrupt */ + HRTIM_IRQ_DLYPRT = (1 << 14) /* Slave Delayed Protection Interrupt */ +}; + +/* HRTIM Common Interrupts */ + +enum stm32_irq_cmn_e +{ + HRTIM_IRQ_FLT1 = (1 << 0), /* Fault 1 Interrupt */ + HRTIM_IRQ_FLT2 = (1 << 1), /* Fault 2 Interrupt */ + HRTIM_IRQ_FLT3 = (1 << 2), /* Fault 3 Interrupt */ + HRTIM_IRQ_FLT4 = (1 << 3), /* Fault 4 Interrupt */ + HRTIM_IRQ_FLT5 = (1 << 4), /* Fault 5 Interrupt */ + HRTIM_IRQ_SYSFLT = (1 << 5), /* System Fault Interrupt */ + HRTIM_IRQ_DLLRDY = (1 << 16), /* DLL Ready Interrupt */ + HRTIM_IRQ_BMPER = (1 << 17) /* Burst Mode Period Interrupt */ +}; + +/* HRTIM DMA requests */ + +enum stm32_hrtim_dma_e +{ + HRTIM_DMA_CMP1 = (1 << 0), /* Common: Compare 1 DMA request */ + HRTIM_DMA_CMP2 = (1 << 1), /* Common: Compare 2 DMA request */ + HRTIM_DMA_CMP3 = (1 << 2), /* Common: Compare 3 DMA request */ + HRTIM_DMA_CMP4 = (1 << 3), /* Common:Compare 4 DMA request */ + HRTIM_DMA_REP = (1 << 4), /* Common: Repetition DMA request */ + HRTIM_DMA_SYNC = (1 << 5), /* Master: Sync Input DMA request */ + HRTIM_DMA_UPD = (1 << 6), /* Common: Update DMA request */ + HRTIM_DMA_CPT1 = (1 << 7), /* Slaves: Capture 1 DMA request */ + HRTIM_DMA_CPT2 = (1 << 8), /* Slaves: Capture 2 DMA request */ + HRTIM_DMA_SET1 = (1 << 9), /* Slaves: Output 1 Set DMA request */ + HRTIM_DMA_RST1 = (1 << 10), /* Slaves: Output 1 Reset DMA request */ + HRTIM_DMA_SET2 = (1 << 11), /* Slaves: Output 2 Set DMA request */ + HRTIM_DMA_RST2 = (1 << 12), /* Slaves: Output 2 Reset DMA request */ + HRTIM_DMA_RST = (1 << 13), /* Slaves: Reset DMA request */ + HRTIM_DMA_DLYPRT = (1 << 14) /* Slaves: Delayed Protection DMA request */ +}; + +/* HRTIM Output IDLE state */ + +enum stm32_hrtim_idle_state +{ + HRTIM_IDLE_INACTIVE = 0, /* Output inactive during IDLE state */ + HRTIM_IDLE_ACTIVE = 1 /* Output active during IDLE state */ +}; + +/* HRTIM Burst Mode clock source */ + +enum stm32_hrtim_burst_source_e +{ + HRTIM_BURST_CLOCK_MASTER = 0, /* Master timer counter reset/roll-over */ + HRTIM_BURST_CLOCK_TIMA = 1, /* Timer A counter reset/roll-over */ + HRTIM_BURST_CLOCK_TIMB = 2, /* Timer B counter reset/roll-over */ + HRTIM_BURST_CLOCK_TIMC = 3, /* Timer C counter reset/roll-over */ + HRTIM_BURST_CLOCK_TIMD = 4, /* Timer D counter reset/roll-over */ + HRTIM_BURST_CLOCK_TIME = 5, /* Timer E counter reset/roll-over */ + HRTIM_BURST_CLOCK_EV1 = 6, /* On-chip Event 1 */ + HRTIM_BURST_CLOCK_EV2 = 7, /* On-chip Event 2 */ + HRTIM_BURST_CLOCK_EV3 = 8, /* On-chip Event 3 */ + HRTIM_BURST_CLOCK_EV4 = 9, /* On-chip Event 4 */ + HRTIM_BURST_CLOCK_HRTIM = 10 /* Prescaled f_HRTIM clock */ +}; + +/* HRTIM Burst Mode prescaler for fHRTIM clock */ + +enum stm32_hrtim_burst_precaler_e +{ + HRTIM_BURST_PRESCALER_1 = 0, + HRTIM_BURST_PRESCALER_2 = 1, + HRTIM_BURST_PRESCALER_4 = 2, + HRTIM_BURST_PRESCALER_8 = 3, + HRTIM_BURST_PRESCALER_16 = 4, + HRTIM_BURST_PRESCALER_32 = 5, + HRTIM_BURST_PRESCALER_64 = 6, + HRTIM_BURST_PRESCALER_128 = 7, + HRTIM_BURST_PRESCALER_256 = 8, + HRTIM_BURST_PRESCALER_512 = 9, + HRTIM_BURST_PRESCALER_1024 = 10, + HRTIM_BURST_PRESCALER_2048 = 11, + HRTIM_BURST_PRESCALER_4096 = 12, + HRTIM_BURST_PRESCALER_8192 = 13, + HRTIM_BURST_PRESCALER_16384 = 14, + HRTIM_BURST_PRESCALER_32768 = 15 +}; + +/* HRTIM Burst Mode triggers */ + +enum stm32_hrtim_burst_triggers_e +{ + HRTIM_BURST_TRG_MSTRST = (1 << 1), + HRTIM_BURST_TRG_MSTREP = (1 << 2), + HRTIM_BURST_TRG_MSTCMP1 = (1 << 3), + HRTIM_BURST_TRG_MSTCMP2 = (1 << 4), + HRTIM_BURST_TRG_MSTCMP3 = (1 << 5), + HRTIM_BURST_TRG_MSTCMP4 = (1 << 6), + HRTIM_BURST_TRG_TARST = (1 << 7), + HRTIM_BURST_TRG_TAREP = (1 << 8), + HRTIM_BURST_TRG_TACMP1 = (1 << 9), + HRTIM_BURST_TRG_TACMP2 = (1 << 10), + HRTIM_BURST_TRG_TBRST = (1 << 11), + HRTIM_BURST_TRG_TBREP = (1 << 12), + HRTIM_BURST_TRG_TBCMP1 = (1 << 13), + HRTIM_BURST_TRG_TBCMP2 = (1 << 14), + HRTIM_BURST_TRG_TCRST = (1 << 15), + HRTIM_BURST_TRG_TCREP = (1 << 16), + HRTIM_BURST_TRG_TCCMP1 = (1 << 17), + HRTIM_BURST_TRG_TCCMP2 = (1 << 18), + HRTIM_BURST_TRG_TDRST = (1 << 19), + HRTIM_BURST_TRG_TDREP = (1 << 20), + HRTIM_BURST_TRG_TDCMP1 = (1 << 21), + HRTIM_BURST_TRG_TDCMP2 = (1 << 22), + HRTIM_BURST_TRG_TERST = (1 << 23), + HRTIM_BURST_TRG_TEREP = (1 << 24), + HRTIM_BURST_TRG_TECMP1 = (1 << 25), + HRTIM_BURST_TRG_TECMP2 = (1 << 26), + HRTIM_BURST_TRG_TAEEV7 = (1 << 27), + HRTIM_BURST_TRG_TDEEV8 = (1 << 28), + HRTIM_BURST_TRG_EEV7 = (1 << 29), + HRTIM_BURST_TRG_EEV8 = (1 << 30), + HRTIM_BURST_TRG_OCHPEV = (1 << 31), +}; + +/* HRTIM Capture triggers */ + +enum stm32_hrtim_capture_index_e +{ + HRTIM_CAPTURE1 = 0, + HRTIM_CAPTURE2 = 1 +}; + +/* HRTIM Capture triggers */ + +enum stm32_hrtim_capture_triggers_e +{ + HRTIM_CAPTURE_TRG_SW = (1 << 0), + HRTIM_CAPTURE_TRG_UPD = (1 << 1), + HRTIM_CAPTURE_TRG_EXEV1 = (1 << 2), + HRTIM_CAPTURE_TRG_EXEV2 = (1 << 3), + HRTIM_CAPTURE_TRG_EXEV3 = (1 << 4), + HRTIM_CAPTURE_TRG_EXEV4 = (1 << 5), + HRTIM_CAPTURE_TRG_EXEV5 = (1 << 6), + HRTIM_CAPTURE_TRG_EXEV6 = (1 << 7), + HRTIM_CAPTURE_TRG_EXEV7 = (1 << 8), + HRTIM_CAPTURE_TRG_EXEV8 = (1 << 9), + HRTIM_CAPTURE_TRG_EXEV9 = (1 << 10), + HRTIM_CAPTURE_TRG_EXEV10 = (1 << 11), + HRTIM_CAPTURE_TRG_TA1SET = (1 << 12), + HRTIM_CAPTURE_TRG_TA1RST = (1 << 13), + HRTIM_CAPTURE_TRG_TACMP1 = (1 << 14), + HRTIM_CAPTURE_TRG_TACMP2 = (1 << 15), + HRTIM_CAPTURE_TRG_TB1SET = (1 << 16), + HRTIM_CAPTURE_TRG_TB1RST = (1 << 17), + HRTIM_CAPTURE_TRG_TBCMP1 = (1 << 18), + HRTIM_CAPTURE_TRG_TBCMP2 = (1 << 19), + HRTIM_CAPTURE_TRG_TC1SET = (1 << 20), + HRTIM_CAPTURE_TRG_TC1RST = (1 << 21), + HRTIM_CAPTURE_TRG_TCCMP1 = (1 << 22), + HRTIM_CAPTURE_TRG_TCCMP2 = (1 << 23), + HRTIM_CAPTURE_TRG_TD1SET = (1 << 24), + HRTIM_CAPTURE_TRG_TD1RST = (1 << 25), + HRTIM_CAPTURE_TRG_TDCMP1 = (1 << 26), + HRTIM_CAPTURE_TRG_TDCMP2 = (1 << 27), + HRTIM_CAPTURE_TRG_TE1SET = (1 << 28), + HRTIM_CAPTURE_TRG_TE1RST = (1 << 29), + HRTIM_CAPTURE_TRG_TECMP1 = (1 << 30), + HRTIM_CAPTURE_TRG_TECMP2 = (1 << 31), +}; + +/* HRTIM vtable */ + +struct hrtim_dev_s; +struct stm32_hrtim_ops_s +{ + int (*cmp_update)(struct hrtim_dev_s *dev, uint8_t timer, + uint8_t index, uint16_t cmp); + int (*per_update)(struct hrtim_dev_s *dev, + uint8_t timer, uint16_t per); + int (*rep_update)(struct hrtim_dev_s *dev, + uint8_t timer, uint8_t rep); + uint16_t (*per_get)(struct hrtim_dev_s *dev, uint8_t timer); + uint16_t (*cmp_get)(struct hrtim_dev_s *dev, uint8_t timer, + uint8_t index); + uint64_t (*fclk_get)(struct hrtim_dev_s *dev, uint8_t timer); + int (*soft_update)(struct hrtim_dev_s *dev, uint8_t timer); + int (*soft_reset)(struct hrtim_dev_s *dev, uint8_t timer); + int (*freq_set)(struct hrtim_dev_s *dev, uint8_t timer, + uint64_t freq); + int (*tim_enable)(struct hrtim_dev_s *dev, uint8_t timers, + bool state); + +#ifdef CONFIG_STM32_HRTIM_INTERRUPTS + int (*irq_ack)(struct hrtim_dev_s *dev, + uint8_t timer, int source); + uint16_t (*irq_get)(struct hrtim_dev_s *dev, uint8_t timer); +#endif +#ifdef CONFIG_STM32_HRTIM_PWM + int (*outputs_enable)(struct hrtim_dev_s *dev, uint16_t outputs, + bool state); + int (*output_set_set)(struct hrtim_dev_s *dev, uint16_t output, + uint32_t set); + int (*output_rst_set)(struct hrtim_dev_s *dev, uint16_t output, + uint32_t rst); +#endif +#ifdef CONFIG_STM32_HRTIM_BURST + int (*burst_enable)(struct hrtim_dev_s *dev, bool state); + int (*burst_cmp_set)(struct hrtim_dev_s *dev, uint16_t cmp); + int (*burst_per_set)(struct hrtim_dev_s *dev, uint16_t per); + int (*burst_pre_set)(struct hrtim_dev_s *dev, uint8_t pre); + uint16_t (*burst_cmp_get)(struct hrtim_dev_s *dev); + uint16_t (*burst_per_get)(struct hrtim_dev_s *dev); + int (*burst_pre_get)(struct hrtim_dev_s *dev); +#endif +#ifdef CONFIG_STM32_HRTIM_CHOPPER + int (*chopper_enable)(struct hrtim_dev_s *dev, uint8_t timer, + uint8_t chan, bool state); +#endif +#ifdef CONFIG_STM32_HRTIM_DEADTIME + int (*deadtime_update)(struct hrtim_dev_s *dev, uint8_t timer, + uint8_t dt, uint16_t value); + uint16_t (*deadtime_get)(struct hrtim_dev_s *dev, uint8_t timer, + uint8_t dt); +#endif +#ifdef CONFIG_STM32_HRTIM_CAPTURE + uint16_t (*capture_get)(struct hrtim_dev_s *dev, uint8_t timer, + uint8_t index); + int (*soft_capture)(struct hrtim_dev_s *dev, uint8_t timer, + uint8_t index); + +#endif +}; + +/* HRTIM device structure */ + +struct hrtim_dev_s +{ +#ifdef CONFIG_STM32_HRTIM + /* Fields managed by common upper half HRTIM logic */ + + uint8_t hd_ocount; /* The number of times the device has been opened */ +#endif + + /* Fields provided by lower half HRTIM logic */ + + const struct stm32_hrtim_ops_s *hd_ops; /* HRTIM operations */ + void *hd_priv; /* Used by the arch-specific logic */ + bool initialized; /* true: HRTIM driver has been initialized */ +}; + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#ifndef __ASSEMBLY__ +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Name: stm32_hrtiminitialize + * + * Description: + * Initialize the HRTIM. + * + * Input Parameters: + * None + * + * Returned Value: + * Valid HRTIM device structure reference on success; a NULL on failure. + * + * Assumptions: + * 1. Clock to the HRTIM block has enabled, + * 2. Board-specific logic has already configured + * + ****************************************************************************/ + +struct hrtim_dev_s *stm32_hrtiminitialize(void); + +/**************************************************************************** + * Name: hrtim_register + ****************************************************************************/ + +#ifndef CONFIG_STM32_HRTIM_DISABLE_CHARDRV +int hrtim_register(const char *path, struct hrtim_dev_s *dev); +#endif + +#undef EXTERN +#ifdef __cplusplus +} +#endif +#endif /* __ASSEMBLY__ */ + +#endif /* CONFIG_STM32_HRTIM1 */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_HRTIM_H */ diff --git a/arch/arm/src/common/stm32/stm32_hsi48.h b/arch/arm/src/common/stm32/stm32_hsi48.h new file mode 100644 index 0000000000000..6116df0117e42 --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_hsi48.h @@ -0,0 +1,38 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_hsi48.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_COMPAT_STM32HSI48_H +#define __ARCH_ARM_SRC_COMMON_COMPAT_STM32HSI48_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#if defined(CONFIG_STM32_HAVE_IP_HSI48_M0_V1) +# include "stm32_hsi48_m0_v1.h" +#else +# error "Unsupported STM32 stm32_hsi48" +#endif + +#endif /* __ARCH_ARM_SRC_COMMON_COMPAT_STM32HSI48_H */ diff --git a/arch/arm/src/common/stm32/stm32_hsi48_m0_v1.c b/arch/arm/src/common/stm32/stm32_hsi48_m0_v1.c new file mode 100644 index 0000000000000..ac6162fc82bed --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_hsi48_m0_v1.c @@ -0,0 +1,187 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_hsi48_m0_v1.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "arm_internal.h" +#include "chip.h" +#include "hardware/stm32_rcc.h" +#include "hardware/stm32_crs.h" + +#include "stm32_hsi48_m0_v1.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#if defined(CONFIG_ARCH_CHIP_STM32F0) +# define STM32_HSI48_REG STM32_RCC_CR2 +# define STM32_HSI48ON RCC_CR2_HSI48ON +# define STM32_HSI48RDY RCC_CR2_HSI48RDY +#elif defined(CONFIG_ARCH_CHIP_STM32L0) +# define STM32_HSI48_REG STM32_RCC_CRRCR +# define STM32_HSI48ON RCC_CRRCR_HSI48ON +# define STM32_HSI48RDY RCC_CRRCR_HSI48RDY +#elif defined(CONFIG_ARCH_CHIP_STM32G0) +# define STM32_HSI48_REG STM32_RCC_CR +# define STM32_HSI48ON RCC_CR_HSI48ON +# define STM32_HSI48RDY RCC_CR_HSI48RDY +#else +# error "Unsupported STM32F0/L0 HSI48" +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_enable_hsi48 + * + * Description: + * On STM32F04x, STM32F07x and STM32F09x devices only, the HSI48 clock + * signal is generated from an internal 48 MHz RC oscillator and can be + * used directly as a system clock or divided and be used as PLL input. + * + * The internal 48MHz RC oscillator is mainly dedicated to provide a high + * precision clock to the USB peripheral by means of a special Clock + * Recovery System (CRS) circuitry, which could use the USB SOF signal or + * the LSE or an external signal to automatically adjust the oscillator + * frequency on-fly, in a very small steps. This oscillator can also be + * used as a system clock source when the system is in run mode; it will + * be disabled as soon as the system enters in Stop or Standby mode. When + * the CRS is not used, the HSI48 RC oscillator runs on its default + * frequency which is subject to manufacturing process variations. + * + * Input Parameters: + * Identifies the synchronization source for the HSI48. When used as the + * USB source clock, this must be set to SYNCSRC_USB. + * + * Returned Value: + * None + * + ****************************************************************************/ + +void stm32_enable_hsi48(enum syncsrc_e syncsrc) +{ + uint32_t regval; + + /* Enable the HSI48 clock. + * + * The HSI48 RC can be switched on and off using the HSI48ON bit in the + * Clock control register (RCC_CR). + * + * The USB clock may be derived from either the PLL clock or from the + * HSI48 clock. This oscillator will be also automatically enabled (by + * hardware forcing HSI48ON bit to one) as soon as it is chosen as a clock + * source for the USB and the peripheral is + * enabled. + */ + + regval = getreg32(STM32_HSI48_REG); + regval |= STM32_HSI48ON; + putreg32(regval, STM32_HSI48_REG); + + /* Wait for the HSI48 clock to stabilize */ + + while ((getreg32(STM32_HSI48_REG) & STM32_HSI48RDY) == 0); + + /* Return if no synchronization */ + + if (syncsrc == SYNCSRC_NONE) + { + return; + } + + /* The CRS synchronization (SYNC) source, selectable through the CRS_CFGR + * register, can be the signal from the external CRS_SYNC pin, the LSE + * clock or the USB SOF signal. + */ + + regval = getreg32(STM32_CRS_CFGR); + regval &= ~CRS_CFGR_SYNCSRC_MASK; + + switch (syncsrc) + { + default: + case SYNCSRC_GPIO: /* GPIO selected as SYNC signal source */ + regval |= CRS_CFGR_SYNCSRC_GPIO; + break; + + case SYNCSRC_LSE: /* LSE selected as SYNC signal source */ + regval |= CRS_CFGR_SYNCSRC_LSE; + break; + + case SYNCSRC_USB: /* USB SOF selected as SYNC signal source */ + regval |= CRS_CFGR_SYNCSRC_USBSOF; + break; + } + + putreg32(regval, STM32_CRS_CFGR); + + /* Set the AUTOTRIMEN bit the CRS_CR register to enables the automatic + * hardware adjustment of TRIM bits according to the measured frequency + * error between the selected SYNC event. + */ + + regval = getreg32(STM32_CRS_CR); + regval |= CRS_CR_AUTOTRIMEN; + putreg32(regval, STM32_CRS_CR); +} + +/**************************************************************************** + * Name: stm32_disable_hsi48 + * + * Description: + * Disable the HSI48 clock. + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void stm32_disable_hsi48(void) +{ + uint32_t regval; + + /* Disable the HSI48 clock */ + + regval = getreg32(STM32_HSI48_REG); + regval &= ~STM32_HSI48ON; + putreg32(regval, STM32_HSI48_REG); + + /* Set other registers to the default settings. */ + + regval = getreg32(STM32_CRS_CFGR); + regval &= ~CRS_CFGR_SYNCSRC_MASK; + putreg32(regval, STM32_CRS_CFGR); + + regval = getreg32(STM32_CRS_CR); + regval &= ~CRS_CR_AUTOTRIMEN; + putreg32(regval, STM32_CRS_CR); +} diff --git a/arch/arm/src/common/stm32/stm32_hsi48_m0_v1.h b/arch/arm/src/common/stm32/stm32_hsi48_m0_v1.h new file mode 100644 index 0000000000000..095c9e62cc67c --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_hsi48_m0_v1.h @@ -0,0 +1,96 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_hsi48_m0_v1.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_HSI48_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_HSI48_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#ifdef CONFIG_STM32_HAVE_HSI48 + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +enum syncsrc_e +{ + SYNCSRC_NONE = 0, /* No SYNC signal */ + SYNCSRC_GPIO, /* GPIO selected as SYNC signal source */ + SYNCSRC_LSE, /* LSE selected as SYNC signal source */ + SYNCSRC_USB, /* USB SOF selected as SYNC signal source */ +}; + +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_enable_hsi48 + * + * Description: + * On STM32F04x, STM32F07x and STM32F09x devices only, the HSI48 clock + * signal is generated from an internal 48 MHz RC oscillator and can be + * used directly as a system clock or divided and be used as PLL input. + * + * The internal 48MHz RC oscillator is mainly dedicated to provide a high + * precision clock to the USB peripheral by means of a special Clock + * Recovery System (CRS) circuitry, which could use the USB SOF signal or + * the LSE or an external signal to automatically adjust the oscillator + * frequency on-fly, in a very small steps. This oscillator can also be + * used as a system clock source when the system is in run mode; it will + * be disabled as soon as the system enters in Stop or Standby mode. When + * the CRS is not used, the HSI48 RC oscillator runs on its default + * frequency which is subject to manufacturing process variations. + * + * Input Parameters: + * Identifies the synchronization source for the HSI48. When used as the + * USB source clock, this must be set to SYNCSRC_USB. + * + * Returned Value: + * None + * + ****************************************************************************/ + +void stm32_enable_hsi48(enum syncsrc_e syncsrc); + +/**************************************************************************** + * Name: stm32_disable_hsi48 + * + * Description: + * Disable the HSI48 clock. + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void stm32_disable_hsi48(void); + +#endif /* CONFIG_STM32_HAVE_HSI48 */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_HSI48_H */ diff --git a/arch/arm/src/common/stm32/stm32_i2c.h b/arch/arm/src/common/stm32/stm32_i2c.h new file mode 100644 index 0000000000000..834372fd75c7c --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_i2c.h @@ -0,0 +1,110 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_i2c.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_I2C_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_I2C_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include "chip.h" +#include "hardware/stm32_i2c.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* If a dynamic timeout is selected, then a non-negative, non-zero micro- + * seconds per byte value must be provided as well. + */ + +#ifdef CONFIG_STM32_I2C_DYNTIMEO +# if CONFIG_STM32_I2C_DYNTIMEO_USECPERBYTE < 1 +# warning "Ignoring CONFIG_STM32_I2C_DYNTIMEO because of CONFIG_STM32_I2C_DYNTIMEO_USECPERBYTE" +# undef CONFIG_STM32_I2C_DYNTIMEO +# endif +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_i2cbus_initialize + * + * Description: + * Initialize the selected I2C port. And return a unique instance of struct + * struct i2c_master_s. This function may be called to obtain multiple + * instances of the interface, each of which may be set up with a + * different frequency and slave address. + * + * Input Parameters: + * Port number (for hardware that has multiple I2C interfaces) + * + * Returned Value: + * Valid I2C device structure reference on success; a NULL on failure + * + ****************************************************************************/ + +struct i2c_master_s *stm32_i2cbus_initialize(int port); + +/**************************************************************************** + * Name: stm32_i2cbus_uninitialize + * + * Description: + * De-initialize the selected I2C port, and power down the device. + * + * Input Parameters: + * Device structure as returned by the stm32_i2cbus_initialize() + * + * Returned Value: + * OK on success, ERROR when internal reference count mismatch or dev + * points to invalid hardware device. + * + ****************************************************************************/ + +int stm32_i2cbus_uninitialize(struct i2c_master_s *dev); + +#if defined(CONFIG_STM32_HAVE_IP_I2C_M3M4_V1) || defined(CONFIG_STM32_HAVE_IP_I2C_M3M4_V2) +/**************************************************************************** + * Name: stm32_i2cbus_slaveinitialize + * + * Description: + * Initialize the selected I2C port as a slave. Return an unique + * instance of struct i2c_slave_s. + * + * Input Parameters: + * Port number (for hardware that has multiple I2C interfaces) + * + * Returned Value: + * Valid I2C device structure reference on success; a NULL on failure + * + ****************************************************************************/ + +struct i2c_slave_s *stm32_i2cbus_slaveinitialize(int port); +#endif + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_I2C_H */ diff --git a/arch/arm/src/common/stm32/stm32_i2c_m0_v1.c b/arch/arm/src/common/stm32/stm32_i2c_m0_v1.c new file mode 100644 index 0000000000000..b8cbdebce4cf2 --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_i2c_m0_v1.c @@ -0,0 +1,2814 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_i2c_m0_v1.c + * + * SPDX-License-Identifier: BSD-3-Clause + * SPDX-FileCopyrightText: 2011 Uros Platise. All rights reserved. + * SPDX-FileCopyrightText: 2016-2017 Gregory Nutt. All rights reserved. + * SPDX-FileCopyrightText: 2016 Doug Vetter. All rights reserved. + * SPDX-FileContributor: Uros Platise + * SPDX-FileContributor: Gregory Nutt + * SPDX-FileContributor: John Wharington + * SPDX-FileContributor: David Sidrane + * SPDX-FileContributor: Bob Feretich + * SPDX-FileContributor: Doug Vetter + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/* -------------------------------------------------------------------------- + * + * STM32 I2C IPv2 I2C Driver + * + * Supports: + * - Master operation: + * Standard-mode (up to 100 kHz) + * Fast-mode (up to 400 kHz) + * Fast-mode Plus (up to 1 MHz) + * fI2CCLK clock source selection is based on STM32_RCC_DCKCFGR2_I2CxSRC + * being set to HSI and the calculations are based on + * STM32_HSI_FREQUENCY of 16mHz + * + * - Multiple instances (shared bus) + * - Interrupt based operation + * - RELOAD support + * + * Unsupported, possible future work: + * - More effective error reporting to higher layers + * - Slave operation + * - Support of fI2CCLK frequencies other than 16Mhz + * - Polled operation (code present but untested) + * - SMBus support + * - Multi-master support + * - IPMI + * + * Test Environment: + * + * - B-L072Z-LRWAN1 + * + * Operational Status: + * + * All supported features have been tested and found to be operational. + * + * Although the RELOAD capability has been tested as it was required to + * implement the I2C_M_NOSTART flag on F3 hardware, the associated + * logic to support the transfer messages with more than 255 byte + * payloads has not been tested as the author lacked access to a real + * device supporting these types of transfers. + * + * Performance Benchmarks: TBD + * + * Time to transfer two messages, each a byte in length, in addition to + * the START condition, in interrupt mode: + * + * DEBUG enabled (development): TBDms + * Excessive delay here is caused by printing to the console and + * is of no concern. + * + * DEBUG disabled (production): TBSus + * Between Messages: TBDus + * Between Bytes: TBDus + * + * Implementation: + * + * - Device: structure as defined by the nuttx/i2c/i2c.h + * + * - Instance: represents each individual access to the I2C driver, obtained + * by the i2c_init(); it extends the Device structure from the + * nuttx/i2c/i2c.h; + * Instance points to OPS, to common I2C Hardware private data and + * contains its own private data including frequency, address and mode of + * operation. + * + * - Private: Private data of an I2C Hardware + * + * High Level Functional Description + * + * This driver works with I2C "messages" (struct i2c_msg_s), which carry a + * buffer intended to transfer data to, or store data read from, the I2C bus. + * + * As the hardware can only transmit or receive one byte at a time the basic + * job of the driver (and the ISR specifically) is to process each message in + * the order they are stored in the message list, one byte at a time. When + * no messages are left the ISR exits and returns the result to the caller. + * + * The order of the list of I2C messages provided to the driver is important + * and dependent upon the hardware in use. A typical I2C transaction between + * the F3 as an I2C Master and some other IC as a I2C Slave requires two + * messages that communicate the: + * + * 1) Subaddress (register offset on the slave device) + * 2) Data sent to or read from the device + * + * These messages will typically be one byte in length but may be up to 2^31 + * bytes in length. Incidentally, the maximum length is limited only because + * i2c_msg_s.length is a signed int for some odd reason. + * + * Interrupt mode relies on the following interrupt events: + * + * TXIS - Transmit interrupt + * (data transmitted to bus and acknowledged) + * NACKF - Not Acknowledge Received + * (data transmitted to bus and NOT acknowledged) + * RXNE - Receive interrupt + * (data received from bus) + * TC - Transfer Complete + * (All bytes in message transferred) + * TCR - Transfer Complete (Reload) + * (Current batch of bytes in message transferred) + * + * The driver currently supports Single Master mode only. Slave mode is not + * supported. Additionally, the driver runs in Software End Mode (AUTOEND + * disabled) so the driver is responsible for telling the hardware what to + * do at the end of a transfer. + * + * -------------------------------------------------------------------------- + * + * Configuration: + * + * To use this driver, enable the following configuration variable: + * + * CONFIG_STM32_I2C1 + * CONFIG_STM32_I2C2 + * CONFIG_STM32_I2C3 + * CONFIG_STM32_I2C4 + * + * To configure the ISR timeout using fixed values + * (CONFIG_STM32_I2C_DYNTIMEO=n): + * + * CONFIG_STM32_I2CTIMEOSEC (Timeout in seconds) + * CONFIG_STM32_I2CTIMEOMS (Timeout in milliseconds) + * CONFIG_STM32_I2CTIMEOTICKS (Timeout in ticks) + * + * To configure the ISR timeout using dynamic values + * (CONFIG_STM32_I2C_DYNTIMEO=y): + * + * CONFIG_STM32_I2C_DYNTIMEO_USECPERBYTE + * (Timeout in microseconds per byte) + * CONFIG_STM32_I2C_DYNTIMEO_STARTSTOP + * (Timeout for start/stop in milliseconds) + * + * Debugging output enabled with: + * + * CONFIG_DEBUG_FEATURES and CONFIG_DEBUG_I2C_{ERROR|WARN|INFO} + * + * ISR Debugging output may be enabled with: + * + * CONFIG_DEBUG_FEATURES and CONFIG_DEBUG_I2C_INFO + * + * -------------------------------------------------------------------------- + * + * References: + * + * RM0431: + * ST STM322xxx and STM323xxx Reference Manual + * Document ID: DocID029480 Revision 1, Jan 2017. + * + * RM0316: + * ST STM326xxx and STM327xxx Reference Manual + * Document ID: DocID028270 Revision 2, April 2016. + * + * DATASHEET: + * ST STM3277xx/STM3278Ax/STM3279x Datasheet + * Document ID: DocID028294, Revision 3, May 2016. + * + * ERRATA: + * STM326xxx/STM327xxx Errata sheet Rev A device limitations + * Document ID: DocID028806, Revision 2, April 2016. + * + * I2CSPEC: + * I2C Bus Specification and User Manual + * Document ID: UM10204, Revision 6, April 2014. + * + * -------------------------------------------------------------------------- + */ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "arm_internal.h" +#include "stm32_rcc.h" +#include "stm32_i2c.h" +#include "stm32_gpio.h" + +/* At least one I2C peripheral must be enabled */ + +#if defined(CONFIG_STM32_I2C1) || defined(CONFIG_STM32_I2C2) || \ + defined(CONFIG_STM32_I2C3) || defined(CONFIG_STM32_I2C4) + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#undef INVALID_CLOCK_SOURCE + +#warning TODO: check I2C clock source and clock frequency. It must be HSI! + +/* CONFIG_I2C_POLLED may be set so that I2C interrupts will not be used. + * Instead, CPU-intensive polling will be used. + */ + +/* Interrupt wait timeout in seconds and milliseconds */ + +#if !defined(CONFIG_STM32_I2CTIMEOSEC) && !defined(CONFIG_STM32_I2CTIMEOMS) +# define CONFIG_STM32_I2CTIMEOSEC 0 +# define CONFIG_STM32_I2CTIMEOMS 500 /* Default is 500 milliseconds */ +# warning "Using Default 500 Ms Timeout" +#elif !defined(CONFIG_STM32_I2CTIMEOSEC) +# define CONFIG_STM32_I2CTIMEOSEC 0 /* User provided milliseconds */ +#elif !defined(CONFIG_STM32_I2CTIMEOMS) +# define CONFIG_STM32_I2CTIMEOMS 0 /* User provided seconds */ +#endif + +/* Interrupt wait time timeout in system timer ticks */ + +#ifndef CONFIG_STM32_I2CTIMEOTICKS +# define CONFIG_STM32_I2CTIMEOTICKS \ + (SEC2TICK(CONFIG_STM32_I2CTIMEOSEC) + MSEC2TICK(CONFIG_STM32_I2CTIMEOMS)) +#endif + +#ifndef CONFIG_STM32_I2C_DYNTIMEO_STARTSTOP +# define CONFIG_STM32_I2C_DYNTIMEO_STARTSTOP TICK2USEC(CONFIG_STM32_I2CTIMEOTICKS) +#endif + +/* Macros to convert a I2C pin to a GPIO output */ + +#define I2C_OUTPUT (GPIO_OUTPUT | GPIO_FLOAT | GPIO_OPENDRAIN |\ + GPIO_SPEED_50MHz | GPIO_OUTPUT_SET) + +#define MKI2C_OUTPUT(p) (((p) & (GPIO_PORT_MASK | GPIO_PIN_MASK)) | I2C_OUTPUT) + +#define I2C_CR1_TXRX (I2C_CR1_RXIE | I2C_CR1_TXIE) +#define I2C_CR1_ALLINTS (I2C_CR1_TXRX | I2C_CR1_TCIE | I2C_CR1_ERRIE) + +/* Unused bit in I2c_ISR used to communicate a bad state has occurred in + * the isr processing + */ + +#define I2C_INT_BAD_STATE 0x8000000 + +/* I2C event tracing + * + * To enable tracing statements which show the details of the state machine + * enable the following configuration variable: + * + * CONFIG_I2C_TRACE + * + * Note: This facility uses syslog, which sends output to the console by + * default. No other debug configuration variables are required. + */ + +#ifndef CONFIG_I2C_TRACE +# define stm32_i2c_tracereset(p) +# define stm32_i2c_tracenew(p,s) +# define stm32_i2c_traceevent(p,e,a) +# define stm32_i2c_tracedump(p) +#endif + +#ifndef CONFIG_I2C_NTRACE +# define CONFIG_I2C_NTRACE 32 +#endif + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/* Interrupt state */ + +enum stm32_intstate_e +{ + INTSTATE_IDLE = 0, /* No I2C activity */ + INTSTATE_WAITING, /* Waiting for completion of interrupt activity */ + INTSTATE_DONE, /* Interrupt activity complete */ +}; + +/* Trace events */ + +enum stm32_trace_e +{ + I2CEVENT_NONE = 0, + I2CEVENT_STATE_ERROR, + I2CEVENT_ISR_SHUTDOWN, + I2CEVENT_ISR_CALL, + I2CEVENT_ISR_EMPTY_CALL, + I2CEVENT_MSG_HANDLING, + I2CEVENT_POLL_NOT_READY, + I2CEVENT_EMPTY_MSG, + I2CEVENT_START, + I2CEVENT_ADDRESS_ACKED, + I2CEVENT_ADDRESS_NACKED, + I2CEVENT_NACK, + I2CEVENT_READ, + I2CEVENT_READ_ERROR, + I2CEVENT_WRITE_TO_DR, + I2CEVENT_WRITE_STOP, + I2CEVENT_WRITE_RESTART, + I2CEVENT_WRITE_NO_RESTART, + I2CEVENT_WRITE_ERROR, + I2CEVENT_WRITE_FLAG_ERROR, + I2CEVENT_TC_RESTART, + I2CEVENT_TC_NO_RESTART +}; + +/* Trace data */ + +struct stm32_trace_s +{ + uint32_t status; /* I2C 32-bit SR2|SR1 status */ + uint32_t count; /* Interrupt count when status change */ + enum stm32_intstate_e event; /* Last event that occurred with this status */ + uint32_t parm; /* Parameter associated with the event */ + clock_t time; /* First of event or first status */ +}; + +/* I2C Device hardware configuration */ + +struct stm32_i2c_config_s +{ + uint32_t base; /* I2C base address */ + uint32_t clk_bit; /* Clock enable bit */ + uint32_t reset_bit; /* Reset bit */ + uint32_t scl_pin; /* GPIO configuration for SCL as SCL */ + uint32_t sda_pin; /* GPIO configuration for SDA as SDA */ +#ifndef CONFIG_I2C_POLLED + uint32_t irq; /* IRQ */ +#endif +}; + +/* I2C Device Private Data */ + +struct stm32_i2c_priv_s +{ + /* Port configuration */ + + const struct stm32_i2c_config_s *config; + + int refs; /* Reference count */ + + mutex_t lock; /* Mutual exclusion mutex */ +#ifndef CONFIG_I2C_POLLED + sem_t sem_isr; /* Interrupt wait semaphore */ +#endif + volatile uint8_t intstate; /* Interrupt handshake (see enum stm32_intstate_e) */ + + uint8_t msgc; /* Message count */ + struct i2c_msg_s *msgv; /* Message list */ + uint8_t *ptr; /* Current message buffer */ + uint32_t frequency; /* Current I2C frequency */ + int dcnt; /* Current message bytes remaining to transfer */ + uint16_t flags; /* Current message flags */ + bool astart; /* START sent */ + + /* I2C trace support */ + +#ifdef CONFIG_I2C_TRACE + int tndx; /* Trace array index */ + clock_t start_time; /* Time when the trace was started */ + + /* The actual trace data */ + + struct stm32_trace_s trace[CONFIG_I2C_NTRACE]; +#endif + + uint32_t status; /* End of transfer SR2|SR1 status */ + +#ifdef CONFIG_PM + struct pm_callback_s pm_cb; /* PM callbacks */ +#endif +}; + +/* I2C Device, Instance */ + +struct stm32_i2c_inst_s +{ + const struct i2c_ops_s *ops; /* Standard I2C operations */ + struct stm32_i2c_priv_s *priv; /* Common driver private data structure */ +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +static inline uint16_t stm32_i2c_getreg(struct stm32_i2c_priv_s *priv, + uint8_t offset); +static inline void stm32_i2c_putreg(struct stm32_i2c_priv_s *priv, + uint8_t offset, uint16_t value); +static inline void stm32_i2c_putreg32(struct stm32_i2c_priv_s *priv, + uint8_t offset, uint32_t value); +static inline void stm32_i2c_modifyreg32(struct stm32_i2c_priv_s *priv, + uint8_t offset, uint32_t clearbits, + uint32_t setbits); +#ifdef CONFIG_STM32_I2C_DYNTIMEO +static uint32_t stm32_i2c_toticks(int msgc, struct i2c_msg_s *msgs); +#endif /* CONFIG_STM32_I2C_DYNTIMEO */ +static inline int stm32_i2c_sem_waitdone(struct stm32_i2c_priv_s *priv); +static inline void stm32_i2c_sem_waitstop(struct stm32_i2c_priv_s *priv); +#ifdef CONFIG_I2C_TRACE +static void stm32_i2c_tracereset(struct stm32_i2c_priv_s *priv); +static void stm32_i2c_tracenew(struct stm32_i2c_priv_s *priv, + uint32_t status); +static void stm32_i2c_traceevent(struct stm32_i2c_priv_s *priv, + enum stm32_trace_e event, uint32_t parm); +static void stm32_i2c_tracedump(struct stm32_i2c_priv_s *priv); +#endif /* CONFIG_I2C_TRACE */ +static void stm32_i2c_setclock(struct stm32_i2c_priv_s *priv, + uint32_t frequency); +static inline void stm32_i2c_sendstart(struct stm32_i2c_priv_s *priv); +static inline void stm32_i2c_sendstop(struct stm32_i2c_priv_s *priv); +static inline +uint32_t stm32_i2c_getstatus(struct stm32_i2c_priv_s *priv); +static int stm32_i2c_isr_process(struct stm32_i2c_priv_s *priv); +#ifndef CONFIG_I2C_POLLED +static int stm32_i2c_isr(int irq, void *context, void *arg); +#endif +static int stm32_i2c_init(struct stm32_i2c_priv_s *priv); +static int stm32_i2c_deinit(struct stm32_i2c_priv_s *priv); + +static int stm32_i2c_process(struct i2c_master_s *dev, + struct i2c_msg_s *msgs, int count); +static int stm32_i2c_transfer(struct i2c_master_s *dev, + struct i2c_msg_s *msgs, int count); +#ifdef CONFIG_I2C_RESET +static int stm32_i2c_reset(struct i2c_master_s *dev); +#endif +#ifdef CONFIG_PM +static int stm32_i2c_pm_prepare(struct pm_callback_s *cb, + int domain, enum pm_state_e pmstate); +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#ifdef CONFIG_STM32_I2C1 +static const struct stm32_i2c_config_s stm32_i2c1_config = +{ + .base = STM32_I2C1_BASE, + .clk_bit = RCC_APB1ENR_I2C1EN, + .reset_bit = RCC_APB1RSTR_I2C1RST, + .scl_pin = GPIO_I2C1_SCL, + .sda_pin = GPIO_I2C1_SDA, +#ifndef CONFIG_I2C_POLLED + .irq = STM32_IRQ_I2C1 +#endif +}; + +static struct stm32_i2c_priv_s stm32_i2c1_priv = +{ + .config = &stm32_i2c1_config, + .refs = 0, + .lock = NXMUTEX_INITIALIZER, +#ifndef CONFIG_I2C_POLLED + .sem_isr = SEM_INITIALIZER(0), +#endif + .intstate = INTSTATE_IDLE, + .msgc = 0, + .msgv = NULL, + .ptr = NULL, + .frequency = 0, + .dcnt = 0, + .flags = 0, + .status = 0, +#ifdef CONFIG_PM + .pm_cb.prepare = stm32_i2c_pm_prepare, +#endif +}; +#endif + +#ifdef CONFIG_STM32_I2C2 +static const struct stm32_i2c_config_s stm32_i2c2_config = +{ + .base = STM32_I2C2_BASE, + .clk_bit = RCC_APB1ENR_I2C2EN, + .reset_bit = RCC_APB1RSTR_I2C2RST, + .scl_pin = GPIO_I2C2_SCL, + .sda_pin = GPIO_I2C2_SDA, +#ifndef CONFIG_I2C_POLLED + .irq = STM32_IRQ_I2C2 +#endif +}; + +static struct stm32_i2c_priv_s stm32_i2c2_priv = +{ + .config = &stm32_i2c2_config, + .refs = 0, + .lock = NXMUTEX_INITIALIZER, +#ifndef CONFIG_I2C_POLLED + .sem_isr = SEM_INITIALIZER(0), +#endif + .intstate = INTSTATE_IDLE, + .msgc = 0, + .msgv = NULL, + .ptr = NULL, + .frequency = 0, + .dcnt = 0, + .flags = 0, + .status = 0, +#ifdef CONFIG_PM + .pm_cb.prepare = stm32_i2c_pm_prepare, +#endif +}; +#endif + +#ifdef CONFIG_STM32_I2C3 +static const struct stm32_i2c_config_s stm32_i2c3_config = +{ + .base = STM32_I2C3_BASE, + .clk_bit = RCC_APB1ENR_I2C3EN, + .reset_bit = RCC_APB1RSTR_I2C3RST, + .scl_pin = GPIO_I2C3_SCL, + .sda_pin = GPIO_I2C3_SDA, +#ifndef CONFIG_I2C_POLLED + .irq = STM32_IRQ_I2C3 +#endif +}; + +static struct stm32_i2c_priv_s stm32_i2c3_priv = +{ + .config = &stm32_i2c3_config, + .refs = 0, + .lock = NXMUTEX_INITIALIZER, +#ifndef CONFIG_I2C_POLLED + .sem_isr = SEM_INITIALIZER(0), +#endif + .intstate = INTSTATE_IDLE, + .msgc = 0, + .msgv = NULL, + .ptr = NULL, + .frequency = 0, + .dcnt = 0, + .flags = 0, + .status = 0, +#ifdef CONFIG_PM + .pm_cb.prepare = stm32_i2c_pm_prepare, +#endif +}; +#endif + +#ifdef CONFIG_STM32_I2C4 +static const struct stm32_i2c_config_s stm32_i2c4_config = +{ + .base = STM32_I2C4_BASE, + .clk_bit = RCC_APB1ENR_I2C4EN, + .reset_bit = RCC_APB1RSTR_I2C4RST, + .scl_pin = GPIO_I2C4_SCL, + .sda_pin = GPIO_I2C4_SDA, +#ifndef CONFIG_I2C_POLLED + .irq = STM32_IRQ_I2C4 +#endif +}; + +static struct stm32_i2c_priv_s stm32_i2c4_priv = +{ + .config = &stm32_i2c4_config, + .refs = 0, + .lock = NXMUTEX_INITIALIZER, +#ifndef CONFIG_I2C_POLLED + .sem_isr = SEM_INITIALIZER(0), +#endif + .intstate = INTSTATE_IDLE, + .msgc = 0, + .msgv = NULL, + .ptr = NULL, + .frequency = 0, + .dcnt = 0, + .flags = 0, + .status = 0, +#ifdef CONFIG_PM + .pm_cb.prepare = stm32_i2c_pm_prepare, +#endif +}; +#endif + +/* Device Structures, Instantiation */ + +static const struct i2c_ops_s stm32_i2c_ops = +{ + .transfer = stm32_i2c_transfer, +#ifdef CONFIG_I2C_RESET + .reset = stm32_i2c_reset, +#endif +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_i2c_getreg + * + * Description: + * Get a 16-bit register value by offset + * + ****************************************************************************/ + +static inline uint16_t stm32_i2c_getreg(struct stm32_i2c_priv_s *priv, + uint8_t offset) +{ + return getreg16(priv->config->base + offset); +} + +/**************************************************************************** + * Name: stm32_i2c_getreg32 + * + * Description: + * Get a 32-bit register value by offset + * + ****************************************************************************/ + +static inline uint32_t stm32_i2c_getreg32(struct stm32_i2c_priv_s *priv, + uint8_t offset) +{ + return getreg32(priv->config->base + offset); +} + +/**************************************************************************** + * Name: stm32_i2c_putreg + * + * Description: + * Put a 16-bit register value by offset + * + ****************************************************************************/ + +static inline void stm32_i2c_putreg(struct stm32_i2c_priv_s *priv, + uint8_t offset, uint16_t value) +{ + putreg16(value, priv->config->base + offset); +} + +/**************************************************************************** + * Name: stm32_i2c_putreg32 + * + * Description: + * Put a 32-bit register value by offset + * + ****************************************************************************/ + +static inline void stm32_i2c_putreg32(struct stm32_i2c_priv_s *priv, + uint8_t offset, uint32_t value) +{ + putreg32(value, priv->config->base + offset); +} + +/**************************************************************************** + * Name: stm32_i2c_modifyreg32 + * + * Description: + * Modify a 32-bit register value by offset + * + ****************************************************************************/ + +static inline void stm32_i2c_modifyreg32(struct stm32_i2c_priv_s *priv, + uint8_t offset, uint32_t clearbits, + uint32_t setbits) +{ + modifyreg32(priv->config->base + offset, clearbits, setbits); +} + +/**************************************************************************** + * Name: stm32_i2c_toticks + * + * Description: + * Return a micro-second delay based on the number of bytes left to be + * processed. + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_I2C_DYNTIMEO +static uint32_t stm32_i2c_toticks(int msgc, struct i2c_msg_s *msgs) +{ + size_t bytecount = 0; + int i; + + /* Count the number of bytes left to process */ + + for (i = 0; i < msgc; i++) + { + bytecount += msgs[i].length; + } + + /* Then return a number of microseconds based on a user provided scaling + * factor. + */ + + return USEC2TICK(CONFIG_STM32_I2C_DYNTIMEO_USECPERBYTE * bytecount); +} +#endif + +/**************************************************************************** + * Name: stm32_i2c_enableinterrupts + * + * Description: + * Enable I2C interrupts + * + ****************************************************************************/ + +#ifndef CONFIG_I2C_POLLED +static inline void stm32_i2c_enableinterrupts(struct stm32_i2c_priv_s *priv) +{ + stm32_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, 0, + (I2C_CR1_TXRX | I2C_CR1_NACKIE)); +} +#endif + +/**************************************************************************** + * Name: stm32_i2c_sem_waitdone + * + * Description: + * Wait for a transfer to complete + * + * There are two versions of this function. The first is included when + * using interrupts while the second is used if polling + * (CONFIG_I2C_POLLED=y). + * + ****************************************************************************/ + +#ifndef CONFIG_I2C_POLLED +static inline int stm32_i2c_sem_waitdone(struct stm32_i2c_priv_s *priv) +{ + irqstate_t flags; + int ret; + + flags = enter_critical_section(); + + /* Enable I2C interrupts */ + + /* The TXIE and RXIE interrupts are enabled initially in stm32_i2c_process. + * The remainder of the interrupts, including error-related, are enabled + * here. + */ + + stm32_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, 0, + (I2C_CR1_ALLINTS & ~I2C_CR1_TXRX)); + + /* Signal the interrupt handler that we are waiting */ + + priv->intstate = INTSTATE_WAITING; + do + { + /* Wait until either the transfer is complete or the timeout expires */ + +#ifdef CONFIG_STM32_I2C_DYNTIMEO + ret = nxsem_tickwait_uninterruptible(&priv->sem_isr, + stm32_i2c_toticks(priv->msgc, priv->msgv)); +#else + ret = nxsem_tickwait_uninterruptible(&priv->sem_isr, + CONFIG_STM32_I2CTIMEOTICKS); +#endif + if (ret < 0) + { + /* Break out of the loop on irrecoverable errors. This would + * include timeouts and mystery errors reported by + * nxsem_tickwait_uninterruptible. + */ + + break; + } + } + + /* Loop until the interrupt level transfer is complete. */ + + while (priv->intstate != INTSTATE_DONE); + + /* Set the interrupt state back to IDLE */ + + priv->intstate = INTSTATE_IDLE; + + /* Disable I2C interrupts */ + + stm32_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, I2C_CR1_ALLINTS, 0); + + leave_critical_section(flags); + return ret; +} +#else +static inline int stm32_i2c_sem_waitdone(struct stm32_i2c_priv_s *priv) +{ + clock_t timeout; + clock_t start; + clock_t elapsed; + int ret; + + /* Get the timeout value */ + +#ifdef CONFIG_STM32_I2C_DYNTIMEO + timeout = stm32_i2c_toticks(priv->msgc, priv->msgv); +#else + timeout = CONFIG_STM32_I2CTIMEOTICKS; +#endif + + /* Signal the interrupt handler that we are waiting. NOTE: Interrupts + * are currently disabled but will be temporarily re-enabled below when + * nxsem_tickwait_uninterruptible() sleeps. + */ + + priv->intstate = INTSTATE_WAITING; + start = clock_systime_ticks(); + + do + { + /* Calculate the elapsed time */ + + elapsed = clock_systime_ticks() - start; + + /* Poll by simply calling the timer interrupt handler until it + * reports that it is done. + */ + + stm32_i2c_isr_process(priv); + } + + /* Loop until the transfer is complete. */ + + while (priv->intstate != INTSTATE_DONE && elapsed < timeout); + + i2cinfo("intstate: %d elapsed: %ld threshold: %ld" + " status: 0x%08" PRIx32 "\n", + priv->intstate, (long)elapsed, (long)timeout, priv->status); + + /* Set the interrupt state back to IDLE */ + + ret = priv->intstate == INTSTATE_DONE ? OK : -ETIMEDOUT; + priv->intstate = INTSTATE_IDLE; + return ret; +} +#endif + +/**************************************************************************** + * Name: stm32_i2c_set_7bit_address + * + * Description: + * + ****************************************************************************/ + +static inline void +stm32_i2c_set_7bit_address(struct stm32_i2c_priv_s *priv) +{ + stm32_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, I2C_CR2_SADD7_MASK, + ((priv->msgv->addr & 0x7f) << I2C_CR2_SADD7_SHIFT)); +} + +/**************************************************************************** + * Name: stm32_i2c_set_bytes_to_transfer + * + * Description: + * + ****************************************************************************/ + +static inline void +stm32_i2c_set_bytes_to_transfer(struct stm32_i2c_priv_s *priv, + uint8_t n_bytes) +{ + stm32_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, I2C_CR2_NBYTES_MASK, + (n_bytes << I2C_CR2_NBYTES_SHIFT)); +} + +/**************************************************************************** + * Name: stm32_i2c_set_write_transfer_dir + * + * Description: + * + ****************************************************************************/ + +static inline void +stm32_i2c_set_write_transfer_dir(struct stm32_i2c_priv_s *priv) +{ + stm32_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, I2C_CR2_RD_WRN, 0); +} + +/**************************************************************************** + * Name: stm32_i2c_set_read_transfer_dir + * + * Description: + * + ****************************************************************************/ + +static inline void +stm32_i2c_set_read_transfer_dir(struct stm32_i2c_priv_s *priv) +{ + stm32_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, 0, I2C_CR2_RD_WRN); +} + +/**************************************************************************** + * Name: stm32_i2c_enable_reload + * + * Description: + * + ****************************************************************************/ + +static inline void +stm32_i2c_enable_reload(struct stm32_i2c_priv_s *priv) +{ + stm32_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, 0, I2C_CR2_RELOAD); +} + +/**************************************************************************** + * Name: stm32_i2c_disable_reload + * + * Description: + * + ****************************************************************************/ + +static inline void +stm32_i2c_disable_reload(struct stm32_i2c_priv_s *priv) +{ + stm32_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, I2C_CR2_RELOAD, 0); +} + +/**************************************************************************** + * Name: stm32_i2c_sem_waitstop + * + * Description: + * Wait for a STOP to complete + * + ****************************************************************************/ + +static inline void stm32_i2c_sem_waitstop(struct stm32_i2c_priv_s *priv) +{ + clock_t start; + clock_t elapsed; + clock_t timeout; + uint32_t cr; + uint32_t sr; + + /* Select a timeout */ + +#ifdef CONFIG_STM32_I2C_DYNTIMEO + timeout = USEC2TICK(CONFIG_STM32_I2C_DYNTIMEO_STARTSTOP); +#else + timeout = CONFIG_STM32_I2CTIMEOTICKS; +#endif + + /* Wait as stop might still be in progress */ + + start = clock_systime_ticks(); + do + { + /* Calculate the elapsed time */ + + elapsed = clock_systime_ticks() - start; + + /* Check for STOP condition */ + + cr = stm32_i2c_getreg32(priv, STM32_I2C_CR2_OFFSET); + if ((cr & I2C_CR2_STOP) == 0) + { + return; + } + + /* Check for timeout error */ + + sr = stm32_i2c_getreg(priv, STM32_I2C_ISR_OFFSET); + if ((sr & I2C_INT_TIMEOUT) != 0) + { + return; + } + } + + /* Loop until the stop is complete or a timeout occurs. */ + + while (elapsed < timeout); + + /* If we get here then a timeout occurred with the STOP condition + * still pending. + */ + + i2cinfo("Timeout with CR: %04" PRIx32 " SR: %04" PRIx32 "\n", + cr, sr); +} + +/**************************************************************************** + * Name: stm32_i2c_trace* + * + * Description: + * I2C trace instrumentation + * + ****************************************************************************/ + +#ifdef CONFIG_I2C_TRACE +static void stm32_i2c_traceclear(struct stm32_i2c_priv_s *priv) +{ + struct stm32_trace_s *trace = &priv->trace[priv->tndx]; + + trace->status = 0; /* I2C 32-bit status */ + trace->count = 0; /* Interrupt count when status change */ + trace->event = I2CEVENT_NONE; /* Last event that occurred with this status */ + trace->parm = 0; /* Parameter associated with the event */ + trace->time = 0; /* Time of first status or event */ +} + +static void stm32_i2c_tracereset(struct stm32_i2c_priv_s *priv) +{ + /* Reset the trace info for a new data collection */ + + priv->tndx = 0; + priv->start_time = clock_systime_ticks(); + stm32_i2c_traceclear(priv); +} + +static void stm32_i2c_tracenew(struct stm32_i2c_priv_s *priv, + uint32_t status) +{ + struct stm32_trace_s *trace = &priv->trace[priv->tndx]; + + /* Is the current entry uninitialized? Has the status changed? */ + + if (trace->count == 0 || status != trace->status) + { + /* Yes.. Was it the status changed? */ + + if (trace->count != 0) + { + /* Yes.. bump up the trace index + * (unless we are out of trace entries) + */ + + if (priv->tndx >= (CONFIG_I2C_NTRACE - 1)) + { + i2cerr("ERROR: Trace table overflow\n"); + return; + } + + priv->tndx++; + trace = &priv->trace[priv->tndx]; + } + + /* Initialize the new trace entry */ + + stm32_i2c_traceclear(priv); + trace->status = status; + trace->count = 1; + trace->time = clock_systime_ticks(); + } + else + { + /* Just increment the count of times that we have seen this status */ + + trace->count++; + } +} + +static void stm32_i2c_traceevent(struct stm32_i2c_priv_s *priv, + enum stm32_trace_e event, uint32_t parm) +{ + struct stm32_trace_s *trace; + + if (event != I2CEVENT_NONE) + { + trace = &priv->trace[priv->tndx]; + + /* Initialize the new trace entry */ + + trace->event = event; + trace->parm = parm; + + /* Bump up the trace index (unless we are out of trace entries) */ + + if (priv->tndx >= (CONFIG_I2C_NTRACE - 1)) + { + i2cerr("ERROR: Trace table overflow\n"); + return; + } + + priv->tndx++; + stm32_i2c_traceclear(priv); + } +} + +static void stm32_i2c_tracedump(struct stm32_i2c_priv_s *priv) +{ + struct stm32_trace_s *trace; + int i; + + syslog(LOG_DEBUG, "Elapsed time: %d\n", + (int)(clock_systime_ticks() - priv->start_time)); + + for (i = 0; i < priv->tndx; i++) + { + trace = &priv->trace[i]; + syslog(LOG_DEBUG, + "%2d. STATUS: %08" PRIx32 " COUNT: %3d EVENT: %2d" + " PARM: %08" PRIx32 " TIME: %d\n", + i + 1, trace->status, trace->count, trace->event, trace->parm, + (int)(trace->time - priv->start_time)); + } +} +#endif /* CONFIG_I2C_TRACE */ + +/**************************************************************************** + * Name: stm32_i2c_setclock + * + * Description: + * + * Sets the I2C bus clock frequency by configuring the I2C_TIMINGR + * register. + * + * This function supports bus clock frequencies of: + * + * 1000Khz (Fast Mode+) + * 400Khz (Fast Mode) + * 100Khz (Standard Mode) + * 10Khz (Standard Mode) + * + * Attempts to set a different frequency will quietly provision the + * default of 10Khz. + * + * The only differences between the various modes of operation (std, fast, + * fast+) are the bus clock speed and setup/hold times. Setup/hold times + * are specified as a MINIMUM time for the given mode, and naturally std + * mode has the longest minimum times. As a result, by provisioning + * setup/hold times for std mode they are also compatible with fast/fast+, + * though some performance degradation occurs in fast/fast+ as a result of + * the times being somewhat longer than strictly required. The values + * remain as they are because reliability is favored over performance. + * + * Clock Selection: + * + * The I2C peripheral clock can be provided by either PCLK1, SYSCLK or the + * HSI. + * + * PCLK1 >------|\ I2CCLK + * SYSCLK >------| |---------> + * HSI >------|/ + * + * HSI is the default and is always 16Mhz. + * + * SYSCLK can, in turn, be derived from the HSI, HSE, PPLCLK. + * + * HSI >------|\ + * | | SYSCLK + * PLL >------| |---------> + * | | + * HSE >------|/ + * + * + * References: + * + * App Note AN4235 and the associated software STSW-STM32126. + * + ****************************************************************************/ + +static void stm32_i2c_setclock(struct stm32_i2c_priv_s *priv, + uint32_t frequency) +{ + uint8_t presc; + uint8_t scl_delay; + uint8_t sda_delay; + uint8_t scl_h_period; + uint8_t scl_l_period; + + /* I2C peripheral must be disabled to update clocking configuration. + * This will SW reset the device. + */ + + stm32_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, I2C_CR1_PE, 0); + + if (frequency != priv->frequency) + { + /* The Speed and timing calculation are based on the following + * fI2CCLK = HSI and is 16Mhz + * Analog filter is on, + * Digital filter off + * Rise Time is 120 ns and fall is 10ns + * Mode is FastMode + */ + + if (frequency == 100000) + { + presc = 0; + scl_delay = 5; + sda_delay = 0; + scl_h_period = 61; + scl_l_period = 89; + } + else if (frequency == 400000) + { + presc = 0; + scl_delay = 3; + sda_delay = 0; + scl_h_period = 6; + scl_l_period = 24; + } + else if (frequency == 1000000) + { + presc = 0; + scl_delay = 2; + sda_delay = 0; + scl_h_period = 1; + scl_l_period = 5; + } + else + { + presc = 7; + scl_delay = 0; + sda_delay = 0; + scl_h_period = 35; + scl_l_period = 162; + } + + uint32_t timingr = + (presc << I2C_TIMINGR_PRESC_SHIFT) | + (scl_delay << I2C_TIMINGR_SCLDEL_SHIFT) | + (sda_delay << I2C_TIMINGR_SDADEL_SHIFT) | + (scl_h_period << I2C_TIMINGR_SCLH_SHIFT) | + (scl_l_period << I2C_TIMINGR_SCLL_SHIFT); + + stm32_i2c_putreg32(priv, STM32_I2C_TIMINGR_OFFSET, timingr); + priv->frequency = frequency; + } + + /* Enable I2C peripheral */ + + stm32_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, 0, I2C_CR1_PE); +} + +/**************************************************************************** + * Name: stm32_i2c_sendstart + * + * Description: + * Send the START condition / force Master mode + * + * A START condition in I2C consists of a single byte that contains both + * the 7 bit slave address and a read/write bit (0 = WRITE, 1 = READ). + * If the address is recognized by one of the slave devices that slave + * device will ACK the byte so that data transfers can begin. + * + * A RESTART (or repeated START per the I2CSPEC) is simply a START + * condition issued in the middle of a transfer (i.e. after the initial + * START and before a STOP). A RESTART sends a new address byte and R/W + * bit to the bus. A RESTART is optional in most cases but mandatory in + * the event the transfer direction is changed. + * + * Most of the time reading data from an I2C slave requires a WRITE of + * the subaddress followed by a READ (and hence a RESTART in between). + * Writing to an I2C slave typically requires only WRITE operations and + * hence no RESTARTs. + * + * This function is therefore called both at the beginning of a transfer + * (START) and at appropriate times during a transfer (RESTART). + * + ****************************************************************************/ + +static inline void stm32_i2c_sendstart(struct stm32_i2c_priv_s *priv) +{ + bool next_norestart = false; + + /* Set the private "current message" data used in protocol processing. + * + * ptr: A pointer to the start of the current message buffer. This is + * advanced after each byte in the current message is transferred. + * + * dcnt: A running counter of the bytes in the current message waiting + * to be transferred. This is decremented each time a byte is + * transferred. + * The hardware normally accepts a maximum of 255 bytes per transfer + * but can support more via the RELOAD mechanism. If dcnt initially + * exceeds 255, the RELOAD mechanism will be enabled automatically. + * + * flags: Used to characterize handling of the current message. + * + * The default flags value is 0 which specifies: + * + * - A transfer direction of WRITE (R/W bit = 0) + * - RESTARTs between all messages + * + * The following flags can be used to override this behavior as follows: + * + * - I2C_M_READ: Sets the transfer direction to READ (R/W bit = 1) + * - I2C_M_NOSTART: Prevents a RESTART from being issued prior to the + * transfer of the message (where allowed by the protocol). + * + */ + + priv->ptr = priv->msgv->buffer; + priv->dcnt = priv->msgv->length; + priv->flags = priv->msgv->flags; + + if ((priv->flags & I2C_M_NOSTART) == 0) + { + /* Flag the first byte as an address byte */ + + priv->astart = true; + } + + /* Enabling RELOAD allows the transfer of: + * + * - individual messages with a payload exceeding 255 bytes + * - multiple messages back to back without a RESTART in between + * + * so we enable it if either of those conditions exist and disable + * it otherwise. + */ + + /* Check if there are multiple messages and the next is a continuation */ + + if (priv->msgc > 1) + { + next_norestart = (((priv->msgv + 1)->flags & I2C_M_NOSTART) != 0); + } + + if (next_norestart || priv->dcnt > 255) + { + i2cinfo("RELOAD enabled: dcnt = %i msgc = %i\n", + priv->dcnt, priv->msgc); + stm32_i2c_enable_reload(priv); + } + else + { + i2cinfo("RELOAD disable: dcnt = %i msgc = %i\n", + priv->dcnt, priv->msgc); + stm32_i2c_disable_reload(priv); + } + + /* Set the number of bytes to transfer (I2C_CR2->NBYTES) to the number of + * bytes in the current message or 255, whichever is lower so as to not + * exceed the hardware maximum allowed. + */ + + if (priv->dcnt > 255) + { + stm32_i2c_set_bytes_to_transfer(priv, 255); + } + else + { + stm32_i2c_set_bytes_to_transfer(priv, priv->dcnt); + } + + /* Set the (7 bit) address. + * 10 bit addressing is not yet supported. + */ + + stm32_i2c_set_7bit_address(priv); + + /* The flag of the current message is used to determine the direction of + * transfer required for the current message. + */ + + if (priv->flags & I2C_M_READ) + { + stm32_i2c_set_read_transfer_dir(priv); + } + else + { + stm32_i2c_set_write_transfer_dir(priv); + } + + /* Set the I2C_CR2->START bit to 1 to instruct the hardware to send the + * START condition using the address and transfer direction data entered. + */ + + i2cinfo("Sending START: dcnt=%i msgc=%i flags=0x%04x\n", + priv->dcnt, priv->msgc, priv->flags); + + stm32_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, 0, I2C_CR2_START); +} + +/**************************************************************************** + * Name: stm32_i2c_sendstop + * + * Description: + * Send the STOP conditions + * + * A STOP condition can be requested by setting the STOP bit in the I2C_CR2 + * register. Setting the STOP bit clears the TC flag and the STOP condition + * is sent on the bus. + * + ****************************************************************************/ + +static inline void stm32_i2c_sendstop(struct stm32_i2c_priv_s *priv) +{ + i2cinfo("Sending STOP\n"); + stm32_i2c_traceevent(priv, I2CEVENT_WRITE_STOP, 0); + + stm32_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, 0, I2C_CR2_STOP); +} + +/**************************************************************************** + * Name: stm32_i2c_getstatus + * + * Description: + * Get 32-bit status (SR1 and SR2 combined) + * + ****************************************************************************/ + +static inline uint32_t stm32_i2c_getstatus(struct stm32_i2c_priv_s *priv) +{ + return getreg32(priv->config->base + STM32_I2C_ISR_OFFSET); +} + +/**************************************************************************** + * Name: stm32_i2c_clearinterrupts + * + * Description: + * Clear all interrupts + * + ****************************************************************************/ + +static inline void stm32_i2c_clearinterrupts(struct stm32_i2c_priv_s *priv) +{ + stm32_i2c_modifyreg32(priv, STM32_I2C_ICR_OFFSET, 0, I2C_ICR_CLEARMASK); +} + +/**************************************************************************** + * Name: stm32_i2c_isr_process + * + * Description: + * Common interrupt service routine (ISR) that handles I2C protocol logic. + * This is instantiated for each configured I2C interface + * (I2C1, I2C2, I2C3). + * + * This ISR is activated and deactivated by: + * + * stm32_i2c_process + * and + * stm32_i2c_waitdone + * + * Input Parameters: + * priv - The private struct of the I2C driver. + * + ****************************************************************************/ + +static int stm32_i2c_isr_process(struct stm32_i2c_priv_s *priv) +{ + uint32_t status; + + /* Get state of the I2C controller */ + + status = stm32_i2c_getreg32(priv, STM32_I2C_ISR_OFFSET); + + i2cinfo("ENTER: status = 0x%08" PRIx32 "\n", status); + + /* Update private version of the state assuming a good state */ + + priv->status = status & ~I2C_INT_BAD_STATE; + + /* If this is a new transmission set up the trace table accordingly */ + + stm32_i2c_tracenew(priv, status); + stm32_i2c_traceevent(priv, I2CEVENT_ISR_CALL, 0); + + /* ------------------- Start of I2C protocol handling ------------------ */ + + /* I2C protocol logic follows. + * It's organized in an if else chain such that only one mode of operation + * is executed every time the ISR is called. + * + * If you need to add additional states to support new features be sure + * they continue the chain (i.e. begin with "else if") and are placed + * before the empty call / error states at the end of the chain. + */ + + /* NACK Handling + * + * This branch is only triggered when the NACK (Not Acknowledge Received) + * interrupt occurs. This interrupt will only fire when the + * I2C_CR1->NACKIE bit is 1. + * + * I2C_ISR->NACKF is set by hardware when a NACK is received after a byte + * is transmitted and the slave fails to acknowledge it. This is the + * opposite of, and mutually exclusive to, the I2C_ISR->TXIS event. + * + * In response to the NACK the hardware automatically triggers generation + * of a STOP condition, terminating the transfer. The only valid response + * to this state is to exit the ISR and report the failure. + * + * To differentiate an "address NACK" from a NACK that might occur during + * the transfer of other bytes the "priv->astart" parameter is + * used. This flag is set to TRUE in sendstart() and set to FALSE when + * the first TXIS event is received, which would be after the first byte + * (the address) is transmitted successfully (acknowledged). + */ + + if (status & I2C_INT_NACK) + { + if (priv->astart == true) + { + /* NACK received on first (address) byte: address is invalid */ + + i2cinfo("NACK: Address invalid: dcnt=%i msgc=%i " + "status=0x%08" PRIx32 "\n", + priv->dcnt, priv->msgc, status); + stm32_i2c_traceevent(priv, + I2CEVENT_ADDRESS_NACKED, priv->msgv->addr); + } + else + { + /* NACK received on regular byte */ + + i2cinfo("NACK: NACK received: dcnt=%i msgc=%i " + "status=0x%08" PRIx32 "\n", + priv->dcnt, priv->msgc, status); + stm32_i2c_traceevent(priv, + I2CEVENT_ADDRESS_NACKED, priv->msgv->addr); + } + + /* Set flags to terminate message transmission: + * + * set message length to -1 to indicate last byte of message sent + * set message count to 0 to indicate no more messages to send + * + * As we fall through the logic in the ISR the message handling block + * will be triggered by these flags and signal the ISR to terminate. + */ + + priv->dcnt = -1; + priv->msgc = 0; + } + + /* Transmit Interrupt Status (TXIS) Handler + * + * This branch is only triggered when the TXIS interrupt occurs. This + * interrupt will only fire when the I2C_CR1->TXIE bit is 1. + * + * This indicates the transmit data register I2C_TXDR has been emptied + * following the successful transmission of a byte and slave + * acknowledgment. + * In this state the I2C_TXDR register is ready to accept another byte + * for transmission. The TXIS bit will be cleared automatically when + * the next byte is written to I2C_TXDR. + * + * The number of TXIS events during the transfer corresponds to NBYTES. + * + * The TXIS flag is not set when a NACK is received. + * + * When RELOAD is disabled (RELOAD=0) and NBYTES data have been + * transferred: + * + * - In Automatic End Mode (AUTOEND=1), a STOP is automatically sent. + * + * Note: Automatic End Mode is not currently supported. + * + * - In Software End Mode (AUTOEND=0), the TC event occurs and the SCL + * line is stretched low in order to allow software actions (STOP, + * RESTART). + * + * When RELOAD is enabled (RELOAD=1) and NBYTES bytes have been + * transferred a TCR event occurs instead and that handler simply updates + * NBYTES which causes TXIS events to continue. The process repeats until + * all bytes in the message have been transferred. + */ + + else if ((priv->flags & (I2C_M_READ)) == 0 && + (status & (I2C_ISR_TXIS)) != 0) + { + /* TXIS interrupt occurred, address valid, ready to transmit */ + + stm32_i2c_traceevent(priv, I2CEVENT_WRITE, 0); + i2cinfo("TXIS: ENTER dcnt = %i msgc = %i status 0x%08" PRIx32 "\n", + priv->dcnt, priv->msgc, status); + + /* The first event after the address byte is sent will be either TXIS + * or NACKF so it's safe to set the astart flag to false on + * the first TXIS event to indicate that it is no longer necessary to + * check for address validity. + */ + + if (priv->astart == true) + { + i2cinfo("TXIS: Address Valid\n"); + stm32_i2c_traceevent(priv, I2CEVENT_ADDRESS_ACKED, + priv->msgv->addr); + priv->astart = false; + } + + /* If one or more bytes in the current message are ready to transmit */ + + if (priv->dcnt > 0) + { + /* Prepare to transmit the current byte */ + + stm32_i2c_traceevent(priv, I2CEVENT_WRITE_TO_DR, priv->dcnt); + i2cinfo("TXIS: Write Data 0x%02x\n", *priv->ptr); + + /* Decrement byte counter */ + + priv->dcnt--; + + /* If we are about to transmit the last byte in the current + * message + */ + + if (priv->dcnt == 0) + { + /* If this is also the last message to send, disable RELOAD so + * TC fires next and issues STOP condition. If we don't do + * this TCR will fire next, and since there are no bytes to + * send we can't write NBYTES to clear TCR so it will fire + * forever. + */ + + if (priv->msgc == 1) + { + stm32_i2c_disable_reload(priv); + } + } + + /* Transmit current byte */ + + stm32_i2c_putreg(priv, STM32_I2C_TXDR_OFFSET, *priv->ptr); + + /* Advance to next byte */ + + priv->ptr++; + } + else + { + /* Unsupported state */ + + i2cerr("ERROR: TXIS Unsupported state detected, dcnt=%i, " + "status 0x%08" PRIx32 "\n", + priv->dcnt, status); + stm32_i2c_traceevent(priv, I2CEVENT_WRITE_ERROR, 0); + + /* Indicate the bad state, + * so that on termination HW will be reset + */ + + priv->status |= I2C_INT_BAD_STATE; + } + + i2cinfo("TXIS: EXIT dcnt = %i msgc = %i status 0x%08" PRIx32 "\n", + priv->dcnt, priv->msgc, status); + } + + /* Receive Buffer Not Empty (RXNE) State Handler + * + * This branch is only triggered when the RXNE interrupt occurs. This + * interrupt will only fire when the I2C_CR1->RXIE bit is 1. + * + * This indicates data has been received from the bus and is waiting to + * be read from the I2C_RXDR register. When I2C_RXDR is read this bit + * is automatically cleared and then an ACK or NACK is sent depending on + * whether we have more bytes to receive. + * + * When RELOAD is disabled and bytes remain to be transferred an + * acknowledge is automatically sent on the bus and the RXNE events + * continue until the last byte is received. + * + * When RELOAD is disabled (RELOAD=0) and BYTES have been transferred: + * + * - In Automatic End Mode (AUTOEND=1), a NACK and a STOP are + * automatically sent after the last received byte. + * + * Note: Automatic End Mode is not currently supported. + * + * - In Software End Mode (AUTOEND=0), a NACK is automatically sent + * after the last received byte, the TC event occurs and the SCL line + * is stretched low in order to allow software actions (STOP, RESTART). + * + * When RELOAD is enabled (RELOAD=1) and NBYTES bytes have been transferred + * a TCR event occurs and that handler simply updates NBYTES which causes + * RXNE events to continue until all bytes have been transferred. + */ + + else if ((priv->flags & (I2C_M_READ)) != 0 && (status & I2C_ISR_RXNE) != 0) + { + /* When read flag is set and the receive buffer is not empty + * (RXNE is set) then the driver can read from the data register. + */ + + stm32_i2c_traceevent(priv, I2CEVENT_READ, 0); + i2cinfo("RXNE: ENTER dcnt = %i msgc = %i status 0x%08" PRIx32 "\n", + priv->dcnt, priv->msgc, status); + + /* If more bytes in the current message */ + + if (priv->dcnt > 0) + { + stm32_i2c_traceevent(priv, I2CEVENT_RCVBYTE, priv->dcnt); + + /* No interrupts or context switches may occur in the following + * sequence. Otherwise, additional bytes may be received. + */ + +#ifdef CONFIG_I2C_POLLED + irqstate_t state = enter_critical_section(); +#endif + /* Receive a byte */ + + *priv->ptr = stm32_i2c_getreg(priv, STM32_I2C_RXDR_OFFSET); + + i2cinfo("RXNE: Read Data 0x%02x\n", *priv->ptr); + + /* Advance buffer to the next byte in the message */ + + priv->ptr++; + + /* Signal byte received */ + + priv->dcnt--; + +#ifdef CONFIG_I2C_POLLED + leave_critical_section(state); +#endif + } + else + { + /* Unsupported state */ + + stm32_i2c_traceevent(priv, I2CEVENT_READ_ERROR, 0); + status = stm32_i2c_getreg(priv, STM32_I2C_ISR_OFFSET); + i2cerr("ERROR: RXNE Unsupported state detected, dcnt=%i, " + "status 0x%08" PRIx32 "\n", + priv->dcnt, status); + + /* Set signals that will terminate ISR and wake waiting thread */ + + priv->status |= I2C_INT_BAD_STATE; + priv->dcnt = -1; + priv->msgc = 0; + } + + i2cinfo("RXNE: EXIT dcnt = %i msgc = %i status 0x%08" PRIx32 "\n", + priv->dcnt, priv->msgc, status); + } + + /* Transfer Complete (TC) State Handler + * + * This branch is only triggered when the TC interrupt occurs. This + * interrupt will only fire when: + * + * I2C_CR1->TCIE = 1 (Transfer Complete Interrupts Enabled) + * I2C_CR2->RELOAD = 0 (Reload Mode Disabled) + * I2C_CR2->AUTOEND = 0 (Autoend Mode Disabled, i.e. Software End Mode) + * + * This event indicates that the number of bytes initially defined + * in NBYTES, meaning, the number of bytes in the current message + * (priv->dcnt) has been successfully transmitted or received. + * + * When the TC interrupt occurs we have two choices to clear it and move + * on, regardless of the transfer direction: + * + * - if more messages follow, perform a repeated START if required + * and then fall through to transmit or receive the next message. + * + * - if no messages follow, perform a STOP and set flags needed to + * exit the ISR. + * + * The fact that the hardware must either RESTART or STOP when a TC + * event occurs explains why, when messages must be sent back to back + * (i.e. without a restart by specifying the I2C_M_NOSTART flag), + * RELOAD mode must be enabled and TCR event(s) must be generated + * instead. See the TCR handler for more. + */ + + else if ((status & I2C_ISR_TC) != 0) + { + i2cinfo("TC: ENTER dcnt = %i msgc = %i status 0x%08" PRIx32 "\n", + priv->dcnt, priv->msgc, status); + + /* Prior message has been sent successfully. Or there could have + * been an error that set msgc to 0; So test for that case as + * we do not want to decrement msgc less then zero nor move msgv + * past the last message. + */ + + if (priv->msgc > 0) + { + priv->msgc--; + } + + /* Are there additional messages remain to be transmitted / received? */ + + if (priv->msgc > 0) + { + i2cinfo("TC: RESTART: dcnt=%i, msgc=%i\n", + priv->dcnt, priv->msgc); + stm32_i2c_traceevent(priv, I2CEVENT_TC_NO_RESTART, priv->msgc); + + /* Issue a START condition. + * + * Note that the first thing sendstart does is update the + * private structure "current message" data (ptr, dcnt, flags) + * so they all reflect the next message in the list so we + * update msgv before we get there. + */ + + /* Advance to the next message in the list */ + + priv->msgv++; + + stm32_i2c_sendstart(priv); + } + else + { + /* Issue a STOP conditions. + * + * No additional messages to transmit / receive, so the + * transfer is indeed complete. Nothing else to do but + * issue a STOP and exit. + */ + + i2cinfo("TC: STOP: dcnt=%i msgc=%i\n", + priv->dcnt, priv->msgc); + stm32_i2c_traceevent(priv, I2CEVENT_STOP, priv->dcnt); + + stm32_i2c_sendstop(priv); + + /* Set signals that will terminate ISR and wake waiting thread */ + + priv->dcnt = -1; + priv->msgc = 0; + } + + i2cinfo("TC: EXIT dcnt = %i msgc = %i status 0x%08" PRIx32 "\n", + priv->dcnt, priv->msgc, status); + } + + /* Transfer Complete (Reload) State Handler + * + * This branch is only triggered when the TCR interrupt occurs. This + * interrupt will only fire when: + * + * I2C_CR1->TCIE = 1 (Transfer Complete Interrupts Enabled) + * I2C_CR2->RELOAD = 1 (Reload Mode Active) + * I2C_CR2->AUTOEND = 0 (Autoend Mode Disabled, i.e. Software End Mode) + * + * This is similar to the TC event except that TCR assumes that additional + * bytes are available to transfer. So despite what its name might imply + * the transfer really isn't complete. + * + * There are two reasons RELOAD would be enabled: + * + * 1) We're trying to send a message with a payload greater than 255 + * bytes. + * 2) We're trying to send messages back to back, regardless of their + * payload size, to avoid a RESTART (i.e. I2C_M_NOSTART flag is set). + * + * These conditions may be true simultaneously, as would be the case if + * we're sending multiple messages with payloads > 255 bytes. So we + * only advance to the next message if we arrive here and dcnt is 0, + * meaning, we're finished with the last message and ready to move to the + * next. + * + * This logic supports the transfer of bytes limited only by the size of + * the i2c_msg_s length variable. The SCL line will be stretched low + * until NBYTES is written with a non-zero value, allowing the transfer + * to continue. + * + * TODO: RESTARTs are required by the I2CSPEC if the next message transfer + * direction changes. Right now the NORESTART flag overrides this + * behavior. May have to introduce logic to issue sendstart, assuming it's + * legal with the hardware in the TCR state. + */ + + else if ((status & I2C_ISR_TCR) != 0) + { + i2cinfo("TCR: ENTER dcnt = %i msgc = %i status 0x%08" PRIx32 "\n", + priv->dcnt, priv->msgc, status); + + /* If no more bytes in the current message to transfer */ + + if (priv->dcnt == 0) + { + /* Prior message has been sent successfully */ + + priv->msgc--; + + /* Advance to the next message in the list */ + + priv->msgv++; + + /* Update current message data */ + + priv->ptr = priv->msgv->buffer; + priv->dcnt = priv->msgv->length; + priv->flags = priv->msgv->flags; + + /* if this is the last message, disable reload so the + * TC event fires next time. + */ + + if (priv->msgc == 0) + { + i2cinfo("TCR: DISABLE RELOAD: dcnt = %i msgc = %i\n", + priv->dcnt, priv->msgc); + + stm32_i2c_disable_reload(priv); + } + + /* Update NBYTES with length of current message */ + + i2cinfo("TCR: NEXT MSG dcnt = %i msgc = %i\n", + priv->dcnt, priv->msgc); + + stm32_i2c_set_bytes_to_transfer(priv, priv->dcnt); + } + else + { + /* More bytes in the current (greater than 255 byte payload + * length) message, so set NBYTES according to the bytes + * remaining in the message, up to a maximum each cycle of 255. + */ + + if (priv->dcnt > 255) + { + i2cinfo( + "TCR: ENABLE RELOAD: NBYTES = 255 dcnt = %i msgc = %i\n", + priv->dcnt, priv->msgc); + + /* More than 255 bytes to transfer so the RELOAD bit is + * set in order to generate a TCR event rather than a TC + * event when 255 bytes are successfully transferred. + * This forces us to return here to update NBYTES and + * continue until NBYTES is set to less than 255 bytes, + * at which point RELOAD will be disabled and a TC + * event will (eventually) follow to officially terminate + * the transfer. + */ + + stm32_i2c_enable_reload(priv); + + stm32_i2c_set_bytes_to_transfer(priv, 255); + } + else + { + /* Less than 255 bytes left to transfer, which means we'll + * complete the transfer of all bytes in the current message + * the next time around. + * + * This means we need to disable the RELOAD functionality so + * we receive a TC event next time which will allow us to + * either RESTART and continue sending the contents of the + * next message or send a STOP condition and exit the ISR. + */ + + i2cinfo("TCR: DISABLE RELOAD: NBYTES = dcnt = %i msgc = %i\n", + priv->dcnt, priv->msgc); + + stm32_i2c_set_bytes_to_transfer(priv, priv->dcnt); + + stm32_i2c_disable_reload(priv); + } + + i2cinfo("TCR: EXIT dcnt = %i msgc = %i status 0x%08" PRIx32 "\n", + priv->dcnt, priv->msgc, status); + } + } + + /* Empty call handler + * + * Case to handle an empty call to the ISR where it has nothing to + * do and should exit immediately. + */ + + else if (priv->dcnt == -1 && priv->msgc == 0) + { + status = stm32_i2c_getreg(priv, STM32_I2C_ISR_OFFSET); + i2cwarn("WARNING: EMPTY CALL: Stopping ISR: status 0x%08" PRIx32 "\n", + status); + stm32_i2c_traceevent(priv, I2CEVENT_ISR_EMPTY_CALL, 0); + } + + /* Error handler + * + * We get to this branch only if we can't handle the current state. + * + * This can happen in interrupt based operation on ARLO & BUSY. + * + * This will happen during polled operation when the device is not + * in one of the supported states when polled. + */ + + else + { +#ifdef CONFIG_I2C_POLLED + stm32_i2c_traceevent(priv, I2CEVENT_POLL_DEV_NOT_RDY, 0); +#else + /* Read rest of the state */ + + status = stm32_i2c_getreg(priv, STM32_I2C_ISR_OFFSET); + + i2cerr("ERROR: Invalid state detected, status 0x%08" PRIx32 "\n", + status); + + /* set condition to terminate ISR and wake waiting thread */ + + priv->status |= I2C_INT_BAD_STATE; + priv->dcnt = -1; + priv->msgc = 0; + stm32_i2c_traceevent(priv, I2CEVENT_STATE_ERROR, 0); +#endif + } + + /* ------------------- End of I2C protocol handling ----------------- */ + + /* Message Handling + * + * Transmission of the whole message chain has been completed. We have to + * terminate the ISR and wake up stm32_i2c_process() that is waiting for + * the ISR cycle to handle the sending/receiving of the messages. + */ + + if (priv->dcnt == -1 && priv->msgc == 0) + { + i2cinfo("MSG: Shutting down I2C ISR\n"); + + stm32_i2c_traceevent(priv, I2CEVENT_ISR_SHUTDOWN, 0); + + /* clear pointer to message content to reflect we are done + * with the current transaction. + */ + + priv->msgv = NULL; + +#ifdef CONFIG_I2C_POLLED + priv->intstate = INTSTATE_DONE; +#else + + /* We will update private state to capture NACK which is used in + * combination with the astart flag to report the type of NACK + * received (address vs data) to the upper layers once we exit the ISR. + * + * Note: status is captured prior to clearing interrupts because + * the NACKF flag will naturally be cleared by that process. + */ + + status = stm32_i2c_getreg32(priv, STM32_I2C_ISR_OFFSET); + + /* Clear all interrupts */ + + stm32_i2c_modifyreg32(priv, STM32_I2C_ICR_OFFSET, 0, + I2C_ICR_CLEARMASK); + + /* Was a bad state detected in the processing? */ + + if (priv->status & I2C_INT_BAD_STATE) + { + /* SW reset device */ + + stm32_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, I2C_CR1_PE, 0); + } + + /* Update private status from above sans I2C_INT_BAD_STATE */ + + priv->status = status; + + /* If a thread is waiting then inform it transfer is complete */ + + if (priv->intstate == INTSTATE_WAITING) + { + nxsem_post(&priv->sem_isr); + priv->intstate = INTSTATE_DONE; + } +#endif + } + + status = stm32_i2c_getreg32(priv, STM32_I2C_ISR_OFFSET); + i2cinfo("EXIT: status = 0x%08" PRIx32 "\n", status); + + return OK; +} + +/**************************************************************************** + * Name: stm32_i2c_isr + * + * Description: + * Common I2C interrupt service routine + * + ****************************************************************************/ + +#ifndef CONFIG_I2C_POLLED +static int stm32_i2c_isr(int irq, void *context, void *arg) +{ + struct stm32_i2c_priv_s *priv = (struct stm32_i2c_priv_s *)arg; + + DEBUGASSERT(priv != NULL); + return stm32_i2c_isr_process(priv); +} +#endif + +/**************************************************************************** + * Name: stm32_i2c_init + * + * Description: + * Setup the I2C hardware, ready for operation with defaults + * + ****************************************************************************/ + +static int stm32_i2c_init(struct stm32_i2c_priv_s *priv) +{ + /* Power-up and configure GPIOs */ + + /* Enable power and reset the peripheral */ + + modifyreg32(STM32_RCC_APB1ENR, 0, priv->config->clk_bit); + modifyreg32(STM32_RCC_APB1RSTR, 0, priv->config->reset_bit); + modifyreg32(STM32_RCC_APB1RSTR, priv->config->reset_bit, 0); + + /* Configure pins */ + + if (stm32_configgpio(priv->config->scl_pin) < 0) + { + return ERROR; + } + + if (stm32_configgpio(priv->config->sda_pin) < 0) + { + stm32_unconfiggpio(priv->config->scl_pin); + return ERROR; + } + +#ifndef CONFIG_I2C_POLLED + /* Attach error and event interrupts to the ISRs */ + + irq_attach(priv->config->irq, stm32_i2c_isr, priv); + up_enable_irq(priv->config->irq); +#endif + + /* TODO: + * - Provide means to set peripheral clock source via RCC_CFGR3_I2CxSW + * - Set to HSI by default, make Kconfig option + */ + + /* Force a frequency update */ + + priv->frequency = 0; + stm32_i2c_setclock(priv, 100000); + + return OK; +} + +/**************************************************************************** + * Name: stm32_i2c_deinit + * + * Description: + * Shutdown the I2C hardware + * + ****************************************************************************/ + +static int stm32_i2c_deinit(struct stm32_i2c_priv_s *priv) +{ + /* Disable I2C */ + + stm32_i2c_putreg32(priv, STM32_I2C_CR1_OFFSET, 0); + + /* Unconfigure GPIO pins */ + + stm32_unconfiggpio(priv->config->scl_pin); + stm32_unconfiggpio(priv->config->sda_pin); + +#ifndef CONFIG_I2C_POLLED + + /* Disable and detach interrupts */ + + up_disable_irq(priv->config->irq); + irq_detach(priv->config->irq); +#endif + + /* Disable clocking */ + + modifyreg32(STM32_RCC_APB1ENR, priv->config->clk_bit, 0); + + return OK; +} + +/**************************************************************************** + * Name: stm32_i2c_process + * + * Description: + * Common I2C transfer logic + * + * Initiates a master mode transaction on the I2C bus to transfer the + * provided messages to and from the slave devices. + * + ****************************************************************************/ + +static int stm32_i2c_process(struct i2c_master_s *dev, + struct i2c_msg_s *msgs, int count) +{ + struct stm32_i2c_inst_s *inst = (struct stm32_i2c_inst_s *)dev; + struct stm32_i2c_priv_s *priv = inst->priv; + uint32_t status = 0; + uint32_t cr1; + uint32_t cr2; + int errval = 0; + int waitrc = 0; + + DEBUGASSERT(count > 0); + + /* Wait for any STOP in progress */ + + stm32_i2c_sem_waitstop(priv); + + /* Clear any pending error interrupts */ + + stm32_i2c_clearinterrupts(priv); + + /* Old transfers are done */ + + priv->msgv = msgs; + priv->msgc = count; + + /* Reset I2C trace logic */ + + stm32_i2c_tracereset(priv); + + /* Set I2C clock frequency toggles I2C_CR1_PE performing a SW reset! */ + + stm32_i2c_setclock(priv, msgs->frequency); + + /* Trigger start condition, then the process moves into the ISR. I2C + * interrupts will be enabled within stm32_i2c_waitdone(). + */ + + priv->status = 0; + +#ifndef CONFIG_I2C_POLLED + /* Enable transmit and receive interrupts here so when we send the start + * condition below the ISR will fire if the data was sent and some + * response from the slave received. All other interrupts relevant to + * our needs are enabled in stm32_i2c_sem_waitdone() below. + */ + + stm32_i2c_enableinterrupts(priv); +#endif + + /* Trigger START condition generation, which also sends the slave address + * with read/write flag and the data in the first message + */ + + stm32_i2c_sendstart(priv); + + /* Wait for the ISR to tell us that the transfer is complete by attempting + * to grab the semaphore that is initially locked by the ISR. If the ISR + * does not release the lock so we can obtain it here prior to the end of + * the timeout period waitdone returns error and we report a timeout. + */ + + waitrc = stm32_i2c_sem_waitdone(priv); + + cr1 = stm32_i2c_getreg32(priv, STM32_I2C_CR1_OFFSET); + cr2 = stm32_i2c_getreg32(priv, STM32_I2C_CR2_OFFSET); +#if !defined(CONFIG_DEBUG_I2C) + UNUSED(cr1); + UNUSED(cr2); +#endif + + /* Status after a normal / good exit is usually 0x00000001, meaning the TXE + * bit is set. That occurs as a result of the I2C_TXDR register being + * empty, and it naturally will be after the last byte is transmitted. + * This bit is cleared when we attempt communications again and re-enable + * the peripheral. The priv->status field can hold additional information + * like a NACK, so we reset the status field to include that information. + */ + + status = stm32_i2c_getstatus(priv); + + /* The priv->status field can hold additional information like a NACK + * event so we include that information. + */ + + status = priv->status & 0xffffffff; + + if (waitrc < 0) + { + /* Connection timed out */ + + errval = ETIMEDOUT; + i2cerr("ERROR: Waitdone timed out CR1: 0x%08" PRIx32 + " CR2: 0x%08" PRIx32 " status: 0x%08" PRIx32 "\n", + cr1, cr2, status); + } + else + { + i2cinfo("Waitdone success: CR1: 0x%08" PRIx32 + " CR2: 0x%08" PRIx32 " status: 0x%08" PRIx32 "\n", + cr1, cr2, status); + } + + UNUSED(cr1); + UNUSED(cr2); + + i2cinfo("priv->status: 0x%08" PRIx32 "\n", priv->status); + + /* Check for error status conditions */ + + if ((status & (I2C_INT_BERR | + I2C_INT_ARLO | + I2C_INT_OVR | + I2C_INT_PECERR | + I2C_INT_TIMEOUT | + I2C_INT_NACK)) != 0) + + { + /* one or more errors in the mask are present */ + + if (status & I2C_INT_BERR) + { + /* Bus Error, ignore it because of errata (revision A,Z) */ + + i2cerr("ERROR: I2C Bus Error\n"); + + /* errval = EIO; */ + } + else if (status & I2C_INT_ARLO) + { + /* Arbitration Lost (master mode) */ + + i2cerr("ERROR: I2C Arbitration Lost\n"); + errval = EAGAIN; + } + + else if (status & I2C_INT_OVR) + { + /* Overrun/Underrun */ + + i2cerr("ERROR: I2C Overrun/Underrun\n"); + errval = EIO; + } + else if (status & I2C_INT_PECERR) + { + /* PEC Error in reception (SMBus Only) */ + + i2cerr("ERROR: I2C PEC Error\n"); + errval = EPROTO; + } + else if (status & I2C_INT_TIMEOUT) + { + /* Timeout or Tlow Error (SMBus Only) */ + + i2cerr("ERROR: I2C Timeout / Tlow Error\n"); + errval = ETIME; + } + else if (status & I2C_INT_NACK) + { + /* NACK Received, flag as "communication error on send" */ + + if (priv->astart == TRUE) + { + i2cwarn("WARNING: I2C Address NACK\n"); + errval = EADDRNOTAVAIL; + } + else + { + i2cwarn("WARNING: I2C Data NACK\n"); + errval = ECOMM; + } + } + else + { + /* Unrecognized error */ + + i2cerr("ERROR: I2C Unrecognized Error"); + errval = EINTR; + } + } + + /* This is not an error, but should not happen. The BUSY signal can be + * present if devices on the bus are in an odd state and need to be reset. + * NOTE: We will only see this busy indication if stm32_i2c_sem_waitdone() + * fails above; Otherwise it is cleared. + */ + + else if ((status & I2C_ISR_BUSY) != 0) + { + /* I2C Bus Busy + * + * This is a status condition rather than an error. + * + * We will only see this busy indication if stm32_i2c_sem_waitdone() + * fails above; Otherwise it is cleared by the hardware when the ISR + * wraps up the transfer with a STOP condition. + */ + + clock_t start = clock_systime_ticks(); + clock_t timeout = USEC2TICK(USEC_PER_SEC / priv->frequency) + 1; + + status = stm32_i2c_getstatus(priv); + + while (status & I2C_ISR_BUSY) + { + if ((clock_systime_ticks() - start) > timeout) + { + i2cerr("ERROR: I2C Bus busy"); + errval = EBUSY; + break; + } + + status = stm32_i2c_getstatus(priv); + } + } + + /* Dump the trace result */ + + stm32_i2c_tracedump(priv); + nxmutex_unlock(&priv->lock); + + return -errval; +} + +/**************************************************************************** + * Name: stm32_i2c_transfer + * + * Description: + * Generic I2C transfer function + * + ****************************************************************************/ + +static int stm32_i2c_transfer(struct i2c_master_s *dev, + struct i2c_msg_s *msgs, int count) +{ + struct stm32_i2c_priv_s *priv; + int ret; + + DEBUGASSERT(dev); + + /* Get I2C private structure */ + + priv = ((struct stm32_i2c_inst_s *)dev)->priv; + + /* Ensure that address or flags don't change meanwhile */ + + ret = nxmutex_lock(&priv->lock); + if (ret >= 0) + { + ret = stm32_i2c_process(dev, msgs, count); + } + + return ret; +} + +/**************************************************************************** + * Name: stm32_i2c_reset + * + * Description: + * Reset an I2C bus + * + ****************************************************************************/ + +#ifdef CONFIG_I2C_RESET +static int stm32_i2c_reset(struct i2c_master_s *dev) +{ + struct stm32_i2c_priv_s *priv; + unsigned int clock_count; + unsigned int stretch_count; + uint32_t scl_gpio; + uint32_t sda_gpio; + uint32_t frequency; + int ret; + + DEBUGASSERT(dev); + + /* Get I2C private structure */ + + priv = ((struct stm32_i2c_inst_s *)dev)->priv; + + /* Our caller must own a ref */ + + DEBUGASSERT(priv->refs > 0); + + /* Lock out other clients */ + + ret = nxmutex_lock(&priv->lock); + if (ret < 0) + { + return ret; + } + + ret = -EIO; + + /* Save the current frequency */ + + frequency = priv->frequency; + + /* De-init the port */ + + stm32_i2c_deinit(priv); + + /* Use GPIO configuration to un-wedge the bus */ + + scl_gpio = MKI2C_OUTPUT(priv->config->scl_pin); + sda_gpio = MKI2C_OUTPUT(priv->config->sda_pin); + + stm32_configgpio(sda_gpio); + stm32_configgpio(scl_gpio); + + /* Let SDA go high */ + + stm32_gpiowrite(sda_gpio, 1); + + /* Clock the bus until any slaves currently driving it let it go. */ + + clock_count = 0; + while (!stm32_gpioread(sda_gpio)) + { + /* Give up if we have tried too hard */ + + if (clock_count++ > 10) + { + goto out; + } + + /* Sniff to make sure that clock stretching has finished. + * + * If the bus never relaxes, the reset has failed. + */ + + stretch_count = 0; + while (!stm32_gpioread(scl_gpio)) + { + /* Give up if we have tried too hard */ + + if (stretch_count++ > 10) + { + goto out; + } + + up_udelay(10); + } + + /* Drive SCL low */ + + stm32_gpiowrite(scl_gpio, 0); + up_udelay(10); + + /* Drive SCL high again */ + + stm32_gpiowrite(scl_gpio, 1); + up_udelay(10); + } + + /* Generate a start followed by a stop to reset slave + * state machines. + */ + + stm32_gpiowrite(sda_gpio, 0); + up_udelay(10); + stm32_gpiowrite(scl_gpio, 0); + up_udelay(10); + stm32_gpiowrite(scl_gpio, 1); + up_udelay(10); + stm32_gpiowrite(sda_gpio, 1); + up_udelay(10); + + /* Revert the GPIO configuration. */ + + stm32_unconfiggpio(sda_gpio); + stm32_unconfiggpio(scl_gpio); + + /* Re-init the port */ + + stm32_i2c_init(priv); + + /* Restore the frequency */ + + stm32_i2c_setclock(priv, frequency); + ret = OK; + +out: + + /* Release the port for reuse by other clients */ + + nxmutex_unlock(&priv->lock); + return ret; +} +#endif /* CONFIG_I2C_RESET */ + +/**************************************************************************** + * Name: stm32_i2c_pm_prepare + * + * Description: + * Request the driver to prepare for a new power state. This is a + * warning that the system is about to enter into a new power state. The + * driver should begin whatever operations that may be required to enter + * power state. The driver may abort the state change mode by returning + * a non-zero value from the callback function. + * + * Input Parameters: + * cb - Returned to the driver. The driver version of the callback + * structure may include additional, driver-specific state + * data at the end of the structure. + * domain - Identifies the activity domain of the state change + * pmstate - Identifies the new PM state + * + * Returned Value: + * 0 (OK) means the event was successfully processed and that the driver + * is prepared for the PM state change. Non-zero means that the driver + * is not prepared to perform the tasks needed achieve this power setting + * and will cause the state change to be aborted. NOTE: The prepare + * method will also be recalled when reverting from lower back to higher + * power consumption modes (say because another driver refused a lower + * power state change). Drivers are not permitted to return non-zero + * values when reverting back to higher power consumption modes! + * + ****************************************************************************/ + +#ifdef CONFIG_PM +static int stm32_i2c_pm_prepare(struct pm_callback_s *cb, int domain, + enum pm_state_e pmstate) +{ + struct stm32_i2c_priv_s *priv = + (struct stm32_i2c_priv_s *)((char *)cb - + offsetof(struct stm32_i2c_priv_s, pm_cb)); + + /* Logic to prepare for a reduced power state goes here. */ + + switch (pmstate) + { + case PM_NORMAL: + case PM_IDLE: + break; + + case PM_STANDBY: + case PM_SLEEP: + + /* Check if exclusive lock for I2C bus is held. */ + + if (nxmutex_is_locked(&priv->lock)) + { + /* Exclusive lock is held, do not allow entry to deeper PM + * states. + */ + + return -EBUSY; + } + + break; + + default: + + /* Should not get here */ + + break; + } + + return OK; +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_i2cbus_initialize + * + * Description: + * Initialize one I2C bus + * + ****************************************************************************/ + +struct i2c_master_s *stm32_i2cbus_initialize(int port) +{ + struct stm32_i2c_priv_s *priv = NULL; /* private data of device with multiple instances */ + struct stm32_i2c_inst_s *inst = NULL; /* device, single instance */ + + /* Get I2C private structure */ + + switch (port) + { +#ifdef CONFIG_STM32_I2C1 + case 1: + priv = (struct stm32_i2c_priv_s *)&stm32_i2c1_priv; + break; +#endif +#ifdef CONFIG_STM32_I2C2 + case 2: + priv = (struct stm32_i2c_priv_s *)&stm32_i2c2_priv; + break; +#endif +#ifdef CONFIG_STM32_I2C3 + case 3: + priv = (struct stm32_i2c_priv_s *)&stm32_i2c3_priv; + break; +#endif +#ifdef CONFIG_STM32_I2C4 + case 4: + priv = (struct stm32_i2c_priv_s *)&stm32_i2c4_priv; + break; +#endif + default: + return NULL; + } + + /* Allocate instance */ + + if (!(inst = kmm_malloc(sizeof(struct stm32_i2c_inst_s)))) + { + return NULL; + } + + /* Initialize instance */ + + inst->ops = &stm32_i2c_ops; + inst->priv = priv; + + /* Init private data for the first time, increment refs count, + * power-up hardware and configure GPIOs. + */ + + nxmutex_lock(&priv->lock); + + if (priv->refs++ == 0) + { + stm32_i2c_init(priv); + +#ifdef CONFIG_PM + /* Register to receive power management callbacks */ + + DEBUGVERIFY(pm_register(&priv->pm_cb)); +#endif + } + + nxmutex_unlock(&priv->lock); + return (struct i2c_master_s *)inst; +} + +/**************************************************************************** + * Name: stm32_i2cbus_uninitialize + * + * Description: + * Uninitialize an I2C bus + * + ****************************************************************************/ + +int stm32_i2cbus_uninitialize(struct i2c_master_s *dev) +{ + struct stm32_i2c_priv_s *priv; + + DEBUGASSERT(dev); + priv = ((struct stm32_i2c_inst_s *)dev)->priv; + + /* Decrement refs and check for underflow */ + + if (priv->refs == 0) + { + return ERROR; + } + + nxmutex_lock(&priv->lock); + if (--priv->refs) + { + nxmutex_unlock(&priv->lock); + kmm_free(dev); + return OK; + } + +#ifdef CONFIG_PM + /* Unregister power management callbacks */ + + pm_unregister(&priv->pm_cb); +#endif + + /* Disable power and other HW resource (GPIO's) */ + + stm32_i2c_deinit(priv); + nxmutex_unlock(&priv->lock); + + kmm_free(dev); + return OK; +} + +#endif /* CONFIG_STM32_I2C1 || CONFIG_STM32_I2C2 || \ + * CONFIG_STM32_I2C3 || CONFIG_STM32_I2C4 */ diff --git a/arch/arm/src/common/stm32/stm32_i2c_m3m4_v1.c b/arch/arm/src/common/stm32/stm32_i2c_m3m4_v1.c new file mode 100644 index 0000000000000..4cc9c4f829187 --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_i2c_m3m4_v1.c @@ -0,0 +1,1945 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_i2c_m3m4_v1.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* Supports: + * - Master operation, 100 kHz (standard) and 400 kHz (full speed) + * - Multiple instances (shared bus) + * - Interrupt based operation + * + * Structure naming: + * - Device: structure as defined by the nuttx/i2c/i2c.h + * - Instance: represents each individual access to the I2C driver, obtained + * by the i2c_init(); it extends the Device structure from the + * nuttx/i2c/i2c.h; + * Instance points to OPS, to common I2C Hardware private data and + * contains its own private data, as frequency, address, mode of + * operation (in the future) + * - Private: Private data of an I2C Hardware + * + * TODO + * - Check for all possible deadlocks (as BUSY='1' I2C needs to be reset in + * HW using the I2C_CR1_SWRST) + * - SMBus support (hardware layer timings are already supported) and add + * SMBA gpio pin + * - Slave support with multiple addresses (on multiple instances): + * - 2 x 7-bit address or + * - 1 x 10 bit addresses + 1 x 7 bit address (?) + * - plus the broadcast address (general call) + * - Multi-master support + * - DMA (to get rid of too many CPU wake-ups and interventions) + * - Be ready for IPMI + */ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#include + +#include "arm_internal.h" +#include "stm32_rcc.h" +#include "stm32_i2c.h" +#include "stm32_waste.h" + +/* At least one I2C peripheral must be enabled */ + +#if defined(CONFIG_STM32_I2C1) || defined(CONFIG_STM32_I2C2) || \ + defined(CONFIG_STM32_I2C3) + +/* This implementation is for the STM32 F1, F2, and F4 only. + * Experimentally enabled for STM32L15XX. + */ + +#if defined(CONFIG_STM32_STM32L15XX) || defined(CONFIG_STM32_STM32F10XX) || \ + defined(CONFIG_STM32_HAVE_IP_DMA_V2) + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#if STM32_PCLK1_FREQUENCY < 4000000 +# warning "STM32_I2C: Periph clk must be at least 4MHz to support 400kHz." +#endif + +#if STM32_PCLK1_FREQUENCY < 2000000 +# error "STM32_I2C: Periph clk must be at least 2MHz to support 100kHz." +#endif + +/* Configuration ************************************************************/ + +/* CONFIG_I2C_POLLED may be set so that I2C interrupts will not be used. + * Instead, CPU-intensive polling will be used. + */ + +/* Interrupt wait timeout in seconds and milliseconds */ + +#if !defined(CONFIG_STM32_I2CTIMEOSEC) && !defined(CONFIG_STM32_I2CTIMEOMS) +# define CONFIG_STM32_I2CTIMEOSEC 0 +# define CONFIG_STM32_I2CTIMEOMS 500 /* Default is 500 milliseconds */ +#elif !defined(CONFIG_STM32_I2CTIMEOSEC) +# define CONFIG_STM32_I2CTIMEOSEC 0 /* User provided milliseconds */ +#elif !defined(CONFIG_STM32_I2CTIMEOMS) +# define CONFIG_STM32_I2CTIMEOMS 0 /* User provided seconds */ +#endif + +/* Interrupt wait time timeout in system timer ticks */ + +#ifndef CONFIG_STM32_I2CTIMEOTICKS +# define CONFIG_STM32_I2CTIMEOTICKS \ + (SEC2TICK(CONFIG_STM32_I2CTIMEOSEC) + MSEC2TICK(CONFIG_STM32_I2CTIMEOMS)) +#endif + +#ifndef CONFIG_STM32_I2C_DYNTIMEO_STARTSTOP +# define CONFIG_STM32_I2C_DYNTIMEO_STARTSTOP TICK2USEC(CONFIG_STM32_I2CTIMEOTICKS) +#endif + +/* On the STM32F103ZE, there is an internal conflict between I2C1 and FSMC. + * In that case, it is necessary to disable FSMC before each I2C1 access + * and re-enable FSMC when the I2C access completes. + */ + +#undef I2C1_FSMC_CONFLICT +#if defined(CONFIG_STM32_STM32F10XX) && defined(CONFIG_STM32_FSMC) && defined(CONFIG_STM32_I2C1) +# define I2C1_FSMC_CONFLICT +#endif + +/* Macros to convert a I2C pin to a GPIO output */ + +#if defined(CONFIG_STM32_STM32L15XX) +# define I2C_OUTPUT (GPIO_OUTPUT | GPIO_OUTPUT_SET | GPIO_OPENDRAIN | \ + GPIO_SPEED_40MHz) +#elif defined(CONFIG_STM32_STM32F10XX) +# define I2C_OUTPUT (GPIO_OUTPUT | GPIO_OUTPUT_SET | GPIO_CNF_OUTOD | \ + GPIO_MODE_50MHz) +#elif defined(CONFIG_STM32_HAVE_IP_DMA_V2) +# define I2C_OUTPUT (GPIO_OUTPUT | GPIO_FLOAT | GPIO_OPENDRAIN |\ + GPIO_SPEED_50MHz | GPIO_OUTPUT_SET) +#endif + +#define MKI2C_OUTPUT(p) (((p) & (GPIO_PORT_MASK | GPIO_PIN_MASK)) | I2C_OUTPUT) + +/* Debug ********************************************************************/ + +/* I2C event trace logic. NOTE: trace uses the internal, non-standard, + * low-level debug interface syslog() but does not require that any other + * debug is enabled. + */ + +#ifndef CONFIG_I2C_TRACE +# define stm32_i2c_tracereset(p) +# define stm32_i2c_tracenew(p,s) +# define stm32_i2c_traceevent(p,e,a) +# define stm32_i2c_tracedump(p) +#endif + +#ifndef CONFIG_I2C_NTRACE +# define CONFIG_I2C_NTRACE 32 +#endif + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/* Interrupt state */ + +enum stm32_intstate_e +{ + INTSTATE_IDLE = 0, /* No I2C activity */ + INTSTATE_WAITING, /* Waiting for completion of interrupt activity */ + INTSTATE_DONE, /* Interrupt activity complete */ +}; + +/* Trace events */ + +enum stm32_trace_e +{ + I2CEVENT_NONE = 0, /* No events have occurred with this status */ + I2CEVENT_SENDADDR, /* Start/Master bit set and address sent, param = msgc */ + I2CEVENT_SENDBYTE, /* Send byte, param = dcnt */ + I2CEVENT_ITBUFEN, /* Enable buffer interrupts, param = 0 */ + I2CEVENT_RCVBYTE, /* Read more dta, param = dcnt */ + I2CEVENT_REITBUFEN, /* Re-enable buffer interrupts, param = 0 */ + I2CEVENT_DISITBUFEN, /* Disable buffer interrupts, param = 0 */ + I2CEVENT_BTFNOSTART, /* BTF on last byte with no restart, param = msgc */ + I2CEVENT_BTFRESTART, /* Last byte sent, re-starting, param = msgc */ + I2CEVENT_BTFSTOP, /* Last byte sten, send stop, param = 0 */ + I2CEVENT_ERROR /* Error occurred, param = 0 */ +}; + +/* Trace data */ + +struct stm32_trace_s +{ + uint32_t status; /* I2C 32-bit SR2|SR1 status */ + uint32_t count; /* Interrupt count when status change */ + enum stm32_intstate_e event; /* Last event that occurred with this status */ + uint32_t parm; /* Parameter associated with the event */ + clock_t time; /* First of event or first status */ +}; + +/* I2C Device hardware configuration */ + +struct stm32_i2c_config_s +{ + uint32_t base; /* I2C base address */ + uint32_t clk_bit; /* Clock enable bit */ + uint32_t reset_bit; /* Reset bit */ + uint32_t scl_pin; /* GPIO configuration for SCL as SCL */ + uint32_t sda_pin; /* GPIO configuration for SDA as SDA */ +#ifndef CONFIG_I2C_POLLED + uint32_t ev_irq; /* Event IRQ */ + uint32_t er_irq; /* Error IRQ */ +#endif +}; + +/* I2C Device Private Data */ + +struct stm32_i2c_priv_s +{ + /* Standard I2C operations */ + + const struct i2c_ops_s *ops; + + /* Port configuration */ + + const struct stm32_i2c_config_s *config; + + int refs; /* Reference count */ + mutex_t lock; /* Mutual exclusion lock */ +#ifndef CONFIG_I2C_POLLED + sem_t sem_isr; /* Interrupt wait semaphore */ +#endif + volatile uint8_t intstate; /* Interrupt handshake (see enum stm32_intstate_e) */ + + uint8_t msgc; /* Message count */ + struct i2c_msg_s *msgv; /* Message list */ + uint8_t *ptr; /* Current message buffer */ + uint32_t frequency; /* Current I2C frequency */ + int dcnt; /* Current message length */ + uint16_t flags; /* Current message flags */ + + /* I2C trace support */ + +#ifdef CONFIG_I2C_TRACE + int tndx; /* Trace array index */ + clock_t start_time; /* Time when the trace was started */ + + /* The actual trace data */ + + struct stm32_trace_s trace[CONFIG_I2C_NTRACE]; +#endif + + uint32_t status; /* End of transfer SR2|SR1 status */ +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +static inline uint16_t stm32_i2c_getreg(struct stm32_i2c_priv_s *priv, + uint8_t offset); +static inline void stm32_i2c_putreg(struct stm32_i2c_priv_s *priv, + uint8_t offset, uint16_t value); +static inline void stm32_i2c_modifyreg(struct stm32_i2c_priv_s *priv, + uint8_t offset, uint16_t clearbits, + uint16_t setbits); + +#ifdef CONFIG_STM32_I2C_DYNTIMEO +static uint32_t stm32_i2c_toticks(int msgc, struct i2c_msg_s *msgs); +#endif /* CONFIG_STM32_I2C_DYNTIMEO */ + +static inline int stm32_i2c_sem_waitdone(struct stm32_i2c_priv_s *priv); +static inline void stm32_i2c_sem_waitstop(struct stm32_i2c_priv_s *priv); + +#ifdef CONFIG_I2C_TRACE +static void stm32_i2c_tracereset(struct stm32_i2c_priv_s *priv); +static void stm32_i2c_tracenew(struct stm32_i2c_priv_s *priv, + uint32_t status); +static void stm32_i2c_traceevent(struct stm32_i2c_priv_s *priv, + enum stm32_trace_e event, uint32_t parm); +static void stm32_i2c_tracedump(struct stm32_i2c_priv_s *priv); +#endif /* CONFIG_I2C_TRACE */ + +static void stm32_i2c_setclock(struct stm32_i2c_priv_s *priv, + uint32_t frequency); +static inline void stm32_i2c_sendstart(struct stm32_i2c_priv_s *priv); +static inline void stm32_i2c_clrstart(struct stm32_i2c_priv_s *priv); +static inline void stm32_i2c_sendstop(struct stm32_i2c_priv_s *priv); +static inline +uint32_t stm32_i2c_getstatus(struct stm32_i2c_priv_s *priv); + +#ifdef I2C1_FSMC_CONFLICT +static inline +uint32_t stm32_i2c_disablefsmc(struct stm32_i2c_priv_s *priv); +static inline void stm32_i2c_enablefsmc(uint32_t ahbenr); +#endif /* I2C1_FSMC_CONFLICT */ + +static int stm32_i2c_isr_process(struct stm32_i2c_priv_s *priv); + +#ifndef CONFIG_I2C_POLLED +static int stm32_i2c_isr(int irq, void *context, void *arg); +#endif /* !CONFIG_I2C_POLLED */ + +static int stm32_i2c_init(struct stm32_i2c_priv_s *priv); +static int stm32_i2c_deinit(struct stm32_i2c_priv_s *priv); +static int stm32_i2c_transfer(struct i2c_master_s *dev, + struct i2c_msg_s *msgs, int count); +#ifdef CONFIG_I2C_RESET +static int stm32_i2c_reset(struct i2c_master_s *dev); +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* Trace events strings */ + +#ifdef CONFIG_I2C_TRACE +static const char *g_trace_names[] = +{ + "NONE ", + "SENDADDR ", + "SENDBYTE ", + "ITBUFEN ", + "RCVBYTE ", + "REITBUFEN ", + "DISITBUFEN", + "BTFNOSTART", + "BTFRESTART", + "BTFSTOP ", + "ERROR " +}; +#endif + +/* I2C interface */ + +static const struct i2c_ops_s stm32_i2c_ops = +{ + .transfer = stm32_i2c_transfer +#ifdef CONFIG_I2C_RESET + , .reset = stm32_i2c_reset +#endif +}; + +/* I2C device structures */ + +#ifdef CONFIG_STM32_I2C1 +static const struct stm32_i2c_config_s stm32_i2c1_config = +{ + .base = STM32_I2C1_BASE, + .clk_bit = RCC_APB1ENR_I2C1EN, + .reset_bit = RCC_APB1RSTR_I2C1RST, + .scl_pin = GPIO_I2C1_SCL, + .sda_pin = GPIO_I2C1_SDA, +#ifndef CONFIG_I2C_POLLED + .ev_irq = STM32_IRQ_I2C1EV, + .er_irq = STM32_IRQ_I2C1ER +#endif +}; + +static struct stm32_i2c_priv_s stm32_i2c1_priv = +{ + .ops = &stm32_i2c_ops, + .config = &stm32_i2c1_config, + .refs = 0, + .lock = NXMUTEX_INITIALIZER, +#ifndef CONFIG_I2C_POLLED + .sem_isr = SEM_INITIALIZER(0), +#endif + .intstate = INTSTATE_IDLE, + .msgc = 0, + .msgv = NULL, + .ptr = NULL, + .dcnt = 0, + .flags = 0, + .status = 0 +}; +#endif + +#ifdef CONFIG_STM32_I2C2 +static const struct stm32_i2c_config_s stm32_i2c2_config = +{ + .base = STM32_I2C2_BASE, + .clk_bit = RCC_APB1ENR_I2C2EN, + .reset_bit = RCC_APB1RSTR_I2C2RST, + .scl_pin = GPIO_I2C2_SCL, + .sda_pin = GPIO_I2C2_SDA, +#ifndef CONFIG_I2C_POLLED + .ev_irq = STM32_IRQ_I2C2EV, + .er_irq = STM32_IRQ_I2C2ER +#endif +}; + +static struct stm32_i2c_priv_s stm32_i2c2_priv = +{ + .ops = &stm32_i2c_ops, + .config = &stm32_i2c2_config, + .refs = 0, + .lock = NXMUTEX_INITIALIZER, +#ifndef CONFIG_I2C_POLLED + .sem_isr = SEM_INITIALIZER(0), +#endif + .intstate = INTSTATE_IDLE, + .msgc = 0, + .msgv = NULL, + .ptr = NULL, + .dcnt = 0, + .flags = 0, + .status = 0 +}; +#endif + +#ifdef CONFIG_STM32_I2C3 +static const struct stm32_i2c_config_s stm32_i2c3_config = +{ + .base = STM32_I2C3_BASE, + .clk_bit = RCC_APB1ENR_I2C3EN, + .reset_bit = RCC_APB1RSTR_I2C3RST, + .scl_pin = GPIO_I2C3_SCL, + .sda_pin = GPIO_I2C3_SDA, +#ifndef CONFIG_I2C_POLLED + .ev_irq = STM32_IRQ_I2C3EV, + .er_irq = STM32_IRQ_I2C3ER +#endif +}; + +static struct stm32_i2c_priv_s stm32_i2c3_priv = +{ + .ops = &stm32_i2c_ops, + .config = &stm32_i2c3_config, + .refs = 0, + .lock = NXMUTEX_INITIALIZER, +#ifndef CONFIG_I2C_POLLED + .sem_isr = SEM_INITIALIZER(0), +#endif + .intstate = INTSTATE_IDLE, + .msgc = 0, + .msgv = NULL, + .ptr = NULL, + .dcnt = 0, + .flags = 0, + .status = 0 +}; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_i2c_getreg + * + * Description: + * Get a 16-bit register value by offset + * + ****************************************************************************/ + +static inline uint16_t stm32_i2c_getreg(struct stm32_i2c_priv_s *priv, + uint8_t offset) +{ + return getreg16(priv->config->base + offset); +} + +/**************************************************************************** + * Name: stm32_i2c_putreg + * + * Description: + * Put a 16-bit register value by offset + * + ****************************************************************************/ + +static inline void stm32_i2c_putreg(struct stm32_i2c_priv_s *priv, + uint8_t offset, uint16_t value) +{ + putreg16(value, priv->config->base + offset); +} + +/**************************************************************************** + * Name: stm32_i2c_modifyreg + * + * Description: + * Modify a 16-bit register value by offset + * + ****************************************************************************/ + +static inline void stm32_i2c_modifyreg(struct stm32_i2c_priv_s *priv, + uint8_t offset, uint16_t clearbits, + uint16_t setbits) +{ + modifyreg16(priv->config->base + offset, clearbits, setbits); +} + +/**************************************************************************** + * Name: stm32_i2c_toticks + * + * Description: + * Return a micro-second delay based on the number of bytes left to be + * processed. + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_I2C_DYNTIMEO +static uint32_t stm32_i2c_toticks(int msgc, struct i2c_msg_s *msgs) +{ + size_t bytecount = 0; + int i; + + /* Count the number of bytes left to process */ + + for (i = 0; i < msgc; i++) + { + bytecount += msgs[i].length; + } + + /* Then return a number of microseconds based on a user provided scaling + * factor. + */ + + return USEC2TICK(CONFIG_STM32_I2C_DYNTIMEO_USECPERBYTE * bytecount); +} +#endif + +/**************************************************************************** + * Name: stm32_i2c_sem_waitdone + * + * Description: + * Wait for a transfer to complete + * + ****************************************************************************/ + +#ifndef CONFIG_I2C_POLLED +static inline int stm32_i2c_sem_waitdone(struct stm32_i2c_priv_s *priv) +{ + irqstate_t flags; + uint32_t regval; + int ret; + + flags = enter_critical_section(); + + /* Enable I2C interrupts */ + + regval = stm32_i2c_getreg(priv, STM32_I2C_CR2_OFFSET); + regval |= (I2C_CR2_ITERREN | I2C_CR2_ITEVFEN); + stm32_i2c_putreg(priv, STM32_I2C_CR2_OFFSET, regval); + + /* Signal the interrupt handler that we are waiting. NOTE: Interrupts + * are currently disabled but will be temporarily re-enabled below when + * nxsem_tickwait_uninterruptible() sleeps. + */ + + priv->intstate = INTSTATE_WAITING; + do + { + /* Wait until either the transfer is complete or the timeout expires */ + +#ifdef CONFIG_STM32_I2C_DYNTIMEO + ret = nxsem_tickwait_uninterruptible(&priv->sem_isr, + stm32_i2c_toticks(priv->msgc, priv->msgv)); +#else + ret = nxsem_tickwait_uninterruptible(&priv->sem_isr, + CONFIG_STM32_I2CTIMEOTICKS); +#endif + if (ret < 0) + { + /* Break out of the loop on irrecoverable errors. This would + * include timeouts and mystery errors reported by + * nxsem_tickwait_uninterruptible. + */ + + break; + } + } + + /* Loop until the interrupt level transfer is complete. */ + + while (priv->intstate != INTSTATE_DONE); + + /* Set the interrupt state back to IDLE */ + + priv->intstate = INTSTATE_IDLE; + + /* Disable I2C interrupts */ + + regval = stm32_i2c_getreg(priv, STM32_I2C_CR2_OFFSET); + regval &= ~I2C_CR2_ALLINTS; + stm32_i2c_putreg(priv, STM32_I2C_CR2_OFFSET, regval); + + leave_critical_section(flags); + return ret; +} +#else +static inline int stm32_i2c_sem_waitdone(struct stm32_i2c_priv_s *priv) +{ + clock_t timeout; + clock_t start; + clock_t elapsed; + int ret; + + /* Get the timeout value */ + +#ifdef CONFIG_STM32_I2C_DYNTIMEO + timeout = stm32_i2c_toticks(priv->msgc, priv->msgv); +#else + timeout = CONFIG_STM32_I2CTIMEOTICKS; +#endif + + /* Signal the interrupt handler that we are waiting. NOTE: Interrupts + * are currently disabled but will be temporarily re-enabled below when + * nxsem_tickwait_uninterruptible() sleeps. + */ + + priv->intstate = INTSTATE_WAITING; + start = clock_systime_ticks(); + + do + { + /* Calculate the elapsed time */ + + elapsed = clock_systime_ticks() - start; + + /* Poll by simply calling the timer interrupt handler until it + * reports that it is done. + */ + + stm32_i2c_isr_process(priv); + } + + /* Loop until the transfer is complete. */ + + while (priv->intstate != INTSTATE_DONE && elapsed < timeout); + + i2cinfo("intstate: %d elapsed: %ld threshold: %ld status: %08" PRIx32 "\n", + priv->intstate, (long)elapsed, (long)timeout, priv->status); + + /* Set the interrupt state back to IDLE */ + + ret = priv->intstate == INTSTATE_DONE ? OK : -ETIMEDOUT; + priv->intstate = INTSTATE_IDLE; + return ret; +} +#endif + +/**************************************************************************** + * Name: stm32_i2c_sem_waitstop + * + * Description: + * Wait for a STOP to complete + * + ****************************************************************************/ + +static inline void stm32_i2c_sem_waitstop(struct stm32_i2c_priv_s *priv) +{ + clock_t start; + clock_t elapsed; + clock_t timeout; + uint32_t cr1; + uint32_t sr1; + + /* Select a timeout */ + +#ifdef CONFIG_STM32_I2C_DYNTIMEO + timeout = USEC2TICK(CONFIG_STM32_I2C_DYNTIMEO_STARTSTOP); +#else + timeout = CONFIG_STM32_I2CTIMEOTICKS; +#endif + + /* Wait as stop might still be in progress; but stop might also + * be set because of a timeout error: "The [STOP] bit is set and + * cleared by software, cleared by hardware when a Stop condition is + * detected, set by hardware when a timeout error is detected." + */ + + start = clock_systime_ticks(); + do + { + /* Calculate the elapsed time */ + + elapsed = clock_systime_ticks() - start; + + /* Check for STOP condition */ + + cr1 = stm32_i2c_getreg(priv, STM32_I2C_CR1_OFFSET); + if ((cr1 & I2C_CR1_STOP) == 0) + { + return; + } + + /* Check for timeout error */ + + sr1 = stm32_i2c_getreg(priv, STM32_I2C_SR1_OFFSET); + if ((sr1 & I2C_SR1_TIMEOUT) != 0) + { + return; + } + } + + /* Loop until the stop is complete or a timeout occurs. */ + + while (elapsed < timeout); + + /* If we get here then a timeout occurred with the STOP condition + * still pending. + */ + + i2cinfo("Timeout with CR1: %04" PRIx32 " SR1: %04" PRIx32 "\n", cr1, sr1); +} + +/**************************************************************************** + * Name: stm32_i2c_trace* + * + * Description: + * I2C trace instrumentation + * + ****************************************************************************/ + +#ifdef CONFIG_I2C_TRACE +static void stm32_i2c_traceclear(struct stm32_i2c_priv_s *priv) +{ + struct stm32_trace_s *trace = &priv->trace[priv->tndx]; + + trace->status = 0; /* I2C 32-bit SR2|SR1 status */ + trace->count = 0; /* Interrupt count when status change */ + trace->event = I2CEVENT_NONE; /* Last event that occurred with this status */ + trace->parm = 0; /* Parameter associated with the event */ + trace->time = 0; /* Time of first status or event */ +} + +static void stm32_i2c_tracereset(struct stm32_i2c_priv_s *priv) +{ + /* Reset the trace info for a new data collection */ + + priv->tndx = 0; + priv->start_time = clock_systime_ticks(); + stm32_i2c_traceclear(priv); +} + +static void stm32_i2c_tracenew(struct stm32_i2c_priv_s *priv, + uint32_t status) +{ + struct stm32_trace_s *trace = &priv->trace[priv->tndx]; + + /* Is the current entry uninitialized? Has the status changed? */ + + if (trace->count == 0 || status != trace->status) + { + /* Yes.. Was it the status changed? */ + + if (trace->count != 0) + { + /* Yes.. bump up the trace index + * (unless we are out of trace entries) + */ + + if (priv->tndx >= (CONFIG_I2C_NTRACE - 1)) + { + i2cerr("ERROR: Trace table overflow\n"); + return; + } + + priv->tndx++; + trace = &priv->trace[priv->tndx]; + } + + /* Initialize the new trace entry */ + + stm32_i2c_traceclear(priv); + trace->status = status; + trace->count = 1; + trace->time = clock_systime_ticks(); + } + else + { + /* Just increment the count of times that we have seen this status */ + + trace->count++; + } +} + +static void stm32_i2c_traceevent(struct stm32_i2c_priv_s *priv, + enum stm32_trace_e event, uint32_t parm) +{ + struct stm32_trace_s *trace; + + if (event != I2CEVENT_NONE) + { + trace = &priv->trace[priv->tndx]; + + /* Initialize the new trace entry */ + + trace->event = event; + trace->parm = parm; + + /* Bump up the trace index (unless we are out of trace entries) */ + + if (priv->tndx >= (CONFIG_I2C_NTRACE - 1)) + { + i2cerr("ERROR: Trace table overflow\n"); + return; + } + + priv->tndx++; + stm32_i2c_traceclear(priv); + } +} + +static void stm32_i2c_tracedump(struct stm32_i2c_priv_s *priv) +{ + struct stm32_trace_s *trace; + int i; + + syslog(LOG_DEBUG, "Elapsed time: %ld\n", + (long)(clock_systime_ticks() - priv->start_time)); + + for (i = 0; i < priv->tndx; i++) + { + trace = &priv->trace[i]; + syslog(LOG_DEBUG, + "%2d. STATUS: %08" PRIx32 " COUNT: %3d EVENT: %s(%2d) PARM:" + " %08" PRIx32 " TIME: %d\n", + i + 1, trace->status, trace->count, g_trace_names[trace->event], + trace->event, trace->parm, trace->time - priv->start_time); + } +} +#endif /* CONFIG_I2C_TRACE */ + +/**************************************************************************** + * Name: stm32_i2c_setclock + * + * Description: + * Set the I2C clock + * + ****************************************************************************/ + +static void stm32_i2c_setclock(struct stm32_i2c_priv_s *priv, + uint32_t frequency) +{ + uint16_t cr1; + uint16_t ccr; + uint16_t trise; + uint16_t freqmhz; + uint16_t speed; + + /* Has the I2C bus frequency changed? */ + + if (frequency != priv->frequency) + { + /* Disable the selected I2C peripheral to configure TRISE */ + + cr1 = stm32_i2c_getreg(priv, STM32_I2C_CR1_OFFSET); + stm32_i2c_putreg(priv, STM32_I2C_CR1_OFFSET, cr1 & ~I2C_CR1_PE); + + /* Update timing and control registers */ + + freqmhz = (uint16_t)(STM32_PCLK1_FREQUENCY / 1000000); + ccr = 0; + + /* Configure speed in standard mode */ + + if (frequency <= 100000) + { + /* Standard mode speed calculation */ + + speed = (uint16_t)(STM32_PCLK1_FREQUENCY / (frequency << 1)); + + /* The CCR fault must be >= 4 */ + + if (speed < 4) + { + /* Set the minimum allowed value */ + + speed = 4; + } + + ccr |= speed; + + /* Set Maximum Rise Time for standard mode */ + + trise = freqmhz + 1; + } + + /* Configure speed in fast mode */ + + else /* (frequency <= 400000) */ + { + /* Fast mode speed calculation with Tlow/Thigh = 16/9 */ + +#ifdef CONFIG_STM32_I2C_DUTY16_9 + speed = (uint16_t)(STM32_PCLK1_FREQUENCY / (frequency * 25)); + + /* Set DUTY and fast speed bits */ + + ccr |= (I2C_CCR_DUTY | I2C_CCR_FS); +#else + /* Fast mode speed calculation with Tlow/Thigh = 2 */ + + speed = (uint16_t)(STM32_PCLK1_FREQUENCY / (frequency * 3)); + + /* Set fast speed bit */ + + ccr |= I2C_CCR_FS; +#endif + + /* Verify that the CCR speed value is nonzero */ + + if (speed < 1) + { + /* Set the minimum allowed value */ + + speed = 1; + } + + ccr |= speed; + + /* Set Maximum Rise Time for fast mode */ + + trise = (uint16_t)(((freqmhz * 300) / 1000) + 1); + } + + /* Write the new values of the CCR and TRISE registers */ + + stm32_i2c_putreg(priv, STM32_I2C_CCR_OFFSET, ccr); + stm32_i2c_putreg(priv, STM32_I2C_TRISE_OFFSET, trise); + + /* Bit 14 of OAR1 must be configured and kept at 1 */ + + stm32_i2c_putreg(priv, STM32_I2C_OAR1_OFFSET, I2C_OAR1_ONE); + + /* Re-enable the peripheral (or not) */ + + stm32_i2c_putreg(priv, STM32_I2C_CR1_OFFSET, cr1); + + /* Save the new I2C frequency */ + + priv->frequency = frequency; + } +} + +/**************************************************************************** + * Name: stm32_i2c_sendstart + * + * Description: + * Send the START conditions/force Master mode + * + ****************************************************************************/ + +static inline void stm32_i2c_sendstart(struct stm32_i2c_priv_s *priv) +{ + /* Disable ACK on receive by default and generate START */ + + stm32_i2c_modifyreg(priv, STM32_I2C_CR1_OFFSET, + I2C_CR1_ACK, I2C_CR1_START); +} + +/**************************************************************************** + * Name: stm32_i2c_clrstart + * + * Description: + * Clear the STOP, START or PEC condition on certain error recovery steps. + * + ****************************************************************************/ + +static inline void stm32_i2c_clrstart(struct stm32_i2c_priv_s *priv) +{ + /* "Note: When the STOP, START or PEC bit is set, the software must + * not perform any write access to I2C_CR1 before this bit is + * cleared by hardware. Otherwise there is a risk of setting a + * second STOP, START or PEC request." + * + * "The [STOP] bit is set and cleared by software, cleared by hardware + * when a Stop condition is detected, set by hardware when a timeout + * error is detected. + * + * "This [START] bit is set and cleared by software and cleared by hardware + * when start is sent or PE=0." The bit must be cleared by software if + * the START is never sent. + * + * "This [PEC] bit is set and cleared by software, and cleared by hardware + * when PEC is transferred or by a START or Stop condition or when PE=0." + */ + + stm32_i2c_modifyreg(priv, STM32_I2C_CR1_OFFSET, + I2C_CR1_START | I2C_CR1_STOP | I2C_CR1_PEC, 0); +} + +/**************************************************************************** + * Name: stm32_i2c_sendstop + * + * Description: + * Send the STOP conditions + * + ****************************************************************************/ + +static inline void stm32_i2c_sendstop(struct stm32_i2c_priv_s *priv) +{ + stm32_i2c_modifyreg(priv, STM32_I2C_CR1_OFFSET, I2C_CR1_ACK, I2C_CR1_STOP); +} + +/**************************************************************************** + * Name: stm32_i2c_getstatus + * + * Description: + * Get 32-bit status (SR1 and SR2 combined) + * + ****************************************************************************/ + +static inline uint32_t stm32_i2c_getstatus(struct stm32_i2c_priv_s *priv) +{ + uint32_t status = stm32_i2c_getreg(priv, STM32_I2C_SR1_OFFSET); + status |= (stm32_i2c_getreg(priv, STM32_I2C_SR2_OFFSET) << 16); + return status; +} + +/**************************************************************************** + * Name: stm32_i2c_disablefsmc + * + * Description: + * FSMC must be disable while accessing I2C1 because it uses a common + * resource (LBAR) + * + * NOTE: + * This is an issue with the STM32F103ZE, but may not be an issue with other + * STM32s. You may need to experiment + * + ****************************************************************************/ + +#ifdef I2C1_FSMC_CONFLICT +static inline +uint32_t stm32_i2c_disablefsmc(struct stm32_i2c_priv_s *priv) +{ + uint32_t ret = 0; + uint32_t regval; + + /* Is this I2C1 */ + +#if defined(CONFIG_STM32_I2C2) || defined(CONFIG_STM32_I2C3) + if (priv->config->base == STM32_I2C1_BASE) +#endif + { + /* Disable FSMC unconditionally */ + + ret = getreg32(STM32_RCC_AHBENR); + regval = ret & ~RCC_AHBENR_FSMCEN; + putreg32(regval, STM32_RCC_AHBENR); + } + + return ret; +} + +/**************************************************************************** + * Name: stm32_i2c_enablefsmc + * + * Description: + * Re-enable the FSMC + * + ****************************************************************************/ + +static inline void stm32_i2c_enablefsmc(uint32_t ahbenr) +{ + uint32_t regval; + + /* Enable AHB clocking to the FSMC only if it was previously enabled. */ + + if ((ahbenr & RCC_AHBENR_FSMCEN) != 0) + { + regval = getreg32(STM32_RCC_AHBENR); + regval |= RCC_AHBENR_FSMCEN; + putreg32(regval, STM32_RCC_AHBENR); + } +} +#else +# define stm32_i2c_disablefsmc(priv) (0) +# define stm32_i2c_enablefsmc(ahbenr) +#endif /* I2C1_FSMC_CONFLICT */ + +/**************************************************************************** + * Name: stm32_i2c_isr_process + * + * Description: + * Common Interrupt Service Routine + * + ****************************************************************************/ + +static int stm32_i2c_isr_process(struct stm32_i2c_priv_s *priv) +{ + uint32_t status = stm32_i2c_getstatus(priv); + + /* Check for new trace setup */ + + stm32_i2c_tracenew(priv, status); + + /* Was start bit sent */ + + if ((status & I2C_SR1_SB) != 0) + { + stm32_i2c_traceevent(priv, I2CEVENT_SENDADDR, priv->msgc); + + /* We check for msgc > 0 here as an unexpected interrupt with + * I2C_SR1_SB set due to noise on the I2C cable can otherwise cause + * msgc to wrap causing memory overwrite + */ + + if (priv->msgc > 0 && priv->msgv != NULL) + { + /* Get run-time data */ + + priv->ptr = priv->msgv->buffer; + priv->dcnt = priv->msgv->length; + priv->flags = priv->msgv->flags; + + /* Send address byte and define addressing mode */ + + stm32_i2c_putreg(priv, STM32_I2C_DR_OFFSET, + (priv->flags & I2C_M_TEN) ? + 0 : ((priv->msgv->addr << 1) | + (priv->flags & I2C_M_READ))); + + /* Set ACK for receive mode */ + + if (priv->dcnt > 1 && (priv->flags & I2C_M_READ) != 0) + { + stm32_i2c_modifyreg(priv, STM32_I2C_CR1_OFFSET, + 0, I2C_CR1_ACK); + } + + /* Increment to next pointer and decrement message count */ + + priv->msgv++; + priv->msgc--; + } + else + { + /* Clear ISR by writing to DR register */ + + stm32_i2c_putreg(priv, STM32_I2C_DR_OFFSET, 0); + } + } + + /* In 10-bit addressing mode, was first byte sent */ + + else if ((status & I2C_SR1_ADD10) != 0) + { + /* TODO: Finish 10-bit mode addressing. + * + * For now just clear ISR by writing to DR register. As we don't do + * 10 bit addressing this must be a spurious ISR + */ + + stm32_i2c_putreg(priv, STM32_I2C_DR_OFFSET, 0); + } + + /* Was address sent, continue with either sending or reading data */ + + else if ((priv->flags & I2C_M_READ) == 0 && + (status & (I2C_SR1_ADDR | I2C_SR1_TXE)) != 0) + { + if (priv->dcnt > 0) + { + /* Send a byte */ + + stm32_i2c_traceevent(priv, I2CEVENT_SENDBYTE, priv->dcnt); + stm32_i2c_putreg(priv, STM32_I2C_DR_OFFSET, *priv->ptr++); + priv->dcnt--; + } + } + + else if ((priv->flags & I2C_M_READ) != 0 && (status & I2C_SR1_ADDR) != 0) + { + /* Enable RxNE and TxE buffers in order to receive one or multiple + * bytes + */ + +#ifndef CONFIG_I2C_POLLED + stm32_i2c_traceevent(priv, I2CEVENT_ITBUFEN, 0); + stm32_i2c_modifyreg(priv, STM32_I2C_CR2_OFFSET, 0, I2C_CR2_ITBUFEN); +#endif + } + + /* More bytes to read */ + + else if ((status & I2C_SR1_RXNE) != 0) + { + /* Read a byte, if dcnt goes < 0, then read dummy bytes to ack ISRs */ + + if (priv->dcnt > 0) + { + stm32_i2c_traceevent(priv, I2CEVENT_RCVBYTE, priv->dcnt); + + /* No interrupts or context switches may occur in the following + * sequence. Otherwise, additional bytes may be sent by the + * device. + */ + +#ifdef CONFIG_I2C_POLLED + irqstate_t flags = enter_critical_section(); +#endif + /* Receive a byte */ + + *priv->ptr++ = stm32_i2c_getreg(priv, STM32_I2C_DR_OFFSET); + + /* Disable acknowledge when last byte is to be received */ + + priv->dcnt--; + if (priv->dcnt == 1) + { + stm32_i2c_modifyreg(priv, STM32_I2C_CR1_OFFSET, + I2C_CR1_ACK, 0); + } + +#ifdef CONFIG_I2C_POLLED + leave_critical_section(flags); +#endif + } + else + { + /* Throw away the unexpected byte */ + + stm32_i2c_getreg(priv, STM32_I2C_DR_OFFSET); + } + } + else if (status & I2C_SR1_TXE) + { + /* This should never happen, but it does happen occasionally with lots + * of noise on the bus. It means the peripheral is expecting more data + * bytes, but we don't have any to give. + */ + + stm32_i2c_putreg(priv, STM32_I2C_DR_OFFSET, 0); + } + else if (status & I2C_SR1_BTF) + { + /* We should have handled all cases where this could happen above, but + * just to ensure it gets ACKed, lets clear it here + */ + + stm32_i2c_getreg(priv, STM32_I2C_DR_OFFSET); + } + else if (status & I2C_SR1_STOPF) + { + /* We should never get this, as we are a master not a slave. Write CR1 + * with its current value to clear the error + */ + + stm32_i2c_modifyreg(priv, STM32_I2C_CR1_OFFSET, 0, 0); + } + + /* Do we have more bytes to send, enable/disable buffer interrupts + * (these ISRs could be replaced by DMAs) + */ + +#ifndef CONFIG_I2C_POLLED + if (priv->dcnt > 0) + { + stm32_i2c_traceevent(priv, I2CEVENT_REITBUFEN, 0); + stm32_i2c_modifyreg(priv, STM32_I2C_CR2_OFFSET, 0, I2C_CR2_ITBUFEN); + } + else if (priv->dcnt == 0) + { + stm32_i2c_traceevent(priv, I2CEVENT_DISITBUFEN, 0); + stm32_i2c_modifyreg(priv, STM32_I2C_CR2_OFFSET, I2C_CR2_ITBUFEN, 0); + } +#endif + + /* Was last byte received or sent? Hmmm... the F2 and F4 seems to differ + * from the F1 in that BTF is not set after data is received (only RXNE). + */ + +#if defined(CONFIG_STM32_HAVE_IP_DMA_V2) || \ + defined(CONFIG_STM32_STM32L15XX) + if (priv->dcnt <= 0 && (status & (I2C_SR1_BTF | I2C_SR1_RXNE)) != 0) +#else + if (priv->dcnt <= 0 && (status & I2C_SR1_BTF) != 0) +#endif + { + stm32_i2c_getreg(priv, STM32_I2C_DR_OFFSET); /* ACK ISR */ + + /* Do we need to terminate or restart after this byte? + * If there are more messages to send, then we may: + * + * - continue with repeated start + * - or just continue sending writeable part + * - or we close down by sending the stop bit + */ + + if (priv->msgc > 0 && priv->msgv != NULL) + { + if (priv->msgv->flags & I2C_M_NOSTART) + { + stm32_i2c_traceevent(priv, I2CEVENT_BTFNOSTART, priv->msgc); + priv->ptr = priv->msgv->buffer; + priv->dcnt = priv->msgv->length; + priv->flags = priv->msgv->flags; + priv->msgv++; + priv->msgc--; + + /* Restart this ISR! */ + +#ifndef CONFIG_I2C_POLLED + stm32_i2c_modifyreg(priv, STM32_I2C_CR2_OFFSET, + 0, I2C_CR2_ITBUFEN); +#endif + } + else + { + stm32_i2c_traceevent(priv, I2CEVENT_BTFRESTART, priv->msgc); + stm32_i2c_sendstart(priv); + } + } + else if (priv->msgv) + { + stm32_i2c_traceevent(priv, I2CEVENT_BTFSTOP, 0); + stm32_i2c_sendstop(priv); + + /* Is there a thread waiting for this event (there should be) */ + +#ifndef CONFIG_I2C_POLLED + if (priv->intstate == INTSTATE_WAITING) + { + /* Yes.. inform the thread that the transfer is complete + * and wake it up. + */ + + nxsem_post(&priv->sem_isr); + priv->intstate = INTSTATE_DONE; + } +#else + priv->intstate = INTSTATE_DONE; +#endif + + /* Mark that we have stopped with this transaction */ + + priv->msgv = NULL; + } + } + + /* Check for errors, in which case, stop the transfer and return + * Note that in master reception mode AF becomes set on last byte + * since ACK is not returned. We should ignore this error. + */ + + if ((status & I2C_SR1_ERRORMASK) != 0) + { + stm32_i2c_traceevent(priv, I2CEVENT_ERROR, 0); + + /* Clear interrupt flags */ + + stm32_i2c_putreg(priv, STM32_I2C_SR1_OFFSET, 0); + + /* Is there a thread waiting for this event (there should be) */ + +#ifndef CONFIG_I2C_POLLED + if (priv->intstate == INTSTATE_WAITING) + { + /* Yes.. inform the thread that the transfer is complete + * and wake it up. + */ + + nxsem_post(&priv->sem_isr); + priv->intstate = INTSTATE_DONE; + } +#else + priv->intstate = INTSTATE_DONE; +#endif + } + + priv->status = status; + return OK; +} + +/**************************************************************************** + * Name: stm32_i2c_isr + * + * Description: + * Common I2C interrupt service routine + * + ****************************************************************************/ + +#ifndef CONFIG_I2C_POLLED +static int stm32_i2c_isr(int irq, void *context, void *arg) +{ + struct stm32_i2c_priv_s *priv = (struct stm32_i2c_priv_s *)arg; + + DEBUGASSERT(priv != NULL); + return stm32_i2c_isr_process(priv); +} +#endif + +/**************************************************************************** + * Name: stm32_i2c_init + * + * Description: + * Setup the I2C hardware, ready for operation with defaults + * + ****************************************************************************/ + +static int stm32_i2c_init(struct stm32_i2c_priv_s *priv) +{ + /* Power-up and configure GPIOs */ + + /* Enable power and reset the peripheral */ + + modifyreg32(STM32_RCC_APB1ENR, 0, priv->config->clk_bit); + modifyreg32(STM32_RCC_APB1RSTR, 0, priv->config->reset_bit); + modifyreg32(STM32_RCC_APB1RSTR, priv->config->reset_bit, 0); + + /* Configure pins */ + + if (stm32_configgpio(priv->config->scl_pin) < 0) + { + return ERROR; + } + + if (stm32_configgpio(priv->config->sda_pin) < 0) + { + stm32_unconfiggpio(priv->config->scl_pin); + return ERROR; + } + + /* Attach ISRs */ + +#ifndef CONFIG_I2C_POLLED + irq_attach(priv->config->ev_irq, stm32_i2c_isr, priv); + irq_attach(priv->config->er_irq, stm32_i2c_isr, priv); + up_enable_irq(priv->config->ev_irq); + up_enable_irq(priv->config->er_irq); +#endif + + /* Set peripheral frequency, where it must be at least 2 MHz for 100 kHz + * or 4 MHz for 400 kHz. This also disables all I2C interrupts. + */ + + stm32_i2c_putreg(priv, STM32_I2C_CR2_OFFSET, + (STM32_PCLK1_FREQUENCY / 1000000)); + + /* Force a frequency update */ + + priv->frequency = 0; + + stm32_i2c_setclock(priv, 100000); + + /* Enable I2C */ + + stm32_i2c_putreg(priv, STM32_I2C_CR1_OFFSET, I2C_CR1_PE); + return OK; +} + +/**************************************************************************** + * Name: stm32_i2c_deinit + * + * Description: + * Shutdown the I2C hardware + * + ****************************************************************************/ + +static int stm32_i2c_deinit(struct stm32_i2c_priv_s *priv) +{ + /* Disable I2C */ + + stm32_i2c_putreg(priv, STM32_I2C_CR1_OFFSET, 0); + + /* Unconfigure GPIO pins */ + + stm32_unconfiggpio(priv->config->scl_pin); + stm32_unconfiggpio(priv->config->sda_pin); + + /* Disable and detach interrupts */ + +#ifndef CONFIG_I2C_POLLED + up_disable_irq(priv->config->ev_irq); + up_disable_irq(priv->config->er_irq); + irq_detach(priv->config->ev_irq); + irq_detach(priv->config->er_irq); +#endif + + /* Disable clocking */ + + modifyreg32(STM32_RCC_APB1ENR, priv->config->clk_bit, 0); + return OK; +} + +/**************************************************************************** + * Device Driver Operations + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_i2c_transfer + * + * Description: + * Generic I2C transfer function + * + ****************************************************************************/ + +static int stm32_i2c_transfer(struct i2c_master_s *dev, + struct i2c_msg_s *msgs, int count) +{ + struct stm32_i2c_priv_s *priv = (struct stm32_i2c_priv_s *)dev; + uint32_t status = 0; +#ifdef I2C1_FSMC_CONFLICT + uint32_t ahbenr; +#endif + int ret; + + DEBUGASSERT(count > 0); + + /* Ensure that address or flags don't change meanwhile */ + + ret = nxmutex_lock(&priv->lock); + if (ret < 0) + { + return ret; + } + +#ifdef I2C1_FSMC_CONFLICT + /* Disable FSMC that shares a pin with I2C1 (LBAR) */ + + ahbenr = stm32_i2c_disablefsmc(priv); + +#else + /* Wait for any STOP in progress. NOTE: If we have to disable the FSMC + * then we cannot do this at the top of the loop, unfortunately. The STOP + * will not complete normally if the FSMC is enabled. + */ + + stm32_i2c_sem_waitstop(priv); +#endif + + /* Clear any pending error interrupts */ + + stm32_i2c_putreg(priv, STM32_I2C_SR1_OFFSET, 0); + + /* "Note: When the STOP, START or PEC bit is set, the software must + * not perform any write access to I2C_CR1 before this bit is + * cleared by hardware. Otherwise there is a risk of setting a + * second STOP, START or PEC request." However, if the bits are + * not cleared by hardware, then we will have to do that from hardware. + */ + + stm32_i2c_clrstart(priv); + + /* Old transfers are done */ + + /* Reset ptr and dcnt to ensure an unexpected data interrupt doesn't + * overwrite stale data. + */ + + priv->dcnt = 0; + priv->ptr = NULL; + + priv->msgv = msgs; + priv->msgc = count; + + /* Reset I2C trace logic */ + + stm32_i2c_tracereset(priv); + + /* Set I2C clock frequency (on change it toggles I2C_CR1_PE !) + * REVISIT: Note that the frequency is set only on the first message. + * This could be extended to support different transfer frequencies for + * each message segment. + */ + + stm32_i2c_setclock(priv, msgs->frequency); + + /* Trigger start condition, then the process moves into the ISR. I2C + * interrupts will be enabled within stm32_i2c_waitdone(). + */ + + priv->status = 0; + stm32_i2c_sendstart(priv); + + /* Wait for an ISR, if there was a timeout, fetch latest status to get + * the BUSY flag. + */ + + if (stm32_i2c_sem_waitdone(priv) < 0) + { + status = stm32_i2c_getstatus(priv); + ret = -ETIMEDOUT; + + i2cerr("ERROR: Timed out: CR1: 0x%04x status: 0x%08" PRIx32 "\n", + stm32_i2c_getreg(priv, STM32_I2C_CR1_OFFSET), status); + + /* "Note: When the STOP, START or PEC bit is set, the software must + * not perform any write access to I2C_CR1 before this bit is + * cleared by hardware. Otherwise there is a risk of setting a + * second STOP, START or PEC request." + */ + + stm32_i2c_clrstart(priv); + + /* Clear busy flag in case of timeout */ + + status = priv->status & 0xffff; + } + else + { + /* clear SR2 (BUSY flag) as we've done successfully */ + + status = priv->status & 0xffff; + } + + /* Check for error status conditions */ + + if ((status & I2C_SR1_ERRORMASK) != 0) + { + /* I2C_SR1_ERRORMASK is the 'OR' of the following individual bits: */ + + if (status & I2C_SR1_BERR) + { + /* Bus Error */ + + ret = -EIO; + } + else if (status & I2C_SR1_ARLO) + { + /* Arbitration Lost (master mode) */ + + ret = -EAGAIN; + } + else if (status & I2C_SR1_AF) + { + /* Acknowledge Failure */ + + ret = -ENXIO; + } + else if (status & I2C_SR1_OVR) + { + /* Overrun/Underrun */ + + ret = -EIO; + } + else if (status & I2C_SR1_PECERR) + { + /* PEC Error in reception */ + + ret = -EPROTO; + } + else if (status & I2C_SR1_TIMEOUT) + { + /* Timeout or Tlow Error */ + + ret = -ETIME; + } + + /* This is not an error and should never happen since SMBus is not + * enabled + */ + + else /* if (status & I2C_SR1_SMBALERT) */ + { + /* SMBus alert is an optional signal with an interrupt line for + * devices that want to trade their ability to master for a pin. + */ + + ret = -EINTR; + } + } + + /* This is not an error, but should not happen. The BUSY signal can hang, + * however, if there are unhealthy devices on the bus that need to be + * reset. + * NOTE: We will only see this busy indication if stm32_i2c_sem_waitdone() + * fails above; Otherwise it is cleared. + */ + + else if ((status & (I2C_SR2_BUSY << 16)) != 0) + { + /* I2C Bus is for some reason busy */ + + ret = -EBUSY; + } + + /* Dump the trace result */ + + stm32_i2c_tracedump(priv); + +#ifdef I2C1_FSMC_CONFLICT + /* Wait for any STOP in progress. NOTE: If we have to disable the FSMC + * then we cannot do this at the top of the loop, unfortunately. The STOP + * will not complete normally if the FSMC is enabled. + */ + + stm32_i2c_sem_waitstop(priv); + + /* Re-enable the FSMC */ + + stm32_i2c_enablefsmc(ahbenr); +#endif + + /* Ensure that any ISR happening after we finish can't overwrite any user + * data + */ + + priv->dcnt = 0; + priv->ptr = NULL; + + nxmutex_unlock(&priv->lock); + return ret; +} + +/**************************************************************************** + * Name: stm32_i2c_reset + * + * Description: + * Perform an I2C bus reset in an attempt to break loose stuck I2C devices. + * + * Input Parameters: + * dev - Device-specific state data + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +#ifdef CONFIG_I2C_RESET +static int stm32_i2c_reset(struct i2c_master_s *dev) +{ + struct stm32_i2c_priv_s *priv = (struct stm32_i2c_priv_s *)dev; + unsigned int clock_count; + unsigned int stretch_count; + uint32_t scl_gpio; + uint32_t sda_gpio; + uint32_t frequency; + int ret; + + DEBUGASSERT(dev); + + /* Our caller must own a ref */ + + DEBUGASSERT(priv->refs > 0); + + /* Lock out other clients */ + + ret = nxmutex_lock(&priv->lock); + if (ret < 0) + { + return ret; + } + + ret = -EIO; + + /* Save the current frequency */ + + frequency = priv->frequency; + + /* De-init the port */ + + stm32_i2c_deinit(priv); + + /* Use GPIO configuration to un-wedge the bus */ + + scl_gpio = MKI2C_OUTPUT(priv->config->scl_pin); + sda_gpio = MKI2C_OUTPUT(priv->config->sda_pin); + + stm32_configgpio(scl_gpio); + stm32_configgpio(sda_gpio); + + /* Let SDA go high */ + + stm32_gpiowrite(sda_gpio, 1); + + /* Clock the bus until any slaves currently driving it let it go. */ + + clock_count = 0; + while (!stm32_gpioread(sda_gpio)) + { + /* Give up if we have tried too hard */ + + if (clock_count++ > 10) + { + goto out; + } + + /* Sniff to make sure that clock stretching has finished. + * + * If the bus never relaxes, the reset has failed. + */ + + stretch_count = 0; + while (!stm32_gpioread(scl_gpio)) + { + /* Give up if we have tried too hard */ + + if (stretch_count++ > 10) + { + goto out; + } + + up_udelay(10); + } + + /* Drive SCL low */ + + stm32_gpiowrite(scl_gpio, 0); + up_udelay(10); + + /* Drive SCL high again */ + + stm32_gpiowrite(scl_gpio, 1); + up_udelay(10); + } + + /* Generate a start followed by a stop to reset slave + * state machines. + */ + + stm32_gpiowrite(sda_gpio, 0); + up_udelay(10); + stm32_gpiowrite(scl_gpio, 0); + up_udelay(10); + stm32_gpiowrite(scl_gpio, 1); + up_udelay(10); + stm32_gpiowrite(sda_gpio, 1); + up_udelay(10); + + /* Revert the GPIO configuration. */ + + stm32_unconfiggpio(sda_gpio); + stm32_unconfiggpio(scl_gpio); + + /* Re-init the port */ + + stm32_i2c_init(priv); + + /* Restore the frequency */ + + stm32_i2c_setclock(priv, frequency); + ret = OK; + +out: + + /* Release the port for reuse by other clients */ + + nxmutex_unlock(&priv->lock); + return ret; +} +#endif /* CONFIG_I2C_RESET */ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_i2cbus_initialize + * + * Description: + * Initialize one I2C bus + * + ****************************************************************************/ + +struct i2c_master_s *stm32_i2cbus_initialize(int port) +{ + struct stm32_i2c_priv_s *priv = NULL; + + /* Get I2C private structure */ + + switch (port) + { +#ifdef CONFIG_STM32_I2C1 + case 1: + priv = (struct stm32_i2c_priv_s *)&stm32_i2c1_priv; + break; +#endif +#ifdef CONFIG_STM32_I2C2 + case 2: + priv = (struct stm32_i2c_priv_s *)&stm32_i2c2_priv; + break; +#endif +#ifdef CONFIG_STM32_I2C3 + case 3: + priv = (struct stm32_i2c_priv_s *)&stm32_i2c3_priv; + break; +#endif + default: + return NULL; + } + + /* Initialize private data for the first time, increment reference count, + * power-up hardware and configure GPIOs. + */ + + nxmutex_lock(&priv->lock); + if (priv->refs++ == 0) + { + stm32_i2c_init(priv); + } + + nxmutex_unlock(&priv->lock); + return (struct i2c_master_s *)priv; +} + +/**************************************************************************** + * Name: stm32_i2cbus_uninitialize + * + * Description: + * Uninitialize an I2C bus + * + ****************************************************************************/ + +int stm32_i2cbus_uninitialize(struct i2c_master_s *dev) +{ + struct stm32_i2c_priv_s *priv = (struct stm32_i2c_priv_s *)dev; + + DEBUGASSERT(dev); + + /* Decrement reference count and check for underflow */ + + if (priv->refs == 0) + { + return ERROR; + } + + nxmutex_lock(&priv->lock); + if (--priv->refs) + { + nxmutex_unlock(&priv->lock); + return OK; + } + + /* Disable power and other HW resource (GPIO's) */ + + stm32_i2c_deinit(priv); + nxmutex_unlock(&priv->lock); + + return OK; +} + +#endif /* CONFIG_STM32_HAVE_IP_I2C_M3M4_V1 */ +#endif /* CONFIG_STM32_I2C1 || CONFIG_STM32_I2C2 || CONFIG_STM32_I2C3 */ diff --git a/arch/arm/src/common/stm32/stm32_i2c_m3m4_v1_alt.c b/arch/arm/src/common/stm32/stm32_i2c_m3m4_v1_alt.c new file mode 100644 index 0000000000000..3f4055fd0bf7f --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_i2c_m3m4_v1_alt.c @@ -0,0 +1,2452 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_i2c_m3m4_v1_alt.c + * + * SPDX-License-Identifier: BSD-3-Clause + * SPDX-FileCopyrightText: 2016-2017 Gregory Nutt. All rights reserved. + * SPDX-FileCopyrightText: 2014 Patrizio Simona. All rights reserved. + * SPDX-FileCopyrightText: 2011-2014 Gregory Nutt. All rights reserved. + * SPDX-FileCopyrightText: 2011 Uros Platise. All rights reserved. + * SPDX-FileContributor: Uros Platise + * SPDX-FileContributor: Gregory Nutt + * SPDX-FileContributor: Patrizio Simona + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/* Supports: + * - Master operation, 100 kHz (standard) and 400 kHz (full speed) + * - Multiple instances (shared bus) + * - Interrupt based operation + * + * Structure naming: + * - Device: structure as defined by the nuttx/i2c/i2c.h + * - Instance: represents each individual access to the I2C driver, obtained + * by the i2c_init(); it extends the Device structure from the + * nuttx/i2c/i2c.h; + * Instance points to OPS, to common I2C Hardware private data and + * contains its own private data, as frequency, address, mode of + * operation (in the future) + * - Private: Private data of an I2C Hardware + * + * TODO + * - Trace events in polled operation fill trace table very quickly. Events + * 1111 and 1004 get traced in an alternate fashion during polling causing + * multiple entries. + * - Check for all possible deadlocks (as BUSY='1' I2C needs to be reset in + * HW using the I2C_CR1_SWRST) + * - SMBus support (hardware layer timings are already supported) and add + * SMBA gpio pin + * - Slave support with multiple addresses (on multiple instances): + * - 2 x 7-bit address or + * - 1 x 10 bit addresses + 1 x 7 bit address (?) + * - plus the broadcast address (general call) + * - Multi-master support + * - DMA (to get rid of too many CPU wake-ups and interventions) + * - Be ready for IPMI + * - Write trace events to keep track of ISR flow + */ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#include + +#include "arm_internal.h" +#include "stm32_rcc.h" +#include "stm32_i2c.h" +#include "stm32_waste.h" + +/* At least one I2C peripheral must be enabled */ + +#if defined(CONFIG_STM32_I2C1) || defined(CONFIG_STM32_I2C2) || \ + defined(CONFIG_STM32_I2C3) + +/* This implementation is for the STM32 F1, F2, and F4 only. + * Experimentally enabled for STM32L15XX. + */ + +#if defined(CONFIG_STM32_STM32L15XX) || defined(CONFIG_STM32_STM32F10XX) || \ + defined(CONFIG_STM32_HAVE_IP_DMA_V2) + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#if STM32_PCLK1_FREQUENCY < 4000000 +# warning STM32_I2C: Peripheral clock must be at least 4 MHz to support 400 kHz operation. +#endif + +#if STM32_PCLK1_FREQUENCY < 2000000 +# error STM32_I2C: Peripheral clock must be at least 2 MHz to support 100 kHz operation. +#endif + +/* Configuration ************************************************************/ + +/* CONFIG_I2C_POLLED may be set so that I2C interrupts will not be used. + * Instead, CPU-intensive polling will be used. + */ + +/* Interrupt wait timeout in seconds and milliseconds */ + +#if !defined(CONFIG_STM32_I2CTIMEOSEC) && !defined(CONFIG_STM32_I2CTIMEOMS) +# define CONFIG_STM32_I2CTIMEOSEC 0 +# define CONFIG_STM32_I2CTIMEOMS 500 /* Default is 500 milliseconds */ +#elif !defined(CONFIG_STM32_I2CTIMEOSEC) +# define CONFIG_STM32_I2CTIMEOSEC 0 /* User provided milliseconds */ +#elif !defined(CONFIG_STM32_I2CTIMEOMS) +# define CONFIG_STM32_I2CTIMEOMS 0 /* User provided seconds */ +#endif + +/* Interrupt wait time timeout in system timer ticks */ + +#ifndef CONFIG_STM32_I2CTIMEOTICKS +# define CONFIG_STM32_I2CTIMEOTICKS \ + (SEC2TICK(CONFIG_STM32_I2CTIMEOSEC) + MSEC2TICK(CONFIG_STM32_I2CTIMEOMS)) +#endif + +#ifndef CONFIG_STM32_I2C_DYNTIMEO_STARTSTOP +# define CONFIG_STM32_I2C_DYNTIMEO_STARTSTOP TICK2USEC(CONFIG_STM32_I2CTIMEOTICKS) +#endif + +/* On the STM32F103ZE, there is an internal conflict between I2C1 and FSMC. + * In that case, it is necessary to disable FSMC before each I2C1 access and + * re-enable FSMC when the I2C access completes. + */ + +#undef I2C1_FSMC_CONFLICT +#if defined(CONFIG_STM32_STM32F10XX) && defined(CONFIG_STM32_FSMC) && defined(CONFIG_STM32_I2C1) +# define I2C1_FSMC_CONFLICT +#endif + +/* Macros to convert a I2C pin to a GPIO output */ + +#if defined(CONFIG_STM32_STM32L15XX) +# define I2C_OUTPUT (GPIO_OUTPUT | GPIO_OUTPUT_SET | GPIO_OPENDRAIN | \ + GPIO_SPEED_40MHz) +#elif defined(CONFIG_STM32_STM32F10XX) +# define I2C_OUTPUT (GPIO_OUTPUT | GPIO_OUTPUT_SET | GPIO_CNF_OUTOD | \ + GPIO_MODE_50MHz) +#elif defined(CONFIG_STM32_HAVE_IP_DMA_V2) +# define I2C_OUTPUT (GPIO_OUTPUT | GPIO_FLOAT | GPIO_OPENDRAIN |\ + GPIO_SPEED_50MHz | GPIO_OUTPUT_SET) +#endif + +#define MKI2C_OUTPUT(p) (((p) & (GPIO_PORT_MASK | GPIO_PIN_MASK)) | I2C_OUTPUT) + +/* Debug ********************************************************************/ + +/* I2C event trace logic. NOTE: trace uses the internal, non-standard, + * low-level debug interface syslog() but does not require that any other + * debug is enabled. + */ + +#ifndef CONFIG_I2C_TRACE +# define stm32_i2c_tracereset(p) +# define stm32_i2c_tracenew(p,s) +# define stm32_i2c_traceevent(p,e,a) +# define stm32_i2c_tracedump(p) +#endif + +#ifndef CONFIG_I2C_NTRACE +# define CONFIG_I2C_NTRACE 32 +#endif + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/* Interrupt state */ + +enum stm32_intstate_e +{ + INTSTATE_IDLE = 0, /* No I2C activity */ + INTSTATE_WAITING, /* Waiting for completion of interrupt activity */ + INTSTATE_DONE, /* Interrupt activity complete */ +}; + +/* Trace events */ + +#ifdef CONFIG_I2C_TRACE +static const uint16_t I2CEVENT_NONE = 0; /* No events have occurred with this status */ +static const uint16_t I2CEVENT_STATE_ERROR = 1000; /* No correct state detected, diver cannot handle state */ +static const uint16_t I2CEVENT_ISR_SHUTDOWN = 1001; /* ISR gets shutdown */ +static const uint16_t I2CEVENT_ISR_EMPTY_CALL = 1002; /* ISR gets called but no I2C logic comes into play */ +static const uint16_t I2CEVENT_MSG_HANDLING = 1003; /* Message Handling 1/1: advances the msg processing param = msgc */ +static const uint16_t I2CEVENT_POLL_DEV_NOT_RDY = 1004; /* During polled operation if device is not ready yet */ +static const uint16_t I2CEVENT_ISR_SR1ERROR = 1005; /* ERROR set in SR1 at end of transfer */ +static const uint16_t I2CEVENT_ISR_CALL = 1111; /* ISR called */ + +static const uint16_t I2CEVENT_SENDADDR = 5; /* Start/Master bit set and address sent, param = priv->msgv->addr(EV5 in reference manual) */ +static const uint16_t I2CEVENT_ADDR_HDL_READ_1 = 51; /* Read of length 1 address handling, param = 0 */ +static const uint16_t I2CEVENT_ADDR_HDL_READ_2 = 52; /* Read of length 2 address handling, param = 0 */ +static const uint16_t I2CEVENT_EMPTY_MSG = 5000; /* Empty message detected, param=0 */ + +static const uint16_t I2CEVENT_ADDRESS_ACKED = 6; /* Address has been ACKed(i.e. it's a valid address) param = address */ +static const uint16_t I2CEVENT_ADDRESS_ACKED_READ_1 = 63; /* Event when reading single byte just after address is being ACKed, param = 0 */ +static const uint16_t I2CEVENT_ADDRESS_ACKED_READ_2 = 61; /* Event when reading two bytes just after address is being ACKed, param = 0 */ +static const uint16_t I2CEVENT_ADDRESS_ACKED_WRITE = 681; /* Address has been ACKed(i.e. it's a valid address) in write mode and byte has been written */ +static const uint16_t I2CEVENT_ADDRESS_NACKED = 6000; /* Address has been NACKed(i.e. it's an invalid address) param = address */ + +static const uint16_t I2CEVENT_READ = 7; /* RxNE = 1 therefore can be read, param = dcnt */ +static const uint16_t I2CEVENT_READ_3 = 72; /* EV7_2 reference manual, reading byte N-2 and N-1 when N >=3 */ +static const uint16_t I2CEVENT_READ_2 = 73; /* EV7_3 reference manual, reading byte 1 and 2 when N == 2 */ +static const uint16_t I2CEVENT_READ_SR_EMPTY = 79; /* DR is full but SR is empty, does not read DR and waits for SR to fill in next ISR */ +static const uint16_t I2CEVENT_READ_LAST_BYTE = 72; /* EV7_2 reference manual last two bytes are in SR and DR */ +static const uint16_t I2CEVENT_READ_ERROR = 7000; /* read mode error */ + +static const uint16_t I2CEVENT_WRITE_TO_DR = 8; /* EV8 reference manual, writing into the data register param = byte to send */ +static const uint16_t I2CEVENT_WRITE_STOP = 82; /* EV8_2 reference manual, set stop bit after write is finished */ +static const uint16_t I2CEVENT_WRITE_RESTART = 83; /* Re-send start bit as next packet is a read */ +static const uint16_t I2CEVENT_WRITE_NO_RESTART = 84; /* don't restart as packet flag says so */ +static const uint16_t I2CEVENT_WRITE_ERROR = 8000; /* Error in write mode, param = 0 */ +static const uint16_t I2CEVENT_WRITE_FLAG_ERROR = 8001; /* Next message has unrecognized flag, param = priv->msgv->flags */ +#endif /* CONFIG_I2C_TRACE */ + +/* Trace data */ + +struct stm32_trace_s +{ + uint32_t status; /* I2C 32-bit SR2|SR1 status */ + uint32_t count; /* Interrupt count when status change */ + uint32_t event; /* Last event that occurred with this status */ + uint32_t parm; /* Parameter associated with the event */ + clock_t time; /* First of event or first status */ +}; + +/* I2C Device hardware configuration */ + +struct stm32_i2c_config_s +{ + uint32_t base; /* I2C base address */ + uint32_t clk_bit; /* Clock enable bit */ + uint32_t reset_bit; /* Reset bit */ + uint32_t scl_pin; /* GPIO configuration for SCL as SCL */ + uint32_t sda_pin; /* GPIO configuration for SDA as SDA */ +#ifndef CONFIG_I2C_POLLED + uint32_t ev_irq; /* Event IRQ */ + uint32_t er_irq; /* Error IRQ */ +#endif +}; + +/* I2C Device Private Data */ + +struct stm32_i2c_priv_s +{ + /* Standard I2C operations */ + + const struct i2c_ops_s *ops; + + /* Port configuration */ + + const struct stm32_i2c_config_s *config; + + int refs; /* Reference count */ + mutex_t lock; /* Mutual exclusion mutex */ +#ifndef CONFIG_I2C_POLLED + sem_t sem_isr; /* Interrupt wait semaphore */ +#endif + volatile uint8_t intstate; /* Interrupt handshake (see enum stm32_intstate_e) */ + + uint8_t msgc; /* Message count */ + struct i2c_msg_s *msgv; /* Message list */ + uint8_t *ptr; /* Current message buffer */ + uint32_t frequency; /* Current I2C frequency */ + int dcnt; /* Current message length */ + uint16_t flags; /* Current message flags */ + bool check_addr_ack; /* Flag to signal if on next interrupt address has ACKed */ + uint8_t total_msg_len; /* Flag to signal a short read sequence */ + + /* I2C trace support */ + +#ifdef CONFIG_I2C_TRACE + int tndx; /* Trace array index */ + clock_t start_time; /* Time when the trace was started */ + + /* The actual trace data */ + + struct stm32_trace_s trace[CONFIG_I2C_NTRACE]; +#endif + + uint32_t status; /* End of transfer SR2|SR1 status */ +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +static inline uint16_t stm32_i2c_getreg(struct stm32_i2c_priv_s *priv, + uint8_t offset); +static inline void stm32_i2c_putreg(struct stm32_i2c_priv_s *priv, + uint8_t offset, uint16_t value); +static inline void stm32_i2c_modifyreg(struct stm32_i2c_priv_s *priv, + uint8_t offset, uint16_t clearbits, + uint16_t setbits); + +#ifdef CONFIG_STM32_I2C_DYNTIMEO +static uint32_t stm32_i2c_toticks(int msgc, struct i2c_msg_s *msgs); +#endif /* CONFIG_STM32_I2C_DYNTIMEO */ + +static inline int stm32_i2c_sem_waitdone(struct stm32_i2c_priv_s *priv); +static inline void stm32_i2c_sem_waitstop(struct stm32_i2c_priv_s *priv); + +#ifdef CONFIG_I2C_TRACE +static void stm32_i2c_tracereset(struct stm32_i2c_priv_s *priv); +static void stm32_i2c_tracenew(struct stm32_i2c_priv_s *priv, + uint16_t status); +static void stm32_i2c_traceevent(struct stm32_i2c_priv_s *priv, + uint16_t event, uint32_t parm); +static void stm32_i2c_tracedump(struct stm32_i2c_priv_s *priv); +#endif /* CONFIG_I2C_TRACE */ + +static void stm32_i2c_setclock(struct stm32_i2c_priv_s *priv, + uint32_t frequency); +static inline void stm32_i2c_sendstart(struct stm32_i2c_priv_s *priv); +static inline void stm32_i2c_clrstart(struct stm32_i2c_priv_s *priv); +static inline void stm32_i2c_sendstop(struct stm32_i2c_priv_s *priv); +static inline +uint32_t stm32_i2c_getstatus(struct stm32_i2c_priv_s *priv); + +#ifdef I2C1_FSMC_CONFLICT +static inline +uint32_t stm32_i2c_disablefsmc(struct stm32_i2c_priv_s *priv); +static inline void stm32_i2c_enablefsmc(uint32_t ahbenr); +#endif /* I2C1_FSMC_CONFLICT */ + +static int stm32_i2c_isr_process(struct stm32_i2c_priv_s *priv); + +#ifndef CONFIG_I2C_POLLED +static int stm32_i2c_isr(int irq, void *context, void *arg); +#endif /* !CONFIG_I2C_POLLED */ + +static int stm32_i2c_init(struct stm32_i2c_priv_s *priv); +static int stm32_i2c_deinit(struct stm32_i2c_priv_s *priv); +static int stm32_i2c_transfer(struct i2c_master_s *dev, + struct i2c_msg_s *msgs, int count); +#ifdef CONFIG_I2C_RESET +static int stm32_i2c_reset(struct i2c_master_s *dev); +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* I2C interface */ + +static const struct i2c_ops_s stm32_i2c_ops = +{ + .transfer = stm32_i2c_transfer +#ifdef CONFIG_I2C_RESET + , .reset = stm32_i2c_reset +#endif +}; + +#ifdef CONFIG_STM32_I2C1 +static const struct stm32_i2c_config_s stm32_i2c1_config = +{ + .base = STM32_I2C1_BASE, + .clk_bit = RCC_APB1ENR_I2C1EN, + .reset_bit = RCC_APB1RSTR_I2C1RST, + .scl_pin = GPIO_I2C1_SCL, + .sda_pin = GPIO_I2C1_SDA, +#ifndef CONFIG_I2C_POLLED + .ev_irq = STM32_IRQ_I2C1EV, + .er_irq = STM32_IRQ_I2C1ER +#endif +}; + +static struct stm32_i2c_priv_s stm32_i2c1_priv = +{ + .ops = &stm32_i2c_ops, + .config = &stm32_i2c1_config, + .refs = 0, + .lock = NXMUTEX_INITIALIZER, +#ifndef CONFIG_I2C_POLLED + .sem_isr = SEM_INITIALIZER(0), +#endif + .intstate = INTSTATE_IDLE, + .msgc = 0, + .msgv = NULL, + .ptr = NULL, + .dcnt = 0, + .flags = 0, + .status = 0 +}; +#endif + +#ifdef CONFIG_STM32_I2C2 +static const struct stm32_i2c_config_s stm32_i2c2_config = +{ + .base = STM32_I2C2_BASE, + .clk_bit = RCC_APB1ENR_I2C2EN, + .reset_bit = RCC_APB1RSTR_I2C2RST, + .scl_pin = GPIO_I2C2_SCL, + .sda_pin = GPIO_I2C2_SDA, +#ifndef CONFIG_I2C_POLLED + .ev_irq = STM32_IRQ_I2C2EV, + .er_irq = STM32_IRQ_I2C2ER +#endif +}; + +static struct stm32_i2c_priv_s stm32_i2c2_priv = +{ + .ops = &stm32_i2c_ops, + .config = &stm32_i2c2_config, + .refs = 0, + .lock = NXMUTEX_INITIALIZER, +#ifndef CONFIG_I2C_POLLED + .sem_isr = SEM_INITIALIZER(0), +#endif + .intstate = INTSTATE_IDLE, + .msgc = 0, + .msgv = NULL, + .ptr = NULL, + .dcnt = 0, + .flags = 0, + .status = 0 +}; +#endif + +#ifdef CONFIG_STM32_I2C3 +static const struct stm32_i2c_config_s stm32_i2c3_config = +{ + .base = STM32_I2C3_BASE, + .clk_bit = RCC_APB1ENR_I2C3EN, + .reset_bit = RCC_APB1RSTR_I2C3RST, + .scl_pin = GPIO_I2C3_SCL, + .sda_pin = GPIO_I2C3_SDA, +#ifndef CONFIG_I2C_POLLED + .ev_irq = STM32_IRQ_I2C3EV, + .er_irq = STM32_IRQ_I2C3ER +#endif +}; + +static struct stm32_i2c_priv_s stm32_i2c3_priv = +{ + .ops = &stm32_i2c_ops, + .config = &stm32_i2c3_config, + .refs = 0, + .lock = NXMUTEX_INITIALIZER, +#ifndef CONFIG_I2C_POLLED + .sem_isr = SEM_INITIALIZER(0), +#endif + .intstate = INTSTATE_IDLE, + .msgc = 0, + .msgv = NULL, + .ptr = NULL, + .dcnt = 0, + .flags = 0, + .status = 0 +}; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_i2c_getreg + * + * Description: + * Get a 16-bit register value by offset + * + ****************************************************************************/ + +static inline uint16_t stm32_i2c_getreg(struct stm32_i2c_priv_s *priv, + uint8_t offset) +{ + return getreg16(priv->config->base + offset); +} + +/**************************************************************************** + * Name: stm32_i2c_putreg + * + * Description: + * Put a 16-bit register value by offset + * + ****************************************************************************/ + +static inline void stm32_i2c_putreg(struct stm32_i2c_priv_s *priv, + uint8_t offset, uint16_t value) +{ + putreg16(value, priv->config->base + offset); +} + +/**************************************************************************** + * Name: stm32_i2c_modifyreg + * + * Description: + * Modify a 16-bit register value by offset + * + ****************************************************************************/ + +static inline void stm32_i2c_modifyreg(struct stm32_i2c_priv_s *priv, + uint8_t offset, uint16_t clearbits, + uint16_t setbits) +{ + modifyreg16(priv->config->base + offset, clearbits, setbits); +} + +/**************************************************************************** + * Name: stm32_i2c_toticks + * + * Description: + * Return a micro-second delay based on the number of bytes left to be + * processed. + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_I2C_DYNTIMEO +static uint32_t stm32_i2c_toticks(int msgc, struct i2c_msg_s *msgs) +{ + size_t bytecount = 0; + int i; + + /* Count the number of bytes left to process */ + + for (i = 0; i < msgc; i++) + { + bytecount += msgs[i].length; + } + + /* Then return a number of microseconds based on a user provided scaling + * factor. + */ + + return USEC2TICK(CONFIG_STM32_I2C_DYNTIMEO_USECPERBYTE * bytecount); +} +#endif + +/**************************************************************************** + * Name: stm32_i2c_sem_waitdone + * + * Description: + * Wait for a transfer to complete + * + ****************************************************************************/ + +#ifndef CONFIG_I2C_POLLED +static int stm32_i2c_sem_waitdone(struct stm32_i2c_priv_s *priv) +{ + irqstate_t flags; + uint32_t regval; + int ret; + + flags = enter_critical_section(); + + /* Enable I2C interrupts */ + + regval = stm32_i2c_getreg(priv, STM32_I2C_CR2_OFFSET); + regval |= (I2C_CR2_ITERREN | I2C_CR2_ITEVFEN); + stm32_i2c_putreg(priv, STM32_I2C_CR2_OFFSET, regval); + + /* Signal the interrupt handler that we are waiting. NOTE: Interrupts + * are currently disabled but will be temporarily re-enabled below when + * nxsem_tickwait_uninterruptible() sleeps. + */ + + priv->intstate = INTSTATE_WAITING; + do + { + /* Wait until either the transfer is complete or the timeout expires */ + +#ifdef CONFIG_STM32_I2C_DYNTIMEO + ret = nxsem_tickwait_uninterruptible(&priv->sem_isr, + stm32_i2c_toticks(priv->msgc, priv->msgv)); +#else + ret = nxsem_tickwait_uninterruptible(&priv->sem_isr, + CONFIG_STM32_I2CTIMEOTICKS); +#endif + if (ret < 0) + { + /* Break out of the loop on irrecoverable errors. This would + * include timeouts and mystery errors reported by + * nxsem_tickwait_uninterruptible. + */ + + break; + } + } + + /* Loop until the interrupt level transfer is complete. */ + + while (priv->intstate != INTSTATE_DONE); + + /* Set the interrupt state back to IDLE */ + + priv->intstate = INTSTATE_IDLE; + + /* Disable I2C interrupts */ + + regval = stm32_i2c_getreg(priv, STM32_I2C_CR2_OFFSET); + regval &= ~I2C_CR2_ALLINTS; + stm32_i2c_putreg(priv, STM32_I2C_CR2_OFFSET, regval); + + leave_critical_section(flags); + return ret; +} +#else +static int stm32_i2c_sem_waitdone(struct stm32_i2c_priv_s *priv) +{ + clock_t timeout; + clock_t start; + clock_t elapsed; + int ret; + + /* Get the timeout value */ + +#ifdef CONFIG_STM32_I2C_DYNTIMEO + timeout = stm32_i2c_toticks(priv->msgc, priv->msgv); +#else + timeout = CONFIG_STM32_I2CTIMEOTICKS; +#endif + + /* Signal the interrupt handler that we are waiting. NOTE: Interrupts + * are currently disabled but will be temporarily re-enabled below when + * nxsem_tickwait_uninterruptible() sleeps. + */ + + priv->intstate = INTSTATE_WAITING; + start = clock_systime_ticks(); + + do + { + /* Calculate the elapsed time */ + + elapsed = clock_systime_ticks() - start; + + /* Poll by simply calling the timer interrupt handler until it + * reports that it is done. + */ + + stm32_i2c_isr_process(priv); + } + + /* Loop until the transfer is complete. */ + + while (priv->intstate != INTSTATE_DONE && elapsed < timeout); + + i2cinfo("intstate: %d elapsed: %ld threshold: %ld status: %08" PRIx32 "\n", + priv->intstate, (long)elapsed, (long)timeout, priv->status); + + /* Set the interrupt state back to IDLE */ + + ret = priv->intstate == INTSTATE_DONE ? OK : -ETIMEDOUT; + priv->intstate = INTSTATE_IDLE; + return ret; +} +#endif + +/**************************************************************************** + * Name: stm32_i2c_sem_waitstop + * + * Description: + * Wait for a STOP to complete + * + ****************************************************************************/ + +static inline void stm32_i2c_sem_waitstop(struct stm32_i2c_priv_s *priv) +{ + clock_t start; + clock_t elapsed; + clock_t timeout; + uint32_t cr1; + uint32_t sr1; + + /* Select a timeout */ + +#ifdef CONFIG_STM32_I2C_DYNTIMEO + timeout = USEC2TICK(CONFIG_STM32_I2C_DYNTIMEO_STARTSTOP); +#else + timeout = CONFIG_STM32_I2CTIMEOTICKS; +#endif + + /* Wait as stop might still be in progress; but stop might also + * be set because of a timeout error: "The [STOP] bit is set and + * cleared by software, cleared by hardware when a Stop condition is + * detected, set by hardware when a timeout error is detected." + */ + + start = clock_systime_ticks(); + do + { + /* Calculate the elapsed time */ + + elapsed = clock_systime_ticks() - start; + + /* Check for STOP condition */ + + cr1 = stm32_i2c_getreg(priv, STM32_I2C_CR1_OFFSET); + if ((cr1 & I2C_CR1_STOP) == 0) + { + return; + } + + /* Check for timeout error */ + + sr1 = stm32_i2c_getreg(priv, STM32_I2C_SR1_OFFSET); + if ((sr1 & I2C_SR1_TIMEOUT) != 0) + { + return; + } + } + + /* Loop until the stop is complete or a timeout occurs. */ + + while (elapsed < timeout); + + /* If we get here then a timeout occurred with the STOP condition + * still pending. + */ + + i2cinfo("Timeout with CR1: %04" PRIx32 " SR1: %04" PRIx32 "\n", cr1, sr1); +} + +/**************************************************************************** + * Name: stm32_i2c_trace* + * + * Description: + * I2C trace instrumentation + * + ****************************************************************************/ + +#ifdef CONFIG_I2C_TRACE +static void stm32_i2c_traceclear(struct stm32_i2c_priv_s *priv) +{ + struct stm32_trace_s *trace = &priv->trace[priv->tndx]; + + trace->status = 0; /* I2C 32-bit SR2|SR1 status */ + trace->count = 0; /* Interrupt count when status change */ + trace->event = I2CEVENT_NONE; /* Last event that occurred with this status */ + trace->parm = 0; /* Parameter associated with the event */ + trace->time = 0; /* Time of first status or event */ +} + +static void stm32_i2c_tracereset(struct stm32_i2c_priv_s *priv) +{ + /* Reset the trace info for a new data collection */ + + priv->tndx = 0; + priv->start_time = clock_systime_ticks(); + stm32_i2c_traceclear(priv); +} + +static void stm32_i2c_tracenew(struct stm32_i2c_priv_s *priv, + uint16_t status) +{ + struct stm32_trace_s *trace = &priv->trace[priv->tndx]; + + /* Is the current entry uninitialized? Has the status changed? */ + + if (trace->count == 0 || status != trace->status) + { + /* Yes.. Was it the status changed? */ + + if (trace->count != 0) + { + /* Yes.. bump up the trace index + * (unless we are out of trace entries) + */ + + if (priv->tndx >= (CONFIG_I2C_NTRACE - 1)) + { + i2cerr("ERROR: Trace table overflow\n"); + return; + } + + priv->tndx++; + trace = &priv->trace[priv->tndx]; + } + + /* Initialize the new trace entry */ + + stm32_i2c_traceclear(priv); + trace->status = status; + trace->count = 1; + trace->time = clock_systime_ticks(); + } + else + { + /* Just increment the count of times that we have seen this status */ + + trace->count++; + } +} + +static void stm32_i2c_traceevent(struct stm32_i2c_priv_s *priv, + uint16_t event, uint32_t parm) +{ + struct stm32_trace_s *trace; + + if (event != I2CEVENT_NONE || event != I2CEVENT_POLL_DEV_NOT_RDY) + { + trace = &priv->trace[priv->tndx]; + + /* Initialize the new trace entry */ + + trace->event = event; + trace->parm = parm; + + /* Bump up the trace index (unless we are out of trace entries) */ + + if (priv->tndx >= (CONFIG_I2C_NTRACE - 1)) + { + i2cerr("ERROR: Trace table overflow\n"); + return; + } + + priv->tndx++; + stm32_i2c_traceclear(priv); + } +} + +static void stm32_i2c_tracedump(struct stm32_i2c_priv_s *priv) +{ + struct stm32_trace_s *trace; + int i; + + syslog(LOG_DEBUG, "Elapsed time: %ld\n", + (long)(clock_systime_ticks() - priv->start_time)); + + for (i = 0; i < priv->tndx; i++) + { + trace = &priv->trace[i]; + syslog(LOG_DEBUG, + "%2d. STATUS: %08" PRIx32 " COUNT: %4d EVENT: %4d PARM:" + " %08" PRIx32 " TIME: %d\n", + i + 1, trace->status, trace->count, trace->event, trace->parm, + trace->time - priv->start_time); + } +} +#endif /* CONFIG_I2C_TRACE */ + +/**************************************************************************** + * Name: stm32_i2c_setclock + * + * Description: + * Set the I2C clock + * + ****************************************************************************/ + +static void stm32_i2c_setclock(struct stm32_i2c_priv_s *priv, + uint32_t frequency) +{ + uint16_t cr1; + uint16_t ccr; + uint16_t trise; + uint16_t freqmhz; + uint16_t speed; + + /* Has the I2C bus frequency changed? */ + + if (frequency != priv->frequency) + { + /* Disable the selected I2C peripheral to configure TRISE */ + + cr1 = stm32_i2c_getreg(priv, STM32_I2C_CR1_OFFSET); + stm32_i2c_putreg(priv, STM32_I2C_CR1_OFFSET, cr1 & ~I2C_CR1_PE); + + /* Update timing and control registers */ + + freqmhz = (uint16_t)(STM32_PCLK1_FREQUENCY / 1000000); + ccr = 0; + + /* Configure speed in standard mode */ + + if (frequency <= 100000) + { + /* Standard mode speed calculation */ + + speed = (uint16_t)(STM32_PCLK1_FREQUENCY / (frequency << 1)); + + /* The CCR fault must be >= 4 */ + + if (speed < 4) + { + /* Set the minimum allowed value */ + + speed = 4; + } + + ccr |= speed; + + /* Set Maximum Rise Time for standard mode */ + + trise = freqmhz + 1; + } + + /* Configure speed in fast mode */ + + else /* (frequency <= 400000) */ + { + /* Fast mode speed calculation with Tlow/Thigh = 16/9 */ + +#ifdef CONFIG_STM32_I2C_DUTY16_9 + speed = (uint16_t)(STM32_PCLK1_FREQUENCY / (frequency * 25)); + + /* Set DUTY and fast speed bits */ + + ccr |= (I2C_CCR_DUTY | I2C_CCR_FS); +#else + /* Fast mode speed calculation with Tlow/Thigh = 2 */ + + speed = (uint16_t)(STM32_PCLK1_FREQUENCY / (frequency * 3)); + + /* Set fast speed bit */ + + ccr |= I2C_CCR_FS; +#endif + + /* Verify that the CCR speed value is nonzero */ + + if (speed < 1) + { + /* Set the minimum allowed value */ + + speed = 1; + } + + ccr |= speed; + + /* Set Maximum Rise Time for fast mode */ + + trise = (uint16_t)(((freqmhz * 300) / 1000) + 1); + } + + /* Write the new values of the CCR and TRISE registers */ + + stm32_i2c_putreg(priv, STM32_I2C_CCR_OFFSET, ccr); + stm32_i2c_putreg(priv, STM32_I2C_TRISE_OFFSET, trise); + + /* Bit 14 of OAR1 must be configured and kept at 1 */ + + stm32_i2c_putreg(priv, STM32_I2C_OAR1_OFFSET, I2C_OAR1_ONE); + + /* Re-enable the peripheral (or not) */ + + stm32_i2c_putreg(priv, STM32_I2C_CR1_OFFSET, cr1); + + /* Save the new I2C frequency */ + + priv->frequency = frequency; + } +} + +/**************************************************************************** + * Name: stm32_i2c_sendstart + * + * Description: + * Send the START conditions/force Master mode + * + ****************************************************************************/ + +static inline void stm32_i2c_sendstart(struct stm32_i2c_priv_s *priv) +{ + /* Disable ACK on receive by default and generate START */ + + stm32_i2c_modifyreg(priv, STM32_I2C_CR1_OFFSET, + I2C_CR1_ACK, I2C_CR1_START); +} + +/**************************************************************************** + * Name: stm32_i2c_clrstart + * + * Description: + * Clear the STOP, START or PEC condition on certain error recovery steps. + * + ****************************************************************************/ + +static inline void stm32_i2c_clrstart(struct stm32_i2c_priv_s *priv) +{ + /* "Note: When the STOP, START or PEC bit is set, the software must + * not perform any write access to I2C_CR1 before this bit is + * cleared by hardware. Otherwise there is a risk of setting a + * second STOP, START or PEC request." + * + * "The [STOP] bit is set and cleared by software, cleared by hardware + * when a Stop condition is detected, set by hardware when a timeout + * error is detected. + * + * "This [START] bit is set and cleared by software and cleared by hardware + * when start is sent or PE=0." The bit must be cleared by software if + * the START is never sent. + * + * "This [PEC] bit is set and cleared by software, and cleared by hardware + * when PEC is transferred or by a START or Stop condition or when PE=0." + */ + + stm32_i2c_modifyreg(priv, STM32_I2C_CR1_OFFSET, + I2C_CR1_START | I2C_CR1_STOP | I2C_CR1_PEC, 0); +} + +/**************************************************************************** + * Name: stm32_i2c_sendstop + * + * Description: + * Send the STOP conditions + * + ****************************************************************************/ + +static inline void stm32_i2c_sendstop(struct stm32_i2c_priv_s *priv) +{ + stm32_i2c_modifyreg(priv, STM32_I2C_CR1_OFFSET, I2C_CR1_ACK, I2C_CR1_STOP); +} + +/**************************************************************************** + * Name: stm32_i2c_getstatus + * + * Description: + * Get 32-bit status (SR1 and SR2 combined) + * + ****************************************************************************/ + +static inline uint32_t stm32_i2c_getstatus(struct stm32_i2c_priv_s *priv) +{ + uint32_t status = stm32_i2c_getreg(priv, STM32_I2C_SR1_OFFSET); + status |= (stm32_i2c_getreg(priv, STM32_I2C_SR2_OFFSET) << 16); + return status; +} + +/**************************************************************************** + * Name: stm32_i2c_disablefsmc + * + * Description: + * FSMC must be disable while accessing I2C1 because it uses a common + * resource (LBAR) + * + * NOTE: This is an issue with the STM32F103ZE, but may not be an issue with + * other STM32s. You may need to experiment + * + ****************************************************************************/ + +#ifdef I2C1_FSMC_CONFLICT +static inline +uint32_t stm32_i2c_disablefsmc(struct stm32_i2c_priv_s *priv) +{ + uint32_t ret = 0; + uint32_t regval; + + /* Is this I2C1 */ + +#if defined(CONFIG_STM32_I2C2) || defined(CONFIG_STM32_I2C3) + if (priv->config->base == STM32_I2C1_BASE) +#endif + { + /* Disable FSMC unconditionally */ + + ret = getreg32(STM32_RCC_AHBENR); + regval = ret & ~RCC_AHBENR_FSMCEN; + putreg32(regval, STM32_RCC_AHBENR); + } + + return ret; +} + +/**************************************************************************** + * Name: stm32_i2c_enablefsmc + * + * Description: + * Re-enable the FSMC + * + ****************************************************************************/ + +static inline void stm32_i2c_enablefsmc(uint32_t ahbenr) +{ + uint32_t regval; + + /* Enable AHB clocking to the FSMC only if it was previously enabled. */ + + if ((ahbenr & RCC_AHBENR_FSMCEN) != 0) + { + regval = getreg32(STM32_RCC_AHBENR); + regval |= RCC_AHBENR_FSMCEN; + putreg32(regval, STM32_RCC_AHBENR); + } +} +#else +# define stm32_i2c_disablefsmc(priv) (0) +# define stm32_i2c_enablefsmc(ahbenr) +#endif /* I2C1_FSMC_CONFLICT */ + +/**************************************************************************** + * Name: stm32_i2c_isr_process + * + * Description: + * Common interrupt service routine (ISR) that handles I2C protocol logic. + * + * This ISR is activated and deactivated by stm32_i2c_waitdone(). + * Interrupt fires on(both ITEVFEN and ITBUFEN are set): + * + * - Start bit + * - Address sent + * - 10-bit header sent + * - Data byte transfer finished + * - Receive buffer not empty + * - Transmit buffer empty + * + * Input Parameters: + * priv - The private struct of the I2C driver. + * + * Returned Value: + * + ****************************************************************************/ + +static int stm32_i2c_isr_process(struct stm32_i2c_priv_s *priv) +{ +#ifndef CONFIG_I2C_POLLED + uint32_t regval; +#endif + uint32_t status; + + i2cinfo("I2C ISR called\n"); + + /* Get state of the I2C controller (register SR1 only) + * + * Get control register SR1 only as reading both SR1 and SR2 clears the + * ADDR flag(possibly others) causing the hardware to advance to the + * next state without the proper action being taken. + */ + + status = stm32_i2c_getreg(priv, STM32_I2C_SR1_OFFSET); + + /* Update private version of the state */ + + priv->status = status; + + /* Check if this is a new transmission so to set up the + * trace table accordingly. + */ + + stm32_i2c_tracenew(priv, status); + stm32_i2c_traceevent(priv, I2CEVENT_ISR_CALL, 0); + + /* Messages handling (1/2) + * + * Message handling should only operate when a message has been completely + * sent and after the ISR had the chance to run to set bits after the last + * written/read byte, i.e. priv->dcnt == -1. This is also the case in when + * the ISR is called for the first time. This can seen in + * stm32_i2c_transfer() before entering the stm32_i2c_sem_waitdone() + * waiting process. + * + * Message handling should only operate when: + * - A message has been completely sent and there are still messages + * to send(i.e. msgc > 0). + * - After the ISR had the chance to run to set start bit or + * termination flags after the last written/read byte(after last byte + * dcnt=0, msg handling dcnt = -1). + * + * When the ISR is called for the first time the same conditions hold. + * This can seen in stm32_i2c_transfer() before entering the + * stm32_i2c_sem_waitdone() waiting process. + */ + + if (priv->dcnt == -1 && priv->msgc > 0) + { + i2cinfo("Switch to new message\n"); + + /* Get current message to process data and copy to private structure */ + + priv->ptr = priv->msgv->buffer; /* Copy buffer to private struct */ + priv->dcnt = priv->msgv->length; /* Set counter of current msg length */ + priv->total_msg_len = priv->msgv->length; /* Set total msg length */ + priv->flags = priv->msgv->flags; /* Copy flags to private struct */ + + i2cinfo("Current flags %i\n", priv->flags); + + /* Decrease counter to indicate the number of messages left to + * process + */ + + priv->msgc--; + + /* Decrease message pointer. If last message set next message vector + * to null + */ + + if (priv->msgc == 0) + { + /* No more messages, don't need to increment msgv. This pointer + * will be set to zero when reaching the termination of the ISR + * calls, i.e. Messages handling(2/2). + */ + } + else + { + /* If not last message increment to next message to process */ + + priv->msgv++; + } + + /* Trace event */ + + stm32_i2c_traceevent(priv, I2CEVENT_MSG_HANDLING, priv->msgc); + } + + /* Note the event where we are on the last message and after the last + * byte is handled at the bottom of this function, as it terminates + * the repeated calls to the ISR. + */ + + /* I2C protocol logic + * + * I2C protocol logic follows. It's organized in an if else chain such that + * only one mode of operation is executed every time the ISR is called. + */ + + /* Address Handling + * + * Check if a start bit was set and transmit address with proper format. + * + * Note: + * On first call the start bit has been set by stm32_i2c_waitdone() + * Otherwise it will be set from this ISR. + * + * Remember that after a start bit an address has always to be sent. + */ + + if ((status & I2C_SR1_SB) != 0) + { + /* Start bit is set */ + + i2cinfo("Entering address handling, status = %" PRIi32 "\n", status); + + /* Check for empty message (for robustness) */ + + if (priv->dcnt > 0) + { + /* When reading messages of length 1 or 2 actions have to be taken + * during this event. The following block handles that. + */ + + if (priv->total_msg_len == 1 && (priv->flags & I2C_M_READ)) + { + i2cinfo("short read N=1: setting NACK\n"); + + /* Set POS bit to zero + * (can be up from a previous 2 byte receive) + */ + + stm32_i2c_modifyreg(priv, + STM32_I2C_CR1_OFFSET, I2C_CR1_POS, 0); + + /* Immediately set NACK */ + + stm32_i2c_modifyreg(priv, + STM32_I2C_CR1_OFFSET, I2C_CR1_ACK, 0); + stm32_i2c_traceevent(priv, I2CEVENT_ADDR_HDL_READ_1, 0); + } + else if (priv->total_msg_len == 2 && (priv->flags & I2C_M_READ)) + { + i2cinfo("short read N=2: setting POS and ACK bits\n"); + + stm32_i2c_modifyreg(priv, + STM32_I2C_CR1_OFFSET, 0, I2C_CR1_POS); + stm32_i2c_modifyreg(priv, + STM32_I2C_CR1_OFFSET, 0, I2C_CR1_ACK); + stm32_i2c_traceevent(priv, + I2CEVENT_ADDR_HDL_READ_2, 0); + } + else + { + /* Enable ACK after address byte */ + + i2cinfo("setting ACK\n"); + + /* Set POS bit to zero + * (can be up from a previous 2 byte receive) + */ + + stm32_i2c_modifyreg(priv, + STM32_I2C_CR1_OFFSET, I2C_CR1_POS, 0); + + /* ACK is the expected answer for N>=3 reads and writes */ + + stm32_i2c_modifyreg(priv, + STM32_I2C_CR1_OFFSET, 0, I2C_CR1_ACK); + } + + /* Send address byte with correct 8th bit set(for writing or + * reading) Transmission happens after having written to the + * data register STM32_I2C_DR + */ + + stm32_i2c_putreg(priv, STM32_I2C_DR_OFFSET, + (priv->flags & I2C_M_TEN) ? + 0 : ((priv->msgv->addr << 1) | + (priv->flags & I2C_M_READ))); + + i2cinfo("Address sent. Addr=%#02x Write/Read bit=%i\n", + priv->msgv->addr, (priv->flags & I2C_M_READ)); + + /* Flag that address has just been sent */ + + priv->check_addr_ack = true; + + stm32_i2c_traceevent(priv, I2CEVENT_SENDADDR, priv->msgv->addr); + } + else + { + /* TODO: untested!! */ + + i2cwarn("WARNING: An empty message has been detected, " + "ignoring and passing to next message.\n"); + + /* Trace event */ + + stm32_i2c_traceevent(priv, I2CEVENT_EMPTY_MSG, 0); + + /* Set condition to activate msg handling */ + + priv->dcnt = -1; + + /* Restart ISR by setting an interrupt buffer bit */ + + stm32_i2c_modifyreg(priv, + STM32_I2C_CR2_OFFSET, 0, I2C_CR2_ITBUFEN); + } + } + + /* Address cleared event + * + * Check if the address cleared, i.e. the driver found a valid + * address. + * If a NACK was received the address is invalid, if an ACK was + * received the address is valid and transmission can continue. + */ + + /* Check for NACK after an address */ + +#ifndef CONFIG_I2C_POLLED + /* When polling the i2c ISR it's not possible to determine when + * an address has been ACKed(i.e. the address is valid). + * + * The mechanism to deal a NACKed address is to wait for the I2C + * call to timeout (value defined in defconfig by one of the + * following: CONFIG_STM32_I2C_DYNTIMEO, CONFIG_STM32_I2CTIMEOSEC, + * CONFIG_STM32_I2CTIMEOMS, CONFIG_STM32_I2CTIMEOTICKS). + * + * To be safe in the case of a timeout/NACKed address a stop bit + * is set on the bus to clear it. In POLLED operation it's done + * stm32_i2c_transfer() after the call to stm32_i2c_sem_waitdone(). + * + * In ISR driven operation the stop bit in case of a NACKed address + * is set in the ISR itself. + * + * Note: this commentary is found in both places. + */ + + else if ((status & I2C_SR1_ADDR) == 0 && priv->check_addr_ack) + { + i2cinfo("Invalid Address."); + i2cinfo(" Setting stop bit and clearing message\n"); + i2cinfo("status %" PRIi32 "\n", status); + + /* Set condition to terminate msg chain transmission as address + * is invalid. + */ + + priv->dcnt = -1; + priv->msgc = 0; + + i2cinfo("dcnt %i , msgc %i\n", priv->dcnt, priv->msgc); + + /* Reset flag to check for valid address */ + + priv->check_addr_ack = false; + + /* Send stop bit to clear bus */ + + stm32_i2c_sendstop(priv); + + /* Trace event */ + + stm32_i2c_traceevent(priv, + I2CEVENT_ADDRESS_NACKED, priv->msgv->addr); + } +#endif + + /* ACK in read mode, ACK in write mode is handled separately */ + + else if ((priv->flags & I2C_M_READ) != 0 && (status & I2C_SR1_ADDR) != 0 && + priv->check_addr_ack) + { + /* Reset check addr flag as we are handling this event */ + + priv->check_addr_ack = false; + + /* Clear ADDR flag by reading SR2 and adding it to status */ + + status |= (stm32_i2c_getreg(priv, STM32_I2C_SR2_OFFSET) << 16); + + /* Note: + * + * When reading a single byte the stop condition has to be set + * immediately after clearing the state flags, which happens + * when reading SR2(as SR1 has already been read). + * + * Similarly when reading 2 bytes the NACK bit has to be set as just + * after the clearing of the address. + */ + + if (priv->dcnt == 1 && priv->total_msg_len == 1) + { + /* this should only happen when receiving a message of length 1 */ + + stm32_i2c_modifyreg(priv, + STM32_I2C_CR2_OFFSET, 0, I2C_CR2_ITBUFEN); + stm32_i2c_sendstop(priv); + + i2cinfo("Address ACKed beginning data reception\n"); + i2cinfo("short read N=1: programming stop bit\n"); + priv->dcnt--; + + /* Trace */ + + stm32_i2c_traceevent(priv, I2CEVENT_ADDRESS_ACKED_READ_1, 0); + } + else if (priv->dcnt == 2 && priv->total_msg_len == 2) + { + /* This should only happen when receiving a message of length 2 + * Set NACK + */ + + stm32_i2c_modifyreg(priv, STM32_I2C_CR1_OFFSET, I2C_CR1_ACK, 0); + + i2cinfo("Address ACKed beginning data reception\n"); + i2cinfo("short read N=2: programming NACK\n"); + + /* Trace */ + + stm32_i2c_traceevent(priv, I2CEVENT_ADDRESS_ACKED_READ_2, 0); + } + else + { + i2cinfo("Address ACKed beginning data reception\n"); + + /* Trace */ + + stm32_i2c_traceevent(priv, I2CEVENT_ADDRESS_ACKED, 0); + } + } + + /* Write mode + * + * Handles all write related I2C protocol logic. Also handles the + * ACK event after clearing the ADDR flag as the write has to + * begin immediately after. + */ + + else if ((priv->flags & (I2C_M_READ)) == 0 && + (status & (I2C_SR1_ADDR | I2C_SR1_TXE)) != 0) + { + /* The has cleared(ADDR is set, ACK was received after the address) + * or the transmit buffer is empty flag has been set(TxE) then we can + * transmit the next byte. + */ + + i2cinfo("Entering write mode dcnt = %i msgc = %i\n", + priv->dcnt, priv->msgc); + + /* Clear ADDR flag by reading SR2 and adding it to status */ + + status |= (stm32_i2c_getreg(priv, STM32_I2C_SR2_OFFSET) << 16); + + /* Address has cleared so don't check on next call */ + + priv->check_addr_ack = false; + + /* Check if we have transmitted the whole message or we are after + * the last byte where the stop condition or else(according to the + * msg flags) has to be set. + */ + + if (priv->dcnt >= 1) + { + /* Transmitting message. + * Send byte == write data into write register + */ + + stm32_i2c_putreg(priv, STM32_I2C_DR_OFFSET, *priv->ptr++); + + /* Decrease current message length */ + + stm32_i2c_traceevent(priv, I2CEVENT_WRITE_TO_DR, priv->dcnt); + priv->dcnt--; + } + else if (priv->dcnt == 0) + { + /* After last byte, check what to do based on next message flags */ + + if (priv->msgc == 0) + { + /* If last message send stop bit */ + + stm32_i2c_sendstop(priv); + i2cinfo("Stop sent dcnt = %i msgc = %i\n", + priv->dcnt, priv->msgc); + + /* Decrease counter to get to next message */ + + priv->dcnt--; + i2cinfo("dcnt %i\n", priv->dcnt); + stm32_i2c_traceevent(priv, I2CEVENT_WRITE_STOP, priv->dcnt); + } + + /* If there is a next message with no flags or the read flag + * a restart sequence has to be sent. + * Note msgv already points to the next message. + */ + + else if (priv->msgc > 0 && + (priv->msgv->flags == 0 || + (priv->msgv[0].flags & I2C_M_READ) != 0)) + { + stm32_i2c_sendstart(priv); + + i2cinfo("Restart detected!\n"); + i2cinfo("Nextflag %i\n", priv->msgv[0].flags); + + /* Decrease counter to get to next message */ + + priv->dcnt--; + i2cinfo("dcnt %i\n", priv->dcnt); + stm32_i2c_traceevent(priv, I2CEVENT_WRITE_RESTART, priv->dcnt); + } + + /* If there is a next message with the NO_RESTART flag + * do nothing. + */ + + else if (priv->msgc > 0 && + ((priv->msgv->flags & I2C_M_NOSTART) != 0)) + { + /* Set condition to get to next message */ + + priv->dcnt = -1; + stm32_i2c_traceevent(priv, + I2CEVENT_WRITE_NO_RESTART, priv->dcnt); + } + else + { + i2cerr( + "ERROR: Write mode: next message has an unrecognized flag.\n"); + stm32_i2c_traceevent(priv, I2CEVENT_WRITE_FLAG_ERROR, + priv->msgv->flags); + } + } + else + { + i2cerr("ERROR: Write mode error.\n"); + stm32_i2c_traceevent(priv, I2CEVENT_WRITE_ERROR, 0); + } + } + + /* Read mode + * + * Handles all read related I2C protocol logic. + * + * * * * * * * WARNING STM32F1xx HARDWARE ERRATA * * * * * * * + * source: https://github.com/hikob/openlab/blob/master/drivers/stm32/i2c.c + * + * RXNE-only events should not be handled since it sometimes + * fails. Only BTF & RXNE events should be handled (with the + * consequence of slowing down the transfer). + * + * It seems that when a RXNE interrupt is handled 'around' + * the end of the next byte reception, the DR register read + * is ignored by the i2c controller: it does not flush the + * DR with next byte + * + * Thus we read twice the same byte and we read effectively + * read one byte less than expected from the i2c slave point + * of view. + * + * Example: + * + we want to receive 6 bytes (B1 to B6) + * + the problem appear when reading B3 + * -> we read B1 B2 B3 B3 B4 B5(B3 twice) + * -> the i2c transfer was B1 B2 B3 B4 B5(B6 is not sent) + */ + + else if ((priv->flags & (I2C_M_READ)) != 0 && (status & I2C_SR1_RXNE) != 0) + { + /* When read flag is set and the receive buffer is not empty + * (RXNE is set) then the driver can read from the data register. + */ + + i2cinfo("Entering read mode dcnt = %i msgc = %i, status %" PRIi32 "\n", + priv->dcnt, priv->msgc, status); + + /* Implementation of method 2 for receiving data following + * the stm32f1xx reference manual. + */ + + /* Case total message length = 1 */ + + if (priv->dcnt == 0 && priv->total_msg_len == 1) + { + i2cinfo("short read N=1: Read data from data register(DR)\n"); + + *priv->ptr++ = stm32_i2c_getreg(priv, STM32_I2C_DR_OFFSET); + priv->dcnt--; + stm32_i2c_traceevent(priv, I2CEVENT_READ, 0); + } + + /* Case total message length = 2 */ + + else if (priv->dcnt == 2 && priv->total_msg_len == 2 && + !(status & I2C_SR1_BTF)) + { + i2cinfo("short read N=2: " + "DR full, SR empty. Waiting for more bytes.\n"); + stm32_i2c_traceevent(priv, I2CEVENT_READ_SR_EMPTY, 0); + } + else if (priv->dcnt == 2 && priv->total_msg_len == 2 && + (status & I2C_SR1_BTF)) + { + i2cinfo("short read N=2: " + "DR and SR full setting stop bit and reading twice\n"); + + stm32_i2c_sendstop(priv); + *priv->ptr++ = stm32_i2c_getreg(priv, STM32_I2C_DR_OFFSET); + priv->dcnt--; + *priv->ptr++ = stm32_i2c_getreg(priv, STM32_I2C_DR_OFFSET); + priv->dcnt--; + + /* Stop request already programmed so set dcnt for next message */ + + priv->dcnt--; + + /* Set trace */ + + stm32_i2c_traceevent(priv, I2CEVENT_READ_2, 0); + } + + /* Case total message length >= 3 */ + + else if (priv->total_msg_len >= 3 && !(status & I2C_SR1_BTF)) + { + /* If the shift register is still empty (i.e. BTF is low) + * then do nothing and wait for it to fill in the next ISR. + * (should not happen in ISR mode, but if using polled mode + * this should be able to handle it). + */ + + i2cinfo("DR full, SR empty. Waiting for more bytes.\n"); + stm32_i2c_traceevent(priv, I2CEVENT_READ_SR_EMPTY, 0); + } + else if (priv->dcnt >= 4 && + priv->total_msg_len >= 3 && (status & I2C_SR1_BTF)) + { + /* Read data from data register(DR). Note this clears the + * RXNE(receive buffer not empty) flag. + */ + + i2cinfo("Read data from data register(DR)\n"); + *priv->ptr++ = stm32_i2c_getreg(priv, STM32_I2C_DR_OFFSET); + + /* Decrease current message length */ + + priv->dcnt--; + stm32_i2c_traceevent(priv, I2CEVENT_READ, 0); + } + else if (priv->dcnt == 3 && + (status & I2C_SR1_BTF) && priv->total_msg_len >= 3) + { + /* This means that we are reading dcnt 3 and there is + * already dcnt 2 in the shift register. + * This coincides with EV7_2 in the reference manual. + */ + + i2cinfo("Program NACK\n"); + i2cinfo("Read data from data register(DR) dcnt=3\n"); + + stm32_i2c_traceevent(priv, I2CEVENT_READ_3, priv->dcnt); + + /* Program NACK */ + + stm32_i2c_modifyreg(priv, STM32_I2C_CR1_OFFSET, I2C_CR1_ACK, 0); + + /* Read dcnt = 3, to ensure a BTF event after having received + * in the shift register. + */ + + *priv->ptr++ = stm32_i2c_getreg(priv, STM32_I2C_DR_OFFSET); + + /* Decrease current message length */ + + priv->dcnt--; + } + else if (priv->dcnt == 2 && + (status & I2C_SR1_BTF) && priv->total_msg_len >= 3) + { + i2cinfo("Program stop\n"); + i2cinfo("Read data from data register(DR) dcnt=2\n"); + i2cinfo("Read data from data register(SR) dcnt=1\n"); + i2cinfo("Setting condition to stop ISR dcnt = -1\n"); + + stm32_i2c_traceevent(priv, I2CEVENT_READ_3, priv->dcnt); + + /* Program stop */ + + stm32_i2c_sendstop(priv); + + /* read dcnt = 2 */ + + *priv->ptr++ = stm32_i2c_getreg(priv, STM32_I2C_DR_OFFSET); + + /* read last byte dcnt=1 */ + + *priv->ptr++ = stm32_i2c_getreg(priv, STM32_I2C_DR_OFFSET); + + /* Stop already sent will not get another interrupt set + * condition to stop ISR + */ + + priv->dcnt = -1; + } + + /* Error handling for read mode */ + + else + { + i2cerr("ERROR: I2C read mode no correct state detected\n"); + i2cerr(" state %" PRIi32 ", dcnt=%i\n", status, priv->dcnt); + + /* set condition to terminate ISR and wake waiting thread */ + + priv->dcnt = -1; + priv->msgc = 0; + stm32_i2c_traceevent(priv, I2CEVENT_READ_ERROR, 0); + } + + /* Read rest of the state */ + + status |= (stm32_i2c_getreg(priv, STM32_I2C_SR2_OFFSET) << 16); + } + + /* Empty call handler + * + * Case to handle an empty call to the ISR where it only has to + * Shutdown + */ + + else if (priv->dcnt == -1 && priv->msgc == 0) + { + /* Read rest of the state */ + + status |= (stm32_i2c_getreg(priv, STM32_I2C_SR2_OFFSET) << 16); + i2cwarn("WARNING: Empty call to ISR: Stopping ISR\n"); + stm32_i2c_traceevent(priv, I2CEVENT_ISR_EMPTY_CALL, 0); + } + + /* Error handler + * + * Gets triggered if the driver does not recognize a situation(state) + * it can deal with. + * This should not happen in interrupt based operation(i.e. when + * CONFIG_I2C_POLLED is not set in the defconfig file). + * During polled operation(i.e. CONFIG_I2C_POLLED=y in defconfig) + * this case should do nothing but tracing the event that the + * device wasn't ready yet. + */ + + else + { +#ifdef CONFIG_I2C_POLLED + stm32_i2c_traceevent(priv, I2CEVENT_POLL_DEV_NOT_RDY, 0); +#else + /* Read rest of the state */ + + status |= (stm32_i2c_getreg(priv, STM32_I2C_SR2_OFFSET) << 16); + + i2cerr("ERROR: " + "No correct state detected(start bit, read or write)\n"); + i2cerr(" state %" PRIi32 "\n", status); + + /* Set condition to terminate ISR and wake waiting thread */ + + priv->dcnt = -1; + priv->msgc = 0; + stm32_i2c_traceevent(priv, I2CEVENT_STATE_ERROR, 0); +#endif + } + + /* Messages handling(2/2) + * + * Transmission of the whole message chain has been completed. We have to + * terminate the ISR and wake up stm32_i2c_transfer() that is waiting for + * the ISR cycle to handle the sending/receiving of the messages. + */ + + /* First check for errors */ + + if ((status & I2C_SR1_ERRORMASK) != 0) + { + stm32_i2c_traceevent(priv, + I2CEVENT_ISR_SR1ERROR, + status & I2C_SR1_ERRORMASK); + + /* Clear interrupt flags */ + + stm32_i2c_putreg(priv, STM32_I2C_SR1_OFFSET, 0); + + priv->dcnt = -1; + priv->msgc = 0; + } + + if (priv->dcnt == -1 && priv->msgc == 0) + { + i2cinfo("Shutting down I2C ISR\n"); + + stm32_i2c_traceevent(priv, I2CEVENT_ISR_SHUTDOWN, 0); + + /* Clear internal pointer to the message content. + * Good practice + done by last implementation when messages are + * finished (compatibility concerns) + */ + + priv->msgv = NULL; + +#ifdef CONFIG_I2C_POLLED + priv->intstate = INTSTATE_DONE; +#else + /* Clear all interrupts */ + + regval = stm32_i2c_getreg(priv, STM32_I2C_CR2_OFFSET); + regval &= ~I2C_CR2_ALLINTS; + stm32_i2c_putreg(priv, STM32_I2C_CR2_OFFSET, regval); + + /* Is there a thread waiting for this event(there should be) */ + + if (priv->intstate == INTSTATE_WAITING) + { + /* Yes.. inform the thread that the transfer is complete + * and wake it up. + */ + + nxsem_post(&priv->sem_isr); + priv->intstate = INTSTATE_DONE; + } +#endif + } + + return OK; +} + +/**************************************************************************** + * Name: stm32_i2c_isr + * + * Description: + * Common I2C interrupt service routine + * + ****************************************************************************/ + +#ifndef CONFIG_I2C_POLLED +static int stm32_i2c_isr(int irq, void *context, void *arg) +{ + struct stm32_i2c_priv_s *priv = (struct stm32_i2c_priv_s *)arg; + + DEBUGASSERT(priv != NULL); + return stm32_i2c_isr_process(priv); +} +#endif + +/**************************************************************************** + * Name: stm32_i2c_init + * + * Description: + * Setup the I2C hardware, ready for operation with defaults + * + ****************************************************************************/ + +static int stm32_i2c_init(struct stm32_i2c_priv_s *priv) +{ + /* Power-up and configure GPIOs */ + + /* Enable power and reset the peripheral */ + + modifyreg32(STM32_RCC_APB1ENR, 0, priv->config->clk_bit); + modifyreg32(STM32_RCC_APB1RSTR, 0, priv->config->reset_bit); + modifyreg32(STM32_RCC_APB1RSTR, priv->config->reset_bit, 0); + + /* Configure pins */ + + if (stm32_configgpio(priv->config->scl_pin) < 0) + { + return ERROR; + } + + if (stm32_configgpio(priv->config->sda_pin) < 0) + { + stm32_unconfiggpio(priv->config->scl_pin); + return ERROR; + } + + /* Attach ISRs */ + +#ifndef CONFIG_I2C_POLLED + irq_attach(priv->config->ev_irq, stm32_i2c_isr, priv); + irq_attach(priv->config->er_irq, stm32_i2c_isr, priv); + up_enable_irq(priv->config->ev_irq); + up_enable_irq(priv->config->er_irq); +#endif + + /* Set peripheral frequency, where it must be at least 2 MHz for 100 kHz + * or 4 MHz for 400 kHz. This also disables all I2C interrupts. + */ + + stm32_i2c_putreg(priv, + STM32_I2C_CR2_OFFSET, (STM32_PCLK1_FREQUENCY / 1000000)); + + /* Force a frequency update */ + + priv->frequency = 0; + + stm32_i2c_setclock(priv, 100000); + + /* Enable I2C */ + + stm32_i2c_putreg(priv, STM32_I2C_CR1_OFFSET, I2C_CR1_PE); + return OK; +} + +/**************************************************************************** + * Name: stm32_i2c_deinit + * + * Description: + * Shutdown the I2C hardware + * + ****************************************************************************/ + +static int stm32_i2c_deinit(struct stm32_i2c_priv_s *priv) +{ + /* Disable I2C */ + + stm32_i2c_putreg(priv, STM32_I2C_CR1_OFFSET, 0); + + /* Unconfigure GPIO pins */ + + stm32_unconfiggpio(priv->config->scl_pin); + stm32_unconfiggpio(priv->config->sda_pin); + + /* Disable and detach interrupts */ + +#ifndef CONFIG_I2C_POLLED + up_disable_irq(priv->config->ev_irq); + up_disable_irq(priv->config->er_irq); + irq_detach(priv->config->ev_irq); + irq_detach(priv->config->er_irq); +#endif + + /* Disable clocking */ + + modifyreg32(STM32_RCC_APB1ENR, priv->config->clk_bit, 0); + return OK; +} + +/**************************************************************************** + * Device Driver Operations + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_i2c_transfer + * + * Description: + * Generic I2C transfer function + * + ****************************************************************************/ + +static int stm32_i2c_transfer(struct i2c_master_s *dev, + struct i2c_msg_s *msgs, int count) +{ + struct stm32_i2c_priv_s *priv = (struct stm32_i2c_priv_s *)dev; + uint32_t status = 0; +#ifdef I2C1_FSMC_CONFLICT + uint32_t ahbenr; +#endif + int ret; + + DEBUGASSERT(dev != NULL && msgs != NULL && count > 0); + + /* Ensure that address or flags don't change meanwhile */ + + ret = nxmutex_lock(&priv->lock); + if (ret < 0) + { + return ret; + } + +#ifdef I2C1_FSMC_CONFLICT + /* Disable FSMC that shares a pin with I2C1 (LBAR) */ + + ahbenr = stm32_i2c_disablefsmc(priv); + +#else + /* Wait for any STOP in progress. NOTE: If we have to disable the FSMC + * then we cannot do this at the top of the loop, unfortunately. The STOP + * will not complete normally if the FSMC is enabled. + */ + + stm32_i2c_sem_waitstop(priv); +#endif + + /* Clear any pending error interrupts */ + + stm32_i2c_putreg(priv, STM32_I2C_SR1_OFFSET, 0); + + /* "Note: When the STOP, START or PEC bit is set, the software must + * not perform any write access to I2C_CR1 before this bit is + * cleared by hardware. Otherwise there is a risk of setting a + * second STOP, START or PEC request." However, if the bits are + * not cleared by hardware, then we will have to do that from hardware. + */ + + stm32_i2c_clrstart(priv); + + /* Old transfers are done */ + + priv->msgv = msgs; + priv->msgc = count; + + /* Reset I2C trace logic */ + + stm32_i2c_tracereset(priv); + + /* Set I2C clock frequency (on change it toggles I2C_CR1_PE !) + * REVISIT: Note that the frequency is set only on the first message. + * This could be extended to support different transfer frequencies for + * each message segment. + */ + + stm32_i2c_setclock(priv, msgs->frequency); + + /* Trigger start condition, then the process moves into the ISR. I2C + * interrupts will be enabled within stm32_i2c_waitdone(). + * + * Initialize current message length counter to zero. This is needed to + * process the first message(first priv->msgv entry) correctly. + */ + + priv->dcnt = -1; + priv->status = 0; + stm32_i2c_sendstart(priv); + + /* Wait for an ISR, if there was a timeout, fetch latest status to get + * the BUSY flag. + */ + + if (stm32_i2c_sem_waitdone(priv) < 0) + { + status = stm32_i2c_getstatus(priv); + ret = -ETIMEDOUT; + + i2cerr("ERROR: Timed out: CR1: 0x%04x status: 0x%08" PRIx32 "\n", + stm32_i2c_getreg(priv, STM32_I2C_CR1_OFFSET), status); + + /* "Note: When the STOP, START or PEC bit is set, the software must + * not perform any write access to I2C_CR1 before this bit is + * cleared by hardware. Otherwise there is a risk of setting a + * second STOP, START or PEC request." + */ + + stm32_i2c_clrstart(priv); + +#ifdef CONFIG_I2C_POLLED + /* When polling the i2c ISR it's not possible to determine when + * an address has been ACKed(i.e. the address is valid). + * + * The mechanism to deal a NACKed address is to wait for the I2C + * call to timeout(value defined in defconfig by one of the + * following: CONFIG_STM32_I2C_DYNTIMEO, CONFIG_STM32_I2CTIMEOSEC, + * CONFIG_STM32_I2CTIMEOMS, CONFIG_STM32_I2CTIMEOTICKS). + * + * To be safe in the case of a timeout/NACKed address a stop bit + * is set on the bus to clear it. In POLLED operation it's done + * stm32_i2c_transfer() after the call to stm32_i2c_sem_waitdone(). + * + * In ISR driven operation the stop bit in case of a NACKed address + * is set in the ISR itself. + * + * Note: this commentary is found in both places. + * + */ + + i2cinfo("Check if the address was valid\n"); + stm32_i2c_sendstop(priv); +#endif + /* Clear busy flag in case of timeout */ + + status = priv->status & 0xffff; + } + else + { + /* clear SR2 (BUSY flag) as we've done successfully */ + + status = priv->status & 0xffff; + } + + /* Check for error status conditions */ + + if ((status & I2C_SR1_ERRORMASK) != 0) + { + /* I2C_SR1_ERRORMASK is the 'OR' of the following individual bits: */ + + if (status & I2C_SR1_BERR) + { + /* Bus Error */ + + ret = -EIO; + } + else if (status & I2C_SR1_ARLO) + { + /* Arbitration Lost (master mode) */ + + ret = -EAGAIN; + } + else if (status & I2C_SR1_AF) + { + /* Acknowledge Failure */ + + ret = -ENXIO; + } + else if (status & I2C_SR1_OVR) + { + /* Overrun/Underrun */ + + ret = -EIO; + } + else if (status & I2C_SR1_PECERR) + { + /* PEC Error in reception */ + + ret = -EPROTO; + } + else if (status & I2C_SR1_TIMEOUT) + { + /* Timeout or Tlow Error */ + + ret = -ETIME; + } + + /* This is not an error and should never happen since SMBus is not + * enabled + */ + + else /* if (status & I2C_SR1_SMBALERT) */ + { + /* SMBus alert is an optional signal with an interrupt line for + * devices that want to trade their ability to master for a pin. + */ + + ret = -EINTR; + } + } + + /* This is not an error, but should not happen. The BUSY signal can hang, + * however, if there are unhealthy devices on the bus that need to be + * reset. + * NOTE: We will only see this busy indication if stm32_i2c_sem_waitdone() + * fails above; Otherwise it is cleared. + */ + + else if ((status & (I2C_SR2_BUSY << 16)) != 0) + { + /* I2C Bus is for some reason busy */ + + ret = -EBUSY; + } + + /* Dump the trace result */ + + stm32_i2c_tracedump(priv); + +#ifdef I2C1_FSMC_CONFLICT + /* Wait for any STOP in progress. NOTE: If we have to disable the FSMC + * then we cannot do this at the top of the loop, unfortunately. The STOP + * will not complete normally if the FSMC is enabled. + */ + + stm32_i2c_sem_waitstop(priv); + + /* Re-enable the FSMC */ + + stm32_i2c_enablefsmc(ahbenr); +#endif + + nxmutex_unlock(&priv->lock); + return ret; +} + +/**************************************************************************** + * Name: stm32_i2c_reset + * + * Description: + * Perform an I2C bus reset in an attempt to break loose stuck I2C devices. + * + * Input Parameters: + * dev - Device-specific state data + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +#ifdef CONFIG_I2C_RESET +static int stm32_i2c_reset(struct i2c_master_s *dev) +{ + struct stm32_i2c_priv_s *priv = (struct stm32_i2c_priv_s *)dev; + unsigned int clock_count; + unsigned int stretch_count; + uint32_t scl_gpio; + uint32_t sda_gpio; + uint32_t frequency; + int ret; + + DEBUGASSERT(dev); + + /* Our caller must own a ref */ + + DEBUGASSERT(priv->refs > 0); + + /* Lock out other clients */ + + ret = nxmutex_lock(&priv->lock); + if (ret < 0) + { + return ret; + } + + ret = -EIO; + + /* Save the current frequency */ + + frequency = priv->frequency; + + /* De-init the port */ + + stm32_i2c_deinit(priv); + + /* Use GPIO configuration to un-wedge the bus */ + + scl_gpio = MKI2C_OUTPUT(priv->config->scl_pin); + sda_gpio = MKI2C_OUTPUT(priv->config->sda_pin); + + /* Let SDA go high */ + + stm32_gpiowrite(sda_gpio, 1); + + /* Clock the bus until any slaves currently driving it let it go. */ + + clock_count = 0; + while (!stm32_gpioread(sda_gpio)) + { + /* Give up if we have tried too hard */ + + if (clock_count++ > 10) + { + goto out; + } + + /* Sniff to make sure that clock stretching has finished. + * + * If the bus never relaxes, the reset has failed. + */ + + stretch_count = 0; + while (!stm32_gpioread(scl_gpio)) + { + /* Give up if we have tried too hard */ + + if (stretch_count++ > 10) + { + goto out; + } + + up_udelay(10); + } + + /* Drive SCL low */ + + stm32_gpiowrite(scl_gpio, 0); + up_udelay(10); + + /* Drive SCL high again */ + + stm32_gpiowrite(scl_gpio, 1); + up_udelay(10); + } + + /* Generate a start followed by a stop to reset slave + * state machines. + */ + + stm32_gpiowrite(sda_gpio, 0); + up_udelay(10); + stm32_gpiowrite(scl_gpio, 0); + up_udelay(10); + stm32_gpiowrite(scl_gpio, 1); + up_udelay(10); + stm32_gpiowrite(sda_gpio, 1); + up_udelay(10); + + /* Revert the GPIO configuration. */ + + stm32_unconfiggpio(sda_gpio); + stm32_unconfiggpio(scl_gpio); + + /* Re-init the port */ + + stm32_i2c_init(priv); + + /* Restore the frequency */ + + stm32_i2c_setclock(priv, frequency); + ret = OK; + +out: + + /* Release the port for reuse by other clients */ + + nxmutex_unlock(&priv->lock); + return ret; +} +#endif /* CONFIG_I2C_RESET */ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_i2cbus_initialize + * + * Description: + * Initialize one I2C bus + * + ****************************************************************************/ + +struct i2c_master_s *stm32_i2cbus_initialize(int port) +{ + struct stm32_i2c_priv_s *priv = NULL; + + /* Get I2C private structure */ + + switch (port) + { +#ifdef CONFIG_STM32_I2C1 + case 1: + priv = (struct stm32_i2c_priv_s *)&stm32_i2c1_priv; + break; +#endif +#ifdef CONFIG_STM32_I2C2 + case 2: + priv = (struct stm32_i2c_priv_s *)&stm32_i2c2_priv; + break; +#endif +#ifdef CONFIG_STM32_I2C3 + case 3: + priv = (struct stm32_i2c_priv_s *)&stm32_i2c3_priv; + break; +#endif + default: + return NULL; + } + + /* Initialize private data for the first time, increment reference count, + * power-up hardware and configure GPIOs. + */ + + nxmutex_lock(&priv->lock); + if (priv->refs++ == 0) + { + stm32_i2c_init(priv); + } + + nxmutex_unlock(&priv->lock); + return (struct i2c_master_s *)priv; +} + +/**************************************************************************** + * Name: stm32_i2cbus_uninitialize + * + * Description: + * Uninitialize an I2C bus + * + ****************************************************************************/ + +int stm32_i2cbus_uninitialize(struct i2c_master_s *dev) +{ + struct stm32_i2c_priv_s *priv = (struct stm32_i2c_priv_s *)dev; + + DEBUGASSERT(dev); + + /* Decrement reference count and check for underflow */ + + if (priv->refs == 0) + { + return ERROR; + } + + nxmutex_lock(&priv->lock); + if (--priv->refs) + { + nxmutex_unlock(&priv->lock); + return OK; + } + + /* Disable power and other HW resource (GPIO's) */ + + stm32_i2c_deinit(priv); + nxmutex_unlock(&priv->lock); + + return OK; +} + +#endif /* CONFIG_STM32_HAVE_IP_I2C_M3M4_V1 */ +#endif /* CONFIG_STM32_I2C1 || CONFIG_STM32_I2C2 || CONFIG_STM32_I2C3 */ diff --git a/arch/arm/src/common/stm32/stm32_i2c_m3m4_v1_f40xxx.c b/arch/arm/src/common/stm32/stm32_i2c_m3m4_v1_f40xxx.c new file mode 100644 index 0000000000000..9ed73e228db8f --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_i2c_m3m4_v1_f40xxx.c @@ -0,0 +1,2694 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_i2c_m3m4_v1_f40xxx.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* Supports: + * - Master operation, 100 kHz (standard) and 400 kHz (full speed) + * - Multiple instances (shared bus) + * - Interrupt based operation + * + * Structure naming: + * - Device: structure as defined by the nuttx/i2c/i2c.h + * - Instance: represents each individual access to the I2C driver, obtained + * by the i2c_init(); it extends the Device structure from the + * nuttx/i2c/i2c.h; + * Instance points to OPS, to common I2C Hardware private data and + * contains its own private data, as frequency, address, mode of + * operation (in the future) + * - Private: Private data of an I2C Hardware + * + * TODO + * - Check for all possible deadlocks (as BUSY='1' I2C needs to be reset in + * HW using the I2C_CR1_SWRST) + * - SMBus support (hardware layer timings are already supported) and add + * SMBA gpio pin + * - Slave support with multiple addresses (on multiple instances): + * - 2 x 7-bit address or + * - 1 x 10 bit addresses + 1 x 7 bit address (?) + * - plus the broadcast address (general call) + * - Multi-master support + * - Be ready for IPMI + */ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#include + +#include "arm_internal.h" +#include "stm32_rcc.h" +#include "stm32_i2c.h" +#include "stm32_waste.h" +#include "stm32_dma.h" + +/* At least one I2C peripheral must be enabled */ + +#if defined(CONFIG_STM32_I2C1) || defined(CONFIG_STM32_I2C2) || \ + defined(CONFIG_STM32_I2C3) + +/* This implementation is for the STM32 F1, F2, and F4 only. + * Experimentally enabled for STM32L15XX. + */ + +#if defined(CONFIG_STM32_STM32L15XX) || defined(CONFIG_STM32_STM32F10XX) || \ + defined(CONFIG_STM32_HAVE_IP_DMA_V2) + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#if STM32_PCLK1_FREQUENCY < 4000000 +# warning STM32_I2C: Peripheral clock must be at least 4 MHz to support 400 kHz operation. +#endif + +#if STM32_PCLK1_FREQUENCY < 2000000 +# error STM32_I2C: Peripheral clock must be at least 2 MHz to support 100 kHz operation. +#endif + +/* Configuration ************************************************************/ + +/* CONFIG_I2C_POLLED may be set so that I2C interrupts will not be used. + * Instead, CPU-intensive polling will be used. + */ + +/* Interrupt wait timeout in seconds and milliseconds */ + +#if !defined(CONFIG_STM32_I2CTIMEOSEC) && !defined(CONFIG_STM32_I2CTIMEOMS) +# define CONFIG_STM32_I2CTIMEOSEC 0 +# define CONFIG_STM32_I2CTIMEOMS 500 /* Default is 500 milliseconds */ +#elif !defined(CONFIG_STM32_I2CTIMEOSEC) +# define CONFIG_STM32_I2CTIMEOSEC 0 /* User provided milliseconds */ +#elif !defined(CONFIG_STM32_I2CTIMEOMS) +# define CONFIG_STM32_I2CTIMEOMS 0 /* User provided seconds */ +#endif + +/* Interrupt wait time timeout in system timer ticks */ + +#ifndef CONFIG_STM32_I2CTIMEOTICKS +# define CONFIG_STM32_I2CTIMEOTICKS \ + (SEC2TICK(CONFIG_STM32_I2CTIMEOSEC) + MSEC2TICK(CONFIG_STM32_I2CTIMEOMS)) +#endif + +#ifndef CONFIG_STM32_I2C_DYNTIMEO_STARTSTOP +# define CONFIG_STM32_I2C_DYNTIMEO_STARTSTOP TICK2USEC(CONFIG_STM32_I2CTIMEOTICKS) +#endif + +/* On the STM32F103ZE, there is an internal conflict between I2C1 and FSMC. + * In that case, it is necessary to disable FSMC before each I2C1 access and + * re-enable FSMC when the I2C access completes. + */ + +#undef I2C1_FSMC_CONFLICT +#if defined(CONFIG_STM32_STM32F10XX) && defined(CONFIG_STM32_FSMC) && defined(CONFIG_STM32_I2C1) +# define I2C1_FSMC_CONFLICT +#endif + +/* Macros to convert a I2C pin to a GPIO output */ + +#if defined(CONFIG_STM32_STM32L15XX) +# define I2C_OUTPUT (GPIO_OUTPUT | GPIO_OUTPUT_SET | GPIO_OPENDRAIN | \ + GPIO_SPEED_40MHz) +#elif defined(CONFIG_STM32_STM32F10XX) +# define I2C_OUTPUT (GPIO_OUTPUT | GPIO_OUTPUT_SET | GPIO_CNF_OUTOD | \ + GPIO_MODE_50MHz) +#elif defined(CONFIG_STM32_HAVE_IP_DMA_V2) +# define I2C_OUTPUT (GPIO_OUTPUT | GPIO_FLOAT | GPIO_OPENDRAIN |\ + GPIO_SPEED_50MHz | GPIO_OUTPUT_SET) +#endif + +#define MKI2C_OUTPUT(p) (((p) & (GPIO_PORT_MASK | GPIO_PIN_MASK)) | I2C_OUTPUT) + +/* I2C DMA priority */ + +#ifdef CONFIG_STM32_I2C_DMA + +# if defined(CONFIG_I2C_DMAPRIO) +# if (CONFIG_I2C_DMAPRIO & ~DMA_SCR_PL_MASK) != 0 +# error "Illegal value for CONFIG_I2C_DMAPRIO" +# endif +# define I2C_DMA_PRIO CONFIG_I2C_DMAPRIO +# else +# define I2C_DMA_PRIO DMA_SCR_PRIMED +# endif + +#endif + +/* Debug ********************************************************************/ + +/* I2C event trace logic. NOTE: trace uses the internal, non-standard, + * low-level debug interface syslog() but does not require that any other + * debug is enabled. + */ + +#ifndef CONFIG_I2C_TRACE +# define stm32_i2c_tracereset(p) +# define stm32_i2c_tracenew(p,s) +# define stm32_i2c_traceevent(p,e,a) +# define stm32_i2c_tracedump(p) +#endif + +#ifndef CONFIG_I2C_NTRACE +# define CONFIG_I2C_NTRACE 32 +#endif + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/* Interrupt state */ + +enum stm32_intstate_e +{ + INTSTATE_IDLE = 0, /* No I2C activity */ + INTSTATE_WAITING, /* Waiting for completion of interrupt activity */ + INTSTATE_DONE, /* Interrupt activity complete */ +}; + +/* Trace events */ + +enum stm32_trace_e +{ + I2CEVENT_NONE = 0, + I2CEVENT_STATE_ERROR, + I2CEVENT_ISR_SHUTDOWN, + I2CEVENT_ISR_CALL, + I2CEVENT_ISR_EMPTY_CALL, + I2CEVENT_MSG_HANDLING, + I2CEVENT_POLL_NOT_READY, + I2CEVENT_EMPTY_MSG, + I2CEVENT_START, + I2CEVENT_SENDADDR, + I2CEVENT_ADDRESS_ACKED, + I2CEVENT_ADDRESS_NACKED, + I2CEVENT_NACK, + I2CEVENT_READ, + I2CEVENT_READ_ERROR, + I2CEVENT_ADDRESS_ACKED_READ_1, + I2CEVENT_ADDRESS_ACKED_READ_2, + I2CEVENT_WRITE_TO_DR, + I2CEVENT_WRITE_STOP, + I2CEVENT_WRITE_RESTART, + I2CEVENT_WRITE_NO_RESTART, + I2CEVENT_WRITE_ERROR, + I2CEVENT_WRITE_FLAG_ERROR, + I2CEVENT_TC_RESTART, + I2CEVENT_TC_NO_RESTART, + I2CEVENT_ERROR +}; + +/* Trace data */ + +struct stm32_trace_s +{ + uint32_t status; /* I2C 32-bit SR2|SR1 status */ + uint32_t count; /* Interrupt count when status change */ + enum stm32_intstate_e event; /* Last event that occurred with this status */ + uint32_t parm; /* Parameter associated with the event */ + clock_t time; /* First of event or first status */ +}; + +/* I2C Device hardware configuration */ + +struct stm32_i2c_config_s +{ + uint32_t base; /* I2C base address */ + uint32_t clk_bit; /* Clock enable bit */ + uint32_t reset_bit; /* Reset bit */ + uint32_t scl_pin; /* GPIO configuration for SCL as SCL */ + uint32_t sda_pin; /* GPIO configuration for SDA as SDA */ +#ifndef CONFIG_I2C_POLLED + uint32_t ev_irq; /* Event IRQ */ + uint32_t er_irq; /* Error IRQ */ +#endif +}; + +/* I2C Device Private Data */ + +struct stm32_i2c_priv_s +{ + /* Standard I2C operations */ + + const struct i2c_ops_s *ops; + + /* Port configuration */ + + const struct stm32_i2c_config_s *config; + + int refs; /* Reference count */ + mutex_t lock; /* Mutual exclusion mutex */ +#ifndef CONFIG_I2C_POLLED + sem_t sem_isr; /* Interrupt wait semaphore */ +#endif + volatile uint8_t intstate; /* Interrupt handshake (see enum stm32_intstate_e) */ + + uint8_t msgc; /* Message count */ + struct i2c_msg_s *msgv; /* Message list */ + uint8_t *ptr; /* Current message buffer */ + uint32_t frequency; /* Current I2C frequency */ + volatile int dcnt; /* Current message length */ + uint16_t flags; /* Current message flags */ + bool check_addr_ack; /* Flag to signal if on next interrupt address has ACKed */ + + /* I2C trace support */ + +#ifdef CONFIG_I2C_TRACE + int tndx; /* Trace array index */ + clock_t start_time; /* Time when the trace was started */ + + /* The actual trace data */ + + struct stm32_trace_s trace[CONFIG_I2C_NTRACE]; +#endif + + uint32_t status; /* End of transfer SR2|SR1 status */ + + /* I2C DMA support */ + +#ifdef CONFIG_STM32_I2C_DMA + DMA_HANDLE txdma; /* TX DMA handle */ + DMA_HANDLE rxdma; /* RX DMA handle */ + uint8_t txch; /* TX DMA channel */ + uint8_t rxch; /* RX DMA channel */ +#endif +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +static inline uint16_t stm32_i2c_getreg(struct stm32_i2c_priv_s *priv, + uint8_t offset); +static inline void stm32_i2c_putreg(struct stm32_i2c_priv_s *priv, + uint8_t offset, uint16_t value); +static inline void stm32_i2c_modifyreg(struct stm32_i2c_priv_s *priv, + uint8_t offset, uint16_t clearbits, + uint16_t setbits); + +#ifdef CONFIG_STM32_I2C_DYNTIMEO +static uint32_t stm32_i2c_toticks(int msgc, struct i2c_msg_s *msgs); +#endif /* CONFIG_STM32_I2C_DYNTIMEO */ + +static inline int stm32_i2c_sem_waitdone(struct stm32_i2c_priv_s *priv); +static inline void stm32_i2c_sem_waitstop(struct stm32_i2c_priv_s *priv); + +#ifdef CONFIG_I2C_TRACE +static void stm32_i2c_tracereset(struct stm32_i2c_priv_s *priv); +static void stm32_i2c_tracenew(struct stm32_i2c_priv_s *priv, + uint32_t status); +static void stm32_i2c_traceevent(struct stm32_i2c_priv_s *priv, + enum stm32_trace_e event, uint32_t parm); +static void stm32_i2c_tracedump(struct stm32_i2c_priv_s *priv); +#endif /* CONFIG_I2C_TRACE */ + +static void stm32_i2c_setclock(struct stm32_i2c_priv_s *priv, + uint32_t frequency); +static inline void stm32_i2c_sendstart(struct stm32_i2c_priv_s *priv); +static inline void stm32_i2c_clrstart(struct stm32_i2c_priv_s *priv); +static inline void stm32_i2c_sendstop(struct stm32_i2c_priv_s *priv); +static inline +uint32_t stm32_i2c_getstatus(struct stm32_i2c_priv_s *priv); + +#ifdef I2C1_FSMC_CONFLICT +static inline +uint32_t stm32_i2c_disablefsmc(struct stm32_i2c_priv_s *priv); +static inline void stm32_i2c_enablefsmc(uint32_t ahbenr); +#endif /* I2C1_FSMC_CONFLICT */ + +static int stm32_i2c_isr_process(struct stm32_i2c_priv_s *priv); + +#ifndef CONFIG_I2C_POLLED +static int stm32_i2c_isr(int irq, void *context, void *arg); +#endif /* !CONFIG_I2C_POLLED */ + +static int stm32_i2c_init(struct stm32_i2c_priv_s *priv); +static int stm32_i2c_deinit(struct stm32_i2c_priv_s *priv); +static int stm32_i2c_transfer(struct i2c_master_s *dev, + struct i2c_msg_s *msgs, int count); +#ifdef CONFIG_I2C_RESET +static int stm32_i2c_reset(struct i2c_master_s *dev); +#endif + +/* DMA support */ + +#ifdef CONFIG_STM32_I2C_DMA +static void stm32_i2c_dmarxcallback(DMA_HANDLE handle, + uint8_t status, void *arg); +static void stm32_i2c_dmatxcallback(DMA_HANDLE handle, + uint8_t status, void *arg); +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* I2C interface */ + +static const struct i2c_ops_s stm32_i2c_ops = +{ + .transfer = stm32_i2c_transfer +#ifdef CONFIG_I2C_RESET + , .reset = stm32_i2c_reset +#endif +}; + +/* I2C device structures */ + +#ifdef CONFIG_STM32_I2C1 +static const struct stm32_i2c_config_s stm32_i2c1_config = +{ + .base = STM32_I2C1_BASE, + .clk_bit = RCC_APB1ENR_I2C1EN, + .reset_bit = RCC_APB1RSTR_I2C1RST, + .scl_pin = GPIO_I2C1_SCL, + .sda_pin = GPIO_I2C1_SDA, +#ifndef CONFIG_I2C_POLLED + .ev_irq = STM32_IRQ_I2C1EV, + .er_irq = STM32_IRQ_I2C1ER +#endif +}; + +static struct stm32_i2c_priv_s stm32_i2c1_priv = +{ + .ops = &stm32_i2c_ops, + .config = &stm32_i2c1_config, + .refs = 0, + .lock = NXMUTEX_INITIALIZER, +#ifndef CONFIG_I2C_POLLED + .sem_isr = SEM_INITIALIZER(0), +#endif + .intstate = INTSTATE_IDLE, + .msgc = 0, + .msgv = NULL, + .ptr = NULL, + .dcnt = 0, + .flags = 0, + .status = 0, +#ifdef CONFIG_STM32_I2C_DMA +# ifndef CONFIG_STM32_DMA1 +# error "I2C1 enabled with DMA but corresponding DMA controller 1 is not enabled!" +# endif + /* TODO: ch for i2c 1 and 2 could be *X_2 based on stream priority */ + + .rxch = DMAMAP_I2C1_RX, + .txch = DMAMAP_I2C1_TX, +#endif +}; +#endif + +#ifdef CONFIG_STM32_I2C2 +static const struct stm32_i2c_config_s stm32_i2c2_config = +{ + .base = STM32_I2C2_BASE, + .clk_bit = RCC_APB1ENR_I2C2EN, + .reset_bit = RCC_APB1RSTR_I2C2RST, + .scl_pin = GPIO_I2C2_SCL, + .sda_pin = GPIO_I2C2_SDA, +# ifndef CONFIG_I2C_POLLED + .ev_irq = STM32_IRQ_I2C2EV, + .er_irq = STM32_IRQ_I2C2ER +# endif +}; + +static struct stm32_i2c_priv_s stm32_i2c2_priv = +{ + .ops = &stm32_i2c_ops, + .config = &stm32_i2c2_config, + .refs = 0, + .lock = NXMUTEX_INITIALIZER, +# ifndef CONFIG_I2C_POLLED + .sem_isr = SEM_INITIALIZER(0), +# endif + .intstate = INTSTATE_IDLE, + .msgc = 0, + .msgv = NULL, + .ptr = NULL, + .dcnt = 0, + .flags = 0, + .status = 0, +# ifdef CONFIG_STM32_I2C_DMA +# ifndef CONFIG_STM32_DMA1 +# error "I2C2 enabled with DMA but corresponding DMA controller 1 is not enabled!" +# endif + .rxch = DMAMAP_I2C2_RX, + .txch = DMAMAP_I2C2_TX, +# endif +}; +#endif + +#ifdef CONFIG_STM32_I2C3 +static const struct stm32_i2c_config_s stm32_i2c3_config = +{ + .base = STM32_I2C3_BASE, + .clk_bit = RCC_APB1ENR_I2C3EN, + .reset_bit = RCC_APB1RSTR_I2C3RST, + .scl_pin = GPIO_I2C3_SCL, + .sda_pin = GPIO_I2C3_SDA, +# ifndef CONFIG_I2C_POLLED + .ev_irq = STM32_IRQ_I2C3EV, + .er_irq = STM32_IRQ_I2C3ER +# endif +}; + +static struct stm32_i2c_priv_s stm32_i2c3_priv = +{ + .ops = &stm32_i2c_ops, + .config = &stm32_i2c3_config, + .refs = 0, + .lock = NXMUTEX_INITIALIZER, +# ifndef CONFIG_I2C_POLLED + .sem_isr = SEM_INITIALIZER(0), +# endif + .intstate = INTSTATE_IDLE, + .msgc = 0, + .msgv = NULL, + .ptr = NULL, + .dcnt = 0, + .flags = 0, + .status = 0, +# ifdef CONFIG_STM32_I2C_DMA +# ifndef CONFIG_STM32_DMA1 +# error "I2C3 enabled with DMA but corresponding DMA controller 1 is not enabled!" +# endif + .rxch = DMAMAP_I2C3_RX, + .txch = DMAMAP_I2C3_TX, +# endif +}; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_i2c_getreg + * + * Description: + * Get a 16-bit register value by offset + * + ****************************************************************************/ + +static inline uint16_t stm32_i2c_getreg(struct stm32_i2c_priv_s *priv, + uint8_t offset) +{ + return getreg16(priv->config->base + offset); +} + +/**************************************************************************** + * Name: stm32_i2c_putreg + * + * Description: + * Put a 16-bit register value by offset + * + ****************************************************************************/ + +static inline void stm32_i2c_putreg(struct stm32_i2c_priv_s *priv, + uint8_t offset, uint16_t value) +{ + putreg16(value, priv->config->base + offset); +} + +/**************************************************************************** + * Name: stm32_i2c_modifyreg + * + * Description: + * Modify a 16-bit register value by offset + * + ****************************************************************************/ + +static inline void stm32_i2c_modifyreg(struct stm32_i2c_priv_s *priv, + uint8_t offset, uint16_t clearbits, + uint16_t setbits) +{ + modifyreg16(priv->config->base + offset, clearbits, setbits); +} + +/**************************************************************************** + * Name: stm32_i2c_toticks + * + * Description: + * Return a micro-second delay based on the number of bytes left to be + * processed. + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_I2C_DYNTIMEO +static uint32_t stm32_i2c_toticks(int msgc, struct i2c_msg_s *msgs) +{ + size_t bytecount = 0; + int i; + + /* Count the number of bytes left to process */ + + for (i = 0; i < msgc; i++) + { + bytecount += msgs[i].length; + } + + /* Then return a number of microseconds based on a user provided scaling + * factor. + */ + + return USEC2TICK(CONFIG_STM32_I2C_DYNTIMEO_USECPERBYTE * bytecount); +} +#endif + +/**************************************************************************** + * Name: stm32_i2c_sem_waitdone + * + * Description: + * Wait for a transfer to complete + * + ****************************************************************************/ + +#ifndef CONFIG_I2C_POLLED +static inline int stm32_i2c_sem_waitdone(struct stm32_i2c_priv_s *priv) +{ + irqstate_t flags; + uint32_t regval; + int ret; + + flags = enter_critical_section(); + + /* Enable I2C interrupts */ + + regval = stm32_i2c_getreg(priv, STM32_I2C_CR2_OFFSET); + regval |= (I2C_CR2_ITERREN | I2C_CR2_ITEVFEN); + stm32_i2c_putreg(priv, STM32_I2C_CR2_OFFSET, regval); + + /* Signal the interrupt handler that we are waiting. NOTE: Interrupts + * are currently disabled but will be temporarily re-enabled below when + * nxsem_tickwait_uninterruptible() sleeps. + */ + + priv->intstate = INTSTATE_WAITING; + do + { + /* Wait until either the transfer is complete or the timeout expires */ + +#ifdef CONFIG_STM32_I2C_DYNTIMEO + ret = nxsem_tickwait_uninterruptible(&priv->sem_isr, + stm32_i2c_toticks(priv->msgc, priv->msgv)); +#else + ret = nxsem_tickwait_uninterruptible(&priv->sem_isr, + CONFIG_STM32_I2CTIMEOTICKS); +#endif + if (ret < 0) + { + /* Break out of the loop on irrecoverable errors. This would + * include timeouts and mystery errors reported by + * nxsem_tickwait_uninterruptible. + */ + + break; + } + } + + /* Loop until the interrupt level transfer is complete. */ + + while (priv->intstate != INTSTATE_DONE); + + /* Set the interrupt state back to IDLE */ + + priv->intstate = INTSTATE_IDLE; + + /* Disable I2C interrupts */ + + regval = stm32_i2c_getreg(priv, STM32_I2C_CR2_OFFSET); + regval &= ~I2C_CR2_ALLINTS; + stm32_i2c_putreg(priv, STM32_I2C_CR2_OFFSET, regval); + + leave_critical_section(flags); + return ret; +} +#else +static inline int stm32_i2c_sem_waitdone(struct stm32_i2c_priv_s *priv) +{ + clock_t timeout; + clock_t start; + clock_t elapsed; + int ret; + + /* Get the timeout value */ + +#ifdef CONFIG_STM32_I2C_DYNTIMEO + timeout = stm32_i2c_toticks(priv->msgc, priv->msgv); +#else + timeout = CONFIG_STM32_I2CTIMEOTICKS; +#endif + + /* Signal the interrupt handler that we are waiting. NOTE: Interrupts + * are currently disabled but will be temporarily re-enabled below when + * nxsem_tickwait_uninterruptible() sleeps. + */ + + priv->intstate = INTSTATE_WAITING; + start = clock_systime_ticks(); + + do + { + /* Calculate the elapsed time */ + + elapsed = clock_systime_ticks() - start; + + /* Poll by simply calling the timer interrupt handler until it + * reports that it is done. + */ + + stm32_i2c_isr_process(priv); + } + + /* Loop until the transfer is complete. */ + + while (priv->intstate != INTSTATE_DONE && elapsed < timeout); + + i2cinfo("intstate: %d elapsed: %ld threshold: %ld status: %08" PRIx32 "\n", + priv->intstate, (long)elapsed, (long)timeout, priv->status); + + /* Set the interrupt state back to IDLE */ + + ret = priv->intstate == INTSTATE_DONE ? OK : -ETIMEDOUT; + priv->intstate = INTSTATE_IDLE; + return ret; +} +#endif + +/**************************************************************************** + * Name: stm32_i2c_sem_waitstop + * + * Description: + * Wait for a STOP to complete + * + ****************************************************************************/ + +static inline void stm32_i2c_sem_waitstop(struct stm32_i2c_priv_s *priv) +{ + clock_t start; + clock_t elapsed; + clock_t timeout; + uint32_t cr1; + uint32_t sr1; + + /* Select a timeout */ + +#ifdef CONFIG_STM32_I2C_DYNTIMEO + timeout = USEC2TICK(CONFIG_STM32_I2C_DYNTIMEO_STARTSTOP); +#else + timeout = CONFIG_STM32_I2CTIMEOTICKS; +#endif + + /* Wait as stop might still be in progress; but stop might also + * be set because of a timeout error: "The [STOP] bit is set and + * cleared by software, cleared by hardware when a Stop condition is + * detected, set by hardware when a timeout error is detected." + */ + + start = clock_systime_ticks(); + do + { + /* Calculate the elapsed time */ + + elapsed = clock_systime_ticks() - start; + + /* Check for STOP condition */ + + cr1 = stm32_i2c_getreg(priv, STM32_I2C_CR1_OFFSET); + if ((cr1 & I2C_CR1_STOP) == 0) + { + return; + } + + /* Check for timeout error */ + + sr1 = stm32_i2c_getreg(priv, STM32_I2C_SR1_OFFSET); + if ((sr1 & I2C_SR1_TIMEOUT) != 0) + { + return; + } + } + + /* Loop until the stop is complete or a timeout occurs. */ + + while (elapsed < timeout); + + /* If we get here then a timeout occurred with the STOP condition + * still pending. + */ + + i2cinfo("Timeout with CR1: %04" PRIx32 " SR1: %04" PRIx32 "\n", cr1, sr1); +} + +/**************************************************************************** + * Name: stm32_i2c_trace* + * + * Description: + * I2C trace instrumentation + * + ****************************************************************************/ + +#ifdef CONFIG_I2C_TRACE +static void stm32_i2c_traceclear(struct stm32_i2c_priv_s *priv) +{ + struct stm32_trace_s *trace = &priv->trace[priv->tndx]; + + trace->status = 0; /* I2C 32-bit SR2|SR1 status */ + trace->count = 0; /* Interrupt count when status change */ + trace->event = I2CEVENT_NONE; /* Last event that occurred with this status */ + trace->parm = 0; /* Parameter associated with the event */ + trace->time = 0; /* Time of first status or event */ +} + +static void stm32_i2c_tracereset(struct stm32_i2c_priv_s *priv) +{ + /* Reset the trace info for a new data collection */ + + priv->tndx = 0; + priv->start_time = clock_systime_ticks(); + stm32_i2c_traceclear(priv); +} + +static void stm32_i2c_tracenew(struct stm32_i2c_priv_s *priv, + uint32_t status) +{ + struct stm32_trace_s *trace = &priv->trace[priv->tndx]; + + /* Is the current entry uninitialized? Has the status changed? */ + + if (trace->count == 0 || status != trace->status) + { + /* Yes.. Was it the status changed? */ + + if (trace->count != 0) + { + /* Yes.. bump up the trace index + * (unless we are out of trace entries) + */ + + if (priv->tndx >= (CONFIG_I2C_NTRACE - 1)) + { + i2cerr("ERROR: Trace table overflow\n"); + return; + } + + priv->tndx++; + trace = &priv->trace[priv->tndx]; + } + + /* Initialize the new trace entry */ + + stm32_i2c_traceclear(priv); + trace->status = status; + trace->count = 1; + trace->time = clock_systime_ticks(); + } + else + { + /* Just increment the count of times that we have seen this status */ + + trace->count++; + } +} + +static void stm32_i2c_traceevent(struct stm32_i2c_priv_s *priv, + enum stm32_trace_e event, uint32_t parm) +{ + struct stm32_trace_s *trace; + + if (event != I2CEVENT_NONE) + { + trace = &priv->trace[priv->tndx]; + + /* Initialize the new trace entry */ + + trace->event = event; + trace->parm = parm; + + /* Bump up the trace index (unless we are out of trace entries) */ + + if (priv->tndx >= (CONFIG_I2C_NTRACE - 1)) + { + i2cerr("ERROR: Trace table overflow\n"); + return; + } + + priv->tndx++; + stm32_i2c_traceclear(priv); + } +} + +static void stm32_i2c_tracedump(struct stm32_i2c_priv_s *priv) +{ + struct stm32_trace_s *trace; + int i; + + syslog(LOG_DEBUG, "Elapsed time: %ld\n", + (long)(clock_systime_ticks() - priv->start_time)); + + for (i = 0; i < priv->tndx; i++) + { + trace = &priv->trace[i]; + syslog(LOG_DEBUG, + "%2d. STATUS: %08" PRIx32 " COUNT: %3d EVENT: %2d" + " PARM: %08" PRIx32 " TIME: %d\n", + i + 1, trace->status, trace->count, trace->event, trace->parm, + (int)(trace->time - priv->start_time)); + } +} +#endif /* CONFIG_I2C_TRACE */ + +/**************************************************************************** + * Name: stm32_i2c_setclock + * + * Description: + * Set the I2C clock + * + ****************************************************************************/ + +static void stm32_i2c_setclock(struct stm32_i2c_priv_s *priv, + uint32_t frequency) +{ + uint16_t cr1; + uint16_t ccr; + uint16_t trise; + uint16_t freqmhz; + uint16_t speed; + + /* Has the I2C bus frequency changed? */ + + if (frequency != priv->frequency) + { + /* Disable the selected I2C peripheral to configure TRISE */ + + cr1 = stm32_i2c_getreg(priv, STM32_I2C_CR1_OFFSET); + stm32_i2c_putreg(priv, STM32_I2C_CR1_OFFSET, cr1 & ~I2C_CR1_PE); + + /* Update timing and control registers */ + + freqmhz = (uint16_t)(STM32_PCLK1_FREQUENCY / 1000000); + ccr = 0; + + /* Configure speed in standard mode */ + + if (frequency <= 100000) + { + /* Standard mode speed calculation */ + + speed = (uint16_t)(STM32_PCLK1_FREQUENCY / (frequency << 1)); + + /* The CCR fault must be >= 4 */ + + if (speed < 4) + { + /* Set the minimum allowed value */ + + speed = 4; + } + + ccr |= speed; + + /* Set Maximum Rise Time for standard mode */ + + trise = freqmhz + 1; + } + + /* Configure speed in fast mode */ + + else /* (frequency <= 400000) */ + { + /* Fast mode speed calculation with Tlow/Thigh = 16/9 */ + +#ifdef CONFIG_STM32_I2C_DUTY16_9 + speed = (uint16_t)(STM32_PCLK1_FREQUENCY / (frequency * 25)); + + /* Set DUTY and fast speed bits */ + + ccr |= (I2C_CCR_DUTY | I2C_CCR_FS); +#else + /* Fast mode speed calculation with Tlow/Thigh = 2 */ + + speed = (uint16_t)(STM32_PCLK1_FREQUENCY / (frequency * 3)); + + /* Set fast speed bit */ + + ccr |= I2C_CCR_FS; +#endif + + /* Verify that the CCR speed value is nonzero */ + + if (speed < 1) + { + /* Set the minimum allowed value */ + + speed = 1; + } + + ccr |= speed; + + /* Set Maximum Rise Time for fast mode */ + + trise = (uint16_t)(((freqmhz * 300) / 1000) + 1); + } + + /* Write the new values of the CCR and TRISE registers */ + + stm32_i2c_putreg(priv, STM32_I2C_CCR_OFFSET, ccr); + stm32_i2c_putreg(priv, STM32_I2C_TRISE_OFFSET, trise); + + /* Bit 14 of OAR1 must be configured and kept at 1 */ + + stm32_i2c_putreg(priv, STM32_I2C_OAR1_OFFSET, I2C_OAR1_ONE); + + /* Re-enable the peripheral (or not) */ + + stm32_i2c_putreg(priv, STM32_I2C_CR1_OFFSET, cr1); + + /* Save the new I2C frequency */ + + priv->frequency = frequency; + } +} + +/**************************************************************************** + * Name: stm32_i2c_sendstart + * + * Description: + * Send the START conditions/force Master mode + * + ****************************************************************************/ + +static inline void stm32_i2c_sendstart(struct stm32_i2c_priv_s *priv) +{ + /* Disable ACK on receive by default and generate START */ + + stm32_i2c_modifyreg(priv, + STM32_I2C_CR1_OFFSET, I2C_CR1_ACK, I2C_CR1_START); +} + +/**************************************************************************** + * Name: stm32_i2c_clrstart + * + * Description: + * Clear the STOP, START or PEC condition on certain error recovery steps. + * + ****************************************************************************/ + +static inline void stm32_i2c_clrstart(struct stm32_i2c_priv_s *priv) +{ + /* "Note: When the STOP, START or PEC bit is set, the software must + * not perform any write access to I2C_CR1 before this bit is + * cleared by hardware. Otherwise there is a risk of setting a + * second STOP, START or PEC request." + * + * "The [STOP] bit is set and cleared by software, cleared by hardware + * when a Stop condition is detected, set by hardware when a timeout + * error is detected. + * + * "This [START] bit is set and cleared by software and cleared by hardware + * when start is sent or PE=0." The bit must be cleared by software if + * the START is never sent. + * + * "This [PEC] bit is set and cleared by software, and cleared by hardware + * when PEC is transferred or by a START or Stop condition or when PE=0." + */ + + stm32_i2c_modifyreg(priv, STM32_I2C_CR1_OFFSET, + I2C_CR1_START | I2C_CR1_STOP | I2C_CR1_PEC, 0); +} + +/**************************************************************************** + * Name: stm32_i2c_sendstop + * + * Description: + * Send the STOP conditions + * + ****************************************************************************/ + +static inline void stm32_i2c_sendstop(struct stm32_i2c_priv_s *priv) +{ + stm32_i2c_modifyreg(priv, STM32_I2C_CR1_OFFSET, I2C_CR1_ACK, I2C_CR1_STOP); +} + +/**************************************************************************** + * Name: stm32_i2c_getstatus + * + * Description: + * Get 32-bit status (SR1 and SR2 combined) + * + ****************************************************************************/ + +static inline uint32_t stm32_i2c_getstatus(struct stm32_i2c_priv_s *priv) +{ + uint32_t status = stm32_i2c_getreg(priv, STM32_I2C_SR1_OFFSET); + status |= (stm32_i2c_getreg(priv, STM32_I2C_SR2_OFFSET) << 16); + return status; +} + +/**************************************************************************** + * Name: stm32_i2c_disablefsmc + * + * Description: + * FSMC must be disable while accessing I2C1 because it uses a common + * resource (LBAR) + * + * NOTE: + * This is an issue with the STM32F103ZE, but may not be an issue with other + * STM32s. You may need to experiment + * + ****************************************************************************/ + +#ifdef I2C1_FSMC_CONFLICT +static inline +uint32_t stm32_i2c_disablefsmc(struct stm32_i2c_priv_s *priv) +{ + uint32_t ret = 0; + uint32_t regval; + + /* Is this I2C1 */ + +#if defined(CONFIG_STM32_I2C2) || defined(CONFIG_STM32_I2C3) + if (priv->config->base == STM32_I2C1_BASE) +#endif + { + /* Disable FSMC unconditionally */ + + ret = getreg32(STM32_RCC_AHBENR); + regval = ret & ~RCC_AHBENR_FSMCEN; + putreg32(regval, STM32_RCC_AHBENR); + } + + return ret; +} + +/**************************************************************************** + * Name: stm32_i2c_enablefsmc + * + * Description: + * Re-enable the FSMC + * + ****************************************************************************/ + +static inline void stm32_i2c_enablefsmc(uint32_t ahbenr) +{ + uint32_t regval; + + /* Enable AHB clocking to the FSMC only if it was previously enabled. */ + + if ((ahbenr & RCC_AHBENR_FSMCEN) != 0) + { + regval = getreg32(STM32_RCC_AHBENR); + regval |= RCC_AHBENR_FSMCEN; + putreg32(regval, STM32_RCC_AHBENR); + } +} +#else +# define stm32_i2c_disablefsmc(priv) (0) +# define stm32_i2c_enablefsmc(ahbenr) +#endif /* I2C1_FSMC_CONFLICT */ + +/**************************************************************************** + * Name: stm32_i2c_isr_process + * + * Description: + * Common Interrupt Service Routine + * + ****************************************************************************/ + +static int stm32_i2c_isr_process(struct stm32_i2c_priv_s *priv) +{ + uint32_t status; +#ifndef CONFIG_I2C_POLLED + uint32_t regval; +#endif +#ifdef CONFIG_STM32_I2C_DMA + uint16_t cr2; +#endif + + i2cinfo("I2C ISR called\n"); + + /* Get state of the I2C controller (register SR1 only) + * + * Get control register SR1 only as reading both SR1 and SR2 clears the + * ADDR flag(possibly others) causing the hardware to advance to the next + * state without the proper action being taken. + */ + + status = stm32_i2c_getreg(priv, STM32_I2C_SR1_OFFSET); + + /* Update private version of the state */ + + priv->status = status; + + /* Check if this is a new transmission so to set up the + * trace table accordingly. + */ + + stm32_i2c_tracenew(priv, status); + stm32_i2c_traceevent(priv, I2CEVENT_ISR_CALL, 0); + + /* Messages handling (1/2) + * + * Message handling should only operate when a message has been completely + * sent and after the ISR had the chance to run to set bits after the last + * written/read byte, i.e. priv->dcnt == -1. This is also the case in when + * the ISR is called for the first time. This can seen in + * stm32_i2c_process() before entering the stm32_i2c_sem_waitdone() waiting + * process. + * + * Message handling should only operate when: + * - A message has been completely sent and there are still messages + * to send(i.e. msgc > 0). + * - After the ISR had the chance to run to set start bit or + * termination flags after the last written/read byte(after last byte + * dcnt=0, msg handling dcnt = -1). + * + * When the ISR is called for the first time the same conditions hold. + * This can seen in stm32_i2c_process() before entering the + * stm32_i2c_sem_waitdone() waiting process. + */ + +#ifdef CONFIG_STM32_I2C_DMA + /* If ISR gets called (ex. polling mode) while DMA is still in + * progress, we should just return and let the DMA finish. + */ + + cr2 = stm32_i2c_getreg(priv, STM32_I2C_CR2_OFFSET); + if ((cr2 & I2C_CR2_DMAEN) != 0) + { +#ifdef CONFIG_DEBUG_I2C_INFO + size_t left = stm32_dmaresidual(priv->rxdma); + + i2cinfo("DMA in progress: %ld [bytes] remainining. Returning.\n", + left); +#endif + return OK; + } +#endif + + if (priv->dcnt == -1 && priv->msgc > 0) + { + /* Any new message should begin with "Start" condition + * However there were 2 situations where that was not true + * Situation 1: + * Next message continue transmission sequence of previous message + * + * Situation 2: If an error is injected that looks like a STOP the + * interrupt will be reentered with some status that will be incorrect. + * This will ensure that the error handler will clear the interrupt + * enables and return the error to the waiting task. + */ + + if (((priv->msgv[0].flags & I2C_M_NOSTART) != 0 && + (status & I2C_SR1_TXE) == 0) || + ((priv->msgv[0].flags & I2C_M_NOSTART) == 0 && + (status & I2C_SR1_SB) == 0)) + { +#if defined(CONFIG_STM32_I2C_DMA) || defined(CONFIG_I2C_POLLED) + return OK; +#else + priv->status |= I2C_SR1_TIMEOUT; + goto state_error; +#endif + } + + i2cinfo("Switch to new message\n"); + + /* Get current message to process data and copy to private structure */ + + priv->ptr = priv->msgv->buffer; /* Copy buffer to private struct */ + priv->dcnt = priv->msgv->length; /* Set counter of current msg length */ + priv->flags = priv->msgv->flags; /* Copy flags to private struct */ + + i2cinfo("Current flags %i\n", priv->flags); + + /* Decrease counter to indicate the number of messages left to + * process + */ + + priv->msgc--; + + /* Decrease message pointer. + * If last message set next message vector to null + */ + + if (priv->msgc == 0) + { + /* No more messages, don't need to increment msgv. This pointer + * will be set to zero when reaching the termination of the ISR + * calls, i.e. Messages handling(2/2). + */ + } + else + { + /* If not last message increment to next message to process */ + + priv->msgv++; + } + + /* Trace event */ + + stm32_i2c_traceevent(priv, I2CEVENT_MSG_HANDLING, priv->msgc); + } + + /* Note the event where we are on the last message and after the last + * byte is handled at the bottom of this function, as it terminates + * the repeated calls to the ISR. + */ + + /* I2C protocol logic + * + * I2C protocol logic follows. It's organized in an if else chain such that + * only one mode of operation is executed every time the ISR is called. + */ + + /* Address Handling + * + * Check if a start bit was set and transmit address with proper format. + * + * Note: + * On first call the start bit has been set by stm32_i2c_waitdone() + * Otherwise it will be set from this ISR. + * + * Remember that after a start bit an address has always to be sent. + */ + + if ((status & I2C_SR1_SB) != 0) + { + /* Start bit is set */ + + i2cinfo("Entering address handling, status = %" PRIi32 "\n", status); + + /* Check for empty message (for robustness) */ + + if (priv->dcnt > 0) + { + /* Set POS bit to zero (can be up from a previous 2 byte receive) */ + + stm32_i2c_modifyreg(priv, STM32_I2C_CR1_OFFSET, I2C_CR1_POS, 0); + + /* ACK is the expected answer for N>=3 reads and writes */ + + stm32_i2c_modifyreg(priv, STM32_I2C_CR1_OFFSET, 0, I2C_CR1_ACK); + + /* Send address byte with correct 8th bit set + * (for writing or reading) + * Transmission happens after having written to the data register + * STM32_I2C_DR + */ + + stm32_i2c_putreg(priv, STM32_I2C_DR_OFFSET, + (priv->flags & I2C_M_TEN) ? + 0 : ((priv->msgv->addr << 1) | + (priv->flags & I2C_M_READ))); + + i2cinfo("Address sent. Addr=%#02x Write/Read bit=%i\n", + priv->msgv->addr, (priv->flags & I2C_M_READ)); + + /* Flag that address has just been sent */ + + priv->check_addr_ack = true; + + stm32_i2c_traceevent(priv, I2CEVENT_SENDADDR, priv->msgv->addr); + } + else + { + /* TODO: untested!! */ + + i2cwarn(" An empty message has been detected, " + "ignoring and passing to next message.\n"); + + /* Trace event */ + + stm32_i2c_traceevent(priv, I2CEVENT_EMPTY_MSG, 0); + + /* Set condition to activate msg handling */ + + priv->dcnt = -1; + +#ifndef CONFIG_I2C_POLLED + /* Restart ISR by setting an interrupt buffer bit */ + + stm32_i2c_modifyreg(priv, + STM32_I2C_CR2_OFFSET, 0, I2C_CR2_ITBUFEN); +#endif + } + } + + /* Address cleared event + * + * Check if the address cleared, i.e. the driver found a valid address. + * If a NACK was received the address is invalid, if an ACK was + * received the address is valid and transmission can continue. + */ + + /* Check for NACK after an address */ + +#ifndef CONFIG_I2C_POLLED + /* When polling the i2c ISR it's not possible to determine when + * an address has been ACKed(i.e. the address is valid). + * + * The mechanism to deal a NACKed address is to wait for the I2C + * call to timeout (value defined in defconfig by one of the + * following: CONFIG_STM32_I2C_DYNTIMEO, CONFIG_STM32_I2CTIMEOSEC, + * CONFIG_STM32_I2CTIMEOMS, CONFIG_STM32_I2CTIMEOTICKS). + * + * To be safe in the case of a timeout/NACKed address a stop bit + * is set on the bus to clear it. In POLLED operation it's done + * stm32_i2c_process() after the call to stm32_i2c_sem_waitdone(). + * + * In ISR driven operation the stop bit in case of a NACKed address + * is set in the ISR itself. + * + * Note: this commentary is found in both places. + */ + + else if ((status & I2C_SR1_ADDR) == 0 && priv->check_addr_ack) + { + i2cinfo("Invalid Address. Setting stop bit and clearing message\n"); + i2cinfo("status %" PRIi32 "\n", status); + + /* Set condition to terminate msg chain transmission as address is + * invalid. + */ + + priv->dcnt = -1; + priv->msgc = 0; + + i2cinfo("dcnt %i , msgc %i\n", priv->dcnt, priv->msgc); + + /* Reset flag to check for valid address */ + + priv->check_addr_ack = false; + + /* Send stop bit to clear bus */ + + stm32_i2c_sendstop(priv); + + /* Trace event */ + + stm32_i2c_traceevent(priv, I2CEVENT_ADDRESS_NACKED, priv->msgv->addr); + } +#endif + + /* ACK in read mode, ACK in write mode is handled separately */ + + else if ((priv->flags & I2C_M_READ) != 0 && (status & I2C_SR1_ADDR) != 0 && + priv->check_addr_ack) + { + /* Reset check addr flag as we are handling this event */ + + priv->check_addr_ack = false; + + /* Note: + * + * When reading a single byte the stop condition has to be set + * immediately after clearing the state flags, which happens + * when reading SR2(as SR1 has already been read). + * + * Similarly when reading 2 bytes the NACK bit has to be set as just + * after the clearing of the address. + */ + + if (priv->dcnt == 1) + { + /* this should only happen when receiving a message of length 1 */ + + i2cinfo("short read N=1: setting NACK\n"); + + /* Set POS bit to zero (can be up from a previous 2 byte receive) */ + + stm32_i2c_modifyreg(priv, STM32_I2C_CR1_OFFSET, I2C_CR1_POS, 0); + + /* Immediately set NACK */ + + stm32_i2c_modifyreg(priv, STM32_I2C_CR1_OFFSET, I2C_CR1_ACK, 0); + +#ifndef CONFIG_I2C_POLLED + /* Enable RxNE and TxE buffers in order to receive one or multiple + * bytes + */ + + stm32_i2c_modifyreg(priv, + STM32_I2C_CR2_OFFSET, 0, I2C_CR2_ITBUFEN); +#endif + + /* Clear ADDR flag by reading SR2 and adding it to status */ + + status |= (stm32_i2c_getreg(priv, STM32_I2C_SR2_OFFSET) << 16); + + /* Send Stop/Restart */ + + if (priv->msgc > 0) + { + stm32_i2c_sendstart(priv); + } + else + { + stm32_i2c_sendstop(priv); + } + + i2cinfo("Address ACKed beginning data reception\n"); + i2cinfo("short read N=1: programming stop bit\n"); + + /* Trace */ + + stm32_i2c_traceevent(priv, I2CEVENT_ADDRESS_ACKED_READ_1, 0); + } + else if (priv->dcnt == 2) + { + /* This should only happen when receiving a message of length 2 */ + + /* Set POS bit to zero (can be up from a previous 2 byte receive) */ + + stm32_i2c_modifyreg(priv, STM32_I2C_CR1_OFFSET, 0, I2C_CR1_POS); + + /* Immediately set NACK */ + + stm32_i2c_modifyreg(priv, STM32_I2C_CR1_OFFSET, I2C_CR1_ACK, 0); + + /* Clear ADDR flag by reading SR2 and adding it to status */ + + status |= (stm32_i2c_getreg(priv, STM32_I2C_SR2_OFFSET) << 16); + + i2cinfo("Address ACKed beginning data reception\n"); + i2cinfo("short read N=2: programming NACK\n"); + + /* Trace */ + + stm32_i2c_traceevent(priv, I2CEVENT_ADDRESS_ACKED_READ_2, 0); + } + else + { + i2cinfo("Address ACKed beginning data reception\n"); + + /* Clear ADDR flag by reading SR2 and adding it to status */ + + status |= (stm32_i2c_getreg(priv, STM32_I2C_SR2_OFFSET) << 16); + + /* Trace */ + + stm32_i2c_traceevent(priv, I2CEVENT_ADDRESS_ACKED, 0); + +#ifdef CONFIG_STM32_I2C_DMA + /* DMA only when not doing a short read */ + + i2cinfo("Starting dma transfer and disabling interrupts\n"); + + /* The DMA must be initialized and enabled before the I2C data + * transfer. + * The DMAEN bit must be set in the I2C_CR2 register before the + * ADDR event. + */ + + stm32_dmasetup(priv->rxdma, + priv->config->base + STM32_I2C_DR_OFFSET, + (uint32_t)priv->ptr, priv->dcnt, + DMA_SCR_DIR_P2M | + DMA_SCR_MSIZE_8BITS | + DMA_SCR_PSIZE_8BITS | + DMA_SCR_MINC | + I2C_DMA_PRIO); + + /* Do not enable the ITBUFEN bit in the I2C_CR2 register if DMA is + * used. + */ + + stm32_i2c_modifyreg(priv, + STM32_I2C_CR2_OFFSET, I2C_CR2_ITBUFEN, 0); + +#ifndef CONFIG_I2C_POLLED + /* Now let DMA do all the work, disable i2c interrupts */ + + regval = stm32_i2c_getreg(priv, STM32_I2C_CR2_OFFSET); + regval &= ~I2C_CR2_ALLINTS; + stm32_i2c_putreg(priv, STM32_I2C_CR2_OFFSET, regval); +#endif + + /* The user can generate a Stop condition in the DMA Transfer + * Complete interrupt routine if enabled. This will be done in + * the dma rx callback Start DMA. + */ + + stm32_dmastart(priv->rxdma, stm32_i2c_dmarxcallback, priv, false); + stm32_i2c_modifyreg(priv, STM32_I2C_CR2_OFFSET, 0, I2C_CR2_DMAEN); +#else +#ifndef CONFIG_I2C_POLLED + if (priv->dcnt > 3) + { + /* Don't enable I2C_CR2_ITBUFEN for messages longer than 3 + * bytes + */ + + stm32_i2c_modifyreg(priv, + STM32_I2C_CR2_OFFSET, 0, I2C_CR2_ITBUFEN); + } +#endif +#endif + } + } + + /* Write mode + * + * Handles all write related I2C protocol logic. Also handles the + * ACK event after clearing the ADDR flag as the write has to + * begin immediately after. + */ + + else if ((priv->flags & I2C_M_READ) == 0 && + (status & I2C_SR1_BTF) != 0 && + priv->dcnt == 0) + { + /* After last byte, check what to do based on next message flags */ + + if (priv->msgc == 0) + { + /* If last message send stop bit */ + + stm32_i2c_sendstop(priv); + i2cinfo("Stop sent dcnt = %i msgc = %i\n", priv->dcnt, priv->msgc); + + /* Decrease counter to get to next message */ + + priv->dcnt--; + i2cinfo("dcnt %i\n", priv->dcnt); + stm32_i2c_traceevent(priv, I2CEVENT_WRITE_STOP, priv->dcnt); + } + + /* If there is a next message with no flags or the read flag + * a restart sequence has to be sent. + * Note msgv already points to the next message. + */ + + else if (priv->msgc > 0 && + (priv->msgv->flags == 0 || + (priv->msgv[0].flags & I2C_M_READ) != 0)) + { + /* Send start */ + + stm32_i2c_sendstart(priv); + + stm32_i2c_getreg(priv, STM32_I2C_DR_OFFSET); + + i2cinfo("Restart detected!\n"); + i2cinfo("Nextflag %i\n", priv->msgv[0].flags); + + /* Decrease counter to get to next message */ + + priv->dcnt--; + i2cinfo("dcnt %i\n", priv->dcnt); + stm32_i2c_traceevent(priv, I2CEVENT_WRITE_RESTART, priv->dcnt); + } + else + { + i2cinfo("Write mode: next message has an unrecognized flag.\n"); + stm32_i2c_traceevent(priv, + I2CEVENT_WRITE_FLAG_ERROR, priv->msgv->flags); + } + + status |= (stm32_i2c_getreg(priv, STM32_I2C_SR2_OFFSET) << 16); + } + else if ((priv->flags & I2C_M_READ) == 0 && + (status & (I2C_SR1_ADDR | I2C_SR1_TXE)) != 0 && + priv->dcnt != 0) + { + /* The has cleared(ADDR is set, ACK was received after the address) + * or the transmit buffer is empty flag has been set(TxE) then we can + * transmit the next byte. + */ + + i2cinfo("Entering write mode dcnt = %i msgc = %i\n", + priv->dcnt, priv->msgc); + + /* Clear ADDR flag by reading SR2 and adding it to status */ + + status |= (stm32_i2c_getreg(priv, STM32_I2C_SR2_OFFSET) << 16); + + /* Address has cleared so don't check on next call */ + + priv->check_addr_ack = false; + + /* Check if we have transmitted the whole message or we are after + * the last byte where the stop condition or else(according to the + * msg flags) has to be set. + */ + +#ifdef CONFIG_STM32_I2C_DMA + /* if DMA is enabled, only makes sense to make use of it for longer + * than 1 B transfers. + */ + + if (priv->dcnt > 1) + { + i2cinfo("Starting DMA transfer and disabling interrupts\n"); + + /* The DMA must be initialized and enabled before the I2C data + * transfer. The DMAEN bit must be set in the I2C_CR2 register + * before the ADDR event. + */ + + stm32_dmasetup(priv->txdma, + priv->config->base + STM32_I2C_DR_OFFSET, + (uint32_t) priv->ptr, priv->dcnt, + DMA_SCR_DIR_M2P | + DMA_SCR_MSIZE_8BITS | + DMA_SCR_PSIZE_8BITS | + DMA_SCR_MINC | + I2C_DMA_PRIO); + + /* Do not enable the ITBUFEN bit in the I2C_CR2 register if DMA is + * used. + */ + + stm32_i2c_modifyreg(priv, + STM32_I2C_CR2_OFFSET, I2C_CR2_ITBUFEN, 0); + +#ifndef CONFIG_I2C_POLLED + /* Now let DMA do all the work, disable i2c interrupts */ + + regval = stm32_i2c_getreg(priv, STM32_I2C_CR2_OFFSET); + regval &= ~I2C_CR2_ALLINTS; + stm32_i2c_putreg(priv, STM32_I2C_CR2_OFFSET, regval); +#endif + + /* In the interrupt routine after the EOT interrupt, disable DMA + * requests then wait for a BTF event before programming the Stop + * condition. To do this, we'll just call the ISR again in + * DMA tx callback, in which point we fall into the msgc==0 case + * which ultimately sends the stop..TODO: but we don't explicitly + * wait for BTF bit being set... + * Start DMA. + */ + + stm32_i2c_modifyreg(priv, STM32_I2C_CR2_OFFSET, 0, I2C_CR2_DMAEN); + stm32_dmastart(priv->txdma, stm32_i2c_dmatxcallback, priv, false); + } + else +#endif /* CONFIG_STM32_I2C_DMA */ + { +#ifndef CONFIG_I2C_POLLED + if (priv->dcnt == 1 && + (priv->msgc == 0 || (priv->msgv->flags & I2C_M_NOSTART) == 0)) + { + stm32_i2c_modifyreg(priv, + STM32_I2C_CR2_OFFSET, I2C_CR2_ITBUFEN, 0); + } +#endif + + /* Transmitting message. + * Send byte == write data into write register + */ + + stm32_i2c_putreg(priv, STM32_I2C_DR_OFFSET, *priv->ptr++); + + /* Decrease current message length */ + + stm32_i2c_traceevent(priv, I2CEVENT_WRITE_TO_DR, priv->dcnt); + priv->dcnt--; + + if ((status & I2C_SR1_ADDR) != 0 && priv->dcnt > 0) + { + /* Transmitting message. + * ADDR -> BTF & TXE - Send one more byte + */ + + stm32_i2c_putreg(priv, STM32_I2C_DR_OFFSET, *priv->ptr++); + + /* Decrease current message length */ + + stm32_i2c_traceevent(priv, I2CEVENT_WRITE_TO_DR, priv->dcnt); + priv->dcnt--; + } + +#ifndef CONFIG_I2C_POLLED + if (((status & I2C_SR1_ADDR) != 0 && priv->dcnt > 0) || + (priv->msgc > 0 && (priv->msgv->flags & I2C_M_NOSTART) != 0)) + { + stm32_i2c_modifyreg(priv, + STM32_I2C_CR2_OFFSET, 0, I2C_CR2_ITBUFEN); + } +#endif + + if (priv->dcnt == 0 && + priv->msgc > 0 && (priv->msgv->flags & I2C_M_NOSTART) != 0) + { + /* Set condition to get to next message */ + + priv->dcnt = -1; + stm32_i2c_traceevent(priv, + I2CEVENT_WRITE_NO_RESTART, priv->dcnt); + } + } + } + + /* Read mode + * + * Handles all read related I2C protocol logic. + * + * * * * * * * WARNING STM32F1xx HARDWARE ERRATA * * * * * * * + * + * source: https://github.com/hikob/openlab/blob/master/drivers/stm32/i2c.c + * + * RXNE-only events should not be handled since it sometimes + * fails. Only BTF & RXNE events should be handled (with the + * consequence of slowing down the transfer). + * + * It seems that when a RXNE interrupt is handled 'around' + * the end of the next byte reception, the DR register read + * is ignored by the i2c controller: it does not flush the + * DR with next byte + * + * Thus we read twice the same byte and we read effectively + * read one byte less than expected from the i2c slave point + * of view. + * + * Example: + * + we want to receive 6 bytes (B1 to B6) + * + the problem appear when reading B3 + * -> we read B1 B2 B3 B3 B4 B5(B3 twice) + * -> the i2c transfer was B1 B2 B3 B4 B5(B6 is not sent) + */ + + else if ((priv->flags & (I2C_M_READ)) != 0 && + (status & (I2C_SR1_RXNE | I2C_SR1_BTF)) != 0) + { + /* When read flag is set and the receive buffer is not empty + * (RXNE is set) then the driver can read from the data register. + */ + + status |= (stm32_i2c_getreg(priv, STM32_I2C_SR2_OFFSET) << 16); + + i2cinfo("Entering read mode dcnt = %i msgc = %i, " + "status 0x%04" PRIx32 "\n", + priv->dcnt, priv->msgc, status); + + /* Byte #N-3W, we don't want to manage RxNE interrupt anymore, bytes + * N, N-1, N-2 will be read with BTF: + */ + +#ifndef CONFIG_I2C_POLLED + if (priv->dcnt < 5) + { + stm32_i2c_modifyreg(priv, + STM32_I2C_CR2_OFFSET, I2C_CR2_ITBUFEN, 0); + } +#else + if (priv->dcnt == 1 || + priv->dcnt > 3 || (status & I2C_SR1_BTF) != 0) +#endif + { + /* BTF: N-2/N-1, set NACK, read N-2 */ + + if (priv->dcnt == 3) + { + stm32_i2c_modifyreg(priv, + STM32_I2C_CR1_OFFSET, I2C_CR1_ACK, 0); + } + + /* BTF: N-1/N, STOP/START, read N-1, N */ + + else if (priv->dcnt == 2) + { + if (priv->msgc > 0) + { + stm32_i2c_sendstart(priv); + } + else + { + stm32_i2c_sendstop(priv); + } + + /* Read byte #N-1 */ + + *priv->ptr++ = stm32_i2c_getreg(priv, STM32_I2C_DR_OFFSET); + priv->dcnt--; + } + + /* Read last or current byte */ + + *priv->ptr++ = stm32_i2c_getreg(priv, STM32_I2C_DR_OFFSET); + priv->dcnt--; + + if (priv->dcnt == 0) + { + priv->dcnt = -1; + } + } + } + + /* Empty call handler + * + * Case to handle an empty call to the ISR where it only has to + * Shutdown + */ + + else if (priv->dcnt == -1 && priv->msgc == 0) + { + /* Read rest of the state */ + + status |= (stm32_i2c_getreg(priv, STM32_I2C_SR2_OFFSET) << 16); + i2cinfo("Empty call to ISR: Stopping ISR\n"); + stm32_i2c_traceevent(priv, I2CEVENT_ISR_EMPTY_CALL, 0); + } + + /* Error handler + * + * Gets triggered if the driver does not recognize a situation(state) + * it can deal with. + * This should not happen in interrupt based operation(i.e. when + * CONFIG_I2C_POLLED is not set in the defconfig file). + * During polled operation(i.e. CONFIG_I2C_POLLED=y in defconfig) + * this case should do nothing but tracing the event that the + * device wasn't ready yet. + */ + + else + { +#ifdef CONFIG_I2C_POLLED + stm32_i2c_traceevent(priv, I2CEVENT_POLL_DEV_NOT_RDY, 0); +#else + /* Read rest of the state */ + + status |= (stm32_i2c_getreg(priv, STM32_I2C_SR2_OFFSET) << 16); + + /* No any error bit is set, but driver is in incorrect state, signal + * it with "Bus error" bit. + */ + + if ((status & I2C_SR1_ERRORMASK) != 0) + { + priv->status |= I2C_SR1_BERR; + } + + i2cinfo(" No correct state detected(start bit, read or write)\n"); + i2cinfo(" state %" PRIi32 "\n", status); + + /* Set condition to terminate ISR and wake waiting thread */ + + priv->dcnt = -1; + priv->msgc = 0; + stm32_i2c_traceevent(priv, I2CEVENT_STATE_ERROR, 0); +#endif + } + + /* Messages handling(2/2) + * + * Transmission of the whole message chain has been completed. We have to + * terminate the ISR and wake up stm32_i2c_process() that is waiting for + * the ISR cycle to handle the sending/receiving of the messages. + */ + + /* First check for errors */ + + if ((status & I2C_SR1_ERRORMASK) != 0) + { + stm32_i2c_traceevent(priv, I2CEVENT_ERROR, status & I2C_SR1_ERRORMASK); + + /* Clear interrupt flags */ + +#if !defined(CONFIG_STM32_I2C_DMA) && !defined(CONFIG_I2C_POLLED) +state_error: +#endif + stm32_i2c_putreg(priv, STM32_I2C_SR1_OFFSET, 0); + + priv->dcnt = -1; + priv->msgc = 0; + } + + if (priv->dcnt == -1 && priv->msgc == 0) + { + i2cinfo("Shutting down I2C ISR\n"); + + stm32_i2c_traceevent(priv, I2CEVENT_ISR_SHUTDOWN, 0); + + /* Clear internal pointer to the message content. + * Good practice + done by last implementation when messages are + * finished (compatibility concerns) + */ + + priv->msgv = NULL; + +#ifdef CONFIG_I2C_POLLED + priv->intstate = INTSTATE_DONE; +#else + /* Clear all interrupts */ + + regval = stm32_i2c_getreg(priv, STM32_I2C_CR2_OFFSET); + regval &= ~I2C_CR2_ALLINTS; + stm32_i2c_putreg(priv, STM32_I2C_CR2_OFFSET, regval); + + /* Is there a thread waiting for this event(there should be) */ + + if (priv->intstate == INTSTATE_WAITING) + { + /* Yes.. inform the thread that the transfer is complete + * and wake it up. + */ + + nxsem_post(&priv->sem_isr); + priv->intstate = INTSTATE_DONE; + } +#endif + } + + return OK; +} + +/**************************************************************************** + * Name: stm32_i2c_isr + * + * Description: + * Common I2C interrupt service routine + * + ****************************************************************************/ + +#ifndef CONFIG_I2C_POLLED +static int stm32_i2c_isr(int irq, void *context, void *arg) +{ + struct stm32_i2c_priv_s *priv = (struct stm32_i2c_priv_s *)arg; + + DEBUGASSERT(priv != NULL); + return stm32_i2c_isr_process(priv); +} +#endif + +/**************************************************************************** + * Name: stm32_i2c_dmarxcallback + * + * Description: + * Called when the RX DMA completes + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_I2C_DMA +static void stm32_i2c_dmarxcallback(DMA_HANDLE handle, + uint8_t status, void *arg) +{ +#ifndef CONFIG_I2C_POLLED + uint32_t regval; +#endif + + i2cinfo("DMA rx callback, status = %d\n", status); + + struct stm32_i2c_priv_s *priv = (struct stm32_i2c_priv_s *)arg; + + priv->dcnt = -1; + + /* The user can generate a Stop condition in the DMA Transfer Complete + * interrupt routine if enabled. + */ + + if (priv->msgc > 0) + { + stm32_i2c_sendstart(priv); + } + else + { + stm32_i2c_sendstop(priv); + } + + /* Let the I2C periph know to stop DMA transfers, also is used by ISR + * to check if DMA is done. + */ + + stm32_i2c_modifyreg(priv, STM32_I2C_CR2_OFFSET, I2C_CR2_DMAEN, 0); + +#ifndef CONFIG_I2C_POLLED + /* Re-enable interrupts */ + + regval = stm32_i2c_getreg(priv, STM32_I2C_CR2_OFFSET); + regval |= (I2C_CR2_ITERREN | I2C_CR2_ITEVFEN); + stm32_i2c_putreg(priv, STM32_I2C_CR2_OFFSET, regval); +#endif + + /* let the ISR routine take care of shutting down or switching to + * next msg + */ + + stm32_i2c_isr_process(priv); +} +#endif /* ifdef CONFIG_STM32_I2C_DMA */ + +/**************************************************************************** + * Name: stm32_i2c_dmarxcallback + * + * Description: + * Called when the RX DMA completes + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_I2C_DMA +static void stm32_i2c_dmatxcallback(DMA_HANDLE handle, + uint8_t status, void *arg) +{ +#ifndef CONFIG_I2C_POLLED + uint32_t regval; +#endif + + i2cinfo("DMA tx callback, status = %d\n", status); + + struct stm32_i2c_priv_s *priv = (struct stm32_i2c_priv_s *)arg; + + priv->dcnt = 0; + + /* In the interrupt routine after the EOT interrupt, + * disable DMA requests + */ + + stm32_i2c_modifyreg(priv, STM32_I2C_CR2_OFFSET, I2C_CR2_DMAEN, 0); + +#ifndef CONFIG_I2C_POLLED + /* re-enable interrupts */ + + regval = stm32_i2c_getreg(priv, STM32_I2C_CR2_OFFSET); + regval |= (I2C_CR2_ITERREN | I2C_CR2_ITEVFEN); + stm32_i2c_putreg(priv, STM32_I2C_CR2_OFFSET, regval); +#endif +} +#endif /* ifdef CONFIG_STM32_I2C_DMA */ + +/**************************************************************************** + * Name: stm32_i2c_init + * + * Description: + * Setup the I2C hardware, ready for operation with defaults + * + ****************************************************************************/ + +static int stm32_i2c_init(struct stm32_i2c_priv_s *priv) +{ + /* Power-up and configure GPIOs */ + + /* Enable power and reset the peripheral */ + + modifyreg32(STM32_RCC_APB1ENR, 0, priv->config->clk_bit); + modifyreg32(STM32_RCC_APB1RSTR, 0, priv->config->reset_bit); + modifyreg32(STM32_RCC_APB1RSTR, priv->config->reset_bit, 0); + + /* Configure pins */ + + if (stm32_configgpio(priv->config->scl_pin) < 0) + { + return ERROR; + } + + if (stm32_configgpio(priv->config->sda_pin) < 0) + { + stm32_unconfiggpio(priv->config->scl_pin); + return ERROR; + } + + /* Attach ISRs */ + +#ifndef CONFIG_I2C_POLLED + irq_attach(priv->config->ev_irq, stm32_i2c_isr, priv); + irq_attach(priv->config->er_irq, stm32_i2c_isr, priv); + up_enable_irq(priv->config->ev_irq); + up_enable_irq(priv->config->er_irq); +#endif + + /* Set peripheral frequency, where it must be at least 2 MHz for 100 kHz + * or 4 MHz for 400 kHz. This also disables all I2C interrupts. + */ + + stm32_i2c_putreg(priv, + STM32_I2C_CR2_OFFSET, (STM32_PCLK1_FREQUENCY / 1000000)); + + /* Force a frequency update */ + + priv->frequency = 0; + + stm32_i2c_setclock(priv, 100000); + +#ifdef CONFIG_STM32_I2C_DMA + /* If, in the I2C_CR2 register, the LAST bit is set, I2C automatically + * sends a NACK after the next byte following EOT_1. + * Clear DMA en just in case. + */ + + stm32_i2c_modifyreg(priv, + STM32_I2C_CR2_OFFSET, I2C_CR2_DMAEN, I2C_CR2_LAST); +#endif + + /* Enable I2C */ + + stm32_i2c_putreg(priv, STM32_I2C_CR1_OFFSET, I2C_CR1_PE); + return OK; +} + +/**************************************************************************** + * Name: stm32_i2c_deinit + * + * Description: + * Shutdown the I2C hardware + * + ****************************************************************************/ + +static int stm32_i2c_deinit(struct stm32_i2c_priv_s *priv) +{ + /* Disable I2C */ + + stm32_i2c_putreg(priv, STM32_I2C_CR1_OFFSET, 0); + stm32_i2c_putreg(priv, STM32_I2C_CR2_OFFSET, 0); + + /* Unconfigure GPIO pins */ + + stm32_unconfiggpio(priv->config->scl_pin); + stm32_unconfiggpio(priv->config->sda_pin); + + /* Disable and detach interrupts */ + +#ifndef CONFIG_I2C_POLLED + up_disable_irq(priv->config->ev_irq); + up_disable_irq(priv->config->er_irq); + irq_detach(priv->config->ev_irq); + irq_detach(priv->config->er_irq); +#endif + +#ifdef CONFIG_STM32_I2C_DMA + /* Disable DMA */ + + stm32_dmastop(priv->txdma); + stm32_dmastop(priv->rxdma); +#endif + + /* Disable clocking */ + + modifyreg32(STM32_RCC_APB1ENR, priv->config->clk_bit, 0); + return OK; +} + +/**************************************************************************** + * Device Driver Operations + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_i2c_transfer + * + * Description: + * Generic I2C transfer function + * + ****************************************************************************/ + +static int stm32_i2c_transfer(struct i2c_master_s *dev, + struct i2c_msg_s *msgs, int count) +{ + struct stm32_i2c_priv_s *priv = (struct stm32_i2c_priv_s *)dev; + uint32_t status = 0; +#ifdef I2C1_FSMC_CONFLICT + uint32_t ahbenr; +#endif + int ret; + + DEBUGASSERT(count); + + /* Ensure that address or flags don't change meanwhile */ + + ret = nxmutex_lock(&priv->lock); + if (ret < 0) + { + return ret; + } + +#ifdef CONFIG_STM32_I2C_DMA + /* Stop DMA just in case */ + + stm32_i2c_modifyreg(priv, STM32_I2C_CR2_OFFSET, I2C_CR2_DMAEN, 0); + stm32_dmastop(priv->rxdma); + stm32_dmastop(priv->txdma); +#endif + +#ifdef I2C1_FSMC_CONFLICT + /* Disable FSMC that shares a pin with I2C1 (LBAR) */ + + ahbenr = stm32_i2c_disablefsmc(priv); + +#else + /* Wait for any STOP in progress. NOTE: If we have to disable the FSMC + * then we cannot do this at the top of the loop, unfortunately. The STOP + * will not complete normally if the FSMC is enabled. + */ + + stm32_i2c_sem_waitstop(priv); +#endif + + /* Clear any pending error interrupts */ + + stm32_i2c_putreg(priv, STM32_I2C_SR1_OFFSET, 0); + + /* "Note: When the STOP, START or PEC bit is set, the software must + * not perform any write access to I2C_CR1 before this bit is + * cleared by hardware. Otherwise there is a risk of setting a + * second STOP, START or PEC request." However, if the bits are + * not cleared by hardware, then we will have to do that from hardware. + */ + + stm32_i2c_clrstart(priv); + + /* Old transfers are done */ + + /* Reset ptr and dcnt to ensure an unexpected data interrupt doesn't + * overwrite stale data. + */ + + priv->dcnt = 0; + priv->ptr = NULL; + + priv->msgv = msgs; + priv->msgc = count; + + /* Reset I2C trace logic */ + + stm32_i2c_tracereset(priv); + + /* Set I2C clock frequency (on change it toggles I2C_CR1_PE !) + * REVISIT: Note that the frequency is set only on the first message. + * This could be extended to support different transfer frequencies for + * each message segment. + */ + + stm32_i2c_setclock(priv, msgs->frequency); + + /* Trigger start condition, then the process moves into the ISR. I2C + * interrupts will be enabled within stm32_i2c_waitdone(). + */ + + priv->dcnt = -1; + priv->status = 0; + stm32_i2c_sendstart(priv); + + /* Wait for an ISR, if there was a timeout, fetch latest status to get + * the BUSY flag. + */ + + if (stm32_i2c_sem_waitdone(priv) < 0) + { + status = stm32_i2c_getstatus(priv); + ret = -ETIMEDOUT; + + i2cerr("ERROR: Timed out: CR1: 0x%04x status: 0x%08" PRIx32 "\n", + stm32_i2c_getreg(priv, STM32_I2C_CR1_OFFSET), status); + + /* "Note: When the STOP, START or PEC bit is set, the software must + * not perform any write access to I2C_CR1 before this bit is + * cleared by hardware. Otherwise there is a risk of setting a + * second STOP, START or PEC request." + */ + + stm32_i2c_clrstart(priv); + + /* Clear busy flag in case of timeout */ + + status = priv->status & 0xffff; + } + else + { + /* clear SR2 (BUSY flag) as we've done successfully */ + + status = priv->status & 0xffff; + } + + /* Check for error status conditions */ + + if ((status & I2C_SR1_ERRORMASK) != 0) + { + /* I2C_SR1_ERRORMASK is the 'OR' of the following individual bits: */ + + if (status & I2C_SR1_BERR) + { + /* Bus Error */ + + ret = -EIO; + } + else if (status & I2C_SR1_ARLO) + { + /* Arbitration Lost (master mode) */ + + ret = -EAGAIN; + } + else if (status & I2C_SR1_AF) + { + /* Acknowledge Failure */ + + ret = -ENXIO; + } + else if (status & I2C_SR1_OVR) + { + /* Overrun/Underrun */ + + ret = -EIO; + } + else if (status & I2C_SR1_PECERR) + { + /* PEC Error in reception */ + + ret = -EPROTO; + } + else if (status & I2C_SR1_TIMEOUT) + { + /* Timeout or Tlow Error */ + + ret = -ETIME; + } + + /* This is not an error and should never happen since SMBus is not + * enabled + */ + + else /* if (status & I2C_SR1_SMBALERT) */ + { + /* SMBus alert is an optional signal with an interrupt line for + * devices that want to trade their ability to master for a pin. + */ + + ret = -EINTR; + } + } + + /* This is not an error, but should not happen. The BUSY signal can hang, + * however, if there are unhealthy devices on the bus that need to be + * reset. + * NOTE: We will only see this busy indication if stm32_i2c_sem_waitdone() + * fails above; Otherwise it is cleared. + */ + + else if ((status & (I2C_SR2_BUSY << 16)) != 0) + { + /* I2C Bus is for some reason busy */ + + ret = -EBUSY; + } + + /* Dump the trace result */ + + stm32_i2c_tracedump(priv); + +#ifdef I2C1_FSMC_CONFLICT + /* Wait for any STOP in progress. NOTE: If we have to disable the FSMC + * then we cannot do this at the top of the loop, unfortunately. The STOP + * will not complete normally if the FSMC is enabled. + */ + + stm32_i2c_sem_waitstop(priv); + + /* Re-enable the FSMC */ + + stm32_i2c_enablefsmc(ahbenr); +#endif + + /* Ensure that any ISR happening after we finish can't overwrite any user + * data + */ + + priv->dcnt = 0; + priv->ptr = NULL; + + nxmutex_unlock(&priv->lock); + return ret; +} + +/**************************************************************************** + * Name: stm32_i2c_reset + * + * Description: + * Perform an I2C bus reset in an attempt to break loose stuck I2C devices. + * + * Input Parameters: + * dev - Device-specific state data + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +#ifdef CONFIG_I2C_RESET +static int stm32_i2c_reset(struct i2c_master_s *dev) +{ + struct stm32_i2c_priv_s *priv = (struct stm32_i2c_priv_s *)dev; + unsigned int clock_count; + unsigned int stretch_count; + uint32_t scl_gpio; + uint32_t sda_gpio; + uint32_t frequency; + int ret; + + DEBUGASSERT(dev); + + /* Our caller must own a ref */ + + DEBUGASSERT(priv->refs > 0); + + /* Lock out other clients */ + + ret = nxmutex_lock(&priv->lock); + if (ret < 0) + { + return ret; + } + + ret = -EIO; + + /* Save the current frequency */ + + frequency = priv->frequency; + + /* De-init the port */ + + stm32_i2c_deinit(priv); + + /* Use GPIO configuration to un-wedge the bus */ + + scl_gpio = MKI2C_OUTPUT(priv->config->scl_pin); + sda_gpio = MKI2C_OUTPUT(priv->config->sda_pin); + + stm32_configgpio(scl_gpio); + stm32_configgpio(sda_gpio); + + /* Let SDA go high */ + + stm32_gpiowrite(sda_gpio, 1); + + /* Clock the bus until any slaves currently driving it let it go. */ + + clock_count = 0; + while (!stm32_gpioread(sda_gpio)) + { + /* Give up if we have tried too hard */ + + if (clock_count++ > 10) + { + goto out; + } + + /* Sniff to make sure that clock stretching has finished. + * + * If the bus never relaxes, the reset has failed. + */ + + stretch_count = 0; + while (!stm32_gpioread(scl_gpio)) + { + /* Give up if we have tried too hard */ + + if (stretch_count++ > 10) + { + goto out; + } + + up_udelay(10); + } + + /* Drive SCL low */ + + stm32_gpiowrite(scl_gpio, 0); + up_udelay(10); + + /* Drive SCL high again */ + + stm32_gpiowrite(scl_gpio, 1); + up_udelay(10); + } + + /* Generate a start followed by a stop to reset slave + * state machines. + */ + + stm32_gpiowrite(sda_gpio, 0); + up_udelay(10); + stm32_gpiowrite(scl_gpio, 0); + up_udelay(10); + stm32_gpiowrite(scl_gpio, 1); + up_udelay(10); + stm32_gpiowrite(sda_gpio, 1); + up_udelay(10); + + /* Revert the GPIO configuration. */ + + stm32_unconfiggpio(sda_gpio); + stm32_unconfiggpio(scl_gpio); + + /* Re-init the port */ + + stm32_i2c_init(priv); + + /* Restore the frequency */ + + stm32_i2c_setclock(priv, frequency); + ret = OK; + +out: + + /* Release the port for reuse by other clients */ + + nxmutex_unlock(&priv->lock); + return ret; +} +#endif /* CONFIG_I2C_RESET */ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_i2cbus_initialize + * + * Description: + * Initialize one I2C bus + * + ****************************************************************************/ + +struct i2c_master_s *stm32_i2cbus_initialize(int port) +{ + struct stm32_i2c_priv_s *priv = NULL; + + /* Get I2C private structure */ + + switch (port) + { +#ifdef CONFIG_STM32_I2C1 + case 1: + priv = (struct stm32_i2c_priv_s *)&stm32_i2c1_priv; + break; +#endif +#ifdef CONFIG_STM32_I2C2 + case 2: + priv = (struct stm32_i2c_priv_s *)&stm32_i2c2_priv; + break; +#endif +#ifdef CONFIG_STM32_I2C3 + case 3: + priv = (struct stm32_i2c_priv_s *)&stm32_i2c3_priv; + break; +#endif + default: + return NULL; + } + + /* Initialize private data for the first time, increment reference count, + * power-up hardware and configure GPIOs. + */ + + nxmutex_lock(&priv->lock); + if (priv->refs++ == 0) + { + stm32_i2c_init(priv); + +#ifdef CONFIG_STM32_I2C_DMA + /* Get DMA channels. NOTE: stm32_dmachannel() will always assign the + * DMA channel. If the channel is not available, then + * stm32_dmachannel() will block and wait until the channel becomes + * available. + * WARNING: If you have another device sharing a DMA channel with SPI + * and the code never releases that channel, then the call to + * stm32_dmachannel() will hang forever in this function! + * Don't let your design do that! + */ + + priv->rxdma = stm32_dmachannel(priv->rxch); + priv->txdma = stm32_dmachannel(priv->txch); + DEBUGASSERT(priv->rxdma && priv->txdma); +#endif /* CONFIG_STM32_I2C_DMA */ + } + + nxmutex_unlock(&priv->lock); + return (struct i2c_master_s *)priv; +} + +/**************************************************************************** + * Name: stm32_i2cbus_uninitialize + * + * Description: + * Uninitialize an I2C bus + * + ****************************************************************************/ + +int stm32_i2cbus_uninitialize(struct i2c_master_s *dev) +{ + struct stm32_i2c_priv_s *priv = (struct stm32_i2c_priv_s *)dev; + + DEBUGASSERT(dev); + + /* Decrement reference count and check for underflow */ + + if (priv->refs == 0) + { + return ERROR; + } + + nxmutex_lock(&priv->lock); + if (--priv->refs) + { + nxmutex_unlock(&priv->lock); + return OK; + } + + /* Disable power and other HW resource (GPIO's) */ + + stm32_i2c_deinit(priv); + +#ifdef CONFIG_STM32_I2C_DMA + stm32_dmafree(priv->rxdma); + stm32_dmafree(priv->txdma); +#endif + + nxmutex_unlock(&priv->lock); + return OK; +} + +#endif /* CONFIG_STM32_HAVE_IP_I2C_M3M4_V1 */ +#endif /* CONFIG_STM32_I2C1 || CONFIG_STM32_I2C2 || CONFIG_STM32_I2C3 */ diff --git a/arch/arm/src/common/stm32/stm32_i2c_m3m4_v2.c b/arch/arm/src/common/stm32/stm32_i2c_m3m4_v2.c new file mode 100644 index 0000000000000..8b0fd802c5e4a --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_i2c_m3m4_v2.c @@ -0,0 +1,2829 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_i2c_m3m4_v2.c + * + * SPDX-License-Identifier: BSD-3-Clause + * SPDX-FileCopyrightText: 2016-2017 Gregory Nutt. All rights reserved. + * SPDX-FileCopyrightText: 2016 Doug Vetter. All rights reserved. + * SPDX-FileCopyrightText: 2011 Uros Platise. All rights reserved. + * SPDX-FileContributor: Uros Platise + * SPDX-FileContributor: Gregory Nutt + * SPDX-FileContributor: John Wharington + * SPDX-FileContributor: David Sidrane + * SPDX-FileContributor: Bob Feretich + * SPDX-FileContributor: Doug Vetter + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/* -------------------------------------------------------------------------- + * + * STM32 I2C IPv2 I2C Driver + * + * Supports: + * - Master operation: + * Standard-mode (up to 100 kHz) + * Fast-mode (up to 400 kHz) + * Fast-mode Plus (up to 1 MHz) + * fI2CCLK clock source selection is based on STM32_RCC_DCKCFGR2_I2CxSRC + * being set to HSI and the calculations are based on + * STM32_HSI_FREQUENCY of 16mHz + * + * - Multiple instances (shared bus) + * - Interrupt based operation + * - RELOAD support + * + * Unsupported, possible future work: + * - More effective error reporting to higher layers + * - Slave operation + * - Support of fI2CCLK frequencies other than HSI + * - Polled operation (code present but untested) + * - SMBus support + * - Multi-master support + * - IPMI + * + * Test Environment: + * + * - NUCLEO-F303ZE + * + * Operational Status: + * + * All supported features have been tested and found to be operational. + * + * Although the RELOAD capability has been tested as it was required to + * implement the I2C_M_NOSTART flag on F3 hardware, the associated + * logic to support the transfer messages with more than 255 byte + * payloads has not been tested as the author lacked access to a real + * device supporting these types of transfers. + * + * Performance Benchmarks: TBD + * + * Time to transfer two messages, each a byte in length, in addition to the + * START condition, in interrupt mode: + * + * DEBUG enabled (development): TBDms + * Excessive delay here is caused by printing to the console and + * is of no concern. + * + * DEBUG disabled (production): TBSus + * Between Messages: TBDus + * Between Bytes: TBDus + * + * Implementation: + * + * - Device: structure as defined by the nuttx/i2c/i2c.h + * + * - Instance: represents each individual access to the I2C driver, obtained + * by the i2c_init(); it extends the Device structure from the + * nuttx/i2c/i2c.h; Instance points to OPS, to common I2C Hardware + * private data and contains its own private data including frequency, + * address and mode of operation. + * + * - Private: Private data of an I2C Hardware + * + * High Level Functional Description + * + * This driver works with I2C "messages" (struct i2c_msg_s), which carry a + * buffer intended to transfer data to, or store data read from, the I2C bus. + * + * As the hardware can only transmit or receive one byte at a time the basic + * job of the driver (and the ISR specifically) is to process each message in + * the order they are stored in the message list, one byte at a time. When + * no messages are left the ISR exits and returns the result to the caller. + * + * The order of the list of I2C messages provided to the driver is important + * and dependent upon the hardware in use. A typical I2C transaction between + * the F3 as an I2C Master and some other IC as a I2C Slave requires two + * messages that communicate the: + * + * 1) Subaddress (register offset on the slave device) + * 2) Data sent to or read from the device + * + * These messages will typically be one byte in length but may be up to 2^31 + * bytes in length. Incidentally, the maximum length is limited only because + * i2c_msg_s.length is a signed int for some odd reason. + * + * Interrupt mode relies on the following interrupt events: + * + * TXIS - Transmit interrupt + * (data transmitted to bus and acknowledged) + * NACKF - Not Acknowledge Received + * (data transmitted to bus and NOT acknowledged) + * RXNE - Receive interrupt + * (data received from bus) + * TC - Transfer Complete + * (All bytes in message transferred) + * TCR - Transfer Complete (Reload) + * (Current batch of bytes in message transferred) + * + * The driver currently supports Single Master mode only. Slave mode is not + * supported. Additionally, the driver runs in Software End Mode (AUTOEND + * disabled) so the driver is responsible for telling the hardware what to + * do at the end of a transfer. + * + * -------------------------------------------------------------------------- + * + * Configuration: + * + * To use this driver, enable the following configuration variable: + * + * CONFIG_STM32_I2C1 + * CONFIG_STM32_I2C2 + * CONFIG_STM32_I2C3 + * CONFIG_STM32_I2C4 + * + * To configure the ISR timeout using fixed values + * (CONFIG_STM32_I2C_DYNTIMEO=n): + * + * CONFIG_STM32_I2CTIMEOSEC (Timeout in seconds) + * CONFIG_STM32_I2CTIMEOMS (Timeout in milliseconds) + * CONFIG_STM32_I2CTIMEOTICKS (Timeout in ticks) + * + * To configure the ISR timeout using dynamic values + * (CONFIG_STM32_I2C_DYNTIMEO=y): + * + * CONFIG_STM32_I2C_DYNTIMEO_USECPERBYTE + * (Timeout in microseconds per byte) + * CONFIG_STM32_I2C_DYNTIMEO_STARTSTOP + * (Timeout for start/stop in milliseconds) + * + * Debugging output enabled with: + * + * CONFIG_DEBUG_FEATURES and CONFIG_DEBUG_I2C_{ERROR|WARN|INFO} + * + * ISR Debugging output may be enabled with: + * + * CONFIG_DEBUG_FEATURES and CONFIG_DEBUG_I2C_INFO + * + * -------------------------------------------------------------------------- + * + * References: + * + * RM0431: + * ST STM322xxx and STM323xxx Reference Manual + * Document ID: DocID029480 Revision 1, Jan 2017. + * + * RM0316: + * ST STM326xxx and STM327xxx Reference Manual + * Document ID: DocID028270 Revision 2, April 2016. + * + * DATASHEET: + * ST STM3277xx/STM3278Ax/STM3279x Datasheet + * Document ID: DocID028294, Revision 3, May 2016. + * + * ERRATA: + * STM326xxx/STM327xxx Errata sheet Rev A device limitations + * Document ID: DocID028806, Revision 2, April 2016. + * + * I2CSPEC: + * I2C Bus Specification and User Manual + * Document ID: UM10204, Revision 6, April 2014. + * + * -------------------------------------------------------------------------- + */ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "arm_internal.h" +#include "stm32_rcc.h" +#include "stm32_i2c.h" +#include "stm32_gpio.h" + +/* At least one I2C peripheral must be enabled */ + +#if defined(CONFIG_STM32_I2C1) || defined(CONFIG_STM32_I2C2) || \ + defined(CONFIG_STM32_I2C3) || defined(CONFIG_STM32_I2C4) + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#warning TODO: check I2C clock source. It must be HSI! +#undef INVALID_CLOCK_SOURCE + +#if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) || \ + defined(CONFIG_STM32_STM32F37XX) +# if STM32_HSI_FREQUENCY != 8000000 || defined(INVALID_CLOCK_SOURCE) +# error STM32_I2C: Peripheral clock is HSI and it must be 8MHz or the speed/timing calculations need to be redone. +# endif +#elif defined(CONFIG_STM32_STM32G4XXX) +# if STM32_HSI_FREQUENCY != 16000000 || defined(INVALID_CLOCK_SOURCE) +# error STM32_I2C: Peripheral clock is HSI and it must be 16MHz or the speed/timing calculations need to be redone. +# endif +#else +# error STM32_I2C: Device not Supported. +#endif + +/* CONFIG_I2C_POLLED may be set so that I2C interrupts will not be used. + * Instead, CPU-intensive polling will be used. + */ + +/* Interrupt wait timeout in seconds and milliseconds */ + +#if !defined(CONFIG_STM32_I2CTIMEOSEC) && !defined(CONFIG_STM32_I2CTIMEOMS) +# define CONFIG_STM32_I2CTIMEOSEC 0 +# define CONFIG_STM32_I2CTIMEOMS 500 /* Default is 500 milliseconds */ +# warning "Using Default 500 Ms Timeout" +#elif !defined(CONFIG_STM32_I2CTIMEOSEC) +# define CONFIG_STM32_I2CTIMEOSEC 0 /* User provided milliseconds */ +#elif !defined(CONFIG_STM32_I2CTIMEOMS) +# define CONFIG_STM32_I2CTIMEOMS 0 /* User provided seconds */ +#endif + +/* Interrupt wait time timeout in system timer ticks */ + +#ifndef CONFIG_STM32_I2CTIMEOTICKS +# define CONFIG_STM32_I2CTIMEOTICKS \ + (SEC2TICK(CONFIG_STM32_I2CTIMEOSEC) + MSEC2TICK(CONFIG_STM32_I2CTIMEOMS)) +#endif + +#ifndef CONFIG_STM32_I2C_DYNTIMEO_STARTSTOP +# define CONFIG_STM32_I2C_DYNTIMEO_STARTSTOP TICK2USEC(CONFIG_STM32_I2CTIMEOTICKS) +#endif + +/* Macros to convert a I2C pin to a GPIO output */ + +#define I2C_OUTPUT (GPIO_OUTPUT | GPIO_FLOAT | GPIO_OPENDRAIN |\ + GPIO_SPEED_50MHz | GPIO_OUTPUT_SET) + +#define MKI2C_OUTPUT(p) (((p) & (GPIO_PORT_MASK | GPIO_PIN_MASK)) | I2C_OUTPUT) + +#define I2C_CR1_TXRX (I2C_CR1_RXIE | I2C_CR1_TXIE) +#define I2C_CR1_ALLINTS (I2C_CR1_TXRX | I2C_CR1_TCIE | I2C_CR1_ERRIE) + +/* Unused bit in I2c_ISR used to communicate a bad state has occurred in + * the isr processing + */ + +#define I2C_INT_BAD_STATE 0x8000000 + +/* I2C event tracing + * + * To enable tracing statements which show the details of the state machine + * enable the following configuration variable: + * + * CONFIG_I2C_TRACE + * + * Note: This facility uses syslog, which sends output to the console by + * default. No other debug configuration variables are required. + */ + +#ifndef CONFIG_I2C_TRACE +# define stm32_i2c_tracereset(p) +# define stm32_i2c_tracenew(p,s) +# define stm32_i2c_traceevent(p,e,a) +# define stm32_i2c_tracedump(p) +#endif + +#ifndef CONFIG_I2C_NTRACE +# define CONFIG_I2C_NTRACE 32 +#endif + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/* Interrupt state */ + +enum stm32_intstate_e +{ + INTSTATE_IDLE = 0, /* No I2C activity */ + INTSTATE_WAITING, /* Waiting for completion of interrupt activity */ + INTSTATE_DONE, /* Interrupt activity complete */ +}; + +/* Trace events */ + +enum stm32_trace_e +{ + I2CEVENT_NONE = 0, + I2CEVENT_STATE_ERROR, + I2CEVENT_ISR_SHUTDOWN, + I2CEVENT_ISR_CALL, + I2CEVENT_ISR_EMPTY_CALL, + I2CEVENT_MSG_HANDLING, + I2CEVENT_POLL_NOT_READY, + I2CEVENT_EMPTY_MSG, + I2CEVENT_START, + I2CEVENT_ADDRESS_ACKED, + I2CEVENT_ADDRESS_NACKED, + I2CEVENT_NACK, + I2CEVENT_READ, + I2CEVENT_READ_ERROR, + I2CEVENT_WRITE_TO_DR, + I2CEVENT_WRITE_STOP, + I2CEVENT_WRITE_RESTART, + I2CEVENT_WRITE_NO_RESTART, + I2CEVENT_WRITE_ERROR, + I2CEVENT_WRITE_FLAG_ERROR, + I2CEVENT_TC_RESTART, + I2CEVENT_TC_NO_RESTART +}; + +/* Trace data */ + +struct stm32_trace_s +{ + uint32_t status; /* I2C 32-bit SR2|SR1 status */ + uint32_t count; /* Interrupt count when status change */ + enum stm32_intstate_e event; /* Last event that occurred with this status */ + uint32_t parm; /* Parameter associated with the event */ + clock_t time; /* First of event or first status */ +}; + +/* I2C Device hardware configuration */ + +struct stm32_i2c_config_s +{ + uint32_t base; /* I2C base address */ + uint32_t clk_bit; /* Clock enable bit */ + uint32_t reset_bit; /* Reset bit */ + uint32_t scl_pin; /* GPIO configuration for SCL as SCL */ + uint32_t sda_pin; /* GPIO configuration for SDA as SDA */ +#ifndef CONFIG_I2C_POLLED + uint32_t ev_irq; /* Event IRQ */ + uint32_t er_irq; /* Error IRQ */ +#endif +}; + +/* I2C Device Private Data */ + +struct stm32_i2c_priv_s +{ + /* Port configuration */ + + const struct stm32_i2c_config_s *config; + + int refs; /* Reference count */ + mutex_t lock; /* Mutual exclusion mutex */ +#ifndef CONFIG_I2C_POLLED + sem_t sem_isr; /* Interrupt wait semaphore */ +#endif + volatile uint8_t intstate; /* Interrupt handshake (see enum stm32_intstate_e) */ + + uint8_t msgc; /* Message count */ + struct i2c_msg_s *msgv; /* Message list */ + uint8_t *ptr; /* Current message buffer */ + uint32_t frequency; /* Current I2C frequency */ + int dcnt; /* Current message bytes remaining to transfer */ + uint16_t flags; /* Current message flags */ + bool astart; /* START sent */ + + /* I2C trace support */ + +#ifdef CONFIG_I2C_TRACE + int tndx; /* Trace array index */ + clock_t start_time; /* Time when the trace was started */ + + /* The actual trace data */ + + struct stm32_trace_s trace[CONFIG_I2C_NTRACE]; +#endif + + uint32_t status; /* End of transfer SR2|SR1 status */ + +#ifdef CONFIG_PM + struct pm_callback_s pm_cb; /* PM callbacks */ +#endif +}; + +/* I2C Device, Instance */ + +struct stm32_i2c_inst_s +{ + const struct i2c_ops_s *ops; /* Standard I2C operations */ + struct stm32_i2c_priv_s *priv; /* Common driver private data structure */ +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +static inline uint16_t stm32_i2c_getreg(struct stm32_i2c_priv_s *priv, + uint8_t offset); +static inline void stm32_i2c_putreg(struct stm32_i2c_priv_s *priv, + uint8_t offset, uint16_t value); +static inline void stm32_i2c_putreg32(struct stm32_i2c_priv_s *priv, + uint8_t offset, uint32_t value); +static inline void stm32_i2c_modifyreg32(struct stm32_i2c_priv_s *priv, + uint8_t offset, uint32_t clearbits, + uint32_t setbits); +#ifdef CONFIG_STM32_I2C_DYNTIMEO +static uint32_t stm32_i2c_toticks(int msgc, struct i2c_msg_s *msgs); +#endif /* CONFIG_STM32_I2C_DYNTIMEO */ +static inline int stm32_i2c_sem_waitdone(struct stm32_i2c_priv_s *priv); +static inline void stm32_i2c_sem_waitstop(struct stm32_i2c_priv_s *priv); +#ifdef CONFIG_I2C_TRACE +static void stm32_i2c_tracereset(struct stm32_i2c_priv_s *priv); +static void stm32_i2c_tracenew(struct stm32_i2c_priv_s *priv, + uint32_t status); +static void stm32_i2c_traceevent(struct stm32_i2c_priv_s *priv, + enum stm32_trace_e event, uint32_t parm); +static void stm32_i2c_tracedump(struct stm32_i2c_priv_s *priv); +#endif /* CONFIG_I2C_TRACE */ +static void stm32_i2c_setclock(struct stm32_i2c_priv_s *priv, + uint32_t frequency); +static inline void stm32_i2c_sendstart(struct stm32_i2c_priv_s *priv); +static inline void stm32_i2c_sendstop(struct stm32_i2c_priv_s *priv); +static inline +uint32_t stm32_i2c_getstatus(struct stm32_i2c_priv_s *priv); +static int stm32_i2c_isr_process(struct stm32_i2c_priv_s *priv); +#ifndef CONFIG_I2C_POLLED +static int stm32_i2c_isr(int irq, void *context, void *arg); +#endif +static int stm32_i2c_init(struct stm32_i2c_priv_s *priv); +static int stm32_i2c_deinit(struct stm32_i2c_priv_s *priv); + +static int stm32_i2c_process(struct i2c_master_s *dev, + struct i2c_msg_s *msgs, int count); +static int stm32_i2c_transfer(struct i2c_master_s *dev, + struct i2c_msg_s *msgs, int count); +#ifdef CONFIG_I2C_RESET +static int stm32_i2c_reset(struct i2c_master_s *dev); +#endif +#ifdef CONFIG_PM +static int stm32_i2c_pm_prepare(struct pm_callback_s *cb, int domain, + enum pm_state_e pmstate); +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#ifdef CONFIG_STM32_I2C1 +static const struct stm32_i2c_config_s stm32_i2c1_config = +{ + .base = STM32_I2C1_BASE, + .clk_bit = RCC_APB1ENR_I2C1EN, + .reset_bit = RCC_APB1RSTR_I2C1RST, + .scl_pin = GPIO_I2C1_SCL, + .sda_pin = GPIO_I2C1_SDA, +#ifndef CONFIG_I2C_POLLED + .ev_irq = STM32_IRQ_I2C1EV, + .er_irq = STM32_IRQ_I2C1ER +#endif +}; + +static struct stm32_i2c_priv_s stm32_i2c1_priv = +{ + .config = &stm32_i2c1_config, + .refs = 0, + .lock = NXMUTEX_INITIALIZER, +#ifndef CONFIG_I2C_POLLED + .sem_isr = SEM_INITIALIZER(0), +#endif + .intstate = INTSTATE_IDLE, + .msgc = 0, + .msgv = NULL, + .ptr = NULL, + .frequency = 0, + .dcnt = 0, + .flags = 0, + .status = 0, +#ifdef CONFIG_PM + .pm_cb.prepare = stm32_i2c_pm_prepare, +#endif +}; +#endif + +#ifdef CONFIG_STM32_I2C2 +static const struct stm32_i2c_config_s stm32_i2c2_config = +{ + .base = STM32_I2C2_BASE, + .clk_bit = RCC_APB1ENR_I2C2EN, + .reset_bit = RCC_APB1RSTR_I2C2RST, + .scl_pin = GPIO_I2C2_SCL, + .sda_pin = GPIO_I2C2_SDA, +#ifndef CONFIG_I2C_POLLED + .ev_irq = STM32_IRQ_I2C2EV, + .er_irq = STM32_IRQ_I2C2ER +#endif +}; + +static struct stm32_i2c_priv_s stm32_i2c2_priv = +{ + .config = &stm32_i2c2_config, + .refs = 0, + .lock = NXMUTEX_INITIALIZER, +#ifndef CONFIG_I2C_POLLED + .sem_isr = SEM_INITIALIZER(0), +#endif + .intstate = INTSTATE_IDLE, + .msgc = 0, + .msgv = NULL, + .ptr = NULL, + .frequency = 0, + .dcnt = 0, + .flags = 0, + .status = 0, +#ifdef CONFIG_PM + .pm_cb.prepare = stm32_i2c_pm_prepare, +#endif +}; +#endif + +#ifdef CONFIG_STM32_I2C3 +static const struct stm32_i2c_config_s stm32_i2c3_config = +{ + .base = STM32_I2C3_BASE, + .clk_bit = RCC_APB1ENR_I2C3EN, + .reset_bit = RCC_APB1RSTR_I2C3RST, + .scl_pin = GPIO_I2C3_SCL, + .sda_pin = GPIO_I2C3_SDA, +#ifndef CONFIG_I2C_POLLED + .ev_irq = STM32_IRQ_I2C3EV, + .er_irq = STM32_IRQ_I2C3ER +#endif +}; + +static struct stm32_i2c_priv_s stm32_i2c3_priv = +{ + .config = &stm32_i2c3_config, + .refs = 0, + .lock = NXMUTEX_INITIALIZER, +#ifndef CONFIG_I2C_POLLED + .sem_isr = SEM_INITIALIZER(0), +#endif + .intstate = INTSTATE_IDLE, + .msgc = 0, + .msgv = NULL, + .ptr = NULL, + .frequency = 0, + .dcnt = 0, + .flags = 0, + .status = 0, +#ifdef CONFIG_PM + .pm_cb.prepare = stm32_i2c_pm_prepare, +#endif +}; +#endif + +#ifdef CONFIG_STM32_I2C4 +static const struct stm32_i2c_config_s stm32_i2c4_config = +{ + .base = STM32_I2C4_BASE, + .clk_bit = RCC_APB1ENR_I2C4EN, + .reset_bit = RCC_APB1RSTR_I2C4RST, + .scl_pin = GPIO_I2C4_SCL, + .sda_pin = GPIO_I2C4_SDA, +#ifndef CONFIG_I2C_POLLED + .ev_irq = STM32_IRQ_I2C4EV, + .er_irq = STM32_IRQ_I2C4ER +#endif +}; + +static struct stm32_i2c_priv_s stm32_i2c4_priv = +{ + .config = &stm32_i2c4_config, + .refs = 0, + .lock = NXMUTEX_INITIALIZER, +#ifndef CONFIG_I2C_POLLED + .sem_isr = SEM_INITIALIZER(0), +#endif + .intstate = INTSTATE_IDLE, + .msgc = 0, + .msgv = NULL, + .ptr = NULL, + .frequency = 0, + .dcnt = 0, + .flags = 0, + .status = 0, +#ifdef CONFIG_PM + .pm_cb.prepare = stm32_i2c_pm_prepare, +#endif +}; +#endif + +/* Device Structures, Instantiation */ + +static const struct i2c_ops_s stm32_i2c_ops = +{ + .transfer = stm32_i2c_transfer, +#ifdef CONFIG_I2C_RESET + .reset = stm32_i2c_reset, +#endif +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_i2c_getreg + * + * Description: + * Get a 16-bit register value by offset + * + ****************************************************************************/ + +static inline uint16_t stm32_i2c_getreg(struct stm32_i2c_priv_s *priv, + uint8_t offset) +{ + return getreg16(priv->config->base + offset); +} + +/**************************************************************************** + * Name: stm32_i2c_getreg32 + * + * Description: + * Get a 32-bit register value by offset + * + ****************************************************************************/ + +static inline uint32_t stm32_i2c_getreg32(struct stm32_i2c_priv_s *priv, + uint8_t offset) +{ + return getreg32(priv->config->base + offset); +} + +/**************************************************************************** + * Name: stm32_i2c_putreg + * + * Description: + * Put a 16-bit register value by offset + * + ****************************************************************************/ + +static inline void stm32_i2c_putreg(struct stm32_i2c_priv_s *priv, + uint8_t offset, uint16_t value) +{ + putreg16(value, priv->config->base + offset); +} + +/**************************************************************************** + * Name: stm32_i2c_putreg32 + * + * Description: + * Put a 32-bit register value by offset + * + ****************************************************************************/ + +static inline void stm32_i2c_putreg32(struct stm32_i2c_priv_s *priv, + uint8_t offset, uint32_t value) +{ + putreg32(value, priv->config->base + offset); +} + +/**************************************************************************** + * Name: stm32_i2c_modifyreg32 + * + * Description: + * Modify a 32-bit register value by offset + * + ****************************************************************************/ + +static inline void stm32_i2c_modifyreg32(struct stm32_i2c_priv_s *priv, + uint8_t offset, uint32_t clearbits, + uint32_t setbits) +{ + modifyreg32(priv->config->base + offset, clearbits, setbits); +} + +/**************************************************************************** + * Name: stm32_i2c_toticks + * + * Description: + * Return a micro-second delay based on the number of bytes left to be + * processed. + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_I2C_DYNTIMEO +static uint32_t stm32_i2c_toticks(int msgc, struct i2c_msg_s *msgs) +{ + size_t bytecount = 0; + int i; + + /* Count the number of bytes left to process */ + + for (i = 0; i < msgc; i++) + { + bytecount += msgs[i].length; + } + + /* Then return a number of microseconds based on a user provided scaling + * factor. + */ + + return USEC2TICK(CONFIG_STM32_I2C_DYNTIMEO_USECPERBYTE * bytecount); +} +#endif + +/**************************************************************************** + * Name: stm32_i2c_enableinterrupts + * + * Description: + * Enable I2C interrupts + * + ****************************************************************************/ + +#ifndef CONFIG_I2C_POLLED +static inline void stm32_i2c_enableinterrupts(struct stm32_i2c_priv_s *priv) +{ + stm32_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, 0, + (I2C_CR1_TXRX | I2C_CR1_NACKIE)); +} +#endif + +/**************************************************************************** + * Name: stm32_i2c_sem_waitdone + * + * Description: + * Wait for a transfer to complete + * + * There are two versions of this function. The first is included when using + * interrupts while the second is used if polling (CONFIG_I2C_POLLED=y). + * + ****************************************************************************/ + +#ifndef CONFIG_I2C_POLLED +static inline int stm32_i2c_sem_waitdone(struct stm32_i2c_priv_s *priv) +{ + irqstate_t flags; + int ret; + + flags = enter_critical_section(); + + /* Enable I2C interrupts */ + + /* The TXIE and RXIE interrupts are enabled initially in stm32_i2c_process. + * The remainder of the interrupts, including error-related, are enabled + * here. + */ + + stm32_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, 0, + (I2C_CR1_ALLINTS & ~I2C_CR1_TXRX)); + + /* Signal the interrupt handler that we are waiting */ + + priv->intstate = INTSTATE_WAITING; + do + { + /* Wait until either the transfer is complete or the timeout expires */ + +#ifdef CONFIG_STM32_I2C_DYNTIMEO + ret = nxsem_tickwait_uninterruptible(&priv->sem_isr, + stm32_i2c_toticks(priv->msgc, priv->msgv)); +#else + ret = nxsem_tickwait_uninterruptible(&priv->sem_isr, + CONFIG_STM32_I2CTIMEOTICKS); +#endif + if (ret < 0) + { + /* Break out of the loop on irrecoverable errors. This would + * include timeouts and mystery errors reported by + * nxsem_tickwait_uninterruptible. + */ + + break; + } + } + + /* Loop until the interrupt level transfer is complete. */ + + while (priv->intstate != INTSTATE_DONE); + + /* Set the interrupt state back to IDLE */ + + priv->intstate = INTSTATE_IDLE; + + /* Disable I2C interrupts */ + + stm32_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, I2C_CR1_ALLINTS, 0); + + leave_critical_section(flags); + return ret; +} +#else +static inline int stm32_i2c_sem_waitdone(struct stm32_i2c_priv_s *priv) +{ + clock_t timeout; + clock_t start; + clock_t elapsed; + int ret; + + /* Get the timeout value */ + +#ifdef CONFIG_STM32_I2C_DYNTIMEO + timeout = stm32_i2c_toticks(priv->msgc, priv->msgv); +#else + timeout = CONFIG_STM32_I2CTIMEOTICKS; +#endif + + /* Signal the interrupt handler that we are waiting. NOTE: Interrupts + * are currently disabled but will be temporarily re-enabled below when + * nxsem_tickwait_uninterruptible() sleeps. + */ + + priv->intstate = INTSTATE_WAITING; + start = clock_systime_ticks(); + + do + { + /* Calculate the elapsed time */ + + elapsed = clock_systime_ticks() - start; + + /* Poll by simply calling the timer interrupt handler until it + * reports that it is done. + */ + + stm32_i2c_isr_process(priv); + } + + /* Loop until the transfer is complete. */ + + while (priv->intstate != INTSTATE_DONE && elapsed < timeout); + + i2cinfo("intstate: %d elapsed: %ld threshold: %ld status:" + " 0x%08" PRIx32 "\n", + priv->intstate, (long)elapsed, (long)timeout, priv->status); + + /* Set the interrupt state back to IDLE */ + + ret = priv->intstate == INTSTATE_DONE ? OK : -ETIMEDOUT; + priv->intstate = INTSTATE_IDLE; + return ret; +} +#endif + +/**************************************************************************** + * Name: stm32_i2c_set_7bit_address + * + * Description: + * + ****************************************************************************/ + +static inline void +stm32_i2c_set_7bit_address(struct stm32_i2c_priv_s *priv) +{ + stm32_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, I2C_CR2_SADD7_MASK, + ((priv->msgv->addr & 0x7f) << I2C_CR2_SADD7_SHIFT)); +} + +/**************************************************************************** + * Name: stm32_i2c_set_bytes_to_transfer + * + * Description: + * + ****************************************************************************/ + +static inline void +stm32_i2c_set_bytes_to_transfer(struct stm32_i2c_priv_s *priv, + uint8_t n_bytes) +{ + stm32_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, I2C_CR2_NBYTES_MASK, + (n_bytes << I2C_CR2_NBYTES_SHIFT)); +} + +/**************************************************************************** + * Name: stm32_i2c_set_write_transfer_dir + * + * Description: + * + ****************************************************************************/ + +static inline void +stm32_i2c_set_write_transfer_dir(struct stm32_i2c_priv_s *priv) +{ + stm32_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, I2C_CR2_RD_WRN, 0); +} + +/**************************************************************************** + * Name: stm32_i2c_set_read_transfer_dir + * + * Description: + * + ****************************************************************************/ + +static inline void +stm32_i2c_set_read_transfer_dir(struct stm32_i2c_priv_s *priv) +{ + stm32_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, 0, I2C_CR2_RD_WRN); +} + +/**************************************************************************** + * Name: stm32_i2c_enable_reload + * + * Description: + * + ****************************************************************************/ + +static inline void +stm32_i2c_enable_reload(struct stm32_i2c_priv_s *priv) +{ + stm32_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, 0, I2C_CR2_RELOAD); +} + +/**************************************************************************** + * Name: stm32_i2c_disable_reload + * + * Description: + * + ****************************************************************************/ + +static inline void +stm32_i2c_disable_reload(struct stm32_i2c_priv_s *priv) +{ + stm32_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, I2C_CR2_RELOAD, 0); +} + +/**************************************************************************** + * Name: stm32_i2c_sem_waitstop + * + * Description: + * Wait for a STOP to complete + * + ****************************************************************************/ + +static inline void stm32_i2c_sem_waitstop(struct stm32_i2c_priv_s *priv) +{ + clock_t start; + clock_t elapsed; + clock_t timeout; + uint32_t cr; + uint32_t sr; + + /* Select a timeout */ + +#ifdef CONFIG_STM32_I2C_DYNTIMEO + timeout = USEC2TICK(CONFIG_STM32_I2C_DYNTIMEO_STARTSTOP); +#else + timeout = CONFIG_STM32_I2CTIMEOTICKS; +#endif + + /* Wait as stop might still be in progress */ + + start = clock_systime_ticks(); + do + { + /* Calculate the elapsed time */ + + elapsed = clock_systime_ticks() - start; + + /* Check for STOP condition */ + + cr = stm32_i2c_getreg32(priv, STM32_I2C_CR2_OFFSET); + if ((cr & I2C_CR2_STOP) == 0) + { + return; + } + + /* Check for timeout error */ + + sr = stm32_i2c_getreg(priv, STM32_I2C_ISR_OFFSET); + if ((sr & I2C_INT_TIMEOUT) != 0) + { + return; + } + } + + /* Loop until the stop is complete or a timeout occurs. */ + + while (elapsed < timeout); + + /* If we get here then a timeout occurred with the STOP condition + * still pending. + */ + + i2cinfo("Timeout with CR: %04" PRIx32 " SR: %04" PRIx32 "\n", cr, sr); +} + +/**************************************************************************** + * Name: stm32_i2c_trace* + * + * Description: + * I2C trace instrumentation + * + ****************************************************************************/ + +#ifdef CONFIG_I2C_TRACE +static void stm32_i2c_traceclear(struct stm32_i2c_priv_s *priv) +{ + struct stm32_trace_s *trace = &priv->trace[priv->tndx]; + + trace->status = 0; /* I2C 32-bit status */ + trace->count = 0; /* Interrupt count when status change */ + trace->event = I2CEVENT_NONE; /* Last event that occurred with this status */ + trace->parm = 0; /* Parameter associated with the event */ + trace->time = 0; /* Time of first status or event */ +} + +static void stm32_i2c_tracereset(struct stm32_i2c_priv_s *priv) +{ + /* Reset the trace info for a new data collection */ + + priv->tndx = 0; + priv->start_time = clock_systime_ticks(); + stm32_i2c_traceclear(priv); +} + +static void stm32_i2c_tracenew(struct stm32_i2c_priv_s *priv, + uint32_t status) +{ + struct stm32_trace_s *trace = &priv->trace[priv->tndx]; + + /* Is the current entry uninitialized? Has the status changed? */ + + if (trace->count == 0 || status != trace->status) + { + /* Yes.. Was it the status changed? */ + + if (trace->count != 0) + { + /* Yes.. bump up the trace index + * (unless we are out of trace entries) + */ + + if (priv->tndx >= (CONFIG_I2C_NTRACE - 1)) + { + i2cerr("ERROR: Trace table overflow\n"); + return; + } + + priv->tndx++; + trace = &priv->trace[priv->tndx]; + } + + /* Initialize the new trace entry */ + + stm32_i2c_traceclear(priv); + trace->status = status; + trace->count = 1; + trace->time = clock_systime_ticks(); + } + else + { + /* Just increment the count of times that we have seen this status */ + + trace->count++; + } +} + +static void stm32_i2c_traceevent(struct stm32_i2c_priv_s *priv, + enum stm32_trace_e event, uint32_t parm) +{ + struct stm32_trace_s *trace; + + if (event != I2CEVENT_NONE) + { + trace = &priv->trace[priv->tndx]; + + /* Initialize the new trace entry */ + + trace->event = event; + trace->parm = parm; + + /* Bump up the trace index (unless we are out of trace entries) */ + + if (priv->tndx >= (CONFIG_I2C_NTRACE - 1)) + { + i2cerr("ERROR: Trace table overflow\n"); + return; + } + + priv->tndx++; + stm32_i2c_traceclear(priv); + } +} + +static void stm32_i2c_tracedump(struct stm32_i2c_priv_s *priv) +{ + struct stm32_trace_s *trace; + int i; + + syslog(LOG_DEBUG, "Elapsed time: %d\n", + (int)(clock_systime_ticks() - priv->start_time)); + + for (i = 0; i < priv->tndx; i++) + { + trace = &priv->trace[i]; + syslog(LOG_DEBUG, + "%2d. STATUS: %08" PRIx32 " COUNT: %3d EVENT: %2d PARM:" + " %08" PRIx32 " TIME: %d\n", + i + 1, trace->status, trace->count, trace->event, trace->parm, + (int)(trace->time - priv->start_time)); + } +} +#endif /* CONFIG_I2C_TRACE */ + +/**************************************************************************** + * Name: stm32_i2c_setclock + * + * Description: + * + * Sets the I2C bus clock frequency by configuring the I2C_TIMINGR register. + * + * This function supports bus clock frequencies of: + * + * 1000Khz (Fast Mode+) + * 400Khz (Fast Mode) + * 100Khz (Standard Mode) + * 10Khz (Standard Mode) + * + * Attempts to set a different frequency will quietly provision the default + * of 10Khz. + * + * The only differences between the various modes of operation (std, fast, + * fast+) are the bus clock speed and setup/hold times. Setup/hold times + * are specified as a MINIMUM time for the given mode, and naturally std + * mode has the longest minimum times. As a result, by provisioning + * setup/hold times for std mode they are also compatible with fast/fast+, + * though some performance degradation occurs in fast/fast+ as a result of + * the times being somewhat longer than strictly required. The values + * remain as they are because reliability is favored over performance. + * + * Clock Selection: + * + * The I2C peripheral clock can be provided by either PCLK1, SYSCLK or the + * HSI. + * + * PCLK1 >------|\ I2CCLK + * SYSCLK >------| |---------> + * HSI >------|/ + * + * HSI is the default and is always 8Mhz. + * + * SYSCLK can, in turn, be derived from the HSI, HSE, PPLCLK. + * + * HSI >------|\ + * | | SYSCLK + * PLL >------| |---------> + * | | + * HSE >------|/ + * + * + * References: + * + * App Note AN4235 and the associated software STSW-STM32126. + * + ****************************************************************************/ + +static void stm32_i2c_setclock(struct stm32_i2c_priv_s *priv, + uint32_t frequency) +{ + uint8_t presc; + uint8_t scl_delay; + uint8_t sda_delay; + uint8_t scl_h_period; + uint8_t scl_l_period; + + /* I2C peripheral must be disabled to update clocking configuration. + * This will SW reset the device. + */ + + stm32_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, I2C_CR1_PE, 0); + + if (frequency != priv->frequency) + { + /* The Speed and timing calculation are based on the following + * fI2CCLK = HSI and is 16Mhz + * Analog filter is on, + * Digital filter off + * Rise Time is 120 ns and fall is 10ns + * Mode is FastMode + */ + + if (frequency == 100000) + { + presc = 0; + scl_delay = 5; + sda_delay = 0; + scl_h_period = 61; + scl_l_period = 89; + } + else if (frequency == 400000) + { + presc = 0; + scl_delay = 3; + sda_delay = 0; + scl_h_period = 6; + scl_l_period = 24; + } + else if (frequency == 1000000) + { + presc = 0; + scl_delay = 2; + sda_delay = 0; + scl_h_period = 1; + scl_l_period = 5; + } + else + { + presc = 7; + scl_delay = 0; + sda_delay = 0; + scl_h_period = 35; + scl_l_period = 162; + } + + uint32_t timingr = + (presc << I2C_TIMINGR_PRESC_SHIFT) | + (scl_delay << I2C_TIMINGR_SCLDEL_SHIFT) | + (sda_delay << I2C_TIMINGR_SDADEL_SHIFT) | + (scl_h_period << I2C_TIMINGR_SCLH_SHIFT) | + (scl_l_period << I2C_TIMINGR_SCLL_SHIFT); + + stm32_i2c_putreg32(priv, STM32_I2C_TIMINGR_OFFSET, timingr); + priv->frequency = frequency; + } + + /* Enable I2C peripheral */ + + stm32_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, 0, I2C_CR1_PE); +} + +/**************************************************************************** + * Name: stm32_i2c_sendstart + * + * Description: + * Send the START condition / force Master mode + * + * A START condition in I2C consists of a single byte that contains both + * the 7 bit slave address and a read/write bit (0 = WRITE, 1 = READ). + * If the address is recognized by one of the slave devices that slave + * device will ACK the byte so that data transfers can begin. + * + * A RESTART (or repeated START per the I2CSPEC) is simply a START + * condition issued in the middle of a transfer (i.e. after the initial + * START and before a STOP). A RESTART sends a new address byte and R/W + * bit to the bus. A RESTART is optional in most cases but mandatory in + * the event the transfer direction is changed. + * + * Most of the time reading data from an I2C slave requires a WRITE of the + * subaddress followed by a READ (and hence a RESTART in between). Writing + * to an I2C slave typically requires only WRITE operations and hence no + * RESTARTs. + * + * This function is therefore called both at the beginning of a transfer + * (START) and at appropriate times during a transfer (RESTART). + * + ****************************************************************************/ + +static inline void stm32_i2c_sendstart(struct stm32_i2c_priv_s *priv) +{ + bool next_norestart = false; + + /* Set the private "current message" data used in protocol processing. + * + * ptr: A pointer to the start of the current message buffer. This is + * advanced after each byte in the current message is transferred. + * + * dcnt: A running counter of the bytes in the current message waiting to + * be transferred. This is decremented each time a byte is + * transferred. The hardware normally accepts a maximum of 255 bytes + * per transfer but can support more via the RELOAD mechanism. + * If dcnt initially exceeds 255, the RELOAD mechanism will be + * enabled automatically. + * + * flags: Used to characterize handling of the current message. + * + * The default flags value is 0 which specifies: + * + * - A transfer direction of WRITE (R/W bit = 0) + * - RESTARTs between all messages + * + * The following flags can be used to override this behavior as follows: + * + * - I2C_M_READ: Sets the transfer direction to READ (R/W bit = 1) + * - I2C_M_NOSTART: Prevents a RESTART from being issued prior to the + * transfer of the message (where allowed by the protocol). + * + */ + + priv->ptr = priv->msgv->buffer; + priv->dcnt = priv->msgv->length; + priv->flags = priv->msgv->flags; + + if ((priv->flags & I2C_M_NOSTART) == 0) + { + /* Flag the first byte as an address byte */ + + priv->astart = true; + } + + /* Enabling RELOAD allows the transfer of: + * + * - individual messages with a payload exceeding 255 bytes + * - multiple messages back to back without a RESTART in between + * + * so we enable it if either of those conditions exist and disable + * it otherwise. + */ + + /* Check if there are multiple messages and the next is a continuation */ + + if (priv->msgc > 1) + { + next_norestart = (((priv->msgv + 1)->flags & I2C_M_NOSTART) != 0); + } + + if (next_norestart || priv->dcnt > 255) + { + i2cinfo("RELOAD enabled: dcnt = %i msgc = %i\n", + priv->dcnt, priv->msgc); + stm32_i2c_enable_reload(priv); + } + else + { + i2cinfo("RELOAD disable: dcnt = %i msgc = %i\n", + priv->dcnt, priv->msgc); + stm32_i2c_disable_reload(priv); + } + + /* Set the number of bytes to transfer (I2C_CR2->NBYTES) to the number of + * bytes in the current message or 255, whichever is lower so as to not + * exceed the hardware maximum allowed. + */ + + if (priv->dcnt > 255) + { + stm32_i2c_set_bytes_to_transfer(priv, 255); + } + else + { + stm32_i2c_set_bytes_to_transfer(priv, priv->dcnt); + } + + /* Set the (7 bit) address. + * 10 bit addressing is not yet supported. + */ + + stm32_i2c_set_7bit_address(priv); + + /* The flag of the current message is used to determine the direction of + * transfer required for the current message. + */ + + if (priv->flags & I2C_M_READ) + { + stm32_i2c_set_read_transfer_dir(priv); + } + else + { + stm32_i2c_set_write_transfer_dir(priv); + } + + /* Set the I2C_CR2->START bit to 1 to instruct the hardware to send the + * START condition using the address and transfer direction data entered. + */ + + i2cinfo("Sending START: dcnt=%i msgc=%i flags=0x%04x\n", + priv->dcnt, priv->msgc, priv->flags); + + stm32_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, 0, I2C_CR2_START); +} + +/**************************************************************************** + * Name: stm32_i2c_sendstop + * + * Description: + * Send the STOP conditions + * + * A STOP condition can be requested by setting the STOP bit in the I2C_CR2 + * register. Setting the STOP bit clears the TC flag and the STOP condition + * is sent on the bus. + * + ****************************************************************************/ + +static inline void stm32_i2c_sendstop(struct stm32_i2c_priv_s *priv) +{ + i2cinfo("Sending STOP\n"); + stm32_i2c_traceevent(priv, I2CEVENT_WRITE_STOP, 0); + + stm32_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, 0, I2C_CR2_STOP); +} + +/**************************************************************************** + * Name: stm32_i2c_getstatus + * + * Description: + * Get 32-bit status (SR1 and SR2 combined) + * + ****************************************************************************/ + +static inline uint32_t stm32_i2c_getstatus(struct stm32_i2c_priv_s *priv) +{ + return getreg32(priv->config->base + STM32_I2C_ISR_OFFSET); +} + +/**************************************************************************** + * Name: stm32_i2c_clearinterrupts + * + * Description: + * Clear all interrupts + * + ****************************************************************************/ + +static inline void stm32_i2c_clearinterrupts(struct stm32_i2c_priv_s *priv) +{ + stm32_i2c_modifyreg32(priv, STM32_I2C_ICR_OFFSET, 0, I2C_ICR_CLEARMASK); +} + +/**************************************************************************** + * Name: stm32_i2c_isr_process + * + * Description: + * Common interrupt service routine (ISR) that handles I2C protocol logic. + * This is instantiated for each configured I2C interface + * (I2C1, I2C2, I2C3). + * + * This ISR is activated and deactivated by: + * + * stm32_i2c_process + * and + * stm32_i2c_waitdone + * + * Input Parameters: + * priv - The private struct of the I2C driver. + * + ****************************************************************************/ + +static int stm32_i2c_isr_process(struct stm32_i2c_priv_s *priv) +{ + uint32_t status; + + /* Get state of the I2C controller */ + + status = stm32_i2c_getreg32(priv, STM32_I2C_ISR_OFFSET); + + i2cinfo("ENTER: status = 0x%08" PRIx32 "\n", status); + + /* Update private version of the state assuming a good state */ + + priv->status = status & ~I2C_INT_BAD_STATE; + + /* If this is a new transmission set up the trace table accordingly */ + + stm32_i2c_tracenew(priv, status); + stm32_i2c_traceevent(priv, I2CEVENT_ISR_CALL, 0); + + /* ------------------- Start of I2C protocol handling ------------------ */ + + /* I2C protocol logic follows. It's organized in an if else chain such + * that only one mode of operation is executed every time the ISR is + * called. + * + * If you need to add additional states to support new features be sure + * they continue the chain (i.e. begin with "else if") and are placed + * before the empty call / error states at the end of the chain. + */ + + /* NACK Handling + * + * This branch is only triggered when the NACK (Not Acknowledge Received) + * interrupt occurs. This interrupt will only fire when the + * I2C_CR1->NACKIE bit is 1. + * + * I2C_ISR->NACKF is set by hardware when a NACK is received after a + * byte is transmitted and the slave fails to acknowledge it. This is + * the opposite of, and mutually exclusive to, the I2C_ISR->TXIS event. + * + * In response to the NACK the hardware automatically triggers generation + * of a STOP condition, terminating the transfer. The only valid response + * to this state is to exit the ISR and report the failure. + * + * To differentiate an "address NACK" from a NACK that might occur during + * the transfer of other bytes the "priv->astart" parameter is + * used. This flag is set to TRUE in sendstart() and set to FALSE when + * the first TXIS event is received, which would be after the first byte + * (the address) is transmitted successfully (acknowledged). + */ + + if (status & I2C_INT_NACK) + { + if (priv->astart == true) + { + /* NACK received on first (address) byte: address is invalid */ + + i2cinfo("NACK: Address invalid: dcnt=%i msgc=%i " + "status=0x%08" PRIx32 "\n", + priv->dcnt, priv->msgc, status); + stm32_i2c_traceevent(priv, I2CEVENT_ADDRESS_NACKED, + priv->msgv->addr); + } + else + { + /* NACK received on regular byte */ + + i2cinfo("NACK: NACK received: dcnt=%i msgc=%i " + "status=0x%08" PRIx32 "\n", + priv->dcnt, priv->msgc, status); + stm32_i2c_traceevent(priv, I2CEVENT_ADDRESS_NACKED, + priv->msgv->addr); + } + + /* Set flags to terminate message transmission: + * + * set message length to -1 to indicate last byte of message sent + * set message count to 0 to indicate no more messages to send + * + * As we fall through the logic in the ISR the message handling block + * will be triggered by these flags and signal the ISR to terminate. + */ + + priv->dcnt = -1; + priv->msgc = 0; + } + + /* Transmit Interrupt Status (TXIS) Handler + * + * This branch is only triggered when the TXIS interrupt occurs. This + * interrupt will only fire when the I2C_CR1->TXIE bit is 1. + * + * This indicates the transmit data register I2C_TXDR has been emptied + * following the successful transmission of a byte and slave + * acknowledgment. + * In this state the I2C_TXDR register is ready to accept another byte for + * transmission. The TXIS bit will be cleared automatically when the next + * byte is written to I2C_TXDR. + * + * The number of TXIS events during the transfer corresponds to NBYTES. + * + * The TXIS flag is not set when a NACK is received. + * + * When RELOAD is disabled (RELOAD=0) and NBYTES data have been + * transferred: + * + * - In Automatic End Mode (AUTOEND=1), a STOP is automatically sent. + * + * Note: Automatic End Mode is not currently supported. + * + * - In Software End Mode (AUTOEND=0), the TC event occurs and the SCL + * line is stretched low in order to allow software actions (STOP, + * RESTART). + * + * When RELOAD is enabled (RELOAD=1) and NBYTES bytes have been transferred + * a TCR event occurs instead and that handler simply updates NBYTES which + * causes TXIS events to continue. The process repeats until all bytes in + * the message have been transferred. + */ + + else if ((priv->flags & (I2C_M_READ)) == 0 && + (status & (I2C_ISR_TXIS)) != 0) + { + /* TXIS interrupt occurred, address valid, ready to transmit */ + + stm32_i2c_traceevent(priv, I2CEVENT_WRITE, 0); + i2cinfo("TXIS: ENTER dcnt = %i msgc = %i status 0x%08" PRIx32 "\n", + priv->dcnt, priv->msgc, status); + + /* The first event after the address byte is sent will be either TXIS + * or NACKF so it's safe to set the astart flag to false on + * the first TXIS event to indicate that it is no longer necessary to + * check for address validity. + */ + + if (priv->astart == true) + { + i2cinfo("TXIS: Address Valid\n"); + stm32_i2c_traceevent(priv, I2CEVENT_ADDRESS_ACKED, + priv->msgv->addr); + priv->astart = false; + } + + /* If one or more bytes in the current message are ready to transmit */ + + if (priv->dcnt > 0) + { + /* Prepare to transmit the current byte */ + + stm32_i2c_traceevent(priv, I2CEVENT_WRITE_TO_DR, priv->dcnt); + i2cinfo("TXIS: Write Data 0x%02x\n", *priv->ptr); + + /* Decrement byte counter */ + + priv->dcnt--; + + /* If we are about to transmit the last byte in the current + * message + */ + + if (priv->dcnt == 0) + { + /* If this is also the last message to send, disable RELOAD so + * TC fires next and issues STOP condition. If we don't do + * this TCR will fire next, and since there are no bytes to + * send we can't write NBYTES to clear TCR so it will fire + * forever. + */ + + if (priv->msgc == 1) + { + stm32_i2c_disable_reload(priv); + } + } + + /* Transmit current byte */ + + stm32_i2c_putreg(priv, STM32_I2C_TXDR_OFFSET, *priv->ptr); + + /* Advance to next byte */ + + priv->ptr++; + } + else + { + /* Unsupported state */ + + i2cerr("ERROR: TXIS Unsupported state detected, dcnt=%i, " + "status 0x%08" PRIx32 "\n", + priv->dcnt, status); + stm32_i2c_traceevent(priv, I2CEVENT_WRITE_ERROR, 0); + + /* Indicate the bad state, + * so that on termination HW will be reset + */ + + priv->status |= I2C_INT_BAD_STATE; + } + + i2cinfo("TXIS: EXIT dcnt = %i msgc = %i status 0x%08" PRIx32 "\n", + priv->dcnt, priv->msgc, status); + } + + /* Receive Buffer Not Empty (RXNE) State Handler + * + * This branch is only triggered when the RXNE interrupt occurs. This + * interrupt will only fire when the I2C_CR1->RXIE bit is 1. + * + * This indicates data has been received from the bus and is waiting to + * be read from the I2C_RXDR register. When I2C_RXDR is read this bit + * is automatically cleared and then an ACK or NACK is sent depending on + * whether we have more bytes to receive. + * + * When RELOAD is disabled and bytes remain to be transferred an + * acknowledge is automatically sent on the bus and the RXNE events + * continue until the last byte is received. + * + * When RELOAD is disabled (RELOAD=0) and BYTES have been transferred: + * + * - In Automatic End Mode (AUTOEND=1), a NACK and a STOP are + * automatically sent after the last received byte. + * + * Note: Automatic End Mode is not currently supported. + * + * - In Software End Mode (AUTOEND=0), a NACK is automatically sent after + * the last received byte, the TC event occurs and the SCL line is + * stretched low in order to allow software actions (STOP, RESTART). + * + * When RELOAD is enabled (RELOAD=1) and NBYTES bytes have been transferred + * a TCR event occurs and that handler simply updates NBYTES which causes + * RXNE events to continue until all bytes have been transferred. + */ + + else if ((priv->flags & (I2C_M_READ)) != 0 && (status & I2C_ISR_RXNE) != 0) + { + /* When read flag is set and the receive buffer is not empty + * (RXNE is set) then the driver can read from the data register. + */ + + stm32_i2c_traceevent(priv, I2CEVENT_READ, 0); + i2cinfo("RXNE: ENTER dcnt = %i msgc = %i status 0x%08" PRIx32 "\n", + priv->dcnt, priv->msgc, status); + + /* If more bytes in the current message */ + + if (priv->dcnt > 0) + { + stm32_i2c_traceevent(priv, I2CEVENT_RCVBYTE, priv->dcnt); + + /* No interrupts or context switches may occur in the following + * sequence. Otherwise, additional bytes may be received. + */ + +#ifdef CONFIG_I2C_POLLED + irqstate_t state = enter_critical_section(); +#endif + /* Receive a byte */ + + *priv->ptr = stm32_i2c_getreg(priv, STM32_I2C_RXDR_OFFSET); + + i2cinfo("RXNE: Read Data 0x%02x\n", *priv->ptr); + + /* Advance buffer to the next byte in the message */ + + priv->ptr++; + + /* Signal byte received */ + + priv->dcnt--; + +#ifdef CONFIG_I2C_POLLED + leave_critical_section(state); +#endif + } + else + { + /* Unsupported state */ + + stm32_i2c_traceevent(priv, I2CEVENT_READ_ERROR, 0); + status = stm32_i2c_getreg(priv, STM32_I2C_ISR_OFFSET); + i2cerr("ERROR: RXNE Unsupported state detected, dcnt=%i, " + "status 0x%08" PRIx32 "\n", + priv->dcnt, status); + + /* Set signals that will terminate ISR and wake waiting thread */ + + priv->status |= I2C_INT_BAD_STATE; + priv->dcnt = -1; + priv->msgc = 0; + } + + i2cinfo("RXNE: EXIT dcnt = %i msgc = %i status 0x%08" PRIx32 "\n", + priv->dcnt, priv->msgc, status); + } + + /* Transfer Complete (TC) State Handler + * + * This branch is only triggered when the TC interrupt occurs. This + * interrupt will only fire when: + * + * I2C_CR1->TCIE = 1 (Transfer Complete Interrupts Enabled) + * I2C_CR2->RELOAD = 0 (Reload Mode Disabled) + * I2C_CR2->AUTOEND = 0 (Autoend Mode Disabled, i.e. Software End Mode) + * + * This event indicates that the number of bytes initially defined + * in NBYTES, meaning, the number of bytes in the current message + * (priv->dcnt) has been successfully transmitted or received. + * + * When the TC interrupt occurs we have two choices to clear it and + * move on, regardless of the transfer direction: + * + * - if more messages follow, perform a repeated START if required + * and then fall through to transmit or receive the next message. + * + * - if no messages follow, perform a STOP and set flags needed to + * exit the ISR. + * + * The fact that the hardware must either RESTART or STOP when a TC + * event occurs explains why, when messages must be sent back to back + * (i.e. without a restart by specifying the I2C_M_NOSTART flag), + * RELOAD mode must be enabled and TCR event(s) must be generated + * instead. See the TCR handler for more. + */ + + else if ((status & I2C_ISR_TC) != 0) + { + i2cinfo("TC: ENTER dcnt = %i msgc = %i status 0x%08" PRIx32 "\n", + priv->dcnt, priv->msgc, status); + + /* Prior message has been sent successfully. Or there could have + * been an error that set msgc to 0; So test for that case as + * we do not want to decrement msgc less then zero nor move msgv + * past the last message. + */ + + if (priv->msgc > 0) + { + priv->msgc--; + } + + /* Are there additional messages remain to be transmitted / received? */ + + if (priv->msgc > 0) + { + i2cinfo("TC: RESTART: dcnt=%i, msgc=%i\n", + priv->dcnt, priv->msgc); + stm32_i2c_traceevent(priv, I2CEVENT_TC_NO_RESTART, priv->msgc); + + /* Issue a START condition. + * + * Note that the first thing sendstart does is update the + * private structure "current message" data (ptr, dcnt, flags) + * so they all reflect the next message in the list so we + * update msgv before we get there. + */ + + /* Advance to the next message in the list */ + + priv->msgv++; + + stm32_i2c_sendstart(priv); + } + else + { + /* Issue a STOP conditions. + * + * No additional messages to transmit / receive, so the + * transfer is indeed complete. Nothing else to do but + * issue a STOP and exit. + */ + + i2cinfo("TC: STOP: dcnt=%i msgc=%i\n", + priv->dcnt, priv->msgc); + stm32_i2c_traceevent(priv, I2CEVENT_STOP, priv->dcnt); + + stm32_i2c_sendstop(priv); + + /* Set signals that will terminate ISR and wake waiting thread */ + + priv->dcnt = -1; + priv->msgc = 0; + } + + i2cinfo("TC: EXIT dcnt = %i msgc = %i status 0x%08" PRIx32 "\n", + priv->dcnt, priv->msgc, status); + } + + /* Transfer Complete (Reload) State Handler + * + * This branch is only triggered when the TCR interrupt occurs. This + * interrupt will only fire when: + * + * I2C_CR1->TCIE = 1 (Transfer Complete Interrupts Enabled) + * I2C_CR2->RELOAD = 1 (Reload Mode Active) + * I2C_CR2->AUTOEND = 0 (Autoend Mode Disabled, i.e. Software End Mode) + * + * This is similar to the TC event except that TCR assumes that additional + * bytes are available to transfer. So despite what its name might imply + * the transfer really isn't complete. + * + * There are two reasons RELOAD would be enabled: + * + * 1) We're trying to send a message with a payload greater than 255 + * bytes. + * 2) We're trying to send messages back to back, regardless of their + * payload size, to avoid a RESTART (i.e. I2C_M_NOSTART flag is set). + * + * These conditions may be true simultaneously, as would be the case if + * we're sending multiple messages with payloads > 255 bytes. So we + * only advance to the next message if we arrive here and dcnt is 0, + * meaning, we're finished with the last message and ready to move to + * the next. + * + * This logic supports the transfer of bytes limited only by the size of + * the i2c_msg_s length variable. The SCL line will be stretched low + * until NBYTES is written with a non-zero value, allowing the transfer + * to continue. + * + * TODO: RESTARTs are required by the I2CSPEC if the next message transfer + * direction changes. Right now the NORESTART flag overrides this + * behavior. May have to introduce logic to issue sendstart, assuming it's + * legal with the hardware in the TCR state. + */ + + else if ((status & I2C_ISR_TCR) != 0) + { + i2cinfo("TCR: ENTER dcnt = %i msgc = %i status 0x%08" PRIx32 "\n", + priv->dcnt, priv->msgc, status); + + /* If no more bytes in the current message to transfer */ + + if (priv->dcnt == 0) + { + /* Prior message has been sent successfully */ + + priv->msgc--; + + /* Advance to the next message in the list */ + + priv->msgv++; + + /* Update current message data */ + + priv->ptr = priv->msgv->buffer; + priv->dcnt = priv->msgv->length; + priv->flags = priv->msgv->flags; + + /* If this is the last message, disable reload so the + * TC event fires next time. + */ + + if (priv->msgc == 0) + { + i2cinfo("TCR: DISABLE RELOAD: dcnt = %i msgc = %i\n", + priv->dcnt, priv->msgc); + + stm32_i2c_disable_reload(priv); + } + + /* Update NBYTES with length of current message */ + + i2cinfo("TCR: NEXT MSG dcnt = %i msgc = %i\n", + priv->dcnt, priv->msgc); + + stm32_i2c_set_bytes_to_transfer(priv, priv->dcnt); + } + else + { + /* More bytes in the current (greater than 255 byte payload + * length) message, so set NBYTES according to the bytes + * remaining in the message, up to a maximum each cycle of 255. + */ + + if (priv->dcnt > 255) + { + i2cinfo( + "TCR: ENABLE RELOAD: NBYTES = 255 dcnt = %i msgc = %i\n", + priv->dcnt, priv->msgc); + + /* More than 255 bytes to transfer so the RELOAD bit is + * set in order to generate a TCR event rather than a TC + * event when 255 bytes are successfully transferred. + * This forces us to return here to update NBYTES and + * continue until NBYTES is set to less than 255 bytes, + * at which point RELOAD will be disabled and a TC + * event will (eventually) follow to officially terminate + * the transfer. + */ + + stm32_i2c_enable_reload(priv); + + stm32_i2c_set_bytes_to_transfer(priv, 255); + } + else + { + /* Less than 255 bytes left to transfer, which means we'll + * complete the transfer of all bytes in the current message + * the next time around. + * + * This means we need to disable the RELOAD functionality so + * we receive a TC event next time which will allow us to + * either RESTART and continue sending the contents of the + * next message or send a STOP condition and exit the ISR. + */ + + i2cinfo("TCR: DISABLE RELOAD: NBYTES = dcnt = %i msgc = %i\n", + priv->dcnt, priv->msgc); + + stm32_i2c_set_bytes_to_transfer(priv, priv->dcnt); + + stm32_i2c_disable_reload(priv); + } + + i2cinfo("TCR: EXIT dcnt = %i msgc = %i status 0x%08" PRIx32 "\n", + priv->dcnt, priv->msgc, status); + } + } + + /* Empty call handler + * + * Case to handle an empty call to the ISR where it has nothing to + * do and should exit immediately. + */ + + else if (priv->dcnt == -1 && priv->msgc == 0) + { + status = stm32_i2c_getreg(priv, STM32_I2C_ISR_OFFSET); + i2cwarn("WARNING: EMPTY CALL: Stopping ISR: status 0x%08" PRIx32 "\n", + status); + stm32_i2c_traceevent(priv, I2CEVENT_ISR_EMPTY_CALL, 0); + } + + /* Error handler + * + * We get to this branch only if we can't handle the current state. + * + * This can happen in interrupt based operation on ARLO & BUSY. + * + * This will happen during polled operation when the device is not + * in one of the supported states when polled. + */ + + else + { +#ifdef CONFIG_I2C_POLLED + stm32_i2c_traceevent(priv, I2CEVENT_POLL_DEV_NOT_RDY, 0); +#else + /* Read rest of the state */ + + status = stm32_i2c_getreg(priv, STM32_I2C_ISR_OFFSET); + + i2cerr("ERROR: Invalid state detected, status 0x%08" PRIx32 "\n", + status); + + /* set condition to terminate ISR and wake waiting thread */ + + priv->status |= I2C_INT_BAD_STATE; + priv->dcnt = -1; + priv->msgc = 0; + stm32_i2c_traceevent(priv, I2CEVENT_STATE_ERROR, 0); +#endif + } + + /* --------------------- End of I2C protocol handling ------------------ */ + + /* Message Handling + * + * Transmission of the whole message chain has been completed. We have to + * terminate the ISR and wake up stm32_i2c_process() that is waiting for + * the ISR cycle to handle the sending/receiving of the messages. + */ + + if (priv->dcnt == -1 && priv->msgc == 0) + { + i2cinfo("MSG: Shutting down I2C ISR\n"); + + stm32_i2c_traceevent(priv, I2CEVENT_ISR_SHUTDOWN, 0); + + /* Clear pointer to message content to reflect we are done + * with the current transaction. + */ + + priv->msgv = NULL; + +#ifdef CONFIG_I2C_POLLED + priv->intstate = INTSTATE_DONE; +#else + + /* We will update private state to capture NACK which is used in + * combination with the astart flag to report the type of NACK received + * (address vs data) to the upper layers once we exit the ISR. + * + * Note: status is captured prior to clearing interrupts because + * the NACKF flag will naturally be cleared by that process. + */ + + status = stm32_i2c_getreg32(priv, STM32_I2C_ISR_OFFSET); + + /* Clear all interrupts */ + + stm32_i2c_modifyreg32(priv, STM32_I2C_ICR_OFFSET, + 0, I2C_ICR_CLEARMASK); + + /* Was a bad state detected in the processing? */ + + if (priv->status & I2C_INT_BAD_STATE) + { + /* SW reset device */ + + stm32_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, I2C_CR1_PE, 0); + } + + /* Update private status from above sans I2C_INT_BAD_STATE */ + + priv->status = status; + + /* If a thread is waiting then inform it transfer is complete */ + + if (priv->intstate == INTSTATE_WAITING) + { + nxsem_post(&priv->sem_isr); + priv->intstate = INTSTATE_DONE; + } +#endif + } + + status = stm32_i2c_getreg32(priv, STM32_I2C_ISR_OFFSET); + i2cinfo("EXIT: status = 0x%08" PRIx32 "\n", status); + + return OK; +} + +/**************************************************************************** + * Name: stm32_i2c_isr + * + * Description: + * Common I2C interrupt service routine + * + ****************************************************************************/ + +#ifndef CONFIG_I2C_POLLED +static int stm32_i2c_isr(int irq, void *context, void *arg) +{ + struct stm32_i2c_priv_s *priv = (struct stm32_i2c_priv_s *)arg; + + DEBUGASSERT(priv != NULL); + return stm32_i2c_isr_process(priv); +} +#endif + +/**************************************************************************** + * Name: stm32_i2c_init + * + * Description: + * Setup the I2C hardware, ready for operation with defaults + * + ****************************************************************************/ + +static int stm32_i2c_init(struct stm32_i2c_priv_s *priv) +{ + /* Power-up and configure GPIOs */ + + /* Enable power and reset the peripheral */ + + modifyreg32(STM32_RCC_APB1ENR, 0, priv->config->clk_bit); + modifyreg32(STM32_RCC_APB1RSTR, 0, priv->config->reset_bit); + modifyreg32(STM32_RCC_APB1RSTR, priv->config->reset_bit, 0); + + /* Configure pins */ + + if (stm32_configgpio(priv->config->scl_pin) < 0) + { + return ERROR; + } + + if (stm32_configgpio(priv->config->sda_pin) < 0) + { + stm32_unconfiggpio(priv->config->scl_pin); + return ERROR; + } + +#ifndef CONFIG_I2C_POLLED + /* Attach error and event interrupts to the ISRs */ + + irq_attach(priv->config->ev_irq, stm32_i2c_isr, priv); + irq_attach(priv->config->er_irq, stm32_i2c_isr, priv); + up_enable_irq(priv->config->ev_irq); + up_enable_irq(priv->config->er_irq); +#endif + + /* TODO: + * - Provide means to set peripheral clock source via RCC_CFGR3_I2CxSW + * - Set to HSI by default, make Kconfig option + */ + + /* Force a frequency update */ + + priv->frequency = 0; + stm32_i2c_setclock(priv, 100000); + + return OK; +} + +/**************************************************************************** + * Name: stm32_i2c_deinit + * + * Description: + * Shutdown the I2C hardware + * + ****************************************************************************/ + +static int stm32_i2c_deinit(struct stm32_i2c_priv_s *priv) +{ + /* Disable I2C */ + + stm32_i2c_putreg32(priv, STM32_I2C_CR1_OFFSET, 0); + + /* Unconfigure GPIO pins */ + + stm32_unconfiggpio(priv->config->scl_pin); + stm32_unconfiggpio(priv->config->sda_pin); + +#ifndef CONFIG_I2C_POLLED + + /* Disable and detach interrupts */ + + up_disable_irq(priv->config->ev_irq); + up_disable_irq(priv->config->er_irq); + irq_detach(priv->config->ev_irq); + irq_detach(priv->config->er_irq); +#endif + + /* Disable clocking */ + + modifyreg32(STM32_RCC_APB1ENR, priv->config->clk_bit, 0); + + return OK; +} + +/**************************************************************************** + * Name: stm32_i2c_process + * + * Description: + * Common I2C transfer logic + * + * Initiates a master mode transaction on the I2C bus to transfer the + * provided messages to and from the slave devices. + * + ****************************************************************************/ + +static int stm32_i2c_process(struct i2c_master_s *dev, + struct i2c_msg_s *msgs, int count) +{ + struct stm32_i2c_inst_s *inst = (struct stm32_i2c_inst_s *)dev; + struct stm32_i2c_priv_s *priv = inst->priv; + uint32_t status = 0; + uint32_t cr1; + uint32_t cr2; + int errval = 0; + int waitrc = 0; + + DEBUGASSERT(count > 0); + + /* Wait for any STOP in progress */ + + stm32_i2c_sem_waitstop(priv); + + /* Clear any pending error interrupts */ + + stm32_i2c_clearinterrupts(priv); + + /* Old transfers are done */ + + priv->msgv = msgs; + priv->msgc = count; + + /* Reset I2C trace logic */ + + stm32_i2c_tracereset(priv); + + /* Set I2C clock frequency toggles I2C_CR1_PE performing a SW reset! */ + + stm32_i2c_setclock(priv, msgs->frequency); + + /* Trigger start condition, then the process moves into the ISR. I2C + * interrupts will be enabled within stm32_i2c_waitdone(). + */ + + priv->status = 0; + +#ifndef CONFIG_I2C_POLLED + /* Enable transmit and receive interrupts here so when we send the start + * condition below the ISR will fire if the data was sent and some + * response from the slave received. All other interrupts relevant to + * our needs are enabled in stm32_i2c_sem_waitdone() below. + */ + + stm32_i2c_enableinterrupts(priv); +#endif + + /* Trigger START condition generation, which also sends the slave address + * with read/write flag and the data in the first message + */ + + stm32_i2c_sendstart(priv); + + /* Wait for the ISR to tell us that the transfer is complete by attempting + * to grab the semaphore that is initially locked by the ISR. If the ISR + * does not release the lock so we can obtain it here prior to the end of + * the timeout period waitdone returns error and we report a timeout. + */ + + waitrc = stm32_i2c_sem_waitdone(priv); + + cr1 = stm32_i2c_getreg32(priv, STM32_I2C_CR1_OFFSET); + cr2 = stm32_i2c_getreg32(priv, STM32_I2C_CR2_OFFSET); +#if !defined(CONFIG_DEBUG_I2C) + UNUSED(cr1); + UNUSED(cr2); +#endif + + /* Status after a normal / good exit is usually 0x00000001, meaning the TXE + * bit is set. That occurs as a result of the I2C_TXDR register being + * empty, and it naturally will be after the last byte is transmitted. + * This bit is cleared when we attempt communications again and re-enable + * the peripheral. The priv->status field can hold additional information + * like a NACK, so we reset the status field to include that information. + */ + + status = stm32_i2c_getstatus(priv); + + /* The priv->status field can hold additional information like a NACK + * event so we include that information. + */ + + status = priv->status & 0xffffffff; + + if (waitrc < 0) + { + /* Connection timed out */ + + errval = ETIMEDOUT; + i2cerr("ERROR: Waitdone timed out CR1: 0x%08" PRIx32 + " CR2: 0x%08" PRIx32 " status: 0x%08" PRIx32 "\n", + cr1, cr2, status); + } + else + { + i2cinfo("Waitdone success: CR1: 0x%08" PRIx32 + " CR2: 0x%08" PRIx32 " status: 0x%08" PRIx32 "\n", + cr1, cr2, status); + } + + UNUSED(cr1); + UNUSED(cr2); + + i2cinfo("priv->status: 0x%08" PRIx32 "\n", priv->status); + + /* Check for error status conditions */ + + if ((status & (I2C_INT_BERR | + I2C_INT_ARLO | + I2C_INT_OVR | + I2C_INT_PECERR | + I2C_INT_TIMEOUT | + I2C_INT_NACK)) != 0) + + { + /* one or more errors in the mask are present */ + + if (status & I2C_INT_BERR) + { + /* Bus Error, ignore it because of errata (revision A,Z) */ + + i2cerr("ERROR: I2C Bus Error\n"); + + /* errval = EIO; */ + } + else if (status & I2C_INT_ARLO) + { + /* Arbitration Lost (master mode) */ + + i2cerr("ERROR: I2C Arbitration Lost\n"); + errval = EAGAIN; + } + + else if (status & I2C_INT_OVR) + { + /* Overrun/Underrun */ + + i2cerr("ERROR: I2C Overrun/Underrun\n"); + errval = EIO; + } + else if (status & I2C_INT_PECERR) + { + /* PEC Error in reception (SMBus Only) */ + + i2cerr("ERROR: I2C PEC Error\n"); + errval = EPROTO; + } + else if (status & I2C_INT_TIMEOUT) + { + /* Timeout or Tlow Error (SMBus Only) */ + + i2cerr("ERROR: I2C Timeout / Tlow Error\n"); + errval = ETIME; + } + else if (status & I2C_INT_NACK) + { + /* NACK Received, flag as "communication error on send" */ + + if (priv->astart == TRUE) + { + i2cwarn("WARNING: I2C Address NACK\n"); + errval = EADDRNOTAVAIL; + } + else + { + i2cwarn("WARNING: I2C Data NACK\n"); + errval = ECOMM; + } + } + else + { + /* Unrecognized error */ + + i2cerr("ERROR: I2C Unrecognized Error"); + errval = EINTR; + } + } + + /* This is not an error, but should not happen. The BUSY signal can be + * present if devices on the bus are in an odd state and need to be reset. + * NOTE: We will only see this busy indication if stm32_i2c_sem_waitdone() + * fails above; Otherwise it is cleared. + */ + + else if ((status & I2C_ISR_BUSY) != 0) + { + /* I2C Bus Busy + * + * This is a status condition rather than an error. + * + * We will only see this busy indication if stm32_i2c_sem_waitdone() + * fails above; Otherwise it is cleared by the hardware when the ISR + * wraps up the transfer with a STOP condition. + */ + + clock_t start = clock_systime_ticks(); + clock_t timeout = USEC2TICK(USEC_PER_SEC / priv->frequency) + 1; + + status = stm32_i2c_getstatus(priv); + + while (status & I2C_ISR_BUSY) + { + if ((clock_systime_ticks() - start) > timeout) + { + i2cerr("ERROR: I2C Bus busy"); + errval = EBUSY; + break; + } + + status = stm32_i2c_getstatus(priv); + } + } + + /* Dump the trace result */ + + stm32_i2c_tracedump(priv); + nxmutex_unlock(&priv->lock); + + return -errval; +} + +/**************************************************************************** + * Name: stm32_i2c_transfer + * + * Description: + * Generic I2C transfer function + * + ****************************************************************************/ + +static int stm32_i2c_transfer(struct i2c_master_s *dev, + struct i2c_msg_s *msgs, int count) +{ + struct stm32_i2c_priv_s *priv; + int ret; + + DEBUGASSERT(dev); + + /* Get I2C private structure */ + + priv = ((struct stm32_i2c_inst_s *)dev)->priv; + + /* Ensure that address or flags don't change meanwhile */ + + ret = nxmutex_lock(&priv->lock); + if (ret >= 0) + { + ret = stm32_i2c_process(dev, msgs, count); + } + + return ret; +} + +/**************************************************************************** + * Name: stm32_i2c_reset + * + * Description: + * Reset an I2C bus + * + ****************************************************************************/ + +#ifdef CONFIG_I2C_RESET +static int stm32_i2c_reset(struct i2c_master_s *dev) +{ + struct stm32_i2c_priv_s *priv; + unsigned int clock_count; + unsigned int stretch_count; + uint32_t scl_gpio; + uint32_t sda_gpio; + uint32_t frequency; + int ret; + + DEBUGASSERT(dev); + + /* Get I2C private structure */ + + priv = ((struct stm32_i2c_inst_s *)dev)->priv; + + /* Our caller must own a ref */ + + DEBUGASSERT(priv->refs > 0); + + /* Lock out other clients */ + + ret = nxmutex_lock(&priv->lock); + if (ret < 0) + { + return ret; + } + + ret = -EIO; + + /* Save the current frequency */ + + frequency = priv->frequency; + + /* De-init the port */ + + stm32_i2c_deinit(priv); + + /* Use GPIO configuration to un-wedge the bus */ + + scl_gpio = MKI2C_OUTPUT(priv->config->scl_pin); + sda_gpio = MKI2C_OUTPUT(priv->config->sda_pin); + + stm32_configgpio(sda_gpio); + stm32_configgpio(scl_gpio); + + /* Let SDA go high */ + + stm32_gpiowrite(sda_gpio, 1); + + /* Clock the bus until any slaves currently driving it let it go. */ + + clock_count = 0; + while (!stm32_gpioread(sda_gpio)) + { + /* Give up if we have tried too hard */ + + if (clock_count++ > 10) + { + goto out; + } + + /* Sniff to make sure that clock stretching has finished. + * + * If the bus never relaxes, the reset has failed. + */ + + stretch_count = 0; + while (!stm32_gpioread(scl_gpio)) + { + /* Give up if we have tried too hard */ + + if (stretch_count++ > 10) + { + goto out; + } + + up_udelay(10); + } + + /* Drive SCL low */ + + stm32_gpiowrite(scl_gpio, 0); + up_udelay(10); + + /* Drive SCL high again */ + + stm32_gpiowrite(scl_gpio, 1); + up_udelay(10); + } + + /* Generate a start followed by a stop to reset slave + * state machines. + */ + + stm32_gpiowrite(sda_gpio, 0); + up_udelay(10); + stm32_gpiowrite(scl_gpio, 0); + up_udelay(10); + stm32_gpiowrite(scl_gpio, 1); + up_udelay(10); + stm32_gpiowrite(sda_gpio, 1); + up_udelay(10); + + /* Revert the GPIO configuration. */ + + stm32_unconfiggpio(sda_gpio); + stm32_unconfiggpio(scl_gpio); + + /* Re-init the port */ + + stm32_i2c_init(priv); + + /* Restore the frequency */ + + stm32_i2c_setclock(priv, frequency); + ret = OK; + +out: + + /* Release the port for reuse by other clients */ + + nxmutex_unlock(&priv->lock); + return ret; +} +#endif /* CONFIG_I2C_RESET */ + +/**************************************************************************** + * Name: stm32_i2c_pm_prepare + * + * Description: + * Request the driver to prepare for a new power state. This is a + * warning that the system is about to enter into a new power state. The + * driver should begin whatever operations that may be required to enter + * power state. The driver may abort the state change mode by returning + * a non-zero value from the callback function. + * + * Input Parameters: + * cb - Returned to the driver. The driver version of the callback + * structure may include additional, driver-specific state + * data at the end of the structure. + * domain - Identifies the activity domain of the state change + * pmstate - Identifies the new PM state + * + * Returned Value: + * 0 (OK) means the event was successfully processed and that the driver + * is prepared for the PM state change. Non-zero means that the driver + * is not prepared to perform the tasks needed achieve this power setting + * and will cause the state change to be aborted. NOTE: The prepare + * method will also be recalled when reverting from lower back to higher + * power consumption modes (say because another driver refused a lower + * power state change). Drivers are not permitted to return non-zero + * values when reverting back to higher power consumption modes! + * + ****************************************************************************/ + +#ifdef CONFIG_PM +static int stm32_i2c_pm_prepare(struct pm_callback_s *cb, int domain, + enum pm_state_e pmstate) +{ + struct stm32_i2c_priv_s *priv = + (struct stm32_i2c_priv_s *)((char *)cb - + offsetof(struct stm32_i2c_priv_s, pm_cb)); + + /* Logic to prepare for a reduced power state goes here. */ + + switch (pmstate) + { + case PM_NORMAL: + case PM_IDLE: + break; + + case PM_STANDBY: + case PM_SLEEP: + + /* Check if exclusive lock for I2C bus is held. */ + + if (nxmutex_is_locked(&priv->lock)) + { + /* Exclusive lock is held, do not allow entry to deeper PM + * states. + */ + + return -EBUSY; + } + + break; + + default: + + /* Should not get here */ + + break; + } + + return OK; +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_i2cbus_initialize + * + * Description: + * Initialize one I2C bus + * + ****************************************************************************/ + +struct i2c_master_s *stm32_i2cbus_initialize(int port) +{ + struct stm32_i2c_priv_s *priv = NULL; /* private data of device with multiple instances */ + struct stm32_i2c_inst_s *inst = NULL; /* device, single instance */ + + /* Get I2C private structure */ + + switch (port) + { +#ifdef CONFIG_STM32_I2C1 + case 1: + priv = (struct stm32_i2c_priv_s *)&stm32_i2c1_priv; + break; +#endif +#ifdef CONFIG_STM32_I2C2 + case 2: + priv = (struct stm32_i2c_priv_s *)&stm32_i2c2_priv; + break; +#endif +#ifdef CONFIG_STM32_I2C3 + case 3: + priv = (struct stm32_i2c_priv_s *)&stm32_i2c3_priv; + break; +#endif +#ifdef CONFIG_STM32_I2C4 + case 4: + priv = (struct stm32_i2c_priv_s *)&stm32_i2c4_priv; + break; +#endif + default: + return NULL; + } + + /* Allocate instance */ + + if (!(inst = kmm_malloc(sizeof(struct stm32_i2c_inst_s)))) + { + return NULL; + } + + /* Initialize instance */ + + inst->ops = &stm32_i2c_ops; + inst->priv = priv; + + /* Init private data for the first time, increment refs count, + * power-up hardware and configure GPIOs. + */ + + nxmutex_lock(&priv->lock); + if (priv->refs++ == 0) + { + stm32_i2c_init(priv); + +#ifdef CONFIG_PM + /* Register to receive power management callbacks */ + + DEBUGVERIFY(pm_register(&priv->pm_cb)); +#endif + } + + nxmutex_unlock(&priv->lock); + return (struct i2c_master_s *)inst; +} + +/**************************************************************************** + * Name: stm32_i2cbus_uninitialize + * + * Description: + * Uninitialize an I2C bus + * + ****************************************************************************/ + +int stm32_i2cbus_uninitialize(struct i2c_master_s *dev) +{ + struct stm32_i2c_priv_s *priv; + + DEBUGASSERT(dev); + priv = ((struct stm32_i2c_inst_s *)dev)->priv; + + /* Decrement refs and check for underflow */ + + if (priv->refs == 0) + { + return ERROR; + } + + nxmutex_lock(&priv->lock); + if (--priv->refs) + { + nxmutex_unlock(&priv->lock); + kmm_free(dev); + return OK; + } + +#ifdef CONFIG_PM + /* Unregister power management callbacks */ + + pm_unregister(&priv->pm_cb); +#endif + + /* Disable power and other HW resource (GPIO's) */ + + stm32_i2c_deinit(priv); + nxmutex_unlock(&priv->lock); + + kmm_free(dev); + return OK; +} + +#endif /* CONFIG_STM32_I2C1 || CONFIG_STM32_I2C2 || \ + * CONFIG_STM32_I2C3 || CONFIG_STM32_I2C4 */ diff --git a/arch/arm/src/common/stm32/stm32_i2c_m3m4_v2_slave.c b/arch/arm/src/common/stm32/stm32_i2c_m3m4_v2_slave.c new file mode 100644 index 0000000000000..53ce3975f1673 --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_i2c_m3m4_v2_slave.c @@ -0,0 +1,793 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_i2c_m3m4_v2_slave.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + * TODO + * - DMA + * - SMBus adaptation + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include + +#include "arm_internal.h" +#include "hardware/stm32_pinmap.h" +#include "hardware/stm32_i2c_v2.h" +#include "stm32_gpio.h" +#include "stm32_rcc.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define I2C_CR1_ALLINTS (I2C_CR1_RXIE | I2C_CR1_TXIE | I2C_CR1_ADDRIE | \ + I2C_CR1_STOPIE) + +#ifdef CONFIG_STM32_I2C_SLAVE_USEWQ +# ifdef CONFIG_SCHED_HPWORK +# define I2CSWORK HPWORK +# endif + +# ifndef I2CSWORK +# ifdef CONFIG_SCHED_LPWORK +# define I2CSWORK LPWORK +# endif +# endif + +# ifndef I2CSWORK +# error "For correct operation, you should define LPWORK or HPWORK." +# endif +#endif + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +struct stm32_i2cslave_s +{ + const struct i2c_slaveops_s *ops; + int refs; + mutex_t lock; + uint32_t frequency; + uint32_t base; + uint32_t clk_bit; + uint32_t reset_bit; + uint32_t ev_irq; + uint32_t scl_pin; + uint32_t sda_pin; + const uint8_t *tx_buffer; + uint8_t *rx_buffer; + int rx_buflen; + int rx_curptr; + int tx_buflen; + int tx_curptr; + int rx_received; + i2c_slave_callback_t *callback; + void *callback_arg; + bool read; +#ifdef CONFIG_STM32_I2C_SLAVE_USEWQ + struct work_s irqwork; /* For deferring interrupt work to the wq */ +#endif +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +static int stm32_i2c_setup(struct i2c_slave_s *dev); +static int stm32_i2c_shutdown(struct i2c_slave_s *dev); +static int stm32_i2c_setownaddress(struct i2c_slave_s *dev, int addr, + int nbits); +static int stm32_i2c_write(struct i2c_slave_s *dev, const uint8_t *buffer, + int buflen); +static int stm32_i2c_read(struct i2c_slave_s *dev, uint8_t *buffer, + int buflen); +static int stm32_i2c_registercallback(struct i2c_slave_s *dev, + i2c_slave_callback_t *callback, + void *arg); +static int stm32_i2c_init(struct stm32_i2cslave_s *priv); +static int stm32_i2c_deinit(struct stm32_i2cslave_s *priv); +static int stm32_i2c_isr(int irq, void *context, void *arg); +static int stm32_i2c_isr_impl(struct stm32_i2cslave_s *priv); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static const struct i2c_slaveops_s stm32_i2cslave_ops = +{ + .setownaddress = stm32_i2c_setownaddress, + .write = stm32_i2c_write, + .read = stm32_i2c_read, + .registercallback = stm32_i2c_registercallback, + .setup = stm32_i2c_setup, + .shutdown = stm32_i2c_shutdown +}; + +#ifdef CONFIG_STM32_I2C1_SLAVE +static struct stm32_i2cslave_s stm32_i2c1_priv = +{ + .ops = &stm32_i2cslave_ops, + .refs = 0, + .lock = NXMUTEX_INITIALIZER, + .frequency = 0, + .base = STM32_I2C1_BASE, + .clk_bit = RCC_APB1ENR_I2C1EN, + .reset_bit = RCC_APB1RSTR_I2C1RST, + .ev_irq = STM32_IRQ_I2C1EV, + .scl_pin = GPIO_I2C1_SCL, + .sda_pin = GPIO_I2C1_SDA, + .tx_buffer = NULL, + .rx_buffer = NULL, + .rx_buflen = 0, + .rx_curptr = 0, + .tx_curptr = 0, +}; +#endif + +#ifdef CONFIG_STM32_I2C2_SLAVE +static struct stm32_i2cslave_s stm32_i2c2_priv = +{ + .ops = &stm32_i2cslave_ops, + .refs = 0, + .lock = NXMUTEX_INITIALIZER, + .frequency = 0, + .base = STM32_I2C2_BASE, + .clk_bit = RCC_APB1ENR_I2C2EN, + .reset_bit = RCC_APB1RSTR_I2C2RST, + .ev_irq = STM32_IRQ_I2C2EV, + .scl_pin = GPIO_I2C2_SCL, + .sda_pin = GPIO_I2C2_SDA, + .tx_buffer = NULL, + .rx_buffer = NULL, + .rx_buflen = 0, + .rx_curptr = 0, + .tx_curptr = 0, +}; +#endif + +#ifdef CONFIG_STM32_I2C3_SLAVE +static struct stm32_i2cslave_s stm32_i2c3_priv = +{ + .ops = &stm32_i2cslave_ops, + .refs = 0, + .lock = NXMUTEX_INITIALIZER, + .frequency = 0, + .base = STM32_I2C3_BASE, + .clk_bit = RCC_APB1ENR_I2C3EN, + .reset_bit = RCC_APB1RSTR_I2C3RST, + .ev_irq = STM32_IRQ_I2C3EV, + .scl_pin = GPIO_I2C3_SCL, + .sda_pin = GPIO_I2C3_SDA, + .tx_buffer = NULL, + .rx_buffer = NULL, + .rx_buflen = 0, + .rx_curptr = 0, + .tx_curptr = 0, +}; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_i2c_getreg + * + * Description: + * Get a 16-bit register value by offset + * + ****************************************************************************/ + +static inline uint16_t stm32_i2c_getreg(struct stm32_i2cslave_s *priv, + uint8_t offset) +{ + return getreg16(priv->base + offset); +} + +/**************************************************************************** + * Name: stm32_i2c_getreg32 + * + * Description: + * Get a 32-bit register value by offset + * + ****************************************************************************/ + +static inline uint32_t stm32_i2c_getreg32(struct stm32_i2cslave_s *priv, + uint8_t offset) +{ + return getreg32(priv->base + offset); +} + +/**************************************************************************** + * Name: stm32_i2c_putreg + * + * Description: + * Put a 16-bit register value by offset + * + ****************************************************************************/ + +static inline void stm32_i2c_putreg(struct stm32_i2cslave_s *priv, + uint8_t offset, uint16_t value) +{ + putreg16(value, priv->base + offset); +} + +/**************************************************************************** + * Name: stm32_i2c_putreg32 + * + * Description: + * Put a 32-bit register value by offset + * + ****************************************************************************/ + +static inline void stm32_i2c_putreg32(struct stm32_i2cslave_s *priv, + uint8_t offset, uint32_t value) +{ + putreg32(value, priv->base + offset); +} + +/**************************************************************************** + * Name: stm32_i2c_isr + * + * Description: + * Common I2C interrupt service routine + * + ****************************************************************************/ + +static int stm32_i2c_isr(int irq, void *context, void *arg) +{ + struct stm32_i2cslave_s *priv = (struct stm32_i2cslave_s *)arg; + DEBUGASSERT(priv != NULL); + return stm32_i2c_isr_impl(priv); +} + +/**************************************************************************** + * Name: stm32_i2c_rxdone_work + * + * Description: + * A routine for delegating frame reception information + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_I2C_SLAVE_USEWQ +static void stm32_i2c_rxdone_work(void *arg) +{ + struct stm32_i2cslave_s *priv = (struct stm32_i2cslave_s *)arg; + priv->callback(priv->callback_arg, I2CS_RX_COMPLETE, + priv->rx_curptr); +} +#endif + +/**************************************************************************** + * Name: stm32_i2c_rxdone_work + * + * Description: + * A routine for delegating tx frame information + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_I2C_SLAVE_USEWQ +static void stm32_i2c_txdone_work(void *arg) +{ + struct stm32_i2cslave_s *priv = (struct stm32_i2cslave_s *)arg; + priv->callback(priv->callback_arg, I2CS_TX_COMPLETE, + priv->tx_curptr); +} +#endif + +/**************************************************************************** + * Name: stm32_i2c_isr_impl + * + * Description: + * Interrupt handler + * + ****************************************************************************/ + +static int stm32_i2c_isr_impl(struct stm32_i2cslave_s *priv) +{ + volatile uint32_t isr; + volatile uint8_t rx; + volatile uint8_t tx; + + /* Get the status register first. */ + + isr = stm32_i2c_getreg32(priv, STM32_I2C_ISR_OFFSET); + + /* Was the TX completed? */ + + if ((isr & I2C_ISR_TXIS) != 0) + { + /* Check, if anything must be sent */ + + if (priv->tx_curptr < priv->tx_buflen - 1) + { + /* Yes... */ + + priv->tx_curptr++; + tx = priv->tx_buffer[priv->tx_curptr]; + } + else if (priv->tx_curptr == priv->tx_buflen - 1) + { + tx = CONFIG_STM32_I2C_SLAVE_DEFAULT_TX; + if (priv->callback) + { +#ifdef CONFIG_STM32_I2C_SLAVE_USEWQ + work_queue(I2CSWORK, &priv->irqwork, + stm32_i2c_txdone_work, priv, 0); +#else + priv->callback(priv->callback_arg, I2CS_TX_COMPLETE, + priv->tx_curptr); +#endif + } + } + else + { + /* No... Send the default value. */ + + tx = CONFIG_STM32_I2C_SLAVE_DEFAULT_TX; + } + + stm32_i2c_putreg(priv, STM32_I2C_TXDR_OFFSET, tx); + } + + /* Was a byte received? */ + + if ((isr & I2C_ISR_RXNE) != 0) + { + /* Write it if not overflowed. RXDR must be read to clear int. */ + + rx = stm32_i2c_getreg(priv, STM32_I2C_RXDR_OFFSET); + if (priv->rx_curptr < priv->rx_buflen) + { + priv->rx_buffer[priv->rx_curptr++] = rx; + } + } + + /* Was the stop condition detected? */ + + if ((isr & I2C_INT_STOP) != 0) + { + /* Clear the interrupt. */ + + stm32_i2c_putreg(priv, STM32_I2C_ICR_OFFSET, I2C_INT_STOP); + + /* If RX was present, notify the upper driver. */ + + if (priv->read) + { + if (priv->callback) + { +#ifdef CONFIG_STM32_I2C_SLAVE_USEWQ + work_queue(I2CSWORK, &priv->irqwork, + stm32_i2c_rxdone_work, priv, 0); +#else + priv->callback(priv->callback_arg, I2CS_RX_COMPLETE, + priv->rx_curptr); + priv->rx_curptr = 0; +#endif + } + } +#ifdef CONFIG_STM32_I2C_SLAVE_RETRANSFER + else + { + priv->tx_curptr = 0; + } +#endif + } + + /* Was an address matched? */ + + if ((isr & I2C_INT_ADDR) != 0) + { + /* Clear the address match flag. */ + + stm32_i2c_putreg(priv, STM32_I2C_ICR_OFFSET, I2C_INT_ADDR); + + /* Repeated Start */ + + if (priv->rx_curptr > 0 && priv->callback) + { +#ifdef CONFIG_STM32_I2C_SLAVE_USEWQ + work_queue(I2CSWORK, &priv->irqwork, + stm32_i2c_rxdone_work, priv, 0); +#else + priv->callback(priv->callback_arg, I2CS_RX_COMPLETE, + priv->rx_curptr); +#endif + } + + /* Check whether RX or TX should be done. */ + + if ((isr & I2C_ISR_DIR) != 0) + { + /* Write transfer. Flush the TX buffer by writing ISR_TXE. + * Then send any remaining data. Or send the default TX byte. + */ + + stm32_i2c_putreg32(priv, STM32_I2C_ISR_OFFSET, I2C_ISR_TXE); + + if (priv->tx_curptr < priv->tx_buflen) + { + tx = priv->tx_buffer[priv->tx_curptr]; + } + else + { + /* Nothing to be sent. */ + + tx = CONFIG_STM32_I2C_SLAVE_DEFAULT_TX; + } + + stm32_i2c_putreg(priv, STM32_I2C_TXDR_OFFSET, tx); + priv->read = false; + } + else + { + /* Initialize the reading. */ + + priv->read = true; + priv->rx_curptr = 0; + } + } + + return OK; +} + +/**************************************************************************** + * Name: stm32_i2c_setownaddress + * + * Description: + * Sets up the address of the I2C Slave + * + ****************************************************************************/ + +static int stm32_i2c_setownaddress(struct i2c_slave_s *dev, int addr, + int nbits) +{ + struct stm32_i2cslave_s *priv = (struct stm32_i2cslave_s *)dev; + uint16_t oar1; + uint32_t cr1; + + i2cinfo("SETOWNADDR %d\n", addr); + + /* STM32 supports up to 2 addresses the slave can respond to. + * However, NuttX supports the setting of only one address. + * Use only the first "OWN ADDRESS" (I2C_OAR1) + * Before this, reset the peripheral by disabling it. + * If the peripheral is launched for the first time, this does nothing. + */ + + cr1 = stm32_i2c_getreg32(priv, STM32_I2C_CR1_OFFSET); + stm32_i2c_putreg32(priv, STM32_I2C_CR1_OFFSET, + cr1 & ~(I2C_CR1_ALLINTS | I2C_CR1_PE)); + + /* Clear I2C_OAR1_OA1EN, then configure I2C_OAR1_OA1[9:0]. + * Afterwards, set I2C_OAR1_{OA1MODE, OA1EN}. + * According to i2c_slave_open in i2c_slave_driver.c, SETOWNADDRESS comes + * after SETUP. Therefore, enable the peripheral and RX and TX interrupts + * here. + * + * Attention: If a 10 bit address is used, all 10 bits are used. + * However, bits 7:1 are used (instead of 6:0) in the 7 bit mode. + * Therefore, the address must be shifted. + */ + + if (nbits == 10) + { + oar1 = ((uint16_t) addr) & 0x03ff; + oar1 |= I2C_OAR1_OA1MODE; + } + else if (nbits == 7) + { + oar1 = ((uint16_t) addr << 1) & 0x00fe; + } + else + { + /* Wrong nbits. */ + + return ERROR; + } + + /* Clear OA1EN (whole register can be cleared) */ + + stm32_i2c_putreg32(priv, STM32_I2C_OAR1_OFFSET, 0); + stm32_i2c_putreg32(priv, STM32_I2C_OAR1_OFFSET, oar1); + + /* Enable the address here. */ + + oar1 |= I2C_OAR1_OA1EN; + stm32_i2c_putreg32(priv, STM32_I2C_OAR1_OFFSET, oar1); + + /* Enable the peripheral and interrupts */ + + priv->read = false; + stm32_i2c_putreg32(priv, STM32_I2C_CR1_OFFSET, + I2C_CR1_ALLINTS | I2C_CR1_PE); + + return OK; +} + +/**************************************************************************** + * Name: stm32_i2c_setup + * + * Description: + * Sets up the STM32 I2C peripheral + * + ****************************************************************************/ + +static int stm32_i2c_setup(struct i2c_slave_s *dev) +{ + struct stm32_i2cslave_s *priv = (struct stm32_i2cslave_s *)dev; + DEBUGASSERT(dev); + + /* Enable the interrupts here. This function is called when the device + * is opened for the first time. + */ + + irq_attach(priv->ev_irq, stm32_i2c_isr, priv); + up_enable_irq(priv->ev_irq); + return OK; +} + +/**************************************************************************** + * Name: stm32_i2c_shutdown + * + * Description: + * Shutdown the STM32 I2C peripheral + * + ****************************************************************************/ + +static int stm32_i2c_shutdown(struct i2c_slave_s *dev) +{ + struct stm32_i2cslave_s *priv = (struct stm32_i2cslave_s *)dev; + uint32_t cr1; + + DEBUGASSERT(dev); + + /* Disable I2C_CR1_PE. Disabling the I2C should have no effect + * on configuration bits, and SCL and SDA lines are released. + * Disable TX and TX interrupts. + */ + + cr1 = stm32_i2c_getreg32(priv, STM32_I2C_CR1_OFFSET); + stm32_i2c_putreg32(priv, STM32_I2C_CR1_OFFSET, + cr1 & ~(I2C_CR1_ALLINTS | I2C_CR1_PE)); + + /* Disable the interrupts here. This function is called when the device + * is closed by the last task. + */ + + up_disable_irq(priv->ev_irq); + irq_detach(priv->ev_irq); + return OK; +} + +/**************************************************************************** + * Name: stm32_i2c_write + * + * Description: + * Receive a pointer to a buffer where to write data to + * + ****************************************************************************/ + +static int stm32_i2c_write(struct i2c_slave_s *dev, const uint8_t *buffer, + int buflen) +{ + struct stm32_i2cslave_s *priv = (struct stm32_i2cslave_s *)dev; + int flags; + + DEBUGASSERT(dev); + flags = enter_critical_section(); + + /* Initialize the TX buffer. */ + + priv->tx_buffer = buffer; + priv->tx_buflen = buflen; + priv->tx_curptr = 0; + + leave_critical_section(flags); + return OK; +} + +/**************************************************************************** + * Name: stm32_i2c_read + * + * Description: + * Receive a pointer to a buffer where to read data to + * + ****************************************************************************/ + +static int stm32_i2c_read(struct i2c_slave_s *dev, uint8_t *buffer, + int buflen) +{ + struct stm32_i2cslave_s *priv = (struct stm32_i2cslave_s *)dev; + int flags; + + DEBUGASSERT(dev); + flags = enter_critical_section(); + + /* Initialize the RX buffer. */ + + priv->rx_buffer = buffer; + priv->rx_buflen = buflen; + + leave_critical_section(flags); + return OK; +} + +/**************************************************************************** + * Name: stm32_i2c_registercallback + * + * Description: + * Register a function which notifies the upperhalf driver + * + ****************************************************************************/ + +static int stm32_i2c_registercallback(struct i2c_slave_s *dev, + i2c_slave_callback_t *callback, + void *arg) +{ + struct stm32_i2cslave_s *priv = (struct stm32_i2cslave_s *)dev; + int flags; + + DEBUGASSERT(dev); + flags = enter_critical_section(); + + /* Initialize the pointer to a callback. */ + + priv->callback = callback; + priv->callback_arg = arg; + + leave_critical_section(flags); + return OK; +} + +/**************************************************************************** + * Name: stm32_i2c_init + * + * Description: + * Initialize STM32 I2C peripheral - clocks and pins + * + ****************************************************************************/ + +static int stm32_i2c_init(struct stm32_i2cslave_s *priv) +{ + DEBUGASSERT(priv); + + modifyreg32(STM32_RCC_APB1ENR, 0, priv->clk_bit); + modifyreg32(STM32_RCC_APB1RSTR, 0, priv->reset_bit); + modifyreg32(STM32_RCC_APB1RSTR, priv->reset_bit, 0); + + if (stm32_configgpio(priv->scl_pin) < 0) + { + return ERROR; + } + + if (stm32_configgpio(priv->sda_pin) < 0) + { + return ERROR; + } + + return OK; +} + +/**************************************************************************** + * Name: stm32_i2c_deinit + * + * Description: + * Deinitialize STM32 I2C peripheral - clocks and pins + * + ****************************************************************************/ + +static int stm32_i2c_deinit(struct stm32_i2cslave_s *priv) +{ + DEBUGASSERT(priv); + + modifyreg32(STM32_RCC_APB1ENR, priv->clk_bit, 0); + modifyreg32(STM32_RCC_APB1RSTR, 0, priv->reset_bit); + stm32_unconfiggpio(priv->scl_pin); + stm32_configgpio(priv->sda_pin); + + return OK; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_i2cbus_slaveinitialize + * + * Description: + * Initialize on I2C bus as a slave and get pointer to i2c_slave_s struct + * + ****************************************************************************/ + +struct i2c_slave_s *stm32_i2cbus_slaveinitialize(int port) +{ + int ret; + struct stm32_i2cslave_s *priv = NULL; + + i2cinfo("SLAVEINIT"); + + switch (port) + { +#ifdef CONFIG_STM32_I2C1_SLAVE + case 1: + priv = (struct stm32_i2cslave_s *)&stm32_i2c1_priv; + break; +#endif +#ifdef CONFIG_STM32_I2C2_SLAVE + case 2: + priv = (struct stm32_i2cslave_s *)&stm32_i2c2_priv; + break; +#endif +#ifdef CONFIG_STM32_I2C3_SLAVE + case 3: + priv = (struct stm32_i2cslave_s *)&stm32_i2c3_priv; + break; +#endif + default: + return NULL; + } + + nxmutex_lock(&priv->lock); + if (priv->refs++ == 0) + { + ret = stm32_i2c_init(priv); + if (ret < 0) + { + stm32_i2c_deinit(priv); + priv = NULL; + } + } + + nxmutex_unlock(&priv->lock); + return (struct i2c_slave_s *)priv; +} + +/**************************************************************************** + * Name: stm32_i2cbus_slaveunitialize + * + * Description: + * Denitialize a given I2C device. + * + ****************************************************************************/ + +int stm32_i2cbus_slaveunitialize(struct i2c_slave_s *dev) +{ + struct stm32_i2cslave_s *priv = (struct stm32_i2cslave_s *)dev; + stm32_i2c_deinit(priv); + return OK; +} diff --git a/arch/arm/src/stm32/stm32_i2s.h b/arch/arm/src/common/stm32/stm32_i2s.h similarity index 78% rename from arch/arm/src/stm32/stm32_i2s.h rename to arch/arm/src/common/stm32/stm32_i2s.h index 5ed34136591cf..376fa24efed81 100644 --- a/arch/arm/src/stm32/stm32_i2s.h +++ b/arch/arm/src/common/stm32/stm32_i2s.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_i2s.h + * arch/arm/src/common/stm32/stm32_i2s.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,32 +20,35 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_STM32_I2S_H -#define __ARCH_ARM_SRC_STM32_STM32_I2S_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_I2S_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_I2S_H /**************************************************************************** * Included Files ****************************************************************************/ #include -#include -#include "chip.h" +#ifdef CONFIG_STM32_HAVE_IP_I2S_M3M4_V1 -#ifndef __ASSEMBLY__ +# include + +# include "chip.h" + +# ifndef __ASSEMBLY__ /**************************************************************************** * Public Data ****************************************************************************/ -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" +# undef EXTERN +# if defined(__cplusplus) +# define EXTERN extern "C" extern "C" { -#else -#define EXTERN extern -#endif +# else +# define EXTERN extern +# endif /**************************************************************************** * Public Function Prototypes @@ -67,10 +70,13 @@ extern "C" struct i2s_dev_s *stm32_i2sbus_initialize(int port); -#undef EXTERN -#if defined(__cplusplus) +# undef EXTERN +# if defined(__cplusplus) } -#endif +# endif + +# endif /* __ASSEMBLY__ */ + +#endif /* CONFIG_STM32_HAVE_IP_I2S_M3M4_V1 */ -#endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32_STM32_I2S_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_I2S_H */ diff --git a/arch/arm/src/common/stm32/stm32_i2s_m3m4_v1.c b/arch/arm/src/common/stm32/stm32_i2s_m3m4_v1.c new file mode 100644 index 0000000000000..49be32aa82630 --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_i2s_m3m4_v1.c @@ -0,0 +1,2612 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_i2s_m3m4_v1.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status + * must be provided by board-specific logic. They are implementations of + * the select and status methods of the SPI interface defined by struct + * spi_ops_s (see include/nuttx/spi/spi.h). All other methods (including + * up_spiinitialize()) are provided by common STM32 logic. To use this + * common SPI logic on your board: + * + * 1. Provide logic in stm32_boardinitialize() to configure I2S chip + * select pins. + * 2. Provide stm32_i2s2/3select() and stm32_i2s2/3status() functions in + * your board-specific logic. These functions will perform chip + * selection and status operations using GPIOs in the way your board + * is configured. + * 3. Add a calls to up_spiinitialize() in your low level application + * initialization logic + * 4. The handle returned by stm32_i2sbus_initialize() may then be used to + * bind the I2S driver to higher level logic + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "arm_internal.h" +#include "stm32_dma.h" +#include "stm32_i2s.h" +#include "stm32_spi.h" +#include "stm32_rcc.h" + +#if defined(CONFIG_STM32_I2S2) || defined(CONFIG_STM32_I2S3) + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +#ifndef CONFIG_SCHED_WORKQUEUE +# error Work queue support is required (CONFIG_SCHED_WORKQUEUE) +#endif + +#ifndef CONFIG_AUDIO +# error CONFIG_AUDIO required by this driver +#endif + +#ifndef CONFIG_STM32_I2S_MAXINFLIGHT +# define CONFIG_STM32_I2S_MAXINFLIGHT 16 +#endif + +/* Assume no RX/TX support until we learn better */ + +#undef I2S_HAVE_RX +#undef I2S_HAVE_TX + +/* Check for I2S RX support */ + +# if defined(CONFIG_STM32_I2S3_RX) +# define I2S_HAVE_RX 1 + +# ifdef CONFIG_STM32_I2S_MCK +# define I2S_HAVE_MCK 1 +# endif + +# endif + +/* Check for I2S3 TX support */ + +# if defined(CONFIG_STM32_I2S3_TX) +# define I2S_HAVE_TX 1 + +# ifdef CONFIG_STM32_I2S_MCK +# define I2S_HAVE_MCK 1 +# endif + +# endif + +/* Configuration ************************************************************/ + +/* I2S interrupts */ + +#ifdef CONFIG_STM32_SPI_INTERRUPTS +# error "Interrupt driven I2S not yet supported" +#endif + +/* Can't have both interrupt driven SPI and SPI DMA */ + +#if defined(CONFIG_STM32_SPI_INTERRUPTS) && defined(CONFIG_STM32_SPI_DMA) +# error "Cannot enable both interrupt mode and DMA mode for SPI" +#endif + +/* SPI DMA priority */ + +#ifdef CONFIG_STM32_SPI_DMA + +# if defined(CONFIG_SPI_DMAPRIO) +# define SPI_DMA_PRIO CONFIG_SPI_DMAPRIO +# elif defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32L15XX) +# define SPI_DMA_PRIO DMA_CCR_PRIMED +# elif defined(CONFIG_STM32_HAVE_IP_DMA_V2) +# define SPI_DMA_PRIO DMA_SCR_PRIMED +# else +# error "Unknown STM32 DMA" +# endif + +# if defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32L15XX) +# if (SPI_DMA_PRIO & ~DMA_CCR_PL_MASK) != 0 +# error "Illegal value for CONFIG_SPI_DMAPRIO" +# endif +# elif defined(CONFIG_STM32_HAVE_IP_DMA_V2) +# if (SPI_DMA_PRIO & ~DMA_SCR_PL_MASK) != 0 +# error "Illegal value for CONFIG_SPI_DMAPRIO" +# endif +# else +# error "Unknown STM32 DMA" +# endif + +#endif + +/* DMA channel configuration */ + +#if defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F30XX) || \ + defined(CONFIG_STM32_STM32L15XX) +# define SPI_RXDMA16_CONFIG (SPI_DMA_PRIO|DMA_CCR_MSIZE_16BITS|DMA_CCR_PSIZE_16BITS|DMA_CCR_MINC ) +# define SPI_RXDMA8_CONFIG (SPI_DMA_PRIO|DMA_CCR_MSIZE_8BITS |DMA_CCR_PSIZE_8BITS |DMA_CCR_MINC ) +# define SPI_RXDMA16NULL_CONFIG (SPI_DMA_PRIO|DMA_CCR_MSIZE_8BITS |DMA_CCR_PSIZE_16BITS ) +# define SPI_RXDMA8NULL_CONFIG (SPI_DMA_PRIO|DMA_CCR_MSIZE_8BITS |DMA_CCR_PSIZE_8BITS ) +# define SPI_TXDMA16_CONFIG (SPI_DMA_PRIO|DMA_CCR_MSIZE_16BITS|DMA_CCR_PSIZE_16BITS|DMA_CCR_MINC|DMA_CCR_DIR) +# define SPI_TXDMA8_CONFIG (SPI_DMA_PRIO|DMA_CCR_MSIZE_8BITS |DMA_CCR_PSIZE_8BITS |DMA_CCR_MINC|DMA_CCR_DIR) +# define SPI_TXDMA16NULL_CONFIG (SPI_DMA_PRIO|DMA_CCR_MSIZE_8BITS |DMA_CCR_PSIZE_16BITS |DMA_CCR_DIR) +# define SPI_TXDMA8NULL_CONFIG (SPI_DMA_PRIO|DMA_CCR_MSIZE_8BITS |DMA_CCR_PSIZE_8BITS |DMA_CCR_DIR) +#elif defined(CONFIG_STM32_HAVE_IP_DMA_V2) +# define SPI_RXDMA16_CONFIG (SPI_DMA_PRIO|DMA_SCR_MSIZE_16BITS|DMA_SCR_PSIZE_16BITS|DMA_SCR_MINC|DMA_SCR_DIR_P2M) +# define SPI_RXDMA8_CONFIG (SPI_DMA_PRIO|DMA_SCR_MSIZE_8BITS |DMA_SCR_PSIZE_8BITS |DMA_SCR_MINC|DMA_SCR_DIR_P2M) +# define SPI_RXDMA16NULL_CONFIG (SPI_DMA_PRIO|DMA_SCR_MSIZE_8BITS |DMA_SCR_PSIZE_16BITS |DMA_SCR_DIR_P2M) +# define SPI_RXDMA8NULL_CONFIG (SPI_DMA_PRIO|DMA_SCR_MSIZE_8BITS |DMA_SCR_PSIZE_8BITS |DMA_SCR_DIR_P2M) +# define SPI_TXDMA16_CONFIG (SPI_DMA_PRIO|DMA_SCR_MSIZE_16BITS|DMA_SCR_PSIZE_16BITS|DMA_SCR_MINC|DMA_SCR_DIR_M2P) +# define SPI_TXDMA8_CONFIG (SPI_DMA_PRIO|DMA_SCR_MSIZE_8BITS |DMA_SCR_PSIZE_8BITS |DMA_SCR_MINC|DMA_SCR_DIR_M2P) +# define SPI_TXDMA16NULL_CONFIG (SPI_DMA_PRIO|DMA_SCR_MSIZE_8BITS |DMA_SCR_PSIZE_16BITS |DMA_SCR_DIR_M2P) +# define SPI_TXDMA8NULL_CONFIG (SPI_DMA_PRIO|DMA_SCR_MSIZE_8BITS |DMA_SCR_PSIZE_8BITS |DMA_SCR_DIR_M2P) +#else +# error "Unknown STM32 DMA" +#endif + +/* Debug ********************************************************************/ + +/* Check if SSC debug is enabled (non-standard.. no support in + * include/nuttx/debug.h + */ + +#ifndef CONFIG_DEBUG_I2S_INFO +# undef CONFIG_STM32_I2S_DMADEBUG +# undef CONFIG_STM32_I2S_REGDEBUG +# undef CONFIG_STM32_I2S_QDEBUG +# undef CONFIG_STM32_I2S_DUMPBUFFERS +#endif + +/* The I2S can handle most any bit width from 8 to 32. However, the DMA + * logic here is constrained to byte, half-word, and word sizes. + */ + +#ifndef CONFIG_STM32_I2S3_DATALEN +# define CONFIG_STM32_I2S3_DATALEN 16 +#endif + +#if CONFIG_STM32_I2S3_DATALEN == 8 +# define STM32_I2S3_DATAMASK 0 +#elif CONFIG_STM32_I2S3_DATALEN == 16 +# define STM32_I2S3_DATAMASK 1 +#elif CONFIG_STM32_I2S3_DATALEN < 8 || CONFIG_STM32_I2S3_DATALEN > 16 +# error Invalid value for CONFIG_STM32_I2S3_DATALEN +#else +# error Valid but supported value for CONFIG_STM32_I2S3_DATALEN +#endif + +/* Check if we need to build RX and/or TX support */ + +#if defined(I2S_HAVE_RX) || defined(I2S_HAVE_TX) + +#ifndef CONFIG_DEBUG_DMA +# undef CONFIG_STM32_I2S_DMADEBUG +#endif + +#define DMA_INITIAL 0 +#define DMA_AFTER_SETUP 1 +#define DMA_AFTER_START 2 +#define DMA_CALLBACK 3 +#define DMA_TIMEOUT 3 +#define DMA_END_TRANSFER 4 +#define DMA_NSAMPLES 5 + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/* I2S buffer container */ + +struct stm32_buffer_s +{ + struct stm32_buffer_s *flink; /* Supports a singly linked list */ + i2s_callback_t callback; /* Function to call when the transfer + * completes */ + uint32_t timeout; /* The timeout value to use with DMA + * transfers */ + void *arg; /* The argument to be returned with the + * callback */ + struct ap_buffer_s *apb; /* The audio buffer */ + int result; /* The result of the transfer */ +}; + +/* This structure describes the state of one receiver or transmitter + * transport. + */ + +struct stm32_transport_s +{ + DMA_HANDLE dma; /* I2S DMA handle */ + struct wdog_s dog; /* Watchdog that handles DMA timeouts */ + sq_queue_t pend; /* A queue of pending transfers */ + sq_queue_t act; /* A queue of active transfers */ + sq_queue_t done; /* A queue of completed transfers */ + struct work_s work; /* Supports worker thread operations */ + +#ifdef CONFIG_STM32_I2S_DMADEBUG + struct stm32_dmaregs_s dmaregs[DMA_NSAMPLES]; +#endif +}; + +/* The state of the one I2S peripheral */ + +struct stm32_i2s_s +{ + struct i2s_dev_s dev; /* Externally visible I2S interface */ + uintptr_t base; /* I2S controller register base address */ + mutex_t lock; /* Assures mutually exclusive access to I2S */ + bool initialized; /* Has I2S interface been initialized */ + uint8_t datalen; /* Data width (8 or 16) */ + uint8_t align; /* Log2 of data width (0 or 1) */ + uint8_t rxenab:1; /* True: RX transfers enabled */ + uint8_t txenab:1; /* True: TX transfers enabled */ + uint8_t i2sno:6; /* I2S controller number (0 or 1) */ +#ifdef I2S_HAVE_MCK + uint32_t samplerate; /* Data sample rate (determines only MCK + * divider) */ +#endif + uint32_t rxccr; /* DMA control register for RX transfers */ + uint32_t txccr; /* DMA control register for TX transfers */ +#ifdef I2S_HAVE_RX + struct stm32_transport_s rx; /* RX transport state */ +#endif +#ifdef I2S_HAVE_TX + struct stm32_transport_s tx; /* TX transport state */ +#endif + + /* Pre-allocated pool of buffer containers */ + + sem_t bufsem; /* Buffer wait semaphore */ + struct stm32_buffer_s *freelist; /* A list a free buffer containers */ + struct stm32_buffer_s containers[CONFIG_STM32_I2S_MAXINFLIGHT]; + + /* Debug stuff */ + +#ifdef CONFIG_STM32_I2S_REGDEBUG + bool wr; /* Last was a write */ + uint32_t regaddr; /* Last address */ + uint16_t regval; /* Last value */ + int count; /* Number of times */ +#endif +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/* Register helpers */ + +#ifdef CONFIG_STM32_I2S_REGDEBUG +static bool i2s_checkreg(struct stm32_i2s_s *priv, bool wr, + uint16_t regval, uint32_t regaddr); +#else +# define i2s_checkreg(priv,wr,regval,regaddr) (false) +#endif + +static inline uint16_t i2s_getreg(struct stm32_i2s_s *priv, uint8_t offset); +static inline void i2s_putreg(struct stm32_i2s_s *priv, uint8_t offset, + uint16_t regval); + +#if defined(CONFIG_DEBUG_I2S_INFO) +static void i2s_dump_regs(struct stm32_i2s_s *priv, const char *msg); +#else +# define i2s_dump_regs(s,m) +#endif + +#ifdef CONFIG_STM32_I2S_DUMPBUFFERS +# define i2s_init_buffer(b,s) memset(b, 0x55, s); +# define i2s_dump_buffer(m,b,s) lib_dumpbuffer(m,b,s) +#else +# define i2s_init_buffer(b,s) +# define i2s_dump_buffer(m,b,s) +#endif + +/* Buffer container helpers */ + +static struct stm32_buffer_s * + i2s_buf_allocate(struct stm32_i2s_s *priv); +static void i2s_buf_free(struct stm32_i2s_s *priv, + struct stm32_buffer_s *bfcontainer); +static void i2s_buf_initialize(struct stm32_i2s_s *priv); + +/* DMA support */ + +#ifdef CONFIG_STM32_I2S_DMADEBUG +static void i2s_dma_sampleinit(struct stm32_i2s_s *priv, + struct stm32_transport_s *xpt); +#endif + +#if defined(CONFIG_STM32_I2S_DMADEBUG) && defined(I2S_HAVE_RX) +# define i2s_rxdma_sample(s,i) stm32_dmasample((s)->rx.dma, &(s)->rx.dmaregs[i]) +# define i2s_rxdma_sampleinit(s) i2s_dma_sampleinit(s, &(s)->rx) +static void i2s_rxdma_sampledone(struct stm32_i2s_s *priv, int result); + +#else +# define i2s_rxdma_sample(s,i) +# define i2s_rxdma_sampleinit(s) +# define i2s_rxdma_sampledone(s,r) + +#endif + +#if defined(CONFIG_STM32_I2S_DMADEBUG) && defined(I2S_HAVE_TX) +# define i2s_txdma_sample(s,i) stm32_dmasample((s)->tx.dma, &(s)->tx.dmaregs[i]) +# define i2s_txdma_sampleinit(s) i2s_dma_sampleinit(s, &(s)->tx) +static void i2s_txdma_sampledone(struct stm32_i2s_s *priv, int result); + +#else +# define i2s_txdma_sample(s,i) +# define i2s_txdma_sampleinit(s) +# define i2s_txdma_sampledone(s,r) + +#endif + +#ifdef I2S_HAVE_RX +static void i2s_rxdma_timeout(wdparm_t arg); +static int i2s_rxdma_setup(struct stm32_i2s_s *priv); +static void i2s_rx_worker(void *arg); +static void i2s_rx_schedule(struct stm32_i2s_s *priv, int result); +static void i2s_rxdma_callback(DMA_HANDLE handle, uint8_t result, + void *arg); +#endif +#ifdef I2S_HAVE_TX +static void i2s_txdma_timeout(wdparm_t arg); +static int i2s_txdma_setup(struct stm32_i2s_s *priv); +static void i2s_tx_worker(void *arg); +static void i2s_tx_schedule(struct stm32_i2s_s *priv, int result); +static void i2s_txdma_callback(DMA_HANDLE handle, uint8_t result, + void *arg); +#endif + +/* I2S methods (and close friends) */ + +static int i2s_checkwidth(struct stm32_i2s_s *priv, int bits); + +static uint32_t stm32_i2s_rxsamplerate(struct i2s_dev_s *dev, uint32_t rate); +static uint32_t stm32_i2s_rxdatawidth(struct i2s_dev_s *dev, int bits); +static int stm32_i2s_receive(struct i2s_dev_s *dev, + struct ap_buffer_s *apb, + i2s_callback_t callback, + void *arg, uint32_t timeout); +static uint32_t stm32_i2s_txsamplerate(struct i2s_dev_s *dev, uint32_t rate); +static uint32_t stm32_i2s_txdatawidth(struct i2s_dev_s *dev, int bits); +static int stm32_i2s_send(struct i2s_dev_s *dev, + struct ap_buffer_s *apb, + i2s_callback_t callback, void *arg, + uint32_t timeout); + +/* Initialization */ + +static uint32_t i2s_mckdivider(struct stm32_i2s_s *priv); +static int i2s_dma_flags(struct stm32_i2s_s *priv); +static int i2s_dma_allocate(struct stm32_i2s_s *priv); +static void i2s_dma_free(struct stm32_i2s_s *priv); +#ifdef CONFIG_STM32_I2S2 +static void i2s2_configure(struct stm32_i2s_s *priv); +#endif +#ifdef CONFIG_STM32_I2S3 +static void i2s3_configure(struct stm32_i2s_s *priv); +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* I2S device operations */ + +static const struct i2s_ops_s g_i2sops = +{ + /* Receiver methods */ + + .i2s_rxsamplerate = stm32_i2s_rxsamplerate, + .i2s_rxdatawidth = stm32_i2s_rxdatawidth, + .i2s_receive = stm32_i2s_receive, + + /* Transmitter methods */ + + .i2s_txsamplerate = stm32_i2s_txsamplerate, + .i2s_txdatawidth = stm32_i2s_txdatawidth, + .i2s_send = stm32_i2s_send, +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: i2s_checkreg + * + * Description: + * Check if the current register access is a duplicate of the preceding. + * + * Input Parameters: + * regval - The value to be written + * regaddr - The address of the register to write to + * + * Returned Value: + * true: This is the first register access of this type. + * false: This is the same as the preceding register access. + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_I2S_REGDEBUG +static bool i2s_checkreg(struct stm32_i2s_s *priv, bool wr, uint16_t regval, + uint32_t regaddr) +{ + if (wr == priv->wr && /* Same kind of access? */ + regval == priv->regval && /* Same value? */ + regaddr == priv->regaddr) /* Same address? */ + { + /* Yes, then just keep a count of the number of times we did this. */ + + priv->count++; + return false; + } + else + { + /* Did we do the previous operation more than once? */ + + if (priv->count > 0) + { + /* Yes... show how many times we did it */ + + i2sinfo("...[Repeats %d times]...\n", priv->count); + } + + /* Save information about the new access */ + + priv->wr = wr; + priv->regval = regval; + priv->regaddr = regaddr; + priv->count = 0; + } + + /* Return true if this is the first time that we have done this operation */ + + return true; +} +#endif + +/**************************************************************************** + * Name: i2s_getreg + * + * Description: + * Get the contents of the I2S register at offset + * + * Input Parameters: + * priv - private I2S device structure + * offset - offset to the register of interest + * + * Returned Value: + * The contents of the 16-bit register + * + ****************************************************************************/ + +static inline uint16_t i2s_getreg(struct stm32_i2s_s *priv, + uint8_t offset) +{ + uint32_t regaddr = priv->base + offset; + uint16_t regval = getreg16(regaddr); + +#ifdef CONFIG_STM32_I2S_REGDEBUG + if (i2s_checkreg(priv, false, regval, regaddr)) + { + i2sinfo("%08" PRIx32 "->%04x\n", regaddr, regval); + } +#endif + + return regval; +} + +/**************************************************************************** + * Name: spi_putreg + * + * Description: + * Write a 16-bit value to the SPI register at offset + * + * Input Parameters: + * priv - private SPI device structure + * offset - offset to the register of interest + * value - the 16-bit value to be written + * + * Returned Value: + * The contents of the 16-bit register + * + ****************************************************************************/ + +static inline void i2s_putreg(struct stm32_i2s_s *priv, uint8_t offset, + uint16_t regval) +{ + uint32_t regaddr = priv->base + offset; + +#ifdef CONFIG_STM32_I2S_REGDEBUG + if (i2s_checkreg(priv, true, regval, regaddr)) + { + i2sinfo("%08" PRIx32 "<-%04x\n", regaddr, regval); + } +#endif + + putreg16(regval, regaddr); +} + +/**************************************************************************** + * Name: i2s_dump_regs + * + * Description: + * Dump the contents of all I2S registers + * + * Input Parameters: + * priv - The I2S controller to dump + * msg - Message to print before the register data + * + * Returned Value: + * None + * + ****************************************************************************/ + +#if defined(CONFIG_DEBUG_I2S) +static void i2s_dump_regs(struct stm32_i2s_s *priv, const char *msg) +{ + i2sinfo("I2S%d: %s\n", priv->i2sno, msg); + i2sinfo(" CR1:%04x CR2:%04x SR:%04x DR:%04x\n", + i2s_getreg(priv, STM32_SPI_CR1_OFFSET), + i2s_getreg(priv, STM32_SPI_CR2_OFFSET), + i2s_getreg(priv, STM32_SPI_SR_OFFSET), + i2s_getreg(priv, STM32_SPI_DR_OFFSET)); + i2sinfo(" I2SCFGR:%04x I2SPR:%04x\n", + i2s_getreg(priv, STM32_SPI_I2SCFGR_OFFSET), + i2s_getreg(priv, STM32_SPI_I2SPR_OFFSET)); +} +#endif + +/**************************************************************************** + * Name: i2s_buf_allocate + * + * Description: + * Allocate a buffer container by removing the one at the head of the + * free list + * + * Input Parameters: + * priv - I2S state instance + * + * Returned Value: + * A non-NULL pointer to the allocate buffer container on success; NULL if + * there are no available buffer containers. + * + * Assumptions: + * The caller does NOT have exclusive access to the I2S state structure. + * That would result in a deadlock! + * + ****************************************************************************/ + +static struct stm32_buffer_s *i2s_buf_allocate(struct stm32_i2s_s *priv) +{ + struct stm32_buffer_s *bfcontainer; + irqstate_t flags; + int ret; + + /* Set aside a buffer container. By doing this, we guarantee that we will + * have at least one free buffer container. + */ + + ret = nxsem_wait_uninterruptible(&priv->bufsem); + if (ret < 0) + { + return NULL; + } + + /* Get the buffer from the head of the free list */ + + flags = enter_critical_section(); + bfcontainer = priv->freelist; + DEBUGASSERT(bfcontainer); + + /* Unlink the buffer from the freelist */ + + priv->freelist = bfcontainer->flink; + leave_critical_section(flags); + return bfcontainer; +} + +/**************************************************************************** + * Name: i2s_buf_free + * + * Description: + * Free buffer container by adding it to the head of the free list + * + * Input Parameters: + * priv - I2S state instance + * bfcontainer - The buffer container to be freed + * + * Returned Value: + * None + * + * Assumptions: + * The caller has exclusive access to the I2S state structure + * + ****************************************************************************/ + +static void i2s_buf_free(struct stm32_i2s_s *priv, + struct stm32_buffer_s *bfcontainer) +{ + irqstate_t flags; + + /* Put the buffer container back on the free list */ + + flags = enter_critical_section(); + bfcontainer->flink = priv->freelist; + priv->freelist = bfcontainer; + leave_critical_section(flags); + + /* Wake up any threads waiting for a buffer container */ + + nxsem_post(&priv->bufsem); +} + +/**************************************************************************** + * Name: i2s_buf_initialize + * + * Description: + * Initialize the buffer container allocator by adding all of the + * pre-allocated buffer containers to the free list + * + * Input Parameters: + * priv - I2S state instance + * + * Returned Value: + * None + * + * Assumptions: + * Called early in I2S initialization so that there are no issues with + * concurrency. + * + ****************************************************************************/ + +static void i2s_buf_initialize(struct stm32_i2s_s *priv) +{ + int i; + + priv->freelist = NULL; + nxsem_init(&priv->bufsem, 0, CONFIG_STM32_I2S_MAXINFLIGHT); + + for (i = 0; i < CONFIG_STM32_I2S_MAXINFLIGHT; i++) + { + i2s_buf_free(priv, &priv->containers[i]); + } +} + +/**************************************************************************** + * Name: i2s_dma_sampleinit + * + * Description: + * Initialize sampling of DMA registers (if CONFIG_STM32_I2S_DMADEBUG) + * + * Input Parameters: + * priv - I2S state instance + * + * Returned Value: + * None + * + ****************************************************************************/ + +#if defined(CONFIG_STM32_I2S_DMADEBUG) +static void i2s_dma_sampleinit(struct stm32_i2s_s *priv, + struct stm32_transport_s *xpt) +{ + /* Put contents of register samples into a known state */ + + memset(xpt->dmaregs, 0xff, DMA_NSAMPLES * sizeof(struct stm32_dmaregs_s)); + + /* Then get the initial samples */ + + stm32_dmasample(xpt->dma, &xpt->dmaregs[DMA_INITIAL]); +} +#endif + +/**************************************************************************** + * Name: i2s_rxdma_sampledone + * + * Description: + * Dump sampled RX DMA registers + * + * Input Parameters: + * priv - I2S state instance + * + * Returned Value: + * None + * + ****************************************************************************/ + +#if defined(CONFIG_STM32_I2S_DMADEBUG) && defined(I2S_HAVE_RX) +static void i2s_rxdma_sampledone(struct stm32_i2s_s *priv, int result) +{ + i2sinfo("result: %d\n", result); + + /* Sample the final registers */ + + stm32_dmasample(priv->rx.dma, &priv->rx.dmaregs[DMA_END_TRANSFER]); + + /* Then dump the sampled DMA registers */ + + /* Initial register values */ + + stm32_dmadump(priv->rx.dma, &priv->rx.dmaregs[DMA_INITIAL], + "RX: Initial Registers"); + + /* Register values after DMA setup */ + + stm32_dmadump(priv->rx.dma, &priv->rx.dmaregs[DMA_AFTER_SETUP], + "RX: After DMA Setup"); + + /* Register values after DMA start */ + + stm32_dmadump(priv->rx.dma, &priv->rx.dmaregs[DMA_AFTER_START], + "RX: After DMA Start"); + + /* Register values at the time of the TX and RX DMA callbacks + * -OR- DMA timeout. + * + * If the DMA timedout, then there will not be any RX DMA + * callback samples. There is probably no TX DMA callback + * samples either, but we don't know for sure. + */ + + if (result == -ETIMEDOUT || result == -EINTR) + { + stm32_dmadump(priv->rx.dma, &priv->rx.dmaregs[DMA_TIMEOUT], + "RX: At DMA timeout"); + } + else + { + stm32_dmadump(priv->rx.dma, &priv->rx.dmaregs[DMA_CALLBACK], + "RX: At DMA callback"); + } + + stm32_dmadump(priv->rx.dma, &priv->rx.dmaregs[DMA_END_TRANSFER], + "RX: At End-of-Transfer"); + + i2s_dump_regs(priv, "RX: At End-of-Transfer"); +} +#endif + +/**************************************************************************** + * Name: i2s_txdma_sampledone + * + * Description: + * Dump sampled DMA registers + * + * Input Parameters: + * priv - I2S state instance + * + * Returned Value: + * None + * + ****************************************************************************/ + +#if defined(CONFIG_STM32_I2S_DMADEBUG) && defined(I2S_HAVE_TX) +static void i2s_txdma_sampledone(struct stm32_i2s_s *priv, int result) +{ + i2sinfo("result: %d\n", result); + + /* Sample the final registers */ + + stm32_dmasample(priv->tx.dma, &priv->tx.dmaregs[DMA_END_TRANSFER]); + + /* Then dump the sampled DMA registers */ + + /* Initial register values */ + + stm32_dmadump(priv->tx.dma, &priv->tx.dmaregs[DMA_INITIAL], + "TX: Initial Registers"); + + /* Register values after DMA setup */ + + stm32_dmadump(priv->tx.dma, &priv->tx.dmaregs[DMA_AFTER_SETUP], + "TX: After DMA Setup"); + + /* Register values after DMA start */ + + stm32_dmadump(priv->tx.dma, &priv->tx.dmaregs[DMA_AFTER_START], + "TX: After DMA Start"); + + /* Register values at the time of the TX and RX DMA callbacks + * -OR- DMA timeout. + */ + + if (result == -ETIMEDOUT || result == -EINTR) + { + stm32_dmadump(priv->tx.dma, &priv->tx.dmaregs[DMA_TIMEOUT], + "TX: At DMA timeout"); + } + else + { + stm32_dmadump(priv->tx.dma, &priv->tx.dmaregs[DMA_CALLBACK], + "TX: At DMA callback"); + } + + stm32_dmadump(priv->tx.dma, &priv->tx.dmaregs[DMA_END_TRANSFER], + "TX: At End-of-Transfer"); + + i2s_dump_regs(priv, "TX: At End-of-Transfer"); +} +#endif + +/**************************************************************************** + * Name: i2s_rxdma_timeout + * + * Description: + * The RX watchdog timeout without completion of the RX DMA. + * + * Input Parameters: + * arg - The argument + * + * Returned Value: + * None + * + * Assumptions: + * Always called from the interrupt level with interrupts disabled. + * + ****************************************************************************/ + +#ifdef I2S_HAVE_RX +static void i2s_rxdma_timeout(wdparm_t arg) +{ + struct stm32_i2s_s *priv = (struct stm32_i2s_s *)arg; + DEBUGASSERT(priv != NULL); + + /* Sample DMA registers at the time of the timeout */ + + i2s_rxdma_sample(priv, DMA_TIMEOUT); + + /* Cancel the DMA */ + + stm32_dmastop(priv->rx.dma); + + /* Then schedule completion of the transfer to occur on the worker thread. + * NOTE: stm32_dmastop() will call the DMA complete callback with an error + * of -EINTR. So the following is just insurance and should have no + * effect if the worker is already schedule. + */ + + i2s_rx_schedule(priv, -ETIMEDOUT); +} +#endif + +/**************************************************************************** + * Name: i2s_rxdma_setup + * + * Description: + * Setup and initiate the next RX DMA transfer + * + * Input Parameters: + * priv - I2S state instance + * + * Returned Value: + * OK on success; a negated errno value on failure + * + * Assumptions: + * Interrupts are disabled + * + ****************************************************************************/ + +#ifdef I2S_HAVE_RX +static int i2s_rxdma_setup(struct stm32_i2s_s *priv) +{ + struct stm32_buffer_s *bfcontainer; + struct ap_buffer_s *apb; + uintptr_t samp; + uint32_t timeout; + bool notimeout; + int ret; + + /* If there is already an active transmission in progress, then bail + * returning success. + */ + + if (!sq_empty(&priv->rx.act)) + { + return OK; + } + + /* If there are no pending transfer, then bail returning success */ + + if (sq_empty(&priv->rx.pend)) + { + return OK; + } + + /* Initialize DMA register sampling */ + + i2s_rxdma_sampleinit(priv); + + /* Loop, adding each pending DMA */ + + timeout = 0; + notimeout = false; + + do + { + /* Remove the pending RX transfer at the head of the RX pending + * queue. + */ + + bfcontainer = (struct stm32_buffer_s *)sq_remfirst(&priv->rx.pend); + DEBUGASSERT(bfcontainer && bfcontainer->apb); + + apb = bfcontainer->apb; + DEBUGASSERT(((uintptr_t)apb->samp % priv->align) == 0); + + /* No data received yet */ + + apb->nbytes = 0; + apb->curbyte = 0; + samp = (uintptr_t)&apb->samp[apb->curbyte]; + + /* Configure the RX DMA */ + + stm32_dmasetup(priv->rx.dma, priv->base + STM32_SPI_DR_OFFSET, + (uint32_t)samp, apb->nmaxbytes, priv->rxccr); + + /* Increment the DMA timeout */ + + if (bfcontainer->timeout > 0) + { + timeout += bfcontainer->timeout; + } + else + { + notimeout = true; + } + + /* Add the container to the list of active DMAs */ + + sq_addlast((sq_entry_t *)bfcontainer, &priv->rx.act); + } +#if 1 /* REVISIT: Chained RX transfers */ + while (0); +#else + while (!sq_empty(&priv->rx.pend)); +#endif + + /* Sample DMA registers */ + + i2s_rxdma_sample(priv, DMA_AFTER_SETUP); + + /* Start the DMA, saving the container as the current active transfer */ + + stm32_dmastart(priv->rx.dma, i2s_rxdma_callback, priv, false); + + i2s_rxdma_sample(priv, DMA_AFTER_START); + + /* Enable the receiver */ + + i2s_putreg(priv, STM32_SPI_CR2_OFFSET, + i2s_getreg(priv, STM32_SPI_CR2_OFFSET) | SPI_CR2_RXDMAEN); + + /* Start a watchdog to catch DMA timeouts */ + + if (!notimeout) + { + ret = wd_start(&priv->rx.dog, timeout, + i2s_rxdma_timeout, (wdparm_t)priv); + + /* Check if we have successfully started the watchdog timer. Note + * that we do nothing in the case of failure to start the timer. We + * are already committed to the DMA anyway. Let's just hope that the + * DMA does not hang. + */ + + if (ret < 0) + { + i2serr("ERROR: wd_start failed: %d\n", ret); + } + } + + return OK; +} +#endif + +/**************************************************************************** + * Name: i2s_rx_worker + * + * Description: + * RX transfer done worker + * + * Input Parameters: + * arg - the I2S device instance cast to void* + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef I2S_HAVE_RX +static void i2s_rx_worker(void *arg) +{ + struct stm32_i2s_s *priv = (struct stm32_i2s_s *)arg; + struct stm32_buffer_s *bfcontainer; + struct ap_buffer_s *apb; + irqstate_t flags; + + DEBUGASSERT(priv); + + /* When the transfer was started, the active buffer containers were removed + * from the rx.pend queue and saved in the rx.act queue. We get here when + * the DMA is finished... either successfully, with a DMA error, or with a + * DMA timeout. + * + * In any case, the buffer containers in rx.act will be moved to the end + * of the rx.done queue and rx.act queue will be emptied before this worker + * is started. + * + * REVISIT: Normal DMA callback processing should restart the DMA + * immediately to avoid audio artifacts at the boundaries between DMA + * transfers. Unfortunately, the DMA callback occurs at the interrupt + * level and we cannot call dma_rxsetup() from the interrupt level. + * So we have to start the next DMA here. + */ + + i2sinfo("rx.act.head=%p rx.done.head=%p\n", + priv->rx.act.head, priv->rx.done.head); + + /* Check if the DMA is IDLE */ + + if (sq_empty(&priv->rx.act)) + { +#ifdef CONFIG_STM32_I2S_DMADEBUG + bfcontainer = (struct stm32_buffer_s *)sq_peek(&priv->rx.done); + if (bfcontainer) + { + /* Dump the DMA registers */ + + i2s_rxdma_sampledone(priv, bfcontainer->result); + } +#endif + + /* Then start the next DMA. This must be done with interrupts + * disabled. + */ + + flags = enter_critical_section(); + i2s_rxdma_setup(priv); + leave_critical_section(flags); + } + + /* Process each buffer in the rx.done queue */ + + while (sq_peek(&priv->rx.done) != NULL) + { + /* Remove the buffer container from the rx.done queue. NOTE that + * interrupts must be enabled to do this because the rx.done queue is + * also modified from the interrupt level. + */ + + flags = enter_critical_section(); + bfcontainer = (struct stm32_buffer_s *)sq_remfirst(&priv->rx.done); + leave_critical_section(flags); + + DEBUGASSERT(bfcontainer && bfcontainer->apb && bfcontainer->callback); + apb = bfcontainer->apb; + + /* If the DMA was successful, then update the number of valid bytes in + * the audio buffer. + */ + + if (bfcontainer->result == OK) + { + apb->nbytes = apb->nmaxbytes; + } + + i2s_dump_buffer("Received", apb->samp, apb->nbytes); + + /* Perform the RX transfer done callback */ + + bfcontainer->callback(&priv->dev, apb, bfcontainer->arg, + bfcontainer->result); + + /* Release our reference on the audio buffer. This may very likely + * cause the audio buffer to be freed. + */ + + apb_free(apb); + + /* And release the buffer container */ + + i2s_buf_free(priv, bfcontainer); + } +} +#endif + +/**************************************************************************** + * Name: i2s_rx_schedule + * + * Description: + * An RX DMA completion or timeout has occurred. Schedule processing on + * the working thread. + * + * Input Parameters: + * handle - The DMA handler + * arg - A pointer to the chip select struction + * result - The result of the DMA transfer + * + * Returned Value: + * None + * + * Assumptions: + * Interrupts are disabled + * + ****************************************************************************/ + +#ifdef I2S_HAVE_RX +static void i2s_rx_schedule(struct stm32_i2s_s *priv, int result) +{ + struct stm32_buffer_s *bfcontainer; + int ret; + + /* Upon entry, the transfer(s) that just completed are the ones in the + * priv->rx.act queue. NOTE: In certain conditions, this function may + * be called an additional time, hence, we can't assert this to be true. + * For example, in the case of a timeout, this function will be called by + * both indirectly via the stm32_dmastop() logic and directly via the + * i2s_rxdma_timeout() logic. + */ + + /* Move all entries from the rx.act queue to the rx.done queue */ + + while (!sq_empty(&priv->rx.act)) + { + /* Remove the next buffer container from the rx.act list */ + + bfcontainer = (struct stm32_buffer_s *)sq_remfirst(&priv->rx.act); + + /* Report the result of the transfer */ + + bfcontainer->result = result; + + /* Add the completed buffer container to the tail of the rx.done + * queue + */ + + sq_addlast((sq_entry_t *)bfcontainer, &priv->rx.done); + } + + /* If the worker has completed running, then reschedule the working thread. + * REVISIT: There may be a race condition here. So we do nothing is the + * worker is not available. + */ + + if (work_available(&priv->rx.work)) + { + /* Schedule the TX DMA done processing to occur on the worker thread. */ + + ret = work_queue(HPWORK, &priv->rx.work, i2s_rx_worker, priv, 0); + if (ret != 0) + { + i2serr("ERROR: Failed to queue RX work: %d\n", ret); + } + } +} +#endif + +/**************************************************************************** + * Name: i2s_rxdma_callback + * + * Description: + * This callback function is invoked at the completion of the I2S RX DMA. + * + * Input Parameters: + * handle - The DMA handler + * arg - A pointer to the chip select struction + * result - The result of the DMA transfer + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef I2S_HAVE_RX +static void i2s_rxdma_callback(DMA_HANDLE handle, uint8_t result, void *arg) +{ + struct stm32_i2s_s *priv = (struct stm32_i2s_s *)arg; + DEBUGASSERT(priv != NULL); + + /* Cancel the watchdog timeout */ + + wd_cancel(&priv->rx.dog); + + /* Sample DMA registers at the time of the DMA completion */ + + i2s_rxdma_sample(priv, DMA_CALLBACK); + + /* REVISIT: We would like to the next DMA started here so that we do not + * get audio glitches at the boundaries between DMA transfers. + * Unfortunately, we cannot call stm32_dmasetup() from an interrupt + * handler! + */ + + /* Then schedule completion of the transfer to occur on the worker thread */ + + i2s_rx_schedule(priv, result); +} +#endif + +/**************************************************************************** + * Name: i2s_txdma_timeout + * + * Description: + * The RX watchdog timeout without completion of the RX DMA. + * + * Input Parameters: + * arg - The argument + * + * Returned Value: + * None + * + * Assumptions: + * Always called from the interrupt level with interrupts disabled. + * + ****************************************************************************/ + +#ifdef I2S_HAVE_TX +static void i2s_txdma_timeout(wdparm_t arg) +{ + struct stm32_i2s_s *priv = (struct stm32_i2s_s *)arg; + DEBUGASSERT(priv != NULL); + + /* Sample DMA registers at the time of the timeout */ + + i2s_txdma_sample(priv, DMA_TIMEOUT); + + /* Cancel the DMA */ + + stm32_dmastop(priv->tx.dma); + + /* Then schedule completion of the transfer to occur on the worker thread. + * NOTE: stm32_dmastop() will call the DMA complete callback with an error + * of -EINTR. So the following is just insurance and should have no + * effect if the worker is already schedule. + */ + + i2s_tx_schedule(priv, -ETIMEDOUT); +} +#endif + +/**************************************************************************** + * Name: i2s_txdma_setup + * + * Description: + * Setup and initiate the next TX DMA transfer + * + * Input Parameters: + * priv - I2S state instance + * + * Returned Value: + * OK on success; a negated errno value on failure + * + * Assumptions: + * Interrupts are disabled + * + ****************************************************************************/ + +#ifdef I2S_HAVE_TX +static int i2s_txdma_setup(struct stm32_i2s_s *priv) +{ + struct stm32_buffer_s *bfcontainer; + struct ap_buffer_s *apb; + uintptr_t samp; + uint32_t timeout; + apb_samp_t nbytes; + bool notimeout; + int ret; + + /* If there is already an active transmission in progress, then bail + * returning success. + */ + + if (!sq_empty(&priv->tx.act)) + { + return OK; + } + + /* If there are no pending transfer, then bail returning success */ + + if (sq_empty(&priv->tx.pend)) + { + return OK; + } + + /* Initialize DMA register sampling */ + + i2s_txdma_sampleinit(priv); + + /* Loop, adding each pending DMA */ + + timeout = 0; + notimeout = false; + + do + { + /* Remove the pending TX transfer at the head of the TX pending + * queue. + */ + + bfcontainer = (struct stm32_buffer_s *)sq_remfirst(&priv->tx.pend); + DEBUGASSERT(bfcontainer && bfcontainer->apb); + + apb = bfcontainer->apb; + + /* Get the transfer information, accounting for any data offset */ + + samp = (uintptr_t)&apb->samp[apb->curbyte]; + nbytes = apb->nbytes - apb->curbyte; + DEBUGASSERT((samp & priv->align) == 0 && (nbytes & priv->align) == 0); + + /* Configure DMA stream */ + + stm32_dmasetup(priv->tx.dma, priv->base + STM32_SPI_DR_OFFSET, + (uint32_t)samp, nbytes / 2, priv->txccr); + + /* Increment the DMA timeout */ + + if (bfcontainer->timeout > 0) + { + timeout += bfcontainer->timeout; + } + else + { + notimeout = true; + } + + /* Add the container to the list of active DMAs */ + + sq_addlast((sq_entry_t *)bfcontainer, &priv->tx.act); + } +#if 1 /* REVISIT: Chained TX transfers */ + while (0); +#else + while (!sq_empty(&priv->tx.pend)); +#endif + + /* Sample DMA registers */ + + i2s_txdma_sample(priv, DMA_AFTER_SETUP); + + /* Start the DMA, saving the container as the current active transfer */ + + stm32_dmastart(priv->tx.dma, i2s_txdma_callback, priv, true); + + i2s_txdma_sample(priv, DMA_AFTER_START); + + /* Enable the transmitter */ + + i2s_putreg(priv, STM32_SPI_CR2_OFFSET, + i2s_getreg(priv, STM32_SPI_CR2_OFFSET) | SPI_CR2_TXDMAEN); + + /* Start a watchdog to catch DMA timeouts */ + + if (!notimeout) + { + ret = wd_start(&priv->tx.dog, timeout, + i2s_txdma_timeout, (wdparm_t)priv); + + /* Check if we have successfully started the watchdog timer. Note + * that we do nothing in the case of failure to start the timer. We + * are already committed to the DMA anyway. Let's just hope that the + * DMA does not hang. + */ + + if (ret < 0) + { + i2serr("ERROR: wd_start failed: %d\n", ret); + } + } + + return OK; +} +#endif + +/**************************************************************************** + * Name: i2s_tx_worker + * + * Description: + * TX transfer done worker + * + * Input Parameters: + * arg - the I2S device instance cast to void* + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef I2S_HAVE_TX +static void i2s_tx_worker(void *arg) +{ + struct stm32_i2s_s *priv = (struct stm32_i2s_s *)arg; + struct stm32_buffer_s *bfcontainer; + irqstate_t flags; + + DEBUGASSERT(priv); + + /* When the transfer was started, the active buffer containers were removed + * from the tx.pend queue and saved in the tx.act queue. We get here when + * the DMA is finished... either successfully, with a DMA error, or with a + * DMA timeout. + * + * In any case, the buffer containers in tx.act will be moved to the end + * of the tx.done queue and tx.act will be emptied before this worker is + * started. + * + * REVISIT: Normal DMA callback processing should restart the DMA + * immediately to avoid audio artifacts at the boundaries between DMA + * transfers. Unfortunately, the DMA callback occurs at the interrupt + * level and we cannot call dma_txsetup() from the interrupt level. + * So we have to start the next DMA here. + */ + + i2sinfo("tx.act.head=%p tx.done.head=%p\n", + priv->tx.act.head, priv->tx.done.head); + + /* Check if the DMA is IDLE */ + + if (sq_empty(&priv->tx.act)) + { +#ifdef CONFIG_STM32_I2S_DMADEBUG + bfcontainer = (struct stm32_buffer_s *)sq_peek(&priv->tx.done); + if (bfcontainer) + { + /* Dump the DMA registers */ + + i2s_txdma_sampledone(priv, bfcontainer->result); + } +#endif + + /* Then start the next DMA. This must be done with interrupts + * disabled. + */ + + flags = enter_critical_section(); + i2s_txdma_setup(priv); + leave_critical_section(flags); + } + + /* Process each buffer in the tx.done queue */ + + while (sq_peek(&priv->tx.done) != NULL) + { + /* Remove the buffer container from the tx.done queue. NOTE that + * interrupts must be enabled to do this because the tx.done queue is + * also modified from the interrupt level. + */ + + flags = enter_critical_section(); + bfcontainer = (struct stm32_buffer_s *)sq_remfirst(&priv->tx.done); + leave_critical_section(flags); + + /* Perform the TX transfer done callback */ + + DEBUGASSERT(bfcontainer && bfcontainer->callback); + bfcontainer->callback(&priv->dev, bfcontainer->apb, + bfcontainer->arg, bfcontainer->result); + + /* Release our reference on the audio buffer. This may very likely + * cause the audio buffer to be freed. + */ + + apb_free(bfcontainer->apb); + + /* And release the buffer container */ + + i2s_buf_free(priv, bfcontainer); + } +} +#endif + +/**************************************************************************** + * Name: i2s_tx_schedule + * + * Description: + * An TX DMA completion or timeout has occurred. Schedule processing on + * the working thread. + * + * Input Parameters: + * handle - The DMA handler + * arg - A pointer to the chip select struction + * result - The result of the DMA transfer + * + * Returned Value: + * None + * + * Assumptions: + * - Interrupts are disabled + * - The TX timeout has been canceled. + * + ****************************************************************************/ + +#ifdef I2S_HAVE_TX +static void i2s_tx_schedule(struct stm32_i2s_s *priv, int result) +{ + struct stm32_buffer_s *bfcontainer; + int ret; + + /* Upon entry, the transfer(s) that just completed are the ones in the + * priv->tx.act queue. NOTE: In certain conditions, this function may + * be called an additional time, hence, we can't assert this to be true. + * For example, in the case of a timeout, this function will be called by + * both indirectly via the stm32_dmastop() logic and directly via the + * i2s_txdma_timeout() logic. + */ + + /* Move all entries from the tx.act queue to the tx.done queue */ + + while (!sq_empty(&priv->tx.act)) + { + /* Remove the next buffer container from the tx.act list */ + + bfcontainer = (struct stm32_buffer_s *)sq_remfirst(&priv->tx.act); + + /* Report the result of the transfer */ + + bfcontainer->result = result; + + /* Add the completed buffer container to the tail of the tx.done + * queue + */ + + sq_addlast((sq_entry_t *)bfcontainer, &priv->tx.done); + } + + /* If the worker has completed running, then reschedule the working thread. + * REVISIT: There may be a race condition here. So we do nothing is the + * worker is not available. + */ + + if (work_available(&priv->tx.work)) + { + /* Schedule the TX DMA done processing to occur on the worker thread. */ + + ret = work_queue(HPWORK, &priv->tx.work, i2s_tx_worker, priv, 0); + if (ret != 0) + { + i2serr("ERROR: Failed to queue TX work: %d\n", ret); + } + } +} +#endif + +/**************************************************************************** + * Name: i2s_txdma_callback + * + * Description: + * This callback function is invoked at the completion of the I2S TX DMA. + * + * Input Parameters: + * handle - The DMA handler + * arg - A pointer to the chip select struction + * result - The result of the DMA transfer + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef I2S_HAVE_TX +static void i2s_txdma_callback(DMA_HANDLE handle, uint8_t result, void *arg) +{ + struct stm32_i2s_s *priv = (struct stm32_i2s_s *)arg; + DEBUGASSERT(priv != NULL); + + /* Cancel the watchdog timeout */ + + wd_cancel(&priv->tx.dog); + + /* Sample DMA registers at the time of the DMA completion */ + + i2s_txdma_sample(priv, DMA_CALLBACK); + + /* REVISIT: We would like to the next DMA started here so that we do not + * get audio glitches at the boundaries between DMA transfers. + * Unfortunately, we cannot call stm32_dmasetup() from an interrupt + * handler! + */ + + /* Then schedule completion of the transfer to occur on the worker thread */ + + i2s_tx_schedule(priv, result); +} +#endif + +/**************************************************************************** + * Name: i2s_checkwidth + * + * Description: + * Check for a valid bit width. The I2S is capable of handling most any + * bit width from 8 to 16, but the DMA logic in this driver is constrained + * to 8- and 16-bit data widths + * + * Input Parameters: + * dev - Device-specific state data + * rate - The I2S sample rate in samples (not bits) per second + * + * Returned Value: + * Returns the resulting bitrate + * + ****************************************************************************/ + +static int i2s_checkwidth(struct stm32_i2s_s *priv, int bits) +{ + /* The I2S can handle most any bit width from 8 to 32. However, the DMA + * logic here is constrained to byte, half-word, and word sizes. + */ + + switch (bits) + { + case 8: + priv->align = 0; + break; + + case 16: + priv->align = 1; + break; + + default: + i2serr("ERROR: Unsupported or invalid data width: %d\n", bits); + return (bits < 8 || bits > 16) ? -EINVAL : -ENOSYS; + } + + /* Save the new data width */ + + priv->datalen = bits; + return OK; +} + +/**************************************************************************** + * Name: stm32_i2s_rxsamplerate + * + * Description: + * Set the I2S RX sample rate. NOTE: This will have no effect if (1) the + * driver does not support an I2C receiver or if (2) the sample rate is + * driven by the I2S frame clock. This may also have unexpected side- + * effects of the RX sample is coupled with the TX sample rate. + * + * Input Parameters: + * dev - Device-specific state data + * rate - The I2S sample rate in samples (not bits) per second + * + * Returned Value: + * Returns the resulting bitrate + * + ****************************************************************************/ + +static uint32_t stm32_i2s_rxsamplerate(struct i2s_dev_s *dev, uint32_t rate) +{ +#if defined(I2S_HAVE_RX) && defined(I2S_HAVE_MCK) + struct stm32_i2s_s *priv = (struct stm32_i2s_s *)dev; + DEBUGASSERT(priv && priv->samplerate >= 0 && rate > 0); + + /* Check if the receiver is driven by the MCK */ + + if (priv->samplerate != rate) + { + /* Save the new sample rate and update the MCK divider */ + + priv->samplerate = rate; + return i2s_mckdivider(priv); + } +#endif + + return 0; +} + +/**************************************************************************** + * Name: stm32_i2s_rxdatawidth + * + * Description: + * Set the I2S RX data width. The RX bitrate is determined by + * sample_rate * data_width. + * + * Input Parameters: + * dev - Device-specific state data + * width - The I2S data with in bits. + * + * Returned Value: + * Returns the resulting bitrate + * + ****************************************************************************/ + +static uint32_t stm32_i2s_rxdatawidth(struct i2s_dev_s *dev, int bits) +{ +#ifdef I2S_HAVE_RX + struct stm32_i2s_s *priv = (struct stm32_i2s_s *)dev; + int ret; + + DEBUGASSERT(priv && bits > 1); + + /* Check if this is a bit width that we are configured to handle */ + + ret = i2s_checkwidth(priv, bits); + if (ret < 0) + { + i2serr("ERROR: i2s_checkwidth failed: %d\n", ret); + return 0; + } + + /* Update the DMA flags */ + + ret = i2s_dma_flags(priv); + if (ret < 0) + { + i2serr("ERROR: i2s_dma_flags failed: %d\n", ret); + return 0; + } + +#endif + + return 0; +} + +/**************************************************************************** + * Name: stm32_i2s_receive + * + * Description: + * Receive a block of data from I2S. + * + * Input Parameters: + * dev - Device-specific state data + * apb - A pointer to the audio buffer in which to receive data + * callback - A user provided callback function that will be called at + * the completion of the transfer. The callback will be + * performed in the context of the worker thread. + * arg - An opaque argument that will be provided to the callback + * when the transfer complete + * timeout - The timeout value to use. The transfer will be canceled + * and an ETIMEDOUT error will be reported if this timeout + * elapsed without completion of the DMA transfer. Units + * are system clock ticks. Zero means no timeout. + * + * Returned Value: + * OK on success; a negated errno value on failure. NOTE: This function + * only enqueues the transfer and returns immediately. Success here only + * means that the transfer was enqueued correctly. + * + * When the transfer is complete, a 'result' value will be provided as + * an argument to the callback function that will indicate if the transfer + * failed. + * + ****************************************************************************/ + +static int stm32_i2s_receive(struct i2s_dev_s *dev, struct ap_buffer_s *apb, + i2s_callback_t callback, void *arg, uint32_t timeout) +{ + struct stm32_i2s_s *priv = (struct stm32_i2s_s *)dev; +#ifdef I2S_HAVE_RX + struct stm32_buffer_s *bfcontainer; + irqstate_t flags; + int ret; +#endif + + DEBUGASSERT(priv && apb && ((uintptr_t)apb->samp & priv->align) == 0); + i2sinfo("apb=%p nmaxbytes=%d arg=%p timeout=%" PRId32 "\n", + apb, apb->nmaxbytes, arg, timeout); + + i2s_init_buffer(apb->samp, apb->nmaxbytes); + +#ifdef I2S_HAVE_RX + /* Allocate a buffer container in advance */ + + bfcontainer = i2s_buf_allocate(priv); + DEBUGASSERT(bfcontainer); + + /* Get exclusive access to the I2S driver data */ + + ret = nxmutex_lock(&priv->lock); + if (ret < 0) + { + goto errout_with_buf; + } + + /* Has the RX channel been enabled? */ + + if (!priv->rxenab) + { + i2serr("ERROR: I2S%d has no receiver\n", priv->i2sno); + ret = -EAGAIN; + goto errout_with_lock; + } + + /* Add a reference to the audio buffer */ + + apb_reference(apb); + + /* Initialize the buffer container structure */ + + bfcontainer->callback = (void *)callback; + bfcontainer->timeout = timeout; + bfcontainer->arg = arg; + bfcontainer->apb = apb; + bfcontainer->result = -EBUSY; + + /* Add the buffer container to the end of the RX pending queue */ + + flags = enter_critical_section(); + sq_addlast((sq_entry_t *)bfcontainer, &priv->rx.pend); + + /* Then start the next transfer. If there is already a transfer in + * progress, then this will do nothing. + */ + + ret = i2s_rxdma_setup(priv); + DEBUGASSERT(ret == OK); + leave_critical_section(flags); + nxmutex_unlock(&priv->lock); + return OK; + +errout_with_lock: + nxmutex_unlock(&priv->lock); + +errout_with_buf: + i2s_buf_free(priv, bfcontainer); + return ret; + +#else + i2serr("ERROR: I2S%d has no receiver\n", priv->i2sno); + UNUSED(priv); + return -ENOSYS; +#endif +} + +static int stm32_i2s_roundf(float num) +{ + if (((int)(num + 0.5f)) > num) + { + return num + 1; + } + + return num; +} + +/**************************************************************************** + * Name: stm32_i2s_txsamplerate + * + * Description: + * Set the I2S TX sample rate. NOTE: This will have no effect if (1) the + * driver does not support an I2S transmitter or if (2) the sample rate is + * driven by the I2S frame clock. This may also have unexpected side- + * effects of the TX sample is coupled with the RX sample rate. + * + * Input Parameters: + * dev - Device-specific state data + * rate - The I2S sample rate in samples (not bits) per second + * + * Returned Value: + * Returns the resulting bitrate + * + ****************************************************************************/ + +static uint32_t stm32_i2s_txsamplerate(struct i2s_dev_s *dev, uint32_t rate) +{ +#if defined(I2S_HAVE_TX) && defined(I2S_HAVE_MCK) + struct stm32_i2s_s *priv = (struct stm32_i2s_s *)dev; + + DEBUGASSERT(priv && priv->samplerate >= 0 && rate > 0); + + /* Check if the receiver is driven by the MCK/2 */ + + if (priv->samplerate != rate) + { + /* Save the new sample rate and update the MCK/2 divider */ + + priv->samplerate = rate; + return i2s_mckdivider(priv); + } +#endif + + return 0; +} + +/**************************************************************************** + * Name: stm32_i2s_txdatawidth + * + * Description: + * Set the I2S TX data width. The TX bitrate is determined by + * sample_rate * data_width. + * + * Input Parameters: + * dev - Device-specific state data + * width - The I2S data with in bits. + * + * Returned Value: + * Returns the resulting bitrate + * + ****************************************************************************/ + +static uint32_t stm32_i2s_txdatawidth(struct i2s_dev_s *dev, int bits) +{ +#ifdef I2S_HAVE_TX + struct stm32_i2s_s *priv = (struct stm32_i2s_s *)dev; + int ret; + + i2sinfo("Data width bits of tx = %d\n", bits); + DEBUGASSERT(priv && bits > 1); + + /* Check if this is a bit width that we are configured to handle */ + + ret = i2s_checkwidth(priv, bits); + if (ret < 0) + { + i2serr("ERROR: i2s_checkwidth failed: %d\n", ret); + return 0; + } + + /* Update the DMA flags */ + + ret = i2s_dma_flags(priv); + if (ret < 0) + { + i2serr("ERROR: i2s_dma_flags failed: %d\n", ret); + return 0; + } +#endif + + return 0; +} + +/**************************************************************************** + * Name: stm32_i2s_send + * + * Description: + * Send a block of data on I2S. + * + * Input Parameters: + * dev - Device-specific state data + * apb - A pointer to the audio buffer from which to send data + * callback - A user provided callback function that will be called at + * the completion of the transfer. The callback will be + * performed in the context of the worker thread. + * arg - An opaque argument that will be provided to the callback + * when the transfer complete + * timeout - The timeout value to use. The transfer will be canceled + * and an ETIMEDOUT error will be reported if this timeout + * elapsed without completion of the DMA transfer. Units + * are system clock ticks. Zero means no timeout. + * + * Returned Value: + * OK on success; a negated errno value on failure. NOTE: This function + * only enqueues the transfer and returns immediately. Success here only + * means that the transfer was enqueued correctly. + * + * When the transfer is complete, a 'result' value will be provided as + * an argument to the callback function that will indicate if the transfer + * failed. + * + ****************************************************************************/ + +static int stm32_i2s_send(struct i2s_dev_s *dev, struct ap_buffer_s *apb, + i2s_callback_t callback, void *arg, uint32_t timeout) +{ + struct stm32_i2s_s *priv = (struct stm32_i2s_s *)dev; +#ifdef I2S_HAVE_TX + struct stm32_buffer_s *bfcontainer; + irqstate_t flags; + int ret; +#endif + + /* Make sure that we have valid pointers that that the data has uint32_t + * alignment. + */ + + DEBUGASSERT(priv && apb); + i2sinfo("apb=%p nbytes=%d arg=%p timeout=%" PRId32 "\n", + apb, apb->nbytes - apb->curbyte, arg, timeout); + + i2s_dump_buffer("Sending", &apb->samp[apb->curbyte], + apb->nbytes - apb->curbyte); + DEBUGASSERT(((uintptr_t)&apb->samp[apb->curbyte] & priv->align) == 0); + +#ifdef I2S_HAVE_TX + /* Allocate a buffer container in advance */ + + bfcontainer = i2s_buf_allocate(priv); + DEBUGASSERT(bfcontainer); + + /* Get exclusive access to the I2S driver data */ + + ret = nxmutex_lock(&priv->lock); + if (ret < 0) + { + goto errout_with_buf; + } + + /* Has the TX channel been enabled? */ + + if (!priv->txenab) + { + i2serr("ERROR: I2S%d has no transmitter\n", priv->i2sno); + ret = -EAGAIN; + goto errout_with_lock; + } + + /* Add a reference to the audio buffer */ + + apb_reference(apb); + + /* Initialize the buffer container structure */ + + bfcontainer->callback = (void *)callback; + bfcontainer->timeout = timeout; + bfcontainer->arg = arg; + bfcontainer->apb = apb; + bfcontainer->result = -EBUSY; + + /* Add the buffer container to the end of the TX pending queue */ + + flags = enter_critical_section(); + sq_addlast((sq_entry_t *)bfcontainer, &priv->tx.pend); + + /* Then start the next transfer. If there is already a transfer in + * progress, then this will do nothing. + */ + + ret = i2s_txdma_setup(priv); + DEBUGASSERT(ret == OK); + leave_critical_section(flags); + nxmutex_unlock(&priv->lock); + return OK; + +errout_with_lock: + nxmutex_unlock(&priv->lock); + +errout_with_buf: + i2s_buf_free(priv, bfcontainer); + return ret; + +#else + i2serr("ERROR: I2S%d has no transmitter\n", priv->i2sno); + UNUSED(priv); + return -ENOSYS; +#endif +} + +/**************************************************************************** + * Name: i2s_mckdivider + * + * Description: + * Setup the MCK divider based on the currently selected data width and + * the sample rate + * + * Input Parameters: + * priv - I2C device structure (only the sample rate and data length is + * needed at this point). + * + * Returned Value: + * The current bitrate + * + ****************************************************************************/ + +static uint32_t i2s_mckdivider(struct stm32_i2s_s *priv) +{ +#ifdef I2S_HAVE_MCK + uint32_t bitrate; + uint32_t regval; + + uint16_t pllr = 5; + uint16_t plln = 256; + uint16_t div = 12; + uint16_t odd = 1; + + DEBUGASSERT(priv && priv->samplerate >= 0 && priv->datalen > 0); + + /* A zero sample rate means to disable the MCK/2 clock */ + + if (priv->samplerate == 0) + { + bitrate = 0; + regval = 0; + } + else + { + int R; + int n; + int od; + int napprox; + int diff; + int diff_min = 500000000; + + for (od = 0; od <= 1; ++od) + { + for (R = 2; R <= 7; ++R) + { + for (n = 2; n <= 256; ++n) + { + napprox = stm32_i2s_roundf(priv->samplerate / 1000000.0f * + (8 * 32 * R * (2 * n + od))); + if ((napprox > 432) || (napprox < 50)) + { + continue; + } + + diff = abs(priv->samplerate - 1000000 * napprox / + (8 * 32 * R * (2 * n + od))); + if (diff_min > diff) + { + diff_min = diff; + plln = napprox; + pllr = R; + div = n; + odd = od; + } + } + } + } + + /* Calculate the new bitrate in Hz */ + + bitrate = priv->samplerate * priv->datalen; + } + + /* Configure MCK divider */ + + /* Disable I2S */ + + i2s_putreg(priv, STM32_SPI_I2SCFGR_OFFSET, 0); + + /* I2S clock configuration */ + + putreg32((getreg32(STM32_RCC_CR) & (~RCC_CR_PLLI2SON)), STM32_RCC_CR); + + /* PLLI2S clock used as I2S clock source */ + + putreg32(((getreg32(STM32_RCC_CFGR)) & (~RCC_CFGR_I2SSRC)), + STM32_RCC_CFGR); + regval = (pllr << 28) | (plln << 6); + putreg32(regval, STM32_RCC_PLLI2SCFGR); + + /* Enable PLLI2S and wait until it is ready */ + + putreg32((getreg32(STM32_RCC_CR) | RCC_CR_PLLI2SON), STM32_RCC_CR); + while (!(getreg32(STM32_RCC_CR) & RCC_CR_PLLI2SRDY)); + + i2s_putreg(priv, STM32_SPI_I2SPR_OFFSET, + div | (odd << 8) | SPI_I2SPR_MCKOE); + i2s_putreg(priv, STM32_SPI_I2SCFGR_OFFSET, + SPI_I2SCFGR_I2SMOD | SPI_I2SCFGR_I2SCFG_MTX | SPI_I2SCFGR_I2SE); + +#if 0 + putreg32((getreg32(STM32_DMA1_HIFCR) | DMA_HIFCR_CTCIF7), + STM32_DMA1_HIFCR); +#endif + + putreg32((getreg32(STM32_DMA1_HIFCR) | 0x80000000), STM32_DMA1_HIFCR); + + return bitrate; +#else + return 0; +#endif +} + +/**************************************************************************** + * Name: i2s_dma_flags + * + * Description: + * Determine DMA FLAGS based on PID and data width + * + * Input Parameters: + * priv - Partially initialized I2C device structure. + * + * Returned Value: + * OK on success; a negated errno value on failure + * + ****************************************************************************/ + +static int i2s_dma_flags(struct stm32_i2s_s *priv) +{ + switch (priv->datalen) + { + case 8: + + /* Reconfigure the RX DMA (and TX DMA if applicable) */ + + priv->rxccr = SPI_RXDMA8_CONFIG; + priv->txccr = SPI_TXDMA8_CONFIG; + break; + + case 16: + priv->rxccr = SPI_RXDMA16_CONFIG; + priv->txccr = SPI_TXDMA16_CONFIG; + break; + + default: + i2serr("ERROR: Unsupported data width: %d\n", priv->datalen); + return -ENOSYS; + } + + return OK; +} + +/**************************************************************************** + * Name: i2s_dma_allocate + * + * Description: + * Allocate I2S DMA channels + * + * Input Parameters: + * priv - Partially initialized I2S device structure. This function + * will complete the DMA specific portions of the initialization + * + * Returned Value: + * OK on success; A negated errno value on failure. + * + ****************************************************************************/ + +static int i2s_dma_allocate(struct stm32_i2s_s *priv) +{ + int ret; + + /* Get the DMA flags for this channel */ + + ret = i2s_dma_flags(priv); + if (ret < 0) + { + i2serr("ERROR: i2s_dma_flags failed: %d\n", ret); + return ret; + } + + /* Allocate DMA channels. These allocations exploit that fact that + * I2S2 is managed by DMA1 and I2S3 is managed by DMA2. Hence, + * the I2S number (i2sno) is the same as the DMA number. + */ + +#ifdef I2S_HAVE_RX + if (priv->rxenab) + { + /* Allocate an RX DMA channel */ + + priv->rx.dma = stm32_dmachannel(DMACHAN_I2S3_RX); + if (!priv->rx.dma) + { + i2serr("ERROR: Failed to allocate the RX DMA channel\n"); + goto errout; + } + } +#endif + +#ifdef I2S_HAVE_TX + if (priv->txenab) + { + /* Allocate a TX DMA channel */ + + priv->tx.dma = stm32_dmachannel(DMACHAN_I2S3_TX); + if (!priv->tx.dma) + { + i2serr("ERROR: Failed to allocate the TX DMA channel\n"); + goto errout; + } + } +#endif + + /* Success exit */ + + return OK; + + /* Error exit */ + +errout: + i2s_dma_free(priv); + return -ENOMEM; +} + +/**************************************************************************** + * Name: i2s_dma_free + * + * Description: + * Release DMA-related resources allocated by i2s_dma_allocate() + * + * Input Parameters: + * priv - Partially initialized I2C device structure. + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void i2s_dma_free(struct stm32_i2s_s *priv) +{ +#ifdef I2S_HAVE_TX + wd_cancel(&priv->tx.dog); + if (priv->tx.dma) + { + stm32_dmafree(priv->tx.dma); + } +#endif + +#ifdef I2S_HAVE_RX + wd_cancel(&priv->rx.dog); + if (priv->rx.dma) + { + stm32_dmafree(priv->rx.dma); + } +#endif +} + +/**************************************************************************** + * Name: i2s2_configure + * + * Description: + * Configure I2S2 + * + * Input Parameters: + * priv - Partially initialized I2C device structure. These functions + * will complete the I2S specific portions of the initialization + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_I2S2 +static void i2s2_configure(struct stm32_i2s_s *priv) +{ + /* Configure multiplexed pins as connected on the board. Chip + * select pins must be selected by board-specific logic. + */ + + priv->base = STM32_I2S2_BASE; + +#ifdef CONFIG_STM32_I2S2_RX + priv->rxenab = true; + + if (!priv->initialized) + { + /* Configure I2S2 pins: MCK, SD, CK, WS */ + + stm32_configgpio(GPIO_I2S2_MCK); + stm32_configgpio(GPIO_I2S2_SD); + stm32_configgpio(GPIO_I2S2_CK); + stm32_configgpio(GPIO_I2S2_WS); + priv->initialized = true; + } +#endif /* CONFIG_STM32_I2S2_RX */ + +#ifdef CONFIG_STM32_I2S2_TX + priv->txenab = true; + + /* Only configure if the port is not already configured */ + + if (!priv->initialized) + { + /* Configure I2S2 pins: MCK, SD, CK, WS */ + + stm32_configgpio(GPIO_I2S2_MCK); + stm32_configgpio(GPIO_I2S2_SD); + stm32_configgpio(GPIO_I2S2_CK); + stm32_configgpio(GPIO_I2S2_WS); + priv->initialized = true; + } +#endif /* CONFIG_STM32_I2S2_TX */ + + /* Configure driver state specific to this I2S peripheral */ + + priv->datalen = CONFIG_STM32_I2S2_DATALEN; +#ifdef CONFIG_DEBUG + priv->align = STM32_I2S2_DATAMASK; +#endif +} +#endif /* CONFIG_STM32_I2S2 */ + +/**************************************************************************** + * Name: i2s3_configure + * + * Description: + * Configure I2S3 + * + * Input Parameters: + * priv - Partially initialized I2C device structure. These functions + * will complete the I2S specific portions of the initialization + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_I2S3 +static void i2s3_configure(struct stm32_i2s_s *priv) +{ + /* Configure multiplexed pins as connected on the board. Chip + * select pins must be selected by board-specific logic. + */ + + priv->base = STM32_I2S3_BASE; + +#ifdef CONFIG_STM32_I2S3_RX + priv->rxenab = true; + + if (!priv->initialized) + { + /* Configure I2S3 pins: MCK, SD, CK, WS */ + + stm32_configgpio(GPIO_I2S3_MCK); + stm32_configgpio(GPIO_I2S3_SD); + stm32_configgpio(GPIO_I2S3_CK); + stm32_configgpio(GPIO_I2S3_WS); + priv->initialized = true; + } +#endif /* CONFIG_STM32_I2S3_RX */ + +#ifdef CONFIG_STM32_I2S3_TX + priv->txenab = true; + + /* Only configure if the port is not already configured */ + + if (!priv->initialized) + { + /* Configure I2S3 pins: MCK, SD, CK, WS */ + + stm32_configgpio(GPIO_I2S3_MCK); + stm32_configgpio(GPIO_I2S3_SD); + stm32_configgpio(GPIO_I2S3_CK); + stm32_configgpio(GPIO_I2S3_WS); + priv->initialized = true; + } +#endif /* CONFIG_STM32_I2S3_TX */ + + /* Configure driver state specific to this I2S peripheral */ + + priv->datalen = CONFIG_STM32_I2S3_DATALEN; +#ifdef CONFIG_DEBUG + priv->align = STM32_I2S3_DATAMASK; +#endif +} +#endif /* CONFIG_STM32_I2S3 */ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_i2sbus_initialize + * + * Description: + * Initialize the selected i2S port + * + * Input Parameters: + * Port number (for hardware that has multiple I2S interfaces) + * + * Returned Value: + * Valid I2S device structure reference on success; a NULL on failure + * + ****************************************************************************/ + +struct i2s_dev_s *stm32_i2sbus_initialize(int port) +{ + struct stm32_i2s_s *priv = NULL; + irqstate_t flags; + int ret; + + /* The support STM32 parts have only a single I2S port */ + + i2sinfo("port: %d\n", port); + + /* Allocate a new state structure for this chip select. NOTE that there + * is no protection if the same chip select is used in two different + * chip select structures. + */ + + priv = kmm_zalloc(sizeof(struct stm32_i2s_s)); + if (!priv) + { + i2serr("ERROR: Failed to allocate a chip select structure\n"); + return NULL; + } + + /* Set up the initial state for this chip select structure. Other fields + * were zeroed by kmm_zalloc(). + */ + + /* Initialize the common parts for the I2S device structure */ + + nxmutex_init(&priv->lock); + priv->dev.ops = &g_i2sops; + priv->i2sno = port; + + /* Initialize buffering */ + + i2s_buf_initialize(priv); + + flags = enter_critical_section(); + +#ifdef CONFIG_STM32_I2S2 + if (port == 2) + { + /* Select I2S2 */ + + i2s2_configure(priv); + } + else +#endif +#ifdef CONFIG_STM32_I2S3 + if (port == 3) + { + /* Select I2S3 */ + + i2s3_configure(priv); + } + else +#endif + { + i2serr("ERROR: Unsupported I2S port: %d\n", port); + leave_critical_section(flags); + return NULL; + } + + /* Allocate DMA channels */ + + ret = i2s_dma_allocate(priv); + if (ret < 0) + { + goto errout_with_alloc; + } + + leave_critical_section(flags); + i2s_dump_regs(priv, "After initialization"); + + /* Success exit */ + + return &priv->dev; + + /* Failure exits */ + +errout_with_alloc: + leave_critical_section(flags); + nxmutex_destroy(&priv->lock); + nxsem_destroy(&priv->bufsem); + kmm_free(priv); + return NULL; +} +#endif /* I2S_HAVE_RX || I2S_HAVE_TX */ + +#endif /* CONFIG_STM32_I2S2 || CONFIG_STM32_I2S3 */ diff --git a/arch/arm/src/common/stm32/stm32_idle_m0_v1.c b/arch/arm/src/common/stm32/stm32_idle_m0_v1.c new file mode 100644 index 0000000000000..a9d6ff68a084b --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_idle_m0_v1.c @@ -0,0 +1,97 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_idle_m0_v1.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include + +#include "arm_internal.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Does the board support an IDLE LED to indicate that the board is in the + * IDLE state? + */ + +#if defined(CONFIG_ARCH_LEDS) && defined(LED_IDLE) +# define BEGIN_IDLE() board_autoled_on(LED_IDLE) +# define END_IDLE() board_autoled_off(LED_IDLE) +#else +# define BEGIN_IDLE() +# define END_IDLE() +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_idle + * + * Description: + * up_idle() is the logic that will be executed when there is no other + * ready-to-run task. This is processor idle time and will continue until + * some interrupt occurs to cause a context switch from the idle task. + * + * Processing in this state may be processor-specific. e.g., this is where + * power management operations might be performed. + * + ****************************************************************************/ + +void up_idle(void) +{ +#if defined(CONFIG_SUPPRESS_INTERRUPTS) || defined(CONFIG_SUPPRESS_TIMER_INTS) + /* If the system is idle and there are no timer interrupts, then process + * "fake" timer interrupts. Hopefully, something will wake up. + */ + + nxsched_process_timer(); +#else + +/* If the g_dma_inprogress is zero, then there is no DMA in progress. This + * value is needed in the IDLE loop to determine if the IDLE loop should + * go into lower power power consumption modes. According to the LPC17xx + * User Manual: "The DMA controller can continue to work in Sleep mode, and + * has access to the peripheral SRAMs and all peripheral registers. The + * flash memory and the Main SRAM are not available in Sleep mode, they are + * disabled in order to save power." + */ + +#ifdef CONFIG_STM32_GPDMA + if (g_dma_inprogress == 0) +#endif + { + /* Sleep until an interrupt occurs in order to save power */ + + BEGIN_IDLE(); + asm("WFI"); + END_IDLE(); + } +#endif +} diff --git a/arch/arm/src/common/stm32/stm32_idle_m3m4_v1.c b/arch/arm/src/common/stm32/stm32_idle_m3m4_v1.c new file mode 100644 index 0000000000000..19f57a3117eac --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_idle_m3m4_v1.c @@ -0,0 +1,197 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_idle_m3m4_v1.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include + +#include +#include +#include + +#include + +#include "chip.h" +#include "stm32_pm.h" +#include "arm_internal.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Does the board support an IDLE LED to indicate that the board is in the + * IDLE state? + */ + +#if defined(CONFIG_ARCH_LEDS) && defined(LED_IDLE) +# define BEGIN_IDLE() board_autoled_on(LED_IDLE) +# define END_IDLE() board_autoled_off(LED_IDLE) +#else +# define BEGIN_IDLE() +# define END_IDLE() +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_idlepm + * + * Description: + * Perform IDLE state power management. + * + ****************************************************************************/ + +#ifdef CONFIG_PM +static void up_idlepm(void) +{ + static enum pm_state_e oldstate = PM_NORMAL; + enum pm_state_e newstate; + irqstate_t flags; + int ret; + + /* Decide, which power saving level can be obtained */ + + newstate = pm_checkstate(PM_IDLE_DOMAIN); + + /* Check for state changes */ + + if (newstate != oldstate) + { + flags = enter_critical_section(); + + /* Perform board-specific, state-dependent logic here */ + + _info("newstate= %d oldstate=%d\n", newstate, oldstate); + + /* Then force the global state change */ + + ret = pm_changestate(PM_IDLE_DOMAIN, newstate); + if (ret < 0) + { + /* The new state change failed, revert to the preceding state */ + + pm_changestate(PM_IDLE_DOMAIN, oldstate); + } + else + { + /* Save the new state */ + + oldstate = newstate; + } + + /* MCU-specific power management logic */ + + switch (newstate) + { + case PM_NORMAL: + break; + + case PM_IDLE: + break; + + case PM_STANDBY: + stm32_pmstop(true); + break; + + case PM_SLEEP: + stm32_pmstandby(); + break; + + default: + break; + } + + leave_critical_section(flags); + } +} +#else +# define up_idlepm() +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_idle + * + * Description: + * up_idle() is the logic that will be executed when there is no other + * ready-to-run task. This is processor idle time and will continue until + * some interrupt occurs to cause a context switch from the idle task. + * + * Processing in this state may be processor-specific. e.g., this is where + * power management operations might be performed. + * + ****************************************************************************/ + +void up_idle(void) +{ +#if defined(CONFIG_SUPPRESS_INTERRUPTS) || defined(CONFIG_SUPPRESS_TIMER_INTS) + /* If the system is idle and there are no timer interrupts, then process + * "fake" timer interrupts. Hopefully, something will wake up. + */ + + nxsched_process_timer(); +#else + + /* Perform IDLE mode power management */ + + up_idlepm(); + + /* Sleep until an interrupt occurs to save power. + * + * NOTE: There is an STM32F107 errata that is fixed by the following + * workaround: + * + * "2.17.11 Ethernet DMA not working after WFI/WFE instruction + * Description + * If a WFI/WFE instruction is executed to put the system in sleep mode + * while the Ethernet MAC master clock on the AHB bus matrix is ON and + * all remaining masters clocks are OFF, the Ethernet DMA will be not + * able to perform any AHB master accesses during sleep mode." + * + * Workaround + * Enable DMA1 or DMA2 clocks in the RCC_AHBENR register before + * executing the WFI/WFE instruction." + * + * Here the workaround is just to avoid SLEEP mode for the connectivity + * line parts if Ethernet is enabled. The errate recommends a more + * general solution: Enabling DMA1/2 clocking in stm32f10xx_rcc.c if the + * STM32107 Ethernet peripheral is enabled. + */ + +#if !defined(CONFIG_STM32_CONNECTIVITYLINE) || !defined(CONFIG_STM32_ETHMAC) +#if !(defined(CONFIG_DEBUG_SYMBOLS) && defined(CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG)) + BEGIN_IDLE(); + asm("WFI"); + END_IDLE(); +#endif +#endif +#endif +} diff --git a/arch/arm/src/common/stm32/stm32_irq_m0_v1.c b/arch/arm/src/common/stm32/stm32_irq_m0_v1.c new file mode 100644 index 0000000000000..fb71ce0917a1e --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_irq_m0_v1.c @@ -0,0 +1,314 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_irq_m0_v1.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include +#include +#include + +#include "nvic.h" +#include "arm_internal.h" + +/* #include "stm32_irq.h" */ + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Get a 32-bit version of the default priority */ + +#define DEFPRIORITY32 \ + (NVIC_SYSH_PRIORITY_DEFAULT << 24 | NVIC_SYSH_PRIORITY_DEFAULT << 16 | \ + NVIC_SYSH_PRIORITY_DEFAULT << 8 | NVIC_SYSH_PRIORITY_DEFAULT) + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_dumpnvic + * + * Description: + * Dump some interesting NVIC registers + * + ****************************************************************************/ + +#if defined(CONFIG_DEBUG_IRQ_INFO) +static void stm32_dumpnvic(const char *msg, int irq) +{ + irqstate_t flags; + + flags = enter_critical_section(); + + irqinfo("NVIC (%s, irq=%d):\n", msg, irq); + irqinfo(" ISER: %08" PRIx32 " ICER: %08" PRIx32 "\n", + getreg32(ARMV6M_NVIC_ISER), getreg32(ARMV6M_NVIC_ICER)); + irqinfo(" ISPR: %08" PRIx32 " ICPR: %08" PRIx32 "\n", + getreg32(ARMV6M_NVIC_ISPR), getreg32(ARMV6M_NVIC_ICPR)); + irqinfo(" IRQ PRIO: %08" PRIx32 " %08" PRIx32 " %08" PRIx32 + " %08" PRIx32 "\n", + getreg32(ARMV6M_NVIC_IPR0), getreg32(ARMV6M_NVIC_IPR1), + getreg32(ARMV6M_NVIC_IPR2), getreg32(ARMV6M_NVIC_IPR3)); + irqinfo(" %08" PRIx32 " %08" PRIx32 " %08" PRIx32 + " %08" PRIx32 "\n", + getreg32(ARMV6M_NVIC_IPR4), getreg32(ARMV6M_NVIC_IPR5), + getreg32(ARMV6M_NVIC_IPR6), getreg32(ARMV6M_NVIC_IPR7)); + + irqinfo("SYSCON:\n"); + irqinfo(" CPUID: %08" PRIx32 "\n", + getreg32(ARMV6M_SYSCON_CPUID)); + irqinfo(" ICSR: %08" PRIx32 " AIRCR: %08" PRIx32 "\n", + getreg32(ARMV6M_SYSCON_ICSR), getreg32(ARMV6M_SYSCON_AIRCR)); + irqinfo(" SCR: %08" PRIx32 " CCR: %08" PRIx32 "\n", + getreg32(ARMV6M_SYSCON_SCR), getreg32(ARMV6M_SYSCON_CCR)); + irqinfo(" SHPR2: %08" PRIx32 " SHPR3: %08" PRIx32 "\n", + getreg32(ARMV6M_SYSCON_SHPR2), getreg32(ARMV6M_SYSCON_SHPR3)); + + leave_critical_section(flags); +} + +#else +# define stm32_dumpnvic(msg, irq) +#endif + +/**************************************************************************** + * Name: stm32_nmi, stm32_busfault, stm32_usagefault, stm32_pendsv, + * stm32_dbgmonitor, stm32_pendsv, stm32_reserved + * + * Description: + * Handlers for various exceptions. None are handled and all are fatal + * error conditions. The only advantage these provided over the default + * unexpected interrupt handler is that they provide a diagnostic output. + * + ****************************************************************************/ + +#ifdef CONFIG_DEBUG_FEATURES +static int stm32_nmi(int irq, void *context, void *arg) +{ + up_irq_save(); + _err("PANIC!!! NMI received\n"); + PANIC(); + return 0; +} + +static int stm32_pendsv(int irq, void *context, void *arg) +{ + up_irq_save(); + _err("PANIC!!! PendSV received\n"); + PANIC(); + return 0; +} + +static int stm32_reserved(int irq, void *context, void *arg) +{ + up_irq_save(); + _err("PANIC!!! Reserved interrupt\n"); + PANIC(); + return 0; +} +#endif + +/**************************************************************************** + * Name: stm32_clrpend + * + * Description: + * Clear a pending interrupt at the NVIC. + * + ****************************************************************************/ + +static inline void stm32_clrpend(int irq) +{ + /* This will be called on each interrupt exit whether the interrupt can be + * enambled or not. So this assertion is necessarily lame. + */ + + DEBUGASSERT((unsigned)irq < NR_IRQS); + + /* Check for an external interrupt */ + + if (irq >= STM32_IRQ_EXTINT && irq < (STM32_IRQ_EXTINT + 32)) + { + /* Set the appropriate bit in the ISER register to enable the + * interrupt + */ + + putreg32((1 << (irq - STM32_IRQ_EXTINT)), ARMV6M_NVIC_ICPR); + } +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_irqinitialize + ****************************************************************************/ + +void up_irqinitialize(void) +{ + uint32_t regaddr; + int i; + + /* Disable all interrupts */ + + putreg32(0xffffffff, ARMV6M_NVIC_ICER); + + /* Set all interrupts (and exceptions) to the default priority */ + + putreg32(DEFPRIORITY32, ARMV6M_SYSCON_SHPR2); + putreg32(DEFPRIORITY32, ARMV6M_SYSCON_SHPR3); + + /* Now set all of the interrupt lines to the default priority */ + + for (i = 0; i < 8; i++) + { + regaddr = ARMV6M_NVIC_IPR(i); + putreg32(DEFPRIORITY32, regaddr); + } + + /* Attach the SVCall and Hard Fault exception handlers. The SVCall + * exception is used for performing context switches; The Hard Fault + * must also be caught because a SVCall may show up as a Hard Fault + * under certain conditions. + */ + + irq_attach(STM32_IRQ_SVCALL, arm_svcall, NULL); + irq_attach(STM32_IRQ_HARDFAULT, arm_hardfault, NULL); + + /* Attach all other processor exceptions (except reset and sys tick) */ + +#ifdef CONFIG_DEBUG_FEATURES + irq_attach(STM32_IRQ_NMI, stm32_nmi, NULL); + irq_attach(STM32_IRQ_PENDSV, stm32_pendsv, NULL); + irq_attach(STM32_IRQ_RESERVED, stm32_reserved, NULL); +#endif + + stm32_dumpnvic("initial", NR_IRQS); + + /* Initialize logic to support a second level of interrupt decoding for + * configured pin interrupts. + */ + +#ifdef CONFIG_STM32_GPIOIRQ + stm32_gpioirqinitialize(); +#endif + +#ifndef CONFIG_SUPPRESS_INTERRUPTS + + /* And finally, enable interrupts */ + + arm_color_intstack(); + up_irq_enable(); +#endif +} + +/**************************************************************************** + * Name: up_disable_irq + * + * Description: + * Disable the IRQ specified by 'irq' + * + ****************************************************************************/ + +void up_disable_irq(int irq) +{ + DEBUGASSERT((unsigned)irq < NR_IRQS); + + /* Check for an external interrupt */ + + if (irq >= STM32_IRQ_EXTINT && irq < (STM32_IRQ_EXTINT + 32)) + { + /* Set the appropriate bit in the ICER register to disable the + * interrupt + */ + + putreg32((1 << (irq - STM32_IRQ_EXTINT)), ARMV6M_NVIC_ICER); + } + + /* Handle processor exceptions. Only SysTick can be disabled */ + + else if (irq == STM32_IRQ_SYSTICK) + { + modifyreg32(ARMV6M_SYSTICK_CSR, SYSTICK_CSR_ENABLE, 0); + } + + stm32_dumpnvic("disable", irq); +} + +/**************************************************************************** + * Name: up_enable_irq + * + * Description: + * Enable the IRQ specified by 'irq' + * + ****************************************************************************/ + +void up_enable_irq(int irq) +{ + /* This will be called on each interrupt exit whether the interrupt can be + * enabled or not. So this assertion is necessarily lame. + */ + + DEBUGASSERT((unsigned)irq < NR_IRQS); + + /* Check for external interrupt */ + + if (irq >= STM32_IRQ_EXTINT && irq < (STM32_IRQ_EXTINT + 32)) + { + /* Set the appropriate bit in the ISER register to enable the + * interrupt + */ + + putreg32((1 << (irq - STM32_IRQ_EXTINT)), ARMV6M_NVIC_ISER); + } + + /* Handle processor exceptions. Only SysTick can be disabled */ + + else if (irq == STM32_IRQ_SYSTICK) + { + modifyreg32(ARMV6M_SYSTICK_CSR, 0, SYSTICK_CSR_ENABLE); + } + + stm32_dumpnvic("enable", irq); +} + +/**************************************************************************** + * Name: arm_ack_irq + * + * Description: + * Acknowledge the IRQ + * + ****************************************************************************/ + +void arm_ack_irq(int irq) +{ + stm32_clrpend(irq); +} diff --git a/arch/arm/src/common/stm32/stm32_irq_m3m4_v1.c b/arch/arm/src/common/stm32/stm32_irq_m3m4_v1.c new file mode 100644 index 0000000000000..c79c0bddd8deb --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_irq_m3m4_v1.c @@ -0,0 +1,542 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_irq_m3m4_v1.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include +#include +#include +#include + +#include "nvic.h" +#ifdef CONFIG_ARCH_RAMVECTORS +# include "ram_vectors.h" +#endif +#include "arm_internal.h" +#include "stm32.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Get a 32-bit version of the default priority */ + +#define DEFPRIORITY32 \ + (NVIC_SYSH_PRIORITY_DEFAULT << 24 | \ + NVIC_SYSH_PRIORITY_DEFAULT << 16 | \ + NVIC_SYSH_PRIORITY_DEFAULT << 8 | \ + NVIC_SYSH_PRIORITY_DEFAULT) + +/* Given the address of a NVIC ENABLE register, this is the offset to + * the corresponding CLEAR ENABLE register. + */ + +#define NVIC_ENA_OFFSET (0) +#define NVIC_CLRENA_OFFSET (NVIC_IRQ0_31_CLEAR - NVIC_IRQ0_31_ENABLE) + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_dumpnvic + * + * Description: + * Dump some interesting NVIC registers + * + ****************************************************************************/ + +#if defined(CONFIG_DEBUG_IRQ_INFO) +static void stm32_dumpnvic(const char *msg, int irq) +{ + irqstate_t flags; + unsigned int i; + unsigned int j; + unsigned int nregs; + unsigned int off; + unsigned int nintr; + unsigned int nreg_per_line = 4; + unsigned int nenable_per_reg = 32; + unsigned int nenable_per_line = nenable_per_reg * nreg_per_line; + unsigned int nprio_per_reg = 4; + unsigned int nprio_per_line = nprio_per_reg * nreg_per_line; + char buf[64]; + + flags = enter_critical_section(); + nintr = STM32_IRQ_NEXTINTS; + + irqinfo("NVIC (%s, irq=%d):\n", msg, irq); + irqinfo(" INTCTRL: %08" PRIx32 " VECTAB: %08" PRIx32 "\n", + getreg32(NVIC_INTCTRL), getreg32(NVIC_VECTAB)); +#if 0 + irqinfo(" SYSH ENABLE MEMFAULT: %08" PRIx32 " BUSFAULT: %08" + PRIx32 " USGFAULT: %08" PRIx32 " SYSTICK: %08" PRIx32 "\n", + getreg32(NVIC_SYSHCON_MEMFAULTENA), + getreg32(NVIC_SYSHCON_BUSFAULTENA), + getreg32(NVIC_SYSHCON_USGFAULTENA), + getreg32(NVIC_SYSTICK_CTRL_ENABLE)); +#endif + for (i = 0; i < nintr; i += nenable_per_line) + { + if (!i) + { + off = snprintf(buf, sizeof(buf), " IRQ ENAB 0:"); + } + else + { + off = snprintf(buf, sizeof(buf), " %3u:", i); + } + + nregs = nintr - i; + if (nregs > nenable_per_line) + { + nregs = nenable_per_line; + } + + for (j = 0; j < nregs; j += nenable_per_reg) + { + off += snprintf(&buf[off], sizeof(buf)-off, " %08" PRIx32, + getreg32(NVIC_IRQ_ENABLE(i + j))); + } + + irqinfo("%s\n", buf); + } + + irqinfo(" SYSH_PRIO: %08" PRIx32 " %08" PRIx32 " %08" PRIx32 "\n", + getreg32(NVIC_SYSH4_7_PRIORITY), + getreg32(NVIC_SYSH8_11_PRIORITY), + getreg32(NVIC_SYSH12_15_PRIORITY)); + + for (i = 0; + i < nintr; + i += nprio_per_line) + { + if (!i) + { + off = snprintf(buf, sizeof(buf), " IRQ PRIO 0:"); + } + else + { + off = snprintf(buf, sizeof(buf), " %3u:", i); + } + + nregs = nintr - i; + if (nregs > nprio_per_line) + { + nregs = nprio_per_line; + } + + for (j = 0; j < nregs; j += nprio_per_reg) + { + off += snprintf(&buf[off], sizeof(buf)-off, " %08" PRIx32, + getreg32(NVIC_IRQ_PRIORITY(i + j))); + } + + irqinfo("%s\n", buf); + } + + leave_critical_section(flags); +} +#else +# define stm32_dumpnvic(msg, irq) +#endif + +/**************************************************************************** + * Name: stm32_nmi, stm32_pendsv, stm32_pendsv, stm32_reserved + * + * Description: + * Handlers for various exceptions. None are handled and all are fatal + * error conditions. The only advantage these provided over the default + * unexpected interrupt handler is that they provide a diagnostic output. + * + ****************************************************************************/ + +#ifdef CONFIG_DEBUG_FEATURES +static int stm32_nmi(int irq, void *context, void *arg) +{ + up_irq_save(); + _err("PANIC!!! NMI received\n"); + PANIC(); + return 0; +} + +static int stm32_pendsv(int irq, void *context, void *arg) +{ +#ifndef CONFIG_ARCH_HIPRI_INTERRUPT + up_irq_save(); + _err("PANIC!!! PendSV received\n"); + PANIC(); +#endif + return 0; +} + +static int stm32_reserved(int irq, void *context, void *arg) +{ + up_irq_save(); + _err("PANIC!!! Reserved interrupt\n"); + PANIC(); + return 0; +} +#endif + +/**************************************************************************** + * Name: stm32_prioritize_syscall + * + * Description: + * Set the priority of an exception. This function may be needed + * internally even if support for prioritized interrupts is not enabled. + * + ****************************************************************************/ + +static inline void stm32_prioritize_syscall(int priority) +{ + uint32_t regval; + + /* SVCALL is system handler 11 */ + + regval = getreg32(NVIC_SYSH8_11_PRIORITY); + regval &= ~NVIC_SYSH_PRIORITY_PR11_MASK; + regval |= (priority << NVIC_SYSH_PRIORITY_PR11_SHIFT); + putreg32(regval, NVIC_SYSH8_11_PRIORITY); +} + +/**************************************************************************** + * Name: stm32_irqinfo + * + * Description: + * Given an IRQ number, provide the register and bit setting to enable or + * disable the irq. + * + ****************************************************************************/ + +static int stm32_irqinfo(int irq, uintptr_t *regaddr, uint32_t *bit, + uintptr_t offset) +{ + int n; + + DEBUGASSERT(irq >= STM32_IRQ_NMI && irq < NR_IRQS); + + /* Check for external interrupt */ + + if (irq >= STM32_IRQ_FIRST) + { + n = irq - STM32_IRQ_FIRST; + *regaddr = NVIC_IRQ_ENABLE(n) + offset; + *bit = (uint32_t)1 << (n & 0x1f); + } + + /* Handle processor exceptions. Only a few can be disabled */ + + else + { + *regaddr = NVIC_SYSHCON; + if (irq == STM32_IRQ_MEMFAULT) + { + *bit = NVIC_SYSHCON_MEMFAULTENA; + } + else if (irq == STM32_IRQ_BUSFAULT) + { + *bit = NVIC_SYSHCON_BUSFAULTENA; + } + else if (irq == STM32_IRQ_USAGEFAULT) + { + *bit = NVIC_SYSHCON_USGFAULTENA; + } + else if (irq == STM32_IRQ_SYSTICK) + { + *regaddr = NVIC_SYSTICK_CTRL; + *bit = NVIC_SYSTICK_CTRL_ENABLE; + } + else + { + return ERROR; /* Invalid or unsupported exception */ + } + } + + return OK; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_irqinitialize + ****************************************************************************/ + +void up_irqinitialize(void) +{ + uint32_t regaddr; + int num_priority_registers; + int i; + + /* Disable all interrupts */ + + for (i = 0; i < NR_IRQS - STM32_IRQ_FIRST; i += 32) + { + putreg32(0xffffffff, NVIC_IRQ_CLEAR(i)); + } + + /* The standard location for the vector table is at the beginning of FLASH + * at address 0x0800:0000. If we are using the STMicro DFU bootloader, + * then the vector table will be offset to a different location in FLASH + * and we will need to set the NVIC vector location to this alternative + * location. + */ + +#if defined(__ICCARM__) + putreg32((uint32_t)__vector_table, NVIC_VECTAB); +#else + putreg32((uint32_t)_vectors, NVIC_VECTAB); +#endif + +#ifdef CONFIG_ARCH_RAMVECTORS + /* If CONFIG_ARCH_RAMVECTORS is defined, then we are using a RAM-based + * vector table that requires special initialization. + */ + + arm_ramvec_initialize(); +#endif + + /* Set all interrupts (and exceptions) to the default priority */ + + putreg32(DEFPRIORITY32, NVIC_SYSH4_7_PRIORITY); + putreg32(DEFPRIORITY32, NVIC_SYSH8_11_PRIORITY); + putreg32(DEFPRIORITY32, NVIC_SYSH12_15_PRIORITY); + + /* The NVIC ICTR register (bits 0-4) holds the number of interrupt + * lines that the NVIC supports: + * + * 0 -> 32 interrupt lines, 8 priority registers + * 1 -> 64 " " " ", 16 priority registers + * 2 -> 96 " " " ", 32 priority registers + * ... + */ + + num_priority_registers = (getreg32(NVIC_ICTR) + 1) * 8; + + /* Now set all of the interrupt lines to the default priority */ + + regaddr = NVIC_IRQ0_3_PRIORITY; + while (num_priority_registers--) + { + putreg32(DEFPRIORITY32, regaddr); + regaddr += 4; + } + + /* Attach the SVCall and Hard Fault exception handlers. The SVCall + * exception is used for performing context switches; The Hard Fault + * must also be caught because a SVCall may show up as a Hard Fault + * under certain conditions. + */ + + irq_attach(STM32_IRQ_SVCALL, arm_svcall, NULL); + irq_attach(STM32_IRQ_HARDFAULT, arm_hardfault, NULL); + + /* Set the priority of the SVCall interrupt */ + +#ifdef CONFIG_ARCH_IRQPRIO + /* up_prioritize_irq(STM32_IRQ_PENDSV, NVIC_SYSH_PRIORITY_MIN); */ +#endif + + stm32_prioritize_syscall(NVIC_SYSH_SVCALL_PRIORITY); + + /* If the MPU is enabled, then attach and enable the Memory Management + * Fault handler. + */ + +#ifdef CONFIG_ARM_MPU + irq_attach(STM32_IRQ_MEMFAULT, arm_memfault, NULL); + up_enable_irq(STM32_IRQ_MEMFAULT); +#endif + +#if defined(CONFIG_RTC) && !defined(CONFIG_RTC_EXTERNAL) + /* RTC was initialized earlier but IRQs weren't ready at that time */ + + stm32_rtc_irqinitialize(); +#endif + + /* Attach all other processor exceptions (except reset and sys tick) */ + +#ifdef CONFIG_DEBUG_FEATURES + irq_attach(STM32_IRQ_NMI, stm32_nmi, NULL); +#ifndef CONFIG_ARM_MPU + irq_attach(STM32_IRQ_MEMFAULT, arm_memfault, NULL); +#endif + irq_attach(STM32_IRQ_BUSFAULT, arm_busfault, NULL); + irq_attach(STM32_IRQ_USAGEFAULT, arm_usagefault, NULL); + irq_attach(STM32_IRQ_PENDSV, stm32_pendsv, NULL); + arm_enable_dbgmonitor(); + irq_attach(STM32_IRQ_DBGMONITOR, arm_dbgmonitor, NULL); + irq_attach(STM32_IRQ_RESERVED, stm32_reserved, NULL); +#endif + + stm32_dumpnvic("initial", NR_IRQS); + +#ifndef CONFIG_SUPPRESS_INTERRUPTS + + /* And finally, enable interrupts */ + + arm_color_intstack(); + up_irq_enable(); +#endif +} + +/**************************************************************************** + * Name: up_disable_irq + * + * Description: + * Disable the IRQ specified by 'irq' + * + ****************************************************************************/ + +void up_disable_irq(int irq) +{ + uintptr_t regaddr; + uint32_t regval; + uint32_t bit; + + if (stm32_irqinfo(irq, ®addr, &bit, NVIC_CLRENA_OFFSET) == 0) + { + /* Modify the appropriate bit in the register to disable the interrupt. + * For normal interrupts, we need to set the bit in the associated + * Interrupt Clear Enable register. For other exceptions, we need to + * clear the bit in the System Handler Control and State Register. + */ + + if (irq >= STM32_IRQ_FIRST) + { + putreg32(bit, regaddr); + } + else + { + regval = getreg32(regaddr); + regval &= ~bit; + putreg32(regval, regaddr); + } + } +} + +/**************************************************************************** + * Name: up_enable_irq + * + * Description: + * Enable the IRQ specified by 'irq' + * + ****************************************************************************/ + +void up_enable_irq(int irq) +{ + uintptr_t regaddr; + uint32_t regval; + uint32_t bit; + + if (stm32_irqinfo(irq, ®addr, &bit, NVIC_ENA_OFFSET) == 0) + { + /* Modify the appropriate bit in the register to enable the interrupt. + * For normal interrupts, we need to set the bit in the associated + * Interrupt Set Enable register. For other exceptions, we need to + * set the bit in the System Handler Control and State Register. + */ + + if (irq >= STM32_IRQ_FIRST) + { + putreg32(bit, regaddr); + } + else + { + regval = getreg32(regaddr); + regval |= bit; + putreg32(regval, regaddr); + } + } +} + +/**************************************************************************** + * Name: arm_ack_irq + * + * Description: + * Acknowledge the IRQ + * + ****************************************************************************/ + +void arm_ack_irq(int irq) +{ +} + +/**************************************************************************** + * Name: up_prioritize_irq + * + * Description: + * Set the priority of an IRQ. + * + * Since this API is not supported on all architectures, it should be + * avoided in common implementations where possible. + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_IRQPRIO +int up_prioritize_irq(int irq, int priority) +{ + uint32_t regaddr; + uint32_t regval; + int shift; + + DEBUGASSERT(irq >= STM32_IRQ_MEMFAULT && irq < NR_IRQS && + (unsigned)priority <= NVIC_SYSH_PRIORITY_MIN); + + if (irq < STM32_IRQ_FIRST) + { + /* NVIC_SYSH_PRIORITY() maps {0..15} to one of three priority + * registers (0-3 are invalid) + */ + + regaddr = NVIC_SYSH_PRIORITY(irq); + irq -= 4; + } + else + { + /* NVIC_IRQ_PRIORITY() maps {0..} to one of many priority registers */ + + irq -= STM32_IRQ_FIRST; + regaddr = NVIC_IRQ_PRIORITY(irq); + } + + regval = getreg32(regaddr); + shift = ((irq & 3) << 3); + regval &= ~(0xff << shift); + regval |= (priority << shift); + putreg32(regval, regaddr); + + stm32_dumpnvic("prioritize", irq); + return OK; +} +#endif diff --git a/arch/arm/src/common/stm32/stm32_iwdg_m0_v1.c b/arch/arm/src/common/stm32/stm32_iwdg_m0_v1.c new file mode 100644 index 0000000000000..172534d89e831 --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_iwdg_m0_v1.c @@ -0,0 +1,709 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_iwdg_m0_v1.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include "arm_internal.h" +#include "stm32_rcc.h" +#include "hardware/stm32_dbgmcu.h" +#include "stm32_wdg.h" + +#if defined(CONFIG_WATCHDOG) && defined(CONFIG_STM32_IWDG) + +/* STM32C0 uses the second CSR register for LSI. */ + +#ifdef CONFIG_ARCH_CHIP_STM32C0 +# define STM32_RCC_CSR STM32_RCC_CSR2 +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Clocking *****************************************************************/ + +/* The minimum frequency of the IWDG clock is: + * + * Fmin = Flsi / 256 + * + * So the maximum delay (in milliseconds) is then: + * + * 1000 * IWDG_RLR_MAX / Fmin + * + * For example, if Flsi = 30Khz (the nominal, uncalibrated value), then the + * maximum delay is: + * + * Fmin = 117.1875 + * 1000 * 4095 / Fmin = 34,944 MSec + */ + +#define IWDG_FMIN (STM32_LSI_FREQUENCY / 256) +#define IWDG_MAXTIMEOUT (1000 * IWDG_RLR_MAX / IWDG_FMIN) + +/* Configuration ************************************************************/ + +#ifndef CONFIG_STM32_IWDG_DEFTIMOUT +# define CONFIG_STM32_IWDG_DEFTIMOUT IWDG_MAXTIMEOUT +#endif + +#ifndef CONFIG_DEBUG_WATCHDOG_INFO +# undef CONFIG_STM32_IWDG_REGDEBUG +#endif + +/* REVISIT: It appears that you can only setup the prescaler and reload + * registers once. After that, the SR register's PVU and RVU bits never go + * to zero. So we defer setting up these registers until the watchdog + * is started, then refuse any further attempts to change timeout. + */ + +#define CONFIG_STM32_IWDG_ONETIMESETUP 1 + +/* REVISIT: Another possibility is that we CAN change the prescaler and + * reload values after starting the timer. This option is untested but the + * implementation place conditioned on the following: + */ + +#undef CONFIG_STM32_IWDG_DEFERREDSETUP + +/* But you can only try one at a time */ + +#if defined(CONFIG_STM32_IWDG_ONETIMESETUP) && defined(CONFIG_STM32_IWDG_DEFERREDSETUP) +# error "Both CONFIG_STM32_IWDG_ONETIMESETUP and CONFIG_STM32_IWDG_DEFERREDSETUP are defined" +#endif + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/* This structure provides the private representation of the "lower-half" + * driver state structure. This structure must be cast-compatible with the + * well-known watchdog_lowerhalf_s structure. + */ + +struct stm32_lowerhalf_s +{ + const struct watchdog_ops_s *ops; /* Lower half operations */ + uint32_t lsifreq; /* The calibrated frequency of the LSI oscillator */ + uint32_t timeout; /* The (actual) selected timeout */ + uint32_t lastreset; /* The last reset time */ + bool started; /* true: The watchdog timer has been started */ + uint8_t prescaler; /* Clock prescaler value */ + uint16_t reload; /* Timer reload value */ +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/* Register operations ******************************************************/ + +#ifdef CONFIG_STM32_IWDG_REGDEBUG +static uint16_t stm32_getreg(uint32_t addr); +static void stm32_putreg(uint16_t val, uint32_t addr); +#else +# define stm32_getreg(addr) getreg16(addr) +# define stm32_putreg(val,addr) putreg16(val,addr) +#endif + +static inline void stm32_setprescaler(struct stm32_lowerhalf_s *priv); + +/* "Lower half" driver methods **********************************************/ + +static int stm32_start(struct watchdog_lowerhalf_s *lower); +static int stm32_stop(struct watchdog_lowerhalf_s *lower); +static int stm32_keepalive(struct watchdog_lowerhalf_s *lower); +static int stm32_getstatus(struct watchdog_lowerhalf_s *lower, + struct watchdog_status_s *status); +static int stm32_settimeout(struct watchdog_lowerhalf_s *lower, + uint32_t timeout); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* "Lower half" driver methods */ + +static const struct watchdog_ops_s g_wdgops = +{ + .start = stm32_start, + .stop = stm32_stop, + .keepalive = stm32_keepalive, + .getstatus = stm32_getstatus, + .settimeout = stm32_settimeout, + .capture = NULL, + .ioctl = NULL, +}; + +/* "Lower half" driver state */ + +static struct stm32_lowerhalf_s g_wdgdev; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_getreg + * + * Description: + * Get the contents of an STM32 IWDG register + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_IWDG_REGDEBUG +static uint16_t stm32_getreg(uint32_t addr) +{ + static uint32_t prevaddr = 0; + static uint32_t count = 0; + static uint16_t preval = 0; + + /* Read the value from the register */ + + uint16_t val = getreg16(addr); + + /* Is this the same value that we read from the same register last time? + * Are we polling the register? If so, suppress some of the output. + */ + + if (addr == prevaddr && val == preval) + { + if (count == 0xffffffff || ++count > 3) + { + if (count == 4) + { + wdinfo("...\n"); + } + + return val; + } + } + + /* No this is a new address or value */ + + else + { + /* Did we print "..." for the previous value? */ + + if (count > 3) + { + /* Yes.. then show how many times the value repeated */ + + wdinfo("[repeats %d more times]\n", count - 3); + } + + /* Save the new address, value, and count */ + + prevaddr = addr; + preval = val; + count = 1; + } + + /* Show the register value read */ + + wdinfo("%08" PRIx32 "->%04x\n", addr, val); + return val; +} +#endif + +/**************************************************************************** + * Name: stm32_putreg + * + * Description: + * Set the contents of an STM32 register to a value + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_IWDG_REGDEBUG +static void stm32_putreg(uint16_t val, uint32_t addr) +{ + /* Show the register value being written */ + + wdinfo("%08" PRIx32 "<-%04x\n", addr, val); + + /* Write the value */ + + putreg16(val, addr); +} +#endif + +/**************************************************************************** + * Name: stm32_setprescaler + * + * Description: + * Set up the prescaler and reload values. This seems to be something + * that can only be done one time. + * + * Input Parameters: + * priv - A pointer the internal representation of the "lower-half" + * driver state structure. + * + ****************************************************************************/ + +static inline void stm32_setprescaler(struct stm32_lowerhalf_s *priv) +{ + /* Enable write access to IWDG_PR and IWDG_RLR registers */ + + stm32_putreg(IWDG_KR_KEY_ENABLE, STM32_IWDG_KR); + + /* Wait for the PVU and RVU bits to be reset be hardware. These bits + * were set the last time that the PR register was written and may not + * yet be cleared. + * + * If the setup is only permitted one time, then this wait should not + * be necessary. + */ + +#ifndef CONFIG_STM32_IWDG_ONETIMESETUP + while ((stm32_getreg(STM32_IWDG_SR) & (IWDG_SR_PVU | IWDG_SR_RVU)) != 0); +#endif + + /* Set the prescaler */ + + stm32_putreg((uint16_t)priv->prescaler << IWDG_PR_SHIFT, STM32_IWDG_PR); + + /* Set the reload value */ + + stm32_putreg((uint16_t)priv->reload, STM32_IWDG_RLR); + + /* Reload the counter (and disable write access) */ + + stm32_putreg(IWDG_KR_KEY_RELOAD, STM32_IWDG_KR); +} + +/**************************************************************************** + * Name: stm32_start + * + * Description: + * Start the watchdog timer, resetting the time to the current timeout, + * + * Input Parameters: + * lower - A pointer the publicly visible representation of the + * "lower-half" driver state structure. + * + * Returned Value: + * Zero on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int stm32_start(struct watchdog_lowerhalf_s *lower) +{ + struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; + irqstate_t flags; + + wdinfo("Entry: started\n"); + DEBUGASSERT(priv); + + /* Have we already been started? */ + + if (!priv->started) + { + /* REVISIT: It appears that you can only setup the prescaler and reload + * registers once. After that, the SR register's PVU and RVU bits never + * go to 0. So we defer setting up these registers until the watchdog + * is started, then refuse any further attempts to change timeout. + */ + + /* Set up prescaler and reload value for the selected timeout before + * starting the watchdog timer. + */ + +#if defined(CONFIG_STM32_IWDG_ONETIMESETUP) || defined(CONFIG_STM32_IWDG_DEFERREDSETUP) + stm32_setprescaler(priv); +#endif + + /* Enable IWDG (the LSI oscillator will be enabled by hardware). NOTE: + * If the "Hardware watchdog" feature is enabled through the device + * option bits, the watchdog is automatically enabled at power-on. + */ + + flags = enter_critical_section(); + stm32_putreg(IWDG_KR_KEY_START, STM32_IWDG_KR); + priv->lastreset = clock_systime_ticks(); + priv->started = true; + leave_critical_section(flags); + } + + return OK; +} + +/**************************************************************************** + * Name: stm32_stop + * + * Description: + * Stop the watchdog timer + * + * Input Parameters: + * lower - A pointer the publicly visible representation of the + * "lower-half" driver state structure. + * + * Returned Value: + * Zero on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int stm32_stop(struct watchdog_lowerhalf_s *lower) +{ + /* There is no way to disable the IDWG timer once it has been started */ + + wdinfo("Entry\n"); + return -ENOSYS; +} + +/**************************************************************************** + * Name: stm32_keepalive + * + * Description: + * Reset the watchdog timer to the current timeout value, prevent any + * imminent watchdog timeouts. This is sometimes referred as "pinging" + * the watchdog timer or "petting the dog". + * + * Input Parameters: + * lower - A pointer the publicly visible representation of the + * "lower-half" driver state structure. + * + * Returned Value: + * Zero on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int stm32_keepalive(struct watchdog_lowerhalf_s *lower) +{ + struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; + irqstate_t flags; + + wdinfo("Entry\n"); + + /* Reload the IWDG timer */ + + flags = enter_critical_section(); + stm32_putreg(IWDG_KR_KEY_RELOAD, STM32_IWDG_KR); + priv->lastreset = clock_systime_ticks(); + leave_critical_section(flags); + + return OK; +} + +/**************************************************************************** + * Name: stm32_getstatus + * + * Description: + * Get the current watchdog timer status + * + * Input Parameters: + * lower - A pointer the publicly visible representation of the + * "lower-half" driver state structure. + * status - The location to return the watchdog status information. + * + * Returned Value: + * Zero on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int stm32_getstatus(struct watchdog_lowerhalf_s *lower, + struct watchdog_status_s *status) +{ + struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; + uint32_t ticks; + uint32_t elapsed; + + wdinfo("Entry\n"); + DEBUGASSERT(priv); + + /* Return the status bit */ + + status->flags = WDFLAGS_RESET; + if (priv->started) + { + status->flags |= WDFLAGS_ACTIVE; + } + + /* Return the actual timeout in milliseconds */ + + status->timeout = priv->timeout; + + /* Get the elapsed time since the last ping */ + + ticks = clock_systime_ticks() - priv->lastreset; + elapsed = (int32_t)TICK2MSEC(ticks); + + if (elapsed > priv->timeout) + { + elapsed = priv->timeout; + } + + /* Return the approximate time until the watchdog timer expiration */ + + status->timeleft = priv->timeout - elapsed; + + wdinfo("Status :\n"); + wdinfo(" flags : %08" PRIx32 "\n", status->flags); + wdinfo(" timeout : %" PRId32 "\n", status->timeout); + wdinfo(" timeleft : %" PRId32 "\n", status->timeleft); + return OK; +} + +/**************************************************************************** + * Name: stm32_settimeout + * + * Description: + * Set a new timeout value (and reset the watchdog timer) + * + * Input Parameters: + * lower - A pointer the publicly visible representation of the + * "lower-half" driver state structure. + * timeout - The new timeout value in milliseconds. + * + * Returned Value: + * Zero on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int stm32_settimeout(struct watchdog_lowerhalf_s *lower, + uint32_t timeout) +{ + struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; + uint32_t fiwdg; + uint64_t reload; + int prescaler; + int shift; + + wdinfo("Entry: timeout=%" PRId32 "\n", timeout); + DEBUGASSERT(priv); + + /* Can this timeout be represented? */ + + if (timeout < 1 || timeout > IWDG_MAXTIMEOUT) + { + wderr("ERROR: Cannot represent timeout=%" PRId32 " > %d\n", + timeout, IWDG_MAXTIMEOUT); + return -ERANGE; + } + + /* REVISIT: It appears that you can only setup the prescaler and reload + * registers once. After that, the SR register's PVU and RVU bits never go + * to zero. + */ + +#ifdef CONFIG_STM32_IWDG_ONETIMESETUP + if (priv->started) + { + wdwarn("WARNING: Timer is already started\n"); + return -EBUSY; + } +#endif + + /* Select the smallest prescaler that will result in a reload value that is + * less than the maximum. + */ + + for (prescaler = 0; ; prescaler++) + { + /* PR = 0 -> Divider = 4 = 1 << 2 + * PR = 1 -> Divider = 8 = 1 << 3 + * PR = 2 -> Divider = 16 = 1 << 4 + * PR = 3 -> Divider = 32 = 1 << 5 + * PR = 4 -> Divider = 64 = 1 << 6 + * PR = 5 -> Divider = 128 = 1 << 7 + * PR = 6 -> Divider = 256 = 1 << 8 + * PR = n -> Divider = 1 << (n+2) + */ + + shift = prescaler + 2; + + /* Get the IWDG counter frequency in Hz. For a nominal 32Khz LSI clock, + * this is value in the range of 7500 and 125. + */ + + fiwdg = priv->lsifreq >> shift; + + /* We want: + * 1000 * reload / Fiwdg = timeout + * Or: + * reload = Fiwdg * timeout / 1000 + */ + + reload = (uint64_t)fiwdg * (uint64_t)timeout / 1000; + + /* If this reload valid is less than the maximum or we are not ready + * at the prescaler value, then break out of the loop to use these + * settings. + */ + + if (reload <= IWDG_RLR_MAX || prescaler == 6) + { + /* Note that we explicitly break out of the loop rather than using + * the 'for' loop termination logic because we do not want the + * value of prescaler to be incremented. + */ + + break; + } + } + + /* Make sure that the final reload value is within range */ + + if (reload > IWDG_RLR_MAX) + { + reload = IWDG_RLR_MAX; + } + + /* Get the actual timeout value in milliseconds. + * + * We have: + * reload = Fiwdg * timeout / 1000 + * So we want: + * timeout = 1000 * reload / Fiwdg + */ + + priv->timeout = (1000 * (uint32_t)reload) / fiwdg; + + /* Save setup values for later use */ + + priv->prescaler = prescaler; + priv->reload = reload; + + /* Write the prescaler and reload values to the IWDG registers. + * + * REVISIT: It appears that you can only setup the prescaler and reload + * registers once. After that, the SR register's PVU and RVU bits never go + * to zero. + */ + +#ifndef CONFIG_STM32_IWDG_ONETIMESETUP + /* If CONFIG_STM32_IWDG_DEFERREDSETUP is selected, then perform the + * register configuration only if the timer has been started. + */ + +#ifdef CONFIG_STM32_IWDG_DEFERREDSETUP + if (priv->started) +#endif + { + stm32_setprescaler(priv); + } +#endif + + wdinfo("prescaler=%d fiwdg=%" PRId32 " reload=%" PRId64 "\n", + prescaler, fiwdg, reload); + + return OK; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_iwdginitialize + * + * Description: + * Initialize the IWDG watchdog timer. The watchdog timer is initialized + * and registers as 'devpath'. The initial state of the watchdog timer is + * disabled. + * + * Input Parameters: + * devpath - The full path to the watchdog. This should be of the form + * /dev/watchdog0 + * lsifreq - The calibrated LSI clock frequency + * + * Returned Value: + * None + * + ****************************************************************************/ + +void stm32_iwdginitialize(const char *devpath, uint32_t lsifreq) +{ + struct stm32_lowerhalf_s *priv = &g_wdgdev; + + wdinfo("Entry: devpath=%s lsifreq=%" PRId32 "\n", devpath, lsifreq); + + /* NOTE we assume that clocking to the IWDG has already been provided by + * the RCC initialization logic. + */ + + /* Initialize the driver state structure. */ + + priv->ops = &g_wdgops; + priv->lsifreq = lsifreq; + priv->started = false; + + /* Make sure that the LSI oscillator is enabled. NOTE: The LSI oscillator + * is enabled here but is not disabled by this file, because this file does + * not know the global usage of the oscillator. Any clock management + * logic (say, as part of a power management scheme) needs handle other + * LSI controls outside of this file. + */ + + stm32_rcc_enablelsi(); + wdinfo("RCC CSR: %08" PRIx32 "\n", getreg32(STM32_RCC_CSR)); + + /* Select an arbitrary initial timeout value. But don't start the watchdog + * yet. NOTE: If the "Hardware watchdog" feature is enabled through the + * device option bits, the watchdog is automatically enabled at power-on. + */ + + stm32_settimeout((struct watchdog_lowerhalf_s *)priv, + CONFIG_STM32_IWDG_DEFTIMOUT); + + /* Register the watchdog driver as /dev/watchdog0 */ + + watchdog_register(devpath, (struct watchdog_lowerhalf_s *)priv); + + /* When the microcontroller enters debug mode (Cortex-M4F core halted), + * the IWDG counter either continues to work normally or stops, depending + * on DBG_IWDG_STOP configuration bit in DBG module. + */ + +#if defined(CONFIG_STM32_JTAG_FULL_ENABLE) || \ + defined(CONFIG_STM32_JTAG_NOJNTRST_ENABLE) || \ + defined(CONFIG_STM32_JTAG_SW_ENABLE) + { +#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F30XX) || \ + defined(CONFIG_STM32_STM32F4XXX) || defined(CONFIG_STM32_STM32L15XX) + uint32_t cr = getreg32(STM32_DBGMCU_APB1_FZ); + cr |= DBGMCU_APB1_IWDGSTOP; + putreg32(cr, STM32_DBGMCU_APB1_FZ); +#else /* if defined(CONFIG_STM32_STM32F10XX) */ + uint32_t cr = getreg32(STM32_DBGMCU_CR); + cr |= DBGMCU_CR_IWDGSTOP; + putreg32(cr, STM32_DBGMCU_CR); +#endif + } +#endif +} + +#endif /* CONFIG_WATCHDOG && CONFIG_STM32_IWDG */ diff --git a/arch/arm/src/common/stm32/stm32_iwdg_m3m4_v1.c b/arch/arm/src/common/stm32/stm32_iwdg_m3m4_v1.c new file mode 100644 index 0000000000000..026b0edf05370 --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_iwdg_m3m4_v1.c @@ -0,0 +1,703 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_iwdg_m3m4_v1.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include "arm_internal.h" +#include "stm32_rcc.h" +#include "hardware/stm32_dbgmcu.h" +#include "stm32_wdg.h" + +#if defined(CONFIG_WATCHDOG) && defined(CONFIG_STM32_IWDG) + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Clocking *****************************************************************/ + +/* The minimum frequency of the IWDG clock is: + * + * Fmin = Flsi / 256 + * + * So the maximum delay (in milliseconds) is then: + * + * 1000 * IWDG_RLR_MAX / Fmin + * + * For example, if Flsi = 30Khz (the nominal, uncalibrated value), then the + * maximum delay is: + * + * Fmin = 117.1875 + * 1000 * 4095 / Fmin = 34,944 MSec + */ + +#define IWDG_FMIN (STM32_LSI_FREQUENCY / 256) +#define IWDG_MAXTIMEOUT (1000 * IWDG_RLR_MAX / IWDG_FMIN) + +/* Configuration ************************************************************/ + +#ifndef CONFIG_STM32_IWDG_DEFTIMOUT +# define CONFIG_STM32_IWDG_DEFTIMOUT IWDG_MAXTIMEOUT +#endif + +#ifndef CONFIG_DEBUG_WATCHDOG_INFO +# undef CONFIG_STM32_IWDG_REGDEBUG +#endif + +/* REVISIT: It appears that you can only setup the prescaler and reload + * registers once. After that, the SR register's PVU and RVU bits never go + * to zero. So we defer setting up these registers until the watchdog + * is started, then refuse any further attempts to change timeout. + */ + +#define CONFIG_STM32_IWDG_ONETIMESETUP 1 + +/* REVISIT: Another possibility is that we CAN change the prescaler and + * reload values after starting the timer. This option is untested but the + * implementation place conditioned on the following: + */ + +#undef CONFIG_STM32_IWDG_DEFERREDSETUP + +/* But you can only try one at a time */ + +#if defined(CONFIG_STM32_IWDG_ONETIMESETUP) && defined(CONFIG_STM32_IWDG_DEFERREDSETUP) +# error "Both CONFIG_STM32_IWDG_ONETIMESETUP and CONFIG_STM32_IWDG_DEFERREDSETUP are defined" +#endif + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/* This structure provides the private representation of the "lower-half" + * driver state structure. This structure must be cast-compatible with the + * well-known watchdog_lowerhalf_s structure. + */ + +struct stm32_lowerhalf_s +{ + const struct watchdog_ops_s *ops; /* Lower half operations */ + uint32_t lsifreq; /* The calibrated frequency of the LSI oscillator */ + uint32_t timeout; /* The (actual) selected timeout */ + uint32_t lastreset; /* The last reset time */ + bool started; /* true: The watchdog timer has been started */ + uint8_t prescaler; /* Clock prescaler value */ + uint16_t reload; /* Timer reload value */ +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/* Register operations ******************************************************/ + +#ifdef CONFIG_STM32_IWDG_REGDEBUG +static uint16_t stm32_getreg(uint32_t addr); +static void stm32_putreg(uint16_t val, uint32_t addr); +#else +# define stm32_getreg(addr) getreg16(addr) +# define stm32_putreg(val,addr) putreg16(val,addr) +#endif + +static inline void stm32_setprescaler(struct stm32_lowerhalf_s *priv); + +/* "Lower half" driver methods **********************************************/ + +static int stm32_start(struct watchdog_lowerhalf_s *lower); +static int stm32_stop(struct watchdog_lowerhalf_s *lower); +static int stm32_keepalive(struct watchdog_lowerhalf_s *lower); +static int stm32_getstatus(struct watchdog_lowerhalf_s *lower, + struct watchdog_status_s *status); +static int stm32_settimeout(struct watchdog_lowerhalf_s *lower, + uint32_t timeout); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* "Lower half" driver methods */ + +static const struct watchdog_ops_s g_wdgops = +{ + .start = stm32_start, + .stop = stm32_stop, + .keepalive = stm32_keepalive, + .getstatus = stm32_getstatus, + .settimeout = stm32_settimeout, + .capture = NULL, + .ioctl = NULL, +}; + +/* "Lower half" driver state */ + +static struct stm32_lowerhalf_s g_wdgdev; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_getreg + * + * Description: + * Get the contents of an STM32 IWDG register + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_IWDG_REGDEBUG +static uint16_t stm32_getreg(uint32_t addr) +{ + static uint32_t prevaddr = 0; + static uint32_t count = 0; + static uint16_t preval = 0; + + /* Read the value from the register */ + + uint16_t val = getreg16(addr); + + /* Is this the same value that we read from the same register last time? + * Are we polling the register? If so, suppress some of the output. + */ + + if (addr == prevaddr && val == preval) + { + if (count == 0xffffffff || ++count > 3) + { + if (count == 4) + { + wdinfo("...\n"); + } + + return val; + } + } + + /* No this is a new address or value */ + + else + { + /* Did we print "..." for the previous value? */ + + if (count > 3) + { + /* Yes.. then show how many times the value repeated */ + + wdinfo("[repeats %d more times]\n", count - 3); + } + + /* Save the new address, value, and count */ + + prevaddr = addr; + preval = val; + count = 1; + } + + /* Show the register value read */ + + wdinfo("%08" PRIx32 "->%04x\n", addr, val); + return val; +} +#endif + +/**************************************************************************** + * Name: stm32_putreg + * + * Description: + * Set the contents of an STM32 register to a value + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_IWDG_REGDEBUG +static void stm32_putreg(uint16_t val, uint32_t addr) +{ + /* Show the register value being written */ + + wdinfo("%08" PRIx32 "<-%04x\n", addr, val); + + /* Write the value */ + + putreg16(val, addr); +} +#endif + +/**************************************************************************** + * Name: stm32_setprescaler + * + * Description: + * Set up the prescaler and reload values. This seems to be something + * that can only be done one time. + * + * Input Parameters: + * priv - A pointer the internal representation of the "lower-half" + * driver state structure. + * + ****************************************************************************/ + +static inline void stm32_setprescaler(struct stm32_lowerhalf_s *priv) +{ + /* Enable write access to IWDG_PR and IWDG_RLR registers */ + + stm32_putreg(IWDG_KR_KEY_ENABLE, STM32_IWDG_KR); + + /* Wait for the PVU and RVU bits to be reset be hardware. These bits + * were set the last time that the PR register was written and may not + * yet be cleared. + * + * If the setup is only permitted one time, then this wait should not + * be necessary. + */ + +#ifndef CONFIG_STM32_IWDG_ONETIMESETUP + while ((stm32_getreg(STM32_IWDG_SR) & (IWDG_SR_PVU | IWDG_SR_RVU)) != 0); +#endif + + /* Set the prescaler */ + + stm32_putreg((uint16_t)priv->prescaler << IWDG_PR_SHIFT, STM32_IWDG_PR); + + /* Set the reload value */ + + stm32_putreg((uint16_t)priv->reload, STM32_IWDG_RLR); + + /* Reload the counter (and disable write access) */ + + stm32_putreg(IWDG_KR_KEY_RELOAD, STM32_IWDG_KR); +} + +/**************************************************************************** + * Name: stm32_start + * + * Description: + * Start the watchdog timer, resetting the time to the current timeout, + * + * Input Parameters: + * lower - A pointer the publicly visible representation of the + * "lower-half" driver state structure. + * + * Returned Value: + * Zero on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int stm32_start(struct watchdog_lowerhalf_s *lower) +{ + struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; + irqstate_t flags; + + wdinfo("Entry: started\n"); + DEBUGASSERT(priv); + + /* Have we already been started? */ + + if (!priv->started) + { + /* REVISIT: It appears that you can only setup the prescaler and reload + * registers once. After that, the SR register's PVU and RVU bits never + * go to 0. So we defer setting up these registers until the watchdog + * is started, then refuse any further attempts to change timeout. + */ + + /* Set up prescaler and reload value for the selected timeout before + * starting the watchdog timer. + */ + +#if defined(CONFIG_STM32_IWDG_ONETIMESETUP) || defined(CONFIG_STM32_IWDG_DEFERREDSETUP) + stm32_setprescaler(priv); +#endif + + /* Enable IWDG (the LSI oscillator will be enabled by hardware). NOTE: + * If the "Hardware watchdog" feature is enabled through the device + * option bits, the watchdog is automatically enabled at power-on. + */ + + flags = enter_critical_section(); + stm32_putreg(IWDG_KR_KEY_START, STM32_IWDG_KR); + priv->lastreset = clock_systime_ticks(); + priv->started = true; + leave_critical_section(flags); + } + + return OK; +} + +/**************************************************************************** + * Name: stm32_stop + * + * Description: + * Stop the watchdog timer + * + * Input Parameters: + * lower - A pointer the publicly visible representation of the + * "lower-half" driver state structure. + * + * Returned Value: + * Zero on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int stm32_stop(struct watchdog_lowerhalf_s *lower) +{ + /* There is no way to disable the IDWG timer once it has been started */ + + wdinfo("Entry\n"); + return -ENOSYS; +} + +/**************************************************************************** + * Name: stm32_keepalive + * + * Description: + * Reset the watchdog timer to the current timeout value, prevent any + * imminent watchdog timeouts. This is sometimes referred as "pinging" + * the watchdog timer or "petting the dog". + * + * Input Parameters: + * lower - A pointer the publicly visible representation of the + * "lower-half" driver state structure. + * + * Returned Value: + * Zero on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int stm32_keepalive(struct watchdog_lowerhalf_s *lower) +{ + struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; + irqstate_t flags; + + wdinfo("Entry\n"); + + /* Reload the IWDG timer */ + + flags = enter_critical_section(); + stm32_putreg(IWDG_KR_KEY_RELOAD, STM32_IWDG_KR); + priv->lastreset = clock_systime_ticks(); + leave_critical_section(flags); + + return OK; +} + +/**************************************************************************** + * Name: stm32_getstatus + * + * Description: + * Get the current watchdog timer status + * + * Input Parameters: + * lower - A pointer the publicly visible representation of the + * "lower-half" driver state structure. + * status - The location to return the watchdog status information. + * + * Returned Value: + * Zero on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int stm32_getstatus(struct watchdog_lowerhalf_s *lower, + struct watchdog_status_s *status) +{ + struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; + uint32_t ticks; + uint32_t elapsed; + + wdinfo("Entry\n"); + DEBUGASSERT(priv); + + /* Return the status bit */ + + status->flags = WDFLAGS_RESET; + if (priv->started) + { + status->flags |= WDFLAGS_ACTIVE; + } + + /* Return the actual timeout in milliseconds */ + + status->timeout = priv->timeout; + + /* Get the elapsed time since the last ping */ + + ticks = clock_systime_ticks() - priv->lastreset; + elapsed = (int32_t)TICK2MSEC(ticks); + + if (elapsed > priv->timeout) + { + elapsed = priv->timeout; + } + + /* Return the approximate time until the watchdog timer expiration */ + + status->timeleft = priv->timeout - elapsed; + + wdinfo("Status :\n"); + wdinfo(" flags : %08" PRIx32 "\n", status->flags); + wdinfo(" timeout : %" PRId32 "\n", status->timeout); + wdinfo(" timeleft : %" PRId32 "\n", status->timeleft); + return OK; +} + +/**************************************************************************** + * Name: stm32_settimeout + * + * Description: + * Set a new timeout value (and reset the watchdog timer) + * + * Input Parameters: + * lower - A pointer the publicly visible representation of the + * "lower-half" driver state structure. + * timeout - The new timeout value in milliseconds. + * + * Returned Value: + * Zero on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int stm32_settimeout(struct watchdog_lowerhalf_s *lower, + uint32_t timeout) +{ + struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; + uint32_t fiwdg; + uint64_t reload; + int prescaler; + int shift; + + wdinfo("Entry: timeout=%" PRId32 "\n", timeout); + DEBUGASSERT(priv); + + /* Can this timeout be represented? */ + + if (timeout < 1 || timeout > IWDG_MAXTIMEOUT) + { + wderr("ERROR: Cannot represent timeout=%" PRId32 " > %d\n", + timeout, IWDG_MAXTIMEOUT); + return -ERANGE; + } + + /* REVISIT: It appears that you can only setup the prescaler and reload + * registers once. After that, the SR register's PVU and RVU bits never go + * to zero. + */ + +#ifdef CONFIG_STM32_IWDG_ONETIMESETUP + if (priv->started) + { + wdwarn("WARNING: Timer is already started\n"); + return -EBUSY; + } +#endif + + /* Select the smallest prescaler that will result in a reload value that is + * less than the maximum. + */ + + for (prescaler = 0; ; prescaler++) + { + /* PR = 0 -> Divider = 4 = 1 << 2 + * PR = 1 -> Divider = 8 = 1 << 3 + * PR = 2 -> Divider = 16 = 1 << 4 + * PR = 3 -> Divider = 32 = 1 << 5 + * PR = 4 -> Divider = 64 = 1 << 6 + * PR = 5 -> Divider = 128 = 1 << 7 + * PR = 6 -> Divider = 256 = 1 << 8 + * PR = n -> Divider = 1 << (n+2) + */ + + shift = prescaler + 2; + + /* Get the IWDG counter frequency in Hz. For a nominal 32Khz LSI clock, + * this is value in the range of 7500 and 125. + */ + + fiwdg = priv->lsifreq >> shift; + + /* We want: + * 1000 * reload / Fiwdg = timeout + * Or: + * reload = Fiwdg * timeout / 1000 + */ + + reload = (uint64_t)fiwdg * (uint64_t)timeout / 1000; + + /* If this reload valid is less than the maximum or we are not ready + * at the prescaler value, then break out of the loop to use these + * settings. + */ + + if (reload <= IWDG_RLR_MAX || prescaler == 6) + { + /* Note that we explicitly break out of the loop rather than using + * the 'for' loop termination logic because we do not want the + * value of prescaler to be incremented. + */ + + break; + } + } + + /* Make sure that the final reload value is within range */ + + if (reload > IWDG_RLR_MAX) + { + reload = IWDG_RLR_MAX; + } + + /* Get the actual timeout value in milliseconds. + * + * We have: + * reload = Fiwdg * timeout / 1000 + * So we want: + * timeout = 1000 * reload / Fiwdg + */ + + priv->timeout = (1000 * (uint32_t)reload) / fiwdg; + + /* Save setup values for later use */ + + priv->prescaler = prescaler; + priv->reload = reload; + + /* Write the prescaler and reload values to the IWDG registers. + * + * REVISIT: It appears that you can only setup the prescaler and reload + * registers once. After that, the SR register's PVU and RVU bits never go + * to zero. + */ + +#ifndef CONFIG_STM32_IWDG_ONETIMESETUP + /* If CONFIG_STM32_IWDG_DEFERREDSETUP is selected, then perform the + * register configuration only if the timer has been started. + */ + +#ifdef CONFIG_STM32_IWDG_DEFERREDSETUP + if (priv->started) +#endif + { + stm32_setprescaler(priv); + } +#endif + + wdinfo("prescaler=%d fiwdg=%" PRId32 " reload=%" PRId64 "\n", + prescaler, fiwdg, reload); + + return OK; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_iwdginitialize + * + * Description: + * Initialize the IWDG watchdog timer. The watchdog timer is initialized + * and registers as 'devpath'. The initial state of the watchdog timer is + * disabled. + * + * Input Parameters: + * devpath - The full path to the watchdog. This should be of the form + * /dev/watchdog0 + * lsifreq - The calibrated LSI clock frequency + * + * Returned Value: + * None + * + ****************************************************************************/ + +void stm32_iwdginitialize(const char *devpath, uint32_t lsifreq) +{ + struct stm32_lowerhalf_s *priv = &g_wdgdev; + + wdinfo("Entry: devpath=%s lsifreq=%" PRId32 "\n", devpath, lsifreq); + + /* NOTE we assume that clocking to the IWDG has already been provided by + * the RCC initialization logic. + */ + + /* Initialize the driver state structure. */ + + priv->ops = &g_wdgops; + priv->lsifreq = lsifreq; + priv->started = false; + + /* Make sure that the LSI oscillator is enabled. NOTE: The LSI oscillator + * is enabled here but is not disabled by this file, because this file does + * not know the global usage of the oscillator. Any clock management + * logic (say, as part of a power management scheme) needs handle other + * LSI controls outside of this file. + */ + + stm32_rcc_enablelsi(); + wdinfo("RCC CSR: %08" PRIx32 "\n", getreg32(STM32_RCC_CSR)); + + /* Select an arbitrary initial timeout value. But don't start the watchdog + * yet. NOTE: If the "Hardware watchdog" feature is enabled through the + * device option bits, the watchdog is automatically enabled at power-on. + */ + + stm32_settimeout((struct watchdog_lowerhalf_s *)priv, + CONFIG_STM32_IWDG_DEFTIMOUT); + + /* Register the watchdog driver as /dev/watchdog0 */ + + watchdog_register(devpath, (struct watchdog_lowerhalf_s *)priv); + + /* When the microcontroller enters debug mode (Cortex-M4F core halted), + * the IWDG counter either continues to work normally or stops, depending + * on DBG_IWDG_STOP configuration bit in DBG module. + */ + +#if defined(CONFIG_STM32_JTAG_FULL_ENABLE) || \ + defined(CONFIG_STM32_JTAG_NOJNTRST_ENABLE) || \ + defined(CONFIG_STM32_JTAG_SW_ENABLE) + { +#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F30XX) || \ + defined(CONFIG_STM32_STM32F4XXX) || defined(CONFIG_STM32_STM32L15XX) + uint32_t cr = getreg32(STM32_DBGMCU_APB1_FZ); + cr |= DBGMCU_APB1_IWDGSTOP; + putreg32(cr, STM32_DBGMCU_APB1_FZ); +#else /* if defined(CONFIG_STM32_STM32F10XX) */ + uint32_t cr = getreg32(STM32_DBGMCU_CR); + cr |= DBGMCU_CR_IWDGSTOP; + putreg32(cr, STM32_DBGMCU_CR); +#endif + } +#endif +} + +#endif /* CONFIG_WATCHDOG && CONFIG_STM32_IWDG */ diff --git a/arch/arm/src/common/stm32/stm32_lowputc.h b/arch/arm/src/common/stm32/stm32_lowputc.h new file mode 100644 index 0000000000000..0c2ddb9156d36 --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_lowputc.h @@ -0,0 +1,66 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_lowputc.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_LOWPUTC_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_LOWPUTC_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "chip.h" + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Name: stm32_lowsetup + * + * Description: + * Called at the very beginning of _start. Performs low level + * initialization of serial console. + * + ****************************************************************************/ + +void stm32_lowsetup(void); + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_LOWPUTC_H */ diff --git a/arch/arm/src/common/stm32/stm32_lowputc_usart_m0_v3.c b/arch/arm/src/common/stm32/stm32_lowputc_usart_m0_v3.c new file mode 100644 index 0000000000000..03acef0e8d0f7 --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_lowputc_usart_m0_v3.c @@ -0,0 +1,394 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_lowputc_usart_m0_v3.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include + +#include "arm_internal.h" +#include "chip.h" + +#include "stm32_rcc.h" +#include "stm32_gpio.h" +#include "stm32_uart.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Select USART parameters for the selected console */ + +#ifdef HAVE_CONSOLE +# if defined(CONFIG_USART1_SERIAL_CONSOLE) +# define STM32_CONSOLE_BASE STM32_USART1_BASE +# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY +# define STM32_CONSOLE_BAUD CONFIG_USART1_BAUD +# define STM32_CONSOLE_BITS CONFIG_USART1_BITS +# define STM32_CONSOLE_PARITY CONFIG_USART1_PARITY +# define STM32_CONSOLE_2STOP CONFIG_USART1_2STOP +# ifdef CONFIG_USART1_RS485 +# define STM32_CONSOLE_RS485_DIR GPIO_USART1_RS485_DIR +# if (CONFIG_USART1_RS485_DIR_POLARITY == 0) +# define STM32_CONSOLE_RS485_DIR_POLARITY false +# else +# define STM32_CONSOLE_RS485_DIR_POLARITY true +# endif +# endif +# elif defined(CONFIG_USART2_SERIAL_CONSOLE) +# define STM32_CONSOLE_BASE STM32_USART2_BASE +# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY +# define STM32_CONSOLE_BAUD CONFIG_USART2_BAUD +# define STM32_CONSOLE_BITS CONFIG_USART2_BITS +# define STM32_CONSOLE_PARITY CONFIG_USART2_PARITY +# define STM32_CONSOLE_2STOP CONFIG_USART2_2STOP +# ifdef CONFIG_USART2_RS485 +# define STM32_CONSOLE_RS485_DIR GPIO_USART2_RS485_DIR +# if (CONFIG_USART2_RS485_DIR_POLARITY == 0) +# define STM32_CONSOLE_RS485_DIR_POLARITY false +# else +# define STM32_CONSOLE_RS485_DIR_POLARITY true +# endif +# endif +# elif defined(CONFIG_USART3_SERIAL_CONSOLE) +# define STM32_CONSOLE_BASE STM32_USART3_BASE +# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY +# define STM32_CONSOLE_BAUD CONFIG_USART3_BAUD +# define STM32_CONSOLE_BITS CONFIG_USART3_BITS +# define STM32_CONSOLE_PARITY CONFIG_USART3_PARITY +# define STM32_CONSOLE_2STOP CONFIG_USART3_2STOP +# ifdef CONFIG_USART3_RS485 +# define STM32_CONSOLE_RS485_DIR GPIO_USART3_RS485_DIR +# if (CONFIG_USART3_RS485_DIR_POLARITY == 0) +# define STM32_CONSOLE_RS485_DIR_POLARITY false +# else +# define STM32_CONSOLE_RS485_DIR_POLARITY true +# endif +# endif +# elif defined(CONFIG_USART4_SERIAL_CONSOLE) +# define STM32_CONSOLE_BASE STM32_USART4_BASE +# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY +# define STM32_CONSOLE_BAUD CONFIG_USART4_BAUD +# define STM32_CONSOLE_BITS CONFIG_USART4_BITS +# define STM32_CONSOLE_PARITY CONFIG_USART4_PARITY +# define STM32_CONSOLE_2STOP CONFIG_USART4_2STOP +# ifdef CONFIG_USART4_RS485 +# define STM32_CONSOLE_RS485_DIR GPIO_USART4_RS485_DIR +# if (CONFIG_USART4_RS485_DIR_POLARITY == 0) +# define STM32_CONSOLE_RS485_DIR_POLARITY false +# else +# define STM32_CONSOLE_RS485_DIR_POLARITY true +# endif +# endif +# elif defined(CONFIG_USART5_SERIAL_CONSOLE) +# define STM32_CONSOLE_BASE STM32_USART5_BASE +# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY +# define STM32_CONSOLE_BAUD CONFIG_USART5_BAUD +# define STM32_CONSOLE_BITS CONFIG_USART5_BITS +# define STM32_CONSOLE_PARITY CONFIG_USART5_PARITY +# define STM32_CONSOLE_2STOP CONFIG_USART5_2STOP +# ifdef CONFIG_USART5_RS485 +# define STM32_CONSOLE_RS485_DIR GPIO_USART5_RS485_DIR +# if (CONFIG_USART5_RS485_DIR_POLARITY == 0) +# define STM32_CONSOLE_RS485_DIR_POLARITY false +# else +# define STM32_CONSOLE_RS485_DIR_POLARITY true +# endif +# endif +# endif + + /* CR1 settings */ + +# if STM32_CONSOLE_BITS == 9 +# define USART_CR1_M0_VALUE USART_CR1_M0 +# define USART_CR1_M1_VALUE 0 +# elif STM32_CONSOLE_BITS == 7 +# define USART_CR1_M0_VALUE 0 +# define USART_CR1_M1_VALUE USART_CR1_M1 +# else /* 8 bits */ +# define USART_CR1_M0_VALUE 0 +# define USART_CR1_M1_VALUE 0 +# endif + +# if STM32_CONSOLE_PARITY == 1 /* odd parity */ +# define USART_CR1_PARITY_VALUE (USART_CR1_PCE|USART_CR1_PS) +# elif STM32_CONSOLE_PARITY == 2 /* even parity */ +# define USART_CR1_PARITY_VALUE USART_CR1_PCE +# else /* no parity */ +# define USART_CR1_PARITY_VALUE 0 +# endif + +# define USART_CR1_CLRBITS \ + (USART_CR1_UESM | USART_CR1_RE | USART_CR1_TE | USART_CR1_PS | \ + USART_CR1_PCE | USART_CR1_WAKE | USART_CR1_M0 | USART_CR1_M1 | \ + USART_CR1_MME | USART_CR1_OVER8 | USART_CR1_DEDT_MASK | \ + USART_CR1_DEAT_MASK | USART_CR1_ALLINTS) + +# define USART_CR1_SETBITS (USART_CR1_M0_VALUE|USART_CR1_M1_VALUE|USART_CR1_PARITY_VALUE) + + /* CR2 settings */ + +# if STM32_CONSOLE_2STOP != 0 +# define USART_CR2_STOP2_VALUE USART_CR2_STOP2 +# else +# define USART_CR2_STOP2_VALUE 0 +# endif + +# define USART_CR2_CLRBITS \ + (USART_CR2_ADDM7 | USART_CR2_LBDL | USART_CR2_LBDIE | USART_CR2_LBCL | \ + USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_CLKEN | USART_CR2_STOP_MASK | \ + USART_CR2_LINEN | USART_CR2_SWAP | USART_CR2_RXINV | USART_CR2_TXINV | \ + USART_CR2_DATAINV | USART_CR2_MSBFIRST | USART_CR2_ABREN | \ + USART_CR2_ABRMOD_MASK | USART_CR2_RTOEN | USART_CR2_ADD_MASK) + +# define USART_CR2_SETBITS USART_CR2_STOP2_VALUE + + /* CR3 settings */ + +# define USART_CR3_CLRBITS \ + (USART_CR3_EIE | USART_CR3_IREN | USART_CR3_IRLP | USART_CR3_HDSEL | \ + USART_CR3_NACK | USART_CR3_SCEN | USART_CR3_DMAR | USART_CR3_DMAT | \ + USART_CR3_RTSE | USART_CR3_CTSE | USART_CR3_CTSIE | USART_CR3_ONEBIT | \ + USART_CR3_OVRDIS | USART_CR3_DDRE | USART_CR3_DEM | USART_CR3_DEP | \ + USART_CR3_SCARCNT_MASK | USART_CR3_WUS_MASK | USART_CR3_WUFIE) + +# define USART_CR3_SETBITS 0 + +# undef USE_OVER8 + + /* Calculate USART BAUD rate divider */ + + /* Baud rate for standard USART (SPI mode included): + * + * In case of oversampling by 16, the equation is: + * baud = fCK / UARTDIV + * UARTDIV = fCK / baud + * + * In case of oversampling by 8, the equation is: + * + * baud = 2 * fCK / UARTDIV + * UARTDIV = 2 * fCK / baud + */ + +# define STM32_USARTDIV8 \ + (((STM32_APBCLOCK << 1) + (STM32_CONSOLE_BAUD >> 1)) / STM32_CONSOLE_BAUD) +# define STM32_USARTDIV16 \ + ((STM32_APBCLOCK + (STM32_CONSOLE_BAUD >> 1)) / STM32_CONSOLE_BAUD) + +/* Use oversamply by 8 only if the divisor is small. But what is small? */ + +# if STM32_USARTDIV8 > 100 +# define STM32_BRR_VALUE STM32_USARTDIV16 +# else +# define USE_OVER8 1 +# define STM32_BRR_VALUE \ + ((STM32_USARTDIV8 & 0xfff0) | ((STM32_USARTDIV8 & 0x000f) >> 1)) +# endif + +#endif /* HAVE_CONSOLE */ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: arm_lowputc + * + * Description: + * Output one byte on the serial console + * + ****************************************************************************/ + +void arm_lowputc(char ch) +{ +#ifdef HAVE_CONSOLE + /* Wait until the TX data register is empty */ + + while ((getreg32(STM32_CONSOLE_BASE + STM32_USART_ISR_OFFSET) & + USART_ISR_TXE) == 0); +#ifdef STM32_CONSOLE_RS485_DIR + stm32_gpiowrite(STM32_CONSOLE_RS485_DIR, + STM32_CONSOLE_RS485_DIR_POLARITY); +#endif + + /* Then send the character */ + + putreg32((uint32_t)ch, STM32_CONSOLE_BASE + STM32_USART_TDR_OFFSET); + +#ifdef STM32_CONSOLE_RS485_DIR + while ((getreg32(STM32_CONSOLE_BASE + STM32_USART_ISR_OFFSET) & + USART_ISR_TC) == 0); + stm32_gpiowrite(STM32_CONSOLE_RS485_DIR, + !STM32_CONSOLE_RS485_DIR_POLARITY); +#endif + +#endif /* HAVE_CONSOLE */ +} + +/**************************************************************************** + * Name: stm32_lowsetup + * + * Description: + * This performs basic initialization of the USART used for the serial + * console. Its purpose is to get the console output available as soon + * as possible. + * + ****************************************************************************/ + +void stm32_lowsetup(void) +{ +#if defined(HAVE_USART) +#if defined(HAVE_CONSOLE) && !defined(CONFIG_SUPPRESS_UART_CONFIG) + uint32_t cr; +#endif + + /* Setup clocking and GPIO pins for all configured USARTs */ + +#ifdef CONFIG_STM32_USART1 + /* Enable USART APB2 clock */ + + modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_USART1EN); + + /* Configure RX/TX pins */ + + stm32_configgpio(GPIO_USART1_TX); + stm32_configgpio(GPIO_USART1_RX); + +#ifdef CONFIG_USART1_RS485 + stm32_configgpio(GPIO_USART1_RS485_DIR); + stm32_gpiowrite(GPIO_USART1_RS485_DIR, !CONFIG_USART1_RS485_DIR_POLARITY); +#endif +#endif + +#ifdef CONFIG_STM32_USART2 + /* Enable USART APB1 clock */ + + modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_USART2EN); + + /* Configure RX/TX pins */ + + stm32_configgpio(GPIO_USART2_TX); + stm32_configgpio(GPIO_USART2_RX); + +#ifdef CONFIG_USART2_RS485 + stm32_configgpio(GPIO_USART2_RS485_DIR); + stm32_gpiowrite(GPIO_USART2_RS485_DIR, !CONFIG_USART2_RS485_DIR_POLARITY); +#endif +#endif + +#ifdef CONFIG_STM32_USART3 + /* Enable USART APB1 clock */ + + modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_USART3EN); + + /* Configure RX/TX pins */ + + stm32_configgpio(GPIO_USART3_TX); + stm32_configgpio(GPIO_USART3_RX); + +#ifdef CONFIG_USART3_RS485 + stm32_configgpio(GPIO_USART3_RS485_DIR); + stm32_gpiowrite(GPIO_USART3_RS485_DIR, !CONFIG_USART3_RS485_DIR_POLARITY); +#endif +#endif + +#ifdef CONFIG_STM32_USART4 + /* Enable USART APB1 clock */ + + modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_USART4EN); + + /* Configure RX/TX pins */ + + stm32_configgpio(GPIO_USART4_TX); + stm32_configgpio(GPIO_USART4_RX); + +#ifdef CONFIG_USART4_RS485 + stm32_configgpio(GPIO_USART4_RS485_DIR); + stm32_gpiowrite(GPIO_USART4_RS485_DIR, !CONFIG_USART4_RS485_DIR_POLARITY); +#endif +#endif + +#ifdef CONFIG_STM32_USART5 + /* Enable USART APB1 clock */ + + modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_USART5EN); + + /* Configure RX/TX pins */ + + stm32_configgpio(GPIO_USART5_TX); + stm32_configgpio(GPIO_USART5_RX); + +#ifdef CONFIG_USART5_RS485 + stm32_configgpio(GPIO_USART5_RS485_DIR); + stm32_gpiowrite(GPIO_USART5_RS485_DIR, !CONFIG_USART5_RS485_DIR_POLARITY); +#endif +#endif + + /* Enable and configure the selected console device */ + +#if defined(HAVE_CONSOLE) && !defined(CONFIG_SUPPRESS_UART_CONFIG) + /* Configure CR2 */ + + cr = getreg32(STM32_CONSOLE_BASE + STM32_USART_CR2_OFFSET); + cr &= ~USART_CR2_CLRBITS; + cr |= USART_CR2_SETBITS; + putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR2_OFFSET); + + /* Configure CR1 */ + + cr = getreg32(STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET); + cr &= ~USART_CR1_CLRBITS; + cr |= USART_CR1_SETBITS; + putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET); + + /* Configure CR3 */ + + cr = getreg32(STM32_CONSOLE_BASE + STM32_USART_CR3_OFFSET); + cr &= ~USART_CR3_CLRBITS; + cr |= USART_CR3_SETBITS; + putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR3_OFFSET); + + /* Configure the USART Baud Rate */ + + putreg32(STM32_BRR_VALUE, STM32_CONSOLE_BASE + STM32_USART_BRR_OFFSET); + + /* Select oversampling by 8 */ + + cr = getreg32(STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET); +#ifdef USE_OVER8 + cr |= USART_CR1_OVER8; + putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET); +#endif + + /* Enable Rx, Tx, and the USART */ + + cr |= (USART_CR1_UE | USART_CR1_TE | USART_CR1_RE); + putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET); + +#endif /* HAVE_CONSOLE && !CONFIG_SUPPRESS_UART_CONFIG */ +#endif /* HAVE_USART */ +} diff --git a/arch/arm/src/common/stm32/stm32_lowputc_usart_m0_v4.c b/arch/arm/src/common/stm32/stm32_lowputc_usart_m0_v4.c new file mode 100644 index 0000000000000..154051ca63cc2 --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_lowputc_usart_m0_v4.c @@ -0,0 +1,354 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_lowputc_usart_m0_v4.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include "arm_internal.h" +#include "chip.h" + +#include "hardware/stm32_pinmap.h" +#include "stm32_rcc.h" +#include "stm32_gpio.h" +#include "stm32_uart.h" + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Select USART parameters for the selected console */ + +#ifdef HAVE_CONSOLE +# if defined(CONFIG_USART1_SERIAL_CONSOLE) +# define STM32_CONSOLE_BASE STM32_USART1_BASE +# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY +# define STM32_CONSOLE_APBREG STM32_RCC_APB2ENR +# define STM32_CONSOLE_APBEN RCC_APB2ENR_USART1EN +# define STM32_CONSOLE_BAUD CONFIG_USART1_BAUD +# define STM32_CONSOLE_BITS CONFIG_USART1_BITS +# define STM32_CONSOLE_PARITY CONFIG_USART1_PARITY +# define STM32_CONSOLE_2STOP CONFIG_USART1_2STOP +# define STM32_CONSOLE_TX GPIO_USART1_TX +# define STM32_CONSOLE_RX GPIO_USART1_RX +# ifdef CONFIG_USART1_RS485 +# define STM32_CONSOLE_RS485_DIR GPIO_USART1_RS485_DIR +# if (CONFIG_USART1_RS485_DIR_POLARITY == 0) +# define STM32_CONSOLE_RS485_DIR_POLARITY false +# else +# define STM32_CONSOLE_RS485_DIR_POLARITY true +# endif +# endif +# elif defined(CONFIG_USART2_SERIAL_CONSOLE) +# define STM32_CONSOLE_BASE STM32_USART2_BASE +# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY +# define STM32_CONSOLE_APBREG STM32_RCC_APB1ENR +# define STM32_CONSOLE_APBEN RCC_APB1ENR_USART2EN +# define STM32_CONSOLE_BAUD CONFIG_USART2_BAUD +# define STM32_CONSOLE_BITS CONFIG_USART2_BITS +# define STM32_CONSOLE_PARITY CONFIG_USART2_PARITY +# define STM32_CONSOLE_2STOP CONFIG_USART2_2STOP +# define STM32_CONSOLE_TX GPIO_USART2_TX +# define STM32_CONSOLE_RX GPIO_USART2_RX +# ifdef CONFIG_USART2_RS485 +# define STM32_CONSOLE_RS485_DIR GPIO_USART2_RS485_DIR +# if (CONFIG_USART2_RS485_DIR_POLARITY == 0) +# define STM32_CONSOLE_RS485_DIR_POLARITY false +# else +# define STM32_CONSOLE_RS485_DIR_POLARITY true +# endif +# endif +# elif defined(CONFIG_USART3_SERIAL_CONSOLE) +# define STM32_CONSOLE_BASE STM32_USART3_BASE +# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY +# define STM32_CONSOLE_APBREG STM32_RCC_APB1ENR +# define STM32_CONSOLE_APBEN RCC_APB1ENR_USART3EN +# define STM32_CONSOLE_BAUD CONFIG_USART3_BAUD +# define STM32_CONSOLE_BITS CONFIG_USART3_BITS +# define STM32_CONSOLE_PARITY CONFIG_USART3_PARITY +# define STM32_CONSOLE_2STOP CONFIG_USART3_2STOP +# define STM32_CONSOLE_TX GPIO_USART3_TX +# define STM32_CONSOLE_RX GPIO_USART3_RX +# ifdef CONFIG_USART3_RS485 +# define STM32_CONSOLE_RS485_DIR GPIO_USART3_RS485_DIR +# if (CONFIG_USART3_RS485_DIR_POLARITY == 0) +# define STM32_CONSOLE_RS485_DIR_POLARITY false +# else +# define STM32_CONSOLE_RS485_DIR_POLARITY true +# endif +# endif +# elif defined(CONFIG_USART4_SERIAL_CONSOLE) +# define STM32_CONSOLE_BASE STM32_USART4_BASE +# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY +# define STM32_CONSOLE_APBREG STM32_RCC_APB1ENR +# define STM32_CONSOLE_APBEN RCC_APB1ENR_USART4EN +# define STM32_CONSOLE_BAUD CONFIG_USART4_BAUD +# define STM32_CONSOLE_BITS CONFIG_USART4_BITS +# define STM32_CONSOLE_PARITY CONFIG_USART4_PARITY +# define STM32_CONSOLE_2STOP CONFIG_USART4_2STOP +# define STM32_CONSOLE_TX GPIO_USART4_TX +# define STM32_CONSOLE_RX GPIO_USART4_RX +# ifdef CONFIG_USART4_RS485 +# define STM32_CONSOLE_RS485_DIR GPIO_USART4_RS485_DIR +# if (CONFIG_USART4_RS485_DIR_POLARITY == 0) +# define STM32_CONSOLE_RS485_DIR_POLARITY false +# else +# define STM32_CONSOLE_RS485_DIR_POLARITY true +# endif +# endif +# endif + + /* CR1 settings */ + +# if STM32_CONSOLE_BITS == 7 +# define USART_CR_M01_VALUE USART_CR1_M1 +# elif STM32_CONSOLE_BITS == 9 +# define USART_CR_M01_VALUE USART_CR1_M0 +# else /* STM32_CONSOLE_BITS == 8 */ +# define USART_CR_M01_VALUE 0 +# endif + +# if STM32_CONSOLE_PARITY == 1 +# define USART_CR1_PARITY_VALUE (USART_CR1_PCE|USART_CR1_PS) +# elif STM32_CONSOLE_PARITY == 2 +# define USART_CR1_PARITY_VALUE USART_CR1_PCE +# else +# define USART_CR1_PARITY_VALUE 0 +# endif + +# define USART_CR1_CLRBITS \ + (USART_CR1_RE | USART_CR1_TE | USART_CR1_PS | USART_CR1_PCE | \ + USART_CR1_WAKE | USART_CR1_M0 | USART_CR1_MME | USART_CR1_OVER8 | \ + USART_CR1_DEDT_MASK | USART_CR1_DEAT_MASK | USART_CR1_ALLINTS) + +# define USART_CR1_SETBITS (USART_CR_M01_VALUE | USART_CR1_PARITY_VALUE) + + /* CR2 settings */ + +# if STM32_CONSOLE_2STOP != 0 +# define USART_CR2_STOP2_VALUE USART_CR2_STOP2 +# else +# define USART_CR2_STOP2_VALUE 0 +# endif + +# define USART_CR2_CLRBITS \ + (USART_CR2_ADDM7 | USART_CR2_LBDL | USART_CR2_LBDIE | USART_CR2_LBCL | \ + USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_CLKEN | USART_CR2_STOP_MASK | \ + USART_CR2_LINEN | USART_CR2_RXINV | USART_CR2_TXINV | USART_CR2_DATAINV | \ + USART_CR2_MSBFIRST | USART_CR2_ABREN | USART_CR2_ABRMOD_MASK | \ + USART_CR2_RTOEN | USART_CR2_ADD8_MASK) + +# define USART_CR2_SETBITS USART_CR2_STOP2_VALUE + + /* CR3 settings */ + +# define USART_CR3_CLRBITS \ + (USART_CR3_EIE | USART_CR3_IREN | USART_CR3_IRLP | USART_CR3_HDSEL | \ + USART_CR3_NACK | USART_CR3_SCEN | USART_CR3_DMAR | USART_CR3_DMAT | \ + USART_CR3_RTSE | USART_CR3_CTSE | USART_CR3_CTSIE | USART_CR3_ONEBIT | \ + USART_CR3_OVRDIS | USART_CR3_DDRE | USART_CR3_DEM | USART_CR3_DEP | \ + USART_CR3_SCARCNT_MASK) + +# define USART_CR3_SETBITS 0 + + /* Only the STM32 F3 supports oversampling by 8 */ + +# undef USE_OVER8 + +/* Calculate USART BAUD rate divider */ + +/* Baud rate for standard USART (SPI mode included): + * + * In case of oversampling by 16, the equation is: + * baud = fCK / UARTDIV + * UARTDIV = fCK / baud + * + * In case of oversampling by 8, the equation is: + * + * baud = 2 * fCK / UARTDIV + * UARTDIV = 2 * fCK / baud + */ + +# define STM32_USARTDIV8 \ + (((STM32_APBCLOCK << 1) + (STM32_CONSOLE_BAUD >> 1)) / STM32_CONSOLE_BAUD) +# define STM32_USARTDIV16 \ + ((STM32_APBCLOCK + (STM32_CONSOLE_BAUD >> 1)) / STM32_CONSOLE_BAUD) + +/* Use oversampling by 8 only if the divisor is small. But what is small? */ + +# if STM32_USARTDIV8 > 100 +# define STM32_BRR_VALUE STM32_USARTDIV16 +# else +# define USE_OVER8 1 +# define STM32_BRR_VALUE \ + ((STM32_USARTDIV8 & 0xfff0) | ((STM32_USARTDIV8 & 0x000f) >> 1)) +# endif +#endif /* HAVE_CONSOLE */ + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: arm_lowputc + * + * Description: + * Output one byte on the serial console + * + ****************************************************************************/ + +void arm_lowputc(char ch) +{ +#ifdef HAVE_CONSOLE + /* Wait until the TX data register is empty */ + + while ((getreg32(STM32_CONSOLE_BASE + STM32_USART_ISR_OFFSET) & + USART_ISR_TXE) == 0); +#ifdef STM32_CONSOLE_RS485_DIR + stm32_gpiowrite(STM32_CONSOLE_RS485_DIR, STM32_CONSOLE_RS485_DIR_POLARITY); +#endif + + /* Then send the character */ + + putreg32((uint32_t)ch, STM32_CONSOLE_BASE + STM32_USART_TDR_OFFSET); + +#ifdef STM32_CONSOLE_RS485_DIR + while ((getreg32(STM32_CONSOLE_BASE + STM32_USART_ISR_OFFSET) & + USART_ISR_TC) == 0); + stm32_gpiowrite(STM32_CONSOLE_RS485_DIR, + !STM32_CONSOLE_RS485_DIR_POLARITY); +#endif + +#endif /* HAVE_CONSOLE */ +} + +/**************************************************************************** + * Name: stm32_lowsetup + * + * Description: + * This performs basic initialization of the USART used for the serial + * console. Its purpose is to get the console output available as soon + * as possible. + * + ****************************************************************************/ + +void stm32_lowsetup(void) +{ +#if defined(HAVE_USART) +#if defined(HAVE_CONSOLE) && !defined(CONFIG_SUPPRESS_UART_CONFIG) + uint32_t cr; +#endif + +#if defined(HAVE_CONSOLE) + /* Enable USART APB1/2 clock */ + + modifyreg32(STM32_CONSOLE_APBREG, 0, STM32_CONSOLE_APBEN); +#endif + + /* Enable the console USART and configure GPIO pins needed for rx/tx. + * + * NOTE: Clocking for selected U[S]ARTs was already provided in stm32_rcc.c + */ + +#ifdef STM32_CONSOLE_TX + stm32_configgpio(STM32_CONSOLE_TX); +#endif +#ifdef STM32_CONSOLE_RX + stm32_configgpio(STM32_CONSOLE_RX); +#endif + +#ifdef STM32_CONSOLE_RS485_DIR + stm32_configgpio(STM32_CONSOLE_RS485_DIR); + stm32_gpiowrite(STM32_CONSOLE_RS485_DIR, + !STM32_CONSOLE_RS485_DIR_POLARITY); +#endif + + /* Enable and configure the selected console device */ + +#if defined(HAVE_CONSOLE) && !defined(CONFIG_SUPPRESS_UART_CONFIG) + /* Configure CR2 */ + + cr = getreg32(STM32_CONSOLE_BASE + STM32_USART_CR2_OFFSET); + cr &= ~USART_CR2_CLRBITS; + cr |= USART_CR2_SETBITS; + putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR2_OFFSET); + + /* Configure CR1 */ + + cr = getreg32(STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET); + cr &= ~USART_CR1_CLRBITS; + cr |= USART_CR1_SETBITS; + putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET); + + /* Configure CR3 */ + + cr = getreg32(STM32_CONSOLE_BASE + STM32_USART_CR3_OFFSET); + cr &= ~USART_CR3_CLRBITS; + cr |= USART_CR3_SETBITS; + putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR3_OFFSET); + + /* Configure the USART Baud Rate */ + + putreg32(STM32_BRR_VALUE, STM32_CONSOLE_BASE + STM32_USART_BRR_OFFSET); + + /* Select oversampling by 8 */ + + cr = getreg32(STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET); +#ifdef USE_OVER8 + cr |= USART_CR1_OVER8; + putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET); +#endif + + /* Enable Rx, Tx and the USART */ + + cr |= (USART_CR1_UE | USART_CR1_TE | USART_CR1_RE); + putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET); + +#endif /* HAVE_CONSOLE && !CONFIG_SUPPRESS_UART_CONFIG */ +#endif /* HAVE_USART */ +} diff --git a/arch/arm/src/common/stm32/stm32_lowputc_usart_m3m4_v1v2v3v4.c b/arch/arm/src/common/stm32/stm32_lowputc_usart_m3m4_v1v2v3v4.c new file mode 100644 index 0000000000000..aa83d21a3b3e2 --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_lowputc_usart_m3m4_v1v2v3v4.c @@ -0,0 +1,694 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_lowputc_usart_m3m4_v1v2v3v4.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include + +#include "arm_internal.h" +#include "chip.h" + +#include "stm32.h" +#include "stm32_rcc.h" +#include "stm32_gpio.h" +#include "stm32_uart.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Select USART parameters for the selected console */ + +#ifdef HAVE_CONSOLE +# if defined(CONFIG_USART1_SERIAL_CONSOLE) +# define STM32_CONSOLE_BASE STM32_USART1_BASE +# if defined(CONFIG_STM32_STM32F33XX) +# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY /* Errata 2.5.1 */ +# else +# define STM32_APBCLOCK STM32_PCLK2_FREQUENCY +# endif +# define STM32_CONSOLE_APBREG STM32_RCC_APB2ENR +# define STM32_CONSOLE_APBEN RCC_APB2ENR_USART1EN +# define STM32_CONSOLE_BAUD CONFIG_USART1_BAUD +# define STM32_CONSOLE_BITS CONFIG_USART1_BITS +# define STM32_CONSOLE_PARITY CONFIG_USART1_PARITY +# define STM32_CONSOLE_2STOP CONFIG_USART1_2STOP +# define STM32_CONSOLE_TX GPIO_USART1_TX +# define STM32_CONSOLE_RX GPIO_USART1_RX +# ifdef CONFIG_USART1_RS485 +# define STM32_CONSOLE_RS485_DIR GPIO_USART1_RS485_DIR +# if (CONFIG_USART1_RS485_DIR_POLARITY == 0) +# define STM32_CONSOLE_RS485_DIR_POLARITY false +# else +# define STM32_CONSOLE_RS485_DIR_POLARITY true +# endif +# endif +# elif defined(CONFIG_USART2_SERIAL_CONSOLE) +# define STM32_CONSOLE_BASE STM32_USART2_BASE +# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY +# define STM32_CONSOLE_APBREG STM32_RCC_APB1ENR +# define STM32_CONSOLE_APBEN RCC_APB1ENR_USART2EN +# define STM32_CONSOLE_BAUD CONFIG_USART2_BAUD +# define STM32_CONSOLE_BITS CONFIG_USART2_BITS +# define STM32_CONSOLE_PARITY CONFIG_USART2_PARITY +# define STM32_CONSOLE_2STOP CONFIG_USART2_2STOP +# define STM32_CONSOLE_TX GPIO_USART2_TX +# define STM32_CONSOLE_RX GPIO_USART2_RX +# ifdef CONFIG_USART2_RS485 +# define STM32_CONSOLE_RS485_DIR GPIO_USART2_RS485_DIR +# if (CONFIG_USART2_RS485_DIR_POLARITY == 0) +# define STM32_CONSOLE_RS485_DIR_POLARITY false +# else +# define STM32_CONSOLE_RS485_DIR_POLARITY true +# endif +# endif +# elif defined(CONFIG_USART3_SERIAL_CONSOLE) +# define STM32_CONSOLE_BASE STM32_USART3_BASE +# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY +# define STM32_CONSOLE_APBREG STM32_RCC_APB1ENR +# define STM32_CONSOLE_APBEN RCC_APB1ENR_USART3EN +# define STM32_CONSOLE_BAUD CONFIG_USART3_BAUD +# define STM32_CONSOLE_BITS CONFIG_USART3_BITS +# define STM32_CONSOLE_PARITY CONFIG_USART3_PARITY +# define STM32_CONSOLE_2STOP CONFIG_USART3_2STOP +# define STM32_CONSOLE_TX GPIO_USART3_TX +# define STM32_CONSOLE_RX GPIO_USART3_RX +# ifdef CONFIG_USART3_RS485 +# define STM32_CONSOLE_RS485_DIR GPIO_USART3_RS485_DIR +# if (CONFIG_USART3_RS485_DIR_POLARITY == 0) +# define STM32_CONSOLE_RS485_DIR_POLARITY false +# else +# define STM32_CONSOLE_RS485_DIR_POLARITY true +# endif +# endif +# elif defined(CONFIG_UART4_SERIAL_CONSOLE) +# define STM32_CONSOLE_BASE STM32_UART4_BASE +# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY +# define STM32_CONSOLE_APBREG STM32_RCC_APB1ENR +# define STM32_CONSOLE_APBEN RCC_APB1ENR_UART4EN +# define STM32_CONSOLE_BAUD CONFIG_UART4_BAUD +# define STM32_CONSOLE_BITS CONFIG_UART4_BITS +# define STM32_CONSOLE_PARITY CONFIG_UART4_PARITY +# define STM32_CONSOLE_2STOP CONFIG_UART4_2STOP +# define STM32_CONSOLE_TX GPIO_UART4_TX +# define STM32_CONSOLE_RX GPIO_UART4_RX +# ifdef CONFIG_UART4_RS485 +# define STM32_CONSOLE_RS485_DIR GPIO_UART4_RS485_DIR +# if (CONFIG_UART4_RS485_DIR_POLARITY == 0) +# define STM32_CONSOLE_RS485_DIR_POLARITY false +# else +# define STM32_CONSOLE_RS485_DIR_POLARITY true +# endif +# endif +# elif defined(CONFIG_UART5_SERIAL_CONSOLE) +# define STM32_CONSOLE_BASE STM32_UART5_BASE +# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY +# define STM32_CONSOLE_APBREG STM32_RCC_APB1ENR +# define STM32_CONSOLE_APBEN RCC_APB1ENR_UART5EN +# define STM32_CONSOLE_BAUD CONFIG_UART5_BAUD +# define STM32_CONSOLE_BITS CONFIG_UART5_BITS +# define STM32_CONSOLE_PARITY CONFIG_UART5_PARITY +# define STM32_CONSOLE_2STOP CONFIG_UART5_2STOP +# define STM32_CONSOLE_TX GPIO_UART5_TX +# define STM32_CONSOLE_RX GPIO_UART5_RX +# ifdef CONFIG_UART5_RS485 +# define STM32_CONSOLE_RS485_DIR GPIO_UART5_RS485_DIR +# if (CONFIG_UART5_RS485_DIR_POLARITY == 0) +# define STM32_CONSOLE_RS485_DIR_POLARITY false +# else +# define STM32_CONSOLE_RS485_DIR_POLARITY true +# endif +# endif +# elif defined(CONFIG_USART6_SERIAL_CONSOLE) +# define STM32_CONSOLE_BASE STM32_USART6_BASE +# define STM32_APBCLOCK STM32_PCLK2_FREQUENCY +# define STM32_CONSOLE_APBREG STM32_RCC_APB2ENR +# define STM32_CONSOLE_APBEN RCC_APB2ENR_USART6EN +# define STM32_CONSOLE_BAUD CONFIG_USART6_BAUD +# define STM32_CONSOLE_BITS CONFIG_USART6_BITS +# define STM32_CONSOLE_PARITY CONFIG_USART6_PARITY +# define STM32_CONSOLE_2STOP CONFIG_USART6_2STOP +# define STM32_CONSOLE_TX GPIO_USART6_TX +# define STM32_CONSOLE_RX GPIO_USART6_RX +# ifdef CONFIG_USART6_RS485 +# define STM32_CONSOLE_RS485_DIR GPIO_USART6_RS485_DIR +# if (CONFIG_USART6_RS485_DIR_POLARITY == 0) +# define STM32_CONSOLE_RS485_DIR_POLARITY false +# else +# define STM32_CONSOLE_RS485_DIR_POLARITY true +# endif +# endif +# elif defined(CONFIG_UART7_SERIAL_CONSOLE) +# define STM32_CONSOLE_BASE STM32_UART7_BASE +# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY +# define STM32_CONSOLE_APBREG STM32_RCC_APB1ENR +# define STM32_CONSOLE_APBEN RCC_APB1ENR_UART7EN +# define STM32_CONSOLE_BAUD CONFIG_UART7_BAUD +# define STM32_CONSOLE_BITS CONFIG_UART7_BITS +# define STM32_CONSOLE_PARITY CONFIG_UART7_PARITY +# define STM32_CONSOLE_2STOP CONFIG_UART7_2STOP +# define STM32_CONSOLE_TX GPIO_UART7_TX +# define STM32_CONSOLE_RX GPIO_UART7_RX +# ifdef CONFIG_UART7_RS485 +# define STM32_CONSOLE_RS485_DIR GPIO_UART7_RS485_DIR +# if (CONFIG_UART7_RS485_DIR_POLARITY == 0) +# define STM32_CONSOLE_RS485_DIR_POLARITY false +# else +# define STM32_CONSOLE_RS485_DIR_POLARITY true +# endif +# endif +# elif defined(CONFIG_UART8_SERIAL_CONSOLE) +# define STM32_CONSOLE_BASE STM32_UART8_BASE +# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY +# define STM32_CONSOLE_APBREG STM32_RCC_APB1ENR +# define STM32_CONSOLE_APBEN RCC_APB1ENR_UART8EN +# define STM32_CONSOLE_BAUD CONFIG_UART8_BAUD +# define STM32_CONSOLE_BITS CONFIG_UART8_BITS +# define STM32_CONSOLE_PARITY CONFIG_UART8_PARITY +# define STM32_CONSOLE_2STOP CONFIG_UART8_2STOP +# define STM32_CONSOLE_TX GPIO_UART8_TX +# define STM32_CONSOLE_RX GPIO_UART8_RX +# ifdef CONFIG_UART8_RS485 +# define STM32_CONSOLE_RS485_DIR GPIO_UART8_RS485_DIR +# if (CONFIG_UART8_RS485_DIR_POLARITY == 0) +# define STM32_CONSOLE_RS485_DIR_POLARITY false +# else +# define STM32_CONSOLE_RS485_DIR_POLARITY true +# endif +# endif +# elif defined(CONFIG_LPUART1_SERIAL_CONSOLE) +# define STM32_CONSOLE_BASE STM32_LPUART1_BASE +# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY +# define STM32_CONSOLE_APBREG STM32_RCC_APB1ENR2 +# define STM32_CONSOLE_APBEN RCC_APB1ENR2_LPUART1EN +# define STM32_CONSOLE_BAUD CONFIG_LPUART1_BAUD +# define STM32_CONSOLE_BITS CONFIG_LPUART1_BITS +# define STM32_CONSOLE_PARITY CONFIG_LPUART1_PARITY +# define STM32_CONSOLE_2STOP CONFIG_LPUART1_2STOP +# define STM32_CONSOLE_TX GPIO_LPUART1_TX +# define STM32_CONSOLE_RX GPIO_LPUART1_RX +# ifdef CONFIG_LPUART1_RS485 +# define STM32_CONSOLE_RS485_DIR GPIO_LPUART1_RS485_DIR +# if (CONFIG_LPUART1_RS485_DIR_POLARITY == 0) +# define STM32_CONSOLE_RS485_DIR_POLARITY false +# else +# define STM32_CONSOLE_RS485_DIR_POLARITY true +# endif +# endif +# endif + +/* CR1 settings */ + +# if STM32_CONSOLE_BITS == 9 +# define USART_CR1_M_VALUE USART_CR1_M +# else +# define USART_CR1_M_VALUE 0 +# endif + +# if STM32_CONSOLE_PARITY == 1 +# define USART_CR1_PARITY_VALUE (USART_CR1_PCE|USART_CR1_PS) +# elif STM32_CONSOLE_PARITY == 2 +# define USART_CR1_PARITY_VALUE USART_CR1_PCE +# else +# define USART_CR1_PARITY_VALUE 0 +# endif + +# if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) || \ + defined(CONFIG_STM32_STM32F37XX) || defined(CONFIG_STM32_STM32G4XXX) +# define USART_CR1_CLRBITS\ + (USART_CR1_UESM | USART_CR1_RE | USART_CR1_TE | USART_CR1_PS | \ + USART_CR1_PCE | USART_CR1_WAKE | USART_CR1_M | USART_CR1_MME | \ + USART_CR1_OVER8 | USART_CR1_DEDT_MASK | USART_CR1_DEAT_MASK | \ + USART_CR1_ALLINTS) +# else +# define USART_CR1_CLRBITS\ + (USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | \ + USART_CR1_RE | USART_CR1_ALLINTS) +# endif + +# define USART_CR1_SETBITS (USART_CR1_M_VALUE|USART_CR1_PARITY_VALUE) + +/* CR2 settings */ + +# if STM32_CONSOLE_2STOP != 0 +# define USART_CR2_STOP2_VALUE USART_CR2_STOP2 +# else +# define USART_CR2_STOP2_VALUE 0 +# endif + +# if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) || \ + defined(CONFIG_STM32_STM32F37XX) || defined(CONFIG_STM32_STM32G4XXX) +# define USART_CR2_CLRBITS \ + (USART_CR2_ADDM7 | USART_CR2_LBDL | USART_CR2_LBDIE | USART_CR2_LBCL | \ + USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_CLKEN | USART_CR2_STOP_MASK | \ + USART_CR2_LINEN | USART_CR2_RXINV | USART_CR2_TXINV | USART_CR2_DATAINV | \ + USART_CR2_MSBFIRST | USART_CR2_ABREN | USART_CR2_ABRMOD_MASK | \ + USART_CR2_RTOEN | USART_CR2_ADD8_MASK) +# else +# define USART_CR2_CLRBITS \ + (USART_CR2_STOP_MASK | USART_CR2_CLKEN | USART_CR2_CPOL | USART_CR2_CPHA | \ + USART_CR2_LBCL | USART_CR2_LBDIE) +# endif +# define USART_CR2_SETBITS USART_CR2_STOP2_VALUE + +/* CR3 settings */ + +# if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) || \ + defined(CONFIG_STM32_STM32F37XX) || defined(CONFIG_STM32_STM32G4XXX) + +# define USART_CR3_CLRBITS \ + (USART_CR3_EIE | USART_CR3_IREN | USART_CR3_IRLP | USART_CR3_HDSEL | \ + USART_CR3_NACK | USART_CR3_SCEN | USART_CR3_DMAR | USART_CR3_DMAT | \ + USART_CR3_RTSE | USART_CR3_CTSE | USART_CR3_CTSIE | USART_CR3_ONEBIT | \ + USART_CR3_OVRDIS | USART_CR3_DDRE | USART_CR3_DEM | USART_CR3_DEP | \ + USART_CR3_SCARCNT_MASK | USART_CR3_WUS_MASK | USART_CR3_WUFIE) +# else +# define USART_CR3_CLRBITS \ + (USART_CR3_CTSIE | USART_CR3_CTSE | USART_CR3_RTSE | USART_CR3_EIE) +# endif +# define USART_CR3_SETBITS 0 + +/* Only the STM32 F3 supports oversampling by 8 */ + +# undef USE_OVER8 + +/* Calculate USART BAUD rate divider */ +# if CONSOLE_LPUART > 0 && defined(CONFIG_STM32_STM32G4XXX) + + /* BRR = (256 * (APBCLOCK / Prescaler)) / (Baud rate) + * With Prescaler == 16, BRR = (16 * APBCLOCK / (Baud rate) + * Set Prescaler to 16 to support wide range of standard baud rates + */ + +# define STM32_BRR_VALUE \ + (((STM32_APBCLOCK & 0xf0000000) / STM32_CONSOLE_BAUD) << 4) + \ + (((STM32_APBCLOCK & 0x0fffffff) << 4) / STM32_CONSOLE_BAUD) +# define STM32_PRESC_VALUE 0x7 + +# else + +# if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) || \ + defined(CONFIG_STM32_STM32F37XX) || defined(CONFIG_STM32_STM32G4XXX) + + /* Baud rate for standard USART (SPI mode included): + * + * In case of oversampling by 16, the equation is: + * baud = fCK / UARTDIV + * UARTDIV = fCK / baud + * + * In case of oversampling by 8, the equation is: + * + * baud = 2 * fCK / UARTDIV + * UARTDIV = 2 * fCK / baud + */ + +# define STM32_USARTDIV8 \ + (((STM32_APBCLOCK << 1) + (STM32_CONSOLE_BAUD >> 1)) / STM32_CONSOLE_BAUD) +# define STM32_USARTDIV16 \ + ((STM32_APBCLOCK + (STM32_CONSOLE_BAUD >> 1)) / STM32_CONSOLE_BAUD) +/* Use oversamply by 8 only if the divisor is small. But what is small? */ + +# if STM32_USARTDIV8 > 100 +# define STM32_BRR_VALUE STM32_USARTDIV16 +# else +# define USE_OVER8 1 +# define STM32_BRR_VALUE \ + ((STM32_USARTDIV8 & 0xfff0) | ((STM32_USARTDIV8 & 0x000f) >> 1)) +# endif + +# else /* CONFIG_STM32_STM32F30XX */ + +/* The baud rate for the receiver and transmitter (Rx and Tx) are both set + * to the same value as programmed in the Mantissa and Fraction values of + * USARTDIV. + * + * baud = fCK / (16 * usartdiv) + * usartdiv = fCK / (16 * baud) + * + * Where fCK is the input clock to the peripheral (PCLK1 for USART2, 3, 4, + * 5 or PCLK2 for USART1). Example, fCK=72MHz baud=115200, + * usartdiv=39.0625=39 1/16th; + * + * First calculate: + * + * usartdiv32 = 32 * usartdiv = fCK / (baud/2) + * + * (NOTE: all standard baud values are even so dividing by two does not + * lose precision). Eg. (same fCK and baud), usartdiv32 = 1250 + */ + +# define STM32_USARTDIV32 (STM32_APBCLOCK / (STM32_CONSOLE_BAUD >> 1)) + +/* The mantissa is then usartdiv32 / 32: + * + * mantissa = usartdiv32 / 32/ + * + * Eg. usartdiv32=1250, mantissa = 39 + */ + +# define STM32_MANTISSA (STM32_USARTDIV32 >> 5) + +/* And the fraction: + * + * fraction = (usartdiv32 - mantissa*32 + 1) / 2 + * + * Eg., (1,250 - 39*32 + 1)/2 = 1 (or 0.0625) + */ + +# define STM32_FRACTION \ + ((STM32_USARTDIV32 - (STM32_MANTISSA << 5) + 1) >> 1) + + /* And, finally, the BRR value is: */ + + # define STM32_BRR_VALUE \ + ((STM32_MANTISSA << USART_BRR_MANT_SHIFT) | \ + (STM32_FRACTION << USART_BRR_FRAC_SHIFT)) + +# endif /* CONFIG_STM32_STM32F30XX */ +# endif /* CONSOLE_LPUART > 0 */ +#endif /* HAVE_CONSOLE */ + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: arm_lowputc + * + * Description: + * Output one byte on the serial console + * + ****************************************************************************/ + +void arm_lowputc(char ch) +{ +#ifdef HAVE_CONSOLE + /* Wait until the TX data register is empty */ + + while ((getreg32(STM32_CONSOLE_BASE + STM32_USART_SR_OFFSET) & + USART_SR_TC) == 0); +#ifdef STM32_CONSOLE_RS485_DIR + stm32_gpiowrite(STM32_CONSOLE_RS485_DIR, + STM32_CONSOLE_RS485_DIR_POLARITY); +#endif + + /* Then send the character */ + + putreg32((uint32_t)ch, STM32_CONSOLE_BASE + STM32_USART_TDR_OFFSET); + +#ifdef STM32_CONSOLE_RS485_DIR + while ((getreg32(STM32_CONSOLE_BASE + STM32_USART_SR_OFFSET) & + USART_SR_TC) == 0); + stm32_gpiowrite(STM32_CONSOLE_RS485_DIR, + !STM32_CONSOLE_RS485_DIR_POLARITY); +#endif + +#endif /* HAVE_CONSOLE */ +} + +/**************************************************************************** + * Name: stm32_lowsetup + * + * Description: + * This performs basic initialization of the USART used for the serial + * console. Its purpose is to get the console output available as soon + * as possible. + * + ****************************************************************************/ + +#if defined(CONFIG_STM32_STM32F10XX) + +void stm32_lowsetup(void) +{ +#if defined(HAVE_SERIALDRIVER) + uint32_t mapr; +#if defined(HAVE_CONSOLE) && !defined(CONFIG_SUPPRESS_UART_CONFIG) + uint32_t cr; +#endif + + /* Set up the pin mapping registers for the selected U[S]ARTs. + * + * NOTE: Clocking for selected U[S]ARTs was already provided in stm32_rcc.c + */ + + mapr = getreg32(STM32_AFIO_MAPR); + +#ifdef CONFIG_STM32_USART1 + /* Assume default pin mapping: + * + * Alternate USART1_REMAP USART1_REMAP + * Function = 0 = 1 + * ---------- ------------ ------------ + * USART1_TX PA9 PB6 + * USART1_RX PA10 PB7 + */ + +#ifdef CONFIG_STM32_USART1_REMAP + mapr |= AFIO_MAPR_USART1_REMAP; +#else + mapr &= ~AFIO_MAPR_USART1_REMAP; +#endif +#endif /* CONFIG_STM32_USART1 */ + +#ifdef CONFIG_STM32_USART2 + /* Assume default pin mapping: + * + * Alternate USART2_REMAP USART2_REMAP + * Function = 0 = 1 + * ---------- ------------ ------------ + * USART2_CTS PA0 PD3 + * USART2_RTS PA1 PD4 + * USART2_TX PA2 PD5 + * USART2_RX PA3 PD6 + * USART3_CK PA4 PD7 + */ + +#ifdef CONFIG_STM32_USART2_REMAP + mapr |= AFIO_MAPR_USART2_REMAP; +#else + mapr &= ~AFIO_MAPR_USART2_REMAP; +#endif +#endif /* CONFIG_STM32_USART2 */ + + /* Assume default pin mapping: + * + * Alternate USART3_REMAP[1:0] USART3_REMAP[1:0] USART3_REMAP[1:0] + * Function = 00 (no remap) = 01 (partial remap) = 11 (full remap) + * ---------_ ------------------ ---------------------- ----------------- + * USART3_TX PB10 PC10 PD8 + * USART3_RX PB11 PC11 PD9 + * USART3_CK PB12 PC12 PD10 + * USART3_CTS PB13 PB13 PD11 + * USART3_RTS PB14 PB14 PD12 + */ + + mapr &= ~AFIO_MAPR_USART3_REMAP_MASK; + +#ifdef CONFIG_STM32_USART3 +#if defined(CONFIG_STM32_USART3_PARTIAL_REMAP) + mapr |= AFIO_MAPR_USART3_PARTREMAP; +#elif defined(CONFIG_STM32_USART3_FULL_REMAP) + mapr |= AFIO_MAPR_USART3_FULLREMAP; +#endif +#endif /* CONFIG_STM32_USART3 */ + + putreg32(mapr, STM32_AFIO_MAPR); + + /* Configure GPIO pins needed for rx/tx. */ + +#ifdef STM32_CONSOLE_TX + stm32_configgpio(STM32_CONSOLE_TX); +#endif +#ifdef STM32_CONSOLE_RX + stm32_configgpio(STM32_CONSOLE_RX); +#endif + +#ifdef STM32_CONSOLE_RS485_DIR + stm32_configgpio(STM32_CONSOLE_RS485_DIR); + stm32_gpiowrite(STM32_CONSOLE_RS485_DIR, + !STM32_CONSOLE_RS485_DIR_POLARITY); +#endif + + /* Enable and configure the selected console device */ + +#if defined(HAVE_CONSOLE) && !defined(CONFIG_SUPPRESS_UART_CONFIG) + /* Configure CR2 */ + + cr = getreg32(STM32_CONSOLE_BASE + STM32_USART_CR2_OFFSET); + cr &= ~USART_CR2_CLRBITS; + cr |= USART_CR2_SETBITS; + putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR2_OFFSET); + + /* Configure CR1 */ + + cr = getreg32(STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET); + cr &= ~USART_CR1_CLRBITS; + cr |= USART_CR1_SETBITS; + putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET); + + /* Configure CR3 */ + + cr = getreg32(STM32_CONSOLE_BASE + STM32_USART_CR3_OFFSET); + cr &= ~USART_CR3_CLRBITS; + cr |= USART_CR3_SETBITS; + putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR3_OFFSET); + + /* Configure the USART Baud Rate */ + + putreg32(STM32_BRR_VALUE, STM32_CONSOLE_BASE + STM32_USART_BRR_OFFSET); + + /* Enable Rx, Tx, and the USART */ + + cr = getreg32(STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET); + cr |= (USART_CR1_UE | USART_CR1_TE | USART_CR1_RE); + putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET); + +#endif /* HAVE_CONSOLE && !CONFIG_SUPPRESS_UART_CONFIG */ +#endif /* HAVE_SERIALDRIVER */ +} + +#elif defined(CONFIG_STM32_STM32L15XX) || defined(CONFIG_STM32_STM32F20XX) || \ + defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) || \ + defined(CONFIG_STM32_STM32F37XX) || defined(CONFIG_STM32_STM32F4XXX) || \ + defined(CONFIG_STM32_STM32G4XXX) + +void stm32_lowsetup(void) +{ +#if defined(HAVE_SERIALDRIVER) +#if defined(HAVE_CONSOLE) && !defined(CONFIG_SUPPRESS_UART_CONFIG) + uint32_t cr; +#endif + +#if defined(HAVE_CONSOLE) + /* Enable USART APB1/2 clock */ + + modifyreg32(STM32_CONSOLE_APBREG, 0, STM32_CONSOLE_APBEN); +#endif + + /* Enable the console USART and configure GPIO pins needed for rx/tx. + * + * NOTE: Clocking for selected U[S]ARTs was already provided in stm32_rcc.c + */ + +#ifdef STM32_CONSOLE_TX + stm32_configgpio(STM32_CONSOLE_TX); +#endif +#ifdef STM32_CONSOLE_RX + stm32_configgpio(STM32_CONSOLE_RX); +#endif + +#ifdef STM32_CONSOLE_RS485_DIR + stm32_configgpio(STM32_CONSOLE_RS485_DIR); + stm32_gpiowrite(STM32_CONSOLE_RS485_DIR, + !STM32_CONSOLE_RS485_DIR_POLARITY); +#endif + + /* Enable and configure the selected console device */ + +#if defined(HAVE_CONSOLE) && !defined(CONFIG_SUPPRESS_UART_CONFIG) + /* Ensure the USART is disabled because some bits of the following + * registers cannot be modified otherwise. + * + * Although the USART is expected to be disabled at power on reset, this + * might not be the case if we boot from a serial bootloader that does not + * clean up properly. + */ + + cr = getreg32(STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET); + cr &= ~USART_CR1_UE; + putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET); + + /* Configure CR2 */ + + cr = getreg32(STM32_CONSOLE_BASE + STM32_USART_CR2_OFFSET); + cr &= ~USART_CR2_CLRBITS; + cr |= USART_CR2_SETBITS; + putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR2_OFFSET); + + /* Configure CR1 */ + + cr = getreg32(STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET); + cr &= ~USART_CR1_CLRBITS; + cr |= USART_CR1_SETBITS; + putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET); + + /* Configure CR3 */ + + cr = getreg32(STM32_CONSOLE_BASE + STM32_USART_CR3_OFFSET); + cr &= ~USART_CR3_CLRBITS; + cr |= USART_CR3_SETBITS; + putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR3_OFFSET); + + /* Configure the USART Baud Rate */ + +#if CONSOLE_LPUART > 0 && defined(CONFIG_STM32_STM32G4XXX) + putreg32(STM32_PRESC_VALUE, STM32_CONSOLE_BASE + STM32_USART_PRESC_OFFSET); +#endif + + putreg32(STM32_BRR_VALUE, STM32_CONSOLE_BASE + STM32_USART_BRR_OFFSET); + + /* Select oversampling by 8 */ + + cr = getreg32(STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET); +#ifdef USE_OVER8 + cr |= USART_CR1_OVER8; + putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET); +#endif + + /* Enable Rx, Tx, and the USART */ + + cr |= (USART_CR1_UE | USART_CR1_TE | USART_CR1_RE); + putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET); + +#endif /* HAVE_CONSOLE && !CONFIG_SUPPRESS_UART_CONFIG */ +#endif /* HAVE_SERIALDRIVER */ +} + +#else +# error "Unsupported STM32 chip" +#endif diff --git a/arch/arm/src/common/stm32/stm32_lse_m0_v1.c b/arch/arm/src/common/stm32/stm32_lse_m0_v1.c new file mode 100644 index 0000000000000..0e5bc4fbc3db5 --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_lse_m0_v1.c @@ -0,0 +1,104 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_lse_m0_v1.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "arm_internal.h" +#include "stm32_pwr.h" +#include "stm32_rcc.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_rcc_enablelse + * + * Description: + * Enable the External Low-Speed (LSE) oscillator. + * + * Todo: + * Check for LSE good timeout and return with -1, + * + ****************************************************************************/ + +void stm32_rcc_enablelse(void) +{ +#ifdef HAVE_PWR_DBP + /* The LSE is in the RTC domain and write access is denied to this domain + * after reset, you have to enable write access using DBP bit in the PWR CR + * register before to configuring the LSE. + */ + + stm32_pwr_enablebkp(true); +#endif + +#if defined(CONFIG_ARCH_CHIP_STM32L0) + /* Enable the External Low-Speed (LSE) oscillator by setting the LSEON bit + * the RCC CSR register. + */ + + modifyreg32(STM32_RCC_CSR, 0, RCC_CSR_LSEON); + + /* Wait for the LSE clock to be ready */ + + while ((getreg32(STM32_RCC_CSR) & RCC_CSR_LSERDY) == 0) + { + } + +#elif defined(CONFIG_ARCH_CHIP_STM32F0) + /* Enable the External Low-Speed (LSE) oscillator by setting the LSEON bit + * the RCC BDCR register. + */ + + modifyreg16(STM32_RCC_BDCR, 0, RCC_BDCR_LSEON); + + /* Wait for the LSE clock to be ready */ + + while ((getreg16(STM32_RCC_BDCR) & RCC_BDCR_LSERDY) == 0) + { + } + +#elif defined(CONFIG_ARCH_CHIP_STM32C0) + /* Enable the External Low-Speed (LSE) oscillator by setting the LSEON bit + * the RCC CSR1 register. + */ + + modifyreg32(STM32_RCC_CSR1, 0, RCC_CSR1_LSEON); + + /* Wait for the LSE clock to be ready */ + + while ((getreg32(STM32_RCC_CSR1) & RCC_CSR1_LSERDY) == 0) + { + } +#endif + +#ifdef HAVE_PWR_DBP + /* Disable backup domain access if it was disabled on entry */ + + stm32_pwr_enablebkp(false); +#endif +} diff --git a/arch/arm/src/common/stm32/stm32_lse_m3m4_v1.c b/arch/arm/src/common/stm32/stm32_lse_m3m4_v1.c new file mode 100644 index 0000000000000..25f33542e59c4 --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_lse_m3m4_v1.c @@ -0,0 +1,91 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_lse_m3m4_v1.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "arm_internal.h" +#include "stm32_pwr.h" +#include "stm32_rcc.h" +#include "stm32_waste.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_rcc_enablelse + * + * Description: + * Enable the External Low-Speed (LSE) oscillator. + * + * Todo: + * Check for LSE good timeout and return with -1, + * + ****************************************************************************/ + +void stm32_rcc_enablelse(void) +{ + /* The LSE is in the RTC domain and write access is denied to this domain + * after reset, you have to enable write access using DBP bit in the PWR CR + * register before to configuring the LSE. + */ + + stm32_pwr_enablebkp(true); + +#if defined(CONFIG_STM32_STM32L15XX) + /* Enable the External Low-Speed (LSE) oscillator by setting the LSEON bit + * the RCC CSR register. + */ + + modifyreg32(STM32_RCC_CSR, 0, RCC_CSR_LSEON); + + /* Wait for the LSE clock to be ready */ + + while ((getreg32(STM32_RCC_CSR) & RCC_CSR_LSERDY) == 0) + { + stm32_waste(); + } + +#else + /* Enable the External Low-Speed (LSE) oscillator by setting the LSEON bit + * the RCC BDCR register. + */ + + modifyreg16(STM32_RCC_BDCR, 0, RCC_BDCR_LSEON); + + /* Wait for the LSE clock to be ready */ + + while ((getreg16(STM32_RCC_BDCR) & RCC_BDCR_LSERDY) == 0) + { + stm32_waste(); + } + +#endif + + /* Disable backup domain access if it was disabled on entry */ + + stm32_pwr_enablebkp(false); +} diff --git a/arch/arm/src/common/stm32/stm32_lsi_m0_v1.c b/arch/arm/src/common/stm32/stm32_lsi_m0_v1.c new file mode 100644 index 0000000000000..19aa04dd4f037 --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_lsi_m0_v1.c @@ -0,0 +1,94 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_lsi_m0_v1.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "arm_internal.h" +#include "stm32_rcc.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* STM32C0 uses the second CSR register for LSI. */ + +#ifdef CONFIG_ARCH_CHIP_STM32C0 +# define STM32_RCC_CSR STM32_RCC_CSR2 +# define RCC_CSR_LSION RCC_CSR2_LSION +# define RCC_CSR_LSIRDY RCC_CSR2_LSIRDY +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_rcc_enablelsi + * + * Description: + * Enable the Internal Low-Speed (LSI) RC Oscillator. + * + ****************************************************************************/ + +void stm32_rcc_enablelsi(void) +{ + /* Enable the Internal Low-Speed (LSI) RC Oscillator by setting the LSION + * bit in the RCC CSR register. + */ + + modifyreg32(STM32_RCC_CSR, 0, RCC_CSR_LSION); + + /* Wait for the internal RC 40 kHz oscillator to be stable. */ + + while ((getreg32(STM32_RCC_CSR) & RCC_CSR_LSIRDY) == 0); +} + +/**************************************************************************** + * Name: stm32_rcc_disablelsi + * + * Description: + * Disable the Internal Low-Speed (LSI) RC Oscillator. + * + ****************************************************************************/ + +void stm32_rcc_disablelsi(void) +{ + /* Enable the Internal Low-Speed (LSI) RC Oscillator by setting the LSION + * bit in the RCC CSR register. + */ + + modifyreg32(STM32_RCC_CSR, RCC_CSR_LSION, 0); + + /* LSIRDY should go low after 3 LSI clock cycles */ +} diff --git a/arch/arm/src/common/stm32/stm32_lsi_m3m4_v1.c b/arch/arm/src/common/stm32/stm32_lsi_m3m4_v1.c new file mode 100644 index 0000000000000..97ae757a001b7 --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_lsi_m3m4_v1.c @@ -0,0 +1,94 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_lsi_m3m4_v1.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "arm_internal.h" +#include "stm32_rcc.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* STM32C0 uses the second CSR register for LSI. */ + +#ifdef CONFIG_ARCH_CHIP_STM32C0 +# define STM32_RCC_CSR STM32_RCC_CSR2 +# define RCC_CSR_LSION RCC_CSR2_LSION +# define RCC_CSR_LSIRDY RCC_CSR2_LSIRDY +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_rcc_enablelsi + * + * Description: + * Enable the Internal Low-Speed (LSI) RC Oscillator. + * + ****************************************************************************/ + +void stm32_rcc_enablelsi(void) +{ + /* Enable the Internal Low-Speed (LSI) RC Oscillator by setting the LSION + * bit in the RCC CSR register. + */ + + modifyreg32(STM32_RCC_CSR, 0, RCC_CSR_LSION); + + /* Wait for the internal RC 40 kHz oscillator to be stable. */ + + while ((getreg32(STM32_RCC_CSR) & RCC_CSR_LSIRDY) == 0); +} + +/**************************************************************************** + * Name: stm32_rcc_disablelsi + * + * Description: + * Disable the Internal Low-Speed (LSI) RC Oscillator. + * + ****************************************************************************/ + +void stm32_rcc_disablelsi(void) +{ + /* Enable the Internal Low-Speed (LSI) RC Oscillator by setting the LSION + * bit in the RCC CSR register. + */ + + modifyreg32(STM32_RCC_CSR, RCC_CSR_LSION, 0); + + /* LSIRDY should go low after 3 LSI clock cycles */ +} diff --git a/arch/arm/src/common/stm32/stm32_ltdc.h b/arch/arm/src/common/stm32/stm32_ltdc.h new file mode 100644 index 0000000000000..d51c2b4ba3d38 --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_ltdc.h @@ -0,0 +1,38 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_ltdc.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_COMPAT_STM32LTDC_H +#define __ARCH_ARM_SRC_COMMON_COMPAT_STM32LTDC_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#if defined(CONFIG_STM32_HAVE_IP_LTDC_M3M4_V1) +# include "stm32_ltdc_m3m4_v1.h" +#else +# error "Unsupported STM32 stm32_ltdc" +#endif + +#endif /* __ARCH_ARM_SRC_COMMON_COMPAT_STM32LTDC_H */ diff --git a/arch/arm/src/common/stm32/stm32_ltdc_m3m4_v1.c b/arch/arm/src/common/stm32/stm32_ltdc_m3m4_v1.c new file mode 100644 index 0000000000000..59bc7fc4484ee --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_ltdc_m3m4_v1.c @@ -0,0 +1,3139 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_ltdc_m3m4_v1.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* References: + * STM32F429 Technical Reference Manual and Data Sheet + */ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include + +#include "arm_internal.h" +#include "stm32.h" +#include "hardware/stm32_ltdc.h" +#include "hardware/stm32_dma2d.h" +#include "stm32_ltdc_m3m4_v1.h" +#include "stm32_dma2d_m3m4_v1.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Register definition ******************************************************/ + +#ifndef BOARD_LTDC_WIDTH +# error BOARD_LTDC_WIDTH must be defined in the board.h header file +#endif + +#ifndef BOARD_LTDC_HEIGHT +# error BOARD_LTDC_HEIGHT must be defined in the board.h header file +#endif + +#define STM32_LTDC_HEIGHT BOARD_LTDC_HEIGHT +#define STM32_LTDC_WIDTH BOARD_LTDC_WIDTH + +/* Configure LTDC register */ + +/* LTDC_LxWHPCR register */ + +#define STM32_LTDC_LXWHPCR_WHSTPOS (BOARD_LTDC_HSYNC + BOARD_LTDC_HBP - 1) +#define STM32_LTDC_LxWHPCR_WHSPPOS (BOARD_LTDC_HSYNC + BOARD_LTDC_HBP + \ + STM32_LTDC_WIDTH - 1) + +/* LTDC_LxWVPCR register */ + +#define STM32_LTDC_LXWVPCR_WVSTPOS (BOARD_LTDC_VSYNC + BOARD_LTDC_VBP - 1) +#define STM32_LTDC_LxWVPCR_WVSPPOS (BOARD_LTDC_VSYNC + BOARD_LTDC_VBP + \ + STM32_LTDC_HEIGHT - 1) + +/* LTDC_SSCR register */ + +#define STM32_LTDC_SSCR_VSH LTDC_SSCR_VSH(BOARD_LTDC_VSYNC - 1) +#define STM32_LTDC_SSCR_HSW LTDC_SSCR_HSW(BOARD_LTDC_HSYNC - 1) + +/* LTDC_BPCR register */ + +#define STM32_LTDC_BPCR_AVBP LTDC_BPCR_AVBP(STM32_LTDC_LXWVPCR_WVSTPOS) +#define STM32_LTDC_BPCR_AHBP LTDC_BPCR_AHBP(STM32_LTDC_LXWHPCR_WHSTPOS) + +/* LTDC_AWCR register */ + +#define STM32_LTDC_AWCR_AAH LTDC_AWCR_AAH(STM32_LTDC_LxWVPCR_WVSPPOS) +#define STM32_LTDC_AWCR_AAW LTDC_AWCR_AAW(STM32_LTDC_LxWHPCR_WHSPPOS) + +/* LTDC_TWCR register */ + +#define STM32_LTDC_TWCR_TOTALH LTDC_TWCR_TOTALH(BOARD_LTDC_VSYNC + \ + BOARD_LTDC_VBP + \ + STM32_LTDC_HEIGHT + BOARD_LTDC_VFP - 1) +#define STM32_LTDC_TWCR_TOTALW LTDC_TWCR_TOTALW(BOARD_LTDC_HSYNC + \ + BOARD_LTDC_HBP + \ + STM32_LTDC_WIDTH + BOARD_LTDC_HFP - 1) + +/* Global GCR register */ + +/* Synchronisation and Polarity */ + +#define STM32_LTDC_GCR_PCPOL BOARD_LTDC_GCR_PCPOL +#define STM32_LTDC_GCR_DEPOL BOARD_LTDC_GCR_DEPOL +#define STM32_LTDC_GCR_VSPOL BOARD_LTDC_GCR_VSPOL +#define STM32_LTDC_GCR_HSPOL BOARD_LTDC_GCR_HSPOL + +/* Dither */ + +#define STM32_LTDC_GCR_DEN BOARD_LTDC_GCR_DEN +#define STM32_LTDC_GCR_DBW LTDC_GCR_GBW(BOARD_LTDC_GCR_DBW) +#define STM32_LTDC_GCR_DGW LTDC_GCR_DGW(BOARD_LTDC_GCR_DGW) +#define STN32_LTDC_GCR_DRW LTDC_GCR_DBW(BOARD_LTDC_GCR_DRW) + +/* LIPCR register */ + +#define STM32_LTDC_LIPCR_LIPOS LTDC_LIPCR_LIPOS(STM32_LTDC_TWCR_TOTALW) + +/* Configuration ************************************************************/ + +#ifndef CONFIG_STM32_LTDC_DEFBACKLIGHT +# define CONFIG_STM32_LTDC_DEFBACKLIGHT 0xf0 +#endif +#define STM32_LTDC_BACKLIGHT_OFF 0x00 + +/* Color/video formats */ + +/* Layer 1 format */ + +#if defined(CONFIG_STM32_LTDC_L1_L8) +# define STM32_LTDC_L1_BPP 8 +# define STM32_LTDC_L1_COLOR_FMT FB_FMT_RGB8 +# define STM32_LTDC_L1PFCR_PF LTDC_LXPFCR_PF(LTDC_PF_L8) +# define STM32_LTDC_L1_DMA2D_PF DMA2D_PF_L8 +# define STM32_LTDC_L1CMAP +#elif defined(CONFIG_STM32_LTDC_L1_RGB565) +# define STM32_LTDC_L1_BPP 16 +# define STM32_LTDC_L1_COLOR_FMT FB_FMT_RGB16_565 +# define STM32_LTDC_L1PFCR_PF LTDC_LXPFCR_PF(LTDC_PF_RGB565) +# define STM32_LTDC_L1_DMA2D_PF DMA2D_PF_RGB565 +#elif defined(CONFIG_STM32_LTDC_L1_RGB888) +# define STM32_LTDC_L1_BPP 24 +# define STM32_LTDC_L1_COLOR_FMT FB_FMT_RGB24 +# define STM32_LTDC_L1PFCR_PF LTDC_LXPFCR_PF(LTDC_PF_RGB888) +# define STM32_LTDC_L1_DMA2D_PF DMA2D_PF_RGB888 +#elif defined(CONFIG_STM32_LTDC_L1_ARGB8888) +# define STM32_LTDC_L1_BPP 32 +# define STM32_LTDC_L1_COLOR_FMT FB_FMT_RGB32 +# define STM32_LTDC_L1PFCR_PF LTDC_LXPFCR_PF(LTDC_PF_ARGB8888) +# define STM32_LTDC_L1_DMA2D_PF DMA2D_PF_ARGB8888 +#else +# error "LTDC pixel format not supported" +#endif + +/* Layer 2 format */ + +#ifdef CONFIG_STM32_LTDC_L2 +# if defined(CONFIG_STM32_LTDC_L2_L8) +# define STM32_LTDC_L2_BPP 8 +# define STM32_LTDC_L2_COLOR_FMT FB_FMT_RGB8 +# define STM32_LTDC_L2PFCR_PF LTDC_LXPFCR_PF(LTDC_PF_L8) +# define STM32_LTDC_L2_DMA2D_PF DMA2D_PF_L8 +# define STM32_LTDC_L2CMAP +# elif defined(CONFIG_STM32_LTDC_L2_RGB565) +# define STM32_LTDC_L2_BPP 16 +# define STM32_LTDC_L2_COLOR_FMT FB_FMT_RGB16_565 +# define STM32_LTDC_L2PFCR_PF LTDC_LXPFCR_PF(LTDC_PF_RGB565) +# define STM32_LTDC_L2_DMA2D_PF DMA2D_PF_RGB565 +# elif defined(CONFIG_STM32_LTDC_L2_RGB888) +# define STM32_LTDC_L2_BPP 24 +# define STM32_LTDC_L2_COLOR_FMT FB_FMT_RGB24 +# define STM32_LTDC_L2PFCR_PF LTDC_LXPFCR_PF(LTDC_PF_RGB888) +# define STM32_LTDC_L2_DMA2D_PF DMA2D_PF_RGB888 +# elif defined(CONFIG_STM32_LTDC_L2_ARGB8888) +# define STM32_LTDC_L2_BPP 32 +# define STM32_LTDC_L2_COLOR_FMT FB_FMT_RGB32 +# define STM32_LTDC_L2PFCR_PF LTDC_LXPFCR_PF(LTDC_PF_ARGB8888) +# define STM32_LTDC_L2_DMA2D_PF DMA2D_PF_ARGB8888 +# else +# error "LTDC pixel format not supported" +# endif +#endif /* CONFIG_STM32_LTDC_L2 */ + +/* Framebuffer sizes in bytes */ + +#if STM32_LTDC_L1_BPP == 8 +# define STM32_LTDC_L1_STRIDE (STM32_LTDC_WIDTH) +#elif STM32_LTDC_L1_BPP == 16 +# define STM32_LTDC_L1_STRIDE ((STM32_LTDC_WIDTH * 16 + 7) / 8) +#elif STM32_LTDC_L1_BPP == 24 +# define STM32_LTDC_L1_STRIDE ((STM32_LTDC_WIDTH * 24 + 7) / 8) +#elif STM32_LTDC_L1_BPP == 32 +# define STM32_LTDC_L1_STRIDE ((STM32_LTDC_WIDTH * 32 + 7) / 8) +#else +# error Undefined or unrecognized base resolution +#endif + +/* LTDC only supports 8 bit per pixel overall */ + +#define STM32_LTDC_LX_BYPP(n) ((n) / 8) + +#define STM32_LTDC_L1_FBSIZE (STM32_LTDC_L1_STRIDE * STM32_LTDC_HEIGHT) + +#ifdef CONFIG_STM32_LTDC_L2 +# ifndef CONFIG_STM32_LTDC_L2_WIDTH +# define CONFIG_STM32_LTDC_L2_WIDTH STM32_LTDC_WIDTH +# endif + +# if CONFIG_STM32_LTDC_L2_WIDTH > STM32_LTDC_WIDTH +# error Width of Layer 2 exceeds the width of the display +# endif + +# ifndef CONFIG_STM32_LTDC_L2_HEIGHT +# define CONFIG_STM32_LTDC_L2_HEIGHT STM32_LTDC_HEIGHT +# endif + +# if CONFIG_STM32_LTDC_L2_HEIGHT > STM32_LTDC_HEIGHT +# error Height of Layer 2 exceeds the height of the display +# endif + +# if STM32_LTDC_L2_BPP == 8 +# define STM32_LTDC_L2_STRIDE (CONFIG_STM32_LTDC_L2_WIDTH) +# elif STM32_LTDC_L2_BPP == 16 +# define STM32_LTDC_L2_STRIDE ((CONFIG_STM32_LTDC_L2_WIDTH * 16 + 7) / 8) +# elif STM32_LTDC_L2_BPP == 24 +# define STM32_LTDC_L2_STRIDE ((CONFIG_STM32_LTDC_L2_WIDTH * 24 + 7) / 8) +# elif STM32_LTDC_L2_BPP == 32 +# define STM32_LTDC_L2_STRIDE ((CONFIG_STM32_LTDC_L2_WIDTH * 32 + 7) / 8) +# else +# error Undefined or unrecognized base resolution +# endif + +# define STM32_LTDC_L2_FBSIZE (STM32_LTDC_L2_STRIDE * \ + CONFIG_STM32_LTDC_L2_HEIGHT) + +#else +# define STM32_LTDC_L2_FBSIZE (0) +#endif + +/* Total memory used for framebuffers */ + +#define STM32_LTDC_TOTAL_FBSIZE (STM32_LTDC_L1_FBSIZE + \ + STM32_LTDC_L2_FBSIZE) + +/* Debug option */ + +#ifdef CONFIG_STM32_LTDC_REGDEBUG +# define regerr lcderr +# define reginfo lcdinfo +#else +# define regerr(x...) +# define reginfo(x...) +#endif + +/* Preallocated LTDC framebuffers */ + +/* Position the framebuffer memory in the center of the memory set aside. We + * will use any skirts before or after the framebuffer memory as a guard + * against wild framebuffer writes. + */ + +#define STM32_LTDC_BUFFER_SIZE CONFIG_STM32_LTDC_FB_SIZE +#define STM32_LTDC_BUFFER_FREE (STM32_LTDC_BUFFER_SIZE - \ + STM32_LTDC_TOTAL_FBSIZE) +#define STM32_LTDC_BUFFER_START (CONFIG_STM32_LTDC_FB_BASE + \ + STM32_LTDC_BUFFER_FREE/2) + +#if STM32_LTDC_BUFFER_FREE < 0 +# error "STM32_LTDC_BUFFER_SIZE not large enough for frame buffers" +#endif + +/* Layer frame buffer */ + +#define STM32_LTDC_BUFFER_L1 STM32_LTDC_BUFFER_START +#define STM32_LTDC_ENDBUF_L1 (STM32_LTDC_BUFFER_L1 + \ + STM32_LTDC_L1_FBSIZE) + +#ifdef CONFIG_STM32_LTDC_L2 +# define STM32_LTDC_BUFFER_L2 STM32_LTDC_ENDBUF_L1 +# define STM32_LTDC_ENDBUF_L2 (STM32_LTDC_BUFFER_L2 + \ + STM32_LTDC_L2_FBSIZE) +#else +# define STM32_LTDC_ENDBUF_L2 STM32_LTDC_ENDBUF_L1 +#endif + +/* LTDC layer */ + +#ifdef CONFIG_STM32_LTDC_L2 +# define LTDC_NLAYERS 2 +#else +# define LTDC_NLAYERS 1 +#endif + +/* DMA2D layer */ + +#ifdef CONFIG_STM32_DMA2D +# define DMA2D_NLAYERS CONFIG_STM32_DMA2D_NLAYERS +# if DMA2D_NLAYERS < 1 +# error "DMA2D must at least support 1 overlay" +# endif + +#define STM32_DMA2D_WIDTH CONFIG_STM32_DMA2D_LAYER_PPLINE + +# if defined(CONFIG_STM32_DMA2D_L8) +# define STM32_DMA2D_STRIDE (STM32_DMA2D_WIDTH) +# define STM32_DMA2D_BPP 8 +# define STM32_DMA2D_COLOR_FMT DMA2D_PF_L8 +# elif defined(CONFIG_STM32_DMA2D_RGB565) +# define STM32_DMA2D_STRIDE ((STM32_DMA2D_WIDTH * 16 + 7) / 8) +# define STM32_DMA2D_BPP 16 +# define STM32_DMA2D_COLOR_FMT DMA2D_PF_RGB565 +# elif defined(CONFIG_STM32_DMA2D_RGB888) +# define STM32_DMA2D_STRIDE ((STM32_DMA2D_WIDTH * 24 + 7) / 8) +# define STM32_DMA2D_BPP 24 +# define STM32_DMA2D_COLOR_FMT DMA2D_PF_RGB888 +# elif defined(CONFIG_STM32_DMA2D_ARGB8888) +# define STM32_DMA2D_STRIDE ((STM32_DMA2D_WIDTH * 32 + 7) / 8) +# define STM32_DMA2D_BPP 32 +# define STM32_DMA2D_COLOR_FMT DMA2D_PF_ARGB8888 +# else +# error "DMA2D pixel format not supported" +# endif + +# ifdef CONFIG_STM32_DMA2D_LAYER_SHARED +# define STM32_DMA2D_FBSIZE CONFIG_STM32_DMA2D_FB_SIZE +# define STM32_DMA2D_LAYER_SIZE 0 +# else +# define STM32_DMA2D_FBSIZE CONFIG_STM32_DMA2D_FB_SIZE / DMA2D_NLAYERS +# define STM32_DMA2D_LAYER_SIZE STM32_DMA2D_FBSIZE +# if STM32_DMA2D_FBSIZE * DMA2D_NLAYERS > CONFIG_STM32_DMA2D_FB_SIZE +# error "DMA2D framebuffer size to small for configured number of overlays" +# endif +# endif /* CONFIG_STM32_DMA2D_LAYER_SHARED */ + +# define STM32_DMA2D_HEIGHT STM32_DMA2D_FBSIZE / STM32_DMA2D_STRIDE + +# define STM32_DMA2D_BUFFER_START CONFIG_STM32_DMA2D_FB_BASE +#else +# define DMA2D_NLAYERS 0 +#endif /* CONFIG_STM32_DMA2D */ + +#define LTDC_NOVERLAYS LTDC_NLAYERS + DMA2D_NLAYERS + +/* Dithering */ + +#ifndef CONFIG_STM32_LTDC_DITHER_RED +# define STM32_LTDC_DITHER_RED 0 +#else +# define STM32_LTDC_DITHER_RED CONFIG_STM32_LTDC_DITHER_RED +#endif +#ifndef CONFIG_STM32_LTDC_DITHER_GREEN +# define STM32_LTDC_DITHER_GREEN 0 +#else +# define STM32_LTDC_DITHER_GREEN CONFIG_STM32_LTDC_DITHER_GREEN +#endif +#ifndef CONFIG_STM32_LTDC_DITHER_BLUE +# define STM32_LTDC_DITHER_BLUE 0 +#else +# define STM32_LTDC_DITHER_BLUE CONFIG_STM32_LTDC_DITHER_BLUE +#endif + +/* Background color */ + +#ifndef CONFIG_STM32_LTDC_BACKCOLOR +# define STM32_LTDC_BACKCOLOR 0 +#else +# define STM32_LTDC_BACKCOLOR CONFIG_STM32_LTDC_BACKCOLOR +#endif + +/* Layer default color */ + +#ifdef CONFIG_STM32_LTDC_L1_COLOR +# define STM32_LTDC_L1_COLOR CONFIG_STM32_LTDC_L1_COLOR +#else +# define STM32_LTDC_L1_COLOR 0x000000 +#endif + +#ifdef CONFIG_STM32_LTDC_L2 +# ifdef CONFIG_STM32_LTDC_L2_COLOR +# define STM32_LTDC_L2_COLOR CONFIG_STM32_LTDC_L2_COLOR +# else +# define STM32_LTDC_L2_COLOR 0x000000 +# endif +#endif + +/* Internal operation flags */ + +#define LTDC_LAYER_SETAREA (1 << 0) /* Change visible area */ +#define LTDC_LAYER_SETALPHAVALUE (1 << 1) /* Change constant alpha value */ +#define LTDC_LAYER_SETBLENDMODE (1 << 2) /* Change blendmode */ +#define LTDC_LAYER_SETCOLORKEY (1 << 3) /* Change color key */ +#define LTDC_LAYER_ENABLECOLORKEY (1 << 4) /* Enable colorkey */ +#define LTDC_LAYER_SETCOLOR (1 << 5) /* Change default color */ +#define LTDC_LAYER_SETENABLE (1 << 6) /* Change enabled state */ +#define LTDC_LAYER_ENABLE (1 << 7) /* Enable the layer */ + +/* Layer initializing state */ + +#define LTDC_LAYER_INIT LTDC_LAYER_SETAREA | \ + LTDC_LAYER_SETALPHAVALUE | \ + LTDC_LAYER_SETBLENDMODE | \ + LTDC_LAYER_SETCOLORKEY | \ + LTDC_LAYER_SETCOLOR | \ + LTDC_LAYER_SETENABLE | \ + LTDC_LAYER_ENABLE + +/* Blendfactor reset values for flip operation */ + +#define STM32_LTDC_BF1_RESET 6 +#define STM32_LTDC_BF2_RESET 7 + +/* Check pixel format support by DMA2D driver */ + +#ifdef CONFIG_STM32_DMA2D +# if defined(CONFIG_STM32_LTDC_L1_L8) || \ + defined(CONFIG_STM32_LTDC_L2_L8) +# if !defined(CONFIG_STM32_DMA2D_L8) +# error "DMA2D must support FB_FMT_RGB8 pixel format" +# endif +# endif +# if defined(CONFIG_STM32_LTDC_L1_RGB565) || \ + defined(CONFIG_STM32_LTDC_L2_RGB565) +# if !defined(CONFIG_STM32_DMA2D_RGB565) +# error "DMA2D must support FB_FMT_RGB16_565 pixel format" +# endif +# endif +# if defined(CONFIG_STM32_LTDC_L1_RGB888) || \ + defined(CONFIG_STM32_LTDC_L2_RGB888) +# if !defined(CONFIG_STM32_DMA2D_RGB888) +# error "DMA2D must support FB_FMT_RGB24 pixel format" +# endif +# endif +# if defined(CONFIG_STM32_LTDC_L1_ARGB8888) || \ + defined(CONFIG_STM32_LTDC_L2_ARGB8888) +# if !defined(CONFIG_STM32_DMA2D_ARGB8888) +# error "DMA2D must support FB_FMT_RGB32 pixel format" +# endif +# endif +#endif + +/* Calculate the size of the layers clut table */ + +#ifdef CONFIG_STM32_FB_CMAP +# if defined(CONFIG_STM32_DMA2D) && !defined(CONFIG_STM32_DMA2D_L8) +# error "DMA2D must also support L8 CLUT pixel format if supported by LTDC" +# endif +# ifdef STM32_LTDC_L1CMAP +# ifdef CONFIG_STM32_FB_TRANSPARENCY +# define STM32_LAYER_CLUT_SIZE STM32_LTDC_NCLUT * sizeof(uint32_t) +# else +# define STM32_LAYER_CLUT_SIZE STM32_LTDC_NCLUT * 3 * sizeof(uint8_t) +# endif +# endif +# ifdef STM32_LTDC_L2CMAP +# undef STM32_LAYER_CLUT_SIZE +# ifdef CONFIG_STM32_FB_TRANSPARENCY +# define STM32_LAYER_CLUT_SIZE STM32_LTDC_NCLUT * sizeof(uint32_t) * 2 +# else +# define STM32_LAYER_CLUT_SIZE STM32_LTDC_NCLUT * 3 * sizeof(uint8_t) * 2 +# endif +# endif +#endif + +#ifndef CONFIG_STM32_FB_CMAP +# if defined(STM32_LTDC_L1CMAP) || defined(STM32_LTDC_L2CMAP) +# undef STM32_LTDC_L1CMAP +# undef STM32_LTDC_L2CMAP +# error "Enable cmap to support the configured layer format!" +# endif +#endif + +/* Layer clut rgb value positioning */ + +#define LTDC_L1CLUT_REDOFFSET 0 +#define LTDC_L1CLUT_GREENOFFSET 256 +#define LTDC_L1CLUT_BLUEOFFSET 512 +#define LTDC_L2CLUT_REDOFFSET 768 +#define LTDC_L2CLUT_GREENOFFSET 1024 +#define LTDC_L2CLUT_BLUEOFFSET 1280 + +/* Layer argb clut register position */ + +#define LTDC_CLUT_ADD(n) ((uint32_t)(n) << 24) +#define LTDC_CLUT_ALPHA(n) LTDC_CLUT_ADD(n) +#define LTDC_CLUT_RED(n) ((uint32_t)(n) << 16) +#define LTDC_CLUT_GREEN(n) ((uint32_t)(n) << 8) +#define LTDC_CLUT_BLUE(n) ((uint32_t)(n) << 0) +#define LTDC_CLUT_RGB888_MASK 0xffffff + +/* Layer argb cmap conversion */ + +#define LTDC_CMAP_ALPHA(n) ((uint32_t)(n) >> 24) +#define LTDC_CMAP_RED(n) ((uint32_t)(n) >> 16) +#define LTDC_CMAP_GREEN(n) ((uint32_t)(n) >> 8) +#define LTDC_CMAP_BLUE(n) ((uint32_t)(n) >> 0) + +/* Hardware acceleration support */ + +/* Acceleration support for LTDC overlays */ + +#ifdef CONFIG_STM32_LTDC_L1_CHROMAKEYEN +# define STM32_LTDC_L1_CHROMAEN true +# define STM32_LTDC_L1_CHROMAKEY CONFIG_STM32_LTDC_L1_CHROMAKEY +# define LTDC_LTDC_ACCL_L1 FB_ACCL_TRANSP | FB_ACCL_CHROMA +#else +# define STM32_LTDC_L1_CHROMAEN false +# define STM32_LTDC_L1_CHROMAKEY 0 +# define LTDC_LTDC_ACCL_L1 FB_ACCL_TRANSP +#endif + +#ifdef CONFIG_STM32_LTDC_L2_CHROMAKEYEN +# define STM32_LTDC_L2_CHROMAEN true +# define STM32_LTDC_L2_CHROMAKEY CONFIG_STM32_LTDC_L2_CHROMAKEY +# define LTDC_LTDC_ACCL_L2 FB_ACCL_TRANSP | FB_ACCL_CHROMA +#else +# define STM32_LTDC_L2_CHROMAEN false +# define STM32_LTDC_L2_CHROMAKEY 0 +# define LTDC_LTDC_ACCL_L2 FB_ACCL_TRANSP +#endif + +#ifdef CONFIG_STM32_DMA2D +# ifdef CONFIG_FB_OVERLAY_BLIT +# ifdef CONFIG_STM32_FB_CMAP +# define LTDC_BLIT_ACCL FB_ACCL_BLIT +# else +# define LTDC_BLIT_ACCL FB_ACCL_BLIT | FB_ACCL_BLEND +# endif /* CONFIG_STM32_FB_CMAP */ +# else +# define LTDC_BLIT_ACCL 0 +# endif /* CONFIG_FB_OVERLAY_BLIT */ + +# ifdef CONFIG_STM32_FB_CMAP +# define LTDC_DMA2D_ACCL LTDC_BLIT_ACCL +# else +# define LTDC_DMA2D_ACCL FB_ACCL_COLOR | LTDC_BLIT_ACCL +# endif /* CONFIG_STM32_FB_CMAP */ +#else +# define LTDC_DMA2D_ACCL 0 +#endif /* CONFIG_STM32_DMA2D */ + +#define LTDC_L1_ACCL LTDC_LTDC_ACCL_L1 | LTDC_DMA2D_ACCL +#ifdef CONFIG_STM32_LTDC_L2 +# define LTDC_L2_ACCL LTDC_LTDC_ACCL_L2 | LTDC_DMA2D_ACCL +#endif + +/* Acceleration support for DMA2D overlays */ + +#ifdef CONFIG_STM32_FB_CMAP +# ifdef CONFIG_FB_OVERLAY_BLIT +# define DMA2D_ACCL FB_ACCL_BLIT | FB_ACCL_AREA +# else +# define DMA2D_ACCL FB_ACCL_AREA +# endif +#else +# ifdef CONFIG_FB_OVERLAY_BLIT +# define DMA2D_ACCL FB_ACCL_AREA | \ + FB_ACCL_TRANSP | \ + FB_ACCL_COLOR | \ + FB_ACCL_BLIT | \ + FB_ACCL_BLEND +# else +# define DMA2D_ACCL FB_ACCL_AREA | \ + FB_ACCL_TRANSP | \ + FB_ACCL_COLOR +# endif +#endif + +/* Color normalization */ + +#if defined(CONFIG_STM32_LTDC_L1_RGB565) +# define RGB888_R(x) (((((x) >> 11) & 0x1f) * 527 + 23) >> 6) +# define RGB888_G(x) (((((x) >> 5) & 0x3f) * 259 + 33) >> 6) +# define RGB888_B(x) ((((x) & 0x1f) * 527 + 23) >> 6) +# define ARGB8888(x) ((RGB888_R(x) << 16) | \ + (RGB888_G(x) << 8) | \ + RGB888_B(x)) +#else +# define ARGB8888(x) (x) +#endif + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/* This enumeration names each layer supported by the hardware */ + +enum stm32_layer_e +{ + LTDC_LAYER_L1 = 0, /* LCD Layer 1 */ + LTDC_LAYER_L2, /* LCD Layer 2 */ +}; + +/* LTDC General layer information */ + +struct stm32_ltdc_s +{ + int layerno; /* layer number */ + +#ifdef CONFIG_FB_OVERLAY + struct fb_overlayinfo_s oinfo; /* Overlay info */ +#endif + +#ifdef CONFIG_STM32_DMA2D + struct stm32_dma2d_overlay_s dma2dinfo; /* Overlay info for DMA2D */ +#endif + + mutex_t *lock; /* Layer exclusive access */ +}; + +/* This structure provides the overall state of the LTDC layer */ + +struct stm32_ltdcdev_s +{ + /* Framebuffer interface */ + + struct fb_vtable_s vtable; + + /* Framebuffer video information */ + + struct fb_videoinfo_s vinfo; + + /* Framebuffer plane information */ + + struct fb_planeinfo_s pinfo; + + /* Cmap information */ + +#ifdef CONFIG_STM32_FB_CMAP + struct fb_cmap_s cmap; +#endif + + /* Layer information */ + + struct stm32_ltdc_s layer[LTDC_NOVERLAYS]; + +#ifdef CONFIG_STM32_DMA2D + /* Interface to the dma2d controller */ + + struct dma2d_layer_s *dma2d; +#endif +}; + +/* Interrupt handling */ + +struct stm32_interrupt_s +{ + int irq; /* irq number */ + int error; /* Interrupt error */ + sem_t *sem; /* Semaphore for waiting for irq */ +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/* Overall LTDC helper */ + +static void stm32_ltdc_enable(bool enable); +static void stm32_ltdc_gpioconfig(void); +static void stm32_ltdc_periphconfig(void); +static void stm32_ltdc_bgcolor(uint32_t rgb); +static void stm32_ltdc_dither(bool enable, uint8_t red, + uint8_t green, uint8_t blue); +static int stm32_ltdcirq(int irq, void *context, void *arg); +static int stm32_ltdc_waitforirq(void); +static int stm32_ltdc_reload(uint8_t value, bool waitvblank); + +/* Helper for layer register configuration */ + +static void stm32_ltdc_lpixelformat(struct stm32_ltdc_s *layer); +static void stm32_ltdc_lframebuffer(struct stm32_ltdc_s *layer); +static void stm32_ltdc_lenable(struct stm32_ltdc_s *layer, bool enable); +static void stm32_ltdc_ldefaultcolor(struct stm32_ltdc_s *layer, + uint32_t rgb); +static void stm32_ltdc_ltransp(struct stm32_ltdc_s *layer, + uint8_t transp, + uint32_t mode); +static void stm32_ltdc_lchromakey(struct stm32_ltdc_s *layer, + uint32_t chromakey); +static void stm32_ltdc_lchromakeyenable(struct stm32_ltdc_s *layer, + bool enable); +static void stm32_ltdc_linit(uint8_t lid); + +#ifdef CONFIG_STM32_DMA2D +static void stm32_ltdc_dma2dlinit(void); + +# ifdef CONFIG_FB_OVERLAY_BLIT +static bool stm32_ltdc_lvalidate(const struct stm32_ltdc_s *layer, + const struct fb_area_s *area); +# endif +#endif + +#ifdef CONFIG_STM32_FB_CMAP +static void stm32_ltdc_lputclut(struct stm32_ltdc_s *layer, + const struct fb_cmap_s *cmap); +static void stm32_ltdc_lgetclut(struct stm32_ltdc_s *layer, + struct fb_cmap_s *cmap); +static void stm32_ltdc_lclutenable(struct stm32_ltdc_s *layer, + bool enable); +#endif + +static void stm32_ltdc_lclear(uint8_t overlayno); + +/* Framebuffer interface */ + +static int stm32_getvideoinfo(struct fb_vtable_s *vtable, + struct fb_videoinfo_s *vinfo); +static int stm32_getplaneinfo(struct fb_vtable_s *vtable, + int planeno, + struct fb_planeinfo_s *pinfo); + +/* The following is provided only if the video hardware supports RGB color + * mapping + */ + +#ifdef CONFIG_STM32_FB_CMAP +static int stm32_getcmap(struct fb_vtable_s *vtable, + struct fb_cmap_s *cmap); +static int stm32_putcmap(struct fb_vtable_s *vtable, + const struct fb_cmap_s *cmap); +#endif + +/* The following is provided only if the video hardware signals vertical + * synchronisation + */ + +#ifdef CONFIG_FB_SYNC +static int stm32_waitforvsync(struct fb_vtable_s *vtable); +#endif + +/* The following is provided only if the video hardware supports overlays */ + +#ifdef CONFIG_FB_OVERLAY +static int stm32_getoverlayinfo(struct fb_vtable_s *vtable, + int overlayno, + struct fb_overlayinfo_s *oinfo); +static int stm32_settransp(struct fb_vtable_s *vtable, + const struct fb_overlayinfo_s *oinfo); +static int stm32_setchromakey(struct fb_vtable_s *vtable, + const struct fb_overlayinfo_s *oinfo); +static int stm32_setcolor(struct fb_vtable_s *vtable, + const struct fb_overlayinfo_s *oinfo); +static int stm32_setblank(struct fb_vtable_s *vtable, + const struct fb_overlayinfo_s *oinfo); +static int stm32_setarea(struct fb_vtable_s *vtable, + const struct fb_overlayinfo_s *oinfo); + +/* The following is provided only if the video hardware supports blit and + * blend operation + */ + +# ifdef CONFIG_FB_OVERLAY_BLIT +static int stm32_blit(struct fb_vtable_s *vtable, + const struct fb_overlayblit_s *blit); +static int stm32_blend(struct fb_vtable_s *vtable, + const struct fb_overlayblend_s *blend); +# endif /* CONFIG_FB_OVERLAY_BLIT */ +#endif /* CONFIG_FB_OVERLAY */ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* PIO pin configurations */ + +static const uint32_t g_ltdcpins[] = +{ + GPIO_LTDC_R4, GPIO_LTDC_R5, GPIO_LTDC_R6, GPIO_LTDC_R7, + GPIO_LTDC_G4, GPIO_LTDC_G5, GPIO_LTDC_G6, GPIO_LTDC_G7, + GPIO_LTDC_B4, GPIO_LTDC_B5, GPIO_LTDC_B6, GPIO_LTDC_B7, +#if BOARD_LTDC_OUTPUT_BPP > 12 + GPIO_LTDC_R3, GPIO_LTDC_G2, GPIO_LTDC_G3, GPIO_LTDC_B3, +# if BOARD_LTDC_OUTPUT_BPP > 16 + GPIO_LTDC_R2, GPIO_LTDC_B2, +# if BOARD_LTDC_OUTPUT_BPP > 18 + GPIO_LTDC_R0, GPIO_LTDC_R1, GPIO_LTDC_G0, GPIO_LTDC_G1, + GPIO_LTDC_B0, GPIO_LTDC_B1, +# endif +# endif +#endif + GPIO_LTDC_VSYNC, GPIO_LTDC_HSYNC, GPIO_LTDC_DE, GPIO_LTDC_CLK +}; + +#define STM32_LTDC_NPINCONFIGS (sizeof(g_ltdcpins) / sizeof(uint32_t)) + +#ifdef CONFIG_STM32_FB_CMAP +/* The layers clut table entries */ + +static uint8_t g_redclut[STM32_LTDC_NCLUT]; +static uint8_t g_greenclut[STM32_LTDC_NCLUT]; +static uint8_t g_blueclut[STM32_LTDC_NCLUT]; +# ifdef CONFIG_STM32_FB_TRANSPARENCY +static uint8_t g_transpclut[STM32_LTDC_NCLUT]; +# endif +#endif /* CONFIG_STM32_FB_CMAP */ + +/* The LTDC mutex that enforces mutually exclusive access */ + +static mutex_t g_lock = NXMUTEX_INITIALIZER; + +/* The semaphore for interrupt handling */ + +static sem_t g_semirq = SEM_INITIALIZER(0); + +/* This structure provides irq handling */ + +static struct stm32_interrupt_s g_interrupt = +{ + .irq = STM32_IRQ_LTDCINT, + .error = OK, + .sem = &g_semirq +}; + +/* This structure provides the internal interface */ + +static struct stm32_ltdcdev_s g_vtable = +{ + .vtable = + { + .getvideoinfo = stm32_getvideoinfo, + .getplaneinfo = stm32_getplaneinfo +#ifdef CONFIG_FB_SYNC + , + .waitforvsync = stm32_waitforvsync +#endif + +#ifdef CONFIG_STM32_FB_CMAP + , + .getcmap = stm32_getcmap, + .putcmap = stm32_putcmap +#endif + +#ifdef CONFIG_FB_OVERLAY + , + .getoverlayinfo = stm32_getoverlayinfo, + .settransp = stm32_settransp, + .setchromakey = stm32_setchromakey, + .setcolor = stm32_setcolor, + .setblank = stm32_setblank, + .setarea = stm32_setarea +# ifdef CONFIG_FB_OVERLAY_BLIT + , + .blit = stm32_blit, + .blend = stm32_blend +# endif +#endif /* CONFIG_FB_OVERLAY */ + }, +#ifdef CONFIG_STM32_LTDC_L2 + .pinfo = + { + .fbmem = (uint8_t *)STM32_LTDC_BUFFER_L2, + .fblen = STM32_LTDC_L2_FBSIZE, + .stride = STM32_LTDC_L2_STRIDE, + .display = 0, + .bpp = STM32_LTDC_L2_BPP + }, + .vinfo = + { + .fmt = STM32_LTDC_L2_COLOR_FMT, + .xres = STM32_LTDC_WIDTH, + .yres = STM32_LTDC_HEIGHT, + .nplanes = 1, +# ifdef CONFIG_FB_OVERLAY + .noverlays = LTDC_NOVERLAYS +# endif + } +#else + .pinfo = + { + .fbmem = (uint8_t *)STM32_LTDC_BUFFER_L1, + .fblen = STM32_LTDC_L1_FBSIZE, + .stride = STM32_LTDC_L1_STRIDE, + .display = 0, + .bpp = STM32_LTDC_L1_BPP + }, + .vinfo = + { + .fmt = STM32_LTDC_L1_COLOR_FMT, + .xres = STM32_LTDC_WIDTH, + .yres = STM32_LTDC_HEIGHT, + .nplanes = 1, +# ifdef CONFIG_FB_OVERLAY + .noverlays = LTDC_NOVERLAYS +# endif + } +#endif /* CONFIG_STM32_LTDC_L2 */ + , +#ifdef CONFIG_STM32_FB_CMAP + .cmap = + { + .first = 0, + .len = STM32_LTDC_NCLUT, + .red = g_redclut, + .green = g_greenclut, + .blue = g_blueclut, +# ifdef CONFIG_STM32_FB_TRANSPARENCY + .transp = g_transpclut +# endif + } + , +#endif + .layer[LTDC_LAYER_L1] = + { + .layerno = LTDC_LAYER_L1, +#ifdef CONFIG_FB_OVERLAY + .oinfo = + { + .fbmem = (uint8_t *)STM32_LTDC_BUFFER_L1, + .fblen = STM32_LTDC_L1_FBSIZE, + .stride = STM32_LTDC_L1_STRIDE, + .overlay = LTDC_LAYER_L1, + .bpp = STM32_LTDC_L1_BPP, + .blank = 0, + .chromakey = 0, + .color = 0, + .transp = + { + .transp = 0xff, + .transp_mode = FB_CONST_ALPHA + }, + .sarea = + { + .x = 0, + .y = 0, + .w = STM32_LTDC_WIDTH, + .h = STM32_LTDC_HEIGHT + }, + .accl = LTDC_L1_ACCL + }, +#endif + +#ifdef CONFIG_STM32_DMA2D + .dma2dinfo = + { + .fmt = STM32_LTDC_L1_DMA2D_PF, + .transp_mode = STM32_DMA2D_PFCCR_AM_NONE, + .xres = STM32_LTDC_WIDTH, + .yres = STM32_LTDC_HEIGHT, + .oinfo = &g_vtable.layer[LTDC_LAYER_L1].oinfo + }, +#endif + .lock = &g_lock + } +#ifdef CONFIG_STM32_LTDC_L2 + , + .layer[LTDC_LAYER_L2] = + { + .layerno = LTDC_LAYER_L2, +#ifdef CONFIG_FB_OVERLAY + .oinfo = + { + .overlay = LTDC_LAYER_L2, + .fbmem = (uint8_t *)STM32_LTDC_BUFFER_L2, + .fblen = STM32_LTDC_L2_FBSIZE, + .stride = STM32_LTDC_L2_STRIDE, + .bpp = STM32_LTDC_L2_BPP, + .blank = 0, + .chromakey = 0, + .color = 0, + .transp = + { + .transp = 0xff, + .transp_mode = FB_CONST_ALPHA + }, + .sarea = + { + .x = 0, + .y = 0, + .w = STM32_LTDC_WIDTH, + .h = STM32_LTDC_HEIGHT + }, + .accl = LTDC_L2_ACCL + }, +#endif + +#ifdef CONFIG_STM32_DMA2D + .dma2dinfo = + { + .fmt = STM32_LTDC_L2_DMA2D_PF, + .transp_mode = STM32_DMA2D_PFCCR_AM_NONE, + .xres = STM32_LTDC_WIDTH, + .yres = STM32_LTDC_HEIGHT, + .oinfo = &g_vtable.layer[LTDC_LAYER_L2].oinfo + }, +#endif + .lock = &g_lock + } +#endif +}; + +/* Configuration lookup tables */ + +/* LTDC width */ + +static const uint32_t stm32_width_layer_t[LTDC_NLAYERS] = +{ + STM32_LTDC_WIDTH +#ifdef CONFIG_STM32_LTDC_L2 + , STM32_LTDC_WIDTH +#endif +}; + +/* LTDC height */ + +static const uint32_t stm32_height_layer_t[LTDC_NLAYERS] = +{ + STM32_LTDC_HEIGHT +#ifdef CONFIG_STM32_LTDC_L2 + , STM32_LTDC_HEIGHT +#endif +}; + +/* LTDC stride */ + +static const uint32_t stm32_stride_layer_t[LTDC_NLAYERS] = +{ + STM32_LTDC_L1_STRIDE +#ifdef CONFIG_STM32_LTDC_L2 + , STM32_LTDC_L2_STRIDE +#endif +}; + +/* LTDC bpp */ + +static const uint32_t stm32_bpp_layer_t[LTDC_NLAYERS] = +{ + STM32_LTDC_L1_BPP +#ifdef CONFIG_STM32_LTDC_L2 + , STM32_LTDC_L2_BPP +#endif +}; + +/* LTDC framebuffer len */ + +static const uint32_t stm32_fblen_layer_t[LTDC_NLAYERS] = +{ + STM32_LTDC_L1_FBSIZE +#ifdef CONFIG_STM32_LTDC_L2 + , STM32_LTDC_L2_FBSIZE +#endif +}; + +/* LTDC framebuffer */ + +static const uint32_t stm32_fbmem_layer_t[LTDC_NLAYERS] = +{ + STM32_LTDC_BUFFER_L1 +#ifdef CONFIG_STM32_LTDC_L2 + , STM32_LTDC_BUFFER_L2 +#endif +}; + +/* LTDC default color lookup table */ + +static const uint32_t stm32_defaultcolor_layer_t[LTDC_NLAYERS] = +{ + STM32_LTDC_L1_COLOR +#ifdef CONFIG_STM32_LTDC_L2 + , STM32_LTDC_L2_COLOR +#endif +}; + +/* LTDC default chromakey */ + +static const uint32_t stm32_chromakey_layer_t[LTDC_NLAYERS] = +{ + STM32_LTDC_L1_CHROMAKEY +#ifdef CONFIG_STM32_LTDC_L2 + , STM32_LTDC_L2_CHROMAKEY +#endif +}; + +/* LTDC chromakey enabled state */ + +static const bool stm32_chromakeyen_layer_t[LTDC_NLAYERS] = +{ + STM32_LTDC_L1_CHROMAEN +#ifdef CONFIG_STM32_LTDC_L2 + , STM32_LTDC_L2_CHROMAEN +#endif +}; + +/* LTDC pixel format lookup table */ + +static const uint32_t stm32_fmt_layer_t[LTDC_NLAYERS] = +{ + STM32_LTDC_L1PFCR_PF +#ifdef CONFIG_STM32_LTDC_L2 + , STM32_LTDC_L2PFCR_PF +#endif +}; + +/* Register lookup tables */ + +/* LTDC_LxCR */ + +static const uintptr_t stm32_cr_layer_t[LTDC_NLAYERS] = +{ + STM32_LTDC_L1CR +#ifdef CONFIG_STM32_LTDC_L2 + , STM32_LTDC_L2CR +#endif +}; + +/* LTDC_LxWHPCR */ + +static const uintptr_t stm32_whpcr_layer_t[LTDC_NLAYERS] = +{ + STM32_LTDC_L1WHPCR +#ifdef CONFIG_STM32_LTDC_L2 + , STM32_LTDC_L2WHPCR +#endif +}; + +/* LTDC_LxWVPCR */ + +static const uintptr_t stm32_wvpcr_layer_t[LTDC_NLAYERS] = +{ + STM32_LTDC_L1WVPCR +#ifdef CONFIG_STM32_LTDC_L2 + , STM32_LTDC_L2WVPCR +#endif +}; + +/* LTDC_LxPFCR */ + +static const uintptr_t stm32_pfcr_layer_t[LTDC_NLAYERS] = +{ + STM32_LTDC_L1PFCR +#ifdef CONFIG_STM32_LTDC_L2 + , STM32_LTDC_L2PFCR +#endif +}; + +/* LTDC_LxDCCR */ + +static const uintptr_t stm32_dccr_layer_t[LTDC_NLAYERS] = +{ + STM32_LTDC_L1DCCR +#ifdef CONFIG_STM32_LTDC_L2 + , STM32_LTDC_L2DCCR +#endif +}; + +/* LTDC_LxCKCR */ + +static const uintptr_t stm32_ckcr_layer_t[LTDC_NLAYERS] = +{ + STM32_LTDC_L1CKCR +#ifdef CONFIG_STM32_LTDC_L2 + , STM32_LTDC_L2CKCR +#endif +}; + +/* LTDC_LxCACR */ + +static const uintptr_t stm32_cacr_layer_t[LTDC_NLAYERS] = +{ + STM32_LTDC_L1CACR +#ifdef CONFIG_STM32_LTDC_L2 + , STM32_LTDC_L2CACR +#endif +}; + +/* LTDC_LxBFCR */ + +static const uintptr_t stm32_bfcr_layer_t[LTDC_NLAYERS] = +{ + STM32_LTDC_L1BFCR +#ifdef CONFIG_STM32_LTDC_L2 + , STM32_LTDC_L2BFCR +#endif +}; + +/* LTDC_LxCFBAR */ + +static const uintptr_t stm32_cfbar_layer_t[LTDC_NLAYERS] = +{ + STM32_LTDC_L1CFBAR +#ifdef CONFIG_STM32_LTDC_L2 + , STM32_LTDC_L2CFBAR +#endif +}; + +/* LTDC_LxCFBLR */ + +static const uintptr_t stm32_cfblr_layer_t[LTDC_NLAYERS] = +{ + STM32_LTDC_L1CFBLR +#ifdef CONFIG_STM32_LTDC_L2 + , STM32_LTDC_L2CFBLR +#endif +}; + +/* LTDC_LxCFBLNR */ + +static const uintptr_t stm32_cfblnr_layer_t[LTDC_NLAYERS] = +{ + STM32_LTDC_L1CFBLNR +#ifdef CONFIG_STM32_LTDC_L2 + , STM32_LTDC_L2CFBLNR +#endif +}; + +/* LTDC_LxCLUTWR */ + +#ifdef CONFIG_STM32_FB_CMAP +static const uintptr_t stm32_clutwr_layer_t[LTDC_NLAYERS] = +{ + STM32_LTDC_L1CLUTWR +# ifdef CONFIG_STM32_LTDC_L2 + , STM32_LTDC_L2CLUTWR +# endif +}; +#endif /* CONFIG_STM32_FB_CMAP */ + +/* The initialized state of the driver */ + +static bool g_initialized; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_ltdc_gpioconfig + * + * Description: + * Configure GPIO pins for use with the LTDC + * + ****************************************************************************/ + +static void stm32_ltdc_gpioconfig(void) +{ + int i; + + lcdinfo("Configuring pins\n"); + + /* Configure each pin */ + + for (i = 0; i < STM32_LTDC_NPINCONFIGS; i++) + { + reginfo("set gpio%d = %08" PRIx32 "\n", i, g_ltdcpins[i]); + stm32_configgpio(g_ltdcpins[i]); + } +} + +/**************************************************************************** + * Name: stm32_ltdc_periphconfig + * + * Description: + * Configures the synchronous timings + * Configures the synchronous signals and clock polarity + * + ****************************************************************************/ + +static void stm32_ltdc_periphconfig(void) +{ + uint32_t regval; + + /* Configure GPIO's */ + + stm32_ltdc_gpioconfig(); + + /* Configure APB2 LTDC clock external */ + + reginfo("configured RCC_APB2ENR=%08" PRIx32 "\n", + getreg32(STM32_RCC_APB2ENR)); + + /* Configure the SAI PLL external to provide the LCD_CLK */ + + reginfo("configured RCC_PLLSAI=%08" PRIx32 "\n", + getreg32(STM32_RCC_PLLSAICFGR)); + + /* Configure dedicated clock external */ + + reginfo("configured RCC_DCKCFGR=%08" PRIx32 "\n", + getreg32(STM32_RCC_DCKCFGR)); + + /* Configure LTDC_SSCR */ + + regval = (STM32_LTDC_SSCR_VSH | STM32_LTDC_SSCR_HSW); + reginfo("set LTDC_SSCR=%08" PRIx32 "\n", regval); + putreg32(regval, STM32_LTDC_SSCR); + reginfo("configured LTDC_SSCR=%08" PRIx32 "\n", getreg32(STM32_LTDC_SSCR)); + + /* Configure LTDC_BPCR */ + + regval = (STM32_LTDC_BPCR_AVBP | STM32_LTDC_BPCR_AHBP); + reginfo("set LTDC_BPCR=%08" PRIx32 "\n", regval); + putreg32(regval, STM32_LTDC_BPCR); + reginfo("configured LTDC_BPCR=%08" PRIx32 "\n", getreg32(STM32_LTDC_BPCR)); + + /* Configure LTDC_AWCR */ + + regval = (STM32_LTDC_AWCR_AAH | STM32_LTDC_AWCR_AAW); + reginfo("set LTDC_AWCR=%08" PRIx32 "\n", regval); + putreg32(regval, STM32_LTDC_AWCR); + reginfo("configured LTDC_AWCR=%08" PRIx32 "\n", getreg32(STM32_LTDC_AWCR)); + + /* Configure LTDC_TWCR */ + + regval = (STM32_LTDC_TWCR_TOTALH | STM32_LTDC_TWCR_TOTALW); + reginfo("set LTDC_TWCR=%08" PRIx32 "\n", regval); + putreg32(regval, STM32_LTDC_TWCR); + reginfo("configured LTDC_TWCR=%08" PRIx32 "\n", getreg32(STM32_LTDC_TWCR)); + + /* Configure LTDC_GCR */ + + regval = getreg32(STM32_LTDC_GCR); + regval &= ~(LTDC_GCR_PCPOL | LTDC_GCR_DEPOL | LTDC_GCR_VSPOL | + LTDC_GCR_HSPOL); + regval |= (STM32_LTDC_GCR_PCPOL | STM32_LTDC_GCR_DEPOL | + STM32_LTDC_GCR_VSPOL | STM32_LTDC_GCR_HSPOL); + + reginfo("set LTDC_GCR=%08" PRIx32 "\n", regval); + putreg32(regval, STM32_LTDC_GCR); + reginfo("configured LTDC_GCR=%08" PRIx32 "\n", getreg32(STM32_LTDC_GCR)); +} + +/**************************************************************************** + * Name: stm32_ltdc_ldefaultcolor + * + * Description: + * Configures layer default color. + * + * Input Parameters: + * layer - Reference to the layer control structure + * rgb - RGB888 background color + * + ****************************************************************************/ + +static void stm32_ltdc_ldefaultcolor(struct stm32_ltdc_s *layer, + uint32_t rgb) +{ + DEBUGASSERT(layer->layerno < LTDC_NLAYERS); + reginfo("set LTDC_L%dDCCR=%08" PRIx32 "\n", layer->layerno + 1, rgb); + + putreg32(rgb, stm32_dccr_layer_t[layer->layerno]); + + /* Reload shadow register */ + + stm32_ltdc_reload(LTDC_SRCR_IMR, false); + + reginfo("configured LTDC_L%dDCCR=%08" PRIx32 "\n", layer->layerno + 1, + getreg32(STM32_LTDC_BCCR)); +} + +/**************************************************************************** + * Name: stm32_ltdc_bgcolor + * + * Description: + * Configures background color of the LCD controller. + * + * Input Parameters: + * rgb - RGB888 background color + * + ****************************************************************************/ + +static void stm32_ltdc_bgcolor(uint32_t rgb) +{ + reginfo("set LTDC_BCCR=%08" PRIx32 "\n", rgb); + putreg32(rgb, STM32_LTDC_BCCR); + reginfo("configured LTDC_BCCR=%08" PRIx32 "\n", getreg32(STM32_LTDC_BCCR)); +} + +/**************************************************************************** + * Name: stm32_ltdc_dither + * + * Description: + * Configures dither settings of the LCD controller. + * + * Input Parameters: + * enable - Enable dithering + * red - Red dither width + * green - Green dither width + * blue - Blue dither width + * + ****************************************************************************/ + +static void stm32_ltdc_dither(bool enable, uint8_t red, + uint8_t green, uint8_t blue) +{ + uint32_t regval; + + regval = getreg32(STM32_LTDC_GCR); + + if (enable == true) + { + regval |= LTDC_GCR_DEN; + } + else + { + regval &= ~LTDC_GCR_DEN; + } + + regval &= ~(LTDC_GCR_DBW_MASK | LTDC_GCR_DGW_MASK | LTDC_GCR_DRW_MASK); + regval |= (LTDC_GCR_DRW(red) | LTDC_GCR_DGW(green) | LTDC_GCR_DBW(blue)); + + reginfo("set LTDC_GCR=%08" PRIx32 "\n", regval); + putreg32(regval, STM32_LTDC_GCR); + reginfo("configured LTDC_GCR=%08" PRIx32 "\n", + getreg32(STM32_LTDC_GCR)); +} + +/**************************************************************************** + * Name: stm32_ltdc_linepos + * + * Description: + * Configures line position register + * + ****************************************************************************/ + +static void stm32_ltdc_linepos(void) +{ + /* Configure LTDC_LIPCR */ + + reginfo("set LTDC_LIPCR=%08x\n", STM32_LTDC_LIPCR_LIPOS); + putreg32(STM32_LTDC_LIPCR_LIPOS, STM32_LTDC_LIPCR); + reginfo("configured LTDC_LIPCR=%08" PRIx32 "\n", + getreg32(STM32_LTDC_LIPCR)); +} + +/**************************************************************************** + * Name: stm32_ltdc_irqctrl + * + * Description: + * Control interrupts generated by the ltdc controller + * + * Input Parameters: + * setirqs - set interrupt mask + * clrirqs - clear interrupt mask + * + ****************************************************************************/ + +static void stm32_ltdc_irqctrl(uint32_t setirqs, uint32_t clrirqs) +{ + uint32_t regval; + + regval = getreg32(STM32_LTDC_IER); + regval &= ~clrirqs; + regval |= setirqs; + reginfo("set LTDC_IER=%08" PRIx32 "\n", regval); + putreg32(regval, STM32_LTDC_IER); + reginfo("configured LTDC_IER=%08" PRIx32 "\n", getreg32(STM32_LTDC_IER)); +} + +/**************************************************************************** + * Name: stm32_ltdcirq + * + * Description: + * LTDC interrupt handler + * + ****************************************************************************/ + +static int stm32_ltdcirq(int irq, void *context, void *arg) +{ + int ret; + struct stm32_interrupt_s *priv = &g_interrupt; + uint32_t regval = getreg32(STM32_LTDC_ISR); + + reginfo("irq = %d, regval = %08" PRIx32 "\n", irq, regval); + + if (regval & LTDC_ISR_RRIF) + { + /* Register reload interrupt */ + + /* Clear the interrupt status register */ + + reginfo("Register reloaded\n"); + putreg32(LTDC_ICR_CRRIF, STM32_LTDC_ICR); + priv->error = OK; + } + else if (regval & LTDC_IER_LIE) + { + /* Line interrupt */ + + /* Clear the interrupt status register */ + + reginfo("Line interrupt\n"); + putreg32(LTDC_ICR_CLIF, STM32_LTDC_ICR); + priv->error = OK; + } + else if (regval & LTDC_IER_TERRIE) + { + /* Transfer error interrupt */ + + /* Clear the interrupt status register */ + + reginfo("Error transfer\n"); + putreg32(LTDC_ICR_CTERRIF, STM32_LTDC_ICR); + priv->error = -ECANCELED; + } + else if (regval & LTDC_IER_FUIE) + { + /* Fifo underrun error interrupt */ + + /* Clear the interrupt status register */ + + reginfo("Error fifo underrun\n"); + putreg32(LTDC_ICR_CFUIF, STM32_LTDC_ICR); + priv->error = -ECANCELED; + } + else + { + DEBUGASSERT("Unknown interrupt"); + } + + /* Unlock the semaphore if locked */ + + ret = nxsem_post(priv->sem); + + if (ret < 0) + { + lcderr("ERROR: nxsem_post() failed\n"); + } + + return OK; +} + +/**************************************************************************** + * Name: stm32_ltdc_waitforirq + * + * Description: + * Helper waits until the ltdc irq occurs. In the current design That means + * that a register reload was been completed. + * Note! The caller must use this function within a critical section. + * + * Returned Value: + * OK - On success otherwise ERROR + * + ****************************************************************************/ + +static int stm32_ltdc_waitforirq(void) +{ + int ret = OK; + struct stm32_interrupt_s *priv = &g_interrupt; + + ret = nxsem_wait(priv->sem); + + if (ret < 0) + { + lcderr("ERROR: nxsem_wait() failed\n"); + } + + ret = priv->error; + + return ret; +} + +/**************************************************************************** + * Name: stm32_ltdc_reload + * + * Description: + * Reload the layer shadow register and make layer changes visible. + * Note! The caller must ensure that a previous register reloading has been + * completed. + * + * Input Parameters: + * value - Reload flag (e.g. upon vertical blank or immediately) + * waitvblank - Wait until register reload is finished + * + ****************************************************************************/ + +static int stm32_ltdc_reload(uint8_t value, bool waitvblank) +{ + int ret = OK; + + /* Reloads the shadow register. + * Note! This will not trigger an register reload interrupt if + * immediately reload is set. + */ + + reginfo("set LTDC_SRCR=%08x\n", value); + putreg32(value, STM32_LTDC_SRCR); + reginfo("configured LTDC_SRCR=%08" PRIx32 "\n", getreg32(STM32_LTDC_SRCR)); + + if (value == LTDC_SRCR_VBR && waitvblank) + { + /* Wait upon vertical blanking period */ + + ret = stm32_ltdc_waitforirq(); + } + else + { + /* Wait until register reload hase been done */ + + while (getreg32(STM32_LTDC_SRCR) & value); + } + + return ret; +} + +/**************************************************************************** + * Name: stm32_ltdc_irqconfig + * + * Description: + * Configure interrupts + * + ****************************************************************************/ + +static void stm32_ltdc_irqconfig(void) +{ + /* Attach LTDC interrupt vector */ + + irq_attach(g_interrupt.irq, stm32_ltdcirq, NULL); + + /* Enable the IRQ at the NVIC */ + + up_enable_irq(g_interrupt.irq); + + /* Enable interrupts expect line interrupt */ + + stm32_ltdc_irqctrl(LTDC_IER_RRIE | + LTDC_IER_TERRIE | + LTDC_IER_FUIE, + LTDC_IER_LIE); + + /* Configure line interrupt */ + + stm32_ltdc_linepos(); +} + +/**************************************************************************** + * Name: stm32_ltdc_globalconfig + * + * Description: + * Configure background color + * Configure dithering + * + ****************************************************************************/ + +static void stm32_ltdc_globalconfig(void) +{ + /* Configure dither */ + + stm32_ltdc_dither( +#ifdef CONFIG_STM32_LTDC_DITHER + true, +#else + false, +#endif + STM32_LTDC_DITHER_RED, + STM32_LTDC_DITHER_GREEN, + STM32_LTDC_DITHER_BLUE); + + /* Configure background color */ + + stm32_ltdc_bgcolor(STM32_LTDC_BACKCOLOR); +} + +/**************************************************************************** + * Name: stm32_ltdc_enable + * + * Description: + * Disable the LCD peripheral + * + * Input Parameters: + * enable - Enable or disable + * + ****************************************************************************/ + +static void stm32_ltdc_enable(bool enable) +{ + uint32_t regval; + + regval = getreg32(STM32_LTDC_GCR); + reginfo("get LTDC_GCR=%08" PRIx32 "\n", regval); + + if (enable == true) + { + regval |= LTDC_GCR_LTDCEN; + } + else + { + regval &= ~LTDC_GCR_LTDCEN; + } + + reginfo("set LTDC_GCR=%08" PRIx32 "\n", regval); + putreg32(regval, STM32_LTDC_GCR); + reginfo("configured LTDC_GCR=%08" PRIx32 "\n", getreg32(STM32_LTDC_GCR)); +} + +/**************************************************************************** + * Name: stm32_ltdc_lpixelformat + * + * Description: + * Set the layer pixel format. + * Note! This changes have no effect until the shadow register reload has + * been done. + * + * Input Parameters: + * Reference to the layer control structure + * + ****************************************************************************/ + +static void stm32_ltdc_lpixelformat(struct stm32_ltdc_s *layer) +{ + uint8_t overlay = layer->layerno; + DEBUGASSERT(layer->layerno < LTDC_NLAYERS); + + /* Configure PFCR register */ + + reginfo("set LTDC_L%dPFCR=%08" PRIx32 "\n", overlay + 1, + stm32_fmt_layer_t[overlay]); + putreg32(stm32_fmt_layer_t[overlay], stm32_pfcr_layer_t[overlay]); + + /* Reload shadow register */ + + stm32_ltdc_reload(LTDC_SRCR_IMR, false); +} + +/**************************************************************************** + * Name: stm32_ltdc_lframebuffer + * + * Description: + * Configure layer framebuffer of the entire window. + * Note! This changes have no effect until the shadow register reload has + * been done. + * + * Input Parameters: + * Reference to the layer control structure + * + ****************************************************************************/ + +static void stm32_ltdc_lframebuffer(struct stm32_ltdc_s *layer) +{ + uint32_t cfblr; + uint32_t rxpos; + uint32_t rypos; + uint32_t whpcr; + uint32_t wvpcr; + uint8_t layerno = layer->layerno; + + DEBUGASSERT(layer->layerno < LTDC_NLAYERS); + reginfo("xpos = %d, ypos = %d, xres = %d, yres = %d\n", 0, 0, + stm32_width_layer_t[layerno], stm32_height_layer_t[layerno]); + + /* Calculate register position */ + + rxpos = STM32_LTDC_LXWHPCR_WHSTPOS + 1; + rypos = STM32_LTDC_LXWVPCR_WVSTPOS + 1; + + /* Accumulate horizontal position */ + + whpcr = LTDC_LXWHPCR_WHSTPOS(rxpos); + whpcr |= LTDC_LXWHPCR_WHSPPOS(rxpos + stm32_width_layer_t[layerno] - 1); + + /* Accumulate vertical position */ + + wvpcr = LTDC_LXWVPCR_WVSTPOS(rypos); + wvpcr |= LTDC_LXWVPCR_WVSPPOS(rypos + stm32_height_layer_t[layerno] - 1); + + /* Configure LxWHPCR / LxWVPCR register */ + + reginfo("set LTDC_L%dWHPCR=%08" PRIx32 "\n", layerno + 1, whpcr); + putreg32(whpcr, stm32_whpcr_layer_t[layerno]); + reginfo("set LTDC_L%dWVPCR=%08" PRIx32 "\n", layerno + 1, wvpcr); + putreg32(wvpcr, stm32_wvpcr_layer_t[layerno]); + + /* Configure LxCFBAR register */ + + reginfo("set LTDC_L%dCFBAR=%08" PRIx32 "\n", layerno + 1, + stm32_fbmem_layer_t[layerno]); + putreg32(stm32_fbmem_layer_t[layerno], stm32_cfbar_layer_t[layerno]); + + /* Configure LxCFBLR register */ + + /* Calculate line length */ + + cfblr = LTDC_LXCFBLR_CFBP(stm32_stride_layer_t[layerno]) | + LTDC_LXCFBLR_CFBLL(stm32_width_layer_t[layerno] * + STM32_LTDC_LX_BYPP(stm32_bpp_layer_t[layerno]) + 3); + + reginfo("set LTDC_L%dCFBLR=%08" PRIx32 "\n", layerno + 1, cfblr); + putreg32(cfblr, stm32_cfblr_layer_t[layerno]); + + /* Configure LxCFBLNR register */ + + reginfo("set LTDC_L%dCFBLNR=%08" PRIx32 "\n", layerno + 1, + stm32_height_layer_t[layerno]); + putreg32(stm32_height_layer_t[layerno], stm32_cfblnr_layer_t[layerno]); + + /* Reload shadow register */ + + stm32_ltdc_reload(LTDC_SRCR_IMR, false); +} + +/**************************************************************************** + * Name: stm32_ltdc_lenable + * + * Description: + * Enable or disable layer. + * Note! This changes have no effect until the shadow register reload has + * been done. + * + * Input Parameters: + * layer - Reference to the layer control structure + * enable - Enable or disable layer + * + ****************************************************************************/ + +static void stm32_ltdc_lenable(struct stm32_ltdc_s *layer, bool enable) +{ + uint32_t regval; + DEBUGASSERT(layer->layerno < LTDC_NLAYERS); + + regval = getreg32(stm32_cr_layer_t[layer->layerno]); + + if (enable == true) + { + regval |= LTDC_LXCR_LEN; + } + else + { + regval &= ~LTDC_LXCR_LEN; + } + + /* Enable/Disable layer */ + + reginfo("set LTDC_L%dCR=%08" PRIx32 "\n", layer->layerno + 1, regval); + putreg32(regval, stm32_cr_layer_t[layer->layerno]); + + /* Reload shadow register */ + + stm32_ltdc_reload(LTDC_SRCR_IMR, false); +} + +/**************************************************************************** + * Name: stm32_ltdc_ltransp + * + * Description: + * Change layer transparency. + * Note! This changes have no effect until the shadow register reload has + * been done. + * + * Input Parameters: + * layer - Reference to the layer control structure + * transp - Transparency + * mode - Transparency mode + * + ****************************************************************************/ + +static void stm32_ltdc_ltransp(struct stm32_ltdc_s *layer, + uint8_t transp, + uint32_t mode) +{ + uint32_t bf1; + uint32_t bf2; + + DEBUGASSERT(layer->layerno < LTDC_NLAYERS); + +#ifdef CONFIG_FB_OVERLAY + if (mode == FB_CONST_ALPHA) + { + bf1 = LTDC_BF1_CONST_ALPHA; + bf2 = LTDC_BF2_CONST_ALPHA; + } + else + { + bf1 = LTDC_BF1_PIXEL_ALPHA; + bf2 = LTDC_BF2_PIXEL_ALPHA; + } +#else + bf1 = LTDC_BF1_CONST_ALPHA; + bf2 = LTDC_BF2_CONST_ALPHA; +#endif + + reginfo("set LTDC_L%dBFCR=%08" PRIx32 "\n", layer->layerno + 1, + (LTDC_LXBFCR_BF1(bf1) | LTDC_LXBFCR_BF2(bf2))); + + /* Set blendmode */ + + putreg32((LTDC_LXBFCR_BF1(bf1) | LTDC_LXBFCR_BF2(bf2)), + stm32_bfcr_layer_t[layer->layerno]); + + /* Set alpha */ + + reginfo("set LTDC_L%dCACR=%02x\n", layer->layerno + 1, transp); + putreg32(transp, stm32_cacr_layer_t[layer->layerno]); + + /* Reload shadow register */ + + stm32_ltdc_reload(LTDC_SRCR_IMR, false); +} + +/**************************************************************************** + * Name: stm32_ltdc_lchromakey + * + * Description: + * Change layer chromakey. + * Note! This changes have no effect until the shadow register reload has + * been done. + * + * Input Parameters: + * layer - Reference to the layer control structure + * chroma - chromakey + * + ****************************************************************************/ + +static void stm32_ltdc_lchromakey(struct stm32_ltdc_s *layer, + uint32_t chroma) +{ + uint32_t rgb; + DEBUGASSERT(layer->layerno < LTDC_NLAYERS); + + reginfo("%08" PRIx32 "\n", getreg32(stm32_cr_layer_t[layer->layerno])); + + /* Set chromakey */ + +#ifdef CONFIG_STM32_FB_CMAP + uint8_t r = g_vtable.cmap.red[chroma]; + uint8_t g = g_vtable.cmap.green[chroma]; + uint8_t b = g_vtable.cmap.blue[chroma]; + rgb = ((r << 16) | (g << 8) | b); +#else + rgb = ARGB8888(chroma); +#endif + + reginfo("set LTDC_L%dCKCR=%08" PRIx32 "\n", layer->layerno + 1, rgb); + putreg32(rgb, stm32_ckcr_layer_t[layer->layerno]); + + /* Reload shadow register */ + + stm32_ltdc_reload(LTDC_SRCR_IMR, false); +} + +/**************************************************************************** + * Name: stm32_ltdc_lchromakeyenable + * + * Description: + * Enable or disable layer chromakey support. + * Note! This changes have no effect until the shadow register reload has + * been done. + * + * Input Parameters: + * layer - Reference to the layer control structure + * enable - Enable or disable chromakey + * + ****************************************************************************/ + +static void stm32_ltdc_lchromakeyenable(struct stm32_ltdc_s *layer, + bool enable) +{ + uint32_t regval; + DEBUGASSERT(layer->layerno < LTDC_NLAYERS); + + regval = getreg32(stm32_cr_layer_t[layer->layerno]); + + /* Enable/Disable colorkey */ + + if (enable == true) + { + regval |= LTDC_LXCR_COLKEN; + } + else + { + regval &= ~LTDC_LXCR_COLKEN; + } + + reginfo("set LTDC_L%dCR=%08" PRIx32 "\n", layer->layerno + 1, regval); + putreg32(regval, stm32_cr_layer_t[layer->layerno]); + + /* Reload shadow register */ + + stm32_ltdc_reload(LTDC_SRCR_IMR, false); +} + +/**************************************************************************** + * Name: stm32_ltdc_lclutenable + * + * Description: + * Disable or enable the layer clut support + * + * Input Parameters: + * layer - Reference to the layer control structure + * enable - Enable or disable + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_FB_CMAP +static void stm32_ltdc_lclutenable(struct stm32_ltdc_s *layer, + bool enable) +{ + uint32_t regval; + + regval = getreg32(stm32_cr_layer_t[layer->oinfo.overlay]); + reginfo("get LTDC_L%dCR=%08" PRIx32 "\n", + layer->oinfo.overlay + 1, regval); + + /* Disable the clut support during update the color table */ + + if (enable == true) + { + regval |= LTDC_LXCR_CLUTEN; + } + else + { + regval &= ~LTDC_LXCR_CLUTEN; + } + + reginfo("set LTDC_L%dCR=%08" PRIx32 "\n", layer->oinfo.overlay, regval); + putreg32(regval, stm32_cr_layer_t[layer->oinfo.overlay]); + + /* Reload shadow register */ + + stm32_ltdc_reload(LTDC_SRCR_IMR, false); +} + +/**************************************************************************** + * Name: stm32_ltdc_lputclut + * + * Description: + * Update the clut layer register during blank period. + * Note! The clut register is no shadow register. + * + * Input Parameters: + * layer - Reference to the layer control structure + * cmap - Color map + * + ****************************************************************************/ + +static void stm32_ltdc_lputclut(struct stm32_ltdc_s *layer, + const struct fb_cmap_s *cmap) +{ + int n; + irqstate_t flags; + + /* Disable clut during register update */ + + stm32_ltdc_lclutenable(layer, false); + + /* Update the clut registers. Ensure operation is atomic or in interrupt + * protected context. + */ + + flags = enter_critical_section(); + + for (n = cmap->first; n < cmap->len && n < STM32_LTDC_NCLUT; n++) + { + uint32_t regval; + + regval = (uint32_t)LTDC_CLUT_ADD(n) | + (uint32_t)LTDC_CLUT_RED(cmap->red[n]) | + (uint32_t)LTDC_CLUT_GREEN(cmap->green[n]) | + (uint32_t)LTDC_CLUT_BLUE(cmap->blue[n]); + + reginfo("set LTDC_L%dCLUTWR = %08" PRIx32 ", first = %d, len = %d\n", + layer->oinfo.overlay + 1, regval, cmap->first, cmap->len); + putreg32(regval, stm32_clutwr_layer_t[layer->oinfo.overlay]); + } + + leave_critical_section(flags); + + /* Enable clut after register update */ + + stm32_ltdc_lclutenable(layer, true); + + /* Reload shadow control register */ + + stm32_ltdc_reload(LTDC_SRCR_IMR, false); +} + +/**************************************************************************** + * Name: stm32_ltdc_lgetclut + * + * Description: + * Copy the layers color lookup table. + * + * Input Parameters: + * layer - Reference to the layer control structure + * cmap - Color map + * + ****************************************************************************/ + +static void stm32_ltdc_lgetclut(struct stm32_ltdc_s *layer, + struct fb_cmap_s *cmap) +{ + int n; + struct fb_cmap_s *priv_cmap = &g_vtable.cmap; + + /* Copy from internal cmap */ + + for (n = cmap->first; n < cmap->len && n < STM32_LTDC_NCLUT; n++) + { +# ifdef CONFIG_STM32_FB_TRANSPARENCY + cmap->transp[n] = priv_cmap->transp[n]; +# endif + cmap->red[n] = priv_cmap->red[n]; + cmap->green[n] = priv_cmap->green[n]; + cmap->blue[n] = priv_cmap->blue[n]; + + reginfo("color = %d, transp=%02x, red=%02x, green=%02x, blue=%02x\n", + n, +# ifdef CONFIG_STM32_FB_TRANSPARENCY + cmap->transp[n], +# endif + cmap->red[n], + cmap->green[n], + cmap->blue[n]); + } +} +#endif /* CONFIG_STM32_FB_CMAP */ + +/**************************************************************************** + * Name: stm32_ltdc_lclear + * + * Description: + * Clear the whole layer + * + * Input Parameters: + * overlayno - Number overlay + * + ****************************************************************************/ + +static void stm32_ltdc_lclear(uint8_t overlayno) +{ + memset((uint8_t *)stm32_fbmem_layer_t[overlayno], 0, + stm32_fblen_layer_t[overlayno]); +} + +/**************************************************************************** + * Name: stm32_ltdc_lvalidate + * + * Description: + * Validates if the given area is within the overlay framebuffer memory + * region + * + * Input Parameters: + * layer - Reference to the layer control structure + * area - Reference to the overlay area + * + ****************************************************************************/ + +#if defined(CONFIG_STM32_DMA2D) && defined(CONFIG_FB_OVERLAY_BLIT) +static bool stm32_ltdc_lvalidate(const struct stm32_ltdc_s *layer, + const struct fb_area_s *area) +{ + uint32_t offset; + + offset = (area->y + area->h - 1) * layer->oinfo.stride + + (area->x + area->w) * layer->oinfo.bpp / 8; + + return (offset <= layer->oinfo.fblen && area->w > 0 && area->h > 0); +} +#endif /* defined(CONFIG_STM32_DMA2D) && defined(CONFIG_FB_OVERLAY_BLIT) */ + +/**************************************************************************** + * Name: stm32_ltdc_linit + * + * Description: + * Initialize layer to their default states. + * + * Initialize: + * - layer framebuffer + * - layer pixelformat + * - layer defaultcolor + * - layer chromakey + * - layer transparency + * - layer clut + * + * Input Parameters: + * layer - Reference to the layer control structure + * + ****************************************************************************/ + +static void stm32_ltdc_linit(uint8_t overlay) +{ + DEBUGASSERT(overlay < LTDC_NLAYERS); + + struct stm32_ltdcdev_s *dev = &g_vtable; + struct stm32_ltdc_s *layer = &dev->layer[overlay]; + + /* Disable layer */ + + stm32_ltdc_lenable(layer, false); + + /* Clear the layer framebuffer */ + + stm32_ltdc_lclear(overlay); + + /* Set layers framebuffer */ + + stm32_ltdc_lframebuffer(layer); + + /* Set layers pixel input format */ + + stm32_ltdc_lpixelformat(layer); + + /* Configure layer default color */ + + stm32_ltdc_ldefaultcolor(layer, stm32_defaultcolor_layer_t[overlay]); + + /* Layers default transparency */ + + stm32_ltdc_ltransp(layer, 0xff, 0); + + /* Layers chromakey */ + + stm32_ltdc_lchromakey(layer, stm32_chromakey_layer_t[overlay]); + + /* Enable chromakey */ + + stm32_ltdc_lchromakeyenable(layer, stm32_chromakeyen_layer_t[overlay]); + +#ifdef CONFIG_STM32_FB_CMAP + /* Disable clut by default */ + + if (dev->vinfo.fmt == FB_FMT_RGB8) + { + /* Initialize LTDC clut register */ + + stm32_ltdc_lputclut(layer, &g_vtable.cmap); + + /* Configure the clut register */ + + stm32_ltdc_lclutenable(layer, true); + } +#endif + + /* Finally enable the layer */ + + stm32_ltdc_lenable(layer, true); +} + +/**************************************************************************** + * Name: stm32_ltdc_dma2dlinit + * + * Description: + * Initialize dma2d layer to their default states. + * + * Initialize: + * - layer framebuffer + * - layer pixelformat + * - layer size + * - layer color + * - layer chromakey + * - layer transparency + * - layer clut + * + * Input Parameters: + * layer - Reference to the layer control structure + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_DMA2D +static void stm32_ltdc_dma2dlinit(void) +{ + int n; + struct stm32_ltdcdev_s *dev = &g_vtable; + + for (n = 0; n < DMA2D_NLAYERS; n++) + { + uint32_t overlay = n + LTDC_NLAYERS; + struct stm32_ltdc_s *layer = &dev->layer[overlay]; + uint8_t * fbmem = (uint8_t *)STM32_DMA2D_BUFFER_START; + + layer->layerno = overlay; + layer->oinfo.fbmem = fbmem + STM32_DMA2D_LAYER_SIZE * n; + layer->oinfo.fblen = STM32_DMA2D_FBSIZE; + layer->oinfo.stride = STM32_DMA2D_STRIDE; + layer->oinfo.overlay = overlay; + layer->oinfo.bpp = STM32_DMA2D_BPP; + layer->oinfo.blank = 0; + layer->oinfo.chromakey = 0; + layer->oinfo.color = 0; + layer->oinfo.transp.transp = 0xff; + layer->oinfo.transp.transp_mode = 0; + layer->oinfo.sarea.x = 0; + layer->oinfo.sarea.y = 0; + layer->oinfo.sarea.w = STM32_DMA2D_WIDTH; + layer->oinfo.sarea.h = STM32_DMA2D_HEIGHT; + layer->oinfo.accl = DMA2D_ACCL; + layer->lock = &g_lock; + layer->dma2dinfo.fmt = STM32_DMA2D_COLOR_FMT; + layer->dma2dinfo.transp_mode = STM32_DMA2D_PFCCR_AM_NONE; + layer->dma2dinfo.xres = layer->oinfo.sarea.w; + layer->dma2dinfo.yres = layer->oinfo.sarea.h; + layer->dma2dinfo.oinfo = &layer->oinfo; + } +} +#endif /* CONFIG_STM32_DMA2D */ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_getvideoinfo + * + * Description: + * Entrypoint ioctl FBIOGET_VIDEOINFO + * Get the videoinfo for the framebuffer + * + * Input Parameters: + * vtable - The framebuffer driver object + * vinfo - the videoinfo object + * + * Returned Value: + * On success - OK + * On error - -EINVAL + * + ****************************************************************************/ + +static int stm32_getvideoinfo(struct fb_vtable_s *vtable, + struct fb_videoinfo_s *vinfo) +{ + struct stm32_ltdcdev_s *priv = (struct stm32_ltdcdev_s *)vtable; + + lcdinfo("vtable=%p vinfo=%p\n", vtable, vinfo); + DEBUGASSERT(vtable != NULL && priv == &g_vtable && vinfo != NULL); + + memcpy(vinfo, &priv->vinfo, sizeof(struct fb_videoinfo_s)); + return OK; +} + +/**************************************************************************** + * Name: stm32_getplaneinfo + * + * Description: + * Entrypoint ioctl FBIOGET_PLANEINFO + * Get the planeinfo for the framebuffer + * + * Input Parameters: + * vtable - The framebuffer driver object + * pinfo - the planeinfo object + * + * Returned Value: + * On success - OK + * On error - -EINVAL + * + ****************************************************************************/ + +static int stm32_getplaneinfo(struct fb_vtable_s *vtable, int planeno, + struct fb_planeinfo_s *pinfo) +{ + struct stm32_ltdcdev_s *priv = (struct stm32_ltdcdev_s *)vtable; + + DEBUGASSERT(vtable != NULL && priv == &g_vtable); + lcdinfo("vtable=%p planeno=%d pinfo=%p\n", vtable, planeno, pinfo); + + if (planeno == 0) + { + memcpy(pinfo, &priv->pinfo, sizeof(struct fb_planeinfo_s)); + return OK; + } + + lcderr("ERROR: Returning EINVAL\n"); + return -EINVAL; +} + +/**************************************************************************** + * Name: stm32_getcmap + * + * Description: + * Entrypoint ioctl FBIOGET_CMAP + * Get a range of CLUT values for the LCD + * + * Input Parameters: + * vtable - The framebuffer driver object + * cmap - the color table + * + * Returned Value: + * On success - OK + * On error - -EINVAL + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_FB_CMAP +static int stm32_getcmap(struct fb_vtable_s *vtable, + struct fb_cmap_s *cmap) +{ + int ret; + struct stm32_ltdcdev_s *priv = (struct stm32_ltdcdev_s *)vtable; + + DEBUGASSERT(vtable != NULL && priv == &g_vtable && cmap != NULL); + lcdinfo("vtable=%p cmap=%p\n", vtable, cmap); + + if (priv->vinfo.fmt != FB_FMT_RGB8) + { + lcderr("ERROR: CLUT is not supported for the pixel format: %d\n", + priv->vinfo.fmt); + ret = -EINVAL; + } + else if (cmap->first >= STM32_LTDC_NCLUT) + { + lcderr("ERROR: only %d color table entries supported\n", + STM32_LTDC_NCLUT); + ret = -EINVAL; + } + else + { + /* Currently, there is no api to set color map for each overlay + * separately. LTDC layers can have different color maps. Get the cmap + * from the main overlay. + */ + + struct stm32_ltdc_s *layer; +# ifdef CONFIG_STM32_LTDC_L2 + layer = &priv->layer[LTDC_LAYER_L2]; +# else + layer = &priv->layer[LTDC_LAYER_L1]; +# endif + nxmutex_lock(layer->lock); + stm32_ltdc_lgetclut(layer, cmap); + nxmutex_unlock(layer->lock); + + ret = OK; + } + + return ret; +} + +/**************************************************************************** + * Name: stm32_putcmap + * + * Description: + * Entrypoint ioctl FBIOPUT_CMAP + * Set a range of the CLUT values for the LCD + * + * Input Parameters: + * vtable - The framebuffer driver object + * cmap - the color table + * + * Returned Value: + * On success - OK + * On error - -EINVAL + * + ****************************************************************************/ + +static int stm32_putcmap(struct fb_vtable_s *vtable, + const struct fb_cmap_s *cmap) +{ + int ret; + struct stm32_ltdcdev_s *priv = (struct stm32_ltdcdev_s *)vtable; + + DEBUGASSERT(vtable != NULL && priv == &g_vtable && cmap != NULL); + lcdinfo("vtable=%p cmap=%p\n", vtable, cmap); + + if (priv->vinfo.fmt != FB_FMT_RGB8) + { + lcderr("ERROR: CLUT is not supported for the pixel format: %d\n", + priv->vinfo.fmt); + ret = -EINVAL; + } + else if (cmap->first >= STM32_LTDC_NCLUT) + { + lcderr("ERROR: only %d color table entries supported\n", + STM32_LTDC_NCLUT); + ret = -EINVAL; + } + else + { + /* Currently, there is no api to set color map for each overlay + * separately. LTDC layers can have different color maps, but is shared + * for now. + */ + + int n; + struct fb_cmap_s *priv_cmap = &g_vtable.cmap; + + /* First copy to internal cmap */ + + for (n = cmap->first; n < cmap->len && n < STM32_LTDC_NCLUT; n++) + { + priv_cmap->red[n] = cmap->red[n]; + priv_cmap->green[n] = cmap->green[n]; + priv_cmap->blue[n] = cmap->blue[n]; +# ifdef CONFIG_STM32_FB_TRANSPARENCY + /* Not supported by LTDC */ + + priv_cmap->transp[n] = cmap->transp[n]; +# endif + } + + priv_cmap->first = cmap->first; + priv_cmap->len = cmap->len; + + /* Update the layer clut register */ + + nxmutex_lock(&g_lock); + + for (n = 0; n < LTDC_NLAYERS; n++) + { + struct stm32_ltdc_s *layer = &priv->layer[n]; + stm32_ltdc_lputclut(layer, priv_cmap); + } + +# ifdef CONFIG_STM32_DMA2D + /* Update dma2d cmap */ + + priv->dma2d->setclut(cmap); +# endif + nxmutex_unlock(&g_lock); + + ret = OK; + } + + return ret; +} +#endif /* CONFIG_STM32_FB_CMAP */ + +/**************************************************************************** + * Name: stm32_ioctl_waitforvsync + * Description: + * Entrypoint ioctl FBIO_WAITFORSYNC + ****************************************************************************/ + +#ifdef CONFIG_FB_SYNC +static int stm32_waitforvsync(struct fb_vtable_s *vtable) +{ + int ret; + + DEBUGASSERT(vtable != NULL && vtable == &g_vtable.vtable); + + /* Wait upon vertical synchronization. */ + + ret = stm32_ltdc_reload(LTDC_SRCR_VBR, true); + + return ret; +} +#endif /* CONFIG_FB_SYNC */ + +/**************************************************************************** + * Name: stm32_getoverlayinfo + * Description: + * Entrypoint ioctl FBIOGET_OVERLAYINFO + ****************************************************************************/ + +#ifdef CONFIG_FB_OVERLAY +static int stm32_getoverlayinfo(struct fb_vtable_s *vtable, + int overlayno, + struct fb_overlayinfo_s *oinfo) +{ + struct stm32_ltdcdev_s *priv = (struct stm32_ltdcdev_s *)vtable; + + lcdinfo("vtable=%p overlay=%d oinfo=%p\n", vtable, overlayno, oinfo); + DEBUGASSERT(vtable != NULL && priv == &g_vtable); + + if (overlayno < LTDC_NOVERLAYS) + { + struct stm32_ltdc_s *layer = &priv->layer[overlayno]; + memcpy(oinfo, &layer->oinfo, sizeof(struct fb_overlayinfo_s)); + return OK; + } + + lcderr("ERROR: Returning EINVAL\n"); + return -EINVAL; +} + +/**************************************************************************** + * Name: stm32_settransp + * Description: + * Entrypoint ioctl FBIOSET_TRANSP + ****************************************************************************/ + +static int stm32_settransp(struct fb_vtable_s *vtable, + const struct fb_overlayinfo_s *oinfo) +{ + struct stm32_ltdcdev_s *priv = (struct stm32_ltdcdev_s *)vtable; + + DEBUGASSERT(vtable != NULL && priv == &g_vtable); + lcdinfo("vtable=%p, overlay=%d, transp=%02x, transp_mode=%02x\n", vtable, + oinfo->overlay, oinfo->transp.transp, oinfo->transp.transp_mode); + + if (oinfo->transp.transp_mode > 1) + { + lcderr("ERROR: Returning ENOSYS, transparency mode not supported\n"); + return -ENOSYS; + } + + if (oinfo->overlay < LTDC_NOVERLAYS) + { + struct stm32_ltdc_s *layer = &priv->layer[oinfo->overlay]; + + nxmutex_lock(layer->lock); + layer->oinfo.transp.transp = oinfo->transp.transp; + layer->oinfo.transp.transp_mode = oinfo->transp.transp_mode; + +# ifdef CONFIG_STM32_DMA2D + if (layer->oinfo.transp.transp_mode == 0) + { + layer->dma2dinfo.transp_mode = STM32_DMA2D_PFCCR_AM_CONST; + } + else if (layer->oinfo.transp.transp_mode == 1) + { + layer->dma2dinfo.transp_mode = STM32_DMA2D_PFCCR_AM_PIXEL; + } + + if (oinfo->overlay < LTDC_NLAYERS) +# endif + { + /* Set LTDC blendmode and alpha value */ + + stm32_ltdc_ltransp(layer, layer->oinfo.transp.transp, + layer->oinfo.transp.transp_mode); + } + + nxmutex_unlock(layer->lock); + return OK; + } + + lcderr("ERROR: Returning EINVAL\n"); + return -EINVAL; +} + +/**************************************************************************** + * Name: stm32_setchromakey + * Description: + * Entrypoint ioctl FBIOSET_CHROMAKEY + ****************************************************************************/ + +static int stm32_setchromakey(struct fb_vtable_s *vtable, + const struct fb_overlayinfo_s *oinfo) +{ + struct stm32_ltdcdev_s *priv = (struct stm32_ltdcdev_s *)vtable; + + DEBUGASSERT(vtable != NULL && priv == &g_vtable && oinfo != NULL); + lcdinfo("vtable=%p, overlay=%d, chromakey=%08" PRIx32 "\n", vtable, + oinfo->overlay, oinfo->chromakey); + + if (oinfo->overlay < LTDC_NLAYERS) + { + int ret; + struct stm32_ltdc_s *layer = &priv->layer[oinfo->overlay]; + +# ifndef CONFIG_STM32_LTDC_L1_CHROMAKEY + if (oinfo->overlay == LTDC_LAYER_L1) + { + return -ENOSYS; + } +# endif + +# ifndef CONFIG_STM32_LTDC_L2_CHROMAKEY + if (oinfo->overlay == LTDC_LAYER_L2) + { + return -ENOSYS; + } +# endif + + nxmutex_lock(layer->lock); +# ifdef CONFIG_STM32_FB_CMAP + if (oinfo->chromakey >= g_vtable.cmap.len) + { + lcderr("ERROR: Clut index %" PRId32 " is out of range\n", + oinfo->chromakey); + ret = -EINVAL; + } + else +# endif + { + layer->oinfo.chromakey = oinfo->chromakey; + + /* Set chromakey */ + + stm32_ltdc_lchromakey(layer, layer->oinfo.chromakey); + ret = OK; + } + + nxmutex_unlock(layer->lock); + return ret; + } +# ifdef CONFIG_STM32_DMA2D + else if (oinfo->overlay < LTDC_NOVERLAYS) + { + /* Chromakey not supported by DMA2D */ + + return -ENOSYS; + } +# endif + + lcderr("ERROR: Returning EINVAL\n"); + return -EINVAL; +} + +/**************************************************************************** + * Name: stm32_setcolor + * Description: + * Entrypoint ioctl FBIOSET_COLOR + ****************************************************************************/ + +static int stm32_setcolor(struct fb_vtable_s *vtable, + const struct fb_overlayinfo_s *oinfo) +{ + DEBUGASSERT(vtable != NULL && vtable == &g_vtable.vtable && oinfo != NULL); + lcdinfo("vtable=%p, overlay=%d, color=%08" PRIx32 "\n", + vtable, oinfo->overlay, oinfo->color); + + if (oinfo->overlay < LTDC_NOVERLAYS) + { +# ifdef CONFIG_STM32_DMA2D + + /* Set color within the active overlay is not supported by LTDC. So use + * DMA2D controller instead when configured. + */ + + int ret; + struct stm32_ltdcdev_s *priv = (struct stm32_ltdcdev_s *) + vtable; + struct stm32_ltdc_s *layer = &priv->layer[oinfo->overlay]; + struct fb_overlayinfo_s *poverlay = layer->dma2dinfo.oinfo; + + DEBUGASSERT(&layer->oinfo == poverlay); + + nxmutex_lock(layer->lock); + poverlay->color = oinfo->color; + ret = priv->dma2d->fillcolor(&layer->dma2dinfo, &poverlay->sarea, + poverlay->color); + nxmutex_unlock(layer->lock); + + return ret; +# else + /* Coloring not supported by LTDC */ + + return -ENOSYS; +# endif + } + + lcderr("ERROR: Returning EINVAL\n"); + return -EINVAL; +} + +/**************************************************************************** + * Name: stm32_setblank + * Description: + * Entrypoint ioctl FBIOSET_BLANK + ****************************************************************************/ + +static int stm32_setblank(struct fb_vtable_s *vtable, + const struct fb_overlayinfo_s *oinfo) +{ + struct stm32_ltdcdev_s *priv = (struct stm32_ltdcdev_s *)vtable; + + DEBUGASSERT(vtable != NULL && priv == &g_vtable && oinfo != NULL); + lcdinfo("vtable=%p, overlay=%d, blank=%02x\n", + vtable, oinfo->overlay, oinfo->blank); + + if (oinfo->overlay < LTDC_NLAYERS) + { + struct stm32_ltdc_s *layer = &priv->layer[oinfo->overlay]; + + nxmutex_lock(layer->lock); + layer->oinfo.blank = oinfo->blank; + + /* Enable or disable layer */ + + stm32_ltdc_lenable(layer, (layer->oinfo.blank == 0)); + nxmutex_unlock(layer->lock); + + return OK; + } +# ifdef CONFIG_STM32_DMA2D + else if (oinfo->overlay < LTDC_NOVERLAYS) + { + /* DMA2D overlays are non visible */ + + return OK; + } +# endif + + lcderr("ERROR: Returning EINVAL\n"); + return -EINVAL; +} + +/**************************************************************************** + * Name: stm32_setarea + * Description: + * Entrypoint ioctl FBIOSET_AREA + ****************************************************************************/ + +static int stm32_setarea(struct fb_vtable_s *vtable, + const struct fb_overlayinfo_s *oinfo) +{ + DEBUGASSERT(vtable != NULL && vtable == &g_vtable.vtable && oinfo != NULL); + lcdinfo("vtable=%p, overlay=%d, x=%d, y=%d, w=%d, h=%d\n", vtable, + oinfo->overlay, oinfo->sarea.x, oinfo->sarea.y, oinfo->sarea.w, + oinfo->sarea.h); + + if (oinfo->overlay < LTDC_NLAYERS) + { + /* LTDC area is defined by the overlay size (display resolution) only */ + + return -ENOSYS; + } + +# ifdef CONFIG_STM32_DMA2D + if (oinfo->overlay < LTDC_NOVERLAYS) + { + struct stm32_ltdcdev_s *priv = (struct stm32_ltdcdev_s *) + vtable; + struct stm32_ltdc_s *layer = &priv->layer[oinfo->overlay]; + + nxmutex_lock(layer->lock); + memcpy(&layer->oinfo.sarea, &oinfo->sarea, sizeof(struct fb_area_s)); + nxmutex_unlock(layer->lock); + + return OK; + } +# endif + + lcderr("ERROR: Returning EINVAL\n"); + return -EINVAL; +} + +/**************************************************************************** + * Name: stm32_blit + * Description: + * Entrypoint ioctl FBIOSET_BLIT + ****************************************************************************/ + +# ifdef CONFIG_FB_OVERLAY_BLIT +static int stm32_blit(struct fb_vtable_s *vtable, + const struct fb_overlayblit_s *blit) +{ + DEBUGASSERT(vtable != NULL && vtable == &g_vtable.vtable && blit != NULL); + lcdinfo("vtable = %p, blit = %p\n", vtable, blit); + + if (blit->dest.overlay < LTDC_NOVERLAYS && + blit->src.overlay < LTDC_NOVERLAYS) + { +# ifdef CONFIG_STM32_DMA2D + int ret; + struct fb_area_s sarea; + const struct fb_area_s *darea = &blit->dest.area; + struct stm32_ltdcdev_s *priv = (struct stm32_ltdcdev_s *) + vtable; + struct stm32_ltdc_s *dlayer = &priv->layer[blit->dest.overlay]; + struct stm32_ltdc_s *slayer = &priv->layer[blit->src.overlay]; + + DEBUGASSERT(&dlayer->oinfo == dlayer->dma2dinfo.oinfo && + &slayer->oinfo == slayer->dma2dinfo.oinfo); + + /* DMA2D doesn't support image scale, so set to the smallest area */ + + memcpy(&sarea, &blit->src.area, sizeof(struct fb_area_s)); + + /* Check if area is within the entire overlay */ + + if (!stm32_ltdc_lvalidate(dlayer, darea) || + !stm32_ltdc_lvalidate(slayer, &sarea)) + { + return -EINVAL; + } + + sarea.w = MIN(darea->w, sarea.w); + sarea.h = MIN(darea->h, sarea.h); + + nxmutex_lock(dlayer->lock); + ret = priv->dma2d->blit(&dlayer->dma2dinfo, darea->x, darea->y, + &slayer->dma2dinfo, &sarea); + nxmutex_unlock(dlayer->lock); + + return ret; +# else + /* LTDC doesn't support blit transfer */ + + return -ENOSYS; +# endif + } + + lcderr("ERROR: Returning EINVAL\n"); + return -EINVAL; +} + +/**************************************************************************** + * Name: stm32_blend + * Description: + * Entrypoint ioctl FBIOSET_BLEND + ****************************************************************************/ + +static int stm32_blend(struct fb_vtable_s *vtable, + const struct fb_overlayblend_s *blend) +{ + DEBUGASSERT(vtable != NULL && vtable == &g_vtable.vtable && blend != NULL); + lcdinfo("vtable = %p, blend = %p\n", vtable, blend); + + if (blend->dest.overlay < LTDC_NOVERLAYS && + blend->foreground.overlay < LTDC_NOVERLAYS && + blend->background.overlay < LTDC_NOVERLAYS) + { +# ifdef CONFIG_STM32_DMA2D + int ret; + struct fb_area_s barea; + const struct fb_area_s *darea = &blend->dest.area; + const struct fb_area_s *farea = &blend->foreground.area; + struct stm32_ltdcdev_s *priv = (struct stm32_ltdcdev_s *) + vtable; + struct stm32_ltdc_s *dlayer = &priv->layer[blend->dest.overlay]; + struct stm32_ltdc_s *flayer = + &priv->layer[blend->foreground.overlay]; + struct stm32_ltdc_s *blayer = + &priv->layer[blend->background.overlay]; + + DEBUGASSERT(&dlayer->oinfo == dlayer->dma2dinfo.oinfo && + &flayer->oinfo == flayer->dma2dinfo.oinfo && + &blayer->oinfo == blayer->dma2dinfo.oinfo); + + /* DMA2D doesn't support image scale, so set to the smallest area */ + + memcpy(&barea, &blend->background.area, sizeof(struct fb_area_s)); + + /* Check if area is within the entire overlay */ + + if (!stm32_ltdc_lvalidate(dlayer, darea) || + !stm32_ltdc_lvalidate(flayer, farea) || + !stm32_ltdc_lvalidate(blayer, &barea)) + { + lcderr("ERROR: Returning EINVAL\n"); + return -EINVAL; + } + + barea.w = MIN(darea->w, barea.w); + barea.h = MIN(darea->h, barea.h); + barea.w = MIN(farea->w, barea.w); + barea.h = MIN(farea->h, barea.h); + + nxmutex_lock(dlayer->lock); + ret = priv->dma2d->blend(&dlayer->dma2dinfo, darea->x, darea->y, + &flayer->dma2dinfo, farea->x, farea->y, + &blayer->dma2dinfo, &barea); + nxmutex_unlock(dlayer->lock); + + return ret; +# else + /* LTDC doesn't support blend transfer */ + + return -ENOSYS; +# endif + } + + lcderr("ERROR: Returning EINVAL\n"); + return -EINVAL; +} +# endif /* CONFIG_FB_OVERLAY_BLIT */ +#endif /* CONFIG_FB_OVERLAY */ + +/**************************************************************************** + * Name: stm32_ltdcreset + * + * Description: + * Reset LTDC via APB2RSTR + * + ****************************************************************************/ + +void stm32_ltdcreset(void) +{ + uint32_t regval = getreg32(STM32_RCC_APB2RSTR); + putreg32(regval | RCC_APB2RSTR_LTDCRST, STM32_RCC_APB2RSTR); + putreg32(regval & ~RCC_APB2RSTR_LTDCRST, STM32_RCC_APB2RSTR); +} + +/**************************************************************************** + * Name: stm32_ltdcinitialize + * + * Description: + * Initialize the ltdc controller + * + * Returned Value: + * OK + * + ****************************************************************************/ + +int stm32_ltdcinitialize(void) +{ + int ret = OK; + + lcdinfo("Initialize LTDC driver\n"); + + if (g_initialized == true) + { + return ret; + } + + /* Disable the LCD */ + + stm32_ltdc_enable(false); + + lcdinfo("Configuring the LCD controller\n"); + + /* Configure LCD periphery */ + + lcdinfo("Configure lcd periphery\n"); + stm32_ltdc_periphconfig(); + + /* Configure interrupts */ + + lcdinfo("Configure interrupts\n"); + stm32_ltdc_irqconfig(); + + /* Configure global ltdc register */ + + lcdinfo("Configure global register\n"); + stm32_ltdc_globalconfig(); + +#ifdef CONFIG_STM32_DMA2D + /* Initialize the dma2d controller */ + + ret = stm32_dma2dinitialize(); + + if (ret != OK) + { + return ret; + } + + /* Bind the dma2d interface */ + + g_vtable.dma2d = stm32_dma2ddev(); + DEBUGASSERT(g_vtable.dma2d != NULL); +#endif + +#ifdef CONFIG_STM32_FB_CMAP + /* Cleanup clut */ + + memset(&g_redclut, 0, STM32_LTDC_NCLUT); + memset(&g_blueclut, 0, STM32_LTDC_NCLUT); + memset(&g_greenclut, 0, STM32_LTDC_NCLUT); +# ifdef CONFIG_STM32_FB_TRANSPARENCY + memset(&g_transpclut, 0, STM32_LTDC_NCLUT); +# endif +#endif /* CONFIG_STM32_FB_CMAP */ + + /* Initialize ltdc layer */ + + lcdinfo("Initialize ltdc layer\n"); + stm32_ltdc_linit(LTDC_LAYER_L1); +#ifdef CONFIG_STM32_LTDC_L2 + stm32_ltdc_linit(LTDC_LAYER_L2); +#endif + +#ifdef CONFIG_STM32_DMA2D + stm32_ltdc_dma2dlinit(); +#endif + /* Enable the backlight */ + +#ifdef CONFIG_STM32_LCD_BACKLIGHT + stm32_backlight(true); +#endif + + /* Reload shadow register */ + + lcdinfo("Reload shadow register\n"); + stm32_ltdc_reload(LTDC_SRCR_IMR, false); + + /* Turn the LCD on */ + + lcdinfo("Enabling the display\n"); + stm32_ltdc_enable(true); + + /* Set initialized state */ + + g_initialized = true; + return ret; +} + +/**************************************************************************** + * Name: stm32_ltdcgetvplane + * + * Description: + * Return a a reference to the framebuffer object for the specified video + * plane. + * + * Input Parameters: + * None + * + * Returned Value: + * Reference to the framebuffer object (NULL on failure) + * + ****************************************************************************/ + +struct fb_vtable_s *stm32_ltdcgetvplane(int vplane) +{ + lcdinfo("vplane: %d\n", vplane); + + if (vplane == 0) + { + return &g_vtable.vtable; + } + + return NULL; +} + +/**************************************************************************** + * Name: stm32_ltdcuninitialize + * + * Description: + * Uninitialize the framebuffer driver. Bad things will happen if you + * call this without first calling fb_initialize()! + * + ****************************************************************************/ + +void stm32_ltdcuninitialize(void) +{ + /* Disable all ltdc interrupts */ + + stm32_ltdc_irqctrl(0, LTDC_IER_RRIE | LTDC_IER_TERRIE | + LTDC_IER_FUIE | LTDC_IER_LIE); + + up_disable_irq(g_interrupt.irq); + irq_detach(g_interrupt.irq); + + /* Disable the LCD controller */ + + stm32_ltdc_enable(false); + + /* Set initialized state */ + + g_initialized = false; +} + +/**************************************************************************** + * Name: stm32_lcd_backlight + * + * Description: + * Provide this interface to turn the backlight on and off. + * + * Input Parameters: + * blon - Enable or disable the lcd backlight + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_LCD_BACKLIGHT +void stm32_backlight(bool blon) +{ + /* Set default backlight level CONFIG_STM32_LTDC_DEFBACKLIGHT */ + + lcderr("ERROR: Not supported\n"); +} +#endif diff --git a/arch/arm/src/common/stm32/stm32_ltdc_m3m4_v1.h b/arch/arm/src/common/stm32/stm32_ltdc_m3m4_v1.h new file mode 100644 index 0000000000000..c0e4e3adb5fbb --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_ltdc_m3m4_v1.h @@ -0,0 +1,106 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_ltdc_m3m4_v1.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_LTDC_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_LTDC_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#if defined(CONFIG_STM32_HAVE_IP_LTDC_M3M4_V1) + +#include + +#include +#include + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_ltdcreset + * + * Description: + * Reset LTDC via APB2RSTR + * + ****************************************************************************/ + +void stm32_ltdcreset(void); + +/**************************************************************************** + * Name: stm32_ltdcinitialize + * + * Description: + * Initialize the ltdc controller + * + * Returned Value: + * OK + * + ****************************************************************************/ + +int stm32_ltdcinitialize(void); + +/**************************************************************************** + * Name: stm32_ltdcuninitialize + * + * Description: + * Uninitialize the ltdc controller + * + ****************************************************************************/ + +void stm32_ltdcuninitialize(void); + +/**************************************************************************** + * Name: stm32_ltdcgetvplane + * + * Description: + * Get video plane reference used by framebuffer interface + * + * Parameter: + * vplane - Video plane + * + * Returned Value: + * Video plane reference + * + ****************************************************************************/ + +struct fb_vtable_s *stm32_ltdcgetvplane(int vplane); + +/**************************************************************************** + * Name: stm32_lcd_backlight + * + * Description: + * If CONFIG_STM32_LCD_BACKLIGHT is defined, then the board-specific logic + * must provide this interface to turn the backlight on and off. + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_LCD_BACKLIGHT +void stm32_backlight(bool blon); +#endif + +#endif /* CONFIG_STM32_HAVE_IP_LTDC_M3M4_V1 */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_LTDC_H */ diff --git a/arch/arm/src/stm32/stm32_mpuinit.h b/arch/arm/src/common/stm32/stm32_mpuinit.h similarity index 91% rename from arch/arm/src/stm32/stm32_mpuinit.h rename to arch/arm/src/common/stm32/stm32_mpuinit.h index f4af906ef4e2c..606d589ef28e4 100644 --- a/arch/arm/src/stm32/stm32_mpuinit.h +++ b/arch/arm/src/common/stm32/stm32_mpuinit.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_mpuinit.h + * arch/arm/src/common/stm32/stm32_mpuinit.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_STM32_MPUINIT_H -#define __ARCH_ARM_SRC_STM32_STM32_MPUINIT_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_MPUINIT_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_MPUINIT_H /**************************************************************************** * Included Files @@ -62,4 +62,4 @@ void stm32_mpu_uheap(uintptr_t start, size_t size); # define stm32_mpu_uheap(start,size) #endif -#endif /* __ARCH_ARM_SRC_STM32_STM32_MPUINIT_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_MPUINIT_H */ diff --git a/arch/arm/src/common/stm32/stm32_mpuinit_m3m4_v1.c b/arch/arm/src/common/stm32/stm32_mpuinit_m3m4_v1.c new file mode 100644 index 0000000000000..cc066077de60b --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_mpuinit_m3m4_v1.c @@ -0,0 +1,103 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_mpuinit_m3m4_v1.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include + +#include "mpu.h" +#include "stm32_mpuinit.h" + +#if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_ARM_MPU) + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_mpuinitialize + * + * Description: + * Configure the MPU to permit user-space access to only restricted SAM3U + * resources. + * + ****************************************************************************/ + +void stm32_mpuinitialize(void) +{ + uintptr_t datastart = MIN(USERSPACE->us_datastart, USERSPACE->us_bssstart); + uintptr_t dataend = MAX(USERSPACE->us_dataend, USERSPACE->us_bssend); + + DEBUGASSERT(USERSPACE->us_textend >= USERSPACE->us_textstart && + dataend >= datastart); + + /* Show MPU information */ + + mpu_showtype(); + + /* Reset MPU if enabled */ + + mpu_reset(); + + /* Configure user flash and SRAM space */ + + mpu_user_flash(USERSPACE->us_textstart, + USERSPACE->us_textend - USERSPACE->us_textstart); + + mpu_user_intsram(datastart, dataend - datastart); + + /* Then enable the MPU */ + + mpu_control(true, false, true); +} + +/**************************************************************************** + * Name: stm32_mpu_uheap + * + * Description: + * Map the user-heap region. + * + * This logic may need an extension to handle external SDRAM). + * + ****************************************************************************/ + +void stm32_mpu_uheap(uintptr_t start, size_t size) +{ + mpu_user_intsram(start, size); +} + +#endif /* CONFIG_BUILD_PROTECTED && CONFIG_ARM_MPU */ diff --git a/arch/arm/src/common/stm32/stm32_oneshot.h b/arch/arm/src/common/stm32/stm32_oneshot.h new file mode 100644 index 0000000000000..7cb508f67d48f --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_oneshot.h @@ -0,0 +1,94 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_oneshot.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_ONESHOT_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_ONESHOT_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include + +#include "stm32_tim.h" + +#ifdef CONFIG_STM32_ONESHOT + +#if !defined(CONFIG_STM32_ONESHOT_MAXTIMERS) || \ + CONFIG_STM32_ONESHOT_MAXTIMERS < 1 +# undef CONFIG_STM32_ONESHOT_MAXTIMERS +# define CONFIG_STM32_ONESHOT_MAXTIMERS 1 +#endif + +#if CONFIG_STM32_ONESHOT_MAXTIMERS > 8 +# warning Additional logic required to handle more than 8 timers +# undef CONFIG_STM32_ONESHOT_MAXTIMERS +# define CONFIG_STM32_ONESHOT_MAXTIMERS 8 +#endif + +typedef void (*oneshot_handler_t)(void *arg); + +struct stm32_oneshot_s +{ + uint8_t chan; +#if CONFIG_STM32_ONESHOT_MAXTIMERS > 1 + uint8_t cbndx; +#endif + volatile bool running; + struct stm32_tim_dev_s *tch; + volatile oneshot_handler_t handler; + volatile void *arg; + uint32_t frequency; + uint32_t period; +}; + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +int stm32_oneshot_initialize(struct stm32_oneshot_s *oneshot, int chan, + uint16_t resolution); +int stm32_oneshot_max_delay(struct stm32_oneshot_s *oneshot, uint64_t *usec); +int stm32_oneshot_start(struct stm32_oneshot_s *oneshot, + oneshot_handler_t handler, void *arg, + const struct timespec *ts); +int stm32_oneshot_cancel(struct stm32_oneshot_s *oneshot, + struct timespec *ts); + +#undef EXTERN +#ifdef __cplusplus +} +#endif + +#endif /* CONFIG_STM32_ONESHOT */ + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_ONESHOT_H */ diff --git a/arch/arm/src/common/stm32/stm32_oneshot_m3m4_v1.c b/arch/arm/src/common/stm32/stm32_oneshot_m3m4_v1.c new file mode 100644 index 0000000000000..e8ba155e9daf7 --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_oneshot_m3m4_v1.c @@ -0,0 +1,458 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_oneshot_m3m4_v1.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include "stm32_oneshot.h" + +#ifdef CONFIG_STM32_ONESHOT + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +static int stm32_oneshot_handler(int irg_num, void * context, void *arg); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static struct stm32_oneshot_s *g_oneshot[CONFIG_STM32_ONESHOT_MAXTIMERS]; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_oneshot_handler + * + * Description: + * Common timer interrupt callback. When any oneshot timer interrupt + * expires, this function will be called. It will forward the call to + * the next level up. + * + * Input Parameters: + * oneshot - The state associated with the expired timer + * + * Returned Value: + * Always returns OK + * + ****************************************************************************/ + +static int stm32_oneshot_handler(int irg_num, void * context, void *arg) +{ + struct stm32_oneshot_s * oneshot = (struct stm32_oneshot_s *) arg; + oneshot_handler_t oneshot_handler; + void *oneshot_arg; + + tmrinfo("Expired...\n"); + DEBUGASSERT(oneshot != NULL && oneshot->handler); + + /* The clock was stopped, but not disabled when the RC match occurred. + * Disable the TC now and disable any further interrupts. + */ + + STM32_TIM_SETISR(oneshot->tch, NULL, NULL, 0); + STM32_TIM_DISABLEINT(oneshot->tch, GTIM_DIER_UIE); + STM32_TIM_SETMODE(oneshot->tch, STM32_TIM_MODE_DISABLED); + STM32_TIM_ACKINT(oneshot->tch, GTIM_SR_UIF); + + /* The timer is no longer running */ + + oneshot->running = false; + + /* Forward the event, clearing out any vestiges */ + + oneshot_handler = (oneshot_handler_t)oneshot->handler; + oneshot->handler = NULL; + oneshot_arg = (void *)oneshot->arg; + oneshot->arg = NULL; + + oneshot_handler(oneshot_arg); + return OK; +} + +/**************************************************************************** + * Name: stm32_allocate_handler + * + * Description: + * Allocate a timer callback handler for the oneshot instance. + * + * Input Parameters: + * oneshot - The state instance the new oneshot timer + * + * Returned Value: + * Returns zero (OK) on success. This can only fail if the number of + * timers exceeds CONFIG_STM32_ONESHOT_MAXTIMERS. + * + ****************************************************************************/ + +static inline int stm32_allocate_handler(struct stm32_oneshot_s *oneshot) +{ +#if CONFIG_STM32_ONESHOT_MAXTIMERS > 1 + int ret = -EBUSY; + int i; + + /* Search for an unused handler */ + + for (i = 0; i < CONFIG_STM32_ONESHOT_MAXTIMERS; i++) + { + /* Is this handler available? */ + + if (g_oneshot[i] == NULL) + { + /* Yes... assign it to this oneshot */ + + g_oneshot[i] = oneshot; + oneshot->cbndx = i; + ret = OK; + break; + } + } + + return ret; + +#else + if (g_oneshot[0] == NULL) + { + g_oneshot[0] = oneshot; + return OK; + } + + return -EBUSY; +#endif +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_oneshot_initialize + * + * Description: + * Initialize the oneshot timer wrapper + * + * Input Parameters: + * oneshot Caller allocated instance of the oneshot state structure + * chan Timer counter channel to be used. + * resolution The required resolution of the timer in units of + * microseconds. NOTE that the range is restricted to the + * range of uint16_t (excluding zero). + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned + * on failure. + * + ****************************************************************************/ + +int stm32_oneshot_initialize(struct stm32_oneshot_s *oneshot, int chan, + uint16_t resolution) +{ + uint32_t frequency; + + tmrinfo("chan=%d resolution=%d usec\n", chan, resolution); + DEBUGASSERT(oneshot && resolution > 0); + + /* Get the TC frequency the corresponds to the requested resolution */ + + frequency = USEC_PER_SEC / (uint32_t)resolution; + oneshot->frequency = frequency; + + oneshot->tch = stm32_tim_init(chan); + if (!oneshot->tch) + { + tmrerr("ERROR: Failed to allocate TIM%d\n", chan); + return -EBUSY; + } + + STM32_TIM_SETCLOCK(oneshot->tch, frequency); + + /* Initialize the remaining fields in the state structure. */ + + oneshot->chan = chan; + oneshot->running = false; + oneshot->handler = NULL; + oneshot->arg = NULL; + + /* Assign a callback handler to the oneshot */ + + return stm32_allocate_handler(oneshot); +} + +/**************************************************************************** + * Name: stm32_oneshot_max_delay + * + * Description: + * Determine the maximum delay of the one-shot timer (in microseconds) + * + ****************************************************************************/ + +int stm32_oneshot_max_delay(struct stm32_oneshot_s *oneshot, uint64_t *usec) +{ + DEBUGASSERT(oneshot != NULL && usec != NULL); + + *usec = (uint64_t)(UINT32_MAX / oneshot->frequency) * + (uint64_t)USEC_PER_SEC; + return OK; +} + +/**************************************************************************** + * Name: stm32_oneshot_start + * + * Description: + * Start the oneshot timer + * + * Input Parameters: + * oneshot Caller allocated instance of the oneshot state structure. This + * structure must have been previously initialized via a call to + * stm32_oneshot_initialize(); + * handler The function to call when when the oneshot timer expires. + * arg An opaque argument that will accompany the callback. + * ts Provides the duration of the one shot timer. + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned + * on failure. + * + ****************************************************************************/ + +int stm32_oneshot_start(struct stm32_oneshot_s *oneshot, + oneshot_handler_t handler, void *arg, + const struct timespec *ts) +{ + uint64_t usec; + uint64_t period; + irqstate_t flags; + + tmrinfo("handler=%p arg=%p, ts=(%jd, %ld)\n", + handler, arg, (intmax_t)ts->tv_sec, ts->tv_nsec); + DEBUGASSERT(oneshot && handler && ts); + DEBUGASSERT(oneshot->tch); + + /* Was the oneshot already running? */ + + flags = enter_critical_section(); + if (oneshot->running) + { + /* Yes.. then cancel it */ + + tmrinfo("Already running... cancelling\n"); + stm32_oneshot_cancel(oneshot, NULL); + } + + /* Save the new handler and its argument */ + + oneshot->handler = handler; + oneshot->arg = arg; + + /* Express the delay in microseconds */ + + usec = ts->tv_sec * USEC_PER_SEC + + (ts->tv_nsec / NSEC_PER_USEC); + + /* Get the timer counter frequency and determine the number of counts need + * to achieve the requested delay. + * + * frequency = ticks / second + * ticks = seconds * frequency + * = (usecs * frequency) / USEC_PER_SEC; + */ + + period = (usec * (uint64_t)oneshot->frequency) / USEC_PER_SEC; + + tmrinfo("usec=%llu period=%08llx\n", usec, period); + DEBUGASSERT(period <= UINT32_MAX); + + /* Set up to receive the callback when the interrupt occurs */ + + STM32_TIM_SETISR(oneshot->tch, stm32_oneshot_handler, oneshot, 0); + + /* Set timer period */ + + oneshot->period = (uint32_t)period; + STM32_TIM_SETPERIOD(oneshot->tch, (uint32_t)period); + + /* Start the counter */ + + STM32_TIM_SETMODE(oneshot->tch, STM32_TIM_MODE_PULSE); + + STM32_TIM_ACKINT(oneshot->tch, GTIM_SR_UIF); + STM32_TIM_ENABLEINT(oneshot->tch, GTIM_DIER_UIE); + + /* Enable interrupts. We should get the callback when the interrupt + * occurs. + */ + + oneshot->running = true; + leave_critical_section(flags); + return OK; +} + +/**************************************************************************** + * Name: stm32_oneshot_cancel + * + * Description: + * Cancel the oneshot timer and return the time remaining on the timer. + * + * NOTE: This function may execute at a high rate with no timer running (as + * when pre-emption is enabled and disabled). + * + * Input Parameters: + * oneshot Caller allocated instance of the oneshot state structure. This + * structure must have been previously initialized via a call to + * stm32_oneshot_initialize(); + * ts The location in which to return the time remaining on the + * oneshot timer. A time of zero is returned if the timer is + * not running. ts may be zero in which case the time remaining + * is not returned. + * + * Returned Value: + * Zero (OK) is returned on success. A call to up_timer_cancel() when + * the timer is not active should also return success; a negated errno + * value is returned on any failure. + * + ****************************************************************************/ + +int stm32_oneshot_cancel(struct stm32_oneshot_s *oneshot, + struct timespec *ts) +{ + irqstate_t flags; + uint64_t usec; + uint64_t sec; + uint64_t nsec; + uint32_t count; + uint32_t period; + + /* Was the timer running? */ + + flags = enter_critical_section(); + if (!oneshot->running) + { + /* No.. Just return zero timer remaining and successful cancellation. + * This function may execute at a high rate with no timer running + * (as when pre-emption is enabled and disabled). + */ + + ts->tv_sec = 0; + ts->tv_nsec = 0; + leave_critical_section(flags); + return OK; + } + + /* Yes.. Get the timer counter and period registers and stop the counter. + * If the counter expires while we are doing this, the counter clock will + * be stopped, but the clock will not be disabled. + * + * The expected behavior is that the counter register will freezes at + * a value equal to the RC register when the timer expires. The counter + * should have values between 0 and RC in all other cased. + * + * REVISIT: This does not appear to be the case. + */ + + tmrinfo("Cancelling...\n"); + + count = STM32_TIM_GETCOUNTER(oneshot->tch); + period = oneshot->period; + + /* Now we can disable the interrupt and stop the timer. */ + + STM32_TIM_DISABLEINT(oneshot->tch, GTIM_DIER_UIE); + STM32_TIM_SETISR(oneshot->tch, NULL, NULL, 0); + STM32_TIM_SETMODE(oneshot->tch, STM32_TIM_MODE_DISABLED); + + oneshot->running = false; + oneshot->handler = NULL; + oneshot->arg = NULL; + leave_critical_section(flags); + + /* Did the caller provide us with a location to return the time + * remaining? + */ + + if (ts) + { + /* Yes.. then calculate and return the time remaining on the + * oneshot timer. + */ + + tmrinfo("period=%lu count=%lu\n", + (unsigned long)period, (unsigned long)count); + + /* REVISIT: I am not certain why the timer counter value sometimes + * exceeds RC. Might be a bug, or perhaps the counter does not stop + * in all cases. + */ + + if (count >= period) + { + /* No time remaining (?) */ + + ts->tv_sec = 0; + ts->tv_nsec = 0; + } + else + { + /* The total time remaining is the difference. Convert that + * to units of microseconds. + * + * frequency = ticks / second + * seconds = ticks * frequency + * usecs = (ticks * USEC_PER_SEC) / frequency; + */ + + usec = (((uint64_t)(period - count)) * USEC_PER_SEC) / + oneshot->frequency; + + /* Return the time remaining in the correct form */ + + sec = usec / USEC_PER_SEC; + nsec = ((usec) - (sec * USEC_PER_SEC)) * NSEC_PER_USEC; + + ts->tv_sec = sec; + ts->tv_nsec = nsec; + } + + tmrinfo("remaining (%jd, %ld)\n", + (intmax_t)ts->tv_sec, ts->tv_nsec); + } + + return OK; +} + +#endif /* CONFIG_STM32_ONESHOT */ diff --git a/arch/arm/src/common/stm32/stm32_oneshot_m3m4_v1_lowerhalf.c b/arch/arm/src/common/stm32/stm32_oneshot_m3m4_v1_lowerhalf.c new file mode 100644 index 0000000000000..729adb4078c3e --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_oneshot_m3m4_v1_lowerhalf.c @@ -0,0 +1,309 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_oneshot_m3m4_v1_lowerhalf.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include +#include +#include + +#include "stm32_oneshot.h" + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/* This structure describes the state of the oneshot timer lower-half driver + */ + +struct stm32_oneshot_lowerhalf_s +{ + /* This is the part of the lower half driver that is visible to the upper- + * half client of the driver. This must be the first thing in this + * structure so that pointers to struct oneshot_lowerhalf_s are cast + * compatible to struct stm32_oneshot_lowerhalf_s and vice versa. + */ + + struct oneshot_lowerhalf_s lh; /* Common lower-half driver fields */ + + /* Private lower half data follows */ + + struct stm32_oneshot_s oneshot; /* STM32-specific oneshot state */ +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +static void stm32_oneshot_handler(void *arg); + +static int stm32_max_delay(struct oneshot_lowerhalf_s *lower, + struct timespec *ts); +static int stm32_start(struct oneshot_lowerhalf_s *lower, + const struct timespec *ts); +static int stm32_cancel(struct oneshot_lowerhalf_s *lower, + struct timespec *ts); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* Lower half operations */ + +static const struct oneshot_operations_s g_oneshot_ops = +{ + .max_delay = stm32_max_delay, + .start = stm32_start, + .cancel = stm32_cancel, +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_oneshot_handler + * + * Description: + * Timer expiration handler + * + * Input Parameters: + * arg - Should be the same argument provided when stm32_oneshot_start() + * was called. + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void stm32_oneshot_handler(void *arg) +{ + struct stm32_oneshot_lowerhalf_s *priv = + (struct stm32_oneshot_lowerhalf_s *)arg; + + DEBUGASSERT(priv != NULL); + + /* Perhaps the callback was nullified in a race condition with + * stm32_cancel? + */ + + oneshot_process_callback(&priv->lh); +} + +/**************************************************************************** + * Name: stm32_max_delay + * + * Description: + * Determine the maximum delay of the one-shot timer (in microseconds) + * + * Input Parameters: + * lower An instance of the lower-half oneshot state structure. This + * structure must have been previously initialized via a call to + * oneshot_initialize(); + * ts The location in which to return the maximum delay. + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned + * on failure. + * + ****************************************************************************/ + +static int stm32_max_delay(struct oneshot_lowerhalf_s *lower, + struct timespec *ts) +{ + struct stm32_oneshot_lowerhalf_s *priv = + (struct stm32_oneshot_lowerhalf_s *)lower; + uint64_t usecs; + int ret; + + DEBUGASSERT(priv != NULL && ts != NULL); + ret = stm32_oneshot_max_delay(&priv->oneshot, &usecs); + if (ret >= 0) + { + uint64_t sec = usecs / 1000000; + usecs -= 1000000 * sec; + + ts->tv_sec = sec; + ts->tv_nsec = usecs * 1000; + } + + return ret; +} + +/**************************************************************************** + * Name: stm32_start + * + * Description: + * Start the oneshot timer + * + * Input Parameters: + * lower An instance of the lower-half oneshot state structure. This + * structure must have been previously initialized via a call to + * oneshot_initialize(); + * handler The function to call when when the oneshot timer expires. + * arg An opaque argument that will accompany the callback. + * ts Provides the duration of the one shot timer. + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned + * on failure. + * + ****************************************************************************/ + +static int stm32_start(struct oneshot_lowerhalf_s *lower, + const struct timespec *ts) +{ + struct stm32_oneshot_lowerhalf_s *priv = + (struct stm32_oneshot_lowerhalf_s *)lower; + irqstate_t flags; + int ret; + + DEBUGASSERT(priv != NULL && ts != NULL); + + /* Save the callback information and start the timer */ + + flags = enter_critical_section(); + ret = stm32_oneshot_start(&priv->oneshot, + stm32_oneshot_handler, priv, ts); + leave_critical_section(flags); + + if (ret < 0) + { + tmrerr("ERROR: stm32_oneshot_start failed: %d\n", flags); + } + + return ret; +} + +/**************************************************************************** + * Name: stm32_cancel + * + * Description: + * Cancel the oneshot timer and return the time remaining on the timer. + * + * NOTE: This function may execute at a high rate with no timer running (as + * when pre-emption is enabled and disabled). + * + * Input Parameters: + * lower Caller allocated instance of the oneshot state structure. This + * structure must have been previously initialized via a call to + * oneshot_initialize(); + * ts The location in which to return the time remaining on the + * oneshot timer. A time of zero is returned if the timer is + * not running. + * + * Returned Value: + * Zero (OK) is returned on success. A call to up_timer_cancel() when + * the timer is not active should also return success; a negated errno + * value is returned on any failure. + * + ****************************************************************************/ + +static int stm32_cancel(struct oneshot_lowerhalf_s *lower, + struct timespec *ts) +{ + struct stm32_oneshot_lowerhalf_s *priv = + (struct stm32_oneshot_lowerhalf_s *)lower; + irqstate_t flags; + int ret; + + DEBUGASSERT(priv != NULL); + + /* Cancel the timer */ + + flags = enter_critical_section(); + ret = stm32_oneshot_cancel(&priv->oneshot, ts); + leave_critical_section(flags); + + if (ret < 0) + { + tmrerr("ERROR: stm32_oneshot_cancel failed: %d\n", flags); + } + + return ret; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: oneshot_initialize + * + * Description: + * Initialize the oneshot timer and return a oneshot lower half driver + * instance. + * + * Input Parameters: + * chan Timer counter channel to be used. + * resolution The required resolution of the timer in units of + * microseconds. NOTE that the range is restricted to the + * range of uint16_t (excluding zero). + * + * Returned Value: + * On success, a non-NULL instance of the oneshot lower-half driver is + * returned. NULL is return on any failure. + * + ****************************************************************************/ + +struct oneshot_lowerhalf_s *oneshot_initialize(int chan, + uint16_t resolution) +{ + struct stm32_oneshot_lowerhalf_s *priv; + int ret; + + /* Allocate an instance of the lower half driver */ + + priv = (struct stm32_oneshot_lowerhalf_s *) + kmm_zalloc(sizeof(struct stm32_oneshot_lowerhalf_s)); + + if (priv == NULL) + { + tmrerr("ERROR: Failed to initialized state structure\n"); + return NULL; + } + + /* Initialize the lower-half driver structure */ + + priv->lh.ops = &g_oneshot_ops; + + /* Initialize the contained STM32 oneshot timer */ + + ret = stm32_oneshot_initialize(&priv->oneshot, chan, resolution); + if (ret < 0) + { + tmrerr("ERROR: stm32_oneshot_initialize failed: %d\n", ret); + kmm_free(priv); + return NULL; + } + + return &priv->lh; +} diff --git a/arch/arm/src/common/stm32/stm32_opamp.h b/arch/arm/src/common/stm32/stm32_opamp.h new file mode 100644 index 0000000000000..f3c9827a95927 --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_opamp.h @@ -0,0 +1,38 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_opamp.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_COMPAT_STM32OPAMP_H +#define __ARCH_ARM_SRC_COMMON_COMPAT_STM32OPAMP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#if defined(CONFIG_STM32_HAVE_IP_OPAMP_M3M4_V1) +# include "stm32_opamp_m3m4_v1.h" +#else +# error "Unsupported STM32 stm32_opamp" +#endif + +#endif /* __ARCH_ARM_SRC_COMMON_COMPAT_STM32OPAMP_H */ diff --git a/arch/arm/src/common/stm32/stm32_opamp_m3m4_v1.c b/arch/arm/src/common/stm32/stm32_opamp_m3m4_v1.c new file mode 100644 index 0000000000000..7c90dae4b8b8d --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_opamp_m3m4_v1.c @@ -0,0 +1,1411 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_opamp_m3m4_v1.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include +#include + +#include "chip.h" +#include "stm32_gpio.h" +#include "stm32_opamp_m3m4_v1.h" +#include "stm32_gpio.h" +#include "stm32_opamp_m3m4_v1.h" + +/* OPAMP "upper half" support must be enabled */ + +#ifdef CONFIG_STM32_OPAMP + +/* Some OPAMP peripheral must be enabled */ + +/* Up to 4 OPAMPs in STM32F3 Series */ + +#if defined(CONFIG_STM32_OPAMP1) || defined(CONFIG_STM32_OPAMP2) || \ + defined(CONFIG_STM32_OPAMP3) || defined(CONFIG_STM32_OPAMP4) + +#ifndef CONFIG_STM32_SYSCFG +# error "SYSCFG clock enable must be set" +#endif + +/* @TODO: support for STM32F30XX opamps */ + +#if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) + +/* Currently only STM32F33XX supported */ + +#if defined(CONFIG_STM32_STM32F30XX) +# error "Not supported yet" +#endif + +#if defined(CONFIG_STM32_STM32F33XX) +# if defined(CONFIG_STM32_OPAMP1) || defined(CONFIG_STM32_OPAMP3) || \ + defined(CONFIG_STM32_OPAMP4) +# error "STM32F33 supports only OPAMP2" +# endif +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* OPAMPs default configuration *********************************************/ + +#ifdef CONFIG_STM32_OPAMP1 +# ifndef OPAMP1_MODE +# define OPAMP1_MODE OPAMP_MODE_DEFAULT +# endif +# ifndef OPAMP1_MUX +# define OPAMP1_MUX OPAMP_MUX_DEFAULT +# endif +# ifndef OPAMP1_USERCAL +# define OPAMP1_USERCAL OPAMP_USERCAL_DEFAULT +# endif +# ifndef OPAMP1_LOCK +# define OPAMP1_LOCK OPAMP_LOCK_DEFAULT +# endif +# ifndef OPAMP1_GAIN +# define OPAMP1_GAIN OPAMP_GAIN_DEFAULT +# endif +#endif +#ifdef CONFIG_STM32_OPAMP2 +# ifndef OPAMP2_MODE +# define OPAMP2_MODE OPAMP_MODE_DEFAULT +# endif +# ifndef OPAMP2_MUX +# define OPAMP2_MUX OPAMP_MUX_DEFAULT +# endif +# ifndef OPAMP2_USERCAL +# define OPAMP2_USERCAL OPAMP_USERCAL_DEFAULT +# endif +# ifndef OPAMP2_LOCK +# define OPAMP2_LOCK OPAMP_LOCK_DEFAULT +# endif +# ifndef OPAMP2_GAIN +# define OPAMP2_GAIN OPAMP_GAIN_DEFAULT +# endif +#endif +#ifdef CONFIG_STM32_OPAMP3 +# ifndef OPAMP3_MODE +# define OPAMP3_MODE OPAMP_MODE_DEFAULT +# endif +# ifndef OPAMP3_MUX +# define OPAMP3_MUX OPAMP_MUX_DEFAULT +# endif +# ifndef OPAMP3_USERCAL +# define OPAMP3_USERCAL OPAMP_USERCAL_DEFAULT +# endif +# ifndef OPAMP3_LOCK +# define OPAMP3_LOCK OPAMP_LOCK_DEFAULT +# endif +# ifndef OPAMP3_GAIN +# define OPAMP3_GAIN OPAMP_GAIN_DEFAULT +# endif +#endif +#ifdef CONFIG_STM32_OPAMP4 +# ifndef OPAMP4_MODE +# define OPAMP4_MODE OPAMP_MODE_DEFAULT +# endif +# ifndef OPAMP4_MUX +# define OPAMP4_MUX OPAMP_MUX_DEFAULT +# endif +# ifndef OPAMP4_USERCAL +# define OPAMP4_USERCAL OPAMP_USERCAL_DEFAULT +# endif +# ifndef OPAMP4_LOCK +# define OPAMP4_LOCK OPAMP_LOCK_DEFAULT +# endif +# ifndef OPAMP4_GAIN +# define OPAMP4_GAIN OPAMP_GAIN_DEFAULT +# endif +#endif + +/* Some assertions *********************************************************/ + +/* Check OPAMPs inputs selection */ + +#ifdef CONFIG_STM32_OPAMP1 +# if (OPAMP1_MODE == OPAMP_MODE_FOLLOWER) +# define OPAMP1_VMSEL OPAMP1_VMSEL_FOLLOWER +# endif +# if (OPAMP1_MODE == OPAMP_MODE_PGA) +# define OPAMP1_VMSEL OPAMP1_VMSEL_PGA +# endif +# if (OPAMP1_MODE == OPAMP_MODE_STANDALONE) +# ifndef OPAMP1_VMSEL +# error "OPAMP1_VMSEL must be selected in standalone mode!" +# endif +# endif +# ifndef OPAMP1_VPSEL +# error "OPAMP1_VPSEL must be selected in standalone mode!" +# endif +#endif +#ifdef CONFIG_STM32_OPAMP2 +# if (OPAMP2_MODE == OPAMP_MODE_FOLLOWER) +# define OPAMP2_VMSEL OPAMP2_VMSEL_FOLLOWER +# endif +# if (OPAMP2_MODE == OPAMP_MODE_PGA) +# define OPAMP2_VMSEL OPAMP2_VMSEL_PGA +# endif +# if (OPAMP2_MODE == OPAMP_MODE_STANDALONE) +# ifndef OPAMP2_VMSEL +# error "OPAMP2_VMSEL must be selected in standalone mode!" +# endif +# endif +# ifndef OPAMP2_VPSEL +# error "OPAMP2_VPSEL must be selected in standalone mode!" +# endif +#endif +#ifdef CONFIG_STM32_OPAMP3 +# if (OPAMP3_MODE == OPAMP_MODE_FOLLOWER) +# define OPAMP3_VMSEL OPAMP3_VMSEL_FOLLOWER +# endif +# if (OPAMP3_MODE == OPAMP_MODE_PGA) +# define OPAMP3_VMSEL OPAMP3_VMSEL_PGA +# endif +# if (OPAMP3_MODE == OPAMP_MODE_STANDALONE) +# ifndef OPAMP3_VMSEL +# error "OPAMP3_VMSEL must be selected in standalone mode!" +# endif +# endif +# ifndef OPAMP3_VPSEL +# error "OPAMP3_VPSEL must be selected in standalone mode!" +# endif +#endif +#ifdef CONFIG_STM32_OPAMP4 +# if (OPAMP4_MODE == OPAMP_MODE_FOLLOWER) +# define OPAMP4_VMSEL OPAMP4_VMSEL_FOLLOWER +# endif +# if (OPAMP4_MODE == OPAMP_MODE_PGA) +# define OPAMP4_VMSEL OPAMP4_VMSEL_PGA +# endif +# if (OPAMP4_MODE == OPAMP_MODE_STANDALONE) +# ifndef OPAMP4_VMSEL +# error "OPAMP4_VMSEL must be selected in standalone mode!" +# endif +# endif +# ifndef OPAMP4_VPSEL +# error "OPAMP4_VPSEL must be selected in standalone mode!" +# endif +#endif + +/* When OPAMP MUX enabled, make sure that secondary selection inputs are + * configured + */ + +#ifdef CONFIG_STM32_OPAMP1 +# if (OPAMP1_MUX == OPAMP_MUX_ENABLE) +# if !defined(OPAMP1_VMSSEL) || !defined(OPAMP1_VPSSEL) +# error "OPAMP1_VMSSEL and OPAMP1_VPSSEL must be selected when OPAMP1 MUX enabled!" +# endif +# endif +#endif +#ifdef CONFIG_STM32_OPAMP2 +# if (OPAMP2_MUX == OPAMP_MUX_ENABLE) +# if !defined(OPAMP2_VMSSEL) || !defined(OPAMP2_VPSSEL) +# error "OPAMP2_VMSSEL and OPAMP2_VPSSEL must be selected when OPAMP2 MUX enabled!" +# endif +# endif +#endif +#ifdef CONFIG_STM32_OPAMP3 +# if (OPAMP3_MUX == OPAMP_MUX_ENABLE) +# if !defined(OPAMP3_VMSSEL) || !defined(OPAMP3_VPSSEL) +# error "OPAMP3_VMSSEL and OPAMP3_VPSSEL must be selected when OPAMP3 MUX enabled!" +# endif +# endif +#endif +#ifdef CONFIG_STM32_OPAMP4 +# if (OPAMP4_MUX == OPAMP_MUX_ENABLE) +# if !defined(OPAMP4_VMSSEL) || !defined(OPAMP4_VPSSEL) +# error "OPAMP4_VMSSEL and OPAMP4_VPSSEL must be selected when OPAMP4 MUX enabled!" +# endif +# endif +#endif + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/* This structure describes the configuration of one OPAMP device */ + +struct stm32_opamp_s +{ + uint32_t csr; /* Control and status register */ + + uint8_t lock:1; /* OPAMP lock */ + uint8_t mux:1; /* Timer controlled MUX mode */ + uint8_t mode:2; /* OPAMP mode */ + uint8_t gain:4; /* OPAMP gain in PGA mode */ + + uint8_t vm_sel:2; /* Inverting input selection */ + uint8_t vp_sel:2; /* Non inverting input selection */ + uint8_t vms_sel:2; /* Inverting input secondary selection (MUX mode) */ + uint8_t vps_sel:2; /* Non inverting input secondary selection (Mux mode) */ + + uint16_t trim_n:5; /* Offset trimming value (NMOS) */ + uint16_t trim_p:5; /* Offset trimming value (PMOS) */ + uint16_t _reserved:6; /* reserved for calibration */ +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/* OPAMP Register access */ + +static inline void opamp_modify_csr(struct stm32_opamp_s *priv, + uint32_t clearbits, uint32_t setbits); +static inline uint32_t opamp_getreg_csr(struct stm32_opamp_s *priv); +static inline void opamp_putreg_csr(struct stm32_opamp_s *priv, + uint32_t value); +static bool stm32_opamplock_get(struct stm32_opamp_s *priv); +static int stm32_opamplock(struct stm32_opamp_s *priv, bool lock); + +/* Initialization */ + +static int stm32_opampconfig(struct stm32_opamp_s *priv); +static int stm32_opampenable(struct stm32_opamp_s *priv, bool enable); +static int stm32_opampgain_set(struct stm32_opamp_s *priv, uint8_t gain); +#if 0 +static int stm32_opampcalibrate(struct stm32_opamp_s *priv); +#endif + +/* OPAMP Driver Methods */ + +static void opamp_shutdown(struct opamp_dev_s *dev); +static int opamp_setup(struct opamp_dev_s *dev); +static int opamp_ioctl(struct opamp_dev_s *dev, int cmd, + unsigned long arg); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static const struct opamp_ops_s g_opampops = +{ + .ao_shutdown = opamp_shutdown, + .ao_setup = opamp_setup, + .ao_ioctl = opamp_ioctl +}; + +#ifdef CONFIG_STM32_OPAMP1 +static struct stm32_opamp_s g_opamp1priv = +{ + .csr = STM32_OPAMP1_CSR, + .lock = OPAMP1_LOCK, + .mux = OPAMP1_MUX, + .mode = OPAMP1_MODE, + .vm_sel = OPAMP1_VMSEL, + .vp_sel = OPAMP1_VPSEL, +#if OPAMP1_MUX == OPAMP_MUX_ENABLE + .vms_sel = OPAMP1_VMSSEL, + .vps_sel = OPAMP1_VPSSEL, +#endif + .gain = OPAMP1_GAIN +}; + +static struct opamp_dev_s g_opamp1dev = +{ + .ad_ops = &g_opampops, + .ad_priv = &g_opamp1priv +}; +#endif + +#ifdef CONFIG_STM32_OPAMP2 +static struct stm32_opamp_s g_opamp2priv = +{ + .csr = STM32_OPAMP2_CSR, + .lock = OPAMP2_LOCK, + .mux = OPAMP2_MUX, + .mode = OPAMP2_MODE, + .vm_sel = OPAMP2_VMSEL, + .vp_sel = OPAMP2_VPSEL, +#if OPAMP2_MUX == OPAMP_MUX_ENABLE + .vms_sel = OPAMP2_VMSSEL, + .vps_sel = OPAMP2_VPSSEL, +#endif + .gain = OPAMP2_GAIN +}; + +static struct opamp_dev_s g_opamp2dev = + { + .ad_ops = &g_opampops, + .ad_priv = &g_opamp2priv + }; +#endif + +#ifdef CONFIG_STM32_OPAMP3 +static struct stm32_opamp_s g_opamp3priv = +{ + .csr = STM32_OPAMP3_CSR, + .lock = OPAMP3_LOCK, + .mux = OPAMP3_MUX, + .mode = OPAMP3_MODE, + .vm_sel = OPAMP3_VMSEL, + .vp_sel = OPAMP3_VPSEL, +#if OPAMP3_MUX == OPAMP_MUX_ENABLE + .vms_sel = OPAMP3_VMSSEL, + .vps_sel = OPAMP3_VPSSEL, +#endif + .gain = OPAMP3_GAIN +}; + +static struct opamp_dev_s g_opamp3dev = +{ + .ad_ops = &g_opampops, + .ad_priv = &g_opamp3priv +}; +#endif + +#ifdef CONFIG_STM32_OPAMP4 +static struct stm32_opamp_s g_opamp4priv = +{ + .csr = STM32_OPAMP4_CSR, + .lock = OPAMP4_LOCK, + .mux = OPAMP4_MUX, + .mode = OPAMP4_MODE, + .vm_sel = OPAMP4_VMSEL, + .vp_sel = OPAMP4_VPSEL, +#if OPAMP4_MUX == OPAMP_MUX_ENABLE + .vms_sel = OPAMP4_VMSSEL, + .vps_sel = OPAMP4_VPSSEL, +#endif + .gain = OPAMP4_GAIN +}; + +static struct opamp_dev_s g_opamp4dev = +{ + .ad_ops = &g_opampops, + .ad_priv = &g_opamp4priv +}; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: opamp_modify_csr + * + * Description: + * Modify the value of a 32-bit OPAMP CSR register (not atomic). + * + * Input Parameters: + * priv - A reference to the OPAMP structure + * clrbits - The bits to clear + * setbits - The bits to set + * + * Returned Value: + * None + * + ****************************************************************************/ + +static inline void opamp_modify_csr(struct stm32_opamp_s *priv, + uint32_t clearbits, uint32_t setbits) +{ + uint32_t csr = priv->csr; + + modifyreg32(csr, clearbits, setbits); +} + +/**************************************************************************** + * Name: opamp_getreg_csr + * + * Description: + * Read the value of an OPAMP CSR register + * + * Input Parameters: + * priv - A reference to the OPAMP structure + * + * Returned Value: + * The current contents of the OPAMP CSR register + * + ****************************************************************************/ + +static inline uint32_t opamp_getreg_csr(struct stm32_opamp_s *priv) +{ + uint32_t csr = priv->csr; + + return getreg32(csr); +} + +/**************************************************************************** + * Name: opamp_putreg_csr + * + * Description: + * Write a value to an OPAMP register. + * + * Input Parameters: + * priv - A reference to the OPAMP structure + * value - The value to write to the OPAMP CSR register + * + * Returned Value: + * None + * + ****************************************************************************/ + +static inline void opamp_putreg_csr(struct stm32_opamp_s *priv, + uint32_t value) +{ + uint32_t csr = priv->csr; + + putreg32(value, csr); +} + +/**************************************************************************** + * Name: stm32_opamp_opamplock_get + * + * Description: + * Get OPAMP lock bit state + * + * Input Parameters: + * priv - A reference to the OPAMP structure + * + * Returned Value: + * True if OPAMP locked, false if not locked + * + ****************************************************************************/ + +static bool stm32_opamplock_get(struct stm32_opamp_s *priv) +{ + uint32_t regval; + + regval = opamp_getreg_csr(priv); + + return (((regval & OPAMP_CSR_LOCK) == 0) ? false : true); +} + +/**************************************************************************** + * Name: stm32_opamplock + * + * Description: + * Lock OPAMP CSR register + * + * Input Parameters: + * priv - A reference to the OPAMP structure + * enable - lock flag + * + * Returned Value: + * 0 on success, a negated errno value on failure + * + ****************************************************************************/ + +static int stm32_opamplock(struct stm32_opamp_s *priv, bool lock) +{ + bool current; + + current = stm32_opamplock_get(priv); + + if (current) + { + if (lock == false) + { + aerr("ERROR: OPAMP LOCK can be cleared only by a system reset\n"); + + return -EPERM; + } + } + else + { + if (lock == true) + { + opamp_modify_csr(priv, 0, OPAMP_CSR_LOCK); + + priv->lock = OPAMP_LOCK_RO; + } + } + + return OK; +} + +/**************************************************************************** + * Name: stm32_opampconfig + * + * Description: + * Configure OPAMP and used I/Os + * + * Input Parameters: + * priv - A reference to the OPAMP structure + * + * Returned Value: + * 0 on success, a negated errno value on failure + * + ****************************************************************************/ + +static int stm32_opampconfig(struct stm32_opamp_s *priv) +{ + uint32_t regval = 0; + int index; + + /* Get OPAMP index */ + + switch (priv->csr) + { +#ifdef CONFIG_STM32_OPAMP1 + case STM32_OPAMP1_CSR: + index = 1; + break; +#endif + +#ifdef CONFIG_STM32_OPAMP2 + case STM32_OPAMP2_CSR: + index = 2; + break; +#endif + +#ifdef CONFIG_STM32_OPAMP3 + case STM32_OPAMP3_CSR: + index = 3; + break; +#endif + +#ifdef CONFIG_STM32_OPAMP4 + case STM32_OPAMP4_CSR: + index = 4; + break; +#endif + + default: + return -EINVAL; + } + + /* Configure non inverting input */ + + switch (index) + { +#ifdef CONFIG_STM32_OPAMP1 + case 1: + { + switch (priv->vp_sel) + { + case OPAMP1_VPSEL_PA7: + stm32_configgpio(GPIO_OPAMP1_VINP_1); + regval |= OPAMP_CSR_VPSEL_PA7; + break; + + case OPAMP1_VPSEL_PA5: + stm32_configgpio(GPIO_OPAMP1_VINP_2); + regval |= OPAMP_CSR_VPSEL_PA5; + break; + + case OPAMP1_VPSEL_PA3: + stm32_configgpio(GPIO_OPAMP1_VINP_3); + regval |= OPAMP_CSR_VPSEL_PA3; + break; + + case OPAMP1_VPSEL_PA1: + stm32_configgpio(GPIO_OPAMP1_VINP_4); + regval |= OPAMP_CSR_VPSEL_PA1; + break; + + default: + return -EINVAL; + } + break; + } +#endif + +#ifdef CONFIG_STM32_OPAMP2 + case 2: + { + switch (priv->vp_sel) + { +#ifndef CONFIG_STM32_STM32F33XX + case OPAMP2_VPSEL_PD14: + stm32_configgpio(GPIO_OPAMP2_VINP_1); + regval |= OPAMP_CSR_VPSEL_PD14; + break; +#endif + case OPAMP2_VPSEL_PB14: + stm32_configgpio(GPIO_OPAMP2_VINP_2); + regval |= OPAMP_CSR_VPSEL_PB14; + break; + + case OPAMP2_VPSEL_PB0: + stm32_configgpio(GPIO_OPAMP2_VINP_3); + regval |= OPAMP_CSR_VPSEL_PB0; + break; + + case OPAMP2_VPSEL_PA7: + stm32_configgpio(GPIO_OPAMP2_VINP_4); + regval |= OPAMP_CSR_VPSEL_PA7; + break; + + default: + return -EINVAL; + } + break; + } +#endif + +#ifdef CONFIG_STM32_OPAMP3 + case 3: + { + switch (priv->vp_sel) + { + case OPAMP3_VPSEL_PB13: + stm32_configgpio(GPIO_OPAMP3_VINP_1); + regval |= OPAMP_CSR_VPSEL_PB13; + break; + + case OPAMP3_VPSEL_PA5: + stm32_configgpio(GPIO_OPAMP3_VINP_2); + regval |= OPAMP_CSR_VPSEL_PA5; + break; + + case OPAMP3_VPSEL_PA1: + stm32_configgpio(GPIO_OPAMP3_VINP_3); + regval |= OPAMP_CSR_VPSEL_PA1; + break; + + case OPAMP3_VPSEL_PB0: + stm32_configgpio(GPIO_OPAMP3_VINP_4); + regval |= OPAMP_CSR_VPSEL_PB0; + break; + + default: + return -EINVAL; + } + break; + } +#endif + +#ifdef CONFIG_STM32_OPAMP4 + case 4: + { + switch (priv->vp_sel) + { + case OPAMP4_VPSEL_PD11: + stm32_configgpio(GPIO_OPAMP4_VINP_1); + regval |= OPAMP_CSR_VPSEL_PD11; + break; + + case OPAMP4_VPSEL_PB11: + stm32_configgpio(GPIO_OPAMP4_VINP_2); + regval |= OPAMP_CSR_VPSEL_PB11; + break; + + case OPAMP4_VPSEL_PA4: + stm32_configgpio(GPIO_OPAMP4_VINP_3); + regval |= OPAMP_CSR_VPSEL_PA4; + break; + + case OPAMP4_VPSEL_PB13: + stm32_configgpio(GPIO_OPAMP4_VINP_4; + regval |= OPAMP_CSR_VPSEL_PB13; + break; + + default: + return -EINVAL; + } + break; + } +#endif + + default: + return -EINVAL; + } + + /* Configure inverting input */ + + switch (index) + { +#ifdef CONFIG_STM32_OPAMP1 + case 1: + { + switch (priv->vm_sel) + { + case OPAMP1_VSEL_PC5: + stm32_configgpio(GPIO_OPAMP1_VINM_1); + regval |= OPAMP_CSR_VMSEL_PC5; + break; + + case OPAMP1_VMSEL_PA3: + stm32_configgpio(GPIO_OPAMP1_VINM_2); + regval |= OPAMP_CSR_VMSEL_PA3; + break; + + case OPAMP1_VMSEL_PGAMODE: + regval |= OPAMP_CSR_VMSEL_PGA; + break; + + case OPAMP1_VMSEL_FOLLOWER: + regval |= OPAMP_CSR_VMSEL_FOLLOWER; + break; + + default: + return -EINVAL; + } + break; + } +#endif + +#ifdef CONFIG_STM32_OPAMP2 + case 2: + { + switch (priv->vm_sel) + { + case OPAMP2_VMSEL_PC5: + stm32_configgpio(GPIO_OPAMP2_VINM_1); + regval |= OPAMP_CSR_VMSEL_PC5; + break; + + case OPAMP2_VMSEL_PA5: + stm32_configgpio(GPIO_OPAMP2_VINM_2); + regval |= OPAMP_CSR_VMSEL_PA5; + break; + + case OPAMP2_VMSEL_PGAMODE: + regval |= OPAMP_CSR_VMSEL_PGA; + break; + + case OPAMP2_VMSEL_FOLLOWER: + regval |= OPAMP_CSR_VMSEL_FOLLOWER; + break; + + default: + return -EINVAL; + } + break; + } +#endif + +#ifdef CONFIG_STM32_OPAMP3 + case 3: + { + switch (priv->vm_sel) + { + case OPAMP3_VMSEL_PB10: + stm32_configgpio(GPIO_OPAMP3_VINM_1); + regval |= OPAMP_CSR_VMSEL_PB10; + break; + + case OPAMP3_VMSEL_PB2: + stm32_configgpio(GPIO_OPAMP3_VINM_2); + regval |= OPAMP_CSR_VMSEL_PB2; + break; + + case OPAMP3_VMSEL_PGAMODE: + regval |= OPAMP_CSR_VMSEL_PGA; + break; + + case OPAMP3_VMSEL_FOLLOWER: + regval |= OPAMP_CSR_VMSEL_FOLLOWER; + break; + + default: + return -EINVAL; + } + break; + } +#endif + +#ifdef CONFIG_STM32_OPAMP4 + case 4: + { + switch (priv->vm_sel) + { + case OPAMP4_VMSEL_PB10: + stm32_configgpio(GPIO_OPAMP4_VINM_1); + regval |= OPAMP_CSR_VMSEL_PB10; + break; + + case OPAMP4_VMSEL_PD8: + stm32_configgpio(GPIO_OPAMP4_VINM_2); + regval |= OPAMP_CSR_VMSEL_PD8; + break; + + case OPAMP4_VMSEL_PGAMODE: + regval |= OPAMP_CSR_VMSEL_PGA; + break; + + case OPAMP4_VMSEL_FOLLOWER: + regval |= OPAMP_CSR_VMSEL_FOLLOWER; + break; + + default: + return -EINVAL; + } + break; + } +#endif + + default: + return -EINVAL; + } + + if (priv->mux == 1) + { + /* Enable Timer controlled Mux mode */ + + regval |= OPAMP_CSR_TCMEN; + + /* Configure non inverting secondary input */ + + switch (index) + { +#ifdef CONFIG_STM32_OPAMP1 + case 1: + { + switch (priv->vps_sel) + { + case OPAMP1_VPSEL_PA7: + stm32_configgpio(GPIO_OPAMP1_VINP_1); + regval |= OPAMP_CSR_VPSSEL_PA7; + break; + + case OPAMP1_VPSEL_PA5: + stm32_configgpio(GPIO_OPAMP1_VINP_2); + regval |= OPAMP_CSR_VPSSEL_PA5; + break; + + case OPAMP1_VPSEL_PA3: + stm32_configgpio(GPIO_OPAMP1_VINP_3); + regval |= OPAMP_CSR_VPSSEL_PA3; + break; + + case OPAMP1_VPSEL_PA1: + stm32_configgpio(GPIO_OPAMP1_VINP_4); + regval |= OPAMP_CSR_VPSSEL_PA1; + break; + + default: + return -EINVAL; + } + break; + } +#endif + +#ifdef CONFIG_STM32_OPAMP2 + case 2: + { + switch (priv->vps_sel) + { +#ifndef CONFIG_STM32_STM32F33XX + case OPAMP2_VPSEL_PD14: + stm32_configgpio(GPIO_OPAMP2_VINP_1); + regval |= OPAMP_CSR_VPSSEL_PD14; + break; +#endif + case OPAMP2_VPSEL_PB14: + stm32_configgpio(GPIO_OPAMP2_VINP_2); + regval |= OPAMP_CSR_VPSSEL_PB14; + break; + + case OPAMP2_VPSEL_PB0: + stm32_configgpio(GPIO_OPAMP2_VINP_3); + regval |= OPAMP_CSR_VPSSEL_PB0; + break; + + case OPAMP2_VPSEL_PA7: + stm32_configgpio(GPIO_OPAMP2_VINP_4); + regval |= OPAMP_CSR_VPSSEL_PA7; + break; + + default: + return -EINVAL; + } + break; + } +#endif + +#ifdef CONFIG_STM32_OPAMP3 + case 3: + { + switch (priv->vps_sel) + { + case OPAMP3_VPSEL_PB13: + stm32_configgpio(GPIO_OPAMP3_VINP_1); + regval |= OPAMP_CSR_VPSSEL_PB13; + break; + + case OPAMP3_VPSEL_PA5: + stm32_configgpio(GPIO_OPAMP3_VINP_2); + regval |= OPAMP_CSR_VPSSEL_PA5; + break; + + case OPAMP3_VPSEL_PA1: + stm32_configgpio(GPIO_OPAMP3_VINP_3); + regval |= OPAMP_CSR_VPSSEL_PA1; + break; + + case OPAMP3_VPSEL_PB0: + stm32_configgpio(GPIO_OPAMP3_VINP_4); + regval |= OPAMP_CSR_VPSSEL_PB0; + break; + + default: + return -EINVAL; + } + break; + } +#endif + +#ifdef CONFIG_STM32_OPAMP4 + case 4: + { + switch (priv->vps_sel) + { + case OPAMP4_VPSEL_PD11: + stm32_configgpio(GPIO_OPAMP4_VINP_1); + regval |= OPAMP_CSR_VPSSEL_PD11; + break; + + case OPAMP4_VPSEL_PB11: + stm32_configgpio(GPIO_OPAMP4_VINP_2); + regval |= OPAMP_CSR_VPSSEL_PB11; + break; + + case OPAMP4_VPSEL_PA4: + stm32_configgpio(GPIO_OPAMP4_VINP_3); + regval |= OPAMP_CSR_VPSSEL_PA4; + break; + + case OPAMP4_VPSEL_PB13: + stm32_configgpio(GPIO_OPAMP4_VINP_4); + regval |= OPAMP_CSR_VPSSEL_PB13; + break; + + default: + return -EINVAL; + } + break; + } +#endif + + default: + return -EINVAL; + } + + /* Configure inverting secondary input */ + + switch (index) + { +#ifdef CONFIG_STM32_OPAMP1 + case 1: + { + switch (priv->vms_sel) + { + case OPAMP1_VSEL_PC5: + stm32_configgpio(GPIO_OPAMP1_VINM_1); + regval &= ~OPAMP_CSR_VMSSEL; + break; + + case OPAMP1_VMSEL_PA3: + stm32_configgpio(GPIO_OPAMP1_VINM_2); + regval |= OPAMP_CSR_VMSSEL; + break; + + default: + return -EINVAL; + } + break; + } +#endif + +#ifdef CONFIG_STM32_OPAMP2 + case 2: + { + switch (priv->vms_sel) + { + case OPAMP2_VMSEL_PC5: + stm32_configgpio(GPIO_OPAMP2_VINM_1); + regval &= ~OPAMP_CSR_VMSSEL; + break; + + case OPAMP2_VMSEL_PA5: + stm32_configgpio(GPIO_OPAMP2_VINM_2); + regval |= OPAMP_CSR_VMSSEL; + break; + + default: + return -EINVAL; + } + break; + } +#endif + +#ifdef CONFIG_STM32_OPAMP3 + case 3: + { + switch (priv->vms_sel) + { + case OPAMP3_VMSEL_PB10: + stm32_configgpio(GPIO_OPAMP3_VINM_1); + regval &= ~OPAMP_CSR_VMSSEL; + break; + + case OPAMP3_VMSEL_PB2: + stm32_configgpio(GPIO_OPAMP3_VINM_2); + regval |= OPAMP_CSR_VMSSEL; + break; + + default: + return -EINVAL; + } + break; + } +#endif + +#ifdef CONFIG_STM32_OPAMP4 + case 4: + { + switch (priv->vms_sel) + { + case OPAMP4_VMSEL_PB10: + stm32_configgpio(GPIO_OPAMP4_VINM_1); + regval &= ~OPAMP_CSR_VMSSEL; + break; + + case OPAMP4_VMSEL_PD8: + stm32_configgpio(GPIO_OPAMP4_VINM_2); + regval |= OPAMP_CSR_VMSSEL; + break; + + default: + return -EINVAL; + } + break; + } +#endif + + default: + return -EINVAL; + } + } + + /* Save CSR register */ + + opamp_putreg_csr(priv, regval); + + /* Configure default gain in PGA mode */ + + stm32_opampgain_set(priv, priv->gain); + + /* Enable OPAMP */ + + stm32_opampenable(priv, true); + + /* TODO: OPAMP user calibration */ + + /* stm32_opampcalibrate(priv); */ + + /* Lock OPAMP if needed */ + + if (priv->lock == OPAMP_LOCK_RO) + { + stm32_opamplock(priv, true); + } + + return OK; +} + +/**************************************************************************** + * Name: stm32_opampenable + * + * Description: + * Enable/disable OPAMP + * + * Input Parameters: + * priv - A reference to the OPAMP structure + * enable - enable/disable flag + * + * Returned Value: + * 0 on success, a negated errno value on failure + * + ****************************************************************************/ + +static int stm32_opampenable(struct stm32_opamp_s *priv, bool enable) +{ + bool lock; + + ainfo("enable: %d\n", enable ? 1 : 0); + + lock = stm32_opamplock_get(priv); + + if (lock) + { + aerr("ERROR: OPAMP locked!\n"); + + return -EPERM; + } + else + { + if (enable) + { + /* Enable the OPAMP */ + + opamp_modify_csr(priv, 0, OPAMP_CSR_OPAMPEN); + } + else + { + /* Disable the OPAMP */ + + opamp_modify_csr(priv, OPAMP_CSR_OPAMPEN, 0); + } + } + + return OK; +} + +/**************************************************************************** + * Name: stm32_opampgain_set + * + * Description: + * Set OPAMP gain + * + * Input Parameters: + * priv - A reference to the OPAMP structure + * gain - OPAMP gain + * + * Returned Value: + * 0 on success, a negated errno value on failure + * + ****************************************************************************/ + +static int stm32_opampgain_set(struct stm32_opamp_s *priv, uint8_t gain) +{ + bool lock; + uint32_t regval = 0; + + lock = stm32_opamplock_get(priv); + + if (lock) + { + aerr("ERROR: OPAMP locked!\n"); + return -EPERM; + } + + regval = opamp_getreg_csr(priv); + + switch (gain) + { + case OPAMP_GAIN_2: + regval |= OPAMP_CSR_PGAGAIN_2; + break; + case OPAMP_GAIN_4: + regval |= OPAMP_CSR_PGAGAIN_4; + break; + case OPAMP_GAIN_8: + regval |= OPAMP_CSR_PGAGAIN_8; + break; + case OPAMP_GAIN_2_VM0: + regval |= OPAMP_CSR_PGAGAIN_2VM0; + break; + case OPAMP_GAIN_4_VM0: + regval |= OPAMP_CSR_PGAGAIN_4VM0; + break; + case OPAMP_GAIN_8_VM0: + regval |= OPAMP_CSR_PGAGAIN_8VM0; + break; + case OPAMP_GAIN_16_VM0: + regval |= OPAMP_CSR_PGAGAIN_16VM0; + break; + case OPAMP_GAIN_2_VM1: + regval |= OPAMP_CSR_PGAGAIN_2VM1; + break; + case OPAMP_GAIN_4_VM1: + regval |= OPAMP_CSR_PGAGAIN_4VM1; + break; + case OPAMP_GAIN_8_VM1: + regval |= OPAMP_CSR_PGAGAIN_8VM1; + break; + case OPAMP_GAIN_16_VM1: + regval |= OPAMP_CSR_PGAGAIN_16VM1; + break; + default: + aerr("ERROR: Unsupported OPAMP gain\n"); + return -EINVAL; + } + + /* Update gain in OPAMP device structure */ + + priv->gain = gain; + + return OK; +} + +#if 0 +static int stm32_opampcalibrate(struct stm32_opamp_s *priv) +{ +#warning "Missing logic" + + return OK; +} +#endif + +/**************************************************************************** + * Name: opamp_shutdown + * + * Description: + * Disable the OPAMP. This method is called when the OPAMP device is + * closed. This method reverses the operation the setup method. + * Works only if OPAMP device is not locked. + * + * Input Parameters: + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void opamp_shutdown(struct opamp_dev_s *dev) +{ +#warning "Missing logic" +} + +/**************************************************************************** + * Name: opamp_setup + * + * Description: + * Configure the OPAMP. This method is called the first time that the OPAMP + * device is opened. This will occur when the port is first opened. + * This setup includes configuring and attaching OPAMP interrupts. + * Interrupts are all disabled upon return. + * + * Input Parameters: + * + * Returned Value: + * + ****************************************************************************/ + +static int opamp_setup(struct opamp_dev_s *dev) +{ +#warning "Missing logic" + return OK; +} + +/**************************************************************************** + * Name: opamp_ioctl + * + * Description: + * All ioctl calls will be routed through this method. + * + * Input Parameters: + * dev - pointer to device structure used by the driver + * cmd - command + * arg - arguments passed with command + * + * Returned Value: + * + ****************************************************************************/ + +static int opamp_ioctl(struct opamp_dev_s *dev, int cmd, + unsigned long arg) +{ +#warning "Missing logic" + return -ENOTTY; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_opampinitialize + * + * Description: + * Initialize the OPAMP. + * + * Input Parameters: + * intf - The OPAMP interface number. + * + * Returned Value: + * Valid OPAMP device structure reference on success; a NULL on failure. + * + * Assumptions: + * 1. Clock to the OPAMP block has enabled, + * 2. Board-specific logic has already configured + * + ****************************************************************************/ + +struct opamp_dev_s *stm32_opampinitialize(int intf) +{ + struct opamp_dev_s *dev; + struct stm32_opamp_s *opamp; + int ret; + + switch (intf) + { +#ifdef CONFIG_STM32_OPAMP1 + case 1: + ainfo("OPAMP1 selected\n"); + dev = &g_opamp1dev; + break; +#endif + +#ifdef CONFIG_STM32_OPAMP2 + case 2: + ainfo("OPAMP2 selected\n"); + dev = &g_opamp2dev; + break; +#endif + +#ifdef CONFIG_STM32_OPAMP3 + case 3: + ainfo("OPAMP3 selected\n"); + dev = &g_opamp3dev; + break; +#endif + +#ifdef CONFIG_STM32_OPAMP4 + case 4: + ainfo("OPAMP4 selected\n"); + dev = &g_opamp4dev; + break; +#endif + + default: + aerr("ERROR: No OPAMP interface defined\n"); + return NULL; + } + + /* Configure selected OPAMP */ + + opamp = dev->ad_priv; + + ret = stm32_opampconfig(opamp); + if (ret < 0) + { + aerr("ERROR: Failed to initialize OPAMP%d: %d\n", intf, ret); + return NULL; + } + + return dev; +} + +#endif /* CONFIG_STM32_STM32F30XX || CONFIG_STM32_STM32F33XX*/ + +#endif /* CONFIG_STM32_OPAMP1 || CONFIG_STM32_OPAMP2 || + * CONFIG_STM32_OPAMP3 || CONFIG_STM32_OPAMP4 + */ + +#endif /* CONFIG_STM32_OPAMP */ diff --git a/arch/arm/src/common/stm32/stm32_opamp_m3m4_v1.h b/arch/arm/src/common/stm32/stm32_opamp_m3m4_v1.h new file mode 100644 index 0000000000000..d45a753223622 --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_opamp_m3m4_v1.h @@ -0,0 +1,219 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_opamp_m3m4_v1.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_OPAMP_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_OPAMP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "chip.h" + +#ifdef CONFIG_STM32_OPAMP + +#if defined(CONFIG_STM32_STM32F30XX) +# error "OPAMP support for STM32F30XX not implemented yet" +#elif defined(CONFIG_STM32_STM32F33XX) +# include "hardware/stm32f33xxx_opamp.h" +#endif + +#include + +/**************************************************************************** + * Pre-processor definitions + ****************************************************************************/ + +/* OPAMP operation mode */ + +#define OPAMP_MODE_STANDALONE 0 +#define OPAMP_MODE_FOLLOWER 1 +#define OPAMP_MODE_PGA 2 + +/* Timer controlled Mux mode */ + +#define OPAMP_MUX_DISABLE 0 +#define OPAMP_MUX_ENABLE 1 + +/* User calibration */ + +#define OPAMP_USERCAL_DISABLE 0 +#define OPAMP_USERCAL_ENABLE 1 + +/* Default configuration */ + +#define OPAMP_MODE_DEFAULT OPAMP_MODE_STANDALONE /* Standalone mode */ +#define OPAMP_MUX_DEFAULT OPAMP_MUX_DISABLE /* MUX disabled */ +#define OPAMP_USERCAL_DEFAULT OPAMP_USERCAL_DISABLE /* User calibration disabled */ +#define OPAMP_GAIN_DEFAULT OPAMP_GAIN_2 /* Gain in PGA mode = 2 */ +#define OPAMP_LOCK_DEFAULT OPAMP_LOCK_RW /* Do not lock CSR register */ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/* CSR register lock state */ + +enum stm32_opamp_lock_e +{ + OPAMP_LOCK_RW, + OPAMP_LOCK_RO +}; + +/* Gain in PGA mode */ + +enum stm32_opamp_gain_e +{ + OPAMP_GAIN_2, + OPAMP_GAIN_4, + OPAMP_GAIN_8, + OPAMP_GAIN_2_VM0, + OPAMP_GAIN_4_VM0, + OPAMP_GAIN_8_VM0, + OPAMP_GAIN_16_VM0, + OPAMP_GAIN_2_VM1, + OPAMP_GAIN_4_VM1, + OPAMP_GAIN_8_VM1, + OPAMP_GAIN_16_VM1 +}; + +/* Input selection and secondary input selection use the same GPIOs */ + +#ifdef CONFIG_STM32_OPAMP1 +enum stm32_opamp1_vpsel_e +{ + OPAMP1_VPSEL_PA7, + OPAMP1_VPSEL_PA5, + OPAMP1_VPSEL_PA3, + OPAMP1_VPSEL_PA1 +}; + +enum stm32_opamp1_vmsel_e +{ + OPAMP1_VMSEL_PC5, + OPAMP1_VMSEL_PA3, + OPAMP1_VMSEL_PGAMODE, + OPAMP1_VMSEL_FOLLOWER, +}; +#endif + +#ifdef CONFIG_STM32_OPAMP2 +enum stm32_opamp2_vpsel_e +{ +#ifndef CONFIG_STM32_STM32F33XX + /* TODO: STM32F303xB/C and STM32F358C devices only */ + + OPAMP2_VPSEL_PD14, +#endif + OPAMP2_VPSEL_PB14, + OPAMP2_VPSEL_PB0, + OPAMP2_VPSEL_PA7 +}; + +enum stm32_opamp2_vmsel_e +{ + OPAMP2_VMSEL_PC5, + OPAMP2_VMSEL_PA5, + OPAMP2_VMSEL_PGAMODE, + OPAMP2_VMSEL_FOLLOWER +}; +#endif + +#ifdef CONFIG_STM32_OPAMP3 +enum stm32_opamp3_vpsel_e +{ + OPAMP3_VPSEL_PB13, + OPAMP3_VPSEL_PA5, + OPAMP3_VPSEL_PA1, + OPAMP3_VPSEL_PB0 +}; + +enum stm32_opamp3_vmsel_e +{ + OPAMP3_VMSEL_PB10, + OPAMP3_VMSEL_PB2, + OPAMP3_VMSEL_PGAMODE, + OPAMP3_VMSEL_FOLLOWER +}; +#endif + +#ifdef CONFIG_STM32_OPAMP4 +enum stm32_opamp4_vpsel_e +{ + OPAMP4_VPSEL_PD11, + OPAMP4_VPSEL_PB11, + OPAMP4_VPSEL_PA4, + OPAMP4_VPSEL_PB13 +}; + +enum stm32_opamp4_vmsel_e +{ + OPAMP4_VMSEL_PB10, + OPAMP4_VMSEL_PD8, + OPAMP4_VMSEL_PGAMODE, + OPAMP4_VMSEL_FOLLOWER +}; +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#ifndef __ASSEMBLY__ +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Name: stm32_opampinitialize + * + * Description: + * Initialize the OPAMP. + * + * Input Parameters: + * intf - The OPAMP interface number. + * + * Returned Value: + * Valid OPAMP device structure reference on success; a NULL on failure. + * + * Assumptions: + * 1. Clock to the OPAMP block has enabled, + * 2. Board-specific logic has already configured + * + ****************************************************************************/ + +struct opamp_dev_s *stm32_opampinitialize(int intf); + +#undef EXTERN +#ifdef __cplusplus +} +#endif +#endif /* __ASSEMBLY__ */ + +#endif /* CONFIG_STM32_OPAMP */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_OPAMP_H */ diff --git a/arch/arm/src/stm32/stm32_otgfs.h b/arch/arm/src/common/stm32/stm32_otgfs.h similarity index 95% rename from arch/arm/src/stm32/stm32_otgfs.h rename to arch/arm/src/common/stm32/stm32_otgfs.h index 42287bc2120ea..b7cf5962ed05d 100644 --- a/arch/arm/src/stm32/stm32_otgfs.h +++ b/arch/arm/src/common/stm32/stm32_otgfs.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_otgfs.h + * arch/arm/src/common/stm32/stm32_otgfs.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_STM32_OTGFS_H -#define __ARCH_ARM_SRC_STM32_STM32_OTGFS_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_OTGFS_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_OTGFS_H /**************************************************************************** * Included Files @@ -110,4 +110,4 @@ void stm32_usbsuspend(struct usbdev_s *dev, bool resume); #endif /* __ASSEMBLY__ */ #endif /* CONFIG_STM32_OTGFS */ -#endif /* __ARCH_ARM_SRC_STM32_STM32_OTGFS_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_OTGFS_H */ diff --git a/arch/arm/src/common/stm32/stm32_otgfsdev_m3m4_v1.c b/arch/arm/src/common/stm32/stm32_otgfsdev_m3m4_v1.c new file mode 100644 index 0000000000000..af02d027c98cd --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_otgfsdev_m3m4_v1.c @@ -0,0 +1,5871 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_otgfsdev_m3m4_v1.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32_otgfs.h" +#include "stm32_rcc.h" + +#if defined(CONFIG_USBDEV) && (defined(CONFIG_STM32_OTGFS)) +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +#ifndef CONFIG_USBDEV_EP0_MAXSIZE +# define CONFIG_USBDEV_EP0_MAXSIZE 64 +#endif + +#ifndef CONFIG_USBDEV_SETUP_MAXDATASIZE +# define CONFIG_USBDEV_SETUP_MAXDATASIZE CONFIG_USBDEV_EP0_MAXSIZE +#endif + +#ifndef CONFIG_USBDEV_MAXPOWER +# define CONFIG_USBDEV_MAXPOWER 100 /* mA */ +#endif + +#ifndef CONFIG_DEBUG_USB_INFO +# undef CONFIG_STM32_USBDEV_REGDEBUG +#endif + +/* There is 1.25Kb of FIFO memory. The default partitions this memory + * so that there is a TxFIFO allocated for each endpoint and with more + * memory provided for the common RxFIFO. A more knowledge-able + * configuration would not allocate any TxFIFO space to OUT endpoints. + */ + +#ifndef CONFIG_USBDEV_RXFIFO_SIZE +# define CONFIG_USBDEV_RXFIFO_SIZE 512 +#endif + +#ifndef CONFIG_USBDEV_EP0_TXFIFO_SIZE +# define CONFIG_USBDEV_EP0_TXFIFO_SIZE 192 +#endif + +#ifndef CONFIG_USBDEV_EP1_TXFIFO_SIZE +# define CONFIG_USBDEV_EP1_TXFIFO_SIZE 192 +#endif + +#ifndef CONFIG_USBDEV_EP2_TXFIFO_SIZE +# define CONFIG_USBDEV_EP2_TXFIFO_SIZE 192 +#endif + +#ifndef CONFIG_USBDEV_EP3_TXFIFO_SIZE +# define CONFIG_USBDEV_EP3_TXFIFO_SIZE 192 +#endif + +#if (CONFIG_USBDEV_RXFIFO_SIZE + \ + CONFIG_USBDEV_EP0_TXFIFO_SIZE + CONFIG_USBDEV_EP1_TXFIFO_SIZE + \ + CONFIG_USBDEV_EP2_TXFIFO_SIZE + CONFIG_USBDEV_EP3_TXFIFO_SIZE) > 1280 +# error "FIFO allocations exceed FIFO memory size" +#endif + +/* The actual FIFO addresses that we use must be aligned to 4-byte + * boundaries; + * FIFO sizes must be provided in units of 32-bit words. + */ + +#define STM32_RXFIFO_BYTES ((CONFIG_USBDEV_RXFIFO_SIZE + 3) & ~3) +#define STM32_RXFIFO_WORDS ((CONFIG_USBDEV_RXFIFO_SIZE + 3) >> 2) + +#define STM32_EP0_TXFIFO_BYTES ((CONFIG_USBDEV_EP0_TXFIFO_SIZE + 3) & ~3) +#define STM32_EP0_TXFIFO_WORDS ((CONFIG_USBDEV_EP0_TXFIFO_SIZE + 3) >> 2) + +#if STM32_EP0_TXFIFO_WORDS < 16 || STM32_EP0_TXFIFO_WORDS > 256 +# error "CONFIG_USBDEV_EP0_TXFIFO_SIZE is out of range" +#endif + +#define STM32_EP1_TXFIFO_BYTES ((CONFIG_USBDEV_EP1_TXFIFO_SIZE + 3) & ~3) +#define STM32_EP1_TXFIFO_WORDS ((CONFIG_USBDEV_EP1_TXFIFO_SIZE + 3) >> 2) + +#if STM32_EP1_TXFIFO_WORDS < 16 +# error "CONFIG_USBDEV_EP1_TXFIFO_SIZE is out of range" +#endif + +#define STM32_EP2_TXFIFO_BYTES ((CONFIG_USBDEV_EP2_TXFIFO_SIZE + 3) & ~3) +#define STM32_EP2_TXFIFO_WORDS ((CONFIG_USBDEV_EP2_TXFIFO_SIZE + 3) >> 2) + +#if STM32_EP2_TXFIFO_WORDS < 16 +# error "CONFIG_USBDEV_EP2_TXFIFO_SIZE is out of range" +#endif + +#define STM32_EP3_TXFIFO_BYTES ((CONFIG_USBDEV_EP3_TXFIFO_SIZE + 3) & ~3) +#define STM32_EP3_TXFIFO_WORDS ((CONFIG_USBDEV_EP3_TXFIFO_SIZE + 3) >> 2) + +#if STM32_EP3_TXFIFO_WORDS < 16 +# error "CONFIG_USBDEV_EP3_TXFIFO_SIZE is out of range" +#endif + +#if defined(CONFIG_STM32_STM32F446) || defined(CONFIG_STM32_STM32F469) +# define OTGFS_GINT_RESETS (OTGFS_GINT_USBRST | OTGFS_GINT_RSTDET) +# define OTGFS_GINT_RESERVED (OTGFS_GINT_RES89 | OTGFS_GINT_RES16 | \ + OTGFS_GINTMSK_EPMISM | OTGFS_GINT_RES22) + +# define OTGFS_GINT_RC_W1 (OTGFS_GINT_MMIS | \ + OTGFS_GINT_SOF | \ + OTGFS_GINT_ESUSP | \ + OTGFS_GINT_USBSUSP | \ + OTGFS_GINT_USBRST | \ + OTGFS_GINT_ENUMDNE | \ + OTGFS_GINT_ISOODRP | \ + OTGFS_GINT_EOPF | \ + OTGFS_GINT_IISOIXFR | \ + OTGFS_GINT_IISOOXFR | \ + OTGFS_GINT_RSTDET | \ + OTGFS_GINT_LPMINT | \ + OTGFS_GINT_CIDSCHG | \ + OTGFS_GINT_DISC | \ + OTGFS_GINT_SRQ | \ + OTGFS_GINT_WKUP) +#else +# define OTGFS_GINT_RESETS OTGFS_GINT_USBRST +# define OTGFS_GINT_RESERVED (OTGFS_GINT_RES89 | OTGFS_GINT_RES16 | \ + OTGFS_GINTMSK_EPMISM | OTGFS_GINT_RES2223 | \ + OTGFS_GINT_RES27) + +# define OTGFS_GINT_RC_W1 (OTGFS_GINT_MMIS | \ + OTGFS_GINT_SOF | \ + OTGFS_GINT_ESUSP | \ + OTGFS_GINT_USBSUSP | \ + OTGFS_GINT_USBRST | \ + OTGFS_GINT_ENUMDNE | \ + OTGFS_GINT_ISOODRP | \ + OTGFS_GINT_EOPF | \ + OTGFS_GINT_IISOIXFR | \ + OTGFS_GINT_IISOOXFR | \ + OTGFS_GINT_CIDSCHG | \ + OTGFS_GINT_DISC | \ + OTGFS_GINT_SRQ | \ + OTGFS_GINT_WKUP) +#endif + +/* Debug ********************************************************************/ + +/* Trace error codes */ + +#define STM32_TRACEERR_ALLOCFAIL 0x01 +#define STM32_TRACEERR_BADCLEARFEATURE 0x02 +#define STM32_TRACEERR_BADDEVGETSTATUS 0x03 +#define STM32_TRACEERR_BADEPNO 0x04 +#define STM32_TRACEERR_BADEPGETSTATUS 0x05 +#define STM32_TRACEERR_BADGETCONFIG 0x06 +#define STM32_TRACEERR_BADGETSETDESC 0x07 +#define STM32_TRACEERR_BADGETSTATUS 0x08 +#define STM32_TRACEERR_BADSETADDRESS 0x09 +#define STM32_TRACEERR_BADSETCONFIG 0x0a +#define STM32_TRACEERR_BADSETFEATURE 0x0b +#define STM32_TRACEERR_BADTESTMODE 0x0c +#define STM32_TRACEERR_BINDFAILED 0x0d +#define STM32_TRACEERR_DISPATCHSTALL 0x0e +#define STM32_TRACEERR_DRIVER 0x0f +#define STM32_TRACEERR_DRIVERREGISTERED 0x10 +#define STM32_TRACEERR_EP0NOSETUP 0x11 +#define STM32_TRACEERR_EP0SETUPSTALLED 0x12 +#define STM32_TRACEERR_EPINNULLPACKET 0x13 +#define STM32_TRACEERR_EPINUNEXPECTED 0x14 +#define STM32_TRACEERR_EPOUTNULLPACKET 0x15 +#define STM32_TRACEERR_EPOUTUNEXPECTED 0x16 +#define STM32_TRACEERR_INVALIDCTRLREQ 0x17 +#define STM32_TRACEERR_INVALIDPARMS 0x18 +#define STM32_TRACEERR_IRQREGISTRATION 0x19 +#define STM32_TRACEERR_NOEP 0x1a +#define STM32_TRACEERR_NOTCONFIGURED 0x1b +#define STM32_TRACEERR_EPOUTQEMPTY 0x1c +#define STM32_TRACEERR_EPINREQEMPTY 0x1d +#define STM32_TRACEERR_NOOUTSETUP 0x1e +#define STM32_TRACEERR_POLLTIMEOUT 0x1f + +/* Trace interrupt codes */ + +#define STM32_TRACEINTID_USB 1 /* USB Interrupt entry/exit */ +#define STM32_TRACEINTID_INTPENDING 2 /* On each pass through the loop */ + +#define STM32_TRACEINTID_EPOUT (10 + 0) /* First level interrupt decode */ +#define STM32_TRACEINTID_EPIN (10 + 1) +#define STM32_TRACEINTID_MISMATCH (10 + 2) +#define STM32_TRACEINTID_WAKEUP (10 + 3) +#define STM32_TRACEINTID_SUSPEND (10 + 4) +#define STM32_TRACEINTID_SOF (10 + 5) +#define STM32_TRACEINTID_RXFIFO (10 + 6) +#define STM32_TRACEINTID_DEVRESET (10 + 7) +#define STM32_TRACEINTID_ENUMDNE (10 + 8) +#define STM32_TRACEINTID_IISOIXFR (10 + 9) +#define STM32_TRACEINTID_IISOOXFR (10 + 10) +#define STM32_TRACEINTID_SRQ (10 + 11) +#define STM32_TRACEINTID_OTG (10 + 12) + +#define STM32_TRACEINTID_EPOUT_XFRC (40 + 0) /* EPOUT second level decode */ +#define STM32_TRACEINTID_EPOUT_EPDISD (40 + 1) +#define STM32_TRACEINTID_EPOUT_SETUP (40 + 2) +#define STM32_TRACEINTID_DISPATCH (40 + 3) + +#define STM32_TRACEINTID_GETSTATUS (50 + 0) /* EPOUT third level decode */ +#define STM32_TRACEINTID_EPGETSTATUS (50 + 1) +#define STM32_TRACEINTID_DEVGETSTATUS (50 + 2) +#define STM32_TRACEINTID_IFGETSTATUS (50 + 3) +#define STM32_TRACEINTID_CLEARFEATURE (50 + 4) +#define STM32_TRACEINTID_SETFEATURE (50 + 5) +#define STM32_TRACEINTID_SETADDRESS (50 + 6) +#define STM32_TRACEINTID_GETSETDESC (50 + 7) +#define STM32_TRACEINTID_GETCONFIG (50 + 8) +#define STM32_TRACEINTID_SETCONFIG (50 + 9) +#define STM32_TRACEINTID_GETSETIF (50 + 10) +#define STM32_TRACEINTID_SYNCHFRAME (50 + 11) + +#define STM32_TRACEINTID_EPIN_XFRC (70 + 0) /* EPIN second level decode */ +#define STM32_TRACEINTID_EPIN_TOC (70 + 1) +#define STM32_TRACEINTID_EPIN_ITTXFE (70 + 2) +#define STM32_TRACEINTID_EPIN_EPDISD (70 + 3) +#define STM32_TRACEINTID_EPIN_TXFE (70 + 4) + +#define STM32_TRACEINTID_EPIN_EMPWAIT (80 + 0) /* EPIN second level decode */ + +#define STM32_TRACEINTID_OUTNAK (90 + 0) /* RXFLVL second level decode */ +#define STM32_TRACEINTID_OUTRECVD (90 + 1) +#define STM32_TRACEINTID_OUTDONE (90 + 2) +#define STM32_TRACEINTID_SETUPDONE (90 + 3) +#define STM32_TRACEINTID_SETUPRECVD (90 + 4) + +/* Endpoints ****************************************************************/ + +/* Odd physical endpoint numbers are IN; even are OUT */ + +#define STM32_EPPHYIN2LOG(epphy) ((uint8_t)(epphy)|USB_DIR_IN) +#define STM32_EPPHYOUT2LOG(epphy) ((uint8_t)(epphy)|USB_DIR_OUT) + +/* Endpoint 0 */ + +#define EP0 (0) + +/* The set of all endpoints available to the class implementation (1-3) */ + +#define STM32_EP_AVAILABLE (0x0e) /* All available endpoints */ + +/* Maximum packet sizes for full speed endpoints */ + +#define STM32_MAXPACKET (64) /* Max packet size (1-64) */ + +/* Delays *******************************************************************/ + +#define STM32_READY_DELAY 200000 +#define STM32_FLUSH_DELAY 200000 + +/* Request queue operations *************************************************/ + +#define stm32_rqempty(ep) ((ep)->head == NULL) +#define stm32_rqpeek(ep) ((ep)->head) + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/* Overall device state */ + +enum stm32_devstate_e +{ + DEVSTATE_DEFAULT = 0, /* Power-up, unconfigured state. This state simply + * means that the device is not yet been given an + * address. + * SET: At initialization, uninitialization, + * reset, and whenever the device address + * is set to zero + * TESTED: Never + */ + DEVSTATE_ADDRESSED, /* Device address has been assigned, not no + * configuration has yet been selected. + * SET: When either a non-zero device address + * is first assigned or when the device + * is unconfigured (with configuration == 0) + * TESTED: never + */ + DEVSTATE_CONFIGURED, /* Address assigned and configured: + * SET: When the device has been addressed and + * an non-zero configuration has been selected. + * TESTED: In many places to assure that the USB device + * has been properly configured by the host. + */ +}; + +/* Endpoint 0 states */ + +enum stm32_ep0state_e +{ + EP0STATE_IDLE = 0, /* Idle State, leave on receiving a SETUP packet or + * epsubmit: + * SET: In stm32_epin() and stm32_epout() when + * we revert from request processing to + * SETUP processing. + * TESTED: Never + */ + EP0STATE_SETUP_OUT, /* OUT SETUP packet received. Waiting for the DATA + * OUT phase of SETUP Packet to complete before + * processing a SETUP command (without a USB request): + * SET: Set in stm32_rxinterrupt() when SETUP OUT + * packet is received. + * TESTED: In stm32_ep0out_receive() + */ + EP0STATE_SETUP_READY, /* IN SETUP packet received -OR- OUT SETUP packet and + * accompanying data have been received. Processing + * of SETUP command will happen soon. + * SET: (1) stm32_ep0out_receive() when the OUT + * SETUP data phase completes, or (2) + * stm32_rxinterrupt() when an IN SETUP is + * packet received. + * TESTED: Tested in stm32_epout_interrupt() when + * SETUP phase is done to see if the SETUP + * command is ready to be processed. Also + * tested in stm32_ep0out_setup() just to + * double-check that we have a SETUP request + * and any accompanying data. + */ + EP0STATE_SETUP_PROCESS, /* SETUP Packet is being processed by stm32_ep0out_setup(): + * SET: When SETUP packet received in EP0 OUT + * TESTED: Never + */ + EP0STATE_SETUPRESPONSE, /* Short SETUP response write (without a USB request): + * SET: When SETUP response is sent by + * stm32_ep0in_setupresponse() + * TESTED: Never + */ + EP0STATE_DATA_IN, /* Waiting for data out stage (with a USB request): + * SET: In stm32_epin_request() when a write + * request is processed on EP0. + * TESTED: In stm32_epin() to see if we should + * revert to SETUP processing. + */ + EP0STATE_DATA_OUT /* Waiting for data in phase to complete ( with a + * USB request) + * SET: In stm32_epout_request() when a read + * request is processed on EP0. + * TESTED: In stm32_epout() to see if we should + * revert to SETUP processing + */ +}; + +/* Parsed control request */ + +struct stm32_ctrlreq_s +{ + uint8_t type; + uint8_t req; + uint16_t value; + uint16_t index; + uint16_t len; +}; + +/* A container for a request so that the request may be retained in a list */ + +struct stm32_req_s +{ + struct usbdev_req_s req; /* Standard USB request */ + struct stm32_req_s *flink; /* Supports a singly linked list */ +}; + +/* This is the internal representation of an endpoint */ + +struct stm32_ep_s +{ + /* Common endpoint fields. This must be the first thing defined in the + * structure so that it is possible to simply cast from struct usbdev_ep_s + * to struct stm32_ep_s. + */ + + struct usbdev_ep_s ep; /* Standard endpoint structure */ + + /* STM32-specific fields */ + + struct stm32_usbdev_s *dev; /* Reference to private driver data */ + struct stm32_req_s *head; /* Request list for this endpoint */ + struct stm32_req_s *tail; + uint8_t epphy; /* Physical EP address */ + uint8_t eptype:2; /* Endpoint type */ + uint8_t active:1; /* 1: A request is being processed */ + uint8_t stalled:1; /* 1: Endpoint is stalled */ + uint8_t isin:1; /* 1: IN Endpoint */ + uint8_t odd:1; /* 1: Odd frame */ + uint8_t zlp:1; /* 1: Transmit a zero-length-packet (IN EPs only) */ +}; + +/* This structure retains the state of the USB device controller */ + +struct stm32_usbdev_s +{ + /* Common device fields. This must be the first thing defined in the + * structure so that it is possible to simply cast from struct usbdev_s + * to struct stm32_usbdev_s. + */ + + struct usbdev_s usbdev; + + /* The bound device class driver */ + + struct usbdevclass_driver_s *driver; + + /* STM32-specific fields */ + + uint8_t stalled:1; /* 1: Protocol stalled */ + uint8_t selfpowered:1; /* 1: Device is self powered */ + uint8_t addressed:1; /* 1: Peripheral address has been set */ + uint8_t configured:1; /* 1: Class driver has been configured */ + uint8_t wakeup:1; /* 1: Device remote wake-up */ + uint8_t dotest:1; /* 1: Test mode selected */ + + uint8_t devstate:4; /* See enum stm32_devstate_e */ + uint8_t ep0state:4; /* See enum stm32_ep0state_e */ + uint8_t testmode:4; /* Selected test mode */ + uint8_t epavail[2]; /* Bitset of available OUT/IN endpoints */ + + /* E0 SETUP data buffering. + * + * ctrlreq: + * The 8-byte SETUP request is received on the EP0 OUT endpoint and is + * saved. + * + * ep0data + * For OUT SETUP requests, the SETUP data phase must also complete before + * the SETUP command can be processed. The pack receipt logic will save + * the accompanying EP0 OUT data in ep0data[] before the SETUP command is + * processed. The data length is specified in the SETUP packet payload, + * and can consist of multiple DATA packets. + * + * For IN SETUP requests, the DATA phase will occur AFTER the SETUP + * control request is processed. In that case, ep0data[] may be used as + * the response buffer. + * + * ep0datlen + * Length of data received part of OUT SETUP request. During transfer + * it is the total number of bytes received, which can be more than + * CONFIG_USBDEV_SETUP_MAXDATASIZE. The value is clamped to valid length + * of data in ep0data[] before SETUP OUT handler is called. Bytes that + * exceed the maximum length are discarded, but must be read out of the + * USB peripheral FIFO. + */ + + struct usb_ctrlreq_s ctrlreq; + uint8_t ep0data[CONFIG_USBDEV_SETUP_MAXDATASIZE]; + uint16_t ep0datlen; + + /* The endpoint lists */ + + struct stm32_ep_s epin[STM32_NENDPOINTS]; + struct stm32_ep_s epout[STM32_NENDPOINTS]; +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/* Register operations ******************************************************/ + +#ifdef CONFIG_STM32_USBDEV_REGDEBUG +static uint32_t stm32_getreg(uint32_t addr); +static void stm32_putreg(uint32_t val, uint32_t addr); +#else +# define stm32_getreg(addr) getreg32(addr) +# define stm32_putreg(val,addr) putreg32(val,addr) +#endif + +/* Request queue operations *************************************************/ + +static struct stm32_req_s *stm32_req_remfirst( + struct stm32_ep_s *privep); +static bool stm32_req_addlast(struct stm32_ep_s *privep, + struct stm32_req_s *req); + +/* Low level data transfers and request operations **************************/ + +/* Special endpoint 0 data transfer logic */ + +static void stm32_ep0in_setupresponse(struct stm32_usbdev_s *priv, + uint8_t *data, uint32_t nbytes); +static inline void stm32_ep0in_transmitzlp(struct stm32_usbdev_s *priv); +static void stm32_ep0in_activate(void); + +static void stm32_ep0out_ctrlsetup(struct stm32_usbdev_s *priv); + +/* IN request and TxFIFO handling */ + +static void stm32_txfifo_write(struct stm32_ep_s *privep, + uint8_t *buf, int nbytes); +static void stm32_epin_transfer(struct stm32_ep_s *privep, + uint8_t *buf, int nbytes); +static void stm32_epin_request(struct stm32_usbdev_s *priv, + struct stm32_ep_s *privep); + +/* OUT request and RxFIFO handling */ + +static void stm32_rxfifo_read(struct stm32_ep_s *privep, + uint8_t *dest, uint16_t len); +static void stm32_rxfifo_discard(struct stm32_ep_s *privep, + int len); +static void stm32_epout_complete(struct stm32_usbdev_s *priv, + struct stm32_ep_s *privep); +static inline void stm32_ep0out_receive(struct stm32_ep_s *privep, + int bcnt); +static inline void stm32_epout_receive(struct stm32_ep_s *privep, + int bcnt); +static void stm32_epout_request(struct stm32_usbdev_s *priv, + struct stm32_ep_s *privep); + +/* General request handling */ + +static void stm32_ep_flush(struct stm32_ep_s *privep); +static void stm32_req_complete(struct stm32_ep_s *privep, + int16_t result); +static void stm32_req_cancel(struct stm32_ep_s *privep, + int16_t status); + +/* Interrupt handling *******************************************************/ + +static struct stm32_ep_s *stm32_ep_findbyaddr( + struct stm32_usbdev_s *priv, + uint16_t eplog); +static int stm32_req_dispatch(struct stm32_usbdev_s *priv, + const struct usb_ctrlreq_s *ctrl); +static void stm32_usbreset(struct stm32_usbdev_s *priv); + +/* Second level OUT endpoint interrupt processing */ + +static inline void stm32_ep0out_testmode(struct stm32_usbdev_s *priv, + uint16_t index); +static inline void stm32_ep0out_stdrequest(struct stm32_usbdev_s *priv, + struct stm32_ctrlreq_s *ctrlreq); +static inline void stm32_ep0out_setup(struct stm32_usbdev_s *priv); +static inline void stm32_epout(struct stm32_usbdev_s *priv, + uint8_t epno); +static inline void stm32_epout_interrupt(struct stm32_usbdev_s *priv); + +/* Second level IN endpoint interrupt processing */ + +static inline void stm32_epin_runtestmode(struct stm32_usbdev_s *priv); +static inline void stm32_epin(struct stm32_usbdev_s *priv, uint8_t epno); +static inline void stm32_epin_txfifoempty(struct stm32_usbdev_s *priv, + int epno); +static inline void stm32_epin_interrupt(struct stm32_usbdev_s *priv); + +/* Other second level interrupt processing */ + +static inline void stm32_resumeinterrupt(struct stm32_usbdev_s *priv); +static inline void stm32_suspendinterrupt(struct stm32_usbdev_s *priv); +static inline void stm32_rxinterrupt(struct stm32_usbdev_s *priv); +static inline void stm32_enuminterrupt(struct stm32_usbdev_s *priv); +#ifdef CONFIG_USBDEV_ISOCHRONOUS +static inline void stm32_isocininterrupt(struct stm32_usbdev_s *priv); +static inline void stm32_isocoutinterrupt(struct stm32_usbdev_s *priv); +#endif +#ifdef CONFIG_USBDEV_VBUSSENSING +static inline void stm32_sessioninterrupt(struct stm32_usbdev_s *priv); +static inline void stm32_otginterrupt(struct stm32_usbdev_s *priv); +#endif + +/* First level interrupt processing */ + +static int stm32_usbinterrupt(int irq, void *context, + void *arg); + +/* Endpoint operations ******************************************************/ + +/* Global OUT NAK controls */ + +static void stm32_enablegonak(struct stm32_ep_s *privep); +static void stm32_disablegonak(struct stm32_ep_s *privep); + +/* Endpoint configuration */ + +static int stm32_epout_configure(struct stm32_ep_s *privep, + uint8_t eptype, uint16_t maxpacket); +static int stm32_epin_configure(struct stm32_ep_s *privep, + uint8_t eptype, uint16_t maxpacket); +static int stm32_ep_configure(struct usbdev_ep_s *ep, + const struct usb_epdesc_s *desc, bool last); +static void stm32_ep0_configure(struct stm32_usbdev_s *priv); + +/* Endpoint disable */ + +static void stm32_epout_disable(struct stm32_ep_s *privep); +static void stm32_epin_disable(struct stm32_ep_s *privep); +static int stm32_ep_disable(struct usbdev_ep_s *ep); + +/* Endpoint request management */ + +static struct usbdev_req_s *stm32_ep_allocreq( + struct usbdev_ep_s *ep); +static void stm32_ep_freereq(struct usbdev_ep_s *ep, + struct usbdev_req_s *); + +/* Endpoint buffer management */ + +#ifdef CONFIG_USBDEV_DMA +static void *stm32_ep_allocbuffer(struct usbdev_ep_s *ep, + uint16_t bytes); +static void stm32_ep_freebuffer(struct usbdev_ep_s *ep, + void *buf); +#endif + +/* Endpoint request submission */ + +static int stm32_ep_submit(struct usbdev_ep_s *ep, + struct usbdev_req_s *req); + +/* Endpoint request cancellation */ + +static int stm32_ep_cancel(struct usbdev_ep_s *ep, + struct usbdev_req_s *req); + +/* Stall handling */ + +static int stm32_epout_setstall(struct stm32_ep_s *privep); +static int stm32_epin_setstall(struct stm32_ep_s *privep); +static int stm32_ep_setstall(struct stm32_ep_s *privep); +static int stm32_ep_clrstall(struct stm32_ep_s *privep); +static int stm32_ep_stall(struct usbdev_ep_s *ep, bool resume); +static void stm32_ep0_stall(struct stm32_usbdev_s *priv); + +/* Endpoint allocation */ + +static struct usbdev_ep_s *stm32_ep_alloc(struct usbdev_s *dev, + uint8_t epno, bool in, uint8_t eptype); +static void stm32_ep_free(struct usbdev_s *dev, + struct usbdev_ep_s *ep); + +/* USB device controller operations *****************************************/ + +static int stm32_getframe(struct usbdev_s *dev); +static int stm32_wakeup(struct usbdev_s *dev); +static int stm32_selfpowered(struct usbdev_s *dev, bool selfpowered); +static int stm32_pullup(struct usbdev_s *dev, bool enable); +static void stm32_setaddress(struct stm32_usbdev_s *priv, + uint16_t address); +static int stm32_txfifo_flush(uint32_t txfnum); +static int stm32_rxfifo_flush(void); + +/* Initialization ***********************************************************/ + +static void stm32_swinitialize(struct stm32_usbdev_s *priv); +static void stm32_hwinitialize(struct stm32_usbdev_s *priv); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* Since there is only a single USB interface, all status information can be + * be simply retained in a single global instance. + */ + +static struct stm32_usbdev_s g_otgfsdev; + +static const struct usbdev_epops_s g_epops = +{ + .configure = stm32_ep_configure, + .disable = stm32_ep_disable, + .allocreq = stm32_ep_allocreq, + .freereq = stm32_ep_freereq, +#ifdef CONFIG_USBDEV_DMA + .allocbuffer = stm32_ep_allocbuffer, + .freebuffer = stm32_ep_freebuffer, +#endif + .submit = stm32_ep_submit, + .cancel = stm32_ep_cancel, + .stall = stm32_ep_stall, +}; + +static const struct usbdev_ops_s g_devops = +{ + .allocep = stm32_ep_alloc, + .freeep = stm32_ep_free, + .getframe = stm32_getframe, + .wakeup = stm32_wakeup, + .selfpowered = stm32_selfpowered, + .pullup = stm32_pullup, +}; + +/* Device error strings that may be enabled for more descriptive USB trace + * output. + */ + +#ifdef CONFIG_USBDEV_TRACE_STRINGS +const struct trace_msg_t g_usb_trace_strings_deverror[] = +{ + TRACE_STR(STM32_TRACEERR_ALLOCFAIL), + TRACE_STR(STM32_TRACEERR_BADCLEARFEATURE), + TRACE_STR(STM32_TRACEERR_BADDEVGETSTATUS), + TRACE_STR(STM32_TRACEERR_BADEPNO), + TRACE_STR(STM32_TRACEERR_BADEPGETSTATUS), + TRACE_STR(STM32_TRACEERR_BADGETCONFIG), + TRACE_STR(STM32_TRACEERR_BADGETSETDESC), + TRACE_STR(STM32_TRACEERR_BADGETSTATUS), + TRACE_STR(STM32_TRACEERR_BADSETADDRESS), + TRACE_STR(STM32_TRACEERR_BADSETCONFIG), + TRACE_STR(STM32_TRACEERR_BADSETFEATURE), + TRACE_STR(STM32_TRACEERR_BADTESTMODE), + TRACE_STR(STM32_TRACEERR_BINDFAILED), + TRACE_STR(STM32_TRACEERR_DISPATCHSTALL), + TRACE_STR(STM32_TRACEERR_DRIVER), + TRACE_STR(STM32_TRACEERR_DRIVERREGISTERED), + TRACE_STR(STM32_TRACEERR_EP0NOSETUP), + TRACE_STR(STM32_TRACEERR_EP0SETUPSTALLED), + TRACE_STR(STM32_TRACEERR_EPINNULLPACKET), + TRACE_STR(STM32_TRACEERR_EPINUNEXPECTED), + TRACE_STR(STM32_TRACEERR_EPOUTNULLPACKET), + TRACE_STR(STM32_TRACEERR_EPOUTUNEXPECTED), + TRACE_STR(STM32_TRACEERR_INVALIDCTRLREQ), + TRACE_STR(STM32_TRACEERR_INVALIDPARMS), + TRACE_STR(STM32_TRACEERR_IRQREGISTRATION), + TRACE_STR(STM32_TRACEERR_NOEP), + TRACE_STR(STM32_TRACEERR_NOTCONFIGURED), + TRACE_STR(STM32_TRACEERR_EPOUTQEMPTY), + TRACE_STR(STM32_TRACEERR_EPINREQEMPTY), + TRACE_STR(STM32_TRACEERR_NOOUTSETUP), + TRACE_STR(STM32_TRACEERR_POLLTIMEOUT), + TRACE_STR_END +}; +#endif + +/* Interrupt event strings that may be enabled for more descriptive USB trace + * output. + */ + +#ifdef CONFIG_USBDEV_TRACE_STRINGS +const struct trace_msg_t g_usb_trace_strings_intdecode[] = +{ + TRACE_STR(STM32_TRACEINTID_USB), + TRACE_STR(STM32_TRACEINTID_INTPENDING), + TRACE_STR(STM32_TRACEINTID_EPOUT), + TRACE_STR(STM32_TRACEINTID_EPIN), + TRACE_STR(STM32_TRACEINTID_MISMATCH), + TRACE_STR(STM32_TRACEINTID_WAKEUP), + TRACE_STR(STM32_TRACEINTID_SUSPEND), + TRACE_STR(STM32_TRACEINTID_SOF), + TRACE_STR(STM32_TRACEINTID_RXFIFO), + TRACE_STR(STM32_TRACEINTID_DEVRESET), + TRACE_STR(STM32_TRACEINTID_ENUMDNE), + TRACE_STR(STM32_TRACEINTID_IISOIXFR), + TRACE_STR(STM32_TRACEINTID_IISOOXFR), + TRACE_STR(STM32_TRACEINTID_SRQ), + TRACE_STR(STM32_TRACEINTID_OTG), + TRACE_STR(STM32_TRACEINTID_EPOUT_XFRC), + TRACE_STR(STM32_TRACEINTID_EPOUT_EPDISD), + TRACE_STR(STM32_TRACEINTID_EPOUT_SETUP), + TRACE_STR(STM32_TRACEINTID_DISPATCH), + TRACE_STR(STM32_TRACEINTID_GETSTATUS), + TRACE_STR(STM32_TRACEINTID_EPGETSTATUS), + TRACE_STR(STM32_TRACEINTID_DEVGETSTATUS), + TRACE_STR(STM32_TRACEINTID_IFGETSTATUS), + TRACE_STR(STM32_TRACEINTID_CLEARFEATURE), + TRACE_STR(STM32_TRACEINTID_SETFEATURE), + TRACE_STR(STM32_TRACEINTID_SETADDRESS), + TRACE_STR(STM32_TRACEINTID_GETSETDESC), + TRACE_STR(STM32_TRACEINTID_GETCONFIG), + TRACE_STR(STM32_TRACEINTID_SETCONFIG), + TRACE_STR(STM32_TRACEINTID_GETSETIF), + TRACE_STR(STM32_TRACEINTID_SYNCHFRAME), + TRACE_STR(STM32_TRACEINTID_EPIN_XFRC), + TRACE_STR(STM32_TRACEINTID_EPIN_TOC), + TRACE_STR(STM32_TRACEINTID_EPIN_ITTXFE), + TRACE_STR(STM32_TRACEINTID_EPIN_EPDISD), + TRACE_STR(STM32_TRACEINTID_EPIN_TXFE), + TRACE_STR(STM32_TRACEINTID_EPIN_EMPWAIT), + TRACE_STR(STM32_TRACEINTID_OUTNAK), + TRACE_STR(STM32_TRACEINTID_OUTRECVD), + TRACE_STR(STM32_TRACEINTID_OUTDONE), + TRACE_STR(STM32_TRACEINTID_SETUPDONE), + TRACE_STR(STM32_TRACEINTID_SETUPRECVD), + TRACE_STR_END +}; +#endif + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_getreg + * + * Description: + * Get the contents of an STM32 register + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_USBDEV_REGDEBUG +static uint32_t stm32_getreg(uint32_t addr) +{ + static uint32_t prevaddr = 0; + static uint32_t preval = 0; + static uint32_t count = 0; + + /* Read the value from the register */ + + uint32_t val = getreg32(addr); + + /* Is this the same value that we read from the same register last time? + * Are we polling the register? If so, suppress some of the output. + */ + + if (addr == prevaddr && val == preval) + { + if (count == 0xffffffff || ++count > 3) + { + if (count == 4) + { + uinfo("...\n"); + } + + return val; + } + } + + /* No this is a new address or value */ + + else + { + /* Did we print "..." for the previous value? */ + + if (count > 3) + { + /* Yes.. then show how many times the value repeated */ + + uinfo("[repeats %d more times]\n", count - 3); + } + + /* Save the new address, value, and count */ + + prevaddr = addr; + preval = val; + count = 1; + } + + /* Show the register value read */ + + uinfo("%08" PRIx32 "->%08" PRIx32 "\n", addr, val); + return val; +} +#endif + +/**************************************************************************** + * Name: stm32_putreg + * + * Description: + * Set the contents of an STM32 register to a value + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_USBDEV_REGDEBUG +static void stm32_putreg(uint32_t val, uint32_t addr) +{ + /* Show the register value being written */ + + uinfo("%08" PRIx32 "<-%08" PRIx32 "\n", addr, val); + + /* Write the value */ + + putreg32(val, addr); +} +#endif + +/**************************************************************************** + * Name: stm32_req_remfirst + * + * Description: + * Remove a request from the head of an endpoint request queue + * + ****************************************************************************/ + +static struct stm32_req_s *stm32_req_remfirst( + struct stm32_ep_s *privep) +{ + struct stm32_req_s *ret = privep->head; + + if (ret) + { + privep->head = ret->flink; + if (!privep->head) + { + privep->tail = NULL; + } + + ret->flink = NULL; + } + + return ret; +} + +/**************************************************************************** + * Name: stm32_req_addlast + * + * Description: + * Add a request to the end of an endpoint request queue + * + ****************************************************************************/ + +static bool stm32_req_addlast(struct stm32_ep_s *privep, + struct stm32_req_s *req) +{ + bool is_empty = !privep->head; + + req->flink = NULL; + if (is_empty) + { + privep->head = req; + privep->tail = req; + } + else + { + privep->tail->flink = req; + privep->tail = req; + } + + return is_empty; +} + +/**************************************************************************** + * Name: stm32_ep0in_setupresponse + * + * Description: + * Schedule a short transfer on Endpoint 0 (IN or OUT) + * + ****************************************************************************/ + +static void stm32_ep0in_setupresponse(struct stm32_usbdev_s *priv, + uint8_t *buf, uint32_t nbytes) +{ + stm32_epin_transfer(&priv->epin[EP0], buf, nbytes); + priv->ep0state = EP0STATE_SETUPRESPONSE; + stm32_ep0out_ctrlsetup(priv); +} + +/**************************************************************************** + * Name: stm32_ep0in_transmitzlp + * + * Description: + * Send a zero length packet (ZLP) on endpoint 0 IN + * + ****************************************************************************/ + +static inline void stm32_ep0in_transmitzlp(struct stm32_usbdev_s *priv) +{ + stm32_ep0in_setupresponse(priv, NULL, 0); +} + +/**************************************************************************** + * Name: stm32_ep0in_activate + * + * Description: + * Activate the endpoint 0 IN endpoint. + * + ****************************************************************************/ + +static void stm32_ep0in_activate(void) +{ + uint32_t regval; + + /* Set the max packet size of the IN EP. */ + + regval = stm32_getreg(STM32_OTGFS_DIEPCTL0); + regval &= ~OTGFS_DIEPCTL0_MPSIZ_MASK; + +#if CONFIG_USBDEV_EP0_MAXSIZE == 8 + regval |= OTGFS_DIEPCTL0_MPSIZ_8; +#elif CONFIG_USBDEV_EP0_MAXSIZE == 16 + regval |= OTGFS_DIEPCTL0_MPSIZ_16; +#elif CONFIG_USBDEV_EP0_MAXSIZE == 32 + regval |= OTGFS_DIEPCTL0_MPSIZ_32; +#elif CONFIG_USBDEV_EP0_MAXSIZE == 64 + regval |= OTGFS_DIEPCTL0_MPSIZ_64; +#else +# error "Unsupported value of CONFIG_USBDEV_EP0_MAXSIZE" +#endif + + stm32_putreg(regval, STM32_OTGFS_DIEPCTL0); + + /* Clear global IN NAK */ + + regval = stm32_getreg(STM32_OTGFS_DCTL); + regval |= OTGFS_DCTL_CGINAK; + stm32_putreg(regval, STM32_OTGFS_DCTL); +} + +/**************************************************************************** + * Name: stm32_ep0out_ctrlsetup + * + * Description: + * Setup to receive a SETUP packet. + * + ****************************************************************************/ + +static void stm32_ep0out_ctrlsetup(struct stm32_usbdev_s *priv) +{ + uint32_t regval; + + /* Setup the hardware to perform the SETUP transfer */ + + regval = (USB_SIZEOF_CTRLREQ * 3 << OTGFS_DOEPTSIZ0_XFRSIZ_SHIFT) | + (OTGFS_DOEPTSIZ0_PKTCNT) | + (3 << OTGFS_DOEPTSIZ0_STUPCNT_SHIFT); + stm32_putreg(regval, STM32_OTGFS_DOEPTSIZ0); + + /* Then clear NAKing and enable the transfer */ + + regval = stm32_getreg(STM32_OTGFS_DOEPCTL0); + regval |= (OTGFS_DOEPCTL0_CNAK | OTGFS_DOEPCTL0_EPENA); + stm32_putreg(regval, STM32_OTGFS_DOEPCTL0); +} + +/**************************************************************************** + * Name: stm32_txfifo_write + * + * Description: + * Send data to the endpoint's TxFIFO. + * + ****************************************************************************/ + +static void stm32_txfifo_write(struct stm32_ep_s *privep, + uint8_t *buf, int nbytes) +{ + uint32_t regaddr; + uint32_t regval; + int nwords; + int i; + + /* Convert the number of bytes to words */ + + nwords = (nbytes + 3) >> 2; + + /* Get the TxFIFO for this endpoint (same as the endpoint number) */ + + regaddr = STM32_OTGFS_DFIFO_DEP(privep->epphy); + + /* Then transfer each word to the TxFIFO */ + + for (i = 0; i < nwords; i++) + { + /* Read four bytes from the source buffer (to avoid unaligned accesses) + * and pack these into one 32-bit word (little endian). + */ + + regval = (uint32_t)*buf++; + regval |= ((uint32_t)*buf++) << 8; + regval |= ((uint32_t)*buf++) << 16; + regval |= ((uint32_t)*buf++) << 24; + + /* Then write the packet data to the TxFIFO */ + + stm32_putreg(regval, regaddr); + } +} + +/**************************************************************************** + * Name: stm32_epin_transfer + * + * Description: + * Start the Tx data transfer + * + ****************************************************************************/ + +static void stm32_epin_transfer(struct stm32_ep_s *privep, + uint8_t *buf, int nbytes) +{ + uint32_t pktcnt; + uint32_t regval; + + /* Read the DIEPSIZx register */ + + regval = stm32_getreg(STM32_OTGFS_DIEPTSIZ(privep->epphy)); + + /* Clear the XFRSIZ, PKTCNT, and MCNT field of the DIEPSIZx register */ + + regval &= ~(OTGFS_DIEPTSIZ_XFRSIZ_MASK | OTGFS_DIEPTSIZ_PKTCNT_MASK | + OTGFS_DIEPTSIZ_MCNT_MASK); + + /* Are we sending a zero length packet (ZLP) */ + + if (nbytes == 0) + { + /* Yes.. leave the transfer size at zero and set the packet count to + * 1 + */ + + pktcnt = 1; + } + else + { + /* No.. Program the transfer size and packet count . First calculate: + * + * xfrsize = The total number of bytes to be sent. + * pktcnt = the number of packets (of maxpacket bytes) required to + * perform the transfer. + */ + + pktcnt = ((uint32_t)nbytes + (privep->ep.maxpacket - 1)) / + privep->ep.maxpacket; + } + + /* Set the XFRSIZ and PKTCNT */ + + regval |= (pktcnt << OTGFS_DIEPTSIZ_PKTCNT_SHIFT); + regval |= ((uint32_t)nbytes << OTGFS_DIEPTSIZ_XFRSIZ_SHIFT); + + /* If this is an isochronous endpoint, then set the multi-count field to + * the PKTCNT as well. + */ + + if (privep->eptype == USB_EP_ATTR_XFER_ISOC) + { + regval |= (pktcnt << OTGFS_DIEPTSIZ_MCNT_SHIFT); + } + + /* Save DIEPSIZx register value */ + + stm32_putreg(regval, STM32_OTGFS_DIEPTSIZ(privep->epphy)); + + /* Read the DIEPCTLx register */ + + regval = stm32_getreg(STM32_OTGFS_DIEPCTL(privep->epphy)); + + /* If this is an isochronous endpoint, then set the even/odd frame bit + * the DIEPCTLx register. + */ + + if (privep->eptype == USB_EP_ATTR_XFER_ISOC) + { + /* Check bit 0 of the frame number of the received SOF and set the + * even/odd frame to match. + */ + + uint32_t status = stm32_getreg(STM32_OTGFS_DSTS); + if ((status & OTGFS_DSTS_SOFFN0) == OTGFS_DSTS_SOFFN_EVEN) + { + regval |= OTGFS_DIEPCTL_SEVNFRM; + } + else + { + regval |= OTGFS_DIEPCTL_SODDFRM; + } + } + + /* EP enable, IN data in FIFO */ + + regval &= ~OTGFS_DIEPCTL_EPDIS; + regval |= (OTGFS_DIEPCTL_CNAK | OTGFS_DIEPCTL_EPENA); + stm32_putreg(regval, STM32_OTGFS_DIEPCTL(privep->epphy)); + + /* Transfer the data to the TxFIFO. At this point, the caller has already + * assured that there is sufficient space in the TxFIFO to hold the + * transfer we can just blindly continue. + */ + + stm32_txfifo_write(privep, buf, nbytes); +} + +/**************************************************************************** + * Name: stm32_epin_request + * + * Description: + * Begin or continue write request processing. + * + ****************************************************************************/ + +static void stm32_epin_request(struct stm32_usbdev_s *priv, + struct stm32_ep_s *privep) +{ + struct stm32_req_s *privreq; + uint32_t regaddr; + uint32_t regval; + uint8_t *buf; + int nbytes; + int nwords; + int bytesleft; + + /* We get here in one of four possible ways. From three interrupting + * events: + * + * 1. From stm32_epin as part of the transfer complete interrupt processing + * This interrupt indicates that the last transfer has completed. + * 2. As part of the ITTXFE interrupt processing. That interrupt indicates + * that an IN token was received when the associated TxFIFO was empty. + * 3. From stm32_epin_txfifoempty as part of the TXFE interrupt processing. + * The TXFE interrupt is only enabled when the TxFIFO is full and the + * software must wait for space to become available in the TxFIFO. + * + * And this function may be called immediately when the write request is + * queue to start up the next transaction. + * + * 4. From stm32_ep_submit when a new write request is received WHILE the + * endpoint is not active (privep->active == false). + */ + + /* Check the request from the head of the endpoint request queue */ + + privreq = stm32_rqpeek(privep); + if (!privreq) + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EPINREQEMPTY), privep->epphy); + + /* There is no TX transfer in progress and no new pending TX + * requests to send. To stop transmitting any data on a particular + * IN endpoint, the application must set the IN NAK bit. To set this + * bit, the following field must be programmed. + */ + + regaddr = STM32_OTGFS_DIEPCTL(privep->epphy); + regval = stm32_getreg(regaddr); + regval |= OTGFS_DIEPCTL_SNAK; + stm32_putreg(regval, regaddr); + + /* The endpoint is no longer active */ + + privep->active = false; + return; + } + + uinfo("EP%d req=%p: len=%zu xfrd=%zu zlp=%d\n", + privep->epphy, privreq, privreq->req.len, + privreq->req.xfrd, privep->zlp); + + /* Check for a special case: If we are just starting a request (xfrd==0) + * and the class driver is trying to send a zero-length packet (len==0). + * Then set the ZLP flag so that the packet will be sent. + */ + + if (privreq->req.len == 0) + { + /* The ZLP flag is set TRUE whenever we want to force the driver to + * send a zero-length-packet on the next pass through the loop (below). + * The flag is cleared whenever a packet is sent in the loop below. + */ + + privep->zlp = true; + } + + /* Add one more packet to the TxFIFO. We will wait for the transfer + * complete event before we add the next packet (or part of a packet + * to the TxFIFO). + * + * The documentation says that we can can multiple packets to the TxFIFO, + * but it seems that we need to get the transfer complete event before + * we can add the next (or maybe I have got something wrong?) + */ + +#if 0 + while (privreq->req.xfrd < privreq->req.len || privep->zlp) +#else + if (privreq->req.xfrd < privreq->req.len || privep->zlp) +#endif + { + /* Get the number of bytes left to be sent in the request */ + + bytesleft = privreq->req.len - privreq->req.xfrd; + nbytes = bytesleft; + + /* Assume no zero-length-packet on the next pass through this loop */ + + privep->zlp = false; + + /* Limit the size of the transfer to one full packet and handle + * zero-length packets (ZLPs). + */ + + if (nbytes > 0) + { + /* Either send the maxpacketsize or all of the remaining data in + * the request. + */ + + if (nbytes >= privep->ep.maxpacket) + { + nbytes = privep->ep.maxpacket; + + /* Handle the case where this packet is exactly the + * maxpacketsize. Do we need to send a zero-length packet + * in this case? + */ + + if (bytesleft == privep->ep.maxpacket && + (privreq->req.flags & USBDEV_REQFLAGS_NULLPKT) != 0) + { + /* The ZLP flag is set TRUE whenever we want to force + * the driver to send a zero-length-packet on the next + * pass through this loop. The flag is cleared (above) + * whenever we are committed to sending any packet and + * set here when we want to force one more pass through + * the loop. + */ + + privep->zlp = true; + } + } + } + + /* Get the transfer size in 32-bit words */ + + nwords = (nbytes + 3) >> 2; + + /* Get the number of 32-bit words available in the TxFIFO. The + * DXTFSTS indicates the amount of free space available in the + * endpoint TxFIFO. Values are in terms of 32-bit words: + * + * 0: Endpoint TxFIFO is full + * 1: 1 word available + * 2: 2 words available + * n: n words available + */ + + regaddr = STM32_OTGFS_DTXFSTS(privep->epphy); + + /* Check for space in the TxFIFO. If space in the TxFIFO is not + * available, then set up an interrupt to resume the transfer when + * the TxFIFO is empty. + */ + + regval = stm32_getreg(regaddr); + if ((int)(regval & OTGFS_DTXFSTS_MASK) < nwords) + { + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPIN_EMPWAIT), + (uint16_t)regval); + + /* There is insufficient space in the TxFIFO. Wait for a TxFIFO + * empty interrupt and try again. + */ + + uint32_t empmsk = stm32_getreg(STM32_OTGFS_DIEPEMPMSK); + empmsk |= OTGFS_DIEPEMPMSK(privep->epphy); + stm32_putreg(empmsk, STM32_OTGFS_DIEPEMPMSK); + +#ifdef CONFIG_DEBUG_FEATURES + /* Check if the configured TXFIFO size is sufficient for a given + * request. If not, raise an assertion here. + */ + + regval = stm32_getreg(STM32_OTGFS_DIEPTXF(privep->epphy)); + regval &= OTGFS_DIEPTXF_INEPTXFD_MASK; + regval >>= OTGFS_DIEPTXF_INEPTXFD_SHIFT; + uerr("EP%" PRId8 " TXLEN=%" PRId32 " nwords=%d\n", + privep->epphy, regval, nwords); + DEBUGASSERT(regval >= nwords); +#endif + + /* Terminate the transfer. We will try again when the TxFIFO empty + * interrupt is received. + */ + + return; + } + + /* Transfer data to the TxFIFO */ + + buf = privreq->req.buf + privreq->req.xfrd; + stm32_epin_transfer(privep, buf, nbytes); + + /* If it was not before, the OUT endpoint is now actively transferring + * data. + */ + + privep->active = true; + + /* EP0 is a special case */ + + if (privep->epphy == EP0) + { + priv->ep0state = EP0STATE_DATA_IN; + } + + /* Update for the next time through the loop */ + + privreq->req.xfrd += nbytes; + } + + /* Note that the ZLP, if any, must be sent as a separate transfer. The + * need for a ZLP is indicated by privep->zlp. If all of the bytes were + * sent (including any final null packet) then we are finished with the + * transfer + */ + + if (privreq->req.xfrd >= privreq->req.len && !privep->zlp) + { + usbtrace(TRACE_COMPLETE(privep->epphy), privreq->req.xfrd); + + /* We are finished with the request (although the transfer has not + * yet completed). + */ + + stm32_req_complete(privep, OK); + } +} + +/**************************************************************************** + * Name: stm32_rxfifo_read + * + * Description: + * Read packet from the RxFIFO into a read request. + * + ****************************************************************************/ + +static void stm32_rxfifo_read(struct stm32_ep_s *privep, + uint8_t *dest, uint16_t len) +{ + uint32_t regaddr; + int i; + + /* Get the address of the RxFIFO. Note: there is only one RxFIFO so + * we might as well use the address associated with EP0. + */ + + regaddr = STM32_OTGFS_DFIFO_DEP(EP0); + + /* Read 32-bits and write 4 x 8-bits at time (to avoid unaligned + * accesses) + */ + + for (i = 0; i < len; i += 4) + { + union + { + uint32_t w; + uint8_t b[4]; + } data; + + /* Read 1 x 32-bits of EP0 packet data */ + + data.w = stm32_getreg(regaddr); + + /* Write 4 x 8-bits of EP0 packet data */ + + *dest++ = data.b[0]; + *dest++ = data.b[1]; + *dest++ = data.b[2]; + *dest++ = data.b[3]; + } +} + +/**************************************************************************** + * Name: stm32_rxfifo_discard + * + * Description: + * Discard packet data from the RxFIFO. + * + ****************************************************************************/ + +static void stm32_rxfifo_discard(struct stm32_ep_s *privep, int len) +{ + if (len > 0) + { + uint32_t regaddr; + int i; + + /* Get the address of the RxFIFO Note: there is only one RxFIFO so + * we might as well use the address associated with EP0. + */ + + regaddr = STM32_OTGFS_DFIFO_DEP(EP0); + + /* Read 32-bits at time */ + + for (i = 0; i < len; i += 4) + { + volatile uint32_t data = stm32_getreg(regaddr); + UNUSED(data); + } + } +} + +/**************************************************************************** + * Name: stm32_epout_complete + * + * Description: + * This function is called when an OUT transfer complete interrupt is + * received. It completes the read request at the head of the endpoint's + * request queue. + * + ****************************************************************************/ + +static void stm32_epout_complete(struct stm32_usbdev_s *priv, + struct stm32_ep_s *privep) +{ + struct stm32_req_s *privreq; + + /* Since a transfer just completed, there must be a read request at the + * head of the endpoint request queue. + */ + + privreq = stm32_rqpeek(privep); + DEBUGASSERT(privreq); + + if (!privreq) + { + /* An OUT transfer completed, but no packet to receive the data. This + * should not happen. + */ + + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EPOUTQEMPTY), privep->epphy); + privep->active = false; + return; + } + + uinfo("EP%d: len=%zu xfrd=%zu\n", + privep->epphy, privreq->req.len, privreq->req.xfrd); + + /* Return the completed read request to the class driver and mark the state + * IDLE. + */ + + usbtrace(TRACE_COMPLETE(privep->epphy), privreq->req.xfrd); + stm32_req_complete(privep, OK); + privep->active = false; + + /* Now set up the next read request (if any) */ + + stm32_epout_request(priv, privep); +} + +/**************************************************************************** + * Name: stm32_ep0out_receive + * + * Description: + * This function is called from the RXFLVL interrupt handler when new + * incoming data is available in the endpoint's RxFIFO. This function + * will simply copy the incoming data into pending request's data buffer. + * + ****************************************************************************/ + +static inline void stm32_ep0out_receive(struct stm32_ep_s *privep, + int bcnt) +{ + struct stm32_usbdev_s *priv; + + /* Sanity Checking */ + + DEBUGASSERT(privep && privep->dev); + priv = (struct stm32_usbdev_s *)privep->dev; + + uinfo("EP0: bcnt=%d\n", bcnt); + usbtrace(TRACE_READ(EP0), bcnt); + + /* Verify that an OUT SETUP request as received before this data was + * received in the RxFIFO. + */ + + if (priv->ep0state == EP0STATE_SETUP_OUT) + { + if (priv->ep0datlen < CONFIG_USBDEV_SETUP_MAXDATASIZE) + { + /* Read the data into our special buffer for SETUP data */ + + int bufspace = CONFIG_USBDEV_SETUP_MAXDATASIZE - priv->ep0datlen; + int readlen = MIN(bufspace, bcnt); + stm32_rxfifo_read(privep, priv->ep0data, readlen); + priv->ep0datlen += readlen; + bcnt -= readlen; + } + + /* Do we have to discard any excess bytes? */ + + if (bcnt > 0) + { + stm32_rxfifo_discard(privep, bcnt); + priv->ep0datlen += bcnt; + } + + /* Is the transfer complete? */ + + if (priv->ep0datlen >= GETUINT16(priv->ctrlreq.len)) + { + /* Now we can process the setup command */ + + privep->active = false; + priv->ep0state = EP0STATE_SETUP_READY; + priv->ep0datlen = MIN(CONFIG_USBDEV_SETUP_MAXDATASIZE, + priv->ep0datlen); + + stm32_ep0out_setup(priv); + } + else + { + /* More data to come, clear NAKSTS */ + + uint32_t regval = stm32_getreg(STM32_OTGFS_DOEPCTL0); + regval |= OTGFS_DOEPCTL0_CNAK; + stm32_putreg(regval, STM32_OTGFS_DOEPCTL0); + } + } + else + { + /* This is an error. We don't have any idea what to do with the EP0 + * data in this case. Just read and discard it so that the RxFIFO + * does not become constipated. + */ + + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_NOOUTSETUP), priv->ep0state); + stm32_rxfifo_discard(privep, bcnt); + privep->active = false; + } +} + +/**************************************************************************** + * Name: stm32_epout_receive + * + * Description: + * This function is called from the RXFLVL interrupt handler when new + * incoming data is available in the endpoint's RxFIFO. This function + * will simply copy the incoming data into pending request's data buffer. + * + ****************************************************************************/ + +static inline void stm32_epout_receive(struct stm32_ep_s *privep, + int bcnt) +{ + struct stm32_req_s *privreq; + uint8_t *dest; + int buflen; + int readlen; + + /* Get a reference to the request at the head of the endpoint's request + * queue. + */ + + privreq = stm32_rqpeek(privep); + if (!privreq) + { + /* Incoming data is available in the RxFIFO, but there is no read setup + * to receive the receive the data. This should not happen for data + * endpoints; those endpoints should have been NAKing any OUT data + * tokens. + * + * We should get here normally on OUT data phase following an OUT + * SETUP command. EP0 data will still receive data in this case and it + * should not be NAKing. + */ + + if (privep->epphy == 0) + { + stm32_ep0out_receive(privep, bcnt); + } + else + { + /* Otherwise, the data is lost. This really should not happen if + * NAKing is working as expected. + */ + + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EPOUTQEMPTY), + privep->epphy); + + /* Discard the data in the RxFIFO */ + + stm32_rxfifo_discard(privep, bcnt); + } + + privep->active = false; + return; + } + + uinfo("EP%d: len=%zu xfrd=%zu\n", + privep->epphy, privreq->req.len, privreq->req.xfrd); + usbtrace(TRACE_READ(privep->epphy), bcnt); + + /* Get the number of bytes to transfer from the RxFIFO */ + + buflen = privreq->req.len - privreq->req.xfrd; + DEBUGASSERT(buflen > 0 && buflen >= bcnt); + readlen = MIN(buflen, bcnt); + + /* Get the destination of the data transfer */ + + dest = privreq->req.buf + privreq->req.xfrd; + + /* Transfer the data from the RxFIFO to the request's data buffer */ + + stm32_rxfifo_read(privep, dest, readlen); + + /* If there were more bytes in the RxFIFO than could be held in the read + * request, then we will have to discard those. + */ + + stm32_rxfifo_discard(privep, bcnt - readlen); + + /* Update the number of bytes transferred */ + + privreq->req.xfrd += readlen; +} + +/**************************************************************************** + * Name: stm32_epout_request + * + * Description: + * This function is called when either (1) new read request is received, or + * (2) a pending receive request completes. If there is no read in + * pending, then this function will initiate the next OUT (read) operation. + * + ****************************************************************************/ + +static void stm32_epout_request(struct stm32_usbdev_s *priv, + struct stm32_ep_s *privep) +{ + struct stm32_req_s *privreq; + uint32_t regaddr; + uint32_t regval; + uint32_t xfrsize; + uint32_t pktcnt; + + /* Make sure that there is not already a pending request request. If + * there is, just return, leaving the newly received request in the + * request queue. + */ + + if (!privep->active) + { + /* Loop until a valid request is found (or the request queue is empty). + * The loop is only need to look at the request queue again is an + * invalid read request is encountered. + */ + + for (; ; ) + { + /* Get a reference to the request at the head of the endpoint's + * request queue + */ + + privreq = stm32_rqpeek(privep); + if (!privreq) + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EPOUTQEMPTY), + privep->epphy); + + /* There are no read requests to be setup. Configure the + * hardware to NAK any incoming packets. (This should already + * be the case. I think that the hardware will automatically + * NAK after a transfer is completed until SNAK is cleared). + */ + + regaddr = STM32_OTGFS_DOEPCTL(privep->epphy); + regval = stm32_getreg(regaddr); + regval |= OTGFS_DOEPCTL_SNAK; + stm32_putreg(regval, regaddr); + + /* This endpoint is no longer actively transferring */ + + privep->active = false; + return; + } + + uinfo("EP%d: len=%d\n", privep->epphy, privreq->req.len); + + /* Ignore any attempt to receive a zero length packet (this really + * should not happen. + */ + + if (privreq->req.len <= 0) + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EPOUTNULLPACKET), 0); + stm32_req_complete(privep, OK); + } + + /* Otherwise, we have a usable read request... break out of the + * loop + */ + + else + { + break; + } + } + + /* Setup the pending read into the request buffer. First calculate: + * + * pktcnt = the number of packets (of maxpacket bytes) required to + * perform the transfer. + * xfrsize = The total number of bytes required (in units of + * maxpacket bytes). + */ + + pktcnt = (privreq->req.len + (privep->ep.maxpacket - 1)) / + privep->ep.maxpacket; + xfrsize = pktcnt * privep->ep.maxpacket; + + /* Then setup the hardware to perform this transfer */ + + regaddr = STM32_OTGFS_DOEPTSIZ(privep->epphy); + regval = stm32_getreg(regaddr); + regval &= ~(OTGFS_DOEPTSIZ_XFRSIZ_MASK | OTGFS_DOEPTSIZ_PKTCNT_MASK); + regval |= (xfrsize << OTGFS_DOEPTSIZ_XFRSIZ_SHIFT); + regval |= (pktcnt << OTGFS_DOEPTSIZ_PKTCNT_SHIFT); + stm32_putreg(regval, regaddr); + + /* Then enable the transfer */ + + regaddr = STM32_OTGFS_DOEPCTL(privep->epphy); + regval = stm32_getreg(regaddr); + + /* When an isochronous transfer is enabled the Even/Odd frame bit must + * also be set appropriately. + */ + +#ifdef CONFIG_USBDEV_ISOCHRONOUS + if (privep->eptype == USB_EP_ATTR_XFER_ISOC) + { + if (privep->odd) + { + regval |= OTGFS_DOEPCTL_SODDFRM; + } + else + { + regval |= OTGFS_DOEPCTL_SEVNFRM; + } + } +#endif + + /* Clearing NAKing and enable the transfer. */ + + regval |= (OTGFS_DOEPCTL_CNAK | OTGFS_DOEPCTL_EPENA); + stm32_putreg(regval, regaddr); + + /* A transfer is now active on this endpoint */ + + privep->active = true; + + /* EP0 is a special case. We need to know when to switch back to + * normal SETUP processing. + */ + + if (privep->epphy == EP0) + { + priv->ep0state = EP0STATE_DATA_OUT; + } + } +} + +/**************************************************************************** + * Name: stm32_ep_flush + * + * Description: + * Flush any primed descriptors from this ep + * + ****************************************************************************/ + +static void stm32_ep_flush(struct stm32_ep_s *privep) +{ + if (privep->isin) + { + stm32_txfifo_flush(OTGFS_GRSTCTL_TXFNUM_D(privep->epphy)); + } + else + { + stm32_rxfifo_flush(); + } +} + +/**************************************************************************** + * Name: stm32_req_complete + * + * Description: + * Handle termination of the request at the head of the endpoint request + * queue. + * + ****************************************************************************/ + +static void stm32_req_complete(struct stm32_ep_s *privep, int16_t result) +{ + struct stm32_req_s *privreq; + + /* Remove the request at the head of the request list */ + + privreq = stm32_req_remfirst(privep); + DEBUGASSERT(privreq != NULL); + + /* If endpoint 0, temporarily reflect the state of protocol stalled + * in the callback. + */ + + bool stalled = privep->stalled; + if (privep->epphy == EP0) + { + privep->stalled = privep->dev->stalled; + } + + /* Save the result in the request structure */ + + privreq->req.result = result; + + /* Callback to the request completion handler */ + + privreq->req.callback(&privep->ep, &privreq->req); + + /* Restore the stalled indication */ + + privep->stalled = stalled; +} + +/**************************************************************************** + * Name: stm32_req_cancel + * + * Description: + * Cancel all pending requests for an endpoint + * + ****************************************************************************/ + +static void stm32_req_cancel(struct stm32_ep_s *privep, int16_t status) +{ + if (!stm32_rqempty(privep)) + { + stm32_ep_flush(privep); + } + + while (!stm32_rqempty(privep)) + { + usbtrace(TRACE_COMPLETE(privep->epphy), + (stm32_rqpeek(privep))->req.xfrd); + stm32_req_complete(privep, status); + } +} + +/**************************************************************************** + * Name: stm32_ep_findbyaddr + * + * Description: + * Find the physical endpoint structure corresponding to a logic endpoint + * address + * + ****************************************************************************/ + +static struct stm32_ep_s *stm32_ep_findbyaddr(struct stm32_usbdev_s *priv, + uint16_t eplog) +{ + struct stm32_ep_s *privep; + uint8_t epphy = USB_EPNO(eplog); + + if (epphy >= STM32_NENDPOINTS) + { + return NULL; + } + + /* Is this an IN or an OUT endpoint? */ + + if (USB_ISEPIN(eplog)) + { + privep = &priv->epin[epphy]; + } + else + { + privep = &priv->epout[epphy]; + } + + /* Return endpoint reference */ + + DEBUGASSERT(privep->epphy == epphy); + return privep; +} + +/**************************************************************************** + * Name: stm32_req_dispatch + * + * Description: + * Provide unhandled setup actions to the class driver. This is logically + * part of the USB interrupt handler. + * + ****************************************************************************/ + +static int stm32_req_dispatch(struct stm32_usbdev_s *priv, + const struct usb_ctrlreq_s *ctrl) +{ + int ret = -EIO; + + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_DISPATCH), 0); + if (priv->driver) + { + /* Forward to the control request to the class driver implementation */ + + ret = CLASS_SETUP(priv->driver, &priv->usbdev, ctrl, + priv->ep0data, priv->ep0datlen); + } + + if (ret < 0) + { + /* Stall on failure */ + + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_DISPATCHSTALL), 0); + priv->stalled = true; + } + + return ret; +} + +/**************************************************************************** + * Name: stm32_usbreset + * + * Description: + * Reset Usb engine + * + ****************************************************************************/ + +static void stm32_usbreset(struct stm32_usbdev_s *priv) +{ + struct stm32_ep_s *privep; + uint32_t regval; + int i; + + /* Clear the Remote Wake-up Signaling */ + + regval = stm32_getreg(STM32_OTGFS_DCTL); + regval &= ~OTGFS_DCTL_RWUSIG; + stm32_putreg(regval, STM32_OTGFS_DCTL); + + /* Flush the EP0 Tx FIFO */ + + stm32_txfifo_flush(OTGFS_GRSTCTL_TXFNUM_D(EP0)); + + /* Tell the class driver that we are disconnected. The class + * driver should then accept any new configurations. + */ + + if (priv->driver) + { + CLASS_DISCONNECT(priv->driver, &priv->usbdev); + } + + /* Mark all endpoints as available */ + + priv->epavail[0] = STM32_EP_AVAILABLE; + priv->epavail[1] = STM32_EP_AVAILABLE; + + /* Disable all end point interrupts */ + + for (i = 0; i < STM32_NENDPOINTS ; i++) + { + /* Disable endpoint interrupts */ + + stm32_putreg(0xff, STM32_OTGFS_DIEPINT(i)); + stm32_putreg(0xff, STM32_OTGFS_DOEPINT(i)); + + /* Return write requests to the class implementation */ + + privep = &priv->epin[i]; + stm32_req_cancel(privep, -ESHUTDOWN); + + /* Reset IN endpoint status */ + + privep->stalled = false; + privep->active = false; + privep->zlp = false; + + /* Return read requests to the class implementation */ + + privep = &priv->epout[i]; + stm32_req_cancel(privep, -ESHUTDOWN); + + /* Reset endpoint status */ + + privep->stalled = false; + privep->active = false; + privep->zlp = false; + } + + stm32_putreg(0xffffffff, STM32_OTGFS_DAINT); + + /* Mask all device endpoint interrupts except EP0 */ + + regval = (OTGFS_DAINT_IEP(EP0) | OTGFS_DAINT_OEP(EP0)); + stm32_putreg(regval, STM32_OTGFS_DAINTMSK); + + /* Unmask OUT interrupts */ + + regval = (OTGFS_DOEPMSK_XFRCM | OTGFS_DOEPMSK_STUPM | OTGFS_DOEPMSK_EPDM); + stm32_putreg(regval, STM32_OTGFS_DOEPMSK); + + /* Unmask IN interrupts */ + + regval = (OTGFS_DIEPMSK_XFRCM | OTGFS_DIEPMSK_EPDM | OTGFS_DIEPMSK_TOM); + stm32_putreg(regval, STM32_OTGFS_DIEPMSK); + + /* Reset device address to 0 */ + + stm32_setaddress(priv, 0); + priv->devstate = DEVSTATE_DEFAULT; + priv->usbdev.speed = USB_SPEED_FULL; + + /* Re-configure EP0 */ + + stm32_ep0_configure(priv); + + /* Setup EP0 to receive SETUP packets */ + + stm32_ep0out_ctrlsetup(priv); +} + +/**************************************************************************** + * Name: stm32_ep0out_testmode + * + * Description: + * Select test mode + * + ****************************************************************************/ + +static inline void stm32_ep0out_testmode(struct stm32_usbdev_s *priv, + uint16_t index) +{ + uint8_t testmode; + + testmode = index >> 8; + switch (testmode) + { + case 1: + priv->testmode = OTGFS_TESTMODE_J; + break; + + case 2: + priv->testmode = OTGFS_TESTMODE_K; + break; + + case 3: + priv->testmode = OTGFS_TESTMODE_SE0_NAK; + break; + + case 4: + priv->testmode = OTGFS_TESTMODE_PACKET; + break; + + case 5: + priv->testmode = OTGFS_TESTMODE_FORCE; + break; + + default: + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADTESTMODE), testmode); + priv->dotest = false; + priv->testmode = OTGFS_TESTMODE_DISABLED; + priv->stalled = true; + } + + priv->dotest = true; + stm32_ep0in_transmitzlp(priv); +} + +/**************************************************************************** + * Name: stm32_ep0out_stdrequest + * + * Description: + * Handle a standard request on EP0. Pick off the things of interest to + * the USB device controller driver; pass what is left to the class driver. + * + ****************************************************************************/ + +static inline void stm32_ep0out_stdrequest(struct stm32_usbdev_s *priv, + struct stm32_ctrlreq_s * + ctrlreq) +{ + struct stm32_ep_s *privep; + + /* Handle standard request */ + + switch (ctrlreq->req) + { + case USB_REQ_GETSTATUS: + { + /* type: device-to-host; recipient = device, interface, endpoint + * value: 0 + * index: zero interface endpoint + * len: 2; data = status + */ + + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_GETSTATUS), 0); + if (!priv->addressed || + ctrlreq->len != 2 || + USB_REQ_ISOUT(ctrlreq->type) || + ctrlreq->value != 0) + { + priv->stalled = true; + } + else + { + switch (ctrlreq->type & USB_REQ_RECIPIENT_MASK) + { + case USB_REQ_RECIPIENT_ENDPOINT: + { + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPGETSTATUS), 0); + privep = stm32_ep_findbyaddr(priv, ctrlreq->index); + if (!privep) + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADEPGETSTATUS), + 0); + priv->stalled = true; + } + else + { + if (privep->stalled) + { + priv->ep0data[0] = (1 << USB_FEATURE_ENDPOINTHALT); + } + else + { + priv->ep0data[0] = 0; /* Not stalled */ + } + + priv->ep0data[1] = 0; + stm32_ep0in_setupresponse(priv, priv->ep0data, 2); + } + } + break; + + case USB_REQ_RECIPIENT_DEVICE: + { + if (ctrlreq->index == 0) + { + usbtrace(TRACE_INTDECODE( + STM32_TRACEINTID_DEVGETSTATUS), + 0); + + /* Features: Remote Wakeup and self-powered */ + + priv->ep0data[0] = (priv->selfpowered << + USB_FEATURE_SELFPOWERED); + priv->ep0data[0] |= (priv->wakeup << + USB_FEATURE_REMOTEWAKEUP); + priv->ep0data[1] = 0; + + stm32_ep0in_setupresponse(priv, priv->ep0data, 2); + } + else + { + usbtrace(TRACE_DEVERROR( + STM32_TRACEERR_BADDEVGETSTATUS), + 0); + priv->stalled = true; + } + } + break; + + case USB_REQ_RECIPIENT_INTERFACE: + { + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_IFGETSTATUS), 0); + priv->ep0data[0] = 0; + priv->ep0data[1] = 0; + + stm32_ep0in_setupresponse(priv, priv->ep0data, 2); + } + break; + + default: + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADGETSTATUS), 0); + priv->stalled = true; + } + break; + } + } + } + break; + + case USB_REQ_CLEARFEATURE: + { + /* type: host-to-device; recipient = device, interface or endpoint + * value: feature selector + * index: zero interface endpoint; + * len: zero, data = none + */ + + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_CLEARFEATURE), 0); + if (priv->addressed != 0 && ctrlreq->len == 0) + { + uint8_t recipient = ctrlreq->type & USB_REQ_RECIPIENT_MASK; + if (recipient == USB_REQ_RECIPIENT_ENDPOINT && + ctrlreq->value == USB_FEATURE_ENDPOINTHALT && + (privep = stm32_ep_findbyaddr(priv, ctrlreq->index)) != NULL) + { + stm32_ep_clrstall(privep); + stm32_ep0in_transmitzlp(priv); + } + else if (recipient == USB_REQ_RECIPIENT_DEVICE && + ctrlreq->value == USB_FEATURE_REMOTEWAKEUP) + { + priv->wakeup = 0; + stm32_ep0in_transmitzlp(priv); + } + else + { + /* Actually, I think we could just stall here. */ + + stm32_req_dispatch(priv, &priv->ctrlreq); + } + } + else + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADCLEARFEATURE), 0); + priv->stalled = true; + } + } + break; + + case USB_REQ_SETFEATURE: + { + /* type: host-to-device; recipient = device, interface, endpoint + * value: feature selector + * index: zero interface endpoint; + * len: 0; data = none + */ + + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SETFEATURE), 0); + if (priv->addressed != 0 && ctrlreq->len == 0) + { + uint8_t recipient = ctrlreq->type & USB_REQ_RECIPIENT_MASK; + if (recipient == USB_REQ_RECIPIENT_ENDPOINT && + ctrlreq->value == USB_FEATURE_ENDPOINTHALT && + (privep = stm32_ep_findbyaddr(priv, ctrlreq->index)) != NULL) + { + stm32_ep_setstall(privep); + stm32_ep0in_transmitzlp(priv); + } + else if (recipient == USB_REQ_RECIPIENT_DEVICE && + ctrlreq->value == USB_FEATURE_REMOTEWAKEUP) + { + priv->wakeup = 1; + stm32_ep0in_transmitzlp(priv); + } + else if (recipient == USB_REQ_RECIPIENT_DEVICE && + ctrlreq->value == USB_FEATURE_TESTMODE && + ((ctrlreq->index & 0xff) == 0)) + { + stm32_ep0out_testmode(priv, ctrlreq->index); + } + else if (priv->configured) + { + /* Actually, I think we could just stall here. */ + + stm32_req_dispatch(priv, &priv->ctrlreq); + } + else + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADSETFEATURE), 0); + priv->stalled = true; + } + } + else + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADSETFEATURE), 0); + priv->stalled = true; + } + } + break; + + case USB_REQ_SETADDRESS: + { + /* type: host-to-device; recipient = device + * value: device address + * index: 0 + * len: 0; data = none + */ + + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SETADDRESS), + ctrlreq->value); + if ((ctrlreq->type & USB_REQ_RECIPIENT_MASK) == + USB_REQ_RECIPIENT_DEVICE && + ctrlreq->index == 0 && + ctrlreq->len == 0 && + ctrlreq->value < 128 && + priv->devstate != DEVSTATE_CONFIGURED) + { + /* Save the address. We cannot actually change to the next + * address until the completion of the status phase. + */ + + stm32_setaddress(priv, (uint16_t)priv->ctrlreq.value[0]); + stm32_ep0in_transmitzlp(priv); + } + else + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADSETADDRESS), 0); + priv->stalled = true; + } + } + break; + + case USB_REQ_GETDESCRIPTOR: + /* type: device-to-host; recipient = device + * value: descriptor type and index + * index: 0 or language ID; + * len: descriptor len; data = descriptor + */ + + case USB_REQ_SETDESCRIPTOR: + /* type: host-to-device; recipient = device + * value: descriptor type and index + * index: 0 or language ID; + * len: descriptor len; data = descriptor + */ + + { + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_GETSETDESC), 0); + if ((ctrlreq->type & USB_REQ_RECIPIENT_MASK) == + USB_REQ_RECIPIENT_DEVICE) + { + stm32_req_dispatch(priv, &priv->ctrlreq); + } + else + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADGETSETDESC), 0); + priv->stalled = true; + } + } + break; + + case USB_REQ_GETCONFIGURATION: + /* type: device-to-host; recipient = device + * value: 0; + * index: 0; + * len: 1; data = configuration value + */ + + { + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_GETCONFIG), 0); + if (priv->addressed && + (ctrlreq->type & USB_REQ_RECIPIENT_MASK) == + USB_REQ_RECIPIENT_DEVICE && + ctrlreq->value == 0 && + ctrlreq->index == 0 && + ctrlreq->len == 1) + { + stm32_req_dispatch(priv, &priv->ctrlreq); + } + else + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADGETCONFIG), 0); + priv->stalled = true; + } + } + break; + + case USB_REQ_SETCONFIGURATION: + /* type: host-to-device; recipient = device + * value: configuration value + * index: 0; + * len: 0; data = none + */ + + { + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SETCONFIG), 0); + if (priv->addressed && + (ctrlreq->type & USB_REQ_RECIPIENT_MASK) == + USB_REQ_RECIPIENT_DEVICE && + ctrlreq->index == 0 && + ctrlreq->len == 0) + { + /* Give the configuration to the class driver */ + + int ret = stm32_req_dispatch(priv, &priv->ctrlreq); + + /* If the class driver accepted the configuration, then mark the + * device state as configured (or not, depending on the + * configuration). + */ + + if (ret == OK) + { + uint8_t cfg = (uint8_t)ctrlreq->value; + if (cfg != 0) + { + priv->devstate = DEVSTATE_CONFIGURED; + priv->configured = true; + } + else + { + priv->devstate = DEVSTATE_ADDRESSED; + priv->configured = false; + } + } + } + else + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADSETCONFIG), 0); + priv->stalled = true; + } + } + break; + + case USB_REQ_GETINTERFACE: + /* type: device-to-host; recipient = interface + * value: 0 + * index: interface; + * len: 1; data = alt interface + */ + + case USB_REQ_SETINTERFACE: + /* type: host-to-device; recipient = interface + * value: alternate setting + * index: interface; + * len: 0; data = none + */ + + { + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_GETSETIF), 0); + stm32_req_dispatch(priv, &priv->ctrlreq); + } + break; + + case USB_REQ_SYNCHFRAME: + /* type: device-to-host; recipient = endpoint + * value: 0 + * index: endpoint; + * len: 2; data = frame number + */ + + { + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SYNCHFRAME), 0); + } + break; + + default: + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDCTRLREQ), 0); + priv->stalled = true; + } + break; + } +} + +/**************************************************************************** + * Name: stm32_ep0out_setup + * + * Description: + * USB Ctrl EP Setup Event. This is logically part of the USB interrupt + * handler. This event occurs when a setup packet is receive on EP0 OUT. + * + ****************************************************************************/ + +static inline void stm32_ep0out_setup(struct stm32_usbdev_s *priv) +{ + struct stm32_ctrlreq_s ctrlreq; + + /* Verify that a SETUP was received */ + + if (priv->ep0state != EP0STATE_SETUP_READY) + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EP0NOSETUP), priv->ep0state); + return; + } + + /* Terminate any pending requests */ + + stm32_req_cancel(&priv->epout[EP0], -EPROTO); + stm32_req_cancel(&priv->epin[EP0], -EPROTO); + + /* Assume NOT stalled */ + + priv->epout[EP0].stalled = false; + priv->epin[EP0].stalled = false; + priv->stalled = false; + + /* Starting to process a control request - update state */ + + priv->ep0state = EP0STATE_SETUP_PROCESS; + + /* And extract the little-endian 16-bit values to host order */ + + ctrlreq.type = priv->ctrlreq.type; + ctrlreq.req = priv->ctrlreq.req; + ctrlreq.value = GETUINT16(priv->ctrlreq.value); + ctrlreq.index = GETUINT16(priv->ctrlreq.index); + ctrlreq.len = GETUINT16(priv->ctrlreq.len); + + uinfo("type=%02x req=%02x value=%04x index=%04x len=%04x\n", + ctrlreq.type, ctrlreq.req, ctrlreq.value, ctrlreq.index, + ctrlreq.len); + + /* Check for a standard request */ + + if ((ctrlreq.type & USB_REQ_TYPE_MASK) != USB_REQ_TYPE_STANDARD) + { + /* Dispatch any non-standard requests */ + + stm32_req_dispatch(priv, &priv->ctrlreq); + } + else + { + /* Handle standard requests. */ + + stm32_ep0out_stdrequest(priv, &ctrlreq); + } + + /* Check if the setup processing resulted in a STALL */ + + if (priv->stalled) + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EP0SETUPSTALLED), + priv->ep0state); + stm32_ep0_stall(priv); + } + + /* Reset state/data associated with the SETUP request */ + + priv->ep0datlen = 0; +} + +/**************************************************************************** + * Name: stm32_epout + * + * Description: + * This is part of the OUT endpoint interrupt processing. This function + * handles the OUT event for a single endpoint. + * + ****************************************************************************/ + +static inline void stm32_epout(struct stm32_usbdev_s *priv, uint8_t epno) +{ + struct stm32_ep_s *privep; + + /* Endpoint 0 is a special case. */ + + if (epno == 0) + { + privep = &priv->epout[EP0]; + + /* In the EP0STATE_DATA_OUT state, we are receiving data into the + * request buffer. In that case, we must continue the request + * processing. + */ + + if (priv->ep0state == EP0STATE_DATA_OUT) + { + /* Continue processing data from the EP0 OUT request queue */ + + stm32_epout_complete(priv, privep); + + /* If we are not actively processing an OUT request, then we + * need to setup to receive the next control request. + */ + + if (!privep->active) + { + stm32_ep0out_ctrlsetup(priv); + priv->ep0state = EP0STATE_IDLE; + } + } + } + + /* For other endpoints, the only possibility is that we are continuing + * or finishing an OUT request. + */ + + else if (priv->devstate == DEVSTATE_CONFIGURED) + { + stm32_epout_complete(priv, &priv->epout[epno]); + } +} + +/**************************************************************************** + * Name: stm32_epout_interrupt + * + * Description: + * USB OUT endpoint interrupt handler. The core generates this interrupt + * when there is an interrupt is pending on one of the OUT endpoints of + * the core. + * The driver must read the OTGFS DAINT register to determine the exact + * number of the OUT endpoint on which the interrupt occurred, and then + * read the corresponding OTGFS DOEPINTx register to determine the exact + * cause of the interrupt. + * + ****************************************************************************/ + +static inline void stm32_epout_interrupt(struct stm32_usbdev_s *priv) +{ + uint32_t daint; + uint32_t regval; + uint32_t doepint; + int epno; + + /* Get the pending, enabled interrupts for the OUT endpoint from the + * endpoint interrupt status register. + */ + + regval = stm32_getreg(STM32_OTGFS_DAINT); + regval &= stm32_getreg(STM32_OTGFS_DAINTMSK); + daint = (regval & OTGFS_DAINT_OEP_MASK) >> OTGFS_DAINT_OEP_SHIFT; + + if (daint == 0) + { + /* We got an interrupt, but there is no unmasked endpoint that caused + * it ?! When this happens, the interrupt flag never gets cleared and + * we are stuck in infinite interrupt loop. + * + * This shouldn't happen if we are diligent about handling timing + * issues when masking endpoint interrupts. However, this workaround + * avoids infinite loop and allows operation to continue normally. It + * works by clearing each endpoint flags, masked or not. + */ + + regval = stm32_getreg(STM32_OTGFS_DAINT); + daint = (regval & OTGFS_DAINT_OEP_MASK) >> OTGFS_DAINT_OEP_SHIFT; + + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EPOUTUNEXPECTED), + (uint16_t)regval); + + epno = 0; + while (daint) + { + if ((daint & 1) != 0) + { + regval = stm32_getreg(STM32_OTGFS_DOEPINT(epno)); + uinfo("DOEPINT(%d) = %08" PRIx32 "\n", epno, regval); + stm32_putreg(0xff, STM32_OTGFS_DOEPINT(epno)); + } + + epno++; + daint >>= 1; + } + + return; + } + + /* Process each pending IN endpoint interrupt */ + + epno = 0; + while (daint) + { + /* Is an OUT interrupt pending for this endpoint? */ + + if ((daint & 1) != 0) + { + /* Yes.. get the OUT endpoint interrupt status */ + + doepint = stm32_getreg(STM32_OTGFS_DOEPINT(epno)); + doepint &= stm32_getreg(STM32_OTGFS_DOEPMSK); + + /* Transfer completed interrupt. This interrupt is triggered when + * stm32_rxinterrupt() removes the last packet data from the + * RxFIFO. In this case, core internally sets the NAK bit for this + * endpoint to prevent it from receiving any more packets. + */ + + if ((doepint & OTGFS_DOEPINT_XFRC) != 0) + { + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPOUT_XFRC), + (uint16_t)doepint); + + /* Clear the bit in DOEPINTn for this interrupt */ + + stm32_putreg(OTGFS_DOEPINT_XFRC, STM32_OTGFS_DOEPINT(epno)); + + /* Handle the RX transfer data ready event */ + + stm32_epout(priv, epno); + } + + /* Endpoint disabled interrupt (ignored because this interrupt is + * used in polled mode by the endpoint disable logic). + */ +#if 1 + /* REVISIT: */ + + if ((doepint & OTGFS_DOEPINT_EPDISD) != 0) + { + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPOUT_EPDISD), + (uint16_t)doepint); + + /* Clear the bit in DOEPINTn for this interrupt */ + + stm32_putreg(OTGFS_DOEPINT_EPDISD, STM32_OTGFS_DOEPINT(epno)); + } +#endif + + /* Setup Phase Done (control EPs) */ + + if ((doepint & OTGFS_DOEPINT_SETUP) != 0) + { + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPOUT_SETUP), + priv->ep0state); + + /* Handle the receipt of the IN SETUP packets now (OUT setup + * packet processing may be delayed until the accompanying + * OUT DATA is received) + */ + + if (priv->ep0state == EP0STATE_SETUP_READY) + { + stm32_ep0out_setup(priv); + } + + stm32_putreg(OTGFS_DOEPINT_SETUP, STM32_OTGFS_DOEPINT(epno)); + } + } + + epno++; + daint >>= 1; + } +} + +/**************************************************************************** + * Name: stm32_epin_runtestmode + * + * Description: + * Execute the test mode setup by the SET FEATURE request + * + ****************************************************************************/ + +static inline void stm32_epin_runtestmode(struct stm32_usbdev_s *priv) +{ + uint32_t regval = stm32_getreg(STM32_OTGFS_DCTL); + regval &= OTGFS_DCTL_TCTL_MASK; + regval |= (uint32_t)priv->testmode << OTGFS_DCTL_TCTL_SHIFT; + stm32_putreg(regval , STM32_OTGFS_DCTL); + + priv->dotest = 0; + priv->testmode = OTGFS_TESTMODE_DISABLED; +} + +/**************************************************************************** + * Name: stm32_epin + * + * Description: + * This is part of the IN endpoint interrupt processing. This function + * handles the IN event for a single endpoint. + * + ****************************************************************************/ + +static inline void stm32_epin(struct stm32_usbdev_s *priv, uint8_t epno) +{ + struct stm32_ep_s *privep = &priv->epin[epno]; + + /* Endpoint 0 is a special case. */ + + if (epno == 0) + { + /* In the EP0STATE_DATA_IN state, we are sending data from request + * buffer. In that case, we must continue the request processing. + */ + + if (priv->ep0state == EP0STATE_DATA_IN) + { + /* Continue processing data from the EP0 OUT request queue */ + + stm32_epin_request(priv, privep); + + /* If we are not actively processing an OUT request, then we + * need to setup to receive the next control request. + */ + + if (!privep->active) + { + stm32_ep0out_ctrlsetup(priv); + priv->ep0state = EP0STATE_IDLE; + } + } + + /* Test mode is another special case */ + + if (priv->dotest) + { + stm32_epin_runtestmode(priv); + } + } + + /* For other endpoints, the only possibility is that we are continuing + * or finishing an IN request. + */ + + else if (priv->devstate == DEVSTATE_CONFIGURED) + { + /* Continue processing data from the endpoint write request queue */ + + stm32_epin_request(priv, privep); + } +} + +/**************************************************************************** + * Name: stm32_epin_txfifoempty + * + * Description: + * TxFIFO empty interrupt handling + * + ****************************************************************************/ + +static inline void stm32_epin_txfifoempty(struct stm32_usbdev_s *priv, + int epno) +{ + struct stm32_ep_s *privep = &priv->epin[epno]; + + /* Continue processing the write request queue. This may mean sending + * more data from the existing request or terminating the current requests + * and (perhaps) starting the IN transfer from the next write request. + */ + + stm32_epin_request(priv, privep); +} + +/**************************************************************************** + * Name: stm32_epin_interrupt + * + * Description: + * USB IN endpoint interrupt handler. The core generates this interrupt + * when an interrupt is pending on one of the IN endpoints of the core. + * The driver must read the OTGFS DAINT register to determine the exact + * number of the IN endpoint on which the interrupt occurred, and then + * read the corresponding OTGFS DIEPINTx register to determine the exact + * cause of the interrupt. + * + ****************************************************************************/ + +static inline void stm32_epin_interrupt(struct stm32_usbdev_s *priv) +{ + uint32_t diepint; + uint32_t daint; + uint32_t mask; + uint32_t empty; + int epno; + + /* Get the pending, enabled interrupts for the IN endpoint from the + * endpoint interrupt status register. + */ + + daint = stm32_getreg(STM32_OTGFS_DAINT); + daint &= stm32_getreg(STM32_OTGFS_DAINTMSK); + daint &= OTGFS_DAINT_IEP_MASK; + + if (daint == 0) + { + /* We got an interrupt, but there is no unmasked endpoint that caused + * it ?! When this happens, the interrupt flag never gets cleared and + * we are stuck in infinite interrupt loop. + * + * This shouldn't happen if we are diligent about handling timing + * issues when masking endpoint interrupts. However, this workaround + * avoids infinite loop and allows operation to continue normally. It + * works by clearing each endpoint flags, masked or not. + */ + + daint = stm32_getreg(STM32_OTGFS_DAINT); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EPINUNEXPECTED), + (uint16_t)daint); + + daint &= OTGFS_DAINT_IEP_MASK; + epno = 0; + + while (daint) + { + if ((daint & 1) != 0) + { + uinfo("DIEPINT(%d) = %08" PRIx32 "\n", + epno, stm32_getreg(STM32_OTGFS_DIEPINT(epno))); + stm32_putreg(0xff, STM32_OTGFS_DIEPINT(epno)); + } + + epno++; + daint >>= 1; + } + + return; + } + + /* Process each pending IN endpoint interrupt */ + + epno = 0; + while (daint) + { + /* Is an IN interrupt pending for this endpoint? */ + + if ((daint & 1) != 0) + { + /* Get IN interrupt mask register. Bits 0-6 correspond to enabled + * interrupts as will be found in the DIEPINT interrupt status + * register. + */ + + mask = stm32_getreg(STM32_OTGFS_DIEPMSK); + + /* Check if the TxFIFO not empty interrupt is enabled for this + * endpoint in the DIEPMSK register. Bits n corresponds to + * endpoint n in the register. That condition corresponds to + * bit 7 of the DIEPINT interrupt status register. There is + * no TXFE bit in the mask register, so we fake one here. + */ + + empty = stm32_getreg(STM32_OTGFS_DIEPEMPMSK); + if ((empty & OTGFS_DIEPEMPMSK(epno)) != 0) + { + mask |= OTGFS_DIEPINT_TXFE; + } + + /* Now, read the interrupt status and mask out all disabled + * interrupts. + */ + + diepint = stm32_getreg(STM32_OTGFS_DIEPINT(epno)) & mask; + + /* Decode and process the enabled, pending interrupts */ + + /* Transfer completed interrupt */ + + if ((diepint & OTGFS_DIEPINT_XFRC) != 0) + { + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPIN_XFRC), + (uint16_t)diepint); + + /* It is possible that logic may be waiting for a the + * TxFIFO to become empty. We disable the TxFIFO empty + * interrupt here; it will be re-enabled if there is still + * insufficient space in the TxFIFO. + */ + + empty &= ~OTGFS_DIEPEMPMSK(epno); + stm32_putreg(empty, STM32_OTGFS_DIEPEMPMSK); + stm32_putreg(OTGFS_DIEPINT_XFRC, STM32_OTGFS_DIEPINT(epno)); + + /* IN transfer complete */ + + stm32_epin(priv, epno); + } + + /* Timeout condition */ + + if ((diepint & OTGFS_DIEPINT_TOC) != 0) + { + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPIN_TOC), + (uint16_t)diepint); + stm32_putreg(OTGFS_DIEPINT_TOC, STM32_OTGFS_DIEPINT(epno)); + } + + /* IN token received when TxFIFO is empty. Applies to + * non-periodic IN endpoints only. This interrupt indicates + * that an IN token was received when the associated TxFIFO + * (periodic/non-periodic) was empty. This interrupt is asserted + * on the endpoint for which the IN token was received. + */ + + if ((diepint & OTGFS_DIEPINT_ITTXFE) != 0) + { + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPIN_ITTXFE), + (uint16_t)diepint); + stm32_epin_request(priv, &priv->epin[epno]); + stm32_putreg(OTGFS_DIEPINT_ITTXFE, STM32_OTGFS_DIEPINT(epno)); + } + + /* IN endpoint NAK effective (ignored as this used only in polled + * mode) + */ +#if 0 + if ((diepint & OTGFS_DIEPINT_INEPNE) != 0) + { + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPIN_INEPNE), + (uint16_t)diepint); + stm32_putreg(OTGFS_DIEPINT_INEPNE, STM32_OTGFS_DIEPINT(epno)); + } +#endif + + /* Endpoint disabled interrupt (ignored as this used only in polled + * mode) + */ +#if 0 + if ((diepint & OTGFS_DIEPINT_EPDISD) != 0) + { + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPIN_EPDISD), + (uint16_t)diepint); + stm32_putreg(OTGFS_DIEPINT_EPDISD, STM32_OTGFS_DIEPINT(epno)); + } +#endif + + /* Transmit FIFO empty */ + + if ((diepint & OTGFS_DIEPINT_TXFE) != 0) + { + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPIN_TXFE), + (uint16_t)diepint); + + /* If we were waiting for TxFIFO to become empty, the we might + * have both XFRC and TXFE interrupts pending. Since we do + * the same thing for both cases, ignore the TXFE if we have + * already processed the XFRC. + */ + + if ((diepint & OTGFS_DIEPINT_XFRC) == 0) + { + /* Mask further FIFO empty interrupts. This will be + * re-enabled whenever we need to wait for a FIFO event. + */ + + empty &= ~OTGFS_DIEPEMPMSK(epno); + stm32_putreg(empty, STM32_OTGFS_DIEPEMPMSK); + + /* Handle TxFIFO empty */ + + stm32_epin_txfifoempty(priv, epno); + } + + /* Clear the pending TxFIFO empty interrupt */ + + stm32_putreg(OTGFS_DIEPINT_TXFE, STM32_OTGFS_DIEPINT(epno)); + } + } + + epno++; + daint >>= 1; + } +} + +/**************************************************************************** + * Name: stm32_resumeinterrupt + * + * Description: + * Resume/remote wakeup detected interrupt + * + ****************************************************************************/ + +static inline void stm32_resumeinterrupt(struct stm32_usbdev_s *priv) +{ + uint32_t regval; + + /* Restart the PHY clock and un-gate USB core clock (HCLK) */ + +#ifdef CONFIG_USBDEV_LOWPOWER + regval = stm32_getreg(STM32_OTGFS_PCGCCTL); + regval &= ~(OTGFS_PCGCCTL_STPPCLK | OTGFS_PCGCCTL_GATEHCLK); + stm32_putreg(regval, STM32_OTGFS_PCGCCTL); +#endif + + /* Clear remote wake-up signaling */ + + regval = stm32_getreg(STM32_OTGFS_DCTL); + regval &= ~OTGFS_DCTL_RWUSIG; + stm32_putreg(regval, STM32_OTGFS_DCTL); + + /* Restore full power -- whatever that means for this particular board */ + + stm32_usbsuspend((struct usbdev_s *)priv, true); + + /* Notify the class driver of the resume event */ + + if (priv->driver) + { + CLASS_RESUME(priv->driver, &priv->usbdev); + } +} + +/**************************************************************************** + * Name: stm32_suspendinterrupt + * + * Description: + * USB suspend interrupt + * + ****************************************************************************/ + +static inline void stm32_suspendinterrupt(struct stm32_usbdev_s *priv) +{ +#ifdef CONFIG_USBDEV_LOWPOWER + uint32_t regval; +#endif + + /* Notify the class driver of the suspend event */ + + if (priv->driver) + { + CLASS_SUSPEND(priv->driver, &priv->usbdev); + } + +#ifdef CONFIG_USBDEV_LOWPOWER + /* OTGFS_DSTS_SUSPSTS is set as long as the suspend condition is detected + * on USB. Check if we are still have the suspend condition, that we are + * connected to the host, and that we have been configured. + */ + + regval = stm32_getreg(STM32_OTGFS_DSTS); + + if ((regval & OTGFS_DSTS_SUSPSTS) != 0 && devstate == DEVSTATE_CONFIGURED) + { + /* Switch off OTG FS clocking. Setting OTGFS_PCGCCTL_STPPCLK stops the + * PHY clock. + */ + + regval = stm32_getreg(STM32_OTGFS_PCGCCTL); + regval |= OTGFS_PCGCCTL_STPPCLK; + stm32_putreg(regval, STM32_OTGFS_PCGCCTL); + + /* Setting OTGFS_PCGCCTL_GATEHCLK gate HCLK to modules other than + * the AHB Slave and Master and wakeup logic. + */ + + regval |= OTGFS_PCGCCTL_GATEHCLK; + stm32_putreg(regval, STM32_OTGFS_PCGCCTL); + } +#endif + + /* Let the board-specific logic know that we have entered the suspend + * state + */ + + stm32_usbsuspend((struct usbdev_s *)priv, false); +} + +/**************************************************************************** + * Name: stm32_rxinterrupt + * + * Description: + * RxFIFO non-empty interrupt. This interrupt indicates that there is at + * least one packet pending to be read from the RxFIFO. + * + ****************************************************************************/ + +static inline void stm32_rxinterrupt(struct stm32_usbdev_s *priv) +{ + struct stm32_ep_s *privep; + uint32_t regval; + int bcnt; + int epphy; + + /* Disable the Rx status queue level interrupt */ + + while (0 != (stm32_getreg(STM32_OTGFS_GINTSTS) & OTGFS_GINT_RXFLVL)) + { + /* Get the status from the top of the FIFO */ + + regval = stm32_getreg(STM32_OTGFS_GRXSTSP); + + /* Decode status fields */ + + epphy = (regval & OTGFS_GRXSTSD_EPNUM_MASK) >> + OTGFS_GRXSTSD_EPNUM_SHIFT; + + /* Workaround for bad values read from the STM32_OTGFS_GRXSTSP register + * happens regval is 0xb4e48168 or 0xa80c9367 or 267E781c + * All of which provide out of range indexes for epout[epphy] + */ + + if (epphy < STM32_NENDPOINTS) + { + privep = &priv->epout[epphy]; + + /* Handle the RX event according to the packet status field */ + + switch (regval & OTGFS_GRXSTSD_PKTSTS_MASK) + { + /* Global OUT NAK. This indicate that the global OUT NAK bit + * has taken effect. + * + * PKTSTS = Global OUT NAK, BCNT = 0, EPNUM = Don't Care, + * DPID = Don't Care. + */ + + case OTGFS_GRXSTSD_PKTSTS_OUTNAK: + { + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_OUTNAK), 0); + } + break; + + /* OUT data packet received. + * + * PKTSTS = DataOUT, BCNT = size of the received data OUT packet, + * EPNUM = EPNUM on which the packet was received, DPID = Actual + * Data PID. + */ + + case OTGFS_GRXSTSD_PKTSTS_OUTRECVD: + { + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_OUTRECVD), epphy); + bcnt = (regval & OTGFS_GRXSTSD_BCNT_MASK) >> + OTGFS_GRXSTSD_BCNT_SHIFT; + if (bcnt > 0) + { + stm32_epout_receive(privep, bcnt); + } + } + break; + + /* OUT transfer completed. This indicates that an OUT data + * transfer for the specified OUT endpoint has completed. + * After this entry is popped from the receive FIFO, the core + * asserts a Transfer Completed interrupt on the specified OUT + * endpoint. + * + * PKTSTS = Data OUT Transfer Done, BCNT = 0, EPNUM = OUT EP + * Num on which the data transfer is complete, DPID = Don't Care. + */ + + case OTGFS_GRXSTSD_PKTSTS_OUTDONE: + { + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_OUTDONE), epphy); + } + break; + + /* SETUP transaction completed. This indicates that the Setup + * stage for the specified endpoint has completed and the Data + * stage has started. + * After this entry is popped from the receive FIFO, the core + * asserts a Setup interrupt on the specified control OUT + * endpoint (triggers an interrupt). + * + * PKTSTS = Setup Stage Done, BCNT = 0, EPNUM = Control EP Num, + * DPID = Don't Care. + */ + + case OTGFS_GRXSTSD_PKTSTS_SETUPDONE: + { + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SETUPDONE), epphy); + + /* Now that the Setup Phase is complete if it was an OUT + * enable the endpoint + * (Doing this here prevents the loss of the first FIFO word) + */ + + if (priv->ep0state == EP0STATE_SETUP_OUT) + { + /* Clear NAKSTS so that we can receive the data */ + + regval = stm32_getreg(STM32_OTGFS_DOEPCTL0); + regval |= OTGFS_DOEPCTL0_CNAK; + stm32_putreg(regval, STM32_OTGFS_DOEPCTL0); + } + } + break; + + /* SETUP data packet received. This indicates that a SETUP + * packet for the specified endpoint is now available for + * reading from the receive FIFO. + * + * PKTSTS = SETUP, BCNT = 8, EPNUM = Control EP Num, DPID = D0. + */ + + case OTGFS_GRXSTSD_PKTSTS_SETUPRECVD: + { + uint16_t datlen; + + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SETUPRECVD), + epphy); + + /* Read EP0 setup data. NOTE: If multiple SETUP packets are + * received, the last one overwrites the previous setup + * packets and only that last SETUP packet will be processed. + */ + + stm32_rxfifo_read(&priv->epout[EP0], + (uint8_t *)&priv->ctrlreq, + USB_SIZEOF_CTRLREQ); + + /* Was this an IN or an OUT SETUP packet. If it is an OUT + * SETUP, then we need to wait for the completion of the + * data phase to process the setup command. If it is an + * IN SETUP packet, then we must processing the command + * BEFORE we enter the DATA phase. + * + * If the data associated with the OUT SETUP packet is zero + * length, then, of course, we don't need to wait. + */ + + datlen = GETUINT16(priv->ctrlreq.len); + if (USB_REQ_ISOUT(priv->ctrlreq.type) && datlen > 0) + { + /* Wait for the data phase. */ + + priv->ep0state = EP0STATE_SETUP_OUT; + priv->ep0datlen = 0; + } + else + { + /* We can process the setup data as soon as SETUP done + * word is popped of the RxFIFO. + */ + + priv->ep0state = EP0STATE_SETUP_READY; + } + } + break; + + default: + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), + (regval & OTGFS_GRXSTSD_PKTSTS_MASK) >> + OTGFS_GRXSTSD_PKTSTS_SHIFT); + } + break; + } + } + } +} + +/**************************************************************************** + * Name: stm32_enuminterrupt + * + * Description: + * Enumeration done interrupt + * + ****************************************************************************/ + +static inline void stm32_enuminterrupt(struct stm32_usbdev_s *priv) +{ + uint32_t regval; + + /* Activate EP0 */ + + stm32_ep0in_activate(); + + /* Set USB turn-around time for the full speed device with internal PHY + * interface. + */ + + regval = stm32_getreg(STM32_OTGFS_GUSBCFG); + regval &= ~OTGFS_GUSBCFG_TRDT_MASK; + regval |= OTGFS_GUSBCFG_TRDT(6); + stm32_putreg(regval, STM32_OTGFS_GUSBCFG); +} + +/**************************************************************************** + * Name: stm32_isocininterrupt + * + * Description: + * Incomplete isochronous IN transfer interrupt. Assertion of the + * incomplete isochronous IN transfer interrupt indicates an incomplete + * isochronous IN transfer on at least one of the isochronous IN endpoints. + * + ****************************************************************************/ + +#ifdef CONFIG_USBDEV_ISOCHRONOUS +static inline void stm32_isocininterrupt(struct stm32_usbdev_s *priv) +{ + int i; + + /* The application must read the endpoint control register for all + * isochronous IN endpoints to detect endpoints with incomplete IN data + * transfers. + */ + + for (i = 0; i < STM32_NENDPOINTS; i++) + { + /* Is this an isochronous IN endpoint? */ + + privep = &priv->epin[i]; + if (privep->eptype != USB_EP_ATTR_XFER_ISOC) + { + /* No... keep looking */ + + continue; + } + + /* Is there an active read request on the isochronous OUT endpoint? */ + + if (!privep->active) + { + /* No.. the endpoint is not actively transmitting data */ + + continue; + } + + /* Check if this is the endpoint that had the incomplete transfer */ + + regaddr = STM32_OTGFS_DIEPCTL(privep->epphy); + doepctl = stm32_getreg(regaddr); + dsts = stm32_getreg(STM32_OTGFS_DSTS); + + /* EONUM = 0:even frame, 1:odd frame + * SOFFN = Frame number of the received SOF + */ + + eonum = ((doepctl & OTGFS_DIEPCTL_EONUM) != 0); + soffn = ((dsts & OTGFS_DSTS_SOFFN0) != 0); + + if (eonum != soffn) + { + /* Not this endpoint */ + + continue; + } + + /* For isochronous IN endpoints with incomplete transfers, + * the application must discard the data in the memory and + * disable the endpoint. + */ + + stm32_req_complete(privep, -EIO); +#warning "Will clear OTGFS_DIEPCTL_USBAEP too" + stm32_epin_disable(privep); + break; + } +} +#endif + +/**************************************************************************** + * Name: stm32_isocoutinterrupt + * + * Description: + * Incomplete periodic transfer interrupt + * + ****************************************************************************/ + +#ifdef CONFIG_USBDEV_ISOCHRONOUS +static inline void stm32_isocoutinterrupt(struct stm32_usbdev_s *priv) +{ + struct stm32_ep_s *privep; + struct stm32_req_s *privreq; + uint32_t regaddr; + uint32_t doepctl; + uint32_t dsts; + bool eonum; + bool soffn; + + /* When it receives an IISOOXFR interrupt, the application must read the + * control registers of all isochronous OUT endpoints to determine which + * endpoints had an incomplete transfer in the current microframe. An + * endpoint transfer is incomplete if both the following conditions are + * true: + * + * DOEPCTLx:EONUM = DSTS:SOFFN[0], and + * DOEPCTLx:EPENA = 1 + */ + + for (i = 0; i < STM32_NENDPOINTS; i++) + { + /* Is this an isochronous OUT endpoint? */ + + privep = &priv->epout[i]; + if (privep->eptype != USB_EP_ATTR_XFER_ISOC) + { + /* No... keep looking */ + + continue; + } + + /* Is there an active read request on the isochronous OUT endpoint? */ + + if (!privep->active) + { + /* No.. the endpoint is not actively transmitting data */ + + continue; + } + + /* Check if this is the endpoint that had the incomplete transfer */ + + regaddr = STM32_OTGFS_DOEPCTL(privep->epphy); + doepctl = stm32_getreg(regaddr); + dsts = stm32_getreg(STM32_OTGFS_DSTS); + + /* EONUM = 0:even frame, 1:odd frame + * SOFFN = Frame number of the received SOF + */ + + eonum = ((doepctl & OTGFS_DOEPCTL_EONUM) != 0); + soffn = ((dsts & OTGFS_DSTS_SOFFN0) != 0); + + if (eonum != soffn) + { + /* Not this endpoint */ + + continue; + } + + /* For isochronous OUT endpoints with incomplete transfers, + * the application must discard the data in the memory and + * disable the endpoint. + */ + + stm32_req_complete(privep, -EIO); +#warning "Will clear OTGFS_DOEPCTL_USBAEP too" + stm32_epout_disable(privep); + break; + } +} +#endif + +/**************************************************************************** + * Name: stm32_sessioninterrupt + * + * Description: + * Session request/new session detected interrupt + * + ****************************************************************************/ + +#ifdef CONFIG_USBDEV_VBUSSENSING +static inline void stm32_sessioninterrupt(struct stm32_usbdev_s *priv) +{ +#warning "Missing logic" +} +#endif + +/**************************************************************************** + * Name: stm32_otginterrupt + * + * Description: + * OTG interrupt + * + ****************************************************************************/ + +#ifdef CONFIG_USBDEV_VBUSSENSING +static inline void stm32_otginterrupt(struct stm32_usbdev_s *priv) +{ + uint32_t regval; + + /* Check for session end detected */ + + regval = stm32_getreg(STM32_OTGFS_GOTGINT); + if ((regval & OTGFS_GOTGINT_SEDET) != 0) + { +#warning "Missing logic" + } + + /* Clear OTG interrupt */ + + stm32_putreg(regval, STM32_OTGFS_GOTGINT); +} +#endif + +/**************************************************************************** + * Name: stm32_usbinterrupt + * + * Description: + * USB interrupt handler + * + ****************************************************************************/ + +static int stm32_usbinterrupt(int irq, void *context, void *arg) +{ + /* At present, there is only a single OTG FS device support. Hence it is + * pre-allocated as g_otgfsdev. However, in most code, the private data + * structure will be referenced using the 'priv' pointer (rather than the + * global data) in order to simplify any future support for multiple + * devices. + */ + + struct stm32_usbdev_s *priv = &g_otgfsdev; + uint32_t regval; + uint32_t reserved; + + usbtrace(TRACE_INTENTRY(STM32_TRACEINTID_USB), 0); + + /* Assure that we are in device mode */ + + DEBUGASSERT((stm32_getreg(STM32_OTGFS_GINTSTS) & OTGFS_GINTSTS_CMOD) == + OTGFS_GINTSTS_DEVMODE); + + /* Get the state of all enabled interrupts. We will do this repeatedly + * some interrupts (like RXFLVL) will generate additional interrupting + * events. + */ + + for (; ; ) + { + /* Get the set of pending, un-masked interrupts */ + + regval = stm32_getreg(STM32_OTGFS_GINTSTS); + reserved = (regval & OTGFS_GINT_RESERVED); + regval &= stm32_getreg(STM32_OTGFS_GINTMSK); + + /* With out modifying the reserved bits, acknowledge all + * **Writable** pending irqs we will service below + */ + + stm32_putreg(((regval | reserved) & OTGFS_GINT_RC_W1), + STM32_OTGFS_GINTSTS); + + /* Break out of the loop when there are no further pending (and + * unmasked) interrupts to be processes. + */ + + if (regval == 0) + { + break; + } + + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_INTPENDING), + (uint16_t)regval); + + /* OUT endpoint interrupt. The core sets this bit to indicate that an + * interrupt is pending on one of the OUT endpoints of the core. + */ + + if ((regval & OTGFS_GINT_OEP) != 0) + { + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPOUT), + (uint16_t)regval); + stm32_epout_interrupt(priv); + } + + /* IN endpoint interrupt. The core sets this bit to indicate that + * an interrupt is pending on one of the IN endpoints of the core. + */ + + if ((regval & OTGFS_GINT_IEP) != 0) + { + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPIN), (uint16_t)regval); + stm32_epin_interrupt(priv); + } + + /* Host/device mode mismatch error interrupt */ + +#ifdef CONFIG_DEBUG_USB + if ((regval & OTGFS_GINT_MMIS) != 0) + { + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_MISMATCH), + (uint16_t)regval); + } +#endif + + /* Resume/remote wakeup detected interrupt */ + + if ((regval & OTGFS_GINT_WKUP) != 0) + { + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_WAKEUP), + (uint16_t)regval); + stm32_resumeinterrupt(priv); + } + + /* USB suspend interrupt */ + + if ((regval & OTGFS_GINT_USBSUSP) != 0) + { + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SUSPEND), + (uint16_t)regval); + stm32_suspendinterrupt(priv); + } + + /* Start of frame interrupt */ + +#ifdef CONFIG_USBDEV_SOFINTERRUPT + if ((regval & OTGFS_GINT_SOF) != 0) + { + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SOF), (uint16_t)regval); + usbdev_sof_irq(&priv->usbdev, stm32_getframe(&priv->usbdev)); + } +#endif + + /* RxFIFO non-empty interrupt. Indicates that there is at least one + * packet pending to be read from the RxFIFO. + */ + + if ((regval & OTGFS_GINT_RXFLVL) != 0) + { + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_RXFIFO), + (uint16_t)regval); + stm32_rxinterrupt(priv); + } + + /* USB reset interrupt */ + + if ((regval & OTGFS_GINT_RESETS) != 0) + { + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_DEVRESET), + (uint16_t)regval); + + /* Perform the device reset */ + + stm32_usbreset(priv); + usbtrace(TRACE_INTEXIT(STM32_TRACEINTID_USB), 0); + return OK; + } + + /* Enumeration done interrupt */ + + if ((regval & OTGFS_GINT_ENUMDNE) != 0) + { + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_ENUMDNE), + (uint16_t)regval); + stm32_enuminterrupt(priv); + } + + /* Incomplete isochronous IN transfer interrupt. When the core finds + * non-empty any of the isochronous IN endpoint FIFOs scheduled for + * the current frame non-empty, the core generates an IISOIXFR + * interrupt. + */ + +#ifdef CONFIG_USBDEV_ISOCHRONOUS + if ((regval & OTGFS_GINT_IISOIXFR) != 0) + { + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_IISOIXFR), + (uint16_t)regval); + stm32_isocininterrupt(priv); + } + + /* Incomplete isochronous OUT transfer. For isochronous OUT + * endpoints, the XFRC interrupt may not always be asserted. If the + * core drops isochronous OUT data packets, the application could fail + * to detect the XFRC interrupt. The incomplete Isochronous OUT data + * interrupt indicates that an XFRC interrupt was not asserted on at + * least one of the isochronous OUT endpoints. At this point, the + * endpoint with the incomplete transfer remains enabled, but no active + * transfers remain in progress on this endpoint on the USB. + */ + + if ((regval & OTGFS_GINT_IISOOXFR) != 0) + { + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_IISOOXFR), + (uint16_t)regval); + stm32_isocoutinterrupt(priv); + } +#endif + + /* Session request/new session detected interrupt */ + +#ifdef CONFIG_USBDEV_VBUSSENSING + if ((regval & OTGFS_GINT_SRQ) != 0) + { + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SRQ), (uint16_t)regval); + stm32_sessioninterrupt(priv); + } + + /* OTG interrupt */ + + if ((regval & OTGFS_GINT_OTG) != 0) + { + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_OTG), (uint16_t)regval); + stm32_otginterrupt(priv); + } +#endif + } + + usbtrace(TRACE_INTEXIT(STM32_TRACEINTID_USB), 0); + return OK; +} + +/**************************************************************************** + * Endpoint operations + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_enablegonak + * + * Description: + * Enable global OUT NAK mode + * + ****************************************************************************/ + +static void stm32_enablegonak(struct stm32_ep_s *privep) +{ + uint32_t regval; + + /* First, make sure that there is no GNOAKEFF interrupt pending. */ + +#if 0 + stm32_putreg(OTGFS_GINT_GONAKEFF, STM32_OTGFS_GINTSTS); +#endif + + /* Enable Global OUT NAK mode in the core. */ + + regval = stm32_getreg(STM32_OTGFS_DCTL); + regval |= OTGFS_DCTL_SGONAK; + stm32_putreg(regval, STM32_OTGFS_DCTL); + +#if 0 + /* Wait for the GONAKEFF interrupt that indicates that the OUT NAK + * mode is in effect. When the interrupt handler pops the OUTNAK word + * from the RxFIFO, the core sets the GONAKEFF interrupt. + */ + + while ((stm32_getreg(STM32_OTGFS_GINTSTS) & OTGFS_GINT_GONAKEFF) == 0); + stm32_putreg(OTGFS_GINT_GONAKEFF, STM32_OTGFS_GINTSTS); + +#else + /* Since we are in the interrupt handler, we cannot wait inline for the + * GONAKEFF because it cannot occur until service the RXFLVL global + * interrupt and pop the OUTNAK word from the RxFIFO. + * + * Perhaps it is sufficient to wait for Global OUT NAK status to be + * reported in OTGFS DCTL register? + */ + + while ((stm32_getreg(STM32_OTGFS_DCTL) & OTGFS_DCTL_GONSTS) == 0); +#endif +} + +/**************************************************************************** + * Name: stm32_disablegonak + * + * Description: + * Disable global OUT NAK mode + * + ****************************************************************************/ + +static void stm32_disablegonak(struct stm32_ep_s *privep) +{ + uint32_t regval; + + /* Set the "Clear the Global OUT NAK bit" to disable global OUT NAK mode */ + + regval = stm32_getreg(STM32_OTGFS_DCTL); + regval |= OTGFS_DCTL_CGONAK; + stm32_putreg(regval, STM32_OTGFS_DCTL); +} + +/**************************************************************************** + * Name: stm32_epout_configure + * + * Description: + * Configure an OUT endpoint, making it usable + * + * Input Parameters: + * privep - a pointer to an internal endpoint structure + * eptype - The type of the endpoint + * maxpacket - The max packet size of the endpoint + * + ****************************************************************************/ + +static int stm32_epout_configure(struct stm32_ep_s *privep, + uint8_t eptype, + uint16_t maxpacket) +{ + uint32_t mpsiz; + uint32_t regaddr; + uint32_t regval; + + usbtrace(TRACE_EPCONFIGURE, privep->epphy); + + /* For EP0, the packet size is encoded */ + + if (privep->epphy == EP0) + { + DEBUGASSERT(eptype == USB_EP_ATTR_XFER_CONTROL); + + /* Map the size in bytes to the encoded value in the register */ + + switch (maxpacket) + { + case 8: + mpsiz = OTGFS_DOEPCTL0_MPSIZ_8; + break; + + case 16: + mpsiz = OTGFS_DOEPCTL0_MPSIZ_16; + break; + + case 32: + mpsiz = OTGFS_DOEPCTL0_MPSIZ_32; + break; + + case 64: + mpsiz = OTGFS_DOEPCTL0_MPSIZ_64; + break; + + default: + uerr("ERROR: Unsupported maxpacket: %d\n", maxpacket); + return -EINVAL; + } + } + + /* For other endpoints, the packet size is in bytes */ + + else + { + mpsiz = (maxpacket << OTGFS_DOEPCTL_MPSIZ_SHIFT); + } + + /* If the endpoint is already active don't change the endpoint control + * register. + */ + + regaddr = STM32_OTGFS_DOEPCTL(privep->epphy); + regval = stm32_getreg(regaddr); + if ((regval & OTGFS_DOEPCTL_USBAEP) == 0) + { + if (regval & OTGFS_DOEPCTL_NAKSTS) + { + regval |= OTGFS_DOEPCTL_CNAK; + } + + regval &= ~(OTGFS_DOEPCTL_MPSIZ_MASK | OTGFS_DOEPCTL_EPTYP_MASK); + regval |= mpsiz; + regval |= (eptype << OTGFS_DOEPCTL_EPTYP_SHIFT); + regval |= (OTGFS_DOEPCTL_SD0PID | OTGFS_DOEPCTL_USBAEP); + stm32_putreg(regval, regaddr); + + /* Save the endpoint configuration */ + + privep->ep.maxpacket = maxpacket; + privep->eptype = eptype; + privep->stalled = false; + privep->active = false; + privep->zlp = false; + } + + /* Enable the interrupt for this endpoint */ + + regval = stm32_getreg(STM32_OTGFS_DAINTMSK); + regval |= OTGFS_DAINT_OEP(privep->epphy); + stm32_putreg(regval, STM32_OTGFS_DAINTMSK); + return OK; +} + +/**************************************************************************** + * Name: stm32_epin_configure + * + * Description: + * Configure an IN endpoint, making it usable + * + * Input Parameters: + * privep - a pointer to an internal endpoint structure + * eptype - The type of the endpoint + * maxpacket - The max packet size of the endpoint + * + ****************************************************************************/ + +static int stm32_epin_configure(struct stm32_ep_s *privep, + uint8_t eptype, + uint16_t maxpacket) +{ + uint32_t mpsiz; + uint32_t regaddr; + uint32_t regval; + + usbtrace(TRACE_EPCONFIGURE, privep->epphy); + + /* For EP0, the packet size is encoded */ + + if (privep->epphy == EP0) + { + DEBUGASSERT(eptype == USB_EP_ATTR_XFER_CONTROL); + + /* Map the size in bytes to the encoded value in the register */ + + switch (maxpacket) + { + case 8: + mpsiz = OTGFS_DIEPCTL0_MPSIZ_8; + break; + + case 16: + mpsiz = OTGFS_DIEPCTL0_MPSIZ_16; + break; + + case 32: + mpsiz = OTGFS_DIEPCTL0_MPSIZ_32; + break; + + case 64: + mpsiz = OTGFS_DIEPCTL0_MPSIZ_64; + break; + + default: + uerr("ERROR: Unsupported maxpacket: %d\n", maxpacket); + return -EINVAL; + } + } + + /* For other endpoints, the packet size is in bytes */ + + else + { + mpsiz = (maxpacket << OTGFS_DIEPCTL_MPSIZ_SHIFT); + } + + /* If the endpoint is already active don't change the endpoint control + * register. + */ + + regaddr = STM32_OTGFS_DIEPCTL(privep->epphy); + regval = stm32_getreg(regaddr); + if ((regval & OTGFS_DIEPCTL_USBAEP) == 0) + { + if (regval & OTGFS_DIEPCTL_NAKSTS) + { + regval |= OTGFS_DIEPCTL_CNAK; + } + + regval &= ~(OTGFS_DIEPCTL_MPSIZ_MASK | OTGFS_DIEPCTL_EPTYP_MASK | + OTGFS_DIEPCTL_TXFNUM_MASK); + regval |= mpsiz; + regval |= (eptype << OTGFS_DIEPCTL_EPTYP_SHIFT); + regval |= (privep->epphy << OTGFS_DIEPCTL_TXFNUM_SHIFT); + regval |= (OTGFS_DIEPCTL_SD0PID | OTGFS_DIEPCTL_USBAEP); + stm32_putreg(regval, regaddr); + + /* Save the endpoint configuration */ + + privep->ep.maxpacket = maxpacket; + privep->eptype = eptype; + privep->stalled = false; + privep->active = false; + privep->zlp = false; + } + + /* Enable the interrupt for this endpoint */ + + regval = stm32_getreg(STM32_OTGFS_DAINTMSK); + regval |= OTGFS_DAINT_IEP(privep->epphy); + stm32_putreg(regval, STM32_OTGFS_DAINTMSK); + + return OK; +} + +/**************************************************************************** + * Name: stm32_ep_configure + * + * Description: + * Configure endpoint, making it usable + * + * Input Parameters: + * ep - the struct usbdev_ep_s instance obtained from allocep() + * desc - A struct usb_epdesc_s instance describing the endpoint + * last - true if this this last endpoint to be configured. Some hardware + * needs to take special action when all of the endpoints have been + * configured. + * + ****************************************************************************/ + +static int stm32_ep_configure(struct usbdev_ep_s *ep, + const struct usb_epdesc_s *desc, + bool last) +{ + struct stm32_ep_s *privep = (struct stm32_ep_s *)ep; + uint16_t maxpacket; + uint8_t eptype; + int ret; + + usbtrace(TRACE_EPCONFIGURE, privep->epphy); + DEBUGASSERT(desc->addr == ep->eplog); + + /* Initialize EP capabilities */ + + maxpacket = GETUINT16(desc->mxpacketsize); + eptype = desc->attr & USB_EP_ATTR_XFERTYPE_MASK; + + /* Setup Endpoint Control Register */ + + if (privep->isin) + { + ret = stm32_epin_configure(privep, eptype, maxpacket); + } + else + { + ret = stm32_epout_configure(privep, eptype, maxpacket); + } + + return ret; +} + +/**************************************************************************** + * Name: stm32_ep0_configure + * + * Description: + * Reset Usb engine + * + ****************************************************************************/ + +static void stm32_ep0_configure(struct stm32_usbdev_s *priv) +{ + /* Enable EP0 IN and OUT */ + + stm32_epin_configure(&priv->epin[EP0], USB_EP_ATTR_XFER_CONTROL, + CONFIG_USBDEV_EP0_MAXSIZE); + stm32_epout_configure(&priv->epout[EP0], USB_EP_ATTR_XFER_CONTROL, + CONFIG_USBDEV_EP0_MAXSIZE); +} + +/**************************************************************************** + * Name: stm32_epout_disable + * + * Description: + * Disable an OUT endpoint will no longer be used + * + ****************************************************************************/ + +static void stm32_epout_disable(struct stm32_ep_s *privep) +{ + uint32_t regaddr; + uint32_t regval; + irqstate_t flags; + + usbtrace(TRACE_EPDISABLE, privep->epphy); + + /* Is this an IN or an OUT endpoint */ + + /* Before disabling any OUT endpoint, the application must enable + * Global OUT NAK mode in the core. + */ + + flags = enter_critical_section(); + stm32_enablegonak(privep); + + /* Disable the required OUT endpoint by setting the EPDIS and SNAK bits + * int DOECPTL register. + */ + + regaddr = STM32_OTGFS_DOEPCTL(privep->epphy); + regval = stm32_getreg(regaddr); + regval &= ~OTGFS_DOEPCTL_USBAEP; + regval |= (OTGFS_DOEPCTL_EPDIS | OTGFS_DOEPCTL_SNAK); + stm32_putreg(regval, regaddr); + + /* Wait for the EPDISD interrupt which indicates that the OUT + * endpoint is completely disabled. + */ + +#if 0 /* Doesn't happen */ + regaddr = STM32_OTGFS_DOEPINT(privep->epphy); + while ((stm32_getreg(regaddr) & OTGFS_DOEPINT_EPDISD) == 0); +#else + /* REVISIT: */ + + up_udelay(10); +#endif + + /* Clear the EPDISD interrupt indication */ + + stm32_putreg(OTGFS_DOEPINT_EPDISD, STM32_OTGFS_DOEPINT(privep->epphy)); + + /* Then disable the Global OUT NAK mode to continue receiving data + * from other non-disabled OUT endpoints. + */ + + stm32_disablegonak(privep); + + /* Disable endpoint interrupts */ + + regval = stm32_getreg(STM32_OTGFS_DAINTMSK); + regval &= ~OTGFS_DAINT_OEP(privep->epphy); + stm32_putreg(regval, STM32_OTGFS_DAINTMSK); + + /* Cancel any queued read requests */ + + stm32_req_cancel(privep, -ESHUTDOWN); + + leave_critical_section(flags); +} + +/**************************************************************************** + * Name: stm32_epin_disable + * + * Description: + * Disable an IN endpoint when it will no longer be used + * + ****************************************************************************/ + +static void stm32_epin_disable(struct stm32_ep_s *privep) +{ + uint32_t regaddr; + uint32_t regval; + irqstate_t flags; + + usbtrace(TRACE_EPDISABLE, privep->epphy); + + /* After USB reset, the endpoint will already be deactivated by the + * hardware. Trying to disable again will just hang in the wait. + */ + + regaddr = STM32_OTGFS_DIEPCTL(privep->epphy); + regval = stm32_getreg(regaddr); + if ((regval & OTGFS_DIEPCTL_USBAEP) == 0) + { + return; + } + + /* This INEPNE wait logic is suggested by reference manual, but seems + * to get stuck to infinite loop. + */ + +#if 0 + /* Make sure that there is no pending IPEPNE interrupt (because we are + * to poll this bit below). + */ + + stm32_putreg(OTGFS_DIEPINT_INEPNE, STM32_OTGFS_DIEPINT(privep->epphy)); + + /* Set the endpoint in NAK mode */ + + regaddr = STM32_OTGFS_DIEPCTL(privep->epphy); + regval = stm32_getreg(regaddr); + regval &= ~OTGFS_DIEPCTL_USBAEP; + regval |= (OTGFS_DIEPCTL_EPDIS | OTGFS_DIEPCTL_SNAK); + stm32_putreg(regval, regaddr); + + /* Wait for the INEPNE interrupt that indicates that we are now in NAK + * mode + */ + + regaddr = STM32_OTGFS_DIEPINT(privep->epphy); + while ((stm32_getreg(regaddr) & OTGFS_DIEPINT_INEPNE) == 0); + + /* Clear the INEPNE interrupt indication */ + + stm32_putreg(OTGFS_DIEPINT_INEPNE, regaddr); +#endif + + /* Deactivate and disable the endpoint by setting the EPDIS and SNAK bits + * the DIEPCTLx register. + */ + + flags = enter_critical_section(); + regaddr = STM32_OTGFS_DIEPCTL(privep->epphy); + regval = stm32_getreg(regaddr); + regval &= ~OTGFS_DIEPCTL_USBAEP; + regval |= (OTGFS_DIEPCTL_EPDIS | OTGFS_DIEPCTL_SNAK); + stm32_putreg(regval, regaddr); + + /* Wait for the EPDISD interrupt which indicates that the IN + * endpoint is completely disabled. + */ + + regaddr = STM32_OTGFS_DIEPINT(privep->epphy); + while ((stm32_getreg(regaddr) & OTGFS_DIEPINT_EPDISD) == 0); + + /* Clear the EPDISD interrupt indication */ + + stm32_putreg(OTGFS_DIEPINT_EPDISD, stm32_getreg(regaddr)); + + /* Flush any data remaining in the TxFIFO */ + + stm32_txfifo_flush(OTGFS_GRSTCTL_TXFNUM_D(privep->epphy)); + + /* Disable endpoint interrupts */ + + regval = stm32_getreg(STM32_OTGFS_DAINTMSK); + regval &= ~OTGFS_DAINT_IEP(privep->epphy); + stm32_putreg(regval, STM32_OTGFS_DAINTMSK); + + /* Cancel any queued write requests */ + + stm32_req_cancel(privep, -ESHUTDOWN); + leave_critical_section(flags); +} + +/**************************************************************************** + * Name: stm32_ep_disable + * + * Description: + * The endpoint will no longer be used + * + ****************************************************************************/ + +static int stm32_ep_disable(struct usbdev_ep_s *ep) +{ + struct stm32_ep_s *privep = (struct stm32_ep_s *)ep; + +#ifdef CONFIG_DEBUG_FEATURES + if (!ep) + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); + return -EINVAL; + } +#endif + + usbtrace(TRACE_EPDISABLE, privep->epphy); + + /* Is this an IN or an OUT endpoint */ + + if (privep->isin) + { + /* Disable the IN endpoint */ + + stm32_epin_disable(privep); + } + else + { + /* Disable the OUT endpoint */ + + stm32_epout_disable(privep); + } + + return OK; +} + +/**************************************************************************** + * Name: stm32_ep_allocreq + * + * Description: + * Allocate an I/O request + * + ****************************************************************************/ + +static struct usbdev_req_s *stm32_ep_allocreq(struct usbdev_ep_s *ep) +{ + struct stm32_req_s *privreq; + +#ifdef CONFIG_DEBUG_FEATURES + if (!ep) + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); + return NULL; + } +#endif + + usbtrace(TRACE_EPALLOCREQ, ((struct stm32_ep_s *)ep)->epphy); + + privreq = kmm_malloc(sizeof(struct stm32_req_s)); + if (!privreq) + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_ALLOCFAIL), 0); + return NULL; + } + + memset(privreq, 0, sizeof(struct stm32_req_s)); + return &privreq->req; +} + +/**************************************************************************** + * Name: stm32_ep_freereq + * + * Description: + * Free an I/O request + * + ****************************************************************************/ + +static void stm32_ep_freereq(struct usbdev_ep_s *ep, + struct usbdev_req_s *req) +{ + struct stm32_req_s *privreq = (struct stm32_req_s *)req; + +#ifdef CONFIG_DEBUG_FEATURES + if (!ep || !req) + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); + return; + } +#endif + + usbtrace(TRACE_EPFREEREQ, ((struct stm32_ep_s *)ep)->epphy); + kmm_free(privreq); +} + +/**************************************************************************** + * Name: stm32_ep_allocbuffer + * + * Description: + * Allocate an I/O buffer + * + ****************************************************************************/ + +#ifdef CONFIG_USBDEV_DMA +static void *stm32_ep_allocbuffer(struct usbdev_ep_s *ep, uint16_t bytes) +{ + usbtrace(TRACE_EPALLOCBUFFER, ((struct stm32_ep_s *)ep)->epphy); + +#ifdef CONFIG_USBDEV_DMAMEMORY + return usbdev_dma_alloc(bytes); +#else + return kmm_malloc(bytes); +#endif +} +#endif + +/**************************************************************************** + * Name: stm32_ep_freebuffer + * + * Description: + * Free an I/O buffer + * + ****************************************************************************/ + +#ifdef CONFIG_USBDEV_DMA +static void stm32_ep_freebuffer(struct usbdev_ep_s *ep, void *buf) +{ + usbtrace(TRACE_EPALLOCBUFFER, ((struct stm32_ep_s *)ep)->epphy); + +#ifdef CONFIG_USBDEV_DMAMEMORY + usbdev_dma_free(buf); +#else + kmm_free(buf); +#endif +} +#endif + +/**************************************************************************** + * Name: stm32_ep_submit + * + * Description: + * Submit an I/O request to the endpoint + * + ****************************************************************************/ + +static int stm32_ep_submit(struct usbdev_ep_s *ep, + struct usbdev_req_s *req) +{ + struct stm32_req_s *privreq = (struct stm32_req_s *)req; + struct stm32_ep_s *privep = (struct stm32_ep_s *)ep; + struct stm32_usbdev_s *priv; + irqstate_t flags; + int ret = OK; + + /* Some sanity checking */ + +#ifdef CONFIG_DEBUG_FEATURES + if (!req || !req->callback || !req->buf || !ep) + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); + uinfo("req=%p callback=%p buf=%p ep=%p\n", req, req->callback, + req->buf, ep); + return -EINVAL; + } +#endif + + usbtrace(TRACE_EPSUBMIT, privep->epphy); + priv = privep->dev; + +#ifdef CONFIG_DEBUG_FEATURES + if (!priv->driver) + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_NOTCONFIGURED), + priv->usbdev.speed); + return -ESHUTDOWN; + } +#endif + + /* Handle the request from the class driver */ + + req->result = -EINPROGRESS; + req->xfrd = 0; + + /* Disable Interrupts */ + + flags = enter_critical_section(); + + /* If we are stalled, then drop all requests on the floor */ + + if (privep->stalled) + { + ret = -EBUSY; + } + else + { + /* Add the new request to the request queue for the endpoint. */ + + if (stm32_req_addlast(privep, privreq) && !privep->active) + { + /* If a request was added to an IN endpoint, then attempt to send + * the request data buffer now. + */ + + if (privep->isin) + { + usbtrace(TRACE_INREQQUEUED(privep->epphy), privreq->req.len); + + /* If the endpoint is not busy with another write request, + * then process the newly received write request now. + */ + + if (!privep->active) + { + stm32_epin_request(priv, privep); + } + } + + /* If the request was added to an OUT endpoint, then attempt to + * setup a read into the request data buffer now (this will, of + * course, fail if there is already a read in place). + */ + + else + { + usbtrace(TRACE_OUTREQQUEUED(privep->epphy), privreq->req.len); + stm32_epout_request(priv, privep); + } + } + } + + leave_critical_section(flags); + return ret; +} + +/**************************************************************************** + * Name: stm32_ep_cancel + * + * Description: + * Cancel an I/O request previously sent to an endpoint + * + ****************************************************************************/ + +static int stm32_ep_cancel(struct usbdev_ep_s *ep, + struct usbdev_req_s *req) +{ + struct stm32_ep_s *privep = (struct stm32_ep_s *)ep; + irqstate_t flags; + +#ifdef CONFIG_DEBUG_FEATURES + if (!ep || !req) + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); + return -EINVAL; + } +#endif + + usbtrace(TRACE_EPCANCEL, privep->epphy); + + flags = enter_critical_section(); + + /* FIXME: if the request is the first, then we need to flush the EP + * otherwise just remove it from the list + * + * but ... all other implementations cancel all requests ... + */ + + stm32_req_cancel(privep, -ESHUTDOWN); + leave_critical_section(flags); + return OK; +} + +/**************************************************************************** + * Name: stm32_epout_setstall + * + * Description: + * Stall an OUT endpoint + * + ****************************************************************************/ + +static int stm32_epout_setstall(struct stm32_ep_s *privep) +{ +#if 1 + /* This implementation follows the requirements from the STM32 F4 reference + * manual. + */ + + uint32_t regaddr; + uint32_t regval; + + /* Put the core in the Global OUT NAK mode */ + + stm32_enablegonak(privep); + + /* Disable and STALL the OUT endpoint by setting the EPDIS and STALL bits + * in the DOECPTL register. + */ + + regaddr = STM32_OTGFS_DOEPCTL(privep->epphy); + regval = stm32_getreg(regaddr); + regval |= (OTGFS_DOEPCTL_EPDIS | OTGFS_DOEPCTL_STALL); + stm32_putreg(regval, regaddr); + + /* Wait for the EPDISD interrupt which indicates that the OUT + * endpoint is completely disabled. + */ + +#if 0 /* Doesn't happen */ + regaddr = STM32_OTGFS_DOEPINT(privep->epphy); + while ((stm32_getreg(regaddr) & OTGFS_DOEPINT_EPDISD) == 0); +#else + /* REVISIT: */ + + up_udelay(10); +#endif + + /* Disable Global OUT NAK mode */ + + stm32_disablegonak(privep); + + /* The endpoint is now stalled */ + + privep->stalled = true; + return OK; +#else + /* This implementation follows the STMicro code example. */ + + /* REVISIT: */ + + uint32_t regaddr; + uint32_t regval; + + /* Stall the OUT endpoint by setting the STALL bit in the DOECPTL + * register. + */ + + regaddr = STM32_OTGFS_DOEPCTL(privep->epphy); + regval = stm32_getreg(regaddr); + regval |= OTGFS_DOEPCTL_STALL; + stm32_putreg(regval, regaddr); + + /* The endpoint is now stalled */ + + privep->stalled = true; + return OK; +#endif +} + +/**************************************************************************** + * Name: stm32_epin_setstall + * + * Description: + * Stall an IN endpoint + * + ****************************************************************************/ + +static int stm32_epin_setstall(struct stm32_ep_s *privep) +{ + uint32_t regaddr; + uint32_t regval; + + /* Get the IN endpoint device control register */ + + regaddr = STM32_OTGFS_DIEPCTL(privep->epphy); + regval = stm32_getreg(regaddr); + + /* Then stall the endpoint */ + + regval |= OTGFS_DIEPCTL_STALL; + stm32_putreg(regval, regaddr); + + /* The endpoint is now stalled */ + + privep->stalled = true; + return OK; +} + +/**************************************************************************** + * Name: stm32_ep_setstall + * + * Description: + * Stall an endpoint + * + ****************************************************************************/ + +static int stm32_ep_setstall(struct stm32_ep_s *privep) +{ + usbtrace(TRACE_EPSTALL, privep->epphy); + + /* Is this an IN endpoint? */ + + if (privep->isin == 1) + { + return stm32_epin_setstall(privep); + } + else + { + return stm32_epout_setstall(privep); + } +} + +/**************************************************************************** + * Name: stm32_ep_clrstall + * + * Description: + * Resume a stalled endpoint + * + ****************************************************************************/ + +static int stm32_ep_clrstall(struct stm32_ep_s *privep) +{ + uint32_t regaddr; + uint32_t regval; + uint32_t stallbit; + uint32_t data0bit; + + usbtrace(TRACE_EPRESUME, privep->epphy); + + /* Is this an IN endpoint? */ + + if (privep->isin == 1) + { + /* Clear the stall bit in the IN endpoint device control register */ + + regaddr = STM32_OTGFS_DIEPCTL(privep->epphy); + stallbit = OTGFS_DIEPCTL_STALL; + data0bit = OTGFS_DIEPCTL_SD0PID; + } + else + { + /* Clear the stall bit in the IN endpoint device control register */ + + regaddr = STM32_OTGFS_DOEPCTL(privep->epphy); + stallbit = OTGFS_DOEPCTL_STALL; + data0bit = OTGFS_DOEPCTL_SD0PID; + } + + /* Clear the stall bit */ + + regval = stm32_getreg(regaddr); + regval &= ~stallbit; + + /* Set the DATA0 pid for interrupt and bulk endpoints */ + + if (privep->eptype == USB_EP_ATTR_XFER_INT || + privep->eptype == USB_EP_ATTR_XFER_BULK) + { + /* Writing this bit sets the DATA0 PID */ + + regval |= data0bit; + } + + stm32_putreg(regval, regaddr); + + /* The endpoint is no longer stalled */ + + privep->stalled = false; + return OK; +} + +/**************************************************************************** + * Name: stm32_ep_stall + * + * Description: + * Stall or resume an endpoint + * + ****************************************************************************/ + +static int stm32_ep_stall(struct usbdev_ep_s *ep, bool resume) +{ + struct stm32_ep_s *privep = (struct stm32_ep_s *)ep; + irqstate_t flags; + int ret; + + /* Set or clear the stall condition as requested */ + + flags = enter_critical_section(); + if (resume) + { + ret = stm32_ep_clrstall(privep); + } + else + { + ret = stm32_ep_setstall(privep); + } + + leave_critical_section(flags); + + return ret; +} + +/**************************************************************************** + * Name: stm32_ep0_stall + * + * Description: + * Stall endpoint 0 + * + ****************************************************************************/ + +static void stm32_ep0_stall(struct stm32_usbdev_s *priv) +{ + stm32_epin_setstall(&priv->epin[EP0]); + stm32_epout_setstall(&priv->epout[EP0]); + priv->stalled = true; + stm32_ep0out_ctrlsetup(priv); +} + +/**************************************************************************** + * Device operations + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_ep_alloc + * + * Description: + * Allocate an endpoint matching the parameters. + * + * Input Parameters: + * eplog - 7-bit logical endpoint number (direction bit ignored). + * Zero means that any endpoint matching the other requirements + * will suffice. The assigned endpoint can be found in the eplog + * field. + * in - true: IN (device-to-host) endpoint requested + * eptype - Endpoint type. One of {USB_EP_ATTR_XFER_ISOC, + * USB_EP_ATTR_XFER_BULK, USB_EP_ATTR_XFER_INT} + * + ****************************************************************************/ + +static struct usbdev_ep_s *stm32_ep_alloc(struct usbdev_s *dev, + uint8_t eplog, bool in, + uint8_t eptype) +{ + struct stm32_usbdev_s *priv = (struct stm32_usbdev_s *)dev; + uint8_t epavail; + irqstate_t flags; + int epphy; + int epno = 0; + + usbtrace(TRACE_DEVALLOCEP, (uint16_t)eplog); + + /* Ignore any direction bits in the logical address */ + + epphy = USB_EPNO(eplog); + + /* Get the set of available endpoints depending on the direction */ + + flags = enter_critical_section(); + epavail = priv->epavail[in]; + + /* A physical address of 0 means that any endpoint will do */ + + if (epphy > 0) + { + /* Otherwise, we will return the endpoint structure only for the + * requested 'logical' endpoint. All of the other checks will still + * be performed. + * + * First, verify that the logical endpoint is in the range supported by + * by the hardware. + */ + + if (epphy >= STM32_NENDPOINTS) + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADEPNO), (uint16_t)epphy); + return NULL; + } + + /* Remove all of the candidate endpoints from the bitset except for the + * this physical endpoint number. + */ + + epavail &= (1 << epphy); + } + + /* Is there an available endpoint? */ + + if (epavail) + { + /* Yes.. Select the lowest numbered endpoint in the set of available + * endpoints. + */ + + for (epno = 1; epno < STM32_NENDPOINTS; epno++) + { + uint8_t bit = 1 << epno; + if ((epavail & bit) != 0) + { + /* Mark the endpoint no longer available */ + + priv->epavail[in] &= ~(1 << epno); + + /* And return the pointer to the standard endpoint structure */ + + leave_critical_section(flags); + return in ? &priv->epin[epno].ep : &priv->epout[epno].ep; + } + } + + /* We should not get here */ + } + + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_NOEP), (uint16_t)eplog); + leave_critical_section(flags); + return NULL; +} + +/**************************************************************************** + * Name: stm32_ep_free + * + * Description: + * Free the previously allocated endpoint + * + ****************************************************************************/ + +static void stm32_ep_free(struct usbdev_s *dev, + struct usbdev_ep_s *ep) +{ + struct stm32_usbdev_s *priv = (struct stm32_usbdev_s *)dev; + struct stm32_ep_s *privep = (struct stm32_ep_s *)ep; + irqstate_t flags; + + usbtrace(TRACE_DEVFREEEP, (uint16_t)privep->epphy); + + if (priv && privep) + { + /* Mark the endpoint as available */ + + flags = enter_critical_section(); + priv->epavail[privep->isin] |= (1 << privep->epphy); + leave_critical_section(flags); + } +} + +/**************************************************************************** + * Name: stm32_getframe + * + * Description: + * Returns the current frame number + * + ****************************************************************************/ + +static int stm32_getframe(struct usbdev_s *dev) +{ + uint32_t regval; + + usbtrace(TRACE_DEVGETFRAME, 0); + + /* Return the last frame number of the last SOF detected by the hardware */ + + regval = stm32_getreg(STM32_OTGFS_DSTS); + return (int)((regval & OTGFS_DSTS_SOFFN_MASK) >> OTGFS_DSTS_SOFFN_SHIFT); +} + +/**************************************************************************** + * Name: stm32_wakeup + * + * Description: + * Exit suspend mode. + * + ****************************************************************************/ + +static int stm32_wakeup(struct usbdev_s *dev) +{ + struct stm32_usbdev_s *priv = (struct stm32_usbdev_s *)dev; + uint32_t regval; + irqstate_t flags; + + usbtrace(TRACE_DEVWAKEUP, 0); + + /* Is wakeup enabled? */ + + flags = enter_critical_section(); + if (priv->wakeup) + { + /* Yes... is the core suspended? */ + + regval = stm32_getreg(STM32_OTGFS_DSTS); + if ((regval & OTGFS_DSTS_SUSPSTS) != 0) + { + /* Re-start the PHY clock and un-gate USB core clock (HCLK) */ + +#ifdef CONFIG_USBDEV_LOWPOWER + regval = stm32_getreg(STM32_OTGFS_PCGCCTL); + regval &= ~(OTGFS_PCGCCTL_STPPCLK | OTGFS_PCGCCTL_GATEHCLK); + stm32_putreg(regval, STM32_OTGFS_PCGCCTL); +#endif + /* Activate Remote wakeup signaling */ + + regval = stm32_getreg(STM32_OTGFS_DCTL); + regval |= OTGFS_DCTL_RWUSIG; + stm32_putreg(regval, STM32_OTGFS_DCTL); + up_mdelay(5); + regval &= ~OTGFS_DCTL_RWUSIG; + stm32_putreg(regval, STM32_OTGFS_DCTL); + } + } + + leave_critical_section(flags); + return OK; +} + +/**************************************************************************** + * Name: stm32_selfpowered + * + * Description: + * Sets/clears the device self-powered feature + * + ****************************************************************************/ + +static int stm32_selfpowered(struct usbdev_s *dev, bool selfpowered) +{ + struct stm32_usbdev_s *priv = (struct stm32_usbdev_s *)dev; + + usbtrace(TRACE_DEVSELFPOWERED, (uint16_t)selfpowered); + +#ifdef CONFIG_DEBUG_FEATURES + if (!dev) + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); + return -ENODEV; + } +#endif + + priv->selfpowered = selfpowered; + return OK; +} + +/**************************************************************************** + * Name: stm32_pullup + * + * Description: + * Software-controlled connect to/disconnect from USB host + * + ****************************************************************************/ + +static int stm32_pullup(struct usbdev_s *dev, bool enable) +{ + uint32_t regval; + + usbtrace(TRACE_DEVPULLUP, (uint16_t)enable); + + irqstate_t flags = enter_critical_section(); + regval = stm32_getreg(STM32_OTGFS_DCTL); + if (enable) + { + /* Connect the device by clearing the soft disconnect bit in the DCTL + * register + */ + + regval &= ~OTGFS_DCTL_SDIS; + } + else + { + /* Connect the device by setting the soft disconnect bit in the DCTL + * register + */ + + regval |= OTGFS_DCTL_SDIS; + } + + stm32_putreg(regval, STM32_OTGFS_DCTL); + leave_critical_section(flags); + return OK; +} + +/**************************************************************************** + * Name: stm32_setaddress + * + * Description: + * Set the devices USB address + * + ****************************************************************************/ + +static void stm32_setaddress(struct stm32_usbdev_s *priv, uint16_t address) +{ + uint32_t regval; + + /* Set the device address in the DCFG register */ + + regval = stm32_getreg(STM32_OTGFS_DCFG); + regval &= ~OTGFS_DCFG_DAD_MASK; + regval |= ((uint32_t)address << OTGFS_DCFG_DAD_SHIFT); + stm32_putreg(regval, STM32_OTGFS_DCFG); + + /* Are we now addressed? (i.e., do we have a non-NULL device + * address?) + */ + + if (address != 0) + { + priv->devstate = DEVSTATE_ADDRESSED; + priv->addressed = true; + } + else + { + priv->devstate = DEVSTATE_DEFAULT; + priv->addressed = false; + } +} + +/**************************************************************************** + * Name: stm32_txfifo_flush + * + * Description: + * Flush the specific TX fifo. + * + ****************************************************************************/ + +static int stm32_txfifo_flush(uint32_t txfnum) +{ + uint32_t regval; + uint32_t timeout; + + /* Initiate the TX FIFO flush operation */ + + regval = OTGFS_GRSTCTL_TXFFLSH | txfnum; + stm32_putreg(regval, STM32_OTGFS_GRSTCTL); + + /* Wait for the FLUSH to complete */ + + for (timeout = 0; timeout < STM32_FLUSH_DELAY; timeout++) + { + regval = stm32_getreg(STM32_OTGFS_GRSTCTL); + if ((regval & OTGFS_GRSTCTL_TXFFLSH) == 0) + { + break; + } + } + + /* Wait for 3 PHY Clocks */ + + up_udelay(3); + return OK; +} + +/**************************************************************************** + * Name: stm32_rxfifo_flush + * + * Description: + * Flush the RX fifo. + * + ****************************************************************************/ + +static int stm32_rxfifo_flush(void) +{ + uint32_t regval; + uint32_t timeout; + + /* Initiate the RX FIFO flush operation */ + + stm32_putreg(OTGFS_GRSTCTL_RXFFLSH, STM32_OTGFS_GRSTCTL); + + /* Wait for the FLUSH to complete */ + + for (timeout = 0; timeout < STM32_FLUSH_DELAY; timeout++) + { + regval = stm32_getreg(STM32_OTGFS_GRSTCTL); + if ((regval & OTGFS_GRSTCTL_RXFFLSH) == 0) + { + break; + } + } + + /* Wait for 3 PHY Clocks */ + + up_udelay(3); + return OK; +} + +/**************************************************************************** + * Name: stm32_swinitialize + * + * Description: + * Initialize all driver data structures. + * + ****************************************************************************/ + +static void stm32_swinitialize(struct stm32_usbdev_s *priv) +{ + struct stm32_ep_s *privep; + int i; + + /* Initialize the device state structure */ + + memset(priv, 0, sizeof(struct stm32_usbdev_s)); + + priv->usbdev.ops = &g_devops; + priv->usbdev.ep0 = &priv->epin[EP0].ep; + + priv->epavail[0] = STM32_EP_AVAILABLE; + priv->epavail[1] = STM32_EP_AVAILABLE; + + /* Initialize the endpoint lists */ + + for (i = 0; i < STM32_NENDPOINTS; i++) + { + /* Set endpoint operations, reference to driver structure (not + * really necessary because there is only one controller), and + * the physical endpoint number (which is just the index to the + * endpoint). + */ + + privep = &priv->epin[i]; + privep->ep.ops = &g_epops; + privep->dev = priv; + privep->isin = 1; + + /* The index, i, is the physical endpoint address; Map this + * to a logical endpoint address usable by the class driver. + */ + + privep->epphy = i; + privep->ep.eplog = STM32_EPPHYIN2LOG(i); + + /* Control until endpoint is activated */ + + privep->eptype = USB_EP_ATTR_XFER_CONTROL; + privep->ep.maxpacket = CONFIG_USBDEV_EP0_MAXSIZE; + } + + /* Initialize the endpoint lists */ + + for (i = 0; i < STM32_NENDPOINTS; i++) + { + /* Set endpoint operations, reference to driver structure (not + * really necessary because there is only one controller), and + * the physical endpoint number (which is just the index to the + * endpoint). + */ + + privep = &priv->epout[i]; + privep->ep.ops = &g_epops; + privep->dev = priv; + + /* The index, i, is the physical endpoint address; Map this + * to a logical endpoint address usable by the class driver. + */ + + privep->epphy = i; + privep->ep.eplog = STM32_EPPHYOUT2LOG(i); + + /* Control until endpoint is activated */ + + privep->eptype = USB_EP_ATTR_XFER_CONTROL; + privep->ep.maxpacket = CONFIG_USBDEV_EP0_MAXSIZE; + } +} + +/**************************************************************************** + * Name: stm32_hwinitialize + * + * Description: + * Configure the OTG FS core for operation. + * + ****************************************************************************/ + +static void stm32_hwinitialize(struct stm32_usbdev_s *priv) +{ + uint32_t regval; + uint32_t timeout; + uint32_t address; + int i; + + /* At start-up the core is in FS mode. */ + + /* Disable global interrupts by clearing the GINTMASK bit in the GAHBCFG + * register; Set the TXFELVL bit in the GAHBCFG register so that TxFIFO + * interrupts will occur when the TxFIFO is truly empty (not just half + * full). + */ + + stm32_putreg(OTGFS_GAHBCFG_TXFELVL, STM32_OTGFS_GAHBCFG); + + /* Common USB OTG core initialization */ + + /* Reset after a PHY select and set Host mode. First, wait for AHB master + * IDLE state. + */ + + for (timeout = 0; timeout < STM32_READY_DELAY; timeout++) + { + up_udelay(3); + regval = stm32_getreg(STM32_OTGFS_GRSTCTL); + if ((regval & OTGFS_GRSTCTL_AHBIDL) != 0) + { + break; + } + } + + /* Then perform the core soft reset. */ + + stm32_putreg(OTGFS_GRSTCTL_CSRST, STM32_OTGFS_GRSTCTL); + for (timeout = 0; timeout < STM32_READY_DELAY; timeout++) + { + regval = stm32_getreg(STM32_OTGFS_GRSTCTL); + if ((regval & OTGFS_GRSTCTL_CSRST) == 0) + { + break; + } + } + + /* Wait for 3 PHY Clocks */ + + up_udelay(3); + + /* Deactivate the power down */ + +#if defined(CONFIG_STM32_STM32F446) || defined(CONFIG_STM32_STM32F469) + /* In the case of the STM32F446 or STM32F469 the meaning of the bit + * has changed to VBUS Detection Enable when set + */ + + regval = OTGFS_GCCFG_PWRDWN; + +# ifdef CONFIG_USBDEV_VBUSSENSING + regval |= OTGFS_GCCFG_VBDEN; +# endif + +#else + /* In the case of the all others the meaning of the bit is No VBUS + * Sense when Set + */ + + regval = (OTGFS_GCCFG_PWRDWN | OTGFS_GCCFG_VBUSASEN | + OTGFS_GCCFG_VBUSBSEN); +# ifndef CONFIG_USBDEV_VBUSSENSING + regval |= OTGFS_GCCFG_NOVBUSSENS; +# endif +# ifdef CONFIG_STM32_OTGFS_SOFOUTPUT + regval |= OTGFS_GCCFG_SOFOUTEN; +# endif +#endif + stm32_putreg(regval, STM32_OTGFS_GCCFG); + up_mdelay(20); + + /* For the new OTG controller in the F446, F469 when VBUS sensing is not + * used we need to force the B session valid + */ + +#if defined(CONFIG_STM32_STM32F446) || defined(CONFIG_STM32_STM32F469) +# ifndef CONFIG_USBDEV_VBUSSENSING + regval = stm32_getreg(STM32_OTGFS_GOTGCTL); + regval |= (OTGFS_GOTGCTL_BVALOEN | OTGFS_GOTGCTL_BVALOVAL); + stm32_putreg(regval, STM32_OTGFS_GOTGCTL); +# endif +#endif + + /* Force Device Mode */ + + regval = stm32_getreg(STM32_OTGFS_GUSBCFG); + regval &= ~OTGFS_GUSBCFG_FHMOD; + regval |= OTGFS_GUSBCFG_FDMOD; + stm32_putreg(regval, STM32_OTGFS_GUSBCFG); + up_mdelay(50); + + /* Initialize device mode */ + + /* Restart the PHY Clock */ + + stm32_putreg(0, STM32_OTGFS_PCGCCTL); + + /* Device configuration register */ + + regval = stm32_getreg(STM32_OTGFS_DCFG); + regval &= ~OTGFS_DCFG_PFIVL_MASK; + regval |= OTGFS_DCFG_PFIVL_80PCT; + stm32_putreg(regval, STM32_OTGFS_DCFG); + + /* Set full speed PHY */ + + regval = stm32_getreg(STM32_OTGFS_DCFG); + regval &= ~OTGFS_DCFG_DSPD_MASK; + regval |= OTGFS_DCFG_DSPD_FS; + stm32_putreg(regval, STM32_OTGFS_DCFG); + + /* Set Rx FIFO size */ + + stm32_putreg(STM32_RXFIFO_WORDS, STM32_OTGFS_GRXFSIZ); + + /* EP0 TX */ + + address = STM32_RXFIFO_WORDS; + regval = (address << OTGFS_DIEPTXF0_TX0FD_SHIFT) | + (STM32_EP0_TXFIFO_WORDS << OTGFS_DIEPTXF0_TX0FSA_SHIFT); + stm32_putreg(regval, STM32_OTGFS_DIEPTXF0); + + /* EP1 TX */ + + address += STM32_EP0_TXFIFO_WORDS; + regval = (address << OTGFS_DIEPTXF_INEPTXSA_SHIFT) | + (STM32_EP1_TXFIFO_WORDS << OTGFS_DIEPTXF_INEPTXFD_SHIFT); + stm32_putreg(regval, STM32_OTGFS_DIEPTXF1); + + /* EP2 TX */ + + address += STM32_EP1_TXFIFO_WORDS; + regval = (address << OTGFS_DIEPTXF_INEPTXSA_SHIFT) | + (STM32_EP2_TXFIFO_WORDS << OTGFS_DIEPTXF_INEPTXFD_SHIFT); + stm32_putreg(regval, STM32_OTGFS_DIEPTXF2); + + /* EP3 TX */ + + address += STM32_EP2_TXFIFO_WORDS; + regval = (address << OTGFS_DIEPTXF_INEPTXSA_SHIFT) | + (STM32_EP3_TXFIFO_WORDS << OTGFS_DIEPTXF_INEPTXFD_SHIFT); + stm32_putreg(regval, STM32_OTGFS_DIEPTXF3); + + /* Flush the FIFOs */ + + stm32_txfifo_flush(OTGFS_GRSTCTL_TXFNUM_DALL); + stm32_rxfifo_flush(); + + /* Clear all pending Device Interrupts */ + + stm32_putreg(0, STM32_OTGFS_DIEPMSK); + stm32_putreg(0, STM32_OTGFS_DOEPMSK); + stm32_putreg(0, STM32_OTGFS_DIEPEMPMSK); + stm32_putreg(0xffffffff, STM32_OTGFS_DAINT); + stm32_putreg(0, STM32_OTGFS_DAINTMSK); + + /* Configure all IN endpoints */ + + for (i = 0; i < STM32_NENDPOINTS; i++) + { + regval = stm32_getreg(STM32_OTGFS_DIEPCTL(i)); + if ((regval & OTGFS_DIEPCTL_EPENA) != 0) + { + /* The endpoint is already enabled */ + + regval = OTGFS_DIEPCTL_EPENA | OTGFS_DIEPCTL_SNAK; + } + else + { + regval = 0; + } + + stm32_putreg(regval, STM32_OTGFS_DIEPCTL(i)); + stm32_putreg(0, STM32_OTGFS_DIEPTSIZ(i)); + stm32_putreg(0xff, STM32_OTGFS_DIEPINT(i)); + } + + /* Configure all OUT endpoints */ + + for (i = 0; i < STM32_NENDPOINTS; i++) + { + regval = stm32_getreg(STM32_OTGFS_DOEPCTL(i)); + if ((regval & OTGFS_DOEPCTL_EPENA) != 0) + { + /* The endpoint is already enabled */ + + regval = OTGFS_DOEPCTL_EPENA | OTGFS_DOEPCTL_SNAK; + } + else + { + regval = 0; + } + + stm32_putreg(regval, STM32_OTGFS_DOEPCTL(i)); + stm32_putreg(0, STM32_OTGFS_DOEPTSIZ(i)); + stm32_putreg(0xff, STM32_OTGFS_DOEPINT(i)); + } + + /* Disable all interrupts. */ + + stm32_putreg(0, STM32_OTGFS_GINTMSK); + + /* Clear any pending USB_OTG Interrupts */ + + stm32_putreg(0xffffffff, STM32_OTGFS_GOTGINT); + + /* Clear any pending interrupts */ + + regval = stm32_getreg(STM32_OTGFS_GINTSTS); + regval &= OTGFS_GINT_RESERVED; + stm32_putreg(regval | OTGFS_GINT_RC_W1, STM32_OTGFS_GINTSTS); + + /* Enable the interrupts in the INTMSK */ + + regval = (OTGFS_GINT_RXFLVL | OTGFS_GINT_USBSUSP | OTGFS_GINT_ENUMDNE | + OTGFS_GINT_IEP | OTGFS_GINT_OEP | OTGFS_GINT_USBRST); + +#ifdef CONFIG_USBDEV_ISOCHRONOUS + regval |= (OTGFS_GINT_IISOIXFR | OTGFS_GINT_IISOOXFR); +#endif + +#ifdef CONFIG_USBDEV_SOFINTERRUPT + regval |= OTGFS_GINT_SOF; +#endif + +#ifdef CONFIG_USBDEV_VBUSSENSING + regval |= (OTGFS_GINT_OTG | OTGFS_GINT_SRQ); +#endif + +#ifdef CONFIG_DEBUG_USB + regval |= OTGFS_GINT_MMIS; +#endif + + stm32_putreg(regval, STM32_OTGFS_GINTMSK); + + /* Enable the USB global interrupt by setting GINTMSK in the global OTG + * FS AHB configuration register; Set the TXFELVL bit in the GAHBCFG + * register so that TxFIFO interrupts will occur when the TxFIFO is truly + * empty (not just half full). + */ + + stm32_putreg(OTGFS_GAHBCFG_GINTMSK | OTGFS_GAHBCFG_TXFELVL, + STM32_OTGFS_GAHBCFG); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: arm_usbinitialize + * + * Description: + * Initialize USB hardware. + * + * Assumptions: + * - This function is called very early in the initialization sequence + * - PLL and GIO pin initialization is not performed here but should been in + * the low-level boot logic: PLL1 must be configured for operation at + * 48MHz and P0.23 and PO.31 in PINSEL1 must be configured for Vbus and + * USB connect LED. + * + ****************************************************************************/ + +void arm_usbinitialize(void) +{ + /* At present, there is only a single OTG FS device support. Hence it is + * pre-allocated as g_otgfsdev. However, in most code, the private data + * structure will be referenced using the 'priv' pointer (rather than the + * global data) in order to simplify any future support for multiple + * devices. + */ + + struct stm32_usbdev_s *priv = &g_otgfsdev; + int ret; + + usbtrace(TRACE_DEVINIT, 0); + + /* Here we assume that: + * + * 1. GPIOA and OTG FS peripheral clocking has already been enabled as part + * of the boot sequence. + * 2. Board-specific logic has already enabled other board specific GPIOs + * for things like soft pull-up, VBUS sensing, power controls, and over- + * current detection. + */ + + /* Configure OTG FS alternate function pins + * + * PIN* SIGNAL DIRECTION + * ---- ----------- ---------- + * PA8 OTG_FS_SOF SOF clock output + * PA9 OTG_FS_VBUS VBUS input for device, Driven by external regulator by + * host (not an alternate function) + * PA10 OTG_FS_ID OTG ID pin (only needed in Dual mode) + * PA11 OTG_FS_DM D- I/O + * PA12 OTG_FS_DP D+ I/O + * + * *Pins may vary from device-to-device. + */ + + stm32_configgpio(GPIO_OTGFS_DM); + stm32_configgpio(GPIO_OTGFS_DP); + + /* Only needed for OTG */ +#ifndef CONFIG_OTG_ID_GPIO_DISABLE + stm32_configgpio(GPIO_OTGFS_ID); +#endif + + /* SOF output pin configuration is configurable. */ + +#ifdef CONFIG_STM32_OTGFS_SOFOUTPUT + stm32_configgpio(GPIO_OTGFS_SOF); +#endif + + /* Uninitialize the hardware so that we know that we are starting from a + * known state. + */ + + arm_usbuninitialize(); + + /* Initialize the driver data structure */ + + stm32_swinitialize(priv); + + /* Attach the OTG FS interrupt handler */ + + ret = irq_attach(STM32_IRQ_OTGFS, stm32_usbinterrupt, NULL); + if (ret < 0) + { + uerr("ERROR: irq_attach failed: %d\n", ret); + goto errout; + } + + /* Initialize the USB OTG core */ + + stm32_hwinitialize(priv); + + /* Disconnect device */ + + stm32_pullup(&priv->usbdev, false); + + /* Reset/Re-initialize the USB hardware */ + + stm32_usbreset(priv); + + /* Enable USB controller interrupts at the NVIC */ + + up_enable_irq(STM32_IRQ_OTGFS); + return; + +errout: + arm_usbuninitialize(); +} + +/**************************************************************************** + * Name: arm_usbuninitialize + ****************************************************************************/ + +void arm_usbuninitialize(void) +{ + /* At present, there is only a single OTG FS device support. Hence it is + * pre-allocated as g_otgfsdev. However, in most code, the private data + * structure will be referenced using the 'priv' pointer (rather than the + * global data) in order to simplify any future support for multiple + * devices. + */ + + struct stm32_usbdev_s *priv = &g_otgfsdev; + irqstate_t flags; + int i; + + usbtrace(TRACE_DEVUNINIT, 0); + + if (priv->driver) + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_DRIVERREGISTERED), 0); + usbdev_unregister(priv->driver); + } + + /* Disconnect device */ + + flags = enter_critical_section(); + stm32_pullup(&priv->usbdev, false); + priv->usbdev.speed = USB_SPEED_UNKNOWN; + + /* Disable and detach IRQs */ + + up_disable_irq(STM32_IRQ_OTGFS); + irq_detach(STM32_IRQ_OTGFS); + + /* Disable all endpoint interrupts */ + + for (i = 0; i < STM32_NENDPOINTS; i++) + { + stm32_putreg(0xff, STM32_OTGFS_DIEPINT(i)); + stm32_putreg(0xff, STM32_OTGFS_DOEPINT(i)); + } + + stm32_putreg(0, STM32_OTGFS_DIEPMSK); + stm32_putreg(0, STM32_OTGFS_DOEPMSK); + stm32_putreg(0, STM32_OTGFS_DIEPEMPMSK); + stm32_putreg(0, STM32_OTGFS_DAINTMSK); + stm32_putreg(0xffffffff, STM32_OTGFS_DAINT); + + /* Flush the FIFOs */ + + stm32_txfifo_flush(OTGFS_GRSTCTL_TXFNUM_DALL); + stm32_rxfifo_flush(); + + /* TODO: Turn off USB power and clocking */ + + priv->devstate = DEVSTATE_DEFAULT; + leave_critical_section(flags); +} + +/**************************************************************************** + * Name: usbdev_register + * + * Description: + * Register a USB device class driver. The class driver's bind() method + * will be called to bind it to a USB device driver. + * + ****************************************************************************/ + +int usbdev_register(struct usbdevclass_driver_s *driver) +{ + /* At present, there is only a single OTG FS device support. Hence it is + * pre-allocated as g_otgfsdev. However, in most code, the private data + * structure will be referenced using the 'priv' pointer (rather than the + * global data) in order to simplify any future support for multiple + * devices. + */ + + struct stm32_usbdev_s *priv = &g_otgfsdev; + int ret; + + usbtrace(TRACE_DEVREGISTER, 0); + +#ifdef CONFIG_DEBUG_FEATURES + if (!driver || !driver->ops->bind || !driver->ops->unbind || + !driver->ops->disconnect || !driver->ops->setup) + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); + return -EINVAL; + } + + if (priv->driver) + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_DRIVER), 0); + return -EBUSY; + } +#endif + + /* First hook up the driver */ + + priv->driver = driver; + + /* Then bind the class driver */ + + ret = CLASS_BIND(driver, &priv->usbdev); + if (ret) + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BINDFAILED), (uint16_t)-ret); + priv->driver = NULL; + } + else + { + /* Enable USB controller interrupts */ + + up_enable_irq(STM32_IRQ_OTGFS); + + /* FIXME: nothing seems to call DEV_CONNECT(), but we need to set + * the RS bit to enable the controller. It kind of makes sense + * to do this after the class has bound to us... + * GEN: This bug is really in the class driver. It should make the + * soft connect when it is ready to be enumerated. I have added + * that logic to the class drivers but left this logic here. + */ + + stm32_pullup(&priv->usbdev, true); + priv->usbdev.speed = USB_SPEED_FULL; + } + + return ret; +} + +/**************************************************************************** + * Name: usbdev_unregister + * + * Description: + * Un-register usbdev class driver.If the USB device is connected to a USB + * host, it will first disconnect(). The driver is also requested to + * unbind() and clean up any device state, before this procedure finally + * returns. + * + ****************************************************************************/ + +int usbdev_unregister(struct usbdevclass_driver_s *driver) +{ + /* At present, there is only a single OTG FS device support. Hence it is + * pre-allocated as g_otgfsdev. However, in most code, the private data + * structure will be referenced using the 'priv' pointer (rather than the + * global data) in order to simplify any future support for multiple + * devices. + */ + + struct stm32_usbdev_s *priv = &g_otgfsdev; + irqstate_t flags; + + usbtrace(TRACE_DEVUNREGISTER, 0); + +#ifdef CONFIG_DEBUG_FEATURES + if (driver != priv->driver) + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); + return -EINVAL; + } +#endif + + /* Reset the hardware and cancel all requests. All requests must be + * canceled while the class driver is still bound. + */ + + flags = enter_critical_section(); + stm32_usbreset(priv); + leave_critical_section(flags); + + /* Unbind the class driver */ + + CLASS_UNBIND(driver, &priv->usbdev); + + /* Disable USB controller interrupts */ + + flags = enter_critical_section(); + up_disable_irq(STM32_IRQ_OTGFS); + + /* Disconnect device */ + + stm32_pullup(&priv->usbdev, false); + + /* Unhook the driver */ + + priv->driver = NULL; + leave_critical_section(flags); + + return OK; +} + +#endif /* CONFIG_USBDEV && CONFIG_STM32_OTGFSDEV */ diff --git a/arch/arm/src/common/stm32/stm32_otgfshost_m3m4_v1.c b/arch/arm/src/common/stm32/stm32_otgfshost_m3m4_v1.c new file mode 100644 index 0000000000000..1197648cd1b26 --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_otgfshost_m3m4_v1.c @@ -0,0 +1,5471 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_otgfshost_m3m4_v1.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "chip.h" /* Includes default GPIO settings */ +#include /* May redefine GPIO settings */ + +#include "arm_internal.h" +#include "stm32_gpio.h" +#include "stm32_usbhost_m3m4_v1.h" + +#if defined(CONFIG_STM32_USBHOST) && defined(CONFIG_STM32_OTGFS) + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* STM32 USB OTG FS Host Driver Support + * + * Pre-requisites + * + * CONFIG_STM32_USBHOST - Enable STM32 USB host support + * CONFIG_USBHOST - Enable general USB host support + * CONFIG_STM32_OTGFS - Enable the STM32 USB OTG FS block + * CONFIG_STM32_SYSCFG - Needed + * + * Options: + * + * CONFIG_STM32_OTGFS_RXFIFO_SIZE - Size of the RX FIFO in 32-bit words. + * Default 128 (512 bytes) + * CONFIG_STM32_OTGFS_NPTXFIFO_SIZE - Size of the non-periodic Tx FIFO + * in 32-bit words. Default 96 (384 bytes) + * CONFIG_STM32_OTGFS_PTXFIFO_SIZE - Size of the periodic Tx FIFO in 32-bit + * words. Default 96 (384 bytes) + * CONFIG_STM32_OTGFS_DESCSIZE - Maximum size of a descriptor. Default: 128 + * CONFIG_STM32_OTGFS_SOFINTR - Enable SOF interrupts. Why would you ever + * want to do that? + * CONFIG_STM32_USBHOST_REGDEBUG - Enable very low-level register access + * debug. Depends on CONFIG_DEBUG_FEATURES. + * CONFIG_STM32_USBHOST_PKTDUMP - Dump all incoming and outgoing USB + * packets. Depends on CONFIG_DEBUG_FEATURES. + */ + +/* Pre-requisites (partial) */ + +#ifndef CONFIG_STM32_SYSCFG +# error "CONFIG_STM32_SYSCFG is required" +#endif + +/* Default RxFIFO size */ + +#ifndef CONFIG_STM32_OTGFS_RXFIFO_SIZE +# define CONFIG_STM32_OTGFS_RXFIFO_SIZE 128 +#endif + +/* Default host non-periodic Tx FIFO size */ + +#ifndef CONFIG_STM32_OTGFS_NPTXFIFO_SIZE +# define CONFIG_STM32_OTGFS_NPTXFIFO_SIZE 96 +#endif + +/* Default host periodic Tx fifo size register */ + +#ifndef CONFIG_STM32_OTGFS_PTXFIFO_SIZE +# define CONFIG_STM32_OTGFS_PTXFIFO_SIZE 96 +#endif + +/* Maximum size of a descriptor */ + +#ifndef CONFIG_STM32_OTGFS_DESCSIZE +# define CONFIG_STM32_OTGFS_DESCSIZE 128 +#endif + +/* Register/packet debug depends on CONFIG_DEBUG_FEATURES */ + +#ifndef CONFIG_DEBUG_USB_INFO +# undef CONFIG_STM32_USBHOST_REGDEBUG +# undef CONFIG_STM32_USBHOST_PKTDUMP +#endif + +/* HCD Setup ****************************************************************/ + +/* Hardware capabilities */ + +#define STM32_NHOST_CHANNELS 8 /* Number of host channels */ +#define STM32_MAX_PACKET_SIZE 64 /* Full speed max packet size */ +#define STM32_EP0_DEF_PACKET_SIZE 8 /* EP0 default packet size */ +#define STM32_EP0_MAX_PACKET_SIZE 64 /* EP0 FS max packet size */ +#define STM32_MAX_TX_FIFOS 15 /* Max number of TX FIFOs */ +#define STM32_MAX_PKTCOUNT 256 /* Max packet count */ +#define STM32_RETRY_COUNT 3 /* Number of ctrl transfer retries */ + +/* Delays *******************************************************************/ + +#define STM32_READY_DELAY 200000 /* In loop counts */ +#define STM32_FLUSH_DELAY 200000 /* In loop counts */ +#define STM32_SETUP_DELAY SEC2TICK(5) /* 5 seconds in system ticks */ +#define STM32_DATANAK_DELAY SEC2TICK(5) /* 5 seconds in system ticks */ + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/* The following enumeration represents the various states of the USB host + * state machine (for debug purposes only) + */ + +enum stm32_smstate_e +{ + SMSTATE_DETACHED = 0, /* Not attached to a device */ + SMSTATE_ATTACHED, /* Attached to a device */ + SMSTATE_ENUM, /* Attached, enumerating */ + SMSTATE_CLASS_BOUND, /* Enumeration complete, class bound */ +}; + +/* This enumeration provides the reason for the channel halt. */ + +enum stm32_chreason_e +{ + CHREASON_IDLE = 0, /* Inactive (initial state) */ + CHREASON_FREED, /* Channel is no longer in use */ + CHREASON_XFRC, /* Transfer complete */ + CHREASON_NAK, /* NAK received */ + CHREASON_NYET, /* NotYet received */ + CHREASON_STALL, /* Endpoint stalled */ + CHREASON_TXERR, /* Transfer error received */ + CHREASON_DTERR, /* Data toggle error received */ + CHREASON_FRMOR, /* Frame overrun */ + CHREASON_CANCELLED /* Transfer cancelled */ +}; + +/* This structure retains the state of one host channel. NOTE: Since there + * is only one channel operation active at a time, some of the fields in + * in the structure could be moved in struct stm32_ubhost_s to achieve + * some memory savings. + */ + +struct stm32_chan_s +{ + sem_t waitsem; /* Channel wait semaphore */ + volatile uint8_t result; /* The result of the transfer */ + volatile uint8_t chreason; /* Channel halt reason. See enum stm32_chreason_e */ + uint8_t chidx; /* Channel index */ + uint8_t epno; /* Device endpoint number (0-127) */ + uint8_t eptype; /* See OTGFS_EPTYPE_* definitions */ + uint8_t funcaddr; /* Device function address */ + uint8_t speed; /* Device speed */ + uint8_t interval; /* Interrupt/isochronous EP polling interval */ + uint8_t pid; /* Data PID */ + uint8_t npackets; /* Number of packets (for data toggle) */ + bool inuse; /* True: This channel is "in use" */ + volatile bool indata1; /* IN data toggle. True: DATA01 (Bulk and INTR only) */ + volatile bool outdata1; /* OUT data toggle. True: DATA01 */ + bool in; /* True: IN endpoint */ + volatile bool waiter; /* True: Thread is waiting for a channel event */ + uint16_t maxpacket; /* Max packet size */ + uint16_t buflen; /* Buffer length (at start of transfer) */ + volatile uint16_t xfrd; /* Bytes transferred (at end of transfer) */ + volatile uint16_t inflight; /* Number of Tx bytes "in-flight" */ + uint8_t *buffer; /* Transfer buffer pointer */ +#ifdef CONFIG_USBHOST_ASYNCH + usbhost_asynch_t callback; /* Transfer complete callback */ + void *arg; /* Argument that accompanies the callback */ +#endif +}; + +/* A channel represents on uni-directional endpoint. So, in the case of the + * bi-directional, control endpoint, there must be two channels to represent + * the endpoint. + */ + +struct stm32_ctrlinfo_s +{ + uint8_t inndx; /* EP0 IN control channel index */ + uint8_t outndx; /* EP0 OUT control channel index */ +}; + +/* This structure retains the state of the USB host controller */ + +struct stm32_usbhost_s +{ + /* Common device fields. This must be the first thing defined in the + * structure so that it is possible to simply cast from struct usbhost_s + * to structstm32_usbhost_s. + */ + + struct usbhost_driver_s drvr; + + /* This is the hub port description understood by class drivers */ + + struct usbhost_roothubport_s rhport; + + /* Overall driver status */ + + volatile uint8_t smstate; /* The state of the USB host state machine */ + uint8_t chidx; /* ID of channel waiting for space in Tx FIFO */ + volatile bool connected; /* Connected to device */ + volatile bool change; /* Connection change */ + volatile bool pscwait; /* True: Thread is waiting for a port event */ + mutex_t lock; /* Support mutually exclusive access */ + sem_t pscsem; /* Semaphore to wait for a port event */ + struct stm32_ctrlinfo_s ep0; /* Root hub port EP0 description */ + +#ifdef CONFIG_USBHOST_HUB + /* Used to pass external hub port events */ + + volatile struct usbhost_hubport_s *hport; +#endif + + struct usbhost_devaddr_s devgen; /* Address generation data */ + + /* The state of each host channel */ + + struct stm32_chan_s chan[STM32_MAX_TX_FIFOS]; +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/* Register operations ******************************************************/ + +#ifdef CONFIG_STM32_USBHOST_REGDEBUG +static void stm32_printreg(uint32_t addr, uint32_t val, bool iswrite); +static void stm32_checkreg(uint32_t addr, uint32_t val, bool iswrite); +static uint32_t stm32_getreg(uint32_t addr); +static void stm32_putreg(uint32_t addr, uint32_t value); +#else +# define stm32_getreg(addr) getreg32(addr) +# define stm32_putreg(addr,val) putreg32(val,addr) +#endif + +static inline void stm32_modifyreg(uint32_t addr, uint32_t clrbits, + uint32_t setbits); + +#ifdef CONFIG_STM32_USBHOST_PKTDUMP +# define stm32_pktdump(m,b,n) lib_dumpbuffer(m,b,n) +#else +# define stm32_pktdump(m,b,n) +#endif + +/* Byte stream access helper functions **************************************/ + +static inline uint16_t stm32_getle16(const uint8_t *val); + +/* Channel management *******************************************************/ + +static int stm32_chan_alloc(struct stm32_usbhost_s *priv); +static inline void stm32_chan_free(struct stm32_usbhost_s *priv, + int chidx); +static inline void stm32_chan_freeall(struct stm32_usbhost_s *priv); +static void stm32_chan_configure(struct stm32_usbhost_s *priv, + int chidx); +static void stm32_chan_halt(struct stm32_usbhost_s *priv, int chidx, + enum stm32_chreason_e chreason); +static int stm32_chan_waitsetup(struct stm32_usbhost_s *priv, + struct stm32_chan_s *chan); +#ifdef CONFIG_USBHOST_ASYNCH +static int stm32_chan_asynchsetup(struct stm32_usbhost_s *priv, + struct stm32_chan_s *chan, + usbhost_asynch_t callback, void *arg); +#endif +static int stm32_chan_wait(struct stm32_usbhost_s *priv, + struct stm32_chan_s *chan); +static void stm32_chan_wakeup(struct stm32_usbhost_s *priv, + struct stm32_chan_s *chan); +static int stm32_ctrlchan_alloc(struct stm32_usbhost_s *priv, + uint8_t epno, uint8_t funcaddr, + uint8_t speed, + struct stm32_ctrlinfo_s *ctrlep); +static int stm32_ctrlep_alloc(struct stm32_usbhost_s *priv, + const struct usbhost_epdesc_s *epdesc, + usbhost_ep_t *ep); +static int stm32_xfrep_alloc(struct stm32_usbhost_s *priv, + const struct usbhost_epdesc_s *epdesc, + usbhost_ep_t *ep); + +/* Control/data transfer logic **********************************************/ + +static void stm32_transfer_start(struct stm32_usbhost_s *priv, + int chidx); +#if 0 /* Not used */ +static inline uint16_t stm32_getframe(void); +#endif +static int stm32_ctrl_sendsetup(struct stm32_usbhost_s *priv, + struct stm32_ctrlinfo_s *ep0, + const struct usb_ctrlreq_s *req); +static int stm32_ctrl_senddata(struct stm32_usbhost_s *priv, + struct stm32_ctrlinfo_s *ep0, + uint8_t *buffer, unsigned int buflen); +static int stm32_ctrl_recvdata(struct stm32_usbhost_s *priv, + struct stm32_ctrlinfo_s *ep0, + uint8_t *buffer, unsigned int buflen); +static int stm32_in_setup(struct stm32_usbhost_s *priv, int chidx); +static ssize_t stm32_in_transfer(struct stm32_usbhost_s *priv, int chidx, + uint8_t *buffer, size_t buflen); +#ifdef CONFIG_USBHOST_ASYNCH +static void stm32_in_next(struct stm32_usbhost_s *priv, + struct stm32_chan_s *chan); +static int stm32_in_asynch(struct stm32_usbhost_s *priv, int chidx, + uint8_t *buffer, size_t buflen, + usbhost_asynch_t callback, void *arg); +#endif +static int stm32_out_setup(struct stm32_usbhost_s *priv, int chidx); +static ssize_t stm32_out_transfer(struct stm32_usbhost_s *priv, + int chidx, uint8_t *buffer, + size_t buflen); +#ifdef CONFIG_USBHOST_ASYNCH +static void stm32_out_next(struct stm32_usbhost_s *priv, + struct stm32_chan_s *chan); +static int stm32_out_asynch(struct stm32_usbhost_s *priv, int chidx, + uint8_t *buffer, size_t buflen, + usbhost_asynch_t callback, void *arg); +#endif + +/* Interrupt handling *******************************************************/ + +/* Lower level interrupt handlers */ + +static void stm32_gint_wrpacket(struct stm32_usbhost_s *priv, + uint8_t *buffer, int chidx, int buflen); +static inline void stm32_gint_hcinisr(struct stm32_usbhost_s *priv, + int chidx); +static inline void stm32_gint_hcoutisr(struct stm32_usbhost_s *priv, + int chidx); +static void stm32_gint_connected(struct stm32_usbhost_s *priv); +static void stm32_gint_disconnected(struct stm32_usbhost_s *priv); + +/* Second level interrupt handlers */ + +#ifdef CONFIG_STM32_OTGFS_SOFINTR +static inline void stm32_gint_sofisr(struct stm32_usbhost_s *priv); +#endif +static inline void stm32_gint_rxflvlisr(struct stm32_usbhost_s *priv); +static inline void stm32_gint_nptxfeisr(struct stm32_usbhost_s *priv); +static inline void stm32_gint_ptxfeisr(struct stm32_usbhost_s *priv); +static inline void stm32_gint_hcisr(struct stm32_usbhost_s *priv); +static inline void stm32_gint_hprtisr(struct stm32_usbhost_s *priv); +static inline void stm32_gint_discisr(struct stm32_usbhost_s *priv); +static inline void stm32_gint_ipxfrisr(struct stm32_usbhost_s *priv); + +/* First level, global interrupt handler */ + +static int stm32_gint_isr(int irq, void *context, void *arg); + +/* Interrupt controls */ + +static void stm32_gint_enable(void); +static void stm32_gint_disable(void); +static inline void stm32_hostinit_enable(void); +static void stm32_txfe_enable(struct stm32_usbhost_s *priv, int chidx); + +/* USB host controller operations *******************************************/ + +static int stm32_wait(struct usbhost_connection_s *conn, + struct usbhost_hubport_s **hport); +static int stm32_rh_enumerate(struct stm32_usbhost_s *priv, + struct usbhost_connection_s *conn, + struct usbhost_hubport_s *hport); +static int stm32_enumerate(struct usbhost_connection_s *conn, + struct usbhost_hubport_s *hport); + +static int stm32_ep0configure(struct usbhost_driver_s *drvr, + usbhost_ep_t ep0, uint8_t funcaddr, + uint8_t speed, uint16_t maxpacketsize); +static int stm32_epalloc(struct usbhost_driver_s *drvr, + const struct usbhost_epdesc_s *epdesc, + usbhost_ep_t *ep); +static int stm32_epfree(struct usbhost_driver_s *drvr, usbhost_ep_t ep); +static int stm32_alloc(struct usbhost_driver_s *drvr, + uint8_t **buffer, size_t *maxlen); +static int stm32_free(struct usbhost_driver_s *drvr, + uint8_t *buffer); +static int stm32_ioalloc(struct usbhost_driver_s *drvr, + uint8_t **buffer, size_t buflen); +static int stm32_iofree(struct usbhost_driver_s *drvr, + uint8_t *buffer); +static int stm32_ctrlin(struct usbhost_driver_s *drvr, usbhost_ep_t ep0, + const struct usb_ctrlreq_s *req, + uint8_t *buffer); +static int stm32_ctrlout(struct usbhost_driver_s *drvr, usbhost_ep_t ep0, + const struct usb_ctrlreq_s *req, + const uint8_t *buffer); +static ssize_t stm32_transfer(struct usbhost_driver_s *drvr, + usbhost_ep_t ep, uint8_t *buffer, + size_t buflen); +#ifdef CONFIG_USBHOST_ASYNCH +static int stm32_asynch(struct usbhost_driver_s *drvr, usbhost_ep_t ep, + uint8_t *buffer, size_t buflen, + usbhost_asynch_t callback, void *arg); +#endif +static int stm32_cancel(struct usbhost_driver_s *drvr, usbhost_ep_t ep); +#ifdef CONFIG_USBHOST_HUB +static int stm32_connect(struct usbhost_driver_s *drvr, + struct usbhost_hubport_s *hport, + bool connected); +#endif +static void stm32_disconnect(struct usbhost_driver_s *drvr, + struct usbhost_hubport_s *hport); + +/* Initialization ***********************************************************/ + +static void stm32_portreset(struct stm32_usbhost_s *priv); +static void stm32_flush_txfifos(uint32_t txfnum); +static void stm32_flush_rxfifo(void); +static void stm32_vbusdrive(struct stm32_usbhost_s *priv, bool state); +static void stm32_host_initialize(struct stm32_usbhost_s *priv); + +static inline void stm32_sw_initialize(struct stm32_usbhost_s *priv); +static inline int stm32_hw_initialize(struct stm32_usbhost_s *priv); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* In this driver implementation, support is provided for only a single a + * single USB device. All status information can be simply retained in a + * single global instance. + */ + +static struct stm32_usbhost_s g_usbhost = +{ + .lock = NXMUTEX_INITIALIZER, + .pscsem = SEM_INITIALIZER(0), +}; + +/* This is the connection/enumeration interface */ + +static struct usbhost_connection_s g_usbconn = +{ + .wait = stm32_wait, + .enumerate = stm32_enumerate, +}; + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_printreg + * + * Description: + * Print the contents of an STM32xx register operation + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_USBHOST_REGDEBUG +static void stm32_printreg(uint32_t addr, uint32_t val, bool iswrite) +{ + uinfo("%08" PRIx32 "%s%08" PRIx32 "\n", addr, iswrite ? "<-" : "->", val); +} +#endif + +/**************************************************************************** + * Name: stm32_checkreg + * + * Description: + * Get the contents of an STM32 register + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_USBHOST_REGDEBUG +static void stm32_checkreg(uint32_t addr, uint32_t val, bool iswrite) +{ + static uint32_t prevaddr = 0; + static uint32_t preval = 0; + static uint32_t count = 0; + static bool prevwrite = false; + + /* Is this the same value that we read from/wrote to the same register + * last time? Are we polling the register? If so, suppress the output. + */ + + if (addr == prevaddr && val == preval && prevwrite == iswrite) + { + /* Yes.. Just increment the count */ + + count++; + } + else + { + /* No this is a new address or value or operation. Were there any + * duplicate accesses before this one? + */ + + if (count > 0) + { + /* Yes.. Just one? */ + + if (count == 1) + { + /* Yes.. Just one */ + + stm32_printreg(prevaddr, preval, prevwrite); + } + else + { + /* No.. More than one. */ + + uinfo("[repeats %d more times]\n", count); + } + } + + /* Save the new address, value, count, and operation for next time */ + + prevaddr = addr; + preval = val; + count = 0; + prevwrite = iswrite; + + /* Show the new regisgter access */ + + stm32_printreg(addr, val, iswrite); + } +} +#endif + +/**************************************************************************** + * Name: stm32_getreg + * + * Description: + * Get the contents of an STM32 register + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_USBHOST_REGDEBUG +static uint32_t stm32_getreg(uint32_t addr) +{ + /* Read the value from the register */ + + uint32_t val = getreg32(addr); + + /* Check if we need to print this value */ + + stm32_checkreg(addr, val, false); + return val; +} +#endif + +/**************************************************************************** + * Name: stm32_putreg + * + * Description: + * Set the contents of an STM32 register to a value + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_USBHOST_REGDEBUG +static void stm32_putreg(uint32_t addr, uint32_t val) +{ + /* Check if we need to print this value */ + + stm32_checkreg(addr, val, true); + + /* Write the value */ + + putreg32(val, addr); +} +#endif + +/**************************************************************************** + * Name: stm32_modifyreg + * + * Description: + * Modify selected bits of an STM32 register. + * + ****************************************************************************/ + +static inline void stm32_modifyreg(uint32_t addr, uint32_t clrbits, + uint32_t setbits) +{ + stm32_putreg(addr, (((stm32_getreg(addr)) & ~clrbits) | setbits)); +} + +/**************************************************************************** + * Name: stm32_getle16 + * + * Description: + * Get a (possibly unaligned) 16-bit little endian value. + * + ****************************************************************************/ + +static inline uint16_t stm32_getle16(const uint8_t *val) +{ + return (uint16_t)val[1] << 8 | (uint16_t)val[0]; +} + +/**************************************************************************** + * Name: stm32_chan_alloc + * + * Description: + * Allocate a channel. + * + ****************************************************************************/ + +static int stm32_chan_alloc(struct stm32_usbhost_s *priv) +{ + int chidx; + + /* Search the table of channels */ + + for (chidx = 0; chidx < STM32_NHOST_CHANNELS; chidx++) + { + /* Is this channel available? */ + + if (!priv->chan[chidx].inuse) + { + /* Yes... make it "in use" and return the index */ + + priv->chan[chidx].inuse = true; + return chidx; + } + } + + /* All of the channels are "in-use" */ + + return -EBUSY; +} + +/**************************************************************************** + * Name: stm32_chan_free + * + * Description: + * Free a previoiusly allocated channel. + * + ****************************************************************************/ + +static void stm32_chan_free(struct stm32_usbhost_s *priv, int chidx) +{ + DEBUGASSERT((unsigned)chidx < STM32_NHOST_CHANNELS); + + /* Halt the channel */ + + stm32_chan_halt(priv, chidx, CHREASON_FREED); + + /* Mark the channel available */ + + priv->chan[chidx].inuse = false; +} + +/**************************************************************************** + * Name: stm32_chan_freeall + * + * Description: + * Free all channels. + * + ****************************************************************************/ + +static inline void stm32_chan_freeall(struct stm32_usbhost_s *priv) +{ + uint8_t chidx; + + /* Free all host channels */ + + for (chidx = 2; chidx < STM32_NHOST_CHANNELS; chidx++) + { + stm32_chan_free(priv, chidx); + } +} + +/**************************************************************************** + * Name: stm32_chan_configure + * + * Description: + * Configure or re-configure a host channel. Host channels are configured + * when endpoint is allocated and EP0 (only) is re-configured with the + * max packet size or device address changes. + * + ****************************************************************************/ + +static void stm32_chan_configure(struct stm32_usbhost_s *priv, int chidx) +{ + struct stm32_chan_s *chan = &priv->chan[chidx]; + uint32_t regval; + + /* Clear any old pending interrupts for this host channel. */ + + stm32_putreg(STM32_OTGFS_HCINT(chidx), 0xffffffff); + + /* Enable channel interrupts required for transfers on this channel. */ + + regval = 0; + + switch (chan->eptype) + { + case OTGFS_EPTYPE_CTRL: + case OTGFS_EPTYPE_BULK: + { +#ifdef HAVE_USBHOST_TRACE_VERBOSE + uint16_t intrace; + uint16_t outtrace; + + /* Determine the definitive trace ID to use below */ + + if (chan->eptype == OTGFS_EPTYPE_CTRL) + { + intrace = OTGFS_VTRACE2_CHANCONF_CTRL_IN; + outtrace = OTGFS_VTRACE2_CHANCONF_CTRL_OUT; + } + else + { + intrace = OTGFS_VTRACE2_CHANCONF_BULK_IN; + outtrace = OTGFS_VTRACE2_CHANCONF_BULK_OUT; + } +#endif + + /* Interrupts required for CTRL and BULK endpoints */ + + regval |= (OTGFS_HCINT_XFRC | OTGFS_HCINT_STALL | OTGFS_HCINT_NAK | + OTGFS_HCINT_TXERR | OTGFS_HCINT_DTERR); + + /* Additional setting for IN/OUT endpoints */ + + if (chan->in) + { + usbhost_vtrace2(intrace, chidx, chan->epno); + regval |= OTGFS_HCINT_BBERR; + } + else + { + usbhost_vtrace2(outtrace, chidx, chan->epno); + regval |= OTGFS_HCINT_NYET; + } + } + break; + + case OTGFS_EPTYPE_INTR: + { + /* Interrupts required for INTR endpoints */ + + regval |= (OTGFS_HCINT_XFRC | OTGFS_HCINT_STALL | + OTGFS_HCINT_NAK | OTGFS_HCINT_TXERR | + OTGFS_HCINT_FRMOR | OTGFS_HCINT_DTERR); + + /* Additional setting for IN endpoints */ + + if (chan->in) + { + usbhost_vtrace2(OTGFS_VTRACE2_CHANCONF_INTR_IN, chidx, + chan->epno); + regval |= OTGFS_HCINT_BBERR; + } +#ifdef HAVE_USBHOST_TRACE_VERBOSE + else + { + usbhost_vtrace2(OTGFS_VTRACE2_CHANCONF_INTR_OUT, chidx, + chan->epno); + } +#endif + } + break; + + case OTGFS_EPTYPE_ISOC: + { + /* Interrupts required for ISOC endpoints */ + + regval |= OTGFS_HCINT_XFRC | OTGFS_HCINT_ACK | OTGFS_HCINT_FRMOR; + + /* Additional setting for IN endpoints */ + + if (chan->in) + { + usbhost_vtrace2(OTGFS_VTRACE2_CHANCONF_ISOC_IN, chidx, + chan->epno); + regval |= (OTGFS_HCINT_TXERR | OTGFS_HCINT_BBERR); + } +#ifdef HAVE_USBHOST_TRACE_VERBOSE + else + { + usbhost_vtrace2(OTGFS_VTRACE2_CHANCONF_ISOC_OUT, chidx, + chan->epno); + } +#endif + } + break; + } + + stm32_putreg(STM32_OTGFS_HCINTMSK(chidx), regval); + + /* Enable the top level host channel interrupt. */ + + stm32_modifyreg(STM32_OTGFS_HAINTMSK, 0, OTGFS_HAINT(chidx)); + + /* Make sure host channel interrupts are enabled. */ + + stm32_modifyreg(STM32_OTGFS_GINTMSK, 0, OTGFS_GINT_HC); + + /* Program the HCCHAR register */ + + regval = ((uint32_t)chan->maxpacket << OTGFS_HCCHAR_MPSIZ_SHIFT) | + ((uint32_t)chan->epno << OTGFS_HCCHAR_EPNUM_SHIFT) | + ((uint32_t)chan->eptype << OTGFS_HCCHAR_EPTYP_SHIFT) | + ((uint32_t)chan->funcaddr << OTGFS_HCCHAR_DAD_SHIFT); + + /* Special case settings for low speed devices */ + + if (chan->speed == USB_SPEED_LOW) + { + regval |= OTGFS_HCCHAR_LSDEV; + } + + /* Special case settings for IN endpoints */ + + if (chan->in) + { + regval |= OTGFS_HCCHAR_EPDIR_IN; + } + + /* Special case settings for INTR endpoints */ + + if (chan->eptype == OTGFS_EPTYPE_INTR) + { + regval |= OTGFS_HCCHAR_ODDFRM; + } + + /* Write the channel configuration */ + + stm32_putreg(STM32_OTGFS_HCCHAR(chidx), regval); +} + +/**************************************************************************** + * Name: stm32_chan_halt + * + * Description: + * Halt the channel associated with 'chidx' by setting the CHannel DISable + * (CHDIS) bit in in the HCCHAR register. + * + ****************************************************************************/ + +static void stm32_chan_halt(struct stm32_usbhost_s *priv, int chidx, + enum stm32_chreason_e chreason) +{ + uint32_t hcchar; + uint32_t intmsk; + uint32_t eptype; + unsigned int avail; + + /* Save the reason for the halt. We need this in the channel halt + * interrupt handling logic to know what to do next. + */ + + usbhost_vtrace2(OTGFS_VTRACE2_CHANHALT, chidx, chreason); + + priv->chan[chidx].chreason = (uint8_t)chreason; + + /* "The application can disable any channel by programming the + * OTG_FS_HCCHARx register with the CHDIS and CHENA bits set to 1. This + * enables the OTG_FS host to flush the posted requests (if any) and + * generates a channel halted interrupt. The application must wait for + * the CHH interrupt in OTG_FS_HCINTx before reallocating the channel for + * other transactions. The OTG_FS host does not interrupt the + * transaction that has already been started on the USB." + */ + + hcchar = stm32_getreg(STM32_OTGFS_HCCHAR(chidx)); + hcchar |= (OTGFS_HCCHAR_CHDIS | OTGFS_HCCHAR_CHENA); + + /* Get the endpoint type from the HCCHAR register */ + + eptype = hcchar & OTGFS_HCCHAR_EPTYP_MASK; + + /* Check for space in the Tx FIFO to issue the halt. + * + * "Before disabling a channel, the application must ensure that there is + * at least one free space available in the non-periodic request queue + * (when disabling a non-periodic channel) or the periodic request queue + * (when disabling a periodic channel). The application can simply flush + * the posted requests when the Request queue is full (before disabling + * the channel), by programming the OTG_FS_HCCHARx register with the + * CHDIS bit set to 1, and the CHENA bit cleared to 0." + */ + + if (eptype == OTGFS_HCCHAR_EPTYP_CTRL || + eptype == OTGFS_HCCHAR_EPTYP_BULK) + { + /* Get the number of words available in the non-periodic Tx FIFO. */ + + avail = stm32_getreg(STM32_OTGFS_HNPTXSTS) & + OTGFS_HNPTXSTS_NPTXFSAV_MASK; + } + else + { + /* Get the number of words available in the non-periodic Tx FIFO. */ + + avail = stm32_getreg(STM32_OTGFS_HPTXSTS) & + OTGFS_HPTXSTS_PTXFSAVL_MASK; + } + + /* Check if there is any space available in the Tx FIFO. */ + + if (avail == 0) + { + /* The Tx FIFO is full... disable the channel to flush the requests */ + + hcchar &= ~OTGFS_HCCHAR_CHENA; + } + + /* Unmask the CHannel Halted (CHH) interrupt */ + + intmsk = stm32_getreg(STM32_OTGFS_HCINTMSK(chidx)); + intmsk |= OTGFS_HCINT_CHH; + stm32_putreg(STM32_OTGFS_HCINTMSK(chidx), intmsk); + + /* Halt the channel by setting CHDIS (and maybe CHENA) in the HCCHAR */ + + stm32_putreg(STM32_OTGFS_HCCHAR(chidx), hcchar); +} + +/**************************************************************************** + * Name: stm32_chan_waitsetup + * + * Description: + * Set the request for the transfer complete event well BEFORE enabling + * the transfer (as soon as we are absolutely committed to the transfer). + * We do this to minimize race conditions. This logic would have to be + * expanded if we want to have more than one packet in flight at a time! + * + * Assumptions: + * Called from a normal thread context BEFORE the transfer has been + * started. + * + ****************************************************************************/ + +static int stm32_chan_waitsetup(struct stm32_usbhost_s *priv, + struct stm32_chan_s *chan) +{ + irqstate_t flags = enter_critical_section(); + int ret = -ENODEV; + + /* Is the device still connected? */ + + if (priv->connected) + { + /* Yes.. then set waiter to indicate that we expect to be informed + * when either (1) the device is disconnected, or (2) the transfer + * completed. + */ + + chan->waiter = true; +#ifdef CONFIG_USBHOST_ASYNCH + chan->callback = NULL; + chan->arg = NULL; +#endif + ret = OK; + } + + leave_critical_section(flags); + return ret; +} + +/**************************************************************************** + * Name: stm32_chan_asynchsetup + * + * Description: + * Set the request for the transfer complete event well BEFORE enabling + * the transfer (as soon as we are absolutely committed to the to avoid + * transfer). We do this to minimize race conditions. This logic would + * have to be expanded if we want to have more than one packet in flight + * at a time! + * + * Assumptions: + * Might be called from the level of an interrupt handler + * + ****************************************************************************/ + +#ifdef CONFIG_USBHOST_ASYNCH +static int stm32_chan_asynchsetup(struct stm32_usbhost_s *priv, + struct stm32_chan_s *chan, + usbhost_asynch_t callback, void *arg) +{ + irqstate_t flags = enter_critical_section(); + int ret = -ENODEV; + + /* Is the device still connected? */ + + if (priv->connected) + { + /* Yes.. then set waiter to indicate that we expect to be informed + * when either (1) the device is disconnected, or (2) the transfer + * completed. + */ + + chan->waiter = false; + chan->callback = callback; + chan->arg = arg; + ret = OK; + } + + leave_critical_section(flags); + return ret; +} +#endif + +/**************************************************************************** + * Name: stm32_chan_wait + * + * Description: + * Wait for a transfer on a channel to complete. + * + * Assumptions: + * Called from a normal thread context + * + ****************************************************************************/ + +static int stm32_chan_wait(struct stm32_usbhost_s *priv, + struct stm32_chan_s *chan) +{ + irqstate_t flags; + int ret; + + /* Disable interrupts so that the following operations will be atomic. On + * the OTG FS global interrupt needs to be disabled. However, here we + * disable all interrupts to exploit that fact that interrupts will be re- + * enabled while we wait. + */ + + flags = enter_critical_section(); + + /* Loop, testing for an end of transfer condition. The channel 'result' + * was set to EBUSY and 'waiter' was set to true before the transfer; + * 'waiter' will be set to false and 'result' will be set appropriately + * when the transfer is completed. + */ + + do + { + /* Wait for the transfer to complete. NOTE the transfer may already + * completed before we get here or the transfer may complete while we + * wait here. + */ + + ret = nxsem_wait_uninterruptible(&chan->waitsem); + } + while (chan->waiter && ret >= 0); + + /* The transfer is complete re-enable interrupts and return the result */ + + if (ret >= 0) + { + ret = -(int)chan->result; + } + + leave_critical_section(flags); + return ret; +} + +/**************************************************************************** + * Name: stm32_chan_wakeup + * + * Description: + * A channel transfer has completed... wakeup any threads waiting for the + * transfer to complete. + * + * Assumptions: + * This function is called from the transfer complete interrupt handler for + * the channel. Interrupts are disabled. + * + ****************************************************************************/ + +static void stm32_chan_wakeup(struct stm32_usbhost_s *priv, + struct stm32_chan_s *chan) +{ + /* Is the transfer complete? */ + + if (chan->result != EBUSY) + { + /* Is there a thread waiting for this transfer to complete? */ + + if (chan->waiter) + { +#ifdef CONFIG_USBHOST_ASYNCH + /* Yes.. there should not also be a callback scheduled */ + + DEBUGASSERT(chan->callback == NULL); +#endif + /* Wake'em up! */ + + usbhost_vtrace2(chan->in ? OTGFS_VTRACE2_CHANWAKEUP_IN : + OTGFS_VTRACE2_CHANWAKEUP_OUT, + chan->epno, chan->result); + + nxsem_post(&chan->waitsem); + chan->waiter = false; + } + +#ifdef CONFIG_USBHOST_ASYNCH + /* No.. is an asynchronous callback expected when the transfer + * completes? + */ + + else if (chan->callback) + { + /* Handle continuation of IN/OUT pipes */ + + if (chan->in) + { + stm32_in_next(priv, chan); + } + else + { + stm32_out_next(priv, chan); + } + } +#endif + } +} + +/**************************************************************************** + * Name: stm32_ctrlchan_alloc + * + * Description: + * Allocate and configured channels for a control pipe. + * + ****************************************************************************/ + +static int stm32_ctrlchan_alloc(struct stm32_usbhost_s *priv, + uint8_t epno, uint8_t funcaddr, + uint8_t speed, + struct stm32_ctrlinfo_s *ctrlep) +{ + struct stm32_chan_s *chan; + int inndx; + int outndx; + + outndx = stm32_chan_alloc(priv); + if (outndx < 0) + { + return -ENOMEM; + } + + ctrlep->outndx = outndx; + chan = &priv->chan[outndx]; + chan->epno = epno; + chan->in = false; + chan->eptype = OTGFS_EPTYPE_CTRL; + chan->funcaddr = funcaddr; + chan->speed = speed; + chan->interval = 0; + chan->maxpacket = STM32_EP0_DEF_PACKET_SIZE; + chan->indata1 = false; + chan->outdata1 = false; + + /* Configure control OUT channels */ + + stm32_chan_configure(priv, outndx); + + /* Allocate and initialize the control IN channel */ + + inndx = stm32_chan_alloc(priv); + if (inndx < 0) + { + stm32_chan_free(priv, outndx); + return -ENOMEM; + } + + ctrlep->inndx = inndx; + chan = &priv->chan[inndx]; + chan->epno = epno; + chan->in = true; + chan->eptype = OTGFS_EPTYPE_CTRL; + chan->funcaddr = funcaddr; + chan->speed = speed; + chan->interval = 0; + chan->maxpacket = STM32_EP0_DEF_PACKET_SIZE; + chan->indata1 = false; + chan->outdata1 = false; + + /* Configure control IN channels */ + + stm32_chan_configure(priv, inndx); + return OK; +} + +/**************************************************************************** + * Name: stm32_ctrlep_alloc + * + * Description: + * Allocate a container and channels for control pipe. + * + * Input Parameters: + * priv - The private USB host driver state. + * epdesc - Describes the endpoint to be allocated. + * ep - A memory location provided by the caller in which to receive the + * allocated endpoint descriptor. + * + * Returned Value: + * On success, zero (OK) is returned. On a failure, a negated errno value + * is returned indicating the nature of the failure + * + * Assumptions: + * This function will *not* be called from an interrupt handler. + * + ****************************************************************************/ + +static int stm32_ctrlep_alloc(struct stm32_usbhost_s *priv, + const struct usbhost_epdesc_s *epdesc, + usbhost_ep_t *ep) +{ + struct usbhost_hubport_s *hport; + struct stm32_ctrlinfo_s *ctrlep; + int ret; + + /* Sanity check. NOTE that this method should only be called if a device + * is connected (because we need a valid low speed indication). + */ + + DEBUGASSERT(epdesc->hport != NULL); + hport = epdesc->hport; + + /* Allocate a container for the control endpoint */ + + ctrlep = (struct stm32_ctrlinfo_s *) + kmm_malloc(sizeof(struct stm32_ctrlinfo_s)); + if (ctrlep == NULL) + { + uerr("ERROR: Failed to allocate control endpoint container\n"); + return -ENOMEM; + } + + /* Then allocate and configure the IN/OUT channels */ + + ret = stm32_ctrlchan_alloc(priv, epdesc->addr & USB_EPNO_MASK, + hport->funcaddr, hport->speed, ctrlep); + if (ret < 0) + { + uerr("ERROR: stm32_ctrlchan_alloc failed: %d\n", ret); + kmm_free(ctrlep); + return ret; + } + + /* Return a pointer to the control pipe container as the pipe "handle" */ + + *ep = (usbhost_ep_t)ctrlep; + return OK; +} + +/**************************************************************************** + * Name: stm32_xfrep_alloc + * + * Description: + * Allocate and configure one unidirectional endpoint. + * + * Input Parameters: + * priv - The private USB host driver state. + * epdesc - Describes the endpoint to be allocated. + * ep - A memory location provided by the caller in which to receive the + * allocated endpoint descriptor. + * + * Returned Value: + * On success, zero (OK) is returned. On a failure, a negated errno value + * is returned indicating the nature of the failure + * + * Assumptions: + * This function will *not* be called from an interrupt handler. + * + ****************************************************************************/ + +static int stm32_xfrep_alloc(struct stm32_usbhost_s *priv, + const struct usbhost_epdesc_s *epdesc, + usbhost_ep_t *ep) +{ + struct usbhost_hubport_s *hport; + struct stm32_chan_s *chan; + int chidx; + + /* Sanity check. NOTE that this method should only be called if a device + * is connected (because we need a valid low speed indication). + */ + + DEBUGASSERT(epdesc->hport != NULL); + hport = epdesc->hport; + + /* Allocate a host channel for the endpoint */ + + chidx = stm32_chan_alloc(priv); + if (chidx < 0) + { + uerr("ERROR: Failed to allocate a host channel\n"); + return -ENOMEM; + } + + /* Decode the endpoint descriptor to initialize the channel data + * structures. Note: Here we depend on the fact that the endpoint + * point type is encoded in the same way in the endpoint descriptor as it + * is in the OTG HS hardware. + */ + + chan = &priv->chan[chidx]; + chan->epno = epdesc->addr & USB_EPNO_MASK; + chan->in = epdesc->in; + chan->eptype = epdesc->xfrtype; + chan->funcaddr = hport->funcaddr; + chan->speed = hport->speed; + chan->interval = epdesc->interval; + chan->maxpacket = epdesc->mxpacketsize; + chan->indata1 = false; + chan->outdata1 = false; + + /* Then configure the endpoint */ + + stm32_chan_configure(priv, chidx); + + /* Return the index to the allocated channel as the endpoint "handle" */ + + *ep = (usbhost_ep_t)chidx; + return OK; +} + +/**************************************************************************** + * Name: stm32_transfer_start + * + * Description: + * Start at transfer on the select IN or OUT channel. + * + ****************************************************************************/ + +static void stm32_transfer_start(struct stm32_usbhost_s *priv, int chidx) +{ + struct stm32_chan_s *chan; + uint32_t regval; + unsigned int npackets; + unsigned int maxpacket; + unsigned int avail; + unsigned int wrsize; + unsigned int minsize; + + /* Set up the initial state of the transfer */ + + chan = &priv->chan[chidx]; + + usbhost_vtrace2(OTGFS_VTRACE2_STARTTRANSFER, chidx, chan->buflen); + + chan->result = EBUSY; + chan->inflight = 0; + chan->xfrd = 0; + priv->chidx = chidx; + + /* Compute the expected number of packets associated to the transfer. + * If the transfer length is zero (or less than the size of one maximum + * size packet), then one packet is expected. + */ + + /* If the transfer size is greater than one packet, then calculate the + * number of packets that will be received/sent, including any partial + * final packet. + */ + + maxpacket = chan->maxpacket; + + if (chan->buflen > maxpacket) + { + npackets = (chan->buflen + maxpacket - 1) / maxpacket; + + /* Clip if the buffer length if it exceeds the maximum number of + * packets that can be transferred (this should not happen). + */ + + if (npackets > STM32_MAX_PKTCOUNT) + { + npackets = STM32_MAX_PKTCOUNT; + chan->buflen = STM32_MAX_PKTCOUNT * maxpacket; + usbhost_trace2(OTGFS_TRACE2_CLIP, chidx, chan->buflen); + } + } + else + { + /* One packet will be sent/received (might be a zero length packet) */ + + npackets = 1; + } + + /* If it is an IN transfer, then adjust the size of the buffer UP to + * a full number of packets. Hmmm... couldn't this cause an overrun + * into unallocated memory? + */ + +#if 0 /* Think about this */ + if (chan->in) + { + /* Force the buffer length to an even multiple of maxpacket */ + + chan->buflen = npackets * maxpacket; + } +#endif + + /* Save the number of packets in the transfer. We will need this in + * order to set the next data toggle correctly when the transfer + * completes. + */ + + chan->npackets = (uint8_t)npackets; + + /* Setup the HCTSIZn register */ + + regval = ((uint32_t)chan->buflen << OTGFS_HCTSIZ_XFRSIZ_SHIFT) | + ((uint32_t)npackets << OTGFS_HCTSIZ_PKTCNT_SHIFT) | + ((uint32_t)chan->pid << OTGFS_HCTSIZ_DPID_SHIFT); + stm32_putreg(STM32_OTGFS_HCTSIZ(chidx), regval); + + /* Setup the HCCHAR register: Frame oddness and host channel enable */ + + regval = stm32_getreg(STM32_OTGFS_HCCHAR(chidx)); + + /* Set/clear the Odd Frame bit. Check for an even frame; if so set Odd + * Frame. This field is applicable for only periodic (isochronous and + * interrupt) channels. + */ + + if ((stm32_getreg(STM32_OTGFS_HFNUM) & 1) == 0) + { + regval |= OTGFS_HCCHAR_ODDFRM; + } + else + { + regval &= ~OTGFS_HCCHAR_ODDFRM; + } + + regval &= ~OTGFS_HCCHAR_CHDIS; + regval |= OTGFS_HCCHAR_CHENA; + stm32_putreg(STM32_OTGFS_HCCHAR(chidx), regval); + + /* If this is an out transfer, then we need to do more.. we need to copy + * the outgoing data into the correct TxFIFO. + */ + + if (!chan->in && chan->buflen > 0) + { + /* Handle non-periodic (CTRL and BULK) OUT transfers differently than + * periodic (INTR and ISOC) OUT transfers. + */ + + minsize = MIN(chan->buflen, chan->maxpacket); + + switch (chan->eptype) + { + case OTGFS_EPTYPE_CTRL: /* Non periodic transfer */ + case OTGFS_EPTYPE_BULK: + { + /* Read the Non-periodic Tx FIFO status register */ + + regval = stm32_getreg(STM32_OTGFS_HNPTXSTS); + avail = ((regval & OTGFS_HNPTXSTS_NPTXFSAV_MASK) >> + OTGFS_HNPTXSTS_NPTXFSAV_SHIFT) << 2; + } + break; + + /* Periodic transfer */ + + case OTGFS_EPTYPE_INTR: + case OTGFS_EPTYPE_ISOC: + { + /* Read the Non-periodic Tx FIFO status register */ + + regval = stm32_getreg(STM32_OTGFS_HPTXSTS); + avail = ((regval & OTGFS_HPTXSTS_PTXFSAVL_MASK) >> + OTGFS_HPTXSTS_PTXFSAVL_SHIFT) << 2; + } + break; + + default: + DEBUGPANIC(); + return; + } + + /* Is there space in the TxFIFO to hold the minimum size packet? */ + + if (minsize <= avail) + { + /* Yes.. Get the size of the biggest thing that we can put + * in the Tx FIFO now + */ + + wrsize = chan->buflen; + if (wrsize > avail) + { + /* Clip the write size to the number of full, max sized packets + * that will fit in the Tx FIFO. + */ + + unsigned int wrpackets = avail / chan->maxpacket; + wrsize = wrpackets * chan->maxpacket; + } + + /* Write packet into the Tx FIFO. */ + + stm32_gint_wrpacket(priv, chan->buffer, chidx, wrsize); + } + + /* Did we put the entire buffer into the Tx FIFO? */ + + if (chan->buflen > avail) + { + /* No, there was insufficient space to hold the entire transfer ... + * Enable the Tx FIFO interrupt to handle the transfer when the Tx + * FIFO becomes empty. + */ + + stm32_txfe_enable(priv, chidx); + } + } +} + +/**************************************************************************** + * Name: stm32_getframe + * + * Description: + * Get the current frame number. The frame number (FRNUM) field increments + * when a new SOF is transmitted on the USB, and is cleared to 0 when it + * reaches 0x3fff. + * + ****************************************************************************/ + +#if 0 /* Not used */ +static inline uint16_t stm32_getframe(void) +{ + return (uint16_t) + (stm32_getreg(STM32_OTGFS_HFNUM) & OTGFS_HFNUM_FRNUM_MASK); +} +#endif + +/**************************************************************************** + * Name: stm32_ctrl_sendsetup + * + * Description: + * Send an IN/OUT SETUP packet. + * + ****************************************************************************/ + +static int stm32_ctrl_sendsetup(struct stm32_usbhost_s *priv, + struct stm32_ctrlinfo_s *ep0, + const struct usb_ctrlreq_s *req) +{ + struct stm32_chan_s *chan; + clock_t start; + clock_t elapsed; + int ret; + + /* Loop while the device reports NAK (and a timeout is not exceeded */ + + chan = &priv->chan[ep0->outndx]; + start = clock_systime_ticks(); + + do + { + /* Send the SETUP packet */ + + chan->pid = OTGFS_PID_SETUP; + chan->buffer = (uint8_t *)req; + chan->buflen = USB_SIZEOF_CTRLREQ; + chan->xfrd = 0; + + /* Set up for the wait BEFORE starting the transfer */ + + ret = stm32_chan_waitsetup(priv, chan); + if (ret < 0) + { + usbhost_trace1(OTGFS_TRACE1_DEVDISCONN, 0); + return ret; + } + + /* Start the transfer */ + + stm32_transfer_start(priv, ep0->outndx); + + /* Wait for the transfer to complete */ + + ret = stm32_chan_wait(priv, chan); + + /* Return on success and for all failures other than EAGAIN. EAGAIN + * means that the device NAKed the SETUP command and that we should + * try a few more times. + */ + + if (ret != -EAGAIN) + { + /* Output some debug information if the transfer failed */ + + if (ret < 0) + { + usbhost_trace1(OTGFS_TRACE1_TRNSFRFAILED, ret); + } + + /* Return the result in any event */ + + return ret; + } + + /* Get the elapsed time (in frames) */ + + elapsed = clock_systime_ticks() - start; + } + while (elapsed < STM32_SETUP_DELAY); + + return -ETIMEDOUT; +} + +/**************************************************************************** + * Name: stm32_ctrl_senddata + * + * Description: + * Send data in the data phase of an OUT control transfer. Or send status + * in the status phase of an IN control transfer + * + ****************************************************************************/ + +static int stm32_ctrl_senddata(struct stm32_usbhost_s *priv, + struct stm32_ctrlinfo_s *ep0, + uint8_t *buffer, unsigned int buflen) +{ + struct stm32_chan_s *chan = &priv->chan[ep0->outndx]; + int ret; + + /* Save buffer information */ + + chan->buffer = buffer; + chan->buflen = buflen; + chan->xfrd = 0; + + /* Set the DATA PID */ + + if (buflen == 0) + { + /* For status OUT stage with buflen == 0, set PID DATA1 */ + + chan->outdata1 = true; + } + + /* Set the Data PID as per the outdata1 boolean */ + + chan->pid = chan->outdata1 ? OTGFS_PID_DATA1 : OTGFS_PID_DATA0; + + /* Set up for the wait BEFORE starting the transfer */ + + ret = stm32_chan_waitsetup(priv, chan); + if (ret < 0) + { + usbhost_trace1(OTGFS_TRACE1_DEVDISCONN, 0); + return ret; + } + + /* Start the transfer */ + + stm32_transfer_start(priv, ep0->outndx); + + /* Wait for the transfer to complete and return the result */ + + return stm32_chan_wait(priv, chan); +} + +/**************************************************************************** + * Name: stm32_ctrl_recvdata + * + * Description: + * Receive data in the data phase of an IN control transfer. Or receive + * status in the status phase of an OUT control transfer + * + ****************************************************************************/ + +static int stm32_ctrl_recvdata(struct stm32_usbhost_s *priv, + struct stm32_ctrlinfo_s *ep0, + uint8_t *buffer, unsigned int buflen) +{ + struct stm32_chan_s *chan = &priv->chan[ep0->inndx]; + int ret; + + /* Save buffer information */ + + chan->pid = OTGFS_PID_DATA1; + chan->buffer = buffer; + chan->buflen = buflen; + chan->xfrd = 0; + + /* Set up for the wait BEFORE starting the transfer */ + + ret = stm32_chan_waitsetup(priv, chan); + if (ret < 0) + { + usbhost_trace1(OTGFS_TRACE1_DEVDISCONN, 0); + return ret; + } + + /* Start the transfer */ + + stm32_transfer_start(priv, ep0->inndx); + + /* Wait for the transfer to complete and return the result */ + + return stm32_chan_wait(priv, chan); +} + +/**************************************************************************** + * Name: stm32_in_setup + * + * Description: + * Initiate an IN transfer on an bulk, interrupt, or isochronous pipe. + * + ****************************************************************************/ + +static int stm32_in_setup(struct stm32_usbhost_s *priv, int chidx) +{ + struct stm32_chan_s *chan; + + /* Set up for the transfer based on the direction and the endpoint type */ + + chan = &priv->chan[chidx]; + switch (chan->eptype) + { + default: + case OTGFS_EPTYPE_CTRL: /* Control */ + { + /* This kind of transfer on control endpoints other than EP0 are not + * currently supported + */ + + return -ENOSYS; + } + + case OTGFS_EPTYPE_ISOC: /* Isochronous */ + { + /* Set up the IN data PID */ + + usbhost_vtrace2(OTGFS_VTRACE2_ISOCIN, chidx, chan->buflen); + chan->pid = OTGFS_PID_DATA0; + } + break; + + case OTGFS_EPTYPE_BULK: /* Bulk */ + { + /* Setup the IN data PID */ + + usbhost_vtrace2(OTGFS_VTRACE2_BULKIN, chidx, chan->buflen); + chan->pid = chan->indata1 ? OTGFS_PID_DATA1 : OTGFS_PID_DATA0; + } + break; + + case OTGFS_EPTYPE_INTR: /* Interrupt */ + { + /* Setup the IN data PID */ + + usbhost_vtrace2(OTGFS_VTRACE2_INTRIN, chidx, chan->buflen); + chan->pid = chan->indata1 ? OTGFS_PID_DATA1 : OTGFS_PID_DATA0; + } + break; + } + + /* Start the transfer */ + + stm32_transfer_start(priv, chidx); + return OK; +} + +/**************************************************************************** + * Name: stm32_in_transfer + * + * Description: + * Transfer 'buflen' bytes into 'buffer' from an IN channel. + * + ****************************************************************************/ + +static ssize_t stm32_in_transfer(struct stm32_usbhost_s *priv, int chidx, + uint8_t *buffer, size_t buflen) +{ + struct stm32_chan_s *chan; + clock_t start; + ssize_t xfrd; + int ret; + + /* Loop until the transfer completes (i.e., buflen is decremented to zero) + * or a fatal error occurs any error other than a simple NAK. NAK would + * simply indicate the end of the transfer (short-transfer). + */ + + chan = &priv->chan[chidx]; + chan->buffer = buffer; + chan->buflen = buflen; + chan->xfrd = 0; + xfrd = 0; + + start = clock_systime_ticks(); + while (chan->xfrd < chan->buflen) + { + /* Set up for the wait BEFORE starting the transfer */ + + ret = stm32_chan_waitsetup(priv, chan); + if (ret < 0) + { + usbhost_trace1(OTGFS_TRACE1_DEVDISCONN, 0); + return (ssize_t)ret; + } + + /* Set up for the transfer based on the direction and the endpoint */ + + ret = stm32_in_setup(priv, chidx); + if (ret < 0) + { + uerr("ERROR: stm32_in_setup failed: %d\n", ret); + return (ssize_t)ret; + } + + /* Wait for the transfer to complete and get the result */ + + ret = stm32_chan_wait(priv, chan); + + /* EAGAIN indicates that the device NAKed the transfer. */ + + if (ret < 0) + { + /* The transfer failed. If we received a NAK, return all data + * buffered so far (if any). + */ + + if (ret == -EAGAIN) + { + /* Was data buffered prior to the NAK? */ + + if (xfrd > 0) + { + /* Yes, return the amount of data received. + * + * REVISIT: This behavior is clearly correct for CDC/ACM + * bulk transfers and HID interrupt transfers. But I am + * not so certain for MSC bulk transfers which, I think, + * could have NAKed packets in the middle of a transfer. + */ + + return xfrd; + } + else + { + useconds_t delay; + + /* Get the elapsed time. Has the timeout elapsed? + * if not then try again. + */ + + clock_t elapsed = clock_systime_ticks() - start; + if (elapsed >= STM32_DATANAK_DELAY) + { + /* Timeout out... break out returning the NAK as + * as a failure. + */ + + return (ssize_t)ret; + } + + /* Wait a bit before retrying after a NAK. */ + + if (chan->eptype == OTGFS_EPTYPE_INTR) + { + /* For interrupt (and isochronous) endpoints, the + * polling rate is determined by the bInterval field + * of the endpoint descriptor (in units of frames + * which we treat as milliseconds here). + */ + + if (chan->interval > 0) + { + /* Convert the delay to units of microseconds */ + + delay = (useconds_t)chan->interval * 1000; + } + else + { + /* Out of range! For interrupt endpoints, the valid + * range is 1-255 frames. Assume one frame. + */ + + delay = 1000; + } + } + else + { + /* For Isochronous endpoints, bInterval must be 1. + * Bulk endpoints do not have a polling interval. + * Rather, the should wait until data is received. + * + * REVISIT: For bulk endpoints this 1 msec delay is + * only intended to give the CPU a break from the bulk + * EP tight polling loop. But are there performance + * issues? + */ + + delay = 1000; + } + + /* Wait for the next polling interval. For interrupt and + * isochronous endpoints, this is necessary to assure the + * polling interval. It is used in other cases only to + * prevent the polling from consuming too much CPU + * bandwidth. + * + * Small delays could require more resolution than is + * provided by the system timer. For example, if the + * system timer resolution is 10MS, then + * nxsched_usleep(1000) will actually request a delay 20MS + * (due to both quantization and rounding). + * + * REVISIT: So which is better? To ignore tiny delays and + * hog the system bandwidth? Or to wait for an excessive + * amount and destroy system throughput? + */ + + if (delay > CONFIG_USEC_PER_TICK) + { + nxsched_usleep(delay - CONFIG_USEC_PER_TICK); + } + } + } + else + { + /* Some unexpected, fatal error occurred. */ + + usbhost_trace1(OTGFS_TRACE1_TRNSFRFAILED, ret); + + /* Break out and return the error */ + + uerr("ERROR: stm32_chan_wait failed: %d\n", ret); + return (ssize_t)ret; + } + } + else + { + /* Successfully received another chunk of data... add that to the + * running total. Then continue reading until we read 'buflen' + * bytes of data or until the devices NAKs (implying a short + * packet). + */ + + xfrd += chan->xfrd; + } + } + + return xfrd; +} + +/**************************************************************************** + * Name: stm32_in_next + * + * Description: + * Initiate the next of a sequence of asynchronous transfers. + * + * Assumptions: + * This function is always called from an interrupt handler + * + ****************************************************************************/ + +#ifdef CONFIG_USBHOST_ASYNCH +static void stm32_in_next(struct stm32_usbhost_s *priv, + struct stm32_chan_s *chan) +{ + usbhost_asynch_t callback; + void *arg; + ssize_t nbytes; + int result; + int ret; + + /* Is the full transfer complete? Did the last chunk transfer OK? */ + + result = -(int)chan->result; + if (chan->xfrd < chan->buflen && result == OK) + { + /* Yes.. Set up for the next transfer based on the direction and the + * endpoint type + */ + + ret = stm32_in_setup(priv, chan->chidx); + if (ret >= 0) + { + return; + } + + uerr("ERROR: stm32_in_setup failed: %d\n", ret); + result = ret; + } + + /* The transfer is complete, with or without an error */ + + uinfo("Transfer complete: %d\n", result); + + /* Extract the callback information */ + + callback = chan->callback; + arg = chan->arg; + nbytes = chan->xfrd; + + chan->callback = NULL; + chan->arg = NULL; + chan->xfrd = 0; + + /* Then perform the callback */ + + if (result < 0) + { + nbytes = (ssize_t)result; + } + + callback(arg, nbytes); +} +#endif + +/**************************************************************************** + * Name: stm32_in_asynch + * + * Description: + * Initiate the first of a sequence of asynchronous transfers. + * + * Assumptions: + * This function is never called from an interrupt handler + * + ****************************************************************************/ + +#ifdef CONFIG_USBHOST_ASYNCH +static int stm32_in_asynch(struct stm32_usbhost_s *priv, int chidx, + uint8_t *buffer, size_t buflen, + usbhost_asynch_t callback, void *arg) +{ + struct stm32_chan_s *chan; + int ret; + + /* Set up for the transfer BEFORE starting the first transfer */ + + chan = &priv->chan[chidx]; + chan->buffer = buffer; + chan->buflen = buflen; + chan->xfrd = 0; + + ret = stm32_chan_asynchsetup(priv, chan, callback, arg); + if (ret < 0) + { + uerr("ERROR: stm32_chan_asynchsetup failed: %d\n", ret); + return ret; + } + + /* Set up for the transfer based on the direction and the endpoint type */ + + ret = stm32_in_setup(priv, chidx); + if (ret < 0) + { + uerr("ERROR: stm32_in_setup failed: %d\n", ret); + } + + /* And return with the transfer pending */ + + return ret; +} +#endif + +/**************************************************************************** + * Name: stm32_out_setup + * + * Description: + * Initiate an OUT transfer on an bulk, interrupt, or isochronous pipe. + * + ****************************************************************************/ + +static int stm32_out_setup(struct stm32_usbhost_s *priv, int chidx) +{ + struct stm32_chan_s *chan; + + /* Set up for the transfer based on the direction and the endpoint type */ + + chan = &priv->chan[chidx]; + switch (chan->eptype) + { + default: + case OTGFS_EPTYPE_CTRL: /* Control */ + { + /* This kind of transfer on control endpoints other than EP0 are not + * currently supported + */ + + return -ENOSYS; + } + + case OTGFS_EPTYPE_ISOC: /* Isochronous */ + { + /* Set up the OUT data PID */ + + usbhost_vtrace2(OTGFS_VTRACE2_ISOCOUT, chidx, chan->buflen); + chan->pid = OTGFS_PID_DATA0; + } + break; + + case OTGFS_EPTYPE_BULK: /* Bulk */ + { + /* Setup the OUT data PID */ + + usbhost_vtrace2(OTGFS_VTRACE2_BULKOUT, chidx, chan->buflen); + chan->pid = chan->outdata1 ? OTGFS_PID_DATA1 : OTGFS_PID_DATA0; + } + break; + + case OTGFS_EPTYPE_INTR: /* Interrupt */ + { + /* Setup the OUT data PID */ + + usbhost_vtrace2(OTGFS_VTRACE2_INTROUT, chidx, chan->buflen); + chan->pid = chan->outdata1 ? OTGFS_PID_DATA1 : OTGFS_PID_DATA0; + + /* Toggle the OUT data PID for the next transfer */ + + chan->outdata1 ^= true; + } + break; + } + + /* Start the transfer */ + + stm32_transfer_start(priv, chidx); + return OK; +} + +/**************************************************************************** + * Name: stm32_out_transfer + * + * Description: + * Transfer the 'buflen' bytes in 'buffer' through an OUT channel. + * + ****************************************************************************/ + +static ssize_t stm32_out_transfer(struct stm32_usbhost_s *priv, + int chidx, uint8_t *buffer, + size_t buflen) +{ + struct stm32_chan_s *chan; + clock_t start; + clock_t elapsed; + size_t xfrlen; + ssize_t xfrd; + int ret; + bool zlp; + + /* Loop until the transfer completes (i.e., buflen is decremented to zero) + * or a fatal error occurs (any error other than a simple NAK) + */ + + chan = &priv->chan[chidx]; + start = clock_systime_ticks(); + xfrd = 0; + zlp = (buflen == 0); + + while (buflen > 0 || zlp) + { + /* Transfer one packet at a time. The hardware is capable of queueing + * multiple OUT packets, but I just haven't figured out how to handle + * the case where a single OUT packet in the group is NAKed. + */ + + xfrlen = MIN(chan->maxpacket, buflen); + chan->buffer = buffer; + chan->buflen = xfrlen; + chan->xfrd = 0; + + /* Set up for the wait BEFORE starting the transfer */ + + ret = stm32_chan_waitsetup(priv, chan); + if (ret < 0) + { + usbhost_trace1(OTGFS_TRACE1_DEVDISCONN, 0); + return (ssize_t)ret; + } + + /* Set up for the transfer based on the direction and the endpoint */ + + ret = stm32_out_setup(priv, chidx); + if (ret < 0) + { + uerr("ERROR: stm32_out_setup failed: %d\n", ret); + return (ssize_t)ret; + } + + /* Wait for the transfer to complete and get the result */ + + ret = stm32_chan_wait(priv, chan); + + /* Handle transfer failures */ + + if (ret < 0) + { + usbhost_trace1(OTGFS_TRACE1_TRNSFRFAILED, ret); + + /* Check for a special case: If (1) the transfer was NAKed and (2) + * no Tx FIFO empty or Rx FIFO not-empty event occurred, then we + * should be able to just flush the Rx and Tx FIFOs and try again. + * We can detect this latter case because then the transfer buffer + * pointer and buffer size will be unaltered. + */ + + elapsed = clock_systime_ticks() - start; + if (ret != -EAGAIN || /* Not a NAK condition OR */ + elapsed >= STM32_DATANAK_DELAY || /* Timeout has elapsed OR */ + chan->xfrd > 0) /* Data has been partially transferred */ + { + /* Break out and return the error */ + + uerr("ERROR: stm32_chan_wait failed: %d\n", ret); + return (ssize_t)ret; + } + + /* Is this flush really necessary? What does the hardware do with + * the data in the FIFO when the NAK occurs? Does it discard it? + */ + + stm32_flush_txfifos(OTGFS_GRSTCTL_TXFNUM_HALL); + + /* Get the device a little time to catch up. Then retry the + * transfer using the same buffer pointer and length. + */ + + nxsched_usleep(20 * 1000); + } + else + { + /* Successfully transferred. Update the buffer pointer/length */ + + buffer += xfrlen; + buflen -= xfrlen; + xfrd += chan->xfrd; + zlp = false; + } + } + + return xfrd; +} + +/**************************************************************************** + * Name: stm32_out_next + * + * Description: + * Initiate the next of a sequence of asynchronous transfers. + * + * Assumptions: + * This function is always called from an interrupt handler + * + ****************************************************************************/ + +#ifdef CONFIG_USBHOST_ASYNCH +static void stm32_out_next(struct stm32_usbhost_s *priv, + struct stm32_chan_s *chan) +{ + usbhost_asynch_t callback; + void *arg; + ssize_t nbytes; + int result; + int ret; + + /* Is the full transfer complete? Did the last chunk transfer OK? */ + + result = -(int)chan->result; + if (chan->xfrd < chan->buflen && result == OK) + { + /* Yes.. Set up for the next transfer based on the direction and the + * endpoint type + */ + + ret = stm32_out_setup(priv, chan->chidx); + if (ret >= 0) + { + return; + } + + uerr("ERROR: stm32_out_setup failed: %d\n", ret); + result = ret; + } + + /* The transfer is complete, with or without an error */ + + uinfo("Transfer complete: %d\n", result); + + /* Extract the callback information */ + + callback = chan->callback; + arg = chan->arg; + nbytes = chan->xfrd; + + chan->callback = NULL; + chan->arg = NULL; + chan->xfrd = 0; + + /* Then perform the callback */ + + if (result < 0) + { + nbytes = (ssize_t)result; + } + + callback(arg, nbytes); +} +#endif + +/**************************************************************************** + * Name: stm32_out_asynch + * + * Description: + * Initiate the first of a sequence of asynchronous transfers. + * + * Assumptions: + * This function is never called from an interrupt handler + * + ****************************************************************************/ + +#ifdef CONFIG_USBHOST_ASYNCH +static int stm32_out_asynch(struct stm32_usbhost_s *priv, int chidx, + uint8_t *buffer, size_t buflen, + usbhost_asynch_t callback, void *arg) +{ + struct stm32_chan_s *chan; + int ret; + + /* Set up for the transfer BEFORE starting the first transfer */ + + chan = &priv->chan[chidx]; + chan->buffer = buffer; + chan->buflen = buflen; + chan->xfrd = 0; + + ret = stm32_chan_asynchsetup(priv, chan, callback, arg); + if (ret < 0) + { + uerr("ERROR: stm32_chan_asynchsetup failed: %d\n", ret); + return ret; + } + + /* Set up for the transfer based on the direction and the endpoint type */ + + ret = stm32_out_setup(priv, chidx); + if (ret < 0) + { + uerr("ERROR: stm32_out_setup failed: %d\n", ret); + } + + /* And return with the transfer pending */ + + return ret; +} +#endif + +/**************************************************************************** + * Name: stm32_gint_wrpacket + * + * Description: + * Transfer the 'buflen' bytes in 'buffer' to the Tx FIFO associated with + * 'chidx' (non-DMA). + * + ****************************************************************************/ + +static void stm32_gint_wrpacket(struct stm32_usbhost_s *priv, + uint8_t *buffer, int chidx, int buflen) +{ + uint32_t *src; + uint32_t fifo; + int buflen32; + + stm32_pktdump("Sending", buffer, buflen); + + /* Get the number of 32-byte words associated with this byte size */ + + buflen32 = (buflen + 3) >> 2; + + /* Get the address of the Tx FIFO associated with this channel */ + + fifo = STM32_OTGFS_DFIFO_HCH(chidx); + + /* Transfer all of the data into the Tx FIFO */ + + src = (uint32_t *)buffer; + for (; buflen32 > 0; buflen32--) + { + uint32_t data = *src++; + stm32_putreg(fifo, data); + } + + /* Increment the count of bytes "in-flight" in the Tx FIFO */ + + priv->chan[chidx].inflight += buflen; +} + +/**************************************************************************** + * Name: stm32_gint_hcinisr + * + * Description: + * USB OTG FS host IN channels interrupt handler + * + * One the completion of the transfer, the channel result byte may be set + * as follows: + * + * OK - Transfer completed successfully + * EAGAIN - If devices NAKs the transfer or NYET occurs + * EPERM - If the endpoint stalls + * EIO - On a TX or data toggle error + * EPIPE - Frame overrun + * + * EBUSY in the result field indicates that the transfer has not completed. + * + ****************************************************************************/ + +static inline void stm32_gint_hcinisr(struct stm32_usbhost_s *priv, + int chidx) +{ + struct stm32_chan_s *chan = &priv->chan[chidx]; + uint32_t regval; + uint32_t pending; + + /* Read the HCINT register to get the pending HC interrupts. Read the + * HCINTMSK register to get the set of enabled HC interrupts. + */ + + pending = stm32_getreg(STM32_OTGFS_HCINT(chidx)); + regval = stm32_getreg(STM32_OTGFS_HCINTMSK(chidx)); + + /* AND the two to get the set of enabled, pending HC interrupts */ + + pending &= regval; + uinfo("HCINTMSK%d: %08" PRIx32 " pending: %08" PRIx32 "\n", + chidx, regval, pending); + + /* Check for a pending ACK response received/transmitted interrupt */ + + if ((pending & OTGFS_HCINT_ACK) != 0) + { + /* Clear the pending the ACK response received/transmitted interrupt */ + + stm32_putreg(STM32_OTGFS_HCINT(chidx), OTGFS_HCINT_ACK); + } + + /* Check for a pending STALL response receive (STALL) interrupt */ + + else if ((pending & OTGFS_HCINT_STALL) != 0) + { + /* Clear the NAK and STALL Conditions. */ + + stm32_putreg(STM32_OTGFS_HCINT(chidx), + OTGFS_HCINT_NAK | OTGFS_HCINT_STALL); + + /* Halt the channel when a STALL, TXERR, BBERR or DTERR interrupt is + * received on the channel. + */ + + stm32_chan_halt(priv, chidx, CHREASON_STALL); + + /* When there is a STALL, clear any pending NAK so that it is not + * processed below. + */ + + pending &= ~OTGFS_HCINT_NAK; + } + + /* Check for a pending Data Toggle ERRor (DTERR) interrupt */ + + else if ((pending & OTGFS_HCINT_DTERR) != 0) + { + /* Halt the channel when a STALL, TXERR, BBERR or DTERR interrupt is + * received on the channel. + */ + + stm32_chan_halt(priv, chidx, CHREASON_DTERR); + + /* Clear the NAK and data toggle error conditions */ + + stm32_putreg(STM32_OTGFS_HCINT(chidx), + OTGFS_HCINT_NAK | OTGFS_HCINT_DTERR); + } + + /* Check for a pending FRaMe OverRun (FRMOR) interrupt */ + + if ((pending & OTGFS_HCINT_FRMOR) != 0) + { + /* Halt the channel -- the CHH interrupt is expected next */ + + stm32_chan_halt(priv, chidx, CHREASON_FRMOR); + + /* Clear the FRaMe OverRun (FRMOR) condition */ + + stm32_putreg(STM32_OTGFS_HCINT(chidx), OTGFS_HCINT_FRMOR); + } + + /* Check for a pending TransFeR Completed (XFRC) interrupt */ + + else if ((pending & OTGFS_HCINT_XFRC) != 0) + { + /* Clear the TransFeR Completed (XFRC) condition */ + + stm32_putreg(STM32_OTGFS_HCINT(chidx), OTGFS_HCINT_XFRC); + + /* Then handle the transfer completion event based on the endpoint */ + + if (chan->eptype == OTGFS_EPTYPE_CTRL || + chan->eptype == OTGFS_EPTYPE_BULK) + { + /* Halt the channel -- the CHH interrupt is expected next */ + + stm32_chan_halt(priv, chidx, CHREASON_XFRC); + + /* Clear any pending NAK condition. The 'indata1' data toggle + * should have been appropriately updated by the RxFIFO + * logic as each packet was received. + */ + + stm32_putreg(STM32_OTGFS_HCINT(chidx), OTGFS_HCINT_NAK); + } + else if (chan->eptype == OTGFS_EPTYPE_INTR) + { + /* Force the next transfer on an ODD frame */ + + regval = stm32_getreg(STM32_OTGFS_HCCHAR(chidx)); + regval |= OTGFS_HCCHAR_ODDFRM; + stm32_putreg(STM32_OTGFS_HCCHAR(chidx), regval); + + /* Set the request done state */ + + chan->result = OK; + } + } + + /* Check for a pending CHannel Halted (CHH) interrupt */ + + else if ((pending & OTGFS_HCINT_CHH) != 0) + { + /* Mask the CHannel Halted (CHH) interrupt */ + + regval = stm32_getreg(STM32_OTGFS_HCINTMSK(chidx)); + regval &= ~OTGFS_HCINT_CHH; + stm32_putreg(STM32_OTGFS_HCINTMSK(chidx), regval); + + /* Update the request state based on the host state machine state */ + + if (chan->chreason == CHREASON_XFRC) + { + /* Set the request done result */ + + chan->result = OK; + } + else if (chan->chreason == CHREASON_STALL) + { + /* Set the request stall result */ + + chan->result = EPERM; + } + else if ((chan->chreason == CHREASON_TXERR) || + (chan->chreason == CHREASON_DTERR)) + { + /* Set the request I/O error result */ + + chan->result = EIO; + } + else if (chan->chreason == CHREASON_NAK) + { + /* Set the NAK error result */ + + chan->result = EAGAIN; + } + else /* if (chan->chreason == CHREASON_FRMOR) */ + { + /* Set the frame overrun error result */ + + chan->result = EPIPE; + } + + /* Clear the CHannel Halted (CHH) condition */ + + stm32_putreg(STM32_OTGFS_HCINT(chidx), OTGFS_HCINT_CHH); + } + + /* Check for a pending Transaction ERror (TXERR) interrupt */ + + else if ((pending & OTGFS_HCINT_TXERR) != 0) + { + /* Halt the channel when a STALL, TXERR, BBERR or DTERR interrupt is + * received on the channel. + */ + + stm32_chan_halt(priv, chidx, CHREASON_TXERR); + + /* Clear the Transaction ERror (TXERR) condition */ + + stm32_putreg(STM32_OTGFS_HCINT(chidx), OTGFS_HCINT_TXERR); + } + + /* Check for a pending NAK response received (NAK) interrupt */ + + else if ((pending & OTGFS_HCINT_NAK) != 0) + { + /* For a BULK transfer, the hardware is capable of retrying + * automatically on a NAK. However, this is not always + * what we need to do. So we always halt the transfer and + * return control to high level logic in the event of a NAK. + */ + +#if 1 + /* Halt the interrupt channel */ + + if (chan->eptype == OTGFS_EPTYPE_INTR || + chan->eptype == OTGFS_EPTYPE_BULK) + { + /* Halt the channel -- the CHH interrupt is expected next */ + + stm32_chan_halt(priv, chidx, CHREASON_NAK); + } + + /* Re-activate CTRL and BULK channels. + * + * REVISIT: This can cause a lot of interrupts! + * REVISIT: BULK endpoints are not re-activated. + */ + + else if (chan->eptype == OTGFS_EPTYPE_CTRL) + { + /* Re-activate the channel by clearing CHDIS and assuring that + * CHENA is set + * + * TODO: set channel reason to NACK? + */ + + regval = stm32_getreg(STM32_OTGFS_HCCHAR(chidx)); + regval |= OTGFS_HCCHAR_CHENA; + regval &= ~OTGFS_HCCHAR_CHDIS; + stm32_putreg(STM32_OTGFS_HCCHAR(chidx), regval); + } + +#else + /* Halt all transfers on the NAK -- CHH interrupt is expected next */ + + stm32_chan_halt(priv, chidx, CHREASON_NAK); +#endif + + /* Clear the NAK condition */ + + stm32_putreg(STM32_OTGFS_HCINT(chidx), OTGFS_HCINT_NAK); + } + + /* Check for a transfer complete event */ + + stm32_chan_wakeup(priv, chan); +} + +/**************************************************************************** + * Name: stm32_gint_hcoutisr + * + * Description: + * USB OTG FS host OUT channels interrupt handler + * + * One the completion of the transfer, the channel result byte may be set + * as follows: + * + * OK - Transfer completed successfully + * EAGAIN - If devices NAKs the transfer or NYET occurs + * EPERM - If the endpoint stalls + * EIO - On a TX or data toggle error + * EPIPE - Frame overrun + * + * EBUSY in the result field indicates that the transfer has not completed. + * + ****************************************************************************/ + +static inline void stm32_gint_hcoutisr(struct stm32_usbhost_s *priv, + int chidx) +{ + struct stm32_chan_s *chan = &priv->chan[chidx]; + uint32_t regval; + uint32_t pending; + + /* Read the HCINT register to get the pending HC interrupts. Read the + * HCINTMSK register to get the set of enabled HC interrupts. + */ + + pending = stm32_getreg(STM32_OTGFS_HCINT(chidx)); + regval = stm32_getreg(STM32_OTGFS_HCINTMSK(chidx)); + + /* AND the two to get the set of enabled, pending HC interrupts */ + + pending &= regval; + uinfo("HCINTMSK%d: %08" PRIx32 " pending: %08" PRIx32 "\n", + chidx, regval, pending); + + /* Check for a pending ACK response received/transmitted interrupt */ + + if ((pending & OTGFS_HCINT_ACK) != 0) + { + /* Clear the pending the ACK response received/transmitted interrupt */ + + stm32_putreg(STM32_OTGFS_HCINT(chidx), OTGFS_HCINT_ACK); + } + + /* Check for a pending FRaMe OverRun (FRMOR) interrupt */ + + else if ((pending & OTGFS_HCINT_FRMOR) != 0) + { + /* Halt the channel (probably not necessary for FRMOR) */ + + stm32_chan_halt(priv, chidx, CHREASON_FRMOR); + + /* Clear the pending the FRaMe OverRun (FRMOR) interrupt */ + + stm32_putreg(STM32_OTGFS_HCINT(chidx), OTGFS_HCINT_FRMOR); + } + + /* Check for a pending TransFeR Completed (XFRC) interrupt */ + + else if ((pending & OTGFS_HCINT_XFRC) != 0) + { + /* Decrement the number of bytes remaining by the number of + * bytes that were "in-flight". + */ + + priv->chan[chidx].buffer += priv->chan[chidx].inflight; + priv->chan[chidx].xfrd += priv->chan[chidx].inflight; + priv->chan[chidx].inflight = 0; + + /* Halt the channel -- the CHH interrupt is expected next */ + + stm32_chan_halt(priv, chidx, CHREASON_XFRC); + + /* Clear the pending the TransFeR Completed (XFRC) interrupt */ + + stm32_putreg(STM32_OTGFS_HCINT(chidx), OTGFS_HCINT_XFRC); + } + + /* Check for a pending STALL response receive (STALL) interrupt */ + + else if ((pending & OTGFS_HCINT_STALL) != 0) + { + /* Clear the pending the STALL response receive (STALL) interrupt */ + + stm32_putreg(STM32_OTGFS_HCINT(chidx), OTGFS_HCINT_STALL); + + /* Halt the channel when a STALL, TXERR, BBERR or DTERR interrupt is + * received on the channel. + */ + + stm32_chan_halt(priv, chidx, CHREASON_STALL); + } + + /* Check for a pending NAK response received (NAK) interrupt */ + + else if ((pending & OTGFS_HCINT_NAK) != 0) + { + /* Halt the channel -- the CHH interrupt is expected next */ + + stm32_chan_halt(priv, chidx, CHREASON_NAK); + + /* Clear the pending the NAK response received (NAK) interrupt */ + + stm32_putreg(STM32_OTGFS_HCINT(chidx), OTGFS_HCINT_NAK); + } + + /* Check for a pending Transaction ERror (TXERR) interrupt */ + + else if ((pending & OTGFS_HCINT_TXERR) != 0) + { + /* Halt the channel when a STALL, TXERR, BBERR or DTERR interrupt is + * received on the channel. + */ + + stm32_chan_halt(priv, chidx, CHREASON_TXERR); + + /* Clear the pending the Transaction ERror (TXERR) interrupt */ + + stm32_putreg(STM32_OTGFS_HCINT(chidx), OTGFS_HCINT_TXERR); + } + + /* Check for a NYET interrupt */ + +#if 0 /* NYET is a reserved bit in the HCINT register */ + else if ((pending & OTGFS_HCINT_NYET) != 0) + { + /* Halt the channel */ + + stm32_chan_halt(priv, chidx, CHREASON_NYET); + + /* Clear the pending the NYET interrupt */ + + stm32_putreg(STM32_OTGFS_HCINT(chidx), OTGFS_HCINT_NYET); + } +#endif + + /* Check for a pending Data Toggle ERRor (DTERR) interrupt */ + + else if (pending & OTGFS_HCINT_DTERR) + { + /* Halt the channel when a STALL, TXERR, BBERR or DTERR interrupt is + * received on the channel. + */ + + stm32_chan_halt(priv, chidx, CHREASON_DTERR); + + /* Clear the pending the Data Toggle ERRor (DTERR) and NAK interrupts */ + + stm32_putreg(STM32_OTGFS_HCINT(chidx), + OTGFS_HCINT_DTERR | OTGFS_HCINT_NAK); + } + + /* Check for a pending CHannel Halted (CHH) interrupt */ + + else if ((pending & OTGFS_HCINT_CHH) != 0) + { + /* Mask the CHannel Halted (CHH) interrupt */ + + regval = stm32_getreg(STM32_OTGFS_HCINTMSK(chidx)); + regval &= ~OTGFS_HCINT_CHH; + stm32_putreg(STM32_OTGFS_HCINTMSK(chidx), regval); + + if (chan->chreason == CHREASON_XFRC) + { + /* Set the request done result */ + + chan->result = OK; + + /* Read the HCCHAR register to get the HCCHAR register to get + * the endpoint type. + */ + + regval = stm32_getreg(STM32_OTGFS_HCCHAR(chidx)); + + /* Is it a bulk endpoint? Were an odd number of packets + * transferred? + */ + + if ((regval & OTGFS_HCCHAR_EPTYP_MASK) == + OTGFS_HCCHAR_EPTYP_BULK && + (chan->npackets & 1) != 0) + { + /* Yes to both... toggle the data out PID */ + + chan->outdata1 ^= true; + } + } + else if (chan->chreason == CHREASON_NAK || + chan->chreason == CHREASON_NYET) + { + /* Set the try again later result */ + + chan->result = EAGAIN; + } + else if (chan->chreason == CHREASON_STALL) + { + /* Set the request stall result */ + + chan->result = EPERM; + } + else if ((chan->chreason == CHREASON_TXERR) || + (chan->chreason == CHREASON_DTERR)) + { + /* Set the I/O failure result */ + + chan->result = EIO; + } + else /* if (chan->chreason == CHREASON_FRMOR) */ + { + /* Set the frame error result */ + + chan->result = EPIPE; + } + + /* Clear the pending the CHannel Halted (CHH) interrupt */ + + stm32_putreg(STM32_OTGFS_HCINT(chidx), OTGFS_HCINT_CHH); + } + + /* Check for a transfer complete event */ + + stm32_chan_wakeup(priv, chan); +} + +/**************************************************************************** + * Name: stm32_gint_connected + * + * Description: + * Handle a connection event. + * + ****************************************************************************/ + +static void stm32_gint_connected(struct stm32_usbhost_s *priv) +{ + /* We we previously disconnected? */ + + if (!priv->connected) + { + /* Yes.. then now we are connected */ + + usbhost_vtrace1(OTGFS_VTRACE1_CONNECTED, 0); + priv->connected = true; + priv->change = true; + DEBUGASSERT(priv->smstate == SMSTATE_DETACHED); + + /* Notify any waiters */ + + priv->smstate = SMSTATE_ATTACHED; + if (priv->pscwait) + { + nxsem_post(&priv->pscsem); + priv->pscwait = false; + } + } +} + +/**************************************************************************** + * Name: stm32_gint_disconnected + * + * Description: + * Handle a disconnection event. + * + ****************************************************************************/ + +static void stm32_gint_disconnected(struct stm32_usbhost_s *priv) +{ + /* Were we previously connected? */ + + if (priv->connected) + { + /* Yes.. then we no longer connected */ + + usbhost_vtrace1(OTGFS_VTRACE1_DISCONNECTED, 0); + + /* Are we bound to a class driver? */ + + if (priv->rhport.hport.devclass) + { + /* Yes.. Disconnect the class driver */ + + CLASS_DISCONNECTED(priv->rhport.hport.devclass); + priv->rhport.hport.devclass = NULL; + } + + /* Re-Initialize Host for new Enumeration */ + + priv->smstate = SMSTATE_DETACHED; + priv->connected = false; + priv->change = true; + stm32_chan_freeall(priv); + + priv->rhport.hport.speed = USB_SPEED_FULL; + priv->rhport.hport.funcaddr = 0; + + /* Notify any waiters that there is a change in the connection state */ + + if (priv->pscwait) + { + nxsem_post(&priv->pscsem); + priv->pscwait = false; + } + } +} + +/**************************************************************************** + * Name: stm32_gint_sofisr + * + * Description: + * USB OTG FS start-of-frame interrupt handler + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_OTGFS_SOFINTR +static inline void stm32_gint_sofisr(struct stm32_usbhost_s *priv) +{ + /* Handle SOF interrupt */ + +#warning "Do what?" + + /* Clear pending SOF interrupt */ + + stm32_putreg(STM32_OTGFS_GINTSTS, OTGFS_GINT_SOF); +} +#endif + +/**************************************************************************** + * Name: stm32_gint_rxflvlisr + * + * Description: + * USB OTG FS RxFIFO non-empty interrupt handler + * + ****************************************************************************/ + +static inline void stm32_gint_rxflvlisr(struct stm32_usbhost_s *priv) +{ + uint32_t *dest; + uint32_t grxsts; + uint32_t intmsk; + uint32_t hcchar; + uint32_t hctsiz; + uint32_t fifo; + int bcnt; + int bcnt32; + int chidx; + int i; + + /* Disable the RxFIFO non-empty interrupt */ + + intmsk = stm32_getreg(STM32_OTGFS_GINTMSK); + intmsk &= ~OTGFS_GINT_RXFLVL; + stm32_putreg(STM32_OTGFS_GINTMSK, intmsk); + + /* Read and pop the next status from the Rx FIFO */ + + grxsts = stm32_getreg(STM32_OTGFS_GRXSTSP); + uinfo("GRXSTS: %08" PRIx32 "\n", grxsts); + + /* Isolate the channel number/index in the status word */ + + chidx = (grxsts & OTGFS_GRXSTSH_CHNUM_MASK) >> OTGFS_GRXSTSH_CHNUM_SHIFT; + + /* Get the host channel characteristics register (HCCHAR) */ + + hcchar = stm32_getreg(STM32_OTGFS_HCCHAR(chidx)); + + /* Then process the interrupt according to the packet status */ + + switch (grxsts & OTGFS_GRXSTSH_PKTSTS_MASK) + { + case OTGFS_GRXSTSH_PKTSTS_INRECVD: /* IN data packet received */ + { + /* Read the data into the host buffer. */ + + bcnt = (grxsts & OTGFS_GRXSTSH_BCNT_MASK) >> + OTGFS_GRXSTSH_BCNT_SHIFT; + if (bcnt > 0 && priv->chan[chidx].buffer != NULL) + { + /* Transfer the packet from the Rx FIFO into the user buffer */ + + dest = (uint32_t *)priv->chan[chidx].buffer; + fifo = STM32_OTGFS_DFIFO_HCH(0); + bcnt32 = (bcnt + 3) >> 2; + + for (i = 0; i < bcnt32; i++) + { + *dest++ = stm32_getreg(fifo); + } + + stm32_pktdump("Received", priv->chan[chidx].buffer, bcnt); + + /* Toggle the IN data pid (Used by Bulk and INTR only) */ + + priv->chan[chidx].indata1 ^= true; + + /* Manage multiple packet transfers */ + + priv->chan[chidx].buffer += bcnt; + priv->chan[chidx].xfrd += bcnt; + + /* Check if more packets are expected */ + + hctsiz = stm32_getreg(STM32_OTGFS_HCTSIZ(chidx)); + if ((hctsiz & OTGFS_HCTSIZ_PKTCNT_MASK) != 0) + { + /* Re-activate the channel when more packets are expected */ + + hcchar |= OTGFS_HCCHAR_CHENA; + hcchar &= ~OTGFS_HCCHAR_CHDIS; + stm32_putreg(STM32_OTGFS_HCCHAR(chidx), hcchar); + } + } + } + break; + + case OTGFS_GRXSTSH_PKTSTS_INDONE: /* IN transfer completed */ + case OTGFS_GRXSTSH_PKTSTS_DTOGERR: /* Data toggle error */ + case OTGFS_GRXSTSH_PKTSTS_HALTED: /* Channel halted */ + default: + break; + } + + /* Re-enable the RxFIFO non-empty interrupt */ + + intmsk |= OTGFS_GINT_RXFLVL; + stm32_putreg(STM32_OTGFS_GINTMSK, intmsk); +} + +/**************************************************************************** + * Name: stm32_gint_nptxfeisr + * + * Description: + * USB OTG FS non-periodic TxFIFO empty interrupt handler + * + ****************************************************************************/ + +static inline void stm32_gint_nptxfeisr(struct stm32_usbhost_s *priv) +{ + struct stm32_chan_s *chan; + uint32_t regval; + unsigned int wrsize; + unsigned int avail; + unsigned int chidx; + + /* Recover the index of the channel that is waiting for space in the Tx + * FIFO. + */ + + chidx = priv->chidx; + chan = &priv->chan[chidx]; + + /* Reduce the buffer size by the number of bytes that were previously + * placed in the Tx FIFO. + */ + + chan->buffer += chan->inflight; + chan->xfrd += chan->inflight; + chan->inflight = 0; + + /* If we have now transferred the entire buffer, then this transfer is + * complete (this case really should never happen because we disable + * the NPTXFE interrupt on the final packet). + */ + + if (chan->xfrd >= chan->buflen) + { + /* Disable further Tx FIFO empty interrupts and bail. */ + + stm32_modifyreg(STM32_OTGFS_GINTMSK, OTGFS_GINT_NPTXFE, 0); + return; + } + + /* Read the status from the top of the non-periodic TxFIFO */ + + regval = stm32_getreg(STM32_OTGFS_HNPTXSTS); + + /* Extract the number of bytes available in the non-periodic Tx FIFO. */ + + avail = ((regval & OTGFS_HNPTXSTS_NPTXFSAV_MASK) >> + OTGFS_HNPTXSTS_NPTXFSAV_SHIFT) << 2; + + /* Get the size to put in the Tx FIFO now */ + + wrsize = chan->buflen - chan->xfrd; + + /* Get minimal size packet that can be sent. Something is seriously + * configured wrong if one packet will not fit into the empty Tx FIFO. + */ + + DEBUGASSERT(wrsize > 0 && avail >= MIN(wrsize, chan->maxpacket)); + if (wrsize > avail) + { + /* Clip the write size to the number of full, max sized packets + * that will fit in the Tx FIFO. + */ + + unsigned int wrpackets = avail / chan->maxpacket; + wrsize = wrpackets * chan->maxpacket; + } + + /* Otherwise, this will be the last packet to be sent in this transaction. + * We now need to disable further NPTXFE interrupts. + */ + + else + { + stm32_modifyreg(STM32_OTGFS_GINTMSK, OTGFS_GINT_NPTXFE, 0); + } + + /* Write the next group of packets into the Tx FIFO */ + + uinfo("HNPTXSTS: %08" PRIx32 " chidx: %d avail: %d buflen: %d xfrd: %d " + "wrsize: %d\n", + regval, chidx, avail, chan->buflen, chan->xfrd, wrsize); + + stm32_gint_wrpacket(priv, chan->buffer, chidx, wrsize); +} + +/**************************************************************************** + * Name: stm32_gint_ptxfeisr + * + * Description: + * USB OTG FS periodic TxFIFO empty interrupt handler + * + ****************************************************************************/ + +static inline void stm32_gint_ptxfeisr(struct stm32_usbhost_s *priv) +{ + struct stm32_chan_s *chan; + uint32_t regval; + unsigned int wrsize; + unsigned int avail; + unsigned int chidx; + + /* Recover the index of the channel that is waiting for space in the Tx + * FIFO. + */ + + chidx = priv->chidx; + chan = &priv->chan[chidx]; + + /* Reduce the buffer size by the number of bytes that were previously + * placed in the Tx FIFO. + */ + + chan->buffer += chan->inflight; + chan->xfrd += chan->inflight; + chan->inflight = 0; + + /* If we have now transferred the entire buffer, then this transfer is + * complete (this case really should never happen because we disable + * the PTXFE interrupt on the final packet). + */ + + if (chan->xfrd >= chan->buflen) + { + /* Disable further Tx FIFO empty interrupts and bail. */ + + stm32_modifyreg(STM32_OTGFS_GINTMSK, OTGFS_GINT_PTXFE, 0); + return; + } + + /* Read the status from the top of the periodic TxFIFO */ + + regval = stm32_getreg(STM32_OTGFS_HPTXSTS); + + /* Extract the number of bytes available in the periodic Tx FIFO. */ + + avail = ((regval & OTGFS_HPTXSTS_PTXFSAVL_MASK) >> + OTGFS_HPTXSTS_PTXFSAVL_SHIFT) << 2; + + /* Get the size to put in the Tx FIFO now */ + + wrsize = chan->buflen - chan->xfrd; + + /* Get minimal size packet that can be sent. Something is seriously + * configured wrong if one packet will not fit into the empty Tx FIFO. + */ + + DEBUGASSERT(wrsize && avail >= MIN(wrsize, chan->maxpacket)); + if (wrsize > avail) + { + /* Clip the write size to the number of full, max sized packets + * that will fit in the Tx FIFO. + */ + + unsigned int wrpackets = avail / chan->maxpacket; + wrsize = wrpackets * chan->maxpacket; + } + + /* Otherwise, this will be the last packet to be sent in this transaction. + * We now need to disable further PTXFE interrupts. + */ + + else + { + stm32_modifyreg(STM32_OTGFS_GINTMSK, OTGFS_GINT_PTXFE, 0); + } + + /* Write the next group of packets into the Tx FIFO */ + + uinfo("HPTXSTS: %08" PRIx32 + " chidx: %d avail: %d buflen: %d xfrd: %d wrsize: %d\n", + regval, chidx, avail, chan->buflen, chan->xfrd, wrsize); + + stm32_gint_wrpacket(priv, chan->buffer, chidx, wrsize); +} + +/**************************************************************************** + * Name: stm32_gint_hcisr + * + * Description: + * USB OTG FS host channels interrupt handler + * + ****************************************************************************/ + +static inline void stm32_gint_hcisr(struct stm32_usbhost_s *priv) +{ + uint32_t haint; + uint32_t hcchar; + int i = 0; + + /* Read the Host all channels interrupt register and test each bit in the + * register. Each bit i, i=0...(STM32_NHOST_CHANNELS-1), corresponds to + * a pending interrupt on channel i. + */ + + haint = stm32_getreg(STM32_OTGFS_HAINT); + for (i = 0; i < STM32_NHOST_CHANNELS; i++) + { + /* Is an interrupt pending on this channel? */ + + if ((haint & OTGFS_HAINT(i)) != 0) + { + /* Yes... read the HCCHAR register to get the direction bit */ + + hcchar = stm32_getreg(STM32_OTGFS_HCCHAR(i)); + + /* Was this an interrupt on an IN or an OUT channel? */ + + if ((hcchar & OTGFS_HCCHAR_EPDIR) != 0) + { + /* Handle the HC IN channel interrupt */ + + stm32_gint_hcinisr(priv, i); + } + else + { + /* Handle the HC OUT channel interrupt */ + + stm32_gint_hcoutisr(priv, i); + } + } + } +} + +/**************************************************************************** + * Name: stm32_gint_hprtisr + * + * Description: + * USB OTG FS host port interrupt handler + * + ****************************************************************************/ + +static inline void stm32_gint_hprtisr(struct stm32_usbhost_s *priv) +{ + uint32_t hprt; + uint32_t newhprt; + uint32_t hcfg; + + usbhost_vtrace1(OTGFS_VTRACE1_GINT_HPRT, 0); + + /* Read the port status and control register (HPRT) */ + + hprt = stm32_getreg(STM32_OTGFS_HPRT); + + /* Setup to clear the interrupt bits in GINTSTS by setting the + * corresponding bits in the HPRT. The HCINT interrupt bit is cleared + * when the appropriate status bits in the HPRT register are cleared. + */ + + newhprt = hprt & ~(OTGFS_HPRT_PENA | OTGFS_HPRT_PCDET | + OTGFS_HPRT_PENCHNG | OTGFS_HPRT_POCCHNG); + + /* Check for Port Over-urrent CHaNGe (POCCHNG) */ + + if ((hprt & OTGFS_HPRT_POCCHNG) != 0) + { + /* Set up to clear the POCCHNG status in the new HPRT contents. */ + + usbhost_vtrace1(OTGFS_VTRACE1_GINT_HPRT_POCCHNG, 0); + newhprt |= OTGFS_HPRT_POCCHNG; + } + + /* Check for Port Connect DETected (PCDET). The core sets this bit when a + * device connection is detected. + */ + + if ((hprt & OTGFS_HPRT_PCDET) != 0) + { + /* Set up to clear the PCDET status in the new HPRT contents. Then + * process the new connection event. + */ + + usbhost_vtrace1(OTGFS_VTRACE1_GINT_HPRT_PCDET, 0); + newhprt |= OTGFS_HPRT_PCDET; + stm32_portreset(priv); + stm32_gint_connected(priv); + } + + /* Check for Port Enable CHaNGed (PENCHNG) */ + + if ((hprt & OTGFS_HPRT_PENCHNG) != 0) + { + /* Set up to clear the PENCHNG status in the new HPRT contents. */ + + usbhost_vtrace1(OTGFS_VTRACE1_GINT_HPRT_PENCHNG, 0); + newhprt |= OTGFS_HPRT_PENCHNG; + + /* Was the port enabled? */ + + if ((hprt & OTGFS_HPRT_PENA) != 0) + { + /* Yes.. handle the new connection event */ + + stm32_gint_connected(priv); + + /* Check the Host ConFiGuration register (HCFG) */ + + hcfg = stm32_getreg(STM32_OTGFS_HCFG); + + /* Is this a low speed or full speed connection (OTG FS does not + * support high speed) + */ + + if ((hprt & OTGFS_HPRT_PSPD_MASK) == OTGFS_HPRT_PSPD_LS) + { + /* Set the Host Frame Interval Register for the 6KHz speed */ + + usbhost_vtrace1(OTGFS_VTRACE1_GINT_HPRT_LSDEV, 0); + stm32_putreg(STM32_OTGFS_HFIR, 6000); + + /* Are we switching from FS to LS? */ + + if ((hcfg & OTGFS_HCFG_FSLSPCS_MASK) != + OTGFS_HCFG_FSLSPCS_LS6MHz) + { + usbhost_vtrace1(OTGFS_VTRACE1_GINT_HPRT_FSLSSW, 0); + + /* Yes... configure for LS */ + + hcfg &= ~OTGFS_HCFG_FSLSPCS_MASK; + hcfg |= OTGFS_HCFG_FSLSPCS_LS6MHz; + stm32_putreg(STM32_OTGFS_HCFG, hcfg); + + /* And reset the port */ + + stm32_portreset(priv); + } + } + else /* if ((hprt & OTGFS_HPRT_PSPD_MASK) == OTGFS_HPRT_PSPD_FS) */ + { + usbhost_vtrace1(OTGFS_VTRACE1_GINT_HPRT_FSDEV, 0); + stm32_putreg(STM32_OTGFS_HFIR, 48000); + + /* Are we switching from LS to FS? */ + + if ((hcfg & OTGFS_HCFG_FSLSPCS_MASK) != + OTGFS_HCFG_FSLSPCS_FS48MHz) + { + usbhost_vtrace1(OTGFS_VTRACE1_GINT_HPRT_LSFSSW, 0); + + /* Yes... configure for FS */ + + hcfg &= ~OTGFS_HCFG_FSLSPCS_MASK; + hcfg |= OTGFS_HCFG_FSLSPCS_FS48MHz; + stm32_putreg(STM32_OTGFS_HCFG, hcfg); + + /* And reset the port */ + + stm32_portreset(priv); + } + } + } + } + + /* Clear port interrupts by setting bits in the HPRT */ + + stm32_putreg(STM32_OTGFS_HPRT, newhprt); +} + +/**************************************************************************** + * Name: stm32_gint_discisr + * + * Description: + * USB OTG FS disconnect detected interrupt handler + * + ****************************************************************************/ + +static inline void stm32_gint_discisr(struct stm32_usbhost_s *priv) +{ + /* Handle the disconnection event */ + + stm32_gint_disconnected(priv); + + /* Clear the dicsonnect interrupt */ + + stm32_putreg(STM32_OTGFS_GINTSTS, OTGFS_GINT_DISC); +} + +/**************************************************************************** + * Name: stm32_gint_ipxfrisr + * + * Description: + * USB OTG FS incomplete periodic interrupt handler + * + ****************************************************************************/ + +static inline void stm32_gint_ipxfrisr(struct stm32_usbhost_s *priv) +{ + uint32_t regval; + + /* CHENA : Set to enable the channel + * CHDIS : Set to stop transmitting/receiving data on a channel + */ + + regval = stm32_getreg(STM32_OTGFS_HCCHAR(0)); + regval |= (OTGFS_HCCHAR_CHDIS | OTGFS_HCCHAR_CHENA); + stm32_putreg(STM32_OTGFS_HCCHAR(0), regval); + + /* Clear the incomplete isochronous OUT interrupt */ + + stm32_putreg(STM32_OTGFS_GINTSTS, OTGFS_GINT_IPXFR); +} + +/**************************************************************************** + * Name: stm32_gint_isr + * + * Description: + * USB OTG FS global interrupt handler + * + ****************************************************************************/ + +static int stm32_gint_isr(int irq, void *context, void *arg) +{ + /* At present, there is only support for a single OTG FS host. Hence it is + * pre-allocated as g_usbhost. However, in most code, the private data + * structure will be referenced using the 'priv' pointer (rather than the + * global data) in order to simplify any future support for multiple + * devices. + */ + + struct stm32_usbhost_s *priv = &g_usbhost; + uint32_t pending; + + /* If OTG were supported, we would need to check if we are in host or + * device mode when the global interrupt occurs. Here we support only + * host mode + */ + + /* Loop while there are pending interrupts to process. This loop may save + * a little interrupt handling overhead. + */ + + for (; ; ) + { + /* Get the unmasked bits in the GINT status */ + + pending = stm32_getreg(STM32_OTGFS_GINTSTS); + pending &= stm32_getreg(STM32_OTGFS_GINTMSK); + + /* Return from the interrupt when there are no further pending + * interrupts. + */ + + if (pending == 0) + { + return OK; + } + + /* Otherwise, process each pending, unmasked GINT interrupts */ + + /* Handle the start of frame interrupt */ + +#ifdef CONFIG_STM32_OTGFS_SOFINTR + if ((pending & OTGFS_GINT_SOF) != 0) + { + usbhost_vtrace1(OTGFS_VTRACE1_GINT_SOF, 0); + stm32_gint_sofisr(priv); + } +#endif + + /* Handle the RxFIFO non-empty interrupt */ + + if ((pending & OTGFS_GINT_RXFLVL) != 0) + { + usbhost_vtrace1(OTGFS_VTRACE1_GINT_RXFLVL, 0); + stm32_gint_rxflvlisr(priv); + } + + /* Handle the non-periodic TxFIFO empty interrupt */ + + if ((pending & OTGFS_GINT_NPTXFE) != 0) + { + usbhost_vtrace1(OTGFS_VTRACE1_GINT_NPTXFE, 0); + stm32_gint_nptxfeisr(priv); + } + + /* Handle the periodic TxFIFO empty interrupt */ + + if ((pending & OTGFS_GINT_PTXFE) != 0) + { + usbhost_vtrace1(OTGFS_VTRACE1_GINT_PTXFE, 0); + stm32_gint_ptxfeisr(priv); + } + + /* Handle the host channels interrupt */ + + if ((pending & OTGFS_GINT_HC) != 0) + { + usbhost_vtrace1(OTGFS_VTRACE1_GINT_HC, 0); + stm32_gint_hcisr(priv); + } + + /* Handle the host port interrupt */ + + if ((pending & OTGFS_GINT_HPRT) != 0) + { + stm32_gint_hprtisr(priv); + } + + /* Handle the disconnect detected interrupt */ + + if ((pending & OTGFS_GINT_DISC) != 0) + { + usbhost_vtrace1(OTGFS_VTRACE1_GINT_DISC, 0); + stm32_gint_discisr(priv); + } + + /* Handle the incomplete periodic transfer */ + + if ((pending & OTGFS_GINT_IPXFR) != 0) + { + usbhost_vtrace1(OTGFS_VTRACE1_GINT_IPXFR, 0); + stm32_gint_ipxfrisr(priv); + } + } + + /* We won't get here */ + + return OK; +} + +/**************************************************************************** + * Name: stm32_gint_enable and stm32_gint_disable + * + * Description: + * Respectively enable or disable the global OTG FS interrupt. + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void stm32_gint_enable(void) +{ + uint32_t regval; + + /* Set the GINTMSK bit to unmask the interrupt */ + + regval = stm32_getreg(STM32_OTGFS_GAHBCFG); + regval |= OTGFS_GAHBCFG_GINTMSK; + stm32_putreg(STM32_OTGFS_GAHBCFG, regval); +} + +static void stm32_gint_disable(void) +{ + uint32_t regval; + + /* Clear the GINTMSK bit to mask the interrupt */ + + regval = stm32_getreg(STM32_OTGFS_GAHBCFG); + regval &= ~OTGFS_GAHBCFG_GINTMSK; + stm32_putreg(STM32_OTGFS_GAHBCFG, regval); +} + +/**************************************************************************** + * Name: stm32_hostinit_enable + * + * Description: + * Enable host interrupts. + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +static inline void stm32_hostinit_enable(void) +{ + uint32_t regval; + + /* Disable all interrupts. */ + + stm32_putreg(STM32_OTGFS_GINTMSK, 0); + + /* Clear any pending interrupts. */ + + stm32_putreg(STM32_OTGFS_GINTSTS, 0xffffffff); + + /* Clear any pending USB OTG Interrupts */ + + stm32_putreg(STM32_OTGFS_GOTGINT, 0xffffffff); + + /* Clear any pending USB OTG interrupts */ + + stm32_putreg(STM32_OTGFS_GINTSTS, 0xbfffffff); + + /* Enable the host interrupts */ + + /* Common interrupts: + * + * OTGFS_GINT_WKUP : Resume/remote wakeup detected interrupt + * OTGFS_GINT_USBSUSP : USB suspend + */ + + regval = (OTGFS_GINT_WKUP | OTGFS_GINT_USBSUSP); + + /* If OTG were supported, we would need to enable the following as well: + * + * OTGFS_GINT_OTG : OTG interrupt + * OTGFS_GINT_SRQ : Session request/new session detected interrupt + * OTGFS_GINT_CIDSCHG : Connector ID status change + */ + + /* Host-specific interrupts + * + * OTGFS_GINT_SOF : Start of frame + * OTGFS_GINT_RXFLVL : RxFIFO non-empty + * OTGFS_GINT_IISOOXFR : Incomplete isochronous OUT transfer + * OTGFS_GINT_HPRT : Host port interrupt + * OTGFS_GINT_HC : Host channels interrupt + * OTGFS_GINT_DISC : Disconnect detected interrupt + */ + +#ifdef CONFIG_STM32_OTGFS_SOFINTR + regval |= (OTGFS_GINT_SOF | OTGFS_GINT_RXFLVL | OTGFS_GINT_IISOOXFR | + OTGFS_GINT_HPRT | OTGFS_GINT_HC | OTGFS_GINT_DISC); +#else + regval |= (OTGFS_GINT_RXFLVL | OTGFS_GINT_IPXFR | OTGFS_GINT_HPRT | + OTGFS_GINT_HC | OTGFS_GINT_DISC); +#endif + stm32_putreg(STM32_OTGFS_GINTMSK, regval); +} + +/**************************************************************************** + * Name: stm32_txfe_enable + * + * Description: + * Enable Tx FIFO empty interrupts. This is necessary when the entire + * transfer will not fit into Tx FIFO. The transfer will then be completed + * when the Tx FIFO is empty. NOTE: The Tx FIFO interrupt is disabled + * the fifo empty interrupt handler when the transfer is complete. + * + * Input Parameters: + * priv - Driver state structure reference + * chidx - The channel that requires the Tx FIFO empty interrupt + * + * Returned Value: + * None + * + * Assumptions: + * Called from user task context. Interrupts must be disabled to assure + * exclusive access to the GINTMSK register. + * + ****************************************************************************/ + +static void stm32_txfe_enable(struct stm32_usbhost_s *priv, int chidx) +{ + struct stm32_chan_s *chan = &priv->chan[chidx]; + irqstate_t flags; + uint32_t regval; + + /* Disable all interrupts so that we have exclusive access to the GINTMSK + * (it would be sufficient just to disable the GINT interrupt). + */ + + flags = enter_critical_section(); + + /* Should we enable the periodic or non-peridic Tx FIFO empty interrupts */ + + regval = stm32_getreg(STM32_OTGFS_GINTMSK); + switch (chan->eptype) + { + default: + case OTGFS_EPTYPE_CTRL: /* Non periodic transfer */ + case OTGFS_EPTYPE_BULK: + regval |= OTGFS_GINT_NPTXFE; + break; + + case OTGFS_EPTYPE_INTR: /* Periodic transfer */ + case OTGFS_EPTYPE_ISOC: + regval |= OTGFS_GINT_PTXFE; + break; + } + + /* Enable interrupts */ + + stm32_putreg(STM32_OTGFS_GINTMSK, regval); + leave_critical_section(flags); +} + +/**************************************************************************** + * USB Host Controller Operations + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_wait + * + * Description: + * Wait for a device to be connected or disconnected to/from a hub port. + * + * Input Parameters: + * conn - The USB host connection instance obtained as a parameter from + * the call to the USB driver initialization logic. + * hport - The location to return the hub port descriptor that detected + * the connection related event. + * + * Returned Value: + * Zero (OK) is returned on success when a device is connected or + * disconnected. This function will not return until either (1) a device is + * connected or disconnect to/from any hub port or until (2) some failure + * occurs. On a failure, a negated errno value is returned indicating the + * nature of the failure + * + * Assumptions: + * - Called from a single thread so no mutual exclusion is required. + * - Never called from an interrupt handler. + * + ****************************************************************************/ + +static int stm32_wait(struct usbhost_connection_s *conn, + struct usbhost_hubport_s **hport) +{ + struct stm32_usbhost_s *priv = &g_usbhost; + struct usbhost_hubport_s *connport; + irqstate_t flags; + int ret; + + /* Loop until a change in connection state is detected */ + + flags = enter_critical_section(); + for (; ; ) + { + /* Is there a change in the connection state of the single root hub + * port? + */ + + if (priv->change) + { + connport = &priv->rhport.hport; + + /* Yes. Remember the new state */ + + connport->connected = priv->connected; + priv->change = false; + + /* And return the root hub port */ + + *hport = connport; + leave_critical_section(flags); + + uinfo("RHport Connected: %s\n", + connport->connected ? "YES" : "NO"); + return OK; + } + +#ifdef CONFIG_USBHOST_HUB + /* Is a device connected to an external hub? */ + + if (priv->hport) + { + /* Yes.. return the external hub port */ + + connport = (struct usbhost_hubport_s *)priv->hport; + priv->hport = NULL; + + *hport = connport; + leave_critical_section(flags); + + uinfo("Hub port Connected: %s\n", + connport->connected ? "YES" : "NO"); + return OK; + } +#endif + + /* Wait for the next connection event */ + + priv->pscwait = true; + ret = nxsem_wait_uninterruptible(&priv->pscsem); + if (ret < 0) + { + return ret; + } + } +} + +/**************************************************************************** + * Name: stm32_enumerate + * + * Description: + * Enumerate the connected device. As part of this enumeration process, + * the driver will (1) get the device's configuration descriptor, (2) + * extract the class ID info from the configuration descriptor, (3) call + * usbhost_findclass() to find the class that supports this device, (4) + * call the create() method on the struct usbhost_registry_s interface + * to get a class instance, and finally (5) call the connect() method + * of the struct usbhost_class_s interface. After that, the class is in + * charge of the sequence of operations. + * + * Input Parameters: + * conn - The USB host connection instance obtained as a parameter from + * the call to the USB driver initialization logic. + * hport - The descriptor of the hub port that has the newly connected + * device. + * + * Returned Value: + * On success, zero (OK) is returned. On a failure, a negated errno value + * is returned indicating the nature of the failure + * + * Assumptions: + * This function will *not* be called from an interrupt handler. + * + ****************************************************************************/ + +static int stm32_rh_enumerate(struct stm32_usbhost_s *priv, + struct usbhost_connection_s *conn, + struct usbhost_hubport_s *hport) +{ + uint32_t regval; + int ret; + + DEBUGASSERT(conn != NULL && hport != NULL && hport->port == 0); + + /* Are we connected to a device? The caller should have called the wait() + * method first to be assured that a device is connected. + */ + + while (!priv->connected) + { + /* No, return an error */ + + usbhost_trace1(OTGFS_TRACE1_DEVDISCONN, 0); + return -ENODEV; + } + + DEBUGASSERT(priv->smstate == SMSTATE_ATTACHED); + + /* USB 2.0 spec says at least 50ms delay before port reset. We wait + * 100ms. + */ + + nxsched_usleep(100 * 1000); + + /* Reset the host port */ + + stm32_portreset(priv); + + /* Get the current device speed */ + + regval = stm32_getreg(STM32_OTGFS_HPRT); + if ((regval & OTGFS_HPRT_PSPD_MASK) == OTGFS_HPRT_PSPD_LS) + { + priv->rhport.hport.speed = USB_SPEED_LOW; + } + else + { + priv->rhport.hport.speed = USB_SPEED_FULL; + } + + /* Allocate and initialize the root hub port EP0 channels */ + + ret = stm32_ctrlchan_alloc(priv, 0, 0, priv->rhport.hport.speed, + &priv->ep0); + if (ret < 0) + { + uerr("ERROR: Failed to allocate a control endpoint: %d\n", ret); + } + + return ret; +} + +static int stm32_enumerate(struct usbhost_connection_s *conn, + struct usbhost_hubport_s *hport) +{ + struct stm32_usbhost_s *priv = &g_usbhost; + int ret; + + DEBUGASSERT(hport); + + /* If this is a connection on the root hub, then we need to go to + * little more effort to get the device speed. If it is a connection + * on an external hub, then we already have that information. + */ + +#ifdef CONFIG_USBHOST_HUB + if (ROOTHUB(hport)) +#endif + { + ret = stm32_rh_enumerate(priv, conn, hport); + if (ret < 0) + { + return ret; + } + } + + /* Then let the common usbhost_enumerate do the real enumeration. */ + + uinfo("Enumerate the device\n"); + priv->smstate = SMSTATE_ENUM; + ret = usbhost_enumerate(hport, &hport->devclass); + + /* The enumeration may fail either because of some HCD interfaces failure + * or because the device class is not supported. In either case, we just + * need to perform the disconnection operation and make ready for a new + * enumeration. + */ + + if (ret < 0) + { + /* Return to the disconnected state */ + + uerr("ERROR: Enumeration failed: %d\n", ret); + stm32_gint_disconnected(priv); + } + + return ret; +} + +/**************************************************************************** + * Name: stm32_ep0configure + * + * Description: + * Configure endpoint 0. This method is normally used internally by the + * enumerate() method but is made available at the interface to support an + * external implementation of the enumeration logic. + * + * Input Parameters: + * drvr - The USB host driver instance obtained as a parameter from the + * call to the class create() method. + * ep0 - The (opaque) EP0 endpoint instance + * funcaddr - The USB address of the function containing the endpoint that + * EP0 controls + * speed - The speed of the port USB_SPEED_LOW, _FULL, or _HIGH + * maxpacketsize - The maximum number of bytes that can be sent to or + * received from the endpoint in a single data packet + * + * Returned Value: + * On success, zero (OK) is returned. On a failure, a negated errno value + * is returned indicating the nature of the failure + * + * Assumptions: + * This function will *not* be called from an interrupt handler. + * + ****************************************************************************/ + +static int stm32_ep0configure(struct usbhost_driver_s *drvr, + usbhost_ep_t ep0, uint8_t funcaddr, + uint8_t speed, uint16_t maxpacketsize) +{ + struct stm32_usbhost_s *priv = (struct stm32_usbhost_s *)drvr; + struct stm32_ctrlinfo_s *ep0info = (struct stm32_ctrlinfo_s *)ep0; + struct stm32_chan_s *chan; + int ret; + + DEBUGASSERT(drvr != NULL && ep0info != NULL && funcaddr < 128 && + maxpacketsize <= 64); + + /* We must have exclusive access to the USB host hardware and structures */ + + ret = nxmutex_lock(&priv->lock); + if (ret < 0) + { + return ret; + } + + /* Configure the EP0 OUT channel */ + + chan = &priv->chan[ep0info->outndx]; + chan->funcaddr = funcaddr; + chan->speed = speed; + chan->maxpacket = maxpacketsize; + + stm32_chan_configure(priv, ep0info->outndx); + + /* Configure the EP0 IN channel */ + + chan = &priv->chan[ep0info->inndx]; + chan->funcaddr = funcaddr; + chan->speed = speed; + chan->maxpacket = maxpacketsize; + + stm32_chan_configure(priv, ep0info->inndx); + + nxmutex_unlock(&priv->lock); + return OK; +} + +/**************************************************************************** + * Name: stm32_epalloc + * + * Description: + * Allocate and configure one endpoint. + * + * Input Parameters: + * drvr - The USB host driver instance obtained as a parameter from the + * call to the class create() method. + * epdesc - Describes the endpoint to be allocated. + * ep - A memory location provided by the caller in which to receive the + * allocated endpoint descriptor. + * + * Returned Value: + * On success, zero (OK) is returned. On a failure, a negated errno value + * is returned indicating the nature of the failure + * + * Assumptions: + * This function will *not* be called from an interrupt handler. + * + ****************************************************************************/ + +static int stm32_epalloc(struct usbhost_driver_s *drvr, + const struct usbhost_epdesc_s *epdesc, + usbhost_ep_t *ep) +{ + struct stm32_usbhost_s *priv = (struct stm32_usbhost_s *)drvr; + int ret; + + /* Sanity check. NOTE that this method should only be called if a device + * is connected (because we need a valid low speed indication). + */ + + DEBUGASSERT(drvr != 0 && epdesc != NULL && ep != NULL); + + /* We must have exclusive access to the USB host hardware and structures */ + + ret = nxmutex_lock(&priv->lock); + if (ret < 0) + { + return ret; + } + + /* Handler control pipes differently from other endpoint types. This is + * because the normal, "transfer" endpoints are unidirectional an require + * only a single channel. Control endpoints, however, are bi-diretional + * and require two channels, one for the IN and one for the OUT direction. + */ + + if (epdesc->xfrtype == OTGFS_EPTYPE_CTRL) + { + ret = stm32_ctrlep_alloc(priv, epdesc, ep); + } + else + { + ret = stm32_xfrep_alloc(priv, epdesc, ep); + } + + nxmutex_unlock(&priv->lock); + return ret; +} + +/**************************************************************************** + * Name: stm32_epfree + * + * Description: + * Free and endpoint previously allocated by DRVR_EPALLOC. + * + * Input Parameters: + * drvr - The USB host driver instance obtained as a parameter from the + * call to the class create() method. + * ep - The endpoint to be freed. + * + * Returned Value: + * On success, zero (OK) is returned. On a failure, a negated errno value + * is returned indicating the nature of the failure + * + * Assumptions: + * This function will *not* be called from an interrupt handler. + * + ****************************************************************************/ + +static int stm32_epfree(struct usbhost_driver_s *drvr, usbhost_ep_t ep) +{ + struct stm32_usbhost_s *priv = (struct stm32_usbhost_s *)drvr; + int ret; + + DEBUGASSERT(priv); + + /* We must have exclusive access to the USB host hardware and structures */ + + ret = nxmutex_lock(&priv->lock); + + /* A single channel is represent by an index in the range of 0 to + * STM32_MAX_TX_FIFOS. Otherwise, the ep must be a pointer to an allocated + * control endpoint structure. + */ + + if ((uintptr_t)ep < STM32_MAX_TX_FIFOS) + { + /* Halt the channel and mark the channel available */ + + stm32_chan_free(priv, (int)ep); + } + else + { + /* Halt both control channel and mark the channels available */ + + struct stm32_ctrlinfo_s *ctrlep = + (struct stm32_ctrlinfo_s *)ep; + + stm32_chan_free(priv, ctrlep->inndx); + stm32_chan_free(priv, ctrlep->outndx); + + /* And free the control endpoint container */ + + kmm_free(ctrlep); + } + + nxmutex_unlock(&priv->lock); + return ret; +} + +/**************************************************************************** + * Name: stm32_alloc + * + * Description: + * Some hardware supports special memory in which request and descriptor + * data can be accessed more efficiently. This method provides a + * mechanism to allocate the request/descriptor memory. If the underlying + * hardware does not support such "special" memory, this functions may + * simply map to kmm_malloc. + * + * This interface was optimized under a particular assumption. It was + * assumed that the driver maintains a pool of small, pre-allocated + * buffers for descriptor traffic. NOTE that size is not an input, but + * an output: The size of the pre-allocated buffer is returned. + * + * Input Parameters: + * drvr - The USB host driver instance obtained as a parameter from the + * call to the class create() method. + * buffer - The address of a memory location provided by the caller in + * which to return the allocated buffer memory address. + * maxlen - The address of a memory location provided by the caller in + * which to return the maximum size of the allocated buffer memory. + * + * Returned Value: + * On success, zero (OK) is returned. On a failure, a negated errno value + * is returned indicating the nature of the failure + * + * Assumptions: + * - Called from a single thread so no mutual exclusion is required. + * - Never called from an interrupt handler. + * + ****************************************************************************/ + +static int stm32_alloc(struct usbhost_driver_s *drvr, + uint8_t **buffer, size_t *maxlen) +{ + uint8_t *alloc; + + DEBUGASSERT(drvr && buffer && maxlen); + + /* There is no special memory requirement for the STM32. */ + + alloc = kmm_malloc(CONFIG_STM32_OTGFS_DESCSIZE); + if (!alloc) + { + return -ENOMEM; + } + + /* Return the allocated address and size of the descriptor buffer */ + + *buffer = alloc; + *maxlen = CONFIG_STM32_OTGFS_DESCSIZE; + return OK; +} + +/**************************************************************************** + * Name: stm32_free + * + * Description: + * Some hardware supports special memory in which request and descriptor + * data can be accessed more efficiently. This method provides a + * mechanism to free that request/descriptor memory. If the underlying + * hardware does not support such "special" memory, this functions may + * simply map to kmm_free(). + * + * Input Parameters: + * drvr - The USB host driver instance obtained as a parameter from the + * call to the class create() method. + * buffer - The address of the allocated buffer memory to be freed. + * + * Returned Value: + * On success, zero (OK) is returned. On a failure, a negated errno value + * is returned indicating the nature of the failure + * + * Assumptions: + * - Never called from an interrupt handler. + * + ****************************************************************************/ + +static int stm32_free(struct usbhost_driver_s *drvr, uint8_t *buffer) +{ + /* There is no special memory requirement */ + + DEBUGASSERT(drvr && buffer); + kmm_free(buffer); + return OK; +} + +/**************************************************************************** + * Name: stm32_ioalloc + * + * Description: + * Some hardware supports special memory in which larger IO buffers can + * be accessed more efficiently. This method provides a mechanism to + * allocate the request/descriptor memory. If the underlying hardware + * does not support such "special" memory, this functions may simply map + * to kmm_malloc. + * + * This interface differs from DRVR_ALLOC in that the buffers are + * variable-sized. + * + * Input Parameters: + * drvr - The USB host driver instance obtained as a parameter from the + * call to the class create() method. + * buffer - The address of a memory location provided by the caller in + * which to return the allocated buffer memory address. + * buflen - The size of the buffer required. + * + * Returned Value: + * On success, zero (OK) is returned. On a failure, a negated errno value + * is returned indicating the nature of the failure + * + * Assumptions: + * This function will *not* be called from an interrupt handler. + * + ****************************************************************************/ + +static int stm32_ioalloc(struct usbhost_driver_s *drvr, + uint8_t **buffer, size_t buflen) +{ + uint8_t *alloc; + + DEBUGASSERT(drvr && buffer && buflen > 0); + + /* There is no special memory requirement */ + + alloc = kmm_malloc(buflen); + if (!alloc) + { + return -ENOMEM; + } + + /* Return the allocated buffer */ + + *buffer = alloc; + return OK; +} + +/**************************************************************************** + * Name: stm32_iofree + * + * Description: + * Some hardware supports special memory in which IO data can be accessed + * more efficiently. This method provides a mechanism to free that IO + * buffer memory. If the underlying hardware does not support such + * "special" memory, this functions may simply map to kmm_free(). + * + * Input Parameters: + * drvr - The USB host driver instance obtained as a parameter from the + * call to the class create() method. + * buffer - The address of the allocated buffer memory to be freed. + * + * Returned Value: + * On success, zero (OK) is returned. On a failure, a negated errno value + * is returned indicating the nature of the failure + * + * Assumptions: + * This function will *not* be called from an interrupt handler. + * + ****************************************************************************/ + +static int stm32_iofree(struct usbhost_driver_s *drvr, + uint8_t *buffer) +{ + /* There is no special memory requirement */ + + DEBUGASSERT(drvr && buffer); + kmm_free(buffer); + return OK; +} + +/**************************************************************************** + * Name: stm32_ctrlin and stm32_ctrlout + * + * Description: + * Process a IN or OUT request on the control endpoint. These methods + * will enqueue the request and wait for it to complete. Only one + * transfer may be queued; Neither these methods nor the transfer() + * method can be called again until the control transfer functions + * returns. + * + * These are blocking methods; these functions will not return until the + * control transfer has completed. + * + * Input Parameters: + * drvr - The USB host driver instance obtained as a parameter from the + * call to the class create() method. + * ep0 - The control endpoint to send/receive the control request. + * req - Describes the request to be sent. This request must lie in memory + * created by DRVR_ALLOC. + * buffer - A buffer used for sending the request and for returning any + * responses. This buffer must be large enough to hold the length value + * in the request description. buffer must have been allocated using + * DRVR_ALLOC. + * + * NOTE: On an IN transaction, req and buffer may refer to the same + * allocated memory. + * + * Returned Value: + * On success, zero (OK) is returned. On a failure, a negated errno value + * is returned indicating the nature of the failure + * + * Assumptions: + * - Called from a single thread so no mutual exclusion is required. + * - Never called from an interrupt handler. + * + ****************************************************************************/ + +static int stm32_ctrlin(struct usbhost_driver_s *drvr, usbhost_ep_t ep0, + const struct usb_ctrlreq_s *req, + uint8_t *buffer) +{ + struct stm32_usbhost_s *priv = (struct stm32_usbhost_s *)drvr; + struct stm32_ctrlinfo_s *ep0info = (struct stm32_ctrlinfo_s *)ep0; + uint16_t buflen; + clock_t start; + clock_t elapsed; + int retries; + int ret; + + DEBUGASSERT(priv != NULL && ep0info != NULL && req != NULL); + usbhost_vtrace2(OTGFS_VTRACE2_CTRLIN, req->type, req->req); + uinfo("type:%02x req:%02x value:%02x%02x index:%02x%02x len:%02x%02x\n", + req->type, req->req, req->value[1], req->value[0], + req->index[1], req->index[0], req->len[1], req->len[0]); + + /* Extract values from the request */ + + buflen = stm32_getle16(req->len); + + /* We must have exclusive access to the USB host hardware and structures */ + + ret = nxmutex_lock(&priv->lock); + if (ret < 0) + { + return ret; + } + + /* Loop, retrying until the retry time expires */ + + for (retries = 0; retries < STM32_RETRY_COUNT; retries++) + { + /* Send the SETUP request */ + + ret = stm32_ctrl_sendsetup(priv, ep0info, req); + if (ret < 0) + { + usbhost_trace1(OTGFS_TRACE1_SENDSETUP, -ret); + continue; + } + + /* Handle the IN data phase (if any) */ + + if (buflen > 0) + { + ret = stm32_ctrl_recvdata(priv, ep0info, buffer, buflen); + if (ret < 0) + { + usbhost_trace1(OTGFS_TRACE1_RECVDATA, -ret); + continue; + } + } + + /* Get the start time. Loop again until the timeout expires */ + + start = clock_systime_ticks(); + do + { + /* Handle the status OUT phase */ + + priv->chan[ep0info->outndx].outdata1 ^= true; + ret = stm32_ctrl_senddata(priv, ep0info, NULL, 0); + if (ret == OK) + { + /* All success transactions exit here */ + + nxmutex_unlock(&priv->lock); + return OK; + } + + usbhost_trace1(OTGFS_TRACE1_SENDDATA, ret < 0 ? -ret : ret); + + /* Get the elapsed time (in frames) */ + + elapsed = clock_systime_ticks() - start; + } + while (elapsed < STM32_DATANAK_DELAY); + } + + /* All failures exit here after all retries and timeouts are exhausted */ + + nxmutex_unlock(&priv->lock); + return -ETIMEDOUT; +} + +static int stm32_ctrlout(struct usbhost_driver_s *drvr, usbhost_ep_t ep0, + const struct usb_ctrlreq_s *req, + const uint8_t *buffer) +{ + struct stm32_usbhost_s *priv = (struct stm32_usbhost_s *)drvr; + struct stm32_ctrlinfo_s *ep0info = (struct stm32_ctrlinfo_s *)ep0; + uint16_t buflen; + clock_t start; + clock_t elapsed; + int retries; + int ret; + + DEBUGASSERT(priv != NULL && ep0info != NULL && req != NULL); + usbhost_vtrace2(OTGFS_VTRACE2_CTRLOUT, req->type, req->req); + uinfo("type:%02x req:%02x value:%02x%02x index:%02x%02x len:%02x%02x\n", + req->type, req->req, req->value[1], req->value[0], + req->index[1], req->index[0], req->len[1], req->len[0]); + + /* Extract values from the request */ + + buflen = stm32_getle16(req->len); + + /* We must have exclusive access to the USB host hardware and structures */ + + ret = nxmutex_lock(&priv->lock); + if (ret < 0) + { + return ret; + } + + /* Loop, retrying until the retry time expires */ + + for (retries = 0; retries < STM32_RETRY_COUNT; retries++) + { + /* Send the SETUP request */ + + ret = stm32_ctrl_sendsetup(priv, ep0info, req); + if (ret < 0) + { + usbhost_trace1(OTGFS_TRACE1_SENDSETUP, -ret); + continue; + } + + /* Get the start time. Loop again until the timeout expires */ + + start = clock_systime_ticks(); + do + { + /* Handle the data OUT phase (if any) */ + + if (buflen > 0) + { + /* Start DATA out transfer (only one DATA packet) */ + + priv->chan[ep0info->outndx].outdata1 = true; + ret = stm32_ctrl_senddata(priv, ep0info, (uint8_t *)buffer, + buflen); + if (ret < 0) + { + usbhost_trace1(OTGFS_TRACE1_SENDDATA, -ret); + } + } + + /* Handle the status IN phase */ + + if (ret == OK) + { + ret = stm32_ctrl_recvdata(priv, ep0info, NULL, 0); + if (ret == OK) + { + /* All success transactins exit here */ + + nxmutex_unlock(&priv->lock); + return OK; + } + + usbhost_trace1(OTGFS_TRACE1_RECVDATA, ret < 0 ? -ret : ret); + } + + /* Get the elapsed time (in frames) */ + + elapsed = clock_systime_ticks() - start; + } + while (elapsed < STM32_DATANAK_DELAY); + } + + /* All failures exit here after all retries and timeouts are exhausted */ + + nxmutex_unlock(&priv->lock); + return -ETIMEDOUT; +} + +/**************************************************************************** + * Name: stm32_transfer + * + * Description: + * Process a request to handle a transfer descriptor. This method will + * enqueue the transfer request, blocking until the transfer completes. + * Only one transfer may be queued; Neither this method nor the ctrlin or + * ctrlout methods can be called again until this function returns. + * + * This is a blocking method; this functions will not return until the + * transfer has completed. + * + * Input Parameters: + * drvr - The USB host driver instance obtained as a parameter from the + * call to the class create() method. + * ep - The IN or OUT endpoint descriptor for the device endpoint on + * which to perform the transfer. + * buffer - A buffer containing the data to be sent (OUT endpoint) or + * received (IN endpoint). buffer must have been allocated using + * DRVR_ALLOC + * buflen - The length of the data to be sent or received. + * + * Returned Value: + * On success, a non-negative value is returned that indicates the number + * of bytes successfully transferred. On a failure, a negated errno value + * is returned that indicates the nature of the failure: + * + * EAGAIN - If devices NAKs the transfer (or NYET or other error where + * it may be appropriate to restart the entire transaction). + * EPERM - If the endpoint stalls + * EIO - On a TX or data toggle error + * EPIPE - Overrun errors + * + * Assumptions: + * - Called from a single thread so no mutual exclusion is required. + * - Never called from an interrupt handler. + * + ****************************************************************************/ + +static ssize_t stm32_transfer(struct usbhost_driver_s *drvr, + usbhost_ep_t ep, + uint8_t *buffer, size_t buflen) +{ + struct stm32_usbhost_s *priv = (struct stm32_usbhost_s *)drvr; + unsigned int chidx = (unsigned int)ep; + ssize_t nbytes; + int ret; + + uinfo("chidx: %d buflen: %d\n", (unsigned int)ep, buflen); + + DEBUGASSERT(priv && buffer && chidx < STM32_MAX_TX_FIFOS && buflen > 0); + + /* We must have exclusive access to the USB host hardware and structures */ + + ret = nxmutex_lock(&priv->lock); + if (ret < 0) + { + return (ssize_t)ret; + } + + /* Handle IN and OUT transfer slightly differently */ + + if (priv->chan[chidx].in) + { + nbytes = stm32_in_transfer(priv, chidx, buffer, buflen); + } + else + { + nbytes = stm32_out_transfer(priv, chidx, buffer, buflen); + } + + nxmutex_unlock(&priv->lock); + return nbytes; +} + +/**************************************************************************** + * Name: stm32_asynch + * + * Description: + * Process a request to handle a transfer descriptor. This method will + * enqueue the transfer request and return immediately. When the transfer + * completes, the callback will be invoked with the provided transfer. + * This method is useful for receiving interrupt transfers which may come + * infrequently. + * + * Only one transfer may be queued; Neither this method nor the ctrlin or + * ctrlout methods can be called again until the transfer completes. + * + * Input Parameters: + * drvr - The USB host driver instance obtained as a parameter from the + * call to the class create() method. + * ep - The IN or OUT endpoint descriptor for the device endpoint on + * which to perform the transfer. + * buffer - A buffer containing the data to be sent (OUT endpoint) or + * received (IN endpoint). buffer must have been allocated using + * DRVR_ALLOC + * buflen - The length of the data to be sent or received. + * callback - This function will be called when the transfer completes. + * arg - The arbitrary parameter that will be passed to the callback + * function when the transfer completes. + * + * Returned Value: + * On success, zero (OK) is returned. On a failure, a negated errno value + * is returned indicating the nature of the failure + * + * Assumptions: + * - Called from a single thread so no mutual exclusion is required. + * - Never called from an interrupt handler. + * + ****************************************************************************/ + +#ifdef CONFIG_USBHOST_ASYNCH +static int stm32_asynch(struct usbhost_driver_s *drvr, usbhost_ep_t ep, + uint8_t *buffer, size_t buflen, + usbhost_asynch_t callback, void *arg) +{ + struct stm32_usbhost_s *priv = (struct stm32_usbhost_s *)drvr; + unsigned int chidx = (unsigned int)ep; + int ret; + + uinfo("chidx: %d buflen: %d\n", (unsigned int)ep, buflen); + + DEBUGASSERT(priv && buffer && chidx < STM32_MAX_TX_FIFOS && buflen > 0); + + /* We must have exclusive access to the USB host hardware and structures */ + + ret = nxmutex_lock(&priv->lock); + if (ret < 0) + { + return ret; + } + + /* Handle IN and OUT transfer slightly differently */ + + if (priv->chan[chidx].in) + { + ret = stm32_in_asynch(priv, chidx, buffer, buflen, callback, arg); + } + else + { + ret = stm32_out_asynch(priv, chidx, buffer, buflen, callback, arg); + } + + nxmutex_unlock(&priv->lock); + return ret; +} +#endif /* CONFIG_USBHOST_ASYNCH */ + +/**************************************************************************** + * Name: stm32_cancel + * + * Description: + * Cancel a pending transfer on an endpoint. Cancelled synchronous or + * asynchronous transfer will complete normally with the error -ESHUTDOWN. + * + * Input Parameters: + * drvr - The USB host driver instance obtained as a parameter from the + * call to the class create() method. + * ep - The IN or OUT endpoint descriptor for the device endpoint on + * which an asynchronous transfer should be transferred. + * + * Returned Value: + * On success, zero (OK) is returned. On a failure, a negated errno value + * is returned indicating the nature of the failure + * + ****************************************************************************/ + +static int stm32_cancel(struct usbhost_driver_s *drvr, usbhost_ep_t ep) +{ + struct stm32_usbhost_s *priv = (struct stm32_usbhost_s *)drvr; + struct stm32_chan_s *chan; + unsigned int chidx = (unsigned int)ep; + irqstate_t flags; + + uinfo("chidx: %u\n", chidx); + + DEBUGASSERT(priv && chidx < STM32_MAX_TX_FIFOS); + chan = &priv->chan[chidx]; + + /* We need to disable interrupts to avoid race conditions with the + * asynchronous completion of the transfer being cancelled. + */ + + flags = enter_critical_section(); + + /* Halt the channel */ + + stm32_chan_halt(priv, chidx, CHREASON_CANCELLED); + chan->result = -ESHUTDOWN; + + /* Is there a thread waiting for this transfer to complete? */ + + if (chan->waiter) + { +#ifdef CONFIG_USBHOST_ASYNCH + /* Yes.. there should not also be a callback scheduled */ + + DEBUGASSERT(chan->callback == NULL); +#endif + + /* Wake'em up! */ + + nxsem_post(&chan->waitsem); + chan->waiter = false; + } + +#ifdef CONFIG_USBHOST_ASYNCH + /* No.. is an asynchronous callback expected when the transfer + * completes? + */ + + else if (chan->callback) + { + usbhost_asynch_t callback; + void *arg; + + /* Extract the callback information */ + + callback = chan->callback; + arg = chan->arg; + + chan->callback = NULL; + chan->arg = NULL; + chan->xfrd = 0; + + /* Then perform the callback */ + + callback(arg, -ESHUTDOWN); + } +#endif + + leave_critical_section(flags); + return OK; +} + +/**************************************************************************** + * Name: stm32_connect + * + * Description: + * New connections may be detected by an attached hub. This method is the + * mechanism that is used by the hub class to introduce a new connection + * and port description to the system. + * + * Input Parameters: + * drvr - The USB host driver instance obtained as a parameter from the + * call to the class create() method. + * hport - The descriptor of the hub port that detected the connection + * related event + * connected - True: device connected; false: device disconnected + * + * Returned Value: + * On success, zero (OK) is returned. On a failure, a negated errno value + * is returned indicating the nature of the failure + * + ****************************************************************************/ + +#ifdef CONFIG_USBHOST_HUB +static int stm32_connect(struct usbhost_driver_s *drvr, + struct usbhost_hubport_s *hport, + bool connected) +{ + struct stm32_usbhost_s *priv = (struct stm32_usbhost_s *)drvr; + irqstate_t flags; + + DEBUGASSERT(priv != NULL && hport != NULL); + + /* Set the connected/disconnected flag */ + + hport->connected = connected; + uinfo("Hub port %d connected: %s\n", + hport->port, connected ? "YES" : "NO"); + + /* Report the connection event */ + + flags = enter_critical_section(); + priv->hport = hport; + if (priv->pscwait) + { + priv->pscwait = false; + nxsem_post(&priv->pscsem); + } + + leave_critical_section(flags); + return OK; +} +#endif + +/**************************************************************************** + * Name: stm32_disconnect + * + * Description: + * Called by the class when an error occurs and driver has been + * disconnected. The USB host driver should discard the handle to the + * class instance (it is stale) and not attempt any further interaction + * with the class driver instance (until a new instance is received from + * the create() method). The driver should not call the class' + * disconnected() method. + * + * Input Parameters: + * drvr - The USB host driver instance obtained as a parameter from the + * call to the class create() method. + * hport - The port from which the device is being disconnected. Might be + * a port on a hub. + * + * Returned Value: + * None + * + * Assumptions: + * - Only a single class bound to a single device is supported. + * - Never called from an interrupt handler. + * + ****************************************************************************/ + +static void stm32_disconnect(struct usbhost_driver_s *drvr, + struct usbhost_hubport_s *hport) +{ + DEBUGASSERT(hport != NULL); + hport->devclass = NULL; +} + +/**************************************************************************** + * Name: stm32_portreset + * + * Description: + * Reset the USB host port. + * + * NOTE: "Before starting to drive a USB reset, the application waits for + * the OTG interrupt triggered by the debounce done bit (DBCDNE bit in + * OTG_FS_GOTGINT), which indicates that the bus is stable again after + * the electrical debounce caused by the attachment of a pull-up resistor + * on DP (FS) or DM (LS). + * + * Input Parameters: + * priv -- USB host driver private data structure. + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void stm32_portreset(struct stm32_usbhost_s *priv) +{ + uint32_t regval; + + regval = stm32_getreg(STM32_OTGFS_HPRT); + regval &= ~(OTGFS_HPRT_PENA | OTGFS_HPRT_PCDET | OTGFS_HPRT_PENCHNG | + OTGFS_HPRT_POCCHNG); + regval |= OTGFS_HPRT_PRST; + stm32_putreg(STM32_OTGFS_HPRT, regval); + + up_mdelay(20); + + regval &= ~OTGFS_HPRT_PRST; + stm32_putreg(STM32_OTGFS_HPRT, regval); + + up_mdelay(20); +} + +/**************************************************************************** + * Name: stm32_flush_txfifos + * + * Description: + * Flush the selected Tx FIFO. + * + * Input Parameters: + * txfnum -- USB host driver private data structure. + * + * Returned Value: + * None. + * + ****************************************************************************/ + +static void stm32_flush_txfifos(uint32_t txfnum) +{ + uint32_t regval; + uint32_t timeout; + + /* Initiate the TX FIFO flush operation */ + + regval = OTGFS_GRSTCTL_TXFFLSH | txfnum; + stm32_putreg(STM32_OTGFS_GRSTCTL, regval); + + /* Wait for the FLUSH to complete */ + + for (timeout = 0; timeout < STM32_FLUSH_DELAY; timeout++) + { + regval = stm32_getreg(STM32_OTGFS_GRSTCTL); + if ((regval & OTGFS_GRSTCTL_TXFFLSH) == 0) + { + break; + } + } + + /* Wait for 3 PHY Clocks */ + + up_udelay(3); +} + +/**************************************************************************** + * Name: stm32_flush_rxfifo + * + * Description: + * Flush the Rx FIFO. + * + * Input Parameters: + * priv -- USB host driver private data structure. + * + * Returned Value: + * None. + * + ****************************************************************************/ + +static void stm32_flush_rxfifo(void) +{ + uint32_t regval; + uint32_t timeout; + + /* Initiate the RX FIFO flush operation */ + + stm32_putreg(STM32_OTGFS_GRSTCTL, OTGFS_GRSTCTL_RXFFLSH); + + /* Wait for the FLUSH to complete */ + + for (timeout = 0; timeout < STM32_FLUSH_DELAY; timeout++) + { + regval = stm32_getreg(STM32_OTGFS_GRSTCTL); + if ((regval & OTGFS_GRSTCTL_RXFFLSH) == 0) + { + break; + } + } + + /* Wait for 3 PHY Clocks */ + + up_udelay(3); +} + +/**************************************************************************** + * Name: stm32_vbusdrive + * + * Description: + * Drive the Vbus +5V. + * + * Input Parameters: + * priv - USB host driver private data structure. + * state - True: Drive, False: Don't drive + * + * Returned Value: + * None. + * + ****************************************************************************/ + +static void stm32_vbusdrive(struct stm32_usbhost_s *priv, bool state) +{ + uint32_t regval; + +#ifdef CONFIG_STM32_OTGFS_VBUS_CONTROL + /* Enable/disable the external charge pump */ + + stm32_usbhost_vbusdrive(0, state); +#endif + + /* Turn on the Host port power. */ + + regval = stm32_getreg(STM32_OTGFS_HPRT); + regval &= ~(OTGFS_HPRT_PENA | OTGFS_HPRT_PCDET | OTGFS_HPRT_PENCHNG | + OTGFS_HPRT_POCCHNG); + + if (((regval & OTGFS_HPRT_PPWR) == 0) && state) + { + regval |= OTGFS_HPRT_PPWR; + stm32_putreg(STM32_OTGFS_HPRT, regval); + } + + if (((regval & OTGFS_HPRT_PPWR) != 0) && !state) + { + regval &= ~OTGFS_HPRT_PPWR; + stm32_putreg(STM32_OTGFS_HPRT, regval); + } + + up_mdelay(200); +} + +/**************************************************************************** + * Name: stm32_host_initialize + * + * Description: + * Initialize/re-initialize hardware for host mode operation. At present, + * this function is called only from stm32_hw_initialize(). But if OTG + * mode were supported, this function would also be called to switch + * between host and device modes on a connector ID change interrupt. + * + * Input Parameters: + * priv -- USB host driver private data structure. + * + * Returned Value: + * None. + * + ****************************************************************************/ + +static void stm32_host_initialize(struct stm32_usbhost_s *priv) +{ + uint32_t regval; + uint32_t offset; + int i; + + /* Restart the PHY Clock */ + + stm32_putreg(STM32_OTGFS_PCGCCTL, 0); + + /* Initialize Host Configuration (HCFG) register */ + + regval = stm32_getreg(STM32_OTGFS_HCFG); + regval &= ~OTGFS_HCFG_FSLSPCS_MASK; + regval |= OTGFS_HCFG_FSLSPCS_FS48MHz; + stm32_putreg(STM32_OTGFS_HCFG, regval); + + /* Reset the host port */ + + stm32_portreset(priv); + + /* Clear the FS-/LS-only support bit in the HCFG register */ + + regval = stm32_getreg(STM32_OTGFS_HCFG); + regval &= ~OTGFS_HCFG_FSLSS; + stm32_putreg(STM32_OTGFS_HCFG, regval); + + /* Carve up FIFO memory for the Rx FIFO and the periodic + * and non-periodic Tx FIFOs + */ + + /* Configure Rx FIFO size (GRXFSIZ) */ + + stm32_putreg(STM32_OTGFS_GRXFSIZ, CONFIG_STM32_OTGFS_RXFIFO_SIZE); + offset = CONFIG_STM32_OTGFS_RXFIFO_SIZE; + + /* Setup the host non-periodic Tx FIFO size (HNPTXFSIZ) */ + + regval = (offset | + (CONFIG_STM32_OTGFS_NPTXFIFO_SIZE << + OTGFS_HNPTXFSIZ_NPTXFD_SHIFT)); + stm32_putreg(STM32_OTGFS_HNPTXFSIZ, regval); + offset += CONFIG_STM32_OTGFS_NPTXFIFO_SIZE; + + /* Set up the host periodic Tx fifo size register (HPTXFSIZ) */ + + regval = (offset | + (CONFIG_STM32_OTGFS_PTXFIFO_SIZE << + OTGFS_HPTXFSIZ_PTXFD_SHIFT)); + stm32_putreg(STM32_OTGFS_HPTXFSIZ, regval); + + /* If OTG were supported, we should need to clear HNP enable bit in the + * USB_OTG control register about here. + */ + + /* Flush all FIFOs */ + + stm32_flush_txfifos(OTGFS_GRSTCTL_TXFNUM_HALL); + stm32_flush_rxfifo(); + + /* Clear all pending HC Interrupts */ + + for (i = 0; i < STM32_NHOST_CHANNELS; i++) + { + stm32_putreg(STM32_OTGFS_HCINT(i), 0xffffffff); + stm32_putreg(STM32_OTGFS_HCINTMSK(i), 0); + } + + /* Drive Vbus +5V (the smoke test). Should be done elsewhere in OTG + * mode. + */ + + stm32_vbusdrive(priv, true); + + /* Enable host interrupts */ + + stm32_hostinit_enable(); +} + +/**************************************************************************** + * Name: stm32_sw_initialize + * + * Description: + * One-time setup of the host driver state structure. + * + * Input Parameters: + * priv -- USB host driver private data structure. + * + * Returned Value: + * None. + * + ****************************************************************************/ + +static inline void stm32_sw_initialize(struct stm32_usbhost_s *priv) +{ + struct usbhost_driver_s *drvr; + struct usbhost_hubport_s *hport; + int i; + + /* Initialize the device operations */ + + drvr = &priv->drvr; + drvr->ep0configure = stm32_ep0configure; + drvr->epalloc = stm32_epalloc; + drvr->epfree = stm32_epfree; + drvr->alloc = stm32_alloc; + drvr->free = stm32_free; + drvr->ioalloc = stm32_ioalloc; + drvr->iofree = stm32_iofree; + drvr->ctrlin = stm32_ctrlin; + drvr->ctrlout = stm32_ctrlout; + drvr->transfer = stm32_transfer; +#ifdef CONFIG_USBHOST_ASYNCH + drvr->asynch = stm32_asynch; +#endif + drvr->cancel = stm32_cancel; +#ifdef CONFIG_USBHOST_HUB + drvr->connect = stm32_connect; +#endif + drvr->disconnect = stm32_disconnect; + + /* Initialize the public port representation */ + + hport = &priv->rhport.hport; + hport->drvr = drvr; +#ifdef CONFIG_USBHOST_HUB + hport->parent = NULL; +#endif + hport->ep0 = (usbhost_ep_t)&priv->ep0; + hport->speed = USB_SPEED_FULL; + + /* Initialize function address generation logic */ + + usbhost_devaddr_initialize(&priv->devgen); + priv->rhport.pdevgen = &priv->devgen; + + /* Initialize the driver state data */ + + priv->smstate = SMSTATE_DETACHED; + priv->connected = false; + priv->change = false; + + /* Put all of the channels back in their initial, allocated state */ + + memset(priv->chan, 0, STM32_MAX_TX_FIFOS * sizeof(struct stm32_chan_s)); + + /* Initialize each channel */ + + for (i = 0; i < STM32_MAX_TX_FIFOS; i++) + { + struct stm32_chan_s *chan = &priv->chan[i]; + + chan->chidx = i; + nxsem_init(&chan->waitsem, 0, 0); + } +} + +/**************************************************************************** + * Name: stm32_hw_initialize + * + * Description: + * One-time setup of the host controller hardware for normal operations. + * + * Input Parameters: + * priv -- USB host driver private data structure. + * + * Returned Value: + * Zero on success; a negated errno value on failure. + * + ****************************************************************************/ + +static inline int stm32_hw_initialize(struct stm32_usbhost_s *priv) +{ + uint32_t regval; + unsigned long timeout; + + /* Set the PHYSEL bit in the GUSBCFG register to select the OTG FS serial + * transceiver: "This bit is always 1 with write-only access" + */ + + regval = stm32_getreg(STM32_OTGFS_GUSBCFG); + regval |= OTGFS_GUSBCFG_PHYSEL; + stm32_putreg(STM32_OTGFS_GUSBCFG, regval); + + /* Reset after a PHY select and set Host mode. First, wait for AHB master + * IDLE state. + */ + + for (timeout = 0; timeout < STM32_READY_DELAY; timeout++) + { + up_udelay(3); + regval = stm32_getreg(STM32_OTGFS_GRSTCTL); + if ((regval & OTGFS_GRSTCTL_AHBIDL) != 0) + { + break; + } + } + + /* Then perform the core soft reset. */ + + stm32_putreg(STM32_OTGFS_GRSTCTL, OTGFS_GRSTCTL_CSRST); + for (timeout = 0; timeout < STM32_READY_DELAY; timeout++) + { + regval = stm32_getreg(STM32_OTGFS_GRSTCTL); + if ((regval & OTGFS_GRSTCTL_CSRST) == 0) + { + break; + } + } + + /* Wait for 3 PHY Clocks */ + + up_udelay(3); + + /* Deactivate the power down */ + + regval = OTGFS_GCCFG_PWRDWN | OTGFS_GCCFG_VBUSASEN | + OTGFS_GCCFG_VBUSBSEN; +#if !defined(CONFIG_USBDEV_VBUSSENSING) && !defined(CONFIG_STM32_OTGFS_VBUS_CONTROL) + regval |= OTGFS_GCCFG_NOVBUSSENS; +#endif +#ifdef CONFIG_STM32_OTGFS_SOFOUTPUT + regval |= OTGFS_GCCFG_SOFOUTEN; +#endif + stm32_putreg(STM32_OTGFS_GCCFG, regval); + up_mdelay(20); + + /* Initialize OTG features: In order to support OTP, the HNPCAP and SRPCAP + * bits would need to be set in the GUSBCFG register about here. + */ + + /* Force Host Mode */ + + regval = stm32_getreg(STM32_OTGFS_GUSBCFG); + regval &= ~OTGFS_GUSBCFG_FDMOD; + regval |= OTGFS_GUSBCFG_FHMOD; + stm32_putreg(STM32_OTGFS_GUSBCFG, regval); + up_mdelay(50); + + /* Initialize host mode and return success */ + + stm32_host_initialize(priv); + return OK; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_otgfshost_initialize + * + * Description: + * Initialize USB host device controller hardware. + * + * Input Parameters: + * controller -- If the device supports more than USB host controller, then + * this identifies which controller is being initialized. Normally, this + * is just zero. + * + * Returned Value: + * And instance of the USB host interface. The controlling task should + * use this interface to (1) call the wait() method to wait for a device + * to be connected, and (2) call the enumerate() method to bind the device + * to a class driver. + * + * Assumptions: + * - This function should called in the initialization sequence in order + * to initialize the USB device functionality. + * - Class drivers should be initialized prior to calling this function. + * Otherwise, there is a race condition if the device is already connected. + * + ****************************************************************************/ + +struct usbhost_connection_s *stm32_otgfshost_initialize(int controller) +{ + /* At present, there is only support for a single OTG FS host. Hence it is + * pre-allocated as g_usbhost. However, in most code, the private data + * structure will be referenced using the 'priv' pointer (rather than the + * global data) in order to simplify any future support for multiple + * devices. + */ + + struct stm32_usbhost_s *priv = &g_usbhost; + + /* Sanity checks */ + + DEBUGASSERT(controller == 0); + + /* Make sure that interrupts from the OTG FS core are disabled */ + + stm32_gint_disable(); + + /* Reset the state of the host driver */ + + stm32_sw_initialize(priv); + + /* Alternate function pin configuration. Here we assume that: + * + * 1. GPIOA, SYSCFG, and OTG FS peripheral clocking have already been\ + * enabled as part of the boot sequence. + * 2. Board-specific logic has already enabled other board specific GPIOs + * for things like soft pull-up, VBUS sensing, power controls, and over- + * current detection. + */ + + /* Configure OTG FS alternate function pins for DM, DP, ID, and SOF. + * + * PIN* SIGNAL DIRECTION + * ---- ----------- ---------- + * PA8 OTG_FS_SOF SOF clock output + * PA9 OTG_FS_VBUS VBUS input for device, Driven by external regulator by + * host (not an alternate function) + * PA10 OTG_FS_ID OTG ID pin (only needed in Dual mode) + * PA11 OTG_FS_DM D- I/O + * PA12 OTG_FS_DP D+ I/O + * + * *Pins may vary from device-to-device. + */ + + stm32_configgpio(GPIO_OTGFS_DM); + stm32_configgpio(GPIO_OTGFS_DP); +#ifdef CONFIG_USBDEV + stm32_configgpio(GPIO_OTGFS_ID); /* Only needed for OTG */ +#endif + + /* SOF output pin configuration is configurable */ + +#ifdef CONFIG_STM32_OTGFS_SOFOUTPUT + stm32_configgpio(GPIO_OTGFS_SOF); +#endif + + /* Initialize the USB OTG FS core */ + + stm32_hw_initialize(priv); + + /* Attach USB host controller interrupt handler */ + + if (irq_attach(STM32_IRQ_OTGFS, stm32_gint_isr, NULL) != 0) + { + usbhost_trace1(OTGFS_TRACE1_IRQATTACH, 0); + return NULL; + } + + /* Enable USB OTG FS global interrupts */ + + stm32_gint_enable(); + + /* Enable interrupts at the interrupt controller */ + + up_enable_irq(STM32_IRQ_OTGFS); + return &g_usbconn; +} + +#endif /* CONFIG_STM32_USBHOST && CONFIG_STM32_OTGFS */ diff --git a/arch/arm/src/common/stm32/stm32_otghs.h b/arch/arm/src/common/stm32/stm32_otghs.h new file mode 100644 index 0000000000000..c64843045937e --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_otghs.h @@ -0,0 +1,113 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_otghs.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_OTGHS_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_OTGHS_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include + +#include "hardware/stm32_otghs.h" + +#if defined(CONFIG_STM32_OTGHS) + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Number of endpoints */ + +#define STM32_NENDPOINTS (4) /* ep0-3 x 2 for IN and OUT */ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Name: stm32_otgfshost_initialize + * + * Description: + * Initialize USB host device controller hardware. + * + * Input Parameters: + * controller -- If the device supports more than USB host controller, + * then this identifies which controller is being initializeed. + * Normally, this is just zero. + * + * Returned Value: + * And instance of the USB host interface. The controlling task should + * use this interface to (1) call the wait() method to wait for a device + * to be connected, and (2) call the enumerate() method to bind the device + * to a class driver. + * + * Assumptions: + * - This function should called in the initialization sequence in order to + * initialize the USB device functionality. + * - Class drivers should be initialized prior to calling this function. + * Otherwise, there is a race condition if the device is already + * connected. + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_USBHOST +struct usbhost_connection_s; +struct usbhost_connection_s *stm32_otghshost_initialize(int controller); +#endif + +/**************************************************************************** + * Name: stm32_usbsuspend + * + * Description: + * Board logic must provide the stm32_usbsuspend logic if the OTG FS + * device driver is used. This function is called whenever the USB enters + * or leaves suspend mode. This is an opportunity for the board logic to + * shutdown clocks, power, etc. while the USB is suspended. + * + ****************************************************************************/ + +void stm32_usbsuspend(struct usbdev_s *dev, bool resume); + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* CONFIG_STM32_OTGFS */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_OTGHS_H */ diff --git a/arch/arm/src/common/stm32/stm32_otghsdev_m3m4_v1.c b/arch/arm/src/common/stm32/stm32_otghsdev_m3m4_v1.c new file mode 100644 index 0000000000000..4a0e61a213236 --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_otghsdev_m3m4_v1.c @@ -0,0 +1,5760 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_otghsdev_m3m4_v1.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32_otghs.h" +#include "stm32_rcc.h" + +#if defined(CONFIG_USBDEV) && (defined(CONFIG_STM32_OTGHS)) + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +#ifndef CONFIG_USBDEV_EP0_MAXSIZE +# define CONFIG_USBDEV_EP0_MAXSIZE 64 +#endif + +#ifndef CONFIG_USBDEV_SETUP_MAXDATASIZE +# define CONFIG_USBDEV_SETUP_MAXDATASIZE CONFIG_USBDEV_EP0_MAXSIZE +#endif + +#ifndef CONFIG_USBDEV_MAXPOWER +# define CONFIG_USBDEV_MAXPOWER 100 /* mA */ +#endif + +#ifndef CONFIG_DEBUG_USB_INFO +# undef CONFIG_STM32_USBDEV_REGDEBUG +#endif + +/* There is 1.25Kb of FIFO memory. The default partitions this memory + * so that there is a TxFIFO allocated for each endpoint and with more + * memory provided for the common RxFIFO. A more knowledge-able + * configuration would not allocate any TxFIFO space to OUT endpoints. + */ + +#ifndef CONFIG_USBDEV_RXFIFO_SIZE +# define CONFIG_USBDEV_RXFIFO_SIZE 512 +#endif + +#ifndef CONFIG_USBDEV_EP0_TXFIFO_SIZE +# define CONFIG_USBDEV_EP0_TXFIFO_SIZE 192 +#endif + +#ifndef CONFIG_USBDEV_EP1_TXFIFO_SIZE +# define CONFIG_USBDEV_EP1_TXFIFO_SIZE 192 +#endif + +#ifndef CONFIG_USBDEV_EP2_TXFIFO_SIZE +# define CONFIG_USBDEV_EP2_TXFIFO_SIZE 192 +#endif + +#ifndef CONFIG_USBDEV_EP3_TXFIFO_SIZE +# define CONFIG_USBDEV_EP3_TXFIFO_SIZE 192 +#endif + +#if (CONFIG_USBDEV_RXFIFO_SIZE + CONFIG_USBDEV_EP0_TXFIFO_SIZE + \ + CONFIG_USBDEV_EP2_TXFIFO_SIZE + CONFIG_USBDEV_EP3_TXFIFO_SIZE) > 1280 +# error "FIFO allocations exceed FIFO memory size" +#endif + +/* The actual FIFO addresses that we use must be aligned to 4-byte + * boundaries; FIFO sizes must be provided in units of 32-bit words. + */ + +#define STM32_RXFIFO_BYTES ((CONFIG_USBDEV_RXFIFO_SIZE + 3) & ~3) +#define STM32_RXFIFO_WORDS ((CONFIG_USBDEV_RXFIFO_SIZE + 3) >> 2) + +#define STM32_EP0_TXFIFO_BYTES ((CONFIG_USBDEV_EP0_TXFIFO_SIZE + 3) & ~3) +#define STM32_EP0_TXFIFO_WORDS ((CONFIG_USBDEV_EP0_TXFIFO_SIZE + 3) >> 2) + +#if STM32_EP0_TXFIFO_WORDS < 16 || STM32_EP0_TXFIFO_WORDS > 256 +# error "CONFIG_USBDEV_EP0_TXFIFO_SIZE is out of range" +#endif + +#define STM32_EP1_TXFIFO_BYTES ((CONFIG_USBDEV_EP1_TXFIFO_SIZE + 3) & ~3) +#define STM32_EP1_TXFIFO_WORDS ((CONFIG_USBDEV_EP1_TXFIFO_SIZE + 3) >> 2) + +#if STM32_EP1_TXFIFO_WORDS < 16 +# error "CONFIG_USBDEV_EP1_TXFIFO_SIZE is out of range" +#endif + +#define STM32_EP2_TXFIFO_BYTES ((CONFIG_USBDEV_EP2_TXFIFO_SIZE + 3) & ~3) +#define STM32_EP2_TXFIFO_WORDS ((CONFIG_USBDEV_EP2_TXFIFO_SIZE + 3) >> 2) + +#if STM32_EP2_TXFIFO_WORDS < 16 +# error "CONFIG_USBDEV_EP2_TXFIFO_SIZE is out of range" +#endif + +#define STM32_EP3_TXFIFO_BYTES ((CONFIG_USBDEV_EP3_TXFIFO_SIZE + 3) & ~3) +#define STM32_EP3_TXFIFO_WORDS ((CONFIG_USBDEV_EP3_TXFIFO_SIZE + 3) >> 2) + +#if STM32_EP3_TXFIFO_WORDS < 16 +# error "CONFIG_USBDEV_EP3_TXFIFO_SIZE is out of range" +#endif + +/* Debug ********************************************************************/ + +/* Trace error codes */ + +#define STM32_TRACEERR_ALLOCFAIL 0x01 +#define STM32_TRACEERR_BADCLEARFEATURE 0x02 +#define STM32_TRACEERR_BADDEVGETSTATUS 0x03 +#define STM32_TRACEERR_BADEPNO 0x04 +#define STM32_TRACEERR_BADEPGETSTATUS 0x05 +#define STM32_TRACEERR_BADGETCONFIG 0x06 +#define STM32_TRACEERR_BADGETSETDESC 0x07 +#define STM32_TRACEERR_BADGETSTATUS 0x08 +#define STM32_TRACEERR_BADSETADDRESS 0x09 +#define STM32_TRACEERR_BADSETCONFIG 0x0a +#define STM32_TRACEERR_BADSETFEATURE 0x0b +#define STM32_TRACEERR_BADTESTMODE 0x0c +#define STM32_TRACEERR_BINDFAILED 0x0d +#define STM32_TRACEERR_DISPATCHSTALL 0x0e +#define STM32_TRACEERR_DRIVER 0x0f +#define STM32_TRACEERR_DRIVERREGISTERED 0x10 +#define STM32_TRACEERR_EP0NOSETUP 0x11 +#define STM32_TRACEERR_EP0SETUPSTALLED 0x12 +#define STM32_TRACEERR_EPINNULLPACKET 0x13 +#define STM32_TRACEERR_EPINUNEXPECTED 0x14 +#define STM32_TRACEERR_EPOUTNULLPACKET 0x15 +#define STM32_TRACEERR_EPOUTUNEXPECTED 0x16 +#define STM32_TRACEERR_INVALIDCTRLREQ 0x17 +#define STM32_TRACEERR_INVALIDPARMS 0x18 +#define STM32_TRACEERR_IRQREGISTRATION 0x19 +#define STM32_TRACEERR_NOEP 0x1a +#define STM32_TRACEERR_NOTCONFIGURED 0x1b +#define STM32_TRACEERR_EPOUTQEMPTY 0x1c +#define STM32_TRACEERR_EPINREQEMPTY 0x1d +#define STM32_TRACEERR_NOOUTSETUP 0x1e +#define STM32_TRACEERR_POLLTIMEOUT 0x1f + +/* Trace interrupt codes */ + +#define STM32_TRACEINTID_USB 1 /* USB Interrupt entry/exit */ +#define STM32_TRACEINTID_INTPENDING 2 /* On each pass through the loop */ + +#define STM32_TRACEINTID_EPOUT (10 + 0) /* First level interrupt decode */ +#define STM32_TRACEINTID_EPIN (10 + 1) +#define STM32_TRACEINTID_MISMATCH (10 + 2) +#define STM32_TRACEINTID_WAKEUP (10 + 3) +#define STM32_TRACEINTID_SUSPEND (10 + 4) +#define STM32_TRACEINTID_SOF (10 + 5) +#define STM32_TRACEINTID_RXFIFO (10 + 6) +#define STM32_TRACEINTID_DEVRESET (10 + 7) +#define STM32_TRACEINTID_ENUMDNE (10 + 8) +#define STM32_TRACEINTID_IISOIXFR (10 + 9) +#define STM32_TRACEINTID_IISOOXFR (10 + 10) +#define STM32_TRACEINTID_SRQ (10 + 11) +#define STM32_TRACEINTID_OTG (10 + 12) + +#define STM32_TRACEINTID_EPOUT_XFRC (40 + 0) /* EPOUT second level decode */ +#define STM32_TRACEINTID_EPOUT_EPDISD (40 + 1) +#define STM32_TRACEINTID_EPOUT_SETUP (40 + 2) +#define STM32_TRACEINTID_DISPATCH (40 + 3) + +#define STM32_TRACEINTID_GETSTATUS (50 + 0) /* EPOUT third level decode */ +#define STM32_TRACEINTID_EPGETSTATUS (50 + 1) +#define STM32_TRACEINTID_DEVGETSTATUS (50 + 2) +#define STM32_TRACEINTID_IFGETSTATUS (50 + 3) +#define STM32_TRACEINTID_CLEARFEATURE (50 + 4) +#define STM32_TRACEINTID_SETFEATURE (50 + 5) +#define STM32_TRACEINTID_SETADDRESS (50 + 6) +#define STM32_TRACEINTID_GETSETDESC (50 + 7) +#define STM32_TRACEINTID_GETCONFIG (50 + 8) +#define STM32_TRACEINTID_SETCONFIG (50 + 9) +#define STM32_TRACEINTID_GETSETIF (50 + 10) +#define STM32_TRACEINTID_SYNCHFRAME (50 + 11) + +#define STM32_TRACEINTID_EPIN_XFRC (70 + 0) /* EPIN second level decode */ +#define STM32_TRACEINTID_EPIN_TOC (70 + 1) +#define STM32_TRACEINTID_EPIN_ITTXFE (70 + 2) +#define STM32_TRACEINTID_EPIN_EPDISD (70 + 3) +#define STM32_TRACEINTID_EPIN_TXFE (70 + 4) + +#define STM32_TRACEINTID_EPIN_EMPWAIT (80 + 0) /* EPIN second level decode */ + +#define STM32_TRACEINTID_OUTNAK (90 + 0) /* RXFLVL second level decode */ +#define STM32_TRACEINTID_OUTRECVD (90 + 1) +#define STM32_TRACEINTID_OUTDONE (90 + 2) +#define STM32_TRACEINTID_SETUPDONE (90 + 3) +#define STM32_TRACEINTID_SETUPRECVD (90 + 4) + +/* Endpoints ****************************************************************/ + +/* Odd physical endpoint numbers are IN; even are OUT */ + +#define STM32_EPPHYIN2LOG(epphy) ((uint8_t)(epphy)|USB_DIR_IN) +#define STM32_EPPHYOUT2LOG(epphy) ((uint8_t)(epphy)|USB_DIR_OUT) + +/* Endpoint 0 */ + +#define EP0 (0) + +/* The set of all endpoints available to the class implementation (1-3) */ + +#define STM32_EP_AVAILABLE (0x0e) /* All available endpoints */ + +/* Maximum packet sizes for full speed endpoints */ + +#define STM32_MAXPACKET (64) /* Max packet size (1-64) */ + +/* Delays *******************************************************************/ + +#define STM32_READY_DELAY 200000 +#define STM32_FLUSH_DELAY 200000 + +/* Request queue operations *************************************************/ + +#define stm32_rqempty(ep) ((ep)->head == NULL) +#define stm32_rqpeek(ep) ((ep)->head) + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/* Overall device state */ + +enum stm32_devstate_e +{ + DEVSTATE_DEFAULT = 0, /* Power-up, unconfigured state. This state simply + * means that the device is not yet been given an + * address. + * SET: At initialization, uninitialization, + * reset, and whenever the device address + * is set to zero + * TESTED: Never + */ + DEVSTATE_ADDRESSED, /* Device address has been assigned, not no + * configuration has yet been selected. + * SET: When either a non-zero device address + * is first assigned or when the device + * is unconfigured (with configuration == 0) + * TESTED: never + */ + DEVSTATE_CONFIGURED, /* Address assigned and configured: + * SET: When the device has been addressed and + * an non-zero configuration has been selected. + * TESTED: In many places to assure that the USB device + * has been properly configured by the host. + */ +}; + +/* Endpoint 0 states */ + +enum stm32_ep0state_e +{ + EP0STATE_IDLE = 0, /* Idle State, leave on receiving a SETUP packet or + * epsubmit: + * SET: In stm32_epin() and stm32_epout() when + * we revert from request processing to + * SETUP processing. + * TESTED: Never + */ + EP0STATE_SETUP_OUT, /* OUT SETUP packet received. Waiting for the DATA + * OUT phase of SETUP Packet to complete before + * processing a SETUP command (without a USB request): + * SET: Set in stm32_rxinterrupt() when SETUP OUT + * packet is received. + * TESTED: In stm32_ep0out_receive() + */ + EP0STATE_SETUP_READY, /* IN SETUP packet received -OR- OUT SETUP packet and + * accompanying data have been received. Processing + * of SETUP command will happen soon. + * SET: (1) stm32_ep0out_receive() when the OUT + * SETUP data phase completes, or (2) + * stm32_rxinterrupt() when an IN SETUP is + * packet received. + * TESTED: Tested in stm32_epout_interrupt() when + * SETUP phase is done to see if the SETUP + * command is ready to be processed. Also + * tested in stm32_ep0out_setup() just to + * double-check that we have a SETUP request + * and any accompanying data. + */ + EP0STATE_SETUP_PROCESS, /* SETUP Packet is being processed by stm32_ep0out_setup(): + * SET: When SETUP packet received in EP0 OUT + * TESTED: Never + */ + EP0STATE_SETUPRESPONSE, /* Short SETUP response write (without a USB request): + * SET: When SETUP response is sent by + * stm32_ep0in_setupresponse() + * TESTED: Never + */ + EP0STATE_DATA_IN, /* Waiting for data out stage (with a USB request): + * SET: In stm32_epin_request() when a write + * request is processed on EP0. + * TESTED: In stm32_epin() to see if we should + * revert to SETUP processing. + */ + EP0STATE_DATA_OUT /* Waiting for data in phase to complete ( with a + * USB request) + * SET: In stm32_epout_request() when a read + * request is processed on EP0. + * TESTED: In stm32_epout() to see if we should + * revert to SETUP processing + */ +}; + +/* Parsed control request */ + +struct stm32_ctrlreq_s +{ + uint8_t type; + uint8_t req; + uint16_t value; + uint16_t index; + uint16_t len; +}; + +/* A container for a request so that the request may be retained in a list */ + +struct stm32_req_s +{ + struct usbdev_req_s req; /* Standard USB request */ + struct stm32_req_s *flink; /* Supports a singly linked list */ +}; + +/* This is the internal representation of an endpoint */ + +struct stm32_ep_s +{ + /* Common endpoint fields. This must be the first thing defined in the + * structure so that it is possible to simply cast from struct usbdev_ep_s + * to struct stm32_ep_s. + */ + + struct usbdev_ep_s ep; /* Standard endpoint structure */ + + /* STM32-specific fields */ + + struct stm32_usbdev_s *dev; /* Reference to private driver data */ + struct stm32_req_s *head; /* Request list for this endpoint */ + struct stm32_req_s *tail; + uint8_t epphy; /* Physical EP address */ + uint8_t eptype:2; /* Endpoint type */ + uint8_t active:1; /* 1: A request is being processed */ + uint8_t stalled:1; /* 1: Endpoint is stalled */ + uint8_t isin:1; /* 1: IN Endpoint */ + uint8_t odd:1; /* 1: Odd frame */ + uint8_t zlp:1; /* 1: Transmit a zero-length-packet (IN EPs only) */ +}; + +/* This structure retains the state of the USB device controller */ + +struct stm32_usbdev_s +{ + /* Common device fields. This must be the first thing defined in the + * structure so that it is possible to simply cast from struct usbdev_s + * to struct stm32_usbdev_s. + */ + + struct usbdev_s usbdev; + + /* The bound device class driver */ + + struct usbdevclass_driver_s *driver; + + /* STM32-specific fields */ + + uint8_t stalled:1; /* 1: Protocol stalled */ + uint8_t selfpowered:1; /* 1: Device is self powered */ + uint8_t addressed:1; /* 1: Peripheral address has been set */ + uint8_t configured:1; /* 1: Class driver has been configured */ + uint8_t wakeup:1; /* 1: Device remote wake-up */ + uint8_t dotest:1; /* 1: Test mode selected */ + + uint8_t devstate:4; /* See enum stm32_devstate_e */ + uint8_t ep0state:4; /* See enum stm32_ep0state_e */ + uint8_t testmode:4; /* Selected test mode */ + uint8_t epavail[2]; /* Bitset of available OUT/IN endpoints */ + + /* E0 SETUP data buffering. + * + * ctrlreq: + * The 8-byte SETUP request is received on the EP0 OUT endpoint and is + * saved. + * + * ep0data + * For OUT SETUP requests, the SETUP data phase must also complete before + * the SETUP command can be processed. The pack receipt logic will save + * the accompanying EP0 IN data in ep0data[] before the SETUP command is + * processed. + * + * For IN SETUP requests, the DATA phase will occur AFTER the SETUP + * control request is processed. In that case, ep0data[] may be used as + * the response buffer. + * + * ep0datlen + * Length of OUT DATA received in ep0data[] (Not used with OUT data) + */ + + struct usb_ctrlreq_s ctrlreq; + uint8_t ep0data[CONFIG_USBDEV_SETUP_MAXDATASIZE]; + uint16_t ep0datlen; + + /* The endpoint lists */ + + struct stm32_ep_s epin[STM32_NENDPOINTS]; + struct stm32_ep_s epout[STM32_NENDPOINTS]; +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/* Register operations ******************************************************/ + +#ifdef CONFIG_STM32_USBDEV_REGDEBUG +static uint32_t stm32_getreg(uint32_t addr); +static void stm32_putreg(uint32_t val, uint32_t addr); +#else +# define stm32_getreg(addr) getreg32(addr) +# define stm32_putreg(val,addr) putreg32(val,addr) +#endif + +/* Request queue operations *************************************************/ + +static struct stm32_req_s *stm32_req_remfirst( + struct stm32_ep_s *privep); +static bool stm32_req_addlast(struct stm32_ep_s *privep, + struct stm32_req_s *req); + +/* Low level data transfers and request operations **************************/ + +/* Special endpoint 0 data transfer logic */ + +static void stm32_ep0in_setupresponse(struct stm32_usbdev_s *priv, + uint8_t *data, uint32_t nbytes); +static inline void stm32_ep0in_transmitzlp(struct stm32_usbdev_s *priv); +static void stm32_ep0in_activate(void); + +static void stm32_ep0out_ctrlsetup(struct stm32_usbdev_s *priv); + +/* IN request and TxFIFO handling */ + +static void stm32_txfifo_write(struct stm32_ep_s *privep, + uint8_t *buf, int nbytes); +static void stm32_epin_transfer(struct stm32_ep_s *privep, + uint8_t *buf, int nbytes); +static void stm32_epin_request(struct stm32_usbdev_s *priv, + struct stm32_ep_s *privep); + +/* OUT request and RxFIFO handling */ + +static void stm32_rxfifo_read(struct stm32_ep_s *privep, + uint8_t *dest, uint16_t len); +static void stm32_rxfifo_discard(struct stm32_ep_s *privep, + int len); +static void stm32_epout_complete(struct stm32_usbdev_s *priv, + struct stm32_ep_s *privep); +static inline void stm32_ep0out_receive(struct stm32_ep_s *privep, + int bcnt); +static inline void stm32_epout_receive(struct stm32_ep_s *privep, + int bcnt); +static void stm32_epout_request(struct stm32_usbdev_s *priv, + struct stm32_ep_s *privep); + +/* General request handling */ + +static void stm32_ep_flush(struct stm32_ep_s *privep); +static void stm32_req_complete(struct stm32_ep_s *privep, + int16_t result); +static void stm32_req_cancel(struct stm32_ep_s *privep, + int16_t status); + +/* Interrupt handling *******************************************************/ + +static struct stm32_ep_s *stm32_ep_findbyaddr( + struct stm32_usbdev_s *priv, uint16_t eplog); +static int stm32_req_dispatch(struct stm32_usbdev_s *priv, + const struct usb_ctrlreq_s *ctrl); +static void stm32_usbreset(struct stm32_usbdev_s *priv); + +/* Second level OUT endpoint interrupt processing */ + +static inline void stm32_ep0out_testmode(struct stm32_usbdev_s *priv, + uint16_t index); +static inline void stm32_ep0out_stdrequest(struct stm32_usbdev_s *priv, + struct stm32_ctrlreq_s *ctrlreq); +static inline void stm32_ep0out_setup(struct stm32_usbdev_s *priv); +static inline void stm32_epout(struct stm32_usbdev_s *priv, + uint8_t epno); +static inline void stm32_epout_interrupt(struct stm32_usbdev_s *priv); + +/* Second level IN endpoint interrupt processing */ + +static inline void stm32_epin_runtestmode(struct stm32_usbdev_s *priv); +static inline void stm32_epin(struct stm32_usbdev_s *priv, uint8_t epno); +static inline void stm32_epin_txfifoempty(struct stm32_usbdev_s *priv, + int epno); +static inline void stm32_epin_interrupt(struct stm32_usbdev_s *priv); + +/* Other second level interrupt processing */ + +static inline void stm32_resumeinterrupt(struct stm32_usbdev_s *priv); +static inline void stm32_suspendinterrupt(struct stm32_usbdev_s *priv); +static inline void stm32_rxinterrupt(struct stm32_usbdev_s *priv); +static inline void stm32_enuminterrupt(struct stm32_usbdev_s *priv); +#ifdef CONFIG_USBDEV_ISOCHRONOUS +static inline void stm32_isocininterrupt(struct stm32_usbdev_s *priv); +static inline void stm32_isocoutinterrupt(struct stm32_usbdev_s *priv); +#endif +#ifdef CONFIG_USBDEV_VBUSSENSING +static inline void stm32_sessioninterrupt(struct stm32_usbdev_s *priv); +static inline void stm32_otginterrupt(struct stm32_usbdev_s *priv); +#endif + +/* First level interrupt processing */ + +static int stm32_usbinterrupt(int irq, void *context, + void *arg); + +/* Endpoint operations ******************************************************/ + +/* Global OUT NAK controls */ + +static void stm32_enablegonak(struct stm32_ep_s *privep); +static void stm32_disablegonak(struct stm32_ep_s *privep); + +/* Endpoint configuration */ + +static int stm32_epout_configure(struct stm32_ep_s *privep, + uint8_t eptype, uint16_t maxpacket); +static int stm32_epin_configure(struct stm32_ep_s *privep, + uint8_t eptype, uint16_t maxpacket); +static int stm32_ep_configure(struct usbdev_ep_s *ep, + const struct usb_epdesc_s *desc, bool last); +static void stm32_ep0_configure(struct stm32_usbdev_s *priv); + +/* Endpoint disable */ + +static void stm32_epout_disable(struct stm32_ep_s *privep); +static void stm32_epin_disable(struct stm32_ep_s *privep); +static int stm32_ep_disable(struct usbdev_ep_s *ep); + +/* Endpoint request management */ + +static struct usbdev_req_s *stm32_ep_allocreq( + struct usbdev_ep_s *ep); +static void stm32_ep_freereq(struct usbdev_ep_s *ep, + struct usbdev_req_s *); + +/* Endpoint buffer management */ + +#ifdef CONFIG_USBDEV_DMA +static void *stm32_ep_allocbuffer(struct usbdev_ep_s *ep, + uint16_t bytes); +static void stm32_ep_freebuffer(struct usbdev_ep_s *ep, + void *buf); +#endif + +/* Endpoint request submission */ + +static int stm32_ep_submit(struct usbdev_ep_s *ep, + struct usbdev_req_s *req); + +/* Endpoint request cancellation */ + +static int stm32_ep_cancel(struct usbdev_ep_s *ep, + struct usbdev_req_s *req); + +/* Stall handling */ + +static int stm32_epout_setstall(struct stm32_ep_s *privep); +static int stm32_epin_setstall(struct stm32_ep_s *privep); +static int stm32_ep_setstall(struct stm32_ep_s *privep); +static int stm32_ep_clrstall(struct stm32_ep_s *privep); +static int stm32_ep_stall(struct usbdev_ep_s *ep, bool resume); +static void stm32_ep0_stall(struct stm32_usbdev_s *priv); + +/* Endpoint allocation */ + +static struct usbdev_ep_s *stm32_ep_alloc(struct usbdev_s *dev, + uint8_t epno, bool in, uint8_t eptype); +static void stm32_ep_free(struct usbdev_s *dev, + struct usbdev_ep_s *ep); + +/* USB device controller operations *****************************************/ + +static int stm32_getframe(struct usbdev_s *dev); +static int stm32_wakeup(struct usbdev_s *dev); +static int stm32_selfpowered(struct usbdev_s *dev, bool selfpowered); +static int stm32_pullup(struct usbdev_s *dev, bool enable); +static void stm32_setaddress(struct stm32_usbdev_s *priv, + uint16_t address); +static int stm32_txfifo_flush(uint32_t txfnum); +static int stm32_rxfifo_flush(void); + +/* Initialization ***********************************************************/ + +static void stm32_swinitialize(struct stm32_usbdev_s *priv); +static void stm32_hwinitialize(struct stm32_usbdev_s *priv); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* Since there is only a single USB interface, all status information can be + * be simply retained in a single global instance. + */ + +static struct stm32_usbdev_s g_otghsdev; + +static const struct usbdev_epops_s g_epops = +{ + .configure = stm32_ep_configure, + .disable = stm32_ep_disable, + .allocreq = stm32_ep_allocreq, + .freereq = stm32_ep_freereq, +#ifdef CONFIG_USBDEV_DMA + .allocbuffer = stm32_ep_allocbuffer, + .freebuffer = stm32_ep_freebuffer, +#endif + .submit = stm32_ep_submit, + .cancel = stm32_ep_cancel, + .stall = stm32_ep_stall, +}; + +static const struct usbdev_ops_s g_devops = +{ + .allocep = stm32_ep_alloc, + .freeep = stm32_ep_free, + .getframe = stm32_getframe, + .wakeup = stm32_wakeup, + .selfpowered = stm32_selfpowered, + .pullup = stm32_pullup, +}; + +/* Device error strings that may be enabled for more descriptive USB trace + * output. + */ + +#ifdef CONFIG_USBDEV_TRACE_STRINGS +const struct trace_msg_t g_usb_trace_strings_deverror[] = +{ + TRACE_STR(STM32_TRACEERR_ALLOCFAIL), + TRACE_STR(STM32_TRACEERR_BADCLEARFEATURE), + TRACE_STR(STM32_TRACEERR_BADDEVGETSTATUS), + TRACE_STR(STM32_TRACEERR_BADEPNO), + TRACE_STR(STM32_TRACEERR_BADEPGETSTATUS), + TRACE_STR(STM32_TRACEERR_BADGETCONFIG), + TRACE_STR(STM32_TRACEERR_BADGETSETDESC), + TRACE_STR(STM32_TRACEERR_BADGETSTATUS), + TRACE_STR(STM32_TRACEERR_BADSETADDRESS), + TRACE_STR(STM32_TRACEERR_BADSETCONFIG), + TRACE_STR(STM32_TRACEERR_BADSETFEATURE), + TRACE_STR(STM32_TRACEERR_BADTESTMODE), + TRACE_STR(STM32_TRACEERR_BINDFAILED), + TRACE_STR(STM32_TRACEERR_DISPATCHSTALL), + TRACE_STR(STM32_TRACEERR_DRIVER), + TRACE_STR(STM32_TRACEERR_DRIVERREGISTERED), + TRACE_STR(STM32_TRACEERR_EP0NOSETUP), + TRACE_STR(STM32_TRACEERR_EP0SETUPSTALLED), + TRACE_STR(STM32_TRACEERR_EPINNULLPACKET), + TRACE_STR(STM32_TRACEERR_EPINUNEXPECTED), + TRACE_STR(STM32_TRACEERR_EPOUTNULLPACKET), + TRACE_STR(STM32_TRACEERR_EPOUTUNEXPECTED), + TRACE_STR(STM32_TRACEERR_INVALIDCTRLREQ), + TRACE_STR(STM32_TRACEERR_INVALIDPARMS), + TRACE_STR(STM32_TRACEERR_IRQREGISTRATION), + TRACE_STR(STM32_TRACEERR_NOEP), + TRACE_STR(STM32_TRACEERR_NOTCONFIGURED), + TRACE_STR(STM32_TRACEERR_EPOUTQEMPTY), + TRACE_STR(STM32_TRACEERR_EPINREQEMPTY), + TRACE_STR(STM32_TRACEERR_NOOUTSETUP), + TRACE_STR(STM32_TRACEERR_POLLTIMEOUT), + TRACE_STR_END +}; +#endif + +/* Interrupt event strings that may be enabled for more descriptive USB trace + * output. + */ + +#ifdef CONFIG_USBDEV_TRACE_STRINGS +const struct trace_msg_t g_usb_trace_strings_intdecode[] = +{ + TRACE_STR(STM32_TRACEINTID_USB), + TRACE_STR(STM32_TRACEINTID_INTPENDING), + TRACE_STR(STM32_TRACEINTID_EPOUT), + TRACE_STR(STM32_TRACEINTID_EPIN), + TRACE_STR(STM32_TRACEINTID_MISMATCH), + TRACE_STR(STM32_TRACEINTID_WAKEUP), + TRACE_STR(STM32_TRACEINTID_SUSPEND), + TRACE_STR(STM32_TRACEINTID_SOF), + TRACE_STR(STM32_TRACEINTID_RXFIFO), + TRACE_STR(STM32_TRACEINTID_DEVRESET), + TRACE_STR(STM32_TRACEINTID_ENUMDNE), + TRACE_STR(STM32_TRACEINTID_IISOIXFR), + TRACE_STR(STM32_TRACEINTID_IISOOXFR), + TRACE_STR(STM32_TRACEINTID_SRQ), + TRACE_STR(STM32_TRACEINTID_OTG), + TRACE_STR(STM32_TRACEINTID_EPOUT_XFRC), + TRACE_STR(STM32_TRACEINTID_EPOUT_EPDISD), + TRACE_STR(STM32_TRACEINTID_EPOUT_SETUP), + TRACE_STR(STM32_TRACEINTID_DISPATCH), + TRACE_STR(STM32_TRACEINTID_GETSTATUS), + TRACE_STR(STM32_TRACEINTID_EPGETSTATUS), + TRACE_STR(STM32_TRACEINTID_DEVGETSTATUS), + TRACE_STR(STM32_TRACEINTID_IFGETSTATUS), + TRACE_STR(STM32_TRACEINTID_CLEARFEATURE), + TRACE_STR(STM32_TRACEINTID_SETFEATURE), + TRACE_STR(STM32_TRACEINTID_SETADDRESS), + TRACE_STR(STM32_TRACEINTID_GETSETDESC), + TRACE_STR(STM32_TRACEINTID_GETCONFIG), + TRACE_STR(STM32_TRACEINTID_SETCONFIG), + TRACE_STR(STM32_TRACEINTID_GETSETIF), + TRACE_STR(STM32_TRACEINTID_SYNCHFRAME), + TRACE_STR(STM32_TRACEINTID_EPIN_XFRC), + TRACE_STR(STM32_TRACEINTID_EPIN_TOC), + TRACE_STR(STM32_TRACEINTID_EPIN_ITTXFE), + TRACE_STR(STM32_TRACEINTID_EPIN_EPDISD), + TRACE_STR(STM32_TRACEINTID_EPIN_TXFE), + TRACE_STR(STM32_TRACEINTID_EPIN_EMPWAIT), + TRACE_STR(STM32_TRACEINTID_OUTNAK), + TRACE_STR(STM32_TRACEINTID_OUTRECVD), + TRACE_STR(STM32_TRACEINTID_OUTDONE), + TRACE_STR(STM32_TRACEINTID_SETUPDONE), + TRACE_STR(STM32_TRACEINTID_SETUPRECVD), + TRACE_STR_END +}; +#endif + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_getreg + * + * Description: + * Get the contents of an STM32 register + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_USBDEV_REGDEBUG +static uint32_t stm32_getreg(uint32_t addr) +{ + static uint32_t prevaddr = 0; + static uint32_t preval = 0; + static uint32_t count = 0; + + /* Read the value from the register */ + + uint32_t val = getreg32(addr); + + /* Is this the same value that we read from the same register last time? + * Are we polling the register? If so, suppress some of the output. + */ + + if (addr == prevaddr && val == preval) + { + if (count == 0xffffffff || ++count > 3) + { + if (count == 4) + { + uinfo("...\n"); + } + + return val; + } + } + + /* No this is a new address or value */ + + else + { + /* Did we print "..." for the previous value? */ + + if (count > 3) + { + /* Yes.. then show how many times the value repeated */ + + uinfo("[repeats %d more times]\n", count - 3); + } + + /* Save the new address, value, and count */ + + prevaddr = addr; + preval = val; + count = 1; + } + + /* Show the register value read */ + + uinfo("%08" PRIx32 "->%08" PRIx32 "\n", addr, val); + return val; +} +#endif + +/**************************************************************************** + * Name: stm32_putreg + * + * Description: + * Set the contents of an STM32 register to a value + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_USBDEV_REGDEBUG +static void stm32_putreg(uint32_t val, uint32_t addr) +{ + /* Show the register value being written */ + + uinfo("%08" PRIx32 "<-%08" PRIx32 "\n", addr, val); + + /* Write the value */ + + putreg32(val, addr); +} +#endif + +/**************************************************************************** + * Name: stm32_req_remfirst + * + * Description: + * Remove a request from the head of an endpoint request queue + * + ****************************************************************************/ + +static struct stm32_req_s *stm32_req_remfirst( + struct stm32_ep_s *privep) +{ + struct stm32_req_s *ret = privep->head; + + if (ret) + { + privep->head = ret->flink; + if (!privep->head) + { + privep->tail = NULL; + } + + ret->flink = NULL; + } + + return ret; +} + +/**************************************************************************** + * Name: stm32_req_addlast + * + * Description: + * Add a request to the end of an endpoint request queue + * + ****************************************************************************/ + +static bool stm32_req_addlast(struct stm32_ep_s *privep, + struct stm32_req_s *req) +{ + bool is_empty = !privep->head; + + req->flink = NULL; + if (is_empty) + { + privep->head = req; + privep->tail = req; + } + else + { + privep->tail->flink = req; + privep->tail = req; + } + + return is_empty; +} + +/**************************************************************************** + * Name: stm32_ep0in_setupresponse + * + * Description: + * Schedule a short transfer on Endpoint 0 (IN or OUT) + * + ****************************************************************************/ + +static void stm32_ep0in_setupresponse(struct stm32_usbdev_s *priv, + uint8_t *buf, uint32_t nbytes) +{ + stm32_epin_transfer(&priv->epin[EP0], buf, nbytes); + priv->ep0state = EP0STATE_SETUPRESPONSE; + stm32_ep0out_ctrlsetup(priv); +} + +/**************************************************************************** + * Name: stm32_ep0in_transmitzlp + * + * Description: + * Send a zero length packet (ZLP) on endpoint 0 IN + * + ****************************************************************************/ + +static inline void stm32_ep0in_transmitzlp(struct stm32_usbdev_s *priv) +{ + stm32_ep0in_setupresponse(priv, NULL, 0); +} + +/**************************************************************************** + * Name: stm32_ep0in_activate + * + * Description: + * Activate the endpoint 0 IN endpoint. + * + ****************************************************************************/ + +static void stm32_ep0in_activate(void) +{ + uint32_t regval; + + /* Set the max packet size of the IN EP. */ + + regval = stm32_getreg(STM32_OTGHS_DIEPCTL0); + regval &= ~OTGHS_DIEPCTL0_MPSIZ_MASK; + +#if CONFIG_USBDEV_EP0_MAXSIZE == 8 + regval |= OTGHS_DIEPCTL0_MPSIZ_8; +#elif CONFIG_USBDEV_EP0_MAXSIZE == 16 + regval |= OTGHS_DIEPCTL0_MPSIZ_16; +#elif CONFIG_USBDEV_EP0_MAXSIZE == 32 + regval |= OTGHS_DIEPCTL0_MPSIZ_32; +#elif CONFIG_USBDEV_EP0_MAXSIZE == 64 + regval |= OTGHS_DIEPCTL0_MPSIZ_64; +#else +# error "Unsupported value of CONFIG_USBDEV_EP0_MAXSIZE" +#endif + + stm32_putreg(regval, STM32_OTGHS_DIEPCTL0); + + /* Clear global IN NAK */ + + regval = stm32_getreg(STM32_OTGHS_DCTL); + regval |= OTGHS_DCTL_CGINAK; + stm32_putreg(regval, STM32_OTGHS_DCTL); +} + +/**************************************************************************** + * Name: stm32_ep0out_ctrlsetup + * + * Description: + * Setup to receive a SETUP packet. + * + ****************************************************************************/ + +static void stm32_ep0out_ctrlsetup(struct stm32_usbdev_s *priv) +{ + uint32_t regval; + + /* Setup the hardware to perform the SETUP transfer */ + + regval = (USB_SIZEOF_CTRLREQ * 3 << OTGHS_DOEPTSIZ0_XFRSIZ_SHIFT) | + (OTGHS_DOEPTSIZ0_PKTCNT) | + (3 << OTGHS_DOEPTSIZ0_STUPCNT_SHIFT); + stm32_putreg(regval, STM32_OTGHS_DOEPTSIZ0); + + /* Then clear NAKing and enable the transfer */ + + regval = stm32_getreg(STM32_OTGHS_DOEPCTL0); + regval |= (OTGHS_DOEPCTL0_CNAK | OTGHS_DOEPCTL0_EPENA); + stm32_putreg(regval, STM32_OTGHS_DOEPCTL0); +} + +/**************************************************************************** + * Name: stm32_txfifo_write + * + * Description: + * Send data to the endpoint's TxFIFO. + * + ****************************************************************************/ + +static void stm32_txfifo_write(struct stm32_ep_s *privep, + uint8_t *buf, int nbytes) +{ + uint32_t regaddr; + uint32_t regval; + int nwords; + int i; + + /* Convert the number of bytes to words */ + + nwords = (nbytes + 3) >> 2; + + /* Get the TxFIFO for this endpoint (same as the endpoint number) */ + + regaddr = STM32_OTGHS_DFIFO_DEP(privep->epphy); + + /* Then transfer each word to the TxFIFO */ + + for (i = 0; i < nwords; i++) + { + /* Read four bytes from the source buffer (to avoid unaligned accesses) + * and pack these into one 32-bit word (little endian). + */ + + regval = (uint32_t)*buf++; + regval |= ((uint32_t)*buf++) << 8; + regval |= ((uint32_t)*buf++) << 16; + regval |= ((uint32_t)*buf++) << 24; + + /* Then write the packet data to the TxFIFO */ + + stm32_putreg(regval, regaddr); + } +} + +/**************************************************************************** + * Name: stm32_epin_transfer + * + * Description: + * Start the Tx data transfer + * + ****************************************************************************/ + +static void stm32_epin_transfer(struct stm32_ep_s *privep, + uint8_t *buf, int nbytes) +{ + uint32_t pktcnt; + uint32_t regval; + + /* Read the DIEPSIZx register */ + + regval = stm32_getreg(STM32_OTGHS_DIEPTSIZ(privep->epphy)); + + /* Clear the XFRSIZ, PKTCNT, and MCNT field of the DIEPSIZx register */ + + regval &= ~(OTGHS_DIEPTSIZ_XFRSIZ_MASK | OTGHS_DIEPTSIZ_PKTCNT_MASK | + OTGHS_DIEPTSIZ_MCNT_MASK); + + /* Are we sending a zero length packet (ZLP) */ + + if (nbytes == 0) + { + /* Yes.. + * leave the transfer size at zero and set the packet count to 1 + */ + + pktcnt = 1; + } + else + { + /* No.. Program the transfer size and packet count . First calculate: + * + * xfrsize = The total number of bytes to be sent. + * pktcnt = the number of packets (of maxpacket bytes) required to + * perform the transfer. + */ + + pktcnt = ((uint32_t)nbytes + (privep->ep.maxpacket - 1)) / + privep->ep.maxpacket; + } + + /* Set the XFRSIZ and PKTCNT */ + + regval |= (pktcnt << OTGHS_DIEPTSIZ_PKTCNT_SHIFT); + regval |= ((uint32_t)nbytes << OTGHS_DIEPTSIZ_XFRSIZ_SHIFT); + + /* If this is an isochronous endpoint, then set the multi-count field to + * the PKTCNT as well. + */ + + if (privep->eptype == USB_EP_ATTR_XFER_ISOC) + { + regval |= (pktcnt << OTGHS_DIEPTSIZ_MCNT_SHIFT); + } + + /* Save DIEPSIZx register value */ + + stm32_putreg(regval, STM32_OTGHS_DIEPTSIZ(privep->epphy)); + + /* Read the DIEPCTLx register */ + + regval = stm32_getreg(STM32_OTGHS_DIEPCTL(privep->epphy)); + + /* If this is an isochronous endpoint, then set the even/odd frame bit + * the DIEPCTLx register. + */ + + if (privep->eptype == USB_EP_ATTR_XFER_ISOC) + { + /* Check bit 0 of the frame number of the received SOF and set the + * even/odd frame to match. + */ + + uint32_t status = stm32_getreg(STM32_OTGHS_DSTS); + if ((status & OTGHS_DSTS_SOFFN0) == OTGHS_DSTS_SOFFN_EVEN) + { + regval |= OTGHS_DIEPCTL_SEVNFRM; + } + else + { + regval |= OTGHS_DIEPCTL_SODDFRM; + } + } + + /* EP enable, IN data in FIFO */ + + regval &= ~OTGHS_DIEPCTL_EPDIS; + regval |= (OTGHS_DIEPCTL_CNAK | OTGHS_DIEPCTL_EPENA); + stm32_putreg(regval, STM32_OTGHS_DIEPCTL(privep->epphy)); + + /* Transfer the data to the TxFIFO. At this point, the caller has already + * assured that there is sufficient space in the TxFIFO to hold the + * transfer we can just blindly continue. + */ + + stm32_txfifo_write(privep, buf, nbytes); +} + +/**************************************************************************** + * Name: stm32_epin_request + * + * Description: + * Begin or continue write request processing. + * + ****************************************************************************/ + +static void stm32_epin_request(struct stm32_usbdev_s *priv, + struct stm32_ep_s *privep) +{ + struct stm32_req_s *privreq; + uint32_t regaddr; + uint32_t regval; + uint8_t *buf; + int nbytes; + int nwords; + int bytesleft; + + /* We get here in one of four possible ways. From three interrupting + * events: + * + * 1. From stm32_epin as part of the transfer complete interrupt processing + * This interrupt indicates that the last transfer has completed. + * 2. As part of the ITTXFE interrupt processing. That interrupt indicates + * that an IN token was received when the associated TxFIFO was empty. + * 3. From stm32_epin_txfifoempty as part of the TXFE interrupt processing. + * The TXFE interrupt is only enabled when the TxFIFO is full and the + * software must wait for space to become available in the TxFIFO. + * + * And this function may be called immediately when the write request is + * queue to start up the next transaction. + * + * 4. From stm32_ep_submit when a new write request is received WHILE the + * endpoint is not active (privep->active == false). + */ + + /* Check the request from the head of the endpoint request queue */ + + privreq = stm32_rqpeek(privep); + if (!privreq) + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EPINREQEMPTY), privep->epphy); + + /* There is no TX transfer in progress and no new pending TX + * requests to send. To stop transmitting any data on a particular + * IN endpoint, the application must set the IN NAK bit. To set this + * bit, the following field must be programmed. + */ + + regaddr = STM32_OTGHS_DIEPCTL(privep->epphy); + regval = stm32_getreg(regaddr); + regval |= OTGHS_DIEPCTL_SNAK; + stm32_putreg(regval, regaddr); + + /* The endpoint is no longer active */ + + privep->active = false; + return; + } + + uinfo("EP%d req=%p: len=%zu xfrd=%zu zlp=%d\n", + privep->epphy, privreq, privreq->req.len, + privreq->req.xfrd, privep->zlp); + + /* Check for a special case: If we are just starting a request (xfrd==0) + * and the class driver is trying to send a zero-length packet (len==0). + * Then set the ZLP flag so that the packet will be sent. + */ + + if (privreq->req.len == 0) + { + /* The ZLP flag is set TRUE whenever we want to force the driver to + * send a zero-length-packet on the next pass through the loop (below). + * The flag is cleared whenever a packet is sent in the loop below. + */ + + privep->zlp = true; + } + + /* Add one more packet to the TxFIFO. We will wait for the transfer + * complete event before we add the next packet (or part of a packet + * to the TxFIFO). + * + * The documentation says that we can can multiple packets to the TxFIFO, + * but it seems that we need to get the transfer complete event before + * we can add the next (or maybe I have got something wrong?) + */ + +#if 0 + while (privreq->req.xfrd < privreq->req.len || privep->zlp) +#else + if (privreq->req.xfrd < privreq->req.len || privep->zlp) +#endif + { + /* Get the number of bytes left to be sent in the request */ + + bytesleft = privreq->req.len - privreq->req.xfrd; + nbytes = bytesleft; + + /* Assume no zero-length-packet on the next pass through this loop */ + + privep->zlp = false; + + /* Limit the size of the transfer to one full packet and handle + * zero-length packets (ZLPs). + */ + + if (nbytes > 0) + { + /* Either send the maxpacketsize or all of the remaining data in + * the request. + */ + + if (nbytes >= privep->ep.maxpacket) + { + nbytes = privep->ep.maxpacket; + + /* Handle the case where this packet is exactly the + * maxpacketsize. Do we need to send a zero-length packet + * in this case? + */ + + if (bytesleft == privep->ep.maxpacket && + (privreq->req.flags & USBDEV_REQFLAGS_NULLPKT) != 0) + { + /* The ZLP flag is set TRUE whenever we want to force + * the driver to send a zero-length-packet on the next + * pass through this loop. The flag is cleared (above) + * whenever we are committed to sending any packet and + * set here when we want to force one more pass through + * the loop. + */ + + privep->zlp = true; + } + } + } + + /* Get the transfer size in 32-bit words */ + + nwords = (nbytes + 3) >> 2; + + /* Get the number of 32-bit words available in the TxFIFO. The + * DXTHSTS indicates the amount of free space available in the + * endpoint TxFIFO. Values are in terms of 32-bit words: + * + * 0: Endpoint TxFIFO is full + * 1: 1 word available + * 2: 2 words available + * n: n words available + */ + + regaddr = STM32_OTGHS_DTXFSTS(privep->epphy); + + /* Check for space in the TxFIFO. If space in the TxFIFO is not + * available, then set up an interrupt to resume the transfer when + * the TxFIFO is empty. + */ + + regval = stm32_getreg(regaddr); + if ((int)(regval & OTGHS_DTXFSTS_MASK) < nwords) + { + usbtrace( + TRACE_INTDECODE(STM32_TRACEINTID_EPIN_EMPWAIT), + (uint16_t)regval); + + /* There is insufficient space in the TxFIFO. Wait for a TxFIFO + * empty interrupt and try again. + */ + + uint32_t empmsk = stm32_getreg(STM32_OTGHS_DIEPEMPMSK); + empmsk |= OTGHS_DIEPEMPMSK(privep->epphy); + stm32_putreg(empmsk, STM32_OTGHS_DIEPEMPMSK); + +#ifdef CONFIG_DEBUG_FEATURES + /* Check if the configured TXFIFO size is sufficient for a given + * request. If not, raise an assertion here. + */ + + regval = stm32_getreg(STM32_OTGHS_DIEPTXF(privep->epphy)); + regval &= OTGHS_DIEPTXF_INEPTXFD_MASK; + regval >>= OTGHS_DIEPTXF_INEPTXFD_SHIFT; + uerr("EP%" PRId8 " TXLEN=%" PRId32 " nwords=%d\n", + privep->epphy, regval, nwords); + DEBUGASSERT(regval >= nwords); +#endif + + /* Terminate the transfer. We will try again when the TxFIFO empty + * interrupt is received. + */ + + return; + } + + /* Transfer data to the TxFIFO */ + + buf = privreq->req.buf + privreq->req.xfrd; + stm32_epin_transfer(privep, buf, nbytes); + + /* If it was not before, the OUT endpoint is now actively transferring + * data. + */ + + privep->active = true; + + /* EP0 is a special case */ + + if (privep->epphy == EP0) + { + priv->ep0state = EP0STATE_DATA_IN; + } + + /* Update for the next time through the loop */ + + privreq->req.xfrd += nbytes; + } + + /* Note that the ZLP, if any, must be sent as a separate transfer. The need + * for a ZLP is indicated by privep->zlp. If all of the bytes were sent + * (including any final null packet) then we are finished with the transfer + */ + + if (privreq->req.xfrd >= privreq->req.len && !privep->zlp) + { + usbtrace(TRACE_COMPLETE(privep->epphy), privreq->req.xfrd); + + /* We are finished with the request (although the transfer has not + * yet completed). + */ + + stm32_req_complete(privep, OK); + } +} + +/**************************************************************************** + * Name: stm32_rxfifo_read + * + * Description: + * Read packet from the RxFIFO into a read request. + * + ****************************************************************************/ + +static void stm32_rxfifo_read(struct stm32_ep_s *privep, + uint8_t *dest, uint16_t len) +{ + uint32_t regaddr; + int i; + + /* Get the address of the RxFIFO. Note: there is only one RxFIFO so + * we might as well use the address associated with EP0. + */ + + regaddr = STM32_OTGHS_DFIFO_DEP(EP0); + + /* Read 32-bits and write 4 x 8-bits at time + * (to avoid unaligned accesses) + */ + + for (i = 0; i < len; i += 4) + { + union + { + uint32_t w; + uint8_t b[4]; + } data; + + /* Read 1 x 32-bits of EP0 packet data */ + + data.w = stm32_getreg(regaddr); + + /* Write 4 x 8-bits of EP0 packet data */ + + *dest++ = data.b[0]; + *dest++ = data.b[1]; + *dest++ = data.b[2]; + *dest++ = data.b[3]; + } +} + +/**************************************************************************** + * Name: stm32_rxfifo_discard + * + * Description: + * Discard packet data from the RxFIFO. + * + ****************************************************************************/ + +static void stm32_rxfifo_discard(struct stm32_ep_s *privep, int len) +{ + if (len > 0) + { + uint32_t regaddr; + int i; + + /* Get the address of the RxFIFO Note: there is only one RxFIFO so + * we might as well use the address associated with EP0. + */ + + regaddr = STM32_OTGHS_DFIFO_DEP(EP0); + + /* Read 32-bits at time */ + + for (i = 0; i < len; i += 4) + { + volatile uint32_t data = stm32_getreg(regaddr); + UNUSED(data); + } + } +} + +/**************************************************************************** + * Name: stm32_epout_complete + * + * Description: + * This function is called when an OUT transfer complete interrupt is + * received. It completes the read request at the head of the endpoint's + * request queue. + * + ****************************************************************************/ + +static void stm32_epout_complete(struct stm32_usbdev_s *priv, + struct stm32_ep_s *privep) +{ + struct stm32_req_s *privreq; + + /* Since a transfer just completed, there must be a read request at the + * head of the endpoint request queue. + */ + + privreq = stm32_rqpeek(privep); + DEBUGASSERT(privreq); + + if (!privreq) + { + /* An OUT transfer completed, but no packet to receive the data. This + * should not happen. + */ + + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EPOUTQEMPTY), privep->epphy); + privep->active = false; + return; + } + + uinfo("EP%d: len=%zu xfrd=%zu\n", + privep->epphy, privreq->req.len, privreq->req.xfrd); + + /* Return the completed read request to the class driver and mark the state + * IDLE. + */ + + usbtrace(TRACE_COMPLETE(privep->epphy), privreq->req.xfrd); + stm32_req_complete(privep, OK); + privep->active = false; + + /* Now set up the next read request (if any) */ + + stm32_epout_request(priv, privep); +} + +/**************************************************************************** + * Name: stm32_ep0out_receive + * + * Description: + * This function is called from the RXFLVL interrupt handler when new + * incoming data is available in the endpoint's RxFIFO. This function will + * simply copy the incoming data into pending request's data buffer. + * + ****************************************************************************/ + +static inline void stm32_ep0out_receive(struct stm32_ep_s *privep, + int bcnt) +{ + struct stm32_usbdev_s *priv; + + /* Sanity Checking */ + + DEBUGASSERT(privep && privep->dev); + priv = (struct stm32_usbdev_s *)privep->dev; + + uinfo("EP0: bcnt=%d\n", bcnt); + usbtrace(TRACE_READ(EP0), bcnt); + + /* Verify that an OUT SETUP request as received before this data was + * received in the RxFIFO. + */ + + if (priv->ep0state == EP0STATE_SETUP_OUT) + { + /* Read the data into our special buffer for SETUP data */ + + int readlen = MIN(CONFIG_USBDEV_SETUP_MAXDATASIZE, bcnt); + stm32_rxfifo_read(privep, priv->ep0data, readlen); + + /* Do we have to discard any excess bytes? */ + + stm32_rxfifo_discard(privep, bcnt - readlen); + + /* Now we can process the setup command */ + + privep->active = false; + priv->ep0state = EP0STATE_SETUP_READY; + priv->ep0datlen = readlen; + + stm32_ep0out_setup(priv); + } + else + { + /* This is an error. We don't have any idea what to do with the EP0 + * data in this case. Just read and discard it so that the RxFIFO + * does not become constipated. + */ + + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_NOOUTSETUP), priv->ep0state); + stm32_rxfifo_discard(privep, bcnt); + privep->active = false; + } +} + +/**************************************************************************** + * Name: stm32_epout_receive + * + * Description: + * This function is called from the RXFLVL interrupt handler when new + * incoming data is available in the endpoint's RxFIFO. This function will + * simply copy the incoming data into pending request's data buffer. + * + ****************************************************************************/ + +static inline void stm32_epout_receive(struct stm32_ep_s *privep, + int bcnt) +{ + struct stm32_req_s *privreq; + uint8_t *dest; + int buflen; + int readlen; + + /* Get a reference to the request at the head of the endpoint's request + * queue. + */ + + privreq = stm32_rqpeek(privep); + if (!privreq) + { + /* Incoming data is available in the RxFIFO, but there is no read setup + * to receive the receive the data. This should not happen for data + * endpoints; those endpoints should have been NAKing any OUT data + * tokens. + * + * We should get here normally on OUT data phase following an OUT + * SETUP command. EP0 data will still receive data in this case and it + * should not be NAKing. + */ + + if (privep->epphy == 0) + { + stm32_ep0out_receive(privep, bcnt); + } + else + { + /* Otherwise, the data is lost. This really should not happen if + * NAKing is working as expected. + */ + + usbtrace( + TRACE_DEVERROR(STM32_TRACEERR_EPOUTQEMPTY), privep->epphy); + + /* Discard the data in the RxFIFO */ + + stm32_rxfifo_discard(privep, bcnt); + } + + privep->active = false; + return; + } + + uinfo("EP%d: len=%zu xfrd=%zu\n", + privep->epphy, privreq->req.len, privreq->req.xfrd); + usbtrace(TRACE_READ(privep->epphy), bcnt); + + /* Get the number of bytes to transfer from the RxFIFO */ + + buflen = privreq->req.len - privreq->req.xfrd; + DEBUGASSERT(buflen > 0 && buflen >= bcnt); + readlen = MIN(buflen, bcnt); + + /* Get the destination of the data transfer */ + + dest = privreq->req.buf + privreq->req.xfrd; + + /* Transfer the data from the RxFIFO to the request's data buffer */ + + stm32_rxfifo_read(privep, dest, readlen); + + /* If there were more bytes in the RxFIFO than could be held in the read + * request, then we will have to discard those. + */ + + stm32_rxfifo_discard(privep, bcnt - readlen); + + /* Update the number of bytes transferred */ + + privreq->req.xfrd += readlen; +} + +/**************************************************************************** + * Name: stm32_epout_request + * + * Description: + * This function is called when either (1) new read request is received, or + * (2) a pending receive request completes. If there is no read in + * pending, then this function will initiate the next OUT (read) operation. + * + ****************************************************************************/ + +static void stm32_epout_request(struct stm32_usbdev_s *priv, + struct stm32_ep_s *privep) +{ + struct stm32_req_s *privreq; + uint32_t regaddr; + uint32_t regval; + uint32_t xfrsize; + uint32_t pktcnt; + + /* Make sure that there is not already a pending request request. If there + * is, just return, leaving the newly received request in the request + * queue. + */ + + if (!privep->active) + { + /* Loop until a valid request is found (or the request queue is empty). + * The loop is only need to look at the request queue again is an + * invalid read request is encountered. + */ + + for (; ; ) + { + /* Get a reference to the request at the head of the endpoint's + * request queue + */ + + privreq = stm32_rqpeek(privep); + if (!privreq) + { + usbtrace( + TRACE_DEVERROR(STM32_TRACEERR_EPOUTQEMPTY), privep->epphy); + + /* There are no read requests to be setup. Configure the + * hardware to NAK any incoming packets. (This should already + * be the case. I think that the hardware will automatically + * NAK after a transfer is completed until SNAK is cleared). + */ + + regaddr = STM32_OTGHS_DOEPCTL(privep->epphy); + regval = stm32_getreg(regaddr); + regval |= OTGHS_DOEPCTL_SNAK; + stm32_putreg(regval, regaddr); + + /* This endpoint is no longer actively transferring */ + + privep->active = false; + return; + } + + uinfo("EP%d: len=%d\n", privep->epphy, privreq->req.len); + + /* Ignore any attempt to receive a zero length packet (this really + * should not happen. + */ + + if (privreq->req.len <= 0) + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EPOUTNULLPACKET), 0); + stm32_req_complete(privep, OK); + } + + /* Otherwise, we have a usable read request... + * break out of the loop + */ + + else + { + break; + } + } + + /* Setup the pending read into the request buffer. First calculate: + * + * pktcnt = the number of packets (of maxpacket bytes) required to + * perform the transfer. + * xfrsize = The total number of bytes required (in units of + * maxpacket bytes). + */ + + pktcnt = (privreq->req.len + (privep->ep.maxpacket - 1)) / + privep->ep.maxpacket; + xfrsize = pktcnt * privep->ep.maxpacket; + + /* Then setup the hardware to perform this transfer */ + + regaddr = STM32_OTGHS_DOEPTSIZ(privep->epphy); + regval = stm32_getreg(regaddr); + regval &= ~(OTGHS_DOEPTSIZ_XFRSIZ_MASK | OTGHS_DOEPTSIZ_PKTCNT_MASK); + regval |= (xfrsize << OTGHS_DOEPTSIZ_XFRSIZ_SHIFT); + regval |= (pktcnt << OTGHS_DOEPTSIZ_PKTCNT_SHIFT); + stm32_putreg(regval, regaddr); + + /* Then enable the transfer */ + + regaddr = STM32_OTGHS_DOEPCTL(privep->epphy); + regval = stm32_getreg(regaddr); + + /* When an isochronous transfer is enabled the Even/Odd frame bit must + * also be set appropriately. + */ + +#ifdef CONFIG_USBDEV_ISOCHRONOUS + if (privep->eptype == USB_EP_ATTR_XFER_ISOC) + { + if (privep->odd) + { + regval |= OTGHS_DOEPCTL_SODDFRM; + } + else + { + regval |= OTGHS_DOEPCTL_SEVNFRM; + } + } +#endif + + /* Clearing NAKing and enable the transfer. */ + + regval |= (OTGHS_DOEPCTL_CNAK | OTGHS_DOEPCTL_EPENA); + stm32_putreg(regval, regaddr); + + /* A transfer is now active on this endpoint */ + + privep->active = true; + + /* EP0 is a special case. We need to know when to switch back to + * normal SETUP processing. + */ + + if (privep->epphy == EP0) + { + priv->ep0state = EP0STATE_DATA_OUT; + } + } +} + +/**************************************************************************** + * Name: stm32_ep_flush + * + * Description: + * Flush any primed descriptors from this ep + * + ****************************************************************************/ + +static void stm32_ep_flush(struct stm32_ep_s *privep) +{ + if (privep->isin) + { + stm32_txfifo_flush(OTGHS_GRSTCTL_TXFNUM_D(privep->epphy)); + } + else + { + stm32_rxfifo_flush(); + } +} + +/**************************************************************************** + * Name: stm32_req_complete + * + * Description: + * Handle termination of the request at the head of the endpoint request + * queue. + * + ****************************************************************************/ + +static void stm32_req_complete(struct stm32_ep_s *privep, int16_t result) +{ + struct stm32_req_s *privreq; + + /* Remove the request at the head of the request list */ + + privreq = stm32_req_remfirst(privep); + DEBUGASSERT(privreq != NULL); + + /* If endpoint 0, temporarily reflect the state of protocol stalled + * in the callback. + */ + + bool stalled = privep->stalled; + if (privep->epphy == EP0) + { + privep->stalled = privep->dev->stalled; + } + + /* Save the result in the request structure */ + + privreq->req.result = result; + + /* Callback to the request completion handler */ + + privreq->req.callback(&privep->ep, &privreq->req); + + /* Restore the stalled indication */ + + privep->stalled = stalled; +} + +/**************************************************************************** + * Name: stm32_req_cancel + * + * Description: + * Cancel all pending requests for an endpoint + * + ****************************************************************************/ + +static void stm32_req_cancel(struct stm32_ep_s *privep, int16_t status) +{ + if (!stm32_rqempty(privep)) + { + stm32_ep_flush(privep); + } + + while (!stm32_rqempty(privep)) + { + usbtrace(TRACE_COMPLETE(privep->epphy), + (stm32_rqpeek(privep))->req.xfrd); + stm32_req_complete(privep, status); + } +} + +/**************************************************************************** + * Name: stm32_ep_findbyaddr + * + * Description: + * Find the physical endpoint structure corresponding to a logic endpoint + * address + * + ****************************************************************************/ + +static struct stm32_ep_s *stm32_ep_findbyaddr(struct stm32_usbdev_s *priv, + uint16_t eplog) +{ + struct stm32_ep_s *privep; + uint8_t epphy = USB_EPNO(eplog); + + if (epphy >= STM32_NENDPOINTS) + { + return NULL; + } + + /* Is this an IN or an OUT endpoint? */ + + if (USB_ISEPIN(eplog)) + { + privep = &priv->epin[epphy]; + } + else + { + privep = &priv->epout[epphy]; + } + + /* Return endpoint reference */ + + DEBUGASSERT(privep->epphy == epphy); + return privep; +} + +/**************************************************************************** + * Name: stm32_req_dispatch + * + * Description: + * Provide unhandled setup actions to the class driver. This is logically + * part of the USB interrupt handler. + * + ****************************************************************************/ + +static int stm32_req_dispatch(struct stm32_usbdev_s *priv, + const struct usb_ctrlreq_s *ctrl) +{ + int ret = -EIO; + + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_DISPATCH), 0); + if (priv->driver) + { + /* Forward to the control request to the class driver implementation */ + + ret = CLASS_SETUP(priv->driver, &priv->usbdev, ctrl, + priv->ep0data, priv->ep0datlen); + } + + if (ret < 0) + { + /* Stall on failure */ + + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_DISPATCHSTALL), 0); + priv->stalled = true; + } + + return ret; +} + +/**************************************************************************** + * Name: stm32_usbreset + * + * Description: + * Reset Usb engine + * + ****************************************************************************/ + +static void stm32_usbreset(struct stm32_usbdev_s *priv) +{ + struct stm32_ep_s *privep; + uint32_t regval; + int i; + + /* Clear the Remote Wake-up Signaling */ + + regval = stm32_getreg(STM32_OTGHS_DCTL); + regval &= ~OTGHS_DCTL_RWUSIG; + stm32_putreg(regval, STM32_OTGHS_DCTL); + + /* Flush the EP0 Tx FIFO */ + + stm32_txfifo_flush(OTGHS_GRSTCTL_TXFNUM_D(EP0)); + + /* Tell the class driver that we are disconnected. The class + * driver should then accept any new configurations. + */ + + if (priv->driver) + { + CLASS_DISCONNECT(priv->driver, &priv->usbdev); + } + + /* Mark all endpoints as available */ + + priv->epavail[0] = STM32_EP_AVAILABLE; + priv->epavail[1] = STM32_EP_AVAILABLE; + + /* Disable all end point interrupts */ + + for (i = 0; i < STM32_NENDPOINTS ; i++) + { + /* Disable endpoint interrupts */ + + stm32_putreg(0xff, STM32_OTGHS_DIEPINT(i)); + stm32_putreg(0xff, STM32_OTGHS_DOEPINT(i)); + + /* Return write requests to the class implementation */ + + privep = &priv->epin[i]; + stm32_req_cancel(privep, -ESHUTDOWN); + + /* Reset IN endpoint status */ + + privep->stalled = false; + + /* Return read requests to the class implementation */ + + privep = &priv->epout[i]; + stm32_req_cancel(privep, -ESHUTDOWN); + + /* Reset endpoint status */ + + privep->stalled = false; + } + + stm32_putreg(0xffffffff, STM32_OTGHS_DAINT); + + /* Mask all device endpoint interrupts except EP0 */ + + regval = (OTGHS_DAINT_IEP(EP0) | OTGHS_DAINT_OEP(EP0)); + stm32_putreg(regval, STM32_OTGHS_DAINTMSK); + + /* Unmask OUT interrupts */ + + regval = (OTGHS_DOEPMSK_XFRCM | OTGHS_DOEPMSK_STUPM | OTGHS_DOEPMSK_EPDM); + stm32_putreg(regval, STM32_OTGHS_DOEPMSK); + + /* Unmask IN interrupts */ + + regval = (OTGHS_DIEPMSK_XFRCM | OTGHS_DIEPMSK_EPDM | OTGHS_DIEPMSK_TOM); + stm32_putreg(regval, STM32_OTGHS_DIEPMSK); + + /* Reset device address to 0 */ + + stm32_setaddress(priv, 0); + priv->devstate = DEVSTATE_DEFAULT; + priv->usbdev.speed = USB_SPEED_FULL; + + /* Re-configure EP0 */ + + stm32_ep0_configure(priv); + + /* Setup EP0 to receive SETUP packets */ + + stm32_ep0out_ctrlsetup(priv); +} + +/**************************************************************************** + * Name: stm32_ep0out_testmode + * + * Description: + * Select test mode + * + ****************************************************************************/ + +static inline void stm32_ep0out_testmode(struct stm32_usbdev_s *priv, + uint16_t index) +{ + uint8_t testmode; + + testmode = index >> 8; + switch (testmode) + { + case 1: + priv->testmode = OTGHS_TESTMODE_J; + break; + + case 2: + priv->testmode = OTGHS_TESTMODE_K; + break; + + case 3: + priv->testmode = OTGHS_TESTMODE_SE0_NAK; + break; + + case 4: + priv->testmode = OTGHS_TESTMODE_PACKET; + break; + + case 5: + priv->testmode = OTGHS_TESTMODE_FORCE; + break; + + default: + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADTESTMODE), testmode); + priv->dotest = false; + priv->testmode = OTGHS_TESTMODE_DISABLED; + priv->stalled = true; + } + + priv->dotest = true; + stm32_ep0in_transmitzlp(priv); +} + +/**************************************************************************** + * Name: stm32_ep0out_stdrequest + * + * Description: + * Handle a standard request on EP0. Pick off the things of interest to + * the USB device controller driver; pass what is left to the class driver. + * + ****************************************************************************/ + +static inline void stm32_ep0out_stdrequest(struct stm32_usbdev_s *priv, + struct stm32_ctrlreq_s *ctrlreq) +{ + struct stm32_ep_s *privep; + + /* Handle standard request */ + + switch (ctrlreq->req) + { + case USB_REQ_GETSTATUS: + { + /* type: device-to-host; recipient = device, interface, endpoint + * value: 0 + * index: zero interface endpoint + * len: 2; data = status + */ + + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_GETSTATUS), 0); + if (!priv->addressed || + ctrlreq->len != 2 || + USB_REQ_ISOUT(ctrlreq->type) || + ctrlreq->value != 0) + { + priv->stalled = true; + } + else + { + switch (ctrlreq->type & USB_REQ_RECIPIENT_MASK) + { + case USB_REQ_RECIPIENT_ENDPOINT: + { + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPGETSTATUS), 0); + privep = stm32_ep_findbyaddr(priv, ctrlreq->index); + if (!privep) + { + usbtrace( + TRACE_DEVERROR(STM32_TRACEERR_BADEPGETSTATUS), 0); + priv->stalled = true; + } + else + { + if (privep->stalled) + { + priv->ep0data[0] = (1 << USB_FEATURE_ENDPOINTHALT); + } + else + { + priv->ep0data[0] = 0; /* Not stalled */ + } + + priv->ep0data[1] = 0; + stm32_ep0in_setupresponse(priv, priv->ep0data, 2); + } + } + break; + + case USB_REQ_RECIPIENT_DEVICE: + { + if (ctrlreq->index == 0) + { + usbtrace( + TRACE_INTDECODE(STM32_TRACEINTID_DEVGETSTATUS), 0); + + /* Features: Remote Wakeup and self-powered */ + + priv->ep0data[0] = (priv->selfpowered << + USB_FEATURE_SELFPOWERED); + priv->ep0data[0] |= (priv->wakeup << + USB_FEATURE_REMOTEWAKEUP); + priv->ep0data[1] = 0; + + stm32_ep0in_setupresponse(priv, priv->ep0data, 2); + } + else + { + usbtrace( + TRACE_DEVERROR(STM32_TRACEERR_BADDEVGETSTATUS), 0); + priv->stalled = true; + } + } + break; + + case USB_REQ_RECIPIENT_INTERFACE: + { + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_IFGETSTATUS), 0); + priv->ep0data[0] = 0; + priv->ep0data[1] = 0; + + stm32_ep0in_setupresponse(priv, priv->ep0data, 2); + } + break; + + default: + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADGETSTATUS), 0); + priv->stalled = true; + } + break; + } + } + } + break; + + case USB_REQ_CLEARFEATURE: + { + /* type: host-to-device; recipient = device, interface or endpoint + * value: feature selector + * index: zero interface endpoint; + * len: zero, data = none + */ + + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_CLEARFEATURE), 0); + if (priv->addressed != 0 && ctrlreq->len == 0) + { + uint8_t recipient = ctrlreq->type & USB_REQ_RECIPIENT_MASK; + if (recipient == USB_REQ_RECIPIENT_ENDPOINT && + ctrlreq->value == USB_FEATURE_ENDPOINTHALT && + (privep = stm32_ep_findbyaddr(priv, ctrlreq->index)) != NULL) + { + stm32_ep_clrstall(privep); + stm32_ep0in_transmitzlp(priv); + } + else if (recipient == USB_REQ_RECIPIENT_DEVICE && + ctrlreq->value == USB_FEATURE_REMOTEWAKEUP) + { + priv->wakeup = 0; + stm32_ep0in_transmitzlp(priv); + } + else + { + /* Actually, I think we could just stall here. */ + + stm32_req_dispatch(priv, &priv->ctrlreq); + } + } + else + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADCLEARFEATURE), 0); + priv->stalled = true; + } + } + break; + + case USB_REQ_SETFEATURE: + { + /* type: host-to-device; recipient = device, interface, endpoint + * value: feature selector + * index: zero interface endpoint; + * len: 0; data = none + */ + + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SETFEATURE), 0); + if (priv->addressed != 0 && ctrlreq->len == 0) + { + uint8_t recipient = ctrlreq->type & USB_REQ_RECIPIENT_MASK; + if (recipient == USB_REQ_RECIPIENT_ENDPOINT && + ctrlreq->value == USB_FEATURE_ENDPOINTHALT && + (privep = stm32_ep_findbyaddr(priv, ctrlreq->index)) != NULL) + { + stm32_ep_setstall(privep); + stm32_ep0in_transmitzlp(priv); + } + else if (recipient == USB_REQ_RECIPIENT_DEVICE && + ctrlreq->value == USB_FEATURE_REMOTEWAKEUP) + { + priv->wakeup = 1; + stm32_ep0in_transmitzlp(priv); + } + else if (recipient == USB_REQ_RECIPIENT_DEVICE && + ctrlreq->value == USB_FEATURE_TESTMODE && + ((ctrlreq->index & 0xff) == 0)) + { + stm32_ep0out_testmode(priv, ctrlreq->index); + } + else if (priv->configured) + { + /* Actually, I think we could just stall here. */ + + stm32_req_dispatch(priv, &priv->ctrlreq); + } + else + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADSETFEATURE), 0); + priv->stalled = true; + } + } + else + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADSETFEATURE), 0); + priv->stalled = true; + } + } + break; + + case USB_REQ_SETADDRESS: + { + /* type: host-to-device; recipient = device + * value: device address + * index: 0 + * len: 0; data = none + */ + + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SETADDRESS), + ctrlreq->value); + if ((ctrlreq->type & USB_REQ_RECIPIENT_MASK) == + USB_REQ_RECIPIENT_DEVICE && + ctrlreq->index == 0 && + ctrlreq->len == 0 && + ctrlreq->value < 128 && + priv->devstate != DEVSTATE_CONFIGURED) + { + /* Save the address. We cannot actually change to the next + * address until the completion of the status phase. + */ + + stm32_setaddress(priv, (uint16_t)priv->ctrlreq.value[0]); + stm32_ep0in_transmitzlp(priv); + } + else + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADSETADDRESS), 0); + priv->stalled = true; + } + } + break; + + case USB_REQ_GETDESCRIPTOR: + /* type: device-to-host; recipient = device + * value: descriptor type and index + * index: 0 or language ID; + * len: descriptor len; data = descriptor + */ + + case USB_REQ_SETDESCRIPTOR: + /* type: host-to-device; recipient = device + * value: descriptor type and index + * index: 0 or language ID; + * len: descriptor len; data = descriptor + */ + + { + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_GETSETDESC), 0); + if ((ctrlreq->type & USB_REQ_RECIPIENT_MASK) == + USB_REQ_RECIPIENT_DEVICE || + (ctrlreq->type & USB_REQ_RECIPIENT_MASK) == + USB_REQ_RECIPIENT_INTERFACE) + { + stm32_req_dispatch(priv, &priv->ctrlreq); + } + else + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADGETSETDESC), 0); + priv->stalled = true; + } + } + break; + + case USB_REQ_GETCONFIGURATION: + /* type: device-to-host; recipient = device + * value: 0; + * index: 0; + * len: 1; data = configuration value + */ + + { + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_GETCONFIG), 0); + if (priv->addressed && + (ctrlreq->type & USB_REQ_RECIPIENT_MASK) == + USB_REQ_RECIPIENT_DEVICE && + ctrlreq->value == 0 && + ctrlreq->index == 0 && + ctrlreq->len == 1) + { + stm32_req_dispatch(priv, &priv->ctrlreq); + } + else + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADGETCONFIG), 0); + priv->stalled = true; + } + } + break; + + case USB_REQ_SETCONFIGURATION: + /* type: host-to-device; recipient = device + * value: configuration value + * index: 0; + * len: 0; data = none + */ + + { + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SETCONFIG), 0); + if (priv->addressed && + (ctrlreq->type & USB_REQ_RECIPIENT_MASK) == + USB_REQ_RECIPIENT_DEVICE && + ctrlreq->index == 0 && + ctrlreq->len == 0) + { + /* Give the configuration to the class driver */ + + int ret = stm32_req_dispatch(priv, &priv->ctrlreq); + + /* If the class driver accepted the configuration, then mark the + * device state as configured (or not, depending on the + * configuration). + */ + + if (ret == OK) + { + uint8_t cfg = (uint8_t)ctrlreq->value; + if (cfg != 0) + { + priv->devstate = DEVSTATE_CONFIGURED; + priv->configured = true; + } + else + { + priv->devstate = DEVSTATE_ADDRESSED; + priv->configured = false; + } + } + } + else + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADSETCONFIG), 0); + priv->stalled = true; + } + } + break; + + case USB_REQ_GETINTERFACE: + /* type: device-to-host; recipient = interface + * value: 0 + * index: interface; + * len: 1; data = alt interface + */ + + case USB_REQ_SETINTERFACE: + /* type: host-to-device; recipient = interface + * value: alternate setting + * index: interface; + * len: 0; data = none + */ + + { + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_GETSETIF), 0); + stm32_req_dispatch(priv, &priv->ctrlreq); + } + break; + + case USB_REQ_SYNCHFRAME: + /* type: device-to-host; recipient = endpoint + * value: 0 + * index: endpoint; + * len: 2; data = frame number + */ + + { + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SYNCHFRAME), 0); + } + break; + + default: + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDCTRLREQ), 0); + priv->stalled = true; + } + break; + } +} + +/**************************************************************************** + * Name: stm32_ep0out_setup + * + * Description: + * USB Ctrl EP Setup Event. This is logically part of the USB interrupt + * handler. This event occurs when a setup packet is receive on EP0 OUT. + * + ****************************************************************************/ + +static inline void stm32_ep0out_setup(struct stm32_usbdev_s *priv) +{ + struct stm32_ctrlreq_s ctrlreq; + + /* Verify that a SETUP was received */ + + if (priv->ep0state != EP0STATE_SETUP_READY) + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EP0NOSETUP), priv->ep0state); + return; + } + + /* Terminate any pending requests */ + + stm32_req_cancel(&priv->epout[EP0], -EPROTO); + stm32_req_cancel(&priv->epin[EP0], -EPROTO); + + /* Assume NOT stalled */ + + priv->epout[EP0].stalled = false; + priv->epin[EP0].stalled = false; + priv->stalled = false; + + /* Starting to process a control request - update state */ + + priv->ep0state = EP0STATE_SETUP_PROCESS; + + /* And extract the little-endian 16-bit values to host order */ + + ctrlreq.type = priv->ctrlreq.type; + ctrlreq.req = priv->ctrlreq.req; + ctrlreq.value = GETUINT16(priv->ctrlreq.value); + ctrlreq.index = GETUINT16(priv->ctrlreq.index); + ctrlreq.len = GETUINT16(priv->ctrlreq.len); + + uinfo("type=%02x req=%02x value=%04x index=%04x len=%04x\n", + ctrlreq.type, ctrlreq.req, ctrlreq.value, ctrlreq.index, + ctrlreq.len); + + /* Check for a standard request */ + + if ((ctrlreq.type & USB_REQ_TYPE_MASK) != USB_REQ_TYPE_STANDARD) + { + /* Dispatch any non-standard requests */ + + stm32_req_dispatch(priv, &priv->ctrlreq); + } + else + { + /* Handle standard requests. */ + + stm32_ep0out_stdrequest(priv, &ctrlreq); + } + + /* Check if the setup processing resulted in a STALL */ + + if (priv->stalled) + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EP0SETUPSTALLED), + priv->ep0state); + stm32_ep0_stall(priv); + } + + /* Reset state/data associated with the SETUP request */ + + priv->ep0datlen = 0; +} + +/**************************************************************************** + * Name: stm32_epout + * + * Description: + * This is part of the OUT endpoint interrupt processing. This function + * handles the OUT event for a single endpoint. + * + ****************************************************************************/ + +static inline void stm32_epout(struct stm32_usbdev_s *priv, uint8_t epno) +{ + struct stm32_ep_s *privep; + + /* Endpoint 0 is a special case. */ + + if (epno == 0) + { + privep = &priv->epout[EP0]; + + /* In the EP0STATE_DATA_OUT state, we are receiving data into the + * request buffer. In that case, we must continue the request + * processing. + */ + + if (priv->ep0state == EP0STATE_DATA_OUT) + { + /* Continue processing data from the EP0 OUT request queue */ + + stm32_epout_complete(priv, privep); + + /* If we are not actively processing an OUT request, then we + * need to setup to receive the next control request. + */ + + if (!privep->active) + { + stm32_ep0out_ctrlsetup(priv); + priv->ep0state = EP0STATE_IDLE; + } + } + } + + /* For other endpoints, the only possibility is that we are continuing + * or finishing an OUT request. + */ + + else if (priv->devstate == DEVSTATE_CONFIGURED) + { + stm32_epout_complete(priv, &priv->epout[epno]); + } +} + +/**************************************************************************** + * Name: stm32_epout_interrupt + * + * Description: + * USB OUT endpoint interrupt handler. The core generates this interrupt + * when there is an interrupt is pending on one of the OUT endpoints of the + * core. The driver must read the OTGHS DAINT register to determine the + * exact number of the OUT endpoint on which the interrupt occurred, and + * then read the corresponding OTGHS DOEPINTx register to determine the + * exact cause of the interrupt. + * + ****************************************************************************/ + +static inline void stm32_epout_interrupt(struct stm32_usbdev_s *priv) +{ + uint32_t daint; + uint32_t regval; + uint32_t doepint; + int epno; + + /* Get the pending, enabled interrupts for the OUT endpoint from the + * endpoint interrupt status register. + */ + + regval = stm32_getreg(STM32_OTGHS_DAINT); + regval &= stm32_getreg(STM32_OTGHS_DAINTMSK); + daint = (regval & OTGHS_DAINT_OEP_MASK) >> OTGHS_DAINT_OEP_SHIFT; + + if (daint == 0) + { + /* We got an interrupt, but there is no unmasked endpoint that caused + * it ?! When this happens, the interrupt flag never gets cleared and + * we are stuck in infinite interrupt loop. + * + * This shouldn't happen if we are diligent about handling timing + * issues when masking endpoint interrupts. However, this workaround + * avoids infinite loop and allows operation to continue normally. It + * works by clearing each endpoint flags, masked or not. + */ + + regval = stm32_getreg(STM32_OTGHS_DAINT); + daint = (regval & OTGHS_DAINT_OEP_MASK) >> OTGHS_DAINT_OEP_SHIFT; + + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EPOUTUNEXPECTED), + (uint16_t)regval); + + epno = 0; + while (daint) + { + if ((daint & 1) != 0) + { + regval = stm32_getreg(STM32_OTGHS_DOEPINT(epno)); + uinfo("DOEPINT(%d) = %08" PRIx32 "\n", epno, regval); + stm32_putreg(0xff, STM32_OTGHS_DOEPINT(epno)); + } + + epno++; + daint >>= 1; + } + + return; + } + + /* Process each pending IN endpoint interrupt */ + + epno = 0; + while (daint) + { + /* Is an OUT interrupt pending for this endpoint? */ + + if ((daint & 1) != 0) + { + /* Yes.. get the OUT endpoint interrupt status */ + + doepint = stm32_getreg(STM32_OTGHS_DOEPINT(epno)); + doepint &= stm32_getreg(STM32_OTGHS_DOEPMSK); + + /* Transfer completed interrupt. This interrupt is triggered when + * stm32_rxinterrupt() removes the last packet data from the + * RxFIFO. In this case, core internally sets the NAK bit for this + * endpoint to prevent it from receiving any more packets. + */ + + if ((doepint & OTGHS_DOEPINT_XFRC) != 0) + { + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPOUT_XFRC), + (uint16_t)doepint); + + /* Clear the bit in DOEPINTn for this interrupt */ + + stm32_putreg(OTGHS_DOEPINT_XFRC, STM32_OTGHS_DOEPINT(epno)); + + /* Handle the RX transfer data ready event */ + + stm32_epout(priv, epno); + } + + /* Endpoint disabled interrupt (ignored because this interrupt is + * used in polled mode by the endpoint disable logic). + */ +#if 1 + /* REVISIT: */ + + if ((doepint & OTGHS_DOEPINT_EPDISD) != 0) + { + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPOUT_EPDISD), + (uint16_t)doepint); + + /* Clear the bit in DOEPINTn for this interrupt */ + + stm32_putreg(OTGHS_DOEPINT_EPDISD, STM32_OTGHS_DOEPINT(epno)); + } +#endif + + /* Setup Phase Done (control EPs) */ + + if ((doepint & OTGHS_DOEPINT_SETUP) != 0) + { + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPOUT_SETUP), + priv->ep0state); + + /* Handle the receipt of the IN SETUP packets now (OUT setup + * packet processing may be delayed until the accompanying + * OUT DATA is received) + */ + + if (priv->ep0state == EP0STATE_SETUP_READY) + { + stm32_ep0out_setup(priv); + } + + stm32_putreg(OTGHS_DOEPINT_SETUP, STM32_OTGHS_DOEPINT(epno)); + } + } + + epno++; + daint >>= 1; + } +} + +/**************************************************************************** + * Name: stm32_epin_runtestmode + * + * Description: + * Execute the test mode setup by the SET FEATURE request + * + ****************************************************************************/ + +static inline void stm32_epin_runtestmode(struct stm32_usbdev_s *priv) +{ + uint32_t regval = stm32_getreg(STM32_OTGHS_DCTL); + regval &= OTGHS_DCTL_TCTL_MASK; + regval |= (uint32_t)priv->testmode << OTGHS_DCTL_TCTL_SHIFT; + stm32_putreg(regval , STM32_OTGHS_DCTL); + + priv->dotest = 0; + priv->testmode = OTGHS_TESTMODE_DISABLED; +} + +/**************************************************************************** + * Name: stm32_epin + * + * Description: + * This is part of the IN endpoint interrupt processing. This function + * handles the IN event for a single endpoint. + * + ****************************************************************************/ + +static inline void stm32_epin(struct stm32_usbdev_s *priv, uint8_t epno) +{ + struct stm32_ep_s *privep = &priv->epin[epno]; + + /* Endpoint 0 is a special case. */ + + if (epno == 0) + { + /* In the EP0STATE_DATA_IN state, we are sending data from request + * buffer. In that case, we must continue the request processing. + */ + + if (priv->ep0state == EP0STATE_DATA_IN) + { + /* Continue processing data from the EP0 OUT request queue */ + + stm32_epin_request(priv, privep); + + /* If we are not actively processing an OUT request, then we + * need to setup to receive the next control request. + */ + + if (!privep->active) + { + stm32_ep0out_ctrlsetup(priv); + priv->ep0state = EP0STATE_IDLE; + } + } + + /* Test mode is another special case */ + + if (priv->dotest) + { + stm32_epin_runtestmode(priv); + } + } + + /* For other endpoints, the only possibility is that we are continuing + * or finishing an IN request. + */ + + else if (priv->devstate == DEVSTATE_CONFIGURED) + { + /* Continue processing data from the endpoint write request queue */ + + stm32_epin_request(priv, privep); + } +} + +/**************************************************************************** + * Name: stm32_epin_txfifoempty + * + * Description: + * TxFIFO empty interrupt handling + * + ****************************************************************************/ + +static inline void stm32_epin_txfifoempty(struct stm32_usbdev_s *priv, + int epno) +{ + struct stm32_ep_s *privep = &priv->epin[epno]; + + /* Continue processing the write request queue. This may mean sending + * more data from the existing request or terminating the current requests + * and (perhaps) starting the IN transfer from the next write request. + */ + + stm32_epin_request(priv, privep); +} + +/**************************************************************************** + * Name: stm32_epin_interrupt + * + * Description: + * USB IN endpoint interrupt handler. The core generates this interrupt + * when an interrupt is pending on one of the IN endpoints of the core. + * The driver must read the OTGHS DAINT register to determine the exact + * number of the IN endpoint on which the interrupt occurred, and then read + * the corresponding OTGHS DIEPINTx register to determine the exact cause + * of the interrupt. + * + ****************************************************************************/ + +static inline void stm32_epin_interrupt(struct stm32_usbdev_s *priv) +{ + uint32_t diepint; + uint32_t daint; + uint32_t mask; + uint32_t empty; + int epno; + + /* Get the pending, enabled interrupts for the IN endpoint from the + * endpoint interrupt status register. + */ + + daint = stm32_getreg(STM32_OTGHS_DAINT); + daint &= stm32_getreg(STM32_OTGHS_DAINTMSK); + daint &= OTGHS_DAINT_IEP_MASK; + + if (daint == 0) + { + /* We got an interrupt, but there is no unmasked endpoint that caused + * it ?! When this happens, the interrupt flag never gets cleared and + * we are stuck in infinite interrupt loop. + * + * This shouldn't happen if we are diligent about handling timing + * issues when masking endpoint interrupts. However, this workaround + * avoids infinite loop and allows operation to continue normally. It + * works by clearing each endpoint flags, masked or not. + */ + + daint = stm32_getreg(STM32_OTGHS_DAINT); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EPINUNEXPECTED), + (uint16_t)daint); + + daint &= OTGHS_DAINT_IEP_MASK; + epno = 0; + + while (daint) + { + if ((daint & 1) != 0) + { + uinfo("DIEPINT(%d) = %08" PRIx32 "\n", + epno, stm32_getreg(STM32_OTGHS_DIEPINT(epno))); + stm32_putreg(0xff, STM32_OTGHS_DIEPINT(epno)); + } + + epno++; + daint >>= 1; + } + + return; + } + + /* Process each pending IN endpoint interrupt */ + + epno = 0; + while (daint) + { + /* Is an IN interrupt pending for this endpoint? */ + + if ((daint & 1) != 0) + { + /* Get IN interrupt mask register. Bits 0-6 correspond to enabled + * interrupts as will be found in the DIEPINT interrupt status + * register. + */ + + mask = stm32_getreg(STM32_OTGHS_DIEPMSK); + + /* Check if the TxFIFO not empty interrupt is enabled for this + * endpoint in the DIEPMSK register. Bits n corresponds to + * endpoint n in the register. That condition corresponds to + * bit 7 of the DIEPINT interrupt status register. There is + * no TXFE bit in the mask register, so we fake one here. + */ + + empty = stm32_getreg(STM32_OTGHS_DIEPEMPMSK); + if ((empty & OTGHS_DIEPEMPMSK(epno)) != 0) + { + mask |= OTGHS_DIEPINT_TXFE; + } + + /* Now, read the interrupt status and mask out all disabled + * interrupts. + */ + + diepint = stm32_getreg(STM32_OTGHS_DIEPINT(epno)) & mask; + + /* Decode and process the enabled, pending interrupts */ + + /* Transfer completed interrupt */ + + if ((diepint & OTGHS_DIEPINT_XFRC) != 0) + { + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPIN_XFRC), + (uint16_t)diepint); + + /* It is possible that logic may be waiting for a the + * TxFIFO to become empty. We disable the TxFIFO empty + * interrupt here; it will be re-enabled if there is still + * insufficient space in the TxFIFO. + */ + + empty &= ~OTGHS_DIEPEMPMSK(epno); + stm32_putreg(empty, STM32_OTGHS_DIEPEMPMSK); + stm32_putreg(OTGHS_DIEPINT_XFRC, STM32_OTGHS_DIEPINT(epno)); + + /* IN transfer complete */ + + stm32_epin(priv, epno); + } + + /* Timeout condition */ + + if ((diepint & OTGHS_DIEPINT_TOC) != 0) + { + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPIN_TOC), + (uint16_t)diepint); + stm32_putreg(OTGHS_DIEPINT_TOC, STM32_OTGHS_DIEPINT(epno)); + } + + /* IN token received when TxFIFO is empty. Applies to non-periodic + * IN endpoints only. This interrupt indicates that an IN token + * was received when the associated TxFIFO (periodic/non-periodic) + * was empty. This interrupt is asserted on the endpoint for which + * the IN token was received. + */ + + if ((diepint & OTGHS_DIEPINT_ITTXFE) != 0) + { + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPIN_ITTXFE), + (uint16_t)diepint); + stm32_epin_request(priv, &priv->epin[epno]); + stm32_putreg(OTGHS_DIEPINT_ITTXFE, STM32_OTGHS_DIEPINT(epno)); + } + + /* IN endpoint NAK effective (ignored as this used only in polled + * mode) + */ +#if 0 + if ((diepint & OTGHS_DIEPINT_INEPNE) != 0) + { + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPIN_INEPNE), + (uint16_t)diepint); + stm32_putreg(OTGHS_DIEPINT_INEPNE, STM32_OTGHS_DIEPINT(epno)); + } +#endif + + /* Endpoint disabled interrupt (ignored as this used only in polled + * mode) + */ +#if 0 + if ((diepint & OTGHS_DIEPINT_EPDISD) != 0) + { + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPIN_EPDISD), + (uint16_t)diepint); + stm32_putreg(OTGHS_DIEPINT_EPDISD, STM32_OTGHS_DIEPINT(epno)); + } +#endif + + /* Transmit FIFO empty */ + + if ((diepint & OTGHS_DIEPINT_TXFE) != 0) + { + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPIN_TXFE), + (uint16_t)diepint); + + /* If we were waiting for TxFIFO to become empty, the we might + * have both XFRC and TXFE interrupts pending. Since we do the + * same thing for both cases, ignore the TXFE if we have + * already processed the XFRC. + */ + + if ((diepint & OTGHS_DIEPINT_XFRC) == 0) + { + /* Mask further FIFO empty interrupts. This will be + * re-enabled whenever we need to wait for a FIFO event. + */ + + empty &= ~OTGHS_DIEPEMPMSK(epno); + stm32_putreg(empty, STM32_OTGHS_DIEPEMPMSK); + + /* Handle TxFIFO empty */ + + stm32_epin_txfifoempty(priv, epno); + } + + /* Clear the pending TxFIFO empty interrupt */ + + stm32_putreg(OTGHS_DIEPINT_TXFE, STM32_OTGHS_DIEPINT(epno)); + } + } + + epno++; + daint >>= 1; + } +} + +/**************************************************************************** + * Name: stm32_resumeinterrupt + * + * Description: + * Resume/remote wakeup detected interrupt + * + ****************************************************************************/ + +static inline void stm32_resumeinterrupt(struct stm32_usbdev_s *priv) +{ + uint32_t regval; + + /* Restart the PHY clock and un-gate USB core clock (HCLK) */ + +#ifdef CONFIG_USBDEV_LOWPOWER + regval = stm32_getreg(STM32_OTGHS_PCGCCTL); + regval &= ~(OTGHS_PCGCCTL_STPPCLK | OTGHS_PCGCCTL_GATEHCLK); + stm32_putreg(regval, STM32_OTGHS_PCGCCTL); +#endif + + /* Clear remote wake-up signaling */ + + regval = stm32_getreg(STM32_OTGHS_DCTL); + regval &= ~OTGHS_DCTL_RWUSIG; + stm32_putreg(regval, STM32_OTGHS_DCTL); + + /* Restore full power -- whatever that means for this particular board */ + + stm32_usbsuspend((struct usbdev_s *)priv, true); + + /* Notify the class driver of the resume event */ + + if (priv->driver) + { + CLASS_RESUME(priv->driver, &priv->usbdev); + } +} + +/**************************************************************************** + * Name: stm32_suspendinterrupt + * + * Description: + * USB suspend interrupt + * + ****************************************************************************/ + +static inline void stm32_suspendinterrupt(struct stm32_usbdev_s *priv) +{ +#ifdef CONFIG_USBDEV_LOWPOWER + uint32_t regval; +#endif + + /* Notify the class driver of the suspend event */ + + if (priv->driver) + { + CLASS_SUSPEND(priv->driver, &priv->usbdev); + } + +#ifdef CONFIG_USBDEV_LOWPOWER + /* OTGHS_DSTS_SUSPSTS is set as long as the suspend condition is detected + * on USB. Check if we are still have the suspend condition, that we are + * connected to the host, and that we have been configured. + */ + + regval = stm32_getreg(STM32_OTGHS_DSTS); + + if ((regval & OTGHS_DSTS_SUSPSTS) != 0 && devstate == DEVSTATE_CONFIGURED) + { + /* Switch off OTG HS clocking. Setting OTGHS_PCGCCTL_STPPCLK stops the + * PHY clock. + */ + + regval = stm32_getreg(STM32_OTGHS_PCGCCTL); + regval |= OTGHS_PCGCCTL_STPPCLK; + stm32_putreg(regval, STM32_OTGHS_PCGCCTL); + + /* Setting OTGHS_PCGCCTL_GATEHCLK gate HCLK to modules other than + * the AHB Slave and Master and wakeup logic. + */ + + regval |= OTGHS_PCGCCTL_GATEHCLK; + stm32_putreg(regval, STM32_OTGHS_PCGCCTL); + } +#endif + + /* Let the board-specific logic know that we have entered the suspend + * state + */ + + stm32_usbsuspend((struct usbdev_s *)priv, false); +} + +/**************************************************************************** + * Name: stm32_rxinterrupt + * + * Description: + * RxFIFO non-empty interrupt. This interrupt indicates that there is at + * least one packet pending to be read from the RxFIFO. + * + ****************************************************************************/ + +static inline void stm32_rxinterrupt(struct stm32_usbdev_s *priv) +{ + struct stm32_ep_s *privep; + uint32_t regval; + int bcnt; + int epphy; + + /* Disable the Rx status queue level interrupt */ + + regval = stm32_getreg(STM32_OTGHS_GINTMSK); + regval &= ~OTGHS_GINT_RXFLVL; + stm32_putreg(regval, STM32_OTGHS_GINTMSK); + + /* Get the status from the top of the FIFO */ + + regval = stm32_getreg(STM32_OTGHS_GRXSTSP); + + /* Decode status fields */ + + epphy = (regval & OTGHS_GRXSTSD_EPNUM_MASK) >> OTGHS_GRXSTSD_EPNUM_SHIFT; + + if (epphy < STM32_NENDPOINTS) + { + privep = &priv->epout[epphy]; + + /* Handle the RX event according to the packet status field */ + + switch (regval & OTGHS_GRXSTSD_PKTSTS_MASK) + { + /* Global OUT NAK. This indicate that the global OUT NAK bit has + * taken effect. + * + * PKTSTS = Global OUT NAK, BCNT = 0, + * EPNUM = Don't Care, DPID = Don't Care. + */ + + case OTGHS_GRXSTSD_PKTSTS_OUTNAK: + { + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_OUTNAK), 0); + } + break; + + /* OUT data packet received. + * + * PKTSTS = DataOUT, BCNT = size of the received data OUT packet, + * EPNUM = EPNUM on which the packet was received, + * DPID = Actual Data PID. + */ + + case OTGHS_GRXSTSD_PKTSTS_OUTRECVD: + { + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_OUTRECVD), epphy); + bcnt = (regval & OTGHS_GRXSTSD_BCNT_MASK) >> + OTGHS_GRXSTSD_BCNT_SHIFT; + if (bcnt > 0) + { + stm32_epout_receive(privep, bcnt); + } + } + break; + + /* OUT transfer completed. This indicates that an OUT data transfer + * for the specified OUT endpoint has completed. After this entry is + * popped from the receive FIFO, the core asserts a Transfer + * Completed interrupt on the specified OUT endpoint. + * + * PKTSTS = Data OUT Transfer Done, BCNT = 0, EPNUM = OUT EP Num on + * which the data transfer is complete, DPID = Don't Care. + */ + + case OTGHS_GRXSTSD_PKTSTS_OUTDONE: + { + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_OUTDONE), epphy); + } + break; + + /* SETUP transaction completed. This indicates that the Setup stage + * for the specified endpoint has completed and the Data stage has + * started. After this entry is popped from the receive FIFO, the + * core asserts a Setup interrupt on the specified control OUT + * endpoint (triggers an interrupt). + * + * PKTSTS = Setup Stage Done, BCNT = 0, EPNUM = Control EP Num, + * DPID = Don't Care. + */ + + case OTGHS_GRXSTSD_PKTSTS_SETUPDONE: + { + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SETUPDONE), epphy); + } + break; + + /* SETUP data packet received. This indicates that a SETUP packet + * for the specified endpoint is now available for reading from the + * receive FIFO. + * + * PKTSTS = SETUP, BCNT = 8, EPNUM = Control EP Num, DPID = D0. + */ + + case OTGHS_GRXSTSD_PKTSTS_SETUPRECVD: + { + uint16_t datlen; + + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SETUPRECVD), epphy); + + /* Read EP0 setup data. NOTE: If multiple SETUP packets are + * received, the last one overwrites the previous setup packets + * and only that last SETUP packet will be processed. + */ + + stm32_rxfifo_read(&priv->epout[EP0], + (uint8_t *)&priv->ctrlreq, + USB_SIZEOF_CTRLREQ); + + /* Was this an IN or an OUT SETUP packet. If it is an OUT SETUP, + * then we need to wait for the completion of the data phase to + * process the setup command. If it is an IN SETUP packet, then + * we must processing the command BEFORE we enter the DATA phase. + * + * If the data associated with the OUT SETUP packet is zero + * length, then, of course, we don't need to wait. + */ + + datlen = GETUINT16(priv->ctrlreq.len); + if (USB_REQ_ISOUT(priv->ctrlreq.type) && datlen > 0) + { + /* Clear NAKSTS so that we can receive the data */ + + regval = stm32_getreg(STM32_OTGHS_DOEPCTL0); + regval |= OTGHS_DOEPCTL0_CNAK; + stm32_putreg(regval, STM32_OTGHS_DOEPCTL0); + + /* Wait for the data phase. */ + + priv->ep0state = EP0STATE_SETUP_OUT; + } + else + { + /* We can process the setup data as soon as SETUP done word + * is popped of the RxFIFO. + */ + + priv->ep0state = EP0STATE_SETUP_READY; + } + } + break; + + default: + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), + (regval & OTGHS_GRXSTSD_PKTSTS_MASK) + >> OTGHS_GRXSTSD_PKTSTS_SHIFT); + } + break; + } + } + + /* Enable the Rx Status Queue Level interrupt */ + + regval = stm32_getreg(STM32_OTGHS_GINTMSK); + regval |= OTGHS_GINT_RXFLVL; + stm32_putreg(regval, STM32_OTGHS_GINTMSK); +} + +/**************************************************************************** + * Name: stm32_enuminterrupt + * + * Description: + * Enumeration done interrupt + * + ****************************************************************************/ + +static inline void stm32_enuminterrupt(struct stm32_usbdev_s *priv) +{ + uint32_t regval; + + /* Activate EP0 */ + + stm32_ep0in_activate(); + + /* Set USB turn-around time for the full speed device with internal PHY + * interface. + */ + + regval = stm32_getreg(STM32_OTGHS_GUSBCFG); + regval &= ~OTGHS_GUSBCFG_TRDT_MASK; + regval |= OTGHS_GUSBCFG_TRDT(5); + stm32_putreg(regval, STM32_OTGHS_GUSBCFG); +} + +/**************************************************************************** + * Name: stm32_isocininterrupt + * + * Description: + * Incomplete isochronous IN transfer interrupt. Assertion of the + * incomplete isochronous IN transfer interrupt indicates an incomplete + * isochronous IN transfer on at least one of the isochronous IN endpoints. + * + ****************************************************************************/ + +#ifdef CONFIG_USBDEV_ISOCHRONOUS +static inline void stm32_isocininterrupt(struct stm32_usbdev_s *priv) +{ + int i; + + /* The application must read the endpoint control register for all + * isochronous IN endpoints to detect endpoints with incomplete IN data + * transfers. + */ + + for (i = 0; i < STM32_NENDPOINTS; i++) + { + /* Is this an isochronous IN endpoint? */ + + privep = &priv->epin[i]; + if (privep->eptype != USB_EP_ATTR_XFER_ISOC) + { + /* No... keep looking */ + + continue; + } + + /* Is there an active read request on the isochronous OUT endpoint? */ + + if (!privep->active) + { + /* No.. the endpoint is not actively transmitting data */ + + continue; + } + + /* Check if this is the endpoint that had the incomplete transfer */ + + regaddr = STM32_OTGHS_DIEPCTL(privep->epphy); + doepctl = stm32_getreg(regaddr); + dsts = stm32_getreg(STM32_OTGHS_DSTS); + + /* EONUM = 0:even frame, 1:odd frame + * SOFFN = Frame number of the received SOF + */ + + eonum = ((doepctl & OTGHS_DIEPCTL_EONUM) != 0); + soffn = ((dsts & OTGHS_DSTS_SOFFN0) != 0); + + if (eonum != soffn) + { + /* Not this endpoint */ + + continue; + } + + /* For isochronous IN endpoints with incomplete transfers, + * the application must discard the data in the memory and + * disable the endpoint. + */ + + stm32_req_complete(privep, -EIO); +#warning "Will clear OTGHS_DIEPCTL_USBAEP too" + stm32_epin_disable(privep); + break; + } +} +#endif + +/**************************************************************************** + * Name: stm32_isocoutinterrupt + * + * Description: + * Incomplete periodic transfer interrupt + * + ****************************************************************************/ + +#ifdef CONFIG_USBDEV_ISOCHRONOUS +static inline void stm32_isocoutinterrupt(struct stm32_usbdev_s *priv) +{ + struct stm32_ep_s *privep; + struct stm32_req_s *privreq; + uint32_t regaddr; + uint32_t doepctl; + uint32_t dsts; + bool eonum; + bool soffn; + + /* When it receives an IISOOXFR interrupt, the application must read the + * control registers of all isochronous OUT endpoints to determine which + * endpoints had an incomplete transfer in the current microframe. An + * endpoint transfer is incomplete if both the following conditions are + * true: + * + * DOEPCTLx:EONUM = DSTS:SOFFN[0], and + * DOEPCTLx:EPENA = 1 + */ + + for (i = 0; i < STM32_NENDPOINTS; i++) + { + /* Is this an isochronous OUT endpoint? */ + + privep = &priv->epout[i]; + if (privep->eptype != USB_EP_ATTR_XFER_ISOC) + { + /* No... keep looking */ + + continue; + } + + /* Is there an active read request on the isochronous OUT endpoint? */ + + if (!privep->active) + { + /* No.. the endpoint is not actively transmitting data */ + + continue; + } + + /* Check if this is the endpoint that had the incomplete transfer */ + + regaddr = STM32_OTGHS_DOEPCTL(privep->epphy); + doepctl = stm32_getreg(regaddr); + dsts = stm32_getreg(STM32_OTGHS_DSTS); + + /* EONUM = 0:even frame, 1:odd frame + * SOFFN = Frame number of the received SOF + */ + + eonum = ((doepctl & OTGHS_DOEPCTL_EONUM) != 0); + soffn = ((dsts & OTGHS_DSTS_SOFFN0) != 0); + + if (eonum != soffn) + { + /* Not this endpoint */ + + continue; + } + + /* For isochronous OUT endpoints with incomplete transfers, + * the application must discard the data in the memory and + * disable the endpoint. + */ + + stm32_req_complete(privep, -EIO); +#warning "Will clear OTGHS_DOEPCTL_USBAEP too" + stm32_epout_disable(privep); + break; + } +} +#endif + +/**************************************************************************** + * Name: stm32_sessioninterrupt + * + * Description: + * Session request/new session detected interrupt + * + ****************************************************************************/ + +#ifdef CONFIG_USBDEV_VBUSSENSING +static inline void stm32_sessioninterrupt(struct stm32_usbdev_s *priv) +{ +#warning "Missing logic" +} +#endif + +/**************************************************************************** + * Name: stm32_otginterrupt + * + * Description: + * OTG interrupt + * + ****************************************************************************/ + +#ifdef CONFIG_USBDEV_VBUSSENSING +static inline void stm32_otginterrupt(struct stm32_usbdev_s *priv) +{ + uint32_t regval; + + /* Check for session end detected */ + + regval = stm32_getreg(STM32_OTGHS_GOTGINT); + if ((regval & OTGHS_GOTGINT_SEDET) != 0) + { +#warning "Missing logic" + } + + /* Clear OTG interrupt */ + + stm32_putreg(retval, STM32_OTGHS_GOTGINT); +} +#endif + +/**************************************************************************** + * Name: stm32_usbinterrupt + * + * Description: + * USB interrupt handler + * + ****************************************************************************/ + +static int stm32_usbinterrupt(int irq, void *context, void *arg) +{ + /* At present, there is only a single OTG HS device support. Hence it is + * pre-allocated as g_otghsdev. However, in most code, the private data + * structure will be referenced using the 'priv' pointer (rather than the + * global data) in order to simplify any future support for multiple + * devices. + */ + + struct stm32_usbdev_s *priv = &g_otghsdev; + uint32_t regval; + + usbtrace(TRACE_INTENTRY(STM32_TRACEINTID_USB), 0); + + /* Assure that we are in device mode */ + + DEBUGASSERT((stm32_getreg(STM32_OTGHS_GINTSTS) & OTGHS_GINTSTS_CMOD) + == OTGHS_GINTSTS_DEVMODE); + + /* Get the state of all enabled interrupts. We will do this repeatedly + * some interrupts (like RXFLVL) will generate additional interrupting + * events. + */ + + for (; ; ) + { + /* Get the set of pending, un-masked interrupts */ + + regval = stm32_getreg(STM32_OTGHS_GINTSTS); + regval &= stm32_getreg(STM32_OTGHS_GINTMSK); + + /* Break out of the loop when there are no further pending (and + * unmasked) interrupts to be processes. + */ + + if (regval == 0) + { + break; + } + + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_INTPENDING), + (uint16_t)regval); + + /* OUT endpoint interrupt. The core sets this bit to indicate that an + * interrupt is pending on one of the OUT endpoints of the core. + */ + + if ((regval & OTGHS_GINT_OEP) != 0) + { + usbtrace( + TRACE_INTDECODE(STM32_TRACEINTID_EPOUT), (uint16_t)regval); + stm32_epout_interrupt(priv); + stm32_putreg(OTGHS_GINT_OEP, STM32_OTGHS_GINTSTS); + } + + /* IN endpoint interrupt. The core sets this bit to indicate that + * an interrupt is pending on one of the IN endpoints of the core. + */ + + if ((regval & OTGHS_GINT_IEP) != 0) + { + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPIN), (uint16_t)regval); + stm32_epin_interrupt(priv); + stm32_putreg(OTGHS_GINT_IEP, STM32_OTGHS_GINTSTS); + } + + /* Host/device mode mismatch error interrupt */ + +#ifdef CONFIG_DEBUG_USB + if ((regval & OTGHS_GINT_MMIS) != 0) + { + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_MISMATCH), + (uint16_t)regval); + stm32_putreg(OTGHS_GINT_MMIS, STM32_OTGHS_GINTSTS); + } +#endif + + /* Resume/remote wakeup detected interrupt */ + + if ((regval & OTGHS_GINT_WKUP) != 0) + { + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_WAKEUP), + (uint16_t)regval); + stm32_resumeinterrupt(priv); + stm32_putreg(OTGHS_GINT_WKUP, STM32_OTGHS_GINTSTS); + } + + /* USB suspend interrupt */ + + if ((regval & OTGHS_GINT_USBSUSP) != 0) + { + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SUSPEND), + (uint16_t)regval); + stm32_suspendinterrupt(priv); + stm32_putreg(OTGHS_GINT_USBSUSP, STM32_OTGHS_GINTSTS); + } + + /* Start of frame interrupt */ + +#ifdef CONFIG_USBDEV_SOFINTERRUPT + if ((regval & OTGHS_GINT_SOF) != 0) + { + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SOF), (uint16_t)regval); + stm32_putreg(OTGHS_GINT_SOF, STM32_OTGHS_GINTSTS); + } +#endif + + /* RxFIFO non-empty interrupt. Indicates that there is at least one + * packet pending to be read from the RxFIFO. + */ + + if ((regval & OTGHS_GINT_RXFLVL) != 0) + { + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_RXFIFO), + (uint16_t)regval); + stm32_rxinterrupt(priv); + stm32_putreg(OTGHS_GINT_RXFLVL, STM32_OTGHS_GINTSTS); + } + + /* USB reset interrupt */ + + if ((regval & OTGHS_GINT_USBRST) != 0) + { + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_DEVRESET), + (uint16_t)regval); + + /* Perform the device reset */ + + stm32_usbreset(priv); + usbtrace(TRACE_INTEXIT(STM32_TRACEINTID_USB), 0); + stm32_putreg(OTGHS_GINT_USBRST, STM32_OTGHS_GINTSTS); + return OK; + } + + /* Enumeration done interrupt */ + + if ((regval & OTGHS_GINT_ENUMDNE) != 0) + { + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_ENUMDNE), + (uint16_t)regval); + stm32_enuminterrupt(priv); + stm32_putreg(OTGHS_GINT_ENUMDNE, STM32_OTGHS_GINTSTS); + } + + /* Incomplete isochronous IN transfer interrupt. When the core finds + * non-empty any of the isochronous IN endpoint FIFOs scheduled for + * the current frame non-empty, the core generates an IISOIXFR + * interrupt. + */ + +#ifdef CONFIG_USBDEV_ISOCHRONOUS + if ((regval & OTGHS_GINT_IISOIXFR) != 0) + { + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_IISOIXFR), + (uint16_t)regval); + stm32_isocininterrupt(priv); + stm32_putreg(OTGHS_GINT_IISOIXFR, STM32_OTGHS_GINTSTS); + } + + /* Incomplete isochronous OUT transfer. For isochronous OUT + * endpoints, the XFRC interrupt may not always be asserted. If the + * core drops isochronous OUT data packets, the application could fail + * to detect the XFRC interrupt. The incomplete Isochronous OUT data + * interrupt indicates that an XFRC interrupt was not asserted on at + * least one of the isochronous OUT endpoints. At this point, the + * endpoint with the incomplete transfer remains enabled, but no active + * transfers remain in progress on this endpoint on the USB. + */ + + if ((regval & OTGHS_GINT_IISOOXFR) != 0) + { + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_IISOOXFR), + (uint16_t)regval); + stm32_isocoutinterrupt(priv); + stm32_putreg(OTGHS_GINT_IISOOXFR, STM32_OTGHS_GINTSTS); + } +#endif + + /* Session request/new session detected interrupt */ + +#ifdef CONFIG_USBDEV_VBUSSENSING + if ((regval & OTGHS_GINT_SRQ) != 0) + { + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SRQ), (uint16_t)regval); + stm32_sessioninterrupt(priv); + stm32_putreg(OTGHS_GINT_SRQ, STM32_OTGHS_GINTSTS); + } + + /* OTG interrupt */ + + if ((regval & OTGHS_GINT_OTG) != 0) + { + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_OTG), (uint16_t)regval); + stm32_otginterrupt(priv); + stm32_putreg(OTGHS_GINT_OTG, STM32_OTGHS_GINTSTS); + } +#endif + } + + usbtrace(TRACE_INTEXIT(STM32_TRACEINTID_USB), 0); + return OK; +} + +/**************************************************************************** + * Endpoint operations + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_enablegonak + * + * Description: + * Enable global OUT NAK mode + * + ****************************************************************************/ + +static void stm32_enablegonak(struct stm32_ep_s *privep) +{ + uint32_t regval; + + /* First, make sure that there is no GNOAKEFF interrupt pending. */ + +#if 0 + stm32_putreg(OTGHS_GINT_GONAKEFF, STM32_OTGHS_GINTSTS); +#endif + + /* Enable Global OUT NAK mode in the core. */ + + regval = stm32_getreg(STM32_OTGHS_DCTL); + regval |= OTGHS_DCTL_SGONAK; + stm32_putreg(regval, STM32_OTGHS_DCTL); + +#if 0 + /* Wait for the GONAKEFF interrupt that indicates that the OUT NAK + * mode is in effect. When the interrupt handler pops the OUTNAK word + * from the RxFIFO, the core sets the GONAKEFF interrupt. + */ + + while ((stm32_getreg(STM32_OTGHS_GINTSTS) & OTGHS_GINT_GONAKEFF) == 0); + stm32_putreg(OTGHS_GINT_GONAKEFF, STM32_OTGHS_GINTSTS); + +#else + /* Since we are in the interrupt handler, we cannot wait inline for the + * GONAKEFF because it cannot occur until service the RXFLVL global + * interrupt and pop the OUTNAK word from the RxFIFO. + * + * Perhaps it is sufficient to wait for Global OUT NAK status to be + * reported in OTGHS DCTL register? + */ + + while ((stm32_getreg(STM32_OTGHS_DCTL) & OTGHS_DCTL_GONSTS) == 0); +#endif +} + +/**************************************************************************** + * Name: stm32_disablegonak + * + * Description: + * Disable global OUT NAK mode + * + ****************************************************************************/ + +static void stm32_disablegonak(struct stm32_ep_s *privep) +{ + uint32_t regval; + + /* Set the "Clear the Global OUT NAK bit" to disable global OUT NAK mode */ + + regval = stm32_getreg(STM32_OTGHS_DCTL); + regval |= OTGHS_DCTL_CGONAK; + stm32_putreg(regval, STM32_OTGHS_DCTL); +} + +/**************************************************************************** + * Name: stm32_epout_configure + * + * Description: + * Configure an OUT endpoint, making it usable + * + * Input Parameters: + * privep - a pointer to an internal endpoint structure + * eptype - The type of the endpoint + * maxpacket - The max packet size of the endpoint + * + ****************************************************************************/ + +static int stm32_epout_configure(struct stm32_ep_s *privep, + uint8_t eptype, uint16_t maxpacket) +{ + uint32_t mpsiz; + uint32_t regaddr; + uint32_t regval; + + usbtrace(TRACE_EPCONFIGURE, privep->epphy); + + /* For EP0, the packet size is encoded */ + + if (privep->epphy == EP0) + { + DEBUGASSERT(eptype == USB_EP_ATTR_XFER_CONTROL); + + /* Map the size in bytes to the encoded value in the register */ + + switch (maxpacket) + { + case 8: + mpsiz = OTGHS_DOEPCTL0_MPSIZ_8; + break; + + case 16: + mpsiz = OTGHS_DOEPCTL0_MPSIZ_16; + break; + + case 32: + mpsiz = OTGHS_DOEPCTL0_MPSIZ_32; + break; + + case 64: + mpsiz = OTGHS_DOEPCTL0_MPSIZ_64; + break; + + default: + uerr("ERROR: Unsupported maxpacket: %d\n", maxpacket); + return -EINVAL; + } + } + + /* For other endpoints, the packet size is in bytes */ + + else + { + mpsiz = (maxpacket << OTGHS_DOEPCTL_MPSIZ_SHIFT); + } + + /* If the endpoint is already active don't change the endpoint control + * register. + */ + + regaddr = STM32_OTGHS_DOEPCTL(privep->epphy); + regval = stm32_getreg(regaddr); + if ((regval & OTGHS_DOEPCTL_USBAEP) == 0) + { + if (regval & OTGHS_DOEPCTL_NAKSTS) + { + regval |= OTGHS_DOEPCTL_CNAK; + } + + regval &= ~(OTGHS_DOEPCTL_MPSIZ_MASK | OTGHS_DOEPCTL_EPTYP_MASK); + regval |= mpsiz; + regval |= (eptype << OTGHS_DOEPCTL_EPTYP_SHIFT); + regval |= (OTGHS_DOEPCTL_SD0PID | OTGHS_DOEPCTL_USBAEP); + stm32_putreg(regval, regaddr); + + /* Save the endpoint configuration */ + + privep->ep.maxpacket = maxpacket; + privep->eptype = eptype; + privep->stalled = false; + } + + /* Enable the interrupt for this endpoint */ + + regval = stm32_getreg(STM32_OTGHS_DAINTMSK); + regval |= OTGHS_DAINT_OEP(privep->epphy); + stm32_putreg(regval, STM32_OTGHS_DAINTMSK); + return OK; +} + +/**************************************************************************** + * Name: stm32_epin_configure + * + * Description: + * Configure an IN endpoint, making it usable + * + * Input Parameters: + * privep - a pointer to an internal endpoint structure + * eptype - The type of the endpoint + * maxpacket - The max packet size of the endpoint + * + ****************************************************************************/ + +static int stm32_epin_configure(struct stm32_ep_s *privep, + uint8_t eptype, uint16_t maxpacket) +{ + uint32_t mpsiz; + uint32_t regaddr; + uint32_t regval; + + usbtrace(TRACE_EPCONFIGURE, privep->epphy); + + /* For EP0, the packet size is encoded */ + + if (privep->epphy == EP0) + { + DEBUGASSERT(eptype == USB_EP_ATTR_XFER_CONTROL); + + /* Map the size in bytes to the encoded value in the register */ + + switch (maxpacket) + { + case 8: + mpsiz = OTGHS_DIEPCTL0_MPSIZ_8; + break; + + case 16: + mpsiz = OTGHS_DIEPCTL0_MPSIZ_16; + break; + + case 32: + mpsiz = OTGHS_DIEPCTL0_MPSIZ_32; + break; + + case 64: + mpsiz = OTGHS_DIEPCTL0_MPSIZ_64; + break; + + default: + uerr("ERROR: Unsupported maxpacket: %d\n", maxpacket); + return -EINVAL; + } + } + + /* For other endpoints, the packet size is in bytes */ + + else + { + mpsiz = (maxpacket << OTGHS_DIEPCTL_MPSIZ_SHIFT); + } + + /* If the endpoint is already active don't change the endpoint control + * register. + */ + + regaddr = STM32_OTGHS_DIEPCTL(privep->epphy); + regval = stm32_getreg(regaddr); + if ((regval & OTGHS_DIEPCTL_USBAEP) == 0) + { + if (regval & OTGHS_DIEPCTL_NAKSTS) + { + regval |= OTGHS_DIEPCTL_CNAK; + } + + regval &= ~(OTGHS_DIEPCTL_MPSIZ_MASK | + OTGHS_DIEPCTL_EPTYP_MASK | + OTGHS_DIEPCTL_TXFNUM_MASK); + regval |= mpsiz; + regval |= (eptype << OTGHS_DIEPCTL_EPTYP_SHIFT); + regval |= (privep->epphy << OTGHS_DIEPCTL_TXFNUM_SHIFT); + regval |= (OTGHS_DIEPCTL_SD0PID | OTGHS_DIEPCTL_USBAEP); + stm32_putreg(regval, regaddr); + + /* Save the endpoint configuration */ + + privep->ep.maxpacket = maxpacket; + privep->eptype = eptype; + privep->stalled = false; + } + + /* Enable the interrupt for this endpoint */ + + regval = stm32_getreg(STM32_OTGHS_DAINTMSK); + regval |= OTGHS_DAINT_IEP(privep->epphy); + stm32_putreg(regval, STM32_OTGHS_DAINTMSK); + + return OK; +} + +/**************************************************************************** + * Name: stm32_ep_configure + * + * Description: + * Configure endpoint, making it usable + * + * Input Parameters: + * ep - the struct usbdev_ep_s instance obtained from allocep() + * desc - A struct usb_epdesc_s instance describing the endpoint + * last - true if this this last endpoint to be configured. Some hardware + * needs to take special action when all of the endpoints have been + * configured. + * + ****************************************************************************/ + +static int stm32_ep_configure(struct usbdev_ep_s *ep, + const struct usb_epdesc_s *desc, + bool last) +{ + struct stm32_ep_s *privep = (struct stm32_ep_s *)ep; + uint16_t maxpacket; + uint8_t eptype; + int ret; + + usbtrace(TRACE_EPCONFIGURE, privep->epphy); + DEBUGASSERT(desc->addr == ep->eplog); + + /* Initialize EP capabilities */ + + maxpacket = GETUINT16(desc->mxpacketsize); + eptype = desc->attr & USB_EP_ATTR_XFERTYPE_MASK; + + /* Setup Endpoint Control Register */ + + if (privep->isin) + { + ret = stm32_epin_configure(privep, eptype, maxpacket); + } + else + { + ret = stm32_epout_configure(privep, eptype, maxpacket); + } + + return ret; +} + +/**************************************************************************** + * Name: stm32_ep0_configure + * + * Description: + * Reset Usb engine + * + ****************************************************************************/ + +static void stm32_ep0_configure(struct stm32_usbdev_s *priv) +{ + /* Enable EP0 IN and OUT */ + + stm32_epin_configure(&priv->epin[EP0], USB_EP_ATTR_XFER_CONTROL, + CONFIG_USBDEV_EP0_MAXSIZE); + stm32_epout_configure(&priv->epout[EP0], USB_EP_ATTR_XFER_CONTROL, + CONFIG_USBDEV_EP0_MAXSIZE); +} + +/**************************************************************************** + * Name: stm32_epout_disable + * + * Description: + * Disable an OUT endpoint will no longer be used + * + ****************************************************************************/ + +static void stm32_epout_disable(struct stm32_ep_s *privep) +{ + uint32_t regaddr; + uint32_t regval; + irqstate_t flags; + + usbtrace(TRACE_EPDISABLE, privep->epphy); + + /* Is this an IN or an OUT endpoint */ + + /* Before disabling any OUT endpoint, the application must enable + * Global OUT NAK mode in the core. + */ + + flags = enter_critical_section(); + stm32_enablegonak(privep); + + /* Disable the required OUT endpoint by setting the EPDIS and SNAK bits + * int DOECPTL register. + */ + + regaddr = STM32_OTGHS_DOEPCTL(privep->epphy); + regval = stm32_getreg(regaddr); + regval &= ~OTGHS_DOEPCTL_USBAEP; + regval |= (OTGHS_DOEPCTL_EPDIS | OTGHS_DOEPCTL_SNAK); + stm32_putreg(regval, regaddr); + + /* Wait for the EPDISD interrupt which indicates that the OUT + * endpoint is completely disabled. + */ + +#if 0 /* Doesn't happen */ + regaddr = STM32_OTGHS_DOEPINT(privep->epphy); + while ((stm32_getreg(regaddr) & OTGHS_DOEPINT_EPDISD) == 0); +#else + /* REVISIT: */ + + up_udelay(10); +#endif + + /* Clear the EPDISD interrupt indication */ + + stm32_putreg(OTGHS_DOEPINT_EPDISD, STM32_OTGHS_DOEPINT(privep->epphy)); + + /* Then disable the Global OUT NAK mode to continue receiving data + * from other non-disabled OUT endpoints. + */ + + stm32_disablegonak(privep); + + /* Disable endpoint interrupts */ + + regval = stm32_getreg(STM32_OTGHS_DAINTMSK); + regval &= ~OTGHS_DAINT_OEP(privep->epphy); + stm32_putreg(regval, STM32_OTGHS_DAINTMSK); + + /* Cancel any queued read requests */ + + stm32_req_cancel(privep, -ESHUTDOWN); + + leave_critical_section(flags); +} + +/**************************************************************************** + * Name: stm32_epin_disable + * + * Description: + * Disable an IN endpoint when it will no longer be used + * + ****************************************************************************/ + +static void stm32_epin_disable(struct stm32_ep_s *privep) +{ + uint32_t regaddr; + uint32_t regval; + irqstate_t flags; + + usbtrace(TRACE_EPDISABLE, privep->epphy); + + /* After USB reset, the endpoint will already be deactivated by the + * hardware. Trying to disable again will just hang in the wait. + */ + + regaddr = STM32_OTGHS_DIEPCTL(privep->epphy); + regval = stm32_getreg(regaddr); + if ((regval & OTGHS_DIEPCTL_USBAEP) == 0) + { + return; + } + + /* This INEPNE wait logic is suggested by reference manual, but seems + * to get stuck to infinite loop. + */ + +#if 0 + /* Make sure that there is no pending IPEPNE interrupt (because we are + * to poll this bit below). + */ + + stm32_putreg(OTGHS_DIEPINT_INEPNE, STM32_OTGHS_DIEPINT(privep->epphy)); + + /* Set the endpoint in NAK mode */ + + regaddr = STM32_OTGHS_DIEPCTL(privep->epphy); + regval = stm32_getreg(regaddr); + regval &= ~OTGHS_DIEPCTL_USBAEP; + regval |= (OTGHS_DIEPCTL_EPDIS | OTGHS_DIEPCTL_SNAK); + stm32_putreg(regval, regaddr); + + /* Wait for the INEPNE interrupt that indicates that we are now in NAK mode + */ + + regaddr = STM32_OTGHS_DIEPINT(privep->epphy); + while ((stm32_getreg(regaddr) & OTGHS_DIEPINT_INEPNE) == 0); + + /* Clear the INEPNE interrupt indication */ + + stm32_putreg(OTGHS_DIEPINT_INEPNE, regaddr); +#endif + + /* Deactivate and disable the endpoint by setting the EPDIS and SNAK bits + * the DIEPCTLx register. + */ + + flags = enter_critical_section(); + regaddr = STM32_OTGHS_DIEPCTL(privep->epphy); + regval = stm32_getreg(regaddr); + regval &= ~OTGHS_DIEPCTL_USBAEP; + regval |= (OTGHS_DIEPCTL_EPDIS | OTGHS_DIEPCTL_SNAK); + stm32_putreg(regval, regaddr); + + /* Wait for the EPDISD interrupt which indicates that the IN + * endpoint is completely disabled. + */ + + regaddr = STM32_OTGHS_DIEPINT(privep->epphy); + while ((stm32_getreg(regaddr) & OTGHS_DIEPINT_EPDISD) == 0); + + /* Clear the EPDISD interrupt indication */ + + stm32_putreg(OTGHS_DIEPINT_EPDISD, stm32_getreg(regaddr)); + + /* Flush any data remaining in the TxFIFO */ + + stm32_txfifo_flush(OTGHS_GRSTCTL_TXFNUM_D(privep->epphy)); + + /* Disable endpoint interrupts */ + + regval = stm32_getreg(STM32_OTGHS_DAINTMSK); + regval &= ~OTGHS_DAINT_IEP(privep->epphy); + stm32_putreg(regval, STM32_OTGHS_DAINTMSK); + + /* Cancel any queued write requests */ + + stm32_req_cancel(privep, -ESHUTDOWN); + leave_critical_section(flags); +} + +/**************************************************************************** + * Name: stm32_ep_disable + * + * Description: + * The endpoint will no longer be used + * + ****************************************************************************/ + +static int stm32_ep_disable(struct usbdev_ep_s *ep) +{ + struct stm32_ep_s *privep = (struct stm32_ep_s *)ep; + +#ifdef CONFIG_DEBUG_FEATURES + if (!ep) + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); + return -EINVAL; + } +#endif + + usbtrace(TRACE_EPDISABLE, privep->epphy); + + /* Is this an IN or an OUT endpoint */ + + if (privep->isin) + { + /* Disable the IN endpoint */ + + stm32_epin_disable(privep); + } + else + { + /* Disable the OUT endpoint */ + + stm32_epout_disable(privep); + } + + return OK; +} + +/**************************************************************************** + * Name: stm32_ep_allocreq + * + * Description: + * Allocate an I/O request + * + ****************************************************************************/ + +static struct usbdev_req_s *stm32_ep_allocreq(struct usbdev_ep_s *ep) +{ + struct stm32_req_s *privreq; + +#ifdef CONFIG_DEBUG_FEATURES + if (!ep) + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); + return NULL; + } +#endif + + usbtrace(TRACE_EPALLOCREQ, ((struct stm32_ep_s *)ep)->epphy); + + privreq = kmm_malloc(sizeof(struct stm32_req_s)); + if (!privreq) + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_ALLOCFAIL), 0); + return NULL; + } + + memset(privreq, 0, sizeof(struct stm32_req_s)); + return &privreq->req; +} + +/**************************************************************************** + * Name: stm32_ep_freereq + * + * Description: + * Free an I/O request + * + ****************************************************************************/ + +static void stm32_ep_freereq(struct usbdev_ep_s *ep, + struct usbdev_req_s *req) +{ + struct stm32_req_s *privreq = (struct stm32_req_s *)req; + +#ifdef CONFIG_DEBUG_FEATURES + if (!ep || !req) + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); + return; + } +#endif + + usbtrace(TRACE_EPFREEREQ, ((struct stm32_ep_s *)ep)->epphy); + kmm_free(privreq); +} + +/**************************************************************************** + * Name: stm32_ep_allocbuffer + * + * Description: + * Allocate an I/O buffer + * + ****************************************************************************/ + +#ifdef CONFIG_USBDEV_DMA +static void *stm32_ep_allocbuffer(struct usbdev_ep_s *ep, uint16_t bytes) +{ + usbtrace(TRACE_EPALLOCBUFFER, ((struct stm32_ep_s *)ep)->epphy); + +#ifdef CONFIG_USBDEV_DMAMEMORY + return usbdev_dma_alloc(bytes); +#else + return kmm_malloc(bytes); +#endif +} +#endif + +/**************************************************************************** + * Name: stm32_ep_freebuffer + * + * Description: + * Free an I/O buffer + * + ****************************************************************************/ + +#ifdef CONFIG_USBDEV_DMA +static void stm32_ep_freebuffer(struct usbdev_ep_s *ep, void *buf) +{ + usbtrace(TRACE_EPFREEBUFFER, ((struct stm32_ep_s *)ep)->epphy); + +#ifdef CONFIG_USBDEV_DMAMEMORY + usbdev_dma_free(buf); +#else + kmm_free(buf); +#endif +} +#endif + +/**************************************************************************** + * Name: stm32_ep_submit + * + * Description: + * Submit an I/O request to the endpoint + * + ****************************************************************************/ + +static int stm32_ep_submit(struct usbdev_ep_s *ep, + struct usbdev_req_s *req) +{ + struct stm32_req_s *privreq = (struct stm32_req_s *)req; + struct stm32_ep_s *privep = (struct stm32_ep_s *)ep; + struct stm32_usbdev_s *priv; + irqstate_t flags; + int ret = OK; + + /* Some sanity checking */ + +#ifdef CONFIG_DEBUG_FEATURES + if (!req || !req->callback || !req->buf || !ep) + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); + uinfo("req=%p callback=%p buf=%p ep=%p\n", + req, req->callback, req->buf, ep); + return -EINVAL; + } +#endif + + usbtrace(TRACE_EPSUBMIT, privep->epphy); + priv = privep->dev; + +#ifdef CONFIG_DEBUG_FEATURES + if (!priv->driver) + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_NOTCONFIGURED), + priv->usbdev.speed); + return -ESHUTDOWN; + } +#endif + + /* Handle the request from the class driver */ + + req->result = -EINPROGRESS; + req->xfrd = 0; + + /* Disable Interrupts */ + + flags = enter_critical_section(); + + /* If we are stalled, then drop all requests on the floor */ + + if (privep->stalled) + { + ret = -EBUSY; + } + else + { + /* Add the new request to the request queue for the endpoint. */ + + if (stm32_req_addlast(privep, privreq) && !privep->active) + { + /* If a request was added to an IN endpoint, then attempt to send + * the request data buffer now. + */ + + if (privep->isin) + { + usbtrace(TRACE_INREQQUEUED(privep->epphy), privreq->req.len); + + /* If the endpoint is not busy with another write request, + * then process the newly received write request now. + */ + + if (!privep->active) + { + stm32_epin_request(priv, privep); + } + } + + /* If the request was added to an OUT endpoint, then attempt to + * setup a read into the request data buffer now (this will, of + * course, fail if there is already a read in place). + */ + + else + { + usbtrace(TRACE_OUTREQQUEUED(privep->epphy), privreq->req.len); + stm32_epout_request(priv, privep); + } + } + } + + leave_critical_section(flags); + return ret; +} + +/**************************************************************************** + * Name: stm32_ep_cancel + * + * Description: + * Cancel an I/O request previously sent to an endpoint + * + ****************************************************************************/ + +static int stm32_ep_cancel(struct usbdev_ep_s *ep, + struct usbdev_req_s *req) +{ + struct stm32_ep_s *privep = (struct stm32_ep_s *)ep; + irqstate_t flags; + +#ifdef CONFIG_DEBUG_FEATURES + if (!ep || !req) + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); + return -EINVAL; + } +#endif + + usbtrace(TRACE_EPCANCEL, privep->epphy); + + flags = enter_critical_section(); + + /* FIXME: if the request is the first, then we need to flush the EP + * otherwise just remove it from the list + * + * but ... all other implementations cancel all requests ... + */ + + stm32_req_cancel(privep, -ESHUTDOWN); + leave_critical_section(flags); + return OK; +} + +/**************************************************************************** + * Name: stm32_epout_setstall + * + * Description: + * Stall an OUT endpoint + * + ****************************************************************************/ + +static int stm32_epout_setstall(struct stm32_ep_s *privep) +{ +#if 1 + /* This implementation follows the requirements from the STM32 F4 reference + * manual. + */ + + uint32_t regaddr; + uint32_t regval; + + /* Put the core in the Global OUT NAK mode */ + + stm32_enablegonak(privep); + + /* Disable and STALL the OUT endpoint by setting the EPDIS and STALL bits + * in the DOECPTL register. + */ + + regaddr = STM32_OTGHS_DOEPCTL(privep->epphy); + regval = stm32_getreg(regaddr); + regval |= (OTGHS_DOEPCTL_EPDIS | OTGHS_DOEPCTL_STALL); + stm32_putreg(regval, regaddr); + + /* Wait for the EPDISD interrupt which indicates that the OUT + * endpoint is completely disabled. + */ + +#if 0 /* Doesn't happen */ + regaddr = STM32_OTGHS_DOEPINT(privep->epphy); + while ((stm32_getreg(regaddr) & OTGHS_DOEPINT_EPDISD) == 0); +#else + /* REVISIT: */ + + up_udelay(10); +#endif + + /* Disable Global OUT NAK mode */ + + stm32_disablegonak(privep); + + /* The endpoint is now stalled */ + + privep->stalled = true; + return OK; +#else + /* This implementation follows the STMicro code example. */ + + /* REVISIT: */ + + uint32_t regaddr; + uint32_t regval; + + /* Stall the OUT endpoint by setting the STALL bit in the DOECPTL register. + */ + + regaddr = STM32_OTGHS_DOEPCTL(privep->epphy); + regval = stm32_getreg(regaddr); + regval |= OTGHS_DOEPCTL_STALL; + stm32_putreg(regval, regaddr); + + /* The endpoint is now stalled */ + + privep->stalled = true; + return OK; +#endif +} + +/**************************************************************************** + * Name: stm32_epin_setstall + * + * Description: + * Stall an IN endpoint + * + ****************************************************************************/ + +static int stm32_epin_setstall(struct stm32_ep_s *privep) +{ + uint32_t regaddr; + uint32_t regval; + + /* Get the IN endpoint device control register */ + + regaddr = STM32_OTGHS_DIEPCTL(privep->epphy); + regval = stm32_getreg(regaddr); + + /* Then stall the endpoint */ + + regval |= OTGHS_DIEPCTL_STALL; + stm32_putreg(regval, regaddr); + + /* The endpoint is now stalled */ + + privep->stalled = true; + return OK; +} + +/**************************************************************************** + * Name: stm32_ep_setstall + * + * Description: + * Stall an endpoint + * + ****************************************************************************/ + +static int stm32_ep_setstall(struct stm32_ep_s *privep) +{ + usbtrace(TRACE_EPSTALL, privep->epphy); + + /* Is this an IN endpoint? */ + + if (privep->isin == 1) + { + return stm32_epin_setstall(privep); + } + else + { + return stm32_epout_setstall(privep); + } +} + +/**************************************************************************** + * Name: stm32_ep_clrstall + * + * Description: + * Resume a stalled endpoint + * + ****************************************************************************/ + +static int stm32_ep_clrstall(struct stm32_ep_s *privep) +{ + uint32_t regaddr; + uint32_t regval; + uint32_t stallbit; + uint32_t data0bit; + + usbtrace(TRACE_EPRESUME, privep->epphy); + + /* Is this an IN endpoint? */ + + if (privep->isin == 1) + { + /* Clear the stall bit in the IN endpoint device control register */ + + regaddr = STM32_OTGHS_DIEPCTL(privep->epphy); + stallbit = OTGHS_DIEPCTL_STALL; + data0bit = OTGHS_DIEPCTL_SD0PID; + } + else + { + /* Clear the stall bit in the IN endpoint device control register */ + + regaddr = STM32_OTGHS_DOEPCTL(privep->epphy); + stallbit = OTGHS_DOEPCTL_STALL; + data0bit = OTGHS_DOEPCTL_SD0PID; + } + + /* Clear the stall bit */ + + regval = stm32_getreg(regaddr); + regval &= ~stallbit; + + /* Set the DATA0 pid for interrupt and bulk endpoints */ + + if (privep->eptype == USB_EP_ATTR_XFER_INT || + privep->eptype == USB_EP_ATTR_XFER_BULK) + { + /* Writing this bit sets the DATA0 PID */ + + regval |= data0bit; + } + + stm32_putreg(regval, regaddr); + + /* The endpoint is no longer stalled */ + + privep->stalled = false; + return OK; +} + +/**************************************************************************** + * Name: stm32_ep_stall + * + * Description: + * Stall or resume an endpoint + * + ****************************************************************************/ + +static int stm32_ep_stall(struct usbdev_ep_s *ep, bool resume) +{ + struct stm32_ep_s *privep = (struct stm32_ep_s *)ep; + irqstate_t flags; + int ret; + + /* Set or clear the stall condition as requested */ + + flags = enter_critical_section(); + if (resume) + { + ret = stm32_ep_clrstall(privep); + } + else + { + ret = stm32_ep_setstall(privep); + } + + leave_critical_section(flags); + + return ret; +} + +/**************************************************************************** + * Name: stm32_ep0_stall + * + * Description: + * Stall endpoint 0 + * + ****************************************************************************/ + +static void stm32_ep0_stall(struct stm32_usbdev_s *priv) +{ + stm32_epin_setstall(&priv->epin[EP0]); + stm32_epout_setstall(&priv->epout[EP0]); + priv->stalled = true; + stm32_ep0out_ctrlsetup(priv); +} + +/**************************************************************************** + * Device operations + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_ep_alloc + * + * Description: + * Allocate an endpoint matching the parameters. + * + * Input Parameters: + * eplog - 7-bit logical endpoint number (direction bit ignored). Zero + * means that any endpoint matching the other requirements will + * suffice. The assigned endpoint can be found in the eplog + * field. + * in - true: IN (device-to-host) endpoint requested + * eptype - Endpoint type. One of {USB_EP_ATTR_XFER_ISOC, + * USB_EP_ATTR_XFER_BULK, USB_EP_ATTR_XFER_INT} + * + ****************************************************************************/ + +static struct usbdev_ep_s *stm32_ep_alloc(struct usbdev_s *dev, + uint8_t eplog, bool in, + uint8_t eptype) +{ + struct stm32_usbdev_s *priv = (struct stm32_usbdev_s *)dev; + uint8_t epavail; + irqstate_t flags; + int epphy; + int epno = 0; + + usbtrace(TRACE_DEVALLOCEP, (uint16_t)eplog); + + /* Ignore any direction bits in the logical address */ + + epphy = USB_EPNO(eplog); + + /* Get the set of available endpoints depending on the direction */ + + flags = enter_critical_section(); + epavail = priv->epavail[in]; + + /* A physical address of 0 means that any endpoint will do */ + + if (epphy > 0) + { + /* Otherwise, we will return the endpoint structure only for the + * requested 'logical' endpoint. All of the other checks will still + * be performed. + * + * First, verify that the logical endpoint is in the range supported by + * by the hardware. + */ + + if (epphy >= STM32_NENDPOINTS) + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADEPNO), (uint16_t)epphy); + return NULL; + } + + /* Remove all of the candidate endpoints from the bitset except for the + * this physical endpoint number. + */ + + epavail &= (1 << epphy); + } + + /* Is there an available endpoint? */ + + if (epavail) + { + /* Yes.. Select the lowest numbered endpoint in the set of available + * endpoints. + */ + + for (epno = 1; epno < STM32_NENDPOINTS; epno++) + { + uint8_t bit = 1 << epno; + if ((epavail & bit) != 0) + { + /* Mark the endpoint no longer available */ + + priv->epavail[in] &= ~(1 << epno); + + /* And return the pointer to the standard endpoint structure */ + + leave_critical_section(flags); + return in ? &priv->epin[epno].ep : &priv->epout[epno].ep; + } + } + + /* We should not get here */ + } + + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_NOEP), (uint16_t)eplog); + leave_critical_section(flags); + return NULL; +} + +/**************************************************************************** + * Name: stm32_ep_free + * + * Description: + * Free the previously allocated endpoint + * + ****************************************************************************/ + +static void stm32_ep_free(struct usbdev_s *dev, + struct usbdev_ep_s *ep) +{ + struct stm32_usbdev_s *priv = (struct stm32_usbdev_s *)dev; + struct stm32_ep_s *privep = (struct stm32_ep_s *)ep; + irqstate_t flags; + + usbtrace(TRACE_DEVFREEEP, (uint16_t)privep->epphy); + + if (priv && privep) + { + /* Mark the endpoint as available */ + + flags = enter_critical_section(); + priv->epavail[privep->isin] |= (1 << privep->epphy); + leave_critical_section(flags); + } +} + +/**************************************************************************** + * Name: stm32_getframe + * + * Description: + * Returns the current frame number + * + ****************************************************************************/ + +static int stm32_getframe(struct usbdev_s *dev) +{ + uint32_t regval; + + usbtrace(TRACE_DEVGETFRAME, 0); + + /* Return the last frame number of the last SOF detected by the hardware */ + + regval = stm32_getreg(STM32_OTGHS_DSTS); + return (int)((regval & OTGHS_DSTS_SOFFN_MASK) >> OTGHS_DSTS_SOFFN_SHIFT); +} + +/**************************************************************************** + * Name: stm32_wakeup + * + * Description: + * Exit suspend mode. + * + ****************************************************************************/ + +static int stm32_wakeup(struct usbdev_s *dev) +{ + struct stm32_usbdev_s *priv = (struct stm32_usbdev_s *)dev; + uint32_t regval; + irqstate_t flags; + + usbtrace(TRACE_DEVWAKEUP, 0); + + /* Is wakeup enabled? */ + + flags = enter_critical_section(); + if (priv->wakeup) + { + /* Yes... is the core suspended? */ + + regval = stm32_getreg(STM32_OTGHS_DSTS); + if ((regval & OTGHS_DSTS_SUSPSTS) != 0) + { + /* Re-start the PHY clock and un-gate USB core clock (HCLK) */ + +#ifdef CONFIG_USBDEV_LOWPOWER + regval = stm32_getreg(STM32_OTGHS_PCGCCTL); + regval &= ~(OTGHS_PCGCCTL_STPPCLK | OTGHS_PCGCCTL_GATEHCLK); + stm32_putreg(regval, STM32_OTGHS_PCGCCTL); +#endif + /* Activate Remote wakeup signaling */ + + regval = stm32_getreg(STM32_OTGHS_DCTL); + regval |= OTGHS_DCTL_RWUSIG; + stm32_putreg(regval, STM32_OTGHS_DCTL); + up_mdelay(5); + regval &= ~OTGHS_DCTL_RWUSIG; + stm32_putreg(regval, STM32_OTGHS_DCTL); + } + } + + leave_critical_section(flags); + return OK; +} + +/**************************************************************************** + * Name: stm32_selfpowered + * + * Description: + * Sets/clears the device self-powered feature + * + ****************************************************************************/ + +static int stm32_selfpowered(struct usbdev_s *dev, bool selfpowered) +{ + struct stm32_usbdev_s *priv = (struct stm32_usbdev_s *)dev; + + usbtrace(TRACE_DEVSELFPOWERED, (uint16_t)selfpowered); + +#ifdef CONFIG_DEBUG_FEATURES + if (!dev) + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); + return -ENODEV; + } +#endif + + priv->selfpowered = selfpowered; + return OK; +} + +/**************************************************************************** + * Name: stm32_pullup + * + * Description: + * Software-controlled connect to/disconnect from USB host + * + ****************************************************************************/ + +static int stm32_pullup(struct usbdev_s *dev, bool enable) +{ + uint32_t regval; + + usbtrace(TRACE_DEVPULLUP, (uint16_t)enable); + + irqstate_t flags = enter_critical_section(); + regval = stm32_getreg(STM32_OTGHS_DCTL); + if (enable) + { + /* Connect the device by clearing the soft disconnect bit in the DCTL + * register + */ + + regval &= ~OTGHS_DCTL_SDIS; + } + else + { + /* Connect the device by setting the soft disconnect bit in the DCTL + * register + */ + + regval |= OTGHS_DCTL_SDIS; + } + + stm32_putreg(regval, STM32_OTGHS_DCTL); + leave_critical_section(flags); + return OK; +} + +/**************************************************************************** + * Name: stm32_setaddress + * + * Description: + * Set the devices USB address + * + ****************************************************************************/ + +static void stm32_setaddress(struct stm32_usbdev_s *priv, uint16_t address) +{ + uint32_t regval; + + /* Set the device address in the DCFG register */ + + regval = stm32_getreg(STM32_OTGHS_DCFG); + regval &= ~OTGHS_DCFG_DAD_MASK; + regval |= ((uint32_t)address << OTGHS_DCFG_DAD_SHIFT); + stm32_putreg(regval, STM32_OTGHS_DCFG); + + /* Are we now addressed? (i.e., do we have a non-NULL device + * address?) + */ + + if (address != 0) + { + priv->devstate = DEVSTATE_ADDRESSED; + priv->addressed = true; + } + else + { + priv->devstate = DEVSTATE_DEFAULT; + priv->addressed = false; + } +} + +/**************************************************************************** + * Name: stm32_txfifo_flush + * + * Description: + * Flush the specific TX fifo. + * + ****************************************************************************/ + +static int stm32_txfifo_flush(uint32_t txfnum) +{ + uint32_t regval; + uint32_t timeout; + + /* Initiate the TX FIFO flush operation */ + + regval = OTGHS_GRSTCTL_TXFFLSH | txfnum; + stm32_putreg(regval, STM32_OTGHS_GRSTCTL); + + /* Wait for the FLUSH to complete */ + + for (timeout = 0; timeout < STM32_FLUSH_DELAY; timeout++) + { + regval = stm32_getreg(STM32_OTGHS_GRSTCTL); + if ((regval & OTGHS_GRSTCTL_TXFFLSH) == 0) + { + break; + } + } + + /* Wait for 3 PHY Clocks */ + + up_udelay(3); + return OK; +} + +/**************************************************************************** + * Name: stm32_rxfifo_flush + * + * Description: + * Flush the RX fifo. + * + ****************************************************************************/ + +static int stm32_rxfifo_flush(void) +{ + uint32_t regval; + uint32_t timeout; + + /* Initiate the RX FIFO flush operation */ + + stm32_putreg(OTGHS_GRSTCTL_RXFFLSH, STM32_OTGHS_GRSTCTL); + + /* Wait for the FLUSH to complete */ + + for (timeout = 0; timeout < STM32_FLUSH_DELAY; timeout++) + { + regval = stm32_getreg(STM32_OTGHS_GRSTCTL); + if ((regval & OTGHS_GRSTCTL_RXFFLSH) == 0) + { + break; + } + } + + /* Wait for 3 PHY Clocks */ + + up_udelay(3); + return OK; +} + +/**************************************************************************** + * Name: stm32_swinitialize + * + * Description: + * Initialize all driver data structures. + * + ****************************************************************************/ + +static void stm32_swinitialize(struct stm32_usbdev_s *priv) +{ + struct stm32_ep_s *privep; + int i; + + /* Initialize the device state structure */ + + memset(priv, 0, sizeof(struct stm32_usbdev_s)); + + priv->usbdev.ops = &g_devops; + priv->usbdev.ep0 = &priv->epin[EP0].ep; + + priv->epavail[0] = STM32_EP_AVAILABLE; + priv->epavail[1] = STM32_EP_AVAILABLE; + + /* Initialize the endpoint lists */ + + for (i = 0; i < STM32_NENDPOINTS; i++) + { + /* Set endpoint operations, reference to driver structure (not + * really necessary because there is only one controller), and + * the physical endpoint number (which is just the index to the + * endpoint). + */ + + privep = &priv->epin[i]; + privep->ep.ops = &g_epops; + privep->dev = priv; + privep->isin = 1; + + /* The index, i, is the physical endpoint address; Map this + * to a logical endpoint address usable by the class driver. + */ + + privep->epphy = i; + privep->ep.eplog = STM32_EPPHYIN2LOG(i); + + /* Control until endpoint is activated */ + + privep->eptype = USB_EP_ATTR_XFER_CONTROL; + privep->ep.maxpacket = CONFIG_USBDEV_EP0_MAXSIZE; + } + + /* Initialize the endpoint lists */ + + for (i = 0; i < STM32_NENDPOINTS; i++) + { + /* Set endpoint operations, reference to driver structure (not + * really necessary because there is only one controller), and + * the physical endpoint number (which is just the index to the + * endpoint). + */ + + privep = &priv->epout[i]; + privep->ep.ops = &g_epops; + privep->dev = priv; + + /* The index, i, is the physical endpoint address; Map this + * to a logical endpoint address usable by the class driver. + */ + + privep->epphy = i; + privep->ep.eplog = STM32_EPPHYOUT2LOG(i); + + /* Control until endpoint is activated */ + + privep->eptype = USB_EP_ATTR_XFER_CONTROL; + privep->ep.maxpacket = CONFIG_USBDEV_EP0_MAXSIZE; + } +} + +/**************************************************************************** + * Name: stm32_hwinitialize + * + * Description: + * Configure the OTG HS core for operation. + * + ****************************************************************************/ + +static void stm32_hwinitialize(struct stm32_usbdev_s *priv) +{ + uint32_t regval; + uint32_t timeout; + uint32_t address; + int i; + + /* At start-up the core is in HS mode. */ + + /* Disable global interrupts by clearing the GINTMASK bit in the GAHBCFG + * register; Set the TXFELVL bit in the GAHBCFG register so that TxFIFO + * interrupts will occur when the TxFIFO is truly empty (not just half + * full). + */ + + stm32_putreg(OTGHS_GAHBCFG_TXFELVL, STM32_OTGHS_GAHBCFG); + + /* Set the PHYSEL bit in the GUSBCFG register to select the OTG HS serial + * transceiver: "This bit is always 1 with write-only access" + */ + + regval = stm32_getreg(STM32_OTGHS_GUSBCFG); + regval |= OTGHS_GUSBCFG_PHYSEL; + stm32_putreg(regval, STM32_OTGHS_GUSBCFG); + + /* Common USB OTG core initialization */ + + /* Reset after a PHY select and set Host mode. First, wait for AHB master + * IDLE state. + */ + + for (timeout = 0; timeout < STM32_READY_DELAY; timeout++) + { + up_udelay(3); + regval = stm32_getreg(STM32_OTGHS_GRSTCTL); + if ((regval & OTGHS_GRSTCTL_AHBIDL) != 0) + { + break; + } + } + + /* Then perform the core soft reset. */ + + stm32_putreg(OTGHS_GRSTCTL_CSRST, STM32_OTGHS_GRSTCTL); + for (timeout = 0; timeout < STM32_READY_DELAY; timeout++) + { + regval = stm32_getreg(STM32_OTGHS_GRSTCTL); + if ((regval & OTGHS_GRSTCTL_CSRST) == 0) + { + break; + } + } + + /* Wait for 3 PHY Clocks */ + + up_udelay(3); + + /* Deactivate the power down */ + + regval = (OTGHS_GCCFG_PWRDWN | + OTGHS_GCCFG_VBUSASEN | + OTGHS_GCCFG_VBUSBSEN); +#ifndef CONFIG_USBDEV_VBUSSENSING + regval |= OTGHS_GCCFG_NOVBUSSENS; +#endif +#ifdef CONFIG_STM32_OTGHS_SOFOUTPUT + regval |= OTGHS_GCCFG_SOFOUTEN; +#endif + stm32_putreg(regval, STM32_OTGHS_GCCFG); + up_mdelay(20); + + /* Force Device Mode */ + + regval = stm32_getreg(STM32_OTGHS_GUSBCFG); + regval &= ~OTGHS_GUSBCFG_FHMOD; + regval |= OTGHS_GUSBCFG_FDMOD; + stm32_putreg(regval, STM32_OTGHS_GUSBCFG); + up_mdelay(50); + + /* Initialize device mode */ + + /* Restart the PHY Clock */ + + stm32_putreg(0, STM32_OTGHS_PCGCCTL); + + /* Device configuration register */ + + regval = stm32_getreg(STM32_OTGHS_DCFG); + regval &= ~OTGHS_DCFG_PFIVL_MASK; + regval |= OTGHS_DCFG_PFIVL_80PCT; + stm32_putreg(regval, STM32_OTGHS_DCFG); + + /* Set full speed PHY */ + + regval = stm32_getreg(STM32_OTGHS_DCFG); + regval &= ~OTGHS_DCFG_DSPD_MASK; + regval |= OTGHS_DCFG_DSPD_FS; + stm32_putreg(regval, STM32_OTGHS_DCFG); + + /* Set Rx FIFO size */ + + stm32_putreg(STM32_RXFIFO_WORDS, STM32_OTGHS_GRXFSIZ); + + /* EP0 TX */ + + address = STM32_RXFIFO_WORDS; + regval = (address << OTGHS_DIEPTXF0_TX0FD_SHIFT) | + (STM32_EP0_TXFIFO_WORDS << OTGHS_DIEPTXF0_TX0FSA_SHIFT); + stm32_putreg(regval, STM32_OTGHS_DIEPTXF0); + + /* EP1 TX */ + + address += STM32_EP0_TXFIFO_WORDS; + regval = (address << OTGHS_DIEPTXF_INEPTXSA_SHIFT) | + (STM32_EP1_TXFIFO_WORDS << OTGHS_DIEPTXF_INEPTXFD_SHIFT); + stm32_putreg(regval, STM32_OTGHS_DIEPTXF1); + + /* EP2 TX */ + + address += STM32_EP1_TXFIFO_WORDS; + regval = (address << OTGHS_DIEPTXF_INEPTXSA_SHIFT) | + (STM32_EP2_TXFIFO_WORDS << OTGHS_DIEPTXF_INEPTXFD_SHIFT); + stm32_putreg(regval, STM32_OTGHS_DIEPTXF2); + + /* EP3 TX */ + + address += STM32_EP2_TXFIFO_WORDS; + regval = (address << OTGHS_DIEPTXF_INEPTXSA_SHIFT) | + (STM32_EP3_TXFIFO_WORDS << OTGHS_DIEPTXF_INEPTXFD_SHIFT); + stm32_putreg(regval, STM32_OTGHS_DIEPTXF3); + + /* Flush the FIFOs */ + + stm32_txfifo_flush(OTGHS_GRSTCTL_TXFNUM_DALL); + stm32_rxfifo_flush(); + + /* Clear all pending Device Interrupts */ + + stm32_putreg(0, STM32_OTGHS_DIEPMSK); + stm32_putreg(0, STM32_OTGHS_DOEPMSK); + stm32_putreg(0, STM32_OTGHS_DIEPEMPMSK); + stm32_putreg(0xffffffff, STM32_OTGHS_DAINT); + stm32_putreg(0, STM32_OTGHS_DAINTMSK); + + /* Configure all IN endpoints */ + + for (i = 0; i < STM32_NENDPOINTS; i++) + { + regval = stm32_getreg(STM32_OTGHS_DIEPCTL(i)); + if ((regval & OTGHS_DIEPCTL_EPENA) != 0) + { + /* The endpoint is already enabled */ + + regval = OTGHS_DIEPCTL_EPENA | OTGHS_DIEPCTL_SNAK; + } + else + { + regval = 0; + } + + stm32_putreg(regval, STM32_OTGHS_DIEPCTL(i)); + stm32_putreg(0, STM32_OTGHS_DIEPTSIZ(i)); + stm32_putreg(0xff, STM32_OTGHS_DIEPINT(i)); + } + + /* Configure all OUT endpoints */ + + for (i = 0; i < STM32_NENDPOINTS; i++) + { + regval = stm32_getreg(STM32_OTGHS_DOEPCTL(i)); + if ((regval & OTGHS_DOEPCTL_EPENA) != 0) + { + /* The endpoint is already enabled */ + + regval = OTGHS_DOEPCTL_EPENA | OTGHS_DOEPCTL_SNAK; + } + else + { + regval = 0; + } + + stm32_putreg(regval, STM32_OTGHS_DOEPCTL(i)); + stm32_putreg(0, STM32_OTGHS_DOEPTSIZ(i)); + stm32_putreg(0xff, STM32_OTGHS_DOEPINT(i)); + } + + /* Disable all interrupts. */ + + stm32_putreg(0, STM32_OTGHS_GINTMSK); + + /* Clear any pending USB_OTG Interrupts */ + + stm32_putreg(0xffffffff, STM32_OTGHS_GOTGINT); + + /* Clear any pending interrupts */ + + stm32_putreg(0xbfffffff, STM32_OTGHS_GINTSTS); + +#ifndef BOARD_ENABLE_USBOTG_HSULPI + /* Disable the ULPI Clock enable in RCC AHB1 Register. This must + * be done because if both the ULPI and the FS PHY clock enable bits + * are set at the same time, the ARM never awakens from WFI due to + * some bug / errata in the chip. + */ + + regval = stm32_getreg(STM32_RCC_AHB1LPENR); + regval &= ~RCC_AHB1ENR_OTGHSULPIEN; + stm32_putreg(regval, STM32_RCC_AHB1LPENR); +#endif + + /* Enable the interrupts in the INTMSK */ + + regval = (OTGHS_GINT_RXFLVL | OTGHS_GINT_USBSUSP | OTGHS_GINT_ENUMDNE | + OTGHS_GINT_IEP | OTGHS_GINT_OEP | OTGHS_GINT_USBRST); + +#ifdef CONFIG_USBDEV_ISOCHRONOUS + regval |= (OTGHS_GINT_IISOIXFR | OTGHS_GINT_IISOOXFR); +#endif + +#ifdef CONFIG_USBDEV_SOFINTERRUPT + regval |= OTGHS_GINT_SOF; +#endif + +#ifdef CONFIG_USBDEV_VBUSSENSING + regval |= (OTGHS_GINT_OTG | OTGHS_GINT_SRQ); +#endif + +#ifdef CONFIG_DEBUG_USB + regval |= OTGHS_GINT_MMIS; +#endif + + stm32_putreg(regval, STM32_OTGHS_GINTMSK); + + /* Enable the USB global interrupt by setting GINTMSK in the global OTG + * HS AHB configuration register; Set the TXFELVL bit in the GAHBCFG + * register so that TxFIFO interrupts will occur when the TxFIFO is truly + * empty (not just half full). + */ + + stm32_putreg(OTGHS_GAHBCFG_GINTMSK | OTGHS_GAHBCFG_TXFELVL, + STM32_OTGHS_GAHBCFG); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: arm_usbinitialize + * + * Description: + * Initialize USB hardware. + * + * Assumptions: + * - This function is called very early in the initialization sequence + * - PLL and GIO pin initialization is not performed here but should been in + * the low-level boot logic: PLL1 must be configured for operation at + * 48MHz and P0.23 and PO.31 in PINSEL1 must be configured for Vbus and USB + * connect LED. + * + ****************************************************************************/ + +void arm_usbinitialize(void) +{ + /* At present, there is only a single OTG HS device support. Hence it is + * pre-allocated as g_otghsdev. However, in most code, the private data + * structure will be referenced using the 'priv' pointer (rather than the + * global data) in order to simplify any future support for multiple + * devices. + */ + + struct stm32_usbdev_s *priv = &g_otghsdev; + int ret; + + usbtrace(TRACE_DEVINIT, 0); + + /* Here we assume that: + * + * 1. GPIOA and OTG HS peripheral clocking has already been enabled as part + * of the boot sequence. + * 2. Board-specific logic has already enabled other board specific GPIOs + * for things like soft pull-up, VBUS sensing, power controls, and over- + * current detection. + */ + + /* Configure OTG HS alternate function pins + * + * PIN* SIGNAL DIRECTION + * ---- ----------- ---------- + * PA8 OTG_HS_SOF SOF clock output + * PA9 OTG_HS_VBUS VBUS input for device, Driven by external regulator by + * host (not an alternate function) + * PA10 OTG_HS_ID OTG ID pin (only needed in Dual mode) + * PA11 OTG_HS_DM D- I/O + * PA12 OTG_HS_DP D+ I/O + * + * *Pins may vary from device-to-device. + */ + + stm32_configgpio(GPIO_OTGHS_DM); + stm32_configgpio(GPIO_OTGHS_DP); + stm32_configgpio(GPIO_OTGHS_ID); /* Only needed for OTG */ + + /* SOF output pin configuration is configurable. */ + +#ifdef CONFIG_STM32_OTGHS_SOFOUTPUT + stm32_configgpio(GPIO_OTGHS_SOF); +#endif + + /* Uninitialize the hardware so that we know that we are starting from a + * known state. + */ + + arm_usbuninitialize(); + + /* Initialize the driver data structure */ + + stm32_swinitialize(priv); + + /* Attach the OTG HS interrupt handler */ + + ret = irq_attach(STM32_IRQ_OTGHS, stm32_usbinterrupt, NULL); + if (ret < 0) + { + uerr("ERROR: irq_attach failed: %d\n", ret); + goto errout; + } + + /* Initialize the USB OTG core */ + + stm32_hwinitialize(priv); + + /* Disconnect device */ + + stm32_pullup(&priv->usbdev, false); + + /* Reset/Re-initialize the USB hardware */ + + stm32_usbreset(priv); + + /* Enable USB controller interrupts at the NVIC */ + + up_enable_irq(STM32_IRQ_OTGHS); + return; + +errout: + arm_usbuninitialize(); +} + +/**************************************************************************** + * Name: up_usbhsuninitialize + ****************************************************************************/ + +void arm_usbuninitialize(void) +{ + /* At present, there is only a single OTG HS device support. Hence it is + * pre-allocated as g_otghsdev. However, in most code, the private data + * structure will be referenced using the 'priv' pointer (rather than the + * global data) in order to simplify any future support for multiple + * devices. + */ + + struct stm32_usbdev_s *priv = &g_otghsdev; + irqstate_t flags; + int i; + + usbtrace(TRACE_DEVUNINIT, 0); + + if (priv->driver) + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_DRIVERREGISTERED), 0); + usbdev_unregister(priv->driver); + } + + /* Disconnect device */ + + flags = enter_critical_section(); + stm32_pullup(&priv->usbdev, false); + priv->usbdev.speed = USB_SPEED_UNKNOWN; + + /* Disable and detach IRQs */ + + up_disable_irq(STM32_IRQ_OTGHS); + irq_detach(STM32_IRQ_OTGHS); + + /* Disable all endpoint interrupts */ + + for (i = 0; i < STM32_NENDPOINTS; i++) + { + stm32_putreg(0xff, STM32_OTGHS_DIEPINT(i)); + stm32_putreg(0xff, STM32_OTGHS_DOEPINT(i)); + } + + stm32_putreg(0, STM32_OTGHS_DIEPMSK); + stm32_putreg(0, STM32_OTGHS_DOEPMSK); + stm32_putreg(0, STM32_OTGHS_DIEPEMPMSK); + stm32_putreg(0, STM32_OTGHS_DAINTMSK); + stm32_putreg(0xffffffff, STM32_OTGHS_DAINT); + + /* Flush the FIFOs */ + + stm32_txfifo_flush(OTGHS_GRSTCTL_TXFNUM_DALL); + stm32_rxfifo_flush(); + + /* TODO: Turn off USB power and clocking */ + + priv->devstate = DEVSTATE_DEFAULT; + leave_critical_section(flags); +} + +/**************************************************************************** + * Name: usbdev_register + * + * Description: + * Register a USB device class driver. The class driver's bind() method + * will be called to bind it to a USB device driver. + * + ****************************************************************************/ + +int usbdev_register(struct usbdevclass_driver_s *driver) +{ + /* At present, there is only a single OTG HS device support. Hence it is + * pre-allocated as g_otghsdev. However, in most code, the private data + * structure will be referenced using the 'priv' pointer (rather than the + * global data) in order to simplify any future support for multiple + * devices. + */ + + struct stm32_usbdev_s *priv = &g_otghsdev; + int ret; + + usbtrace(TRACE_DEVREGISTER, 0); + +#ifdef CONFIG_DEBUG_FEATURES + if (!driver || !driver->ops->bind || !driver->ops->unbind || + !driver->ops->disconnect || !driver->ops->setup) + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); + return -EINVAL; + } + + if (priv->driver) + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_DRIVER), 0); + return -EBUSY; + } +#endif + + /* First hook up the driver */ + + priv->driver = driver; + + /* Then bind the class driver */ + + ret = CLASS_BIND(driver, &priv->usbdev); + if (ret) + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BINDFAILED), (uint16_t)-ret); + priv->driver = NULL; + } + else + { + /* Enable USB controller interrupts */ + + up_enable_irq(STM32_IRQ_OTGHS); + + /* FIXME: nothing seems to call DEV_CONNECT(), but we need to set + * the RS bit to enable the controller. It kind of makes sense + * to do this after the class has bound to us... + * GEN: This bug is really in the class driver. It should make the + * soft connect when it is ready to be enumerated. I have added + * that logic to the class drivers but left this logic here. + */ + + stm32_pullup(&priv->usbdev, true); + priv->usbdev.speed = USB_SPEED_FULL; + } + + return ret; +} + +/**************************************************************************** + * Name: usbdev_unregister + * + * Description: + * Un-register usbdev class driver.If the USB device is connected to a + * USB host, it will first disconnect(). The driver is also requested + * to unbind() and clean up any device state, before this procedure + * finally returns. + * + ****************************************************************************/ + +int usbdev_unregister(struct usbdevclass_driver_s *driver) +{ + /* At present, there is only a single OTG HS device support. Hence it is + * pre-allocated as g_otghsdev. However, in most code, the private data + * structure will be referenced using the 'priv' pointer (rather than the + * global data) in order to simplify any future support for multiple + * devices. + */ + + struct stm32_usbdev_s *priv = &g_otghsdev; + irqstate_t flags; + + usbtrace(TRACE_DEVUNREGISTER, 0); + +#ifdef CONFIG_DEBUG_FEATURES + if (driver != priv->driver) + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); + return -EINVAL; + } +#endif + + /* Reset the hardware and cancel all requests. All requests must be + * canceled while the class driver is still bound. + */ + + flags = enter_critical_section(); + stm32_usbreset(priv); + leave_critical_section(flags); + + /* Unbind the class driver */ + + CLASS_UNBIND(driver, &priv->usbdev); + + /* Disable USB controller interrupts */ + + flags = enter_critical_section(); + up_disable_irq(STM32_IRQ_OTGHS); + + /* Disconnect device */ + + stm32_pullup(&priv->usbdev, false); + + /* Unhook the driver */ + + priv->driver = NULL; + leave_critical_section(flags); + + return OK; +} + +#endif /* CONFIG_USBDEV && CONFIG_STM32_OTGHSDEV */ diff --git a/arch/arm/src/common/stm32/stm32_otghshost_m3m4_v1.c b/arch/arm/src/common/stm32/stm32_otghshost_m3m4_v1.c new file mode 100644 index 0000000000000..45faa0a4963e8 --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_otghshost_m3m4_v1.c @@ -0,0 +1,5470 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_otghshost_m3m4_v1.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "chip.h" /* Includes default GPIO settings */ +#include /* May redefine GPIO settings */ + +#include "arm_internal.h" +#include "stm32_gpio.h" +#include "stm32_usbhost_m3m4_v1.h" + +#if defined(CONFIG_STM32_USBHOST) && defined(CONFIG_STM32_OTGHS) + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* STM32 USB OTG HS Host Driver Support + * + * Pre-requisites + * + * CONFIG_STM32_USBHOST - Enable STM32 USB host support + * CONFIG_USBHOST - Enable general USB host support + * CONFIG_STM32_OTGHS - Enable the STM32 USB OTG HS block + * CONFIG_STM32_SYSCFG - Needed + * + * Options: + * + * CONFIG_STM32_OTGHS_RXFIFO_SIZE - Size of the RX FIFO in 32-bit words. + * Default 128 (512 bytes) + * CONFIG_STM32_OTGHS_NPTXFIFO_SIZE - Size of the non-periodic Tx FIFO + * in 32-bit words. Default 96 (384 bytes) + * CONFIG_STM32_OTGHS_PTXFIFO_SIZE - Size of the periodic Tx FIFO in 32-bit + * words. Default 96 (384 bytes) + * CONFIG_STM32_OTGHS_DESCSIZE - Maximum size of a descriptor. Default: 128 + * CONFIG_STM32_OTGHS_SOFINTR - Enable SOF interrupts. Why would you ever + * want to do that? + * CONFIG_STM32_USBHOST_REGDEBUG - Enable very low-level register access + * debug. Depends on CONFIG_DEBUG_FEATURES. + * CONFIG_STM32_USBHOST_PKTDUMP - Dump all incoming and outgoing USB + * packets. Depends on CONFIG_DEBUG_FEATURES. + */ + +/* Pre-requisites (partial) */ + +#ifndef CONFIG_STM32_SYSCFG +# error "CONFIG_STM32_SYSCFG is required" +#endif + +/* Default RxFIFO size */ + +#ifndef CONFIG_STM32_OTGHS_RXFIFO_SIZE +# define CONFIG_STM32_OTGHS_RXFIFO_SIZE 128 +#endif + +/* Default host non-periodic Tx FIFO size */ + +#ifndef CONFIG_STM32_OTGHS_NPTXFIFO_SIZE +# define CONFIG_STM32_OTGHS_NPTXFIFO_SIZE 96 +#endif + +/* Default host periodic Tx fifo size register */ + +#ifndef CONFIG_STM32_OTGHS_PTXFIFO_SIZE +# define CONFIG_STM32_OTGHS_PTXFIFO_SIZE 96 +#endif + +/* Maximum size of a descriptor */ + +#ifndef CONFIG_STM32_OTGHS_DESCSIZE +# define CONFIG_STM32_OTGHS_DESCSIZE 128 +#endif + +/* Register/packet debug depends on CONFIG_DEBUG_FEATURES */ + +#ifndef CONFIG_DEBUG_USB_INFO +# undef CONFIG_STM32_USBHOST_REGDEBUG +# undef CONFIG_STM32_USBHOST_PKTDUMP +#endif + +/* HCD Setup ****************************************************************/ + +/* Hardware capabilities */ + +#if defined(CONFIG_STM32_STM32F446) +# define STM32_NHOST_CHANNELS 16 /* Number of host channels */ +# define STM32_MAX_TX_FIFOS 16 /* Max number of TX FIFOs */ +#else +# define STM32_NHOST_CHANNELS 12 /* Number of host channels */ +# define STM32_MAX_TX_FIFOS 12 /* Max number of TX FIFOs */ +#endif +#define STM32_MAX_PACKET_SIZE 64 /* Full speed max packet size */ +#define STM32_EP0_DEF_PACKET_SIZE 8 /* EP0 default packet size */ +#define STM32_EP0_MAX_PACKET_SIZE 64 /* EP0 HS max packet size */ +#define STM32_MAX_PKTCOUNT 256 /* Max packet count */ +#define STM32_RETRY_COUNT 3 /* Number of ctrl transfer retries */ + +/* Delays *******************************************************************/ + +#define STM32_READY_DELAY 200000 /* In loop counts */ +#define STM32_FLUSH_DELAY 200000 /* In loop counts */ +#define STM32_SETUP_DELAY SEC2TICK(5) /* 5 seconds in system ticks */ +#define STM32_DATANAK_DELAY SEC2TICK(5) /* 5 seconds in system ticks */ + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/* The following enumeration represents the various states of the USB host + * state machine (for debug purposes only) + */ + +enum stm32_smstate_e +{ + SMSTATE_DETACHED = 0, /* Not attached to a device */ + SMSTATE_ATTACHED, /* Attached to a device */ + SMSTATE_ENUM, /* Attached, enumerating */ + SMSTATE_CLASS_BOUND, /* Enumeration complete, class bound */ +}; + +/* This enumeration provides the reason for the channel halt. */ + +enum stm32_chreason_e +{ + CHREASON_IDLE = 0, /* Inactive (initial state) */ + CHREASON_FREED, /* Channel is no longer in use */ + CHREASON_XFRC, /* Transfer complete */ + CHREASON_NAK, /* NAK received */ + CHREASON_NYET, /* NotYet received */ + CHREASON_STALL, /* Endpoint stalled */ + CHREASON_TXERR, /* Transfer error received */ + CHREASON_DTERR, /* Data toggle error received */ + CHREASON_FRMOR, /* Frame overrun */ + CHREASON_CANCELLED /* Transfer cancelled */ +}; + +/* This structure retains the state of one host channel. NOTE: Since there + * is only one channel operation active at a time, some of the fields in + * in the structure could be moved in struct stm32_ubhost_s to achieve + * some memory savings. + */ + +struct stm32_chan_s +{ + sem_t waitsem; /* Channel wait semaphore */ + volatile uint8_t result; /* The result of the transfer */ + volatile uint8_t chreason; /* Channel halt reason. See enum stm32_chreason_e */ + uint8_t chidx; /* Channel index */ + uint8_t epno; /* Device endpoint number (0-127) */ + uint8_t eptype; /* See OTGHS_EPTYPE_* definitions */ + uint8_t funcaddr; /* Device function address */ + uint8_t speed; /* Device speed */ + uint8_t interval; /* Interrupt/isochronous EP polling interval */ + uint8_t pid; /* Data PID */ + uint8_t npackets; /* Number of packets (for data toggle) */ + bool inuse; /* True: This channel is "in use" */ + volatile bool indata1; /* IN data toggle. True: DATA01 (Bulk and INTR only) */ + volatile bool outdata1; /* OUT data toggle. True: DATA01 */ + bool in; /* True: IN endpoint */ + volatile bool waiter; /* True: Thread is waiting for a channel event */ + uint16_t maxpacket; /* Max packet size */ + uint16_t buflen; /* Buffer length (at start of transfer) */ + volatile uint16_t xfrd; /* Bytes transferred (at end of transfer) */ + volatile uint16_t inflight; /* Number of Tx bytes "in-flight" */ + uint8_t *buffer; /* Transfer buffer pointer */ +#ifdef CONFIG_USBHOST_ASYNCH + usbhost_asynch_t callback; /* Transfer complete callback */ + void *arg; /* Argument that accompanies the callback */ +#endif +}; + +/* A channel represents on uni-directional endpoint. So, in the case of the + * bi-directional, control endpoint, there must be two channels to represent + * the endpoint. + */ + +struct stm32_ctrlinfo_s +{ + uint8_t inndx; /* EP0 IN control channel index */ + uint8_t outndx; /* EP0 OUT control channel index */ +}; + +/* This structure retains the state of the USB host controller */ + +struct stm32_usbhost_s +{ + /* Common device fields. This must be the first thing defined in the + * structure so that it is possible to simply cast from struct usbhost_s + * to structstm32_usbhost_s. + */ + + struct usbhost_driver_s drvr; + + /* This is the hub port description understood by class drivers */ + + struct usbhost_roothubport_s rhport; + + /* Overall driver status */ + + volatile uint8_t smstate; /* The state of the USB host state machine */ + uint8_t chidx; /* ID of channel waiting for space in Tx FIFO */ + volatile bool connected; /* Connected to device */ + volatile bool change; /* Connection change */ + volatile bool pscwait; /* True: Thread is waiting for a port event */ + mutex_t lock; /* Support mutually exclusive access */ + sem_t pscsem; /* Semaphore to wait for a port event */ + struct stm32_ctrlinfo_s ep0; /* Root hub port EP0 description */ + +#ifdef CONFIG_USBHOST_HUB + /* Used to pass external hub port events */ + + volatile struct usbhost_hubport_s *hport; +#endif + + struct usbhost_devaddr_s devgen; /* Address generation data */ + + /* The state of each host channel */ + + struct stm32_chan_s chan[STM32_MAX_TX_FIFOS]; +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/* Register operations ******************************************************/ + +#ifdef CONFIG_STM32_USBHOST_REGDEBUG +static void stm32_printreg(uint32_t addr, uint32_t val, bool iswrite); +static void stm32_checkreg(uint32_t addr, uint32_t val, bool iswrite); +static uint32_t stm32_getreg(uint32_t addr); +static void stm32_putreg(uint32_t addr, uint32_t value); +#else +# define stm32_getreg(addr) getreg32(addr) +# define stm32_putreg(addr,val) putreg32(val,addr) +#endif + +static inline void stm32_modifyreg(uint32_t addr, uint32_t clrbits, + uint32_t setbits); + +#ifdef CONFIG_STM32_USBHOST_PKTDUMP +# define stm32_pktdump(m,b,n) lib_dumpbuffer(m,b,n) +#else +# define stm32_pktdump(m,b,n) +#endif + +/* Byte stream access helper functions **************************************/ + +static inline uint16_t stm32_getle16(const uint8_t *val); + +/* Channel management *******************************************************/ + +static int stm32_chan_alloc(struct stm32_usbhost_s *priv); +static inline void stm32_chan_free(struct stm32_usbhost_s *priv, + int chidx); +static inline void stm32_chan_freeall(struct stm32_usbhost_s *priv); +static void stm32_chan_configure(struct stm32_usbhost_s *priv, + int chidx); +static void stm32_chan_halt(struct stm32_usbhost_s *priv, int chidx, + enum stm32_chreason_e chreason); +static int stm32_chan_waitsetup(struct stm32_usbhost_s *priv, + struct stm32_chan_s *chan); +#ifdef CONFIG_USBHOST_ASYNCH +static int stm32_chan_asynchsetup(struct stm32_usbhost_s *priv, + struct stm32_chan_s *chan, + usbhost_asynch_t callback, void *arg); +#endif +static int stm32_chan_wait(struct stm32_usbhost_s *priv, + struct stm32_chan_s *chan); +static void stm32_chan_wakeup(struct stm32_usbhost_s *priv, + struct stm32_chan_s *chan); +static int stm32_ctrlchan_alloc(struct stm32_usbhost_s *priv, + uint8_t epno, uint8_t funcaddr, + uint8_t speed, + struct stm32_ctrlinfo_s *ctrlep); +static int stm32_ctrlep_alloc(struct stm32_usbhost_s *priv, + const struct usbhost_epdesc_s *epdesc, + usbhost_ep_t *ep); +static int stm32_xfrep_alloc(struct stm32_usbhost_s *priv, + const struct usbhost_epdesc_s *epdesc, + usbhost_ep_t *ep); + +/* Control/data transfer logic **********************************************/ + +static void stm32_transfer_start(struct stm32_usbhost_s *priv, + int chidx); +#if 0 /* Not used */ +static inline uint16_t stm32_getframe(void); +#endif +static int stm32_ctrl_sendsetup(struct stm32_usbhost_s *priv, + struct stm32_ctrlinfo_s *ep0, + const struct usb_ctrlreq_s *req); +static int stm32_ctrl_senddata(struct stm32_usbhost_s *priv, + struct stm32_ctrlinfo_s *ep0, + uint8_t *buffer, unsigned int buflen); +static int stm32_ctrl_recvdata(struct stm32_usbhost_s *priv, + struct stm32_ctrlinfo_s *ep0, + uint8_t *buffer, unsigned int buflen); +static int stm32_in_setup(struct stm32_usbhost_s *priv, int chidx); +static ssize_t stm32_in_transfer(struct stm32_usbhost_s *priv, int chidx, + uint8_t *buffer, size_t buflen); +#ifdef CONFIG_USBHOST_ASYNCH +static void stm32_in_next(struct stm32_usbhost_s *priv, + struct stm32_chan_s *chan); +static int stm32_in_asynch(struct stm32_usbhost_s *priv, int chidx, + uint8_t *buffer, size_t buflen, + usbhost_asynch_t callback, void *arg); +#endif +static int stm32_out_setup(struct stm32_usbhost_s *priv, int chidx); +static ssize_t stm32_out_transfer(struct stm32_usbhost_s *priv, + int chidx, uint8_t *buffer, + size_t buflen); +#ifdef CONFIG_USBHOST_ASYNCH +static void stm32_out_next(struct stm32_usbhost_s *priv, + struct stm32_chan_s *chan); +static int stm32_out_asynch(struct stm32_usbhost_s *priv, int chidx, + uint8_t *buffer, size_t buflen, + usbhost_asynch_t callback, void *arg); +#endif + +/* Interrupt handling *******************************************************/ + +/* Lower level interrupt handlers */ + +static void stm32_gint_wrpacket(struct stm32_usbhost_s *priv, + uint8_t *buffer, int chidx, int buflen); +static inline void stm32_gint_hcinisr(struct stm32_usbhost_s *priv, + int chidx); +static inline void stm32_gint_hcoutisr(struct stm32_usbhost_s *priv, + int chidx); +static void stm32_gint_connected(struct stm32_usbhost_s *priv); +static void stm32_gint_disconnected(struct stm32_usbhost_s *priv); + +/* Second level interrupt handlers */ + +#ifdef CONFIG_STM32_OTGHS_SOFINTR +static inline void stm32_gint_sofisr(struct stm32_usbhost_s *priv); +#endif +static inline void stm32_gint_rxflvlisr(struct stm32_usbhost_s *priv); +static inline void stm32_gint_nptxfeisr(struct stm32_usbhost_s *priv); +static inline void stm32_gint_ptxfeisr(struct stm32_usbhost_s *priv); +static inline void stm32_gint_hcisr(struct stm32_usbhost_s *priv); +static inline void stm32_gint_hprtisr(struct stm32_usbhost_s *priv); +static inline void stm32_gint_discisr(struct stm32_usbhost_s *priv); +static inline void stm32_gint_ipxfrisr(struct stm32_usbhost_s *priv); + +/* First level, global interrupt handler */ + +static int stm32_gint_isr(int irq, void *context, void *arg); + +/* Interrupt controls */ + +static void stm32_gint_enable(void); +static void stm32_gint_disable(void); +static inline void stm32_hostinit_enable(void); +static void stm32_txfe_enable(struct stm32_usbhost_s *priv, int chidx); + +/* USB host controller operations *******************************************/ + +static int stm32_wait(struct usbhost_connection_s *conn, + struct usbhost_hubport_s **hport); +static int stm32_rh_enumerate(struct stm32_usbhost_s *priv, + struct usbhost_connection_s *conn, + struct usbhost_hubport_s *hport); +static int stm32_enumerate(struct usbhost_connection_s *conn, + struct usbhost_hubport_s *hport); + +static int stm32_ep0configure(struct usbhost_driver_s *drvr, + usbhost_ep_t ep0, uint8_t funcaddr, + uint8_t speed, uint16_t maxpacketsize); +static int stm32_epalloc(struct usbhost_driver_s *drvr, + const struct usbhost_epdesc_s *epdesc, + usbhost_ep_t *ep); +static int stm32_epfree(struct usbhost_driver_s *drvr, usbhost_ep_t ep); +static int stm32_alloc(struct usbhost_driver_s *drvr, + uint8_t **buffer, size_t *maxlen); +static int stm32_free(struct usbhost_driver_s *drvr, + uint8_t *buffer); +static int stm32_ioalloc(struct usbhost_driver_s *drvr, + uint8_t **buffer, size_t buflen); +static int stm32_iofree(struct usbhost_driver_s *drvr, + uint8_t *buffer); +static int stm32_ctrlin(struct usbhost_driver_s *drvr, usbhost_ep_t ep0, + const struct usb_ctrlreq_s *req, + uint8_t *buffer); +static int stm32_ctrlout(struct usbhost_driver_s *drvr, usbhost_ep_t ep0, + const struct usb_ctrlreq_s *req, + const uint8_t *buffer); +static ssize_t stm32_transfer(struct usbhost_driver_s *drvr, + usbhost_ep_t ep, uint8_t *buffer, + size_t buflen); +#ifdef CONFIG_USBHOST_ASYNCH +static int stm32_asynch(struct usbhost_driver_s *drvr, usbhost_ep_t ep, + uint8_t *buffer, size_t buflen, + usbhost_asynch_t callback, void *arg); +#endif +static int stm32_cancel(struct usbhost_driver_s *drvr, usbhost_ep_t ep); +#ifdef CONFIG_USBHOST_HUB +static int stm32_connect(struct usbhost_driver_s *drvr, + struct usbhost_hubport_s *hport, + bool connected); +#endif +static void stm32_disconnect(struct usbhost_driver_s *drvr, + struct usbhost_hubport_s *hport); + +/* Initialization ***********************************************************/ + +static void stm32_portreset(struct stm32_usbhost_s *priv); +static void stm32_flush_txfifos(uint32_t txfnum); +static void stm32_flush_rxfifo(void); +static void stm32_vbusdrive(struct stm32_usbhost_s *priv, bool state); +static void stm32_host_initialize(struct stm32_usbhost_s *priv); + +static inline void stm32_sw_initialize(struct stm32_usbhost_s *priv); +static inline int stm32_hw_initialize(struct stm32_usbhost_s *priv); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* In this driver implementation, support is provided for only a single a + * single USB device. All status information can be simply retained in a + * single global instance. + */ + +static struct stm32_usbhost_s g_usbhost = +{ + .lock = NXMUTEX_INITIALIZER, + .pscsem = SEM_INITIALIZER(0), +}; + +/* This is the connection/enumeration interface */ + +static struct usbhost_connection_s g_usbconn = +{ + .wait = stm32_wait, + .enumerate = stm32_enumerate, +}; + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_printreg + * + * Description: + * Print the contents of an STM32xx register operation + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_USBHOST_REGDEBUG +static void stm32_printreg(uint32_t addr, uint32_t val, bool iswrite) +{ + uinfo("%08" PRIx32 "%s%08" PRIx32 "\n", addr, iswrite ? "<-" : "->", val); +} +#endif + +/**************************************************************************** + * Name: stm32_checkreg + * + * Description: + * Get the contents of an STM32 register + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_USBHOST_REGDEBUG +static void stm32_checkreg(uint32_t addr, uint32_t val, bool iswrite) +{ + static uint32_t prevaddr = 0; + static uint32_t preval = 0; + static uint32_t count = 0; + static bool prevwrite = false; + + /* Is this the same value that we read from/wrote to the same register + * last time? Are we polling the register? If so, suppress the output. + */ + + if (addr == prevaddr && val == preval && prevwrite == iswrite) + { + /* Yes.. Just increment the count */ + + count++; + } + else + { + /* No this is a new address or value or operation. Were there any + * duplicate accesses before this one? + */ + + if (count > 0) + { + /* Yes.. Just one? */ + + if (count == 1) + { + /* Yes.. Just one */ + + stm32_printreg(prevaddr, preval, prevwrite); + } + else + { + /* No.. More than one. */ + + uinfo("[repeats %d more times]\n", count); + } + } + + /* Save the new address, value, count, and operation for next time */ + + prevaddr = addr; + preval = val; + count = 0; + prevwrite = iswrite; + + /* Show the new regisgter access */ + + stm32_printreg(addr, val, iswrite); + } +} +#endif + +/**************************************************************************** + * Name: stm32_getreg + * + * Description: + * Get the contents of an STM32 register + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_USBHOST_REGDEBUG +static uint32_t stm32_getreg(uint32_t addr) +{ + /* Read the value from the register */ + + uint32_t val = getreg32(addr); + + /* Check if we need to print this value */ + + stm32_checkreg(addr, val, false); + return val; +} +#endif + +/**************************************************************************** + * Name: stm32_putreg + * + * Description: + * Set the contents of an STM32 register to a value + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_USBHOST_REGDEBUG +static void stm32_putreg(uint32_t addr, uint32_t val) +{ + /* Check if we need to print this value */ + + stm32_checkreg(addr, val, true); + + /* Write the value */ + + putreg32(val, addr); +} +#endif + +/**************************************************************************** + * Name: stm32_modifyreg + * + * Description: + * Modify selected bits of an STM32 register. + * + ****************************************************************************/ + +static inline void stm32_modifyreg(uint32_t addr, uint32_t clrbits, + uint32_t setbits) +{ + stm32_putreg(addr, (((stm32_getreg(addr)) & ~clrbits) | setbits)); +} + +/**************************************************************************** + * Name: stm32_getle16 + * + * Description: + * Get a (possibly unaligned) 16-bit little endian value. + * + ****************************************************************************/ + +static inline uint16_t stm32_getle16(const uint8_t *val) +{ + return (uint16_t)val[1] << 8 | (uint16_t)val[0]; +} + +/**************************************************************************** + * Name: stm32_chan_alloc + * + * Description: + * Allocate a channel. + * + ****************************************************************************/ + +static int stm32_chan_alloc(struct stm32_usbhost_s *priv) +{ + int chidx; + + /* Search the table of channels */ + + for (chidx = 0; chidx < STM32_NHOST_CHANNELS; chidx++) + { + /* Is this channel available? */ + + if (!priv->chan[chidx].inuse) + { + /* Yes... make it "in use" and return the index */ + + priv->chan[chidx].inuse = true; + return chidx; + } + } + + /* All of the channels are "in-use" */ + + return -EBUSY; +} + +/**************************************************************************** + * Name: stm32_chan_free + * + * Description: + * Free a previoiusly allocated channel. + * + ****************************************************************************/ + +static void stm32_chan_free(struct stm32_usbhost_s *priv, int chidx) +{ + DEBUGASSERT((unsigned)chidx < STM32_NHOST_CHANNELS); + + /* Halt the channel */ + + stm32_chan_halt(priv, chidx, CHREASON_FREED); + + /* Mark the channel available */ + + priv->chan[chidx].inuse = false; +} + +/**************************************************************************** + * Name: stm32_chan_freeall + * + * Description: + * Free all channels. + * + ****************************************************************************/ + +static inline void stm32_chan_freeall(struct stm32_usbhost_s *priv) +{ + uint8_t chidx; + + /* Free all host channels */ + + for (chidx = 2; chidx < STM32_NHOST_CHANNELS; chidx++) + { + stm32_chan_free(priv, chidx); + } +} + +/**************************************************************************** + * Name: stm32_chan_configure + * + * Description: + * Configure or re-configure a host channel. Host channels are configured + * when endpoint is allocated and EP0 (only) is re-configured with the + * max packet size or device address changes. + * + ****************************************************************************/ + +static void stm32_chan_configure(struct stm32_usbhost_s *priv, int chidx) +{ + struct stm32_chan_s *chan = &priv->chan[chidx]; + uint32_t regval; + + /* Clear any old pending interrupts for this host channel. */ + + stm32_putreg(STM32_OTGHS_HCINT(chidx), 0xffffffff); + + /* Enable channel interrupts required for transfers on this channel. */ + + regval = 0; + + switch (chan->eptype) + { + case OTGHS_EPTYPE_CTRL: + case OTGHS_EPTYPE_BULK: + { +#ifdef HAVE_USBHOST_TRACE_VERBOSE + uint16_t intrace; + uint16_t outtrace; + + /* Determine the definitive trace ID to use below */ + + if (chan->eptype == OTGHS_EPTYPE_CTRL) + { + intrace = OTGHS_VTRACE2_CHANCONF_CTRL_IN; + outtrace = OTGHS_VTRACE2_CHANCONF_CTRL_OUT; + } + else + { + intrace = OTGHS_VTRACE2_CHANCONF_BULK_IN; + outtrace = OTGHS_VTRACE2_CHANCONF_BULK_OUT; + } +#endif + + /* Interrupts required for CTRL and BULK endpoints */ + + regval |= (OTGHS_HCINT_XFRC | OTGHS_HCINT_STALL | OTGHS_HCINT_NAK | + OTGHS_HCINT_TXERR | OTGHS_HCINT_DTERR); + + /* Additional setting for IN/OUT endpoints */ + + if (chan->in) + { + usbhost_vtrace2(intrace, chidx, chan->epno); + regval |= OTGHS_HCINT_BBERR; + } + else + { + usbhost_vtrace2(outtrace, chidx, chan->epno); + regval |= OTGHS_HCINT_NYET; + } + } + break; + + case OTGHS_EPTYPE_INTR: + { + /* Interrupts required for INTR endpoints */ + + regval |= (OTGHS_HCINT_XFRC | OTGHS_HCINT_STALL | + OTGHS_HCINT_NAK | OTGHS_HCINT_TXERR | + OTGHS_HCINT_FRMOR | OTGHS_HCINT_DTERR); + + /* Additional setting for IN endpoints */ + + if (chan->in) + { + usbhost_vtrace2(OTGHS_VTRACE2_CHANCONF_INTR_IN, chidx, + chan->epno); + regval |= OTGHS_HCINT_BBERR; + } +#ifdef HAVE_USBHOST_TRACE_VERBOSE + else + { + usbhost_vtrace2(OTGHS_VTRACE2_CHANCONF_INTR_OUT, chidx, + chan->epno); + } +#endif + } + break; + + case OTGHS_EPTYPE_ISOC: + { + /* Interrupts required for ISOC endpoints */ + + regval |= OTGHS_HCINT_XFRC | OTGHS_HCINT_ACK | OTGHS_HCINT_FRMOR; + + /* Additional setting for IN endpoints */ + + if (chan->in) + { + usbhost_vtrace2(OTGHS_VTRACE2_CHANCONF_ISOC_IN, chidx, + chan->epno); + regval |= (OTGHS_HCINT_TXERR | OTGHS_HCINT_BBERR); + } +#ifdef HAVE_USBHOST_TRACE_VERBOSE + else + { + usbhost_vtrace2(OTGHS_VTRACE2_CHANCONF_ISOC_OUT, chidx, + chan->epno); + } +#endif + } + break; + } + + stm32_putreg(STM32_OTGHS_HCINTMSK(chidx), regval); + + /* Enable the top level host channel interrupt. */ + + stm32_modifyreg(STM32_OTGHS_HAINTMSK, 0, OTGHS_HAINT(chidx)); + + /* Make sure host channel interrupts are enabled. */ + + stm32_modifyreg(STM32_OTGHS_GINTMSK, 0, OTGHS_GINT_HC); + + /* Program the HCCHAR register */ + + regval = ((uint32_t)chan->maxpacket << OTGHS_HCCHAR_MPSIZ_SHIFT) | + ((uint32_t)chan->epno << OTGHS_HCCHAR_EPNUM_SHIFT) | + ((uint32_t)chan->eptype << OTGHS_HCCHAR_EPTYP_SHIFT) | + ((uint32_t)chan->funcaddr << OTGHS_HCCHAR_DAD_SHIFT); + + /* Special case settings for low speed devices */ + + if (chan->speed == USB_SPEED_LOW) + { + regval |= OTGHS_HCCHAR_LSDEV; + } + + /* Special case settings for IN endpoints */ + + if (chan->in) + { + regval |= OTGHS_HCCHAR_EPDIR_IN; + } + + /* Special case settings for INTR endpoints */ + + if (chan->eptype == OTGHS_EPTYPE_INTR) + { + regval |= OTGHS_HCCHAR_ODDFRM; + } + + /* Write the channel configuration */ + + stm32_putreg(STM32_OTGHS_HCCHAR(chidx), regval); +} + +/**************************************************************************** + * Name: stm32_chan_halt + * + * Description: + * Halt the channel associated with 'chidx' by setting the CHannel DISable + * (CHDIS) bit in in the HCCHAR register. + * + ****************************************************************************/ + +static void stm32_chan_halt(struct stm32_usbhost_s *priv, int chidx, + enum stm32_chreason_e chreason) +{ + uint32_t hcchar; + uint32_t intmsk; + uint32_t eptype; + unsigned int avail; + + /* Save the reason for the halt. We need this in the channel halt + * interrupt handling logic to know what to do next. + */ + + usbhost_vtrace2(OTGHS_VTRACE2_CHANHALT, chidx, chreason); + + priv->chan[chidx].chreason = (uint8_t)chreason; + + /* "The application can disable any channel by programming the + * OTG_HS_HCCHARx register with the CHDIS and CHENA bits set to 1. This + * enables the OTG_HS host to flush the posted requests (if any) and + * generates a channel halted interrupt. The application must wait for + * the CHH interrupt in OTG_HS_HCINTx before reallocating the channel for + * other transactions. The OTG_HS host does not interrupt the + * transaction that has already been started on the USB." + */ + + hcchar = stm32_getreg(STM32_OTGHS_HCCHAR(chidx)); + hcchar |= (OTGHS_HCCHAR_CHDIS | OTGHS_HCCHAR_CHENA); + + /* Get the endpoint type from the HCCHAR register */ + + eptype = hcchar & OTGHS_HCCHAR_EPTYP_MASK; + + /* Check for space in the Tx FIFO to issue the halt. + * + * "Before disabling a channel, the application must ensure that there is + * at least one free space available in the non-periodic request queue + * (when disabling a non-periodic channel) or the periodic request queue + * (when disabling a periodic channel). The application can simply flush + * the posted requests when the Request queue is full (before disabling + * the channel), by programming the OTG_HS_HCCHARx register with the + * CHDIS bit set to 1, and the CHENA bit cleared to 0." + */ + + if (eptype == OTGHS_HCCHAR_EPTYP_CTRL || + eptype == OTGHS_HCCHAR_EPTYP_BULK) + { + /* Get the number of words available in the non-periodic Tx FIFO. */ + + avail = stm32_getreg(STM32_OTGHS_HNPTXSTS) & + OTGHS_HNPTXSTS_NPTXFSAV_MASK; + } + else + { + /* Get the number of words available in the non-periodic Tx FIFO. */ + + avail = stm32_getreg(STM32_OTGHS_HPTXSTS) & + OTGHS_HPTXSTS_PTXFSAVL_MASK; + } + + /* Check if there is any space available in the Tx FIFO. */ + + if (avail == 0) + { + /* The Tx FIFO is full... disable the channel to flush the requests */ + + hcchar &= ~OTGHS_HCCHAR_CHENA; + } + + /* Unmask the CHannel Halted (CHH) interrupt */ + + intmsk = stm32_getreg(STM32_OTGHS_HCINTMSK(chidx)); + intmsk |= OTGHS_HCINT_CHH; + stm32_putreg(STM32_OTGHS_HCINTMSK(chidx), intmsk); + + /* Halt the channel by setting CHDIS (and maybe CHENA) in the HCCHAR */ + + stm32_putreg(STM32_OTGHS_HCCHAR(chidx), hcchar); +} + +/**************************************************************************** + * Name: stm32_chan_waitsetup + * + * Description: + * Set the request for the transfer complete event well BEFORE enabling + * the transfer (as soon as we are absolutely committed to the transfer). + * We do this to minimize race conditions. This logic would have to be + * expanded if we want to have more than one packet in flight at a time! + * + * Assumptions: + * Called from a normal thread context BEFORE the transfer has been + * started. + * + ****************************************************************************/ + +static int stm32_chan_waitsetup(struct stm32_usbhost_s *priv, + struct stm32_chan_s *chan) +{ + irqstate_t flags = enter_critical_section(); + int ret = -ENODEV; + + /* Is the device still connected? */ + + if (priv->connected) + { + /* Yes.. then set waiter to indicate that we expect to be informed + * when either (1) the device is disconnected, or (2) the transfer + * completed. + */ + + chan->waiter = true; +#ifdef CONFIG_USBHOST_ASYNCH + chan->callback = NULL; + chan->arg = NULL; +#endif + ret = OK; + } + + leave_critical_section(flags); + return ret; +} + +/**************************************************************************** + * Name: stm32_chan_asynchsetup + * + * Description: + * Set the request for the transfer complete event well BEFORE enabling + * the transfer (as soon as we are absolutely committed to the to avoid + * transfer). We do this to minimize race conditions. This logic would + * have to be expanded if we want to have more than one packet in flight + * at a time! + * + * Assumptions: + * Might be called from the level of an interrupt handler + * + ****************************************************************************/ + +#ifdef CONFIG_USBHOST_ASYNCH +static int stm32_chan_asynchsetup(struct stm32_usbhost_s *priv, + struct stm32_chan_s *chan, + usbhost_asynch_t callback, void *arg) +{ + irqstate_t flags = enter_critical_section(); + int ret = -ENODEV; + + /* Is the device still connected? */ + + if (priv->connected) + { + /* Yes.. then set waiter to indicate that we expect to be informed + * when either (1) the device is disconnected, or (2) the transfer + * completed. + */ + + chan->waiter = false; + chan->callback = callback; + chan->arg = arg; + ret = OK; + } + + leave_critical_section(flags); + return ret; +} +#endif + +/**************************************************************************** + * Name: stm32_chan_wait + * + * Description: + * Wait for a transfer on a channel to complete. + * + * Assumptions: + * Called from a normal thread context + * + ****************************************************************************/ + +static int stm32_chan_wait(struct stm32_usbhost_s *priv, + struct stm32_chan_s *chan) +{ + irqstate_t flags; + int ret; + + /* Disable interrupts so that the following operations will be atomic. On + * the OTG HS global interrupt needs to be disabled. However, here we + * disable all interrupts to exploit that fact that interrupts will be re- + * enabled while we wait. + */ + + flags = enter_critical_section(); + + /* Loop, testing for an end of transfer condition. The channel 'result' + * was set to EBUSY and 'waiter' was set to true before the transfer; + * 'waiter' will be set to false and 'result' will be set appropriately + * when the transfer is completed. + */ + + do + { + /* Wait for the transfer to complete. NOTE the transfer may already + * completed before we get here or the transfer may complete while we + * wait here. + */ + + nxsem_wait_uninterruptible(&chan->waitsem); + } + while (chan->waiter); + + /* The transfer is complete re-enable interrupts and return the result */ + + ret = -(int)chan->result; + leave_critical_section(flags); + return ret; +} + +/**************************************************************************** + * Name: stm32_chan_wakeup + * + * Description: + * A channel transfer has completed... wakeup any threads waiting for the + * transfer to complete. + * + * Assumptions: + * This function is called from the transfer complete interrupt handler for + * the channel. Interrupts are disabled. + * + ****************************************************************************/ + +static void stm32_chan_wakeup(struct stm32_usbhost_s *priv, + struct stm32_chan_s *chan) +{ + /* Is the transfer complete? */ + + if (chan->result != EBUSY) + { + /* Is there a thread waiting for this transfer to complete? */ + + if (chan->waiter) + { +#ifdef CONFIG_USBHOST_ASYNCH + /* Yes.. there should not also be a callback scheduled */ + + DEBUGASSERT(chan->callback == NULL); +#endif + /* Wake'em up! */ + + usbhost_vtrace2(chan->in ? OTGHS_VTRACE2_CHANWAKEUP_IN : + OTGHS_VTRACE2_CHANWAKEUP_OUT, + chan->epno, chan->result); + + nxsem_post(&chan->waitsem); + chan->waiter = false; + } + +#ifdef CONFIG_USBHOST_ASYNCH + /* No.. is an asynchronous callback expected when the transfer + * completes? + */ + + else if (chan->callback) + { + /* Handle continuation of IN/OUT pipes */ + + if (chan->in) + { + stm32_in_next(priv, chan); + } + else + { + stm32_out_next(priv, chan); + } + } +#endif + } +} + +/**************************************************************************** + * Name: stm32_ctrlchan_alloc + * + * Description: + * Allocate and configured channels for a control pipe. + * + ****************************************************************************/ + +static int stm32_ctrlchan_alloc(struct stm32_usbhost_s *priv, + uint8_t epno, uint8_t funcaddr, + uint8_t speed, + struct stm32_ctrlinfo_s *ctrlep) +{ + struct stm32_chan_s *chan; + int inndx; + int outndx; + + outndx = stm32_chan_alloc(priv); + if (outndx < 0) + { + return -ENOMEM; + } + + ctrlep->outndx = outndx; + chan = &priv->chan[outndx]; + chan->epno = epno; + chan->in = false; + chan->eptype = OTGHS_EPTYPE_CTRL; + chan->funcaddr = funcaddr; + chan->speed = speed; + chan->interval = 0; + chan->maxpacket = STM32_EP0_DEF_PACKET_SIZE; + chan->indata1 = false; + chan->outdata1 = false; + + /* Configure control OUT channels */ + + stm32_chan_configure(priv, outndx); + + /* Allocate and initialize the control IN channel */ + + inndx = stm32_chan_alloc(priv); + if (inndx < 0) + { + stm32_chan_free(priv, outndx); + return -ENOMEM; + } + + ctrlep->inndx = inndx; + chan = &priv->chan[inndx]; + chan->epno = epno; + chan->in = true; + chan->eptype = OTGHS_EPTYPE_CTRL; + chan->funcaddr = funcaddr; + chan->speed = speed; + chan->interval = 0; + chan->maxpacket = STM32_EP0_DEF_PACKET_SIZE; + chan->indata1 = false; + chan->outdata1 = false; + + /* Configure control IN channels */ + + stm32_chan_configure(priv, inndx); + return OK; +} + +/**************************************************************************** + * Name: stm32_ctrlep_alloc + * + * Description: + * Allocate a container and channels for control pipe. + * + * Input Parameters: + * priv - The private USB host driver state. + * epdesc - Describes the endpoint to be allocated. + * ep - A memory location provided by the caller in which to receive the + * allocated endpoint descriptor. + * + * Returned Value: + * On success, zero (OK) is returned. On a failure, a negated errno value + * is returned indicating the nature of the failure + * + * Assumptions: + * This function will *not* be called from an interrupt handler. + * + ****************************************************************************/ + +static int stm32_ctrlep_alloc(struct stm32_usbhost_s *priv, + const struct usbhost_epdesc_s *epdesc, + usbhost_ep_t *ep) +{ + struct usbhost_hubport_s *hport; + struct stm32_ctrlinfo_s *ctrlep; + int ret; + + /* Sanity check. NOTE that this method should only be called if a device + * is connected (because we need a valid low speed indication). + */ + + DEBUGASSERT(epdesc->hport != NULL); + hport = epdesc->hport; + + /* Allocate a container for the control endpoint */ + + ctrlep = (struct stm32_ctrlinfo_s *) + kmm_malloc(sizeof(struct stm32_ctrlinfo_s)); + if (ctrlep == NULL) + { + uerr("ERROR: Failed to allocate control endpoint container\n"); + return -ENOMEM; + } + + /* Then allocate and configure the IN/OUT channels */ + + ret = stm32_ctrlchan_alloc(priv, epdesc->addr & USB_EPNO_MASK, + hport->funcaddr, hport->speed, ctrlep); + if (ret < 0) + { + uerr("ERROR: stm32_ctrlchan_alloc failed: %d\n", ret); + kmm_free(ctrlep); + return ret; + } + + /* Return a pointer to the control pipe container as the pipe "handle" */ + + *ep = (usbhost_ep_t)ctrlep; + return OK; +} + +/**************************************************************************** + * Name: stm32_xfrep_alloc + * + * Description: + * Allocate and configure one unidirectional endpoint. + * + * Input Parameters: + * priv - The private USB host driver state. + * epdesc - Describes the endpoint to be allocated. + * ep - A memory location provided by the caller in which to receive the + * allocated endpoint descriptor. + * + * Returned Value: + * On success, zero (OK) is returned. On a failure, a negated errno value + * is returned indicating the nature of the failure + * + * Assumptions: + * This function will *not* be called from an interrupt handler. + * + ****************************************************************************/ + +static int stm32_xfrep_alloc(struct stm32_usbhost_s *priv, + const struct usbhost_epdesc_s *epdesc, + usbhost_ep_t *ep) +{ + struct usbhost_hubport_s *hport; + struct stm32_chan_s *chan; + int chidx; + + /* Sanity check. NOTE that this method should only be called if a device + * is connected (because we need a valid low speed indication). + */ + + DEBUGASSERT(epdesc->hport != NULL); + hport = epdesc->hport; + + /* Allocate a host channel for the endpoint */ + + chidx = stm32_chan_alloc(priv); + if (chidx < 0) + { + uerr("ERROR: Failed to allocate a host channel\n"); + return -ENOMEM; + } + + /* Decode the endpoint descriptor to initialize the channel data + * structures. Note: Here we depend on the fact that the endpoint + * point type is encoded in the same way in the endpoint descriptor as it + * is in the OTG HS hardware. + */ + + chan = &priv->chan[chidx]; + chan->epno = epdesc->addr & USB_EPNO_MASK; + chan->in = epdesc->in; + chan->eptype = epdesc->xfrtype; + chan->funcaddr = hport->funcaddr; + chan->speed = hport->speed; + chan->interval = epdesc->interval; + chan->maxpacket = epdesc->mxpacketsize; + chan->indata1 = false; + chan->outdata1 = false; + + /* Then configure the endpoint */ + + stm32_chan_configure(priv, chidx); + + /* Return the index to the allocated channel as the endpoint "handle" */ + + *ep = (usbhost_ep_t)chidx; + return OK; +} + +/**************************************************************************** + * Name: stm32_transfer_start + * + * Description: + * Start at transfer on the select IN or OUT channel. + * + ****************************************************************************/ + +static void stm32_transfer_start(struct stm32_usbhost_s *priv, int chidx) +{ + struct stm32_chan_s *chan; + uint32_t regval; + unsigned int npackets; + unsigned int maxpacket; + unsigned int avail; + unsigned int wrsize; + unsigned int minsize; + + /* Set up the initial state of the transfer */ + + chan = &priv->chan[chidx]; + + usbhost_vtrace2(OTGHS_VTRACE2_STARTTRANSFER, chidx, chan->buflen); + + chan->result = EBUSY; + chan->inflight = 0; + chan->xfrd = 0; + priv->chidx = chidx; + + /* Compute the expected number of packets associated to the transfer. + * If the transfer length is zero (or less than the size of one maximum + * size packet), then one packet is expected. + */ + + /* If the transfer size is greater than one packet, then calculate the + * number of packets that will be received/sent, including any partial + * final packet. + */ + + maxpacket = chan->maxpacket; + + if (chan->buflen > maxpacket) + { + npackets = (chan->buflen + maxpacket - 1) / maxpacket; + + /* Clip if the buffer length if it exceeds the maximum number of + * packets that can be transferred (this should not happen). + */ + + if (npackets > STM32_MAX_PKTCOUNT) + { + npackets = STM32_MAX_PKTCOUNT; + chan->buflen = STM32_MAX_PKTCOUNT * maxpacket; + usbhost_trace2(OTGHS_TRACE2_CLIP, chidx, chan->buflen); + } + } + else + { + /* One packet will be sent/received (might be a zero length packet) */ + + npackets = 1; + } + + /* If it is an IN transfer, then adjust the size of the buffer UP to + * a full number of packets. Hmmm... couldn't this cause an overrun + * into unallocated memory? + */ + +#if 0 /* Think about this */ + if (chan->in) + { + /* Force the buffer length to an even multiple of maxpacket */ + + chan->buflen = npackets * maxpacket; + } +#endif + + /* Save the number of packets in the transfer. We will need this in + * order to set the next data toggle correctly when the transfer + * completes. + */ + + chan->npackets = (uint8_t)npackets; + + /* Setup the HCTSIZn register */ + + regval = ((uint32_t)chan->buflen << OTGHS_HCTSIZ_XFRSIZ_SHIFT) | + ((uint32_t)npackets << OTGHS_HCTSIZ_PKTCNT_SHIFT) | + ((uint32_t)chan->pid << OTGHS_HCTSIZ_DPID_SHIFT); + stm32_putreg(STM32_OTGHS_HCTSIZ(chidx), regval); + + /* Setup the HCCHAR register: Frame oddness and host channel enable */ + + regval = stm32_getreg(STM32_OTGHS_HCCHAR(chidx)); + + /* Set/clear the Odd Frame bit. Check for an even frame; if so set Odd + * Frame. This field is applicable for only periodic (isochronous and + * interrupt) channels. + */ + + if ((stm32_getreg(STM32_OTGHS_HFNUM) & 1) == 0) + { + regval |= OTGHS_HCCHAR_ODDFRM; + } + else + { + regval &= ~OTGHS_HCCHAR_ODDFRM; + } + + regval &= ~OTGHS_HCCHAR_CHDIS; + regval |= OTGHS_HCCHAR_CHENA; + stm32_putreg(STM32_OTGHS_HCCHAR(chidx), regval); + + /* If this is an out transfer, then we need to do more.. we need to copy + * the outgoing data into the correct TxFIFO. + */ + + if (!chan->in && chan->buflen > 0) + { + /* Handle non-periodic (CTRL and BULK) OUT transfers differently than + * periodic (INTR and ISOC) OUT transfers. + */ + + minsize = MIN(chan->buflen, chan->maxpacket); + + switch (chan->eptype) + { + case OTGHS_EPTYPE_CTRL: /* Non periodic transfer */ + case OTGHS_EPTYPE_BULK: + { + /* Read the Non-periodic Tx FIFO status register */ + + regval = stm32_getreg(STM32_OTGHS_HNPTXSTS); + avail = ((regval & OTGHS_HNPTXSTS_NPTXFSAV_MASK) >> + OTGHS_HNPTXSTS_NPTXFSAV_SHIFT) << 2; + } + break; + + /* Periodic transfer */ + + case OTGHS_EPTYPE_INTR: + case OTGHS_EPTYPE_ISOC: + { + /* Read the Non-periodic Tx FIFO status register */ + + regval = stm32_getreg(STM32_OTGHS_HPTXSTS); + avail = ((regval & OTGHS_HPTXSTS_PTXFSAVL_MASK) >> + OTGHS_HPTXSTS_PTXFSAVL_SHIFT) << 2; + } + break; + + default: + DEBUGPANIC(); + return; + } + + /* Is there space in the TxFIFO to hold the minimum size packet? */ + + if (minsize <= avail) + { + /* Yes.. Get the size of the biggest thing that we can put + * in the Tx FIFO now + */ + + wrsize = chan->buflen; + if (wrsize > avail) + { + /* Clip the write size to the number of full, max sized packets + * that will fit in the Tx FIFO. + */ + + unsigned int wrpackets = avail / chan->maxpacket; + wrsize = wrpackets * chan->maxpacket; + } + + /* Write packet into the Tx FIFO. */ + + stm32_gint_wrpacket(priv, chan->buffer, chidx, wrsize); + } + + /* Did we put the entire buffer into the Tx FIFO? */ + + if (chan->buflen > avail) + { + /* No, there was insufficient space to hold the entire transfer ... + * Enable the Tx FIFO interrupt to handle the transfer when the Tx + * FIFO becomes empty. + */ + + stm32_txfe_enable(priv, chidx); + } + } +} + +/**************************************************************************** + * Name: stm32_getframe + * + * Description: + * Get the current frame number. The frame number (FRNUM) field increments + * when a new SOF is transmitted on the USB, and is cleared to 0 when it + * reaches 0x3fff. + * + ****************************************************************************/ + +#if 0 /* Not used */ +static inline uint16_t stm32_getframe(void) +{ + return (uint16_t) + (stm32_getreg(STM32_OTGHS_HFNUM) & OTGHS_HFNUM_FRNUM_MASK); +} +#endif + +/**************************************************************************** + * Name: stm32_ctrl_sendsetup + * + * Description: + * Send an IN/OUT SETUP packet. + * + ****************************************************************************/ + +static int stm32_ctrl_sendsetup(struct stm32_usbhost_s *priv, + struct stm32_ctrlinfo_s *ep0, + const struct usb_ctrlreq_s *req) +{ + struct stm32_chan_s *chan; + clock_t start; + clock_t elapsed; + int ret; + + /* Loop while the device reports NAK (and a timeout is not exceeded */ + + chan = &priv->chan[ep0->outndx]; + start = clock_systime_ticks(); + + do + { + /* Send the SETUP packet */ + + chan->pid = OTGHS_PID_SETUP; + chan->buffer = (uint8_t *)req; + chan->buflen = USB_SIZEOF_CTRLREQ; + chan->xfrd = 0; + + /* Set up for the wait BEFORE starting the transfer */ + + ret = stm32_chan_waitsetup(priv, chan); + if (ret < 0) + { + usbhost_trace1(OTGHS_TRACE1_DEVDISCONN, 0); + return ret; + } + + /* Start the transfer */ + + stm32_transfer_start(priv, ep0->outndx); + + /* Wait for the transfer to complete */ + + ret = stm32_chan_wait(priv, chan); + + /* Return on success and for all failures other than EAGAIN. EAGAIN + * means that the device NAKed the SETUP command and that we should + * try a few more times. + */ + + if (ret != -EAGAIN) + { + /* Output some debug information if the transfer failed */ + + if (ret < 0) + { + usbhost_trace1(OTGHS_TRACE1_TRNSFRFAILED, ret); + } + + /* Return the result in any event */ + + return ret; + } + + /* Get the elapsed time (in frames) */ + + elapsed = clock_systime_ticks() - start; + } + while (elapsed < STM32_SETUP_DELAY); + + return -ETIMEDOUT; +} + +/**************************************************************************** + * Name: stm32_ctrl_senddata + * + * Description: + * Send data in the data phase of an OUT control transfer. Or send status + * in the status phase of an IN control transfer + * + ****************************************************************************/ + +static int stm32_ctrl_senddata(struct stm32_usbhost_s *priv, + struct stm32_ctrlinfo_s *ep0, + uint8_t *buffer, unsigned int buflen) +{ + struct stm32_chan_s *chan = &priv->chan[ep0->outndx]; + int ret; + + /* Save buffer information */ + + chan->buffer = buffer; + chan->buflen = buflen; + chan->xfrd = 0; + + /* Set the DATA PID */ + + if (buflen == 0) + { + /* For status OUT stage with buflen == 0, set PID DATA1 */ + + chan->outdata1 = true; + } + + /* Set the Data PID as per the outdata1 boolean */ + + chan->pid = chan->outdata1 ? OTGHS_PID_DATA1 : OTGHS_PID_DATA0; + + /* Set up for the wait BEFORE starting the transfer */ + + ret = stm32_chan_waitsetup(priv, chan); + if (ret < 0) + { + usbhost_trace1(OTGHS_TRACE1_DEVDISCONN, 0); + return ret; + } + + /* Start the transfer */ + + stm32_transfer_start(priv, ep0->outndx); + + /* Wait for the transfer to complete and return the result */ + + return stm32_chan_wait(priv, chan); +} + +/**************************************************************************** + * Name: stm32_ctrl_recvdata + * + * Description: + * Receive data in the data phase of an IN control transfer. Or receive + * status in the status phase of an OUT control transfer + * + ****************************************************************************/ + +static int stm32_ctrl_recvdata(struct stm32_usbhost_s *priv, + struct stm32_ctrlinfo_s *ep0, + uint8_t *buffer, unsigned int buflen) +{ + struct stm32_chan_s *chan = &priv->chan[ep0->inndx]; + int ret; + + /* Save buffer information */ + + chan->pid = OTGHS_PID_DATA1; + chan->buffer = buffer; + chan->buflen = buflen; + chan->xfrd = 0; + + /* Set up for the wait BEFORE starting the transfer */ + + ret = stm32_chan_waitsetup(priv, chan); + if (ret < 0) + { + usbhost_trace1(OTGHS_TRACE1_DEVDISCONN, 0); + return ret; + } + + /* Start the transfer */ + + stm32_transfer_start(priv, ep0->inndx); + + /* Wait for the transfer to complete and return the result */ + + return stm32_chan_wait(priv, chan); +} + +/**************************************************************************** + * Name: stm32_in_setup + * + * Description: + * Initiate an IN transfer on an bulk, interrupt, or isochronous pipe. + * + ****************************************************************************/ + +static int stm32_in_setup(struct stm32_usbhost_s *priv, int chidx) +{ + struct stm32_chan_s *chan; + + /* Set up for the transfer based on the direction and the endpoint type */ + + chan = &priv->chan[chidx]; + switch (chan->eptype) + { + default: + case OTGHS_EPTYPE_CTRL: /* Control */ + { + /* This kind of transfer on control endpoints other than EP0 are not + * currently supported + */ + + return -ENOSYS; + } + + case OTGHS_EPTYPE_ISOC: /* Isochronous */ + { + /* Set up the IN data PID */ + + usbhost_vtrace2(OTGHS_VTRACE2_ISOCIN, chidx, chan->buflen); + chan->pid = OTGHS_PID_DATA0; + } + break; + + case OTGHS_EPTYPE_BULK: /* Bulk */ + { + /* Setup the IN data PID */ + + usbhost_vtrace2(OTGHS_VTRACE2_BULKIN, chidx, chan->buflen); + chan->pid = chan->indata1 ? OTGHS_PID_DATA1 : OTGHS_PID_DATA0; + } + break; + + case OTGHS_EPTYPE_INTR: /* Interrupt */ + { + /* Setup the IN data PID */ + + usbhost_vtrace2(OTGHS_VTRACE2_INTRIN, chidx, chan->buflen); + chan->pid = chan->indata1 ? OTGHS_PID_DATA1 : OTGHS_PID_DATA0; + } + break; + } + + /* Start the transfer */ + + stm32_transfer_start(priv, chidx); + return OK; +} + +/**************************************************************************** + * Name: stm32_in_transfer + * + * Description: + * Transfer 'buflen' bytes into 'buffer' from an IN channel. + * + ****************************************************************************/ + +static ssize_t stm32_in_transfer(struct stm32_usbhost_s *priv, int chidx, + uint8_t *buffer, size_t buflen) +{ + struct stm32_chan_s *chan; + clock_t start; + ssize_t xfrd; + int ret; + + /* Loop until the transfer completes (i.e., buflen is decremented to zero) + * or a fatal error occurs any error other than a simple NAK. NAK would + * simply indicate the end of the transfer (short-transfer). + */ + + chan = &priv->chan[chidx]; + chan->buffer = buffer; + chan->buflen = buflen; + chan->xfrd = 0; + xfrd = 0; + + start = clock_systime_ticks(); + while (chan->xfrd < chan->buflen) + { + /* Set up for the wait BEFORE starting the transfer */ + + ret = stm32_chan_waitsetup(priv, chan); + if (ret < 0) + { + usbhost_trace1(OTGHS_TRACE1_DEVDISCONN, 0); + return (ssize_t)ret; + } + + /* Set up for the transfer based on the direction and the endpoint */ + + ret = stm32_in_setup(priv, chidx); + if (ret < 0) + { + uerr("ERROR: stm32_in_setup failed: %d\n", ret); + return (ssize_t)ret; + } + + /* Wait for the transfer to complete and get the result */ + + ret = stm32_chan_wait(priv, chan); + + /* EAGAIN indicates that the device NAKed the transfer. */ + + if (ret < 0) + { + /* The transfer failed. If we received a NAK, return all data + * buffered so far (if any). + */ + + if (ret == -EAGAIN) + { + /* Was data buffered prior to the NAK? */ + + if (xfrd > 0) + { + /* Yes, return the amount of data received. + * + * REVISIT: This behavior is clearly correct for CDC/ACM + * bulk transfers and HID interrupt transfers. But I am + * not so certain for MSC bulk transfers which, I think, + * could have NAKed packets in the middle of a transfer. + */ + + return xfrd; + } + else + { + useconds_t delay; + + /* Get the elapsed time. Has the timeout elapsed? + * if not then try again. + */ + + clock_t elapsed = clock_systime_ticks() - start; + if (elapsed >= STM32_DATANAK_DELAY) + { + /* Timeout out... break out returning the NAK as + * as a failure. + */ + + return (ssize_t)ret; + } + + /* Wait a bit before retrying after a NAK. */ + + if (chan->eptype == OTGFS_EPTYPE_INTR) + { + /* For interrupt (and isochronous) endpoints, the + * polling rate is determined by the bInterval field + * of the endpoint descriptor (in units of frames + * which we treat as milliseconds here). + */ + + if (chan->interval > 0) + { + /* Convert the delay to units of microseconds */ + + delay = (useconds_t)chan->interval * 1000; + } + else + { + /* Out of range! For interrupt endpoints, the valid + * range is 1-255 frames. Assume one frame. + */ + + delay = 1000; + } + } + else + { + /* For Isochronous endpoints, bInterval must be 1. + * Bulk endpoints do not have a polling interval. + * Rather, the should wait until data is received. + * + * REVISIT: For bulk endpoints this 1 msec delay is + * only intended to give the CPU a break from the bulk + * EP tight polling loop. But are there performance + * issues? + */ + + delay = 1000; + } + + /* Wait for the next polling interval. For interrupt and + * isochronous endpoints, this is necessary to assure the + * polling interval. It is used in other cases only to + * prevent the polling from consuming too much CPU + * bandwidth. + * + * Small delays could require more resolution than is + * provided by the system timer. For example, if the + * system timer resolution is 10MS, then + * nxsched_usleep(1000) will actually request a delay 20MS + * (due to both quantization and rounding). + * + * REVISIT: So which is better? To ignore tiny delays and + * hog the system bandwidth? Or to wait for an excessive + * amount and destroy system throughput? + */ + + if (delay > CONFIG_USEC_PER_TICK) + { + nxsched_usleep(delay - CONFIG_USEC_PER_TICK); + } + } + } + else + { + /* Some unexpected, fatal error occurred. */ + + usbhost_trace1(OTGHS_TRACE1_TRNSFRFAILED, ret); + + /* Break out and return the error */ + + uerr("ERROR: stm32_chan_wait failed: %d\n", ret); + return (ssize_t)ret; + } + } + else + { + /* Successfully received another chunk of data... add that to the + * running total. Then continue reading until we read 'buflen' + * bytes of data or until the devices NAKs (implying a short + * packet). + */ + + xfrd += chan->xfrd; + } + } + + return xfrd; +} + +/**************************************************************************** + * Name: stm32_in_next + * + * Description: + * Initiate the next of a sequence of asynchronous transfers. + * + * Assumptions: + * This function is always called from an interrupt handler + * + ****************************************************************************/ + +#ifdef CONFIG_USBHOST_ASYNCH +static void stm32_in_next(struct stm32_usbhost_s *priv, + struct stm32_chan_s *chan) +{ + usbhost_asynch_t callback; + void *arg; + ssize_t nbytes; + int result; + int ret; + + /* Is the full transfer complete? Did the last chunk transfer OK? */ + + result = -(int)chan->result; + if (chan->xfrd < chan->buflen && result == OK) + { + /* Yes.. Set up for the next transfer based on the direction and the + * endpoint type + */ + + ret = stm32_in_setup(priv, chan->chidx); + if (ret >= 0) + { + return; + } + + uerr("ERROR: stm32_in_setup failed: %d\n", ret); + result = ret; + } + + /* The transfer is complete, with or without an error */ + + uinfo("Transfer complete: %d\n", result); + + /* Extract the callback information */ + + callback = chan->callback; + arg = chan->arg; + nbytes = chan->xfrd; + + chan->callback = NULL; + chan->arg = NULL; + chan->xfrd = 0; + + /* Then perform the callback */ + + if (result < 0) + { + nbytes = (ssize_t)result; + } + + callback(arg, nbytes); +} +#endif + +/**************************************************************************** + * Name: stm32_in_asynch + * + * Description: + * Initiate the first of a sequence of asynchronous transfers. + * + * Assumptions: + * This function is never called from an interrupt handler + * + ****************************************************************************/ + +#ifdef CONFIG_USBHOST_ASYNCH +static int stm32_in_asynch(struct stm32_usbhost_s *priv, int chidx, + uint8_t *buffer, size_t buflen, + usbhost_asynch_t callback, void *arg) +{ + struct stm32_chan_s *chan; + int ret; + + /* Set up for the transfer BEFORE starting the first transfer */ + + chan = &priv->chan[chidx]; + chan->buffer = buffer; + chan->buflen = buflen; + chan->xfrd = 0; + + ret = stm32_chan_asynchsetup(priv, chan, callback, arg); + if (ret < 0) + { + uerr("ERROR: stm32_chan_asynchsetup failed: %d\n", ret); + return ret; + } + + /* Set up for the transfer based on the direction and the endpoint type */ + + ret = stm32_in_setup(priv, chidx); + if (ret < 0) + { + uerr("ERROR: stm32_in_setup failed: %d\n", ret); + } + + /* And return with the transfer pending */ + + return ret; +} +#endif + +/**************************************************************************** + * Name: stm32_out_setup + * + * Description: + * Initiate an OUT transfer on an bulk, interrupt, or isochronous pipe. + * + ****************************************************************************/ + +static int stm32_out_setup(struct stm32_usbhost_s *priv, int chidx) +{ + struct stm32_chan_s *chan; + + /* Set up for the transfer based on the direction and the endpoint type */ + + chan = &priv->chan[chidx]; + switch (chan->eptype) + { + default: + case OTGHS_EPTYPE_CTRL: /* Control */ + { + /* This kind of transfer on control endpoints other than EP0 are not + * currently supported + */ + + return -ENOSYS; + } + + case OTGHS_EPTYPE_ISOC: /* Isochronous */ + { + /* Set up the OUT data PID */ + + usbhost_vtrace2(OTGHS_VTRACE2_ISOCOUT, chidx, chan->buflen); + chan->pid = OTGHS_PID_DATA0; + } + break; + + case OTGHS_EPTYPE_BULK: /* Bulk */ + { + /* Setup the OUT data PID */ + + usbhost_vtrace2(OTGHS_VTRACE2_BULKOUT, chidx, chan->buflen); + chan->pid = chan->outdata1 ? OTGHS_PID_DATA1 : OTGHS_PID_DATA0; + } + break; + + case OTGHS_EPTYPE_INTR: /* Interrupt */ + { + /* Setup the OUT data PID */ + + usbhost_vtrace2(OTGHS_VTRACE2_INTROUT, chidx, chan->buflen); + chan->pid = chan->outdata1 ? OTGHS_PID_DATA1 : OTGHS_PID_DATA0; + + /* Toggle the OUT data PID for the next transfer */ + + chan->outdata1 ^= true; + } + break; + } + + /* Start the transfer */ + + stm32_transfer_start(priv, chidx); + return OK; +} + +/**************************************************************************** + * Name: stm32_out_transfer + * + * Description: + * Transfer the 'buflen' bytes in 'buffer' through an OUT channel. + * + ****************************************************************************/ + +static ssize_t stm32_out_transfer(struct stm32_usbhost_s *priv, + int chidx, uint8_t *buffer, + size_t buflen) +{ + struct stm32_chan_s *chan; + clock_t start; + clock_t elapsed; + size_t xfrlen; + ssize_t xfrd; + int ret; + bool zlp; + + /* Loop until the transfer completes (i.e., buflen is decremented to zero) + * or a fatal error occurs (any error other than a simple NAK) + */ + + chan = &priv->chan[chidx]; + start = clock_systime_ticks(); + xfrd = 0; + zlp = (buflen == 0); + + while (buflen > 0 || zlp) + { + /* Transfer one packet at a time. The hardware is capable of queueing + * multiple OUT packets, but I just haven't figured out how to handle + * the case where a single OUT packet in the group is NAKed. + */ + + xfrlen = MIN(chan->maxpacket, buflen); + chan->buffer = buffer; + chan->buflen = xfrlen; + chan->xfrd = 0; + + /* Set up for the wait BEFORE starting the transfer */ + + ret = stm32_chan_waitsetup(priv, chan); + if (ret < 0) + { + usbhost_trace1(OTGHS_TRACE1_DEVDISCONN, 0); + return (ssize_t)ret; + } + + /* Set up for the transfer based on the direction and the endpoint */ + + ret = stm32_out_setup(priv, chidx); + if (ret < 0) + { + uerr("ERROR: stm32_out_setup failed: %d\n", ret); + return (ssize_t)ret; + } + + /* Wait for the transfer to complete and get the result */ + + ret = stm32_chan_wait(priv, chan); + + /* Handle transfer failures */ + + if (ret < 0) + { + usbhost_trace1(OTGHS_TRACE1_TRNSFRFAILED, ret); + + /* Check for a special case: If (1) the transfer was NAKed and (2) + * no Tx FIFO empty or Rx FIFO not-empty event occurred, then we + * should be able to just flush the Rx and Tx FIFOs and try again. + * We can detect this latter case because then the transfer buffer + * pointer and buffer size will be unaltered. + */ + + elapsed = clock_systime_ticks() - start; + if (ret != -EAGAIN || /* Not a NAK condition OR */ + elapsed >= STM32_DATANAK_DELAY || /* Timeout has elapsed OR */ + chan->xfrd > 0) /* Data has been partially transferred */ + { + /* Break out and return the error */ + + uerr("ERROR: stm32_chan_wait failed: %d\n", ret); + return (ssize_t)ret; + } + + /* Is this flush really necessary? What does the hardware do with + * the data in the FIFO when the NAK occurs? Does it discard it? + */ + + stm32_flush_txfifos(OTGHS_GRSTCTL_TXFNUM_HALL); + + /* Get the device a little time to catch up. Then retry the + * transfer using the same buffer pointer and length. + */ + + nxsched_usleep(20 * 1000); + } + else + { + /* Successfully transferred. Update the buffer pointer/length */ + + buffer += xfrlen; + buflen -= xfrlen; + xfrd += chan->xfrd; + zlp = false; + } + } + + return xfrd; +} + +/**************************************************************************** + * Name: stm32_out_next + * + * Description: + * Initiate the next of a sequence of asynchronous transfers. + * + * Assumptions: + * This function is always called from an interrupt handler + * + ****************************************************************************/ + +#ifdef CONFIG_USBHOST_ASYNCH +static void stm32_out_next(struct stm32_usbhost_s *priv, + struct stm32_chan_s *chan) +{ + usbhost_asynch_t callback; + void *arg; + ssize_t nbytes; + int result; + int ret; + + /* Is the full transfer complete? Did the last chunk transfer OK? */ + + result = -(int)chan->result; + if (chan->xfrd < chan->buflen && result == OK) + { + /* Yes.. Set up for the next transfer based on the direction and the + * endpoint type + */ + + ret = stm32_out_setup(priv, chan->chidx); + if (ret >= 0) + { + return; + } + + uerr("ERROR: stm32_out_setup failed: %d\n", ret); + result = ret; + } + + /* The transfer is complete, with or without an error */ + + uinfo("Transfer complete: %d\n", result); + + /* Extract the callback information */ + + callback = chan->callback; + arg = chan->arg; + nbytes = chan->xfrd; + + chan->callback = NULL; + chan->arg = NULL; + chan->xfrd = 0; + + /* Then perform the callback */ + + if (result < 0) + { + nbytes = (ssize_t)result; + } + + callback(arg, nbytes); +} +#endif + +/**************************************************************************** + * Name: stm32_out_asynch + * + * Description: + * Initiate the first of a sequence of asynchronous transfers. + * + * Assumptions: + * This function is never called from an interrupt handler + * + ****************************************************************************/ + +#ifdef CONFIG_USBHOST_ASYNCH +static int stm32_out_asynch(struct stm32_usbhost_s *priv, int chidx, + uint8_t *buffer, size_t buflen, + usbhost_asynch_t callback, void *arg) +{ + struct stm32_chan_s *chan; + int ret; + + /* Set up for the transfer BEFORE starting the first transfer */ + + chan = &priv->chan[chidx]; + chan->buffer = buffer; + chan->buflen = buflen; + chan->xfrd = 0; + + ret = stm32_chan_asynchsetup(priv, chan, callback, arg); + if (ret < 0) + { + uerr("ERROR: stm32_chan_asynchsetup failed: %d\n", ret); + return ret; + } + + /* Set up for the transfer based on the direction and the endpoint type */ + + ret = stm32_out_setup(priv, chidx); + if (ret < 0) + { + uerr("ERROR: stm32_out_setup failed: %d\n", ret); + } + + /* And return with the transfer pending */ + + return ret; +} +#endif + +/**************************************************************************** + * Name: stm32_gint_wrpacket + * + * Description: + * Transfer the 'buflen' bytes in 'buffer' to the Tx FIFO associated with + * 'chidx' (non-DMA). + * + ****************************************************************************/ + +static void stm32_gint_wrpacket(struct stm32_usbhost_s *priv, + uint8_t *buffer, int chidx, int buflen) +{ + uint32_t *src; + uint32_t fifo; + int buflen32; + + stm32_pktdump("Sending", buffer, buflen); + + /* Get the number of 32-byte words associated with this byte size */ + + buflen32 = (buflen + 3) >> 2; + + /* Get the address of the Tx FIFO associated with this channel */ + + fifo = STM32_OTGHS_DFIFO_HCH(chidx); + + /* Transfer all of the data into the Tx FIFO */ + + src = (uint32_t *)buffer; + for (; buflen32 > 0; buflen32--) + { + uint32_t data = *src++; + stm32_putreg(fifo, data); + } + + /* Increment the count of bytes "in-flight" in the Tx FIFO */ + + priv->chan[chidx].inflight += buflen; +} + +/**************************************************************************** + * Name: stm32_gint_hcinisr + * + * Description: + * USB OTG HS host IN channels interrupt handler + * + * One the completion of the transfer, the channel result byte may be set + * as follows: + * + * OK - Transfer completed successfully + * EAGAIN - If devices NAKs the transfer or NYET occurs + * EPERM - If the endpoint stalls + * EIO - On a TX or data toggle error + * EPIPE - Frame overrun + * + * EBUSY in the result field indicates that the transfer has not completed. + * + ****************************************************************************/ + +static inline void stm32_gint_hcinisr(struct stm32_usbhost_s *priv, + int chidx) +{ + struct stm32_chan_s *chan = &priv->chan[chidx]; + uint32_t regval; + uint32_t pending; + + /* Read the HCINT register to get the pending HC interrupts. Read the + * HCINTMSK register to get the set of enabled HC interrupts. + */ + + pending = stm32_getreg(STM32_OTGHS_HCINT(chidx)); + regval = stm32_getreg(STM32_OTGHS_HCINTMSK(chidx)); + + /* AND the two to get the set of enabled, pending HC interrupts */ + + pending &= regval; + uinfo("HCINTMSK%d: %08" PRIx32 " pending: %08" PRIx32 "\n", + chidx, regval, pending); + + /* Check for a pending ACK response received/transmitted interrupt */ + + if ((pending & OTGHS_HCINT_ACK) != 0) + { + /* Clear the pending the ACK response received/transmitted interrupt */ + + stm32_putreg(STM32_OTGHS_HCINT(chidx), OTGHS_HCINT_ACK); + } + + /* Check for a pending STALL response receive (STALL) interrupt */ + + else if ((pending & OTGHS_HCINT_STALL) != 0) + { + /* Clear the NAK and STALL Conditions. */ + + stm32_putreg(STM32_OTGHS_HCINT(chidx), + OTGHS_HCINT_NAK | OTGHS_HCINT_STALL); + + /* Halt the channel when a STALL, TXERR, BBERR or DTERR interrupt is + * received on the channel. + */ + + stm32_chan_halt(priv, chidx, CHREASON_STALL); + + /* When there is a STALL, clear any pending NAK so that it is not + * processed below. + */ + + pending &= ~OTGHS_HCINT_NAK; + } + + /* Check for a pending Data Toggle ERRor (DTERR) interrupt */ + + else if ((pending & OTGHS_HCINT_DTERR) != 0) + { + /* Halt the channel when a STALL, TXERR, BBERR or DTERR interrupt is + * received on the channel. + */ + + stm32_chan_halt(priv, chidx, CHREASON_DTERR); + + /* Clear the NAK and data toggle error conditions */ + + stm32_putreg(STM32_OTGHS_HCINT(chidx), + OTGHS_HCINT_NAK | OTGHS_HCINT_DTERR); + } + + /* Check for a pending FRaMe OverRun (FRMOR) interrupt */ + + if ((pending & OTGHS_HCINT_FRMOR) != 0) + { + /* Halt the channel -- the CHH interrupt is expected next */ + + stm32_chan_halt(priv, chidx, CHREASON_FRMOR); + + /* Clear the FRaMe OverRun (FRMOR) condition */ + + stm32_putreg(STM32_OTGHS_HCINT(chidx), OTGHS_HCINT_FRMOR); + } + + /* Check for a pending TransFeR Completed (XFRC) interrupt */ + + else if ((pending & OTGHS_HCINT_XFRC) != 0) + { + /* Clear the TransFeR Completed (XFRC) condition */ + + stm32_putreg(STM32_OTGHS_HCINT(chidx), OTGHS_HCINT_XFRC); + + /* Then handle the transfer completion event based on the endpoint */ + + if (chan->eptype == OTGHS_EPTYPE_CTRL || + chan->eptype == OTGHS_EPTYPE_BULK) + { + /* Halt the channel -- the CHH interrupt is expected next */ + + stm32_chan_halt(priv, chidx, CHREASON_XFRC); + + /* Clear any pending NAK condition. The 'indata1' data toggle + * should have been appropriately updated by the RxFIFO + * logic as each packet was received. + */ + + stm32_putreg(STM32_OTGHS_HCINT(chidx), OTGHS_HCINT_NAK); + } + else if (chan->eptype == OTGHS_EPTYPE_INTR) + { + /* Force the next transfer on an ODD frame */ + + regval = stm32_getreg(STM32_OTGHS_HCCHAR(chidx)); + regval |= OTGHS_HCCHAR_ODDFRM; + stm32_putreg(STM32_OTGHS_HCCHAR(chidx), regval); + + /* Set the request done state */ + + chan->result = OK; + } + } + + /* Check for a pending CHannel Halted (CHH) interrupt */ + + else if ((pending & OTGHS_HCINT_CHH) != 0) + { + /* Mask the CHannel Halted (CHH) interrupt */ + + regval = stm32_getreg(STM32_OTGHS_HCINTMSK(chidx)); + regval &= ~OTGHS_HCINT_CHH; + stm32_putreg(STM32_OTGHS_HCINTMSK(chidx), regval); + + /* Update the request state based on the host state machine state */ + + if (chan->chreason == CHREASON_XFRC) + { + /* Set the request done result */ + + chan->result = OK; + } + else if (chan->chreason == CHREASON_STALL) + { + /* Set the request stall result */ + + chan->result = EPERM; + } + else if ((chan->chreason == CHREASON_TXERR) || + (chan->chreason == CHREASON_DTERR)) + { + /* Set the request I/O error result */ + + chan->result = EIO; + } + else if (chan->chreason == CHREASON_NAK) + { + /* Set the NAK error result */ + + chan->result = EAGAIN; + } + else /* if (chan->chreason == CHREASON_FRMOR) */ + { + /* Set the frame overrun error result */ + + chan->result = EPIPE; + } + + /* Clear the CHannel Halted (CHH) condition */ + + stm32_putreg(STM32_OTGHS_HCINT(chidx), OTGHS_HCINT_CHH); + } + + /* Check for a pending Transaction ERror (TXERR) interrupt */ + + else if ((pending & OTGHS_HCINT_TXERR) != 0) + { + /* Halt the channel when a STALL, TXERR, BBERR or DTERR interrupt is + * received on the channel. + */ + + stm32_chan_halt(priv, chidx, CHREASON_TXERR); + + /* Clear the Transaction ERror (TXERR) condition */ + + stm32_putreg(STM32_OTGHS_HCINT(chidx), OTGHS_HCINT_TXERR); + } + + /* Check for a pending NAK response received (NAK) interrupt */ + + else if ((pending & OTGHS_HCINT_NAK) != 0) + { + /* For a BULK transfer, the hardware is capable of retrying + * automatically on a NAK. However, this is not always + * what we need to do. So we always halt the transfer and + * return control to high level logic in the event of a NAK. + */ + +#if 1 + /* Halt the interrupt channel */ + + if (chan->eptype == OTGHS_EPTYPE_INTR || + chan->eptype == OTGHS_EPTYPE_BULK) + { + /* Halt the channel -- the CHH interrupt is expected next */ + + stm32_chan_halt(priv, chidx, CHREASON_NAK); + } + + /* Re-activate CTRL and BULK channels. + * + * REVISIT: This can cdause a lot of intedrrupts! + * REVISIT: BULK endpoints are not re-activated. + */ + + else if (chan->eptype == OTGHS_EPTYPE_CTRL) + { + /* Re-activate the channel by clearing CHDIS and assuring that + * CHENA is set + * + * TODO: set channel reason to NACK? + */ + + regval = stm32_getreg(STM32_OTGHS_HCCHAR(chidx)); + regval |= OTGHS_HCCHAR_CHENA; + regval &= ~OTGHS_HCCHAR_CHDIS; + stm32_putreg(STM32_OTGHS_HCCHAR(chidx), regval); + } + +#else + /* Halt all transfers on the NAK -- CHH interrupt is expected next */ + + stm32_chan_halt(priv, chidx, CHREASON_NAK); +#endif + + /* Clear the NAK condition */ + + stm32_putreg(STM32_OTGHS_HCINT(chidx), OTGHS_HCINT_NAK); + } + + /* Check for a transfer complete event */ + + stm32_chan_wakeup(priv, chan); +} + +/**************************************************************************** + * Name: stm32_gint_hcoutisr + * + * Description: + * USB OTG HS host OUT channels interrupt handler + * + * One the completion of the transfer, the channel result byte may be set + * as follows: + * + * OK - Transfer completed successfully + * EAGAIN - If devices NAKs the transfer or NYET occurs + * EPERM - If the endpoint stalls + * EIO - On a TX or data toggle error + * EPIPE - Frame overrun + * + * EBUSY in the result field indicates that the transfer has not completed. + * + ****************************************************************************/ + +static inline void stm32_gint_hcoutisr(struct stm32_usbhost_s *priv, + int chidx) +{ + struct stm32_chan_s *chan = &priv->chan[chidx]; + uint32_t regval; + uint32_t pending; + + /* Read the HCINT register to get the pending HC interrupts. Read the + * HCINTMSK register to get the set of enabled HC interrupts. + */ + + pending = stm32_getreg(STM32_OTGHS_HCINT(chidx)); + regval = stm32_getreg(STM32_OTGHS_HCINTMSK(chidx)); + + /* AND the two to get the set of enabled, pending HC interrupts */ + + pending &= regval; + uinfo("HCINTMSK%d: %08" PRIx32 " pending: %08" PRIx32 "\n", + chidx, regval, pending); + + /* Check for a pending ACK response received/transmitted interrupt */ + + if ((pending & OTGHS_HCINT_ACK) != 0) + { + /* Clear the pending the ACK response received/transmitted interrupt */ + + stm32_putreg(STM32_OTGHS_HCINT(chidx), OTGHS_HCINT_ACK); + } + + /* Check for a pending FRaMe OverRun (FRMOR) interrupt */ + + else if ((pending & OTGHS_HCINT_FRMOR) != 0) + { + /* Halt the channel (probably not necessary for FRMOR) */ + + stm32_chan_halt(priv, chidx, CHREASON_FRMOR); + + /* Clear the pending the FRaMe OverRun (FRMOR) interrupt */ + + stm32_putreg(STM32_OTGHS_HCINT(chidx), OTGHS_HCINT_FRMOR); + } + + /* Check for a pending TransFeR Completed (XFRC) interrupt */ + + else if ((pending & OTGHS_HCINT_XFRC) != 0) + { + /* Decrement the number of bytes remaining by the number of + * bytes that were "in-flight". + */ + + priv->chan[chidx].buffer += priv->chan[chidx].inflight; + priv->chan[chidx].xfrd += priv->chan[chidx].inflight; + priv->chan[chidx].inflight = 0; + + /* Halt the channel -- the CHH interrupt is expected next */ + + stm32_chan_halt(priv, chidx, CHREASON_XFRC); + + /* Clear the pending the TransFeR Completed (XFRC) interrupt */ + + stm32_putreg(STM32_OTGHS_HCINT(chidx), OTGHS_HCINT_XFRC); + } + + /* Check for a pending STALL response receive (STALL) interrupt */ + + else if ((pending & OTGHS_HCINT_STALL) != 0) + { + /* Clear the pending the STALL response receive (STALL) interrupt */ + + stm32_putreg(STM32_OTGHS_HCINT(chidx), OTGHS_HCINT_STALL); + + /* Halt the channel when a STALL, TXERR, BBERR or DTERR interrupt is + * received on the channel. + */ + + stm32_chan_halt(priv, chidx, CHREASON_STALL); + } + + /* Check for a pending NAK response received (NAK) interrupt */ + + else if ((pending & OTGHS_HCINT_NAK) != 0) + { + /* Halt the channel -- the CHH interrupt is expected next */ + + stm32_chan_halt(priv, chidx, CHREASON_NAK); + + /* Clear the pending the NAK response received (NAK) interrupt */ + + stm32_putreg(STM32_OTGHS_HCINT(chidx), OTGHS_HCINT_NAK); + } + + /* Check for a pending Transaction ERror (TXERR) interrupt */ + + else if ((pending & OTGHS_HCINT_TXERR) != 0) + { + /* Halt the channel when a STALL, TXERR, BBERR or DTERR interrupt is + * received on the channel. + */ + + stm32_chan_halt(priv, chidx, CHREASON_TXERR); + + /* Clear the pending the Transaction ERror (TXERR) interrupt */ + + stm32_putreg(STM32_OTGHS_HCINT(chidx), OTGHS_HCINT_TXERR); + } + + /* Check for a NYET interrupt */ + +#if 0 /* NYET is a reserved bit in the HCINT register */ + else if ((pending & OTGHS_HCINT_NYET) != 0) + { + /* Halt the channel */ + + stm32_chan_halt(priv, chidx, CHREASON_NYET); + + /* Clear the pending the NYET interrupt */ + + stm32_putreg(STM32_OTGHS_HCINT(chidx), OTGHS_HCINT_NYET); + } +#endif + + /* Check for a pending Data Toggle ERRor (DTERR) interrupt */ + + else if (pending & OTGHS_HCINT_DTERR) + { + /* Halt the channel when a STALL, TXERR, BBERR or DTERR interrupt is + * received on the channel. + */ + + stm32_chan_halt(priv, chidx, CHREASON_DTERR); + + /* Clear the pending the Data Toggle ERRor (DTERR) and NAK interrupts */ + + stm32_putreg(STM32_OTGHS_HCINT(chidx), + OTGHS_HCINT_DTERR | OTGHS_HCINT_NAK); + } + + /* Check for a pending CHannel Halted (CHH) interrupt */ + + else if ((pending & OTGHS_HCINT_CHH) != 0) + { + /* Mask the CHannel Halted (CHH) interrupt */ + + regval = stm32_getreg(STM32_OTGHS_HCINTMSK(chidx)); + regval &= ~OTGHS_HCINT_CHH; + stm32_putreg(STM32_OTGHS_HCINTMSK(chidx), regval); + + if (chan->chreason == CHREASON_XFRC) + { + /* Set the request done result */ + + chan->result = OK; + + /* Read the HCCHAR register to get the HCCHAR register to get + * the endpoint type. + */ + + regval = stm32_getreg(STM32_OTGHS_HCCHAR(chidx)); + + /* Is it a bulk endpoint? Were an odd number of packets + * transferred? + */ + + if ((regval & OTGHS_HCCHAR_EPTYP_MASK) == + OTGHS_HCCHAR_EPTYP_BULK && + (chan->npackets & 1) != 0) + { + /* Yes to both... toggle the data out PID */ + + chan->outdata1 ^= true; + } + } + else if (chan->chreason == CHREASON_NAK || + chan->chreason == CHREASON_NYET) + { + /* Set the try again later result */ + + chan->result = EAGAIN; + } + else if (chan->chreason == CHREASON_STALL) + { + /* Set the request stall result */ + + chan->result = EPERM; + } + else if ((chan->chreason == CHREASON_TXERR) || + (chan->chreason == CHREASON_DTERR)) + { + /* Set the I/O failure result */ + + chan->result = EIO; + } + else /* if (chan->chreason == CHREASON_FRMOR) */ + { + /* Set the frame error result */ + + chan->result = EPIPE; + } + + /* Clear the pending the CHannel Halted (CHH) interrupt */ + + stm32_putreg(STM32_OTGHS_HCINT(chidx), OTGHS_HCINT_CHH); + } + + /* Check for a transfer complete event */ + + stm32_chan_wakeup(priv, chan); +} + +/**************************************************************************** + * Name: stm32_gint_connected + * + * Description: + * Handle a connection event. + * + ****************************************************************************/ + +static void stm32_gint_connected(struct stm32_usbhost_s *priv) +{ + /* We we previously disconnected? */ + + if (!priv->connected) + { + /* Yes.. then now we are connected */ + + usbhost_vtrace1(OTGHS_VTRACE1_CONNECTED, 0); + priv->connected = true; + priv->change = true; + DEBUGASSERT(priv->smstate == SMSTATE_DETACHED); + + /* Notify any waiters */ + + priv->smstate = SMSTATE_ATTACHED; + if (priv->pscwait) + { + nxsem_post(&priv->pscsem); + priv->pscwait = false; + } + } +} + +/**************************************************************************** + * Name: stm32_gint_disconnected + * + * Description: + * Handle a disconnection event. + * + ****************************************************************************/ + +static void stm32_gint_disconnected(struct stm32_usbhost_s *priv) +{ + /* Were we previously connected? */ + + if (priv->connected) + { + /* Yes.. then we no longer connected */ + + usbhost_vtrace1(OTGHS_VTRACE1_DISCONNECTED, 0); + + /* Are we bound to a class driver? */ + + if (priv->rhport.hport.devclass) + { + /* Yes.. Disconnect the class driver */ + + CLASS_DISCONNECTED(priv->rhport.hport.devclass); + priv->rhport.hport.devclass = NULL; + } + + /* Re-Initialize Host for new Enumeration */ + + priv->smstate = SMSTATE_DETACHED; + priv->connected = false; + priv->change = true; + stm32_chan_freeall(priv); + + priv->rhport.hport.speed = USB_SPEED_FULL; + priv->rhport.hport.funcaddr = 0; + + /* Notify any waiters that there is a change in the connection state */ + + if (priv->pscwait) + { + nxsem_post(&priv->pscsem); + priv->pscwait = false; + } + } +} + +/**************************************************************************** + * Name: stm32_gint_sofisr + * + * Description: + * USB OTG HS start-of-frame interrupt handler + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_OTGHS_SOFINTR +static inline void stm32_gint_sofisr(struct stm32_usbhost_s *priv) +{ + /* Handle SOF interrupt */ + +#warning "Do what?" + + /* Clear pending SOF interrupt */ + + stm32_putreg(STM32_OTGHS_GINTSTS, OTGHS_GINT_SOF); +} +#endif + +/**************************************************************************** + * Name: stm32_gint_rxflvlisr + * + * Description: + * USB OTG HS RxFIFO non-empty interrupt handler + * + ****************************************************************************/ + +static inline void stm32_gint_rxflvlisr(struct stm32_usbhost_s *priv) +{ + uint32_t *dest; + uint32_t grxsts; + uint32_t intmsk; + uint32_t hcchar; + uint32_t hctsiz; + uint32_t fifo; + int bcnt; + int bcnt32; + int chidx; + int i; + + /* Disable the RxFIFO non-empty interrupt */ + + intmsk = stm32_getreg(STM32_OTGHS_GINTMSK); + intmsk &= ~OTGHS_GINT_RXFLVL; + stm32_putreg(STM32_OTGHS_GINTMSK, intmsk); + + /* Read and pop the next status from the Rx FIFO */ + + grxsts = stm32_getreg(STM32_OTGHS_GRXSTSP); + uinfo("GRXSTS: %08" PRIx32 "\n", grxsts); + + /* Isolate the channel number/index in the status word */ + + chidx = (grxsts & OTGHS_GRXSTSH_CHNUM_MASK) >> OTGHS_GRXSTSH_CHNUM_SHIFT; + + /* Get the host channel characteristics register (HCCHAR) */ + + hcchar = stm32_getreg(STM32_OTGHS_HCCHAR(chidx)); + + /* Then process the interrupt according to the packet status */ + + switch (grxsts & OTGHS_GRXSTSH_PKTSTS_MASK) + { + case OTGHS_GRXSTSH_PKTSTS_INRECVD: /* IN data packet received */ + { + /* Read the data into the host buffer. */ + + bcnt = (grxsts & OTGHS_GRXSTSH_BCNT_MASK) >> + OTGHS_GRXSTSH_BCNT_SHIFT; + if (bcnt > 0 && priv->chan[chidx].buffer != NULL) + { + /* Transfer the packet from the Rx FIFO into the user buffer */ + + dest = (uint32_t *)priv->chan[chidx].buffer; + fifo = STM32_OTGHS_DFIFO_HCH(0); + bcnt32 = (bcnt + 3) >> 2; + + for (i = 0; i < bcnt32; i++) + { + *dest++ = stm32_getreg(fifo); + } + + stm32_pktdump("Received", priv->chan[chidx].buffer, bcnt); + + /* Toggle the IN data pid (Used by Bulk and INTR only) */ + + priv->chan[chidx].indata1 ^= true; + + /* Manage multiple packet transfers */ + + priv->chan[chidx].buffer += bcnt; + priv->chan[chidx].xfrd += bcnt; + + /* Check if more packets are expected */ + + hctsiz = stm32_getreg(STM32_OTGHS_HCTSIZ(chidx)); + if ((hctsiz & OTGHS_HCTSIZ_PKTCNT_MASK) != 0) + { + /* Re-activate the channel when more packets are expected */ + + hcchar |= OTGHS_HCCHAR_CHENA; + hcchar &= ~OTGHS_HCCHAR_CHDIS; + stm32_putreg(STM32_OTGHS_HCCHAR(chidx), hcchar); + } + } + } + break; + + case OTGHS_GRXSTSH_PKTSTS_INDONE: /* IN transfer completed */ + case OTGHS_GRXSTSH_PKTSTS_DTOGERR: /* Data toggle error */ + case OTGHS_GRXSTSH_PKTSTS_HALTED: /* Channel halted */ + default: + break; + } + + /* Re-enable the RxFIFO non-empty interrupt */ + + intmsk |= OTGHS_GINT_RXFLVL; + stm32_putreg(STM32_OTGHS_GINTMSK, intmsk); +} + +/**************************************************************************** + * Name: stm32_gint_nptxfeisr + * + * Description: + * USB OTG HS non-periodic TxFIFO empty interrupt handler + * + ****************************************************************************/ + +static inline void stm32_gint_nptxfeisr(struct stm32_usbhost_s *priv) +{ + struct stm32_chan_s *chan; + uint32_t regval; + unsigned int wrsize; + unsigned int avail; + unsigned int chidx; + + /* Recover the index of the channel that is waiting for space in the Tx + * FIFO. + */ + + chidx = priv->chidx; + chan = &priv->chan[chidx]; + + /* Reduce the buffer size by the number of bytes that were previously + * placed in the Tx FIFO. + */ + + chan->buffer += chan->inflight; + chan->xfrd += chan->inflight; + chan->inflight = 0; + + /* If we have now transferred the entire buffer, then this transfer is + * complete (this case really should never happen because we disable + * the NPTXFE interrupt on the final packet). + */ + + if (chan->xfrd >= chan->buflen) + { + /* Disable further Tx FIFO empty interrupts and bail. */ + + stm32_modifyreg(STM32_OTGHS_GINTMSK, OTGHS_GINT_NPTXFE, 0); + return; + } + + /* Read the status from the top of the non-periodic TxFIFO */ + + regval = stm32_getreg(STM32_OTGHS_HNPTXSTS); + + /* Extract the number of bytes available in the non-periodic Tx FIFO. */ + + avail = ((regval & OTGHS_HNPTXSTS_NPTXFSAV_MASK) >> + OTGHS_HNPTXSTS_NPTXFSAV_SHIFT) << 2; + + /* Get the size to put in the Tx FIFO now */ + + wrsize = chan->buflen - chan->xfrd; + + /* Get minimal size packet that can be sent. Something is seriously + * configured wrong if one packet will not fit into the empty Tx FIFO. + */ + + DEBUGASSERT(wrsize > 0 && avail >= MIN(wrsize, chan->maxpacket)); + if (wrsize > avail) + { + /* Clip the write size to the number of full, max sized packets + * that will fit in the Tx FIFO. + */ + + unsigned int wrpackets = avail / chan->maxpacket; + wrsize = wrpackets * chan->maxpacket; + } + + /* Otherwise, this will be the last packet to be sent in this transaction. + * We now need to disable further NPTXFE interrupts. + */ + + else + { + stm32_modifyreg(STM32_OTGHS_GINTMSK, OTGHS_GINT_NPTXFE, 0); + } + + /* Write the next group of packets into the Tx FIFO */ + + uinfo("HNPTXSTS: %08" PRIx32 + " chidx: %d avail: %d buflen: %d xfrd: %dwrsize: %d\n", + regval, chidx, avail, chan->buflen, chan->xfrd, wrsize); + + stm32_gint_wrpacket(priv, chan->buffer, chidx, wrsize); +} + +/**************************************************************************** + * Name: stm32_gint_ptxfeisr + * + * Description: + * USB OTG HS periodic TxFIFO empty interrupt handler + * + ****************************************************************************/ + +static inline void stm32_gint_ptxfeisr(struct stm32_usbhost_s *priv) +{ + struct stm32_chan_s *chan; + uint32_t regval; + unsigned int wrsize; + unsigned int avail; + unsigned int chidx; + + /* Recover the index of the channel that is waiting for space in the Tx + * FIFO. + */ + + chidx = priv->chidx; + chan = &priv->chan[chidx]; + + /* Reduce the buffer size by the number of bytes that were previously + * placed in the Tx FIFO. + */ + + chan->buffer += chan->inflight; + chan->xfrd += chan->inflight; + chan->inflight = 0; + + /* If we have now transferred the entire buffer, then this transfer is + * complete (this case really should never happen because we disable + * the PTXFE interrupt on the final packet). + */ + + if (chan->xfrd >= chan->buflen) + { + /* Disable further Tx FIFO empty interrupts and bail. */ + + stm32_modifyreg(STM32_OTGHS_GINTMSK, OTGHS_GINT_PTXFE, 0); + return; + } + + /* Read the status from the top of the periodic TxFIFO */ + + regval = stm32_getreg(STM32_OTGHS_HPTXSTS); + + /* Extract the number of bytes available in the periodic Tx FIFO. */ + + avail = ((regval & OTGHS_HPTXSTS_PTXFSAVL_MASK) >> + OTGHS_HPTXSTS_PTXFSAVL_SHIFT) << 2; + + /* Get the size to put in the Tx FIFO now */ + + wrsize = chan->buflen - chan->xfrd; + + /* Get minimal size packet that can be sent. Something is seriously + * configured wrong if one packet will not fit into the empty Tx FIFO. + */ + + DEBUGASSERT(wrsize > 0 && avail >= MIN(wrsize, chan->maxpacket)); + if (wrsize > avail) + { + /* Clip the write size to the number of full, max sized packets + * that will fit in the Tx FIFO. + */ + + unsigned int wrpackets = avail / chan->maxpacket; + wrsize = wrpackets * chan->maxpacket; + } + + /* Otherwise, this will be the last packet to be sent in this transaction. + * We now need to disable further PTXFE interrupts. + */ + + else + { + stm32_modifyreg(STM32_OTGHS_GINTMSK, OTGHS_GINT_PTXFE, 0); + } + + /* Write the next group of packets into the Tx FIFO */ + + uinfo("HPTXSTS: %08" PRIx32 + " chidx: %d avail: %d buflen: %d xfrd: %d wrsize: %d\n", + regval, chidx, avail, chan->buflen, chan->xfrd, wrsize); + + stm32_gint_wrpacket(priv, chan->buffer, chidx, wrsize); +} + +/**************************************************************************** + * Name: stm32_gint_hcisr + * + * Description: + * USB OTG HS host channels interrupt handler + * + ****************************************************************************/ + +static inline void stm32_gint_hcisr(struct stm32_usbhost_s *priv) +{ + uint32_t haint; + uint32_t hcchar; + int i = 0; + + /* Read the Host all channels interrupt register and test each bit in the + * register. Each bit i, i=0...(STM32_NHOST_CHANNELS-1), corresponds to + * a pending interrupt on channel i. + */ + + haint = stm32_getreg(STM32_OTGHS_HAINT); + for (i = 0; i < STM32_NHOST_CHANNELS; i++) + { + /* Is an interrupt pending on this channel? */ + + if ((haint & OTGHS_HAINT(i)) != 0) + { + /* Yes... read the HCCHAR register to get the direction bit */ + + hcchar = stm32_getreg(STM32_OTGHS_HCCHAR(i)); + + /* Was this an interrupt on an IN or an OUT channel? */ + + if ((hcchar & OTGHS_HCCHAR_EPDIR) != 0) + { + /* Handle the HC IN channel interrupt */ + + stm32_gint_hcinisr(priv, i); + } + else + { + /* Handle the HC OUT channel interrupt */ + + stm32_gint_hcoutisr(priv, i); + } + } + } +} + +/**************************************************************************** + * Name: stm32_gint_hprtisr + * + * Description: + * USB OTG HS host port interrupt handler + * + ****************************************************************************/ + +static inline void stm32_gint_hprtisr(struct stm32_usbhost_s *priv) +{ + uint32_t hprt; + uint32_t newhprt; + uint32_t hcfg; + + usbhost_vtrace1(OTGHS_VTRACE1_GINT_HPRT, 0); + + /* Read the port status and control register (HPRT) */ + + hprt = stm32_getreg(STM32_OTGHS_HPRT); + + /* Setup to clear the interrupt bits in GINTSTS by setting the + * corresponding bits in the HPRT. The HCINT interrupt bit is cleared + * when the appropriate status bits in the HPRT register are cleared. + */ + + newhprt = hprt & ~(OTGHS_HPRT_PENA | OTGHS_HPRT_PCDET | + OTGHS_HPRT_PENCHNG | OTGHS_HPRT_POCCHNG); + + /* Check for Port Over-urrent CHaNGe (POCCHNG) */ + + if ((hprt & OTGHS_HPRT_POCCHNG) != 0) + { + /* Set up to clear the POCCHNG status in the new HPRT contents. */ + + usbhost_vtrace1(OTGHS_VTRACE1_GINT_HPRT_POCCHNG, 0); + newhprt |= OTGHS_HPRT_POCCHNG; + } + + /* Check for Port Connect DETected (PCDET). The core sets this bit when a + * device connection is detected. + */ + + if ((hprt & OTGHS_HPRT_PCDET) != 0) + { + /* Set up to clear the PCDET status in the new HPRT contents. Then + * process the new connection event. + */ + + usbhost_vtrace1(OTGHS_VTRACE1_GINT_HPRT_PCDET, 0); + newhprt |= OTGHS_HPRT_PCDET; + stm32_portreset(priv); + stm32_gint_connected(priv); + } + + /* Check for Port Enable CHaNGed (PENCHNG) */ + + if ((hprt & OTGHS_HPRT_PENCHNG) != 0) + { + /* Set up to clear the PENCHNG status in the new HPRT contents. */ + + usbhost_vtrace1(OTGHS_VTRACE1_GINT_HPRT_PENCHNG, 0); + newhprt |= OTGHS_HPRT_PENCHNG; + + /* Was the port enabled? */ + + if ((hprt & OTGHS_HPRT_PENA) != 0) + { + /* Yes.. handle the new connection event */ + + stm32_gint_connected(priv); + + /* Check the Host ConFiGuration register (HCFG) */ + + hcfg = stm32_getreg(STM32_OTGHS_HCFG); + + /* Is this a low speed or full speed connection (OTG HS does not + * support high speed) + */ + + if ((hprt & OTGHS_HPRT_PSPD_MASK) == OTGHS_HPRT_PSPD_LS) + { + /* Set the Host Frame Interval Register for the 6KHz speed */ + + usbhost_vtrace1(OTGHS_VTRACE1_GINT_HPRT_LSDEV, 0); + stm32_putreg(STM32_OTGHS_HFIR, 6000); + + /* Are we switching from HS to LS? */ + + if ((hcfg & OTGHS_HCFG_FSLSPCS_MASK) != + OTGHS_HCFG_FSLSPCS_LS6MHz) + { + usbhost_vtrace1(OTGHS_VTRACE1_GINT_HPRT_FSLSSW, 0); + + /* Yes... configure for LS */ + + hcfg &= ~OTGHS_HCFG_FSLSPCS_MASK; + hcfg |= OTGHS_HCFG_FSLSPCS_LS6MHz; + stm32_putreg(STM32_OTGHS_HCFG, hcfg); + + /* And reset the port */ + + stm32_portreset(priv); + } + } + else /* if ((hprt & OTGHS_HPRT_PSPD_MASK) == OTGHS_HPRT_PSPD_HS) */ + { + usbhost_vtrace1(OTGHS_VTRACE1_GINT_HPRT_FSDEV, 0); + stm32_putreg(STM32_OTGHS_HFIR, 48000); + + /* Are we switching from LS to HS? */ + + if ((hcfg & OTGHS_HCFG_FSLSPCS_MASK) != + OTGHS_HCFG_FSLSPCS_FS48MHz) + { + usbhost_vtrace1(OTGHS_VTRACE1_GINT_HPRT_LSFSSW, 0); + + /* Yes... configure for HS */ + + hcfg &= ~OTGHS_HCFG_FSLSPCS_MASK; + hcfg |= OTGHS_HCFG_FSLSPCS_FS48MHz; + stm32_putreg(STM32_OTGHS_HCFG, hcfg); + + /* And reset the port */ + + stm32_portreset(priv); + } + } + } + } + + /* Clear port interrupts by setting bits in the HPRT */ + + stm32_putreg(STM32_OTGHS_HPRT, newhprt); +} + +/**************************************************************************** + * Name: stm32_gint_discisr + * + * Description: + * USB OTG HS disconnect detected interrupt handler + * + ****************************************************************************/ + +static inline void stm32_gint_discisr(struct stm32_usbhost_s *priv) +{ + /* Handle the disconnection event */ + + stm32_gint_disconnected(priv); + + /* Clear the dicsonnect interrupt */ + + stm32_putreg(STM32_OTGHS_GINTSTS, OTGHS_GINT_DISC); +} + +/**************************************************************************** + * Name: stm32_gint_ipxfrisr + * + * Description: + * USB OTG HS incomplete periodic interrupt handler + * + ****************************************************************************/ + +static inline void stm32_gint_ipxfrisr(struct stm32_usbhost_s *priv) +{ + uint32_t regval; + + /* CHENA : Set to enable the channel + * CHDIS : Set to stop transmitting/receiving data on a channel + */ + + regval = stm32_getreg(STM32_OTGHS_HCCHAR(0)); + regval |= (OTGHS_HCCHAR_CHDIS | OTGHS_HCCHAR_CHENA); + stm32_putreg(STM32_OTGHS_HCCHAR(0), regval); + + /* Clear the incomplete isochronous OUT interrupt */ + + stm32_putreg(STM32_OTGHS_GINTSTS, OTGHS_GINT_IPXFR); +} + +/**************************************************************************** + * Name: stm32_gint_isr + * + * Description: + * USB OTG HS global interrupt handler + * + ****************************************************************************/ + +static int stm32_gint_isr(int irq, void *context, void *arg) +{ + /* At present, there is only support for a single OTG HS host. Hence it is + * pre-allocated as g_usbhost. However, in most code, the private data + * structure will be referenced using the 'priv' pointer (rather than the + * global data) in order to simplify any future support for multiple + * devices. + */ + + struct stm32_usbhost_s *priv = &g_usbhost; + uint32_t pending; + + /* If OTG were supported, we would need to check if we are in host or + * device mode when the global interrupt occurs. Here we support only + * host mode + */ + + /* Loop while there are pending interrupts to process. This loop may save + * a little interrupt handling overhead. + */ + + for (; ; ) + { + /* Get the unmasked bits in the GINT status */ + + pending = stm32_getreg(STM32_OTGHS_GINTSTS); + pending &= stm32_getreg(STM32_OTGHS_GINTMSK); + + /* Return from the interrupt when there are no further pending + * interrupts. + */ + + if (pending == 0) + { + return OK; + } + + /* Otherwise, process each pending, unmasked GINT interrupts */ + + /* Handle the start of frame interrupt */ + +#ifdef CONFIG_STM32_OTGHS_SOFINTR + if ((pending & OTGHS_GINT_SOF) != 0) + { + usbhost_vtrace1(OTGHS_VTRACE1_GINT_SOF, 0); + stm32_gint_sofisr(priv); + } +#endif + + /* Handle the RxFIFO non-empty interrupt */ + + if ((pending & OTGHS_GINT_RXFLVL) != 0) + { + usbhost_vtrace1(OTGHS_VTRACE1_GINT_RXFLVL, 0); + stm32_gint_rxflvlisr(priv); + } + + /* Handle the non-periodic TxFIFO empty interrupt */ + + if ((pending & OTGHS_GINT_NPTXFE) != 0) + { + usbhost_vtrace1(OTGHS_VTRACE1_GINT_NPTXFE, 0); + stm32_gint_nptxfeisr(priv); + } + + /* Handle the periodic TxFIFO empty interrupt */ + + if ((pending & OTGHS_GINT_PTXFE) != 0) + { + usbhost_vtrace1(OTGHS_VTRACE1_GINT_PTXFE, 0); + stm32_gint_ptxfeisr(priv); + } + + /* Handle the host channels interrupt */ + + if ((pending & OTGHS_GINT_HC) != 0) + { + usbhost_vtrace1(OTGHS_VTRACE1_GINT_HC, 0); + stm32_gint_hcisr(priv); + } + + /* Handle the host port interrupt */ + + if ((pending & OTGHS_GINT_HPRT) != 0) + { + stm32_gint_hprtisr(priv); + } + + /* Handle the disconnect detected interrupt */ + + if ((pending & OTGHS_GINT_DISC) != 0) + { + usbhost_vtrace1(OTGHS_VTRACE1_GINT_DISC, 0); + stm32_gint_discisr(priv); + } + + /* Handle the incomplete periodic transfer */ + + if ((pending & OTGHS_GINT_IPXFR) != 0) + { + usbhost_vtrace1(OTGHS_VTRACE1_GINT_IPXFR, 0); + stm32_gint_ipxfrisr(priv); + } + } + + /* We won't get here */ + + return OK; +} + +/**************************************************************************** + * Name: stm32_gint_enable and stm32_gint_disable + * + * Description: + * Respectively enable or disable the global OTG HS interrupt. + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void stm32_gint_enable(void) +{ + uint32_t regval; + + /* Set the GINTMSK bit to unmask the interrupt */ + + regval = stm32_getreg(STM32_OTGHS_GAHBCFG); + regval |= OTGHS_GAHBCFG_GINTMSK; + stm32_putreg(STM32_OTGHS_GAHBCFG, regval); +} + +static void stm32_gint_disable(void) +{ + uint32_t regval; + + /* Clear the GINTMSK bit to mask the interrupt */ + + regval = stm32_getreg(STM32_OTGHS_GAHBCFG); + regval &= ~OTGHS_GAHBCFG_GINTMSK; + stm32_putreg(STM32_OTGHS_GAHBCFG, regval); +} + +/**************************************************************************** + * Name: stm32_hostinit_enable + * + * Description: + * Enable host interrupts. + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +static inline void stm32_hostinit_enable(void) +{ + uint32_t regval; + + /* Disable all interrupts. */ + + stm32_putreg(STM32_OTGHS_GINTMSK, 0); + + /* Clear any pending interrupts. */ + + stm32_putreg(STM32_OTGHS_GINTSTS, 0xffffffff); + + /* Clear any pending USB OTG Interrupts */ + + stm32_putreg(STM32_OTGHS_GOTGINT, 0xffffffff); + + /* Clear any pending USB OTG interrupts */ + + stm32_putreg(STM32_OTGHS_GINTSTS, 0xbfffffff); + + /* Enable the host interrupts */ + + /* Common interrupts: + * + * OTGHS_GINT_WKUP : Resume/remote wakeup detected interrupt + * OTGHS_GINT_USBSUSP : USB suspend + */ + + regval = (OTGHS_GINT_WKUP | OTGHS_GINT_USBSUSP); + + /* If OTG were supported, we would need to enable the following as well: + * + * OTGHS_GINT_OTG : OTG interrupt + * OTGHS_GINT_SRQ : Session request/new session detected interrupt + * OTGHS_GINT_CIDSCHG : Connector ID status change + */ + + /* Host-specific interrupts + * + * OTGHS_GINT_SOF : Start of frame + * OTGHS_GINT_RXFLVL : RxFIFO non-empty + * OTGHS_GINT_IISOOXFR : Incomplete isochronous OUT transfer + * OTGHS_GINT_HPRT : Host port interrupt + * OTGHS_GINT_HC : Host channels interrupt + * OTGHS_GINT_DISC : Disconnect detected interrupt + */ + +#ifdef CONFIG_STM32_OTGHS_SOFINTR + regval |= (OTGHS_GINT_SOF | OTGHS_GINT_RXFLVL | OTGHS_GINT_IISOOXFR | + OTGHS_GINT_HPRT | OTGHS_GINT_HC | OTGHS_GINT_DISC); +#else + regval |= (OTGHS_GINT_RXFLVL | OTGHS_GINT_IPXFR | OTGHS_GINT_HPRT | + OTGHS_GINT_HC | OTGHS_GINT_DISC); +#endif + stm32_putreg(STM32_OTGHS_GINTMSK, regval); +} + +/**************************************************************************** + * Name: stm32_txfe_enable + * + * Description: + * Enable Tx FIFO empty interrupts. This is necessary when the entire + * transfer will not fit into Tx FIFO. The transfer will then be completed + * when the Tx FIFO is empty. NOTE: The Tx FIFO interrupt is disabled + * the fifo empty interrupt handler when the transfer is complete. + * + * Input Parameters: + * priv - Driver state structure reference + * chidx - The channel that requires the Tx FIFO empty interrupt + * + * Returned Value: + * None + * + * Assumptions: + * Called from user task context. Interrupts must be disabled to assure + * exclusive access to the GINTMSK register. + * + ****************************************************************************/ + +static void stm32_txfe_enable(struct stm32_usbhost_s *priv, int chidx) +{ + struct stm32_chan_s *chan = &priv->chan[chidx]; + irqstate_t flags; + uint32_t regval; + + /* Disable all interrupts so that we have exclusive access to the GINTMSK + * (it would be sufficient just to disable the GINT interrupt). + */ + + flags = enter_critical_section(); + + /* Should we enable the periodic or non-peridic Tx FIFO empty interrupts */ + + regval = stm32_getreg(STM32_OTGHS_GINTMSK); + switch (chan->eptype) + { + default: + case OTGHS_EPTYPE_CTRL: /* Non periodic transfer */ + case OTGHS_EPTYPE_BULK: + regval |= OTGHS_GINT_NPTXFE; + break; + + case OTGHS_EPTYPE_INTR: /* Periodic transfer */ + case OTGHS_EPTYPE_ISOC: + regval |= OTGHS_GINT_PTXFE; + break; + } + + /* Enable interrupts */ + + stm32_putreg(STM32_OTGHS_GINTMSK, regval); + leave_critical_section(flags); +} + +/**************************************************************************** + * USB Host Controller Operations + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_wait + * + * Description: + * Wait for a device to be connected or disconnected to/from a hub port. + * + * Input Parameters: + * conn - The USB host connection instance obtained as a parameter from + * the call to the USB driver initialization logic. + * hport - The location to return the hub port descriptor that detected + * the connection related event. + * + * Returned Value: + * Zero (OK) is returned on success when a device is connected or + * disconnected. This function will not return until either (1) a device is + * connected or disconnect to/from any hub port or until (2) some failure + * occurs. On a failure, a negated errno value is returned indicating the + * nature of the failure + * + * Assumptions: + * - Called from a single thread so no mutual exclusion is required. + * - Never called from an interrupt handler. + * + ****************************************************************************/ + +static int stm32_wait(struct usbhost_connection_s *conn, + struct usbhost_hubport_s **hport) +{ + struct stm32_usbhost_s *priv = &g_usbhost; + struct usbhost_hubport_s *connport; + irqstate_t flags; + int ret; + + /* Loop until a change in connection state is detected */ + + flags = enter_critical_section(); + for (; ; ) + { + /* Is there a change in the connection state of the single root hub + * port? + */ + + if (priv->change) + { + connport = &priv->rhport.hport; + + /* Yes. Remember the new state */ + + connport->connected = priv->connected; + priv->change = false; + + /* And return the root hub port */ + + *hport = connport; + leave_critical_section(flags); + + uinfo("RHport Connected: %s\n", + connport->connected ? "YES" : "NO"); + return OK; + } + +#ifdef CONFIG_USBHOST_HUB + /* Is a device connected to an external hub? */ + + if (priv->hport) + { + /* Yes.. return the external hub port */ + + connport = (struct usbhost_hubport_s *)priv->hport; + priv->hport = NULL; + + *hport = connport; + leave_critical_section(flags); + + uinfo("Hub port Connected: %s\n", + connport->connected ? "YES" : "NO"); + return OK; + } +#endif + + /* Wait for the next connection event */ + + priv->pscwait = true; + ret = nxsem_wait_uninterruptible(&priv->pscsem); + if (ret < 0) + { + return ret; + } + } +} + +/**************************************************************************** + * Name: stm32_enumerate + * + * Description: + * Enumerate the connected device. As part of this enumeration process, + * the driver will (1) get the device's configuration descriptor, (2) + * extract the class ID info from the configuration descriptor, (3) call + * usbhost_findclass() to find the class that supports this device, (4) + * call the create() method on the struct usbhost_registry_s interface + * to get a class instance, and finally (5) call the connect() method + * of the struct usbhost_class_s interface. After that, the class is in + * charge of the sequence of operations. + * + * Input Parameters: + * conn - The USB host connection instance obtained as a parameter from + * the call to the USB driver initialization logic. + * hport - The descriptor of the hub port that has the newly connected + * device. + * + * Returned Value: + * On success, zero (OK) is returned. On a failure, a negated errno value + * is returned indicating the nature of the failure + * + * Assumptions: + * This function will *not* be called from an interrupt handler. + * + ****************************************************************************/ + +static int stm32_rh_enumerate(struct stm32_usbhost_s *priv, + struct usbhost_connection_s *conn, + struct usbhost_hubport_s *hport) +{ + uint32_t regval; + int ret; + + DEBUGASSERT(conn != NULL && hport != NULL && hport->port == 0); + + /* Are we connected to a device? The caller should have called the wait() + * method first to be assured that a device is connected. + */ + + while (!priv->connected) + { + /* No, return an error */ + + usbhost_trace1(OTGHS_TRACE1_DEVDISCONN, 0); + return -ENODEV; + } + + DEBUGASSERT(priv->smstate == SMSTATE_ATTACHED); + + /* USB 2.0 spec says at least 50ms delay before port reset. We wait + * 100ms. + */ + + nxsched_usleep(100 * 1000); + + /* Reset the host port */ + + stm32_portreset(priv); + + /* Get the current device speed */ + + regval = stm32_getreg(STM32_OTGHS_HPRT); + if ((regval & OTGHS_HPRT_PSPD_MASK) == OTGHS_HPRT_PSPD_LS) + { + priv->rhport.hport.speed = USB_SPEED_LOW; + } + else + { + priv->rhport.hport.speed = USB_SPEED_FULL; + } + + /* Allocate and initialize the root hub port EP0 channels */ + + ret = stm32_ctrlchan_alloc(priv, 0, 0, priv->rhport.hport.speed, + &priv->ep0); + if (ret < 0) + { + uerr("ERROR: Failed to allocate a control endpoint: %d\n", ret); + } + + return ret; +} + +static int stm32_enumerate(struct usbhost_connection_s *conn, + struct usbhost_hubport_s *hport) +{ + struct stm32_usbhost_s *priv = &g_usbhost; + int ret; + + DEBUGASSERT(hport); + + /* If this is a connection on the root hub, then we need to go to + * little more effort to get the device speed. If it is a connection + * on an external hub, then we already have that information. + */ + +#ifdef CONFIG_USBHOST_HUB + if (ROOTHUB(hport)) +#endif + { + ret = stm32_rh_enumerate(priv, conn, hport); + if (ret < 0) + { + return ret; + } + } + + /* Then let the common usbhost_enumerate do the real enumeration. */ + + uinfo("Enumerate the device\n"); + priv->smstate = SMSTATE_ENUM; + ret = usbhost_enumerate(hport, &hport->devclass); + + /* The enumeration may fail either because of some HCD interfaces failure + * or because the device class is not supported. In either case, we just + * need to perform the disconnection operation and make ready for a new + * enumeration. + */ + + if (ret < 0) + { + /* Return to the disconnected state */ + + uerr("ERROR: Enumeration failed: %d\n", ret); + stm32_gint_disconnected(priv); + } + + return ret; +} + +/**************************************************************************** + * Name: stm32_ep0configure + * + * Description: + * Configure endpoint 0. This method is normally used internally by the + * enumerate() method but is made available at the interface to support an + * external implementation of the enumeration logic. + * + * Input Parameters: + * drvr - The USB host driver instance obtained as a parameter from the + * call to the class create() method. + * ep0 - The (opaque) EP0 endpoint instance + * funcaddr - The USB address of the function containing the endpoint that + * EP0 controls + * speed - The speed of the port USB_SPEED_LOW, _FULL, or _HIGH + * maxpacketsize - The maximum number of bytes that can be sent to or + * received from the endpoint in a single data packet + * + * Returned Value: + * On success, zero (OK) is returned. On a failure, a negated errno value + * is returned indicating the nature of the failure + * + * Assumptions: + * This function will *not* be called from an interrupt handler. + * + ****************************************************************************/ + +static int stm32_ep0configure(struct usbhost_driver_s *drvr, + usbhost_ep_t ep0, uint8_t funcaddr, + uint8_t speed, uint16_t maxpacketsize) +{ + struct stm32_usbhost_s *priv = (struct stm32_usbhost_s *)drvr; + struct stm32_ctrlinfo_s *ep0info = (struct stm32_ctrlinfo_s *)ep0; + struct stm32_chan_s *chan; + int ret; + + DEBUGASSERT(drvr != NULL && ep0info != NULL && funcaddr < 128 && + maxpacketsize <= 64); + + /* We must have exclusive access to the USB host hardware and structures */ + + ret = nxmutex_lock(&priv->lock); + if (ret < 0) + { + return ret; + } + + /* Configure the EP0 OUT channel */ + + chan = &priv->chan[ep0info->outndx]; + chan->funcaddr = funcaddr; + chan->speed = speed; + chan->maxpacket = maxpacketsize; + + stm32_chan_configure(priv, ep0info->outndx); + + /* Configure the EP0 IN channel */ + + chan = &priv->chan[ep0info->inndx]; + chan->funcaddr = funcaddr; + chan->speed = speed; + chan->maxpacket = maxpacketsize; + + stm32_chan_configure(priv, ep0info->inndx); + + nxmutex_unlock(&priv->lock); + return OK; +} + +/**************************************************************************** + * Name: stm32_epalloc + * + * Description: + * Allocate and configure one endpoint. + * + * Input Parameters: + * drvr - The USB host driver instance obtained as a parameter from the + * call to the class create() method. + * epdesc - Describes the endpoint to be allocated. + * ep - A memory location provided by the caller in which to receive the + * allocated endpoint descriptor. + * + * Returned Value: + * On success, zero (OK) is returned. On a failure, a negated errno value + * is returned indicating the nature of the failure + * + * Assumptions: + * This function will *not* be called from an interrupt handler. + * + ****************************************************************************/ + +static int stm32_epalloc(struct usbhost_driver_s *drvr, + const struct usbhost_epdesc_s *epdesc, + usbhost_ep_t *ep) +{ + struct stm32_usbhost_s *priv = (struct stm32_usbhost_s *)drvr; + int ret; + + /* Sanity check. NOTE that this method should only be called if a device + * is connected (because we need a valid low speed indication). + */ + + DEBUGASSERT(drvr != 0 && epdesc != NULL && ep != NULL); + + /* We must have exclusive access to the USB host hardware and structures */ + + ret = nxmutex_lock(&priv->lock); + if (ret < 0) + { + return ret; + } + + /* Handler control pipes differently from other endpoint types. This is + * because the normal, "transfer" endpoints are unidirectional an require + * only a single channel. Control endpoints, however, are bi-diretional + * and require two channels, one for the IN and one for the OUT direction. + */ + + if (epdesc->xfrtype == OTGHS_EPTYPE_CTRL) + { + ret = stm32_ctrlep_alloc(priv, epdesc, ep); + } + else + { + ret = stm32_xfrep_alloc(priv, epdesc, ep); + } + + nxmutex_unlock(&priv->lock); + return ret; +} + +/**************************************************************************** + * Name: stm32_epfree + * + * Description: + * Free and endpoint previously allocated by DRVR_EPALLOC. + * + * Input Parameters: + * drvr - The USB host driver instance obtained as a parameter from the + * call to the class create() method. + * ep - The endpoint to be freed. + * + * Returned Value: + * On success, zero (OK) is returned. On a failure, a negated errno value + * is returned indicating the nature of the failure + * + * Assumptions: + * This function will *not* be called from an interrupt handler. + * + ****************************************************************************/ + +static int stm32_epfree(struct usbhost_driver_s *drvr, usbhost_ep_t ep) +{ + struct stm32_usbhost_s *priv = (struct stm32_usbhost_s *)drvr; + int ret; + + DEBUGASSERT(priv); + + /* We must have exclusive access to the USB host hardware and structures */ + + ret = nxmutex_lock(&priv->lock); + + /* A single channel is represent by an index in the range of 0 to + * STM32_MAX_TX_FIFOS. Otherwise, the ep must be a pointer to an allocated + * control endpoint structure. + */ + + if ((uintptr_t)ep < STM32_MAX_TX_FIFOS) + { + /* Halt the channel and mark the channel available */ + + stm32_chan_free(priv, (int)ep); + } + else + { + /* Halt both control channel and mark the channels available */ + + struct stm32_ctrlinfo_s *ctrlep = + (struct stm32_ctrlinfo_s *)ep; + + stm32_chan_free(priv, ctrlep->inndx); + stm32_chan_free(priv, ctrlep->outndx); + + /* And free the control endpoint container */ + + kmm_free(ctrlep); + } + + nxmutex_unlock(&priv->lock); + return ret; +} + +/**************************************************************************** + * Name: stm32_alloc + * + * Description: + * Some hardware supports special memory in which request and descriptor + * data can be accessed more efficiently. This method provides a + * mechanism to allocate the request/descriptor memory. If the underlying + * hardware does not support such "special" memory, this functions may + * simply map to kmm_malloc. + * + * This interface was optimized under a particular assumption. It was + * assumed that the driver maintains a pool of small, pre-allocated + * buffers for descriptor traffic. NOTE that size is not an input, but + * an output: The size of the pre-allocated buffer is returned. + * + * Input Parameters: + * drvr - The USB host driver instance obtained as a parameter from the + * call to the class create() method. + * buffer - The address of a memory location provided by the caller in + * which to return the allocated buffer memory address. + * maxlen - The address of a memory location provided by the caller in + * which to return the maximum size of the allocated buffer memory. + * + * Returned Value: + * On success, zero (OK) is returned. On a failure, a negated errno value + * is returned indicating the nature of the failure + * + * Assumptions: + * - Called from a single thread so no mutual exclusion is required. + * - Never called from an interrupt handler. + * + ****************************************************************************/ + +static int stm32_alloc(struct usbhost_driver_s *drvr, + uint8_t **buffer, size_t *maxlen) +{ + uint8_t *alloc; + + DEBUGASSERT(drvr && buffer && maxlen); + + /* There is no special memory requirement for the STM32. */ + + alloc = kmm_malloc(CONFIG_STM32_OTGHS_DESCSIZE); + if (!alloc) + { + return -ENOMEM; + } + + /* Return the allocated address and size of the descriptor buffer */ + + *buffer = alloc; + *maxlen = CONFIG_STM32_OTGHS_DESCSIZE; + return OK; +} + +/**************************************************************************** + * Name: stm32_free + * + * Description: + * Some hardware supports special memory in which request and descriptor + * data can be accessed more efficiently. This method provides a + * mechanism to free that request/descriptor memory. If the underlying + * hardware does not support such "special" memory, this functions may + * simply map to kmm_free(). + * + * Input Parameters: + * drvr - The USB host driver instance obtained as a parameter from the + * call to the class create() method. + * buffer - The address of the allocated buffer memory to be freed. + * + * Returned Value: + * On success, zero (OK) is returned. On a failure, a negated errno value + * is returned indicating the nature of the failure + * + * Assumptions: + * - Never called from an interrupt handler. + * + ****************************************************************************/ + +static int stm32_free(struct usbhost_driver_s *drvr, uint8_t *buffer) +{ + /* There is no special memory requirement */ + + DEBUGASSERT(drvr && buffer); + kmm_free(buffer); + return OK; +} + +/**************************************************************************** + * Name: stm32_ioalloc + * + * Description: + * Some hardware supports special memory in which larger IO buffers can + * be accessed more efficiently. This method provides a mechanism to + * allocate the request/descriptor memory. If the underlying hardware + * does not support such "special" memory, this functions may simply map + * to kmm_malloc. + * + * This interface differs from DRVR_ALLOC in that the buffers are + * variable-sized. + * + * Input Parameters: + * drvr - The USB host driver instance obtained as a parameter from the + * call to the class create() method. + * buffer - The address of a memory location provided by the caller in + * which to return the allocated buffer memory address. + * buflen - The size of the buffer required. + * + * Returned Value: + * On success, zero (OK) is returned. On a failure, a negated errno value + * is returned indicating the nature of the failure + * + * Assumptions: + * This function will *not* be called from an interrupt handler. + * + ****************************************************************************/ + +static int stm32_ioalloc(struct usbhost_driver_s *drvr, + uint8_t **buffer, size_t buflen) +{ + uint8_t *alloc; + + DEBUGASSERT(drvr && buffer && buflen > 0); + + /* There is no special memory requirement */ + + alloc = kmm_malloc(buflen); + if (!alloc) + { + return -ENOMEM; + } + + /* Return the allocated buffer */ + + *buffer = alloc; + return OK; +} + +/**************************************************************************** + * Name: stm32_iofree + * + * Description: + * Some hardware supports special memory in which IO data can be accessed + * more efficiently. This method provides a mechanism to free that IO + * buffer memory. If the underlying hardware does not support such + * "special" memory, this functions may simply map to kmm_free(). + * + * Input Parameters: + * drvr - The USB host driver instance obtained as a parameter from the + * call to the class create() method. + * buffer - The address of the allocated buffer memory to be freed. + * + * Returned Value: + * On success, zero (OK) is returned. On a failure, a negated errno value + * is returned indicating the nature of the failure + * + * Assumptions: + * This function will *not* be called from an interrupt handler. + * + ****************************************************************************/ + +static int stm32_iofree(struct usbhost_driver_s *drvr, + uint8_t *buffer) +{ + /* There is no special memory requirement */ + + DEBUGASSERT(drvr && buffer); + kmm_free(buffer); + return OK; +} + +/**************************************************************************** + * Name: stm32_ctrlin and stm32_ctrlout + * + * Description: + * Process a IN or OUT request on the control endpoint. These methods + * will enqueue the request and wait for it to complete. Only one + * transfer may be queued; Neither these methods nor the transfer() + * method can be called again until the control transfer functions + * returns. + * + * These are blocking methods; these functions will not return until the + * control transfer has completed. + * + * Input Parameters: + * drvr - The USB host driver instance obtained as a parameter from the + * call to the class create() method. + * ep0 - The control endpoint to send/receive the control request. + * req - Describes the request to be sent. This request must lie in memory + * created by DRVR_ALLOC. + * buffer - A buffer used for sending the request and for returning any + * responses. This buffer must be large enough to hold the length value + * in the request description. buffer must have been allocated using + * DRVR_ALLOC. + * + * NOTE: On an IN transaction, req and buffer may refer to the same + * allocated memory. + * + * Returned Value: + * On success, zero (OK) is returned. On a failure, a negated errno value + * is returned indicating the nature of the failure + * + * Assumptions: + * - Called from a single thread so no mutual exclusion is required. + * - Never called from an interrupt handler. + * + ****************************************************************************/ + +static int stm32_ctrlin(struct usbhost_driver_s *drvr, usbhost_ep_t ep0, + const struct usb_ctrlreq_s *req, + uint8_t *buffer) +{ + struct stm32_usbhost_s *priv = (struct stm32_usbhost_s *)drvr; + struct stm32_ctrlinfo_s *ep0info = (struct stm32_ctrlinfo_s *)ep0; + uint16_t buflen; + clock_t start; + clock_t elapsed; + int retries; + int ret; + + DEBUGASSERT(priv != NULL && ep0info != NULL && req != NULL); + usbhost_vtrace2(OTGHS_VTRACE2_CTRLIN, req->type, req->req); + uinfo("type:%02x req:%02x value:%02x%02x index:%02x%02x len:%02x%02x\n", + req->type, req->req, req->value[1], req->value[0], + req->index[1], req->index[0], req->len[1], req->len[0]); + + /* Extract values from the request */ + + buflen = stm32_getle16(req->len); + + /* We must have exclusive access to the USB host hardware and structures */ + + ret = nxmutex_lock(&priv->lock); + if (ret < 0) + { + return ret; + } + + /* Loop, retrying until the retry time expires */ + + for (retries = 0; retries < STM32_RETRY_COUNT; retries++) + { + /* Send the SETUP request */ + + ret = stm32_ctrl_sendsetup(priv, ep0info, req); + if (ret < 0) + { + usbhost_trace1(OTGHS_TRACE1_SENDSETUP, -ret); + continue; + } + + /* Handle the IN data phase (if any) */ + + if (buflen > 0) + { + ret = stm32_ctrl_recvdata(priv, ep0info, buffer, buflen); + if (ret < 0) + { + usbhost_trace1(OTGHS_TRACE1_RECVDATA, -ret); + continue; + } + } + + /* Get the start time. Loop again until the timeout expires */ + + start = clock_systime_ticks(); + do + { + /* Handle the status OUT phase */ + + priv->chan[ep0info->outndx].outdata1 ^= true; + ret = stm32_ctrl_senddata(priv, ep0info, NULL, 0); + if (ret == OK) + { + /* All success transactions exit here */ + + nxmutex_unlock(&priv->lock); + return OK; + } + + usbhost_trace1(OTGHS_TRACE1_SENDDATA, ret < 0 ? -ret : ret); + + /* Get the elapsed time (in frames) */ + + elapsed = clock_systime_ticks() - start; + } + while (elapsed < STM32_DATANAK_DELAY); + } + + /* All failures exit here after all retries and timeouts are exhausted */ + + nxmutex_unlock(&priv->lock); + return -ETIMEDOUT; +} + +static int stm32_ctrlout(struct usbhost_driver_s *drvr, usbhost_ep_t ep0, + const struct usb_ctrlreq_s *req, + const uint8_t *buffer) +{ + struct stm32_usbhost_s *priv = (struct stm32_usbhost_s *)drvr; + struct stm32_ctrlinfo_s *ep0info = (struct stm32_ctrlinfo_s *)ep0; + uint16_t buflen; + clock_t start; + clock_t elapsed; + int retries; + int ret; + + DEBUGASSERT(priv != NULL && ep0info != NULL && req != NULL); + usbhost_vtrace2(OTGHS_VTRACE2_CTRLOUT, req->type, req->req); + uinfo("type:%02x req:%02x value:%02x%02x index:%02x%02x len:%02x%02x\n", + req->type, req->req, req->value[1], req->value[0], + req->index[1], req->index[0], req->len[1], req->len[0]); + + /* Extract values from the request */ + + buflen = stm32_getle16(req->len); + + /* We must have exclusive access to the USB host hardware and structures */ + + ret = nxmutex_lock(&priv->lock); + if (ret < 0) + { + return ret; + } + + /* Loop, retrying until the retry time expires */ + + for (retries = 0; retries < STM32_RETRY_COUNT; retries++) + { + /* Send the SETUP request */ + + ret = stm32_ctrl_sendsetup(priv, ep0info, req); + if (ret < 0) + { + usbhost_trace1(OTGHS_TRACE1_SENDSETUP, -ret); + continue; + } + + /* Get the start time. Loop again until the timeout expires */ + + start = clock_systime_ticks(); + do + { + /* Handle the data OUT phase (if any) */ + + if (buflen > 0) + { + /* Start DATA out transfer (only one DATA packet) */ + + priv->chan[ep0info->outndx].outdata1 = true; + ret = stm32_ctrl_senddata(priv, ep0info, (uint8_t *)buffer, + buflen); + if (ret < 0) + { + usbhost_trace1(OTGHS_TRACE1_SENDDATA, -ret); + } + } + + /* Handle the status IN phase */ + + if (ret == OK) + { + ret = stm32_ctrl_recvdata(priv, ep0info, NULL, 0); + if (ret == OK) + { + /* All success transactins exit here */ + + nxmutex_unlock(&priv->lock); + return OK; + } + + usbhost_trace1(OTGHS_TRACE1_RECVDATA, ret < 0 ? -ret : ret); + } + + /* Get the elapsed time (in frames) */ + + elapsed = clock_systime_ticks() - start; + } + while (elapsed < STM32_DATANAK_DELAY); + } + + /* All failures exit here after all retries and timeouts are exhausted */ + + nxmutex_unlock(&priv->lock); + return -ETIMEDOUT; +} + +/**************************************************************************** + * Name: stm32_transfer + * + * Description: + * Process a request to handle a transfer descriptor. This method will + * enqueue the transfer request, blocking until the transfer completes. + * Only one transfer may be queued; Neither this method nor the ctrlin or + * ctrlout methods can be called again until this function returns. + * + * This is a blocking method; this functions will not return until the + * transfer has completed. + * + * Input Parameters: + * drvr - The USB host driver instance obtained as a parameter from the + * call to the class create() method. + * ep - The IN or OUT endpoint descriptor for the device endpoint on + * which to perform the transfer. + * buffer - A buffer containing the data to be sent (OUT endpoint) or + * received (IN endpoint). buffer must have been allocated using + * DRVR_ALLOC + * buflen - The length of the data to be sent or received. + * + * Returned Value: + * On success, a non-negative value is returned that indicates the number + * of bytes successfully transferred. On a failure, a negated errno value + * is returned that indicates the nature of the failure: + * + * EAGAIN - If devices NAKs the transfer (or NYET or other error where + * it may be appropriate to restart the entire transaction). + * EPERM - If the endpoint stalls + * EIO - On a TX or data toggle error + * EPIPE - Overrun errors + * + * Assumptions: + * - Called from a single thread so no mutual exclusion is required. + * - Never called from an interrupt handler. + * + ****************************************************************************/ + +static ssize_t stm32_transfer(struct usbhost_driver_s *drvr, + usbhost_ep_t ep, + uint8_t *buffer, size_t buflen) +{ + struct stm32_usbhost_s *priv = (struct stm32_usbhost_s *)drvr; + unsigned int chidx = (unsigned int)ep; + ssize_t nbytes; + int ret; + + uinfo("chidx: %d buflen: %d\n", (unsigned int)ep, buflen); + + DEBUGASSERT(priv && buffer && chidx < STM32_MAX_TX_FIFOS && buflen > 0); + + /* We must have exclusive access to the USB host hardware and structures */ + + ret = nxmutex_lock(&priv->lock); + if (ret < 0) + { + return (ssize_t)ret; + } + + /* Handle IN and OUT transfer slightly differently */ + + if (priv->chan[chidx].in) + { + nbytes = stm32_in_transfer(priv, chidx, buffer, buflen); + } + else + { + nbytes = stm32_out_transfer(priv, chidx, buffer, buflen); + } + + nxmutex_unlock(&priv->lock); + return nbytes; +} + +/**************************************************************************** + * Name: stm32_asynch + * + * Description: + * Process a request to handle a transfer descriptor. This method will + * enqueue the transfer request and return immediately. When the transfer + * completes, the callback will be invoked with the provided transfer. + * This method is useful for receiving interrupt transfers which may come + * infrequently. + * + * Only one transfer may be queued; Neither this method nor the ctrlin or + * ctrlout methods can be called again until the transfer completes. + * + * Input Parameters: + * drvr - The USB host driver instance obtained as a parameter from the + * call to the class create() method. + * ep - The IN or OUT endpoint descriptor for the device endpoint on + * which to perform the transfer. + * buffer - A buffer containing the data to be sent (OUT endpoint) or + * received (IN endpoint). buffer must have been allocated using + * DRVR_ALLOC + * buflen - The length of the data to be sent or received. + * callback - This function will be called when the transfer completes. + * arg - The arbitrary parameter that will be passed to the callback + * function when the transfer completes. + * + * Returned Value: + * On success, zero (OK) is returned. On a failure, a negated errno value + * is returned indicating the nature of the failure + * + * Assumptions: + * - Called from a single thread so no mutual exclusion is required. + * - Never called from an interrupt handler. + * + ****************************************************************************/ + +#ifdef CONFIG_USBHOST_ASYNCH +static int stm32_asynch(struct usbhost_driver_s *drvr, usbhost_ep_t ep, + uint8_t *buffer, size_t buflen, + usbhost_asynch_t callback, void *arg) +{ + struct stm32_usbhost_s *priv = (struct stm32_usbhost_s *)drvr; + unsigned int chidx = (unsigned int)ep; + int ret; + + uinfo("chidx: %d buflen: %d\n", (unsigned int)ep, buflen); + + DEBUGASSERT(priv && buffer && chidx < STM32_MAX_TX_FIFOS && buflen > 0); + + /* We must have exclusive access to the USB host hardware and structures */ + + ret = nxmutex_lock(&priv->lock); + if (ret < 0) + { + return ret; + } + + /* Handle IN and OUT transfer slightly differently */ + + if (priv->chan[chidx].in) + { + ret = stm32_in_asynch(priv, chidx, buffer, buflen, callback, arg); + } + else + { + ret = stm32_out_asynch(priv, chidx, buffer, buflen, callback, arg); + } + + nxmutex_unlock(&priv->lock); + return ret; +} +#endif /* CONFIG_USBHOST_ASYNCH */ + +/**************************************************************************** + * Name: stm32_cancel + * + * Description: + * Cancel a pending transfer on an endpoint. Cancelled synchronous or + * asynchronous transfer will complete normally with the error -ESHUTDOWN. + * + * Input Parameters: + * drvr - The USB host driver instance obtained as a parameter from the + * call to the class create() method. + * ep - The IN or OUT endpoint descriptor for the device endpoint on + * which an asynchronous transfer should be transferred. + * + * Returned Value: + * On success, zero (OK) is returned. On a failure, a negated errno value + * is returned indicating the nature of the failure + * + ****************************************************************************/ + +static int stm32_cancel(struct usbhost_driver_s *drvr, usbhost_ep_t ep) +{ + struct stm32_usbhost_s *priv = (struct stm32_usbhost_s *)drvr; + struct stm32_chan_s *chan; + unsigned int chidx = (unsigned int)ep; + irqstate_t flags; + + uinfo("chidx: %u\n", chidx); + + DEBUGASSERT(priv && chidx < STM32_MAX_TX_FIFOS); + chan = &priv->chan[chidx]; + + /* We need to disable interrupts to avoid race conditions with the + * asynchronous completion of the transfer being cancelled. + */ + + flags = enter_critical_section(); + + /* Halt the channel */ + + stm32_chan_halt(priv, chidx, CHREASON_CANCELLED); + chan->result = -ESHUTDOWN; + + /* Is there a thread waiting for this transfer to complete? */ + + if (chan->waiter) + { +#ifdef CONFIG_USBHOST_ASYNCH + /* Yes.. there should not also be a callback scheduled */ + + DEBUGASSERT(chan->callback == NULL); +#endif + + /* Wake'em up! */ + + nxsem_post(&chan->waitsem); + chan->waiter = false; + } + +#ifdef CONFIG_USBHOST_ASYNCH + /* No.. is an asynchronous callback expected when the transfer + * completes? + */ + + else if (chan->callback) + { + usbhost_asynch_t callback; + void *arg; + + /* Extract the callback information */ + + callback = chan->callback; + arg = chan->arg; + + chan->callback = NULL; + chan->arg = NULL; + chan->xfrd = 0; + + /* Then perform the callback */ + + callback(arg, -ESHUTDOWN); + } +#endif + + leave_critical_section(flags); + return OK; +} + +/**************************************************************************** + * Name: stm32_connect + * + * Description: + * New connections may be detected by an attached hub. This method is the + * mechanism that is used by the hub class to introduce a new connection + * and port description to the system. + * + * Input Parameters: + * drvr - The USB host driver instance obtained as a parameter from the + * call to the class create() method. + * hport - The descriptor of the hub port that detected the connection + * related event + * connected - True: device connected; false: device disconnected + * + * Returned Value: + * On success, zero (OK) is returned. On a failure, a negated errno value + * is returned indicating the nature of the failure + * + ****************************************************************************/ + +#ifdef CONFIG_USBHOST_HUB +static int stm32_connect(struct usbhost_driver_s *drvr, + struct usbhost_hubport_s *hport, + bool connected) +{ + struct stm32_usbhost_s *priv = (struct stm32_usbhost_s *)drvr; + irqstate_t flags; + + DEBUGASSERT(priv != NULL && hport != NULL); + + /* Set the connected/disconnected flag */ + + hport->connected = connected; + uinfo("Hub port %d connected: %s\n", + hport->port, connected ? "YES" : "NO"); + + /* Report the connection event */ + + flags = enter_critical_section(); + priv->hport = hport; + if (priv->pscwait) + { + priv->pscwait = false; + nxsem_post(&priv->pscsem); + } + + leave_critical_section(flags); + return OK; +} +#endif + +/**************************************************************************** + * Name: stm32_disconnect + * + * Description: + * Called by the class when an error occurs and driver has been + * disconnected. The USB host driver should discard the handle to the + * class instance (it is stale) and not attempt any further interaction + * with the class driver instance (until a new instance is received from + * the create() method). The driver should not called the class' + * disconnected() method. + * + * Input Parameters: + * drvr - The USB host driver instance obtained as a parameter from the + * call to the class create() method. + * hport - The port from which the device is being disconnected. Might be + * a port on a hub. + * + * Returned Value: + * None + * + * Assumptions: + * - Only a single class bound to a single device is supported. + * - Never called from an interrupt handler. + * + ****************************************************************************/ + +static void stm32_disconnect(struct usbhost_driver_s *drvr, + struct usbhost_hubport_s *hport) +{ + DEBUGASSERT(hport != NULL); + hport->devclass = NULL; +} + +/**************************************************************************** + * Name: stm32_portreset + * + * Description: + * Reset the USB host port. + * + * NOTE: "Before starting to drive a USB reset, the application waits for + * the OTG interrupt triggered by the debounce done bit (DBCDNE bit in + * OTG_HS_GOTGINT), which indicates that the bus is stable again after the + * electrical debounce caused by the attachment of a pull-up resistor on DP + * (HS) or DM (LS). + * + * Input Parameters: + * priv -- USB host driver private data structure. + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void stm32_portreset(struct stm32_usbhost_s *priv) +{ + uint32_t regval; + + regval = stm32_getreg(STM32_OTGHS_HPRT); + regval &= ~(OTGHS_HPRT_PENA | OTGHS_HPRT_PCDET | OTGHS_HPRT_PENCHNG | + OTGHS_HPRT_POCCHNG); + regval |= OTGHS_HPRT_PRST; + stm32_putreg(STM32_OTGHS_HPRT, regval); + + up_mdelay(20); + + regval &= ~OTGHS_HPRT_PRST; + stm32_putreg(STM32_OTGHS_HPRT, regval); + + up_mdelay(20); +} + +/**************************************************************************** + * Name: stm32_flush_txfifos + * + * Description: + * Flush the selected Tx FIFO. + * + * Input Parameters: + * txfnum -- USB host driver private data structure. + * + * Returned Value: + * None. + * + ****************************************************************************/ + +static void stm32_flush_txfifos(uint32_t txfnum) +{ + uint32_t regval; + uint32_t timeout; + + /* Initiate the TX FIFO flush operation */ + + regval = OTGHS_GRSTCTL_TXFFLSH | txfnum; + stm32_putreg(STM32_OTGHS_GRSTCTL, regval); + + /* Wait for the FLUSH to complete */ + + for (timeout = 0; timeout < STM32_FLUSH_DELAY; timeout++) + { + regval = stm32_getreg(STM32_OTGHS_GRSTCTL); + if ((regval & OTGHS_GRSTCTL_TXFFLSH) == 0) + { + break; + } + } + + /* Wait for 3 PHY Clocks */ + + up_udelay(3); +} + +/**************************************************************************** + * Name: stm32_flush_rxfifo + * + * Description: + * Flush the Rx FIFO. + * + * Input Parameters: + * priv -- USB host driver private data structure. + * + * Returned Value: + * None. + * + ****************************************************************************/ + +static void stm32_flush_rxfifo(void) +{ + uint32_t regval; + uint32_t timeout; + + /* Initiate the RX FIFO flush operation */ + + stm32_putreg(STM32_OTGHS_GRSTCTL, OTGHS_GRSTCTL_RXFFLSH); + + /* Wait for the FLUSH to complete */ + + for (timeout = 0; timeout < STM32_FLUSH_DELAY; timeout++) + { + regval = stm32_getreg(STM32_OTGHS_GRSTCTL); + if ((regval & OTGHS_GRSTCTL_RXFFLSH) == 0) + { + break; + } + } + + /* Wait for 3 PHY Clocks */ + + up_udelay(3); +} + +/**************************************************************************** + * Name: stm32_vbusdrive + * + * Description: + * Drive the Vbus +5V. + * + * Input Parameters: + * priv - USB host driver private data structure. + * state - True: Drive, False: Don't drive + * + * Returned Value: + * None. + * + ****************************************************************************/ + +static void stm32_vbusdrive(struct stm32_usbhost_s *priv, bool state) +{ + uint32_t regval; + + /* Enable/disable the external charge pump */ + + stm32_usbhost_vbusdrive(0, state); + + /* Turn on the Host port power. */ + + regval = stm32_getreg(STM32_OTGHS_HPRT); + regval &= ~(OTGHS_HPRT_PENA | OTGHS_HPRT_PCDET | OTGHS_HPRT_PENCHNG | + OTGHS_HPRT_POCCHNG); + + if (((regval & OTGHS_HPRT_PPWR) == 0) && state) + { + regval |= OTGHS_HPRT_PPWR; + stm32_putreg(STM32_OTGHS_HPRT, regval); + } + + if (((regval & OTGHS_HPRT_PPWR) != 0) && !state) + { + regval &= ~OTGHS_HPRT_PPWR; + stm32_putreg(STM32_OTGHS_HPRT, regval); + } + + up_mdelay(200); +} + +/**************************************************************************** + * Name: stm32_host_initialize + * + * Description: + * Initialize/re-initialize hardware for host mode operation. At present, + * this function is called only from stm32_hw_initialize(). But if OTG + * mode were supported, this function would also be called to switch + * between host and device modes on a connector ID change interrupt. + * + * Input Parameters: + * priv -- USB host driver private data structure. + * + * Returned Value: + * None. + * + ****************************************************************************/ + +static void stm32_host_initialize(struct stm32_usbhost_s *priv) +{ + uint32_t regval; + uint32_t offset; + int i; + + /* Restart the PHY Clock */ + + stm32_putreg(STM32_OTGHS_PCGCCTL, 0); + + /* Initialize Host Configuration (HCFG) register */ + + regval = stm32_getreg(STM32_OTGHS_HCFG); + regval &= ~OTGHS_HCFG_FSLSPCS_MASK; + regval |= OTGHS_HCFG_FSLSPCS_FS48MHz; + stm32_putreg(STM32_OTGHS_HCFG, regval); + + /* Reset the host port */ + + stm32_portreset(priv); + + /* Clear the HS-/LS-only support bit in the HCFG register */ + + regval = stm32_getreg(STM32_OTGHS_HCFG); + regval &= ~OTGHS_HCFG_FSLSS; + stm32_putreg(STM32_OTGHS_HCFG, regval); + + /* Carve up FIFO memory for the Rx FIFO and the periodic and non-periodic + * Tx FIFOs + */ + + /* Configure Rx FIFO size (GRXHSIZ) */ + + stm32_putreg(STM32_OTGHS_GRXFSIZ, CONFIG_STM32_OTGHS_RXFIFO_SIZE); + offset = CONFIG_STM32_OTGHS_RXFIFO_SIZE; + + /* Setup the host non-periodic Tx FIFO size (HNPTXHSIZ) */ + + regval = (offset | + (CONFIG_STM32_OTGHS_NPTXFIFO_SIZE << + OTGHS_HNPTXFSIZ_NPTXFD_SHIFT)); + stm32_putreg(STM32_OTGHS_HNPTXFSIZ, regval); + offset += CONFIG_STM32_OTGHS_NPTXFIFO_SIZE; + + /* Set up the host periodic Tx fifo size register (HPTXHSIZ) */ + + regval = (offset | + (CONFIG_STM32_OTGHS_PTXFIFO_SIZE << + OTGHS_HPTXFSIZ_PTXFD_SHIFT)); + stm32_putreg(STM32_OTGHS_HPTXFSIZ, regval); + + /* If OTG were supported, we should need to clear HNP enable bit in the + * USB_OTG control register about here. + */ + + /* Flush all FIFOs */ + + stm32_flush_txfifos(OTGHS_GRSTCTL_TXFNUM_HALL); + stm32_flush_rxfifo(); + + /* Clear all pending HC Interrupts */ + + for (i = 0; i < STM32_NHOST_CHANNELS; i++) + { + stm32_putreg(STM32_OTGHS_HCINT(i), 0xffffffff); + stm32_putreg(STM32_OTGHS_HCINTMSK(i), 0); + } + + /* Driver Vbus +5V (the smoke test). Should be done elsewhere in OTG + * mode. + */ + + stm32_vbusdrive(priv, true); + + /* Enable host interrupts */ + + stm32_hostinit_enable(); +} + +/**************************************************************************** + * Name: stm32_sw_initialize + * + * Description: + * One-time setup of the host driver state structure. + * + * Input Parameters: + * priv -- USB host driver private data structure. + * + * Returned Value: + * None. + * + ****************************************************************************/ + +static inline void stm32_sw_initialize(struct stm32_usbhost_s *priv) +{ + struct usbhost_driver_s *drvr; + struct usbhost_hubport_s *hport; + int i; + + /* Initialize the device operations */ + + drvr = &priv->drvr; + drvr->ep0configure = stm32_ep0configure; + drvr->epalloc = stm32_epalloc; + drvr->epfree = stm32_epfree; + drvr->alloc = stm32_alloc; + drvr->free = stm32_free; + drvr->ioalloc = stm32_ioalloc; + drvr->iofree = stm32_iofree; + drvr->ctrlin = stm32_ctrlin; + drvr->ctrlout = stm32_ctrlout; + drvr->transfer = stm32_transfer; +#ifdef CONFIG_USBHOST_ASYNCH + drvr->asynch = stm32_asynch; +#endif + drvr->cancel = stm32_cancel; +#ifdef CONFIG_USBHOST_HUB + drvr->connect = stm32_connect; +#endif + drvr->disconnect = stm32_disconnect; + + /* Initialize the public port representation */ + + hport = &priv->rhport.hport; + hport->drvr = drvr; +#ifdef CONFIG_USBHOST_HUB + hport->parent = NULL; +#endif + hport->ep0 = (usbhost_ep_t)&priv->ep0; + hport->speed = USB_SPEED_FULL; + + /* Initialize function address generation logic */ + + usbhost_devaddr_initialize(&priv->devgen); + priv->rhport.pdevgen = &priv->devgen; + + /* Initialize the driver state data */ + + priv->smstate = SMSTATE_DETACHED; + priv->connected = false; + priv->change = false; + + /* Put all of the channels back in their initial, allocated state */ + + memset(priv->chan, 0, STM32_MAX_TX_FIFOS * sizeof(struct stm32_chan_s)); + + /* Initialize each channel */ + + for (i = 0; i < STM32_MAX_TX_FIFOS; i++) + { + struct stm32_chan_s *chan = &priv->chan[i]; + + chan->chidx = i; + nxsem_init(&chan->waitsem, 0, 0); + } +} + +/**************************************************************************** + * Name: stm32_hw_initialize + * + * Description: + * One-time setup of the host controller hardware for normal operations. + * + * Input Parameters: + * priv -- USB host driver private data structure. + * + * Returned Value: + * Zero on success; a negated errno value on failure. + * + ****************************************************************************/ + +static inline int stm32_hw_initialize(struct stm32_usbhost_s *priv) +{ + uint32_t regval; + unsigned long timeout; + + /* Set the PHYSEL bit in the GUSBCFG register to select the OTG HS serial + * transceiver: "This bit is always 1 with write-only access" + */ + + regval = stm32_getreg(STM32_OTGHS_GUSBCFG); + regval |= OTGHS_GUSBCFG_PHYSEL; + stm32_putreg(STM32_OTGHS_GUSBCFG, regval); + + /* Reset after a PHY select and set Host mode. First, wait for AHB master + * IDLE state. + */ + + for (timeout = 0; timeout < STM32_READY_DELAY; timeout++) + { + up_udelay(3); + regval = stm32_getreg(STM32_OTGHS_GRSTCTL); + if ((regval & OTGHS_GRSTCTL_AHBIDL) != 0) + { + break; + } + } + + /* Then perform the core soft reset. */ + + stm32_putreg(STM32_OTGHS_GRSTCTL, OTGHS_GRSTCTL_CSRST); + for (timeout = 0; timeout < STM32_READY_DELAY; timeout++) + { + regval = stm32_getreg(STM32_OTGHS_GRSTCTL); + if ((regval & OTGHS_GRSTCTL_CSRST) == 0) + { + break; + } + } + + /* Wait for 3 PHY Clocks */ + + up_udelay(3); + + /* Deactivate the power down */ + + regval = OTGHS_GCCFG_PWRDWN | OTGHS_GCCFG_VBUSASEN | + OTGHS_GCCFG_VBUSBSEN; +#ifndef CONFIG_USBDEV_VBUSSENSING + regval |= OTGHS_GCCFG_NOVBUSSENS; +#endif +#ifdef CONFIG_STM32_OTGHS_SOFOUTPUT + regval |= OTGHS_GCCFG_SOFOUTEN; +#endif + stm32_putreg(STM32_OTGHS_GCCFG, regval); + up_mdelay(20); + + /* Initialize OTG features: In order to support OTP, the HNPCAP and SRPCAP + * bits would need to be set in the GUSBCFG register about here. + */ + + /* Force Host Mode */ + + regval = stm32_getreg(STM32_OTGHS_GUSBCFG); + regval &= ~OTGHS_GUSBCFG_FDMOD; + regval |= OTGHS_GUSBCFG_FHMOD; + stm32_putreg(STM32_OTGHS_GUSBCFG, regval); + up_mdelay(50); + + /* Initialize host mode and return success */ + + stm32_host_initialize(priv); + return OK; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_otghshost_initialize + * + * Description: + * Initialize USB host device controller hardware. + * + * Input Parameters: + * controller -- If the device supports more than USB host controller, then + * this identifies which controller is being initialized. Normally, this + * is just zero. + * + * Returned Value: + * And instance of the USB host interface. The controlling task should + * use this interface to (1) call the wait() method to wait for a device + * to be connected, and (2) call the enumerate() method to bind the device + * to a class driver. + * + * Assumptions: + * - This function should called in the initialization sequence in order + * to initialize the USB device functionality. + * - Class drivers should be initialized prior to calling this function. + * Otherwise, there is a race condition if the device is already connected. + * + ****************************************************************************/ + +struct usbhost_connection_s *stm32_otghshost_initialize(int controller) +{ + /* At present, there is only support for a single OTG HS host. Hence it is + * pre-allocated as g_usbhost. However, in most code, the private data + * structure will be referenced using the 'priv' pointer (rather than the + * global data) in order to simplify any future support for multiple + * devices. + */ + + struct stm32_usbhost_s *priv = &g_usbhost; + + /* Sanity checks */ + + DEBUGASSERT(controller == 0); + + /* Make sure that interrupts from the OTG HS core are disabled */ + + stm32_gint_disable(); + + /* Reset the state of the host driver */ + + stm32_sw_initialize(priv); + + /* Alternate function pin configuration. Here we assume that: + * + * 1. GPIOA, SYSCFG, and OTG HS peripheral clocking have already been\ + * enabled as part of the boot sequence. + * 2. Board-specific logic has already enabled other board specific GPIOs + * for things like soft pull-up, VBUS sensing, power controls, and over- + * current detection. + */ + + /* Configure OTG HS alternate function pins for DM, DP, ID, and SOF. + * + * PIN* SIGNAL DIRECTION + * ---- ----------- ---------- + * PA8 OTG_HS_SOF SOF clock output + * PA9 OTG_HS_VBUS VBUS input for device, Driven by external regulator by + * host (not an alternate function) + * PA10 OTG_HS_ID OTG ID pin (only needed in Dual mode) + * PA11 OTG_HS_DM D- I/O + * PA12 OTG_HS_DP D+ I/O + * + * *Pins may vary from device-to-device. + */ + + stm32_configgpio(GPIO_OTGHSFS_DM); + stm32_configgpio(GPIO_OTGHSFS_DP); +#if 0 /* Only needed for OTG */ + stm32_configgpio(GPIO_OTGHSFS_ID); +#endif + + /* SOF output pin configuration is configurable */ + +#ifdef CONFIG_STM32_OTGHS_SOFOUTPUT + stm32_configgpio(GPIO_OTGHSFS_SOF); +#endif + + /* Initialize the USB OTG HS core */ + + stm32_hw_initialize(priv); + + /* Attach USB host controller interrupt handler */ + + if (irq_attach(STM32_IRQ_OTGHS, stm32_gint_isr, NULL) != 0) + { + usbhost_trace1(OTGHS_TRACE1_IRQATTACH, 0); + return NULL; + } + + /* Enable USB OTG HS global interrupts */ + + stm32_gint_enable(); + + /* Enable interrupts at the interrupt controller */ + + up_enable_irq(STM32_IRQ_OTGHS); + return &g_usbconn; +} + +#endif /* CONFIG_STM32_USBHOST && CONFIG_STM32_OTGHS */ diff --git a/arch/arm/src/stm32/stm32_pm.h b/arch/arm/src/common/stm32/stm32_pm.h similarity index 95% rename from arch/arm/src/stm32/stm32_pm.h rename to arch/arm/src/common/stm32/stm32_pm.h index 7d66d3b209f11..f9bdebd9f6031 100644 --- a/arch/arm/src/stm32/stm32_pm.h +++ b/arch/arm/src/common/stm32/stm32_pm.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_pm.h + * arch/arm/src/common/stm32/stm32_pm.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_STM32_PM_H -#define __ARCH_ARM_SRC_STM32_STM32_PM_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_PM_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_PM_H /**************************************************************************** * Included Files @@ -124,4 +124,4 @@ void stm32_pmsleep(bool sleeponexit); #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32_STM32_PM_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_PM_H */ diff --git a/arch/arm/src/common/stm32/stm32_pminitialize_m3m4_v1.c b/arch/arm/src/common/stm32/stm32_pminitialize_m3m4_v1.c new file mode 100644 index 0000000000000..6120feeb7c4f3 --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_pminitialize_m3m4_v1.c @@ -0,0 +1,64 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_pminitialize_m3m4_v1.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include "arm_internal.h" +#include "stm32_pm.h" + +#ifdef CONFIG_PM + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: arm_pminitialize + * + * Description: + * This function is called by MCU-specific logic at power-on reset in + * order to provide one-time initialization the power management subsystem. + * This function must be called *very* early in the initialization sequence + * *before* any other device drivers are initialized (since they may + * attempt to register with the power management subsystem). + * + * Input Parameters: + * None. + * + * Returned Value: + * None. + * + ****************************************************************************/ + +void arm_pminitialize(void) +{ + /* Initialize the NuttX power management subsystem proper */ + + pm_initialize(); +} + +#endif /* CONFIG_PM */ diff --git a/arch/arm/src/common/stm32/stm32_pmsleep_m3m4_v1.c b/arch/arm/src/common/stm32/stm32_pmsleep_m3m4_v1.c new file mode 100644 index 0000000000000..24113447340a5 --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_pmsleep_m3m4_v1.c @@ -0,0 +1,99 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_pmsleep_m3m4_v1.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include "arm_internal.h" +#include "nvic.h" +#include "stm32_pwr.h" +#include "stm32_pm.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_pmsleep + * + * Description: + * Enter SLEEP mode. + * + * Input Parameters: + * sleeponexit - true: SLEEPONEXIT bit is set when the WFI instruction is + * executed, the MCU enters Sleep mode as soon as it + * exits the lowest priority ISR. + * - false: SLEEPONEXIT bit is cleared, the MCU enters Sleep + * mode as soon as WFI or WFE instruction is executed. + * Returned Value: + * None + * + ****************************************************************************/ + +void stm32_pmsleep(bool sleeponexit) +{ + uint32_t regval; + + /* Clear SLEEPDEEP bit of Cortex System Control Register */ + + regval = getreg32(NVIC_SYSCON); + regval &= ~NVIC_SYSCON_SLEEPDEEP; + if (sleeponexit) + { + regval |= NVIC_SYSCON_SLEEPONEXIT; + } + else + { + regval &= ~NVIC_SYSCON_SLEEPONEXIT; + } + + putreg32(regval, NVIC_SYSCON); + + /* Sleep until the wakeup interrupt or event occurs */ + +#ifdef CONFIG_PM_WFE + /* Mode: SLEEP + Entry with WFE */ + + asm("wfe"); +#else + /* Mode: SLEEP + Entry with WFI */ + + asm("wfi"); +#endif +} diff --git a/arch/arm/src/common/stm32/stm32_pmstandby_m3m4_v1.c b/arch/arm/src/common/stm32/stm32_pmstandby_m3m4_v1.c new file mode 100644 index 0000000000000..71195ed4bc59b --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_pmstandby_m3m4_v1.c @@ -0,0 +1,98 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_pmstandby_m3m4_v1.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include "arm_internal.h" +#include "nvic.h" +#include "stm32_pwr.h" +#include "stm32_pm.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_pmstandby + * + * Description: + * Enter STANDBY mode. + * + * Input Parameters: + * None + * + * Returned Value: + * On success, this function will not return (STANDBY mode can only be + * terminated with a reset event). Otherwise, STANDBY mode did not occur + * and a negated errno value is returned to indicate the cause of the + * failure. + * + ****************************************************************************/ + +int stm32_pmstandby(void) +{ + uint32_t regval; + + /* Clear the Wake-Up Flag by setting the CWUF bit in the power control + * register. + */ + + regval = getreg32(STM32_PWR_CR); + regval |= PWR_CR_CWUF; + putreg32(regval, STM32_PWR_CR); + + /* Set the Power Down Deep Sleep (PDDS) bit in the power control + * register. + */ + + regval |= PWR_CR_PDDS; + putreg32(regval, STM32_PWR_CR); + + /* Set SLEEPDEEP bit of Cortex System Control Register */ + + regval = getreg32(NVIC_SYSCON); + regval |= NVIC_SYSCON_SLEEPDEEP; + putreg32(regval, NVIC_SYSCON); + + /* Sleep until the wakeup reset occurs */ + + asm("wfi"); + return OK; /* Won't get here */ +} diff --git a/arch/arm/src/common/stm32/stm32_pmstop_m3m4_v1.c b/arch/arm/src/common/stm32/stm32_pmstop_m3m4_v1.c new file mode 100644 index 0000000000000..82ce0a60bc0e8 --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_pmstop_m3m4_v1.c @@ -0,0 +1,109 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_pmstop_m3m4_v1.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include "arm_internal.h" +#include "nvic.h" +#include "stm32_pwr.h" +#include "stm32_pm.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_pmstop + * + * Description: + * Enter STOP mode. + * + * Input Parameters: + * lpds - true: To further reduce power consumption in Stop mode, put the + * internal voltage regulator in low-power mode using the LPDS bit + * of the Power control register (PWR_CR). + * + * Returned Value: + * Zero means that the STOP was successfully entered and the system has + * been re-awakened. The internal voltage regulator is back to its + * original state. Otherwise, STOP mode did not occur and a negated + * errno value is returned to indicate the cause of the failure. + * + ****************************************************************************/ + +int stm32_pmstop(bool lpds) +{ + uint32_t regval; + + /* Clear the Power Down Deep Sleep (PDDS) and the Low Power Deep Sleep + * (LPDS)) bits in the power control register. + */ + + regval = getreg32(STM32_PWR_CR); + regval &= ~(PWR_CR_LPDS | PWR_CR_PDDS); + + /* Set the Low Power Deep Sleep (LPDS) bit if so requested */ + + if (lpds) + { + regval |= PWR_CR_LPDS; + } + + putreg32(regval, STM32_PWR_CR); + + /* Set SLEEPDEEP bit of Cortex System Control Register */ + + regval = getreg32(NVIC_SYSCON); + regval |= NVIC_SYSCON_SLEEPDEEP; + putreg32(regval, NVIC_SYSCON); + + /* Sleep until the wakeup interrupt or event occurs */ + +#ifdef CONFIG_PM_WFE + /* Mode: SLEEP + Entry with WFE */ + + asm("wfe"); +#else + /* Mode: SLEEP + Entry with WFI */ + + asm("wfi"); +#endif + return OK; +} diff --git a/arch/arm/src/common/stm32/stm32_pulsecount.h b/arch/arm/src/common/stm32/stm32_pulsecount.h new file mode 100644 index 0000000000000..ec76dfe48e4ec --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_pulsecount.h @@ -0,0 +1,39 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_pulsecount.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_COMPAT_STM32_PULSECOUNT_H +#define __ARCH_ARM_SRC_COMMON_COMPAT_STM32_PULSECOUNT_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +struct pulsecount_lowerhalf_s *stm32_pulsecountinitialize(int timer); + +#endif /* __ARCH_ARM_SRC_COMMON_COMPAT_STM32_PULSECOUNT_H */ diff --git a/arch/arm/src/common/stm32/stm32_pulsecount_m0_v1.c b/arch/arm/src/common/stm32/stm32_pulsecount_m0_v1.c new file mode 100644 index 0000000000000..e64d5be88fedf --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_pulsecount_m0_v1.c @@ -0,0 +1,1277 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_pulsecount_m0_v1.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include + +#include +#include +#include + +#include "arm_internal.h" +#include "chip.h" +#include "stm32_gpio.h" +#include "stm32_pulsecount.h" +#include "stm32_rcc.h" +#include "stm32_tim.h" + +/* This module only supports pulse count on advanced timers. */ + +#ifdef CONFIG_STM32_TIM1_PULSECOUNT + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Pulse count is supported by advanced timers only. */ + +#define TIMTYPE_ADVANCED 4 /* Advanced timers: TIM1 */ +#define TIMTYPE_TIM1 TIMTYPE_ADVANCED + +#define HAVE_IP_TIMERS_V2 1 + +/* CCMR2 */ + +#define HAVE_CCMR2 1 + +#ifdef STM32_APB2_TIM1_CLKIN +# define PULSECOUNT_TIM1_CLKIN STM32_APB2_TIM1_CLKIN +#else +# define PULSECOUNT_TIM1_CLKIN STM32_APB1_TIM1_CLKIN +#endif + +#if CONFIG_STM32_TIM1_PULSECOUNT_CHANNEL == 1 +# define PULSECOUNT_TIM1_CHCFG GPIO_TIM1_CH1OUT +#elif CONFIG_STM32_TIM1_PULSECOUNT_CHANNEL == 2 +# define PULSECOUNT_TIM1_CHCFG GPIO_TIM1_CH2OUT +#elif CONFIG_STM32_TIM1_PULSECOUNT_CHANNEL == 3 +# define PULSECOUNT_TIM1_CHCFG GPIO_TIM1_CH3OUT +#elif CONFIG_STM32_TIM1_PULSECOUNT_CHANNEL == 4 +# define PULSECOUNT_TIM1_CHCFG GPIO_TIM1_CH4OUT +#else +# error Unsupported TIM1 pulse count channel +#endif + +/* Debug ********************************************************************/ + +#ifdef CONFIG_DEBUG_TIMER_INFO +# define pulsecount_dumpgpio(p,m) +# warning "pulsecount_dumpgpio not implemented" +#else +# define pulsecount_dumpgpio(p,m) +#endif + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +struct stm32_pulsecountchan_s +{ + uint8_t channel; + uint32_t pincfg; +}; + +/* This structure represents the state of one pulsecount timer */ + +struct stm32_pulsecounttimer_s +{ + const struct pulsecount_ops_s *ops; + struct stm32_pulsecountchan_s channel; + uint8_t timid; + uint8_t timtype; + uint8_t irq; + uint32_t prev; + uint32_t curr; + uint32_t count; + uint32_t base; + uint32_t pclk; + void *handle; +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/* Register access */ + +static uint32_t stm32pulsecount_getreg(struct stm32_pulsecounttimer_s *priv, + int offset); +static void stm32pulsecount_putreg(struct stm32_pulsecounttimer_s *priv, + int offset, uint32_t value); +static void stm32pulsecount_modifyreg(struct stm32_pulsecounttimer_s *priv, + uint32_t offset, uint32_t clearbits, + uint32_t setbits); + +#ifdef CONFIG_DEBUG_TIMER_INFO +static void stm32pulsecount_dumpregs(struct stm32_pulsecounttimer_s *priv, + const char *msg); +#else +# define stm32pulsecount_dumpregs(priv,msg) +#endif + +/* Timer management */ + +static int +stm32pulsecount_output_configure(struct stm32_pulsecounttimer_s *priv, + uint8_t channel); +static int stm32pulsecount_timer(struct stm32_pulsecounttimer_s *priv, + const struct pulsecount_info_s *info); +static void stm32pulsecount_setapbclock( + struct stm32_pulsecounttimer_s *priv, bool on); +static int stm32pulsecount_interrupt(struct stm32_pulsecounttimer_s *priv); +static int stm32pulsecount_tim1interrupt(int irq, void *context, void *arg); +static uint32_t stm32pulsecount_pulsecount(uint32_t count); + +/* Pulsecount driver methods */ + +static int stm32pulsecount_setup(struct pulsecount_lowerhalf_s *dev); +static int stm32pulsecount_shutdown(struct pulsecount_lowerhalf_s *dev); + +static int stm32pulsecount_start(struct pulsecount_lowerhalf_s *dev, + const struct pulsecount_info_s *info, + void *handle); + +static int stm32pulsecount_stop(struct pulsecount_lowerhalf_s *dev); +static int stm32pulsecount_ioctl(struct pulsecount_lowerhalf_s *dev, + int cmd, unsigned long arg); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* This is the list of lower half pulsecount driver methods used by the upper + * half driver. + */ + +static const struct pulsecount_ops_s g_pulsecountops = +{ + .setup = stm32pulsecount_setup, + .shutdown = stm32pulsecount_shutdown, + .start = stm32pulsecount_start, + .stop = stm32pulsecount_stop, + .ioctl = stm32pulsecount_ioctl, +}; + +#ifdef CONFIG_STM32_TIM1_PULSECOUNT +static struct stm32_pulsecounttimer_s g_pulsecount1dev = +{ + .ops = &g_pulsecountops, + .timid = 1, + .channel = + { + .channel = CONFIG_STM32_TIM1_PULSECOUNT_CHANNEL, + .pincfg = PULSECOUNT_TIM1_CHCFG, + }, + .timtype = TIMTYPE_TIM1, + .irq = STM32_IRQ_TIM1_BRK, + .base = STM32_TIM1_BASE, + .pclk = PULSECOUNT_TIM1_CLKIN, +}; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32pulsecount_reg_is_32bit + * + * Description: + * Verify whether the timer register is 32bit or not. + * + * Input Parameters: + * timtype - The type of the timer. See the TIMTYPE_* definitions + * offset - The offset to the register to read + * + * Returned Value: + * Return true for 32 bits register; false otherwise. + * + ****************************************************************************/ + +static bool stm32pulsecount_reg_is_32bit(uint8_t timtype, uint32_t offset) +{ + if (timtype == TIMTYPE_ADVANCED) + { + if (offset == STM32_ATIM_CR2_OFFSET || + offset == STM32_ATIM_CCMR1_OFFSET || + offset == STM32_ATIM_CCMR2_OFFSET || + offset == STM32_ATIM_CCER_OFFSET || + offset == STM32_ATIM_BDTR_OFFSET || + offset == STM32_ATIM_DMAR_OFFSET || + offset == STM32_ATIM_AF1_OFFSET || + offset == STM32_ATIM_TISEL_OFFSET) + { + return true; + } + } + + return false; +} + +/**************************************************************************** + * Name: stm32pulsecount_getreg + * + * Description: + * Read the value of an pulsecount timer register + * + * Input Parameters: + * priv - A reference to the pulsecount timer status + * offset - The offset to the register to read + * + * Returned Value: + * The current contents of the specified register + * + ****************************************************************************/ + +static uint32_t stm32pulsecount_getreg( + struct stm32_pulsecounttimer_s *priv, int offset) +{ + uint32_t retval; + + if (stm32pulsecount_reg_is_32bit(priv->timtype, offset) == true) + { + /* 32-bit register */ + + retval = getreg32(priv->base + offset); + } + else + { + /* 16-bit register */ + + retval = getreg16(priv->base + offset); + } + + /* Return 32-bit value */ + + return retval; +} + +/**************************************************************************** + * Name: stm32pulsecount_putreg + * + * Description: + * Read the value of an pulsecount timer register + * + * Input Parameters: + * priv - A reference to the pulsecount timer status + * offset - The offset to the register to read + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void stm32pulsecount_putreg(struct stm32_pulsecounttimer_s *priv, + int offset, uint32_t value) +{ + if (stm32pulsecount_reg_is_32bit(priv->timtype, offset) == true) + { + /* 32-bit register */ + + putreg32(value, priv->base + offset); + } + else + { + /* 16-bit register */ + + putreg16((uint16_t)value, priv->base + offset); + } +} + +/**************************************************************************** + * Name: stm32pulsecount_modifyreg + * + * Description: + * Modify timer register (32-bit or 16-bit) + * + * Input Parameters: + * priv - A reference to the pulsecount timer status + * offset - The offset to the register to read + * clrbits - The bits to clear + * setbits - The bits to set + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void stm32pulsecount_modifyreg(struct stm32_pulsecounttimer_s *priv, + uint32_t offset, uint32_t clearbits, + uint32_t setbits) +{ + if (stm32pulsecount_reg_is_32bit(priv->timtype, offset) == true) + { + /* 32-bit register */ + + modifyreg32(priv->base + offset, clearbits, setbits); + } + else + { + /* 16-bit register */ + + modifyreg16(priv->base + offset, clearbits, setbits); + } +} + +/**************************************************************************** + * Name: stm32pulsecount_dumpregs + * + * Description: + * Dump all timer registers. + * + * Input Parameters: + * priv - A reference to the pulsecount timer status + * msg - A message to be printed on the screen + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_DEBUG_TIMER_INFO +static void stm32pulsecount_dumpregs(struct stm32_pulsecounttimer_s *priv, + const char *msg) +{ + _info("%s:\n", msg); + _info(" CR1: %04x CR2: %04x SMCR: %04x DIER: %04x\n", + stm32pulsecount_getreg(priv, STM32_GTIM_CR1_OFFSET), + stm32pulsecount_getreg(priv, STM32_GTIM_CR2_OFFSET), + stm32pulsecount_getreg(priv, STM32_GTIM_SMCR_OFFSET), + stm32pulsecount_getreg(priv, STM32_GTIM_DIER_OFFSET)); + _info(" SR: %04x EGR: %04x CCMR1: %04x CCMR2: %04x\n", + stm32pulsecount_getreg(priv, STM32_GTIM_SR_OFFSET), + stm32pulsecount_getreg(priv, STM32_GTIM_EGR_OFFSET), + stm32pulsecount_getreg(priv, STM32_GTIM_CCMR1_OFFSET), + stm32pulsecount_getreg(priv, STM32_GTIM_CCMR2_OFFSET)); + _info(" CCER: %04x CNT: %04x PSC: %04x ARR: %04x\n", + stm32pulsecount_getreg(priv, STM32_GTIM_CCER_OFFSET), + stm32pulsecount_getreg(priv, STM32_GTIM_CNT_OFFSET), + stm32pulsecount_getreg(priv, STM32_GTIM_PSC_OFFSET), + stm32pulsecount_getreg(priv, STM32_GTIM_ARR_OFFSET)); + _info(" CCR1: %04x CCR2: %04x CCR3: %04x CCR4: %04x\n", + stm32pulsecount_getreg(priv, STM32_GTIM_CCR1_OFFSET), + stm32pulsecount_getreg(priv, STM32_GTIM_CCR2_OFFSET), + stm32pulsecount_getreg(priv, STM32_GTIM_CCR3_OFFSET), + stm32pulsecount_getreg(priv, STM32_GTIM_CCR4_OFFSET)); + if (priv->timtype == TIMTYPE_ADVANCED) + { + _info(" RCR: %04x BDTR: %04x DCR: %04x DMAR: %04x\n", + stm32pulsecount_getreg(priv, STM32_ATIM_RCR_OFFSET), + stm32pulsecount_getreg(priv, STM32_ATIM_BDTR_OFFSET), + stm32pulsecount_getreg(priv, STM32_ATIM_DCR_OFFSET), + stm32pulsecount_getreg(priv, STM32_ATIM_DMAR_OFFSET)); + + _info(" AF1: %04x TISEL: %04x\n", + stm32pulsecount_getreg(priv, STM32_ATIM_AF1_OFFSET), + stm32pulsecount_getreg(priv, STM32_ATIM_TISEL_OFFSET)); + } +} +#endif + +/**************************************************************************** + * Name: stm32pulsecount_output_configure + * + * Description: + * Configure pulsecount output for given channel + * + * Input Parameters: + * priv - A reference to the pulsecount timer status + * channel - Timer output channel + * + * Returned Value: + * Zero on success; + ****************************************************************************/ + +static int +stm32pulsecount_output_configure(struct stm32_pulsecounttimer_s *priv, + uint8_t channel) +{ + uint32_t cr2; + uint32_t ccer; + + /* Get current registers state */ + + cr2 = stm32pulsecount_getreg(priv, STM32_GTIM_CR2_OFFSET); + ccer = stm32pulsecount_getreg(priv, STM32_GTIM_CCER_OFFSET); + + /* Reset the output polarity level of all channels (selects high + * polarity) + */ + + ccer &= ~(GTIM_CCER_CC1P << ((channel - 1) * 4)); + + /* Enable the output state of the selected channels */ + + ccer |= (GTIM_CCER_CC1E << ((channel - 1) * 4)); + + if (priv->timtype == TIMTYPE_ADVANCED) + { + cr2 &= ~(ATIM_CR2_OIS1 << ((channel - 1) * 2)); + } + + stm32pulsecount_modifyreg(priv, STM32_GTIM_CR2_OFFSET, 0, cr2); + stm32pulsecount_modifyreg(priv, STM32_GTIM_CCER_OFFSET, 0, ccer); + + return OK; +} + +/**************************************************************************** + * Name: stm32pulsecount_timer + * + * Description: + * (Re-)initialize the timer resources and start the pulsed output + * + * Input Parameters: + * priv - A reference to the lower half pulsecount driver state structure + * info - A reference to the characteristics of the pulsed output + * + * Returned Value: + * Zero on success; a negated errno value on failure + * + ****************************************************************************/ + +static int stm32pulsecount_timer(struct stm32_pulsecounttimer_s *priv, + const struct pulsecount_info_s *info) +{ + /* Calculated values */ + + uint32_t prescaler; + uint32_t timclk; + uint32_t reload; + uint32_t ccr; + ub16_t duty; + uint32_t chanmode = GTIM_CCMR_MODE_PWM1; + uint8_t channel; + + /* Register contents */ + + uint32_t cr1; + uint32_t ccmr1; +#if defined(HAVE_CCMR2) + uint32_t ccmr2; + uint32_t ocmode2; +#endif + + /* New timer register bit settings */ + + uint32_t ocmode1; + + DEBUGASSERT(priv != NULL && info != NULL); + + ccmr1 = stm32pulsecount_getreg(priv, STM32_GTIM_CCMR1_OFFSET); + +#if defined(HAVE_CCMR2) + ccmr2 = stm32pulsecount_getreg(priv, STM32_GTIM_CCMR2_OFFSET); +#endif + + _info("TIM%u channel: %u high: %" PRIu32 " ns low: %" PRIu32 + " ns count: %" PRIu32 "\n", + priv->timid, priv->channel.channel, info->high_ns, + info->low_ns, info->count); + + DEBUGASSERT(pulsecount_frequency(info) > 0); + + /* Disable all interrupts and DMA requests, clear all pending status */ + + stm32pulsecount_putreg(priv, STM32_GTIM_DIER_OFFSET, 0); + stm32pulsecount_putreg(priv, STM32_GTIM_SR_OFFSET, 0); + + /* Calculate optimal values for the timer prescaler and for the timer + * reload register. If 'frequency' is the desired frequency, then + * + * reload = timclk / frequency + * timclk = pclk / presc + * + * Or, + * + * reload = pclk / presc / frequency + * + * There are many solutions to this, but the best solution will be the + * one that has the largest reload value and the smallest prescaler value. + * That is the solution that should give us the most accuracy in the timer + * control. Subject to: + * + * 0 <= presc <= 65536 + * 1 <= reload <= 65535 + * + * So presc = pclk / 65535 / frequency would be optimal. + * + * Example: + * + * pclk = 42 MHz + * frequency = 100 Hz + * + * prescaler = 42,000,000 / 65,535 / 100 + * = 6.4 (or 7 -- taking the ceiling always) + * timclk = 42,000,000 / 7 + * = 6,000,000 + * reload = 6,000,000 / 100 + * = 60,000 + */ + + prescaler = (priv->pclk / pulsecount_frequency(info) + 65534) / 65535; + if (prescaler < 1) + { + prescaler = 1; + } + else if (prescaler > 65536) + { + prescaler = 65536; + } + + timclk = priv->pclk / prescaler; + + reload = timclk / pulsecount_frequency(info); + + if (reload < 2) + { + reload = 1; + } + else if (reload > 65535) + { + reload = 65535; + } + else + { + reload--; + } + + _info("TIM%u PCLK: %" PRIu32 " frequency: %" PRIu32 " " + "TIMCLK: %" PRIu32 " prescaler: %" PRIu32 + " reload: %" PRIu32 "\n", + priv->timid, priv->pclk, pulsecount_frequency(info), timclk, + prescaler, reload); + + /* Set up the timer CR1 register: + * + * 1,8 CKD[1:0] ARPE CMS[1:0] DIR OPM URS UDIS CEN + * 2-5 CKD[1:0] ARPE CMS DIR OPM URS UDIS CEN + * 6-7 ARPE OPM URS UDIS CEN + * 9-14 CKD[1:0] ARPE URS UDIS CEN + * 15-17 CKD[1:0] ARPE OPM URS UDIS CEN + */ + + cr1 = stm32pulsecount_getreg(priv, STM32_GTIM_CR1_OFFSET); + + /* Disable the timer until we get it configured */ + + cr1 &= ~GTIM_CR1_CEN; + + cr1 &= ~(GTIM_CR1_DIR | GTIM_CR1_CMS_MASK); + + cr1 |= GTIM_CR1_EDGE; + + /* Set the clock division to zero for all (but the basic timers, but there + * should be no basic timers in this context + */ + + cr1 &= ~GTIM_CR1_CKD_MASK; + stm32pulsecount_putreg(priv, STM32_GTIM_CR1_OFFSET, cr1); + + /* Set the reload and prescaler values */ + + stm32pulsecount_putreg(priv, STM32_GTIM_ARR_OFFSET, reload); + stm32pulsecount_putreg(priv, STM32_GTIM_PSC_OFFSET, (prescaler - 1)); + + /* Set the advanced timer's repetition counter */ + + if (priv->timtype == TIMTYPE_ADVANCED) + { + /* If a non-zero repetition count has been selected, then set the + * repetition counter to the count-1. stm32pulsecount_start() has + * already assured us that the count value is within range. + */ + + if (info->count > 0) + { + /* Save the remaining count and the number of counts that will have + * elapsed on the first interrupt. + */ + + /* If the first interrupt occurs at the end end of the first + * repetition count, then the count will be the same as the RCR + * value. + */ + + priv->prev = stm32pulsecount_pulsecount(info->count); + stm32pulsecount_putreg(priv, STM32_ATIM_RCR_OFFSET, + priv->prev - 1); + + /* Generate an update event to reload the prescaler. This should + * preload the RCR into active repetition counter. + */ + + stm32pulsecount_putreg(priv, STM32_ATIM_EGR_OFFSET, ATIM_EGR_UG); + + /* Now set the value of the RCR that will be loaded on the next + * update event. + */ + + priv->count = info->count; + priv->curr = stm32pulsecount_pulsecount(info->count + - priv->prev); + stm32pulsecount_putreg(priv, STM32_ATIM_RCR_OFFSET, + priv->curr - 1); + } + + /* Otherwise, just clear the repetition counter */ + + else + { + /* Set the repetition counter to zero */ + + stm32pulsecount_putreg(priv, STM32_ATIM_RCR_OFFSET, 0); + + /* Generate an update event to reload the prescaler */ + + stm32pulsecount_putreg(priv, STM32_ATIM_EGR_OFFSET, ATIM_EGR_UG); + } + } + + /* Handle channel specific setup */ + + ocmode1 = 0; +#if defined(HAVE_CCMR2) + ocmode2 = 0; +#endif + + duty = pulsecount_duty(info); + channel = priv->channel.channel; + + /* Duty cycle: + * + * duty cycle = ccr / reload (fractional value) + */ + + ccr = b16toi(duty * reload + b16HALF); + + _info("ccr: %" PRIu32 "\n", ccr); + + switch (channel) + { + case 1: + ocmode1 |= (GTIM_CCMR_CCS_CCOUT << GTIM_CCMR1_CC1S_SHIFT) | + (chanmode << GTIM_CCMR1_OC1M_SHIFT) | + GTIM_CCMR1_OC1PE; + stm32pulsecount_putreg(priv, STM32_GTIM_CCR1_OFFSET, ccr); + ccmr1 &= ~(GTIM_CCMR1_CC1S_MASK | GTIM_CCMR1_OC1M_MASK | + GTIM_CCMR1_OC1PE | GTIM_CCMR1_OC1M); + break; + + case 2: + ocmode1 |= (GTIM_CCMR_CCS_CCOUT << GTIM_CCMR1_CC2S_SHIFT) | + (chanmode << GTIM_CCMR1_OC2M_SHIFT) | + GTIM_CCMR1_OC2PE; + stm32pulsecount_putreg(priv, STM32_GTIM_CCR2_OFFSET, ccr); + ccmr1 &= ~(GTIM_CCMR1_CC2S_MASK | GTIM_CCMR1_OC2M_MASK | + GTIM_CCMR1_OC2PE | GTIM_CCMR1_OC2M); + break; + + case 3: + ocmode2 |= (ATIM_CCMR_CCS_CCOUT << ATIM_CCMR2_CC3S_SHIFT) | + (chanmode << ATIM_CCMR2_OC3M_SHIFT) | + ATIM_CCMR2_OC3PE; + stm32pulsecount_putreg(priv, STM32_ATIM_CCR3_OFFSET, ccr); + ccmr2 &= ~(ATIM_CCMR2_CC3S_MASK | ATIM_CCMR2_OC3M_MASK | + ATIM_CCMR2_OC3PE | ATIM_CCMR2_OC3M); + break; + + case 4: + ocmode2 |= (ATIM_CCMR_CCS_CCOUT << ATIM_CCMR2_CC4S_SHIFT) | + (chanmode << ATIM_CCMR2_OC4M_SHIFT) | + ATIM_CCMR2_OC4PE; + stm32pulsecount_putreg(priv, STM32_ATIM_CCR4_OFFSET, ccr); + ccmr2 &= ~(ATIM_CCMR2_CC4S_MASK | ATIM_CCMR2_OC4M_MASK | + ATIM_CCMR2_OC4PE | ATIM_CCMR2_OC4M); + break; + + default: + _err("ERROR: No such channel: %u\n", channel); + return -EINVAL; + } + + stm32pulsecount_output_configure(priv, channel); + + ccmr1 |= ocmode1; +#if defined(HAVE_CCMR2) + ccmr2 |= ocmode2; +#endif + + if (priv->timtype == TIMTYPE_ADVANCED) + { + uint32_t bdtr; + + /* Get current register state */ + + bdtr = stm32pulsecount_getreg(priv, STM32_ATIM_BDTR_OFFSET); + + bdtr &= ~(ATIM_BDTR_OSSI | ATIM_BDTR_OSSR); + bdtr |= ATIM_BDTR_MOE; + + stm32pulsecount_putreg(priv, STM32_ATIM_BDTR_OFFSET, bdtr); + } + + /* Save the modified register values */ + + putreg32(ccmr1, priv->base + STM32_GTIM_CCMR1_OFFSET); +#if defined(HAVE_CCMR2) + putreg32(ccmr2, priv->base + STM32_ATIM_CCMR2_OFFSET); +#endif + + /* Set the ARR Preload Bit */ + + cr1 = stm32pulsecount_getreg(priv, STM32_GTIM_CR1_OFFSET); + cr1 |= GTIM_CR1_ARPE; + stm32pulsecount_putreg(priv, STM32_GTIM_CR1_OFFSET, cr1); + + /* Setup update interrupt. If info->count is > 0, then we can + * be assured that stm32pulsecount_start() has already verified: (1) that + * this is an advanced timer, and that (2) the repetition count is within + * range. + */ + + if (info->count > 0) + { + /* Clear all pending interrupts and enable the update interrupt. */ + + stm32pulsecount_putreg(priv, STM32_GTIM_SR_OFFSET, 0); + stm32pulsecount_putreg(priv, STM32_GTIM_DIER_OFFSET, GTIM_DIER_UIE); + + /* Enable the timer */ + + cr1 |= GTIM_CR1_CEN; + stm32pulsecount_putreg(priv, STM32_GTIM_CR1_OFFSET, cr1); + + /* And enable timer interrupts at the NVIC */ + + up_enable_irq(priv->irq); + } + else + { + /* Just enable the timer, leaving all interrupts disabled */ + + cr1 |= GTIM_CR1_CEN; + stm32pulsecount_putreg(priv, STM32_GTIM_CR1_OFFSET, cr1); + } + + stm32pulsecount_dumpregs(priv, "After starting"); + return OK; +} + +/**************************************************************************** + * Name: stm32pulsecount_interrupt + * + * Description: + * Handle timer interrupts. + * + * Input Parameters: + * priv - A reference to the lower half pulsecount driver state structure + * + * Returned Value: + * Zero on success; a negated errno value on failure + ****************************************************************************/ + +static int stm32pulsecount_interrupt(struct stm32_pulsecounttimer_s *priv) +{ + uint16_t regval; + + /* Verify that this is an update interrupt. Nothing else is expected. */ + + regval = stm32pulsecount_getreg(priv, STM32_ATIM_SR_OFFSET); + DEBUGASSERT((regval & ATIM_SR_UIF) != 0); + + /* Clear the UIF interrupt bit */ + + stm32pulsecount_putreg(priv, STM32_ATIM_SR_OFFSET, regval & ~ATIM_SR_UIF); + + /* Calculate the new count by subtracting the number of pulses + * since the last interrupt. + */ + + if (priv->count <= priv->prev) + { + /* We are finished. Turn off the mast output to stop the output as + * quickly as possible. + */ + + regval = stm32pulsecount_getreg(priv, STM32_ATIM_BDTR_OFFSET); + regval &= ~ATIM_BDTR_MOE; + stm32pulsecount_putreg(priv, STM32_ATIM_BDTR_OFFSET, regval); + + /* Disable first interrupts, stop and reset the timer */ + + stm32pulsecount_stop((struct pulsecount_lowerhalf_s *)priv); + + /* Then perform the callback into the upper half driver */ + + pulsecount_expired(priv->handle); + + priv->handle = NULL; + priv->count = 0; + priv->prev = 0; + priv->curr = 0; + } + else + { + /* Decrement the count of pulses remaining using the number of + * pulses generated since the last interrupt. + */ + + priv->count -= priv->prev; + + /* Set up the next RCR. Set 'prev' to the value of the RCR that + * was loaded when the update occurred (just before this interrupt) + * and set 'curr' to the current value of the RCR register (which + * will bet loaded on the next update event). + */ + + priv->prev = priv->curr; + priv->curr = stm32pulsecount_pulsecount(priv->count - priv->prev); + stm32pulsecount_putreg(priv, STM32_ATIM_RCR_OFFSET, priv->curr - 1); + } + + /* Now all of the time critical stuff is done so we can do some debug + * output + */ + + _info("Update interrupt SR: %04x prev: %" PRIu32 " curr: %" PRIu32 + " count: %" PRIu32 "\n", + regval, priv->prev, priv->curr, priv->count); + + return OK; +} + +/**************************************************************************** + * Name: stm32pulsecount_tim1interrupt + * + * Description: + * Handle timer 1 interrupts. + * + * Input Parameters: + * Standard NuttX interrupt inputs + * + * Returned Value: + * Zero on success; a negated errno value on failure + * + ****************************************************************************/ + +static int stm32pulsecount_tim1interrupt(int irq, void *context, void *arg) +{ + return stm32pulsecount_interrupt(&g_pulsecount1dev); +} + +/**************************************************************************** + * Name: stm32pulsecount_pulsecount + * + * Description: + * Pick an optimal pulse count to program the RCR. + * + * Input Parameters: + * count - The total count remaining + * + * Returned Value: + * The recommended pulse count + * + ****************************************************************************/ + +static uint32_t stm32pulsecount_pulsecount(uint32_t count) +{ + /* The the remaining pulse count is less than or equal to the maximum, the + * just return the count. + */ + + if (count <= ATIM_RCR_REP_MAX) + { + return count; + } + + /* Otherwise, we have to be careful. We do not want a small number of + * counts at the end because we might have trouble responding fast enough. + * If the remaining count is less than 150% of the maximum, then return + * half of the maximum. In this case the final sequence will be between 64 + * and 128. + */ + + else if (count < (3 * ATIM_RCR_REP_MAX / 2)) + { + return (ATIM_RCR_REP_MAX + 1) >> 1; + } + + /* Otherwise, return the maximum. The final count will be 64 or more */ + + else + { + return ATIM_RCR_REP_MAX; + } +} + +/**************************************************************************** + * Name: stm32pulsecount_setapbclock + * + * Description: + * Enable or disable APB clock for the timer peripheral + * + * Input Parameters: + * dev - A reference to the lower half pulsecount driver state structure + * on - Enable clock if 'on' is 'true' and disable if 'false' + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void stm32pulsecount_setapbclock( + struct stm32_pulsecounttimer_s *priv, bool on) +{ + uint32_t en_bit; + uint32_t regaddr; + + /* Determine which timer to configure */ + + switch (priv->timid) + { +#ifdef CONFIG_STM32_TIM1_PULSECOUNT + case 1: + regaddr = STM32_RCC_APB2ENR; + en_bit = RCC_APB2ENR_TIM1EN; + break; +#endif + default: + return; + } + + /* Enable/disable APB 1/2 clock for timer */ + + if (on) + { + modifyreg32(regaddr, 0, en_bit); + } + else + { + modifyreg32(regaddr, en_bit, 0); + } +} + +/**************************************************************************** + * Name: stm32pulsecount_setup + * + * Description: + * This method is called when the driver is opened. The lower half driver + * should configure and initialize the device so that it is ready for use. + * It should not, however, output pulses until the start method is called. + * + * Input Parameters: + * dev - A reference to the lower half pulsecount driver state structure + * + * Returned Value: + * Zero on success; a negated errno value on failure + * + * Assumptions: + * APB1 or 2 clocking for the GPIOs has already been configured by the RCC + * logic at power up. + * + ****************************************************************************/ + +static int stm32pulsecount_setup(struct pulsecount_lowerhalf_s *dev) +{ + struct stm32_pulsecounttimer_s *priv = + (struct stm32_pulsecounttimer_s *)dev; + uint32_t pincfg; + + _info("TIM%u\n", priv->timid); + stm32pulsecount_dumpregs(priv, "Initially"); + + /* Enable APB1/2 clocking for timer. */ + + stm32pulsecount_setapbclock(priv, true); + + /* Configure the pulsecount output pins, but do not start the timer yet */ + + pincfg = priv->channel.pincfg; + if (pincfg != 0) + { + _info("pincfg: %08" PRIx32 "\n", pincfg); + + stm32_configgpio(pincfg); + } + + pulsecount_dumpgpio(pincfg, "pulsecount setup"); + + return OK; +} + +/**************************************************************************** + * Name: stm32pulsecount_shutdown + * + * Description: + * This method is called when the driver is closed. The lower half driver + * stop pulsed output, free any resources, disable the timer hardware, and + * put the system into the lowest possible power usage state + * + * Input Parameters: + * dev - A reference to the lower half pulsecount driver state structure + * + * Returned Value: + * Zero on success; a negated errno value on failure + * + ****************************************************************************/ + +static int stm32pulsecount_shutdown(struct pulsecount_lowerhalf_s *dev) +{ + struct stm32_pulsecounttimer_s *priv = + (struct stm32_pulsecounttimer_s *)dev; + uint32_t pincfg; + + _info("TIM%u\n", priv->timid); + + /* Make sure that the output has been stopped */ + + stm32pulsecount_stop(dev); + + /* Disable APB1/2 clocking for timer. */ + + stm32pulsecount_setapbclock(priv, false); + + /* Then put the GPIO pins back to the default state */ + + pincfg = priv->channel.pincfg; + if (pincfg != 0) + { + _info("pincfg: %08" PRIx32 "\n", pincfg); + + pincfg &= (GPIO_PORT_MASK | GPIO_PIN_MASK); + pincfg |= GPIO_INPUT | GPIO_FLOAT; + + stm32_configgpio(pincfg); + } + + return OK; +} + +/**************************************************************************** + * Name: stm32pulsecount_start + * + * Description: + * (Re-)initialize the timer resources and start the pulsed output + * + * Input Parameters: + * dev - A reference to the lower half pulsecount driver state structure + * info - A reference to the characteristics of the pulsed output + * + * Returned Value: + * Zero on success; a negated errno value on failure + * + ****************************************************************************/ + +static int stm32pulsecount_start(struct pulsecount_lowerhalf_s *dev, + const struct pulsecount_info_s *info, + void *handle) +{ + struct stm32_pulsecounttimer_s *priv = + (struct stm32_pulsecounttimer_s *)dev; + + /* Check if a pulsecount has been selected */ + + if (info->count > 0) + { + /* Only the advanced timers (TIM1,8 can support the pulse counting) */ + + if (priv->timtype != TIMTYPE_ADVANCED) + { + _err("ERROR: TIM%u cannot support pulse count: %" PRIu32 "\n", + priv->timid, info->count); + return -EPERM; + } + } + + /* Save the handle */ + + priv->handle = handle; + + /* Start the time */ + + return stm32pulsecount_timer(priv, info); +} + +/**************************************************************************** + * Name: stm32pulsecount_stop + * + * Description: + * Stop the pulsed output and reset the timer resources + * + * Input Parameters: + * dev - A reference to the lower half pulsecount driver state structure + * + * Returned Value: + * Zero on success; a negated errno value on failure + * + * Assumptions: + * This function is called to stop the pulsed output at anytime. This + * method is also called from the timer interrupt handler when a repetition + * count expires... automatically stopping the timer. + * + ****************************************************************************/ + +static int stm32pulsecount_stop(struct pulsecount_lowerhalf_s *dev) +{ + struct stm32_pulsecounttimer_s *priv = + (struct stm32_pulsecounttimer_s *)dev; + uint32_t resetbit; + uint32_t regaddr; + uint32_t regval; + irqstate_t flags; + + _info("TIM%u\n", priv->timid); + + /* Disable interrupts momentary to stop any ongoing timer processing and + * to prevent any concurrent access to the reset register. + */ + + flags = enter_critical_section(); + + /* Disable further interrupts and stop the timer */ + + stm32pulsecount_putreg(priv, STM32_GTIM_DIER_OFFSET, 0); + stm32pulsecount_putreg(priv, STM32_GTIM_SR_OFFSET, 0); + + /* Determine which timer to reset */ + + switch (priv->timid) + { +#ifdef CONFIG_STM32_TIM1_PULSECOUNT + case 1: + regaddr = STM32_RCC_APB2RSTR; + resetbit = RCC_APB2RSTR_TIM1RST; + break; +#endif + + default: + leave_critical_section(flags); + return -EINVAL; + } + + /* Reset the timer - stopping the output and putting the timer back + * into a state where stm32pulsecount_start() can be called. + */ + + regval = getreg32(regaddr); + regval |= resetbit; + putreg32(regval, regaddr); + + regval &= ~resetbit; + putreg32(regval, regaddr); + leave_critical_section(flags); + + _info("regaddr: %08" PRIx32 " resetbit: %08" PRIx32 "\n", + regaddr, resetbit); + stm32pulsecount_dumpregs(priv, "After stop"); + return OK; +} + +/**************************************************************************** + * Name: stm32pulsecount_ioctl + * + * Description: + * Lower-half logic may support platform-specific ioctl commands + * + * Input Parameters: + * dev - A reference to the lower half pulsecount driver state structure + * cmd - The ioctl command + * arg - The argument accompanying the ioctl command + * + * Returned Value: + * Zero on success; a negated errno value on failure + * + ****************************************************************************/ + +static int stm32pulsecount_ioctl(struct pulsecount_lowerhalf_s *dev, int cmd, + unsigned long arg) +{ +#ifdef CONFIG_DEBUG_TIMER_INFO + struct stm32_pulsecounttimer_s *priv = + (struct stm32_pulsecounttimer_s *)dev; + + /* There are no platform-specific ioctl commands */ + + _info("TIM%u\n", priv->timid); +#endif + return -ENOTTY; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_pulsecountinitialize + * + * Description: + * Initialize one timer for use with the upper-level pulsecount driver. + * + * Input Parameters: + * timer - A number identifying the timer use. The number of valid timer + * IDs varies with the STM32 MCU and MCU family. This pulsecount driver + * supports TIM1 only on STM32F0/L0/G0. + * + * Returned Value: + * On success, a pointer to the STM32 lower half pulsecount driver is + * returned. NULL is returned on any failure. + * + ****************************************************************************/ + +struct pulsecount_lowerhalf_s *stm32_pulsecountinitialize(int timer) +{ + struct stm32_pulsecounttimer_s *lower; + + _info("TIM%u\n", timer); + + switch (timer) + { +#ifdef CONFIG_STM32_TIM1_PULSECOUNT + case 1: + lower = &g_pulsecount1dev; + + /* Attach but disable the TIM1 update interrupt */ + + irq_attach(lower->irq, stm32pulsecount_tim1interrupt, NULL); + up_disable_irq(lower->irq); + break; +#endif + + default: + _err("ERROR: No such timer configured\n"); + return NULL; + } + + return (struct pulsecount_lowerhalf_s *)lower; +} + +#endif /* CONFIG_STM32_TIMx_PULSECOUNT */ diff --git a/arch/arm/src/common/stm32/stm32_pulsecount_m3m4_v1v2v3.c b/arch/arm/src/common/stm32/stm32_pulsecount_m3m4_v1v2v3.c new file mode 100644 index 0000000000000..d73a83d002294 --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_pulsecount_m3m4_v1v2v3.c @@ -0,0 +1,1775 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_pulsecount_m3m4_v1v2v3.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include + +#include +#include + +#include "arm_internal.h" +#include "chip.h" +#include "stm32_pulsecount.h" +#include "stm32_rcc.h" +#include "stm32_gpio.h" +#include "stm32_tim.h" + +/* This module then only compiles if there is at least one enabled timer + * intended for use with the pulsecount upper half driver. + * + * It implements support for both: + * 1. STM32 TIMER IP version 1 - F0, F1, F2, F37x, F4, L0, L1 + * 2. STM32 TIMER IP version 2 - F3 (no F37x), F7, H7, L4, L4+ + */ + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Timer Definitions ********************************************************/ + +/* Pulsecount is supported by advanced timers only. */ + +#define TIMTYPE_ADVANCED 5 +#define TIMTYPE_TIM1 TIMTYPE_ADVANCED +#define TIMTYPE_TIM8 TIMTYPE_ADVANCED + +/* Advanced timer clock source, RCC EN offset, enable bit, + * RCC RST offset, reset bit to use + */ + +# define TIMCLK_TIM1 STM32_APB2_TIM1_CLKIN +# define TIMRCCEN_TIM1 STM32_RCC_APB2ENR +# define TIMEN_TIM1 RCC_APB2ENR_TIM1EN +# define TIMRCCRST_TIM1 STM32_RCC_APB2RSTR +# define TIMRST_TIM1 RCC_APB2RSTR_TIM1RST +# define TIMCLK_TIM8 STM32_APB2_TIM8_CLKIN +# define TIMRCCEN_TIM8 STM32_RCC_APB2ENR +# define TIMEN_TIM8 RCC_APB2ENR_TIM8EN +# define TIMRCCRST_TIM8 STM32_RCC_APB2RSTR +# define TIMRST_TIM8 RCC_APB2RSTR_TIM8RST + +/* Default GPIO pins state */ + +#if defined(CONFIG_STM32_STM32F10XX) +# define PINCFG_DEFAULT (GPIO_INPUT | GPIO_CNF_INFLOAT | GPIO_MODE_INPUT) +#elif defined(CONFIG_STM32_STM32F20XX) || \ + defined(CONFIG_STM32_STM32F30XX) || \ + defined(CONFIG_STM32_STM32F33XX) || \ + defined(CONFIG_STM32_STM32F37XX) || \ + defined(CONFIG_STM32_STM32F4XXX) || \ + defined(CONFIG_STM32_STM32L15XX) || \ + defined(CONFIG_STM32_STM32G4XXX) +# define PINCFG_DEFAULT (GPIO_INPUT | GPIO_FLOAT) +#else +# error "Unrecognized STM32 chip" +#endif + +#define PULSECOUNT_POL_NEG 1 +#define PULSECOUNT_IDLE_ACTIVE 1 + +/* Debug ********************************************************************/ + +#ifdef CONFIG_DEBUG_TIMER_INFO +# define pulsecount_dumpgpio(p,m) stm32_dumpgpio(p,m) +#else +# define pulsecount_dumpgpio(p,m) +#endif + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/* Pulsecount output configuration */ + +struct stm32_out_s +{ + uint8_t in_use:1; + uint8_t pol:1; + uint8_t idle:1; + uint8_t _res:5; + uint32_t pincfg; +}; + +/* Pulsecount channel configuration */ + +struct stm32_chan_s +{ + uint8_t channel; + struct stm32_out_s out1; +}; + +/* This structure represents the state of one pulsecount timer */ + +struct stm32_tim_s +{ + struct stm32_chan_s channel; + uint8_t timid:5; + uint8_t timtype:3; + uint8_t t_dts:3; + uint8_t _res:5; + uint8_t irq; + uint8_t prev; + uint8_t curr; + uint32_t count; + uint32_t frequency; + uint32_t base; + uint32_t pclk; + void *handle; +}; + +struct stm32_pulsecount_s +{ + const struct pulsecount_ops_s *ops; + struct stm32_tim_s *timer; +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/* Register access */ + +static uint32_t pulsecount_getreg(struct stm32_tim_s *priv, int offset); +static void pulsecount_putreg(struct stm32_tim_s *priv, int offset, + uint32_t value); +static void pulsecount_modifyreg(struct stm32_tim_s *priv, uint32_t offset, + uint32_t clearbits, uint32_t setbits); + +#ifdef CONFIG_DEBUG_TIMER_INFO +static void pulsecount_dumpregs(struct pulsecount_lowerhalf_s *dev, + const char *msg); +#else +# define pulsecount_dumpregs(priv,msg) +#endif + +/* Timer management */ + +static int pulsecount_ccr_update(struct pulsecount_lowerhalf_s *dev, + uint8_t index, uint32_t ccr); +static int pulsecount_duty_update(struct pulsecount_lowerhalf_s *dev, + uint8_t channel, ub16_t duty); +static int pulsecount_frequency_update(struct pulsecount_lowerhalf_s *dev, + uint32_t frequency); +static int pulsecount_timer_configure(struct stm32_tim_s *priv); +static int pulsecount_channel_configure(struct pulsecount_lowerhalf_s *dev, + uint8_t channel); +static int pulsecount_output_configure(struct stm32_tim_s *priv, + struct stm32_chan_s *chan); +static int pulsecount_outputs_enable(struct pulsecount_lowerhalf_s *dev, + uint16_t outputs, bool state); +static void pulsecount_moe_enable(struct pulsecount_lowerhalf_s *dev, + bool enable); +static int pulsecount_configure(struct pulsecount_lowerhalf_s *dev); +static int pulsecount_timer(struct pulsecount_lowerhalf_s *dev, + const struct pulsecount_info_s *info); +static int pulsecount_interrupt(struct pulsecount_lowerhalf_s *dev); +# ifdef CONFIG_STM32_TIM1_PULSECOUNT +static int pulsecount_tim1interrupt(int irq, void *context, void *arg); +# endif +# ifdef CONFIG_STM32_TIM8_PULSECOUNT +static int pulsecount_tim8interrupt(int irq, void *context, void *arg); +# endif +static uint8_t pulsecount_count(uint32_t count); + +/* Pulsecount driver methods */ + +static int pulsecount_ll_setup(struct pulsecount_lowerhalf_s *dev); +static int pulsecount_ll_shutdown(struct pulsecount_lowerhalf_s *dev); + +static int pulsecount_ll_stop(struct pulsecount_lowerhalf_s *dev); +static int pulsecount_ll_ioctl(struct pulsecount_lowerhalf_s *dev, + int cmd, unsigned long arg); + +static int pulsecount_setup(struct pulsecount_lowerhalf_s *dev); +static int pulsecount_shutdown(struct pulsecount_lowerhalf_s *dev); +static int pulsecount_start(struct pulsecount_lowerhalf_s *dev, + const struct pulsecount_info_s *info, + void *handle); +static int pulsecount_stop(struct pulsecount_lowerhalf_s *dev); +static int pulsecount_ioctl(struct pulsecount_lowerhalf_s *dev, + int cmd, unsigned long arg); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#ifdef CONFIG_STM32_TIM1_PULSECOUNT + +static struct stm32_tim_s g_pulsecount1dev = +{ + .channel = + { + .channel = CONFIG_STM32_TIM1_PULSECOUNT_CHANNEL, +#if CONFIG_STM32_TIM1_PULSECOUNT_CHANNEL == 1 + .out1 = + { + .in_use = 1, + .pol = CONFIG_STM32_TIM1_PULSECOUNT_POL, + .idle = CONFIG_STM32_TIM1_PULSECOUNT_IDLE, + .pincfg = GPIO_TIM1_CH1OUT, + }, +#elif CONFIG_STM32_TIM1_PULSECOUNT_CHANNEL == 2 + .out1 = + { + .in_use = 1, + .pol = CONFIG_STM32_TIM1_PULSECOUNT_POL, + .idle = CONFIG_STM32_TIM1_PULSECOUNT_IDLE, + .pincfg = GPIO_TIM1_CH2OUT, + }, +#elif CONFIG_STM32_TIM1_PULSECOUNT_CHANNEL == 3 + .out1 = + { + .in_use = 1, + .pol = CONFIG_STM32_TIM1_PULSECOUNT_POL, + .idle = CONFIG_STM32_TIM1_PULSECOUNT_IDLE, + .pincfg = GPIO_TIM1_CH3OUT, + }, +#elif CONFIG_STM32_TIM1_PULSECOUNT_CHANNEL == 4 + .out1 = + { + .in_use = 1, + .pol = CONFIG_STM32_TIM1_PULSECOUNT_POL, + .idle = CONFIG_STM32_TIM1_PULSECOUNT_IDLE, + .pincfg = GPIO_TIM1_CH4OUT, + }, +#endif + }, + .timid = 1, + .timtype = TIMTYPE_TIM1, + .t_dts = CONFIG_STM32_TIM1_PULSECOUNT_TDTS, + .irq = STM32_IRQ_TIM1UP, + .base = STM32_TIM1_BASE, + .pclk = TIMCLK_TIM1, +}; + +#endif /* CONFIG_STM32_TIM1_PULSECOUNT */ + +#ifdef CONFIG_STM32_TIM8_PULSECOUNT + +static struct stm32_tim_s g_pulsecount8dev = +{ + .channel = + { + .channel = CONFIG_STM32_TIM8_PULSECOUNT_CHANNEL, +#if CONFIG_STM32_TIM8_PULSECOUNT_CHANNEL == 1 + .out1 = + { + .in_use = 1, + .pol = CONFIG_STM32_TIM8_PULSECOUNT_POL, + .idle = CONFIG_STM32_TIM8_PULSECOUNT_IDLE, + .pincfg = GPIO_TIM8_CH1OUT, + }, +#elif CONFIG_STM32_TIM8_PULSECOUNT_CHANNEL == 2 + .out1 = + { + .in_use = 1, + .pol = CONFIG_STM32_TIM8_PULSECOUNT_POL, + .idle = CONFIG_STM32_TIM8_PULSECOUNT_IDLE, + .pincfg = GPIO_TIM8_CH2OUT, + }, +#elif CONFIG_STM32_TIM8_PULSECOUNT_CHANNEL == 3 + .out1 = + { + .in_use = 1, + .pol = CONFIG_STM32_TIM8_PULSECOUNT_POL, + .idle = CONFIG_STM32_TIM8_PULSECOUNT_IDLE, + .pincfg = GPIO_TIM8_CH3OUT, + }, +#elif CONFIG_STM32_TIM8_PULSECOUNT_CHANNEL == 4 + .out1 = + { + .in_use = 1, + .pol = CONFIG_STM32_TIM8_PULSECOUNT_POL, + .idle = CONFIG_STM32_TIM8_PULSECOUNT_IDLE, + .pincfg = GPIO_TIM8_CH4OUT, + }, +#endif + }, + .timid = 8, + .timtype = TIMTYPE_TIM8, + .t_dts = CONFIG_STM32_TIM8_PULSECOUNT_TDTS, + .irq = STM32_IRQ_TIM8UP, + .base = STM32_TIM8_BASE, + .pclk = TIMCLK_TIM8, +}; + +#endif /* CONFIG_STM32_TIM8_PULSECOUNT */ + +static const struct pulsecount_ops_s g_pulsecountops = +{ + .setup = pulsecount_setup, + .shutdown = pulsecount_shutdown, + .start = pulsecount_start, + .stop = pulsecount_stop, + .ioctl = pulsecount_ioctl, +}; + +#ifdef CONFIG_STM32_TIM1_PULSECOUNT +static struct stm32_pulsecount_s g_pulsecount1lower = +{ + .ops = &g_pulsecountops, + .timer = &g_pulsecount1dev, +}; +#endif + +#ifdef CONFIG_STM32_TIM8_PULSECOUNT +static struct stm32_pulsecount_s g_pulsecount8lower = +{ + .ops = &g_pulsecountops, + .timer = &g_pulsecount8dev, +}; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: pulsecount_reg_is_32bit + ****************************************************************************/ + +static bool pulsecount_reg_is_32bit(uint8_t timtype, uint32_t offset) +{ + bool ret = false; + + if (timtype == TIMTYPE_ADVANCED) + { + if (offset == STM32_ATIM_CR2_OFFSET || + offset == STM32_ATIM_CCMR1_OFFSET || + offset == STM32_ATIM_CCMR2_OFFSET || + offset == STM32_ATIM_CCER_OFFSET || + offset == STM32_ATIM_BDTR_OFFSET) + { + ret = true; + } + } + + return ret; +} + +/**************************************************************************** + * Name: pulsecount_getreg + * + * Description: + * Read the value of an pulsecount timer register + * + * Input Parameters: + * priv - A reference to the pulsecount block status + * offset - The offset to the register to read + * + * Returned Value: + * The current contents of the specified register + * + ****************************************************************************/ + +static uint32_t pulsecount_getreg(struct stm32_tim_s *priv, int offset) +{ + uint32_t retval = 0; + + if (pulsecount_reg_is_32bit(priv->timtype, offset) == true) + { + /* 32-bit register */ + + retval = getreg32(priv->base + offset); + } + else + { + /* 16-bit register */ + + retval = getreg16(priv->base + offset); + } + + /* Return 32-bit value */ + + return retval; +} + +/**************************************************************************** + * Name: pulsecount_putreg + * + * Description: + * Read the value of an pulsecount timer register + * + * Input Parameters: + * priv - A reference to the pulsecount block status + * offset - The offset to the register to read + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void pulsecount_putreg(struct stm32_tim_s *priv, int offset, + uint32_t value) +{ + if (pulsecount_reg_is_32bit(priv->timtype, offset) == true) + { + /* 32-bit register */ + + putreg32(value, priv->base + offset); + } + else + { + /* 16-bit register */ + + putreg16((uint16_t)value, priv->base + offset); + } +} + +/**************************************************************************** + * Name: pulsecount_modifyreg + * + * Description: + * Modify timer register (32-bit or 16-bit) + * + * Input Parameters: + * priv - A reference to the pulsecount block status + * offset - The offset to the register to read + * clrbits - The bits to clear + * setbits - The bits to set + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void pulsecount_modifyreg(struct stm32_tim_s *priv, uint32_t offset, + uint32_t clearbits, uint32_t setbits) +{ + if (pulsecount_reg_is_32bit(priv->timtype, offset) == true) + { + /* 32-bit register */ + + modifyreg32(priv->base + offset, clearbits, setbits); + } + else + { + /* 16-bit register */ + + modifyreg16(priv->base + offset, (uint16_t)clearbits, + (uint16_t)setbits); + } +} + +/**************************************************************************** + * Name: pulsecount_dumpregs + * + * Description: + * Dump all timer registers. + * + * Input Parameters: + * dev - A reference to the lower half pulsecount driver state structure + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_DEBUG_TIMER_INFO +static void pulsecount_dumpregs(struct pulsecount_lowerhalf_s *dev, + const char *msg) +{ + struct stm32_tim_s *priv = (struct stm32_tim_s *)dev; + + _info("%s:\n", msg); + _info(" CR1: %04x CR2: %04x SMCR: %04x DIER: %04x\n", + pulsecount_getreg(priv, STM32_GTIM_CR1_OFFSET), + pulsecount_getreg(priv, STM32_GTIM_CR2_OFFSET), + pulsecount_getreg(priv, STM32_GTIM_SMCR_OFFSET), + pulsecount_getreg(priv, STM32_GTIM_DIER_OFFSET)); + + _info(" SR: %04x EGR: %04x CCMR1: %04x CCMR2: %04x\n", + pulsecount_getreg(priv, STM32_GTIM_SR_OFFSET), + pulsecount_getreg(priv, STM32_GTIM_EGR_OFFSET), + pulsecount_getreg(priv, STM32_GTIM_CCMR1_OFFSET), + pulsecount_getreg(priv, STM32_GTIM_CCMR2_OFFSET)); + + _info(" CCER: %04x CNT: %04x PSC: %04x ARR: %04x\n", + pulsecount_getreg(priv, STM32_GTIM_CCER_OFFSET), + pulsecount_getreg(priv, STM32_GTIM_CNT_OFFSET), + pulsecount_getreg(priv, STM32_GTIM_PSC_OFFSET), + pulsecount_getreg(priv, STM32_GTIM_ARR_OFFSET)); + + if (priv->timid == 1 || priv->timid == 8) + { + _info(" RCR: %04x BDTR: %04x\n", + pulsecount_getreg(priv, STM32_ATIM_RCR_OFFSET), + pulsecount_getreg(priv, STM32_ATIM_BDTR_OFFSET)); + } + + _info(" CCR1: %04x CCR2: %04x CCR3: %04x CCR4: %04x\n", + pulsecount_getreg(priv, STM32_GTIM_CCR1_OFFSET), + pulsecount_getreg(priv, STM32_GTIM_CCR2_OFFSET), + pulsecount_getreg(priv, STM32_GTIM_CCR3_OFFSET), + pulsecount_getreg(priv, STM32_GTIM_CCR4_OFFSET)); + + _info(" DCR: %04x DMAR: %04x\n", + pulsecount_getreg(priv, STM32_GTIM_DCR_OFFSET), + pulsecount_getreg(priv, STM32_GTIM_DMAR_OFFSET)); +} +#endif + +/**************************************************************************** + * Name: pulsecount_ccr_update + ****************************************************************************/ + +static int pulsecount_ccr_update(struct pulsecount_lowerhalf_s *dev, + uint8_t index, uint32_t ccr) +{ + struct stm32_tim_s *priv = (struct stm32_tim_s *)dev; + uint32_t offset = 0; + + /* CCR channel indices are one-based to match timer channel numbers. */ + + switch (index) + { + case 1: + { + offset = STM32_GTIM_CCR1_OFFSET; + break; + } + + case 2: + { + offset = STM32_GTIM_CCR2_OFFSET; + break; + } + + case 3: + { + offset = STM32_GTIM_CCR3_OFFSET; + break; + } + + case 4: + { + offset = STM32_GTIM_CCR4_OFFSET; + break; + } + + default: + { + _err("ERROR: No such CCR: %u\n", index); + return -EINVAL; + } + } + + /* Update CCR register */ + + pulsecount_putreg(priv, offset, ccr); + + return OK; +} + +/**************************************************************************** + * Name: pulsecount_duty_update + * + * Description: + * Try to change only channel duty + * + * Input Parameters: + * dev - A reference to the lower half driver state structure + * channel - Channel to by updated + * duty - New duty + * + * Returned Value: + * Zero on success; a negated errno value on failure + * + ****************************************************************************/ + +static int pulsecount_duty_update(struct pulsecount_lowerhalf_s *dev, + uint8_t channel, ub16_t duty) +{ + struct stm32_tim_s *priv = (struct stm32_tim_s *)dev; + uint32_t reload = 0; + uint32_t ccr = 0; + + /* We don't want compilation warnings if no DEBUGASSERT */ + + UNUSED(priv); + + DEBUGASSERT(priv != NULL); + + _info("TIM%u channel: %u duty: %08" PRIx32 "\n", + priv->timid, channel, duty); + + /* Get the reload values */ + + reload = pulsecount_getreg(priv, STM32_GTIM_ARR_OFFSET); + + /* Duty cycle: + * + * duty cycle = ccr / reload (fractional value) + */ + + ccr = b16toi(duty * reload + b16HALF); + + _info("ccr: %" PRIu32 "\n", ccr); + + /* Write corresponding CCR register */ + + return pulsecount_ccr_update(dev, channel, ccr); +} + +/**************************************************************************** + * Name: pulsecount_frequency_update + * + * Description: + * Update a pulsecount timer frequency + * + ****************************************************************************/ + +static int pulsecount_frequency_update(struct pulsecount_lowerhalf_s *dev, + uint32_t frequency) +{ + struct stm32_tim_s *priv = (struct stm32_tim_s *)dev; + uint32_t reload = 0; + uint32_t timclk = 0; + uint32_t prescaler = 0; + + /* Calculate optimal values for the timer prescaler and for the timer + * reload register. If 'frequency' is the desired frequency, then + * + * reload = timclk / frequency + * timclk = pclk / presc + * + * Or, + * + * reload = pclk / presc / frequency + * + * There are many solutions to this, but the best solution will be the one + * that has the largest reload value and the smallest prescaler value. + * That is the solution that should give us the most accuracy in the timer + * control. Subject to: + * + * 0 <= presc <= 65536 + * 1 <= reload <= 65535 + * + * So presc = pclk / 65535 / frequency would be optimal. + * + * Example: + * + * pclk = 42 MHz + * frequency = 100 Hz + * + * prescaler = 42,000,000 / 65,535 / 100 + * = 6.4 (or 7 -- taking the ceiling always) + * timclk = 42,000,000 / 7 + * = 6,000,000 + * reload = 6,000,000 / 100 + * = 60,000 + */ + + prescaler = (priv->pclk / frequency + 65534) / 65535; + if (prescaler < 1) + { + prescaler = 1; + } + else if (prescaler > 65536) + { + prescaler = 65536; + } + + timclk = priv->pclk / prescaler; + + reload = timclk / frequency; + if (reload < 2) + { + reload = 1; + } + else if (reload > 65535) + { + reload = 65535; + } + else + { + reload--; + } + + _info("TIM%u PCLK: %" PRIu32" frequency: %" PRIu32 + " TIMCLK: %" PRIu32 " " + "prescaler: %" PRIu32 " reload: %" PRIu32 "\n", + priv->timid, priv->pclk, frequency, timclk, prescaler, reload); + + /* Set the reload and prescaler values */ + + pulsecount_putreg(priv, STM32_GTIM_ARR_OFFSET, reload); + pulsecount_putreg(priv, STM32_GTIM_PSC_OFFSET, (uint16_t)(prescaler - 1)); + + return OK; +} + +/**************************************************************************** + * Name: pulsecount_timer_configure + * + * Description: + * Initial configuration for pulsecount timer + * + ****************************************************************************/ + +static int pulsecount_timer_configure(struct stm32_tim_s *priv) +{ + uint16_t cr1 = 0; + + /* Set up the advanced timer CR1 register. */ + + cr1 = pulsecount_getreg(priv, STM32_GTIM_CR1_OFFSET); + + /* Pulsecount always uses edge-aligned up-counting mode. */ + + cr1 &= ~(GTIM_CR1_DIR | GTIM_CR1_CMS_MASK); + cr1 |= GTIM_CR1_EDGE; + cr1 &= ~GTIM_CR1_CKD_MASK; + cr1 |= priv->t_dts << GTIM_CR1_CKD_SHIFT; + + /* Enable ARR preload to preserve the previous pulsecount behavior. */ + + cr1 |= GTIM_CR1_ARPE; + + /* Write CR1 */ + + pulsecount_putreg(priv, STM32_GTIM_CR1_OFFSET, cr1); + + return OK; +} + +/**************************************************************************** + * Name: pulsecount_channel_configure + * + * Description: + * Configure pulsecount output compare for a channel + * + ****************************************************************************/ + +static int pulsecount_channel_configure(struct pulsecount_lowerhalf_s *dev, + uint8_t channel) +{ + struct stm32_tim_s *priv = (struct stm32_tim_s *)dev; + uint32_t chanmode = 0; + uint32_t ocmode = 0; + uint32_t ccmr = 0; + uint32_t offset = 0; + int ret = OK; + + /* Configure output compare mode */ + + chanmode = GTIM_CCMR_MODE_PWM1; + + /* Get CCMR offset */ + + switch (channel) + { + case 1: + case 2: + { + offset = STM32_GTIM_CCMR1_OFFSET; + break; + } + + case 3: + case 4: + { + offset = STM32_GTIM_CCMR2_OFFSET; + break; + } + + default: + { + _err("ERROR: No such channel: %u\n", channel); + ret = -EINVAL; + goto errout; + } + } + + /* Get current registers */ + + ccmr = pulsecount_getreg(priv, offset); + + /* output compare configuration. + * NOTE: The CCMRx registers are identical if the channels are outputs. + */ + + switch (channel) + { + /* Configure channel 1/3 */ + + case 1: + case 3: + { + ccmr &= ~(ATIM_CCMR1_CC1S_MASK | ATIM_CCMR1_OC1M_MASK | + ATIM_CCMR1_OC1PE); + ocmode |= (ATIM_CCMR_CCS_CCOUT << ATIM_CCMR1_CC1S_SHIFT); + ocmode |= (chanmode << ATIM_CCMR1_OC1M_SHIFT); + ocmode |= ATIM_CCMR1_OC1PE; +#ifdef HAVE_IP_TIMERS_V2 + ccmr &= ~(ATIM_CCMR1_OC1M); +#endif + break; + } + + /* Configure channel 2/4 */ + + case 2: + case 4: + { + ccmr &= ~(ATIM_CCMR1_CC2S_MASK | ATIM_CCMR1_OC2M_MASK | + ATIM_CCMR1_OC2PE); + ocmode |= (ATIM_CCMR_CCS_CCOUT << ATIM_CCMR1_CC2S_SHIFT); + ocmode |= (chanmode << ATIM_CCMR1_OC2M_SHIFT); + ocmode |= ATIM_CCMR1_OC2PE; +#ifdef HAVE_IP_TIMERS_V2 + ccmr &= ~(ATIM_CCMR1_OC2M); +#endif + break; + } + } + + /* Set the selected output compare configuration */ + + ccmr |= ocmode; + + /* Write CCMRx registers */ + + pulsecount_putreg(priv, offset, ccmr); + +errout: + return ret; +} + +/**************************************************************************** + * Name: pulsecount_output_configure + * + * Description: + * Configure pulsecount output for given channel + * + ****************************************************************************/ + +static int pulsecount_output_configure(struct stm32_tim_s *priv, + struct stm32_chan_s *chan) +{ + uint32_t cr2 = 0; + uint32_t ccer = 0; + uint8_t channel = 0; + + /* Get channel */ + + channel = chan->channel; + + /* Get current registers state */ + + cr2 = pulsecount_getreg(priv, STM32_GTIM_CR2_OFFSET); + ccer = pulsecount_getreg(priv, STM32_GTIM_CCER_OFFSET); + + /* | OISx | IDLE | advanced timers | CR2 register + * | CCxP | POL | all pulsecount timers | CCER register + */ + + /* Configure output polarity (all pulsecount timers) */ + + if (chan->out1.pol == PULSECOUNT_POL_NEG) + { + ccer |= (GTIM_CCER_CC1P << ((channel - 1) * 4)); + } + else + { + ccer &= ~(GTIM_CCER_CC1P << ((channel - 1) * 4)); + } + + if (priv->timtype == TIMTYPE_ADVANCED) + { + /* Configure output IDLE State */ + + if (chan->out1.idle == PULSECOUNT_IDLE_ACTIVE) + { + cr2 |= (ATIM_CR2_OIS1 << ((channel - 1) * 2)); + } + else + { + cr2 &= ~(ATIM_CR2_OIS1 << ((channel - 1) * 2)); + } + } + + /* Write registers */ + + pulsecount_modifyreg(priv, STM32_GTIM_CR2_OFFSET, 0, cr2); + pulsecount_modifyreg(priv, STM32_GTIM_CCER_OFFSET, 0, ccer); + + return OK; +} + +/**************************************************************************** + * Name: pulsecount_outputs_enable + * + * Description: + * Enable/disable given timer pulsecount outputs. + * + * NOTE: This is bulk operation - we can enable/disable many outputs + * at one time + * + * Input Parameters: + * dev - A reference to the lower half driver state structure + * outputs - outputs to set (look at enum stm32_pulsecount_chan_e) + * state - Enable/disable operation + * + ****************************************************************************/ + +static int pulsecount_outputs_enable(struct pulsecount_lowerhalf_s *dev, + uint16_t outputs, bool state) +{ + struct stm32_tim_s *priv = (struct stm32_tim_s *)dev; + uint32_t ccer = 0; + uint32_t regval = 0; + + /* Get current register state */ + + ccer = pulsecount_getreg(priv, STM32_GTIM_CCER_OFFSET); + + /* Get outputs configuration */ + + regval |= ((outputs & (1 << 0)) ? GTIM_CCER_CC1E : 0); + regval |= ((outputs & (1 << 2)) ? GTIM_CCER_CC2E : 0); + regval |= ((outputs & (1 << 4)) ? GTIM_CCER_CC3E : 0); + regval |= ((outputs & (1 << 6)) ? GTIM_CCER_CC4E : 0); + + if (state == true) + { + /* Enable outputs - set bits */ + + ccer |= regval; + } + else + { + /* Disable outputs - reset bits */ + + ccer &= ~regval; + } + + /* Write register */ + + pulsecount_putreg(priv, STM32_GTIM_CCER_OFFSET, ccer); + + return OK; +} + +/**************************************************************************** + * Name: pulsecount_moe_enable + ****************************************************************************/ + +static void pulsecount_moe_enable(struct pulsecount_lowerhalf_s *dev, + bool enable) +{ + struct stm32_tim_s *priv = (struct stm32_tim_s *)dev; + + if (enable) + { + pulsecount_modifyreg(priv, STM32_ATIM_BDTR_OFFSET, 0, ATIM_BDTR_MOE); + } + else + { + pulsecount_modifyreg(priv, STM32_ATIM_BDTR_OFFSET, ATIM_BDTR_MOE, 0); + } +} + +/**************************************************************************** + * Name: pulsecount_outputs_from_channels + * + * Description: + * Get enabled outputs configuration from the pulsecount timer state + * + ****************************************************************************/ + +static uint16_t +pulsecount_outputs_from_channels(struct stm32_tim_s *priv, uint8_t selected) +{ + uint16_t outputs = 0; + uint8_t channel; + + channel = priv->channel.channel; + + if (channel != 0 && (selected == 0 || channel == selected) && + priv->channel.out1.in_use == 1) + { + outputs = (1 << ((channel - 1) * 2)); + } + + return outputs; +} + +/**************************************************************************** + * Name: pulsecount_configure + * + * Description: + * Configure pulsecount timer in PULSECOUNT mode + * + ****************************************************************************/ + +static int pulsecount_configure(struct pulsecount_lowerhalf_s *dev) +{ + struct stm32_tim_s *priv = (struct stm32_tim_s *)dev; + uint16_t outputs = 0; + int ret = OK; + + /* NOTE: leave timer counter disabled and all outputs disabled! */ + + /* Disable the timer until we get it configured */ + + pulsecount_modifyreg(priv, STM32_GTIM_CR1_OFFSET, GTIM_CR1_CEN, 0); + + /* Get configured outputs */ + + outputs = pulsecount_outputs_from_channels(priv, 0); + + /* Disable configured outputs before the timer is reconfigured. */ + + ret = pulsecount_outputs_enable(dev, outputs, false); + if (ret < 0) + { + goto errout; + } + + /* Initial timer configuration */ + + ret = pulsecount_timer_configure(priv); + if (ret < 0) + { + goto errout; + } + + /* Disable software break (enable outputs) */ + + pulsecount_moe_enable(dev, true); + + /* Configure timer channels */ + + if (priv->channel.channel != 0) + { + pulsecount_channel_configure(dev, priv->channel.channel); + pulsecount_output_configure(priv, &priv->channel); + } + +errout: + return ret; +} + +/**************************************************************************** + * Name: pulsecount_timer + * + * Description: + * (Re-)initialize the timer resources and start the pulsed output + * + * Input Parameters: + * dev - A reference to the lower half pulsecount driver state structure + * info - A reference to the characteristics of the pulsed output + * + * Returned Value: + * Zero on success; a negated errno value on failure + * + * This split keeps pulsecount as the existing single-channel mode. + * + ****************************************************************************/ + +static int pulsecount_timer(struct pulsecount_lowerhalf_s *dev, + const struct pulsecount_info_s *info) +{ + struct stm32_tim_s *priv = (struct stm32_tim_s *)dev; + ub16_t duty = 0; + uint8_t channel = 0; + uint16_t outputs = 0; + int ret = OK; + + /* If we got here then the timer instance supports pulsecount output. */ + + DEBUGASSERT(priv != NULL && info != NULL); + + _info("TIM%u channel: %u high: %" PRIu32 " ns low: %" PRIu32 + " ns count: %" PRIu32 "\n", + priv->timid, priv->channel.channel, info->high_ns, + info->low_ns, info->count); + + DEBUGASSERT(pulsecount_frequency(info) > 0); + + /* Channel specific setup */ + + duty = pulsecount_duty(info); + channel = priv->channel.channel; + + /* Disable all interrupts and DMA requests, clear all pending status */ + + pulsecount_putreg(priv, STM32_GTIM_DIER_OFFSET, 0); + pulsecount_putreg(priv, STM32_GTIM_SR_OFFSET, 0); + + /* Set timer frequency */ + + ret = pulsecount_frequency_update(dev, pulsecount_frequency(info)); + if (ret < 0) + { + goto errout; + } + + /* Update duty cycle */ + + ret = pulsecount_duty_update(dev, channel, duty); + if (ret < 0) + { + goto errout; + } + + /* If a non-zero repetition count has been selected, then set the + * repetition counter to the count-1 (pulsecount_start() has already + * assured us that the count value is within range). + */ + + if (info->count > 0) + { + /* Save the remaining count and the number of counts that will have + * elapsed on the first interrupt. + */ + + /* If the first interrupt occurs at the end end of the first + * repetition count, then the count will be the same as the RCR + * value. + */ + + priv->prev = pulsecount_count(info->count); + pulsecount_putreg(priv, STM32_ATIM_RCR_OFFSET, priv->prev - 1); + + /* Generate an update event to reload the prescaler. This should + * preload the RCR into active repetition counter. + */ + + pulsecount_putreg(priv, STM32_GTIM_EGR_OFFSET, GTIM_EGR_UG); + + /* Now set the value of the RCR that will be loaded on the next + * update event. + */ + + priv->count = info->count; + priv->curr = pulsecount_count(info->count - priv->prev); + pulsecount_putreg(priv, STM32_ATIM_RCR_OFFSET, priv->curr - 1); + } + + /* Otherwise, just clear the repetition counter */ + + else + { + /* Set the repetition counter to zero */ + + pulsecount_putreg(priv, STM32_ATIM_RCR_OFFSET, 0); + + /* Generate an update event to reload the prescaler */ + + pulsecount_putreg(priv, STM32_GTIM_EGR_OFFSET, GTIM_EGR_UG); + } + + /* Get configured outputs */ + + outputs = pulsecount_outputs_from_channels(priv, channel); + + /* Enable output */ + + ret = pulsecount_outputs_enable(dev, outputs, true); + if (ret < 0) + { + goto errout; + } + + /* Setup update interrupt. If info->count is > 0, then we can + * be assured that pulsecount_start() has already verified: (1) that + * this is an advanced timer, and that (2) the repetition count is within + * range. + */ + + if (info->count > 0) + { + /* Clear all pending interrupts and enable the update interrupt. */ + + pulsecount_putreg(priv, STM32_GTIM_SR_OFFSET, 0); + pulsecount_putreg(priv, STM32_GTIM_DIER_OFFSET, GTIM_DIER_UIE); + + /* Enable the timer */ + + pulsecount_modifyreg(priv, STM32_GTIM_CR1_OFFSET, 0, GTIM_CR1_CEN); + + /* And enable timer interrupts at the NVIC */ + + up_enable_irq(priv->irq); + } + + pulsecount_dumpregs(dev, "After starting"); + +errout: + return ret; +} + +/**************************************************************************** + * Name: pulsecount_interrupt + * + * Description: + * Handle timer interrupts. + * + * Input Parameters: + * dev - A reference to the lower half pulsecount driver state structure + * + * Returned Value: + * Zero on success; a negated errno value on failure + * + ****************************************************************************/ + +static int pulsecount_interrupt(struct pulsecount_lowerhalf_s *dev) +{ + struct stm32_tim_s *priv = (struct stm32_tim_s *)dev; + uint16_t regval; + + /* Verify that this is an update interrupt. Nothing else is expected. */ + + regval = pulsecount_getreg(priv, STM32_ATIM_SR_OFFSET); + DEBUGASSERT((regval & ATIM_SR_UIF) != 0); + + /* Clear the UIF interrupt bit */ + + pulsecount_putreg(priv, STM32_ATIM_SR_OFFSET, (regval & ~ATIM_SR_UIF)); + + /* Calculate the new count by subtracting the number of pulses + * since the last interrupt. + */ + + if (priv->count <= priv->prev) + { + /* We are finished. Turn off the master output to stop the output as + * quickly as possible. + */ + + pulsecount_moe_enable(dev, false); + + /* Disable first interrupts, stop and reset the timer */ + + pulsecount_ll_stop(dev); + + /* Then perform the callback into the upper half driver */ + + pulsecount_expired(priv->handle); + + priv->handle = NULL; + priv->count = 0; + priv->prev = 0; + priv->curr = 0; + } + else + { + /* Decrement the count of pulses remaining using the number of + * pulses generated since the last interrupt. + */ + + priv->count -= priv->prev; + + /* Set up the next RCR. Set 'prev' to the value of the RCR that + * was loaded when the update occurred (just before this interrupt) + * and set 'curr' to the current value of the RCR register (which + * will bet loaded on the next update event). + */ + + priv->prev = priv->curr; + priv->curr = pulsecount_count(priv->count - priv->prev); + pulsecount_putreg(priv, STM32_ATIM_RCR_OFFSET, priv->curr - 1); + } + + /* Now all of the time critical stuff is done so we can do some debug + * output. + */ + + _info("Update interrupt SR: %04" PRIx16 " prev: %u curr: %u" + " count: %" PRIu32 "\n", + regval, (unsigned int)priv->prev, (unsigned int)priv->curr, + priv->count); + + return OK; +} + +/**************************************************************************** + * Name: pulsecount_tim1/8interrupt + * + * Description: + * Handle timer 1 and 8 interrupts. + * + * Input Parameters: + * Standard NuttX interrupt inputs + * + * Returned Value: + * Zero on success; a negated errno value on failure + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_TIM1_PULSECOUNT +static int pulsecount_tim1interrupt(int irq, void *context, void *arg) +{ + return pulsecount_interrupt((struct pulsecount_lowerhalf_s *) + &g_pulsecount1dev); +} +#endif /* CONFIG_STM32_TIM1_PULSECOUNT */ + +#ifdef CONFIG_STM32_TIM8_PULSECOUNT +static int pulsecount_tim8interrupt(int irq, void *context, void *arg) +{ + return pulsecount_interrupt((struct pulsecount_lowerhalf_s *) + &g_pulsecount8dev); +} +#endif /* CONFIG_STM32_TIM8_PULSECOUNT */ + +/**************************************************************************** + * Name: pulsecount_count + * + * Description: + * Pick an optimal pulse count to program the RCR. + * + * Input Parameters: + * count - The total count remaining + * + * Returned Value: + * The recommended pulse count + * + ****************************************************************************/ + +static uint8_t pulsecount_count(uint32_t count) +{ + /* Use the advanced-timer repetition counter limit. */ + + /* The the remaining pulse count is less than or equal to the maximum, the + * just return the count. + */ + + if (count <= ATIM_RCR_REP_MAX) + { + return (uint8_t)count; + } + + /* Otherwise, we have to be careful. We do not want a small number of + * counts at the end because we might have trouble responding fast enough. + * If the remaining count is less than 150% of the maximum, then return + * half of the maximum. In this case the final sequence will be between 64 + * and 128. + */ + + else if (count < (3 * ATIM_RCR_REP_MAX / 2)) + { + return (uint8_t)((ATIM_RCR_REP_MAX + 1) >> 1); + } + + /* Otherwise, return the maximum. The final count will be 64 or more */ + + else + { + return (uint8_t)ATIM_RCR_REP_MAX; + } +} + +/**************************************************************************** + * Name: pulsecount_set_apb_clock + * + * Description: + * Enable or disable APB clock for the timer peripheral + * + * Input Parameters: + * priv - A reference to the pulsecount block status + * on - Enable clock if 'on' is 'true' and disable if 'false' + * + ****************************************************************************/ + +static int pulsecount_set_apb_clock(struct stm32_tim_s *priv, bool on) +{ + uint32_t en_bit = 0; + uint32_t regaddr = 0; + int ret = OK; + + _info("timer %d clock enable: %d\n", priv->timid, on ? 1 : 0); + + /* Determine which timer to configure */ + + switch (priv->timid) + { +#ifdef CONFIG_STM32_TIM1_PULSECOUNT + case 1: + { + regaddr = TIMRCCEN_TIM1; + en_bit = TIMEN_TIM1; + break; + } +#endif + +#ifdef CONFIG_STM32_TIM8_PULSECOUNT + case 8: + { + regaddr = TIMRCCEN_TIM8; + en_bit = TIMEN_TIM8; + break; + } +#endif + + default: + { + _err("ERROR: No such timer configured %d\n", priv->timid); + ret = -EINVAL; + goto errout; + } + } + + /* Enable/disable APB 1/2 clock for timer */ + + _info("RCC_APBxENR base: %08" PRIx32 " bits: %04" PRIx32 "\n", + regaddr, en_bit); + + if (on) + { + modifyreg32(regaddr, 0, en_bit); + } + else + { + modifyreg32(regaddr, en_bit, 0); + } + +errout: + return ret; +} + +/**************************************************************************** + * Name: pulsecount_ll_setup + * + * Description: + * This method is called when the driver is opened. The lower half driver + * should configure and initialize the device so that it is ready for use. + * It should not, however, output pulses until the start method is called. + * + * Input Parameters: + * dev - A reference to the lower half pulsecount driver state structure + * + * Returned Value: + * Zero on success; a negated errno value on failure + * + * Assumptions: + * APB1 or 2 clocking for the GPIOs has already been configured by the RCC + * logic at power up. + * + ****************************************************************************/ + +static int pulsecount_ll_setup(struct pulsecount_lowerhalf_s *dev) +{ + struct stm32_tim_s *priv = (struct stm32_tim_s *)dev; + uint32_t pincfg = 0; + int ret = OK; + + _info("TIM%u\n", priv->timid); + + /* Enable APB1/2 clocking for timer. */ + + ret = pulsecount_set_apb_clock(priv, true); + if (ret < 0) + { + goto errout; + } + + pulsecount_dumpregs(dev, "Initially"); + + /* Configure the pulsecount output pins, but do not start the timer yet */ + + if (priv->channel.out1.in_use == 1) + { + /* Do not configure the pin if pincfg is not specified. + * This prevents overwriting the PA0 configuration if the + * channel is used internally. + */ + + pincfg = priv->channel.out1.pincfg; + if (pincfg != 0) + { + _info("pincfg: %08" PRIx32 "\n", pincfg); + + stm32_configgpio(pincfg); + pulsecount_dumpgpio(pincfg, "pulsecount setup"); + } + } + +errout: + return ret; +} + +/**************************************************************************** + * Name: pulsecount_ll_shutdown + * + * Description: + * This method is called when the driver is closed. The lower half driver + * stop pulsed output, free any resources, disable the timer hardware, and + * put the system into the lowest possible power usage state + * + * Input Parameters: + * dev - A reference to the lower half pulsecount driver state structure + * + * Returned Value: + * Zero on success; a negated errno value on failure + * + ****************************************************************************/ + +static int pulsecount_ll_shutdown(struct pulsecount_lowerhalf_s *dev) +{ + struct stm32_tim_s *priv = (struct stm32_tim_s *)dev; + uint32_t pincfg = 0; + int ret = OK; + + _info("TIM%u\n", priv->timid); + + /* Make sure that the output has been stopped */ + + pulsecount_ll_stop(dev); + + /* Disable APB1/2 clocking for timer. */ + + ret = pulsecount_set_apb_clock(priv, false); + if (ret < 0) + { + goto errout; + } + + /* Then put the GPIO pins back to the default state */ + + pincfg = priv->channel.out1.pincfg; + if (pincfg != 0) + { + _info("pincfg: %08" PRIx32 "\n", pincfg); + + pincfg &= (GPIO_PORT_MASK | GPIO_PIN_MASK); + pincfg |= PINCFG_DEFAULT; + + stm32_configgpio(pincfg); + } + +errout: + return ret; +} + +/**************************************************************************** + * Name: pulsecount_ll_stop + * + * Description: + * Stop the pulsed output and reset the timer resources + * + * Input Parameters: + * dev - A reference to the lower half pulsecount driver state structure + * + * Returned Value: + * Zero on success; a negated errno value on failure + * + * Assumptions: + * This function is called to stop the pulsed output at anytime. This + * method is also called from the timer interrupt handler when a repetition + * count expires... automatically stopping the timer. + * + ****************************************************************************/ + +static int pulsecount_ll_stop(struct pulsecount_lowerhalf_s *dev) +{ + struct stm32_tim_s *priv = (struct stm32_tim_s *)dev; + irqstate_t flags = 0; + uint16_t outputs = 0; + int ret = OK; + + _info("TIM%u\n", priv->timid); + + /* Disable interrupts momentary to stop any ongoing timer processing and + * to prevent any concurrent access to the reset register. + */ + + flags = enter_critical_section(); + + /* Stopped so frequency is zero */ + + priv->frequency = 0; + + /* Disable further interrupts and stop the timer */ + + pulsecount_putreg(priv, STM32_GTIM_DIER_OFFSET, 0); + pulsecount_putreg(priv, STM32_GTIM_SR_OFFSET, 0); + + /* Disable the timer and timer outputs */ + + pulsecount_modifyreg(priv, STM32_GTIM_CR1_OFFSET, GTIM_CR1_CEN, 0); + outputs = pulsecount_outputs_from_channels(priv, 0); + ret = pulsecount_outputs_enable(dev, outputs, false); + + /* Clear all channels */ + + pulsecount_putreg(priv, STM32_GTIM_CCR1_OFFSET, 0); + pulsecount_putreg(priv, STM32_GTIM_CCR2_OFFSET, 0); + pulsecount_putreg(priv, STM32_GTIM_CCR3_OFFSET, 0); + pulsecount_putreg(priv, STM32_GTIM_CCR4_OFFSET, 0); + + leave_critical_section(flags); + + pulsecount_dumpregs(dev, "After stop"); + + return ret; +} + +/**************************************************************************** + * Name: pulsecount_ll_ioctl + * + * Description: + * Lower-half logic may support platform-specific ioctl commands + * + * Input Parameters: + * dev - A reference to the lower half pulsecount driver state structure + * cmd - The ioctl command + * arg - The argument accompanying the ioctl command + * + * Returned Value: + * Zero on success; a negated errno value on failure + * + ****************************************************************************/ + +static int pulsecount_ll_ioctl(struct pulsecount_lowerhalf_s *dev, int cmd, + unsigned long arg) +{ +#ifdef CONFIG_DEBUG_TIMER_INFO + struct stm32_tim_s *priv = (struct stm32_tim_s *)dev; + + /* There are no platform-specific ioctl commands */ + + _info("TIM%u\n", priv->timid); +#endif + return -ENOTTY; +} + +static int pulsecount_setup(struct pulsecount_lowerhalf_s *dev) +{ + struct stm32_pulsecount_s *pulse = (struct stm32_pulsecount_s *)dev; + int ret; + + ret = pulsecount_ll_setup((struct pulsecount_lowerhalf_s *)pulse->timer); + if (ret < 0) + { + return ret; + } + + return pulsecount_configure((struct pulsecount_lowerhalf_s *)pulse->timer); +} + +static int pulsecount_shutdown(struct pulsecount_lowerhalf_s *dev) +{ + struct stm32_pulsecount_s *pulse = (struct stm32_pulsecount_s *)dev; + return pulsecount_ll_shutdown((struct pulsecount_lowerhalf_s *) + pulse->timer); +} + +static int pulsecount_start(struct pulsecount_lowerhalf_s *dev, + const struct pulsecount_info_s *info, + void *handle) +{ + struct stm32_pulsecount_s *pulse = (struct stm32_pulsecount_s *)dev; + struct stm32_tim_s *priv = pulse->timer; + + /* Check if a pulsecount has been selected */ + + if (info->count > 0) + { + /* Only the advanced timers (TIM1,8 can support the pulse counting) + */ + + if (priv->timtype != TIMTYPE_ADVANCED) + { + _err("ERROR: TIM%u cannot support pulse count: %" PRIu32 "\n", + priv->timid, info->count); + return -EPERM; + } + } + + /* Save the handle */ + + priv->handle = handle; + + /* Start the time */ + + return pulsecount_timer((struct pulsecount_lowerhalf_s *)priv, info); +} + +static int pulsecount_stop(struct pulsecount_lowerhalf_s *dev) +{ + struct stm32_pulsecount_s *pulse = (struct stm32_pulsecount_s *)dev; + return pulsecount_ll_stop((struct pulsecount_lowerhalf_s *)pulse->timer); +} + +static int pulsecount_ioctl(struct pulsecount_lowerhalf_s *dev, + int cmd, unsigned long arg) +{ + struct stm32_pulsecount_s *pulse = (struct stm32_pulsecount_s *)dev; + return pulsecount_ll_ioctl((struct pulsecount_lowerhalf_s *)pulse->timer, + cmd, arg); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +struct pulsecount_lowerhalf_s *stm32_pulsecountinitialize(int timer) +{ + struct stm32_pulsecount_s *lower = NULL; + + _info("TIM%u\n", timer); + + switch (timer) + { +#ifdef CONFIG_STM32_TIM1_PULSECOUNT + case 1: + { + lower = &g_pulsecount1lower; + irq_attach(lower->timer->irq, pulsecount_tim1interrupt, NULL); + up_disable_irq(lower->timer->irq); + break; + } +#endif + +#ifdef CONFIG_STM32_TIM8_PULSECOUNT + case 8: + { + lower = &g_pulsecount8lower; + irq_attach(lower->timer->irq, pulsecount_tim8interrupt, NULL); + up_disable_irq(lower->timer->irq); + break; + } +#endif + + default: + { + _err("ERROR: TIM%d does not support pulse count\n", timer); + return NULL; + } + } + + return (struct pulsecount_lowerhalf_s *)lower; +} diff --git a/arch/arm/src/common/stm32/stm32_pwm.h b/arch/arm/src/common/stm32/stm32_pwm.h new file mode 100644 index 0000000000000..c2a9a90789744 --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_pwm.h @@ -0,0 +1,42 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_pwm.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_COMPAT_STM32_PWM_H +#define __ARCH_ARM_SRC_COMMON_COMPAT_STM32_PWM_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#if defined(CONFIG_STM32_HAVE_IP_TIMERS_M0_V1) +# include "stm32_pwm_m0_v1.h" +#elif defined(CONFIG_STM32_HAVE_IP_TIMERS_M3M4_V1) || \ + defined(CONFIG_STM32_HAVE_IP_TIMERS_M3M4_V2) || \ + defined(CONFIG_STM32_HAVE_IP_TIMERS_M3M4_V3) +# include "stm32_pwm_m3m4_v1v2v3.h" +#else +# error "Unsupported STM32 PWM" +#endif + +#endif /* __ARCH_ARM_SRC_COMMON_COMPAT_STM32_PWM_H */ diff --git a/arch/arm/src/common/stm32/stm32_pwm_m0_v1.c b/arch/arm/src/common/stm32/stm32_pwm_m0_v1.c new file mode 100644 index 0000000000000..cf7e6a3b23843 --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_pwm_m0_v1.c @@ -0,0 +1,1911 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_pwm_m0_v1.c + * + * SPDX-License-Identifier: BSD-3-Clause + * SPDX-FileCopyrightText: 2019 Fundação CERTI. All rights reserved. + * SPDX-FileContributor: Daniel Pereira Volpato + * SPDX-FileContributor: Guillherme da Silva Amaral + * SPDX-FileContributor: Gregory Nutt + * SPDX-FileContributor: Paul Alexander Patience + * SPDX-FileContributor: Mateusz Szafoni + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include + +#include +#include +#include + +#include "arm_internal.h" +#include "chip.h" +#include "stm32_gpio.h" +#include "stm32_pwm.h" +#include "stm32_rcc.h" + +/* This module then only compiles if there is at least one enabled timer + * intended for use with the PWM upper half driver. + */ + +#if defined(CONFIG_STM32_TIM1_PWM) || defined(CONFIG_STM32_TIM2_PWM) || \ + defined(CONFIG_STM32_TIM3_PWM) || defined(CONFIG_STM32_TIM14_PWM) || \ + defined(CONFIG_STM32_TIM15_PWM) || defined(CONFIG_STM32_TIM16_PWM) || \ + defined(CONFIG_STM32_TIM17_PWM) + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* PWM/Timer Definitions ****************************************************/ + +/* The following definitions are used to identify the various time types */ + +#define TIMTYPE_BASIC 0 /* Basic timers: TIM6,7 */ +#define TIMTYPE_GENERAL16 1 /* General 16-bit timers: TIM3 */ +#define TIMTYPE_COUNTUP16 2 /* General 16-bit count-up timers: TIM14 */ +#define TIMTYPE_GENERAL32 3 /* General 32-bit timers: TIM2 */ +#define TIMTYPE_ADVANCED 4 /* Advanced timers: TIM1 */ +#define TIMTYPE_COUNTUP16_N 5 /* General 16-bit count-up timers with + * one complementary output: TIM15-17 + */ + +#define TIMTYPE_TIM1 TIMTYPE_ADVANCED +#define TIMTYPE_TIM2 TIMTYPE_GENERAL32 +#define TIMTYPE_TIM3 TIMTYPE_GENERAL16 +#define TIMTYPE_TIM6 TIMTYPE_BASIC +#define TIMTYPE_TIM7 TIMTYPE_BASIC +#define TIMTYPE_TIM14 TIMTYPE_COUNTUP16 +#define TIMTYPE_TIM15 TIMTYPE_COUNTUP16_N /* Treated as ADVTIM */ +#define TIMTYPE_TIM16 TIMTYPE_COUNTUP16_N /* Treated as ADVTIM */ +#define TIMTYPE_TIM17 TIMTYPE_COUNTUP16_N /* Treated as ADVTIM */ + +/* Advanced timer */ + +#if defined (CONFIG_STM32_TIM1_PWM) +# define HAVE_IP_TIMERS_V2 1 +#endif + +#if defined(CONFIG_STM32_TIM1_PWM) || \ + defined(CONFIG_STM32_TIM8_PWM) || \ + defined(CONFIG_STM32_TIM15_PWM) || \ + defined(CONFIG_STM32_TIM16_PWM) || \ + defined(CONFIG_STM32_TIM17_PWM) +# define HAVE_ADVTIM +#else +# undef HAVE_ADVTIM +#endif + +/* CCMR2 */ + +#if defined(CONFIG_STM32_TIM1_PWM) || \ + defined(CONFIG_STM32_TIM3_PWM) +# define HAVE_CCMR2 +#else +# undef HAVE_CCMR2 +#endif + +/* Debug ********************************************************************/ + +#ifdef CONFIG_DEBUG_PWM_INFO +# define pwm_dumpgpio(p,m) +# warning "pwm_dumpgpio not implemented" +#else +# define pwm_dumpgpio(p,m) +#endif + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +enum stm32_timmode_e +{ + STM32_TIMMODE_COUNTUP = 0, + STM32_TIMMODE_COUNTDOWN = 1, + STM32_TIMMODE_CENTER1 = 2, + STM32_TIMMODE_CENTER2 = 3, + STM32_TIMMODE_CENTER3 = 4, +}; + +enum stm32_chanmode_e +{ + STM32_CHANMODE_PWM1 = 0, + STM32_CHANMODE_PWM2 = 1, + STM32_CHANMODE_COMBINED1 = 2, + STM32_CHANMODE_COMBINED2 = 3, + STM32_CHANMODE_ASYMMETRIC1 = 4, + STM32_CHANMODE_ASYMMETRIC2 = 5, +}; + +struct stm32_pwmchan_s +{ + uint8_t channel; /* Timer output channel: {1,..4} */ + enum stm32_chanmode_e mode; + uint32_t pincfg; /* Output pin configuration */ + uint32_t npincfg; /* Complementary output pin configuration + * (only TIM1,8 CH1-3 and TIM15,16,17 CH1) + */ +}; + +/* This structure represents the state of one PWM timer */ + +struct stm32_pwmtimer_s +{ + const struct pwm_ops_s *ops; /* PWM operations */ + struct stm32_pwmchan_s channels[PWM_NCHANNELS]; + uint8_t timid; /* Timer ID {1,...,17} */ + uint8_t timtype; /* See the TIMTYPE_* definitions */ + enum stm32_timmode_e mode; + uint32_t frequency; /* Current frequency setting */ + uint32_t base; /* The base address of the timer */ + uint32_t pclk; /* The frequency of the peripheral clock + * that drives the timer module. */ +}; + +/**************************************************************************** + * Static Function Prototypes + ****************************************************************************/ + +/* Register access */ + +static uint32_t stm32pwm_getreg(struct stm32_pwmtimer_s *priv, int offset); +static void stm32pwm_putreg(struct stm32_pwmtimer_s *priv, int offset, + uint32_t value); +static void stm32pwm_modifyreg(struct stm32_pwmtimer_s *priv, + uint32_t offset, uint32_t clearbits, + uint32_t setbits); + +#ifdef CONFIG_DEBUG_PWM_INFO +static void stm32pwm_dumpregs(struct stm32_pwmtimer_s *priv, + const char *msg); +#else +# define stm32pwm_dumpregs(priv,msg) +#endif + +/* Timer management */ + +static int stm32pwm_timer(struct stm32_pwmtimer_s *priv, + const struct pwm_info_s *info); +static int stm32pwm_output_configure(struct stm32_pwmtimer_s *priv, + uint8_t channel); +static int stm32pwm_update_duty(struct stm32_pwmtimer_s *priv, + uint8_t channel, ub16_t duty); +static void stm32pwm_setapbclock(struct stm32_pwmtimer_s *priv, bool on); + +/* PWM driver methods */ + +static int stm32pwm_setup(struct pwm_lowerhalf_s *dev); +static int stm32pwm_shutdown(struct pwm_lowerhalf_s *dev); + +static int stm32pwm_start(struct pwm_lowerhalf_s *dev, + const struct pwm_info_s *info); + +static int stm32pwm_stop(struct pwm_lowerhalf_s *dev); +static int stm32pwm_ioctl(struct pwm_lowerhalf_s *dev, + int cmd, unsigned long arg); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* This is the list of lower half PWM driver methods used by the upper half + * driver + */ + +static const struct pwm_ops_s g_pwmops = +{ + .setup = stm32pwm_setup, + .shutdown = stm32pwm_shutdown, + .start = stm32pwm_start, + .stop = stm32pwm_stop, + .ioctl = stm32pwm_ioctl, +}; + +#ifdef CONFIG_STM32_TIM1_PWM +static struct stm32_pwmtimer_s g_pwm1dev = +{ + .ops = &g_pwmops, + .timid = 1, + .channels = + { +#ifdef CONFIG_STM32_TIM1_CHANNEL1 + { + .channel = 1, + .pincfg = PWM_TIM1_CH1CFG, + .mode = CONFIG_STM32_TIM1_CH1MODE, + .npincfg = PWM_TIM1_CH1NCFG, + }, +#endif +#ifdef CONFIG_STM32_TIM1_CHANNEL2 + { + .channel = 2, + .pincfg = PWM_TIM1_CH2CFG, + .mode = CONFIG_STM32_TIM1_CH2MODE, + .npincfg = PWM_TIM1_CH2NCFG, + }, +#endif +#ifdef CONFIG_STM32_TIM1_CHANNEL3 + { + .channel = 3, + .pincfg = PWM_TIM1_CH3CFG, + .mode = CONFIG_STM32_TIM1_CH3MODE, + .npincfg = PWM_TIM1_CH3NCFG, + }, +#endif +#ifdef CONFIG_STM32_TIM1_CHANNEL4 + { + .channel = 4, + .pincfg = PWM_TIM1_CH4CFG, + .mode = CONFIG_STM32_TIM1_CH4MODE, + .npincfg = 0, + }, +#endif + }, + .timtype = TIMTYPE_TIM1, + .mode = CONFIG_STM32_TIM1_MODE, + .base = STM32_TIM1_BASE, + .pclk = STM32_APB2_TIM1_CLKIN, +}; +#endif + +#ifdef CONFIG_STM32_TIM2_PWM +static struct stm32_pwmtimer_s g_pwm2dev = +{ + .ops = &g_pwmops, + .timid = 2, + .channels = + { +#ifdef CONFIG_STM32_TIM2_CHANNEL1 + { + .channel = 1, + .pincfg = PWM_TIM2_CH1CFG, + .mode = CONFIG_STM32_TIM2_CH1MODE, + .npincfg = 0, + }, +#endif +#ifdef CONFIG_STM32_TIM2_CHANNEL2 + { + .channel = 2, + .pincfg = PWM_TIM2_CH2CFG, + .mode = CONFIG_STM32_TIM2_CH2MODE, + .npincfg = 0, + }, +#endif +#ifdef CONFIG_STM32_TIM2_CHANNEL3 + { + .channel = 3, + .pincfg = PWM_TIM2_CH3CFG, + .mode = CONFIG_STM32_TIM2_CH3MODE, + .npincfg = 0, + }, +#endif +#ifdef CONFIG_STM32_TIM2_CHANNEL4 + { + .channel = 4, + .pincfg = PWM_TIM2_CH4CFG, + .mode = CONFIG_STM32_TIM2_CH4MODE, + .npincfg = 0, + }, +#endif + }, + .timtype = TIMTYPE_TIM2, + .mode = CONFIG_STM32_TIM2_MODE, + .base = STM32_TIM2_BASE, + .pclk = STM32_APB1_TIM2_CLKIN, +}; +#endif + +#ifdef CONFIG_STM32_TIM3_PWM +static struct stm32_pwmtimer_s g_pwm3dev = +{ + .ops = &g_pwmops, + .timid = 3, + .channels = + { +#ifdef CONFIG_STM32_TIM3_CHANNEL1 + { + .channel = 1, + .pincfg = PWM_TIM3_CH1CFG, + .mode = CONFIG_STM32_TIM3_CH1MODE, + .npincfg = 0, + }, +#endif +#ifdef CONFIG_STM32_TIM3_CHANNEL2 + { + .channel = 2, + .pincfg = PWM_TIM3_CH2CFG, + .mode = CONFIG_STM32_TIM3_CH2MODE, + .npincfg = 0, + }, +#endif +#ifdef CONFIG_STM32_TIM3_CHANNEL3 + { + .channel = 3, + .pincfg = PWM_TIM3_CH3CFG, + .mode = CONFIG_STM32_TIM3_CH3MODE, + .npincfg = 0, + }, +#endif +#ifdef CONFIG_STM32_TIM3_CHANNEL4 + { + .channel = 4, + .pincfg = PWM_TIM3_CH4CFG, + .mode = CONFIG_STM32_TIM3_CH4MODE, + .npincfg = 0, + }, +#endif + }, + .timtype = TIMTYPE_TIM3, + .mode = CONFIG_STM32_TIM3_MODE, + .base = STM32_TIM3_BASE, + .pclk = STM32_APB1_TIM3_CLKIN, +}; +#endif + +#ifdef CONFIG_STM32_TIM14_PWM +static struct stm32_pwmtimer_s g_pwm14dev = +{ + .ops = &g_pwmops, + .timid = 14, + .channels = + { +#ifdef CONFIG_STM32_TIM14_CHANNEL1 + { + .channel = 1, + .pincfg = PWM_TIM14_CH1CFG, + .mode = CONFIG_STM32_TIM14_CH1MODE, + .npincfg = PWM_TIM14_CH1NCFG, + }, +#endif + }, + .timtype = TIMTYPE_TIM14, + .mode = STM32_TIMMODE_COUNTUP, + .base = STM32_TIM14_BASE, + .pclk = STM32_APB2_TIM14_CLKIN, +}; +#endif + +#ifdef CONFIG_STM32_TIM15_PWM +static struct stm32_pwmtimer_s g_pwm15dev = +{ + .ops = &g_pwmops, + .timid = 15, + .channels = + { +#ifdef CONFIG_STM32_TIM15_CHANNEL1 + { + .channel = 1, + .pincfg = PWM_TIM15_CH1CFG, + .mode = CONFIG_STM32_TIM15_CH1MODE, + .npincfg = PWM_TIM15_CH1NCFG, + }, +#endif +#ifdef CONFIG_STM32_TIM15_CHANNEL2 + { + .channel = 2, + .pincfg = PWM_TIM15_CH2CFG, + .mode = CONFIG_STM32_TIM15_CH2MODE, + .npincfg = 0, + }, +#endif + }, + .timtype = TIMTYPE_TIM15, + .mode = STM32_TIMMODE_COUNTUP, + .base = STM32_TIM15_BASE, + .pclk = STM32_APB2_TIM15_CLKIN, +}; +#endif + +#ifdef CONFIG_STM32_TIM16_PWM +static struct stm32_pwmtimer_s g_pwm16dev = +{ + .ops = &g_pwmops, + .timid = 16, + .channels = + { +#ifdef CONFIG_STM32_TIM16_CHANNEL1 + { + .channel = 1, + .pincfg = PWM_TIM16_CH1CFG, + .mode = CONFIG_STM32_TIM16_CH1MODE, + .npincfg = PWM_TIM16_CH1NCFG, + }, +#endif + }, + .timtype = TIMTYPE_TIM16, + .mode = STM32_TIMMODE_COUNTUP, + .base = STM32_TIM16_BASE, + .pclk = STM32_APB2_TIM16_CLKIN, +}; +#endif + +#ifdef CONFIG_STM32_TIM17_PWM +static struct stm32_pwmtimer_s g_pwm17dev = +{ + .ops = &g_pwmops, + .timid = 17, + .channels = + { +#ifdef CONFIG_STM32_TIM17_CHANNEL1 + { + .channel = 1, + .pincfg = PWM_TIM17_CH1CFG, + .mode = CONFIG_STM32_TIM17_CH1MODE, + .npincfg = PWM_TIM17_CH1NCFG, + }, +#endif + }, + .timtype = TIMTYPE_TIM17, + .mode = STM32_TIMMODE_COUNTUP, + .base = STM32_TIM17_BASE, + .pclk = STM32_APB2_TIM17_CLKIN, +}; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32pwm_reg_is_32bit + * + * Description: + * Verify whether the timer register is 32bit or not. + * + * Input Parameters: + * timtype - The type of the timer. See the TIMTYPE_* definitions + * offset - The offset to the register to read + * + * Returned Value: + * Return true for 32 bits register; false otherwise. + * + ****************************************************************************/ + +static bool stm32pwm_reg_is_32bit(uint8_t timtype, uint32_t offset) +{ + if (offset == STM32_GTIM_CCMR1_OFFSET || + offset == STM32_GTIM_SMCR_OFFSET || + offset == STM32_GTIM_BDTR_OFFSET) + { + return true; + } + + if (timtype == TIMTYPE_GENERAL16) + { + if (offset == STM32_GTIM_CCMR2_OFFSET || + offset == STM32_GTIM_AF1_OFFSET || + offset == STM32_GTIM_TISEL_OFFSET) + { + return true; + } + } + else if (timtype == TIMTYPE_GENERAL32) + { + if (offset == STM32_GTIM_CNT_OFFSET || + offset == STM32_GTIM_ARR_OFFSET || + offset == STM32_GTIM_CCR1_OFFSET || + offset == STM32_GTIM_CCR2_OFFSET || + offset == STM32_GTIM_CCR3_OFFSET || + offset == STM32_GTIM_CCR4_OFFSET) + { + return true; + } + } + else if (timtype == TIMTYPE_ADVANCED) + { + if (offset == STM32_ATIM_CR2_OFFSET || + offset == STM32_ATIM_CCMR2_OFFSET || + offset == STM32_ATIM_CCER_OFFSET || + offset == STM32_ATIM_DMAR_OFFSET || + offset == STM32_ATIM_CCMR3_OFFSET || + offset == STM32_ATIM_CCR5_OFFSET || + offset == STM32_ATIM_AF1_OFFSET || + offset == STM32_ATIM_TISEL_OFFSET) + { + return true; + } + } + + return false; +} + +/**************************************************************************** + * Name: stm32pwm_getreg + * + * Description: + * Read the value of an PWM timer register + * + * Input Parameters: + * priv - A reference to the PWM block status + * offset - The offset to the register to read + * + * Returned Value: + * The current contents of the specified register + * + ****************************************************************************/ + +static uint32_t stm32pwm_getreg(struct stm32_pwmtimer_s *priv, int offset) +{ + uint32_t retval; + + if (stm32pwm_reg_is_32bit(priv->timtype, offset) == true) + { + /* 32-bit register */ + + retval = getreg32(priv->base + offset); + } + else + { + /* 16-bit register */ + + retval = getreg16(priv->base + offset); + } + + /* Return 32-bit value */ + + return retval; +} + +/**************************************************************************** + * Name: stm32pwm_putreg + * + * Description: + * Read the value of an PWM timer register + * + * Input Parameters: + * priv - A reference to the PWM block status + * offset - The offset to the register to read + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void stm32pwm_putreg(struct stm32_pwmtimer_s *priv, int offset, + uint32_t value) +{ + if (stm32pwm_reg_is_32bit(priv->timtype, offset) == true) + { + /* 32-bit register */ + + putreg32(value, priv->base + offset); + } + else + { + /* 16-bit register */ + + putreg16((uint16_t)value, priv->base + offset); + } +} + +/**************************************************************************** + * Name: stm32pwm_modifyreg + * + * Description: + * Modify PWM register (32-bit or 16-bit) + * + * Input Parameters: + * priv - A reference to the PWM block status + * offset - The offset to the register to read + * clrbits - The bits to clear + * setbits - The bits to set + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void stm32pwm_modifyreg(struct stm32_pwmtimer_s *priv, + uint32_t offset, uint32_t clearbits, + uint32_t setbits) +{ + if (stm32pwm_reg_is_32bit(priv->timtype, offset) == true) + { + /* 32-bit register */ + + modifyreg32(priv->base + offset, clearbits, setbits); + } + else + { + /* 16-bit register */ + + modifyreg16(priv->base + offset, clearbits, setbits); + } +} + +/**************************************************************************** + * Name: stm32pwm_dumpregs + * + * Description: + * Dump all timer registers. + * + * Input Parameters: + * priv - A reference to the PWM block status + * msg - A message to be printed on the screen + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_DEBUG_PWM_INFO +static void stm32pwm_dumpregs(struct stm32_pwmtimer_s *priv, + const char *msg) +{ + pwminfo("%s:\n", msg); + pwminfo(" CR1: %04x CR2: %04x SMCR: %04x DIER: %04x\n", + stm32pwm_getreg(priv, STM32_GTIM_CR1_OFFSET), + stm32pwm_getreg(priv, STM32_GTIM_CR2_OFFSET), + stm32pwm_getreg(priv, STM32_GTIM_SMCR_OFFSET), + stm32pwm_getreg(priv, STM32_GTIM_DIER_OFFSET)); + pwminfo(" SR: %04x EGR: %04x CCMR1: %04x CCMR2: %04x\n", + stm32pwm_getreg(priv, STM32_GTIM_SR_OFFSET), + stm32pwm_getreg(priv, STM32_GTIM_EGR_OFFSET), + stm32pwm_getreg(priv, STM32_GTIM_CCMR1_OFFSET), + stm32pwm_getreg(priv, STM32_GTIM_CCMR2_OFFSET)); + pwminfo(" CCER: %04x CNT: %04x PSC: %04x ARR: %04x\n", + stm32pwm_getreg(priv, STM32_GTIM_CCER_OFFSET), + stm32pwm_getreg(priv, STM32_GTIM_CNT_OFFSET), + stm32pwm_getreg(priv, STM32_GTIM_PSC_OFFSET), + stm32pwm_getreg(priv, STM32_GTIM_ARR_OFFSET)); + pwminfo(" CCR1: %04x CCR2: %04x CCR3: %04x CCR4: %04x\n", + stm32pwm_getreg(priv, STM32_GTIM_CCR1_OFFSET), + stm32pwm_getreg(priv, STM32_GTIM_CCR2_OFFSET), + stm32pwm_getreg(priv, STM32_GTIM_CCR3_OFFSET), + stm32pwm_getreg(priv, STM32_GTIM_CCR4_OFFSET)); +#if defined(CONFIG_STM32_TIM1_PWM) || defined(CONFIG_STM32_TIM8_PWM) + if (priv->timtype == TIMTYPE_ADVANCED) + { + pwminfo(" RCR: %04x BDTR: %04x DCR: %04x DMAR: %04x\n", + stm32pwm_getreg(priv, STM32_ATIM_RCR_OFFSET), + stm32pwm_getreg(priv, STM32_ATIM_BDTR_OFFSET), + stm32pwm_getreg(priv, STM32_ATIM_DCR_OFFSET), + stm32pwm_getreg(priv, STM32_ATIM_DMAR_OFFSET)); + + pwminfo(" AF1: %04x TISEL: %04x\n", + stm32pwm_getreg(priv, STM32_ATIM_AF1_OFFSET), + stm32pwm_getreg(priv, STM32_ATIM_TISEL_OFFSET)); + } + else +#endif + { + pwminfo(" RCR: %04x BDTR: %04x DCR: %04x DMAR: %04x\n", + stm32pwm_getreg(priv, STM32_GTIM_RCR_OFFSET), + stm32pwm_getreg(priv, STM32_GTIM_BDTR_OFFSET), + stm32pwm_getreg(priv, STM32_GTIM_DCR_OFFSET), + stm32pwm_getreg(priv, STM32_GTIM_DMAR_OFFSET)); + pwminfo(" AF1: %04x TISEL: %04x\n", + stm32pwm_getreg(priv, STM32_GTIM_AF1_OFFSET), + stm32pwm_getreg(priv, STM32_GTIM_TISEL_OFFSET)); + } +} +#endif + +/**************************************************************************** + * Name: stm32pwm_output_configure + * + * Description: + * Configure PWM output for given channel + * + * Input Parameters: + * priv - A reference to the PWM block status + * channel - Timer output channel + * + * Returned Value: + * Zero on success; + ****************************************************************************/ + +static int stm32pwm_output_configure(struct stm32_pwmtimer_s *priv, + uint8_t channel) +{ + uint32_t cr2; + uint32_t ccer; + + /* Get current registers state */ + + cr2 = stm32pwm_getreg(priv, STM32_GTIM_CR2_OFFSET); + ccer = stm32pwm_getreg(priv, STM32_GTIM_CCER_OFFSET); + + /* Reset the output polarity level of all channels (selects high + * polarity) + */ + + ccer &= ~(GTIM_CCER_CC1P << ((channel - 1) * 4)); + + /* Enable the output state of the selected channels */ + + ccer |= (GTIM_CCER_CC1E << ((channel - 1) * 4)); + +#ifdef HAVE_ADVTIM + if (priv->timtype == TIMTYPE_ADVANCED || + priv->timtype == TIMTYPE_COUNTUP16_N) + { + cr2 &= ~(ATIM_CR2_OIS1 << ((channel - 1) * 2)); + } +#ifdef HAVE_PWM_COMPLEMENTARY + + /* Verify if the current complementary channel is defined */ + + if (priv->channels[channel - 1].npincfg != 0) + { + /* Configure complementary output IDLE state */ + + cr2 &= ~(ATIM_CR2_OIS1N << ((channel - 1) * 2)); + + /* Enable the complementary output state of the selected channels */ + + ccer |= (ATIM_CCER_CC1NE << ((channel - 1) * 4)); + + /* Configure complementary output polarity */ + + ccer &= ~(ATIM_CCER_CC1NP << ((channel - 1) * 4)); + } +#endif /* HAVE_PWM_COMPLEMENTARY */ +#endif /* HAVE_ADVTIM */ + + stm32pwm_modifyreg(priv, STM32_GTIM_CR2_OFFSET, 0, cr2); + stm32pwm_modifyreg(priv, STM32_GTIM_CCER_OFFSET, 0, ccer); + + return OK; +} + +/**************************************************************************** + * Name: stm32pwm_timer + * + * Description: + * (Re-)initialize the timer resources and start the pulsed output + * + * Input Parameters: + * priv - A reference to the lower half PWM driver state structure + * info - A reference to the characteristics of the pulsed output + * + * Returned Value: + * Zero on success; a negated errno value on failure + * + ****************************************************************************/ + +static int stm32pwm_timer(struct stm32_pwmtimer_s *priv, + const struct pwm_info_s *info) +{ + int i; + + /* Calculated values */ + + uint32_t prescaler; + uint32_t timclk; + uint32_t reload; + uint32_t ccr; + + /* Register contents */ + + uint32_t cr1; + uint32_t ccmr1; +#if defined(HAVE_CCMR2) + uint32_t ccmr2; + uint32_t ocmode2; +#endif + + /* New timer register bit settings */ + + uint32_t ocmode1; + + DEBUGASSERT(priv != NULL && info != NULL); + + ccmr1 = stm32pwm_getreg(priv, STM32_GTIM_CCMR1_OFFSET); + +#if defined(HAVE_CCMR2) + ccmr2 = stm32pwm_getreg(priv, STM32_GTIM_CCMR2_OFFSET); +#endif + + pwminfo("TIM%u frequency: %" PRIu32 "\n", + priv->timid, info->frequency); + + DEBUGASSERT(info->frequency > 0); + + /* Disable all interrupts and DMA requests, clear all pending status */ + + /* Calculate optimal values for the timer prescaler and for the timer + * reload register. If 'frequency' is the desired frequency, then + * + * reload = timclk / frequency + * timclk = pclk / presc + * + * Or, + * + * reload = pclk / presc / frequency + * + * There are many solutions to this, but the best solution will be the + * one that has the largest reload value and the smallest prescaler value. + * That is the solution that should give us the most accuracy in the timer + * control. Subject to: + * + * 0 <= presc <= 65536 + * 1 <= reload <= 65535 + * + * So presc = pclk / 65535 / frequency would be optimal. + * + * Example: + * + * pclk = 42 MHz + * frequency = 100 Hz + * + * prescaler = 42,000,000 / 65,535 / 100 + * = 6.4 (or 7 -- taking the ceiling always) + * timclk = 42,000,000 / 7 + * = 6,000,000 + * reload = 6,000,000 / 100 + * = 60,000 + */ + + prescaler = (priv->pclk / info->frequency + 65534) / 65535; + if (prescaler < 1) + { + prescaler = 1; + } + else if (prescaler > 65536) + { + prescaler = 65536; + } + + timclk = priv->pclk / prescaler; + + reload = timclk / info->frequency; + + /* In center-aligned mode, the timer performs upcounting from zero to ARR + * value and then performs downcounting from ARR to zero and repeat. In + * other words, in one cycle the timer counts 2*ARR. For that reason, the + * reload (ARR) value is divided by 2. + */ + + if (priv->mode == STM32_TIMMODE_CENTER1 || + priv->mode == STM32_TIMMODE_CENTER2 || + priv->mode == STM32_TIMMODE_CENTER3) + { + reload /= 2; + } + + if (reload < 2) + { + reload = 1; + } + else if (reload > 65535) + { + reload = 65535; + } + else + { + reload--; + } + + pwminfo("TIM%u PCLK: %" PRIu32 " frequency: %" PRIu32 " " + "TIMCLK: %" PRIu32 " prescaler: %" PRIu32 + " reload: %" PRIu32 "\n", + priv->timid, priv->pclk, info->frequency, timclk, + prescaler, reload); + + /* Set up the timer CR1 register: + * + * 1,8 CKD[1:0] ARPE CMS[1:0] DIR OPM URS UDIS CEN + * 2-5 CKD[1:0] ARPE CMS DIR OPM URS UDIS CEN + * 6-7 ARPE OPM URS UDIS CEN + * 9-14 CKD[1:0] ARPE URS UDIS CEN + * 15-17 CKD[1:0] ARPE OPM URS UDIS CEN + */ + + cr1 = stm32pwm_getreg(priv, STM32_GTIM_CR1_OFFSET); + + /* Disable the timer until we get it configured */ + + cr1 &= ~GTIM_CR1_CEN; + + /* Set the counter mode for the advanced timers (1,8) and most general + * purpose timers (all 2-5, but not 9-17), i.e., all but TIMTYPE_COUNTUP16 + * and TIMTYPE_BASIC + */ + +#if defined(CONFIG_STM32_TIM1_PWM) || defined(CONFIG_STM32_TIM2_PWM) || \ + defined(CONFIG_STM32_TIM3_PWM) || defined(CONFIG_STM32_TIM4_PWM) || \ + defined(CONFIG_STM32_TIM5_PWM) || defined(CONFIG_STM32_TIM8_PWM) + + if (priv->timtype != TIMTYPE_BASIC && priv->timtype != TIMTYPE_COUNTUP16 && + priv->timtype != TIMTYPE_COUNTUP16_N) + { + /* Select the Counter Mode: + * + * GTIM_CR1_EDGE: The counter counts up or down depending on the + * direction bit (DIR). + * GTIM_CR1_CENTER1, GTIM_CR1_CENTER2, GTIM_CR1_CENTER3: The counter + * counts up then down. + * GTIM_CR1_DIR: 0: count up, 1: count down + */ + + cr1 &= ~(GTIM_CR1_DIR | GTIM_CR1_CMS_MASK); + + switch (priv->mode) + { + case STM32_TIMMODE_COUNTUP: + cr1 |= GTIM_CR1_EDGE; + break; + + case STM32_TIMMODE_COUNTDOWN: + cr1 |= GTIM_CR1_EDGE | GTIM_CR1_DIR; + break; + + case STM32_TIMMODE_CENTER1: + cr1 |= GTIM_CR1_CENTER1; + break; + + case STM32_TIMMODE_CENTER2: + cr1 |= GTIM_CR1_CENTER2; + break; + + case STM32_TIMMODE_CENTER3: + cr1 |= GTIM_CR1_CENTER3; + break; + + default: + pwmerr("ERROR: No such timer mode: %u\n", + (unsigned int)priv->mode); + return -EINVAL; + } + } +#endif + + /* Set the clock division to zero for all (but the basic timers, but there + * should be no basic timers in this context + */ + + cr1 &= ~GTIM_CR1_CKD_MASK; + stm32pwm_putreg(priv, STM32_GTIM_CR1_OFFSET, cr1); + + /* Set the reload and prescaler values */ + + stm32pwm_putreg(priv, STM32_GTIM_ARR_OFFSET, reload); + stm32pwm_putreg(priv, STM32_GTIM_PSC_OFFSET, (prescaler - 1)); + + /* Set the advanced timer's repetition counter */ + +#if defined(CONFIG_STM32_TIM1_PWM) || defined(CONFIG_STM32_TIM8_PWM) + if (priv->timtype == TIMTYPE_ADVANCED) + { + /* If a non-zero repetition count has been selected, then set the + * repetition counter to the count-1 (stm32pwm_start() has already + * assured us that the count value is within range). + */ + + { + /* Set the repetition counter to zero */ + + stm32pwm_putreg(priv, STM32_ATIM_RCR_OFFSET, 0); + + /* Generate an update event to reload the prescaler */ + + stm32pwm_putreg(priv, STM32_ATIM_EGR_OFFSET, ATIM_EGR_UG); + } + } + else +#endif + { + /* Generate an update event to reload the prescaler (all timers) */ + + stm32pwm_putreg(priv, STM32_GTIM_EGR_OFFSET, GTIM_EGR_UG); + } + + /* Handle channel specific setup */ + + ocmode1 = 0; +#if defined(HAVE_CCMR2) + ocmode2 = 0; +#endif + + for (i = 0; i < CONFIG_PWM_NCHANNELS; i++) + { + ub16_t duty; + uint32_t chanmode; + bool ocmbit = false; + uint8_t channel; + int j; + enum stm32_chanmode_e mode; + + /* Break the loop if all following channels are not configured */ + + if (info->channels[i].channel == -1) + { + break; + } + + duty = info->channels[i].duty; + channel = info->channels[i].channel; + + /* A value of zero means to skip this channel */ + + if (channel == 0) + { + continue; + } + + /* Find the channel */ + + for (j = 0; j < PWM_NCHANNELS; j++) + { + if (priv->channels[j].channel == channel) + { + mode = priv->channels[j].mode; + break; + } + } + + if (j >= PWM_NCHANNELS) + { + pwmerr("ERROR: No such channel: %u\n", channel); + return -EINVAL; + } + + /* Duty cycle: + * + * duty cycle = ccr / reload (fractional value) + */ + + ccr = b16toi(duty * reload + b16HALF); + + pwminfo("ccr: %" PRIu32 "\n", ccr); + + switch (mode) + { + case STM32_CHANMODE_PWM1: + chanmode = GTIM_CCMR_MODE_PWM1; + break; + + case STM32_CHANMODE_PWM2: + chanmode = GTIM_CCMR_MODE_PWM2; + break; + + case STM32_CHANMODE_COMBINED1: + chanmode = GTIM_CCMR_MODE_COMBINED1; + ocmbit = true; + break; + + case STM32_CHANMODE_COMBINED2: + chanmode = GTIM_CCMR_MODE_COMBINED2; + ocmbit = true; + break; + + case STM32_CHANMODE_ASYMMETRIC1: + chanmode = GTIM_CCMR_MODE_ASYMMETRIC1; + ocmbit = true; + break; + + case STM32_CHANMODE_ASYMMETRIC2: + chanmode = GTIM_CCMR_MODE_ASYMMETRIC2; + ocmbit = true; + break; + + default: + pwmerr("ERROR: No such mode: %u\n", (unsigned int)mode); + return -EINVAL; + } + + switch (channel) + { + case 1: /* PWM Mode configuration: Channel 1 */ + { + /* Set the CCMR1 mode values (leave CCMR2 zero) */ + + ocmode1 |= (GTIM_CCMR_CCS_CCOUT << GTIM_CCMR1_CC1S_SHIFT) | + (chanmode << GTIM_CCMR1_OC1M_SHIFT) | + GTIM_CCMR1_OC1PE; + + if (ocmbit) + { + ocmode1 |= GTIM_CCMR1_OC1M; + } + + /* Set the duty cycle by writing to the CCR register for this + * channel. + */ + + stm32pwm_putreg(priv, STM32_GTIM_CCR1_OFFSET, ccr); + + /* Reset the Output Compare Mode Bits and set the select + * output compare mode. + */ + + ccmr1 &= ~(GTIM_CCMR1_CC1S_MASK | GTIM_CCMR1_OC1M_MASK | + GTIM_CCMR1_OC1PE | GTIM_CCMR1_OC1M); + stm32pwm_output_configure(priv, channel); + } + break; + + case 2: /* PWM Mode configuration: Channel 2 */ + { + /* Set the CCMR1 mode values (leave CCMR2 zero) */ + + ocmode1 |= (GTIM_CCMR_CCS_CCOUT << GTIM_CCMR1_CC2S_SHIFT) | + (chanmode << GTIM_CCMR1_OC2M_SHIFT) | + GTIM_CCMR1_OC2PE; + + if (ocmbit) + { + ocmode1 |= GTIM_CCMR1_OC2M; + } + + /* Set the duty cycle by writing to the CCR register for this + * channel. + */ + + stm32pwm_putreg(priv, STM32_GTIM_CCR2_OFFSET, ccr); + + /* Reset the Output Compare Mode Bits and set the select + * output compare mode. + */ + + ccmr1 &= ~(GTIM_CCMR1_CC2S_MASK | GTIM_CCMR1_OC2M_MASK | + GTIM_CCMR1_OC2PE | GTIM_CCMR1_OC2M); + stm32pwm_output_configure(priv, channel); + } + break; + +#if defined(HAVE_CCMR2) + case 3: /* PWM Mode configuration: Channel 3 */ + { + /* Set the CCMR2 mode values (leave CCMR1 zero) */ + + ocmode2 |= (ATIM_CCMR_CCS_CCOUT << ATIM_CCMR2_CC3S_SHIFT) | + (chanmode << ATIM_CCMR2_OC3M_SHIFT) | + ATIM_CCMR2_OC3PE; + + if (ocmbit) + { + ocmode2 |= ATIM_CCMR2_OC3M; + } + + /* Set the duty cycle by writing to the CCR register for this + * channel. + */ + + stm32pwm_putreg(priv, STM32_ATIM_CCR3_OFFSET, ccr); + + /* Reset the Output Compare Mode Bits and set the select + * output compare mode. + */ + + ccmr2 &= ~(ATIM_CCMR2_CC3S_MASK | ATIM_CCMR2_OC3M_MASK | + ATIM_CCMR2_OC3PE | ATIM_CCMR2_OC3M); + stm32pwm_output_configure(priv, channel); + } + break; + + case 4: /* PWM Mode configuration: Channel 4 */ + { + /* Set the CCMR2 mode values (leave CCMR1 zero) */ + + ocmode2 |= (ATIM_CCMR_CCS_CCOUT << ATIM_CCMR2_CC4S_SHIFT) | + (chanmode << ATIM_CCMR2_OC4M_SHIFT) | + ATIM_CCMR2_OC4PE; + + if (ocmbit) + { + ocmode2 |= ATIM_CCMR2_OC4M; + } + + /* Set the duty cycle by writing to the CCR register for this + * channel. + */ + + stm32pwm_putreg(priv, STM32_ATIM_CCR4_OFFSET, ccr); + + /* Reset the Output Compare Mode Bits and set the select + * output compare mode. + */ + + ccmr2 &= ~(ATIM_CCMR2_CC4S_MASK | ATIM_CCMR2_OC4M_MASK | + ATIM_CCMR2_OC4PE | ATIM_CCMR2_OC4M); + stm32pwm_output_configure(priv, channel); + } + break; +#endif /* HAVE_CCMR2 */ + default: + pwmerr("ERROR: No such channel: %u\n", channel); + return -EINVAL; + } + } + + ccmr1 |= ocmode1; +#if defined(HAVE_CCMR2) + ccmr2 |= ocmode2; +#endif + + /* Special configuration for HAVE_ADVTIM */ + +#ifdef HAVE_ADVTIM + if (priv->timtype == TIMTYPE_ADVANCED || + priv->timtype == TIMTYPE_COUNTUP16_N) + { + uint32_t bdtr; + + /* Get current register state */ + + bdtr = stm32pwm_getreg(priv, STM32_ATIM_BDTR_OFFSET); + + /* Update deadtime */ + + bdtr &= ~(ATIM_BDTR_OSSI | ATIM_BDTR_OSSR); + bdtr |= ATIM_BDTR_MOE; + + stm32pwm_putreg(priv, STM32_ATIM_BDTR_OFFSET, bdtr); + } +#endif + + /* Save the modified register values */ + + putreg32(ccmr1, priv->base + STM32_GTIM_CCMR1_OFFSET); +#if defined(HAVE_CCMR2) + putreg32(ccmr2, priv->base + STM32_ATIM_CCMR2_OFFSET); +#endif + + /* Set the ARR Preload Bit */ + + cr1 = stm32pwm_getreg(priv, STM32_GTIM_CR1_OFFSET); + cr1 |= GTIM_CR1_ARPE; + stm32pwm_putreg(priv, STM32_GTIM_CR1_OFFSET, cr1); + + /* Just enable the timer, leaving all interrupts disabled */ + + cr1 |= GTIM_CR1_CEN; + stm32pwm_putreg(priv, STM32_GTIM_CR1_OFFSET, cr1); + + stm32pwm_dumpregs(priv, "After starting"); + return OK; +} + +/**************************************************************************** + * Name: stm32pwm_update_duty + * + * Description: + * Try to change only channel duty. + * + * Input Parameters: + * priv - A reference to the lower half PWM driver state structure + * channel - Channel to be updated + * duty - New duty. + * + * Returned Value: + * Zero on success; a negated errno value on failure + * + ****************************************************************************/ + +static int stm32pwm_update_duty(struct stm32_pwmtimer_s *priv, + uint8_t channel, ub16_t duty) +{ + /* Register offset */ + + int ccr_offset; + + /* Calculated values */ + + uint32_t reload; + uint32_t ccr; + + DEBUGASSERT(priv != NULL); + + pwminfo("TIM%u channel: %u duty: %08" PRIx32 "\n", + priv->timid, channel, duty); + + /* Get the reload values */ + + reload = stm32pwm_getreg(priv, STM32_GTIM_ARR_OFFSET); + + /* Duty cycle: + * + * duty cycle = ccr / reload (fractional value) + */ + + ccr = b16toi(duty * reload + b16HALF); + + pwminfo("ccr: %" PRIu32 "\n", ccr); + + switch (channel) + { + case 1: /* Register offset for Channel 1 */ + ccr_offset = STM32_GTIM_CCR1_OFFSET; + break; + + case 2: /* Register offset for Channel 2 */ + ccr_offset = STM32_GTIM_CCR2_OFFSET; + break; + + case 3: /* Register offset for Channel 3 */ + ccr_offset = STM32_GTIM_CCR3_OFFSET; + break; + + case 4: /* Register offset for Channel 4 */ + ccr_offset = STM32_GTIM_CCR4_OFFSET; + break; + + default: + pwmerr("ERROR: No such channel: %u\n", channel); + return -EINVAL; + } + + /* Set the duty cycle by writing to the CCR register for this channel */ + + stm32pwm_putreg(priv, ccr_offset, ccr); + + return OK; +} + +/**************************************************************************** + * Name: stm32pwm_setapbclock + * + * Description: + * Enable or disable APB clock for the timer peripheral + * + * Input Parameters: + * dev - A reference to the lower half PWM driver state structure + * on - Enable clock if 'on' is 'true' and disable if 'false' + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void stm32pwm_setapbclock(struct stm32_pwmtimer_s *priv, bool on) +{ + uint32_t en_bit; + uint32_t regaddr; + + /* Determine which timer to configure */ + + switch (priv->timid) + { +#ifdef CONFIG_STM32_TIM1_PWM + case 1: + regaddr = STM32_RCC_APB2ENR; + en_bit = RCC_APB2ENR_TIM1EN; + break; +#endif +#ifdef CONFIG_STM32_TIM2_PWM + case 2: + regaddr = STM32_RCC_APB1ENR; + en_bit = RCC_APB1ENR_TIM2EN; + break; +#endif +#ifdef CONFIG_STM32_TIM3_PWM + case 3: + regaddr = STM32_RCC_APB1ENR; + en_bit = RCC_APB1ENR_TIM3EN; + break; +#endif +#ifdef CONFIG_STM32_TIM14_PWM + case 14: + regaddr = STM32_RCC_APB2ENR; + en_bit = RCC_APB2ENR_TIM14EN; + break; +#endif +#ifdef CONFIG_STM32_TIM15_PWM + case 15: + regaddr = STM32_RCC_APB2ENR; + en_bit = RCC_APB2ENR_TIM15EN; + break; +#endif +#ifdef CONFIG_STM32_TIM16_PWM + case 16: + regaddr = STM32_RCC_APB2ENR; + en_bit = RCC_APB2ENR_TIM16EN; + break; +#endif +#ifdef CONFIG_STM32_TIM17_PWM + case 17: + regaddr = STM32_RCC_APB2ENR; + en_bit = RCC_APB2ENR_TIM17EN; + break; +#endif + default: + return; + } + + /* Enable/disable APB 1/2 clock for timer */ + + if (on) + { + modifyreg32(regaddr, 0, en_bit); + } + else + { + modifyreg32(regaddr, en_bit, 0); + } +} + +/**************************************************************************** + * Name: stm32pwm_setup + * + * Description: + * This method is called when the driver is opened. The lower half driver + * should configure and initialize the device so that it is ready for use. + * It should not, however, output pulses until the start method is called. + * + * Input Parameters: + * dev - A reference to the lower half PWM driver state structure + * + * Returned Value: + * Zero on success; a negated errno value on failure + * + * Assumptions: + * APB1 or 2 clocking for the GPIOs has already been configured by the RCC + * logic at power up. + * + ****************************************************************************/ + +static int stm32pwm_setup(struct pwm_lowerhalf_s *dev) +{ + struct stm32_pwmtimer_s *priv = (struct stm32_pwmtimer_s *)dev; + uint32_t pincfg; + int i; + + pwminfo("TIM%u\n", priv->timid); + stm32pwm_dumpregs(priv, "Initially"); + + /* Enable APB1/2 clocking for timer. */ + + stm32pwm_setapbclock(priv, true); + + /* Configure the PWM output pins, but do not start the timer yet */ + + for (i = 0; i < PWM_NCHANNELS; i++) + { + pincfg = priv->channels[i].pincfg; + if (pincfg != 0) + { + pwminfo("pincfg: %08" PRIx32 "\n", pincfg); + + stm32_configgpio(pincfg); + } + + /* Enable complementary channel if available */ + + pincfg = priv->channels[i].npincfg; + if (pincfg != 0) + { + pwminfo("npincfg: %08" PRIx32 "\n", pincfg); + + stm32_configgpio(pincfg); + } + + pwm_dumpgpio(pincfg, "PWM setup"); + } + + return OK; +} + +/**************************************************************************** + * Name: stm32pwm_shutdown + * + * Description: + * This method is called when the driver is closed. The lower half driver + * stop pulsed output, free any resources, disable the timer hardware, and + * put the system into the lowest possible power usage state + * + * Input Parameters: + * dev - A reference to the lower half PWM driver state structure + * + * Returned Value: + * Zero on success; a negated errno value on failure + * + ****************************************************************************/ + +static int stm32pwm_shutdown(struct pwm_lowerhalf_s *dev) +{ + struct stm32_pwmtimer_s *priv = (struct stm32_pwmtimer_s *)dev; + uint32_t pincfg; + int i; + + pwminfo("TIM%u\n", priv->timid); + + /* Make sure that the output has been stopped */ + + stm32pwm_stop(dev); + + /* Disable APB1/2 clocking for timer. */ + + stm32pwm_setapbclock(priv, false); + + /* Then put the GPIO pins back to the default state */ + + for (i = 0; i < PWM_NCHANNELS; i++) + { + pincfg = priv->channels[i].pincfg; + if (pincfg != 0) + { + pwminfo("pincfg: %08" PRIx32 "\n", pincfg); + + pincfg &= (GPIO_PORT_MASK | GPIO_PIN_MASK); + pincfg |= GPIO_INPUT | GPIO_FLOAT; + + stm32_configgpio(pincfg); + } + + pincfg = priv->channels[i].npincfg; + if (pincfg != 0) + { + pwminfo("npincfg: %08" PRIx32 "\n", pincfg); + + pincfg &= (GPIO_PORT_MASK | GPIO_PIN_MASK); + pincfg |= GPIO_INPUT | GPIO_FLOAT; + + stm32_configgpio(pincfg); + } + } + + return OK; +} + +/**************************************************************************** + * Name: stm32pwm_start + * + * Description: + * (Re-)initialize the timer resources and start the pulsed output + * + * Input Parameters: + * dev - A reference to the lower half PWM driver state structure + * info - A reference to the characteristics of the pulsed output + * + * Returned Value: + * Zero on success; a negated errno value on failure + * + ****************************************************************************/ + +static int stm32pwm_start(struct pwm_lowerhalf_s *dev, + const struct pwm_info_s *info) +{ + int ret = OK; + struct stm32_pwmtimer_s *priv = (struct stm32_pwmtimer_s *)dev; + + /* if frequency has not changed we just update duty */ + + if (info->frequency == priv->frequency) + { + int i; + + for (i = 0; ret == OK && i < CONFIG_PWM_NCHANNELS; i++) + { + /* Break the loop if all following channels are not configured */ + + if (info->channels[i].channel == -1) + { + break; + } + + /* Set output if channel configured */ + + if (info->channels[i].channel != 0) + { + ret = stm32pwm_update_duty(priv, info->channels[i].channel, + info->channels[i].duty); + } + } + } + else + { + ret = stm32pwm_timer(priv, info); + + /* Save current frequency */ + + if (ret == OK) + { + priv->frequency = info->frequency; + } + } + + return ret; +} + +/**************************************************************************** + * Name: stm32pwm_stop + * + * Description: + * Stop the pulsed output and reset the timer resources + * + * Input Parameters: + * dev - A reference to the lower half PWM driver state structure + * + * Returned Value: + * Zero on success; a negated errno value on failure + * + * Assumptions: + * This function is called to stop the pulsed output at anytime. This + * method is also called from the timer interrupt handler when a repetition + * count expires... automatically stopping the timer. + * + ****************************************************************************/ + +static int stm32pwm_stop(struct pwm_lowerhalf_s *dev) +{ + struct stm32_pwmtimer_s *priv = (struct stm32_pwmtimer_s *)dev; + uint32_t resetbit; + uint32_t regaddr; + uint32_t regval; + irqstate_t flags; + + pwminfo("TIM%u\n", priv->timid); + + /* Disable interrupts momentary to stop any ongoing timer processing and + * to prevent any concurrent access to the reset register. + */ + + flags = enter_critical_section(); + + /* Stopped so frequency is zero */ + + priv->frequency = 0; + + /* Disable further interrupts and stop the timer */ + + stm32pwm_putreg(priv, STM32_GTIM_DIER_OFFSET, 0); + stm32pwm_putreg(priv, STM32_GTIM_SR_OFFSET, 0); + + /* Determine which timer to reset */ + + switch (priv->timid) + { +#ifdef CONFIG_STM32_TIM1_PWM + case 1: + regaddr = STM32_RCC_APB2RSTR; + resetbit = RCC_APB2RSTR_TIM1RST; + break; +#endif + +#ifdef CONFIG_STM32_TIM2_PWM + case 2: + regaddr = STM32_RCC_APB1RSTR; + resetbit = RCC_APB1RSTR_TIM2RST; + break; +#endif + +#ifdef CONFIG_STM32_TIM3_PWM + case 3: + regaddr = STM32_RCC_APB1RSTR; + resetbit = RCC_APB1RSTR_TIM3RST; + break; +#endif + +#ifdef CONFIG_STM32_TIM4_PWM + case 4: + regaddr = STM32_RCC_APB1RSTR; + resetbit = RCC_APB1RSTR_TIM4RST; + break; +#endif + +#ifdef CONFIG_STM32_TIM5_PWM + case 5: + regaddr = STM32_RCC_APB1RSTR; + resetbit = RCC_APB1RSTR_TIM5RST; + break; +#endif + +#ifdef CONFIG_STM32_TIM8_PWM + case 8: + regaddr = STM32_RCC_APB2RSTR; + resetbit = RCC_APB2RSTR_TIM8RST; + break; +#endif + +#ifdef CONFIG_STM32_TIM14_PWM + case 14: + regaddr = STM32_RCC_APB2RSTR; + resetbit = RCC_APB2RSTR_TIM14RST; + break; +#endif + +#ifdef CONFIG_STM32_TIM15_PWM + case 15: + regaddr = STM32_RCC_APB2RSTR; + resetbit = RCC_APB2RSTR_TIM15RST; + break; +#endif + +#ifdef CONFIG_STM32_TIM16_PWM + case 16: + regaddr = STM32_RCC_APB2RSTR; + resetbit = RCC_APB2RSTR_TIM16RST; + break; +#endif + +#ifdef CONFIG_STM32_TIM17_PWM + case 17: + regaddr = STM32_RCC_APB2RSTR; + resetbit = RCC_APB2RSTR_TIM17RST; + break; +#endif + + default: + leave_critical_section(flags); + return -EINVAL; + } + + /* Reset the timer - stopping the output and putting the timer back + * into a state where stm32pwm_start() can be called. + */ + + regval = getreg32(regaddr); + regval |= resetbit; + putreg32(regval, regaddr); + + regval &= ~resetbit; + putreg32(regval, regaddr); + leave_critical_section(flags); + + pwminfo("regaddr: %08" PRIx32 " resetbit: %08" PRIx32 "\n", + regaddr, resetbit); + stm32pwm_dumpregs(priv, "After stop"); + return OK; +} + +/**************************************************************************** + * Name: stm32pwm_ioctl + * + * Description: + * Lower-half logic may support platform-specific ioctl commands + * + * Input Parameters: + * dev - A reference to the lower half PWM driver state structure + * cmd - The ioctl command + * arg - The argument accompanying the ioctl command + * + * Returned Value: + * Zero on success; a negated errno value on failure + * + ****************************************************************************/ + +static int stm32pwm_ioctl(struct pwm_lowerhalf_s *dev, int cmd, + unsigned long arg) +{ +#ifdef CONFIG_DEBUG_PWM_INFO + struct stm32_pwmtimer_s *priv = (struct stm32_pwmtimer_s *)dev; + + /* There are no platform-specific ioctl commands */ + + pwminfo("TIM%u\n", priv->timid); +#endif + return -ENOTTY; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_pwminitialize + * + * Description: + * Initialize one timer for use with the upper_level PWM driver. + * + * Input Parameters: + * timer - A number identifying the timer use. The number of valid timer + * IDs varies with the STM32 MCU and MCU family but is somewhere in + * the range of {1,..,17}. + * + * Returned Value: + * On success, a pointer to the STM32 lower half PWM driver is returned. + * NULL is returned on any failure. + * + ****************************************************************************/ + +struct pwm_lowerhalf_s *stm32_pwminitialize(int timer) +{ + struct stm32_pwmtimer_s *lower; + + pwminfo("TIM%u\n", timer); + + switch (timer) + { +#ifdef CONFIG_STM32_TIM1_PWM + case 1: + lower = &g_pwm1dev; + + /* Attach but disable the TIM1 update interrupt */ + + break; +#endif + +#ifdef CONFIG_STM32_TIM2_PWM + case 2: + lower = &g_pwm2dev; + break; +#endif + +#ifdef CONFIG_STM32_TIM3_PWM + case 3: + lower = &g_pwm3dev; + break; +#endif + +#ifdef CONFIG_STM32_TIM4_PWM + case 4: + lower = &g_pwm4dev; + break; +#endif + +#ifdef CONFIG_STM32_TIM5_PWM + case 5: + lower = &g_pwm5dev; + break; +#endif + +#ifdef CONFIG_STM32_TIM8_PWM + case 8: + lower = &g_pwm8dev; + + /* Attach but disable the TIM8 update interrupt */ + + break; +#endif + +#ifdef CONFIG_STM32_TIM14_PWM + case 14: + lower = &g_pwm14dev; + break; +#endif + +#ifdef CONFIG_STM32_TIM15_PWM + case 15: + lower = &g_pwm15dev; + break; +#endif + +#ifdef CONFIG_STM32_TIM16_PWM + case 16: + lower = &g_pwm16dev; + break; +#endif + +#ifdef CONFIG_STM32_TIM17_PWM + case 17: + lower = &g_pwm17dev; + break; +#endif + + default: + pwmerr("ERROR: No such timer configured\n"); + return NULL; + } + + return (struct pwm_lowerhalf_s *)lower; +} + +#endif /* CONFIG_STM32_TIMx_PWM */ diff --git a/arch/arm/src/common/stm32/stm32_pwm_m0_v1.h b/arch/arm/src/common/stm32/stm32_pwm_m0_v1.h new file mode 100644 index 0000000000000..eafff64985fa6 --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_pwm_m0_v1.h @@ -0,0 +1,563 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_pwm_m0_v1.h + * + * SPDX-License-Identifier: BSD-3-Clause + * SPDX-FileCopyrightText: 2019 Fundação CERTI. All rights reserved. + * SPDX-FileContributor: Daniel Pereira Volpato + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_PWM_V3_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_PWM_V3_H + +/* The STM32F0L0G0 does not have dedicated PWM hardware. Rather, pulsed + * output control is a capability of the STM32F0L0G0 timers. The logic in + * this file implements the lower half of the standard, NuttX PWM interface + * using the STM32F0L0G0 timers. That interface is described in + * include/nuttx/timers/pwm.h. + */ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include + +#include "chip.h" +#include "hardware/stm32_tim.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* Timer devices may be used for different purposes. One special purpose is + * to generate modulated outputs for such things as motor control. If + * CONFIG_STM32_TIMn is defined then the CONFIG_STM32_TIMn_PWM + * must also be defined to indicate that timer "n" is intended to be used for + * pulsed output signal generation. + */ + +#ifndef CONFIG_STM32_TIM1 +# undef CONFIG_STM32_TIM1_PWM +#endif +#ifndef CONFIG_STM32_TIM2 +# undef CONFIG_STM32_TIM2_PWM +#endif +#ifndef CONFIG_STM32_TIM3 +# undef CONFIG_STM32_TIM3_PWM +#endif +#ifndef CONFIG_STM32_TIM14 +# undef CONFIG_STM32_TIM14_PWM +#endif +#ifndef CONFIG_STM32_TIM15 +# undef CONFIG_STM32_TIM15_PWM +#endif +#ifndef CONFIG_STM32_TIM16 +# undef CONFIG_STM32_TIM16_PWM +#endif +#ifndef CONFIG_STM32_TIM17 +# undef CONFIG_STM32_TIM17_PWM +#endif + +/* The basic timers (timer 6 and 7) + * are not capable of generating output pulses + */ + +#undef CONFIG_STM32_TIM6_PWM +#undef CONFIG_STM32_TIM7_PWM + +/* Check if PWM support for any channel is enabled. */ + +#if defined(CONFIG_STM32_TIM1_PWM) || defined(CONFIG_STM32_TIM2_PWM) || \ + defined(CONFIG_STM32_TIM3_PWM) || defined(CONFIG_STM32_TIM14_PWM) || \ + defined(CONFIG_STM32_TIM15_PWM) || defined(CONFIG_STM32_TIM16_PWM) || \ + defined(CONFIG_STM32_TIM17_PWM) + +#ifdef CONFIG_STM32_PWM_MULTICHAN + +#ifdef CONFIG_STM32_TIM1_CHANNEL1 +# ifdef CONFIG_STM32_TIM1_CH1OUT +# define PWM_TIM1_CH1CFG GPIO_TIM1_CH1OUT +# else +# define PWM_TIM1_CH1CFG 0 +# endif +# ifdef CONFIG_STM32_TIM1_CH1NOUT +# define PWM_TIM1_CH1NCFG GPIO_TIM1_CH1NOUT +# else +# define PWM_TIM1_CH1NCFG 0 +# endif +# define PWM_TIM1_CHANNEL1 1 +#else +# define PWM_TIM1_CHANNEL1 0 +#endif +#ifdef CONFIG_STM32_TIM1_CHANNEL2 +# ifdef CONFIG_STM32_TIM1_CH2OUT +# define PWM_TIM1_CH2CFG GPIO_TIM1_CH2OUT +# else +# define PWM_TIM1_CH2CFG 0 +# endif +# ifdef CONFIG_STM32_TIM1_CH2NOUT +# define PWM_TIM1_CH2NCFG GPIO_TIM1_CH2NOUT +# else +# define PWM_TIM1_CH2NCFG 0 +# endif +# define PWM_TIM1_CHANNEL2 1 +#else +# define PWM_TIM1_CHANNEL2 0 +#endif +#ifdef CONFIG_STM32_TIM1_CHANNEL3 +# ifdef CONFIG_STM32_TIM1_CH3OUT +# define PWM_TIM1_CH3CFG GPIO_TIM1_CH3OUT +# else +# define PWM_TIM1_CH3CFG 0 +# endif +# ifdef CONFIG_STM32_TIM1_CH3NOUT +# define PWM_TIM1_CH3NCFG GPIO_TIM1_CH3NOUT +# else +# define PWM_TIM1_CH3NCFG 0 +# endif +# define PWM_TIM1_CHANNEL3 1 +#else +# define PWM_TIM1_CHANNEL3 0 +#endif +#ifdef CONFIG_STM32_TIM1_CHANNEL4 +# ifdef CONFIG_STM32_TIM1_CH4OUT +# define PWM_TIM1_CH4CFG GPIO_TIM1_CH4OUT +# else +# define PWM_TIM1_CH4CFG 0 +# endif +# define PWM_TIM1_CHANNEL4 1 +#else +# define PWM_TIM1_CHANNEL4 0 +#endif +#define PWM_TIM1_NCHANNELS (PWM_TIM1_CHANNEL1 + PWM_TIM1_CHANNEL2 + \ + PWM_TIM1_CHANNEL3 + PWM_TIM1_CHANNEL4) + +#ifdef CONFIG_STM32_TIM2_CHANNEL1 +# ifdef CONFIG_STM32_TIM2_CH1OUT +# define PWM_TIM2_CH1CFG GPIO_TIM2_CH1OUT +# else +# define PWM_TIM2_CH1CFG 0 +# endif +# define PWM_TIM2_CHANNEL1 1 +#else +# define PWM_TIM2_CHANNEL1 0 +#endif +#ifdef CONFIG_STM32_TIM2_CHANNEL2 +# ifdef CONFIG_STM32_TIM2_CH2OUT +# define PWM_TIM2_CH2CFG GPIO_TIM2_CH2OUT +# else +# define PWM_TIM2_CH2CFG 0 +# endif +# define PWM_TIM2_CHANNEL2 1 +#else +# define PWM_TIM2_CHANNEL2 0 +#endif +#ifdef CONFIG_STM32_TIM2_CHANNEL3 +# ifdef CONFIG_STM32_TIM2_CH3OUT +# define PWM_TIM2_CH3CFG GPIO_TIM2_CH3OUT +# else +# define PWM_TIM2_CH3CFG 0 +# endif +# define PWM_TIM2_CHANNEL3 1 +#else +# define PWM_TIM2_CHANNEL3 0 +#endif +#ifdef CONFIG_STM32_TIM2_CHANNEL4 +# ifdef CONFIG_STM32_TIM2_CH4OUT +# define PWM_TIM2_CH4CFG GPIO_TIM2_CH4OUT +# else +# define PWM_TIM2_CH4CFG 0 +# endif +# define PWM_TIM2_CHANNEL4 1 +#else +# define PWM_TIM2_CHANNEL4 0 +#endif +#define PWM_TIM2_NCHANNELS (PWM_TIM2_CHANNEL1 + PWM_TIM2_CHANNEL2 + \ + PWM_TIM2_CHANNEL3 + PWM_TIM2_CHANNEL4) + +#ifdef CONFIG_STM32_TIM3_CHANNEL1 +# ifdef CONFIG_STM32_TIM3_CH1OUT +# define PWM_TIM3_CH1CFG GPIO_TIM3_CH1OUT +# else +# define PWM_TIM3_CH1CFG 0 +# endif +# define PWM_TIM3_CHANNEL1 1 +#else +# define PWM_TIM3_CHANNEL1 0 +#endif +#ifdef CONFIG_STM32_TIM3_CHANNEL2 +# ifdef CONFIG_STM32_TIM3_CH2OUT +# define PWM_TIM3_CH2CFG GPIO_TIM3_CH2OUT +# else +# define PWM_TIM3_CH2CFG 0 +# endif +# define PWM_TIM3_CHANNEL2 1 +#else +# define PWM_TIM3_CHANNEL2 0 +#endif +#ifdef CONFIG_STM32_TIM3_CHANNEL3 +# ifdef CONFIG_STM32_TIM3_CH3OUT +# define PWM_TIM3_CH3CFG GPIO_TIM3_CH3OUT +# else +# define PWM_TIM3_CH3CFG 0 +# endif +# define PWM_TIM3_CHANNEL3 1 +#else +# define PWM_TIM3_CHANNEL3 0 +#endif +#ifdef CONFIG_STM32_TIM3_CHANNEL4 +# ifdef CONFIG_STM32_TIM3_CH4OUT +# define PWM_TIM3_CH4CFG GPIO_TIM3_CH4OUT +# else +# define PWM_TIM3_CH4CFG 0 +# endif +# define PWM_TIM3_CHANNEL4 1 +#else +# define PWM_TIM3_CHANNEL4 0 +#endif +#define PWM_TIM3_NCHANNELS (PWM_TIM3_CHANNEL1 + PWM_TIM3_CHANNEL2 + \ + PWM_TIM3_CHANNEL3 + PWM_TIM3_CHANNEL4) + +#ifdef CONFIG_STM32_TIM14_CHANNEL1 +# ifdef CONFIG_STM32_TIM14_CH1OUT +# define PWM_TIM14_CH1CFG GPIO_TIM14_CH1OUT +# else +# define PWM_TIM14_CH1CFG 0 +# endif +# ifdef CONFIG_STM32_TIM14_CH1NOUT +# define PWM_TIM14_CH1NCFG GPIO_TIM14_CH1NOUT +# else +# define PWM_TIM14_CH1NCFG 0 +# endif +# define PWM_TIM14_CHANNEL1 1 +#else +# define PWM_TIM14_CHANNEL1 0 +#endif +#define PWM_TIM14_NCHANNELS PWM_TIM14_CHANNEL1 + +#ifdef CONFIG_STM32_TIM15_CHANNEL1 +# ifdef CONFIG_STM32_TIM15_CH1OUT +# define PWM_TIM15_CH1CFG GPIO_TIM15_CH1OUT +# else +# define PWM_TIM15_CH1CFG 0 +# endif +# ifdef CONFIG_STM32_TIM15_CH1NOUT +# define PWM_TIM15_CH1NCFG GPIO_TIM15_CH1NOUT +# else +# define PWM_TIM15_CH1NCFG 0 +# endif +# define PWM_TIM15_CHANNEL1 1 +#else +# define PWM_TIM15_CHANNEL1 0 +#endif +#ifdef CONFIG_STM32_TIM15_CHANNEL2 +# ifdef CONFIG_STM32_TIM15_CH2OUT +# define PWM_TIM15_CH2CFG GPIO_TIM15_CH2OUT +# else +# define PWM_TIM15_CH2CFG 0 +# endif +# define PWM_TIM15_CHANNEL2 1 +#else +# define PWM_TIM15_CHANNEL2 0 +#endif +#define PWM_TIM15_NCHANNELS (PWM_TIM15_CHANNEL1 + PWM_TIM15_CHANNEL2) + +#ifdef CONFIG_STM32_TIM16_CHANNEL1 +# ifdef CONFIG_STM32_TIM16_CH1OUT +# define PWM_TIM16_CH1CFG GPIO_TIM16_CH1OUT +# else +# define PWM_TIM16_CH1CFG 0 +# endif +# ifdef CONFIG_STM32_TIM16_CH1NOUT +# define PWM_TIM16_CH1NCFG GPIO_TIM16_CH1NOUT +# else +# define PWM_TIM16_CH1NCFG 0 +# endif +# define PWM_TIM16_CHANNEL1 1 +#else +# define PWM_TIM16_CHANNEL1 0 +#endif +#define PWM_TIM16_NCHANNELS PWM_TIM16_CHANNEL1 + +#ifdef CONFIG_STM32_TIM17_CHANNEL1 +# ifdef CONFIG_STM32_TIM17_CH1OUT +# define PWM_TIM17_CH1CFG GPIO_TIM17_CH1OUT +# else +# define PWM_TIM17_CH1CFG 0 +# endif +# ifdef CONFIG_STM32_TIM17_CH1NOUT +# define PWM_TIM17_CH1NCFG GPIO_TIM17_CH1NOUT +# else +# define PWM_TIM17_CH1NCFG 0 +# endif +# define PWM_TIM17_CHANNEL1 1 +#else +# define PWM_TIM17_CHANNEL1 0 +#endif +#define PWM_TIM17_NCHANNELS PWM_TIM17_CHANNEL1 + +#define PWM_NCHANNELS MAX(PWM_TIM1_NCHANNELS, \ + MAX(PWM_TIM2_NCHANNELS, \ + MAX(PWM_TIM3_NCHANNELS, \ + MAX(PWM_TIM14_NCHANNELS, \ + MAX(PWM_TIM15_NCHANNELS, \ + MAX(PWM_TIM16_NCHANNELS, \ + PWM_TIM17_NCHANNELS)))))) + +#else /* !CONFIG_STM32_PWM_MULTICHAN */ + +/* For each timer that is enabled for PWM usage, we need the following + * additional configuration settings: + * + * CONFIG_STM32_TIMx_CHANNEL - Specifies the timer output channel + * {1,..,4} PWM_TIMx_CHn - One of the values defined in + * chip/stm32*_pinmap.h. In the case where there are multiple pin + * selections, the correct setting must be provided in the arch/board/board.h + * file. + * + * NOTE: The STM32 timers are each capable of generating different signals on + * each of the four channels with different duty cycles. That capability is + * not supported by this driver: Only one output channel per timer. + */ + +#ifdef CONFIG_STM32_TIM1_PWM +# if !defined(CONFIG_STM32_TIM1_CHANNEL) +# error "CONFIG_STM32_TIM1_CHANNEL must be provided" +# elif CONFIG_STM32_TIM1_CHANNEL == 1 +# define CONFIG_STM32_TIM1_CHANNEL1 1 +# define CONFIG_STM32_TIM1_CH1MODE CONFIG_STM32_TIM1_CHMODE +# define PWM_TIM1_CH1CFG GPIO_TIM1_CH1OUT +# define PWM_TIM1_CH1NCFG 0 +# elif CONFIG_STM32_TIM1_CHANNEL == 2 +# define CONFIG_STM32_TIM1_CHANNEL2 1 +# define CONFIG_STM32_TIM1_CH2MODE CONFIG_STM32_TIM1_CHMODE +# define PWM_TIM1_CH2CFG GPIO_TIM1_CH2OUT +# define PWM_TIM1_CH2NCFG 0 +# elif CONFIG_STM32_TIM1_CHANNEL == 3 +# define CONFIG_STM32_TIM1_CHANNEL3 1 +# define CONFIG_STM32_TIM1_CH3MODE CONFIG_STM32_TIM1_CHMODE +# define PWM_TIM1_CH3CFG GPIO_TIM1_CH3OUT +# define PWM_TIM1_CH3NCFG 0 +# elif CONFIG_STM32_TIM1_CHANNEL == 4 +# define CONFIG_STM32_TIM1_CHANNEL4 1 +# define CONFIG_STM32_TIM1_CH4MODE CONFIG_STM32_TIM1_CHMODE +# define PWM_TIM1_CH4CFG GPIO_TIM1_CH4OUT +# else +# error "Unsupported value of CONFIG_STM32_TIM1_CHANNEL" +# endif +#endif + +#ifdef CONFIG_STM32_TIM2_PWM +# if !defined(CONFIG_STM32_TIM2_CHANNEL) +# error "CONFIG_STM32_TIM2_CHANNEL must be provided" +# elif CONFIG_STM32_TIM2_CHANNEL == 1 +# define CONFIG_STM32_TIM2_CHANNEL1 1 +# define CONFIG_STM32_TIM2_CH1MODE CONFIG_STM32_TIM2_CHMODE +# define PWM_TIM2_CH1CFG GPIO_TIM2_CH1OUT +# elif CONFIG_STM32_TIM2_CHANNEL == 2 +# define CONFIG_STM32_TIM2_CHANNEL2 1 +# define CONFIG_STM32_TIM2_CH2MODE CONFIG_STM32_TIM2_CHMODE +# define PWM_TIM2_CH2CFG GPIO_TIM2_CH2OUT +# elif CONFIG_STM32_TIM2_CHANNEL == 3 +# define CONFIG_STM32_TIM2_CHANNEL3 1 +# define CONFIG_STM32_TIM2_CH3MODE CONFIG_STM32_TIM2_CHMODE +# define PWM_TIM2_CH3CFG GPIO_TIM2_CH3OUT +# elif CONFIG_STM32_TIM2_CHANNEL == 4 +# define CONFIG_STM32_TIM2_CHANNEL4 1 +# define CONFIG_STM32_TIM2_CH4MODE CONFIG_STM32_TIM2_CHMODE +# define PWM_TIM2_CH4CFG GPIO_TIM2_CH4OUT +# else +# error "Unsupported value of CONFIG_STM32_TIM2_CHANNEL" +# endif +#endif + +#ifdef CONFIG_STM32_TIM3_PWM +# if !defined(CONFIG_STM32_TIM3_CHANNEL) +# error "CONFIG_STM32_TIM3_CHANNEL must be provided" +# elif CONFIG_STM32_TIM3_CHANNEL == 1 +# define CONFIG_STM32_TIM3_CHANNEL1 1 +# define CONFIG_STM32_TIM3_CH1MODE CONFIG_STM32_TIM3_CHMODE +# define PWM_TIM3_CH1CFG GPIO_TIM3_CH1OUT +# elif CONFIG_STM32_TIM3_CHANNEL == 2 +# define CONFIG_STM32_TIM3_CHANNEL2 1 +# define CONFIG_STM32_TIM3_CH2MODE CONFIG_STM32_TIM3_CHMODE +# define PWM_TIM3_CH2CFG GPIO_TIM3_CH2OUT +# elif CONFIG_STM32_TIM3_CHANNEL == 3 +# define CONFIG_STM32_TIM3_CHANNEL3 1 +# define CONFIG_STM32_TIM3_CH3MODE CONFIG_STM32_TIM3_CHMODE +# define PWM_TIM3_CH3CFG GPIO_TIM3_CH3OUT +# elif CONFIG_STM32_TIM3_CHANNEL == 4 +# define CONFIG_STM32_TIM3_CHANNEL4 1 +# define CONFIG_STM32_TIM3_CH4MODE CONFIG_STM32_TIM3_CHMODE +# define PWM_TIM3_CH4CFG GPIO_TIM3_CH4OUT +# else +# error "Unsupported value of CONFIG_STM32_TIM3_CHANNEL" +# endif +#endif + +#ifdef CONFIG_STM32_TIM14_PWM +# if !defined(CONFIG_STM32_TIM14_CHANNEL) +# error "CONFIG_STM32_TIM14_CHANNEL must be provided" +# elif CONFIG_STM32_TIM14_CHANNEL == 1 +# define CONFIG_STM32_TIM14_CHANNEL1 1 +# define CONFIG_STM32_TIM14_CH1MODE CONFIG_STM32_TIM14_CHMODE +# define PWM_TIM14_CH1CFG GPIO_TIM14_CH1OUT +# define PWM_TIM14_CH1NCFG 0 +# else +# error "Unsupported value of CONFIG_STM32_TIM14_CHANNEL" +# endif +#endif + +#ifdef CONFIG_STM32_TIM15_PWM +# if !defined(CONFIG_STM32_TIM15_CHANNEL) +# error "CONFIG_STM32_TIM15_CHANNEL must be provided" +# elif CONFIG_STM32_TIM15_CHANNEL == 1 +# define CONFIG_STM32_TIM15_CHANNEL1 1 +# define CONFIG_STM32_TIM15_CH1MODE CONFIG_STM32_TIM15_CHMODE +# define PWM_TIM15_CH1CFG GPIO_TIM15_CH1OUT +# define PWM_TIM15_CH1NCFG 0 +# elif CONFIG_STM32_TIM15_CHANNEL == 2 +# define CONFIG_STM32_TIM15_CHANNEL2 1 +# define CONFIG_STM32_TIM15_CH2MODE CONFIG_STM32_TIM15_CHMODE +# define PWM_TIM15_CH2CFG GPIO_TIM15_CH2OUT +# else +# error "Unsupported value of CONFIG_STM32_TIM15_CHANNEL" +# endif +#endif + +#ifdef CONFIG_STM32_TIM16_PWM +# if !defined(CONFIG_STM32_TIM16_CHANNEL) +# error "CONFIG_STM32_TIM16_CHANNEL must be provided" +# elif CONFIG_STM32_TIM16_CHANNEL == 1 +# define CONFIG_STM32_TIM16_CHANNEL1 1 +# define CONFIG_STM32_TIM16_CH1MODE CONFIG_STM32_TIM16_CHMODE +# define PWM_TIM16_CH1CFG GPIO_TIM16_CH1OUT +# define PWM_TIM16_CH1NCFG 0 +# else +# error "Unsupported value of CONFIG_STM32_TIM16_CHANNEL" +# endif +#endif + +#ifdef CONFIG_STM32_TIM17_PWM +# if !defined(CONFIG_STM32_TIM17_CHANNEL) +# error "CONFIG_STM32_TIM17_CHANNEL must be provided" +# elif CONFIG_STM32_TIM17_CHANNEL == 1 +# define CONFIG_STM32_TIM17_CHANNEL1 1 +# define CONFIG_STM32_TIM17_CH1MODE CONFIG_STM32_TIM17_CHMODE +# define PWM_TIM17_CH1CFG GPIO_TIM17_CH1OUT +# define PWM_TIM17_CH1NCFG 0 +# else +# error "Unsupported value of CONFIG_STM32_TIM17_CHANNEL" +# endif +#endif + +#define PWM_NCHANNELS 1 + +#endif + +/* Complementary outputs support */ + +#if defined(CONFIG_STM32_TIM1_CH1NOUT) || defined(CONFIG_STM32_TIM1_CH2NOUT) || \ + defined(CONFIG_STM32_TIM1_CH3NOUT) +# define HAVE_TIM1_COMPLEMENTARY +#endif +#if defined(CONFIG_STM32_TIM15_CH1NOUT) +# define HAVE_TIM15_COMPLEMENTARY +#endif +#if defined(CONFIG_STM32_TIM16_CH1NOUT) +# define HAVE_TIM16_COMPLEMENTARY +#endif +#if defined(CONFIG_STM32_TIM17_CH1NOUT) +# define HAVE_TIM17_COMPLEMENTARY +#endif +#if defined(HAVE_TIM1_COMPLEMENTARY) || defined(HAVE_TIM8_COMPLEMENTARY) || \ + defined(HAVE_TIM15_COMPLEMENTARY) || defined(HAVE_TIM16_COMPLEMENTARY) || \ + defined(HAVE_TIM17_COMPLEMENTARY) +# define HAVE_PWM_COMPLEMENTARY +#endif + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_pwminitialize + * + * Description: + * Initialize one timer for use with the upper_level PWM driver. + * + * Input Parameters: + * timer - A number identifying the timer use. The number of valid timer + * IDs varies with the STM32 MCU and MCU family but is somewhere in + * the range of {1,..,17}. + * + * Returned Value: + * On success, a pointer to the STM32 lower half PWM driver is returned. + * NULL is returned on any failure. + * + ****************************************************************************/ + +struct pwm_lowerhalf_s *stm32_pwminitialize(int timer); + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ + +#endif /* CONFIG_STM32_TIMx_PWM */ + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_PWM_V3_H */ diff --git a/arch/arm/src/common/stm32/stm32_pwm_m3m4_v1v2v3.c b/arch/arm/src/common/stm32/stm32_pwm_m3m4_v1v2v3.c new file mode 100644 index 0000000000000..17fff3b6e3e7f --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_pwm_m3m4_v1v2v3.c @@ -0,0 +1,4107 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_pwm_m3m4_v1v2v3.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include + +#include +#include + +#include "arm_internal.h" +#include "chip.h" +#include "stm32_pwm.h" +#include "stm32_rcc.h" +#include "stm32_gpio.h" + +/* This module then only compiles if there is at least one enabled timer + * intended for use with the PWM upper half driver. + * + * It implements support for both: + * 1. STM32 TIMER IP version 1 - F0, F1, F2, F37x, F4, L0, L1 + * 2. STM32 TIMER IP version 2 - F3 (no F37x), F7, H7, L4, L4+ + */ + +#ifdef CONFIG_STM32_PWM + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* PWM/Timer Definitions ****************************************************/ + +/* The following definitions are used to identify the various time types. + * There are some differences in timer types across STM32 families: + * - TIM2 is 16-bit timer for F1, L1 and L0 + * - TIM5 is 16-bit timer for F1 + */ + +#define TIMTYPE_BASIC 0 /* Basic timers (no outputs) */ +#define TIMTYPE_GENERAL16 1 /* General 16-bit timers (up, down, up/down)*/ +#define TIMTYPE_COUNTUP16 2 /* General 16-bit count-up timers */ +#define TIMTYPE_COUNTUP16_N 3 /* General 16-bit count-up timers with + * complementary outputs + */ +#define TIMTYPE_GENERAL32 4 /* General 32-bit timers (up, down, up/down)*/ +#define TIMTYPE_ADVANCED 5 /* Advanced timers */ + +#define TIMTYPE_TIM1 TIMTYPE_ADVANCED +#if defined(CONFIG_STM32_STM32L15XX) || defined(CONFIG_STM32_STM32F10XX) +# define TIMTYPE_TIM2 TIMTYPE_GENERAL16 +#else +# define TIMTYPE_TIM2 TIMTYPE_GENERAL32 +#endif +#define TIMTYPE_TIM3 TIMTYPE_GENERAL16 +#define TIMTYPE_TIM4 TIMTYPE_GENERAL16 +#if defined(CONFIG_STM32_STM32F10XX) +# define TIMTYPE_TIM5 TIMTYPE_GENERAL16 +#else +# define TIMTYPE_TIM5 TIMTYPE_GENERAL32 +#endif +#define TIMTYPE_TIM6 TIMTYPE_BASIC +#define TIMTYPE_TIM7 TIMTYPE_BASIC +#define TIMTYPE_TIM8 TIMTYPE_ADVANCED +#define TIMTYPE_TIM9 TIMTYPE_COUNTUP16 +#define TIMTYPE_TIM10 TIMTYPE_COUNTUP16 +#define TIMTYPE_TIM11 TIMTYPE_COUNTUP16 +#define TIMTYPE_TIM12 TIMTYPE_COUNTUP16 +#define TIMTYPE_TIM13 TIMTYPE_COUNTUP16 +#define TIMTYPE_TIM14 TIMTYPE_COUNTUP16 +#define TIMTYPE_TIM15 TIMTYPE_COUNTUP16_N /* Treated as ADVTIM */ +#define TIMTYPE_TIM16 TIMTYPE_COUNTUP16_N /* Treated as ADVTIM */ +#define TIMTYPE_TIM17 TIMTYPE_COUNTUP16_N /* Treated as ADVTIM */ + +/* Timer clock source, RCC EN offset, enable bit, + * RCC RST offset, reset bit to use + * + * TODO: simplify this and move somewhere else. + */ + +#if defined(CONFIG_STM32_STM32F37XX) +# define TIMCLK_TIM2 STM32_APB1_TIM2_CLKIN +# define TIMRCCEN_TIM2 STM32_RCC_APB1ENR +# define TIMEN_TIM2 RCC_APB1ENR_TIM2EN +# define TIMRCCRST_TIM2 STM32_RCC_APB1RSTR +# define TIMRST_TIM2 RCC_APB1RSTR_TIM2RST +# define TIMCLK_TIM3 STM32_APB1_TIM3_CLKIN +# define TIMRCCEN_TIM3 STM32_RCC_APB1ENR +# define TIMEN_TIM3 RCC_APB1ENR_TIM3EN +# define TIMRCCRST_TIM3 STM32_RCC_APB1RSTR +# define TIMRST_TIM3 RCC_APB1RSTR_TIM3RST +# define TIMCLK_TIM4 STM32_APB1_TIM4_CLKIN +# define TIMRCCEN_TIM4 STM32_RCC_APB1ENR +# define TIMEN_TIM4 RCC_APB1ENR_TIM4EN +# define TIMRCCRST_TIM4 STM32_RCC_APB1RSTR +# define TIMRST_TIM4 RCC_APB1RSTR_TIM4RST +# define TIMCLK_TIM5 STM32_APB1_TIM5_CLKIN +# define TIMRCCEN_TIM5 STM32_RCC_APB1ENR +# define TIMEN_TIM5 RCC_APB1ENR_TIM5EN +# define TIMRCCRST_TIM5 STM32_RCC_APB1RSTR +# define TIMRST_TIM5 RCC_APB1RSTR_TIM5RST +# define TIMCLK_TIM6 STM32_APB1_TIM6_CLKIN +# define TIMRCCEN_TIM6 STM32_RCC_APB1ENR +# define TIMEN_TIM6 RCC_APB1ENR_TIM6EN +# define TIMRCCRST_TIM6 STM32_RCC_APB1RSTR +# define TIMRST_TIM6 RCC_APB1RSTR_TIM6RST +# define TIMCLK_TIM7 STM32_APB1_TIM7_CLKIN +# define TIMRCCEN_TIM7 STM32_RCC_APB1ENR +# define TIMEN_TIM7 RCC_APB1ENR_TIM7EN +# define TIMRCCRST_TIM7 STM32_RCC_APB1RSTR +# define TIMRST_TIM7 RCC_APB1RSTR_TIM7RST +# define TIMCLK_TIM12 STM32_APB1_TIM12_CLKIN +# define TIMRCCEN_TIM12 STM32_RCC_APB1ENR +# define TIMEN_TIM12 RCC_APB1ENR_TIM12EN +# define TIMRCCRST_TIM12 STM32_RCC_APB1RSTR +# define TIMRST_TIM12 RCC_APB1RSTR_TIM12RST +# define TIMCLK_TIM13 STM32_APB1_TIM13_CLKIN +# define TIMRCCEN_TIM13 STM32_RCC_APB1ENR +# define TIMEN_TIM13 RCC_APB1ENR_TIM13EN +# define TIMRCCRST_TIM13 STM32_RCC_APB1RSTR +# define TIMRST_TIM13 RCC_APB1RSTR_TIM13RST +# define TIMCLK_TIM14 STM32_APB1_TIM14_CLKIN +# define TIMRCCEN_TIM14 STM32_RCC_APB1ENR +# define TIMEN_TIM14 RCC_APB1ENR_TIM14EN +# define TIMRCCRST_TIM14 STM32_RCC_APB1RSTR +# define TIMRST_TIM14 RCC_APB1RSTR_TIM14RST +# define TIMCLK_TIM15 STM32_APB2_TIM15_CLKIN +# define TIMRCCEN_TIM15 STM32_RCC_APB2ENR +# define TIMEN_TIM15 RCC_APB2ENR_TIM15EN +# define TIMRCCRST_TIM15 STM32_RCC_APB2RSTR +# define TIMRST_TIM15 RCC_APB2RSTR_TIM15RST +# define TIMCLK_TIM16 STM32_APB2_TIM16_CLKIN +# define TIMRCCEN_TIM16 STM32_RCC_APB2ENR +# define TIMEN_TIM16 RCC_APB2ENR_TIM16EN +# define TIMRCCRST_TIM16 STM32_RCC_APB2RSTR +# define TIMRST_TIM16 RCC_APB2RSTR_TIM16RST +# define TIMCLK_TIM17 STM32_APB2_TIM17_CLKIN +# define TIMRCCEN_TIM17 STM32_RCC_APB2ENR +# define TIMEN_TIM17 RCC_APB2ENR_TIM17EN +# define TIMRCCRST_TIM17 STM32_RCC_APB2RSTR +# define TIMRST_TIM17 RCC_APB2RSTR_TIM17RST +# define TIMCLK_TIM18 STM32_APB1_TIM18_CLKIN +# define TIMRCCEN_TIM18 STM32_RCC_APB1ENR +# define TIMEN_TIM18 RCC_APB1ENR_TIM18EN +# define TIMRCCRST_TIM18 STM32_RCC_APB1RSTR +# define TIMRST_TIM18 RCC_APB1RSTR_TIM18RST +# define TIMCLK_TIM19 STM32_APB2_TIM19_CLKIN +# define TIMRCCEN_TIM19 STM32_RCC_APB2ENR +# define TIMEN_TIM19 RCC_APB2ENR_TIM19EN +# define TIMRCCRST_TIM19 STM32_RCC_APB2RSTR +# define TIMRST_TIM19 RCC_APB2RSTR_TIM19RST +#else +# define TIMCLK_TIM1 STM32_APB2_TIM1_CLKIN +# define TIMRCCEN_TIM1 STM32_RCC_APB2ENR +# define TIMEN_TIM1 RCC_APB2ENR_TIM1EN +# define TIMRCCRST_TIM1 STM32_RCC_APB2RSTR +# define TIMRST_TIM1 RCC_APB2RSTR_TIM1RST +# define TIMCLK_TIM2 STM32_APB1_TIM2_CLKIN +# define TIMRCCEN_TIM2 STM32_RCC_APB1ENR +# define TIMEN_TIM2 RCC_APB1ENR_TIM2EN +# define TIMRCCRST_TIM2 STM32_RCC_APB1RSTR +# define TIMRST_TIM2 RCC_APB1RSTR_TIM2RST +# define TIMCLK_TIM3 STM32_APB1_TIM3_CLKIN +# define TIMRCCEN_TIM3 STM32_RCC_APB1ENR +# define TIMEN_TIM3 RCC_APB1ENR_TIM3EN +# define TIMRCCRST_TIM3 STM32_RCC_APB1RSTR +# define TIMRST_TIM3 RCC_APB1RSTR_TIM3RST +# define TIMCLK_TIM4 STM32_APB1_TIM4_CLKIN +# define TIMRCCEN_TIM4 STM32_RCC_APB1ENR +# define TIMEN_TIM4 RCC_APB1ENR_TIM4EN +# define TIMRCCRST_TIM4 STM32_RCC_APB1RSTR +# define TIMRST_TIM4 RCC_APB1RSTR_TIM4RST +# define TIMCLK_TIM5 STM32_APB1_TIM5_CLKIN +# define TIMRCCEN_TIM5 STM32_RCC_APB1ENR +# define TIMEN_TIM5 RCC_APB1ENR_TIM5EN +# define TIMRCCRST_TIM5 STM32_RCC_APB1RSTR +# define TIMRST_TIM5 RCC_APB1RSTR_TIM5RST +# define TIMCLK_TIM8 STM32_APB2_TIM8_CLKIN +# define TIMRCCEN_TIM8 STM32_RCC_APB2ENR +# define TIMEN_TIM8 RCC_APB2ENR_TIM8EN +# define TIMRCCRST_TIM8 STM32_RCC_APB2RSTR +# define TIMRST_TIM8 RCC_APB2RSTR_TIM8RST +# define TIMCLK_TIM9 STM32_APB2_TIM9_CLKIN +# define TIMRCCEN_TIM9 STM32_RCC_APB2ENR +# define TIMEN_TIM9 RCC_APB2ENR_TIM9EN +# define TIMRCCRST_TIM9 STM32_RCC_APB2RSTR +# define TIMRST_TIM9 RCC_APB2RSTR_TIM9RST +# define TIMCLK_TIM10 STM32_APB2_TIM10_CLKIN +# define TIMRCCEN_TIM10 STM32_RCC_APB2ENR +# define TIMEN_TIM10 RCC_APB2ENR_TIM10EN +# define TIMRCCRST_TIM10 STM32_RCC_APB2RSTR +# define TIMRST_TIM10 RCC_APB2RSTR_TIM10RST +# define TIMCLK_TIM11 STM32_APB2_TIM11_CLKIN +# define TIMRCCEN_TIM11 STM32_RCC_APB2ENR +# define TIMEN_TIM11 RCC_APB2ENR_TIM11EN +# define TIMRCCRST_TIM11 STM32_RCC_APB2RSTR +# define TIMRST_TIM11 RCC_APB2RSTR_TIM11RST +# define TIMCLK_TIM12 STM32_APB1_TIM12_CLKIN +# define TIMRCCEN_TIM12 STM32_RCC_APB1ENR +# define TIMEN_TIM12 RCC_APB1ENR_TIM12EN +# define TIMRCCRST_TIM12 STM32_RCC_APB1RSTR +# define TIMRST_TIM12 RCC_APB1RSTR_TIM12RST +# define TIMCLK_TIM13 STM32_APB1_TIM13_CLKIN +# define TIMRCCEN_TIM13 STM32_RCC_APB1ENR +# define TIMEN_TIM13 RCC_APB1ENR_TIM13EN +# define TIMRCCRST_TIM13 STM32_RCC_APB1RSTR +# define TIMRST_TIM13 RCC_APB1RSTR_TIM13RST +# define TIMCLK_TIM14 STM32_APB1_TIM14_CLKIN +# define TIMRCCEN_TIM14 STM32_RCC_APB1ENR +# define TIMEN_TIM14 RCC_APB1ENR_TIM14EN +# define TIMRCCRST_TIM14 STM32_RCC_APB1RSTR +# define TIMRST_TIM14 RCC_APB1RSTR_TIM14RST +# define TIMCLK_TIM15 STM32_APB1_TIM15_CLKIN +# define TIMRCCEN_TIM15 STM32_RCC_APB1ENR +# define TIMEN_TIM15 RCC_APB1ENR_TIM15EN +# define TIMRCCRST_TIM15 STM32_RCC_APB1RSTR +# define TIMRST_TIM15 RCC_APB1RSTR_TIM15RST +# define TIMCLK_TIM16 STM32_APB1_TIM16_CLKIN +# define TIMRCCEN_TIM16 STM32_RCC_APB1ENR +# define TIMEN_TIM16 RCC_APB1ENR_TIM16EN +# define TIMRCCRST_TIM16 STM32_RCC_APB1RSTR +# define TIMRST_TIM16 RCC_APB1RSTR_TIM16RST +# define TIMCLK_TIM17 STM32_APB1_TIM17_CLKIN +# define TIMRCCEN_TIM17 STM32_RCC_APB1ENR +# define TIMEN_TIM17 RCC_APB1ENR_TIM17EN +# define TIMRCCRST_TIM17 STM32_RCC_APB1RSTR +# define TIMRST_TIM17 RCC_APB1RSTR_TIM17RST +#endif + +/* Default GPIO pins state */ + +#if defined(CONFIG_STM32_STM32F10XX) +# define PINCFG_DEFAULT (GPIO_INPUT | GPIO_CNF_INFLOAT | GPIO_MODE_INPUT) +#elif defined(CONFIG_STM32_STM32F20XX) || \ + defined(CONFIG_STM32_STM32F30XX) || \ + defined(CONFIG_STM32_STM32F33XX) || \ + defined(CONFIG_STM32_STM32F37XX) || \ + defined(CONFIG_STM32_STM32F4XXX) || \ + defined(CONFIG_STM32_STM32L15XX) || \ + defined(CONFIG_STM32_STM32G4XXX) +# define PINCFG_DEFAULT (GPIO_INPUT | GPIO_FLOAT) +#else +# error "Unrecognized STM32 chip" +#endif + +/* Advanced Timer support + * NOTE: TIM15-17 are not ADVTIM but they support most of the + * ADVTIM functionality. The main difference is the number of + * supported capture/compare. + */ + +#if defined(CONFIG_STM32_TIM1_PWM) || defined(CONFIG_STM32_TIM8_PWM) || \ + defined(CONFIG_STM32_TIM15_PWM) || defined(CONFIG_STM32_TIM16_PWM) || \ + defined(CONFIG_STM32_TIM17_PWM) +# define HAVE_ADVTIM +#else +# undef HAVE_ADVTIM +#endif + +/* TRGO/TRGO2 support */ + +#ifdef CONFIG_STM32_PWM_TRGO +# define HAVE_TRGO +#endif + +/* Break support */ + +#if defined(CONFIG_STM32_TIM1_BREAK1) || defined(CONFIG_STM32_TIM1_BREAK2) || \ + defined(CONFIG_STM32_TIM8_BREAK1) || defined(CONFIG_STM32_TIM8_BREAK2) || \ + defined(CONFIG_STM32_TIM15_BREAK1) || defined(CONFIG_STM32_TIM16_BREAK1) || \ + defined(CONFIG_STM32_TIM17_BREAK1) +# defined HAVE_BREAK +#endif + +/* Debug ********************************************************************/ + +#ifdef CONFIG_DEBUG_PWM_INFO +# define pwm_dumpgpio(p,m) stm32_dumpgpio(p,m) +#else +# define pwm_dumpgpio(p,m) +#endif + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/* PWM output configuration */ + +struct stm32_pwm_out_s +{ + uint8_t in_use:1; /* Output in use */ + uint8_t pol:1; /* Polarity. Default: positive */ + uint8_t idle:1; /* Idle state. Default: inactive */ + uint8_t _res:5; /* Reserved */ + uint32_t pincfg; /* Output pin configuration */ +}; + +/* PWM break configuration */ + +#ifdef HAVE_BREAK +struct stm32_pwm_break_s +{ + uint8_t en1:1; /* Break 1 enable */ + uint8_t pol1:1; /* Break 1 polarity */ + uint8_t _res:6; /* Reserved */ +#ifdef HAVE_IP_TIMERS_V2 + uint8_t en2:1; /* Break 2 enable */ + uint8_t pol2:1; /* Break 2 polarity */ + uint8_t flt2:6; /* Break 2 filter */ +#endif +}; +#endif + +/* PWM channel configuration */ + +struct stm32_pwmchan_s +{ + uint8_t channel:4; /* Timer output channel: {1,..4} */ + uint8_t mode:4; /* PWM channel mode (see stm32_pwm_chanmode_e) */ + struct stm32_pwm_out_s out1; /* PWM output configuration */ +#ifdef HAVE_BREAK + struct stm32_pwm_break_s brk; /* PWM break configuration */ +#endif +#ifdef HAVE_PWM_COMPLEMENTARY + struct stm32_pwm_out_s out2; /* PWM complementary output configuration */ +#endif +}; + +/* This structure represents the state of one PWM timer */ + +struct stm32_pwmtimer_s +{ + const struct pwm_ops_s *ops; /* PWM operations */ +#ifdef CONFIG_STM32_PWM_LL_OPS + const struct stm32_pwm_ops_s *llops; /* Low-level PWM ops */ +#endif + struct stm32_pwmchan_s *channels; /* Channels configuration */ + uint8_t timid:5; /* Timer ID {1,...,17} */ + uint8_t chan_num:3; /* Number of configured channels */ + uint8_t timtype:3; /* See the TIMTYPE_* definitions */ + uint8_t mode:3; /* Timer mode (see stm32_pwm_tim_mode_e) */ + uint8_t lock:2; /* Lock configuration */ + uint8_t t_dts:3; /* Clock division for t_DTS */ + uint8_t _res:5; /* Reserved */ +#ifdef HAVE_PWM_COMPLEMENTARY + uint8_t deadtime; /* Dead-time value */ +#endif +#ifdef HAVE_TRGO + uint8_t trgo; /* TRGO configuration: + * 4 LSB = TRGO, 4 MSB = TRGO2 + */ +#endif + uint32_t frequency; /* Current frequency setting */ + uint32_t base; /* The base address of the timer */ + uint32_t pclk; /* The frequency of the peripheral + * clock that drives the timer module + */ +}; + +/**************************************************************************** + * Static Function Prototypes + ****************************************************************************/ + +/* Register access */ + +static uint32_t pwm_getreg(struct stm32_pwmtimer_s *priv, int offset); +static void pwm_putreg(struct stm32_pwmtimer_s *priv, int offset, + uint32_t value); +static void pwm_modifyreg(struct stm32_pwmtimer_s *priv, uint32_t offset, + uint32_t clearbits, uint32_t setbits); + +#ifdef CONFIG_DEBUG_PWM_INFO +static void pwm_dumpregs(struct pwm_lowerhalf_s *dev, + const char *msg); +#else +# define pwm_dumpregs(priv,msg) +#endif + +/* Timer management */ + +static int pwm_frequency_update(struct pwm_lowerhalf_s *dev, + uint32_t frequency); +static int pwm_mode_configure(struct pwm_lowerhalf_s *dev, + uint8_t channel, uint32_t mode); +static int pwm_timer_configure(struct stm32_pwmtimer_s *priv); +static int pwm_output_configure(struct stm32_pwmtimer_s *priv, + struct stm32_pwmchan_s *chan); +static int pwm_outputs_enable(struct pwm_lowerhalf_s *dev, + uint16_t outputs, bool state); +static int pwm_soft_update(struct pwm_lowerhalf_s *dev); +static int pwm_soft_break(struct pwm_lowerhalf_s *dev, bool state); +static int pwm_ccr_update(struct pwm_lowerhalf_s *dev, uint8_t index, + uint32_t ccr); +static int pwm_arr_update(struct pwm_lowerhalf_s *dev, uint32_t arr); +static uint32_t pwm_arr_get(struct pwm_lowerhalf_s *dev); +static int pwm_duty_update(struct pwm_lowerhalf_s *dev, uint8_t channel, + ub16_t duty); +static int pwm_timer_enable(struct pwm_lowerhalf_s *dev, bool state); + +#ifdef HAVE_ADVTIM +static int pwm_break_dt_configure(struct stm32_pwmtimer_s *priv); +#endif +#ifdef HAVE_TRGO +static int pwm_trgo_configure(struct pwm_lowerhalf_s *dev, + uint8_t trgo); +#endif +#if defined(HAVE_PWM_COMPLEMENTARY) && defined(CONFIG_STM32_PWM_LL_OPS) +static int pwm_deadtime_update(struct pwm_lowerhalf_s *dev, uint8_t dt); +#endif +#ifdef CONFIG_STM32_PWM_LL_OPS +static uint32_t pwm_ccr_get(struct pwm_lowerhalf_s *dev, uint8_t index); +static uint16_t pwm_rcr_get(struct pwm_lowerhalf_s *dev); +#endif +#ifdef HAVE_ADVTIM +static int pwm_rcr_update(struct pwm_lowerhalf_s *dev, uint16_t rcr); +#endif + +static int pwm_configure(struct pwm_lowerhalf_s *dev); +static int pwm_timer(struct pwm_lowerhalf_s *dev, + const struct pwm_info_s *info); + +/* PWM driver methods */ + +static int pwm_setup(struct pwm_lowerhalf_s *dev); +static int pwm_shutdown(struct pwm_lowerhalf_s *dev); + +static int pwm_start(struct pwm_lowerhalf_s *dev, + const struct pwm_info_s *info); + +static int pwm_stop(struct pwm_lowerhalf_s *dev); +static int pwm_ioctl(struct pwm_lowerhalf_s *dev, + int cmd, unsigned long arg); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* This is the list of lower half PWM driver methods used by the upper half + * driver. + */ + +static const struct pwm_ops_s g_pwmops = +{ + .setup = pwm_setup, + .shutdown = pwm_shutdown, + .start = pwm_start, + .stop = pwm_stop, + .ioctl = pwm_ioctl, +}; + +#ifdef CONFIG_STM32_PWM_LL_OPS +static const struct stm32_pwm_ops_s g_llpwmops = +{ + .configure = pwm_configure, + .soft_break = pwm_soft_break, + .ccr_update = pwm_ccr_update, + .mode_update = pwm_mode_configure, + .ccr_get = pwm_ccr_get, + .arr_update = pwm_arr_update, + .arr_get = pwm_arr_get, +#ifdef HAVE_ADVTIM + .rcr_update = pwm_rcr_update, +#endif + .rcr_get = pwm_rcr_get, +#ifdef HAVE_TRGO + .trgo_set = pwm_trgo_configure, +#endif + .outputs_enable = pwm_outputs_enable, + .soft_update = pwm_soft_update, + .freq_update = pwm_frequency_update, + .tim_enable = pwm_timer_enable, +# ifdef CONFIG_DEBUG_PWM_INFO + .dump_regs = pwm_dumpregs, +# endif +# ifdef HAVE_PWM_COMPLEMENTARY + .dt_update = pwm_deadtime_update, +# endif +}; +#endif + +#ifdef CONFIG_STM32_TIM1_PWM + +static struct stm32_pwmchan_s g_pwm1channels[] = +{ + /* TIM1 has 4 channels, 4 complementary */ + +#ifdef CONFIG_STM32_TIM1_CHANNEL1 + { + .channel = 1, + .mode = CONFIG_STM32_TIM1_CH1MODE, +#ifdef HAVE_BREAK + .brk = + { +#ifdef CONFIG_STM32_TIM1_BREAK1 + .en1 = 1, + .pol1 = CONFIG_STM32_TIM1_BRK1POL, +#endif +#ifdef CONFIG_STM32_TIM1_BREAK2 + .en2 = 1, + .pol2 = CONFIG_STM32_TIM1_BRK2POL, + .flt2 = CONFIG_STM32_TIM1_BRK2FLT, +#endif + }, +#endif +#ifdef CONFIG_STM32_TIM1_CH1OUT + .out1 = + { + .in_use = 1, + .pol = CONFIG_STM32_TIM1_CH1POL, + .idle = CONFIG_STM32_TIM1_CH1IDLE, + .pincfg = PWM_TIM1_CH1CFG, + }, +#endif +#ifdef CONFIG_STM32_TIM1_CH1NOUT + .out2 = + { + .in_use = 1, + .pol = CONFIG_STM32_TIM1_CH1NPOL, + .idle = CONFIG_STM32_TIM1_CH1NIDLE, + .pincfg = PWM_TIM1_CH1NCFG, + } +#endif + }, +#endif +#ifdef CONFIG_STM32_TIM1_CHANNEL2 + { + .channel = 2, + .mode = CONFIG_STM32_TIM1_CH2MODE, +#ifdef CONFIG_STM32_TIM1_CH2OUT + .out1 = + { + .in_use = 1, + .pol = CONFIG_STM32_TIM1_CH2POL, + .idle = CONFIG_STM32_TIM1_CH2IDLE, + .pincfg = PWM_TIM1_CH2CFG, + }, +#endif +#ifdef CONFIG_STM32_TIM1_CH2NOUT + .out2 = + { + .in_use = 1, + .pol = CONFIG_STM32_TIM1_CH2NPOL, + .idle = CONFIG_STM32_TIM1_CH2NIDLE, + .pincfg = PWM_TIM1_CH2NCFG, + } +#endif + }, +#endif +#ifdef CONFIG_STM32_TIM1_CHANNEL3 + { + .channel = 3, + .mode = CONFIG_STM32_TIM1_CH3MODE, +#ifdef CONFIG_STM32_TIM1_CH3OUT + .out1 = + { + .in_use = 1, + .pol = CONFIG_STM32_TIM1_CH3POL, + .idle = CONFIG_STM32_TIM1_CH3IDLE, + .pincfg = PWM_TIM1_CH3CFG, + }, +#endif +#ifdef CONFIG_STM32_TIM1_CH3NOUT + .out2 = + { + .in_use = 1, + .pol = CONFIG_STM32_TIM1_CH3NPOL, + .idle = CONFIG_STM32_TIM1_CH3NIDLE, + .pincfg = PWM_TIM1_CH3NCFG, + } +#endif + }, +#endif +#ifdef CONFIG_STM32_TIM1_CHANNEL4 + { + .channel = 4, + .mode = CONFIG_STM32_TIM1_CH4MODE, +#ifdef CONFIG_STM32_TIM1_CH4OUT + .out1 = + { + .in_use = 1, + .pol = CONFIG_STM32_TIM1_CH4POL, + .idle = CONFIG_STM32_TIM1_CH4IDLE, + .pincfg = PWM_TIM1_CH4CFG, + } +#endif + }, +#endif +#ifdef CONFIG_STM32_TIM1_CHANNEL5 + { + .channel = 5, + .mode = CONFIG_STM32_TIM1_CH5MODE, +#ifdef CONFIG_STM32_TIM1_CH5OUT + .out1 = + { + .in_use = 1, + .pol = CONFIG_STM32_TIM1_CH5POL, + .idle = CONFIG_STM32_TIM1_CH5IDLE, + .pincfg = 0, /* Not available externally */ + } +#endif + }, +#endif +#ifdef CONFIG_STM32_TIM1_CHANNEL6 + { + .channel = 6, + .mode = CONFIG_STM32_TIM1_CH6MODE, +#ifdef CONFIG_STM32_TIM1_CH6OUT + .out1 = + { + .in_use = 1, + .pol = CONFIG_STM32_TIM1_CH6POL, + .idle = CONFIG_STM32_TIM1_CH6IDLE, + .pincfg = 0, /* Not available externally */ + } +#endif + } +#endif +}; + +static struct stm32_pwmtimer_s g_pwm1dev = +{ + .ops = &g_pwmops, +#ifdef CONFIG_STM32_PWM_LL_OPS + .llops = &g_llpwmops, +#endif + .timid = 1, + .chan_num = PWM_TIM1_NCHANNELS, + .channels = g_pwm1channels, + .timtype = TIMTYPE_TIM1, + .mode = CONFIG_STM32_TIM1_MODE, + .lock = CONFIG_STM32_TIM1_LOCK, + .t_dts = CONFIG_STM32_TIM1_TDTS, +#ifdef HAVE_PWM_COMPLEMENTARY + .deadtime = CONFIG_STM32_TIM1_DEADTIME, +#endif +#if defined(HAVE_TRGO) && defined(STM32_TIM1_TRGO) + .trgo = STM32_TIM1_TRGO, +#endif + .base = STM32_TIM1_BASE, + .pclk = TIMCLK_TIM1, +}; +#endif /* CONFIG_STM32_TIM1_PWM */ + +#ifdef CONFIG_STM32_TIM2_PWM + +static struct stm32_pwmchan_s g_pwm2channels[] = +{ + /* TIM2 has 4 channels */ + +#ifdef CONFIG_STM32_TIM2_CHANNEL1 + { + .channel = 1, + .mode = CONFIG_STM32_TIM2_CH1MODE, +#ifdef CONFIG_STM32_TIM2_CH1OUT + .out1 = + { + .in_use = 1, + .pol = CONFIG_STM32_TIM2_CH1POL, + .idle = CONFIG_STM32_TIM2_CH1IDLE, + .pincfg = PWM_TIM2_CH1CFG, + } +#endif + /* No complementary outputs */ + }, +#endif +#ifdef CONFIG_STM32_TIM2_CHANNEL2 + { + .channel = 2, + .mode = CONFIG_STM32_TIM2_CH2MODE, +#ifdef CONFIG_STM32_TIM2_CH2OUT + .out1 = + { + .in_use = 1, + .pol = CONFIG_STM32_TIM2_CH2POL, + .idle = CONFIG_STM32_TIM2_CH2IDLE, + .pincfg = PWM_TIM2_CH2CFG, + } +#endif + /* No complementary outputs */ + }, +#endif +#ifdef CONFIG_STM32_TIM2_CHANNEL3 + { + .channel = 3, + .mode = CONFIG_STM32_TIM2_CH3MODE, +#ifdef CONFIG_STM32_TIM2_CH3OUT + .out1 = + { + .in_use = 1, + .pol = CONFIG_STM32_TIM2_CH3POL, + .idle = CONFIG_STM32_TIM2_CH3IDLE, + .pincfg = PWM_TIM2_CH3CFG, + } +#endif + /* No complementary outputs */ + }, +#endif +#ifdef CONFIG_STM32_TIM2_CHANNEL4 + { + .channel = 4, + .mode = CONFIG_STM32_TIM2_CH4MODE, +#ifdef CONFIG_STM32_TIM2_CH4OUT + .out1 = + { + .in_use = 1, + .pol = CONFIG_STM32_TIM2_CH4POL, + .idle = CONFIG_STM32_TIM2_CH4IDLE, + .pincfg = PWM_TIM2_CH4CFG, + } +#endif + /* No complementary outputs */ + } +#endif +}; + +static struct stm32_pwmtimer_s g_pwm2dev = +{ + .ops = &g_pwmops, +#ifdef CONFIG_STM32_PWM_LL_OPS + .llops = &g_llpwmops, +#endif + .timid = 2, + .chan_num = PWM_TIM2_NCHANNELS, + .channels = g_pwm2channels, + .timtype = TIMTYPE_TIM2, + .mode = CONFIG_STM32_TIM2_MODE, + .lock = 0, /* No lock */ + .t_dts = 0, /* No t_dts */ +#ifdef HAVE_PWM_COMPLEMENTARY + .deadtime = 0, /* No deadtime */ +#endif +#if defined(HAVE_TRGO) && defined(STM32_TIM2_TRGO) + .trgo = STM32_TIM2_TRGO, +#endif + .base = STM32_TIM2_BASE, + .pclk = TIMCLK_TIM2, +}; +#endif /* CONFIG_STM32_TIM2_PWM */ + +#ifdef CONFIG_STM32_TIM3_PWM + +static struct stm32_pwmchan_s g_pwm3channels[] = +{ + /* TIM3 has 4 channels */ + +#ifdef CONFIG_STM32_TIM3_CHANNEL1 + { + .channel = 1, + .mode = CONFIG_STM32_TIM3_CH1MODE, +#ifdef CONFIG_STM32_TIM3_CH1OUT + .out1 = + { + .in_use = 1, + .pol = CONFIG_STM32_TIM3_CH1POL, + .idle = CONFIG_STM32_TIM3_CH1IDLE, + .pincfg = PWM_TIM3_CH1CFG, + } +#endif + /* No complementary outputs */ + }, +#endif +#ifdef CONFIG_STM32_TIM3_CHANNEL2 + { + .channel = 2, + .mode = CONFIG_STM32_TIM3_CH2MODE, +#ifdef CONFIG_STM32_TIM3_CH2OUT + .out1 = + { + .in_use = 1, + .pol = CONFIG_STM32_TIM3_CH2POL, + .idle = CONFIG_STM32_TIM3_CH2IDLE, + .pincfg = PWM_TIM3_CH2CFG, + } +#endif + /* No complementary outputs */ + }, +#endif +#ifdef CONFIG_STM32_TIM3_CHANNEL3 + { + .channel = 3, + .mode = CONFIG_STM32_TIM3_CH3MODE, +#ifdef CONFIG_STM32_TIM3_CH3OUT + .out1 = + { + .in_use = 1, + .pol = CONFIG_STM32_TIM3_CH3POL, + .idle = CONFIG_STM32_TIM3_CH3IDLE, + .pincfg = PWM_TIM3_CH3CFG, + } +#endif + /* No complementary outputs */ + }, +#endif +#ifdef CONFIG_STM32_TIM3_CHANNEL4 + { + .channel = 4, + .mode = CONFIG_STM32_TIM3_CH4MODE, +#ifdef CONFIG_STM32_TIM3_CH4OUT + .out1 = + { + .in_use = 1, + .pol = CONFIG_STM32_TIM3_CH4POL, + .idle = CONFIG_STM32_TIM3_CH4IDLE, + .pincfg = PWM_TIM3_CH4CFG, + } +#endif + /* No complementary outputs */ + } +#endif +}; + +static struct stm32_pwmtimer_s g_pwm3dev = +{ + .ops = &g_pwmops, +#ifdef CONFIG_STM32_PWM_LL_OPS + .llops = &g_llpwmops, +#endif + .timid = 3, + .chan_num = PWM_TIM3_NCHANNELS, + .channels = g_pwm3channels, + .timtype = TIMTYPE_TIM3, + .mode = CONFIG_STM32_TIM3_MODE, + .lock = 0, /* No lock */ + .t_dts = 0, /* No t_dts */ +#ifdef HAVE_PWM_COMPLEMENTARY + .deadtime = 0, /* No deadtime */ +#endif +#if defined(HAVE_TRGO) && defined(STM32_TIM3_TRGO) + .trgo = STM32_TIM3_TRGO, +#endif + .base = STM32_TIM3_BASE, + .pclk = TIMCLK_TIM3, +}; +#endif /* CONFIG_STM32_TIM3_PWM */ + +#ifdef CONFIG_STM32_TIM4_PWM + +static struct stm32_pwmchan_s g_pwm4channels[] = +{ + /* TIM4 has 4 channels */ + +#ifdef CONFIG_STM32_TIM4_CHANNEL1 + { + .channel = 1, + .mode = CONFIG_STM32_TIM4_CH1MODE, +#ifdef CONFIG_STM32_TIM4_CH1OUT + .out1 = + { + .in_use = 1, + .pol = CONFIG_STM32_TIM4_CH1POL, + .idle = CONFIG_STM32_TIM4_CH1IDLE, + .pincfg = PWM_TIM4_CH1CFG, + } +#endif + /* No complementary outputs */ + }, +#endif +#ifdef CONFIG_STM32_TIM4_CHANNEL2 + { + .channel = 2, + .mode = CONFIG_STM32_TIM4_CH2MODE, +#ifdef CONFIG_STM32_TIM4_CH2OUT + .out1 = + { + .in_use = 1, + .pol = CONFIG_STM32_TIM4_CH2POL, + .idle = CONFIG_STM32_TIM4_CH2IDLE, + .pincfg = PWM_TIM4_CH2CFG, + } +#endif + /* No complementary outputs */ + }, +#endif +#ifdef CONFIG_STM32_TIM4_CHANNEL3 + { + .channel = 3, + .mode = CONFIG_STM32_TIM4_CH3MODE, +#ifdef CONFIG_STM32_TIM4_CH3OUT + .out1 = + { + .in_use = 1, + .pol = CONFIG_STM32_TIM4_CH3POL, + .idle = CONFIG_STM32_TIM4_CH3IDLE, + .pincfg = PWM_TIM4_CH3CFG, + } +#endif + /* No complementary outputs */ + }, +#endif +#ifdef CONFIG_STM32_TIM4_CHANNEL4 + { + .channel = 4, + .mode = CONFIG_STM32_TIM4_CH4MODE, +#ifdef CONFIG_STM32_TIM4_CH4OUT + .out1 = + { + .in_use = 1, + .pol = CONFIG_STM32_TIM4_CH4POL, + .idle = CONFIG_STM32_TIM4_CH4IDLE, + .pincfg = PWM_TIM4_CH4CFG, + } +#endif + /* No complementary outputs */ + } +#endif +}; + +static struct stm32_pwmtimer_s g_pwm4dev = +{ + .ops = &g_pwmops, +#ifdef CONFIG_STM32_PWM_LL_OPS + .llops = &g_llpwmops, +#endif + .timid = 4, + .chan_num = PWM_TIM4_NCHANNELS, + .channels = g_pwm4channels, + .timtype = TIMTYPE_TIM4, + .mode = CONFIG_STM32_TIM4_MODE, + .lock = 0, /* No lock */ + .t_dts = 0, /* No t_dts */ +#ifdef HAVE_PWM_COMPLEMENTARY + .deadtime = 0, /* No deadtime */ +#endif +#if defined(HAVE_TRGO) && defined(STM32_TIM4_TRGO) + .trgo = STM32_TIM4_TRGO, +#endif + .base = STM32_TIM4_BASE, + .pclk = TIMCLK_TIM4, +}; +#endif /* CONFIG_STM32_TIM4_PWM */ + +#ifdef CONFIG_STM32_TIM5_PWM + +static struct stm32_pwmchan_s g_pwm5channels[] = +{ + /* TIM5 has 4 channels */ + +#ifdef CONFIG_STM32_TIM5_CHANNEL1 + { + .channel = 1, + .mode = CONFIG_STM32_TIM5_CH1MODE, +#ifdef CONFIG_STM32_TIM5_CH1OUT + .out1 = + { + .in_use = 1, + .pol = CONFIG_STM32_TIM5_CH1POL, + .idle = CONFIG_STM32_TIM5_CH1IDLE, + .pincfg = PWM_TIM5_CH1CFG, + } +#endif + /* No complementary outputs */ + }, +#endif +#ifdef CONFIG_STM32_TIM5_CHANNEL2 + { + .channel = 2, + .mode = CONFIG_STM32_TIM5_CH2MODE, +#ifdef CONFIG_STM32_TIM5_CH2OUT + .out1 = + { + .in_use = 1, + .pol = CONFIG_STM32_TIM5_CH2POL, + .idle = CONFIG_STM32_TIM5_CH2IDLE, + .pincfg = PWM_TIM5_CH2CFG, + } +#endif + /* No complementary outputs */ + }, +#endif +#ifdef CONFIG_STM32_TIM5_CHANNEL3 + { + .channel = 3, + .mode = CONFIG_STM32_TIM5_CH3MODE, +#ifdef CONFIG_STM32_TIM5_CH3OUT + .out1 = + { + .in_use = 1, + .pol = CONFIG_STM32_TIM5_CH3POL, + .idle = CONFIG_STM32_TIM5_CH3IDLE, + .pincfg = PWM_TIM5_CH3CFG, + } +#endif + }, +#endif +#ifdef CONFIG_STM32_TIM5_CHANNEL4 + { + .channel = 4, + .mode = CONFIG_STM32_TIM5_CH4MODE, +#ifdef CONFIG_STM32_TIM5_CH4OUT + .out1 = + { + .in_use = 1, + .pol = CONFIG_STM32_TIM5_CH4POL, + .idle = CONFIG_STM32_TIM5_CH4IDLE, + .pincfg = PWM_TIM5_CH4CFG, + } +#endif + }, +#endif +}; + +static struct stm32_pwmtimer_s g_pwm5dev = +{ + .ops = &g_pwmops, +#ifdef CONFIG_STM32_PWM_LL_OPS + .llops = &g_llpwmops, +#endif + .timid = 5, + .chan_num = PWM_TIM5_NCHANNELS, + .channels = g_pwm5channels, + .timtype = TIMTYPE_TIM5, + .mode = CONFIG_STM32_TIM5_MODE, + .lock = 0, /* No lock */ + .t_dts = 0, /* No t_dts */ +#ifdef HAVE_PWM_COMPLEMENTARY + .deadtime = 0, /* No deadtime */ +#endif +#if defined(HAVE_TRGO) && defined(STM32_TIM5_TRGO) + .trgo = STM32_TIM5_TRGO, +#endif + .base = STM32_TIM5_BASE, + .pclk = TIMCLK_TIM5, +}; +#endif /* CONFIG_STM32_TIM5_PWM */ + +#ifdef CONFIG_STM32_TIM8_PWM + +static struct stm32_pwmchan_s g_pwm8channels[] = +{ + /* TIM8 has 4 channels, 4 complementary */ + +#ifdef CONFIG_STM32_TIM8_CHANNEL1 + { + .channel = 1, + .mode = CONFIG_STM32_TIM8_CH1MODE, +#ifdef HAVE_BREAK + .brk = + { +#ifdef CONFIG_STM32_TIM8_BREAK1 + .en1 = 1, + .pol1 = CONFIG_STM32_TIM8_BRK1POL, +#endif +#ifdef CONFIG_STM32_TIM8_BREAK2 + .en2 = 1, + .pol2 = CONFIG_STM32_TIM8_BRK2POL, + .flt2 = CONFIG_STM32_TIM8_BRK2FLT, +#endif + }, +#endif +#ifdef CONFIG_STM32_TIM8_CH1OUT + .out1 = + { + .in_use = 1, + .pol = CONFIG_STM32_TIM8_CH1POL, + .idle = CONFIG_STM32_TIM8_CH1IDLE, + .pincfg = PWM_TIM8_CH1CFG, + }, +#endif +#ifdef CONFIG_STM32_TIM8_CH1NOUT + .out2 = + { + .in_use = 1, + .pol = CONFIG_STM32_TIM8_CH1NPOL, + .idle = CONFIG_STM32_TIM8_CH1NIDLE, + .pincfg = PWM_TIM8_CH1NCFG, + } +#endif + }, +#endif +#ifdef CONFIG_STM32_TIM8_CHANNEL2 + { + .channel = 2, + .mode = CONFIG_STM32_TIM8_CH2MODE, +#ifdef CONFIG_STM32_TIM8_CH2OUT + .out1 = + { + .in_use = 1, + .pol = CONFIG_STM32_TIM8_CH2POL, + .idle = CONFIG_STM32_TIM8_CH2IDLE, + .pincfg = PWM_TIM8_CH2CFG, + }, +#endif +#ifdef CONFIG_STM32_TIM8_CH2NOUT + .out2 = + { + .in_use = 1, + .pol = CONFIG_STM32_TIM8_CH2NPOL, + .idle = CONFIG_STM32_TIM8_CH2NIDLE, + .pincfg = PWM_TIM8_CH2NCFG, + } +#endif + }, +#endif +#ifdef CONFIG_STM32_TIM8_CHANNEL3 + { + .channel = 3, + .mode = CONFIG_STM32_TIM8_CH3MODE, +#ifdef CONFIG_STM32_TIM8_CH3OUT + .out1 = + { + .in_use = 1, + .pol = CONFIG_STM32_TIM8_CH3POL, + .idle = CONFIG_STM32_TIM8_CH3IDLE, + .pincfg = PWM_TIM8_CH3CFG, + }, +#endif +#ifdef CONFIG_STM32_TIM8_CH3NOUT + .out2 = + { + .in_use = 1, + .pol = CONFIG_STM32_TIM8_CH3NPOL, + .idle = CONFIG_STM32_TIM8_CH3NIDLE, + .pincfg = PWM_TIM8_CH3NCFG, + } +#endif + }, +#endif +#ifdef CONFIG_STM32_TIM8_CHANNEL4 + { + .channel = 4, + .mode = CONFIG_STM32_TIM8_CH4MODE, +#ifdef CONFIG_STM32_TIM8_CH4OUT + .out1 = + { + .in_use = 1, + .pol = CONFIG_STM32_TIM8_CH4POL, + .idle = CONFIG_STM32_TIM8_CH4IDLE, + .pincfg = PWM_TIM8_CH4CFG, + } +#endif + }, +#endif +#ifdef CONFIG_STM32_TIM8_CHANNEL5 + { + .channel = 5, + .mode = CONFIG_STM32_TIM8_CH5MODE, +#ifdef CONFIG_STM32_TIM8_CH5OUT + .out1 = + { + .in_use = 1, + .pol = CONFIG_STM32_TIM8_CH5POL, + .idle = CONFIG_STM32_TIM8_CH5IDLE, + .pincfg = 0, /* Not available externally */ + } +#endif + }, +#endif +#ifdef CONFIG_STM32_TIM8_CHANNEL6 + { + .channel = 6, + .mode = CONFIG_STM32_TIM8_CH6MODE, +#ifdef CONFIG_STM32_TIM8_CH6OUT + .out1 = + { + .in_use = 1, + .pol = CONFIG_STM32_TIM8_CH6POL, + .idle = CONFIG_STM32_TIM8_CH6IDLE, + .pincfg = 0, /* Not available externally */ + } +#endif + } +#endif +}; + +static struct stm32_pwmtimer_s g_pwm8dev = +{ + .ops = &g_pwmops, +#ifdef CONFIG_STM32_PWM_LL_OPS + .llops = &g_llpwmops, +#endif + .timid = 8, + .chan_num = PWM_TIM8_NCHANNELS, + .channels = g_pwm8channels, + .timtype = TIMTYPE_TIM8, + .mode = CONFIG_STM32_TIM8_MODE, + .lock = CONFIG_STM32_TIM8_LOCK, + .t_dts = CONFIG_STM32_TIM8_TDTS, +#ifdef HAVE_PWM_COMPLEMENTARY + .deadtime = CONFIG_STM32_TIM8_DEADTIME, +#endif +#if defined(HAVE_TRGO) && defined(STM32_TIM8_TRGO) + .trgo = STM32_TIM8_TRGO, +#endif + .base = STM32_TIM8_BASE, + .pclk = TIMCLK_TIM8, +}; +#endif /* CONFIG_STM32_TIM8_PWM */ + +#ifdef CONFIG_STM32_TIM9_PWM + +static struct stm32_pwmchan_s g_pwm9channels[] = +{ + /* TIM9 has 2 channels */ + +#ifdef CONFIG_STM32_TIM9_CHANNEL1 + { + .channel = 1, + .mode = CONFIG_STM32_TIM9_CH1MODE, +#ifdef CONFIG_STM32_TIM9_CH1OUT + .out1 = + { + .in_use = 1, + .pol = CONFIG_STM32_TIM9_CH1POL, + .idle = CONFIG_STM32_TIM9_CH1IDLE, + .pincfg = PWM_TIM9_CH1CFG, + } +#endif + /* No complementary outputs */ + }, +#endif +#ifdef CONFIG_STM32_TIM9_CHANNEL2 + { + .channel = 2, + .mode = CONFIG_STM32_TIM9_CH2MODE, +#ifdef CONFIG_STM32_TIM9_CH2OUT + .out1 = + { + .in_use = 1, + .pol = CONFIG_STM32_TIM9_CH2POL, + .idle = CONFIG_STM32_TIM9_CH2IDLE, + .pincfg = PWM_TIM9_CH2CFG, + } +#endif + /* No complementary outputs */ + } +#endif +}; + +static struct stm32_pwmtimer_s g_pwm9dev = +{ + .ops = &g_pwmops, +#ifdef CONFIG_STM32_PWM_LL_OPS + .llops = &g_llpwmops, +#endif + .timid = 9, + .chan_num = PWM_TIM9_NCHANNELS, + .channels = g_pwm9channels, + .timtype = TIMTYPE_TIM9, + .mode = STM32_TIMMODE_COUNTUP, + .lock = 0, /* No lock */ + .t_dts = 0, /* No t_dts */ +#ifdef HAVE_PWM_COMPLEMENTARY + .deadtime = 0, /* No deadtime */ +#endif +#if defined(HAVE_TRGO) + .trgo = 0, /* TRGO not supported for TIM9 */ +#endif + .base = STM32_TIM9_BASE, + .pclk = TIMCLK_TIM9, +}; +#endif /* CONFIG_STM32_TIM9_PWM */ + +#ifdef CONFIG_STM32_TIM10_PWM + +static struct stm32_pwmchan_s g_pwm10channels[] = +{ + /* TIM10 has 1 channel */ + +#ifdef CONFIG_STM32_TIM10_CHANNEL1 + { + .channel = 1, + .mode = CONFIG_STM32_TIM10_CH1MODE, +#ifdef CONFIG_STM32_TIM10_CH1OUT + .out1 = + { + .in_use = 1, + .pol = CONFIG_STM32_TIM10_CH1POL, + .idle = CONFIG_STM32_TIM10_CH1IDLE, + .pincfg = PWM_TIM10_CH1CFG, + } +#endif + /* No complementary outputs */ + } +#endif +}; + +static struct stm32_pwmtimer_s g_pwm10dev = +{ + .ops = &g_pwmops, +#ifdef CONFIG_STM32_PWM_LL_OPS + .llops = &g_llpwmops, +#endif + .timid = 10, + .chan_num = PWM_TIM10_NCHANNELS, + .channels = g_pwm10channels, + .timtype = TIMTYPE_TIM10, + .mode = STM32_TIMMODE_COUNTUP, + .lock = 0, /* No lock */ + .t_dts = 0, /* No t_dts */ +#ifdef HAVE_PWM_COMPLEMENTARY + .deadtime = 0, /* No deadtime */ +#endif +#if defined(HAVE_TRGO) + .trgo = 0, /* TRGO not supported for TIM10 */ +#endif + .base = STM32_TIM10_BASE, + .pclk = TIMCLK_TIM10, +}; +#endif /* CONFIG_STM32_TIM10_PWM */ + +#ifdef CONFIG_STM32_TIM11_PWM + +static struct stm32_pwmchan_s g_pwm11channels[] = +{ + /* TIM11 has 1 channel */ + +#ifdef CONFIG_STM32_TIM11_CHANNEL1 + { + .channel = 1, + .mode = CONFIG_STM32_TIM11_CH1MODE, +#ifdef CONFIG_STM32_TIM11_CH1OUT + .out1 = + { + .in_use = 1, + .pol = CONFIG_STM32_TIM11_CH1POL, + .idle = CONFIG_STM32_TIM11_CH1IDLE, + .pincfg = PWM_TIM11_CH1CFG, + } +#endif + /* No complementary outputs */ + } +#endif +}; + +static struct stm32_pwmtimer_s g_pwm11dev = +{ + .ops = &g_pwmops, +#ifdef CONFIG_STM32_PWM_LL_OPS + .llops = &g_llpwmops, +#endif + .timid = 11, + .chan_num = PWM_TIM11_NCHANNELS, + .channels = g_pwm11channels, + .timtype = TIMTYPE_TIM11, + .mode = STM32_TIMMODE_COUNTUP, + .lock = 0, /* No lock */ + .t_dts = 0, /* No t_dts */ +#ifdef HAVE_PWM_COMPLEMENTARY + .deadtime = 0, /* No deadtime */ +#endif +#if defined(HAVE_TRGO) + .trgo = 0, /* TRGO not supported for TIM11 */ +#endif + .base = STM32_TIM11_BASE, + .pclk = TIMCLK_TIM11, +}; +#endif /* CONFIG_STM32_TIM11_PWM */ + +#ifdef CONFIG_STM32_TIM12_PWM + +static struct stm32_pwmchan_s g_pwm12channels[] = +{ + /* TIM12 has 2 channels */ + +#ifdef CONFIG_STM32_TIM12_CHANNEL1 + { + .channel = 1, + .mode = CONFIG_STM32_TIM12_CH1MODE, +#ifdef CONFIG_STM32_TIM12_CH1OUT + .out1 = + { + .in_use = 1, + .pol = CONFIG_STM32_TIM12_CH1POL, + .idle = CONFIG_STM32_TIM12_CH1IDLE, + .pincfg = PWM_TIM12_CH1CFG, + } +#endif + /* No complementary outputs */ + }, +#endif +#ifdef CONFIG_STM32_TIM12_CHANNEL2 + { + .channel = 2, + .mode = CONFIG_STM32_TIM12_CH2MODE, +#ifdef CONFIG_STM32_TIM12_CH2OUT + .out1 = + { + .in_use = 1, + .pol = CONFIG_STM32_TIM12_CH2POL, + .idle = CONFIG_STM32_TIM12_CH2IDLE, + .pincfg = PWM_TIM12_CH2CFG, + } +#endif + /* No complementary outputs */ + } +#endif +}; + +static struct stm32_pwmtimer_s g_pwm12dev = +{ + .ops = &g_pwmops, +#ifdef CONFIG_STM32_PWM_LL_OPS + .llops = &g_llpwmops, +#endif + .timid = 12, + .chan_num = PWM_TIM12_NCHANNELS, + .channels = g_pwm12channels, + .timtype = TIMTYPE_TIM12, + .mode = STM32_TIMMODE_COUNTUP, + .lock = 0, /* No lock */ + .t_dts = 0, /* No t_dts */ +#ifdef HAVE_PWM_COMPLEMENTARY + .deadtime = 0, /* No deadtime */ +#endif +#if defined(HAVE_TRGO) + .trgo = 0, /* TRGO not supported for TIM12 */ +#endif + .base = STM32_TIM12_BASE, + .pclk = TIMCLK_TIM12, +}; +#endif /* CONFIG_STM32_TIM12_PWM */ + +#ifdef CONFIG_STM32_TIM13_PWM + +static struct stm32_pwmchan_s g_pwm13channels[] = +{ + /* TIM13 has 1 channel */ + +#ifdef CONFIG_STM32_TIM13_CHANNEL1 + { + .channel = 1, + .mode = CONFIG_STM32_TIM13_CH1MODE, +#ifdef CONFIG_STM32_TIM13_CH1OUT + .out1 = + { + .in_use = 1, + .pol = CONFIG_STM32_TIM13_CH1POL, + .idle = CONFIG_STM32_TIM13_CH1IDLE, + .pincfg = PWM_TIM13_CH1CFG, + } +#endif + /* No complementary outputs */ + } +#endif +}; + +static struct stm32_pwmtimer_s g_pwm13dev = +{ + .ops = &g_pwmops, +#ifdef CONFIG_STM32_PWM_LL_OPS + .llops = &g_llpwmops, +#endif + .timid = 13, + .chan_num = PWM_TIM13_NCHANNELS, + .channels = g_pwm13channels, + .timtype = TIMTYPE_TIM13, + .mode = STM32_TIMMODE_COUNTUP, + .lock = 0, /* No lock */ + .t_dts = 0, /* No t_dts */ +#ifdef HAVE_PWM_COMPLEMENTARY + .deadtime = 0, /* No deadtime */ +#endif +#if defined(HAVE_TRGO) + .trgo = 0, /* TRGO not supported for TIM13 */ +#endif + .base = STM32_TIM13_BASE, + .pclk = TIMCLK_TIM13, +}; +#endif /* CONFIG_STM32_TIM13_PWM */ + +#ifdef CONFIG_STM32_TIM14_PWM + +static struct stm32_pwmchan_s g_pwm14channels[] = +{ + /* TIM14 has 1 channel */ + +#ifdef CONFIG_STM32_TIM14_CHANNEL1 + { + .channel = 1, + .mode = CONFIG_STM32_TIM14_CH1MODE, +#ifdef CONFIG_STM32_TIM14_CH1OUT + .out1 = + { + .in_use = 1, + .pol = CONFIG_STM32_TIM14_CH1POL, + .idle = CONFIG_STM32_TIM14_CH1IDLE, + .pincfg = PWM_TIM14_CH1CFG, + } +#endif + /* No complementary outputs */ + } +#endif +}; + +static struct stm32_pwmtimer_s g_pwm14dev = +{ + .ops = &g_pwmops, +#ifdef CONFIG_STM32_PWM_LL_OPS + .llops = &g_llpwmops, +#endif + .timid = 14, + .chan_num = PWM_TIM14_NCHANNELS, + .channels = g_pwm14channels, + .timtype = TIMTYPE_TIM14, + .mode = STM32_TIMMODE_COUNTUP, + .lock = 0, /* No lock */ + .t_dts = 0, /* No t_dts */ +#ifdef HAVE_PWM_COMPLEMENTARY + .deadtime = 0, /* No deadtime */ +#endif +#if defined(HAVE_TRGO) + .trgo = 0, /* TRGO not supported for TIM14 */ +#endif + .base = STM32_TIM14_BASE, + .pclk = TIMCLK_TIM14, +}; +#endif /* CONFIG_STM32_TIM14_PWM */ + +#ifdef CONFIG_STM32_TIM15_PWM + +static struct stm32_pwmchan_s g_pwm15channels[] = +{ + /* TIM15 has 2 channels, 1 complementary */ + +#ifdef CONFIG_STM32_TIM15_CHANNEL1 + { + .channel = 1, + .mode = CONFIG_STM32_TIM15_CH1MODE, +#ifdef HAVE_BREAK + .brk = + { +#ifdef CONFIG_STM32_TIM15_BREAK1 + .en1 = 1, + .pol1 = CONFIG_STM32_TIM15_BRK1POL, +#endif + /* No BREAK2 */ + }, +#endif +#ifdef CONFIG_STM32_TIM15_CH1OUT + .out1 = + { + .in_use = 1, + .pol = CONFIG_STM32_TIM15_CH1POL, + .idle = CONFIG_STM32_TIM15_CH1IDLE, + .pincfg = PWM_TIM15_CH1CFG, + }, +#endif +#ifdef CONFIG_STM32_TIM15_CH1NOUT + .out2 = + { + .in_use = 1, + .pol = CONFIG_STM32_TIM15_CH1NPOL, + .idle = CONFIG_STM32_TIM15_CH1NIDLE, + .pincfg = PWM_TIM15_CH2CFG, + } +#endif + }, +#endif +#ifdef CONFIG_STM32_TIM15_CHANNEL2 + { + .channel = 2, + .mode = CONFIG_STM32_TIM15_CH2MODE, +#ifdef CONFIG_STM32_TIM12_CH2OUT + .out1 = + { + .in_use = 1, + .pol = CONFIG_STM32_TIM15_CH2POL, + .idle = CONFIG_STM32_TIM15_CH2IDLE, + .pincfg = PWM_TIM15_CH2CFG, + } +#endif + /* No complementary outputs */ + }, +#endif +}; + +static struct stm32_pwmtimer_s g_pwm15dev = +{ + .ops = &g_pwmops, +#ifdef CONFIG_STM32_PWM_LL_OPS + .llops = &g_llpwmops, +#endif + .timid = 15, + .chan_num = PWM_TIM15_NCHANNELS, + .channels = g_pwm15channels, + .timtype = TIMTYPE_TIM15, + .mode = STM32_TIMMODE_COUNTUP, + .lock = CONFIG_STM32_TIM15_LOCK, + .t_dts = CONFIG_STM32_TIM15_TDTS, +#ifdef HAVE_PWM_COMPLEMENTARY + .deadtime = CONFIG_STM32_TIM15_DEADTIME, +#endif +#if defined(HAVE_TRGO) && defined(STM32_TIM15_TRGO) + .trgo = STM32_TIM15_TRGO, +#endif + .base = STM32_TIM15_BASE, + .pclk = TIMCLK_TIM15, +}; +#endif /* CONFIG_STM32_TIM15_PWM */ + +#ifdef CONFIG_STM32_TIM16_PWM + +static struct stm32_pwmchan_s g_pwm16channels[] = +{ + /* TIM16 has 1 channel, 1 complementary */ + +#ifdef CONFIG_STM32_TIM16_CHANNEL1 + { + .channel = 1, + .mode = CONFIG_STM32_TIM16_CH1MODE, +#ifdef HAVE_BREAK + .brk = + { +#ifdef CONFIG_STM32_TIM16_BREAK1 + .en1 = 1, + .pol1 = CONFIG_STM32_TIM16_BRK1POL, +#endif + /* No BREAK2 */ + }, +#endif +#ifdef CONFIG_STM32_TIM16_CH1OUT + .out1 = + { + .in_use = 1, + .pol = CONFIG_STM32_TIM16_CH1POL, + .idle = CONFIG_STM32_TIM16_CH1IDLE, + .pincfg = PWM_TIM16_CH1CFG, + }, +#endif +#ifdef CONFIG_STM32_TIM16_CH1NOUT + .out2 = + { + .in_use = 1, + .pol = CONFIG_STM32_TIM16_CH1NPOL, + .idle = CONFIG_STM32_TIM16_CH1NIDLE, + .pincfg = PWM_TIM16_CH2CFG, + } +#endif + }, +#endif +}; + +static struct stm32_pwmtimer_s g_pwm16dev = +{ + .ops = &g_pwmops, +#ifdef CONFIG_STM32_PWM_LL_OPS + .llops = &g_llpwmops, +#endif + .timid = 16, + .chan_num = PWM_TIM16_NCHANNELS, + .channels = g_pwm16channels, + .timtype = TIMTYPE_TIM16, + .mode = STM32_TIMMODE_COUNTUP, + .lock = CONFIG_STM32_TIM16_LOCK, + .t_dts = CONFIG_STM32_TIM16_TDTS, +#ifdef HAVE_PWM_COMPLEMENTARY + .deadtime = CONFIG_STM32_TIM16_DEADTIME, +#endif +#if defined(HAVE_TRGO) + .trgo = 0, /* TRGO not supported for TIM16 */ +#endif + .base = STM32_TIM16_BASE, + .pclk = TIMCLK_TIM16, +}; +#endif /* CONFIG_STM32_TIM16_PWM */ + +#ifdef CONFIG_STM32_TIM17_PWM + +static struct stm32_pwmchan_s g_pwm17channels[] = +{ + /* TIM17 has 1 channel, 1 complementary */ + +#ifdef CONFIG_STM32_TIM17_CHANNEL1 + { + .channel = 1, + .mode = CONFIG_STM32_TIM17_CH1MODE, +#ifdef HAVE_BREAK + .brk = + { +#ifdef CONFIG_STM32_TIM17_BREAK1 + .en1 = 1, + .pol1 = CONFIG_STM32_TIM17_BRK1POL, +#endif + /* No BREAK2 */ + }, +#endif +#ifdef CONFIG_STM32_TIM17_CH1OUT + .out1 = + { + .in_use = 1, + .pol = CONFIG_STM32_TIM17_CH1POL, + .idle = CONFIG_STM32_TIM17_CH1IDLE, + .pincfg = PWM_TIM17_CH1CFG, + }, +#endif +#ifdef CONFIG_STM32_TIM17_CH1NOUT + .out2 = + { + .in_use = 1, + .pol = CONFIG_STM32_TIM17_CH1NPOL, + .idle = CONFIG_STM32_TIM17_CH1NIDLE, + .pincfg = PWM_TIM17_CH2CFG, + } +#endif + }, +#endif +}; + +static struct stm32_pwmtimer_s g_pwm17dev = +{ + .ops = &g_pwmops, +#ifdef CONFIG_STM32_PWM_LL_OPS + .llops = &g_llpwmops, +#endif + .timid = 17, + .chan_num = PWM_TIM17_NCHANNELS, + .channels = g_pwm17channels, + .timtype = TIMTYPE_TIM17, + .mode = STM32_TIMMODE_COUNTUP, + .lock = CONFIG_STM32_TIM17_LOCK, + .t_dts = CONFIG_STM32_TIM17_TDTS, +#ifdef HAVE_PWM_COMPLEMENTARY + .deadtime = CONFIG_STM32_TIM17_DEADTIME, +#endif +#if defined(HAVE_TRGO) + .trgo = 0, /* TRGO not supported for TIM17 */ +#endif + .base = STM32_TIM17_BASE, + .pclk = TIMCLK_TIM17, +}; +#endif /* CONFIG_STM32_TIM17_PWM */ + +/* TODO: support for TIM19,20,21,22 */ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: pwm_reg_is_32bit + ****************************************************************************/ + +static bool pwm_reg_is_32bit(uint8_t timtype, uint32_t offset) +{ + bool ret = false; + + if (timtype == TIMTYPE_GENERAL32) + { + if (offset == STM32_GTIM_CNT_OFFSET || + offset == STM32_GTIM_ARR_OFFSET || + offset == STM32_GTIM_CCR1_OFFSET || + offset == STM32_GTIM_CCR2_OFFSET || + offset == STM32_GTIM_CCR3_OFFSET || + offset == STM32_GTIM_CCR4_OFFSET) + { + ret = true; + } + } +#ifdef HAVE_IP_TIMERS_V2 + else if (timtype == TIMTYPE_ADVANCED) + { + if (offset == STM32_ATIM_CR2_OFFSET || + offset == STM32_ATIM_CCMR1_OFFSET || + offset == STM32_ATIM_CCMR2_OFFSET || + offset == STM32_ATIM_CCER_OFFSET || + offset == STM32_ATIM_BDTR_OFFSET || + offset == STM32_ATIM_CCMR3_OFFSET || + offset == STM32_ATIM_CCR5_OFFSET) + { + ret = true; + } + } +#endif + + return ret; +} + +/**************************************************************************** + * Name: pwm_getreg + * + * Description: + * Read the value of an PWM timer register + * + * Input Parameters: + * priv - A reference to the PWM block status + * offset - The offset to the register to read + * + * Returned Value: + * The current contents of the specified register + * + ****************************************************************************/ + +static uint32_t pwm_getreg(struct stm32_pwmtimer_s *priv, int offset) +{ + uint32_t retval = 0; + + if (pwm_reg_is_32bit(priv->timtype, offset) == true) + { + /* 32-bit register */ + + retval = getreg32(priv->base + offset); + } + else + { + /* 16-bit register */ + + retval = getreg16(priv->base + offset); + } + + /* Return 32-bit value */ + + return retval; +} + +/**************************************************************************** + * Name: pwm_putreg + * + * Description: + * Read the value of an PWM timer register + * + * Input Parameters: + * priv - A reference to the PWM block status + * offset - The offset to the register to read + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void pwm_putreg(struct stm32_pwmtimer_s *priv, int offset, + uint32_t value) +{ + if (pwm_reg_is_32bit(priv->timtype, offset) == true) + { + /* 32-bit register */ + + putreg32(value, priv->base + offset); + } + else + { + /* 16-bit register */ + + putreg16((uint16_t)value, priv->base + offset); + } +} + +/**************************************************************************** + * Name: pwm_modifyreg + * + * Description: + * Modify PWM register (32-bit or 16-bit) + * + * Input Parameters: + * priv - A reference to the PWM block status + * offset - The offset to the register to read + * clrbits - The bits to clear + * setbits - The bits to set + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void pwm_modifyreg(struct stm32_pwmtimer_s *priv, uint32_t offset, + uint32_t clearbits, uint32_t setbits) +{ + if (pwm_reg_is_32bit(priv->timtype, offset) == true) + { + /* 32-bit register */ + + modifyreg32(priv->base + offset, clearbits, setbits); + } + else + { + /* 16-bit register */ + + modifyreg16(priv->base + offset, (uint16_t)clearbits, + (uint16_t)setbits); + } +} + +/**************************************************************************** + * Name: pwm_dumpregs + * + * Description: + * Dump all timer registers. + * + * Input Parameters: + * dev - A reference to the lower half PWM driver state structure + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_DEBUG_PWM_INFO +static void pwm_dumpregs(struct pwm_lowerhalf_s *dev, const char *msg) +{ + struct stm32_pwmtimer_s *priv = (struct stm32_pwmtimer_s *)dev; + + pwminfo("%s:\n", msg); + if (priv->timid == 16 || priv->timid == 17) + { + pwminfo(" CR1: %04x CR2: %04x DIER: %04x\n", + pwm_getreg(priv, STM32_GTIM_CR1_OFFSET), + pwm_getreg(priv, STM32_GTIM_CR2_OFFSET), + pwm_getreg(priv, STM32_GTIM_DIER_OFFSET)); + } + else + { + pwminfo(" CR1: %04x CR2: %04x SMCR: %04x DIER: %04x\n", + pwm_getreg(priv, STM32_GTIM_CR1_OFFSET), + pwm_getreg(priv, STM32_GTIM_CR2_OFFSET), + pwm_getreg(priv, STM32_GTIM_SMCR_OFFSET), + pwm_getreg(priv, STM32_GTIM_DIER_OFFSET)); + } + + if (priv->timid >= 15 && priv->timid <= 17) + { + pwminfo(" SR: %04x EGR: %04x CCMR1: %04x\n", + pwm_getreg(priv, STM32_GTIM_SR_OFFSET), + pwm_getreg(priv, STM32_GTIM_EGR_OFFSET), + pwm_getreg(priv, STM32_GTIM_CCMR1_OFFSET)); + } + else + { + pwminfo(" SR: %04x EGR: %04x CCMR1: %04x CCMR2: %04x\n", + pwm_getreg(priv, STM32_GTIM_SR_OFFSET), + pwm_getreg(priv, STM32_GTIM_EGR_OFFSET), + pwm_getreg(priv, STM32_GTIM_CCMR1_OFFSET), + pwm_getreg(priv, STM32_GTIM_CCMR2_OFFSET)); + } + + /* REVISIT: CNT and ARR may be 32-bits wide */ + + pwminfo(" CCER: %04x CNT: %04x PSC: %04x ARR: %04x\n", + pwm_getreg(priv, STM32_GTIM_CCER_OFFSET), + pwm_getreg(priv, STM32_GTIM_CNT_OFFSET), + pwm_getreg(priv, STM32_GTIM_PSC_OFFSET), + pwm_getreg(priv, STM32_GTIM_ARR_OFFSET)); + + if (priv->timid == 1 || priv->timid == 8 || + (priv->timid >= 15 && priv->timid <= 17)) + { + pwminfo(" RCR: %04x BDTR: %04x\n", + pwm_getreg(priv, STM32_ATIM_RCR_OFFSET), + pwm_getreg(priv, STM32_ATIM_BDTR_OFFSET)); + } + + /* REVISIT: CCR1-CCR4 may be 32-bits wide */ + + if (priv->timid == 16 || priv->timid == 17) + { + pwminfo(" CCR1: %04x\n", + pwm_getreg(priv, STM32_GTIM_CCR1_OFFSET)); + } + else if (priv->timid == 15) + { + pwminfo(" CCR1: %04x CCR2: %04x\n", + pwm_getreg(priv, STM32_GTIM_CCR1_OFFSET), + pwm_getreg(priv, STM32_GTIM_CCR2_OFFSET)); + } + else + { + pwminfo(" CCR1: %04x CCR2: %04x CCR3: %04x CCR4: %04x\n", + pwm_getreg(priv, STM32_GTIM_CCR1_OFFSET), + pwm_getreg(priv, STM32_GTIM_CCR2_OFFSET), + pwm_getreg(priv, STM32_GTIM_CCR3_OFFSET), + pwm_getreg(priv, STM32_GTIM_CCR4_OFFSET)); + } + + pwminfo(" DCR: %04x DMAR: %04x\n", + pwm_getreg(priv, STM32_GTIM_DCR_OFFSET), + pwm_getreg(priv, STM32_GTIM_DMAR_OFFSET)); + +#ifdef HAVE_IP_TIMERS_V2 + if (priv->timtype == TIMTYPE_ADVANCED) + { + pwminfo(" CCMR3: %04x CCR5: %04x CCR6: %04x\n", + pwm_getreg(priv, STM32_ATIM_CCMR3_OFFSET), + pwm_getreg(priv, STM32_ATIM_CCR5_OFFSET), + pwm_getreg(priv, STM32_ATIM_CCR6_OFFSET)); + } +#endif +} +#endif + +/**************************************************************************** + * Name: pwm_ccr_update + ****************************************************************************/ + +static int pwm_ccr_update(struct pwm_lowerhalf_s *dev, uint8_t index, + uint32_t ccr) +{ + struct stm32_pwmtimer_s *priv = (struct stm32_pwmtimer_s *)dev; + uint32_t offset = 0; + + /* Only ADV timers have CC5 and CC6 */ + +#ifdef HAVE_IP_TIMERS_V2 + if (priv->timtype != TIMTYPE_ADVANCED && (index == 5 || index == 6)) + { + pwmerr("ERROR: No such CCR: %u\n", index); + return -EINVAL; + } +#endif + + /* REVISIT: start index from 0? */ + + switch (index) + { + case STM32_PWM_CHAN1: + { + offset = STM32_GTIM_CCR1_OFFSET; + break; + } + + case STM32_PWM_CHAN2: + { + offset = STM32_GTIM_CCR2_OFFSET; + break; + } + + case STM32_PWM_CHAN3: + { + offset = STM32_GTIM_CCR3_OFFSET; + break; + } + + case STM32_PWM_CHAN4: + { + offset = STM32_GTIM_CCR4_OFFSET; + break; + } + +#ifdef HAVE_IP_TIMERS_V2 + case STM32_PWM_CHAN5: + { + offset = STM32_ATIM_CCR5_OFFSET; + break; + } + + case STM32_PWM_CHAN6: + { + offset = STM32_ATIM_CCR6_OFFSET; + break; + } +#endif + + default: + { + pwmerr("ERROR: No such CCR: %u\n", index); + return -EINVAL; + } + } + + /* Update CCR register */ + + pwm_putreg(priv, offset, ccr); + + return OK; +} + +/**************************************************************************** + * Name: pwm_ccr_get + ****************************************************************************/ + +#ifdef CONFIG_STM32_PWM_LL_OPS +static uint32_t pwm_ccr_get(struct pwm_lowerhalf_s *dev, uint8_t index) +{ + struct stm32_pwmtimer_s *priv = (struct stm32_pwmtimer_s *)dev; + uint32_t offset = 0; + + switch (index) + { + case STM32_PWM_CHAN1: + { + offset = STM32_GTIM_CCR1_OFFSET; + break; + } + + case STM32_PWM_CHAN2: + { + offset = STM32_GTIM_CCR2_OFFSET; + break; + } + + case STM32_PWM_CHAN3: + { + offset = STM32_GTIM_CCR3_OFFSET; + break; + } + + case STM32_PWM_CHAN4: + { + offset = STM32_GTIM_CCR4_OFFSET; + break; + } + +#ifdef HAVE_IP_TIMERS_V2 + case STM32_PWM_CHAN5: + { + offset = STM32_ATIM_CCR5_OFFSET; + break; + } + + case STM32_PWM_CHAN6: + { + offset = STM32_ATIM_CCR6_OFFSET; + break; + } +#endif + + default: + { + pwmerr("ERROR: No such CCR: %u\n", index); + return -EINVAL; + } + } + + /* Return CCR register */ + + return pwm_getreg(priv, offset); +} +#endif /* CONFIG_STM32_PWM_LL_OPS */ + +/**************************************************************************** + * Name: pwm_arr_update + ****************************************************************************/ + +static int pwm_arr_update(struct pwm_lowerhalf_s *dev, uint32_t arr) +{ + struct stm32_pwmtimer_s *priv = (struct stm32_pwmtimer_s *)dev; + + /* Update ARR register */ + + pwm_putreg(priv, STM32_GTIM_ARR_OFFSET, arr); + + return OK; +} + +/**************************************************************************** + * Name: pwm_arr_get + ****************************************************************************/ + +static uint32_t pwm_arr_get(struct pwm_lowerhalf_s *dev) +{ + struct stm32_pwmtimer_s *priv = (struct stm32_pwmtimer_s *)dev; + + return pwm_getreg(priv, STM32_GTIM_ARR_OFFSET); +} + +#ifdef HAVE_ADVTIM +/**************************************************************************** + * Name: pwm_rcr_update + ****************************************************************************/ + +static int pwm_rcr_update(struct pwm_lowerhalf_s *dev, uint16_t rcr) +{ + struct stm32_pwmtimer_s *priv = (struct stm32_pwmtimer_s *)dev; + + /* Update RCR register */ + + pwm_putreg(priv, STM32_ATIM_RCR_OFFSET, rcr); + + return OK; +} +#endif + +#ifdef CONFIG_STM32_PWM_LL_OPS +/**************************************************************************** + * Name: pwm_rcr_get + ****************************************************************************/ + +static uint16_t pwm_rcr_get(struct pwm_lowerhalf_s *dev) +{ + struct stm32_pwmtimer_s *priv = (struct stm32_pwmtimer_s *)dev; + + return pwm_getreg(priv, STM32_ATIM_RCR_OFFSET); +} +#endif + +/**************************************************************************** + * Name: pwm_duty_update + * + * Description: + * Try to change only channel duty + * + * Input Parameters: + * dev - A reference to the lower half PWM driver state structure + * channel - Channel to by updated + * duty - New duty + * + * Returned Value: + * Zero on success; a negated errno value on failure + * + ****************************************************************************/ + +static int pwm_duty_update(struct pwm_lowerhalf_s *dev, uint8_t channel, + ub16_t duty) +{ + struct stm32_pwmtimer_s *priv = (struct stm32_pwmtimer_s *)dev; + uint32_t reload = 0; + uint32_t ccr = 0; + + /* We don't want compilation warnings if no DEBUGASSERT */ + + UNUSED(priv); + + DEBUGASSERT(priv != NULL); + + pwminfo("TIM%u channel: %u duty: %08" PRIx32 "\n", + priv->timid, channel, duty); + + /* Get the reload values */ + + reload = pwm_arr_get(dev); + + /* Duty cycle: + * + * duty cycle = ccr / reload (fractional value) + */ + + ccr = b16toi(duty * reload + b16HALF); + + pwminfo("ccr: %" PRIu32 "\n", ccr); + + /* Write corresponding CCR register */ + + pwm_ccr_update(dev, channel, ccr); + + return OK; +} + +/**************************************************************************** + * Name: pwm_timer_enable + ****************************************************************************/ + +static int pwm_timer_enable(struct pwm_lowerhalf_s *dev, bool state) +{ + struct stm32_pwmtimer_s *priv = (struct stm32_pwmtimer_s *)dev; + + if (state == true) + { + /* Enable timer counter */ + + pwm_modifyreg(priv, STM32_GTIM_CR1_OFFSET, 0, GTIM_CR1_CEN); + } + else + { + /* Disable timer counter */ + + pwm_modifyreg(priv, STM32_GTIM_CR1_OFFSET, GTIM_CR1_CEN, 0); + } + + return OK; +} + +/**************************************************************************** + * Name: pwm_frequency_update + * + * Description: + * Update a PWM timer frequency + * + ****************************************************************************/ + +static int pwm_frequency_update(struct pwm_lowerhalf_s *dev, + uint32_t frequency) +{ + struct stm32_pwmtimer_s *priv = (struct stm32_pwmtimer_s *)dev; + uint32_t reload = 0; + uint32_t timclk = 0; + uint32_t prescaler = 0; + + /* Calculate optimal values for the timer prescaler and for the timer + * reload register. If 'frequency' is the desired frequency, then + * + * reload = timclk / frequency + * timclk = pclk / presc + * + * Or, + * + * reload = pclk / presc / frequency + * + * There are many solutions to this, but the best solution will be the one + * that has the largest reload value and the smallest prescaler value. + * That is the solution that should give us the most accuracy in the timer + * control. Subject to: + * + * 0 <= presc <= 65536 + * 1 <= reload <= 65535 + * + * So presc = pclk / 65535 / frequency would be optimal. + * + * Example: + * + * pclk = 42 MHz + * frequency = 100 Hz + * + * prescaler = 42,000,000 / 65,535 / 100 + * = 6.4 (or 7 -- taking the ceiling always) + * timclk = 42,000,000 / 7 + * = 6,000,000 + * reload = 6,000,000 / 100 + * = 60,000 + */ + + prescaler = (priv->pclk / frequency + 65534) / 65535; + if (prescaler < 1) + { + prescaler = 1; + } + else if (prescaler > 65536) + { + prescaler = 65536; + } + + timclk = priv->pclk / prescaler; + + reload = timclk / frequency; + if (reload < 2) + { + reload = 1; + } + else if (reload > 65535) + { + reload = 65535; + } + else + { + reload--; + } + + pwminfo("TIM%u PCLK: %" PRIu32" frequency: %" PRIu32 + " TIMCLK: %" PRIu32 " " + "prescaler: %" PRIu32 " reload: %" PRIu32 "\n", + priv->timid, priv->pclk, frequency, timclk, prescaler, reload); + + /* Set the reload and prescaler values */ + + pwm_arr_update(dev, reload); + pwm_putreg(priv, STM32_GTIM_PSC_OFFSET, (uint16_t)(prescaler - 1)); + + return OK; +} + +/**************************************************************************** + * Name: pwm_timer_configure + * + * Description: + * Initial configuration for PWM timer + * + ****************************************************************************/ + +static int pwm_timer_configure(struct stm32_pwmtimer_s *priv) +{ + uint16_t cr1 = 0; + int ret = OK; + + /* Set up the timer CR1 register: + * + * 1,8 CKD[1:0] ARPE CMS[1:0] DIR OPM URS UDIS CEN + * 2-5 CKD[1:0] ARPE CMS DIR OPM URS UDIS CEN + * 6-7 ARPE OPM URS UDIS CEN + * 9-14 CKD[1:0] ARPE URS UDIS CEN + * 15-17 CKD[1:0] ARPE OPM URS UDIS CEN + */ + + cr1 = pwm_getreg(priv, STM32_GTIM_CR1_OFFSET); + + /* Set the counter mode for the advanced timers (1,8) and most general + * purpose timers (all 2-5, but not 9-17), i.e., all but TIMTYPE_COUNTUP16 + * and TIMTYPE_BASIC + */ + + if (priv->timtype != TIMTYPE_BASIC && priv->timtype != TIMTYPE_COUNTUP16) + { + /* Select the Counter Mode: + * + * GTIM_CR1_EDGE: The counter counts up or down depending on the + * direction bit (DIR). + * GTIM_CR1_CENTER1, GTIM_CR1_CENTER2, GTIM_CR1_CENTER3: The counter + * counts up then down. + * GTIM_CR1_DIR: 0: count up, 1: count down + */ + + cr1 &= ~(GTIM_CR1_DIR | GTIM_CR1_CMS_MASK); + + switch (priv->mode) + { + case STM32_TIMMODE_COUNTUP: + { + cr1 |= GTIM_CR1_EDGE; + break; + } + + case STM32_TIMMODE_COUNTDOWN: + { + cr1 |= GTIM_CR1_EDGE | GTIM_CR1_DIR; + break; + } + + case STM32_TIMMODE_CENTER1: + { + cr1 |= GTIM_CR1_CENTER1; + break; + } + + case STM32_TIMMODE_CENTER2: + { + cr1 |= GTIM_CR1_CENTER2; + break; + } + + case STM32_TIMMODE_CENTER3: + { + cr1 |= GTIM_CR1_CENTER3; + break; + } + + default: + { + pwmerr("ERROR: No such timer mode: %u\n", + (unsigned int)priv->mode); + ret = -EINVAL; + goto errout; + } + } + } + + /* Enable ARR Preload + * TODO: this should be configurable + */ + + cr1 |= GTIM_CR1_ARPE; + + /* Write CR1 */ + + pwm_putreg(priv, STM32_GTIM_CR1_OFFSET, cr1); + +errout: + return ret; +} + +/**************************************************************************** + * Name: pwm_mode_configure + * + * Description: + * Configure a PWM mode for given channel + * + ****************************************************************************/ + +static int pwm_mode_configure(struct pwm_lowerhalf_s *dev, + uint8_t channel, uint32_t mode) +{ + struct stm32_pwmtimer_s *priv = (struct stm32_pwmtimer_s *)dev; + uint32_t chanmode = 0; + uint32_t ocmode = 0; + uint32_t ccmr = 0; + uint32_t offset = 0; + int ret = OK; +#ifdef HAVE_IP_TIMERS_V2 + bool ocmbit = false; +#endif + +#ifdef HAVE_IP_TIMERS_V2 + /* Only advanced timers have channels 5-6 */ + + if (channel > 4 && priv->timtype != TIMTYPE_ADVANCED) + { + pwmerr("ERROR: No such channel: %u\n", channel); + ret = -EINVAL; + goto errout; + } +#endif + + /* Get channel mode + * TODO: configurable preload for CCxR + */ + + switch (mode) + { + case STM32_CHANMODE_FRZN: + { + chanmode = GTIM_CCMR_MODE_FRZN; + break; + } + + case STM32_CHANMODE_CHACT: + { + chanmode = GTIM_CCMR_MODE_CHACT; + break; + } + + case STM32_CHANMODE_CHINACT: + { + chanmode = GTIM_CCMR_MODE_CHINACT; + break; + } + + case STM32_CHANMODE_OCREFTOG: + { + chanmode = GTIM_CCMR_MODE_OCREFTOG; + break; + } + + case STM32_CHANMODE_OCREFLO: + { + chanmode = GTIM_CCMR_MODE_OCREFLO; + break; + } + + case STM32_CHANMODE_OCREFHI: + { + chanmode = GTIM_CCMR_MODE_OCREFHI; + break; + } + + case STM32_CHANMODE_PWM1: + { + chanmode = GTIM_CCMR_MODE_PWM1; + break; + } + + case STM32_CHANMODE_PWM2: + { + chanmode = GTIM_CCMR_MODE_PWM2; + break; + } + +#ifdef HAVE_IP_TIMERS_V2 + case STM32_CHANMODE_COMBINED1: + { + chanmode = ATIM_CCMR_MODE_COMBINED1; + ocmbit = true; + break; + } + + case STM32_CHANMODE_COMBINED2: + { + chanmode = ATIM_CCMR_MODE_COMBINED2; + ocmbit = true; + break; + } + + case STM32_CHANMODE_ASYMMETRIC1: + { + chanmode = ATIM_CCMR_MODE_ASYMMETRIC1; + ocmbit = true; + break; + } + + case STM32_CHANMODE_ASYMMETRIC2: + { + chanmode = ATIM_CCMR_MODE_ASYMMETRIC2; + ocmbit = true; + break; + } +#endif + + default: + { + pwmerr("ERROR: No such mode: %u\n", (unsigned int)mode); + ret = -EINVAL; + goto errout; + } + } + + /* Get CCMR offset */ + + switch (channel) + { + case STM32_PWM_CHAN1: + case STM32_PWM_CHAN2: + { + offset = STM32_GTIM_CCMR1_OFFSET; + break; + } + + case STM32_PWM_CHAN3: + case STM32_PWM_CHAN4: + { + offset = STM32_GTIM_CCMR2_OFFSET; + break; + } + +#ifdef HAVE_IP_TIMERS_V2 + case STM32_PWM_CHAN5: + case STM32_PWM_CHAN6: + { + offset = STM32_ATIM_CCMR3_OFFSET; + break; + } +#endif + + default: + { + pwmerr("ERROR: No such channel: %u\n", channel); + ret = -EINVAL; + goto errout; + } + } + + /* Get current registers */ + + ccmr = pwm_getreg(priv, offset); + + /* PWM mode configuration. + * NOTE: The CCMRx registers are identical if the channels are outputs. + */ + + switch (channel) + { + /* Configure channel 1/3/5 */ + + case STM32_PWM_CHAN1: + case STM32_PWM_CHAN3: +#ifdef HAVE_IP_TIMERS_V2 + case STM32_PWM_CHAN5: +#endif + { + /* Reset current channel 1/3/5 mode configuration */ + + ccmr &= ~(ATIM_CCMR1_CC1S_MASK | ATIM_CCMR1_OC1M_MASK | + ATIM_CCMR1_OC1PE); + + /* Configure CC1/3/5 as output */ + + ocmode |= (ATIM_CCMR_CCS_CCOUT << ATIM_CCMR1_CC1S_SHIFT); + + /* Configure Compare 1/3/5 mode */ + + ocmode |= (chanmode << ATIM_CCMR1_OC1M_SHIFT); + + /* Enable CCR1/3/5 preload */ + + ocmode |= ATIM_CCMR1_OC1PE; + +#ifdef HAVE_IP_TIMERS_V2 + /* Reset current OC bit */ + + ccmr &= ~(ATIM_CCMR1_OC1M); + + /* Set an additional OC1/3/5M bit */ + + if (ocmbit) + { + ocmode |= ATIM_CCMR1_OC1M; + } +#endif + break; + } + + /* Configure channel 2/4/6 */ + + case STM32_PWM_CHAN2: + case STM32_PWM_CHAN4: +#ifdef HAVE_IP_TIMERS_V2 + case STM32_PWM_CHAN6: +#endif + { + /* Reset current channel 2/4/6 mode configuration */ + + ccmr &= ~(ATIM_CCMR1_CC2S_MASK | ATIM_CCMR1_OC2M_MASK | + ATIM_CCMR1_OC2PE); + + /* Configure CC2/4/6 as output */ + + ocmode |= (ATIM_CCMR_CCS_CCOUT << ATIM_CCMR1_CC2S_SHIFT); + + /* Configure Compare 2/4/6 mode */ + + ocmode |= (chanmode << ATIM_CCMR1_OC2M_SHIFT); + + /* Enable CCR2/4/6 preload */ + + ocmode |= ATIM_CCMR1_OC2PE; + +#ifdef HAVE_IP_TIMERS_V2 + /* Reset current OC bit */ + + ccmr &= ~(ATIM_CCMR1_OC2M); + + /* Set an additioneal OC2/4/6M bit */ + + if (ocmbit) + { + ocmode |= ATIM_CCMR1_OC2M; + } +#endif + break; + } + } + + /* Set the selected output compare mode */ + + ccmr |= ocmode; + + /* Write CCMRx registers */ + + pwm_putreg(priv, offset, ccmr); + +errout: + return ret; +} + +/**************************************************************************** + * Name: pwm_output_configure + * + * Description: + * Configure PWM output for given channel + * + ****************************************************************************/ + +static int pwm_output_configure(struct stm32_pwmtimer_s *priv, + struct stm32_pwmchan_s *chan) +{ + uint32_t cr2 = 0; + uint32_t ccer = 0; + uint8_t channel = 0; + + /* Get channel */ + + channel = chan->channel; + + /* Get current registers state */ + + cr2 = pwm_getreg(priv, STM32_GTIM_CR2_OFFSET); + ccer = pwm_getreg(priv, STM32_GTIM_CCER_OFFSET); + + /* | OISx/OISxN | IDLE | for ADVANCED and COUNTUP16 | CR2 register + * | CCxP/CCxNP | POL | all PWM timers | CCER register + */ + + /* Configure output polarity (all PWM timers) */ + + if (chan->out1.pol == STM32_POL_NEG) + { + ccer |= (GTIM_CCER_CC1P << ((channel - 1) * 4)); + } + else + { + ccer &= ~(GTIM_CCER_CC1P << ((channel - 1) * 4)); + } + +#ifdef HAVE_ADVTIM + if (priv->timtype == TIMTYPE_ADVANCED || + priv->timtype == TIMTYPE_COUNTUP16_N) + { + /* Configure output IDLE State */ + + if (chan->out1.idle == STM32_IDLE_ACTIVE) + { + cr2 |= (ATIM_CR2_OIS1 << ((channel - 1) * 2)); + } + else + { + cr2 &= ~(ATIM_CR2_OIS1 << ((channel - 1) * 2)); + } + +#ifdef HAVE_PWM_COMPLEMENTARY + /* Configure complementary output IDLE state */ + + if (chan->out2.idle == STM32_IDLE_ACTIVE) + { + cr2 |= (ATIM_CR2_OIS1N << ((channel - 1) * 2)); + } + else + { + cr2 &= ~(ATIM_CR2_OIS1N << ((channel - 1) * 2)); + } + + /* Configure complementary output polarity */ + + if (chan->out2.pol == STM32_POL_NEG) + { + ccer |= (ATIM_CCER_CC1NP << ((channel - 1) * 4)); + } + else + { + ccer &= ~(ATIM_CCER_CC1NP << ((channel - 1) * 4)); + } +#endif /* HAVE_PWM_COMPLEMENTARY */ + +#ifdef HAVE_IP_TIMERS_V2 + /* TODO: OIS5 and OIS6 */ + + cr2 &= ~(ATIM_CR2_OIS5 | ATIM_CR2_OIS6); + + /* TODO: CC5P and CC6P */ + + ccer &= ~(ATIM_CCER_CC5P | ATIM_CCER_CC6P); +#endif /* HAVE_IP_TIMERS_V2 */ + } +#ifdef HAVE_GTIM_CCXNP + else +#endif /* HAVE_GTIM_CCXNP */ +#endif /* HAVE_ADVTIM */ +#ifdef HAVE_GTIM_CCXNP + { + /* CCxNP must be cleared if not ADVANCED timer. + * + * REVISIT: not all families have CCxNP bits for GTIM, + * which causes an ugly condition above + */ + + ccer &= ~(GTIM_CCER_CC1NP << ((channel - 1) * 4)); + } +#endif /* HAVE_GTIM_CCXNP */ + + /* Write registers */ + + pwm_modifyreg(priv, STM32_GTIM_CR2_OFFSET, 0, cr2); + pwm_modifyreg(priv, STM32_GTIM_CCER_OFFSET, 0, ccer); + + return OK; +} + +/**************************************************************************** + * Name: pwm_outputs_enable + * + * Description: + * Enable/disable given timer PWM outputs. + * + * NOTE: This is bulk operation - we can enable/disable many outputs + * at one time + * + * Input Parameters: + * dev - A reference to the lower half PWM driver state structure + * outputs - outputs to set (look at enum stm32_chan_e in stm32_pwm.h) + * state - Enable/disable operation + * + ****************************************************************************/ + +static int pwm_outputs_enable(struct pwm_lowerhalf_s *dev, + uint16_t outputs, bool state) +{ + struct stm32_pwmtimer_s *priv = (struct stm32_pwmtimer_s *)dev; + uint32_t ccer = 0; + uint32_t regval = 0; + + /* Get current register state */ + + ccer = pwm_getreg(priv, STM32_GTIM_CCER_OFFSET); + + /* Get outputs configuration */ + + regval |= ((outputs & STM32_PWM_OUT1) ? GTIM_CCER_CC1E : 0); + regval |= ((outputs & STM32_PWM_OUT1N) ? ATIM_CCER_CC1NE : 0); + regval |= ((outputs & STM32_PWM_OUT2) ? GTIM_CCER_CC2E : 0); + regval |= ((outputs & STM32_PWM_OUT2N) ? ATIM_CCER_CC2NE : 0); + regval |= ((outputs & STM32_PWM_OUT3) ? GTIM_CCER_CC3E : 0); + regval |= ((outputs & STM32_PWM_OUT3N) ? ATIM_CCER_CC3NE : 0); + regval |= ((outputs & STM32_PWM_OUT4) ? GTIM_CCER_CC4E : 0); + + /* NOTE: CC4N doesn't exist, but some docs show configuration bits for it */ + +#ifdef HAVE_IP_TIMERS_V2 + regval |= ((outputs & STM32_PWM_OUT5) ? ATIM_CCER_CC5E : 0); + regval |= ((outputs & STM32_PWM_OUT6) ? ATIM_CCER_CC6E : 0); +#endif + + if (state == true) + { + /* Enable outputs - set bits */ + + ccer |= regval; + } + else + { + /* Disable outputs - reset bits */ + + ccer &= ~regval; + } + + /* Write register */ + + pwm_putreg(priv, STM32_GTIM_CCER_OFFSET, ccer); + + return OK; +} + +#if defined(HAVE_PWM_COMPLEMENTARY) && defined(CONFIG_STM32_PWM_LL_OPS) + +/**************************************************************************** + * Name: pwm_deadtime_update + ****************************************************************************/ + +static int pwm_deadtime_update(struct pwm_lowerhalf_s *dev, uint8_t dt) +{ + struct stm32_pwmtimer_s *priv = (struct stm32_pwmtimer_s *)dev; + uint32_t bdtr = 0; + int ret = OK; + + /* Check if locked */ + + if (priv->lock > 0) + { + ret = -EACCES; + goto errout; + } + + /* Get current register state */ + + bdtr = pwm_getreg(priv, STM32_ATIM_BDTR_OFFSET); + + /* TODO: check if BDTR not locked */ + + /* Update deadtime */ + + bdtr &= ~(ATIM_BDTR_DTG_MASK); + bdtr |= (dt << ATIM_BDTR_DTG_SHIFT); + + /* Write BDTR register */ + + pwm_putreg(priv, STM32_ATIM_BDTR_OFFSET, bdtr); + +errout: + return ret; +} +#endif + +#ifdef HAVE_TRGO +/**************************************************************************** + * Name: pwm_trgo_configure + * + * Description: + * Configure an output synchronisation event for PWM timer (TRGO/TRGO2) + * + ****************************************************************************/ + +static int pwm_trgo_configure(struct pwm_lowerhalf_s *dev, + uint8_t trgo) +{ + struct stm32_pwmtimer_s *priv = (struct stm32_pwmtimer_s *)dev; + uint32_t cr2 = 0; + + /* Configure TRGO (4 LSB in trgo) */ + + cr2 |= (((trgo >> 0) & 0x0f) << ATIM_CR2_MMS_SHIFT) & ATIM_CR2_MMS_MASK; + +#ifdef HAVE_IP_TIMERS_V2 + /* Configure TRGO2 (4 MSB in trgo) */ + + cr2 |= (((trgo >> 4) & 0x0f) << ATIM_CR2_MMS2_SHIFT) & ATIM_CR2_MMS2_MASK; +#endif + + /* Write register */ + + pwm_modifyreg(priv, STM32_GTIM_CR2_OFFSET, 0, cr2); + + return OK; +} +#endif + +/**************************************************************************** + * Name: pwm_soft_update + * + * Description: + * Generate an software update event + * + ****************************************************************************/ + +static int pwm_soft_update(struct pwm_lowerhalf_s *dev) +{ + struct stm32_pwmtimer_s *priv = (struct stm32_pwmtimer_s *)dev; + + pwm_putreg(priv, STM32_GTIM_EGR_OFFSET, GTIM_EGR_UG); + + return OK; +} + +/**************************************************************************** + * Name: pwm_soft_break + * + * Description: + * Generate an software break event + * + * Outputs are enabled if state is false. + * Outputs are disabled if state is true. + * + * NOTE: only timers with complementary outputs have BDTR register and + * support software break. + * + ****************************************************************************/ + +static int pwm_soft_break(struct pwm_lowerhalf_s *dev, bool state) +{ + struct stm32_pwmtimer_s *priv = (struct stm32_pwmtimer_s *)dev; + + if (state == true) + { + /* Reset MOE bit */ + + pwm_modifyreg(priv, STM32_ATIM_BDTR_OFFSET, ATIM_BDTR_MOE, 0); + } + else + { + /* Set MOE bit */ + + pwm_modifyreg(priv, STM32_ATIM_BDTR_OFFSET, 0, ATIM_BDTR_MOE); + } + + return OK; +} + +/**************************************************************************** + * Name: pwm_outputs_from_channels + * + * Description: + * Get enabled outputs configuration from the PWM timer state + * + ****************************************************************************/ + +static uint16_t pwm_outputs_from_channels(struct stm32_pwmtimer_s *priv) +{ + uint16_t outputs = 0; + uint8_t channel = 0; + uint8_t i = 0; + + for (i = 0; i < priv->chan_num; i += 1) + { + /* Get channel */ + + channel = priv->channels[i].channel; + + /* Set outputs if channel configured */ + + if (channel != 0) + { + /* Enable output if configured */ + + if (priv->channels[i].out1.in_use == 1) + { + outputs |= (STM32_PWM_OUT1 << ((channel - 1) * 2)); + } + +#ifdef HAVE_PWM_COMPLEMENTARY + /* Enable complementary output if configured */ + + if (priv->channels[i].out2.in_use == 1) + { + outputs |= (STM32_PWM_OUT1N << ((channel - 1) * 2)); + } +#endif + } + } + + return outputs; +} + +#ifdef HAVE_ADVTIM + +/**************************************************************************** + * Name: pwm_break_dt_configure + * + * Description: + * Configure break and deadtime + * + * NOTE: we have to configure all BDTR registers at once due to possible + * lock configuration + * + ****************************************************************************/ + +static int pwm_break_dt_configure(struct stm32_pwmtimer_s *priv) +{ + uint32_t bdtr = 0; + + /* Set the clock division to zero for all (but the basic timers, but there + * should be no basic timers in this context + */ + + pwm_modifyreg(priv, STM32_GTIM_CR1_OFFSET, GTIM_CR1_CKD_MASK, + priv->t_dts << GTIM_CR1_CKD_SHIFT); + +#ifdef HAVE_PWM_COMPLEMENTARY + /* Initialize deadtime */ + + bdtr |= (priv->deadtime << ATIM_BDTR_DTG_SHIFT); +#endif + +#ifdef HAVE_BREAK + /* Configure Break 1 */ + + if (priv->brk.en1 == 1) + { + /* Enable Break 1 */ + + bdtr |= ATIM_BDTR_BKE; + + /* Set Break 1 polarity */ + + bdtr |= (priv->brk.pol1 == STM32_POL_NEG ? ATIM_BDTR_BKP : 0); + } + +#ifdef HAVE_IP_TIMERS_V2 + /* Configure Break 1 */ + + if (priv->brk.en2 == 1) + { + /* Enable Break 2 */ + + bdtr |= ATIM_BDTR_BK2E; + + /* Set Break 2 polarity */ + + bdtr |= (priv->brk.pol2 == STM32_POL_NEG ? ATIM_BDTR_BK2P : 0); + + /* Configure BRK2 filter */ + + bdtr |= (priv->brk.flt2 << ATIM_BDTR_BK2F_SHIFT); + } +#endif /* HAVE_IP_TIMERS_V2 */ +#endif /* HAVE_BREAK */ + + /* Clear the OSSI and OSSR bits in the BDTR register. + * + * REVISIT: this should be configurable + */ + + bdtr &= ~(ATIM_BDTR_OSSI | ATIM_BDTR_OSSR); + + /* Configure lock */ + + bdtr |= priv->lock << ATIM_BDTR_LOCK_SHIFT; + + /* Write BDTR register at once */ + + pwm_putreg(priv, STM32_ATIM_BDTR_OFFSET, bdtr); + + return OK; +} +#endif + +/**************************************************************************** + * Name: pwm_configure + * + * Description: + * Configure PWM timer in standard mode + * + ****************************************************************************/ + +static int pwm_configure(struct pwm_lowerhalf_s *dev) +{ + struct stm32_pwmtimer_s *priv = (struct stm32_pwmtimer_s *)dev; + uint16_t outputs = 0; + uint8_t j = 0; + int ret = OK; + + /* NOTE: leave timer counter disabled and all outputs disabled! */ + + /* Get configured outputs */ + + outputs = pwm_outputs_from_channels(priv); + + /* Disable outputs */ + + ret = pwm_outputs_enable(dev, outputs, false); + if (ret < 0) + { + goto errout; + } + + /* Disable the timer until we get it configured */ + + pwm_timer_enable(dev, false); + + /* Initial timer configuration */ + + ret = pwm_timer_configure(priv); + if (ret < 0) + { + goto errout; + } + + /* Some special setup for advanced timers */ + +#ifdef HAVE_ADVTIM + if (priv->timtype == TIMTYPE_ADVANCED || + priv->timtype == TIMTYPE_COUNTUP16_N) + { + /* Configure break and deadtime register */ + + ret = pwm_break_dt_configure(priv); + if (ret < 0) + { + goto errout; + } + +#ifdef HAVE_TRGO + /* Configure TRGO/TRGO2 */ + + ret = pwm_trgo_configure(dev, priv->trgo); + if (ret < 0) + { + goto errout; + } +#endif + } +#endif + + /* Configure timer channels */ + + for (j = 0; j < priv->chan_num; j++) + { + /* Skip channel if not in use */ + + if (priv->channels[j].channel != 0) + { + /* Update PWM mode */ + + ret = pwm_mode_configure(dev, priv->channels[j].channel, + priv->channels[j].mode); + if (ret < 0) + { + goto errout; + } + + /* PWM outputs configuration */ + + ret = pwm_output_configure(priv, &priv->channels[j]); + if (ret < 0) + { + goto errout; + } + } + } + + /* Disable software break at the end of the outputs configuration (enablei + * outputs). + * + * NOTE: Only timers with complementary outputs have BDTR register and + * support software break. + */ + + if (priv->timtype == TIMTYPE_ADVANCED || + priv->timtype == TIMTYPE_COUNTUP16_N) + { + ret = pwm_soft_break(dev, false); + if (ret < 0) + { + goto errout; + } + } + +errout: + return ret; +} + +/**************************************************************************** + * Name: pwm_duty_channels_update + * + * Description: + * Update duty cycle for given channels + * + ****************************************************************************/ + +static int pwm_duty_channels_update(struct pwm_lowerhalf_s *dev, + const struct pwm_info_s *info) +{ + struct stm32_pwmtimer_s *priv = (struct stm32_pwmtimer_s *)dev; + uint8_t channel = 0; + ub16_t duty = 0; + int ret = OK; + int i = 0; + int j = 0; + + for (i = 0; i < CONFIG_PWM_NCHANNELS; i++) + { + /* Break the loop if all following channels are not configured */ + + if (info->channels[i].channel == -1) + { + break; + } + + duty = info->channels[i].duty; + channel = info->channels[i].channel; + + /* A value of zero means to skip this channel */ + + if (channel != 0) + { + /* Find the channel */ + + for (j = 0; j < priv->chan_num; j++) + { + if (priv->channels[j].channel == channel) + { + break; + } + } + + /* Check range */ + + if (j >= priv->chan_num) + { + pwmerr("ERROR: No such channel: %u\n", channel); + ret = -EINVAL; + goto errout; + } + + /* Update duty cycle */ + + ret = pwm_duty_update(dev, channel, duty); + if (ret < 0) + { + goto errout; + } + } + } + +errout: + return OK; +} + +/**************************************************************************** + * Name: pwm_timer + * + * Description: + * (Re-)initialize the timer resources and start the pulsed output + * + * Input Parameters: + * dev - A reference to the lower half PWM driver state structure + * info - A reference to the characteristics of the pulsed output + * + * Returned Value: + * Zero on success; a negated errno value on failure + * + ****************************************************************************/ + +static int pwm_timer(struct pwm_lowerhalf_s *dev, + const struct pwm_info_s *info) +{ + struct stm32_pwmtimer_s *priv = (struct stm32_pwmtimer_s *)dev; + uint16_t outputs = 0; + int ret = OK; + + DEBUGASSERT(priv != NULL && info != NULL); + + pwminfo("TIM%u frequency: %" PRIu32 "\n", + priv->timid, info->frequency); + + DEBUGASSERT(info->frequency > 0); + + /* TODO: what if we have pwm running and we want disable some channels ? */ + + /* Set timer frequency */ + + ret = pwm_frequency_update(dev, info->frequency); + if (ret < 0) + { + goto errout; + } + + /* Channel specific configuration */ + + ret = pwm_duty_channels_update(dev, info); + if (ret < 0) + { + goto errout; + } + + /* Set the advanced timer's repetition counter */ + +#ifdef HAVE_ADVTIM + if (priv->timtype == TIMTYPE_ADVANCED || + priv->timtype == TIMTYPE_COUNTUP16_N) + { + /* If a non-zero repetition count has been selected, then set the + * repetition counter to the count-1 (pwm_start() has already + * assured us that the count value is within range). + */ + + /* Set the repetition counter to zero */ + + pwm_rcr_update(dev, 0); + + /* Generate an update event to reload the prescaler */ + + pwm_soft_update(dev); + } + else +#endif + { + /* Generate an update event to reload the prescaler (all timers) */ + + pwm_soft_update(dev); + } + + /* Get configured outputs */ + + outputs = pwm_outputs_from_channels(priv); + + /* Enable outputs */ + + ret = pwm_outputs_enable(dev, outputs, true); + if (ret < 0) + { + goto errout; + } + + /* Just enable the timer, leaving all interrupts disabled */ + + pwm_timer_enable(dev, true); + + pwm_dumpregs(dev, "After starting"); + +errout: + return ret; +} + +/**************************************************************************** + * Name: pwm_set_apb_clock + * + * Description: + * Enable or disable APB clock for the timer peripheral + * + * Input Parameters: + * priv - A reference to the PWM block status + * on - Enable clock if 'on' is 'true' and disable if 'false' + * + ****************************************************************************/ + +static int pwm_set_apb_clock(struct stm32_pwmtimer_s *priv, bool on) +{ + uint32_t en_bit = 0; + uint32_t regaddr = 0; + int ret = OK; + + pwminfo("timer %d clock enable: %d\n", priv->timid, on ? 1 : 0); + + /* Determine which timer to configure */ + + switch (priv->timid) + { +#ifdef CONFIG_STM32_TIM1_PWM + case 1: + { + regaddr = TIMRCCEN_TIM1; + en_bit = TIMEN_TIM1; + break; + } +#endif + +#ifdef CONFIG_STM32_TIM2_PWM + case 2: + { + regaddr = TIMRCCEN_TIM2; + en_bit = TIMEN_TIM2; + break; + } +#endif + +#ifdef CONFIG_STM32_TIM3_PWM + case 3: + { + regaddr = TIMRCCEN_TIM3; + en_bit = TIMEN_TIM3; + break; + } +#endif + +#ifdef CONFIG_STM32_TIM4_PWM + case 4: + { + regaddr = TIMRCCEN_TIM4; + en_bit = TIMEN_TIM4; + break; + } +#endif + +#ifdef CONFIG_STM32_TIM5_PWM + case 5: + { + regaddr = TIMRCCEN_TIM5; + en_bit = TIMEN_TIM5; + break; + } +#endif + +#ifdef CONFIG_STM32_TIM8_PWM + case 8: + { + regaddr = TIMRCCEN_TIM8; + en_bit = TIMEN_TIM8; + break; + } +#endif + +#ifdef CONFIG_STM32_TIM9_PWM + case 9: + { + regaddr = TIMRCCEN_TIM9; + en_bit = TIMEN_TIM9; + break; + } +#endif + +#ifdef CONFIG_STM32_TIM10_PWM + case 10: + { + regaddr = TIMRCCEN_TIM10; + en_bit = TIMEN_TIM10; + break; + } +#endif + +#ifdef CONFIG_STM32_TIM11_PWM + case 11: + { + regaddr = TIMRCCEN_TIM11; + en_bit = TIMEN_TIM11; + break; + } +#endif + +#ifdef CONFIG_STM32_TIM12_PWM + case 12: + { + regaddr = TIMRCCEN_TIM12; + en_bit = TIMEN_TIM12; + break; + } +#endif + +#ifdef CONFIG_STM32_TIM13_PWM + case 13: + { + regaddr = TIMRCCEN_TIM13; + en_bit = TIMEN_TIM13; + break; + } +#endif + +#ifdef CONFIG_STM32_TIM14_PWM + case 14: + { + regaddr = TIMRCCEN_TIM14; + en_bit = TIMEN_TIM14; + break; + } +#endif + +#ifdef CONFIG_STM32_TIM15_PWM + case 15: + { + regaddr = TIMRCCEN_TIM15; + en_bit = TIMEN_TIM15; + break; + } +#endif + +#ifdef CONFIG_STM32_TIM16_PWM + case 16: + { + regaddr = TIMRCCEN_TIM16; + en_bit = TIMEN_TIM16; + break; + } +#endif + +#ifdef CONFIG_STM32_TIM17_PWM + case 17: + { + regaddr = TIMRCCEN_TIM17; + en_bit = TIMEN_TIM17; + break; + } +#endif + + default: + { + pwmerr("ERROR: No such timer configured %d\n", priv->timid); + ret = -EINVAL; + goto errout; + } + } + + /* Enable/disable APB 1/2 clock for timer */ + + pwminfo("RCC_APBxENR base: %08" PRIx32 " bits: %04" PRIx32 "\n", + regaddr, en_bit); + + if (on) + { + modifyreg32(regaddr, 0, en_bit); + } + else + { + modifyreg32(regaddr, en_bit, 0); + } + +errout: + return ret; +} + +/**************************************************************************** + * Name: pwm_setup + * + * Description: + * This method is called when the driver is opened. The lower half driver + * should configure and initialize the device so that it is ready for use. + * It should not, however, output pulses until the start method is called. + * + * Input Parameters: + * dev - A reference to the lower half PWM driver state structure + * + * Returned Value: + * Zero on success; a negated errno value on failure + * + * Assumptions: + * APB1 or 2 clocking for the GPIOs has already been configured by the RCC + * logic at power up. + * + ****************************************************************************/ + +static int pwm_setup(struct pwm_lowerhalf_s *dev) +{ + struct stm32_pwmtimer_s *priv = (struct stm32_pwmtimer_s *)dev; + uint32_t pincfg = 0; + int ret = OK; + int i = 0; + + pwminfo("TIM%u\n", priv->timid); + + /* Enable APB1/2 clocking for timer. */ + + ret = pwm_set_apb_clock(priv, true); + if (ret < 0) + { + goto errout; + } + + pwm_dumpregs(dev, "Initially"); + + /* Configure the PWM output pins, but do not start the timer yet */ + + for (i = 0; i < priv->chan_num; i++) + { + if (priv->channels[i].out1.in_use == 1) + { + /* Do not configure the pin if pincfg is not specified. + * This prevents overwriting the PA0 configuration if the + * channel is used internally. + */ + + pincfg = priv->channels[i].out1.pincfg; + if (pincfg != 0) + { + pwminfo("pincfg: %08" PRIx32 "\n", pincfg); + + stm32_configgpio(pincfg); + pwm_dumpgpio(pincfg, "PWM setup"); + } + } + +#ifdef HAVE_PWM_COMPLEMENTARY + if (priv->channels[i].out2.in_use == 1) + { + pincfg = priv->channels[i].out2.pincfg; + + /* Do not configure the pin if pincfg is not specified. + * This prevents overwriting the PA0 configuration if the + * channel is used internally. + */ + + if (pincfg != 0) + { + pwminfo("pincfg: %08" PRIx32 "\n", pincfg); + + stm32_configgpio(pincfg); + pwm_dumpgpio(pincfg, "PWM setup"); + } + } +#endif + } + + /* Configure PWM timer with the selected configuration. + * + * NOTE: We configure PWM here during setup, but leave timer with disabled + * counter, disabled outputs, not configured frequency and duty cycle + */ + + { + ret = pwm_configure(dev); + } + + if (ret < 0) + { + pwmerr("failed to configure PWM %d\n", priv->timid); + ret = ERROR; + goto errout; + } + +errout: + return ret; +} + +/**************************************************************************** + * Name: pwm_shutdown + * + * Description: + * This method is called when the driver is closed. The lower half driver + * stop pulsed output, free any resources, disable the timer hardware, and + * put the system into the lowest possible power usage state + * + * Input Parameters: + * dev - A reference to the lower half PWM driver state structure + * + * Returned Value: + * Zero on success; a negated errno value on failure + * + ****************************************************************************/ + +static int pwm_shutdown(struct pwm_lowerhalf_s *dev) +{ + struct stm32_pwmtimer_s *priv = (struct stm32_pwmtimer_s *)dev; + uint32_t pincfg = 0; + int i = 0; + int ret = OK; + + pwminfo("TIM%u\n", priv->timid); + + /* Make sure that the output has been stopped */ + + pwm_stop(dev); + + /* Disable APB1/2 clocking for timer. */ + + ret = pwm_set_apb_clock(priv, false); + if (ret < 0) + { + goto errout; + } + + /* Then put the GPIO pins back to the default state */ + + for (i = 0; i < priv->chan_num; i++) + { + pincfg = priv->channels[i].out1.pincfg; + if (pincfg != 0) + { + pwminfo("pincfg: %08" PRIx32 "\n", pincfg); + + pincfg &= (GPIO_PORT_MASK | GPIO_PIN_MASK); + pincfg |= PINCFG_DEFAULT; + + stm32_configgpio(pincfg); + } + +#ifdef HAVE_PWM_COMPLEMENTARY + pincfg = priv->channels[i].out2.pincfg; + if (pincfg != 0) + { + pwminfo("pincfg: %08" PRIx32 "\n", pincfg); + + pincfg &= (GPIO_PORT_MASK | GPIO_PIN_MASK); + pincfg |= PINCFG_DEFAULT; + + stm32_configgpio(pincfg); + } +#endif + } + +errout: + return ret; +} + +/**************************************************************************** + * Name: pwm_start + * + * Description: + * (Re-)initialize the timer resources and start the pulsed output + * + * Input Parameters: + * dev - A reference to the lower half PWM driver state structure + * info - A reference to the characteristics of the pulsed output + * + * Returned Value: + * Zero on success; a negated errno value on failure + * + ****************************************************************************/ + +static int pwm_start(struct pwm_lowerhalf_s *dev, + const struct pwm_info_s *info) +{ + struct stm32_pwmtimer_s *priv = (struct stm32_pwmtimer_s *)dev; + int ret = OK; + + /* if frequency has not changed we just update duty */ + + if (info->frequency == priv->frequency) + { + int i; + + for (i = 0; ret == OK && i < CONFIG_PWM_NCHANNELS; i++) + { + /* Break the loop if all following channels are not configured */ + + if (info->channels[i].channel == -1) + { + break; + } + + /* Set output if channel configured */ + + if (info->channels[i].channel != 0) + { + ret = pwm_duty_update(dev, info->channels[i].channel, + info->channels[i].duty); + } + } + } + else + { + ret = pwm_timer(dev, info); + + /* Save current frequency */ + + if (ret == OK) + { + priv->frequency = info->frequency; + } + } + + return ret; +} + +/**************************************************************************** + * Name: pwm_stop + * + * Description: + * Stop the pulsed output and reset the timer resources + * + * Input Parameters: + * dev - A reference to the lower half PWM driver state structure + * + * Returned Value: + * Zero on success; a negated errno value on failure + * + * Assumptions: + * This function is called to stop the pulsed output at anytime. This + * method is also called from the timer interrupt handler when a repetition + * count expires... automatically stopping the timer. + * + ****************************************************************************/ + +static int pwm_stop(struct pwm_lowerhalf_s *dev) +{ + struct stm32_pwmtimer_s *priv = (struct stm32_pwmtimer_s *)dev; + irqstate_t flags = 0; + uint16_t outputs = 0; + int ret = OK; + + pwminfo("TIM%u\n", priv->timid); + + /* Disable interrupts momentary to stop any ongoing timer processing and + * to prevent any concurrent access to the reset register. + */ + + flags = enter_critical_section(); + + /* Stopped so frequency is zero */ + + priv->frequency = 0; + + /* Disable further interrupts and stop the timer */ + + pwm_putreg(priv, STM32_GTIM_DIER_OFFSET, 0); + pwm_putreg(priv, STM32_GTIM_SR_OFFSET, 0); + + /* Disable the timer and timer outputs */ + + pwm_timer_enable(dev, false); + outputs = pwm_outputs_from_channels(priv); + ret = pwm_outputs_enable(dev, outputs, false); + + /* Clear all channels */ + + pwm_putreg(priv, STM32_GTIM_CCR1_OFFSET, 0); + pwm_putreg(priv, STM32_GTIM_CCR2_OFFSET, 0); + pwm_putreg(priv, STM32_GTIM_CCR3_OFFSET, 0); + pwm_putreg(priv, STM32_GTIM_CCR4_OFFSET, 0); + + leave_critical_section(flags); + + pwm_dumpregs(dev, "After stop"); + + return ret; +} + +/**************************************************************************** + * Name: pwm_ioctl + * + * Description: + * Lower-half logic may support platform-specific ioctl commands + * + * Input Parameters: + * dev - A reference to the lower half PWM driver state structure + * cmd - The ioctl command + * arg - The argument accompanying the ioctl command + * + * Returned Value: + * Zero on success; a negated errno value on failure + * + ****************************************************************************/ + +static int pwm_ioctl(struct pwm_lowerhalf_s *dev, int cmd, + unsigned long arg) +{ +#ifdef CONFIG_DEBUG_PWM_INFO + struct stm32_pwmtimer_s *priv = (struct stm32_pwmtimer_s *)dev; + + /* There are no platform-specific ioctl commands */ + + pwminfo("TIM%u\n", priv->timid); +#endif + return -ENOTTY; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_pwminitialize + * + * Description: + * Initialize one timer for use with the upper_level PWM driver. + * + * Input Parameters: + * timer - A number identifying the timer use. The number of valid timer + * IDs varies with the STM32 MCU and MCU family but is somewhere in + * the range of {1,..,17}. + * + * Returned Value: + * On success, a pointer to the STM32 lower half PWM driver is returned. + * NULL is returned on any failure. + * + ****************************************************************************/ + +struct pwm_lowerhalf_s *stm32_pwminitialize(int timer) +{ + struct stm32_pwmtimer_s *lower = NULL; + + pwminfo("TIM%u\n", timer); + + switch (timer) + { +#ifdef CONFIG_STM32_TIM1_PWM + case 1: + { + lower = &g_pwm1dev; + + /* Attach but disable the TIM1 update interrupt */ + + break; + } +#endif + +#ifdef CONFIG_STM32_TIM2_PWM + case 2: + { + lower = &g_pwm2dev; + break; + } +#endif + +#ifdef CONFIG_STM32_TIM3_PWM + case 3: + { + lower = &g_pwm3dev; + break; + } +#endif + +#ifdef CONFIG_STM32_TIM4_PWM + case 4: + { + lower = &g_pwm4dev; + break; + } +#endif + +#ifdef CONFIG_STM32_TIM5_PWM + case 5: + { + lower = &g_pwm5dev; + break; + } +#endif + +#ifdef CONFIG_STM32_TIM8_PWM + case 8: + { + lower = &g_pwm8dev; + + /* Attach but disable the TIM8 update interrupt */ + + break; + } +#endif + +#ifdef CONFIG_STM32_TIM9_PWM + case 9: + { + lower = &g_pwm9dev; + break; + } +#endif + +#ifdef CONFIG_STM32_TIM10_PWM + case 10: + { + lower = &g_pwm10dev; + break; + } + +#endif + +#ifdef CONFIG_STM32_TIM11_PWM + case 11: + { + lower = &g_pwm11dev; + break; + } +#endif + +#ifdef CONFIG_STM32_TIM12_PWM + case 12: + { + lower = &g_pwm12dev; + break; + } +#endif + +#ifdef CONFIG_STM32_TIM13_PWM + case 13: + { + lower = &g_pwm13dev; + break; + } +#endif + +#ifdef CONFIG_STM32_TIM14_PWM + case 14: + { + lower = &g_pwm14dev; + break; + } +#endif + +#ifdef CONFIG_STM32_TIM15_PWM + case 15: + { + lower = &g_pwm15dev; + break; + } +#endif + +#ifdef CONFIG_STM32_TIM16_PWM + case 16: + { + lower = &g_pwm16dev; + break; + } +#endif + +#ifdef CONFIG_STM32_TIM17_PWM + case 17: + { + lower = &g_pwm17dev; + break; + } +#endif + + default: + { + pwmerr("ERROR: No such timer configured %d\n", timer); + lower = NULL; + goto errout; + } + } + +errout: + return (struct pwm_lowerhalf_s *)lower; +} + +#endif /* CONFIG_STM32_PWM */ diff --git a/arch/arm/src/common/stm32/stm32_pwm_m3m4_v1v2v3.h b/arch/arm/src/common/stm32/stm32_pwm_m3m4_v1v2v3.h new file mode 100644 index 0000000000000..032a0410d40d4 --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_pwm_m3m4_v1v2v3.h @@ -0,0 +1,1178 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_pwm_m3m4_v1v2v3.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_PWM_V1V2V3_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_PWM_V1V2V3_H + +/* The STM32 does not have dedicated PWM hardware. Rather, pulsed output + * control is a capability of the STM32 timers. The logic in this file + * implements the lower half of the standard, NuttX PWM interface using the + * STM32 timers. That interface is described in include/nuttx/timers/pwm.h. + */ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include "chip.h" + +#ifdef CONFIG_STM32_PWM +# include +# include "hardware/stm32_tim.h" +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* Timer devices may be used for different purposes. One special purpose is + * to generate modulated outputs for such things as motor control. + * If CONFIG_STM32_TIMn is defined then the CONFIG_STM32_TIMn_PWM must also + * be defined to indicate that timer "n" is intended to be used for pulsed + * output signal generation. + */ + +#ifndef CONFIG_STM32_TIM1 +# undef CONFIG_STM32_TIM1_PWM +#endif +#ifndef CONFIG_STM32_TIM2 +# undef CONFIG_STM32_TIM2_PWM +#endif +#ifndef CONFIG_STM32_TIM3 +# undef CONFIG_STM32_TIM3_PWM +#endif +#ifndef CONFIG_STM32_TIM4 +# undef CONFIG_STM32_TIM4_PWM +#endif +#ifndef CONFIG_STM32_TIM5 +# undef CONFIG_STM32_TIM5_PWM +#endif +#ifndef CONFIG_STM32_TIM8 +# undef CONFIG_STM32_TIM8_PWM +#endif +#ifndef CONFIG_STM32_TIM9 +# undef CONFIG_STM32_TIM9_PWM +#endif +#ifndef CONFIG_STM32_TIM10 +# undef CONFIG_STM32_TIM10_PWM +#endif +#ifndef CONFIG_STM32_TIM11 +# undef CONFIG_STM32_TIM11_PWM +#endif +#ifndef CONFIG_STM32_TIM12 +# undef CONFIG_STM32_TIM12_PWM +#endif +#ifndef CONFIG_STM32_TIM13 +# undef CONFIG_STM32_TIM13_PWM +#endif +#ifndef CONFIG_STM32_TIM14 +# undef CONFIG_STM32_TIM14_PWM +#endif +#ifndef CONFIG_STM32_TIM15 +# undef CONFIG_STM32_TIM15_PWM +#endif +#ifndef CONFIG_STM32_TIM16 +# undef CONFIG_STM32_TIM16_PWM +#endif +#ifndef CONFIG_STM32_TIM17 +# undef CONFIG_STM32_TIM17_PWM +#endif + +/* The basic timers (timer 6 and 7) are not capable of generating output + * pulses + */ + +#undef CONFIG_STM32_TIM6_PWM +#undef CONFIG_STM32_TIM7_PWM + +/* Check if PWM support for any channel is enabled. */ + +#ifdef CONFIG_STM32_PWM + +/* PWM driver channels configuration */ + +#ifdef CONFIG_STM32_PWM_MULTICHAN + +#ifdef CONFIG_STM32_TIM1_CHANNEL1 +# define PWM_TIM1_CHANNEL1 1 +#else +# define PWM_TIM1_CHANNEL1 0 +#endif +#ifdef CONFIG_STM32_TIM1_CHANNEL2 +# define PWM_TIM1_CHANNEL2 1 +#else +# define PWM_TIM1_CHANNEL2 0 +#endif +#ifdef CONFIG_STM32_TIM1_CHANNEL3 +# define PWM_TIM1_CHANNEL3 1 +#else +# define PWM_TIM1_CHANNEL3 0 +#endif +#ifdef CONFIG_STM32_TIM1_CHANNEL4 +# define PWM_TIM1_CHANNEL4 1 +#else +# define PWM_TIM1_CHANNEL4 0 +#endif +#ifdef CONFIG_STM32_TIM1_CHANNEL5 +# define PWM_TIM1_CHANNEL5 1 +#else +# define PWM_TIM1_CHANNEL5 0 +#endif +#ifdef CONFIG_STM32_TIM1_CHANNEL6 +# define PWM_TIM1_CHANNEL6 1 +#else +# define PWM_TIM1_CHANNEL6 0 +#endif +#define PWM_TIM1_NCHANNELS (PWM_TIM1_CHANNEL1 + PWM_TIM1_CHANNEL2 + \ + PWM_TIM1_CHANNEL3 + PWM_TIM1_CHANNEL4 + \ + PWM_TIM1_CHANNEL5 + PWM_TIM1_CHANNEL6) + +#ifdef CONFIG_STM32_TIM2_CHANNEL1 +# define PWM_TIM2_CHANNEL1 1 +#else +# define PWM_TIM2_CHANNEL1 0 +#endif +#ifdef CONFIG_STM32_TIM2_CHANNEL2 +# define PWM_TIM2_CHANNEL2 1 +#else +# define PWM_TIM2_CHANNEL2 0 +#endif +#ifdef CONFIG_STM32_TIM2_CHANNEL3 +# define PWM_TIM2_CHANNEL3 1 +#else +# define PWM_TIM2_CHANNEL3 0 +#endif +#ifdef CONFIG_STM32_TIM2_CHANNEL4 +# define PWM_TIM2_CHANNEL4 1 +#else +# define PWM_TIM2_CHANNEL4 0 +#endif +#define PWM_TIM2_NCHANNELS (PWM_TIM2_CHANNEL1 + PWM_TIM2_CHANNEL2 + \ + PWM_TIM2_CHANNEL3 + PWM_TIM2_CHANNEL4) + +#ifdef CONFIG_STM32_TIM3_CHANNEL1 +# define PWM_TIM3_CHANNEL1 1 +#else +# define PWM_TIM3_CHANNEL1 0 +#endif +#ifdef CONFIG_STM32_TIM3_CHANNEL2 +# define PWM_TIM3_CHANNEL2 1 +#else +# define PWM_TIM3_CHANNEL2 0 +#endif +#ifdef CONFIG_STM32_TIM3_CHANNEL3 +# define PWM_TIM3_CHANNEL3 1 +#else +# define PWM_TIM3_CHANNEL3 0 +#endif +#ifdef CONFIG_STM32_TIM3_CHANNEL4 +# define PWM_TIM3_CHANNEL4 1 +#else +# define PWM_TIM3_CHANNEL4 0 +#endif +#define PWM_TIM3_NCHANNELS (PWM_TIM3_CHANNEL1 + PWM_TIM3_CHANNEL2 + \ + PWM_TIM3_CHANNEL3 + PWM_TIM3_CHANNEL4) + +#ifdef CONFIG_STM32_TIM4_CHANNEL1 +# define PWM_TIM4_CHANNEL1 1 +#else +# define PWM_TIM4_CHANNEL1 0 +#endif +#ifdef CONFIG_STM32_TIM4_CHANNEL2 +# define PWM_TIM4_CHANNEL2 1 +#else +# define PWM_TIM4_CHANNEL2 0 +#endif +#ifdef CONFIG_STM32_TIM4_CHANNEL3 +# define PWM_TIM4_CHANNEL3 1 +#else +# define PWM_TIM4_CHANNEL3 0 +#endif +#ifdef CONFIG_STM32_TIM4_CHANNEL4 +# define PWM_TIM4_CHANNEL4 1 +#else +# define PWM_TIM4_CHANNEL4 0 +#endif +#define PWM_TIM4_NCHANNELS (PWM_TIM4_CHANNEL1 + PWM_TIM4_CHANNEL2 + \ + PWM_TIM4_CHANNEL3 + PWM_TIM4_CHANNEL4) + +#ifdef CONFIG_STM32_TIM5_CHANNEL1 +# define PWM_TIM5_CHANNEL1 1 +#else +# define PWM_TIM5_CHANNEL1 0 +#endif +#ifdef CONFIG_STM32_TIM5_CHANNEL2 +# define PWM_TIM5_CHANNEL2 1 +#else +# define PWM_TIM5_CHANNEL2 0 +#endif +#ifdef CONFIG_STM32_TIM5_CHANNEL3 +# define PWM_TIM5_CHANNEL3 1 +#else +# define PWM_TIM5_CHANNEL3 0 +#endif +#ifdef CONFIG_STM32_TIM5_CHANNEL4 +# define PWM_TIM5_CHANNEL4 1 +#else +# define PWM_TIM5_CHANNEL4 0 +#endif +#define PWM_TIM5_NCHANNELS (PWM_TIM5_CHANNEL1 + PWM_TIM5_CHANNEL2 + \ + PWM_TIM5_CHANNEL3 + PWM_TIM5_CHANNEL4) + +#ifdef CONFIG_STM32_TIM8_CHANNEL1 +# define PWM_TIM8_CHANNEL1 1 +#else +# define PWM_TIM8_CHANNEL1 0 +#endif +#ifdef CONFIG_STM32_TIM8_CHANNEL2 +# define PWM_TIM8_CHANNEL2 1 +#else +# define PWM_TIM8_CHANNEL2 0 +#endif +#ifdef CONFIG_STM32_TIM8_CHANNEL3 +# define PWM_TIM8_CHANNEL3 1 +#else +# define PWM_TIM8_CHANNEL3 0 +#endif +#ifdef CONFIG_STM32_TIM8_CHANNEL4 +# define PWM_TIM8_CHANNEL4 1 +#else +# define PWM_TIM8_CHANNEL4 0 +#endif +#ifdef CONFIG_STM32_TIM8_CHANNEL5 +# define PWM_TIM8_CHANNEL5 1 +#else +# define PWM_TIM8_CHANNEL5 0 +#endif +#ifdef CONFIG_STM32_TIM8_CHANNEL6 +# define PWM_TIM8_CHANNEL6 1 +#else +# define PWM_TIM8_CHANNEL6 0 +#endif +#define PWM_TIM8_NCHANNELS (PWM_TIM8_CHANNEL1 + PWM_TIM8_CHANNEL2 + \ + PWM_TIM8_CHANNEL3 + PWM_TIM8_CHANNEL4 + \ + PWM_TIM8_CHANNEL5 + PWM_TIM8_CHANNEL6) + +#ifdef CONFIG_STM32_TIM9_CHANNEL1 +# define PWM_TIM9_CHANNEL1 1 +#else +# define PWM_TIM9_CHANNEL1 0 +#endif +#ifdef CONFIG_STM32_TIM9_CHANNEL2 +# define PWM_TIM9_CHANNEL2 1 +#else +# define PWM_TIM9_CHANNEL2 0 +#endif +#define PWM_TIM9_NCHANNELS (PWM_TIM9_CHANNEL1 + PWM_TIM9_CHANNEL2) + +#ifdef CONFIG_STM32_TIM10_CHANNEL1 +# define PWM_TIM10_CHANNEL1 1 +#else +# define PWM_TIM10_CHANNEL1 0 +#endif +#define PWM_TIM10_NCHANNELS (PWM_TIM10_CHANNEL1) + +#ifdef CONFIG_STM32_TIM11_CHANNEL1 +# define PWM_TIM11_CHANNEL1 1 +#else +# define PWM_TIM11_CHANNEL1 0 +#endif +#define PWM_TIM11_NCHANNELS (PWM_TIM11_CHANNEL1) + +#ifdef CONFIG_STM32_TIM12_CHANNEL1 +# define PWM_TIM12_CHANNEL1 1 +#else +# define PWM_TIM12_CHANNEL1 0 +#endif +#ifdef CONFIG_STM32_TIM12_CHANNEL2 +# define PWM_TIM12_CHANNEL2 1 +#else +# define PWM_TIM12_CHANNEL2 0 +#endif +#define PWM_TIM12_NCHANNELS (PWM_TIM12_CHANNEL1 + PWM_TIM12_CHANNEL2) + +#ifdef CONFIG_STM32_TIM13_CHANNEL1 +# define PWM_TIM13_CHANNEL1 1 +#else +# define PWM_TIM13_CHANNEL1 0 +#endif +#define PWM_TIM13_NCHANNELS (PWM_TIM13_CHANNEL1) + +#ifdef CONFIG_STM32_TIM14_CHANNEL1 +# define PWM_TIM14_CHANNEL1 1 +#else +# define PWM_TIM14_CHANNEL1 0 +#endif +#define PWM_TIM14_NCHANNELS (PWM_TIM14_CHANNEL1) + +#ifdef CONFIG_STM32_TIM15_CHANNEL1 +# define PWM_TIM15_CHANNEL1 1 +#else +# define PWM_TIM15_CHANNEL1 0 +#endif +#ifdef CONFIG_STM32_TIM15_CHANNEL2 +# define PWM_TIM15_CHANNEL2 1 +#else +# define PWM_TIM15_CHANNEL2 0 +#endif +#define PWM_TIM15_NCHANNELS (PWM_TIM15_CHANNEL1 + PWM_TIM15_CHANNEL2) + +#ifdef CONFIG_STM32_TIM16_CHANNEL1 +# define PWM_TIM16_CHANNEL1 1 +#else +# define PWM_TIM16_CHANNEL1 0 +#endif +#define PWM_TIM16_NCHANNELS PWM_TIM16_CHANNEL1 + +#ifdef CONFIG_STM32_TIM17_CHANNEL1 +# define PWM_TIM17_CHANNEL1 1 +#else +# define PWM_TIM17_CHANNEL1 0 +#endif +#define PWM_TIM17_NCHANNELS PWM_TIM17_CHANNEL1 + +#else /* !CONFIG_STM32_PWM_MULTICHAN */ + +/* For each timer that is enabled for PWM usage, we need the following + * additional configuration settings: + * + * CONFIG_STM32_TIMx_CHANNEL - Specifies the timer output channel {1,..,4} + * PWM_TIMx_CHn - One of the values defined in chip/stm32*_pinmap.h. In the + * case where there are multiple pin selections, the correct setting must be + * provided in the arch/board/board.h file. + * + * NOTE: The STM32 timers are each capable of generating different signals on + * each of the four channels with different duty cycles. That capability is + * not supported by this driver: Only one output channel per timer. + */ + +#ifdef CONFIG_STM32_TIM1_PWM +# if !defined(CONFIG_STM32_TIM1_CHANNEL) +# error "CONFIG_STM32_TIM1_CHANNEL must be provided" +# elif CONFIG_STM32_TIM1_CHANNEL == 1 +# define CONFIG_STM32_TIM1_CHANNEL1 1 +# define CONFIG_STM32_TIM1_CH1MODE CONFIG_STM32_TIM1_CHMODE +# elif CONFIG_STM32_TIM1_CHANNEL == 2 +# define CONFIG_STM32_TIM1_CHANNEL2 1 +# define CONFIG_STM32_TIM1_CH2MODE CONFIG_STM32_TIM1_CHMODE +# elif CONFIG_STM32_TIM1_CHANNEL == 3 +# define CONFIG_STM32_TIM1_CHANNEL3 1 +# define CONFIG_STM32_TIM1_CH3MODE CONFIG_STM32_TIM1_CHMODE +# elif CONFIG_STM32_TIM1_CHANNEL == 4 +# define CONFIG_STM32_TIM1_CHANNEL4 1 +# define CONFIG_STM32_TIM1_CH4MODE CONFIG_STM32_TIM1_CHMODE +# else +# error "Unsupported value of CONFIG_STM32_TIM1_CHANNEL" +# endif +# define PWM_TIM1_NCHANNELS 1 +#endif + +#ifdef CONFIG_STM32_TIM2_PWM +# if !defined(CONFIG_STM32_TIM2_CHANNEL) +# error "CONFIG_STM32_TIM2_CHANNEL must be provided" +# elif CONFIG_STM32_TIM2_CHANNEL == 1 +# define CONFIG_STM32_TIM2_CHANNEL1 1 +# define CONFIG_STM32_TIM2_CH1MODE CONFIG_STM32_TIM2_CHMODE +# elif CONFIG_STM32_TIM2_CHANNEL == 2 +# define CONFIG_STM32_TIM2_CHANNEL2 1 +# define CONFIG_STM32_TIM2_CH2MODE CONFIG_STM32_TIM2_CHMODE +# elif CONFIG_STM32_TIM2_CHANNEL == 3 +# define CONFIG_STM32_TIM2_CHANNEL3 1 +# define CONFIG_STM32_TIM2_CH3MODE CONFIG_STM32_TIM2_CHMODE +# elif CONFIG_STM32_TIM2_CHANNEL == 4 +# define CONFIG_STM32_TIM2_CHANNEL4 1 +# define CONFIG_STM32_TIM2_CH4MODE CONFIG_STM32_TIM2_CHMODE +# else +# error "Unsupported value of CONFIG_STM32_TIM2_CHANNEL" +# endif +# define PWM_TIM2_NCHANNELS 1 +#endif + +#ifdef CONFIG_STM32_TIM3_PWM +# if !defined(CONFIG_STM32_TIM3_CHANNEL) +# error "CONFIG_STM32_TIM3_CHANNEL must be provided" +# elif CONFIG_STM32_TIM3_CHANNEL == 1 +# define CONFIG_STM32_TIM3_CHANNEL1 1 +# define CONFIG_STM32_TIM3_CH1MODE CONFIG_STM32_TIM3_CHMODE +# elif CONFIG_STM32_TIM3_CHANNEL == 2 +# define CONFIG_STM32_TIM3_CHANNEL2 1 +# define CONFIG_STM32_TIM3_CH2MODE CONFIG_STM32_TIM3_CHMODE +# elif CONFIG_STM32_TIM3_CHANNEL == 3 +# define CONFIG_STM32_TIM3_CHANNEL3 1 +# define CONFIG_STM32_TIM3_CH3MODE CONFIG_STM32_TIM3_CHMODE +# elif CONFIG_STM32_TIM3_CHANNEL == 4 +# define CONFIG_STM32_TIM3_CHANNEL4 1 +# define CONFIG_STM32_TIM3_CH4MODE CONFIG_STM32_TIM3_CHMODE +# else +# error "Unsupported value of CONFIG_STM32_TIM3_CHANNEL" +# endif +# define PWM_TIM3_NCHANNELS 1 +#endif + +#ifdef CONFIG_STM32_TIM4_PWM +# if !defined(CONFIG_STM32_TIM4_CHANNEL) +# error "CONFIG_STM32_TIM4_CHANNEL must be provided" +# elif CONFIG_STM32_TIM4_CHANNEL == 1 +# define CONFIG_STM32_TIM4_CHANNEL1 1 +# define CONFIG_STM32_TIM4_CH1MODE CONFIG_STM32_TIM4_CHMODE +# elif CONFIG_STM32_TIM4_CHANNEL == 2 +# define CONFIG_STM32_TIM4_CHANNEL2 1 +# define CONFIG_STM32_TIM4_CH2MODE CONFIG_STM32_TIM4_CHMODE +# elif CONFIG_STM32_TIM4_CHANNEL == 3 +# define CONFIG_STM32_TIM4_CHANNEL3 1 +# define CONFIG_STM32_TIM4_CH3MODE CONFIG_STM32_TIM4_CHMODE +# elif CONFIG_STM32_TIM4_CHANNEL == 4 +# define CONFIG_STM32_TIM4_CHANNEL4 1 +# define CONFIG_STM32_TIM4_CH4MODE CONFIG_STM32_TIM4_CHMODE +# else +# error "Unsupported value of CONFIG_STM32_TIM4_CHANNEL" +# endif +# define PWM_TIM4_NCHANNELS 1 +#endif + +#ifdef CONFIG_STM32_TIM5_PWM +# if !defined(CONFIG_STM32_TIM5_CHANNEL) +# error "CONFIG_STM32_TIM5_CHANNEL must be provided" +# elif CONFIG_STM32_TIM5_CHANNEL == 1 +# define CONFIG_STM32_TIM5_CHANNEL1 1 +# define CONFIG_STM32_TIM5_CH1MODE CONFIG_STM32_TIM5_CHMODE +# elif CONFIG_STM32_TIM5_CHANNEL == 2 +# define CONFIG_STM32_TIM5_CHANNEL2 1 +# define CONFIG_STM32_TIM5_CH2MODE CONFIG_STM32_TIM5_CHMODE +# elif CONFIG_STM32_TIM5_CHANNEL == 3 +# define CONFIG_STM32_TIM5_CHANNEL3 1 +# define CONFIG_STM32_TIM5_CH3MODE CONFIG_STM32_TIM5_CHMODE +# elif CONFIG_STM32_TIM5_CHANNEL == 4 +# define CONFIG_STM32_TIM5_CHANNEL4 1 +# define CONFIG_STM32_TIM5_CH4MODE CONFIG_STM32_TIM5_CHMODE +# else +# error "Unsupported value of CONFIG_STM32_TIM5_CHANNEL" +# endif +# define PWM_TIM5_NCHANNELS 1 +#endif + +#ifdef CONFIG_STM32_TIM8_PWM +# if !defined(CONFIG_STM32_TIM8_CHANNEL) +# error "CONFIG_STM32_TIM8_CHANNEL must be provided" +# elif CONFIG_STM32_TIM8_CHANNEL == 1 +# define CONFIG_STM32_TIM8_CHANNEL1 1 +# define CONFIG_STM32_TIM8_CH1MODE CONFIG_STM32_TIM8_CHMODE +# elif CONFIG_STM32_TIM8_CHANNEL == 2 +# define CONFIG_STM32_TIM8_CHANNEL2 1 +# define CONFIG_STM32_TIM8_CH2MODE CONFIG_STM32_TIM8_CHMODE +# elif CONFIG_STM32_TIM8_CHANNEL == 3 +# define CONFIG_STM32_TIM8_CHANNEL3 1 +# define CONFIG_STM32_TIM8_CH3MODE CONFIG_STM32_TIM8_CHMODE +# elif CONFIG_STM32_TIM8_CHANNEL == 4 +# define CONFIG_STM32_TIM8_CHANNEL4 1 +# define CONFIG_STM32_TIM8_CH4MODE CONFIG_STM32_TIM8_CHMODE +# else +# error "Unsupported value of CONFIG_STM32_TIM8_CHANNEL" +# endif +# define PWM_TIM8_NCHANNELS 1 +#endif + +#ifdef CONFIG_STM32_TIM9_PWM +# if !defined(CONFIG_STM32_TIM9_CHANNEL) +# error "CONFIG_STM32_TIM9_CHANNEL must be provided" +# elif CONFIG_STM32_TIM9_CHANNEL == 1 +# define CONFIG_STM32_TIM9_CHANNEL1 1 +# define CONFIG_STM32_TIM9_CH1MODE CONFIG_STM32_TIM9_CHMODE +# elif CONFIG_STM32_TIM9_CHANNEL == 2 +# define CONFIG_STM32_TIM9_CHANNEL2 1 +# define CONFIG_STM32_TIM9_CH2MODE CONFIG_STM32_TIM9_CHMODE +# else +# error "Unsupported value of CONFIG_STM32_TIM9_CHANNEL" +# endif +# define PWM_TIM9_NCHANNELS 1 +#endif + +#ifdef CONFIG_STM32_TIM10_PWM +# if !defined(CONFIG_STM32_TIM10_CHANNEL) +# error "CONFIG_STM32_TIM10_CHANNEL must be provided" +# elif CONFIG_STM32_TIM10_CHANNEL == 1 +# define CONFIG_STM32_TIM10_CHANNEL1 1 +# define CONFIG_STM32_TIM10_CH1MODE CONFIG_STM32_TIM10_CHMODE +# else +# error "Unsupported value of CONFIG_STM32_TIM10_CHANNEL" +# endif +# define PWM_TIM10_NCHANNELS 1 +#endif + +#ifdef CONFIG_STM32_TIM11_PWM +# if !defined(CONFIG_STM32_TIM11_CHANNEL) +# error "CONFIG_STM32_TIM11_CHANNEL must be provided" +# elif CONFIG_STM32_TIM11_CHANNEL == 1 +# define CONFIG_STM32_TIM11_CHANNEL1 1 +# define CONFIG_STM32_TIM11_CH1MODE CONFIG_STM32_TIM11_CHMODE +# else +# error "Unsupported value of CONFIG_STM32_TIM11_CHANNEL" +# endif +# define PWM_TIM11_NCHANNELS 1 +#endif + +#ifdef CONFIG_STM32_TIM12_PWM +# if !defined(CONFIG_STM32_TIM12_CHANNEL) +# error "CONFIG_STM32_TIM12_CHANNEL must be provided" +# elif CONFIG_STM32_TIM12_CHANNEL == 1 +# define CONFIG_STM32_TIM12_CHANNEL1 1 +# define CONFIG_STM32_TIM12_CH1MODE CONFIG_STM32_TIM12_CHMODE +# elif CONFIG_STM32_TIM12_CHANNEL == 2 +# define CONFIG_STM32_TIM12_CHANNEL2 1 +# define CONFIG_STM32_TIM12_CH2MODE CONFIG_STM32_TIM12_CHMODE +# else +# error "Unsupported value of CONFIG_STM32_TIM12_CHANNEL" +# endif +# define PWM_TIM12_NCHANNELS 1 +#endif + +#ifdef CONFIG_STM32_TIM13_PWM +# if !defined(CONFIG_STM32_TIM13_CHANNEL) +# error "CONFIG_STM32_TIM13_CHANNEL must be provided" +# elif CONFIG_STM32_TIM13_CHANNEL == 1 +# define CONFIG_STM32_TIM13_CHANNEL1 1 +# define CONFIG_STM32_TIM13_CH1MODE CONFIG_STM32_TIM13_CHMODE +# else +# error "Unsupported value of CONFIG_STM32_TIM13_CHANNEL" +# endif +# define PWM_TIM13_NCHANNELS 1 +#endif + +#ifdef CONFIG_STM32_TIM14_PWM +# if !defined(CONFIG_STM32_TIM14_CHANNEL) +# error "CONFIG_STM32_TIM14_CHANNEL must be provided" +# elif CONFIG_STM32_TIM14_CHANNEL == 1 +# define CONFIG_STM32_TIM14_CHANNEL1 1 +# define CONFIG_STM32_TIM14_CH1MODE CONFIG_STM32_TIM14_CHMODE +# else +# error "Unsupported value of CONFIG_STM32_TIM14_CHANNEL" +# endif +# define PWM_TIM14_NCHANNELS 1 +#endif + +#ifdef CONFIG_STM32_TIM15_PWM +# if !defined(CONFIG_STM32_TIM15_CHANNEL) +# error "CONFIG_STM32_TIM15_CHANNEL must be provided" +# elif CONFIG_STM32_TIM15_CHANNEL == 1 +# define CONFIG_STM32_TIM15_CHANNEL1 1 +# define CONFIG_STM32_TIM15_CH1MODE CONFIG_STM32_TIM15_CHMODE +# elif CONFIG_STM32_TIM15_CHANNEL == 2 +# define CONFIG_STM32_TIM15_CHANNEL2 1 +# define CONFIG_STM32_TIM15_CH2MODE CONFIG_STM32_TIM15_CHMODE +# else +# error "Unsupported value of CONFIG_STM32_TIM15_CHANNEL" +# endif +# define PWM_TIM15_NCHANNELS 1 +#endif + +#ifdef CONFIG_STM32_TIM16_PWM +# if !defined(CONFIG_STM32_TIM16_CHANNEL) +# error "CONFIG_STM32_TIM16_CHANNEL must be provided" +# elif CONFIG_STM32_TIM16_CHANNEL == 1 +# define CONFIG_STM32_TIM16_CHANNEL1 1 +# define CONFIG_STM32_TIM16_CH1MODE CONFIG_STM32_TIM16_CHMODE +# else +# error "Unsupported value of CONFIG_STM32_TIM16_CHANNEL" +# endif +# define PWM_TIM16_NCHANNELS 1 +#endif + +#ifdef CONFIG_STM32_TIM17_PWM +# if !defined(CONFIG_STM32_TIM17_CHANNEL) +# error "CONFIG_STM32_TIM17_CHANNEL must be provided" +# elif CONFIG_STM32_TIM17_CHANNEL == 1 +# define CONFIG_STM32_TIM17_CHANNEL1 1 +# define CONFIG_STM32_TIM17_CH1MODE CONFIG_STM32_TIM17_CHMODE +# else +# error "Unsupported value of CONFIG_STM32_TIM17_CHANNEL" +# endif +# define PWM_TIM17_NCHANNELS 1 +#endif + +#endif /* CONFIG_STM32_PWM_MULTICHAN */ + +#ifdef CONFIG_STM32_TIM1_CH1OUT +# define PWM_TIM1_CH1CFG GPIO_TIM1_CH1OUT +#else +# define PWM_TIM1_CH1CFG 0 +#endif +#ifdef CONFIG_STM32_TIM1_CH1NOUT +# define PWM_TIM1_CH1NCFG GPIO_TIM1_CH1NOUT +#else +# define PWM_TIM1_CH1NCFG 0 +#endif +#ifdef CONFIG_STM32_TIM1_CH2OUT +# define PWM_TIM1_CH2CFG GPIO_TIM1_CH2OUT +#else +# define PWM_TIM1_CH2CFG 0 +#endif +#ifdef CONFIG_STM32_TIM1_CH2NOUT +# define PWM_TIM1_CH2NCFG GPIO_TIM1_CH2NOUT +#else +# define PWM_TIM1_CH2NCFG 0 +#endif +#ifdef CONFIG_STM32_TIM1_CH3OUT +# define PWM_TIM1_CH3CFG GPIO_TIM1_CH3OUT +#else +# define PWM_TIM1_CH3CFG 0 +#endif +#ifdef CONFIG_STM32_TIM1_CH3NOUT +# define PWM_TIM1_CH3NCFG GPIO_TIM1_CH3NOUT +#else +# define PWM_TIM1_CH3NCFG 0 +#endif +#ifdef CONFIG_STM32_TIM1_CH4OUT +# define PWM_TIM1_CH4CFG GPIO_TIM1_CH4OUT +#else +# define PWM_TIM1_CH4CFG 0 +#endif + +#ifdef CONFIG_STM32_TIM2_CH1OUT +# define PWM_TIM2_CH1CFG GPIO_TIM2_CH1OUT +#else +# define PWM_TIM2_CH1CFG 0 +#endif +#ifdef CONFIG_STM32_TIM2_CH2OUT +# define PWM_TIM2_CH2CFG GPIO_TIM2_CH2OUT +#else +# define PWM_TIM2_CH2CFG 0 +#endif +#ifdef CONFIG_STM32_TIM2_CH3OUT +# define PWM_TIM2_CH3CFG GPIO_TIM2_CH3OUT +#else +# define PWM_TIM2_CH3CFG 0 +#endif +#ifdef CONFIG_STM32_TIM2_CH4OUT +# define PWM_TIM2_CH4CFG GPIO_TIM2_CH4OUT +#else +# define PWM_TIM2_CH4CFG 0 +#endif + +#ifdef CONFIG_STM32_TIM3_CH1OUT +# define PWM_TIM3_CH1CFG GPIO_TIM3_CH1OUT +#else +# define PWM_TIM3_CH1CFG 0 +#endif +#ifdef CONFIG_STM32_TIM3_CH2OUT +# define PWM_TIM3_CH2CFG GPIO_TIM3_CH2OUT +#else +# define PWM_TIM3_CH2CFG 0 +#endif +#ifdef CONFIG_STM32_TIM3_CH3OUT +# define PWM_TIM3_CH3CFG GPIO_TIM3_CH3OUT +#else +# define PWM_TIM3_CH3CFG 0 +#endif +#ifdef CONFIG_STM32_TIM3_CH4OUT +# define PWM_TIM3_CH4CFG GPIO_TIM3_CH4OUT +#else +# define PWM_TIM3_CH4CFG 0 +#endif + +#ifdef CONFIG_STM32_TIM4_CH1OUT +# define PWM_TIM4_CH1CFG GPIO_TIM4_CH1OUT +#else +# define PWM_TIM4_CH1CFG 0 +#endif +#ifdef CONFIG_STM32_TIM4_CH2OUT +# define PWM_TIM4_CH2CFG GPIO_TIM4_CH2OUT +#else +# define PWM_TIM4_CH2CFG 0 +#endif +#ifdef CONFIG_STM32_TIM4_CH3OUT +# define PWM_TIM4_CH3CFG GPIO_TIM4_CH3OUT +#else +# define PWM_TIM4_CH3CFG 0 +#endif +#ifdef CONFIG_STM32_TIM4_CH4OUT +# define PWM_TIM4_CH4CFG GPIO_TIM4_CH4OUT +#else +# define PWM_TIM4_CH4CFG 0 +#endif + +#ifdef CONFIG_STM32_TIM5_CH1OUT +# define PWM_TIM5_CH1CFG GPIO_TIM5_CH1OUT +#else +# define PWM_TIM5_CH1CFG 0 +#endif +#ifdef CONFIG_STM32_TIM5_CH2OUT +# define PWM_TIM5_CH2CFG GPIO_TIM5_CH2OUT +#else +# define PWM_TIM5_CH2CFG 0 +#endif +#ifdef CONFIG_STM32_TIM5_CH3OUT +# define PWM_TIM5_CH3CFG GPIO_TIM5_CH3OUT +#else +# define PWM_TIM5_CH3CFG 0 +#endif +#ifdef CONFIG_STM32_TIM5_CH4OUT +# define PWM_TIM5_CH4CFG GPIO_TIM5_CH4OUT +#else +# define PWM_TIM5_CH4CFG 0 +#endif + +#ifdef CONFIG_STM32_TIM8_CH1OUT +# define PWM_TIM8_CH1CFG GPIO_TIM8_CH1OUT +#else +# define PWM_TIM8_CH1CFG 0 +#endif +#ifdef CONFIG_STM32_TIM8_CH1NOUT +# define PWM_TIM8_CH1NCFG GPIO_TIM8_CH1NOUT +#else +# define PWM_TIM8_CH1NCFG 0 +#endif +#ifdef CONFIG_STM32_TIM8_CH2OUT +# define PWM_TIM8_CH2CFG GPIO_TIM8_CH2OUT +#else +# define PWM_TIM8_CH2CFG 0 +#endif +#ifdef CONFIG_STM32_TIM8_CH2NOUT +# define PWM_TIM8_CH2NCFG GPIO_TIM8_CH2NOUT +#else +# define PWM_TIM8_CH2NCFG 0 +#endif +#ifdef CONFIG_STM32_TIM8_CH3OUT +# define PWM_TIM8_CH3CFG GPIO_TIM8_CH3OUT +#else +# define PWM_TIM8_CH3CFG 0 +#endif +#ifdef CONFIG_STM32_TIM8_CH3NOUT +# define PWM_TIM8_CH3NCFG GPIO_TIM8_CH3NOUT +#else +# define PWM_TIM8_CH3NCFG 0 +#endif +#ifdef CONFIG_STM32_TIM8_CH4OUT +# define PWM_TIM8_CH4CFG GPIO_TIM8_CH4OUT +#else +# define PWM_TIM8_CH4CFG 0 +#endif + +#ifdef CONFIG_STM32_TIM9_CH1OUT +# define PWM_TIM9_CH1CFG GPIO_TIM9_CH1OUT +#else +# define PWM_TIM9_CH1CFG 0 +#endif + +#ifdef CONFIG_STM32_TIM9_CH2OUT +# define PWM_TIM9_CH2CFG GPIO_TIM9_CH2OUT +#else +# define PWM_TIM9_CH2CFG 0 +#endif + +#ifdef CONFIG_STM32_TIM10_CH1OUT +# define PWM_TIM10_CH1CFG GPIO_TIM10_CH1OUT +#else +# define PWM_TIM10_CH1CFG 0 +#endif + +#ifdef CONFIG_STM32_TIM11_CH1OUT +# define PWM_TIM11_CH1CFG GPIO_TIM11_CH1OUT +#else +# define PWM_TIM11_CH1CFG 0 +#endif + +#ifdef CONFIG_STM32_TIM12_CH1OUT +# define PWM_TIM12_CH1CFG GPIO_TIM12_CH1OUT +#else +# define PWM_TIM12_CH1CFG 0 +#endif +#ifdef CONFIG_STM32_TIM12_CH2OUT +# define PWM_TIM12_CH2CFG GPIO_TIM12_CH2OUT +#else +# define PWM_TIM12_CH2CFG 0 +#endif + +#ifdef CONFIG_STM32_TIM13_CH1OUT +# define PWM_TIM13_CH1CFG GPIO_TIM13_CH1OUT +#else +# define PWM_TIM13_CH1CFG 0 +#endif + +#ifdef CONFIG_STM32_TIM14_CH1OUT +# define PWM_TIM14_CH1CFG GPIO_TIM14_CH1OUT +#else +# define PWM_TIM14_CH1CFG 0 +#endif + +#ifdef CONFIG_STM32_TIM15_CH1OUT +# define PWM_TIM15_CH1CFG GPIO_TIM15_CH1OUT +#else +# define PWM_TIM15_CH1CFG 0 +#endif + +#ifdef CONFIG_STM32_TIM15_CH1NOUT +# define PWM_TIM15_CH1NCFG GPIO_TIM15_CH1NOUT +#else +# define PWM_TIM15_CH1NCFG 0 +#endif +#ifdef CONFIG_STM32_TIM15_CH2OUT +# define PWM_TIM15_CH2CFG GPIO_TIM15_CH2OUT +#else +# define PWM_TIM15_CH2CFG 0 +#endif + +#ifdef CONFIG_STM32_TIM16_CH1OUT +# define PWM_TIM16_CH1CFG GPIO_TIM16_CH1OUT +#else +# define PWM_TIM16_CH1CFG 0 +#endif +#ifdef CONFIG_STM32_TIM16_CH1NOUT +# define PWM_TIM16_CH1NCFG GPIO_TIM16_CH1NOUT +#else +# define PWM_TIM16_CH1NCFG 0 +#endif + +#ifdef CONFIG_STM32_TIM17_CH1OUT +# define PWM_TIM17_CH1CFG GPIO_TIM17_CH1OUT +#else +# define PWM_TIM17_CH1CFG 0 +#endif +#ifdef CONFIG_STM32_TIM17_CH1NOUT +# define PWM_TIM17_CH1NCFG GPIO_TIM17_CH1NOUT +#else +# define PWM_TIM17_CH1NCFG 0 +#endif + +/* Complementary outputs support */ + +#if defined(CONFIG_STM32_TIM1_CH1NOUT) || defined(CONFIG_STM32_TIM1_CH2NOUT) || \ + defined(CONFIG_STM32_TIM1_CH3NOUT) +# define HAVE_TIM1_COMPLEMENTARY +#endif +#if defined(CONFIG_STM32_TIM8_CH1NOUT) || defined(CONFIG_STM32_TIM8_CH2NOUT) || \ + defined(CONFIG_STM32_TIM8_CH3NOUT) +# define HAVE_TIM8_COMPLEMENTARY +#endif +#if defined(CONFIG_STM32_TIM15_CH1NOUT) +# define HAVE_TIM15_COMPLEMENTARY +#endif +#if defined(CONFIG_STM32_TIM16_CH1NOUT) +# define HAVE_TIM16_COMPLEMENTARY +#endif +#if defined(CONFIG_STM32_TIM17_CH1NOUT) +# define HAVE_TIM17_COMPLEMENTARY +#endif +#if defined(HAVE_TIM1_COMPLEMENTARY) || defined(HAVE_TIM8_COMPLEMENTARY) || \ + defined(HAVE_TIM15_COMPLEMENTARY) || defined(HAVE_TIM16_COMPLEMENTARY) || \ + defined(HAVE_TIM17_COMPLEMENTARY) +# define HAVE_PWM_COMPLEMENTARY +#endif + +/* Low-level ops helpers ****************************************************/ + +#ifdef CONFIG_STM32_PWM_LL_OPS + +/* NOTE: + * low-level ops accept pwm_lowerhalf_s as first argument, but llops access + * can be found in stm32_pwm_dev_s + */ + +#define PWM_SETUP(dev) \ + (dev)->ops->setup((struct pwm_lowerhalf_s *)dev) +#define PWM_SHUTDOWN(dev) \ + (dev)->ops->shutdown((struct pwm_lowerhalf_s *)dev) +#define PWM_CCR_UPDATE(dev, index, ccr) \ + (dev)->llops->ccr_update((struct pwm_lowerhalf_s *)dev, index, ccr) +#define PWM_MODE_UPDATE(dev, index, mode) \ + (dev)->llops->mode_update((struct pwm_lowerhalf_s *)dev, index, mode) +#define PWM_CCR_GET(dev, index) \ + (dev)->llops->ccr_get((struct pwm_lowerhalf_s *)dev, index) +#define PWM_ARR_UPDATE(dev, arr) \ + (dev)->llops->arr_update((struct pwm_lowerhalf_s *)dev, arr) +#define PWM_ARR_GET(dev) \ + (dev)->llops->arr_get((struct pwm_lowerhalf_s *)dev) +#define PWM_RCR_UPDATE(dev, rcr) \ + (dev)->llops->rcr_update((struct pwm_lowerhalf_s *)dev, rcr) +#define PWM_RCR_GET(dev) \ + (dev)->llops->rcr_get((struct pwm_lowerhalf_s *)dev) +#ifdef CONFIG_STM32_PWM_TRGO +# define PWM_TRGO_SET(dev, trgo) \ + (dev)->llops->trgo_set((struct pwm_lowerhalf_s *)dev, trgo) +#endif +#define PWM_OUTPUTS_ENABLE(dev, out, state) \ + (dev)->llops->outputs_enable((struct pwm_lowerhalf_s *)dev, out, state) +#define PWM_SOFT_UPDATE(dev) \ + (dev)->llops->soft_update((struct pwm_lowerhalf_s *)dev) +#define PWM_CONFIGURE(dev) \ + (dev)->llops->configure((struct pwm_lowerhalf_s *)dev) +#define PWM_SOFT_BREAK(dev, state) \ + (dev)->llops->soft_break((struct pwm_lowerhalf_s *)dev, state) +#define PWM_FREQ_UPDATE(dev, freq) \ + (dev)->llops->freq_update((struct pwm_lowerhalf_s *)dev, freq) +#define PWM_TIM_ENABLE(dev, state) \ + (dev)->llops->tim_enable((struct pwm_lowerhalf_s *)dev, state) +#ifdef CONFIG_DEBUG_PWM_INFO +# define PWM_DUMP_REGS(dev, msg) \ + (dev)->llops->dump_regs((struct pwm_lowerhalf_s *)dev, msg) +#else +# define PWM_DUMP_REGS(dev, msg) +#endif +#define PWM_DT_UPDATE(dev, dt) \ + (dev)->llops->dt_update((struct pwm_lowerhalf_s *)dev, dt) +#endif + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/* Timer mode */ + +enum stm32_pwm_tim_mode_e +{ + STM32_TIMMODE_COUNTUP = 0, + STM32_TIMMODE_COUNTDOWN = 1, + STM32_TIMMODE_CENTER1 = 2, + STM32_TIMMODE_CENTER2 = 3, + STM32_TIMMODE_CENTER3 = 4, +}; + +/* Timer output polarity */ + +enum stm32_pwm_pol_e +{ + STM32_POL_POS = 0, + STM32_POL_NEG = 1, +}; + +/* Timer output IDLE state */ + +enum stm32_pwm_idle_e +{ + STM32_IDLE_INACTIVE = 0, + STM32_IDLE_ACTIVE = 1 +}; + +/* PWM channel mode */ + +enum stm32_pwm_chanmode_e +{ + STM32_CHANMODE_FRZN = 0, /* CCRx matches has no effects on outputs */ + STM32_CHANMODE_CHACT = 1, /* OCxREF active on match */ + STM32_CHANMODE_CHINACT = 2, /* OCxREF inactive on match */ + STM32_CHANMODE_OCREFTOG = 3, /* OCxREF toggles when TIMy_CNT=TIMyCCRx */ + STM32_CHANMODE_OCREFLO = 4, /* OCxREF is forced low */ + STM32_CHANMODE_OCREFHI = 5, /* OCxREF is forced high */ + STM32_CHANMODE_PWM1 = 6, /* PWM mode 1 */ + STM32_CHANMODE_PWM2 = 7, /* PWM mode 2 */ +#ifdef HAVE_IP_TIMERS_V2 + STM32_CHANMODE_COMBINED1 = 8, /* Combined PWM mode 1 */ + STM32_CHANMODE_COMBINED2 = 9, /* Combined PWM mode 2 */ + STM32_CHANMODE_ASYMMETRIC1 = 10, /* Asymmetric PWM mode 1 */ + STM32_CHANMODE_ASYMMETRIC2 = 11, /* Asymmetric PWM mode 2 */ +#endif +}; + +/* PWM timer channel */ + +enum stm32_pwm_chan_e +{ + STM32_PWM_CHAN1 = 1, + STM32_PWM_CHAN2 = 2, + STM32_PWM_CHAN3 = 3, + STM32_PWM_CHAN4 = 4, +#ifdef HAVE_IP_TIMERS_V2 + STM32_PWM_CHAN5 = 5, + STM32_PWM_CHAN6 = 6, +#endif +}; + +/* PWM timer channel output */ + +enum stm32_pwm_output_e +{ + STM32_PWM_OUT1 = (1 << 0), + STM32_PWM_OUT1N = (1 << 1), + STM32_PWM_OUT2 = (1 << 2), + STM32_PWM_OUT2N = (1 << 3), + STM32_PWM_OUT3 = (1 << 4), + STM32_PWM_OUT3N = (1 << 5), + STM32_PWM_OUT4 = (1 << 6), + + /* 1 << 7 reserved - no complementary output for CH4 */ + +#ifdef HAVE_IP_TIMERS_V2 + /* Only available inside micro */ + + STM32_PWM_OUT5 = (1 << 8), + + /* 1 << 9 reserved - no complementary output for CH5 */ + + STM32_PWM_OUT6 = (1 << 10), + + /* 1 << 11 reserved - no complementary output for CH6 */ +#endif +}; + +#ifdef CONFIG_STM32_PWM_LL_OPS + +/* This structure provides the publicly visible representation of the + * "lower-half" PWM driver structure. + */ + +struct stm32_pwm_dev_s +{ + /* The first field of this state structure must be a pointer to the PWM + * callback structure to be consistent with upper-half PWM driver. + */ + + const struct pwm_ops_s *ops; + + /* Publicly visible portion of the "lower-half" PWM driver structure */ + + const struct stm32_pwm_ops_s *llops; + + /* Require cast-compatibility with private "lower-half" PWM structure */ +}; + +/* Low-level operations for PWM */ + +struct pwm_lowerhalf_s; +struct stm32_pwm_ops_s +{ + /* Update CCR register */ + + int (*ccr_update)(struct pwm_lowerhalf_s *dev, + uint8_t index, uint32_t ccr); + + /* Update PWM mode */ + + int (*mode_update)(struct pwm_lowerhalf_s *dev, + uint8_t index, uint32_t mode); + + /* Get CCR register */ + + uint32_t (*ccr_get)(struct pwm_lowerhalf_s *dev, uint8_t index); + + /* Update ARR register */ + + int (*arr_update)(struct pwm_lowerhalf_s *dev, uint32_t arr); + + /* Get ARR register */ + + uint32_t (*arr_get)(struct pwm_lowerhalf_s *dev); + + /* Update RCR register */ + + int (*rcr_update)(struct pwm_lowerhalf_s *dev, uint16_t rcr); + + /* Get RCR register */ + + uint16_t (*rcr_get)(struct pwm_lowerhalf_s *dev); + +#ifdef CONFIG_STM32_PWM_TRGO + /* Set TRGO/TRGO2 register */ + + int (*trgo_set)(struct pwm_lowerhalf_s *dev, uint8_t trgo); +#endif + + /* Enable outputs */ + + int (*outputs_enable)(struct pwm_lowerhalf_s *dev, uint16_t outputs, + bool state); + + /* Software update */ + + int (*soft_update)(struct pwm_lowerhalf_s *dev); + + /* PWM configure */ + + int (*configure)(struct pwm_lowerhalf_s *dev); + + /* Software break */ + + int (*soft_break)(struct pwm_lowerhalf_s *dev, bool state); + + /* Update frequency */ + + int (*freq_update)(struct pwm_lowerhalf_s *dev, uint32_t frequency); + + /* Enable timer counter */ + + int (*tim_enable)(struct pwm_lowerhalf_s *dev, bool state); + +#ifdef CONFIG_DEBUG_PWM_INFO + /* Dump timer registers */ + + void (*dump_regs)(struct pwm_lowerhalf_s *dev, const char *msg); +#endif + +#ifdef HAVE_PWM_COMPLEMENTARY + /* Deadtime update */ + + int (*dt_update)(struct pwm_lowerhalf_s *dev, uint8_t dt); +#endif +}; + +#endif /* CONFIG_STM32_PWM_LL_OPS */ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_pwminitialize + * + * Description: + * Initialize one timer for use with the upper_level PWM driver. + * + * Input Parameters: + * timer - A number identifying the timer use. The number of valid timer + * IDs varies with the STM32 MCU and MCU family but is somewhere in + * the range of {1,..,17}. + * + * Returned Value: + * On success, a pointer to the STM32 lower half PWM driver is returned. + * NULL is returned on any failure. + * + ****************************************************************************/ + +struct pwm_lowerhalf_s *stm32_pwminitialize(int timer); + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* CONFIG_STM32_PWM */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_PWM_V1V2V3_H */ diff --git a/arch/arm/src/common/stm32/stm32_pwr.h b/arch/arm/src/common/stm32/stm32_pwr.h new file mode 100644 index 0000000000000..f7d0ec2b90956 --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_pwr.h @@ -0,0 +1,267 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_pwr.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_PWR_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_PWR_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include "chip.h" +#include "hardware/stm32_pwr.h" + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +/* Identify MCU-specific wakeup pin. + * Different STM32 parts support differing numbers of wakeup pins. + */ + +enum stm32_pwr_wupin_e +{ + PWR_WUPIN_1 = 0, /* Wake-up pin 1 (all parts) */ + PWR_WUPIN_2, /* Wake-up pin 2 */ + PWR_WUPIN_3 /* Wake-up pin 3 */ +}; + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Name: stm32_pwr_enablesdadc + * + * Description: + * Enables SDADC power + * + * Input Parameters: + * sdadc - SDADC number 1-3 + * + * Returned Value: + * None + * + ****************************************************************************/ + +#if defined(CONFIG_STM32_STM32F37XX) +void stm32_pwr_enablesdadc(uint8_t sdadc); +#endif + +/**************************************************************************** + * Name: stm32_pwr_initbkp + * + * Description: + * Insures the referenced count access to the backup domain + * (RTC registers, RTC backup data registers and backup SRAM is consistent + * with the HW state without relying on a variable. + * + * NOTE: This function should only be called by SoC Start up code. + * + * Input Parameters: + * writable - set the initial state of the enable and the + * bkp_writable_counter + * + * Returned Value: + * None + * + ****************************************************************************/ + +void stm32_pwr_initbkp(bool writable); + +/**************************************************************************** + * Name: stm32_pwr_enablebkp + * + * Description: + * Enables access to the backup domain + * (RTC registers, RTC backup data registers and backup SRAM). + * + * NOTE: + * Reference counting is used in order to supported nested calls to this + * function. As a consequence, every call to stm32_pwr_enablebkp(true) + * must be followed by a matching call to stm32_pwr_enablebkp(false). + * + * Input Parameters: + * writable - True: enable ability to write to backup domain registers + * + * Returned Value: + * None + * + ****************************************************************************/ + +void stm32_pwr_enablebkp(bool writable); + +/**************************************************************************** + * Name: stm32_pwr_enablewkup + * + * Description: + * Enables the WKUP pin. + * + * Input Parameters: + * wupin - Selects the WKUP pin to enable/disable + * wupon - state to set it to + * + * Returned Value: + * Zero (OK) is returned on success; A negated errno value is returned on + * any failure. The only cause of failure is if the selected MCU does not + * support the requested wakeup pin. + * + ****************************************************************************/ + +int stm32_pwr_enablewkup(enum stm32_pwr_wupin_e wupin, bool wupon); + +/**************************************************************************** + * Name: stm32_pwr_getsbf + * + * Description: + * Return the standby flag. + * + ****************************************************************************/ + +bool stm32_pwr_getsbf(void); + +/**************************************************************************** + * Name: stm32_pwr_getwuf + * + * Description: + * Return the wakeup flag. + * + ****************************************************************************/ + +bool stm32_pwr_getwuf(void); + +/**************************************************************************** + * Name: stm32_pwr_enablebreg + * + * Description: + * Enables the Backup regulator, the Backup regulator (used to maintain + * backup SRAM content in Standby and VBAT modes) is enabled. If BRE is + * reset, the backup regulator is switched off. The backup SRAM can still + * be used but its content will be lost in the Standby and VBAT modes. + * Once set, the application must wait that the Backup Regulator Ready flag + * (BRR) is set to indicate that the data written into the RAM will be + * maintained in the Standby and VBAT modes. + * + * Input Parameters: + * region - state to set it to + * + * Returned Value: + * None + * + ****************************************************************************/ + +#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +void stm32_pwr_enablebreg(bool region); +#else +# define stm32_pwr_enablebreg(region) +#endif + +/**************************************************************************** + * Name: stm32_pwr_setvos + * + * Description: + * Set voltage scaling for EnergyLite devices. + * + * Input Parameters: + * vos - Properly aligned voltage scaling select bits for the PWR_CR + * register. + * + * Returned Value: + * None + * + * Assumptions: + * At present, this function is called only from initialization logic. + * If used for any other purpose that protection to assure that its + * operation is atomic will be required. + * + ****************************************************************************/ + +#if defined(CONFIG_STM32_ENERGYLITE) || defined(CONFIG_STM32_STM32G0) +void stm32_pwr_setvos(uint16_t vos); +#endif + +/**************************************************************************** + * Name: stm32_pwr_setpvd + * + * Description: + * Sets power voltage detector for EnergyLite devices. + * + * Input Parameters: + * pls - PVD level + * + * Returned Value: + * None + * + * Assumptions: + * At present, this function is called only from initialization logic. + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_ENERGYLITE +void stm32_pwr_setpvd(uint16_t pls); + +/**************************************************************************** + * Name: stm32_pwr_enablepvd + * + * Description: + * Enable the Programmable Voltage Detector + * + ****************************************************************************/ + +void stm32_pwr_enablepvd(void); + +/**************************************************************************** + * Name: stm32_pwr_disablepvd + * + * Description: + * Disable the Programmable Voltage Detector + * + ****************************************************************************/ + +void stm32_pwr_disablepvd(void); + +#endif /* CONFIG_STM32_ENERGYLITE */ + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_PWR_H */ diff --git a/arch/arm/src/common/stm32/stm32_pwr_m0_g0.c b/arch/arm/src/common/stm32/stm32_pwr_m0_g0.c new file mode 100644 index 0000000000000..d1627f7fa5f8c --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_pwr_m0_g0.c @@ -0,0 +1,96 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_pwr_m0_g0.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "arm_internal.h" +#include "stm32_pwr.h" + +#if defined(CONFIG_STM32_PWR) + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +static inline uint32_t stm32_pwr_getreg32(uint8_t offset) +{ + return getreg32(STM32_PWR_BASE + (uint32_t)offset); +} + +static inline void stm32_pwr_putreg32(uint8_t offset, uint32_t value) +{ + putreg32(value, STM32_PWR_BASE + (uint32_t)offset); +} + +static inline void stm32_pwr_modifyreg32(uint8_t offset, uint32_t clearbits, + uint32_t setbits) +{ + modifyreg32(STM32_PWR_BASE + (uint32_t)offset, clearbits, setbits); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +void stm32_pwr_setvos(uint16_t vos) +{ + uint16_t regval; + + /* The following sequence is required to program the voltage regulator + * ranges: + * 1. Wait until VOSF flag is cleared in Power Status register 2 (PWR_SR2). + * 2. Configure the voltage scaling range by setting the VOS bits in the + * PWR_CR1 register. + * 3. Wait until VOSF flag is cleared in Power Status register 2 (PWR_SR2). + * + * No checking is performed to ensure the VOS value to be set is within the + * valid range. + */ + + while ((stm32_pwr_getreg32(STM32_PWR_SR2_OFFSET) & PWR_SR2_VOSF) != 0) + { + } + + regval = stm32_pwr_getreg32(STM32_PWR_CR1_OFFSET); + regval &= ~PWR_CR1_VOS_MASK; + regval |= (vos & PWR_CR1_VOS_MASK); + stm32_pwr_putreg32(STM32_PWR_CR1_OFFSET, regval); + + while ((stm32_pwr_getreg32(STM32_PWR_SR2_OFFSET) & PWR_SR2_VOSF) != 0) + { + } +} + +/* TODO Other stm32_pwr_* functions need to be implemented */ + +#endif /* CONFIG_STM32_PWR */ diff --git a/arch/arm/src/common/stm32/stm32_pwr_m0_v1.c b/arch/arm/src/common/stm32/stm32_pwr_m0_v1.c new file mode 100644 index 0000000000000..5ff40ed9e6665 --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_pwr_m0_v1.c @@ -0,0 +1,396 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_pwr_m0_v1.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include + +#include "arm_internal.h" +#include "stm32_pwr.h" + +#if defined(CONFIG_STM32_PWR) + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* Parts only support a single Wake-up pin do not include the numeric suffix + * in the naming. + */ + +#ifndef PWR_CSR_EWUP1 +# define PWR_CSR_EWUP1 PWR_CSR_EWUP +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static uint16_t g_bkp_writable_counter = 0; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +static inline uint32_t stm32_pwr_getreg32(uint8_t offset) +{ + return getreg32(STM32_PWR_BASE + (uint32_t)offset); +} + +static inline void stm32_pwr_putreg32(uint8_t offset, uint32_t value) +{ + putreg32(value, STM32_PWR_BASE + (uint32_t)offset); +} + +static inline void stm32_pwr_modifyreg32(uint8_t offset, uint32_t clearbits, + uint32_t setbits) +{ + modifyreg32(STM32_PWR_BASE + (uint32_t)offset, clearbits, setbits); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_pwr_initbkp + * + * Description: + * Insures the referenced count access to the backup domain (RTC registers, + * RTC backup data registers and backup SRAM is consistent with the HW + * state without relying on a variable. + * + * NOTE: This function should only be called by SoC Start up code. + * + * Input Parameters: + * writable - True: enable ability to write to backup domain registers + * + * Returned Value: + * None + * + ****************************************************************************/ + +void stm32_pwr_initbkp(bool writable) +{ + uint16_t regval; + + /* Make the HW not writable */ + + regval = stm32_pwr_getreg32(STM32_PWR_CR_OFFSET); + regval &= ~PWR_CR_DBP; + stm32_pwr_putreg32(STM32_PWR_CR_OFFSET, regval); + + /* Make the reference count agree */ + + g_bkp_writable_counter = 0; + stm32_pwr_enablebkp(writable); +} + +/**************************************************************************** + * Name: stm32_pwr_enablebkp + * + * Description: + * Enables access to the backup domain (RTC registers, RTC backup data + * registers and backup SRAM). + * + * NOTE: Reference counting is used in order to supported nested calls to + * this function. As a consequence, every call to stm32_pwr_enablebkp + * (true) must be followed by a matching call to stm32_pwr_enablebkp(false). + * + * Input Parameters: + * writable - True: enable ability to write to backup domain registers + * + * Returned Value: + * None + * + ****************************************************************************/ + +void stm32_pwr_enablebkp(bool writable) +{ + irqstate_t flags; + uint16_t regval; + bool waswritable; + bool wait = false; + + flags = enter_critical_section(); + + /* Get the current state of the STM32 PWR control register */ + + regval = stm32_pwr_getreg32(STM32_PWR_CR_OFFSET); + waswritable = ((regval & PWR_CR_DBP) != 0); + + if (writable) + { + DEBUGASSERT(g_bkp_writable_counter < UINT16_MAX); + g_bkp_writable_counter++; + } + else if (g_bkp_writable_counter > 0) + { + g_bkp_writable_counter--; + } + + /* Enable or disable the ability to write */ + + if (waswritable && g_bkp_writable_counter == 0) + { + /* Disable backup domain access */ + + regval &= ~PWR_CR_DBP; + stm32_pwr_putreg32(STM32_PWR_CR_OFFSET, regval); + } + else if (!waswritable && g_bkp_writable_counter > 0) + { + /* Enable backup domain access */ + + regval |= PWR_CR_DBP; + stm32_pwr_putreg32(STM32_PWR_CR_OFFSET, regval); + + wait = true; + } + + leave_critical_section(flags); + + if (wait) + { + /* Enable does not happen right away */ + + up_udelay(4); + } +} + +/**************************************************************************** + * Name: stm32_pwr_enablewkup + * + * Description: + * Enables the WKUP pin. + * + * Input Parameters: + * wupin - Selects the WKUP pin to enable/disable + * wupon - state to set it to + * + * Returned Value: + * Zero (OK) is returned on success; A negated errno value is returned on + * any failure. The only cause of failure is if the selected MCU does not + * support the requested wakeup pin. + * + ****************************************************************************/ + +int stm32_pwr_enablewkup(enum stm32_pwr_wupin_e wupin, bool wupon) +{ + uint16_t pinmask; + + /* Select the PWR_CSR bit associated with the requested wakeup pin */ + + switch (wupin) + { + case PWR_WUPIN_1: /* Wake-up pin 1 (all parts) */ + pinmask = PWR_CSR_EWUP1; + break; + +#ifdef HAVE_PWR_WKUP2 + case PWR_WUPIN_2: /* Wake-up pin 2 */ + pinmask = PWR_CSR_EWUP2; + break; +#endif + +#ifdef HAVE_PWR_WKUP3 + case PWR_WUPIN_3: /* Wake-up pin 3 */ + pinmask = PWR_CSR_EWUP3; + break; +#endif + + default: + return -EINVAL; + } + + /* Set/clear the wakeup pin enable bit in the CSR. This must be done + * within a critical section because the CSR is shared with other functions + * that may be running concurrently on another thread. + */ + + if (wupon) + { + /* Enable the wakeup pin by setting the bit in the CSR. */ + + stm32_pwr_modifyreg32(STM32_PWR_CSR_OFFSET, 0, pinmask); + } + else + { + /* Disable the wakeup pin by clearing the bit in the CSR. */ + + stm32_pwr_modifyreg32(STM32_PWR_CSR_OFFSET, pinmask, 0); + } + + return OK; +} + +/**************************************************************************** + * Name: stm32_pwr_getsbf + * + * Description: + * Return the standby flag. + * + ****************************************************************************/ + +bool stm32_pwr_getsbf(void) +{ + return (stm32_pwr_getreg32(STM32_PWR_CSR_OFFSET) & PWR_CSR_SBF) != 0; +} + +/**************************************************************************** + * Name: stm32_pwr_getwuf + * + * Description: + * Return the wakeup flag. + * + ****************************************************************************/ + +bool stm32_pwr_getwuf(void) +{ + return (stm32_pwr_getreg32(STM32_PWR_CSR_OFFSET) & PWR_CSR_WUF) != 0; +} + +/**************************************************************************** + * Name: stm32_pwr_setvos + * + * Description: + * Set voltage scaling for EnergyLite devices. + * + * Input Parameters: + * vos - Properly aligned voltage scaling select bits for the PWR_CR + * register. + * + * Returned Value: + * None + * + * Assumptions: + * At present, this function is called only from initialization logic. If + * used for any other purpose that protection to assure that its operation + * is atomic will be required. + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_ENERGYLITE +void stm32_pwr_setvos(uint16_t vos) +{ + uint16_t regval; + + /* The following sequence is required to program the voltage regulator + * ranges: + * 1. Check VDD to identify which ranges are allowed... + * 2. Poll VOSF bit of in PWR_CSR. Wait until it is reset to 0. + * 3. Configure the voltage scaling range by setting the VOS bits in the + * PWR_CR register. + * 4. Poll VOSF bit of in PWR_CSR register. Wait until it is reset to 0. + */ + + while ((stm32_pwr_getreg32(STM32_PWR_CSR_OFFSET) & PWR_CSR_VOSF) != 0) + { + } + + regval = stm32_pwr_getreg32(STM32_PWR_CR_OFFSET); + regval &= ~PWR_CR_VOS_MASK; + regval |= (vos & PWR_CR_VOS_MASK); + stm32_pwr_putreg32(STM32_PWR_CR_OFFSET, regval); + + while ((stm32_pwr_getreg32(STM32_PWR_CSR_OFFSET) & PWR_CSR_VOSF) != 0) + { + } +} + +/**************************************************************************** + * Name: stm32_pwr_setpvd + * + * Description: + * Sets power voltage detector + * + * Input Parameters: + * pls - PVD level + * + * Returned Value: + * None + * + * Assumptions: + * At present, this function is called only from initialization logic. If + * used for any other purpose that protection to assure that its operation + * is atomic will be required. + * + ****************************************************************************/ + +void stm32_pwr_setpvd(uint16_t pls) +{ + uint16_t regval; + + /* Set PLS */ + + regval = stm32_pwr_getreg32(STM32_PWR_CR_OFFSET); + regval &= ~PWR_CR_PLS_MASK; + regval |= (pls & PWR_CR_PLS_MASK); + + /* Write value to register */ + + stm32_pwr_putreg32(STM32_PWR_CR_OFFSET, regval); +} + +/**************************************************************************** + * Name: stm32_pwr_enablepvd + * + * Description: + * Enable the Programmable Voltage Detector + * + ****************************************************************************/ + +void stm32_pwr_enablepvd(void) +{ + /* Enable PVD by setting the PVDE bit in PWR_CR register. */ + + stm32_pwr_modifyreg32(STM32_PWR_CR_OFFSET, 0, PWR_CR_PVDE); +} + +/**************************************************************************** + * Name: stm32_pwr_disablepvd + * + * Description: + * Disable the Programmable Voltage Detector + * + ****************************************************************************/ + +void stm32_pwr_disablepvd(void) +{ + /* Disable PVD by clearing the PVDE bit in PWR_CR register. */ + + stm32_pwr_modifyreg32(STM32_PWR_CR_OFFSET, PWR_CR_PVDE, 0); +} + +#endif /* CONFIG_STM32_ENERGYLITE */ + +#endif /* CONFIG_STM32_PWR */ diff --git a/arch/arm/src/common/stm32/stm32_pwr_m3m4_v1.c b/arch/arm/src/common/stm32/stm32_pwr_m3m4_v1.c new file mode 100644 index 0000000000000..0d2bed7a90f57 --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_pwr_m3m4_v1.c @@ -0,0 +1,481 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_pwr_m3m4_v1.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include + +#include "arm_internal.h" +#include "stm32_pwr.h" + +#if defined(CONFIG_STM32_PWR) + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* Wakeup Pin Definitions: See chip/stm32_pwr.h */ + +#undef HAVE_PWR_WKUP2 +#undef HAVE_PWR_WKUP3 + +#if defined(CONFIG_STM32_STM32F30XX) +# define HAVE_PWR_WKUP2 1 +#elif defined(CONFIG_STM32_STM32L15XX) || defined(CONFIG_STM32_STM32F33XX) || \ + defined(CONFIG_STM32_STM32F37XX) +# define HAVE_PWR_WKUP2 1 +# define HAVE_PWR_WKUP3 1 +#endif + +/* Thr parts only support a single Wake-up pin do not include the numeric + * suffix in the naming. + */ + +#ifndef PWR_CSR_EWUP1 +# define PWR_CSR_EWUP1 PWR_CSR_EWUP +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static uint16_t g_bkp_writable_counter = 0; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +static inline uint32_t stm32_pwr_getreg32(uint8_t offset) +{ + return getreg32(STM32_PWR_BASE + (uint32_t)offset); +} + +static inline void stm32_pwr_putreg32(uint8_t offset, uint32_t value) +{ + putreg32(value, STM32_PWR_BASE + (uint32_t)offset); +} + +static inline void stm32_pwr_modifyreg32(uint8_t offset, uint32_t clearbits, + uint32_t setbits) +{ + modifyreg32(STM32_PWR_BASE + (uint32_t)offset, clearbits, setbits); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_pwr_enablesdadc + * + * Description: + * Enables SDADC power + * + * Input Parameters: + * sdadc - SDADC number 1-3 + * + * Returned Value: + * None + * + ****************************************************************************/ + +#if defined(CONFIG_STM32_STM32F37XX) +void stm32_pwr_enablesdadc(uint8_t sdadc) +{ + uint32_t setbits = 0; + + switch (sdadc) + { + case 1: + setbits = PWR_CR_ENSD1; + break; + + case 2: + setbits = PWR_CR_ENSD2; + break; + + case 3: + setbits = PWR_CR_ENSD3; + break; + } + + stm32_pwr_modifyreg32(STM32_PWR_CR_OFFSET, 0, setbits); +} +#endif + +/**************************************************************************** + * Name: stm32_pwr_initbkp + * + * Description: + * Insures the referenced count access to the backup domain (RTC registers, + * RTC backup data registers and backup SRAM is consistent with the HW + * state without relying on a variable. + * + * NOTE: This function should only be called by SoC Start up code. + * + * Input Parameters: + * writable - True: enable ability to write to backup domain registers + * + * Returned Value: + * None + * + ****************************************************************************/ + +void stm32_pwr_initbkp(bool writable) +{ + uint16_t regval; + + /* Make the HW not writable */ + + regval = stm32_pwr_getreg32(STM32_PWR_CR_OFFSET); + regval &= ~PWR_CR_DBP; + stm32_pwr_putreg32(STM32_PWR_CR_OFFSET, regval); + + /* Make the reference count agree */ + + g_bkp_writable_counter = 0; + stm32_pwr_enablebkp(writable); +} + +/**************************************************************************** + * Name: stm32_pwr_enablebkp + * + * Description: + * Enables access to the backup domain (RTC registers, RTC backup data + * registers and backup SRAM). + * + * NOTE: + * Reference counting is used in order to supported nested calls to this + * function. As a consequence, every call to stm32_pwr_enablebkp(true) + * must be followed by a matching call to stm32_pwr_enablebkp(false). + * + * Input Parameters: + * writable - True: enable ability to write to backup domain registers + * + * Returned Value: + * None + * + ****************************************************************************/ + +void stm32_pwr_enablebkp(bool writable) +{ + irqstate_t flags; + uint16_t regval; + bool waswritable; + bool wait = false; + + flags = enter_critical_section(); + + /* Get the current state of the STM32 PWR control register */ + + regval = stm32_pwr_getreg32(STM32_PWR_CR_OFFSET); + waswritable = ((regval & PWR_CR_DBP) != 0); + + if (writable) + { + DEBUGASSERT(g_bkp_writable_counter < UINT16_MAX); + g_bkp_writable_counter++; + } + else if (g_bkp_writable_counter > 0) + { + g_bkp_writable_counter--; + } + + /* Enable or disable the ability to write */ + + if (waswritable && g_bkp_writable_counter == 0) + { + /* Disable backup domain access */ + + regval &= ~PWR_CR_DBP; + stm32_pwr_putreg32(STM32_PWR_CR_OFFSET, regval); + } + else if (!waswritable && g_bkp_writable_counter > 0) + { + /* Enable backup domain access */ + + regval |= PWR_CR_DBP; + stm32_pwr_putreg32(STM32_PWR_CR_OFFSET, regval); + + wait = true; + } + + leave_critical_section(flags); + + if (wait) + { + /* Enable does not happen right away */ + + up_udelay(4); + } +} + +/**************************************************************************** + * Name: stm32_pwr_enablewkup + * + * Description: + * Enables the WKUP pin. + * + * Input Parameters: + * wupin - Selects the WKUP pin to enable/disable + * wupon - state to set it to + * + * Returned Value: + * Zero (OK) is returned on success; A negated errno value is returned on + * any failure. The only cause of failure is if the selected MCU does not + * support the requested wakeup pin. + * + ****************************************************************************/ + +int stm32_pwr_enablewkup(enum stm32_pwr_wupin_e wupin, bool wupon) +{ + uint16_t pinmask; + + /* Select the PWR_CSR bit associated with the requested wakeup pin */ + + switch (wupin) + { + case PWR_WUPIN_1: /* Wake-up pin 1 (all parts) */ + pinmask = PWR_CSR_EWUP1; + break; + +#ifdef HAVE_PWR_WKUP2 + case PWR_WUPIN_2: /* Wake-up pin 2 */ + pinmask = PWR_CSR_EWUP2; + break; +#endif + +#ifdef HAVE_PWR_WKUP3 + case PWR_WUPIN_3: /* Wake-up pin 3 */ + pinmask = PWR_CSR_EWUP3; + break; +#endif + + default: + return -EINVAL; + } + + /* Set/clear the wakeup pin enable bit in the CSR. This must be done + * within a critical section because the CSR is shared with other functions + * that may be running concurrently on another thread. + */ + + if (wupon) + { + /* Enable the wakeup pin by setting the bit in the CSR. */ + + stm32_pwr_modifyreg32(STM32_PWR_CSR_OFFSET, 0, pinmask); + } + else + { + /* Disable the wakeup pin by clearing the bit in the CSR. */ + + stm32_pwr_modifyreg32(STM32_PWR_CSR_OFFSET, pinmask, 0); + } + + return OK; +} + +/**************************************************************************** + * Name: stm32_pwr_getsbf + * + * Description: + * Return the standby flag. + * + ****************************************************************************/ + +bool stm32_pwr_getsbf(void) +{ + return (stm32_pwr_getreg32(STM32_PWR_CSR_OFFSET) & PWR_CSR_SBF) != 0; +} + +/**************************************************************************** + * Name: stm32_pwr_getwuf + * + * Description: + * Return the wakeup flag. + * + ****************************************************************************/ + +bool stm32_pwr_getwuf(void) +{ + return (stm32_pwr_getreg32(STM32_PWR_CSR_OFFSET) & PWR_CSR_WUF) != 0; +} + +/**************************************************************************** + * Name: stm32_pwr_enablebreg + * + * Description: + * Enables the Backup regulator, the Backup regulator (used to maintain + * backup SRAM content in Standby and VBAT modes) is enabled. If BRE is + * reset, the backup regulator is switched off. The backup SRAM can still + * be used but its content will be lost in the Standby and VBAT modes. + * Once set, the application must wait that the Backup Regulator Ready + * flag (BRR) is set to indicate that the data written into the RAM will + * be maintained in the Standby and VBAT modes. + * + * Input Parameters: + * region - state to set it to + * + * Returned Value: + * None + * + ****************************************************************************/ + +#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +void stm32_pwr_enablebreg(bool region) +{ + uint16_t regval; + + regval = stm32_pwr_getreg32(STM32_PWR_CSR_OFFSET); + regval &= ~PWR_CSR_BRE; + regval |= region ? PWR_CSR_BRE : 0; + stm32_pwr_putreg32(STM32_PWR_CSR_OFFSET, regval); + + if (region) + { + while ((stm32_pwr_getreg32(STM32_PWR_CSR_OFFSET) & PWR_CSR_BRR) == 0); + } +} +#endif + +/**************************************************************************** + * Name: stm32_pwr_setvos + * + * Description: + * Set voltage scaling for EnergyLite devices. + * + * Input Parameters: + * vos - Properly aligned voltage scaling select bits for the PWR_CR + * register. + * + * Returned Value: + * None + * + * Assumptions: + * At present, this function is called only from initialization logic. + * If used for any other purpose that protection to assure that its + * operation is atomic will be required. + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_ENERGYLITE +void stm32_pwr_setvos(uint16_t vos) +{ + uint16_t regval; + + /* The following sequence is required to program the voltage regulator + * ranges: + * 1. Check VDD to identify which ranges are allowed... + * 2. Poll VOSF bit of in PWR_CSR. Wait until it is reset to 0. + * 3. Configure the voltage scaling range by setting the VOS bits in the + * PWR_CR register. + * 4. Poll VOSF bit of in PWR_CSR register. Wait until it is reset to 0. + */ + + while ((stm32_pwr_getreg32(STM32_PWR_CSR_OFFSET) & PWR_CSR_VOSF) != 0); + + regval = stm32_pwr_getreg32(STM32_PWR_CR_OFFSET); + regval &= ~PWR_CR_VOS_MASK; + regval |= (vos & PWR_CR_VOS_MASK); + stm32_pwr_putreg32(STM32_PWR_CR_OFFSET, regval); + + while ((stm32_pwr_getreg32(STM32_PWR_CSR_OFFSET) & PWR_CSR_VOSF) != 0); +} + +/**************************************************************************** + * Name: stm32_pwr_setpvd + * + * Description: + * Sets power voltage detector + * + * Input Parameters: + * pls - PVD level + * + * Returned Value: + * None + * + * Assumptions: + * At present, this function is called only from initialization logic. + * If used for any other purpose that protection to assure that its + * operation is atomic will be required. + * + ****************************************************************************/ + +void stm32_pwr_setpvd(uint16_t pls) +{ + uint16_t regval; + + /* Set PLS */ + + regval = stm32_pwr_getreg32(STM32_PWR_CR_OFFSET); + regval &= ~PWR_CR_PLS_MASK; + regval |= (pls & PWR_CR_PLS_MASK); + + /* Write value to register */ + + stm32_pwr_putreg32(STM32_PWR_CR_OFFSET, regval); +} + +/**************************************************************************** + * Name: stm32_pwr_enablepvd + * + * Description: + * Enable the Programmable Voltage Detector + * + ****************************************************************************/ + +void stm32_pwr_enablepvd(void) +{ + /* Enable PVD by setting the PVDE bit in PWR_CR register. */ + + stm32_pwr_modifyreg32(STM32_PWR_CR_OFFSET, 0, PWR_CR_PVDE); +} + +/**************************************************************************** + * Name: stm32_pwr_disablepvd + * + * Description: + * Disable the Programmable Voltage Detector + * + ****************************************************************************/ + +void stm32_pwr_disablepvd(void) +{ + /* Disable PVD by clearing the PVDE bit in PWR_CR register. */ + + stm32_pwr_modifyreg32(STM32_PWR_CR_OFFSET, PWR_CR_PVDE, 0); +} + +#endif /* CONFIG_STM32_ENERGYLITE */ + +#endif /* CONFIG_STM32_PWR */ diff --git a/arch/arm/src/common/stm32/stm32_qencoder.h b/arch/arm/src/common/stm32/stm32_qencoder.h new file mode 100644 index 0000000000000..e82881b3032d1 --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_qencoder.h @@ -0,0 +1,122 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_qencoder.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_COMPAT_STM32_QENCODER_H +#define __ARCH_ARM_SRC_COMMON_COMPAT_STM32_QENCODER_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "chip.h" + +#ifdef CONFIG_SENSORS_QENCODER + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Timer devices may be used for different purposes. One special purpose is + * as a quadrature encoder input device. If CONFIG_STM32_TIMn is defined + * then CONFIG_STM32_TIMn_QE indicates that timer "n" is intended to be used + * as a quadrature encoder. + */ + +#ifndef CONFIG_STM32_TIM1 +# undef CONFIG_STM32_TIM1_QE +#endif +#ifndef CONFIG_STM32_TIM2 +# undef CONFIG_STM32_TIM2_QE +#endif +#ifndef CONFIG_STM32_TIM3 +# undef CONFIG_STM32_TIM3_QE +#endif +#ifndef CONFIG_STM32_TIM4 +# undef CONFIG_STM32_TIM4_QE +#endif +#ifndef CONFIG_STM32_TIM5 +# undef CONFIG_STM32_TIM5_QE +#endif +#ifndef CONFIG_STM32_TIM8 +# undef CONFIG_STM32_TIM8_QE +#endif + +/* Basic and small general-purpose timers do not support encoder mode. */ + +#undef CONFIG_STM32_TIM6_QE +#undef CONFIG_STM32_TIM7_QE +#undef CONFIG_STM32_TIM9_QE +#undef CONFIG_STM32_TIM10_QE +#undef CONFIG_STM32_TIM11_QE +#undef CONFIG_STM32_TIM12_QE +#undef CONFIG_STM32_TIM13_QE +#undef CONFIG_STM32_TIM14_QE +#undef CONFIG_STM32_TIM15_QE +#undef CONFIG_STM32_TIM16_QE +#undef CONFIG_STM32_TIM17_QE + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_qeinitialize + * + * Description: + * Initialize a quadrature encoder interface. This function must be called + * from board-specific logic. + * + * Input Parameters: + * devpath - The full path to the driver to register. E.g., "/dev/qe0" + * tim - The timer number to use. + * + * Returned Value: + * Zero on success; A negated errno value is returned on failure. + * + ****************************************************************************/ + +int stm32_qeinitialize(const char *devpath, int tim); + +#ifdef CONFIG_STM32_QENCODER_INDEX_PIN +/**************************************************************************** + * Name: stm32_qe_index_init + * + * Description: + * Register the encoder index pin to a given Qencoder timer + * + * Input Parameters: + * tim - The qenco timer number + * gpio - gpio pin configuration + * + * Returned Value: + * Zero on success; A negated errno value is returned on failure. + * + ****************************************************************************/ + +int stm32_qe_index_init(int tim, uint32_t gpio); +#endif + +#endif /* CONFIG_SENSORS_QENCODER */ + +#endif /* __ARCH_ARM_SRC_COMMON_COMPAT_STM32_QENCODER_H */ diff --git a/arch/arm/src/common/stm32/stm32_qencoder_m0_v1.c b/arch/arm/src/common/stm32/stm32_qencoder_m0_v1.c new file mode 100644 index 0000000000000..e88ff33418d2b --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_qencoder_m0_v1.c @@ -0,0 +1,1254 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_qencoder_m0_v1.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include +#include +#include + +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32.h" +#include "stm32_gpio.h" +#include "stm32_tim.h" +#include "stm32_qencoder.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Timers *******************************************************************/ + +#ifndef CONFIG_STM32_QENCODER_DISABLE_EXTEND16BTIMERS +# undef HAVE_32BIT_TIMERS +# undef HAVE_16BIT_TIMERS + +/* If TIM2 is enabled and is 32-bit, then we have 32-bit timers */ + +# if defined(CONFIG_STM32_TIM2_QE) && defined(HAVE_TIM2_32BIT) +# define HAVE_32BIT_TIMERS 1 +# endif + +/* If TIM1, TIM2 (16-bit variant), TIM3, or TIM4 are enabled, we have + * 16-bit timers + */ + +# if defined(CONFIG_STM32_TIM1_QE) || defined(CONFIG_STM32_TIM3_QE) || \ + defined(CONFIG_STM32_TIM4_QE) || \ + (defined(CONFIG_STM32_TIM2_QE) && defined(HAVE_TIM2_16BIT)) +# define HAVE_16BIT_TIMERS 1 +# endif + +/* The width in bits of each timer */ + +# define TIM1_BITWIDTH 16 +# ifdef HAVE_TIM2_16BIT +# define TIM2_BITWIDTH 16 +# else +# define TIM2_BITWIDTH 32 +# endif +# define TIM3_BITWIDTH 16 +# define TIM4_BITWIDTH 16 + +/* Do we need to support mixed 16- and 32-bit timers */ + +# undef HAVE_MIXEDWIDTH_TIMERS +# if defined(HAVE_16BIT_TIMERS) && defined(HAVE_32BIT_TIMERS) +# define HAVE_MIXEDWIDTH_TIMERS 1 +# endif +#endif + +/* Input filter *************************************************************/ + +#ifdef CONFIG_STM32_QENCODER_FILTER +# if defined(CONFIG_STM32_QENCODER_SAMPLE_FDTS) +# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_1) +# define STM32_QENCODER_ICF GTIM_CCMR_ICF_NOFILT +# endif +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_CKINT) +# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_2) +# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FCKINT2 +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_4) +# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FCKINT4 +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_8) +# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FCKINT8 +# endif +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_FDTS_2) +# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_6) +# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd26 +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_8) +# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd28 +# endif +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_FDTS_4) +# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_6) +# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd46 +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_8) +# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd48 +# endif +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_FDTS_8) +# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_6) +# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd86 +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_8) +# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd88 +# endif +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_FDTS_16) +# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_5) +# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd165 +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_6) +# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd166 +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_8) +# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd168 +# endif +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_FDTS_32) +# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_5) +# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd325 +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_6) +# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd326 +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_8) +# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd328 +# endif +# endif + +# ifndef STM32_QENCODER_ICF +# warning "Invalid encoder filter combination, filter disabled" +# endif +#endif + +#ifndef STM32_QENCODER_ICF +# define STM32_QENCODER_ICF GTIM_CCMR_ICF_NOFILT +#endif + +#define STM32_GPIO_INPUT_FLOAT (GPIO_INPUT | GPIO_FLOAT) + +/* Debug ********************************************************************/ + +/* Non-standard debug that may be enabled just for testing the quadrature + * encoder + */ + +#ifndef CONFIG_DEBUG_FEATURES +# undef CONFIG_DEBUG_SENSORS +#endif + +#ifdef CONFIG_DEBUG_SENSORS +# ifdef CONFIG_DEBUG_INFO +# define qe_dumpgpio(p,m) stm32_dumpgpio(p,m) +# else +# define qe_dumpgpio(p,m) +# endif +#else +# define qe_dumpgpio(p,m) +#endif + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/* Constant configuration structure that is retained in FLASH */ + +struct stm32_qeconfig_s +{ + uint8_t timid; /* Timer ID {1,2,3,4,5,8} */ + uint8_t irq; /* Timer update IRQ */ +#ifdef HAVE_MIXEDWIDTH_TIMERS + uint8_t width; /* Timer width (16- or 32-bits) */ +#endif + uint32_t ti1cfg; /* TI1 input pin configuration (20-bit encoding) */ + uint32_t ti2cfg; /* TI2 input pin configuration (20-bit encoding) */ + uint32_t base; /* Register base address */ + uint32_t psc; /* Encoder pulses prescaler */ +}; + +/* Overall, RAM-based state structure */ + +struct stm32_lowerhalf_s +{ + /* The first field of this state structure must be a pointer to the lower- + * half callback structure: + */ + + const struct qe_ops_s *ops; + + /* STM32 driver-specific fields: */ + + const struct stm32_qeconfig_s *config; + + bool inuse; /* True: The lower-half driver is in-use */ + +#ifdef CONFIG_STM32_QENCODER_INDEX_PIN + uint32_t index_pin; /* Index pin GPIO */ + bool index_use; /* True: Index pin is configured */ + int32_t index_offset; /* Index pin offset */ +#endif + +#ifndef CONFIG_STM32_QENCODER_DISABLE_EXTEND16BTIMERS + volatile int32_t position; /* The current position offset */ +#endif + spinlock_t lock; /* Spinlock */ +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/* Helper functions */ + +static uint16_t stm32_getreg16(struct stm32_lowerhalf_s *priv, int offset); +static void stm32_putreg16(struct stm32_lowerhalf_s *priv, int offset, + uint16_t value); +static uint32_t stm32_getreg32(struct stm32_lowerhalf_s *priv, int offset); +static void stm32_putreg32(struct stm32_lowerhalf_s *priv, int offset, + uint32_t value); + +#if defined(CONFIG_DEBUG_SENSORS) && defined(CONFIG_DEBUG_INFO) +static void stm32_dumpregs(struct stm32_lowerhalf_s *priv, + const char *msg); +#else +# define stm32_dumpregs(priv, msg) +#endif + +static struct stm32_lowerhalf_s *stm32_tim2lower(int tim); + +/* Interrupt handling */ + +#ifdef CONFIG_STM32_QENCODER_INDEX_PIN +static int stm32_qe_index_irq(int irq, void *context, void *arg); +#endif + +#ifndef CONFIG_STM32_QENCODER_DISABLE_EXTEND16BTIMERS +static int stm32_interrupt(int irq, void *context, void *arg); +#endif + +/* Lower-half Quadrature Encoder Driver Methods */ + +static int stm32_setup(struct qe_lowerhalf_s *lower); +static int stm32_shutdown(struct qe_lowerhalf_s *lower); +static int stm32_position(struct qe_lowerhalf_s *lower, int32_t *pos); +static int stm32_setposmax(struct qe_lowerhalf_s *lower, uint32_t pos); +static int stm32_reset(struct qe_lowerhalf_s *lower); +static int stm32_setindex(struct qe_lowerhalf_s *lower, uint32_t pos); +static int stm32_ioctl(struct qe_lowerhalf_s *lower, int cmd, + unsigned long arg); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* The lower half callback structure */ + +static const struct qe_ops_s g_qecallbacks = +{ + .setup = stm32_setup, + .shutdown = stm32_shutdown, + .position = stm32_position, + .setposmax = stm32_setposmax, + .reset = stm32_reset, + .setindex = stm32_setindex, + .ioctl = stm32_ioctl, +}; + +/* Per-timer state structures */ + +#ifdef CONFIG_STM32_TIM1_QE +static const struct stm32_qeconfig_s g_tim1config = +{ + .timid = 1, + .irq = STM32_IRQ_TIM1_BRK, +#ifdef HAVE_MIXEDWIDTH_TIMERS + .width = TIM1_BITWIDTH, +#endif + .base = STM32_TIM1_BASE, + .psc = CONFIG_STM32_TIM1_QEPSC, + .ti1cfg = GPIO_TIM1_CH1IN, + .ti2cfg = GPIO_TIM1_CH2IN, +}; + +static struct stm32_lowerhalf_s g_tim1lower = +{ + .ops = &g_qecallbacks, + .config = &g_tim1config, + .inuse = false, + .lock = SP_UNLOCKED, +}; + +#endif + +#ifdef CONFIG_STM32_TIM2_QE +static const struct stm32_qeconfig_s g_tim2config = +{ + .timid = 2, + .irq = STM32_IRQ_TIM2, +#ifdef HAVE_MIXEDWIDTH_TIMERS + .width = TIM2_BITWIDTH, +#endif + .base = STM32_TIM2_BASE, + .psc = CONFIG_STM32_TIM2_QEPSC, + .ti1cfg = GPIO_TIM2_CH1IN, + .ti2cfg = GPIO_TIM2_CH2IN, +}; + +static struct stm32_lowerhalf_s g_tim2lower = +{ + .ops = &g_qecallbacks, + .config = &g_tim2config, + .inuse = false, + .lock = SP_UNLOCKED, +}; + +#endif + +#ifdef CONFIG_STM32_TIM3_QE +static const struct stm32_qeconfig_s g_tim3config = +{ + .timid = 3, + .irq = STM32_IRQ_TIM3, +#ifdef HAVE_MIXEDWIDTH_TIMERS + .width = TIM3_BITWIDTH, +#endif + .base = STM32_TIM3_BASE, + .psc = CONFIG_STM32_TIM3_QEPSC, + .ti1cfg = GPIO_TIM3_CH1IN, + .ti2cfg = GPIO_TIM3_CH2IN, +}; + +static struct stm32_lowerhalf_s g_tim3lower = +{ + .ops = &g_qecallbacks, + .config = &g_tim3config, + .inuse = false, + .lock = SP_UNLOCKED, +}; + +#endif + +#ifdef CONFIG_STM32_TIM4_QE +static const struct stm32_qeconfig_s g_tim4config = +{ + .timid = 4, + .irq = STM32_IRQ_TIM4, +#ifdef HAVE_MIXEDWIDTH_TIMERS + .width = TIM4_BITWIDTH, +#endif + .base = STM32_TIM4_BASE, + .psc = CONFIG_STM32_TIM4_QEPSC, + .ti1cfg = GPIO_TIM4_CH1IN, + .ti2cfg = GPIO_TIM4_CH2IN, +}; + +static struct stm32_lowerhalf_s g_tim4lower = +{ + .ops = &g_qecallbacks, + .config = &g_tim4config, + .inuse = false, + .lock = SP_UNLOCKED, +}; + +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_getreg16 + * + * Description: + * Read the value of a 16-bit timer register. + * + * Input Parameters: + * priv - A reference to the lower half status + * offset - The offset to the register to read + * + * Returned Value: + * The current contents of the specified register + * + ****************************************************************************/ + +static uint16_t stm32_getreg16(struct stm32_lowerhalf_s *priv, int offset) +{ + return getreg16(priv->config->base + offset); +} + +/**************************************************************************** + * Name: stm32_putreg16 + * + * Description: + * Write a value to a 16-bit timer register. + * + * Input Parameters: + * priv - A reference to the lower half status + * offset - The offset to the register to read + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void stm32_putreg16(struct stm32_lowerhalf_s *priv, int offset, + uint16_t value) +{ + putreg16(value, priv->config->base + offset); +} + +/**************************************************************************** + * Name: stm32_getreg32 + * + * Description: + * Read the value of a 32-bit timer register. + * This applies only for the STM32 F4 32-bit registers (CNT, ARR, CRR1-4) + * in the 32-bit timers TIM2-5 (but works OK with the 16-bit TIM1,8 + * and F1 registers as well). + * + * Input Parameters: + * priv - A reference to the lower half status + * offset - The offset to the register to read + * + * Returned Value: + * The current contents of the specified register + * + ****************************************************************************/ + +static uint32_t stm32_getreg32(struct stm32_lowerhalf_s *priv, int offset) +{ + return getreg32(priv->config->base + offset); +} + +/**************************************************************************** + * Name: stm32_putreg16 + * + * Description: + * Write a value to a 32-bit timer register. + * This applies only for the STM32 F4 32-bit registers (CNT, ARR, CRR1-4) + * in the 32-bit timers TIM2-5 (but works OK with the 16-bit TIM1,8 + * and F1 registers). + * + * Input Parameters: + * priv - A reference to the lower half status + * offset - The offset to the register to read + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void stm32_putreg32(struct stm32_lowerhalf_s *priv, int offset, + uint32_t value) +{ + putreg32(value, priv->config->base + offset); +} + +/**************************************************************************** + * Name: stm32_dumpregs + * + * Description: + * Dump all timer registers. + * + * Input Parameters: + * priv - A reference to the QENCODER block status + * + * Returned Value: + * None + * + ****************************************************************************/ + +#if defined(CONFIG_DEBUG_SENSORS) && defined(CONFIG_DEBUG_INFO) +static void stm32_dumpregs(struct stm32_lowerhalf_s *priv, + const char *msg) +{ + sninfo("%s:\n", msg); + sninfo(" CR1: %04x CR2: %04x SMCR: %08" PRIx32 " DIER: %04x\n", + stm32_getreg16(priv, STM32_GTIM_CR1_OFFSET), + stm32_getreg16(priv, STM32_GTIM_CR2_OFFSET), + stm32_getreg32(priv, STM32_GTIM_SMCR_OFFSET), + stm32_getreg16(priv, STM32_GTIM_DIER_OFFSET)); + sninfo(" SR: %04x EGR: %04x CCMR1: %08" PRIx32 + " CCMR2: %08" PRIx32 "\n", + stm32_getreg16(priv, STM32_GTIM_SR_OFFSET), + stm32_getreg16(priv, STM32_GTIM_EGR_OFFSET), + stm32_getreg32(priv, STM32_GTIM_CCMR1_OFFSET), + stm32_getreg32(priv, STM32_GTIM_CCMR2_OFFSET)); + sninfo(" CCER: %04x CNT: %08" PRIx32 " PSC: %04x" + " ARR: %08" PRIx32 "\n", + stm32_getreg16(priv, STM32_GTIM_CCER_OFFSET), + stm32_getreg32(priv, STM32_GTIM_CNT_OFFSET), + stm32_getreg16(priv, STM32_GTIM_PSC_OFFSET), + stm32_getreg32(priv, STM32_GTIM_ARR_OFFSET)); + sninfo(" CCR1: %08" PRIx32 " CCR2: %08" PRIx32 "\n", + stm32_getreg32(priv, STM32_GTIM_CCR1_OFFSET), + stm32_getreg32(priv, STM32_GTIM_CCR2_OFFSET)); + sninfo(" CCR3: %08" PRIx32 " CCR4: %08" PRIx32 "\n", + stm32_getreg32(priv, STM32_GTIM_CCR3_OFFSET), + stm32_getreg32(priv, STM32_GTIM_CCR4_OFFSET)); +#if defined(CONFIG_STM32_TIM1_QE) + if (priv->config->timid == 1) + { + sninfo(" RCR: %04x BDTR: %04x DCR: %04x DMAR: %04x\n", + stm32_getreg16(priv, STM32_ATIM_RCR_OFFSET), + stm32_getreg16(priv, STM32_ATIM_BDTR_OFFSET), + stm32_getreg16(priv, STM32_ATIM_DCR_OFFSET), + stm32_getreg16(priv, STM32_ATIM_DMAR_OFFSET)); + } + else +#endif + { + sninfo(" DCR: %04x DMAR: %04x\n", + stm32_getreg16(priv, STM32_GTIM_DCR_OFFSET), + stm32_getreg16(priv, STM32_GTIM_DMAR_OFFSET)); + } +} +#endif + +/**************************************************************************** + * Name: stm32_tim2lower + * + * Description: + * Map a timer number to a device structure + * + ****************************************************************************/ + +static struct stm32_lowerhalf_s *stm32_tim2lower(int tim) +{ + switch (tim) + { +#ifdef CONFIG_STM32_TIM1_QE + case 1: + return &g_tim1lower; +#endif +#ifdef CONFIG_STM32_TIM2_QE + case 2: + return &g_tim2lower; +#endif +#ifdef CONFIG_STM32_TIM3_QE + case 3: + return &g_tim3lower; +#endif +#ifdef CONFIG_STM32_TIM4_QE + case 4: + return &g_tim4lower; +#endif + default: + return NULL; + } +} + +/**************************************************************************** + * Name: stm32_qe_index_irq + * + * Description: + * Common encoder index pin interrupt. + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_QENCODER_INDEX_PIN +static int stm32_qe_index_irq(int irq, void *context, void *arg) +{ + struct stm32_lowerhalf_s *priv; + bool valid = false; + + DEBUGASSERT(arg); + + priv = (struct stm32_lowerhalf_s *)arg; + + valid = stm32_gpioread(priv->index_pin); + + if (valid == true) + { + stm32_putreg32(priv, STM32_GTIM_CNT_OFFSET, priv->index_offset); + } + + return OK; +} +#endif + +/**************************************************************************** + * Name: stm32_interrupt + * + * Description: + * Common timer interrupt handling. NOTE: Only 16-bit timers require timer + * interrupts. + * + ****************************************************************************/ + +#ifndef CONFIG_STM32_QENCODER_DISABLE_EXTEND16BTIMERS +static int stm32_interrupt(int irq, void *context, void *arg) +{ + struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)arg; + uint16_t regval; + + DEBUGASSERT(priv != NULL); + + /* Verify that this is an update interrupt. + * Nothing else is expected. + */ + + regval = stm32_getreg16(priv, STM32_GTIM_SR_OFFSET); + DEBUGASSERT((regval & ATIM_SR_UIF) != 0); + + /* Clear the UIF interrupt bit */ + + stm32_putreg16(priv, STM32_GTIM_SR_OFFSET, regval & ~GTIM_SR_UIF); + + /* Check the direction bit in the CR1 register and add or subtract the + * maximum value, as appropriate. + */ + + regval = stm32_getreg16(priv, STM32_GTIM_CR1_OFFSET); + if ((regval & ATIM_CR1_DIR) != 0) + { + priv->position -= (int32_t)0x0000ffff; + } + else + { + priv->position += (int32_t)0x0000ffff; + } + + return OK; +} +#endif + +/**************************************************************************** + * Name: stm32_setup + * + * Description: + * This method is called when the driver is opened. The lower half driver + * should configure and initialize the device so that it is ready for use. + * The initial position value should be zero. * + * + ****************************************************************************/ + +static int stm32_setup(struct qe_lowerhalf_s *lower) +{ + struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; + uint16_t dier; + uint32_t smcr; + uint32_t ccmr1; + uint16_t ccer; + uint16_t cr1; +#ifndef CONFIG_STM32_QENCODER_DISABLE_EXTEND16BTIMERS + uint16_t regval; + int ret; +#endif + + /* NOTE: + * Clocking should have been enabled in the low-level RCC logic at boot-up + */ + + /* Timer base configuration */ + + cr1 = stm32_getreg16(priv, STM32_GTIM_CR1_OFFSET); + + /* Clear the direction bit (0=count up) and select the Counter Mode + * (0=Edge aligned) + * (Timers 2-5 and 1-8 only) + */ + + cr1 &= ~(GTIM_CR1_DIR | GTIM_CR1_CMS_MASK); + stm32_putreg16(priv, STM32_GTIM_CR1_OFFSET, cr1); + + /* Set the Autoreload value */ + +#if defined(HAVE_MIXEDWIDTH_TIMERS) + if (priv->config->width == 32) + { + stm32_putreg32(priv, STM32_GTIM_ARR_OFFSET, 0xffffffff); + } + else + { + stm32_putreg16(priv, STM32_GTIM_ARR_OFFSET, 0xffff); + } +#elif defined(HAVE_32BIT_TIMERS) + stm32_putreg32(priv, STM32_GTIM_ARR_OFFSET, 0xffffffff); +#else + stm32_putreg16(priv, STM32_GTIM_ARR_OFFSET, 0xffff); +#endif + + /* Set the timer prescaler value. */ + + stm32_putreg16(priv, + STM32_GTIM_PSC_OFFSET, (uint16_t)priv->config->psc); + +#if defined(CONFIG_STM32_TIM1_QE) + if (priv->config->timid == 1) + { + /* Clear the Repetition Counter value */ + + stm32_putreg16(priv, STM32_ATIM_RCR_OFFSET, 0); + } +#endif + + /* Generate an update event to reload the Prescaler + * and the repetition counter (only for TIM1) value immediately + */ + + stm32_putreg16(priv, STM32_GTIM_EGR_OFFSET, GTIM_EGR_UG); + + /* GPIO pin configuration */ + + stm32_configgpio(priv->config->ti1cfg); + stm32_configgpio(priv->config->ti2cfg); + + /* Set the encoder Mode 3 */ + + smcr = stm32_getreg32(priv, STM32_GTIM_SMCR_OFFSET); + smcr &= ~GTIM_SMCR_SMS_MASK; + smcr |= GTIM_SMCR_ENCMD3; + stm32_putreg32(priv, STM32_GTIM_SMCR_OFFSET, smcr); + + /* TI1 Channel Configuration */ + + /* Disable the Channel 1: Reset the CC1E Bit */ + + ccer = stm32_getreg16(priv, STM32_GTIM_CCER_OFFSET); + ccer &= ~GTIM_CCER_CC1E; + stm32_putreg16(priv, STM32_GTIM_CCER_OFFSET, ccer); + + ccmr1 = stm32_getreg32(priv, STM32_GTIM_CCMR1_OFFSET); + ccer = stm32_getreg16(priv, STM32_GTIM_CCER_OFFSET); + + /* Select the Input IC1=TI1 and set the filter fSAMPLING=fDTS/4, N=6 */ + + ccmr1 &= ~(GTIM_CCMR1_CC1S_MASK | GTIM_CCMR1_IC1F_MASK); + ccmr1 |= GTIM_CCMR_CCS_CCIN1 << GTIM_CCMR1_CC1S_SHIFT; + ccmr1 |= STM32_QENCODER_ICF << GTIM_CCMR1_IC1F_SHIFT; + + /* Select the Polarity=rising and set the CC1E Bit */ + + ccer &= ~(GTIM_CCER_CC1P | GTIM_CCER_CC1NP); + ccer |= GTIM_CCER_CC1E; + + /* Write to TIM CCMR1 and CCER registers */ + + stm32_putreg32(priv, STM32_GTIM_CCMR1_OFFSET, ccmr1); + stm32_putreg16(priv, STM32_GTIM_CCER_OFFSET, ccer); + + /* Set the Input Capture Prescaler value: Capture performed each time an + * edge is detected on the capture input. + */ + + ccmr1 = stm32_getreg32(priv, STM32_GTIM_CCMR1_OFFSET); + ccmr1 &= ~GTIM_CCMR1_IC1PSC_MASK; + ccmr1 |= (GTIM_CCMR_ICPSC_NOPSC << GTIM_CCMR1_IC1PSC_SHIFT); + stm32_putreg32(priv, STM32_GTIM_CCMR1_OFFSET, ccmr1); + + /* TI2 Channel Configuration */ + + /* Disable the Channel 2: Reset the CC2E Bit */ + + ccer = stm32_getreg16(priv, STM32_GTIM_CCER_OFFSET); + ccer &= ~GTIM_CCER_CC2E; + stm32_putreg16(priv, STM32_GTIM_CCER_OFFSET, ccer); + + ccmr1 = stm32_getreg32(priv, STM32_GTIM_CCMR1_OFFSET); + ccer = stm32_getreg16(priv, STM32_GTIM_CCER_OFFSET); + + /* Select the Input IC2=TI2 and set the filter fSAMPLING=fDTS/4, N=6 */ + + ccmr1 &= ~(GTIM_CCMR1_CC2S_MASK | GTIM_CCMR1_IC2F_MASK); + ccmr1 |= GTIM_CCMR_CCS_CCIN1 << GTIM_CCMR1_CC2S_SHIFT; + ccmr1 |= STM32_QENCODER_ICF << GTIM_CCMR1_IC2F_SHIFT; + + /* Select the Polarity=rising and set the CC2E Bit */ + + ccer &= ~(GTIM_CCER_CC2P | GTIM_CCER_CC2NP); + ccer |= GTIM_CCER_CC2E; + + /* Write to TIM CCMR1 and CCER registers */ + + stm32_putreg32(priv, STM32_GTIM_CCMR1_OFFSET, ccmr1); + stm32_putreg16(priv, STM32_GTIM_CCER_OFFSET, ccer); + + /* Set the Input Capture Prescaler value: Capture performed each time an + * edge is detected on the capture input. + */ + + ccmr1 = stm32_getreg32(priv, STM32_GTIM_CCMR1_OFFSET); + ccmr1 &= ~GTIM_CCMR1_IC2PSC_MASK; + ccmr1 |= (GTIM_CCMR_ICPSC_NOPSC << GTIM_CCMR1_IC2PSC_SHIFT); + stm32_putreg32(priv, STM32_GTIM_CCMR1_OFFSET, ccmr1); + + /* Disable the update interrupt */ + + dier = stm32_getreg16(priv, STM32_GTIM_DIER_OFFSET); + dier &= ~GTIM_DIER_UIE; + stm32_putreg16(priv, STM32_GTIM_DIER_OFFSET, dier); + + /* There is no need for interrupts with 32-bit timers */ + +#ifndef CONFIG_STM32_QENCODER_DISABLE_EXTEND16BTIMERS +#ifdef HAVE_MIXEDWIDTH_TIMERS + if (priv->config->width != 32) +#endif + { + /* Attach the interrupt handler */ + + ret = irq_attach(priv->config->irq, stm32_interrupt, priv); + if (ret < 0) + { + stm32_shutdown(lower); + return ret; + } + + /* Enable the update/global interrupt at the NVIC */ + + up_enable_irq(priv->config->irq); + } +#endif + + /* Reset the Update Disable Bit */ + + cr1 = stm32_getreg16(priv, STM32_GTIM_CR1_OFFSET); + cr1 &= ~GTIM_CR1_UDIS; + stm32_putreg16(priv, STM32_GTIM_CR1_OFFSET, cr1); + + /* Reset the URS Bit */ + + cr1 &= ~GTIM_CR1_URS; + stm32_putreg16(priv, STM32_GTIM_CR1_OFFSET, cr1); + + /* There is no need for interrupts with 32-bit timers */ + +#ifndef CONFIG_STM32_QENCODER_DISABLE_EXTEND16BTIMERS +#ifdef HAVE_MIXEDWIDTH_TIMERS + if (priv->config->width != 32) +#endif + { + /* Clear any pending update interrupts */ + + regval = stm32_getreg16(priv, STM32_GTIM_SR_OFFSET); + stm32_putreg16(priv, STM32_GTIM_SR_OFFSET, regval & ~GTIM_SR_UIF); + + /* Then enable the update interrupt */ + + dier = stm32_getreg16(priv, STM32_GTIM_DIER_OFFSET); + dier |= GTIM_DIER_UIE; + stm32_putreg16(priv, STM32_GTIM_DIER_OFFSET, dier); + } +#endif + +#ifdef CONFIG_STM32_QENCODER_INDEX_PIN + priv->index_offset = 0; +#endif + + /* Enable the TIM Counter */ + + cr1 = stm32_getreg16(priv, STM32_GTIM_CR1_OFFSET); + cr1 |= GTIM_CR1_CEN; + stm32_putreg16(priv, STM32_GTIM_CR1_OFFSET, cr1); + + stm32_dumpregs(priv, "After setup"); + + return OK; +} + +/**************************************************************************** + * Name: stm32_shutdown + * + * Description: + * This method is called when the driver is closed. The lower half driver + * should stop data collection, free any resources, disable timer hardware, + * and put the system into the lowest possible power usage state * + * + ****************************************************************************/ + +static int stm32_shutdown(struct qe_lowerhalf_s *lower) +{ + struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; + irqstate_t flags; + uint32_t regaddr; + uint32_t regval; + uint32_t resetbit; + uint32_t pincfg; + + /* Disable the update/global interrupt at the NVIC */ + + flags = enter_critical_section(); + up_disable_irq(priv->config->irq); + + /* Detach the interrupt handler */ + + irq_detach(priv->config->irq); + + /* Disable interrupts momentary to stop any ongoing timer processing and + * to prevent any concurrent access to the reset register. + */ + + /* Disable further interrupts and stop the timer */ + + stm32_putreg16(priv, STM32_GTIM_DIER_OFFSET, 0); + stm32_putreg16(priv, STM32_GTIM_SR_OFFSET, 0); + + /* Determine which timer to reset */ + + switch (priv->config->timid) + { +#ifdef CONFIG_STM32_TIM1_QE + case 1: + regaddr = STM32_RCC_APB2RSTR; + resetbit = RCC_APB2RSTR_TIM1RST; + break; +#endif +#ifdef CONFIG_STM32_TIM2_QE + case 2: + regaddr = STM32_RCC_APB1RSTR; + resetbit = RCC_APB1RSTR_TIM2RST; + break; +#endif +#ifdef CONFIG_STM32_TIM3_QE + case 3: + regaddr = STM32_RCC_APB1RSTR; + resetbit = RCC_APB1RSTR_TIM3RST; + break; +#endif +#ifdef CONFIG_STM32_TIM4_QE + case 4: + regaddr = STM32_RCC_APB1RSTR; + resetbit = RCC_APB1RSTR_TIM4RST; + break; +#endif + default: + leave_critical_section(flags); + return -EINVAL; + } + + /* Reset the timer - stopping the output and putting the timer back + * into a state where stm32_start() can be called. + */ + + regval = getreg32(regaddr); + regval |= resetbit; + putreg32(regval, regaddr); + + regval &= ~resetbit; + putreg32(regval, regaddr); + leave_critical_section(flags); + + sninfo("regaddr: %08" PRIx32 " resetbit: %08" PRIx32 "\n", + regaddr, resetbit); + stm32_dumpregs(priv, "After stop"); + + /* Put the TI1 GPIO pin back to its default state */ + + pincfg = priv->config->ti1cfg & (GPIO_PORT_MASK | GPIO_PIN_MASK); + pincfg |= STM32_GPIO_INPUT_FLOAT; + + stm32_configgpio(pincfg); + + /* Put the TI2 GPIO pin back to its default state */ + + pincfg = priv->config->ti2cfg & (GPIO_PORT_MASK | GPIO_PIN_MASK); + pincfg |= STM32_GPIO_INPUT_FLOAT; + + stm32_configgpio(pincfg); + return OK; +} + +/**************************************************************************** + * Name: stm32_position + * + * Description: + * Return the current position measurement. + * + ****************************************************************************/ + +static int stm32_position(struct qe_lowerhalf_s *lower, int32_t *pos) +{ + struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; +#ifndef CONFIG_STM32_QENCODER_DISABLE_EXTEND16BTIMERS + irqstate_t flags; + int32_t position; + int32_t verify; + uint32_t count; + + DEBUGASSERT(lower && priv->inuse); + + /* Loop until we are certain that no interrupt occurred between samples */ + + flags = spin_lock_irqsave(&priv->lock); + do + { + position = priv->position; + count = stm32_getreg32(priv, STM32_GTIM_CNT_OFFSET); + verify = priv->position; + } + while (position != verify); + spin_unlock_irqrestore(&priv->lock, flags); + + /* Return the position measurement */ + + *pos = position + (int32_t)count; +#else + /* Return the counter value */ + + *pos = (int32_t)stm32_getreg32(priv, STM32_GTIM_CNT_OFFSET); +#endif + return OK; +} + +/**************************************************************************** + * Name: stm32_reset + * + * Description: + * Reset the position measurement to zero. + * + ****************************************************************************/ + +static int stm32_reset(struct qe_lowerhalf_s *lower) +{ + struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; +#ifndef CONFIG_STM32_QENCODER_DISABLE_EXTEND16BTIMERS + irqstate_t flags; + + sninfo("Resetting position to zero\n"); + DEBUGASSERT(lower && priv->inuse); + + /* Reset the timer and the counter. + * Interrupts are disabled to make this atomic (if possible) + */ + + flags = spin_lock_irqsave(&priv->lock); + stm32_putreg32(priv, STM32_GTIM_CNT_OFFSET, 0); + priv->position = 0; + spin_unlock_irqrestore(&priv->lock, flags); +#else + sninfo("Resetting position to zero\n"); + DEBUGASSERT(lower && priv->inuse); + + /* Reset the counter to zero */ + + stm32_putreg32(priv, STM32_GTIM_CNT_OFFSET, 0); +#endif + return OK; +} + +/**************************************************************************** + * Name: stm32_setposmax + * + * Description: + * Set the maximum encoder position. + * + ****************************************************************************/ + +static int stm32_setposmax(struct qe_lowerhalf_s *lower, uint32_t pos) +{ + struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; + + DEBUGASSERT(lower && priv->inuse); + +#if defined(HAVE_MIXEDWIDTH_TIMERS) + if (priv->config->width == 32) + { + stm32_putreg32(priv, STM32_GTIM_ARR_OFFSET, pos); + } + else + { + stm32_putreg16(priv, STM32_GTIM_ARR_OFFSET, pos); + } +#elif defined(HAVE_32BIT_TIMERS) + stm32_putreg32(priv, STM32_GTIM_ARR_OFFSET, pos); +#else + stm32_putreg16(priv, STM32_GTIM_ARR_OFFSET, pos); +#endif + + return OK; +} + +/**************************************************************************** + * Name: stm32_setindex + * + * Description: + * Set the index pin position + * + ****************************************************************************/ + +static int stm32_setindex(struct qe_lowerhalf_s *lower, uint32_t pos) +{ +#ifdef CONFIG_STM32_QENCODER_INDEX_PIN + struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; + int ret = OK; + + sninfo("Set QE TIM%d the index pin position %" PRIx32 "\n", + priv->config->timid, pos); + DEBUGASSERT(lower && priv->inuse); + + if (priv->index_use == false) + { + snerr("ERROR: QE TIM%d index not registered\n", + priv->config->timid); + ret = -EPERM; + goto errout; + } + + priv->index_offset = pos; + +errout: + return ret; +#else + return -ENOTTY; +#endif +} + +/**************************************************************************** + * Name: stm32_ioctl + * + * Description: + * Lower-half logic may support platform-specific ioctl commands + * + ****************************************************************************/ + +static int stm32_ioctl(struct qe_lowerhalf_s *lower, int cmd, + unsigned long arg) +{ + /* No ioctl commands supported */ + + /* TODO add an IOCTL to control the encoder pulse count prescaler */ + + return -ENOTTY; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_qeinitialize + * + * Description: + * Initialize a quadrature encoder interface. + * This function must be called from board-specific logic. + * + * Input Parameters: + * devpath - The full path to the driver to register. E.g., "/dev/qe0" + * tim - The timer number to used. 'tim' must be an element of + * {1,2,3,4} + * + * Returned Value: + * Zero on success; A negated errno value is returned on failure. + * + ****************************************************************************/ + +int stm32_qeinitialize(const char *devpath, int tim) +{ + struct stm32_lowerhalf_s *priv; + int ret; + + /* Find the pre-allocated timer state structure corresponding to this + * timer + */ + + priv = stm32_tim2lower(tim); + if (!priv) + { + snerr("ERROR: TIM%d support not configured\n", tim); + return -ENXIO; + } + + /* Make sure that it is available */ + + if (priv->inuse) + { + snerr("ERROR: TIM%d is in-use\n", tim); + return -EBUSY; + } + + /* Register the priv-half driver */ + + ret = qe_register(devpath, (struct qe_lowerhalf_s *)priv); + if (ret < 0) + { + snerr("ERROR: qe_register failed: %d\n", ret); + return ret; + } + + /* Make sure that the timer is in the shutdown state */ + + stm32_shutdown((struct qe_lowerhalf_s *)priv); + + /* The driver is now in-use */ + + priv->inuse = true; + return OK; +} + +#ifdef CONFIG_STM32_QENCODER_INDEX_PIN +/**************************************************************************** + * Name: stm32_qe_index_init + * + * Description: + * Register the encoder index pin to a given Qencoder timer + * + * Input Parameters: + * tim - The qenco timer number + * gpio - gpio pin configuration + * + * Returned Value: + * Zero on success; A negated errno value is returned on failure. + * + ****************************************************************************/ + +int stm32_qe_index_init(int tim, uint32_t gpio) +{ + struct stm32_lowerhalf_s *priv; + int ret = OK; + + priv = stm32_tim2lower(tim); + if (!priv) + { + snerr("ERROR: TIM%d support not configured\n", tim); + return -ENXIO; + } + + if (priv->inuse == false) + { + snerr("ERROR: TIM%d is not in-use\n", tim); + ret = -EINVAL; + } + + priv->index_pin = gpio; + stm32_configgpio(priv->index_pin); + + ret = stm32_gpiosetevent(gpio, true, false, true, + stm32_qe_index_irq, priv); + if (ret < 0) + { + snerr("ERROR: QE TIM%d failed register irq\n", tim); + goto errout; + } + + priv->index_use = true; + +errout: + return ret; +} +#endif diff --git a/arch/arm/src/common/stm32/stm32_qencoder_m3m4_v1v2v3.c b/arch/arm/src/common/stm32/stm32_qencoder_m3m4_v1v2v3.c new file mode 100644 index 0000000000000..f5c4bea0d22a0 --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_qencoder_m3m4_v1v2v3.c @@ -0,0 +1,1484 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_qencoder_m3m4_v1v2v3.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32.h" +#include "stm32_gpio.h" +#include "stm32_tim.h" +#include "stm32_qencoder.h" + +#ifdef CONFIG_SENSORS_QENCODER + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Timers *******************************************************************/ + +#undef HAVE_32BIT_TIMERS +#undef HAVE_16BIT_TIMERS + +/* On the F1 series, all timers are 16-bit. */ + +#if defined(CONFIG_STM32_STM32F10XX) + +# define HAVE_16BIT_TIMERS 1 + + /* The width in bits of each timer */ + +# define TIM1_BITWIDTH 16 +# define TIM2_BITWIDTH 16 +# define TIM3_BITWIDTH 16 +# define TIM4_BITWIDTH 16 +# define TIM5_BITWIDTH 16 +# define TIM8_BITWIDTH 16 + +/* On the F2, F3, F4 and G4 series, TIM2 and TIM5 are 32-bit. + * All of the rest are 16-bit + */ + +#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) || \ + defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32G4XXX) + + /* If TIM2 or TIM5 are enabled, then we have 32-bit timers */ + +# if defined(CONFIG_STM32_TIM2_QE) || defined(CONFIG_STM32_TIM5_QE) +# define HAVE_32BIT_TIMERS 1 +# endif + + /* If TIM1,3,4, or 8 are enabled, then we have 16-bit timers */ + +# if defined(CONFIG_STM32_TIM1_QE) || defined(CONFIG_STM32_TIM3_QE) || \ + defined(CONFIG_STM32_TIM4_QE) || defined(CONFIG_STM32_TIM8_QE) +# define HAVE_16BIT_TIMERS 1 +# endif + + /* The width in bits of each timer */ + +# define TIM1_BITWIDTH 16 +# define TIM2_BITWIDTH 32 +# define TIM3_BITWIDTH 16 +# define TIM4_BITWIDTH 16 +# define TIM5_BITWIDTH 32 +# define TIM8_BITWIDTH 16 +#endif + +/* Do we need to support mixed 16- and 32-bit timers */ + +#undef HAVE_MIXEDWIDTH_TIMERS +#if defined(HAVE_16BIT_TIMERS) && defined(HAVE_32BIT_TIMERS) +# define HAVE_MIXEDWIDTH_TIMERS 1 +#endif + +/* Input filter *************************************************************/ + +#ifdef CONFIG_STM32_QENCODER_FILTER +# if defined(CONFIG_STM32_QENCODER_SAMPLE_FDTS) +# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_1) +# define STM32_QENCODER_ICF GTIM_CCMR_ICF_NOFILT +# endif +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_CKINT) +# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_2) +# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FCKINT2 +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_4) +# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FCKINT4 +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_8) +# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FCKINT8 +# endif +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_FDTS_2) +# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_6) +# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd26 +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_8) +# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd28 +# endif +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_FDTS_4) +# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_6) +# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd46 +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_8) +# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd48 +# endif +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_FDTS_8) +# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_6) +# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd86 +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_8) +# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd88 +# endif +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_FDTS_16) +# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_5) +# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd165 +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_6) +# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd166 +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_8) +# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd168 +# endif +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_FDTS_32) +# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_5) +# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd325 +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_6) +# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd326 +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_8) +# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd328 +# endif +# endif + +# ifndef STM32_QENCODER_ICF +# warning "Invalid encoder filter combination, filter disabled" +# endif +#endif + +#ifndef STM32_QENCODER_ICF +# define STM32_QENCODER_ICF GTIM_CCMR_ICF_NOFILT +#endif + +#if defined(CONFIG_STM32_STM32F10XX) +# define STM32_GPIO_INPUT_FLOAT (GPIO_INPUT | GPIO_CNF_INFLOAT | \ + GPIO_MODE_INPUT) +#elif defined(CONFIG_STM32_STM32F20XX) || \ + defined(CONFIG_STM32_STM32F30XX) || \ + defined(CONFIG_STM32_STM32F4XXX) || \ + defined(CONFIG_STM32_STM32G4XXX) +# define STM32_GPIO_INPUT_FLOAT (GPIO_INPUT | GPIO_FLOAT) +#else +# error "Unrecognized STM32 chip" +#endif + +/* RCC definitions */ + +#if defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F20XX) || \ + defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F4XXX) + +# define TIMRCCEN_TIM1 STM32_RCC_APB2ENR +# define TIMEN_TIM1 RCC_APB2ENR_TIM1EN +# define TIMRCCRST_TIM1 STM32_RCC_APB2RSTR +# define TIMRST_TIM1 RCC_APB2RSTR_TIM1RST + +# define TIMRCCEN_TIM2 STM32_RCC_APB1ENR +# define TIMEN_TIM2 RCC_APB1ENR_TIM2EN +# define TIMRCCRST_TIM2 STM32_RCC_APB1RSTR +# define TIMRST_TIM2 RCC_APB1RSTR_TIM2RST + +# define TIMRCCEN_TIM3 STM32_RCC_APB1ENR +# define TIMEN_TIM3 RCC_APB1ENR_TIM3EN +# define TIMRCCRST_TIM3 STM32_RCC_APB1RSTR +# define TIMRST_TIM3 RCC_APB1RSTR_TIM3RST + +# define TIMRCCEN_TIM4 STM32_RCC_APB1ENR +# define TIMEN_TIM4 RCC_APB1ENR_TIM4EN +# define TIMRCCRST_TIM4 STM32_RCC_APB1RSTR +# define TIMRST_TIM4 RCC_APB1RSTR_TIM4RST + +# define TIMRCCEN_TIM5 STM32_RCC_APB1ENR +# define TIMEN_TIM5 RCC_APB1ENR_TIM5EN +# define TIMRCCRST_TIM5 STM32_RCC_APB1RSTR +# define TIMRST_TIM5 RCC_APB1RSTR_TIM5RST + +# define TIMRCCEN_TIM8 STM32_RCC_APB2ENR +# define TIMEN_TIM8 RCC_APB2ENR_TIM8EN +# define TIMRCCRST_TIM8 STM32_RCC_APB2RSTR +# define TIMRST_TIM8 RCC_APB2RSTR_TIM8RST + +#elif defined(CONFIG_STM32_STM32G4XXX) + +# define TIMRCCEN_TIM1 STM32_RCC_APB2ENR +# define TIMEN_TIM1 RCC_APB2ENR_TIM1EN +# define TIMRCCRST_TIM1 STM32_RCC_APB2RSTR +# define TIMRST_TIM1 RCC_APB2RSTR_TIM1RST + +# define TIMRCCEN_TIM2 STM32_RCC_APB1ENR1 +# define TIMEN_TIM2 RCC_APB1ENR1_TIM2EN +# define TIMRCCRST_TIM2 STM32_RCC_APB1RSTR1 +# define TIMRST_TIM2 RCC_APB1RSTR1_TIM2RST + +# define TIMRCCEN_TIM3 STM32_RCC_APB1ENR1 +# define TIMEN_TIM3 RCC_APB1ENR1_TIM3EN +# define TIMRCCRST_TIM3 STM32_RCC_APB1RSTR1 +# define TIMRST_TIM3 RCC_APB1RSTR1_TIM3RST + +# define TIMRCCEN_TIM4 STM32_RCC_APB1ENR1 +# define TIMEN_TIM4 RCC_APB1ENR1_TIM4EN +# define TIMRCCRST_TIM4 STM32_RCC_APB1RSTR1 +# define TIMRST_TIM4 RCC_APB1RSTR1_TIM4RST + +# define TIMRCCEN_TIM5 STM32_RCC_APB1ENR1 +# define TIMEN_TIM5 RCC_APB1ENR1_TIM5EN +# define TIMRCCRST_TIM5 STM32_RCC_APB1RSTR1 +# define TIMRST_TIM5 RCC_APB1RSTR1_TIM5RST + +# define TIMRCCEN_TIM8 STM32_RCC_APB2ENR +# define TIMEN_TIM8 RCC_APB2ENR_TIM8EN +# define TIMRCCRST_TIM8 STM32_RCC_APB2RSTR +# define TIMRST_TIM8 RCC_APB2RSTR_TIM8RST + +#else +# error "Unrecognized STM32 chip" +#endif + +/* Debug ********************************************************************/ + +/* Non-standard debug that may be enabled just for testing the quadrature + * encoder + */ + +#ifndef CONFIG_DEBUG_FEATURES +# undef CONFIG_DEBUG_SENSORS +#endif + +#ifdef CONFIG_DEBUG_SENSORS +# ifdef CONFIG_DEBUG_INFO +# define qe_dumpgpio(p,m) stm32_dumpgpio(p,m) +# else +# define qe_dumpgpio(p,m) +# endif +#else +# define qe_dumpgpio(p,m) +#endif + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/* Constant configuration structure that is retained in FLASH */ + +struct stm32_qeconfig_s +{ + uint8_t timid; /* Timer ID {1,2,3,4,5,8} */ + uint8_t irq; /* Timer update IRQ */ +#ifdef HAVE_MIXEDWIDTH_TIMERS + uint8_t width; /* Timer width (16- or 32-bits) */ +#endif +#ifdef CONFIG_STM32_STM32F10XX + uint16_t ti1cfg; /* TI1 input pin configuration (16-bit encoding) */ + uint16_t ti2cfg; /* TI2 input pin configuration (16-bit encoding) */ +#else + uint32_t ti1cfg; /* TI1 input pin configuration (20-bit encoding) */ + uint32_t ti2cfg; /* TI2 input pin configuration (20-bit encoding) */ +#endif + uintptr_t regaddr; /* RCC clock enable register address */ + uint32_t enable; /* RCC clock enable bit */ + uint32_t base; /* Register base address */ + uint32_t psc; /* Timer input clock prescaler */ +}; + +/* Overall, RAM-based state structure */ + +struct stm32_lowerhalf_s +{ + /* The first field of this state structure must be a pointer to the lower- + * half callback structure: + */ + + const struct qe_ops_s *ops; /* Lower half callback structure */ + + /* STM32 driver-specific fields: */ + + const struct stm32_qeconfig_s *config; /* static configuration */ + + bool inuse; /* True: The lower-half driver is in-use */ +#ifdef CONFIG_STM32_QENCODER_INDEX_PIN + uint32_t index_pin; /* Index pin GPIO */ + bool index_use; /* True: Index pin is configured */ + int32_t index_offset; /* Index pin offset */ +#endif + +#ifndef CONFIG_STM32_QENCODER_DISABLE_EXTEND16BTIMERS + volatile int32_t position; /* The current position offset */ +#endif + spinlock_t lock; +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/* Helper functions */ + +static uint16_t stm32_getreg16(struct stm32_lowerhalf_s *priv, + int offset); +static void stm32_putreg16(struct stm32_lowerhalf_s *priv, int offset, + uint16_t value); +static uint32_t stm32_getreg32(struct stm32_lowerhalf_s *priv, + int offset); +static void stm32_putreg32(struct stm32_lowerhalf_s *priv, int offset, + uint32_t value); + +#if defined(CONFIG_DEBUG_SENSORS) && defined(CONFIG_DEBUG_INFO) +static void stm32_dumpregs(struct stm32_lowerhalf_s *priv, + const char *msg); +#else +# define stm32_dumpregs(priv,msg) +#endif + +static struct stm32_lowerhalf_s *stm32_tim2lower(int tim); + +/* Interrupt handling */ + +#ifndef CONFIG_STM32_QENCODER_DISABLE_EXTEND16BTIMERS +static int stm32_interrupt(int irq, void *context, void *arg); +#endif + +/* Lower-half Quadrature Encoder Driver Methods */ + +static int stm32_setup(struct qe_lowerhalf_s *lower); +static int stm32_shutdown(struct qe_lowerhalf_s *lower); +static int stm32_position(struct qe_lowerhalf_s *lower, + int32_t *pos); +static int stm32_setposmax(struct qe_lowerhalf_s *lower, uint32_t pos); +static int stm32_reset(struct qe_lowerhalf_s *lower); +static int stm32_setindex(struct qe_lowerhalf_s *lower, uint32_t pos); +static int stm32_ioctl(struct qe_lowerhalf_s *lower, int cmd, + unsigned long arg); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* The lower half callback structure */ + +static const struct qe_ops_s g_qecallbacks = +{ + .setup = stm32_setup, + .shutdown = stm32_shutdown, + .position = stm32_position, + .setposmax = stm32_setposmax, + .reset = stm32_reset, + .setindex = stm32_setindex, + .ioctl = stm32_ioctl, +}; + +/* Per-timer state structures */ + +#ifdef CONFIG_STM32_TIM1_QE +static const struct stm32_qeconfig_s g_tim1config = +{ + .timid = 1, + .irq = STM32_IRQ_TIM1UP, +#ifdef HAVE_MIXEDWIDTH_TIMERS + .width = TIM1_BITWIDTH, +#endif + .regaddr = TIMRCCEN_TIM1, + .enable = TIMEN_TIM1, + .base = STM32_TIM1_BASE, + .psc = CONFIG_STM32_TIM1_QEPSC, + .ti1cfg = GPIO_TIM1_CH1IN, + .ti2cfg = GPIO_TIM1_CH2IN, +}; + +static struct stm32_lowerhalf_s g_tim1lower = +{ + .ops = &g_qecallbacks, + .config = &g_tim1config, + .inuse = false, + .lock = SP_UNLOCKED, +}; + +#endif + +#ifdef CONFIG_STM32_TIM2_QE +static const struct stm32_qeconfig_s g_tim2config = +{ + .timid = 2, + .irq = STM32_IRQ_TIM2, +#ifdef HAVE_MIXEDWIDTH_TIMERS + .width = TIM2_BITWIDTH, +#endif + .regaddr = TIMRCCEN_TIM2, + .enable = TIMEN_TIM2, + .base = STM32_TIM2_BASE, + .psc = CONFIG_STM32_TIM2_QEPSC, + .ti1cfg = GPIO_TIM2_CH1IN, + .ti2cfg = GPIO_TIM2_CH2IN, +}; + +static struct stm32_lowerhalf_s g_tim2lower = +{ + .ops = &g_qecallbacks, + .config = &g_tim2config, + .inuse = false, + .lock = SP_UNLOCKED, +}; + +#endif + +#ifdef CONFIG_STM32_TIM3_QE +static const struct stm32_qeconfig_s g_tim3config = +{ + .timid = 3, + .irq = STM32_IRQ_TIM3, +#ifdef HAVE_MIXEDWIDTH_TIMERS + .width = TIM3_BITWIDTH, +#endif + .regaddr = TIMRCCEN_TIM3, + .enable = TIMEN_TIM3, + .base = STM32_TIM3_BASE, + .psc = CONFIG_STM32_TIM3_QEPSC, + .ti1cfg = GPIO_TIM3_CH1IN, + .ti2cfg = GPIO_TIM3_CH2IN, +}; + +static struct stm32_lowerhalf_s g_tim3lower = +{ + .ops = &g_qecallbacks, + .config = &g_tim3config, + .inuse = false, + .lock = SP_UNLOCKED, +}; + +#endif + +#ifdef CONFIG_STM32_TIM4_QE +static const struct stm32_qeconfig_s g_tim4config = +{ + .timid = 4, + .irq = STM32_IRQ_TIM4, +#ifdef HAVE_MIXEDWIDTH_TIMERS + .width = TIM4_BITWIDTH, +#endif + .regaddr = TIMRCCEN_TIM4, + .enable = TIMEN_TIM4, + .base = STM32_TIM4_BASE, + .psc = CONFIG_STM32_TIM4_QEPSC, + .ti1cfg = GPIO_TIM4_CH1IN, + .ti2cfg = GPIO_TIM4_CH2IN, +}; + +static struct stm32_lowerhalf_s g_tim4lower = +{ + .ops = &g_qecallbacks, + .config = &g_tim4config, + .inuse = false, + .lock = SP_UNLOCKED, +}; + +#endif + +#ifdef CONFIG_STM32_TIM5_QE +static const struct stm32_qeconfig_s g_tim5config = +{ + .timid = 5, + .irq = STM32_IRQ_TIM5, +#ifdef HAVE_MIXEDWIDTH_TIMERS + .width = TIM5_BITWIDTH, +#endif + .regaddr = TIMRCCEN_TIM5, + .enable = TIMEN_TIM5, + .base = STM32_TIM5_BASE, + .psc = CONFIG_STM32_TIM5_QEPSC, + .ti1cfg = GPIO_TIM5_CH1IN, + .ti2cfg = GPIO_TIM5_CH2IN, +}; + +static struct stm32_lowerhalf_s g_tim5lower = +{ + .ops = &g_qecallbacks, + .config = &g_tim5config, + .inuse = false, + .lock = SP_UNLOCKED, +}; + +#endif + +#ifdef CONFIG_STM32_TIM8_QE +static const struct stm32_qeconfig_s g_tim8config = +{ + .timid = 8, + .irq = STM32_IRQ_TIM8UP, +#ifdef HAVE_MIXEDWIDTH_TIMERS + .width = TIM8_BITWIDTH, +#endif + .regaddr = TIMRCCEN_TIM8, + .enable = TIMEN_TIM8, + .base = STM32_TIM8_BASE, + .psc = CONFIG_STM32_TIM8_QEPSC, + .ti1cfg = GPIO_TIM8_CH1IN, + .ti2cfg = GPIO_TIM8_CH2IN, +}; + +static struct stm32_lowerhalf_s g_tim8lower = +{ + .ops = &g_qecallbacks, + .config = &g_tim8config, + .inuse = false, + .lock = SP_UNLOCKED, +}; + +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_getreg16 + * + * Description: + * Read the value of a 16-bit timer register. + * + * Input Parameters: + * priv - A reference to the lower half status + * offset - The offset to the register to read + * + * Returned Value: + * The current contents of the specified register + * + ****************************************************************************/ + +static uint16_t stm32_getreg16(struct stm32_lowerhalf_s *priv, int offset) +{ + return getreg16(priv->config->base + offset); +} + +/**************************************************************************** + * Name: stm32_putreg16 + * + * Description: + * Write a value to a 16-bit timer register. + * + * Input Parameters: + * priv - A reference to the lower half status + * offset - The offset to the register to read + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void stm32_putreg16(struct stm32_lowerhalf_s *priv, int offset, + uint16_t value) +{ + putreg16(value, priv->config->base + offset); +} + +/**************************************************************************** + * Name: stm32_getreg32 + * + * Description: + * Read the value of a 32-bit timer register. This applies only for the + * STM32 F4 32-bit registers (CNT, ARR, CRR1-4) in the 32-bit timers TIM2-5 + * (but works OK with the 16-bit TIM1,8 and F1 registers as well). + * + * Input Parameters: + * priv - A reference to the lower half status + * offset - The offset to the register to read + * + * Returned Value: + * The current contents of the specified register + * + ****************************************************************************/ + +static uint32_t stm32_getreg32(struct stm32_lowerhalf_s *priv, + int offset) +{ + return getreg32(priv->config->base + offset); +} + +/**************************************************************************** + * Name: stm32_putreg32 + * + * Description: + * Write a value to a 32-bit timer register. This applies only for the + * STM32 F4 32-bit registers (CNT, ARR, CRR1-4) in the 32-bit timers TIM2-5 + * (but works OK with the 16-bit TIM1,8 and F1 registers). + * + * Input Parameters: + * priv - A reference to the lower half status + * offset - The offset to the register to read + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void stm32_putreg32(struct stm32_lowerhalf_s *priv, int offset, + uint32_t value) +{ + putreg32(value, priv->config->base + offset); +} + +/**************************************************************************** + * Name: stm32_dumpregs + * + * Description: + * Dump all timer registers. + * + * Input Parameters: + * priv - A reference to the QENCODER block status + * + * Returned Value: + * None + * + ****************************************************************************/ + +#if defined(CONFIG_DEBUG_SENSORS) && defined(CONFIG_DEBUG_INFO) +static void stm32_dumpregs(struct stm32_lowerhalf_s *priv, + const char *msg) +{ + sninfo("%s:\n", msg); + sninfo(" CR1: %04x CR2: %04x SMCR: %04x DIER: %04x\n", + stm32_getreg16(priv, STM32_GTIM_CR1_OFFSET), + stm32_getreg16(priv, STM32_GTIM_CR2_OFFSET), + stm32_getreg16(priv, STM32_GTIM_SMCR_OFFSET), + stm32_getreg16(priv, STM32_GTIM_DIER_OFFSET)); + sninfo(" SR: %04x EGR: %04x CCMR1: %04x CCMR2: %04x\n", + stm32_getreg16(priv, STM32_GTIM_SR_OFFSET), + stm32_getreg16(priv, STM32_GTIM_EGR_OFFSET), + stm32_getreg16(priv, STM32_GTIM_CCMR1_OFFSET), + stm32_getreg16(priv, STM32_GTIM_CCMR2_OFFSET)); + sninfo(" CCER: %04x CNT: %04x PSC: %04x ARR: %04x\n", + stm32_getreg16(priv, STM32_GTIM_CCER_OFFSET), + stm32_getreg16(priv, STM32_GTIM_CNT_OFFSET), + stm32_getreg16(priv, STM32_GTIM_PSC_OFFSET), + stm32_getreg16(priv, STM32_GTIM_ARR_OFFSET)); + sninfo(" CCR1: %04x CCR2: %04x CCR3: %04x CCR4: %04x\n", + stm32_getreg16(priv, STM32_GTIM_CCR1_OFFSET), + stm32_getreg16(priv, STM32_GTIM_CCR2_OFFSET), + stm32_getreg16(priv, STM32_GTIM_CCR3_OFFSET), + stm32_getreg16(priv, STM32_GTIM_CCR4_OFFSET)); +#if defined(CONFIG_STM32_TIM1_QE) || defined(CONFIG_STM32_TIM8_QE) + if (priv->config->timid == 1 || priv->config->timid == 8) + { + sninfo(" RCR: %04x BDTR: %04x DCR: %04x DMAR: %04x\n", + stm32_getreg16(priv, STM32_ATIM_RCR_OFFSET), + stm32_getreg16(priv, STM32_ATIM_BDTR_OFFSET), + stm32_getreg16(priv, STM32_ATIM_DCR_OFFSET), + stm32_getreg16(priv, STM32_ATIM_DMAR_OFFSET)); + } + else +#endif + { + sninfo(" DCR: %04x DMAR: %04x\n", + stm32_getreg16(priv, STM32_GTIM_DCR_OFFSET), + stm32_getreg16(priv, STM32_GTIM_DMAR_OFFSET)); + } +} +#endif + +/**************************************************************************** + * Name: stm32_tim2lower + * + * Description: + * Map a timer number to a device structure + * + ****************************************************************************/ + +static struct stm32_lowerhalf_s *stm32_tim2lower(int tim) +{ + switch (tim) + { +#ifdef CONFIG_STM32_TIM1_QE + case 1: + return &g_tim1lower; +#endif +#ifdef CONFIG_STM32_TIM2_QE + case 2: + return &g_tim2lower; +#endif +#ifdef CONFIG_STM32_TIM3_QE + case 3: + return &g_tim3lower; +#endif +#ifdef CONFIG_STM32_TIM4_QE + case 4: + return &g_tim4lower; +#endif +#ifdef CONFIG_STM32_TIM5_QE + case 5: + return &g_tim5lower; +#endif +#ifdef CONFIG_STM32_TIM8_QE + case 8: + return &g_tim8lower; +#endif + default: + return NULL; + } +} + +/**************************************************************************** + * Name: stm32_interrupt + * + * Description: + * Common timer interrupt handling. NOTE: Only 16-bit timers require timer + * interrupts. + * + ****************************************************************************/ + +#ifndef CONFIG_STM32_QENCODER_DISABLE_EXTEND16BTIMERS +static int stm32_interrupt(int irq, void *context, void *arg) +{ + struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)arg; + uint16_t regval; + + DEBUGASSERT(priv != NULL); + + /* Verify that this is an update interrupt. Nothing else is expected. */ + + regval = stm32_getreg16(priv, STM32_GTIM_SR_OFFSET); + DEBUGASSERT((regval & ATIM_SR_UIF) != 0); + + /* Clear the UIF interrupt bit */ + + stm32_putreg16(priv, STM32_GTIM_SR_OFFSET, regval & ~GTIM_SR_UIF); + + /* Check the direction bit in the CR1 register and add or subtract the + * maximum value + 1, as appropriate. + */ + + regval = stm32_getreg16(priv, STM32_GTIM_CR1_OFFSET); + if ((regval & ATIM_CR1_DIR) != 0) + { + priv->position -= (int32_t)0x00010000; + } + else + { + priv->position += (int32_t)0x00010000; + } + + return OK; +} +#endif + +#ifdef CONFIG_STM32_QENCODER_INDEX_PIN +/**************************************************************************** + * Name: stm32_qe_index_irq + * + * Description: + * Common encoder index pin interrupt. + * + ****************************************************************************/ + +static int stm32_qe_index_irq(int irq, void *context, void *arg) +{ + struct stm32_lowerhalf_s *priv; + bool valid = false; + + DEBUGASSERT(arg); + + /* Get QE data */ + + priv = (struct stm32_lowerhalf_s *)arg; + + /* Get pin state */ + + valid = stm32_gpioread(priv->index_pin); + + /* Only if pin still high to avoid noises */ + + if (valid == true) + { + /* Force position to index offset */ + + stm32_putreg32(priv, STM32_GTIM_CNT_OFFSET, priv->index_offset); + } + + return OK; +} +#endif + +/**************************************************************************** + * Name: stm32_setup + * + * Description: + * This method is called when the driver is opened. The lower half driver + * should configure and initialize the device so that it is ready for use. + * The initial position value should be zero. * + * + ****************************************************************************/ + +static int stm32_setup(struct qe_lowerhalf_s *lower) +{ + struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; + uint16_t dier; + uint32_t smcr; + uint32_t ccmr1; + uint16_t ccer; + uint16_t cr1; +#ifndef CONFIG_STM32_QENCODER_DISABLE_EXTEND16BTIMERS + uint16_t regval; + int ret; +#endif + + /* Enable clocking to the timer */ + + modifyreg32(priv->config->regaddr, 0, priv->config->enable); + + /* Timer base configuration */ + + cr1 = stm32_getreg16(priv, STM32_GTIM_CR1_OFFSET); + + /* Clear the direction bit (0=count up) and select the Counter Mode + * (0=Edge aligned) (Timers 2-5 and 1-8 only) + */ + + cr1 &= ~(GTIM_CR1_DIR | GTIM_CR1_CMS_MASK); + stm32_putreg16(priv, STM32_GTIM_CR1_OFFSET, cr1); + + /* Set the Autoreload value */ + +#if defined(HAVE_MIXEDWIDTH_TIMERS) + if (priv->config->width == 32) + { + stm32_putreg32(priv, STM32_GTIM_ARR_OFFSET, 0xffffffff); + } + else + { + stm32_putreg16(priv, STM32_GTIM_ARR_OFFSET, 0xffff); + } +#elif defined(HAVE_32BIT_TIMERS) + stm32_putreg32(priv, STM32_GTIM_ARR_OFFSET, 0xffffffff); +#else + stm32_putreg16(priv, STM32_GTIM_ARR_OFFSET, 0xffff); +#endif + + /* Set the timer prescaler value. + * + * If we are doing precise shaft positioning, each qe pulse is important. + * So the STM32 has direct config control on the pulse count prescaler. + * This input clock just limits the incoming pulse rate, which should be + * lower than the peripheral clock due to resynchronization, but it is the + * responsibility of the system designer to decide the correct prescaler + * value, because it has a direct influence on the encoder resolution. + */ + + stm32_putreg16(priv, STM32_GTIM_PSC_OFFSET, (uint16_t)priv->config->psc); + +#if defined(CONFIG_STM32_TIM1_QE) || defined(CONFIG_STM32_TIM8_QE) + if (priv->config->timid == 1 || priv->config->timid == 8) + { + /* Clear the Repetition Counter value */ + + stm32_putreg16(priv, STM32_ATIM_RCR_OFFSET, 0); + } +#endif + + /* Generate an update event to reload the Prescaler + * and the repetition counter (only for TIM1 and TIM8) value immediately + */ + + stm32_putreg16(priv, STM32_GTIM_EGR_OFFSET, GTIM_EGR_UG); + + /* GPIO pin configuration */ + + stm32_configgpio(priv->config->ti1cfg); + stm32_configgpio(priv->config->ti2cfg); + + /* Set the encoder Mode 3 */ + + smcr = stm32_getreg32(priv, STM32_GTIM_SMCR_OFFSET); + smcr &= ~GTIM_SMCR_SMS_MASK; + smcr |= GTIM_SMCR_ENCMD3; + stm32_putreg32(priv, STM32_GTIM_SMCR_OFFSET, smcr); + + /* TI1 Channel Configuration */ + + /* Disable the Channel 1: Reset the CC1E Bit */ + + ccer = stm32_getreg16(priv, STM32_GTIM_CCER_OFFSET); + ccer &= ~GTIM_CCER_CC1E; + stm32_putreg16(priv, STM32_GTIM_CCER_OFFSET, ccer); + + ccmr1 = stm32_getreg32(priv, STM32_GTIM_CCMR1_OFFSET); + ccer = stm32_getreg16(priv, STM32_GTIM_CCER_OFFSET); + + /* Select the Input IC1=TI1 and set the filter fSAMPLING=fDTS/4, N=6 */ + + ccmr1 &= ~(GTIM_CCMR1_CC1S_MASK | GTIM_CCMR1_IC1F_MASK); + ccmr1 |= GTIM_CCMR_CCS_CCIN1 << GTIM_CCMR1_CC1S_SHIFT; + ccmr1 |= STM32_QENCODER_ICF << GTIM_CCMR1_IC1F_SHIFT; + + /* Select the Polarity=rising and set the CC1E Bit */ + +#ifdef HAVE_GTIM_CCXNP + ccer &= ~(GTIM_CCER_CC1P | GTIM_CCER_CC1NP); +#else + ccer &= ~(GTIM_CCER_CC1P); +#endif + ccer |= GTIM_CCER_CC1E; + + /* Write to TIM CCMR1 and CCER registers */ + + stm32_putreg32(priv, STM32_GTIM_CCMR1_OFFSET, ccmr1); + stm32_putreg16(priv, STM32_GTIM_CCER_OFFSET, ccer); + + /* Set the Input Capture Prescaler value: Capture performed each time an + * edge is detected on the capture input. + */ + + ccmr1 = stm32_getreg32(priv, STM32_GTIM_CCMR1_OFFSET); + ccmr1 &= ~GTIM_CCMR1_IC1PSC_MASK; + ccmr1 |= (GTIM_CCMR_ICPSC_NOPSC << GTIM_CCMR1_IC1PSC_SHIFT); + stm32_putreg32(priv, STM32_GTIM_CCMR1_OFFSET, ccmr1); + + /* TI2 Channel Configuration */ + + /* Disable the Channel 2: Reset the CC2E Bit */ + + ccer = stm32_getreg16(priv, STM32_GTIM_CCER_OFFSET); + ccer &= ~GTIM_CCER_CC2E; + stm32_putreg16(priv, STM32_GTIM_CCER_OFFSET, ccer); + + ccmr1 = stm32_getreg32(priv, STM32_GTIM_CCMR1_OFFSET); + ccer = stm32_getreg16(priv, STM32_GTIM_CCER_OFFSET); + + /* Select the Input IC2=TI2 and set the filter fSAMPLING=fDTS/4, N=6 */ + + ccmr1 &= ~(GTIM_CCMR1_CC2S_MASK | GTIM_CCMR1_IC2F_MASK); + ccmr1 |= GTIM_CCMR_CCS_CCIN1 << GTIM_CCMR1_CC2S_SHIFT; + ccmr1 |= STM32_QENCODER_ICF << GTIM_CCMR1_IC2F_SHIFT; + + /* Select the Polarity=rising and set the CC2E Bit */ + +#ifdef HAVE_GTIM_CCXNP + ccer &= ~(GTIM_CCER_CC2P | GTIM_CCER_CC2NP); +#else + ccer &= ~(GTIM_CCER_CC2P); +#endif + ccer |= GTIM_CCER_CC2E; + + /* Write to TIM CCMR1 and CCER registers */ + + stm32_putreg32(priv, STM32_GTIM_CCMR1_OFFSET, ccmr1); + stm32_putreg16(priv, STM32_GTIM_CCER_OFFSET, ccer); + + /* Set the Input Capture Prescaler value: Capture performed each time an + * edge is detected on the capture input. + */ + + ccmr1 = stm32_getreg32(priv, STM32_GTIM_CCMR1_OFFSET); + ccmr1 &= ~GTIM_CCMR1_IC2PSC_MASK; + ccmr1 |= (GTIM_CCMR_ICPSC_NOPSC << GTIM_CCMR1_IC2PSC_SHIFT); + stm32_putreg32(priv, STM32_GTIM_CCMR1_OFFSET, ccmr1); + + /* Disable the update interrupt */ + + dier = stm32_getreg16(priv, STM32_GTIM_DIER_OFFSET); + dier &= ~GTIM_DIER_UIE; + stm32_putreg16(priv, STM32_GTIM_DIER_OFFSET, dier); + + /* There is no need for interrupts with 32-bit timers */ + +#ifndef CONFIG_STM32_QENCODER_DISABLE_EXTEND16BTIMERS +#ifdef HAVE_MIXEDWIDTH_TIMERS + if (priv->config->width != 32) +#endif + { + /* Attach the interrupt handler */ + + ret = irq_attach(priv->config->irq, stm32_interrupt, priv); + if (ret < 0) + { + stm32_shutdown(lower); + return ret; + } + + /* Enable the update/global interrupt at the NVIC */ + + up_enable_irq(priv->config->irq); + } +#endif + + /* Reset the Update Disable Bit */ + + cr1 = stm32_getreg16(priv, STM32_GTIM_CR1_OFFSET); + cr1 &= ~GTIM_CR1_UDIS; + stm32_putreg16(priv, STM32_GTIM_CR1_OFFSET, cr1); + + /* Reset the URS Bit */ + + cr1 &= ~GTIM_CR1_URS; + stm32_putreg16(priv, STM32_GTIM_CR1_OFFSET, cr1); + + /* There is no need for interrupts with 32-bit timers */ + +#ifndef CONFIG_STM32_QENCODER_DISABLE_EXTEND16BTIMERS +#ifdef HAVE_MIXEDWIDTH_TIMERS + if (priv->config->width != 32) +#endif + { + /* Clear any pending update interrupts */ + + regval = stm32_getreg16(priv, STM32_GTIM_SR_OFFSET); + stm32_putreg16(priv, STM32_GTIM_SR_OFFSET, regval & ~GTIM_SR_UIF); + + /* Then enable the update interrupt */ + + dier = stm32_getreg16(priv, STM32_GTIM_DIER_OFFSET); + dier |= GTIM_DIER_UIE; + stm32_putreg16(priv, STM32_GTIM_DIER_OFFSET, dier); + } +#endif + +#ifdef CONFIG_STM32_QENCODER_INDEX_PIN + /* At default index pin offset is 0 */ + + priv->index_offset = 0; +#endif + + /* Enable the TIM Counter */ + + cr1 = stm32_getreg16(priv, STM32_GTIM_CR1_OFFSET); + cr1 |= GTIM_CR1_CEN; + stm32_putreg16(priv, STM32_GTIM_CR1_OFFSET, cr1); + + stm32_dumpregs(priv, "After setup"); + + return OK; +} + +/**************************************************************************** + * Name: stm32_shutdown + * + * Description: + * This method is called when the driver is closed. The lower half driver + * should stop data collection, free any resources, disable timer hardware, + * and put the system into the lowest possible power usage state + * + ****************************************************************************/ + +static int stm32_shutdown(struct qe_lowerhalf_s *lower) +{ + struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; + irqstate_t flags; + uint32_t regaddr; + uint32_t regval; + uint32_t resetbit; + uint32_t pincfg; + + /* Disable the update/global interrupt at the NVIC */ + + flags = enter_critical_section(); + up_disable_irq(priv->config->irq); + + /* Detach the interrupt handler */ + + irq_detach(priv->config->irq); + + /* Disable interrupts momentary to stop any ongoing timer processing and + * to prevent any concurrent access to the reset register. + */ + + /* Disable further interrupts and stop the timer */ + + stm32_putreg16(priv, STM32_GTIM_DIER_OFFSET, 0); + stm32_putreg16(priv, STM32_GTIM_SR_OFFSET, 0); + + /* Determine which timer to reset */ + + switch (priv->config->timid) + { +#ifdef CONFIG_STM32_TIM1_QE + case 1: + regaddr = TIMRCCRST_TIM1; + resetbit = TIMRST_TIM1; + break; +#endif +#ifdef CONFIG_STM32_TIM2_QE + case 2: + regaddr = TIMRCCRST_TIM2; + resetbit = TIMRST_TIM2; + break; +#endif +#ifdef CONFIG_STM32_TIM3_QE + case 3: + regaddr = TIMRCCRST_TIM3; + resetbit = TIMRST_TIM3; + break; +#endif +#ifdef CONFIG_STM32_TIM4_QE + case 4: + regaddr = TIMRCCRST_TIM4; + resetbit = TIMRST_TIM4; + break; +#endif +#ifdef CONFIG_STM32_TIM5_QE + case 5: + regaddr = TIMRCCRST_TIM5; + resetbit = TIMRST_TIM5; + break; +#endif +#ifdef CONFIG_STM32_TIM8_QE + case 8: + regaddr = TIMRCCRST_TIM8; + resetbit = TIMRST_TIM8; + break; +#endif + default: + leave_critical_section(flags); + return -EINVAL; + } + + /* Reset the timer - stopping the output and putting the timer back + * into a state where stm32_start() can be called. + */ + + regval = getreg32(regaddr); + regval |= resetbit; + putreg32(regval, regaddr); + + regval &= ~resetbit; + putreg32(regval, regaddr); + leave_critical_section(flags); + + sninfo("regaddr: %08" PRIx32 " resetbit: %08" PRIx32 "\n", + regaddr, resetbit); + + stm32_dumpregs(priv, "After stop"); + + /* Disable clocking to the timer */ + + modifyreg32(priv->config->regaddr, priv->config->enable, 0); + + /* Put the TI1 GPIO pin back to its default state */ + + pincfg = priv->config->ti1cfg & (GPIO_PORT_MASK | GPIO_PIN_MASK); + pincfg |= STM32_GPIO_INPUT_FLOAT; + + stm32_configgpio(pincfg); + + /* Put the TI2 GPIO pin back to its default state */ + + pincfg = priv->config->ti2cfg & (GPIO_PORT_MASK | GPIO_PIN_MASK); + pincfg |= STM32_GPIO_INPUT_FLOAT; + + stm32_configgpio(pincfg); + return OK; +} + +/**************************************************************************** + * Name: stm32_position + * + * Description: + * Return the current position measurement. + * + ****************************************************************************/ + +static int stm32_position(struct qe_lowerhalf_s *lower, int32_t *pos) +{ + struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; +#ifndef CONFIG_STM32_QENCODER_DISABLE_EXTEND16BTIMERS + irqstate_t flags; + int32_t position; + int32_t verify; + uint32_t count; + + DEBUGASSERT(lower && priv->inuse); + + /* Loop until we are certain that no interrupt occurred between samples */ + + flags = spin_lock_irqsave(&priv->lock); + do + { + position = priv->position; + count = stm32_getreg32(priv, STM32_GTIM_CNT_OFFSET); + verify = priv->position; + } + while (position != verify); + spin_unlock_irqrestore(&priv->lock, flags); + + /* Return the position measurement */ + + *pos = position + (int32_t)count; +#else + /* Return the counter value */ + +# if defined(HAVE_32BIT_TIMERS) + *pos = (int32_t)stm32_getreg32(priv, STM32_GTIM_CNT_OFFSET); +# else + *pos = (int32_t)stm32_getreg16(priv, STM32_GTIM_CNT_OFFSET); +# endif +#endif + return OK; +} + +/**************************************************************************** + * Name: stm32_setposmax + * + * Description: + * Set the maximum encoder position. + * + ****************************************************************************/ + +static int stm32_setposmax(struct qe_lowerhalf_s *lower, uint32_t pos) +{ +#ifdef CONFIG_STM32_QENCODER_DISABLE_EXTEND16BTIMERS + struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; + +#if defined(HAVE_MIXEDWIDTH_TIMERS) + if (priv->config->width == 32) + { + stm32_putreg32(priv, STM32_GTIM_ARR_OFFSET, pos); + } + else + { + stm32_putreg16(priv, STM32_GTIM_ARR_OFFSET, pos); + } +#elif defined(HAVE_32BIT_TIMERS) + stm32_putreg32(priv, STM32_GTIM_ARR_OFFSET, pos); +#else + stm32_putreg16(priv, STM32_GTIM_ARR_OFFSET, pos); +#endif + + return OK; +#else + return -ENOTTY; +#endif +} + +/**************************************************************************** + * Name: stm32_reset + * + * Description: + * Reset the position measurement to zero. + * + ****************************************************************************/ + +static int stm32_reset(struct qe_lowerhalf_s *lower) +{ + struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; +#ifndef CONFIG_STM32_QENCODER_DISABLE_EXTEND16BTIMERS + irqstate_t flags; + + sninfo("Resetting position to zero\n"); + DEBUGASSERT(lower && priv->inuse); + + /* Reset the timer and the counter. Interrupts are disabled to make this + * atomic (if possible) + */ + + flags = enter_critical_section(); + stm32_putreg32(priv, STM32_GTIM_CNT_OFFSET, 0); + priv->position = 0; + leave_critical_section(flags); +#else + sninfo("Resetting position to zero\n"); + DEBUGASSERT(lower && priv->inuse); + + /* Reset the counter to zero */ + + stm32_putreg32(priv, STM32_GTIM_CNT_OFFSET, 0); +#endif + return OK; +} + +/**************************************************************************** + * Name: stm32_setindex + * + * Description: + * Set the index pin position + * + ****************************************************************************/ + +static int stm32_setindex(struct qe_lowerhalf_s *lower, uint32_t pos) +{ +#ifdef CONFIG_STM32_QENCODER_INDEX_PIN + struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; + int ret = OK; + + sninfo("Set QE TIM%d the index pin position %" PRIx32 "\n", + priv->config->timid, pos); + DEBUGASSERT(lower && priv->inuse); + + /* Only if index pin configured */ + + if (priv->index_use == false) + { + snerr("ERROR: QE TIM%d index not registered\n", + priv->config->timid); + ret = -EPERM; + goto errout; + } + + priv->index_offset = pos; + +errout: + return ret; +#else + return -ENOTTY; +#endif +} + +/**************************************************************************** + * Name: stm32_ioctl + * + * Description: + * Lower-half logic may support platform-specific ioctl commands + * + ****************************************************************************/ + +static int stm32_ioctl(struct qe_lowerhalf_s *lower, int cmd, + unsigned long arg) +{ + /* No ioctl commands supported */ + + /* TODO add an IOCTL to control the encoder pulse count prescaler */ + + return -ENOTTY; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_qeinitialize + * + * Description: + * Initialize a quadrature encoder interface. This function must be + * called from board-specific logic. + * + * Input Parameters: + * devpath - The full path to the driver to register. E.g., "/dev/qe0" + * tim - The timer number to used. 'tim' must be an element of + * {1,2,3,4,5,8} + * + * Returned Value: + * Zero on success; A negated errno value is returned on failure. + * + ****************************************************************************/ + +int stm32_qeinitialize(const char *devpath, int tim) +{ + struct stm32_lowerhalf_s *priv; + int ret; + + /* Find the pre-allocated timer state structure corresponding to this + * timer + */ + + priv = stm32_tim2lower(tim); + if (!priv) + { + snerr("ERROR: TIM%d support not configured\n", tim); + return -ENXIO; + } + + /* Make sure that it is available */ + + if (priv->inuse) + { + snerr("ERROR: TIM%d is in-use\n", tim); + return -EBUSY; + } + + /* Register the upper-half driver */ + + ret = qe_register(devpath, (struct qe_lowerhalf_s *)priv); + if (ret < 0) + { + snerr("ERROR: qe_register failed: %d\n", ret); + return ret; + } + + /* Make sure that the timer is in the shutdown state */ + + stm32_shutdown((struct qe_lowerhalf_s *)priv); + + /* The driver is now in-use */ + + priv->inuse = true; + return OK; +} + +#ifdef CONFIG_STM32_QENCODER_INDEX_PIN +/**************************************************************************** + * Name: stm32_qe_index_init + * + * Description: + * Register the encoder index pin to a given Qencoder timer + * + * Input Parameters: + * tim - The qenco timer number + * gpio - gpio pin configuration + * + * Returned Value: + * Zero on success; A negated errno value is returned on failure. + * + ****************************************************************************/ + +int stm32_qe_index_init(int tim, uint32_t gpio) +{ + struct stm32_lowerhalf_s *priv; + int ret = OK; + + /* Find the pre-allocated timer state structure corresponding to this + * timer + */ + + priv = stm32_tim2lower(tim); + if (!priv) + { + snerr("ERROR: TIM%d support not configured\n", tim); + return -ENXIO; + } + + /* Make sure that it is available */ + + if (priv->inuse == false) + { + snerr("ERROR: TIM%d is not in-use\n", tim); + ret = -EINVAL; + } + + /* Configure QE index pin */ + + priv->index_pin = gpio; + stm32_configgpio(priv->index_pin); + + /* Register interrupt */ + + ret = stm32_gpiosetevent(gpio, true, false, true, + stm32_qe_index_irq, priv); + if (ret < 0) + { + snerr("ERROR: QE TIM%d failed register irq\n", tim); + goto errout; + } + + /* Set flag */ + + priv->index_use = true; + +errout: + return ret; +} +#endif + +#endif /* CONFIG_SENSORS_QENCODER */ diff --git a/arch/arm/src/common/stm32/stm32_rcc.h b/arch/arm/src/common/stm32/stm32_rcc.h new file mode 100644 index 0000000000000..c2c57a6a0b6b4 --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_rcc.h @@ -0,0 +1,227 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_rcc.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_RCC_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_RCC_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "arm_internal.h" +#include "chip.h" + +#include "hardware/stm32_rcc.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Inline Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_mco1config + * + * Description: + * Selects the clock source to output on MCO1 pin (PA8). PA8 should be + * configured in alternate function mode. + * + ****************************************************************************/ + +#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +static inline void stm32_mco1config(uint32_t source, uint32_t div) +{ + uint32_t regval; + + regval = getreg32(STM32_RCC_CFGR); + regval &= ~(RCC_CFGR_MCO1_MASK | RCC_CFGR_MCO1PRE_MASK); + regval |= (source | div); + putreg32(regval, STM32_RCC_CFGR); +} +#endif + +/**************************************************************************** + * Name: stm32_mcoconfig + * + * Description: + * Selects the clock source to output on MC pin (PA8) for stm32f10xxx. + * PA8 should be configured in alternate function mode. + * + ****************************************************************************/ + +#if defined(CONFIG_STM32_CONNECTIVITYLINE) +static inline void stm32_mcoconfig(uint32_t source) +{ + uint32_t regval; + + regval = getreg32(STM32_RCC_CFGR); + regval &= ~(RCC_CFGR_MCO_MASK); + regval |= (source & RCC_CFGR_MCO_MASK); + putreg32(regval, STM32_RCC_CFGR); +} +#endif + +/**************************************************************************** + * Name: stm32_mcodivconfig + * + * Description: + * Selects the clock source to output and clock divider on MC pin (PA4) for + * stm32l1xxx. PA4 should be configured in alternate function mode. + * + ****************************************************************************/ + +#if defined(CONFIG_STM32_STM32L15XX) +static inline void stm32_mcodivconfig(uint32_t source, uint32_t divider) +{ + uint32_t regval; + + regval = getreg32(STM32_RCC_CFGR); + regval &= ~(RCC_CFGR_MCOSEL_MASK); + regval |= (source & RCC_CFGR_MCOSEL_MASK); + regval &= ~(RCC_CFGR_MCOPRE_MASK); + regval |= (divider & RCC_CFGR_MCOPRE_MASK); + putreg32(regval, STM32_RCC_CFGR); +} +#endif + +/**************************************************************************** + * Name: stm32_mco2config + * + * Description: + * Selects the clock source to output on MCO2 pin (PC9). PC9 should be + * configured in alternate function mode. + * + ****************************************************************************/ + +#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +static inline void stm32_mco2config(uint32_t source, uint32_t div) +{ + uint32_t regval; + + regval = getreg32(STM32_RCC_CFGR); + regval &= ~(RCC_CFGR_MCO2_MASK | RCC_CFGR_MCO2PRE_MASK); + regval |= (source | div); + putreg32(regval, STM32_RCC_CFGR); +} +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_clockconfig + * + * Description: + * Called to initialize the STM32F0XX. + * This does whatever setup is needed to put the MCU in a usable state. + * This includes the initialization of clocking using the settings + * in board.h. + * + ****************************************************************************/ + +void stm32_clockconfig(void); + +/**************************************************************************** + * Name: stm32_board_clockconfig + * + * Description: + * Any STM32 board may replace the standard board clock configuration logic + * with its own custom clock configuration logic. + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG +void stm32_board_clockconfig(void); +#endif + +/**************************************************************************** + * Name: stm32_clockenable + * + * Description: + * Re-enable the clock and restore the clock settings after low-power + * modes. + * + ****************************************************************************/ + +#ifdef CONFIG_PM +void stm32_clockenable(void); +#endif + +/**************************************************************************** + * Name: stm32_rcc_enablelse + * + * Description: + * Enable the External Low-Speed (LSE) Oscillator. + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void stm32_rcc_enablelse(void); + +/**************************************************************************** + * Name: stm32_rcc_enablelsi + * + * Description: + * Enable the Internal Low-Speed (LSI) RC Oscillator. + * + ****************************************************************************/ + +void stm32_rcc_enablelsi(void); + +/**************************************************************************** + * Name: stm32_rcc_disablelsi + * + * Description: + * Disable the Internal Low-Speed (LSI) RC Oscillator. + * + ****************************************************************************/ + +void stm32_rcc_disablelsi(void); + +#undef EXTERN +#if defined(__cplusplus) +} +#endif +#endif /* __ASSEMBLY__ */ + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_RCC_H */ diff --git a/arch/arm/src/common/stm32/stm32_rng_m0_v1.c b/arch/arm/src/common/stm32/stm32_rng_m0_v1.c new file mode 100644 index 0000000000000..837ed6ce85ee4 --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_rng_m0_v1.c @@ -0,0 +1,314 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_rng_m0_v1.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#include "hardware/stm32_rng.h" +#include "arm_internal.h" + +#if defined(CONFIG_STM32_RNG) +#if defined(CONFIG_DEV_RANDOM) || defined(CONFIG_DEV_URANDOM_ARCH) + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +static int stm32_rng_initialize(void); +static int stm32_rng_interrupt(int irq, void *context, void *arg); +static void stm32_rng_enable(void); +static void stm32_rng_disable(void); +static ssize_t stm32_rng_read(struct file *filep, char *buffer, size_t); + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +struct rng_dev_s +{ + mutex_t rd_devlock; /* Threads can only exclusively access the RNG */ + sem_t rd_readsem; /* To block until the buffer is filled */ + char *rd_buf; + size_t rd_buflen; + uint32_t rd_lastval; + bool rd_first; +}; + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static struct rng_dev_s g_rngdev = +{ + .rd_devlock = NXMUTEX_INITIALIZER, + .rd_readsem = SEM_INITIALIZER(0), +}; + +static const struct file_operations g_rngops = +{ + NULL, /* open */ + NULL, /* close */ + stm32_rng_read, /* read */ +}; + +/**************************************************************************** + * Private functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_rng_initialize + ****************************************************************************/ + +static int stm32_rng_initialize(void) +{ + uint32_t regval; + + _info("Initializing RNG\n"); + + if (irq_attach(STM32_IRQ_RNG, stm32_rng_interrupt, NULL)) + { + /* We could not attach the ISR to the interrupt */ + + _info("Could not attach IRQ.\n"); + + return -EAGAIN; + } + + /* Enable interrupts */ + + regval = getreg32(STM32_RNG_CR); + regval |= RNG_CR_IE; + putreg32(regval, STM32_RNG_CR); + + up_enable_irq(STM32_IRQ_RNG); + + return OK; +} + +/**************************************************************************** + * Name: stm32_rng_enable + ****************************************************************************/ + +static void stm32_rng_enable(void) +{ + uint32_t regval; + + g_rngdev.rd_first = true; + + regval = getreg32(STM32_RNG_CR); + regval |= RNG_CR_RNGEN; + putreg32(regval, STM32_RNG_CR); +} + +/**************************************************************************** + * Name: stm32_rng_disable + ****************************************************************************/ + +static void stm32_rng_disable(void) +{ + uint32_t regval; + regval = getreg32(STM32_RNG_CR); + regval &= ~RNG_CR_RNGEN; + putreg32(regval, STM32_RNG_CR); +} + +/**************************************************************************** + * Name: stm32_rng_interrupt + ****************************************************************************/ + +static int stm32_rng_interrupt(int irq, void *context, void *arg) +{ + uint32_t rngsr; + uint32_t data; + + rngsr = getreg32(STM32_RNG_SR); + + if ((rngsr & (RNG_SR_SEIS | RNG_SR_CEIS)) /* Check for error bits */ + || !(rngsr & RNG_SR_DRDY)) /* Data ready must be set */ + { + /* This random value is not valid, we will try again. */ + + return OK; + } + + data = getreg32(STM32_RNG_DR); + + /* As required by the FIPS PUB (Federal Information Processing Standard + * Publication) 140-2, the first random number generated after setting the + * RNGEN bit should not be used, but saved for comparison with the next + * generated random number. Each subsequent generated random number has to + * be compared with the previously generated number. The test fails if any + * two compared numbers are equal (continuous random number generator + * test). + */ + + if (g_rngdev.rd_first) + { + g_rngdev.rd_first = false; + g_rngdev.rd_lastval = data; + return OK; + } + + if (g_rngdev.rd_lastval == data) + { + /* Two subsequent same numbers, we will try again. */ + + return OK; + } + + /* If we get here, the random number is valid. */ + + g_rngdev.rd_lastval = data; + + if (g_rngdev.rd_buflen >= 4) + { + g_rngdev.rd_buflen -= 4; + *(uint32_t *)&g_rngdev.rd_buf[g_rngdev.rd_buflen] = data; + } + else + { + while (g_rngdev.rd_buflen > 0) + { + g_rngdev.rd_buf[--g_rngdev.rd_buflen] = (char)data; + data >>= 8; + } + } + + if (g_rngdev.rd_buflen == 0) + { + /* Buffer filled, stop further interrupts. */ + + stm32_rng_disable(); + nxsem_post(&g_rngdev.rd_readsem); + } + + return OK; +} + +/**************************************************************************** + * Name: stm32_rng_read + ****************************************************************************/ + +static ssize_t stm32_rng_read(struct file *filep, char *buffer, + size_t buflen) +{ + int ret; + + ret = nxmutex_lock(&g_rngdev.rd_devlock); + if (ret < 0) + { + return ret; + } + + /* We've got the mutex. */ + + /* Reset the operation semaphore with 0 for blocking until the + * buffer is filled from interrupts. + */ + + nxsem_reset(&g_rngdev.rd_readsem, 0); + + g_rngdev.rd_buflen = buflen; + g_rngdev.rd_buf = buffer; + + /* Enable RNG with interrupts */ + + stm32_rng_enable(); + + /* Wait until the buffer is filled */ + + ret = nxsem_wait(&g_rngdev.rd_readsem); + + /* Free RNG for next use */ + + nxmutex_unlock(&g_rngdev.rd_devlock); + return ret < 0 ? ret : buflen; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: devrandom_register + * + * Description: + * Initialize the RNG hardware and register the /dev/random driver. + * Must be called BEFORE devurandom_register. + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_DEV_RANDOM +void devrandom_register(void) +{ + stm32_rng_initialize(); + register_driver("/dev/random", &g_rngops, 0444, NULL); +} +#endif + +/**************************************************************************** + * Name: devurandom_register + * + * Description: + * Register /dev/urandom + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_DEV_URANDOM_ARCH +void devurandom_register(void) +{ +#ifndef CONFIG_DEV_RANDOM + stm32_rng_initialize(); +#endif + register_driver("/dev/urandom", &g_rngops, 0444, NULL); +} +#endif + +#endif /* CONFIG_DEV_RANDOM || CONFIG_DEV_URANDOM_ARCH */ +#endif /* CONFIG_STM32_RNG */ diff --git a/arch/arm/src/common/stm32/stm32_rng_m3m4_v1.c b/arch/arm/src/common/stm32/stm32_rng_m3m4_v1.c new file mode 100644 index 0000000000000..a40caf80bd529 --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_rng_m3m4_v1.c @@ -0,0 +1,314 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_rng_m3m4_v1.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#include "hardware/stm32_rng.h" +#include "arm_internal.h" + +#if defined(CONFIG_STM32_RNG) +#if defined(CONFIG_DEV_RANDOM) || defined(CONFIG_DEV_URANDOM_ARCH) + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +static int stm32_rng_initialize(void); +static int stm32_rng_interrupt(int irq, void *context, void *arg); +static void stm32_rng_enable(void); +static void stm32_rng_disable(void); +static ssize_t stm32_rng_read(struct file *filep, char *buffer, size_t); + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +struct rng_dev_s +{ + mutex_t rd_devlock; /* Threads can only exclusively access the RNG */ + sem_t rd_readsem; /* To block until the buffer is filled */ + char *rd_buf; + size_t rd_buflen; + uint32_t rd_lastval; + bool rd_first; +}; + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static struct rng_dev_s g_rngdev = +{ + .rd_devlock = NXMUTEX_INITIALIZER, + .rd_readsem = SEM_INITIALIZER(0), +}; + +static const struct file_operations g_rngops = +{ + NULL, /* open */ + NULL, /* close */ + stm32_rng_read, /* read */ +}; + +/**************************************************************************** + * Private functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_rng_initialize + ****************************************************************************/ + +static int stm32_rng_initialize(void) +{ + uint32_t regval; + + _info("Initializing RNG\n"); + + if (irq_attach(STM32_IRQ_RNG, stm32_rng_interrupt, NULL)) + { + /* We could not attach the ISR to the interrupt */ + + _info("Could not attach IRQ.\n"); + + return -EAGAIN; + } + + /* Enable interrupts */ + + regval = getreg32(STM32_RNG_CR); + regval |= RNG_CR_IE; + putreg32(regval, STM32_RNG_CR); + + up_enable_irq(STM32_IRQ_RNG); + + return OK; +} + +/**************************************************************************** + * Name: stm32_rng_enable + ****************************************************************************/ + +static void stm32_rng_enable(void) +{ + uint32_t regval; + + g_rngdev.rd_first = true; + + regval = getreg32(STM32_RNG_CR); + regval |= RNG_CR_RNGEN; + putreg32(regval, STM32_RNG_CR); +} + +/**************************************************************************** + * Name: stm32_rng_disable + ****************************************************************************/ + +static void stm32_rng_disable(void) +{ + uint32_t regval; + regval = getreg32(STM32_RNG_CR); + regval &= ~RNG_CR_RNGEN; + putreg32(regval, STM32_RNG_CR); +} + +/**************************************************************************** + * Name: stm32_rng_interrupt + ****************************************************************************/ + +static int stm32_rng_interrupt(int irq, void *context, void *arg) +{ + uint32_t rngsr; + uint32_t data; + + rngsr = getreg32(STM32_RNG_SR); + + if ((rngsr & (RNG_SR_SEIS | RNG_SR_CEIS)) /* Check for error bits */ + || !(rngsr & RNG_SR_DRDY)) /* Data ready must be set */ + { + /* This random value is not valid, we will try again. */ + + return OK; + } + + data = getreg32(STM32_RNG_DR); + + /* As required by the FIPS PUB (Federal Information Processing Standard + * Publication) 140-2, the first random number generated after setting the + * RNGEN bit should not be used, but saved for comparison with the next + * generated random number. Each subsequent generated random number has to + * be compared with the previously generated number. The test fails if any + * two compared numbers are equal (continuous random number generator + * test). + */ + + if (g_rngdev.rd_first) + { + g_rngdev.rd_first = false; + g_rngdev.rd_lastval = data; + return OK; + } + + if (g_rngdev.rd_lastval == data) + { + /* Two subsequent same numbers, we will try again. */ + + return OK; + } + + /* If we get here, the random number is valid. */ + + g_rngdev.rd_lastval = data; + + if (g_rngdev.rd_buflen >= 4) + { + g_rngdev.rd_buflen -= 4; + *(uint32_t *)&g_rngdev.rd_buf[g_rngdev.rd_buflen] = data; + } + else + { + while (g_rngdev.rd_buflen > 0) + { + g_rngdev.rd_buf[--g_rngdev.rd_buflen] = (char)data; + data >>= 8; + } + } + + if (g_rngdev.rd_buflen == 0) + { + /* Buffer filled, stop further interrupts. */ + + stm32_rng_disable(); + nxsem_post(&g_rngdev.rd_readsem); + } + + return OK; +} + +/**************************************************************************** + * Name: stm32_rng_read + ****************************************************************************/ + +static ssize_t stm32_rng_read(struct file *filep, char *buffer, + size_t buflen) +{ + int ret; + + ret = nxmutex_lock(&g_rngdev.rd_devlock); + if (ret < 0) + { + return ret; + } + + /* We've got the mutex. */ + + /* Reset the operation semaphore with 0 for blocking until the + * buffer is filled from interrupts. + */ + + nxsem_reset(&g_rngdev.rd_readsem, 0); + + g_rngdev.rd_buflen = buflen; + g_rngdev.rd_buf = buffer; + + /* Enable RNG with interrupts */ + + stm32_rng_enable(); + + /* Wait until the buffer is filled */ + + ret = nxsem_wait(&g_rngdev.rd_readsem); + + /* Free RNG for next use */ + + nxmutex_unlock(&g_rngdev.rd_devlock); + return ret < 0 ? ret : buflen; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: devrandom_register + * + * Description: + * Initialize the RNG hardware and register the /dev/random driver. + * Must be called BEFORE devurandom_register. + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_DEV_RANDOM +void devrandom_register(void) +{ + stm32_rng_initialize(); + register_driver("/dev/random", &g_rngops, 0444, NULL); +} +#endif + +/**************************************************************************** + * Name: devurandom_register + * + * Description: + * Register /dev/urandom + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_DEV_URANDOM_ARCH +void devurandom_register(void) +{ +#ifndef CONFIG_DEV_RANDOM + stm32_rng_initialize(); +#endif + register_driver("/dev/urandom", &g_rngops, 0444, NULL); +} +#endif + +#endif /* CONFIG_DEV_RANDOM || CONFIG_DEV_URANDOM_ARCH */ +#endif /* CONFIG_STM32_RNG */ diff --git a/arch/arm/src/common/stm32/stm32_rtc.h b/arch/arm/src/common/stm32/stm32_rtc.h new file mode 100644 index 0000000000000..96c8e4f5b8bcb --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_rtc.h @@ -0,0 +1,229 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_rtc.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_RTC_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_RTC_H + +#include + +#ifdef CONFIG_STM32_HAVE_IP_RTC_M3M4_V1 + +#include "chip.h" + +/* The STM32 F1 has a simple battery-backed counter for its RTC and has a + * separate block for the BKP registers. + */ + +#if defined(CONFIG_STM32_STM32F10XX) +# include "hardware/stm32_rtc.h" +# include "hardware/stm32_bkp.h" + +/* The other families use a more traditional Realtime Clock/Calendar (RTCC) + * with broken-out data/time in BCD format. The backup registers are + * integrated into the RTCC in these families. + */ + +#elif defined(CONFIG_STM32_STM32L15XX) || defined(CONFIG_STM32_STM32F20XX) || \ + defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F4XXX) +# include "hardware/stm32_rtcc.h" +#endif + +/* Alarm function differs from part to part */ + +#if defined(CONFIG_STM32_STM32F4XXX) +# include "stm32f40xxx_alarm.h" +#elif defined(CONFIG_STM32_STM32L15XX) +# include "stm32l15xxx_alarm.h" +#else +# include "stm32_alarm.h" +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define STM32_RTC_PRESCALER_SECOND 32767 /* Default prescaler to get a + * second base */ +#define STM32_RTC_PRESCALER_MIN 1 /* Maximum speed of 16384 Hz */ + +#if defined(CONFIG_STM32_STM32F10XX) +/* RTC is only a counter, store RTC data in backup domain register DR1 (if + * CONFIG_RTC_HIRES) and DR2 (state). + */ + +#if !defined(CONFIG_STM32_RTC_MAGIC) +# define CONFIG_STM32_RTC_MAGIC (0xface) /* only 16 bit */ +#endif + +#if !defined(CONFIG_STM32_RTC_MAGIC_TIME_SET) +# define CONFIG_STM32_RTC_MAGIC_TIME_SET (0xf00d) +#endif + +#define RTC_MAGIC_REG STM32_BKP_DR2 + +#else /* !CONFIG_STM32_STM32F10XX */ + +#if !defined(CONFIG_STM32_RTC_MAGIC) +# define CONFIG_STM32_RTC_MAGIC (0xfacefeed) +#endif + +#if !defined(CONFIG_STM32_RTC_MAGIC_TIME_SET) +# define CONFIG_STM32_RTC_MAGIC_TIME_SET (0xf00dface) +#endif + +#if !defined(CONFIG_STM32_RTC_MAGIC_REG) +# define CONFIG_STM32_RTC_MAGIC_REG (0) +#endif + +#define RTC_MAGIC_REG STM32_RTC_BKR(CONFIG_STM32_RTC_MAGIC_REG) + +#endif /* CONFIG_STM32_STM32F10XX */ + +#define RTC_MAGIC CONFIG_STM32_RTC_MAGIC +#define RTC_MAGIC_TIME_SET CONFIG_STM32_RTC_MAGIC_TIME_SET + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_rtc_irqinitialize + * + * Description: + * Initialize IRQs for RTC, not possible during up_rtc_initialize because + * up_irqinitialize is called later. + * + * Input Parameters: + * None + * + * Returned Value: + * Zero (OK) on success; a negated errno on failure + * + ****************************************************************************/ + +int stm32_rtc_irqinitialize(void); + +/**************************************************************************** + * Name: stm32_rtc_getdatetime_with_subseconds + * + * Description: + * Get the current date and time from the date/time RTC. This interface + * is only supported by the date/time RTC hardware implementation. + * It is used to replace the system timer. It is only used by the RTOS + * during initialization to set up the system time when CONFIG_RTC and + * CONFIG_RTC_DATETIME are selected (and CONFIG_RTC_HIRES is not). + * + * NOTE: Some date/time RTC hardware is capability of sub-second accuracy. + * Thatsub-second accuracy is returned through 'nsec'. + * + * Input Parameters: + * tp - The location to return the high resolution time value. + * nsec - The location to return the subsecond time value. + * + * Returned Value: + * Zero (OK) on success; a negated errno on failure + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_HAVE_RTC_SUBSECONDS +int stm32_rtc_getdatetime_with_subseconds(struct tm *tp, long *nsec); +#endif + +/**************************************************************************** + * Name: stm32_rtc_setdatetime + * + * Description: + * Set the RTC to the provided time. RTC implementations which provide + * up_rtc_getdatetime() (CONFIG_RTC_DATETIME is selected) should provide + * this function. + * + * Input Parameters: + * tp - the time to use + * + * Returned Value: + * Zero (OK) on success; a negated errno on failure + * + ****************************************************************************/ + +#ifdef CONFIG_RTC_DATETIME +struct tm; +int stm32_rtc_setdatetime(const struct tm *tp); +#endif + +/**************************************************************************** + * Name: stm32_rtc_lowerhalf + * + * Description: + * Instantiate the RTC lower half driver for the STM32. General usage: + * + * #include + * #include "stm32_rtc.h" + * + * struct rtc_lowerhalf_s *lower; + * lower = stm32_rtc_lowerhalf(); + * rtc_initialize(0, lower); + * + * Input Parameters: + * None + * + * Returned Value: + * On success, a non-NULL RTC lower interface is returned. NULL is + * returned on any failure. + * + ****************************************************************************/ + +#ifdef CONFIG_RTC_DRIVER +struct rtc_lowerhalf_s; +struct rtc_lowerhalf_s *stm32_rtc_lowerhalf(void); +#endif + +#undef EXTERN +#if defined(__cplusplus) +} +#endif +#endif /* __ASSEMBLY__ */ + +#endif /* CONFIG_STM32_HAVE_IP_RTC_M3M4_V1 */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_RTC_H */ diff --git a/arch/arm/src/common/stm32/stm32_rtc_m3m4_v1_lowerhalf.c b/arch/arm/src/common/stm32/stm32_rtc_m3m4_v1_lowerhalf.c new file mode 100644 index 0000000000000..e8c1c75fc9d84 --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_rtc_m3m4_v1_lowerhalf.c @@ -0,0 +1,931 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_rtc_m3m4_v1_lowerhalf.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include + +#include +#include +#include + +#include "arm_internal.h" +#include "chip.h" +#include "stm32_rtc.h" + +#ifdef CONFIG_RTC_DRIVER + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#if defined(CONFIG_STM32_STM32F4XXX) || defined(CONFIG_STM32_STM32L15XX) +# define STM32_NALARMS 2 +#else +# define STM32_NALARMS 1 +#endif + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +#ifdef CONFIG_RTC_ALARM +struct stm32_cbinfo_s +{ + volatile rtc_alarm_callback_t cb; /* Callback when the alarm expires */ + volatile void *priv; /* Private argument to accompany callback */ +#if defined(CONFIG_STM32_STM32F4XXX) || defined(CONFIG_STM32_STM32L15XX) + uint8_t id; /* Identifies the alarm */ +#endif +}; +#endif + +/* This is the private type for the RTC state. It must be cast compatible + * with struct rtc_lowerhalf_s. + */ + +struct stm32_lowerhalf_s +{ + /* This is the contained reference to the read-only, lower-half + * operations vtable (which may lie in FLASH or ROM) + */ + + const struct rtc_ops_s *ops; + + /* Data following is private to this driver and not visible outside of + * this file. + */ + + mutex_t devlock; /* Threads can only exclusively access the RTC */ + +#ifdef CONFIG_RTC_ALARM + /* Alarm callback information */ + + struct stm32_cbinfo_s cbinfo[STM32_NALARMS]; +#endif + +#ifdef CONFIG_RTC_PERIODIC + /* Periodic wakeup information */ + + struct lower_setperiodic_s periodic; +#endif +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/* Prototypes for static methods in struct rtc_ops_s */ + +static int stm32_rdtime(struct rtc_lowerhalf_s *lower, + struct rtc_time *rtctime); +static int stm32_settime(struct rtc_lowerhalf_s *lower, + const struct rtc_time *rtctime); +static bool stm32_havesettime(struct rtc_lowerhalf_s *lower); + +#ifdef CONFIG_RTC_ALARM +static int stm32_setalarm(struct rtc_lowerhalf_s *lower, + const struct lower_setalarm_s *alarminfo); +static int stm32_setrelative(struct rtc_lowerhalf_s *lower, + const struct lower_setrelative_s *alarminfo); +static int stm32_cancelalarm(struct rtc_lowerhalf_s *lower, + int alarmid); +static int stm32_rdalarm(struct rtc_lowerhalf_s *lower, + struct lower_rdalarm_s *alarminfo); +#endif + +#ifdef CONFIG_RTC_PERIODIC +static int stm32_setperiodic(struct rtc_lowerhalf_s *lower, + const struct lower_setperiodic_s *alarminfo); +static int stm32_cancelperiodic(struct rtc_lowerhalf_s *lower, int id); +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* STM32 RTC driver operations */ + +static const struct rtc_ops_s g_rtc_ops = +{ + .rdtime = stm32_rdtime, + .settime = stm32_settime, + .havesettime = stm32_havesettime, +#ifdef CONFIG_RTC_ALARM + .setalarm = stm32_setalarm, + .setrelative = stm32_setrelative, + .cancelalarm = stm32_cancelalarm, + .rdalarm = stm32_rdalarm, +#endif +#ifdef CONFIG_RTC_PERIODIC + .setperiodic = stm32_setperiodic, + .cancelperiodic = stm32_cancelperiodic, +#endif +}; + +/* STM32 RTC device state */ + +static struct stm32_lowerhalf_s g_rtc_lowerhalf = +{ + .ops = &g_rtc_ops, + .devlock = NXMUTEX_INITIALIZER, +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_alarm_callback + * + * Description: + * This is the function that is called from the RTC driver when the alarm + * goes off. It just invokes the upper half drivers callback. + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_RTC_ALARM +#if defined(CONFIG_STM32_STM32F4XXX) || defined(CONFIG_STM32_STM32L15XX) +static void stm32_alarm_callback(void *arg, unsigned int alarmid) +{ + struct stm32_lowerhalf_s *lower; + struct stm32_cbinfo_s *cbinfo; + rtc_alarm_callback_t cb; + void *priv; + + DEBUGASSERT(alarmid == RTC_ALARMA || alarmid == RTC_ALARMB); + + lower = (struct stm32_lowerhalf_s *)arg; + cbinfo = &lower->cbinfo[alarmid]; + + /* Sample and clear the callback information to minimize the window in + * time in which race conditions can occur. + */ + + cb = (rtc_alarm_callback_t)cbinfo->cb; + priv = (void *)cbinfo->priv; + DEBUGASSERT(priv != NULL); + + cbinfo->cb = NULL; + cbinfo->priv = NULL; + + /* Perform the callback */ + + if (cb != NULL) + { + cb(priv, alarmid); + } +} + +#else +static void stm32_alarm_callback(void) +{ + struct stm32_cbinfo_s *cbinfo = &g_rtc_lowerhalf.cbinfo[0]; + + /* Sample and clear the callback information to minimize the window in + * time in which race conditions can occur. + */ + + rtc_alarm_callback_t cb = (rtc_alarm_callback_t)cbinfo->cb; + void *arg = (void *)cbinfo->priv; + + cbinfo->cb = NULL; + cbinfo->priv = NULL; + + /* Perform the callback */ + + if (cb != NULL) + { + cb(arg, 0); + } +} + +#endif /* CONFIG_STM32_STM32F4XXX || CONFIG_STM32_STM32L15XX */ +#endif /* CONFIG_RTC_ALARM */ + +/**************************************************************************** + * Name: stm32_rdtime + * + * Description: + * Implements the rdtime() method of the RTC driver interface + * + * Input Parameters: + * lower - A reference to RTC lower half driver state structure + * rcttime - The location in which to return the current RTC time. + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned + * on any failure. + * + ****************************************************************************/ + +static int stm32_rdtime(struct rtc_lowerhalf_s *lower, + struct rtc_time *rtctime) +{ +#if defined(CONFIG_RTC_DATETIME) + /* This operation depends on the fact that struct rtc_time is cast + * compatible with struct tm. + */ + + return up_rtc_getdatetime((struct tm *)rtctime); + +#elif defined(CONFIG_RTC_HIRES) + struct timespec ts; + int ret; + + /* Get the higher resolution time */ + + ret = up_rtc_gettime(&ts); + if (ret < 0) + { + goto errout; + } + + /* Convert the one second epoch time to a struct tm. This operation + * depends on the fact that struct rtc_time and struct tm are cast + * compatible. + */ + + if (!gmtime_r(&ts.tv_sec, (struct tm *)rtctime)) + { + ret = -get_errno(); + goto errout; + } + + return OK; + +errout: + DEBUGASSERT(ret < 0); + return ret; + +#else + time_t timer; + + /* The resolution of time is only 1 second */ + + timer = up_rtc_time(); + + /* Convert the one second epoch time to a struct tm */ + + if (!gmtime_r(&timer, (struct tm *)rtctime)) + { + int errcode = get_errno(); + DEBUGASSERT(errcode > 0); + return -errcode; + } + + return OK; +#endif +} + +/**************************************************************************** + * Name: stm32_settime + * + * Description: + * Implements the settime() method of the RTC driver interface + * + * Input Parameters: + * lower - A reference to RTC lower half driver state structure + * rcttime - The new time to set + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned + * on any failure. + * + ****************************************************************************/ + +static int stm32_settime(struct rtc_lowerhalf_s *lower, + const struct rtc_time *rtctime) +{ +#ifdef CONFIG_RTC_DATETIME + /* This operation depends on the fact that struct rtc_time is cast + * compatible with struct tm. + */ + + return stm32_rtc_setdatetime((const struct tm *)rtctime); + +#else + struct timespec ts; + + /* Convert the struct rtc_time to a time_t. Here we assume that struct + * rtc_time is cast compatible with struct tm. + */ + + ts.tv_sec = timegm((struct tm *)rtctime); + ts.tv_nsec = 0; + + /* Now set the time (to one second accuracy) */ + + return up_rtc_settime(&ts); +#endif +} + +/**************************************************************************** + * Name: stm32_havesettime + * + * Description: + * Implements the havesettime() method of the RTC driver interface + * + * Input Parameters: + * lower - A reference to RTC lower half driver state structure + * + * Returned Value: + * Returns true if RTC date-time have been previously set. + * + ****************************************************************************/ + +static bool stm32_havesettime(struct rtc_lowerhalf_s *lower) +{ +#if defined(CONFIG_STM32_STM32F10XX) + return getreg16(RTC_MAGIC_REG) == RTC_MAGIC_TIME_SET; +#else + return getreg32(RTC_MAGIC_REG) == RTC_MAGIC_TIME_SET; +#endif +} + +/**************************************************************************** + * Name: stm32_setalarm + * + * Description: + * Set a new alarm. This function implements the setalarm() method of the + * RTC driver interface + * + * Input Parameters: + * lower - A reference to RTC lower half driver state structure + * alarminfo - Provided information needed to set the alarm + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned + * on any failure. + * + ****************************************************************************/ + +#ifdef CONFIG_RTC_ALARM +static int stm32_setalarm(struct rtc_lowerhalf_s *lower, + const struct lower_setalarm_s *alarminfo) +{ +#if defined(CONFIG_STM32_STM32F4XXX) || defined(CONFIG_STM32_STM32L15XX) + struct stm32_lowerhalf_s *priv; + struct stm32_cbinfo_s *cbinfo; + struct alm_setalarm_s lowerinfo; + int ret; + + /* ID0-> Alarm A; ID1 -> Alarm B */ + + DEBUGASSERT(lower != NULL && alarminfo != NULL); + DEBUGASSERT(alarminfo->id == RTC_ALARMA || alarminfo->id == RTC_ALARMB); + priv = (struct stm32_lowerhalf_s *)lower; + + ret = nxmutex_lock(&priv->devlock); + if (ret < 0) + { + return ret; + } + + ret = -EINVAL; + if (alarminfo->id == RTC_ALARMA || alarminfo->id == RTC_ALARMB) + { + /* Remember the callback information */ + + cbinfo = &priv->cbinfo[alarminfo->id]; + cbinfo->cb = alarminfo->cb; + cbinfo->priv = alarminfo->priv; + cbinfo->id = alarminfo->id; + + /* Set the alarm */ + + lowerinfo.as_id = alarminfo->id; + lowerinfo.as_cb = stm32_alarm_callback; + lowerinfo.as_arg = priv; + memcpy(&lowerinfo.as_time, &alarminfo->time, sizeof(struct tm)); + + /* And set the alarm */ + + ret = stm32_rtc_setalarm(&lowerinfo); + if (ret < 0) + { + cbinfo->cb = NULL; + cbinfo->priv = NULL; + } + } + + nxmutex_unlock(&priv->devlock); + return ret; + +#else + struct stm32_lowerhalf_s *priv; + struct stm32_cbinfo_s *cbinfo; + int ret; + + DEBUGASSERT(lower != NULL && alarminfo != NULL && alarminfo->id == 0); + priv = (struct stm32_lowerhalf_s *)lower; + + ret = nxmutex_lock(&priv->devlock); + if (ret < 0) + { + return ret; + } + + ret = -EINVAL; + if (alarminfo->id == 0) + { + struct timespec ts; + + /* Convert the RTC time to a timespec (1 second accuracy) */ + + ts.tv_sec = timegm((struct tm *)&alarminfo->time); + ts.tv_nsec = 0; + + /* Remember the callback information */ + + cbinfo = &priv->cbinfo[0]; + cbinfo->cb = alarminfo->cb; + cbinfo->priv = alarminfo->priv; + + /* And set the alarm */ + + ret = stm32_rtc_setalarm(&ts, stm32_alarm_callback); + if (ret < 0) + { + cbinfo->cb = NULL; + cbinfo->priv = NULL; + } + } + + nxmutex_unlock(&priv->devlock); + return ret; +#endif +} +#endif + +/**************************************************************************** + * Name: stm32_setrelative + * + * Description: + * Set a new alarm relative to the current time. This function implements + * the setrelative() method of the RTC driver interface + * + * Input Parameters: + * lower - A reference to RTC lower half driver state structure + * alarminfo - Provided information needed to set the alarm + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned + * on any failure. + * + ****************************************************************************/ + +#ifdef CONFIG_RTC_ALARM +static int stm32_setrelative(struct rtc_lowerhalf_s *lower, + const struct lower_setrelative_s *alarminfo) +{ +#if defined(CONFIG_STM32_STM32F4XXX) || defined(CONFIG_STM32_STM32L15XX) + struct lower_setalarm_s setalarm; + struct tm time; + time_t seconds; + int ret = -EINVAL; + irqstate_t flags; + + DEBUGASSERT(lower != NULL && alarminfo != NULL); + DEBUGASSERT(alarminfo->id == RTC_ALARMA || alarminfo->id == RTC_ALARMB); + + if ((alarminfo->id == RTC_ALARMA || alarminfo->id == RTC_ALARMB) && + alarminfo->reltime > 0) + { + /* Disable pre-emption while we do this so that we don't have to worry + * about being suspended and working on an old time. + */ + + flags = enter_critical_section(); + + /* Get the current time in broken out format */ + + ret = up_rtc_getdatetime(&time); + if (ret >= 0) + { + /* Convert to seconds since the epoch */ + + seconds = timegm(&time); + + /* Add the seconds offset. Add one to the number of seconds + * because we are unsure of the phase of the timer. + */ + + seconds += (alarminfo->reltime + 1); + + /* And convert the time back to broken out format */ + + gmtime_r(&seconds, (struct tm *)&setalarm.time); + + /* The set the alarm using this absolute time */ + + setalarm.id = alarminfo->id; + setalarm.cb = alarminfo->cb; + setalarm.priv = alarminfo->priv; + + ret = stm32_setalarm(lower, &setalarm); + } + + leave_critical_section(flags); + } + + return ret; + +#else + struct stm32_lowerhalf_s *priv; + struct stm32_cbinfo_s *cbinfo; +#if defined(CONFIG_RTC_DATETIME) + struct tm time; +#endif + struct timespec ts; + int ret = -EINVAL; + irqstate_t flags; + + DEBUGASSERT(lower != NULL && alarminfo != NULL && alarminfo->id == 0); + priv = (struct stm32_lowerhalf_s *)lower; + + if (alarminfo->id == 0 && alarminfo->reltime > 0) + { + /* Disable pre-emption while we do this so that we don't have to worry + * about being suspended and working on an old time. + */ + + flags = enter_critical_section(); + + /* Get the current time in seconds */ + +#if defined(CONFIG_RTC_DATETIME) + /* Get the broken out time and convert to seconds */ + + ret = up_rtc_getdatetime(&time); + if (ret < 0) + { + leave_critical_section(flags); + return ret; + } + + ts.tv_sec = timegm(&time); + ts.tv_nsec = 0; + +#elif defined(CONFIG_RTC_HIRES) + /* Get the higher resolution time */ + + ret = up_rtc_gettime(&ts); + if (ret < 0) + { + leave_critical_section(flags); + return ret; + } +#else + /* The resolution of time is only 1 second */ + + ts.tv_sec = up_rtc_time(); + ts.tv_nsec = 0; +#endif + + /* Add the seconds offset. Add one to the number of seconds because + * we are unsure of the phase of the timer. + */ + + ts.tv_sec += (alarminfo->reltime + 1); + + /* Remember the callback information */ + + cbinfo = &priv->cbinfo[0]; + cbinfo->cb = alarminfo->cb; + cbinfo->priv = alarminfo->priv; + + /* And set the alarm */ + + ret = stm32_rtc_setalarm(&ts, stm32_alarm_callback); + if (ret < 0) + { + cbinfo->cb = NULL; + cbinfo->priv = NULL; + } + + leave_critical_section(flags); + } + + return ret; +#endif +} +#endif + +/**************************************************************************** + * Name: stm32_cancelalarm + * + * Description: + * Cancel the current alarm. This function implements the cancelalarm() + * method of the RTC driver interface + * + * Input Parameters: + * lower - A reference to RTC lower half driver state structure + * alarminfo - Provided information needed to set the alarm + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned + * on any failure. + * + ****************************************************************************/ + +#ifdef CONFIG_RTC_ALARM +static int stm32_cancelalarm(struct rtc_lowerhalf_s *lower, int alarmid) +{ +#if defined(CONFIG_STM32_STM32F4XXX) || defined(CONFIG_STM32_STM32L15XX) + struct stm32_lowerhalf_s *priv; + struct stm32_cbinfo_s *cbinfo; + int ret; + + DEBUGASSERT(lower != NULL); + DEBUGASSERT(alarmid == RTC_ALARMA || alarmid == RTC_ALARMB); + priv = (struct stm32_lowerhalf_s *)lower; + + ret = nxmutex_lock(&priv->devlock); + if (ret < 0) + { + return ret; + } + + /* ID0-> Alarm A; ID1 -> Alarm B */ + + ret = -EINVAL; + if (alarmid == RTC_ALARMA || alarmid == RTC_ALARMB) + { + /* Nullify callback information to reduce window for race conditions */ + + cbinfo = &priv->cbinfo[alarmid]; + cbinfo->cb = NULL; + cbinfo->priv = NULL; + + /* Then cancel the alarm */ + + ret = stm32_rtc_cancelalarm((enum alm_id_e)alarmid); + } + + nxmutex_unlock(&priv->devlock); + return ret; + +#else + struct stm32_lowerhalf_s *priv; + struct stm32_cbinfo_s *cbinfo; + + DEBUGASSERT(lower != NULL); + DEBUGASSERT(alarmid == 0); + priv = (struct stm32_lowerhalf_s *)lower; + + /* Nullify callback information to reduce window for race conditions */ + + cbinfo = &priv->cbinfo[0]; + cbinfo->cb = NULL; + cbinfo->priv = NULL; + + /* Then cancel the alarm */ + + return stm32_rtc_cancelalarm(); +#endif +} +#endif + +/**************************************************************************** + * Name: stm32_rdalarm + * + * Description: + * Query the RTC alarm. + * + * Input Parameters: + * lower - A reference to RTC lower half driver state structure + * alarminfo - Provided information needed to query the alarm + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned + * on any failure. + * + ****************************************************************************/ + +#ifdef CONFIG_RTC_ALARM +static int stm32_rdalarm(struct rtc_lowerhalf_s *lower, + struct lower_rdalarm_s *alarminfo) +{ + struct alm_rdalarm_s lowerinfo; + int ret = -EINVAL; + irqstate_t flags; + + DEBUGASSERT(lower != NULL && alarminfo != NULL && alarminfo->time != NULL); +#if defined(CONFIG_STM32_STM32F4XXX) || defined(CONFIG_STM32_STM32L15XX) + DEBUGASSERT(alarminfo->id == RTC_ALARMA || alarminfo->id == RTC_ALARMB); + + if (alarminfo->id == RTC_ALARMA || alarminfo->id == RTC_ALARMB) +#else + DEBUGASSERT(alarminfo->id >= 0 && alarminfo->id < CONFIG_RTC_NALARMS); + + if (alarminfo != NULL && alarminfo->id >= 0 && + alarminfo->id < CONFIG_RTC_NALARMS) +#endif + { + /* Disable pre-emption while we do this so that we don't have to worry + * about being suspended and working on an old time. + */ + + flags = enter_critical_section(); + + lowerinfo.ar_id = alarminfo->id; + lowerinfo.ar_time = alarminfo->time; + + ret = stm32_rtc_rdalarm(&lowerinfo); + + leave_critical_section(flags); + } + + return ret; +} +#endif + +/**************************************************************************** + * Name: stm32_periodic_callback + * + * Description: + * This is the function that is called from the RTC driver when the + * periodic wakeup goes off. It just invokes the upper half drivers + * callback. + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_RTC_PERIODIC +static int stm32_periodic_callback(void) +{ + struct stm32_lowerhalf_s *lower; + struct lower_setperiodic_s *cbinfo; + rtc_wakeup_callback_t cb; + void *priv; + + lower = (struct stm32_lowerhalf_s *)&g_rtc_lowerhalf; + + cbinfo = &lower->periodic; + cb = (rtc_wakeup_callback_t)cbinfo->cb; + priv = (void *)cbinfo->priv; + + /* Perform the callback */ + + if (cb != NULL) + { + cb(priv, 0); + } + + return OK; +} +#endif /* CONFIG_RTC_PERIODIC */ + +/**************************************************************************** + * Name: stm32_setperiodic + * + * Description: + * Set a new periodic wakeup relative to the current time, with a given + * period. This function implements the setperiodic() method of the RTC + * driver interface + * + * Input Parameters: + * lower - A reference to RTC lower half driver state structure + * alarminfo - Provided information needed to set the wakeup activity + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned + * on any failure. + * + ****************************************************************************/ + +#ifdef CONFIG_RTC_PERIODIC +static int stm32_setperiodic(struct rtc_lowerhalf_s *lower, + const struct lower_setperiodic_s *alarminfo) +{ + struct stm32_lowerhalf_s *priv; + int ret; + + DEBUGASSERT(lower != NULL && alarminfo != NULL); + priv = (struct stm32_lowerhalf_s *)lower; + + ret = nxmutex_lock(&priv->devlock); + if (ret < 0) + { + return ret; + } + + memcpy(&priv->periodic, alarminfo, sizeof(struct lower_setperiodic_s)); + ret = stm32_rtc_setperiodic(&alarminfo->period, stm32_periodic_callback); + + nxmutex_unlock(&priv->devlock); + return ret; +} +#endif + +/**************************************************************************** + * Name: stm32_cancelperiodic + * + * Description: + * Cancel the current periodic wakeup activity. This function implements + * the cancelperiodic() method of the RTC driver interface + * + * Input Parameters: + * lower - A reference to RTC lower half driver state structure + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned + * on any failure. + * + ****************************************************************************/ + +#ifdef CONFIG_RTC_PERIODIC +static int stm32_cancelperiodic(struct rtc_lowerhalf_s *lower, int id) +{ + struct stm32_lowerhalf_s *priv; + int ret; + + DEBUGASSERT(lower != NULL); + priv = (struct stm32_lowerhalf_s *)lower; + + DEBUGASSERT(id == 0); + + ret = nxmutex_lock(&priv->devlock); + if (ret < 0) + { + return ret; + } + + ret = stm32_rtc_cancelperiodic(); + + nxmutex_unlock(&priv->devlock); + return ret; +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_rtc_lowerhalf + * + * Description: + * Instantiate the RTC lower half driver for the STM32. General usage: + * + * #include + * #include "stm32_rtc.h> + * + * struct rtc_lowerhalf_s *lower; + * lower = stm32_rtc_lowerhalf(); + * rtc_initialize(0, lower); + * + * Input Parameters: + * None + * + * Returned Value: + * On success, a non-NULL RTC lower interface is returned. NULL is + * returned on any failure. + * + ****************************************************************************/ + +struct rtc_lowerhalf_s *stm32_rtc_lowerhalf(void) +{ + return (struct rtc_lowerhalf_s *)&g_rtc_lowerhalf; +} + +#endif /* CONFIG_RTC_DRIVER */ diff --git a/arch/arm/src/common/stm32/stm32_rtcc_m3m4_f4.c b/arch/arm/src/common/stm32/stm32_rtcc_m3m4_f4.c new file mode 100644 index 0000000000000..9dff0b4bccab7 --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_rtcc_m3m4_f4.c @@ -0,0 +1,1633 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_rtcc_m3m4_f4.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include "arm_internal.h" +#include "stm32_rcc.h" +#include "stm32_pwr.h" +#include "stm32_exti.h" +#include "stm32_rtc.h" + +#include + +#ifdef CONFIG_STM32_RTC + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* This RTC implementation supports + * - date/time RTC hardware + * - extended functions Alarm A and B for STM32F4xx and onwards + * */ + +#ifndef CONFIG_RTC_DATETIME +# error "CONFIG_RTC_DATETIME must be set to use this driver" +#endif + +#ifdef CONFIG_RTC_HIRES +# error "CONFIG_RTC_HIRES must NOT be set with this driver" +#endif + +#ifndef CONFIG_STM32_PWR +# error "CONFIG_STM32_PWR must selected to use this driver" +#endif + +/* Constants ****************************************************************/ + +#define SYNCHRO_TIMEOUT (0x00020000) +#define INITMODE_TIMEOUT (0x00010000) + +/* Proxy definitions to make the same code work for all the STM32 series ****/ + +# define STM32_RCC_XXX STM32_RCC_BDCR +# define RCC_XXX_YYYRST RCC_BDCR_BDRST +# define RCC_XXX_RTCEN RCC_BDCR_RTCEN +# define RCC_XXX_RTCSEL_MASK RCC_BDCR_RTCSEL_MASK +# define RCC_XXX_RTCSEL_LSE RCC_BDCR_RTCSEL_LSE +# define RCC_XXX_RTCSEL_LSI RCC_BDCR_RTCSEL_LSI +# define RCC_XXX_RTCSEL_HSE RCC_BDCR_RTCSEL_HSE + +/* Time conversions */ + +#define MINUTES_IN_HOUR 60 +#define HOURS_IN_DAY 24 + +#define hours_add(parm_hrs) \ + time->tm_hour += parm_hrs;\ + if ((HOURS_IN_DAY-1) < (time->tm_hour))\ + {\ + time->tm_hour = (parm_hrs - HOURS_IN_DAY);\ + } + +#define RTC_ALRMR_DIS_MASK (RTC_ALRMR_MSK4 | RTC_ALRMR_MSK3 | \ + RTC_ALRMR_MSK2 | RTC_ALRMR_MSK1) +#define RTC_ALRMR_DIS_DATE_MASK (RTC_ALRMR_MSK4) +#define RTC_ALRMR_ENABLE (0) + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +#ifdef CONFIG_RTC_ALARM +typedef unsigned int rtc_alarmreg_t; + +struct alm_cbinfo_s +{ + volatile alm_callback_t ac_cb; /* Client callback function */ + volatile void *ac_arg; /* Argument to pass with the callback function */ +}; +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#ifdef CONFIG_RTC_ALARM +/* Callback to use when an EXTI is activated */ + +static struct alm_cbinfo_s g_alarmcb[RTC_ALARM_LAST]; +static bool g_alarm_enabled; /* True: Alarm interrupts are enabled */ +#endif + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/* g_rtc_enabled is set true after the RTC has successfully initialized */ + +volatile bool g_rtc_enabled = false; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +#ifdef CONFIG_RTC_ALARM +static int rtchw_check_alrawf(void); +static int rtchw_set_alrmar(rtc_alarmreg_t alarmreg); +#if CONFIG_RTC_NALARMS > 1 +static int rtchw_check_alrbwf(void); +static int rtchw_set_alrmbr(rtc_alarmreg_t alarmreg); +#endif +static inline void rtc_enable_alarm(void); +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: rtc_dumpregs + ****************************************************************************/ + +#ifdef CONFIG_DEBUG_RTC_INFO +static void rtc_dumpregs(const char *msg) +{ + int rtc_state; + + rtcinfo("%s:\n", msg); + rtcinfo(" TR: %08" PRIx32 "\n", getreg32(STM32_RTC_TR)); + rtcinfo(" DR: %08" PRIx32 "\n", getreg32(STM32_RTC_DR)); + rtcinfo(" CR: %08" PRIx32 "\n", getreg32(STM32_RTC_CR)); + rtcinfo(" ISR: %08" PRIx32 "\n", getreg32(STM32_RTC_ISR)); + rtcinfo(" PRER: %08" PRIx32 "\n", getreg32(STM32_RTC_PRER)); + rtcinfo(" WUTR: %08" PRIx32 "\n", getreg32(STM32_RTC_WUTR)); + rtcinfo(" ALRMAR: %08" PRIx32 "\n", getreg32(STM32_RTC_ALRMAR)); + rtcinfo(" ALRMBR: %08" PRIx32 "\n", getreg32(STM32_RTC_ALRMBR)); + rtcinfo(" SHIFTR: %08" PRIx32 "\n", getreg32(STM32_RTC_SHIFTR)); + rtcinfo(" TSTR: %08" PRIx32 "\n", getreg32(STM32_RTC_TSTR)); + rtcinfo(" TSDR: %08" PRIx32 "\n", getreg32(STM32_RTC_TSDR)); + rtcinfo(" TSSSR: %08" PRIx32 "\n", getreg32(STM32_RTC_TSSSR)); + rtcinfo(" CALR: %08" PRIx32 "\n", getreg32(STM32_RTC_CALR)); + rtcinfo(" TAFCR: %08" PRIx32 "\n", getreg32(STM32_RTC_TAFCR)); + rtcinfo("ALRMASSR: %08" PRIx32 "\n", getreg32(STM32_RTC_ALRMASSR)); + rtcinfo("ALRMBSSR: %08" PRIx32 "\n", getreg32(STM32_RTC_ALRMBSSR)); + rtcinfo("MAGICREG: %08" PRIx32 "\n", getreg32(RTC_MAGIC_REG)); + + rtc_state = + ((getreg32(STM32_EXTI_RTSR) & EXTI_RTC_ALARM) ? 0x1000 : 0) | + ((getreg32(STM32_EXTI_FTSR) & EXTI_RTC_ALARM) ? 0x0100 : 0) | + ((getreg32(STM32_EXTI_IMR) & EXTI_RTC_ALARM) ? 0x0010 : 0) | + ((getreg32(STM32_EXTI_EMR) & EXTI_RTC_ALARM) ? 0x0001 : 0); + rtcinfo("EXTI (RTSR FTSR ISR EVT): %01x\n", rtc_state); +} +#else +# define rtc_dumpregs(msg) +#endif + +/**************************************************************************** + * Name: rtc_dumptime + ****************************************************************************/ + +#ifdef CONFIG_DEBUG_RTC_INFO +static void rtc_dumptime(const struct tm *tp, const char *msg) +{ + rtcinfo("%s:\n", msg); + rtcinfo(" tm_sec: %08x\n", tp->tm_sec); + rtcinfo(" tm_min: %08x\n", tp->tm_min); + rtcinfo(" tm_hour: %08x\n", tp->tm_hour); + rtcinfo(" tm_mday: %08x\n", tp->tm_mday); + rtcinfo(" tm_mon: %08x\n", tp->tm_mon); + rtcinfo(" tm_year: %08x\n", tp->tm_year); +} +#else +# define rtc_dumptime(tp, msg) +#endif + +/**************************************************************************** + * Name: rtc_wprunlock + * + * Description: + * Disable RTC write protection + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void rtc_wprunlock(void) +{ + /* Enable write access to the backup domain (RTC registers, RTC backup data + * registers and backup SRAM). + */ + + stm32_pwr_enablebkp(true); + + /* The following steps are required to unlock the write protection on all + * the RTC registers (except for RTC_ISR[13:8], RTC_TAFCR, and RTC_BKPxR): + * + * 1. Write 0xCA into the RTC_WPR register. + * 2. Write 0x53 into the RTC_WPR register. + * + * Writing a wrong key re-activates the write protection. + */ + + putreg32(0xca, STM32_RTC_WPR); + putreg32(0x53, STM32_RTC_WPR); +} + +/**************************************************************************** + * Name: rtc_wprlock + * + * Description: + * Enable RTC write protection + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +static inline void rtc_wprlock(void) +{ + /* Writing any wrong key re-activates the write protection. */ + + putreg32(0xff, STM32_RTC_WPR); + + /* Disable write access to the backup domain (RTC registers, RTC backup + * data registers and backup SRAM). + */ + + stm32_pwr_enablebkp(false); +} + +/**************************************************************************** + * Name: rtc_synchwait + * + * Description: + * Waits until the RTC Time and Date registers (RTC_TR and RTC_DR) are + * synchronized with RTC APB clock. + * + * Input Parameters: + * None + * + * Returned Value: + * Zero (OK) on success; a negated errno on failure + * + ****************************************************************************/ + +static int rtc_synchwait(void) +{ + volatile uint32_t timeout; + uint32_t regval; + int ret; + + /* Disable the write protection for RTC registers */ + + rtc_wprunlock(); + + /* Clear Registers synchronization flag (RSF) */ + + regval = getreg32(STM32_RTC_ISR); + regval &= ~RTC_ISR_RSF; + putreg32(regval, STM32_RTC_ISR); + + /* Now wait the registers to become synchronised */ + + ret = -ETIMEDOUT; + for (timeout = 0; timeout < SYNCHRO_TIMEOUT; timeout++) + { + regval = getreg32(STM32_RTC_ISR); + if ((regval & RTC_ISR_RSF) != 0) + { + /* Synchronized */ + + ret = OK; + break; + } + } + + /* Re-enable the write protection for RTC registers */ + + rtc_wprlock(); + return ret; +} + +/**************************************************************************** + * Name: rtc_enterinit + * + * Description: + * Enter RTC initialization mode. + * + * Input Parameters: + * None + * + * Returned Value: + * Zero (OK) on success; a negated errno on failure + * + ****************************************************************************/ + +static int rtc_enterinit(void) +{ + volatile uint32_t timeout; + uint32_t regval; + int ret; + + /* Check if the Initialization mode is already set */ + + regval = getreg32(STM32_RTC_ISR); + + ret = OK; + if ((regval & RTC_ISR_INITF) == 0) + { + /* Set the Initialization mode */ + + putreg32(RTC_ISR_INIT, STM32_RTC_ISR); + + /* Wait until the RTC is in the INIT state (or a timeout occurs) */ + + ret = -ETIMEDOUT; + for (timeout = 0; timeout < INITMODE_TIMEOUT; timeout++) + { + regval = getreg32(STM32_RTC_ISR); + if ((regval & RTC_ISR_INITF) != 0) + { + ret = OK; + break; + } + } + } + + return ret; +} + +/**************************************************************************** + * Name: rtc_exitinit + * + * Description: + * Exit RTC initialization mode. + * + * Input Parameters: + * None + * + * Returned Value: + * Zero (OK) on success; a negated errno on failure + * + ****************************************************************************/ + +static void rtc_exitinit(void) +{ + uint32_t regval; + + regval = getreg32(STM32_RTC_ISR); + regval &= ~(RTC_ISR_INIT); + putreg32(regval, STM32_RTC_ISR); +} + +/**************************************************************************** + * Name: rtc_bin2bcd + * + * Description: + * Converts a 2 digit binary to BCD format + * + * Input Parameters: + * value - The byte to be converted. + * + * Returned Value: + * The value in BCD representation + * + ****************************************************************************/ + +static uint32_t rtc_bin2bcd(int value) +{ + uint32_t msbcd = 0; + + while (value >= 10) + { + msbcd++; + value -= 10; + } + + return (msbcd << 4) | value; +} + +/**************************************************************************** + * Name: rtc_bin2bcd + * + * Description: + * Convert from 2 digit BCD to binary. + * + * Input Parameters: + * value - The BCD value to be converted. + * + * Returned Value: + * The value in binary representation + * + ****************************************************************************/ + +static int rtc_bcd2bin(uint32_t value) +{ + uint32_t tens = (value >> 4) * 10; + return (int)(tens + (value & 0x0f)); +} + +/**************************************************************************** + * Name: rtc_setup + * + * Description: + * Performs first time configuration of the RTC. A special value written + * into back-up register 0 will prevent this function from being called on + * sub-sequent resets or power up. + * + * Input Parameters: + * None + * + * Returned Value: + * Zero (OK) on success; a negated errno on failure + * + ****************************************************************************/ + +static int rtc_setup(void) +{ + uint32_t regval; + int ret; + + /* Disable the write protection for RTC registers */ + + rtc_wprunlock(); + + /* Set Initialization mode */ + + ret = rtc_enterinit(); + if (ret == OK) + { + /* Set the 24 hour format by clearing the FMT bit in the RTC + * control register + */ + + regval = getreg32(STM32_RTC_CR); + regval &= ~RTC_CR_FMT; + putreg32(regval, STM32_RTC_CR); + + /* Configure RTC pre-scaler with the required values */ + +#ifdef CONFIG_STM32_RTC_HSECLOCK + /* STMicro app note AN4759 suggests using 7999 and 124 to + * get exactly 1MHz when using the RTC at 8MHz. + */ + + putreg32(((uint32_t)7999 << RTC_PRER_PREDIV_S_SHIFT) | + ((uint32_t)124 << RTC_PRER_PREDIV_A_SHIFT), + STM32_RTC_PRER); +#else + /* Correct values for 32.768 KHz LSE clock and inaccurate LSI clock */ + + putreg32(((uint32_t)0xff << RTC_PRER_PREDIV_S_SHIFT) | + ((uint32_t)0x7f << RTC_PRER_PREDIV_A_SHIFT), + STM32_RTC_PRER); +#endif + + /* Exit RTC initialization mode */ + + rtc_exitinit(); + } + + /* Re-enable the write protection for RTC registers */ + + rtc_wprlock(); + + return ret; +} + +/**************************************************************************** + * Name: rtc_resume + * + * Description: + * Called when the RTC was already initialized on a previous power cycle. + * This just brings the RTC back into full operation. + * + * Input Parameters: + * None + * + * Returned Value: + * Zero (OK) on success; a negated errno on failure + * + ****************************************************************************/ + +static void rtc_resume(void) +{ +#ifdef CONFIG_RTC_ALARM + uint32_t regval; + + /* Clear the RTC alarm flags */ + + regval = getreg32(STM32_RTC_ISR); + regval &= ~(RTC_ISR_ALRAF | RTC_ISR_ALRBF); + putreg32(regval, STM32_RTC_ISR); + + /* Clear the RTC Alarm Pending bit */ + + putreg32(EXTI_RTC_ALARM, STM32_EXTI_PR); +#endif +} + +/**************************************************************************** + * Name: stm32_rtc_alarm_handler + * + * Description: + * RTC ALARM interrupt service routine through the EXTI line + * + * Input Parameters: + * irq - The IRQ number that generated the interrupt + * context - Architecture specific register save information. + * + * Returned Value: + * Zero (OK) on success; A negated errno value on failure. + * + ****************************************************************************/ + +#ifdef CONFIG_RTC_ALARM +static int stm32_rtc_alarm_handler(int irq, void *context, void *arg) +{ + struct alm_cbinfo_s *cbinfo; + alm_callback_t cb; + void *cb_arg; + uint32_t isr; + uint32_t cr; + int ret = OK; + + /* Disable the write protection for RTC registers */ + + rtc_wprunlock(); + + isr = getreg32(STM32_RTC_ISR); + + /* Check for EXTI from Alarm A or B and handle according */ + + if ((isr & RTC_ISR_ALRAF) != 0) + { + cr = getreg32(STM32_RTC_CR); + if ((cr & RTC_CR_ALRAIE) != 0) + { + cbinfo = &g_alarmcb[RTC_ALARMA]; + if (cbinfo->ac_cb != NULL) + { + /* Alarm A callback */ + + cb = cbinfo->ac_cb; + cb_arg = (void *)cbinfo->ac_arg; + + cbinfo->ac_cb = NULL; + cbinfo->ac_arg = NULL; + + cb(cb_arg, RTC_ALARMA); + } + + isr = getreg32(STM32_RTC_ISR) & ~RTC_ISR_ALRAF; + putreg32(isr, STM32_RTC_ISR); + } + } + +#if CONFIG_RTC_NALARMS > 1 + if ((isr & RTC_ISR_ALRBF) != 0) + { + cr = getreg32(STM32_RTC_CR); + if ((cr & RTC_CR_ALRBIE) != 0) + { + cbinfo = &g_alarmcb[RTC_ALARMB]; + if (cbinfo->ac_cb != NULL) + { + /* Alarm B callback */ + + cb = cbinfo->ac_cb; + cb_arg = (void *)cbinfo->ac_arg; + + cbinfo->ac_cb = NULL; + cbinfo->ac_arg = NULL; + + cb(cb_arg, RTC_ALARMB); + } + + isr = getreg32(STM32_RTC_ISR) & ~RTC_ISR_ALRBF; + putreg32(isr, STM32_RTC_ISR); + } + } +#endif + + /* Re-enable the write protection for RTC registers */ + + rtc_wprlock(); + return ret; +} +#endif + +/**************************************************************************** + * Name: rtchw_check_alrXwf X= a or B + * + * Description: + * Check registers + * + * Input Parameters: + * None + * + * Returned Value: + * Zero (OK) on success; a negated errno on failure + * + ****************************************************************************/ + +#ifdef CONFIG_RTC_ALARM +static int rtchw_check_alrawf(void) +{ + volatile uint32_t timeout; + uint32_t regval; + int ret = -ETIMEDOUT; + + /* Check RTC_ISR ALRAWF for access to alarm register, + * Can take 2 RTCCLK cycles or timeout + * CubeMX use GetTick. + */ + + for (timeout = 0; timeout < INITMODE_TIMEOUT; timeout++) + { + regval = getreg32(STM32_RTC_ISR); + if ((regval & RTC_ISR_ALRAWF) != 0) + { + ret = OK; + break; + } + } + + return ret; +} +#endif + +#if defined(CONFIG_RTC_ALARM) && CONFIG_RTC_NALARMS > 1 +static int rtchw_check_alrbwf(void) +{ + volatile uint32_t timeout; + uint32_t regval; + int ret = -ETIMEDOUT; + + /* Check RTC_ISR ALRBWF for access to alarm register, + * can take 2 RTCCLK cycles or timeout + * CubeMX use GetTick. + */ + + for (timeout = 0; timeout < INITMODE_TIMEOUT; timeout++) + { + regval = getreg32(STM32_RTC_ISR); + if ((regval & RTC_ISR_ALRBWF) != 0) + { + ret = OK; + break; + } + } + + return ret; +} +#endif + +/**************************************************************************** + * Name: stm32_rtchw_set_alrmXr X is a or b + * + * Description: + * Set the alarm (A or B) hardware registers, using the required hardware + * access protocol + * + * Input Parameters: + * alarmreg - the register + * + * Returned Value: + * Zero (OK) on success; a negated errno on failure + * + ****************************************************************************/ + +#ifdef CONFIG_RTC_ALARM +static int rtchw_set_alrmar(rtc_alarmreg_t alarmreg) +{ + int ret = -EBUSY; + + /* Disable the write protection for RTC registers */ + + rtc_wprunlock(); + + /* Disable RTC alarm & Interrupt */ + + modifyreg32(STM32_RTC_CR, (RTC_CR_ALRAE | RTC_CR_ALRAIE), 0); + + ret = rtchw_check_alrawf(); + if (ret != OK) + { + goto errout_with_wprunlock; + } + + /* Set the RTC Alarm register */ + + putreg32(alarmreg, STM32_RTC_ALRMAR); + rtcinfo(" ALRMAR: %08" PRIx32 "\n", getreg32(STM32_RTC_ALRMAR)); + + /* Enable RTC alarm */ + + modifyreg32(STM32_RTC_CR, 0, (RTC_CR_ALRAE | RTC_CR_ALRAIE)); + +errout_with_wprunlock: + rtc_wprlock(); + return ret; +} +#endif + +#if defined(CONFIG_RTC_ALARM) && CONFIG_RTC_NALARMS > 1 +static int rtchw_set_alrmbr(rtc_alarmreg_t alarmreg) +{ + int ret = -EBUSY; + + /* Disable the write protection for RTC registers */ + + rtc_wprunlock(); + + /* Disable RTC alarm B & Interrupt B */ + + modifyreg32(STM32_RTC_CR, (RTC_CR_ALRBE | RTC_CR_ALRBIE), 0); + + ret = rtchw_check_alrbwf(); + if (ret != OK) + { + goto rtchw_set_alrmbr_exit; + } + + /* Set the RTC Alarm register */ + + putreg32(alarmreg, STM32_RTC_ALRMBR); + rtcinfo(" ALRMBR: %08" PRIx32 "\n", getreg32(STM32_RTC_ALRMBR)); + + /* Enable RTC alarm B */ + + modifyreg32(STM32_RTC_CR, 0, (RTC_CR_ALRBE | RTC_CR_ALRBIE)); + +rtchw_set_alrmbr_exit: + rtc_wprlock(); + return ret; +} +#endif + +/**************************************************************************** + * Name: rtc_enable_alarm + * + * Description: + * Enable ALARM interrupts + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_RTC_ALARM +static inline void rtc_enable_alarm(void) +{ + /* Is the alarm already enabled? */ + + if (!g_alarm_enabled) + { + /* Configure RTC interrupt to catch alarm interrupts. All RTC + * interrupts are connected to the EXTI controller. To enable the + * RTC Alarm interrupt, the following sequence is required: + * + * 1. Configure and enable the EXTI Line 17 RTC ALARM in interrupt + * mode and select the rising edge sensitivity. + * For STM32F4xx + * EXTI line 21 RTC Tamper & Timestamp + * EXTI line 22 RTC Wakeup + * 2. Configure and enable the RTC_Alarm IRQ channel in the NVIC. + * 3. Configure the RTC to generate RTC alarms (Alarm A or Alarm B). + */ + + stm32_exti_alarm(true, false, true, stm32_rtc_alarm_handler, NULL); + g_alarm_enabled = true; + } +} +#endif + +/**************************************************************************** + * Name: stm32_rtc_getalarmdatetime + * + * Description: + * Get the current date and time for a RTC alarm. + * + * Input Parameters: + * reg - RTC alarm register + * tp - The location to return the high resolution time value. + * + * Returned Value: + * Zero (OK) on success; a negated errno on failure + * + ****************************************************************************/ + +#ifdef CONFIG_RTC_ALARM +static int stm32_rtc_getalarmdatetime(rtc_alarmreg_t reg, struct tm *tp) +{ + uint32_t data; + uint32_t tmp; + + DEBUGASSERT(tp != NULL); + + /* Sample the data time register. */ + + data = getreg32(reg); + + /* Convert the RTC time to fields in struct tm format. All of the STM32 + * ranges of values correspond between struct tm and the time register. + */ + + tmp = (data & (RTC_ALRMR_SU_MASK | RTC_ALRMR_ST_MASK)) >> + RTC_ALRMR_SU_SHIFT; + tp->tm_sec = rtc_bcd2bin(tmp); + + tmp = (data & (RTC_ALRMR_MNU_MASK | RTC_ALRMR_MNT_MASK)) >> + RTC_ALRMR_MNU_SHIFT; + tp->tm_min = rtc_bcd2bin(tmp); + + tmp = (data & (RTC_ALRMR_HU_MASK | RTC_ALRMR_HT_MASK)) >> + RTC_ALRMR_HU_SHIFT; + tp->tm_hour = rtc_bcd2bin(tmp); + + tmp = (data & (RTC_ALRMR_DU_MASK | RTC_ALRMR_DT_MASK)) >> + RTC_ALRMR_DU_SHIFT; + tp->tm_mday = rtc_bcd2bin(tmp); + + return OK; +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_rtc_initialize + * + * Description: + * Initialize the hardware RTC per the selected configuration. This + * function is called once during the OS initialization sequence + * + * Input Parameters: + * None + * + * Returned Value: + * Zero (OK) on success; a negated errno on failure + * + ****************************************************************************/ + +int up_rtc_initialize(void) +{ + uint32_t regval; + uint32_t tr_bkp; + uint32_t dr_bkp; + int ret; + int maxretry = 10; + int nretry = 0; + + /* Clocking for the PWR block must be provided. However, this is done + * unconditionally in stm32f40xxx_rcc.c on power up. This done + * unconditionally because the PWR block is also needed to set the + * internal voltage regulator for maximum performance. + */ + + /* Select the clock source */ + + /* Save the token before losing it when resetting */ + + regval = getreg32(RTC_MAGIC_REG); + + stm32_pwr_enablebkp(true); + + if (regval != RTC_MAGIC && regval != RTC_MAGIC_TIME_SET) + { + /* Some boards do not have the external 32khz oscillator installed, + * for those boards we must fallback to the crummy internal RC clock + * or the external high rate clock + */ + +#ifdef CONFIG_STM32_RTC_HSECLOCK + /* Use the HSE clock as the input to the RTC block */ + + rtc_dumpregs("On reset HSE"); + modifyreg32(STM32_RCC_XXX, RCC_XXX_RTCSEL_MASK, RCC_XXX_RTCSEL_HSE); + +#elif defined(CONFIG_STM32_RTC_LSICLOCK) + /* Use the LSI clock as the input to the RTC block */ + + rtc_dumpregs("On reset LSI"); + modifyreg32(STM32_RCC_XXX, RCC_XXX_RTCSEL_MASK, RCC_XXX_RTCSEL_LSI); + +#elif defined(CONFIG_STM32_RTC_LSECLOCK) + /* Use the LSE clock as the input to the RTC block */ + + rtc_dumpregs("On reset LSE"); + modifyreg32(STM32_RCC_XXX, RCC_XXX_RTCSEL_MASK, RCC_XXX_RTCSEL_LSE); + +#endif + /* Enable the RTC Clock by setting the RTCEN bit in the RCC register */ + + modifyreg32(STM32_RCC_XXX, 0, RCC_XXX_RTCEN); + } + else /* The RTC is already in use: check if the clock source is changed */ + { +#if defined(CONFIG_STM32_RTC_HSECLOCK) || defined(CONFIG_STM32_RTC_LSICLOCK) || \ + defined(CONFIG_STM32_RTC_LSECLOCK) + + uint32_t clksrc = getreg32(STM32_RCC_XXX); + + rtc_dumpregs("On reset warm"); + +#if defined(CONFIG_STM32_RTC_HSECLOCK) + if ((clksrc & RCC_XXX_RTCSEL_MASK) != RCC_XXX_RTCSEL_HSE) +#elif defined(CONFIG_STM32_RTC_LSICLOCK) + if ((clksrc & RCC_XXX_RTCSEL_MASK) != RCC_XXX_RTCSEL_LSI) +#elif defined(CONFIG_STM32_RTC_LSECLOCK) + if ((clksrc & RCC_XXX_RTCSEL_MASK) != RCC_XXX_RTCSEL_LSE) +#endif +#endif + { + tr_bkp = getreg32(STM32_RTC_TR); + dr_bkp = getreg32(STM32_RTC_DR); + modifyreg32(STM32_RCC_XXX, 0, RCC_XXX_YYYRST); + modifyreg32(STM32_RCC_XXX, RCC_XXX_YYYRST, 0); + +#if defined(CONFIG_STM32_RTC_HSECLOCK) + /* Change to the new clock as the input to the RTC block */ + + modifyreg32(STM32_RCC_XXX, RCC_XXX_RTCSEL_MASK, + RCC_XXX_RTCSEL_HSE); + +#elif defined(CONFIG_STM32_RTC_LSICLOCK) + modifyreg32(STM32_RCC_XXX, RCC_XXX_RTCSEL_MASK, + RCC_XXX_RTCSEL_LSI); + +#elif defined(CONFIG_STM32_RTC_LSECLOCK) + modifyreg32(STM32_RCC_XXX, RCC_XXX_RTCSEL_MASK, + RCC_XXX_RTCSEL_LSE); +#endif + + putreg32(tr_bkp, STM32_RTC_TR); + putreg32(dr_bkp, STM32_RTC_DR); + + /* Remember that the RTC is initialized */ + + putreg32(RTC_MAGIC, RTC_MAGIC_REG); + + /* Enable the RTC Clock by setting the RTCEN bit in the RCC + * register + */ + + modifyreg32(STM32_RCC_XXX, 0, RCC_XXX_RTCEN); + } + } + + stm32_pwr_enablebkp(false); + + /* Loop, attempting to initialize/resume the RTC. This loop is necessary + * because it seems that occasionally it takes longer to initialize the RTC + * (the actual failure is in rtc_synchwait()). + */ + + do + { + /* Wait for the RTC Time and Date registers to be synchronized with RTC + * APB clock. + */ + + ret = rtc_synchwait(); + + /* Check that rtc_syncwait() returned successfully */ + + switch (ret) + { + case OK: + { + rtcinfo("rtc_syncwait() okay\n"); + break; + } + + default: + { + rtcerr("ERROR: rtc_syncwait() failed (%d)\n", ret); + break; + } + } + } + while (ret != OK && ++nretry < maxretry); + + /* Check if the one-time initialization of the RTC has already been + * performed. We can determine this by checking if the magic number + * has been written to the back-up date register DR0. + */ + + if (regval != RTC_MAGIC && regval != RTC_MAGIC_TIME_SET) + { + rtcinfo("Do setup\n"); + + /* Perform the one-time setup of the LSE clocking to the RTC */ + + ret = rtc_setup(); + + /* Enable write access to the backup domain (RTC registers, RTC + * backup data registers and backup SRAM). + */ + + stm32_pwr_enablebkp(true); + + /* Remember that the RTC is initialized */ + + putreg32(RTC_MAGIC, RTC_MAGIC_REG); + + /* Disable write access to the backup domain (RTC registers, RTC + * backup data registers and backup SRAM). + */ + + stm32_pwr_enablebkp(false); + } + else + { + rtcinfo("Do resume\n"); + + /* RTC already set-up, just resume normal operation */ + + rtc_resume(); + rtc_dumpregs("Did resume"); + } + + if (ret != OK && nretry > 0) + { + rtcinfo("setup/resume ran %d times and failed with %d\n", + nretry, ret); + return -ETIMEDOUT; + } + + rtc_dumpregs("After Initialization"); + + g_rtc_enabled = true; + return OK; +} + +/**************************************************************************** + * Name: stm32_rtc_irqinitialize + * + * Description: + * Initialize IRQs for RTC, not possible during up_rtc_initialize because + * up_irqinitialize is called later. + * + * Input Parameters: + * None + * + * Returned Value: + * Zero (OK) on success; a negated errno on failure + * + ****************************************************************************/ + +int stm32_rtc_irqinitialize(void) +{ + /* Nothing to do */ + + return OK; +} + +/**************************************************************************** + * Name: stm32_rtc_getdatetime_with_subseconds + * + * Description: + * Get the current date and time from the date/time RTC. This interface + * is only supported by the date/time RTC hardware implementation. + * It is used to replace the system timer. It is only used by the RTOS + * during initialization to set up the system time when CONFIG_RTC and + * CONFIG_RTC_DATETIME are selected (and CONFIG_RTC_HIRES is not). + * + * NOTE: Some date/time RTC hardware is capability of sub-second accuracy. + * That sub-second accuracy is returned through 'nsec'. + * + * Input Parameters: + * tp - The location to return the high resolution time value. + * nsec - The location to return the subsecond time value. + * + * Returned Value: + * Zero (OK) on success; a negated errno on failure + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_HAVE_RTC_SUBSECONDS +int stm32_rtc_getdatetime_with_subseconds(struct tm *tp, long *nsec) +#else +int up_rtc_getdatetime(struct tm *tp) +#endif +{ +#ifdef CONFIG_STM32_HAVE_RTC_SUBSECONDS + uint32_t ssr; +#endif + uint32_t dr; + uint32_t tr; + uint32_t tmp; + + /* Sample the data time registers. There is a race condition here... If + * we sample the time just before midnight on December 31, the date could + * be wrong because the day rolled over while were sampling. Thus loop for + * checking overflow here is needed. There is a race condition with + * subseconds too. If we sample TR register just before second rolling + * and subseconds are read at wrong second, we get wrong time. + */ + + do + { + dr = getreg32(STM32_RTC_DR); + tr = getreg32(STM32_RTC_TR); +#ifdef CONFIG_STM32_HAVE_RTC_SUBSECONDS + ssr = getreg32(STM32_RTC_SSR); + tmp = getreg32(STM32_RTC_TR); + if (tmp != tr) + { + continue; + } +#endif + + tmp = getreg32(STM32_RTC_DR); + if (tmp == dr) + { + break; + } + } + while (1); + + rtc_dumpregs("Reading Time"); + + /* Convert the RTC time to fields in struct tm format. All of the STM32 + * ranges of values correspond between struct tm and the time register. + */ + + tmp = (tr & (RTC_TR_SU_MASK | RTC_TR_ST_MASK)) >> RTC_TR_SU_SHIFT; + tp->tm_sec = rtc_bcd2bin(tmp); + + tmp = (tr & (RTC_TR_MNU_MASK | RTC_TR_MNT_MASK)) >> RTC_TR_MNU_SHIFT; + tp->tm_min = rtc_bcd2bin(tmp); + + tmp = (tr & (RTC_TR_HU_MASK | RTC_TR_HT_MASK)) >> RTC_TR_HU_SHIFT; + tp->tm_hour = rtc_bcd2bin(tmp); + + /* Now convert the RTC date to fields in struct tm format: + * Days: 1-31 match in both cases. + * Month: STM32 is 1-12, struct tm is 0-11. + * Years: STM32 is 00-99, struct tm is years since 1900. + * WeekDay: STM32 is 1 = Mon - 7 = Sun + * + * Issue: I am not sure what the STM32 years mean. Are these the + * years 2000-2099? I'll assume so. + */ + + tmp = (dr & (RTC_DR_DU_MASK | RTC_DR_DT_MASK)) >> RTC_DR_DU_SHIFT; + tp->tm_mday = rtc_bcd2bin(tmp); + + tmp = (dr & (RTC_DR_MU_MASK | RTC_DR_MT)) >> RTC_DR_MU_SHIFT; + tp->tm_mon = rtc_bcd2bin(tmp) - 1; + + tmp = (dr & (RTC_DR_YU_MASK | RTC_DR_YT_MASK)) >> RTC_DR_YU_SHIFT; + tp->tm_year = rtc_bcd2bin(tmp) + 100; + + tmp = (dr & RTC_DR_WDU_MASK) >> RTC_DR_WDU_SHIFT; + tp->tm_wday = tmp % 7; + tp->tm_yday = tp->tm_mday - 1 + + clock_daysbeforemonth(tp->tm_mon, + clock_isleapyear(tp->tm_year + 1900)); + tp->tm_isdst = 0; + +#ifdef CONFIG_STM32_HAVE_RTC_SUBSECONDS + /* Return RTC sub-seconds if no configured and if a non-NULL value + * of nsec has been provided to receive the sub-second value. + */ + + if (nsec) + { + uint32_t prediv_s; + uint32_t usecs; + + prediv_s = getreg32(STM32_RTC_PRER) & RTC_PRER_PREDIV_S_MASK; + prediv_s >>= RTC_PRER_PREDIV_S_SHIFT; + + ssr &= RTC_SSR_MASK; + + /* Maximum prediv_s is 0x7fff, thus we can multiply by 100000 and + * still fit 32-bit unsigned integer. + */ + + usecs = (((prediv_s - ssr) * 100000) / (prediv_s + 1)) * 10; + *nsec = usecs * 1000; + } +#endif /* CONFIG_STM32_HAVE_RTC_SUBSECONDS */ + + rtc_dumptime((const struct tm *)tp, "Returning"); + return OK; +} + +/**************************************************************************** + * Name: up_rtc_getdatetime + * + * Description: + * Get the current date and time from the date/time RTC. This interface + * is only supported by the date/time RTC hardware implementation. + * It is used to replace the system timer. It is only used by the RTOS + * during initialization to set up the system time when CONFIG_RTC and + * CONFIG_RTC_DATETIME are selected (and CONFIG_RTC_HIRES is not). + * + * NOTE: Some date/time RTC hardware is capability of sub-second accuracy. + * That sub-second accuracy is lost in this interface. However, since the + * system time is reinitialized on each power-up/reset, there will be no + * timing inaccuracy in the long run. + * + * Input Parameters: + * tp - The location to return the high resolution time value. + * + * Returned Value: + * Zero (OK) on success; a negated errno on failure + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_HAVE_RTC_SUBSECONDS +int up_rtc_getdatetime(struct tm *tp) +{ + return stm32_rtc_getdatetime_with_subseconds(tp, NULL); +} +#endif + +/**************************************************************************** + * Name: stm32_rtc_setdatetime + * + * Description: + * Set the RTC to the provided time. RTC implementations which provide + * up_rtc_getdatetime() (CONFIG_RTC_DATETIME is selected) should provide + * this function. + * + * Input Parameters: + * tp - the time to use + * + * Returned Value: + * Zero (OK) on success; a negated errno on failure + * + ****************************************************************************/ + +int stm32_rtc_setdatetime(const struct tm *tp) +{ + uint32_t tr; + uint32_t dr; + int ret; + + rtc_dumptime(tp, "Setting time"); + + /* Then write the broken out values to the RTC */ + + /* Convert the struct tm format to RTC time register fields. + * All of the ranges of values correspond between struct tm and the time + * register. + */ + + tr = (rtc_bin2bcd(tp->tm_sec) << RTC_TR_SU_SHIFT) | + (rtc_bin2bcd(tp->tm_min) << RTC_TR_MNU_SHIFT) | + (rtc_bin2bcd(tp->tm_hour) << RTC_TR_HU_SHIFT); + + /* Now convert the fields in struct tm format to the RTC date register + * fields: + * + * Days: 1-31 match in both cases. + * Month: STM32 is 1-12, struct tm is 0-11. + * Years: STM32 is 00-99, struct tm is years since 1900. + * WeekDay: STM32 is 1 = Mon - 7 = Sun + * + * Issue: I am not sure what the STM32 years mean. Are these the + * years 2000-2099? I'll assume so. + */ + + dr = (rtc_bin2bcd(tp->tm_mday) << RTC_DR_DU_SHIFT) | + ((rtc_bin2bcd(tp->tm_mon + 1)) << RTC_DR_MU_SHIFT) | + ((tp->tm_wday == 0 ? 7 : (tp->tm_wday & 7)) << RTC_DR_WDU_SHIFT) | + ((rtc_bin2bcd(tp->tm_year - 100)) << RTC_DR_YU_SHIFT); + + dr &= ~RTC_DR_RESERVED_BITS; + + /* Disable the write protection for RTC registers */ + + rtc_wprunlock(); + + /* Set Initialization mode */ + + ret = rtc_enterinit(); + if (ret == OK) + { + /* Set the RTC TR and DR registers */ + + putreg32(tr, STM32_RTC_TR); + putreg32(dr, STM32_RTC_DR); + + /* Exit Initialization mode and wait for the RTC Time and Date + * registers to be synchronized with RTC APB clock. + */ + + rtc_exitinit(); + ret = rtc_synchwait(); + } + + /* Remember that the RTC is initialized and had its time set. */ + + if (getreg32(RTC_MAGIC_REG) != RTC_MAGIC_TIME_SET) + { + stm32_pwr_enablebkp(true); + putreg32(RTC_MAGIC_TIME_SET, RTC_MAGIC_REG); + stm32_pwr_enablebkp(false); + } + + /* Re-enable the write protection for RTC registers */ + + rtc_wprlock(); + rtc_dumpregs("New time setting"); + return ret; +} + +/**************************************************************************** + * Name: up_rtc_settime + * + * Description: + * Set the RTC to the provided time. All RTC implementations must be able + * to set their time based on a standard timespec. + * + * Input Parameters: + * tp - the time to use + * + * Returned Value: + * Zero (OK) on success; a negated errno on failure + * + ****************************************************************************/ + +int up_rtc_settime(const struct timespec *tp) +{ + struct tm newtime; + + /* Break out the time values (not that the time is set only to units of + * seconds) + */ + + gmtime_r(&tp->tv_sec, &newtime); + return stm32_rtc_setdatetime(&newtime); +} + +/**************************************************************************** + * Name: stm32_rtc_setalarm + * + * Description: + * Set an alarm to an absolute time using associated hardware. + * + * Input Parameters: + * alminfo - Information about the alarm configuration. + * + * Returned Value: + * Zero (OK) on success; a negated errno on failure + * + ****************************************************************************/ + +#ifdef CONFIG_RTC_ALARM +int stm32_rtc_setalarm(struct alm_setalarm_s *alminfo) +{ + struct alm_cbinfo_s *cbinfo; + rtc_alarmreg_t alarmreg; + int ret = -EINVAL; + + DEBUGASSERT(alminfo != NULL); + DEBUGASSERT(RTC_ALARM_LAST > alminfo->as_id); + + /* Make sure the alarm interrupt is enabled at the NVIC */ + + rtc_enable_alarm(); + + /* REVISIT: Should test that the time is in the future */ + + rtc_dumptime(&alminfo->as_time, "New alarm time"); + + /* Break out the values to the HW alarm register format. The values in + * all STM32 fields match the fields of struct tm in this case. Notice + * that the alarm is limited to one month. + */ + + alarmreg = (rtc_bin2bcd(alminfo->as_time.tm_sec) << RTC_ALRMR_SU_SHIFT) | + (rtc_bin2bcd(alminfo->as_time.tm_min) << RTC_ALRMR_MNU_SHIFT) | + (rtc_bin2bcd(alminfo->as_time.tm_hour) << RTC_ALRMR_HU_SHIFT) | + (rtc_bin2bcd(alminfo->as_time.tm_mday) << RTC_ALRMR_DU_SHIFT); + + /* Set the alarm in hardware and enable interrupts from the RTC */ + + switch (alminfo->as_id) + { + case RTC_ALARMA: + { + cbinfo = &g_alarmcb[RTC_ALARMA]; + cbinfo->ac_cb = alminfo->as_cb; + cbinfo->ac_arg = alminfo->as_arg; + + ret = rtchw_set_alrmar(alarmreg | RTC_ALRMR_ENABLE); + if (ret < 0) + { + cbinfo->ac_cb = NULL; + cbinfo->ac_arg = NULL; + } + + rtc_dumpregs("Set AlarmA"); + } + break; + +#if CONFIG_RTC_NALARMS > 1 + case RTC_ALARMB: + { + cbinfo = &g_alarmcb[RTC_ALARMB]; + cbinfo->ac_cb = alminfo->as_cb; + cbinfo->ac_arg = alminfo->as_arg; + + ret = rtchw_set_alrmbr(alarmreg | RTC_ALRMR_ENABLE); + if (ret < 0) + { + cbinfo->ac_cb = NULL; + cbinfo->ac_arg = NULL; + } + + rtc_dumpregs("Set AlarmB"); + } + break; +#endif + + default: + rtcerr("ERROR: Invalid ALARM%d\n", alminfo->as_id); + break; + } + + return ret; +} +#endif + +/**************************************************************************** + * Name: stm32_rtc_cancelalarm + * + * Description: + * Cancel an alarm. + * + * Input Parameters: + * alarmid - Identifies the alarm to be cancelled + * + * Returned Value: + * Zero (OK) on success; a negated errno on failure + * + ****************************************************************************/ + +#ifdef CONFIG_RTC_ALARM +int stm32_rtc_cancelalarm(enum alm_id_e alarmid) +{ + int ret = -EINVAL; + + DEBUGASSERT(RTC_ALARM_LAST > alarmid); + + /* Cancel the alarm in hardware and disable interrupts */ + + switch (alarmid) + { + case RTC_ALARMA: + { + /* Cancel the global callback function */ + + g_alarmcb[alarmid].ac_cb = NULL; + g_alarmcb[alarmid].ac_arg = NULL; + + /* Disable the write protection for RTC registers */ + + rtc_wprunlock(); + + /* Disable RTC alarm and interrupt */ + + modifyreg32(STM32_RTC_CR, (RTC_CR_ALRAE | RTC_CR_ALRAIE), 0); + + ret = rtchw_check_alrawf(); + if (ret < 0) + { + goto errout_with_wprunlock; + } + + /* Unset the alarm */ + + putreg32(-1, STM32_RTC_ALRMAR); + rtc_wprlock(); + ret = OK; + } + break; + +#if CONFIG_RTC_NALARMS > 1 + case RTC_ALARMB: + { + /* Cancel the global callback function */ + + g_alarmcb[alarmid].ac_cb = NULL; + g_alarmcb[alarmid].ac_arg = NULL; + + /* Disable the write protection for RTC registers */ + + rtc_wprunlock(); + + /* Disable RTC alarm and interrupt */ + + modifyreg32(STM32_RTC_CR, (RTC_CR_ALRBE | RTC_CR_ALRBIE), 0); + + ret = rtchw_check_alrbwf(); + if (ret < 0) + { + goto errout_with_wprunlock; + } + + /* Unset the alarm */ + + putreg32(-1, STM32_RTC_ALRMBR); + rtc_wprlock(); + ret = OK; + } + break; +#endif + + default: + rtcerr("ERROR: Invalid ALARM%d\n", alarmid); + break; + } + + return ret; + +errout_with_wprunlock: + rtc_wprlock(); + return ret; +} +#endif + +/**************************************************************************** + * Name: stm32_rtc_rdalarm + * + * Description: + * Query an alarm configured in hardware. + * + * Input Parameters: + * alminfo - Information about the alarm configuration. + * + * Returned Value: + * Zero (OK) on success; a negated errno on failure + * + ****************************************************************************/ + +#ifdef CONFIG_RTC_ALARM +int stm32_rtc_rdalarm(struct alm_rdalarm_s *alminfo) +{ + rtc_alarmreg_t alarmreg; + int ret = -EINVAL; + + DEBUGASSERT(alminfo != NULL); + DEBUGASSERT(RTC_ALARM_LAST > alminfo->ar_id); + + switch (alminfo->ar_id) + { + case RTC_ALARMA: + { + alarmreg = STM32_RTC_ALRMAR; + ret = stm32_rtc_getalarmdatetime(alarmreg, + (struct tm *)alminfo->ar_time); + } + break; + +#if CONFIG_RTC_NALARMS > 1 + case RTC_ALARMB: + { + alarmreg = STM32_RTC_ALRMBR; + ret = stm32_rtc_getalarmdatetime(alarmreg, + (struct tm *)alminfo->ar_time); + } + break; +#endif + + default: + rtcerr("ERROR: Invalid ALARM%d\n", alminfo->ar_id); + break; + } + + return ret; +} +#endif + +#endif /* CONFIG_STM32_RTC */ diff --git a/arch/arm/src/common/stm32/stm32_rtcc_m3m4_l1.c b/arch/arm/src/common/stm32/stm32_rtcc_m3m4_l1.c new file mode 100644 index 0000000000000..06d729c437bc9 --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_rtcc_m3m4_l1.c @@ -0,0 +1,1883 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_rtcc_m3m4_l1.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include "chip.h" + +#include +#include +#include +#include +#include + +#include +#include +#include + +#include + +#include "arm_internal.h" +#include "stm32_rcc.h" +#include "stm32_pwr.h" +#include "stm32_exti.h" +#include "stm32_rtc.h" + +#ifdef CONFIG_STM32_RTC + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* This RTC implementation supports + * - date/time RTC hardware + * - extended functions Alarm A and B + * */ + +#ifndef CONFIG_RTC_DATETIME +# error "CONFIG_RTC_DATETIME must be set to use this driver" +#endif + +#ifdef CONFIG_RTC_HIRES +# error "CONFIG_RTC_HIRES must NOT be set with this driver" +#endif + +#ifndef CONFIG_STM32_PWR +# error "CONFIG_STM32_PWR must selected to use this driver" +#endif + +#if defined(CONFIG_STM32_RTC_HSECLOCK) +# warning "RTC with HSE clock not yet tested on STM32L15XXX" +#elif defined(CONFIG_STM32_RTC_LSICLOCK) +# warning "RTC with LSI clock not yet tested on STM32L15XXX" +#endif + +#if !defined(CONFIG_STM32_RTC_MAGIC) +# define CONFIG_STM32_RTC_MAGIC (0xfacefeed) +#endif + +#if !defined(CONFIG_STM32_RTC_MAGIC_TIME_SET) +# define CONFIG_STM32_RTC_MAGIC_TIME_SET (0xf00dface) +#endif + +#if !defined(CONFIG_STM32_RTC_MAGIC_REG) +# define CONFIG_STM32_RTC_MAGIC_REG (0) +#endif + +#define RTC_MAGIC CONFIG_STM32_RTC_MAGIC +#define RTC_MAGIC_TIME_SET CONFIG_STM32_RTC_MAGIC_TIME_SET +#define RTC_MAGIC_REG STM32_RTC_BKR(CONFIG_STM32_RTC_MAGIC_REG) + +/* Constants ****************************************************************/ + +#define SYNCHRO_TIMEOUT (0x00020000) +#define INITMODE_TIMEOUT (0x00010000) + +#define RTC_ALRMR_ENABLE 0 + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +#ifdef CONFIG_RTC_ALARM +typedef unsigned int rtc_alarmreg_t; + +struct alm_cbinfo_s +{ + volatile alm_callback_t ac_cb; /* Client callback function */ + volatile void *ac_arg; /* Argument to pass with the callback function */ +}; +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#ifdef CONFIG_RTC_ALARM +/* Callback to use when an EXTI is activated */ + +static struct alm_cbinfo_s g_alarmcb[RTC_ALARM_LAST]; +static bool g_alarm_enabled; /* True: Alarm interrupts are enabled */ +#endif + +#ifdef CONFIG_RTC_PERIODIC +static wakeupcb_t g_wakeupcb; +static bool g_wakeup_enabled; /* True: Wakeup interrupts are enabled */ +#endif + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/* g_rtc_enabled is set true after the RTC has successfully initialized */ + +volatile bool g_rtc_enabled = false; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +#ifdef CONFIG_RTC_ALARM +static int rtchw_check_alrawf(void); +static int rtchw_set_alrmar(rtc_alarmreg_t alarmreg); +#if CONFIG_RTC_NALARMS > 1 +static int rtchw_check_alrbwf(void); +static int rtchw_set_alrmbr(rtc_alarmreg_t alarmreg); +#endif +static inline void rtc_enable_alarm(void); +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: rtc_dumpregs + ****************************************************************************/ + +#ifdef CONFIG_DEBUG_RTC_INFO +static void rtc_dumpregs(const char *msg) +{ + rtcinfo("%s:\n", msg); + rtcinfo(" TR: %08" PRIx32 "\n", getreg32(STM32_RTC_TR)); + rtcinfo(" DR: %08" PRIx32 "\n", getreg32(STM32_RTC_DR)); + rtcinfo(" CR: %08" PRIx32 "\n", getreg32(STM32_RTC_CR)); + rtcinfo(" ISR: %08" PRIx32 "\n", getreg32(STM32_RTC_ISR)); + rtcinfo(" PRER: %08" PRIx32 "\n", getreg32(STM32_RTC_PRER)); + rtcinfo(" WUTR: %08" PRIx32 "\n", getreg32(STM32_RTC_WUTR)); + rtcinfo(" CALIBR: %08" PRIx32 "\n", getreg32(STM32_RTC_CALIBR)); + rtcinfo(" ALRMAR: %08" PRIx32 "\n", getreg32(STM32_RTC_ALRMAR)); + rtcinfo(" ALRMBR: %08" PRIx32 "\n", getreg32(STM32_RTC_ALRMBR)); + rtcinfo(" SHIFTR: %08" PRIx32 "\n", getreg32(STM32_RTC_SHIFTR)); + rtcinfo(" TSTR: %08" PRIx32 "\n", getreg32(STM32_RTC_TSTR)); + rtcinfo(" TSDR: %08" PRIx32 "\n", getreg32(STM32_RTC_TSDR)); + rtcinfo(" TSSSR: %08" PRIx32 "\n", getreg32(STM32_RTC_TSSSR)); + rtcinfo(" CALR: %08" PRIx32 "\n", getreg32(STM32_RTC_CALR)); + rtcinfo(" TAFCR: %08" PRIx32 "\n", getreg32(STM32_RTC_TAFCR)); + rtcinfo("ALRMASSR: %08" PRIx32 "\n", getreg32(STM32_RTC_ALRMASSR)); + rtcinfo("ALRMBSSR: %08" PRIx32 "\n", getreg32(STM32_RTC_ALRMBSSR)); + rtcinfo("MAGICREG: %08" PRIx32 "\n", getreg32(RTC_MAGIC_REG)); +} +#else +# define rtc_dumpregs(msg) +#endif + +/**************************************************************************** + * Name: rtc_dumptime + ****************************************************************************/ + +#ifdef CONFIG_DEBUG_RTC_INFO +static void rtc_dumptime(const struct tm *tp, const char *msg) +{ + rtcinfo("%s:\n", msg); +#if 0 + rtcinfo(" tm_sec: %08x\n", tp->tm_sec); + rtcinfo(" tm_min: %08x\n", tp->tm_min); + rtcinfo(" tm_hour: %08x\n", tp->tm_hour); + rtcinfo(" tm_mday: %08x\n", tp->tm_mday); + rtcinfo(" tm_mon: %08x\n", tp->tm_mon); + rtcinfo(" tm_year: %08x\n", tp->tm_year); +#else + rtcinfo(" tm: %04d-%02d-%02d %02d:%02d:%02d\n", + tp->tm_year + 1900, tp->tm_mon + 1, tp->tm_mday, + tp->tm_hour, tp->tm_min, tp->tm_sec); +#endif +} +#else +# define rtc_dumptime(tp, msg) +#endif + +/**************************************************************************** + * Name: rtc_wprunlock + * + * Description: + * Disable RTC write protection + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void rtc_wprunlock(void) +{ + /* Enable write access to the backup domain. */ + + stm32_pwr_enablebkp(true); + + /* The following steps are required to unlock the write protection on all + * the RTC registers (except for RTC_ISR[13:8], RTC_TAFCR, and RTC_BKPxR). + * + * 1. Write 0xCA into the RTC_WPR register. + * 2. Write 0x53 into the RTC_WPR register. + * + * Writing a wrong key re-activates the write protection. + */ + + putreg32(0xca, STM32_RTC_WPR); + putreg32(0x53, STM32_RTC_WPR); +} + +/**************************************************************************** + * Name: rtc_wprlock + * + * Description: + * Enable RTC write protection + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +static inline void rtc_wprlock(void) +{ + /* Writing any wrong key re-activates the write protection. */ + + putreg32(0xff, STM32_RTC_WPR); + + /* Disable write access to the backup domain. */ + + stm32_pwr_enablebkp(false); +} + +/**************************************************************************** + * Name: rtc_synchwait + * + * Description: + * Waits until the RTC Time and Date registers (RTC_TR and RTC_DR) are + * synchronized with RTC APB clock. + * + * Input Parameters: + * None + * + * Returned Value: + * Zero (OK) on success; a negated errno on failure + * + ****************************************************************************/ + +static int rtc_synchwait(void) +{ + volatile uint32_t timeout; + uint32_t regval; + int ret; + + /* Clear Registers synchronization flag (RSF) */ + + regval = getreg32(STM32_RTC_ISR); + regval &= ~RTC_ISR_RSF; + putreg32(regval, STM32_RTC_ISR); + + /* Now wait the registers to become synchronised */ + + ret = -ETIMEDOUT; + for (timeout = 0; timeout < SYNCHRO_TIMEOUT; timeout++) + { + regval = getreg32(STM32_RTC_ISR); + if ((regval & RTC_ISR_RSF) != 0) + { + /* Synchronized */ + + ret = OK; + break; + } + } + + return ret; +} + +/**************************************************************************** + * Name: rtc_enterinit + * + * Description: + * Enter RTC initialization mode. + * + * Input Parameters: + * None + * + * Returned Value: + * Zero (OK) on success; a negated errno on failure + * + ****************************************************************************/ + +static int rtc_enterinit(void) +{ + volatile uint32_t timeout; + uint32_t regval; + int ret; + + /* Check if the Initialization mode is already set */ + + regval = getreg32(STM32_RTC_ISR); + + ret = OK; + if ((regval & RTC_ISR_INITF) == 0) + { + /* Set the Initialization mode */ + + putreg32(RTC_ISR_INIT, STM32_RTC_ISR); + + /* Wait until the RTC is in the INIT state (or a timeout occurs) */ + + ret = -ETIMEDOUT; + for (timeout = 0; timeout < INITMODE_TIMEOUT; timeout++) + { + regval = getreg32(STM32_RTC_ISR); + if ((regval & RTC_ISR_INITF) != 0) + { + ret = OK; + break; + } + } + } + + return ret; +} + +/**************************************************************************** + * Name: rtc_exitinit + * + * Description: + * Exit RTC initialization mode. + * + * Input Parameters: + * None + * + * Returned Value: + * Zero (OK) on success; a negated errno on failure + * + ****************************************************************************/ + +static void rtc_exitinit(void) +{ + uint32_t regval; + + regval = getreg32(STM32_RTC_ISR); + regval &= ~(RTC_ISR_INIT); + putreg32(regval, STM32_RTC_ISR); +} + +/**************************************************************************** + * Name: rtc_bin2bcd + * + * Description: + * Converts a 2 digit binary to BCD format + * + * Input Parameters: + * value - The byte to be converted. + * + * Returned Value: + * The value in BCD representation + * + ****************************************************************************/ + +static uint32_t rtc_bin2bcd(int value) +{ + uint32_t msbcd = 0; + + while (value >= 10) + { + msbcd++; + value -= 10; + } + + return (msbcd << 4) | value; +} + +/**************************************************************************** + * Name: rtc_bin2bcd + * + * Description: + * Convert from 2 digit BCD to binary. + * + * Input Parameters: + * value - The BCD value to be converted. + * + * Returned Value: + * The value in binary representation + * + ****************************************************************************/ + +static int rtc_bcd2bin(uint32_t value) +{ + uint32_t tens = (value >> 4) * 10; + return (int)(tens + (value & 0x0f)); +} + +/**************************************************************************** + * Name: rtc_resume + * + * Description: + * Called when the RTC was already initialized on a previous power cycle. + * This just brings the RTC back into full operation. + * + * Input Parameters: + * None + * + * Returned Value: + * Zero (OK) on success; a negated errno on failure + * + ****************************************************************************/ + +static void rtc_resume(void) +{ +#ifdef CONFIG_RTC_ALARM + uint32_t regval; + + /* Clear the RTC alarm flags */ + + regval = getreg32(STM32_RTC_ISR); + regval &= ~(RTC_ISR_ALRAF | RTC_ISR_ALRBF); + putreg32(regval, STM32_RTC_ISR); + + /* Clear the EXTI Line 18 Pending bit (Connected internally to RTC Alarm) */ + + putreg32(EXTI_RTC_ALARM, STM32_EXTI_PR); +#endif +} + +/**************************************************************************** + * Name: stm32_rtc_alarm_handler + * + * Description: + * RTC ALARM interrupt service routine through the EXTI line + * + * Input Parameters: + * irq - The IRQ number that generated the interrupt + * context - Architecture specific register save information. + * + * Returned Value: + * Zero (OK) on success; A negated errno value on failure. + * + ****************************************************************************/ + +#ifdef CONFIG_RTC_ALARM +static int stm32_rtc_alarm_handler(int irq, void *context, + void *rtc_handler_arg) +{ + struct alm_cbinfo_s *cbinfo; + alm_callback_t cb; + void *arg; + uint32_t isr; + uint32_t cr; + int ret = OK; + + /* Enable write access to the backup domain (RTC registers, RTC + * backup data registers and backup SRAM). + */ + + stm32_pwr_enablebkp(true); + + /* Check for EXTI from Alarm A or B and handle according */ + + cr = getreg32(STM32_RTC_CR); + if ((cr & RTC_CR_ALRAIE) != 0) + { + isr = getreg32(STM32_RTC_ISR); + if ((isr & RTC_ISR_ALRAF) != 0) + { + cbinfo = &g_alarmcb[RTC_ALARMA]; + if (cbinfo->ac_cb != NULL) + { + /* Alarm A callback */ + + cb = cbinfo->ac_cb; + arg = (void *)cbinfo->ac_arg; + + cbinfo->ac_cb = NULL; + cbinfo->ac_arg = NULL; + + cb(arg, RTC_ALARMA); + } + + /* note, bits 8-13 do /not/ require the write enable procedure */ + + isr = getreg32(STM32_RTC_ISR); + isr &= ~RTC_ISR_ALRAF; + putreg32(isr, STM32_RTC_ISR); + } + } + +#if CONFIG_RTC_NALARMS > 1 + cr = getreg32(STM32_RTC_CR); + if ((cr & RTC_CR_ALRBIE) != 0) + { + isr = getreg32(STM32_RTC_ISR); + if ((isr & RTC_ISR_ALRBF) != 0) + { + cbinfo = &g_alarmcb[RTC_ALARMB]; + if (cbinfo->ac_cb != NULL) + { + /* Alarm B callback */ + + cb = cbinfo->ac_cb; + arg = (void *)cbinfo->ac_arg; + + cbinfo->ac_cb = NULL; + cbinfo->ac_arg = NULL; + + cb(arg, RTC_ALARMB); + } + + /* note, bits 8-13 do /not/ require the write enable procedure */ + + isr = getreg32(STM32_RTC_ISR); + isr &= ~RTC_ISR_ALRBF; + putreg32(isr, STM32_RTC_ISR); + } + } +#endif + + /* Disable write access to the backup domain (RTC registers, RTC backup + * data registers and backup SRAM). + */ + + stm32_pwr_enablebkp(false); + + return ret; +} +#endif + +/**************************************************************************** + * Name: rtchw_check_alrXwf X= a or B + * + * Description: + * Check registers + * + * Input Parameters: + * None + * + * Returned Value: + * Zero (OK) on success; a negated errno on failure + * + ****************************************************************************/ + +#ifdef CONFIG_RTC_ALARM +static int rtchw_check_alrawf(void) +{ + volatile uint32_t timeout; + uint32_t regval; + int ret = -ETIMEDOUT; + + /* Check RTC_ISR ALRAWF for access to alarm register, + * Can take 2 RTCCLK cycles or timeout + * CubeMX use GetTick. + */ + + for (timeout = 0; timeout < INITMODE_TIMEOUT; timeout++) + { + regval = getreg32(STM32_RTC_ISR); + if ((regval & RTC_ISR_ALRAWF) != 0) + { + ret = OK; + break; + } + } + + return ret; +} +#endif + +#if defined(CONFIG_RTC_ALARM) && CONFIG_RTC_NALARMS > 1 +static int rtchw_check_alrbwf(void) +{ + volatile uint32_t timeout; + uint32_t regval; + int ret = -ETIMEDOUT; + + /* Check RTC_ISR ALRBWF for access to alarm register, + * can take 2 RTCCLK cycles or timeout + * CubeMX use GetTick. + */ + + for (timeout = 0; timeout < INITMODE_TIMEOUT; timeout++) + { + regval = getreg32(STM32_RTC_ISR); + if ((regval & RTC_ISR_ALRBWF) != 0) + { + ret = OK; + break; + } + } + + return ret; +} +#endif + +/**************************************************************************** + * Name: stm32_rtchw_set_alrmXr X is a or b + * + * Description: + * Set the alarm (A or B) hardware registers, using the required hardware + * access protocol + * + * Input Parameters: + * alarmreg - the register + * + * Returned Value: + * Zero (OK) on success; a negated errno on failure + * + ****************************************************************************/ + +#ifdef CONFIG_RTC_ALARM +static int rtchw_set_alrmar(rtc_alarmreg_t alarmreg) +{ + int isr; + int ret = -EBUSY; + + /* Disable the write protection for RTC registers */ + + rtc_wprunlock(); + + /* Disable RTC alarm A & Interrupt A */ + + modifyreg32(STM32_RTC_CR, (RTC_CR_ALRAE | RTC_CR_ALRAIE), 0); + + /* Ensure Alarm A flag reset; this is edge triggered */ + + isr = getreg32(STM32_RTC_ISR) & ~RTC_ISR_ALRAF; + putreg32(isr, STM32_RTC_ISR); + + /* Wait for Alarm A to be writable */ + + ret = rtchw_check_alrawf(); + if (ret != OK) + { + goto errout_with_wprunlock; + } + + /* Set the RTC Alarm A register */ + + putreg32(alarmreg, STM32_RTC_ALRMAR); + putreg32(0, STM32_RTC_ALRMASSR); + rtcinfo(" ALRMAR: %08" PRIx32 "\n", getreg32(STM32_RTC_ALRMAR)); + + /* Enable RTC alarm A */ + + modifyreg32(STM32_RTC_CR, 0, (RTC_CR_ALRAE | RTC_CR_ALRAIE)); + +errout_with_wprunlock: + rtc_wprlock(); + return ret; +} +#endif + +#if defined(CONFIG_RTC_ALARM) && CONFIG_RTC_NALARMS > 1 +static int rtchw_set_alrmbr(rtc_alarmreg_t alarmreg) +{ + int isr; + int ret = -EBUSY; + + /* Disable the write protection for RTC registers */ + + rtc_wprunlock(); + + /* Disable RTC alarm B & Interrupt B */ + + modifyreg32(STM32_RTC_CR, (RTC_CR_ALRBE | RTC_CR_ALRBIE), 0); + + /* Ensure Alarm B flag reset; this is edge triggered */ + + isr = getreg32(STM32_RTC_ISR) & ~RTC_ISR_ALRBF; + putreg32(isr, STM32_RTC_ISR); + + /* Wait for Alarm B to be writable */ + + ret = rtchw_check_alrbwf(); + if (ret != OK) + { + goto rtchw_set_alrmbr_exit; + } + + /* Set the RTC Alarm B register */ + + putreg32(alarmreg, STM32_RTC_ALRMBR); + putreg32(0, STM32_RTC_ALRMBSSR); + rtcinfo(" ALRMBR: %08" PRIx32 "\n", getreg32(STM32_RTC_ALRMBR)); + + /* Enable RTC alarm B */ + + modifyreg32(STM32_RTC_CR, 0, (RTC_CR_ALRBE | RTC_CR_ALRBIE)); + +rtchw_set_alrmbr_exit: + rtc_wprlock(); + return ret; +} +#endif + +/**************************************************************************** + * Name: rtc_enable_alarm + * + * Description: + * Enable ALARM interrupts + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_RTC_ALARM +static inline void rtc_enable_alarm(void) +{ + /* Is the alarm already enabled? */ + + if (!g_alarm_enabled) + { + /* Configure RTC interrupt to catch alarm interrupts. All RTC + * interrupts are connected to the EXTI controller. To enable the + * RTC Alarm interrupt, the following sequence is required: + * + * 1. Configure and enable the EXTI Line 18 in interrupt mode and + * select the rising edge sensitivity. + * EXTI line 19 RTC Tamper or Timestamp or CSS_LSE + * EXTI line 20 RTC Wakeup + * 2. Configure and enable the RTC_Alarm IRQ channel in the NVIC. + * 3. Configure the RTC to generate RTC alarms (Alarm A or Alarm B). + */ + + stm32_exti_alarm(true, false, true, stm32_rtc_alarm_handler, NULL); + g_alarm_enabled = true; + } +} +#endif + +/**************************************************************************** + * Name: stm32_rtc_getalarmdatetime + * + * Description: + * Get the current date and time for a RTC alarm. + * + * Input Parameters: + * reg - RTC alarm register + * tp - The location to return the high resolution time value. + * + * Returned Value: + * Zero (OK) on success; a negated errno on failure + * + ****************************************************************************/ + +#ifdef CONFIG_RTC_ALARM +static int stm32_rtc_getalarmdatetime(rtc_alarmreg_t reg, struct tm *tp) +{ + uint32_t data; + uint32_t tmp; + + DEBUGASSERT(tp != NULL); + + /* Sample the data time register. */ + + data = getreg32(reg); + + /* Convert the RTC time to fields in struct tm format. All of the STM32 + * ranges of values correspond between struct tm and the time register. + */ + + tmp = (data & (RTC_ALRMR_SU_MASK | RTC_ALRMR_ST_MASK)) >> + RTC_ALRMR_SU_SHIFT; + tp->tm_sec = rtc_bcd2bin(tmp); + + tmp = (data & (RTC_ALRMR_MNU_MASK | RTC_ALRMR_MNT_MASK)) >> + RTC_ALRMR_MNU_SHIFT; + tp->tm_min = rtc_bcd2bin(tmp); + + tmp = (data & (RTC_ALRMR_HU_MASK | RTC_ALRMR_HT_MASK)) >> + RTC_ALRMR_HU_SHIFT; + tp->tm_hour = rtc_bcd2bin(tmp); + + tmp = (data & (RTC_ALRMR_DU_MASK | RTC_ALRMR_DT_MASK)) >> + RTC_ALRMR_DU_SHIFT; + tp->tm_mday = rtc_bcd2bin(tmp); + + return OK; +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_rtc_is_initialized + * + * Description: + * Returns 'true' if the RTC has been initialized + * Returns 'false' if the RTC has never been initialized since first time + * power up, and the counters are stopped until it is first initialized. + * + * Input Parameters: + * None + * + * Returned Value: + * Returns true if RTC has been initialized. + * + ****************************************************************************/ + +bool stm32_rtc_is_initialized(void) +{ + uint32_t regval; + + regval = getreg32(RTC_MAGIC_REG); + + return regval == RTC_MAGIC || regval == RTC_MAGIC_TIME_SET; +} + +/**************************************************************************** + * Name: up_rtc_initialize + * + * Description: + * Initialize the hardware RTC per the selected configuration. This + * function is called once during the OS initialization sequence + * + * Input Parameters: + * None + * + * Returned Value: + * Zero (OK) on success; a negated errno on failure + * + ****************************************************************************/ + +int up_rtc_initialize(void) +{ + bool init_stat; + uint32_t regval; + + rtc_dumpregs("Before Initialization"); + + /* See if the clock has already been initialized; since it is battery + * backed, we don't need or want to re-initialize on each reset. + */ + + init_stat = stm32_rtc_is_initialized(); + if (!init_stat) + { + /* Enable write access to the backup domain (RTC registers, RTC + * backup data registers and backup SRAM). + */ + + stm32_pwr_enablebkp(true); + +#if defined(CONFIG_STM32_RTC_HSECLOCK) + modifyreg32(STM32_RCC_CSR, RCC_CSR_RTCSEL_MASK, RCC_CSR_RTCSEL_HSE); +#elif defined(CONFIG_STM32_RTC_LSICLOCK) + modifyreg32(STM32_RCC_CSR, RCC_CSR_RTCSEL_MASK, RCC_CSR_RTCSEL_LSI); +#elif defined(CONFIG_STM32_RTC_LSECLOCK) + modifyreg32(STM32_RCC_CSR, RCC_CSR_RTCSEL_MASK, RCC_CSR_RTCSEL_LSE); +#else +# error "No clock for RTC!" +#endif + + /* Enable the RTC Clock by setting the RTCEN bit in the CSR register */ + + modifyreg32(STM32_RCC_CSR, 0, RCC_CSR_RTCEN); + + /* Disable the write protection for RTC registers */ + + rtc_wprunlock(); + + /* Set Initialization mode */ + + if (OK != rtc_enterinit()) + { + /* Enable the write protection for RTC registers */ + + rtc_wprlock(); + + /* Disable write access to the backup domain (RTC registers, RTC + * backup data registers and backup SRAM). + */ + + stm32_pwr_enablebkp(false); + + rtc_dumpregs("After Failed Initialization"); + + return ERROR; + } + else + { + /* Clear RTC_CR FMT, OSEL and POL Bits */ + + regval = getreg32(STM32_RTC_CR); + regval &= ~(RTC_CR_FMT | RTC_CR_OSEL_MASK | RTC_CR_POL); + putreg32(regval, STM32_RTC_CR); + + /* Configure RTC pre-scaler with the required values */ + +#ifdef CONFIG_STM32_RTC_HSECLOCK + /* The HSE is divided by 32 prior to the prescaler we set here. + * + * NOTE: max HSE/32 is 4 MHz if it is to be used with RTC + */ + + /* For a 1 MHz clock this yields 0.9999360041 Hz on the second + * timer - which is pretty close. + */ + + putreg32(((uint32_t)7812 << RTC_PRER_PREDIV_S_SHIFT) | + ((uint32_t)0x7f << RTC_PRER_PREDIV_A_SHIFT), + STM32_RTC_PRER); +#elif defined(CONFIG_STM32_RTC_LSICLOCK) + /* Suitable values for 32.000 KHz LSI clock + * (29.5 - 34 KHz, though) + */ + + putreg32(((uint32_t)0xf9 << RTC_PRER_PREDIV_S_SHIFT) | + ((uint32_t)0x7f << RTC_PRER_PREDIV_A_SHIFT), + STM32_RTC_PRER); +#else /* defined(CONFIG_STM32_RTC_LSECLOCK) */ + /* Correct values for 32.768 KHz LSE clock */ + + putreg32(((uint32_t)0xff << RTC_PRER_PREDIV_S_SHIFT) | + ((uint32_t)0x7f << RTC_PRER_PREDIV_A_SHIFT), + STM32_RTC_PRER); +#endif + + /* Exit Initialization mode */ + + rtc_exitinit(); + + /* Wait for the RTC Time and Date registers to be synchronized + * with RTC APB clock. + */ + + rtc_synchwait(); + + /* Keep the fact that the RTC is initialized */ + + putreg32(RTC_MAGIC, RTC_MAGIC_REG); + + /* Enable the write protection for RTC registers */ + + rtc_wprlock(); + + /* Disable write access to the backup domain (RTC registers, RTC + * backup data registers and backup SRAM). + */ + + stm32_pwr_enablebkp(false); + } + } + else + { + /* Enable write access to the backup domain (RTC registers, RTC + * backup data registers and backup SRAM). + */ + + stm32_pwr_enablebkp(true); + + /* Write protection for RTC registers does not need to be disabled. */ + + rtc_resume(); + + /* Disable write access to the backup domain (RTC registers, RTC backup + * data registers and backup SRAM). + */ + + stm32_pwr_enablebkp(false); + } + + g_rtc_enabled = true; + rtc_dumpregs("After Initialization"); + + return OK; +} + +/**************************************************************************** + * Name: stm32_rtc_irqinitialize + * + * Description: + * Initialize IRQs for RTC, not possible during up_rtc_initialize because + * up_irqinitialize is called later. + * + * Input Parameters: + * None + * + * Returned Value: + * Zero (OK) on success; a negated errno on failure + * + ****************************************************************************/ + +int stm32_rtc_irqinitialize(void) +{ + /* Nothing to do */ + + return OK; +} + +/**************************************************************************** + * Name: stm32_rtc_getdatetime_with_subseconds + * + * Description: + * Get the current date and time from the date/time RTC. This interface + * is only supported by the date/time RTC hardware implementation. It is + * used to replace the system timer. It is only used by the RTOS during + * initialization to set up the system time when CONFIG_RTC and + * CONFIG_RTC_DATETIME are selected. + * + * Sub-second accuracy is returned through 'nsec'. + * + * Input Parameters: + * tp - The location to return the high resolution time value. + * nsec - The location to return the subsecond time value. + * + * Returned Value: + * Zero (OK) on success; a negated errno on failure + * + ****************************************************************************/ + +int stm32_rtc_getdatetime_with_subseconds(struct tm *tp, long *nsec) +{ +#ifdef CONFIG_STM32_HAVE_RTC_SUBSECONDS + uint32_t ssr; +#endif + uint32_t dr; + uint32_t tr; + uint32_t tmp; + + /* Sample the data time registers. There is a race condition here... If + * we sample the time just before midnight on December 31, the date could + * be wrong because the day rolled over while were sampling. Thus loop for + * checking overflow here is needed. There is a race condition with + * subseconds too. If we sample TR register just before second rolling + * and subseconds are read at wrong second, we get wrong time. + */ + + do + { + dr = getreg32(STM32_RTC_DR); + tr = getreg32(STM32_RTC_TR); +#ifdef CONFIG_STM32_HAVE_RTC_SUBSECONDS + ssr = getreg32(STM32_RTC_SSR); + tmp = getreg32(STM32_RTC_TR); + if (tmp != tr) + { + continue; + } +#endif + + tmp = getreg32(STM32_RTC_DR); + if (tmp == dr) + { + break; + } + } + while (1); + + rtc_dumpregs("Reading Time"); + + /* Convert the RTC time to fields in struct tm format. All of the STM32 + * ranges of values correspond between struct tm and the time register. + */ + + tmp = (tr & (RTC_TR_SU_MASK | RTC_TR_ST_MASK)) >> RTC_TR_SU_SHIFT; + tp->tm_sec = rtc_bcd2bin(tmp); + + tmp = (tr & (RTC_TR_MNU_MASK | RTC_TR_MNT_MASK)) >> RTC_TR_MNU_SHIFT; + tp->tm_min = rtc_bcd2bin(tmp); + + tmp = (tr & (RTC_TR_HU_MASK | RTC_TR_HT_MASK)) >> RTC_TR_HU_SHIFT; + tp->tm_hour = rtc_bcd2bin(tmp); + + /* Now convert the RTC date to fields in struct tm format: + * Days: 1-31 match in both cases. + * Month: STM32 is 1-12, struct tm is 0-11. + * Years: STM32 is 00-99, struct tm is years since 1900. + * WeekDay: STM32 is 1 = Mon - 7 = Sun + * + * Issue: I am not sure what the STM32 years mean. Are these the + * years 2000-2099? I'll assume so. + */ + + tmp = (dr & (RTC_DR_DU_MASK | RTC_DR_DT_MASK)) >> RTC_DR_DU_SHIFT; + tp->tm_mday = rtc_bcd2bin(tmp); + + tmp = (dr & (RTC_DR_MU_MASK | RTC_DR_MT)) >> RTC_DR_MU_SHIFT; + tp->tm_mon = rtc_bcd2bin(tmp) - 1; + + tmp = (dr & (RTC_DR_YU_MASK | RTC_DR_YT_MASK)) >> RTC_DR_YU_SHIFT; + tp->tm_year = rtc_bcd2bin(tmp) + 100; + + tmp = (dr & RTC_DR_WDU_MASK) >> RTC_DR_WDU_SHIFT; + tp->tm_wday = tmp % 7; + tp->tm_yday = tp->tm_mday - 1 + + clock_daysbeforemonth(tp->tm_mon, + clock_isleapyear(tp->tm_year + 1900)); + tp->tm_isdst = 0; + + /* Return RTC sub-seconds if a non-NULL value + * of nsec has been provided to receive the sub-second value. + */ + +#ifdef CONFIG_STM32_HAVE_RTC_SUBSECONDS + if (nsec) + { + uint32_t prediv_s; + uint32_t usecs; + + prediv_s = getreg32(STM32_RTC_PRER) & RTC_PRER_PREDIV_S_MASK; + prediv_s >>= RTC_PRER_PREDIV_S_SHIFT; + + ssr &= RTC_SSR_MASK; + + /* Maximum prediv_s is 0x7fff, thus we can multiply by 100000 and + * still fit 32-bit unsigned integer. + */ + + usecs = (((prediv_s - ssr) * 100000) / (prediv_s + 1)) * 10; + *nsec = usecs * 1000; + } +#else + DEBUGASSERT(nsec == NULL); +#endif + + rtc_dumptime(tp, "Returning"); + return OK; +} + +/**************************************************************************** + * Name: up_rtc_getdatetime + * + * Description: + * Get the current date and time from the date/time RTC. This interface + * is only supported by the date/time RTC hardware implementation. It is + * used to replace the system timer. It is only used by the RTOS during + * initialization to set up the system time when CONFIG_RTC and + * CONFIG_RTC_DATETIME are selected. + * + * NOTE: Some date/time RTC hardware is capability of sub-second accuracy. + * That sub-second accuracy is lost in this interface. However, since the + * system time is reinitialized on each power-up/reset, there will be no + * timing inaccuracy in the long run. + * + * Input Parameters: + * tp - The location to return the high resolution time value. + * + * Returned Value: + * Zero (OK) on success; a negated errno on failure + * + ****************************************************************************/ + +int up_rtc_getdatetime(struct tm *tp) +{ + return stm32_rtc_getdatetime_with_subseconds(tp, NULL); +} + +/**************************************************************************** + * Name: up_rtc_getdatetime_with_subseconds + * + * Description: + * Get the current date and time from the date/time RTC. This interface + * is only supported by the date/time RTC hardware implementation. + * It is used to replace the system timer. It is only used by the RTOS + * during initialization to set up the system time when CONFIG_RTC and + * CONFIG_RTC_DATETIME are selected (and CONFIG_RTC_HIRES is not). + * + * NOTE: This interface exposes sub-second accuracy capability of RTC + * hardware. This interface allow maintaining timing accuracy when + * system time needs constant resynchronization with RTC, for example + * with board level power-save mode utilizing deep-sleep modes such as + * STOP on STM32 MCUs. + * + * Input Parameters: + * tp - The location to return the high resolution time value. + * nsec - The location to return the subsecond time value. + * + * Returned Value: + * Zero (OK) on success; a negated errno on failure + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_HAVE_RTC_SUBSECONDS +# ifndef CONFIG_STM32_HAVE_RTC_SUBSECONDS +# error "Invalid config, enable CONFIG_STM32_HAVE_RTC_SUBSECONDS." +# endif +int up_rtc_getdatetime_with_subseconds(struct tm *tp, long *nsec) +{ + return stm32_rtc_getdatetime_with_subseconds(tp, nsec); +} +#endif + +/**************************************************************************** + * Name: stm32_rtc_setdatetime + * + * Description: + * Set the RTC to the provided time. RTC implementations which provide + * up_rtc_getdatetime() (CONFIG_RTC_DATETIME is selected) should provide + * this function. + * + * Input Parameters: + * tp - the time to use + * + * Returned Value: + * Zero (OK) on success; a negated errno on failure + * + ****************************************************************************/ + +int stm32_rtc_setdatetime(const struct tm *tp) +{ + uint32_t tr; + uint32_t dr; + int ret; + + rtc_dumptime(tp, "Setting time"); + + /* Then write the broken out values to the RTC */ + + /* Convert the struct tm format to RTC time register fields. + * All of the ranges of values correspond between struct tm and the time + * register. + */ + + tr = (rtc_bin2bcd(tp->tm_sec) << RTC_TR_SU_SHIFT) | + (rtc_bin2bcd(tp->tm_min) << RTC_TR_MNU_SHIFT) | + (rtc_bin2bcd(tp->tm_hour) << RTC_TR_HU_SHIFT); + tr &= ~RTC_TR_RESERVED_BITS; + + /* Now convert the fields in struct tm format to the RTC date register + * fields: + * + * Days: 1-31 match in both cases. + * Month: STM32 is 1-12, struct tm is 0-11. + * Years: STM32 is 00-99, struct tm is years since 1900. + * WeekDay: STM32 is 1 = Mon - 7 = Sun + * Issue: I am not sure what the STM32 years mean. Are these the + * years 2000-2099? I'll assume so. + */ + + dr = (rtc_bin2bcd(tp->tm_mday) << RTC_DR_DU_SHIFT) | + ((rtc_bin2bcd(tp->tm_mon + 1)) << RTC_DR_MU_SHIFT) | + ((tp->tm_wday == 0 ? 7 : (tp->tm_wday & 7)) << RTC_DR_WDU_SHIFT) | + ((rtc_bin2bcd(tp->tm_year - 100)) << RTC_DR_YU_SHIFT); + + dr &= ~RTC_DR_RESERVED_BITS; + + /* Disable the write protection for RTC registers */ + + rtc_wprunlock(); + + /* Set Initialization mode */ + + ret = rtc_enterinit(); + if (ret == OK) + { + /* Set the RTC TR and DR registers */ + + putreg32(tr, STM32_RTC_TR); + putreg32(dr, STM32_RTC_DR); + + /* Exit Initialization mode and wait for the RTC Time and Date + * registers to be synchronized with RTC APB clock. + */ + + rtc_exitinit(); + ret = rtc_synchwait(); + } + + /* Remember that the RTC is initialized and had its time set. */ + + if (getreg32(RTC_MAGIC_REG) != RTC_MAGIC_TIME_SET) + { + stm32_pwr_enablebkp(true); + putreg32(RTC_MAGIC_TIME_SET, RTC_MAGIC_REG); + stm32_pwr_enablebkp(false); + } + + /* Re-enable the write protection for RTC registers */ + + rtc_wprlock(); + rtc_dumpregs("New time setting"); + return ret; +} + +/**************************************************************************** + * Name: stm32_rtc_havesettime + * + * Description: + * Check if RTC time has been set. + * + * Returned Value: + * Returns true if RTC date-time have been previously set. + * + ****************************************************************************/ + +bool stm32_rtc_havesettime(void) +{ + return getreg32(RTC_MAGIC_REG) == RTC_MAGIC_TIME_SET; +} + +/**************************************************************************** + * Name: up_rtc_settime + * + * Description: + * Set the RTC to the provided time. All RTC implementations must be able + * to set their time based on a standard timespec. + * + * Input Parameters: + * tp - the time to use + * + * Returned Value: + * Zero (OK) on success; a negated errno on failure + * + ****************************************************************************/ + +int up_rtc_settime(const struct timespec *tp) +{ + struct tm newtime; + + /* Break out the time values (not that the time is set only to units of + * seconds) + */ + + gmtime_r(&tp->tv_sec, &newtime); + return stm32_rtc_setdatetime(&newtime); +} + +/**************************************************************************** + * Name: stm32_rtc_setalarm + * + * Description: + * Set an alarm to an absolute time using associated hardware. + * + * Input Parameters: + * alminfo - Information about the alarm configuration. + * + * Returned Value: + * Zero (OK) on success; a negated errno on failure + * + ****************************************************************************/ + +#ifdef CONFIG_RTC_ALARM +int stm32_rtc_setalarm(struct alm_setalarm_s *alminfo) +{ + struct alm_cbinfo_s *cbinfo; + rtc_alarmreg_t alarmreg; + int ret = -EINVAL; + + DEBUGASSERT(alminfo != NULL); + DEBUGASSERT(RTC_ALARM_LAST > alminfo->as_id); + + /* Make sure the alarm interrupt is enabled at the NVIC */ + + rtc_enable_alarm(); + + /* REVISIT: Should test that the time is in the future */ + + rtc_dumptime(&alminfo->as_time, "New alarm time"); + + /* Break out the values to the HW alarm register format. The values in + * all STM32 fields match the fields of struct tm in this case. Notice + * that the alarm is limited to one month. + */ + + alarmreg = (rtc_bin2bcd(alminfo->as_time.tm_sec) << RTC_ALRMR_SU_SHIFT) | + (rtc_bin2bcd(alminfo->as_time.tm_min) << RTC_ALRMR_MNU_SHIFT) | + (rtc_bin2bcd(alminfo->as_time.tm_hour) << RTC_ALRMR_HU_SHIFT) | + (rtc_bin2bcd(alminfo->as_time.tm_mday) << RTC_ALRMR_DU_SHIFT); + + /* Set the alarm in hardware and enable interrupts from the RTC */ + + switch (alminfo->as_id) + { + case RTC_ALARMA: + { + cbinfo = &g_alarmcb[RTC_ALARMA]; + cbinfo->ac_cb = alminfo->as_cb; + cbinfo->ac_arg = alminfo->as_arg; + + ret = rtchw_set_alrmar(alarmreg | RTC_ALRMR_ENABLE); + if (ret < 0) + { + cbinfo->ac_cb = NULL; + cbinfo->ac_arg = NULL; + } + } + break; + +#if CONFIG_RTC_NALARMS > 1 + case RTC_ALARMB: + { + cbinfo = &g_alarmcb[RTC_ALARMB]; + cbinfo->ac_cb = alminfo->as_cb; + cbinfo->ac_arg = alminfo->as_arg; + + ret = rtchw_set_alrmbr(alarmreg | RTC_ALRMR_ENABLE); + if (ret < 0) + { + cbinfo->ac_cb = NULL; + cbinfo->ac_arg = NULL; + } + } + break; +#endif + + default: + rtcerr("ERROR: Invalid ALARM%d\n", alminfo->as_id); + break; + } + + rtc_dumpregs("After alarm setting"); + + return ret; +} +#endif + +/**************************************************************************** + * Name: stm32_rtc_cancelalarm + * + * Description: + * Cancel an alarm. + * + * Input Parameters: + * alarmid - Identifies the alarm to be cancelled + * + * Returned Value: + * Zero (OK) on success; a negated errno on failure + * + ****************************************************************************/ + +#ifdef CONFIG_RTC_ALARM +int stm32_rtc_cancelalarm(enum alm_id_e alarmid) +{ + int ret = -EINVAL; + + DEBUGASSERT(RTC_ALARM_LAST > alarmid); + + /* Cancel the alarm in hardware and disable interrupts */ + + switch (alarmid) + { + case RTC_ALARMA: + { + /* Cancel the global callback function */ + + g_alarmcb[alarmid].ac_cb = NULL; + g_alarmcb[alarmid].ac_arg = NULL; + + /* Disable the write protection for RTC registers */ + + rtc_wprunlock(); + + /* Disable RTC alarm and interrupt */ + + modifyreg32(STM32_RTC_CR, (RTC_CR_ALRAE | RTC_CR_ALRAIE), 0); + + ret = rtchw_check_alrawf(); + if (ret < 0) + { + goto errout_with_wprunlock; + } + + /* Unset the alarm */ + + putreg32(-1, STM32_RTC_ALRMAR); + modifyreg32(STM32_RTC_ISR, RTC_ISR_ALRAF, 0); + rtc_wprlock(); + ret = OK; + } + break; + +#if CONFIG_RTC_NALARMS > 1 + case RTC_ALARMB: + { + /* Cancel the global callback function */ + + g_alarmcb[alarmid].ac_cb = NULL; + g_alarmcb[alarmid].ac_arg = NULL; + + /* Disable the write protection for RTC registers */ + + rtc_wprunlock(); + + /* Disable RTC alarm and interrupt */ + + modifyreg32(STM32_RTC_CR, (RTC_CR_ALRBE | RTC_CR_ALRBIE), 0); + + ret = rtchw_check_alrbwf(); + if (ret < 0) + { + goto errout_with_wprunlock; + } + + /* Unset the alarm */ + + putreg32(-1, STM32_RTC_ALRMBR); + modifyreg32(STM32_RTC_ISR, RTC_ISR_ALRBF, 0); + rtc_wprlock(); + ret = OK; + } + break; +#endif + + default: + rtcerr("ERROR: Invalid ALARM%d\n", alarmid); + break; + } + + return ret; + +errout_with_wprunlock: + rtc_wprlock(); + return ret; +} +#endif + +/**************************************************************************** + * Name: stm32_rtc_rdalarm + * + * Description: + * Query an alarm configured in hardware. + * + * Input Parameters: + * alminfo - Information about the alarm configuration. + * + * Returned Value: + * Zero (OK) on success; a negated errno on failure + * + ****************************************************************************/ + +#ifdef CONFIG_RTC_ALARM +int stm32_rtc_rdalarm(struct alm_rdalarm_s *alminfo) +{ + rtc_alarmreg_t alarmreg; + int ret = -EINVAL; + + DEBUGASSERT(alminfo != NULL); + DEBUGASSERT(RTC_ALARM_LAST > alminfo->ar_id); + + switch (alminfo->ar_id) + { + case RTC_ALARMA: + { + alarmreg = STM32_RTC_ALRMAR; + ret = stm32_rtc_getalarmdatetime(alarmreg, + (struct tm *)alminfo->ar_time); + } + break; + +#if CONFIG_RTC_NALARMS > 1 + case RTC_ALARMB: + { + alarmreg = STM32_RTC_ALRMBR; + ret = stm32_rtc_getalarmdatetime(alarmreg, + (struct tm *)alminfo->ar_time); + } + break; +#endif + + default: + rtcerr("ERROR: Invalid ALARM%d\n", alminfo->ar_id); + break; + } + + return ret; +} +#endif + +/**************************************************************************** + * Name: stm32_rtc_wakeup_handler + * + * Description: + * RTC WAKEUP interrupt service routine through the EXTI line + * + * Input Parameters: + * irq - The IRQ number that generated the interrupt + * + * Returned Value: + * Zero (OK) on success; A negated errno value on failure. + * + ****************************************************************************/ + +#ifdef CONFIG_RTC_PERIODIC +static int stm32_rtc_wakeup_handler(int irq, void *context, + void *arg) +{ + uint32_t regval = 0; + + stm32_pwr_enablebkp(true); + + regval = getreg32(STM32_RTC_ISR); + regval &= ~RTC_ISR_WUTF; + putreg32(regval, STM32_RTC_ISR); + + stm32_pwr_enablebkp(false); + + if (g_wakeupcb != NULL) + { + g_wakeupcb(); + } + + return OK; +} +#endif + +/**************************************************************************** + * Name: rtc_enable_wakeup + * + * Description: + * Enable periodic wakeup interrupts + * + ****************************************************************************/ + +#ifdef CONFIG_RTC_PERIODIC +static inline void rtc_enable_wakeup(void) +{ + if (!g_wakeup_enabled) + { + stm32_exti_wakeup(true, false, true, stm32_rtc_wakeup_handler, NULL); + g_wakeup_enabled = true; + } +} +#endif + +/**************************************************************************** + * Name: rtc_set_wcksel + * + * Description: + * Sets RTC wakeup clock selection value + * + ****************************************************************************/ + +#ifdef CONFIG_RTC_PERIODIC +static inline void rtc_set_wcksel(unsigned int wucksel) +{ + uint32_t regval = 0; + + regval = getreg32(STM32_RTC_CR); + regval &= ~RTC_CR_WUCKSEL_MASK; + regval |= wucksel; + putreg32(regval, STM32_RTC_CR); +} +#endif + +/**************************************************************************** + * Name: stm32_rtc_setperiodic + * + * Description: + * Set a periodic RTC wakeup + * + * Input Parameters: + * period - Time to sleep between wakeups + * callback - Function to call when the period expires. + * + * Returned Value: + * Zero (OK) on success; a negated errno on failure + * + ****************************************************************************/ + +#ifdef CONFIG_RTC_PERIODIC +int stm32_rtc_setperiodic(const struct timespec *period, + wakeupcb_t callback) +{ + unsigned int wutr_val; + int ret; + int timeout; + uint32_t regval; + uint32_t secs; + uint32_t millisecs; + +#if defined(CONFIG_STM32_RTC_HSECLOCK) +# error "Periodic wakeup not available for HSE" +#elif defined(CONFIG_STM32_RTC_LSICLOCK) +# error "Periodic wakeup not available for LSI (and it is too inaccurate!)" +#elif defined(CONFIG_STM32_RTC_LSECLOCK) + const uint32_t rtc_div16_max_msecs = 16 * 1000 * 0xffffu / + STM32_LSE_FREQUENCY; +#else +# error "No clock for RTC!" +#endif + + /* Lets use RTC wake-up with 0.001 sec to ~18 hour range. + * + * TODO: scale to higher periods, with necessary losing some precision. + * We currently go for subseconds accuracy instead of maximum period. + */ + + if (period->tv_sec > 0xffffu || + (period->tv_sec == 0xffffu && period->tv_nsec > 0)) + { + /* More than max. */ + + secs = 0xffffu; + millisecs = secs * 1000; + } + else + { + secs = period->tv_sec; + millisecs = secs * 1000 + period->tv_nsec / NSEC_PER_MSEC; + } + + if (millisecs == 0) + { + return -EINVAL; + } + + /* Make sure the alarm interrupt is enabled at the NVIC */ + + rtc_enable_wakeup(); + + rtc_wprunlock(); + + /* Clear WUTE in RTC_CR to disable the wakeup timer */ + + regval = getreg32(STM32_RTC_CR); + regval &= ~RTC_CR_WUTE; + putreg32(regval, STM32_RTC_CR); + + /* Poll WUTWF until it is set in RTC_ISR (takes around 2 RTCCLK clock + * cycles) + */ + + ret = -ETIMEDOUT; + for (timeout = 0; timeout < SYNCHRO_TIMEOUT; timeout++) + { + regval = getreg32(STM32_RTC_ISR); + if ((regval & RTC_ISR_WUTWF) != 0) + { + /* Synchronized */ + + ret = OK; + break; + } + } + + /* Set callback function pointer. */ + + g_wakeupcb = callback; + + if (millisecs <= rtc_div16_max_msecs) + { + unsigned int ticks; + + /* Select wake-up with 32768/16 hz counter. */ + + rtc_set_wcksel(RTC_CR_WUCKSEL_RTCDIV16); + + /* Get number of ticks. */ + + ticks = millisecs * STM32_LSE_FREQUENCY / (16 * 1000); + + /* Wake-up is after WUT+1 ticks. */ + + wutr_val = ticks - 1; + } + else + { + /* Select wake-up with 1hz counter. */ + + rtc_set_wcksel(RTC_CR_WUCKSEL_CKSPRE); + + /* Wake-up is after WUT+1 ticks. */ + + wutr_val = secs - 1; + } + + /* Program the wakeup auto-reload value WUT[15:0], and the wakeup clock + * selection. + */ + + putreg32(wutr_val, STM32_RTC_WUTR); + + regval = getreg32(STM32_RTC_CR); + regval |= RTC_CR_WUTIE | RTC_CR_WUTE; + putreg32(regval, STM32_RTC_CR); + + /* Just in case resets the WUTF flag in RTC_ISR */ + + regval = getreg32(STM32_RTC_ISR); + regval &= ~RTC_ISR_WUTF; + putreg32(regval, STM32_RTC_ISR); + + rtc_wprlock(); + + return ret; +} +#endif + +/**************************************************************************** + * Name: stm32_rtc_cancelperiodic + * + * Description: + * Cancel a periodic wakeup + * + * Input Parameters: + * + * Returned Value: + * Zero (OK) on success; a negated errno on failure + * + ****************************************************************************/ + +#ifdef CONFIG_RTC_PERIODIC +int stm32_rtc_cancelperiodic(void) +{ + int ret = OK; + int timeout = 0; + uint32_t regval = 0; + + rtc_wprunlock(); + + /* Clear WUTE and WUTIE in RTC_CR to disable the wakeup timer */ + + regval = getreg32(STM32_RTC_CR); + regval &= ~(RTC_CR_WUTE | RTC_CR_WUTIE); + putreg32(regval, STM32_RTC_CR); + + /* Poll WUTWF until it is set in RTC_ISR (takes around 2 RTCCLK clock + * cycles) + */ + + ret = -ETIMEDOUT; + for (timeout = 0; timeout < SYNCHRO_TIMEOUT; timeout++) + { + regval = getreg32(STM32_RTC_ISR); + if ((regval & RTC_ISR_WUTWF) != 0) + { + /* Synchronized */ + + ret = OK; + break; + } + } + + /* Clears RTC_WUTR register */ + + regval = getreg32(STM32_RTC_WUTR); + regval &= ~RTC_WUTR_MASK; + putreg32(regval, STM32_RTC_WUTR); + + rtc_wprlock(); + + return ret; +} +#endif + +#endif /* CONFIG_STM32_RTC */ diff --git a/arch/arm/src/common/stm32/stm32_rtcc_m3m4_v1.c b/arch/arm/src/common/stm32/stm32_rtcc_m3m4_v1.c new file mode 100644 index 0000000000000..fac37d3b5638a --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_rtcc_m3m4_v1.c @@ -0,0 +1,1080 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_rtcc_m3m4_v1.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include +#include + +#include + +#include "arm_internal.h" +#include "stm32_rcc.h" +#include "stm32_pwr.h" +#include "stm32_exti.h" +#include "stm32_rtc.h" + +#ifdef CONFIG_STM32_RTC + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* This RTC implementation supports only date/time RTC hardware */ + +#ifndef CONFIG_RTC_DATETIME +# error "CONFIG_RTC_DATETIME must be set to use this driver" +#endif + +#ifdef CONFIG_RTC_HIRES +# error "CONFIG_RTC_HIRES must NOT be set with this driver" +#endif + +#ifndef CONFIG_STM32_PWR +# error "CONFIG_STM32_PWR must selected to use this driver" +#endif + +/* Constants ****************************************************************/ + +#define SYNCHRO_TIMEOUT (0x00020000) +#define INITMODE_TIMEOUT (0x00010000) + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* Callback to use when the alarm expires */ + +#ifdef CONFIG_RTC_ALARM +static alarmcb_t g_alarmcb; +#endif + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/* g_rtc_enabled is set true after the RTC has successfully initialized */ + +volatile bool g_rtc_enabled = false; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: rtc_dumpregs + ****************************************************************************/ + +#ifdef CONFIG_DEBUG_RTC_INFO +static void rtc_dumpregs(const char *msg) +{ + rtcinfo("%s:\n", msg); + rtcinfo(" TR: %08" PRIx32 "\n", getreg32(STM32_RTC_TR)); + rtcinfo(" DR: %08" PRIx32 "\n", getreg32(STM32_RTC_DR)); + rtcinfo(" CR: %08" PRIx32 "\n", getreg32(STM32_RTC_CR)); + rtcinfo(" ISR: %08" PRIx32 "\n", getreg32(STM32_RTC_ISR)); + rtcinfo(" PRER: %08" PRIx32 "\n", getreg32(STM32_RTC_PRER)); + rtcinfo(" WUTR: %08" PRIx32 "\n", getreg32(STM32_RTC_WUTR)); +#ifndef CONFIG_STM32_STM32F30XX + rtcinfo(" CALIBR: %08" PRIx32 "\n", getreg32(STM32_RTC_CALIBR)); +#endif + rtcinfo(" ALRMAR: %08" PRIx32 "\n", getreg32(STM32_RTC_ALRMAR)); + rtcinfo(" ALRMBR: %08" PRIx32 "\n", getreg32(STM32_RTC_ALRMBR)); + rtcinfo(" SHIFTR: %08" PRIx32 "\n", getreg32(STM32_RTC_SHIFTR)); + rtcinfo(" TSTR: %08" PRIx32 "\n", getreg32(STM32_RTC_TSTR)); + rtcinfo(" TSDR: %08" PRIx32 "\n", getreg32(STM32_RTC_TSDR)); + rtcinfo(" TSSSR: %08" PRIx32 "\n", getreg32(STM32_RTC_TSSSR)); + rtcinfo(" CALR: %08" PRIx32 "\n", getreg32(STM32_RTC_CALR)); + rtcinfo(" TAFCR: %08" PRIx32 "\n", getreg32(STM32_RTC_TAFCR)); + rtcinfo("ALRMASSR: %08" PRIx32 "\n", getreg32(STM32_RTC_ALRMASSR)); + rtcinfo("ALRMBSSR: %08" PRIx32 "\n", getreg32(STM32_RTC_ALRMBSSR)); + rtcinfo("MAGICREG: %08" PRIx32 "\n", getreg32(RTC_MAGIC_REG)); +} +#else +# define rtc_dumpregs(msg) +#endif + +/**************************************************************************** + * Name: rtc_dumptime + ****************************************************************************/ + +#ifdef CONFIG_DEBUG_RTC_INFO +static void rtc_dumptime(struct tm *tp, const char *msg) +{ + rtcinfo("%s:\n", msg); + rtcinfo(" tm_sec: %08x\n", tp->tm_sec); + rtcinfo(" tm_min: %08x\n", tp->tm_min); + rtcinfo(" tm_hour: %08x\n", tp->tm_hour); + rtcinfo(" tm_mday: %08x\n", tp->tm_mday); + rtcinfo(" tm_mon: %08x\n", tp->tm_mon); + rtcinfo(" tm_year: %08x\n", tp->tm_year); +} +#else +# define rtc_dumptime(tp, msg) +#endif + +/**************************************************************************** + * Name: rtc_wprunlock + * + * Description: + * Disable RTC write protection + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void rtc_wprunlock(void) +{ + /* Enable write access to the backup domain (RTC registers, RTC backup data + * registers and backup SRAM). + */ + + stm32_pwr_enablebkp(true); + + /* The following steps are required to unlock the write protection on all + * the RTC registers (except for RTC_ISR[13:8], RTC_TAFCR, and RTC_BKPxR). + * + * 1. Write 0xCA into the RTC_WPR register. + * 2. Write 0x53 into the RTC_WPR register. + * + * Writing a wrong key re-activates the write protection. + */ + + putreg32(0xca, STM32_RTC_WPR); + putreg32(0x53, STM32_RTC_WPR); +} + +/**************************************************************************** + * Name: rtc_wprlock + * + * Description: + * Enable RTC write protection + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +static inline void rtc_wprlock(void) +{ + /* Writing any wrong key re-activates the write protection. */ + + putreg32(0xff, STM32_RTC_WPR); + + /* Disable write access to the backup domain (RTC registers, RTC backup + * data registers and backup SRAM). + */ + + stm32_pwr_enablebkp(false); +} + +/**************************************************************************** + * Name: rtc_synchwait + * + * Description: + * Waits until the RTC Time and Date registers (RTC_TR and RTC_DR) are + * synchronized with RTC APB clock. + * + * Input Parameters: + * None + * + * Returned Value: + * Zero (OK) on success; a negated errno on failure + * + ****************************************************************************/ + +static int rtc_synchwait(void) +{ + volatile uint32_t timeout; + uint32_t regval; + int ret; + + /* Disable the write protection for RTC registers */ + + rtc_wprunlock(); + + /* Clear Registers synchronization flag (RSF) */ + + regval = getreg32(STM32_RTC_ISR); + regval &= ~RTC_ISR_RSF; + putreg32(regval, STM32_RTC_ISR); + + /* Now wait the registers to become synchronised */ + + ret = -ETIMEDOUT; + for (timeout = 0; timeout < SYNCHRO_TIMEOUT; timeout++) + { + regval = getreg32(STM32_RTC_ISR); + if ((regval & RTC_ISR_RSF) != 0) + { + /* Synchronized */ + + ret = OK; + break; + } + } + + /* Re-enable the write protection for RTC registers */ + + rtc_wprlock(); + return ret; +} + +/**************************************************************************** + * Name: rtc_enterinit + * + * Description: + * Enter RTC initialization mode. + * + * Input Parameters: + * None + * + * Returned Value: + * Zero (OK) on success; a negated errno on failure + * + ****************************************************************************/ + +static int rtc_enterinit(void) +{ + volatile uint32_t timeout; + uint32_t regval; + int ret; + + /* Check if the Initialization mode is already set */ + + regval = getreg32(STM32_RTC_ISR); + + ret = OK; + if ((regval & RTC_ISR_INITF) == 0) + { + /* Set the Initialization mode */ + + putreg32(RTC_ISR_INIT, STM32_RTC_ISR); + + /* Wait until the RTC is in the INIT state (or a timeout occurs) */ + + ret = -ETIMEDOUT; + for (timeout = 0; timeout < INITMODE_TIMEOUT; timeout++) + { + regval = getreg32(STM32_RTC_ISR); + if ((regval & RTC_ISR_INITF) != 0) + { + ret = OK; + break; + } + } + } + + return ret; +} + +/**************************************************************************** + * Name: rtc_exitinit + * + * Description: + * Exit RTC initialization mode. + * + * Input Parameters: + * None + * + * Returned Value: + * Zero (OK) on success; a negated errno on failure + * + ****************************************************************************/ + +static void rtc_exitinit(void) +{ + uint32_t regval; + + regval = getreg32(STM32_RTC_ISR); + regval &= ~(RTC_ISR_INIT); + putreg32(regval, STM32_RTC_ISR); +} + +/**************************************************************************** + * Name: rtc_bin2bcd + * + * Description: + * Converts a 2 digit binary to BCD format + * + * Input Parameters: + * value - The byte to be converted. + * + * Returned Value: + * The value in BCD representation + * + ****************************************************************************/ + +static uint32_t rtc_bin2bcd(int value) +{ + uint32_t msbcd = 0; + + while (value >= 10) + { + msbcd++; + value -= 10; + } + + return (msbcd << 4) | value; +} + +/**************************************************************************** + * Name: rtc_bin2bcd + * + * Description: + * Convert from 2 digit BCD to binary. + * + * Input Parameters: + * value - The BCD value to be converted. + * + * Returned Value: + * The value in binary representation + * + ****************************************************************************/ + +static int rtc_bcd2bin(uint32_t value) +{ + uint32_t tens = (value >> 4) * 10; + return (int)(tens + (value & 0x0f)); +} + +/**************************************************************************** + * Name: rtc_setup + * + * Description: + * Performs first time configuration of the RTC. A special value written + * into back-up register 0 will prevent this function from being called on + * sub-sequent resets or power up. + * + * Input Parameters: + * None + * + * Returned Value: + * Zero (OK) on success; a negated errno on failure + * + ****************************************************************************/ + +static int rtc_setup(void) +{ + uint32_t regval; + int ret; + + /* Disable the write protection for RTC registers */ + + rtc_wprunlock(); + + /* Set Initialization mode */ + + ret = rtc_enterinit(); + if (ret == OK) + { + /* Set the 24 hour format by clearing the FMT bit in the RTC + * control register + */ + + regval = getreg32(STM32_RTC_CR); + regval &= ~RTC_CR_FMT; + putreg32(regval, STM32_RTC_CR); + + /* Configure RTC pre-scaler with the required values */ + +#ifdef CONFIG_STM32_RTC_HSECLOCK + /* STMicro app note AN4759 suggests using 7999 and 124 to + * get exactly 1MHz when using the RTC at 8MHz. + */ + + putreg32(((uint32_t)7999 << RTC_PRER_PREDIV_S_SHIFT) | + ((uint32_t)124 << RTC_PRER_PREDIV_A_SHIFT), + STM32_RTC_PRER); +#else + /* Correct values for 32.768 KHz LSE clock and inaccurate LSI clock */ + + putreg32(((uint32_t)0xff << RTC_PRER_PREDIV_S_SHIFT) | + ((uint32_t)0x7f << RTC_PRER_PREDIV_A_SHIFT), + STM32_RTC_PRER); +#endif + + /* Exit RTC initialization mode */ + + rtc_exitinit(); + } + + /* Re-enable the write protection for RTC registers */ + + rtc_wprlock(); + + return ret; +} + +/**************************************************************************** + * Name: rtc_resume + * + * Description: + * Called when the RTC was already initialized on a previous power cycle. + * This just brings the RTC back into full operation. + * + * Input Parameters: + * None + * + * Returned Value: + * Zero (OK) on success; a negated errno on failure + * + ****************************************************************************/ + +static void rtc_resume(void) +{ +#ifdef CONFIG_RTC_ALARM + uint32_t regval; + + /* Clear the RTC alarm flags */ + + regval = getreg32(STM32_RTC_ISR); + regval &= ~(RTC_ISR_ALRAF | RTC_ISR_ALRBF); + putreg32(regval, STM32_RTC_ISR); + + /* Clear the EXTI Line 17 Pending bit (Connected internally to RTC Alarm) */ + + putreg32((1 << 17), STM32_EXTI_PR); +#endif +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_rtc_initialize + * + * Description: + * Initialize the hardware RTC per the selected configuration. + * This function is called once during the OS initialization sequence + * + * Input Parameters: + * None + * + * Returned Value: + * Zero (OK) on success; a negated errno on failure + * + ****************************************************************************/ + +int up_rtc_initialize(void) +{ + uint32_t regval; + uint32_t tr_bkp; + uint32_t dr_bkp; + int ret; + int maxretry = 10; + int nretry = 0; + + /* Clocking for the PWR block must be provided. However, this is done + * unconditionally in stm32f40xxx_rcc.c on power up. This done + * unconditionally because the PWR block is also needed to set the internal + * voltage regulator for maximum performance. + */ + + rtc_dumpregs("On reset"); + + /* Select the clock source */ + + /* Save the token before losing it when resetting */ + + regval = getreg32(RTC_MAGIC_REG); + + stm32_pwr_enablebkp(true); + + if (regval != RTC_MAGIC && regval != RTC_MAGIC_TIME_SET) + { + /* Some boards do not have the external 32khz oscillator installed, + * for those boards we must fallback to the crummy internal RC clock + * or the external high rate clock + */ + +#ifdef CONFIG_STM32_RTC_HSECLOCK + /* Use the HSE clock as the input to the RTC block */ + + modifyreg32(STM32_RCC_BDCR, RCC_BDCR_RTCSEL_MASK, RCC_BDCR_RTCSEL_HSE); + +#elif defined(CONFIG_STM32_RTC_LSICLOCK) + /* Use the LSI clock as the input to the RTC block */ + + modifyreg32(STM32_RCC_BDCR, RCC_BDCR_RTCSEL_MASK, RCC_BDCR_RTCSEL_LSI); + +#elif defined(CONFIG_STM32_RTC_LSECLOCK) + /* Use the LSE clock as the input to the RTC block */ + + modifyreg32(STM32_RCC_BDCR, RCC_BDCR_RTCSEL_MASK, RCC_BDCR_RTCSEL_LSE); + +#endif + /* Enable the RTC Clock by setting the RTCEN bit in the RCC register */ + + modifyreg32(STM32_RCC_BDCR, 0, RCC_BDCR_RTCEN); + } + else /* The RTC is already in use: check if the clock source is changed */ + { +#if defined(CONFIG_STM32_RTC_HSECLOCK) || defined(CONFIG_STM32_RTC_LSICLOCK) || \ + defined(CONFIG_STM32_RTC_LSECLOCK) + + uint32_t clksrc = getreg32(STM32_RCC_BDCR); + +#if defined(CONFIG_STM32_RTC_HSECLOCK) + if ((clksrc & RCC_BDCR_RTCSEL_MASK) != RCC_BDCR_RTCSEL_HSE) +#elif defined(CONFIG_STM32_RTC_LSICLOCK) + if ((clksrc & RCC_BDCR_RTCSEL_MASK) != RCC_BDCR_RTCSEL_LSI) +#elif defined(CONFIG_STM32_RTC_LSECLOCK) + if ((clksrc & RCC_BDCR_RTCSEL_MASK) != RCC_BDCR_RTCSEL_LSE) +#endif +#endif + { + tr_bkp = getreg32(STM32_RTC_TR); + dr_bkp = getreg32(STM32_RTC_DR); + modifyreg32(STM32_RCC_BDCR, 0, RCC_BDCR_BDRST); + modifyreg32(STM32_RCC_BDCR, RCC_BDCR_BDRST, 0); + +#if defined(CONFIG_STM32_RTC_HSECLOCK) + /* Change to the new clock as the input to the RTC block */ + + modifyreg32(STM32_RCC_BDCR, + RCC_BDCR_RTCSEL_MASK, RCC_BDCR_RTCSEL_HSE); + +#elif defined(CONFIG_STM32_RTC_LSICLOCK) + modifyreg32(STM32_RCC_BDCR, + RCC_BDCR_RTCSEL_MASK, RCC_BDCR_RTCSEL_LSI); + +#elif defined(CONFIG_STM32_RTC_LSECLOCK) + modifyreg32(STM32_RCC_BDCR, + RCC_BDCR_RTCSEL_MASK, RCC_BDCR_RTCSEL_LSE); +#endif + + putreg32(tr_bkp, STM32_RTC_TR); + putreg32(dr_bkp, STM32_RTC_DR); + + /* Remember that the RTC is initialized */ + + putreg32(RTC_MAGIC, RTC_MAGIC_REG); + + /* Enable the RTC Clock by setting the RTCEN bit in the RCC + * register + */ + + modifyreg32(STM32_RCC_BDCR, 0, RCC_BDCR_RTCEN); + } + } + + stm32_pwr_enablebkp(false); + + /* Loop, attempting to initialize/resume the RTC. This loop is necessary + * because it seems that occasionally it takes longer to initialize the RTC + * (the actual failure is in rtc_synchwait()). + */ + + do + { + /* Wait for the RTC Time and Date registers to be synchronized with RTC + * APB clock. + */ + + ret = rtc_synchwait(); + + /* Check that rtc_syncwait() returned successfully */ + + switch (ret) + { + case OK: + { + rtcinfo("rtc_syncwait() okay\n"); + break; + } + + default: + { + rtcerr("ERROR: rtc_syncwait() failed (%d)\n", ret); + break; + } + } + } + while (ret != OK && ++nretry < maxretry); + + /* Check if the one-time initialization of the RTC has already been + * performed. We can determine this by checking if the magic number + * has been written to the back-up date register DR0. + */ + + if (regval != RTC_MAGIC && regval != RTC_MAGIC_TIME_SET) + { + rtcinfo("Do setup\n"); + + /* Perform the one-time setup of the LSE clocking to the RTC */ + + ret = rtc_setup(); + + /* Enable write access to the backup domain (RTC registers, RTC + * backup data registers and backup SRAM). + */ + + stm32_pwr_enablebkp(true); + + /* Remember that the RTC is initialized */ + + putreg32(RTC_MAGIC, RTC_MAGIC_REG); + + /* Disable write access to the backup domain (RTC registers, RTC + * backup data registers and backup SRAM). + */ + + stm32_pwr_enablebkp(false); + } + else + { + rtcinfo("Do resume\n"); + + /* RTC already set-up, just resume normal operation */ + + rtc_resume(); + rtc_dumpregs("Did resume"); + } + + if (ret != OK && nretry > 0) + { + rtcinfo("setup/resume ran %d times and failed with %d\n", + nretry, ret); + return -ETIMEDOUT; + } + + /* Configure RTC interrupt to catch alarm interrupts. All RTC interrupts + * are connected to the EXTI controller. To enable the RTC Alarm + * interrupt, the following sequence is required: + * + * 1. Configure and enable the EXTI Line 17 in interrupt mode and select + * the rising edge sensitivity. + * 2. Configure and enable the RTC_Alarm IRQ channel in the NVIC. + * 3. Configure the RTC to generate RTC alarms (Alarm A or Alarm B). + */ + + g_rtc_enabled = true; + rtc_dumpregs("After Initialization"); + return OK; +} + +/**************************************************************************** + * Name: stm32_rtc_irqinitialize + * + * Description: + * Initialize IRQs for RTC, not possible during up_rtc_initialize because + * up_irqinitialize is called later. + * + * Input Parameters: + * None + * + * Returned Value: + * Zero (OK) on success; a negated errno on failure + * + ****************************************************************************/ + +int stm32_rtc_irqinitialize(void) +{ +#ifdef CONFIG_RTC_ALARM +# warning "Missing logic" +#endif + + return OK; +} + +/**************************************************************************** + * Name: stm32_rtc_getdatetime_with_subseconds + * + * Description: + * Get the current date and time from the date/time RTC. This interface + * is only supported by the date/time RTC hardware implementation. + * It is used to replace the system timer. It is only used by the RTOS + * during initialization to set up the system time when CONFIG_RTC and + * CONFIG_RTC_DATETIME are selected (and CONFIG_RTC_HIRES is not). + * + * NOTE: Some date/time RTC hardware is capability of sub-second accuracy. + * That sub-second accuracy is returned through 'nsec'. + * + * Input Parameters: + * tp - The location to return the high resolution time value. + * nsec - The location to return the subsecond time value. + * + * Returned Value: + * Zero (OK) on success; a negated errno on failure + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_HAVE_RTC_SUBSECONDS +int stm32_rtc_getdatetime_with_subseconds(struct tm *tp, long *nsec) +#else +int up_rtc_getdatetime(struct tm *tp) +#endif +{ +#ifdef CONFIG_STM32_HAVE_RTC_SUBSECONDS + uint32_t ssr; +#endif + uint32_t dr; + uint32_t tr; + uint32_t tmp; + + /* Sample the data time registers. There is a race condition here... If + * we sample the time just before midnight on December 31, the date could + * be wrong because the day rolled over while were sampling. Thus loop for + * checking overflow here is needed. There is a race condition with + * subseconds too. If we sample TR register just before second rolling + * and subseconds are read at wrong second, we get wrong time. + */ + + do + { + dr = getreg32(STM32_RTC_DR); + tr = getreg32(STM32_RTC_TR); +#ifdef CONFIG_STM32_HAVE_RTC_SUBSECONDS + ssr = getreg32(STM32_RTC_SSR); + tmp = getreg32(STM32_RTC_TR); + if (tmp != tr) + { + continue; + } +#endif + + tmp = getreg32(STM32_RTC_DR); + if (tmp == dr) + { + break; + } + } + while (1); + + rtc_dumpregs("Reading Time"); + + /* Convert the RTC time to fields in struct tm format. All of the STM32 + * ranges of values correspond between struct tm and the time register. + */ + + tmp = (tr & (RTC_TR_SU_MASK | RTC_TR_ST_MASK)) >> RTC_TR_SU_SHIFT; + tp->tm_sec = rtc_bcd2bin(tmp); + + tmp = (tr & (RTC_TR_MNU_MASK | RTC_TR_MNT_MASK)) >> RTC_TR_MNU_SHIFT; + tp->tm_min = rtc_bcd2bin(tmp); + + tmp = (tr & (RTC_TR_HU_MASK | RTC_TR_HT_MASK)) >> RTC_TR_HU_SHIFT; + tp->tm_hour = rtc_bcd2bin(tmp); + + /* Now convert the RTC date to fields in struct tm format: + * Days: 1-31 match in both cases. + * Month: STM32 is 1-12, struct tm is 0-11. + * Years: STM32 is 00-99, struct tm is years since 1900. + * WeekDay: STM32 is 1 = Mon - 7 = Sun + * + * Issue: I am not sure what the STM32 years mean. Are these the + * years 2000-2099? I'll assume so. + */ + + tmp = (dr & (RTC_DR_DU_MASK | RTC_DR_DT_MASK)) >> RTC_DR_DU_SHIFT; + tp->tm_mday = rtc_bcd2bin(tmp); + + tmp = (dr & (RTC_DR_MU_MASK | RTC_DR_MT)) >> RTC_DR_MU_SHIFT; + tp->tm_mon = rtc_bcd2bin(tmp) - 1; + + tmp = (dr & (RTC_DR_YU_MASK | RTC_DR_YT_MASK)) >> RTC_DR_YU_SHIFT; + tp->tm_year = rtc_bcd2bin(tmp) + 100; + + tmp = (dr & RTC_DR_WDU_MASK) >> RTC_DR_WDU_SHIFT; + tp->tm_wday = tmp % 7; + tp->tm_yday = tp->tm_mday - 1 + + clock_daysbeforemonth(tp->tm_mon, + clock_isleapyear(tp->tm_year + 1900)); + tp->tm_isdst = 0; + +#ifdef CONFIG_STM32_HAVE_RTC_SUBSECONDS + /* Return RTC sub-seconds if no configured and if a non-NULL value + * of nsec has been provided to receive the sub-second value. + */ + + if (nsec) + { + uint32_t prediv_s; + uint32_t usecs; + + prediv_s = getreg32(STM32_RTC_PRER) & RTC_PRER_PREDIV_S_MASK; + prediv_s >>= RTC_PRER_PREDIV_S_SHIFT; + + ssr &= RTC_SSR_MASK; + + /* Maximum prediv_s is 0x7fff, thus we can multiply by 100000 and + * still fit 32-bit unsigned integer. + */ + + usecs = (((prediv_s - ssr) * 100000) / (prediv_s + 1)) * 10; + *nsec = usecs * 1000; + } +#endif /* CONFIG_STM32_HAVE_RTC_SUBSECONDS */ + + rtc_dumptime(tp, "Returning"); + return OK; +} + +/**************************************************************************** + * Name: up_rtc_getdatetime + * + * Description: + * Get the current date and time from the date/time RTC. This interface + * is only supported by the date/time RTC hardware implementation. + * It is used to replace the system timer. It is only used by the RTOS + * during initialization to set up the system time when CONFIG_RTC and + * CONFIG_RTC_DATETIME are selected (and CONFIG_RTC_HIRES is not). + * + * NOTE: Some date/time RTC hardware is capability of sub-second accuracy. + * That sub-second accuracy is lost in this interface. However, since the + * system time is reinitialized on each power-up/reset, there will be no + * timing inaccuracy in the long run. + * + * Input Parameters: + * tp - The location to return the high resolution time value. + * + * Returned Value: + * Zero (OK) on success; a negated errno on failure + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_HAVE_RTC_SUBSECONDS +int up_rtc_getdatetime(struct tm *tp) +{ + return stm32_rtc_getdatetime_with_subseconds(tp, NULL); +} +#endif + +/**************************************************************************** + * Name: up_rtc_getdatetime_with_subseconds + * + * Description: + * Get the current date and time from the date/time RTC. This interface + * is only supported by the date/time RTC hardware implementation. + * It is used to replace the system timer. It is only used by the RTOS + * during initialization to set up the system time when CONFIG_RTC and + * CONFIG_RTC_DATETIME are selected (and CONFIG_RTC_HIRES is not). + * + * NOTE: + * This interface exposes sub-second accuracy capability of RTC hardware. + * This interface allow maintaining timing accuracy when system time needs + * constant resynchronization with RTC, for example on MCU with low-power + * state that stop system timer. + * + * Input Parameters: + * tp - The location to return the high resolution time value. + * nsec - The location to return the subsecond time value. + * + * Returned Value: + * Zero (OK) on success; a negated errno on failure + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_HAVE_RTC_SUBSECONDS +# ifndef CONFIG_STM32_HAVE_RTC_SUBSECONDS +# error "Invalid config, enable CONFIG_STM32_HAVE_RTC_SUBSECONDS." +# endif +int up_rtc_getdatetime_with_subseconds(struct tm *tp, long *nsec) +{ + return stm32_rtc_getdatetime_with_subseconds(tp, nsec); +} +#endif + +/**************************************************************************** + * Name: stm32_rtc_setdatetime + * + * Description: + * Set the RTC to the provided time. RTC implementations which provide + * up_rtc_getdatetime() (CONFIG_RTC_DATETIME is selected) should provide + * this function. + * + * Input Parameters: + * tp - the time to use + * + * Returned Value: + * Zero (OK) on success; a negated errno on failure + * + ****************************************************************************/ + +int stm32_rtc_setdatetime(const struct tm *tp) +{ + uint32_t tr; + uint32_t dr; + int ret; + + rtc_dumptime(tp, "Setting time"); + + /* Then write the broken out values to the RTC */ + + /* Convert the struct tm format to RTC time register fields. All of the + * STM32 All of the ranges of values correspond between struct tm and the + * time register. + */ + + tr = (rtc_bin2bcd(tp->tm_sec) << RTC_TR_SU_SHIFT) | + (rtc_bin2bcd(tp->tm_min) << RTC_TR_MNU_SHIFT) | + (rtc_bin2bcd(tp->tm_hour) << RTC_TR_HU_SHIFT); + tr &= ~RTC_TR_RESERVED_BITS; + + /* Now convert the fields in struct tm format to the RTC date register + * fields: + * Days: 1-31 match in both cases. + * Month: STM32 is 1-12, struct tm is 0-11. + * Years: STM32 is 00-99, struct tm is years since 1900. + * WeekDay: STM32 is 1 = Mon - 7 = Sun + * Issue: I am not sure what the STM32 years mean. Are these the + * years 2000-2099? I'll assume so. + */ + + dr = (rtc_bin2bcd(tp->tm_mday) << RTC_DR_DU_SHIFT) | + ((rtc_bin2bcd(tp->tm_mon + 1)) << RTC_DR_MU_SHIFT) | + ((tp->tm_wday == 0 ? 7 : (tp->tm_wday & 7)) << RTC_DR_WDU_SHIFT) | + ((rtc_bin2bcd(tp->tm_year - 100)) << RTC_DR_YU_SHIFT); + + dr &= ~RTC_DR_RESERVED_BITS; + + /* Disable the write protection for RTC registers */ + + rtc_wprunlock(); + + /* Set Initialization mode */ + + ret = rtc_enterinit(); + if (ret == OK) + { + /* Set the RTC TR and DR registers */ + + putreg32(tr, STM32_RTC_TR); + putreg32(dr, STM32_RTC_DR); + + /* Exit Initialization mode and wait for the RTC Time and Date + * registers to be synchronized with RTC APB clock. + */ + + rtc_exitinit(); + ret = rtc_synchwait(); + } + + /* Remember that the RTC is initialized and had its time set. */ + + if (getreg32(RTC_MAGIC_REG) != RTC_MAGIC_TIME_SET) + { + stm32_pwr_enablebkp(true); + putreg32(RTC_MAGIC_TIME_SET, RTC_MAGIC_REG); + stm32_pwr_enablebkp(false); + } + + /* Re-enable the write protection for RTC registers */ + + rtc_wprlock(); + rtc_dumpregs("New time setting"); + return ret; +} + +/**************************************************************************** + * Name: up_rtc_settime + * + * Description: + * Set the RTC to the provided time. All RTC implementations must be able + * to set their time based on a standard timespec. + * + * Input Parameters: + * tp - the time to use + * + * Returned Value: + * Zero (OK) on success; a negated errno on failure + * + ****************************************************************************/ + +int up_rtc_settime(const struct timespec *tp) +{ + struct tm newtime; + + /* Break out the time values + * (not that the time is set only to units of seconds) + */ + + gmtime_r(&tp->tv_sec, &newtime); + return stm32_rtc_setdatetime(&newtime); +} + +/**************************************************************************** + * Name: stm32_rtc_setalarm + * + * Description: + * Set up an alarm. + * Up to two alarms can be supported (ALARM A and ALARM B). + * + * Input Parameters: + * tp - the time to set the alarm + * callback - the function to call when the alarm expires. + * + * Returned Value: + * Zero (OK) on success; a negated errno on failure + * + ****************************************************************************/ + +#ifdef CONFIG_RTC_ALARM +int stm32_rtc_setalarm(const struct timespec *tp, alarmcb_t callback) +{ + int ret = -EBUSY; + + /* Is there already something waiting on the ALARM? */ + + if (g_alarmcb == NULL) + { + /* No.. Save the callback function pointer */ + + g_alarmcb = callback; + + /* Break out the time values */ + +#warning "Missing logic" + + /* The set the alarm */ + +#warning "Missing logic" + + ret = OK; + } + + return ret; +} +#endif + +#endif /* CONFIG_STM32_RTC */ diff --git a/arch/arm/src/common/stm32/stm32_rtcounter_m3m4_v1.c b/arch/arm/src/common/stm32/stm32_rtcounter_m3m4_v1.c new file mode 100644 index 0000000000000..6f5259e449806 --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_rtcounter_m3m4_v1.c @@ -0,0 +1,848 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_rtcounter_m3m4_v1.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* The STM32 RTC Driver offers standard precision of 1 Hz or High Resolution + * operating at rate up to 16384 Hz. It provides UTC time and alarm interface + * with external output pin (for wake-up). + * + * RTC is based on hardware RTC module which is located in a separate power + * domain. The 32-bit counter is extended by 16-bit registers in BKP domain + * STM32_BKP_DR1 to provide system equiv. function to the: time_t time + * (time_t *). + * + * Notation: + * - clock refers to 32-bit hardware counter + * - time is a combination of clock and upper bits stored in backuped domain + * with unit of 1 [s] + * + * TODO: + * Error Handling in case LSE fails during start-up or during operation. + */ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "arm_internal.h" +#include "stm32_pwr.h" +#include "stm32_rcc.h" +#include "stm32_rtc.h" +#include "stm32_waste.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* In hi-res mode, the RTC operates at 16384Hz. Overflow interrupts are + * handled when the 32-bit RTC counter overflows every 3 days and 43 minutes. + * A BKP register is incremented on each overflow interrupt creating, + * effectively, a 48-bit RTC counter. + * + * In the lo-res mode, the RTC operates at 1Hz. Overflow interrupts are not + * handled (because the next overflow is not expected until the year 2106). + * + * WARNING: + * Overflow interrupts are lost whenever the STM32 is powered down. The + * overflow interrupt may be lost even if the STM32 is powered down only + * momentarily. Therefore hi-res solution is only useful in systems where + * the power is always on. + */ + +#ifdef CONFIG_RTC_HIRES +# ifndef CONFIG_RTC_FREQUENCY +# error "CONFIG_RTC_FREQUENCY is required for CONFIG_RTC_HIRES" +# elif CONFIG_RTC_FREQUENCY != 16384 +# error "Only hi-res CONFIG_RTC_FREQUENCY of 16384Hz is supported" +# endif +#else +# ifndef CONFIG_RTC_FREQUENCY +# define CONFIG_RTC_FREQUENCY 1 +# endif +# if CONFIG_RTC_FREQUENCY != 1 +# error "Only lo-res CONFIG_RTC_FREQUENCY of 1Hz is supported" +# endif +#endif + +#ifndef CONFIG_STM32_BKP +# error "CONFIG_STM32_BKP is required for CONFIG_STM32_RTC" +#endif + +#ifndef CONFIG_STM32_PWR +# error "CONFIG_STM32_PWR is required for CONFIG_STM32_RTC" +#endif + +#ifdef CONFIG_STM32_STM32F10XX +# if defined(CONFIG_STM32_RTC_HSECLOCK) +# error "RTC with HSE clock not yet implemented for STM32F10XXX" +# elif defined(CONFIG_STM32_RTC_LSICLOCK) +# error "RTC with LSI clock not yet implemented for STM32F10XXX" +# endif +#endif + +/* RTC/BKP Definitions ******************************************************/ + +/* STM32_RTC_PRESCALAR_VALUE + * RTC pre-scalar value. The RTC is driven by a 32,768Hz input clock. + * This input value is divided by this value (plus one) to generate the + * RTC frequency. + * RTC_TIMEMSB_REG + * The BKP module register used to hold the RTC overflow value. + * Overflows are only handled in hi-res mode. + * RTC_CLOCKS_SHIFT + * The shift used to convert the hi-res timer LSB to one second. + * Not used with the lo-res timer. + */ + +#ifdef CONFIG_RTC_HIRES +# define STM32_RTC_PRESCALAR_VALUE STM32_RTC_PRESCALER_MIN +# define RTC_TIMEMSB_REG STM32_BKP_DR1 +# define RTC_CLOCKS_SHIFT 14 +#else +# define STM32_RTC_PRESCALAR_VALUE STM32_RTC_PRESCALER_SECOND +#endif + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +struct rtc_regvals_s +{ + uint16_t cntl; + uint16_t cnth; +#ifdef CONFIG_RTC_HIRES + uint16_t ovf; +#endif +}; + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static spinlock_t g_rtc_lock = SP_UNLOCKED; + +/* Callback to use when the alarm expires */ + +#ifdef CONFIG_RTC_ALARM +static alarmcb_t g_alarmcb; +#endif + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/* Variable determines the state of the LSE oscillator. + * Possible errors: + * - on start-up + * - during operation, reported by LSE interrupt + */ + +volatile bool g_rtc_enabled = false; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_rtc_waitlasttask + * + * Description: + * wait task done + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +static inline void stm32_rtc_waitlasttask(void) +{ + /* Previous write is done? */ + + while ((getreg16(STM32_RTC_CRL) & RTC_CRL_RTOFF) == 0) + { + stm32_waste(); + } +} + +/**************************************************************************** + * Name: stm32_rtc_beginwr + * + * Description: + * Enter configuration mode + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +static inline void stm32_rtc_beginwr(void) +{ + stm32_rtc_waitlasttask(); + + /* Enter Config mode, Set Value and Exit */ + + modifyreg16(STM32_RTC_CRL, 0, RTC_CRL_CNF); +} + +/**************************************************************************** + * Name: stm32_rtc_endwr + * + * Description: + * Exit configuration mode + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +static inline void stm32_rtc_endwr(void) +{ + modifyreg16(STM32_RTC_CRL, RTC_CRL_CNF, 0); + stm32_rtc_waitlasttask(); +} + +/**************************************************************************** + * Name: stm32_rtc_wait4rsf + * + * Description: + * Wait for registers to synchronise with RTC module, call after power-up + * only + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +static inline void stm32_rtc_wait4rsf(void) +{ + modifyreg16(STM32_RTC_CRL, RTC_CRL_RSF, 0); + while ((getreg16(STM32_RTC_CRL) & RTC_CRL_RSF) == 0) + { + stm32_waste(); + } +} + +/**************************************************************************** + * Name: stm32_rtc_breakout + * + * Description: + * Set the RTC to the provided time. + * + * Input Parameters: + * tp - the time to use + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_RTC_HIRES +static void stm32_rtc_breakout(const struct timespec *tp, + struct rtc_regvals_s *regvals) +{ + uint64_t frac; + uint32_t cnt; + uint16_t ovf; + + /* Break up the time in seconds + milleconds into the correct values for + * our use + */ + + frac = (tp->tv_nsec * CONFIG_RTC_FREQUENCY) / 1000000000; + cnt = (tp->tv_sec << RTC_CLOCKS_SHIFT) | + ((uint32_t)frac & (CONFIG_RTC_FREQUENCY - 1)); + ovf = (tp->tv_sec >> (32 - RTC_CLOCKS_SHIFT)); + + /* Then return the broken out time */ + + regvals->cnth = cnt >> 16; + regvals->cntl = cnt & 0xffff; + regvals->ovf = ovf; +} +#else +static inline void stm32_rtc_breakout(const struct timespec *tp, + struct rtc_regvals_s *regvals) +{ + /* The low-res timer is easy... tv_sec holds exactly the value needed + * by the CNTH/CNTL registers. + */ + + regvals->cnth = (uint16_t)((uint32_t)tp->tv_sec >> 16); + regvals->cntl = (uint16_t)((uint32_t)tp->tv_sec & 0xffff); +} +#endif + +/**************************************************************************** + * Name: stm32_rtc_interrupt + * + * Description: + * RTC interrupt service routine + * + * Input Parameters: + * irq - The IRQ number that generated the interrupt + * context - Architecture specific register save information. + * + * Returned Value: + * Zero (OK) on success; A negated errno value on failure. + * + ****************************************************************************/ + +#if defined(CONFIG_RTC_HIRES) || defined(CONFIG_RTC_ALARM) +static int stm32_rtc_interrupt(int irq, void *context, void *arg) +{ + uint16_t source = getreg16(STM32_RTC_CRL); + +#ifdef CONFIG_RTC_HIRES + if ((source & RTC_CRL_OWF) != 0) + { + stm32_pwr_enablebkp(true); + putreg16(getreg16(RTC_TIMEMSB_REG) + 1, RTC_TIMEMSB_REG); + stm32_pwr_enablebkp(false); + } +#endif + +#ifdef CONFIG_RTC_ALARM + if ((source & RTC_CRL_ALRF) != 0 && g_alarmcb != NULL) + { + /* Alarm callback */ + + g_alarmcb(); + g_alarmcb = NULL; + } +#endif + + /* Clear pending flags, leave RSF high */ + + putreg16(RTC_CRL_RSF, STM32_RTC_CRL); + return 0; +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_rtc_initialize + * + * Description: + * Initialize the hardware RTC per the selected configuration. + * This function is called once during the OS initialization sequence + * + * Input Parameters: + * None + * + * Returned Value: + * Zero (OK) on success; a negated errno on failure + * + ****************************************************************************/ + +int up_rtc_initialize(void) +{ + uint32_t regval; + + /* Enable write access to the backup domain (RTC registers, RTC backup data + * registers and backup SRAM). + */ + + stm32_pwr_enablebkp(true); + + regval = getreg32(RTC_MAGIC_REG); + if (regval != RTC_MAGIC && regval != RTC_MAGIC_TIME_SET) + { + /* Reset backup domain if bad magic */ + + modifyreg32(STM32_RCC_BDCR, 0, RCC_BDCR_BDRST); + modifyreg32(STM32_RCC_BDCR, RCC_BDCR_BDRST, 0); + + modifyreg16(STM32_RCC_BDCR, 0, RCC_BDCR_LSEON); + + /* Wait for the LSE clock to be ready */ + + while ((getreg16(STM32_RCC_BDCR) & RCC_BDCR_LSERDY) == 0) + { + stm32_waste(); + } + + /* Select the lower power external 32,768Hz (Low-Speed External, LSE) + * oscillator as RTC Clock Source and enable the Clock. + */ + + modifyreg16(STM32_RCC_BDCR, RCC_BDCR_RTCSEL_MASK, RCC_BDCR_RTCSEL_LSE); + + /* Enable RTC and wait for RSF */ + + modifyreg16(STM32_RCC_BDCR, 0, RCC_BDCR_RTCEN); + stm32_rtc_waitlasttask(); + + stm32_rtc_wait4rsf(); + stm32_rtc_waitlasttask(); + + /* Configure prescaler, note that these are write-only registers */ + + stm32_rtc_beginwr(); + putreg16(STM32_RTC_PRESCALAR_VALUE >> 16, STM32_RTC_PRLH); + putreg16(STM32_RTC_PRESCALAR_VALUE & 0xffff, STM32_RTC_PRLL); + stm32_rtc_endwr(); + + stm32_rtc_wait4rsf(); + stm32_rtc_waitlasttask(); + + /* Write the magic register after RTC initialization. */ + + putreg16(RTC_MAGIC, RTC_MAGIC_REG); + } + +#ifdef CONFIG_RTC_HIRES + /* Enable overflow interrupt - alarm interrupt is enabled in + * stm32_rtc_setalarm. + */ + + modifyreg16(STM32_RTC_CRH, 0, RTC_CRH_OWIE); +#endif + + /* TODO: Get state from this function, if everything is + * okay and whether it is already enabled (if it was disabled + * reset upper time register) + */ + + g_rtc_enabled = true; + + /* Alarm Int via EXTI Line */ + + /* STM32_IRQ_RTCALRM 41: RTC alarm through EXTI line interrupt */ + + /* Disable write access to the backup domain + * (RTC registers, RTC backup data registers and backup SRAM). + */ + + stm32_pwr_enablebkp(false); + + return OK; +} + +/**************************************************************************** + * Name: stm32_rtc_irqinitialize + * + * Description: + * Initialize IRQs for RTC, not possible during up_rtc_initialize because + * up_irqinitialize is called later. + * + * Input Parameters: + * None + * + * Returned Value: + * Zero (OK) on success; a negated errno on failure + * + ****************************************************************************/ + +int stm32_rtc_irqinitialize(void) +{ +#if defined(CONFIG_RTC_HIRES) || defined(CONFIG_RTC_ALARM) + /* Configure RTC interrupt to catch overflow and alarm interrupts. */ + + irq_attach(STM32_IRQ_RTC, stm32_rtc_interrupt, NULL); + up_enable_irq(STM32_IRQ_RTC); +#endif + + return OK; +} + +/**************************************************************************** + * Name: up_rtc_time + * + * Description: + * Get the current time in seconds. + * This is similar to the standard time() function. + * This interface is only required if the low-resolution RTC/counter + * hardware implementation selected. It is only used by the RTOS during + * initialization to set up the system time when CONFIG_RTC is set but + * neither CONFIG_RTC_HIRES nor CONFIG_RTC_DATETIME are set. + * + * Input Parameters: + * None + * + * Returned Value: + * The current time in seconds + * + ****************************************************************************/ + +#ifndef CONFIG_RTC_HIRES +time_t up_rtc_time(void) +{ + irqstate_t flags; + uint16_t cnth; + uint16_t cntl; + uint16_t tmp; + + /* The RTC counter is read from two 16-bit registers to form one 32-bit + * value. Because these are non-atomic operations, many things can happen + * between the two reads: This thread could get suspended or interrupted + * or the lower 16-bit counter could rollover between reads. Disabling + * interrupts will prevent suspensions and interruptions: + */ + + flags = spin_lock_irqsave(&g_rtc_lock); + + /* And the following loop will handle any clock rollover events that may + * happen between samples. Most of the time (like 99.9%), the following + * loop will execute only once. In the rare rollover case, it should + * execute no more than 2 times. + */ + + do + { + tmp = getreg16(STM32_RTC_CNTL); + cnth = getreg16(STM32_RTC_CNTH); + cntl = getreg16(STM32_RTC_CNTL); + } + + /* The second sample of CNTL could be less than the first sample of CNTL + * only if rollover occurred. In that case, CNTH may or may not be out + * of sync. The best thing to do is try again until we know that no + * rollover occurred. + */ + + while (cntl < tmp); + spin_unlock_irqrestore(&g_rtc_lock, flags); + + /* Okay.. the samples should be as close together in time as possible and + * we can be assured that no clock rollover occurred between the samples. + * + * Return the time in seconds. + */ + + return (time_t)cnth << 16 | (time_t)cntl; +} +#endif + +/**************************************************************************** + * Name: up_rtc_gettime + * + * Description: + * Get the current time from the high resolution RTC clock/counter. This + * interface is only supported by the high-resolution RTC/counter hardware + * implementation. + * It is used to replace the system timer. + * + * Input Parameters: + * tp - The location to return the high resolution time value. + * + * Returned Value: + * Zero (OK) on success; a negated errno on failure + * + ****************************************************************************/ + +#ifdef CONFIG_RTC_HIRES +int up_rtc_gettime(struct timespec *tp) +{ + irqstate_t flags; + uint32_t ls; + uint32_t ms; + uint16_t ovf; + uint16_t cnth; + uint16_t cntl; + uint16_t tmp; + + /* The RTC counter is read from two 16-bit registers to form one 32-bit + * value. Because these are non-atomic operations, many things can happen + * between the two reads: This thread could get suspended or interrupted + * or the lower 16-bit counter could rollover between reads. Disabling + * interrupts will prevent suspensions and interruptions: + */ + + flags = spin_lock_irqsave(&g_rtc_lock); + + /* And the following loop will handle any clock rollover events that may + * happen between samples. Most of the time (like 99.9%), the following + * loop will execute only once. In the rare rollover case, it should + * execute no more than 2 times. + */ + + do + { + tmp = getreg16(STM32_RTC_CNTL); + cnth = getreg16(STM32_RTC_CNTH); + ovf = getreg16(RTC_TIMEMSB_REG); + cntl = getreg16(STM32_RTC_CNTL); + } + + /* The second sample of CNTL could be less than the first sample of CNTL + * only if rollover occurred. In that case, CNTH may or may not be out + * of sync. The best thing to do is try again until we know that no + * rollover occurred. + */ + + while (cntl < tmp); + spin_unlock_irqrestore(&g_rtc_lock, flags); + + /* Okay.. the samples should be as close together in time as possible and + * we can be assured that no clock rollover occurred between the samples. + * + * Create a 32-bit value from the LS and MS 16-bit RTC counter values and + * from the MS and overflow 16-bit counter values. + */ + + ls = (uint32_t)cnth << 16 | (uint32_t)cntl; + ms = (uint32_t)ovf << 16 | (uint32_t)cnth; + + /* Then we can save the time in seconds and fractional seconds. */ + + tp->tv_sec = (ms << (32 - RTC_CLOCKS_SHIFT - 16)) | + (ls >> (RTC_CLOCKS_SHIFT + 16)); + tp->tv_nsec = (ls & (CONFIG_RTC_FREQUENCY - 1)) * + (1000000000 / CONFIG_RTC_FREQUENCY); + return OK; +} +#endif + +/**************************************************************************** + * Name: up_rtc_settime + * + * Description: + * Set the RTC to the provided time. All RTC implementations must be able + * to set their time based on a standard timespec. + * + * Input Parameters: + * tp - the time to use + * + * Returned Value: + * Zero (OK) on success; a negated errno on failure + * + ****************************************************************************/ + +int up_rtc_settime(const struct timespec *tp) +{ + struct rtc_regvals_s regvals; + irqstate_t flags; + + /* Break out the time values */ + + stm32_rtc_breakout(tp, ®vals); + + /* Enable write access to the backup domain */ + + flags = spin_lock_irqsave(&g_rtc_lock); + stm32_pwr_enablebkp(true); + + /* Then write the broken out values to the RTC counter and BKP overflow + * register (hi-res mode only) + */ + + stm32_rtc_beginwr(); + putreg16(regvals.cnth, STM32_RTC_CNTH); + putreg16(regvals.cntl, STM32_RTC_CNTL); + stm32_rtc_endwr(); + putreg16(RTC_MAGIC_TIME_SET, RTC_MAGIC_REG); + +#ifdef CONFIG_RTC_HIRES + putreg16(regvals.ovf, RTC_TIMEMSB_REG); +#endif + + stm32_pwr_enablebkp(false); + spin_unlock_irqrestore(&g_rtc_lock, flags); + return OK; +} + +/**************************************************************************** + * Name: stm32_rtc_setalarm + * + * Description: + * Set up an alarm. + * + * Input Parameters: + * tp - the time to set the alarm + * callback - the function to call when the alarm expires. + * + * Returned Value: + * Zero (OK) on success; a negated errno on failure + * + ****************************************************************************/ + +#ifdef CONFIG_RTC_ALARM +int stm32_rtc_setalarm(const struct timespec *tp, alarmcb_t callback) +{ + struct rtc_regvals_s regvals; + irqstate_t flags; + uint16_t cr; + int ret = -EBUSY; + + flags = spin_lock_irqsave(&g_rtc_lock); + + /* Is there already something waiting on the ALARM? */ + + if (g_alarmcb == NULL) + { + /* No.. Save the callback function pointer */ + + g_alarmcb = callback; + + /* Break out the time values */ + + stm32_rtc_breakout(tp, ®vals); + + stm32_pwr_enablebkp(true); + + /* Enable RTC alarm */ + + cr = getreg16(STM32_RTC_CRH); + cr |= RTC_CRH_ALRIE; + putreg16(cr, STM32_RTC_CRH); + + /* The set the alarm */ + + stm32_rtc_beginwr(); + putreg16(regvals.cnth, STM32_RTC_ALRH); + putreg16(regvals.cntl, STM32_RTC_ALRL); + stm32_rtc_endwr(); + + stm32_pwr_enablebkp(false); + + ret = OK; + } + + spin_unlock_irqrestore(&g_rtc_lock, flags); + + return ret; +} +#endif + +/**************************************************************************** + * Name: stm32_rtc_cancelalarm + * + * Description: + * Cancel a pending alarm alarm + * + * Input Parameters: + * none + * + * Returned Value: + * Zero (OK) on success; a negated errno on failure + * + ****************************************************************************/ + +#ifdef CONFIG_RTC_ALARM +int stm32_rtc_cancelalarm(void) +{ + irqstate_t flags; + int ret = -ENODATA; + + flags = spin_lock_irqsave(&g_rtc_lock); + + if (g_alarmcb != NULL) + { + /* Cancel the global callback function */ + + g_alarmcb = NULL; + + /* Unset the alarm */ + + stm32_pwr_enablebkp(true); + stm32_rtc_beginwr(); + putreg16(0xffff, STM32_RTC_ALRH); + putreg16(0xffff, STM32_RTC_ALRL); + stm32_rtc_endwr(); + stm32_pwr_enablebkp(false); + + ret = OK; + } + + spin_unlock_irqrestore(&g_rtc_lock, flags); + + return ret; +} +#endif + +/**************************************************************************** + * Name: stm32_rtc_rdalarm + * + * Description: + * Query an alarm configured in hardware. + * + * Input Parameters: + * alminfo - Information about the alarm configuration. + * + * Returned Value: + * Zero (OK) on success; a negated errno on failure + * + ****************************************************************************/ + +#ifdef CONFIG_RTC_ALARM +int stm32_rtc_rdalarm(FAR struct alm_rdalarm_s *alminfo) +{ + struct rtc_regvals_s regvals; + FAR struct timespec tp; + int ret = -EINVAL; + + DEBUGASSERT(alminfo != NULL); + DEBUGASSERT(alminfo->ar_id == 0); + + switch (alminfo->ar_id) + { + case 0: + { + regvals.cnth = getreg16(STM32_RTC_ALRH); + regvals.cntl = getreg16(STM32_RTC_ALRL); + tp.tv_sec = regvals.cnth << 16 | regvals.cntl; + memcpy(alminfo->ar_time, gmtime(&tp.tv_sec), + sizeof(struct tm)); + ret = OK; + } + break; + + default: + rtcerr("ERROR: Invalid ALARM%d\n", alminfo->ar_id); + break; + } + + return ret; +} +#endif diff --git a/arch/arm/src/common/stm32/stm32_sdadc.h b/arch/arm/src/common/stm32/stm32_sdadc.h new file mode 100644 index 0000000000000..f69f80d1d56de --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_sdadc.h @@ -0,0 +1,38 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_sdadc.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_COMPAT_STM32SDADC_H +#define __ARCH_ARM_SRC_COMMON_COMPAT_STM32SDADC_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#if defined(CONFIG_STM32_HAVE_IP_SDADC_M3M4_V1) +# include "stm32_sdadc_m3m4_v1.h" +#else +# error "Unsupported STM32 stm32_sdadc" +#endif + +#endif /* __ARCH_ARM_SRC_COMMON_COMPAT_STM32SDADC_H */ diff --git a/arch/arm/src/common/stm32/stm32_sdadc_m3m4_v1.c b/arch/arm/src/common/stm32/stm32_sdadc_m3m4_v1.c new file mode 100644 index 0000000000000..23e5fc8a33f22 --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_sdadc_m3m4_v1.c @@ -0,0 +1,1410 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_sdadc_m3m4_v1.c + * + * SPDX-License-Identifier: BSD-3-Clause + * SPDX-FileCopyrightText: 2015-2017 Gregory Nutt. All rights reserved. + * SPDX-FileCopyrightText: 2009, 2011 Gregory Nutt. All rights reserved. + * SPDX-FileCopyrightText: 2016 Studelec. All rights reserved. + * SPDX-FileContributor: Gregory Nutt + * SPDX-FileContributor: Marc Rechté + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include "arm_internal.h" +#include "chip.h" +#include "stm32.h" +#include "stm32_dma.h" +#include "stm32_sdadc_m3m4_v1.h" +#include "stm32_pwr.h" +#include "stm32_dma.h" +#include "stm32_sdadc_m3m4_v1.h" + +#ifdef CONFIG_STM32_SDADC + +/* Some SDADC peripheral must be enabled */ + +#if defined(CONFIG_STM32_SDADC1) || defined(CONFIG_STM32_SDADC2) || \ + defined(CONFIG_STM32_SDADC3) + +/* This implementation is for the STM32F37XX only */ + +#ifndef CONFIG_STM32_STM32F37XX +# error "This chip is not yet supported" +#endif + +/* TODO: At the moment there is no implementation + * for timer and external triggers + */ + +#if defined(SDADC_HAVE_TIMER) +# error "There is no proper implementation for TIMER TRIGGERS at the moment" +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* RCC reset ****************************************************************/ + +#define STM32_RCC_RSTR STM32_RCC_APB2RSTR +#define RCC_RSTR_SDADC1RST RCC_APB2RSTR_SDADC1RST +#define RCC_RSTR_SDADC2RST RCC_APB2RSTR_SDADC2RST +#define RCC_RSTR_SDADC3RST RCC_APB2RSTR_SDADC3RST + +/* SDADC interrupts *********************************************************/ + +#define SDADC_ISR_ALLINTS (SDADC_ISR_JEOCF | SDADC_ISR_JOVRF) + +/* SDADC Channels/DMA *******************************************************/ + +#define SDADC_DMA_CONTROL_WORD (DMA_CCR_MSIZE_16BITS | \ + DMA_CCR_PSIZE_16BITS | \ + DMA_CCR_MINC | \ + DMA_CCR_CIRC) + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/* This structure describes the state of one SDADC block */ + +struct stm32_dev_s +{ + const struct adc_callback_s *cb; + uint8_t irq; /* Interrupt generated by this SDADC block */ + uint8_t nchannels; /* Number of channels */ + uint8_t cchannels; /* Number of configured channels */ + uint8_t intf; /* SDADC interface number */ + uint8_t current; /* Current SDADC channel being converted */ + uint8_t refv; /* Reference voltage selection */ +#ifdef SDADC_HAVE_DMA + uint8_t dmachan; /* DMA channel needed by this SDADC */ + bool hasdma; /* True: This channel supports DMA */ +#endif +#ifdef SDADC_HAVE_TIMER + uint8_t trigger; /* Timer trigger selection: see SDADCx_JEXTSEL_TIMxx */ +#endif + uint32_t base; /* Base address of registers unique to this SDADC + * block */ +#ifdef SDADC_HAVE_TIMER + uint32_t tbase; /* Base address of timer used by this SDADC block */ + uint32_t jextsel; /* JEXTSEL value used by this SDADC block */ + uint32_t pclck; /* The PCLK frequency that drives this timer */ + uint32_t freq; /* The desired frequency of conversions */ +#endif +#ifdef SDADC_HAVE_DMA + DMA_HANDLE dma; /* Allocated DMA channel */ + + /* DMA transfer buffer */ + + int16_t dmabuffer[SDADC_MAX_SAMPLES]; +#endif + + /* List of selected SDADC injected channels to sample */ + + uint8_t chanlist[SDADC_MAX_SAMPLES]; +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/* ADC Register access */ + +static uint32_t sdadc_getreg(struct stm32_dev_s *priv, int offset); +static void sdadc_putreg(struct stm32_dev_s *priv, int offset, + uint32_t value); +static void sdadc_modifyreg(struct stm32_dev_s *priv, int offset, + uint32_t clrbits, uint32_t setbits); +#ifdef ADC_HAVE_TIMER +static uint16_t tim_getreg(struct stm32_dev_s *priv, int offset); +static void tim_putreg(struct stm32_dev_s *priv, int offset, + uint16_t value); +static void tim_modifyreg(struct stm32_dev_s *priv, int offset, + uint16_t clrbits, uint16_t setbits); +static void tim_dumpregs(struct stm32_dev_s *priv, + const char *msg); +#endif + +static void sdadc_rccreset(struct stm32_dev_s *priv, bool reset); + +/* ADC Interrupt Handler */ + +static int sdadc_interrupt(int irq, void *context, void *arg); + +/* ADC Driver Methods */ + +static int sdadc_bind(struct adc_dev_s *dev, + const struct adc_callback_s *callback); +static void sdadc_reset(struct adc_dev_s *dev); +static int sdadc_setup(struct adc_dev_s *dev); +static void sdadc_shutdown(struct adc_dev_s *dev); +static void sdadc_rxint(struct adc_dev_s *dev, bool enable); +static int sdadc_ioctl(struct adc_dev_s *dev, int cmd, + unsigned long arg); +static void sdadc_enable(struct stm32_dev_s *priv, bool enable); + +static int sdadc_set_ch(struct adc_dev_s *dev, uint8_t ch); + +#ifdef ADC_HAVE_TIMER +static void sdadc_timstart(struct stm32_dev_s *priv, bool enable); +static int sdadc_timinit(struct stm32_dev_s *priv); +#endif + +#ifdef ADC_HAVE_DMA +static void sdadc_dmaconvcallback(DMA_HANDLE handle, uint8_t isr, + void *arg); +#endif + +static void sdadc_startconv(struct stm32_dev_s *priv, bool enable); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* SDADC interface operations */ + +static const struct adc_ops_s g_sdadcops = +{ + .ao_bind = sdadc_bind, + .ao_reset = sdadc_reset, + .ao_setup = sdadc_setup, + .ao_shutdown = sdadc_shutdown, + .ao_rxint = sdadc_rxint, + .ao_ioctl = sdadc_ioctl, +}; + +/* SDADC1 state */ + +#ifdef CONFIG_STM32_SDADC1 +static struct stm32_dev_s g_sdadcpriv1 = +{ + .irq = STM32_IRQ_SDADC1, + .intf = 1, + .base = STM32_SDADC1_BASE, + .refv = SDADC1_REFV, +#ifdef SDADC1_HAVE_TIMER + .trigger = CONFIG_STM32_SDADC1_TIMTRIG, + .tbase = SDADC1_TIMER_BASE, + .extsel = SDADC1_EXTSEL_VALUE, + .pclck = SDADC1_TIMER_PCLK_FREQUENCY, + .freq = CONFIG_STM32_SDADC1_SAMPLE_FREQUENCY, +#endif +#ifdef SDADC1_HAVE_DMA + .dmachan = DMACHAN_SDADC1, + .hasdma = true, +#endif +}; + +static struct adc_dev_s g_sdadcdev1 = +{ + .ad_ops = &g_sdadcops, + .ad_priv = &g_sdadcpriv1, +}; +#endif + +/* SDADC2 state */ + +#ifdef CONFIG_STM32_SDADC2 +static struct stm32_dev_s g_sdadcpriv2 = +{ + .irq = STM32_IRQ_SDADC2, + .base = STM32_SDADC2_BASE, + .refv = SDADC2_REFV, +#ifdef SDADC2_HAVE_TIMER + .trigger = CONFIG_STM32_SDADC2_TIMTRIG, + .tbase = SDADC2_TIMER_BASE, + .extsel = SDADC2_EXTSEL_VALUE, + .pclck = SDADC2_TIMER_PCLK_FREQUENCY, + .freq = CONFIG_STM32_SDADC2_SAMPLE_FREQUENCY, +#endif +#ifdef SDADC2_HAVE_DMA + .dmachan = DMACHAN_SDADC2, + .hasdma = true, +#endif +}; + +static struct adc_dev_s g_sdadcdev2 = +{ + .ad_ops = &g_sdadcops, + .ad_priv = &g_sdadcpriv2, +}; +#endif + +/* SDADC3 state */ + +#ifdef CONFIG_STM32_SDADC3 +static struct stm32_dev_s g_sdadcpriv3 = +{ + .irq = STM32_IRQ_SDADC3, + .base = STM32_SDADC3_BASE, + .refv = SDADC3_REFV, +#ifdef SDADC3_HAVE_TIMER + .trigger = CONFIG_STM32_SDADC3_TIMTRIG, + .tbase = SDADC3_TIMER_BASE, + .extsel = SDADC3_EXTSEL_VALUE, + .pclck = SDADC3_TIMER_PCLK_FREQUENCY, + .freq = CONFIG_STM32_SDADC3_SAMPLE_FREQUENCY, +#endif +#ifdef SDADC3_HAVE_DMA + .dmachan = DMACHAN_SDADC3, + .hasdma = true, +#endif +}; + +static struct adc_dev_s g_sdadcdev3 = +{ + .ad_ops = &g_sdadcops, + .ad_priv = &g_sdadcpriv3, +}; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: sdadc_getreg + * + * Description: + * Read the value of an SDADC register. + * + * Input Parameters: + * priv - A reference to the SDADC block state + * offset - The offset to the register to read + * + * Returned Value: + * The current contents of the specified register + * + ****************************************************************************/ + +static uint32_t sdadc_getreg(struct stm32_dev_s *priv, int offset) +{ + return getreg32(priv->base + offset); +} + +/**************************************************************************** + * Name: sdadc_putreg + * + * Description: + * Write a value to an SDADC register. + * + * Input Parameters: + * priv - A reference to the SDADC block state + * offset - The offset to the register to write to + * value - The value to write to the register + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void sdadc_putreg(struct stm32_dev_s *priv, int offset, + uint32_t value) +{ + putreg32(value, priv->base + offset); +} + +/**************************************************************************** + * Name: sdadc_modifyreg + * + * Description: + * Modify the value of an SDADC register (not atomic). + * + * Input Parameters: + * priv - A reference to the SDADC block state + * offset - The offset to the register to modify + * clrbits - The bits to clear + * setbits - The bits to set + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void sdadc_modifyreg(struct stm32_dev_s *priv, int offset, + uint32_t clrbits, uint32_t setbits) +{ + sdadc_putreg(priv, offset, + (sdadc_getreg(priv, offset) & ~clrbits) | setbits); +} + +/**************************************************************************** + * Name: tim_getreg + * + * Description: + * Read the value of an SDADC timer register. + * + * Input Parameters: + * priv - A reference to the SDADC block state + * offset - The offset to the register to read + * + * Returned Value: + * The current contents of the specified register + * + ****************************************************************************/ + +#ifdef SDADC_HAVE_TIMER +static uint16_t tim_getreg(struct stm32_dev_s *priv, int offset) +{ + return getreg16(priv->tbase + offset); +} +#endif + +/**************************************************************************** + * Name: tim_putreg + * + * Description: + * Write a value to an SDADC timer register. + * + * Input Parameters: + * priv - A reference to the SDADC block state + * offset - The offset to the register to write to + * value - The value to write to the register + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef SDADC_HAVE_TIMER +static void tim_putreg(struct stm32_dev_s *priv, int offset, + uint16_t value) +{ + putreg16(value, priv->tbase + offset); +} +#endif + +/**************************************************************************** + * Name: tim_modifyreg + * + * Description: + * Modify the value of an SDADC timer register (not atomic). + * + * Input Parameters: + * priv - A reference to the SDADC block state + * offset - The offset to the register to modify + * clrbits - The bits to clear + * setbits - The bits to set + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef SDADC_HAVE_TIMER +static void tim_modifyreg(struct stm32_dev_s *priv, int offset, + uint16_t clrbits, uint16_t setbits) +{ + tim_putreg(priv, offset, (tim_getreg(priv, offset) & ~clrbits) | setbits); +} +#endif + +/**************************************************************************** + * Name: tim_dumpregs + * + * Description: + * Dump all timer registers. + * + * Input Parameters: + * priv - A reference to the SDADC block state + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef SDADC_HAVE_TIMER +static void tim_dumpregs(struct stm32_dev_s *priv, const char *msg) +{ + ainfo("%s:\n", msg); + + /* TODO */ +} +#endif + +/**************************************************************************** + * Name: sdadc_timstart + * + * Description: + * Start (or stop) the timer counter + * + * Input Parameters: + * priv - A reference to the SDADC block state + * enable - True: Start conversion + * + * Returned Value: + * + ****************************************************************************/ + +#ifdef SDADC_HAVE_TIMER +static void sdadc_timstart(struct stm32_dev_s *priv, bool enable) +{ + ainfo("enable: %d\n", enable ? 1 : 0); + + if (enable) + { + /* Start the counter */ + + tim_modifyreg(priv, STM32_GTIM_CR1_OFFSET, 0, GTIM_CR1_CEN); + } + else + { + /* Disable the counter */ + + tim_modifyreg(priv, STM32_GTIM_CR1_OFFSET, GTIM_CR1_CEN, 0); + } +} +#endif + +/**************************************************************************** + * Name: sdadc_timinit + * + * Description: + * Initialize the timer that drivers the SDADC sampling for this channel + * using the pre-calculated timer divider definitions. + * + * Input Parameters: + * priv - A reference to the SDADC block state + * + * Returned Value: + * Zero on success; a negated errno value on failure. + * + ****************************************************************************/ + +#ifdef SDADC_HAVE_TIMER +static int sdadc_timinit(struct stm32_dev_s *priv) +{ + /* TODO */ + + aerr("ERROR: not implemented"); + return ERROR; +} +#endif + +/**************************************************************************** + * Name: sdadc_startconv + * + * Description: + * Start (or stop) the SDADC conversion process + * + * Input Parameters: + * priv - A reference to the SDADC block state + * enable - True: Start conversion + * + * Returned Value: + * + ****************************************************************************/ + +static void sdadc_startconv(struct stm32_dev_s *priv, bool enable) +{ + ainfo("enable: %d\n", enable ? 1 : 0); + + if (enable) + { + /* Start the conversion of injected channels */ + + sdadc_modifyreg(priv, STM32_SDADC_CR2_OFFSET, 0, SDADC_CR2_JSWSTART); + } + else + { + /* Wait for a possible conversion to stop */ + + while ((sdadc_getreg(priv, + STM32_SDADC_ISR_OFFSET) & SDADC_ISR_JCIP) != 0); + } +} + +/**************************************************************************** + * Name: sdadc_rccreset + * + * Description: + * (De)Initializes the SDADC block registers to their default + * reset values. + * + * Input Parameters: + * priv - A reference to the SDADC block state + * reset - true: to put in reset state, false: to revert to normal state + * + * Returned Value: + * + ****************************************************************************/ + +static void sdadc_rccreset(struct stm32_dev_s *priv, bool reset) +{ + uint32_t adcbit; + + /* Pick the appropriate bit in the APB2 reset register. + */ + + switch (priv->intf) + { +#ifdef CONFIG_STM32_SDADC1 + case 1: + adcbit = RCC_RSTR_SDADC1RST; + break; +#endif +#ifdef CONFIG_STM32_SDADC2 + case 2: + adcbit = RCC_RSTR_SDADC2RST; + break; +#endif +#ifdef CONFIG_STM32_SDADC3 + case 3: + adcbit = RCC_RSTR_SDADC3RST; + break; +#endif + default: + return; + } + + /* Set or clear the selected bit in the APB2 reset register. + * modifyreg32() disables interrupts. Disabling interrupts is necessary + * because the APB2RSTR register is used by several different drivers. + */ + + if (reset) + { + /* Enable SDADC reset state */ + + modifyreg32(STM32_RCC_RSTR, 0, adcbit); + } + else + { + /* Release SDADC from reset state */ + + modifyreg32(STM32_RCC_RSTR, adcbit, 0); + } +} + +/**************************************************************************** + * Name: sdadc_power_down_idle + * + * Description: + * Enables or disables power down during the idle phase. + * + * Input Parameters: + * priv - A reference to the SDADC block state + * pdi_high - true: The SDADC is powered down when waiting for a start + * event + * false: The SDADC is powered up when waiting for a start event + * + * Returned Value: + * None. + * + ****************************************************************************/ + +#if 0 +static void sdadc_power_down_idle(struct stm32_dev_s *priv, + bool pdi_high) +{ + uint32_t regval; + + ainfo("PDI: %d\n", pdi_high ? 1 : 0); + + regval = sdadc_getreg(priv, STM32_SDADC_CR2_OFFSET); + + if ((regval & SDADC_CR2_ADON) == 0) + { + regval = sdadc_getreg(priv, STM32_SDADC_CR1_OFFSET); + if (pdi_high) + { + regval |= SDADC_CR1_PDI; + } + else + { + regval &= ~SDADC_CR1_PDI; + } + + sdadc_putreg(priv, STM32_SDADC_CR1_OFFSET, regval); + } +} +#endif + +/**************************************************************************** + * Name: sdadc_enable + * + * Description: + * Enables or disables the specified SDADC peripheral. + * Does not start conversion unless the SDADC is + * triggered by timer + * + * Input Parameters: + * priv - A reference to the SDADC block state + * enable - true: enable SDADC conversion + * false: disable SDADC conversion + * + * Returned Value: + * + ****************************************************************************/ + +static void sdadc_enable(struct stm32_dev_s *priv, bool enable) +{ + uint32_t regval; + + ainfo("enable: %d\n", enable ? 1 : 0); + + regval = sdadc_getreg(priv, STM32_SDADC_CR2_OFFSET); + + if (enable) + { + /* Enable the SDADC */ + + sdadc_putreg(priv, STM32_SDADC_CR2_OFFSET, regval | SDADC_CR2_ADON); + + /* Wait for the SDADC to be stabilized */ + + while (sdadc_getreg(priv, STM32_SDADC_ISR_OFFSET) & SDADC_ISR_STABIP); + } + else if ((regval & SDADC_CR2_ADON) != 0) + { + /* Ongoing conversions will be stopped implicitly */ + + /* Disable the SDADC */ + + sdadc_putreg(priv, STM32_SDADC_CR2_OFFSET, regval & ~SDADC_CR2_ADON); + } +} + +/**************************************************************************** + * Name: sdadc_dmaconvcallback + * + * Description: + * Callback for DMA. Called from the DMA transfer complete interrupt after + * all channels have been converted and transferred with DMA. + * + * Input Parameters: + * handle - handle to DMA + * isr - + * arg - SDADC device + * + * Returned Value: + * + ****************************************************************************/ + +#ifdef SDADC_HAVE_DMA +static void sdadc_dmaconvcallback(DMA_HANDLE handle, + uint8_t isr, void *arg) +{ + struct adc_dev_s *dev = (struct adc_dev_s *)arg; + struct stm32_dev_s *priv = (struct stm32_dev_s *)dev->ad_priv; + int i; + + /* Verify that the upper-half driver has bound its callback functions */ + + if (priv->cb != NULL) + { + DEBUGASSERT(priv->cb->au_receive != NULL); + + for (i = 0; i < priv->nchannels; i++) + { + priv->cb->au_receive(dev, priv->chanlist[priv->current], + priv->dmabuffer[priv->current]); + priv->current++; + if (priv->current >= priv->nchannels) + { + /* Restart the conversion sequence from the beginning */ + + priv->current = 0; + } + } + } +} +#endif + +/**************************************************************************** + * Name: sdadc_bind + * + * Description: + * Bind the upper-half driver callbacks to the lower-half implementation. + * This must be called early in order to receive SDADC event notifications. + * + ****************************************************************************/ + +static int sdadc_bind(struct adc_dev_s *dev, + const struct adc_callback_s *callback) +{ + struct stm32_dev_s *priv = (struct stm32_dev_s *)dev->ad_priv; + + DEBUGASSERT(priv != NULL); + priv->cb = callback; + return OK; +} + +/**************************************************************************** + * Name: sdadc_reset + * + * Description: + * Reset the SDADC device. + * This is firstly called whenever the SDADC device is registered by + * sdadc_register() + * Does mostly the SDAC register setting. + * Leave the device in power down mode. + * Note that SDACx clock is already enable (for all SDADC) by the + * rcc_enableapb2() + * + * Input Parameters: + * dev - pointer to the sdadc device structure + * + * Returned Value: + * + ****************************************************************************/ + +static void sdadc_reset(struct adc_dev_s *dev) +{ + struct stm32_dev_s *priv = (struct stm32_dev_s *)dev->ad_priv; + irqstate_t flags; + uint32_t setbits = 0; + + ainfo("intf: %d\n", priv->intf); + + /* TODO: why critical ? */ + + flags = enter_critical_section(); + + /* Enable SDADC reset state */ + + sdadc_rccreset(priv, true); + + /* Enable power */ + + stm32_pwr_enablesdadc(priv->intf); + + /* Release SDADC from reset state */ + + sdadc_rccreset(priv, false); + + /* Enable the SDADC (and wait until it stabilizes) */ + + sdadc_enable(priv, true); + + /* Put SDADC in in initialization mode */ + + sdadc_putreg(priv, STM32_SDADC_CR1_OFFSET, SDADC_CR1_INIT); + + /* Wait for the SDADC to be ready */ + + while ((sdadc_getreg(priv, + STM32_SDADC_ISR_OFFSET) & + SDADC_ISR_INITRDY) == 0); + + /* Load configurations */ + + sdadc_putreg(priv, STM32_SDADC_CONF0R_OFFSET, SDADC_CONF0R_DEFAULT); + sdadc_putreg(priv, STM32_SDADC_CONF1R_OFFSET, SDADC_CONF1R_DEFAULT); + sdadc_putreg(priv, STM32_SDADC_CONF2R_OFFSET, SDADC_CONF2R_DEFAULT); + + sdadc_putreg(priv, STM32_SDADC_CONFCHR1_OFFSET, SDADC_CONFCHR1_DEFAULT); + sdadc_putreg(priv, STM32_SDADC_CONFCHR2_OFFSET, SDADC_CONFCHR2_DEFAULT); + + /* Configuration of the injected channels group */ + + sdadc_set_ch(dev, 0); + + /* CR1 ********************************************************************/ + + /* Enable interrupt / dma flags, is done later by upper half when opening + * device by calling sdadc_rxint() + */ + + setbits = SDADC_CR1_INIT; /* remains in init mode while configuring */ + + /* Reference voltage */ + + setbits |= priv->refv; + + /* Set CR1 configuration */ + + sdadc_putreg(priv, STM32_SDADC_CR1_OFFSET, setbits); + + /* CR2 ********************************************************************/ + + setbits = SDADC_CR2_ADON; /* leave it ON ! */ + + /* TODO: JEXTEN / JEXTSEL */ + + /* Number of calibrations is for 3 configurations */ + + setbits |= (2 << SDADC_CR2_CALIBCNT_SHIFT); + + /* Set CR2 configuration */ + + sdadc_putreg(priv, STM32_SDADC_CR2_OFFSET, setbits); + + /* Release INIT mode ******************************************************/ + + sdadc_modifyreg(priv, STM32_SDADC_CR1_OFFSET, SDADC_CR1_INIT, 0); + + /* Calibrate the SDADC */ + + sdadc_modifyreg(priv, STM32_SDADC_CR2_OFFSET, 0, SDADC_CR2_STARTCALIB); + + /* Wait for the calibration to complete (may take up to 5ms) */ + + while ((sdadc_getreg(priv, + STM32_SDADC_ISR_OFFSET) & SDADC_ISR_EOCALF) == 0); + + /* Clear this flag */ + + sdadc_modifyreg(priv, + STM32_SDADC_CLRISR_OFFSET, SDADC_CLRISR_CLREOCALF, 0); + +#ifdef SDADC_HAVE_TIMER + if (priv->tbase != 0) + { + ret = sdadc_timinit(priv); + if (ret < 0) + { + aerr("ERROR: sdadc_timinit failed: %d\n", ret); + } + } +#endif + + /* Put the device in low power mode until it is actually used by + * application code. + */ + + sdadc_enable(priv, false); + + leave_critical_section(flags); + + ainfo("CR1: 0x%08" PRIx32 " CR2: 0x%08" PRIx32 "\n", + sdadc_getreg(priv, STM32_SDADC_CR1_OFFSET), + sdadc_getreg(priv, STM32_SDADC_CR2_OFFSET)); + + ainfo("CONF0R: 0x%08" PRIx32 " CONF1R: 0x%08" PRIx32 + " CONF3R: 0x%08" PRIx32 "\n", + sdadc_getreg(priv, STM32_SDADC_CONF0R_OFFSET), + sdadc_getreg(priv, STM32_SDADC_CONF1R_OFFSET), + sdadc_getreg(priv, STM32_SDADC_CONF2R_OFFSET)); + + ainfo("CONFCHR1: 0x%08" PRIx32 " CONFCHR2: 0x%08" PRIx32 + " JCHGR: 0x%08" PRIx32 "\n", + sdadc_getreg(priv, STM32_SDADC_CONFCHR1_OFFSET), + sdadc_getreg(priv, STM32_SDADC_CONFCHR2_OFFSET), + sdadc_getreg(priv, STM32_SDADC_JCHGR_OFFSET)); +} + +/**************************************************************************** + * Name: sdadc_setup + * + * Description: + * Configure the ADC. This method is called the first time that the SDADC + * device is opened. + * This is called by the upper half driver sdadc_open(). + * This will occur when the port is first + * opened in the application code (/dev/sdadcN). + * It would be called again after closing all references to this file and + * reopening it. + * This function wakes up the device and setup the DMA / IRQ + * + * Input Parameters: + * dev - pointer to the sdadc device structure + * + * Returned Value: + * + ****************************************************************************/ + +static int sdadc_setup(struct adc_dev_s *dev) +{ + struct stm32_dev_s *priv = (struct stm32_dev_s *)dev->ad_priv; + int ret; + + /* Wakes up the device */ + + sdadc_enable(priv, true); + + /* Setup DMA or interrupt control. Note that either DMA or interrupt is + * setup not both. + */ + +#ifdef SDADC_HAVE_DMA + if (priv->hasdma) + { + /* Setup DMA */ + + /* Stop and free DMA if it was started before */ + + if (priv->dma != NULL) + { + stm32_dmastop(priv->dma); + stm32_dmafree(priv->dma); + } + + priv->dma = stm32_dmachannel(priv->dmachan); + + stm32_dmasetup(priv->dma, + priv->base + STM32_SDADC_JDATAR_OFFSET, + (uint32_t)priv->dmabuffer, + priv->nchannels, + SDADC_DMA_CONTROL_WORD); + + stm32_dmastart(priv->dma, sdadc_dmaconvcallback, dev, false); + } + else + { + /* Attach the SDADC interrupt */ + + ret = irq_attach(priv->irq, sdadc_interrupt, dev); + if (ret < 0) + { + ainfo("irq_attach failed: %d\n", ret); + return ret; + } + } +#else + /* Attach the SDADC interrupt */ + + ret = irq_attach(priv->irq, sdadc_interrupt, dev); + if (ret < 0) + { + ainfo("irq_attach failed: %d\n", ret); + return ret; + } +#endif + + return OK; +} + +/**************************************************************************** + * Name: sdadc_shutdown + * + * Description: + * Disable the ADC. This method is called when the last instance + * of the SDADC device is closed by the user application. + * This method reverses the operation the setup method. + * + * Input Parameters: + * dev - pointer to the sdadc device structure + * + * Returned Value: + * + ****************************************************************************/ + +static void sdadc_shutdown(struct adc_dev_s *dev) +{ + struct stm32_dev_s *priv = (struct stm32_dev_s *)dev->ad_priv; + + /* Put the device in low power mode */ + + sdadc_enable(priv, false); + + /* Disable interrupt / dma */ + + sdadc_rxint(dev, false); + +#ifdef SDADC_HAVE_DMA + if (priv->hasdma) + { + /* Stop and free DMA if it was started before */ + + if (priv->dma != NULL) + { + stm32_dmastop(priv->dma); + stm32_dmafree(priv->dma); + } + } + else + { + /* Disable ADC interrupts and detach the SDADC interrupt handler */ + + up_disable_irq(priv->irq); + irq_detach(priv->irq); + } +#else + /* Disable ADC interrupts and detach the SDADC interrupt handler */ + + up_disable_irq(priv->irq); + irq_detach(priv->irq); +#endif +} + +/**************************************************************************** + * Name: sdadc_rxint + * + * Description: + * Call to enable or disable RX interrupts. + * + * Input Parameters: + * + * Returned Value: + * + ****************************************************************************/ + +static void sdadc_rxint(struct adc_dev_s *dev, bool enable) +{ + struct stm32_dev_s *priv = (struct stm32_dev_s *)dev->ad_priv; + uint32_t setbits; + + ainfo("intf: %d enable: %d\n", priv->intf, enable ? 1 : 0); + + /* DMA mode */ + +#ifdef SDADC_HAVE_DMA + if (priv->hasdma) + { + setbits = SDADC_CR1_JDMAEN; /* DMA enabled for injected channels group */ + } + else + { + /* Interrupt enable for injected channel group overrun + * and end of conversion + */ + + setbits = SDADC_CR1_JOVRIE | SDADC_CR1_JEOCIE; + } +#else + setbits = SDADC_CR1_JOVRIE | SDADC_CR1_JEOCIE; +#endif + + if (enable) + { + /* Enable */ + + sdadc_modifyreg(priv, STM32_SDADC_CR1_OFFSET, 0, setbits); + } + else + { + /* Disable all ADC interrupts and DMA */ + + sdadc_modifyreg(priv, STM32_SDADC_CR1_OFFSET, + SDADC_CR1_JOVRIE | SDADC_CR1_JEOCIE | SDADC_CR1_JDMAEN, + 0); + } +} + +/**************************************************************************** + * Name: sdadc_set_ch + * + * Description: + * Sets the SDADC injected channel group. + * + * Input Parameters: + * dev - pointer to device structure used by the driver + * ch - ADC channel number + 1. 0 reserved for all configured channels + * + * Returned Value: + * int - errno + * + ****************************************************************************/ + +static int sdadc_set_ch(struct adc_dev_s *dev, uint8_t ch) +{ + struct stm32_dev_s *priv = (struct stm32_dev_s *)dev->ad_priv; + uint32_t bits = 0; + int i; + + if (ch == 0) + { + priv->current = 0; + priv->nchannels = priv->cchannels; + } + else + { + for (i = 0; i < priv->cchannels && priv->chanlist[i] != ch - 1; i++); + + if (i >= priv->cchannels) + { + return -ENODEV; + } + + priv->current = i; + priv->nchannels = 1; + } + + for (i = 0; i < priv->nchannels; i++) + { + bits |= (uint32_t)(1 << priv->chanlist[i]); + } + + sdadc_putreg(priv, STM32_SDADC_JCHGR_OFFSET, bits); + + return OK; +} + +/**************************************************************************** + * Name: sdadc_ioctl + * + * Description: + * All ioctl calls will be routed through this method. + * + * Input Parameters: + * dev - pointer to device structure used by the driver + * cmd - command + * arg - arguments passed with command + * + * Returned Value: + * + ****************************************************************************/ + +static int sdadc_ioctl(struct adc_dev_s *dev, int cmd, unsigned long arg) +{ + struct stm32_dev_s *priv = (struct stm32_dev_s *)dev->ad_priv; + int ret = OK; + + switch (cmd) + { + case ANIOC_TRIGGER: + { + sdadc_startconv(priv, true); + } + break; + + case ANIOC_GET_NCHANNELS: + { + /* Return the number of configured channels */ + + ret = priv->cchannels; + } + break; + + default: + { + aerr("ERROR: Unknown cmd: %d\n", cmd); + ret = -ENOTTY; + } + break; + } + + return ret; +} + +/**************************************************************************** + * Name: sdadc_interrupt + * + * Description: + * Common SDADC interrupt handler. + * + * Input Parameters: + * + * Returned Value: + * + ****************************************************************************/ + +static int sdadc_interrupt(int irq, void *context, void *arg) +{ + struct adc_dev_s *dev = (struct adc_dev_s *)arg; + struct stm32_dev_s *priv; + uint32_t regval; + uint32_t pending; + int32_t data; + uint8_t chan; + + DEBUGASSERT(dev != NULL && dev->ad_priv != NULL); + priv = (struct stm32_dev_s *)dev->ad_priv; + + regval = sdadc_getreg(priv, STM32_SDADC_ISR_OFFSET); + pending = regval & SDADC_ISR_ALLINTS; + if (pending == 0) + { + return OK; + } + + /* JOVRF: overrun flag */ + + if ((regval & SDADC_ISR_JOVRF) != 0) + { + awarn("WARNING: Overrun has occurred!\n"); + } + + /* JEOCF: End of conversion */ + + if ((regval & SDADC_ISR_JEOCF) != 0) + { + /* Read the converted value and clear JEOCF bit + * (It is cleared by reading the SDADC_JDATAR) + */ + + data = sdadc_getreg(priv, + STM32_SDADC_JDATAR_OFFSET) & + SDADC_JDATAR_JDATA_MASK; + chan = sdadc_getreg(priv, + STM32_SDADC_JDATAR_OFFSET) & + SDADC_JDATAR_JDATACH_MASK; + + DEBUGASSERT(priv->chanlist[priv->current] == chan); + + /* Verify that the upper-half driver has bound its callback functions */ + + if (priv->cb != NULL) + { + /* Give the SDADC data to the ADC driver. The ADC receive() method + * accepts 3 parameters: + * + * 1) The first is the ADC device instance for this SDADC block. + * 2) The second is the channel number for the data, and + * 3) The third is the converted data for the channel. + */ + + DEBUGASSERT(priv->cb->au_receive != NULL); + priv->cb->au_receive(dev, chan, data); + } + + /* Set the channel number of the next channel that will complete + * conversion. + */ + + priv->current++; + + if (priv->current >= priv->nchannels) + { + /* Restart the conversion sequence from the beginning */ + + priv->current = 0; + } + + /* do no clear this interrupt (cleared by reading data) */ + + pending &= ~SDADC_ISR_JEOCF; + } + + /* Clears interrupt flags, if any */ + + if (pending) + { + sdadc_putreg(priv, STM32_SDADC_CLRISR_OFFSET, pending); + } + + return OK; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_sdadcinitialize + * + * Description: + * Initialize one SDADC block + * + * The logic is, save and initialize the channel list in the private driver + * structure and return the corresponding adc device structure. + * + * Each SDADC will convert the channels indicated each + * time a conversion is triggered either by software, timer or external + * event. Channels are numbered from 0 - 8 and must be given in order + * (contrarily to what says ST RM0313 doc !!!). + * + * Input Parameters: + * intf - Could be {1,2,3} for SDADC1, SDADC2, or SDADC3 + * chanlist - The list of channels eg. { 0, 3, 7, 8 } + * cchannels - Number of channels + * + * Returned Value: + * Valid ADC device structure reference on success; a NULL on failure + * + ****************************************************************************/ + +struct adc_dev_s *stm32_sdadcinitialize(int intf, + const uint8_t *chanlist, + int cchannels) +{ + struct adc_dev_s *dev; + struct stm32_dev_s *priv; + int i; + + ainfo("intf: %d cchannels: %d\n", intf, cchannels); + + switch (intf) + { +#ifdef CONFIG_STM32_SDADC1 + case 1: + ainfo("SDADC1 selected\n"); + dev = &g_sdadcdev1; + break; +#endif +#ifdef CONFIG_STM32_SDADC2 + case 2: + ainfo("SDADC2 selected\n"); + dev = &g_sdadcdev2; + break; +#endif +#ifdef CONFIG_STM32_SDADC3 + case 3: + ainfo("SDADC3 selected\n"); + dev = &g_sdadcdev3; + break; +#endif + default: + aerr("ERROR: No SDADC interface defined\n"); + return NULL; + } + + /* Check channel list in order */ + + DEBUGASSERT((cchannels <= SDADC_MAX_SAMPLES) && (cchannels > 0)); + for (i = 0; i < cchannels - 1; i++) + { + if (chanlist[i] >= chanlist[i + 1]) + { + aerr("ERROR: SDADC channel list must be given in order\n"); + return NULL; + } + } + + /* Configure the selected SDADC */ + + priv = (struct stm32_dev_s *)dev->ad_priv; + + priv->cb = NULL; + priv->cchannels = cchannels; + + memcpy(priv->chanlist, chanlist, cchannels); + + return dev; +} + +#endif /* CONFIG_STM32_SDADC1 || CONFIG_STM32_SDADC2 || + * CONFIG_STM32_SDADC3 */ +#endif /* CONFIG_STM32_SDADC */ diff --git a/arch/arm/src/common/stm32/stm32_sdadc_m3m4_v1.h b/arch/arm/src/common/stm32/stm32_sdadc_m3m4_v1.h new file mode 100644 index 0000000000000..6906d43f07c11 --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_sdadc_m3m4_v1.h @@ -0,0 +1,431 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_sdadc_m3m4_v1.h + * + * SPDX-License-Identifier: BSD-3-Clause + * SPDX-FileCopyrightText: 2015 Gregory Nutt. All rights reserved. + * SPDX-FileCopyrightText: 2009, 2011 Gregory Nutt. All rights reserved. + * SPDX-FileCopyrightText: 2016 Studelec. All rights reserved. + * SPDX-FileContributor: Gregory Nutt + * SPDX-FileContributor: Marc Rechté + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_SDADC_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_SDADC_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "chip.h" + +#if defined(CONFIG_STM32_STM32F37XX) +# include "hardware/stm32f37xxx_sdadc.h" +#else +/* No generic chip/stm32_sdadc.h yet */ + +# error "This chip is not yet supported" +#endif + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* Timer devices may be used for different purposes. One special purpose + * is to control periodic SDADC sampling. If CONFIG_STM32_TIMn is defined + * then CONFIG_STM32_TIMn_SDADC must also be defined to indicate that timer + * "n" is intended to be used for that purpose. + */ + +/* For the STM32 F37XX line, timers 2-4, 12-17 an 19 may be used. */ + +/* TODO cf. stm32_adc.h */ + +/* Up to 3 SDADC interfaces are supported */ + +#if STM32_NSDADC < 3 +# undef CONFIG_STM32_SDADC3 +#endif + +#if STM32_NSDADC < 2 +# undef CONFIG_STM32_SDADC2 +#endif + +#if STM32_NSDADC < 1 +# undef CONFIG_STM32_SDADC1 +#endif + +#if defined(CONFIG_STM32_SDADC1) || defined(CONFIG_STM32_SDADC2) || \ + defined(CONFIG_STM32_SDADC3) + +/* DMA support */ + +#if defined(CONFIG_STM32_SDADC1_DMA) || defined(CONFIG_STM32_SDADC2_DMA) || \ + defined(CONFIG_STM32_SDADC3_DMA) +# define SDADC_HAVE_DMA 1 +#endif + +#ifdef CONFIG_STM32_SDADC1_DMA +# define SDADC1_HAVE_DMA 1 +#else +# undef SDADC1_HAVE_DMA +#endif + +#ifdef CONFIG_STM32_SDADC2_DMA +# define SDADC2_HAVE_DMA 1 +#else +# undef SDADC2_HAVE_DMA +#endif + +#ifdef CONFIG_STM32_SDADC3_DMA +# define SDADC3_HAVE_DMA 1 +#else +# undef SDADC3_HAVE_DMA +#endif + +/* SDADC Channels/DMA ******************************************************* + * The maximum number of channels that can be sampled at each scan. + * If DMA support is not enabled, then only a single channel + * ought to be sampled. + * Otherwise, unless sampling frequency is reduced, + * data overruns would occur. + */ + +#define SDADC_MAX_CHANNELS_DMA 9 +#define SDADC_MAX_CHANNELS_NODMA 1 + +#ifndef SDADC_MAX_SAMPLES +#ifdef SDADC_HAVE_DMA +# define SDADC_MAX_SAMPLES SDADC_MAX_CHANNELS_DMA +#else +# define SDADC_MAX_SAMPLES SDADC_MAX_CHANNELS_NODMA +#endif +#endif + +/* Timer configuration: If a timer trigger is specified, then get + * information about the timer. + */ + +#if defined(CONFIG_STM32_TIM3_SDADC1) +# define SDADC1_HAVE_TIMER 1 +# define SDADC1_TIMER_BASE STM32_TIM3_BASE +# define SDADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM3_CLKIN +#elif defined(CONFIG_STM32_TIM4_SDADC1) +# define SDADC1_HAVE_TIMER 1 +# define SDADC1_TIMER_BASE STM32_TIM4_BASE +# define SDADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM4_CLKIN +#elif defined(CONFIG_STM32_TIM13_SDADC1) +# define SDADC1_HAVE_TIMER 1 +# define SDADC1_TIMER_BASE STM32_TIM13_BASE +# define SDADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM13_CLKIN +#elif defined(CONFIG_STM32_TIM14_SDADC1) +# define SDADC1_HAVE_TIMER 1 +# define SDADC1_TIMER_BASE STM32_TIM14_BASE +# define SDADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM14_CLKIN +#elif defined(CONFIG_STM32_TIM15_SDADC1) +# define SDADC1_HAVE_TIMER 1 +# define SDADC1_TIMER_BASE STM32_TIM15_BASE +# define SDADC1_TIMER_PCLK_FREQUENCY STM32_APB2_TIM15_CLKIN +#elif defined(CONFIG_STM32_TIM19_SDADC1) +# define SDADC1_HAVE_TIMER 1 +# define SDADC1_TIMER_BASE STM32_TIM19_BASE +# define SDADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM19_CLKIN +#else +# undef SDADC1_HAVE_TIMER +#endif + +#ifdef SDADC1_HAVE_TIMER +# ifndef CONFIG_STM32_SDADC1_SAMPLE_FREQUENCY +# error "CONFIG_STM32_SDADC1_SAMPLE_FREQUENCY not defined" +# endif +# ifndef CONFIG_STM32_SDADC1_TIMTRIG +# error "CONFIG_STM32_SDADC1_TIMTRIG not defined" +# warning "Values 0:TIM13_CH1 1:TIM14_CH1 2:TIM15_CH2 3:TIM3_CH1 4:TIM4_CH1 5:TIM19_CH2" +# endif +#endif + +#if defined(CONFIG_STM32_TIM2_SDADC2) +# define SDADC2_HAVE_TIMER 1 +# define SDADC2_TIMER_BASE STM32_TIM2_BASE +# define SDADC2_TIMER_PCLK_FREQUENCY STM32_APB1_TIM2_CLKIN +#elif defined(CONFIG_STM32_TIM3_SDADC2) +# define SDADC2_HAVE_TIMER 1 +# define SDADC2_TIMER_BASE STM32_TIM3_BASE +# define SDADC2_TIMER_PCLK_FREQUENCY STM32_APB1_TIM3_CLKIN +#elif defined(CONFIG_STM32_TIM4_SDADC2) +# define SDADC2_HAVE_TIMER 1 +# define SDADC2_TIMER_BASE STM32_TIM4_BASE +# define SDADC2_TIMER_PCLK_FREQUENCY STM32_APB1_TIM4_CLKIN +#elif defined(CONFIG_STM32_TIM12_SDADC2) +# define SDADC2_HAVE_TIMER 1 +# define SDADC2_TIMER_BASE STM32_TIM12_BASE +# define SDADC2_TIMER_PCLK_FREQUENCY STM32_APB1_TIM12_CLKIN +#elif defined(CONFIG_STM32_TIM17_SDADC2) +# define SDADC2_HAVE_TIMER 1 +# define SDADC2_TIMER_BASE STM32_TIM17_BASE +# define SDADC2_TIMER_PCLK_FREQUENCY STM32_APB2_TIM17_CLKIN +#elif defined(CONFIG_STM32_TIM19_SDADC2) +# define SDADC2_HAVE_TIMER 1 +# define SDADC2_TIMER_BASE STM32_TIM19_BASE +# define SDADC2_TIMER_PCLK_FREQUENCY STM32_APB1_TIM19_CLKIN +#else +# undef SDADC2_HAVE_TIMER +#endif + +#ifdef SDADC2_HAVE_TIMER +# ifndef CONFIG_STM32_SDADC2_SAMPLE_FREQUENCY +# error "CONFIG_STM32_SDADC2_SAMPLE_FREQUENCY not defined" +# endif +# ifndef CONFIG_STM32_SDADC2_TIMTRIG +# error "CONFIG_STM32_SDADC2_TIMTRIG not defined" +# warning "Values 0:TIM17_CH1 1:TIM12_CH1 2:TIM2_CH3 3:TIM3_CH2 4:TIM4_CH2 5:TIM19_CH3" +# endif +#endif + +#if defined(CONFIG_STM32_TIM2_SDADC3) +# define SDADC3_HAVE_TIMER 1 +# define SDADC3_TIMER_BASE STM32_TIM2_BASE +# define SDADC3_TIMER_PCLK_FREQUENCY STM32_APB1_TIM2_CLKIN +#elif defined(CONFIG_STM32_TIM3_SDADC3) +# define SDADC3_HAVE_TIMER 1 +# define SDADC3_TIMER_BASE STM32_TIM3_BASE +# define SDADC3_TIMER_PCLK_FREQUENCY STM32_APB1_TIM3_CLKIN +#elif defined(CONFIG_STM32_TIM4_SDADC3) +# define SDADC3_HAVE_TIMER 1 +# define SDADC3_TIMER_BASE STM32_TIM4_BASE +# define SDADC3_TIMER_PCLK_FREQUENCY STM32_APB1_TIM4_CLKIN +#elif defined(CONFIG_STM32_TIM12_SDADC3) +# define SDADC3_HAVE_TIMER 1 +# define SDADC3_TIMER_BASE STM32_TIM12_BASE +# define SDADC3_TIMER_PCLK_FREQUENCY STM32_APB1_TIM12_CLKIN +#elif defined(CONFIG_STM32_TIM16_SDADC3) +# define SDADC3_HAVE_TIMER 1 +# define SDADC3_TIMER_BASE STM32_TIM16_BASE +# define SDADC3_TIMER_PCLK_FREQUENCY STM32_APB2_TIM16_CLKIN +#elif defined(CONFIG_STM32_TIM19_SDADC3) +# define SDADC3_HAVE_TIMER 1 +# define SDADC3_TIMER_BASE STM32_TIM19_BASE +# define SDADC3_TIMER_PCLK_FREQUENCY STM32_APB1_TIM19_CLKIN +#else +# undef SDADC3_HAVE_TIMER +#endif + +#ifdef SDADC3_HAVE_TIMER +# ifndef CONFIG_STM32_SDADC3_SAMPLE_FREQUENCY +# error "CONFIG_STM32_SDADC3_SAMPLE_FREQUENCY not defined" +# endif +# ifndef CONFIG_STM32_SDADC3_TIMTRIG +# error "CONFIG_STM32_SDADC3_TIMTRIG not defined" +# warning "Values 0:TIM16_CH1 1:TIM12_CH2 2:TIM2_CH4 3:TIM3_CH3 4:TIM4_CH3 5:TIM19_CH4" +# endif +#endif + +#if defined(SDADC1_HAVE_TIMER) || defined(SDADC2_HAVE_TIMER) || \ + defined(SDADC3_HAVE_TIMER) +# define SDADC_HAVE_TIMER 1 +# if defined(CONFIG_STM32_STM32F37XX) && !defined(CONFIG_STM32_FORCEPOWER) +# warning "CONFIG_STM32_FORCEPOWER must be defined to enable the timer(s)" +# endif +#else +# undef SDADC_HAVE_TIMER +#endif + +/* NOTE: The following assumes that all possible combinations of timers and + * values are support JEXTSEL. That is not so and it varies from one STM32 + * to another. But this (wrong) assumptions keeps the logic as simple as + * possible. If unsupported combination is used, an error will show up + * later during compilation although it may be difficult to track it back + * to this simplification. + * + * STM32L37XX-family has 3 SDADC onboard + */ + +#ifdef CONFIG_STM32_STM32F37XX +# define SDADC1_JEXTSEL_TIM13_CH1 SDADC1_CR2_JEXTSEL_TIM13_CH1 +# define SDADC1_JEXTSEL_TIM14_CH1 SDADC1_CR2_JEXTSEL_TIM14_CH1 +# define SDADC1_JEXTSEL_TIM15_CH2 SDADC1_CR2_JEXTSEL_TIM15_CH2 +# define SDADC1_JEXTSEL_TIM3_CH1 SDADC1_CR2_JEXTSEL_TIM3_CH1 +# define SDADC1_JEXTSEL_TIM4_CH1 SDADC1_CR2_JEXTSEL_TIM4_CH1 +# define SDADC1_JEXTSEL_TIM19_CH2 SDADC1_CR2_JEXTSEL_TIM19_CH2 +# define SDADC1_JEXTSEL_EXTI15 SDADC1_CR2_JEXTSEL_EXTI15 +# define SDADC1_JEXTSEL_EXTI11 SDADC1_CR2_JEXTSEL_EXTI11 +# define SDADC2_JEXTSEL_TIM17_CH1 SDADC2_CR2_JEXTSEL_TIM17_CH1 +# define SDADC2_JEXTSEL_TIM12_CH1 SDADC2_CR2_JEXTSEL_TIM12_CH1 +# define SDADC2_JEXTSEL_TIM2_CH3 SDADC2_CR2_JEXTSEL_TIM2_CH3 +# define SDADC2_JEXTSEL_TIM3_CH2 SDADC2_CR2_JEXTSEL_TIM3_CH2 +# define SDADC2_JEXTSEL_TIM4_CH2 SDADC2_CR2_JEXTSEL_TIM4_CH2 +# define SDADC2_JEXTSEL_TIM19_CH3 SDADC2_CR2_JEXTSEL_TIM19_CH3 +# define SDADC2_JEXTSEL_EXTI15 SDADC2_CR2_JEXTSEL_EXTI15 +# define SDADC2_JEXTSEL_EXTI11 SDADC2_CR2_JEXTSEL_EXTI11 +# define SDADC3_JEXTSEL_TIM16_CH1 SDADC3_CR2_JEXTSEL_TIM16_CH1 +# define SDADC3_JEXTSEL_TIM12_CH1 SDADC3_CR2_JEXTSEL_TIM12_CH1 +# define SDADC3_JEXTSEL_TIM2_CH4 SDADC3_CR2_JEXTSEL_TIM2_CH4 +# define SDADC3_JEXTSEL_TIM3_CH3 SDADC3_CR2_JEXTSEL_TIM3_CH3 +# define SDADC3_JEXTSEL_TIM4_CH3 SDADC3_CR2_JEXTSEL_TIM4_CH3 +# define SDADC3_JEXTSEL_TIM19_CH4 SDADC3_CR2_JEXTSEL_TIM19_CH4 +# define SDADC3_JEXTSEL_EXTI15 SDADC3_CR2_JEXTSEL_EXTI15 +# define SDADC3_JEXTSEL_EXTI11 SDADC3_CR2_JEXTSEL_EXTI11 +#endif + +#if defined(CONFIG_STM32_TIM3_SDADC1) +# define SDADC1_JEXTSEL_VALUE 3 +#elif defined(CONFIG_STM32_TIM4_SDADC1) +# define SDADC1_JEXTSEL_VALUE 4 +#elif defined(CONFIG_STM32_TIM13_SDADC1) +# define SDADC1_JEXTSEL_VALUE 0 +#elif defined(CONFIG_STM32_TIM14_SDADC1) +# define SDADC1_JEXTSEL_VALUE 1 +#elif defined(CONFIG_STM32_TIM15_SDADC1) +# define SDADC1_JEXTSEL_VALUE 2 +#elif defined(CONFIG_STM32_TIM19_SDADC1) +# define SDADC1_JEXTSEL_VALUE 5 +#else +# undef SDADC1_JEXTSEL_VALUE +#endif + +#if defined(CONFIG_STM32_TIM2_SDADC2) +# define SDADC2_JEXTSEL_VALUE 2 +#elif defined(CONFIG_STM32_TIM3_SDADC2) +# define SDADC2_JEXTSEL_VALUE 3 +#elif defined(CONFIG_STM32_TIM4_SDADC2) +# define SDADC2_JEXTSEL_VALUE 4 +#elif defined(CONFIG_STM32_TIM12_SDADC2) +# define SDADC2_JEXTSEL_VALUE 1 +#elif defined(CONFIG_STM32_TIM17_SDADC2) +# define SDADC2_JEXTSEL_VALUE 0 +#elif defined(CONFIG_STM32_TIM19_SDADC2) +# define SDADC2_JEXTSEL_VALUE 5 +#else +# undef SDADC2_JEXTSEL_VALUE +#endif + +#if defined(CONFIG_STM32_TIM2_SDADC3) +# define SDADC3_JEXTSEL_VALUE 2 +#elif defined(CONFIG_STM32_TIM3_SDADC3) +# define SDADC3_JEXTSEL_VALUE 3 +#elif defined(CONFIG_STM32_TIM4_SDADC3) +# define SDADC3_JEXTSEL_VALUE 4 +#elif defined(CONFIG_STM32_TIM12_SDADC3) +# define SDADC3_JEXTSEL_VALUE 1 +#elif defined(CONFIG_STM32_TIM16_SDADC3) +# define SDADC3_JEXTSEL_VALUE 0 +#elif defined(CONFIG_STM32_TIM19_SDADC3) +# define SDADC3_JEXTSEL_VALUE 5 +#else +# undef SDADC3_JEXTSEL_VALUE +#endif + +/* SDADC Configurations ***************************************************** + * Up to 3 configuration profiles may be defined in order to define: + * - calibration method + * - SE/differential mode + * - input gain + * Each of the 9 SDADC channels is assigned to a configuration profile + */ +#ifndef SDADC_CONF0R_DEFAULT +# define SDADC_CONF0R_DEFAULT (SDADC_CONFR_GAIN_1X | SDADC_CONFR_SE_SE_OFFSET | SDADC_CONFR_COMMON_GND) +#endif +#ifndef SDADC_CONF1R_DEFAULT +# define SDADC_CONF1R_DEFAULT (SDADC_CONFR_GAIN_2X | SDADC_CONFR_SE_SE_OFFSET | SDADC_CONFR_COMMON_GND) +#endif +#ifndef SDADC_CONF2R_DEFAULT +# define SDADC_CONF2R_DEFAULT (SDADC_CONFR_GAIN_4X | SDADC_CONFR_SE_SE_OFFSET | SDADC_CONFR_COMMON_GND) +#endif +#ifndef SDADC_CONFCHR1_DEFAULT +# define SDADC_CONFCHR1_DEFAULT ((SDADC_CONF0R << SDADC_CONFCHR1_CH_SHIFT(0)) | \ + (SDADC_CONF0R << SDADC_CONFCHR1_CH_SHIFT(1)) | \ + (SDADC_CONF0R << SDADC_CONFCHR1_CH_SHIFT(2)) | \ + (SDADC_CONF0R << SDADC_CONFCHR1_CH_SHIFT(3)) | \ + (SDADC_CONF0R << SDADC_CONFCHR1_CH_SHIFT(4)) | \ + (SDADC_CONF0R << SDADC_CONFCHR1_CH_SHIFT(5)) | \ + (SDADC_CONF0R << SDADC_CONFCHR1_CH_SHIFT(6)) | \ + (SDADC_CONF0R << SDADC_CONFCHR1_CH_SHIFT(7))) +#endif +#ifndef SDADC_CONFCHR2_DEFAULT +# define SDADC_CONFCHR2_DEFAULT (SDADC_CONF0R << SDADC_CONFCHR2_CH8_SHIFT) +#endif + +/* SDADC Reference voltage selection ****************************************/ + +#ifndef SDADC_REFV_DEFAULT +# define SDADC_REFV_DEFAULT SDADC_CR1_REFV_EXT +#endif +#ifndef SDADC1_REFV +# define SDADC1_REFV SDADC_REFV_DEFAULT +#endif +#ifndef SDADC2_REFV +# define SDADC2_REFV SDADC_REFV_DEFAULT +#endif +#ifndef SDADC3_REFV +# define SDADC3_REFV SDADC_REFV_DEFAULT +#endif + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#ifndef __ASSEMBLY__ +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Name: stm32_sdadcinitialize + * + ****************************************************************************/ + +struct adc_dev_s *stm32_sdadcinitialize(int intf, + const uint8_t *chanlist, + int nchannels); + +#undef EXTERN +#ifdef __cplusplus +} +#endif +#endif /* __ASSEMBLY__ */ + +#endif /* CONFIG_STM32_SDADC1 || CONFIG_STM32_SDADC2 || + * CONFIG_STM32_SDADC3 + */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_SDADC_H */ diff --git a/arch/arm/src/common/stm32/stm32_sdio.h b/arch/arm/src/common/stm32/stm32_sdio.h new file mode 100644 index 0000000000000..8dc71bb2709d6 --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_sdio.h @@ -0,0 +1,38 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_sdio.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_COMPAT_STM32SDIO_H +#define __ARCH_ARM_SRC_COMMON_COMPAT_STM32SDIO_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#if defined(CONFIG_STM32_HAVE_IP_SDIO_M3M4_V1) +# include "stm32_sdio_m3m4_v1.h" +#else +# error "Unsupported STM32 stm32_sdio" +#endif + +#endif /* __ARCH_ARM_SRC_COMMON_COMPAT_STM32SDIO_H */ diff --git a/arch/arm/src/common/stm32/stm32_sdio_m3m4_v1.c b/arch/arm/src/common/stm32/stm32_sdio_m3m4_v1.c new file mode 100644 index 0000000000000..3387e111c4e0e --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_sdio_m3m4_v1.c @@ -0,0 +1,3196 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_sdio_m3m4_v1.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32.h" +#include "stm32_dma.h" +#include "stm32_sdio_m3m4_v1.h" +#include "stm32_dma.h" +#include "stm32_sdio_m3m4_v1.h" + +#ifdef CONFIG_STM32_SDIO + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* Required system configuration options: + * + * CONFIG_ARCH_DMA - Enable architecture-specific DMA subsystem + * initialization. Required if CONFIG_STM32_SDIO_DMA is enabled. + * CONFIG_STM32_DMA2 - Enable STM32 DMA2 support. Required if + * CONFIG_STM32_SDIO_DMA is enabled + * CONFIG_SCHED_WORKQUEUE -- Callback support requires work queue support. + * + * Driver-specific configuration options: + * + * CONFIG_SDIO_MUXBUS - Setting this configuration enables some locking + * APIs to manage concurrent accesses on the SDIO bus. This is not + * needed for the simple case of a single SD card, for example. + * CONFIG_STM32_SDIO_DMA - Enable SDIO. This is a marginally optional. + * For most usages, SDIO will cause data overruns if used without DMA. + * NOTE the above system DMA configuration options. + * CONFIG_STM32_SDIO_WIDTH_D1_ONLY - This may be selected to force the + * driver operate with only a single data line (the default is to use + * all 4 SD data lines). + * CONFIG_SDM_DMAPRIO - SDIO DMA priority. This can be selected if + * CONFIG_STM32_SDIO_DMA is enabled. + * CONFIG_SDIO_XFRDEBUG - Enables some very low-level debug output + * This also requires CONFIG_DEBUG_FS and CONFIG_DEBUG_INFO + */ + +#if !defined(CONFIG_STM32_SDIO_DMA) +# warning "Large Non-DMA transfer may result in RX overrun failures" +#else +# ifndef CONFIG_STM32_DMA2 +# error "CONFIG_STM32_SDIO_DMA support requires CONFIG_STM32_DMA2" +# endif +# ifndef CONFIG_SDIO_DMA +# error CONFIG_SDIO_DMA must be defined with CONFIG_STM32_SDIO_DMA +# endif +#endif + +#ifndef CONFIG_STM32_SDIO_DMA +# warning "Large Non-DMA transfer may result in RX overrun failures" +#endif + +#ifndef CONFIG_SCHED_WORKQUEUE +# error "Callback support requires CONFIG_SCHED_WORKQUEUE" +#endif + +#ifdef CONFIG_STM32_SDIO_DMA +# ifndef CONFIG_STM32_SDIO_DMAPRIO +# if defined(CONFIG_STM32_STM32F10XX) +# define CONFIG_STM32_SDIO_DMAPRIO DMA_CCR_PRIMED +# elif defined(CONFIG_STM32_HAVE_IP_DMA_V2) +# define CONFIG_STM32_SDIO_DMAPRIO DMA_SCR_PRIVERYHI +# else +# error "Unknown STM32 DMA" +# endif +# endif +# if defined(CONFIG_STM32_STM32F10XX) +# if (CONFIG_STM32_SDIO_DMAPRIO & ~DMA_CCR_PL_MASK) != 0 +# error "Illegal value for CONFIG_STM32_SDIO_DMAPRIO" +# endif +# elif defined(CONFIG_STM32_HAVE_IP_DMA_V2) +# if (CONFIG_STM32_SDIO_DMAPRIO & ~DMA_SCR_PL_MASK) != 0 +# error "Illegal value for CONFIG_STM32_SDIO_DMAPRIO" +# endif +# else +# error "Unknown STM32 DMA" +# endif +#else +# undef CONFIG_STM32_SDIO_DMAPRIO +#endif + +#ifndef CONFIG_DEBUG_MEMCARD_INFO +# undef CONFIG_SDIO_XFRDEBUG +#endif + +/* Enable the SDIO pull-up resistors if needed */ + +#ifdef CONFIG_STM32_SDIO_PULLUP +# define SDIO_PULLUP_ENABLE GPIO_PULLUP +#else +# define SDIO_PULLUP_ENABLE 0 +#endif + +/* Friendly CLKCR bit re-definitions ****************************************/ + +#define SDIO_CLKCR_RISINGEDGE (0) +#define SDIO_CLKCR_FALLINGEDGE SDIO_CLKCR_NEGEDGE + +/* Use the default of the rising edge but allow a configuration, + * that does not have the errata, to override the edge the SDIO + * command and data is changed on. + */ + +#if !defined(SDIO_CLKCR_EDGE) +# define SDIO_CLKCR_EDGE SDIO_CLKCR_RISINGEDGE +#endif + +/* Mode dependent settings. These depend on clock divisor settings that must + * be defined in the board-specific board.h header file: SDIO_INIT_CLKDIV, + * SDIO_MMCXFR_CLKDIV, and SDIO_SDXFR_CLKDIV. + */ + +#define STM32_CLCKCR_INIT (SDIO_INIT_CLKDIV | SDIO_CLKCR_EDGE | \ + SDIO_CLKCR_WIDBUS_D1) +#define SDIO_CLKCR_MMCXFR (SDIO_MMCXFR_CLKDIV | SDIO_CLKCR_EDGE | \ + SDIO_CLKCR_WIDBUS_D1) +#define SDIO_CLCKR_SDXFR (SDIO_SDXFR_CLKDIV | SDIO_CLKCR_EDGE | \ + SDIO_CLKCR_WIDBUS_D1) +#define SDIO_CLCKR_SDWIDEXFR (SDIO_SDXFR_CLKDIV | SDIO_CLKCR_EDGE | \ + SDIO_CLKCR_WIDBUS_D4) + +/* Timing */ + +#define SDIO_CMDTIMEOUT (100000) +#define SDIO_LONGTIMEOUT (0x7fffffff) + +/* DTIMER setting */ + +/* Assuming Max timeout in bypass 48 Mhz */ + +#define IP_CLCK_FREQ UINT32_C(48000000) +#define SDIO_DTIMER_DATATIMEOUT_MS 250 + +/* DMA channel/stream configuration register settings. The following + * must be selected. The DMA driver will select the remaining fields. + * + * - 32-bit DMA + * - Memory increment + * - Direction (memory-to-peripheral, peripheral-to-memory) + * - Memory burst size (F4 only) + */ + +/* STM32 F1 channel configuration register (CCR) settings */ + +#if defined(CONFIG_STM32_STM32F10XX) +# define SDIO_RXDMA32_CONFIG (CONFIG_STM32_SDIO_DMAPRIO | DMA_CCR_MSIZE_32BITS | \ + DMA_CCR_PSIZE_32BITS | DMA_CCR_MINC) +# define SDIO_TXDMA32_CONFIG (CONFIG_STM32_SDIO_DMAPRIO | DMA_CCR_MSIZE_32BITS | \ + DMA_CCR_PSIZE_32BITS | DMA_CCR_MINC | DMA_CCR_DIR) + +/* STM32 F4 stream configuration register (SCR) settings. */ + +#elif defined(CONFIG_STM32_HAVE_IP_DMA_V2) +# define SDIO_RXDMA32_CONFIG (DMA_SCR_PFCTRL | DMA_SCR_DIR_P2M|DMA_SCR_MINC | \ + DMA_SCR_PSIZE_32BITS | DMA_SCR_MSIZE_32BITS | \ + CONFIG_STM32_SDIO_DMAPRIO | DMA_SCR_PBURST_INCR4 | \ + DMA_SCR_MBURST_INCR4) +# define SDIO_TXDMA32_CONFIG (DMA_SCR_PFCTRL | DMA_SCR_DIR_M2P | DMA_SCR_MINC | \ + DMA_SCR_PSIZE_32BITS | DMA_SCR_MSIZE_32BITS | \ + CONFIG_STM32_SDIO_DMAPRIO | DMA_SCR_PBURST_INCR4 | \ + DMA_SCR_MBURST_INCR4) +#else +# error "Unknown STM32 DMA" +#endif + +/* SDIO DMA Channel/Stream selection. For the case of the STM32 F4, there + * are multiple DMA stream options that must be dis-ambiguated in the board.h + * file. + */ + +#if defined(CONFIG_STM32_STM32F10XX) +# define SDIO_DMACHAN DMACHAN_SDIO +#elif defined(CONFIG_STM32_HAVE_IP_DMA_V2) +# define SDIO_DMACHAN DMAMAP_SDIO +#else +# error "Unknown STM32 DMA" +#endif + +/* FIFO sizes */ + +#define SDIO_HALFFIFO_WORDS (8) +#define SDIO_HALFFIFO_BYTES (8*4) + +/* Data transfer interrupt mask bits */ + +#define SDIO_RECV_MASK (SDIO_MASK_DCRCFAILIE | SDIO_MASK_DTIMEOUTIE | \ + SDIO_MASK_DATAENDIE | SDIO_MASK_RXOVERRIE | \ + SDIO_MASK_RXFIFOHFIE | SDIO_MASK_STBITERRIE) +#define SDIO_SEND_MASK (SDIO_MASK_DCRCFAILIE | SDIO_MASK_DTIMEOUTIE | \ + SDIO_MASK_DATAENDIE | SDIO_MASK_TXUNDERRIE | \ + SDIO_MASK_TXFIFOHEIE | SDIO_MASK_STBITERRIE) +#define SDIO_DMARECV_MASK (SDIO_MASK_DCRCFAILIE | SDIO_MASK_DTIMEOUTIE | \ + SDIO_MASK_DATAENDIE | SDIO_MASK_RXOVERRIE | \ + SDIO_MASK_STBITERRIE) +#define SDIO_DMASEND_MASK (SDIO_MASK_DCRCFAILIE | SDIO_MASK_DTIMEOUTIE | \ + SDIO_MASK_DATAENDIE | SDIO_MASK_TXUNDERRIE | \ + SDIO_MASK_STBITERRIE) + +/* Event waiting interrupt mask bits */ + +#define SDIO_CMDDONE_STA (SDIO_STA_CMDSENT) +#define SDIO_RESPDONE_STA (SDIO_STA_CTIMEOUT | SDIO_STA_CCRCFAIL | \ + SDIO_STA_CMDREND) +#define SDIO_XFRDONE_STA (0) + +#define SDIO_CMDDONE_MASK (SDIO_MASK_CMDSENTIE) +#define SDIO_RESPDONE_MASK (SDIO_MASK_CCRCFAILIE | SDIO_MASK_CTIMEOUTIE | \ + SDIO_MASK_CMDRENDIE) +#define SDIO_XFRDONE_MASK (0) + +#define SDIO_CMDDONE_ICR (SDIO_ICR_CMDSENTC | SDIO_ICR_DBCKENDC) +#define SDIO_RESPDONE_ICR (SDIO_ICR_CTIMEOUTC | SDIO_ICR_CCRCFAILC | \ + SDIO_ICR_CMDRENDC | SDIO_ICR_DBCKENDC) +#define SDIO_XFRDONE_ICR (SDIO_ICR_DATAENDC | SDIO_ICR_DCRCFAILC | \ + SDIO_ICR_DTIMEOUTC | SDIO_ICR_RXOVERRC | \ + SDIO_ICR_TXUNDERRC | SDIO_ICR_STBITERRC | \ + SDIO_ICR_DBCKENDC) + +#define SDIO_WAITALL_ICR (SDIO_CMDDONE_ICR | SDIO_RESPDONE_ICR | \ + SDIO_XFRDONE_ICR | SDIO_ICR_DBCKENDC) + +/* Let's wait until we have both SDIO transfer complete and DMA complete. */ + +#define SDIO_XFRDONE_FLAG (1) +#define SDIO_DMADONE_FLAG (2) +#define SDIO_ALLDONE (3) + +/* Register logging support */ + +#ifdef CONFIG_SDIO_XFRDEBUG +# ifdef CONFIG_STM32_SDIO_DMA +# define SAMPLENDX_BEFORE_SETUP 0 +# define SAMPLENDX_BEFORE_ENABLE 1 +# define SAMPLENDX_AFTER_SETUP 2 +# define SAMPLENDX_END_TRANSFER 3 +# define SAMPLENDX_DMA_CALLBACK 4 +# define DEBUG_NSAMPLES 5 +# else +# define SAMPLENDX_BEFORE_SETUP 0 +# define SAMPLENDX_AFTER_SETUP 1 +# define SAMPLENDX_END_TRANSFER 2 +# define DEBUG_NSAMPLES 3 +# endif +#endif + +#define STM32_SDIO_USE_DEFAULT_BLOCKSIZE ((uint8_t)-1) + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/* This structure defines the state of the STM32 SDIO interface */ + +struct stm32_dev_s +{ + struct sdio_dev_s dev; /* Standard, base SDIO interface */ + + /* STM32-specific extensions */ + + /* Event support */ + + sem_t waitsem; /* Implements event waiting */ + sdio_eventset_t waitevents; /* Set of events to be waited for */ + uint32_t waitmask; /* Interrupt enables for event waiting */ + volatile sdio_eventset_t wkupevent; /* The event that caused the wakeup */ + struct wdog_s waitwdog; /* Watchdog that handles event timeouts */ + + /* Callback support */ + + sdio_statset_t cdstatus; /* Card status */ + sdio_eventset_t cbevents; /* Set of events to be cause callbacks */ + worker_t callback; /* Registered callback function */ + void *cbarg; /* Registered callback argument */ + struct work_s cbwork; /* Callback work queue structure */ + + /* Interrupt mode data transfer support */ + + uint32_t *buffer; /* Address of current R/W buffer */ + size_t remaining; /* Number of bytes remaining in the transfer */ + uint32_t xfrmask; /* Interrupt enables for data transfer */ + +#ifdef CONFIG_STM32_SDIO_CARD + /* Interrupt at SDIO_D1 pin, only for SDIO cards */ + + uint32_t sdiointmask; /* STM32 SDIO register mask */ + int (*do_sdio_card)(void *); /* SDIO card ISR */ + void *do_sdio_arg; /* arg for SDIO card ISR */ +#endif + + /* Fixed transfer block size support */ + +#ifdef CONFIG_SDIO_BLOCKSETUP + uint8_t block_size; +#endif + + /* DMA data transfer support */ + + bool widebus; /* Required for DMA support */ +#ifdef CONFIG_STM32_SDIO_DMA + volatile uint8_t xfrflags; /* Used to synchronize SDIO and + * DMA completion events */ + bool dmamode; /* true: DMA mode transfer */ + DMA_HANDLE dma; /* Handle for DMA channel */ +#endif +}; + +/* Register logging support */ + +#ifdef CONFIG_SDIO_XFRDEBUG +struct stm32_sdioregs_s +{ + uint8_t power; + uint16_t clkcr; + uint16_t dctrl; + uint32_t dtimer; + uint32_t dlen; + uint32_t dcount; + uint32_t sta; + uint32_t mask; + uint32_t fifocnt; +}; + +struct stm32_sampleregs_s +{ + struct stm32_sdioregs_s sdio; +#if defined(CONFIG_DEBUG_DMA_INFO) && defined(CONFIG_STM32_SDIO_DMA) + struct stm32_dmaregs_s dma; +#endif +}; +#endif + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/* Low-level helpers ********************************************************/ + +static inline void stm32_setclkcr(uint32_t clkcr); +static void stm32_configwaitints(struct stm32_dev_s *priv, uint32_t waitmask, + sdio_eventset_t waitevents, sdio_eventset_t wkupevents); +static void stm32_configxfrints(struct stm32_dev_s *priv, uint32_t xfrmask); +static void stm32_setpwrctrl(uint32_t pwrctrl); + +/* DMA Helpers **************************************************************/ + +#ifdef CONFIG_SDIO_XFRDEBUG +static void stm32_sampleinit(void); +static void stm32_sdiosample(struct stm32_sdioregs_s *regs); +static void stm32_sample(struct stm32_dev_s *priv, int index); +static void stm32_sdiodump(struct stm32_sdioregs_s *regs, const char *msg); +static void stm32_dumpsample(struct stm32_dev_s *priv, + struct stm32_sampleregs_s *regs, const char *msg); +static void stm32_dumpsamples(struct stm32_dev_s *priv); +#else +# define stm32_sampleinit() +# define stm32_sample(priv,index) +# define stm32_dumpsamples(priv) +#endif + +#ifdef CONFIG_STM32_SDIO_DMA +static void stm32_dmacallback(DMA_HANDLE handle, uint8_t status, void *arg); +#endif + +/* Data Transfer Helpers ****************************************************/ + +static uint8_t stm32_log2(uint16_t value); +static void stm32_dataconfig(uint32_t timeout, uint32_t dlen, + uint32_t dctrl); +static void stm32_datadisable(void); +static void stm32_sendfifo(struct stm32_dev_s *priv); +static void stm32_recvfifo(struct stm32_dev_s *priv); +static void stm32_eventtimeout(wdparm_t arg); +static void stm32_endwait(struct stm32_dev_s *priv, + sdio_eventset_t wkupevent); +static void stm32_endtransfer(struct stm32_dev_s *priv, + sdio_eventset_t wkupevent); + +/* Interrupt Handling *******************************************************/ + +static int stm32_interrupt(int irq, void *context, void *arg); +#ifdef CONFIG_MMCSD_SDIOWAIT_WRCOMPLETE +static int stm32_rdyinterrupt(int irq, void *context, void *arg); +#endif + +/* SDIO interface methods ***************************************************/ + +/* Mutual exclusion */ + +#ifdef CONFIG_SDIO_MUXBUS +static int stm32_lock(struct sdio_dev_s *dev, bool lock); +#endif + +/* Initialization/setup */ + +static void stm32_reset(struct sdio_dev_s *dev); +static sdio_capset_t stm32_capabilities(struct sdio_dev_s *dev); +static sdio_statset_t stm32_status(struct sdio_dev_s *dev); +static void stm32_widebus(struct sdio_dev_s *dev, bool enable); +static void stm32_clock(struct sdio_dev_s *dev, + enum sdio_clock_e rate); +static int stm32_attach(struct sdio_dev_s *dev); + +/* Command/Status/Data Transfer */ + +static int stm32_sendcmd(struct sdio_dev_s *dev, uint32_t cmd, + uint32_t arg); +#ifdef CONFIG_SDIO_BLOCKSETUP +static void stm32_blocksetup(struct sdio_dev_s *dev, + unsigned int blocklen, unsigned int nblocks); +#endif +static int stm32_recvsetup(struct sdio_dev_s *dev, uint8_t *buffer, + size_t nbytes); +static int stm32_sendsetup(struct sdio_dev_s *dev, + const uint8_t *buffer, size_t nbytes); +static int stm32_cancel(struct sdio_dev_s *dev); + +static int stm32_waitresponse(struct sdio_dev_s *dev, uint32_t cmd); +static int stm32_recvshortcrc(struct sdio_dev_s *dev, uint32_t cmd, + uint32_t *rshort); +static int stm32_recvlong(struct sdio_dev_s *dev, uint32_t cmd, + uint32_t rlong[4]); +static int stm32_recvshort(struct sdio_dev_s *dev, uint32_t cmd, + uint32_t *rshort); + +/* EVENT handler */ + +static void stm32_waitenable(struct sdio_dev_s *dev, + sdio_eventset_t eventset, uint32_t timeout); +static sdio_eventset_t stm32_eventwait(struct sdio_dev_s *dev); +static void stm32_callbackenable(struct sdio_dev_s *dev, + sdio_eventset_t eventset); +static int stm32_registercallback(struct sdio_dev_s *dev, + worker_t callback, void *arg); + +/* DMA */ + +#ifdef CONFIG_STM32_SDIO_DMA +#ifdef CONFIG_ARCH_HAVE_SDIO_PREFLIGHT +static int stm32_dmapreflight(struct sdio_dev_s *dev, + const uint8_t *buffer, size_t buflen); +#endif +static int stm32_dmarecvsetup(struct sdio_dev_s *dev, + uint8_t *buffer, size_t buflen); +static int stm32_dmasendsetup(struct sdio_dev_s *dev, + const uint8_t *buffer, size_t buflen); +#endif + +/* Initialization/uninitialization/reset ************************************/ + +static void stm32_callback(void *arg); +static void stm32_default(void); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +struct stm32_dev_s g_sdiodev = +{ + .dev = + { +#ifdef CONFIG_SDIO_MUXBUS + .lock = stm32_lock, +#endif + .reset = stm32_reset, + .capabilities = stm32_capabilities, + .status = stm32_status, + .widebus = stm32_widebus, + .clock = stm32_clock, + .attach = stm32_attach, + .sendcmd = stm32_sendcmd, +#ifdef CONFIG_SDIO_BLOCKSETUP + .blocksetup = stm32_blocksetup, +#endif + .recvsetup = stm32_recvsetup, + .sendsetup = stm32_sendsetup, + .cancel = stm32_cancel, + .waitresponse = stm32_waitresponse, + .recv_r1 = stm32_recvshortcrc, + .recv_r2 = stm32_recvlong, + .recv_r3 = stm32_recvshort, + .recv_r4 = stm32_recvshort, + .recv_r5 = stm32_recvshortcrc, + .recv_r6 = stm32_recvshortcrc, + .recv_r7 = stm32_recvshort, + .waitenable = stm32_waitenable, + .eventwait = stm32_eventwait, + .callbackenable = stm32_callbackenable, + .registercallback = stm32_registercallback, +#ifdef CONFIG_SDIO_DMA +#ifdef CONFIG_STM32_SDIO_DMA +#ifdef CONFIG_ARCH_HAVE_SDIO_PREFLIGHT + .dmapreflight = stm32_dmapreflight, +#endif + .dmarecvsetup = stm32_dmarecvsetup, + .dmasendsetup = stm32_dmasendsetup, +#else +#ifdef CONFIG_ARCH_HAVE_SDIO_PREFLIGHT + .dmapreflight = NULL, +#endif + .dmarecvsetup = stm32_recvsetup, + .dmasendsetup = stm32_sendsetup, +#endif +#endif + }, + .waitsem = SEM_INITIALIZER(0), +}; + +/* Register logging support */ + +#ifdef CONFIG_SDIO_XFRDEBUG +static struct stm32_sampleregs_s g_sampleregs[DEBUG_NSAMPLES]; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_setclkcr + * + * Description: + * Modify oft-changed bits in the CLKCR register. Only the following bit- + * fields are changed: + * + * CLKDIV, PWRSAV, BYPASS, WIDBUS, NEGEDGE, and HWFC_EN + * + * Input Parameters: + * clkcr - A new CLKCR setting for the above mentions bits (other bits + * are ignored. + * + * Returned Value: + * None + * + ****************************************************************************/ + +static inline void stm32_setclkcr(uint32_t clkcr) +{ + uint32_t regval = getreg32(STM32_SDIO_CLKCR); + + /* Clear CLKDIV, PWRSAV, BYPASS, WIDBUS, NEGEDGE, HWFC_EN bits */ + + regval &= ~(SDIO_CLKCR_CLKDIV_MASK | SDIO_CLKCR_PWRSAV | + SDIO_CLKCR_BYPASS | SDIO_CLKCR_WIDBUS_MASK | + SDIO_CLKCR_NEGEDGE | SDIO_CLKCR_HWFC_EN | + SDIO_CLKCR_CLKEN); + + /* Replace with user provided settings */ + + clkcr &= (SDIO_CLKCR_CLKDIV_MASK | SDIO_CLKCR_PWRSAV | + SDIO_CLKCR_BYPASS | SDIO_CLKCR_WIDBUS_MASK | + SDIO_CLKCR_NEGEDGE | SDIO_CLKCR_HWFC_EN | + SDIO_CLKCR_CLKEN); + + regval |= clkcr; + putreg32(regval, STM32_SDIO_CLKCR); + + mcinfo("CLKCR: %08" PRIx32 " PWR: %08" PRIx32 "\n", + getreg32(STM32_SDIO_CLKCR), getreg32(STM32_SDIO_POWER)); +} + +/**************************************************************************** + * Name: stm32_configwaitints + * + * Description: + * Enable/disable SDIO interrupts needed to support the wait function + * + * Input Parameters: + * priv - A reference to the SDIO device state structure + * waitmask - The set of bits in the SDIO MASK register to set + * waitevents - Waited for events + * wkupevent - Wake-up events + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void stm32_configwaitints(struct stm32_dev_s *priv, uint32_t waitmask, + sdio_eventset_t waitevents, + sdio_eventset_t wkupevent) +{ + irqstate_t flags; +#ifdef CONFIG_MMCSD_SDIOWAIT_WRCOMPLETE + int pinset; +#endif + + /* Save all of the data and set the new interrupt mask in one, atomic + * operation. + */ + + flags = enter_critical_section(); + +#ifdef CONFIG_MMCSD_SDIOWAIT_WRCOMPLETE + if ((waitevents & SDIOWAIT_WRCOMPLETE) != 0) + { + pinset = GPIO_SDIO_D0 & (GPIO_PORT_MASK | GPIO_PIN_MASK); + pinset |= (GPIO_INPUT | GPIO_FLOAT | GPIO_EXTI); + + /* Arm the SDIO_D0 Ready and install Isr */ + + stm32_gpiosetevent(pinset, true, false, false, + stm32_rdyinterrupt, priv); + } + + /* Disarm SDIO_D0 ready and return it to SDIO D0 */ + + if ((wkupevent & SDIOWAIT_WRCOMPLETE) != 0) + { + stm32_gpiosetevent(GPIO_SDIO_D0, false, false, false, + NULL, NULL); + } +#endif + + priv->waitevents = waitevents; + priv->wkupevent = wkupevent; + priv->waitmask = waitmask; +#ifdef CONFIG_STM32_SDIO_DMA + priv->xfrflags = 0; +#endif + +#ifdef CONFIG_STM32_SDIO_CARD + putreg32(priv->xfrmask | priv->waitmask | priv->sdiointmask, + STM32_SDIO_MASK); +#else + putreg32(priv->xfrmask | priv->waitmask, STM32_SDIO_MASK); +#endif + + leave_critical_section(flags); +} + +/**************************************************************************** + * Name: stm32_configxfrints + * + * Description: + * Enable SDIO interrupts needed to support the data transfer event + * + * Input Parameters: + * priv - A reference to the SDIO device state structure + * xfrmask - The set of bits in the SDIO MASK register to set + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void stm32_configxfrints(struct stm32_dev_s *priv, uint32_t xfrmask) +{ + irqstate_t flags; + + flags = enter_critical_section(); + priv->xfrmask = xfrmask; +#ifdef CONFIG_STM32_SDIO_CARD + putreg32(priv->xfrmask | priv->waitmask | priv->sdiointmask, + STM32_SDIO_MASK); +#else + putreg32(priv->xfrmask | priv->waitmask, STM32_SDIO_MASK); +#endif + leave_critical_section(flags); +} + +/**************************************************************************** + * Name: stm32_setpwrctrl + * + * Description: + * Change the PWRCTRL field of the SDIO POWER register to turn the SDIO + * ON or OFF + * + * Input Parameters: + * clkcr - A new PWRCTRL setting + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void stm32_setpwrctrl(uint32_t pwrctrl) +{ + uint32_t regval; + + regval = getreg32(STM32_SDIO_POWER); + regval &= ~SDIO_POWER_PWRCTRL_MASK; + regval |= pwrctrl; + putreg32(regval, STM32_SDIO_POWER); +} + +/**************************************************************************** + * Name: stm32_sampleinit + * + * Description: + * Setup prior to collecting DMA samples + * + ****************************************************************************/ + +#ifdef CONFIG_SDIO_XFRDEBUG +static void stm32_sampleinit(void) +{ + memset(g_sampleregs, 0xff, + DEBUG_NSAMPLES * sizeof(struct stm32_sampleregs_s)); +} +#endif + +/**************************************************************************** + * Name: stm32_sdiosample + * + * Description: + * Sample SDIO registers + * + ****************************************************************************/ + +#ifdef CONFIG_SDIO_XFRDEBUG +static void stm32_sdiosample(struct stm32_sdioregs_s *regs) +{ + regs->power = (uint8_t)getreg32(STM32_SDIO_POWER); + regs->clkcr = (uint16_t)getreg32(STM32_SDIO_CLKCR); + regs->dctrl = (uint16_t)getreg32(STM32_SDIO_DCTRL); + regs->dtimer = getreg32(STM32_SDIO_DTIMER); + regs->dlen = getreg32(STM32_SDIO_DLEN); + regs->dcount = getreg32(STM32_SDIO_DCOUNT); + regs->sta = getreg32(STM32_SDIO_STA); + regs->mask = getreg32(STM32_SDIO_MASK); + regs->fifocnt = getreg32(STM32_SDIO_FIFOCNT); +} +#endif + +/**************************************************************************** + * Name: stm32_sample + * + * Description: + * Sample SDIO/DMA registers + * + ****************************************************************************/ + +#ifdef CONFIG_SDIO_XFRDEBUG +static void stm32_sample(struct stm32_dev_s *priv, int index) +{ + struct stm32_sampleregs_s *regs = &g_sampleregs[index]; + +#if defined(CONFIG_DEBUG_DMA_INFO) && defined(CONFIG_STM32_SDIO_DMA) + if (priv->dmamode) + { + stm32_dmasample(priv->dma, ®s->dma); + } +#endif + + stm32_sdiosample(®s->sdio); +} +#endif + +/**************************************************************************** + * Name: stm32_sdiodump + * + * Description: + * Dump one register sample + * + ****************************************************************************/ + +#ifdef CONFIG_SDIO_XFRDEBUG +static void stm32_sdiodump(struct stm32_sdioregs_s *regs, const char *msg) +{ + mcinfo("SDIO Registers: %s\n", msg); + mcinfo(" POWER[%08x]: %08x\n", STM32_SDIO_POWER, regs->power); + mcinfo(" CLKCR[%08x]: %08x\n", STM32_SDIO_CLKCR, regs->clkcr); + mcinfo(" DCTRL[%08x]: %08x\n", STM32_SDIO_DCTRL, regs->dctrl); + mcinfo(" DTIMER[%08x]: %08" PRIx32 "\n", + STM32_SDIO_DTIMER, regs->dtimer); + mcinfo(" DLEN[%08x]: %08" PRIx32 "\n", + STM32_SDIO_DLEN, regs->dlen); + mcinfo(" DCOUNT[%08x]: %08" PRIx32 "\n", + STM32_SDIO_DCOUNT, regs->dcount); + mcinfo(" STA[%08x]: %08" PRIx32 "\n", + STM32_SDIO_STA, regs->sta); + mcinfo(" MASK[%08x]: %08" PRIx32 "\n", + STM32_SDIO_MASK, regs->mask); + mcinfo("FIFOCNT[%08x]: %08" PRIx32 "\n", + STM32_SDIO_FIFOCNT, regs->fifocnt); +} +#endif + +/**************************************************************************** + * Name: stm32_dumpsample + * + * Description: + * Dump one register sample + * + ****************************************************************************/ + +#ifdef CONFIG_SDIO_XFRDEBUG +static void stm32_dumpsample(struct stm32_dev_s *priv, + struct stm32_sampleregs_s *regs, + const char *msg) +{ +#if defined(CONFIG_DEBUG_DMA_INFO) && defined(CONFIG_STM32_SDIO_DMA) + if (priv->dmamode) + { + stm32_dmadump(priv->dma, ®s->dma, msg); + } +#endif + + stm32_sdiodump(®s->sdio, msg); +} +#endif + +/**************************************************************************** + * Name: stm32_dumpsamples + * + * Description: + * Dump all sampled register data + * + ****************************************************************************/ + +#ifdef CONFIG_SDIO_XFRDEBUG +static void stm32_dumpsamples(struct stm32_dev_s *priv) +{ + stm32_dumpsample(priv, &g_sampleregs[SAMPLENDX_BEFORE_SETUP], + "Before setup"); + +#if defined(CONFIG_DEBUG_DMA_INFO) && defined(CONFIG_STM32_SDIO_DMA) + if (priv->dmamode) + { + stm32_dumpsample(priv, &g_sampleregs[SAMPLENDX_BEFORE_ENABLE], + "Before DMA enable"); + } +#endif + + stm32_dumpsample(priv, &g_sampleregs[SAMPLENDX_AFTER_SETUP], + "After setup"); + stm32_dumpsample(priv, &g_sampleregs[SAMPLENDX_END_TRANSFER], + "End of transfer"); + +#if defined(CONFIG_DEBUG_DMA_INFO) && defined(CONFIG_STM32_SDIO_DMA) + if (priv->dmamode) + { + stm32_dumpsample(priv, &g_sampleregs[SAMPLENDX_DMA_CALLBACK], + "DMA Callback"); + } +#endif +} +#endif + +/**************************************************************************** + * Name: stm32_dmacallback + * + * Description: + * Called when SDIO DMA completes + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_SDIO_DMA +static void stm32_dmacallback(DMA_HANDLE handle, uint8_t status, void *arg) +{ + struct stm32_dev_s *priv = (struct stm32_dev_s *)arg; + DEBUGASSERT(priv->dmamode); + sdio_eventset_t result; + + /* In the normal case, SDIO appears to handle the End-Of-Transfer interrupt + * first with the End-Of-DMA event occurring significantly later. On + * transfer errors, however, the DMA error will occur before the End-of- + * Transfer. + */ + + stm32_sample((struct stm32_dev_s *)arg, SAMPLENDX_DMA_CALLBACK); + + /* Get the result of the DMA transfer */ + + if ((status & DMA_STATUS_ERROR) != 0) + { + mcerr("ERROR: DMA error %02x, remaining: %d\n", + status, priv->remaining); + result = SDIOWAIT_ERROR; + } + else + { + result = SDIOWAIT_TRANSFERDONE; + } + + /* Then terminate the transfer if this completes all of the steps in the + * transfer OR if a DMA error occurred. In the non-error case, we should + * already have the SDIO transfer done interrupt. If not, the transfer + * will appropriately time out. + */ + + priv->xfrflags |= SDIO_DMADONE_FLAG; + if (priv->xfrflags == SDIO_ALLDONE || result == SDIOWAIT_ERROR) + { + stm32_endtransfer(priv, result); + } +} +#endif + +/**************************************************************************** + * Name: stm32_log2 + * + * Description: + * Take (approximate) log base 2 of the provided number (Only works if the + * provided number is a power of 2). + * + ****************************************************************************/ + +static uint8_t stm32_log2(uint16_t value) +{ + uint8_t log2 = 0; + + /* 0000 0000 0000 0001 -> return 0, + * 0000 0000 0000 001x -> return 1, + * 0000 0000 0000 01xx -> return 2, + * 0000 0000 0000 1xxx -> return 3, + * ... + * 1xxx xxxx xxxx xxxx -> return 15, + */ + + DEBUGASSERT(value > 0); + while (value != 1) + { + value >>= 1; + log2++; + } + + return log2; +} + +/**************************************************************************** + * Name: stm32_dataconfig + * + * Description: + * Configure the SDIO data path for the next data transfer + * + ****************************************************************************/ + +static void stm32_dataconfig(uint32_t timeout, uint32_t dlen, uint32_t dctrl) +{ + uint32_t clkdiv; + uint32_t regval; + uint32_t sdio_clk = IP_CLCK_FREQ; + + /* Enable data path using a timeout scaled to the SD_CLOCK (the card + * clock). + */ + + regval = getreg32(STM32_SDIO_CLKCR); + clkdiv = (regval & SDIO_CLKCR_CLKDIV_MASK) >> SDIO_CLKCR_CLKDIV_SHIFT; + if ((regval & SDIO_CLKCR_BYPASS) == 0) + { + sdio_clk = sdio_clk / (2 + clkdiv); + } + + /* Convert Timeout in Ms to SD_CLK counts */ + + timeout = timeout * (sdio_clk / 1000); + + putreg32(timeout, STM32_SDIO_DTIMER); /* Set DTIMER */ + putreg32(dlen, STM32_SDIO_DLEN); /* Set DLEN */ + + /* Configure DCTRL DTDIR, DTMODE, and DBLOCKSIZE fields and set the DTEN + * field + */ + + regval = getreg32(STM32_SDIO_DCTRL); + regval &= ~(SDIO_DCTRL_DTDIR | SDIO_DCTRL_DTMODE | + SDIO_DCTRL_DBLOCKSIZE_MASK); + dctrl &= (SDIO_DCTRL_DTDIR | SDIO_DCTRL_DTMODE | + SDIO_DCTRL_DBLOCKSIZE_MASK); + regval |= (dctrl | SDIO_DCTRL_DTEN | SDIO_DCTRL_SDIOEN); + putreg32(regval, STM32_SDIO_DCTRL); +} + +/**************************************************************************** + * Name: stm32_datadisable + * + * Description: + * Disable the SDIO data path setup by stm32_dataconfig() and + * disable DMA. + * + ****************************************************************************/ + +static void stm32_datadisable(void) +{ + uint32_t regval; + + /* Disable the data path */ + + /* Reset DTIMER */ + + putreg32(UINT32_MAX, STM32_SDIO_DTIMER); + + /* Reset DLEN */ + + putreg32(0, STM32_SDIO_DLEN); + + /* Reset DCTRL DTEN, DTDIR, DTMODE, DMAEN, and DBLOCKSIZE fields */ + + regval = getreg32(STM32_SDIO_DCTRL); + regval &= ~(SDIO_DCTRL_DTEN | SDIO_DCTRL_DTDIR | SDIO_DCTRL_DTMODE | + SDIO_DCTRL_DMAEN | SDIO_DCTRL_DBLOCKSIZE_MASK); + putreg32(regval, STM32_SDIO_DCTRL); +} + +/**************************************************************************** + * Name: stm32_sendfifo + * + * Description: + * Send SDIO data in interrupt mode + * + * Input Parameters: + * priv - An instance of the SDIO device interface + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void stm32_sendfifo(struct stm32_dev_s *priv) +{ + union + { + uint32_t w; + uint8_t b[4]; + } data; + + /* Loop while there is more data to be sent and the RX FIFO is not full */ + + while (priv->remaining > 0 && + (getreg32(STM32_SDIO_STA) & SDIO_STA_TXFIFOF) == 0) + { + /* Is there a full word remaining in the user buffer? */ + + if (priv->remaining >= sizeof(uint32_t)) + { + /* Yes, transfer the word to the TX FIFO */ + + data.w = *priv->buffer++; + priv->remaining -= sizeof(uint32_t); + } + else + { + /* No.. transfer just the bytes remaining in the user buffer, + * padding with zero as necessary to extend to a full word. + */ + + uint8_t *ptr = (uint8_t *)priv->remaining; + int i; + + data.w = 0; + for (i = 0; i < (int)priv->remaining; i++) + { + data.b[i] = *ptr++; + } + + /* Now the transfer is finished */ + + priv->remaining = 0; + } + + /* Put the word in the FIFO */ + + putreg32(data.w, STM32_SDIO_FIFO); + } +} + +/**************************************************************************** + * Name: stm32_recvfifo + * + * Description: + * Receive SDIO data in interrupt mode + * + * Input Parameters: + * priv - An instance of the SDIO device interface + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void stm32_recvfifo(struct stm32_dev_s *priv) +{ + union + { + uint32_t w; + uint8_t b[4]; + } data; + + /* Loop while there is space to store the data and there is more + * data available in the RX FIFO. + */ + + while (priv->remaining > 0 && + (getreg32(STM32_SDIO_STA) & SDIO_STA_RXDAVL) != 0) + { + /* Read the next word from the RX FIFO */ + + data.w = getreg32(STM32_SDIO_FIFO); + if (priv->remaining >= sizeof(uint32_t)) + { + /* Transfer the whole word to the user buffer */ + + *priv->buffer++ = data.w; + priv->remaining -= sizeof(uint32_t); + } + else + { + /* Transfer any trailing fractional word */ + + uint8_t *ptr = (uint8_t *)priv->buffer; + int i; + + for (i = 0; i < (int)priv->remaining; i++) + { + *ptr++ = data.b[i]; + } + + /* Now the transfer is finished */ + + priv->remaining = 0; + } + } +} + +/**************************************************************************** + * Name: stm32_eventtimeout + * + * Description: + * The watchdog timeout setup when the event wait start has expired without + * any other waited-for event occurring. + * + * Input Parameters: + * arg - The argument + * + * Returned Value: + * None + * + * Assumptions: + * Always called from the interrupt level with interrupts disabled. + * + ****************************************************************************/ + +static void stm32_eventtimeout(wdparm_t arg) +{ + struct stm32_dev_s *priv = (struct stm32_dev_s *)arg; + + /* There is always race conditions with timer expirations. */ + + DEBUGASSERT((priv->waitevents & SDIOWAIT_TIMEOUT) != 0 || + priv->wkupevent != 0); + + mcinfo("sta: %08" PRIx32 " enabled irq: %08" PRIx32 "\n", + getreg32(STM32_SDIO_STA), + getreg32(STM32_SDIO_MASK)); + + /* Is a data transfer complete event expected? */ + + if ((priv->waitevents & SDIOWAIT_TIMEOUT) != 0) + { + /* Yes.. wake up any waiting threads */ + +#ifdef CONFIG_MMCSD_SDIOWAIT_WRCOMPLETE + stm32_endwait(priv, SDIOWAIT_TIMEOUT | + (priv->waitevents & SDIOWAIT_WRCOMPLETE)); +#else + stm32_endwait(priv, SDIOWAIT_TIMEOUT); +#endif + mcerr("Timeout: remaining: %d\n", priv->remaining); + } +} + +/**************************************************************************** + * Name: stm32_endwait + * + * Description: + * Wake up a waiting thread if the waited-for event has occurred. + * + * Input Parameters: + * priv - An instance of the SDIO device interface + * wkupevent - The event that caused the wait to end + * + * Returned Value: + * None + * + * Assumptions: + * Always called from the interrupt level with interrupts disabled. + * + ****************************************************************************/ + +static void stm32_endwait(struct stm32_dev_s *priv, + sdio_eventset_t wkupevent) +{ + /* Cancel the watchdog timeout */ + + wd_cancel(&priv->waitwdog); + + /* Disable event-related interrupts */ + + stm32_configwaitints(priv, 0, 0, wkupevent); + + /* Wake up the waiting thread */ + + nxsem_post(&priv->waitsem); +} + +/**************************************************************************** + * Name: stm32_endtransfer + * + * Description: + * Terminate a transfer with the provided status. This function is called + * only from the SDIO interrupt handler when end-of-transfer conditions + * are detected. + * + * Input Parameters: + * priv - An instance of the SDIO device interface + * wkupevent - The event that caused the transfer to end + * + * Returned Value: + * None + * + * Assumptions: + * Always called from the interrupt level with interrupts disabled. + * + ****************************************************************************/ + +static void stm32_endtransfer(struct stm32_dev_s *priv, + sdio_eventset_t wkupevent) +{ + /* Disable all transfer related interrupts */ + + stm32_configxfrints(priv, 0); + + /* Clearing pending interrupt status on all transfer related interrupts */ + + putreg32(SDIO_XFRDONE_ICR, STM32_SDIO_ICR); + + /* If this was a DMA transfer, make sure that DMA is stopped */ + +#ifdef CONFIG_STM32_SDIO_DMA + if (priv->dmamode) + { + /* DMA debug instrumentation */ + + stm32_sample(priv, SAMPLENDX_END_TRANSFER); + + /* Make sure that the DMA is stopped (it will be stopped automatically + * on normal transfers, but not necessarily when the transfer + * terminates on an error condition). + */ + + stm32_dmastop(priv->dma); + } +#endif + + /* Mark the transfer finished */ + + priv->remaining = 0; + + /* Is a thread wait for these data transfer complete events? */ + + if ((priv->waitevents & wkupevent) != 0) + { + /* Yes.. wake up any waiting threads */ + + stm32_endwait(priv, wkupevent); + } +} + +/**************************************************************************** + * Name: stm32_rdyinterrupt + * + * Description: + * SDIO ready interrupt handler + * + * Input Parameters: + * dev - An instance of the SDIO device interface + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_MMCSD_SDIOWAIT_WRCOMPLETE +static int stm32_rdyinterrupt(int irq, void *context, void *arg) +{ + struct stm32_dev_s *priv = (struct stm32_dev_s *)arg; + + /* Avoid noise, check the state */ + + if (stm32_gpioread(GPIO_SDIO_D0)) + { + stm32_endwait(priv, SDIOWAIT_WRCOMPLETE); + } + + return OK; +} +#endif + +/**************************************************************************** + * Name: stm32_interrupt + * + * Description: + * SDIO interrupt handler + * + * Input Parameters: + * dev - An instance of the SDIO device interface + * + * Returned Value: + * None + * + ****************************************************************************/ + +static int stm32_interrupt(int irq, void *context, void *arg) +{ + struct stm32_dev_s *priv = &g_sdiodev; + uint32_t enabled; + uint32_t pending; + + /* Loop while there are pending interrupts. Check the SDIO status + * register. Mask out all bits that don't correspond to enabled + * interrupts. (This depends on the fact that bits are ordered + * the same in both the STA and MASK register). If there are non-zero + * bits remaining, then we have work to do here. + */ + + while ((enabled = getreg32(STM32_SDIO_STA) & + getreg32(STM32_SDIO_MASK)) != 0) + { + /* Handle in progress, interrupt driven data transfers ****************/ + + pending = enabled & priv->xfrmask; + if (pending != 0) + { +#ifdef CONFIG_STM32_SDIO_DMA + if (!priv->dmamode) +#endif + { + /* Is the RX FIFO half full or more? Is so then we must be + * processing a receive transaction. + */ + + if ((pending & SDIO_STA_RXFIFOHF) != 0) + { + /* Receive data from the RX FIFO */ + + stm32_recvfifo(priv); + } + + /* Otherwise, Is the transmit FIFO half empty or less? If so + * we must be processing a send transaction. NOTE: We can't + * be processing both! + */ + + else if ((pending & SDIO_STA_TXFIFOHE) != 0) + { + /* Send data via the TX FIFO */ + + stm32_sendfifo(priv); + } + } + + /* Handle data end events */ + + if ((pending & SDIO_STA_DATAEND) != 0) + { + /* Handle any data remaining the RX FIFO. If the RX FIFO is + * less than half full at the end of the transfer, then no + * half-full interrupt will be received. + */ + + /* Was this transfer performed in DMA mode? */ + +#ifdef CONFIG_STM32_SDIO_DMA + if (priv->dmamode) + { + /* Yes.. Terminate the transfers only if the DMA has also + * finished. + */ + + priv->xfrflags |= SDIO_XFRDONE_FLAG; + if (priv->xfrflags == SDIO_ALLDONE) + { + stm32_endtransfer(priv, SDIOWAIT_TRANSFERDONE); + } + + /* Otherwise, just disable further transfer interrupts and + * wait for the DMA complete event. + */ + + else + { + stm32_configxfrints(priv, 0); + } + } + else +#endif + { + /* Receive data from the RX FIFO */ + + stm32_recvfifo(priv); + + /* Then terminate the transfer */ + + stm32_endtransfer(priv, SDIOWAIT_TRANSFERDONE); + } + } + + /* Handle data block send/receive CRC failure */ + + else if ((pending & SDIO_STA_DCRCFAIL) != 0) + { + /* Terminate the transfer with an error */ + + mcerr("ERROR: Data block CRC failure, remaining: %d\n", + priv->remaining); + stm32_endtransfer(priv, + SDIOWAIT_TRANSFERDONE | SDIOWAIT_ERROR); + } + + /* Handle data timeout error */ + + else if ((pending & SDIO_STA_DTIMEOUT) != 0) + { + /* Terminate the transfer with an error */ + + mcerr("ERROR: Data timeout, remaining: %d\n", + priv->remaining); + stm32_endtransfer(priv, + SDIOWAIT_TRANSFERDONE | SDIOWAIT_TIMEOUT); + } + + /* Handle RX FIFO overrun error */ + + else if ((pending & SDIO_STA_RXOVERR) != 0) + { + /* Terminate the transfer with an error */ + + mcerr("ERROR: RX FIFO overrun, remaining: %d\n", + priv->remaining); + stm32_endtransfer(priv, + SDIOWAIT_TRANSFERDONE | SDIOWAIT_ERROR); + } + + /* Handle TX FIFO underrun error */ + + else if ((pending & SDIO_STA_TXUNDERR) != 0) + { + /* Terminate the transfer with an error */ + + mcerr("ERROR: TX FIFO underrun, remaining: %d\n", + priv->remaining); + stm32_endtransfer(priv, + SDIOWAIT_TRANSFERDONE | SDIOWAIT_ERROR); + } + + /* Handle start bit error */ + + else if ((pending & SDIO_STA_STBITERR) != 0) + { + /* Terminate the transfer with an error */ + + mcerr("ERROR: Start bit, remaining: %d\n", + priv->remaining); + stm32_endtransfer(priv, + SDIOWAIT_TRANSFERDONE | SDIOWAIT_ERROR); + } + } + + /* Handle wait events *************************************************/ + + pending = enabled & priv->waitmask; + if (pending != 0) + { + /* Is this a response completion event? */ + + if ((pending & SDIO_RESPDONE_STA) != 0) + { + /* Yes.. Is their a thread waiting for response done? */ + + if ((priv->waitevents & SDIOWAIT_RESPONSEDONE) != 0) + { + /* Yes.. wake the thread up */ + + putreg32(SDIO_RESPDONE_ICR | SDIO_CMDDONE_ICR, + STM32_SDIO_ICR); + stm32_endwait(priv, SDIOWAIT_RESPONSEDONE); + } + } + + /* Is this a command completion event? */ + + if ((pending & SDIO_CMDDONE_STA) != 0) + { + /* Yes.. Is their a thread waiting for command done? */ + + if ((priv->waitevents & SDIOWAIT_RESPONSEDONE) != 0) + { + /* Yes.. wake the thread up */ + + putreg32(SDIO_CMDDONE_ICR, STM32_SDIO_ICR); + stm32_endwait(priv, SDIOWAIT_CMDDONE); + } + } + } + +#ifdef CONFIG_STM32_SDIO_CARD + /* Handle SDIO card interrupt */ + + pending = enabled & priv->sdiointmask; + if (pending != 0) + { + putreg32(SDIO_STA_SDIOIT, STM32_SDIO_ICR); + + /* Perform callback */ + + if (priv->do_sdio_card) + { + priv->do_sdio_card(priv->do_sdio_arg); + } + } +#endif + } + + return OK; +} + +/**************************************************************************** + * Name: stm32_lock + * + * Description: + * Locks the bus. Function calls low-level multiplexed bus routines to + * resolve bus requests and acknowledgment issues. + * + * Input Parameters: + * dev - An instance of the SDIO device interface + * lock - TRUE to lock, FALSE to unlock. + * + * Returned Value: + * OK on success; a negated errno on failure + * + ****************************************************************************/ + +#ifdef CONFIG_SDIO_MUXBUS +static int stm32_lock(struct sdio_dev_s *dev, bool lock) +{ + /* Single SDIO instance so there is only one possibility. The multiplex + * bus is part of board support package. + */ + + /* FIXME: Implement the below function to support bus share: + * + * stm32_muxbus_sdio_lock(lock); + */ + + return OK; +} +#endif + +/**************************************************************************** + * Name: stm32_reset + * + * Description: + * Reset the SDIO controller. Undo all setup and initialization. + * + * Input Parameters: + * dev - An instance of the SDIO device interface + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void stm32_reset(struct sdio_dev_s *dev) +{ + struct stm32_dev_s *priv = (struct stm32_dev_s *)dev; + irqstate_t flags; + + /* Disable clocking */ + + flags = enter_critical_section(); + putreg32(0, SDIO_CLKCR_CLKEN_BB); + stm32_setpwrctrl(SDIO_POWER_PWRCTRL_OFF); + + /* Put SDIO registers in their default, reset state */ + + stm32_default(); + + /* Reset data */ + + priv->waitevents = 0; /* Set of events to be waited for */ + priv->waitmask = 0; /* Interrupt enables for event waiting */ + priv->wkupevent = 0; /* The event that caused the wakeup */ +#ifdef CONFIG_STM32_SDIO_DMA + priv->xfrflags = 0; /* Used to synchronize SDIO and DMA completion events */ +#endif + + wd_cancel(&priv->waitwdog); /* Cancel any timeouts */ + + /* Interrupt mode data transfer support */ + + priv->buffer = 0; /* Address of current R/W buffer */ + priv->remaining = 0; /* Number of bytes remaining in the transfer */ + priv->xfrmask = 0; /* Interrupt enables for data transfer */ + +#ifdef CONFIG_STM32_SDIO_CARD + priv->sdiointmask = 0; /* SDIO card in-band interrupt mask */ +#endif + + /* DMA data transfer support */ + + priv->widebus = false; /* Required for DMA support */ +#ifdef CONFIG_STM32_SDIO_DMA + priv->dmamode = false; /* true: DMA mode transfer */ +#endif + + /* Configure the SDIO peripheral */ + + stm32_setclkcr(STM32_CLCKCR_INIT | SDIO_CLKCR_CLKEN); + stm32_setpwrctrl(SDIO_POWER_PWRCTRL_ON); + leave_critical_section(flags); + + mcinfo("CLCKR: %08" PRIx32 " POWER: %08" PRIx32 "\n", + getreg32(STM32_SDIO_CLKCR), getreg32(STM32_SDIO_POWER)); +} + +/**************************************************************************** + * Name: stm32_capabilities + * + * Description: + * Get capabilities (and limitations) of the SDIO driver (optional) + * + * Input Parameters: + * dev - Device-specific state data + * + * Returned Value: + * Returns a bitset of status values (see SDIO_CAPS_* defines) + * + ****************************************************************************/ + +static sdio_capset_t stm32_capabilities(struct sdio_dev_s *dev) +{ + sdio_capset_t caps = 0; + +#ifdef CONFIG_STM32_SDIO_WIDTH_D1_ONLY + caps |= SDIO_CAPS_1BIT_ONLY; +#endif +#ifdef CONFIG_STM32_SDIO_DMA + caps |= SDIO_CAPS_DMASUPPORTED; +#endif + + return caps; +} + +/**************************************************************************** + * Name: stm32_status + * + * Description: + * Get SDIO status. + * + * Input Parameters: + * dev - Device-specific state data + * + * Returned Value: + * Returns a bitset of status values (see stm32_status_* defines) + * + ****************************************************************************/ + +static sdio_statset_t stm32_status(struct sdio_dev_s *dev) +{ + struct stm32_dev_s *priv = (struct stm32_dev_s *)dev; + return priv->cdstatus; +} + +/**************************************************************************** + * Name: stm32_widebus + * + * Description: + * Called after change in Bus width has been selected (via ACMD6). Most + * controllers will need to perform some special operations to work + * correctly in the new bus mode. + * + * Input Parameters: + * dev - An instance of the SDIO device interface + * wide - true: wide bus (4-bit) bus mode enabled + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void stm32_widebus(struct sdio_dev_s *dev, bool wide) +{ + struct stm32_dev_s *priv = (struct stm32_dev_s *)dev; + priv->widebus = wide; +} + +/**************************************************************************** + * Name: stm32_clock + * + * Description: + * Enable/disable SDIO clocking + * + * Input Parameters: + * dev - An instance of the SDIO device interface + * rate - Specifies the clocking to use (see enum sdio_clock_e) + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void stm32_clock(struct sdio_dev_s *dev, enum sdio_clock_e rate) +{ + uint32_t clckr; + + switch (rate) + { + /* Disable clocking (with default ID mode divisor) */ + + default: + case CLOCK_SDIO_DISABLED: + clckr = STM32_CLCKCR_INIT; + break; + + /* Enable in initial ID mode clocking (<400KHz) */ + + case CLOCK_IDMODE: + clckr = (STM32_CLCKCR_INIT | SDIO_CLKCR_CLKEN); + break; + + /* Enable in MMC normal operation clocking */ + + case CLOCK_MMC_TRANSFER: + clckr = (SDIO_CLKCR_MMCXFR | SDIO_CLKCR_CLKEN); + break; + + /* SD normal operation clocking (wide 4-bit mode) */ + + case CLOCK_SD_TRANSFER_4BIT: +#ifndef CONFIG_STM32_SDIO_WIDTH_D1_ONLY + clckr = (SDIO_CLCKR_SDWIDEXFR | SDIO_CLKCR_CLKEN); + break; +#endif + + /* SD normal operation clocking (narrow 1-bit mode) */ + + case CLOCK_SD_TRANSFER_1BIT: + clckr = (SDIO_CLCKR_SDXFR | SDIO_CLKCR_CLKEN); + break; + } + + /* Set the new clock frequency along with the clock enable/disable bit */ + + stm32_setclkcr(clckr); +} + +/**************************************************************************** + * Name: stm32_attach + * + * Description: + * Attach and prepare interrupts + * + * Input Parameters: + * dev - An instance of the SDIO device interface + * + * Returned Value: + * OK on success; A negated errno on failure. + * + ****************************************************************************/ + +static int stm32_attach(struct sdio_dev_s *dev) +{ + int ret; + + /* Attach the SDIO interrupt handler */ + + ret = irq_attach(STM32_IRQ_SDIO, stm32_interrupt, NULL); + if (ret == OK) + { + /* Disable all interrupts at the SDIO controller and clear static + * interrupt flags + */ + + putreg32(SDIO_MASK_RESET, STM32_SDIO_MASK); + putreg32(SDIO_ICR_STATICFLAGS, STM32_SDIO_ICR); + + /* Enable SDIO interrupts at the NVIC. They can now be enabled at + * the SDIO controller as needed. + */ + + up_enable_irq(STM32_IRQ_SDIO); + } + + return ret; +} + +/**************************************************************************** + * Name: stm32_sendcmd + * + * Description: + * Send the SDIO command + * + * Input Parameters: + * dev - An instance of the SDIO device interface + * cmd - The command to send (32-bits, encoded) + * arg - 32-bit argument required with some commands + * + * Returned Value: + * None + * + ****************************************************************************/ + +static int stm32_sendcmd(struct sdio_dev_s *dev, uint32_t cmd, + uint32_t arg) +{ + uint32_t regval; + uint32_t cmdidx; + + /* Set the SDIO Argument value */ + + putreg32(arg, STM32_SDIO_ARG); + + /* Clear CMDINDEX, WAITRESP, WAITINT, WAITPEND, and CPSMEN bits */ + + regval = getreg32(STM32_SDIO_CMD); + regval &= ~(SDIO_CMD_CMDINDEX_MASK | SDIO_CMD_WAITRESP_MASK | + SDIO_CMD_WAITINT | SDIO_CMD_WAITPEND | SDIO_CMD_CPSMEN); + + /* Set WAITRESP bits */ + + switch (cmd & MMCSD_RESPONSE_MASK) + { + case MMCSD_NO_RESPONSE: + regval |= SDIO_CMD_NORESPONSE; + break; + + case MMCSD_R1_RESPONSE: + case MMCSD_R1B_RESPONSE: + case MMCSD_R3_RESPONSE: + case MMCSD_R4_RESPONSE: + case MMCSD_R5_RESPONSE: + case MMCSD_R6_RESPONSE: + case MMCSD_R7_RESPONSE: + regval |= SDIO_CMD_SHORTRESPONSE; + break; + + case MMCSD_R2_RESPONSE: + regval |= SDIO_CMD_LONGRESPONSE; + break; + } + + /* Set CPSMEN and the command index */ + + cmdidx = (cmd & MMCSD_CMDIDX_MASK) >> MMCSD_CMDIDX_SHIFT; + regval |= cmdidx | SDIO_CMD_CPSMEN; + + mcinfo("cmd: %08" PRIx32 " arg: %08" PRIx32 " regval: %08" PRIx32 + " enabled irq: %08" PRIx32 "\n", + cmd, arg, regval, getreg32(STM32_SDIO_MASK)); + + /* Write the SDIO CMD */ + + putreg32(SDIO_RESPDONE_ICR | SDIO_CMDDONE_ICR, STM32_SDIO_ICR); + putreg32(regval, STM32_SDIO_CMD); + return OK; +} + +/**************************************************************************** + * Name: stm32_blocksetup + * + * Description: + * Configure block size and the number of blocks for next transfer + * + * Input Parameters: + * dev - An instance of the SDIO device interface + * blocklen - The selected block size. + * nblocklen - The number of blocks to transfer + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_SDIO_BLOCKSETUP +static void stm32_blocksetup(struct sdio_dev_s *dev, + unsigned int blocklen, unsigned int nblocks) +{ + struct stm32_dev_s *priv = (struct stm32_dev_s *)dev; + + /* Configure block size for next transfer */ + + priv->block_size = stm32_log2(blocklen); +} +#endif + +/**************************************************************************** + * Name: stm32_recvsetup + * + * Description: + * Setup hardware in preparation for data transfer from the card in non-DMA + * (interrupt driven mode). This method will do whatever controller setup + * is necessary. This would be called for SD memory just BEFORE sending + * CMD13 (SEND_STATUS), CMD17 (READ_SINGLE_BLOCK), CMD18 + * (READ_MULTIPLE_BLOCKS), ACMD51 (SEND_SCR), etc. Normally, + * SDIO_WAITEVENT will be called to receive the indication that the + * transfer is complete. + * + * Input Parameters: + * dev - An instance of the SDIO device interface + * buffer - Address of the buffer in which to receive the data + * nbytes - The number of bytes in the transfer + * + * Returned Value: + * Number of bytes sent on success; a negated errno on failure + * + ****************************************************************************/ + +static int stm32_recvsetup(struct sdio_dev_s *dev, uint8_t *buffer, + size_t nbytes) +{ + struct stm32_dev_s *priv = (struct stm32_dev_s *)dev; + uint32_t dblocksize; + + DEBUGASSERT(priv != NULL && buffer != NULL && nbytes > 0); + DEBUGASSERT(((uint32_t)buffer & 3) == 0); + + /* Reset the DPSM configuration */ + + stm32_datadisable(); + stm32_sampleinit(); + stm32_sample(priv, SAMPLENDX_BEFORE_SETUP); + + /* Save the destination buffer information for use by the interrupt + * handler. + */ + + priv->buffer = (uint32_t *)buffer; + priv->remaining = nbytes; +#ifdef CONFIG_STM32_SDIO_DMA + priv->dmamode = false; +#endif + + /* Then set up the SDIO data path */ + +#ifdef CONFIG_SDIO_BLOCKSETUP + if (priv->block_size != STM32_SDIO_USE_DEFAULT_BLOCKSIZE) + { + dblocksize = priv->block_size << SDIO_DCTRL_DBLOCKSIZE_SHIFT; + } + else +#endif + { + dblocksize = stm32_log2(nbytes) << SDIO_DCTRL_DBLOCKSIZE_SHIFT; + } + + stm32_dataconfig(SDIO_DTIMER_DATATIMEOUT_MS, nbytes, + dblocksize | SDIO_DCTRL_DTDIR); + + /* And enable interrupts */ + + stm32_configxfrints(priv, SDIO_RECV_MASK); + stm32_sample(priv, SAMPLENDX_AFTER_SETUP); + return OK; +} + +/**************************************************************************** + * Name: stm32_sendsetup + * + * Description: + * Setup hardware in preparation for data transfer from the card. This + * method will do whatever controller setup is necessary. This would be + * called for SD memory just AFTER sending CMD24 (WRITE_BLOCK), CMD25 + * (WRITE_MULTIPLE_BLOCK), ... and before SDIO_SENDDATA is called. + * + * Input Parameters: + * dev - An instance of the SDIO device interface + * buffer - Address of the buffer containing the data to send + * nbytes - The number of bytes in the transfer + * + * Returned Value: + * Number of bytes sent on success; a negated errno on failure + * + ****************************************************************************/ + +static int stm32_sendsetup(struct sdio_dev_s *dev, + const uint8_t *buffer, size_t nbytes) +{ + struct stm32_dev_s *priv = (struct stm32_dev_s *)dev; + uint32_t dblocksize; + + DEBUGASSERT(priv != NULL && buffer != NULL && nbytes > 0); + DEBUGASSERT(((uint32_t)buffer & 3) == 0); + + /* Reset the DPSM configuration */ + + stm32_datadisable(); + stm32_sampleinit(); + stm32_sample(priv, SAMPLENDX_BEFORE_SETUP); + + /* Save the source buffer information for use by the interrupt handler */ + + priv->buffer = (uint32_t *)buffer; + priv->remaining = nbytes; +#ifdef CONFIG_STM32_SDIO_DMA + priv->dmamode = false; +#endif + + /* Then set up the SDIO data path */ + +#ifdef CONFIG_SDIO_BLOCKSETUP + if (priv->block_size != STM32_SDIO_USE_DEFAULT_BLOCKSIZE) + { + dblocksize = priv->block_size << SDIO_DCTRL_DBLOCKSIZE_SHIFT; + } + else +#endif + { + dblocksize = stm32_log2(nbytes) << SDIO_DCTRL_DBLOCKSIZE_SHIFT; + } + + stm32_dataconfig(SDIO_DTIMER_DATATIMEOUT_MS, nbytes, dblocksize); + + /* Enable TX interrupts */ + + stm32_configxfrints(priv, SDIO_SEND_MASK); + stm32_sample(priv, SAMPLENDX_AFTER_SETUP); + return OK; +} + +/**************************************************************************** + * Name: stm32_cancel + * + * Description: + * Cancel the data transfer setup of SDIO_RECVSETUP, SDIO_SENDSETUP, + * SDIO_DMARECVSETUP or SDIO_DMASENDSETUP. This must be called to cancel + * the data transfer setup if, for some reason, you cannot perform the + * transfer. + * + * Input Parameters: + * dev - An instance of the SDIO device interface + * + * Returned Value: + * OK is success; a negated errno on failure + * + ****************************************************************************/ + +static int stm32_cancel(struct sdio_dev_s *dev) +{ + struct stm32_dev_s *priv = (struct stm32_dev_s *)dev; + + /* Disable all transfer- and event- related interrupts */ + + stm32_configxfrints(priv, 0); + stm32_configwaitints(priv, 0, 0, 0); + + /* Clearing pending interrupt status on all transfer- and event- related + * interrupts + */ + + putreg32(SDIO_WAITALL_ICR, STM32_SDIO_ICR); + + /* Cancel any watchdog timeout */ + + wd_cancel(&priv->waitwdog); + + /* If this was a DMA transfer, make sure that DMA is stopped */ + +#ifdef CONFIG_STM32_SDIO_DMA + if (priv->dmamode) + { + /* Make sure that the DMA is stopped (it will be stopped automatically + * on normal transfers, but not necessarily when the transfer + * terminates on an error condition. + */ + + stm32_dmastop(priv->dma); + } +#endif + + /* Mark no transfer in progress */ + + priv->remaining = 0; + return OK; +} + +/**************************************************************************** + * Name: stm32_waitresponse + * + * Description: + * Poll-wait for the response to the last command to be ready. + * + * Input Parameters: + * dev - An instance of the SDIO device interface + * cmd - The command that was sent. See 32-bit command definitions above. + * + * Returned Value: + * OK is success; a negated errno on failure + * + ****************************************************************************/ + +static int stm32_waitresponse(struct sdio_dev_s *dev, uint32_t cmd) +{ + int32_t timeout; + uint32_t events; + + switch (cmd & MMCSD_RESPONSE_MASK) + { + case MMCSD_NO_RESPONSE: + events = SDIO_CMDDONE_STA; + timeout = SDIO_CMDTIMEOUT; + break; + + case MMCSD_R1_RESPONSE: + case MMCSD_R1B_RESPONSE: + case MMCSD_R2_RESPONSE: + case MMCSD_R4_RESPONSE: + case MMCSD_R5_RESPONSE: + case MMCSD_R6_RESPONSE: + events = SDIO_RESPDONE_STA; + timeout = SDIO_LONGTIMEOUT; + break; + + case MMCSD_R3_RESPONSE: + case MMCSD_R7_RESPONSE: + events = SDIO_RESPDONE_STA; + timeout = SDIO_CMDTIMEOUT; + break; + + default: + return -EINVAL; + } + + /* Then wait for the response (or timeout) */ + + while ((getreg32(STM32_SDIO_STA) & events) == 0) + { + if (--timeout <= 0) + { + mcerr("ERROR: Timeout cmd: %08" PRIx32 " events: %08" PRIx32 + " STA: %08" PRIx32 "\n", + cmd, events, getreg32(STM32_SDIO_STA)); + + return -ETIMEDOUT; + } + } + + putreg32(SDIO_CMDDONE_ICR, STM32_SDIO_ICR); + return OK; +} + +/**************************************************************************** + * Name: stm32_recv* + * + * Description: + * Receive response to SDIO command. Only the critical payload is + * returned -- that is 32 bits for 48 bit status and 128 bits for 136 bit + * status. The driver implementation should verify the correctness of + * the remaining, non-returned bits (CRCs, CMD index, etc.). + * + * Input Parameters: + * dev - An instance of the SDIO device interface + * Rx - Buffer in which to receive the response + * + * Returned Value: + * Number of bytes sent on success; a negated errno on failure. Here a + * failure means only a failure to obtain the requested response (due to + * transport problem -- timeout, CRC, etc.). The implementation only + * assures that the response is returned intacta and does not check errors + * within the response itself. + * + ****************************************************************************/ + +static int stm32_recvshortcrc(struct sdio_dev_s *dev, uint32_t cmd, + uint32_t *rshort) +{ +#ifdef CONFIG_DEBUG_MEMCARD_INFO + uint32_t respcmd; +#endif + uint32_t regval; + int ret = OK; + + /* R1 Command response (48-bit) + * 47 0 Start bit + * 46 0 Transmission bit (0=from card) + * 45:40 bit5 - bit0 Command index (0-63) + * 39:8 bit31 - bit0 32-bit card status + * 7:1 bit6 - bit0 CRC7 + * 0 1 End bit + * + * R1b Identical to R1 with the additional busy signaling via the data + * line. + * + * R6 Published RCA Response (48-bit, SD card only) + * 47 0 Start bit + * 46 0 Transmission bit (0=from card) + * 45:40 bit5 - bit0 Command index (0-63) + * 39:8 bit31 - bit0 32-bit Argument Field, consisting of: + * [31:16] New published RCA of card + * [15:0] Card status bits {23,22,19,12:0} + * 7:1 bit6 - bit0 CRC7 + * 0 1 End bit + */ + +#ifdef CONFIG_DEBUG_MEMCARD_INFO + if (!rshort) + { + mcerr("ERROR: rshort=NULL\n"); + ret = -EINVAL; + } + + /* Check that this is the correct response to this command */ + + else if ((cmd & MMCSD_RESPONSE_MASK) != MMCSD_R1_RESPONSE && + (cmd & MMCSD_RESPONSE_MASK) != MMCSD_R1B_RESPONSE && + (cmd & MMCSD_RESPONSE_MASK) != MMCSD_R5_RESPONSE && + (cmd & MMCSD_RESPONSE_MASK) != MMCSD_R6_RESPONSE) + { + mcerr("ERROR: Wrong response CMD=%08" PRIx32 "\n", cmd); + ret = -EINVAL; + } + else +#endif + { + /* Check if a timeout or CRC error occurred */ + + regval = getreg32(STM32_SDIO_STA); + if ((regval & SDIO_STA_CTIMEOUT) != 0) + { + mcerr("ERROR: Command timeout: %08" PRIx32 "\n", regval); + ret = -ETIMEDOUT; + } + else if ((regval & SDIO_STA_CCRCFAIL) != 0) + { + mcerr("ERROR: CRC failure: %08" PRIx32 "\n", regval); + ret = -EIO; + } +#ifdef CONFIG_DEBUG_MEMCARD_INFO + else + { + /* Check response received is of desired command */ + + respcmd = getreg32(STM32_SDIO_RESPCMD); + if ((uint8_t)(respcmd & SDIO_RESPCMD_MASK) != + (cmd & MMCSD_CMDIDX_MASK)) + { + mcerr("ERROR: RESCMD=%02" PRIx32 " CMD=%08" PRIx32 "\n", + respcmd, cmd); + ret = -EINVAL; + } + } +#endif + } + + /* Clear all pending message completion events and return the R1/R6 + * response. + */ + + putreg32(SDIO_RESPDONE_ICR | SDIO_CMDDONE_ICR, STM32_SDIO_ICR); + *rshort = getreg32(STM32_SDIO_RESP1); + return ret; +} + +static int stm32_recvlong(struct sdio_dev_s *dev, uint32_t cmd, + uint32_t rlong[4]) +{ + uint32_t regval; + int ret = OK; + + /* R2 CID, CSD register (136-bit) + * 135 0 Start bit + * 134 0 Transmission bit (0=from card) + * 133:128 bit5 - bit0 Reserved + * 127:1 bit127 - bit1 127-bit CID or CSD register + * (including internal CRC) + * 0 1 End bit + */ + +#ifdef CONFIG_DEBUG_MEMCARD_INFO + /* Check that R1 is the correct response to this command */ + + if ((cmd & MMCSD_RESPONSE_MASK) != MMCSD_R2_RESPONSE) + { + mcerr("ERROR: Wrong response CMD=%08" PRIx32 "\n", cmd); + ret = -EINVAL; + } + else +#endif + { + /* Check if a timeout or CRC error occurred */ + + regval = getreg32(STM32_SDIO_STA); + if (regval & SDIO_STA_CTIMEOUT) + { + mcerr("ERROR: Timeout STA: %08" PRIx32 "\n", regval); + ret = -ETIMEDOUT; + } + else if (regval & SDIO_STA_CCRCFAIL) + { + mcerr("ERROR: CRC fail STA: %08" PRIx32 "\n", regval); + ret = -EIO; + } + } + + /* Return the long response */ + + putreg32(SDIO_RESPDONE_ICR | SDIO_CMDDONE_ICR, STM32_SDIO_ICR); + if (rlong) + { + rlong[0] = getreg32(STM32_SDIO_RESP1); + rlong[1] = getreg32(STM32_SDIO_RESP2); + rlong[2] = getreg32(STM32_SDIO_RESP3); + rlong[3] = getreg32(STM32_SDIO_RESP4); + } + + return ret; +} + +static int stm32_recvshort(struct sdio_dev_s *dev, uint32_t cmd, + uint32_t *rshort) +{ + uint32_t regval; + int ret = OK; + + /* R3 OCR (48-bit) + * 47 0 Start bit + * 46 0 Transmission bit (0=from card) + * 45:40 bit5 - bit0 Reserved + * 39:8 bit31 - bit0 32-bit OCR register + * 7:1 bit6 - bit0 Reserved + * 0 1 End bit + */ + + /* Check that this is the correct response to this command */ + +#ifdef CONFIG_DEBUG_MEMCARD_INFO + if ((cmd & MMCSD_RESPONSE_MASK) != MMCSD_R3_RESPONSE && + (cmd & MMCSD_RESPONSE_MASK) != MMCSD_R4_RESPONSE && + (cmd & MMCSD_RESPONSE_MASK) != MMCSD_R7_RESPONSE) + { + mcerr("ERROR: Wrong response CMD=%08" PRIx32 "\n", cmd); + ret = -EINVAL; + } + else +#endif + { + /* Check if a timeout occurred (Apparently a CRC error can terminate + * a good response) + */ + + regval = getreg32(STM32_SDIO_STA); + if (regval & SDIO_STA_CTIMEOUT) + { + mcerr("ERROR: Timeout STA: %08" PRIx32 "\n", regval); + ret = -ETIMEDOUT; + } + } + + putreg32(SDIO_RESPDONE_ICR | SDIO_CMDDONE_ICR, STM32_SDIO_ICR); + if (rshort) + { + *rshort = getreg32(STM32_SDIO_RESP1); + } + + return ret; +} + +/**************************************************************************** + * Name: stm32_waitenable + * + * Description: + * Enable/disable of a set of SDIO wait events. This is part of the + * the SDIO_WAITEVENT sequence. The set of to-be-waited-for events is + * configured before calling stm32_eventwait. This is done in this way + * to help the driver to eliminate race conditions between the command + * setup and the subsequent events. + * + * The enabled events persist until either (1) SDIO_WAITENABLE is called + * again specifying a different set of wait events, or (2) SDIO_EVENTWAIT + * returns. + * + * Input Parameters: + * dev - An instance of the SDIO device interface + * eventset - A bitset of events to enable or disable (see SDIOWAIT_* + * definitions). 0=disable; 1=enable. + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void stm32_waitenable(struct sdio_dev_s *dev, + sdio_eventset_t eventset, uint32_t timeout) +{ + struct stm32_dev_s *priv = (struct stm32_dev_s *)dev; + uint32_t waitmask; + + DEBUGASSERT(priv != NULL); + + /* Disable event-related interrupts */ + + stm32_configwaitints(priv, 0, 0, 0); + + /* Select the interrupt mask that will give us the appropriate wakeup + * interrupts. + */ + +#if defined(CONFIG_MMCSD_SDIOWAIT_WRCOMPLETE) + if ((eventset & SDIOWAIT_WRCOMPLETE) != 0) + { + /* eventset carries this */ + + waitmask = 0; + } + else +#endif + { + waitmask = 0; + if ((eventset & SDIOWAIT_CMDDONE) != 0) + { + waitmask |= SDIO_CMDDONE_MASK; + } + + if ((eventset & SDIOWAIT_RESPONSEDONE) != 0) + { + waitmask |= SDIO_RESPDONE_MASK; + } + + if ((eventset & SDIOWAIT_TRANSFERDONE) != 0) + { + waitmask |= SDIO_XFRDONE_MASK; + } + + /* Enable event-related interrupts */ + + putreg32(SDIO_WAITALL_ICR, STM32_SDIO_ICR); + } + + stm32_configwaitints(priv, waitmask, eventset, 0); + + /* Check if the timeout event is specified in the event set */ + + if ((priv->waitevents & SDIOWAIT_TIMEOUT) != 0) + { + int delay; + int ret; + + /* Yes.. Handle a cornercase: The user request a timeout event but + * with timeout == 0? + */ + + if (!timeout) + { + priv->wkupevent = SDIOWAIT_TIMEOUT; + return; + } + + /* Start the watchdog timer */ + + delay = MSEC2TICK(timeout); + ret = wd_start(&priv->waitwdog, delay, + stm32_eventtimeout, (wdparm_t)priv); + if (ret < 0) + { + mcerr("ERROR: wd_start failed: %d\n", ret); + } + } +} + +/**************************************************************************** + * Name: stm32_eventwait + * + * Description: + * Wait for one of the enabled events to occur (or a timeout). Note that + * all events enabled by SDIO_WAITEVENTS are disabled when stm32_eventwait + * returns. SDIO_WAITEVENTS must be called again before stm32_eventwait + * can be used again. + * + * Input Parameters: + * dev - An instance of the SDIO device interface + * timeout - Maximum time in milliseconds to wait. Zero means immediate + * timeout with no wait. The timeout value is ignored if + * SDIOWAIT_TIMEOUT is not included in the waited-for eventset. + * + * Returned Value: + * Event set containing the event(s) that ended the wait. Should always + * be non-zero. All events are disabled after the wait concludes. + * + ****************************************************************************/ + +static sdio_eventset_t stm32_eventwait(struct sdio_dev_s *dev) +{ + struct stm32_dev_s *priv = (struct stm32_dev_s *)dev; + sdio_eventset_t wkupevent = 0; + irqstate_t flags; + int ret; + + /* There is a race condition here... the event may have completed before + * we get here. In this case waitevents will be zero, but wkupevents will + * be non-zero (and, hopefully, the semaphore count will also be non-zero. + */ + + flags = enter_critical_section(); + +#if defined(CONFIG_MMCSD_SDIOWAIT_WRCOMPLETE) + /* A card ejected while in SDIOWAIT_WRCOMPLETE can lead to a + * condition where there is no waitevents set and no wkupevent + */ + + if (priv->waitevents == 0 && priv->wkupevent == 0) + { + wkupevent = SDIOWAIT_ERROR; + goto errout_with_waitints; + } + +#else + DEBUGASSERT(priv->waitevents != 0 || priv->wkupevent != 0); +#endif + +#if defined(CONFIG_MMCSD_SDIOWAIT_WRCOMPLETE) + if ((priv->waitevents & SDIOWAIT_WRCOMPLETE) != 0) + { + /* Atomically read pin to see if ready (true) and determine if ISR + * fired. If Pin is ready and if ISR did NOT fire end the wait here. + */ + + if (stm32_gpioread(GPIO_SDIO_D0) && + (priv->wkupevent & SDIOWAIT_WRCOMPLETE) == 0) + { + stm32_endwait(priv, SDIOWAIT_WRCOMPLETE); + } + } +#endif + + /* Loop until the event (or the timeout occurs). Race conditions are + * avoided by calling stm32_waitenable prior to triggering the logic that + * will cause the wait to terminate. Under certain race conditions, the + * waited-for may have already occurred before this function was called! + */ + + for (; ; ) + { + /* Wait for an event in event set to occur. If this the event has + * already occurred, then the semaphore will already have been + * incremented and there will be no wait. + */ + + ret = nxsem_wait_uninterruptible(&priv->waitsem); + if (ret < 0) + { + /* Task canceled. Cancel the wdog (assuming it was started) and + * return an SDIO error. + */ + + wd_cancel(&priv->waitwdog); + wkupevent = SDIOWAIT_ERROR; + goto errout_with_waitints; + } + + wkupevent = priv->wkupevent; + + /* Check if the event has occurred. When the event has occurred, then + * evenset will be set to 0 and wkupevent will be set to a nonzero + * value. + */ + + if (wkupevent != 0) + { + /* Yes... break out of the loop with wkupevent non-zero */ + + break; + } + } + + /* Disable event-related interrupts */ + +errout_with_waitints: + stm32_configwaitints(priv, 0, 0, 0); +#ifdef CONFIG_STM32_SDIO_DMA + priv->xfrflags = 0; +#endif + + leave_critical_section(flags); + stm32_dumpsamples(priv); + return wkupevent; +} + +/**************************************************************************** + * Name: stm32_callbackenable + * + * Description: + * Enable/disable of a set of SDIO callback events. This is part of the + * the SDIO callback sequence. The set of events is configured to enabled + * callbacks to the function provided in stm32_registercallback. + * + * Events are automatically disabled once the callback is performed and no + * further callback events will occur until they are again enabled by + * calling this method. + * + * Input Parameters: + * dev - An instance of the SDIO device interface + * eventset - A bitset of events to enable or disable (see SDIOMEDIA_* + * definitions). 0=disable; 1=enable. + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void stm32_callbackenable(struct sdio_dev_s *dev, + sdio_eventset_t eventset) +{ + struct stm32_dev_s *priv = (struct stm32_dev_s *)dev; + + mcinfo("eventset: %02x\n", eventset); + DEBUGASSERT(priv != NULL); + + priv->cbevents = eventset; + stm32_callback(priv); +} + +/**************************************************************************** + * Name: stm32_registercallback + * + * Description: + * Register a callback that that will be invoked on any media status + * change. Callbacks should not be made from interrupt handlers, rather + * interrupt level events should be handled by calling back on the work + * thread. + * + * When this method is called, all callbacks should be disabled until they + * are enabled via a call to SDIO_CALLBACKENABLE + * + * Input Parameters: + * dev - Device-specific state data + * callback - The function to call on the media change + * arg - A caller provided value to return with the callback + * + * Returned Value: + * 0 on success; negated errno on failure. + * + ****************************************************************************/ + +static int stm32_registercallback(struct sdio_dev_s *dev, + worker_t callback, void *arg) +{ + struct stm32_dev_s *priv = (struct stm32_dev_s *)dev; + + /* Disable callbacks and register this callback and is argument */ + + mcinfo("Register %p(%p)\n", callback, arg); + DEBUGASSERT(priv != NULL); + + priv->cbevents = 0; + priv->cbarg = arg; + priv->callback = callback; + return OK; +} + +/**************************************************************************** + * Name: stm32_dmapreflight + * + * Description: + * Preflight an SDIO DMA operation. If the buffer is not well-formed for + * SDIO DMA transfer (alignment, size, etc.) returns an error. + * + * Input Parameters: + * dev - An instance of the SDIO device interface + * buffer - The memory to DMA to/from + * buflen - The size of the DMA transfer in bytes + * + * Returned Value: + * OK on success; a negated errno on failure + ****************************************************************************/ + +#if defined(CONFIG_STM32_SDIO_DMA) && defined(CONFIG_ARCH_HAVE_SDIO_PREFLIGHT) +static int stm32_dmapreflight(struct sdio_dev_s *dev, + const uint8_t *buffer, size_t buflen) +{ +#if !defined(CONFIG_STM32_STM32F4XXX) + struct stm32_dev_s *priv = (struct stm32_dev_s *)dev; + + DEBUGASSERT(priv != NULL && buffer != NULL && buflen > 0); + + /* Wide bus operation is required for DMA */ + + if (!priv->widebus) + { + return -EINVAL; + } +#endif + + /* DMA must be possible to the buffer */ + + if (!stm32_dmacapable((uintptr_t)buffer, (buflen + 3) >> 2, + SDIO_RXDMA32_CONFIG)) + { + return -EFAULT; + } + + return 0; +} +#endif + +/**************************************************************************** + * Name: stm32_dmarecvsetup + * + * Description: + * Setup to perform a read DMA. If the processor supports a data cache, + * then this method will also make sure that the contents of the DMA memory + * and the data cache are coherent. For read transfers this may mean + * invalidating the data cache. + * + * Input Parameters: + * dev - An instance of the SDIO device interface + * buffer - The memory to DMA from + * buflen - The size of the DMA transfer in bytes + * + * Returned Value: + * OK on success; a negated errno on failure + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_SDIO_DMA +static int stm32_dmarecvsetup(struct sdio_dev_s *dev, + uint8_t *buffer, size_t buflen) +{ + struct stm32_dev_s *priv = (struct stm32_dev_s *)dev; + uint32_t dblocksize; + + DEBUGASSERT(priv != NULL && buffer != NULL && buflen > 0); +#ifdef CONFIG_ARCH_HAVE_SDIO_PREFLIGHT + DEBUGASSERT(stm32_dmapreflight(dev, buffer, buflen) == 0); +#endif + + /* Reset the DPSM configuration */ + + stm32_datadisable(); + + /* Initialize register sampling */ + + stm32_sampleinit(); + stm32_sample(priv, SAMPLENDX_BEFORE_SETUP); + + /* Save the destination buffer information for use by the interrupt + * handler. + */ + + priv->buffer = (uint32_t *)buffer; + priv->remaining = buflen; + priv->dmamode = true; + + /* Then set up the SDIO data path */ + +#ifdef CONFIG_SDIO_BLOCKSETUP + if (priv->block_size != STM32_SDIO_USE_DEFAULT_BLOCKSIZE) + { + dblocksize = priv->block_size << SDIO_DCTRL_DBLOCKSIZE_SHIFT; + } + else +#endif + { + dblocksize = stm32_log2(buflen) << SDIO_DCTRL_DBLOCKSIZE_SHIFT; + } + + stm32_dataconfig(SDIO_DTIMER_DATATIMEOUT_MS, buflen, + dblocksize | SDIO_DCTRL_DTDIR); + + /* Configure the RX DMA */ + + stm32_configxfrints(priv, SDIO_DMARECV_MASK); + + putreg32(1, SDIO_DCTRL_DMAEN_BB); + stm32_dmasetup(priv->dma, STM32_SDIO_FIFO, (uint32_t)buffer, + (buflen + 3) >> 2, SDIO_RXDMA32_CONFIG); + + /* Start the DMA */ + + stm32_sample(priv, SAMPLENDX_BEFORE_ENABLE); + stm32_dmastart(priv->dma, stm32_dmacallback, priv, false); + stm32_sample(priv, SAMPLENDX_AFTER_SETUP); + + return OK; +} +#endif + +/**************************************************************************** + * Name: stm32_dmasendsetup + * + * Description: + * Setup to perform a write DMA. If the processor supports a data cache, + * then this method will also make sure that the contents of the DMA memory + * and the data cache are coherent. For write transfers, this may mean + * flushing the data cache. + * + * Input Parameters: + * dev - An instance of the SDIO device interface + * buffer - The memory to DMA into + * buflen - The size of the DMA transfer in bytes + * + * Returned Value: + * OK on success; a negated errno on failure + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_SDIO_DMA +static int stm32_dmasendsetup(struct sdio_dev_s *dev, + const uint8_t *buffer, size_t buflen) +{ + struct stm32_dev_s *priv = (struct stm32_dev_s *)dev; + uint32_t dblocksize; + + DEBUGASSERT(priv != NULL && buffer != NULL && buflen > 0); +#ifdef CONFIG_ARCH_HAVE_SDIO_PREFLIGHT + DEBUGASSERT(stm32_dmapreflight(dev, buffer, buflen) == 0); +#endif + + /* Reset the DPSM configuration */ + + stm32_datadisable(); + + /* Initialize register sampling */ + + stm32_sampleinit(); + stm32_sample(priv, SAMPLENDX_BEFORE_SETUP); + + /* Save the source buffer information for use by the interrupt handler */ + + priv->buffer = (uint32_t *)buffer; + priv->remaining = buflen; + priv->dmamode = true; + + /* Then set up the SDIO data path */ + +#ifdef CONFIG_SDIO_BLOCKSETUP + if (priv->block_size != STM32_SDIO_USE_DEFAULT_BLOCKSIZE) + { + dblocksize = priv->block_size << SDIO_DCTRL_DBLOCKSIZE_SHIFT; + } + else +#endif + { + dblocksize = stm32_log2(buflen) << SDIO_DCTRL_DBLOCKSIZE_SHIFT; + } + + stm32_dataconfig(SDIO_DTIMER_DATATIMEOUT_MS, buflen, dblocksize); + + /* Configure the TX DMA */ + + stm32_dmasetup(priv->dma, STM32_SDIO_FIFO, (uint32_t)buffer, + (buflen + 3) >> 2, SDIO_TXDMA32_CONFIG); + + stm32_sample(priv, SAMPLENDX_BEFORE_ENABLE); + putreg32(1, SDIO_DCTRL_DMAEN_BB); + + /* Start the DMA */ + + stm32_dmastart(priv->dma, stm32_dmacallback, priv, false); + stm32_sample(priv, SAMPLENDX_AFTER_SETUP); + + /* Enable TX interrupts */ + + stm32_configxfrints(priv, SDIO_DMASEND_MASK); + + return OK; +} +#endif + +/**************************************************************************** + * Name: stm32_callback + * + * Description: + * Perform callback. + * + * Assumptions: + * This function does not execute in the context of an interrupt handler. + * It may be invoked on any user thread or scheduled on the work thread + * from an interrupt handler. + * + ****************************************************************************/ + +static void stm32_callback(void *arg) +{ + struct stm32_dev_s *priv = (struct stm32_dev_s *)arg; + + /* Is a callback registered? */ + + DEBUGASSERT(priv != NULL); + mcinfo("Callback %p(%p) cbevents: %02x cdstatus: %02x\n", + priv->callback, priv->cbarg, priv->cbevents, priv->cdstatus); + + if (priv->callback) + { + /* Yes.. Check for enabled callback events */ + + if ((priv->cdstatus & SDIO_STATUS_PRESENT) != 0) + { + /* Media is present. Is the media inserted event enabled? */ + + if ((priv->cbevents & SDIOMEDIA_INSERTED) == 0) + { + /* No... return without performing the callback */ + + return; + } + } + else + { + /* Media is not present. Is the media eject event enabled? */ + + if ((priv->cbevents & SDIOMEDIA_EJECTED) == 0) + { + /* No... return without performing the callback */ + + return; + } + } + + /* Perform the callback, disabling further callbacks. Of course, the + * the callback can (and probably should) re-enable callbacks. + */ + + priv->cbevents = 0; + + /* Callbacks cannot be performed in the context of an interrupt + * handler. If we are in an interrupt handler, then queue the + * callback to be performed later on the work thread. + */ + + if (up_interrupt_context()) + { + /* Yes.. queue it */ + + mcinfo("Queuing callback to %p(%p)\n", + priv->callback, priv->cbarg); + work_queue(HPWORK, &priv->cbwork, priv->callback, + priv->cbarg, 0); + } + else + { + /* No.. then just call the callback here */ + + mcinfo("Callback to %p(%p)\n", priv->callback, priv->cbarg); + priv->callback(priv->cbarg); + } + } +} + +/**************************************************************************** + * Name: stm32_default + * + * Description: + * Restore SDIO registers to their default, reset values + * + ****************************************************************************/ + +static void stm32_default(void) +{ + putreg32(SDIO_POWER_RESET, STM32_SDIO_POWER); + putreg32(SDIO_CLKCR_RESET, STM32_SDIO_CLKCR); + putreg32(SDIO_ARG_RESET, STM32_SDIO_ARG); + putreg32(SDIO_CMD_RESET, STM32_SDIO_CMD); + putreg32(SDIO_DTIMER_RESET, STM32_SDIO_DTIMER); + putreg32(SDIO_DLEN_RESET, STM32_SDIO_DLEN); + putreg32(SDIO_DCTRL_RESET, STM32_SDIO_DCTRL); + putreg32(SDIO_ICR_RESET, STM32_SDIO_ICR); + putreg32(SDIO_MASK_RESET, STM32_SDIO_MASK); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: sdio_initialize + * + * Description: + * Initialize SDIO for operation. + * + * Input Parameters: + * slotno - Not used. + * + * Returned Value: + * A reference to an SDIO interface structure. NULL is returned on + * failures. + * + ****************************************************************************/ + +struct sdio_dev_s *sdio_initialize(int slotno) +{ + /* There is only one slot */ + + struct stm32_dev_s *priv = &g_sdiodev; + + /* Allocate a DMA channel */ + +#ifdef CONFIG_STM32_SDIO_DMA + priv->dma = stm32_dmachannel(SDIO_DMACHAN); + DEBUGASSERT(priv->dma); +#endif + + /* Configure GPIOs for 4-bit, wide-bus operation (the chip is capable of + * 8-bit wide bus operation but D4-D7 are not configured). + * + * If bus is multiplexed then there is a custom bus configuration utility + * in the scope of the board support package. + */ + +#ifndef CONFIG_SDIO_MUXBUS + stm32_configgpio(GPIO_SDIO_D0 | SDIO_PULLUP_ENABLE); +#ifndef CONFIG_STM32_SDIO_WIDTH_D1_ONLY + stm32_configgpio(GPIO_SDIO_D1 | SDIO_PULLUP_ENABLE); + stm32_configgpio(GPIO_SDIO_D2 | SDIO_PULLUP_ENABLE); + stm32_configgpio(GPIO_SDIO_D3 | SDIO_PULLUP_ENABLE); +#endif + stm32_configgpio(GPIO_SDIO_CK | SDIO_PULLUP_ENABLE); + stm32_configgpio(GPIO_SDIO_CMD | SDIO_PULLUP_ENABLE); +#endif + + /* Reset the card and assure that it is in the initial, unconfigured + * state. + */ + + stm32_reset(&priv->dev); + return &g_sdiodev.dev; +} + +/**************************************************************************** + * Name: sdio_mediachange + * + * Description: + * Called by board-specific logic -- possibly from an interrupt handler -- + * in order to signal to the driver that a card has been inserted or + * removed from the slot + * + * Input Parameters: + * dev - An instance of the SDIO driver device state structure. + * cardinslot - true is a card has been detected in the slot; false if a + * card has been removed from the slot. Only transitions + * (inserted->removed or removed->inserted should be reported) + * + * Returned Value: + * None + * + ****************************************************************************/ + +void sdio_mediachange(struct sdio_dev_s *dev, bool cardinslot) +{ + struct stm32_dev_s *priv = (struct stm32_dev_s *)dev; + sdio_statset_t cdstatus; + irqstate_t flags; + + /* Update card status */ + + flags = enter_critical_section(); + cdstatus = priv->cdstatus; + if (cardinslot) + { + priv->cdstatus |= SDIO_STATUS_PRESENT; + } + else + { + priv->cdstatus &= ~SDIO_STATUS_PRESENT; + } + + leave_critical_section(flags); + + mcinfo("cdstatus OLD: %02x NEW: %02x\n", cdstatus, priv->cdstatus); + + /* Perform any requested callback if the status has changed */ + + if (cdstatus != priv->cdstatus) + { + stm32_callback(priv); + } +} + +/**************************************************************************** + * Name: sdio_wrprotect + * + * Description: + * Called by board-specific logic to report if the card in the slot is + * mechanically write protected. + * + * Input Parameters: + * dev - An instance of the SDIO driver device state structure. + * wrprotect - true is a card is writeprotected. + * + * Returned Value: + * None + * + ****************************************************************************/ + +void sdio_wrprotect(struct sdio_dev_s *dev, bool wrprotect) +{ + struct stm32_dev_s *priv = (struct stm32_dev_s *)dev; + irqstate_t flags; + + /* Update card status */ + + flags = enter_critical_section(); + if (wrprotect) + { + priv->cdstatus |= SDIO_STATUS_WRPROTECTED; + } + else + { + priv->cdstatus &= ~SDIO_STATUS_WRPROTECTED; + } + + mcinfo("cdstatus: %02x\n", priv->cdstatus); + leave_critical_section(flags); +} + +/**************************************************************************** + * Name: sdio_set_sdio_card_isr + * + * Description: + * SDIO card generates interrupt via SDIO_DATA_1 pin. + * Called by board-specific logic to register an ISR for SDIO card. + * + * Input Parameters: + * func - callback function. + * arg - arg to be passed to the function. + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_SDIO_CARD +void sdio_set_sdio_card_isr(struct sdio_dev_s *dev, + int (*func)(void *), void *arg) +{ + struct stm32_dev_s *priv = (struct stm32_dev_s *)dev; + + priv->do_sdio_card = func; + + if (func != NULL) + { + priv->sdiointmask = SDIO_STA_SDIOIT; + priv->do_sdio_arg = arg; + } + else + { + priv->sdiointmask = 0; + } + + putreg32(priv->xfrmask | priv->waitmask | priv->sdiointmask, + STM32_SDIO_MASK); +} +#endif + +#endif /* CONFIG_STM32_SDIO */ diff --git a/arch/arm/src/common/stm32/stm32_sdio_m3m4_v1.h b/arch/arm/src/common/stm32/stm32_sdio_m3m4_v1.h new file mode 100644 index 0000000000000..8ffd42b7eecbd --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_sdio_m3m4_v1.h @@ -0,0 +1,141 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_sdio_m3m4_v1.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_SDIO_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_SDIO_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#ifdef CONFIG_STM32_HAVE_IP_SDIO_M3M4_V1 + +#include +#include + +#include "chip.h" +#include "hardware/stm32_sdio.h" + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Name: sdio_initialize + * + * Description: + * Initialize SDIO for operation. + * + * Input Parameters: + * slotno - Not used. + * + * Returned Value: + * A reference to an SDIO interface structure. NULL is returned on + * failures. + * + ****************************************************************************/ + +struct sdio_dev_s; /* See include/nuttx/sdio.h */ +struct sdio_dev_s *sdio_initialize(int slotno); + +/**************************************************************************** + * Name: sdio_mediachange + * + * Description: + * Called by board-specific logic -- possibly from an interrupt handler -- + * in order to signal to the driver that a card has been inserted or + * removed from the slot + * + * Input Parameters: + * dev - An instance of the SDIO driver device state structure. + * cardinslot - true is a card has been detected in the slot; false if a + * card has been removed from the slot. Only transitions + * (inserted->removed or removed->inserted should be reported) + * + * Returned Value: + * None + * + ****************************************************************************/ + +void sdio_mediachange(struct sdio_dev_s *dev, bool cardinslot); + +/**************************************************************************** + * Name: sdio_wrprotect + * + * Description: + * Called by board-specific logic to report if the card in the slot is + * mechanically write protected. + * + * Input Parameters: + * dev - An instance of the SDIO driver device state structure. + * wrprotect - true is a card is writeprotected. + * + * Returned Value: + * None + * + ****************************************************************************/ + +void sdio_wrprotect(struct sdio_dev_s *dev, bool wrprotect); + +/**************************************************************************** + * Name: sdio_set_sdio_card_isr + * + * Description: + * SDIO card generates interrupt via SDIO_DATA_1 pin. + * Called by board-specific logic to register an ISR for SDIO card. + * + * Input Parameters: + * func - callback function. + * arg - arg to be passed to the function. + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_SDIO_CARD +void sdio_set_sdio_card_isr(struct sdio_dev_s *dev, + int (*func)(void *), void *arg); +#endif + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ + +#endif /* CONFIG_STM32_HAVE_IP_SDIO_M3M4_V1 */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_SDIO_H */ diff --git a/arch/arm/src/common/stm32/stm32_serial_m0_v3.c b/arch/arm/src/common/stm32/stm32_serial_m0_v3.c new file mode 100644 index 0000000000000..504e31b9c49e6 --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_serial_m0_v3.c @@ -0,0 +1,2614 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_serial_m0_v3.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#ifdef CONFIG_SERIAL_TERMIOS +# include +#endif + +#include "arm_internal.h" +#include "chip.h" +#include "stm32_gpio.h" +#include "stm32_uart.h" +#include "stm32_rcc.h" +#include "hardware/stm32_pinmap.h" + +/* board.h should be included last. It may depend on definitions from + * previous header files and it may, in certain cases, override definitions + * provided in previous header files. + */ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Some sanity checks *******************************************************/ + +/* DMA configuration */ + +/* If DMA is enabled on any USART, then very that other pre-requisites + * have also been selected. + * USART DMA1 DMA2 + * 1 X X + * 2 X + * 3 X + * 4 X + * 5 X + */ + +#ifdef SERIAL_HAVE_RXDMA + +/* Verify that DMA has been enabled and the DMA channel has been defined. + */ + +# if defined(CONFIG_USART2_RXDMA) || defined(CONFIG_USART3_RXDMA) +# ifndef CONFIG_STM32_DMA1 +# error STM32F0 USART2/3 receive DMA requires CONFIG_STM32_DMA1 +# endif +# endif + +# if defined(CONFIG_USART4_RXDMA) || defined(CONFIG_USART5_RXDMA) +# ifndef CONFIG_STM32_DMA2 +# error STM32F0 USART4/5 receive DMA requires CONFIG_STM32_DMA2 +# endif +# endif + +/* Currently RS-485 support cannot be enabled when RXDMA is in use due to + * lack of testing - RS-485 support was developed on STM32F1x + */ + +# if (defined(CONFIG_USART1_RXDMA) && defined(CONFIG_USART1_RS485)) || \ + (defined(CONFIG_USART2_RXDMA) && defined(CONFIG_USART2_RS485)) || \ + (defined(CONFIG_USART3_RXDMA) && defined(CONFIG_USART3_RS485)) || \ + (defined(CONFIG_USART4_RXDMA) && defined(CONFIG_USART4_RS485)) || \ + (defined(CONFIG_USART5_RXDMA) && defined(CONFIG_USART5_RS485)) +# error "RXDMA and RS-485 cannot be enabled at the same time for the same U[S]ART" +# endif + +/* For the L4, there are alternate DMA channels for USART1. + * Logic in the board.h file make the DMA channel selection by defining + * the following in the board.h file. + */ + +# if defined(CONFIG_USART1_RXDMA) && !defined(DMAMAP_USART1_RX) +# error "USART1 DMA channel not defined (DMAMAP_USART1_RX)" +# endif + +/* USART2-5 have no alternate channels */ + +# define DMAMAP_USART2_RX DMACHAN_USART2_RX +# define DMAMAP_USART3_RX DMACHAN_USART3_RX +# define DMAMAP_USART4_RX DMACHAN_USART4_RX +# define DMAMAP_USART5_RX DMACHAN_USART5_RX + +/* The DMA buffer size when using RX DMA to emulate a FIFO. + * + * When streaming data, the generic serial layer will be called + * every time the FIFO receives half this number of bytes. + */ + +# define RXDMA_BUFFER_SIZE 32 + +/* DMA priority */ + +# ifndef CONFIG_USART_RXDMAPRIO +# define CONFIG_USART_RXDMAPRIO DMA_CCR_PRIMED +# endif +# if (CONFIG_USART_RXDMAPRIO & ~DMA_CCR_PL_MASK) != 0 +# error "Illegal value for CONFIG_USART_RXDMAPRIO" +# endif + +/* DMA control words */ + +# define SERIAL_DMA_CONTROL_WORD \ + (DMA_CCR_CIRC | \ + DMA_CCR_MINC | \ + DMA_CCR_PSIZE_8BITS | \ + DMA_CCR_MSIZE_8BITS | \ + CONFIG_USART_RXDMAPRIO) +# ifdef CONFIG_SERIAL_IFLOWCONTROL +# define SERIAL_DMA_IFLOW_CONTROL_WORD \ + (DMA_CCR_MINC | \ + DMA_CCR_PSIZE_8BITS | \ + DMA_CCR_MSIZE_8BITS | \ + CONFIG_USART_RXDMAPRIO) +# endif + +#endif + +/* Power management definitions */ + +#if defined(CONFIG_PM) && !defined(CONFIG_STM32_PM_SERIAL_ACTIVITY) +# define CONFIG_STM32_PM_SERIAL_ACTIVITY 10 +#endif + +/* Keep track if a Break was set + * + * Note: + * + * 1) This value is set in the priv->ie but never written to the control + * register. It must not collide with USART_CR1_USED_INTS or USART_CR3_EIE + * 2) USART_CR3_EIE is also carried in the up_dev_s ie member. + * + * See stm32serial_restoreusartint where the masking is done. + */ + +#ifdef CONFIG_STM32_SERIALBRK_BSDCOMPAT +# define USART_CR1_IE_BREAK_INPROGRESS_SHFTS 15 +# define USART_CR1_IE_BREAK_INPROGRESS (1 << USART_CR1_IE_BREAK_INPROGRESS_SHFTS) +#endif + +#ifdef USE_SERIALDRIVER +#ifdef HAVE_USART + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +struct stm32_serial_s +{ + struct uart_dev_s dev; /* Generic USART device */ + uint16_t ie; /* Saved interrupt mask bits value */ + uint16_t sr; /* Saved status bits */ + + /* If termios are supported, then the following fields may vary at + * runtime. + */ + +#ifdef CONFIG_SERIAL_TERMIOS + uint8_t parity; /* 0=none, 1=odd, 2=even */ + uint8_t bits; /* Number of bits (7 or 8) */ + bool stopbits2; /* True: Configure with 2 stop bits instead of 1 */ +#ifdef CONFIG_SERIAL_IFLOWCONTROL + bool iflow; /* input flow control (RTS) enabled */ +#endif +#ifdef CONFIG_SERIAL_OFLOWCONTROL + bool oflow; /* output flow control (CTS) enabled */ +#endif + uint32_t baud; /* Configured baud */ +#else + const uint8_t parity; /* 0=none, 1=odd, 2=even */ + const uint8_t bits; /* Number of bits (7 or 8) */ + const bool stopbits2; /* True: Configure with 2 stop bits instead of 1 */ +#ifdef CONFIG_SERIAL_IFLOWCONTROL + const bool iflow; /* input flow control (RTS) enabled */ +#endif +#ifdef CONFIG_SERIAL_OFLOWCONTROL + const bool oflow; /* output flow control (CTS) enabled */ +#endif + const uint32_t baud; /* Configured baud */ +#endif + + const uint8_t irq; /* IRQ associated with this USART */ + const uint32_t apbclock; /* PCLK 1 or 2 frequency */ + const uint32_t usartbase; /* Base address of USART registers */ + const uint32_t tx_gpio; /* U[S]ART TX GPIO pin configuration */ + const uint32_t rx_gpio; /* U[S]ART RX GPIO pin configuration */ +#ifdef CONFIG_SERIAL_IFLOWCONTROL + const uint32_t rts_gpio; /* U[S]ART RTS GPIO pin configuration */ +#endif +#ifdef CONFIG_SERIAL_OFLOWCONTROL + const uint32_t cts_gpio; /* U[S]ART CTS GPIO pin configuration */ +#endif + +#ifdef SERIAL_HAVE_RXDMA + const unsigned int rxdma_channel; /* DMA channel assigned */ +#endif + + /* RX DMA state */ + +#ifdef SERIAL_HAVE_RXDMA + DMA_HANDLE rxdma; /* currently-open receive DMA stream */ + bool rxenable; /* DMA-based reception en/disable */ + uint32_t rxdmanext; /* Next byte in the DMA buffer to be read */ + char *const rxfifo; /* Receive DMA buffer */ +#endif + +#ifdef HAVE_RS485 + const uint32_t rs485_dir_gpio; /* U[S]ART RS-485 DIR GPIO pin configuration */ + const bool rs485_dir_polarity; /* U[S]ART RS-485 DIR pin state for TX enabled */ +#endif + spinlock_t lock; /* Spinlock */ +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +#ifndef CONFIG_SUPPRESS_UART_CONFIG +static void stm32serial_setformat(struct uart_dev_s *dev); +#endif +static int stm32serial_setup(struct uart_dev_s *dev); +static void stm32serial_shutdown(struct uart_dev_s *dev); +static int stm32serial_attach(struct uart_dev_s *dev); +static void stm32serial_detach(struct uart_dev_s *dev); +static int up_interrupt(int irq, void *context, void *arg); +static int stm32serial_ioctl(struct file *filep, int cmd, + unsigned long arg); +#ifndef SERIAL_HAVE_ONLY_DMA +static int stm32serial_receive(struct uart_dev_s *dev, + unsigned int *status); +static void stm32serial_rxint(struct uart_dev_s *dev, bool enable); +static bool stm32serial_rxavailable(struct uart_dev_s *dev); +#endif +#ifdef CONFIG_SERIAL_IFLOWCONTROL +static bool stm32serial_rxflowcontrol(struct uart_dev_s *dev, + unsigned int nbuffered, bool upper); +#endif +static void stm32serial_send(struct uart_dev_s *dev, int ch); +static void stm32serial_txint(struct uart_dev_s *dev, bool enable); +static bool stm32serial_txready(struct uart_dev_s *dev); + +#ifdef SERIAL_HAVE_RXDMA +static int stm32serial_dmasetup(struct uart_dev_s *dev); +static void stm32serial_dmashutdown(struct uart_dev_s *dev); +static int stm32serial_dmareceive(struct uart_dev_s *dev, + unsigned int *status); +static void stm32serial_dmarxint(struct uart_dev_s *dev, bool enable); +static bool stm32serial_dmarxavailable(struct uart_dev_s *dev); + +static void stm32serial_dmarxcallback(DMA_HANDLE handle, uint8_t status, + void *arg); +#endif + +#ifdef CONFIG_PM +static void stm32serial_pmnotify(struct pm_callback_s *cb, int domain, + enum pm_state_e pmstate); +static int stm32serial_pmprepare(struct pm_callback_s *cb, int domain, + enum pm_state_e pmstate); +#endif + +/**************************************************************************** + * Private Variables + ****************************************************************************/ + +#ifndef SERIAL_HAVE_ONLY_DMA +static const struct uart_ops_s g_uart_ops = +{ + .setup = stm32serial_setup, + .shutdown = stm32serial_shutdown, + .attach = stm32serial_attach, + .detach = stm32serial_detach, + .ioctl = stm32serial_ioctl, + .receive = stm32serial_receive, + .rxint = stm32serial_rxint, + .rxavailable = stm32serial_rxavailable, +# ifdef CONFIG_SERIAL_IFLOWCONTROL + .rxflowcontrol = stm32serial_rxflowcontrol, +# endif + .send = stm32serial_send, + .txint = stm32serial_txint, + .txready = stm32serial_txready, + .txempty = stm32serial_txready, +}; +#endif + +#ifdef SERIAL_HAVE_RXDMA +static const struct uart_ops_s g_uart_dma_ops = +{ + .setup = stm32serial_dmasetup, + .shutdown = stm32serial_dmashutdown, + .attach = stm32serial_attach, + .detach = stm32serial_detach, + .ioctl = stm32serial_ioctl, + .receive = stm32serial_dmareceive, + .rxint = stm32serial_dmarxint, + .rxavailable = stm32serial_dmarxavailable, +# ifdef CONFIG_SERIAL_IFLOWCONTROL + .rxflowcontrol = stm32serial_rxflowcontrol, +# endif + .send = stm32serial_send, + .txint = stm32serial_txint, + .txready = stm32serial_txready, + .txempty = stm32serial_txready, +}; +#endif + +/* I/O buffers */ + +#ifdef CONFIG_STM32_USART1 +static char g_usart1rxbuffer[CONFIG_USART1_RXBUFSIZE]; +static char g_usart1txbuffer[CONFIG_USART1_TXBUFSIZE]; +# ifdef CONFIG_USART1_RXDMA +static char g_usart1rxfifo[RXDMA_BUFFER_SIZE]; +# endif +#endif + +#ifdef CONFIG_STM32_USART2 +static char g_usart2rxbuffer[CONFIG_USART2_RXBUFSIZE]; +static char g_usart2txbuffer[CONFIG_USART2_TXBUFSIZE]; +# ifdef CONFIG_USART2_RXDMA +static char g_usart2rxfifo[RXDMA_BUFFER_SIZE]; +# endif +#endif + +#ifdef CONFIG_STM32_USART3 +static char g_usart3rxbuffer[CONFIG_USART3_RXBUFSIZE]; +static char g_usart3txbuffer[CONFIG_USART3_TXBUFSIZE]; +# ifdef CONFIG_USART3_RXDMA +static char g_usart3rxfifo[RXDMA_BUFFER_SIZE]; +# endif +#endif + +#ifdef CONFIG_STM32_USART4 +static char g_usart4rxbuffer[CONFIG_USART4_RXBUFSIZE]; +static char g_usart4txbuffer[CONFIG_USART4_TXBUFSIZE]; +# ifdef CONFIG_USART4_RXDMA +static char g_usart4rxfifo[RXDMA_BUFFER_SIZE]; +# endif +#endif + +#ifdef CONFIG_STM32_USART5 +static char g_usart5rxbuffer[CONFIG_USART5_RXBUFSIZE]; +static char g_usart5txbuffer[CONFIG_USART5_TXBUFSIZE]; +# ifdef CONFIG_USART5_RXDMA +static char g_usart5rxfifo[RXDMA_BUFFER_SIZE]; +# endif +#endif + +/* This describes the state of the STM32 USART1 ports. */ + +#ifdef CONFIG_STM32_USART1 +static struct stm32_serial_s g_usart1priv = +{ + .dev = + { +# if CONSOLE_USART == 1 + .isconsole = true, +# endif + .recv = + { + .size = CONFIG_USART1_RXBUFSIZE, + .buffer = g_usart1rxbuffer, + }, + .xmit = + { + .size = CONFIG_USART1_TXBUFSIZE, + .buffer = g_usart1txbuffer, + }, +# ifdef CONFIG_USART1_RXDMA + .ops = &g_uart_dma_ops, +# else + .ops = &g_uart_ops, +# endif + .priv = &g_usart1priv, + }, + + .irq = STM32_IRQ_USART1, + .parity = CONFIG_USART1_PARITY, + .bits = CONFIG_USART1_BITS, + .stopbits2 = CONFIG_USART1_2STOP, + .baud = CONFIG_USART1_BAUD, + .apbclock = STM32_PCLK2_FREQUENCY, + .usartbase = STM32_USART1_BASE, + .tx_gpio = GPIO_USART1_TX, + .rx_gpio = GPIO_USART1_RX, +# if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_USART1_OFLOWCONTROL) + .oflow = true, + .cts_gpio = GPIO_USART1_CTS, +# endif +# if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_USART1_IFLOWCONTROL) + .iflow = true, + .rts_gpio = GPIO_USART1_RTS, +# endif +# ifdef CONFIG_USART1_RXDMA + .rxdma_channel = DMAMAP_USART1_RX, + .rxfifo = g_usart1rxfifo, +# endif + +# ifdef CONFIG_USART1_RS485 + .rs485_dir_gpio = GPIO_USART1_RS485_DIR, +# if (CONFIG_USART1_RS485_DIR_POLARITY == 0) + .rs485_dir_polarity = false, +# else + .rs485_dir_polarity = true, +# endif +# endif + .lock = SP_UNLOCKED, +}; +#endif + +/* This describes the state of the STM32 USART2 port. */ + +#ifdef CONFIG_STM32_USART2 +static struct stm32_serial_s g_usart2priv = +{ + .dev = + { +# if CONSOLE_USART == 2 + .isconsole = true, +# endif + .recv = + { + .size = CONFIG_USART2_RXBUFSIZE, + .buffer = g_usart2rxbuffer, + }, + .xmit = + { + .size = CONFIG_USART2_TXBUFSIZE, + .buffer = g_usart2txbuffer, + }, +# ifdef CONFIG_USART2_RXDMA + .ops = &g_uart_dma_ops, +# else + .ops = &g_uart_ops, +# endif + .priv = &g_usart2priv, + }, + + .irq = STM32_IRQ_USART2, + .parity = CONFIG_USART2_PARITY, + .bits = CONFIG_USART2_BITS, + .stopbits2 = CONFIG_USART2_2STOP, + .baud = CONFIG_USART2_BAUD, + .apbclock = STM32_PCLK1_FREQUENCY, + .usartbase = STM32_USART2_BASE, + .tx_gpio = GPIO_USART2_TX, + .rx_gpio = GPIO_USART2_RX, +# if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_USART2_OFLOWCONTROL) + .oflow = true, + .cts_gpio = GPIO_USART2_CTS, +# endif +# if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_USART2_IFLOWCONTROL) + .iflow = true, + .rts_gpio = GPIO_USART2_RTS, +# endif +# ifdef CONFIG_USART2_RXDMA + .rxdma_channel = DMAMAP_USART2_RX, + .rxfifo = g_usart2rxfifo, +# endif + +# ifdef CONFIG_USART2_RS485 + .rs485_dir_gpio = GPIO_USART2_RS485_DIR, +# if (CONFIG_USART2_RS485_DIR_POLARITY == 0) + .rs485_dir_polarity = false, +# else + .rs485_dir_polarity = true, +# endif +# endif + .lock = SP_UNLOCKED, +}; +#endif + +/* This describes the state of the STM32 USART3 port. */ + +#ifdef CONFIG_STM32_USART3 +static struct stm32_serial_s g_usart3priv = +{ + .dev = + { +# if CONSOLE_USART == 3 + .isconsole = true, +# endif + .recv = + { + .size = CONFIG_USART3_RXBUFSIZE, + .buffer = g_usart3rxbuffer, + }, + .xmit = + { + .size = CONFIG_USART3_TXBUFSIZE, + .buffer = g_usart3txbuffer, + }, +# ifdef CONFIG_USART3_RXDMA + .ops = &g_uart_dma_ops, +# else + .ops = &g_uart_ops, +# endif + .priv = &g_usart3priv, + }, + + .irq = STM32_IRQ_USART3, + .parity = CONFIG_USART3_PARITY, + .bits = CONFIG_USART3_BITS, + .stopbits2 = CONFIG_USART3_2STOP, + .baud = CONFIG_USART3_BAUD, + .apbclock = STM32_PCLK1_FREQUENCY, + .usartbase = STM32_USART3_BASE, + .tx_gpio = GPIO_USART3_TX, + .rx_gpio = GPIO_USART3_RX, +# if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_USART3_OFLOWCONTROL) + .oflow = true, + .cts_gpio = GPIO_USART3_CTS, +# endif +# if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_USART3_IFLOWCONTROL) + .iflow = true, + .rts_gpio = GPIO_USART3_RTS, +# endif +# ifdef CONFIG_USART3_RXDMA + .rxdma_channel = DMAMAP_USART3_RX, + .rxfifo = g_usart3rxfifo, +# endif + +# ifdef CONFIG_USART3_RS485 + .rs485_dir_gpio = GPIO_USART3_RS485_DIR, +# if (CONFIG_USART3_RS485_DIR_POLARITY == 0) + .rs485_dir_polarity = false, +# else + .rs485_dir_polarity = true, +# endif +# endif + .lock = SP_UNLOCKED, +}; +#endif + +/* This describes the state of the STM32 USART4 port. */ + +#ifdef CONFIG_STM32_USART4 +static struct stm32_serial_s g_usart4priv = +{ + .dev = + { +# if CONSOLE_USART == 4 + .isconsole = true, +# endif + .recv = + { + .size = CONFIG_USART4_RXBUFSIZE, + .buffer = g_usart4rxbuffer, + }, + .xmit = + { + .size = CONFIG_USART4_TXBUFSIZE, + .buffer = g_usart4txbuffer, + }, +# ifdef CONFIG_USART4_RXDMA + .ops = &g_uart_dma_ops, +# else + .ops = &g_uart_ops, +# endif + .priv = &g_usart4priv, + }, + + .irq = STM32_IRQ_USART4, + .parity = CONFIG_USART4_PARITY, + .bits = CONFIG_USART4_BITS, + .stopbits2 = CONFIG_USART4_2STOP, +# ifdef CONFIG_SERIAL_IFLOWCONTROL + .iflow = false, +# endif +# ifdef CONFIG_SERIAL_OFLOWCONTROL + .oflow = false, +# endif + .baud = CONFIG_USART4_BAUD, + .apbclock = STM32_PCLK1_FREQUENCY, + .usartbase = STM32_USART4_BASE, + .tx_gpio = GPIO_USART4_TX, + .rx_gpio = GPIO_USART4_RX, +# ifdef CONFIG_SERIAL_OFLOWCONTROL + .cts_gpio = 0, +# endif +# ifdef CONFIG_SERIAL_IFLOWCONTROL + .rts_gpio = 0, +# endif +# ifdef CONFIG_USART4_RXDMA + .rxdma_channel = DMAMAP_USART4_RX, + .rxfifo = g_usart4rxfifo, +# endif + +# ifdef CONFIG_USART4_RS485 + .rs485_dir_gpio = GPIO_USART4_RS485_DIR, +# if (CONFIG_USART4_RS485_DIR_POLARITY == 0) + .rs485_dir_polarity = false, +# else + .rs485_dir_polarity = true, +# endif +# endif + .lock = SP_UNLOCKED, +}; +#endif + +/* This describes the state of the STM32 USART5 port. */ + +#ifdef CONFIG_STM32_USART5 +static struct stm32_serial_s g_usart5priv = +{ + .dev = + { +# if CONSOLE_USART == 5 + .isconsole = true, +# endif + .recv = + { + .size = CONFIG_USART5_RXBUFSIZE, + .buffer = g_usart5rxbuffer, + }, + .xmit = + { + .size = CONFIG_USART5_TXBUFSIZE, + .buffer = g_usart5txbuffer, + }, +# ifdef CONFIG_USART5_RXDMA + .ops = &g_uart_dma_ops, +# else + .ops = &g_uart_ops, +# endif + .priv = &g_usart5priv, + }, + + .irq = STM32_IRQ_USART5, + .parity = CONFIG_USART5_PARITY, + .bits = CONFIG_USART5_BITS, + .stopbits2 = CONFIG_USART5_2STOP, +# ifdef CONFIG_SERIAL_IFLOWCONTROL + .iflow = false, +# endif +# ifdef CONFIG_SERIAL_OFLOWCONTROL + .oflow = false, +# endif + .baud = CONFIG_USART5_BAUD, + .apbclock = STM32_PCLK1_FREQUENCY, + .usartbase = STM32_USART5_BASE, + .tx_gpio = GPIO_USART5_TX, + .rx_gpio = GPIO_USART5_RX, +# ifdef CONFIG_SERIAL_OFLOWCONTROL + .cts_gpio = 0, +# endif +# ifdef CONFIG_SERIAL_IFLOWCONTROL + .rts_gpio = 0, +# endif +# ifdef CONFIG_USART5_RXDMA + .rxdma_channel = DMAMAP_USART5_RX, + .rxfifo = g_usart5rxfifo, +# endif + +# ifdef CONFIG_USART5_RS485 + .rs485_dir_gpio = GPIO_USART5_RS485_DIR, +# if (CONFIG_USART5_RS485_DIR_POLARITY == 0) + .rs485_dir_polarity = false, +# else + .rs485_dir_polarity = true, +# endif +# endif + .lock = SP_UNLOCKED, +}; +#endif + +/* This table lets us iterate over the configured USARTs */ + +static struct stm32_serial_s * const g_uart_devs[STM32_NUSART] = +{ +#ifdef CONFIG_STM32_USART1 + [0] = &g_usart1priv, +#endif +#ifdef CONFIG_STM32_USART2 + [1] = &g_usart2priv, +#endif +#ifdef CONFIG_STM32_USART3 + [2] = &g_usart3priv, +#endif +#ifdef CONFIG_STM32_USART4 + [3] = &g_usart4priv, +#endif +#ifdef CONFIG_STM32_USART5 + [4] = &g_usart5priv, +#endif +}; + +#ifdef CONFIG_PM +static struct pm_callback_s g_serialcb = +{ + .notify = stm32serial_pmnotify, + .prepare = stm32serial_pmprepare, +}; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32serial_getreg + ****************************************************************************/ + +static inline uint32_t stm32serial_getreg(struct stm32_serial_s *priv, + int offset) +{ + return getreg32(priv->usartbase + offset); +} + +/**************************************************************************** + * Name: stm32serial_putreg + ****************************************************************************/ + +static inline void stm32serial_putreg(struct stm32_serial_s *priv, + int offset, uint32_t value) +{ + putreg32(value, priv->usartbase + offset); +} + +/**************************************************************************** + * Name: stm32serial_setusartint + ****************************************************************************/ + +static void stm32serial_setusartint(struct stm32_serial_s *priv, + uint16_t ie) +{ + uint32_t cr; + + /* Save the interrupt mask */ + + priv->ie = ie; + + /* And restore the interrupt state + * (see the interrupt enable/usage table above) + */ + + cr = stm32serial_getreg(priv, STM32_USART_CR1_OFFSET); + cr &= ~(USART_CR1_USED_INTS); + cr |= (ie & (USART_CR1_USED_INTS)); + stm32serial_putreg(priv, STM32_USART_CR1_OFFSET, cr); + + cr = stm32serial_getreg(priv, STM32_USART_CR3_OFFSET); + cr &= ~USART_CR3_EIE; + cr |= (ie & USART_CR3_EIE); + stm32serial_putreg(priv, STM32_USART_CR3_OFFSET, cr); +} + +/**************************************************************************** + * Name: stm32serial_restoreusartint + ****************************************************************************/ + +static void stm32serial_restoreusartint(struct stm32_serial_s *priv, + uint16_t ie) +{ + irqstate_t flags; + + flags = enter_critical_section(); + + stm32serial_setusartint(priv, ie); + + leave_critical_section(flags); +} + +/**************************************************************************** + * Name: stm32serial_disableusartint + ****************************************************************************/ + +static void stm32serial_disableusartint(struct stm32_serial_s *priv, + uint16_t *ie) +{ + irqstate_t flags; + + flags = spin_lock_irqsave(&priv->lock); + + if (ie) + { + uint32_t cr1; + uint32_t cr3; + + /* USART interrupts: + * + * Enable Status Meaning Usage + * ---------------- -------------- ----------------------- ---------- + * USART_CR1_IDLEIE USART_ISR_IDLE Idle Line Detected (not used) + * USART_CR1_RXNEIE USART_ISR_RXNE Received Data Ready + * to be Read + * " " USART_ISR_ORE Overrun Error Detected + * USART_CR1_TCIE USART_ISR_TC Transmission Complete (used only + * for RS-485) + * USART_CR1_TXEIE USART_ISR_TXE Transmit Data Register + * Empty + * USART_CR1_PEIE USART_ISR_PE Parity Error + * + * USART_CR2_LBDIE USART_ISR_LBD Break Flag (not used) + * USART_CR3_EIE USART_ISR_FE Framing Error + * " " USART_ISR_NF Noise Flag + * " " USART_ISR_ORE Overrun Error Detected + * USART_CR3_CTSIE USART_ISR_CTS CTS flag (not used) + */ + + cr1 = stm32serial_getreg(priv, STM32_USART_CR1_OFFSET); + cr3 = stm32serial_getreg(priv, STM32_USART_CR3_OFFSET); + + /* Return the current interrupt mask value for the used interrupts. + * Notice that this depends on the fact that none of the used interrupt + * enable bits overlap. + * This logic would fail if we needed the break interrupt! + */ + + *ie = (cr1 & (USART_CR1_USED_INTS)) | (cr3 & USART_CR3_EIE); + } + + /* Disable all interrupts */ + + stm32serial_setusartint(priv, 0); + + spin_unlock_irqrestore(&priv->lock, flags); +} + +/**************************************************************************** + * Name: stm32serial_dmanextrx + * + * Description: + * Returns the index into the RX FIFO where the DMA will place the next + * byte that it receives. + * + ****************************************************************************/ + +#ifdef SERIAL_HAVE_RXDMA +static int stm32serial_dmanextrx(struct stm32_serial_s *priv) +{ + size_t dmaresidual; + + dmaresidual = stm32_dmaresidual(priv->rxdma); + + return (RXDMA_BUFFER_SIZE - (int)dmaresidual); +} +#endif + +/**************************************************************************** + * Name: stm32serial_setformat + * + * Description: + * Set the serial line format and speed. + * + ****************************************************************************/ + +#ifndef CONFIG_SUPPRESS_UART_CONFIG +static void stm32serial_setformat(struct uart_dev_s *dev) +{ + struct stm32_serial_s *priv = (struct stm32_serial_s *)dev->priv; + uint32_t regval; + + /* This first implementation is for U[S]ARTs that support oversampling + * by 8 in additional to the standard oversampling by 16. + */ + + uint32_t usartdiv8; + uint32_t cr1; + uint32_t brr; + + /* In case of oversampling by 8, the equation is: + * + * baud = 2 * fCK / usartdiv8 + * usartdiv8 = 2 * fCK / baud + */ + + usartdiv8 = ((priv->apbclock << 1) + (priv->baud >> 1)) / priv->baud; + + /* Baud rate for standard USART (SPI mode included): + * + * In case of oversampling by 16, the equation is: + * baud = fCK / usartdiv16 + * usartdiv16 = fCK / baud + * = 2 * usartdiv8 + */ + + /* Use oversamply by 8 only if the divisor is small. But what is small? */ + + cr1 = stm32serial_getreg(priv, STM32_USART_CR1_OFFSET); + if (usartdiv8 > 100) + { + /* Use usartdiv16 */ + + brr = (usartdiv8 + 1) >> 1; + + /* Clear oversampling by 8 to enable oversampling by 16 */ + + cr1 &= ~USART_CR1_OVER8; + } + else + { + DEBUGASSERT(usartdiv8 >= 8); + + /* Perform mysterious operations on bits 0-3 */ + + brr = ((usartdiv8 & 0xfff0) | ((usartdiv8 & 0x000f) >> 1)); + + /* Set oversampling by 8 */ + + cr1 |= USART_CR1_OVER8; + } + + stm32serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1); + stm32serial_putreg(priv, STM32_USART_BRR_OFFSET, brr); + + /* Configure parity mode */ + + regval = stm32serial_getreg(priv, STM32_USART_CR1_OFFSET); + regval &= ~(USART_CR1_PCE | USART_CR1_PS | USART_CR1_M0 | USART_CR1_M1); + + if (priv->parity == 1) /* Odd parity */ + { + regval |= (USART_CR1_PCE | USART_CR1_PS); + } + else if (priv->parity == 2) /* Even parity */ + { + regval |= USART_CR1_PCE; + } + + /* Configure word length (parity uses one of configured bits) + * + * Default: 1 start, 8 data (no parity), n stop, OR + * 1 start, 7 data + parity, n stop + */ + + if (priv->bits == 9 || (priv->bits == 8 && priv->parity != 0)) + { + /* Select: 1 start, 8 data + parity, n stop, OR + * 1 start, 9 data (no parity), n stop. + */ + + regval |= USART_CR1_M0; + } + else if (priv->bits == 7 && priv->parity == 0) + { + /* Select: 1 start, 7 data (no parity), n stop, OR + */ + + regval |= USART_CR1_M1; + } + + /* Else Select: 1 start, 7 data + parity, n stop, OR + * 1 start, 8 data (no parity), n stop. + */ + + stm32serial_putreg(priv, STM32_USART_CR1_OFFSET, regval); + + /* Configure STOP bits */ + + regval = stm32serial_getreg(priv, STM32_USART_CR2_OFFSET); + regval &= ~(USART_CR2_STOP_MASK); + + if (priv->stopbits2) + { + regval |= USART_CR2_STOP2; + } + + stm32serial_putreg(priv, STM32_USART_CR2_OFFSET, regval); + + /* Configure hardware flow control */ + + regval = stm32serial_getreg(priv, STM32_USART_CR3_OFFSET); + regval &= ~(USART_CR3_CTSE | USART_CR3_RTSE); + +#if defined(CONFIG_SERIAL_IFLOWCONTROL) && !defined(CONFIG_STM32_FLOWCONTROL_BROKEN) + if (priv->iflow && (priv->rts_gpio != 0)) + { + regval |= USART_CR3_RTSE; + } +#endif + +#ifdef CONFIG_SERIAL_OFLOWCONTROL + if (priv->oflow && (priv->cts_gpio != 0)) + { + regval |= USART_CR3_CTSE; + } +#endif + + stm32serial_putreg(priv, STM32_USART_CR3_OFFSET, regval); +} +#endif /* CONFIG_SUPPRESS_UART_CONFIG */ + +/**************************************************************************** + * Name: stm32serial_setapbclock + * + * Description: + * Enable or disable APB clock for the USART peripheral + * + * Input Parameters: + * dev - A reference to the USART driver state structure + * on - Enable clock if 'on' is 'true' and disable if 'false' + * + ****************************************************************************/ + +static void stm32serial_setapbclock(struct uart_dev_s *dev, bool on) +{ + struct stm32_serial_s *priv = (struct stm32_serial_s *)dev->priv; + uint32_t rcc_en; + uint32_t regaddr; + + /* Determine which USART to configure */ + + switch (priv->usartbase) + { + default: + return; +#ifdef CONFIG_STM32_USART1 + case STM32_USART1_BASE: + rcc_en = RCC_APB2ENR_USART1EN; + regaddr = STM32_RCC_APB2ENR; + break; +#endif +#ifdef CONFIG_STM32_USART2 + case STM32_USART2_BASE: + rcc_en = RCC_APB1ENR_USART2EN; + regaddr = STM32_RCC_APB1ENR; + break; +#endif +#ifdef CONFIG_STM32_USART3 + case STM32_USART3_BASE: + rcc_en = RCC_APB1ENR_USART3EN; + regaddr = STM32_RCC_APB1ENR; + break; +#endif +#ifdef CONFIG_STM32_USART4 + case STM32_USART4_BASE: + rcc_en = RCC_APB1ENR_USART4EN; + regaddr = STM32_RCC_APB1ENR; + break; +#endif +#ifdef CONFIG_STM32_USART5 + case STM32_USART5_BASE: + rcc_en = RCC_APB1ENR_USART5EN; + regaddr = STM32_RCC_APB1ENR; + break; +#endif + } + + /* Enable/disable APB 1/2 clock for USART */ + + if (on) + { + modifyreg32(regaddr, 0, rcc_en); + } + else + { + modifyreg32(regaddr, rcc_en, 0); + } +} + +/**************************************************************************** + * Name: stm32serial_setup + * + * Description: + * Configure the USART baud, bits, parity, etc. This method is called the + * first time that the serial port is opened. + * + ****************************************************************************/ + +static int stm32serial_setup(struct uart_dev_s *dev) +{ + struct stm32_serial_s *priv = (struct stm32_serial_s *)dev->priv; + +#ifndef CONFIG_SUPPRESS_UART_CONFIG + uint32_t regval; + + /* Note: The logic here depends on the fact that that the USART module + * was enabled in stm32_lowsetup(). + */ + + /* Enable USART APB1/2 clock */ + + stm32serial_setapbclock(dev, true); + + /* Configure pins for USART use */ + + stm32_configgpio(priv->tx_gpio); + stm32_configgpio(priv->rx_gpio); + +#ifdef CONFIG_SERIAL_OFLOWCONTROL + if (priv->cts_gpio != 0) + { + stm32_configgpio(priv->cts_gpio); + } +#endif + +#ifdef CONFIG_SERIAL_IFLOWCONTROL + if (priv->rts_gpio != 0) + { + uint32_t config = priv->rts_gpio; + +#ifdef CONFIG_STM32_FLOWCONTROL_BROKEN + /* Instead of letting hw manage this pin, we will bitbang */ + + config = (config & ~GPIO_MODE_MASK) | GPIO_OUTPUT; +#endif + stm32_configgpio(config); + } +#endif + +#ifdef HAVE_RS485 + if (priv->rs485_dir_gpio != 0) + { + stm32_configgpio(priv->rs485_dir_gpio); + stm32_gpiowrite(priv->rs485_dir_gpio, !priv->rs485_dir_polarity); + } +#endif + + /* Configure CR2 + * + * Clear STOP, CLKEN, CPOL, CPHA, LBCL, and interrupt enable bits + */ + + regval = stm32serial_getreg(priv, STM32_USART_CR2_OFFSET); + regval &= ~(USART_CR2_STOP_MASK | USART_CR2_CLKEN | USART_CR2_CPOL | + USART_CR2_CPHA | USART_CR2_LBCL | USART_CR2_LBDIE); + + /* Configure STOP bits */ + + if (priv->stopbits2) + { + regval |= USART_CR2_STOP2; + } + + stm32serial_putreg(priv, STM32_USART_CR2_OFFSET, regval); + + /* Configure CR1 + * + * Clear TE, REm and all interrupt enable bits + */ + + regval = stm32serial_getreg(priv, STM32_USART_CR1_OFFSET); + regval &= ~(USART_CR1_TE | USART_CR1_RE | USART_CR1_ALLINTS); + + stm32serial_putreg(priv, STM32_USART_CR1_OFFSET, regval); + + /* Configure CR3 + * + * Clear CTSE, RTSE, and all interrupt enable bits + */ + + regval = stm32serial_getreg(priv, STM32_USART_CR3_OFFSET); + regval &= ~(USART_CR3_CTSIE | USART_CR3_CTSE | USART_CR3_RTSE | + USART_CR3_EIE); + + stm32serial_putreg(priv, STM32_USART_CR3_OFFSET, regval); + + /* Configure the USART line format and speed. */ + + stm32serial_setformat(dev); + + /* Enable Rx, Tx, and the USART */ + + regval = stm32serial_getreg(priv, STM32_USART_CR1_OFFSET); + regval |= (USART_CR1_UE | USART_CR1_TE | USART_CR1_RE); + stm32serial_putreg(priv, STM32_USART_CR1_OFFSET, regval); + +#endif /* CONFIG_SUPPRESS_UART_CONFIG */ + + /* Set up the cached interrupt enables value */ + + priv->ie = 0; + return OK; +} + +/**************************************************************************** + * Name: stm32serial_dmasetup + * + * Description: + * Configure the USART baud, bits, parity, etc. This method is called the + * first time that the serial port is opened. + * + ****************************************************************************/ + +#ifdef SERIAL_HAVE_RXDMA +static int stm32serial_dmasetup(struct uart_dev_s *dev) +{ + struct stm32_serial_s *priv = (struct stm32_serial_s *)dev->priv; + int result; + uint32_t regval; + + /* Do the basic USART setup first, unless we are the console */ + + if (!dev->isconsole) + { + result = stm32serial_setup(dev); + if (result != OK) + { + return result; + } + } + + /* Acquire the DMA channel. This should always succeed. */ + + priv->rxdma = stm32_dmachannel(priv->rxdma_channel); + +#ifdef CONFIG_SERIAL_IFLOWCONTROL + if (priv->iflow) + { + /* Configure for non-circular DMA reception into the RX FIFO */ + + stm32_dmasetup(priv->rxdma, + priv->usartbase + STM32_USART_RDR_OFFSET, + (uint32_t)priv->rxfifo, + RXDMA_BUFFER_SIZE, + SERIAL_DMA_IFLOW_CONTROL_WORD); + } + else +#endif + { + /* Configure for circular DMA reception into the RX FIFO */ + + stm32_dmasetup(priv->rxdma, + priv->usartbase + STM32_USART_RDR_OFFSET, + (uint32_t)priv->rxfifo, + RXDMA_BUFFER_SIZE, + SERIAL_DMA_CONTROL_WORD); + } + + /* Reset our DMA shadow pointer to match the address just + * programmed above. + */ + + priv->rxdmanext = 0; + + /* Enable receive DMA for the USART */ + + regval = stm32serial_getreg(priv, STM32_USART_CR3_OFFSET); + regval |= USART_CR3_DMAR; + stm32serial_putreg(priv, STM32_USART_CR3_OFFSET, regval); + +#ifdef CONFIG_SERIAL_IFLOWCONTROL + if (priv->iflow) + { + /* Start the DMA channel, and arrange for callbacks at the full point + * in the FIFO. After buffer gets full, hardware flow-control kicks + * in and DMA transfer is stopped. + */ + + stm32_dmastart(priv->rxdma, stm32serial_dmarxcallback, + (void *)priv, false); + } + else +#endif + { + /* Start the DMA channel, and arrange for callbacks at the half and + * full points in the FIFO. This ensures that we have half a FIFO + * worth of time to claim bytes before they are overwritten. + */ + + stm32_dmastart(priv->rxdma, stm32serial_dmarxcallback, + (void *)priv, true); + } + + return OK; +} +#endif + +/**************************************************************************** + * Name: stm32serial_shutdown + * + * Description: + * Disable the USART. This method is called when the serial + * port is closed + * + ****************************************************************************/ + +static void stm32serial_shutdown(struct uart_dev_s *dev) +{ + struct stm32_serial_s *priv = (struct stm32_serial_s *)dev->priv; + uint32_t regval; + + /* Disable all interrupts */ + + stm32serial_disableusartint(priv, NULL); + + /* Disable USART APB1/2 clock */ + + stm32serial_setapbclock(dev, false); + + /* Disable Rx, Tx, and the USART */ + + regval = stm32serial_getreg(priv, STM32_USART_CR1_OFFSET); + regval &= ~(USART_CR1_UE | USART_CR1_TE | USART_CR1_RE); + stm32serial_putreg(priv, STM32_USART_CR1_OFFSET, regval); + + /* Release pins. "If the serial-attached device is powered down, the TX + * pin causes back-powering, potentially confusing the device to the point + * of complete lock-up." + * + * REVISIT: Is unconfiguring the pins appropriate for all device? If not, + * then this may need to be a configuration option. + */ + + stm32_unconfiggpio(priv->tx_gpio); + stm32_unconfiggpio(priv->rx_gpio); + +#ifdef CONFIG_SERIAL_OFLOWCONTROL + if (priv->cts_gpio != 0) + { + stm32_unconfiggpio(priv->cts_gpio); + } +#endif + +#ifdef CONFIG_SERIAL_IFLOWCONTROL + if (priv->rts_gpio != 0) + { + stm32_unconfiggpio(priv->rts_gpio); + } +#endif + +#ifdef HAVE_RS485 + if (priv->rs485_dir_gpio != 0) + { + stm32_unconfiggpio(priv->rs485_dir_gpio); + } +#endif +} + +/**************************************************************************** + * Name: stm32serial_dmashutdown + * + * Description: + * Disable the USART. This method is called when the serial + * port is closed + * + ****************************************************************************/ + +#ifdef SERIAL_HAVE_RXDMA +static void stm32serial_dmashutdown(struct uart_dev_s *dev) +{ + struct stm32_serial_s *priv = (struct stm32_serial_s *)dev->priv; + + /* Perform the normal USART shutdown */ + + stm32serial_shutdown(dev); + + /* Stop the DMA channel */ + + stm32_dmastop(priv->rxdma); + + /* Release the DMA channel */ + + stm32_dmafree(priv->rxdma); + priv->rxdma = NULL; +} +#endif + +/**************************************************************************** + * Name: stm32serial_attach + * + * Description: + * Configure the USART to operation in interrupt driven mode. This method + * is called when the serial port is opened. Normally, this is just after + * the setup() method is called, however, the serial console may + * operate in a non-interrupt driven mode during the boot phase. + * + * RX and TX interrupts are not enabled when by the attach method (unless + * the hardware supports multiple levels of interrupt enabling). The RX + * and TX interrupts are not enabled until the txint() and rxint() methods + * are called. + * + ****************************************************************************/ + +static int stm32serial_attach(struct uart_dev_s *dev) +{ + struct stm32_serial_s *priv = (struct stm32_serial_s *)dev->priv; + int ret; + + /* Attach and enable the IRQ */ + + ret = irq_attach(priv->irq, up_interrupt, priv); + if (ret == OK) + { + /* Enable the interrupt (RX and TX interrupts are still disabled + * in the USART + */ + + up_enable_irq(priv->irq); + } + + return ret; +} + +/**************************************************************************** + * Name: stm32serial_detach + * + * Description: + * Detach USART interrupts. This method is called when the serial port + * is closed normally just before the shutdown method is called. + * The exception is the serial console which is never shutdown. + * + ****************************************************************************/ + +static void stm32serial_detach(struct uart_dev_s *dev) +{ + struct stm32_serial_s *priv = (struct stm32_serial_s *)dev->priv; + up_disable_irq(priv->irq); + irq_detach(priv->irq); +} + +/**************************************************************************** + * Name: up_interrupt + * + * Description: + * This is the USART interrupt handler. It will be invoked when an + * interrupt is received on the 'irq'. It should call uart_xmitchars or + * uart_recvchars to perform the appropriate data transfers. The + * interrupt handling logic must be able to map the 'arg' to the + * appropriate stm32_serial_s structure in order to call these functions. + * + ****************************************************************************/ + +static int up_interrupt(int irq, void *context, void *arg) +{ + struct stm32_serial_s *priv = (struct stm32_serial_s *)arg; + int passes; + bool handled; + + DEBUGASSERT(priv != NULL); + + /* Report serial activity to the power management logic */ + +#if defined(CONFIG_PM) && CONFIG_STM32_PM_SERIAL_ACTIVITY > 0 + pm_activity(PM_IDLE_DOMAIN, CONFIG_STM32_PM_SERIAL_ACTIVITY); +#endif + + /* Loop until there are no characters to be transferred or, + * until we have been looping for a long time. + */ + + handled = true; + for (passes = 0; passes < 256 && handled; passes++) + { + handled = false; + + /* Get the masked USART status word. */ + + priv->sr = stm32serial_getreg(priv, STM32_USART_ISR_OFFSET); + + /* USART interrupts: + * + * Enable Status Meaning Usage + * ---------------- -------------- ---------------------- ---------- + * USART_CR1_IDLEIE USART_ISR_IDLE Idle Line Detected (not used) + * USART_CR1_RXNEIE USART_ISR_RXNE Received Data Ready + * to be Read + * " " USART_ISR_ORE Overrun Error Detected + * USART_CR1_TCIE USART_ISR_TC Transmission Complete (used only + * for RS-485) + * USART_CR1_TXEIE USART_ISR_TXE Transmit Data Register + * Empty + * USART_CR1_PEIE USART_ISR_PE Parity Error + * + * USART_CR2_LBDIE USART_ISR_LBD Break Flag (not used) + * USART_CR3_EIE USART_ISR_FE Framing Error + * " " USART_ISR_NE Noise Error + * " " USART_ISR_ORE Overrun Error + * Detected + * USART_CR3_CTSIE USART_ISR_CTS CTS flag (not used) + * + * NOTE: + * Some of these status bits must be cleared by explicitly writing + * zero to the SR register: USART_ISR_CTS, USART_ISR_LBD. + * Note of those are currently being used. + */ + +#ifdef HAVE_RS485 + /* Transmission of whole buffer is over - TC is set, TXEIE is + * cleared. Note - this should be first, to have the most recent TC + * bit value from SR register - sending data affects TC, but without + * refresh we will not know that... + */ + + if ((priv->sr & USART_ISR_TC) != 0 && + (priv->ie & USART_CR1_TCIE) != 0 && + (priv->ie & USART_CR1_TXEIE) == 0) + { + stm32_gpiowrite(priv->rs485_dir_gpio, !priv->rs485_dir_polarity); + stm32serial_restoreusartint(priv, priv->ie & ~USART_CR1_TCIE); + } +#endif + + /* Handle incoming, receive bytes. */ + + if ((priv->sr & USART_ISR_RXNE) != 0 && + (priv->ie & USART_CR1_RXNEIE) != 0) + { + /* Received data ready... process incoming bytes. NOTE the check + * for RXNEIE: We cannot call uart_recvchards of RX interrupts + * are disabled. + */ + + uart_recvchars(&priv->dev); + handled = true; + } + + /* We may still have to read from the DR register to clear any pending + * error conditions. + */ + + else if ((priv->sr & + (USART_ISR_ORE | USART_ISR_NF | USART_ISR_FE)) != 0) + { + /* These errors are cleared by writing the corresponding bit to + * the interrupt clear register (ICR). + */ + + stm32serial_putreg(priv, STM32_USART_ICR_OFFSET, + (USART_ICR_NCF | USART_ICR_ORECF | + USART_ICR_FECF)); + } + + /* Handle outgoing, transmit bytes */ + + if ((priv->sr & USART_ISR_TXE) != 0 && + (priv->ie & USART_CR1_TXEIE) != 0) + { + /* Transmit data register empty ... + * process outgoing bytes + */ + + uart_xmitchars(&priv->dev); + handled = true; + } + } + + return OK; +} + +/**************************************************************************** + * Name: stm32serial_ioctl + * + * Description: + * All ioctl calls will be routed through this method + * + ****************************************************************************/ + +static int stm32serial_ioctl(struct file *filep, int cmd, + unsigned long arg) +{ +#if defined(CONFIG_SERIAL_TERMIOS) || defined(CONFIG_SERIAL_TIOCSERGSTRUCT) + struct inode *inode = filep->f_inode; + struct uart_dev_s *dev = inode->i_private; +#endif +#if defined(CONFIG_SERIAL_TERMIOS) + struct stm32_serial_s *priv = (struct stm32_serial_s *)dev->priv; +#endif + int ret = OK; + + switch (cmd) + { +#ifdef CONFIG_SERIAL_TIOCSERGSTRUCT + case TIOCSERGSTRUCT: + { + struct stm32_serial_s *user = (struct stm32_serial_s *)arg; + if (!user) + { + ret = -EINVAL; + } + else + { + memcpy(user, dev, sizeof(struct stm32_serial_s)); + } + } + break; +#endif + +#ifdef CONFIG_STM32_USART_SINGLEWIRE +#warning please review the potential use of ALTERNATE_FUNCTION_OPENDRAIN + case TIOCSSINGLEWIRE: + { + /* Change the TX port to be open-drain/push-pull and + * enable/disable half-duplex mode. + */ + + uint32_t cr = stm32serial_getreg(priv, STM32_USART_CR3_OFFSET); + + if ((arg & SER_SINGLEWIRE_ENABLED) != 0) + { + uint32_t gpio_val = (arg & SER_SINGLEWIRE_PUSHPULL) == + SER_SINGLEWIRE_PUSHPULL ? + GPIO_PUSHPULL : GPIO_OPENDRAIN; + gpio_val |= + (arg & SER_SINGLEWIRE_PULL_MASK) == + SER_SINGLEWIRE_PULLUP ? + GPIO_PULLUP : GPIO_FLOAT; + gpio_val |= + (arg & SER_SINGLEWIRE_PULL_MASK) == + SER_SINGLEWIRE_PULLDOWN ? + GPIO_PULLDOWN : GPIO_FLOAT; + stm32_configgpio((priv->tx_gpio & + ~(GPIO_PUPD_MASK | GPIO_OPENDRAIN)) | + gpio_val); + cr |= USART_CR3_HDSEL; + } + else + { + stm32_configgpio((priv->tx_gpio & + ~(GPIO_PUPD_MASK | GPIO_OPENDRAIN)) | + GPIO_PUSHPULL); + cr &= ~USART_CR3_HDSEL; + } + + stm32serial_putreg(priv, STM32_USART_CR3_OFFSET, cr); + } + break; +#endif + +#ifdef CONFIG_SERIAL_TERMIOS + case TCGETS: + { + struct termios *termiosp = (struct termios *)arg; + + if (!termiosp) + { + ret = -EINVAL; + break; + } + + cfsetispeed(termiosp, priv->baud); + + /* Note that since we only support 8/9 bit modes and + * there is no way to report 9-bit mode, we always claim 8. + */ + + termiosp->c_cflag = + ((priv->parity != 0) ? PARENB : 0) | + ((priv->parity == 1) ? PARODD : 0) | + ((priv->stopbits2) ? CSTOPB : 0) | +#ifdef CONFIG_SERIAL_OFLOWCONTROL + ((priv->oflow) ? CCTS_OFLOW : 0) | +#endif +#ifdef CONFIG_SERIAL_IFLOWCONTROL + ((priv->iflow) ? CRTS_IFLOW : 0) | +#endif + CS8; + + /* TODO: CRTS_IFLOW, CCTS_OFLOW */ + } + break; + + case TCSETS: + { + struct termios *termiosp = (struct termios *)arg; + + if (!termiosp) + { + ret = -EINVAL; + break; + } + + /* Perform some sanity checks before accepting any changes */ + + if (((termiosp->c_cflag & CSIZE) != CS8) +#ifdef CONFIG_SERIAL_OFLOWCONTROL + || ((termiosp->c_cflag & CCTS_OFLOW) && + (priv->cts_gpio == 0)) +#endif +#ifdef CONFIG_SERIAL_IFLOWCONTROL + || ((termiosp->c_cflag & CRTS_IFLOW) && + (priv->rts_gpio == 0)) +#endif + ) + { + ret = -EINVAL; + break; + } + + if (termiosp->c_cflag & PARENB) + { + priv->parity = (termiosp->c_cflag & PARODD) ? 1 : 2; + } + else + { + priv->parity = 0; + } + + priv->stopbits2 = (termiosp->c_cflag & CSTOPB) != 0; +#ifdef CONFIG_SERIAL_OFLOWCONTROL + priv->oflow = (termiosp->c_cflag & CCTS_OFLOW) != 0; +#endif +#ifdef CONFIG_SERIAL_IFLOWCONTROL + priv->iflow = (termiosp->c_cflag & CRTS_IFLOW) != 0; +#endif + + /* Note that since there is no way to request 9-bit mode + * and no way to support 5/6/7-bit modes, we ignore them + * all here. + */ + + /* Note that only cfgetispeed is used because we have knowledge + * that only one speed is supported. + */ + + priv->baud = cfgetispeed(termiosp); + + /* Effect the changes immediately - note that we do not implement + * TCSADRAIN / TCSAFLUSH + */ + + stm32serial_setformat(dev); + } + break; +#endif /* CONFIG_SERIAL_TERMIOS */ + +#ifdef CONFIG_STM32_USART_BREAKS +# ifdef CONFIG_STM32_SERIALBRK_BSDCOMPAT + case TIOCSBRK: /* BSD compatibility: Turn break on, unconditionally */ + { + irqstate_t flags; + uint32_t tx_break; + + flags = enter_critical_section(); + + /* Disable any further tx activity */ + + priv->ie |= USART_CR1_IE_BREAK_INPROGRESS; + + stm32serial_txint(dev, false); + + /* Configure TX as a GPIO output pin and Send a break signal */ + + tx_break = GPIO_OUTPUT | + (~(GPIO_MODE_MASK | GPIO_OUTPUT_SET) & priv->tx_gpio); + stm32_configgpio(tx_break); + + leave_critical_section(flags); + } + break; + + case TIOCCBRK: /* BSD compatibility: Turn break off, unconditionally */ + { + irqstate_t flags; + + flags = enter_critical_section(); + + /* Configure TX back to U(S)ART */ + + stm32_configgpio(priv->tx_gpio); + + priv->ie &= ~USART_CR1_IE_BREAK_INPROGRESS; + + /* Enable further tx activity */ + + stm32serial_txint(dev, true); + + leave_critical_section(flags); + } + break; +# else + case TIOCSBRK: /* No BSD compatibility: Turn break on for M bit times */ + { + uint32_t cr1; + irqstate_t flags; + + flags = enter_critical_section(); + cr1 = stm32serial_getreg(priv, STM32_USART_CR1_OFFSET); + stm32serial_putreg(priv, STM32_USART_CR1_OFFSET, + cr1 | USART_CR1_SBK); + leave_critical_section(flags); + } + break; + + case TIOCCBRK: /* No BSD compatibility: May turn off break too soon */ + { + uint32_t cr1; + irqstate_t flags; + + flags = enter_critical_section(); + cr1 = stm32serial_getreg(priv, STM32_USART_CR1_OFFSET); + stm32serial_putreg(priv, STM32_USART_CR1_OFFSET, + cr1 & ~USART_CR1_SBK); + leave_critical_section(flags); + } + break; +# endif +#endif + + default: + ret = -ENOTTY; + break; + } + + return ret; +} + +/**************************************************************************** + * Name: stm32serial_receive + * + * Description: + * Called (usually) from the interrupt level to receive one + * character from the USART. Error bits associated with the + * receipt are provided in the return 'status'. + * + ****************************************************************************/ + +#ifndef SERIAL_HAVE_ONLY_DMA +static int stm32serial_receive(struct uart_dev_s *dev, + unsigned int *status) +{ + struct stm32_serial_s *priv = (struct stm32_serial_s *)dev->priv; + uint32_t rdr; + + /* Get the Rx byte */ + + rdr = stm32serial_getreg(priv, STM32_USART_RDR_OFFSET); + + /* Get the Rx byte plux error information. Return those in status */ + + *status = priv->sr << 16 | rdr; + priv->sr = 0; + + /* Then return the actual received byte */ + + return rdr & 0xff; +} +#endif + +/**************************************************************************** + * Name: stm32serial_rxint + * + * Description: + * Call to enable or disable RX interrupts + * + ****************************************************************************/ + +#ifndef SERIAL_HAVE_ONLY_DMA +static void stm32serial_rxint(struct uart_dev_s *dev, bool enable) +{ + struct stm32_serial_s *priv = (struct stm32_serial_s *)dev->priv; + irqstate_t flags; + uint16_t ie; + + /* USART receive interrupts: + * + * Enable Status Meaning Usage + * ---------------- -------------- ----------------------- ---------- + * USART_CR1_IDLEIE USART_ISR_IDLE Idle Line Detected (not used) + * USART_CR1_RXNEIE USART_ISR_RXNE Received Data Ready + * to be Read + * " " USART_ISR_ORE Overrun Error Detected + * USART_CR1_PEIE USART_ISR_PE Parity Error + * + * USART_CR2_LBDIE USART_ISR_LBD Break Flag (not used) + * USART_CR3_EIE USART_ISR_FE Framing Error + * " " USART_ISR_NF Noise Flag + * " " USART_ISR_ORE Overrun Error Detected + */ + + flags = enter_critical_section(); + ie = priv->ie; + if (enable) + { + /* Receive an interrupt when their is anything in the Rx data + * register (or an Rx timeout occurs). + */ + +#ifndef CONFIG_SUPPRESS_SERIAL_INTS +#ifdef CONFIG_USART_ERRINTS + ie |= (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR3_EIE); +#else + ie |= USART_CR1_RXNEIE; +#endif +#endif + } + else + { + ie &= ~(USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR3_EIE); + } + + /* Then set the new interrupt state */ + + stm32serial_restoreusartint(priv, ie); + leave_critical_section(flags); +} +#endif + +/**************************************************************************** + * Name: stm32serial_rxavailable + * + * Description: + * Return true if the receive register is not empty + * + ****************************************************************************/ + +#ifndef SERIAL_HAVE_ONLY_DMA +static bool stm32serial_rxavailable(struct uart_dev_s *dev) +{ + struct stm32_serial_s *priv = (struct stm32_serial_s *)dev->priv; + return ((stm32serial_getreg(priv, + STM32_USART_ISR_OFFSET) & USART_ISR_RXNE) != + 0); +} +#endif + +/**************************************************************************** + * Name: stm32serial_rxflowcontrol + * + * Description: + * Called when Rx buffer is full (or exceeds configured watermark levels + * if CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS is defined). + * Return true if USART activated RX flow control to block more incoming + * data + * + * Input Parameters: + * dev - USART device instance + * nbuffered - the number of characters currently buffered + * (if CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS is + * not defined the value will be 0 for an empty buffer or the + * defined buffer size for a full buffer) + * upper - true indicates the upper watermark was crossed where + * false indicates the lower watermark has been crossed + * + * Returned Value: + * true if RX flow control activated. + * + ****************************************************************************/ + +#ifdef CONFIG_SERIAL_IFLOWCONTROL +static bool stm32serial_rxflowcontrol(struct uart_dev_s *dev, + unsigned int nbuffered, bool upper) +{ + struct stm32_serial_s *priv = (struct stm32_serial_s *)dev->priv; + +#if defined(CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS) && \ + defined(CONFIG_STM32_FLOWCONTROL_BROKEN) + if (priv->iflow && (priv->rts_gpio != 0)) + { + /* Assert/de-assert nRTS set it high resume/stop sending */ + + stm32_gpiowrite(priv->rts_gpio, upper); + return upper; + } + +#else + if (priv->iflow) + { + /* Is the RX buffer full? */ + + if (upper) + { + /* Disable Rx interrupt to prevent more data being from + * peripheral. When hardware RTS is enabled, this will + * prevent more data from coming in. + * + * This function is only called when USART recv buffer is full, + * that is: "dev->recv.head + 1 == dev->recv.tail". + * + * Logic in "uart_read" will automatically toggle Rx interrupts + * when buffer is read empty and thus we do not have to re- + * enable Rx interrupts. + */ + + uart_disablerxint(dev); + return true; + } + + /* No.. The RX buffer is empty */ + + else + { + /* We might leave Rx interrupt disabled if full recv buffer was + * read empty. Enable Rx interrupt to make sure that more input + * is received. + */ + + uart_enablerxint(dev); + } + } +#endif + + return false; +} +#endif + +/**************************************************************************** + * Name: stm32serial_dmareceive + * + * Description: + * Called (usually) from the interrupt level to receive one + * character from the USART. Error bits associated with the + * receipt are provided in the return 'status'. + * + ****************************************************************************/ + +#ifdef SERIAL_HAVE_RXDMA +static int stm32serial_dmareceive(struct uart_dev_s *dev, + unsigned int *status) +{ + struct stm32_serial_s *priv = (struct stm32_serial_s *)dev->priv; + int c = 0; + + if (stm32serial_dmanextrx(priv) != priv->rxdmanext) + { + c = priv->rxfifo[priv->rxdmanext]; + + priv->rxdmanext++; + if (priv->rxdmanext == RXDMA_BUFFER_SIZE) + { +#ifdef CONFIG_SERIAL_IFLOWCONTROL + if (priv->iflow) + { + /* RX DMA buffer full. RX paused, RTS line pulled up to prevent + * more input data from other end. + */ + } + else +#endif + { + priv->rxdmanext = 0; + } + } + } + + return c; +} +#endif + +/**************************************************************************** + * Name: stm32serial_dmareenable + * + * Description: + * Call to re-enable RX DMA. + * + ****************************************************************************/ + +#if defined(SERIAL_HAVE_RXDMA) && defined(CONFIG_SERIAL_IFLOWCONTROL) +static void stm32serial_dmareenable(struct stm32_serial_s *priv) +{ + /* Configure for non-circular DMA reception into the RX fifo */ + + stm32_dmasetup(priv->rxdma, + priv->usartbase + STM32_USART_RDR_OFFSET, + (uint32_t)priv->rxfifo, + RXDMA_BUFFER_SIZE, + SERIAL_DMA_IFLOW_CONTROL_WORD); + + /* Reset our DMA shadow pointer to match the address just + * programmed above. + */ + + priv->rxdmanext = 0; + + /* Start the DMA channel, and arrange for callbacks at the full point in + * the FIFO. After buffer gets full, hardware flow-control kicks in and + * DMA transfer is stopped. + */ + + stm32_dmastart(priv->rxdma, stm32serial_dmarxcallback, (void *)priv, + false); +} +#endif + +/**************************************************************************** + * Name: stm32serial_dmarxint + * + * Description: + * Call to enable or disable RX interrupts + * + ****************************************************************************/ + +#ifdef SERIAL_HAVE_RXDMA +static void stm32serial_dmarxint(struct uart_dev_s *dev, bool enable) +{ + struct stm32_serial_s *priv = (struct stm32_serial_s *)dev->priv; + + /* En/disable DMA reception. + * + * Note that it is not safe to check for available bytes and immediately + * pass them to uart_recvchars as that could potentially recurse back + * to us again. Instead, bytes must wait until the next up_dma_poll or + * DMA event. + */ + + priv->rxenable = enable; + +#ifdef CONFIG_SERIAL_IFLOWCONTROL + if (priv->iflow && priv->rxenable && + (priv->rxdmanext == RXDMA_BUFFER_SIZE)) + { + /* Re-enable RX DMA. */ + + stm32serial_dmareenable(priv); + } +#endif +} +#endif + +/**************************************************************************** + * Name: stm32serial_dmarxavailable + * + * Description: + * Return true if the receive register is not empty + * + ****************************************************************************/ + +#ifdef SERIAL_HAVE_RXDMA +static bool stm32serial_dmarxavailable(struct uart_dev_s *dev) +{ + struct stm32_serial_s *priv = (struct stm32_serial_s *)dev->priv; + + /* Compare our receive pointer to the current DMA pointer, if they + * do not match, then there are bytes to be received. + */ + + return (stm32serial_dmanextrx(priv) != priv->rxdmanext); +} +#endif + +/**************************************************************************** + * Name: stm32serial_send + * + * Description: + * This method will send one byte on the USART + * + ****************************************************************************/ + +static void stm32serial_send(struct uart_dev_s *dev, int ch) +{ + struct stm32_serial_s *priv = (struct stm32_serial_s *)dev->priv; + +#ifdef HAVE_RS485 + if (priv->rs485_dir_gpio != 0) + { + stm32_gpiowrite(priv->rs485_dir_gpio, priv->rs485_dir_polarity); + } +#endif + + stm32serial_putreg(priv, STM32_USART_TDR_OFFSET, (uint32_t)ch); +} + +/**************************************************************************** + * Name: stm32serial_txint + * + * Description: + * Call to enable or disable TX interrupts + * + ****************************************************************************/ + +static void stm32serial_txint(struct uart_dev_s *dev, bool enable) +{ + struct stm32_serial_s *priv = (struct stm32_serial_s *)dev->priv; + irqstate_t flags; + + /* USART transmit interrupts: + * + * Enable Status Meaning Usage + * --------------- ------------- --------------- ---------- + * USART_CR1_TCIE USART_ISR_TC Transmission (used only + * Complete for RS-485) + * USART_CR1_TXEIE USART_ISR_TXE Transmit Data + * Register Empty + * USART_CR3_CTSIE USART_ISR_CTS CTS flag (not used) + */ + + flags = enter_critical_section(); + if (enable) + { + /* Set to receive an interrupt when the TX data register + * is empty + */ + +#ifndef CONFIG_SUPPRESS_SERIAL_INTS + uint16_t ie = priv->ie | USART_CR1_TXEIE; + + /* If RS-485 is supported on this U[S]ART, then also enable the + * transmission complete interrupt. + */ + +# ifdef HAVE_RS485 + if (priv->rs485_dir_gpio != 0) + { + ie |= USART_CR1_TCIE; + } +# endif + +# ifdef CONFIG_STM32_SERIALBRK_BSDCOMPAT + if (priv->ie & USART_CR1_IE_BREAK_INPROGRESS) + { + leave_critical_section(flags); + return; + } +# endif + + stm32serial_restoreusartint(priv, ie); + + /* Fake a TX interrupt here by just calling uart_xmitchars() with + * interrupts disabled (note this may recurse). + */ + + uart_xmitchars(dev); +#endif + } + else + { + /* Disable the TX interrupt */ + + stm32serial_restoreusartint(priv, priv->ie & ~USART_CR1_TXEIE); + } + + leave_critical_section(flags); +} + +/**************************************************************************** + * Name: stm32serial_txready + * + * Description: + * Return true if the transmit data register is empty + * + ****************************************************************************/ + +static bool stm32serial_txready(struct uart_dev_s *dev) +{ + struct stm32_serial_s *priv = (struct stm32_serial_s *)dev->priv; + return ((stm32serial_getreg(priv, + STM32_USART_ISR_OFFSET) & USART_ISR_TXE) != 0); +} + +/**************************************************************************** + * Name: stm32serial_dmarxcallback + * + * Description: + * This function checks the current DMA state and calls the generic + * serial stack when bytes appear to be available. + * + ****************************************************************************/ + +#ifdef SERIAL_HAVE_RXDMA +static void stm32serial_dmarxcallback(DMA_HANDLE handle, uint8_t status, + void *arg) +{ + struct stm32_serial_s *priv = (struct stm32_serial_s *)arg; + + if (priv->rxenable && stm32serial_dmarxavailable(&priv->dev)) + { + uart_recvchars(&priv->dev); + +#ifdef CONFIG_SERIAL_IFLOWCONTROL + if (priv->iflow && priv->rxenable && + (priv->rxdmanext == RXDMA_BUFFER_SIZE)) + { + /* Re-enable RX DMA. */ + + stm32serial_dmareenable(priv); + } +#endif + } +} +#endif + +/**************************************************************************** + * Name: stm32serial_pmnotify + * + * Description: + * Notify the driver of new power state. This callback is called after + * all drivers have had the opportunity to prepare for the new power state. + * + * Input Parameters: + * + * cb - Returned to the driver. The driver version of the callback + * structure may include additional, driver-specific state data at + * the end of the structure. + * + * pmstate - Identifies the new PM state + * + * Returned Value: + * None - The driver already agreed to transition to the low power + * consumption state when when it returned OK to the prepare() call. + * + * + ****************************************************************************/ + +#ifdef CONFIG_PM +static void stm32serial_pmnotify(struct pm_callback_s *cb, int domain, + enum pm_state_e pmstate) +{ + switch (pmstate) + { + case (PM_NORMAL): + { + /* Logic for PM_NORMAL goes here */ + } + break; + + case (PM_IDLE): + { + /* Logic for PM_IDLE goes here */ + } + break; + + case (PM_STANDBY): + { + /* Logic for PM_STANDBY goes here */ + } + break; + + case (PM_SLEEP): + { + /* Logic for PM_SLEEP goes here */ + } + break; + + default: + + /* Should not get here */ + + break; + } +} +#endif + +/**************************************************************************** + * Name: stm32serial_pmprepare + * + * Description: + * Request the driver to prepare for a new power state. This is a warning + * that the system is about to enter into a new power state. The driver + * should begin whatever operations that may be required to enter power + * state. The driver may abort the state change mode by returning a + * non-zero value from the callback function. + * + * Input Parameters: + * + * cb - Returned to the driver. The driver version of the callback + * structure may include additional, driver-specific state data at + * the end of the structure. + * + * pmstate - Identifies the new PM state + * + * Returned Value: + * Zero - (OK) means the event was successfully processed and that the + * driver is prepared for the PM state change. + * + * Non-zero - means that the driver is not prepared to perform the tasks + * needed achieve this power setting and will cause the state + * change to be aborted. NOTE: The prepare() method will also + * be called when reverting from lower back to higher power + * consumption modes (say because another driver refused a + * lower power state change). Drivers are not permitted to + * return non-zero values when reverting back to higher power + * consumption modes! + * + ****************************************************************************/ + +#ifdef CONFIG_PM +static int stm32serial_pmprepare(struct pm_callback_s *cb, int domain, + enum pm_state_e pmstate) +{ + /* Logic to prepare for a reduced power state goes here. */ + + return OK; +} +#endif +#endif /* HAVE_USART */ +#endif /* USE_SERIALDRIVER */ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +#ifdef USE_SERIALDRIVER + +/**************************************************************************** + * Name: arm_earlyserialinit + * + * Description: + * Performs the low level USART initialization early in debug so that the + * serial console will be available during boot up. This must be called + * before stm32serial_getregit. + * + ****************************************************************************/ + +#ifdef USE_EARLYSERIALINIT +void arm_earlyserialinit(void) +{ +#ifdef HAVE_USART + unsigned i; + + /* Disable all USART interrupts */ + + for (i = 0; i < STM32_NUSART; i++) + { + if (g_uart_devs[i]) + { + stm32serial_disableusartint(g_uart_devs[i], NULL); + } + } + + /* Configure whichever one is the console */ + +#if CONSOLE_USART > 0 + stm32serial_setup(&g_uart_devs[CONSOLE_USART - 1]->dev); +#endif +#endif /* HAVE USART */ +} +#endif + +/**************************************************************************** + * Name: stm32serial_getregit + * + * Description: + * Register serial console and serial ports. This assumes + * that arm_earlyserialinit was called previously. + * + ****************************************************************************/ + +void arm_serialinit(void) +{ +#ifdef HAVE_USART + char devname[16]; + unsigned i; + unsigned minor = 0; +#ifdef CONFIG_PM + int ret; +#endif + + /* Register to receive power management callbacks */ + +#ifdef CONFIG_PM + ret = pm_register(&g_serialcb); + DEBUGASSERT(ret == OK); + UNUSED(ret); +#endif + + /* Register the console */ + +#if CONSOLE_USART > 0 + uart_register("/dev/console", &g_uart_devs[CONSOLE_USART - 1]->dev); + +#ifndef CONFIG_STM32_SERIAL_DISABLE_REORDERING + /* If not disabled, register the console USART to ttyS0 and exclude + * it from initializing it further down + */ + + uart_register("/dev/ttyS0", &g_uart_devs[CONSOLE_USART - 1]->dev); + minor = 1; +#endif + +#ifdef SERIAL_HAVE_CONSOLE_DMA + /* If we need to re-initialise the console to enable DMA do that here. */ + + stm32serial_dmasetup(&g_uart_devs[CONSOLE_USART - 1]->dev); +#endif +#endif /* CONSOLE_USART > 0 */ + + /* Register all remaining USARTs */ + + strlcpy(devname, "/dev/ttySx", sizeof(devname)); + + for (i = 0; i < STM32_NUSART; i++) + { + /* Don't create a device for non-configured ports. */ + + if (g_uart_devs[i] == 0) + { + continue; + } + +#ifndef CONFIG_STM32_SERIAL_DISABLE_REORDERING + /* Don't create a device for the console - we did that above */ + + if (g_uart_devs[i]->dev.isconsole) + { + continue; + } +#endif + + /* Register USARTs as devices in increasing order */ + + devname[9] = '0' + minor++; + uart_register(devname, &g_uart_devs[i]->dev); + } +#endif /* HAVE USART */ +} + +/**************************************************************************** + * Name: stm32serial_dmapoll + * + * Description: + * Checks receive DMA buffers for received bytes that have not accumulated + * to the point where the DMA half/full interrupt has triggered. + * + * This function should be called from a timer or other periodic context. + * + ****************************************************************************/ + +#ifdef SERIAL_HAVE_RXDMA +void stm32serial_dmapoll(void) +{ + irqstate_t flags; + + flags = enter_critical_section(); + +#ifdef CONFIG_USART1_RXDMA + if (g_usart1priv.rxdma != NULL) + { + stm32serial_dmarxcallback(g_usart1priv.rxdma, 0, &g_usart1priv); + } +#endif + +#ifdef CONFIG_USART2_RXDMA + if (g_usart2priv.rxdma != NULL) + { + stm32serial_dmarxcallback(g_usart2priv.rxdma, 0, &g_usart2priv); + } +#endif + +#ifdef CONFIG_USART3_RXDMA + if (g_usart3priv.rxdma != NULL) + { + stm32serial_dmarxcallback(g_usart3priv.rxdma, 0, &g_usart3priv); + } +#endif + +#ifdef CONFIG_USART4_RXDMA + if (g_usart4priv.rxdma != NULL) + { + stm32serial_dmarxcallback(g_usart4priv.rxdma, 0, &g_usart4priv); + } +#endif + +#ifdef CONFIG_USART5_RXDMA + if (g_usart5priv.rxdma != NULL) + { + stm32serial_dmarxcallback(g_usart5priv.rxdma, 0, &g_usart5priv); + } +#endif + + leave_critical_section(flags); +} +#endif + +/**************************************************************************** + * Name: up_putc + * + * Description: + * Provide priority, low-level access to support OS debug writes + * + ****************************************************************************/ + +void up_putc(int ch) +{ +#if CONSOLE_USART > 0 + struct stm32_serial_s *priv = g_uart_devs[CONSOLE_USART - 1]; + uint16_t ie; + + stm32serial_disableusartint(priv, &ie); + arm_lowputc(ch); + stm32serial_restoreusartint(priv, ie); +#endif +} + +#else /* USE_SERIALDRIVER */ + +/**************************************************************************** + * Name: up_putc + * + * Description: + * Provide priority, low-level access to support OS debug writes + * + ****************************************************************************/ + +void up_putc(int ch) +{ +#if CONSOLE_USART > 0 + arm_lowputc(ch); +#endif +} + +#endif /* USE_SERIALDRIVER */ diff --git a/arch/arm/src/common/stm32/stm32_serial_m0_v4.c b/arch/arm/src/common/stm32/stm32_serial_m0_v4.c new file mode 100644 index 0000000000000..feb3307bc6d84 --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_serial_m0_v4.c @@ -0,0 +1,2048 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_serial_m0_v4.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#ifdef CONFIG_SERIAL_TERMIOS +# include +#endif + +#include "arm_internal.h" +#include "chip.h" +#include "stm32_gpio.h" +#include "hardware/stm32_pinmap.h" +#include "stm32_rcc.h" +#include "stm32_uart.h" + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Some sanity checks *******************************************************/ + +/* Total number of possible serial devices */ + +#define STM32_NSERIAL (STM32_NUSART) +#define HAVE_UART + +/* Power management definitions */ + +#if defined(CONFIG_PM) && !defined(CONFIG_STM32_PM_SERIAL_ACTIVITY) +# define CONFIG_STM32_PM_SERIAL_ACTIVITY 10 +#endif + +/* Keep track if a Break was set + * + * Note: + * + * 1) This value is set in the priv->ie but never written to the control + * register. It must not collide with USART_CR1_USED_INTS or USART_CR3_EIE + * 2) USART_CR3_EIE is also carried in the up_dev_s ie member. + * + * See up_restoreusartint where the masking is done. + */ + +#ifdef CONFIG_STM32_SERIALBRK_BSDCOMPAT +# define USART_CR1_IE_BREAK_INPROGRESS_SHFTS 15 +# define USART_CR1_IE_BREAK_INPROGRESS (1 << USART_CR1_IE_BREAK_INPROGRESS_SHFTS) +#endif + +#ifdef USE_SERIALDRIVER +#ifdef HAVE_UART + +/* Warnings for potentially unsafe configuration combinations. */ + +#if defined(CONFIG_STM32_FLOWCONTROL_BROKEN) && \ + !defined(CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS) +# error "CONFIG_STM32_FLOWCONTROL_BROKEN requires \ + CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS to be enabled." +#endif + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +struct up_dev_s +{ + struct uart_dev_s dev; /* Generic UART device */ + uint16_t ie; /* Saved interrupt mask bits value */ + uint16_t sr; /* Saved status bits */ + + /* Has been initialized and HW is setup. */ + + bool initialized; + + /* If termios are supported, then the following fields may vary at + * runtime. + */ + +#ifdef CONFIG_SERIAL_TERMIOS + uint8_t rxftcfg; /* Rx FIFO threshold level */ + uint8_t parity; /* 0=none, 1=odd, 2=even */ + uint8_t bits; /* Number of bits (7 or 8) */ + bool stopbits2; /* True: Configure with 2 stop bits instead of 1 */ +#ifdef CONFIG_SERIAL_IFLOWCONTROL + bool iflow; /* input flow control (RTS) enabled */ +#endif +#ifdef CONFIG_SERIAL_OFLOWCONTROL + bool oflow; /* output flow control (CTS) enabled */ +#endif + uint32_t baud; /* Configured baud */ +#else + const uint8_t rxftcfg; /* Rx FIFO threshold level */ + const uint8_t parity; /* 0=none, 1=odd, 2=even */ + const uint8_t bits; /* Number of bits (7 or 8) */ + const bool stopbits2; /* True: Configure with 2 stop bits instead of 1 */ +#ifdef CONFIG_SERIAL_IFLOWCONTROL + const bool iflow; /* input flow control (RTS) enabled */ +#endif +#ifdef CONFIG_SERIAL_OFLOWCONTROL + const bool oflow; /* output flow control (CTS) enabled */ +#endif + const uint32_t baud; /* Configured baud */ +#endif + + const uint8_t irq; /* IRQ associated with this USART */ + const uint32_t apbclock; /* PCLK 1 or 2 frequency */ + const uint32_t usartbase; /* Base address of USART registers */ + const uint32_t tx_gpio; /* U[S]ART TX GPIO pin configuration */ + const uint32_t rx_gpio; /* U[S]ART RX GPIO pin configuration */ +#ifdef CONFIG_SERIAL_IFLOWCONTROL + const uint32_t rts_gpio; /* U[S]ART RTS GPIO pin configuration */ +#endif +#ifdef CONFIG_SERIAL_OFLOWCONTROL + const uint32_t cts_gpio; /* U[S]ART CTS GPIO pin configuration */ +#endif + +#ifdef HAVE_RS485 + const uint32_t rs485_dir_gpio; /* U[S]ART RS-485 DIR GPIO pin configuration */ + const bool rs485_dir_polarity; /* U[S]ART RS-485 DIR pin state for TX enabled */ +#endif + spinlock_t lock; +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +static void up_set_format(struct uart_dev_s *dev); +static int up_setup(struct uart_dev_s *dev); +static void up_shutdown(struct uart_dev_s *dev); +static int up_attach(struct uart_dev_s *dev); +static void up_detach(struct uart_dev_s *dev); +static int up_interrupt(int irq, void *context, void *arg); +static int up_ioctl(struct file *filep, int cmd, unsigned long arg); +static int up_receive(struct uart_dev_s *dev, unsigned int *status); +static void up_rxint(struct uart_dev_s *dev, bool enable); +static bool up_rxavailable(struct uart_dev_s *dev); +#ifdef CONFIG_SERIAL_IFLOWCONTROL +static bool up_rxflowcontrol(struct uart_dev_s *dev, unsigned int nbuffered, + bool upper); +#endif +static void up_send(struct uart_dev_s *dev, int ch); +static void up_txint(struct uart_dev_s *dev, bool enable); +static bool up_txready(struct uart_dev_s *dev); + +#ifdef CONFIG_PM +static void up_pm_notify(struct pm_callback_s *cb, int domain, + enum pm_state_e pmstate); +static int up_pm_prepare(struct pm_callback_s *cb, int domain, + enum pm_state_e pmstate); +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static const struct uart_ops_s g_uart_ops = +{ + .setup = up_setup, + .shutdown = up_shutdown, + .attach = up_attach, + .detach = up_detach, + .ioctl = up_ioctl, + .receive = up_receive, + .rxint = up_rxint, + .rxavailable = up_rxavailable, +#ifdef CONFIG_SERIAL_IFLOWCONTROL + .rxflowcontrol = up_rxflowcontrol, +#endif + .send = up_send, + .txint = up_txint, + .txready = up_txready, + .txempty = up_txready, +}; + +/* Receive/Transmit buffers */ + +#ifdef CONFIG_STM32_USART1 +static char g_usart1rxbuffer[CONFIG_USART1_RXBUFSIZE]; +static char g_usart1txbuffer[CONFIG_USART1_TXBUFSIZE]; +#endif + +#ifdef CONFIG_STM32_USART2 +static char g_usart2rxbuffer[CONFIG_USART2_RXBUFSIZE]; +static char g_usart2txbuffer[CONFIG_USART2_TXBUFSIZE]; +#endif + +#ifdef CONFIG_STM32_USART3 +static char g_usart3rxbuffer[CONFIG_USART3_RXBUFSIZE]; +static char g_usart3txbuffer[CONFIG_USART3_TXBUFSIZE]; +#endif + +#ifdef CONFIG_STM32_USART4 +static char g_usart4rxbuffer[CONFIG_USART4_RXBUFSIZE]; +static char g_usart4txbuffer[CONFIG_USART4_TXBUFSIZE]; +#endif + +/* This describes the state of the STM32 USART1 ports. */ + +#ifdef CONFIG_STM32_USART1 +static struct up_dev_s g_usart1priv = +{ + .dev = + { +#if CONSOLE_USART == 1 + .isconsole = true, +#endif + .recv = + { + .size = CONFIG_USART1_RXBUFSIZE, + .buffer = g_usart1rxbuffer, + }, + .xmit = + { + .size = CONFIG_USART1_TXBUFSIZE, + .buffer = g_usart1txbuffer, + }, + .ops = &g_uart_ops, + .priv = &g_usart1priv, + }, + + .irq = STM32_IRQ_USART1, + .rxftcfg = CONFIG_USART1_RXFIFO_THRES, + .parity = CONFIG_USART1_PARITY, + .bits = CONFIG_USART1_BITS, + .stopbits2 = CONFIG_USART1_2STOP, + .baud = CONFIG_USART1_BAUD, + .apbclock = STM32_PCLK1_FREQUENCY, + .usartbase = STM32_USART1_BASE, + .tx_gpio = GPIO_USART1_TX, + .rx_gpio = GPIO_USART1_RX, +#if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_USART1_OFLOWCONTROL) + .oflow = true, + .cts_gpio = GPIO_USART1_CTS, +#endif +#if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_USART1_IFLOWCONTROL) + .iflow = true, + .rts_gpio = GPIO_USART1_RTS, +#endif + +#ifdef CONFIG_USART1_RS485 + .rs485_dir_gpio = GPIO_USART1_RS485_DIR, +# if (CONFIG_USART1_RS485_DIR_POLARITY == 0) + .rs485_dir_polarity = false, +# else + .rs485_dir_polarity = true, +# endif +#endif + .lock = SP_UNLOCKED, +}; +#endif + +/* This describes the state of the STM32 USART2 port. */ + +#ifdef CONFIG_STM32_USART2 +static struct up_dev_s g_usart2priv = +{ + .dev = + { +#if CONSOLE_USART == 2 + .isconsole = true, +#endif + .recv = + { + .size = CONFIG_USART2_RXBUFSIZE, + .buffer = g_usart2rxbuffer, + }, + .xmit = + { + .size = CONFIG_USART2_TXBUFSIZE, + .buffer = g_usart2txbuffer, + }, + .ops = &g_uart_ops, + .priv = &g_usart2priv, + }, + + .irq = STM32_IRQ_USART2, + .rxftcfg = CONFIG_USART2_RXFIFO_THRES, + .parity = CONFIG_USART2_PARITY, + .bits = CONFIG_USART2_BITS, + .stopbits2 = CONFIG_USART2_2STOP, + .baud = CONFIG_USART2_BAUD, + .apbclock = STM32_PCLK1_FREQUENCY, + .usartbase = STM32_USART2_BASE, + .tx_gpio = GPIO_USART2_TX, + .rx_gpio = GPIO_USART2_RX, +#if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_USART2_OFLOWCONTROL) + .oflow = true, + .cts_gpio = GPIO_USART2_CTS, +#endif +#if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_USART2_IFLOWCONTROL) + .iflow = true, + .rts_gpio = GPIO_USART2_RTS, +#endif + +#ifdef CONFIG_USART2_RS485 + .rs485_dir_gpio = GPIO_USART2_RS485_DIR, +# if (CONFIG_USART2_RS485_DIR_POLARITY == 0) + .rs485_dir_polarity = false, +# else + .rs485_dir_polarity = true, +# endif +#endif + .lock = SP_UNLOCKED, +}; +#endif + +/* This describes the state of the STM32 USART3 port. */ + +#ifdef CONFIG_STM32_USART3 +static struct up_dev_s g_usart3priv = +{ + .dev = + { +#if CONSOLE_USART == 3 + .isconsole = true, +#endif + .recv = + { + .size = CONFIG_USART3_RXBUFSIZE, + .buffer = g_usart3rxbuffer, + }, + .xmit = + { + .size = CONFIG_USART3_TXBUFSIZE, + .buffer = g_usart3txbuffer, + }, + .ops = &g_uart_ops, + .priv = &g_usart3priv, + }, + + .irq = STM32_IRQ_USART3, + .rxftcfg = 0, /* No FIFO */ + .parity = CONFIG_USART3_PARITY, + .bits = CONFIG_USART3_BITS, + .stopbits2 = CONFIG_USART3_2STOP, + .baud = CONFIG_USART3_BAUD, + .apbclock = STM32_PCLK1_FREQUENCY, + .usartbase = STM32_USART3_BASE, + .tx_gpio = GPIO_USART3_TX, + .rx_gpio = GPIO_USART3_RX, +#if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_USART3_OFLOWCONTROL) + .oflow = true, + .cts_gpio = GPIO_USART3_CTS, +#endif +#if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_USART3_IFLOWCONTROL) + .iflow = true, + .rts_gpio = GPIO_USART3_RTS, +#endif + +#ifdef CONFIG_USART3_RS485 + .rs485_dir_gpio = GPIO_USART3_RS485_DIR, +# if (CONFIG_USART3_RS485_DIR_POLARITY == 0) + .rs485_dir_polarity = false, +# else + .rs485_dir_polarity = true, +# endif +#endif + .lock = SP_UNLOCKED, +}; +#endif + +/* This describes the state of the STM32 USART4 port. */ + +#ifdef CONFIG_STM32_USART4 +static struct up_dev_s g_usart4priv = +{ + .dev = + { +#if CONSOLE_USART == 4 + .isconsole = true, +#endif + .recv = + { + .size = CONFIG_USART4_RXBUFSIZE, + .buffer = g_usart4rxbuffer, + }, + .xmit = + { + .size = CONFIG_USART4_TXBUFSIZE, + .buffer = g_usart4txbuffer, + }, + .ops = &g_uart_ops, + .priv = &g_usart4priv, + }, + + .irq = STM32_IRQ_USART4, + .rxftcfg = 0, /* No FIFO */ + .parity = CONFIG_USART4_PARITY, + .bits = CONFIG_USART4_BITS, + .stopbits2 = CONFIG_USART4_2STOP, + .baud = CONFIG_USART4_BAUD, + .apbclock = STM32_PCLK1_FREQUENCY, + .usartbase = STM32_USART4_BASE, + .tx_gpio = GPIO_USART4_TX, + .rx_gpio = GPIO_USART4_RX, +#if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_USART4_OFLOWCONTROL) + .oflow = true, + .cts_gpio = GPIO_USART4_CTS, +#endif +#if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_USART4_IFLOWCONTROL) + .iflow = true, + .rts_gpio = GPIO_USART4_RTS, +#endif + +#ifdef CONFIG_USART4_RS485 + .rs485_dir_gpio = GPIO_USART4_RS485_DIR, +# if (CONFIG_USART4_RS485_DIR_POLARITY == 0) + .rs485_dir_polarity = false, +# else + .rs485_dir_polarity = true, +# endif +#endif + .lock = SP_UNLOCKED, +}; +#endif + +/* This table lets us iterate over the configured USARTs */ + +static struct up_dev_s * const g_uart_devs[STM32_NSERIAL] = +{ +#ifdef CONFIG_STM32_USART1 + [0] = &g_usart1priv, +#endif +#ifdef CONFIG_STM32_USART2 + [1] = &g_usart2priv, +#endif +#ifdef CONFIG_STM32_USART3 + [2] = &g_usart3priv, +#endif +#ifdef CONFIG_STM32_USART4 + [3] = &g_usart4priv +#endif +}; + +#ifdef CONFIG_PM +static struct pm_callback_s g_serialcb = +{ + .notify = up_pm_notify, + .prepare = up_pm_prepare, +}; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_serialin + ****************************************************************************/ + +static inline uint32_t up_serialin(struct up_dev_s *priv, int offset) +{ + return getreg32(priv->usartbase + offset); +} + +/**************************************************************************** + * Name: up_serialout + ****************************************************************************/ + +static inline void up_serialout(struct up_dev_s *priv, + int offset, uint32_t value) +{ + putreg32(value, priv->usartbase + offset); +} + +/**************************************************************************** + * Name: up_setusartint + ****************************************************************************/ + +static inline void up_setusartint(struct up_dev_s *priv, uint16_t ie) +{ + uint32_t cr; + + /* Save the interrupt mask */ + + priv->ie = ie; + + /* And restore the interrupt state + * (see the interrupt enable/usage table above) + */ + + cr = up_serialin(priv, STM32_USART_CR1_OFFSET); + cr &= ~(USART_CR1_USED_INTS); + cr |= (ie & (USART_CR1_USED_INTS)); + up_serialout(priv, STM32_USART_CR1_OFFSET, cr); + + cr = up_serialin(priv, STM32_USART_CR3_OFFSET); + cr &= ~USART_CR3_EIE; + cr |= (ie & USART_CR3_EIE); + up_serialout(priv, STM32_USART_CR3_OFFSET, cr); +} + +/**************************************************************************** + * Name: up_restoreusartint + ****************************************************************************/ + +static void up_restoreusartint(struct up_dev_s *priv, uint16_t ie) +{ + irqstate_t flags; + + flags = spin_lock_irqsave(&priv->lock); + + up_setusartint(priv, ie); + + spin_unlock_irqrestore(&priv->lock, flags); +} + +/**************************************************************************** + * Name: up_disableusartint + ****************************************************************************/ + +static void up_disableusartint(struct up_dev_s *priv, uint16_t *ie) +{ + irqstate_t flags; + + flags = spin_lock_irqsave(&priv->lock); + + if (ie) + { + uint32_t cr1; + uint32_t cr3; + + /* USART interrupts: + * + * Enable Status Meaning Usage + * ---------------- -------------- ----------------------- ---------- + * USART_CR1_IDLEIE USART_ISR_IDLE Idle Line Detected (not used) + * USART_CR1_RXNEIE USART_ISR_RXNE Received Data Ready + * to be Read + * " " USART_ISR_ORE Overrun Error Detected + * USART_CR1_TCIE USART_ISR_TC Transmission Complete (used only + * for RS-485) + * USART_CR1_TXEIE USART_ISR_TXE Transmit Data Register + * Empty + * USART_CR1_PEIE USART_ISR_PE Parity Error + * + * USART_CR2_LBDIE USART_ISR_LBD Break Flag (not used) + * USART_CR3_EIE USART_ISR_FE Framing Error + * " " USART_ISR_NF Noise Error + * " " USART_ISR_ORE Overrun Error Detected + * USART_CR3_CTSIE USART_ISR_CTS CTS flag (not used) + */ + + cr1 = up_serialin(priv, STM32_USART_CR1_OFFSET); + cr3 = up_serialin(priv, STM32_USART_CR3_OFFSET); + + /* Return the current interrupt mask value for the used interrupts. + * Notice that this depends on the fact that none of the used interrupt + * enable bits overlap. + * This logic would fail if we needed the break interrupt! + */ + + *ie = (cr1 & (USART_CR1_USED_INTS)) | (cr3 & USART_CR3_EIE); + } + + /* Disable all interrupts */ + + up_setusartint(priv, 0); + + spin_unlock_irqrestore(&priv->lock, flags); +} + +/**************************************************************************** + * Name: up_set_format + * + * Description: + * Set the serial line format and speed. + * + ****************************************************************************/ + +#ifndef CONFIG_SUPPRESS_UART_CONFIG +static void up_set_format(struct uart_dev_s *dev) +{ + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; + uint32_t regval; + uint32_t usartdiv8; + uint32_t cr1; + uint32_t cr1_ue; + uint32_t brr; + irqstate_t flags; + + flags = enter_critical_section(); + + /* Get the original state of UE */ + + cr1 = up_serialin(priv, STM32_USART_CR1_OFFSET); + cr1_ue = cr1 & USART_CR1_UE; + cr1 &= ~USART_CR1_UE; + + /* Disable UE as the format bits and baud rate registers can not be + * updated while UE = 1 + */ + + up_serialout(priv, STM32_USART_CR1_OFFSET, cr1); + + /* In case of oversampling by 8, the equation is: + * + * baud = 2 * fCK / usartdiv8 + * usartdiv8 = 2 * fCK / baud + */ + + usartdiv8 = ((priv->apbclock << 1) + (priv->baud >> 1)) / priv->baud; + + /* Baud rate for standard USART (SPI mode included): + * + * In case of oversampling by 16, the equation is: + * baud = fCK / usartdiv16 + * usartdiv16 = fCK / baud + * = 2 * usartdiv8 + */ + + /* Use oversamply by 8 only if the divisor is small. But what is small? */ + + if (usartdiv8 > 100) + { + /* Use usartdiv16 */ + + brr = (usartdiv8 + 1) >> 1; + + /* Clear oversampling by 8 to enable oversampling by 16 */ + + cr1 &= ~USART_CR1_OVER8; + } + else + { + DEBUGASSERT(usartdiv8 >= 8); + + /* Perform mysterious operations on bits 0-3 */ + + brr = ((usartdiv8 & 0xfff0) | ((usartdiv8 & 0x000f) >> 1)); + + /* Set oversampling by 8 */ + + cr1 |= USART_CR1_OVER8; + } + + up_serialout(priv, STM32_USART_CR1_OFFSET, cr1); + up_serialout(priv, STM32_USART_BRR_OFFSET, brr); + + /* Configure parity mode */ + + cr1 &= ~(USART_CR1_PCE | USART_CR1_PS | USART_CR1_M0 | USART_CR1_M1); + + if (priv->parity == 1) /* Odd parity */ + { + cr1 |= (USART_CR1_PCE | USART_CR1_PS); + } + else if (priv->parity == 2) /* Even parity */ + { + cr1 |= USART_CR1_PCE; + } + + /* Configure word length (parity uses one of configured bits) + * + * Default: 1 start, 8 data (no parity), n stop, OR + * 1 start, 7 data + parity, n stop + */ + + if (priv->bits == 9 || (priv->bits == 8 && priv->parity != 0)) + { + /* Select: 1 start, 8 data + parity, n stop, OR + * 1 start, 9 data (no parity), n stop. + */ + + cr1 |= USART_CR1_M0; + } + else if (priv->bits == 7 && priv->parity == 0) + { + /* Select: 1 start, 7 data (no parity), n stop, OR + */ + + cr1 |= USART_CR1_M1; + } + + /* Else Select: 1 start, 7 data + parity, n stop, OR + * 1 start, 8 data (no parity), n stop. + */ + + up_serialout(priv, STM32_USART_CR1_OFFSET, cr1); + + /* Configure STOP bits */ + + regval = up_serialin(priv, STM32_USART_CR2_OFFSET); + regval &= ~(USART_CR2_STOP_MASK); + + if (priv->stopbits2) + { + regval |= USART_CR2_STOP2; + } + + up_serialout(priv, STM32_USART_CR2_OFFSET, regval); + + /* Configure hardware flow control */ + + regval = up_serialin(priv, STM32_USART_CR3_OFFSET); + regval &= ~(USART_CR3_CTSE | USART_CR3_RTSE); + +#if defined(CONFIG_SERIAL_IFLOWCONTROL) && \ + !defined(CONFIG_STM32_FLOWCONTROL_BROKEN) + if (priv->iflow && (priv->rts_gpio != 0)) + { + regval |= USART_CR3_RTSE; + } +#endif + +#ifdef CONFIG_SERIAL_OFLOWCONTROL + if (priv->oflow && (priv->cts_gpio != 0)) + { + regval |= USART_CR3_CTSE; + } +#endif + + up_serialout(priv, STM32_USART_CR3_OFFSET, regval); + up_serialout(priv, STM32_USART_CR1_OFFSET, cr1 | cr1_ue); + leave_critical_section(flags); +} +#endif /* CONFIG_SUPPRESS_UART_CONFIG */ + +/**************************************************************************** + * Name: up_set_apb_clock + * + * Description: + * Enable or disable APB clock for the USART peripheral + * + * Input Parameters: + * dev - A reference to the UART driver state structure + * on - Enable clock if 'on' is 'true' and disable if 'false' + * + ****************************************************************************/ + +static void up_set_apb_clock(struct uart_dev_s *dev, bool on) +{ + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; + uint32_t rcc_en; + uint32_t regaddr; + + /* Determine which USART to configure */ + + switch (priv->usartbase) + { + default: + return; +#ifdef CONFIG_STM32_USART1 + case STM32_USART1_BASE: + rcc_en = RCC_APB2ENR_USART1EN; + regaddr = STM32_RCC_APB2ENR; + break; +#endif +#ifdef CONFIG_STM32_USART2 + case STM32_USART2_BASE: + rcc_en = RCC_APB1ENR_USART2EN; + regaddr = STM32_RCC_APB1ENR; + break; +#endif +#ifdef CONFIG_STM32_USART3 + case STM32_USART3_BASE: + rcc_en = RCC_APB1ENR_USART3EN; + regaddr = STM32_RCC_APB1ENR; + break; +#endif +#ifdef CONFIG_STM32_USART4 + case STM32_USART4_BASE: + rcc_en = RCC_APB1ENR_USART4EN; + regaddr = STM32_RCC_APB1ENR; + break; +#endif + } + + /* Enable/disable APB 1/2 clock for USART */ + + if (on) + { + modifyreg32(regaddr, 0, rcc_en); + } + else + { + modifyreg32(regaddr, rcc_en, 0); + } +} + +/**************************************************************************** + * Name: up_setup + * + * Description: + * Configure the USART baud, bits, parity, etc. This method is called the + * first time that the serial port is opened. + * + ****************************************************************************/ + +static int up_setup(struct uart_dev_s *dev) +{ + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; + + /* Make sure that USART is disabled */ + + up_serialout(priv, STM32_USART_CR1_OFFSET, 0); + +#ifndef CONFIG_SUPPRESS_UART_CONFIG + uint32_t regval; + + /* Note: The logic here depends on the fact that that the USART module + * was enabled in stm32_lowsetup(). + */ + + /* Enable USART APB1/2 clock */ + + up_set_apb_clock(dev, true); + + /* Configure pins for USART use */ + + stm32_configgpio(priv->tx_gpio); + stm32_configgpio(priv->rx_gpio); + +#ifdef CONFIG_SERIAL_OFLOWCONTROL + if (priv->cts_gpio != 0) + { + stm32_configgpio(priv->cts_gpio); + } +#endif + +#ifdef CONFIG_SERIAL_IFLOWCONTROL + if (priv->rts_gpio != 0) + { + uint32_t config = priv->rts_gpio; + +#ifdef CONFIG_STM32_FLOWCONTROL_BROKEN + /* Instead of letting hw manage this pin, we will bitbang */ + + config = (config & ~GPIO_MODE_MASK) | GPIO_OUTPUT; +#endif + stm32_configgpio(config); + } +#endif + +#ifdef HAVE_RS485 + if (priv->rs485_dir_gpio != 0) + { + stm32_configgpio(priv->rs485_dir_gpio); + stm32_gpiowrite(priv->rs485_dir_gpio, !priv->rs485_dir_polarity); + } +#endif + + /* Configure CR2 + * + * Clear STOP, CLKEN, CPOL, CPHA, LBCL, and interrupt enable bits + */ + + regval = up_serialin(priv, STM32_USART_CR2_OFFSET); + regval &= ~(USART_CR2_STOP_MASK | USART_CR2_CLKEN | USART_CR2_CPOL | + USART_CR2_CPHA | USART_CR2_LBCL | USART_CR2_LBDIE); + + /* Configure STOP bits */ + + if (priv->stopbits2) + { + regval |= USART_CR2_STOP2; + } + + up_serialout(priv, STM32_USART_CR2_OFFSET, regval); + + /* Configure CR1 + * + * Clear TE, REm and all interrupt enable bits + */ + + regval = up_serialin(priv, STM32_USART_CR1_OFFSET); + regval &= ~(USART_CR1_TE | USART_CR1_RE | USART_CR1_ALLINTS); + + up_serialout(priv, STM32_USART_CR1_OFFSET, regval); + + /* Configure CR3 + * + * Clear CTSE, RTSE, and all interrupt enable bits + */ + + regval = up_serialin(priv, STM32_USART_CR3_OFFSET); + regval &= ~(USART_CR3_CTSIE | USART_CR3_CTSE | + USART_CR3_RTSE | USART_CR3_EIE); + + /* Set Rx FIFO threshold to the configured level */ + + regval |= USART_CR3_RXFTCFG(priv->rxftcfg); + + up_serialout(priv, STM32_USART_CR3_OFFSET, regval); + + /* Configure the USART line format and speed. */ + + up_set_format(dev); + + /* Enable Rx, Tx, and the USART */ + + /* Enable FIFO */ + + regval = up_serialin(priv, STM32_USART_CR1_OFFSET); + regval |= (USART_CR1_UE | USART_CR1_TE | USART_CR1_RE); + regval |= USART_CR1_FIFOEN; + + up_serialout(priv, STM32_USART_CR1_OFFSET, regval); + +#endif /* CONFIG_SUPPRESS_UART_CONFIG */ + + /* Set up the cached interrupt enables value */ + + priv->ie = 0; + + /* Mark device as initialized. */ + + priv->initialized = true; + + return OK; +} + +/**************************************************************************** + * Name: up_shutdown + * + * Description: + * Disable the USART. This method is called when the serial + * port is closed + * + ****************************************************************************/ + +static void up_shutdown(struct uart_dev_s *dev) +{ + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; + uint32_t regval; + + /* Mark device as uninitialized. */ + + priv->initialized = false; + + /* Disable all interrupts */ + + up_disableusartint(priv, NULL); + + /* Disable USART APB1/2 clock */ + + up_set_apb_clock(dev, false); + + /* Disable Rx, Tx, and the UART */ + + regval = up_serialin(priv, STM32_USART_CR1_OFFSET); + regval &= ~(USART_CR1_UE | USART_CR1_TE | USART_CR1_RE); + up_serialout(priv, STM32_USART_CR1_OFFSET, regval); + + /* Release pins. + * "If the serial-attached device is powered down, the TX pin causes + * back-powering, potentially confusing the device to the point of + * complete lock-up." + * + * REVISIT: Is unconfiguring the pins appropriate for all device? + * If not, then this may need to be a configuration option. + */ + + stm32_unconfiggpio(priv->tx_gpio); + stm32_unconfiggpio(priv->rx_gpio); + +#ifdef CONFIG_SERIAL_OFLOWCONTROL + if (priv->cts_gpio != 0) + { + stm32_unconfiggpio(priv->cts_gpio); + } +#endif + +#ifdef CONFIG_SERIAL_IFLOWCONTROL + if (priv->rts_gpio != 0) + { + stm32_unconfiggpio(priv->rts_gpio); + } +#endif + +#ifdef HAVE_RS485 + if (priv->rs485_dir_gpio != 0) + { + stm32_unconfiggpio(priv->rs485_dir_gpio); + } +#endif +} + +/**************************************************************************** + * Name: up_attach + * + * Description: + * Configure the USART to operation in interrupt driven mode. This method + * is called when the serial port is opened. Normally, this is just after + * the setup() method is called, however, the serial console may + * operate in a non-interrupt driven mode during the boot phase. + * + * RX and TX interrupts are not enabled when by the attach method (unless + * the hardware supports multiple levels of interrupt enabling). The RX + * and TX interrupts are not enabled until the txint() and rxint() methods + * are called. + * + ****************************************************************************/ + +static int up_attach(struct uart_dev_s *dev) +{ + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; + int ret; + + /* Attach and enable the IRQ */ + + ret = irq_attach(priv->irq, up_interrupt, priv); + if (ret == OK) + { + /* Enable the interrupt (RX and TX interrupts are still disabled + * in the USART + */ + + up_enable_irq(priv->irq); + } + + return ret; +} + +/**************************************************************************** + * Name: up_detach + * + * Description: + * Detach USART interrupts. This method is called when the serial port is + * closed normally just before the shutdown method is called. + * The exception is the serial console which is never shutdown. + * + ****************************************************************************/ + +static void up_detach(struct uart_dev_s *dev) +{ + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; + up_disable_irq(priv->irq); + irq_detach(priv->irq); +} + +/**************************************************************************** + * Name: up_interrupt + * + * Description: + * This is the USART interrupt handler. It will be invoked when an + * interrupt is received on the 'irq'. It should call uart_xmitchars or + * uart_recvchars to perform the appropriate data transfers. The + * interrupt handling logic must be able to map the 'arg' to the + * appropriate uart_dev_s structure in order to call these functions. + * + ****************************************************************************/ + +static int up_interrupt(int irq, void *context, void *arg) +{ + struct up_dev_s *priv = (struct up_dev_s *)arg; + int passes; + bool handled; + + DEBUGASSERT(priv != NULL); + + /* Report serial activity to the power management logic */ + +#if defined(CONFIG_PM) && CONFIG_STM32_PM_SERIAL_ACTIVITY > 0 + pm_activity(PM_IDLE_DOMAIN, CONFIG_STM32_PM_SERIAL_ACTIVITY); +#endif + + /* Loop until there are no characters to be transferred or, + * until we have been looping for a long time. + */ + + handled = true; + for (passes = 0; passes < 256 && handled; passes++) + { + handled = false; + + /* Get the masked USART status word. */ + + priv->sr = up_serialin(priv, STM32_USART_ISR_OFFSET); + + /* USART interrupts: + * + * Enable Status Meaning Usage + * ---------------- -------------- ----------------------- ---------- + * USART_CR1_IDLEIE USART_ISR_IDLE Idle Line Detected (not used) + * USART_CR1_RXNEIE USART_ISR_RXNE Received Data Ready + * to be Read + * " " USART_ISR_ORE Overrun Error Detected + * USART_CR1_TCIE USART_ISR_TC Transmission Complete (used only + * for RS-485) + * USART_CR1_TXEIE USART_ISR_TXE Transmit Data + * Register Empty + * USART_CR1_PEIE USART_ISR_PE Parity Error + * + * USART_CR2_LBDIE USART_ISR_LBD Break Flag (not used) + * USART_CR3_EIE USART_ISR_FE Framing Error + * " " USART_ISR_NF Noise Error + * " " USART_ISR_ORE Overrun Error Detected + * USART_CR3_CTSIE USART_ISR_CTS CTS flag (not used) + * + * NOTE: + * Some of these status bits must be cleared by explicitly writing zero + * to the SR register: USART_ISR_CTS, USART_ISR_LBD. Note of those are + * currently being used. + */ + +#ifdef HAVE_RS485 + /* Transmission of whole buffer is over - TC is set, TXEIE is cleared. + * Note - this should be first, to have the most recent TC bit value + * from SR register - sending data affects TC, but without refresh we + * will not know that... + */ + + if ((priv->sr & USART_ISR_TC) != 0 && + (priv->ie & USART_CR1_TCIE) != 0 && + (priv->ie & USART_CR1_TXEIE) == 0) + { + stm32_gpiowrite(priv->rs485_dir_gpio, !priv->rs485_dir_polarity); + up_restoreusartint(priv, priv->ie & ~USART_CR1_TCIE); + } +#endif + + /* Handle incoming, receive bytes. */ + + if ((priv->sr & USART_ISR_RXNE) != 0 && + (priv->ie & USART_CR1_RXNEIE) != 0) + { + /* Received data ready... process incoming bytes. NOTE the check + * for RXNEIE: We cannot call uart_recvchards of RX interrupts are + * disabled. + */ + + uart_recvchars(&priv->dev); + handled = true; + } + + /* We may still have to read from the DR register to clear any pending + * error conditions. + */ + + else if ((priv->sr & + (USART_ISR_ORE | USART_ISR_NE | USART_ISR_FE)) != 0) + { + /* These errors are cleared by writing the corresponding bit to the + * interrupt clear register (ICR). + */ + + up_serialout(priv, STM32_USART_ICR_OFFSET, + (USART_ICR_NCF | USART_ICR_ORECF | USART_ICR_FECF)); + } + + /* Handle outgoing, transmit bytes */ + + if ((priv->sr & USART_ISR_TXE) != 0 && + (priv->ie & USART_CR1_TXEIE) != 0) + { + /* Transmit data register empty ... process outgoing bytes */ + + uart_xmitchars(&priv->dev); + handled = true; + } + } + + return OK; +} + +/**************************************************************************** + * Name: up_ioctl + * + * Description: + * All ioctl calls will be routed through this method + * + ****************************************************************************/ + +static int up_ioctl(struct file *filep, int cmd, unsigned long arg) +{ +#if defined(CONFIG_SERIAL_TERMIOS) || defined(CONFIG_SERIAL_TIOCSERGSTRUCT) \ + || defined(CONFIG_STM32_USART_SINGLEWIRE) \ + || defined(CONFIG_STM32_SERIALBRK_BSDCOMPAT) + struct inode *inode = filep->f_inode; + struct uart_dev_s *dev = inode->i_private; +#endif +#if defined(CONFIG_SERIAL_TERMIOS) \ + || defined(CONFIG_STM32_USART_SINGLEWIRE) \ + || defined(CONFIG_STM32_SERIALBRK_BSDCOMPAT) + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; +#endif + int ret = OK; + + switch (cmd) + { +#ifdef CONFIG_SERIAL_TIOCSERGSTRUCT + case TIOCSERGSTRUCT: + { + struct up_dev_s *user = (struct up_dev_s *)arg; + if (!user) + { + ret = -EINVAL; + } + else + { + memcpy(user, dev, sizeof(struct up_dev_s)); + } + } + break; +#endif + +#ifdef CONFIG_STM32_USART_SINGLEWIRE + case TIOCSSINGLEWIRE: + { + uint32_t cr1; + uint32_t cr1_ue; + irqstate_t flags; + + flags = enter_critical_section(); + + /* Get the original state of UE */ + + cr1 = up_serialin(priv, STM32_USART_CR1_OFFSET); + cr1_ue = cr1 & USART_CR1_UE; + cr1 &= ~USART_CR1_UE; + + /* Disable UE, HDSEL can only be written when UE=0 */ + + up_serialout(priv, STM32_USART_CR1_OFFSET, cr1); + + /* Change the TX port to be open-drain/push-pull and enable/disable + * half-duplex mode. + */ + + uint32_t cr = up_serialin(priv, STM32_USART_CR3_OFFSET); + + if ((arg & SER_SINGLEWIRE_ENABLED) != 0) + { + uint32_t gpio_val = (arg & SER_SINGLEWIRE_PUSHPULL) == + SER_SINGLEWIRE_PUSHPULL ? + GPIO_PUSHPULL : GPIO_OPENDRAIN; + gpio_val |= (arg & SER_SINGLEWIRE_PULL_MASK) == + SER_SINGLEWIRE_PULLUP ? + GPIO_PULLUP : GPIO_FLOAT; + gpio_val |= (arg & SER_SINGLEWIRE_PULL_MASK) == + SER_SINGLEWIRE_PULLDOWN ? + GPIO_PULLDOWN : GPIO_FLOAT; + stm32_configgpio((priv->tx_gpio & + ~(GPIO_PUPD_MASK | GPIO_OPENDRAIN)) | gpio_val); + cr |= USART_CR3_HDSEL; + } + else + { + stm32_configgpio((priv->tx_gpio & + ~(GPIO_PUPD_MASK | GPIO_OPENDRAIN)) | + GPIO_PUSHPULL); + cr &= ~USART_CR3_HDSEL; + } + + up_serialout(priv, STM32_USART_CR3_OFFSET, cr); + + /* Re-enable UE if appropriate */ + + up_serialout(priv, STM32_USART_CR1_OFFSET, cr1 | cr1_ue); + leave_critical_section(flags); + } + break; +#endif + +#ifdef CONFIG_SERIAL_TERMIOS + case TCGETS: + { + struct termios *termiosp = (struct termios *)arg; + + if (!termiosp) + { + ret = -EINVAL; + break; + } + + cfsetispeed(termiosp, priv->baud); + + /* Note that since we only support 8/9 bit modes and + * there is no way to report 9-bit mode, we always claim 8. + */ + + termiosp->c_cflag = + ((priv->parity != 0) ? PARENB : 0) | + ((priv->parity == 1) ? PARODD : 0) | + ((priv->stopbits2) ? CSTOPB : 0) | +#ifdef CONFIG_SERIAL_OFLOWCONTROL + ((priv->oflow) ? CCTS_OFLOW : 0) | +#endif +#ifdef CONFIG_SERIAL_IFLOWCONTROL + ((priv->iflow) ? CRTS_IFLOW : 0) | +#endif + CS8; + + /* TODO: CRTS_IFLOW, CCTS_OFLOW */ + } + break; + + case TCSETS: + { + struct termios *termiosp = (struct termios *)arg; + + if (!termiosp) + { + ret = -EINVAL; + break; + } + + /* Perform some sanity checks before accepting any changes */ + + if (((termiosp->c_cflag & CSIZE) != CS8) +#ifdef CONFIG_SERIAL_OFLOWCONTROL + || ((termiosp->c_cflag & CCTS_OFLOW) && (priv->cts_gpio == 0)) +#endif +#ifdef CONFIG_SERIAL_IFLOWCONTROL + || ((termiosp->c_cflag & CRTS_IFLOW) && (priv->rts_gpio == 0)) +#endif + ) + { + ret = -EINVAL; + break; + } + + if (termiosp->c_cflag & PARENB) + { + priv->parity = (termiosp->c_cflag & PARODD) ? 1 : 2; + } + else + { + priv->parity = 0; + } + + priv->stopbits2 = (termiosp->c_cflag & CSTOPB) != 0; +#ifdef CONFIG_SERIAL_OFLOWCONTROL + priv->oflow = (termiosp->c_cflag & CCTS_OFLOW) != 0; +#endif +#ifdef CONFIG_SERIAL_IFLOWCONTROL + priv->iflow = (termiosp->c_cflag & CRTS_IFLOW) != 0; +#endif + + /* Note that since there is no way to request 9-bit mode + * and no way to support 5/6/7-bit modes, we ignore them + * all here. + */ + + /* Note that only cfgetispeed is used because we have knowledge + * that only one speed is supported. + */ + + priv->baud = cfgetispeed(termiosp); + + /* Effect the changes immediately - note that we do not implement + * TCSADRAIN / TCSAFLUSH + */ + + up_set_format(dev); + } + break; +#endif /* CONFIG_SERIAL_TERMIOS */ + +#ifdef CONFIG_STM32_USART_BREAKS +# ifdef CONFIG_STM32_SERIALBRK_BSDCOMPAT + case TIOCSBRK: /* BSD compatibility: Turn break on, unconditionally */ + { + irqstate_t flags; + uint32_t tx_break; + + flags = enter_critical_section(); + + /* Disable any further tx activity */ + + priv->ie |= USART_CR1_IE_BREAK_INPROGRESS; + + up_txint(dev, false); + + /* Configure TX as a GPIO output pin and Send a break signal */ + + tx_break = GPIO_OUTPUT | (~(GPIO_MODE_MASK | GPIO_OUTPUT_SET) & + priv->tx_gpio); + stm32_configgpio(tx_break); + + leave_critical_section(flags); + } + break; + + case TIOCCBRK: /* BSD compatibility: Turn break off, unconditionally */ + { + irqstate_t flags; + + flags = enter_critical_section(); + + /* Configure TX back to U(S)ART */ + + stm32_configgpio(priv->tx_gpio); + + priv->ie &= ~USART_CR1_IE_BREAK_INPROGRESS; + + /* Enable further tx activity */ + + up_txint(dev, true); + + leave_critical_section(flags); + } + break; +# else + case TIOCSBRK: /* No BSD compatibility: Turn break on for M bit times */ + { + uint32_t cr1; + irqstate_t flags; + + flags = enter_critical_section(); + cr1 = up_serialin(priv, STM32_USART_CR1_OFFSET); + up_serialout(priv, STM32_USART_RQR_OFFSET, cr1 | USART_RQR_SBKRQ); + leave_critical_section(flags); + } + break; + + case TIOCCBRK: /* No BSD compatibility: HW does not support stopping a break */ + break; +# endif +#endif + + default: + ret = -ENOTTY; + break; + } + + return ret; +} + +/**************************************************************************** + * Name: up_receive + * + * Description: + * Called (usually) from the interrupt level to receive one + * character from the USART. Error bits associated with the + * receipt are provided in the return 'status'. + * + ****************************************************************************/ + +static int up_receive(struct uart_dev_s *dev, unsigned int *status) +{ + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; + uint32_t rdr; + + /* Get the Rx byte */ + + rdr = up_serialin(priv, STM32_USART_RDR_OFFSET); + + /* Get the Rx byte plux error information. Return those in status */ + + *status = priv->sr << 16 | rdr; + priv->sr = 0; + + /* Then return the actual received byte */ + + return rdr & 0xff; +} + +/**************************************************************************** + * Name: up_rxint + * + * Description: + * Call to enable or disable RX interrupts + * + ****************************************************************************/ + +static void up_rxint(struct uart_dev_s *dev, bool enable) +{ + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; + irqstate_t flags; + uint16_t ie; + + /* USART receive interrupts: + * + * Enable Status Meaning Usage + * ---------------- -------------- ----------------------- ---------- + * USART_CR1_IDLEIE USART_ISR_IDLE Idle Line Detected (not used) + * USART_CR1_RXNEIE USART_ISR_RXNE Received Data Ready + * to be Read + * " " USART_ISR_ORE Overrun Error Detected + * USART_CR1_PEIE USART_ISR_PE Parity Error + * + * USART_CR2_LBDIE USART_ISR_LBD Break Flag (not used) + * USART_CR3_EIE USART_ISR_FE Framing Error + * " " USART_ISR_NF Noise Error + * " " USART_ISR_ORE Overrun Error Detected + */ + + flags = enter_critical_section(); + ie = priv->ie; + if (enable) + { + /* Receive an interrupt when their is anything in the Rx data register + * (or an Rx timeout occurs). + */ + +#ifndef CONFIG_SUPPRESS_SERIAL_INTS +#ifdef CONFIG_USART_ERRINTS + ie |= (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR3_EIE); +#else + ie |= USART_CR1_RXNEIE; +#endif +#endif + } + else + { + ie &= ~(USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR3_EIE); + } + + /* Then set the new interrupt state */ + + up_restoreusartint(priv, ie); + leave_critical_section(flags); +} + +/**************************************************************************** + * Name: up_rxavailable + * + * Description: + * Return true if the receive register is not empty + * + ****************************************************************************/ + +static bool up_rxavailable(struct uart_dev_s *dev) +{ + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; + return ((up_serialin(priv, STM32_USART_ISR_OFFSET) & USART_ISR_RXNE) != 0); +} + +/**************************************************************************** + * Name: up_rxflowcontrol + * + * Description: + * Called when Rx buffer is full (or exceeds configured watermark levels + * if CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS is defined). + * Return true if UART activated RX flow control to block more incoming + * data + * + * Input Parameters: + * dev - UART device instance + * nbuffered - the number of characters currently buffered + * (if CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS is + * not defined the value will be 0 for an empty buffer or the + * defined buffer size for a full buffer) + * upper - true indicates the upper watermark was crossed where + * false indicates the lower watermark has been crossed + * + * Returned Value: + * true if RX flow control activated. + * + ****************************************************************************/ + +#ifdef CONFIG_SERIAL_IFLOWCONTROL +static bool up_rxflowcontrol(struct uart_dev_s *dev, + unsigned int nbuffered, bool upper) +{ + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; + +#if defined(CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS) && \ + defined(CONFIG_STM32_FLOWCONTROL_BROKEN) + if (priv->iflow && (priv->rts_gpio != 0)) + { + /* Assert/de-assert nRTS set it high resume/stop sending */ + + stm32_gpiowrite(priv->rts_gpio, upper); + + if (upper) + { + /* With heavy Rx traffic, RXNE might be set and data pending. + * Returning 'true' in such case would cause RXNE left unhandled + * and causing interrupt storm. Sending end might be also be slow + * to react on nRTS, and returning 'true' here would prevent + * processing that data. + * + * Therefore, return 'false' so input data is still being processed + * until sending end reacts on nRTS signal and stops sending more. + */ + + return false; + } + + return upper; + } + +#else + if (priv->iflow) + { + /* Is the RX buffer full? */ + + if (upper) + { + /* Disable Rx interrupt to prevent more data being from + * peripheral. When hardware RTS is enabled, this will + * prevent more data from coming in. + * + * This function is only called when UART recv buffer is full, + * that is: "dev->recv.head + 1 == dev->recv.tail". + * + * Logic in "uart_read" will automatically toggle Rx interrupts + * when buffer is read empty and thus we do not have to re- + * enable Rx interrupts. + */ + + uart_disablerxint(dev); + return true; + } + + /* No.. The RX buffer is empty */ + + else + { + /* We might leave Rx interrupt disabled if full recv buffer was + * read empty. Enable Rx interrupt to make sure that more input is + * received. + */ + + uart_enablerxint(dev); + } + } +#endif + + return false; +} +#endif + +/**************************************************************************** + * Name: up_send + * + * Description: + * This method will send one byte on the USART + * + ****************************************************************************/ + +static void up_send(struct uart_dev_s *dev, int ch) +{ + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; + +#ifdef HAVE_RS485 + if (priv->rs485_dir_gpio != 0) + { + stm32_gpiowrite(priv->rs485_dir_gpio, priv->rs485_dir_polarity); + } +#endif + + up_serialout(priv, STM32_USART_TDR_OFFSET, (uint32_t)ch); +} + +/**************************************************************************** + * Name: up_txint + * + * Description: + * Call to enable or disable TX interrupts + * + ****************************************************************************/ + +static void up_txint(struct uart_dev_s *dev, bool enable) +{ + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; + irqstate_t flags; + + /* USART transmit interrupts: + * + * Enable Status Meaning Usage + * ---------------- ------------- --------------------- ---------- + * USART_CR1_TCIE USART_ISR_TC Transmission Complete (used only + * for RS-485) + * USART_CR1_TXEIE USART_ISR_TXE Transmit Data + * Register Empty + * USART_CR3_CTSIE USART_ISR_CTS CTS flag (not used) + */ + + flags = enter_critical_section(); + if (enable) + { + /* Set to receive an interrupt when the TX data register is empty */ + +#ifndef CONFIG_SUPPRESS_SERIAL_INTS + uint16_t ie = priv->ie | USART_CR1_TXEIE; + + /* If RS-485 is supported on this U[S]ART, then also enable the + * transmission complete interrupt. + */ + +# ifdef HAVE_RS485 + if (priv->rs485_dir_gpio != 0) + { + ie |= USART_CR1_TCIE; + } +# endif + +# ifdef CONFIG_STM32_SERIALBRK_BSDCOMPAT + if (priv->ie & USART_CR1_IE_BREAK_INPROGRESS) + { + leave_critical_section(flags); + return; + } +# endif + + up_restoreusartint(priv, ie); + + /* Fake a TX interrupt here by just calling uart_xmitchars() with + * interrupts disabled (note this may recurse). + */ + + uart_xmitchars(dev); +#endif + } + else + { + /* Disable the TX interrupt */ + + up_restoreusartint(priv, priv->ie & ~USART_CR1_TXEIE); + } + + leave_critical_section(flags); +} + +/**************************************************************************** + * Name: up_txready + * + * Description: + * Return true if the transmit data register is empty + * + ****************************************************************************/ + +static bool up_txready(struct uart_dev_s *dev) +{ + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; + return ((up_serialin(priv, STM32_USART_ISR_OFFSET) & USART_ISR_TXE) != 0); +} + +/**************************************************************************** + * Name: up_pm_notify + * + * Description: + * Notify the driver of new power state. This callback is called after + * all drivers have had the opportunity to prepare for the new power state. + * + * Input Parameters: + * + * cb - Returned to the driver. The driver version of the callback + * structure may include additional, driver-specific state data at + * the end of the structure. + * + * pmstate - Identifies the new PM state + * + * Returned Value: + * None - The driver already agreed to transition to the low power + * consumption state when when it returned OK to the prepare() call. + * + * + ****************************************************************************/ + +#ifdef CONFIG_PM +static void up_pm_notify(struct pm_callback_s *cb, int domain, + enum pm_state_e pmstate) +{ + switch (pmstate) + { + case (PM_NORMAL): + { + /* Logic for PM_NORMAL goes here */ + } + break; + + case (PM_IDLE): + { + /* Logic for PM_IDLE goes here */ + } + break; + + case (PM_STANDBY): + { + /* Logic for PM_STANDBY goes here */ + } + break; + + case (PM_SLEEP): + { + /* Logic for PM_SLEEP goes here */ + } + break; + + default: + + /* Should not get here */ + + break; + } +} +#endif + +/**************************************************************************** + * Name: up_pm_prepare + * + * Description: + * Request the driver to prepare for a new power state. This is a warning + * that the system is about to enter into a new power state. The driver + * should begin whatever operations that may be required to enter power + * state. The driver may abort the state change mode by returning a + * non-zero value from the callback function. + * + * Input Parameters: + * + * cb - Returned to the driver. The driver version of the callback + * structure may include additional, driver-specific state data at + * the end of the structure. + * + * pmstate - Identifies the new PM state + * + * Returned Value: + * Zero - (OK) means the event was successfully processed and that the + * driver is prepared for the PM state change. + * + * Non-zero - means that the driver is not prepared to perform the tasks + * needed achieve this power setting and will cause the state + * change to be aborted. NOTE: The prepare() method will also + * be called when reverting from lower back to higher power + * consumption modes (say because another driver refused a + * lower power state change). Drivers are not permitted to + * return non-zero values when reverting back to higher power + * consumption modes! + * + ****************************************************************************/ + +#ifdef CONFIG_PM +static int up_pm_prepare(struct pm_callback_s *cb, int domain, + enum pm_state_e pmstate) +{ + /* Logic to prepare for a reduced power state goes here. */ + + return OK; +} +#endif +#endif /* HAVE_UART */ +#endif /* USE_SERIALDRIVER */ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +#ifdef USE_SERIALDRIVER + +/**************************************************************************** + * Name: stm32_serial_get_uart + * + * Description: + * Get serial driver structure for STM32 USART + * + ****************************************************************************/ + +uart_dev_t *stm32_serial_get_uart(int uart_num) +{ + int uart_idx = uart_num - 1; + + if (uart_idx < 0 || uart_idx >= STM32_NSERIAL || !g_uart_devs[uart_idx]) + { + return NULL; + } + + if (!g_uart_devs[uart_idx]->initialized) + { + return NULL; + } + + return &g_uart_devs[uart_idx]->dev; +} + +/**************************************************************************** + * Name: arm_earlyserialinit + * + * Description: + * Performs the low level USART initialization early in debug so that the + * serial console will be available during boot up. This must be called + * before arm_serialinit. + * + ****************************************************************************/ + +#ifdef USE_EARLYSERIALINIT +void arm_earlyserialinit(void) +{ +#ifdef HAVE_UART + unsigned i; + + /* Disable all USART interrupts */ + + for (i = 0; i < STM32_NSERIAL; i++) + { + if (g_uart_devs[i]) + { + up_disableusartint(g_uart_devs[i], NULL); + } + } + + /* Configure whichever one is the console */ + +#if CONSOLE_USART > 0 + up_setup(&g_uart_devs[CONSOLE_USART - 1]->dev); +#endif +#endif /* HAVE UART */ +} +#endif + +/**************************************************************************** + * Name: arm_serialinit + * + * Description: + * Register serial console and serial ports. This assumes + * that arm_earlyserialinit was called previously. + * + ****************************************************************************/ + +void arm_serialinit(void) +{ +#ifdef HAVE_UART + char devname[16]; + unsigned i; + unsigned minor = 0; +#ifdef CONFIG_PM + int ret; +#endif + + /* Register to receive power management callbacks */ + +#ifdef CONFIG_PM + ret = pm_register(&g_serialcb); + DEBUGASSERT(ret == OK); + UNUSED(ret); +#endif + + /* Register the console */ + +#if CONSOLE_USART > 0 + uart_register("/dev/console", &g_uart_devs[CONSOLE_USART - 1]->dev); + +#ifndef CONFIG_STM32_SERIAL_DISABLE_REORDERING + /* If not disabled, register the console UART to ttyS0 and exclude + * it from initializing it further down + */ + + uart_register("/dev/ttyS0", &g_uart_devs[CONSOLE_USART - 1]->dev); + minor = 1; +#endif + +#endif /* CONSOLE_USART > 0 */ + + /* Register all remaining USARTs */ + + strlcpy(devname, "/dev/ttySx", sizeof(devname)); + + for (i = 0; i < STM32_NSERIAL; i++) + { + /* Don't create a device for non-configured ports. */ + + if (g_uart_devs[i] == 0) + { + continue; + } + +#ifndef CONFIG_STM32_SERIAL_DISABLE_REORDERING + /* Don't create a device for the console - we did that above */ + + if (g_uart_devs[i]->dev.isconsole) + { + continue; + } +#endif + + /* Register USARTs as devices in increasing order */ + + devname[9] = '0' + minor++; + uart_register(devname, &g_uart_devs[i]->dev); + } +#endif /* HAVE UART */ +} + +/**************************************************************************** + * Name: up_putc + * + * Description: + * Provide priority, low-level access to support OS debug writes + * + ****************************************************************************/ + +void up_putc(int ch) +{ +#if CONSOLE_USART > 0 + struct up_dev_s *priv = g_uart_devs[CONSOLE_USART - 1]; + uint16_t ie; + + up_disableusartint(priv, &ie); + arm_lowputc(ch); + up_restoreusartint(priv, ie); + +#endif +} + +#else /* USE_SERIALDRIVER */ + +/**************************************************************************** + * Name: up_putc + * + * Description: + * Provide priority, low-level access to support OS debug writes + * + ****************************************************************************/ + +void up_putc(int ch) +{ +#if CONSOLE_USART > 0 + arm_lowputc(ch); +#endif +} + +#endif /* USE_SERIALDRIVER */ diff --git a/arch/arm/src/common/stm32/stm32_serial_m3m4_v1v2v3v4.c b/arch/arm/src/common/stm32/stm32_serial_m3m4_v1v2v3v4.c new file mode 100644 index 0000000000000..c5b3f861d109a --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_serial_m3m4_v1v2v3v4.c @@ -0,0 +1,3765 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_serial_m3m4_v1v2v3v4.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#ifdef CONFIG_SERIAL_TERMIOS +# include +#endif + +#include + +#include "chip.h" +#include "stm32_uart.h" +#include "stm32_dma.h" +#include "stm32_rcc.h" +#include "arm_internal.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Some sanity checks *******************************************************/ + +/* DMA configuration */ + +/* If DMA is enabled on any USART, then very that other pre-requisites + * have also been selected. + */ + +#ifdef SERIAL_HAVE_RXDMA + +# if defined(CONFIG_STM32_HAVE_IP_DMA_V2) +/* Verify that DMA has been enabled and the DMA channel has been defined. + */ + +# if defined(CONFIG_USART1_RXDMA) || defined(CONFIG_USART6_RXDMA) +# ifndef CONFIG_STM32_DMA2 +# error STM32 USART1/6 receive DMA requires CONFIG_STM32_DMA2 +# endif +# endif + +# if defined(CONFIG_USART2_RXDMA) || defined(CONFIG_USART3_RXDMA) || \ + defined(CONFIG_UART4_RXDMA) || defined(CONFIG_UART5_RXDMA) || \ + defined(CONFIG_UART7_RXDMA) || defined(CONFIG_UART8_RXDMA) +# ifndef CONFIG_STM32_DMA1 +# error STM32 USART2/3/4/5/7/8 receive DMA requires CONFIG_STM32_DMA1 +# endif +# endif + +/* Currently RS-485 support cannot be enabled when RXDMA is in use due to + * lack of testing - RS-485 support was developed on STM32F1x + */ + +# if (defined(CONFIG_USART1_RXDMA) && defined(CONFIG_USART1_RS485)) || \ + (defined(CONFIG_USART2_RXDMA) && defined(CONFIG_USART2_RS485)) || \ + (defined(CONFIG_USART3_RXDMA) && defined(CONFIG_USART3_RS485)) || \ + (defined(CONFIG_UART4_RXDMA) && defined(CONFIG_UART4_RS485)) || \ + (defined(CONFIG_UART5_RXDMA) && defined(CONFIG_UART5_RS485)) || \ + (defined(CONFIG_USART6_RXDMA) && defined(CONFIG_USART6_RS485)) || \ + (defined(CONFIG_UART7_RXDMA) && defined(CONFIG_UART7_RS485)) || \ + (defined(CONFIG_UART8_RXDMA) && defined(CONFIG_UART8_RS485)) +# error "RXDMA and RS-485 cannot be enabled at the same time for the same U[S]ART" +# endif + +/* For the F4, there are alternate DMA channels for USART1 and 6. + * Logic in the board.h file make the DMA channel selection by defining + * the following in the board.h file. + */ + +# if defined(CONFIG_USART1_RXDMA) && !defined(DMAMAP_USART1_RX) +# error "USART1 DMA channel not defined (DMAMAP_USART1_RX)" +# endif + +# if defined(CONFIG_USART2_RXDMA) && !defined(DMAMAP_USART2_RX) +# error "USART2 DMA channel not defined (DMAMAP_USART2_RX)" +# endif + +# if defined(CONFIG_USART3_RXDMA) && !defined(DMAMAP_USART3_RX) +# error "USART3 DMA channel not defined (DMAMAP_USART3_RX)" +# endif + +# if defined(CONFIG_UART4_RXDMA) && !defined(DMAMAP_UART4_RX) +# error "UART4 DMA channel not defined (DMAMAP_UART4_RX)" +# endif + +# if defined(CONFIG_UART5_RXDMA) && !defined(DMAMAP_UART5_RX) +# error "UART5 DMA channel not defined (DMAMAP_UART5_RX)" +# endif + +# if defined(CONFIG_USART6_RXDMA) && !defined(DMAMAP_USART6_RX) +# error "USART6 DMA channel not defined (DMAMAP_USART6_RX)" +# endif + +# if defined(CONFIG_UART7_RXDMA) && !defined(DMAMAP_UART7_RX) +# error "UART7 DMA channel not defined (DMAMAP_UART7_RX)" +# endif + +# if defined(CONFIG_UART8_RXDMA) && !defined(DMAMAP_UART8_RX) +# error "UART8 DMA channel not defined (DMAMAP_UART8_RX)" +# endif + +# elif defined(CONFIG_STM32_HAVE_IP_DMA_V1) + +# if defined(CONFIG_USART1_RXDMA) || defined(CONFIG_USART2_RXDMA) || \ + defined(CONFIG_USART3_RXDMA) || defined(CONFIG_LPUART1_RXDMA) +# ifndef CONFIG_STM32_DMA1 +# error STM32 LPUART1 / USART1/2/3 receive DMA requires CONFIG_STM32_DMA1 +# endif +# endif + +# if defined(CONFIG_UART4_RXDMA) || defined(CONFIG_UART5_RXDMA) +# ifndef CONFIG_STM32_DMA2 +# error STM32 UART4/5 receive DMA requires CONFIG_STM32_DMA2 +# endif +# endif + +/* There are no optional DMA channel assignments for the F1 */ + +# define DMAMAP_USART1_RX DMACHAN_USART1_RX +# define DMAMAP_USART2_RX DMACHAN_USART2_RX +# define DMAMAP_USART3_RX DMACHAN_USART3_RX +# define DMAMAP_UART4_RX DMACHAN_UART4_RX +# define DMAMAP_UART5_RX DMACHAN_UART5_RX +# if defined(CONFIG_LPUART1_RXDMA) && defined(CONFIG_STM32_STM32G4XXX) +# define DMAMAP_LPUART1_RX DMAMAP_DMA12_LPUART1RX_0 +# endif + +# endif + +/* The DMA buffer size when using RX DMA to emulate a FIFO. + * + * When streaming data, the generic serial layer will be called + * every time the FIFO receives half this number of bytes. + */ +# if !defined(CONFIG_STM32_SERIAL_RXDMA_BUFFER_SIZE) +# define CONFIG_STM32_SERIAL_RXDMA_BUFFER_SIZE 32 +# endif +# define RXDMA_MUTIPLE 4 +# define RXDMA_MUTIPLE_MASK (RXDMA_MUTIPLE -1) +# define RXDMA_BUFFER_SIZE ((CONFIG_STM32_SERIAL_RXDMA_BUFFER_SIZE \ + + RXDMA_MUTIPLE_MASK) \ + & ~RXDMA_MUTIPLE_MASK) + +/* DMA priority */ + +# ifndef CONFIG_USART_RXDMAPRIO +# if defined(CONFIG_STM32_HAVE_IP_DMA_V1) +# define CONFIG_USART_RXDMAPRIO DMA_CCR_PRIMED +# elif defined(CONFIG_STM32_HAVE_IP_DMA_V2) +# define CONFIG_USART_RXDMAPRIO DMA_SCR_PRIMED +# else +# error "Unknown STM32 DMA" +# endif +# endif +# if defined(CONFIG_STM32_HAVE_IP_DMA_V1) +# if (CONFIG_USART_RXDMAPRIO & ~DMA_CCR_PL_MASK) != 0 +# error "Illegal value for CONFIG_USART_RXDMAPRIO" +# endif +# elif defined(CONFIG_STM32_HAVE_IP_DMA_V2) +# if (CONFIG_USART_RXDMAPRIO & ~DMA_SCR_PL_MASK) != 0 +# error "Illegal value for CONFIG_USART_RXDMAPRIO" +# endif +# else +# error "Unknown STM32 DMA" +# endif + +/* DMA control word */ + +# if defined(CONFIG_STM32_HAVE_IP_DMA_V2) +# define SERIAL_RXDMA_CONTROL_WORD \ + (DMA_SCR_DIR_P2M | \ + DMA_SCR_CIRC | \ + DMA_SCR_MINC | \ + DMA_SCR_PSIZE_8BITS | \ + DMA_SCR_MSIZE_8BITS | \ + CONFIG_USART_RXDMAPRIO | \ + DMA_SCR_PBURST_SINGLE | \ + DMA_SCR_MBURST_SINGLE) +# else +# define SERIAL_RXDMA_CONTROL_WORD \ + (DMA_CCR_CIRC | \ + DMA_CCR_MINC | \ + DMA_CCR_PSIZE_8BITS | \ + DMA_CCR_MSIZE_8BITS | \ + CONFIG_USART_RXDMAPRIO) +# endif + +#endif /* SERIAL_HAVE_RXDMA */ + +#ifdef SERIAL_HAVE_TXDMA + +# if defined(CONFIG_STM32_HAVE_IP_DMA_V2) + +/* Verify that DMA has been enabled and the DMA channel has been defined. + */ + +# if defined(CONFIG_USART1_TXDMA) || defined(CONFIG_USART6_TXDMA) +# ifndef CONFIG_STM32_DMA2 +# error STM32 USART1/6 receive DMA requires CONFIG_STM32_DMA2 +# endif +# endif + +# if defined(CONFIG_USART2_TXDMA) || defined(CONFIG_USART3_TXDMA) || \ + defined(CONFIG_UART4_TXDMA) || defined(CONFIG_UART5_TXDMA) || \ + defined(CONFIG_UART7_TXDMA) || defined(CONFIG_UART8_TXDMA) +# ifndef CONFIG_STM32_DMA1 +# error STM32 USART2/3/4/5/7/8 receive DMA requires CONFIG_STM32_DMA1 +# endif +# endif + +/* Currently RS-485 support cannot be enabled when TXDMA is in use due to + * lack of testing - RS-485 support was developed on STM32F1x + */ + +# if (defined(CONFIG_USART1_TXDMA) && defined(CONFIG_USART1_RS485)) || \ + (defined(CONFIG_USART2_TXDMA) && defined(CONFIG_USART2_RS485)) || \ + (defined(CONFIG_USART3_TXDMA) && defined(CONFIG_USART3_RS485)) || \ + (defined(CONFIG_UART4_TXDMA) && defined(CONFIG_UART4_RS485)) || \ + (defined(CONFIG_UART5_TXDMA) && defined(CONFIG_UART5_RS485)) || \ + (defined(CONFIG_USART6_TXDMA) && defined(CONFIG_USART6_RS485)) || \ + (defined(CONFIG_UART7_TXDMA) && defined(CONFIG_UART7_RS485)) || \ + (defined(CONFIG_UART8_TXDMA) && defined(CONFIG_UART8_RS485)) +# error "TXDMA and RS-485 cannot be enabled at the same time for the same U[S]ART" +# endif + +# if defined(CONFIG_USART1_TXDMA) && !defined(DMAMAP_USART1_TX) +# error "USART1 DMA channel not defined (DMAMAP_USART1_TX)" +# endif + +# if defined(CONFIG_USART2_TXDMA) && !defined(DMAMAP_USART2_TX) +# error "USART2 DMA channel not defined (DMAMAP_USART2_TX)" +# endif + +# if defined(CONFIG_USART3_TXDMA) && !defined(DMAMAP_USART3_TX) +# error "USART3 DMA channel not defined (DMAMAP_USART3_TX)" +# endif + +# if defined(CONFIG_UART4_TXDMA) && !defined(DMAMAP_UART4_TX) +# error "UART4 DMA channel not defined (DMAMAP_UART4_TX)" +# endif + +# if defined(CONFIG_UART5_TXDMA) && !defined(DMAMAP_UART5_TX) +# error "UART5 DMA channel not defined (DMAMAP_UART5_TX)" +# endif + +# if defined(CONFIG_USART6_TXDMA) && !defined(DMAMAP_USART6_TX) +# error "USART6 DMA channel not defined (DMAMAP_USART6_TX)" +# endif + +# if defined(CONFIG_UART7_TXDMA) && !defined(DMAMAP_UART7_TX) +# error "UART7 DMA channel not defined (DMAMAP_UART7_TX)" +# endif + +# if defined(CONFIG_UART8_TXDMA) && !defined(DMAMAP_UART8_TX) +# error "UART8 DMA channel not defined (DMAMAP_UART8_TX)" +# endif + +# elif defined(CONFIG_STM32_HAVE_IP_DMA_V1) + +# if defined(CONFIG_USART1_TXDMA) || defined(CONFIG_USART2_TXDMA) || \ + defined(CONFIG_USART3_TXDMA) || defined(CONFIG_LPUART1_TXDMA) +# ifndef CONFIG_STM32_DMA1 +# error STM32 USART1/2/3 receive DMA requires CONFIG_STM32_DMA1 +# endif +# endif + +# if defined(CONFIG_UART4_TXDMA) || defined(CONFIG_UART5_TXDMA) +# ifndef CONFIG_STM32_DMA2 +# error STM32 UART4/5 receive DMA requires CONFIG_STM32_DMA2 +# endif +# endif + +# define DMAMAP_USART1_TX DMACHAN_USART1_TX +# define DMAMAP_USART2_TX DMACHAN_USART2_TX +# define DMAMAP_USART3_TX DMACHAN_USART3_TX +# define DMAMAP_UART4_TX DMACHAN_UART4_TX +# define DMAMAP_UART5_TX DMACHAN_UART5_TX +# if defined(CONFIG_LPUART1_TXDMA) && defined(CONFIG_STM32_STM32G4XXX) +# define DMAMAP_LPUART1_TX DMAMAP_DMA12_LPUART1TX_0 +# endif + +# endif + +/* DMA priority */ + +# ifndef CONFIG_USART_TXDMAPRIO +# if defined(CONFIG_STM32_HAVE_IP_DMA_V1) +# define CONFIG_USART_TXDMAPRIO DMA_CCR_PRIMED +# elif defined(CONFIG_STM32_HAVE_IP_DMA_V2) +# define CONFIG_USART_TXDMAPRIO DMA_SCR_PRIMED +# else +# error "Unknown STM32 DMA" +# endif +# endif +# if defined(CONFIG_STM32_HAVE_IP_DMA_V1) +# if (CONFIG_USART_TXDMAPRIO & ~DMA_CCR_PL_MASK) != 0 +# error "Illegal value for CONFIG_USART_TXDMAPRIO" +# endif +# elif defined(CONFIG_STM32_HAVE_IP_DMA_V2) +# if (CONFIG_USART_TXDMAPRIO & ~DMA_SCR_PL_MASK) != 0 +# error "Illegal value for CONFIG_USART_TXDMAPRIO" +# endif +# else +# error "Unknown STM32 DMA" +# endif + +/* DMA control word */ + +# if defined(CONFIG_STM32_HAVE_IP_DMA_V2) +# define SERIAL_TXDMA_CONTROL_WORD \ + (DMA_SCR_DIR_M2P | \ + DMA_SCR_MINC | \ + DMA_SCR_PSIZE_8BITS | \ + DMA_SCR_MSIZE_8BITS | \ + CONFIG_USART_TXDMAPRIO | \ + DMA_SCR_PBURST_SINGLE | \ + DMA_SCR_MBURST_SINGLE) +# elif defined(CONFIG_STM32_HAVE_IP_DMA_V1) +# define SERIAL_TXDMA_CONTROL_WORD \ + (DMA_CCR_DIR | \ + DMA_CCR_MINC | \ + DMA_CCR_PSIZE_8BITS | \ + DMA_CCR_MSIZE_8BITS | \ + CONFIG_USART_TXDMAPRIO) +# else +# error "Unknown STM32 DMA" +# endif + +/* DMA ISR status */ + +# if defined(CONFIG_STM32_HAVE_IP_DMA_V1) +# define DMA_ISR_HTIF_BIT DMA_CHAN_HTIF_BIT +# define DMA_ISR_TCIF_BIT DMA_CHAN_TCIF_BIT +# elif defined(CONFIG_STM32_HAVE_IP_DMA_V2) +# define DMA_ISR_HTIF_BIT DMA_STREAM_HTIF_BIT +# define DMA_ISR_TCIF_BIT DMA_STREAM_TCIF_BIT +# else +# error "Unknown STM32 DMA" +# endif + +#endif /* SERIAL_HAVE_TXDMA */ + +/* Power management definitions */ + +#if defined(CONFIG_PM) && !defined(CONFIG_STM32_PM_SERIAL_ACTIVITY) +# define CONFIG_STM32_PM_SERIAL_ACTIVITY 10 +#endif + +/* Since RX DMA or TX DMA or both may be enabled for a given U[S]ART. + * We need runtime detection in up_dma_setup and up_dma_shutdown + * We use the default struct default init value of 0 which maps to + * STM32_DMA_MAP(DMA1,DMA_STREAM0,DMA_CHAN0) which is not a U[S]ART. + */ + +#define INVALID_SERIAL_DMA_CHANNEL 0 + +/* Keep track if a Break was set + * + * Note: + * + * 1) This value is set in the priv->ie but never written to the control + * register. It must not collide with USART_CR1_USED_INTS or USART_CR3_EIE + * 2) USART_CR3_EIE is also carried in the up_dev_s ie member. + * + * See up_restoreusartint where the masking is done. + */ + +#ifdef CONFIG_STM32_SERIALBRK_BSDCOMPAT +# define USART_CR1_IE_BREAK_INPROGRESS_SHFTS 15 +# define USART_CR1_IE_BREAK_INPROGRESS (1 << USART_CR1_IE_BREAK_INPROGRESS_SHFTS) +#endif + +#ifdef USE_SERIALDRIVER +#ifdef HAVE_SERIALDRIVER + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +struct up_dev_s +{ + struct uart_dev_s dev; /* Generic UART device */ + uint16_t ie; /* Saved interrupt mask bits value */ + uint16_t sr; /* Saved status bits */ + + /* Has been initialized and HW is setup. */ + + bool initialized; + + /* If termios are supported, then the following fields may vary at + * runtime. + */ + +#ifdef CONFIG_SERIAL_TERMIOS + uint8_t parity; /* 0=none, 1=odd, 2=even */ + uint8_t bits; /* Number of bits (7 or 8) */ + bool stopbits2; /* True: Configure with 2 stop bits instead of 1 */ +#ifdef CONFIG_SERIAL_IFLOWCONTROL + bool iflow; /* input flow control (RTS) enabled */ +#endif +#ifdef CONFIG_SERIAL_OFLOWCONTROL + bool oflow; /* output flow control (CTS) enabled */ +#endif + uint32_t baud; /* Configured baud */ +#else + const uint8_t parity; /* 0=none, 1=odd, 2=even */ + const uint8_t bits; /* Number of bits (7 or 8) */ + const bool stopbits2; /* True: Configure with 2 stop bits instead of 1 */ +#ifdef CONFIG_SERIAL_IFLOWCONTROL + const bool iflow; /* input flow control (RTS) enabled */ +#endif +#ifdef CONFIG_SERIAL_OFLOWCONTROL + const bool oflow; /* output flow control (CTS) enabled */ +#endif + const uint32_t baud; /* Configured baud */ +#endif + + const uint8_t irq; /* IRQ associated with this USART */ + const uint32_t apbclock; /* PCLK 1 or 2 frequency */ + const uint32_t usartbase; /* Base address of USART registers */ + const uint32_t tx_gpio; /* U[S]ART TX GPIO pin configuration */ + const uint32_t rx_gpio; /* U[S]ART RX GPIO pin configuration */ +#ifdef CONFIG_SERIAL_IFLOWCONTROL + const uint32_t rts_gpio; /* U[S]ART RTS GPIO pin configuration */ +#endif +#ifdef CONFIG_SERIAL_OFLOWCONTROL + const uint32_t cts_gpio; /* U[S]ART CTS GPIO pin configuration */ +#endif +#ifdef CONFIG_SERIAL_TIOCGICOUNT + struct serial_icounter_s icount; /* U[S]ART error report */ +#endif + + /* TX DMA state */ + +#ifdef SERIAL_HAVE_TXDMA + const unsigned int txdma_channel; /* DMA channel assigned */ + DMA_HANDLE txdma; /* currently-open transmit DMA stream */ +#endif + +#ifdef SERIAL_HAVE_RXDMA + const unsigned int rxdma_channel; /* DMA channel assigned */ +#endif + + /* RX DMA state */ + +#ifdef SERIAL_HAVE_RXDMA + DMA_HANDLE rxdma; /* currently-open receive DMA stream */ + bool rxenable; /* DMA-based reception en/disable */ + uint32_t rxdmanext; /* Next byte in the DMA buffer to be read */ + char *const rxfifo; /* Receive DMA buffer */ +#endif + +#ifdef HAVE_RS485 + const uint32_t rs485_dir_gpio; /* U[S]ART RS-485 DIR GPIO pin cfg */ + const bool rs485_dir_polarity; /* U[S]ART RS-485 DIR TXEN polarity */ +#endif + const bool islpuart; /* Is this device a Low Power UART? */ + spinlock_t lock; /* Spinlock */ +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +static void up_set_format(struct uart_dev_s *dev); +static int up_setup(struct uart_dev_s *dev); +static void up_shutdown(struct uart_dev_s *dev); +static int up_attach(struct uart_dev_s *dev); +static void up_detach(struct uart_dev_s *dev); +static int up_interrupt(int irq, void *context, void *arg); +static int up_ioctl(struct file *filep, int cmd, unsigned long arg); +#if defined(SERIAL_HAVE_TXDMA_OPS) || defined(SERIAL_HAVE_NODMA_OPS) +static int up_receive(struct uart_dev_s *dev, unsigned int *status); +static void up_rxint(struct uart_dev_s *dev, bool enable); +static bool up_rxavailable(struct uart_dev_s *dev); +#endif +#ifdef CONFIG_SERIAL_IFLOWCONTROL +static bool up_rxflowcontrol(struct uart_dev_s *dev, unsigned int nbuffered, + bool upper); +#endif +static void up_send(struct uart_dev_s *dev, int ch); +#if defined(SERIAL_HAVE_RXDMA_OPS) || defined(SERIAL_HAVE_NODMA_OPS) || \ + defined(CONFIG_STM32_SERIALBRK_BSDCOMPAT) +static void up_txint(struct uart_dev_s *dev, bool enable); +#endif +static bool up_txready(struct uart_dev_s *dev); + +#ifdef SERIAL_HAVE_TXDMA +static void up_dma_send(struct uart_dev_s *dev); +static void up_dma_txint(struct uart_dev_s *dev, bool enable); +static void up_dma_txavailable(struct uart_dev_s *dev); +static void up_dma_txcallback(DMA_HANDLE handle, uint8_t status, void *arg); +#endif + +#if defined(SERIAL_HAVE_RXDMA) || defined(SERIAL_HAVE_TXDMA) +static int up_dma_setup(struct uart_dev_s *dev); +static void up_dma_shutdown(struct uart_dev_s *dev); +#endif + +#ifdef SERIAL_HAVE_RXDMA +static int up_dma_receive(struct uart_dev_s *dev, unsigned int *status); +static void up_dma_rxint(struct uart_dev_s *dev, bool enable); +static bool up_dma_rxavailable(struct uart_dev_s *dev); + +static void up_dma_rxcallback(DMA_HANDLE handle, uint8_t status, void *arg); +#endif + +#ifdef CONFIG_PM +static void up_pm_notify(struct pm_callback_s *cb, int dowmin, + enum pm_state_e pmstate); +static int up_pm_prepare(struct pm_callback_s *cb, int domain, + enum pm_state_e pmstate); +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#ifdef SERIAL_HAVE_NODMA_OPS +static const struct uart_ops_s g_uart_ops = +{ + .setup = up_setup, + .shutdown = up_shutdown, + .attach = up_attach, + .detach = up_detach, + .ioctl = up_ioctl, + .receive = up_receive, + .rxint = up_rxint, + .rxavailable = up_rxavailable, +#ifdef CONFIG_SERIAL_IFLOWCONTROL + .rxflowcontrol = up_rxflowcontrol, +#endif + .send = up_send, + .txint = up_txint, + .txready = up_txready, + .txempty = up_txready, +}; +#endif + +#ifdef SERIAL_HAVE_RXTXDMA_OPS +static const struct uart_ops_s g_uart_rxtxdma_ops = +{ + .setup = up_dma_setup, + .shutdown = up_dma_shutdown, + .attach = up_attach, + .detach = up_detach, + .ioctl = up_ioctl, + .receive = up_dma_receive, + .rxint = up_dma_rxint, + .rxavailable = up_dma_rxavailable, +#ifdef CONFIG_SERIAL_IFLOWCONTROL + .rxflowcontrol = up_rxflowcontrol, +#endif + .send = up_send, + .txint = up_dma_txint, + .txready = up_txready, + .txempty = up_txready, + .dmatxavail = up_dma_txavailable, + .dmasend = up_dma_send, +}; +#endif + +#ifdef SERIAL_HAVE_RXDMA_OPS +static const struct uart_ops_s g_uart_rxdma_ops = +{ + .setup = up_dma_setup, + .shutdown = up_dma_shutdown, + .attach = up_attach, + .detach = up_detach, + .ioctl = up_ioctl, + .receive = up_dma_receive, + .rxint = up_dma_rxint, + .rxavailable = up_dma_rxavailable, +#ifdef CONFIG_SERIAL_IFLOWCONTROL + .rxflowcontrol = up_rxflowcontrol, +#endif + .send = up_send, + .txint = up_txint, + .txready = up_txready, + .txempty = up_txready, +}; +#endif + +#ifdef SERIAL_HAVE_TXDMA_OPS +static const struct uart_ops_s g_uart_txdma_ops = +{ + .setup = up_dma_setup, + .shutdown = up_dma_shutdown, + .attach = up_attach, + .detach = up_detach, + .ioctl = up_ioctl, + .receive = up_receive, + .rxint = up_rxint, + .rxavailable = up_rxavailable, +#ifdef CONFIG_SERIAL_IFLOWCONTROL + .rxflowcontrol = up_rxflowcontrol, +#endif + .send = up_send, + .txint = up_dma_txint, + .txready = up_txready, + .txempty = up_txready, + .dmatxavail = up_dma_txavailable, + .dmasend = up_dma_send, +}; +#endif + +/* I/O buffers */ + +#ifdef CONFIG_STM32_USART1_SERIALDRIVER +static char g_usart1rxbuffer[CONFIG_USART1_RXBUFSIZE]; +static char g_usart1txbuffer[CONFIG_USART1_TXBUFSIZE]; +# ifdef CONFIG_USART1_RXDMA +static char g_usart1rxfifo[RXDMA_BUFFER_SIZE]; +# endif +#endif + +#ifdef CONFIG_STM32_USART2_SERIALDRIVER +static char g_usart2rxbuffer[CONFIG_USART2_RXBUFSIZE]; +static char g_usart2txbuffer[CONFIG_USART2_TXBUFSIZE]; +# ifdef CONFIG_USART2_RXDMA +static char g_usart2rxfifo[RXDMA_BUFFER_SIZE]; +# endif +#endif + +#ifdef CONFIG_STM32_USART3_SERIALDRIVER +static char g_usart3rxbuffer[CONFIG_USART3_RXBUFSIZE]; +static char g_usart3txbuffer[CONFIG_USART3_TXBUFSIZE]; +# ifdef CONFIG_USART3_RXDMA +static char g_usart3rxfifo[RXDMA_BUFFER_SIZE]; +# endif +#endif + +#ifdef CONFIG_STM32_UART4_SERIALDRIVER +static char g_uart4rxbuffer[CONFIG_UART4_RXBUFSIZE]; +static char g_uart4txbuffer[CONFIG_UART4_TXBUFSIZE]; +# ifdef CONFIG_UART4_RXDMA +static char g_uart4rxfifo[RXDMA_BUFFER_SIZE]; +# endif +#endif + +#ifdef CONFIG_STM32_UART5_SERIALDRIVER +static char g_uart5rxbuffer[CONFIG_UART5_RXBUFSIZE]; +static char g_uart5txbuffer[CONFIG_UART5_TXBUFSIZE]; +# ifdef CONFIG_UART5_RXDMA +static char g_uart5rxfifo[RXDMA_BUFFER_SIZE]; +# endif +#endif + +#ifdef CONFIG_STM32_USART6_SERIALDRIVER +static char g_usart6rxbuffer[CONFIG_USART6_RXBUFSIZE]; +static char g_usart6txbuffer[CONFIG_USART6_TXBUFSIZE]; +# ifdef CONFIG_USART6_RXDMA +static char g_usart6rxfifo[RXDMA_BUFFER_SIZE]; +# endif +#endif + +#ifdef CONFIG_STM32_UART7_SERIALDRIVER +static char g_uart7rxbuffer[CONFIG_UART7_RXBUFSIZE]; +static char g_uart7txbuffer[CONFIG_UART7_TXBUFSIZE]; +# ifdef CONFIG_UART7_RXDMA +static char g_uart7rxfifo[RXDMA_BUFFER_SIZE]; +# endif +#endif + +#ifdef CONFIG_STM32_UART8_SERIALDRIVER +static char g_uart8rxbuffer[CONFIG_UART8_RXBUFSIZE]; +static char g_uart8txbuffer[CONFIG_UART8_TXBUFSIZE]; +# ifdef CONFIG_UART8_RXDMA +static char g_uart8rxfifo[RXDMA_BUFFER_SIZE]; +# endif +#endif + +#ifdef CONFIG_STM32_LPUART1_SERIALDRIVER +static char g_lpuart1rxbuffer[CONFIG_LPUART1_RXBUFSIZE]; +static char g_lpuart1txbuffer[CONFIG_LPUART1_TXBUFSIZE]; +# ifdef CONFIG_LPUART1_RXDMA +static char g_lpuart1rxfifo[RXDMA_BUFFER_SIZE]; +# endif +#endif + +/* This describes the state of the STM32 USART1 ports. */ + +#ifdef CONFIG_STM32_USART1_SERIALDRIVER +static struct up_dev_s g_usart1priv = +{ + .dev = + { +# if CONSOLE_UART == 1 + .isconsole = true, +# endif + .recv = + { + .size = CONFIG_USART1_RXBUFSIZE, + .buffer = g_usart1rxbuffer, + }, + .xmit = + { + .size = CONFIG_USART1_TXBUFSIZE, + .buffer = g_usart1txbuffer, + }, +# if defined(CONFIG_USART1_RXDMA) && defined(CONFIG_USART1_TXDMA) + .ops = &g_uart_rxtxdma_ops, +# elif defined(CONFIG_USART1_RXDMA) && !defined(CONFIG_USART1_TXDMA) + .ops = &g_uart_rxdma_ops, +# elif !defined(CONFIG_USART1_RXDMA) && defined(CONFIG_USART1_TXDMA) + .ops = &g_uart_txdma_ops, +# else + .ops = &g_uart_ops, +# endif + .priv = &g_usart1priv, + }, + + .islpuart = false, + .irq = STM32_IRQ_USART1, + .parity = CONFIG_USART1_PARITY, + .bits = CONFIG_USART1_BITS, + .stopbits2 = CONFIG_USART1_2STOP, + .baud = CONFIG_USART1_BAUD, +# if defined(CONFIG_STM32_STM32F33XX) || defined(CONFIG_STM32_STM32F302) + .apbclock = STM32_PCLK1_FREQUENCY, /* Errata 2.5.1 */ +# else + .apbclock = STM32_PCLK2_FREQUENCY, +# endif + .usartbase = STM32_USART1_BASE, + .tx_gpio = GPIO_USART1_TX, + .rx_gpio = GPIO_USART1_RX, +# if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_USART1_OFLOWCONTROL) + .oflow = true, + .cts_gpio = GPIO_USART1_CTS, +# endif +# if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_USART1_IFLOWCONTROL) + .iflow = true, + .rts_gpio = GPIO_USART1_RTS, +# endif +# ifdef CONFIG_USART1_TXDMA + .txdma_channel = DMAMAP_USART1_TX, +# endif +# ifdef CONFIG_USART1_RXDMA + .rxdma_channel = DMAMAP_USART1_RX, + .rxfifo = g_usart1rxfifo, +# endif + +# ifdef CONFIG_USART1_RS485 + .rs485_dir_gpio = GPIO_USART1_RS485_DIR, +# if (CONFIG_USART1_RS485_DIR_POLARITY == 0) + .rs485_dir_polarity = false, +# else + .rs485_dir_polarity = true, +# endif +# endif + .lock = SP_UNLOCKED, +}; +#endif + +/* This describes the state of the STM32 USART2 port. */ + +#ifdef CONFIG_STM32_USART2_SERIALDRIVER +static struct up_dev_s g_usart2priv = +{ + .dev = + { +# if CONSOLE_UART == 2 + .isconsole = true, +# endif + .recv = + { + .size = CONFIG_USART2_RXBUFSIZE, + .buffer = g_usart2rxbuffer, + }, + .xmit = + { + .size = CONFIG_USART2_TXBUFSIZE, + .buffer = g_usart2txbuffer, + }, +# if defined(CONFIG_USART2_RXDMA) && defined(CONFIG_USART2_TXDMA) + .ops = &g_uart_rxtxdma_ops, +# elif defined(CONFIG_USART2_RXDMA) && !defined(CONFIG_USART2_TXDMA) + .ops = &g_uart_rxdma_ops, +# elif !defined(CONFIG_USART2_RXDMA) && defined(CONFIG_USART2_TXDMA) + .ops = &g_uart_txdma_ops, +# else + .ops = &g_uart_ops, +# endif + .priv = &g_usart2priv, + }, + + .islpuart = false, + .irq = STM32_IRQ_USART2, + .parity = CONFIG_USART2_PARITY, + .bits = CONFIG_USART2_BITS, + .stopbits2 = CONFIG_USART2_2STOP, + .baud = CONFIG_USART2_BAUD, + .apbclock = STM32_PCLK1_FREQUENCY, + .usartbase = STM32_USART2_BASE, + .tx_gpio = GPIO_USART2_TX, + .rx_gpio = GPIO_USART2_RX, +# if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_USART2_OFLOWCONTROL) + .oflow = true, + .cts_gpio = GPIO_USART2_CTS, +# endif +# if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_USART2_IFLOWCONTROL) + .iflow = true, + .rts_gpio = GPIO_USART2_RTS, +# endif +# ifdef CONFIG_USART2_TXDMA + .txdma_channel = DMAMAP_USART2_TX, +# endif +# ifdef CONFIG_USART2_RXDMA + .rxdma_channel = DMAMAP_USART2_RX, + .rxfifo = g_usart2rxfifo, +# endif + +# ifdef CONFIG_USART2_RS485 + .rs485_dir_gpio = GPIO_USART2_RS485_DIR, +# if (CONFIG_USART2_RS485_DIR_POLARITY == 0) + .rs485_dir_polarity = false, +# else + .rs485_dir_polarity = true, +# endif +# endif + .lock = SP_UNLOCKED, +}; +#endif + +/* This describes the state of the STM32 USART3 port. */ + +#ifdef CONFIG_STM32_USART3_SERIALDRIVER +static struct up_dev_s g_usart3priv = +{ + .dev = + { +# if CONSOLE_UART == 3 + .isconsole = true, +# endif + .recv = + { + .size = CONFIG_USART3_RXBUFSIZE, + .buffer = g_usart3rxbuffer, + }, + .xmit = + { + .size = CONFIG_USART3_TXBUFSIZE, + .buffer = g_usart3txbuffer, + }, +# if defined(CONFIG_USART3_RXDMA) && defined(CONFIG_USART3_TXDMA) + .ops = &g_uart_rxtxdma_ops, +# elif defined(CONFIG_USART3_RXDMA) && !defined(CONFIG_USART3_TXDMA) + .ops = &g_uart_rxdma_ops, +# elif !defined(CONFIG_USART3_RXDMA) && defined(CONFIG_USART3_TXDMA) + .ops = &g_uart_txdma_ops, +# else + .ops = &g_uart_ops, +# endif + .priv = &g_usart3priv, + }, + + .islpuart = false, + .irq = STM32_IRQ_USART3, + .parity = CONFIG_USART3_PARITY, + .bits = CONFIG_USART3_BITS, + .stopbits2 = CONFIG_USART3_2STOP, + .baud = CONFIG_USART3_BAUD, + .apbclock = STM32_PCLK1_FREQUENCY, + .usartbase = STM32_USART3_BASE, + .tx_gpio = GPIO_USART3_TX, + .rx_gpio = GPIO_USART3_RX, +# if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_USART3_OFLOWCONTROL) + .oflow = true, + .cts_gpio = GPIO_USART3_CTS, +# endif +# if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_USART3_IFLOWCONTROL) + .iflow = true, + .rts_gpio = GPIO_USART3_RTS, +# endif +# ifdef CONFIG_USART3_TXDMA + .txdma_channel = DMAMAP_USART3_TX, +# endif +# ifdef CONFIG_USART3_RXDMA + .rxdma_channel = DMAMAP_USART3_RX, + .rxfifo = g_usart3rxfifo, +# endif + +# ifdef CONFIG_USART3_RS485 + .rs485_dir_gpio = GPIO_USART3_RS485_DIR, +# if (CONFIG_USART3_RS485_DIR_POLARITY == 0) + .rs485_dir_polarity = false, +# else + .rs485_dir_polarity = true, +# endif +# endif + .lock = SP_UNLOCKED, +}; +#endif + +/* This describes the state of the STM32 UART4 port. */ + +#ifdef CONFIG_STM32_UART4_SERIALDRIVER +static struct up_dev_s g_uart4priv = +{ + .dev = + { +# if CONSOLE_UART == 4 + .isconsole = true, +# endif + .recv = + { + .size = CONFIG_UART4_RXBUFSIZE, + .buffer = g_uart4rxbuffer, + }, + .xmit = + { + .size = CONFIG_UART4_TXBUFSIZE, + .buffer = g_uart4txbuffer, + }, +# if defined(CONFIG_UART4_RXDMA) && defined(CONFIG_UART4_TXDMA) + .ops = &g_uart_rxtxdma_ops, +# elif defined(CONFIG_UART4_RXDMA) && !defined(CONFIG_UART4_TXDMA) + .ops = &g_uart_rxdma_ops, +# elif !defined(CONFIG_UART4_RXDMA) && defined(CONFIG_UART4_TXDMA) + .ops = &g_uart_txdma_ops, +# else + .ops = &g_uart_ops, +# endif + .priv = &g_uart4priv, + }, + + .islpuart = false, + .irq = STM32_IRQ_UART4, + .parity = CONFIG_UART4_PARITY, + .bits = CONFIG_UART4_BITS, + .stopbits2 = CONFIG_UART4_2STOP, +# if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_UART4_OFLOWCONTROL) + .oflow = true, + .cts_gpio = GPIO_UART4_CTS, +# endif +# if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_UART4_IFLOWCONTROL) + .iflow = true, + .rts_gpio = GPIO_UART4_RTS, +# endif + .baud = CONFIG_UART4_BAUD, + .apbclock = STM32_PCLK1_FREQUENCY, + .usartbase = STM32_UART4_BASE, + .tx_gpio = GPIO_UART4_TX, + .rx_gpio = GPIO_UART4_RX, +# ifdef CONFIG_UART4_TXDMA + .txdma_channel = DMAMAP_UART4_TX, +# endif +# ifdef CONFIG_UART4_RXDMA + .rxdma_channel = DMAMAP_UART4_RX, + .rxfifo = g_uart4rxfifo, +# endif + +# ifdef CONFIG_UART4_RS485 + .rs485_dir_gpio = GPIO_UART4_RS485_DIR, +# if (CONFIG_UART4_RS485_DIR_POLARITY == 0) + .rs485_dir_polarity = false, +# else + .rs485_dir_polarity = true, +# endif +# endif + .lock = SP_UNLOCKED, +}; +#endif + +/* This describes the state of the STM32 UART5 port. */ + +#ifdef CONFIG_STM32_UART5_SERIALDRIVER +static struct up_dev_s g_uart5priv = +{ + .dev = + { +# if CONSOLE_UART == 5 + .isconsole = true, +# endif + .recv = + { + .size = CONFIG_UART5_RXBUFSIZE, + .buffer = g_uart5rxbuffer, + }, + .xmit = + { + .size = CONFIG_UART5_TXBUFSIZE, + .buffer = g_uart5txbuffer, + }, +# if defined(CONFIG_UART5_RXDMA) && defined(CONFIG_UART5_TXDMA) + .ops = &g_uart_rxtxdma_ops, +# elif defined(CONFIG_UART5_RXDMA) && !defined(CONFIG_UART5_TXDMA) + .ops = &g_uart_rxdma_ops, +# elif !defined(CONFIG_UART5_RXDMA) && defined(CONFIG_UART5_TXDMA) + .ops = &g_uart_txdma_ops, +# else + .ops = &g_uart_ops, +# endif + .priv = &g_uart5priv, + }, + + .islpuart = false, + .irq = STM32_IRQ_UART5, + .parity = CONFIG_UART5_PARITY, + .bits = CONFIG_UART5_BITS, + .stopbits2 = CONFIG_UART5_2STOP, +# if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_UART5_OFLOWCONTROL) + .oflow = true, + .cts_gpio = GPIO_UART5_CTS, +# endif +# if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_UART5_IFLOWCONTROL) + .iflow = true, + .rts_gpio = GPIO_UART5_RTS, +# endif + .baud = CONFIG_UART5_BAUD, + .apbclock = STM32_PCLK1_FREQUENCY, + .usartbase = STM32_UART5_BASE, + .tx_gpio = GPIO_UART5_TX, + .rx_gpio = GPIO_UART5_RX, +# ifdef CONFIG_UART5_TXDMA + .txdma_channel = DMAMAP_UART5_TX, +# endif +# ifdef CONFIG_UART5_RXDMA + .rxdma_channel = DMAMAP_UART5_RX, + .rxfifo = g_uart5rxfifo, +# endif + +# ifdef CONFIG_UART5_RS485 + .rs485_dir_gpio = GPIO_UART5_RS485_DIR, +# if (CONFIG_UART5_RS485_DIR_POLARITY == 0) + .rs485_dir_polarity = false, +# else + .rs485_dir_polarity = true, +# endif +# endif + .lock = SP_UNLOCKED, +}; +#endif + +/* This describes the state of the STM32 USART6 port. */ + +#ifdef CONFIG_STM32_USART6_SERIALDRIVER +static struct up_dev_s g_usart6priv = +{ + .dev = + { +# if CONSOLE_UART == 6 + .isconsole = true, +# endif + .recv = + { + .size = CONFIG_USART6_RXBUFSIZE, + .buffer = g_usart6rxbuffer, + }, + .xmit = + { + .size = CONFIG_USART6_TXBUFSIZE, + .buffer = g_usart6txbuffer, + }, +# if defined(CONFIG_USART6_RXDMA) && defined(CONFIG_USART6_TXDMA) + .ops = &g_uart_rxtxdma_ops, +# elif defined(CONFIG_USART6_RXDMA) && !defined(CONFIG_USART6_TXDMA) + .ops = &g_uart_rxdma_ops, +# elif !defined(CONFIG_USART6_RXDMA) && defined(CONFIG_USART6_TXDMA) + .ops = &g_uart_txdma_ops, +# else + .ops = &g_uart_ops, +# endif + .priv = &g_usart6priv, + }, + + .islpuart = false, + .irq = STM32_IRQ_USART6, + .parity = CONFIG_USART6_PARITY, + .bits = CONFIG_USART6_BITS, + .stopbits2 = CONFIG_USART6_2STOP, + .baud = CONFIG_USART6_BAUD, + .apbclock = STM32_PCLK2_FREQUENCY, + .usartbase = STM32_USART6_BASE, + .tx_gpio = GPIO_USART6_TX, + .rx_gpio = GPIO_USART6_RX, +# if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_USART6_OFLOWCONTROL) + .oflow = true, + .cts_gpio = GPIO_USART6_CTS, +# endif +# if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_USART6_IFLOWCONTROL) + .iflow = true, + .rts_gpio = GPIO_USART6_RTS, +# endif +# ifdef CONFIG_USART6_TXDMA + .txdma_channel = DMAMAP_USART6_TX, +# endif +# ifdef CONFIG_USART6_RXDMA + .rxdma_channel = DMAMAP_USART6_RX, + .rxfifo = g_usart6rxfifo, +# endif + +# ifdef CONFIG_USART6_RS485 + .rs485_dir_gpio = GPIO_USART6_RS485_DIR, +# if (CONFIG_USART6_RS485_DIR_POLARITY == 0) + .rs485_dir_polarity = false, +# else + .rs485_dir_polarity = true, +# endif +# endif + .lock = SP_UNLOCKED, +}; +#endif + +/* This describes the state of the STM32 UART7 port. */ + +#ifdef CONFIG_STM32_UART7_SERIALDRIVER +static struct up_dev_s g_uart7priv = +{ + .dev = + { +# if CONSOLE_UART == 7 + .isconsole = true, +# endif + .recv = + { + .size = CONFIG_UART7_RXBUFSIZE, + .buffer = g_uart7rxbuffer, + }, + .xmit = + { + .size = CONFIG_UART7_TXBUFSIZE, + .buffer = g_uart7txbuffer, + }, +# if defined(CONFIG_UART7_RXDMA) && defined(CONFIG_UART7_TXDMA) + .ops = &g_uart_rxtxdma_ops, +# elif defined(CONFIG_UART7_RXDMA) && !defined(CONFIG_UART7_TXDMA) + .ops = &g_uart_rxdma_ops, +# elif !defined(CONFIG_UART7_RXDMA) && defined(CONFIG_UART7_TXDMA) + .ops = &g_uart_txdma_ops, +# else + .ops = &g_uart_ops, +# endif + .priv = &g_uart7priv, + }, + + .islpuart = false, + .irq = STM32_IRQ_UART7, + .parity = CONFIG_UART7_PARITY, + .bits = CONFIG_UART7_BITS, + .stopbits2 = CONFIG_UART7_2STOP, + .baud = CONFIG_UART7_BAUD, + .apbclock = STM32_PCLK1_FREQUENCY, + .usartbase = STM32_UART7_BASE, + .tx_gpio = GPIO_UART7_TX, + .rx_gpio = GPIO_UART7_RX, +# if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_UART7_OFLOWCONTROL) + .oflow = true, + .cts_gpio = GPIO_UART7_CTS, +# endif +# if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_UART7_IFLOWCONTROL) + .iflow = true, + .rts_gpio = GPIO_UART7_RTS, +# endif +# ifdef CONFIG_UART7_TXDMA + .txdma_channel = DMAMAP_UART7_TX, +# endif +# ifdef CONFIG_UART7_RXDMA + .rxdma_channel = DMAMAP_UART7_RX, + .rxfifo = g_uart7rxfifo, +# endif + +# ifdef CONFIG_UART7_RS485 + .rs485_dir_gpio = GPIO_UART7_RS485_DIR, +# if (CONFIG_UART7_RS485_DIR_POLARITY == 0) + .rs485_dir_polarity = false, +# else + .rs485_dir_polarity = true, +# endif +# endif + .lock = SP_UNLOCKED, +}; +#endif + +/* This describes the state of the STM32 UART8 port. */ + +#ifdef CONFIG_STM32_UART8_SERIALDRIVER +static struct up_dev_s g_uart8priv = +{ + .dev = + { +# if CONSOLE_UART == 8 + .isconsole = true, +# endif + .recv = + { + .size = CONFIG_UART8_RXBUFSIZE, + .buffer = g_uart8rxbuffer, + }, + .xmit = + { + .size = CONFIG_UART8_TXBUFSIZE, + .buffer = g_uart8txbuffer, + }, +# if defined(CONFIG_UART8_RXDMA) && defined(CONFIG_UART8_TXDMA) + .ops = &g_uart_rxtxdma_ops, +# elif defined(CONFIG_UART8_RXDMA) && !defined(CONFIG_UART8_TXDMA) + .ops = &g_uart_rxdma_ops, +# elif !defined(CONFIG_UART8_RXDMA) && defined(CONFIG_UART8_TXDMA) + .ops = &g_uart_txdma_ops, +# else + .ops = &g_uart_ops, +# endif + .priv = &g_uart8priv, + }, + + .islpuart = false, + .irq = STM32_IRQ_UART8, + .parity = CONFIG_UART8_PARITY, + .bits = CONFIG_UART8_BITS, + .stopbits2 = CONFIG_UART8_2STOP, + .baud = CONFIG_UART8_BAUD, + .apbclock = STM32_PCLK1_FREQUENCY, + .usartbase = STM32_UART8_BASE, + .tx_gpio = GPIO_UART8_TX, + .rx_gpio = GPIO_UART8_RX, +# if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_UART8_OFLOWCONTROL) + .oflow = true, + .cts_gpio = GPIO_UART8_CTS, +# endif +# if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_UART8_IFLOWCONTROL) + .iflow = true, + .rts_gpio = GPIO_UART8_RTS, +# endif +# ifdef CONFIG_UART8_TXDMA + .txdma_channel = DMAMAP_UART8_TX, +# endif +# ifdef CONFIG_UART8_RXDMA + .rxdma_channel = DMAMAP_UART8_RX, + .rxfifo = g_uart8rxfifo, +# endif + +# ifdef CONFIG_UART8_RS485 + .rs485_dir_gpio = GPIO_UART8_RS485_DIR, +# if (CONFIG_UART8_RS485_DIR_POLARITY == 0) + .rs485_dir_polarity = false, +# else + .rs485_dir_polarity = true, +# endif +# endif + .lock = SP_UNLOCKED, +}; +#endif + +/* This describes the state of the STM32 LPUART1 ports. */ +#ifdef CONFIG_STM32_LPUART1_SERIALDRIVER +static struct up_dev_s g_lpuart1priv = +{ + .dev = + { +# if CONSOLE_LPUART == 1 + .isconsole = true, +# endif + .recv = + { + .size = CONFIG_LPUART1_RXBUFSIZE, + .buffer = g_lpuart1rxbuffer, + }, + .xmit = + { + .size = CONFIG_LPUART1_TXBUFSIZE, + .buffer = g_lpuart1txbuffer, + }, +# if defined(CONFIG_LPUART1_RXDMA) && defined(CONFIG_LPUART1_TXDMA) + .ops = &g_uart_rxtxdma_ops, +# elif defined(CONFIG_LPUART1_RXDMA) && !defined(CONFIG_LPUART1_TXDMA) + .ops = &g_uart_rxdma_ops, +# elif !defined(CONFIG_LPUART1_RXDMA) && defined(CONFIG_LPUART1_TXDMA) + .ops = &g_uart_txdma_ops, +# else + .ops = &g_uart_ops, +# endif + .priv = &g_lpuart1priv, + }, + + .islpuart = true, + .irq = STM32_IRQ_LPUART, + .parity = CONFIG_LPUART1_PARITY, + .bits = CONFIG_LPUART1_BITS, + .stopbits2 = CONFIG_LPUART1_2STOP, + .baud = CONFIG_LPUART1_BAUD, + .apbclock = STM32_PCLK2_FREQUENCY, + .usartbase = STM32_LPUART1_BASE, + .tx_gpio = GPIO_LPUART1_TX, + .rx_gpio = GPIO_LPUART1_RX, +# if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_LPUART1_OFLOWCONTROL) + .oflow = true, + .cts_gpio = GPIO_LPUART1_CTS, +# endif +# if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART1_IFLOWCONTROL) + .iflow = true, + .rts_gpio = GPIO_LPUART1_RTS, +# endif +# ifdef CONFIG_LPUART1_TXDMA + .txdma_channel = DMAMAP_LPUART1_TX, +# endif +# ifdef CONFIG_LPUART1_RXDMA + .rxdma_channel = DMAMAP_LPUART1_RX, + .rxfifo = g_lpuart1rxfifo, +# endif + +# ifdef CONFIG_LPUART1_RS485 + .rs485_dir_gpio = GPIO_LPUART1_RS485_DIR, +# if (CONFIG_USART1_RS485_DIR_POLARITY == 0) + .rs485_dir_polarity = false, +# else + .rs485_dir_polarity = true, +# endif +# endif + .lock = SP_UNLOCKED, +}; +#endif + +/* This table lets us iterate over the configured USARTs */ + +static struct up_dev_s * const g_uart_devs[STM32_NUSART] = +{ +#ifdef CONFIG_STM32_USART1_SERIALDRIVER + [0] = &g_usart1priv, +#endif +#ifdef CONFIG_STM32_USART2_SERIALDRIVER + [1] = &g_usart2priv, +#endif +#ifdef CONFIG_STM32_USART3_SERIALDRIVER + [2] = &g_usart3priv, +#endif +#ifdef CONFIG_STM32_UART4_SERIALDRIVER + [3] = &g_uart4priv, +#endif +#ifdef CONFIG_STM32_UART5_SERIALDRIVER + [4] = &g_uart5priv, +#endif +#ifdef CONFIG_STM32_USART6_SERIALDRIVER + [5] = &g_usart6priv, +#endif +#ifdef CONFIG_STM32_UART7_SERIALDRIVER + [6] = &g_uart7priv, +#endif +#ifdef CONFIG_STM32_UART8_SERIALDRIVER + [7] = &g_uart8priv, +#endif +}; + +/* This table lets us iterate over the configured LPUARTs */ + +static struct up_dev_s * const g_lpuart_devs[STM32_NLPUART] = +{ +#ifdef CONFIG_STM32_LPUART1_SERIALDRIVER + [0] = &g_lpuart1priv, +#endif +}; + +#ifdef CONFIG_PM +static struct pm_callback_s g_serialcb = +{ + .notify = up_pm_notify, + .prepare = up_pm_prepare, +}; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_serialin + ****************************************************************************/ + +static inline uint32_t up_serialin(struct up_dev_s *priv, int offset) +{ + return getreg32(priv->usartbase + offset); +} + +/**************************************************************************** + * Name: up_serialout + ****************************************************************************/ + +static inline void up_serialout(struct up_dev_s *priv, int offset, + uint32_t value) +{ + putreg32(value, priv->usartbase + offset); +} + +/**************************************************************************** + * Name: up_setusartint + ****************************************************************************/ + +static inline void up_setusartint(struct up_dev_s *priv, uint16_t ie) +{ + uint32_t cr; + + /* Save the interrupt mask */ + + priv->ie = ie; + + /* And restore the interrupt state (see the interrupt enable/usage + * table above) + */ + + cr = up_serialin(priv, STM32_USART_CR1_OFFSET); + cr &= ~(USART_CR1_USED_INTS); + cr |= (ie & (USART_CR1_USED_INTS)); + up_serialout(priv, STM32_USART_CR1_OFFSET, cr); + + cr = up_serialin(priv, STM32_USART_CR3_OFFSET); + cr &= ~USART_CR3_EIE; + cr |= (ie & USART_CR3_EIE); + up_serialout(priv, STM32_USART_CR3_OFFSET, cr); +} + +/**************************************************************************** + * Name: up_restoreusartint + ****************************************************************************/ + +static void up_restoreusartint(struct up_dev_s *priv, uint16_t ie) +{ + irqstate_t flags; + + flags = spin_lock_irqsave(&priv->lock); + + up_setusartint(priv, ie); + + spin_unlock_irqrestore(&priv->lock, flags); +} + +/**************************************************************************** + * Name: up_disableusartint + ****************************************************************************/ + +static void up_disableusartint(struct up_dev_s *priv, uint16_t *ie) +{ + irqstate_t flags; + + flags = spin_lock_irqsave(&priv->lock); + + if (ie) + { + uint32_t cr1; + uint32_t cr3; + + /* USART interrupts: + * + * Enable Status Meaning Usage + * ------------------ --------------- ---------------------- ---------- + * USART_CR1_IDLEIE USART_SR_IDLE Idle Line Detected (not used) + * USART_CR1_RXNEIE USART_SR_RXNE Rx Data Ready + * " " USART_SR_ORE Overrun Error Detected + * USART_CR1_TCIE USART_SR_TC Transmission Complete (RS-485) + * USART_CR1_TXEIE USART_SR_TXE Tx Data Register Empty + * USART_CR1_PEIE USART_SR_PE Parity Error + * + * USART_CR2_LBDIE USART_SR_LBD Break Flag + * USART_CR3_EIE USART_SR_FE Framing Error + * " " USART_SR_NE Noise Error + * " " USART_SR_ORE Overrun Error Detected + * USART_CR3_CTSIE USART_SR_CTS CTS flag (not used) + */ + + cr1 = up_serialin(priv, STM32_USART_CR1_OFFSET); + cr3 = up_serialin(priv, STM32_USART_CR3_OFFSET); + + /* Return the current interrupt mask value for the used interrupts. + * Notice that this depends on the fact that none of the used interrupt + * enable bits overlap. This logic would fail if we needed the break + * interrupt! + */ + + *ie = (cr1 & (USART_CR1_USED_INTS)) | (cr3 & USART_CR3_EIE); + } + + /* Disable all interrupts */ + + up_setusartint(priv, 0); + + spin_unlock_irqrestore(&priv->lock, flags); +} + +/**************************************************************************** + * Name: up_dma_nextrx + * + * Description: + * Returns the index into the RX FIFO where the DMA will place the next + * byte that it receives. + * + ****************************************************************************/ + +#ifdef SERIAL_HAVE_RXDMA +static int up_dma_nextrx(struct up_dev_s *priv) +{ + size_t dmaresidual; + + dmaresidual = stm32_dmaresidual(priv->rxdma); + + return (RXDMA_BUFFER_SIZE - (int)dmaresidual); +} +#endif + +/**************************************************************************** + * Name: up_set_format + * + * Description: + * Set the serial line format and speed. + * + ****************************************************************************/ + +#ifndef CONFIG_SUPPRESS_UART_CONFIG +static void up_set_format(struct uart_dev_s *dev) +{ + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; +#if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) || \ + defined(CONFIG_STM32_STM32F37XX) || defined(CONFIG_STM32_STM32G4XXX) + uint32_t usartdiv8; +#else + uint32_t usartdiv32; + uint32_t mantissa; + uint32_t fraction; +#endif + uint32_t regval; + uint32_t brr; + + /* Load CR1 */ + + regval = up_serialin(priv, STM32_USART_CR1_OFFSET); + +#if defined(CONFIG_STM32_STM32G4XXX) + regval &= ~(USART_CR1_UE | USART_CR1_TE | USART_CR1_RE); + up_serialout(priv, STM32_USART_CR1_OFFSET, regval); +#endif +#if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX)|| \ + defined(CONFIG_STM32_STM32F37XX) || defined(CONFIG_STM32_STM32G4XXX) + +#ifdef CONFIG_STM32_LPUART1 + if (priv->islpuart == true) + { + /* LPUART BRR (19:00) = (256*apbclock_hz/baud_rate) */ + + uint32_t apbclock_whole = priv->apbclock; + uint32_t clock_baud_ratio = apbclock_whole / priv->baud; + uint32_t presc_reg = 0x0; + + /* LPUART PRESC (3:0) + * Divide the apbclock if necessary for low baud rates + * 3 * baud_rate <= apbclock_whole <= 4096 * baud_rate + */ + + if (clock_baud_ratio <= 4096) + { + presc_reg = 0x0; + } + else if (clock_baud_ratio > 4096 && clock_baud_ratio <= 8192) + { + presc_reg = 0x1; + apbclock_whole >>= 1; + } + else if (clock_baud_ratio > 8192 && clock_baud_ratio <= 16384) + { + presc_reg = 0x2; + apbclock_whole >>= 2; + } + else if (clock_baud_ratio > 16384 && clock_baud_ratio <= 24576) + { + presc_reg = 0x3; + apbclock_whole /= 6; + } + else if (clock_baud_ratio > 24576 && clock_baud_ratio <= 32768) + { + presc_reg = 0x4; + apbclock_whole >>= 3; + } + else if (clock_baud_ratio > 32768 && clock_baud_ratio <= 40960) + { + presc_reg = 0x5; + apbclock_whole /= 10; + } + else if (clock_baud_ratio > 40960 && clock_baud_ratio <= 49152) + { + presc_reg = 0x6; + apbclock_whole /= 12; + } + else if (clock_baud_ratio > 32768 && clock_baud_ratio <= 65536) + { + presc_reg = 0x7; + apbclock_whole >>= 4; + } + else if (clock_baud_ratio > 65536 && clock_baud_ratio <= 131072) + { + presc_reg = 0x8; + apbclock_whole >>= 5; + } + else if (clock_baud_ratio > 131072 && clock_baud_ratio <= 262144) + { + presc_reg = 0x9; + apbclock_whole >>= 6; + } + else if (clock_baud_ratio > 262144 && clock_baud_ratio <= 524288) + { + presc_reg = 0xa; + apbclock_whole >>= 7; + } + else + { + presc_reg = 0xb; + apbclock_whole >>= 8; + } + + /* Write the PRESC register */ + + up_serialout(priv, STM32_USART_PRESC_OFFSET, presc_reg); + + /* Set the LPUART BRR value after setting Prescaler + * BRR = ( (256 * apbclock_whole) + baud_rate / 2 ) / baud_rate + */ + + brr = (((uint64_t)apbclock_whole << 8) + (priv->baud >> 1)) / \ + priv->baud; + } + else +#endif /* CONFIG_STM32_LPUART1 */ + { + /* This first implementation is for U[S]ARTs that support oversampling + * by 8 in additional to the standard oversampling by 16. + * With baud rate of fCK / Divider for oversampling by 16. + * and baud rate of 2 * fCK / Divider for oversampling by 8 + * + * In case of oversampling by 8, the equation is: + * + * baud = 2 * fCK / usartdiv8 + * usartdiv8 = 2 * fCK / baud + */ + + usartdiv8 = ((priv->apbclock << 1) + (priv->baud >> 1)) / priv->baud; + + /* Baud rate for standard USART (SPI mode included): + * + * In case of oversampling by 16, the equation is: + * baud = fCK / usartdiv16 + * usartdiv16 = fCK / baud + * = 2 * usartdiv8 + * + * Use oversamply by 8 only if the divisor is small. But what is small? + */ + + if (usartdiv8 > 100) + { + /* Use usartdiv16 */ + + brr = (usartdiv8 + 1) >> 1; + + /* Clear oversampling by 8 to enable oversampling by 16 */ + + regval &= ~USART_CR1_OVER8; + } + else + { + DEBUGASSERT(usartdiv8 >= 8); + + /* Perform mysterious operations on bits 0-3 */ + + brr = ((usartdiv8 & 0xfff0) | ((usartdiv8 & 0x000f) >> 1)); + + /* Set oversampling by 8 */ + + regval |= USART_CR1_OVER8; + } + } +#else + /* This second implementation is for U[S]ARTs that support fractional + * dividers. + * + * Configure the USART Baud Rate. The baud rate for the receiver and + * transmitter (Rx and Tx) are both set to the same value as programmed + * in the Mantissa and Fraction values of USARTDIV. + * + * baud = fCK / (16 * usartdiv) + * usartdiv = fCK / (16 * baud) + * + * Where fCK is the input clock to the peripheral (PCLK1 for USART2, 3, + * 4, 5 or PCLK2 for USART1) + * + * First calculate (NOTE: all standard baud values are even so dividing by + * two does not lose precision): + * + * usartdiv32 = 32 * usartdiv = fCK / (baud/2) + */ + + usartdiv32 = priv->apbclock / (priv->baud >> 1); + + /* The mantissa part is then */ + + mantissa = usartdiv32 >> 5; + + /* The fractional remainder (with rounding) */ + + fraction = (usartdiv32 - (mantissa << 5) + 1) >> 1; + +#if defined(CONFIG_STM32_STM32F4XXX) + /* The F4 supports 8 X in oversampling additional to the + * standard oversampling by 16. + * + * With baud rate of fCK / (16 * Divider) for oversampling by 16. + * and baud rate of fCK / (8 * Divider) for oversampling by 8 + */ + + /* Check if 8x oversampling is necessary */ + + if (mantissa == 0) + { + regval |= USART_CR1_OVER8; + + /* Rescale the mantissa */ + + mantissa = usartdiv32 >> 4; + + /* The fractional remainder (with rounding) */ + + fraction = (usartdiv32 - (mantissa << 4) + 1) >> 1; + } + else + { + /* Use 16x Oversampling */ + + regval &= ~USART_CR1_OVER8; + } +#endif + + brr = mantissa << USART_BRR_MANT_SHIFT; + brr |= fraction << USART_BRR_FRAC_SHIFT; +#endif + + up_serialout(priv, STM32_USART_CR1_OFFSET, regval); + up_serialout(priv, STM32_USART_BRR_OFFSET, brr); + + /* Configure parity mode */ + + regval &= ~(USART_CR1_PCE | USART_CR1_PS | USART_CR1_M); + + if (priv->parity == 1) /* Odd parity */ + { + regval |= (USART_CR1_PCE | USART_CR1_PS); + } + else if (priv->parity == 2) /* Even parity */ + { + regval |= USART_CR1_PCE; + } + + /* Configure word length (parity uses one of configured bits) + * + * Default: 1 start, 8 data (no parity), n stop, OR + * 1 start, 7 data + parity, n stop + */ + + if (priv->bits == 9 || (priv->bits == 8 && priv->parity != 0)) + { + /* Select: 1 start, 8 data + parity, n stop, OR + * 1 start, 9 data (no parity), n stop. + */ + + regval |= USART_CR1_M; + } + + up_serialout(priv, STM32_USART_CR1_OFFSET, regval); + + /* Configure STOP bits */ + + regval = up_serialin(priv, STM32_USART_CR2_OFFSET); + regval &= ~(USART_CR2_STOP_MASK); + + if (priv->stopbits2) + { + regval |= USART_CR2_STOP2; + } + + up_serialout(priv, STM32_USART_CR2_OFFSET, regval); + + /* Configure hardware flow control */ + + regval = up_serialin(priv, STM32_USART_CR3_OFFSET); + regval &= ~(USART_CR3_CTSE | USART_CR3_RTSE); + +#if defined(CONFIG_SERIAL_IFLOWCONTROL) && \ + !defined(CONFIG_STM32_FLOWCONTROL_BROKEN) + if (priv->iflow && (priv->rts_gpio != 0)) + { + regval |= USART_CR3_RTSE; + } +#endif + +#ifdef CONFIG_SERIAL_OFLOWCONTROL + if (priv->oflow && (priv->cts_gpio != 0)) + { + regval |= USART_CR3_CTSE; + } +#endif + + up_serialout(priv, STM32_USART_CR3_OFFSET, regval); +#if defined(CONFIG_STM32_STM32G4XXX) + regval = up_serialin(priv, STM32_USART_CR1_OFFSET); + regval |= (USART_CR1_UE | USART_CR1_TE | USART_CR1_RE); + up_serialout(priv, STM32_USART_CR1_OFFSET, regval); +#endif +} +#endif /* CONFIG_SUPPRESS_UART_CONFIG */ + +/**************************************************************************** + * Name: up_set_apb_clock + * + * Description: + * Enable or disable APB clock for the USART peripheral + * + * Input Parameters: + * dev - A reference to the UART driver state structure + * on - Enable clock if 'on' is 'true' and disable if 'false' + * + ****************************************************************************/ + +static void up_set_apb_clock(struct uart_dev_s *dev, bool on) +{ + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; + uint32_t rcc_en; + uint32_t regaddr; + + /* Determine which USART to configure */ + + switch (priv->usartbase) + { + default: + return; +#ifdef CONFIG_STM32_USART1_SERIALDRIVER + case STM32_USART1_BASE: + rcc_en = RCC_APB2ENR_USART1EN; + regaddr = STM32_RCC_APB2ENR; + break; +#endif +#ifdef CONFIG_STM32_USART2_SERIALDRIVER + case STM32_USART2_BASE: + rcc_en = RCC_APB1ENR_USART2EN; + regaddr = STM32_RCC_APB1ENR; + break; +#endif +#ifdef CONFIG_STM32_USART3_SERIALDRIVER + case STM32_USART3_BASE: + rcc_en = RCC_APB1ENR_USART3EN; + regaddr = STM32_RCC_APB1ENR; + break; +#endif +#ifdef CONFIG_STM32_UART4_SERIALDRIVER + case STM32_UART4_BASE: + rcc_en = RCC_APB1ENR_UART4EN; + regaddr = STM32_RCC_APB1ENR; + break; +#endif +#ifdef CONFIG_STM32_UART5_SERIALDRIVER + case STM32_UART5_BASE: + rcc_en = RCC_APB1ENR_UART5EN; + regaddr = STM32_RCC_APB1ENR; + break; +#endif +#ifdef CONFIG_STM32_USART6_SERIALDRIVER + case STM32_USART6_BASE: + rcc_en = RCC_APB2ENR_USART6EN; + regaddr = STM32_RCC_APB2ENR; + break; +#endif +#ifdef CONFIG_STM32_UART7_SERIALDRIVER + case STM32_UART7_BASE: + rcc_en = RCC_APB1ENR_UART7EN; + regaddr = STM32_RCC_APB1ENR; + break; +#endif +#ifdef CONFIG_STM32_UART8_SERIALDRIVER + case STM32_UART8_BASE: + rcc_en = RCC_APB1ENR_UART8EN; + regaddr = STM32_RCC_APB1ENR; + break; +#endif +#ifdef CONFIG_STM32_LPUART1_SERIALDRIVER + case STM32_LPUART1_BASE: + rcc_en = RCC_APB1ENR2_LPUART1EN; + regaddr = STM32_RCC_APB1ENR2; + break; +#endif + } + + /* Enable/disable APB 1/2 clock for USART */ + + if (on) + { + modifyreg32(regaddr, 0, rcc_en); + } + else + { + modifyreg32(regaddr, rcc_en, 0); + } +} + +/**************************************************************************** + * Name: up_setup + * + * Description: + * Configure the USART baud, bits, parity, etc. This method is called the + * first time that the serial port is opened. + * + ****************************************************************************/ + +static int up_setup(struct uart_dev_s *dev) +{ + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; + +#ifndef CONFIG_SUPPRESS_UART_CONFIG + uint32_t regval; + + /* Note: The logic here depends on the fact that that the USART module + * was enabled in stm32_lowsetup(). + */ + + /* Enable USART APB1/2 clock */ + + up_set_apb_clock(dev, true); + + /* Configure pins for USART use */ + + if (priv->tx_gpio != 0) + { + stm32_configgpio(priv->tx_gpio); + } + + if (priv->rx_gpio != 0) + { + stm32_configgpio(priv->rx_gpio); + } + +#ifdef CONFIG_SERIAL_OFLOWCONTROL + if (priv->cts_gpio != 0) + { + stm32_configgpio(priv->cts_gpio); + } +#endif + +#ifdef CONFIG_SERIAL_IFLOWCONTROL + if (priv->rts_gpio != 0) + { + uint32_t config = priv->rts_gpio; + +#ifdef CONFIG_STM32_FLOWCONTROL_BROKEN + /* Instead of letting hw manage this pin, we will bitbang */ + + config = (config & ~GPIO_MODE_MASK) | GPIO_OUTPUT; +#endif + stm32_configgpio(config); + } +#endif + +#ifdef HAVE_RS485 + if (priv->rs485_dir_gpio != 0) + { + stm32_configgpio(priv->rs485_dir_gpio); + stm32_gpiowrite(priv->rs485_dir_gpio, !priv->rs485_dir_polarity); + } +#endif + + /* Configure CR2 + * Clear STOP, CLKEN, CPOL, CPHA, LBCL, and interrupt enable bits + */ + + regval = up_serialin(priv, STM32_USART_CR2_OFFSET); + if (priv->islpuart == true) + { + regval &= ~(USART_CR2_STOP_MASK | USART_CR2_CLKEN); + } + else + { + regval &= ~(USART_CR2_STOP_MASK | USART_CR2_CLKEN | USART_CR2_CPOL | + USART_CR2_CPHA | USART_CR2_LBCL | USART_CR2_LBDIE); + } + + /* Configure STOP bits */ + + if (priv->stopbits2) + { + regval |= USART_CR2_STOP2; + } + + up_serialout(priv, STM32_USART_CR2_OFFSET, regval); + + /* Configure CR1 + * Clear TE, REm and all interrupt enable bits + */ + + regval = up_serialin(priv, STM32_USART_CR1_OFFSET); + +#ifdef CONFIG_STM32_LPUART1 + if (priv->islpuart == true) + { + regval &= ~(USART_CR1_TE | USART_CR1_RE | LPUART_CR1_ALLINTS); + } + else +#endif + { + regval &= ~(USART_CR1_TE | USART_CR1_RE | USART_CR1_ALLINTS); + } + + up_serialout(priv, STM32_USART_CR1_OFFSET, regval); + + /* Configure CR3 + * Clear CTSE, RTSE, and all interrupt enable bits + */ + + regval = up_serialin(priv, STM32_USART_CR3_OFFSET); + regval &= ~(USART_CR3_CTSIE | USART_CR3_CTSE | USART_CR3_RTSE | + USART_CR3_EIE); + + up_serialout(priv, STM32_USART_CR3_OFFSET, regval); + + /* Configure the USART line format and speed. */ + + up_set_format(dev); + + /* Enable Rx, Tx, and the USART */ + + regval = up_serialin(priv, STM32_USART_CR1_OFFSET); + regval |= (USART_CR1_UE | USART_CR1_TE | USART_CR1_RE); + up_serialout(priv, STM32_USART_CR1_OFFSET, regval); + +#endif /* CONFIG_SUPPRESS_UART_CONFIG */ + + /* Set up the cached interrupt enables value */ + + priv->ie = 0; + + /* Mark device as initialized. */ + + priv->initialized = true; + + return OK; +} + +/**************************************************************************** + * Name: up_dma_setup + * + * Description: + * Configure the USART baud, bits, parity, etc. This method is called the + * first time that the serial port is opened. + * + ****************************************************************************/ + +#if defined(SERIAL_HAVE_RXDMA) || defined(SERIAL_HAVE_TXDMA) +static int up_dma_setup(struct uart_dev_s *dev) +{ + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; + int result; + + /* Do the basic UART setup first, unless we are the console */ + + if (!dev->isconsole) + { + result = up_setup(dev); + if (result != OK) + { + return result; + } + } + +#if defined(SERIAL_HAVE_TXDMA) + /* Acquire the Tx DMA channel. This should always succeed. */ + + if (priv->txdma_channel != INVALID_SERIAL_DMA_CHANNEL) + { + priv->txdma = stm32_dmachannel(priv->txdma_channel); + + /* Enable receive Tx DMA for the UART */ + + modifyreg32(priv->usartbase + STM32_USART_CR3_OFFSET, + 0, USART_CR3_DMAT); + } +#endif + +#if defined(SERIAL_HAVE_RXDMA) + /* Acquire the DMA channel. This should always succeed. */ + + if (priv->rxdma_channel != INVALID_SERIAL_DMA_CHANNEL) + { + priv->rxdma = stm32_dmachannel(priv->rxdma_channel); + + /* Configure for circular DMA reception into the RX fifo */ + + stm32_dmasetup(priv->rxdma, + priv->usartbase + STM32_USART_RDR_OFFSET, + (uint32_t)priv->rxfifo, + RXDMA_BUFFER_SIZE, + SERIAL_RXDMA_CONTROL_WORD); + + /* Reset our DMA shadow pointer to match the address just + * programmed above. + */ + + priv->rxdmanext = 0; + + /* Enable receive Rx DMA for the UART */ + + modifyreg32(priv->usartbase + STM32_USART_CR3_OFFSET, + 0, USART_CR3_DMAR); + + /* Start the DMA channel, and arrange for callbacks at the half and + * full points in the FIFO. This ensures that we have half a FIFO + * worth of time to claim bytes before they are overwritten. + */ + + stm32_dmastart(priv->rxdma, up_dma_rxcallback, (void *)priv, true); + } +#endif + + return OK; +} +#endif + +/**************************************************************************** + * Name: up_shutdown + * + * Description: + * Disable the USART. This method is called when the serial + * port is closed + * + ****************************************************************************/ + +static void up_shutdown(struct uart_dev_s *dev) +{ + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; + uint32_t regval; + + /* Mark device as uninitialized. */ + + priv->initialized = false; + + /* Disable all interrupts */ + + up_disableusartint(priv, NULL); + + /* Disable USART APB1/2 clock */ + + up_set_apb_clock(dev, false); + + /* Disable Rx, Tx, and the UART */ + + regval = up_serialin(priv, STM32_USART_CR1_OFFSET); + regval &= ~(USART_CR1_UE | USART_CR1_TE | USART_CR1_RE); + up_serialout(priv, STM32_USART_CR1_OFFSET, regval); + + /* Release pins. "If the serial-attached device is powered down, the TX + * pin causes back-powering, potentially confusing the device to the point + * of complete lock-up." + * + * REVISIT: Is unconfiguring the pins appropriate for all device? If not, + * then this may need to be a configuration option. + */ + + if (priv->tx_gpio != 0) + { + stm32_unconfiggpio(priv->tx_gpio); + } + + if (priv->rx_gpio != 0) + { + stm32_unconfiggpio(priv->rx_gpio); + } + +#ifdef CONFIG_SERIAL_OFLOWCONTROL + if (priv->cts_gpio != 0) + { + stm32_unconfiggpio(priv->cts_gpio); + } +#endif + +#ifdef CONFIG_SERIAL_IFLOWCONTROL + if (priv->rts_gpio != 0) + { + stm32_unconfiggpio(priv->rts_gpio); + } +#endif + +#ifdef HAVE_RS485 + if (priv->rs485_dir_gpio != 0) + { + stm32_unconfiggpio(priv->rs485_dir_gpio); + } +#endif +} + +/**************************************************************************** + * Name: up_dma_shutdown + * + * Description: + * Disable the USART. This method is called when the serial + * port is closed + * + ****************************************************************************/ + +#if defined(SERIAL_HAVE_RXDMA) || defined(SERIAL_HAVE_TXDMA) +static void up_dma_shutdown(struct uart_dev_s *dev) +{ + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; + + /* Perform the normal UART shutdown */ + + up_shutdown(dev); + +#if defined(SERIAL_HAVE_RXDMA) + /* Stop the RX DMA channel */ + + if (priv->rxdma_channel != INVALID_SERIAL_DMA_CHANNEL) + { + stm32_dmastop(priv->rxdma); + + /* Release the RX DMA channel */ + + stm32_dmafree(priv->rxdma); + priv->rxdma = NULL; + } +#endif + +#if defined(SERIAL_HAVE_TXDMA) + /* Stop the TX DMA channel */ + + if (priv->txdma_channel != INVALID_SERIAL_DMA_CHANNEL) + { + stm32_dmastop(priv->txdma); + + /* Release the TX DMA channel */ + + stm32_dmafree(priv->txdma); + priv->txdma = NULL; + } +#endif +} +#endif + +/**************************************************************************** + * Name: up_attach + * + * Description: + * Configure the USART to operation in interrupt driven mode. This method + * is called when the serial port is opened. Normally, this is just after + * the setup() method is called, however, the serial console may operate + * in a non-interrupt driven mode during the boot phase. + * + * RX and TX interrupts are not enabled when by the attach method (unless + * the hardware supports multiple levels of interrupt enabling). The RX + * and TX interrupts are not enabled until the txint() and rxint() methods + * are called. + * + ****************************************************************************/ + +static int up_attach(struct uart_dev_s *dev) +{ + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; + int ret; + + /* Attach and enable the IRQ */ + + ret = irq_attach(priv->irq, up_interrupt, priv); + if (ret == OK) + { + /* Enable the interrupt (RX and TX interrupts are still disabled + * in the USART + */ + + up_enable_irq(priv->irq); + } + + return ret; +} + +/**************************************************************************** + * Name: up_detach + * + * Description: + * Detach USART interrupts. This method is called when the serial port is + * closed normally just before the shutdown method is called. The + * exception is the serial console which is never shutdown. + * + ****************************************************************************/ + +static void up_detach(struct uart_dev_s *dev) +{ + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; + up_disable_irq(priv->irq); + irq_detach(priv->irq); +} + +/**************************************************************************** + * Name: up_interrupt + * + * Description: + * This is the UART interrupt handler. It will be invoked when an + * interrupt is received on the 'irq'. It should call uart_xmitchars or + * uart_recvchars to perform the appropriate data transfers. The + * interrupt handling logic must be able to map the 'arg' to the + * appropriate uart_dev_s structure in order to call these functions. + * + ****************************************************************************/ + +static int up_interrupt(int irq, void *context, void *arg) +{ + struct up_dev_s *priv = (struct up_dev_s *)arg; + int passes; + bool handled; + + DEBUGASSERT(priv != NULL); + + /* Report serial activity to the power management logic */ + +#if defined(CONFIG_PM) && CONFIG_STM32_PM_SERIAL_ACTIVITY > 0 + pm_activity(PM_IDLE_DOMAIN, CONFIG_STM32_PM_SERIAL_ACTIVITY); +#endif + + /* Loop until there are no characters to be transferred or, + * until we have been looping for a long time. + */ + + handled = true; + for (passes = 0; passes < 256 && handled; passes++) + { + handled = false; + + /* Get the masked USART status word. */ + + priv->sr = up_serialin(priv, STM32_USART_SR_OFFSET); + + /* USART interrupts: + * + * Enable Status Meaning Usage + * ------------------ --------------- ---------------------- ---------- + * USART_CR1_IDLEIE USART_SR_IDLE Idle Line Detected (not used) + * USART_CR1_RXNEIE USART_SR_RXNE Rx Data Ready + * " " USART_SR_ORE Overrun Error Detected + * USART_CR1_TCIE USART_SR_TC Tx Complete (RS-485) + * USART_CR1_TXEIE USART_SR_TXE Tx Data Register Empty + * USART_CR1_PEIE USART_SR_PE Parity Error + * + * USART_CR2_LBDIE USART_SR_LBD Break Flag + * USART_CR3_EIE USART_SR_FE Framing Error + * " " USART_SR_NE Noise Error + * " " USART_SR_ORE Overrun Error Detected + * USART_CR3_CTSIE USART_SR_CTS CTS flag (not used) + * + * NOTE: Some of these status bits must be cleared by explicitly + * writing zero to the SR register: USART_SR_CTS, USART_SR_LBD. Note of + * those are currently being used. + */ + + /* Error report */ + +#ifdef CONFIG_SERIAL_TIOCGICOUNT + if (priv->sr & USART_SR_FE) + { + priv->icount.frame++; + } + + if (priv->sr & USART_SR_ORE) + { + priv->icount.overrun++; + } + + if (priv->sr & USART_SR_PE) + { + priv->icount.parity++; + } + + if (priv->sr & USART_SR_LBD) + { + priv->icount.brk++; + } +#endif + +#ifdef HAVE_RS485 + /* Transmission of whole buffer is over - TC is set, TXEIE is cleared. + * Note - this should be first, to have the most recent TC bit value + * from SR register - sending data affects TC, but without refresh we + * will not know that... + */ + + if (((priv->sr & USART_SR_TC) != 0) && + ((priv->ie & USART_CR1_TCIE) != 0) && + ((priv->ie & USART_CR1_TXEIE) == 0)) + { + stm32_gpiowrite(priv->rs485_dir_gpio, !priv->rs485_dir_polarity); + up_restoreusartint(priv, priv->ie & ~USART_CR1_TCIE); + } +#endif + + /* Handle incoming, receive bytes. */ + + if (((priv->sr & USART_SR_RXNE) != 0) && + ((priv->ie & USART_CR1_RXNEIE) != 0)) + { + /* Received data ready... process incoming bytes. NOTE the check + * for RXNEIE: We cannot call uart_recvchards of RX interrupts are + * disabled. + */ + + uart_recvchars(&priv->dev); + handled = true; + } + + /* We may still have to read from the DR register to clear any pending + * error conditions. + */ + + else if ((priv->sr & (USART_SR_ORE | USART_SR_NE | USART_SR_FE | + USART_SR_LBD)) != 0) + { +#if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) || \ + defined(CONFIG_STM32_STM32F37XX) || defined(CONFIG_STM32_STM32G4XXX) + /* These errors are cleared by writing the corresponding bit to the + * interrupt clear register (ICR). + */ + + up_serialout(priv, STM32_USART_ICR_OFFSET, + (USART_ICR_NCF | USART_ICR_ORECF | USART_ICR_FECF | + USART_ICR_LBDCF)); +#else + /* If an error occurs, read from DR to clear the error (data has + * been lost). If ORE is set along with RXNE then it tells you + * that the byte *after* the one in the data register has been + * lost, but the data register value is correct. That case will + * be handled above if interrupts are enabled. Otherwise, that + * good byte will be lost. + */ + + up_serialin(priv, STM32_USART_RDR_OFFSET); +#endif + } + + /* Handle outgoing, transmit bytes */ + + if (((priv->sr & USART_SR_TXE) != 0) && + ((priv->ie & USART_CR1_TXEIE) != 0)) + { + /* Transmit data register empty ... process outgoing bytes */ + + uart_xmitchars(&priv->dev); + handled = true; + } + } + + return OK; +} + +/**************************************************************************** + * Name: up_ioctl + * + * Description: + * All ioctl calls will be routed through this method + * + ****************************************************************************/ + +static int up_ioctl(struct file *filep, int cmd, unsigned long arg) +{ +#if defined(CONFIG_SERIAL_TERMIOS) || defined(CONFIG_SERIAL_TIOCSERGSTRUCT) \ + || defined(CONFIG_SERIAL_TIOCGICOUNT) \ + || defined(CONFIG_STM32_SERIALBRK_BSDCOMPAT) \ + || defined(CONFIG_STM32_USART_SINGLEWIRE) + struct inode *inode = filep->f_inode; + struct uart_dev_s *dev = inode->i_private; +#endif +#if defined(CONFIG_SERIAL_TERMIOS) \ + || defined(CONFIG_SERIAL_TIOCGICOUNT) \ + || defined(CONFIG_STM32_SERIALBRK_BSDCOMPAT) \ + || defined(CONFIG_STM32_USART_SINGLEWIRE) + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; +#endif + int ret = OK; + + switch (cmd) + { +#ifdef CONFIG_SERIAL_TIOCSERGSTRUCT + case TIOCSERGSTRUCT: + { + struct up_dev_s *user = (struct up_dev_s *)arg; + if (!user) + { + ret = -EINVAL; + } + else + { + memcpy(user, dev, sizeof(struct up_dev_s)); + } + } + break; +#endif + +#ifdef CONFIG_SERIAL_TIOCGICOUNT + /* Get U(S)ART error counters */ + + case TIOCGICOUNT: + { + struct serial_icounter_s *icount = (struct serial_icounter_s *)arg; + if (icount == NULL) + { + ret = -EINVAL; + } + else + { + memcpy(icount, &priv->icount, sizeof(struct serial_icounter_s)); + } + } + break; +#endif + +#ifdef CONFIG_STM32_USART_SINGLEWIRE + case TIOCSSINGLEWIRE: + { + /* Change the TX port to be open-drain/push-pull and enable/disable + * half-duplex mode. + */ + + uint32_t cr = up_serialin(priv, STM32_USART_CR3_OFFSET); + +#if defined(CONFIG_STM32_STM32F10XX) + if ((arg & SER_SINGLEWIRE_ENABLED) != 0) + { + if (priv->tx_gpio != 0) + { + stm32_configgpio((priv->tx_gpio & ~(GPIO_CNF_MASK)) | + GPIO_CNF_AFOD); + } + + cr |= USART_CR3_HDSEL; + } + else + { + if (priv->tx_gpio != 0) + { + stm32_configgpio((priv->tx_gpio & ~(GPIO_CNF_MASK)) | + GPIO_CNF_AFPP); + } + + cr &= ~USART_CR3_HDSEL; + } +#else + if ((arg & SER_SINGLEWIRE_ENABLED) != 0) + { + uint32_t gpio_val = (arg & SER_SINGLEWIRE_PUSHPULL) == + SER_SINGLEWIRE_PUSHPULL ? + GPIO_PUSHPULL : GPIO_OPENDRAIN; + gpio_val |= ((arg & SER_SINGLEWIRE_PULL_MASK) == + SER_SINGLEWIRE_PULLUP) ? GPIO_PULLUP + : GPIO_FLOAT; + gpio_val |= ((arg & SER_SINGLEWIRE_PULL_MASK) == + SER_SINGLEWIRE_PULLDOWN) ? GPIO_PULLDOWN + : GPIO_FLOAT; + if (priv->tx_gpio != 0) + { + stm32_configgpio((priv->tx_gpio & ~(GPIO_PUPD_MASK | + GPIO_OPENDRAIN)) | + gpio_val); + } + + cr |= USART_CR3_HDSEL; + } + else + { + if (priv->tx_gpio != 0) + { + stm32_configgpio((priv->tx_gpio & ~(GPIO_PUPD_MASK | + GPIO_OPENDRAIN)) | + GPIO_PUSHPULL); + } + + cr &= ~USART_CR3_HDSEL; + } +#endif + + up_serialout(priv, STM32_USART_CR3_OFFSET, cr); + } + break; +#endif + +#ifdef CONFIG_SERIAL_TERMIOS + case TCGETS: + { + struct termios *termiosp = (struct termios *)arg; + + if (!termiosp) + { + ret = -EINVAL; + break; + } + + /* Note that since we only support 8/9 bit modes and + * there is no way to report 9-bit mode, we always claim 8. + */ + + termiosp->c_cflag = + ((priv->parity != 0) ? PARENB : 0) | + ((priv->parity == 1) ? PARODD : 0) | + ((priv->stopbits2) ? CSTOPB : 0) | +#ifdef CONFIG_SERIAL_OFLOWCONTROL + ((priv->oflow) ? CCTS_OFLOW : 0) | +#endif +#ifdef CONFIG_SERIAL_IFLOWCONTROL + ((priv->iflow) ? CRTS_IFLOW : 0) | +#endif + CS8; + + cfsetispeed(termiosp, priv->baud); + + /* TODO: CRTS_IFLOW, CCTS_OFLOW */ + } + break; + + case TCSETS: + { + struct termios *termiosp = (struct termios *)arg; + + if (!termiosp) + { + ret = -EINVAL; + break; + } + + /* Perform some sanity checks before accepting any changes */ + + if (((termiosp->c_cflag & CSIZE) != CS8) +#ifdef CONFIG_SERIAL_OFLOWCONTROL + || ((termiosp->c_cflag & CCTS_OFLOW) && (priv->cts_gpio == 0)) +#endif +#ifdef CONFIG_SERIAL_IFLOWCONTROL + || ((termiosp->c_cflag & CRTS_IFLOW) && (priv->rts_gpio == 0)) +#endif + ) + { + ret = -EINVAL; + break; + } + + if (termiosp->c_cflag & PARENB) + { + priv->parity = (termiosp->c_cflag & PARODD) ? 1 : 2; + } + else + { + priv->parity = 0; + } + + priv->stopbits2 = (termiosp->c_cflag & CSTOPB) != 0; +#ifdef CONFIG_SERIAL_OFLOWCONTROL + priv->oflow = (termiosp->c_cflag & CCTS_OFLOW) != 0; +#endif +#ifdef CONFIG_SERIAL_IFLOWCONTROL + priv->iflow = (termiosp->c_cflag & CRTS_IFLOW) != 0; +#endif + + /* Note that since there is no way to request 9-bit mode + * and no way to support 5/6/7-bit modes, we ignore them + * all here. + */ + + /* Note that only cfgetispeed is used because we have knowledge + * that only one speed is supported. + */ + + priv->baud = cfgetispeed(termiosp); + + /* Effect the changes immediately - note that we do not implement + * TCSADRAIN / TCSAFLUSH + */ + + up_set_format(dev); + } + break; +#endif /* CONFIG_SERIAL_TERMIOS */ + +#ifdef CONFIG_STM32_USART_BREAKS +# ifdef CONFIG_STM32_SERIALBRK_BSDCOMPAT + case TIOCSBRK: /* BSD compatibility: Turn break on, unconditionally */ + { + irqstate_t flags; + + flags = enter_critical_section(); + + /* Disable any further tx activity */ + + priv->ie |= USART_CR1_IE_BREAK_INPROGRESS; + + up_txint(dev, false); + + /* Configure TX as a GPIO output pin and Send a break signal */ + + if (priv->tx_gpio != 0) + { + uint32_t tx_break = GPIO_OUTPUT | + (~(GPIO_MODE_MASK | GPIO_OUTPUT_SET) & + priv->tx_gpio); + stm32_configgpio(tx_break); + } + + leave_critical_section(flags); + } + break; + + case TIOCCBRK: /* BSD compatibility: Turn break off, unconditionally */ + { + irqstate_t flags; + + flags = enter_critical_section(); + + /* Configure TX back to U(S)ART */ + + if (priv->tx_gpio != 0) + { + stm32_configgpio(priv->tx_gpio); + } + + priv->ie &= ~USART_CR1_IE_BREAK_INPROGRESS; + + /* Enable further tx activity */ + + up_txint(dev, true); + + leave_critical_section(flags); + } + break; +# else + case TIOCSBRK: /* No BSD compatibility: Turn break on for M bit times */ + { + uint32_t cr1; + irqstate_t flags; + + flags = enter_critical_section(); + cr1 = up_serialin(priv, STM32_USART_CR1_OFFSET); + up_serialout(priv, STM32_USART_CR1_OFFSET, cr1 | USART_CR1_SBK); + leave_critical_section(flags); + } + break; + + case TIOCCBRK: /* No BSD compatibility: May turn off break too soon */ + { + uint32_t cr1; + irqstate_t flags; + + flags = enter_critical_section(); + cr1 = up_serialin(priv, STM32_USART_CR1_OFFSET); + up_serialout(priv, STM32_USART_CR1_OFFSET, cr1 & ~USART_CR1_SBK); + leave_critical_section(flags); + } + break; +# endif +#endif + + default: + ret = -ENOTTY; + break; + } + + return ret; +} + +/**************************************************************************** + * Name: up_receive + * + * Description: + * Called (usually) from the interrupt level to receive one + * character from the USART. Error bits associated with the + * receipt are provided in the return 'status'. + * + ****************************************************************************/ + +#if defined(SERIAL_HAVE_TXDMA_OPS) || defined(SERIAL_HAVE_NODMA_OPS) +static int up_receive(struct uart_dev_s *dev, unsigned int *status) +{ + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; + uint32_t rdr; + + /* Get the Rx byte */ + + rdr = up_serialin(priv, STM32_USART_RDR_OFFSET); + + /* Get the Rx byte plux error information. Return those in status */ + + *status = priv->sr << 16 | rdr; + priv->sr = 0; + + /* Then return the actual received byte */ + + return rdr & 0xff; +} +#endif + +/**************************************************************************** + * Name: up_rxint + * + * Description: + * Call to enable or disable RX interrupts + * + ****************************************************************************/ + +#if defined(SERIAL_HAVE_TXDMA_OPS) || defined(SERIAL_HAVE_NODMA_OPS) +static void up_rxint(struct uart_dev_s *dev, bool enable) +{ + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; + irqstate_t flags; + uint16_t ie; + + /* USART receive interrupts: + * + * Enable Status Meaning Usage + * ------------------ --------------- ------------------------- ---------- + * USART_CR1_IDLEIE USART_SR_IDLE Idle Line Detected (not used) + * USART_CR1_RXNEIE USART_SR_RXNE Rx Data Ready to be Read + * " " USART_SR_ORE Overrun Error Detected + * USART_CR1_PEIE USART_SR_PE Parity Error + * + * USART_CR2_LBDIE USART_SR_LBD Break Flag + * USART_CR3_EIE USART_SR_FE Framing Error + * " " USART_SR_NE Noise Error + * " " USART_SR_ORE Overrun Error Detected + */ + + flags = enter_critical_section(); + ie = priv->ie; + if (enable) + { + /* Receive an interrupt when their is anything in the Rx data register + * (or an Rx timeout occurs). + */ + +#ifndef CONFIG_SUPPRESS_SERIAL_INTS +#ifdef CONFIG_USART_ERRINTS + ie |= (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR3_EIE); +#else + ie |= USART_CR1_RXNEIE; +#endif +#endif + } + else + { + ie &= ~(USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR3_EIE); + } + + /* Then set the new interrupt state */ + + up_restoreusartint(priv, ie); + leave_critical_section(flags); +} +#endif + +/**************************************************************************** + * Name: up_rxavailable + * + * Description: + * Return true if the receive register is not empty + * + ****************************************************************************/ + +#if defined(SERIAL_HAVE_TXDMA_OPS) || defined(SERIAL_HAVE_NODMA_OPS) +static bool up_rxavailable(struct uart_dev_s *dev) +{ + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; + return ((up_serialin(priv, STM32_USART_SR_OFFSET) & USART_SR_RXNE) != 0); +} +#endif + +/**************************************************************************** + * Name: up_rxflowcontrol + * + * Description: + * Called when Rx buffer is full (or exceeds configured watermark levels + * if CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS is defined). + * Return true if UART activated RX flow control to block more incoming + * data + * + * Input Parameters: + * dev - UART device instance + * nbuffered - the number of characters currently buffered + * (if CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS is + * not defined the value will be 0 for an empty buffer or the + * defined buffer size for a full buffer) + * upper - true indicates the upper watermark was crossed where + * false indicates the lower watermark has been crossed + * + * Returned Value: + * true if RX flow control activated. + * + ****************************************************************************/ + +#ifdef CONFIG_SERIAL_IFLOWCONTROL +static bool up_rxflowcontrol(struct uart_dev_s *dev, + unsigned int nbuffered, bool upper) +{ + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; + +#if defined(CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS) && \ + defined(CONFIG_STM32_FLOWCONTROL_BROKEN) + if (priv->iflow && (priv->rts_gpio != 0)) + { + /* Assert/de-assert nRTS set it high resume/stop sending */ + + stm32_gpiowrite(priv->rts_gpio, upper); + + if (upper) + { + /* With heavy Rx traffic, RXNE might be set and data pending. + * Returning 'true' in such case would cause RXNE left unhandled + * and causing interrupt storm. Sending end might be also be slow + * to react on nRTS, and returning 'true' here would prevent + * processing that data. + * + * Therefore, return 'false' so input data is still being processed + * until sending end reacts on nRTS signal and stops sending more. + */ + + return false; + } + + return upper; + } + +#else + if (priv->iflow) + { + /* Is the RX buffer full? */ + + if (upper) + { + /* Disable Rx interrupt to prevent more data being from + * peripheral. When hardware RTS is enabled, this will + * prevent more data from coming in. + * + * This function is only called when UART recv buffer is full, + * that is: "dev->recv.head + 1 == dev->recv.tail". + * + * Logic in "uart_read" will automatically toggle Rx interrupts + * when buffer is read empty and thus we do not have to re- + * enable Rx interrupts. + */ + + uart_disablerxint(dev); + return true; + } + + /* No.. The RX buffer is empty */ + + else + { + /* We might leave Rx interrupt disabled if full recv buffer was + * read empty. Enable Rx interrupt to make sure that more input is + * received. + */ + + uart_enablerxint(dev); + } + } +#endif + + return false; +} +#endif + +/**************************************************************************** + * Name: up_dma_receive + * + * Description: + * Called (usually) from the interrupt level to receive one + * character from the USART. Error bits associated with the + * receipt are provided in the return 'status'. + * + ****************************************************************************/ + +#ifdef SERIAL_HAVE_RXDMA +static int up_dma_receive(struct uart_dev_s *dev, unsigned int *status) +{ + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; + int c = 0; + + if (up_dma_nextrx(priv) != priv->rxdmanext) + { + c = priv->rxfifo[priv->rxdmanext]; + + priv->rxdmanext++; + if (priv->rxdmanext == RXDMA_BUFFER_SIZE) + { + priv->rxdmanext = 0; + } + } + + return c; +} +#endif + +/**************************************************************************** + * Name: up_dma_rxint + * + * Description: + * Call to enable or disable RX interrupts + * + ****************************************************************************/ + +#ifdef SERIAL_HAVE_RXDMA +static void up_dma_rxint(struct uart_dev_s *dev, bool enable) +{ + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; + + /* En/disable DMA reception. + * + * Note that it is not safe to check for available bytes and immediately + * pass them to uart_recvchars as that could potentially recurse back + * to us again. Instead, bytes must wait until the next up_dma_poll or + * DMA event. + */ + + priv->rxenable = enable; +} +#endif + +/**************************************************************************** + * Name: up_dma_rxavailable + * + * Description: + * Return true if the receive register is not empty + * + ****************************************************************************/ + +#ifdef SERIAL_HAVE_RXDMA +static bool up_dma_rxavailable(struct uart_dev_s *dev) +{ + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; + + /* Compare our receive pointer to the current DMA pointer, if they + * do not match, then there are bytes to be received. + */ + + return (up_dma_nextrx(priv) != priv->rxdmanext); +} +#endif + +/**************************************************************************** + * Name: up_dma_txcallback + * + * Description: + * This function clears dma buffer at complete of DMA transfer and wakes up + * threads waiting for space in buffer. + * + ****************************************************************************/ + +#ifdef SERIAL_HAVE_TXDMA +static void up_dma_txcallback(DMA_HANDLE handle, uint8_t status, void *arg) +{ + struct up_dev_s *priv = (struct up_dev_s *)arg; + + /* Update 'nbytes' indicating number of bytes actually transferred by DMA. + * This is important to free TX buffer space by 'uart_xmitchars_done'. + */ + + if (status & DMA_ISR_TCIF_BIT) + { + priv->dev.dmatx.nbytes += priv->dev.dmatx.length; + if (priv->dev.dmatx.nlength) + { + /* Set up DMA on next buffer */ + + stm32_dmasetup(priv->txdma, + priv->usartbase + STM32_USART_TDR_OFFSET, + (uint32_t) priv->dev.dmatx.nbuffer, + (size_t) priv->dev.dmatx.nlength, + SERIAL_TXDMA_CONTROL_WORD); + + /* Set length for the next completion */ + + priv->dev.dmatx.length = priv->dev.dmatx.nlength; + priv->dev.dmatx.nlength = 0; + + /* Start transmission with the callback on DMA completion */ + + stm32_dmastart(priv->txdma, up_dma_txcallback, + (void *)priv, false); + + return; + } + } + else if (status & DMA_ISR_HTIF_BIT) + { + priv->dev.dmatx.nbytes += priv->dev.dmatx.length / 2; + } + + /* Adjust the pointers */ + + uart_xmitchars_done(&priv->dev); +} +#endif + +/**************************************************************************** + * Name: up_dma_txavailable + * + * Description: + * Informs DMA that Tx data is available and is ready for transfer. + * + ****************************************************************************/ + +#ifdef SERIAL_HAVE_TXDMA +static void up_dma_txavailable(struct uart_dev_s *dev) +{ + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; + + /* Only send when the DMA is idle */ + + if (stm32_dmaresidual(priv->txdma) == 0) + { + uart_xmitchars_dma(dev); + } +} +#endif + +/**************************************************************************** + * Name: up_dma_send + * + * Description: + * Called (usually) from the interrupt level to start DMA transfer. + * (Re-)Configures DMA Stream updating buffer and buffer length. + * + ****************************************************************************/ + +#ifdef SERIAL_HAVE_TXDMA +static void up_dma_send(struct uart_dev_s *dev) +{ + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; + + /* We need to stop DMA before reconfiguration */ + + stm32_dmastop(priv->txdma); + + /* Reset the number sent */ + + dev->dmatx.nbytes = 0; + + /* Make use of setup function to update buffer and its length for + * next transfer + */ + + stm32_dmasetup(priv->txdma, + priv->usartbase + STM32_USART_TDR_OFFSET, + (uint32_t) dev->dmatx.buffer, + (size_t) dev->dmatx.length, + SERIAL_TXDMA_CONTROL_WORD); + + /* Start transmission with the callback on DMA completion */ + + stm32_dmastart(priv->txdma, up_dma_txcallback, (void *)priv, false); +} +#endif + +/**************************************************************************** + * Name: up_send + * + * Description: + * This method will send one byte on the USART + * + ****************************************************************************/ + +static void up_send(struct uart_dev_s *dev, int ch) +{ + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; +#ifdef HAVE_RS485 + if (priv->rs485_dir_gpio != 0) + { + stm32_gpiowrite(priv->rs485_dir_gpio, priv->rs485_dir_polarity); + } +#endif + + up_serialout(priv, STM32_USART_TDR_OFFSET, (uint32_t)ch); +} + +/**************************************************************************** + * Name: up_dma_txint + * + * Description: + * Call to enable or disable TX interrupts from the UART. + * + ****************************************************************************/ + +#ifdef SERIAL_HAVE_TXDMA +static void up_dma_txint(struct uart_dev_s *dev, bool enable) +{ + /* Nothing to do. */ + + /* In case of DMA transfer we do not want to make use of UART interrupts. + * Instead, we use DMA interrupts that are activated once during boot + * sequence. Furthermore we can use up_dma_txcallback() to handle staff at + * half DMA transfer or after transfer completion (depending configuration, + * see stm32_dmastart(...) ). + */ +} +#endif + +/**************************************************************************** + * Name: up_txint + * + * Description: + * Call to enable or disable TX interrupts + * + ****************************************************************************/ + +#if defined(SERIAL_HAVE_RXDMA_OPS) || defined(SERIAL_HAVE_NODMA_OPS) || \ + defined(CONFIG_STM32_SERIALBRK_BSDCOMPAT) +static void up_txint(struct uart_dev_s *dev, bool enable) +{ + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; + irqstate_t flags; + + /* USART transmit interrupts: + * + * Enable Status Meaning Usage + * ------------------ --------------- ----------------------- ---------- + * USART_CR1_TCIE USART_SR_TC Tx Complete (RS-485) + * USART_CR1_TXEIE USART_SR_TXE Tx Data Register Empty + * USART_CR3_CTSIE USART_SR_CTS CTS flag (not used) + */ + + flags = enter_critical_section(); + if (enable) + { + /* Set to receive an interrupt when the TX data register is empty */ + +#ifndef CONFIG_SUPPRESS_SERIAL_INTS + uint16_t ie = priv->ie | USART_CR1_TXEIE; + + /* If RS-485 is supported on this U[S]ART, then also enable the + * transmission complete interrupt. + */ + +# ifdef HAVE_RS485 + if (priv->rs485_dir_gpio != 0) + { + ie |= USART_CR1_TCIE; + } +# endif + +# ifdef CONFIG_STM32_SERIALBRK_BSDCOMPAT + if (priv->ie & USART_CR1_IE_BREAK_INPROGRESS) + { + leave_critical_section(flags); + return; + } +# endif + + up_restoreusartint(priv, ie); + +#else + /* Fake a TX interrupt here by just calling uart_xmitchars() with + * interrupts disabled (note this may recurse). + */ + + uart_xmitchars(dev); +#endif + } + else + { + /* Disable the TX interrupt */ + + up_restoreusartint(priv, priv->ie & ~USART_CR1_TXEIE); + } + + leave_critical_section(flags); +} +#endif + +/**************************************************************************** + * Name: up_txready + * + * Description: + * Return true if the transmit data register is empty + * + ****************************************************************************/ + +static bool up_txready(struct uart_dev_s *dev) +{ + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; + return ((up_serialin(priv, STM32_USART_SR_OFFSET) & USART_SR_TXE) != 0); +} + +/**************************************************************************** + * Name: up_dma_rxcallback + * + * Description: + * This function checks the current DMA state and calls the generic + * serial stack when bytes appear to be available. + * + ****************************************************************************/ + +#ifdef SERIAL_HAVE_RXDMA +static void up_dma_rxcallback(DMA_HANDLE handle, uint8_t status, void *arg) +{ + struct up_dev_s *priv = (struct up_dev_s *)arg; + + if (priv->rxenable && up_dma_rxavailable(&priv->dev)) + { + uart_recvchars(&priv->dev); + } +} +#endif + +/**************************************************************************** + * Name: up_pm_notify + * + * Description: + * Notify the driver of new power state. This callback is called after + * all drivers have had the opportunity to prepare for the new power state. + * + * Input Parameters: + * + * cb - Returned to the driver. The driver version of the callback + * structure may include additional, driver-specific state data at + * the end of the structure. + * + * pmstate - Identifies the new PM state + * + * Returned Value: + * None - The driver already agreed to transition to the low power + * consumption state when when it returned OK to the prepare() call. + * + * + ****************************************************************************/ + +#ifdef CONFIG_PM +static void up_pm_notify(struct pm_callback_s *cb, int domain, + enum pm_state_e pmstate) +{ + switch (pmstate) + { + case (PM_NORMAL): + { + /* Logic for PM_NORMAL goes here */ + } + break; + + case (PM_IDLE): + { + /* Logic for PM_IDLE goes here */ + } + break; + + case (PM_STANDBY): + { + /* Logic for PM_STANDBY goes here */ + } + break; + + case (PM_SLEEP): + { + /* Logic for PM_SLEEP goes here */ + } + break; + + default: + { + /* Should not get here */ + } + break; + } +} +#endif + +/**************************************************************************** + * Name: up_pm_prepare + * + * Description: + * Request the driver to prepare for a new power state. This is a warning + * that the system is about to enter into a new power state. The driver + * should begin whatever operations that may be required to enter power + * state. The driver may abort the state change mode by returning a + * non-zero value from the callback function. + * + * Input Parameters: + * + * cb - Returned to the driver. The driver version of the callback + * structure may include additional, driver-specific state data at + * the end of the structure. + * + * pmstate - Identifies the new PM state + * + * Returned Value: + * Zero - (OK) means the event was successfully processed and that the + * driver is prepared for the PM state change. + * + * Non-zero - means that the driver is not prepared to perform the tasks + * needed achieve this power setting and will cause the state + * change to be aborted. NOTE: The prepare() method will also + * be called when reverting from lower back to higher power + * consumption modes (say because another driver refused a + * lower power state change). Drivers are not permitted to + * return non-zero values when reverting back to higher power + * consumption modes! + * + * + ****************************************************************************/ + +#ifdef CONFIG_PM +static int up_pm_prepare(struct pm_callback_s *cb, int domain, + enum pm_state_e pmstate) +{ + /* Logic to prepare for a reduced power state goes here. */ + + return OK; +} +#endif +#endif /* HAVE_SERIALDRIVER */ +#endif /* USE_SERIALDRIVER */ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +#ifdef USE_SERIALDRIVER + +/**************************************************************************** + * Name: stm32_serial_get_uart + * + * Description: + * Get serial driver structure for STM32 USART + * + ****************************************************************************/ + +#ifdef HAVE_SERIALDRIVER +uart_dev_t *stm32_serial_get_uart(int uart_num) +{ + int uart_idx = uart_num - 1; + + if (uart_idx < 0 || uart_idx >= STM32_NUSART || !g_uart_devs[uart_idx]) + { + return NULL; + } + + if (!g_uart_devs[uart_idx]->initialized) + { + return NULL; + } + + return &g_uart_devs[uart_idx]->dev; +} +#endif /* HAVE_SERIALDRIVER */ + +/**************************************************************************** + * Name: arm_earlyserialinit + * + * Description: + * Performs the low level USART initialization early in debug so that the + * serial console will be available during boot up. This must be called + * before arm_serialinit. + * + ****************************************************************************/ + +#ifdef USE_EARLYSERIALINIT +void arm_earlyserialinit(void) +{ +#ifdef HAVE_SERIALDRIVER + unsigned i; + + /* Disable all USART interrupts */ + + for (i = 0; i < STM32_NUSART; i++) + { + if (g_uart_devs[i]) + { + up_disableusartint(g_uart_devs[i], NULL); + } + } + + for (i = 0; i < STM32_NLPUART; i++) + { + if (g_lpuart_devs[i]) + { + up_disableusartint(g_lpuart_devs[i], NULL); + } + } + + /* Configure whichever one is the console */ + +#if CONSOLE_UART > 0 + up_setup(&g_uart_devs[CONSOLE_UART - 1]->dev); +#elif CONSOLE_LPUART > 0 + up_setup(&g_lpuart_devs[CONSOLE_LPUART - 1]->dev); +#endif +#endif /* HAVE_UART */ +} +#endif + +/**************************************************************************** + * Name: arm_serialinit + * + * Description: + * Register serial console and serial ports. This assumes + * that arm_earlyserialinit was called previously. + * + ****************************************************************************/ + +void arm_serialinit(void) +{ +#ifdef HAVE_SERIALDRIVER + char devname[16]; + unsigned i; + unsigned minor = 0; +#ifdef CONFIG_PM + int ret; +#endif + + /* Register to receive power management callbacks */ + +#ifdef CONFIG_PM + ret = pm_register(&g_serialcb); + DEBUGASSERT(ret == OK); + UNUSED(ret); +#endif + + /* Register the console */ + +#if CONSOLE_UART > 0 + struct uart_dev_s *dev = &g_uart_devs[CONSOLE_UART - 1]->dev; +#elif CONSOLE_LPUART > 0 + struct uart_dev_s *dev = &g_lpuart_devs[CONSOLE_LPUART - 1]->dev; +#endif + +#if CONSOLE_UART > 0 || CONSOLE_LPUART > 0 + uart_register("/dev/console", dev); + +#ifndef CONFIG_STM32_SERIAL_DISABLE_REORDERING + /* If not disabled, register the console UART to ttyS0 and exclude + * it from initializing it further down + */ + + uart_register("/dev/ttyS0", dev); + minor = 1; +#endif + +#if defined(SERIAL_HAVE_CONSOLE_RXDMA) || defined(SERIAL_HAVE_CONSOLE_TXDMA) + /* If we need to re-initialise the console to enable DMA do that here. */ + + up_dma_setup(dev); +#endif +#endif /* CONSOLE_UART > 0 || CONSOLE_LPUART > 0 */ + + /* Register all remaining USARTs */ + + strlcpy(devname, "/dev/ttySx", sizeof(devname)); + + for (i = 0; i < STM32_NUSART; i++) + { + /* Don't create a device for non-configured ports. */ + + if (g_uart_devs[i] == 0) + { + continue; + } + +#ifndef CONFIG_STM32_SERIAL_DISABLE_REORDERING + /* Don't create a device for the console - we did that above */ + + if (g_uart_devs[i]->dev.isconsole) + { + continue; + } +#endif + + /* Register USARTs as devices in increasing order */ + + devname[9] = '0' + minor++; + uart_register(devname, &g_uart_devs[i]->dev); + } + + for (i = 0; i < STM32_NLPUART; i++) + { + /* Don't create a device for non-configured ports. */ + + if (g_lpuart_devs[i] == 0) + { + continue; + } + +#ifndef CONFIG_STM32_SERIAL_DISABLE_REORDERING + /* Don't create a device for the console - we did that above */ + + if (g_lpuart_devs[i]->dev.isconsole) + { + continue; + } +#endif + + /* Register USARTs as devices in increasing order */ + + devname[9] = '0' + minor++; + uart_register(devname, &g_lpuart_devs[i]->dev); + } + +#endif /* HAVE UART */ +} + +/**************************************************************************** + * Name: stm32_serial_dma_poll + * + * Description: + * Checks receive DMA buffers for received bytes that have not accumulated + * to the point where the DMA half/full interrupt has triggered. + * + * This function should be called from a timer or other periodic context. + * + ****************************************************************************/ + +#ifdef SERIAL_HAVE_RXDMA +void stm32_serial_dma_poll(void) +{ + irqstate_t flags; + + flags = enter_critical_section(); + +#ifdef CONFIG_USART1_RXDMA + if (g_usart1priv.rxdma != NULL) + { + up_dma_rxcallback(g_usart1priv.rxdma, 0, &g_usart1priv); + } +#endif + +#ifdef CONFIG_USART2_RXDMA + if (g_usart2priv.rxdma != NULL) + { + up_dma_rxcallback(g_usart2priv.rxdma, 0, &g_usart2priv); + } +#endif + +#ifdef CONFIG_USART3_RXDMA + if (g_usart3priv.rxdma != NULL) + { + up_dma_rxcallback(g_usart3priv.rxdma, 0, &g_usart3priv); + } +#endif + +#ifdef CONFIG_UART4_RXDMA + if (g_uart4priv.rxdma != NULL) + { + up_dma_rxcallback(g_uart4priv.rxdma, 0, &g_uart4priv); + } +#endif + +#ifdef CONFIG_UART5_RXDMA + if (g_uart5priv.rxdma != NULL) + { + up_dma_rxcallback(g_uart5priv.rxdma, 0, &g_uart5priv); + } +#endif + +#ifdef CONFIG_USART6_RXDMA + if (g_usart6priv.rxdma != NULL) + { + up_dma_rxcallback(g_usart6priv.rxdma, 0, &g_usart6priv); + } +#endif + +#ifdef CONFIG_UART7_RXDMA + if (g_uart7priv.rxdma != NULL) + { + up_dma_rxcallback(g_uart7priv.rxdma, 0, &g_uart7priv); + } +#endif + +#ifdef CONFIG_UART8_RXDMA + if (g_uart8priv.rxdma != NULL) + { + up_dma_rxcallback(g_uart8priv.rxdma, 0, &g_uart8priv); + } +#endif + +#ifdef CONFIG_LPUART1_RXDMA + if (g_lpuart1priv.rxdma != NULL) + { + up_dma_rxcallback(g_lpuart1priv.rxdma, 0, &g_lpuart1priv); + } +#endif + + leave_critical_section(flags); +} +#endif + +/**************************************************************************** + * Name: up_putc + * + * Description: + * Provide priority, low-level access to support OS debug writes + * + ****************************************************************************/ + +#ifndef CONFIG_ARM_SEMIHOSTING_SYSLOG +void up_putc(int ch) +{ +#if CONSOLE_UART > 0 + struct up_dev_s *priv = g_uart_devs[CONSOLE_UART - 1]; +#elif CONSOLE_LPUART > 0 + struct up_dev_s *priv = g_lpuart_devs[CONSOLE_LPUART - 1]; +#endif + +#if CONSOLE_UART > 0 || CONSOLE_LPUART > 0 + uint16_t ie; + + up_disableusartint(priv, &ie); + arm_lowputc(ch); + up_restoreusartint(priv, ie); +#endif +} +#endif + +#else /* USE_SERIALDRIVER */ + +/**************************************************************************** + * Name: up_putc + * + * Description: + * Provide priority, low-level access to support OS debug writes + * + ****************************************************************************/ + +#ifndef CONFIG_ARM_SEMIHOSTING_SYSLOG +void up_putc(int ch) +{ +#if CONSOLE_UART > 0 || CONSOLE_LPUART > 0 + arm_lowputc(ch); +#endif +} +#endif + +#endif /* USE_SERIALDRIVER */ diff --git a/arch/arm/src/common/stm32/stm32_spi.h b/arch/arm/src/common/stm32/stm32_spi.h new file mode 100644 index 0000000000000..9e861bcc69025 --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_spi.h @@ -0,0 +1,216 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_spi.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_SPI_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_SPI_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#if !(defined(CONFIG_STM32_HAVE_IP_SPI_V1) || \ + defined(CONFIG_STM32_HAVE_IP_SPI_V2) || \ + defined(CONFIG_STM32_HAVE_IP_SPI_V3) || \ + defined(CONFIG_STM32_HAVE_IP_SPI_V4)) +# error "Unsupported STM32 SPI" +#endif + +#include + +#include "chip.h" +#include "hardware/stm32_spi.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +struct spi_dev_s; + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_spibus_initialize + * + * Description: + * Initialize the selected SPI bus + * + * Input Parameters: + * bus number (for hardware that has multiple SPI interfaces) + * + * Returned Value: + * Valid SPI device structure reference on success; a NULL on failure + * + ****************************************************************************/ + +struct spi_dev_s *stm32_spibus_initialize(int bus); + +/**************************************************************************** + * Name: stm32_spi1/2/...select and stm32_spi1/2/...status + * + * Description: + * The external functions, stm32_spi1/2/...select, stm32_spi1/2/...status, + * and stm32_spi1/2/...cmddata must be provided by board-specific logic. + * These are implementations of the select, status, and cmddata methods of + * the SPI interface defined by struct spi_ops_s (see + * include/nuttx/spi/spi.h). All other methods (including + * stm32_spibus_initialize()) are provided by common STM32 logic. To use + * this common SPI logic on your board: + * + * 1. Provide logic in stm32_boardinitialize() to configure SPI chip + * select pins. + * 2. Provide stm32_spi1/2/...select() and stm32_spi1/2/...status() + * functions in your board-specific logic. These functions will + * perform chip selection and status operations using GPIOs in the way + * your board is configured. + * 3. If CONFIG_SPI_CMDDATA is defined in your NuttX configuration file, + * then provide stm32_spi1/2/...cmddata() functions in your board- + * specific logic. These functions will perform cmd/data selection + * operations using GPIOs in the way your board is configured. + * 4. Add a calls to stm32_spibus_initialize() in your low level + * application initialization logic + * 5. The handle returned by stm32_spibus_initialize() may then be used to + * bind the SPI driver to higher level logic (e.g., calling + * mmcsd_spislotinitialize(), for example, will bind the SPI driver to + * the SPI MMC/SD driver). + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_SPI1 +void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, + bool selected); +uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid); +int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); +#endif + +#ifdef CONFIG_STM32_SPI2 +void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid, + bool selected); +uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid); +int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); +#endif + +#ifdef CONFIG_STM32_SPI3 +void stm32_spi3select(struct spi_dev_s *dev, uint32_t devid, + bool selected); +uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid); +int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); +#endif + +#ifdef CONFIG_STM32_SPI4 +void stm32_spi4select(struct spi_dev_s *dev, uint32_t devid, + bool selected); +uint8_t stm32_spi4status(struct spi_dev_s *dev, uint32_t devid); +int stm32_spi4cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); +#endif + +#ifdef CONFIG_STM32_SPI5 +void stm32_spi5select(struct spi_dev_s *dev, uint32_t devid, + bool selected); +uint8_t stm32_spi5status(struct spi_dev_s *dev, uint32_t devid); +int stm32_spi5cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); +#endif + +#ifdef CONFIG_STM32_SPI6 +void stm32_spi6select(struct spi_dev_s *dev, uint32_t devid, + bool selected); +uint8_t stm32_spi6status(struct spi_dev_s *dev, uint32_t devid); +int stm32_spi6cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); +#endif + +/**************************************************************************** + * Name: stm32_spi1/2/...register + * + * Description: + * If the board supports a card detect callback to inform the SPI-based + * MMC/SD driver when an SD card is inserted or removed, then + * CONFIG_SPI_CALLBACK should be defined and the following function(s) + * must be implemented. These functions implements the registercallback + * method of the SPI interface (see include/nuttx/spi/spi.h for details) + * + * Input Parameters: + * dev - Device-specific state data + * callback - The function to call on the media change + * arg - A caller provided value to return with the callback + * + * Returned Value: + * 0 on success; negated errno on failure. + * + ****************************************************************************/ + +#ifdef CONFIG_SPI_CALLBACK +#ifdef CONFIG_STM32_SPI1 +int stm32_spi1register(struct spi_dev_s *dev, spi_mediachange_t callback, + void *arg); +#endif + +#ifdef CONFIG_STM32_SPI2 +int stm32_spi2register(struct spi_dev_s *dev, spi_mediachange_t callback, + void *arg); +#endif + +#ifdef CONFIG_STM32_SPI3 +int stm32_spi3register(struct spi_dev_s *dev, spi_mediachange_t callback, + void *arg); +#endif + +#ifdef CONFIG_STM32_SPI4 +int stm32_spi4register(struct spi_dev_s *dev, spi_mediachange_t callback, + void *arg); +#endif + +#ifdef CONFIG_STM32_SPI5 +int stm32_spi5register(struct spi_dev_s *dev, spi_mediachange_t callback, + void *arg); +#endif + +#ifdef CONFIG_STM32_SPI6 +int stm32_spi6register(struct spi_dev_s *dev, spi_mediachange_t callback, + void *arg); +#endif +#endif + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_SPI_H */ diff --git a/arch/arm/src/common/stm32/stm32_spi_m0_v1.c b/arch/arm/src/common/stm32/stm32_spi_m0_v1.c new file mode 100644 index 0000000000000..9b32cd490f5b0 --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_spi_m0_v1.c @@ -0,0 +1,2134 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_spi_m0_v1.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status must + * be provided by board-specific logic. They are implementations of the + * select and status methods of the SPI interface defined by + * struct spi_ops_s (see include/nuttx/spi/spi.h). All other methods + * (including stm32_spibus_initialize()) are provided by common STM32 logic. + * To use this common SPI logic on your board: + * + * 1. Provide logic in stm32_board_initialize() to configure SPI chip + * select pins. + * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() functions + * in your board-specific logic. These functions will perform chip + * selection and status operations using GPIOs in the way your board is + * configured. + * 3. Add a calls to stm32_spibus_initialize() in your low level + * application initialization logic + * 4. The handle returned by stm32_spibus_initialize() may then be used to + * bind the SPI driver to higher level logic (e.g., calling + * mmcsd_spislotinitialize(), for example, will bind the SPI driver to + * the SPI MMC/SD driver). + * + ****************************************************************************/ + +/* This driver is ported from the stm32 one, which only supports 8 and 16 + * bits transfers. The STM32 family supports frame size from 4 to 16 bits, + * but we do not support that yet. For the moment, we replace uses of the + * CR1_DFF bit with a check of the CR2_DS[0..3] bits. If the value is + * SPI_CR2_DS_16BIT it means 16 bits, else 8 bits. + */ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#include "arm_internal.h" +#include "chip.h" +#include "stm32.h" +#include "stm32_gpio.h" +#include "stm32_dma.h" +#include "stm32_spi.h" + +#include + +#ifdef CONFIG_STM32_SPI + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* SPI interrupts */ + +#ifdef CONFIG_STM32_SPI_INTERRUPTS +# error "Interrupt driven SPI not yet supported" +#endif + +/* Can't have both interrupt driven SPI and SPI DMA */ + +#if defined(CONFIG_STM32_SPI_INTERRUPTS) && defined(CONFIG_STM32_SPI_DMA) +# error "Cannot enable both interrupt mode and DMA mode for SPI" +#endif + +/* SPI DMA priority */ + +#ifdef CONFIG_STM32_SPI_DMA + +# if defined(CONFIG_SPI_DMAPRIO) +# define SPI_DMA_PRIO CONFIG_SPI_DMAPRIO +# else +# define SPI_DMA_PRIO DMA_CCR_PRIMED +# endif + +# if (SPI_DMA_PRIO & ~DMA_CCR_PL_MASK) != 0 +# error "Illegal value for CONFIG_SPI_DMAPRIO" +# endif + +#endif + +/* DMA channel configuration */ + +#define SPI_RXDMA16_CONFIG (SPI_DMA_PRIO|DMA_CCR_MSIZE_16BITS|DMA_CCR_PSIZE_16BITS|DMA_CCR_MINC ) +#define SPI_RXDMA8_CONFIG (SPI_DMA_PRIO|DMA_CCR_MSIZE_8BITS |DMA_CCR_PSIZE_8BITS |DMA_CCR_MINC ) +#define SPI_RXDMA16NULL_CONFIG (SPI_DMA_PRIO|DMA_CCR_MSIZE_8BITS |DMA_CCR_PSIZE_16BITS ) +#define SPI_RXDMA8NULL_CONFIG (SPI_DMA_PRIO|DMA_CCR_MSIZE_8BITS |DMA_CCR_PSIZE_8BITS ) +#define SPI_TXDMA16_CONFIG (SPI_DMA_PRIO|DMA_CCR_MSIZE_16BITS|DMA_CCR_PSIZE_16BITS|DMA_CCR_MINC|DMA_CCR_DIR) +#define SPI_TXDMA8_CONFIG (SPI_DMA_PRIO|DMA_CCR_MSIZE_8BITS |DMA_CCR_PSIZE_8BITS |DMA_CCR_MINC|DMA_CCR_DIR) +#define SPI_TXDMA16NULL_CONFIG (SPI_DMA_PRIO|DMA_CCR_MSIZE_8BITS |DMA_CCR_PSIZE_16BITS |DMA_CCR_DIR) +#define SPI_TXDMA8NULL_CONFIG (SPI_DMA_PRIO|DMA_CCR_MSIZE_8BITS |DMA_CCR_PSIZE_8BITS |DMA_CCR_DIR) + +/* SPI clocks */ + +#if defined(CONFIG_STM32_STM32F0) || defined(CONFIG_STM32_STM32L0) +# define SPI1_PCLK_FREQUENCY STM32_PCLK2_FREQUENCY +# define SPI2_PCLK_FREQUENCY STM32_PCLK1_FREQUENCY +#elif defined(CONFIG_STM32_STM32G0) +# define SPI1_PCLK_FREQUENCY STM32_PCLK1_FREQUENCY +# define SPI2_PCLK_FREQUENCY STM32_PCLK1_FREQUENCY +# define SPI3_PCLK_FREQUENCY STM32_PCLK1_FREQUENCY +#else +# error Unsupported family +#endif + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +enum spi_config_e +{ + FULL_DUPLEX = 0, + SIMPLEX_TX, + SIMPLEX_RX, + HALF_DUPLEX +}; + +struct stm32_spidev_s +{ + struct spi_dev_s spidev; /* Externally visible part of the SPI interface */ + uint32_t spibase; /* SPIn base address */ + uint32_t spiclock; /* Clocking for the SPI module */ +#ifdef CONFIG_STM32_SPI_INTERRUPTS + uint8_t spiirq; /* SPI IRQ number */ +#endif +#ifdef CONFIG_STM32_SPI_DMA + volatile uint8_t rxresult; /* Result of the RX DMA */ + volatile uint8_t txresult; /* Result of the RX DMA */ +#ifdef CONFIG_SPI_TRIGGER + bool defertrig; /* Flag indicating that trigger should be deferred */ + bool trigarmed; /* Flag indicating that the trigger is armed */ +#endif + uint16_t rxch; /* The RX DMA channel number */ + uint16_t txch; /* The TX DMA channel number */ + DMA_HANDLE rxdma; /* DMA channel handle for RX transfers */ + DMA_HANDLE txdma; /* DMA channel handle for TX transfers */ + sem_t rxsem; /* Wait for RX DMA to complete */ + sem_t txsem; /* Wait for TX DMA to complete */ + uint32_t txccr; /* DMA control register for TX transfers */ + uint32_t rxccr; /* DMA control register for RX transfers */ +#endif + bool initialized; /* Has SPI interface been initialized */ + mutex_t lock; /* Held while chip is selected for mutual exclusion */ + uint32_t frequency; /* Requested clock frequency */ + uint32_t actual; /* Actual clock frequency */ + uint8_t nbits; /* Width of word in bits (4 through 16) */ + uint8_t mode; /* Mode 0,1,2,3 */ +#ifdef CONFIG_PM + struct pm_callback_s pm_cb; /* PM callbacks */ +#endif + enum spi_config_e config; /* full/half duplex, simplex transmit/read only */ + bool rx_now; /* Half duplex only: receiving data now */ + bool rx_mode; /* Half duplex only: SPI_CR1_BIDIOE bit status */ +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/* Helpers */ + +static inline uint16_t spi_getreg(struct stm32_spidev_s *priv, + uint8_t offset); +static inline void spi_putreg(struct stm32_spidev_s *priv, + uint8_t offset, uint16_t value); +static inline void spi_rx_mode(struct stm32_spidev_s *priv, bool enable); +static inline uint16_t spi_readword(struct stm32_spidev_s *priv); +static inline void spi_writeword(struct stm32_spidev_s *priv, + uint16_t byte); +static inline bool spi_16bitmode(struct stm32_spidev_s *priv); + +static void spi_modifycr(uint32_t addr, struct stm32_spidev_s *priv, + uint16_t setbits, uint16_t clrbits); + +/* DMA support */ + +#ifdef CONFIG_STM32_SPI_DMA +static int spi_dmarxwait(struct stm32_spidev_s *priv); +static int spi_dmatxwait(struct stm32_spidev_s *priv); +static inline void spi_dmarxwakeup(struct stm32_spidev_s *priv); +static inline void spi_dmatxwakeup(struct stm32_spidev_s *priv); +static void spi_dmarxcallback(DMA_HANDLE handle, uint8_t isr, + void *arg); +static void spi_dmatxcallback(DMA_HANDLE handle, uint8_t isr, + void *arg); +static void spi_dmarxsetup(struct stm32_spidev_s *priv, + void *rxbuffer, void *rxdummy, + size_t nwords); +static void spi_dmatxsetup(struct stm32_spidev_s *priv, + const void *txbuffer, + const void *txdummy, size_t nwords); +static inline void spi_dmarxstart(struct stm32_spidev_s *priv); +static inline void spi_dmatxstart(struct stm32_spidev_s *priv); +#endif + +/* SPI methods */ + +static int spi_lock(struct spi_dev_s *dev, bool lock); +static uint32_t spi_setfrequency(struct spi_dev_s *dev, + uint32_t frequency); +static void spi_setmode(struct spi_dev_s *dev, + enum spi_mode_e mode); +static void spi_setbits(struct spi_dev_s *dev, int nbits); +#ifdef CONFIG_SPI_HWFEATURES +static int spi_hwfeatures(struct spi_dev_s *dev, + spi_hwfeatures_t features); +#endif +static uint32_t spi_send(struct spi_dev_s *dev, uint32_t wd); +static void spi_exchange(struct spi_dev_s *dev, + const void *txbuffer, void *rxbuffer, + size_t nwords); + +#ifdef CONFIG_STM32_SPI_DMA +static void spi_exchange_nodma(struct spi_dev_s *dev, + const void *txbuffer, void *rxbuffer, + size_t nwords); +#endif + +#ifdef CONFIG_SPI_TRIGGER +static int spi_trigger(struct spi_dev_s *dev); +#endif +#ifndef CONFIG_SPI_EXCHANGE +static void spi_sndblock(struct spi_dev_s *dev, + const void *txbuffer, size_t nwords); +static void spi_recvblock(struct spi_dev_s *dev, + void *rxbuffer, size_t nwords); +#endif + +/* Initialization */ + +static void spi_bus_initialize(struct stm32_spidev_s *priv); + +/* PM interface */ + +#ifdef CONFIG_PM +static int spi_pm_prepare(struct pm_callback_s *cb, int domain, + enum pm_state_e pmstate); +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#ifdef CONFIG_STM32_SPI1 +static const struct spi_ops_s g_spi1ops = +{ + .lock = spi_lock, + .select = stm32_spi1select, + .setfrequency = spi_setfrequency, + .setmode = spi_setmode, + .setbits = spi_setbits, +#ifdef CONFIG_SPI_HWFEATURES + .hwfeatures = spi_hwfeatures, +#endif + .status = stm32_spi1status, +#ifdef CONFIG_SPI_CMDDATA + .cmddata = stm32_spi1cmddata, +#endif + .send = spi_send, +#ifdef CONFIG_SPI_EXCHANGE + .exchange = spi_exchange, +#else + .sndblock = spi_sndblock, + .recvblock = spi_recvblock, +#endif +#ifdef CONFIG_SPI_TRIGGER + .trigger = spi_trigger, +#endif +#ifdef CONFIG_SPI_CALLBACK + .registercallback = stm32_spi1register, /* Provided externally */ +#else + .registercallback = 0, /* Not implemented */ +#endif +}; + +static struct stm32_spidev_s g_spi1dev = +{ + .spidev = + { + .ops = &g_spi1ops, + }, + .spibase = STM32_SPI1_BASE, + .spiclock = SPI1_PCLK_FREQUENCY, +#ifdef CONFIG_STM32_SPI_INTERRUPTS + .spiirq = STM32_IRQ_SPI1, +#endif +#ifdef CONFIG_STM32_SPI1_DMA + /* lines must be configured in board.h */ + + .rxch = DMACHAN_SPI1_RX, + .txch = DMACHAN_SPI1_TX, + .rxsem = SEM_INITIALIZER(0), + .txsem = SEM_INITIALIZER(0), +#endif + .lock = NXMUTEX_INITIALIZER, +#ifdef CONFIG_PM + .pm_cb.prepare = spi_pm_prepare, +#endif + .config = CONFIG_STM32_SPI1_COMMTYPE, +}; +#endif + +#ifdef CONFIG_STM32_SPI2 +static const struct spi_ops_s g_spi2ops = +{ + .lock = spi_lock, + .select = stm32_spi2select, + .setfrequency = spi_setfrequency, + .setmode = spi_setmode, + .setbits = spi_setbits, +#ifdef CONFIG_SPI_HWFEATURES + .hwfeatures = spi_hwfeatures, +#endif + .status = stm32_spi2status, +#ifdef CONFIG_SPI_CMDDATA + .cmddata = stm32_spi2cmddata, +#endif + .send = spi_send, +#ifdef CONFIG_SPI_EXCHANGE + .exchange = spi_exchange, +#else + .sndblock = spi_sndblock, + .recvblock = spi_recvblock, +#endif +#ifdef CONFIG_SPI_TRIGGER + .trigger = spi_trigger, +#endif +#ifdef CONFIG_SPI_CALLBACK + .registercallback = stm32_spi2register, /* provided externally */ +#else + .registercallback = 0, /* not implemented */ +#endif +}; + +static struct stm32_spidev_s g_spi2dev = +{ + .spidev = + { + .ops = &g_spi2ops, + }, + .spibase = STM32_SPI2_BASE, + .spiclock = SPI1_PCLK_FREQUENCY, +#ifdef CONFIG_STM32_SPI_INTERRUPTS + .spiirq = STM32_IRQ_SPI2, +#endif +#ifdef CONFIG_STM32_SPI2_DMA + .rxch = DMACHAN_SPI2_RX, + .txch = DMACHAN_SPI2_TX, + .rxsem = SEM_INITIALIZER(0), + .txsem = SEM_INITIALIZER(0), +#endif + .lock = NXMUTEX_INITIALIZER, +#ifdef CONFIG_PM + .pm_cb.prepare = spi_pm_prepare, +#endif + .config = CONFIG_STM32_SPI2_COMMTYPE, +}; +#endif + +#ifdef CONFIG_STM32_SPI3 +static const struct spi_ops_s g_spi3ops = +{ + .lock = spi_lock, + .select = stm32_spi3select, + .setfrequency = spi_setfrequency, + .setmode = spi_setmode, + .setbits = spi_setbits, +#ifdef CONFIG_SPI_HWFEATURES + .hwfeatures = spi_hwfeatures, +#endif + .status = stm32_spi3status, +#ifdef CONFIG_SPI_CMDDATA + .cmddata = stm32_spi3cmddata, +#endif + .send = spi_send, +#ifdef CONFIG_SPI_EXCHANGE + .exchange = spi_exchange, +#else + .sndblock = spi_sndblock, + .recvblock = spi_recvblock, +#endif +#ifdef CONFIG_SPI_TRIGGER + .trigger = spi_trigger, +#endif +#ifdef CONFIG_SPI_CALLBACK + .registercallback = stm32_spi3register, /* provided externally */ +#else + .registercallback = 0, /* not implemented */ +#endif +}; + +static struct stm32_spidev_s g_spi3dev = +{ + .spidev = + { + .ops = &g_spi3ops, + }, + .spibase = STM32_SPI3_BASE, + .spiclock = SPI1_PCLK_FREQUENCY, +#ifdef CONFIG_STM32_SPI_INTERRUPTS + .spiirq = STM32_IRQ_SPI3, +#endif +#ifdef CONFIG_STM32_SPI3_DMA + .rxch = DMACHAN_SPI3_RX, + .txch = DMACHAN_SPI3_TX, + .rxsem = SEM_INITIALIZER(0), + .txsem = SEM_INITIALIZER(0), +#endif + .lock = NXMUTEX_INITIALIZER, +#ifdef CONFIG_PM + .pm_cb.prepare = spi_pm_prepare, +#endif + .config = CONFIG_STM32_SPI3_COMMTYPE, +}; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: spi_getreg + * + * Description: + * Get the contents of the SPI register at offset + * + * Input Parameters: + * priv - private SPI device structure + * offset - offset to the register of interest + * + * Returned Value: + * The contents of the 16-bit register + * + ****************************************************************************/ + +static inline uint16_t spi_getreg(struct stm32_spidev_s *priv, + uint8_t offset) +{ + return getreg16(priv->spibase + offset); +} + +/**************************************************************************** + * Name: spi_putreg + * + * Description: + * Write a 16-bit value to the SPI register at offset + * + * Input Parameters: + * priv - private SPI device structure + * offset - offset to the register of interest + * value - the 16-bit value to be written + * + * Returned Value: + * The contents of the 16-bit register + * + ****************************************************************************/ + +static inline void spi_putreg(struct stm32_spidev_s *priv, + uint8_t offset, uint16_t value) +{ + putreg16(value, priv->spibase + offset); +} + +/**************************************************************************** + * Name: spi_rx_mode + * + * Description: + * Activate SPI RX or SPI TX for the half-duplex mode + * + ****************************************************************************/ + +static inline void spi_rx_mode(struct stm32_spidev_s *priv, bool enable) +{ + if (enable) + { + /* Enable RX */ + + if (!priv->rx_mode) + { + /* Disable SPI */ + + spi_modifycr(STM32_SPI_CR1_OFFSET, priv, 0, SPI_CR1_SPE); + + /* Disable output for half-duplex mode - SPI starts to + * automatically output clocks. + */ + + spi_modifycr(STM32_SPI_CR1_OFFSET, priv, 0, SPI_CR1_BIDIOE); + + /* Enable SPI */ + + spi_modifycr(STM32_SPI_CR1_OFFSET, priv, SPI_CR1_SPE, 0); + + priv->rx_mode = true; + } + } + else + { + /* Enable TX */ + + if (priv->rx_mode) + { + /* Disable SPI */ + + spi_modifycr(STM32_SPI_CR1_OFFSET, priv, 0, SPI_CR1_SPE); + + /* Enable TX output */ + + spi_modifycr(STM32_SPI_CR1_OFFSET, priv, SPI_CR1_BIDIOE, 0); + + /* Enable SPI */ + + spi_modifycr(STM32_SPI_CR1_OFFSET, priv, SPI_CR1_SPE, 0); + + priv->rx_mode = false; + } + } +} + +/**************************************************************************** + * Name: spi_getreg8 + * + * Description: + * Get the contents of the SPI register at offset + * + * Input Parameters: + * priv - private SPI device structure + * offset - offset to the register of interest + * + * Returned Value: + * The contents of the 8-bit register + * + ****************************************************************************/ + +#ifdef HAVE_IP_SPI_V2 +static inline uint8_t spi_getreg8(struct stm32_spidev_s *priv, + uint8_t offset) +{ + return getreg8(priv->spibase + offset); +} +#endif + +/**************************************************************************** + * Name: spi_putreg8 + * + * Description: + * Write a 8-bit value to the SPI register at offset + * + * Input Parameters: + * priv - private SPI device structure + * offset - offset to the register of interest + * value - the 8-bit value to be written + * + ****************************************************************************/ + +#ifdef HAVE_IP_SPI_V2 +static inline void spi_putreg8(struct stm32_spidev_s *priv, + uint8_t offset, uint8_t value) +{ + putreg8(value, priv->spibase + offset); +} +#endif + +/**************************************************************************** + * Name: spi_readword + * + * Description: + * Read one word (TWO bytes!) from SPI + * + * Input Parameters: + * priv - Device-specific state data + * + * Returned Value: + * Word as read + * + ****************************************************************************/ + +static inline uint16_t spi_readword(struct stm32_spidev_s *priv) +{ + /* Can't receive in tx only mode */ + + if (priv->config == SIMPLEX_TX) + { + return 0; + } + + if (priv->config == HALF_DUPLEX) + { + spi_rx_mode(priv, true); + } + + /* Wait until the receive buffer is not empty */ + + while ((spi_getreg(priv, STM32_SPI_SR_OFFSET) & SPI_SR_RXNE) == 0); + + if (priv->config == HALF_DUPLEX) + { + spi_rx_mode(priv, false); + } + + /* Then return the received byte */ + +#ifdef HAVE_IP_SPI_V2 + if (priv->nbits < 9) + { + return (uint16_t)spi_getreg8(priv, STM32_SPI_DR_OFFSET); + } + else +#endif + { + return spi_getreg(priv, STM32_SPI_DR_OFFSET); + } +} + +/**************************************************************************** + * Name: spi_writeword + * + * Description: + * Write one 16-bit frame to the SPI FIFO + * + * Input Parameters: + * priv - Device-specific state data + * byte - Word to send + * + * Returned Value: + * None + * + ****************************************************************************/ + +static inline void spi_writeword(struct stm32_spidev_s *priv, + uint16_t word) +{ + /* Can't transmit in rx only mode */ + + if (priv->config == SIMPLEX_RX) + { + return; + } + + if (priv->config == HALF_DUPLEX) + { + spi_rx_mode(priv, false); + } + + /* Wait until the transmit buffer is empty */ + + while ((spi_getreg(priv, STM32_SPI_SR_OFFSET) & SPI_SR_TXE) == 0) + { + } + + /* Then send the word */ + +#ifdef HAVE_IP_SPI_V2 + /* "When the data frame size fits into one byte (less than or equal to 8 + * bits), data packing is used automatically when any read or write 16-bit + * access is performed on the SPIx_DR register. The double data frame + * pattern is handled in parallel in this case. At first, the SPI operates + * using the pattern stored in the LSB of the accessed word, then with the + * other half stored in the MSB... + * + * "A specific problem appears if an odd number of such "fit into one + * byte" data frames must be handled. On the transmitter side, writing + * the last data frame of any odd sequence with an 8-bit access to + * SPIx_DR is enough. ..." + * + * REVISIT: "...The receiver has to change the Rx_FIFO threshold level for + * the last data frame received in the odd sequence of frames in order to + * generate the RXNE event." + */ + + if (priv->nbits < 9) + { + spi_putreg8(priv, STM32_SPI_DR_OFFSET, (uint8_t)word); + } + else +#endif + { + spi_putreg(priv, STM32_SPI_DR_OFFSET, word); + } + + if (priv->config == HALF_DUPLEX) + { + /* Wait for data transfer to be completed */ + + while ((spi_getreg(priv, STM32_SPI_SR_OFFSET) & SPI_SR_BSY) != 0); + } +} + +/**************************************************************************** + * Name: spi_16bitmode + * + * Description: + * Check if the SPI is operating in 16-bit mode + * + * Input Parameters: + * priv - Device-specific state data + * + * Returned Value: + * true: 16-bit mode, false: 8-bit mode + * + ****************************************************************************/ + +static inline bool spi_16bitmode(struct stm32_spidev_s *priv) +{ +#ifdef HAVE_IP_SPI_V2 + return (priv->nbits > 8); +#else + return ((spi_getreg(priv, STM32_SPI_CR1_OFFSET) & SPI_CR1_DFF) != 0); +#endif +} + +/**************************************************************************** + * Name: spi_dmarxwait + * + * Description: + * Wait for DMA to complete. + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_SPI_DMA +static int spi_dmarxwait(struct stm32_spidev_s *priv) +{ + int ret; + + /* Take the semaphore (perhaps waiting). If the result is zero, then the + * DMA must not really have completed??? + */ + + do + { + ret = nxsem_wait_uninterruptible(&priv->rxsem); + + /* The only expected error is ECANCELED which would occur if the + * calling thread were canceled. + */ + + DEBUGASSERT(ret == OK || ret == -ECANCELED); + } + while (priv->rxresult == 0 && ret == OK); + + return ret; +} +#endif + +/**************************************************************************** + * Name: spi_dmatxwait + * + * Description: + * Wait for DMA to complete. + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_SPI_DMA +static int spi_dmatxwait(struct stm32_spidev_s *priv) +{ + int ret; + + /* Take the semaphore (perhaps waiting). If the result is zero, then the + * DMA must not really have completed??? + */ + + do + { + ret = nxsem_wait_uninterruptible(&priv->txsem); + + /* The only expected error is ECANCELED which would occur if the + * calling thread were canceled. + */ + + DEBUGASSERT(ret == OK || ret == -ECANCELED); + } + while (priv->txresult == 0 && ret == OK); + + return ret; +} +#endif + +/**************************************************************************** + * Name: spi_dmarxwakeup + * + * Description: + * Signal that DMA is complete + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_SPI_DMA +static inline void spi_dmarxwakeup(struct stm32_spidev_s *priv) +{ + nxsem_post(&priv->rxsem); +} +#endif + +/**************************************************************************** + * Name: spi_dmatxwakeup + * + * Description: + * Signal that DMA is complete + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_SPI_DMA +static inline void spi_dmatxwakeup(struct stm32_spidev_s *priv) +{ + nxsem_post(&priv->txsem); +} +#endif + +/**************************************************************************** + * Name: spi_dmarxcallback + * + * Description: + * Called when the RX DMA completes + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_SPI_DMA +static void spi_dmarxcallback(DMA_HANDLE handle, uint8_t isr, void *arg) +{ + struct stm32_spidev_s *priv = (struct stm32_spidev_s *)arg; + + /* Wake-up the SPI driver */ + + priv->rxresult = isr | 0x080; /* OR'ed with 0x80 to assure non-zero */ + spi_dmarxwakeup(priv); +} +#endif + +/**************************************************************************** + * Name: spi_dmatxcallback + * + * Description: + * Called when the RX DMA completes + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_SPI_DMA +static void spi_dmatxcallback(DMA_HANDLE handle, uint8_t isr, void *arg) +{ + struct stm32_spidev_s *priv = (struct stm32_spidev_s *)arg; + + /* Wake-up the SPI driver */ + + priv->txresult = isr | 0x080; /* OR'ed with 0x80 to assure non-zero */ + spi_dmatxwakeup(priv); +} +#endif + +/**************************************************************************** + * Name: spi_dmarxsetup + * + * Description: + * Setup to perform RX DMA + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_SPI_DMA +static void spi_dmarxsetup(struct stm32_spidev_s *priv, + void *rxbuffer, void *rxdummy, + size_t nwords) +{ + /* 8- or 16-bit mode? */ + + if (spi_16bitmode(priv)) + { + /* 16-bit mode -- is there a buffer to receive data in? */ + + if (rxbuffer) + { + priv->rxccr = SPI_RXDMA16_CONFIG; + } + else + { + rxbuffer = rxdummy; + priv->rxccr = SPI_RXDMA16NULL_CONFIG; + } + } + else + { + /* 8-bit mode -- is there a buffer to receive data in? */ + + if (rxbuffer) + { + priv->rxccr = SPI_RXDMA8_CONFIG; + } + else + { + rxbuffer = rxdummy; + priv->rxccr = SPI_RXDMA8NULL_CONFIG; + } + } + + /* Configure the RX DMA */ + + stm32_dmasetup(priv->rxdma, priv->spibase + STM32_SPI_DR_OFFSET, + (uint32_t)rxbuffer, nwords, priv->rxccr); +} +#endif + +/**************************************************************************** + * Name: spi_dmatxsetup + * + * Description: + * Setup to perform TX DMA + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_SPI_DMA +static void spi_dmatxsetup(struct stm32_spidev_s *priv, + const void *txbuffer, const void *txdummy, + size_t nwords) +{ + /* 8- or 16-bit mode? */ + + if (spi_16bitmode(priv)) + { + /* 16-bit mode -- is there a buffer to transfer data from? */ + + if (txbuffer) + { + priv->txccr = SPI_TXDMA16_CONFIG; + } + else + { + txbuffer = txdummy; + priv->txccr = SPI_TXDMA16NULL_CONFIG; + } + } + else + { + /* 8-bit mode -- is there a buffer to transfer data from? */ + + if (txbuffer) + { + priv->txccr = SPI_TXDMA8_CONFIG; + } + else + { + txbuffer = txdummy; + priv->txccr = SPI_TXDMA8NULL_CONFIG; + } + } + + /* Setup the TX DMA */ + + stm32_dmasetup(priv->txdma, priv->spibase + STM32_SPI_DR_OFFSET, + (uint32_t)txbuffer, nwords, priv->txccr); +} +#endif + +/**************************************************************************** + * Name: spi_dmarxstart + * + * Description: + * Start RX DMA + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_SPI_DMA +static inline void spi_dmarxstart(struct stm32_spidev_s *priv) +{ + priv->rxresult = 0; + stm32_dmastart(priv->rxdma, spi_dmarxcallback, priv, false); +} +#endif + +/**************************************************************************** + * Name: spi_dmatxstart + * + * Description: + * Start TX DMA + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_SPI_DMA +static inline void spi_dmatxstart(struct stm32_spidev_s *priv) +{ + priv->txresult = 0; + stm32_dmastart(priv->txdma, spi_dmatxcallback, priv, false); +} +#endif + +/**************************************************************************** + * Name: spi_modifycr + * + * Description: + * Clear and set bits in the CR1 or CR2 register + * + * Input Parameters: + * priv - Device-specific state data + * clrbits - The bits to clear + * setbits - The bits to set + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void spi_modifycr(uint32_t addr, struct stm32_spidev_s *priv, + uint16_t setbits, uint16_t clrbits) +{ + uint16_t cr; + + cr = spi_getreg(priv, addr); + cr &= ~clrbits; + cr |= setbits; + spi_putreg(priv, addr, cr); +} + +/**************************************************************************** + * Name: spi_lock + * + * Description: + * On SPI buses where there are multiple devices, it will be necessary to + * lock SPI to have exclusive access to the buses for a sequence of + * transfers. The bus should be locked before the chip is selected. After + * locking the SPI bus, the caller should then also call the setfrequency, + * setbits, and setmode methods to make sure that the SPI is properly + * configured for the device. If the SPI bus is being shared, then it + * may have been left in an incompatible state. + * + * Input Parameters: + * dev - Device-specific state data + * lock - true: Lock spi bus, false: unlock SPI bus + * + * Returned Value: + * None + * + ****************************************************************************/ + +static int spi_lock(struct spi_dev_s *dev, bool lock) +{ + struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev; + int ret; + + if (lock) + { + ret = nxmutex_lock(&priv->lock); + } + else + { + ret = nxmutex_unlock(&priv->lock); + } + + return ret; +} + +/**************************************************************************** + * Name: spi_setfrequency + * + * Description: + * Set the SPI frequency. + * + * Input Parameters: + * dev - Device-specific state data + * frequency - The SPI frequency requested + * + * Returned Value: + * Returns the actual frequency selected + * + ****************************************************************************/ + +static uint32_t spi_setfrequency(struct spi_dev_s *dev, + uint32_t frequency) +{ + struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev; + uint16_t setbits; + uint32_t actual; + + /* Limit to max possible (if STM32_SPI_CLK_MAX is defined in board.h) */ + + if (frequency > STM32_SPI_CLK_MAX) + { + frequency = STM32_SPI_CLK_MAX; + } + + /* Has the frequency changed? */ + + if (frequency != priv->frequency) + { + /* Choices are limited by PCLK frequency with a set of divisors */ + + if (frequency >= priv->spiclock >> 1) + { + /* More than fPCLK/2. This is as fast as we can go */ + + setbits = SPI_CR1_FPCLCKd2; /* 000: fPCLK/2 */ + actual = priv->spiclock >> 1; + } + else if (frequency >= priv->spiclock >> 2) + { + /* Between fPCLCK/2 and fPCLCK/4, pick the slower */ + + setbits = SPI_CR1_FPCLCKd4; /* 001: fPCLK/4 */ + actual = priv->spiclock >> 2; + } + else if (frequency >= priv->spiclock >> 3) + { + /* Between fPCLCK/4 and fPCLCK/8, pick the slower */ + + setbits = SPI_CR1_FPCLCKd8; /* 010: fPCLK/8 */ + actual = priv->spiclock >> 3; + } + else if (frequency >= priv->spiclock >> 4) + { + /* Between fPCLCK/8 and fPCLCK/16, pick the slower */ + + setbits = SPI_CR1_FPCLCKd16; /* 011: fPCLK/16 */ + actual = priv->spiclock >> 4; + } + else if (frequency >= priv->spiclock >> 5) + { + /* Between fPCLCK/16 and fPCLCK/32, pick the slower */ + + setbits = SPI_CR1_FPCLCKd32; /* 100: fPCLK/32 */ + actual = priv->spiclock >> 5; + } + else if (frequency >= priv->spiclock >> 6) + { + /* Between fPCLCK/32 and fPCLCK/64, pick the slower */ + + setbits = SPI_CR1_FPCLCKd64; /* 101: fPCLK/64 */ + actual = priv->spiclock >> 6; + } + else if (frequency >= priv->spiclock >> 7) + { + /* Between fPCLCK/64 and fPCLCK/128, pick the slower */ + + setbits = SPI_CR1_FPCLCKd128; /* 110: fPCLK/128 */ + actual = priv->spiclock >> 7; + } + else + { + /* Less than fPCLK/128. This is as slow as we can go */ + + setbits = SPI_CR1_FPCLCKd256; /* 111: fPCLK/256 */ + actual = priv->spiclock >> 8; + } + + spi_modifycr(STM32_SPI_CR1_OFFSET, priv, 0, SPI_CR1_SPE); + spi_modifycr(STM32_SPI_CR1_OFFSET, priv, setbits, SPI_CR1_BR_MASK); + spi_modifycr(STM32_SPI_CR1_OFFSET, priv, SPI_CR1_SPE, 0); + + /* Save the frequency selection so that subsequent reconfigurations + * will be faster. + */ + + spiinfo("Frequency %" PRId32 "->% " PRId32 "\n", frequency, actual); + + priv->frequency = frequency; + priv->actual = actual; + } + + return priv->actual; +} + +/**************************************************************************** + * Name: spi_setmode + * + * Description: + * Set the SPI mode. see enum spi_mode_e for mode definitions + * + * Input Parameters: + * dev - Device-specific state data + * mode - The SPI mode requested + * + * Returned Value: + * Returns the actual frequency selected + * + ****************************************************************************/ + +static void spi_setmode(struct spi_dev_s *dev, enum spi_mode_e mode) +{ + struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev; + uint16_t setbits; + uint16_t clrbits; + + spiinfo("mode=%d\n", mode); + + /* Has the mode changed? */ + + if (mode != priv->mode) + { + /* Yes... Set CR1 appropriately */ + + switch (mode) + { + case SPIDEV_MODE0: /* CPOL=0; CPHA=0 */ + setbits = 0; + clrbits = SPI_CR1_CPOL | SPI_CR1_CPHA; + break; + + case SPIDEV_MODE1: /* CPOL=0; CPHA=1 */ + setbits = SPI_CR1_CPHA; + clrbits = SPI_CR1_CPOL; + break; + + case SPIDEV_MODE2: /* CPOL=1; CPHA=0 */ + setbits = SPI_CR1_CPOL; + clrbits = SPI_CR1_CPHA; + break; + + case SPIDEV_MODE3: /* CPOL=1; CPHA=1 */ + setbits = SPI_CR1_CPOL | SPI_CR1_CPHA; + clrbits = 0; + break; + + default: + return; + } + + spi_modifycr(STM32_SPI_CR1_OFFSET, priv, 0, SPI_CR1_SPE); + spi_modifycr(STM32_SPI_CR1_OFFSET, priv, setbits, clrbits); + spi_modifycr(STM32_SPI_CR1_OFFSET, priv, SPI_CR1_SPE, 0); + + /* Save the mode so that subsequent re-configurations will be + * faster. + */ + + priv->mode = mode; + } +} + +/**************************************************************************** + * Name: spi_setbits + * + * Description: + * Set the number of bits per word. With STM32, this is not restricted to + * 8 or 16, but can be any value between 4 and 16. + * + * Input Parameters: + * dev - Device-specific state data + * nbits - The number of bits requested, negative value means LSB first. + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void spi_setbits(struct spi_dev_s *dev, int nbits) +{ + struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev; + uint16_t setbits; + uint16_t clrbits; + + spiinfo("nbits=%d\n", nbits); + + /* Has the number of bits changed? */ + + if (nbits != priv->nbits) + { +#ifdef HAVE_IP_SPI_V2 + /* Yes... Set CR2 appropriately */ + + /* Set the number of bits (valid range 4-16) */ + + if (nbits < 4 || nbits > 16) + { + spierr("ERROR: nbits out of range: %d\n", nbits); + return; + } + + clrbits = SPI_CR2_DS_MASK; + setbits = SPI_CR2_DS_VAL(nbits); + + /* If nbits is <=8, then we are in byte mode and FRXTH shall be set + * (else, transaction will not complete). + */ + + if (nbits < 9) + { + setbits |= SPI_CR2_FRXTH; /* RX FIFO Threshold = 1 byte */ + } + else + { + clrbits |= SPI_CR2_FRXTH; /* RX FIFO Threshold = 2 bytes */ + } + + spi_modifycr(STM32_SPI_CR1_OFFSET, priv, 0, SPI_CR1_SPE); + spi_modifycr(STM32_SPI_CR2_OFFSET, priv, setbits, clrbits); + spi_modifycr(STM32_SPI_CR1_OFFSET, priv, SPI_CR1_SPE, 0); +#else + /* Yes... Set CR1 appropriately */ + + switch (nbits) + { + case 8: + setbits = 0; + clrbits = SPI_CR1_DFF; + break; + + case 16: + setbits = SPI_CR1_DFF; + clrbits = 0; + break; + + default: + return; + } + + spi_modifycr(STM32_SPI_CR1_OFFSET, priv, 0, SPI_CR1_SPE); + spi_modifycr(STM32_SPI_CR1_OFFSET, priv, setbits, clrbits); + spi_modifycr(STM32_SPI_CR1_OFFSET, priv, SPI_CR1_SPE, 0); +#endif + + /* Save the selection so that subsequent re-configurations will be + * faster. + */ + + priv->nbits = nbits; + } +} + +/**************************************************************************** + * Name: spi_hwfeatures + * + * Description: + * Set hardware-specific feature flags. + * + * Input Parameters: + * dev - Device-specific state data + * features - H/W feature flags + * + * Returned Value: + * Zero (OK) if the selected H/W features are enabled; A negated errno + * value if any H/W feature is not supportable. + * + ****************************************************************************/ + +#ifdef CONFIG_SPI_HWFEATURES +static int spi_hwfeatures(struct spi_dev_s *dev, + spi_hwfeatures_t features) +{ +#if defined(CONFIG_SPI_BITORDER) || defined(CONFIG_SPI_TRIGGER) + struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev; +#endif + +#ifdef CONFIG_SPI_BITORDER + uint16_t setbits; + uint16_t clrbits; + + spiinfo("features=%08x\n", features); + + /* Transfer data LSB first? */ + + if ((features & HWFEAT_LSBFIRST) != 0) + { + setbits = SPI_CR1_LSBFIRST; + clrbits = 0; + } + else + { + setbits = 0; + clrbits = SPI_CR1_LSBFIRST; + } + + spi_modifycr(STM32_SPI_CR1_OFFSET, priv, 0, SPI_CR1_SPE); + spi_modifycr(STM32_SPI_CR1_OFFSET, priv, setbits, clrbits); + spi_modifycr(STM32_SPI_CR1_OFFSET, priv, SPI_CR1_SPE, 0); + + features &= ~HWFEAT_LSBFIRST; +#endif + +#ifdef CONFIG_SPI_TRIGGER +/* Turn deferred trigger mode on or off. Only applicable for DMA mode. If a + * transfer is deferred then the DMA will not actually be triggered until a + * subsequent call to SPI_TRIGGER to set it off. The thread will be waiting + * on the transfer completing as normal. + */ + + priv->defertrig = ((features & HWFEAT_TRIGGER) != 0); + features &= ~HWFEAT_TRIGGER; +#endif + + /* Other H/W features are not supported */ + + return (features == 0) ? OK : -ENOSYS; +} +#endif + +/**************************************************************************** + * Name: spi_send + * + * Description: + * Exchange one word on SPI + * + * Input Parameters: + * dev - Device-specific state data + * wd - The word to send. the size of the data is determined by the + * number of bits selected for the SPI interface. + * + * Returned Value: + * response + * + ****************************************************************************/ + +static uint32_t spi_send(struct spi_dev_s *dev, uint32_t wd) +{ + struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev; + uint32_t regval; + uint32_t ret = 0; + + DEBUGASSERT(priv && priv->spibase); + + if (priv->config != HALF_DUPLEX) + { + spi_writeword(priv, (uint16_t)(wd & 0xffff)); + ret = (uint32_t)spi_readword(priv); + } + else + { + /* In half duplex we must send data and receive data in separate + * spi_send() calls. + */ + + if (!priv->rx_now) + { + spi_writeword(priv, (uint16_t)(wd & 0xffff)); + } + else + { + ret = (uint32_t)spi_readword(priv); + + priv->rx_now = false; + } + } + + /* Check and clear any error flags (Reading from the SR clears the error + * flags) + */ + + regval = spi_getreg(priv, STM32_SPI_SR_OFFSET); + + spiinfo("Sent: %04" PRIx32 " Return: %04" PRIx32 + " Status: %02" PRIx32 "\n", wd, ret, regval); + UNUSED(regval); + + return ret; +} + +/**************************************************************************** + * Name: spi_exchange (no DMA). aka spi_exchange_nodma + * + * Description: + * Exchange a block of data on SPI without using DMA + * + * Input Parameters: + * dev - Device-specific state data + * txbuffer - A pointer to the buffer of data to be sent + * rxbuffer - A pointer to a buffer in which to receive data + * nwords - the length of data to be exchanged in units of words. + * The wordsize is determined by the number of bits-per-word + * selected for the SPI interface. If nbits <= 8, the data is + * packed into uint8_t's; if nbits >8, the data is packed into + * uint16_t's + * + * Returned Value: + * None + * + ****************************************************************************/ + +#if !defined(CONFIG_STM32_SPI_DMA) +static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, + void *rxbuffer, size_t nwords) +#else +static void spi_exchange_nodma(struct spi_dev_s *dev, + const void *txbuffer, void *rxbuffer, + size_t nwords) +#endif +{ + struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev; + DEBUGASSERT(priv && priv->spibase); + + spiinfo("txbuffer=%p rxbuffer=%p nwords=%d\n", txbuffer, rxbuffer, nwords); + + /* 8- or 16-bit mode? */ + + if (spi_16bitmode(priv)) + { + /* 16-bit mode */ + + const uint16_t *src = (const uint16_t *)txbuffer; + uint16_t *dest = (uint16_t *)rxbuffer; + uint16_t word; + + while (nwords-- > 0) + { + /* Get the next word to write. Is there a source buffer? */ + + if (src) + { + word = *src++; + priv->rx_now = false; + } + else + { + word = 0xffff; + priv->rx_now = true; + } + + /* Exchange one word */ + + word = (uint16_t)spi_send(dev, (uint32_t)word); + + /* Is there a buffer to receive the return value? */ + + if (dest) + { + *dest++ = word; + } + } + } + else + { + /* 8-bit mode */ + + const uint8_t *src = (const uint8_t *)txbuffer; + uint8_t *dest = (uint8_t *)rxbuffer; + uint8_t word; + + while (nwords-- > 0) + { + /* Get the next word to write. Is there a source buffer? */ + + if (src) + { + word = *src++; + priv->rx_now = false; + } + else + { + word = 0xff; + priv->rx_now = true; + } + + /* Exchange one word */ + + word = (uint8_t)spi_send(dev, (uint32_t)word); + + /* Is there a buffer to receive the return value? */ + + if (dest) + { + *dest++ = word; + } + } + } +} + +/**************************************************************************** + * Name: spi_exchange (with DMA capability) + * + * Description: + * Exchange a block of data on SPI using DMA + * + * Input Parameters: + * dev - Device-specific state data + * txbuffer - A pointer to the buffer of data to be sent + * rxbuffer - A pointer to a buffer in which to receive data + * nwords - the length of data to be exchanged in units of words. + * The wordsize is determined by the number of bits-per-word + * selected for the SPI interface. If nbits <= 8, the data is + * packed into uint8_t's; if nbits >8, the data is packed into + * uint16_t's + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_SPI_DMA +static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, + void *rxbuffer, size_t nwords) +{ + struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev; + int ret = OK; + + if ((priv->rxdma == NULL) || (priv->txdma == NULL) || + up_interrupt_context()) + { + /* Invalid DMA channels, or interrupt context, fall + * back to non-DMA method. + */ + + spi_exchange_nodma(dev, txbuffer, rxbuffer, nwords); + return; + } + +#ifdef CONFIG_STM32_DMACAPABLE + if ((txbuffer && + !stm32_dmacapable((uintptr_t)txbuffer, nwords, priv->txccr)) || + (rxbuffer && + !stm32_dmacapable((uintptr_t)rxbuffer, nwords, priv->rxccr))) + { + /* Unsupported memory region, fall back to non-DMA method. */ + + spi_exchange_nodma(dev, txbuffer, rxbuffer, nwords); + } + else +#endif + { + static uint16_t rxdummy = 0xffff; + static const uint16_t txdummy = 0xffff; + + spiinfo("txbuffer=%p rxbuffer=%p nwords=%d\n", + txbuffer, rxbuffer, nwords); + DEBUGASSERT(priv && priv->spibase); + + /* Setup DMAs */ + + spi_dmarxsetup(priv, rxbuffer, &rxdummy, nwords); + spi_dmatxsetup(priv, txbuffer, &txdummy, nwords); + +#ifdef CONFIG_SPI_TRIGGER + /* Is deferred triggering in effect? */ + + if (!priv->defertrig) + { + /* No.. Start the DMAs */ + + spi_dmarxstart(priv); + spi_dmatxstart(priv); + } + else + { + /* Yes.. indicated that we are ready to be started */ + + priv->trigarmed = true; + } +#else + /* Start the DMAs */ + + spi_dmarxstart(priv); + spi_dmatxstart(priv); +#endif + + /* Then wait for each to complete */ + + ret = spi_dmarxwait(priv); + if (ret >= 0) + { + ret = spi_dmatxwait(priv); + UNUSED(ret); + } + +#ifdef CONFIG_SPI_TRIGGER + priv->trigarmed = false; +#endif + } +} +#endif /* CONFIG_STM32_SPI_DMA */ + +/**************************************************************************** + * Name: spi_trigger + * + * Description: + * Trigger a previously configured DMA transfer. + * + * Input Parameters: + * dev - Device-specific state data + * + * Returned Value: + * OK - Trigger was fired + * ENOTSUP - Trigger not fired due to lack of DMA support + * EIO - Trigger not fired because not previously primed + * + ****************************************************************************/ + +#ifdef CONFIG_SPI_TRIGGER +static int spi_trigger(struct spi_dev_s *dev) +{ +#ifdef CONFIG_STM32_SPI_DMA + struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev; + + if (!priv->trigarmed) + { + return -EIO; + } + + spi_dmarxstart(priv); + spi_dmatxstart(priv); + + return OK; +#else + return -ENOSYS; +#endif +} +#endif + +/**************************************************************************** + * Name: spi_sndblock + * + * Description: + * Send a block of data on SPI + * + * Input Parameters: + * dev - Device-specific state data + * txbuffer - A pointer to the buffer of data to be sent + * nwords - the length of data to send from the buffer in number of + * words. The wordsize is determined by the number of + * bits-per-word selected for the SPI interface. If nbits <= 8, + * the data is packed into uint8_t's; if nbits >8, the data is + * packed into uint16_t's + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifndef CONFIG_SPI_EXCHANGE +static void spi_sndblock(struct spi_dev_s *dev, const void *txbuffer, + size_t nwords) +{ + spiinfo("txbuffer=%p nwords=%d\n", txbuffer, nwords); + return spi_exchange(dev, txbuffer, NULL, nwords); +} +#endif + +/**************************************************************************** + * Name: spi_recvblock + * + * Description: + * Receive a block of data from SPI + * + * Input Parameters: + * dev - Device-specific state data + * rxbuffer - A pointer to the buffer in which to receive data + * nwords - the length of data that can be received in the buffer in + * number of words. The wordsize is determined by the number of + * bits-per-word selected for the SPI interface. If nbits <= 8, + * the data is packed into uint8_t's; if nbits >8, the data is + * packed into uint16_t's + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifndef CONFIG_SPI_EXCHANGE +static void spi_recvblock(struct spi_dev_s *dev, void *rxbuffer, + size_t nwords) +{ + spiinfo("rxbuffer=%p nwords=%d\n", rxbuffer, nwords); + return spi_exchange(dev, NULL, rxbuffer, nwords); +} +#endif + +/**************************************************************************** + * Name: spi_pm_prepare + * + * Description: + * Request the driver to prepare for a new power state. This is a + * warning that the system is about to enter into a new power state. The + * driver should begin whatever operations that may be required to enter + * power state. The driver may abort the state change mode by returning + * a non-zero value from the callback function. + * + * Input Parameters: + * cb - Returned to the driver. The driver version of the callback + * structure may include additional, driver-specific state + * data at the end of the structure. + * domain - Identifies the activity domain of the state change + * pmstate - Identifies the new PM state + * + * Returned Value: + * 0 (OK) means the event was successfully processed and that the driver + * is prepared for the PM state change. Non-zero means that the driver + * is not prepared to perform the tasks needed achieve this power setting + * and will cause the state change to be aborted. NOTE: The prepare + * method will also be recalled when reverting from lower back to higher + * power consumption modes (say because another driver refused a lower + * power state change). Drivers are not permitted to return non-zero + * values when reverting back to higher power consumption modes! + * + ****************************************************************************/ + +#ifdef CONFIG_PM +static int spi_pm_prepare(struct pm_callback_s *cb, int domain, + enum pm_state_e pmstate) +{ + struct stm32_spidev_s *priv = + (struct stm32_spidev_s *)((char *)cb - + offsetof(struct stm32_spidev_s, pm_cb)); + + /* Logic to prepare for a reduced power state goes here. */ + + switch (pmstate) + { + case PM_NORMAL: + case PM_IDLE: + break; + + case PM_STANDBY: + case PM_SLEEP: + + if (nxmutex_is_locked(&priv->lock)) + { + /* Exclusive lock is held, do not allow entry to deeper PM + * states. + */ + + return -EBUSY; + } + + break; + + default: + + /* Should not get here */ + + break; + } + + return OK; +} +#endif + +/**************************************************************************** + * Name: spi_bus_initialize + * + * Description: + * Initialize the selected SPI bus in its default state (Master, 8-bit, + * mode 0, etc.) + * + * Input Parameters: + * priv - private SPI device structure + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void spi_bus_initialize(struct stm32_spidev_s *priv) +{ + uint16_t setbits; + uint16_t clrbits; +#ifdef CONFIG_PM + int ret; +#endif + +#ifdef HAVE_IP_SPI_V2 + /* Configure CR1 and CR2. Default configuration: + * Mode 0: CR1.CPHA=0 and CR1.CPOL=0 + * Master: CR1.MSTR=1 + * 8-bit: CR2.DS=7 + * MSB transmitted first: CR1.LSBFIRST=0 + * Replace NSS with SSI & SSI=1: CR1.SSI=1 CR1.SSM=1 (prevents MODF + * error) + * Two lines full duplex: CR1.BIDIMODE=0 CR1.BIDIOIE=(Don't care) + * and CR1.RXONLY=0 + */ + + clrbits = SPI_CR1_CPHA | SPI_CR1_CPOL | SPI_CR1_BR_MASK | + SPI_CR1_LSBFIRST; + setbits = SPI_CR1_MSTR | SPI_CR1_SSI | SPI_CR1_SSM; + + switch (priv->config) + { + default: + case FULL_DUPLEX: + clrbits |= SPI_CR1_BIDIOE | SPI_CR1_BIDIMODE | SPI_CR1_RXONLY; + setbits |= 0; + break; + case SIMPLEX_TX: + clrbits |= SPI_CR1_BIDIOE | SPI_CR1_BIDIMODE | SPI_CR1_RXONLY; + setbits |= 0; + break; + case SIMPLEX_RX: + clrbits |= SPI_CR1_BIDIOE | SPI_CR1_BIDIMODE; + setbits |= SPI_CR1_RXONLY; + break; + case HALF_DUPLEX: + clrbits |= SPI_CR1_RXONLY; + setbits |= SPI_CR1_BIDIOE | SPI_CR1_BIDIMODE; /* TX mode */ + priv->rx_mode = false; + break; + } + + spi_modifycr(STM32_SPI_CR1_OFFSET, priv, setbits, clrbits); + + clrbits = SPI_CR2_DS_MASK; + setbits = SPI_CR2_DS_8BIT | SPI_CR2_FRXTH; /* FRXTH must be high in 8-bit mode */ + spi_modifycr(STM32_SPI_CR2_OFFSET, priv, setbits, clrbits); +#else + /* Configure CR1. Default configuration: + * Mode 0: CPHA=0 and CPOL=0 + * Master: MSTR=1 + * 8-bit: DFF=0 + * MSB transmitted first: LSBFIRST=0 + * Replace NSS with SSI & SSI=1: SSI=1 SSM=1 (prevents MODF error) + * Two lines full duplex: BIDIMODE=0 BIDIOIE=(Don't care) and + * RXONLY=0 + */ + + clrbits = SPI_CR1_CPHA | SPI_CR1_CPOL | SPI_CR1_BR_MASK | + SPI_CR1_LSBFIRST | SPI_CR1_DFF; + setbits = SPI_CR1_MSTR | SPI_CR1_SSI | SPI_CR1_SSM; + + switch (priv->config) + { + default: + case FULL_DUPLEX: + clrbits |= SPI_CR1_BIDIOE | SPI_CR1_BIDIMODE | SPI_CR1_RXONLY; + setbits |= 0; + break; + case SIMPLEX_TX: + clrbits |= SPI_CR1_BIDIOE | SPI_CR1_BIDIMODE | SPI_CR1_RXONLY; + setbits |= 0; + break; + case SIMPLEX_RX: + clrbits |= SPI_CR1_BIDIOE | SPI_CR1_BIDIMODE; + setbits |= SPI_CR1_RXONLY; + break; + case HALF_DUPLEX: + clrbits |= SPI_CR1_RXONLY; + setbits |= SPI_CR1_BIDIOE | SPI_CR1_BIDIMODE; /* TX mode */ + priv->rx_mode = false; + break; + } + + spi_modifycr(STM32_SPI_CR1_OFFSET, priv, setbits, clrbits); +#endif + + priv->frequency = 0; + priv->nbits = 8; + priv->mode = SPIDEV_MODE0; + + /* Select a default frequency of approx. 400KHz */ + + spi_setfrequency((struct spi_dev_s *)priv, 400000); + + /* CRCPOLY configuration */ + + spi_putreg(priv, STM32_SPI_CRCPR_OFFSET, 7); + +#ifdef CONFIG_STM32_SPI_DMA + if (priv->rxch && priv->txch) + { + /* Get DMA channels. NOTE: stm32_dmachannel() will always assign the + * DMA channel. If the channel is not available, then + * stm32_dmachannel() will block and wait until the channel becomes + * available. WARNING: If you have another device sharing a DMA channel + * with SPI and the code never releases that channel, then the call to + * stm32_dmachannel() will hang forever in this function! + * Don't let your design do that! + */ + + priv->rxdma = stm32_dmachannel(priv->rxch); + priv->txdma = stm32_dmachannel(priv->txch); + DEBUGASSERT(priv->rxdma && priv->txdma); + + spi_modifycr(STM32_SPI_CR2_OFFSET, priv, + SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN, 0); + } + else + { + priv->rxdma = NULL; + priv->txdma = NULL; + } +#endif + + /* Enable spi */ + + spi_modifycr(STM32_SPI_CR1_OFFSET, priv, SPI_CR1_SPE, 0); + +#ifdef CONFIG_PM + /* Register to receive power management callbacks */ + + ret = pm_register(&priv->pm_cb); + DEBUGASSERT(ret == OK); + UNUSED(ret); +#endif +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_spibus_initialize + * + * Description: + * Initialize the selected SPI bus + * + * Input Parameters: + * Port number (for hardware that has multiple SPI interfaces) + * + * Returned Value: + * Valid SPI device structure reference on success; a NULL on failure + * + ****************************************************************************/ + +struct spi_dev_s *stm32_spibus_initialize(int bus) +{ + struct stm32_spidev_s *priv = NULL; + + irqstate_t flags = enter_critical_section(); + +#ifdef CONFIG_STM32_SPI1 + if (bus == 1) + { + /* Select SPI1 */ + + priv = &g_spi1dev; + + /* Only configure if the bus is not already configured */ + + if (!priv->initialized) + { + /* Configure SPI1 pins: SCK, MISO, and MOSI */ + + stm32_configgpio(GPIO_SPI1_SCK); + stm32_configgpio(GPIO_SPI1_MOSI); + + if (priv->config == FULL_DUPLEX || priv->config == SIMPLEX_RX) + { + stm32_configgpio(GPIO_SPI1_MISO); + } + } + } + else +#endif +#ifdef CONFIG_STM32_SPI2 + if (bus == 2) + { + /* Select SPI2 */ + + priv = &g_spi2dev; + + /* Only configure if the bus is not already configured */ + + if (!priv->initialized) + { + /* Configure SPI2 pins: SCK, MISO, and MOSI */ + + stm32_configgpio(GPIO_SPI2_SCK); + stm32_configgpio(GPIO_SPI2_MOSI); + + if (priv->config == FULL_DUPLEX || priv->config == SIMPLEX_RX) + { + stm32_configgpio(GPIO_SPI2_MISO); + } + } + } + else +#endif +#ifdef CONFIG_STM32_SPI3 + if (bus == 3) + { + /* Select SPI3 */ + + priv = &g_spi3dev; + + /* Only configure if the bus is not already configured */ + + if (!priv->initialized) + { + /* Configure SPI3 pins: SCK, MISO, and MOSI */ + + stm32_configgpio(GPIO_SPI3_SCK); + stm32_configgpio(GPIO_SPI3_MOSI); + + if (priv->config == FULL_DUPLEX || priv->config == SIMPLEX_RX) + { + stm32_configgpio(GPIO_SPI3_MISO); + } + } + } + else +#endif + { + spierr("ERROR: Unsupported SPI bus: %d\n", bus); + priv = NULL; + goto errout; + } + +#ifdef CONFIG_STM32_SPI_DMA + /* SPI DMA supported only for full-duplex mode */ + + if (priv->rxch && priv->txch && priv->config != FULL_DUPLEX) + { + priv = NULL; + spierr("ERROR: SPI DMA supported only for full duplex mode\n"); + goto errout; + } +#endif + + /* Set up default configuration: Master, 8-bit, etc. */ + + spi_bus_initialize(priv); + priv->initialized = true; + +errout: + leave_critical_section(flags); + return (struct spi_dev_s *)priv; +} + +#endif /* CONFIG_STM32_SPI */ diff --git a/arch/arm/src/common/stm32/stm32_spi_m3m4_v2v3v4.c b/arch/arm/src/common/stm32/stm32_spi_m3m4_v2v3v4.c new file mode 100644 index 0000000000000..567f79a95fe27 --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_spi_m3m4_v2v3v4.c @@ -0,0 +1,2395 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_spi_m3m4_v2v3v4.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status must + * be provided by board-specific logic. They are implementations of the + * select and status methods of the SPI interface defined by struct spi_ops_s + * (see include/nuttx/spi/spi.h). + * All other methods (including stm32_spibus_initialize()) are provided by + * common STM32 logic. To use this common SPI logic on your board: + * + * 1. Provide logic in stm32_boardinitialize() to configure SPI chip select + * pins. + * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() functions + * in your board-specific logic. These functions will perform chip + * selection and status operations using GPIOs in the way your board is + * configured. + * 3. Add a calls to stm32_spibus_initialize() in your low level + * application initialization logic + * 4. The handle returned by stm32_spibus_initialize() may then be used to + * bind the SPI driver to higher level logic (e.g., calling + * mmcsd_spislotinitialize(), for example, will bind the SPI driver to + * the SPI MMC/SD driver). + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include + +#include "arm_internal.h" +#include "chip.h" +#include "stm32.h" +#include "stm32_gpio.h" +#include "stm32_dma.h" +#include "stm32_spi.h" + +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || \ + defined(CONFIG_STM32_SPI3) || defined(CONFIG_STM32_SPI4) || \ + defined(CONFIG_STM32_SPI5) || defined(CONFIG_STM32_SPI6) + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* SPI interrupts */ + +#ifdef CONFIG_STM32_SPI_INTERRUPTS +# error "Interrupt driven SPI not yet supported" +#endif + +/* Can't have both interrupt driven SPI and SPI DMA */ + +#if defined(CONFIG_STM32_SPI_INTERRUPTS) && defined(CONFIG_STM32_SPI_DMA) +# error "Cannot enable both interrupt mode and DMA mode for SPI" +#endif + +/* SPI DMA priority */ + +#ifdef CONFIG_STM32_SPI_DMA + +# if defined(CONFIG_SPI_DMAPRIO) +# define SPI_DMA_PRIO CONFIG_SPI_DMAPRIO +# elif defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32L15XX) || \ + defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32G4XXX) +# define SPI_DMA_PRIO DMA_CCR_PRIMED +# elif defined(CONFIG_STM32_HAVE_IP_DMA_V2) +# define SPI_DMA_PRIO DMA_SCR_PRIMED +# else +# error "Unknown STM32 DMA" +# endif + +# if defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32L15XX) || \ + defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32G4XXX) +# if (SPI_DMA_PRIO & ~DMA_CCR_PL_MASK) != 0 +# error "Illegal value for CONFIG_SPI_DMAPRIO" +# endif +# elif defined(CONFIG_STM32_HAVE_IP_DMA_V2) +# if (SPI_DMA_PRIO & ~DMA_SCR_PL_MASK) != 0 +# error "Illegal value for CONFIG_SPI_DMAPRIO" +# endif +# else +# error "Unknown STM32 DMA" +# endif + +/* DMA channel configuration */ + +#if defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32L15XX) || \ + defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX) || \ + defined(CONFIG_STM32_STM32G4XXX) +# define SPI_RXDMA16_CONFIG (SPI_DMA_PRIO|DMA_CCR_MSIZE_16BITS|DMA_CCR_PSIZE_16BITS|DMA_CCR_MINC ) +# define SPI_RXDMA8_CONFIG (SPI_DMA_PRIO|DMA_CCR_MSIZE_8BITS |DMA_CCR_PSIZE_8BITS |DMA_CCR_MINC ) +# define SPI_RXDMA16NULL_CONFIG (SPI_DMA_PRIO|DMA_CCR_MSIZE_8BITS |DMA_CCR_PSIZE_16BITS ) +# define SPI_RXDMA8NULL_CONFIG (SPI_DMA_PRIO|DMA_CCR_MSIZE_8BITS |DMA_CCR_PSIZE_8BITS ) +# define SPI_TXDMA16_CONFIG (SPI_DMA_PRIO|DMA_CCR_MSIZE_16BITS|DMA_CCR_PSIZE_16BITS|DMA_CCR_MINC|DMA_CCR_DIR) +# define SPI_TXDMA8_CONFIG (SPI_DMA_PRIO|DMA_CCR_MSIZE_8BITS |DMA_CCR_PSIZE_8BITS |DMA_CCR_MINC|DMA_CCR_DIR) +# define SPI_TXDMA16NULL_CONFIG (SPI_DMA_PRIO|DMA_CCR_MSIZE_8BITS |DMA_CCR_PSIZE_16BITS |DMA_CCR_DIR) +# define SPI_TXDMA8NULL_CONFIG (SPI_DMA_PRIO|DMA_CCR_MSIZE_8BITS |DMA_CCR_PSIZE_8BITS |DMA_CCR_DIR) +#elif defined(CONFIG_STM32_HAVE_IP_DMA_V2) +# define SPI_RXDMA16_CONFIG (SPI_DMA_PRIO|DMA_SCR_MSIZE_16BITS|DMA_SCR_PSIZE_16BITS|DMA_SCR_MINC|DMA_SCR_DIR_P2M) +# define SPI_RXDMA8_CONFIG (SPI_DMA_PRIO|DMA_SCR_MSIZE_8BITS |DMA_SCR_PSIZE_8BITS |DMA_SCR_MINC|DMA_SCR_DIR_P2M) +# define SPI_RXDMA16NULL_CONFIG (SPI_DMA_PRIO|DMA_SCR_MSIZE_8BITS |DMA_SCR_PSIZE_16BITS |DMA_SCR_DIR_P2M) +# define SPI_RXDMA8NULL_CONFIG (SPI_DMA_PRIO|DMA_SCR_MSIZE_8BITS |DMA_SCR_PSIZE_8BITS |DMA_SCR_DIR_P2M) +# define SPI_TXDMA16_CONFIG (SPI_DMA_PRIO|DMA_SCR_MSIZE_16BITS|DMA_SCR_PSIZE_16BITS|DMA_SCR_MINC|DMA_SCR_DIR_M2P) +# define SPI_TXDMA8_CONFIG (SPI_DMA_PRIO|DMA_SCR_MSIZE_8BITS |DMA_SCR_PSIZE_8BITS |DMA_SCR_MINC|DMA_SCR_DIR_M2P) +# define SPI_TXDMA16NULL_CONFIG (SPI_DMA_PRIO|DMA_SCR_MSIZE_8BITS |DMA_SCR_PSIZE_16BITS |DMA_SCR_DIR_M2P) +# define SPI_TXDMA8NULL_CONFIG (SPI_DMA_PRIO|DMA_SCR_MSIZE_8BITS |DMA_SCR_PSIZE_8BITS |DMA_SCR_DIR_M2P) +#else +# error "Unknown STM32 DMA" +#endif + +/* Maximum number of data items per single DMA descriptor. + * + * Both the STM32 DMA IPv1 (CNDTR on F0/F1/F3/G4/L0/L1/L4) and IPv2 (SxNDTR + * on F2/F4/F7/H7) transfer-count registers are 16 bits wide, so each call + * to stm32_dmasetup() can program at most 65535 transfers. spi_exchange() + * below chunks larger requests to stay within this limit; without it a + * single SPI_EXCHANGE() of >= 64 KiB silently programs NDTR to 0 (low 16 + * bits of nwords) and the driver blocks forever waiting on a DMA-complete + * IRQ that never fires. + */ + +# define STM32_SPI_DMA_MAX_XFER 65535u + +# define SPIDMA_BUFFER_MASK (4 - 1) +# define SPIDMA_SIZE(b) (((b) + SPIDMA_BUFFER_MASK) & ~SPIDMA_BUFFER_MASK) +# define SPIDMA_BUF_ALIGN aligned_data(4) + +# if defined(CONFIG_STM32_SPI1_DMA_BUFFER) && \ + CONFIG_STM32_SPI1_DMA_BUFFER > 0 +# define SPI1_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32_SPI1_DMA_BUFFER) +# define SPI1_DMABUFSIZE_ALGN SPIDMA_BUF_ALIGN +# endif + +# if defined(CONFIG_STM32_SPI2_DMA_BUFFER) && \ + CONFIG_STM32_SPI2_DMA_BUFFER > 0 +# define SPI2_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32_SPI2_DMA_BUFFER) +# define SPI2_DMABUFSIZE_ALGN SPIDMA_BUF_ALIGN +# endif + +# if defined(CONFIG_STM32_SPI3_DMA_BUFFER) && \ + CONFIG_STM32_SPI3_DMA_BUFFER > 0 +# define SPI3_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32_SPI3_DMA_BUFFER) +# define SPI3_DMABUFSIZE_ALGN SPIDMA_BUF_ALIGN +# endif + +# if defined(CONFIG_STM32_SPI4_DMA_BUFFER) && \ + CONFIG_STM32_SPI4_DMA_BUFFER > 0 +# define SPI4_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32_SPI4_DMA_BUFFER) +# define SPI4_DMABUFSIZE_ALGN SPIDMA_BUF_ALIGN +# endif + +# if defined(CONFIG_STM32_SPI5_DMA_BUFFER) && \ + CONFIG_STM32_SPI5_DMA_BUFFER > 0 +# define SPI5_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32_SPI5_DMA_BUFFER) +# define SPI5_DMABUFSIZE_ALGN SPIDMA_BUF_ALIGN +# endif + +# if defined(CONFIG_STM32_SPI6_DMA_BUFFER) && \ + CONFIG_STM32_SPI6_DMA_BUFFER > 0 +# define SPI6_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32_SPI6_DMA_BUFFER) +# define SPI6_DMABUFSIZE_ALGN SPIDMA_BUF_ALIGN +# endif + +#endif + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +struct stm32_spidev_s +{ + struct spi_dev_s spidev; /* Externally visible part of the SPI interface */ + uint32_t spibase; /* SPIn base address */ + uint32_t spiclock; /* Clocking for the SPI module */ +#ifdef CONFIG_STM32_SPI_INTERRUPTS + uint8_t spiirq; /* SPI IRQ number */ +#endif +#ifdef CONFIG_STM32_SPI_DMA + volatile uint8_t rxresult; /* Result of the RX DMA */ + volatile uint8_t txresult; /* Result of the RX DMA */ +#ifdef CONFIG_SPI_TRIGGER + bool defertrig; /* Flag indicating that trigger should be deferred */ + bool trigarmed; /* Flag indicating that the trigger is armed */ +#endif + uint8_t rxch; /* The RX DMA channel number */ + uint8_t txch; /* The TX DMA channel number */ + uint8_t *rxbuf; /* The RX DMA buffer */ + uint8_t *txbuf; /* The TX DMA buffer */ + size_t buflen; /* The DMA buffer length */ + DMA_HANDLE rxdma; /* DMA channel handle for RX transfers */ + DMA_HANDLE txdma; /* DMA channel handle for TX transfers */ + sem_t rxsem; /* Wait for RX DMA to complete */ + sem_t txsem; /* Wait for TX DMA to complete */ + uint32_t txccr; /* DMA control register for TX transfers */ + uint32_t rxccr; /* DMA control register for RX transfers */ +#endif + bool initialized; /* Has SPI interface been initialized */ + mutex_t lock; /* Held while chip is selected for mutual exclusion */ + uint32_t frequency; /* Requested clock frequency */ + uint32_t actual; /* Actual clock frequency */ + uint8_t nbits; /* Width of word in bits (4 through 16) */ + uint8_t mode; /* Mode 0,1,2,3 */ +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/* Helpers */ + +static inline uint16_t spi_getreg(struct stm32_spidev_s *priv, + uint8_t offset); +#if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX) +static inline uint8_t spi_getreg8(struct stm32_spidev_s *priv, + uint8_t offset); +#endif +static inline void spi_putreg(struct stm32_spidev_s *priv, + uint8_t offset, + uint16_t value); +#if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX) +static inline void spi_putreg8(struct stm32_spidev_s *priv, + uint8_t offset, + uint8_t value); +#endif +static inline uint16_t spi_readword(struct stm32_spidev_s *priv); +static inline void spi_writeword(struct stm32_spidev_s *priv, + uint16_t byte); + +/* DMA support */ + +#ifdef CONFIG_STM32_SPI_DMA +static int spi_dmarxwait(struct stm32_spidev_s *priv); +static int spi_dmatxwait(struct stm32_spidev_s *priv); +static inline void spi_dmarxwakeup(struct stm32_spidev_s *priv); +static inline void spi_dmatxwakeup(struct stm32_spidev_s *priv); +static void spi_dmarxcallback(DMA_HANDLE handle, uint8_t isr, + void *arg); +static void spi_dmatxcallback(DMA_HANDLE handle, uint8_t isr, + void *arg); +static void spi_dmarxsetup(struct stm32_spidev_s *priv, + void *rxbuffer, + void *rxdummy, + size_t nwords); +static void spi_dmatxsetup(struct stm32_spidev_s *priv, + const void *txbuffer, + const void *txdummy, + size_t nwords); +static inline void spi_dmarxstart(struct stm32_spidev_s *priv); +static inline void spi_dmatxstart(struct stm32_spidev_s *priv); +#endif + +/* SPI methods */ + +static int spi_lock(struct spi_dev_s *dev, bool lock); +static uint32_t spi_setfrequency(struct spi_dev_s *dev, + uint32_t frequency); +static void spi_setmode(struct spi_dev_s *dev, + enum spi_mode_e mode); +static void spi_setbits(struct spi_dev_s *dev, int nbits); +#ifdef CONFIG_SPI_HWFEATURES +static int spi_hwfeatures(struct spi_dev_s *dev, + spi_hwfeatures_t features); +#endif +static uint32_t spi_send(struct spi_dev_s *dev, uint32_t wd); +static void spi_exchange(struct spi_dev_s *dev, + const void *txbuffer, + void *rxbuffer, size_t nwords); +#ifdef CONFIG_SPI_TRIGGER +static int spi_trigger(struct spi_dev_s *dev); +#endif +#ifndef CONFIG_SPI_EXCHANGE +static void spi_sndblock(struct spi_dev_s *dev, + const void *txbuffer, + size_t nwords); +static void spi_recvblock(struct spi_dev_s *dev, + void *rxbuffer, + size_t nwords); +#endif + +/* Initialization */ + +static void spi_bus_initialize(struct stm32_spidev_s *priv); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#ifdef CONFIG_STM32_SPI1 +static const struct spi_ops_s g_sp1iops = +{ + .lock = spi_lock, + .select = stm32_spi1select, + .setfrequency = spi_setfrequency, + .setmode = spi_setmode, + .setbits = spi_setbits, +#ifdef CONFIG_SPI_HWFEATURES + .hwfeatures = spi_hwfeatures, +#endif + .status = stm32_spi1status, +#ifdef CONFIG_SPI_CMDDATA + .cmddata = stm32_spi1cmddata, +#endif + .send = spi_send, +#ifdef CONFIG_SPI_EXCHANGE + .exchange = spi_exchange, +#else + .sndblock = spi_sndblock, + .recvblock = spi_recvblock, +#endif +#ifdef CONFIG_SPI_TRIGGER + .trigger = spi_trigger, +#endif +#ifdef CONFIG_SPI_CALLBACK + .registercallback = stm32_spi1register, /* Provided externally */ +#else + .registercallback = 0, /* Not implemented */ +#endif +}; + +#if defined(SPI1_DMABUFSIZE_ADJUSTED) +static uint8_t g_spi1_txbuf[SPI1_DMABUFSIZE_ADJUSTED] SPI1_DMABUFSIZE_ALGN; +static uint8_t g_spi1_rxbuf[SPI1_DMABUFSIZE_ADJUSTED] SPI1_DMABUFSIZE_ALGN; +#endif + +static struct stm32_spidev_s g_spi1dev = +{ + .spidev = + { + .ops = &g_sp1iops + }, + .spibase = STM32_SPI1_BASE, + .spiclock = STM32_PCLK2_FREQUENCY, +#ifdef CONFIG_STM32_SPI_INTERRUPTS + .spiirq = STM32_IRQ_SPI1, +#endif +#ifdef CONFIG_STM32_SPI_DMA +# ifdef CONFIG_STM32_SPI1_DMA + .rxch = DMACHAN_SPI1_RX, + .txch = DMACHAN_SPI1_TX, +# ifdef SPI1_DMABUFSIZE_ADJUSTED + .rxbuf = g_spi1_rxbuf, + .txbuf = g_spi1_txbuf, + .buflen = SPI1_DMABUFSIZE_ADJUSTED, +# endif +# else + .rxch = 0, + .txch = 0, +# endif + .rxsem = SEM_INITIALIZER(0), + .txsem = SEM_INITIALIZER(0), +#endif + .lock = NXMUTEX_INITIALIZER, +}; +#endif + +#ifdef CONFIG_STM32_SPI2 +static const struct spi_ops_s g_sp2iops = +{ + .lock = spi_lock, + .select = stm32_spi2select, + .setfrequency = spi_setfrequency, + .setmode = spi_setmode, + .setbits = spi_setbits, +#ifdef CONFIG_SPI_HWFEATURES + .hwfeatures = spi_hwfeatures, +#endif + .status = stm32_spi2status, +#ifdef CONFIG_SPI_CMDDATA + .cmddata = stm32_spi2cmddata, +#endif + .send = spi_send, +#ifdef CONFIG_SPI_EXCHANGE + .exchange = spi_exchange, +#else + .sndblock = spi_sndblock, + .recvblock = spi_recvblock, +#endif +#ifdef CONFIG_SPI_TRIGGER + .trigger = spi_trigger, +#endif +#ifdef CONFIG_SPI_CALLBACK + .registercallback = stm32_spi2register, /* provided externally */ +#else + .registercallback = 0, /* not implemented */ +#endif +}; + +#if defined(SPI2_DMABUFSIZE_ADJUSTED) +static uint8_t g_spi2_txbuf[SPI2_DMABUFSIZE_ADJUSTED] SPI2_DMABUFSIZE_ALGN; +static uint8_t g_spi2_rxbuf[SPI2_DMABUFSIZE_ADJUSTED] SPI2_DMABUFSIZE_ALGN; +#endif + +static struct stm32_spidev_s g_spi2dev = +{ + .spidev = + { + .ops = &g_sp2iops + }, + .spibase = STM32_SPI2_BASE, + .spiclock = STM32_PCLK1_FREQUENCY, +#ifdef CONFIG_STM32_SPI_INTERRUPTS + .spiirq = STM32_IRQ_SPI2, +#endif +#ifdef CONFIG_STM32_SPI_DMA +# ifdef CONFIG_STM32_SPI2_DMA + .rxch = DMACHAN_SPI2_RX, + .txch = DMACHAN_SPI2_TX, +# ifdef SPI2_DMABUFSIZE_ADJUSTED + .rxbuf = g_spi2_rxbuf, + .txbuf = g_spi2_txbuf, + .buflen = SPI2_DMABUFSIZE_ADJUSTED, +# endif +# else + .rxch = 0, + .txch = 0, +# endif + .rxsem = SEM_INITIALIZER(0), + .txsem = SEM_INITIALIZER(0), +#endif + .lock = NXMUTEX_INITIALIZER, +}; +#endif + +#ifdef CONFIG_STM32_SPI3 +static const struct spi_ops_s g_sp3iops = +{ + .lock = spi_lock, + .select = stm32_spi3select, + .setfrequency = spi_setfrequency, + .setmode = spi_setmode, + .setbits = spi_setbits, +#ifdef CONFIG_SPI_HWFEATURES + .hwfeatures = spi_hwfeatures, +#endif + .status = stm32_spi3status, +#ifdef CONFIG_SPI_CMDDATA + .cmddata = stm32_spi3cmddata, +#endif + .send = spi_send, +#ifdef CONFIG_SPI_EXCHANGE + .exchange = spi_exchange, +#else + .sndblock = spi_sndblock, + .recvblock = spi_recvblock, +#endif +#ifdef CONFIG_SPI_TRIGGER + .trigger = spi_trigger, +#endif +#ifdef CONFIG_SPI_CALLBACK + .registercallback = stm32_spi3register, /* provided externally */ +#else + .registercallback = 0, /* not implemented */ +#endif +}; + +#if defined(SPI3_DMABUFSIZE_ADJUSTED) +static uint8_t g_spi3_txbuf[SPI3_DMABUFSIZE_ADJUSTED] SPI3_DMABUFSIZE_ALGN; +static uint8_t g_spi3_rxbuf[SPI3_DMABUFSIZE_ADJUSTED] SPI3_DMABUFSIZE_ALGN; +#endif + +static struct stm32_spidev_s g_spi3dev = +{ + .spidev = + { + .ops = &g_sp3iops + }, + .spibase = STM32_SPI3_BASE, + .spiclock = STM32_PCLK1_FREQUENCY, +#ifdef CONFIG_STM32_SPI_INTERRUPTS + .spiirq = STM32_IRQ_SPI3, +#endif +#ifdef CONFIG_STM32_SPI_DMA +# ifdef CONFIG_STM32_SPI3_DMA + .rxch = DMACHAN_SPI3_RX, + .txch = DMACHAN_SPI3_TX, +# ifdef SPI3_DMABUFSIZE_ADJUSTED + .rxbuf = g_spi3_rxbuf, + .txbuf = g_spi3_txbuf, + .buflen = SPI3_DMABUFSIZE_ADJUSTED, +# endif +# else + .rxch = 0, + .txch = 0, +# endif + .rxsem = SEM_INITIALIZER(0), + .txsem = SEM_INITIALIZER(0), +#endif + .lock = NXMUTEX_INITIALIZER, +}; +#endif + +#ifdef CONFIG_STM32_SPI4 +static const struct spi_ops_s g_sp4iops = +{ + .lock = spi_lock, + .select = stm32_spi4select, + .setfrequency = spi_setfrequency, + .setmode = spi_setmode, + .setbits = spi_setbits, +#ifdef CONFIG_SPI_HWFEATURES + .hwfeatures = spi_hwfeatures, +#endif + .status = stm32_spi4status, +#ifdef CONFIG_SPI_CMDDATA + .cmddata = stm32_spi4cmddata, +#endif + .send = spi_send, +#ifdef CONFIG_SPI_EXCHANGE + .exchange = spi_exchange, +#else + .sndblock = spi_sndblock, + .recvblock = spi_recvblock, +#endif +#ifdef CONFIG_SPI_TRIGGER + .trigger = spi_trigger, +#endif +#ifdef CONFIG_SPI_CALLBACK + .registercallback = stm32_spi4register, /* provided externally */ +#else + .registercallback = 0, /* not implemented */ +#endif +}; + +#if defined(SPI4_DMABUFSIZE_ADJUSTED) +static uint8_t g_spi4_txbuf[SPI4_DMABUFSIZE_ADJUSTED] SPI4_DMABUFSIZE_ALGN; +static uint8_t g_spi4_rxbuf[SPI4_DMABUFSIZE_ADJUSTED] SPI4_DMABUFSIZE_ALGN; +#endif + +static struct stm32_spidev_s g_spi4dev = +{ + .spidev = + { + .ops = &g_sp4iops + }, + .spibase = STM32_SPI4_BASE, + .spiclock = STM32_PCLK2_FREQUENCY, +#ifdef CONFIG_STM32_SPI_INTERRUPTS + .spiirq = STM32_IRQ_SPI4, +#endif +#ifdef CONFIG_STM32_SPI_DMA +# ifdef CONFIG_STM32_SPI4_DMA + .rxch = DMACHAN_SPI4_RX, + .txch = DMACHAN_SPI4_TX, +# ifdef SPI4_DMABUFSIZE_ADJUSTED + .rxbuf = g_spi4_rxbuf, + .txbuf = g_spi4_txbuf, + .buflen = SPI4_DMABUFSIZE_ADJUSTED, +# endif +# else + .rxch = 0, + .txch = 0, +# endif + .rxsem = SEM_INITIALIZER(0), + .txsem = SEM_INITIALIZER(0), +#endif + .lock = NXMUTEX_INITIALIZER, +}; +#endif + +#ifdef CONFIG_STM32_SPI5 +static const struct spi_ops_s g_sp5iops = +{ + .lock = spi_lock, + .select = stm32_spi5select, + .setfrequency = spi_setfrequency, + .setmode = spi_setmode, + .setbits = spi_setbits, +#ifdef CONFIG_SPI_HWFEATURES + .hwfeatures = spi_hwfeatures, +#endif + .status = stm32_spi5status, +#ifdef CONFIG_SPI_CMDDATA + .cmddata = stm32_spi5cmddata, +#endif + .send = spi_send, +#ifdef CONFIG_SPI_EXCHANGE + .exchange = spi_exchange, +#else + .sndblock = spi_sndblock, + .recvblock = spi_recvblock, +#endif +#ifdef CONFIG_SPI_TRIGGER + .trigger = spi_trigger, +#endif +#ifdef CONFIG_SPI_CALLBACK + .registercallback = stm32_spi5register, /* provided externally */ +#else + .registercallback = 0, /* not implemented */ +#endif +}; + +#if defined(SPI5_DMABUFSIZE_ADJUSTED) +static uint8_t g_spi5_txbuf[SPI5_DMABUFSIZE_ADJUSTED] SPI5_DMABUFSIZE_ALGN; +static uint8_t g_spi5_rxbuf[SPI5_DMABUFSIZE_ADJUSTED] SPI5_DMABUFSIZE_ALGN; +#endif + +static struct stm32_spidev_s g_spi5dev = +{ + .spidev = + { + .ops = &g_sp5iops + }, + .spibase = STM32_SPI5_BASE, + .spiclock = STM32_PCLK2_FREQUENCY, +#ifdef CONFIG_STM32_SPI_INTERRUPTS + .spiirq = STM32_IRQ_SPI5, +#endif +#ifdef CONFIG_STM32_SPI_DMA +# ifdef CONFIG_STM32_SPI5_DMA + .rxch = DMACHAN_SPI5_RX, + .txch = DMACHAN_SPI5_TX, +# ifdef SPI5_DMABUFSIZE_ADJUSTED + .rxbuf = g_spi5_rxbuf, + .txbuf = g_spi5_txbuf, + .buflen = SPI5_DMABUFSIZE_ADJUSTED, +# endif +# else + .rxch = 0, + .txch = 0, +# endif + .rxsem = SEM_INITIALIZER(0), + .txsem = SEM_INITIALIZER(0), +#endif + .lock = NXMUTEX_INITIALIZER, +}; +#endif + +#ifdef CONFIG_STM32_SPI6 +static const struct spi_ops_s g_sp6iops = +{ + .lock = spi_lock, + .select = stm32_spi6select, + .setfrequency = spi_setfrequency, + .setmode = spi_setmode, + .setbits = spi_setbits, +#ifdef CONFIG_SPI_HWFEATURES + .hwfeatures = spi_hwfeatures, +#endif + .status = stm32_spi6status, +#ifdef CONFIG_SPI_CMDDATA + .cmddata = stm32_spi6cmddata, +#endif + .send = spi_send, +#ifdef CONFIG_SPI_EXCHANGE + .exchange = spi_exchange, +#else + .sndblock = spi_sndblock, + .recvblock = spi_recvblock, +#endif +#ifdef CONFIG_SPI_TRIGGER + .trigger = spi_trigger, +#endif +#ifdef CONFIG_SPI_CALLBACK + .registercallback = stm32_spi6register, /* provided externally */ +#else + .registercallback = 0, /* not implemented */ +#endif +}; + +#if defined(SPI6_DMABUFSIZE_ADJUSTED) +static uint8_t g_spi6_txbuf[SPI6_DMABUFSIZE_ADJUSTED] SPI6_DMABUFSIZE_ALGN; +static uint8_t g_spi6_rxbuf[SPI6_DMABUFSIZE_ADJUSTED] SPI6_DMABUFSIZE_ALGN; +#endif + +static struct stm32_spidev_s g_spi6dev = +{ + .spidev = + { + .ops = &g_sp6iops + }, + .spibase = STM32_SPI6_BASE, + .spiclock = STM32_PCLK2_FREQUENCY, +#ifdef CONFIG_STM32_SPI_INTERRUPTS + .spiirq = STM32_IRQ_SPI6, +#endif +#ifdef CONFIG_STM32_SPI_DMA +# ifdef CONFIG_STM32_SPI6_DMA + .rxch = DMACHAN_SPI6_RX, + .txch = DMACHAN_SPI6_TX, +# ifdef SPI6_DMABUFSIZE_ADJUSTED + .rxbuf = g_spi6_rxbuf, + .txbuf = g_spi6_txbuf, + .buflen = SPI6_DMABUFSIZE_ADJUSTED, +# endif +# else + .rxch = 0, + .txch = 0, +# endif + .rxsem = SEM_INITIALIZER(0), + .txsem = SEM_INITIALIZER(0), +#endif + .lock = NXMUTEX_INITIALIZER, +}; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: spi_getreg + * + * Description: + * Get the contents of the SPI register at offset + * + * Input Parameters: + * priv - private SPI device structure + * offset - offset to the register of interest + * + * Returned Value: + * The contents of the 16-bit register + * + ****************************************************************************/ + +static inline uint16_t spi_getreg(struct stm32_spidev_s *priv, + uint8_t offset) +{ + return getreg16(priv->spibase + offset); +} + +/**************************************************************************** + * Name: spi_getreg8 + * + * Description: + * Get the contents of the SPI register at offset + * + * Input Parameters: + * priv - private SPI device structure + * offset - offset to the register of interest + * + * Returned Value: + * The contents of the 16-bit register + * + ****************************************************************************/ + +#if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX) || \ + defined(CONFIG_STM32_STM32G4XXX) +static inline uint8_t spi_getreg8(struct stm32_spidev_s *priv, + uint8_t offset) +{ + return getreg8(priv->spibase + offset); +} +#endif + +/**************************************************************************** + * Name: spi_putreg + * + * Description: + * Write a 16-bit value to the SPI register at offset + * + * Input Parameters: + * priv - private SPI device structure + * offset - offset to the register of interest + * value - the 16-bit value to be written + * + * Returned Value: + * The contents of the 16-bit register + * + ****************************************************************************/ + +static inline void spi_putreg(struct stm32_spidev_s *priv, + uint8_t offset, + uint16_t value) +{ + putreg16(value, priv->spibase + offset); +} + +/**************************************************************************** + * Name: spi_putreg8 + * + * Description: + * Write an 8-bit value to the SPI register at offset + * + * Input Parameters: + * priv - private SPI device structure + * offset - offset to the register of interest + * value - the 16-bit value to be written + * + * Returned Value: + * The contents of the 16-bit register + * + ****************************************************************************/ + +#if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX) || \ + defined(CONFIG_STM32_STM32G4XXX) +static inline void spi_putreg8(struct stm32_spidev_s *priv, + uint8_t offset, + uint8_t value) +{ + putreg8(value, priv->spibase + offset); +} +#endif + +/**************************************************************************** + * Name: spi_readword + * + * Description: + * Read one byte from SPI + * + * Input Parameters: + * priv - Device-specific state data + * + * Returned Value: + * Byte as read + * + ****************************************************************************/ + +static inline uint16_t spi_readword(struct stm32_spidev_s *priv) +{ + /* Wait until the receive buffer is not empty */ + + while ((spi_getreg(priv, STM32_SPI_SR_OFFSET) & SPI_SR_RXNE) == 0) + { + } + + /* Then return the received byte */ + +#if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX)|| \ + defined(CONFIG_STM32_STM32G4XXX) + /* "When the data frame size fits into one byte + * (less than or equal to 8 bits), + * data packing is used automatically when any read or write 16-bit access + * is performed on the SPIx_DR register. The double data frame pattern is + * handled in parallel in this case. At first, the SPI operates using the + * pattern stored in the LSB of the accessed word, then with the other + * half stored in the MSB.... The receiver then has to access both data + * frames by a single 16-bit read of SPIx_DR as a response to this single + * RXNE event. The RxFIFO threshold setting and the following read access + * must be always kept aligned at the receiver side, as data can be lost + * if it is not in line." + */ + + if (priv->nbits < 9) + { + return (uint16_t)spi_getreg8(priv, STM32_SPI_DR_OFFSET); + } + else +#endif + { + return spi_getreg(priv, STM32_SPI_DR_OFFSET); + } +} + +/**************************************************************************** + * Name: spi_writeword + * + * Description: + * Write one byte to SPI + * + * Input Parameters: + * priv - Device-specific state data + * byte - Byte to send + * + * Returned Value: + * None + * + ****************************************************************************/ + +static inline void spi_writeword(struct stm32_spidev_s *priv, + uint16_t word) +{ + /* Wait until the transmit buffer is empty */ + + while ((spi_getreg(priv, STM32_SPI_SR_OFFSET) & SPI_SR_TXE) == 0) + { + } + + /* Then send the word */ + +#if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX) || \ + defined(CONFIG_STM32_STM32G4XXX) + /* "When the data frame size fits into one byte (less than or equal to 8 + * bits), data packing is used automatically when any read or write 16-bit + * access is performed on the SPIx_DR register. The double data frame + * pattern is handled in parallel in this case. At first, the SPI operates + * using the pattern stored in the LSB of the accessed word, then with the + * other half stored in the MSB... + * + * "A specific problem appears if an odd number of such "fit into one + * byte" data frames must be handled. On the transmitter side, writing + * the last data frame of any odd sequence with an 8-bit access to + * SPIx_DR is enough. ..." + * + * REVISIT: "...The receiver has to change the Rx_FIFO threshold level for + * the last data frame received in the odd sequence of frames in order to + * generate the RXNE event." + */ + + if (priv->nbits < 9) + { + spi_putreg8(priv, STM32_SPI_DR_OFFSET, (uint8_t)word); + } + else +#endif + { + spi_putreg(priv, STM32_SPI_DR_OFFSET, word); + } +} + +/**************************************************************************** + * Name: spi_dmarxwait + * + * Description: + * Wait for DMA to complete. + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_SPI_DMA +static int spi_dmarxwait(struct stm32_spidev_s *priv) +{ + int ret; + + /* Take the semaphore (perhaps waiting). If the result is zero, then the + * DMA must not really have completed??? + */ + + do + { + ret = nxsem_wait_uninterruptible(&priv->rxsem); + + /* The only expected error is ECANCELED which would occur if the + * calling thread were canceled. + */ + + DEBUGASSERT(ret == OK || ret == -ECANCELED); + } + while (priv->rxresult == 0 && ret == OK); + + return ret; +} +#endif + +/**************************************************************************** + * Name: spi_dmatxwait + * + * Description: + * Wait for DMA to complete. + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_SPI_DMA +static int spi_dmatxwait(struct stm32_spidev_s *priv) +{ + int ret; + + /* Take the semaphore (perhaps waiting). If the result is zero, then the + * DMA must not really have completed??? + */ + + do + { + ret = nxsem_wait_uninterruptible(&priv->txsem); + + /* The only expected error is ECANCELED which would occur if the + * calling thread were canceled. + */ + + DEBUGASSERT(ret == OK || ret == -ECANCELED); + } + while (priv->txresult == 0 && ret == OK); + + return ret; +} +#endif + +/**************************************************************************** + * Name: spi_dmarxwakeup + * + * Description: + * Signal that DMA is complete + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_SPI_DMA +static inline void spi_dmarxwakeup(struct stm32_spidev_s *priv) +{ + nxsem_post(&priv->rxsem); +} +#endif + +/**************************************************************************** + * Name: spi_dmatxwakeup + * + * Description: + * Signal that DMA is complete + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_SPI_DMA +static inline void spi_dmatxwakeup(struct stm32_spidev_s *priv) +{ + nxsem_post(&priv->txsem); +} +#endif + +/**************************************************************************** + * Name: spi_dmarxcallback + * + * Description: + * Called when the RX DMA completes + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_SPI_DMA +static void spi_dmarxcallback(DMA_HANDLE handle, uint8_t isr, void *arg) +{ + struct stm32_spidev_s *priv = (struct stm32_spidev_s *)arg; + + /* Wake-up the SPI driver */ + + priv->rxresult = isr | 0x080; /* OR'ed with 0x80 to assure non-zero */ + spi_dmarxwakeup(priv); +} +#endif + +/**************************************************************************** + * Name: spi_dmatxcallback + * + * Description: + * Called when the RX DMA completes + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_SPI_DMA +static void spi_dmatxcallback(DMA_HANDLE handle, uint8_t isr, void *arg) +{ + struct stm32_spidev_s *priv = (struct stm32_spidev_s *)arg; + + /* Wake-up the SPI driver */ + + priv->txresult = isr | 0x080; /* OR'ed with 0x80 to assure non-zero */ + spi_dmatxwakeup(priv); +} +#endif + +/**************************************************************************** + * Name: spi_dmarxsetup + * + * Description: + * Setup to perform RX DMA + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_SPI_DMA +static void spi_dmarxsetup(struct stm32_spidev_s *priv, + void *rxbuffer, + void *rxdummy, size_t nwords) +{ + /* 8- or 16-bit mode? */ + + if (priv->nbits > 8) + { + /* 16-bit mode -- is there a buffer to receive data in? */ + + if (rxbuffer) + { + priv->rxccr = SPI_RXDMA16_CONFIG; + } + else + { + rxbuffer = rxdummy; + priv->rxccr = SPI_RXDMA16NULL_CONFIG; + } + } + else + { + /* 8-bit mode -- is there a buffer to receive data in? */ + + if (rxbuffer) + { + priv->rxccr = SPI_RXDMA8_CONFIG; + } + else + { + rxbuffer = rxdummy; + priv->rxccr = SPI_RXDMA8NULL_CONFIG; + } + } + + /* Configure the RX DMA */ + + stm32_dmasetup(priv->rxdma, priv->spibase + STM32_SPI_DR_OFFSET, + (uint32_t)rxbuffer, nwords, priv->rxccr); +} +#endif + +/**************************************************************************** + * Name: spi_dmatxsetup + * + * Description: + * Setup to perform TX DMA + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_SPI_DMA +static void spi_dmatxsetup(struct stm32_spidev_s *priv, + const void *txbuffer, + const void *txdummy, size_t nwords) +{ + /* 8- or 16-bit mode? */ + + if (priv->nbits > 8) + { + /* 16-bit mode -- is there a buffer to transfer data from? */ + + if (txbuffer) + { + priv->txccr = SPI_TXDMA16_CONFIG; + } + else + { + txbuffer = txdummy; + priv->txccr = SPI_TXDMA16NULL_CONFIG; + } + } + else + { + /* 8-bit mode -- is there a buffer to transfer data from? */ + + if (txbuffer) + { + priv->txccr = SPI_TXDMA8_CONFIG; + } + else + { + txbuffer = txdummy; + priv->txccr = SPI_TXDMA8NULL_CONFIG; + } + } + + /* Setup the TX DMA */ + + stm32_dmasetup(priv->txdma, priv->spibase + STM32_SPI_DR_OFFSET, + (uint32_t)txbuffer, nwords, priv->txccr); +} +#endif + +/**************************************************************************** + * Name: spi_dmarxstart + * + * Description: + * Start RX DMA + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_SPI_DMA +static inline void spi_dmarxstart(struct stm32_spidev_s *priv) +{ + priv->rxresult = 0; + stm32_dmastart(priv->rxdma, spi_dmarxcallback, priv, false); +} +#endif + +/**************************************************************************** + * Name: spi_dmatxstart + * + * Description: + * Start TX DMA + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_SPI_DMA +static inline void spi_dmatxstart(struct stm32_spidev_s *priv) +{ + priv->txresult = 0; + stm32_dmastart(priv->txdma, spi_dmatxcallback, priv, false); +} +#endif + +/**************************************************************************** + * Name: spi_modifycr1 + * + * Description: + * Clear and set bits in the CR1 register + * + * Input Parameters: + * priv - Device-specific state data + * clrbits - The bits to clear + * setbits - The bits to set + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void spi_modifycr1(struct stm32_spidev_s *priv, + uint16_t setbits, + uint16_t clrbits) +{ + uint16_t cr1; + cr1 = spi_getreg(priv, STM32_SPI_CR1_OFFSET); + cr1 &= ~clrbits; + cr1 |= setbits; + spi_putreg(priv, STM32_SPI_CR1_OFFSET, cr1); +} + +/**************************************************************************** + * Name: spi_modifycr2 + * + * Description: + * Clear and set bits in the CR2 register + * + * Input Parameters: + * priv - Device-specific state data + * clrbits - The bits to clear + * setbits - The bits to set + * + * Returned Value: + * None + * + ****************************************************************************/ + +#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F30XX) || \ + defined(CONFIG_STM32_STM32F37XX) || defined(CONFIG_STM32_STM32F4XXX) || \ + defined(CONFIG_STM32_STM32G4XXX) || defined(CONFIG_STM32_SPI_DMA) +static void spi_modifycr2(struct stm32_spidev_s *priv, uint16_t setbits, + uint16_t clrbits) +{ + uint16_t cr2; + cr2 = spi_getreg(priv, STM32_SPI_CR2_OFFSET); + cr2 &= ~clrbits; + cr2 |= setbits; + spi_putreg(priv, STM32_SPI_CR2_OFFSET, cr2); +} +#endif + +/**************************************************************************** + * Name: spi_lock + * + * Description: + * On SPI buses where there are multiple devices, it will be necessary to + * lock SPI to have exclusive access to the buses for a sequence of + * transfers. The bus should be locked before the chip is selected. After + * locking the SPI bus, the caller should then also call the setfrequency, + * setbits, and setmode methods to make sure that the SPI is properly + * configured for the device. If the SPI bus is being shared, then it + * may have been left in an incompatible state. + * + * Input Parameters: + * dev - Device-specific state data + * lock - true: Lock spi bus, false: unlock SPI bus + * + * Returned Value: + * None + * + ****************************************************************************/ + +static int spi_lock(struct spi_dev_s *dev, bool lock) +{ + struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev; + int ret; + + if (lock) + { + ret = nxmutex_lock(&priv->lock); + } + else + { + ret = nxmutex_unlock(&priv->lock); + } + + return ret; +} + +/**************************************************************************** + * Name: spi_setfrequency + * + * Description: + * Set the SPI frequency. + * + * Input Parameters: + * dev - Device-specific state data + * frequency - The SPI frequency requested + * + * Returned Value: + * Returns the actual frequency selected + * + ****************************************************************************/ + +static uint32_t spi_setfrequency(struct spi_dev_s *dev, + uint32_t frequency) +{ + struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev; + uint16_t setbits; + uint32_t actual; + + /* Has the frequency changed? */ + + if (frequency != priv->frequency) + { + /* Choices are limited by PCLK frequency with a set of divisors */ + + if (frequency >= priv->spiclock >> 1) + { + /* More than fPCLK/2. This is as fast as we can go */ + + setbits = SPI_CR1_FPCLCKd2; /* 000: fPCLK/2 */ + actual = priv->spiclock >> 1; + } + else if (frequency >= priv->spiclock >> 2) + { + /* Between fPCLCK/2 and fPCLCK/4, pick the slower */ + + setbits = SPI_CR1_FPCLCKd4; /* 001: fPCLK/4 */ + actual = priv->spiclock >> 2; + } + else if (frequency >= priv->spiclock >> 3) + { + /* Between fPCLCK/4 and fPCLCK/8, pick the slower */ + + setbits = SPI_CR1_FPCLCKd8; /* 010: fPCLK/8 */ + actual = priv->spiclock >> 3; + } + else if (frequency >= priv->spiclock >> 4) + { + /* Between fPCLCK/8 and fPCLCK/16, pick the slower */ + + setbits = SPI_CR1_FPCLCKd16; /* 011: fPCLK/16 */ + actual = priv->spiclock >> 4; + } + else if (frequency >= priv->spiclock >> 5) + { + /* Between fPCLCK/16 and fPCLCK/32, pick the slower */ + + setbits = SPI_CR1_FPCLCKd32; /* 100: fPCLK/32 */ + actual = priv->spiclock >> 5; + } + else if (frequency >= priv->spiclock >> 6) + { + /* Between fPCLCK/32 and fPCLCK/64, pick the slower */ + + setbits = SPI_CR1_FPCLCKd64; /* 101: fPCLK/64 */ + actual = priv->spiclock >> 6; + } + else if (frequency >= priv->spiclock >> 7) + { + /* Between fPCLCK/64 and fPCLCK/128, pick the slower */ + + setbits = SPI_CR1_FPCLCKd128; /* 110: fPCLK/128 */ + actual = priv->spiclock >> 7; + } + else + { + /* Less than fPCLK/128. This is as slow as we can go */ + + setbits = SPI_CR1_FPCLCKd256; /* 111: fPCLK/256 */ + actual = priv->spiclock >> 8; + } + + spi_modifycr1(priv, 0, SPI_CR1_SPE); + spi_modifycr1(priv, setbits, SPI_CR1_BR_MASK); + spi_modifycr1(priv, SPI_CR1_SPE, 0); + + /* Save the frequency selection so that subsequent reconfigurations + * will be faster. + */ + + spiinfo("Frequency %" PRIu32 "->%" PRIu32 "\n", frequency, actual); + + priv->frequency = frequency; + priv->actual = actual; + } + + return priv->actual; +} + +/**************************************************************************** + * Name: spi_setmode + * + * Description: + * Set the SPI mode. see enum spi_mode_e for mode definitions + * + * Input Parameters: + * dev - Device-specific state data + * mode - The SPI mode requested + * + * Returned Value: + * Returns the actual frequency selected + * + ****************************************************************************/ + +static void spi_setmode(struct spi_dev_s *dev, enum spi_mode_e mode) +{ + struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev; + uint16_t setbits; + uint16_t clrbits; + + spiinfo("mode=%d\n", mode); + + /* Has the mode changed? */ + + if (mode != priv->mode) + { + /* Yes... Set CR1 appropriately */ + + switch (mode) + { + case SPIDEV_MODE0: /* CPOL=0; CPHA=0 */ + setbits = 0; + clrbits = SPI_CR1_CPOL | SPI_CR1_CPHA; + break; + + case SPIDEV_MODE1: /* CPOL=0; CPHA=1 */ + setbits = SPI_CR1_CPHA; + clrbits = SPI_CR1_CPOL; + break; + + case SPIDEV_MODE2: /* CPOL=1; CPHA=0 */ + setbits = SPI_CR1_CPOL; + clrbits = SPI_CR1_CPHA; + break; + + case SPIDEV_MODE3: /* CPOL=1; CPHA=1 */ + setbits = SPI_CR1_CPOL | SPI_CR1_CPHA; + clrbits = 0; + break; + +#ifdef SPI_CR2_FRF /* If MCU supports TI Synchronous Serial Frame Format */ + case SPIDEV_MODETI: + setbits = 0; + clrbits = SPI_CR1_CPOL | SPI_CR1_CPHA; + break; +#endif + + default: + return; + } + + spi_modifycr1(priv, 0, SPI_CR1_SPE); + spi_modifycr1(priv, setbits, clrbits); + spi_modifycr1(priv, SPI_CR1_SPE, 0); + +#ifdef SPI_CR2_FRF /* If MCU supports TI Synchronous Serial Frame Format */ + switch (mode) + { + case SPIDEV_MODE0: + case SPIDEV_MODE1: + case SPIDEV_MODE2: + case SPIDEV_MODE3: + setbits = 0; + clrbits = SPI_CR2_FRF; + break; + + case SPIDEV_MODETI: + setbits = SPI_CR2_FRF; + clrbits = 0; + break; + + default: + return; + } + + spi_modifycr1(priv, 0, SPI_CR1_SPE); + spi_modifycr2(priv, setbits, clrbits); + spi_modifycr1(priv, SPI_CR1_SPE, 0); +#endif + + /* Save the mode so that subsequent re-configurations will be + * faster + */ + + priv->mode = mode; + } +} + +/**************************************************************************** + * Name: spi_setbits + * + * Description: + * Set the number of bits per word. + * + * Input Parameters: + * dev - Device-specific state data + * nbits - The number of bits requested + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void spi_setbits(struct spi_dev_s *dev, int nbits) +{ + struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev; + uint16_t setbits; + uint16_t clrbits; + + spiinfo("nbits=%d\n", nbits); + + /* Has the number of bits changed? */ + + if (nbits != priv->nbits) + { +#if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX) || \ + defined(CONFIG_STM32_STM32G4XXX) + /* Yes... Set CR2 appropriately */ + + /* Set the number of bits (valid range 4-16) */ + + if (nbits < 4 || nbits > 16) + { + spierr("ERROR: nbits out of range: %d\n", nbits); + return; + } + + clrbits = SPI_CR2_DS_MASK; + setbits = SPI_CR2_DS(nbits); + + /* If nbits is <=8, then we are in byte mode and FRXTH must be set + * (else, transaction will not complete). + */ + + if (nbits < 9) + { + setbits |= SPI_CR2_FRXTH; /* RX FIFO Threshold = 1 byte */ + } + else + { + clrbits |= SPI_CR2_FRXTH; /* RX FIFO Threshold = 2 bytes */ + } + + spi_modifycr1(priv, 0, SPI_CR1_SPE); + spi_modifycr2(priv, setbits, clrbits); + spi_modifycr1(priv, SPI_CR1_SPE, 0); +#else + /* Yes... Set CR1 appropriately */ + + switch (nbits) + { + case 8: + setbits = 0; + clrbits = SPI_CR1_DFF; + break; + + case 16: + setbits = SPI_CR1_DFF; + clrbits = 0; + break; + + default: + return; + } + + spi_modifycr1(priv, 0, SPI_CR1_SPE); + spi_modifycr1(priv, setbits, clrbits); + spi_modifycr1(priv, SPI_CR1_SPE, 0); +#endif + /* Save the selection so that subsequent re-configurations will be + * faster. + */ + + priv->nbits = nbits; + } +} + +/**************************************************************************** + * Name: spi_hwfeatures + * + * Description: + * Set hardware-specific feature flags. + * + * Input Parameters: + * dev - Device-specific state data + * features - H/W feature flags + * + * Returned Value: + * Zero (OK) if the selected H/W features are enabled; A negated errno + * value if any H/W feature is not supportable. + * + ****************************************************************************/ + +#ifdef CONFIG_SPI_HWFEATURES +static int spi_hwfeatures(struct spi_dev_s *dev, + spi_hwfeatures_t features) +{ +#if defined(CONFIG_SPI_BITORDER) || defined(CONFIG_SPI_TRIGGER) + struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev; +#endif + +#ifdef CONFIG_SPI_BITORDER + uint16_t setbits; + uint16_t clrbits; + + spiinfo("features=%08x\n", features); + + /* Transfer data LSB first? */ + + if ((features & HWFEAT_LSBFIRST) != 0) + { + setbits = SPI_CR1_LSBFIRST; + clrbits = 0; + } + else + { + setbits = 0; + clrbits = SPI_CR1_LSBFIRST; + } + + spi_modifycr1(priv, 0, SPI_CR1_SPE); + spi_modifycr1(priv, setbits, clrbits); + spi_modifycr1(priv, SPI_CR1_SPE, 0); + + features &= ~HWFEAT_LSBFIRST; +#endif + +#ifdef CONFIG_SPI_TRIGGER +/* Turn deferred trigger mode on or off. Only applicable for DMA mode. If a + * transfer is deferred then the DMA will not actually be triggered until a + * subsequent call to SPI_TRIGGER to set it off. The thread will be waiting + * on the transfer completing as normal. + */ + + priv->defertrig = ((features & HWFEAT_TRIGGER) != 0); + features &= ~HWFEAT_TRIGGER; +#endif + + /* Other H/W features are not supported */ + + return (features == 0) ? OK : -ENOSYS; +} +#endif + +/**************************************************************************** + * Name: spi_send + * + * Description: + * Exchange one word on SPI + * + * Input Parameters: + * dev - Device-specific state data + * wd - The word to send. the size of the data is determined by the + * number of bits selected for the SPI interface. + * + * Returned Value: + * response + * + ****************************************************************************/ + +static uint32_t spi_send(struct spi_dev_s *dev, uint32_t wd) +{ + struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev; + uint32_t regval; + uint32_t ret; + + DEBUGASSERT(priv && priv->spibase); + + spi_writeword(priv, (uint32_t)(wd & 0xffff)); + ret = (uint32_t)spi_readword(priv); + + /* Check and clear any error flags + * (Reading from the SR clears the error flags) + */ + + regval = spi_getreg(priv, STM32_SPI_SR_OFFSET); + + spiinfo("Sent: %04" PRIx32 " Return: %04" PRIx32 + " Status: %02" PRIx32 "\n", wd, ret, regval); + UNUSED(regval); + + return ret; +} + +/**************************************************************************** + * Name: spi_exchange (no DMA). aka spi_exchange_nodma + * + * Description: + * Exchange a block of data on SPI without using DMA + * + * REVISIT: + * This function could be much more efficient by exploiting (1) RX and TX + * FIFOs and (2) the STM32 F3 data packing. + * + * Input Parameters: + * dev - Device-specific state data + * txbuffer - A pointer to the buffer of data to be sent + * rxbuffer - A pointer to a buffer in which to receive data + * nwords - the length of data to be exchanged in units of words. + * The wordsize is determined by the number of bits-per-word + * selected for the SPI interface. If nbits <= 8, the data is + * packed into uint8_t's; if nbits >8, the data is packed into + * uint16_t's + * + * Returned Value: + * None + * + ****************************************************************************/ + +#if !defined(CONFIG_STM32_SPI_DMA) || defined(CONFIG_STM32_DMACAPABLE) || \ + defined(CONFIG_STM32_SPI_DMATHRESHOLD) +#if !defined(CONFIG_STM32_SPI_DMA) +static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, + void *rxbuffer, size_t nwords) +#else +static void spi_exchange_nodma(struct spi_dev_s *dev, + const void *txbuffer, + void *rxbuffer, size_t nwords) +#endif +{ + struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev; + DEBUGASSERT(priv && priv->spibase); + + spiinfo("txbuffer=%p rxbuffer=%p nwords=%d\n", txbuffer, rxbuffer, nwords); + + /* 8- or 16-bit mode? */ + + if (priv->nbits > 8) + { + /* 16-bit mode */ + + const uint16_t *src = (const uint16_t *)txbuffer; + uint16_t *dest = (uint16_t *)rxbuffer; + uint16_t word; + + while (nwords-- > 0) + { + /* Get the next word to write. Is there a source buffer? */ + + if (src) + { + word = *src++; + } + else + { + word = 0xffff; + } + + /* Exchange one word */ + + word = (uint16_t)spi_send(dev, (uint32_t)word); + + /* Is there a buffer to receive the return value? */ + + if (dest) + { + *dest++ = word; + } + } + } + else + { + /* 8-bit mode */ + + const uint8_t *src = (const uint8_t *)txbuffer; + uint8_t *dest = (uint8_t *)rxbuffer; + uint8_t word; + + while (nwords-- > 0) + { + /* Get the next word to write. Is there a source buffer? */ + + if (src) + { + word = *src++; + } + else + { + word = 0xff; + } + + /* Exchange one word */ + + word = (uint8_t)spi_send(dev, (uint32_t)word); + + /* Is there a buffer to receive the return value? */ + + if (dest) + { + *dest++ = word; + } + } + } +} +#endif /* !CONFIG_STM32_SPI_DMA || CONFIG_STM32_DMACAPABLE || CONFIG_STM32_SPI_DMATHRESHOLD */ + +/**************************************************************************** + * Name: spi_exchange (with DMA capability) + * + * Description: + * Exchange a block of data on SPI using DMA + * + * Input Parameters: + * dev - Device-specific state data + * txbuffer - A pointer to the buffer of data to be sent + * rxbuffer - A pointer to a buffer in which to receive data + * nwords - the length of data to be exchanged in units of words. + * The wordsize is determined by the number of bits-per-word + * selected for the SPI interface. If nbits <= 8, the data is + * packed into uint8_t's; if nbits >8, the data is packed into + * uint16_t's + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_SPI_DMA +static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, + void *rxbuffer, size_t nwords) +{ + struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev; + void *xbuffer = rxbuffer; + int ret; + + DEBUGASSERT(priv != NULL); + + /* Convert the number of word to a number of bytes */ + + size_t nbytes = (priv->nbits > 8) ? nwords << 1 : nwords; + +#ifdef CONFIG_STM32_SPI_DMATHRESHOLD + /* If this is a small SPI transfer, then let spi_exchange_nodma() do the + * work. + */ + + if (nbytes <= CONFIG_STM32_SPI_DMATHRESHOLD) + { + spi_exchange_nodma(dev, txbuffer, rxbuffer, nwords); + return; + } +#endif + + if ((priv->rxdma == NULL) || (priv->txdma == NULL) || + up_interrupt_context()) + { + /* Invalid DMA channels, or interrupt context, fall + * back to non-DMA method. + */ + + spi_exchange_nodma(dev, txbuffer, rxbuffer, nwords); + return; + } + +#ifdef CONFIG_STM32_DMACAPABLE + if ((txbuffer && priv->txbuf == 0 && + !stm32_dmacapable((uintptr_t)txbuffer, nwords, priv->txccr)) || + (rxbuffer && priv->rxbuf == 0 && + !stm32_dmacapable((uintptr_t)rxbuffer, nwords, priv->rxccr))) + { + /* Unsupported memory region fall back to non-DMA method. */ + + spi_exchange_nodma(dev, txbuffer, rxbuffer, nwords); + } + else +#endif + { + static uint16_t rxdummy = 0xffff; + static const uint16_t txdummy = 0xffff; + const size_t word_size = (priv->nbits > 8) ? 2u : 1u; + const uint8_t *txp; + uint8_t *rxp; + + spiinfo("txbuffer=%p rxbuffer=%p nwords=%zu\n", + txbuffer, rxbuffer, nwords); + DEBUGASSERT(priv && priv->spibase); + + /* Setup DMAs */ + + /* If this bus uses an in-driver buffer we will incur 2 copies, + * The copy cost is << less the non DMA transfer time and having + * the buffer in the driver ensures DMA can be used. This is because + * the API does not support passing the buffer extent so the only + * extent is buffer + the transfer size. These can sizes be less than + * the cache line size, and not aligned and typically greater then 4 + * bytes, which is about the break even point for the DMA IO overhead. + */ + + if (txbuffer && priv->txbuf) + { + if (nbytes > priv->buflen) + { + nbytes = priv->buflen; + } + + memcpy(priv->txbuf, txbuffer, nbytes); + txbuffer = priv->txbuf; + rxbuffer = rxbuffer ? priv->rxbuf : rxbuffer; + + /* Rescale nwords to match the (possibly clamped) nbytes. */ + + nwords = (priv->nbits > 8) ? nbytes >> 1 : nbytes; + } + + txp = (const uint8_t *)txbuffer; + rxp = (uint8_t *)rxbuffer; + ret = OK; + + /* Walk the request in chunks of at most STM32_SPI_DMA_MAX_XFER words. + * The STM32 DMA NDTR/CNDTR transfer-count register is only 16 bits + * wide; submitting more than 65535 transfers in a single descriptor + * silently programs NDTR to (nwords & 0xffff) and on most paths + * results in a stream that never raises transfer-complete, causing + * the SPI driver to block forever in spi_dmarxwait(). Splitting the + * request keeps each descriptor within the hardware limit and lets + * the W25/SD/etc. driver remain agnostic of this constraint. + */ + + while (nwords > 0) + { + size_t chunk = (nwords > STM32_SPI_DMA_MAX_XFER) + ? STM32_SPI_DMA_MAX_XFER + : nwords; + + spi_dmarxsetup(priv, rxp, &rxdummy, chunk); + spi_dmatxsetup(priv, txp, &txdummy, chunk); + +#ifdef CONFIG_SPI_TRIGGER + /* Is deferred triggering in effect? */ + + if (!priv->defertrig) + { + /* No.. Start the DMAs */ + + spi_dmarxstart(priv); + spi_dmatxstart(priv); + } + else + { + /* Yes.. indicate that we are ready to be started. Deferred + * triggering is only meaningful for the first (often only) + * chunk; subsequent chunks must run unconditionally or the + * caller would have to re-arm between chunks. + */ + + priv->trigarmed = true; + } +#else + /* Start the DMAs */ + + spi_dmarxstart(priv); + spi_dmatxstart(priv); +#endif + + /* Then wait for each to complete */ + + ret = spi_dmarxwait(priv); + if (ret < 0) + { + ret = spi_dmatxwait(priv); + } + + if (ret < 0) + { + break; + } + + if (txp != NULL) + { + txp += chunk * word_size; + } + + if (rxp != NULL) + { + rxp += chunk * word_size; + } + + nwords -= chunk; + } + + if (rxbuffer != NULL && priv->rxbuf != NULL && ret >= 0) + { + memcpy(xbuffer, priv->rxbuf, nbytes); + } + +#ifdef CONFIG_SPI_TRIGGER + priv->trigarmed = false; +#endif + } +} +#endif /* CONFIG_STM32_SPI_DMA */ + +/**************************************************************************** + * Name: spi_trigger + * + * Description: + * Trigger a previously configured DMA transfer. + * + * Input Parameters: + * dev - Device-specific state data + * + * Returned Value: + * OK - Trigger was fired + * ENOTSUP - Trigger not fired due to lack of DMA support + * EIO - Trigger not fired because not previously primed + * + ****************************************************************************/ + +#ifdef CONFIG_SPI_TRIGGER +static int spi_trigger(struct spi_dev_s *dev) +{ +#ifdef CONFIG_STM32_SPI_DMA + struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev; + + if (!priv->trigarmed) + { + return -EIO; + } + + spi_dmarxstart(priv); + spi_dmatxstart(priv); + + return OK; +#else + return -ENOSYS; +#endif +} +#endif + +/**************************************************************************** + * Name: spi_sndblock + * + * Description: + * Send a block of data on SPI + * + * Input Parameters: + * dev - Device-specific state data + * txbuffer - A pointer to the buffer of data to be sent + * nwords - the length of data to send from the buffer in number of + * words. + * The wordsize is determined by the number of bits-per-word + * selected for the SPI interface. If nbits <= 8, the data is + * packed into uint8_t's; if nbits >8, the data is packed into + * uint16_t's + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifndef CONFIG_SPI_EXCHANGE +static void spi_sndblock(struct spi_dev_s *dev, + const void *txbuffer, + size_t nwords) +{ + spiinfo("txbuffer=%p nwords=%d\n", txbuffer, nwords); + return spi_exchange(dev, txbuffer, NULL, nwords); +} +#endif + +/**************************************************************************** + * Name: spi_recvblock + * + * Description: + * Receive a block of data from SPI + * + * Input Parameters: + * dev - Device-specific state data + * rxbuffer - A pointer to the buffer in which to receive data + * nwords - the length of data that can be received in the buffer in + * number of words. The wordsize is determined by the number + * of bits-per-word selected for the SPI interface. If + * nbits <= 8, the data is packed into uint8_t's; if nbits >8, + * the data is packed into uint16_t's + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifndef CONFIG_SPI_EXCHANGE +static void spi_recvblock(struct spi_dev_s *dev, + void *rxbuffer, + size_t nwords) +{ + spiinfo("rxbuffer=%p nwords=%d\n", rxbuffer, nwords); + return spi_exchange(dev, NULL, rxbuffer, nwords); +} +#endif + +/**************************************************************************** + * Name: spi_bus_initialize + * + * Description: + * Initialize the selected SPI bus in its default state (Master, 8-bit, + * mode 0, etc.) + * + * Input Parameters: + * priv - private SPI device structure + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void spi_bus_initialize(struct stm32_spidev_s *priv) +{ + uint16_t setbits; + uint16_t clrbits; + +#if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX) || \ + defined(CONFIG_STM32_STM32G4XXX) + /* Configure CR1 and CR2. Default configuration: + * Mode 0: CR1.CPHA=0 and CR1.CPOL=0 + * Master: CR1.MSTR=1 + * 8-bit: CR2.DS=7 + * MSB transmitted first: CR1.LSBFIRST=0 + * Replace NSS with SSI & SSI=1: CR1.SSI=1 CR1.SSM=1 + * (prevents MODF error) + * Two lines full duplex: CR1.BIDIMODE=0 CR1.BIDIOIE=(Don't care) + * and CR1.RXONLY=0 + */ + + clrbits = SPI_CR1_CPHA | SPI_CR1_CPOL | SPI_CR1_BR_MASK | + SPI_CR1_LSBFIRST | SPI_CR1_RXONLY | SPI_CR1_CRCL | + SPI_CR1_BIDIOE | SPI_CR1_BIDIMODE; + setbits = SPI_CR1_MSTR | SPI_CR1_SSI | SPI_CR1_SSM; + spi_modifycr1(priv, setbits, clrbits); + + clrbits = SPI_CR2_DS_MASK; + setbits = SPI_CR2_DS_8BIT | SPI_CR2_FRXTH; /* FRXTH must be high in 8-bit mode */ + spi_modifycr2(priv, setbits, clrbits); +#else + /* Configure CR1. Default configuration: + * Mode 0: CPHA=0 and CPOL=0 + * Master: MSTR=1 + * 8-bit: DFF=0 + * MSB transmitted first: LSBFIRST=0 + * Replace NSS with SSI & SSI=1: SSI=1 SSM=1 (prevents MODF error) + * Two lines full duplex: BIDIMODE=0 BIDIOIE=(Don't care) + * and RXONLY=0 + */ + + clrbits = SPI_CR1_CPHA | SPI_CR1_CPOL | SPI_CR1_BR_MASK | + SPI_CR1_LSBFIRST | SPI_CR1_RXONLY | SPI_CR1_DFF | + SPI_CR1_BIDIOE | SPI_CR1_BIDIMODE; + setbits = SPI_CR1_MSTR | SPI_CR1_SSI | SPI_CR1_SSM; + spi_modifycr1(priv, setbits, clrbits); +#endif + + priv->frequency = 0; + priv->nbits = 8; + priv->mode = SPIDEV_MODE0; + + /* Select a default frequency of approx. 400KHz */ + + spi_setfrequency((struct spi_dev_s *)priv, 400000); + + /* CRCPOLY configuration */ + + spi_putreg(priv, STM32_SPI_CRCPR_OFFSET, 7); + +#ifdef CONFIG_STM32_SPI_DMA + if (priv->rxch && priv->txch) + { + /* Get DMA channels. NOTE: stm32_dmachannel() will always assign the + * DMA channel. If the channel is not available, then + * stm32_dmachannel() will block and wait until the channel becomes + * available. + * WARNING: If you have another device sharing a DMA channel with + * SPI and the code never releases that channel, then the call to + * stm32_dmachannel() will hang forever in this function! + * Don't let your design do that! + */ + + priv->rxdma = stm32_dmachannel(priv->rxch); + priv->txdma = stm32_dmachannel(priv->txch); + DEBUGASSERT(priv->rxdma && priv->txdma); + + spi_modifycr2(priv, SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN, 0); + } + else + { + priv->rxdma = NULL; + priv->txdma = NULL; + } +#endif + + /* Enable SPI */ + + spi_modifycr1(priv, SPI_CR1_SPE, 0); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_spibus_initialize + * + * Description: + * Initialize the selected SPI bus + * + * Input Parameters: + * Port number (for hardware that has multiple SPI interfaces) + * + * Returned Value: + * Valid SPI device structure reference on success; a NULL on failure + * + ****************************************************************************/ + +struct spi_dev_s *stm32_spibus_initialize(int bus) +{ + struct stm32_spidev_s *priv = NULL; + + irqstate_t flags = enter_critical_section(); + +#ifdef CONFIG_STM32_SPI1 + if (bus == 1) + { + /* Select SPI1 */ + + priv = &g_spi1dev; + + /* Only configure if the bus is not already configured */ + + if (!priv->initialized) + { + /* Configure SPI1 pins: SCK, MISO, and MOSI */ + + stm32_configgpio(GPIO_SPI1_SCK); + stm32_configgpio(GPIO_SPI1_MISO); + stm32_configgpio(GPIO_SPI1_MOSI); + + /* Set up default configuration: Master, 8-bit, etc. */ + + spi_bus_initialize(priv); + priv->initialized = true; + } + } + else +#endif +#ifdef CONFIG_STM32_SPI2 + if (bus == 2) + { + /* Select SPI2 */ + + priv = &g_spi2dev; + + /* Only configure if the bus is not already configured */ + + if (!priv->initialized) + { + /* Configure SPI2 pins: SCK, MISO, and MOSI */ + + stm32_configgpio(GPIO_SPI2_SCK); + stm32_configgpio(GPIO_SPI2_MISO); + stm32_configgpio(GPIO_SPI2_MOSI); + + /* Set up default configuration: Master, 8-bit, etc. */ + + spi_bus_initialize(priv); + priv->initialized = true; + } + } + else +#endif +#ifdef CONFIG_STM32_SPI3 + if (bus == 3) + { + /* Select SPI3 */ + + priv = &g_spi3dev; + + /* Only configure if the bus is not already configured */ + + if (!priv->initialized) + { + /* Configure SPI3 pins: SCK, MISO, and MOSI */ + + stm32_configgpio(GPIO_SPI3_SCK); + stm32_configgpio(GPIO_SPI3_MISO); + stm32_configgpio(GPIO_SPI3_MOSI); + + /* Set up default configuration: Master, 8-bit, etc. */ + + spi_bus_initialize(priv); + priv->initialized = true; + } + } + else +#endif +#ifdef CONFIG_STM32_SPI4 + if (bus == 4) + { + /* Select SPI4 */ + + priv = &g_spi4dev; + + /* Only configure if the bus is not already configured */ + + if (!priv->initialized) + { + /* Configure SPI4 pins: SCK, MISO, and MOSI */ + + stm32_configgpio(GPIO_SPI4_SCK); + stm32_configgpio(GPIO_SPI4_MISO); + stm32_configgpio(GPIO_SPI4_MOSI); + + /* Set up default configuration: Master, 8-bit, etc. */ + + spi_bus_initialize(priv); + priv->initialized = true; + } + } + else +#endif +#ifdef CONFIG_STM32_SPI5 + if (bus == 5) + { + /* Select SPI5 */ + + priv = &g_spi5dev; + + /* Only configure if the bus is not already configured */ + + if (!priv->initialized) + { + /* Configure SPI5 pins: SCK, MISO, and MOSI */ + + stm32_configgpio(GPIO_SPI5_SCK); + stm32_configgpio(GPIO_SPI5_MISO); + stm32_configgpio(GPIO_SPI5_MOSI); + + /* Set up default configuration: Master, 8-bit, etc. */ + + spi_bus_initialize(priv); + priv->initialized = true; + } + } + else +#endif +#ifdef CONFIG_STM32_SPI6 + if (bus == 6) + { + /* Select SPI6 */ + + priv = &g_spi6dev; + + /* Only configure if the bus is not already configured */ + + if (!priv->initialized) + { + /* Configure SPI6 pins: SCK, MISO, and MOSI */ + + stm32_configgpio(GPIO_SPI6_SCK); + stm32_configgpio(GPIO_SPI6_MISO); + stm32_configgpio(GPIO_SPI6_MOSI); + + /* Set up default configuration: Master, 8-bit, etc. */ + + spi_bus_initialize(priv); + priv->initialized = true; + } + } + else +#endif + { + spierr("ERROR: Unsupported SPI bus: %d\n", bus); + } + + leave_critical_section(flags); + return (struct spi_dev_s *)priv; +} + +#endif /* CONFIG_STM32_SPI1 || CONFIG_STM32_SPI2 || CONFIG_STM32_SPI3 || + * CONFIG_STM32_SPI4 || CONFIG_STM32_SPI5 || CONFIG_STM32_SPI6 + */ diff --git a/arch/arm/src/common/stm32/stm32_start.h b/arch/arm/src/common/stm32/stm32_start.h new file mode 100644 index 0000000000000..ad9bbda5e31f1 --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_start.h @@ -0,0 +1,64 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_start.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_START_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_START_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#ifndef __ASSEMBLY__ +#ifdef __cplusplus +extern "C" +{ +#endif + +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_boardinitialize + * + * Description: + * All STM32 architectures must provide the following entry point. This + * entry point is called early in the initialization -- after all memory + * has been configured and mapped but before any devices have been + * initialized. + * + ****************************************************************************/ + +void stm32_boardinitialize(void); + +#ifdef __cplusplus +} +#endif +#endif /* __ASSEMBLY__ */ + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_START_H */ diff --git a/arch/arm/src/common/stm32/stm32_start_m0_v1.c b/arch/arm/src/common/stm32/stm32_start_m0_v1.c new file mode 100644 index 0000000000000..b2585f49bc627 --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_start_m0_v1.c @@ -0,0 +1,157 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_start_m0_v1.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "arm_internal.h" +#include "stm32_rcc.h" +#include "stm32_lowputc.h" +#include "stm32_start.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define IDLE_STACK ((uint32_t)_ebss + CONFIG_IDLETHREAD_STACKSIZE) + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +const uintptr_t g_idle_topstack = IDLE_STACK; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: showprogress + * + * Description: + * Print a character on the CONSOLE USART to show boot status. + * + ****************************************************************************/ + +#ifdef CONFIG_DEBUG_FEATURES +# define showprogress(c) arm_lowputc(c) +#else +# define showprogress(c) +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: __start + * + * Description: + * This is the reset entry point. + * + ****************************************************************************/ + +void __start(void) +{ + const uint32_t *src; + uint32_t *dest; + + /* Configure the uart so that we can get debug output as soon as possible */ + + stm32_clockconfig(); + stm32_lowsetup(); + showprogress('A'); + + /* Clear .bss. We'll do this inline (vs. calling memset) just to be + * certain that there are no issues with the state of global variables. + */ + + for (dest = (uint32_t *)_sbss; dest < (uint32_t *)_ebss; ) + { + *dest++ = 0; + } + + showprogress('B'); + + /* Move the initialized data section from his temporary holding spot in + * FLASH into the correct place in SRAM. The correct place in SRAM is + * give by _sdata and _edata. The temporary location is in FLASH at the + * end of all of the other read-only data (.text, .rodata) at _eronly. + */ + + for (src = (const uint32_t *)_eronly, + dest = (uint32_t *)_sdata; dest < (uint32_t *)_edata; + ) + { + *dest++ = *src++; + } + + showprogress('C'); + +#ifdef CONFIG_ARCH_PERF_EVENTS + up_perf_init((void *)STM32_SYSCLK_FREQUENCY); +#endif + + /* Perform early serial initialization */ + +#ifdef USE_EARLYSERIALINIT + arm_earlyserialinit(); +#endif + showprogress('D'); + + /* For the case of the separate user-/kernel-space build, perform whatever + * platform specific initialization of the user memory is required. + * Normally this just means initializing the user space .data and .bss + * segments. + */ + +#ifdef CONFIG_BUILD_PROTECTED + stm32_userspace(); + showprogress('E'); +#endif + + /* Initialize onboard resources */ + + stm32_boardinitialize(); + showprogress('F'); + + /* Then start NuttX */ + + showprogress('\r'); + showprogress('\n'); + + nx_start(); + + /* Shouldn't get here */ + + for (; ; ); +} diff --git a/arch/arm/src/common/stm32/stm32_start_m3m4_v1.c b/arch/arm/src/common/stm32/stm32_start_m3m4_v1.c new file mode 100644 index 0000000000000..ad74f104e3c61 --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_start_m3m4_v1.c @@ -0,0 +1,213 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_start_m3m4_v1.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include + +#include "arch/board/board.h" +#include "arm_internal.h" +#include "itm_syslog.h" +#include "nvic.h" +#include "mpu.h" + +#include "stm32.h" +#include "stm32_gpio.h" +#include "stm32_userspace.h" +#include "stm32_start.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* .data is positioned first in the primary RAM followed immediately by .bss. + * The IDLE thread stack lies just after .bss and has size give by + * CONFIG_IDLETHREAD_STACKSIZE; The heap then begins just after the IDLE. + * ARM EABI requires 64 bit stack alignment. + */ + +#define HEAP_BASE ((uintptr_t)_ebss + CONFIG_IDLETHREAD_STACKSIZE) + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/* g_idle_topstack: _sbss is the start of the BSS region as defined by the + * linker script. _ebss lies at the end of the BSS region. The idle task + * stack starts at the end of BSS and is of size CONFIG_IDLETHREAD_STACKSIZE. + * The IDLE thread is the thread that the system boots on and, eventually, + * becomes the IDLE, do nothing task that runs only when there is nothing + * else to run. The heap continues from there until the end of memory. + * g_idle_topstack is a read-only variable the provides this computed + * address. + */ + +const uintptr_t g_idle_topstack = HEAP_BASE; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: showprogress + * + * Description: + * Print a character on the UART to show boot status. + * + ****************************************************************************/ + +#ifdef CONFIG_DEBUG_FEATURES +# define showprogress(c) arm_lowputc(c) +#else +# define showprogress(c) +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +#ifdef CONFIG_ARMV7M_STACKCHECK +/* we need to get r10 set before we can allow instrumentation calls */ + +void __start(void) noinstrument_function; +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: __start + * + * Description: + * This is the reset entry point. + * + ****************************************************************************/ + +void __start(void) +{ + const uint32_t *src; + uint32_t *dest; + +#ifdef CONFIG_ARMV7M_STACKCHECK + /* Set the stack limit before we attempt to call any functions */ + + __asm__ volatile("sub r10, sp, %0" : : + "r"(CONFIG_IDLETHREAD_STACKSIZE - 64) :); +#endif + + /* If enabled reset the MPU */ + + mpu_early_reset(); + + /* Configure the UART so that we can get debug output as soon as possible */ + + stm32_clockconfig(); + arm_fpuconfig(); + stm32_lowsetup(); + stm32_gpioinit(); + showprogress('A'); + + /* Clear .bss. We'll do this inline (vs. calling memset) just to be + * certain that there are no issues with the state of global variables. + */ + + for (dest = (uint32_t *)_START_BSS; dest < (uint32_t *)_END_BSS; ) + { + *dest++ = 0; + } + + showprogress('B'); + + /* Move the initialized data section from his temporary holding spot in + * FLASH into the correct place in SRAM. The correct place in SRAM is + * give by _sdata and _edata. The temporary location is in FLASH at the + * end of all of the other read-only data (.text, .rodata) at _eronly. + */ + + for (src = (const uint32_t *)_DATA_INIT, + dest = (uint32_t *)_START_DATA; dest < (uint32_t *)_END_DATA; + ) + { + *dest++ = *src++; + } + + showprogress('C'); + +#ifdef CONFIG_ARMV7M_STACKCHECK + arm_stack_check_init(); +#endif + +#ifdef CONFIG_ARCH_PERF_EVENTS + up_perf_init((void *)STM32_SYSCLK_FREQUENCY); +#endif + +#ifdef CONFIG_ARMV7M_ITMSYSLOG + /* Perform ARMv7-M ITM SYSLOG initialization */ + + itm_syslog_initialize(); +#endif + + /* Perform early serial initialization */ + +#ifdef USE_EARLYSERIALINIT + arm_earlyserialinit(); +#endif + showprogress('D'); + + /* For the case of the separate user-/kernel-space build, perform whatever + * platform specific initialization of the user memory is required. + * Normally this just means initializing the user space .data and .bss + * segments. + */ + +#ifdef CONFIG_BUILD_PROTECTED + stm32_userspace(); + showprogress('E'); +#endif + + /* Initialize onboard resources */ + + stm32_boardinitialize(); + showprogress('F'); + + /* Then start NuttX */ + + showprogress('\r'); + showprogress('\n'); + + nx_start(); + + /* Shouldn't get here */ + +#ifndef CONFIG_DISABLE_IDLE_LOOP + for (; ; ); +#endif +} diff --git a/arch/arm/src/common/stm32/stm32_syscfg.h b/arch/arm/src/common/stm32/stm32_syscfg.h new file mode 100644 index 0000000000000..1e95d770342d8 --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_syscfg.h @@ -0,0 +1,53 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_syscfg.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_SYSCFG_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_SYSCFG_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include "chip.h" + +#if defined(CONFIG_STM32_STM32L15XX) +# include "hardware/stm32l15xxx_syscfg.h" +#elif defined(CONFIG_STM32_STM32F20XX) +# include "hardware/stm32f20xxx_syscfg.h" +#elif defined(CONFIG_STM32_STM32F30XX) +# include "hardware/stm32f30xxx_syscfg.h" +#elif defined(CONFIG_STM32_STM32F33XX) +# include "hardware/stm32f33xxx_syscfg.h" +#elif defined(CONFIG_STM32_STM32F37XX) +# include "hardware/stm32f37xxx_syscfg.h" +#elif defined(CONFIG_STM32_STM32F4XXX) +# include "hardware/stm32f40xxx_syscfg.h" +#elif defined(CONFIG_STM32_STM32G4XXX) +# include "hardware/stm32g4xxxx_syscfg.h" +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_SYSCFG_H */ diff --git a/arch/arm/src/common/stm32/stm32_tickless_m3m4_v1.c b/arch/arm/src/common/stm32/stm32_tickless_m3m4_v1.c new file mode 100644 index 0000000000000..1e49c2a3cb3d8 --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_tickless_m3m4_v1.c @@ -0,0 +1,974 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_tickless_m3m4_v1.c + * + * SPDX-License-Identifier: BSD-3-Clause + * SPDX-FileCopyrightText: 2016-2017 Gregory Nutt. All rights reserved. + * SPDX-FileCopyrightText: 2017 Ansync Labs. All rights reserved. + * SPDX-FileContributor: Gregory Nutt + * SPDX-FileContributor: Konstantin Berezenko + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Tickless OS Support. + * + * When CONFIG_SCHED_TICKLESS is enabled, all support for timer interrupts + * is suppressed and the platform specific code is expected to provide the + * following custom functions. + * + * void up_timer_initialize(void): Initializes the timer facilities. + * Called early in the initialization sequence (by up_initialize()). + * int up_timer_gettime(struct timespec *ts): Returns the current + * time from the platform specific time source. + * int up_timer_cancel(void): Cancels the interval timer. + * int up_timer_start(const struct timespec *ts): Start (or re-starts) + * the interval timer. + * + * The RTOS will provide the following interfaces for use by the platform- + * specific interval timer implementation: + * + * void nxsched_process_timer(void): Called by the platform-specific + * logic when the interval timer expires. + * + ****************************************************************************/ + +/**************************************************************************** + * STM32 Timer Usage + * + * This implementation uses one timer: A free running timer to provide + * the current time and a capture/compare channel for timed-events. + * + * BASIC timers that are found on some STM32 chips (timers 6 and 7) are + * incompatible with this implementation because they don't have capture/ + * compare channels. There are two interrupts generated from our timer, + * the overflow interrupt which drives the timing handler and the capture/ + * compare interrupt which drives the interval handler. There are some low + * level timer control functions implemented here because the API of + * stm32_tim.c does not provide adequate control over capture/compare + * interrupts. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include + +#include "arm_internal.h" +#include "stm32_tim.h" + +#ifdef CONFIG_SCHED_TICKLESS + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Only TIM2 and TIM5 timers may be 32-bits in width + * + * Reference Table 2 of en.DM00042534.pdf + */ + +#undef HAVE_32BIT_TICKLESS + +#if (CONFIG_STM32_TICKLESS_TIMER == 2 && \ + !defined(STM32_STM32F10XX) && \ + !defined(STM32_STM32L15XX)) \ + || (CONFIG_STM32_TICKLESS_TIMER == 5 && \ + !defined(STM32_STM32F10XX)) + #define HAVE_32BIT_TICKLESS 1 +#endif + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +struct stm32_tickless_s +{ + uint8_t timer; /* The timer/counter in use */ + uint8_t channel; /* The timer channel to use for intervals */ + struct stm32_tim_dev_s *tch; /* Handle returned by stm32_tim_init() */ + uint32_t frequency; + uint32_t overflow; /* Timer counter overflow */ + volatile bool pending; /* True: pending task */ + uint32_t period; /* Interval period */ + uint32_t base; +}; + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static struct stm32_tickless_s g_tickless; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_getreg16 + * + * Description: + * Get a 16-bit register value by offset + * + ****************************************************************************/ + +static inline uint16_t stm32_getreg16(uint8_t offset) +{ + return getreg16(g_tickless.base + offset); +} + +/**************************************************************************** + * Name: stm32_putreg16 + * + * Description: + * Put a 16-bit register value by offset + * + ****************************************************************************/ + +static inline void stm32_putreg16(uint8_t offset, uint16_t value) +{ + putreg16(value, g_tickless.base + offset); +} + +/**************************************************************************** + * Name: stm32_modifyreg16 + * + * Description: + * Modify a 16-bit register value by offset + * + ****************************************************************************/ + +static inline void stm32_modifyreg16(uint8_t offset, uint16_t clearbits, + uint16_t setbits) +{ + modifyreg16(g_tickless.base + offset, clearbits, setbits); +} + +/**************************************************************************** + * Name: stm32_tickless_enableint + ****************************************************************************/ + +static inline void stm32_tickless_enableint(int channel) +{ + stm32_modifyreg16(STM32_BTIM_DIER_OFFSET, 0, 1 << channel); +} + +/**************************************************************************** + * Name: stm32_tickless_disableint + ****************************************************************************/ + +static inline void stm32_tickless_disableint(int channel) +{ + stm32_modifyreg16(STM32_BTIM_DIER_OFFSET, 1 << channel, 0); +} + +/**************************************************************************** + * Name: stm32_tickless_ackint + ****************************************************************************/ + +static inline void stm32_tickless_ackint(int channel) +{ + stm32_putreg16(STM32_BTIM_SR_OFFSET, ~(1 << channel)); +} + +/**************************************************************************** + * Name: stm32_tickless_getint + ****************************************************************************/ + +static inline uint16_t stm32_tickless_getint(void) +{ + return stm32_getreg16(STM32_BTIM_SR_OFFSET); +} + +/**************************************************************************** + * Name: stm32_tickless_setchannel + ****************************************************************************/ + +static int stm32_tickless_setchannel(uint8_t channel) +{ + uint16_t ccmr_orig = 0; + uint16_t ccmr_val = 0; + uint16_t ccmr_mask = 0xff; + uint16_t ccer_val = stm32_getreg16(STM32_GTIM_CCER_OFFSET); + uint8_t ccmr_offset = STM32_GTIM_CCMR1_OFFSET; + + /* Further we use range as 0..3; if channel=0 it will also overflow here */ + + if (--channel > 4) + { + return -EINVAL; + } + + /* Assume that channel is disabled and polarity is active high */ + + ccer_val &= ~((GTIM_CCER_CC1P | GTIM_CCER_CC1E) << + GTIM_CCER_CCXBASE(channel)); + + /* This function is not supported on basic timers. To enable or + * disable it, simply set its clock to valid frequency or zero. + */ + +#if STM32_NBTIM > 0 + if (g_tickless.base == STM32_TIM6_BASE +#endif +#if STM32_NBTIM > 1 + || g_tickless.base == STM32_TIM7_BASE +#endif +#if STM32_NBTIM > 0 + ) + { + return -EINVAL; + } +#endif + + /* Frozen mode because we don't want to change the GPIO, preload register + * disabled. + */ + + ccmr_val = (ATIM_CCMR_MODE_FRZN << ATIM_CCMR1_OC1M_SHIFT); + + /* Set polarity */ + + ccer_val |= ATIM_CCER_CC1P << GTIM_CCER_CCXBASE(channel); + + /* Define its position (shift) and get register offset */ + + if ((channel & 1) != 0) + { + ccmr_val <<= 8; + ccmr_mask <<= 8; + } + + if (channel > 1) + { + ccmr_offset = STM32_GTIM_CCMR2_OFFSET; + } + + ccmr_orig = stm32_getreg16(ccmr_offset); + ccmr_orig &= ~ccmr_mask; + ccmr_orig |= ccmr_val; + stm32_putreg16(ccmr_offset, ccmr_orig); + stm32_putreg16(STM32_GTIM_CCER_OFFSET, ccer_val); + + return OK; +} + +/**************************************************************************** + * Name: stm32_interval_handler + * + * Description: + * Called when the timer counter matches the compare register + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + * Assumptions: + * Called early in the initialization sequence before any special + * concurrency protections are required. + * + ****************************************************************************/ + +static void stm32_interval_handler(void) +{ + tmrinfo("Expired...\n"); + + /* Disable the compare interrupt now. */ + + stm32_tickless_disableint(g_tickless.channel); + stm32_tickless_ackint(g_tickless.channel); + + g_tickless.pending = false; + + nxsched_process_timer(); +} + +/**************************************************************************** + * Name: stm32_timing_handler + * + * Description: + * Timer interrupt callback. When the freerun timer counter overflows, + * this interrupt will occur. We will just increment an overflow count. + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void stm32_timing_handler(void) +{ + g_tickless.overflow++; + + STM32_TIM_ACKINT(g_tickless.tch, GTIM_SR_UIF); +} + +/**************************************************************************** + * Name: stm32_tickless_handler + * + * Description: + * Generic interrupt handler for this timer. It checks the source of the + * interrupt and fires the appropriate handler. + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +static int stm32_tickless_handler(int irq, void *context, void *arg) +{ + int interrupt_flags = stm32_tickless_getint(); + + if (interrupt_flags & ATIM_SR_UIF) + { + stm32_timing_handler(); + } + + if (interrupt_flags & (1 << g_tickless.channel)) + { + stm32_interval_handler(); + } + + return OK; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_timer_initialize + * + * Description: + * Initializes all platform-specific timer facilities. This function is + * called early in the initialization sequence by up_initialize(). + * On return, the current up-time should be available from + * up_timer_gettime() and the interval timer is ready for use (but not + * actively timing. + * + * Provided by platform-specific code and called from the architecture- + * specific logic. + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + * Assumptions: + * Called early in the initialization sequence before any special + * concurrency protections are required. + * + ****************************************************************************/ + +void up_timer_initialize(void) +{ + switch (CONFIG_STM32_TICKLESS_TIMER) + { +#ifdef CONFIG_STM32_TIM1 + case 1: + g_tickless.base = STM32_TIM1_BASE; + break; +#endif + +#ifdef CONFIG_STM32_TIM2 + case 2: + g_tickless.base = STM32_TIM2_BASE; + break; +#endif + +#ifdef CONFIG_STM32_TIM3 + case 3: + g_tickless.base = STM32_TIM3_BASE; + break; +#endif + +#ifdef CONFIG_STM32_TIM4 + case 4: + g_tickless.base = STM32_TIM4_BASE; + break; +#endif +#ifdef CONFIG_STM32_TIM5 + case 5: + g_tickless.base = STM32_TIM5_BASE; + break; +#endif + +#ifdef CONFIG_STM32_TIM6 + case 6: + + /* Basic timers not supported by this implementation */ + + DEBUGPANIC(); + break; +#endif + +#ifdef CONFIG_STM32_TIM7 + case 7: + + /* Basic timers not supported by this implementation */ + + DEBUGPANIC(); + break; +#endif + +#ifdef CONFIG_STM32_TIM8 + case 8: + g_tickless.base = STM32_TIM8_BASE; + break; +#endif + +#ifdef CONFIG_STM32_TIM9 + case 9: + g_tickless.base = STM32_TIM9_BASE; + break; +#endif +#ifdef CONFIG_STM32_TIM10 + case 10: + g_tickless.base = STM32_TIM10_BASE; + break; +#endif + +#ifdef CONFIG_STM32_TIM11 + case 11: + g_tickless.base = STM32_TIM11_BASE; + break; +#endif +#ifdef CONFIG_STM32_TIM12 + case 12: + g_tickless.base = STM32_TIM12_BASE; + break; +#endif +#ifdef CONFIG_STM32_TIM13 + case 13: + g_tickless.base = STM32_TIM13_BASE; + break; +#endif + +#ifdef CONFIG_STM32_TIM14 + case 14: + g_tickless.base = STM32_TIM14_BASE; + break; +#endif +#ifdef CONFIG_STM32_TIM15 + case 15: + g_tickless.base = STM32_TIM15_BASE; + break; +#endif + +#ifdef CONFIG_STM32_TIM16 + case 16: + g_tickless.base = STM32_TIM16_BASE; + break; +#endif + +#ifdef CONFIG_STM32_TIM17 + case 17: + g_tickless.base = STM32_TIM17_BASE; + break; +#endif + + default: + DEBUGPANIC(); + } + + /* Get the TC frequency that corresponds to the requested resolution */ + + g_tickless.frequency = USEC_PER_SEC / (uint32_t)CONFIG_USEC_PER_TICK; + g_tickless.timer = CONFIG_STM32_TICKLESS_TIMER; + g_tickless.channel = CONFIG_STM32_TICKLESS_CHANNEL; + g_tickless.pending = false; + g_tickless.period = 0; + g_tickless.overflow = 0; + + tmrinfo("timer=%d channel=%d frequency=%lu Hz\n", + g_tickless.timer, g_tickless.channel, g_tickless.frequency); + + g_tickless.tch = stm32_tim_init(g_tickless.timer); + if (!g_tickless.tch) + { + tmrerr("ERROR: Failed to allocate TIM%d\n", g_tickless.timer); + DEBUGPANIC(); + } + + STM32_TIM_SETCLOCK(g_tickless.tch, g_tickless.frequency); + + /* Set up to receive the callback when the counter overflow occurs */ + + STM32_TIM_SETISR(g_tickless.tch, stm32_tickless_handler, NULL, 0); + + /* Initialize interval to zero */ + + STM32_TIM_SETCOMPARE(g_tickless.tch, g_tickless.channel, 0); + + /* Setup compare channel for the interval timing */ + + stm32_tickless_setchannel(g_tickless.channel); + + /* Set timer period */ + +#ifdef HAVE_32BIT_TICKLESS + STM32_TIM_SETPERIOD(g_tickless.tch, UINT32_MAX); +#ifdef CONFIG_SCHED_TICKLESS_LIMIT_MAX_SLEEP + g_oneshot_maxticks = UINT32_MAX; +#endif +#else + STM32_TIM_SETPERIOD(g_tickless.tch, UINT16_MAX); +#ifdef CONFIG_SCHED_TICKLESS_LIMIT_MAX_SLEEP + g_oneshot_maxticks = UINT16_MAX; +#endif +#endif + + /* Initialize the counter */ + + STM32_TIM_SETMODE(g_tickless.tch, STM32_TIM_MODE_UP); + + /* Start the timer */ + + STM32_TIM_ACKINT(g_tickless.tch, ~0); + STM32_TIM_ENABLEINT(g_tickless.tch, GTIM_DIER_UIE); +} + +/**************************************************************************** + * Name: up_timer_gettime + * + * Description: + * Return the elapsed time since power-up (or, more correctly, since + * up_timer_initialize() was called). This function is functionally + * equivalent to: + * + * int clock_gettime(clockid_t clockid, struct timespec *ts); + * + * when clockid is CLOCK_MONOTONIC. + * + * This function provides the basis for reporting the current time and + * also is used to eliminate error build-up from small errors in interval + * time calculations. + * + * Provided by platform-specific code and called from the RTOS base code. + * + * Input Parameters: + * ts - Provides the location in which to return the up-time. + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned on + * any failure. + * + * Assumptions: + * Called from the normal tasking context. The implementation must + * provide whatever mutual exclusion is necessary for correct operation. + * This can include disabling interrupts in order to assure atomic register + * operations. + * + ****************************************************************************/ + +int up_timer_gettime(struct timespec *ts) +{ + uint64_t usec; + uint32_t counter; + uint32_t verify; + uint32_t overflow; + uint32_t sec; + int pending; + irqstate_t flags; + + DEBUGASSERT(ts); + + /* Timer not initialized yet, return zero */ + + if (g_tickless.tch == 0) + { + ts->tv_nsec = 0; + ts->tv_sec = 0; + return OK; + } + + /* Temporarily disable the overflow counter. NOTE that we have to be + * careful here because stm32_tc_getpending() will reset the pending + * interrupt status. If we do not handle the overflow here then, it will + * be lost. + */ + + flags = enter_critical_section(); + + overflow = g_tickless.overflow; + counter = STM32_TIM_GETCOUNTER(g_tickless.tch); + pending = STM32_TIM_CHECKINT(g_tickless.tch, GTIM_SR_UIF); + verify = STM32_TIM_GETCOUNTER(g_tickless.tch); + + /* If an interrupt was pending before we re-enabled interrupts, + * then the overflow needs to be incremented. + */ + + if (pending) + { + STM32_TIM_ACKINT(g_tickless.tch, GTIM_SR_UIF); + + /* Increment the overflow count and use the value of the + * guaranteed to be AFTER the overflow occurred. + */ + + overflow++; + counter = verify; + + /* Update tickless overflow counter. */ + + g_tickless.overflow = overflow; + } + + leave_critical_section(flags); + + tmrinfo("counter=%lu (%lu) overflow=%lu, pending=%i\n", + (unsigned long)counter, (unsigned long)verify, + (unsigned long)overflow, pending); + tmrinfo("frequency=%lu\n", g_tickless.frequency); + + /* Convert the whole thing to units of microseconds. + * + * frequency = ticks / second + * seconds = ticks * frequency + * usecs = (ticks * USEC_PER_SEC) / frequency; + */ +#ifdef HAVE_32BIT_TICKLESS + usec = ((((uint64_t)overflow << 32) + (uint64_t)counter) * USEC_PER_SEC) / + g_tickless.frequency; +#else + usec = ((((uint64_t)overflow << 16) + (uint64_t)counter) * USEC_PER_SEC) / + g_tickless.frequency; +#endif + + /* And return the value of the timer */ + + sec = (uint32_t)(usec / USEC_PER_SEC); + ts->tv_sec = sec; + ts->tv_nsec = (usec - (sec * USEC_PER_SEC)) * NSEC_PER_USEC; + + tmrinfo("usec=%llu ts=(%jd, %ld)\n", + usec, (intmax_t)ts->tv_sec, ts->tv_nsec); + + return OK; +} + +#ifdef CONFIG_CLOCK_TIMEKEEPING + +/**************************************************************************** + * Name: up_timer_gettick + * + * Description: + * To be provided + * + * Input Parameters: + * cycles - 64-bit return value + * + * Returned Value: + * None + * + ****************************************************************************/ + +int up_timer_gettick(clock_t *ticks) +{ + *ticks = STM32_TIM_GETCOUNTER(g_tickless.tch); + return OK; +} + +/**************************************************************************** + * Name: up_timer_getmask + * + * Description: + * To be provided + * + * Input Parameters: + * mask - Location to return the 64-bit mask + * + * Returned Value: + * None + * + ****************************************************************************/ + +void up_timer_getmask(clock_t *mask) +{ + DEBUGASSERT(mask != NULL); +#ifdef HAVE_32BIT_TICKLESS + *mask = UINT32_MAX; +#else + *mask = UINT16_MAX; +#endif +} + +#endif /* CONFIG_CLOCK_TIMEKEEPING */ + +/**************************************************************************** + * Name: up_timer_cancel + * + * Description: + * Cancel the interval timer and return the time remaining on the timer. + * These two steps need to be as nearly atomic as possible. + * nxsched_process_timer() will not be called unless the timer is + * restarted with up_timer_start(). + * + * If, as a race condition, the timer has already expired when this + * function is called, then that pending interrupt must be cleared so + * that up_timer_start() and the remaining time of zero should be + * returned. + * + * NOTE: This function may execute at a high rate with no timer running (as + * when pre-emption is enabled and disabled). + * + * Provided by platform-specific code and called from the RTOS base code. + * + * Input Parameters: + * ts - Location to return the remaining time. Zero should be returned + * if the timer is not active. ts may be zero in which case the + * time remaining is not returned. + * + * Returned Value: + * Zero (OK) is returned on success. A call to up_timer_cancel() when + * the timer is not active should also return success; a negated errno + * value is returned on any failure. + * + * Assumptions: + * May be called from interrupt level handling or from the normal tasking + * level. Interrupts may need to be disabled internally to assure + * non-reentrancy. + * + ****************************************************************************/ + +int up_timer_cancel(struct timespec *ts) +{ + irqstate_t flags; + uint64_t usec; + uint64_t sec; + uint64_t nsec; + uint32_t count; + uint32_t period; + + /* Was the timer running? */ + + flags = enter_critical_section(); + if (!g_tickless.pending) + { + /* No.. Just return zero timer remaining and successful cancellation. + * This function may execute at a high rate with no timer running + * (as when pre-emption is enabled and disabled). + */ + + if (ts) + { + ts->tv_sec = 0; + ts->tv_nsec = 0; + } + + leave_critical_section(flags); + return OK; + } + + /* Yes.. Get the timer counter and period registers and disable the compare + * interrupt. + */ + + tmrinfo("Cancelling...\n"); + + /* Disable the interrupt. */ + + stm32_tickless_disableint(g_tickless.channel); + + count = STM32_TIM_GETCOUNTER(g_tickless.tch); + period = g_tickless.period; + + g_tickless.pending = false; + leave_critical_section(flags); + + /* Did the caller provide us with a location to return the time + * remaining? + */ + + if (ts != NULL) + { + /* Yes.. then calculate and return the time remaining on the + * oneshot timer. + */ + + tmrinfo("period=%lu count=%lu\n", + (unsigned long)period, (unsigned long)count); + +#ifndef HAVE_32BIT_TICKLESS + if (count > period) + { + /* Handle rollover */ + + period += UINT16_MAX; + } + else if (count == period) +#else + if (count >= period) +#endif + { + /* No time remaining */ + + ts->tv_sec = 0; + ts->tv_nsec = 0; + return OK; + } + + /* The total time remaining is the difference. Convert that + * to units of microseconds. + * + * frequency = ticks / second + * seconds = ticks * frequency + * usecs = (ticks * USEC_PER_SEC) / frequency; + */ + + usec = (((uint64_t)(period - count)) * USEC_PER_SEC) / + g_tickless.frequency; + + /* Return the time remaining in the correct form */ + + sec = usec / USEC_PER_SEC; + nsec = ((usec) - (sec * USEC_PER_SEC)) * NSEC_PER_USEC; + + ts->tv_sec = sec; + ts->tv_nsec = nsec; + + tmrinfo("remaining (%jd, %ld)\n", + (intmax_t)ts->tv_sec, ts->tv_nsec); + } + + return OK; +} + +/**************************************************************************** + * Name: up_timer_start + * + * Description: + * Start the interval timer. nxsched_process_timer() will be + * called at the completion of the timeout (unless up_timer_cancel + * is called to stop the timing. + * + * Provided by platform-specific code and called from the RTOS base code. + * + * Input Parameters: + * ts - Provides the time interval until nxsched_process_timer() is + * called. + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned on + * any failure. + * + * Assumptions: + * May be called from interrupt level handling or from the normal tasking + * level. Interrupts may need to be disabled internally to assure + * non-reentrancy. + * + ****************************************************************************/ + +int up_timer_start(const struct timespec *ts) +{ + uint64_t usec; + uint64_t period; + uint32_t count; + irqstate_t flags; + + tmrinfo("ts=(%jd, %ld)\n", + (intmax_t)ts->tv_sec, ts->tv_nsec); + DEBUGASSERT(ts); + DEBUGASSERT(g_tickless.tch); + + /* Was an interval already running? */ + + flags = enter_critical_section(); + if (g_tickless.pending) + { + /* Yes.. then cancel it */ + + tmrinfo("Already running... cancelling\n"); + up_timer_cancel(NULL); + } + + /* Express the delay in microseconds */ + + usec = ts->tv_sec * USEC_PER_SEC + + (ts->tv_nsec / NSEC_PER_USEC); + + /* Get the timer counter frequency and determine the number of counts need + * to achieve the requested delay. + * + * frequency = ticks / second + * ticks = seconds * frequency + * = (usecs * frequency) / USEC_PER_SEC; + */ + + period = (usec * (uint64_t)g_tickless.frequency) / USEC_PER_SEC; + count = STM32_TIM_GETCOUNTER(g_tickless.tch); + + tmrinfo("usec=%llu period=%08llx\n", usec, period); + + /* Set interval compare value. Rollover is fine, + * channel will trigger on the next period. + */ + +#ifdef HAVE_32BIT_TICKLESS + DEBUGASSERT(period <= UINT32_MAX); + g_tickless.period = (uint32_t)(period + count); +#else + DEBUGASSERT(period <= UINT16_MAX); + g_tickless.period = (uint16_t)(period + count); +#endif + + STM32_TIM_SETCOMPARE(g_tickless.tch, g_tickless.channel, + g_tickless.period); + + /* Enable interrupts. We should get the callback when the interrupt + * occurs. + */ + + stm32_tickless_ackint(g_tickless.channel); + stm32_tickless_enableint(g_tickless.channel); + + g_tickless.pending = true; + leave_critical_section(flags); + return OK; +} +#endif /* CONFIG_SCHED_TICKLESS */ diff --git a/arch/arm/src/common/stm32/stm32_tim.h b/arch/arm/src/common/stm32/stm32_tim.h new file mode 100644 index 0000000000000..77d884e06727a --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_tim.h @@ -0,0 +1,42 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_tim.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_COMPAT_STM32_TIM_H +#define __ARCH_ARM_SRC_COMMON_COMPAT_STM32_TIM_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#if defined(CONFIG_STM32_HAVE_IP_TIMERS_M0_V1) +# include "stm32_tim_m0_v1.h" +#elif defined(CONFIG_STM32_HAVE_IP_TIMERS_M3M4_V1) || \ + defined(CONFIG_STM32_HAVE_IP_TIMERS_M3M4_V2) || \ + defined(CONFIG_STM32_HAVE_IP_TIMERS_M3M4_V3) +# include "stm32_tim_m3m4_v1v2v3.h" +#else +# error "Unsupported STM32 TIM" +#endif + +#endif /* __ARCH_ARM_SRC_COMMON_COMPAT_STM32_TIM_H */ diff --git a/arch/arm/src/common/stm32/stm32_tim_m0_v1.c b/arch/arm/src/common/stm32/stm32_tim_m0_v1.c new file mode 100644 index 0000000000000..9401a884a27c0 --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_tim_m0_v1.c @@ -0,0 +1,1502 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_tim_m0_v1.c + * + * SPDX-License-Identifier: BSD-3-Clause + * SPDX-FileCopyrightText: 2019 Fundação CERTI. All rights reserved. + * SPDX-FileContributor: Daniel Pereira Volpato + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32_rcc.h" +#include "stm32_gpio.h" +#include "stm32_tim.h" + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* Timer devices may be used for different purposes. Such special purposes + * include: + * + * - To generate modulated outputs for such things as motor control. If + * CONFIG_STM32_TIMn is defined then the CONFIG_STM32_TIMn_PWM + * may also be defined to indicate that the timer is intended to be used + * for pulsed output modulation. + * + * - To control periodic ADC input sampling. If CONFIG_STM32_TIMn is + * defined then CONFIG_STM32_TIMn_ADC may also be defined to indicate + * that timer "n" is intended to be used for that purpose. + * + * - To control periodic DAC outputs. If CONFIG_STM32_TIMn is defined + * then CONFIG_STM32_TIMn_DAC may also be defined to indicate that + * timer "n" is intended to be used for that purpose. + * + * - To use a Quadrature Encoder. If CONFIG_STM32_TIMn is defined then + * CONFIG_STM32_TIMn_QE may also be defined to indicate that timer + * "n" is intended to be used for that purpose. + * + * In any of these cases, the timer will not be used by this timer module. + */ + +#if defined(CONFIG_STM32_TIM1_PWM) || defined(CONFIG_STM32_TIM1_ADC) || \ + defined(CONFIG_STM32_TIM1_DAC) || defined(CONFIG_STM32_TIM1_QE) +# undef CONFIG_STM32_TIM1 +#endif + +#if defined(CONFIG_STM32_TIM2_PWM) || defined(CONFIG_STM32_TIM2_ADC) || \ + defined(CONFIG_STM32_TIM2_DAC) || defined(CONFIG_STM32_TIM2_QE) +# undef CONFIG_STM32_TIM2 +#endif + +#if defined(CONFIG_STM32_TIM3_PWM) || defined(CONFIG_STM32_TIM3_ADC) || \ + defined(CONFIG_STM32_TIM3_DAC) || defined(CONFIG_STM32_TIM3_QE) +# undef CONFIG_STM32_TIM3 +#endif + +#if defined(CONFIG_STM32_TIM4_PWM) || defined(CONFIG_STM32_TIM4_ADC) || \ + defined(CONFIG_STM32_TIM4_DAC) || defined(CONFIG_STM32_TIM4_QE) +# undef CONFIG_STM32_TIM4 +#endif + +#if defined(CONFIG_STM32_TIM5_PWM) || defined(CONFIG_STM32_TIM5_ADC) || \ + defined(CONFIG_STM32_TIM5_DAC) || defined(CONFIG_STM32_TIM5_QE) +# undef CONFIG_STM32_TIM5 +#endif + +#if defined(CONFIG_STM32_TIM6_PWM) || defined(CONFIG_STM32_TIM6_ADC) || \ + defined(CONFIG_STM32_TIM6_DAC) || defined(CONFIG_STM32_TIM6_QE) +# undef CONFIG_STM32_TIM6 +#endif + +#if defined(CONFIG_STM32_TIM7_PWM) || defined(CONFIG_STM32_TIM7_ADC) || \ + defined(CONFIG_STM32_TIM7_DAC) || defined(CONFIG_STM32_TIM7_QE) +# undef CONFIG_STM32_TIM7 +#endif + +#if defined(CONFIG_STM32_TIM8_PWM) || defined(CONFIG_STM32_TIM8_ADC) || \ + defined(CONFIG_STM32_TIM8_DAC) || defined(CONFIG_STM32_TIM8_QE) +# undef CONFIG_STM32_TIM8 +#endif + +#if defined(CONFIG_STM32_TIM12_PWM) || defined(CONFIG_STM32_TIM12_ADC) || \ + defined(CONFIG_STM32_TIM12_DAC) || defined(CONFIG_STM32_TIM12_QE) +# undef CONFIG_STM32_TIM12 +#endif + +#if defined(CONFIG_STM32_TIM13_PWM) || defined(CONFIG_STM32_TIM13_ADC) || \ + defined(CONFIG_STM32_TIM13_DAC) || defined(CONFIG_STM32_TIM13_QE) +# undef CONFIG_STM32_TIM13 +#endif + +#if defined(CONFIG_STM32_TIM14_PWM) || defined(CONFIG_STM32_TIM14_ADC) || \ + defined(CONFIG_STM32_TIM14_DAC) || defined(CONFIG_STM32_TIM14_QE) +# undef CONFIG_STM32_TIM14 +#endif + +#if defined(CONFIG_STM32_TIM15_PWM) || defined(CONFIG_STM32_TIM15_ADC) || \ + defined(CONFIG_STM32_TIM15_DAC) || defined(CONFIG_STM32_TIM15_QE) +# undef CONFIG_STM32_TIM15 +#endif + +#if defined(CONFIG_STM32_TIM16_PWM) || defined(CONFIG_STM32_TIM16_ADC) || \ + defined(CONFIG_STM32_TIM16_DAC) || defined(CONFIG_STM32_TIM16_QE) +# undef CONFIG_STM32_TIM16 +#endif + +#if defined(CONFIG_STM32_TIM17_PWM) || defined(CONFIG_STM32_TIM17_ADC) || \ + defined(CONFIG_STM32_TIM17_DAC) || defined(CONFIG_STM32_TIM17_QE) +# undef CONFIG_STM32_TIM17 +#endif + +#if defined(CONFIG_STM32_TIM1) +# if defined(GPIO_TIM1_CH1OUT) || defined(GPIO_TIM1_CH2OUT) || \ + defined(GPIO_TIM1_CH3OUT) || defined(GPIO_TIM1_CH4OUT) || \ + defined(GPIO_TIM1_CH5OUT) || defined(GPIO_TIM1_CH6OUT) +# define HAVE_TIM1_GPIOCONFIG 1 +# endif +#endif + +#if defined(CONFIG_STM32_TIM2) +# if defined(GPIO_TIM2_CH1OUT) || defined(GPIO_TIM2_CH2OUT) || \ + defined(GPIO_TIM2_CH3OUT) || defined(GPIO_TIM2_CH4OUT) +# define HAVE_TIM2_GPIOCONFIG 1 +# endif +#endif + +#if defined(CONFIG_STM32_TIM3) +# if defined(GPIO_TIM3_CH1OUT) || defined(GPIO_TIM3_CH2OUT) || \ + defined(GPIO_TIM3_CH3OUT) || defined(GPIO_TIM3_CH4OUT) +# define HAVE_TIM3_GPIOCONFIG 1 +# endif +#endif + +#if defined(CONFIG_STM32_TIM4) +# if defined(GPIO_TIM4_CH1OUT) || defined(GPIO_TIM4_CH2OUT) || \ + defined(GPIO_TIM4_CH3OUT) || defined(GPIO_TIM4_CH4OUT) +# define HAVE_TIM4_GPIOCONFIG 1 +# endif +#endif + +#if defined(CONFIG_STM32_TIM5) +# if defined(GPIO_TIM5_CH1OUT) || defined(GPIO_TIM5_CH2OUT) || \ + defined(GPIO_TIM5_CH3OUT) || defined(GPIO_TIM5_CH4OUT) +# define HAVE_TIM5_GPIOCONFIG 1 +# endif +#endif + +#if defined(CONFIG_STM32_TIM8) +# if defined(GPIO_TIM8_CH1OUT) || defined(GPIO_TIM8_CH2OUT) || \ + defined(GPIO_TIM8_CH3OUT) || defined(GPIO_TIM8_CH4OUT) || \ + defined(GPIO_TIM8_CH5OUT) || defined(GPIO_TIM8_CH6OUT) +# define HAVE_TIM8_GPIOCONFIG 1 +# endif +#endif + +#if defined(CONFIG_STM32_TIM12) +# if defined(GPIO_TIM12_CH1OUT) || defined(GPIO_TIM12_CH2OUT) +# define HAVE_TIM12_GPIOCONFIG 1 +# endif +#endif + +#if defined(CONFIG_STM32_TIM13) +# if defined(GPIO_TIM13_CH1OUT) +# define HAVE_TIM13_GPIOCONFIG 1 +# endif +#endif + +#if defined(CONFIG_STM32_TIM14) +# if defined(GPIO_TIM14_CH1OUT) +# define HAVE_TIM14_GPIOCONFIG 1 +# endif +#endif + +#if defined(CONFIG_STM32_TIM15) +# if defined(GPIO_TIM15_CH1OUT) || defined(GPIO_TIM15_CH2OUT) +# define HAVE_TIM15_GPIOCONFIG 1 +# endif +#endif + +#if defined(CONFIG_STM32_TIM16) +# if defined(GPIO_TIM16_CH1OUT) +# define HAVE_TIM16_GPIOCONFIG 1 +# endif +#endif + +#if defined(CONFIG_STM32_TIM17) +# if defined(GPIO_TIM17_CH1OUT) +# define HAVE_TIM17_GPIOCONFIG 1 +# endif +#endif + +/* This module then only compiles if there are enabled timers that are not + * intended for some other purpose. + */ + +#if defined(CONFIG_STM32_TIM1) || defined(CONFIG_STM32_TIM2) || \ + defined(CONFIG_STM32_TIM3) || defined(CONFIG_STM32_TIM4) || \ + defined(CONFIG_STM32_TIM5) || defined(CONFIG_STM32_TIM6) || \ + defined(CONFIG_STM32_TIM7) || defined(CONFIG_STM32_TIM8) || \ + defined(CONFIG_STM32_TIM12) || defined(CONFIG_STM32_TIM13) || \ + defined(CONFIG_STM32_TIM14) || defined(CONFIG_STM32_TIM15) || \ + defined(CONFIG_STM32_TIM16) || defined(CONFIG_STM32_TIM17) + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/* TIM Device Structure */ + +struct stm32_tim_priv_s +{ + const struct stm32_tim_ops_s *ops; + stm32_tim_mode_t mode; + uint32_t base; /* TIMn base address */ +}; + +/**************************************************************************** + * Private Function prototypes + ****************************************************************************/ + +/* Timer helpers */ + +static void stm32_tim_reload_counter(struct stm32_tim_dev_s *dev); +static void stm32_tim_enable(struct stm32_tim_dev_s *dev); +static void stm32_tim_disable(struct stm32_tim_dev_s *dev); +static void stm32_tim_reset(struct stm32_tim_dev_s *dev); + +/* Timer methods */ + +static int stm32_tim_setmode(struct stm32_tim_dev_s *dev, + stm32_tim_mode_t mode); +static int stm32_tim_setclock(struct stm32_tim_dev_s *dev, + uint32_t freq); +static uint32_t stm32_tim_getclock(struct stm32_tim_dev_s *dev); +static void stm32_tim_setperiod(struct stm32_tim_dev_s *dev, + uint32_t period); +static uint32_t stm32_tim_getperiod(struct stm32_tim_dev_s *dev); +static uint32_t stm32_tim_getcounter(struct stm32_tim_dev_s *dev); +static int stm32_tim_getwidth(struct stm32_tim_dev_s *dev); +static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, + uint8_t channel, + stm32_tim_channel_t mode); +static int stm32_tim_setcompare(struct stm32_tim_dev_s *dev, + uint8_t channel, + uint32_t compare); +static int stm32_tim_getcapture(struct stm32_tim_dev_s *dev, + uint8_t channel); +static int stm32_tim_setisr(struct stm32_tim_dev_s *dev, xcpt_t handler, + void *arg, int source); +static void stm32_tim_enableint(struct stm32_tim_dev_s *dev, int source); +static void stm32_tim_disableint(struct stm32_tim_dev_s *dev, + int source); +static void stm32_tim_ackint(struct stm32_tim_dev_s *dev, int source); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static const struct stm32_tim_ops_s stm32_tim_ops = +{ + .enable = &stm32_tim_enable, + .disable = &stm32_tim_disable, + .setmode = &stm32_tim_setmode, + .setclock = &stm32_tim_setclock, + .getclock = &stm32_tim_getclock, + .setperiod = &stm32_tim_setperiod, + .getperiod = &stm32_tim_getperiod, + .getcounter = &stm32_tim_getcounter, + .getwidth = &stm32_tim_getwidth, + .setchannel = &stm32_tim_setchannel, + .setcompare = &stm32_tim_setcompare, + .getcapture = &stm32_tim_getcapture, + .setisr = &stm32_tim_setisr, + .enableint = &stm32_tim_enableint, + .disableint = &stm32_tim_disableint, + .ackint = &stm32_tim_ackint +}; + +#ifdef CONFIG_STM32_TIM1 +struct stm32_tim_priv_s stm32_tim1_priv = +{ + .ops = &stm32_tim_ops, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM1_BASE, +}; +#endif +#ifdef CONFIG_STM32_TIM2 +struct stm32_tim_priv_s stm32_tim2_priv = +{ + .ops = &stm32_tim_ops, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM2_BASE, +}; +#endif + +#ifdef CONFIG_STM32_TIM3 +struct stm32_tim_priv_s stm32_tim3_priv = +{ + .ops = &stm32_tim_ops, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM3_BASE, +}; +#endif + +#ifdef CONFIG_STM32_TIM4 +struct stm32_tim_priv_s stm32_tim4_priv = +{ + .ops = &stm32_tim_ops, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM4_BASE, +}; +#endif + +#ifdef CONFIG_STM32_TIM5 +struct stm32_tim_priv_s stm32_tim5_priv = +{ + .ops = &stm32_tim_ops, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM5_BASE, +}; +#endif + +#ifdef CONFIG_STM32_TIM6 +struct stm32_tim_priv_s stm32_tim6_priv = +{ + .ops = &stm32_tim_ops, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM6_BASE, +}; +#endif + +#ifdef CONFIG_STM32_TIM7 +struct stm32_tim_priv_s stm32_tim7_priv = +{ + .ops = &stm32_tim_ops, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM7_BASE, +}; +#endif + +#ifdef CONFIG_STM32_TIM8 +struct stm32_tim_priv_s stm32_tim8_priv = +{ + .ops = &stm32_tim_ops, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM8_BASE, +}; +#endif + +#ifdef CONFIG_STM32_TIM12 +struct stm32_tim_priv_s stm32_tim12_priv = +{ + .ops = &stm32_tim_ops, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM12_BASE, +}; +#endif + +#ifdef CONFIG_STM32_TIM13 +struct stm32_tim_priv_s stm32_tim13_priv = +{ + .ops = &stm32_tim_ops, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM13_BASE, +}; +#endif + +#ifdef CONFIG_STM32_TIM14 +struct stm32_tim_priv_s stm32_tim14_priv = +{ + .ops = &stm32_tim_ops, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM14_BASE, +}; +#endif + +#ifdef CONFIG_STM32_TIM15 +struct stm32_tim_priv_s stm32_tim15_priv = +{ + .ops = &stm32_tim_ops, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM15_BASE, +}; +#endif + +#ifdef CONFIG_STM32_TIM16 +struct stm32_tim_priv_s stm32_tim16_priv = +{ + .ops = &stm32_tim_ops, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM16_BASE, +}; +#endif + +#ifdef CONFIG_STM32_TIM17 +struct stm32_tim_priv_s stm32_tim17_priv = +{ + .ops = &stm32_tim_ops, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM17_BASE, +}; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/* Get a 16-bit register value by offset */ + +static inline uint16_t stm32_getreg16(struct stm32_tim_dev_s *dev, + uint8_t offset) +{ + return getreg16(((struct stm32_tim_priv_s *)dev)->base + offset); +} + +/* Put a 16-bit register value by offset */ + +static inline void stm32_putreg16(struct stm32_tim_dev_s *dev, + uint8_t offset, uint16_t value) +{ + putreg16(value, ((struct stm32_tim_priv_s *)dev)->base + offset); +} + +/* Modify a 16-bit register value by offset */ + +static inline void stm32_modifyreg16(struct stm32_tim_dev_s *dev, + uint8_t offset, uint16_t clearbits, + uint16_t setbits) +{ + modifyreg16(((struct stm32_tim_priv_s *)dev)->base + offset, clearbits, + setbits); +} + +/* Get a 32-bit register value by offset. This applies only for the STM32 F4 + * 32-bit registers (CNT, ARR, CRR1-4) in the 32-bit timers TIM2-5. + */ + +static inline uint32_t stm32_getreg32(struct stm32_tim_dev_s *dev, + uint8_t offset) +{ + return getreg32(((struct stm32_tim_priv_s *)dev)->base + offset); +} + +/* Put a 32-bit register value by offset. This applies only for the STM32 F4 + * 32-bit registers (CNT, ARR, CRR1-4) in the 32-bit timers TIM2-5. + */ + +static inline void stm32_putreg32(struct stm32_tim_dev_s *dev, + uint8_t offset, uint32_t value) +{ + putreg32(value, ((struct stm32_tim_priv_s *)dev)->base + offset); +} + +static void stm32_tim_reload_counter(struct stm32_tim_dev_s *dev) +{ + uint16_t val = stm32_getreg16(dev, STM32_GTIM_EGR_OFFSET); + val |= GTIM_EGR_UG; + stm32_putreg16(dev, STM32_GTIM_EGR_OFFSET, val); +} + +static void stm32_tim_enable(struct stm32_tim_dev_s *dev) +{ + uint16_t val = stm32_getreg16(dev, STM32_GTIM_CR1_OFFSET); + val |= GTIM_CR1_CEN; + stm32_tim_reload_counter(dev); + stm32_putreg16(dev, STM32_GTIM_CR1_OFFSET, val); +} + +static void stm32_tim_disable(struct stm32_tim_dev_s *dev) +{ + uint16_t val = stm32_getreg16(dev, STM32_GTIM_CR1_OFFSET); + val &= ~GTIM_CR1_CEN; + stm32_putreg16(dev, STM32_GTIM_CR1_OFFSET, val); +} + +/* Reset timer into system default state, but do not affect output/input + * pins + */ + +static void stm32_tim_reset(struct stm32_tim_dev_s *dev) +{ + ((struct stm32_tim_priv_s *)dev)->mode = STM32_TIM_MODE_DISABLED; + stm32_tim_disable(dev); +} + +#if defined(HAVE_TIM1_GPIOCONFIG) || defined(HAVE_TIM2_GPIOCONFIG) || \ + defined(HAVE_TIM3_GPIOCONFIG) || defined(HAVE_TIM4_GPIOCONFIG) || \ + defined(HAVE_TIM5_GPIOCONFIG) || defined(HAVE_TIM6_GPIOCONFIG) || \ + defined(HAVE_TIM7_GPIOCONFIG) || defined(HAVE_TIM8_GPIOCONFIG) || \ + defined(HAVE_TIM12_GPIOCONFIG) || defined(HAVE_TIM13_GPIOCONFIG) || \ + defined(HAVE_TIM14_GPIOCONFIG) || defined(HAVE_TIM15_GPIOCONFIG) || \ + defined(HAVE_TIM16_GPIOCONFIG) || defined(HAVE_TIM17_GPIOCONFIG) +static void stm32_tim_gpioconfig(uint32_t cfg, stm32_tim_channel_t mode) +{ + /* TODO: Add support for input capture and bipolar dual outputs for TIM8 */ + + if (mode & STM32_TIM_CH_MODE_MASK) + { + stm32_configgpio(cfg); + } + else + { + stm32_unconfiggpio(cfg); + } +} +#endif + +/**************************************************************************** + * Basic Functions + ****************************************************************************/ + +static int stm32_tim_setclock(struct stm32_tim_dev_s *dev, uint32_t freq) +{ + uint32_t freqin; + int prescaler; + + tmrinfo("Set clock=%" PRId32 "\n", freq); + + DEBUGASSERT(dev != NULL); + + /* Disable Timer? */ + + if (freq == 0) + { + stm32_tim_disable(dev); + return 0; + } + + /* Get the input clock frequency for this timer. These vary with + * different timer clock sources, MCU-specific timer configuration, and + * board-specific clock configuration. The correct input clock frequency + * must be defined in the board.h header file. + */ + + switch (((struct stm32_tim_priv_s *)dev)->base) + { +#ifdef CONFIG_STM32_TIM1 + case STM32_TIM1_BASE: + freqin = STM32_APB2_TIM1_CLKIN; + break; +#endif +#ifdef CONFIG_STM32_TIM2 + case STM32_TIM2_BASE: + freqin = STM32_APB1_TIM2_CLKIN; + break; +#endif +#ifdef CONFIG_STM32_TIM3 + case STM32_TIM3_BASE: + freqin = STM32_APB1_TIM3_CLKIN; + break; +#endif +#ifdef CONFIG_STM32_TIM6 + case STM32_TIM6_BASE: + freqin = STM32_APB1_TIM6_CLKIN; + break; +#endif +#ifdef CONFIG_STM32_TIM7 + case STM32_TIM7_BASE: + freqin = STM32_APB1_TIM7_CLKIN; + break; +#endif +#ifdef CONFIG_STM32_TIM14 + case STM32_TIM14_BASE: + freqin = STM32_APB2_TIM14_CLKIN; + break; +#endif +#ifdef CONFIG_STM32_TIM15 + case STM32_TIM15_BASE: + freqin = STM32_APB2_TIM15_CLKIN; + break; +#endif +#ifdef CONFIG_STM32_TIM16 + case STM32_TIM16_BASE: + freqin = STM32_APB2_TIM16_CLKIN; + break; +#endif +#ifdef CONFIG_STM32_TIM17 + case STM32_TIM17_BASE: + freqin = STM32_APB2_TIM17_CLKIN; + break; +#endif + default: + return -EINVAL; + } + + /* Select a pre-scaler value for this timer using the input clock + * frequency. + */ + + prescaler = freqin / freq; + tmrinfo(" timer freq=%" PRId32 "\n", freqin); + tmrinfo(" prescaler=%d\n", prescaler); + + /* We need to decrement value for '1', but only, if that will not to + * cause underflow. + */ + + if (prescaler > 0) + { + prescaler--; + } + + /* Check for overflow as well. */ + + if (prescaler > 0xffff) + { + prescaler = 0xffff; + } + + tmrinfo(" prescaler (adjusted)=%d\n", prescaler); + + /* PSC_OFFSET is the same for ATIM, BTIM or GTIM */ + + stm32_putreg16(dev, STM32_GTIM_PSC_OFFSET, prescaler); + stm32_tim_enable(dev); + + return prescaler; +} + +static uint32_t stm32_tim_getclock(struct stm32_tim_dev_s *dev) +{ + uint32_t freqin; + uint32_t clock; + uint32_t prescaler; + DEBUGASSERT(dev != NULL); + + /* Get the input clock frequency for this timer. These vary with + * different timer clock sources, MCU-specific timer configuration, and + * board-specific clock configuration. The correct input clock frequency + * must be defined in the board.h header file. + */ + + switch (((struct stm32_tim_priv_s *)dev)->base) + { +#ifdef CONFIG_STM32_TIM1 + case STM32_TIM1_BASE: + freqin = STM32_APB2_TIM1_CLKIN; + break; +#endif +#ifdef CONFIG_STM32_TIM2 + case STM32_TIM2_BASE: + freqin = STM32_APB1_TIM2_CLKIN; + break; +#endif +#ifdef CONFIG_STM32_TIM3 + case STM32_TIM3_BASE: + freqin = STM32_APB1_TIM3_CLKIN; + break; +#endif +#ifdef CONFIG_STM32_TIM6 + case STM32_TIM6_BASE: + freqin = STM32_APB1_TIM6_CLKIN; + break; +#endif +#ifdef CONFIG_STM32_TIM7 + case STM32_TIM7_BASE: + freqin = STM32_APB1_TIM7_CLKIN; + break; +#endif +#ifdef CONFIG_STM32_TIM14 + case STM32_TIM14_BASE: + freqin = STM32_APB2_TIM14_CLKIN; + break; +#endif +#ifdef CONFIG_STM32_TIM15 + case STM32_TIM15_BASE: + freqin = STM32_APB2_TIM15_CLKIN; + break; +#endif +#ifdef CONFIG_STM32_TIM16 + case STM32_TIM16_BASE: + freqin = STM32_APB2_TIM16_CLKIN; + break; +#endif +#ifdef CONFIG_STM32_TIM17 + case STM32_TIM17_BASE: + freqin = STM32_APB2_TIM17_CLKIN; + break; +#endif + default: + return -EINVAL; + } + + prescaler = stm32_getreg16(dev, STM32_GTIM_PSC_OFFSET); + clock = freqin / (prescaler + 1); + return clock; +} + +static void stm32_tim_setperiod(struct stm32_tim_dev_s *dev, + uint32_t period) +{ + tmrinfo("Set period=%" PRId32 "\n", period); + DEBUGASSERT(dev != NULL); + + /* ARR_OFFSET is the same for ATIM, BTIM or GTIM */ + + stm32_putreg32(dev, STM32_GTIM_ARR_OFFSET, period); +} + +static uint32_t stm32_tim_getperiod (struct stm32_tim_dev_s *dev) +{ + DEBUGASSERT(dev != NULL); + return stm32_getreg32 (dev, STM32_GTIM_ARR_OFFSET); +} + +static int stm32_tim_getwidth(struct stm32_tim_dev_s *dev) +{ + DEBUGASSERT(dev != NULL); + +#ifdef HAVE_TIM2_32BIT + /* TIM2 is 16-bit on L0 */ + + if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM2_BASE) + { + return 32; + } +#endif + + /* All other timers are 16-bit */ + + return 16; +} + +static uint32_t stm32_tim_getcounter(struct stm32_tim_dev_s *dev) +{ + DEBUGASSERT(dev != NULL); + return stm32_tim_getwidth(dev) > 16 ? + stm32_getreg32(dev, STM32_GTIM_CNT_OFFSET) : + (uint32_t)stm32_getreg16(dev, STM32_GTIM_CNT_OFFSET); +} + +static int stm32_tim_setisr(struct stm32_tim_dev_s *dev, + xcpt_t handler, void *arg, int source) +{ + int vectorno; + + tmrinfo("Set ISR\n"); + + DEBUGASSERT(dev != NULL); + DEBUGASSERT(source == 0); + + switch (((struct stm32_tim_priv_s *)dev)->base) + { +#ifdef CONFIG_STM32_TIM1 + case STM32_TIM1_BASE: + vectorno = STM32_IRQ_TIM1_BRK; + break; +#endif +#ifdef CONFIG_STM32_TIM2 + case STM32_TIM2_BASE: + vectorno = STM32_IRQ_TIM2; + break; +#endif +#ifdef CONFIG_STM32_TIM3 + case STM32_TIM3_BASE: + vectorno = STM32_IRQ_TIM3; + break; +#endif +#ifdef CONFIG_STM32_TIM6 + case STM32_TIM6_BASE: + vectorno = STM32_IRQ_TIM6; + break; +#endif +#ifdef CONFIG_STM32_TIM7 + case STM32_TIM7_BASE: + vectorno = STM32_IRQ_TIM7; + break; +#endif +#ifdef CONFIG_STM32_TIM13 + case STM32_TIM13_BASE: + vectorno = STM32_IRQ_TIM13; + break; +#endif +#ifdef CONFIG_STM32_TIM14 + case STM32_TIM14_BASE: + vectorno = STM32_IRQ_TIM14; + break; +#endif +#ifdef CONFIG_STM32_TIM15 + case STM32_TIM15_BASE: + vectorno = STM32_IRQ_TIM15; + break; +#endif +#ifdef CONFIG_STM32_TIM16 + case STM32_TIM16_BASE: + vectorno = STM32_IRQ_TIM16; + break; +#endif +#ifdef CONFIG_STM32_TIM17 + case STM32_TIM17_BASE: + vectorno = STM32_IRQ_TIM17; + break; +#endif + + default: + return -EINVAL; + } + + /* Disable interrupt when callback is removed */ + + if (!handler) + { + up_disable_irq(vectorno); + irq_detach(vectorno); + return OK; + } + + /* Otherwise set callback and enable interrupt */ + + irq_attach(vectorno, handler, arg); + up_enable_irq(vectorno); + +#ifdef CONFIG_ARCH_IRQPRIO + /* Set the interrupt priority */ + + up_prioritize_irq(vectorno, NVIC_SYSH_PRIORITY_DEFAULT); +#endif + + return OK; +} + +static void stm32_tim_enableint(struct stm32_tim_dev_s *dev, int source) +{ + DEBUGASSERT(dev != NULL); + + /* DIER_OFFSET is the same for ATIM, BTIM or GTIM */ + + stm32_modifyreg16(dev, STM32_GTIM_DIER_OFFSET, 0, source); +} + +static void stm32_tim_disableint(struct stm32_tim_dev_s *dev, int source) +{ + DEBUGASSERT(dev != NULL); + + /* DIER_OFFSET is the same for ATIM, BTIM or GTIM */ + + stm32_modifyreg16(dev, STM32_GTIM_DIER_OFFSET, source, 0); +} + +static void stm32_tim_ackint(struct stm32_tim_dev_s *dev, int source) +{ + /* SR_OFFSET is the same for ATIM, BTIM or GTIM */ + + stm32_putreg16(dev, STM32_GTIM_SR_OFFSET, ~source); +} + +/**************************************************************************** + * General Functions + ****************************************************************************/ + +static int stm32_tim_setmode(struct stm32_tim_dev_s *dev, + stm32_tim_mode_t mode) +{ + tmrinfo("Set mode=%d\n", mode); + uint16_t val = GTIM_CR1_CEN | GTIM_CR1_ARPE; + + DEBUGASSERT(dev != NULL); + + /* This function is not supported on basic timers. To enable or + * disable it, simply set its clock to valid frequency or zero. + */ + +#ifdef STM32_TIM6_BASE + if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM6_BASE) + { + return -EINVAL; + } +#endif + +#ifdef STM32_TIM7_BASE + if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM7_BASE) + { + return -EINVAL; + } +#endif + + /* Decode operational modes */ + + switch (mode & STM32_TIM_MODE_MASK) + { + case STM32_TIM_MODE_DISABLED: + val = 0; + break; + + case STM32_TIM_MODE_DOWN: + val |= GTIM_CR1_DIR; + + case STM32_TIM_MODE_UP: + break; + + case STM32_TIM_MODE_UPDOWN: + val |= GTIM_CR1_CENTER1; + + /* Our default: Interrupts are generated on compare, when counting + * down + */ + + break; + + case STM32_TIM_MODE_PULSE: + val |= GTIM_CR1_OPM; + break; + + default: + return -EINVAL; + } + + stm32_tim_reload_counter(dev); + + /* CR1_OFFSET is the same for ATIM, BTIM or GTIM */ + + stm32_putreg16(dev, STM32_GTIM_CR1_OFFSET, val); + + /* Advanced registers require Main Output Enable */ +#if defined(CONFIG_STM32_TIM1) || defined(CONFIG_STM32_TIM8) + if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM1_BASE +# if defined(CONFIG_STM32_TIM8) + || ((struct stm32_tim_priv_s *)dev)->base == STM32_TIM8_BASE +# endif + ) + { + stm32_modifyreg16(dev, STM32_ATIM_BDTR_OFFSET, 0, ATIM_BDTR_MOE); + } +#endif /* CONFIG_STM32_TIM1 || CONFIG_STM32_TIM8 */ + + return OK; +} + +static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, + uint8_t channel, stm32_tim_channel_t mode) +{ + uint16_t ccmr_orig = 0; + uint16_t ccmr_val = 0; + uint16_t ccmr_mask = 0xff; + + /* CCER_OFFSET and CCMR1_OFFSET are the same for ATIM and GTIM */ + + uint16_t ccer_val = stm32_getreg16(dev, STM32_GTIM_CCER_OFFSET); + uint8_t ccmr_offset = STM32_GTIM_CCMR1_OFFSET; + + DEBUGASSERT(dev != NULL); + + /* Further we use range as 0..3; if channel=0 it will also overflow here */ + + if (--channel > 4) + { + return -EINVAL; + } + + /* Assume that channel is disabled and polarity is active high */ + + ccer_val &= ~((GTIM_CCER_CC1P | GTIM_CCER_CC1E) << + GTIM_CCER_CCXBASE(channel)); + + /* This function is not supported on basic timers. To enable or + * disable it, simply set its clock to valid frequency or zero. + */ + +#ifdef STM32_TIM6_BASE + if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM6_BASE) + { + return -EINVAL; + } +#endif + +#ifdef STM32_TIM7_BASE + if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM7_BASE) + { + return -EINVAL; + } +#endif + + /* Decode configuration */ + + switch (mode & STM32_TIM_CH_MODE_MASK) + { + case STM32_TIM_CH_DISABLED: + break; + + case STM32_TIM_CH_OUTPWM: + ccmr_val = (GTIM_CCMR_MODE_PWM1 << GTIM_CCMR1_OC1M_SHIFT) + + GTIM_CCMR1_OC1PE; + ccer_val |= GTIM_CCER_CC1E << GTIM_CCER_CCXBASE(channel); + break; + + default: + return -EINVAL; + } + + /* Set polarity */ + + if (mode & STM32_TIM_CH_POLARITY_NEG) + { + ccer_val |= GTIM_CCER_CC1P << GTIM_CCER_CCXBASE(channel); + } + + /* Define its position (shift) and get register offset */ + + if (channel & 1) + { + ccmr_val <<= 8; + ccmr_mask <<= 8; + } + + if (channel > 1) + { + ccmr_offset = STM32_GTIM_CCMR2_OFFSET; + } + + ccmr_orig = stm32_getreg16(dev, ccmr_offset); + ccmr_orig &= ~ccmr_mask; + ccmr_orig |= ccmr_val; + stm32_putreg16(dev, ccmr_offset, ccmr_orig); + stm32_putreg16(dev, STM32_GTIM_CCER_OFFSET, ccer_val); + + /* set GPIO */ + + switch (((struct stm32_tim_priv_s *)dev)->base) + { +#ifdef CONFIG_STM32_TIM1 + case STM32_TIM1_BASE: + switch (channel) + { +# if defined(GPIO_TIM1_CH1OUT) + case 0: + stm32_tim_gpioconfig(GPIO_TIM1_CH1OUT, mode); break; +# endif +# if defined(GPIO_TIM1_CH2OUT) + case 1: + stm32_tim_gpioconfig(GPIO_TIM1_CH2OUT, mode); break; +# endif +# if defined(GPIO_TIM1_CH3OUT) + case 2: + stm32_tim_gpioconfig(GPIO_TIM1_CH3OUT, mode); break; +# endif +# if defined(GPIO_TIM1_CH4OUT) + case 3: + stm32_tim_gpioconfig(GPIO_TIM1_CH4OUT, mode); break; +# endif +# if defined(GPIO_TIM1_CH5OUT) + case 4: + stm32_tim_gpioconfig(GPIO_TIM1_CH5OUT, mode); break; +# endif +# if defined(GPIO_TIM1_CH6OUT) + case 5: + stm32_tim_gpioconfig(GPIO_TIM1_CH6OUT, mode); break; +# endif + default: + return -EINVAL; + } + break; +#endif + +#ifdef CONFIG_STM32_TIM2 + case STM32_TIM2_BASE: + switch (channel) + { +# if defined(GPIO_TIM2_CH1OUT) + case 0: + stm32_tim_gpioconfig(GPIO_TIM2_CH1OUT, mode); + break; +# endif +# if defined(GPIO_TIM2_CH2OUT) + case 1: + stm32_tim_gpioconfig(GPIO_TIM2_CH2OUT, mode); + break; +# endif +# if defined(GPIO_TIM2_CH3OUT) + case 2: + stm32_tim_gpioconfig(GPIO_TIM2_CH3OUT, mode); + break; +# endif +# if defined(GPIO_TIM2_CH4OUT) + case 3: + stm32_tim_gpioconfig(GPIO_TIM2_CH4OUT, mode); + break; +#endif + default: + return -EINVAL; + } + break; +#endif + +#ifdef CONFIG_STM32_TIM3 + case STM32_TIM3_BASE: + switch (channel) + { +# if defined(GPIO_TIM3_CH1OUT) + case 0: + stm32_tim_gpioconfig(GPIO_TIM3_CH1OUT, mode); + break; +# endif +# if defined(GPIO_TIM3_CH2OUT) + case 1: + stm32_tim_gpioconfig(GPIO_TIM3_CH2OUT, mode); + break; +# endif +# if defined(GPIO_TIM3_CH3OUT) + case 2: + stm32_tim_gpioconfig(GPIO_TIM3_CH3OUT, mode); + break; +# endif +# if defined(GPIO_TIM3_CH4OUT) + case 3: + stm32_tim_gpioconfig(GPIO_TIM3_CH4OUT, mode); + break; +#endif + default: + return -EINVAL; + } + break; +#endif + +#ifdef CONFIG_STM32_TIM13 + case STM32_TIM13_BASE: + switch (channel) + { +# if defined(GPIO_TIM13_CH1OUT) + case 0: + stm32_tim_gpioconfig(GPIO_TIM13_CH1OUT, mode); + break; +# endif + default: + return -EINVAL; + } + break; +#endif + +#ifdef CONFIG_STM32_TIM14 + case STM32_TIM14_BASE: + switch (channel) + { +# if defined(GPIO_TIM14_CH1OUT) + case 0: + stm32_tim_gpioconfig(GPIO_TIM14_CH1OUT, mode); + break; +# endif + default: + return -EINVAL; + } + break; +#endif + +#ifdef CONFIG_STM32_TIM15 + case STM32_TIM15_BASE: + switch (channel) + { +# if defined(GPIO_TIM15_CH1OUT) + case 0: + stm32_tim_gpioconfig(GPIO_TIM15_CH1OUT, mode); + break; +# endif +# if defined(GPIO_TIM15_CH2OUT) + case 1: + stm32_tim_gpioconfig(GPIO_TIM15_CH2OUT, mode); + break; +# endif + default: + return -EINVAL; + } + break; +#endif + +#ifdef CONFIG_STM32_TIM16 + case STM32_TIM16_BASE: + switch (channel) + { +# if defined(GPIO_TIM16_CH1OUT) + case 0: + stm32_tim_gpioconfig(GPIO_TIM16_CH1OUT, mode); + break; +# endif + default: + return -EINVAL; + } + break; +#endif + +#ifdef CONFIG_STM32_TIM17 + case STM32_TIM17_BASE: + switch (channel) + { +# if defined(GPIO_TIM17_CH1OUT) + case 0: + stm32_tim_gpioconfig(GPIO_TIM17_CH1OUT, mode); + break; +# endif + default: + return -EINVAL; + } + break; +#endif + } + + return OK; +} + +static int stm32_tim_setcompare(struct stm32_tim_dev_s *dev, + uint8_t channel, uint32_t compare) +{ + DEBUGASSERT(dev != NULL); + + switch (channel) + { + case 1: + stm32_putreg32(dev, STM32_GTIM_CCR1_OFFSET, compare); + break; + + case 2: + stm32_putreg32(dev, STM32_GTIM_CCR2_OFFSET, compare); + break; + + case 3: + stm32_putreg32(dev, STM32_GTIM_CCR3_OFFSET, compare); + break; + + case 4: + stm32_putreg32(dev, STM32_GTIM_CCR4_OFFSET, compare); + break; + + default: + return -EINVAL; + } + + return OK; +} + +static int stm32_tim_getcapture(struct stm32_tim_dev_s *dev, + uint8_t channel) +{ + DEBUGASSERT(dev != NULL); + + switch (channel) + { + case 1: + return stm32_getreg32(dev, STM32_GTIM_CCR1_OFFSET); + + case 2: + return stm32_getreg32(dev, STM32_GTIM_CCR2_OFFSET); + + case 3: + return stm32_getreg32(dev, STM32_GTIM_CCR3_OFFSET); + + case 4: + return stm32_getreg32(dev, STM32_GTIM_CCR4_OFFSET); + } + + return -EINVAL; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +struct stm32_tim_dev_s *stm32_tim_init(int timer) +{ + struct stm32_tim_dev_s *dev = NULL; + + /* Get structure and enable power */ + + switch (timer) + { +#ifdef CONFIG_STM32_TIM1 + case 1: + dev = (struct stm32_tim_dev_s *)&stm32_tim1_priv; + modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM1EN); + break; +#endif +#ifdef CONFIG_STM32_TIM2 + case 2: + dev = (struct stm32_tim_dev_s *)&stm32_tim2_priv; + modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM2EN); + break; +#endif +#ifdef CONFIG_STM32_TIM3 + case 3: + dev = (struct stm32_tim_dev_s *)&stm32_tim3_priv; + modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM3EN); + break; +#endif +#ifdef CONFIG_STM32_TIM4 + case 4: + dev = (struct stm32_tim_dev_s *)&stm32_tim4_priv; + modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM4EN); + break; +#endif +#ifdef CONFIG_STM32_TIM5 + case 5: + dev = (struct stm32_tim_dev_s *)&stm32_tim5_priv; + modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM5EN); + break; +#endif +#ifdef CONFIG_STM32_TIM6 + case 6: + dev = (struct stm32_tim_dev_s *)&stm32_tim6_priv; + modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM6EN); + break; +#endif +#ifdef CONFIG_STM32_TIM7 + case 7: + dev = (struct stm32_tim_dev_s *)&stm32_tim7_priv; + modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM7EN); + break; +#endif +#ifdef CONFIG_STM32_TIM8 + case 8: + dev = (struct stm32_tim_dev_s *)&stm32_tim8_priv; + modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM8EN); + break; +#endif +#ifdef CONFIG_STM32_TIM12 + case 12: + dev = (struct stm32_tim_dev_s *)&stm32_tim12_priv; + modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM12EN); + break; +#endif +#ifdef CONFIG_STM32_TIM13 + case 13: + dev = (struct stm32_tim_dev_s *)&stm32_tim13_priv; + modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM13EN); + break; +#endif +#ifdef CONFIG_STM32_TIM14 + case 14: + dev = (struct stm32_tim_dev_s *)&stm32_tim14_priv; + modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM14EN); + break; +#endif +#ifdef CONFIG_STM32_TIM15 + case 15: + dev = (struct stm32_tim_dev_s *)&stm32_tim15_priv; + modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM15EN); + break; +#endif +#ifdef CONFIG_STM32_TIM16 + case 16: + dev = (struct stm32_tim_dev_s *)&stm32_tim16_priv; + modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM16EN); + break; +#endif +#ifdef CONFIG_STM32_TIM17 + case 17: + dev = (struct stm32_tim_dev_s *)&stm32_tim17_priv; + modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM17EN); + break; +#endif + default: + return NULL; + } + + /* Is device already allocated */ + + if (((struct stm32_tim_priv_s *)dev)->mode != STM32_TIM_MODE_UNUSED) + { + return NULL; + } + + stm32_tim_reset(dev); + + return dev; +} + +/* TODO: Detach interrupts, and close down all TIM Channels */ + +int stm32_tim_deinit(struct stm32_tim_dev_s * dev) +{ + DEBUGASSERT(dev != NULL); + + /* Disable power */ + + switch (((struct stm32_tim_priv_s *)dev)->base) + { +#ifdef CONFIG_STM32_TIM1 + case STM32_TIM1_BASE: + modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM1EN, 0); + break; +#endif +#ifdef CONFIG_STM32_TIM2 + case STM32_TIM2_BASE: + modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM2EN, 0); + break; +#endif +#ifdef CONFIG_STM32_TIM3 + case STM32_TIM3_BASE: + modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM3EN, 0); + break; +#endif +#ifdef CONFIG_STM32_TIM4 + case STM32_TIM4_BASE: + modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM4EN, 0); + break; +#endif +#ifdef CONFIG_STM32_TIM5 + case STM32_TIM5_BASE: + modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM5EN, 0); + break; +#endif +#ifdef CONFIG_STM32_TIM6 + case STM32_TIM6_BASE: + modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM6EN, 0); + break; +#endif +#ifdef CONFIG_STM32_TIM7 + case STM32_TIM7_BASE: + modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM7EN, 0); + break; +#endif +#ifdef CONFIG_STM32_TIM8 + case STM32_TIM8_BASE: + modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM8EN, 0); + break; +#endif +#ifdef CONFIG_STM32_TIM12 + case STM32_TIM12_BASE: + modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM12EN, 0); + break; +#endif +#ifdef CONFIG_STM32_TIM13 + case STM32_TIM13_BASE: + modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM13EN, 0); + break; +#endif +#ifdef CONFIG_STM32_TIM14 + case STM32_TIM14_BASE: + modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM14EN, 0); + break; +#endif +#ifdef CONFIG_STM32_TIM15 + case STM32_TIM15_BASE: + modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM15EN, 0); + break; +#endif +#ifdef CONFIG_STM32_TIM16 + case STM32_TIM16_BASE: + modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM16EN, 0); + break; +#endif +#ifdef CONFIG_STM32_TIM17 + case STM32_TIM17_BASE: + modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM17EN, 0); + break; +#endif + default: + return -EINVAL; + } + + /* Mark it as free */ + + ((struct stm32_tim_priv_s *)dev)->mode = STM32_TIM_MODE_UNUSED; + + return OK; +} + +#endif /* defined(CONFIG_STM32_TIM1 || ... || TIM17) */ diff --git a/arch/arm/src/common/stm32/stm32_tim_m0_v1.h b/arch/arm/src/common/stm32/stm32_tim_m0_v1.h new file mode 100644 index 0000000000000..07c0ef1f7e592 --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_tim_m0_v1.h @@ -0,0 +1,233 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_tim_m0_v1.h + * + * SPDX-License-Identifier: BSD-3-Clause + * SPDX-FileCopyrightText: 2019 Fundação CERTI. All rights reserved. + * SPDX-FileContributor: Daniel Pereira Volpato + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_TIM_V3_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_TIM_V3_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "chip.h" +#include "hardware/stm32_tim.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Helpers ******************************************************************/ + +#define STM32_TIM_SETMODE(d,mode) ((d)->ops->setmode(d,mode)) +#define STM32_TIM_SETCLOCK(d,freq) ((d)->ops->setclock(d,freq)) +#define STM32_TIM_GETCLOCK(d) ((d)->ops->getclock(d)) +#define STM32_TIM_SETPERIOD(d,period) ((d)->ops->setperiod(d,period)) +#define STM32_TIM_GETPERIOD(d) ((d)->ops->getperiod(d)) +#define STM32_TIM_GETCOUNTER(d) ((d)->ops->getcounter(d)) +#define STM32_TIM_GETWIDTH(d) ((d)->ops->getwidth(d)) +#define STM32_TIM_SETCHANNEL(d,ch,mode) ((d)->ops->setchannel(d,ch,mode)) +#define STM32_TIM_SETCOMPARE(d,ch,comp) ((d)->ops->setcompare(d,ch,comp)) +#define STM32_TIM_GETCAPTURE(d,ch) ((d)->ops->getcapture(d,ch)) +#define STM32_TIM_SETISR(d,hnd,arg,s) ((d)->ops->setisr(d,hnd,arg,s)) +#define STM32_TIM_ENABLEINT(d,s) ((d)->ops->enableint(d,s)) +#define STM32_TIM_DISABLEINT(d,s) ((d)->ops->disableint(d,s)) +#define STM32_TIM_ACKINT(d,s) ((d)->ops->ackint(d,s)) +#define STM32_TIM_ENABLE(d) ((d)->ops->enable(d)) +#define STM32_TIM_DISABLE(d) ((d)->ops->disable(d)) + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/* TIM Device Structure */ + +struct stm32_tim_dev_s +{ + struct stm32_tim_ops_s *ops; +}; + +/* TIM Modes of Operation */ + +typedef enum +{ + STM32_TIM_MODE_UNUSED = -1, + + /* One of the following */ + + STM32_TIM_MODE_MASK = 0x0310, + STM32_TIM_MODE_DISABLED = 0x0000, + STM32_TIM_MODE_UP = 0x0100, + STM32_TIM_MODE_DOWN = 0x0110, + STM32_TIM_MODE_UPDOWN = 0x0200, + STM32_TIM_MODE_PULSE = 0x0300, + + /* One of the following */ + + STM32_TIM_MODE_CK_INT = 0x0000, +#if 0 + STM32_TIM_MODE_CK_INT_TRIG = 0x0400, + STM32_TIM_MODE_CK_EXT = 0x0800, + STM32_TIM_MODE_CK_EXT_TRIG = 0x0c00, +#endif + + /* Clock sources, OR'ed with CK_EXT */ + +#if 0 + STM32_TIM_MODE_CK_CHINVALID = 0x0000, + STM32_TIM_MODE_CK_CH1 = 0x0001, + STM32_TIM_MODE_CK_CH2 = 0x0002, + STM32_TIM_MODE_CK_CH3 = 0x0003, + STM32_TIM_MODE_CK_CH4 = 0x0004 +#endif + + /* TODO external trigger block */ +} stm32_tim_mode_t; + +/* TIM Channel Modes */ + +typedef enum +{ + STM32_TIM_CH_DISABLED = 0x00, + + /* Common configuration */ + + STM32_TIM_CH_POLARITY_POS = 0x00, + STM32_TIM_CH_POLARITY_NEG = 0x01, + + /* MODES: */ + + STM32_TIM_CH_MODE_MASK = 0x06, + + /* Output Compare Modes */ + + STM32_TIM_CH_OUTPWM = 0x04, /* Enable standard PWM mode, active high when counter < compare */ +#if 0 + STM32_TIM_CH_OUTCOMPARE = 0x06, + + /* TODO other modes ... as PWM capture, ENCODER and Hall Sensor */ + + STM32_TIM_CH_INCAPTURE = 0x10, + STM32_TIM_CH_INPWM = 0x20 + STM32_TIM_CH_DRIVE_OC = open collector mode +#endif +} stm32_tim_channel_t; + +/* TIM Operations */ + +struct stm32_tim_ops_s +{ + /* Basic Timers */ + + void (*enable)(struct stm32_tim_dev_s *dev); + void (*disable)(struct stm32_tim_dev_s *dev); + int (*setmode)(struct stm32_tim_dev_s *dev, stm32_tim_mode_t mode); + int (*setclock)(struct stm32_tim_dev_s *dev, uint32_t freq); + uint32_t (*getclock)(struct stm32_tim_dev_s *dev); + void (*setperiod)(struct stm32_tim_dev_s *dev, uint32_t period); + uint32_t (*getperiod)(struct stm32_tim_dev_s *dev); + uint32_t (*getcounter)(struct stm32_tim_dev_s *dev); + int (*getwidth)(struct stm32_tim_dev_s *dev); + + /* General and Advanced Timers Adds */ + + int (*setchannel)(struct stm32_tim_dev_s *dev, uint8_t channel, + stm32_tim_channel_t mode); + int (*setcompare)(struct stm32_tim_dev_s *dev, uint8_t channel, + uint32_t compare); + int (*getcapture)(struct stm32_tim_dev_s *dev, uint8_t channel); + + /* Timer interrupts */ + + int (*setisr)(struct stm32_tim_dev_s *dev, xcpt_t handler, void *arg, + int source); + void (*enableint)(struct stm32_tim_dev_s *dev, int source); + void (*disableint)(struct stm32_tim_dev_s *dev, int source); + void (*ackint)(struct stm32_tim_dev_s *dev, int source); +}; + +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ + +/* Power-up timer and get its structure */ + +struct stm32_tim_dev_s *stm32_tim_init(int timer); + +/* Power-down timer, mark it as unused */ + +int stm32_tim_deinit(struct stm32_tim_dev_s *dev); + +/**************************************************************************** + * Name: stm32_timer_initialize + * + * Description: + * Bind the configuration timer to a timer lower half instance and + * register the timer drivers at 'devpath' + * + * Input Parameters: + * devpath - The full path to the timer device. This should be of the + * form /dev/timer0 + * timer - the timer number. + * + * Returned Values: + * Zero (OK) is returned on success; A negated errno value is returned + * to indicate the nature of any failure. + * + ****************************************************************************/ + +#ifdef CONFIG_TIMER +int stm32_timer_initialize(const char *devpath, int timer); +#endif + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_TIM_V3_H */ diff --git a/arch/arm/src/common/stm32/stm32_tim_m0_v1_lowerhalf.c b/arch/arm/src/common/stm32/stm32_tim_m0_v1_lowerhalf.c new file mode 100644 index 0000000000000..356a3e9e6c782 --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_tim_m0_v1_lowerhalf.c @@ -0,0 +1,668 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_tim_m0_v1_lowerhalf.c + * + * SPDX-License-Identifier: BSD-3-Clause + * SPDX-FileCopyrightText: 2019 Fundação CERTI. All rights reserved. + * SPDX-FileContributor: Daniel Pereira Volpato + * SPDX-FileContributor: Wail Khemir + * SPDX-FileContributor: Paul Alexander Patience + * SPDX-FileContributor: dev@ziggurat29.com + * SPDX-FileContributor: Sebastien Lorquet + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include +#include +#include +#include +#include + +#include +#include +#include + +#include + +#include "stm32_tim.h" + +#if defined(CONFIG_TIMER) && \ + (defined(CONFIG_STM32_TIM1) || defined(CONFIG_STM32_TIM2) || \ + defined(CONFIG_STM32_TIM3) || defined(CONFIG_STM32_TIM4) || \ + defined(CONFIG_STM32_TIM5) || defined(CONFIG_STM32_TIM6) || \ + defined(CONFIG_STM32_TIM7) || defined(CONFIG_STM32_TIM8) || \ + defined(CONFIG_STM32_TIM12) || defined(CONFIG_STM32_TIM13) || \ + defined(CONFIG_STM32_TIM14) || defined(CONFIG_STM32_TIM15) || \ + defined(CONFIG_STM32_TIM16) || defined(CONFIG_STM32_TIM17)) + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define STM32_TIM1_RES 16 +#define STM32_TIM2_RES 16 +#define STM32_TIM3_RES 16 +#define STM32_TIM4_RES 16 +#define STM32_TIM5_RES 16 +#define STM32_TIM6_RES 16 +#define STM32_TIM7_RES 16 +#define STM32_TIM8_RES 16 +#define STM32_TIM9_RES 16 +#define STM32_TIM10_RES 16 +#define STM32_TIM11_RES 16 +#define STM32_TIM12_RES 16 +#define STM32_TIM13_RES 16 +#define STM32_TIM14_RES 16 +#define STM32_TIM15_RES 16 +#define STM32_TIM16_RES 16 +#define STM32_TIM17_RES 16 + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/* This structure provides the private representation of the "lower-half" + * driver state structure. This structure must be cast-compatible with the + * timer_lowerhalf_s structure. + */ + +struct stm32_lowerhalf_s +{ + const struct timer_ops_s *ops; /* Lower half operations */ + struct stm32_tim_dev_s *tim; /* stm32 timer driver */ + tccb_t callback; /* Current user interrupt callback */ + void *arg; /* Argument passed to upper half callback */ + bool started; /* True: Timer has been started */ + const uint8_t resolution; /* Number of bits in the timer (16 or 32 bits) */ +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +static int stm32_timer_handler(int irq, void * context, void * arg); + +/* "Lower half" driver methods **********************************************/ + +static int stm32_start(struct timer_lowerhalf_s *lower); +static int stm32_stop(struct timer_lowerhalf_s *lower); +static int stm32_getstatus(struct timer_lowerhalf_s *lower, + struct timer_status_s *status); +static int stm32_settimeout(struct timer_lowerhalf_s *lower, + uint32_t timeout); +static void stm32_setcallback(struct timer_lowerhalf_s *lower, + tccb_t callback, void *arg); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* "Lower half" driver methods */ + +static const struct timer_ops_s g_timer_ops = +{ + .start = stm32_start, + .stop = stm32_stop, + .getstatus = stm32_getstatus, + .settimeout = stm32_settimeout, + .setcallback = stm32_setcallback, + .ioctl = NULL, +}; + +#ifdef CONFIG_STM32_TIM1 +static struct stm32_lowerhalf_s g_tim1_lowerhalf = +{ + .ops = &g_timer_ops, + .resolution = STM32_TIM1_RES, +}; +#endif + +#ifdef CONFIG_STM32_TIM2 +static struct stm32_lowerhalf_s g_tim2_lowerhalf = +{ + .ops = &g_timer_ops, + .resolution = STM32_TIM2_RES, +}; +#endif + +#ifdef CONFIG_STM32_TIM3 +static struct stm32_lowerhalf_s g_tim3_lowerhalf = +{ + .ops = &g_timer_ops, + .resolution = STM32_TIM3_RES, +}; +#endif + +#ifdef CONFIG_STM32_TIM4 +static struct stm32_lowerhalf_s g_tim4_lowerhalf = +{ + .ops = &g_timer_ops, + .resolution = STM32_TIM4_RES, +}; +#endif + +#ifdef CONFIG_STM32_TIM5 +static struct stm32_lowerhalf_s g_tim5_lowerhalf = +{ + .ops = &g_timer_ops, + .resolution = STM32_TIM5_RES, +}; +#endif + +#ifdef CONFIG_STM32_TIM6 +static struct stm32_lowerhalf_s g_tim6_lowerhalf = +{ + .ops = &g_timer_ops, + .resolution = STM32_TIM6_RES, +}; +#endif + +#ifdef CONFIG_STM32_TIM7 +static struct stm32_lowerhalf_s g_tim7_lowerhalf = +{ + .ops = &g_timer_ops, + .resolution = STM32_TIM7_RES, +}; +#endif + +#ifdef CONFIG_STM32_TIM8 +static struct stm32_lowerhalf_s g_tim8_lowerhalf = +{ + .ops = &g_timer_ops, + .resolution = STM32_TIM8_RES, +}; +#endif + +#ifdef CONFIG_STM32_TIM12 +static struct stm32_lowerhalf_s g_tim12_lowerhalf = +{ + .ops = &g_timer_ops, + .resolution = STM32_TIM12_RES, +}; +#endif + +#ifdef CONFIG_STM32_TIM13 +static struct stm32_lowerhalf_s g_tim13_lowerhalf = +{ + .ops = &g_timer_ops, + .resolution = STM32_TIM13_RES, +}; +#endif + +#ifdef CONFIG_STM32_TIM14 +static struct stm32_lowerhalf_s g_tim14_lowerhalf = +{ + .ops = &g_timer_ops, + .resolution = STM32_TIM14_RES, +}; +#endif + +#ifdef CONFIG_STM32_TIM15 +static struct stm32_lowerhalf_s g_tim15_lowerhalf = +{ + .ops = &g_timer_ops, + .resolution = STM32_TIM15_RES, +}; +#endif + +#ifdef CONFIG_STM32_TIM16 +static struct stm32_lowerhalf_s g_tim16_lowerhalf = +{ + .ops = &g_timer_ops, + .resolution = STM32_TIM16_RES, +}; +#endif + +#ifdef CONFIG_STM32_TIM17 +static struct stm32_lowerhalf_s g_tim17_lowerhalf = +{ + .ops = &g_timer_ops, + .resolution = STM32_TIM17_RES, +}; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_timer_handler + * + * Description: + * timer interrupt handler + * + * Input Parameters: + * + * Returned Value: + * + ****************************************************************************/ + +static int stm32_timer_handler(int irq, void * context, void * arg) +{ + struct stm32_lowerhalf_s *lower = (struct stm32_lowerhalf_s *) arg; + uint32_t next_interval_us = 0; + + STM32_TIM_ACKINT(lower->tim, ATIM_DIER_UIE); + + if (lower->callback(&next_interval_us, lower->arg)) + { + if (next_interval_us > 0) + { + STM32_TIM_SETPERIOD(lower->tim, next_interval_us); + } + } + else + { + stm32_stop((struct timer_lowerhalf_s *)lower); + } + + return OK; +} + +/**************************************************************************** + * Name: stm32_start + * + * Description: + * Start the timer, resetting the time to the current timeout, + * + * Input Parameters: + * lower - A pointer the publicly visible representation of the + * "lower-half" driver state structure. + * + * Returned Value: + * Zero on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int stm32_start(struct timer_lowerhalf_s *lower) +{ + struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; + + tmrinfo("Start\n"); + + if (!priv->started) + { + STM32_TIM_SETMODE(priv->tim, STM32_TIM_MODE_UP); + + if (priv->callback != NULL) + { + STM32_TIM_SETISR(priv->tim, stm32_timer_handler, priv, 0); + STM32_TIM_ENABLEINT(priv->tim, ATIM_DIER_UIE); + } + + priv->started = true; + return OK; + } + + /* Return EBUSY to indicate that the timer was already running */ + + return -EBUSY; +} + +/**************************************************************************** + * Name: stm32_stop + * + * Description: + * Stop the timer + * + * Input Parameters: + * lower - A pointer the publicly visible representation of the + * "lower-half" driver state structure. + * + * Returned Value: + * Zero on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int stm32_stop(struct timer_lowerhalf_s *lower) +{ + struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; + + if (priv->started) + { + STM32_TIM_SETMODE(priv->tim, STM32_TIM_MODE_DISABLED); + STM32_TIM_DISABLEINT(priv->tim, ATIM_DIER_UIE); + STM32_TIM_SETISR(priv->tim, NULL, NULL, 0); + priv->started = false; + return OK; + } + + /* Return ENODEV to indicate that the timer was not running */ + + return -ENODEV; +} + +/**************************************************************************** + * Name: stm32_getstatus + * + * Description: + * get timer status + * + * Input Parameters: + * lower - A pointer the publicly visible representation of the "lower- + * half" driver state structure. + * status - The location to return the status information. + * + * Returned Value: + * Zero on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int stm32_getstatus(struct timer_lowerhalf_s *lower, + struct timer_status_s *status) +{ + struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; + uint32_t timeout; + uint32_t clock; + uint32_t period; + uint32_t counter; + + DEBUGASSERT(priv); + + /* Return the status bit */ + + status->flags = 0; + if (priv->started) + { + status->flags |= TCFLAGS_ACTIVE; + } + + if (priv->callback) + { + status->flags |= TCFLAGS_HANDLER; + } + + /* Get timeout */ + + clock = STM32_TIM_GETCLOCK(priv->tim); + period = STM32_TIM_GETPERIOD(priv->tim); + + if (clock == 1000000) + { + timeout = period; + } + else + { + timeout = ((uint64_t)period * 1000000) / clock; + } + + status->timeout = timeout; + + /* Get the time remaining until the timer expires (in microseconds) */ + + counter = STM32_TIM_GETCOUNTER(priv->tim); + status->timeleft = ((uint64_t)(timeout - counter) * clock) / 1000000; + tmrinfo("timeout=%" PRIu32 " counter=%" PRIu32 "\n", timeout, counter); + tmrinfo("timeleft=%" PRIu32 "\n", status->timeleft); + return OK; +} + +/**************************************************************************** + * Name: stm32_settimeout + * + * Description: + * Set a new timeout value (and reset the timer) + * + * Input Parameters: + * lower - A pointer the publicly visible representation of the "lower- + * half" driver state structure. + * timeout - The new timeout value in microseconds. + * + * Returned Value: + * Zero on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int stm32_settimeout(struct timer_lowerhalf_s *lower, + uint32_t timeout) +{ + struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; + uint64_t maxtimeout; + uint32_t clock; + uint32_t period; + + if (priv->started) + { + return -EPERM; + } + + tmrinfo("Set timeout=%" PRId32 "\n", timeout); + + maxtimeout = ((uint64_t)1 << priv->resolution) - 1; + if (timeout > maxtimeout) + { + uint64_t freq = (maxtimeout * 1000000) / timeout; + clock = (uint32_t) freq; + period = (uint32_t) maxtimeout; + } + else + { + clock = (uint32_t) 1000000; + period = (uint32_t) timeout; + } + + tmrinfo(" clock=%" PRIu32 " period=%" PRIu32 " maxtimeout=%" PRIu32 "\n", + clock, period, (uint32_t)maxtimeout); + STM32_TIM_SETCLOCK(priv->tim, clock); + STM32_TIM_SETPERIOD(priv->tim, period); + + return OK; +} + +/**************************************************************************** + * Name: stm32_setcallback + * + * Description: + * Call this user provided timeout callback. + * + * Input Parameters: + * lower - A pointer the publicly visible representation of the + * "lower-half" driver state structure. + * callback - The new timer expiration function pointer. If this + * function pointer is NULL, then the reset-on-expiration + * behavior is restored, + * arg - Argument that will be provided in the callback + * + * Returned Value: + * The previous timer expiration function pointer or NULL is there was + * no previous function pointer. + * + ****************************************************************************/ + +static void stm32_setcallback(struct timer_lowerhalf_s *lower, + tccb_t callback, void *arg) +{ + struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; + + irqstate_t flags = enter_critical_section(); + + /* Save the new callback */ + + priv->callback = callback; + priv->arg = arg; + + if (callback != NULL && priv->started) + { + STM32_TIM_SETISR(priv->tim, stm32_timer_handler, priv, 0); + STM32_TIM_ENABLEINT(priv->tim, ATIM_DIER_UIE); + } + else + { + STM32_TIM_DISABLEINT(priv->tim, ATIM_DIER_UIE); + STM32_TIM_SETISR(priv->tim, NULL, NULL, 0); + } + + leave_critical_section(flags); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_timer_initialize + * + * Description: + * Bind the configuration timer to a timer lower half instance and + * register the timer drivers at 'devpath' + * + * Input Parameters: + * devpath - The full path to the timer device. This should be of the + * form /dev/timer0 + * timer - the timer's number. + * + * Returned Value: + * Zero (OK) is returned on success; A negated errno value is returned + * to indicate the nature of any failure. + * + ****************************************************************************/ + +int stm32_timer_initialize(const char *devpath, int timer) +{ + struct stm32_lowerhalf_s *lower; + + tmrinfo("Init TIM%d\n", timer); + + switch (timer) + { +#ifdef CONFIG_STM32_TIM1 + case 1: + lower = &g_tim1_lowerhalf; + break; +#endif +#ifdef CONFIG_STM32_TIM2 + case 2: + lower = &g_tim2_lowerhalf; + break; +#endif +#ifdef CONFIG_STM32_TIM3 + case 3: + lower = &g_tim3_lowerhalf; + break; +#endif +#ifdef CONFIG_STM32_TIM4 + case 4: + lower = &g_tim4_lowerhalf; + break; +#endif +#ifdef CONFIG_STM32_TIM5 + case 5: + lower = &g_tim5_lowerhalf; + break; +#endif +#ifdef CONFIG_STM32_TIM6 + case 6: + lower = &g_tim6_lowerhalf; + break; +#endif +#ifdef CONFIG_STM32_TIM7 + case 7: + lower = &g_tim7_lowerhalf; + break; +#endif +#ifdef CONFIG_STM32_TIM8 + case 8: + lower = &g_tim8_lowerhalf; + break; +#endif +#ifdef CONFIG_STM32_TIM12 + case 12: + lower = &g_tim12_lowerhalf; + break; +#endif +#ifdef CONFIG_STM32_TIM13 + case 13: + lower = &g_tim13_lowerhalf; + break; +#endif +#ifdef CONFIG_STM32_TIM14 + case 14: + lower = &g_tim14_lowerhalf; + break; +#endif +#ifdef CONFIG_STM32_TIM15 + case 15: + lower = &g_tim15_lowerhalf; + break; +#endif +#ifdef CONFIG_STM32_TIM16 + case 16: + lower = &g_tim16_lowerhalf; + break; +#endif +#ifdef CONFIG_STM32_TIM17 + case 17: + lower = &g_tim17_lowerhalf; + break; +#endif + default: + return -ENODEV; + } + + /* Initialize the elements of lower half state structure */ + + lower->started = false; + lower->callback = NULL; + lower->tim = stm32_tim_init(timer); + + if (lower->tim == NULL) + { + return -EINVAL; + } + + /* Register the timer driver as /dev/timerX. The returned value from + * timer_register is a handle that could be used with timer_unregister(). + * REVISIT: The returned handle is discard here. + */ + + void *drvr = timer_register(devpath, + (struct timer_lowerhalf_s *)lower); + if (drvr == NULL) + { + /* The actual cause of the failure may have been a failure to allocate + * perhaps a failure to register the timer driver (such as if the + * 'depath' were not unique). We know here but we return EEXIST to + * indicate the failure (implying the non-unique devpath). + */ + + return -EEXIST; + } + + return OK; +} + +#endif /* CONFIG_TIMER */ diff --git a/arch/arm/src/common/stm32/stm32_tim_m3m4_v1v2v3.c b/arch/arm/src/common/stm32/stm32_tim_m3m4_v1v2v3.c new file mode 100644 index 0000000000000..65a9a062d05bd --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_tim_m3m4_v1v2v3.c @@ -0,0 +1,1967 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_tim_m3m4_v1v2v3.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32.h" +#include "stm32_gpio.h" +#include "stm32_tim.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* Timer devices may be used for different purposes. Such special purposes + * include: + * + * - To generate modulated outputs for such things as motor control. If + * CONFIG_STM32_TIMn is defined then the CONFIG_STM32_TIMn_PWM may also be + * defined to indicate that the timer is intended to be used for pulsed + * output modulation. + * + * - To control periodic ADC input sampling. If CONFIG_STM32_TIMn is + * defined then CONFIG_STM32_TIMn_ADC may also be defined to indicate that + * timer "n" is intended to be used for that purpose. + * + * - To control periodic DAC outputs. If CONFIG_STM32_TIMn is defined then + * CONFIG_STM32_TIMn_DAC may also be defined to indicate that timer "n" is + * intended to be used for that purpose. + * + * - To use a Quadrature Encoder. If CONFIG_STM32_TIMn is defined then + * CONFIG_STM32_TIMn_QE may also be defined to indicate that timer "n" is + * intended to be used for that purpose. + * + * In any of these cases, the timer will not be used by this timer module. + */ + +#if defined(CONFIG_STM32_TIM1_PWM) || defined (CONFIG_STM32_TIM1_ADC) || \ + defined(CONFIG_STM32_TIM1_DAC) || defined(CONFIG_STM32_TIM1_QE) || \ + defined(CONFIG_STM32_TIM1_CAP) +# undef CONFIG_STM32_TIM1 +#endif +#if defined(CONFIG_STM32_TIM2_PWM) || defined (CONFIG_STM32_TIM2_ADC) || \ + defined(CONFIG_STM32_TIM2_DAC) || defined(CONFIG_STM32_TIM2_QE) || \ + defined(CONFIG_STM32_TIM2_CAP) +# undef CONFIG_STM32_TIM2 +#endif +#if defined(CONFIG_STM32_TIM3_PWM) || defined (CONFIG_STM32_TIM3_ADC) || \ + defined(CONFIG_STM32_TIM3_DAC) || defined(CONFIG_STM32_TIM3_QE) || \ + defined(CONFIG_STM32_TIM3_CAP) +# undef CONFIG_STM32_TIM3 +#endif +#if defined(CONFIG_STM32_TIM4_PWM) || defined (CONFIG_STM32_TIM4_ADC) || \ + defined(CONFIG_STM32_TIM4_DAC) || defined(CONFIG_STM32_TIM4_QE) || \ + defined(CONFIG_STM32_TIM4_CAP) +# undef CONFIG_STM32_TIM4 +#endif +#if defined(CONFIG_STM32_TIM5_PWM) || defined (CONFIG_STM32_TIM5_ADC) || \ + defined(CONFIG_STM32_TIM5_DAC) || defined(CONFIG_STM32_TIM5_QE) || \ + defined(CONFIG_STM32_TIM5_CAP) +# undef CONFIG_STM32_TIM5 +#endif +#if defined(CONFIG_STM32_TIM6_PWM) || defined (CONFIG_STM32_TIM6_ADC) || \ + defined(CONFIG_STM32_TIM6_DAC) || defined(CONFIG_STM32_TIM6_QE) +# undef CONFIG_STM32_TIM6 +#endif +#if defined(CONFIG_STM32_TIM7_PWM) || defined (CONFIG_STM32_TIM7_ADC) || \ + defined(CONFIG_STM32_TIM7_DAC) || defined(CONFIG_STM32_TIM7_QE) +# undef CONFIG_STM32_TIM7 +#endif +#if defined(CONFIG_STM32_TIM8_PWM) || defined (CONFIG_STM32_TIM8_ADC) || \ + defined(CONFIG_STM32_TIM8_DAC) || defined(CONFIG_STM32_TIM8_QE) || \ + defined(CONFIG_STM32_TIM8_CAP) +# undef CONFIG_STM32_TIM8 +#endif +#if defined(CONFIG_STM32_TIM9_PWM) || defined (CONFIG_STM32_TIM9_ADC) || \ + defined(CONFIG_STM32_TIM9_DAC) || defined(CONFIG_STM32_TIM9_QE) || \ + defined(CONFIG_STM32_TIM9_CAP) +# undef CONFIG_STM32_TIM9 +#endif +#if defined(CONFIG_STM32_TIM10_PWM) || defined (CONFIG_STM32_TIM10_ADC) || \ + defined(CONFIG_STM32_TIM10_DAC) || defined(CONFIG_STM32_TIM10_QE) || \ + defined(CONFIG_STM32_TIM10_CAP) +# undef CONFIG_STM32_TIM10 +#endif +#if defined(CONFIG_STM32_TIM11_PWM) || defined (CONFIG_STM32_TIM11_ADC) || \ + defined(CONFIG_STM32_TIM11_DAC) || defined(CONFIG_STM32_TIM11_QE) || \ + defined(CONFIG_STM32_TIM11_CAP) +# undef CONFIG_STM32_TIM11 +#endif +#if defined(CONFIG_STM32_TIM12_PWM) || defined (CONFIG_STM32_TIM12_ADC) || \ + defined(CONFIG_STM32_TIM12_DAC) || defined(CONFIG_STM32_TIM12_QE) || \ + defined(CONFIG_STM32_TIM12_CAP) +# undef CONFIG_STM32_TIM12 +#endif +#if defined(CONFIG_STM32_TIM13_PWM) || defined (CONFIG_STM32_TIM13_ADC) || \ + defined(CONFIG_STM32_TIM13_DAC) || defined(CONFIG_STM32_TIM13_QE) || \ + defined(CONFIG_STM32_TIM13_CAP) +# undef CONFIG_STM32_TIM13 +#endif +#if defined(CONFIG_STM32_TIM14_PWM) || defined (CONFIG_STM32_TIM14_ADC) || \ + defined(CONFIG_STM32_TIM14_DAC) || defined(CONFIG_STM32_TIM14_QE) || \ + defined(CONFIG_STM32_TIM14_CAP) +# undef CONFIG_STM32_TIM14 +#endif +#if defined(CONFIG_STM32_TIM15_PWM) || defined (CONFIG_STM32_TIM15_ADC) || \ + defined(CONFIG_STM32_TIM15_DAC) || defined(CONFIG_STM32_TIM15_QE) +# undef CONFIG_STM32_TIM15 +#endif +#if defined(CONFIG_STM32_TIM16_PWM) || defined (CONFIG_STM32_TIM16_ADC) || \ + defined(CONFIG_STM32_TIM16_DAC) || defined(CONFIG_STM32_TIM16_QE) +# undef CONFIG_STM32_TIM16 +#endif +#if defined(CONFIG_STM32_TIM17_PWM) || defined (CONFIG_STM32_TIM17_ADC) || \ + defined(CONFIG_STM32_TIM17_DAC) || defined(CONFIG_STM32_TIM17_QE) +# undef CONFIG_STM32_TIM17 +#endif + +#undef HAVE_TIM_GPIOCONFIG +#if defined(CONFIG_STM32_TIM1) +# if defined(GPIO_TIM1_CH1OUT) ||defined(GPIO_TIM1_CH2OUT)||\ + defined(GPIO_TIM1_CH3OUT) ||defined(GPIO_TIM1_CH4OUT) +# undef HAVE_TIM_GPIOCONFIG +# define HAVE_TIM_GPIOCONFIG 1 +# define HAVE_TIM1_GPIOCONFIG 1 +#endif +#endif + +#if defined(CONFIG_STM32_TIM2) +# if defined(GPIO_TIM2_CH1OUT) ||defined(GPIO_TIM2_CH2OUT)||\ + defined(GPIO_TIM2_CH3OUT) ||defined(GPIO_TIM2_CH4OUT) +# undef HAVE_TIM_GPIOCONFIG +# define HAVE_TIM_GPIOCONFIG 1 +# define HAVE_TIM2_GPIOCONFIG 1 +#endif +#endif + +#if defined(CONFIG_STM32_TIM3) +# if defined(GPIO_TIM3_CH1OUT) ||defined(GPIO_TIM3_CH2OUT)||\ + defined(GPIO_TIM3_CH3OUT) ||defined(GPIO_TIM3_CH4OUT) +# undef HAVE_TIM_GPIOCONFIG +# define HAVE_TIM_GPIOCONFIG 1 +# define HAVE_TIM3_GPIOCONFIG 1 +#endif +#endif + +#if defined(CONFIG_STM32_TIM4) +# if defined(GPIO_TIM4_CH1OUT) ||defined(GPIO_TIM4_CH2OUT)||\ + defined(GPIO_TIM4_CH3OUT) ||defined(GPIO_TIM4_CH4OUT) +# undef HAVE_TIM_GPIOCONFIG +# define HAVE_TIM_GPIOCONFIG 1 +# define HAVE_TIM4_GPIOCONFIG 1 +#endif +#endif + +#if defined(CONFIG_STM32_TIM5) +# if defined(GPIO_TIM5_CH1OUT) ||defined(GPIO_TIM5_CH2OUT)||\ + defined(GPIO_TIM5_CH3OUT) ||defined(GPIO_TIM5_CH4OUT) +# undef HAVE_TIM_GPIOCONFIG +# define HAVE_TIM_GPIOCONFIG 1 +# define HAVE_TIM5_GPIOCONFIG 1 +#endif +#endif + +#if defined(CONFIG_STM32_TIM8) +# if defined(GPIO_TIM8_CH1OUT) ||defined(GPIO_TIM8_CH2OUT)||\ + defined(GPIO_TIM8_CH3OUT) ||defined(GPIO_TIM8_CH4OUT) +# undef HAVE_TIM_GPIOCONFIG +# define HAVE_TIM_GPIOCONFIG 1 +# define HAVE_TIM8_GPIOCONFIG 1 +#endif +#endif + +#if defined(CONFIG_STM32_TIM9) +# if defined(GPIO_TIM9_CH1OUT) ||defined(GPIO_TIM9_CH2OUT)||\ + defined(GPIO_TIM9_CH3OUT) ||defined(GPIO_TIM9_CH4OUT) +# define HAVE_TIM9_GPIOCONFIG 1 +#endif +#endif + +#if defined(CONFIG_STM32_TIM10) +# if defined(GPIO_TIM10_CH1OUT) ||defined(GPIO_TIM10_CH2OUT)||\ + defined(GPIO_TIM10_CH3OUT) ||defined(GPIO_TIM10_CH4OUT) +# define HAVE_TIM10_GPIOCONFIG 1 +#endif +#endif + +#if defined(CONFIG_STM32_TIM11) +# if defined(GPIO_TIM11_CH1OUT) ||defined(GPIO_TIM11_CH2OUT)||\ + defined(GPIO_TIM11_CH3OUT) ||defined(GPIO_TIM11_CH4OUT) +# define HAVE_TIM11_GPIOCONFIG 1 +#endif +#endif + +#if defined(CONFIG_STM32_TIM12) +# if defined(GPIO_TIM12_CH1OUT) ||defined(GPIO_TIM12_CH2OUT)||\ + defined(GPIO_TIM12_CH3OUT) ||defined(GPIO_TIM12_CH4OUT) +# define HAVE_TIM12_GPIOCONFIG 1 +#endif +#endif + +#if defined(CONFIG_STM32_TIM13) +# if defined(GPIO_TIM13_CH1OUT) ||defined(GPIO_TIM13_CH2OUT)||\ + defined(GPIO_TIM13_CH3OUT) ||defined(GPIO_TIM13_CH4OUT) +# define HAVE_TIM13_GPIOCONFIG 1 +#endif +#endif + +#if defined(CONFIG_STM32_TIM14) +# if defined(GPIO_TIM14_CH1OUT) ||defined(GPIO_TIM14_CH2OUT)||\ + defined(GPIO_TIM14_CH3OUT) ||defined(GPIO_TIM14_CH4OUT) +# define HAVE_TIM14_GPIOCONFIG 1 +#endif +#endif + +#if defined(CONFIG_STM32_TIM15) +# if defined(GPIO_TIM15_CH1OUT) ||defined(GPIO_TIM15_CH2OUT)||\ + defined(GPIO_TIM15_CH3OUT) ||defined(GPIO_TIM15_CH4OUT) +# define HAVE_TIM15_GPIOCONFIG 1 +#endif +#endif + +#if defined(CONFIG_STM32_TIM16) +# if defined(GPIO_TIM16_CH1OUT) ||defined(GPIO_TIM16_CH2OUT)||\ + defined(GPIO_TIM16_CH3OUT) ||defined(GPIO_TIM16_CH4OUT) +# define HAVE_TIM16_GPIOCONFIG 1 +#endif +#endif + +#if defined(CONFIG_STM32_TIM17) +# if defined(GPIO_TIM17_CH1OUT) ||defined(GPIO_TIM17_CH2OUT)||\ + defined(GPIO_TIM17_CH3OUT) ||defined(GPIO_TIM17_CH4OUT) +# define HAVE_TIM17_GPIOCONFIG 1 +#endif +#endif + +/* This module then only compiles if there are enabled timers that are not + * intended for some other purpose. + */ + +#if defined(CONFIG_STM32_TIM1) || defined(CONFIG_STM32_TIM2) || \ + defined(CONFIG_STM32_TIM3) || defined(CONFIG_STM32_TIM4) || \ + defined(CONFIG_STM32_TIM5) || defined(CONFIG_STM32_TIM6) || \ + defined(CONFIG_STM32_TIM7) || defined(CONFIG_STM32_TIM8) || \ + defined(CONFIG_STM32_TIM9) || defined(CONFIG_STM32_TIM10) || \ + defined(CONFIG_STM32_TIM11) || defined(CONFIG_STM32_TIM12) || \ + defined(CONFIG_STM32_TIM13) || defined(CONFIG_STM32_TIM14) || \ + defined(CONFIG_STM32_TIM15) || defined(CONFIG_STM32_TIM16) || \ + defined(CONFIG_STM32_TIM17) + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/* TIM Device Structure */ + +struct stm32_tim_priv_s +{ + const struct stm32_tim_ops_s *ops; + stm32_tim_mode_t mode; + uint32_t base; /* TIMn base address */ +}; + +/**************************************************************************** + * Private Function prototypes + ****************************************************************************/ + +/* Register helpers */ + +static inline uint16_t stm32_getreg16(struct stm32_tim_dev_s *dev, + uint8_t offset); +static inline void stm32_putreg16(struct stm32_tim_dev_s *dev, + uint8_t offset, uint16_t value); +static inline void stm32_modifyreg16(struct stm32_tim_dev_s *dev, + uint8_t offset, uint16_t clearbits, + uint16_t setbits); +static inline uint32_t stm32_getreg32(struct stm32_tim_dev_s *dev, + uint8_t offset); +static inline void stm32_putreg32(struct stm32_tim_dev_s *dev, + uint8_t offset, uint32_t value); + +/* Timer helpers */ + +static void stm32_tim_reload_counter(struct stm32_tim_dev_s *dev); +static void stm32_tim_enable(struct stm32_tim_dev_s *dev); +static void stm32_tim_disable(struct stm32_tim_dev_s *dev); +static void stm32_tim_reset(struct stm32_tim_dev_s *dev); + +#ifdef HAVE_TIM_GPIOCONFIG +static void stm32_tim_gpioconfig(uint32_t cfg, stm32_tim_channel_t mode); +#endif + +/* Timer methods */ + +static int stm32_tim_setmode(struct stm32_tim_dev_s *dev, + stm32_tim_mode_t mode); +static int stm32_tim_setclock(struct stm32_tim_dev_s *dev, + uint32_t freq); +static void stm32_tim_setperiod(struct stm32_tim_dev_s *dev, + uint32_t period); +static uint32_t stm32_tim_getcounter(struct stm32_tim_dev_s *dev); +static void stm32_tim_setcounter(struct stm32_tim_dev_s *dev, + uint32_t count); +static int stm32_tim_getwidth(struct stm32_tim_dev_s *dev); +static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, + uint8_t channel, stm32_tim_channel_t mode); +static int stm32_tim_setcompare(struct stm32_tim_dev_s *dev, + uint8_t channel, uint32_t compare); +static int stm32_tim_getcapture(struct stm32_tim_dev_s *dev, + uint8_t channel); +static int stm32_tim_setisr(struct stm32_tim_dev_s *dev, + xcpt_t handler, void *arg, int source); +static void stm32_tim_enableint(struct stm32_tim_dev_s *dev, + int source); +static void stm32_tim_disableint(struct stm32_tim_dev_s *dev, + int source); +static void stm32_tim_ackint(struct stm32_tim_dev_s *dev, int source); +static int stm32_tim_checkint(struct stm32_tim_dev_s *dev, int source); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static const struct stm32_tim_ops_s stm32_tim_ops = +{ + .enable = stm32_tim_enable, + .disable = stm32_tim_disable, + .setmode = stm32_tim_setmode, + .setclock = stm32_tim_setclock, + .setperiod = stm32_tim_setperiod, + .getcounter = stm32_tim_getcounter, + .setcounter = stm32_tim_setcounter, + .getwidth = stm32_tim_getwidth, + .setchannel = stm32_tim_setchannel, + .setcompare = stm32_tim_setcompare, + .getcapture = stm32_tim_getcapture, + .setisr = stm32_tim_setisr, + .enableint = stm32_tim_enableint, + .disableint = stm32_tim_disableint, + .ackint = stm32_tim_ackint, + .checkint = stm32_tim_checkint, +}; + +#ifdef CONFIG_STM32_TIM1 +struct stm32_tim_priv_s stm32_tim1_priv = +{ + .ops = &stm32_tim_ops, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM1_BASE, +}; +#endif +#ifdef CONFIG_STM32_TIM2 +struct stm32_tim_priv_s stm32_tim2_priv = +{ + .ops = &stm32_tim_ops, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM2_BASE, +}; +#endif + +#ifdef CONFIG_STM32_TIM3 +struct stm32_tim_priv_s stm32_tim3_priv = +{ + .ops = &stm32_tim_ops, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM3_BASE, +}; +#endif + +#ifdef CONFIG_STM32_TIM4 +struct stm32_tim_priv_s stm32_tim4_priv = +{ + .ops = &stm32_tim_ops, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM4_BASE, +}; +#endif + +#ifdef CONFIG_STM32_TIM5 +struct stm32_tim_priv_s stm32_tim5_priv = +{ + .ops = &stm32_tim_ops, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM5_BASE, +}; +#endif + +#ifdef CONFIG_STM32_TIM6 +struct stm32_tim_priv_s stm32_tim6_priv = +{ + .ops = &stm32_tim_ops, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM6_BASE, +}; +#endif + +#ifdef CONFIG_STM32_TIM7 +struct stm32_tim_priv_s stm32_tim7_priv = +{ + .ops = &stm32_tim_ops, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM7_BASE, +}; +#endif + +#ifdef CONFIG_STM32_TIM8 +struct stm32_tim_priv_s stm32_tim8_priv = +{ + .ops = &stm32_tim_ops, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM8_BASE, +}; +#endif + +#ifdef CONFIG_STM32_TIM9 +struct stm32_tim_priv_s stm32_tim9_priv = +{ + .ops = &stm32_tim_ops, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM9_BASE, +}; +#endif + +#ifdef CONFIG_STM32_TIM10 +struct stm32_tim_priv_s stm32_tim10_priv = +{ + .ops = &stm32_tim_ops, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM10_BASE, +}; +#endif + +#ifdef CONFIG_STM32_TIM11 +struct stm32_tim_priv_s stm32_tim11_priv = +{ + .ops = &stm32_tim_ops, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM11_BASE, +}; +#endif + +#ifdef CONFIG_STM32_TIM12 +struct stm32_tim_priv_s stm32_tim12_priv = +{ + .ops = &stm32_tim_ops, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM12_BASE, +}; +#endif + +#ifdef CONFIG_STM32_TIM13 +struct stm32_tim_priv_s stm32_tim13_priv = +{ + .ops = &stm32_tim_ops, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM13_BASE, +}; +#endif + +#ifdef CONFIG_STM32_TIM14 +struct stm32_tim_priv_s stm32_tim14_priv = +{ + .ops = &stm32_tim_ops, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM14_BASE, +}; +#endif + +#ifdef CONFIG_STM32_TIM15 +struct stm32_tim_priv_s stm32_tim15_priv = +{ + .ops = &stm32_tim_ops, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM15_BASE, +}; +#endif + +#ifdef CONFIG_STM32_TIM16 +struct stm32_tim_priv_s stm32_tim16_priv = +{ + .ops = &stm32_tim_ops, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM16_BASE, +}; +#endif + +#ifdef CONFIG_STM32_TIM17 +struct stm32_tim_priv_s stm32_tim17_priv = +{ + .ops = &stm32_tim_ops, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM17_BASE, +}; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_getreg16 + * + * Description: + * Get a 16-bit register value by offset + * + ****************************************************************************/ + +static inline uint16_t stm32_getreg16(struct stm32_tim_dev_s *dev, + uint8_t offset) +{ + return getreg16(((struct stm32_tim_priv_s *)dev)->base + offset); +} + +/**************************************************************************** + * Name: stm32_putreg16 + * + * Description: + * Put a 16-bit register value by offset + * + ****************************************************************************/ + +static inline void stm32_putreg16(struct stm32_tim_dev_s *dev, + uint8_t offset, uint16_t value) +{ + putreg16(value, ((struct stm32_tim_priv_s *)dev)->base + offset); +} + +/**************************************************************************** + * Name: stm32_modifyreg16 + * + * Description: + * Modify a 16-bit register value by offset + * + ****************************************************************************/ + +static inline void stm32_modifyreg16(struct stm32_tim_dev_s *dev, + uint8_t offset, uint16_t clearbits, + uint16_t setbits) +{ + modifyreg16(((struct stm32_tim_priv_s *)dev)->base + offset, + clearbits, setbits); +} + +/**************************************************************************** + * Name: stm32_getreg32 + * + * Description: + * Get a 32-bit register value by offset. This applies only for the STM32 + * F4 32-bit registers (CNT, ARR, CRR1-4) in the 32-bit timers TIM2-5. + * + ****************************************************************************/ + +static inline uint32_t stm32_getreg32(struct stm32_tim_dev_s *dev, + uint8_t offset) +{ + return getreg32(((struct stm32_tim_priv_s *)dev)->base + offset); +} + +/**************************************************************************** + * Name: stm32_putreg32 + * + * Description: + * Put a 32-bit register value by offset. This applies only for the STM32 + * F4 32-bit registers (CNT, ARR, CRR1-4) in the 32-bit timers TIM2-5. + * + ****************************************************************************/ + +static inline void stm32_putreg32(struct stm32_tim_dev_s *dev, + uint8_t offset, uint32_t value) +{ + putreg32(value, ((struct stm32_tim_priv_s *)dev)->base + offset); +} + +/**************************************************************************** + * Name: stm32_tim_reload_counter + ****************************************************************************/ + +static void stm32_tim_reload_counter(struct stm32_tim_dev_s *dev) +{ + uint16_t val = stm32_getreg16(dev, STM32_GTIM_EGR_OFFSET); + val |= GTIM_EGR_UG; + stm32_putreg16(dev, STM32_GTIM_EGR_OFFSET, val); +} + +/**************************************************************************** + * Name: stm32_tim_enable + ****************************************************************************/ + +static void stm32_tim_enable(struct stm32_tim_dev_s *dev) +{ + uint16_t val = stm32_getreg16(dev, STM32_GTIM_CR1_OFFSET); + val |= GTIM_CR1_CEN; + stm32_tim_reload_counter(dev); + stm32_putreg16(dev, STM32_GTIM_CR1_OFFSET, val); +} + +/**************************************************************************** + * Name: stm32_tim_disable + ****************************************************************************/ + +static void stm32_tim_disable(struct stm32_tim_dev_s *dev) +{ + uint16_t val = stm32_getreg16(dev, STM32_GTIM_CR1_OFFSET); + val &= ~GTIM_CR1_CEN; + stm32_putreg16(dev, STM32_GTIM_CR1_OFFSET, val); +} + +/**************************************************************************** + * Name: stm32_tim_reset + * + * Description: + * Reset timer into system default state, but do not affect output/input + * pins + * + ****************************************************************************/ + +static void stm32_tim_reset(struct stm32_tim_dev_s *dev) +{ + ((struct stm32_tim_priv_s *)dev)->mode = STM32_TIM_MODE_DISABLED; + stm32_tim_disable(dev); +} + +/**************************************************************************** + * Name: stm32_tim_gpioconfig + ****************************************************************************/ + +#ifdef HAVE_TIM_GPIOCONFIG +static void stm32_tim_gpioconfig(uint32_t cfg, stm32_tim_channel_t mode) +{ + /* TODO: Add support for input capture and bipolar dual outputs for TIM8 */ + + if (mode & STM32_TIM_CH_MODE_MASK) + { + stm32_configgpio(cfg); + } + else + { + stm32_unconfiggpio(cfg); + } +} +#endif + +/**************************************************************************** + * Name: stm32_tim_setmode + ****************************************************************************/ + +static int stm32_tim_setmode(struct stm32_tim_dev_s *dev, + stm32_tim_mode_t mode) +{ + uint16_t val = GTIM_CR1_CEN | GTIM_CR1_ARPE; + + DEBUGASSERT(dev != NULL); + + /* This function is not supported on basic timers. To enable or + * disable it, simply set its clock to valid frequency or zero. + */ + +#if STM32_NBTIM > 0 + if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM6_BASE +#endif +#if STM32_NBTIM > 1 + || ((struct stm32_tim_priv_s *)dev)->base == STM32_TIM7_BASE +#endif +#if STM32_NBTIM > 0 + ) + { + return -EINVAL; + } +#endif + + /* Decode operational modes */ + + switch (mode & STM32_TIM_MODE_MASK) + { + case STM32_TIM_MODE_DISABLED: + val = 0; + break; + + case STM32_TIM_MODE_DOWN: + val |= GTIM_CR1_DIR; + + case STM32_TIM_MODE_UP: + break; + + case STM32_TIM_MODE_UPDOWN: + /* Our default: + * Interrupts are generated on compare, when counting down + */ + + val |= GTIM_CR1_CENTER1; + break; + + case STM32_TIM_MODE_PULSE: + val |= GTIM_CR1_OPM; + break; + + default: + return -EINVAL; + } + + stm32_tim_reload_counter(dev); + stm32_putreg16(dev, STM32_GTIM_CR1_OFFSET, val); + +#if STM32_NATIM > 0 + /* Advanced registers require Main Output Enable */ + + if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM1_BASE +#ifdef STM32_TIM8_BASE + || ((struct stm32_tim_priv_s *)dev)->base == STM32_TIM8_BASE +#endif + ) + { + stm32_modifyreg16(dev, STM32_ATIM_BDTR_OFFSET, 0, ATIM_BDTR_MOE); + } +#endif + + return OK; +} + +/**************************************************************************** + * Name: stm32_tim_setclock + ****************************************************************************/ + +static int stm32_tim_setclock(struct stm32_tim_dev_s *dev, uint32_t freq) +{ + uint32_t freqin; + int prescaler; + + DEBUGASSERT(dev != NULL); + + /* Disable Timer? */ + + if (freq == 0) + { + stm32_tim_disable(dev); + return 0; + } + + /* Get the input clock frequency for this timer. These vary with + * different timer clock sources, MCU-specific timer configuration, and + * board-specific clock configuration. The correct input clock frequency + * must be defined in the board.h header file. + */ + + switch (((struct stm32_tim_priv_s *)dev)->base) + { +#ifdef CONFIG_STM32_TIM1 + case STM32_TIM1_BASE: + freqin = STM32_APB2_TIM1_CLKIN; + break; +#endif +#ifdef CONFIG_STM32_TIM2 + case STM32_TIM2_BASE: + freqin = STM32_APB1_TIM2_CLKIN; + break; +#endif +#ifdef CONFIG_STM32_TIM3 + case STM32_TIM3_BASE: + freqin = STM32_APB1_TIM3_CLKIN; + break; +#endif +#ifdef CONFIG_STM32_TIM4 + case STM32_TIM4_BASE: + freqin = STM32_APB1_TIM4_CLKIN; + break; +#endif +#ifdef CONFIG_STM32_TIM5 + case STM32_TIM5_BASE: + freqin = STM32_APB1_TIM5_CLKIN; + break; +#endif +#ifdef CONFIG_STM32_TIM6 + case STM32_TIM6_BASE: + freqin = STM32_APB1_TIM6_CLKIN; + break; +#endif +#ifdef CONFIG_STM32_TIM7 + case STM32_TIM7_BASE: + freqin = STM32_APB1_TIM7_CLKIN; + break; +#endif +#ifdef CONFIG_STM32_TIM8 + case STM32_TIM8_BASE: + freqin = STM32_APB2_TIM8_CLKIN; + break; +#endif +#ifdef CONFIG_STM32_TIM9 + case STM32_TIM9_BASE: + freqin = STM32_APB2_TIM9_CLKIN; + break; +#endif +#ifdef CONFIG_STM32_TIM10 + case STM32_TIM10_BASE: + freqin = STM32_APB2_TIM10_CLKIN; + break; +#endif +#ifdef CONFIG_STM32_TIM11 + case STM32_TIM11_BASE: + freqin = STM32_APB2_TIM11_CLKIN; + break; +#endif +#ifdef CONFIG_STM32_TIM12 + case STM32_TIM12_BASE: + freqin = STM32_APB1_TIM12_CLKIN; + break; +#endif +#ifdef CONFIG_STM32_TIM13 + case STM32_TIM13_BASE: + freqin = STM32_APB1_TIM13_CLKIN; + break; +#endif +#ifdef CONFIG_STM32_TIM14 + case STM32_TIM14_BASE: + freqin = STM32_APB1_TIM14_CLKIN; + break; +#endif +#ifdef CONFIG_STM32_TIM15 + case STM32_TIM15_BASE: + freqin = STM32_APB2_TIM15_CLKIN; + break; +#endif +#ifdef CONFIG_STM32_TIM16 + case STM32_TIM16_BASE: + freqin = STM32_APB2_TIM16_CLKIN; + break; +#endif +#ifdef CONFIG_STM32_TIM17 + case STM32_TIM17_BASE: + freqin = STM32_APB2_TIM17_CLKIN; + break; +#endif + + default: + return -EINVAL; + } + + /* Select a pre-scaler value for this timer using the input clock + * frequency. + */ + + prescaler = freqin / freq; + + /* We need to decrement value for '1', but only, if that will not to + * cause underflow. + */ + + if (prescaler > 0) + { + prescaler--; + } + + /* Check for overflow as well. */ + + if (prescaler > 0xffff) + { + prescaler = 0xffff; + } + + stm32_putreg16(dev, STM32_GTIM_PSC_OFFSET, prescaler); + stm32_tim_enable(dev); + + return prescaler; +} + +/**************************************************************************** + * Name: stm32_tim_setperiod + ****************************************************************************/ + +static void stm32_tim_setperiod(struct stm32_tim_dev_s *dev, + uint32_t period) +{ + DEBUGASSERT(dev != NULL); + stm32_putreg32(dev, STM32_GTIM_ARR_OFFSET, period); +} + +/**************************************************************************** + * Name: stm32_tim_getcounter + ****************************************************************************/ + +static uint32_t stm32_tim_getcounter(struct stm32_tim_dev_s *dev) +{ + DEBUGASSERT(dev != NULL); + return stm32_tim_getwidth(dev) > 16 ? + stm32_getreg32(dev, STM32_GTIM_CNT_OFFSET) : + (uint32_t)stm32_getreg16(dev, STM32_GTIM_CNT_OFFSET); +} + +/**************************************************************************** + * Name: stm32_tim_setcounter + ****************************************************************************/ + +static void stm32_tim_setcounter(struct stm32_tim_dev_s *dev, + uint32_t count) +{ + DEBUGASSERT(dev != NULL); + + if (stm32_tim_getwidth(dev) > 16) + { + stm32_putreg32(dev, STM32_GTIM_CNT_OFFSET, count); + } + else + { + stm32_putreg16(dev, STM32_GTIM_CNT_OFFSET, (uint16_t)count); + } +} + +/**************************************************************************** + * Name: stm32_tim_getwidth + ****************************************************************************/ + +static int stm32_tim_getwidth(struct stm32_tim_dev_s *dev) +{ + /* Only TIM2 and TIM5 timers may be 32-bits in width + * + * Reference Table 2 of en.DM00042534.pdf + */ + + switch (((struct stm32_tim_priv_s *)dev)->base) + { + /* TIM2 is 32-bits on all except F10x, L0x, and L1x lines */ + +#if defined(CONFIG_STM32_TIM2) && !defined(STM32_STM32F10XX) && \ + !defined(STM32_STM32L15XX) + case STM32_TIM2_BASE: + return 32; +#endif + + /* TIM5 is 32-bits on all except F10x lines */ + +#if defined(CONFIG_STM32_TIM5) && !defined(STM32_STM32F10XX) + case STM32_TIM5_BASE: + return 32; +#endif + + /* All others are 16-bit times */ + + default: + return 16; + } +} + +/**************************************************************************** + * Name: stm32_tim_setchannel + ****************************************************************************/ + +static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, + uint8_t channel, stm32_tim_channel_t mode) +{ + uint16_t ccmr_orig = 0; + uint16_t ccmr_val = 0; + uint16_t ccmr_mask = 0xff; + uint16_t ccer_val = stm32_getreg16(dev, STM32_GTIM_CCER_OFFSET); + uint8_t ccmr_offset = STM32_GTIM_CCMR1_OFFSET; + + DEBUGASSERT(dev != NULL); + + /* Further we use range as 0..3; if channel=0 it will also overflow here */ + + if (--channel > 4) + { + return -EINVAL; + } + + /* Assume that channel is disabled and polarity is active high */ + + ccer_val &= ~((GTIM_CCER_CC1P | GTIM_CCER_CC1E) << + GTIM_CCER_CCXBASE(channel)); + + /* This function is not supported on basic timers. To enable or + * disable it, simply set its clock to valid frequency or zero. + */ + +#if STM32_NBTIM > 0 + if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM6_BASE +#endif +#if STM32_NBTIM > 1 + || ((struct stm32_tim_priv_s *)dev)->base == STM32_TIM7_BASE +#endif +#if STM32_NBTIM > 0 + ) + { + return -EINVAL; + } +#endif + + /* Decode configuration */ + + switch (mode & STM32_TIM_CH_MODE_MASK) + { + case STM32_TIM_CH_DISABLED: + break; + + case STM32_TIM_CH_OUTPWM: + ccmr_val = (GTIM_CCMR_MODE_PWM1 << GTIM_CCMR1_OC1M_SHIFT) + + GTIM_CCMR1_OC1PE; + ccer_val |= GTIM_CCER_CC1E << GTIM_CCER_CCXBASE(channel); + break; + + default: + return -EINVAL; + } + + /* Set polarity */ + + if (mode & STM32_TIM_CH_POLARITY_NEG) + { + ccer_val |= GTIM_CCER_CC1P << GTIM_CCER_CCXBASE(channel); + } + + /* Define its position (shift) and get register offset */ + + if (channel & 1) + { + ccmr_val <<= 8; + ccmr_mask <<= 8; + } + + if (channel > 1) + { + ccmr_offset = STM32_GTIM_CCMR2_OFFSET; + } + + ccmr_orig = stm32_getreg16(dev, ccmr_offset); + ccmr_orig &= ~ccmr_mask; + ccmr_orig |= ccmr_val; + stm32_putreg16(dev, ccmr_offset, ccmr_orig); + stm32_putreg16(dev, STM32_GTIM_CCER_OFFSET, ccer_val); + + /* set GPIO */ + + switch (((struct stm32_tim_priv_s *)dev)->base) + { +#ifdef CONFIG_STM32_TIM1 + case STM32_TIM1_BASE: + switch (channel) + { +#if defined(GPIO_TIM1_CH1OUT) + case 0: + stm32_tim_gpioconfig(GPIO_TIM1_CH1OUT, mode); break; +#endif +#if defined(GPIO_TIM1_CH2OUT) + case 1: + stm32_tim_gpioconfig(GPIO_TIM1_CH2OUT, mode); break; +#endif +#if defined(GPIO_TIM1_CH3OUT) + case 2: + stm32_tim_gpioconfig(GPIO_TIM1_CH3OUT, mode); break; +#endif +#if defined(GPIO_TIM1_CH4OUT) + case 3: + stm32_tim_gpioconfig(GPIO_TIM1_CH4OUT, mode); break; +#endif + default: + return -EINVAL; + } + break; +#endif +#ifdef CONFIG_STM32_TIM2 + case STM32_TIM2_BASE: + switch (channel) + { +#if defined(GPIO_TIM2_CH1OUT) + case 0: + stm32_tim_gpioconfig(GPIO_TIM2_CH1OUT, mode); + break; +#endif +#if defined(GPIO_TIM2_CH2OUT) + case 1: + stm32_tim_gpioconfig(GPIO_TIM2_CH2OUT, mode); + break; +#endif +#if defined(GPIO_TIM2_CH3OUT) + case 2: + stm32_tim_gpioconfig(GPIO_TIM2_CH3OUT, mode); + break; +#endif +#if defined(GPIO_TIM2_CH4OUT) + case 3: + stm32_tim_gpioconfig(GPIO_TIM2_CH4OUT, mode); + break; +#endif + default: + return -EINVAL; + } + break; +#endif +#ifdef CONFIG_STM32_TIM3 + case STM32_TIM3_BASE: + switch (channel) + { +#if defined(GPIO_TIM3_CH1OUT) + case 0: + stm32_tim_gpioconfig(GPIO_TIM3_CH1OUT, mode); + break; +#endif +#if defined(GPIO_TIM3_CH2OUT) + case 1: + stm32_tim_gpioconfig(GPIO_TIM3_CH2OUT, mode); + break; +#endif +#if defined(GPIO_TIM3_CH3OUT) + case 2: + stm32_tim_gpioconfig(GPIO_TIM3_CH3OUT, mode); + break; +#endif +#if defined(GPIO_TIM3_CH4OUT) + case 3: + stm32_tim_gpioconfig(GPIO_TIM3_CH4OUT, mode); + break; +#endif + default: + return -EINVAL; + } + break; +#endif +#ifdef CONFIG_STM32_TIM4 + case STM32_TIM4_BASE: + switch (channel) + { +#if defined(GPIO_TIM4_CH1OUT) + case 0: + stm32_tim_gpioconfig(GPIO_TIM4_CH1OUT, mode); + break; +#endif +#if defined(GPIO_TIM4_CH2OUT) + case 1: + stm32_tim_gpioconfig(GPIO_TIM4_CH2OUT, mode); + break; +#endif +#if defined(GPIO_TIM4_CH3OUT) + case 2: + stm32_tim_gpioconfig(GPIO_TIM4_CH3OUT, mode); + break; +#endif +#if defined(GPIO_TIM4_CH4OUT) + case 3: + stm32_tim_gpioconfig(GPIO_TIM4_CH4OUT, mode); + break; +#endif + default: + return -EINVAL; + } + break; +#endif +#ifdef CONFIG_STM32_TIM5 + case STM32_TIM5_BASE: + switch (channel) + { +#if defined(GPIO_TIM5_CH1OUT) + case 0: + stm32_tim_gpioconfig(GPIO_TIM5_CH1OUT, mode); + break; +#endif +#if defined(GPIO_TIM5_CH2OUT) + case 1: + stm32_tim_gpioconfig(GPIO_TIM5_CH2OUT, mode); + break; +#endif +#if defined(GPIO_TIM5_CH3OUT) + case 2: + stm32_tim_gpioconfig(GPIO_TIM5_CH3OUT, mode); + break; +#endif +#if defined(GPIO_TIM5_CH4OUT) + case 3: + stm32_tim_gpioconfig(GPIO_TIM5_CH4OUT, mode); + break; +#endif + default: + return -EINVAL; + } + break; +#endif +#ifdef CONFIG_STM32_TIM8 + case STM32_TIM8_BASE: + switch (channel) + { +#if defined(GPIO_TIM8_CH1OUT) + case 0: + stm32_tim_gpioconfig(GPIO_TIM8_CH1OUT, mode); break; +#endif +#if defined(GPIO_TIM8_CH2OUT) + case 1: + stm32_tim_gpioconfig(GPIO_TIM8_CH2OUT, mode); break; +#endif +#if defined(GPIO_TIM8_CH3OUT) + case 2: + stm32_tim_gpioconfig(GPIO_TIM8_CH3OUT, mode); break; +#endif +#if defined(GPIO_TIM8_CH4OUT) + case 3: + stm32_tim_gpioconfig(GPIO_TIM8_CH4OUT, mode); break; +#endif + default: + return -EINVAL; + } + break; +#endif +#ifdef CONFIG_STM32_TIM9 + case STM32_TIM9_BASE: + switch (channel) + { +#if defined(GPIO_TIM9_CH1OUT) + case 0: + stm32_tim_gpioconfig(GPIO_TIM9_CH1OUT, mode); + break; +#endif +#if defined(GPIO_TIM9_CH2OUT) + case 1: + stm32_tim_gpioconfig(GPIO_TIM9_CH2OUT, mode); + break; +#endif +#if defined(GPIO_TIM9_CH3OUT) + case 2: + stm32_tim_gpioconfig(GPIO_TIM9_CH3OUT, mode); + break; +#endif +#if defined(GPIO_TIM9_CH4OUT) + case 3: + stm32_tim_gpioconfig(GPIO_TIM9_CH4OUT, mode); + break; +#endif + default: + return -EINVAL; + } + break; +#endif +#ifdef CONFIG_STM32_TIM10 + case STM32_TIM10_BASE: + switch (channel) + { +#if defined(GPIO_TIM10_CH1OUT) + case 0: + stm32_tim_gpioconfig(GPIO_TIM10_CH1OUT, mode); + break; +#endif +#if defined(GPIO_TIM10_CH2OUT) + case 1: + stm32_tim_gpioconfig(GPIO_TIM10_CH2OUT, mode); + break; +#endif +#if defined(GPIO_TIM10_CH3OUT) + case 2: + stm32_tim_gpioconfig(GPIO_TIM10_CH3OUT, mode); + break; +#endif +#if defined(GPIO_TIM10_CH4OUT) + case 3: + stm32_tim_gpioconfig(GPIO_TIM10_CH4OUT, mode); + break; +#endif + default: + return -EINVAL; + } + break; +#endif +#ifdef CONFIG_STM32_TIM11 + case STM32_TIM11_BASE: + switch (channel) + { +#if defined(GPIO_TIM11_CH1OUT) + case 0: + stm32_tim_gpioconfig(GPIO_TIM11_CH1OUT, mode); + break; +#endif +#if defined(GPIO_TIM11_CH2OUT) + case 1: + stm32_tim_gpioconfig(GPIO_TIM11_CH2OUT, mode); + break; +#endif +#if defined(GPIO_TIM11_CH3OUT) + case 2: + stm32_tim_gpioconfig(GPIO_TIM11_CH3OUT, mode); + break; +#endif +#if defined(GPIO_TIM11_CH4OUT) + case 3: + stm32_tim_gpioconfig(GPIO_TIM11_CH4OUT, mode); + break; +#endif + default: + return -EINVAL; + } + break; +#endif +#ifdef CONFIG_STM32_TIM12 + case STM32_TIM12_BASE: + switch (channel) + { +#if defined(GPIO_TIM12_CH1OUT) + case 0: + stm32_tim_gpioconfig(GPIO_TIM12_CH1OUT, mode); + break; +#endif +#if defined(GPIO_TIM12_CH2OUT) + case 1: + stm32_tim_gpioconfig(GPIO_TIM12_CH2OUT, mode); + break; +#endif +#if defined(GPIO_TIM12_CH3OUT) + case 2: + stm32_tim_gpioconfig(GPIO_TIM12_CH3OUT, mode); + break; +#endif +#if defined(GPIO_TIM12_CH4OUT) + case 3: + stm32_tim_gpioconfig(GPIO_TIM12_CH4OUT, mode); + break; +#endif + default: + return -EINVAL; + } + break; +#endif +#ifdef CONFIG_STM32_TIM13 + case STM32_TIM13_BASE: + switch (channel) + { +#if defined(GPIO_TIM13_CH1OUT) + case 0: + stm32_tim_gpioconfig(GPIO_TIM13_CH1OUT, mode); + break; +#endif +#if defined(GPIO_TIM13_CH2OUT) + case 1: + stm32_tim_gpioconfig(GPIO_TIM13_CH2OUT, mode); + break; +#endif +#if defined(GPIO_TIM13_CH3OUT) + case 2: + stm32_tim_gpioconfig(GPIO_TIM13_CH3OUT, mode); + break; +#endif +#if defined(GPIO_TIM13_CH4OUT) + case 3: + stm32_tim_gpioconfig(GPIO_TIM13_CH4OUT, mode); + break; +#endif + default: + return -EINVAL; + } + break; +#endif +#ifdef CONFIG_STM32_TIM14 + case STM32_TIM14_BASE: + switch (channel) + { +#if defined(GPIO_TIM14_CH1OUT) + case 0: + stm32_tim_gpioconfig(GPIO_TIM14_CH1OUT, mode); + break; +#endif +#if defined(GPIO_TIM14_CH2OUT) + case 1: + stm32_tim_gpioconfig(GPIO_TIM14_CH2OUT, mode); + break; +#endif +#if defined(GPIO_TIM14_CH3OUT) + case 2: + stm32_tim_gpioconfig(GPIO_TIM14_CH3OUT, mode); + break; +#endif +#if defined(GPIO_TIM14_CH4OUT) + case 3: + stm32_tim_gpioconfig(GPIO_TIM14_CH4OUT, mode); + break; +#endif + default: + return -EINVAL; + } + break; +#endif +#ifdef CONFIG_STM32_TIM15 + case STM32_TIM15_BASE: + switch (channel) + { +#if defined(GPIO_TIM15_CH1OUT) + case 0: + stm32_tim_gpioconfig(GPIO_TIM15_CH1OUT, mode); + break; +#endif +#if defined(GPIO_TIM15_CH2OUT) + case 1: + stm32_tim_gpioconfig(GPIO_TIM15_CH2OUT, mode); + break; +#endif +#if defined(GPIO_TIM15_CH3OUT) + case 2: + stm32_tim_gpioconfig(GPIO_TIM15_CH3OUT, mode); + break; +#endif +#if defined(GPIO_TIM15_CH4OUT) + case 3: + stm32_tim_gpioconfig(GPIO_TIM15_CH4OUT, mode); + break; +#endif + default: + return -EINVAL; + } + break; +#endif +#ifdef CONFIG_STM32_TIM16 + case STM32_TIM16_BASE: + switch (channel) + { +#if defined(GPIO_TIM16_CH1OUT) + case 0: + stm32_tim_gpioconfig(GPIO_TIM16_CH1OUT, mode); + break; +#endif +#if defined(GPIO_TIM16_CH2OUT) + case 1: + stm32_tim_gpioconfig(GPIO_TIM16_CH2OUT, mode); + break; +#endif +#if defined(GPIO_TIM16_CH3OUT) + case 2: + stm32_tim_gpioconfig(GPIO_TIM16_CH3OUT, mode); + break; +#endif +#if defined(GPIO_TIM16_CH4OUT) + case 3: + stm32_tim_gpioconfig(GPIO_TIM16_CH4OUT, mode); + break; +#endif + default: + return -EINVAL; + } + break; +#endif +#ifdef CONFIG_STM32_TIM17 + case STM32_TIM17_BASE: + switch (channel) + { +#if defined(GPIO_TIM17_CH1OUT) + case 0: + stm32_tim_gpioconfig(GPIO_TIM17_CH1OUT, mode); + break; +#endif +#if defined(GPIO_TIM17_CH2OUT) + case 1: + stm32_tim_gpioconfig(GPIO_TIM17_CH2OUT, mode); + break; +#endif +#if defined(GPIO_TIM17_CH3OUT) + case 2: + stm32_tim_gpioconfig(GPIO_TIM17_CH3OUT, mode); + break; +#endif +#if defined(GPIO_TIM17_CH4OUT) + case 3: + stm32_tim_gpioconfig(GPIO_TIM17_CH4OUT, mode); + break; +#endif + default: + return -EINVAL; + } + break; +#endif + default: + return -EINVAL; + } + + return OK; +} + +/**************************************************************************** + * Name: stm32_tim_setcompare + ****************************************************************************/ + +static int stm32_tim_setcompare(struct stm32_tim_dev_s *dev, + uint8_t channel, uint32_t compare) +{ + DEBUGASSERT(dev != NULL); + + switch (channel) + { + case 1: + stm32_putreg32(dev, STM32_GTIM_CCR1_OFFSET, compare); + break; + + case 2: + stm32_putreg32(dev, STM32_GTIM_CCR2_OFFSET, compare); + break; + + case 3: + stm32_putreg32(dev, STM32_GTIM_CCR3_OFFSET, compare); + break; + + case 4: + stm32_putreg32(dev, STM32_GTIM_CCR4_OFFSET, compare); + break; + + default: + return -EINVAL; + } + + return OK; +} + +/**************************************************************************** + * Name: stm32_tim_getcapture + ****************************************************************************/ + +static int stm32_tim_getcapture(struct stm32_tim_dev_s *dev, + uint8_t channel) +{ + DEBUGASSERT(dev != NULL); + + switch (channel) + { + case 1: + return stm32_getreg32(dev, STM32_GTIM_CCR1_OFFSET); + case 2: + return stm32_getreg32(dev, STM32_GTIM_CCR2_OFFSET); + case 3: + return stm32_getreg32(dev, STM32_GTIM_CCR3_OFFSET); + case 4: + return stm32_getreg32(dev, STM32_GTIM_CCR4_OFFSET); + } + + return -EINVAL; +} + +/**************************************************************************** + * Name: stm32_tim_setisr + ****************************************************************************/ + +static int stm32_tim_setisr(struct stm32_tim_dev_s *dev, xcpt_t handler, + void * arg, int source) +{ + int vectorno; + + DEBUGASSERT(dev != NULL); + DEBUGASSERT(source == 0); + + switch (((struct stm32_tim_priv_s *)dev)->base) + { +#ifdef CONFIG_STM32_TIM1 + case STM32_TIM1_BASE: + vectorno = STM32_IRQ_TIM1UP; + break; +#endif +#ifdef CONFIG_STM32_TIM2 + case STM32_TIM2_BASE: + vectorno = STM32_IRQ_TIM2; + break; +#endif +#ifdef CONFIG_STM32_TIM3 + case STM32_TIM3_BASE: + vectorno = STM32_IRQ_TIM3; + break; +#endif +#ifdef CONFIG_STM32_TIM4 + case STM32_TIM4_BASE: + vectorno = STM32_IRQ_TIM4; + break; +#endif +#ifdef CONFIG_STM32_TIM5 + case STM32_TIM5_BASE: + vectorno = STM32_IRQ_TIM5; + break; +#endif +#ifdef CONFIG_STM32_TIM6 + case STM32_TIM6_BASE: + vectorno = STM32_IRQ_TIM6; + break; +#endif +#ifdef CONFIG_STM32_TIM7 + case STM32_TIM7_BASE: + vectorno = STM32_IRQ_TIM7; + break; +#endif +#ifdef CONFIG_STM32_TIM8 + case STM32_TIM8_BASE: + vectorno = STM32_IRQ_TIM8UP; + break; +#endif +#ifdef CONFIG_STM32_TIM9 + case STM32_TIM9_BASE: + vectorno = STM32_IRQ_TIM9; + break; +#endif +#ifdef CONFIG_STM32_TIM10 + case STM32_TIM10_BASE: + vectorno = STM32_IRQ_TIM10; + break; +#endif +#ifdef CONFIG_STM32_TIM11 + case STM32_TIM11_BASE: + vectorno = STM32_IRQ_TIM11; + break; +#endif +#ifdef CONFIG_STM32_TIM12 + case STM32_TIM12_BASE: + vectorno = STM32_IRQ_TIM12; + break; +#endif +#ifdef CONFIG_STM32_TIM13 + case STM32_TIM13_BASE: + vectorno = STM32_IRQ_TIM13; + break; +#endif +#ifdef CONFIG_STM32_TIM14 + case STM32_TIM14_BASE: + vectorno = STM32_IRQ_TIM14; + break; +#endif +#ifdef CONFIG_STM32_TIM15 + case STM32_TIM15_BASE: + vectorno = STM32_IRQ_TIM15; + break; +#endif +#ifdef CONFIG_STM32_TIM16 + case STM32_TIM16_BASE: + vectorno = STM32_IRQ_TIM16; + break; +#endif +#ifdef CONFIG_STM32_TIM17 + case STM32_TIM17_BASE: + vectorno = STM32_IRQ_TIM17; + break; +#endif + + default: + return -EINVAL; + } + + /* Disable interrupt when callback is removed */ + + if (!handler) + { + up_disable_irq(vectorno); + irq_detach(vectorno); + return OK; + } + + /* Otherwise set callback and enable interrupt */ + + irq_attach(vectorno, handler, arg); + up_enable_irq(vectorno); + + return OK; +} + +/**************************************************************************** + * Name: stm32_tim_enableint + ****************************************************************************/ + +static void stm32_tim_enableint(struct stm32_tim_dev_s *dev, int source) +{ + DEBUGASSERT(dev != NULL); + stm32_modifyreg16(dev, STM32_GTIM_DIER_OFFSET, 0, source); +} + +/**************************************************************************** + * Name: stm32_tim_disableint + ****************************************************************************/ + +static void stm32_tim_disableint(struct stm32_tim_dev_s *dev, int source) +{ + DEBUGASSERT(dev != NULL); + stm32_modifyreg16(dev, STM32_GTIM_DIER_OFFSET, source, 0); +} + +/**************************************************************************** + * Name: stm32_tim_ackint + ****************************************************************************/ + +static void stm32_tim_ackint(struct stm32_tim_dev_s *dev, int source) +{ + stm32_putreg16(dev, STM32_GTIM_SR_OFFSET, ~source); +} + +/**************************************************************************** + * Name: stm32_tim_checkint + ****************************************************************************/ + +static int stm32_tim_checkint(struct stm32_tim_dev_s *dev, int source) +{ + uint16_t regval = stm32_getreg16(dev, STM32_GTIM_SR_OFFSET); + return (regval & source) ? 1 : 0; +} + +/**************************************************************************** + * Pubic Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_tim_init + ****************************************************************************/ + +struct stm32_tim_dev_s *stm32_tim_init(int timer) +{ + struct stm32_tim_dev_s *dev = NULL; + + /* Get structure and enable power */ + + switch (timer) + { +#ifdef CONFIG_STM32_TIM1 + case 1: + dev = (struct stm32_tim_dev_s *)&stm32_tim1_priv; + modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM1EN); + break; +#endif +#ifdef CONFIG_STM32_TIM2 + case 2: + dev = (struct stm32_tim_dev_s *)&stm32_tim2_priv; + modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM2EN); + break; +#endif +#ifdef CONFIG_STM32_TIM3 + case 3: + dev = (struct stm32_tim_dev_s *)&stm32_tim3_priv; + modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM3EN); + break; +#endif +#ifdef CONFIG_STM32_TIM4 + case 4: + dev = (struct stm32_tim_dev_s *)&stm32_tim4_priv; + modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM4EN); + break; +#endif +#ifdef CONFIG_STM32_TIM5 + case 5: + dev = (struct stm32_tim_dev_s *)&stm32_tim5_priv; + modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM5EN); + break; +#endif +#ifdef CONFIG_STM32_TIM6 + case 6: + dev = (struct stm32_tim_dev_s *)&stm32_tim6_priv; + modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM6EN); + break; +#endif +#ifdef CONFIG_STM32_TIM7 + case 7: + dev = (struct stm32_tim_dev_s *)&stm32_tim7_priv; + modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM7EN); + break; +#endif +#ifdef CONFIG_STM32_TIM8 + case 8: + dev = (struct stm32_tim_dev_s *)&stm32_tim8_priv; + modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM8EN); + break; +#endif +#ifdef CONFIG_STM32_TIM9 + case 9: + dev = (struct stm32_tim_dev_s *)&stm32_tim9_priv; + modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM9EN); + break; +#endif +#ifdef CONFIG_STM32_TIM10 + case 10: + dev = (struct stm32_tim_dev_s *)&stm32_tim10_priv; + modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM10EN); + break; +#endif +#ifdef CONFIG_STM32_TIM11 + case 11: + dev = (struct stm32_tim_dev_s *)&stm32_tim11_priv; + modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM11EN); + break; +#endif +#ifdef CONFIG_STM32_TIM12 + case 12: + dev = (struct stm32_tim_dev_s *)&stm32_tim12_priv; + modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM12EN); + break; +#endif +#ifdef CONFIG_STM32_TIM13 + case 13: + dev = (struct stm32_tim_dev_s *)&stm32_tim13_priv; + modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM13EN); + break; +#endif +#ifdef CONFIG_STM32_TIM14 + case 14: + dev = (struct stm32_tim_dev_s *)&stm32_tim14_priv; + modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM14EN); + break; +#endif +#ifdef CONFIG_STM32_TIM15 + case 15: + dev = (struct stm32_tim_dev_s *)&stm32_tim15_priv; + modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM15EN); + break; +#endif +#ifdef CONFIG_STM32_TIM16 + case 16: + dev = (struct stm32_tim_dev_s *)&stm32_tim16_priv; + modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM16EN); + break; +#endif +#ifdef CONFIG_STM32_TIM17 + case 17: + dev = (struct stm32_tim_dev_s *)&stm32_tim17_priv; + modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM17EN); + break; +#endif + default: + return NULL; + } + + /* Is device already allocated */ + + if (((struct stm32_tim_priv_s *)dev)->mode != STM32_TIM_MODE_UNUSED) + { + return NULL; + } + + stm32_tim_reset(dev); + + return dev; +} + +/**************************************************************************** + * Name: stm32_tim_deinit + * + * TODO: Detach interrupts, and close down all TIM Channels + * + ****************************************************************************/ + +int stm32_tim_deinit(struct stm32_tim_dev_s * dev) +{ + DEBUGASSERT(dev != NULL); + + /* Disable power */ + + switch (((struct stm32_tim_priv_s *)dev)->base) + { +#ifdef CONFIG_STM32_TIM1 + case STM32_TIM1_BASE: + modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM1EN, 0); + break; +#endif +#ifdef CONFIG_STM32_TIM2 + case STM32_TIM2_BASE: + modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM2EN, 0); + break; +#endif +#ifdef CONFIG_STM32_TIM3 + case STM32_TIM3_BASE: + modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM3EN, 0); + break; +#endif +#ifdef CONFIG_STM32_TIM4 + case STM32_TIM4_BASE: + modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM4EN, 0); + break; +#endif +#ifdef CONFIG_STM32_TIM5 + case STM32_TIM5_BASE: + modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM5EN, 0); + break; +#endif +#ifdef CONFIG_STM32_TIM6 + case STM32_TIM6_BASE: + modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM6EN, 0); + break; +#endif +#ifdef CONFIG_STM32_TIM7 + case STM32_TIM7_BASE: + modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM7EN, 0); + break; +#endif +#ifdef CONFIG_STM32_TIM8 + case STM32_TIM8_BASE: + modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM8EN, 0); + break; +#endif +#ifdef CONFIG_STM32_TIM9 + case STM32_TIM9_BASE: + modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM9EN, 0); + break; +#endif +#ifdef CONFIG_STM32_TIM10 + case STM32_TIM10_BASE: + modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM10EN, 0); + break; +#endif +#ifdef CONFIG_STM32_TIM11 + case STM32_TIM11_BASE: + modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM11EN, 0); + break; +#endif +#ifdef CONFIG_STM32_TIM12 + case STM32_TIM12_BASE: + modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM12EN, 0); + break; +#endif +#ifdef CONFIG_STM32_TIM13 + case STM32_TIM13_BASE: + modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM13EN, 0); + break; +#endif +#ifdef CONFIG_STM32_TIM14 + case STM32_TIM14_BASE: + modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM14EN, 0); + break; +#endif +#ifdef CONFIG_STM32_TIM15 + case STM32_TIM15_BASE: + modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM15EN, 0); + break; +#endif +#ifdef CONFIG_STM32_TIM16 + case STM32_TIM16_BASE: + modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM16EN, 0); + break; +#endif +#ifdef CONFIG_STM32_TIM17 + case STM32_TIM17_BASE: + modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM17EN, 0); + break; +#endif + default: + return -EINVAL; + } + + /* Mark it as free */ + + ((struct stm32_tim_priv_s *)dev)->mode = STM32_TIM_MODE_UNUSED; + + return OK; +} + +#endif /* defined(CONFIG_STM32_TIM1 || ... || TIM17) */ diff --git a/arch/arm/src/common/stm32/stm32_tim_m3m4_v1v2v3.h b/arch/arm/src/common/stm32/stm32_tim_m3m4_v1v2v3.h new file mode 100644 index 0000000000000..9bd99fb862f29 --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_tim_m3m4_v1v2v3.h @@ -0,0 +1,225 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_tim_m3m4_v1v2v3.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_TIM_V1V2V3_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_TIM_V1V2V3_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "chip.h" +#include "hardware/stm32_tim.h" + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Helpers ******************************************************************/ + +#define STM32_TIM_SETMODE(d,mode) ((d)->ops->setmode(d,mode)) +#define STM32_TIM_SETCLOCK(d,freq) ((d)->ops->setclock(d,freq)) +#define STM32_TIM_SETPERIOD(d,period) ((d)->ops->setperiod(d,period)) +#define STM32_TIM_GETCOUNTER(d) ((d)->ops->getcounter(d)) +#define STM32_TIM_SETCOUNTER(d,c) ((d)->ops->setcounter(d,c)) +#define STM32_TIM_GETWIDTH(d) ((d)->ops->getwidth(d)) +#define STM32_TIM_SETCHANNEL(d,ch,mode) ((d)->ops->setchannel(d,ch,mode)) +#define STM32_TIM_SETCOMPARE(d,ch,comp) ((d)->ops->setcompare(d,ch,comp)) +#define STM32_TIM_GETCAPTURE(d,ch) ((d)->ops->getcapture(d,ch)) +#define STM32_TIM_SETISR(d,hnd,arg,s) ((d)->ops->setisr(d,hnd,arg,s)) +#define STM32_TIM_ENABLEINT(d,s) ((d)->ops->enableint(d,s)) +#define STM32_TIM_DISABLEINT(d,s) ((d)->ops->disableint(d,s)) +#define STM32_TIM_ACKINT(d,s) ((d)->ops->ackint(d,s)) +#define STM32_TIM_CHECKINT(d,s) ((d)->ops->checkint(d,s)) +#define STM32_TIM_ENABLE(d) ((d)->ops->enable(d)) +#define STM32_TIM_DISABLE(d) ((d)->ops->disable(d)) + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/* TIM Device Structure */ + +struct stm32_tim_dev_s +{ + struct stm32_tim_ops_s *ops; +}; + +/* TIM Modes of Operation */ + +typedef enum +{ + STM32_TIM_MODE_UNUSED = -1, + + /* One of the following */ + + STM32_TIM_MODE_MASK = 0x0310, + STM32_TIM_MODE_DISABLED = 0x0000, + STM32_TIM_MODE_UP = 0x0100, + STM32_TIM_MODE_DOWN = 0x0110, + STM32_TIM_MODE_UPDOWN = 0x0200, + STM32_TIM_MODE_PULSE = 0x0300, + + /* One of the following */ + + STM32_TIM_MODE_CK_INT = 0x0000, + + /* STM32_TIM_MODE_CK_INT_TRIG = 0x0400, */ + + /* STM32_TIM_MODE_CK_EXT = 0x0800, */ + + /* STM32_TIM_MODE_CK_EXT_TRIG = 0x0C00, */ + + /* Clock sources, OR'ed with CK_EXT */ + + /* STM32_TIM_MODE_CK_CHINVALID = 0x0000, */ + + /* STM32_TIM_MODE_CK_CH1 = 0x0001, */ + + /* STM32_TIM_MODE_CK_CH2 = 0x0002, */ + + /* STM32_TIM_MODE_CK_CH3 = 0x0003, */ + + /* STM32_TIM_MODE_CK_CH4 = 0x0004 */ + + /* Todo: external trigger block */ +} stm32_tim_mode_t; + +/* TIM Channel Modes */ + +typedef enum +{ + STM32_TIM_CH_DISABLED = 0x00, + + /* Common configuration */ + + STM32_TIM_CH_POLARITY_POS = 0x00, + STM32_TIM_CH_POLARITY_NEG = 0x01, + + /* MODES: */ + + STM32_TIM_CH_MODE_MASK = 0x06, + + /* Output Compare Modes */ + + STM32_TIM_CH_OUTPWM = 0x04, /* Enable standard PWM mode, active high when counter < compare */ + + /* STM32_TIM_CH_OUTCOMPARE = 0x06, */ + + /* TODO other modes ... as PWM capture, ENCODER and Hall Sensor */ + + /* STM32_TIM_CH_INCAPTURE = 0x10, */ + + /* STM32_TIM_CH_INPWM = 0x20 */ + + /* STM32_TIM_CH_DRIVE_OC -- open collector mode */ +} stm32_tim_channel_t; + +/* TIM Operations */ + +struct stm32_tim_ops_s +{ + /* Basic Timers */ + + void (*enable)(struct stm32_tim_dev_s *dev); + void (*disable)(struct stm32_tim_dev_s *dev); + int (*setmode)(struct stm32_tim_dev_s *dev, stm32_tim_mode_t mode); + int (*setclock)(struct stm32_tim_dev_s *dev, uint32_t freq); + void (*setperiod)(struct stm32_tim_dev_s *dev, uint32_t period); + uint32_t (*getcounter)(struct stm32_tim_dev_s *dev); + void (*setcounter)(struct stm32_tim_dev_s *dev, uint32_t count); + + /* General and Advanced Timers Adds */ + + int (*getwidth)(struct stm32_tim_dev_s *dev); + int (*setchannel)(struct stm32_tim_dev_s *dev, uint8_t channel, + stm32_tim_channel_t mode); + int (*setcompare)(struct stm32_tim_dev_s *dev, uint8_t channel, + uint32_t compare); + int (*getcapture)(struct stm32_tim_dev_s *dev, uint8_t channel); + + /* Timer interrupts */ + + int (*setisr)(struct stm32_tim_dev_s *dev, + xcpt_t handler, void * arg, int source); + void (*enableint)(struct stm32_tim_dev_s *dev, int source); + void (*disableint)(struct stm32_tim_dev_s *dev, int source); + void (*ackint)(struct stm32_tim_dev_s *dev, int source); + int (*checkint)(struct stm32_tim_dev_s *dev, int source); +}; + +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ + +/* Power-up timer and get its structure */ + +struct stm32_tim_dev_s *stm32_tim_init(int timer); + +/* Power-down timer, mark it as unused */ + +int stm32_tim_deinit(struct stm32_tim_dev_s *dev); + +/**************************************************************************** + * Name: stm32_timer_initialize + * + * Description: + * Bind the configuration timer to a timer lower half instance and + * register the timer drivers at 'devpath' + * + * Input Parameters: + * devpath - The full path to the timer device. + * This should be of the form /dev/timer0 + * timer - the timer number. + * + * Returned Value: + * Zero (OK) is returned on success; A negated errno value is returned + * to indicate the nature of any failure. + * + ****************************************************************************/ + +#ifdef CONFIG_TIMER +int stm32_timer_initialize(const char *devpath, int timer); +#endif + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_TIM_V1V2V3_H */ diff --git a/arch/arm/src/common/stm32/stm32_tim_m3m4_v1v2v3_lowerhalf.c b/arch/arm/src/common/stm32/stm32_tim_m3m4_v1v2v3_lowerhalf.c new file mode 100644 index 0000000000000..25d5b63192639 --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_tim_m3m4_v1v2v3_lowerhalf.c @@ -0,0 +1,588 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_tim_m3m4_v1v2v3_lowerhalf.c + * + * SPDX-License-Identifier: BSD-3-Clause + * SPDX-FileCopyrightText: 2015 Wail Khemir. All rights reserved. + * SPDX-FileCopyrightText: 2015 Omni Hoverboards Inc. All rights reserved. + * SPDX-FileContributor: Wail Khemir + * SPDX-FileContributor: Paul Alexander Patience + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include +#include +#include + +#include +#include + +#include + +#include "stm32_tim.h" + +#if defined(CONFIG_TIMER) && \ + (defined(CONFIG_STM32_TIM1) || defined(CONFIG_STM32_TIM2) || \ + defined(CONFIG_STM32_TIM3) || defined(CONFIG_STM32_TIM4) || \ + defined(CONFIG_STM32_TIM5) || defined(CONFIG_STM32_TIM6) || \ + defined(CONFIG_STM32_TIM7) || defined(CONFIG_STM32_TIM8) || \ + defined(CONFIG_STM32_TIM9) || defined(CONFIG_STM32_TIM10) || \ + defined(CONFIG_STM32_TIM11) || defined(CONFIG_STM32_TIM12) || \ + defined(CONFIG_STM32_TIM13) || defined(CONFIG_STM32_TIM14)) + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define STM32_TIM1_RES 16 +#if defined(CONFIG_STM32_STM32L15XX) || defined(CONFIG_STM32_STM32F10XX) +# define STM32_TIM2_RES 16 +#else +# define STM32_TIM2_RES 32 +#endif +#define STM32_TIM3_RES 16 +#define STM32_TIM4_RES 16 +#if defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F30XX) +# define STM32_TIM5_RES 16 +#else +# define STM32_TIM5_RES 32 +#endif +#define STM32_TIM6_RES 16 +#define STM32_TIM7_RES 16 +#define STM32_TIM8_RES 16 +#define STM32_TIM9_RES 16 +#define STM32_TIM10_RES 16 +#define STM32_TIM11_RES 16 +#define STM32_TIM12_RES 16 +#define STM32_TIM13_RES 16 +#define STM32_TIM14_RES 16 + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/* This structure provides the private representation of the "lower-half" + * driver state structure. This structure must be cast-compatible with the + * timer_lowerhalf_s structure. + */ + +struct stm32_lowerhalf_s +{ + const struct timer_ops_s *ops; /* Lower half operations */ + struct stm32_tim_dev_s *tim; /* stm32 timer driver */ + tccb_t callback; /* Current user interrupt callback */ + void *arg; /* Argument passed to upper half callback */ + bool started; /* True: Timer has been started */ + const uint8_t resolution; /* Number of bits in the timer (16 or 32 bits) */ +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +static int stm32_timer_handler(int irq, void * context, void * arg); + +/* "Lower half" driver methods **********************************************/ + +static int stm32_start(struct timer_lowerhalf_s *lower); +static int stm32_stop(struct timer_lowerhalf_s *lower); +static int stm32_settimeout(struct timer_lowerhalf_s *lower, + uint32_t timeout); +static void stm32_setcallback(struct timer_lowerhalf_s *lower, + tccb_t callback, void *arg); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* "Lower half" driver methods */ + +static const struct timer_ops_s g_timer_ops = +{ + .start = stm32_start, + .stop = stm32_stop, + .getstatus = NULL, + .settimeout = stm32_settimeout, + .setcallback = stm32_setcallback, + .ioctl = NULL, +}; + +#ifdef CONFIG_STM32_TIM1 +static struct stm32_lowerhalf_s g_tim1_lowerhalf = +{ + .ops = &g_timer_ops, + .resolution = STM32_TIM1_RES, +}; +#endif + +#ifdef CONFIG_STM32_TIM2 +static struct stm32_lowerhalf_s g_tim2_lowerhalf = +{ + .ops = &g_timer_ops, + .resolution = STM32_TIM2_RES, +}; +#endif + +#ifdef CONFIG_STM32_TIM3 +static struct stm32_lowerhalf_s g_tim3_lowerhalf = +{ + .ops = &g_timer_ops, + .resolution = STM32_TIM3_RES, +}; +#endif + +#ifdef CONFIG_STM32_TIM4 +static struct stm32_lowerhalf_s g_tim4_lowerhalf = +{ + .ops = &g_timer_ops, + .resolution = STM32_TIM4_RES, +}; +#endif + +#ifdef CONFIG_STM32_TIM5 +static struct stm32_lowerhalf_s g_tim5_lowerhalf = +{ + .ops = &g_timer_ops, + .resolution = STM32_TIM5_RES, +}; +#endif + +#ifdef CONFIG_STM32_TIM6 +static struct stm32_lowerhalf_s g_tim6_lowerhalf = +{ + .ops = &g_timer_ops, + .resolution = STM32_TIM6_RES, +}; +#endif + +#ifdef CONFIG_STM32_TIM7 +static struct stm32_lowerhalf_s g_tim7_lowerhalf = +{ + .ops = &g_timer_ops, + .resolution = STM32_TIM7_RES, +}; +#endif + +#ifdef CONFIG_STM32_TIM8 +static struct stm32_lowerhalf_s g_tim8_lowerhalf = +{ + .ops = &g_timer_ops, + .resolution = STM32_TIM8_RES, +}; +#endif + +#ifdef CONFIG_STM32_TIM9 +static struct stm32_lowerhalf_s g_tim9_lowerhalf = +{ + .ops = &g_timer_ops, + .resolution = STM32_TIM9_RES, +}; +#endif + +#ifdef CONFIG_STM32_TIM10 +static struct stm32_lowerhalf_s g_tim10_lowerhalf = +{ + .ops = &g_timer_ops, + .resolution = STM32_TIM10_RES, +}; +#endif + +#ifdef CONFIG_STM32_TIM11 +static struct stm32_lowerhalf_s g_tim11_lowerhalf = +{ + .ops = &g_timer_ops, + .resolution = STM32_TIM11_RES, +}; +#endif + +#ifdef CONFIG_STM32_TIM12 +static struct stm32_lowerhalf_s g_tim12_lowerhalf = +{ + .ops = &g_timer_ops, + .resolution = STM32_TIM12_RES, +}; +#endif + +#ifdef CONFIG_STM32_TIM13 +static struct stm32_lowerhalf_s g_tim13_lowerhalf = +{ + .ops = &g_timer_ops, + .resolution = STM32_TIM13_RES, +}; +#endif + +#ifdef CONFIG_STM32_TIM14 +static struct stm32_lowerhalf_s g_tim14_lowerhalf = +{ + .ops = &g_timer_ops, + .resolution = STM32_TIM14_RES, +}; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_timer_handler + * + * Description: + * timer interrupt handler + * + * Input Parameters: + * + * Returned Value: + * + ****************************************************************************/ + +static int stm32_timer_handler(int irq, void * context, void * arg) +{ + struct stm32_lowerhalf_s *lower = (struct stm32_lowerhalf_s *) arg; + uint32_t next_interval_us = 0; + + STM32_TIM_ACKINT(lower->tim, ATIM_DIER_UIE); + + if (lower->callback(&next_interval_us, lower->arg)) + { + if (next_interval_us > 0) + { + STM32_TIM_SETPERIOD(lower->tim, next_interval_us); + } + } + else + { + stm32_stop((struct timer_lowerhalf_s *)lower); + } + + return OK; +} + +/**************************************************************************** + * Name: stm32_start + * + * Description: + * Start the timer, resetting the time to the current timeout, + * + * Input Parameters: + * lower - A pointer the publicly visible representation of the + * "lower-half" driver state structure. + * + * Returned Value: + * Zero on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int stm32_start(struct timer_lowerhalf_s *lower) +{ + struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; + + if (!priv->started) + { + STM32_TIM_SETMODE(priv->tim, STM32_TIM_MODE_UP); + + if (priv->callback != NULL) + { + STM32_TIM_SETISR(priv->tim, stm32_timer_handler, priv, 0); + STM32_TIM_ENABLEINT(priv->tim, ATIM_DIER_UIE); + } + + priv->started = true; + return OK; + } + + /* Return EBUSY to indicate that the timer was already running */ + + return -EBUSY; +} + +/**************************************************************************** + * Name: stm32_stop + * + * Description: + * Stop the timer + * + * Input Parameters: + * lower - A pointer the publicly visible representation of the + * "lower-half" driver state structure. + * + * Returned Value: + * Zero on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int stm32_stop(struct timer_lowerhalf_s *lower) +{ + struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; + + if (priv->started) + { + STM32_TIM_SETMODE(priv->tim, STM32_TIM_MODE_DISABLED); + STM32_TIM_DISABLEINT(priv->tim, ATIM_DIER_UIE); + STM32_TIM_SETISR(priv->tim, NULL, NULL, 0); + priv->started = false; + return OK; + } + + /* Return ENODEV to indicate that the timer was not running */ + + return -ENODEV; +} + +/**************************************************************************** + * Name: stm32_settimeout + * + * Description: + * Set a new timeout value (and reset the timer) + * + * Input Parameters: + * lower - A pointer the publicly visible representation of the + * "lower-half" driver state structure. + * timeout - The new timeout value in microseconds. + * + * Returned Value: + * Zero on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int stm32_settimeout(struct timer_lowerhalf_s *lower, + uint32_t timeout) +{ + struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; + uint64_t maxtimeout; + + if (priv->started) + { + return -EPERM; + } + + maxtimeout = (1 << priv->resolution) - 1; + if (timeout > maxtimeout) + { + uint64_t freq = (maxtimeout * 1000000) / timeout; + STM32_TIM_SETCLOCK(priv->tim, freq); + STM32_TIM_SETPERIOD(priv->tim, maxtimeout); + } + else + { + STM32_TIM_SETCLOCK(priv->tim, 1000000); + STM32_TIM_SETPERIOD(priv->tim, timeout); + } + + return OK; +} + +/**************************************************************************** + * Name: stm32_setcallback + * + * Description: + * Call this user provided timeout callback. + * + * Input Parameters: + * lower - A pointer the publicly visible representation of the + * "lower-half" driver state structure. + * callback - The new timer expiration function pointer. If this + * function pointer is NULL, then the reset-on-expiration + * behavior is restored, + * arg - Argument that will be provided in the callback + * + * Returned Value: + * The previous timer expiration function pointer or NULL is there was + * no previous function pointer. + * + ****************************************************************************/ + +static void stm32_setcallback(struct timer_lowerhalf_s *lower, + tccb_t callback, void *arg) +{ + struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; + + irqstate_t flags = enter_critical_section(); + + /* Save the new callback */ + + priv->callback = callback; + priv->arg = arg; + + if (callback != NULL && priv->started) + { + STM32_TIM_SETISR(priv->tim, stm32_timer_handler, priv, 0); + STM32_TIM_ENABLEINT(priv->tim, ATIM_DIER_UIE); + } + else + { + STM32_TIM_DISABLEINT(priv->tim, ATIM_DIER_UIE); + STM32_TIM_SETISR(priv->tim, NULL, NULL, 0); + } + + leave_critical_section(flags); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_timer_initialize + * + * Description: + * Bind the configuration timer to a timer lower half instance and + * register the timer drivers at 'devpath' + * + * Input Parameters: + * devpath - The full path to the timer device. This should be of the + * form /dev/timer0 + * timer - the timer's number. + * + * Returned Value: + * Zero (OK) is returned on success; A negated errno value is returned + * to indicate the nature of any failure. + * + ****************************************************************************/ + +int stm32_timer_initialize(const char *devpath, int timer) +{ + struct stm32_lowerhalf_s *lower; + + switch (timer) + { +#ifdef CONFIG_STM32_TIM1 + case 1: + lower = &g_tim1_lowerhalf; + break; +#endif +#ifdef CONFIG_STM32_TIM2 + case 2: + lower = &g_tim2_lowerhalf; + break; +#endif +#ifdef CONFIG_STM32_TIM3 + case 3: + lower = &g_tim3_lowerhalf; + break; +#endif +#ifdef CONFIG_STM32_TIM4 + case 4: + lower = &g_tim4_lowerhalf; + break; +#endif +#ifdef CONFIG_STM32_TIM5 + case 5: + lower = &g_tim5_lowerhalf; + break; +#endif +#ifdef CONFIG_STM32_TIM6 + case 6: + lower = &g_tim6_lowerhalf; + break; +#endif +#ifdef CONFIG_STM32_TIM7 + case 7: + lower = &g_tim7_lowerhalf; + break; +#endif +#ifdef CONFIG_STM32_TIM8 + case 8: + lower = &g_tim8_lowerhalf; + break; +#endif +#ifdef CONFIG_STM32_TIM9 + case 9: + lower = &g_tim9_lowerhalf; + break; +#endif +#ifdef CONFIG_STM32_TIM10 + case 10: + lower = &g_tim10_lowerhalf; + break; +#endif +#ifdef CONFIG_STM32_TIM11 + case 11: + lower = &g_tim11_lowerhalf; + break; +#endif +#ifdef CONFIG_STM32_TIM12 + case 12: + lower = &g_tim12_lowerhalf; + break; +#endif +#ifdef CONFIG_STM32_TIM13 + case 13: + lower = &g_tim13_lowerhalf; + break; +#endif +#ifdef CONFIG_STM32_TIM14 + case 14: + lower = &g_tim14_lowerhalf; + break; +#endif + default: + return -ENODEV; + } + + /* Initialize the elements of lower half state structure */ + + lower->started = false; + lower->callback = NULL; + lower->tim = stm32_tim_init(timer); + + if (lower->tim == NULL) + { + return -EINVAL; + } + + /* Register the timer driver as /dev/timerX. The returned value from + * timer_register is a handle that could be used with timer_unregister(). + * REVISIT: The returned handle is discard here. + */ + + void *drvr = timer_register(devpath, + (struct timer_lowerhalf_s *)lower); + if (drvr == NULL) + { + /* The actual cause of the failure may have been a failure to allocate + * perhaps a failure to register the timer driver (such as if the + * 'depath' were not unique). We know here but we return EEXIST to + * indicate the failure (implying the non-unique devpath). + */ + + return -EEXIST; + } + + return OK; +} + +#endif /* CONFIG_TIMER */ diff --git a/arch/arm/src/common/stm32/stm32_timerisr_armv6m.c b/arch/arm/src/common/stm32/stm32_timerisr_armv6m.c new file mode 100644 index 0000000000000..a3136b8657912 --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_timerisr_armv6m.c @@ -0,0 +1,152 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_timerisr_armv6m.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include +#include + +#include "nvic.h" +#include "clock/clock.h" +#include "arm_internal.h" +#include "chip.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* "The CLKSOURCE bit in SysTick Control and Status register selects either + * the core clock (when CLKSOURCE = 1) or a divide-by-16 of the core clock + * (when CLKSOURCE = 0). ..." + */ + +#if defined(CONFIG_STM32_SYSTICK_CORECLK) +# define SYSTICK_CLOCK STM32_SYSCLK_FREQUENCY /* Core clock */ +#elif defined(CONFIG_STM32_SYSTICK_CORECLK_DIV16) +# define SYSTICK_CLOCK (STM32_SYSCLK_FREQUENCY / 16) /* Core clock divided by 16 */ +#endif + +/* The desired timer interrupt frequency is provided by the definition + * CLK_TCK (see include/time.h). CLK_TCK defines the desired number of + * system clock ticks per second. That value is a user configurable setting + * that defaults to 100 (100 ticks per second = 10 MS interval). + * + * Then, for example, if the external high speed crystal is the SysTick + * clock source and BOARD_XTALHI_FREQUENCY is 12MHz and CLK_TCK is 100, then + * the reload value would be: + * + * SYSTICK_RELOAD = (12,000,000 / 100) - 1 + * = 119,999 + * = 0x1d4bf + * + * Which fits within the maximum 24-bit reload value. + */ + +#define SYSTICK_RELOAD ((SYSTICK_CLOCK / CLK_TCK) - 1) + +/* The size of the reload field is 24 bits. Verify that the reload value + * will fit in the reload register. + */ + +#if SYSTICK_RELOAD > 0x00ffffff +# error SYSTICK_RELOAD exceeds the range of the RELOAD register +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Function: stm32_timerisr + * + * Description: + * The timer ISR will perform a variety of services for various portions + * of the systems. + * + ****************************************************************************/ + +static int stm32_timerisr(int irq, uint32_t *regs, void *arg) +{ + /* Process timer interrupt */ + + nxsched_process_timer(); + return 0; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Function: up_timer_initialize + * + * Description: + * This function is called during start-up to initialize + * the timer interrupt. + * + ****************************************************************************/ + +void up_timer_initialize(void) +{ + uint32_t regval; + + /* Set the SysTick interrupt to the default priority */ + + regval = getreg32(ARMV6M_SYSCON_SHPR3); + regval &= ~SYSCON_SHPR3_PRI_15_MASK; + regval |= (NVIC_SYSH_PRIORITY_DEFAULT << SYSCON_SHPR3_PRI_15_SHIFT); + putreg32(regval, ARMV6M_SYSCON_SHPR3); + + /* Configure SysTick to interrupt at the requested rate */ + + putreg32(SYSTICK_RELOAD, ARMV6M_SYSTICK_RVR); + + /* Attach the timer interrupt vector */ + + irq_attach(STM32_IRQ_SYSTICK, (xcpt_t)stm32_timerisr, NULL); + + /* Enable SysTick interrupts. "The CLKSOURCE bit in SysTick Control and + * Status register selects either the core clock (when CLKSOURCE = 1) or + * a divide-by-16 of the core clock (when CLKSOURCE = 0). ..." + */ + +#ifdef CONFIG_STM32_SYSTICK_CORECLK + putreg32((SYSTICK_CSR_CLKSOURCE | + SYSTICK_CSR_TICKINT | + SYSTICK_CSR_ENABLE), + ARMV6M_SYSTICK_CSR); +#else + putreg32((SYSTICK_CSR_TICKINT | SYSTICK_CSR_ENABLE), ARMV6M_SYSTICK_CSR); +#endif + + /* And enable the timer interrupt */ + + up_enable_irq(STM32_IRQ_SYSTICK); +} diff --git a/arch/arm/src/common/stm32/stm32_timerisr_armv7m.c b/arch/arm/src/common/stm32/stm32_timerisr_armv7m.c new file mode 100644 index 0000000000000..b7f8e713252f6 --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_timerisr_armv7m.c @@ -0,0 +1,196 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_timerisr_armv7m.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include +#include +#include + +#include "nvic.h" +#include "clock/clock.h" +#include "arm_internal.h" +#include "systick.h" + +#include "chip.h" +#include "stm32.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* The desired timer interrupt frequency is provided by the definition + * CLK_TCK (see include/time.h). CLK_TCK defines the desired number of + * system clock ticks per second. That value is a user configurable setting + * that defaults to 100 (100 ticks per second = 10 MS interval). + * + * The RCC feeds the Cortex System Timer (SysTick) with the AHB clock (HCLK) + * divided by 8. The SysTick can work either with this clock or with the + * Cortex clock (HCLK), configurable in the SysTick Control and Status + * register. + */ + +#undef CONFIG_STM32_SYSTICK_HCLKd8 /* Power up default is HCLK, not HCLK/8 */ + /* And I don't know now to re-configure it yet */ + +#ifdef CONFIG_STM32_SYSTICK_HCLKd8 +# define SYSTICK_CLOCK (STM32_HCLK_FREQUENCY / 8) +#else +# define SYSTICK_CLOCK (STM32_HCLK_FREQUENCY) +#endif + +#define SYSTICK_RELOAD ((SYSTICK_CLOCK / CLK_TCK) - 1) + +/* The size of the reload field is 24 bits. Verify that the reload value + * will fit in the reload register. + */ + +#define SYSTICK_MAX 0x00ffffff +#if SYSTICK_RELOAD > SYSTICK_MAX +# error SYSTICK_RELOAD exceeds the range of the RELOAD register +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Function: stm32_timerisr + * + * Description: + * The timer ISR will perform a variety of services for various portions + * of the systems. + * + ****************************************************************************/ + +#if !defined(CONFIG_ARMV7M_SYSTICK) && !defined(CONFIG_TIMER_ARCH) +static int stm32_timerisr(int irq, uint32_t *regs, void *arg) +{ + /* Process timer interrupt */ + + nxsched_process_timer(); + return 0; +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Function: up_adjtime + * + * Description: + * Adjusts timer period. This call is used when adjusting timer period as + * defined in adjtime() function. + * + * Input Parameters: + * ppb - Adjustment in parts per billion (nanoseconds per second). + * Zero is default rate, positive value makes clock run faster + * and negative value slower. + * + * Assumptions: + * Called from within critical section or interrupt context. + ****************************************************************************/ + +#ifdef CONFIG_CLOCK_ADJTIME +void up_adjtime(long ppb) +{ + uint32_t period = SYSTICK_RELOAD; + + if (ppb != 0) + { + period -= (long long)ppb * SYSTICK_RELOAD / 1000000000; + } + + /* Check whether period is at maximum value. */ + + if (period > SYSTICK_MAX) + { + period = SYSTICK_MAX; + } + + putreg32(period, NVIC_SYSTICK_RELOAD); +} +#endif + +/**************************************************************************** + * Function: up_timer_initialize + * + * Description: + * This function is called during start-up to initialize + * the timer interrupt. + * + ****************************************************************************/ + +void up_timer_initialize(void) +{ + uint32_t regval; + + /* Set the SysTick interrupt to the default priority */ + + regval = getreg32(NVIC_SYSH12_15_PRIORITY); + regval &= ~NVIC_SYSH_PRIORITY_PR15_MASK; + regval |= (NVIC_SYSH_PRIORITY_DEFAULT << NVIC_SYSH_PRIORITY_PR15_SHIFT); + putreg32(regval, NVIC_SYSH12_15_PRIORITY); + + /* Make sure that the SYSTICK clock source is set correctly */ + +#if 0 /* Does not work. Comes up with HCLK source and I can't change it */ + regval = getreg32(NVIC_SYSTICK_CTRL); +#ifdef CONFIG_STM32_SYSTICK_HCLKd8 + regval &= ~NVIC_SYSTICK_CTRL_CLKSOURCE; +#else + regval |= NVIC_SYSTICK_CTRL_CLKSOURCE; +#endif + putreg32(regval, NVIC_SYSTICK_CTRL); +#endif + +#if defined(CONFIG_ARMV7M_SYSTICK) && defined(CONFIG_TIMER_ARCH) + up_timer_set_lowerhalf(systick_initialize(true, STM32_HCLK_FREQUENCY, -1)); +#else + /* Configure SysTick to interrupt at the requested rate */ + + putreg32(SYSTICK_RELOAD, NVIC_SYSTICK_RELOAD); + + /* Attach the timer interrupt vector */ + + irq_attach(STM32_IRQ_SYSTICK, (xcpt_t)stm32_timerisr, NULL); + + /* Enable SysTick interrupts */ + + putreg32((NVIC_SYSTICK_CTRL_CLKSOURCE | NVIC_SYSTICK_CTRL_TICKINT | + NVIC_SYSTICK_CTRL_ENABLE), NVIC_SYSTICK_CTRL); + + /* And enable the timer interrupt */ + + up_enable_irq(STM32_IRQ_SYSTICK); +#endif +} diff --git a/arch/arm/src/common/stm32/stm32_uart.h b/arch/arm/src/common/stm32/stm32_uart.h new file mode 100644 index 0000000000000..29de62701fe9c --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_uart.h @@ -0,0 +1,46 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_uart.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_COMPAT_STM32_UART_H +#define __ARCH_ARM_SRC_COMMON_COMPAT_STM32_UART_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#if defined(CONFIG_ARCH_ARMV6M) +# if defined(CONFIG_STM32_HAVE_IP_USART_V3) || \ + defined(CONFIG_STM32_HAVE_IP_USART_V4) +# include "stm32_uart_m0_v1.h" +# else +# error "Unsupported STM32 UART core for M0" +# endif +#elif defined(CONFIG_STM32_HAVE_IP_USART_V1) || \ + defined(CONFIG_STM32_HAVE_IP_USART_V2) || \ + defined(CONFIG_STM32_HAVE_IP_USART_V3) || \ + defined(CONFIG_STM32_HAVE_IP_USART_V4) +# include "stm32_uart_m3m4_v1v2.h" +#else +# error "Unsupported STM32 UART" +#endif + +#endif /* __ARCH_ARM_SRC_COMMON_COMPAT_STM32_UART_H */ diff --git a/arch/arm/src/common/stm32/stm32_uart_m0_v1.h b/arch/arm/src/common/stm32/stm32_uart_m0_v1.h new file mode 100644 index 0000000000000..5844f46e08413 --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_uart_m0_v1.h @@ -0,0 +1,452 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_uart_m0_v1.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_UART_M0_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_UART_M0_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "chip.h" + +#include "hardware/stm32_uart.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Make sure that we have not enabled more U[S]ARTs than are supported by the + * device. + */ + +#if STM32_NUSART < 8 || !defined(CONFIG_STM32_HAVE_USART8) +# undef CONFIG_STM32_USART8 +#endif +#if STM32_NUSART < 7 || !defined(CONFIG_STM32_HAVE_USART7) +# undef CONFIG_STM32_USART7 +#endif +#if STM32_NUSART < 6 || !defined(CONFIG_STM32_HAVE_USART6) +# undef CONFIG_STM32_USART6 +#endif +#if STM32_NUSART < 5 || !defined(CONFIG_STM32_HAVE_USART5) +# undef CONFIG_STM32_USART5 +#endif +#if STM32_NUSART < 4 || !defined(CONFIG_STM32_HAVE_USART4) +# undef CONFIG_STM32_USART4 +#endif +#if STM32_NUSART < 3 || !defined(CONFIG_STM32_HAVE_USART3) +# undef CONFIG_STM32_USART3 +#endif +#if STM32_NUSART < 2 +# undef CONFIG_STM32_USART2 +#endif +#if STM32_NUSART < 1 +# undef CONFIG_STM32_USART1 +#endif + +/* USART 3-8 are multiplexed to the same interrupt. Current interrupt + * handling logic will support only one USART in that range. That is + * not an issue for currently supported chips but could become an + * issue in the future. + */ + +#if defined(CONFIG_STM32_USART3) +# undef CONFIG_STM32_USART4 +# undef CONFIG_STM32_USART5 +# undef CONFIG_STM32_USART6 +# undef CONFIG_STM32_USART7 +# undef CONFIG_STM32_USART8 +#elif defined(CONFIG_STM32_USART4) +# undef CONFIG_STM32_USART5 +# undef CONFIG_STM32_USART6 +# undef CONFIG_STM32_USART7 +# undef CONFIG_STM32_USART8 +#elif defined(CONFIG_STM32_USART5) +# undef CONFIG_STM32_USART6 +# undef CONFIG_STM32_USART7 +# undef CONFIG_STM32_USART8 +#elif defined(CONFIG_STM32_USART6) +# undef CONFIG_STM32_USART7 +# undef CONFIG_STM32_USART8 +#elif defined(CONFIG_STM32_USART7) +# undef CONFIG_STM32_USART8 +#endif + +/* Is there a USART enabled? */ + +#if defined(CONFIG_STM32_USART1) || defined(CONFIG_STM32_USART2) || \ + defined(CONFIG_STM32_USART3) || defined(CONFIG_STM32_USART4) || \ + defined(CONFIG_STM32_USART5) || defined(CONFIG_STM32_USART6) || \ + defined(CONFIG_STM32_USART7) || defined(CONFIG_STM32_USART8) +# define HAVE_USART 1 +#endif + +/* Sanity checks */ + +#if !defined(CONFIG_STM32_USART1) +# undef CONFIG_STM32_USART1_SERIALDRIVER +# undef CONFIG_STM32_USART1_1WIREDRIVER +#endif +#if !defined(CONFIG_STM32_USART2) +# undef CONFIG_STM32_USART2_SERIALDRIVER +# undef CONFIG_STM32_USART2_1WIREDRIVER +#endif +#if !defined(CONFIG_STM32_USART3) +# undef CONFIG_STM32_USART3_SERIALDRIVER +# undef CONFIG_STM32_USART3_1WIREDRIVER +#endif +#if !defined(CONFIG_STM32_USART4) +# undef CONFIG_STM32_USART4_SERIALDRIVER +# undef CONFIG_STM32_USART4_1WIREDRIVER +#endif +#if !defined(CONFIG_STM32_USART5) +# undef CONFIG_STM32_USART5_SERIALDRIVER +# undef CONFIG_STM32_USART5_1WIREDRIVER +#endif +#if !defined(CONFIG_STM32_USART6) +# undef CONFIG_STM32_USART6_SERIALDRIVER +# undef CONFIG_STM32_USART6_1WIREDRIVER +#endif +#if !defined(CONFIG_STM32_USART7) +# undef CONFIG_STM32_USART7_SERIALDRIVER +# undef CONFIG_STM32_USART7_1WIREDRIVER +#endif +#if !defined(CONFIG_STM32_USART8) +# undef CONFIG_STM32_USART8_SERIALDRIVER +# undef CONFIG_STM32_USART8_1WIREDRIVER +#endif + +/* Check 1-Wire and U(S)ART conflicts */ + +#if defined(CONFIG_STM32_USART1_1WIREDRIVER) && defined(CONFIG_STM32_USART1_SERIALDRIVER) +# error Both CONFIG_STM32_USART1_1WIREDRIVER and CONFIG_STM32_USART1_SERIALDRIVER defined +# undef CONFIG_STM32_USART1_1WIREDRIVER +#endif +#if defined(CONFIG_STM32_USART2_1WIREDRIVER) && defined(CONFIG_STM32_USART2_SERIALDRIVER) +# error Both CONFIG_STM32_USART2_1WIREDRIVER and CONFIG_STM32_USART2_SERIALDRIVER defined +# undef CONFIG_STM32_USART2_1WIREDRIVER +#endif +#if defined(CONFIG_STM32_USART3_1WIREDRIVER) && defined(CONFIG_STM32_USART3_SERIALDRIVER) +# error Both CONFIG_STM32_USART3_1WIREDRIVER and CONFIG_STM32_USART3_SERIALDRIVER defined +# undef CONFIG_STM32_USART3_1WIREDRIVER +#endif +#if defined(CONFIG_STM32_USART4_1WIREDRIVER) && defined(CONFIG_STM32_USART4_SERIALDRIVER) +# error Both CONFIG_STM32_USART4_1WIREDRIVER and CONFIG_STM32_USART4_SERIALDRIVER defined +# undef CONFIG_STM32_USART4_1WIREDRIVER +#endif +#if defined(CONFIG_STM32_USART5_1WIREDRIVER) && defined(CONFIG_STM32_USART5_SERIALDRIVER) +# error Both CONFIG_STM32_USART5_1WIREDRIVER and CONFIG_STM32_USART5_SERIALDRIVER defined +# undef CONFIG_STM32_USART5_1WIREDRIVER +#endif +#if defined(CONFIG_STM32_USART6_1WIREDRIVER) && defined(CONFIG_STM32_USART6_SERIALDRIVER) +# error Both CONFIG_STM32_USART6_1WIREDRIVER and CONFIG_STM32_USART6_SERIALDRIVER defined +# undef CONFIG_STM32_USART6_1WIREDRIVER +#endif +#if defined(CONFIG_STM32_USART7_1WIREDRIVER) && defined(CONFIG_STM32_USART7_SERIALDRIVER) +# error Both CONFIG_STM32_USART7_1WIREDRIVER and CONFIG_STM32_USART7_SERIALDRIVER defined +# undef CONFIG_STM32_USART7_1WIREDRIVER +#endif +#if defined(CONFIG_STM32_USART8_1WIREDRIVER) && defined(CONFIG_STM32_USART8_SERIALDRIVER) +# error Both CONFIG_STM32_USART8_1WIREDRIVER and CONFIG_STM32_USART8_SERIALDRIVER defined +# undef CONFIG_STM32_USART8_1WIREDRIVER +#endif + +/* Is the serial driver enabled? */ + +#if defined(CONFIG_STM32_USART1_SERIALDRIVER) || defined(CONFIG_STM32_USART2_SERIALDRIVER) || \ + defined(CONFIG_STM32_USART3_SERIALDRIVER) || defined(CONFIG_STM32_USART4_SERIALDRIVER) || \ + defined(CONFIG_STM32_USART5_SERIALDRIVER) || defined(CONFIG_STM32_USART6_SERIALDRIVER) || \ + defined(CONFIG_STM32_USART7_SERIALDRIVER) || defined(CONFIG_STM32_USART8_SERIALDRIVER) +# define HAVE_SERIALDRIVER 1 +#endif + +/* Is the 1-Wire driver? */ + +#if defined(CONFIG_STM32_USART1_1WIREDRIVER) || defined(CONFIG_STM32_USART2_1WIREDRIVER) || \ + defined(CONFIG_STM32_USART3_1WIREDRIVER) || defined(CONFIG_STM32_USART4_1WIREDRIVER) || \ + defined(CONFIG_STM32_USART5_1WIREDRIVER) || defined(CONFIG_STM32_USART6_1WIREDRIVER) || \ + defined(CONFIG_STM32_USART7_1WIREDRIVER) || defined(CONFIG_STM32_USART8_1WIREDRIVER) +# define HAVE_1WIREDRIVER 1 +#endif + +/* Is there a serial console? */ + +#if defined(CONFIG_USART1_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART1_SERIALDRIVER) +# undef CONFIG_USART2_SERIAL_CONSOLE +# undef CONFIG_USART3_SERIAL_CONSOLE +# undef CONFIG_USART4_SERIAL_CONSOLE +# undef CONFIG_USART5_SERIAL_CONSOLE +# undef CONFIG_USART6_SERIAL_CONSOLE +# undef CONFIG_USART7_SERIAL_CONSOLE +# undef CONFIG_USART8_SERIAL_CONSOLE +# define CONSOLE_USART 1 +# define HAVE_CONSOLE 1 +#elif defined(CONFIG_USART2_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART2_SERIALDRIVER) +# undef CONFIG_USART1_SERIAL_CONSOLE +# undef CONFIG_USART3_SERIAL_CONSOLE +# undef CONFIG_USART4_SERIAL_CONSOLE +# undef CONFIG_USART5_SERIAL_CONSOLE +# undef CONFIG_USART6_SERIAL_CONSOLE +# undef CONFIG_USART7_SERIAL_CONSOLE +# undef CONFIG_USART8_SERIAL_CONSOLE +# define CONSOLE_USART 2 +# define HAVE_CONSOLE 1 +#elif defined(CONFIG_USART3_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART3_SERIALDRIVER) +# undef CONFIG_USART1_SERIAL_CONSOLE +# undef CONFIG_USART2_SERIAL_CONSOLE +# undef CONFIG_USART4_SERIAL_CONSOLE +# undef CONFIG_USART5_SERIAL_CONSOLE +# undef CONFIG_USART6_SERIAL_CONSOLE +# undef CONFIG_USART7_SERIAL_CONSOLE +# undef CONFIG_USART8_SERIAL_CONSOLE +# define CONSOLE_USART 3 +# define HAVE_CONSOLE 1 +#elif defined(CONFIG_USART4_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART4_SERIALDRIVER) +# undef CONFIG_USART1_SERIAL_CONSOLE +# undef CONFIG_USART2_SERIAL_CONSOLE +# undef CONFIG_USART3_SERIAL_CONSOLE +# undef CONFIG_USART5_SERIAL_CONSOLE +# undef CONFIG_USART6_SERIAL_CONSOLE +# undef CONFIG_USART7_SERIAL_CONSOLE +# undef CONFIG_USART8_SERIAL_CONSOLE +# define CONSOLE_USART 4 +# define HAVE_CONSOLE 1 +#elif defined(CONFIG_USART5_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART5_SERIALDRIVER) +# undef CONFIG_USART1_SERIAL_CONSOLE +# undef CONFIG_USART2_SERIAL_CONSOLE +# undef CONFIG_USART3_SERIAL_CONSOLE +# undef CONFIG_USART4_SERIAL_CONSOLE +# undef CONFIG_USART6_SERIAL_CONSOLE +# undef CONFIG_USART7_SERIAL_CONSOLE +# undef CONFIG_USART8_SERIAL_CONSOLE +# define CONSOLE_USART 5 +# define HAVE_CONSOLE 1 +#elif defined(CONFIG_USART6_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART6_SERIALDRIVER) +# undef CONFIG_USART1_SERIAL_CONSOLE +# undef CONFIG_USART2_SERIAL_CONSOLE +# undef CONFIG_USART3_SERIAL_CONSOLE +# undef CONFIG_USART4_SERIAL_CONSOLE +# undef CONFIG_USART5_SERIAL_CONSOLE +# undef CONFIG_USART7_SERIAL_CONSOLE +# undef CONFIG_USART8_SERIAL_CONSOLE +# define CONSOLE_USART 6 +# define HAVE_CONSOLE 1 +#elif defined(CONFIG_USART7_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART7_SERIALDRIVER) +# undef CONFIG_USART1_SERIAL_CONSOLE +# undef CONFIG_USART2_SERIAL_CONSOLE +# undef CONFIG_USART3_SERIAL_CONSOLE +# undef CONFIG_USART4_SERIAL_CONSOLE +# undef CONFIG_USART5_SERIAL_CONSOLE +# undef CONFIG_USART6_SERIAL_CONSOLE +# undef CONFIG_USART5_SERIAL_CONSOLE +# undef CONFIG_USART8_SERIAL_CONSOLE +# define CONSOLE_USART 7 +# define HAVE_CONSOLE 1 +#elif defined(CONFIG_USART8_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART8_SERIALDRIVER) +# undef CONFIG_USART1_SERIAL_CONSOLE +# undef CONFIG_USART2_SERIAL_CONSOLE +# undef CONFIG_USART3_SERIAL_CONSOLE +# undef CONFIG_USART4_SERIAL_CONSOLE +# undef CONFIG_USART6_SERIAL_CONSOLE +# undef CONFIG_USART6_SERIAL_CONSOLE +# undef CONFIG_USART7_SERIAL_CONSOLE +# define CONSOLE_USART 8 +# define HAVE_CONSOLE 1 +#else +# undef CONFIG_USART1_SERIAL_CONSOLE +# undef CONFIG_USART2_SERIAL_CONSOLE +# undef CONFIG_USART3_SERIAL_CONSOLE +# undef CONFIG_USART4_SERIAL_CONSOLE +# undef CONFIG_USART5_SERIAL_CONSOLE +# undef CONFIG_USART6_SERIAL_CONSOLE +# undef CONFIG_USART7_SERIAL_CONSOLE +# undef CONFIG_USART8_SERIAL_CONSOLE +# define CONSOLE_USART 0 +# undef HAVE_CONSOLE +#endif + +/* DMA support is only provided if CONFIG_ARCH_DMA is in the NuttX + * configuration + */ + +#if !defined(HAVE_SERIALDRIVER) || !defined(CONFIG_ARCH_DMA) +# undef CONFIG_USART1_RXDMA +# undef CONFIG_USART2_RXDMA +# undef CONFIG_USART3_RXDMA +# undef CONFIG_USART4_RXDMA +# undef CONFIG_USART5_RXDMA +# undef CONFIG_USART6_RXDMA +# undef CONFIG_USART7_RXDMA +# undef CONFIG_USART8_RXDMA +#endif + +/* Disable the DMA configuration on all unused USARTs */ + +#ifndef CONFIG_STM32_USART1_SERIALDRIVER +# undef CONFIG_USART1_RXDMA +#endif + +#ifndef CONFIG_STM32_USART2_SERIALDRIVER +# undef CONFIG_USART2_RXDMA +#endif + +#ifndef CONFIG_STM32_USART3_SERIALDRIVER +# undef CONFIG_USART3_RXDMA +#endif + +#ifndef CONFIG_STM32_USART4_SERIALDRIVER +# undef CONFIG_USART4_RXDMA +#endif + +#ifndef CONFIG_STM32_USART5_SERIALDRIVER +# undef CONFIG_USART5_RXDMA +#endif + +#ifndef CONFIG_STM32_USART6_SERIALDRIVER +# undef CONFIG_USART6_RXDMA +#endif + +#ifndef CONFIG_STM32_USART7_SERIALDRIVER +# undef CONFIG_USART7_RXDMA +#endif + +#ifndef CONFIG_STM32_USART8_SERIALDRIVER +# undef CONFIG_USART8_RXDMA +#endif + +/* Is DMA available on any (enabled) USART? */ + +#undef SERIAL_HAVE_RXDMA +#if defined(CONFIG_USART1_RXDMA) || defined(CONFIG_USART2_RXDMA) || \ + defined(CONFIG_USART3_RXDMA) || defined(CONFIG_USART4_RXDMA) || \ + defined(CONFIG_USART5_RXDMA) || defined(CONFIG_USART6_RXDMA) || \ + defined(CONFIG_USART7_RXDMA) || defined(CONFIG_USART8_RXDMA) +# define SERIAL_HAVE_RXDMA 1 +#endif + +/* Is DMA used on the console USART? */ + +#undef SERIAL_HAVE_CONSOLE_DMA +#if defined(CONFIG_USART1_SERIAL_CONSOLE) && defined(CONFIG_USART1_RXDMA) +# define SERIAL_HAVE_CONSOLE_DMA 1 +#elif defined(CONFIG_USART2_SERIAL_CONSOLE) && defined(CONFIG_USART2_RXDMA) +# define SERIAL_HAVE_CONSOLE_DMA 1 +#elif defined(CONFIG_USART3_SERIAL_CONSOLE) && defined(CONFIG_USART3_RXDMA) +# define SERIAL_HAVE_CONSOLE_DMA 1 +#elif defined(CONFIG_USART4_SERIAL_CONSOLE) && defined(CONFIG_USART4_RXDMA) +# define SERIAL_HAVE_CONSOLE_DMA 1 +#elif defined(CONFIG_USART5_SERIAL_CONSOLE) && defined(CONFIG_USART5_RXDMA) +# define SERIAL_HAVE_CONSOLE_DMA 1 +#elif defined(CONFIG_USART6_SERIAL_CONSOLE) && defined(CONFIG_USART6_RXDMA) +# define SERIAL_HAVE_CONSOLE_DMA 1 +#elif defined(CONFIG_USART7_SERIAL_CONSOLE) && defined(CONFIG_USART7_RXDMA) +# define SERIAL_HAVE_CONSOLE_DMA 1 +#elif defined(CONFIG_USART8_SERIAL_CONSOLE) && defined(CONFIG_USART8_RXDMA) +# define SERIAL_HAVE_CONSOLE_DMA 1 +#endif + +/* Is DMA used on all (enabled) USARTs */ + +#define SERIAL_HAVE_ONLY_DMA 1 +#if defined(CONFIG_STM32_USART1_SERIALDRIVER) && !defined(CONFIG_USART1_RXDMA) +# undef SERIAL_HAVE_ONLY_DMA +#elif defined(CONFIG_STM32_USART2_SERIALDRIVER) && !defined(CONFIG_USART2_RXDMA) +# undef SERIAL_HAVE_ONLY_DMA +#elif defined(CONFIG_STM32_USART3_SERIALDRIVER) && !defined(CONFIG_USART3_RXDMA) +# undef SERIAL_HAVE_ONLY_DMA +#elif defined(CONFIG_STM32_USART4_SERIALDRIVER) && !defined(CONFIG_USART4_RXDMA) +# undef SERIAL_HAVE_ONLY_DMA +#elif defined(CONFIG_STM32_USART5_SERIALDRIVER) && !defined(CONFIG_USART5_RXDMA) +# undef SERIAL_HAVE_ONLY_DMA +#elif defined(CONFIG_STM32_USART6_SERIALDRIVER) && !defined(CONFIG_USART6_RXDMA) +# undef SERIAL_HAVE_ONLY_DMA +#elif defined(CONFIG_STM32_USART7_SERIALDRIVER) && !defined(CONFIG_USART7_RXDMA) +# undef SERIAL_HAVE_ONLY_DMA +#elif defined(CONFIG_STM32_USART8_SERIALDRIVER) && !defined(CONFIG_USART8_RXDMA) +# undef SERIAL_HAVE_ONLY_DMA +#endif + +/* Is RS-485 used? */ + +#if defined(CONFIG_USART1_RS485) || defined(CONFIG_USART2_RS485) || \ + defined(CONFIG_USART3_RS485) || defined(CONFIG_USART4_RS485) || \ + defined(CONFIG_USART5_RS485) || defined(CONFIG_USART6_RS485) || \ + defined(CONFIG_USART7_RS485) || defined(CONFIG_USART8_RS485) +# define HAVE_RS485 1 +#endif + +#ifdef HAVE_RS485 +# define USART_CR1_USED_INTS (USART_CR1_RXNEIE | USART_CR1_TXEIE | USART_CR1_PEIE | USART_CR1_TCIE) +#else +# define USART_CR1_USED_INTS (USART_CR1_RXNEIE | USART_CR1_TXEIE | USART_CR1_PEIE) +#endif + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_serial_dma_poll + * + * Description: + * Must be called periodically if any STM32 USART is configured for DMA. + * The DMA callback is triggered for each fifo size/2 bytes, but this can + * result in some bytes being transferred but not collected if the incoming + * data is not a whole multiple of half the FIFO size. + * + * May be safely called from either interrupt or thread context. + * + ****************************************************************************/ + +#ifdef SERIAL_HAVE_RXDMA +void stm32_serial_dma_poll(void); +#endif + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_UART_M0_H */ diff --git a/arch/arm/src/common/stm32/stm32_uart_m3m4_v1v2.h b/arch/arm/src/common/stm32/stm32_uart_m3m4_v1v2.h new file mode 100644 index 0000000000000..c4e20a1a781f1 --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_uart_m3m4_v1v2.h @@ -0,0 +1,652 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_uart_m3m4_v1v2.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_UART_V1V2_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_UART_V1V2_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include "chip.h" +#include "hardware/stm32_uart.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Make sure that we have not enabled more U[S]ARTs than are supported by the + * device. + */ + +#if STM32_NUSART < 8 || !defined(CONFIG_STM32_HAVE_UART8) +# undef CONFIG_STM32_UART8 +#endif +#if STM32_NUSART < 7 || !defined(CONFIG_STM32_HAVE_UART7) +# undef CONFIG_STM32_UART7 +#endif +#if STM32_NUSART < 6 || !defined(CONFIG_STM32_HAVE_USART6) +# undef CONFIG_STM32_USART6 +#endif +#if STM32_NUSART < 5 || !defined(CONFIG_STM32_HAVE_UART5) +# undef CONFIG_STM32_UART5 +#endif +#if STM32_NUSART < 4 || !defined(CONFIG_STM32_HAVE_UART4) +# undef CONFIG_STM32_UART4 +#endif +#if STM32_NUSART < 3 || !defined(CONFIG_STM32_HAVE_USART3) +# undef CONFIG_STM32_USART3 +#endif +#if STM32_NUSART < 2 +# undef CONFIG_STM32_USART2 +#endif +#if STM32_NUSART < 1 +# undef CONFIG_STM32_USART1 +#endif + +#if !defined(CONFIG_STM32_HAVE_LPUART1) +# undef CONFIG_STM32_LPUART1 +#endif + +/* Sanity checks */ +#if !defined(CONFIG_STM32_LPUART1) +# undef CONFIG_STM32_LPUART1_SERIALDRIVER +# undef CONFIG_STM32_LPUART1_1WIREDRIVER +#endif +#if !defined(CONFIG_STM32_USART1) +# undef CONFIG_STM32_USART1_SERIALDRIVER +# undef CONFIG_STM32_USART1_1WIREDRIVER +#endif +#if !defined(CONFIG_STM32_USART2) +# undef CONFIG_STM32_USART2_SERIALDRIVER +# undef CONFIG_STM32_USART2_1WIREDRIVER +#endif +#if !defined(CONFIG_STM32_USART3) +# undef CONFIG_STM32_USART3_SERIALDRIVER +# undef CONFIG_STM32_USART3_1WIREDRIVER +#endif +#if !defined(CONFIG_STM32_UART4) +# undef CONFIG_STM32_UART4_SERIALDRIVER +# undef CONFIG_STM32_UART4_1WIREDRIVER +#endif +#if !defined(CONFIG_STM32_UART5) +# undef CONFIG_STM32_UART5_SERIALDRIVER +# undef CONFIG_STM32_UART5_1WIREDRIVER +#endif +#if !defined(CONFIG_STM32_USART6) +# undef CONFIG_STM32_USART6_SERIALDRIVER +# undef CONFIG_STM32_USART6_1WIREDRIVER +#endif +#if !defined(CONFIG_STM32_UART7) +# undef CONFIG_STM32_UART7_SERIALDRIVER +# undef CONFIG_STM32_UART7_1WIREDRIVER +#endif +#if !defined(CONFIG_STM32_UART8) +# undef CONFIG_STM32_UART8_SERIALDRIVER +# undef CONFIG_STM32_UART8_1WIREDRIVER +#endif + +/* Check 1-Wire and U(S)ART conflicts */ + +#if defined(CONFIG_STM32_USART1_1WIREDRIVER) && defined(CONFIG_STM32_USART1_SERIALDRIVER) +# error Both CONFIG_STM32_USART1_1WIREDRIVER and CONFIG_STM32_USART1_SERIALDRIVER defined +# undef CONFIG_STM32_USART1_1WIREDRIVER +#endif +#if defined(CONFIG_STM32_USART2_1WIREDRIVER) && defined(CONFIG_STM32_USART2_SERIALDRIVER) +# error Both CONFIG_STM32_USART2_1WIREDRIVER and CONFIG_STM32_USART2_SERIALDRIVER defined +# undef CONFIG_STM32_USART2_1WIREDRIVER +#endif +#if defined(CONFIG_STM32_USART3_1WIREDRIVER) && defined(CONFIG_STM32_USART3_SERIALDRIVER) +# error Both CONFIG_STM32_USART3_1WIREDRIVER and CONFIG_STM32_USART3_SERIALDRIVER defined +# undef CONFIG_STM32_USART3_1WIREDRIVER +#endif +#if defined(CONFIG_STM32_UART4_1WIREDRIVER) && defined(CONFIG_STM32_UART4_SERIALDRIVER) +# error Both CONFIG_STM32_UART4_1WIREDRIVER and CONFIG_STM32_UART4_SERIALDRIVER defined +# undef CONFIG_STM32_UART4_1WIREDRIVER +#endif +#if defined(CONFIG_STM32_UART5_1WIREDRIVER) && defined(CONFIG_STM32_UART5_SERIALDRIVER) +# error Both CONFIG_STM32_UART5_1WIREDRIVER and CONFIG_STM32_UART5_SERIALDRIVER defined +# undef CONFIG_STM32_UART5_1WIREDRIVER +#endif +#if defined(CONFIG_STM32_USART6_1WIREDRIVER) && defined(CONFIG_STM32_USART6_SERIALDRIVER) +# error Both CONFIG_STM32_USART6_1WIREDRIVER and CONFIG_STM32_USART6_SERIALDRIVER defined +# undef CONFIG_STM32_USART6_1WIREDRIVER +#endif +#if defined(CONFIG_STM32_UART7_1WIREDRIVER) && defined(CONFIG_STM32_UART7_SERIALDRIVER) +# error Both CONFIG_STM32_UART7_1WIREDRIVER and CONFIG_STM32_UART7_SERIALDRIVER defined +# undef CONFIG_STM32_UART7_1WIREDRIVER +#endif +#if defined(CONFIG_STM32_UART8_1WIREDRIVER) && defined(CONFIG_STM32_UART8_SERIALDRIVER) +# error Both CONFIG_STM32_UART8_1WIREDRIVER and CONFIG_STM32_UART8_SERIALDRIVER defined +# undef CONFIG_STM32_UART8_1WIREDRIVER +#endif + +/* Is the serial driver enabled? */ + +#if defined(CONFIG_STM32_USART1_SERIALDRIVER) || defined(CONFIG_STM32_USART2_SERIALDRIVER) || \ + defined(CONFIG_STM32_USART3_SERIALDRIVER) || defined(CONFIG_STM32_UART4_SERIALDRIVER) || \ + defined(CONFIG_STM32_UART5_SERIALDRIVER) || defined(CONFIG_STM32_USART6_SERIALDRIVER) || \ + defined(CONFIG_STM32_UART7_SERIALDRIVER) || defined(CONFIG_STM32_UART8_SERIALDRIVER) || \ + defined(CONFIG_STM32_LPUART1_SERIALDRIVER) +# define HAVE_SERIALDRIVER 1 +#endif + +/* Is the 1-Wire driver? */ + +#if defined(CONFIG_STM32_USART1_1WIREDRIVER) || defined(CONFIG_STM32_USART2_1WIREDRIVER) || \ + defined(CONFIG_STM32_USART3_1WIREDRIVER) || defined(CONFIG_STM32_UART4_1WIREDRIVER) || \ + defined(CONFIG_STM32_UART5_1WIREDRIVER) || defined(CONFIG_STM32_USART6_1WIREDRIVER) || \ + defined(CONFIG_STM32_UART7_1WIREDRIVER) || defined(CONFIG_STM32_UART8_1WIREDRIVER) +# define HAVE_1WIREDRIVER 1 +#endif + +/* Is there a serial console? */ + +#if defined(CONFIG_USART1_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART1_SERIALDRIVER) +# undef CONFIG_USART2_SERIAL_CONSOLE +# undef CONFIG_USART3_SERIAL_CONSOLE +# undef CONFIG_UART4_SERIAL_CONSOLE +# undef CONFIG_UART5_SERIAL_CONSOLE +# undef CONFIG_USART6_SERIAL_CONSOLE +# undef CONFIG_UART7_SERIAL_CONSOLE +# undef CONFIG_UART8_SERIAL_CONSOLE +# undef CONFIG_LPUART1_SERIAL_CONSOLE +# define CONSOLE_UART 1 +# define CONSOLE_LPUART 0 +# define HAVE_CONSOLE 1 +#elif defined(CONFIG_USART2_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART2_SERIALDRIVER) +# undef CONFIG_USART1_SERIAL_CONSOLE +# undef CONFIG_USART3_SERIAL_CONSOLE +# undef CONFIG_UART4_SERIAL_CONSOLE +# undef CONFIG_UART5_SERIAL_CONSOLE +# undef CONFIG_USART6_SERIAL_CONSOLE +# undef CONFIG_UART7_SERIAL_CONSOLE +# undef CONFIG_UART8_SERIAL_CONSOLE +# undef CONFIG_LPUART1_SERIAL_CONSOLE +# define CONSOLE_UART 2 +# define CONSOLE_LPUART 0 +# define HAVE_CONSOLE 1 +#elif defined(CONFIG_USART3_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART3_SERIALDRIVER) +# undef CONFIG_USART1_SERIAL_CONSOLE +# undef CONFIG_USART2_SERIAL_CONSOLE +# undef CONFIG_UART4_SERIAL_CONSOLE +# undef CONFIG_UART5_SERIAL_CONSOLE +# undef CONFIG_USART6_SERIAL_CONSOLE +# undef CONFIG_UART7_SERIAL_CONSOLE +# undef CONFIG_UART8_SERIAL_CONSOLE +# undef CONFIG_LPUART1_SERIAL_CONSOLE +# define CONSOLE_UART 3 +# define CONSOLE_LPUART 0 +# define HAVE_CONSOLE 1 +#elif defined(CONFIG_UART4_SERIAL_CONSOLE) && defined(CONFIG_STM32_UART4_SERIALDRIVER) +# undef CONFIG_USART1_SERIAL_CONSOLE +# undef CONFIG_USART2_SERIAL_CONSOLE +# undef CONFIG_USART3_SERIAL_CONSOLE +# undef CONFIG_UART5_SERIAL_CONSOLE +# undef CONFIG_USART6_SERIAL_CONSOLE +# undef CONFIG_UART7_SERIAL_CONSOLE +# undef CONFIG_UART8_SERIAL_CONSOLE +# undef CONFIG_LPUART1_SERIAL_CONSOLE +# define CONSOLE_UART 4 +# define CONSOLE_LPUART 0 +# define HAVE_CONSOLE 1 +#elif defined(CONFIG_UART5_SERIAL_CONSOLE) && defined(CONFIG_STM32_UART5_SERIALDRIVER) +# undef CONFIG_USART1_SERIAL_CONSOLE +# undef CONFIG_USART2_SERIAL_CONSOLE +# undef CONFIG_USART3_SERIAL_CONSOLE +# undef CONFIG_UART4_SERIAL_CONSOLE +# undef CONFIG_USART6_SERIAL_CONSOLE +# undef CONFIG_UART7_SERIAL_CONSOLE +# undef CONFIG_UART8_SERIAL_CONSOLE +# undef CONFIG_LPUART1_SERIAL_CONSOLE +# define CONSOLE_UART 5 +# define CONSOLE_LPUART 0 +# define HAVE_CONSOLE 1 +#elif defined(CONFIG_USART6_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART6_SERIALDRIVER) +# undef CONFIG_USART1_SERIAL_CONSOLE +# undef CONFIG_USART2_SERIAL_CONSOLE +# undef CONFIG_USART3_SERIAL_CONSOLE +# undef CONFIG_UART4_SERIAL_CONSOLE +# undef CONFIG_UART5_SERIAL_CONSOLE +# undef CONFIG_UART7_SERIAL_CONSOLE +# undef CONFIG_UART8_SERIAL_CONSOLE +# undef CONFIG_LPUART1_SERIAL_CONSOLE +# define CONSOLE_UART 6 +# define CONSOLE_LPUART 0 +# define HAVE_CONSOLE 1 +#elif defined(CONFIG_UART7_SERIAL_CONSOLE) && defined(CONFIG_STM32_UART7_SERIALDRIVER) +# undef CONFIG_USART1_SERIAL_CONSOLE +# undef CONFIG_USART2_SERIAL_CONSOLE +# undef CONFIG_USART3_SERIAL_CONSOLE +# undef CONFIG_UART4_SERIAL_CONSOLE +# undef CONFIG_UART5_SERIAL_CONSOLE +# undef CONFIG_USART6_SERIAL_CONSOLE +# undef CONFIG_UART8_SERIAL_CONSOLE +# undef CONFIG_LPUART1_SERIAL_CONSOLE +# define CONSOLE_UART 7 +# define CONSOLE_LPUART 0 +# define HAVE_CONSOLE 1 +#elif defined(CONFIG_UART8_SERIAL_CONSOLE) && defined(CONFIG_STM32_UART8_SERIALDRIVER) +# undef CONFIG_USART1_SERIAL_CONSOLE +# undef CONFIG_USART2_SERIAL_CONSOLE +# undef CONFIG_USART3_SERIAL_CONSOLE +# undef CONFIG_UART4_SERIAL_CONSOLE +# undef CONFIG_UART5_SERIAL_CONSOLE +# undef CONFIG_USART6_SERIAL_CONSOLE +# undef CONFIG_UART7_SERIAL_CONSOLE +# undef CONFIG_LPUART1_SERIAL_CONSOLE +# define CONSOLE_UART 8 +# define CONSOLE_LPUART 0 +# define HAVE_CONSOLE 1 +#elif defined(CONFIG_LPUART1_SERIAL_CONSOLE) && defined(CONFIG_STM32_LPUART1_SERIALDRIVER) +# undef CONFIG_USART1_SERIAL_CONSOLE +# undef CONFIG_USART2_SERIAL_CONSOLE +# undef CONFIG_USART3_SERIAL_CONSOLE +# undef CONFIG_UART4_SERIAL_CONSOLE +# undef CONFIG_UART5_SERIAL_CONSOLE +# undef CONFIG_USART6_SERIAL_CONSOLE +# undef CONFIG_UART7_SERIAL_CONSOLE +# undef CONFIG_UART8_SERIAL_CONSOLE +# define CONSOLE_LPUART 1 +# define CONSOLE_UART 0 +# define HAVE_CONSOLE 1 +#else +# undef CONFIG_USART1_SERIAL_CONSOLE +# undef CONFIG_USART2_SERIAL_CONSOLE +# undef CONFIG_USART3_SERIAL_CONSOLE +# undef CONFIG_UART4_SERIAL_CONSOLE +# undef CONFIG_UART5_SERIAL_CONSOLE +# undef CONFIG_USART6_SERIAL_CONSOLE +# undef CONFIG_UART7_SERIAL_CONSOLE +# undef CONFIG_UART8_SERIAL_CONSOLE +# undef CONFIG_LPUART1_SERIAL_CONSOLE +# define CONSOLE_UART 0 +# define CONSOLE_LPUART 0 +# undef HAVE_CONSOLE +#endif + +/* DMA support is only provided if CONFIG_ARCH_DMA is in the + * NuttX configuration + */ + +#if !defined(HAVE_SERIALDRIVER) || !defined(CONFIG_ARCH_DMA) +# undef CONFIG_USART1_RXDMA +# undef CONFIG_USART1_TXDMA +# undef CONFIG_USART2_RXDMA +# undef CONFIG_USART2_TXDMA +# undef CONFIG_USART3_RXDMA +# undef CONFIG_USART3_TXDMA +# undef CONFIG_UART4_RXDMA +# undef CONFIG_UART4_TXDMA +# undef CONFIG_UART5_RXDMA +# undef CONFIG_UART5_TXDMA +# undef CONFIG_USART6_RXDMA +# undef CONFIG_USART6_TXDMA +# undef CONFIG_UART7_RXDMA +# undef CONFIG_UART7_TXDMA +# undef CONFIG_UART8_RXDMA +# undef CONFIG_UART8_TXDMA +#endif + +/* Disable the DMA configuration on all unused USARTs */ + +#ifndef CONFIG_STM32_LPUART1_SERIALDRIVER +# undef CONFIG_LPUART1_RXDMA +# undef CONFIG_LPUART1_TXDMA +#endif + +#ifndef CONFIG_STM32_USART1_SERIALDRIVER +# undef CONFIG_USART1_RXDMA +# undef CONFIG_USART1_TXDMA +#endif + +#ifndef CONFIG_STM32_USART2_SERIALDRIVER +# undef CONFIG_USART2_RXDMA +# undef CONFIG_USART2_TXDMA +#endif + +#ifndef CONFIG_STM32_USART3_SERIALDRIVER +# undef CONFIG_USART3_RXDMA +# undef CONFIG_USART3_TXDMA +#endif + +#ifndef CONFIG_STM32_UART4_SERIALDRIVER +# undef CONFIG_UART4_RXDMA +# undef CONFIG_UART4_TXDMA +#endif + +#ifndef CONFIG_STM32_UART5_SERIALDRIVER +# undef CONFIG_UART5_RXDMA +# undef CONFIG_UART5_TXDMA +#endif + +#ifndef CONFIG_STM32_USART6_SERIALDRIVER +# undef CONFIG_USART6_RXDMA +# undef CONFIG_USART6_TXDMA +#endif + +#ifndef CONFIG_STM32_UART7_SERIALDRIVER +# undef CONFIG_UART7_RXDMA +# undef CONFIG_UART7_TXDMA +#endif + +#ifndef CONFIG_STM32_UART8_SERIALDRIVER +# undef CONFIG_UART8_RXDMA +# undef CONFIG_UART8_TXDMA +#endif + +/* Is DMA available on any (enabled) USART? */ + +#undef SERIAL_HAVE_RXDMA +#if defined(CONFIG_USART1_RXDMA) || defined(CONFIG_USART2_RXDMA) || \ + defined(CONFIG_USART3_RXDMA) || defined(CONFIG_UART4_RXDMA) || \ + defined(CONFIG_UART5_RXDMA) || defined(CONFIG_USART6_RXDMA) || \ + defined(CONFIG_UART7_RXDMA) || defined(CONFIG_UART8_RXDMA) || \ + defined(CONFIG_LPUART1_RXDMA) +# define SERIAL_HAVE_RXDMA 1 +#endif + +/* Is TX DMA available on any (enabled) USART? */ + +#undef SERIAL_HAVE_TXDMA +#if defined(CONFIG_USART1_TXDMA) || defined(CONFIG_USART2_TXDMA) || \ + defined(CONFIG_USART3_TXDMA) || defined(CONFIG_UART4_TXDMA) || \ + defined(CONFIG_UART5_TXDMA) || defined(CONFIG_USART6_TXDMA) || \ + defined(CONFIG_UART7_TXDMA) || defined(CONFIG_UART8_TXDMA) || \ + defined(CONFIG_LPUART1_TXDMA) +# define SERIAL_HAVE_TXDMA 1 +#endif + +/* Is RX DMA used on the console UART? */ + +#undef SERIAL_HAVE_CONSOLE_RXDMA +#if defined(CONFIG_USART1_SERIAL_CONSOLE) && defined(CONFIG_USART1_RXDMA) +# define SERIAL_HAVE_CONSOLE_RXDMA 1 +#elif defined(CONFIG_USART2_SERIAL_CONSOLE) && defined(CONFIG_USART2_RXDMA) +# define SERIAL_HAVE_CONSOLE_RXDMA 1 +#elif defined(CONFIG_USART3_SERIAL_CONSOLE) && defined(CONFIG_USART3_RXDMA) +# define SERIAL_HAVE_CONSOLE_RXDMA 1 +#elif defined(CONFIG_UART4_SERIAL_CONSOLE) && defined(CONFIG_UART4_RXDMA) +# define SERIAL_HAVE_CONSOLE_RXDMA 1 +#elif defined(CONFIG_UART5_SERIAL_CONSOLE) && defined(CONFIG_UART5_RXDMA) +# define SERIAL_HAVE_CONSOLE_RXDMA 1 +#elif defined(CONFIG_USART6_SERIAL_CONSOLE) && defined(CONFIG_USART6_RXDMA) +# define SERIAL_HAVE_CONSOLE_RXDMA 1 +#elif defined(CONFIG_UART7_SERIAL_CONSOLE) && defined(CONFIG_UART7_RXDMA) +# define SERIAL_HAVE_CONSOLE_RXDMA 1 +#elif defined(CONFIG_UART8_SERIAL_CONSOLE) && defined(CONFIG_UART8_RXDMA) +# define SERIAL_HAVE_CONSOLE_RXDMA 1 +#elif defined(CONFIG_LPUART1_SERIAL_CONSOLE) && defined(CONFIG_LPUART1_RXDMA) +# define SERIAL_HAVE_CONSOLE_RXDMA 1 +#endif + +/* Is TX DMA used on the console UART? */ + +#undef SERIAL_HAVE_CONSOLE_TXDMA +#if defined(CONFIG_USART1_SERIAL_CONSOLE) && defined(CONFIG_USART1_TXDMA) +# define SERIAL_HAVE_CONSOLE_TXDMA 1 +#elif defined(CONFIG_USART2_SERIAL_CONSOLE) && defined(CONFIG_USART2_TXDMA) +# define SERIAL_HAVE_CONSOLE_TXDMA 1 +#elif defined(CONFIG_USART3_SERIAL_CONSOLE) && defined(CONFIG_USART3_TXDMA) +# define SERIAL_HAVE_CONSOLE_TXDMA 1 +#elif defined(CONFIG_UART4_SERIAL_CONSOLE) && defined(CONFIG_UART4_TXDMA) +# define SERIAL_HAVE_CONSOLE_TXDMA 1 +#elif defined(CONFIG_UART5_SERIAL_CONSOLE) && defined(CONFIG_UART5_TXDMA) +# define SERIAL_HAVE_CONSOLE_TXDMA 1 +#elif defined(CONFIG_USART6_SERIAL_CONSOLE) && defined(CONFIG_USART6_TXDMA) +# define SERIAL_HAVE_CONSOLE_TXDMA 1 +#elif defined(CONFIG_UART7_SERIAL_CONSOLE) && defined(CONFIG_UART7_TXDMA) +# define SERIAL_HAVE_CONSOLE_TXDMA 1 +#elif defined(CONFIG_UART8_SERIAL_CONSOLE) && defined(CONFIG_UART8_TXDMA) +# define SERIAL_HAVE_CONSOLE_TXDMA 1 +#elif defined(CONFIG_LPUART1_SERIAL_CONSOLE) && defined(CONFIG_LPUART1_TXDMA) +# define SERIAL_HAVE_CONSOLE_TXDMA 1 +#endif + +/* Is RX DMA used on all (enabled) USARTs */ + +#define SERIAL_HAVE_ONLY_RXDMA 1 +#if defined(CONFIG_STM32_USART1) && !defined(CONFIG_USART1_RXDMA) +# undef SERIAL_HAVE_ONLY_RXDMA +#elif defined(CONFIG_STM32_USART2) && !defined(CONFIG_USART2_RXDMA) +# undef SERIAL_HAVE_ONLY_RXDMA +#elif defined(CONFIG_STM32_USART3) && !defined(CONFIG_USART3_RXDMA) +# undef SERIAL_HAVE_ONLY_RXDMA +#elif defined(CONFIG_STM32_UART4) && !defined(CONFIG_UART4_RXDMA) +# undef SERIAL_HAVE_ONLY_RXDMA +#elif defined(CONFIG_STM32_UART5) && !defined(CONFIG_UART5_RXDMA) +# undef SERIAL_HAVE_ONLY_RXDMA +#elif defined(CONFIG_STM32_USART6) && !defined(CONFIG_USART6_RXDMA) +# undef SERIAL_HAVE_ONLY_RXDMA +#elif defined(CONFIG_STM32_UART7) && !defined(CONFIG_UART7_RXDMA) +# undef SERIAL_HAVE_ONLY_RXDMA +#elif defined(CONFIG_STM32_UART8) && !defined(CONFIG_UART8_RXDMA) +# undef SERIAL_HAVE_ONLY_RXDMA +#elif defined(CONFIG_STM32_LPUART1) && !defined(CONFIG_LPUART1_RXDMA) +# undef SERIAL_HAVE_ONLY_RXDMA +#endif + +/* Is TX DMA used on all (enabled) USARTs */ + +#define SERIAL_HAVE_ONLY_TXDMA 1 +#if defined(CONFIG_STM32_USART1) && !defined(CONFIG_USART1_TXDMA) +# undef SERIAL_HAVE_ONLY_TXDMA +#elif defined(CONFIG_STM32_USART2) && !defined(CONFIG_USART2_TXDMA) +# undef SERIAL_HAVE_ONLY_TXDMA +#elif defined(CONFIG_STM32_USART3) && !defined(CONFIG_USART3_TXDMA) +# undef SERIAL_HAVE_ONLY_TXDMA +#elif defined(CONFIG_STM32_UART4) && !defined(CONFIG_UART4_TXDMA) +# undef SERIAL_HAVE_ONLY_TXDMA +#elif defined(CONFIG_STM32_UART5) && !defined(CONFIG_UART5_TXDMA) +# undef SERIAL_HAVE_ONLY_TXDMA +#elif defined(CONFIG_STM32_USART6) && !defined(CONFIG_USART6_TXDMA) +# undef SERIAL_HAVE_ONLY_TXDMA +#elif defined(CONFIG_STM32_UART7) && !defined(CONFIG_UART7_TXDMA) +# undef SERIAL_HAVE_ONLY_TXDMA +#elif defined(CONFIG_STM32_UART8) && !defined(CONFIG_UART8_TXDMA) +# undef SERIAL_HAVE_ONLY_TXDMA +#elif defined(CONFIG_STM32_LPUART1) && !defined(CONFIG_LPUART1_TXDMA) +# undef SERIAL_HAVE_ONLY_TXDMA +#endif + +#undef SERIAL_HAVE_ONLY_DMA +#if defined(SERIAL_HAVE_ONLY_RXDMA) && defined(SERIAL_HAVE_ONLY_TXDMA) +# define SERIAL_HAVE_ONLY_DMA 1 +#endif + +/* No DMA ops */ + +#undef SERIAL_HAVE_NODMA_OPS +#if defined(CONFIG_STM32_USART1) && !defined(CONFIG_USART1_RXDMA) && \ + !defined(CONFIG_USART1_TXDMA) +# define SERIAL_HAVE_NODMA_OPS +#elif defined(CONFIG_STM32_USART2) && !defined(CONFIG_USART2_RXDMA) && \ + !defined(CONFIG_USART2_TXDMA) +# define SERIAL_HAVE_NODMA_OPS +#elif defined(CONFIG_STM32_USART3) && !defined(CONFIG_USART3_RXDMA) && \ + !defined(CONFIG_USART3_TXDMA) +# define SERIAL_HAVE_NODMA_OPS +#elif defined(CONFIG_STM32_UART4) && !defined(CONFIG_UART4_RXDMA) && \ + !defined(CONFIG_UART4_TXDMA) +# define SERIAL_HAVE_NODMA_OPS +#elif defined(CONFIG_STM32_UART5) && !defined(CONFIG_UART5_RXDMA) && \ + !defined(CONFIG_UART5_TXDMA) +# define SERIAL_HAVE_NODMA_OPS +#elif defined(CONFIG_STM32_USART6) && !defined(CONFIG_USART6_RXDMA) && \ + !defined(CONFIG_USART6_TXDMA) +# define SERIAL_HAVE_NODMA_OPS +#elif defined(CONFIG_STM32_UART7) && !defined(CONFIG_UART7_RXDMA) && \ + !defined(CONFIG_UART7_TXDMA) +# define SERIAL_HAVE_NODMA_OPS +#elif defined(CONFIG_STM32_UART8) && !defined(CONFIG_UART8_RXDMA) && \ + !defined(CONFIG_UART8_TXDMA) +# define SERIAL_HAVE_NODMA_OPS +#elif defined(CONFIG_STM32_LPUART1) && !defined(CONFIG_LPUART1_RXDMA) && \ + !defined(CONFIG_LPUART1_TXDMA) +# define SERIAL_HAVE_NODMA_OPS +#endif + +/* RX+TX DMA ops */ + +#undef SERIAL_HAVE_RXTXDMA_OPS +#if defined(CONFIG_USART1_RXDMA) && defined(CONFIG_USART1_TXDMA) +# define SERIAL_HAVE_RXTXDMA_OPS +#elif defined(CONFIG_USART2_RXDMA) && defined(CONFIG_USART2_TXDMA) +# define SERIAL_HAVE_RXTXDMA_OPS +#elif defined(CONFIG_USART3_RXDMA) && defined(CONFIG_USART3_TXDMA) +# define SERIAL_HAVE_RXTXDMA_OPS +#elif defined(CONFIG_UART4_RXDMA) && defined(CONFIG_UART4_TXDMA) +# define SERIAL_HAVE_RXTXDMA_OPS +#elif defined(CONFIG_UART5_RXDMA) && defined(CONFIG_UART5_TXDMA) +# define SERIAL_HAVE_RXTXDMA_OPS +#elif defined(CONFIG_USART6_RXDMA) && defined(CONFIG_USART6_TXDMA) +# define SERIAL_HAVE_RXTXDMA_OPS +#elif defined(CONFIG_UART7_RXDMA) && defined(CONFIG_UART7_TXDMA) +# define SERIAL_HAVE_RXTXDMA_OPS +#elif defined(CONFIG_UART8_RXDMA) && defined(CONFIG_UART8_TXDMA) +# define SERIAL_HAVE_RXTXDMA_OPS +#elif defined(CONFIG_LPUART1_RXDMA) && defined(CONFIG_LPUART1_TXDMA) +# define SERIAL_HAVE_RXTXDMA_OPS +#endif + +/* TX DMA ops */ + +#undef SERIAL_HAVE_TXDMA_OPS +#if !defined(CONFIG_USART1_RXDMA) && defined(CONFIG_USART1_TXDMA) +# define SERIAL_HAVE_TXDMA_OPS +#elif !defined(CONFIG_USART2_RXDMA) && defined(CONFIG_USART2_TXDMA) +# define SERIAL_HAVE_TXDMA_OPS +#elif !defined(CONFIG_USART3_RXDMA) && defined(CONFIG_USART3_TXDMA) +# define SERIAL_HAVE_TXDMA_OPS +#elif !defined(CONFIG_UART4_RXDMA) && defined(CONFIG_UART4_TXDMA) +# define SERIAL_HAVE_TXDMA_OPS +#elif !defined(CONFIG_UART5_RXDMA) && defined(CONFIG_UART5_TXDMA) +# define SERIAL_HAVE_TXDMA_OPS +#elif !defined(CONFIG_USART6_RXDMA) && defined(CONFIG_USART6_TXDMA) +# define SERIAL_HAVE_TXDMA_OPS +#elif !defined(CONFIG_UART7_RXDMA) && defined(CONFIG_UART7_TXDMA) +# define SERIAL_HAVE_TXDMA_OPS +#elif !defined(CONFIG_UART8_RXDMA) && defined(CONFIG_UART8_TXDMA) +# define SERIAL_HAVE_TXDMA_OPS +#elif !defined(CONFIG_LPUART1_RXDMA) && defined(CONFIG_LPUART1_TXDMA) +# define SERIAL_HAVE_TXDMA_OPS +#endif + +/* RX DMA ops */ + +#undef SERIAL_HAVE_RXDMA_OPS +#if defined(CONFIG_USART1_RXDMA) && !defined(CONFIG_USART1_TXDMA) +# define SERIAL_HAVE_RXDMA_OPS +#elif defined(CONFIG_USART2_RXDMA) && !defined(CONFIG_USART2_TXDMA) +# define SERIAL_HAVE_RXDMA_OPS +#elif defined(CONFIG_USART3_RXDMA) && !defined(CONFIG_USART3_TXDMA) +# define SERIAL_HAVE_RXDMA_OPS +#elif defined(CONFIG_UART4_RXDMA) && !defined(CONFIG_UART4_TXDMA) +# define SERIAL_HAVE_RXDMA_OPS +#elif defined(CONFIG_UART5_RXDMA) && !defined(CONFIG_UART5_TXDMA) +# define SERIAL_HAVE_RXDMA_OPS +#elif defined(CONFIG_USART6_RXDMA) && !defined(CONFIG_USART6_TXDMA) +# define SERIAL_HAVE_RXDMA_OPS +#elif defined(CONFIG_UART7_RXDMA) && !defined(CONFIG_UART7_TXDMA) +# define SERIAL_HAVE_RXDMA_OPS +#elif defined(CONFIG_UART8_RXDMA) && !defined(CONFIG_UART8_TXDMA) +# define SERIAL_HAVE_RXDMA_OPS +#elif defined(CONFIG_LPUART1_RXDMA) && !defined(CONFIG_LPUART1_TXDMA) +# define SERIAL_HAVE_RXDMA_OPS +#endif + +/* Is RS-485 used? */ + +#if defined(CONFIG_USART1_RS485) || defined(CONFIG_USART2_RS485) || \ + defined(CONFIG_USART3_RS485) || defined(CONFIG_UART4_RS485) || \ + defined(CONFIG_UART5_RS485) || defined(CONFIG_USART6_RS485) || \ + defined(CONFIG_UART7_RS485) || defined(CONFIG_UART8_RS485) || \ + defined(CONFIG_LPUART1_RS485) +# define HAVE_RS485 1 +#endif + +#ifdef HAVE_RS485 +# define USART_CR1_USED_INTS (USART_CR1_RXNEIE | USART_CR1_TXEIE | USART_CR1_PEIE | USART_CR1_TCIE) +#else +# define USART_CR1_USED_INTS (USART_CR1_RXNEIE | USART_CR1_TXEIE | USART_CR1_PEIE) +#endif + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_serial_get_uart + * + * Description: + * Get serial driver structure for STM32 USART + * + ****************************************************************************/ + +uart_dev_t *stm32_serial_get_uart(int uart_num); + +/**************************************************************************** + * Name: stm32_serial_dma_poll + * + * Description: + * Must be called periodically if any STM32 UART is configured for DMA. + * The DMA callback is triggered for each fifo size/2 bytes, but this can + * result in some bytes being transferred but not collected if the incoming + * data is not a whole multiple of half the FIFO size. + * + * May be safely called from either interrupt or thread context. + * + ****************************************************************************/ + +#ifdef SERIAL_HAVE_RXDMA +void stm32_serial_dma_poll(void); +#endif + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_UART_V1V2_H */ diff --git a/arch/arm/src/common/stm32/stm32_uid.c b/arch/arm/src/common/stm32/stm32_uid.c new file mode 100644 index 0000000000000..190f38b975ff1 --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_uid.c @@ -0,0 +1,62 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_uid.c + * + * SPDX-License-Identifier: BSD-3-Clause + * SPDX-FileCopyrightText: 2015 Marawan Ragab. All rights reserved. + * SPDX-FileContributor: Marawan Ragab + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "chip.h" +#include "stm32_uid.h" + +#ifdef STM32_SYSMEM_UID /* Not defined for some STM32 parts */ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +void stm32_get_uniqueid(uint8_t uniqueid[12]) +{ + int i; + + for (i = 0; i < 12; i++) + { + uniqueid[i] = *((uint8_t *)(STM32_SYSMEM_UID) + i); + } +} + +#endif /* STM32_SYSMEM_UID */ diff --git a/arch/arm/src/common/stm32/stm32_uid.h b/arch/arm/src/common/stm32/stm32_uid.h new file mode 100644 index 0000000000000..7bf3119bbcbef --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_uid.h @@ -0,0 +1,44 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_uid.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_COMPAT_STM32_UID_H +#define __ARCH_ARM_SRC_COMMON_COMPAT_STM32_UID_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/* Read the 96-bit STM32 unique device ID into a 12-byte buffer. This + * interface is common to all STM32 families. + */ + +void stm32_get_uniqueid(uint8_t uniqueid[12]); + +#endif /* __ARCH_ARM_SRC_COMMON_COMPAT_STM32_UID_H */ diff --git a/arch/arm/src/common/stm32/stm32_usbdev.h b/arch/arm/src/common/stm32/stm32_usbdev.h new file mode 100644 index 0000000000000..1d1a989b0d082 --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_usbdev.h @@ -0,0 +1,94 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_usbdev.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_USBDEV_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_USBDEV_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include + +#include "chip.h" +#include "hardware/stm32_usbdev.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Number of endpoints */ + +#ifndef STM32_NENDPOINTS +# define STM32_NENDPOINTS (8) +#endif + +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Name: stm32_usbpullup + * + * Description: + * If USB is supported and the board supports a pullup via GPIO + * (for USB software connect and disconnect), then the board software must + * provide stm32_pullup. + * See include/nuttx/usb/usbdev.h for additional description of this method. + * + ****************************************************************************/ + +int stm32_usbpullup(struct usbdev_s *dev, bool enable); + +/**************************************************************************** + * Name: stm32_usbsuspend + * + * Description: + * Board logic must provide the stm32_usbsuspend logic if the USBDEV driver + * is used. This function is called whenever the USB enters or leaves + * suspend mode. This is an opportunity for the board logic to shutdown + * clocks, power, etc. while the USB is suspended. + * + ****************************************************************************/ + +void stm32_usbsuspend(struct usbdev_s *dev, bool resume); + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_USBDEV_H */ diff --git a/arch/arm/src/common/stm32/stm32_usbdev_m0_v1.c b/arch/arm/src/common/stm32/stm32_usbdev_m0_v1.c new file mode 100644 index 0000000000000..59632743a295c --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_usbdev_m0_v1.c @@ -0,0 +1,3888 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_usbdev_m0_v1.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* Ported from the STM32 F1 implementation. References: + * - RM0008 Reference manual, STMicro document ID 13902 + * - STM32F10xxx USB development kit, UM0424, STMicro + */ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include + +#include "arm_internal.h" +#include "hardware/stm32_rcc.h" +#include "hardware/stm32_usbdev.h" +#include "stm32_gpio.h" +#include "stm32_usbdev.h" + +#if defined(CONFIG_USBDEV) && defined(CONFIG_STM32_USB) + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +#ifndef CONFIG_USBDEV_EP0_MAXSIZE +# define CONFIG_USBDEV_EP0_MAXSIZE 64 +#endif + +#ifndef CONFIG_USBDEV_SETUP_MAXDATASIZE +# define CONFIG_USBDEV_SETUP_MAXDATASIZE CONFIG_USBDEV_EP0_MAXSIZE +#endif + +/* Extremely detailed register debug that you would normally never want + * enabled. + */ + +#ifndef CONFIG_DEBUG_USB_INFO +# undef CONFIG_STM32_USBDEV_REGDEBUG +#endif + +/* Initial interrupt mask: Reset + Suspend + Correct Transfer */ + +#define STM32_CNTR_SETUP (USB_CNTR_RESETM|USB_CNTR_SUSPM|USB_CNTR_CTRM) + +/* Endpoint identifiers. The STM32 supports up to 16 mono-directional or 8 + * bidirectional endpoints. However, when you take into account PMA buffer + * usage (see below) and the fact that EP0 is bidirectional, then there is + * a functional limitation of EP0 + 5 mono-directional endpoints = 6. We'll + * define STM32_NENDPOINTS to be 8, however, because that is how many + * endpoint register sets there are. + */ + +#define EP0 (0) +#define EP1 (1) +#define EP2 (2) +#define EP3 (3) +#define EP4 (4) +#define EP5 (5) +#define EP6 (6) +#define EP7 (7) + +#define STM32_ENDP_BIT(ep) (1 << (ep)) +#define STM32_ENDP_ALLSET 0xff + +/* Packet sizes. We us a fixed 64 max packet size for all endpoint types */ + +#define STM32_MAXPACKET_SHIFT (6) +#define STM32_MAXPACKET_SIZE (1 << (STM32_MAXPACKET_SHIFT)) +#define STM32_MAXPACKET_MASK (STM32_MAXPACKET_SIZE-1) + +#define STM32_EP0MAXPACKET STM32_MAXPACKET_SIZE + +/* Buffer descriptor table. We assume that USB has exclusive use of CAN/USB + * memory. The buffer table is positioned at the beginning of the 512-byte + * CAN/USB memory. + * We will use the first STM32_NENDPOINTS*4 words for the buffer table. + * That is exactly 64 bytes, leaving 7*64 bytes for endpoint buffers. + */ + +#define STM32_BTABLE_ADDRESS (0x00) /* Start at the beginning of USB/CAN RAM */ +#define STM32_DESC_SIZE (8) /* Each descriptor is 4*2=8 bytes in size */ +#define STM32_BTABLE_SIZE (STM32_NENDPOINTS*STM32_DESC_SIZE) + +/* Buffer layout. Assume that all buffers are 64-bytes (maxpacketsize), then + * we have space for only 7 buffers; endpoint 0 will require two buffers, + * leaving 5 for other endpoints. + */ + +#define STM32_BUFFER_START STM32_BTABLE_SIZE +#define STM32_EP0_RXADDR STM32_BUFFER_START +#define STM32_EP0_TXADDR (STM32_EP0_RXADDR+STM32_EP0MAXPACKET) + +#define STM32_BUFFER_EP0 0x03 +#define STM32_NBUFFERS 7 +#define STM32_BUFFER_BIT(bn) (1 << (bn)) +#define STM32_BUFFER_ALLSET 0x7f +#define STM32_BUFNO2BUF(bn) (STM32_BUFFER_START+((bn)<head == NULL) +#define stm32_rqpeek(ep) ((ep)->head) + +/* USB trace ****************************************************************/ + +/* Trace error codes */ + +#define STM32_TRACEERR_ALLOCFAIL 0x0001 +#define STM32_TRACEERR_BADCLEARFEATURE 0x0002 +#define STM32_TRACEERR_BADDEVGETSTATUS 0x0003 +#define STM32_TRACEERR_BADEPGETSTATUS 0x0004 +#define STM32_TRACEERR_BADEPNO 0x0005 +#define STM32_TRACEERR_BADEPTYPE 0x0006 +#define STM32_TRACEERR_BADGETCONFIG 0x0007 +#define STM32_TRACEERR_BADGETSETDESC 0x0008 +#define STM32_TRACEERR_BADGETSTATUS 0x0009 +#define STM32_TRACEERR_BADSETADDRESS 0x000a +#define STM32_TRACEERR_BADSETCONFIG 0x000b +#define STM32_TRACEERR_BADSETFEATURE 0x000c +#define STM32_TRACEERR_BINDFAILED 0x000d +#define STM32_TRACEERR_DISPATCHSTALL 0x000e +#define STM32_TRACEERR_DRIVER 0x000f +#define STM32_TRACEERR_DRIVERREGISTERED 0x0010 +#define STM32_TRACEERR_EP0BADCTR 0x0011 +#define STM32_TRACEERR_EP0SETUPSTALLED 0x0012 +#define STM32_TRACEERR_EPBUFFER 0x0013 +#define STM32_TRACEERR_EPDISABLED 0x0014 +#define STM32_TRACEERR_EPOUTNULLPACKET 0x0015 +#define STM32_TRACEERR_EPRESERVE 0x0016 +#define STM32_TRACEERR_INVALIDCTRLREQ 0x0017 +#define STM32_TRACEERR_INVALIDPARMS 0x0018 +#define STM32_TRACEERR_IRQREGISTRATION 0x0019 +#define STM32_TRACEERR_NOTCONFIGURED 0x001a +#define STM32_TRACEERR_REQABORTED 0x001b + +/* Trace interrupt codes */ + +#define STM32_TRACEINTID_CLEARFEATURE 0x0001 +#define STM32_TRACEINTID_DEVGETSTATUS 0x0002 +#define STM32_TRACEINTID_DISPATCH 0x0003 +#define STM32_TRACEINTID_EP0IN 0x0004 +#define STM32_TRACEINTID_EP0INDONE 0x0005 +#define STM32_TRACEINTID_EP0OUTDONE 0x0006 +#define STM32_TRACEINTID_EP0SETUPDONE 0x0007 +#define STM32_TRACEINTID_EP0SETUPSETADDRESS 0x0008 +#define STM32_TRACEINTID_EPGETSTATUS 0x0009 +#define STM32_TRACEINTID_EPINDONE 0x000a +#define STM32_TRACEINTID_EPINQEMPTY 0x000b +#define STM32_TRACEINTID_EPOUTDONE 0x000c +#define STM32_TRACEINTID_EPOUTPENDING 0x000d +#define STM32_TRACEINTID_EPOUTQEMPTY 0x000e +#define STM32_TRACEINTID_ESOF 0x000f +#define STM32_TRACEINTID_GETCONFIG 0x0010 +#define STM32_TRACEINTID_GETSETDESC 0x0011 +#define STM32_TRACEINTID_GETSETIF 0x0012 +#define STM32_TRACEINTID_GETSTATUS 0x0013 +#define STM32_TRACEINTID_INTERRUPT 0x0014 +#define STM32_TRACEINTID_IFGETSTATUS 0x0015 +#define STM32_TRACEINTID_LPCTR 0x0016 +#define STM32_TRACEINTID_NOSTDREQ 0x0017 +#define STM32_TRACEINTID_RESET 0x0018 +#define STM32_TRACEINTID_SETCONFIG 0x0019 +#define STM32_TRACEINTID_SETFEATURE 0x001a +#define STM32_TRACEINTID_SUSP 0x001b +#define STM32_TRACEINTID_SYNCHFRAME 0x001c +#define STM32_TRACEINTID_WKUP 0x001d +#define STM32_TRACEINTID_EP0SETUPOUT 0x001e +#define STM32_TRACEINTID_EP0SETUPOUTDATA 0x001f + +/* Byte ordering in host-based values */ + +#ifdef CONFIG_ENDIAN_BIG +# define LSB 1 +# define MSB 0 +#else +# define LSB 0 +# define MSB 1 +#endif + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/* The various states of a control pipe */ + +enum stm32_ep0state_e +{ + EP0STATE_IDLE = 0, /* No request in progress */ + EP0STATE_SETUP_OUT, /* Set up received with data for device OUT in progress */ + EP0STATE_SETUP_READY, /* Set up was received prior and is in ctrl, + * now the data has arrived */ + EP0STATE_WRREQUEST, /* Write request in progress */ + EP0STATE_RDREQUEST, /* Read request in progress */ + EP0STATE_STALLED /* We are stalled */ +}; + +/* Resume states */ + +enum stm32_rsmstate_e +{ + RSMSTATE_IDLE = 0, /* Device is either fully suspended or running */ + RSMSTATE_STARTED, /* Resume sequence has been started */ + RSMSTATE_WAITING /* Waiting (on ESOFs) for end of sequence */ +}; + +union wb_u +{ + uint16_t w; + uint8_t b[2]; +}; + +/* A container for a request so that the request make be retained in a list */ + +struct stm32_req_s +{ + struct usbdev_req_s req; /* Standard USB request */ + struct stm32_req_s *flink; /* Supports a singly linked list */ +}; + +/* This is the internal representation of an endpoint */ + +struct stm32_ep_s +{ + /* Common endpoint fields. This must be the first thing defined in the + * structure so that it is possible to simply cast from struct usbdev_ep_s + * to struct stm32_ep_s. + */ + + struct usbdev_ep_s ep; /* Standard endpoint structure */ + + /* STR71X-specific fields */ + + struct stm32_usbdev_s *dev; /* Reference to private driver data */ + struct stm32_req_s *head; /* Request list for this endpoint */ + struct stm32_req_s *tail; + uint8_t bufno; /* Allocated buffer number */ + uint8_t stalled:1; /* true: Endpoint is stalled */ + uint8_t halted:1; /* true: Endpoint feature halted */ + uint8_t txbusy:1; /* true: TX endpoint FIFO full */ + uint8_t txnullpkt:1; /* Null packet needed at end of transfer */ +}; + +struct stm32_usbdev_s +{ + /* Common device fields. This must be the first thing defined in the + * structure so that it is possible to simply cast from struct usbdev_s + * to structstm32_usbdev_s. + */ + + struct usbdev_s usbdev; + + /* The bound device class driver */ + + struct usbdevclass_driver_s *driver; + + /* STM32-specific fields */ + + uint8_t ep0state; /* State of EP0 (see enum stm32_ep0state_e) */ + uint8_t rsmstate; /* Resume state (see enum stm32_rsmstate_e) */ + uint8_t nesofs; /* ESOF counter (for resume support) */ + uint8_t rxpending:1; /* 1: OUT data in PMA, but no read requests */ + uint8_t selfpowered:1; /* 1: Device is self powered */ + uint8_t epavail; /* Bitset of available endpoints */ + uint8_t bufavail; /* Bitset of available buffers */ + uint16_t rxstatus; /* Saved during interrupt processing */ + uint16_t txstatus; /* " " " " " " " " */ + uint16_t imask; /* Current interrupt mask */ + + /* E0 SETUP data buffering. + * + * ctrl + * The 8-byte SETUP request is received on the EP0 OUT endpoint and is + * saved. + * + * ep0data + * For OUT SETUP requests, the SETUP data phase must also complete before + * the SETUP command can be processed. The ep0 packet receipt logic + * stm32_ep0_rdrequest will save the accompanying EP0 OUT data in + * ep0data[] before the SETUP command is re-processed. + * + * ep0datlen + * Length of OUT DATA received in ep0data[] + */ + + struct usb_ctrlreq_s ctrl; /* Last EP0 request */ + + uint8_t ep0data[CONFIG_USBDEV_SETUP_MAXDATASIZE]; + uint16_t ep0datlen; + + /* The endpoint list */ + + struct stm32_ep_s eplist[STM32_NENDPOINTS]; +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/* Register operations ******************************************************/ + +#ifdef CONFIG_STM32_USBDEV_REGDEBUG +static uint16_t stm32_getreg(uint32_t addr); +static void stm32_putreg(uint16_t val, uint32_t addr); +static void stm32_dumpep(int epno); +#else +# define stm32_getreg(addr) getreg16(addr) +# define stm32_putreg(val,addr) putreg16(val,addr) +# define stm32_dumpep(epno) +#endif + +/* Low-Level Helpers ********************************************************/ + +static inline void stm32_seteptxcount(uint8_t epno, + uint16_t count); +static inline void stm32_seteptxaddr(uint8_t epno, + uint16_t addr); +static inline uint16_t stm32_geteptxaddr(uint8_t epno); +static void stm32_seteprxcount(uint8_t epno, uint16_t count); +static inline uint16_t stm32_geteprxcount(uint8_t epno); +static inline void stm32_seteprxaddr(uint8_t epno, uint16_t addr); +static inline uint16_t stm32_geteprxaddr(uint8_t epno); +static inline void stm32_setepaddress(uint8_t epno, uint16_t addr); +static inline void stm32_seteptype(uint8_t epno, uint16_t type); +static inline void stm32_seteptxaddr(uint8_t epno, uint16_t addr); +static inline void stm32_clrstatusout(uint8_t epno); +static void stm32_clrrxdtog(uint8_t epno); +static void stm32_clrtxdtog(uint8_t epno); +static void stm32_clrepctrrx(uint8_t epno); +static void stm32_clrepctrtx(uint8_t epno); +static void stm32_seteptxstatus(uint8_t epno, uint16_t state); +static void stm32_seteprxstatus(uint8_t epno, uint16_t state); +static inline uint16_t stm32_geteptxstatus(uint8_t epno); +static inline uint16_t stm32_geteprxstatus(uint8_t epno); +static bool stm32_eptxstalled(uint8_t epno); +static bool stm32_eprxstalled(uint8_t epno); +static void stm32_setimask(struct stm32_usbdev_s *priv, + uint16_t setbits, + uint16_t clrbits); + +/* Suspend/Resume Helpers ***************************************************/ + +static void stm32_suspend(struct stm32_usbdev_s *priv); +static void stm32_initresume(struct stm32_usbdev_s *priv); +static void stm32_esofpoll(struct stm32_usbdev_s *priv) ; + +/* Request Helpers **********************************************************/ + +static void stm32_copytopma(const uint8_t *buffer, + uint16_t pma, uint16_t nbytes); +static inline void stm32_copyfrompma(uint8_t *buffer, + uint16_t pma, uint16_t nbytes); +static struct stm32_req_s * stm32_rqdequeue(struct stm32_ep_s *privep); +static void stm32_rqenqueue(struct stm32_ep_s *privep, + struct stm32_req_s *req); +static inline void stm32_abortrequest(struct stm32_ep_s *privep, + struct stm32_req_s *privreq, + int16_t result); +static void stm32_reqcomplete(struct stm32_ep_s *privep, int16_t result); +static void stm32_epwrite(struct stm32_usbdev_s *buf, + struct stm32_ep_s *privep, + const uint8_t *data, uint32_t nbytes); +static int stm32_wrrequest(struct stm32_usbdev_s *priv, + struct stm32_ep_s *privep); +inline static int stm32_wrrequest_ep0(struct stm32_usbdev_s *priv, + struct stm32_ep_s *privep); +static inline int stm32_ep0_rdrequest(struct stm32_usbdev_s *priv); +static int stm32_rdrequest(struct stm32_usbdev_s *priv, + struct stm32_ep_s *privep); +static void stm32_cancelrequests(struct stm32_ep_s *privep); + +/* Interrupt level processing ***********************************************/ + +static void stm32_dispatchrequest(struct stm32_usbdev_s *priv); +static void stm32_epdone(struct stm32_usbdev_s *priv, uint8_t epno); +static void stm32_setdevaddr(struct stm32_usbdev_s *priv, uint8_t value); +static void stm32_ep0setup(struct stm32_usbdev_s *priv); +static void stm32_ep0out(struct stm32_usbdev_s *priv); +static void stm32_ep0in(struct stm32_usbdev_s *priv); +static inline void + stm32_ep0done(struct stm32_usbdev_s *priv, uint16_t istr); +static void stm32_lptransfer(struct stm32_usbdev_s *priv); +static int stm32_usb_interrupt(int irq, void *context, void *arg); + +/* Endpoint helpers *********************************************************/ + +static inline struct stm32_ep_s * + stm32_epreserve(struct stm32_usbdev_s *priv, uint8_t epset); +static inline void + stm32_epunreserve(struct stm32_usbdev_s *priv, + struct stm32_ep_s *privep); +static inline bool + stm32_epreserved(struct stm32_usbdev_s *priv, int epno); +static int stm32_epallocpma(struct stm32_usbdev_s *priv); +static inline void + stm32_epfreepma(struct stm32_usbdev_s *priv, + struct stm32_ep_s *privep); + +/* Endpoint operations ******************************************************/ + +static int stm32_epconfigure(struct usbdev_ep_s *ep, + const struct usb_epdesc_s *desc, bool last); +static int stm32_epdisable(struct usbdev_ep_s *ep); +static struct usbdev_req_s * + stm32_epallocreq(struct usbdev_ep_s *ep); +static void stm32_epfreereq(struct usbdev_ep_s *ep, + struct usbdev_req_s *); +static int stm32_epsubmit(struct usbdev_ep_s *ep, + struct usbdev_req_s *req); +static int stm32_epcancel(struct usbdev_ep_s *ep, + struct usbdev_req_s *req); +static int stm32_epstall(struct usbdev_ep_s *ep, bool resume); + +/* USB device controller operations *****************************************/ + +static struct usbdev_ep_s * + stm32_allocep(struct usbdev_s *dev, uint8_t epno, bool in, + uint8_t eptype); +static void stm32_freeep(struct usbdev_s *dev, struct usbdev_ep_s *ep); +static int stm32_getframe(struct usbdev_s *dev); +static int stm32_wakeup(struct usbdev_s *dev); +static int stm32_selfpowered(struct usbdev_s *dev, bool selfpowered); + +/* Initialization/Reset *****************************************************/ + +static void stm32_reset(struct stm32_usbdev_s *priv); +static void stm32_hwreset(struct stm32_usbdev_s *priv); +static void stm32_hwsetup(struct stm32_usbdev_s *priv); +static void stm32_hwshutdown(struct stm32_usbdev_s *priv); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* Since there is only a single USB interface, all status information can be + * be simply retained in a single global instance. + */ + +static struct stm32_usbdev_s g_usbdev; + +static const struct usbdev_epops_s g_epops = +{ + .configure = stm32_epconfigure, + .disable = stm32_epdisable, + .allocreq = stm32_epallocreq, + .freereq = stm32_epfreereq, + .submit = stm32_epsubmit, + .cancel = stm32_epcancel, + .stall = stm32_epstall, +}; + +static const struct usbdev_ops_s g_devops = +{ + .allocep = stm32_allocep, + .freeep = stm32_freeep, + .getframe = stm32_getframe, + .wakeup = stm32_wakeup, + .selfpowered = stm32_selfpowered, + .pullup = stm32_usbpullup, +}; + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#ifdef CONFIG_USBDEV_TRACE_STRINGS +const struct trace_msg_t g_usb_trace_strings_intdecode[] = +{ + TRACE_STR(STM32_TRACEINTID_CLEARFEATURE), + TRACE_STR(STM32_TRACEINTID_DEVGETSTATUS), + TRACE_STR(STM32_TRACEINTID_DISPATCH), + TRACE_STR(STM32_TRACEINTID_EP0IN), + TRACE_STR(STM32_TRACEINTID_EP0INDONE), + TRACE_STR(STM32_TRACEINTID_EP0OUTDONE), + TRACE_STR(STM32_TRACEINTID_EP0SETUPDONE), + TRACE_STR(STM32_TRACEINTID_EP0SETUPSETADDRESS), + TRACE_STR(STM32_TRACEINTID_EPGETSTATUS), + TRACE_STR(STM32_TRACEINTID_EPINDONE), + TRACE_STR(STM32_TRACEINTID_EPINQEMPTY), + TRACE_STR(STM32_TRACEINTID_EPOUTDONE), + TRACE_STR(STM32_TRACEINTID_EPOUTPENDING), + TRACE_STR(STM32_TRACEINTID_EPOUTQEMPTY), + TRACE_STR(STM32_TRACEINTID_ESOF), + TRACE_STR(STM32_TRACEINTID_GETCONFIG), + TRACE_STR(STM32_TRACEINTID_GETSETDESC), + TRACE_STR(STM32_TRACEINTID_GETSETIF), + TRACE_STR(STM32_TRACEINTID_GETSTATUS), + TRACE_STR(STM32_TRACEINTID_INTERRUPT), + TRACE_STR(STM32_TRACEINTID_IFGETSTATUS), + TRACE_STR(STM32_TRACEINTID_LPCTR), + TRACE_STR(STM32_TRACEINTID_NOSTDREQ), + TRACE_STR(STM32_TRACEINTID_RESET), + TRACE_STR(STM32_TRACEINTID_SETCONFIG), + TRACE_STR(STM32_TRACEINTID_SETFEATURE), + TRACE_STR(STM32_TRACEINTID_SUSP), + TRACE_STR(STM32_TRACEINTID_SYNCHFRAME), + TRACE_STR(STM32_TRACEINTID_WKUP), + TRACE_STR(STM32_TRACEINTID_EP0SETUPOUT), + TRACE_STR(STM32_TRACEINTID_EP0SETUPOUTDATA), + TRACE_STR_END +}; +#endif + +#ifdef CONFIG_USBDEV_TRACE_STRINGS +const struct trace_msg_t g_usb_trace_strings_deverror[] = +{ + TRACE_STR(STM32_TRACEERR_ALLOCFAIL), + TRACE_STR(STM32_TRACEERR_BADCLEARFEATURE), + TRACE_STR(STM32_TRACEERR_BADDEVGETSTATUS), + TRACE_STR(STM32_TRACEERR_BADEPGETSTATUS), + TRACE_STR(STM32_TRACEERR_BADEPNO), + TRACE_STR(STM32_TRACEERR_BADEPTYPE), + TRACE_STR(STM32_TRACEERR_BADGETCONFIG), + TRACE_STR(STM32_TRACEERR_BADGETSETDESC), + TRACE_STR(STM32_TRACEERR_BADGETSTATUS), + TRACE_STR(STM32_TRACEERR_BADSETADDRESS), + TRACE_STR(STM32_TRACEERR_BADSETCONFIG), + TRACE_STR(STM32_TRACEERR_BADSETFEATURE), + TRACE_STR(STM32_TRACEERR_BINDFAILED), + TRACE_STR(STM32_TRACEERR_DISPATCHSTALL), + TRACE_STR(STM32_TRACEERR_DRIVER), + TRACE_STR(STM32_TRACEERR_DRIVERREGISTERED), + TRACE_STR(STM32_TRACEERR_EP0BADCTR), + TRACE_STR(STM32_TRACEERR_EP0SETUPSTALLED), + TRACE_STR(STM32_TRACEERR_EPBUFFER), + TRACE_STR(STM32_TRACEERR_EPDISABLED), + TRACE_STR(STM32_TRACEERR_EPOUTNULLPACKET), + TRACE_STR(STM32_TRACEERR_EPRESERVE), + TRACE_STR(STM32_TRACEERR_INVALIDCTRLREQ), + TRACE_STR(STM32_TRACEERR_INVALIDPARMS), + TRACE_STR(STM32_TRACEERR_IRQREGISTRATION), + TRACE_STR(STM32_TRACEERR_NOTCONFIGURED), + TRACE_STR(STM32_TRACEERR_REQABORTED), + TRACE_STR_END +}; +#endif + +/**************************************************************************** + * Private Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Register Operations + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_getreg + ****************************************************************************/ + +#ifdef CONFIG_STM32_USBDEV_REGDEBUG +static uint16_t stm32_getreg(uint32_t addr) +{ + static uint32_t prevaddr = 0; + static uint16_t preval = 0; + static uint32_t count = 0; + + /* Read the value from the register */ + + uint16_t val = getreg16(addr); + + /* Is this the same value that we read from the same register last time? + * Are we polling the register? If so, suppress some of the output. + */ + + if (addr == prevaddr && val == preval) + { + if (count == 0xffffffff || ++count > 3) + { + if (count == 4) + { + uinfo("...\n"); + } + return val; + } + } + + /* No this is a new address or value */ + + else + { + /* Did we print "..." for the previous value? */ + + if (count > 3) + { + /* Yes.. then show how many times the value repeated */ + + uinfo("[repeats %d more times]\n", count - 3); + } + + /* Save the new address, value, and count */ + + prevaddr = addr; + preval = val; + count = 1; + } + + /* Show the register value read */ + + uinfo("%08" PRIx32 "->%04x\n", addr, val); + return val; +} +#endif + +/**************************************************************************** + * Name: stm32_putreg + ****************************************************************************/ + +#ifdef CONFIG_STM32_USBDEV_REGDEBUG +static void stm32_putreg(uint16_t val, uint32_t addr) +{ + /* Show the register value being written */ + + uinfo("%08" PRIx32 "<-%04x\n", addr, val); + + /* Write the value */ + + putreg16(val, addr); +} +#endif + +/**************************************************************************** + * Name: stm32_dumpep + ****************************************************************************/ + +#ifdef CONFIG_STM32_USBDEV_REGDEBUG +static void stm32_dumpep(int epno) +{ + uint32_t addr; + + /* Common registers */ + + uinfo("CNTR: %04x\n", getreg16(STM32_USB_CNTR)); + uinfo("ISTR: %04x\n", getreg16(STM32_USB_ISTR)); + uinfo("FNR: %04x\n", getreg16(STM32_USB_FNR)); + uinfo("DADDR: %04x\n", getreg16(STM32_USB_DADDR)); + uinfo("BTABLE: %04x\n", getreg16(STM32_USB_BTABLE)); + + /* Endpoint register */ + + addr = STM32_USB_EPR(epno); + uinfo("EPR%d: [%08" PRIx32 "] %04x\n", epno, addr, getreg16(addr)); + + /* Endpoint descriptor */ + + addr = STM32_USB_BTABLE_ADDR(epno, 0); + uinfo("DESC: %08" PRIx32 "\n", addr); + + /* Endpoint buffer descriptor */ + + addr = STM32_USB_ADDR_TX(epno); + uinfo(" TX ADDR: [%08" PRIx32 "] %04x\n", addr, getreg16(addr)); + + addr = STM32_USB_COUNT_TX(epno); + uinfo(" COUNT: [%08" PRIx32 "] %04x\n", addr, getreg16(addr)); + + addr = STM32_USB_ADDR_RX(epno); + uinfo(" RX ADDR: [%08" PRIx32 "] %04x\n", addr, getreg16(addr)); + + addr = STM32_USB_COUNT_RX(epno); + uinfo(" COUNT: [%08" PRIx32 "] %04x\n", addr, getreg16(addr)); +} +#endif + +/**************************************************************************** + * Low-Level Helpers + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_seteptxcount + ****************************************************************************/ + +static inline void stm32_seteptxcount(uint8_t epno, uint16_t count) +{ + volatile uint32_t *epaddr = (uint32_t *)STM32_USB_COUNT_TX(epno); + *epaddr = count; +} + +/**************************************************************************** + * Name: stm32_seteptxaddr + ****************************************************************************/ + +static inline void stm32_seteptxaddr(uint8_t epno, uint16_t addr) +{ + volatile uint32_t *txaddr = (uint32_t *)STM32_USB_ADDR_TX(epno); + *txaddr = addr; +} + +/**************************************************************************** + * Name: stm32_geteptxaddr + ****************************************************************************/ + +static inline uint16_t stm32_geteptxaddr(uint8_t epno) +{ + volatile uint32_t *txaddr = (uint32_t *)STM32_USB_ADDR_TX(epno); + return (uint16_t)*txaddr; +} + +/**************************************************************************** + * Name: stm32_seteprxcount + ****************************************************************************/ + +static void stm32_seteprxcount(uint8_t epno, uint16_t count) +{ + volatile uint32_t *epaddr = (uint32_t *)STM32_USB_COUNT_RX(epno); + uint32_t rxcount = 0; + uint16_t nblocks; + + /* The upper bits of the RX COUNT value contain the size of allocated + * RX buffer. This is based on a block size of 2 or 32: + * + * USB_COUNT_RX_BL_SIZE not set: + * nblocks is in units of 2 bytes. + * 00000 - not allowed + * 00001 - 2 bytes + * .... + * 11111 - 62 bytes + * + * USB_COUNT_RX_BL_SIZE set: + * 00000 - 32 bytes + * 00001 - 64 bytes + * ... + * 01111 - 512 bytes + * 1xxxx - Not allowed + */ + + if (count > 62) + { + /* Blocks of 32 (with 0 meaning one block of 32) */ + + nblocks = (count >> 5) - 1 ; + DEBUGASSERT(nblocks <= 0x0f); + rxcount = (uint32_t)((nblocks << + USB_COUNT_RX_NUM_BLOCK_SHIFT) | + USB_COUNT_RX_BL_SIZE); + } + else if (count > 0) + { + /* Blocks of 2 (with 1 meaning one block of 2) */ + + nblocks = (count + 1) >> 1; + DEBUGASSERT(nblocks > 0 && nblocks < 0x1f); + rxcount = (uint32_t)(nblocks << USB_COUNT_RX_NUM_BLOCK_SHIFT); + } + *epaddr = rxcount; +} + +/**************************************************************************** + * Name: stm32_geteprxcount + ****************************************************************************/ + +static inline uint16_t stm32_geteprxcount(uint8_t epno) +{ + volatile uint32_t *epaddr = (uint32_t *)STM32_USB_COUNT_RX(epno); + return (*epaddr) & USB_COUNT_RX_MASK; +} + +/**************************************************************************** + * Name: stm32_seteprxaddr + ****************************************************************************/ + +static inline void stm32_seteprxaddr(uint8_t epno, uint16_t addr) +{ + volatile uint32_t *rxaddr = (uint32_t *)STM32_USB_ADDR_RX(epno); + *rxaddr = addr; +} + +/**************************************************************************** + * Name: stm32_seteprxaddr + ****************************************************************************/ + +static inline uint16_t stm32_geteprxaddr(uint8_t epno) +{ + volatile uint32_t *rxaddr = (uint32_t *)STM32_USB_ADDR_RX(epno); + return (uint16_t)*rxaddr; +} + +/**************************************************************************** + * Name: stm32_setepaddress + ****************************************************************************/ + +static inline void stm32_setepaddress(uint8_t epno, uint16_t addr) +{ + uint32_t epaddr = STM32_USB_EPR(epno); + uint16_t regval; + + regval = stm32_getreg(epaddr); + regval &= EPR_NOTOG_MASK; + regval &= ~USB_EPR_EA_MASK; + regval |= (addr << USB_EPR_EA_SHIFT); + stm32_putreg(regval, epaddr); +} + +/**************************************************************************** + * Name: stm32_seteptype + ****************************************************************************/ + +static inline void stm32_seteptype(uint8_t epno, uint16_t type) +{ + uint32_t epaddr = STM32_USB_EPR(epno); + uint16_t regval; + + regval = stm32_getreg(epaddr); + regval &= EPR_NOTOG_MASK; + regval &= ~USB_EPR_EPTYPE_MASK; + regval |= type; + stm32_putreg(regval, epaddr); +} + +/**************************************************************************** + * Name: stm32_clrstatusout + ****************************************************************************/ + +static inline void stm32_clrstatusout(uint8_t epno) +{ + uint32_t epaddr = STM32_USB_EPR(epno); + uint16_t regval; + + /* For a BULK endpoint the EP_KIND bit is used to enabled double buffering; + * for a CONTROL endpoint, it is set to indicate that a status OUT + * transaction is expected. The bit is not used with out endpoint types. + */ + + regval = stm32_getreg(epaddr); + regval &= EPR_NOTOG_MASK; + regval &= ~USB_EPR_EP_KIND; + stm32_putreg(regval, epaddr); +} + +/**************************************************************************** + * Name: stm32_clrrxdtog + ****************************************************************************/ + +static void stm32_clrrxdtog(uint8_t epno) +{ + uint32_t epaddr = STM32_USB_EPR(epno); + uint16_t regval; + + regval = stm32_getreg(epaddr); + if ((regval & USB_EPR_DTOG_RX) != 0) + { + regval &= EPR_NOTOG_MASK; + regval |= USB_EPR_DTOG_RX; + stm32_putreg(regval, epaddr); + } +} + +/**************************************************************************** + * Name: stm32_clrtxdtog + ****************************************************************************/ + +static void stm32_clrtxdtog(uint8_t epno) +{ + uint32_t epaddr = STM32_USB_EPR(epno); + uint16_t regval; + + regval = stm32_getreg(epaddr); + if ((regval & USB_EPR_DTOG_TX) != 0) + { + regval &= EPR_NOTOG_MASK; + regval |= USB_EPR_DTOG_TX; + stm32_putreg(regval, epaddr); + } +} + +/**************************************************************************** + * Name: stm32_clrepctrrx + ****************************************************************************/ + +static void stm32_clrepctrrx(uint8_t epno) +{ + uint32_t epaddr = STM32_USB_EPR(epno); + uint16_t regval; + + regval = stm32_getreg(epaddr); + regval &= EPR_NOTOG_MASK; + regval &= ~USB_EPR_CTR_RX; + stm32_putreg(regval, epaddr); +} + +/**************************************************************************** + * Name: stm32_clrepctrtx + ****************************************************************************/ + +static void stm32_clrepctrtx(uint8_t epno) +{ + uint32_t epaddr = STM32_USB_EPR(epno); + uint16_t regval; + + regval = stm32_getreg(epaddr); + regval &= EPR_NOTOG_MASK; + regval &= ~USB_EPR_CTR_TX; + stm32_putreg(regval, epaddr); +} + +/**************************************************************************** + * Name: stm32_geteptxstatus + ****************************************************************************/ + +static inline uint16_t stm32_geteptxstatus(uint8_t epno) +{ + return (uint16_t)(stm32_getreg(STM32_USB_EPR(epno)) & + USB_EPR_STATTX_MASK); +} + +/**************************************************************************** + * Name: stm32_geteprxstatus + ****************************************************************************/ + +static inline uint16_t stm32_geteprxstatus(uint8_t epno) +{ + return (stm32_getreg(STM32_USB_EPR(epno)) & USB_EPR_STATRX_MASK); +} + +/**************************************************************************** + * Name: stm32_seteptxstatus + ****************************************************************************/ + +static void stm32_seteptxstatus(uint8_t epno, uint16_t state) +{ + uint32_t epaddr = STM32_USB_EPR(epno); + uint16_t regval; + + /* The bits in the STAT_TX field can be toggled by software to set their + * value. When set to 0, the value remains unchanged; when set to one, + * value toggles. + */ + + regval = stm32_getreg(epaddr); + + /* The exclusive OR will set STAT_TX bits to 1 if there value is + * different from the bits requested in 'state' + */ + + regval ^= state; + regval &= EPR_TXDTOG_MASK; + stm32_putreg(regval, epaddr); +} + +/**************************************************************************** + * Name: stm32_seteprxstatus + ****************************************************************************/ + +static void stm32_seteprxstatus(uint8_t epno, uint16_t state) +{ + uint32_t epaddr = STM32_USB_EPR(epno); + uint16_t regval; + + /* The bits in the STAT_RX field can be toggled by software to set their + * value. When set to 0, the value remains unchanged; when set to one, + * value toggles. + */ + + regval = stm32_getreg(epaddr); + + /* The exclusive OR will set STAT_RX bits to 1 if there value is + * different from the bits requested in 'state' + */ + + regval ^= state; + regval &= EPR_RXDTOG_MASK; + stm32_putreg(regval, epaddr); +} + +/**************************************************************************** + * Name: stm32_eptxstalled + ****************************************************************************/ + +static inline bool stm32_eptxstalled(uint8_t epno) +{ + return (stm32_geteptxstatus(epno) == USB_EPR_STATTX_STALL); +} + +/**************************************************************************** + * Name: stm32_eprxstalled + ****************************************************************************/ + +static inline bool stm32_eprxstalled(uint8_t epno) +{ + return (stm32_geteprxstatus(epno) == USB_EPR_STATRX_STALL); +} + +/**************************************************************************** + * Request Helpers + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_copytopma + ****************************************************************************/ + +static void stm32_copytopma(const uint8_t *buffer, + uint16_t pma, uint16_t nbytes) +{ + uint16_t *dest; + uint16_t ms; + uint16_t ls; + int nwords = (nbytes + 1) >> 1; + int i; + + /* Copy loop. Source=user buffer, Dest=packet memory */ + + dest = (uint16_t *)(STM32_USBRAM_BASE + ((uint32_t)pma << 1)); + for (i = nwords; i != 0; i--) + { + /* Read two bytes and pack into on 16-bit word */ + + ls = (uint16_t)(*buffer++); + ms = (uint16_t)(*buffer++); + *dest = ms << 8 | ls; + + /* Source address increments by 2*sizeof(uint8_t) = 2; Dest address + * increments by 2*sizeof(uint16_t) = 4. + */ + + dest += 2; + } +} + +/**************************************************************************** + * Name: stm32_copyfrompma + ****************************************************************************/ + +static inline void +stm32_copyfrompma(uint8_t *buffer, uint16_t pma, uint16_t nbytes) +{ + uint32_t *src; + int nwords = (nbytes + 1) >> 1; + int i; + + /* Copy loop. Source=packet memory, Dest=user buffer */ + + src = (uint32_t *)(STM32_USBRAM_BASE + ((uint32_t)pma << 1)); + for (i = nwords; i != 0; i--) + { + /* Copy 16-bits from packet memory to user buffer. */ + + *(uint16_t *)buffer = *src++; + + /* Source address increments by 1*sizeof(uint32_t) = 4; Dest address + * increments by 2*sizeof(uint8_t) = 2. + */ + + buffer += 2; + } +} + +/**************************************************************************** + * Name: stm32_rqdequeue + ****************************************************************************/ + +static struct stm32_req_s *stm32_rqdequeue(struct stm32_ep_s *privep) +{ + struct stm32_req_s *ret = privep->head; + + if (ret) + { + privep->head = ret->flink; + if (!privep->head) + { + privep->tail = NULL; + } + + ret->flink = NULL; + } + + return ret; +} + +/**************************************************************************** + * Name: stm32_rqenqueue + ****************************************************************************/ + +static void stm32_rqenqueue(struct stm32_ep_s *privep, + struct stm32_req_s *req) +{ + req->flink = NULL; + if (!privep->head) + { + privep->head = req; + privep->tail = req; + } + else + { + privep->tail->flink = req; + privep->tail = req; + } +} + +/**************************************************************************** + * Name: stm32_abortrequest + ****************************************************************************/ + +static inline void +stm32_abortrequest(struct stm32_ep_s *privep, + struct stm32_req_s *privreq, + int16_t result) +{ + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_REQABORTED), + (uint16_t)USB_EPNO(privep->ep.eplog)); + + /* Save the result in the request structure */ + + privreq->req.result = result; + + /* Callback to the request completion handler */ + + privreq->req.callback(&privep->ep, &privreq->req); +} + +/**************************************************************************** + * Name: stm32_reqcomplete + ****************************************************************************/ + +static void stm32_reqcomplete(struct stm32_ep_s *privep, int16_t result) +{ + struct stm32_req_s *privreq; + irqstate_t flags; + + /* Remove the completed request at the head of the endpoint request list */ + + flags = enter_critical_section(); + privreq = stm32_rqdequeue(privep); + leave_critical_section(flags); + + if (privreq) + { + /* If endpoint 0, temporarily reflect the state of protocol stalled + * in the callback. + */ + + bool stalled = privep->stalled; + if (USB_EPNO(privep->ep.eplog) == EP0) + { + privep->stalled = (privep->dev->ep0state == EP0STATE_STALLED); + } + + /* Save the result in the request structure */ + + privreq->req.result = result; + + /* Callback to the request completion handler */ + + privreq->flink = NULL; + privreq->req.callback(&privep->ep, &privreq->req); + + /* Restore the stalled indication */ + + privep->stalled = stalled; + } +} + +/**************************************************************************** + * Name: tm32_epwrite + ****************************************************************************/ + +static void stm32_epwrite(struct stm32_usbdev_s *priv, + struct stm32_ep_s *privep, + const uint8_t *buf, uint32_t nbytes) +{ + uint8_t epno = USB_EPNO(privep->ep.eplog); + usbtrace(TRACE_WRITE(epno), nbytes); + + /* Check for a zero-length packet */ + + if (nbytes > 0) + { + /* Copy the data from the user buffer into packet memory for this + * endpoint + */ + + stm32_copytopma(buf, stm32_geteptxaddr(epno), nbytes); + } + + /* Send the packet (might be a null packet nbytes == 0) */ + + stm32_seteptxcount(epno, nbytes); + priv->txstatus = USB_EPR_STATTX_VALID; + + /* Indicate that there is data in the TX packet memory. + * This will be cleared when the next data out interrupt is received. + */ + + privep->txbusy = true; +} + +/**************************************************************************** + * Name: stm32_wrrequest_ep0 + * + * Description: + * Handle the ep0 state on writes. + * + ****************************************************************************/ + +inline static int stm32_wrrequest_ep0(struct stm32_usbdev_s *priv, + struct stm32_ep_s *privep) +{ + int ret; + ret = stm32_wrrequest(priv, privep); + priv->ep0state = ((ret == OK) ? EP0STATE_WRREQUEST : EP0STATE_IDLE); + return ret; +} + +/**************************************************************************** + * Name: stm32_wrrequest + ****************************************************************************/ + +static int stm32_wrrequest(struct stm32_usbdev_s *priv, + struct stm32_ep_s *privep) +{ + struct stm32_req_s *privreq; + uint8_t *buf; + uint8_t epno; + int nbytes; + int bytesleft; + + /* We get here when an IN endpoint interrupt occurs. So now we know that + * there is no TX transfer in progress. + */ + + privep->txbusy = false; + + /* Check the request from the head of the endpoint request queue */ + + privreq = stm32_rqpeek(privep); + if (!privreq) + { + /* There is no TX transfer in progress and no new pending TX + * requests to send. + */ + + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPINQEMPTY), 0); + return -ENOENT; + } + + epno = USB_EPNO(privep->ep.eplog); + uinfo("epno=%d req=%p: len=%zu xfrd=%zu nullpkt=%d\n", + epno, privreq, privreq->req.len, + privreq->req.xfrd, privep->txnullpkt); + UNUSED(epno); + + /* Get the number of bytes left to be sent in the packet */ + + bytesleft = privreq->req.len - privreq->req.xfrd; + nbytes = bytesleft; + +#warning "REVISIT: If the EP supports double buffering, then we can do better" + + /* Either + * (1) we are committed to sending the null packet + * (because txnullpkt == 1 && nbytes == 0), or + * (2) we have not yet send the last packet (nbytes > 0). + * In either case, it is appropriate to clearn txnullpkt now. + */ + + privep->txnullpkt = 0; + + /* If we are not sending a NULL packet, then clip the size to maxpacket + * and check if we need to send a following NULL packet. + */ + + if (nbytes > 0) + { + /* Either send the maxpacketsize or all of the remaining data in + * the request. + */ + + if (nbytes >= privep->ep.maxpacket) + { + nbytes = privep->ep.maxpacket; + + /* Handle the case where this packet is exactly the + * maxpacketsize. Do we need to send a zero-length packet + * in this case? + */ + + if (bytesleft == privep->ep.maxpacket && + (privreq->req.flags & USBDEV_REQFLAGS_NULLPKT) != 0) + { + privep->txnullpkt = 1; + } + } + } + + /* Send the packet (might be a null packet nbytes == 0) */ + + buf = privreq->req.buf + privreq->req.xfrd; + stm32_epwrite(priv, privep, buf, nbytes); + + /* Update for the next data IN interrupt */ + + privreq->req.xfrd += nbytes; + bytesleft = privreq->req.len - privreq->req.xfrd; + + /* If all of the bytes were sent (including any final null packet) + * then we are finished with the request buffer). + */ + + if (bytesleft == 0 && !privep->txnullpkt) + { + /* Return the write request to the class driver */ + + usbtrace(TRACE_COMPLETE(USB_EPNO(privep->ep.eplog)), + privreq->req.xfrd); + privep->txnullpkt = 0; + stm32_reqcomplete(privep, OK); + } + + return OK; +} + +/**************************************************************************** + * Name: stm32_ep0_rdrequest + * + * Description: + * This function is called from the stm32_ep0out handler when the ep0state + * is EP0STATE_SETUP_OUT and upon new incoming data is available in the + * endpoint 0's buffer. + * This function will simply copy the OUT data into ep0data. + * + ****************************************************************************/ + +static inline int stm32_ep0_rdrequest(struct stm32_usbdev_s *priv) +{ + uint32_t src; + int pmalen; + int readlen; + + /* Get the number of bytes to read from packet memory */ + + pmalen = stm32_geteprxcount(EP0); + + uinfo("EP0: pmalen=%d\n", pmalen); + usbtrace(TRACE_READ(EP0), pmalen); + + /* Read the data into our special buffer for SETUP data */ + + readlen = MIN(CONFIG_USBDEV_SETUP_MAXDATASIZE, pmalen); + src = stm32_geteprxaddr(EP0); + + /* Receive the next packet */ + + stm32_copyfrompma(&priv->ep0data[0], src, readlen); + + /* Now we can process the setup command */ + + priv->ep0state = EP0STATE_SETUP_READY; + priv->ep0datlen = readlen; + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EP0SETUPOUTDATA), readlen); + + stm32_ep0setup(priv); + priv->ep0datlen = 0; /* mark the date consumed */ + + return OK; +} + +/**************************************************************************** + * Name: stm32_rdrequest + ****************************************************************************/ + +static int stm32_rdrequest(struct stm32_usbdev_s *priv, + struct stm32_ep_s *privep) +{ + struct stm32_req_s *privreq; + uint32_t src; + uint8_t *dest; + uint8_t epno; + int pmalen; + int readlen; + + /* Check the request from the head of the endpoint request queue */ + + epno = USB_EPNO(privep->ep.eplog); + privreq = stm32_rqpeek(privep); + if (!privreq) + { + /* Incoming data available in PMA, but no packet to receive the data. + * Mark that the RX data is pending and hope that a packet is returned + * soon. + */ + + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPOUTQEMPTY), epno); + return -ENOENT; + } + + uinfo("EP%d: len=%zu xfrd=%zu\n", + epno, privreq->req.len, privreq->req.xfrd); + + /* Ignore any attempt to receive a zero length packet */ + + if (privreq->req.len == 0) + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EPOUTNULLPACKET), 0); + stm32_reqcomplete(privep, OK); + return OK; + } + + usbtrace(TRACE_READ(USB_EPNO(privep->ep.eplog)), privreq->req.xfrd); + + /* Get the source and destination transfer addresses */ + + dest = privreq->req.buf + privreq->req.xfrd; + src = stm32_geteprxaddr(epno); + + /* Get the number of bytes to read from packet memory */ + + pmalen = stm32_geteprxcount(epno); + readlen = MIN(privreq->req.len, pmalen); + + /* Receive the next packet */ + + stm32_copyfrompma(dest, src, readlen); + + /* If the receive buffer is full or this is a partial packet, + * then we are finished with the request buffer). + */ + + privreq->req.xfrd += readlen; + if (pmalen < privep->ep.maxpacket || privreq->req.xfrd >= privreq->req.len) + { + /* Return the read request to the class driver. */ + + usbtrace(TRACE_COMPLETE(epno), privreq->req.xfrd); + stm32_reqcomplete(privep, OK); + } + + return OK; +} + +/**************************************************************************** + * Name: stm32_cancelrequests + ****************************************************************************/ + +static void stm32_cancelrequests(struct stm32_ep_s *privep) +{ + while (!stm32_rqempty(privep)) + { + usbtrace(TRACE_COMPLETE(USB_EPNO(privep->ep.eplog)), + (stm32_rqpeek(privep))->req.xfrd); + stm32_reqcomplete(privep, -ESHUTDOWN); + } +} + +/**************************************************************************** + * Interrupt Level Processing + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_dispatchrequest + ****************************************************************************/ + +static void stm32_dispatchrequest(struct stm32_usbdev_s *priv) +{ + int ret; + + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_DISPATCH), 0); + if (priv && priv->driver) + { + /* Forward to the control request to the class driver implementation */ + + ret = CLASS_SETUP(priv->driver, &priv->usbdev, &priv->ctrl, + priv->ep0data, priv->ep0datlen); + if (ret < 0) + { + /* Stall on failure */ + + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_DISPATCHSTALL), 0); + priv->ep0state = EP0STATE_STALLED; + } + } +} + +/**************************************************************************** + * Name: stm32_epdone + ****************************************************************************/ + +static void stm32_epdone(struct stm32_usbdev_s *priv, uint8_t epno) +{ + struct stm32_ep_s *privep; + uint16_t epr; + + /* Decode and service non control endpoints interrupt */ + + epr = stm32_getreg(STM32_USB_EPR(epno)); + privep = &priv->eplist[epno]; + + /* OUT: host-to-device + * CTR_RX is set by the hardware when an OUT/SETUP transaction + * successfully completed on this endpoint. + */ + + if ((epr & USB_EPR_CTR_RX) != 0) + { + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPOUTDONE), epr); + + /* Handle read requests. First check if a read request is available to + * accept the host data. + */ + + if (!stm32_rqempty(privep)) + { + /* Read host data into the current read request */ + + stm32_rdrequest(priv, privep); + + /* "After the received data is processed, the application software + * should set the STAT_RX bits to '11' (Valid) in the USB_EPnR, + * enabling further transactions. " + */ + + priv->rxstatus = USB_EPR_STATRX_VALID; + } + + /* NAK further OUT packets if there there no more read requests */ + + if (stm32_rqempty(privep)) + { + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPOUTPENDING), + (uint16_t)epno); + + /* Mark the RX processing as pending and NAK any OUT actions + * on this endpoint. "While the STAT_RX bits are equal to '10' + * (NAK), any OUT request addressed to that endpoint is NAKed, + * indicating a flow control condition: the USB host will retry + * the transaction until it succeeds." + */ + + priv->rxstatus = USB_EPR_STATRX_NAK; + priv->rxpending = true; + } + + /* Clear the interrupt status and set the new RX status */ + + stm32_clrepctrrx(epno); + stm32_seteprxstatus(epno, priv->rxstatus); + } + + /* IN: device-to-host + * CTR_TX is set when an IN transaction successfully completes on + * an endpoint + */ + + else if ((epr & USB_EPR_CTR_TX) != 0) + { + /* Clear interrupt status */ + + stm32_clrepctrtx(epno); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPINDONE), epr); + + /* Handle write requests */ + + priv->txstatus = USB_EPR_STATTX_NAK; + if (epno == EP0) + { + stm32_wrrequest_ep0(priv, privep); + } + else + { + stm32_wrrequest(priv, privep); + } + + /* Set the new TX status */ + + stm32_seteptxstatus(epno, priv->txstatus); + } +} + +/**************************************************************************** + * Name: stm32_setdevaddr + ****************************************************************************/ + +static void stm32_setdevaddr(struct stm32_usbdev_s *priv, uint8_t value) +{ + int epno; + + /* Set address in every allocated endpoint */ + + for (epno = 0; epno < STM32_NENDPOINTS; epno++) + { + if (stm32_epreserved(priv, epno)) + { + stm32_setepaddress((uint8_t)epno, (uint8_t)epno); + } + } + + /* Set the device address and enable function */ + + stm32_putreg(value | USB_DADDR_EF, STM32_USB_DADDR); +} + +/**************************************************************************** + * Name: stm32_ep0setup + ****************************************************************************/ + +static void stm32_ep0setup(struct stm32_usbdev_s *priv) +{ + struct stm32_ep_s *ep0 = &priv->eplist[EP0]; + struct stm32_req_s *privreq = stm32_rqpeek(ep0); + struct stm32_ep_s *privep; + union wb_u value; + union wb_u index; + union wb_u len; + union wb_u response; + bool handled = false; + uint8_t epno; + int nbytes = 0; /* Assume zero-length packet */ + + /* Terminate any pending requests (doesn't work if the pending request + * was a zero-length transfer!) + */ + + while (!stm32_rqempty(ep0)) + { + int16_t result = OK; + if (privreq->req.xfrd != privreq->req.len) + { + result = -EPROTO; + } + + usbtrace(TRACE_COMPLETE(ep0->ep.eplog), privreq->req.xfrd); + stm32_reqcomplete(ep0, result); + } + + /* Assume NOT stalled; no TX in progress */ + + ep0->stalled = 0; + ep0->txbusy = 0; + + /* Check to see if called from the DATA phase of a SETUP Transfer */ + + if (priv->ep0state != EP0STATE_SETUP_READY) + { + /* Not the data phase */ + + /* Get a 32-bit PMA address and use that to get the 8-byte setup + * request + */ + + stm32_copyfrompma((uint8_t *)&priv->ctrl, stm32_geteprxaddr(EP0), + USB_SIZEOF_CTRLREQ); + + /* And extract the little-endian 16-bit values to host order */ + + value.w = GETUINT16(priv->ctrl.value); + index.w = GETUINT16(priv->ctrl.index); + len.w = GETUINT16(priv->ctrl.len); + + uinfo("SETUP: type=%02x req=%02x value=%04x index=%04x len=%04x\n", + priv->ctrl.type, priv->ctrl.req, value.w, index.w, len.w); + + /* Is this an setup with OUT and data of length > 0 */ + + if (USB_REQ_ISOUT(priv->ctrl.type) && len.w > 0) + { + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EP0SETUPOUT), len.w); + + /* At this point priv->ctrl is the setup packet. */ + + priv->ep0state = EP0STATE_SETUP_OUT; + return; + } + else + { + priv->ep0state = EP0STATE_SETUP_READY; + } + } + + /* Dispatch any non-standard requests */ + + if ((priv->ctrl.type & USB_REQ_TYPE_MASK) != USB_REQ_TYPE_STANDARD) + { + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_NOSTDREQ), priv->ctrl.type); + + /* Let the class implementation handle all non-standar requests */ + + stm32_dispatchrequest(priv); + return; + } + + /* Handle standard request. Pick off the things of interest to the + * USB device controller driver; pass what is left to the class driver + */ + + switch (priv->ctrl.req) + { + case USB_REQ_GETSTATUS: + { + /* type: device-to-host; recipient = device, interface, endpoint + * value: 0 + * index: zero interface endpoint + * len: 2; data = status + */ + + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_GETSTATUS), + priv->ctrl.type); + if (len.w != 2 || (priv->ctrl.type & USB_REQ_DIR_IN) == 0 || + index.b[MSB] != 0 || value.w != 0) + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADEPGETSTATUS), 0); + priv->ep0state = EP0STATE_STALLED; + } + else + { + switch (priv->ctrl.type & USB_REQ_RECIPIENT_MASK) + { + case USB_REQ_RECIPIENT_ENDPOINT: + { + epno = USB_EPNO(index.b[LSB]); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPGETSTATUS), + epno); + if (epno >= STM32_NENDPOINTS) + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADEPGETSTATUS), + epno); + priv->ep0state = EP0STATE_STALLED; + } + else + { + response.w = 0; /* Not stalled */ + nbytes = 2; /* Response size: 2 bytes */ + + if (USB_ISEPIN(index.b[LSB])) + { + /* IN endpoint */ + + if (stm32_eptxstalled(epno)) + { + /* IN Endpoint stalled */ + + response.b[LSB] = 1; /* Stalled */ + } + } + else + { + /* OUT endpoint */ + + if (stm32_eprxstalled(epno)) + { + /* OUT Endpoint stalled */ + + response.b[LSB] = 1; /* Stalled */ + } + } + } + } + break; + + case USB_REQ_RECIPIENT_DEVICE: + { + if (index.w == 0) + { + usbtrace(TRACE_INTDECODE( + STM32_TRACEINTID_DEVGETSTATUS), 0); + + /* Features: Remote Wakeup=YES; selfpowered=? */ + + response.w = 0; + response.b[LSB] = (priv->selfpowered << + USB_FEATURE_SELFPOWERED) | + (1 << USB_FEATURE_REMOTEWAKEUP); + nbytes = 2; /* Response size: 2 bytes */ + } + else + { + usbtrace(TRACE_DEVERROR( + STM32_TRACEERR_BADDEVGETSTATUS), 0); + priv->ep0state = EP0STATE_STALLED; + } + } + break; + + case USB_REQ_RECIPIENT_INTERFACE: + { + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_IFGETSTATUS), 0); + response.w = 0; + nbytes = 2; /* Response size: 2 bytes */ + } + break; + + default: + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADGETSTATUS), 0); + priv->ep0state = EP0STATE_STALLED; + } + break; + } + } + } + break; + + case USB_REQ_CLEARFEATURE: + { + /* type: host-to-device; recipient = device, interface or endpoint + * value: feature selector + * index: zero interface endpoint; + * len: zero, data = none + */ + + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_CLEARFEATURE), + priv->ctrl.type); + if ((priv->ctrl.type & USB_REQ_RECIPIENT_MASK) != + USB_REQ_RECIPIENT_ENDPOINT) + { + /* Let the class implementation handle all recipients + * (except for the endpoint recipient) + */ + + stm32_dispatchrequest(priv); + handled = true; + } + else + { + /* Endpoint recipient */ + + epno = USB_EPNO(index.b[LSB]); + if (epno < STM32_NENDPOINTS && index.b[MSB] == 0 && + value.w == USB_FEATURE_ENDPOINTHALT && len.w == 0) + { + privep = &priv->eplist[epno]; + privep->halted = 0; + stm32_epstall(&privep->ep, true); + } + else + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADCLEARFEATURE), 0); + priv->ep0state = EP0STATE_STALLED; + } + } + } + break; + + case USB_REQ_SETFEATURE: + { + /* type: host-to-device; recipient = device, interface, endpoint + * value: feature selector + * index: zero interface endpoint; + * len: 0; data = none + */ + + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SETFEATURE), + priv->ctrl.type); + if (((priv->ctrl.type & USB_REQ_RECIPIENT_MASK) == + USB_REQ_RECIPIENT_DEVICE) && + value.w == USB_FEATURE_TESTMODE) + { + /* Special case recipient=device test mode */ + + uinfo("test mode: %d\n", index.w); + } + else if ((priv->ctrl.type & USB_REQ_RECIPIENT_MASK) != + USB_REQ_RECIPIENT_ENDPOINT) + { + /* The class driver handles all recipients except + * recipient=endpoint + */ + + stm32_dispatchrequest(priv); + handled = true; + } + else + { + /* Handler recipient=endpoint */ + + epno = USB_EPNO(index.b[LSB]); + if (epno < STM32_NENDPOINTS && index.b[MSB] == 0 && + value.w == USB_FEATURE_ENDPOINTHALT && len.w == 0) + { + privep = &priv->eplist[epno]; + privep->halted = 1; + stm32_epstall(&privep->ep, false); + } + else + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADSETFEATURE), 0); + priv->ep0state = EP0STATE_STALLED; + } + } + } + break; + + case USB_REQ_SETADDRESS: + { + /* type: host-to-device; recipient = device + * value: device address + * index: 0 + * len: 0; data = none + */ + + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EP0SETUPSETADDRESS), + value.w); + if ((priv->ctrl.type & USB_REQ_RECIPIENT_MASK) != + USB_REQ_RECIPIENT_DEVICE || + index.w != 0 || len.w != 0 || value.w > 127) + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADSETADDRESS), 0); + priv->ep0state = EP0STATE_STALLED; + } + + /* Note that setting of the device address will be deferred. + * A zero-length packet will be sent and the device address will + * be set when the zero- length packet transfer completes. + */ + } + break; + + case USB_REQ_GETDESCRIPTOR: + /* type: device-to-host; recipient = device + * value: descriptor type and index + * index: 0 or language ID; + * len: descriptor len; data = descriptor + */ + + case USB_REQ_SETDESCRIPTOR: + /* type: host-to-device; recipient = device + * value: descriptor type and index + * index: 0 or language ID; + * len: descriptor len; data = descriptor + */ + + { + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_GETSETDESC), + priv->ctrl.type); + if ((priv->ctrl.type & USB_REQ_RECIPIENT_MASK) == + USB_REQ_RECIPIENT_DEVICE) + { + /* The request seems valid... + * let the class implementation handle it + */ + + stm32_dispatchrequest(priv); + handled = true; + } + else + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADGETSETDESC), 0); + priv->ep0state = EP0STATE_STALLED; + } + } + break; + + case USB_REQ_GETCONFIGURATION: + /* type: device-to-host; recipient = device + * value: 0; + * index: 0; + * len: 1; data = configuration value + */ + + { + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_GETCONFIG), + priv->ctrl.type); + if ((priv->ctrl.type & USB_REQ_RECIPIENT_MASK) == + USB_REQ_RECIPIENT_DEVICE && + value.w == 0 && index.w == 0 && len.w == 1) + { + /* The request seems valid... + * let the class implementation handle it + */ + + stm32_dispatchrequest(priv); + handled = true; + } + else + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADGETCONFIG), 0); + priv->ep0state = EP0STATE_STALLED; + } + } + break; + + case USB_REQ_SETCONFIGURATION: + /* type: host-to-device; recipient = device + * value: configuration value + * index: 0; + * len: 0; data = none + */ + + { + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SETCONFIG), + priv->ctrl.type); + if ((priv->ctrl.type & USB_REQ_RECIPIENT_MASK) == + USB_REQ_RECIPIENT_DEVICE && + index.w == 0 && len.w == 0) + { + /* The request seems valid... + * let the class implementation handle it + */ + + stm32_dispatchrequest(priv); + handled = true; + } + else + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADSETCONFIG), 0); + priv->ep0state = EP0STATE_STALLED; + } + } + break; + + case USB_REQ_GETINTERFACE: + /* type: device-to-host; recipient = interface + * value: 0 + * index: interface; + * len: 1; data = alt interface + */ + + case USB_REQ_SETINTERFACE: + /* type: host-to-device; recipient = interface + * value: alternate setting + * index: interface; + * len: 0; data = none + */ + + { + /* Let the class implementation handle the request */ + + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_GETSETIF), + priv->ctrl.type); + stm32_dispatchrequest(priv); + handled = true; + } + break; + + case USB_REQ_SYNCHFRAME: + /* type: device-to-host; recipient = endpoint + * value: 0 + * index: endpoint; + * len: 2; data = frame number + */ + + { + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SYNCHFRAME), 0); + } + break; + + default: + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDCTRLREQ), + priv->ctrl.req); + priv->ep0state = EP0STATE_STALLED; + } + break; + } + + /* At this point, the request has been handled and there are three + * possible outcomes: + * + * 1. The setup request was successfully handled above and a response + * packet must be sent (may be a zero length packet). + * 2. The request was successfully handled by the class implementation. + * In case, the EP0 IN response has already been queued and the local + * variable 'handled' will be set to true and + * ep0state != EP0STATE_STALLED; + * 3. An error was detected in either the above logic or by the class + * implementation logic. In either case, priv->state will be set + * EP0STATE_STALLED to indicate this case. + * + * NOTE: Non-standard requests are a special case. They are handled by the + * class implementation and this function returned early above, skipping + * this logic altogether. + */ + + if (priv->ep0state != EP0STATE_STALLED && !handled) + { + /* We will response. First, restrict the data length to the length + * requested in the setup packet + */ + + if (nbytes > len.w) + { + nbytes = len.w; + } + + /* Send the response (might be a zero-length packet) */ + + stm32_epwrite(priv, ep0, response.b, nbytes); + priv->ep0state = EP0STATE_IDLE; + } +} + +/**************************************************************************** + * Name: stm32_ep0in + ****************************************************************************/ + +static void stm32_ep0in(struct stm32_usbdev_s *priv) +{ + /* There is no longer anything in the EP0 TX packet memory */ + + priv->eplist[EP0].txbusy = false; + + /* Are we processing the completion of one packet of an outgoing request + * from the class driver? + */ + + if (priv->ep0state == EP0STATE_WRREQUEST) + { + stm32_wrrequest_ep0(priv, &priv->eplist[EP0]); + } + + /* No.. Are we processing the completion of a status response? */ + + else if (priv->ep0state == EP0STATE_IDLE) + { + /* Look at the saved SETUP command. Was it a SET ADDRESS request? + * If so, then now is the time to set the address. + */ + + if (priv->ctrl.req == USB_REQ_SETADDRESS && + (priv->ctrl.type & REQRECIPIENT_MASK) == + (USB_REQ_TYPE_STANDARD | USB_REQ_RECIPIENT_DEVICE)) + { + union wb_u value; + value.w = GETUINT16(priv->ctrl.value); + stm32_setdevaddr(priv, value.b[LSB]); + } + } + else + { + priv->ep0state = EP0STATE_STALLED; + } +} + +/**************************************************************************** + * Name: stm32_ep0out + ****************************************************************************/ + +static void stm32_ep0out(struct stm32_usbdev_s *priv) +{ + int ret; + + struct stm32_ep_s *privep = &priv->eplist[EP0]; + switch (priv->ep0state) + { + case EP0STATE_RDREQUEST: /* Read request in progress */ + case EP0STATE_IDLE: /* No transfer in progress */ + ret = stm32_rdrequest(priv, privep); + priv->ep0state = ((ret == OK) ? EP0STATE_RDREQUEST : EP0STATE_IDLE); + break; + + case EP0STATE_SETUP_OUT: /* SETUP was waiting for data */ + ret = stm32_ep0_rdrequest(priv); /* Off load the data and run the + * last set up command with the OUT + * data + */ + priv->ep0state = EP0STATE_IDLE; /* There is no notion of receiving OUT + * data greater then the length of + * CONFIG_USBDEV_SETUP_MAXDATASIZE + * so we are done + */ + break; + + default: + /* Unexpected state OR host aborted the OUT transfer before it + * completed, STALL the endpoint in either case + */ + + priv->ep0state = EP0STATE_STALLED; + break; + } +} + +/**************************************************************************** + * Name: stm32_ep0done + ****************************************************************************/ + +static inline void stm32_ep0done(struct stm32_usbdev_s *priv, uint16_t istr) +{ + uint16_t epr; + + /* Initialize RX and TX status. We shouldn't have to actually look at the + * status because the hardware is supposed to set the both RX and TX status + * to NAK when an EP0 SETUP occurs (of course, this might not be a setup) + */ + + priv->rxstatus = USB_EPR_STATRX_NAK; + priv->txstatus = USB_EPR_STATTX_NAK; + + /* Set both RX and TX status to NAK */ + + stm32_seteprxstatus(EP0, USB_EPR_STATRX_NAK); + stm32_seteptxstatus(EP0, USB_EPR_STATTX_NAK); + + /* Check the direction bit to determine if this the completion of an EP0 + * packet sent to or received from the host PC. + */ + + if ((istr & USB_ISTR_DIR) == 0) + { + /* EP0 IN: device-to-host (DIR=0) */ + + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EP0IN), istr); + stm32_clrepctrtx(EP0); + stm32_ep0in(priv); + } + else + { + /* EP0 OUT: host-to-device (DIR=1) */ + + epr = stm32_getreg(STM32_USB_EPR(EP0)); + + /* CTR_TX is set when an IN transaction successfully + * completes on an endpoint + */ + + if ((epr & USB_EPR_CTR_TX) != 0) + { + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EP0INDONE), epr); + stm32_clrepctrtx(EP0); + stm32_ep0in(priv); + } + + /* SETUP is set by the hardware when the last completed + * transaction was a control endpoint SETUP + */ + + else if ((epr & USB_EPR_SETUP) != 0) + { + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EP0SETUPDONE), epr); + stm32_clrepctrrx(EP0); + stm32_ep0setup(priv); + } + + /* Set by the hardware when an OUT/SETUP transaction successfully + * completed on this endpoint. + */ + + else if ((epr & USB_EPR_CTR_RX) != 0) + { + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EP0OUTDONE), epr); + stm32_clrepctrrx(EP0); + stm32_ep0out(priv); + } + + /* None of the above */ + + else + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EP0BADCTR), epr); + return; /* Does this ever happen? */ + } + } + + /* Make sure that the EP0 packet size is still OK (superstitious?) */ + + stm32_seteprxcount(EP0, STM32_EP0MAXPACKET); + + /* Now figure out the new RX/TX status. Here are all possible + * consequences of the above EP0 operations: + * + * rxstatus txstatus ep0state MEANING + * -------- -------- --------- --------------------------------- + * NAK NAK IDLE Nothing happened + * NAK VALID IDLE EP0 response sent from USBDEV driver + * NAK VALID WRREQUEST EP0 response sent from class driver + * NAK --- STALL Some protocol error occurred + * + * First handle the STALL condition: + */ + + if (priv->ep0state == EP0STATE_STALLED) + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EP0SETUPSTALLED), + priv->ep0state); + priv->rxstatus = USB_EPR_STATRX_STALL; + priv->txstatus = USB_EPR_STATTX_STALL; + } + + /* Was a transmission started? If so, txstatus will be VALID. The + * only special case to handle is when both are set to NAK. In that + * case, we need to set RX status to VALID in order to accept the next + * SETUP request. + */ + + else if (priv->rxstatus == USB_EPR_STATRX_NAK && + priv->txstatus == USB_EPR_STATTX_NAK) + { + priv->rxstatus = USB_EPR_STATRX_VALID; + } + + /* Now set the new TX and RX status */ + + stm32_seteprxstatus(EP0, priv->rxstatus); + stm32_seteptxstatus(EP0, priv->txstatus); +} + +/**************************************************************************** + * Name: stm32_lptransfer + ****************************************************************************/ + +static void stm32_lptransfer(struct stm32_usbdev_s *priv) +{ + uint8_t epno; + uint16_t istr; + + /* Stay in loop while LP interrupts are pending */ + + while (((istr = stm32_getreg(STM32_USB_ISTR)) & USB_ISTR_CTR) != 0) + { + stm32_putreg((uint16_t)~USB_ISTR_CTR, STM32_USB_ISTR); + + /* Extract highest priority endpoint number */ + + epno = (uint8_t)(istr & USB_ISTR_EPID_MASK); + + /* Handle EP0 completion events */ + + if (epno == 0) + { + stm32_ep0done(priv, istr); + } + + /* Handle other endpoint completion events */ + + else + { + stm32_epdone(priv, epno); + } + } +} + +/**************************************************************************** + * Name: stm32_usb_interrupt + ****************************************************************************/ + +static int stm32_usb_interrupt(int irq, void *context, void *arg) +{ + struct stm32_usbdev_s *priv = (struct stm32_usbdev_s *)arg; + uint16_t istr; + uint8_t epno; + + DEBUGASSERT(priv != NULL); + + /* High priority interrupts are only triggered by a correct transfer event + * for isochronous and double-buffer bulk transfers. + */ + + istr = stm32_getreg(STM32_USB_ISTR); + usbtrace(TRACE_INTENTRY(STM32_TRACEINTID_INTERRUPT), istr); + while ((istr & USB_ISTR_CTR) != 0) + { + stm32_putreg((uint16_t)~USB_ISTR_CTR, STM32_USB_ISTR); + + /* Extract highest priority endpoint number */ + + epno = (uint8_t)(istr & USB_ISTR_EPID_MASK); + + /* And handle the completion event */ + + stm32_epdone(priv, epno); + + /* Fetch the status again for the next time through the loop */ + + istr = stm32_getreg(STM32_USB_ISTR); + } + + /* Handle Reset interrupts. When this event occurs, the peripheral is left + * in the same conditions it is left by the system reset (but with the + * USB controller enabled). + */ + + if ((istr & USB_ISTR_RESET) != 0) + { + /* Reset interrupt received. Clear the RESET interrupt status. */ + + stm32_putreg(~USB_ISTR_RESET, STM32_USB_ISTR); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_RESET), istr); + + /* Restore our power-up state and exit now because istr is no longer + * valid. + */ + + stm32_reset(priv); + goto exit_interrupt; + } + + /* Handle Wakeup interrupts. + * This interrupt is only enable while the USB is suspended. + */ + + if ((istr & USB_ISTR_WKUP & priv->imask) != 0) + { + /* Wakeup interrupt received. Clear the WKUP interrupt status. + * The cause of the resume is indicated in the FNR register + */ + + stm32_putreg(~USB_ISTR_WKUP, STM32_USB_ISTR); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_WKUP), + stm32_getreg(STM32_USB_FNR)); + + /* Perform the wakeup action */ + + stm32_initresume(priv); + priv->rsmstate = RSMSTATE_IDLE; + + /* Disable ESOF polling, disable the wakeup interrupt, and + * re-enable the suspend interrupt. Clear any pending SUSP + * interrupts. + */ + + stm32_setimask(priv, USB_CNTR_SUSPM, USB_CNTR_ESOFM | USB_CNTR_WKUPM); + stm32_putreg(~USB_CNTR_SUSPM, STM32_USB_ISTR); + } + + if ((istr & USB_ISTR_SUSP & priv->imask) != 0) + { + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SUSP), 0); + stm32_suspend(priv); + + /* Clear of the ISTR bit must be done after setting of + * USB_CNTR_FSUSP + */ + + stm32_putreg(~USB_ISTR_SUSP, STM32_USB_ISTR); + } + + if ((istr & USB_ISTR_ESOF & priv->imask) != 0) + { + stm32_putreg(~USB_ISTR_ESOF, STM32_USB_ISTR); + + /* Resume handling timing is made with ESOFs */ + + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_ESOF), 0); + stm32_esofpoll(priv); + } + + if ((istr & USB_ISTR_CTR & priv->imask) != 0) + { + /* Low priority endpoint correct transfer interrupt */ + + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_LPCTR), istr); + stm32_lptransfer(priv); + } + +exit_interrupt: + usbtrace(TRACE_INTEXIT(STM32_TRACEINTID_INTERRUPT), 0); + return OK; +} + +/**************************************************************************** + * Name: stm32_setimask + ****************************************************************************/ + +static void +stm32_setimask(struct stm32_usbdev_s *priv, + uint16_t setbits, uint16_t clrbits) +{ + uint16_t regval; + + /* Adjust the interrupt mask bits in the shadow copy first */ + + priv->imask &= ~clrbits; + priv->imask |= setbits; + + /* Then make the interrupt mask bits in the CNTR register match the + * shadow register (Hmmm... who is shadowing whom?) + */ + + regval = stm32_getreg(STM32_USB_CNTR); + regval &= ~USB_CNTR_ALLINTS; + regval |= priv->imask; + stm32_putreg(regval, STM32_USB_CNTR); +} + +/**************************************************************************** + * Suspend/Resume Helpers + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_suspend + ****************************************************************************/ + +static void stm32_suspend(struct stm32_usbdev_s *priv) +{ + uint16_t regval; + + /* Notify the class driver of the suspend event */ + + if (priv->driver) + { + CLASS_SUSPEND(priv->driver, &priv->usbdev); + } + + /* Disable ESOF polling, disable the SUSP interrupt, and enable the WKUP + * interrupt. Clear any pending WKUP interrupt. + */ + + stm32_setimask(priv, USB_CNTR_WKUPM, USB_CNTR_ESOFM | USB_CNTR_SUSPM); + stm32_putreg(~USB_ISTR_WKUP, STM32_USB_ISTR); + + /* Set the FSUSP bit in the CNTR register. This activates suspend mode + * within the USB peripheral and disables further SUSP interrupts. + */ + + regval = stm32_getreg(STM32_USB_CNTR); + regval |= USB_CNTR_FSUSP; + stm32_putreg(regval, STM32_USB_CNTR); + + /* If we are not a self-powered device, the got to low-power mode */ + + if (!priv->selfpowered) + { + /* Setting LPMODE in the CNTR register removes static power + * consumption in the USB analog transceivers but keeps them + * able to detect resume activity + */ + + regval = stm32_getreg(STM32_USB_CNTR); + regval |= USB_CNTR_LPMODE; + stm32_putreg(regval, STM32_USB_CNTR); + } + + /* Let the board-specific logic know that we have entered the suspend + * state + */ + + stm32_usbsuspend((struct usbdev_s *)priv, false); +} + +/**************************************************************************** + * Name: stm32_initresume + ****************************************************************************/ + +static void stm32_initresume(struct stm32_usbdev_s *priv) +{ + uint16_t regval; + + /* This function is called when either (1) a WKUP interrupt is received + * from the host PC, or (2) the class device implementation calls the + * wakeup() method. + */ + + /* Clear the USB low power mode (lower power mode was not set if this is + * a self-powered device. Also, low power mode is automatically cleared + * by hardware when a WKUP interrupt event occurs). + */ + + regval = stm32_getreg(STM32_USB_CNTR); + regval &= (~USB_CNTR_LPMODE); + stm32_putreg(regval, STM32_USB_CNTR); + + /* Restore full power -- whatever that means for this particular board */ + + stm32_usbsuspend((struct usbdev_s *)priv, true); + + /* Reset FSUSP bit and enable normal interrupt handling */ + + stm32_putreg(STM32_CNTR_SETUP, STM32_USB_CNTR); + + /* Notify the class driver of the resume event */ + + if (priv->driver) + { + CLASS_RESUME(priv->driver, &priv->usbdev); + } +} + +/**************************************************************************** + * Name: stm32_esofpoll + ****************************************************************************/ + +static void stm32_esofpoll(struct stm32_usbdev_s *priv) +{ + uint16_t regval; + + /* Called periodically from ESOF interrupt after RSMSTATE_STARTED */ + + switch (priv->rsmstate) + { + /* One ESOF after internal resume requested */ + + case RSMSTATE_STARTED: + regval = stm32_getreg(STM32_USB_CNTR); + regval |= USB_CNTR_RESUME; + stm32_putreg(regval, STM32_USB_CNTR); + priv->rsmstate = RSMSTATE_WAITING; + priv->nesofs = 10; + break; + + /* Countdown before completing the operation */ + + case RSMSTATE_WAITING: + priv->nesofs--; + if (priv->nesofs == 0) + { + /* Okay.. we are ready to resume normal operation */ + + regval = stm32_getreg(STM32_USB_CNTR); + regval &= (~USB_CNTR_RESUME); + stm32_putreg(regval, STM32_USB_CNTR); + priv->rsmstate = RSMSTATE_IDLE; + + /* Disable ESOF polling, disable the SUSP interrupt, and enable + * the WKUP interrupt. Clear any pending WKUP interrupt. + */ + + stm32_setimask(priv, + USB_CNTR_WKUPM, USB_CNTR_ESOFM | USB_CNTR_SUSPM); + stm32_putreg(~USB_ISTR_WKUP, STM32_USB_ISTR); + } + break; + + case RSMSTATE_IDLE: + default: + priv->rsmstate = RSMSTATE_IDLE; + break; + } +} + +/**************************************************************************** + * Endpoint Helpers + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_epreserve + ****************************************************************************/ + +static inline struct stm32_ep_s * +stm32_epreserve(struct stm32_usbdev_s *priv, uint8_t epset) +{ + struct stm32_ep_s *privep = NULL; + irqstate_t flags; + int epndx = 0; + + flags = enter_critical_section(); + epset &= priv->epavail; + if (epset) + { + /* Select the lowest bit in the set of matching, available endpoints + * (skipping EP0) + */ + + for (epndx = 1; epndx < STM32_NENDPOINTS; epndx++) + { + uint8_t bit = STM32_ENDP_BIT(epndx); + if ((epset & bit) != 0) + { + /* Mark the endpoint no longer available */ + + priv->epavail &= ~bit; + + /* And return the pointer to the standard endpoint structure */ + + privep = &priv->eplist[epndx]; + break; + } + } + } + + leave_critical_section(flags); + return privep; +} + +/**************************************************************************** + * Name: stm32_epunreserve + ****************************************************************************/ + +static inline void +stm32_epunreserve(struct stm32_usbdev_s *priv, struct stm32_ep_s *privep) +{ + irqstate_t flags = enter_critical_section(); + priv->epavail |= STM32_ENDP_BIT(USB_EPNO(privep->ep.eplog)); + leave_critical_section(flags); +} + +/**************************************************************************** + * Name: stm32_epreserved + ****************************************************************************/ + +static inline bool +stm32_epreserved(struct stm32_usbdev_s *priv, int epno) +{ + return ((priv->epavail & STM32_ENDP_BIT(epno)) == 0); +} + +/**************************************************************************** + * Name: stm32_epallocpma + ****************************************************************************/ + +static int stm32_epallocpma(struct stm32_usbdev_s *priv) +{ + irqstate_t flags; + int bufno = ERROR; + int bufndx; + + flags = enter_critical_section(); + for (bufndx = 2; bufndx < STM32_NBUFFERS; bufndx++) + { + /* Check if this buffer is available */ + + uint8_t bit = STM32_BUFFER_BIT(bufndx); + if ((priv->bufavail & bit) != 0) + { + /* Yes.. Mark the endpoint no longer available */ + + priv->bufavail &= ~bit; + + /* And return the index of the allocated buffer */ + + bufno = bufndx; + break; + } + } + + leave_critical_section(flags); + return bufno; +} + +/**************************************************************************** + * Name: stm32_epfreepma + ****************************************************************************/ + +static inline void +stm32_epfreepma(struct stm32_usbdev_s *priv, struct stm32_ep_s *privep) +{ + irqstate_t flags = enter_critical_section(); + priv->epavail |= STM32_ENDP_BIT(privep->bufno); + leave_critical_section(flags); +} + +/**************************************************************************** + * Endpoint operations + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_epconfigure + ****************************************************************************/ + +static int stm32_epconfigure(struct usbdev_ep_s *ep, + const struct usb_epdesc_s *desc, + bool last) +{ + struct stm32_ep_s *privep = (struct stm32_ep_s *)ep; + uint16_t pma; + uint16_t setting; + uint16_t maxpacket; + uint8_t epno; + +#ifdef CONFIG_DEBUG_FEATURES + if (!ep || !desc) + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); + uerr("ERROR: ep=%p desc=%p\n", ep, desc); + return -EINVAL; + } +#endif + + /* Get the unadorned endpoint address */ + + epno = USB_EPNO(desc->addr); + usbtrace(TRACE_EPCONFIGURE, (uint16_t)epno); + DEBUGASSERT(epno == USB_EPNO(ep->eplog)); + + /* Set the requested type */ + + switch (desc->attr & USB_EP_ATTR_XFERTYPE_MASK) + { + case USB_EP_ATTR_XFER_INT: /* Interrupt endpoint */ + setting = USB_EPR_EPTYPE_INTERRUPT; + break; + + case USB_EP_ATTR_XFER_BULK: /* Bulk endpoint */ + setting = USB_EPR_EPTYPE_BULK; + break; + + case USB_EP_ATTR_XFER_ISOC: /* Isochronous endpoint */ +#warning "REVISIT: Need to review isochronous EP setup" + setting = USB_EPR_EPTYPE_ISOC; + break; + + case USB_EP_ATTR_XFER_CONTROL: /* Control endpoint */ + setting = USB_EPR_EPTYPE_CONTROL; + break; + + default: + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADEPTYPE), + (uint16_t)desc->type); + return -EINVAL; + } + + stm32_seteptype(epno, setting); + + /* Get the address of the PMA buffer allocated for this endpoint */ + +#warning "REVISIT: Should configure BULK EPs using double buffer feature" + pma = STM32_BUFNO2BUF(privep->bufno); + + /* Get the maxpacket size of the endpoint. */ + + maxpacket = GETUINT16(desc->mxpacketsize); + DEBUGASSERT(maxpacket <= STM32_MAXPACKET_SIZE); + ep->maxpacket = maxpacket; + + /* Get the subset matching the requested direction */ + + if (USB_ISEPIN(desc->addr)) + { + /* The full, logical EP number includes direction */ + + ep->eplog = USB_EPIN(epno); + + /* Set up TX; disable RX */ + + stm32_seteptxaddr(epno, pma); + stm32_seteptxstatus(epno, USB_EPR_STATTX_NAK); + stm32_seteprxstatus(epno, USB_EPR_STATRX_DIS); + } + else + { + /* The full, logical EP number includes direction */ + + ep->eplog = USB_EPOUT(epno); + + /* Set up RX; disable TX */ + + stm32_seteprxaddr(epno, pma); + stm32_seteprxcount(epno, maxpacket); + stm32_seteprxstatus(epno, USB_EPR_STATRX_VALID); + stm32_seteptxstatus(epno, USB_EPR_STATTX_DIS); + } + + stm32_dumpep(epno); + return OK; +} + +/**************************************************************************** + * Name: stm32_epdisable + ****************************************************************************/ + +static int stm32_epdisable(struct usbdev_ep_s *ep) +{ + struct stm32_ep_s *privep = (struct stm32_ep_s *)ep; + irqstate_t flags; + uint8_t epno; + +#ifdef CONFIG_DEBUG_FEATURES + if (!ep) + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); + uerr("ERROR: ep=%p\n", ep); + return -EINVAL; + } +#endif + + epno = USB_EPNO(ep->eplog); + usbtrace(TRACE_EPDISABLE, epno); + + /* Cancel any ongoing activity */ + + flags = enter_critical_section(); + stm32_cancelrequests(privep); + + /* Disable TX; disable RX */ + + stm32_seteprxcount(epno, 0); + stm32_seteprxstatus(epno, USB_EPR_STATRX_DIS); + stm32_seteptxstatus(epno, USB_EPR_STATTX_DIS); + + leave_critical_section(flags); + return OK; +} + +/**************************************************************************** + * Name: stm32_epallocreq + ****************************************************************************/ + +static struct usbdev_req_s *stm32_epallocreq(struct usbdev_ep_s *ep) +{ + struct stm32_req_s *privreq; + +#ifdef CONFIG_DEBUG_FEATURES + if (!ep) + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); + return NULL; + } +#endif + usbtrace(TRACE_EPALLOCREQ, USB_EPNO(ep->eplog)); + + privreq = kmm_malloc(sizeof(struct stm32_req_s)); + if (!privreq) + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_ALLOCFAIL), 0); + return NULL; + } + + memset(privreq, 0, sizeof(struct stm32_req_s)); + return &privreq->req; +} + +/**************************************************************************** + * Name: stm32_epfreereq + ****************************************************************************/ + +static void stm32_epfreereq(struct usbdev_ep_s *ep, struct usbdev_req_s *req) +{ + struct stm32_req_s *privreq = (struct stm32_req_s *)req; + +#ifdef CONFIG_DEBUG_FEATURES + if (!ep || !req) + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); + return; + } +#endif + usbtrace(TRACE_EPFREEREQ, USB_EPNO(ep->eplog)); + + kmm_free(privreq); +} + +/**************************************************************************** + * Name: stm32_epsubmit + ****************************************************************************/ + +static int stm32_epsubmit(struct usbdev_ep_s *ep, + struct usbdev_req_s *req) +{ + struct stm32_req_s *privreq = (struct stm32_req_s *)req; + struct stm32_ep_s *privep = (struct stm32_ep_s *)ep; + struct stm32_usbdev_s *priv; + irqstate_t flags; + uint8_t epno; + int ret = OK; + +#ifdef CONFIG_DEBUG_FEATURES + if (!req || !req->callback || !req->buf || !ep) + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); + uerr("ERROR: req=%p callback=%p buf=%p ep=%p\n", + req, req->callback, req->buf, ep); + return -EINVAL; + } +#endif + + usbtrace(TRACE_EPSUBMIT, USB_EPNO(ep->eplog)); + priv = privep->dev; + +#ifdef CONFIG_DEBUG_FEATURES + if (!priv->driver) + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_NOTCONFIGURED), + priv->usbdev.speed); + uerr("ERROR: driver=%p\n", priv->driver); + return -ESHUTDOWN; + } +#endif + + /* Handle the request from the class driver */ + + epno = USB_EPNO(ep->eplog); + req->result = -EINPROGRESS; + req->xfrd = 0; + flags = enter_critical_section(); + + /* If we are stalled, then drop all requests on the floor */ + + if (privep->stalled) + { + stm32_abortrequest(privep, privreq, -EBUSY); + uerr("ERROR: stalled\n"); + ret = -EBUSY; + } + + /* Handle IN (device-to-host) requests. NOTE: If the class device is + * using the bi-directional EP0, then we assume that they intend the EP0 + * IN functionality. + */ + + else if (USB_ISEPIN(ep->eplog) || epno == EP0) + { + /* Add the new request to the request queue for the IN endpoint */ + + stm32_rqenqueue(privep, privreq); + usbtrace(TRACE_INREQQUEUED(epno), req->len); + + /* If the IN endpoint FIFO is available, then transfer the data now */ + + if (!privep->txbusy) + { + priv->txstatus = USB_EPR_STATTX_NAK; + if (epno == EP0) + { + ret = stm32_wrrequest_ep0(priv, privep); + } + else + { + ret = stm32_wrrequest(priv, privep); + } + + /* Set the new TX status */ + + stm32_seteptxstatus(epno, priv->txstatus); + } + } + + /* Handle OUT (host-to-device) requests */ + + else + { + /* Add the new request to the request queue for the OUT endpoint */ + + privep->txnullpkt = 0; + stm32_rqenqueue(privep, privreq); + usbtrace(TRACE_OUTREQQUEUED(epno), req->len); + + /* This there a incoming data pending the availability of a + * request? + */ + + if (priv->rxpending) + { + /* Set STAT_RX bits to '11' in the USB_EPnR, enabling further + * transactions. "While the STAT_RX bits are equal to '10' + * (NAK), any OUT request addressed to that endpoint is NAKed, + * indicating a flow control condition: the USB host will retry + * the transaction until it succeeds." + */ + + priv->rxstatus = USB_EPR_STATRX_VALID; + stm32_seteprxstatus(epno, priv->rxstatus); + + /* Data is no longer pending */ + + priv->rxpending = false; + } + } + + leave_critical_section(flags); + return ret; +} + +/**************************************************************************** + * Name: stm32_epcancel + ****************************************************************************/ + +static int stm32_epcancel(struct usbdev_ep_s *ep, + struct usbdev_req_s *req) +{ + struct stm32_ep_s *privep = (struct stm32_ep_s *)ep; + irqstate_t flags; + +#ifdef CONFIG_DEBUG_USB + if (!ep || !req) + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); + return -EINVAL; + } +#endif + usbtrace(TRACE_EPCANCEL, USB_EPNO(ep->eplog)); + + flags = enter_critical_section(); + stm32_cancelrequests(privep); + leave_critical_section(flags); + return OK; +} + +/**************************************************************************** + * Name: stm32_epstall + ****************************************************************************/ + +static int stm32_epstall(struct usbdev_ep_s *ep, bool resume) +{ + struct stm32_ep_s *privep; + struct stm32_usbdev_s *priv; + uint8_t epno; + uint16_t status; + irqstate_t flags; + +#ifdef CONFIG_DEBUG_USB + if (!ep) + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); + return -EINVAL; + } +#endif + + privep = (struct stm32_ep_s *)ep; + priv = (struct stm32_usbdev_s *)privep->dev; + epno = USB_EPNO(ep->eplog); + + /* STALL or RESUME the endpoint */ + + flags = enter_critical_section(); + usbtrace(resume ? TRACE_EPRESUME : TRACE_EPSTALL, USB_EPNO(ep->eplog)); + + /* Get status of the endpoint; stall the request if the endpoint is + * disabled + */ + + if (USB_ISEPIN(ep->eplog)) + { + status = stm32_geteptxstatus(epno); + } + else + { + status = stm32_geteprxstatus(epno); + } + + if (status == 0) + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EPDISABLED), 0); + + if (epno == 0) + { + priv->ep0state = EP0STATE_STALLED; + } + + leave_critical_section(flags); + return -ENODEV; + } + + /* Handle the resume condition */ + + if (resume) + { + /* Resuming a stalled endpoint */ + + usbtrace(TRACE_EPRESUME, epno); + privep->stalled = false; + + if (USB_ISEPIN(ep->eplog)) + { + /* IN endpoint */ + + if (stm32_eptxstalled(epno)) + { + stm32_clrtxdtog(epno); + + /* Restart any queued write requests */ + + priv->txstatus = USB_EPR_STATTX_NAK; + if (epno == EP0) + { + stm32_wrrequest_ep0(priv, privep); + } + else + { + stm32_wrrequest(priv, privep); + } + + /* Set the new TX status */ + + stm32_seteptxstatus(epno, priv->txstatus); + } + } + else + { + /* OUT endpoint */ + + if (stm32_eprxstalled(epno)) + { + if (epno == EP0) + { + /* After clear the STALL, + * enable the default endpoint receiver + */ + + stm32_seteprxcount(epno, ep->maxpacket); + } + else + { + stm32_clrrxdtog(epno); + } + + priv->rxstatus = USB_EPR_STATRX_VALID; + stm32_seteprxstatus(epno, USB_EPR_STATRX_VALID); + } + } + } + + /* Handle the stall condition */ + + else + { + usbtrace(TRACE_EPSTALL, epno); + privep->stalled = true; + + if (USB_ISEPIN(ep->eplog)) + { + /* IN endpoint */ + + priv->txstatus = USB_EPR_STATTX_STALL; + stm32_seteptxstatus(epno, USB_EPR_STATTX_STALL); + } + else + { + /* OUT endpoint */ + + priv->rxstatus = USB_EPR_STATRX_STALL; + stm32_seteprxstatus(epno, USB_EPR_STATRX_STALL); + } + } + + leave_critical_section(flags); + return OK; +} + +/**************************************************************************** + * Device Controller Operations + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_allocep + ****************************************************************************/ + +static struct usbdev_ep_s *stm32_allocep(struct usbdev_s *dev, + uint8_t epno, + bool in, uint8_t eptype) +{ + struct stm32_usbdev_s *priv = (struct stm32_usbdev_s *)dev; + struct stm32_ep_s *privep = NULL; + uint8_t epset = STM32_ENDP_ALLSET; + int bufno; + + usbtrace(TRACE_DEVALLOCEP, (uint16_t)epno); +#ifdef CONFIG_DEBUG_USB + if (!dev) + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); + return NULL; + } +#endif + + /* Ignore any direction bits in the logical address */ + + epno = USB_EPNO(epno); + + /* A logical address of 0 means that any endpoint will do */ + + if (epno > 0) + { + /* Otherwise, we will return the endpoint structure only for the + * requested 'logical' endpoint. + * All of the other checks will still be performed. + * + * First, verify that the logical endpoint is in the range supported by + * by the hardware. + */ + + if (epno >= STM32_NENDPOINTS) + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADEPNO), (uint16_t)epno); + return NULL; + } + + /* Convert the logical address to a physical OUT endpoint address and + * remove all of the candidate endpoints from the bitset except for the + * the IN/OUT pair for this logical address. + */ + + epset = STM32_ENDP_BIT(epno); + } + + /* Check if the selected endpoint number is available */ + + privep = stm32_epreserve(priv, epset); + if (!privep) + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EPRESERVE), (uint16_t)epset); + goto errout; + } + + /* Allocate a PMA buffer for this endpoint */ + +#warning "REVISIT: Should configure BULK EPs using double buffer feature" + bufno = stm32_epallocpma(priv); + if (bufno < 0) + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EPBUFFER), 0); + goto errout_with_ep; + } + + privep->bufno = (uint8_t)bufno; + return &privep->ep; + +errout_with_ep: + stm32_epunreserve(priv, privep); +errout: + return NULL; +} + +/**************************************************************************** + * Name: stm32_freeep + ****************************************************************************/ + +static void stm32_freeep(struct usbdev_s *dev, struct usbdev_ep_s *ep) +{ + struct stm32_usbdev_s *priv; + struct stm32_ep_s *privep; + +#ifdef CONFIG_DEBUG_USB + if (!dev || !ep) + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); + return; + } +#endif + priv = (struct stm32_usbdev_s *)dev; + privep = (struct stm32_ep_s *)ep; + usbtrace(TRACE_DEVFREEEP, (uint16_t)USB_EPNO(ep->eplog)); + + if (priv && privep) + { + /* Free the PMA buffer assigned to this endpoint */ + + stm32_epfreepma(priv, privep); + + /* Mark the endpoint as available */ + + stm32_epunreserve(priv, privep); + } +} + +/**************************************************************************** + * Name: stm32_getframe + ****************************************************************************/ + +static int stm32_getframe(struct usbdev_s *dev) +{ + uint16_t fnr; + +#ifdef CONFIG_DEBUG_USB + if (!dev) + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); + return -EINVAL; + } +#endif + + /* Return the last frame number detected by the hardware */ + + fnr = stm32_getreg(STM32_USB_FNR); + usbtrace(TRACE_DEVGETFRAME, fnr); + return (fnr & USB_FNR_FN_MASK); +} + +/**************************************************************************** + * Name: stm32_wakeup + ****************************************************************************/ + +static int stm32_wakeup(struct usbdev_s *dev) +{ + struct stm32_usbdev_s *priv = (struct stm32_usbdev_s *)dev; + irqstate_t flags; + + usbtrace(TRACE_DEVWAKEUP, 0); +#ifdef CONFIG_DEBUG_USB + if (!dev) + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); + return -EINVAL; + } +#endif + + /* Start the resume sequence. The actual resume steps will be driven + * by the ESOF interrupt. + */ + + flags = enter_critical_section(); + stm32_initresume(priv); + priv->rsmstate = RSMSTATE_STARTED; + + /* Disable the SUSP interrupt (until we are fully resumed), disable + * the WKUP interrupt (we are already waking up), and enable the + * ESOF interrupt that will drive the resume operations. Clear any + * pending ESOF interrupt. + */ + + stm32_setimask(priv, USB_CNTR_ESOFM, USB_CNTR_WKUPM | USB_CNTR_SUSPM); + stm32_putreg(~USB_ISTR_ESOF, STM32_USB_ISTR); + leave_critical_section(flags); + return OK; +} + +/**************************************************************************** + * Name: stm32_selfpowered + ****************************************************************************/ + +static int stm32_selfpowered(struct usbdev_s *dev, bool selfpowered) +{ + struct stm32_usbdev_s *priv = (struct stm32_usbdev_s *)dev; + + usbtrace(TRACE_DEVSELFPOWERED, (uint16_t)selfpowered); + +#ifdef CONFIG_DEBUG_USB + if (!dev) + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); + return -ENODEV; + } +#endif + + priv->selfpowered = selfpowered; + return OK; +} + +/**************************************************************************** + * Initialization/Reset + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_reset + ****************************************************************************/ + +static void stm32_reset(struct stm32_usbdev_s *priv) +{ + int epno; + + /* Put the USB controller in reset, disable all interrupts */ + + stm32_putreg(USB_CNTR_FRES, STM32_USB_CNTR); + + /* Tell the class driver that we are disconnected. The class driver + * should then accept any new configurations. + */ + + CLASS_DISCONNECT(priv->driver, &priv->usbdev); + + /* Reset the device state structure */ + + priv->ep0state = EP0STATE_IDLE; + priv->rsmstate = RSMSTATE_IDLE; + priv->rxpending = false; + + /* Reset endpoints */ + + for (epno = 0; epno < STM32_NENDPOINTS; epno++) + { + struct stm32_ep_s *privep = &priv->eplist[epno]; + + /* Cancel any queued requests. Since they are canceled + * with status -ESHUTDOWN, then will not be requeued + * until the configuration is reset. NOTE: This should + * not be necessary... the CLASS_DISCONNECT above should + * result in the class implementation calling stm32_epdisable + * for each of its configured endpoints. + */ + + stm32_cancelrequests(privep); + + /* Reset endpoint status */ + + privep->stalled = false; + privep->halted = false; + privep->txbusy = false; + privep->txnullpkt = false; + } + + /* Re-configure the USB controller in its initial, unconnected state */ + + stm32_hwreset(priv); + priv->usbdev.speed = USB_SPEED_FULL; +} + +/**************************************************************************** + * Name: stm32_hwreset + ****************************************************************************/ + +static void stm32_hwreset(struct stm32_usbdev_s *priv) +{ + /* Put the USB controller into reset, clear all interrupt enables */ + + stm32_putreg(USB_CNTR_FRES, STM32_USB_CNTR); + + /* Disable interrupts (and perhaps take the USB controller out of reset) */ + + priv->imask = 0; + stm32_putreg(priv->imask, STM32_USB_CNTR); + + /* Set the STM32 BTABLE address */ + + stm32_putreg(STM32_BTABLE_ADDRESS & 0xfff8, STM32_USB_BTABLE); + + /* Initialize EP0 */ + + stm32_seteptype(EP0, USB_EPR_EPTYPE_CONTROL); + stm32_seteptxstatus(EP0, USB_EPR_STATTX_NAK); + stm32_seteprxaddr(EP0, STM32_EP0_RXADDR); + stm32_seteprxcount(EP0, STM32_EP0MAXPACKET); + stm32_seteptxaddr(EP0, STM32_EP0_TXADDR); + stm32_clrstatusout(EP0); + stm32_seteprxstatus(EP0, USB_EPR_STATRX_VALID); + + /* Set the device to respond on default address */ + + stm32_setdevaddr(priv, 0); + + /* Clear any pending interrupts */ + + stm32_putreg(0, STM32_USB_ISTR); + + /* Enable interrupts at the USB controller */ + + stm32_setimask(priv, STM32_CNTR_SETUP, + (USB_CNTR_ALLINTS & ~STM32_CNTR_SETUP)); + stm32_dumpep(EP0); +} + +/**************************************************************************** + * Name: stm32_hwsetup + ****************************************************************************/ + +static void stm32_hwsetup(struct stm32_usbdev_s *priv) +{ + int epno; + + /* Power the USB controller, put the USB controller into reset, disable + * all USB interrupts + */ + + stm32_putreg(USB_CNTR_FRES | USB_CNTR_PDWN, STM32_USB_CNTR); + + /* Disconnect the device / disable the pull-up. We don't want the + * host to enumerate us until the class driver is registered. + */ + + stm32_usbpullup(&priv->usbdev, false); + + /* Initialize the device state structure. NOTE: many fields + * have the initial value of zero and, hence, are not explicitly + * initialized here. + */ + + memset(priv, 0, sizeof(struct stm32_usbdev_s)); + priv->usbdev.ops = &g_devops; + priv->usbdev.ep0 = &priv->eplist[EP0].ep; + priv->epavail = STM32_ENDP_ALLSET & ~STM32_ENDP_BIT(EP0); + priv->bufavail = STM32_BUFFER_ALLSET & ~STM32_BUFFER_EP0; + + /* Initialize the endpoint list */ + + for (epno = 0; epno < STM32_NENDPOINTS; epno++) + { + /* Set endpoint operations, reference to driver structure (not + * really necessary because there is only one controller), and + * the (physical) endpoint number which is just the index to the + * endpoint. + */ + + priv->eplist[epno].ep.ops = &g_epops; + priv->eplist[epno].dev = priv; + priv->eplist[epno].ep.eplog = epno; + + /* We will use a fixed maxpacket size for all endpoints (perhaps + * ISOC endpoints could have larger maxpacket???). A smaller + * packet size can be selected when the endpoint is configured. + */ + + priv->eplist[epno].ep.maxpacket = STM32_MAXPACKET_SIZE; + } + + /* Select a smaller endpoint size for EP0 */ + +#if STM32_EP0MAXPACKET < STM32_MAXPACKET_SIZE + priv->eplist[EP0].ep.maxpacket = STM32_EP0MAXPACKET; +#endif + + /* Configure the USB controller. USB uses the following GPIO pins: + * + * PA9 - VBUS + * PA10 - ID + * PA11 - DM + * PA12 - DP + * + * "As soon as the USB is enabled, these pins [DM and DP] are connected to + * the USB internal transceiver automatically." + */ + + /* Power up the USB controller, holding it in reset. There is a delay of + * about 1uS after applying power before the USB will behave predictably. + * A 5MS delay is more than enough. NOTE that we leave the USB controller + * in the reset state; the hardware will not be initialized until the + * class driver has been bound. + */ + + stm32_putreg(USB_CNTR_FRES, STM32_USB_CNTR); + up_mdelay(5); +} + +/**************************************************************************** + * Name: stm32_hwshutdown + ****************************************************************************/ + +static void stm32_hwshutdown(struct stm32_usbdev_s *priv) +{ + priv->usbdev.speed = USB_SPEED_UNKNOWN; + + /* Disable all interrupts and force the USB controller into reset */ + + stm32_putreg(USB_CNTR_FRES, STM32_USB_CNTR); + + /* Clear any pending interrupts */ + + stm32_putreg(0, STM32_USB_ISTR); + + /* Disconnect the device / disable the pull-up */ + + stm32_usbpullup(&priv->usbdev, false); + + /* Power down the USB controller */ + + stm32_putreg(USB_CNTR_FRES | USB_CNTR_PDWN, STM32_USB_CNTR); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: arm_usbinitialize + * Description: + * Initialize the USB driver + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void arm_usbinitialize(void) +{ + /* For now there is only one USB controller, but we will always refer to + * it using a pointer to make any future ports to multiple USB controllers + * easier. + */ + + struct stm32_usbdev_s *priv = &g_usbdev; + uint32_t regval; + + usbtrace(TRACE_DEVINIT, 0); + + /* Configure USB GPIO alternate function pins */ + + stm32_configgpio(GPIO_USB_DM); + stm32_configgpio(GPIO_USB_DP); + + /* Enable clocking to the USB peripheral */ + + regval = getreg32(STM32_RCC_APB1RSTR); + regval &= ~RCC_APB1ENR_USBEN; + putreg32(regval, STM32_RCC_APB1RSTR); + + /* Power up the USB controller, but leave it in the reset state */ + + stm32_hwsetup(priv); + + /* Attach USB controller interrupt handlers. The hardware will not be + * initialized and interrupts will not be enabled until the class device + * driver is bound. Getting the IRQs here only makes sure that we have + * them when we need them later. + */ + + if (irq_attach(STM32_IRQ_USB, stm32_usb_interrupt, priv) != 0) + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_IRQREGISTRATION), + (uint16_t)STM32_IRQ_USB); + goto errout; + } + + return; + +errout: + arm_usbuninitialize(); +} + +/**************************************************************************** + * Name: arm_usbuninitialize + * Description: + * Initialize the USB driver + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void arm_usbuninitialize(void) +{ + /* For now there is only one USB controller, but we will always refer to + * it using a pointer to make any future ports to multiple USB controllers + * easier. + */ + + struct stm32_usbdev_s *priv = &g_usbdev; + irqstate_t flags; + + flags = enter_critical_section(); + usbtrace(TRACE_DEVUNINIT, 0); + + /* Disable and detach the USB IRQs */ + + up_disable_irq(STM32_IRQ_USB); + irq_detach(STM32_IRQ_USB); + + if (priv->driver) + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_DRIVERREGISTERED), 0); + usbdev_unregister(priv->driver); + } + + /* Put the hardware in an inactive state */ + + stm32_hwshutdown(priv); + leave_critical_section(flags); +} + +/**************************************************************************** + * Name: usbdev_register + * + * Description: + * Register a USB device class driver. The class driver's bind() method + * will be called to bind it to a USB device driver. + * + ****************************************************************************/ + +int usbdev_register(struct usbdevclass_driver_s *driver) +{ + /* For now there is only one USB controller, but we will always refer to + * it using a pointer to make any future ports to multiple USB controllers + * easier. + */ + + struct stm32_usbdev_s *priv = &g_usbdev; + int ret; + + usbtrace(TRACE_DEVREGISTER, 0); + +#ifdef CONFIG_DEBUG_USB + if (!driver || !driver->ops->bind || !driver->ops->unbind || + !driver->ops->disconnect || !driver->ops->setup) + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); + return -EINVAL; + } + + if (priv->driver) + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_DRIVER), 0); + return -EBUSY; + } +#endif + + /* First hook up the driver */ + + priv->driver = driver; + + /* Then bind the class driver */ + + ret = CLASS_BIND(driver, &priv->usbdev); + if (ret) + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BINDFAILED), + (uint16_t) - ret); + } + else + { + /* Setup the USB controller -- enabling interrupts at the USB + * controller + */ + + stm32_hwreset(priv); + + /* Enable USB controller interrupts at the NVIC */ + + up_enable_irq(STM32_IRQ_USB); + + /* Enable pull-up to connect the device. The host should enumerate + * us some time after this + */ + + stm32_usbpullup(&priv->usbdev, true); + priv->usbdev.speed = USB_SPEED_FULL; + } + + return ret; +} + +/**************************************************************************** + * Name: usbdev_unregister + * + * Description: + * Un-register usbdev class driver. If the USB device is connected to a + * USB host, it will first disconnect(). The driver is also requested to + * unbind() and clean up any device state, before this procedure finally + * returns. + * + ****************************************************************************/ + +int usbdev_unregister(struct usbdevclass_driver_s *driver) +{ + /* For now there is only one USB controller, but we will always refer to + * it using a pointer to make any future ports to multiple USB controllers + * easier. + */ + + struct stm32_usbdev_s *priv = &g_usbdev; + irqstate_t flags; + + usbtrace(TRACE_DEVUNREGISTER, 0); + +#ifdef CONFIG_DEBUG_USB + if (driver != priv->driver) + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); + return -EINVAL; + } +#endif + + /* Reset the hardware and cancel all requests. All requests must be + * canceled while the class driver is still bound. + */ + + flags = enter_critical_section(); + stm32_reset(priv); + + /* Unbind the class driver */ + + CLASS_UNBIND(driver, &priv->usbdev); + + /* Disable USB controller interrupts (but keep them attached) */ + + up_disable_irq(STM32_IRQ_USB); + + /* Put the hardware in an inactive state. Then bring the hardware back up + * in the reset state (this is probably not necessary, the stm32_reset() + * call above was probably sufficient). + */ + + stm32_hwshutdown(priv); + stm32_hwsetup(priv); + + /* Unhook the driver */ + + priv->driver = NULL; + leave_critical_section(flags); + return OK; +} + +#endif /* CONFIG_USBDEV && CONFIG_STM32_USB */ diff --git a/arch/arm/src/common/stm32/stm32_usbdev_m3m4_v1.c b/arch/arm/src/common/stm32/stm32_usbdev_m3m4_v1.c new file mode 100644 index 0000000000000..f84789892b163 --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_usbdev_m3m4_v1.c @@ -0,0 +1,3983 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_usbdev_m3m4_v1.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* References: + * - RM0008 Reference manual, STMicro document ID 13902 + * - STM32F10xxx USB development kit, UM0424, STMicro + */ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include +#include + +#include "arm_internal.h" +#include "stm32.h" +#include "stm32_syscfg.h" +#include "stm32_gpio.h" +#include "stm32_usbdev.h" + +#if defined(CONFIG_USBDEV) && defined(CONFIG_STM32_USB) + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +#ifndef CONFIG_USBDEV_EP0_MAXSIZE +# define CONFIG_USBDEV_EP0_MAXSIZE 64 +#endif + +#ifndef CONFIG_USBDEV_SETUP_MAXDATASIZE +# define CONFIG_USBDEV_SETUP_MAXDATASIZE CONFIG_USBDEV_EP0_MAXSIZE +#endif + +/* USB Interrupts. Should be re-mapped if CAN is used. */ + +#ifdef CONFIG_STM32_STM32F30XX +# ifdef CONFIG_STM32_USB_ITRMP +# define STM32_IRQ_USBHP STM32_IRQ_USBHP_2 +# define STM32_IRQ_USBLP STM32_IRQ_USBLP_2 +# define STM32_IRQ_USBWKUP STM32_IRQ_USBWKUP_2 +# else +# define STM32_IRQ_USBHP STM32_IRQ_USBHP_1 +# define STM32_IRQ_USBLP STM32_IRQ_USBLP_1 +# define STM32_IRQ_USBWKUP STM32_IRQ_USBWKUP_1 +# endif +#endif + +/* Extremely detailed register debug that you would normally never want + * enabled. + */ + +#ifndef CONFIG_DEBUG_USB_INFO +# undef CONFIG_STM32_USBDEV_REGDEBUG +#endif + +/* Initial interrupt mask: Reset + Suspend + Correct Transfer */ + +#define STM32_CNTR_SETUP (USB_CNTR_RESETM|USB_CNTR_SUSPM|USB_CNTR_CTRM) + +/* Endpoint identifiers. The STM32 supports up to 16 mono-directional or 8 + * bidirectional endpoints. However, when you take into account PMA buffer + * usage (see below) and the fact that EP0 is bidirectional, then there is + * a functional limitation of EP0 + 5 mono-directional endpoints = 6. We'll + * define STM32_NENDPOINTS to be 8, however, because that is how many + * endpoint register sets there are. + */ + +#define EP0 (0) +#define EP1 (1) +#define EP2 (2) +#define EP3 (3) +#define EP4 (4) +#define EP5 (5) +#define EP6 (6) +#define EP7 (7) + +#define STM32_ENDP_BIT(ep) (1 << (ep)) +#define STM32_ENDP_ALLSET 0xff + +/* Packet sizes. We us a fixed 64 max packet size for all endpoint types */ + +#define STM32_MAXPACKET_SHIFT (6) +#define STM32_MAXPACKET_SIZE (1 << (STM32_MAXPACKET_SHIFT)) +#define STM32_MAXPACKET_MASK (STM32_MAXPACKET_SIZE-1) + +#define STM32_EP0MAXPACKET STM32_MAXPACKET_SIZE + +/* Buffer descriptor table. We assume that USB has exclusive use of CAN/USB + * memory. The buffer table is positioned at the beginning of the 512-byte + * CAN/USB memory. We will use the first STM32_NENDPOINTS*4 words for the + * buffer table. + * That is exactly 64 bytes, leaving 7*64 bytes for endpoint buffers. + */ + +#define STM32_BTABLE_ADDRESS (0x00) /* Start at the beginning of USB/CAN RAM */ +#define STM32_DESC_SIZE (8) /* Each descriptor is 4*2=8 bytes in size */ +#define STM32_BTABLE_SIZE (STM32_NENDPOINTS*STM32_DESC_SIZE) + +/* Buffer layout. Assume that all buffers are 64-bytes (maxpacketsize), then + * we have space for only 7 buffers; endpoint 0 will require two buffers, + * leaving 5 for other endpoints. + */ + +#define STM32_BUFFER_START STM32_BTABLE_SIZE +#define STM32_EP0_RXADDR STM32_BUFFER_START +#define STM32_EP0_TXADDR (STM32_EP0_RXADDR+STM32_EP0MAXPACKET) + +#define STM32_BUFFER_EP0 0x03 +#define STM32_NBUFFERS 7 +#define STM32_BUFFER_BIT(bn) (1 << (bn)) +#define STM32_BUFFER_ALLSET 0x7f +#define STM32_BUFNO2BUF(bn) (STM32_BUFFER_START+((bn)<head == NULL) +#define stm32_rqpeek(ep) ((ep)->head) + +/* USB trace ****************************************************************/ + +/* Trace error codes */ + +#define STM32_TRACEERR_ALLOCFAIL 0x0001 +#define STM32_TRACEERR_BADCLEARFEATURE 0x0002 +#define STM32_TRACEERR_BADDEVGETSTATUS 0x0003 +#define STM32_TRACEERR_BADEPGETSTATUS 0x0004 +#define STM32_TRACEERR_BADEPNO 0x0005 +#define STM32_TRACEERR_BADEPTYPE 0x0006 +#define STM32_TRACEERR_BADGETCONFIG 0x0007 +#define STM32_TRACEERR_BADGETSETDESC 0x0008 +#define STM32_TRACEERR_BADGETSTATUS 0x0009 +#define STM32_TRACEERR_BADSETADDRESS 0x000a +#define STM32_TRACEERR_BADSETCONFIG 0x000b +#define STM32_TRACEERR_BADSETFEATURE 0x000c +#define STM32_TRACEERR_BINDFAILED 0x000d +#define STM32_TRACEERR_DISPATCHSTALL 0x000e +#define STM32_TRACEERR_DRIVER 0x000f +#define STM32_TRACEERR_DRIVERREGISTERED 0x0010 +#define STM32_TRACEERR_EP0BADCTR 0x0011 +#define STM32_TRACEERR_EP0SETUPSTALLED 0x0012 +#define STM32_TRACEERR_EPBUFFER 0x0013 +#define STM32_TRACEERR_EPDISABLED 0x0014 +#define STM32_TRACEERR_EPOUTNULLPACKET 0x0015 +#define STM32_TRACEERR_EPRESERVE 0x0016 +#define STM32_TRACEERR_INVALIDCTRLREQ 0x0017 +#define STM32_TRACEERR_INVALIDPARMS 0x0018 +#define STM32_TRACEERR_IRQREGISTRATION 0x0019 +#define STM32_TRACEERR_NOTCONFIGURED 0x001a +#define STM32_TRACEERR_REQABORTED 0x001b + +/* Trace interrupt codes */ + +#define STM32_TRACEINTID_CLEARFEATURE 0x0001 +#define STM32_TRACEINTID_DEVGETSTATUS 0x0002 +#define STM32_TRACEINTID_DISPATCH 0x0003 +#define STM32_TRACEINTID_EP0IN 0x0004 +#define STM32_TRACEINTID_EP0INDONE 0x0005 +#define STM32_TRACEINTID_EP0OUTDONE 0x0006 +#define STM32_TRACEINTID_EP0SETUPDONE 0x0007 +#define STM32_TRACEINTID_EP0SETUPSETADDRESS 0x0008 +#define STM32_TRACEINTID_EPGETSTATUS 0x0009 +#define STM32_TRACEINTID_EPINDONE 0x000a +#define STM32_TRACEINTID_EPINQEMPTY 0x000b +#define STM32_TRACEINTID_EPOUTDONE 0x000c +#define STM32_TRACEINTID_EPOUTPENDING 0x000d +#define STM32_TRACEINTID_EPOUTQEMPTY 0x000e +#define STM32_TRACEINTID_ESOF 0x000f +#define STM32_TRACEINTID_GETCONFIG 0x0010 +#define STM32_TRACEINTID_GETSETDESC 0x0011 +#define STM32_TRACEINTID_GETSETIF 0x0012 +#define STM32_TRACEINTID_GETSTATUS 0x0013 +#define STM32_TRACEINTID_HPINTERRUPT 0x0014 +#define STM32_TRACEINTID_IFGETSTATUS 0x0015 +#define STM32_TRACEINTID_LPCTR 0x0016 +#define STM32_TRACEINTID_LPINTERRUPT 0x0017 +#define STM32_TRACEINTID_NOSTDREQ 0x0018 +#define STM32_TRACEINTID_RESET 0x0019 +#define STM32_TRACEINTID_SETCONFIG 0x001a +#define STM32_TRACEINTID_SETFEATURE 0x001b +#define STM32_TRACEINTID_SUSP 0x001c +#define STM32_TRACEINTID_SYNCHFRAME 0x001d +#define STM32_TRACEINTID_WKUP 0x001e +#define STM32_TRACEINTID_EP0SETUPOUT 0x001f +#define STM32_TRACEINTID_EP0SETUPOUTDATA 0x0020 + +/* Byte ordering in host-based values */ + +#ifdef CONFIG_ENDIAN_BIG +# define LSB 1 +# define MSB 0 +#else +# define LSB 0 +# define MSB 1 +#endif + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/* The various states of a control pipe */ + +enum stm32_ep0state_e +{ + EP0STATE_IDLE = 0, /* No request in progress */ + EP0STATE_SETUP_OUT, /* Set up received with data for device OUT in progress */ + EP0STATE_SETUP_READY, /* Set up was received prior and is in ctrl, + * now the data has arrived */ + EP0STATE_WRREQUEST, /* Write request in progress */ + EP0STATE_RDREQUEST, /* Read request in progress */ + EP0STATE_STALLED /* We are stalled */ +}; + +/* Resume states */ + +enum stm32_rsmstate_e +{ + RSMSTATE_IDLE = 0, /* Device is either fully suspended or running */ + RSMSTATE_STARTED, /* Resume sequence has been started */ + RSMSTATE_WAITING /* Waiting (on ESOFs) for end of sequence */ +}; + +union wb_u +{ + uint16_t w; + uint8_t b[2]; +}; + +/* A container for a request so that the request make be retained in a list */ + +struct stm32_req_s +{ + struct usbdev_req_s req; /* Standard USB request */ + struct stm32_req_s *flink; /* Supports a singly linked list */ +}; + +/* This is the internal representation of an endpoint */ + +struct stm32_ep_s +{ + /* Common endpoint fields. This must be the first thing defined in the + * structure so that it is possible to simply cast from struct usbdev_ep_s + * to struct stm32_ep_s. + */ + + struct usbdev_ep_s ep; /* Standard endpoint structure */ + + /* STR71X-specific fields */ + + struct stm32_usbdev_s *dev; /* Reference to private driver data */ + struct stm32_req_s *head; /* Request list for this endpoint */ + struct stm32_req_s *tail; + uint8_t bufno; /* Allocated buffer number */ + uint8_t stalled:1; /* true: Endpoint is stalled */ + uint8_t halted:1; /* true: Endpoint feature halted */ + uint8_t txbusy:1; /* true: TX endpoint FIFO full */ + uint8_t txnullpkt:1; /* Null packet needed at end of transfer */ +}; + +struct stm32_usbdev_s +{ + /* Common device fields. This must be the first thing defined in the + * structure so that it is possible to simply cast from struct usbdev_s + * to structstm32_usbdev_s. + */ + + struct usbdev_s usbdev; + + /* The bound device class driver */ + + struct usbdevclass_driver_s *driver; + + /* STM32-specific fields */ + + uint8_t ep0state; /* State of EP0 (see enum stm32_ep0state_e) */ + uint8_t rsmstate; /* Resume state (see enum stm32_rsmstate_e) */ + uint8_t nesofs; /* ESOF counter (for resume support) */ + uint8_t rxpending:1; /* 1: OUT data in PMA, but no read requests */ + uint8_t selfpowered:1; /* 1: Device is self powered */ + uint8_t epavail; /* Bitset of available endpoints */ + uint8_t bufavail; /* Bitset of available buffers */ + uint16_t rxstatus; /* Saved during interrupt processing */ + uint16_t txstatus; /* " " " " " " " " */ + uint16_t imask; /* Current interrupt mask */ + + /* E0 SETUP data buffering. + * + * ctrl + * The 8-byte SETUP request is received on the EP0 OUT endpoint and is + * saved. + * + * ep0data + * For OUT SETUP requests, the SETUP data phase must also complete + * before the SETUP command can be processed. The ep0 packet receipt + * logic stm32_ep0_rdrequest will save the accompanying EP0 OUT data + * in ep0data[] before the SETUP command is re-processed. + * + * ep0datlen + * Length of OUT DATA received in ep0data[] + */ + + struct usb_ctrlreq_s ctrl; /* Last EP0 request */ + + uint8_t ep0data[CONFIG_USBDEV_SETUP_MAXDATASIZE]; + uint16_t ep0datlen; + + /* The endpoint list */ + + struct stm32_ep_s eplist[STM32_NENDPOINTS]; +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/* Register operations ******************************************************/ + +#ifdef CONFIG_STM32_USBDEV_REGDEBUG +static uint16_t stm32_getreg(uint32_t addr); +static void stm32_putreg(uint16_t val, uint32_t addr); +static void stm32_checksetup(void); +static void stm32_dumpep(int epno); +#else +# define stm32_getreg(addr) getreg16(addr) +# define stm32_putreg(val,addr) putreg16(val,addr) +# define stm32_checksetup() +# define stm32_dumpep(epno) +#endif + +/* Low-Level Helpers ********************************************************/ + +static inline void + stm32_seteptxcount(uint8_t epno, uint16_t count); +static inline void + stm32_seteptxaddr(uint8_t epno, uint16_t addr); +static inline uint16_t + stm32_geteptxaddr(uint8_t epno); +static void stm32_seteprxcount(uint8_t epno, uint16_t count); +static inline uint16_t + stm32_geteprxcount(uint8_t epno); +static inline void + stm32_seteprxaddr(uint8_t epno, uint16_t addr); +static inline uint16_t + stm32_geteprxaddr(uint8_t epno); +static inline void + stm32_setepaddress(uint8_t epno, uint16_t addr); +static inline void + stm32_seteptype(uint8_t epno, uint16_t type); +static inline void + stm32_seteptxaddr(uint8_t epno, uint16_t addr); +static inline void + stm32_clrstatusout(uint8_t epno); +static void stm32_clrrxdtog(uint8_t epno); +static void stm32_clrtxdtog(uint8_t epno); +static void stm32_clrepctrrx(uint8_t epno); +static void stm32_clrepctrtx(uint8_t epno); +static void stm32_seteptxstatus(uint8_t epno, uint16_t state); +static void stm32_seteprxstatus(uint8_t epno, uint16_t state); +static inline uint16_t + stm32_geteptxstatus(uint8_t epno); +static inline uint16_t + stm32_geteprxstatus(uint8_t epno); +static bool stm32_eptxstalled(uint8_t epno); +static bool stm32_eprxstalled(uint8_t epno); +static void stm32_setimask(struct stm32_usbdev_s *priv, + uint16_t setbits, + uint16_t clrbits); + +/* Suspend/Resume Helpers ***************************************************/ + +static void stm32_suspend(struct stm32_usbdev_s *priv); +static void stm32_initresume(struct stm32_usbdev_s *priv); +static void stm32_esofpoll(struct stm32_usbdev_s *priv) ; + +/* Request Helpers **********************************************************/ + +static void stm32_copytopma(const uint8_t *buffer, uint16_t pma, + uint16_t nbytes); +static inline void stm32_copyfrompma(uint8_t *buffer, + uint16_t pma, uint16_t nbytes); +static struct stm32_req_s * + stm32_rqdequeue(struct stm32_ep_s *privep); +static void stm32_rqenqueue(struct stm32_ep_s *privep, + struct stm32_req_s *req); +static inline void + stm32_abortrequest(struct stm32_ep_s *privep, + struct stm32_req_s *privreq, int16_t result); +static void stm32_reqcomplete(struct stm32_ep_s *privep, int16_t result); +static void stm32_epwrite(struct stm32_usbdev_s *buf, + struct stm32_ep_s *privep, + const uint8_t *data, uint32_t nbytes); +static int stm32_wrrequest(struct stm32_usbdev_s *priv, + struct stm32_ep_s *privep); +inline static int + stm32_wrrequest_ep0(struct stm32_usbdev_s *priv, + struct stm32_ep_s *privep); +static inline int + stm32_ep0_rdrequest(struct stm32_usbdev_s *priv); +static int stm32_rdrequest(struct stm32_usbdev_s *priv, + struct stm32_ep_s *privep); +static void stm32_cancelrequests(struct stm32_ep_s *privep); + +/* Interrupt level processing ***********************************************/ + +static void stm32_dispatchrequest(struct stm32_usbdev_s *priv); +static void stm32_epdone(struct stm32_usbdev_s *priv, uint8_t epno); +static void stm32_setdevaddr(struct stm32_usbdev_s *priv, uint8_t value); +static void stm32_ep0setup(struct stm32_usbdev_s *priv); +static void stm32_ep0out(struct stm32_usbdev_s *priv); +static void stm32_ep0in(struct stm32_usbdev_s *priv); +static inline void + stm32_ep0done(struct stm32_usbdev_s *priv, uint16_t istr); +static void stm32_lptransfer(struct stm32_usbdev_s *priv); +static int stm32_hpinterrupt(int irq, void *context, void *arg); +static int stm32_lpinterrupt(int irq, void *context, void *arg); + +/* Endpoint helpers *********************************************************/ + +static inline struct stm32_ep_s * + stm32_epreserve(struct stm32_usbdev_s *priv, uint8_t epset); +static inline void + stm32_epunreserve(struct stm32_usbdev_s *priv, + struct stm32_ep_s *privep); +static inline bool + stm32_epreserved(struct stm32_usbdev_s *priv, int epno); +static int stm32_epallocpma(struct stm32_usbdev_s *priv); +static inline void + stm32_epfreepma(struct stm32_usbdev_s *priv, + struct stm32_ep_s *privep); + +/* Endpoint operations ******************************************************/ + +static int stm32_epconfigure(struct usbdev_ep_s *ep, + const struct usb_epdesc_s *desc, bool last); +static int stm32_epdisable(struct usbdev_ep_s *ep); +static struct usbdev_req_s * + stm32_epallocreq(struct usbdev_ep_s *ep); +static void stm32_epfreereq(struct usbdev_ep_s *ep, + struct usbdev_req_s *); +static int stm32_epsubmit(struct usbdev_ep_s *ep, + struct usbdev_req_s *req); +static int stm32_epcancel(struct usbdev_ep_s *ep, + struct usbdev_req_s *req); +static int stm32_epstall(struct usbdev_ep_s *ep, bool resume); + +/* USB device controller operations *****************************************/ + +static struct usbdev_ep_s * + stm32_allocep(struct usbdev_s *dev, uint8_t epno, bool in, + uint8_t eptype); +static void stm32_freeep(struct usbdev_s *dev, struct usbdev_ep_s *ep); +static int stm32_getframe(struct usbdev_s *dev); +static int stm32_wakeup(struct usbdev_s *dev); +static int stm32_selfpowered(struct usbdev_s *dev, bool selfpowered); + +/* Initialization/Reset *****************************************************/ + +static void stm32_reset(struct stm32_usbdev_s *priv); +static void stm32_hwreset(struct stm32_usbdev_s *priv); +static void stm32_hwsetup(struct stm32_usbdev_s *priv); +static void stm32_hwshutdown(struct stm32_usbdev_s *priv); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* Since there is only a single USB interface, all status information can be + * be simply retained in a single global instance. + */ + +static struct stm32_usbdev_s g_usbdev; + +static const struct usbdev_epops_s g_epops = +{ + .configure = stm32_epconfigure, + .disable = stm32_epdisable, + .allocreq = stm32_epallocreq, + .freereq = stm32_epfreereq, + .submit = stm32_epsubmit, + .cancel = stm32_epcancel, + .stall = stm32_epstall, +}; + +static const struct usbdev_ops_s g_devops = +{ + .allocep = stm32_allocep, + .freeep = stm32_freeep, + .getframe = stm32_getframe, + .wakeup = stm32_wakeup, + .selfpowered = stm32_selfpowered, + .pullup = stm32_usbpullup, +}; + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#ifdef CONFIG_USBDEV_TRACE_STRINGS +const struct trace_msg_t g_usb_trace_strings_intdecode[] = +{ + TRACE_STR(STM32_TRACEINTID_CLEARFEATURE), + TRACE_STR(STM32_TRACEINTID_DEVGETSTATUS), + TRACE_STR(STM32_TRACEINTID_DISPATCH), + TRACE_STR(STM32_TRACEINTID_EP0IN), + TRACE_STR(STM32_TRACEINTID_EP0INDONE), + TRACE_STR(STM32_TRACEINTID_EP0OUTDONE), + TRACE_STR(STM32_TRACEINTID_EP0SETUPDONE), + TRACE_STR(STM32_TRACEINTID_EP0SETUPSETADDRESS), + TRACE_STR(STM32_TRACEINTID_EPGETSTATUS), + TRACE_STR(STM32_TRACEINTID_EPINDONE), + TRACE_STR(STM32_TRACEINTID_EPINQEMPTY), + TRACE_STR(STM32_TRACEINTID_EPOUTDONE), + TRACE_STR(STM32_TRACEINTID_EPOUTPENDING), + TRACE_STR(STM32_TRACEINTID_EPOUTQEMPTY), + TRACE_STR(STM32_TRACEINTID_ESOF), + TRACE_STR(STM32_TRACEINTID_GETCONFIG), + TRACE_STR(STM32_TRACEINTID_GETSETDESC), + TRACE_STR(STM32_TRACEINTID_GETSETIF), + TRACE_STR(STM32_TRACEINTID_GETSTATUS), + TRACE_STR(STM32_TRACEINTID_HPINTERRUPT), + TRACE_STR(STM32_TRACEINTID_IFGETSTATUS), + TRACE_STR(STM32_TRACEINTID_LPCTR), + TRACE_STR(STM32_TRACEINTID_LPINTERRUPT), + TRACE_STR(STM32_TRACEINTID_NOSTDREQ), + TRACE_STR(STM32_TRACEINTID_RESET), + TRACE_STR(STM32_TRACEINTID_SETCONFIG), + TRACE_STR(STM32_TRACEINTID_SETFEATURE), + TRACE_STR(STM32_TRACEINTID_SUSP), + TRACE_STR(STM32_TRACEINTID_SYNCHFRAME), + TRACE_STR(STM32_TRACEINTID_WKUP), + TRACE_STR(STM32_TRACEINTID_EP0SETUPOUT), + TRACE_STR(STM32_TRACEINTID_EP0SETUPOUTDATA), + TRACE_STR_END +}; +#endif + +#ifdef CONFIG_USBDEV_TRACE_STRINGS +const struct trace_msg_t g_usb_trace_strings_deverror[] = +{ + TRACE_STR(STM32_TRACEERR_ALLOCFAIL), + TRACE_STR(STM32_TRACEERR_BADCLEARFEATURE), + TRACE_STR(STM32_TRACEERR_BADDEVGETSTATUS), + TRACE_STR(STM32_TRACEERR_BADEPGETSTATUS), + TRACE_STR(STM32_TRACEERR_BADEPNO), + TRACE_STR(STM32_TRACEERR_BADEPTYPE), + TRACE_STR(STM32_TRACEERR_BADGETCONFIG), + TRACE_STR(STM32_TRACEERR_BADGETSETDESC), + TRACE_STR(STM32_TRACEERR_BADGETSTATUS), + TRACE_STR(STM32_TRACEERR_BADSETADDRESS), + TRACE_STR(STM32_TRACEERR_BADSETCONFIG), + TRACE_STR(STM32_TRACEERR_BADSETFEATURE), + TRACE_STR(STM32_TRACEERR_BINDFAILED), + TRACE_STR(STM32_TRACEERR_DISPATCHSTALL), + TRACE_STR(STM32_TRACEERR_DRIVER), + TRACE_STR(STM32_TRACEERR_DRIVERREGISTERED), + TRACE_STR(STM32_TRACEERR_EP0BADCTR), + TRACE_STR(STM32_TRACEERR_EP0SETUPSTALLED), + TRACE_STR(STM32_TRACEERR_EPBUFFER), + TRACE_STR(STM32_TRACEERR_EPDISABLED), + TRACE_STR(STM32_TRACEERR_EPOUTNULLPACKET), + TRACE_STR(STM32_TRACEERR_EPRESERVE), + TRACE_STR(STM32_TRACEERR_INVALIDCTRLREQ), + TRACE_STR(STM32_TRACEERR_INVALIDPARMS), + TRACE_STR(STM32_TRACEERR_IRQREGISTRATION), + TRACE_STR(STM32_TRACEERR_NOTCONFIGURED), + TRACE_STR(STM32_TRACEERR_REQABORTED), + TRACE_STR_END +}; +#endif + +/**************************************************************************** + * Private Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Register Operations + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_getreg + ****************************************************************************/ + +#ifdef CONFIG_STM32_USBDEV_REGDEBUG +static uint16_t stm32_getreg(uint32_t addr) +{ + static uint32_t prevaddr = 0; + static uint16_t preval = 0; + static uint32_t count = 0; + + /* Read the value from the register */ + + uint16_t val = getreg16(addr); + + /* Is this the same value that we read from the same register last time? + * Are we polling the register? If so, suppress some of the output. + */ + + if (addr == prevaddr && val == preval) + { + if (count == 0xffffffff || ++count > 3) + { + if (count == 4) + { + uinfo("...\n"); + } + + return val; + } + } + + /* No this is a new address or value */ + + else + { + /* Did we print "..." for the previous value? */ + + if (count > 3) + { + /* Yes.. then show how many times the value repeated */ + + uinfo("[repeats %d more times]\n", count - 3); + } + + /* Save the new address, value, and count */ + + prevaddr = addr; + preval = val; + count = 1; + } + + /* Show the register value read */ + + uinfo("%08" PRIx32 "->%04x\n", addr, val); + return val; +} +#endif + +/**************************************************************************** + * Name: stm32_putreg + ****************************************************************************/ + +#ifdef CONFIG_STM32_USBDEV_REGDEBUG +static void stm32_putreg(uint16_t val, uint32_t addr) +{ + /* Show the register value being written */ + + uinfo("%08" PRIx32 "<-%04x\n", addr, val); + + /* Write the value */ + + putreg16(val, addr); +} +#endif + +/**************************************************************************** + * Name: stm32_dumpep + ****************************************************************************/ + +#ifdef CONFIG_STM32_USBDEV_REGDEBUG +static void stm32_dumpep(int epno) +{ + uint32_t addr; + + /* Common registers */ + + uinfo("CNTR: %04x\n", getreg16(STM32_USB_CNTR)); + uinfo("ISTR: %04x\n", getreg16(STM32_USB_ISTR)); + uinfo("FNR: %04x\n", getreg16(STM32_USB_FNR)); + uinfo("DADDR: %04x\n", getreg16(STM32_USB_DADDR)); + uinfo("BTABLE: %04x\n", getreg16(STM32_USB_BTABLE)); + + /* Endpoint register */ + + addr = STM32_USB_EPR(epno); + uinfo("EPR%d: [%08" PRIx32 "] %04x\n", epno, addr, getreg16(addr)); + + /* Endpoint descriptor */ + + addr = STM32_USB_BTABLE_ADDR(epno, 0); + uinfo("DESC: %08" PRIx32 "\n", addr); + + /* Endpoint buffer descriptor */ + + addr = STM32_USB_ADDR_TX(epno); + uinfo(" TX ADDR: [%08" PRIx32 "] %04x\n", addr, getreg16(addr)); + + addr = STM32_USB_COUNT_TX(epno); + uinfo(" COUNT: [%08" PRIx32 "] %04x\n", addr, getreg16(addr)); + + addr = STM32_USB_ADDR_RX(epno); + uinfo(" RX ADDR: [%08" PRIx32 "] %04x\n", addr, getreg16(addr)); + + addr = STM32_USB_COUNT_RX(epno); + uinfo(" COUNT: [%08" PRIx32 "] %04x\n", addr, getreg16(addr)); +} +#endif + +/**************************************************************************** + * Name: stm32_checksetup + ****************************************************************************/ + +#ifdef CONFIG_STM32_USBDEV_REGDEBUG +static void stm32_checksetup(void) +{ + uint32_t cfgr = getreg32(STM32_RCC_CFGR); + uint32_t apb1rstr = getreg32(STM32_RCC_APB1RSTR); + uint32_t apb1enr = getreg32(STM32_RCC_APB1ENR); + + uinfo("CFGR: %08" PRIx32 " APB1RSTR: %08" PRIx32 + " APB1ENR: %08" PRIx32 "\n", + cfgr, apb1rstr, apb1enr); + + if ((apb1rstr & RCC_APB1RSTR_USBRST) != 0 || + (apb1enr & RCC_APB1ENR_USBEN) == 0) + { + uerr("ERROR: USB is NOT setup correctly\n"); + } +} +#endif + +/**************************************************************************** + * Low-Level Helpers + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_seteptxcount + ****************************************************************************/ + +static inline void stm32_seteptxcount(uint8_t epno, uint16_t count) +{ + volatile uint32_t *epaddr = (uint32_t *)STM32_USB_COUNT_TX(epno); + *epaddr = count; +} + +/**************************************************************************** + * Name: stm32_seteptxaddr + ****************************************************************************/ + +static inline void stm32_seteptxaddr(uint8_t epno, uint16_t addr) +{ + volatile uint32_t *txaddr = (uint32_t *)STM32_USB_ADDR_TX(epno); + *txaddr = addr; +} + +/**************************************************************************** + * Name: stm32_geteptxaddr + ****************************************************************************/ + +static inline uint16_t stm32_geteptxaddr(uint8_t epno) +{ + volatile uint32_t *txaddr = (uint32_t *)STM32_USB_ADDR_TX(epno); + return (uint16_t)*txaddr; +} + +/**************************************************************************** + * Name: stm32_seteprxcount + ****************************************************************************/ + +static void stm32_seteprxcount(uint8_t epno, uint16_t count) +{ + volatile uint32_t *epaddr = (uint32_t *)STM32_USB_COUNT_RX(epno); + uint32_t rxcount = 0; + uint16_t nblocks; + + /* The upper bits of the RX COUNT value contain the size of allocated + * RX buffer. This is based on a block size of 2 or 32: + * + * USB_COUNT_RX_BL_SIZE not set: + * nblocks is in units of 2 bytes. + * 00000 - not allowed + * 00001 - 2 bytes + * .... + * 11111 - 62 bytes + * + * USB_COUNT_RX_BL_SIZE set: + * 00000 - 32 bytes + * 00001 - 64 bytes + * ... + * 01111 - 512 bytes + * 1xxxx - Not allowed + */ + + if (count > 62) + { + /* Blocks of 32 (with 0 meaning one block of 32) */ + + nblocks = (count >> 5) - 1 ; + DEBUGASSERT(nblocks <= 0x0f); + rxcount = (uint32_t)((nblocks << + USB_COUNT_RX_NUM_BLOCK_SHIFT) | USB_COUNT_RX_BL_SIZE); + } + else if (count > 0) + { + /* Blocks of 2 (with 1 meaning one block of 2) */ + + nblocks = (count + 1) >> 1; + DEBUGASSERT(nblocks > 0 && nblocks < 0x1f); + rxcount = (uint32_t)(nblocks << USB_COUNT_RX_NUM_BLOCK_SHIFT); + } + + *epaddr = rxcount; +} + +/**************************************************************************** + * Name: stm32_geteprxcount + ****************************************************************************/ + +static inline uint16_t stm32_geteprxcount(uint8_t epno) +{ + volatile uint32_t *epaddr = (uint32_t *)STM32_USB_COUNT_RX(epno); + return (*epaddr) & USB_COUNT_RX_MASK; +} + +/**************************************************************************** + * Name: stm32_seteprxaddr + ****************************************************************************/ + +static inline void stm32_seteprxaddr(uint8_t epno, uint16_t addr) +{ + volatile uint32_t *rxaddr = (uint32_t *)STM32_USB_ADDR_RX(epno); + *rxaddr = addr; +} + +/**************************************************************************** + * Name: stm32_seteprxaddr + ****************************************************************************/ + +static inline uint16_t stm32_geteprxaddr(uint8_t epno) +{ + volatile uint32_t *rxaddr = (uint32_t *)STM32_USB_ADDR_RX(epno); + return (uint16_t)*rxaddr; +} + +/**************************************************************************** + * Name: stm32_setepaddress + ****************************************************************************/ + +static inline void stm32_setepaddress(uint8_t epno, uint16_t addr) +{ + uint32_t epaddr = STM32_USB_EPR(epno); + uint16_t regval; + + regval = stm32_getreg(epaddr); + regval &= EPR_NOTOG_MASK; + regval &= ~USB_EPR_EA_MASK; + regval |= (addr << USB_EPR_EA_SHIFT); + stm32_putreg(regval, epaddr); +} + +/**************************************************************************** + * Name: stm32_seteptype + ****************************************************************************/ + +static inline void stm32_seteptype(uint8_t epno, uint16_t type) +{ + uint32_t epaddr = STM32_USB_EPR(epno); + uint16_t regval; + + regval = stm32_getreg(epaddr); + regval &= EPR_NOTOG_MASK; + regval &= ~USB_EPR_EPTYPE_MASK; + regval |= type; + stm32_putreg(regval, epaddr); +} + +/**************************************************************************** + * Name: stm32_clrstatusout + ****************************************************************************/ + +static inline void stm32_clrstatusout(uint8_t epno) +{ + uint32_t epaddr = STM32_USB_EPR(epno); + uint16_t regval; + + /* For a BULK endpoint the EP_KIND bit is used to enabled double buffering; + * for a CONTROL endpoint, it is set to indicate that a status OUT + * transaction is expected. The bit is not used with out endpoint types. + */ + + regval = stm32_getreg(epaddr); + regval &= EPR_NOTOG_MASK; + regval &= ~USB_EPR_EP_KIND; + stm32_putreg(regval, epaddr); +} + +/**************************************************************************** + * Name: stm32_clrrxdtog + ****************************************************************************/ + +static void stm32_clrrxdtog(uint8_t epno) +{ + uint32_t epaddr = STM32_USB_EPR(epno); + uint16_t regval; + + regval = stm32_getreg(epaddr); + if ((regval & USB_EPR_DTOG_RX) != 0) + { + regval &= EPR_NOTOG_MASK; + regval |= USB_EPR_DTOG_RX; + stm32_putreg(regval, epaddr); + } +} + +/**************************************************************************** + * Name: stm32_clrtxdtog + ****************************************************************************/ + +static void stm32_clrtxdtog(uint8_t epno) +{ + uint32_t epaddr = STM32_USB_EPR(epno); + uint16_t regval; + + regval = stm32_getreg(epaddr); + if ((regval & USB_EPR_DTOG_TX) != 0) + { + regval &= EPR_NOTOG_MASK; + regval |= USB_EPR_DTOG_TX; + stm32_putreg(regval, epaddr); + } +} + +/**************************************************************************** + * Name: stm32_clrepctrrx + ****************************************************************************/ + +static void stm32_clrepctrrx(uint8_t epno) +{ + uint32_t epaddr = STM32_USB_EPR(epno); + uint16_t regval; + + regval = stm32_getreg(epaddr); + regval &= EPR_NOTOG_MASK; + regval &= ~USB_EPR_CTR_RX; + stm32_putreg(regval, epaddr); +} + +/**************************************************************************** + * Name: stm32_clrepctrtx + ****************************************************************************/ + +static void stm32_clrepctrtx(uint8_t epno) +{ + uint32_t epaddr = STM32_USB_EPR(epno); + uint16_t regval; + + regval = stm32_getreg(epaddr); + regval &= EPR_NOTOG_MASK; + regval &= ~USB_EPR_CTR_TX; + stm32_putreg(regval, epaddr); +} + +/**************************************************************************** + * Name: stm32_geteptxstatus + ****************************************************************************/ + +static inline uint16_t stm32_geteptxstatus(uint8_t epno) +{ + return (uint16_t)(stm32_getreg(STM32_USB_EPR(epno)) & + USB_EPR_STATTX_MASK); +} + +/**************************************************************************** + * Name: stm32_geteprxstatus + ****************************************************************************/ + +static inline uint16_t stm32_geteprxstatus(uint8_t epno) +{ + return (stm32_getreg(STM32_USB_EPR(epno)) & USB_EPR_STATRX_MASK); +} + +/**************************************************************************** + * Name: stm32_seteptxstatus + ****************************************************************************/ + +static void stm32_seteptxstatus(uint8_t epno, uint16_t state) +{ + uint32_t epaddr = STM32_USB_EPR(epno); + uint16_t regval; + + /* The bits in the STAT_TX field can be toggled by software to set their + * value. When set to 0, the value remains unchanged; when set to one, + * value toggles. + */ + + regval = stm32_getreg(epaddr); + + /* The exclusive OR will set STAT_TX bits to 1 if there value is different + * from the bits requested in 'state' + */ + + regval ^= state; + regval &= EPR_TXDTOG_MASK; + stm32_putreg(regval, epaddr); +} + +/**************************************************************************** + * Name: stm32_seteprxstatus + ****************************************************************************/ + +static void stm32_seteprxstatus(uint8_t epno, uint16_t state) +{ + uint32_t epaddr = STM32_USB_EPR(epno); + uint16_t regval; + + /* The bits in the STAT_RX field can be toggled by software to set their + * value. When set to 0, the value remains unchanged; when set to one, + * value toggles. + */ + + regval = stm32_getreg(epaddr); + + /* The exclusive OR will set STAT_RX bits to 1 if there value is different + * from the bits requested in 'state' + */ + + regval ^= state; + regval &= EPR_RXDTOG_MASK; + stm32_putreg(regval, epaddr); +} + +/**************************************************************************** + * Name: stm32_eptxstalled + ****************************************************************************/ + +static inline bool stm32_eptxstalled(uint8_t epno) +{ + return (stm32_geteptxstatus(epno) == USB_EPR_STATTX_STALL); +} + +/**************************************************************************** + * Name: stm32_eprxstalled + ****************************************************************************/ + +static inline bool stm32_eprxstalled(uint8_t epno) +{ + return (stm32_geteprxstatus(epno) == USB_EPR_STATRX_STALL); +} + +/**************************************************************************** + * Request Helpers + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_copytopma + ****************************************************************************/ + +static void stm32_copytopma(const uint8_t *buffer, + uint16_t pma, uint16_t nbytes) +{ + uint16_t *dest; + uint16_t ms; + uint16_t ls; + int nwords = (nbytes + 1) >> 1; + int i; + + /* Copy loop. Source=user buffer, Dest=packet memory */ + + dest = (uint16_t *)(STM32_USBRAM_BASE + ((uint32_t)pma << 1)); + for (i = nwords; i != 0; i--) + { + /* Read two bytes and pack into on 16-bit word */ + + ls = (uint16_t)(*buffer++); + ms = (uint16_t)(*buffer++); + *dest = ms << 8 | ls; + + /* Source address increments by 2*sizeof(uint8_t) = 2; Dest address + * increments by 2*sizeof(uint16_t) = 4. + */ + + dest += 2; + } +} + +/**************************************************************************** + * Name: stm32_copyfrompma + ****************************************************************************/ + +static inline void +stm32_copyfrompma(uint8_t *buffer, uint16_t pma, uint16_t nbytes) +{ + uint32_t *src; + int nwords = (nbytes + 1) >> 1; + int i; + + /* Copy loop. Source=packet memory, Dest=user buffer */ + + src = (uint32_t *)(STM32_USBRAM_BASE + ((uint32_t)pma << 1)); + for (i = nwords; i != 0; i--) + { + /* Copy 16-bits from packet memory to user buffer. */ + + *(uint16_t *)buffer = *src++; + + /* Source address increments by 1*sizeof(uint32_t) = 4; Dest address + * increments by 2*sizeof(uint8_t) = 2. + */ + + buffer += 2; + } +} + +/**************************************************************************** + * Name: stm32_rqdequeue + ****************************************************************************/ + +static struct stm32_req_s *stm32_rqdequeue(struct stm32_ep_s *privep) +{ + struct stm32_req_s *ret = privep->head; + + if (ret) + { + privep->head = ret->flink; + if (!privep->head) + { + privep->tail = NULL; + } + + ret->flink = NULL; + } + + return ret; +} + +/**************************************************************************** + * Name: stm32_rqenqueue + ****************************************************************************/ + +static void stm32_rqenqueue(struct stm32_ep_s *privep, + struct stm32_req_s *req) +{ + req->flink = NULL; + if (!privep->head) + { + privep->head = req; + privep->tail = req; + } + else + { + privep->tail->flink = req; + privep->tail = req; + } +} + +/**************************************************************************** + * Name: stm32_abortrequest + ****************************************************************************/ + +static inline void +stm32_abortrequest(struct stm32_ep_s *privep, + struct stm32_req_s *privreq, int16_t result) +{ + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_REQABORTED), + (uint16_t)USB_EPNO(privep->ep.eplog)); + + /* Save the result in the request structure */ + + privreq->req.result = result; + + /* Callback to the request completion handler */ + + privreq->req.callback(&privep->ep, &privreq->req); +} + +/**************************************************************************** + * Name: stm32_reqcomplete + ****************************************************************************/ + +static void stm32_reqcomplete(struct stm32_ep_s *privep, int16_t result) +{ + struct stm32_req_s *privreq; + irqstate_t flags; + + /* Remove the completed request at the head of the endpoint request list */ + + flags = enter_critical_section(); + privreq = stm32_rqdequeue(privep); + leave_critical_section(flags); + + if (privreq) + { + /* If endpoint 0, temporarily reflect the state of protocol stalled + * in the callback. + */ + + bool stalled = privep->stalled; + if (USB_EPNO(privep->ep.eplog) == EP0) + { + privep->stalled = (privep->dev->ep0state == EP0STATE_STALLED); + } + + /* Save the result in the request structure */ + + privreq->req.result = result; + + /* Callback to the request completion handler */ + + privreq->flink = NULL; + privreq->req.callback(&privep->ep, &privreq->req); + + /* Restore the stalled indication */ + + privep->stalled = stalled; + } +} + +/**************************************************************************** + * Name: tm32_epwrite + ****************************************************************************/ + +static void stm32_epwrite(struct stm32_usbdev_s *priv, + struct stm32_ep_s *privep, + const uint8_t *buf, uint32_t nbytes) +{ + uint8_t epno = USB_EPNO(privep->ep.eplog); + usbtrace(TRACE_WRITE(epno), nbytes); + + /* Check for a zero-length packet */ + + if (nbytes > 0) + { + /* Copy the data from the user buffer into packet memory for this + * endpoint + */ + + stm32_copytopma(buf, stm32_geteptxaddr(epno), nbytes); + } + + /* Send the packet (might be a null packet nbytes == 0) */ + + stm32_seteptxcount(epno, nbytes); + priv->txstatus = USB_EPR_STATTX_VALID; + + /* Indicate that there is data in the TX packet memory. This will be + * cleared when the next data out interrupt is received. + */ + + privep->txbusy = true; +} + +/**************************************************************************** + * Name: stm32_wrrequest_ep0 + * + * Description: + * Handle the ep0 state on writes. + * + ****************************************************************************/ + +inline static int stm32_wrrequest_ep0(struct stm32_usbdev_s *priv, + struct stm32_ep_s *privep) +{ + int ret; + ret = stm32_wrrequest(priv, privep); + priv->ep0state = ((ret == OK) ? EP0STATE_WRREQUEST : EP0STATE_IDLE); + return ret; +} + +/**************************************************************************** + * Name: stm32_wrrequest + ****************************************************************************/ + +static int stm32_wrrequest(struct stm32_usbdev_s *priv, + struct stm32_ep_s *privep) +{ + struct stm32_req_s *privreq; + uint8_t *buf; + uint8_t epno; + int nbytes; + int bytesleft; + + /* We get here when an IN endpoint interrupt occurs. So now we know that + * there is no TX transfer in progress. + */ + + privep->txbusy = false; + + /* Check the request from the head of the endpoint request queue */ + + privreq = stm32_rqpeek(privep); + if (!privreq) + { + /* There is no TX transfer in progress and no new pending TX + * requests to send. + */ + + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPINQEMPTY), 0); + return -ENOENT; + } + + epno = USB_EPNO(privep->ep.eplog); + uinfo("epno=%d req=%p: len=%zu xfrd=%zu nullpkt=%d\n", + epno, privreq, privreq->req.len, + privreq->req.xfrd, privep->txnullpkt); + UNUSED(epno); + + /* Get the number of bytes left to be sent in the packet */ + + bytesleft = privreq->req.len - privreq->req.xfrd; + nbytes = bytesleft; + +#warning "REVISIT: If the EP supports double buffering, then we can do better" + + /* Either (1) we are committed to sending the null packet + * (because txnullpkt == 1 && nbytes == 0), or (2) we have not yet send + * the last packet (nbytes > 0). + * In either case, it is appropriate to clearn txnullpkt now. + */ + + privep->txnullpkt = 0; + + /* If we are not sending a NULL packet, then clip the size to maxpacket + * and check if we need to send a following NULL packet. + */ + + if (nbytes > 0) + { + /* Either send the maxpacketsize or all of the remaining data in + * the request. + */ + + if (nbytes >= privep->ep.maxpacket) + { + nbytes = privep->ep.maxpacket; + + /* Handle the case where this packet is exactly the + * maxpacketsize. Do we need to send a zero-length packet + * in this case? + */ + + if (bytesleft == privep->ep.maxpacket && + (privreq->req.flags & USBDEV_REQFLAGS_NULLPKT) != 0) + { + privep->txnullpkt = 1; + } + } + } + + /* Send the packet (might be a null packet nbytes == 0) */ + + buf = privreq->req.buf + privreq->req.xfrd; + stm32_epwrite(priv, privep, buf, nbytes); + + /* Update for the next data IN interrupt */ + + privreq->req.xfrd += nbytes; + bytesleft = privreq->req.len - privreq->req.xfrd; + + /* If all of the bytes were sent (including any final null packet) + * then we are finished with the request buffer). + */ + + if (bytesleft == 0 && !privep->txnullpkt) + { + /* Return the write request to the class driver */ + + usbtrace(TRACE_COMPLETE(USB_EPNO(privep->ep.eplog)), + privreq->req.xfrd); + privep->txnullpkt = 0; + stm32_reqcomplete(privep, OK); + } + + return OK; +} + +/**************************************************************************** + * Name: stm32_ep0_rdrequest + * + * Description: + * This function is called from the stm32_ep0out handler when the ep0state + * is EP0STATE_SETUP_OUT and upon new incoming data is available in the + * endpoint 0's buffer. + * This function will simply copy the OUT data into ep0data. + * + ****************************************************************************/ + +static inline int stm32_ep0_rdrequest(struct stm32_usbdev_s *priv) +{ + uint32_t src; + int pmalen; + int readlen; + + /* Get the number of bytes to read from packet memory */ + + pmalen = stm32_geteprxcount(EP0); + + uinfo("EP0: pmalen=%d\n", pmalen); + usbtrace(TRACE_READ(EP0), pmalen); + + /* Read the data into our special buffer for SETUP data */ + + readlen = MIN(CONFIG_USBDEV_SETUP_MAXDATASIZE, pmalen); + src = stm32_geteprxaddr(EP0); + + /* Receive the next packet */ + + stm32_copyfrompma(&priv->ep0data[0], src, readlen); + + /* Now we can process the setup command */ + + priv->ep0state = EP0STATE_SETUP_READY; + priv->ep0datlen = readlen; + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EP0SETUPOUTDATA), + readlen); + + stm32_ep0setup(priv); + priv->ep0datlen = 0; /* mark the date consumed */ + + return OK; +} + +/**************************************************************************** + * Name: stm32_rdrequest + ****************************************************************************/ + +static int stm32_rdrequest(struct stm32_usbdev_s *priv, + struct stm32_ep_s *privep) +{ + struct stm32_req_s *privreq; + uint32_t src; + uint8_t *dest; + uint8_t epno; + int pmalen; + int readlen; + + /* Check the request from the head of the endpoint request queue */ + + epno = USB_EPNO(privep->ep.eplog); + privreq = stm32_rqpeek(privep); + if (!privreq) + { + /* Incoming data available in PMA, but no packet to receive the data. + * Mark that the RX data is pending and hope that a packet is returned + * soon. + */ + + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPOUTQEMPTY), epno); + return -ENOENT; + } + + uinfo("EP%d: len=%zu xfrd=%zu\n", + epno, privreq->req.len, privreq->req.xfrd); + + /* Ignore any attempt to receive a zero length packet */ + + if (privreq->req.len == 0) + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EPOUTNULLPACKET), 0); + stm32_reqcomplete(privep, OK); + return OK; + } + + usbtrace(TRACE_READ(USB_EPNO(privep->ep.eplog)), privreq->req.xfrd); + + /* Get the source and destination transfer addresses */ + + dest = privreq->req.buf + privreq->req.xfrd; + src = stm32_geteprxaddr(epno); + + /* Get the number of bytes to read from packet memory */ + + pmalen = stm32_geteprxcount(epno); + readlen = MIN(privreq->req.len, pmalen); + + /* Receive the next packet */ + + stm32_copyfrompma(dest, src, readlen); + + /* If the receive buffer is full or this is a partial packet, + * then we are finished with the request buffer). + */ + + privreq->req.xfrd += readlen; + if (pmalen < privep->ep.maxpacket || privreq->req.xfrd >= privreq->req.len) + { + /* Return the read request to the class driver. */ + + usbtrace(TRACE_COMPLETE(epno), privreq->req.xfrd); + stm32_reqcomplete(privep, OK); + } + + return OK; +} + +/**************************************************************************** + * Name: stm32_cancelrequests + ****************************************************************************/ + +static void stm32_cancelrequests(struct stm32_ep_s *privep) +{ + while (!stm32_rqempty(privep)) + { + usbtrace(TRACE_COMPLETE(USB_EPNO(privep->ep.eplog)), + (stm32_rqpeek(privep))->req.xfrd); + stm32_reqcomplete(privep, -ESHUTDOWN); + } +} + +/**************************************************************************** + * Interrupt Level Processing + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_dispatchrequest + ****************************************************************************/ + +static void stm32_dispatchrequest(struct stm32_usbdev_s *priv) +{ + int ret; + + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_DISPATCH), 0); + if (priv && priv->driver) + { + /* Forward to the control request to the class driver implementation */ + + ret = CLASS_SETUP(priv->driver, &priv->usbdev, &priv->ctrl, + priv->ep0data, priv->ep0datlen); + if (ret < 0) + { + /* Stall on failure */ + + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_DISPATCHSTALL), 0); + priv->ep0state = EP0STATE_STALLED; + } + } +} + +/**************************************************************************** + * Name: stm32_epdone + ****************************************************************************/ + +static void stm32_epdone(struct stm32_usbdev_s *priv, uint8_t epno) +{ + struct stm32_ep_s *privep; + uint16_t epr; + + /* Decode and service non control endpoints interrupt */ + + epr = stm32_getreg(STM32_USB_EPR(epno)); + privep = &priv->eplist[epno]; + + /* OUT: host-to-device + * CTR_RX is set by the hardware when an OUT/SETUP transaction + * successfully completed on this endpoint. + */ + + if ((epr & USB_EPR_CTR_RX) != 0) + { + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPOUTDONE), epr); + + /* Handle read requests. First check if a read request is available to + * accept the host data. + */ + + if (!stm32_rqempty(privep)) + { + /* Read host data into the current read request */ + + stm32_rdrequest(priv, privep); + + /* "After the received data is processed, the application software + * should set the STAT_RX bits to '11' (Valid) in the USB_EPnR, + * enabling further transactions. " + */ + + priv->rxstatus = USB_EPR_STATRX_VALID; + } + + /* NAK further OUT packets if there there no more read requests */ + + if (stm32_rqempty(privep)) + { + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPOUTPENDING), + (uint16_t)epno); + + /* Mark the RX processing as pending and NAK any OUT actions + * on this endpoint. "While the STAT_RX bits are equal to '10' + * (NAK), any OUT request addressed to that endpoint is NAKed, + * indicating a flow control condition: the USB host will retry + * the transaction until it succeeds." + */ + + priv->rxstatus = USB_EPR_STATRX_NAK; + priv->rxpending = true; + } + + /* Clear the interrupt status and set the new RX status */ + + stm32_clrepctrrx(epno); + stm32_seteprxstatus(epno, priv->rxstatus); + } + + /* IN: device-to-host + * CTR_TX is set when an IN transaction successfully completes on + * an endpoint + */ + + else if ((epr & USB_EPR_CTR_TX) != 0) + { + /* Clear interrupt status */ + + stm32_clrepctrtx(epno); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPINDONE), epr); + + /* Handle write requests */ + + priv->txstatus = USB_EPR_STATTX_NAK; + if (epno == EP0) + { + stm32_wrrequest_ep0(priv, privep); + } + else + { + stm32_wrrequest(priv, privep); + } + + /* Set the new TX status */ + + stm32_seteptxstatus(epno, priv->txstatus); + } +} + +/**************************************************************************** + * Name: stm32_setdevaddr + ****************************************************************************/ + +static void stm32_setdevaddr(struct stm32_usbdev_s *priv, uint8_t value) +{ + int epno; + + /* Set address in every allocated endpoint */ + + for (epno = 0; epno < STM32_NENDPOINTS; epno++) + { + if (stm32_epreserved(priv, epno)) + { + stm32_setepaddress((uint8_t)epno, (uint8_t)epno); + } + } + + /* Set the device address and enable function */ + + stm32_putreg(value | USB_DADDR_EF, STM32_USB_DADDR); +} + +/**************************************************************************** + * Name: stm32_ep0setup + ****************************************************************************/ + +static void stm32_ep0setup(struct stm32_usbdev_s *priv) +{ + struct stm32_ep_s *ep0 = &priv->eplist[EP0]; + struct stm32_req_s *privreq = stm32_rqpeek(ep0); + struct stm32_ep_s *privep; + union wb_u value; + union wb_u index; + union wb_u len; + union wb_u response; + bool handled = false; + uint8_t epno; + int nbytes = 0; /* Assume zero-length packet */ + + /* Terminate any pending requests (doesn't work if the pending request + * was a zero-length transfer!) + */ + + while (!stm32_rqempty(ep0)) + { + int16_t result = OK; + if (privreq->req.xfrd != privreq->req.len) + { + result = -EPROTO; + } + + usbtrace(TRACE_COMPLETE(ep0->ep.eplog), privreq->req.xfrd); + stm32_reqcomplete(ep0, result); + } + + /* Assume NOT stalled; no TX in progress */ + + ep0->stalled = 0; + ep0->txbusy = 0; + + value.w = 0; + index.w = 0; + len.w = 0; + response.w = 0; + + /* Check to see if called from the DATA phase of a SETUP Transfer */ + + if (priv->ep0state != EP0STATE_SETUP_READY) + { + /* Not the data phase */ + + /* Get a 32-bit PMA address and use that to get the 8-byte setup + * request + */ + + stm32_copyfrompma((uint8_t *)&priv->ctrl, stm32_geteprxaddr(EP0), + USB_SIZEOF_CTRLREQ); + + /* And extract the little-endian 16-bit values to host order */ + + value.w = GETUINT16(priv->ctrl.value); + index.w = GETUINT16(priv->ctrl.index); + len.w = GETUINT16(priv->ctrl.len); + + uinfo("SETUP: type=%02x req=%02x value=%04x index=%04x len=%04x\n", + priv->ctrl.type, priv->ctrl.req, value.w, index.w, len.w); + + /* Is this an setup with OUT and data of length > 0 */ + + if (USB_REQ_ISOUT(priv->ctrl.type) && len.w > 0) + { + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EP0SETUPOUT), len.w); + + /* At this point priv->ctrl is the setup packet. */ + + priv->ep0state = EP0STATE_SETUP_OUT; + return; + } + else + { + priv->ep0state = EP0STATE_SETUP_READY; + } + } + + /* Dispatch any non-standard requests */ + + if ((priv->ctrl.type & USB_REQ_TYPE_MASK) != USB_REQ_TYPE_STANDARD) + { + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_NOSTDREQ), priv->ctrl.type); + + /* Let the class implementation handle all non-standar requests */ + + stm32_dispatchrequest(priv); + return; + } + + /* Handle standard request. Pick off the things of interest to the + * USB device controller driver; pass what is left to the class driver + */ + + switch (priv->ctrl.req) + { + case USB_REQ_GETSTATUS: + { + /* type: device-to-host; recipient = device, interface, endpoint + * value: 0 + * index: zero interface endpoint + * len: 2; data = status + */ + + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_GETSTATUS), + priv->ctrl.type); + if (len.w != 2 || (priv->ctrl.type & + USB_REQ_DIR_IN) == 0 || + index.b[MSB] != 0 || value.w != 0) + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADEPGETSTATUS), 0); + priv->ep0state = EP0STATE_STALLED; + } + else + { + switch (priv->ctrl.type & USB_REQ_RECIPIENT_MASK) + { + case USB_REQ_RECIPIENT_ENDPOINT: + { + epno = USB_EPNO(index.b[LSB]); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPGETSTATUS), + epno); + if (epno >= STM32_NENDPOINTS) + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADEPGETSTATUS), + epno); + priv->ep0state = EP0STATE_STALLED; + } + else + { + response.w = 0; /* Not stalled */ + nbytes = 2; /* Response size: 2 bytes */ + + if (USB_ISEPIN(index.b[LSB])) + { + /* IN endpoint */ + + if (stm32_eptxstalled(epno)) + { + /* IN Endpoint stalled */ + + response.b[LSB] = 1; /* Stalled */ + } + } + else + { + /* OUT endpoint */ + + if (stm32_eprxstalled(epno)) + { + /* OUT Endpoint stalled */ + + response.b[LSB] = 1; /* Stalled */ + } + } + } + } + break; + + case USB_REQ_RECIPIENT_DEVICE: + { + if (index.w == 0) + { + usbtrace(TRACE_INTDECODE( + STM32_TRACEINTID_DEVGETSTATUS), 0); + + /* Features: Remote Wakeup=YES; selfpowered=? */ + + response.w = 0; + response.b[LSB] = (priv->selfpowered << + USB_FEATURE_SELFPOWERED) | + (1 << USB_FEATURE_REMOTEWAKEUP); + nbytes = 2; /* Response size: 2 bytes */ + } + else + { + usbtrace(TRACE_DEVERROR( + STM32_TRACEERR_BADDEVGETSTATUS), 0); + priv->ep0state = EP0STATE_STALLED; + } + } + break; + + case USB_REQ_RECIPIENT_INTERFACE: + { + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_IFGETSTATUS), 0); + response.w = 0; + nbytes = 2; /* Response size: 2 bytes */ + } + break; + + default: + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADGETSTATUS), 0); + priv->ep0state = EP0STATE_STALLED; + } + break; + } + } + } + break; + + case USB_REQ_CLEARFEATURE: + { + /* type: host-to-device; recipient = device, interface or endpoint + * value: feature selector + * index: zero interface endpoint; + * len: zero, data = none + */ + + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_CLEARFEATURE), + priv->ctrl.type); + if ((priv->ctrl.type & USB_REQ_RECIPIENT_MASK) != + USB_REQ_RECIPIENT_ENDPOINT) + { + /* Let the class implementation handle all recipients + * (except for the endpoint recipient) + */ + + stm32_dispatchrequest(priv); + handled = true; + } + else + { + /* Endpoint recipient */ + + epno = USB_EPNO(index.b[LSB]); + if (epno < STM32_NENDPOINTS && index.b[MSB] == 0 && + value.w == USB_FEATURE_ENDPOINTHALT && len.w == 0) + { + privep = &priv->eplist[epno]; + privep->halted = 0; + stm32_epstall(&privep->ep, true); + } + else + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADCLEARFEATURE), 0); + priv->ep0state = EP0STATE_STALLED; + } + } + } + break; + + case USB_REQ_SETFEATURE: + { + /* type: host-to-device; recipient = device, interface, endpoint + * value: feature selector + * index: zero interface endpoint; + * len: 0; data = none + */ + + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SETFEATURE), + priv->ctrl.type); + if (((priv->ctrl.type & USB_REQ_RECIPIENT_MASK) == + USB_REQ_RECIPIENT_DEVICE) && + value.w == USB_FEATURE_TESTMODE) + { + /* Special case recipient=device test mode */ + + uinfo("test mode: %d\n", index.w); + } + else if ((priv->ctrl.type & USB_REQ_RECIPIENT_MASK) != + USB_REQ_RECIPIENT_ENDPOINT) + { + /* The class driver handles all recipients except + * recipient=endpoint + */ + + stm32_dispatchrequest(priv); + handled = true; + } + else + { + /* Handler recipient=endpoint */ + + epno = USB_EPNO(index.b[LSB]); + if (epno < STM32_NENDPOINTS && index.b[MSB] == 0 && + value.w == USB_FEATURE_ENDPOINTHALT && len.w == 0) + { + privep = &priv->eplist[epno]; + privep->halted = 1; + stm32_epstall(&privep->ep, false); + } + else + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADSETFEATURE), 0); + priv->ep0state = EP0STATE_STALLED; + } + } + } + break; + + case USB_REQ_SETADDRESS: + { + /* type: host-to-device; recipient = device + * value: device address + * index: 0 + * len: 0; data = none + */ + + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EP0SETUPSETADDRESS), + value.w); + if ((priv->ctrl.type & USB_REQ_RECIPIENT_MASK) != + USB_REQ_RECIPIENT_DEVICE || + index.w != 0 || len.w != 0 || value.w > 127) + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADSETADDRESS), 0); + priv->ep0state = EP0STATE_STALLED; + } + /* Note that setting of the device address will be deferred. + * A zero-length packet will be sent and the device address + * will be set when the zero- length packet transfer completes. + */ + } + break; + + case USB_REQ_GETDESCRIPTOR: + /* type: device-to-host; recipient = device + * value: descriptor type and index + * index: 0 or language ID; + * len: descriptor len; data = descriptor + */ + + case USB_REQ_SETDESCRIPTOR: + /* type: host-to-device; recipient = device + * value: descriptor type and index + * index: 0 or language ID; + * len: descriptor len; data = descriptor + */ + + { + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_GETSETDESC), + priv->ctrl.type); + + /* The request seems valid... + * let the class implementation handle it + */ + + stm32_dispatchrequest(priv); + handled = true; + } + break; + + case USB_REQ_GETCONFIGURATION: + /* type: device-to-host; recipient = device + * value: 0; + * index: 0; + * len: 1; data = configuration value + */ + + { + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_GETCONFIG), + priv->ctrl.type); + if ((priv->ctrl.type & USB_REQ_RECIPIENT_MASK) == + USB_REQ_RECIPIENT_DEVICE && + value.w == 0 && index.w == 0 && len.w == 1) + { + /* The request seems valid... + * let the class implementation handle it + */ + + stm32_dispatchrequest(priv); + handled = true; + } + else + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADGETCONFIG), 0); + priv->ep0state = EP0STATE_STALLED; + } + } + break; + + case USB_REQ_SETCONFIGURATION: + /* type: host-to-device; recipient = device + * value: configuration value + * index: 0; + * len: 0; data = none + */ + + { + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SETCONFIG), + priv->ctrl.type); + if ((priv->ctrl.type & USB_REQ_RECIPIENT_MASK) == + USB_REQ_RECIPIENT_DEVICE && + index.w == 0 && len.w == 0) + { + /* The request seems valid... + * let the class implementation handle it + */ + + stm32_dispatchrequest(priv); + handled = true; + } + else + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADSETCONFIG), 0); + priv->ep0state = EP0STATE_STALLED; + } + } + break; + + case USB_REQ_GETINTERFACE: + /* type: device-to-host; recipient = interface + * value: 0 + * index: interface; + * len: 1; data = alt interface + */ + + case USB_REQ_SETINTERFACE: + /* type: host-to-device; recipient = interface + * value: alternate setting + * index: interface; + * len: 0; data = none + */ + + { + /* Let the class implementation handle the request */ + + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_GETSETIF), + priv->ctrl.type); + stm32_dispatchrequest(priv); + handled = true; + } + break; + + case USB_REQ_SYNCHFRAME: + /* type: device-to-host; recipient = endpoint + * value: 0 + * index: endpoint; + * len: 2; data = frame number + */ + + { + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SYNCHFRAME), 0); + } + break; + + default: + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDCTRLREQ), + priv->ctrl.req); + priv->ep0state = EP0STATE_STALLED; + } + break; + } + + /* At this point, the request has been handled and there are three possible + * outcomes: + * + * 1. The setup request was successfully handled above and a response + * packet must be sent (may be a zero length packet). + * 2. The request was successfully handled by the class implementation. + * In case, the EP0 IN response has already been queued and the local + * variable 'handled' will be set to true and + * ep0state != EP0STATE_STALLED; + * 3. An error was detected in either the above logic or by the class + * implementation logic. In either case, priv->state will be set + * EP0STATE_STALLED to indicate this case. + * + * NOTE: + * Non-standard requests are a special case. They are handled by the + * class implementation and this function returned early above, skipping + * this logic altogether. + */ + + if (priv->ep0state != EP0STATE_STALLED && !handled) + { + /* We will response. First, restrict the data length to the length + * requested in the setup packet + */ + + if (nbytes > len.w) + { + nbytes = len.w; + } + + /* Send the response (might be a zero-length packet) */ + + stm32_epwrite(priv, ep0, response.b, nbytes); + priv->ep0state = EP0STATE_IDLE; + } +} + +/**************************************************************************** + * Name: stm32_ep0in + ****************************************************************************/ + +static void stm32_ep0in(struct stm32_usbdev_s *priv) +{ + /* There is no longer anything in the EP0 TX packet memory */ + + priv->eplist[EP0].txbusy = false; + + /* Are we processing the completion of one packet of an outgoing request + * from the class driver? + */ + + if (priv->ep0state == EP0STATE_WRREQUEST) + { + stm32_wrrequest_ep0(priv, &priv->eplist[EP0]); + } + + /* No.. Are we processing the completion of a status response? */ + + else if (priv->ep0state == EP0STATE_IDLE) + { + /* Look at the saved SETUP command. Was it a SET ADDRESS request? + * If so, then now is the time to set the address. + */ + + if (priv->ctrl.req == USB_REQ_SETADDRESS && + (priv->ctrl.type & REQRECIPIENT_MASK) == + (USB_REQ_TYPE_STANDARD | USB_REQ_RECIPIENT_DEVICE)) + { + union wb_u value; + value.w = GETUINT16(priv->ctrl.value); + stm32_setdevaddr(priv, value.b[LSB]); + } + } + else + { + priv->ep0state = EP0STATE_STALLED; + } +} + +/**************************************************************************** + * Name: stm32_ep0out + ****************************************************************************/ + +static void stm32_ep0out(struct stm32_usbdev_s *priv) +{ + int ret; + + struct stm32_ep_s *privep = &priv->eplist[EP0]; + switch (priv->ep0state) + { + case EP0STATE_RDREQUEST: /* Read request in progress */ + case EP0STATE_IDLE: /* No transfer in progress */ + ret = stm32_rdrequest(priv, privep); + priv->ep0state = ((ret == OK) ? EP0STATE_RDREQUEST : EP0STATE_IDLE); + break; + + case EP0STATE_SETUP_OUT: /* SETUP was waiting for data */ + ret = stm32_ep0_rdrequest(priv); /* Off load the data and run the + * last set up command with the OUT + * data + */ + priv->ep0state = EP0STATE_IDLE; /* There is no notion of receiving OUT + * data greater then the length of + * CONFIG_USBDEV_SETUP_MAXDATASIZE + * so we are done + */ + break; + + default: + /* Unexpected state OR host aborted the OUT transfer before it + * completed, STALL the endpoint in either case + */ + + priv->ep0state = EP0STATE_STALLED; + break; + } +} + +/**************************************************************************** + * Name: stm32_ep0done + ****************************************************************************/ + +static inline void stm32_ep0done(struct stm32_usbdev_s *priv, uint16_t istr) +{ + uint16_t epr; + + /* Initialize RX and TX status. We shouldn't have to actually look at the + * status because the hardware is supposed to set the both RX and TX status + * to NAK when an EP0 SETUP occurs (of course, this might not be a setup) + */ + + priv->rxstatus = USB_EPR_STATRX_NAK; + priv->txstatus = USB_EPR_STATTX_NAK; + + /* Set both RX and TX status to NAK */ + + stm32_seteprxstatus(EP0, USB_EPR_STATRX_NAK); + stm32_seteptxstatus(EP0, USB_EPR_STATTX_NAK); + + /* Check the direction bit to determine if this the completion of an EP0 + * packet sent to or received from the host PC. + */ + + if ((istr & USB_ISTR_DIR) == 0) + { + /* EP0 IN: device-to-host (DIR=0) */ + + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EP0IN), istr); + stm32_clrepctrtx(EP0); + stm32_ep0in(priv); + } + else + { + /* EP0 OUT: host-to-device (DIR=1) */ + + epr = stm32_getreg(STM32_USB_EPR(EP0)); + + /* CTR_TX is set when an IN transaction successfully + * completes on an endpoint + */ + + if ((epr & USB_EPR_CTR_TX) != 0) + { + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EP0INDONE), epr); + stm32_clrepctrtx(EP0); + stm32_ep0in(priv); + } + + /* SETUP is set by the hardware when the last completed + * transaction was a control endpoint SETUP + */ + + else if ((epr & USB_EPR_SETUP) != 0) + { + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EP0SETUPDONE), epr); + stm32_clrepctrrx(EP0); + stm32_ep0setup(priv); + } + + /* Set by the hardware when an OUT/SETUP transaction successfully + * completed on this endpoint. + */ + + else if ((epr & USB_EPR_CTR_RX) != 0) + { + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EP0OUTDONE), epr); + stm32_clrepctrrx(EP0); + stm32_ep0out(priv); + } + + /* None of the above */ + + else + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EP0BADCTR), epr); + return; /* Does this ever happen? */ + } + } + + /* Make sure that the EP0 packet size is still OK (superstitious?) */ + + stm32_seteprxcount(EP0, STM32_EP0MAXPACKET); + + /* Now figure out the new RX/TX status. Here are all possible + * consequences of the above EP0 operations: + * + * rxstatus txstatus ep0state MEANING + * -------- -------- --------- --------------------------------- + * NAK NAK IDLE Nothing happened + * NAK VALID IDLE EP0 response sent from USBDEV driver + * NAK VALID WRREQUEST EP0 response sent from class driver + * NAK --- STALL Some protocol error occurred + * + * First handle the STALL condition: + */ + + if (priv->ep0state == EP0STATE_STALLED) + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EP0SETUPSTALLED), + priv->ep0state); + priv->rxstatus = USB_EPR_STATRX_STALL; + priv->txstatus = USB_EPR_STATTX_STALL; + } + + /* Was a transmission started? If so, txstatus will be VALID. The + * only special case to handle is when both are set to NAK. In that + * case, we need to set RX status to VALID in order to accept the next + * SETUP request. + */ + + else if (priv->rxstatus == USB_EPR_STATRX_NAK && + priv->txstatus == USB_EPR_STATTX_NAK) + { + priv->rxstatus = USB_EPR_STATRX_VALID; + } + + /* Now set the new TX and RX status */ + + stm32_seteprxstatus(EP0, priv->rxstatus); + stm32_seteptxstatus(EP0, priv->txstatus); +} + +/**************************************************************************** + * Name: stm32_lptransfer + ****************************************************************************/ + +static void stm32_lptransfer(struct stm32_usbdev_s *priv) +{ + uint8_t epno; + uint16_t istr; + + /* Stay in loop while LP interrupts are pending */ + + while (((istr = stm32_getreg(STM32_USB_ISTR)) & USB_ISTR_CTR) != 0) + { + stm32_putreg((uint16_t)~USB_ISTR_CTR, STM32_USB_ISTR); + + /* Extract highest priority endpoint number */ + + epno = (uint8_t)(istr & USB_ISTR_EPID_MASK); + + /* Handle EP0 completion events */ + + if (epno == 0) + { + stm32_ep0done(priv, istr); + } + + /* Handle other endpoint completion events */ + + else + { + stm32_epdone(priv, epno); + } + } +} + +/**************************************************************************** + * Name: stm32_hpinterrupt + ****************************************************************************/ + +static int stm32_hpinterrupt(int irq, void *context, void *arg) +{ + /* For now there is only one USB controller, but we will always refer to + * it using a pointer to make any future ports to multiple USB controllers + * easier. + */ + + struct stm32_usbdev_s *priv = &g_usbdev; + uint16_t istr; + uint8_t epno; + + /* High priority interrupts are only triggered by a correct transfer event + * for isochronous and double-buffer bulk transfers. + */ + + istr = stm32_getreg(STM32_USB_ISTR); + usbtrace(TRACE_INTENTRY(STM32_TRACEINTID_HPINTERRUPT), istr); + while ((istr & USB_ISTR_CTR) != 0) + { + stm32_putreg((uint16_t)~USB_ISTR_CTR, STM32_USB_ISTR); + + /* Extract highest priority endpoint number */ + + epno = (uint8_t)(istr & USB_ISTR_EPID_MASK); + + /* And handle the completion event */ + + stm32_epdone(priv, epno); + + /* Fetch the status again for the next time through the loop */ + + istr = stm32_getreg(STM32_USB_ISTR); + } + + usbtrace(TRACE_INTEXIT(STM32_TRACEINTID_HPINTERRUPT), 0); + return OK; +} + +/**************************************************************************** + * Name: stm32_lpinterrupt + ****************************************************************************/ + +static int stm32_lpinterrupt(int irq, void *context, void *arg) +{ + /* For now there is only one USB controller, but we will always refer to + * it using a pointer to make any future ports to multiple USB controllers + * easier. + */ + + struct stm32_usbdev_s *priv = &g_usbdev; + uint16_t istr = stm32_getreg(STM32_USB_ISTR); + + usbtrace(TRACE_INTENTRY(STM32_TRACEINTID_LPINTERRUPT), istr); + + /* Handle Reset interrupts. When this event occurs, the peripheral is left + * in the same conditions it is left by the system reset (but with the + * USB controller enabled). + */ + + if ((istr & USB_ISTR_RESET) != 0) + { + /* Reset interrupt received. Clear the RESET interrupt status. */ + + stm32_putreg(~USB_ISTR_RESET, STM32_USB_ISTR); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_RESET), istr); + + /* Restore our power-up state and exit now because istr is no longer + * valid. + */ + + stm32_reset(priv); + goto exit_lpinterrupt; + } + + /* Handle Wakeup interrupts. + * This interrupt is only enable while the USB is suspended. + */ + + if ((istr & USB_ISTR_WKUP & priv->imask) != 0) + { + /* Wakeup interrupt received. Clear the WKUP interrupt status. The + * cause of the resume is indicated in the FNR register + */ + + stm32_putreg(~USB_ISTR_WKUP, STM32_USB_ISTR); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_WKUP), + stm32_getreg(STM32_USB_FNR)); + + /* Perform the wakeup action */ + + stm32_initresume(priv); + priv->rsmstate = RSMSTATE_IDLE; + + /* Disable ESOF polling, disable the wakeup interrupt, and + * re-enable the suspend interrupt. Clear any pending SUSP + * interrupts. + */ + + stm32_setimask(priv, USB_CNTR_SUSPM, USB_CNTR_ESOFM | USB_CNTR_WKUPM); + stm32_putreg(~USB_CNTR_SUSPM, STM32_USB_ISTR); + } + + if ((istr & USB_ISTR_SUSP & priv->imask) != 0) + { + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SUSP), 0); + stm32_suspend(priv); + + /* Clear of the ISTR bit must be done after setting + * of USB_CNTR_FSUSP + */ + + stm32_putreg(~USB_ISTR_SUSP, STM32_USB_ISTR); + } + + if ((istr & USB_ISTR_ESOF & priv->imask) != 0) + { + stm32_putreg(~USB_ISTR_ESOF, STM32_USB_ISTR); + + /* Resume handling timing is made with ESOFs */ + + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_ESOF), 0); + stm32_esofpoll(priv); + } + + if ((istr & USB_ISTR_CTR & priv->imask) != 0) + { + /* Low priority endpoint correct transfer interrupt */ + + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_LPCTR), istr); + stm32_lptransfer(priv); + } + +exit_lpinterrupt: + usbtrace(TRACE_INTEXIT(STM32_TRACEINTID_LPINTERRUPT), + stm32_getreg(STM32_USB_EP0R)); + return OK; +} + +/**************************************************************************** + * Name: stm32_setimask + ****************************************************************************/ + +static void +stm32_setimask(struct stm32_usbdev_s *priv, + uint16_t setbits, uint16_t clrbits) +{ + uint16_t regval; + + /* Adjust the interrupt mask bits in the shadow copy first */ + + priv->imask &= ~clrbits; + priv->imask |= setbits; + + /* Then make the interrupt mask bits in the CNTR register match the shadow + * register (Hmmm... who is shadowing whom?) + */ + + regval = stm32_getreg(STM32_USB_CNTR); + regval &= ~USB_CNTR_ALLINTS; + regval |= priv->imask; + stm32_putreg(regval, STM32_USB_CNTR); +} + +/**************************************************************************** + * Suspend/Resume Helpers + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_suspend + ****************************************************************************/ + +static void stm32_suspend(struct stm32_usbdev_s *priv) +{ + uint16_t regval; + + /* Notify the class driver of the suspend event */ + + if (priv->driver) + { + CLASS_SUSPEND(priv->driver, &priv->usbdev); + } + + /* Disable ESOF polling, disable the SUSP interrupt, and enable the WKUP + * interrupt. Clear any pending WKUP interrupt. + */ + + stm32_setimask(priv, USB_CNTR_WKUPM, USB_CNTR_ESOFM | USB_CNTR_SUSPM); + stm32_putreg(~USB_ISTR_WKUP, STM32_USB_ISTR); + + /* Set the FSUSP bit in the CNTR register. This activates suspend mode + * within the USB peripheral and disables further SUSP interrupts. + */ + + regval = stm32_getreg(STM32_USB_CNTR); + regval |= USB_CNTR_FSUSP; + stm32_putreg(regval, STM32_USB_CNTR); + + /* If we are not a self-powered device, the got to low-power mode */ + + if (!priv->selfpowered) + { + /* Setting LPMODE in the CNTR register removes static power + * consumption in the USB analog transceivers but keeps them + * able to detect resume activity + */ + + regval = stm32_getreg(STM32_USB_CNTR); + regval |= USB_CNTR_LPMODE; + stm32_putreg(regval, STM32_USB_CNTR); + } + + /* Let the board-specific logic know that we have entered the suspend + * state + */ + + stm32_usbsuspend((struct usbdev_s *)priv, false); +} + +/**************************************************************************** + * Name: stm32_initresume + ****************************************************************************/ + +static void stm32_initresume(struct stm32_usbdev_s *priv) +{ + uint16_t regval; + + /* This function is called when either (1) a WKUP interrupt is received + * from the host PC, or (2) the class device implementation calls the + * wakeup() method. + */ + + /* Clear the USB low power mode (lower power mode was not set if this is + * a self-powered device. Also, low power mode is automatically cleared by + * hardware when a WKUP interrupt event occurs). + */ + + regval = stm32_getreg(STM32_USB_CNTR); + regval &= (~USB_CNTR_LPMODE); + stm32_putreg(regval, STM32_USB_CNTR); + + /* Restore full power -- whatever that means for this particular board */ + + stm32_usbsuspend((struct usbdev_s *)priv, true); + + /* Reset FSUSP bit and enable normal interrupt handling */ + + stm32_putreg(STM32_CNTR_SETUP, STM32_USB_CNTR); + + /* Notify the class driver of the resume event */ + + if (priv->driver) + { + CLASS_RESUME(priv->driver, &priv->usbdev); + } +} + +/**************************************************************************** + * Name: stm32_esofpoll + ****************************************************************************/ + +static void stm32_esofpoll(struct stm32_usbdev_s *priv) +{ + uint16_t regval; + + /* Called periodically from ESOF interrupt after RSMSTATE_STARTED */ + + switch (priv->rsmstate) + { + /* One ESOF after internal resume requested */ + + case RSMSTATE_STARTED: + regval = stm32_getreg(STM32_USB_CNTR); + regval |= USB_CNTR_RESUME; + stm32_putreg(regval, STM32_USB_CNTR); + priv->rsmstate = RSMSTATE_WAITING; + priv->nesofs = 10; + break; + + /* Countdown before completing the operation */ + + case RSMSTATE_WAITING: + priv->nesofs--; + if (priv->nesofs == 0) + { + /* Okay.. we are ready to resume normal operation */ + + regval = stm32_getreg(STM32_USB_CNTR); + regval &= (~USB_CNTR_RESUME); + stm32_putreg(regval, STM32_USB_CNTR); + priv->rsmstate = RSMSTATE_IDLE; + + /* Disable ESOF polling, disable the SUSP interrupt, and enable + * the WKUP interrupt. Clear any pending WKUP interrupt. + */ + + stm32_setimask(priv, + USB_CNTR_WKUPM, USB_CNTR_ESOFM | USB_CNTR_SUSPM); + stm32_putreg(~USB_ISTR_WKUP, STM32_USB_ISTR); + } + break; + + case RSMSTATE_IDLE: + default: + priv->rsmstate = RSMSTATE_IDLE; + break; + } +} + +/**************************************************************************** + * Endpoint Helpers + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_epreserve + ****************************************************************************/ + +static inline struct stm32_ep_s * +stm32_epreserve(struct stm32_usbdev_s *priv, uint8_t epset) +{ + struct stm32_ep_s *privep = NULL; + irqstate_t flags; + int epndx = 0; + + flags = enter_critical_section(); + epset &= priv->epavail; + if (epset) + { + /* Select the lowest bit in the set of matching, available endpoints + * (skipping EP0) + */ + + for (epndx = 1; epndx < STM32_NENDPOINTS; epndx++) + { + uint8_t bit = STM32_ENDP_BIT(epndx); + if ((epset & bit) != 0) + { + /* Mark the endpoint no longer available */ + + priv->epavail &= ~bit; + + /* And return the pointer to the standard endpoint structure */ + + privep = &priv->eplist[epndx]; + break; + } + } + } + + leave_critical_section(flags); + return privep; +} + +/**************************************************************************** + * Name: stm32_epunreserve + ****************************************************************************/ + +static inline void +stm32_epunreserve(struct stm32_usbdev_s *priv, struct stm32_ep_s *privep) +{ + irqstate_t flags = enter_critical_section(); + priv->epavail |= STM32_ENDP_BIT(USB_EPNO(privep->ep.eplog)); + leave_critical_section(flags); +} + +/**************************************************************************** + * Name: stm32_epreserved + ****************************************************************************/ + +static inline bool +stm32_epreserved(struct stm32_usbdev_s *priv, int epno) +{ + return ((priv->epavail & STM32_ENDP_BIT(epno)) == 0); +} + +/**************************************************************************** + * Name: stm32_epallocpma + ****************************************************************************/ + +static int stm32_epallocpma(struct stm32_usbdev_s *priv) +{ + irqstate_t flags; + int bufno = ERROR; + int bufndx; + + flags = enter_critical_section(); + for (bufndx = 2; bufndx < STM32_NBUFFERS; bufndx++) + { + /* Check if this buffer is available */ + + uint8_t bit = STM32_BUFFER_BIT(bufndx); + if ((priv->bufavail & bit) != 0) + { + /* Yes.. Mark the endpoint no longer available */ + + priv->bufavail &= ~bit; + + /* And return the index of the allocated buffer */ + + bufno = bufndx; + break; + } + } + + leave_critical_section(flags); + return bufno; +} + +/**************************************************************************** + * Name: stm32_epfreepma + ****************************************************************************/ + +static inline void +stm32_epfreepma(struct stm32_usbdev_s *priv, struct stm32_ep_s *privep) +{ + irqstate_t flags = enter_critical_section(); + priv->epavail |= STM32_ENDP_BIT(privep->bufno); + leave_critical_section(flags); +} + +/**************************************************************************** + * Endpoint operations + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_epconfigure + ****************************************************************************/ + +static int stm32_epconfigure(struct usbdev_ep_s *ep, + const struct usb_epdesc_s *desc, + bool last) +{ + struct stm32_ep_s *privep = (struct stm32_ep_s *)ep; + uint16_t pma; + uint16_t setting; + uint16_t maxpacket; + uint8_t epno; + +#ifdef CONFIG_DEBUG_FEATURES + if (!ep || !desc) + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); + uerr("ERROR: ep=%p desc=%p\n", ep, desc); + return -EINVAL; + } +#endif + + /* Get the unadorned endpoint address */ + + epno = USB_EPNO(desc->addr); + usbtrace(TRACE_EPCONFIGURE, (uint16_t)epno); + DEBUGASSERT(epno == USB_EPNO(ep->eplog)); + + /* Set the requested type */ + + switch (desc->attr & USB_EP_ATTR_XFERTYPE_MASK) + { + case USB_EP_ATTR_XFER_INT: /* Interrupt endpoint */ + setting = USB_EPR_EPTYPE_INTERRUPT; + break; + + case USB_EP_ATTR_XFER_BULK: /* Bulk endpoint */ + setting = USB_EPR_EPTYPE_BULK; + break; + + case USB_EP_ATTR_XFER_ISOC: /* Isochronous endpoint */ +#warning "REVISIT: Need to review isochronous EP setup" + setting = USB_EPR_EPTYPE_ISOC; + break; + + case USB_EP_ATTR_XFER_CONTROL: /* Control endpoint */ + setting = USB_EPR_EPTYPE_CONTROL; + break; + + default: + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADEPTYPE), + (uint16_t)desc->type); + return -EINVAL; + } + + stm32_seteptype(epno, setting); + + /* Get the address of the PMA buffer allocated for this endpoint */ + +#warning "REVISIT: Should configure BULK EPs using double buffer feature" + pma = STM32_BUFNO2BUF(privep->bufno); + + /* Get the maxpacket size of the endpoint. */ + + maxpacket = GETUINT16(desc->mxpacketsize); + DEBUGASSERT(maxpacket <= STM32_MAXPACKET_SIZE); + ep->maxpacket = maxpacket; + + /* Get the subset matching the requested direction */ + + if (USB_ISEPIN(desc->addr)) + { + /* The full, logical EP number includes direction */ + + ep->eplog = USB_EPIN(epno); + + /* Set up TX; disable RX */ + + stm32_seteptxaddr(epno, pma); + stm32_seteptxstatus(epno, USB_EPR_STATTX_NAK); + stm32_seteprxstatus(epno, USB_EPR_STATRX_DIS); + } + else + { + /* The full, logical EP number includes direction */ + + ep->eplog = USB_EPOUT(epno); + + /* Set up RX; disable TX */ + + stm32_seteprxaddr(epno, pma); + stm32_seteprxcount(epno, maxpacket); + stm32_seteprxstatus(epno, USB_EPR_STATRX_VALID); + stm32_seteptxstatus(epno, USB_EPR_STATTX_DIS); + } + + stm32_dumpep(epno); + return OK; +} + +/**************************************************************************** + * Name: stm32_epdisable + ****************************************************************************/ + +static int stm32_epdisable(struct usbdev_ep_s *ep) +{ + struct stm32_ep_s *privep = (struct stm32_ep_s *)ep; + irqstate_t flags; + uint8_t epno; + +#ifdef CONFIG_DEBUG_FEATURES + if (!ep) + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); + uerr("ERROR: ep=%p\n", ep); + return -EINVAL; + } +#endif + + epno = USB_EPNO(ep->eplog); + usbtrace(TRACE_EPDISABLE, epno); + + /* Cancel any ongoing activity */ + + flags = enter_critical_section(); + stm32_cancelrequests(privep); + + /* Disable TX; disable RX */ + + stm32_seteprxcount(epno, 0); + stm32_seteprxstatus(epno, USB_EPR_STATRX_DIS); + stm32_seteptxstatus(epno, USB_EPR_STATTX_DIS); + + leave_critical_section(flags); + return OK; +} + +/**************************************************************************** + * Name: stm32_epallocreq + ****************************************************************************/ + +static struct usbdev_req_s *stm32_epallocreq(struct usbdev_ep_s *ep) +{ + struct stm32_req_s *privreq; + +#ifdef CONFIG_DEBUG_FEATURES + if (!ep) + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); + return NULL; + } +#endif + usbtrace(TRACE_EPALLOCREQ, USB_EPNO(ep->eplog)); + + privreq = kmm_malloc(sizeof(struct stm32_req_s)); + if (!privreq) + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_ALLOCFAIL), 0); + return NULL; + } + + memset(privreq, 0, sizeof(struct stm32_req_s)); + return &privreq->req; +} + +/**************************************************************************** + * Name: stm32_epfreereq + ****************************************************************************/ + +static void stm32_epfreereq(struct usbdev_ep_s *ep, struct usbdev_req_s *req) +{ + struct stm32_req_s *privreq = (struct stm32_req_s *)req; + +#ifdef CONFIG_DEBUG_FEATURES + if (!ep || !req) + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); + return; + } +#endif + usbtrace(TRACE_EPFREEREQ, USB_EPNO(ep->eplog)); + + kmm_free(privreq); +} + +/**************************************************************************** + * Name: stm32_epsubmit + ****************************************************************************/ + +static int stm32_epsubmit(struct usbdev_ep_s *ep, struct usbdev_req_s *req) +{ + struct stm32_req_s *privreq = (struct stm32_req_s *)req; + struct stm32_ep_s *privep = (struct stm32_ep_s *)ep; + struct stm32_usbdev_s *priv; + irqstate_t flags; + uint8_t epno; + int ret = OK; + +#ifdef CONFIG_DEBUG_FEATURES + if (!req || !req->callback || !req->buf || !ep) + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); + uerr("ERROR: req=%p callback=%p buf=%p ep=%p\n", + req, req->callback, req->buf, ep); + return -EINVAL; + } +#endif + + usbtrace(TRACE_EPSUBMIT, USB_EPNO(ep->eplog)); + priv = privep->dev; + +#ifdef CONFIG_DEBUG_FEATURES + if (!priv->driver) + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_NOTCONFIGURED), + priv->usbdev.speed); + uerr("ERROR: driver=%p\n", priv->driver); + return -ESHUTDOWN; + } +#endif + + /* Handle the request from the class driver */ + + epno = USB_EPNO(ep->eplog); + req->result = -EINPROGRESS; + req->xfrd = 0; + flags = enter_critical_section(); + + /* If we are stalled, then drop all requests on the floor */ + + if (privep->stalled) + { + stm32_abortrequest(privep, privreq, -EBUSY); + uerr("ERROR: stalled\n"); + ret = -EBUSY; + } + + /* Handle IN (device-to-host) requests. NOTE: If the class device is + * using the bi-directional EP0, then we assume that they intend the EP0 + * IN functionality. + */ + + else if (USB_ISEPIN(ep->eplog) || epno == EP0) + { + /* Add the new request to the request queue for the IN endpoint */ + + stm32_rqenqueue(privep, privreq); + usbtrace(TRACE_INREQQUEUED(epno), req->len); + + /* If the IN endpoint FIFO is available, then transfer the data now */ + + if (!privep->txbusy) + { + priv->txstatus = USB_EPR_STATTX_NAK; + if (epno == EP0) + { + ret = stm32_wrrequest_ep0(priv, privep); + } + else + { + ret = stm32_wrrequest(priv, privep); + } + + /* Set the new TX status */ + + stm32_seteptxstatus(epno, priv->txstatus); + } + } + + /* Handle OUT (host-to-device) requests */ + + else + { + /* Add the new request to the request queue for the OUT endpoint */ + + privep->txnullpkt = 0; + stm32_rqenqueue(privep, privreq); + usbtrace(TRACE_OUTREQQUEUED(epno), req->len); + + /* This there a incoming data pending the availability of a request? */ + + if (priv->rxpending) + { + /* Set STAT_RX bits to '11' in the USB_EPnR, enabling further + * transactions. "While the STAT_RX bits are equal to '10' + * (NAK), any OUT request addressed to that endpoint is NAKed, + * indicating a flow control condition: the USB host will retry + * the transaction until it succeeds." + */ + + priv->rxstatus = USB_EPR_STATRX_VALID; + stm32_seteprxstatus(epno, priv->rxstatus); + + /* Data is no longer pending */ + + priv->rxpending = false; + } + } + + leave_critical_section(flags); + return ret; +} + +/**************************************************************************** + * Name: stm32_epcancel + ****************************************************************************/ + +static int stm32_epcancel(struct usbdev_ep_s *ep, struct usbdev_req_s *req) +{ + struct stm32_ep_s *privep = (struct stm32_ep_s *)ep; + irqstate_t flags; + +#ifdef CONFIG_DEBUG_USB + if (!ep || !req) + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); + return -EINVAL; + } +#endif + usbtrace(TRACE_EPCANCEL, USB_EPNO(ep->eplog)); + + flags = enter_critical_section(); + stm32_cancelrequests(privep); + leave_critical_section(flags); + return OK; +} + +/**************************************************************************** + * Name: stm32_epstall + ****************************************************************************/ + +static int stm32_epstall(struct usbdev_ep_s *ep, bool resume) +{ + struct stm32_ep_s *privep; + struct stm32_usbdev_s *priv; + uint8_t epno; + uint16_t status; + irqstate_t flags; + +#ifdef CONFIG_DEBUG_USB + if (!ep) + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); + return -EINVAL; + } +#endif + + privep = (struct stm32_ep_s *)ep; + priv = (struct stm32_usbdev_s *)privep->dev; + epno = USB_EPNO(ep->eplog); + + /* STALL or RESUME the endpoint */ + + flags = enter_critical_section(); + usbtrace(resume ? TRACE_EPRESUME : TRACE_EPSTALL, USB_EPNO(ep->eplog)); + + /* Get status of the endpoint; stall the request if the endpoint is + * disabled + */ + + if (USB_ISEPIN(ep->eplog)) + { + status = stm32_geteptxstatus(epno); + } + else + { + status = stm32_geteprxstatus(epno); + } + + if (status == 0) + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EPDISABLED), 0); + + if (epno == 0) + { + priv->ep0state = EP0STATE_STALLED; + } + + leave_critical_section(flags); + return -ENODEV; + } + + /* Handle the resume condition */ + + if (resume) + { + /* Resuming a stalled endpoint */ + + usbtrace(TRACE_EPRESUME, epno); + privep->stalled = false; + + if (USB_ISEPIN(ep->eplog)) + { + /* IN endpoint */ + + if (stm32_eptxstalled(epno)) + { + stm32_clrtxdtog(epno); + + /* Restart any queued write requests */ + + priv->txstatus = USB_EPR_STATTX_NAK; + if (epno == EP0) + { + stm32_wrrequest_ep0(priv, privep); + } + else + { + stm32_wrrequest(priv, privep); + } + + /* Set the new TX status */ + + stm32_seteptxstatus(epno, priv->txstatus); + } + } + else + { + /* OUT endpoint */ + + if (stm32_eprxstalled(epno)) + { + if (epno == EP0) + { + /* After clear the STALL, enable the default endpoint + * receiver + */ + + stm32_seteprxcount(epno, ep->maxpacket); + } + else + { + stm32_clrrxdtog(epno); + } + + priv->rxstatus = USB_EPR_STATRX_VALID; + stm32_seteprxstatus(epno, USB_EPR_STATRX_VALID); + } + } + } + + /* Handle the stall condition */ + + else + { + usbtrace(TRACE_EPSTALL, epno); + privep->stalled = true; + + if (USB_ISEPIN(ep->eplog)) + { + /* IN endpoint */ + + priv->txstatus = USB_EPR_STATTX_STALL; + stm32_seteptxstatus(epno, USB_EPR_STATTX_STALL); + } + else + { + /* OUT endpoint */ + + priv->rxstatus = USB_EPR_STATRX_STALL; + stm32_seteprxstatus(epno, USB_EPR_STATRX_STALL); + } + } + + leave_critical_section(flags); + return OK; +} + +/**************************************************************************** + * Device Controller Operations + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_allocep + ****************************************************************************/ + +static struct usbdev_ep_s *stm32_allocep(struct usbdev_s *dev, uint8_t epno, + bool in, uint8_t eptype) +{ + struct stm32_usbdev_s *priv = (struct stm32_usbdev_s *)dev; + struct stm32_ep_s *privep = NULL; + uint8_t epset = STM32_ENDP_ALLSET; + int bufno; + + usbtrace(TRACE_DEVALLOCEP, (uint16_t)epno); +#ifdef CONFIG_DEBUG_USB + if (!dev) + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); + return NULL; + } +#endif + + /* Ignore any direction bits in the logical address */ + + epno = USB_EPNO(epno); + + /* A logical address of 0 means that any endpoint will do */ + + if (epno > 0) + { + /* Otherwise, we will return the endpoint structure only for the + * requested 'logical' endpoint. + * All of the other checks will still be performed. + * + * First, verify that the logical endpoint is in the range supported by + * by the hardware. + */ + + if (epno >= STM32_NENDPOINTS) + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADEPNO), (uint16_t)epno); + return NULL; + } + + /* Convert the logical address to a physical OUT endpoint address and + * remove all of the candidate endpoints from the bitset except for the + * the IN/OUT pair for this logical address. + */ + + epset = STM32_ENDP_BIT(epno); + } + + /* Check if the selected endpoint number is available */ + + privep = stm32_epreserve(priv, epset); + if (!privep) + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EPRESERVE), (uint16_t)epset); + goto errout; + } + + /* Allocate a PMA buffer for this endpoint */ + +#warning "REVISIT: Should configure BULK EPs using double buffer feature" + bufno = stm32_epallocpma(priv); + if (bufno < 0) + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EPBUFFER), 0); + goto errout_with_ep; + } + + privep->bufno = (uint8_t)bufno; + return &privep->ep; + +errout_with_ep: + stm32_epunreserve(priv, privep); +errout: + return NULL; +} + +/**************************************************************************** + * Name: stm32_freeep + ****************************************************************************/ + +static void stm32_freeep(struct usbdev_s *dev, struct usbdev_ep_s *ep) +{ + struct stm32_usbdev_s *priv; + struct stm32_ep_s *privep; + +#ifdef CONFIG_DEBUG_USB + if (!dev || !ep) + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); + return; + } +#endif + priv = (struct stm32_usbdev_s *)dev; + privep = (struct stm32_ep_s *)ep; + usbtrace(TRACE_DEVFREEEP, (uint16_t)USB_EPNO(ep->eplog)); + + if (priv && privep) + { + /* Free the PMA buffer assigned to this endpoint */ + + stm32_epfreepma(priv, privep); + + /* Mark the endpoint as available */ + + stm32_epunreserve(priv, privep); + } +} + +/**************************************************************************** + * Name: stm32_getframe + ****************************************************************************/ + +static int stm32_getframe(struct usbdev_s *dev) +{ + uint16_t fnr; + +#ifdef CONFIG_DEBUG_USB + if (!dev) + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); + return -EINVAL; + } +#endif + + /* Return the last frame number detected by the hardware */ + + fnr = stm32_getreg(STM32_USB_FNR); + usbtrace(TRACE_DEVGETFRAME, fnr); + return (fnr & USB_FNR_FN_MASK); +} + +/**************************************************************************** + * Name: stm32_wakeup + ****************************************************************************/ + +static int stm32_wakeup(struct usbdev_s *dev) +{ + struct stm32_usbdev_s *priv = (struct stm32_usbdev_s *)dev; + irqstate_t flags; + + usbtrace(TRACE_DEVWAKEUP, 0); +#ifdef CONFIG_DEBUG_USB + if (!dev) + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); + return -EINVAL; + } +#endif + + /* Start the resume sequence. The actual resume steps will be driven + * by the ESOF interrupt. + */ + + flags = enter_critical_section(); + stm32_initresume(priv); + priv->rsmstate = RSMSTATE_STARTED; + + /* Disable the SUSP interrupt (until we are fully resumed), disable + * the WKUP interrupt (we are already waking up), and enable the + * ESOF interrupt that will drive the resume operations. Clear any + * pending ESOF interrupt. + */ + + stm32_setimask(priv, USB_CNTR_ESOFM, USB_CNTR_WKUPM | USB_CNTR_SUSPM); + stm32_putreg(~USB_ISTR_ESOF, STM32_USB_ISTR); + leave_critical_section(flags); + return OK; +} + +/**************************************************************************** + * Name: stm32_selfpowered + ****************************************************************************/ + +static int stm32_selfpowered(struct usbdev_s *dev, bool selfpowered) +{ + struct stm32_usbdev_s *priv = (struct stm32_usbdev_s *)dev; + + usbtrace(TRACE_DEVSELFPOWERED, (uint16_t)selfpowered); + +#ifdef CONFIG_DEBUG_USB + if (!dev) + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); + return -ENODEV; + } +#endif + + priv->selfpowered = selfpowered; + return OK; +} + +/**************************************************************************** + * Initialization/Reset + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_reset + ****************************************************************************/ + +static void stm32_reset(struct stm32_usbdev_s *priv) +{ + int epno; + + /* Put the USB controller in reset, disable all interrupts */ + + stm32_putreg(USB_CNTR_FRES, STM32_USB_CNTR); + + /* Tell the class driver that we are disconnected. The class driver + * should then accept any new configurations. + */ + + CLASS_DISCONNECT(priv->driver, &priv->usbdev); + + /* Reset the device state structure */ + + priv->ep0state = EP0STATE_IDLE; + priv->rsmstate = RSMSTATE_IDLE; + priv->rxpending = false; + + /* Reset endpoints */ + + for (epno = 0; epno < STM32_NENDPOINTS; epno++) + { + struct stm32_ep_s *privep = &priv->eplist[epno]; + + /* Cancel any queued requests. Since they are canceled + * with status -ESHUTDOWN, then will not be requeued + * until the configuration is reset. NOTE: This should + * not be necessary... the CLASS_DISCONNECT above should + * result in the class implementation calling stm32_epdisable + * for each of its configured endpoints. + */ + + stm32_cancelrequests(privep); + + /* Reset endpoint status */ + + privep->stalled = false; + privep->halted = false; + privep->txbusy = false; + privep->txnullpkt = false; + } + + /* Re-configure the USB controller in its initial, unconnected state */ + + stm32_hwreset(priv); + priv->usbdev.speed = USB_SPEED_FULL; +} + +/**************************************************************************** + * Name: stm32_hwreset + ****************************************************************************/ + +static void stm32_hwreset(struct stm32_usbdev_s *priv) +{ + /* Put the USB controller into reset, clear all interrupt enables */ + + stm32_putreg(USB_CNTR_FRES, STM32_USB_CNTR); + + /* Disable interrupts (and perhaps take the USB controller out of reset) */ + + priv->imask = 0; + stm32_putreg(priv->imask, STM32_USB_CNTR); + + /* Set the STM32 BTABLE address */ + + stm32_putreg(STM32_BTABLE_ADDRESS & 0xfff8, STM32_USB_BTABLE); + + /* Initialize EP0 */ + + stm32_seteptype(EP0, USB_EPR_EPTYPE_CONTROL); + stm32_seteptxstatus(EP0, USB_EPR_STATTX_NAK); + stm32_seteprxaddr(EP0, STM32_EP0_RXADDR); + stm32_seteprxcount(EP0, STM32_EP0MAXPACKET); + stm32_seteptxaddr(EP0, STM32_EP0_TXADDR); + stm32_clrstatusout(EP0); + stm32_seteprxstatus(EP0, USB_EPR_STATRX_VALID); + + /* Set the device to respond on default address */ + + stm32_setdevaddr(priv, 0); + + /* Clear any pending interrupts */ + + stm32_putreg(0, STM32_USB_ISTR); + + /* Enable interrupts at the USB controller */ + + stm32_setimask(priv, STM32_CNTR_SETUP, + (USB_CNTR_ALLINTS & ~STM32_CNTR_SETUP)); + stm32_dumpep(EP0); +} + +/**************************************************************************** + * Name: stm32_hwsetup + ****************************************************************************/ + +static void stm32_hwsetup(struct stm32_usbdev_s *priv) +{ + int epno; + + /* Power the USB controller, put the USB controller into reset, disable + * all USB interrupts + */ + + stm32_putreg(USB_CNTR_FRES | USB_CNTR_PDWN, STM32_USB_CNTR); + + /* Disconnect the device / disable the pull-up. We don't want the + * host to enumerate us until the class driver is registered. + */ + + stm32_usbpullup(&priv->usbdev, false); + + /* Initialize the device state structure. NOTE: many fields + * have the initial value of zero and, hence, are not explicitly + * initialized here. + */ + + memset(priv, 0, sizeof(struct stm32_usbdev_s)); + priv->usbdev.ops = &g_devops; + priv->usbdev.ep0 = &priv->eplist[EP0].ep; + priv->epavail = STM32_ENDP_ALLSET & ~STM32_ENDP_BIT(EP0); + priv->bufavail = STM32_BUFFER_ALLSET & ~STM32_BUFFER_EP0; + + /* Initialize the endpoint list */ + + for (epno = 0; epno < STM32_NENDPOINTS; epno++) + { + /* Set endpoint operations, reference to driver structure (not + * really necessary because there is only one controller), and + * the (physical) endpoint number which is just the index to the + * endpoint. + */ + + priv->eplist[epno].ep.ops = &g_epops; + priv->eplist[epno].dev = priv; + priv->eplist[epno].ep.eplog = epno; + + /* We will use a fixed maxpacket size for all endpoints (perhaps + * ISOC endpoints could have larger maxpacket???). A smaller + * packet size can be selected when the endpoint is configured. + */ + + priv->eplist[epno].ep.maxpacket = STM32_MAXPACKET_SIZE; + } + + /* Select a smaller endpoint size for EP0 */ + +#if STM32_EP0MAXPACKET < STM32_MAXPACKET_SIZE + priv->eplist[EP0].ep.maxpacket = STM32_EP0MAXPACKET; +#endif + + /* Configure the USB controller. USB uses the following GPIO pins: + * + * PA9 - VBUS + * PA10 - ID + * PA11 - DM + * PA12 - DP + * + * "As soon as the USB is enabled, these pins [DM and DP] are connected to + * the USB internal transceiver automatically." + */ + + /* Power up the USB controller, holding it in reset. There is a delay of + * about 1uS after applying power before the USB will behave predictably. + * A 5MS delay is more than enough. NOTE that we leave the USB controller + * in the reset state; the hardware will not be initialized until the + * class driver has been bound. + */ + + stm32_putreg(USB_CNTR_FRES, STM32_USB_CNTR); + up_mdelay(5); +} + +/**************************************************************************** + * Name: stm32_hwshutdown + ****************************************************************************/ + +static void stm32_hwshutdown(struct stm32_usbdev_s *priv) +{ + priv->usbdev.speed = USB_SPEED_UNKNOWN; + + /* Disable all interrupts and force the USB controller into reset */ + + stm32_putreg(USB_CNTR_FRES, STM32_USB_CNTR); + + /* Clear any pending interrupts */ + + stm32_putreg(0, STM32_USB_ISTR); + + /* Disconnect the device / disable the pull-up */ + + stm32_usbpullup(&priv->usbdev, false); + + /* Power down the USB controller */ + + stm32_putreg(USB_CNTR_FRES | USB_CNTR_PDWN, STM32_USB_CNTR); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: arm_usbinitialize + * Description: + * Initialize the USB driver + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void arm_usbinitialize(void) +{ + /* For now there is only one USB controller, but we will always refer to + * it using a pointer to make any future ports to multiple USB controllers + * easier. + */ + + struct stm32_usbdev_s *priv = &g_usbdev; + + usbtrace(TRACE_DEVINIT, 0); + stm32_checksetup(); + + /* Configure USB GPIO alternate function pins */ + +#ifdef CONFIG_STM32_STM32F30XX + stm32_configgpio(GPIO_USB_DM); + stm32_configgpio(GPIO_USB_DP); +#endif + + /* Power up the USB controller, but leave it in the reset state */ + + stm32_hwsetup(priv); + + /* Remap the USB interrupt as needed + * (Only supported by the STM32 F3 family) + */ + +#ifdef CONFIG_STM32_STM32F30XX +# ifdef CONFIG_STM32_USB_ITRMP + /* Clear the ITRMP bit to use the legacy, shared USB/CAN interrupts */ + + modifyreg32(STM32_RCC_APB1ENR, SYSCFG_CFGR1_USB_ITRMP, 0); +# else + /* Set the ITRMP bit to use the STM32 F3's dedicated USB interrupts */ + + modifyreg32(STM32_RCC_APB1ENR, 0, SYSCFG_CFGR1_USB_ITRMP); +# endif +#endif + + /* Attach USB controller interrupt handlers. The hardware will not be + * initialized and interrupts will not be enabled until the class device + * driver is bound. Getting the IRQs here only makes sure that we have + * them when we need them later. + */ + + if (irq_attach(STM32_IRQ_USBHP, stm32_hpinterrupt, NULL) != 0) + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_IRQREGISTRATION), + (uint16_t)STM32_IRQ_USBHP); + goto errout; + } + + if (irq_attach(STM32_IRQ_USBLP, stm32_lpinterrupt, NULL) != 0) + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_IRQREGISTRATION), + (uint16_t)STM32_IRQ_USBLP); + goto errout; + } + + return; + +errout: + arm_usbuninitialize(); +} + +/**************************************************************************** + * Name: arm_usbuninitialize + * Description: + * Initialize the USB driver + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void arm_usbuninitialize(void) +{ + /* For now there is only one USB controller, but we will always refer to + * it using a pointer to make any future ports to multiple USB controllers + * easier. + */ + + struct stm32_usbdev_s *priv = &g_usbdev; + irqstate_t flags; + + flags = enter_critical_section(); + usbtrace(TRACE_DEVUNINIT, 0); + + /* Disable and detach the USB IRQs */ + + up_disable_irq(STM32_IRQ_USBHP); + up_disable_irq(STM32_IRQ_USBLP); + irq_detach(STM32_IRQ_USBHP); + irq_detach(STM32_IRQ_USBLP); + + if (priv->driver) + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_DRIVERREGISTERED), 0); + usbdev_unregister(priv->driver); + } + + /* Put the hardware in an inactive state */ + + stm32_hwshutdown(priv); + leave_critical_section(flags); +} + +/**************************************************************************** + * Name: usbdev_register + * + * Description: + * Register a USB device class driver. The class driver's bind() method + * will be called to bind it to a USB device driver. + * + ****************************************************************************/ + +int usbdev_register(struct usbdevclass_driver_s *driver) +{ + /* For now there is only one USB controller, but we will always refer to + * it using a pointer to make any future ports to multiple USB controllers + * easier. + */ + + struct stm32_usbdev_s *priv = &g_usbdev; + int ret; + + usbtrace(TRACE_DEVREGISTER, 0); + +#ifdef CONFIG_DEBUG_USB + if (!driver || !driver->ops->bind || !driver->ops->unbind || + !driver->ops->disconnect || !driver->ops->setup) + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); + return -EINVAL; + } + + if (priv->driver) + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_DRIVER), 0); + return -EBUSY; + } +#endif + + /* First hook up the driver */ + + priv->driver = driver; + + /* Then bind the class driver */ + + ret = CLASS_BIND(driver, &priv->usbdev); + if (ret) + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BINDFAILED), (uint16_t) - ret); + } + else + { + /* Setup the USB controller -- enabling interrupts at the USB + * controller + */ + + stm32_hwreset(priv); + + /* Enable USB controller interrupts at the NVIC */ + + up_enable_irq(STM32_IRQ_USBHP); + up_enable_irq(STM32_IRQ_USBLP); + + /* Enable pull-up to connect the device. The host should enumerate us + * some time after this + */ + + stm32_usbpullup(&priv->usbdev, true); + priv->usbdev.speed = USB_SPEED_FULL; + } + + return ret; +} + +/**************************************************************************** + * Name: usbdev_unregister + * + * Description: + * Un-register usbdev class driver. If the USB device is connected to a + * USB host, it will first disconnect(). The driver is also requested to + * unbind() and clean up any device state, before this procedure finally + * returns. + * + ****************************************************************************/ + +int usbdev_unregister(struct usbdevclass_driver_s *driver) +{ + /* For now there is only one USB controller, but we will always refer to + * it using a pointer to make any future ports to multiple USB controllers + * easier. + */ + + struct stm32_usbdev_s *priv = &g_usbdev; + irqstate_t flags; + + usbtrace(TRACE_DEVUNREGISTER, 0); + +#ifdef CONFIG_DEBUG_USB + if (driver != priv->driver) + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); + return -EINVAL; + } +#endif + + /* Reset the hardware and cancel all requests. All requests must be + * canceled while the class driver is still bound. + */ + + flags = enter_critical_section(); + stm32_reset(priv); + + /* Unbind the class driver */ + + CLASS_UNBIND(driver, &priv->usbdev); + + /* Disable USB controller interrupts (but keep them attached) */ + + up_disable_irq(STM32_IRQ_USBHP); + up_disable_irq(STM32_IRQ_USBLP); + + /* Put the hardware in an inactive state. Then bring the hardware back up + * in the reset state (this is probably not necessary, the stm32_reset() + * call above was probably sufficient). + */ + + stm32_hwshutdown(priv); + stm32_hwsetup(priv); + + /* Unhook the driver */ + + priv->driver = NULL; + leave_critical_section(flags); + return OK; +} + +#endif /* CONFIG_USBDEV && CONFIG_STM32_USB */ diff --git a/arch/arm/src/common/stm32/stm32_usbfs.h b/arch/arm/src/common/stm32/stm32_usbfs.h new file mode 100644 index 0000000000000..443a87bacfe36 --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_usbfs.h @@ -0,0 +1,38 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_usbfs.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_COMPAT_STM32USBFS_H +#define __ARCH_ARM_SRC_COMMON_COMPAT_STM32USBFS_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#if defined(CONFIG_STM32_HAVE_IP_USBFS_M3M4_V1) +# include "stm32_usbfs_m3m4_v1.h" +#else +# error "Unsupported STM32 stm32_usbfs" +#endif + +#endif /* __ARCH_ARM_SRC_COMMON_COMPAT_STM32USBFS_H */ diff --git a/arch/arm/src/common/stm32/stm32_usbfs_m3m4_v1.c b/arch/arm/src/common/stm32/stm32_usbfs_m3m4_v1.c new file mode 100644 index 0000000000000..418dcf33211f8 --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_usbfs_m3m4_v1.c @@ -0,0 +1,3989 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_usbfs_m3m4_v1.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include + +#include "arm_internal.h" +#include "stm32.h" +#include "stm32_syscfg.h" +#include "stm32_usbfs_m3m4_v1.h" +#include "stm32_gpio.h" +#include "stm32_syscfg.h" +#include "stm32_usbfs_m3m4_v1.h" + +#if defined(CONFIG_STM32_USBFS) + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +#ifndef CONFIG_USBDEV_EP0_MAXSIZE +# define CONFIG_USBDEV_EP0_MAXSIZE 64 +#endif + +#ifndef CONFIG_USBDEV_SETUP_MAXDATASIZE +# define CONFIG_USBDEV_SETUP_MAXDATASIZE CONFIG_USBDEV_EP0_MAXSIZE +#endif + +/* Extremely detailed register debug that you would normally never want + * enabled. + */ + +#ifndef CONFIG_DEBUG_USB_INFO +# undef CONFIG_STM32_USBFS_REGDEBUG +#endif + +/* Initial interrupt mask: Reset + Suspend + Correct Transfer */ + +#define STM32_CNTR_SETUP (USB_CNTR_RESETM|USB_CNTR_SUSPM|USB_CNTR_CTRM) + +/* Endpoint identifiers. The STM32 supports up to 16 mono-directional or 8 + * bidirectional endpoints. However, when you take into account PMA buffer + * usage (see below) and the fact that EP0 is bidirectional, then there is + * a functional limitation of EP0 + 5 mono-directional endpoints = 6. We'll + * define STM32_NENDPOINTS to be 8, however, because that is how many + * endpoint register sets there are. + */ + +#define EP0 (0) +#define EP1 (1) +#define EP2 (2) +#define EP3 (3) +#define EP4 (4) +#define EP5 (5) +#define EP6 (6) +#define EP7 (7) + +#define STM32_ENDP_BIT(ep) (1 << (ep)) +#define STM32_ENDP_ALLSET 0xff + +/* Packet sizes. We us a fixed 64 max packet size for all endpoint types */ + +#define STM32_MAXPACKET_SHIFT (6) +#define STM32_MAXPACKET_SIZE (1 << (STM32_MAXPACKET_SHIFT)) +#define STM32_MAXPACKET_MASK (STM32_MAXPACKET_SIZE-1) + +#define STM32_EP0MAXPACKET STM32_MAXPACKET_SIZE + +/* Buffer descriptor table. We assume that USB has exclusive use of CAN/USB + * memory. The buffer table is positioned at the beginning of the 512-byte + * CAN/USB memory. We will use the first STM32_NENDPOINTS*4 words for the + * buffer table. + * That is exactly 64 bytes, leaving 7*64 bytes for endpoint buffers. + */ + +#define STM32_BTABLE_ADDRESS (0x00) /* Start at the beginning of USB/CAN RAM */ +#define STM32_DESC_SIZE (8) /* Each descriptor is 4*2=8 bytes in size */ +#define STM32_BTABLE_SIZE (STM32_NENDPOINTS*STM32_DESC_SIZE) + +/* Buffer layout. Assume that all buffers are 64-bytes (maxpacketsize), then + * we have space for only 7 buffers; endpoint 0 will require two buffers, + * leaving 5 for other endpoints. + */ + +#define STM32_BUFFER_START STM32_BTABLE_SIZE +#define STM32_EP0_RXADDR STM32_BUFFER_START +#define STM32_EP0_TXADDR (STM32_EP0_RXADDR+STM32_EP0MAXPACKET) + +#define STM32_BUFFER_EP0 0x03 +#define STM32_NBUFFERS 7 +#define STM32_BUFFER_BIT(bn) (1 << (bn)) +#define STM32_BUFFER_ALLSET 0x7f +#define STM32_BUFNO2BUF(bn) (STM32_BUFFER_START+((bn)<head == NULL) +#define stm32_rqpeek(ep) ((ep)->head) + +/* USB trace ****************************************************************/ + +/* Trace error codes */ + +#define STM32_TRACEERR_ALLOCFAIL 0x0001 +#define STM32_TRACEERR_BADCLEARFEATURE 0x0002 +#define STM32_TRACEERR_BADDEVGETSTATUS 0x0003 +#define STM32_TRACEERR_BADEPGETSTATUS 0x0004 +#define STM32_TRACEERR_BADEPNO 0x0005 +#define STM32_TRACEERR_BADEPTYPE 0x0006 +#define STM32_TRACEERR_BADGETCONFIG 0x0007 +#define STM32_TRACEERR_BADGETSETDESC 0x0008 +#define STM32_TRACEERR_BADGETSTATUS 0x0009 +#define STM32_TRACEERR_BADSETADDRESS 0x000a +#define STM32_TRACEERR_BADSETCONFIG 0x000b +#define STM32_TRACEERR_BADSETFEATURE 0x000c +#define STM32_TRACEERR_BINDFAILED 0x000d +#define STM32_TRACEERR_DISPATCHSTALL 0x000e +#define STM32_TRACEERR_DRIVER 0x000f +#define STM32_TRACEERR_DRIVERREGISTERED 0x0010 +#define STM32_TRACEERR_EP0BADCTR 0x0011 +#define STM32_TRACEERR_EP0SETUPSTALLED 0x0012 +#define STM32_TRACEERR_EPBUFFER 0x0013 +#define STM32_TRACEERR_EPDISABLED 0x0014 +#define STM32_TRACEERR_EPOUTNULLPACKET 0x0015 +#define STM32_TRACEERR_EPRESERVE 0x0016 +#define STM32_TRACEERR_INVALIDCTRLREQ 0x0017 +#define STM32_TRACEERR_INVALIDPARMS 0x0018 +#define STM32_TRACEERR_IRQREGISTRATION 0x0019 +#define STM32_TRACEERR_NOTCONFIGURED 0x001a +#define STM32_TRACEERR_REQABORTED 0x001b + +/* Trace interrupt codes */ + +#define STM32_TRACEINTID_CLEARFEATURE 0x0001 +#define STM32_TRACEINTID_DEVGETSTATUS 0x0002 +#define STM32_TRACEINTID_DISPATCH 0x0003 +#define STM32_TRACEINTID_EP0IN 0x0004 +#define STM32_TRACEINTID_EP0INDONE 0x0005 +#define STM32_TRACEINTID_EP0OUTDONE 0x0006 +#define STM32_TRACEINTID_EP0SETUPDONE 0x0007 +#define STM32_TRACEINTID_EP0SETUPSETADDRESS 0x0008 +#define STM32_TRACEINTID_EPGETSTATUS 0x0009 +#define STM32_TRACEINTID_EPINDONE 0x000a +#define STM32_TRACEINTID_EPINQEMPTY 0x000b +#define STM32_TRACEINTID_EPOUTDONE 0x000c +#define STM32_TRACEINTID_EPOUTPENDING 0x000d +#define STM32_TRACEINTID_EPOUTQEMPTY 0x000e +#define STM32_TRACEINTID_ESOF 0x000f +#define STM32_TRACEINTID_GETCONFIG 0x0010 +#define STM32_TRACEINTID_GETSETDESC 0x0011 +#define STM32_TRACEINTID_GETSETIF 0x0012 +#define STM32_TRACEINTID_GETSTATUS 0x0013 +#define STM32_TRACEINTID_HPINTERRUPT 0x0014 +#define STM32_TRACEINTID_IFGETSTATUS 0x0015 +#define STM32_TRACEINTID_LPCTR 0x0016 +#define STM32_TRACEINTID_LPINTERRUPT 0x0017 +#define STM32_TRACEINTID_NOSTDREQ 0x0018 +#define STM32_TRACEINTID_RESET 0x0019 +#define STM32_TRACEINTID_SETCONFIG 0x001a +#define STM32_TRACEINTID_SETFEATURE 0x001b +#define STM32_TRACEINTID_SUSP 0x001c +#define STM32_TRACEINTID_SYNCHFRAME 0x001d +#define STM32_TRACEINTID_WKUP 0x001e +#define STM32_TRACEINTID_EP0SETUPOUT 0x001f +#define STM32_TRACEINTID_EP0SETUPOUTDATA 0x0020 + +/* Byte ordering in host-based values */ + +#ifdef CONFIG_ENDIAN_BIG +# define LSB 1 +# define MSB 0 +#else +# define LSB 0 +# define MSB 1 +#endif + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/* The various states of a control pipe */ + +enum stm32_ep0state_e +{ + EP0STATE_IDLE = 0, /* No request in progress */ + EP0STATE_SETUP_OUT, /* Set up received with data for device OUT in progress */ + EP0STATE_SETUP_READY, /* Set up was received prior and is in ctrl, + * now the data has arrived */ + EP0STATE_WRREQUEST, /* Write request in progress */ + EP0STATE_RDREQUEST, /* Read request in progress */ + EP0STATE_STALLED /* We are stalled */ +}; + +/* Resume states */ + +enum stm32_rsmstate_e +{ + RSMSTATE_IDLE = 0, /* Device is either fully suspended or running */ + RSMSTATE_STARTED, /* Resume sequence has been started */ + RSMSTATE_WAITING /* Waiting (on ESOFs) for end of sequence */ +}; + +union wb_u +{ + uint16_t w; + uint8_t b[2]; +}; + +/* A container for a request so that the request make be retained in a list */ + +struct stm32_req_s +{ + struct usbdev_req_s req; /* Standard USB request */ + struct stm32_req_s *flink; /* Supports a singly linked list */ +}; + +/* This is the internal representation of an endpoint */ + +struct stm32_ep_s +{ + /* Common endpoint fields. This must be the first thing defined in the + * structure so that it is possible to simply cast from struct usbdev_ep_s + * to struct stm32_ep_s. + */ + + struct usbdev_ep_s ep; /* Standard endpoint structure */ + + /* STR71X-specific fields */ + + struct stm32_usbdev_s *dev; /* Reference to private driver data */ + struct stm32_req_s *head; /* Request list for this endpoint */ + struct stm32_req_s *tail; + uint8_t bufno; /* Allocated buffer number */ + uint8_t stalled:1; /* true: Endpoint is stalled */ + uint8_t halted:1; /* true: Endpoint feature halted */ + uint8_t txbusy:1; /* true: TX endpoint FIFO full */ + uint8_t txnullpkt:1; /* Null packet needed at end of transfer */ +}; + +struct stm32_usbdev_s +{ + /* Common device fields. This must be the first thing defined in the + * structure so that it is possible to simply cast from struct usbdev_s + * to structstm32_usbdev_s. + */ + + struct usbdev_s usbdev; + + /* The bound device class driver */ + + struct usbdevclass_driver_s *driver; + + /* STM32-specific fields */ + + uint8_t ep0state; /* State of EP0 (see enum stm32_ep0state_e) */ + uint8_t rsmstate; /* Resume state (see enum stm32_rsmstate_e) */ + uint8_t nesofs; /* ESOF counter (for resume support) */ + uint8_t rxpending:1; /* 1: OUT data in PMA, but no read requests */ + uint8_t selfpowered:1; /* 1: Device is self powered */ + uint8_t epavail; /* Bitset of available endpoints */ + uint8_t bufavail; /* Bitset of available buffers */ + uint16_t rxstatus; /* Saved during interrupt processing */ + uint16_t txstatus; /* " " " " " " " " */ + uint16_t imask; /* Current interrupt mask */ + + /* E0 SETUP data buffering. + * + * ctrl + * The 8-byte SETUP request is received on the EP0 OUT endpoint and is + * saved. + * + * ep0data + * For OUT SETUP requests, the SETUP data phase must also complete + * before the SETUP command can be processed. The ep0 packet receipt + * logic stm32_ep0_rdrequest will save the accompanying EP0 OUT data + * in ep0data[] before the SETUP command is re-processed. + * + * ep0datlen + * Length of OUT DATA received in ep0data[] + */ + + struct usb_ctrlreq_s ctrl; /* Last EP0 request */ + + uint8_t ep0data[CONFIG_USBDEV_SETUP_MAXDATASIZE]; + uint16_t ep0datlen; + + /* The endpoint list */ + + struct stm32_ep_s eplist[STM32_NENDPOINTS]; +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/* Register operations ******************************************************/ + +#ifdef CONFIG_STM32_USBFS_REGDEBUG +static uint16_t stm32_getreg(uint32_t addr); +static void stm32_putreg(uint16_t val, uint32_t addr); +static void stm32_checksetup(void); +static void stm32_dumpep(int epno); +#else +# define stm32_getreg(addr) getreg16(addr) +# define stm32_putreg(val,addr) putreg16(val,addr) +# define stm32_checksetup() +# define stm32_dumpep(epno) +#endif + +/* Low-Level Helpers ********************************************************/ + +static inline void + stm32_seteptxcount(uint8_t epno, uint16_t count); +static inline void + stm32_seteptxaddr(uint8_t epno, uint16_t addr); +static inline uint16_t + stm32_geteptxaddr(uint8_t epno); +static void stm32_seteprxcount(uint8_t epno, uint16_t count); +static inline uint16_t + stm32_geteprxcount(uint8_t epno); +static inline void + stm32_seteprxaddr(uint8_t epno, uint16_t addr); +static inline uint16_t + stm32_geteprxaddr(uint8_t epno); +static inline void + stm32_setepaddress(uint8_t epno, uint16_t addr); +static inline void + stm32_seteptype(uint8_t epno, uint16_t type); +static inline void + stm32_seteptxaddr(uint8_t epno, uint16_t addr); +static inline void + stm32_clrstatusout(uint8_t epno); +static void stm32_clrrxdtog(uint8_t epno); +static void stm32_clrtxdtog(uint8_t epno); +static void stm32_clrepctrrx(uint8_t epno); +static void stm32_clrepctrtx(uint8_t epno); +static void stm32_seteptxstatus(uint8_t epno, uint16_t state); +static void stm32_seteprxstatus(uint8_t epno, uint16_t state); +static inline uint16_t + stm32_geteptxstatus(uint8_t epno); +static inline uint16_t + stm32_geteprxstatus(uint8_t epno); +static bool stm32_eptxstalled(uint8_t epno); +static bool stm32_eprxstalled(uint8_t epno); +static void stm32_setimask(struct stm32_usbdev_s *priv, + uint16_t setbits, + uint16_t clrbits); + +/* Suspend/Resume Helpers ***************************************************/ + +static void stm32_suspend(struct stm32_usbdev_s *priv); +static void stm32_initresume(struct stm32_usbdev_s *priv); +static void stm32_esofpoll(struct stm32_usbdev_s *priv) ; + +/* Request Helpers **********************************************************/ + +static void stm32_copytopma(const uint8_t *buffer, uint16_t pma, + uint16_t nbytes); +static inline void stm32_copyfrompma(uint8_t *buffer, + uint16_t pma, uint16_t nbytes); +static struct stm32_req_s * + stm32_rqdequeue(struct stm32_ep_s *privep); +static void stm32_rqenqueue(struct stm32_ep_s *privep, + struct stm32_req_s *req); +static inline void + stm32_abortrequest(struct stm32_ep_s *privep, + struct stm32_req_s *privreq, int16_t result); +static void stm32_reqcomplete(struct stm32_ep_s *privep, int16_t result); +static void stm32_epwrite(struct stm32_usbdev_s *buf, + struct stm32_ep_s *privep, + const uint8_t *data, uint32_t nbytes); +static int stm32_wrrequest(struct stm32_usbdev_s *priv, + struct stm32_ep_s *privep); +inline static int + stm32_wrrequest_ep0(struct stm32_usbdev_s *priv, + struct stm32_ep_s *privep); +static inline int + stm32_ep0_rdrequest(struct stm32_usbdev_s *priv); +static int stm32_rdrequest(struct stm32_usbdev_s *priv, + struct stm32_ep_s *privep); +static void stm32_cancelrequests(struct stm32_ep_s *privep); + +/* Interrupt level processing ***********************************************/ + +static void stm32_dispatchrequest(struct stm32_usbdev_s *priv); +static void stm32_epdone(struct stm32_usbdev_s *priv, uint8_t epno); +static void stm32_setdevaddr(struct stm32_usbdev_s *priv, uint8_t value); +static void stm32_ep0setup(struct stm32_usbdev_s *priv); +static void stm32_ep0out(struct stm32_usbdev_s *priv); +static void stm32_ep0in(struct stm32_usbdev_s *priv); +static inline void + stm32_ep0done(struct stm32_usbdev_s *priv, uint16_t istr); +static void stm32_lptransfer(struct stm32_usbdev_s *priv); +static int stm32_hpinterrupt(int irq, void *context, void *arg); +static int stm32_lpinterrupt(int irq, void *context, void *arg); + +/* Endpoint helpers *********************************************************/ + +static inline struct stm32_ep_s * + stm32_epreserve(struct stm32_usbdev_s *priv, uint8_t epset); +static inline void + stm32_epunreserve(struct stm32_usbdev_s *priv, + struct stm32_ep_s *privep); +static inline bool + stm32_epreserved(struct stm32_usbdev_s *priv, int epno); +static int stm32_epallocpma(struct stm32_usbdev_s *priv); +static inline void + stm32_epfreepma(struct stm32_usbdev_s *priv, + struct stm32_ep_s *privep); + +/* Endpoint operations ******************************************************/ + +static int stm32_epconfigure(struct usbdev_ep_s *ep, + const struct usb_epdesc_s *desc, bool last); +static int stm32_epdisable(struct usbdev_ep_s *ep); +static struct usbdev_req_s * + stm32_epallocreq(struct usbdev_ep_s *ep); +static void stm32_epfreereq(struct usbdev_ep_s *ep, + struct usbdev_req_s *); +static int stm32_epsubmit(struct usbdev_ep_s *ep, + struct usbdev_req_s *req); +static int stm32_epcancel(struct usbdev_ep_s *ep, + struct usbdev_req_s *req); +static int stm32_epstall(struct usbdev_ep_s *ep, bool resume); + +/* USB device controller operations *****************************************/ + +static struct usbdev_ep_s * + stm32_allocep(struct usbdev_s *dev, uint8_t epno, bool in, + uint8_t eptype); +static void stm32_freeep(struct usbdev_s *dev, struct usbdev_ep_s *ep); +static int stm32_getframe(struct usbdev_s *dev); +static int stm32_wakeup(struct usbdev_s *dev); +static int stm32_selfpowered(struct usbdev_s *dev, bool selfpowered); +static int stm32_pullup(struct usbdev_s *dev, bool enable); + +/* Initialization/Reset *****************************************************/ + +static void stm32_reset(struct stm32_usbdev_s *priv); +static void stm32_hwreset(struct stm32_usbdev_s *priv); +static void stm32_hwsetup(struct stm32_usbdev_s *priv); +static void stm32_hwshutdown(struct stm32_usbdev_s *priv); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* Since there is only a single USB interface, all status information can be + * be simply retained in a single global instance. + */ + +static struct stm32_usbdev_s g_usbdev; + +static const struct usbdev_epops_s g_epops = +{ + .configure = stm32_epconfigure, + .disable = stm32_epdisable, + .allocreq = stm32_epallocreq, + .freereq = stm32_epfreereq, + .submit = stm32_epsubmit, + .cancel = stm32_epcancel, + .stall = stm32_epstall, +}; + +static const struct usbdev_ops_s g_devops = +{ + .allocep = stm32_allocep, + .freeep = stm32_freeep, + .getframe = stm32_getframe, + .wakeup = stm32_wakeup, + .selfpowered = stm32_selfpowered, + .pullup = stm32_pullup, +}; + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#ifdef CONFIG_USBDEV_TRACE_STRINGS +const struct trace_msg_t g_usb_trace_strings_intdecode[] = +{ + TRACE_STR(STM32_TRACEINTID_CLEARFEATURE), + TRACE_STR(STM32_TRACEINTID_DEVGETSTATUS), + TRACE_STR(STM32_TRACEINTID_DISPATCH), + TRACE_STR(STM32_TRACEINTID_EP0IN), + TRACE_STR(STM32_TRACEINTID_EP0INDONE), + TRACE_STR(STM32_TRACEINTID_EP0OUTDONE), + TRACE_STR(STM32_TRACEINTID_EP0SETUPDONE), + TRACE_STR(STM32_TRACEINTID_EP0SETUPSETADDRESS), + TRACE_STR(STM32_TRACEINTID_EPGETSTATUS), + TRACE_STR(STM32_TRACEINTID_EPINDONE), + TRACE_STR(STM32_TRACEINTID_EPINQEMPTY), + TRACE_STR(STM32_TRACEINTID_EPOUTDONE), + TRACE_STR(STM32_TRACEINTID_EPOUTPENDING), + TRACE_STR(STM32_TRACEINTID_EPOUTQEMPTY), + TRACE_STR(STM32_TRACEINTID_ESOF), + TRACE_STR(STM32_TRACEINTID_GETCONFIG), + TRACE_STR(STM32_TRACEINTID_GETSETDESC), + TRACE_STR(STM32_TRACEINTID_GETSETIF), + TRACE_STR(STM32_TRACEINTID_GETSTATUS), + TRACE_STR(STM32_TRACEINTID_HPINTERRUPT), + TRACE_STR(STM32_TRACEINTID_IFGETSTATUS), + TRACE_STR(STM32_TRACEINTID_LPCTR), + TRACE_STR(STM32_TRACEINTID_LPINTERRUPT), + TRACE_STR(STM32_TRACEINTID_NOSTDREQ), + TRACE_STR(STM32_TRACEINTID_RESET), + TRACE_STR(STM32_TRACEINTID_SETCONFIG), + TRACE_STR(STM32_TRACEINTID_SETFEATURE), + TRACE_STR(STM32_TRACEINTID_SUSP), + TRACE_STR(STM32_TRACEINTID_SYNCHFRAME), + TRACE_STR(STM32_TRACEINTID_WKUP), + TRACE_STR(STM32_TRACEINTID_EP0SETUPOUT), + TRACE_STR(STM32_TRACEINTID_EP0SETUPOUTDATA), + TRACE_STR_END +}; +#endif + +#ifdef CONFIG_USBDEV_TRACE_STRINGS +const struct trace_msg_t g_usb_trace_strings_deverror[] = +{ + TRACE_STR(STM32_TRACEERR_ALLOCFAIL), + TRACE_STR(STM32_TRACEERR_BADCLEARFEATURE), + TRACE_STR(STM32_TRACEERR_BADDEVGETSTATUS), + TRACE_STR(STM32_TRACEERR_BADEPGETSTATUS), + TRACE_STR(STM32_TRACEERR_BADEPNO), + TRACE_STR(STM32_TRACEERR_BADEPTYPE), + TRACE_STR(STM32_TRACEERR_BADGETCONFIG), + TRACE_STR(STM32_TRACEERR_BADGETSETDESC), + TRACE_STR(STM32_TRACEERR_BADGETSTATUS), + TRACE_STR(STM32_TRACEERR_BADSETADDRESS), + TRACE_STR(STM32_TRACEERR_BADSETCONFIG), + TRACE_STR(STM32_TRACEERR_BADSETFEATURE), + TRACE_STR(STM32_TRACEERR_BINDFAILED), + TRACE_STR(STM32_TRACEERR_DISPATCHSTALL), + TRACE_STR(STM32_TRACEERR_DRIVER), + TRACE_STR(STM32_TRACEERR_DRIVERREGISTERED), + TRACE_STR(STM32_TRACEERR_EP0BADCTR), + TRACE_STR(STM32_TRACEERR_EP0SETUPSTALLED), + TRACE_STR(STM32_TRACEERR_EPBUFFER), + TRACE_STR(STM32_TRACEERR_EPDISABLED), + TRACE_STR(STM32_TRACEERR_EPOUTNULLPACKET), + TRACE_STR(STM32_TRACEERR_EPRESERVE), + TRACE_STR(STM32_TRACEERR_INVALIDCTRLREQ), + TRACE_STR(STM32_TRACEERR_INVALIDPARMS), + TRACE_STR(STM32_TRACEERR_IRQREGISTRATION), + TRACE_STR(STM32_TRACEERR_NOTCONFIGURED), + TRACE_STR(STM32_TRACEERR_REQABORTED), + TRACE_STR_END +}; +#endif + +/**************************************************************************** + * Private Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Register Operations + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_getreg + ****************************************************************************/ + +#ifdef CONFIG_STM32_USBFS_REGDEBUG +static uint16_t stm32_getreg(uint32_t addr) +{ + static uint32_t prevaddr = 0; + static uint16_t preval = 0; + static uint32_t count = 0; + + /* Read the value from the register */ + + uint16_t val = getreg16(addr); + + /* Is this the same value that we read from the same register last time? + * Are we polling the register? If so, suppress some of the output. + */ + + if (addr == prevaddr && val == preval) + { + if (count == 0xffffffff || ++count > 3) + { + if (count == 4) + { + uinfo("...\n"); + } + + return val; + } + } + + /* No this is a new address or value */ + + else + { + /* Did we print "..." for the previous value? */ + + if (count > 3) + { + /* Yes.. then show how many times the value repeated */ + + uinfo("[repeats %d more times]\n", count - 3); + } + + /* Save the new address, value, and count */ + + prevaddr = addr; + preval = val; + count = 1; + } + + /* Show the register value read */ + + uinfo("%08" PRIx32 "->%04" PRIx32 "\n", addr, val); + return val; +} +#endif + +/**************************************************************************** + * Name: stm32_putreg + ****************************************************************************/ + +#ifdef CONFIG_STM32_USBFS_REGDEBUG +static void stm32_putreg(uint16_t val, uint32_t addr) +{ + /* Show the register value being written */ + + uinfo("%08" PRIx32 "<-%04" PRIx32 "\n", addr, val); + + /* Write the value */ + + putreg16(val, addr); +} +#endif + +/**************************************************************************** + * Name: stm32_dumpep + ****************************************************************************/ + +#ifdef CONFIG_STM32_USBFS_REGDEBUG +static void stm32_dumpep(int epno) +{ + uint32_t addr; + + /* Common registers */ + + uinfo("CNTR: %04x\n", getreg16(STM32_USB_CNTR)); + uinfo("ISTR: %04x\n", getreg16(STM32_USB_ISTR)); + uinfo("FNR: %04x\n", getreg16(STM32_USB_FNR)); + uinfo("DADDR: %04x\n", getreg16(STM32_USB_DADDR)); + uinfo("BTABLE: %04x\n", getreg16(STM32_USB_BTABLE)); + + /* Endpoint register */ + + addr = STM32_USB_EPR(epno); + uinfo("EPR%d: [%08" PRIx32 "] %04x\n", epno, addr, getreg16(addr)); + + /* Endpoint descriptor */ + + addr = STM32_USB_BTABLE_ADDR(epno, 0); + uinfo("DESC: %08" PRIx32 "\n", addr); + + /* Endpoint buffer descriptor */ + + addr = STM32_USB_ADDR_TX(epno); + uinfo(" TX ADDR: [%08" PRIx32 "] %04x\n", addr, getreg16(addr)); + + addr = STM32_USB_COUNT_TX(epno); + uinfo(" COUNT: [%08" PRIx32 "] %04x\n", addr, getreg16(addr)); + + addr = STM32_USB_ADDR_RX(epno); + uinfo(" RX ADDR: [%08" PRIx32 "] %04x\n", addr, getreg16(addr)); + + addr = STM32_USB_COUNT_RX(epno); + uinfo(" COUNT: [%08" PRIx32 "] %04x\n", addr, getreg16(addr)); +} +#endif + +/**************************************************************************** + * Name: stm32_checksetup + ****************************************************************************/ + +#ifdef CONFIG_STM32_USBFS_REGDEBUG +static void stm32_checksetup(void) +{ + uint32_t cfgr = getreg32(STM32_RCC_CFGR); + uint32_t apb1rstr = getreg32(STM32_RCC_APB1RSTR1); + uint32_t apb1enr = getreg32(STM32_RCC_APB1ENR1); + + uinfo("CFGR: %08" PRIx32 " APB1RSTR: %08" PRIx32 + " APB1ENR: %08" PRIx32 "\n", + cfgr, apb1rstr, apb1enr); + + if ((apb1rstr & RCC_APB1RSTR1_USBRST) != 0 || + (apb1enr & RCC_APB1ENR1_USBEN) == 0) + { + uerr("ERROR: USB is NOT setup correctly\n"); + } +} +#endif + +/**************************************************************************** + * Low-Level Helpers + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_seteptxcount + ****************************************************************************/ + +static inline void stm32_seteptxcount(uint8_t epno, uint16_t count) +{ + volatile uint16_t *epaddr = (uint16_t *)STM32_USB_COUNT_TX(epno); + *epaddr = count; +} + +/**************************************************************************** + * Name: stm32_seteptxaddr + ****************************************************************************/ + +static inline void stm32_seteptxaddr(uint8_t epno, uint16_t addr) +{ + volatile uint16_t *txaddr = (uint16_t *)STM32_USB_ADDR_TX(epno); + *txaddr = addr; +} + +/**************************************************************************** + * Name: stm32_geteptxaddr + ****************************************************************************/ + +static inline uint16_t stm32_geteptxaddr(uint8_t epno) +{ + volatile uint16_t *txaddr = (uint16_t *)STM32_USB_ADDR_TX(epno); + return (uint16_t)*txaddr; +} + +/**************************************************************************** + * Name: stm32_seteprxcount + ****************************************************************************/ + +static void stm32_seteprxcount(uint8_t epno, uint16_t count) +{ + volatile uint16_t *epaddr = (uint16_t *)STM32_USB_COUNT_RX(epno); + uint32_t rxcount = 0; + uint16_t nblocks; + + /* The upper bits of the RX COUNT value contain the size of allocated + * RX buffer. This is based on a block size of 2 or 32: + * + * USB_COUNT_RX_BL_SIZE not set: + * nblocks is in units of 2 bytes. + * 00000 - not allowed + * 00001 - 2 bytes + * .... + * 11111 - 62 bytes + * + * USB_COUNT_RX_BL_SIZE set: + * 00000 - 32 bytes + * 00001 - 64 bytes + * ... + * 01111 - 512 bytes + * 1xxxx - Not allowed + */ + + if (count > 62) + { + /* Blocks of 32 (with 0 meaning one block of 32) */ + + nblocks = (count >> 5) - 1 ; + DEBUGASSERT(nblocks <= 0x0f); + rxcount = (uint32_t)((nblocks << + USB_COUNT_RX_NUM_BLOCK_SHIFT) | USB_COUNT_RX_BL_SIZE); + } + else if (count > 0) + { + /* Blocks of 2 (with 1 meaning one block of 2) */ + + nblocks = (count + 1) >> 1; + DEBUGASSERT(nblocks > 0 && nblocks < 0x1f); + rxcount = (uint32_t)(nblocks << USB_COUNT_RX_NUM_BLOCK_SHIFT); + } + + *epaddr = rxcount; +} + +/**************************************************************************** + * Name: stm32_geteprxcount + ****************************************************************************/ + +static inline uint16_t stm32_geteprxcount(uint8_t epno) +{ + volatile uint16_t *epaddr = (uint16_t *)STM32_USB_COUNT_RX(epno); + return (*epaddr) & USB_COUNT_RX_MASK; +} + +/**************************************************************************** + * Name: stm32_seteprxaddr + ****************************************************************************/ + +static inline void stm32_seteprxaddr(uint8_t epno, uint16_t addr) +{ + volatile uint16_t *rxaddr = (uint16_t *)STM32_USB_ADDR_RX(epno); + *rxaddr = addr; +} + +/**************************************************************************** + * Name: stm32_seteprxaddr + ****************************************************************************/ + +static inline uint16_t stm32_geteprxaddr(uint8_t epno) +{ + volatile uint16_t *rxaddr = (uint16_t *)STM32_USB_ADDR_RX(epno); + return (uint16_t)*rxaddr; +} + +/**************************************************************************** + * Name: stm32_setepaddress + ****************************************************************************/ + +static inline void stm32_setepaddress(uint8_t epno, uint16_t addr) +{ + uint32_t epaddr = STM32_USB_EPR(epno); + uint16_t regval; + + regval = stm32_getreg(epaddr); + regval &= EPR_NOTOG_MASK; + regval &= ~USB_EPR_EA_MASK; + regval |= (addr << USB_EPR_EA_SHIFT); + stm32_putreg(regval, epaddr); +} + +/**************************************************************************** + * Name: stm32_seteptype + ****************************************************************************/ + +static inline void stm32_seteptype(uint8_t epno, uint16_t type) +{ + uint32_t epaddr = STM32_USB_EPR(epno); + uint16_t regval; + + regval = stm32_getreg(epaddr); + regval &= EPR_NOTOG_MASK; + regval &= ~USB_EPR_EPTYPE_MASK; + regval |= type; + stm32_putreg(regval, epaddr); +} + +/**************************************************************************** + * Name: stm32_clrstatusout + ****************************************************************************/ + +static inline void stm32_clrstatusout(uint8_t epno) +{ + uint32_t epaddr = STM32_USB_EPR(epno); + uint16_t regval; + + /* For a BULK endpoint the EP_KIND bit is used to enabled double buffering; + * for a CONTROL endpoint, it is set to indicate that a status OUT + * transaction is expected. The bit is not used with out endpoint types. + */ + + regval = stm32_getreg(epaddr); + regval &= EPR_NOTOG_MASK; + regval &= ~USB_EPR_EP_KIND; + stm32_putreg(regval, epaddr); +} + +/**************************************************************************** + * Name: stm32_clrrxdtog + ****************************************************************************/ + +static void stm32_clrrxdtog(uint8_t epno) +{ + uint32_t epaddr = STM32_USB_EPR(epno); + uint16_t regval; + + regval = stm32_getreg(epaddr); + if ((regval & USB_EPR_DTOG_RX) != 0) + { + regval &= EPR_NOTOG_MASK; + regval |= USB_EPR_DTOG_RX; + stm32_putreg(regval, epaddr); + } +} + +/**************************************************************************** + * Name: stm32_clrtxdtog + ****************************************************************************/ + +static void stm32_clrtxdtog(uint8_t epno) +{ + uint32_t epaddr = STM32_USB_EPR(epno); + uint16_t regval; + + regval = stm32_getreg(epaddr); + if ((regval & USB_EPR_DTOG_TX) != 0) + { + regval &= EPR_NOTOG_MASK; + regval |= USB_EPR_DTOG_TX; + stm32_putreg(regval, epaddr); + } +} + +/**************************************************************************** + * Name: stm32_clrepctrrx + ****************************************************************************/ + +static void stm32_clrepctrrx(uint8_t epno) +{ + uint32_t epaddr = STM32_USB_EPR(epno); + uint16_t regval; + + regval = stm32_getreg(epaddr); + regval &= EPR_NOTOG_MASK; + regval &= ~USB_EPR_CTR_RX; + stm32_putreg(regval, epaddr); +} + +/**************************************************************************** + * Name: stm32_clrepctrtx + ****************************************************************************/ + +static void stm32_clrepctrtx(uint8_t epno) +{ + uint32_t epaddr = STM32_USB_EPR(epno); + uint16_t regval; + + regval = stm32_getreg(epaddr); + regval &= EPR_NOTOG_MASK; + regval &= ~USB_EPR_CTR_TX; + stm32_putreg(regval, epaddr); +} + +/**************************************************************************** + * Name: stm32_geteptxstatus + ****************************************************************************/ + +static inline uint16_t stm32_geteptxstatus(uint8_t epno) +{ + return (uint16_t)(stm32_getreg(STM32_USB_EPR(epno)) & + USB_EPR_STATTX_MASK); +} + +/**************************************************************************** + * Name: stm32_geteprxstatus + ****************************************************************************/ + +static inline uint16_t stm32_geteprxstatus(uint8_t epno) +{ + return (stm32_getreg(STM32_USB_EPR(epno)) & USB_EPR_STATRX_MASK); +} + +/**************************************************************************** + * Name: stm32_seteptxstatus + ****************************************************************************/ + +static void stm32_seteptxstatus(uint8_t epno, uint16_t state) +{ + uint32_t epaddr = STM32_USB_EPR(epno); + uint16_t regval; + + /* The bits in the STAT_TX field can be toggled by software to set their + * value. When set to 0, the value remains unchanged; when set to one, + * value toggles. + */ + + regval = stm32_getreg(epaddr); + + /* The exclusive OR will set STAT_TX bits to 1 if there value is different + * from the bits requested in 'state' + */ + + regval ^= state; + regval &= EPR_TXDTOG_MASK; + stm32_putreg(regval, epaddr); +} + +/**************************************************************************** + * Name: stm32_seteprxstatus + ****************************************************************************/ + +static void stm32_seteprxstatus(uint8_t epno, uint16_t state) +{ + uint32_t epaddr = STM32_USB_EPR(epno); + uint16_t regval; + + /* The bits in the STAT_RX field can be toggled by software to set their + * value. When set to 0, the value remains unchanged; when set to one, + * value toggles. + */ + + regval = stm32_getreg(epaddr); + + /* The exclusive OR will set STAT_RX bits to 1 if there value is different + * from the bits requested in 'state' + */ + + regval ^= state; + regval &= EPR_RXDTOG_MASK; + stm32_putreg(regval, epaddr); +} + +/**************************************************************************** + * Name: stm32_eptxstalled + ****************************************************************************/ + +static inline bool stm32_eptxstalled(uint8_t epno) +{ + return (stm32_geteptxstatus(epno) == USB_EPR_STATTX_STALL); +} + +/**************************************************************************** + * Name: stm32_eprxstalled + ****************************************************************************/ + +static inline bool stm32_eprxstalled(uint8_t epno) +{ + return (stm32_geteprxstatus(epno) == USB_EPR_STATRX_STALL); +} + +/**************************************************************************** + * Request Helpers + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_copytopma + ****************************************************************************/ + +static void stm32_copytopma(const uint8_t *buffer, + uint16_t pma, uint16_t nbytes) +{ + uint16_t *dest; + uint16_t ms; + uint16_t ls; + int nwords = (nbytes + 1) >> 1; + int i; + + /* Copy loop. Source=user buffer, Dest=packet memory */ + + dest = (uint16_t *)(STM32_USBRAM_BASE + (uint32_t)pma); + for (i = nwords; i != 0; i--) + { + /* Read two bytes and pack into on 16-bit word */ + + ls = (uint16_t)(*buffer++); + ms = (uint16_t)(*buffer++); + *dest++ = ms << 8 | ls; + } +} + +/**************************************************************************** + * Name: stm32_copyfrompma + ****************************************************************************/ + +static inline void +stm32_copyfrompma(uint8_t *buffer, uint16_t pma, uint16_t nbytes) +{ + uint16_t *src; + int nwords = (nbytes + 1) >> 1; + int i; + + /* Copy loop. Source=packet memory, Dest=user buffer */ + + src = (uint16_t *)(STM32_USBRAM_BASE + (uint32_t)pma); + for (i = nwords; i != 0; i--) + { + /* Copy 16-bits from packet memory to user buffer. */ + + *(uint16_t *)buffer = *src++; + + /* Source address increments by 1*sizeof(uint16_t) = 2; Dest address + * increments by 2*sizeof(uint8_t) = 2. + */ + + buffer += 2; + } +} + +/**************************************************************************** + * Name: stm32_rqdequeue + ****************************************************************************/ + +static struct stm32_req_s *stm32_rqdequeue(struct stm32_ep_s *privep) +{ + struct stm32_req_s *ret = privep->head; + + if (ret) + { + privep->head = ret->flink; + if (!privep->head) + { + privep->tail = NULL; + } + + ret->flink = NULL; + } + + return ret; +} + +/**************************************************************************** + * Name: stm32_rqenqueue + ****************************************************************************/ + +static void stm32_rqenqueue(struct stm32_ep_s *privep, + struct stm32_req_s *req) +{ + req->flink = NULL; + if (!privep->head) + { + privep->head = req; + privep->tail = req; + } + else + { + privep->tail->flink = req; + privep->tail = req; + } +} + +/**************************************************************************** + * Name: stm32_abortrequest + ****************************************************************************/ + +static inline void +stm32_abortrequest(struct stm32_ep_s *privep, + struct stm32_req_s *privreq, int16_t result) +{ + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_REQABORTED), + (uint16_t)USB_EPNO(privep->ep.eplog)); + + /* Save the result in the request structure */ + + privreq->req.result = result; + + /* Callback to the request completion handler */ + + privreq->req.callback(&privep->ep, &privreq->req); +} + +/**************************************************************************** + * Name: stm32_reqcomplete + ****************************************************************************/ + +static void stm32_reqcomplete(struct stm32_ep_s *privep, int16_t result) +{ + struct stm32_req_s *privreq; + irqstate_t flags; + + /* Remove the completed request at the head of the endpoint request list */ + + flags = enter_critical_section(); + privreq = stm32_rqdequeue(privep); + leave_critical_section(flags); + + if (privreq) + { + /* If endpoint 0, temporarily reflect the state of protocol stalled + * in the callback. + */ + + bool stalled = privep->stalled; + if (USB_EPNO(privep->ep.eplog) == EP0) + { + privep->stalled = (privep->dev->ep0state == EP0STATE_STALLED); + } + + /* Save the result in the request structure */ + + privreq->req.result = result; + + /* Callback to the request completion handler */ + + privreq->flink = NULL; + privreq->req.callback(&privep->ep, &privreq->req); + + /* Restore the stalled indication */ + + privep->stalled = stalled; + } +} + +/**************************************************************************** + * Name: tm32_epwrite + ****************************************************************************/ + +static void stm32_epwrite(struct stm32_usbdev_s *priv, + struct stm32_ep_s *privep, + const uint8_t *buf, uint32_t nbytes) +{ + uint8_t epno = USB_EPNO(privep->ep.eplog); + usbtrace(TRACE_WRITE(epno), nbytes); + + /* Check for a zero-length packet */ + + if (nbytes > 0) + { + /* Copy the data from the user buffer into packet memory for this + * endpoint + */ + + stm32_copytopma(buf, stm32_geteptxaddr(epno), nbytes); + } + + /* Send the packet (might be a null packet nbytes == 0) */ + + stm32_seteptxcount(epno, nbytes); + priv->txstatus = USB_EPR_STATTX_VALID; + + /* Indicate that there is data in the TX packet memory. This will be + * cleared when the next data out interrupt is received. + */ + + privep->txbusy = true; +} + +/**************************************************************************** + * Name: stm32_wrrequest_ep0 + * + * Description: + * Handle the ep0 state on writes. + * + ****************************************************************************/ + +inline static int stm32_wrrequest_ep0(struct stm32_usbdev_s *priv, + struct stm32_ep_s *privep) +{ + int ret; + ret = stm32_wrrequest(priv, privep); + priv->ep0state = ((ret == OK) ? EP0STATE_WRREQUEST : EP0STATE_IDLE); + return ret; +} + +/**************************************************************************** + * Name: stm32_wrrequest + ****************************************************************************/ + +static int stm32_wrrequest(struct stm32_usbdev_s *priv, + struct stm32_ep_s *privep) +{ + struct stm32_req_s *privreq; + uint8_t *buf; + uint8_t epno; + int nbytes; + int bytesleft; + + /* We get here when an IN endpoint interrupt occurs. So now we know that + * there is no TX transfer in progress. + */ + + privep->txbusy = false; + + /* Check the request from the head of the endpoint request queue */ + + privreq = stm32_rqpeek(privep); + if (!privreq) + { + /* There is no TX transfer in progress and no new pending TX + * requests to send. + */ + + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPINQEMPTY), 0); + return -ENOENT; + } + + epno = USB_EPNO(privep->ep.eplog); + uinfo("epno=%d req=%p: len=%zu xfrd=%zu nullpkt=%d\n", + epno, privreq, privreq->req.len, + privreq->req.xfrd, privep->txnullpkt); + UNUSED(epno); + + /* Get the number of bytes left to be sent in the packet */ + + bytesleft = privreq->req.len - privreq->req.xfrd; + nbytes = bytesleft; + +#warning "REVISIT: If the EP supports double buffering, then we can do better" + + /* Either (1) we are committed to sending the null packet + * (because txnullpkt == 1 && nbytes == 0), or (2) we have not yet send + * the last packet (nbytes > 0). + * In either case, it is appropriate to clearn txnullpkt now. + */ + + privep->txnullpkt = 0; + + /* If we are not sending a NULL packet, then clip the size to maxpacket + * and check if we need to send a following NULL packet. + */ + + if (nbytes > 0) + { + /* Either send the maxpacketsize or all of the remaining data in + * the request. + */ + + if (nbytes >= privep->ep.maxpacket) + { + nbytes = privep->ep.maxpacket; + + /* Handle the case where this packet is exactly the + * maxpacketsize. Do we need to send a zero-length packet + * in this case? + */ + + if (bytesleft == privep->ep.maxpacket && + (privreq->req.flags & USBDEV_REQFLAGS_NULLPKT) != 0) + { + privep->txnullpkt = 1; + } + } + } + + /* Send the packet (might be a null packet nbytes == 0) */ + + buf = privreq->req.buf + privreq->req.xfrd; + stm32_epwrite(priv, privep, buf, nbytes); + + /* Update for the next data IN interrupt */ + + privreq->req.xfrd += nbytes; + bytesleft = privreq->req.len - privreq->req.xfrd; + + /* If all of the bytes were sent (including any final null packet) + * then we are finished with the request buffer). + */ + + if (bytesleft == 0 && !privep->txnullpkt) + { + /* Return the write request to the class driver */ + + usbtrace(TRACE_COMPLETE(USB_EPNO(privep->ep.eplog)), + privreq->req.xfrd); + privep->txnullpkt = 0; + stm32_reqcomplete(privep, OK); + } + + return OK; +} + +/**************************************************************************** + * Name: stm32_ep0_rdrequest + * + * Description: + * This function is called from the stm32_ep0out handler when the ep0state + * is EP0STATE_SETUP_OUT and upon new incoming data is available in the + * endpoint 0's buffer. + * This function will simply copy the OUT data into ep0data. + * + ****************************************************************************/ + +static inline int stm32_ep0_rdrequest(struct stm32_usbdev_s *priv) +{ + uint32_t src; + int pmalen; + int readlen; + + /* Get the number of bytes to read from packet memory */ + + pmalen = stm32_geteprxcount(EP0); + + uinfo("EP0: pmalen=%d\n", pmalen); + usbtrace(TRACE_READ(EP0), pmalen); + + /* Read the data into our special buffer for SETUP data */ + + readlen = MIN(CONFIG_USBDEV_SETUP_MAXDATASIZE, pmalen); + src = stm32_geteprxaddr(EP0); + + /* Receive the next packet */ + + stm32_copyfrompma(&priv->ep0data[0], src, readlen); + + /* Now we can process the setup command */ + + priv->ep0state = EP0STATE_SETUP_READY; + priv->ep0datlen = readlen; + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EP0SETUPOUTDATA), + readlen); + + stm32_ep0setup(priv); + priv->ep0datlen = 0; /* mark the date consumed */ + + return OK; +} + +/**************************************************************************** + * Name: stm32_rdrequest + ****************************************************************************/ + +static int stm32_rdrequest(struct stm32_usbdev_s *priv, + struct stm32_ep_s *privep) +{ + struct stm32_req_s *privreq; + uint32_t src; + uint8_t *dest; + uint8_t epno; + int pmalen; + int readlen; + + /* Check the request from the head of the endpoint request queue */ + + epno = USB_EPNO(privep->ep.eplog); + privreq = stm32_rqpeek(privep); + if (!privreq) + { + /* Incoming data available in PMA, but no packet to receive the data. + * Mark that the RX data is pending and hope that a packet is returned + * soon. + */ + + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPOUTQEMPTY), epno); + return -ENOENT; + } + + uinfo("EP%d: len=%zu xfrd=%zu\n", + epno, privreq->req.len, privreq->req.xfrd); + + /* Ignore any attempt to receive a zero length packet */ + + if (privreq->req.len == 0) + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EPOUTNULLPACKET), 0); + stm32_reqcomplete(privep, OK); + return OK; + } + + usbtrace(TRACE_READ(USB_EPNO(privep->ep.eplog)), privreq->req.xfrd); + + /* Get the source and destination transfer addresses */ + + dest = privreq->req.buf + privreq->req.xfrd; + src = stm32_geteprxaddr(epno); + + /* Get the number of bytes to read from packet memory */ + + pmalen = stm32_geteprxcount(epno); + readlen = MIN(privreq->req.len, pmalen); + + /* Receive the next packet */ + + stm32_copyfrompma(dest, src, readlen); + + /* If the receive buffer is full or this is a partial packet, + * then we are finished with the request buffer). + */ + + privreq->req.xfrd += readlen; + if (pmalen < privep->ep.maxpacket || privreq->req.xfrd >= privreq->req.len) + { + /* Return the read request to the class driver. */ + + usbtrace(TRACE_COMPLETE(epno), privreq->req.xfrd); + stm32_reqcomplete(privep, OK); + } + + return OK; +} + +/**************************************************************************** + * Name: stm32_cancelrequests + ****************************************************************************/ + +static void stm32_cancelrequests(struct stm32_ep_s *privep) +{ + while (!stm32_rqempty(privep)) + { + usbtrace(TRACE_COMPLETE(USB_EPNO(privep->ep.eplog)), + (stm32_rqpeek(privep))->req.xfrd); + stm32_reqcomplete(privep, -ESHUTDOWN); + } +} + +/**************************************************************************** + * Interrupt Level Processing + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_dispatchrequest + ****************************************************************************/ + +static void stm32_dispatchrequest(struct stm32_usbdev_s *priv) +{ + int ret; + + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_DISPATCH), 0); + if (priv && priv->driver) + { + /* Forward to the control request to the class driver implementation */ + + ret = CLASS_SETUP(priv->driver, &priv->usbdev, &priv->ctrl, + priv->ep0data, priv->ep0datlen); + if (ret < 0) + { + /* Stall on failure */ + + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_DISPATCHSTALL), 0); + priv->ep0state = EP0STATE_STALLED; + } + } +} + +/**************************************************************************** + * Name: stm32_epdone + ****************************************************************************/ + +static void stm32_epdone(struct stm32_usbdev_s *priv, uint8_t epno) +{ + struct stm32_ep_s *privep; + uint16_t epr; + + /* Decode and service non control endpoints interrupt */ + + epr = stm32_getreg(STM32_USB_EPR(epno)); + privep = &priv->eplist[epno]; + + /* OUT: host-to-device + * CTR_RX is set by the hardware when an OUT/SETUP transaction + * successfully completed on this endpoint. + */ + + if ((epr & USB_EPR_CTR_RX) != 0) + { + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPOUTDONE), epr); + + /* Handle read requests. First check if a read request is available to + * accept the host data. + */ + + if (!stm32_rqempty(privep)) + { + /* Read host data into the current read request */ + + stm32_rdrequest(priv, privep); + + /* "After the received data is processed, the application software + * should set the STAT_RX bits to '11' (Valid) in the USB_EPnR, + * enabling further transactions. " + */ + + priv->rxstatus = USB_EPR_STATRX_VALID; + } + + /* NAK further OUT packets if there there no more read requests */ + + if (stm32_rqempty(privep)) + { + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPOUTPENDING), + (uint16_t)epno); + + /* Mark the RX processing as pending and NAK any OUT actions + * on this endpoint. "While the STAT_RX bits are equal to '10' + * (NAK), any OUT request addressed to that endpoint is NAKed, + * indicating a flow control condition: the USB host will retry + * the transaction until it succeeds." + */ + + priv->rxstatus = USB_EPR_STATRX_NAK; + priv->rxpending = true; + } + + /* Clear the interrupt status and set the new RX status */ + + stm32_clrepctrrx(epno); + stm32_seteprxstatus(epno, priv->rxstatus); + } + + /* IN: device-to-host + * CTR_TX is set when an IN transaction successfully completes on + * an endpoint + */ + + else if ((epr & USB_EPR_CTR_TX) != 0) + { + /* Clear interrupt status */ + + stm32_clrepctrtx(epno); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPINDONE), epr); + + /* Handle write requests */ + + priv->txstatus = USB_EPR_STATTX_NAK; + if (epno == EP0) + { + stm32_wrrequest_ep0(priv, privep); + } + else + { + stm32_wrrequest(priv, privep); + } + + /* Set the new TX status */ + + stm32_seteptxstatus(epno, priv->txstatus); + } +} + +/**************************************************************************** + * Name: stm32_setdevaddr + ****************************************************************************/ + +static void stm32_setdevaddr(struct stm32_usbdev_s *priv, uint8_t value) +{ + int epno; + + /* Set address in every allocated endpoint */ + + for (epno = 0; epno < STM32_NENDPOINTS; epno++) + { + if (stm32_epreserved(priv, epno)) + { + stm32_setepaddress((uint8_t)epno, (uint8_t)epno); + } + } + + /* Set the device address and enable function */ + + stm32_putreg(value | USB_DADDR_EF, STM32_USB_DADDR); +} + +/**************************************************************************** + * Name: stm32_ep0setup + ****************************************************************************/ + +static void stm32_ep0setup(struct stm32_usbdev_s *priv) +{ + struct stm32_ep_s *ep0 = &priv->eplist[EP0]; + struct stm32_req_s *privreq = stm32_rqpeek(ep0); + struct stm32_ep_s *privep; + union wb_u value; + union wb_u index; + union wb_u len; + union wb_u response; + bool handled = false; + uint8_t epno; + int nbytes = 0; /* Assume zero-length packet */ + + /* Terminate any pending requests (doesn't work if the pending request + * was a zero-length transfer!) + */ + + while (!stm32_rqempty(ep0)) + { + int16_t result = OK; + if (privreq->req.xfrd != privreq->req.len) + { + result = -EPROTO; + } + + usbtrace(TRACE_COMPLETE(ep0->ep.eplog), privreq->req.xfrd); + stm32_reqcomplete(ep0, result); + } + + /* Assume NOT stalled; no TX in progress */ + + ep0->stalled = 0; + ep0->txbusy = 0; + + value.w = 0; + index.w = 0; + len.w = 0; + response.w = 0; + + /* Check to see if called from the DATA phase of a SETUP Transfer */ + + if (priv->ep0state != EP0STATE_SETUP_READY) + { + /* Not the data phase */ + + /* Get a 32-bit PMA address and use that to get the 8-byte setup + * request + */ + + stm32_copyfrompma((uint8_t *)&priv->ctrl, stm32_geteprxaddr(EP0), + USB_SIZEOF_CTRLREQ); + + /* And extract the little-endian 16-bit values to host order */ + + value.w = GETUINT16(priv->ctrl.value); + index.w = GETUINT16(priv->ctrl.index); + len.w = GETUINT16(priv->ctrl.len); + + uinfo("SETUP: type=%02x req=%02x value=%04x index=%04x len=%04x\n", + priv->ctrl.type, priv->ctrl.req, value.w, index.w, len.w); + + /* Is this an setup with OUT and data of length > 0 */ + + if (USB_REQ_ISOUT(priv->ctrl.type) && len.w > 0) + { + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EP0SETUPOUT), len.w); + + /* At this point priv->ctrl is the setup packet. */ + + priv->ep0state = EP0STATE_SETUP_OUT; + return; + } + else + { + priv->ep0state = EP0STATE_SETUP_READY; + } + } + + /* Dispatch any non-standard requests */ + + if ((priv->ctrl.type & USB_REQ_TYPE_MASK) != USB_REQ_TYPE_STANDARD) + { + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_NOSTDREQ), priv->ctrl.type); + + /* Let the class implementation handle all non-standar requests */ + + stm32_dispatchrequest(priv); + return; + } + + /* Handle standard request. Pick off the things of interest to the + * USB device controller driver; pass what is left to the class driver + */ + + switch (priv->ctrl.req) + { + case USB_REQ_GETSTATUS: + { + /* type: device-to-host; recipient = device, interface, endpoint + * value: 0 + * index: zero interface endpoint + * len: 2; data = status + */ + + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_GETSTATUS), + priv->ctrl.type); + if (len.w != 2 || (priv->ctrl.type & + USB_REQ_DIR_IN) == 0 || + index.b[MSB] != 0 || value.w != 0) + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADEPGETSTATUS), 0); + priv->ep0state = EP0STATE_STALLED; + } + else + { + switch (priv->ctrl.type & USB_REQ_RECIPIENT_MASK) + { + case USB_REQ_RECIPIENT_ENDPOINT: + { + epno = USB_EPNO(index.b[LSB]); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPGETSTATUS), + epno); + if (epno >= STM32_NENDPOINTS) + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADEPGETSTATUS), + epno); + priv->ep0state = EP0STATE_STALLED; + } + else + { + response.w = 0; /* Not stalled */ + nbytes = 2; /* Response size: 2 bytes */ + + if (USB_ISEPIN(index.b[LSB])) + { + /* IN endpoint */ + + if (stm32_eptxstalled(epno)) + { + /* IN Endpoint stalled */ + + response.b[LSB] = 1; /* Stalled */ + } + } + else + { + /* OUT endpoint */ + + if (stm32_eprxstalled(epno)) + { + /* OUT Endpoint stalled */ + + response.b[LSB] = 1; /* Stalled */ + } + } + } + } + break; + + case USB_REQ_RECIPIENT_DEVICE: + { + if (index.w == 0) + { + usbtrace(TRACE_INTDECODE( + STM32_TRACEINTID_DEVGETSTATUS), 0); + + /* Features: Remote Wakeup=YES; selfpowered=? */ + + response.w = 0; + response.b[LSB] = (priv->selfpowered << + USB_FEATURE_SELFPOWERED) | + (1 << USB_FEATURE_REMOTEWAKEUP); + nbytes = 2; /* Response size: 2 bytes */ + } + else + { + usbtrace(TRACE_DEVERROR( + STM32_TRACEERR_BADDEVGETSTATUS), 0); + priv->ep0state = EP0STATE_STALLED; + } + } + break; + + case USB_REQ_RECIPIENT_INTERFACE: + { + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_IFGETSTATUS), 0); + response.w = 0; + nbytes = 2; /* Response size: 2 bytes */ + } + break; + + default: + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADGETSTATUS), 0); + priv->ep0state = EP0STATE_STALLED; + } + break; + } + } + } + break; + + case USB_REQ_CLEARFEATURE: + { + /* type: host-to-device; recipient = device, interface or endpoint + * value: feature selector + * index: zero interface endpoint; + * len: zero, data = none + */ + + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_CLEARFEATURE), + priv->ctrl.type); + if ((priv->ctrl.type & USB_REQ_RECIPIENT_MASK) != + USB_REQ_RECIPIENT_ENDPOINT) + { + /* Let the class implementation handle all recipients + * (except for the endpoint recipient) + */ + + stm32_dispatchrequest(priv); + handled = true; + } + else + { + /* Endpoint recipient */ + + epno = USB_EPNO(index.b[LSB]); + if (epno < STM32_NENDPOINTS && index.b[MSB] == 0 && + value.w == USB_FEATURE_ENDPOINTHALT && len.w == 0) + { + privep = &priv->eplist[epno]; + privep->halted = 0; + stm32_epstall(&privep->ep, true); + } + else + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADCLEARFEATURE), 0); + priv->ep0state = EP0STATE_STALLED; + } + } + } + break; + + case USB_REQ_SETFEATURE: + { + /* type: host-to-device; recipient = device, interface, endpoint + * value: feature selector + * index: zero interface endpoint; + * len: 0; data = none + */ + + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SETFEATURE), + priv->ctrl.type); + if (((priv->ctrl.type & USB_REQ_RECIPIENT_MASK) == + USB_REQ_RECIPIENT_DEVICE) && + value.w == USB_FEATURE_TESTMODE) + { + /* Special case recipient=device test mode */ + + uinfo("test mode: %d\n", index.w); + } + else if ((priv->ctrl.type & USB_REQ_RECIPIENT_MASK) != + USB_REQ_RECIPIENT_ENDPOINT) + { + /* The class driver handles all recipients except + * recipient=endpoint + */ + + stm32_dispatchrequest(priv); + handled = true; + } + else + { + /* Handler recipient=endpoint */ + + epno = USB_EPNO(index.b[LSB]); + if (epno < STM32_NENDPOINTS && index.b[MSB] == 0 && + value.w == USB_FEATURE_ENDPOINTHALT && len.w == 0) + { + privep = &priv->eplist[epno]; + privep->halted = 1; + stm32_epstall(&privep->ep, false); + } + else + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADSETFEATURE), 0); + priv->ep0state = EP0STATE_STALLED; + } + } + } + break; + + case USB_REQ_SETADDRESS: + { + /* type: host-to-device; recipient = device + * value: device address + * index: 0 + * len: 0; data = none + */ + + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EP0SETUPSETADDRESS), + value.w); + if ((priv->ctrl.type & USB_REQ_RECIPIENT_MASK) != + USB_REQ_RECIPIENT_DEVICE || + index.w != 0 || len.w != 0 || value.w > 127) + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADSETADDRESS), 0); + priv->ep0state = EP0STATE_STALLED; + } + /* Note that setting of the device address will be deferred. + * A zero-length packet will be sent and the device address + * will be set when the zero- length packet transfer completes. + */ + } + break; + + case USB_REQ_GETDESCRIPTOR: + /* type: device-to-host; recipient = device + * value: descriptor type and index + * index: 0 or language ID; + * len: descriptor len; data = descriptor + */ + + case USB_REQ_SETDESCRIPTOR: + /* type: host-to-device; recipient = device + * value: descriptor type and index + * index: 0 or language ID; + * len: descriptor len; data = descriptor + */ + + { + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_GETSETDESC), + priv->ctrl.type); + + /* The request seems valid... + * let the class implementation handle it + */ + + stm32_dispatchrequest(priv); + handled = true; + } + break; + + case USB_REQ_GETCONFIGURATION: + /* type: device-to-host; recipient = device + * value: 0; + * index: 0; + * len: 1; data = configuration value + */ + + { + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_GETCONFIG), + priv->ctrl.type); + if ((priv->ctrl.type & USB_REQ_RECIPIENT_MASK) == + USB_REQ_RECIPIENT_DEVICE && + value.w == 0 && index.w == 0 && len.w == 1) + { + /* The request seems valid... + * let the class implementation handle it + */ + + stm32_dispatchrequest(priv); + handled = true; + } + else + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADGETCONFIG), 0); + priv->ep0state = EP0STATE_STALLED; + } + } + break; + + case USB_REQ_SETCONFIGURATION: + /* type: host-to-device; recipient = device + * value: configuration value + * index: 0; + * len: 0; data = none + */ + + { + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SETCONFIG), + priv->ctrl.type); + if ((priv->ctrl.type & USB_REQ_RECIPIENT_MASK) == + USB_REQ_RECIPIENT_DEVICE && + index.w == 0 && len.w == 0) + { + /* The request seems valid... + * let the class implementation handle it + */ + + stm32_dispatchrequest(priv); + handled = true; + } + else + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADSETCONFIG), 0); + priv->ep0state = EP0STATE_STALLED; + } + } + break; + + case USB_REQ_GETINTERFACE: + /* type: device-to-host; recipient = interface + * value: 0 + * index: interface; + * len: 1; data = alt interface + */ + + case USB_REQ_SETINTERFACE: + /* type: host-to-device; recipient = interface + * value: alternate setting + * index: interface; + * len: 0; data = none + */ + + { + /* Let the class implementation handle the request */ + + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_GETSETIF), + priv->ctrl.type); + stm32_dispatchrequest(priv); + handled = true; + } + break; + + case USB_REQ_SYNCHFRAME: + /* type: device-to-host; recipient = endpoint + * value: 0 + * index: endpoint; + * len: 2; data = frame number + */ + + { + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SYNCHFRAME), 0); + } + break; + + default: + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDCTRLREQ), + priv->ctrl.req); + priv->ep0state = EP0STATE_STALLED; + } + break; + } + + /* At this point, the request has been handled and there are three possible + * outcomes: + * + * 1. The setup request was successfully handled above and a response + * packet must be sent (may be a zero length packet). + * 2. The request was successfully handled by the class implementation. + * In case, the EP0 IN response has already been queued and the local + * variable 'handled' will be set to true and + * ep0state != EP0STATE_STALLED; + * 3. An error was detected in either the above logic or by the class + * implementation logic. In either case, priv->state will be set + * EP0STATE_STALLED to indicate this case. + * + * NOTE: + * Non-standard requests are a special case. They are handled by the + * class implementation and this function returned early above, skipping + * this logic altogether. + */ + + if (priv->ep0state != EP0STATE_STALLED && !handled) + { + /* We will response. First, restrict the data length to the length + * requested in the setup packet + */ + + if (nbytes > len.w) + { + nbytes = len.w; + } + + /* Send the response (might be a zero-length packet) */ + + stm32_epwrite(priv, ep0, response.b, nbytes); + priv->ep0state = EP0STATE_IDLE; + } +} + +/**************************************************************************** + * Name: stm32_ep0in + ****************************************************************************/ + +static void stm32_ep0in(struct stm32_usbdev_s *priv) +{ + /* There is no longer anything in the EP0 TX packet memory */ + + priv->eplist[EP0].txbusy = false; + + /* Are we processing the completion of one packet of an outgoing request + * from the class driver? + */ + + if (priv->ep0state == EP0STATE_WRREQUEST) + { + stm32_wrrequest_ep0(priv, &priv->eplist[EP0]); + } + + /* No.. Are we processing the completion of a status response? */ + + else if (priv->ep0state == EP0STATE_IDLE) + { + /* Look at the saved SETUP command. Was it a SET ADDRESS request? + * If so, then now is the time to set the address. + */ + + if (priv->ctrl.req == USB_REQ_SETADDRESS && + (priv->ctrl.type & REQRECIPIENT_MASK) == + (USB_REQ_TYPE_STANDARD | USB_REQ_RECIPIENT_DEVICE)) + { + union wb_u value; + value.w = GETUINT16(priv->ctrl.value); + stm32_setdevaddr(priv, value.b[LSB]); + } + } + else + { + priv->ep0state = EP0STATE_STALLED; + } +} + +/**************************************************************************** + * Name: stm32_ep0out + ****************************************************************************/ + +static void stm32_ep0out(struct stm32_usbdev_s *priv) +{ + int ret; + + struct stm32_ep_s *privep = &priv->eplist[EP0]; + switch (priv->ep0state) + { + case EP0STATE_RDREQUEST: /* Read request in progress */ + case EP0STATE_IDLE: /* No transfer in progress */ + ret = stm32_rdrequest(priv, privep); + priv->ep0state = ((ret == OK) ? EP0STATE_RDREQUEST : EP0STATE_IDLE); + break; + + case EP0STATE_SETUP_OUT: /* SETUP was waiting for data */ + ret = stm32_ep0_rdrequest(priv); /* Off load the data and run the + * last set up command with the OUT + * data + */ + priv->ep0state = EP0STATE_IDLE; /* There is no notion of receiving OUT + * data greater then the length of + * CONFIG_USBDEV_SETUP_MAXDATASIZE + * so we are done + */ + break; + + default: + /* Unexpected state OR host aborted the OUT transfer before it + * completed, STALL the endpoint in either case + */ + + priv->ep0state = EP0STATE_STALLED; + break; + } +} + +/**************************************************************************** + * Name: stm32_ep0done + ****************************************************************************/ + +static inline void stm32_ep0done(struct stm32_usbdev_s *priv, uint16_t istr) +{ + uint16_t epr; + + /* Initialize RX and TX status. We shouldn't have to actually look at the + * status because the hardware is supposed to set the both RX and TX status + * to NAK when an EP0 SETUP occurs (of course, this might not be a setup) + */ + + priv->rxstatus = USB_EPR_STATRX_NAK; + priv->txstatus = USB_EPR_STATTX_NAK; + + /* Set both RX and TX status to NAK */ + + stm32_seteprxstatus(EP0, USB_EPR_STATRX_NAK); + stm32_seteptxstatus(EP0, USB_EPR_STATTX_NAK); + + /* Check the direction bit to determine if this the completion of an EP0 + * packet sent to or received from the host PC. + */ + + if ((istr & USB_ISTR_DIR) == 0) + { + /* EP0 IN: device-to-host (DIR=0) */ + + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EP0IN), istr); + stm32_clrepctrtx(EP0); + stm32_ep0in(priv); + } + else + { + /* EP0 OUT: host-to-device (DIR=1) */ + + epr = stm32_getreg(STM32_USB_EPR(EP0)); + + /* CTR_TX is set when an IN transaction successfully + * completes on an endpoint + */ + + if ((epr & USB_EPR_CTR_TX) != 0) + { + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EP0INDONE), epr); + stm32_clrepctrtx(EP0); + stm32_ep0in(priv); + } + + /* SETUP is set by the hardware when the last completed + * transaction was a control endpoint SETUP + */ + + else if ((epr & USB_EPR_SETUP) != 0) + { + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EP0SETUPDONE), epr); + stm32_clrepctrrx(EP0); + stm32_ep0setup(priv); + } + + /* Set by the hardware when an OUT/SETUP transaction successfully + * completed on this endpoint. + */ + + else if ((epr & USB_EPR_CTR_RX) != 0) + { + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EP0OUTDONE), epr); + stm32_clrepctrrx(EP0); + stm32_ep0out(priv); + } + + /* None of the above */ + + else + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EP0BADCTR), epr); + return; /* Does this ever happen? */ + } + } + + /* Make sure that the EP0 packet size is still OK (superstitious?) */ + + stm32_seteprxcount(EP0, STM32_EP0MAXPACKET); + + /* Now figure out the new RX/TX status. Here are all possible + * consequences of the above EP0 operations: + * + * rxstatus txstatus ep0state MEANING + * -------- -------- --------- --------------------------------- + * NAK NAK IDLE Nothing happened + * NAK VALID IDLE EP0 response sent from USBDEV driver + * NAK VALID WRREQUEST EP0 response sent from class driver + * NAK --- STALL Some protocol error occurred + * + * First handle the STALL condition: + */ + + if (priv->ep0state == EP0STATE_STALLED) + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EP0SETUPSTALLED), + priv->ep0state); + priv->rxstatus = USB_EPR_STATRX_STALL; + priv->txstatus = USB_EPR_STATTX_STALL; + } + + /* Was a transmission started? If so, txstatus will be VALID. The + * only special case to handle is when both are set to NAK. In that + * case, we need to set RX status to VALID in order to accept the next + * SETUP request. + */ + + else if (priv->rxstatus == USB_EPR_STATRX_NAK && + priv->txstatus == USB_EPR_STATTX_NAK) + { + priv->rxstatus = USB_EPR_STATRX_VALID; + } + + /* Now set the new TX and RX status */ + + stm32_seteprxstatus(EP0, priv->rxstatus); + stm32_seteptxstatus(EP0, priv->txstatus); +} + +/**************************************************************************** + * Name: stm32_lptransfer + ****************************************************************************/ + +static void stm32_lptransfer(struct stm32_usbdev_s *priv) +{ + uint8_t epno; + uint16_t istr; + + /* Stay in loop while LP interrupts are pending */ + + while (((istr = stm32_getreg(STM32_USB_ISTR)) & USB_ISTR_CTR) != 0) + { + stm32_putreg((uint16_t)~USB_ISTR_CTR, STM32_USB_ISTR); + + /* Extract highest priority endpoint number */ + + epno = (uint8_t)(istr & USB_ISTR_EPID_MASK); + + /* Handle EP0 completion events */ + + if (epno == 0) + { + stm32_ep0done(priv, istr); + } + + /* Handle other endpoint completion events */ + + else + { + stm32_epdone(priv, epno); + } + } +} + +/**************************************************************************** + * Name: stm32_hpinterrupt + ****************************************************************************/ + +static int stm32_hpinterrupt(int irq, void *context, void *arg) +{ + /* For now there is only one USB controller, but we will always refer to + * it using a pointer to make any future ports to multiple USB controllers + * easier. + */ + + struct stm32_usbdev_s *priv = &g_usbdev; + uint16_t istr; + uint8_t epno; + + /* High priority interrupts are only triggered by a correct transfer event + * for isochronous and double-buffer bulk transfers. + */ + + istr = stm32_getreg(STM32_USB_ISTR); + usbtrace(TRACE_INTENTRY(STM32_TRACEINTID_HPINTERRUPT), istr); + while ((istr & USB_ISTR_CTR) != 0) + { + stm32_putreg((uint16_t)~USB_ISTR_CTR, STM32_USB_ISTR); + + /* Extract highest priority endpoint number */ + + epno = (uint8_t)(istr & USB_ISTR_EPID_MASK); + + /* And handle the completion event */ + + stm32_epdone(priv, epno); + + /* Fetch the status again for the next time through the loop */ + + istr = stm32_getreg(STM32_USB_ISTR); + } + + usbtrace(TRACE_INTEXIT(STM32_TRACEINTID_HPINTERRUPT), 0); + return OK; +} + +/**************************************************************************** + * Name: stm32_lpinterrupt + ****************************************************************************/ + +static int stm32_lpinterrupt(int irq, void *context, void *arg) +{ + /* For now there is only one USB controller, but we will always refer to + * it using a pointer to make any future ports to multiple USB controllers + * easier. + */ + + struct stm32_usbdev_s *priv = &g_usbdev; + uint16_t istr = stm32_getreg(STM32_USB_ISTR); + + usbtrace(TRACE_INTENTRY(STM32_TRACEINTID_LPINTERRUPT), istr); + + /* Handle Reset interrupts. When this event occurs, the peripheral is left + * in the same conditions it is left by the system reset (but with the + * USB controller enabled). + */ + + if ((istr & USB_ISTR_RESET) != 0) + { + /* Reset interrupt received. Clear the RESET interrupt status. */ + + stm32_putreg(~USB_ISTR_RESET, STM32_USB_ISTR); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_RESET), istr); + + /* Restore our power-up state and exit now because istr is no longer + * valid. + */ + + stm32_reset(priv); + goto exit_lpinterrupt; + } + + /* Handle Wakeup interrupts. + * This interrupt is only enable while the USB is suspended. + */ + + if ((istr & USB_ISTR_WKUP & priv->imask) != 0) + { + /* Wakeup interrupt received. Clear the WKUP interrupt status. The + * cause of the resume is indicated in the FNR register + */ + + stm32_putreg(~USB_ISTR_WKUP, STM32_USB_ISTR); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_WKUP), + stm32_getreg(STM32_USB_FNR)); + + /* Perform the wakeup action */ + + stm32_initresume(priv); + priv->rsmstate = RSMSTATE_IDLE; + + /* Disable ESOF polling, disable the wakeup interrupt, and + * re-enable the suspend interrupt. Clear any pending SUSP + * interrupts. + */ + + stm32_setimask(priv, USB_CNTR_SUSPM, USB_CNTR_ESOFM | USB_CNTR_WKUPM); + stm32_putreg(~USB_CNTR_SUSPM, STM32_USB_ISTR); + } + + if ((istr & USB_ISTR_SUSP & priv->imask) != 0) + { + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SUSP), 0); + stm32_suspend(priv); + + /* Clear of the ISTR bit must be done after setting + * of USB_CNTR_FSUSP + */ + + stm32_putreg(~USB_ISTR_SUSP, STM32_USB_ISTR); + } + + if ((istr & USB_ISTR_ESOF & priv->imask) != 0) + { + stm32_putreg(~USB_ISTR_ESOF, STM32_USB_ISTR); + + /* Resume handling timing is made with ESOFs */ + + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_ESOF), 0); + stm32_esofpoll(priv); + } + + if ((istr & USB_ISTR_CTR & priv->imask) != 0) + { + /* Low priority endpoint correct transfer interrupt */ + + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_LPCTR), istr); + stm32_lptransfer(priv); + } + +exit_lpinterrupt: + usbtrace(TRACE_INTEXIT(STM32_TRACEINTID_LPINTERRUPT), + stm32_getreg(STM32_USB_EP0R)); + return OK; +} + +/**************************************************************************** + * Name: stm32_setimask + ****************************************************************************/ + +static void +stm32_setimask(struct stm32_usbdev_s *priv, + uint16_t setbits, uint16_t clrbits) +{ + uint16_t regval; + + /* Adjust the interrupt mask bits in the shadow copy first */ + + priv->imask &= ~clrbits; + priv->imask |= setbits; + + /* Then make the interrupt mask bits in the CNTR register match the shadow + * register (Hmmm... who is shadowing whom?) + */ + + regval = stm32_getreg(STM32_USB_CNTR); + regval &= ~USB_CNTR_ALLINTS; + regval |= priv->imask; + stm32_putreg(regval, STM32_USB_CNTR); +} + +/**************************************************************************** + * Suspend/Resume Helpers + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_suspend + ****************************************************************************/ + +static void stm32_suspend(struct stm32_usbdev_s *priv) +{ + uint16_t regval; + + /* Notify the class driver of the suspend event */ + + if (priv->driver) + { + CLASS_SUSPEND(priv->driver, &priv->usbdev); + } + + /* Disable ESOF polling, disable the SUSP interrupt, and enable the WKUP + * interrupt. Clear any pending WKUP interrupt. + */ + + stm32_setimask(priv, USB_CNTR_WKUPM, USB_CNTR_ESOFM | USB_CNTR_SUSPM); + stm32_putreg(~USB_ISTR_WKUP, STM32_USB_ISTR); + + /* Set the FSUSP bit in the CNTR register. This activates suspend mode + * within the USB peripheral and disables further SUSP interrupts. + */ + + regval = stm32_getreg(STM32_USB_CNTR); + regval |= USB_CNTR_FSUSP; + stm32_putreg(regval, STM32_USB_CNTR); + + /* If we are not a self-powered device, the got to low-power mode */ + + if (!priv->selfpowered) + { + /* Setting LPMODE in the CNTR register removes static power + * consumption in the USB analog transceivers but keeps them + * able to detect resume activity + */ + + regval = stm32_getreg(STM32_USB_CNTR); + regval |= USB_CNTR_LPMODE; + stm32_putreg(regval, STM32_USB_CNTR); + } + + /* Let the board-specific logic know that we have entered the suspend + * state + */ + + stm32_usbsuspend((struct usbdev_s *)priv, false); +} + +/**************************************************************************** + * Name: stm32_initresume + ****************************************************************************/ + +static void stm32_initresume(struct stm32_usbdev_s *priv) +{ + uint16_t regval; + + /* This function is called when either (1) a WKUP interrupt is received + * from the host PC, or (2) the class device implementation calls the + * wakeup() method. + */ + + /* Clear the USB low power mode (lower power mode was not set if this is + * a self-powered device. Also, low power mode is automatically cleared by + * hardware when a WKUP interrupt event occurs). + */ + + regval = stm32_getreg(STM32_USB_CNTR); + regval &= (~USB_CNTR_LPMODE); + stm32_putreg(regval, STM32_USB_CNTR); + + /* Restore full power -- whatever that means for this particular board */ + + stm32_usbsuspend((struct usbdev_s *)priv, true); + + /* Reset FSUSP bit and enable normal interrupt handling */ + + stm32_putreg(STM32_CNTR_SETUP, STM32_USB_CNTR); + + /* Notify the class driver of the resume event */ + + if (priv->driver) + { + CLASS_RESUME(priv->driver, &priv->usbdev); + } +} + +/**************************************************************************** + * Name: stm32_esofpoll + ****************************************************************************/ + +static void stm32_esofpoll(struct stm32_usbdev_s *priv) +{ + uint16_t regval; + + /* Called periodically from ESOF interrupt after RSMSTATE_STARTED */ + + switch (priv->rsmstate) + { + /* One ESOF after internal resume requested */ + + case RSMSTATE_STARTED: + regval = stm32_getreg(STM32_USB_CNTR); + regval |= USB_CNTR_RESUME; + stm32_putreg(regval, STM32_USB_CNTR); + priv->rsmstate = RSMSTATE_WAITING; + priv->nesofs = 10; + break; + + /* Countdown before completing the operation */ + + case RSMSTATE_WAITING: + priv->nesofs--; + if (priv->nesofs == 0) + { + /* Okay.. we are ready to resume normal operation */ + + regval = stm32_getreg(STM32_USB_CNTR); + regval &= (~USB_CNTR_RESUME); + stm32_putreg(regval, STM32_USB_CNTR); + priv->rsmstate = RSMSTATE_IDLE; + + /* Disable ESOF polling, disable the SUSP interrupt, and enable + * the WKUP interrupt. Clear any pending WKUP interrupt. + */ + + stm32_setimask(priv, + USB_CNTR_WKUPM, USB_CNTR_ESOFM | USB_CNTR_SUSPM); + stm32_putreg(~USB_ISTR_WKUP, STM32_USB_ISTR); + } + break; + + case RSMSTATE_IDLE: + default: + priv->rsmstate = RSMSTATE_IDLE; + break; + } +} + +/**************************************************************************** + * Endpoint Helpers + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_epreserve + ****************************************************************************/ + +static inline struct stm32_ep_s * +stm32_epreserve(struct stm32_usbdev_s *priv, uint8_t epset) +{ + struct stm32_ep_s *privep = NULL; + irqstate_t flags; + int epndx = 0; + + flags = enter_critical_section(); + epset &= priv->epavail; + if (epset) + { + /* Select the lowest bit in the set of matching, available endpoints + * (skipping EP0) + */ + + for (epndx = 1; epndx < STM32_NENDPOINTS; epndx++) + { + uint8_t bit = STM32_ENDP_BIT(epndx); + if ((epset & bit) != 0) + { + /* Mark the endpoint no longer available */ + + priv->epavail &= ~bit; + + /* And return the pointer to the standard endpoint structure */ + + privep = &priv->eplist[epndx]; + break; + } + } + } + + leave_critical_section(flags); + return privep; +} + +/**************************************************************************** + * Name: stm32_epunreserve + ****************************************************************************/ + +static inline void +stm32_epunreserve(struct stm32_usbdev_s *priv, struct stm32_ep_s *privep) +{ + irqstate_t flags = enter_critical_section(); + priv->epavail |= STM32_ENDP_BIT(USB_EPNO(privep->ep.eplog)); + leave_critical_section(flags); +} + +/**************************************************************************** + * Name: stm32_epreserved + ****************************************************************************/ + +static inline bool +stm32_epreserved(struct stm32_usbdev_s *priv, int epno) +{ + return ((priv->epavail & STM32_ENDP_BIT(epno)) == 0); +} + +/**************************************************************************** + * Name: stm32_epallocpma + ****************************************************************************/ + +static int stm32_epallocpma(struct stm32_usbdev_s *priv) +{ + irqstate_t flags; + int bufno = ERROR; + int bufndx; + + flags = enter_critical_section(); + for (bufndx = 2; bufndx < STM32_NBUFFERS; bufndx++) + { + /* Check if this buffer is available */ + + uint8_t bit = STM32_BUFFER_BIT(bufndx); + if ((priv->bufavail & bit) != 0) + { + /* Yes.. Mark the endpoint no longer available */ + + priv->bufavail &= ~bit; + + /* And return the index of the allocated buffer */ + + bufno = bufndx; + break; + } + } + + leave_critical_section(flags); + return bufno; +} + +/**************************************************************************** + * Name: stm32_epfreepma + ****************************************************************************/ + +static inline void +stm32_epfreepma(struct stm32_usbdev_s *priv, struct stm32_ep_s *privep) +{ + irqstate_t flags = enter_critical_section(); + priv->epavail |= STM32_ENDP_BIT(privep->bufno); + leave_critical_section(flags); +} + +/**************************************************************************** + * Endpoint operations + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_epconfigure + ****************************************************************************/ + +static int stm32_epconfigure(struct usbdev_ep_s *ep, + const struct usb_epdesc_s *desc, + bool last) +{ + struct stm32_ep_s *privep = (struct stm32_ep_s *)ep; + uint16_t pma; + uint16_t setting; + uint16_t maxpacket; + uint8_t epno; + +#ifdef CONFIG_DEBUG_FEATURES + if (!ep || !desc) + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); + uerr("ERROR: ep=%p desc=%p\n", ep, desc); + return -EINVAL; + } +#endif + + /* Get the unadorned endpoint address */ + + epno = USB_EPNO(desc->addr); + usbtrace(TRACE_EPCONFIGURE, (uint16_t)epno); + DEBUGASSERT(epno == USB_EPNO(ep->eplog)); + + /* Set the requested type */ + + switch (desc->attr & USB_EP_ATTR_XFERTYPE_MASK) + { + case USB_EP_ATTR_XFER_INT: /* Interrupt endpoint */ + setting = USB_EPR_EPTYPE_INTERRUPT; + break; + + case USB_EP_ATTR_XFER_BULK: /* Bulk endpoint */ + setting = USB_EPR_EPTYPE_BULK; + break; + + case USB_EP_ATTR_XFER_ISOC: /* Isochronous endpoint */ +#warning "REVISIT: Need to review isochronous EP setup" + setting = USB_EPR_EPTYPE_ISOC; + break; + + case USB_EP_ATTR_XFER_CONTROL: /* Control endpoint */ + setting = USB_EPR_EPTYPE_CONTROL; + break; + + default: + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADEPTYPE), + (uint16_t)desc->type); + return -EINVAL; + } + + stm32_seteptype(epno, setting); + + /* Get the address of the PMA buffer allocated for this endpoint */ + +#warning "REVISIT: Should configure BULK EPs using double buffer feature" + pma = STM32_BUFNO2BUF(privep->bufno); + + /* Get the maxpacket size of the endpoint. */ + + maxpacket = GETUINT16(desc->mxpacketsize); + DEBUGASSERT(maxpacket <= STM32_MAXPACKET_SIZE); + ep->maxpacket = maxpacket; + + /* Get the subset matching the requested direction */ + + if (USB_ISEPIN(desc->addr)) + { + /* The full, logical EP number includes direction */ + + ep->eplog = USB_EPIN(epno); + + /* Set up TX; disable RX */ + + stm32_seteptxaddr(epno, pma); + stm32_seteptxstatus(epno, USB_EPR_STATTX_NAK); + stm32_seteprxstatus(epno, USB_EPR_STATRX_DIS); + } + else + { + /* The full, logical EP number includes direction */ + + ep->eplog = USB_EPOUT(epno); + + /* Set up RX; disable TX */ + + stm32_seteprxaddr(epno, pma); + stm32_seteprxcount(epno, maxpacket); + stm32_seteprxstatus(epno, USB_EPR_STATRX_VALID); + stm32_seteptxstatus(epno, USB_EPR_STATTX_DIS); + } + + stm32_dumpep(epno); + return OK; +} + +/**************************************************************************** + * Name: stm32_epdisable + ****************************************************************************/ + +static int stm32_epdisable(struct usbdev_ep_s *ep) +{ + struct stm32_ep_s *privep = (struct stm32_ep_s *)ep; + irqstate_t flags; + uint8_t epno; + +#ifdef CONFIG_DEBUG_FEATURES + if (!ep) + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); + uerr("ERROR: ep=%p\n", ep); + return -EINVAL; + } +#endif + + epno = USB_EPNO(ep->eplog); + usbtrace(TRACE_EPDISABLE, epno); + + /* Cancel any ongoing activity */ + + flags = enter_critical_section(); + stm32_cancelrequests(privep); + + /* Disable TX; disable RX */ + + stm32_seteprxcount(epno, 0); + stm32_seteprxstatus(epno, USB_EPR_STATRX_DIS); + stm32_seteptxstatus(epno, USB_EPR_STATTX_DIS); + + leave_critical_section(flags); + return OK; +} + +/**************************************************************************** + * Name: stm32_epallocreq + ****************************************************************************/ + +static struct usbdev_req_s *stm32_epallocreq(struct usbdev_ep_s *ep) +{ + struct stm32_req_s *privreq; + +#ifdef CONFIG_DEBUG_FEATURES + if (!ep) + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); + return NULL; + } +#endif + usbtrace(TRACE_EPALLOCREQ, USB_EPNO(ep->eplog)); + + privreq = kmm_malloc(sizeof(struct stm32_req_s)); + if (!privreq) + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_ALLOCFAIL), 0); + return NULL; + } + + memset(privreq, 0, sizeof(struct stm32_req_s)); + return &privreq->req; +} + +/**************************************************************************** + * Name: stm32_epfreereq + ****************************************************************************/ + +static void stm32_epfreereq(struct usbdev_ep_s *ep, struct usbdev_req_s *req) +{ + struct stm32_req_s *privreq = (struct stm32_req_s *)req; + +#ifdef CONFIG_DEBUG_FEATURES + if (!ep || !req) + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); + return; + } +#endif + usbtrace(TRACE_EPFREEREQ, USB_EPNO(ep->eplog)); + + kmm_free(privreq); +} + +/**************************************************************************** + * Name: stm32_epsubmit + ****************************************************************************/ + +static int stm32_epsubmit(struct usbdev_ep_s *ep, struct usbdev_req_s *req) +{ + struct stm32_req_s *privreq = (struct stm32_req_s *)req; + struct stm32_ep_s *privep = (struct stm32_ep_s *)ep; + struct stm32_usbdev_s *priv; + irqstate_t flags; + uint8_t epno; + int ret = OK; + +#ifdef CONFIG_DEBUG_FEATURES + if (!req || !req->callback || !req->buf || !ep) + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); + uerr("ERROR: req=%p callback=%p buf=%p ep=%p\n", + req, req->callback, req->buf, ep); + return -EINVAL; + } +#endif + + usbtrace(TRACE_EPSUBMIT, USB_EPNO(ep->eplog)); + priv = privep->dev; + +#ifdef CONFIG_DEBUG_FEATURES + if (!priv->driver) + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_NOTCONFIGURED), + priv->usbdev.speed); + uerr("ERROR: driver=%p\n", priv->driver); + return -ESHUTDOWN; + } +#endif + + /* Handle the request from the class driver */ + + epno = USB_EPNO(ep->eplog); + req->result = -EINPROGRESS; + req->xfrd = 0; + flags = enter_critical_section(); + + /* If we are stalled, then drop all requests on the floor */ + + if (privep->stalled) + { + stm32_abortrequest(privep, privreq, -EBUSY); + uerr("ERROR: stalled\n"); + ret = -EBUSY; + } + + /* Handle IN (device-to-host) requests. NOTE: If the class device is + * using the bi-directional EP0, then we assume that they intend the EP0 + * IN functionality. + */ + + else if (USB_ISEPIN(ep->eplog) || epno == EP0) + { + /* Add the new request to the request queue for the IN endpoint */ + + stm32_rqenqueue(privep, privreq); + usbtrace(TRACE_INREQQUEUED(epno), req->len); + + /* If the IN endpoint FIFO is available, then transfer the data now */ + + if (!privep->txbusy) + { + priv->txstatus = USB_EPR_STATTX_NAK; + if (epno == EP0) + { + ret = stm32_wrrequest_ep0(priv, privep); + } + else + { + ret = stm32_wrrequest(priv, privep); + } + + /* Set the new TX status */ + + stm32_seteptxstatus(epno, priv->txstatus); + } + } + + /* Handle OUT (host-to-device) requests */ + + else + { + /* Add the new request to the request queue for the OUT endpoint */ + + privep->txnullpkt = 0; + stm32_rqenqueue(privep, privreq); + usbtrace(TRACE_OUTREQQUEUED(epno), req->len); + + /* This there a incoming data pending the availability of a request? */ + + if (priv->rxpending) + { + /* Set STAT_RX bits to '11' in the USB_EPnR, enabling further + * transactions. "While the STAT_RX bits are equal to '10' + * (NAK), any OUT request addressed to that endpoint is NAKed, + * indicating a flow control condition: the USB host will retry + * the transaction until it succeeds." + */ + + priv->rxstatus = USB_EPR_STATRX_VALID; + stm32_seteprxstatus(epno, priv->rxstatus); + + /* Data is no longer pending */ + + priv->rxpending = false; + } + } + + leave_critical_section(flags); + return ret; +} + +/**************************************************************************** + * Name: stm32_epcancel + ****************************************************************************/ + +static int stm32_epcancel(struct usbdev_ep_s *ep, struct usbdev_req_s *req) +{ + struct stm32_ep_s *privep = (struct stm32_ep_s *)ep; + irqstate_t flags; + +#ifdef CONFIG_DEBUG_USB + if (!ep || !req) + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); + return -EINVAL; + } +#endif + usbtrace(TRACE_EPCANCEL, USB_EPNO(ep->eplog)); + + flags = enter_critical_section(); + stm32_cancelrequests(privep); + leave_critical_section(flags); + return OK; +} + +/**************************************************************************** + * Name: stm32_epstall + ****************************************************************************/ + +static int stm32_epstall(struct usbdev_ep_s *ep, bool resume) +{ + struct stm32_ep_s *privep; + struct stm32_usbdev_s *priv; + uint8_t epno; + uint16_t status; + irqstate_t flags; + +#ifdef CONFIG_DEBUG_USB + if (!ep) + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); + return -EINVAL; + } +#endif + + privep = (struct stm32_ep_s *)ep; + priv = (struct stm32_usbdev_s *)privep->dev; + epno = USB_EPNO(ep->eplog); + + /* STALL or RESUME the endpoint */ + + flags = enter_critical_section(); + usbtrace(resume ? TRACE_EPRESUME : TRACE_EPSTALL, USB_EPNO(ep->eplog)); + + /* Get status of the endpoint; stall the request if the endpoint is + * disabled + */ + + if (USB_ISEPIN(ep->eplog)) + { + status = stm32_geteptxstatus(epno); + } + else + { + status = stm32_geteprxstatus(epno); + } + + if (status == 0) + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EPDISABLED), 0); + + if (epno == 0) + { + priv->ep0state = EP0STATE_STALLED; + } + + leave_critical_section(flags); + return -ENODEV; + } + + /* Handle the resume condition */ + + if (resume) + { + /* Resuming a stalled endpoint */ + + usbtrace(TRACE_EPRESUME, epno); + privep->stalled = false; + + if (USB_ISEPIN(ep->eplog)) + { + /* IN endpoint */ + + if (stm32_eptxstalled(epno)) + { + stm32_clrtxdtog(epno); + + /* Restart any queued write requests */ + + priv->txstatus = USB_EPR_STATTX_NAK; + if (epno == EP0) + { + stm32_wrrequest_ep0(priv, privep); + } + else + { + stm32_wrrequest(priv, privep); + } + + /* Set the new TX status */ + + stm32_seteptxstatus(epno, priv->txstatus); + } + } + else + { + /* OUT endpoint */ + + if (stm32_eprxstalled(epno)) + { + if (epno == EP0) + { + /* After clear the STALL, enable the default endpoint + * receiver + */ + + stm32_seteprxcount(epno, ep->maxpacket); + } + else + { + stm32_clrrxdtog(epno); + } + + priv->rxstatus = USB_EPR_STATRX_VALID; + stm32_seteprxstatus(epno, USB_EPR_STATRX_VALID); + } + } + } + + /* Handle the stall condition */ + + else + { + usbtrace(TRACE_EPSTALL, epno); + privep->stalled = true; + + if (USB_ISEPIN(ep->eplog)) + { + /* IN endpoint */ + + priv->txstatus = USB_EPR_STATTX_STALL; + stm32_seteptxstatus(epno, USB_EPR_STATTX_STALL); + } + else + { + /* OUT endpoint */ + + priv->rxstatus = USB_EPR_STATRX_STALL; + stm32_seteprxstatus(epno, USB_EPR_STATRX_STALL); + } + } + + leave_critical_section(flags); + return OK; +} + +/**************************************************************************** + * Device Controller Operations + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_allocep + ****************************************************************************/ + +static struct usbdev_ep_s *stm32_allocep(struct usbdev_s *dev, uint8_t epno, + bool in, uint8_t eptype) +{ + struct stm32_usbdev_s *priv = (struct stm32_usbdev_s *)dev; + struct stm32_ep_s *privep = NULL; + uint8_t epset = STM32_ENDP_ALLSET; + int bufno; + + usbtrace(TRACE_DEVALLOCEP, (uint16_t)epno); +#ifdef CONFIG_DEBUG_USB + if (!dev) + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); + return NULL; + } +#endif + + /* Ignore any direction bits in the logical address */ + + epno = USB_EPNO(epno); + + /* A logical address of 0 means that any endpoint will do */ + + if (epno > 0) + { + /* Otherwise, we will return the endpoint structure only for the + * requested 'logical' endpoint. + * All of the other checks will still be performed. + * + * First, verify that the logical endpoint is in the range supported by + * by the hardware. + */ + + if (epno >= STM32_NENDPOINTS) + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADEPNO), (uint16_t)epno); + return NULL; + } + + /* Convert the logical address to a physical OUT endpoint address and + * remove all of the candidate endpoints from the bitset except for the + * the IN/OUT pair for this logical address. + */ + + epset = STM32_ENDP_BIT(epno); + } + + /* Check if the selected endpoint number is available */ + + privep = stm32_epreserve(priv, epset); + if (!privep) + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EPRESERVE), (uint16_t)epset); + goto errout; + } + + /* Allocate a PMA buffer for this endpoint */ + +#warning "REVISIT: Should configure BULK EPs using double buffer feature" + bufno = stm32_epallocpma(priv); + if (bufno < 0) + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EPBUFFER), 0); + goto errout_with_ep; + } + + privep->bufno = (uint8_t)bufno; + return &privep->ep; + +errout_with_ep: + stm32_epunreserve(priv, privep); +errout: + return NULL; +} + +/**************************************************************************** + * Name: stm32_freeep + ****************************************************************************/ + +static void stm32_freeep(struct usbdev_s *dev, struct usbdev_ep_s *ep) +{ + struct stm32_usbdev_s *priv; + struct stm32_ep_s *privep; + +#ifdef CONFIG_DEBUG_USB + if (!dev || !ep) + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); + return; + } +#endif + priv = (struct stm32_usbdev_s *)dev; + privep = (struct stm32_ep_s *)ep; + usbtrace(TRACE_DEVFREEEP, (uint16_t)USB_EPNO(ep->eplog)); + + if (priv && privep) + { + /* Free the PMA buffer assigned to this endpoint */ + + stm32_epfreepma(priv, privep); + + /* Mark the endpoint as available */ + + stm32_epunreserve(priv, privep); + } +} + +/**************************************************************************** + * Name: stm32_getframe + ****************************************************************************/ + +static int stm32_getframe(struct usbdev_s *dev) +{ + uint16_t fnr; + +#ifdef CONFIG_DEBUG_USB + if (!dev) + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); + return -EINVAL; + } +#endif + + /* Return the last frame number detected by the hardware */ + + fnr = stm32_getreg(STM32_USB_FNR); + usbtrace(TRACE_DEVGETFRAME, fnr); + return (fnr & USB_FNR_FN_MASK); +} + +/**************************************************************************** + * Name: stm32_wakeup + ****************************************************************************/ + +static int stm32_wakeup(struct usbdev_s *dev) +{ + struct stm32_usbdev_s *priv = (struct stm32_usbdev_s *)dev; + irqstate_t flags; + + usbtrace(TRACE_DEVWAKEUP, 0); +#ifdef CONFIG_DEBUG_USB + if (!dev) + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); + return -EINVAL; + } +#endif + + /* Start the resume sequence. The actual resume steps will be driven + * by the ESOF interrupt. + */ + + flags = enter_critical_section(); + stm32_initresume(priv); + priv->rsmstate = RSMSTATE_STARTED; + + /* Disable the SUSP interrupt (until we are fully resumed), disable + * the WKUP interrupt (we are already waking up), and enable the + * ESOF interrupt that will drive the resume operations. Clear any + * pending ESOF interrupt. + */ + + stm32_setimask(priv, USB_CNTR_ESOFM, USB_CNTR_WKUPM | USB_CNTR_SUSPM); + stm32_putreg(~USB_ISTR_ESOF, STM32_USB_ISTR); + leave_critical_section(flags); + return OK; +} + +/**************************************************************************** + * Name: stm32_selfpowered + ****************************************************************************/ + +static int stm32_selfpowered(struct usbdev_s *dev, bool selfpowered) +{ + struct stm32_usbdev_s *priv = (struct stm32_usbdev_s *)dev; + + usbtrace(TRACE_DEVSELFPOWERED, (uint16_t)selfpowered); + +#ifdef CONFIG_DEBUG_USB + if (!dev) + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); + return -ENODEV; + } +#endif + + priv->selfpowered = selfpowered; + return OK; +} + +/**************************************************************************** + * Name: stm32_pullup + ****************************************************************************/ + +static int stm32_pullup(struct usbdev_s *dev, bool enable) +{ + uint32_t regval; + irqstate_t flags; + + usbtrace(TRACE_DEVPULLUP, (uint16_t)enable); + + flags = enter_critical_section(); + regval = stm32_getreg(STM32_USB_BCDR); + if (enable) + { + /* Connect the device by setting the DP pull-up bit in the BCDR + * register. + */ + + regval |= USB_BCDR_DPPU; + } + else + { + /* Disconnect the device by clearing the DP pull-up bit in the BCDR + * register. + */ + + regval &= ~USB_BCDR_DPPU; + } + + stm32_putreg(regval, STM32_USB_BCDR); + leave_critical_section(flags); + return OK; +} + +/**************************************************************************** + * Initialization/Reset + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_reset + ****************************************************************************/ + +static void stm32_reset(struct stm32_usbdev_s *priv) +{ + int epno; + + /* Put the USB controller in reset, disable all interrupts */ + + stm32_putreg(USB_CNTR_FRES, STM32_USB_CNTR); + + /* Tell the class driver that we are disconnected. The class driver + * should then accept any new configurations. + */ + + CLASS_DISCONNECT(priv->driver, &priv->usbdev); + + /* Reset the device state structure */ + + priv->ep0state = EP0STATE_IDLE; + priv->rsmstate = RSMSTATE_IDLE; + priv->rxpending = false; + + /* Reset endpoints */ + + for (epno = 0; epno < STM32_NENDPOINTS; epno++) + { + struct stm32_ep_s *privep = &priv->eplist[epno]; + + /* Cancel any queued requests. Since they are canceled + * with status -ESHUTDOWN, then will not be requeued + * until the configuration is reset. NOTE: This should + * not be necessary... the CLASS_DISCONNECT above should + * result in the class implementation calling stm32_epdisable + * for each of its configured endpoints. + */ + + stm32_cancelrequests(privep); + + /* Reset endpoint status */ + + privep->stalled = false; + privep->halted = false; + privep->txbusy = false; + privep->txnullpkt = false; + } + + /* Re-configure the USB controller in its initial, unconnected state */ + + stm32_hwreset(priv); + priv->usbdev.speed = USB_SPEED_FULL; +} + +/**************************************************************************** + * Name: stm32_hwreset + ****************************************************************************/ + +static void stm32_hwreset(struct stm32_usbdev_s *priv) +{ + /* Put the USB controller into reset, clear all interrupt enables */ + + stm32_putreg(USB_CNTR_FRES, STM32_USB_CNTR); + + /* Disable interrupts (and perhaps take the USB controller out of reset) */ + + priv->imask = 0; + stm32_putreg(priv->imask, STM32_USB_CNTR); + + /* Set the STM32 BTABLE address */ + + stm32_putreg(STM32_BTABLE_ADDRESS & 0xfff8, STM32_USB_BTABLE); + + /* Initialize EP0 */ + + stm32_seteptype(EP0, USB_EPR_EPTYPE_CONTROL); + stm32_seteptxstatus(EP0, USB_EPR_STATTX_NAK); + stm32_seteprxaddr(EP0, STM32_EP0_RXADDR); + stm32_seteprxcount(EP0, STM32_EP0MAXPACKET); + stm32_seteptxaddr(EP0, STM32_EP0_TXADDR); + stm32_clrstatusout(EP0); + stm32_seteprxstatus(EP0, USB_EPR_STATRX_VALID); + + /* Set the device to respond on default address */ + + stm32_setdevaddr(priv, 0); + + /* Clear any pending interrupts */ + + stm32_putreg(0, STM32_USB_ISTR); + + /* Enable interrupts at the USB controller */ + + stm32_setimask(priv, STM32_CNTR_SETUP, + (USB_CNTR_ALLINTS & ~STM32_CNTR_SETUP)); + stm32_dumpep(EP0); +} + +/**************************************************************************** + * Name: stm32_hwsetup + ****************************************************************************/ + +static void stm32_hwsetup(struct stm32_usbdev_s *priv) +{ + int epno; + +#ifdef CONFIG_STM32_STM32G47XX + /* FIXME + * Because stm32g4xxxx_rcc.c does not handle HSI48 for now, + * enable HSI48 clock for USB block here and wait till HSI48 is ready. + */ + + modifyreg32(STM32_RCC_CRRCR, RCC_CRRCR_HSI48ON, RCC_CRRCR_HSI48ON); + while (!(getreg32(STM32_RCC_CRRCR) & RCC_CRRCR_HSI48RDY)) + { + /* nothing to do here */ + } +#endif + + /* Power the USB controller, put the USB controller into reset, disable + * all USB interrupts + */ + + stm32_putreg(USB_CNTR_FRES | USB_CNTR_PDWN, STM32_USB_CNTR); + + /* Disconnect the device / disable the pull-up. We don't want the + * host to enumerate us until the class driver is registered. + */ + + stm32_pullup(&priv->usbdev, false); + + /* Initialize the device state structure. NOTE: many fields + * have the initial value of zero and, hence, are not explicitly + * initialized here. + */ + + memset(priv, 0, sizeof(struct stm32_usbdev_s)); + priv->usbdev.ops = &g_devops; + priv->usbdev.ep0 = &priv->eplist[EP0].ep; + priv->epavail = STM32_ENDP_ALLSET & ~STM32_ENDP_BIT(EP0); + priv->bufavail = STM32_BUFFER_ALLSET & ~STM32_BUFFER_EP0; + + /* Initialize the endpoint list */ + + for (epno = 0; epno < STM32_NENDPOINTS; epno++) + { + /* Set endpoint operations, reference to driver structure (not + * really necessary because there is only one controller), and + * the (physical) endpoint number which is just the index to the + * endpoint. + */ + + priv->eplist[epno].ep.ops = &g_epops; + priv->eplist[epno].dev = priv; + priv->eplist[epno].ep.eplog = epno; + + /* We will use a fixed maxpacket size for all endpoints (perhaps + * ISOC endpoints could have larger maxpacket???). A smaller + * packet size can be selected when the endpoint is configured. + */ + + priv->eplist[epno].ep.maxpacket = STM32_MAXPACKET_SIZE; + } + + /* Select a smaller endpoint size for EP0 */ + +#if STM32_EP0MAXPACKET < STM32_MAXPACKET_SIZE + priv->eplist[EP0].ep.maxpacket = STM32_EP0MAXPACKET; +#endif + + /* Configure the USB controller. USB uses the following GPIO pins: + * + * PA9 - VBUS + * PA10 - ID + * PA11 - DM + * PA12 - DP + * + * "As soon as the USB is enabled, these pins [DM and DP] are connected to + * the USB internal transceiver automatically." + */ + + /* Power up the USB controller, holding it in reset. There is a delay of + * about 1uS after applying power before the USB will behave predictably. + * A 5MS delay is more than enough. NOTE that we leave the USB controller + * in the reset state; the hardware will not be initialized until the + * class driver has been bound. + */ + + stm32_putreg(USB_CNTR_FRES, STM32_USB_CNTR); + up_mdelay(5); +} + +/**************************************************************************** + * Name: stm32_hwshutdown + ****************************************************************************/ + +static void stm32_hwshutdown(struct stm32_usbdev_s *priv) +{ + priv->usbdev.speed = USB_SPEED_UNKNOWN; + + /* Disable all interrupts and force the USB controller into reset */ + + stm32_putreg(USB_CNTR_FRES, STM32_USB_CNTR); + + /* Clear any pending interrupts */ + + stm32_putreg(0, STM32_USB_ISTR); + + /* Disconnect the device / disable the pull-up */ + + stm32_pullup(&priv->usbdev, false); + + /* Power down the USB controller */ + + stm32_putreg(USB_CNTR_FRES | USB_CNTR_PDWN, STM32_USB_CNTR); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: arm_usbinitialize + * Description: + * Initialize the USB driver + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void arm_usbinitialize(void) +{ + /* For now there is only one USB controller, but we will always refer to + * it using a pointer to make any future ports to multiple USB controllers + * easier. + */ + + struct stm32_usbdev_s *priv = &g_usbdev; + + usbtrace(TRACE_DEVINIT, 0); + stm32_checksetup(); + + /* Power up the USB controller, but leave it in the reset state */ + + stm32_hwsetup(priv); + + /* Remap the USB interrupt as needed + * (Only supported by the STM32 F3 family) + */ + + /* Attach USB controller interrupt handlers. The hardware will not be + * initialized and interrupts will not be enabled until the class device + * driver is bound. Getting the IRQs here only makes sure that we have + * them when we need them later. + */ + + if (irq_attach(STM32_IRQ_USBHP, stm32_hpinterrupt, NULL) != 0) + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_IRQREGISTRATION), + (uint16_t)STM32_IRQ_USBHP); + goto errout; + } + + if (irq_attach(STM32_IRQ_USBLP, stm32_lpinterrupt, NULL) != 0) + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_IRQREGISTRATION), + (uint16_t)STM32_IRQ_USBLP); + goto errout; + } + + return; + +errout: + arm_usbuninitialize(); +} + +/**************************************************************************** + * Name: arm_usbuninitialize + * Description: + * Initialize the USB driver + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void arm_usbuninitialize(void) +{ + /* For now there is only one USB controller, but we will always refer to + * it using a pointer to make any future ports to multiple USB controllers + * easier. + */ + + struct stm32_usbdev_s *priv = &g_usbdev; + irqstate_t flags; + + flags = enter_critical_section(); + usbtrace(TRACE_DEVUNINIT, 0); + + /* Disable and detach the USB IRQs */ + + up_disable_irq(STM32_IRQ_USBHP); + up_disable_irq(STM32_IRQ_USBLP); + irq_detach(STM32_IRQ_USBHP); + irq_detach(STM32_IRQ_USBLP); + + if (priv->driver) + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_DRIVERREGISTERED), 0); + usbdev_unregister(priv->driver); + } + + /* Put the hardware in an inactive state */ + + stm32_hwshutdown(priv); + leave_critical_section(flags); +} + +/**************************************************************************** + * Name: usbdev_register + * + * Description: + * Register a USB device class driver. The class driver's bind() method + * will be called to bind it to a USB device driver. + * + ****************************************************************************/ + +int usbdev_register(struct usbdevclass_driver_s *driver) +{ + /* For now there is only one USB controller, but we will always refer to + * it using a pointer to make any future ports to multiple USB controllers + * easier. + */ + + struct stm32_usbdev_s *priv = &g_usbdev; + int ret; + + usbtrace(TRACE_DEVREGISTER, 0); + +#ifdef CONFIG_DEBUG_USB + if (!driver || !driver->ops->bind || !driver->ops->unbind || + !driver->ops->disconnect || !driver->ops->setup) + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); + return -EINVAL; + } + + if (priv->driver) + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_DRIVER), 0); + return -EBUSY; + } +#endif + + /* First hook up the driver */ + + priv->driver = driver; + + /* Then bind the class driver */ + + ret = CLASS_BIND(driver, &priv->usbdev); + if (ret) + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BINDFAILED), (uint16_t) - ret); + } + else + { + /* Setup the USB controller -- enabling interrupts at the USB + * controller + */ + + stm32_hwreset(priv); + + /* Enable USB controller interrupts at the NVIC */ + + up_enable_irq(STM32_IRQ_USBHP); + up_enable_irq(STM32_IRQ_USBLP); + + /* Enable pull-up to connect the device. The host should enumerate us + * some time after this + */ + + stm32_pullup(&priv->usbdev, true); + priv->usbdev.speed = USB_SPEED_FULL; + } + + return ret; +} + +/**************************************************************************** + * Name: usbdev_unregister + * + * Description: + * Un-register usbdev class driver. If the USB device is connected to a + * USB host, it will first disconnect(). The driver is also requested to + * unbind() and clean up any device state, before this procedure finally + * returns. + * + ****************************************************************************/ + +int usbdev_unregister(struct usbdevclass_driver_s *driver) +{ + /* For now there is only one USB controller, but we will always refer to + * it using a pointer to make any future ports to multiple USB controllers + * easier. + */ + + struct stm32_usbdev_s *priv = &g_usbdev; + irqstate_t flags; + + usbtrace(TRACE_DEVUNREGISTER, 0); + +#ifdef CONFIG_DEBUG_USB + if (driver != priv->driver) + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); + return -EINVAL; + } +#endif + + /* Reset the hardware and cancel all requests. All requests must be + * canceled while the class driver is still bound. + */ + + flags = enter_critical_section(); + stm32_reset(priv); + + /* Unbind the class driver */ + + CLASS_UNBIND(driver, &priv->usbdev); + + /* Disable USB controller interrupts (but keep them attached) */ + + up_disable_irq(STM32_IRQ_USBHP); + up_disable_irq(STM32_IRQ_USBLP); + + /* Put the hardware in an inactive state. Then bring the hardware back up + * in the reset state (this is probably not necessary, the stm32_reset() + * call above was probably sufficient). + */ + + stm32_hwshutdown(priv); + stm32_hwsetup(priv); + + /* Unhook the driver */ + + priv->driver = NULL; + leave_critical_section(flags); + return OK; +} + +#endif /* CONFIG_STM32_USBFS */ diff --git a/arch/arm/src/common/stm32/stm32_usbfs_m3m4_v1.h b/arch/arm/src/common/stm32/stm32_usbfs_m3m4_v1.h new file mode 100644 index 0000000000000..8a5b8adf76287 --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_usbfs_m3m4_v1.h @@ -0,0 +1,79 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_usbfs_m3m4_v1.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_USBFS_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_USBFS_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include + +#include "chip.h" +#include "hardware/stm32_usbfs.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Number of endpoints */ + +#define STM32_NENDPOINTS (8) + +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Name: stm32_usbsuspend + * + * Description: + * Board logic must provide the stm32_usbsuspend logic if the USBDEV driver + * is used. This function is called whenever the USB enters or leaves + * suspend mode. This is an opportunity for the board logic to shutdown + * clocks, power, etc. while the USB is suspended. + * + ****************************************************************************/ + +void stm32_usbsuspend(struct usbdev_s *dev, bool resume); + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_USBFS_H */ diff --git a/arch/arm/src/common/stm32/stm32_usbhost.h b/arch/arm/src/common/stm32/stm32_usbhost.h new file mode 100644 index 0000000000000..c659a23a25b7e --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_usbhost.h @@ -0,0 +1,38 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_usbhost.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_COMPAT_STM32USBHOST_H +#define __ARCH_ARM_SRC_COMMON_COMPAT_STM32USBHOST_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#if defined(CONFIG_STM32_COMMON_LEGACY) +# include "stm32_usbhost_m3m4_v1.h" +#else +# error "Unsupported STM32 stm32_usbhost" +#endif + +#endif /* __ARCH_ARM_SRC_COMMON_COMPAT_STM32USBHOST_H */ diff --git a/arch/arm/src/common/stm32/stm32_usbhost_m3m4_v1.c b/arch/arm/src/common/stm32/stm32_usbhost_m3m4_v1.c new file mode 100644 index 0000000000000..d6241c81881a8 --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_usbhost_m3m4_v1.c @@ -0,0 +1,417 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_usbhost_m3m4_v1.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include "stm32_usbhost_m3m4_v1.h" + +#ifdef HAVE_USBHOST_TRACE + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define TR_FMT1 false +#define TR_FMT2 true + +#define TRENTRY(id,fmt1,string) {string} + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +struct stm32_usbhost_trace_s +{ +#if 0 + uint16_t id; + bool fmt2; +#endif + const char *string; +}; + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static const struct stm32_usbhost_trace_s g_trace1[TRACE1_NSTRINGS] = +{ +#ifdef CONFIG_STM32_OTGFS + + TRENTRY(OTGFS_TRACE1_DEVDISCONN, + TR_FMT1, + "OTGFS ERROR: Host Port %d. Device disconnected\n"), + TRENTRY(OTGFS_TRACE1_IRQATTACH, + TR_FMT1, + "OTGFS ERROR: Failed to attach IRQ\n"), + TRENTRY(OTGFS_TRACE1_TRNSFRFAILED, + TR_FMT1, + "OTGFS ERROR: Transfer Failed. ret=%d\n"), + TRENTRY(OTGFS_TRACE1_SENDSETUP, + TR_FMT1, + "OTGFS ERROR: ctrl_sendsetup() failed with: %d\n"), + TRENTRY(OTGFS_TRACE1_SENDDATA, + TR_FMT1, + "OTGFS ERROR: ctrl_senddata() failed with: %d\n"), + TRENTRY(OTGFS_TRACE1_RECVDATA, + TR_FMT1, + "OTGFS ERROR: ctrl_recvdata() failed with: %d\n"), + +# ifdef HAVE_USBHOST_TRACE_VERBOSE + + TRENTRY(OTGFS_VTRACE1_CONNECTED, + TR_FMT1, + "OTGFS Host Port %d connected.\n"), + TRENTRY(OTGFS_VTRACE1_DISCONNECTED, + TR_FMT1, + "OTGFS Host Port %d disconnected.\n"), + TRENTRY(OTGFS_VTRACE1_GINT, + TR_FMT1, + "OTGFS Handling Interrupt. Entry Point.\n"), + TRENTRY(OTGFS_VTRACE1_GINT_SOF, + TR_FMT1, + "OTGFS Handle the start of frame interrupt.\n"), + TRENTRY(OTGFS_VTRACE1_GINT_RXFLVL, + TR_FMT1, + "OTGFS Handle the RxFIFO non-empty interrupt.\n"), + TRENTRY(OTGFS_VTRACE1_GINT_NPTXFE, + TR_FMT1, + "OTGFS Handle the non-periodic TxFIFO empty interrupt.\n"), + TRENTRY(OTGFS_VTRACE1_GINT_PTXFE, + TR_FMT1, + "OTGFS Handle the periodic TxFIFO empty interrupt.\n"), + TRENTRY(OTGFS_VTRACE1_GINT_HC, + TR_FMT1, + "OTGFS Handle the host channels interrupt.\n"), + TRENTRY(OTGFS_VTRACE1_GINT_HPRT, + TR_FMT1, + "OTGFS Handle the host port interrupt.\n"), + TRENTRY(OTGFS_VTRACE1_GINT_HPRT_POCCHNG, + TR_FMT1, + "OTGFS HPRT: Port Over-Current Change.\n"), + TRENTRY(OTGFS_VTRACE1_GINT_HPRT_PCDET, + TR_FMT1, + "OTGFS HPRT: Port Connect Detect.\n"), + TRENTRY(OTGFS_VTRACE1_GINT_HPRT_PENCHNG, + TR_FMT1, + "OTGFS HPRT: Port Enable Changed.\n"), + TRENTRY(OTGFS_VTRACE1_GINT_HPRT_LSDEV, + TR_FMT1, + "OTGFS HPRT: Low Speed Device Connected.\n"), + TRENTRY(OTGFS_VTRACE1_GINT_HPRT_FSDEV, + TR_FMT1, + "OTGFS HPRT: Full Speed Device Connected.\n"), + TRENTRY(OTGFS_VTRACE1_GINT_HPRT_LSFSSW, + TR_FMT1, + "OTGFS HPRT: Host Switch: LS -> FS.\n"), + TRENTRY(OTGFS_VTRACE1_GINT_HPRT_FSLSSW, + TR_FMT1, + "OTGFS HPRT: Host Switch: FS -> LS.\n"), + TRENTRY(OTGFS_VTRACE1_GINT_DISC, + TR_FMT1, + "OTGFS Handle the disconnect detected interrupt.\n"), + TRENTRY(OTGFS_VTRACE1_GINT_IPXFR, + TR_FMT1, + "OTGFS Handle the incomplete periodic transfer.\n"), + +# endif +#endif + +#ifdef CONFIG_STM32_OTGHS + + TRENTRY(OTGHS_TRACE1_DEVDISCONN, + TR_FMT1, + "OTGHS ERROR: Host Port %d. Device disconnected\n"), + TRENTRY(OTGHS_TRACE1_IRQATTACH, + TR_FMT1, + "OTGHS ERROR: Failed to attach IRQ\n"), + TRENTRY(OTGHS_TRACE1_TRNSFRFAILED, + TR_FMT1, + "OTGHS ERROR: Transfer Failed. ret=%d\n"), + TRENTRY(OTGHS_TRACE1_SENDSETUP, + TR_FMT1, + "OTGHS ERROR: ctrl_sendsetup() failed with: %d\n"), + TRENTRY(OTGHS_TRACE1_SENDDATA, + TR_FMT1, + "OTGHS ERROR: ctrl_senddata() failed with: %d\n"), + TRENTRY(OTGHS_TRACE1_RECVDATA, + TR_FMT1, + "OTGHS ERROR: ctrl_recvdata() failed with: %d\n"), + +# ifdef HAVE_USBHOST_TRACE_VERBOSE + + TRENTRY(OTGHS_VTRACE1_CONNECTED, + TR_FMT1, + "OTGHS Host Port %d connected.\n"), + TRENTRY(OTGHS_VTRACE1_DISCONNECTED, + TR_FMT1, + "OTGHS Host Port %d disconnected.\n"), + TRENTRY(OTGHS_VTRACE1_GINT, + TR_FMT1, + "OTGHS Handling Interrupt. Entry Point.\n"), + TRENTRY(OTGHS_VTRACE1_GINT_SOF, + TR_FMT1, + "OTGHS Handle the start of frame interrupt.\n"), + TRENTRY(OTGHS_VTRACE1_GINT_RXFLVL, + TR_FMT1, + "OTGHS Handle the RxFIFO non-empty interrupt.\n"), + TRENTRY(OTGHS_VTRACE1_GINT_NPTXFE, + TR_FMT1, + "OTGHS Handle the non-periodic TxFIFO empty interrupt.\n"), + TRENTRY(OTGHS_VTRACE1_GINT_PTXFE, + TR_FMT1, + "OTGHS Handle the periodic TxFIFO empty interrupt.\n"), + TRENTRY(OTGHS_VTRACE1_GINT_HC, + TR_FMT1, + "OTGHS Handle the host channels interrupt.\n"), + TRENTRY(OTGHS_VTRACE1_GINT_HPRT, + TR_FMT1, + "OTGHS Handle the host port interrupt.\n"), + TRENTRY(OTGHS_VTRACE1_GINT_HPRT_POCCHNG, + TR_FMT1, + "OTGHS HPRT: Port Over-Current Change.\n"), + TRENTRY(OTGHS_VTRACE1_GINT_HPRT_PCDET, + TR_FMT1, + "OTGHS HPRT: Port Connect Detect.\n"), + TRENTRY(OTGHS_VTRACE1_GINT_HPRT_PENCHNG, + TR_FMT1, + "OTGHS HPRT: Port Enable Changed.\n"), + TRENTRY(OTGHS_VTRACE1_GINT_HPRT_LSDEV, + TR_FMT1, + "OTGHS HPRT: Low Speed Device Connected.\n"), + TRENTRY(OTGHS_VTRACE1_GINT_HPRT_HSDEV, + TR_FMT1, + "OTGHS HPRT: Full Speed Device Connected.\n"), + TRENTRY(OTGHS_VTRACE1_GINT_HPRT_LSHSSW, + TR_FMT1, + "OTGHS HPRT: Host Switch: LS -> HS.\n"), + TRENTRY(OTGHS_VTRACE1_GINT_HPRT_HSLSSW, + TR_FMT1, + "OTGHS HPRT: Host Switch: HS -> LS.\n"), + TRENTRY(OTGHS_VTRACE1_GINT_DISC, + TR_FMT1, + "OTGHS Handle the disconnect detected interrupt.\n"), + TRENTRY(OTGHS_VTRACE1_GINT_IPXFR, + TR_FMT1, + "OTGHS Handle the incomplete periodic transfer.\n"), +# endif +#endif +}; + +static const struct stm32_usbhost_trace_s g_trace2[TRACE2_NSTRINGS] = +{ +#ifdef CONFIG_STM32_OTGFS + + TRENTRY(OTGFS_TRACE2_CLIP, + TR_FMT2, + "OTGFS CLIP: chidx: %d buflen: %d\n"), + +# ifdef HAVE_USBHOST_TRACE_VERBOSE + TRENTRY(OTGFS_VTRACE2_CHANWAKEUP_IN, + TR_FMT2, + "OTGFS EP%d(IN) wake up with result: %d\n"), + TRENTRY(OTGFS_VTRACE2_CHANWAKEUP_OUT, + TR_FMT2, + "OTGFS EP%d(OUT) wake up with result: %d\n"), + TRENTRY(OTGFS_VTRACE2_CTRLIN, + TR_FMT2, + "OTGFS CTRL_IN type: %02x req: %02x\n"), + TRENTRY(OTGFS_VTRACE2_CTRLOUT, + TR_FMT2, + "OTGFS CTRL_OUT type: %02x req: %02x\n"), + TRENTRY(OTGFS_VTRACE2_INTRIN, + TR_FMT2, + "OTGFS INTR_IN chidx: %02x len: %02x\n"), + TRENTRY(OTGFS_VTRACE2_INTROUT, + TR_FMT2, + "OTGFS INTR_OUT chidx: %02x len: %02x\n"), + TRENTRY(OTGFS_VTRACE2_BULKIN, + TR_FMT2, + "OTGFS BULK_IN chidx: %02x len: %02x\n"), + TRENTRY(OTGFS_VTRACE2_BULKOUT, + TR_FMT2, + "OTGFS BULK_OUT chidx: %02x len: %02x\n"), + TRENTRY(OTGFS_VTRACE2_ISOCIN, + TR_FMT2, + "OTGFS ISOC_IN chidx: %02x len: %04d\n"), + TRENTRY(OTGFS_VTRACE2_ISOCOUT, + TR_FMT2, + "OTGFS ISOC_OUT chidx: %02x req: %02x\n"), + TRENTRY(OTGFS_VTRACE2_STARTTRANSFER, + TR_FMT2, + "OTGFS Transfer chidx: %d buflen: %d\n"), + TRENTRY(OTGFS_VTRACE2_CHANCONF_CTRL_IN, + TR_FMT2, + "OTGFS Channel configured. chidx: %d: (EP%d,IN ,CTRL)\n"), + TRENTRY(OTGFS_VTRACE2_CHANCONF_CTRL_OUT, + TR_FMT2, + "OTGFS Channel configured. chidx: %d: (EP%d,OUT,CTRL)\n"), + TRENTRY(OTGFS_VTRACE2_CHANCONF_INTR_IN, + TR_FMT2, + "OTGFS Channel configured. chidx: %d: (EP%d,IN ,INTR)\n"), + TRENTRY(OTGFS_VTRACE2_CHANCONF_INTR_OUT, + TR_FMT2, + "OTGFS Channel configured. chidx: %d: (EP%d,OUT,INTR)\n"), + TRENTRY(OTGFS_VTRACE2_CHANCONF_BULK_IN, + TR_FMT2, + "OTGFS Channel configured. chidx: %d: (EP%d,IN ,BULK)\n"), + TRENTRY(OTGFS_VTRACE2_CHANCONF_BULK_OUT, + TR_FMT2, + "OTGFS Channel configured. chidx: %d: (EP%d,OUT,BULK)\n"), + TRENTRY(OTGFS_VTRACE2_CHANCONF_ISOC_IN, + TR_FMT2, + "OTGFS Channel configured. chidx: %d: (EP%d,IN ,ISOC)\n"), + TRENTRY(OTGFS_VTRACE2_CHANCONF_ISOC_OUT, + TR_FMT2, + "OTGFS Channel configured. chidx: %d: (EP%d,OUT,ISOC)\n"), + TRENTRY(OTGFS_VTRACE2_CHANHALT, + TR_FMT2, + "OTGFS Channel halted. chidx: %d, reason: %d\n"), + +# endif +#endif +#ifdef CONFIG_STM32_OTGHS + + TRENTRY(OTGHS_TRACE2_CLIP, + TR_FMT2, + "OTGHS CLIP: chidx: %d buflen: %d\n"), + +# ifdef HAVE_USBHOST_TRACE_VERBOSE + + TRENTRY(OTGHS_VTRACE2_CHANWAKEUP_IN, + TR_FMT2, + "OTGHS EP%d(IN) wake up with result: %d\n"), + TRENTRY(OTGHS_VTRACE2_CHANWAKEUP_OUT, + TR_FMT2, + "OTGHS EP%d(OUT) wake up with result: %d\n"), + TRENTRY(OTGHS_VTRACE2_CTRLIN, + TR_FMT2, + "OTGHS CTRL_IN type: %02x req: %02x\n"), + TRENTRY(OTGHS_VTRACE2_CTRLOUT, + TR_FMT2, + "OTGHS CTRL_OUT type: %02x req: %02x\n"), + TRENTRY(OTGHS_VTRACE2_INTRIN, + TR_FMT2, + "OTGHS INTR_IN chidx: %02x len: %02x\n"), + TRENTRY(OTGHS_VTRACE2_INTROUT, + TR_FMT2, + "OTGHS INTR_OUT chidx: %02x len: %02x\n"), + TRENTRY(OTGHS_VTRACE2_BULKIN, + TR_FMT2, + "OTGHS BULK_IN chidx: %02x len: %02x\n"), + TRENTRY(OTGHS_VTRACE2_BULKOUT, + TR_FMT2, + "OTGHS BULK_OUT chidx: %02x len: %02x\n"), + TRENTRY(OTGHS_VTRACE2_ISOCIN, + TR_FMT2, + "OTGHS ISOC_IN chidx: %02x len: %04d\n"), + TRENTRY(OTGHS_VTRACE2_ISOCOUT, + TR_FMT2, + "OTGHS ISOC_OUT chidx: %02x req: %02x\n"), + TRENTRY(OTGHS_VTRACE2_STARTTRANSFER, + TR_FMT2, + "OTGHS Transfer chidx: %d buflen: %d\n"), + TRENTRY(OTGHS_VTRACE2_CHANCONF_CTRL_IN, + TR_FMT2, + "OTGHS Channel configured. chidx: %d: (EP%d,IN ,CTRL)\n"), + TRENTRY(OTGHS_VTRACE2_CHANCONF_CTRL_OUT, + TR_FMT2, + "OTGHS Channel configured. chidx: %d: (EP%d,OUT,CTRL)\n"), + TRENTRY(OTGHS_VTRACE2_CHANCONF_INTR_IN, + TR_FMT2, + "OTGHS Channel configured. chidx: %d: (EP%d,IN ,INTR)\n"), + TRENTRY(OTGHS_VTRACE2_CHANCONF_INTR_OUT, + TR_FMT2, + "OTGHS Channel configured. chidx: %d: (EP%d,OUT,INTR)\n"), + TRENTRY(OTGHS_VTRACE2_CHANCONF_BULK_IN, + TR_FMT2, + "OTGHS Channel configured. chidx: %d: (EP%d,IN ,BULK)\n"), + TRENTRY(OTGHS_VTRACE2_CHANCONF_BULK_OUT, + TR_FMT2, + "OTGHS Channel configured. chidx: %d: (EP%d,OUT,BULK)\n"), + TRENTRY(OTGHS_VTRACE2_CHANCONF_ISOC_IN, + TR_FMT2, + "OTGHS Channel configured. chidx: %d: (EP%d,IN ,ISOC)\n"), + TRENTRY(OTGHS_VTRACE2_CHANCONF_ISOC_OUT, + TR_FMT2, + "OTGHS Channel configured. chidx: %d: (EP%d,OUT,ISOC)\n"), + TRENTRY(OTGHS_VTRACE2_CHANHALT, + TR_FMT2, + "OTGHS Channel halted. chidx: %d, reason: %d\n"), + +# endif +#endif +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: usbhost_trformat1 and usbhost_trformat2 + * + * Description: + * This interface must be provided by platform specific logic that knows + * the HCDs encoding of USB trace data. + * + * Given an 9-bit index, return a format string suitable for use with, say, + * printf. The returned format is expected to handle two unsigned integer + * values. + * + ****************************************************************************/ + +const char *usbhost_trformat1(uint16_t id) +{ + int ndx = TRACE1_INDEX(id); + + if (ndx < TRACE1_NSTRINGS) + { + return g_trace1[ndx].string; + } + + return NULL; +} + +const char *usbhost_trformat2(uint16_t id) +{ + int ndx = TRACE2_INDEX(id); + + if (ndx < TRACE2_NSTRINGS) + { + return g_trace2[ndx].string; + } + + return NULL; +} + +#endif /* HAVE_USBHOST_TRACE */ diff --git a/arch/arm/src/common/stm32/stm32_usbhost_m3m4_v1.h b/arch/arm/src/common/stm32/stm32_usbhost_m3m4_v1.h new file mode 100644 index 0000000000000..867260f81c8d1 --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_usbhost_m3m4_v1.h @@ -0,0 +1,283 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_usbhost_m3m4_v1.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_USBHOST_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_USBHOST_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include +#include + +#include "chip.h" +#include "hardware/stm32fxxxxx_otgfs.h" +#include "hardware/stm32_otghs.h" + +#if (defined(CONFIG_STM32_OTGFS) || defined(CONFIG_STM32_OTGHS)) && \ + defined(CONFIG_STM32_USBHOST) + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +#ifdef HAVE_USBHOST_TRACE +enum usbhost_trace1codes_e +{ + __TRACE1_BASEVALUE = 0, /* This will force the first value to be 1 */ + +#ifdef CONFIG_STM32_OTGFS + + OTGFS_TRACE1_DEVDISCONN, /* OTGFS ERROR: Host Port Device disconnected */ + OTGFS_TRACE1_IRQATTACH, /* OTGFS ERROR: Failed to attach IRQ */ + OTGFS_TRACE1_TRNSFRFAILED, /* OTGFS ERROR: Host Port Transfer Failed */ + OTGFS_TRACE1_SENDSETUP, /* OTGFS ERROR: sendsetup() failed with: */ + OTGFS_TRACE1_SENDDATA, /* OTGFS ERROR: senddata() failed with: */ + OTGFS_TRACE1_RECVDATA, /* OTGFS ERROR: recvdata() failed with: */ + +# ifdef HAVE_USBHOST_TRACE_VERBOSE + + OTGFS_VTRACE1_CONNECTED, /* OTGFS Host Port connected */ + OTGFS_VTRACE1_DISCONNECTED, /* OTGFS Host Port disconnected */ + OTGFS_VTRACE1_GINT, /* OTGFS Handling Interrupt. Entry Point */ + OTGFS_VTRACE1_GINT_SOF, /* OTGFS Handle the start of frame interrupt */ + OTGFS_VTRACE1_GINT_RXFLVL, /* OTGFS Handle the RxFIFO non-empty interrupt */ + OTGFS_VTRACE1_GINT_NPTXFE, /* OTGFS Handle the non-periodic TxFIFO empty interrupt */ + OTGFS_VTRACE1_GINT_PTXFE, /* OTGFS Handle the periodic TxFIFO empty interrupt */ + OTGFS_VTRACE1_GINT_HC, /* OTGFS Handle the host channels interrupt */ + OTGFS_VTRACE1_GINT_HPRT, /* OTGFS Handle the host port interrupt */ + OTGFS_VTRACE1_GINT_HPRT_POCCHNG, /* OTGFS HPRT: Port Over-Current Change */ + OTGFS_VTRACE1_GINT_HPRT_PCDET, /* OTGFS HPRT: Port Connect Detect */ + OTGFS_VTRACE1_GINT_HPRT_PENCHNG, /* OTGFS HPRT: Port Enable Changed */ + OTGFS_VTRACE1_GINT_HPRT_LSDEV, /* OTGFS HPRT: Low Speed Device Connected */ + OTGFS_VTRACE1_GINT_HPRT_FSDEV, /* OTGFS HPRT: Full Speed Device Connected */ + OTGFS_VTRACE1_GINT_HPRT_LSFSSW, /* OTGFS HPRT: Host Switch: LS -> FS */ + OTGFS_VTRACE1_GINT_HPRT_FSLSSW, /* OTGFS HPRT: Host Switch: FS -> LS */ + OTGFS_VTRACE1_GINT_DISC, /* OTGFS Handle the disconnect detected interrupt */ + OTGFS_VTRACE1_GINT_IPXFR, /* OTGFS Handle the incomplete periodic transfer */ + +# endif +#endif + +#ifdef CONFIG_STM32_OTGHS + + OTGHS_TRACE1_DEVDISCONN, /* OTGHS ERROR: Host Port Device disconnected */ + OTGHS_TRACE1_IRQATTACH, /* OTGHS ERROR: Failed to attach IRQ */ + OTGHS_TRACE1_TRNSFRFAILED, /* OTGHS ERROR: Host Port Transfer Failed */ + OTGHS_TRACE1_SENDSETUP, /* OTGHS ERROR: sendsetup() failed with: */ + OTGHS_TRACE1_SENDDATA, /* OTGHS ERROR: senddata() failed with: */ + OTGHS_TRACE1_RECVDATA, /* OTGHS ERROR: recvdata() failed with: */ + +# ifdef HAVE_USBHOST_TRACE_VERBOSE + + OTGHS_VTRACE1_CONNECTED, /* OTGHS Host Port connected */ + OTGHS_VTRACE1_DISCONNECTED, /* OTGHS Host Port disconnected */ + OTGHS_VTRACE1_GINT, /* OTGHS Handling Interrupt. Entry Point */ + OTGHS_VTRACE1_GINT_SOF, /* OTGHS Handle the start of frame interrupt */ + OTGHS_VTRACE1_GINT_RXFLVL, /* OTGHS Handle the RxFIFO non-empty interrupt */ + OTGHS_VTRACE1_GINT_NPTXFE, /* OTGHS Handle the non-periodic TxFIFO empty interrupt */ + OTGHS_VTRACE1_GINT_PTXFE, /* OTGHS Handle the periodic TxFIFO empty interrupt */ + OTGHS_VTRACE1_GINT_HC, /* OTGHS Handle the host channels interrupt */ + OTGHS_VTRACE1_GINT_HPRT, /* OTGHS Handle the host port interrupt */ + OTGHS_VTRACE1_GINT_HPRT_POCCHNG, /* OTGHS HPRT: Port Over-Current Change */ + OTGHS_VTRACE1_GINT_HPRT_PCDET, /* OTGHS HPRT: Port Connect Detect */ + OTGHS_VTRACE1_GINT_HPRT_PENCHNG, /* OTGHS HPRT: Port Enable Changed */ + OTGHS_VTRACE1_GINT_HPRT_LSDEV, /* OTGHS HPRT: Low Speed Device Connected */ + OTGHS_VTRACE1_GINT_HPRT_FSDEV, /* OTGHS HPRT: Full Speed Device Connected */ + OTGHS_VTRACE1_GINT_HPRT_LSFSSW, /* OTGHS HPRT: Host Switch: LS -> FS */ + OTGHS_VTRACE1_GINT_HPRT_FSLSSW, /* OTGHS HPRT: Host Switch: FS -> LS */ + OTGHS_VTRACE1_GINT_DISC, /* OTGHS Handle the disconnect detected interrupt */ + OTGHS_VTRACE1_GINT_IPXFR, /* OTGHS Handle the incomplete periodic transfer */ + +# endif +#endif + + __TRACE1_NSTRINGS, /* Separates the format 1 from the format 2 strings */ + +#ifdef CONFIG_STM32_OTGFS + + OTGFS_TRACE2_CLIP, /* OTGFS CLIP: chidx: buflen: */ + +# ifdef HAVE_USBHOST_TRACE_VERBOSE + + OTGFS_VTRACE2_CHANWAKEUP_IN, /* OTGFS IN Channel wake up with result */ + OTGFS_VTRACE2_CHANWAKEUP_OUT, /* OTGFS OUT Channel wake up with result */ + OTGFS_VTRACE2_CTRLIN, /* OTGFS CTRLIN */ + OTGFS_VTRACE2_CTRLOUT, /* OTGFS CTRLOUT */ + OTGFS_VTRACE2_INTRIN, /* OTGFS INTRIN */ + OTGFS_VTRACE2_INTROUT, /* OTGFS INTROUT */ + OTGFS_VTRACE2_BULKIN, /* OTGFS BULKIN */ + OTGFS_VTRACE2_BULKOUT, /* OTGFS BULKOUT */ + OTGFS_VTRACE2_ISOCIN, /* OTGFS ISOCIN */ + OTGFS_VTRACE2_ISOCOUT, /* OTGFS ISOCOUT */ + OTGFS_VTRACE2_STARTTRANSFER, /* OTGFS EP buflen */ + OTGFS_VTRACE2_CHANCONF_CTRL_IN, + OTGFS_VTRACE2_CHANCONF_CTRL_OUT, + OTGFS_VTRACE2_CHANCONF_INTR_IN, + OTGFS_VTRACE2_CHANCONF_INTR_OUT, + OTGFS_VTRACE2_CHANCONF_BULK_IN, + OTGFS_VTRACE2_CHANCONF_BULK_OUT, + OTGFS_VTRACE2_CHANCONF_ISOC_IN, + OTGFS_VTRACE2_CHANCONF_ISOC_OUT, + OTGFS_VTRACE2_CHANHALT, /* Channel halted. chidx: , reason: */ + +# endif +#endif + +#ifdef CONFIG_STM32_OTGHS + + OTGHS_TRACE2_CLIP, /* OTGHS CLIP: chidx: buflen: */ + +# ifdef HAVE_USBHOST_TRACE_VERBOSE + + OTGHS_VTRACE2_CHANWAKEUP_IN, /* OTGHS IN Channel wake up with result */ + OTGHS_VTRACE2_CHANWAKEUP_OUT, /* OTGHS OUT Channel wake up with result */ + OTGHS_VTRACE2_CTRLIN, /* OTGHS CTRLIN */ + OTGHS_VTRACE2_CTRLOUT, /* OTGHS CTRLOUT */ + OTGHS_VTRACE2_INTRIN, /* OTGHS INTRIN */ + OTGHS_VTRACE2_INTROUT, /* OTGHS INTROUT */ + OTGHS_VTRACE2_BULKIN, /* OTGHS BULKIN */ + OTGHS_VTRACE2_BULKOUT, /* OTGHS BULKOUT */ + OTGHS_VTRACE2_ISOCIN, /* OTGHS ISOCIN */ + OTGHS_VTRACE2_ISOCOUT, /* OTGHS ISOCOUT */ + OTGHS_VTRACE2_STARTTRANSFER, /* OTGHS EP buflen */ + OTGHS_VTRACE2_CHANCONF_CTRL_IN, + OTGHS_VTRACE2_CHANCONF_CTRL_OUT, + OTGHS_VTRACE2_CHANCONF_INTR_IN, + OTGHS_VTRACE2_CHANCONF_INTR_OUT, + OTGHS_VTRACE2_CHANCONF_BULK_IN, + OTGHS_VTRACE2_CHANCONF_BULK_OUT, + OTGHS_VTRACE2_CHANCONF_ISOC_IN, + OTGHS_VTRACE2_CHANCONF_ISOC_OUT, + OTGHS_VTRACE2_CHANHALT, /* Channel halted. chidx: , reason: */ + +# endif +#endif + + __TRACE2_NSTRINGS /* Total number of enumeration values */ +}; + +# define TRACE1_FIRST ((int)__TRACE1_BASEVALUE + 1) +# define TRACE1_INDEX(id) ((int)(id) - TRACE1_FIRST) +# define TRACE1_NSTRINGS TRACE1_INDEX(__TRACE1_NSTRINGS) + +# define TRACE2_FIRST ((int)__TRACE1_NSTRINGS + 1) +# define TRACE2_INDEX(id) ((int)(id) - TRACE2_FIRST) +# define TRACE2_NSTRINGS TRACE2_INDEX(__TRACE2_NSTRINGS) + +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/* STM32 USB OTG FS Host Driver Support + * + * Pre-requisites + * + * CONFIG_STM32_USBHOST - Enable general USB host support + * CONFIG_USBHOST - Enable general USB host support + * CONFIG_STM32_OTGFS - Enable the STM32 USB OTG FS block + * or + * CONFIG_STM32_OTGHS - Enable the STM32 USB OTG HS block + * CONFIG_STM32_SYSCFG - Needed + * + * Options: + * + * CONFIG_STM32_OTGFS_RXFIFO_SIZE - Size of the RX FIFO in 32-bit words. + * Default 128 (512 bytes) + * CONFIG_STM32_OTGFS_NPTXFIFO_SIZE - Size of the non-periodic Tx FIFO + * in 32-bit words. Default 96 (384 bytes) + * CONFIG_STM32_OTGFS_PTXFIFO_SIZE - Size of the periodic Tx FIFO in 32-bit + * words. Default 96 (384 bytes) + * CONFIG_STM32_OTGFS_SOFINTR - Enable SOF interrupts. Why would you ever + * want to do that? + * + * CONFIG_STM32_OTGHS_RXFIFO_SIZE - Size of the RX FIFO in 32-bit words. + * Default 128 (512 bytes) + * CONFIG_STM32_OTGHS_NPTXFIFO_SIZE - Size of the non-periodic Tx FIFO + * in 32-bit words. Default 96 (384 bytes) + * CONFIG_STM32_OTGHS_PTXFIFO_SIZE - Size of the periodic Tx FIFO in 32-bit + * words. Default 96 (384 bytes) + * CONFIG_STM32_OTGHS_SOFINTR - Enable SOF interrupts. Why would you ever + * want to do that? + * + * CONFIG_STM32_USBHOST_REGDEBUG - Enable very low-level register access + * debug. Depends on CONFIG_DEBUG_FEATURES. + */ + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Name: stm32_usbhost_vbusdrive + * + * Description: + * Enable/disable driving of VBUS 5V output. This function must be + * provided be each platform that implements the STM32 OTG FS host + * interface. + * + * "On-chip 5 V VBUS generation is not supported. For this reason, a + * charge pump or, if 5 V are available on the application board, a basic + * power switch, must be added externally to drive the 5 V VBUS line. The + * external charge pump can be driven by any GPIO output. When the + * application decides to power on VBUS using the chosen GPIO, it must + * also set the port power bit in the host port control and status + * register (PPWR bit in OTG_FS_HPRT). + * + * "The application uses this field to control power to this port, and the + * core clears this bit on an overcurrent condition." + * + * Input Parameters: + * iface - For future growth to handle multiple USB host interface. + * Should be zero. + * enable - true: enable VBUS power; false: disable VBUS power + * + * Returned Value: + * None + * + ****************************************************************************/ + +#if defined(CONFIG_STM32_OTGFS_VBUS_CONTROL) || \ + defined(CONFIG_STM32_OTGHS_VBUS_CONTROL) +void stm32_usbhost_vbusdrive(int iface, bool enable); +#endif + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* CONFIG_STM32_OTGFS && CONFIG_STM32_USBHOST */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_USBHOST_H */ diff --git a/arch/arm/src/stm32/stm32_userspace.h b/arch/arm/src/common/stm32/stm32_userspace.h similarity index 91% rename from arch/arm/src/stm32/stm32_userspace.h rename to arch/arm/src/common/stm32/stm32_userspace.h index 8cdb47e52ff37..36da6f4a783ab 100644 --- a/arch/arm/src/stm32/stm32_userspace.h +++ b/arch/arm/src/common/stm32/stm32_userspace.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_userspace.h + * arch/arm/src/common/stm32/stm32_userspace.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_STM32_USERSPACE_H -#define __ARCH_ARM_SRC_STM32_STM32_USERSPACE_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_USERSPACE_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_USERSPACE_H /**************************************************************************** * Included Files @@ -60,4 +60,4 @@ void stm32_userspace(void); #endif -#endif /* __ARCH_ARM_SRC_STM32_STM32_USERSPACE_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_USERSPACE_H */ diff --git a/arch/arm/src/common/stm32/stm32_userspace_m3m4_v1.c b/arch/arm/src/common/stm32/stm32_userspace_m3m4_v1.c new file mode 100644 index 0000000000000..31f567ecd0295 --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_userspace_m3m4_v1.c @@ -0,0 +1,105 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_userspace_m3m4_v1.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include + +#include "stm32_mpuinit.h" +#include "stm32_userspace.h" + +#ifdef CONFIG_BUILD_PROTECTED + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_userspace + * + * Description: + * For the case of the separate user-/kernel-space build, perform whatever + * platform specific initialization of the user memory is required. + * Normally this just means initializing the user space .data and .bss + * segments. + * + ****************************************************************************/ + +void stm32_userspace(void) +{ + uint8_t *src; + uint8_t *dest; + uint8_t *end; + + /* Clear all of user-space .bss */ + + DEBUGASSERT(USERSPACE->us_bssstart != 0 && USERSPACE->us_bssend != 0 && + USERSPACE->us_bssstart <= USERSPACE->us_bssend); + + dest = (uint8_t *)USERSPACE->us_bssstart; + end = (uint8_t *)USERSPACE->us_bssend; + + while (dest != end) + { + *dest++ = 0; + } + + /* Initialize all of user-space .data */ + + DEBUGASSERT(USERSPACE->us_datasource != 0 && + USERSPACE->us_datastart != 0 && USERSPACE->us_dataend != 0 && + USERSPACE->us_datastart <= USERSPACE->us_dataend); + + src = (uint8_t *)USERSPACE->us_datasource; + dest = (uint8_t *)USERSPACE->us_datastart; + end = (uint8_t *)USERSPACE->us_dataend; + + while (dest != end) + { + *dest++ = *src++; + } + + /* Configure the MPU to permit user-space access to its FLASH and RAM */ + + stm32_mpuinitialize(); +} + +#endif /* CONFIG_BUILD_PROTECTED */ diff --git a/arch/arm/src/common/stm32/stm32_waste.c b/arch/arm/src/common/stm32/stm32_waste.c new file mode 100644 index 0000000000000..afe7b82661972 --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_waste.c @@ -0,0 +1,44 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_waste.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include "stm32_waste.h" + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +uint32_t g_waste_counter = 0; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +void stm32_waste(void) +{ + g_waste_counter++; +} diff --git a/arch/arm/src/common/stm32/stm32_waste.h b/arch/arm/src/common/stm32/stm32_waste.h new file mode 100644 index 0000000000000..702c166346ab1 --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_waste.h @@ -0,0 +1,45 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_waste.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_WASTE_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_WASTE_H + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +void stm32_waste(void); + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_WASTE_H */ diff --git a/arch/arm/src/common/stm32/stm32_wdg.h b/arch/arm/src/common/stm32/stm32_wdg.h new file mode 100644 index 0000000000000..c70b669ad87d7 --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_wdg.h @@ -0,0 +1,104 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_wdg.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_WDG_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_WDG_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "chip.h" +#include "hardware/stm32_wdg.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_iwdginitialize + * + * Description: + * Initialize the IWDG watchdog time. The watchdog timer is initialized + * and registers as 'devpath. The initial state of the watchdog time is + * disabled. + * + * Input Parameters: + * devpath - The full path to the watchdog. This should be of the form + * /dev/watchdog0 + * lsifreq - The calibrated LSI clock frequency + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_IWDG +void stm32_iwdginitialize(const char *devpath, uint32_t lsifreq); +#endif + +/**************************************************************************** + * Name: stm32_wwdginitialize + * + * Description: + * Initialize the WWDG watchdog time. The watchdog timer is initializeed + * and registers as 'devpath. The initial state of the watchdog time is + * disabled. + * + * Input Parameters: + * devpath - The full path to the watchdog. This should be of the form + * /dev/watchdog0 + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_WWDG +void stm32_wwdginitialize(const char *devpath); +#endif + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_WDG_H */ diff --git a/arch/arm/src/common/stm32/stm32_wwdg_m0_v1.c b/arch/arm/src/common/stm32/stm32_wwdg_m0_v1.c new file mode 100644 index 0000000000000..9ec66a9fa9294 --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_wwdg_m0_v1.c @@ -0,0 +1,801 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_wwdg_m0_v1.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include +#include +#include + +#include +#include +#include +#include + +#include "arm_internal.h" +#include "hardware/stm32_dbgmcu.h" +#include "stm32_wdg.h" + +#if defined(CONFIG_WATCHDOG) && defined(CONFIG_STM32_WWDG) + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Clocking *****************************************************************/ + +/* The minimum frequency of the WWDG clock is: + * + * Fmin = PCLK1 / 4096 / 8 + * + * So the maximum delay (in milliseconds) is then: + * + * 1000 * (WWDG_CR_T_MAX+1) / Fmin + * + * For example, if PCLK1 = 42MHz, then the maximum delay is: + * + * Fmin = 1281.74 + * 1000 * 64 / Fmin = 49.93 msec + */ + +#define WWDG_FMIN (STM32_PCLK1_FREQUENCY / 4096 / 8) +#define WWDG_MAXTIMEOUT (1000 * (WWDG_CR_T_MAX+1) / WWDG_FMIN) + +/* Configuration ************************************************************/ + +#ifndef CONFIG_STM32_WWDG_DEFTIMOUT +# define CONFIG_STM32_WWDG_DEFTIMOUT WWDG_MAXTIMEOUT +#endif + +#ifndef CONFIG_DEBUG_WATCHDOG_INFO +# undef CONFIG_STM32_WWDG_REGDEBUG +#endif + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/* This structure provides the private representation of the "lower-half" + * driver state structure. This structure must be cast-compatible with the + * well-known watchdog_lowerhalf_s structure. + */ + +struct stm32_lowerhalf_s +{ + const struct watchdog_ops_s *ops; /* Lower half operations */ + xcpt_t handler; /* Current EWI interrupt handler */ + uint32_t timeout; /* The actual timeout value */ + uint32_t fwwdg; /* WWDG clock frequency */ + bool started; /* The timer has been started */ + uint8_t reload; /* The 7-bit reload field reset value */ + uint8_t window; /* The 7-bit window (W) field value */ +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/* Register operations ******************************************************/ + +#ifdef CONFIG_STM32_WWDG_REGDEBUG +static uint16_t stm32_getreg(uint32_t addr); +static void stm32_putreg(uint16_t val, uint32_t addr); +#else +# define stm32_getreg(addr) getreg32(addr) +# define stm32_putreg(val,addr) putreg32(val,addr) +#endif +static void stm32_setwindow(struct stm32_lowerhalf_s *priv, + uint8_t window); + +/* Interrupt handling *******************************************************/ + +static int stm32_interrupt(int irq, void *context, void *arg); + +/* "Lower half" driver methods **********************************************/ + +static int stm32_start(struct watchdog_lowerhalf_s *lower); +static int stm32_stop(struct watchdog_lowerhalf_s *lower); +static int stm32_keepalive(struct watchdog_lowerhalf_s *lower); +static int stm32_getstatus(struct watchdog_lowerhalf_s *lower, + struct watchdog_status_s *status); +static int stm32_settimeout(struct watchdog_lowerhalf_s *lower, + uint32_t timeout); +static xcpt_t stm32_capture(struct watchdog_lowerhalf_s *lower, + xcpt_t handler); +static int stm32_ioctl(struct watchdog_lowerhalf_s *lower, int cmd, + unsigned long arg); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* "Lower half" driver methods */ + +static const struct watchdog_ops_s g_wdgops = +{ + .start = stm32_start, + .stop = stm32_stop, + .keepalive = stm32_keepalive, + .getstatus = stm32_getstatus, + .settimeout = stm32_settimeout, + .capture = stm32_capture, + .ioctl = stm32_ioctl, +}; + +/* "Lower half" driver state */ + +static struct stm32_lowerhalf_s g_wdgdev; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_getreg + * + * Description: + * Get the contents of an STM32 register + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_WWDG_REGDEBUG +static uint16_t stm32_getreg(uint32_t addr) +{ + static uint32_t prevaddr = 0; + static uint32_t count = 0; + static uint16_t preval = 0; + + /* Read the value from the register */ + + uint16_t val = getreg16(addr); + + /* Is this the same value that we read from the same register last time? + * Are we polling the register? If so, suppress some of the output. + */ + + if (addr == prevaddr && val == preval) + { + if (count == 0xffffffff || ++count > 3) + { + if (count == 4) + { + wdinfo("...\n"); + } + + return val; + } + } + + /* No this is a new address or value */ + + else + { + /* Did we print "..." for the previous value? */ + + if (count > 3) + { + /* Yes.. then show how many times the value repeated */ + + wdinfo("[repeats %d more times]\n", count - 3); + } + + /* Save the new address, value, and count */ + + prevaddr = addr; + preval = val; + count = 1; + } + + /* Show the register value read */ + + wdinfo("%08" PRIx32 "->%04x\n", addr, val); + return val; +} +#endif + +/**************************************************************************** + * Name: stm32_putreg + * + * Description: + * Set the contents of an STM32 register to a value + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_WWDG_REGDEBUG +static void stm32_putreg(uint16_t val, uint32_t addr) +{ + /* Show the register value being written */ + + wdinfo("%08" PRIx32 "<-%04x\n", addr, val); + + /* Write the value */ + + putreg16(val, addr); +} +#endif + +/**************************************************************************** + * Name: stm32_setwindow + * + * Description: + * Set the CFR window value. The window value is compared to the down- + * counter when the counter is updated. The WWDG counter should be updated + * only when the counter is below this window value (and greater than 64) + * otherwise a reset will be generated + * + ****************************************************************************/ + +static void stm32_setwindow(struct stm32_lowerhalf_s *priv, + uint8_t window) +{ + uint16_t regval; + + /* Set W[6:0] bits according to selected window value */ + + regval = stm32_getreg(STM32_WWDG_CFR); + regval &= ~WWDG_CFR_W_MASK; + regval |= window << WWDG_CFR_W_SHIFT; + stm32_putreg(regval, STM32_WWDG_CFR); + + /* Remember the window setting */ + + priv->window = window; +} + +/**************************************************************************** + * Name: stm32_interrupt + * + * Description: + * WWDG early warning interrupt + * + * Input Parameters: + * Usual interrupt handler arguments. + * + * Returned Value: + * Always returns OK. + * + ****************************************************************************/ + +static int stm32_interrupt(int irq, void *context, void *arg) +{ + struct stm32_lowerhalf_s *priv = &g_wdgdev; + uint16_t regval; + + /* Check if the EWI interrupt is really pending */ + + regval = stm32_getreg(STM32_WWDG_SR); + if ((regval & WWDG_SR_EWIF) != 0) + { + /* Is there a registered handler? */ + + if (priv->handler) + { + /* Yes... NOTE: This interrupt service routine (ISR) must reload + * the WWDG counter to prevent the reset. Otherwise, we will reset + * upon return. + */ + + priv->handler(irq, context, arg); + } + + /* The EWI interrupt is cleared by writing '0' to the EWIF bit in the + * WWDG_SR register. + */ + + regval &= ~WWDG_SR_EWIF; + stm32_putreg(regval, STM32_WWDG_SR); + } + + return OK; +} + +/**************************************************************************** + * Name: stm32_start + * + * Description: + * Start the watchdog timer, resetting the time to the current timeout, + * + * Input Parameters: + * lower - A pointer the publicly visible representation of the "lower- + * half" driver state structure. + * + * Returned Value: + * Zero on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int stm32_start(struct watchdog_lowerhalf_s *lower) +{ + struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; + + wdinfo("Entry\n"); + DEBUGASSERT(priv); + + /* The watchdog is always disabled after a reset. It is enabled by setting + * the WDGA bit in the WWDG_CR register, then it cannot be disabled again + * except by a reset. + */ + + stm32_putreg(WWDG_CR_WDGA | WWDG_CR_T_RESET | priv->reload, STM32_WWDG_CR); + priv->started = true; + return OK; +} + +/**************************************************************************** + * Name: stm32_stop + * + * Description: + * Stop the watchdog timer + * + * Input Parameters: + * lower - A pointer the publicly visible representation of the "lower- + * half" driver state structure. + * + * Returned Value: + * Zero on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int stm32_stop(struct watchdog_lowerhalf_s *lower) +{ + /* The watchdog is always disabled after a reset. It is enabled by setting + * the WDGA bit in the WWDG_CR register, then it cannot be disabled again + * except by a reset. + */ + + wdinfo("Entry\n"); + return -ENOSYS; +} + +/**************************************************************************** + * Name: stm32_keepalive + * + * Description: + * Reset the watchdog timer to the current timeout value, prevent any + * imminent watchdog timeouts. This is sometimes referred as "pinging" + * the watchdog timer or "petting the dog". + * + * The application program must write in the WWDG_CR register at regular + * intervals during normal operation to prevent an MCU reset. This + * operation must occur only when the counter value is lower than the + * window register value. The value to be stored in the WWDG_CR register + * must be between 0xff and 0xC0: + * + * Input Parameters: + * lower - A pointer the publicly visible representation of the "lower- + * half" driver state structure. + * + * Returned Value: + * Zero on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int stm32_keepalive(struct watchdog_lowerhalf_s *lower) +{ + struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; + + wdinfo("Entry\n"); + DEBUGASSERT(priv); + + /* Write to T[6:0] bits to configure the counter value, no need to do + * a read-modify-write; writing a 0 to WDGA bit does nothing. + */ + + stm32_putreg((WWDG_CR_T_RESET | priv->reload), STM32_WWDG_CR); + return OK; +} + +/**************************************************************************** + * Name: stm32_getstatus + * + * Description: + * Get the current watchdog timer status + * + * Input Parameters: + * lower - A pointer the publicly visible representation of the "lower- + * half" driver state structure. + * status - The location to return the watchdog status information. + * + * Returned Value: + * Zero on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int stm32_getstatus(struct watchdog_lowerhalf_s *lower, + struct watchdog_status_s *status) +{ + struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; + uint32_t elapsed; + uint16_t reload; + + wdinfo("Entry\n"); + DEBUGASSERT(priv); + + /* Return the status bit */ + + status->flags = WDFLAGS_RESET; + if (priv->started) + { + status->flags |= WDFLAGS_ACTIVE; + } + + if (priv->handler) + { + status->flags |= WDFLAGS_CAPTURE; + } + + /* Return the actual timeout is milliseconds */ + + status->timeout = priv->timeout; + + /* Get the time remaining until the watchdog expires (in milliseconds) */ + + reload = (stm32_getreg(STM32_WWDG_CR) >> WWDG_CR_T_SHIFT) & 0x7f; + elapsed = priv->reload - reload; + status->timeleft = (priv->timeout * elapsed) / (priv->reload + 1); + + wdinfo("Status :\n"); + wdinfo(" flags : %08x\n", (unsigned)status->flags); + wdinfo(" timeout : %u\n", (unsigned)status->timeout); + wdinfo(" timeleft : %u\n", (unsigned)status->flags); + return OK; +} + +/**************************************************************************** + * Name: stm32_settimeout + * + * Description: + * Set a new timeout value (and reset the watchdog timer) + * + * Input Parameters: + * lower - A pointer the publicly visible representation of the + * "lower-half" driver state structure. + * timeout - The new timeout value in milliseconds. + * + * Returned Value: + * Zero on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int stm32_settimeout(struct watchdog_lowerhalf_s *lower, + uint32_t timeout) +{ + struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; + uint32_t fwwdg; + uint32_t reload; + uint16_t regval; + int wdgtb; + + DEBUGASSERT(priv); + wdinfo("Entry: timeout=%u\n", (unsigned)timeout); + + /* Can this timeout be represented? */ + + if (timeout < 1 || timeout > WWDG_MAXTIMEOUT) + { + wderr("ERROR: Cannot represent timeout=%u > %lu\n", + (unsigned)timeout, WWDG_MAXTIMEOUT); + return -ERANGE; + } + + /* Determine prescaler value. + * + * Fwwdg = PCLK1/4096/prescaler. + * + * Where + * Fwwwdg is the frequency of the WWDG clock + * wdgtb is one of {1, 2, 4, or 8} + */ + + /* Select the smallest prescaler that will result in a reload field value + * that is less than the maximum. + */ + + for (wdgtb = 0; ; wdgtb++) + { + /* WDGTB = 0 -> Divider = 1 = 1 << 0 + * WDGTB = 1 -> Divider = 2 = 1 << 1 + * WDGTB = 2 -> Divider = 4 = 1 << 2 + * WDGTB = 3 -> Divider = 8 = 1 << 3 + */ + + /* Get the WWDG counter frequency in Hz. */ + + fwwdg = (STM32_PCLK1_FREQUENCY / 4096) >> wdgtb; + + /* The formula to calculate the timeout value is given by: + * + * timeout = 1000 * (reload + 1) / Fwwdg, OR + * reload = timeout * Fwwdg / 1000 - 1 + * + * Where + * timeout is the desired timeout in milliseconds + * reload is the contents of T{5:0] + * Fwwdg is the frequency of the WWDG clock + */ + + reload = timeout * fwwdg / 1000 - 1; + + /* If this reload valid is less than the maximum or we are not ready + * at the prescaler value, then break out of the loop to use these + * settings. + */ + +#if 0 + wdinfo("wdgtb=%d fwwdg=%d reload=%d timeout=%d\n", + wdgtb, fwwdg, reload, 1000 * (reload + 1) / fwwdg); +#endif + if (reload <= WWDG_CR_T_MAX || wdgtb == 3) + { + /* Note that we explicitly break out of the loop rather than using + * the 'for' loop termination logic because we do not want the + * value of wdgtb to be incremented. + */ + + break; + } + } + + /* Make sure that the final reload value is within range */ + + if (reload > WWDG_CR_T_MAX) + { + reload = WWDG_CR_T_MAX; + } + + /* Calculate and save the actual timeout value in milliseconds: + * + * timeout = 1000 * (reload + 1) / Fwwdg + */ + + priv->timeout = 1000 * (reload + 1) / fwwdg; + + /* Remember the selected values */ + + priv->fwwdg = fwwdg; + priv->reload = reload; + + wdinfo("wdgtb=%d fwwdg=%u reload=%u timeout=%u\n", + wdgtb, (unsigned)fwwdg, (unsigned)reload, (unsigned)priv->timeout); + + /* Set WDGTB[1:0] bits according to calculated value */ + + regval = stm32_getreg(STM32_WWDG_CFR); + regval &= ~WWDG_CFR_WDGTB_MASK; + regval |= (uint16_t)wdgtb << WWDG_CFR_WDGTB_SHIFT; + stm32_putreg(regval, STM32_WWDG_CFR); + + /* Reset the 7-bit window value to the maximum value.. essentially + * disabling the lower limit of the watchdog reset time. + */ + + stm32_setwindow(priv, 0x7f); + return OK; +} + +/**************************************************************************** + * Name: stm32_capture + * + * Description: + * Don't reset on watchdog timer timeout; instead, call this user provider + * timeout handler. NOTE: Providing handler==NULL will restore the reset + * behavior. + * + * Input Parameters: + * lower - A pointer the publicly visible representation of the + * "lower-half" driver state structure. + * newhandler - The new watchdog expiration function pointer. If this + * function pointer is NULL, then the reset-on-expiration + * behavior is restored, + * + * Returned Value: + * The previous watchdog expiration function pointer or NULL is there was + * no previous function pointer, i.e., if the previous behavior was + * reset-on-expiration (NULL is also returned if an error occurs). + * + ****************************************************************************/ + +static xcpt_t stm32_capture(struct watchdog_lowerhalf_s *lower, + xcpt_t handler) +{ + struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; + irqstate_t flags; + xcpt_t oldhandler; + uint16_t regval; + + DEBUGASSERT(priv); + wdinfo("Entry: handler=%p\n", handler); + + /* Get the old handler return value */ + + flags = enter_critical_section(); + oldhandler = priv->handler; + + /* Save the new handler */ + + priv->handler = handler; + + /* Are we attaching or detaching the handler? */ + + regval = stm32_getreg(STM32_WWDG_CFR); + if (handler) + { + /* Attaching... Enable the EWI interrupt */ + + regval |= WWDG_CFR_EWI; + stm32_putreg(regval, STM32_WWDG_CFR); + + up_enable_irq(STM32_IRQ_WWDG); + } + else + { + /* Detaching... Disable the EWI interrupt */ + + regval &= ~WWDG_CFR_EWI; + stm32_putreg(regval, STM32_WWDG_CFR); + + up_disable_irq(STM32_IRQ_WWDG); + } + + leave_critical_section(flags); + return oldhandler; +} + +/**************************************************************************** + * Name: stm32_ioctl + * + * Description: + * Any ioctl commands that are not recognized by the "upper-half" driver + * are forwarded to the lower half driver through this method. + * + * Input Parameters: + * lower - A pointer the publicly visible representation of the "lower- + * half" driver state structure. + * cmd - The ioctl command value + * arg - The optional argument that accompanies the 'cmd'. The + * interpretation of this argument depends on the particular + * command. + * + * Returned Value: + * Zero on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int stm32_ioctl(struct watchdog_lowerhalf_s *lower, int cmd, + unsigned long arg) +{ + struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; + int ret = -ENOTTY; + + DEBUGASSERT(priv); + wdinfo("Entry: cmd=%d arg=%ld\n", cmd, arg); + + /* WDIOC_MINTIME: Set the minimum ping time. If two keepalive ioctls + * are received within this time, a reset event will be generated. + * Argument: A 32-bit time value in milliseconds. + */ + + if (cmd == WDIOC_MINTIME) + { + uint32_t mintime = (uint32_t)arg; + + /* The minimum time should be strictly less than the total delay + * which, in turn, will be less than or equal to WWDG_CR_T_MAX + */ + + ret = -EINVAL; + if (mintime < priv->timeout) + { + uint32_t window = (priv->timeout - mintime) * priv->fwwdg / + 1000 - 1; + DEBUGASSERT(window < priv->reload); + stm32_setwindow(priv, window | WWDG_CR_T_RESET); + ret = OK; + } + } + + return ret; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_wwdginitialize + * + * Description: + * Initialize the WWDG watchdog timer. The watchdog timer is initialized + * and registers as 'devpath'. The initial state of the watchdog timer is + * disabled. + * + * Input Parameters: + * devpath - The full path to the watchdog. This should be of the form + * /dev/watchdog0 + * + * Returned Value: + * None + * + ****************************************************************************/ + +void stm32_wwdginitialize(const char *devpath) +{ + struct stm32_lowerhalf_s *priv = &g_wdgdev; + + wdinfo("Entry: devpath=%s\n", devpath); + + /* NOTE we assume that clocking to the WWDG has already been provided by + * the RCC initialization logic. + */ + + /* Initialize the driver state structure. Here we assume: (1) the state + * structure lies in .bss and was zeroed at reset time. (2) This function + * is only called once so it is never necessary to re-zero the structure. + */ + + priv->ops = &g_wdgops; + + /* Attach our EWI interrupt handler (But don't enable it yet) */ + + irq_attach(STM32_IRQ_WWDG, stm32_interrupt, NULL); + + /* Select an arbitrary initial timeout value. But don't start the watchdog + * yet. NOTE: If the "Hardware watchdog" feature is enabled through the + * device option bits, the watchdog is automatically enabled at power-on. + */ + + stm32_settimeout((struct watchdog_lowerhalf_s *)priv, + CONFIG_STM32_WWDG_DEFTIMOUT); + + /* Register the watchdog driver as /dev/watchdog0 */ + + watchdog_register(devpath, (struct watchdog_lowerhalf_s *)priv); + + /* When the microcontroller enters debug mode (Cortex-M core halted), + * the WWDG counter either continues to work normally or stops, depending + * on DBG_WWDG_STOP configuration bit in DBG module. + */ + +#if defined(CONFIG_STM32_JTAG_FULL_ENABLE) || \ + defined(CONFIG_STM32_JTAG_NOJNTRST_ENABLE) || \ + defined(CONFIG_STM32_JTAG_SW_ENABLE) + { +#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F30XX) || \ + defined(CONFIG_STM32_STM32F4XXX) || defined(CONFIG_STM32_STM32L15XX) + uint32_t cr = getreg32(STM32_DBGMCU_APB1_FZ); + cr |= DBGMCU_APB1_WWDGSTOP; + putreg32(cr, STM32_DBGMCU_APB1_FZ); +#else /* if defined(CONFIG_STM32_STM32F10XX) */ + uint32_t cr = getreg32(STM32_DBGMCU_CR); + cr |= DBGMCU_CR_WWDGSTOP; + putreg32(cr, STM32_DBGMCU_CR); +#endif + } +#endif +} + +#endif /* CONFIG_WATCHDOG && CONFIG_STM32_WWDG */ diff --git a/arch/arm/src/common/stm32/stm32_wwdg_m3m4_v1.c b/arch/arm/src/common/stm32/stm32_wwdg_m3m4_v1.c new file mode 100644 index 0000000000000..8d8ccdac2b02a --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_wwdg_m3m4_v1.c @@ -0,0 +1,801 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_wwdg_m3m4_v1.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include +#include +#include + +#include +#include +#include +#include + +#include "arm_internal.h" +#include "hardware/stm32_dbgmcu.h" +#include "stm32_wdg.h" + +#if defined(CONFIG_WATCHDOG) && defined(CONFIG_STM32_WWDG) + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Clocking *****************************************************************/ + +/* The minimum frequency of the WWDG clock is: + * + * Fmin = PCLK1 / 4096 / 8 + * + * So the maximum delay (in milliseconds) is then: + * + * 1000 * (WWDG_CR_T_MAX+1) / Fmin + * + * For example, if PCLK1 = 42MHz, then the maximum delay is: + * + * Fmin = 1281.74 + * 1000 * 64 / Fmin = 49.93 msec + */ + +#define WWDG_FMIN (STM32_PCLK1_FREQUENCY / 4096 / 8) +#define WWDG_MAXTIMEOUT (1000 * (WWDG_CR_T_MAX+1) / WWDG_FMIN) + +/* Configuration ************************************************************/ + +#ifndef CONFIG_STM32_WWDG_DEFTIMOUT +# define CONFIG_STM32_WWDG_DEFTIMOUT WWDG_MAXTIMEOUT +#endif + +#ifndef CONFIG_DEBUG_WATCHDOG_INFO +# undef CONFIG_STM32_WWDG_REGDEBUG +#endif + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/* This structure provides the private representation of the "lower-half" + * driver state structure. This structure must be cast-compatible with the + * well-known watchdog_lowerhalf_s structure. + */ + +struct stm32_lowerhalf_s +{ + const struct watchdog_ops_s *ops; /* Lower half operations */ + xcpt_t handler; /* Current EWI interrupt handler */ + uint32_t timeout; /* The actual timeout value */ + uint32_t fwwdg; /* WWDG clock frequency */ + bool started; /* The timer has been started */ + uint8_t reload; /* The 7-bit reload field reset value */ + uint8_t window; /* The 7-bit window (W) field value */ +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/* Register operations ******************************************************/ + +#ifdef CONFIG_STM32_WWDG_REGDEBUG +static uint16_t stm32_getreg(uint32_t addr); +static void stm32_putreg(uint16_t val, uint32_t addr); +#else +# define stm32_getreg(addr) getreg32(addr) +# define stm32_putreg(val,addr) putreg32(val,addr) +#endif +static void stm32_setwindow(struct stm32_lowerhalf_s *priv, + uint8_t window); + +/* Interrupt handling *******************************************************/ + +static int stm32_interrupt(int irq, void *context, void *arg); + +/* "Lower half" driver methods **********************************************/ + +static int stm32_start(struct watchdog_lowerhalf_s *lower); +static int stm32_stop(struct watchdog_lowerhalf_s *lower); +static int stm32_keepalive(struct watchdog_lowerhalf_s *lower); +static int stm32_getstatus(struct watchdog_lowerhalf_s *lower, + struct watchdog_status_s *status); +static int stm32_settimeout(struct watchdog_lowerhalf_s *lower, + uint32_t timeout); +static xcpt_t stm32_capture(struct watchdog_lowerhalf_s *lower, + xcpt_t handler); +static int stm32_ioctl(struct watchdog_lowerhalf_s *lower, int cmd, + unsigned long arg); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* "Lower half" driver methods */ + +static const struct watchdog_ops_s g_wdgops = +{ + .start = stm32_start, + .stop = stm32_stop, + .keepalive = stm32_keepalive, + .getstatus = stm32_getstatus, + .settimeout = stm32_settimeout, + .capture = stm32_capture, + .ioctl = stm32_ioctl, +}; + +/* "Lower half" driver state */ + +static struct stm32_lowerhalf_s g_wdgdev; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_getreg + * + * Description: + * Get the contents of an STM32 register + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_WWDG_REGDEBUG +static uint16_t stm32_getreg(uint32_t addr) +{ + static uint32_t prevaddr = 0; + static uint32_t count = 0; + static uint16_t preval = 0; + + /* Read the value from the register */ + + uint16_t val = getreg16(addr); + + /* Is this the same value that we read from the same register last time? + * Are we polling the register? If so, suppress some of the output. + */ + + if (addr == prevaddr && val == preval) + { + if (count == 0xffffffff || ++count > 3) + { + if (count == 4) + { + wdinfo("...\n"); + } + + return val; + } + } + + /* No this is a new address or value */ + + else + { + /* Did we print "..." for the previous value? */ + + if (count > 3) + { + /* Yes.. then show how many times the value repeated */ + + wdinfo("[repeats %d more times]\n", count - 3); + } + + /* Save the new address, value, and count */ + + prevaddr = addr; + preval = val; + count = 1; + } + + /* Show the register value read */ + + wdinfo("%08" PRIx32 "->%04x\n", addr, val); + return val; +} +#endif + +/**************************************************************************** + * Name: stm32_putreg + * + * Description: + * Set the contents of an STM32 register to a value + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_WWDG_REGDEBUG +static void stm32_putreg(uint16_t val, uint32_t addr) +{ + /* Show the register value being written */ + + wdinfo("%08" PRIx32 "<-%04x\n", addr, val); + + /* Write the value */ + + putreg16(val, addr); +} +#endif + +/**************************************************************************** + * Name: stm32_setwindow + * + * Description: + * Set the CFR window value. The window value is compared to the down- + * counter when the counter is updated. The WWDG counter should be updated + * only when the counter is below this window value (and greater than 64) + * otherwise a reset will be generated + * + ****************************************************************************/ + +static void stm32_setwindow(struct stm32_lowerhalf_s *priv, + uint8_t window) +{ + uint16_t regval; + + /* Set W[6:0] bits according to selected window value */ + + regval = stm32_getreg(STM32_WWDG_CFR); + regval &= ~WWDG_CFR_W_MASK; + regval |= window << WWDG_CFR_W_SHIFT; + stm32_putreg(regval, STM32_WWDG_CFR); + + /* Remember the window setting */ + + priv->window = window; +} + +/**************************************************************************** + * Name: stm32_interrupt + * + * Description: + * WWDG early warning interrupt + * + * Input Parameters: + * Usual interrupt handler arguments. + * + * Returned Value: + * Always returns OK. + * + ****************************************************************************/ + +static int stm32_interrupt(int irq, void *context, void *arg) +{ + struct stm32_lowerhalf_s *priv = &g_wdgdev; + uint16_t regval; + + /* Check if the EWI interrupt is really pending */ + + regval = stm32_getreg(STM32_WWDG_SR); + if ((regval & WWDG_SR_EWIF) != 0) + { + /* Is there a registered handler? */ + + if (priv->handler) + { + /* Yes... NOTE: This interrupt service routine (ISR) must reload + * the WWDG counter to prevent the reset. Otherwise, we will reset + * upon return. + */ + + priv->handler(irq, context, arg); + } + + /* The EWI interrupt is cleared by writing '0' to the EWIF bit in the + * WWDG_SR register. + */ + + regval &= ~WWDG_SR_EWIF; + stm32_putreg(regval, STM32_WWDG_SR); + } + + return OK; +} + +/**************************************************************************** + * Name: stm32_start + * + * Description: + * Start the watchdog timer, resetting the time to the current timeout, + * + * Input Parameters: + * lower - A pointer the publicly visible representation of the "lower- + * half" driver state structure. + * + * Returned Value: + * Zero on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int stm32_start(struct watchdog_lowerhalf_s *lower) +{ + struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; + + wdinfo("Entry\n"); + DEBUGASSERT(priv); + + /* The watchdog is always disabled after a reset. It is enabled by setting + * the WDGA bit in the WWDG_CR register, then it cannot be disabled again + * except by a reset. + */ + + stm32_putreg(WWDG_CR_WDGA | WWDG_CR_T_RESET | priv->reload, STM32_WWDG_CR); + priv->started = true; + return OK; +} + +/**************************************************************************** + * Name: stm32_stop + * + * Description: + * Stop the watchdog timer + * + * Input Parameters: + * lower - A pointer the publicly visible representation of the "lower- + * half" driver state structure. + * + * Returned Value: + * Zero on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int stm32_stop(struct watchdog_lowerhalf_s *lower) +{ + /* The watchdog is always disabled after a reset. It is enabled by setting + * the WDGA bit in the WWDG_CR register, then it cannot be disabled again + * except by a reset. + */ + + wdinfo("Entry\n"); + return -ENOSYS; +} + +/**************************************************************************** + * Name: stm32_keepalive + * + * Description: + * Reset the watchdog timer to the current timeout value, prevent any + * imminent watchdog timeouts. This is sometimes referred as "pinging" + * the watchdog timer or "petting the dog". + * + * The application program must write in the WWDG_CR register at regular + * intervals during normal operation to prevent an MCU reset. This + * operation must occur only when the counter value is lower than the + * window register value. The value to be stored in the WWDG_CR register + * must be between 0xff and 0xC0: + * + * Input Parameters: + * lower - A pointer the publicly visible representation of the "lower- + * half" driver state structure. + * + * Returned Value: + * Zero on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int stm32_keepalive(struct watchdog_lowerhalf_s *lower) +{ + struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; + + wdinfo("Entry\n"); + DEBUGASSERT(priv); + + /* Write to T[6:0] bits to configure the counter value, no need to do + * a read-modify-write; writing a 0 to WDGA bit does nothing. + */ + + stm32_putreg((WWDG_CR_T_RESET | priv->reload), STM32_WWDG_CR); + return OK; +} + +/**************************************************************************** + * Name: stm32_getstatus + * + * Description: + * Get the current watchdog timer status + * + * Input Parameters: + * lower - A pointer the publicly visible representation of the "lower- + * half" driver state structure. + * status - The location to return the watchdog status information. + * + * Returned Value: + * Zero on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int stm32_getstatus(struct watchdog_lowerhalf_s *lower, + struct watchdog_status_s *status) +{ + struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; + uint32_t elapsed; + uint16_t reload; + + wdinfo("Entry\n"); + DEBUGASSERT(priv); + + /* Return the status bit */ + + status->flags = WDFLAGS_RESET; + if (priv->started) + { + status->flags |= WDFLAGS_ACTIVE; + } + + if (priv->handler) + { + status->flags |= WDFLAGS_CAPTURE; + } + + /* Return the actual timeout is milliseconds */ + + status->timeout = priv->timeout; + + /* Get the time remaining until the watchdog expires (in milliseconds) */ + + reload = (stm32_getreg(STM32_WWDG_CR) >> WWDG_CR_T_SHIFT) & 0x7f; + elapsed = priv->reload - reload; + status->timeleft = (priv->timeout * elapsed) / (priv->reload + 1); + + wdinfo("Status :\n"); + wdinfo(" flags : %08x\n", (unsigned)status->flags); + wdinfo(" timeout : %u\n", (unsigned)status->timeout); + wdinfo(" timeleft : %u\n", (unsigned)status->flags); + return OK; +} + +/**************************************************************************** + * Name: stm32_settimeout + * + * Description: + * Set a new timeout value (and reset the watchdog timer) + * + * Input Parameters: + * lower - A pointer the publicly visible representation of the + * "lower-half" driver state structure. + * timeout - The new timeout value in milliseconds. + * + * Returned Value: + * Zero on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int stm32_settimeout(struct watchdog_lowerhalf_s *lower, + uint32_t timeout) +{ + struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; + uint32_t fwwdg; + uint32_t reload; + uint16_t regval; + int wdgtb; + + DEBUGASSERT(priv); + wdinfo("Entry: timeout=%u\n", (unsigned)timeout); + + /* Can this timeout be represented? */ + + if (timeout < 1 || timeout > WWDG_MAXTIMEOUT) + { + wderr("ERROR: Cannot represent timeout=%u > %lu\n", + (unsigned)timeout, WWDG_MAXTIMEOUT); + return -ERANGE; + } + + /* Determine prescaler value. + * + * Fwwdg = PCLK1/4096/prescaler. + * + * Where + * Fwwwdg is the frequency of the WWDG clock + * wdgtb is one of {1, 2, 4, or 8} + */ + + /* Select the smallest prescaler that will result in a reload field value + * that is less than the maximum. + */ + + for (wdgtb = 0; ; wdgtb++) + { + /* WDGTB = 0 -> Divider = 1 = 1 << 0 + * WDGTB = 1 -> Divider = 2 = 1 << 1 + * WDGTB = 2 -> Divider = 4 = 1 << 2 + * WDGTB = 3 -> Divider = 8 = 1 << 3 + */ + + /* Get the WWDG counter frequency in Hz. */ + + fwwdg = (STM32_PCLK1_FREQUENCY / 4096) >> wdgtb; + + /* The formula to calculate the timeout value is given by: + * + * timeout = 1000 * (reload + 1) / Fwwdg, OR + * reload = timeout * Fwwdg / 1000 - 1 + * + * Where + * timeout is the desired timeout in milliseconds + * reload is the contents of T{5:0] + * Fwwdg is the frequency of the WWDG clock + */ + + reload = timeout * fwwdg / 1000 - 1; + + /* If this reload valid is less than the maximum or we are not ready + * at the prescaler value, then break out of the loop to use these + * settings. + */ + +#if 0 + wdinfo("wdgtb=%d fwwdg=%d reload=%d timeout=%d\n", + wdgtb, fwwdg, reload, 1000 * (reload + 1) / fwwdg); +#endif + if (reload <= WWDG_CR_T_MAX || wdgtb == 3) + { + /* Note that we explicitly break out of the loop rather than using + * the 'for' loop termination logic because we do not want the + * value of wdgtb to be incremented. + */ + + break; + } + } + + /* Make sure that the final reload value is within range */ + + if (reload > WWDG_CR_T_MAX) + { + reload = WWDG_CR_T_MAX; + } + + /* Calculate and save the actual timeout value in milliseconds: + * + * timeout = 1000 * (reload + 1) / Fwwdg + */ + + priv->timeout = 1000 * (reload + 1) / fwwdg; + + /* Remember the selected values */ + + priv->fwwdg = fwwdg; + priv->reload = reload; + + wdinfo("wdgtb=%d fwwdg=%u reload=%u timeout=%u\n", + wdgtb, (unsigned)fwwdg, (unsigned)reload, (unsigned)priv->timeout); + + /* Set WDGTB[1:0] bits according to calculated value */ + + regval = stm32_getreg(STM32_WWDG_CFR); + regval &= ~WWDG_CFR_WDGTB_MASK; + regval |= (uint16_t)wdgtb << WWDG_CFR_WDGTB_SHIFT; + stm32_putreg(regval, STM32_WWDG_CFR); + + /* Reset the 7-bit window value to the maximum value.. essentially + * disabling the lower limit of the watchdog reset time. + */ + + stm32_setwindow(priv, 0x7f); + return OK; +} + +/**************************************************************************** + * Name: stm32_capture + * + * Description: + * Don't reset on watchdog timer timeout; instead, call this user provider + * timeout handler. NOTE: Providing handler==NULL will restore the reset + * behavior. + * + * Input Parameters: + * lower - A pointer the publicly visible representation of the + * "lower-half" driver state structure. + * newhandler - The new watchdog expiration function pointer. If this + * function pointer is NULL, then the reset-on-expiration + * behavior is restored, + * + * Returned Value: + * The previous watchdog expiration function pointer or NULL is there was + * no previous function pointer, i.e., if the previous behavior was + * reset-on-expiration (NULL is also returned if an error occurs). + * + ****************************************************************************/ + +static xcpt_t stm32_capture(struct watchdog_lowerhalf_s *lower, + xcpt_t handler) +{ + struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; + irqstate_t flags; + xcpt_t oldhandler; + uint16_t regval; + + DEBUGASSERT(priv); + wdinfo("Entry: handler=%p\n", handler); + + /* Get the old handler return value */ + + flags = enter_critical_section(); + oldhandler = priv->handler; + + /* Save the new handler */ + + priv->handler = handler; + + /* Are we attaching or detaching the handler? */ + + regval = stm32_getreg(STM32_WWDG_CFR); + if (handler) + { + /* Attaching... Enable the EWI interrupt */ + + regval |= WWDG_CFR_EWI; + stm32_putreg(regval, STM32_WWDG_CFR); + + up_enable_irq(STM32_IRQ_WWDG); + } + else + { + /* Detaching... Disable the EWI interrupt */ + + regval &= ~WWDG_CFR_EWI; + stm32_putreg(regval, STM32_WWDG_CFR); + + up_disable_irq(STM32_IRQ_WWDG); + } + + leave_critical_section(flags); + return oldhandler; +} + +/**************************************************************************** + * Name: stm32_ioctl + * + * Description: + * Any ioctl commands that are not recognized by the "upper-half" driver + * are forwarded to the lower half driver through this method. + * + * Input Parameters: + * lower - A pointer the publicly visible representation of the "lower- + * half" driver state structure. + * cmd - The ioctl command value + * arg - The optional argument that accompanies the 'cmd'. The + * interpretation of this argument depends on the particular + * command. + * + * Returned Value: + * Zero on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int stm32_ioctl(struct watchdog_lowerhalf_s *lower, int cmd, + unsigned long arg) +{ + struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; + int ret = -ENOTTY; + + DEBUGASSERT(priv); + wdinfo("Entry: cmd=%d arg=%ld\n", cmd, arg); + + /* WDIOC_MINTIME: Set the minimum ping time. If two keepalive ioctls + * are received within this time, a reset event will be generated. + * Argument: A 32-bit time value in milliseconds. + */ + + if (cmd == WDIOC_MINTIME) + { + uint32_t mintime = (uint32_t)arg; + + /* The minimum time should be strictly less than the total delay + * which, in turn, will be less than or equal to WWDG_CR_T_MAX + */ + + ret = -EINVAL; + if (mintime < priv->timeout) + { + uint32_t window = (priv->timeout - mintime) * priv->fwwdg / + 1000 - 1; + DEBUGASSERT(window < priv->reload); + stm32_setwindow(priv, window | WWDG_CR_T_RESET); + ret = OK; + } + } + + return ret; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_wwdginitialize + * + * Description: + * Initialize the WWDG watchdog timer. The watchdog timer is initialized + * and registers as 'devpath'. The initial state of the watchdog timer is + * disabled. + * + * Input Parameters: + * devpath - The full path to the watchdog. This should be of the form + * /dev/watchdog0 + * + * Returned Value: + * None + * + ****************************************************************************/ + +void stm32_wwdginitialize(const char *devpath) +{ + struct stm32_lowerhalf_s *priv = &g_wdgdev; + + wdinfo("Entry: devpath=%s\n", devpath); + + /* NOTE we assume that clocking to the WWDG has already been provided by + * the RCC initialization logic. + */ + + /* Initialize the driver state structure. Here we assume: (1) the state + * structure lies in .bss and was zeroed at reset time. (2) This function + * is only called once so it is never necessary to re-zero the structure. + */ + + priv->ops = &g_wdgops; + + /* Attach our EWI interrupt handler (But don't enable it yet) */ + + irq_attach(STM32_IRQ_WWDG, stm32_interrupt, NULL); + + /* Select an arbitrary initial timeout value. But don't start the watchdog + * yet. NOTE: If the "Hardware watchdog" feature is enabled through the + * device option bits, the watchdog is automatically enabled at power-on. + */ + + stm32_settimeout((struct watchdog_lowerhalf_s *)priv, + CONFIG_STM32_WWDG_DEFTIMOUT); + + /* Register the watchdog driver as /dev/watchdog0 */ + + watchdog_register(devpath, (struct watchdog_lowerhalf_s *)priv); + + /* When the microcontroller enters debug mode (Cortex-M core halted), + * the WWDG counter either continues to work normally or stops, depending + * on DBG_WWDG_STOP configuration bit in DBG module. + */ + +#if defined(CONFIG_STM32_JTAG_FULL_ENABLE) || \ + defined(CONFIG_STM32_JTAG_NOJNTRST_ENABLE) || \ + defined(CONFIG_STM32_JTAG_SW_ENABLE) + { +#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F30XX) || \ + defined(CONFIG_STM32_STM32F4XXX) || defined(CONFIG_STM32_STM32L15XX) + uint32_t cr = getreg32(STM32_DBGMCU_APB1_FZ); + cr |= DBGMCU_APB1_WWDGSTOP; + putreg32(cr, STM32_DBGMCU_APB1_FZ); +#else /* if defined(CONFIG_STM32_STM32F10XX) */ + uint32_t cr = getreg32(STM32_DBGMCU_CR); + cr |= DBGMCU_CR_WWDGSTOP; + putreg32(cr, STM32_DBGMCU_CR); +#endif + } +#endif +} + +#endif /* CONFIG_WATCHDOG && CONFIG_STM32_WWDG */ diff --git a/arch/arm/src/stm32/CMakeLists.txt b/arch/arm/src/stm32/CMakeLists.txt deleted file mode 100644 index a725dcc6f908b..0000000000000 --- a/arch/arm/src/stm32/CMakeLists.txt +++ /dev/null @@ -1,279 +0,0 @@ -# ############################################################################## -# arch/arm/src/stm32/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -set(SRCS) - -list( - APPEND - SRCS - stm32_allocateheap.c - stm32_start.c - stm32_rcc.c - stm32_lse.c - stm32_lsi.c - stm32_gpio.c - stm32_exti_gpio.c - stm32_flash.c - stm32_irq.c - stm32_lowputc.c - stm32_spi.c - stm32_i2s.c - stm32_sdio.c - stm32_tim.c - stm32_waste.c - stm32_ccm.c - stm32_uid.c - stm32_capture.c - stm32_dfumode.c) - -if(CONFIG_STM32_USART) - list(APPEND SRCS stm32_serial.c) -endif() - -if(CONFIG_STM32_DMA) - list(APPEND SRCS stm32_dma.c) -endif() - -if(CONFIG_TIMER) - list(APPEND SRCS stm32_tim_lowerhalf.c) -endif() - -if(CONFIG_STM32_TICKLESS_TIMER) - list(APPEND SRCS stm32_tickless.c) -else() - list(APPEND SRCS stm32_timerisr.c) -endif() - -if(CONFIG_STM32_ONESHOT) - list(APPEND SRCS stm32_oneshot.c stm32_oneshot_lowerhalf.c) -endif() - -if(CONFIG_STM32_FREERUN) - list(APPEND SRCS stm32_freerun.c) -endif() - -if(CONFIG_BUILD_PROTECTED) - list(APPEND SRCS stm32_userspace.c stm32_mpuinit.c) -endif() - -if(CONFIG_STM32_HAVE_IP_I2C_V1) - if(CONFIG_STM32_I2C_ALT) - list(APPEND SRCS stm32_i2c_alt.c) - elseif(CONFIG_STM32_STM32F4XXX) - list(APPEND SRCS stm32f40xxx_i2c.c) - else() - list(APPEND SRCS stm32_i2c.c) - endif() -elseif(CONFIG_STM32_HAVE_IP_I2C_V2) - list(APPEND SRCS stm32_i2c_v2.c) - if(CONFIG_STM32_I2C_SLAVE) - list(APPEND SRCS stm32_i2cslave_v2.c) - endif() -endif() - -if(CONFIG_USBDEV) - if(CONFIG_STM32_USB) - list(APPEND SRCS stm32_usbdev.c) - endif() - if(CONFIG_STM32_USBFS) - list(APPEND SRCS stm32_usbfs.c) - endif() - if(CONFIG_STM32_OTGFS) - list(APPEND SRCS stm32_otgfsdev.c) - endif() - if(CONFIG_STM32_OTGHS) - list(APPEND SRCS stm32_otghsdev.c) - endif() -endif() - -if(CONFIG_STM32_USBHOST) - if(CONFIG_STM32_OTGFS) - list(APPEND SRCS stm32_otgfshost.c) - endif() - if(CONFIG_STM32_OTGHS) - list(APPEND SRCS stm32_otghshost.c) - endif() - if(CONFIG_USBHOST_TRACE) - list(APPEND SRCS stm32_usbhost.c) - else() - if(CONFIG_DEBUG_USB) - list(APPEND SRCS stm32_usbhost.c) - endif() - endif() -endif() - -if(NOT CONFIG_ARCH_IDLE_CUSTOM) - list(APPEND SRCS stm32_idle.c) -endif() - -list(APPEND SRCS stm32_pmstop.c stm32_pmstandby.c stm32_pmsleep.c) - -if(NOT CONFIG_ARCH_CUSTOM_PMINIT) - list(APPEND SRCS stm32_pminitialize.c) -endif() - -if(CONFIG_STM32_ETHMAC) - list(APPEND SRCS stm32_eth.c) -endif() - -if(CONFIG_STM32_PWR) - list(APPEND SRCS stm32_pwr.c stm32_exti_pwr.c) -endif() - -if(CONFIG_STM32_RTC) - list(APPEND SRCS stm32_rtc.c) - if(CONFIG_RTC_ALARM) - list(APPEND SRCS stm32_exti_alarm.c) - endif() - if(CONFIG_RTC_PERIODIC) - list(APPEND SRCS stm32_exti_wakeup.c) - endif() - if(CONFIG_RTC_DRIVER) - list(APPEND SRCS stm32_rtc_lowerhalf.c) - endif() -endif() - -if(CONFIG_STM32_SDADC) - list(APPEND SRCS stm32_sdadc.c) -endif() - -if(CONFIG_STM32_ADC) - list(APPEND SRCS stm32_adc.c) -endif() - -if(CONFIG_STM32_DAC) - list(APPEND SRCS stm32_dac.c) -endif() - -if(CONFIG_STM32_COMP) - list(APPEND SRCS stm32_comp.c) -endif() - -if(CONFIG_STM32_OPAMP) - list(APPEND SRCS stm32_opamp.c) -endif() - -if(CONFIG_STM32_HRTIM) - list(APPEND SRCS stm32_hrtim.c) -endif() - -if(CONFIG_STM32_1WIREDRIVER) - list(APPEND SRCS stm32_1wire.c) -endif() - -if(CONFIG_STM32_HCIUART) - list(APPEND SRCS stm32_hciuart.c) -endif() - -if(CONFIG_STM32_RNG) - list(APPEND SRCS stm32_rng.c) -endif() - -if(CONFIG_STM32_LTDC) - list(APPEND SRCS stm32_ltdc.c) -endif() - -if(CONFIG_STM32_DMA2D) - list(APPEND SRCS stm32_dma2d.c) -endif() - -if(CONFIG_STM32_PWM) - list(APPEND SRCS stm32_pwm.c) -endif() - -if(CONFIG_PULSECOUNT) - list(APPEND SRCS stm32_pulsecount.c) -endif() - -if(CONFIG_STM32_CAP) - list(APPEND SRCS stm32_capture_lowerhalf.c) -endif() - -if(CONFIG_SENSORS_QENCODER) - if(CONFIG_STM32_QE) - list(APPEND SRCS stm32_qencoder.c) - endif() -endif() - -if(CONFIG_SENSORS_HALL3PHASE) - list(APPEND SRCS stm32_hall3ph.c) -endif() - -if(CONFIG_STM32_CAN) - if(CONFIG_STM32_CAN_CHARDRIVER) - list(APPEND SRCS stm32_can.c) - endif() - if(CONFIG_STM32_CAN_SOCKET) - list(APPEND SRCS stm32_can_sock.c) - endif() -endif() - -if(CONFIG_STM32_FDCAN) - if(CONFIG_STM32_FDCAN_CHARDRIVER) - list(APPEND SRCS stm32_fdcan.c) - endif() - if(CONFIG_STM32_FDCAN_SOCKET) - list(APPEND SRCS stm32_fdcan_sock.c) - endif() -endif() - -if(CONFIG_STM32_IWDG) - list(APPEND SRCS stm32_iwdg.c) -endif() - -if(CONFIG_STM32_WWDG) - list(APPEND SRCS stm32_wwdg.c) -endif() - -if(CONFIG_DEBUG_FEATURES) - list(APPEND SRCS stm32_dumpgpio.c) -endif() - -if(CONFIG_STM32_AES) - list(APPEND SRCS stm32_aes.c) -endif() - -if(CONFIG_CRYPTO_CRYPTODEV_HARDWARE) - list(APPEND SRCS stm32_crypto.c) -endif() - -if(CONFIG_STM32_BBSRAM) - list(APPEND SRCS stm32_bbsram.c) -endif() - -if(CONFIG_STM32_FMC) - list(APPEND SRCS stm32_fmc.c) -endif() - -if(CONFIG_STM32_FSMC) - list(APPEND SRCS stm32_fsmc.c) -endif() - -if(CONFIG_STM32_FOC) - list(APPEND SRCS stm32_foc.c) -endif() - -if(CONFIG_STM32_CORDIC) - list(APPEND SRCS stm32_cordic.c) -endif() - -target_sources(arch PRIVATE ${SRCS}) diff --git a/arch/arm/src/stm32/Kconfig b/arch/arm/src/stm32/Kconfig deleted file mode 100644 index f6d7ff5b37e79..0000000000000 --- a/arch/arm/src/stm32/Kconfig +++ /dev/null @@ -1,12450 +0,0 @@ -# -# For a description of the syntax of this configuration file, -# see the file kconfig-language.txt in the NuttX tools repository. -# - -comment "STM32 Configuration Options" - -choice - prompt "STM32 Chip Selection" - default ARCH_CHIP_STM32F103ZE - depends on ARCH_CHIP_STM32 - -config ARCH_CHIP_STM32L151C6 - bool "STM32L151C6" - select STM32_STM32L15XX - select STM32_LOWDENSITY - ---help--- - STM32L 48-pin EnergyLite, 32KB FLASH, 10KB SRAM, 4KB EEPROM - -config ARCH_CHIP_STM32L151C8 - bool "STM32L151C8" - select STM32_STM32L15XX - select STM32_LOWDENSITY - ---help--- - STM32L 48-pin EnergyLite, 64KB FLASH, 10KB SRAM, 4KB EEPROM - -config ARCH_CHIP_STM32L151CB - bool "STM32L151CB" - select STM32_STM32L15XX - select STM32_LOWDENSITY - ---help--- - STM32L 48-pin EnergyLite, 128KB FLASH, 16KB SRAM, 4KB EEPROM - -config ARCH_CHIP_STM32L151R6 - bool "STM32L151R6" - select STM32_STM32L15XX - select STM32_LOWDENSITY - ---help--- - STM32L 64-pin EnergyLite, 32KB FLASH, 10KB SRAM, 4KB EEPROM - -config ARCH_CHIP_STM32L151R8 - bool "STM32L151R8" - select STM32_STM32L15XX - select STM32_LOWDENSITY - ---help--- - STM32L 64-pin EnergyLite, 64KB FLASH, 10KB SRAM, 4KB EEPROM - -config ARCH_CHIP_STM32L151RB - bool "STM32L151RB" - select STM32_STM32L15XX - select STM32_LOWDENSITY - ---help--- - STM32L 64-pin EnergyLite, 128KB FLASH, 16KB SRAM, 4KB EEPROM - -config ARCH_CHIP_STM32L151V6 - bool "STM32L151V6" - select STM32_STM32L15XX - select STM32_LOWDENSITY - ---help--- - STM32L 100-pin EnergyLite, 32KB FLASH, 10KB SRAM, 4KB EEPROM - -config ARCH_CHIP_STM32L151V8 - bool "STM32L151V8" - select STM32_STM32L15XX - select STM32_LOWDENSITY - ---help--- - STM32L 100-pin EnergyLite, 64KB FLASH, 10KB SRAM, 4KB EEPROM - -config ARCH_CHIP_STM32L151VB - bool "STM32L151VB" - select STM32_STM32L15XX - select STM32_LOWDENSITY - ---help--- - STM32L 100-pin EnergyLite, 128KB FLASH, 16KB SRAM, 4KB EEPROM - -config ARCH_CHIP_STM32L152C6 - bool "STM32L152C6" - select STM32_STM32L15XX - select STM32_LOWDENSITY - ---help--- - STM32L 48-pin EnergyLite, 32KB FLASH, 10KB SRAM, 4KB EEPROM with - 4x18 LCD interface - -config ARCH_CHIP_STM32L152C8 - bool "STM32L152C8" - select STM32_STM32L15XX - select STM32_LOWDENSITY - ---help--- - STM32L 48-pin EnergyLite, 64KB FLASH, 10KB SRAM, 4KB EEPROM with - 4x18 LCD interface - -config ARCH_CHIP_STM32L152CB - bool "STM32L152CB" - select STM32_STM32L15XX - select STM32_LOWDENSITY - ---help--- - STM32L 48-pin EnergyLite, 128KB FLASH, 16KB SRAM, 4KB EEPROM with - 4x18 LCD interface - -config ARCH_CHIP_STM32L152R6 - bool "STM32L152R6" - select STM32_STM32L15XX - select STM32_LOWDENSITY - ---help--- - STM32L 64-pin EnergyLite, 32KB FLASH, 10KB SRAM, 4KB EEPROM with - 4x32/8x28 LCD interface - -config ARCH_CHIP_STM32L152R8 - bool "STM32L152R8" - select STM32_STM32L15XX - select STM32_LOWDENSITY - ---help--- - STM32L 64-pin EnergyLite, 64KB FLASH, 10KB SRAM, 4KB EEPROM with - 4x32/8x28 LCD interface - -config ARCH_CHIP_STM32L152RB - bool "STM32L152RB" - select STM32_STM32L15XX - select STM32_LOWDENSITY - ---help--- - STM32L 64-pin EnergyLite, 128KB FLASH, 16KB SRAM, 4KB EEPROM with - 4x32/8x28 LCD interface - -config ARCH_CHIP_STM32L152V6 - bool "STM32L152V6" - select STM32_STM32L15XX - select STM32_LOWDENSITY - ---help--- - STM32L 100-pin EnergyLite, 32KB FLASH, 10KB SRAM, 4KB EEPROM with - 4x44/8x40 LCD interface - -config ARCH_CHIP_STM32L152V8 - bool "STM32L152V8" - select STM32_STM32L15XX - select STM32_LOWDENSITY - ---help--- - STM32L 100-pin EnergyLite, 64KB FLASH, 10KB SRAM, 4KB EEPROM with - 4x44/8x40 LCD interface - -config ARCH_CHIP_STM32L152VB - bool "STM32L152VB" - select STM32_STM32L15XX - select STM32_LOWDENSITY - ---help--- - STM32L 100-pin EnergyLite, 128KB FLASH, 16KB SRAM, 4KB EEPROM with - 4x44/8x40 LCD interface - -config ARCH_CHIP_STM32L152CC - bool "STM32L152CC" - select STM32_STM32L15XX - select STM32_MEDIUMPLUSDENSITY - ---help--- - STM32L 48-pin EnergyLite, 256KB FLASH, 32KB SRAM, 8KB EEPROM with - 4x18 LCD interface - -config ARCH_CHIP_STM32L152RC - bool "STM32L152RC" - select STM32_STM32L15XX - select STM32_MEDIUMPLUSDENSITY - ---help--- - STM32L 64-pin EnergyLite, 256KB FLASH, 32KB SRAM, 8KB EEPROM with - 4x32/8x28 LCD interface - -config ARCH_CHIP_STM32L152VC - bool "STM32L152VC" - select STM32_STM32L15XX - select STM32_MEDIUMPLUSDENSITY - ---help--- - STM32L 100-pin EnergyLite, 256KB FLASH, 32KB SRAM, 8KB EEPROM with - 4x44/8x40 LCD interface - -config ARCH_CHIP_STM32L151RE - bool "STM32L151RE" - select STM32_STM32L15XX - select STM32_HIGHDENSITY - -config ARCH_CHIP_STM32L152RE - bool "STM32L152RE" - select STM32_STM32L15XX - select STM32_HIGHDENSITY - -config ARCH_CHIP_STM32L151VE - bool "STM32L151VE" - select STM32_STM32L15XX - select STM32_HIGHDENSITY - -config ARCH_CHIP_STM32L152VE - bool "STM32L152VE" - select STM32_STM32L15XX - select STM32_HIGHDENSITY - -config ARCH_CHIP_STM32L151QE - bool "STM32L151QE" - select STM32_STM32L15XX - select STM32_HIGHDENSITY - -config ARCH_CHIP_STM32L152QE - bool "STM32L152QE" - select STM32_STM32L15XX - select STM32_HIGHDENSITY - -config ARCH_CHIP_STM32L151ZE - bool "STM32L151ZE" - select STM32_STM32L15XX - select STM32_HIGHDENSITY - -config ARCH_CHIP_STM32L152ZE - bool "STM32L152ZE" - select STM32_STM32L15XX - select STM32_HIGHDENSITY - -config ARCH_CHIP_STM32L162ZD - bool "STM32L162ZD" - select STM32_STM32L15XX - select STM32_HIGHDENSITY - select STM32_HAVE_AES - ---help--- - STM32L 144-pin EnergyLite, 384KB FLASH, 48KB SRAM, 12KB EEPROM with - 4x44/8x40 LCD interface - -config ARCH_CHIP_STM32L162VE - bool "STM32L162VE" - select STM32_STM32L15XX - select STM32_HIGHDENSITY - select STM32_HAVE_AES - ---help--- - STM32L 100-pin EnergyLite, 512KB FLASH, 80KB SRAM, 16KB EEPROM with - 4x44/8x40 LCD interface - -config ARCH_CHIP_STM32F100C8 - bool "STM32F100C8" - select STM32_STM32F10XX - select STM32_VALUELINE - select STM32_MEDIUMDENSITY - select STM32_HAVE_DAC1 - select STM32_HAVE_I2C2 - select STM32_HAVE_TIM4 - -config ARCH_CHIP_STM32F100CB - bool "STM32F100CB" - select STM32_STM32F10XX - select STM32_VALUELINE - select STM32_MEDIUMDENSITY - select STM32_HAVE_DAC1 - select STM32_HAVE_I2C2 - select STM32_HAVE_TIM4 - -config ARCH_CHIP_STM32F100R8 - bool "STM32F100R8" - select STM32_STM32F10XX - select STM32_VALUELINE - select STM32_MEDIUMDENSITY - select STM32_HAVE_DAC1 - select STM32_HAVE_I2C2 - select STM32_HAVE_TIM4 - -config ARCH_CHIP_STM32F100RB - bool "STM32F100RB" - select STM32_STM32F10XX - select STM32_VALUELINE - select STM32_MEDIUMDENSITY - select STM32_HAVE_DAC1 - select STM32_HAVE_I2C2 - select STM32_HAVE_TIM4 - -config ARCH_CHIP_STM32F100RC - bool "STM32F100RC" - select STM32_STM32F10XX - select STM32_VALUELINE - select STM32_HIGHDENSITY - select STM32_HAVE_DAC1 - select STM32_HAVE_I2C2 - select STM32_HAVE_TIM4 - -config ARCH_CHIP_STM32F100RD - bool "STM32F100RD" - select STM32_STM32F10XX - select STM32_VALUELINE - select STM32_HIGHDENSITY - select STM32_HAVE_DAC1 - select STM32_HAVE_I2C2 - select STM32_HAVE_TIM4 - -config ARCH_CHIP_STM32F100RE - bool "STM32F100RE" - select STM32_STM32F10XX - select STM32_VALUELINE - select STM32_HIGHDENSITY - select STM32_HAVE_DAC1 - select STM32_HAVE_I2C2 - select STM32_HAVE_TIM4 - -config ARCH_CHIP_STM32F100V8 - bool "STM32F100V8" - select STM32_STM32F10XX - select STM32_VALUELINE - select STM32_MEDIUMDENSITY - select STM32_HAVE_DAC1 - select STM32_HAVE_I2C2 - select STM32_HAVE_TIM4 - -config ARCH_CHIP_STM32F100VB - bool "STM32F100VB" - select STM32_STM32F10XX - select STM32_VALUELINE - select STM32_MEDIUMDENSITY - select STM32_HAVE_DAC1 - select STM32_HAVE_I2C2 - select STM32_HAVE_TIM4 - -config ARCH_CHIP_STM32F100VC - bool "STM32F100VC" - select STM32_STM32F10XX - select STM32_VALUELINE - select STM32_HIGHDENSITY - select STM32_HAVE_DAC1 - select STM32_HAVE_I2C2 - select STM32_HAVE_TIM4 - -config ARCH_CHIP_STM32F100VD - bool "STM32F100VD" - select STM32_STM32F10XX - select STM32_VALUELINE - select STM32_HIGHDENSITY - select STM32_HAVE_DAC1 - select STM32_HAVE_I2C2 - select STM32_HAVE_TIM4 - -config ARCH_CHIP_STM32F100VE - bool "STM32F100VE" - select STM32_STM32F10XX - select STM32_VALUELINE - select STM32_HIGHDENSITY - select STM32_HAVE_DAC1 - select STM32_HAVE_I2C2 - select STM32_HAVE_TIM4 - -config ARCH_CHIP_STM32F102CB - bool "STM32F102CB" - select STM32_STM32F10XX - select STM32_USBACCESSLINE - select STM32_MEDIUMDENSITY - select STM32_HAVE_I2C2 - select STM32_HAVE_TIM4 - -config ARCH_CHIP_STM32F103T8 - bool "STM32F103T8" - select STM32_STM32F10XX - select STM32_PERFORMANCELINE - select STM32_MEDIUMDENSITY - select STM32_HAVE_TIM4 - -config ARCH_CHIP_STM32F103TB - bool "STM32F103TB" - select STM32_STM32F10XX - select STM32_PERFORMANCELINE - select STM32_MEDIUMDENSITY - select STM32_HAVE_TIM4 - -config ARCH_CHIP_STM32F103C4 - bool "STM32F103C4" - select STM32_STM32F10XX - select STM32_PERFORMANCELINE - select STM32_LOWDENSITY - -config ARCH_CHIP_STM32F103C8 - bool "STM32F103C8" - select STM32_STM32F10XX - select STM32_PERFORMANCELINE - select STM32_MEDIUMDENSITY - select STM32_HAVE_I2C2 - select STM32_HAVE_TIM4 - -config ARCH_CHIP_STM32F103CB - bool "STM32F103CB" - select STM32_STM32F10XX - select STM32_PERFORMANCELINE - select STM32_MEDIUMDENSITY - select STM32_HAVE_I2C2 - select STM32_HAVE_TIM4 - -config ARCH_CHIP_STM32F103R8 - bool "STM32F103R8" - select STM32_STM32F10XX - select STM32_PERFORMANCELINE - select STM32_MEDIUMDENSITY - select STM32_HAVE_I2C2 - select STM32_HAVE_TIM4 - -config ARCH_CHIP_STM32F103RB - bool "STM32F103RB" - select STM32_STM32F10XX - select STM32_PERFORMANCELINE - select STM32_MEDIUMDENSITY - select STM32_HAVE_I2C2 - select STM32_HAVE_TIM4 - -config ARCH_CHIP_STM32F103RC - bool "STM32F103RC" - select STM32_STM32F10XX - select STM32_PERFORMANCELINE - select STM32_HIGHDENSITY - select STM32_HAVE_DAC1 - select STM32_HAVE_I2C2 - select STM32_HAVE_TIM4 - -config ARCH_CHIP_STM32F103RD - bool "STM32F103RD" - select STM32_STM32F10XX - select STM32_PERFORMANCELINE - select STM32_HIGHDENSITY - select STM32_HAVE_DAC1 - select STM32_HAVE_I2C2 - select STM32_HAVE_TIM4 - -config ARCH_CHIP_STM32F103RE - bool "STM32F103RE" - select STM32_STM32F10XX - select STM32_PERFORMANCELINE - select STM32_HIGHDENSITY - select STM32_HAVE_DAC1 - select STM32_HAVE_I2C2 - select STM32_HAVE_TIM4 - -config ARCH_CHIP_STM32F103RG - bool "STM32F103RG" - select STM32_STM32F10XX - select STM32_PERFORMANCELINE - select STM32_HIGHDENSITY - select STM32_HAVE_DAC1 - select STM32_HAVE_I2C2 - select STM32_HAVE_TIM4 - -config ARCH_CHIP_STM32F103V8 - bool "STM32F103V8" - select STM32_STM32F10XX - select STM32_PERFORMANCELINE - select STM32_MEDIUMDENSITY - select STM32_HAVE_I2C2 - select STM32_HAVE_TIM4 - -config ARCH_CHIP_STM32F103VB - bool "STM32F103VB" - select STM32_STM32F10XX - select STM32_PERFORMANCELINE - select STM32_MEDIUMDENSITY - select STM32_HAVE_I2C2 - select STM32_HAVE_TIM4 - -config ARCH_CHIP_STM32F103VC - bool "STM32F103VC" - select STM32_STM32F10XX - select STM32_PERFORMANCELINE - select STM32_HIGHDENSITY - select STM32_HAVE_DAC1 - select STM32_HAVE_I2C2 - select STM32_HAVE_TIM4 - -config ARCH_CHIP_STM32F103VE - bool "STM32F103VE" - select STM32_STM32F10XX - select STM32_PERFORMANCELINE - select STM32_HIGHDENSITY - select STM32_HAVE_DAC1 - select STM32_HAVE_I2C2 - select STM32_HAVE_TIM4 - -config ARCH_CHIP_STM32F103ZE - bool "STM32F103ZE" - select STM32_STM32F10XX - select STM32_PERFORMANCELINE - select STM32_HIGHDENSITY - select STM32_HAVE_DAC1 - select STM32_HAVE_I2C2 - select STM32_HAVE_TIM4 - -config ARCH_CHIP_STM32F105VB - bool "STM32F105VBT7" - select STM32_STM32F10XX - select STM32_CONNECTIVITYLINE - select STM32_HAVE_DAC1 - select STM32_HAVE_I2C2 - select STM32_HAVE_TIM4 - -config ARCH_CHIP_STM32F105RB - bool "STM32F105RB" - select STM32_STM32F10XX - select STM32_CONNECTIVITYLINE - select STM32_HAVE_DAC1 - select STM32_HAVE_I2C2 - select STM32_HAVE_TIM4 - -config ARCH_CHIP_STM32F107VC - bool "STM32F107VC" - select STM32_STM32F10XX - select STM32_CONNECTIVITYLINE - select STM32_HAVE_DAC1 - select STM32_HAVE_TIM4 - -config ARCH_CHIP_STM32F205RG - bool "STM32F205RG" - select STM32_STM32F20XX - select STM32_STM32F205 - -config ARCH_CHIP_STM32F207VC - bool "STM32F207VC" - select STM32_STM32F20XX - select STM32_STM32F207 - -config ARCH_CHIP_STM32F207VE - bool "STM32F207VE" - select STM32_STM32F20XX - select STM32_STM32F207 - -config ARCH_CHIP_STM32F207VF - bool "STM32F207VF" - select STM32_STM32F20XX - select STM32_STM32F207 - -config ARCH_CHIP_STM32F207VG - bool "STM32F207VG" - select STM32_STM32F20XX - select STM32_STM32F207 - -config ARCH_CHIP_STM32F207IC - bool "STM32F207IC" - select STM32_STM32F20XX - select STM32_STM32F207 - -config ARCH_CHIP_STM32F207IE - bool "STM32F207IE" - select STM32_STM32F20XX - select STM32_STM32F207 - -config ARCH_CHIP_STM32F207IF - bool "STM32F207IF" - select STM32_STM32F20XX - select STM32_STM32F207 - -config ARCH_CHIP_STM32F207IG - bool "STM32F207IG" - select STM32_STM32F20XX - select STM32_STM32F207 - -config ARCH_CHIP_STM32F207ZC - bool "STM32F207ZC" - select STM32_STM32F20XX - select STM32_STM32F207 - -config ARCH_CHIP_STM32F207ZE - bool "STM32F207ZE" - select STM32_STM32F20XX - select STM32_STM32F207 - -config ARCH_CHIP_STM32F207ZF - bool "STM32F207ZF" - select STM32_STM32F20XX - select STM32_STM32F207 - -config ARCH_CHIP_STM32F207ZG - bool "STM32F207ZG" - select STM32_STM32F20XX - select STM32_STM32F207 - -config ARCH_CHIP_STM32F302K6 - bool "STM32F302K6" - select STM32_STM32F30XX - select STM32_STM32F302 - select STM32_HAVE_I2C3 - -config ARCH_CHIP_STM32F302K8 - bool "STM32F302K8" - select STM32_STM32F30XX - select STM32_STM32F302 - select STM32_HAVE_I2C3 - -config ARCH_CHIP_STM32F302C6 - bool "STM32F302C6" - select STM32_STM32F30XX - select STM32_STM32F302 - -config ARCH_CHIP_STM32F302C8 - bool "STM32F302C8" - select STM32_STM32F30XX - select STM32_STM32F302 - -config ARCH_CHIP_STM32F302R6 - bool "STM32F302R6" - select STM32_STM32F30XX - select STM32_STM32F302 - -config ARCH_CHIP_STM32F302R8 - bool "STM32F302R8" - select STM32_STM32F30XX - select STM32_STM32F302 - -config ARCH_CHIP_STM32F302CB - bool "STM32F302CB" - select STM32_STM32F30XX - select STM32_STM32F302 - select STM32_HAVE_ADC2 - select STM32_HAVE_USART3 - -config ARCH_CHIP_STM32F302CC - bool "STM32F302CC" - select STM32_STM32F30XX - select STM32_STM32F302 - select STM32_HAVE_ADC2 - select STM32_HAVE_USART3 - -config ARCH_CHIP_STM32F302RB - bool "STM32F302RB" - select STM32_STM32F30XX - select STM32_STM32F302 - select STM32_HAVE_ADC2 - select STM32_HAVE_USART3 - select STM32_HAVE_UART4 - select STM32_HAVE_UART5 - -config ARCH_CHIP_STM32F302RC - bool "STM32F302RC" - select STM32_STM32F30XX - select STM32_STM32F302 - select STM32_HAVE_ADC2 - select STM32_HAVE_USART3 - select STM32_HAVE_UART4 - select STM32_HAVE_UART5 - -config ARCH_CHIP_STM32F302VB - bool "STM32F302VB" - select STM32_STM32F30XX - select STM32_STM32F302 - select STM32_HAVE_ADC2 - select STM32_HAVE_USART3 - select STM32_HAVE_UART4 - select STM32_HAVE_UART5 - -config ARCH_CHIP_STM32F302VC - bool "STM32F302VC" - select STM32_STM32F30XX - select STM32_STM32F302 - select STM32_HAVE_ADC2 - select STM32_HAVE_USART3 - select STM32_HAVE_UART4 - select STM32_HAVE_UART5 - -config ARCH_CHIP_STM32F303K6 - bool "STM32F303K6" - select STM32_STM32F30XX - select STM32_STM32F303 - select STM32_HAVE_DAC2 - -config ARCH_CHIP_STM32F303K8 - bool "STM32F303K8" - select STM32_STM32F30XX - select STM32_STM32F303 - select STM32_HAVE_DAC2 - -config ARCH_CHIP_STM32F303C6 - bool "STM32F303C6" - select STM32_STM32F30XX - select STM32_STM32F303 - select STM32_HAVE_DAC2 - select STM32_HAVE_USART3 - -config ARCH_CHIP_STM32F303C8 - bool "STM32F303C8" - select STM32_STM32F30XX - select STM32_STM32F303 - select STM32_HAVE_DAC2 - select STM32_HAVE_USART3 - -config ARCH_CHIP_STM32F303CB - bool "STM32F303CB" - select STM32_STM32F30XX - select STM32_STM32F303 - select STM32_HAVE_ADC3 - select STM32_HAVE_ADC4 - select STM32_HAVE_I2C2 - select STM32_HAVE_SPI2 - select STM32_HAVE_SPI3 - select STM32_HAVE_TIM4 - select STM32_HAVE_TIM8 - select STM32_HAVE_USART3 - select STM32_HAVE_USBDEV - -config ARCH_CHIP_STM32F303CC - bool "STM32F303CC" - select STM32_STM32F30XX - select STM32_STM32F303 - select STM32_HAVE_ADC3 - select STM32_HAVE_ADC4 - select STM32_HAVE_I2C2 - select STM32_HAVE_SPI2 - select STM32_HAVE_SPI3 - select STM32_HAVE_TIM4 - select STM32_HAVE_TIM8 - select STM32_HAVE_USART3 - select STM32_HAVE_USBDEV - -config ARCH_CHIP_STM32F303RB - bool "STM32F303RB" - select STM32_STM32F30XX - select STM32_STM32F303 - select STM32_HAVE_ADC3 - select STM32_HAVE_ADC4 - select STM32_HAVE_I2C2 - select STM32_HAVE_SPI2 - select STM32_HAVE_SPI3 - select STM32_HAVE_TIM4 - select STM32_HAVE_TIM8 - select STM32_HAVE_USART3 - select STM32_HAVE_UART4 - select STM32_HAVE_UART5 - select STM32_HAVE_USBDEV - -config ARCH_CHIP_STM32F303RC - bool "STM32F303RC" - select STM32_STM32F30XX - select STM32_STM32F303 - select STM32_HAVE_ADC3 - select STM32_HAVE_ADC4 - select STM32_HAVE_I2C2 - select STM32_HAVE_SPI2 - select STM32_HAVE_SPI3 - select STM32_HAVE_TIM4 - select STM32_HAVE_TIM8 - select STM32_HAVE_USART3 - select STM32_HAVE_UART4 - select STM32_HAVE_UART5 - select STM32_HAVE_USBDEV - -config ARCH_CHIP_STM32F303RD - bool "STM32F303RD" - select STM32_STM32F30XX - select STM32_STM32F303 - select STM32_HAVE_ADC3 - select STM32_HAVE_ADC4 - select STM32_HAVE_I2C2 - select STM32_HAVE_I2C3 - select STM32_HAVE_SPI2 - select STM32_HAVE_SPI3 - select STM32_HAVE_SPI4 - select STM32_HAVE_TIM4 - select STM32_HAVE_TIM8 - select STM32_HAVE_USART3 - select STM32_HAVE_UART4 - select STM32_HAVE_UART5 - select STM32_HAVE_USBDEV - -config ARCH_CHIP_STM32F303RE - bool "STM32F303RE" - select STM32_STM32F30XX - select STM32_STM32F303 - select STM32_HAVE_ADC3 - select STM32_HAVE_ADC4 - select STM32_HAVE_I2C2 - select STM32_HAVE_I2C3 - select STM32_HAVE_SPI2 - select STM32_HAVE_SPI3 - select STM32_HAVE_SPI4 - select STM32_HAVE_TIM4 - select STM32_HAVE_TIM8 - select STM32_HAVE_USART3 - select STM32_HAVE_UART4 - select STM32_HAVE_UART5 - select STM32_HAVE_USBDEV - -config ARCH_CHIP_STM32F303VB - bool "STM32F303VB" - select STM32_STM32F30XX - select STM32_STM32F303 - select STM32_HAVE_ADC3 - select STM32_HAVE_ADC4 - select STM32_HAVE_I2C2 - select STM32_HAVE_SPI2 - select STM32_HAVE_SPI3 - select STM32_HAVE_TIM4 - select STM32_HAVE_TIM8 - select STM32_HAVE_USART3 - select STM32_HAVE_UART4 - select STM32_HAVE_UART5 - select STM32_HAVE_USBDEV - -config ARCH_CHIP_STM32F303VC - bool "STM32F303VC" - select STM32_STM32F30XX - select STM32_STM32F303 - select STM32_HAVE_ADC3 - select STM32_HAVE_ADC4 - select STM32_HAVE_I2C2 - select STM32_HAVE_SPI2 - select STM32_HAVE_SPI3 - select STM32_HAVE_TIM4 - select STM32_HAVE_TIM8 - select STM32_HAVE_USART3 - select STM32_HAVE_UART4 - select STM32_HAVE_UART5 - select STM32_HAVE_USBDEV - -config ARCH_CHIP_STM32F303VD - bool "STM32F303VD" - select STM32_STM32F30XX - select STM32_STM32F303 - select STM32_HAVE_ADC3 - select STM32_HAVE_ADC4 - select STM32_HAVE_USART3 - -config ARCH_CHIP_STM32F303VE - bool "STM32F303VE" - select STM32_STM32F30XX - select STM32_STM32F303 - select STM32_HAVE_ADC3 - select STM32_HAVE_ADC4 - select STM32_HAVE_USART3 - -config ARCH_CHIP_STM32F303ZD - bool "STM32F303ZD" - select STM32_STM32F30XX - select STM32_STM32F303 - select STM32_HAVE_ADC3 - select STM32_HAVE_ADC4 - select STM32_HAVE_USART3 - -config ARCH_CHIP_STM32F303ZE - bool "STM32F303ZE" - select STM32_STM32F30XX - select STM32_STM32F303 - select STM32_HAVE_ADC3 - select STM32_HAVE_ADC4 - select STM32_HAVE_USART3 - -config ARCH_CHIP_STM32F334K4 - bool "STM32F334K4" - select STM32_STM32F33XX - -config ARCH_CHIP_STM32F334K6 - bool "STM32F334K6" - select STM32_STM32F33XX - -config ARCH_CHIP_STM32F334K8 - bool "STM32F334K8" - select STM32_STM32F33XX - -config ARCH_CHIP_STM32F334C4 - bool "STM32F334C4" - select STM32_STM32F33XX - -config ARCH_CHIP_STM32F334C6 - bool "STM32F334C6" - select STM32_STM32F33XX - -config ARCH_CHIP_STM32F334C8 - bool "STM32F334C8" - select STM32_STM32F33XX - -config ARCH_CHIP_STM32F334R4 - bool "STM32F334R4" - select STM32_STM32F33XX - -config ARCH_CHIP_STM32F334R6 - bool "STM32F334R6" - select STM32_STM32F33XX - -config ARCH_CHIP_STM32F334R8 - bool "STM32F334R8" - select STM32_STM32F33XX - -config ARCH_CHIP_STM32F372C8 - bool "STM32F372C8" - select STM32_STM32F37XX - -config ARCH_CHIP_STM32F372R8 - bool "STM32F372R8" - select STM32_STM32F37XX - -config ARCH_CHIP_STM32F372V8 - bool "STM32F372V8" - select STM32_STM32F37XX - -config ARCH_CHIP_STM32F372CB - bool "STM32F372CB" - select STM32_STM32F37XX - -config ARCH_CHIP_STM32F372RB - bool "STM32F372RB" - select STM32_STM32F37XX - -config ARCH_CHIP_STM32F372VB - bool "STM32F372VB" - select STM32_STM32F37XX - -config ARCH_CHIP_STM32F372CC - bool "STM32F372CC" - select STM32_STM32F37XX - -config ARCH_CHIP_STM32F372RC - bool "STM32F372RC" - select STM32_STM32F37XX - -config ARCH_CHIP_STM32F372VC - bool "STM32F372VC" - select STM32_STM32F37XX - -config ARCH_CHIP_STM32F373C8 - bool "STM32F373C8" - select STM32_STM32F37XX - -config ARCH_CHIP_STM32F373R8 - bool "STM32F373R8" - select STM32_STM32F37XX - -config ARCH_CHIP_STM32F373V8 - bool "STM32F373V8" - select STM32_STM32F37XX - -config ARCH_CHIP_STM32F373CB - bool "STM32F373CB" - select STM32_STM32F37XX - -config ARCH_CHIP_STM32F373RB - bool "STM32F373RB" - select STM32_STM32F37XX - -config ARCH_CHIP_STM32F373VB - bool "STM32F373VB" - select STM32_STM32F37XX - -config ARCH_CHIP_STM32F373CC - bool "STM32F373CC" - select STM32_STM32F37XX - -config ARCH_CHIP_STM32F373RC - bool "STM32F373RC" - select STM32_STM32F37XX - -config ARCH_CHIP_STM32F373VC - bool "STM32F373VC" - select STM32_STM32F37XX - -config ARCH_CHIP_STM32F401CB - bool "STM32F401CB" - select STM32_STM32F401xBC - -config ARCH_CHIP_STM32F401RB - bool "STM32F401RB" - select STM32_STM32F401xBC - -config ARCH_CHIP_STM32F401VB - bool "STM32F401VB" - select STM32_STM32F401xBC - -config ARCH_CHIP_STM32F401CC - bool "STM32F401CC" - select STM32_STM32F401xBC - -config ARCH_CHIP_STM32F401RC - bool "STM32F401RC" - select STM32_STM32F401xBC - -config ARCH_CHIP_STM32F401VC - bool "STM32F401VC" - select STM32_STM32F401xBC - -config ARCH_CHIP_STM32F401CD - bool "STM32F401CD" - select STM32_STM32F401xDE - -config ARCH_CHIP_STM32F401RD - bool "STM32F401RD" - select STM32_STM32F401xDE - -config ARCH_CHIP_STM32F401VD - bool "STM32F401VD" - select STM32_STM32F401xDE - -config ARCH_CHIP_STM32F401CE - bool "STM32F401CE" - select STM32_STM32F401xDE - -config ARCH_CHIP_STM32F401RE - bool "STM32F401RE" - select STM32_STM32F401xDE - -config ARCH_CHIP_STM32F401VE - bool "STM32F401VE" - select STM32_STM32F401xDE - -config ARCH_CHIP_STM32F410RB - bool "STM32F410RB" - select STM32_STM32F4XXX - select STM32_STM32F410 - -config ARCH_CHIP_STM32F411CE - bool "STM32F411CE" - select STM32_STM32F4XXX - select STM32_STM32F411 - -config ARCH_CHIP_STM32F411RE - bool "STM32F411RE" - select STM32_STM32F4XXX - select STM32_STM32F411 - -config ARCH_CHIP_STM32F411VE - bool "STM32F411VE" - select STM32_STM32F4XXX - select STM32_STM32F411 - -config ARCH_CHIP_STM32F412CE - bool "STM32F412CE" - select STM32_STM32F4XXX - select STM32_STM32F412 - -config ARCH_CHIP_STM32F412ZG - bool "STM32F412ZG" - select STM32_STM32F4XXX - select STM32_STM32F412 - -config ARCH_CHIP_STM32F405RG - bool "STM32F405RG" - select STM32_STM32F4XXX - select STM32_STM32F405 - -config ARCH_CHIP_STM32F405VG - bool "STM32F405VG" - select STM32_STM32F4XXX - select STM32_STM32F405 - -config ARCH_CHIP_STM32F405ZG - bool "STM32F405ZG" - select STM32_STM32F4XXX - select STM32_STM32F405 - -config ARCH_CHIP_STM32F407VE - bool "STM32F407VE" - select STM32_STM32F4XXX - select STM32_STM32F407 - -config ARCH_CHIP_STM32F407VG - bool "STM32F407VG" - select STM32_STM32F4XXX - select STM32_STM32F407 - -config ARCH_CHIP_STM32F407ZE - bool "STM32F407ZE" - select STM32_STM32F4XXX - select STM32_STM32F407 - -config ARCH_CHIP_STM32F407ZG - bool "STM32F407ZG" - select STM32_STM32F4XXX - select STM32_STM32F407 - -config ARCH_CHIP_STM32F407IE - bool "STM32F407IE" - select STM32_STM32F4XXX - select STM32_STM32F407 - -config ARCH_CHIP_STM32F407IG - bool "STM32F407IG" - select STM32_STM32F4XXX - select STM32_STM32F407 - -config ARCH_CHIP_STM32F427V - bool "STM32F427V" - select STM32_STM32F4XXX - select STM32_STM32F427 - -config ARCH_CHIP_STM32F427Z - bool "STM32F427Z" - select STM32_STM32F4XXX - select STM32_STM32F427 - -config ARCH_CHIP_STM32F427I - bool "STM32F427I" - select STM32_STM32F4XXX - select STM32_STM32F427 - -config ARCH_CHIP_STM32F429V - bool "STM32F429V" - select STM32_STM32F4XXX - select STM32_STM32F429 - -config ARCH_CHIP_STM32F429Z - bool "STM32F429Z" - select STM32_STM32F4XXX - select STM32_STM32F429 - -config ARCH_CHIP_STM32F429I - bool "STM32F429I" - select STM32_STM32F4XXX - select STM32_STM32F429 - -config ARCH_CHIP_STM32F429B - bool "STM32F429B" - select STM32_STM32F4XXX - select STM32_STM32F429 - -config ARCH_CHIP_STM32F429N - bool "STM32F429N" - select STM32_STM32F4XXX - select STM32_STM32F429 - -config ARCH_CHIP_STM32F446M - bool "STM32F446M" - select STM32_STM32F4XXX - select STM32_STM32F446 - -config ARCH_CHIP_STM32F446R - bool "STM32F446R" - select STM32_STM32F4XXX - select STM32_STM32F446 - -config ARCH_CHIP_STM32F446V - bool "STM32F446V" - select STM32_STM32F4XXX - select STM32_STM32F446 - -config ARCH_CHIP_STM32F446Z - bool "STM32F446Z" - select STM32_STM32F4XXX - select STM32_STM32F446 - -config ARCH_CHIP_STM32F469A - bool "STM32F469A" - select STM32_STM32F4XXX - select STM32_STM32F469 - -config ARCH_CHIP_STM32F469I - bool "STM32F469I" - select STM32_STM32F4XXX - select STM32_STM32F469 - select STM32_HAVE_ETHMAC - -config ARCH_CHIP_STM32F469B - bool "STM32F469B" - select STM32_STM32F4XXX - select STM32_STM32F469 - select STM32_HAVE_ETHMAC - -config ARCH_CHIP_STM32F469N - bool "STM32F469N" - select STM32_STM32F4XXX - select STM32_STM32F469 - select STM32_HAVE_ETHMAC - -config ARCH_CHIP_STM32G431K - bool "STM32G431K" - select STM32_STM32G43XX - select STM32_STM32G4XXK - select STM32_STM32G431K - -config ARCH_CHIP_STM32G431C - bool "STM32G431C" - select STM32_STM32G43XX - select STM32_STM32G4XXC - select STM32_STM32G431C - -config ARCH_CHIP_STM32G431R - bool "STM32G431R" - select STM32_STM32G43XX - select STM32_STM32G4XXR - select STM32_STM32G431R - -config ARCH_CHIP_STM32G431M - bool "STM32G431M" - select STM32_STM32G43XX - select STM32_STM32G4XXM - select STM32_STM32G431M - -config ARCH_CHIP_STM32G431V - bool "STM32G431V" - select STM32_STM32G43XX - select STM32_STM32G4XXV - select STM32_STM32G431V - -config ARCH_CHIP_STM32G474C - bool "STM32G474C" - select STM32_STM32G47XX - select STM32_STM32G4XXC - select STM32_STM32G474C - -config ARCH_CHIP_STM32G474M - bool "STM32G474M" - select STM32_STM32G47XX - select STM32_STM32G4XXM - select STM32_STM32G474M - -config ARCH_CHIP_STM32G474R - bool "STM32G474R" - select STM32_STM32G47XX - select STM32_STM32G4XXR - select STM32_STM32G474R - select STM32_HAVE_USBFS - -config ARCH_CHIP_STM32G474Q - bool "STM32G474Q" - select STM32_STM32G47XX - select STM32_STM32G4XXQ - select STM32_STM32G474Q - -config ARCH_CHIP_STM32G474V - bool "STM32G474V" - select STM32_STM32G47XX - select STM32_STM32G4XXV - select STM32_STM32G474V - -endchoice - -choice - prompt "Override Flash Size Designator" - default STM32_FLASH_CONFIG_DEFAULT - depends on ARCH_CHIP_STM32 - ---help--- - STM32F/STM32G/STM32L series parts numbering (sans the package type) - ends with a number or letter that designates the FLASH size. - - Designator Size in KiB - 4 16 - 6 32 - 8 64 - B 128 - Z 192 - C 256 - D 384 - E 512 - F 768 - G 1024 - I 2048 - - This configuration option defaults to using the configuration based - on that designator or the default smaller size if there is no last - character designator is present in the STM32 Chip Selection. - - Examples: - If the STM32F407VE is chosen, the Flash configuration would be - 'E', if a variant of the part with a 2048 KiB Flash is released - in the future one could simply select the 'I' designator here. - - If an STM32F42xxx or Series parts is chosen the default Flash - configuration will be 'G' and can be set herein to 'I' to choose - the larger FLASH part. - -config STM32_FLASH_CONFIG_DEFAULT - bool "Default" - -config STM32_FLASH_CONFIG_4 - bool "4 16KiB" - -config STM32_FLASH_CONFIG_6 - bool "6 32KiB" - -config STM32_FLASH_CONFIG_8 - bool "8 64KiB" - -config STM32_FLASH_CONFIG_B - bool "B 128KiB" - -config STM32_FLASH_CONFIG_Z - bool "Z 192KiB" - -config STM32_FLASH_CONFIG_C - bool "C 256KiB" - -config STM32_FLASH_CONFIG_D - bool "D 384KiB" - -config STM32_FLASH_CONFIG_E - bool "E 512KiB" - -config STM32_FLASH_CONFIG_F - bool "F 768KiB" - -config STM32_FLASH_CONFIG_G - bool "G 1024KiB" - -config STM32_FLASH_CONFIG_I - bool "I 2048KiB" - -endchoice - -# This is really 15XX/16XX, but we treat the two the same. -config STM32_STM32L15XX - bool - default n - select ARCH_CORTEXM3 - select STM32_ENERGYLITE - select STM32_HAVE_USBDEV - select STM32_HAVE_DAC1 - select STM32_HAVE_I2C2 - select STM32_HAVE_SPI2 - select STM32_HAVE_SPI3 - select STM32_HAVE_TIM3 - select STM32_HAVE_TIM4 - select STM32_HAVE_TIM9 - select STM32_HAVE_TIM10 - select STM32_HAVE_TIM11 - select STM32_HAVE_ADC2 - select STM32_HAVE_USART3 - select STM32_HAVE_RTC_SUBSECONDS if !STM32_LOWDENSITY - select STM32_HAVE_IP_DBGMCU_V2 - select STM32_HAVE_IP_TIMERS_V1 - select STM32_HAVE_IP_ADC_V1 - select STM32_HAVE_IP_DAC_V1 - select STM32_HAVE_IP_DMA_V1 - select STM32_HAVE_IP_I2C_V1 - -config STM32_ENERGYLITE - bool - default n - select STM32_HAVE_TIM6 - select STM32_HAVE_TIM7 - -config STM32_STM32F10XX - bool - default n - select ARCH_CORTEXM3 - select STM32_HAVE_SPI2 if STM32_HIGHDENSITY || STM32_MEDIUMDENSITY - select STM32_HAVE_SPI3 if STM32_HIGHDENSITY || STM32_MEDIUMDENSITY - select STM32_HAVE_RTC_COUNTER - select STM32_HAVE_TIM3 - select STM32_HAVE_IP_DBGMCU_V1 - select STM32_HAVE_IP_TIMERS_V1 - select STM32_HAVE_IP_ADC_V1_BASIC - select STM32_HAVE_IP_DAC_V1 - select STM32_HAVE_IP_DMA_V1 - select STM32_HAVE_IP_I2C_V1 - -config STM32_VALUELINE - bool - default n - select STM32_HAVE_USART3 - select STM32_HAVE_UART4 - select STM32_HAVE_UART5 - select STM32_HAVE_TIM1 - select STM32_HAVE_TIM5 - select STM32_HAVE_TIM6 - select STM32_HAVE_TIM7 - select STM32_HAVE_TIM12 - select STM32_HAVE_TIM13 - select STM32_HAVE_TIM14 - select STM32_HAVE_TIM15 - select STM32_HAVE_TIM16 - select STM32_HAVE_TIM17 - select STM32_HAVE_SPI2 if STM32_HIGHDENSITY - select STM32_HAVE_SPI3 if STM32_HIGHDENSITY - -config STM32_CONNECTIVITYLINE - bool - default n - select STM32_HAVE_OTGFS - select STM32_HAVE_USART3 - select STM32_HAVE_UART4 - select STM32_HAVE_UART5 - select STM32_HAVE_TIM1 - select STM32_HAVE_TIM5 - select STM32_HAVE_TIM6 - select STM32_HAVE_TIM7 - select STM32_HAVE_ADC2 - select STM32_HAVE_CAN1 - select STM32_HAVE_CAN2 - select STM32_HAVE_ETHMAC - select STM32_HAVE_SPI2 - select STM32_HAVE_SPI3 - -config STM32_PERFORMANCELINE - bool - default n - select STM32_HAVE_USBDEV - select STM32_HAVE_USART3 - select STM32_HAVE_UART4 - select STM32_HAVE_UART5 - select STM32_HAVE_TIM1 - select STM32_HAVE_TIM5 - select STM32_HAVE_TIM6 - select STM32_HAVE_TIM7 - select STM32_HAVE_TIM8 - select STM32_HAVE_ADC2 - select STM32_HAVE_CAN1 - -config STM32_USBACCESSLINE - bool - default n - select STM32_HAVE_USBDEV - select STM32_HAVE_FSMC - select STM32_HAVE_USART3 - select STM32_HAVE_SPI2 - -config STM32_MEDIUMPLUSDENSITY - bool - default n - -config STM32_HIGHDENSITY - bool - default n - select STM32_HAVE_FSMC - select STM32_HAVE_USART3 - select STM32_HAVE_UART4 - select STM32_HAVE_UART5 - select STM32_HAVE_TIM1 - select STM32_HAVE_TIM5 - select STM32_HAVE_TIM6 - select STM32_HAVE_TIM7 - select STM32_HAVE_TIM8 - select STM32_HAVE_ADC2 - select STM32_HAVE_ADC3 - select STM32_HAVE_CAN1 - -config STM32_MEDIUMDENSITY - bool - default n - select STM32_HAVE_USART3 - select STM32_HAVE_UART4 - select STM32_HAVE_UART5 - select STM32_HAVE_TIM1 - select STM32_HAVE_TIM5 - select STM32_HAVE_TIM6 - select STM32_HAVE_TIM7 - select STM32_HAVE_TIM8 - select STM32_HAVE_ADC2 - select STM32_HAVE_ADC3 - select STM32_HAVE_CAN1 - -config STM32_LOWDENSITY - bool - default n - select STM32_HAVE_USART3 - select STM32_HAVE_UART4 - select STM32_HAVE_UART5 - select STM32_HAVE_TIM1 - select STM32_HAVE_TIM5 - select STM32_HAVE_TIM6 - select STM32_HAVE_TIM7 - select STM32_HAVE_TIM8 - select STM32_HAVE_ADC2 - select STM32_HAVE_CAN1 if !STM32_VALUELINE - -config STM32_STM32F20XX - bool - default n - select ARCH_CORTEXM3 - select STM32_HAVE_FLASH_ICACHE - select STM32_HAVE_FLASH_DCACHE - select STM32_HAVE_CRYP - select STM32_HAVE_OTGFS - select STM32_HAVE_OTGHS - select STM32_HAVE_USART3 - select STM32_HAVE_UART4 - select STM32_HAVE_UART5 - select STM32_HAVE_USART6 - select STM32_HAVE_TIM1 - select STM32_HAVE_TIM3 - select STM32_HAVE_TIM4 - select STM32_HAVE_TIM5 - select STM32_HAVE_TIM6 - select STM32_HAVE_TIM7 - select STM32_HAVE_TIM8 - select STM32_HAVE_TIM9 - select STM32_HAVE_TIM10 - select STM32_HAVE_TIM11 - select STM32_HAVE_TIM12 - select STM32_HAVE_TIM13 - select STM32_HAVE_TIM14 - select STM32_HAVE_ADC2 - select STM32_HAVE_ADC3 - select STM32_HAVE_DAC1 - select STM32_HAVE_I2C2 - select STM32_HAVE_I2C3 - select STM32_HAVE_CAN1 - select STM32_HAVE_CAN2 - select STM32_HAVE_RNG - select STM32_HAVE_SPI2 - select STM32_HAVE_SPI3 - select STM32_HAVE_IOCOMPENSATION - select STM32_HAVE_IP_DBGMCU_V2 - select STM32_HAVE_IP_TIMERS_V1 - select STM32_HAVE_IP_ADC_V1 - select STM32_HAVE_IP_DAC_V1 - select STM32_HAVE_IP_DMA_V2 - select STM32_HAVE_IP_I2C_V1 - -config STM32_STM32F205 - bool - default n - -config STM32_STM32F207 - bool - default n - select STM32_HAVE_FSMC - select STM32_HAVE_ETHMAC - -config STM32_STM32F30XX - bool - default n - select ARCH_CORTEXM4 - select ARCH_HAVE_FPU - select STM32_HAVE_ADC1_DMA - select STM32_HAVE_CAN1 - select STM32_HAVE_DAC1 - select STM32_HAVE_TIM1 - select STM32_HAVE_TIM3 - select STM32_HAVE_TIM6 - select STM32_HAVE_TIM15 - select STM32_HAVE_TIM16 - select STM32_HAVE_TIM17 - select STM32_HAVE_TSC - select STM32_HAVE_IP_DBGMCU_V2 - select STM32_HAVE_IP_TIMERS_V2 - select STM32_HAVE_IP_ADC_V2 - select STM32_HAVE_IP_DAC_V1 - select STM32_HAVE_IP_DMA_V1 - select STM32_HAVE_IP_I2C_V2 - -config STM32_STM32F302 - bool - default n - select STM32_HAVE_ADC2 - select STM32_HAVE_ADC2_DMA - select STM32_HAVE_I2C2 - select STM32_HAVE_SPI2 - select STM32_HAVE_SPI3 - select STM32_HAVE_TIM4 - select STM32_HAVE_USBDEV - -config STM32_STM32F303 - bool - default n - select STM32_HAVE_ADC2 - select STM32_HAVE_ADC2_DMA - select STM32_HAVE_CCM - select STM32_HAVE_TIM7 - -config STM32_STM32F33XX - bool - default n - select ARCH_CORTEXM4 - select ARCH_HAVE_FPU - select STM32_HAVE_HRTIM1 - select STM32_HAVE_HRTIM1_PLLCLK - select STM32_HAVE_COMP2 - select STM32_HAVE_COMP4 - select STM32_HAVE_COMP6 - select STM32_HAVE_OPAMP2 - select STM32_HAVE_CCM - select STM32_HAVE_TIM1 - select STM32_HAVE_TIM6 - select STM32_HAVE_TIM7 - select STM32_HAVE_TIM15 - select STM32_HAVE_TIM16 - select STM32_HAVE_TIM17 - select STM32_HAVE_TSC - select STM32_HAVE_ADC2 - select STM32_HAVE_ADC1_DMA - select STM32_HAVE_ADC2_DMA - select STM32_HAVE_CAN1 - select STM32_HAVE_DAC1 - select STM32_HAVE_DAC2 - select STM32_HAVE_USART3 - select STM32_HAVE_IP_DBGMCU_V2 - select STM32_HAVE_IP_TIMERS_V2 - select STM32_HAVE_IP_ADC_V2 - select STM32_HAVE_IP_COMP_V1 - select STM32_HAVE_IP_DAC_V1 - select STM32_HAVE_IP_DMA_V1 - select STM32_HAVE_IP_I2C_V2 - -config STM32_STM32F37XX - bool - default n - select ARCH_CORTEXM4 - select ARCH_HAVE_FPU - select STM32_HAVE_USBDEV - select STM32_HAVE_TIM3 - select STM32_HAVE_TIM4 - select STM32_HAVE_TIM5 - select STM32_HAVE_TIM6 - select STM32_HAVE_TIM7 - select STM32_HAVE_TIM15 - select STM32_HAVE_TIM16 - select STM32_HAVE_TIM17 - select STM32_HAVE_TSC - select STM32_HAVE_SDADC1 - select STM32_HAVE_SDADC2 - select STM32_HAVE_SDADC3 - select STM32_HAVE_CAN1 - select STM32_HAVE_DAC1 - select STM32_HAVE_DAC2 - select STM32_HAVE_I2C2 - select STM32_HAVE_SPI2 - select STM32_HAVE_SPI3 - select STM32_HAVE_USART3 - select STM32_HAVE_IP_TIMERS_V1 - select STM32_HAVE_IP_ADC_V1_BASIC - select STM32_HAVE_IP_DAC_V1 - select STM32_HAVE_IP_DMA_V1 - select STM32_HAVE_IP_I2C_V2 - -config STM32_STM32F4XXX - bool - default n - select ARCH_CORTEXM4 - select ARCH_HAVE_FPU - select STM32_HAVE_FLASH_ICACHE - select STM32_HAVE_FLASH_DCACHE - select STM32_HAVE_CRYP - select STM32_HAVE_SPI2 - select STM32_HAVE_I2C2 - select STM32_HAVE_IOCOMPENSATION - select STM32_HAVE_IP_DBGMCU_V2 - select STM32_HAVE_IP_TIMERS_V1 - select STM32_HAVE_IP_ADC_V1 - select STM32_HAVE_IP_DAC_V1 - select STM32_HAVE_IP_DMA_V2 - select STM32_HAVE_IP_I2C_V1 - -config STM32_STM32F401xBC - bool - default n - select STM32_STM32F401 - -config STM32_STM32F401xDE - bool - default n - select STM32_STM32F401 - -config STM32_STM32F401 - bool - default n - select ARCH_CORTEXM4 - select STM32_STM32F4XXX - select STM32_HAVE_USART6 - select STM32_HAVE_TIM1 - select STM32_HAVE_TIM3 - select STM32_HAVE_TIM4 - select STM32_HAVE_TIM5 - select STM32_HAVE_TIM9 - select STM32_HAVE_TIM10 - select STM32_HAVE_TIM11 - select STM32_HAVE_SPI2 - select STM32_HAVE_SPI3 - select STM32_HAVE_I2S3 - select STM32_HAVE_I2C3 - select STM32_HAVE_OTGFS - -config STM32_STM32F410 - bool - default n - select STM32_HAVE_USART6 - select STM32_HAVE_TIM1 - select STM32_HAVE_TIM5 - select STM32_HAVE_TIM6 - select STM32_HAVE_TIM9 - select STM32_HAVE_TIM11 - select STM32_HAVE_SPI5 - select STM32_HAVE_DAC1 - -config STM32_STM32F411 - bool - default n - select STM32_HAVE_USART6 - select STM32_HAVE_TIM1 - select STM32_HAVE_TIM3 - select STM32_HAVE_TIM4 - select STM32_HAVE_TIM5 - select STM32_HAVE_TIM9 - select STM32_HAVE_TIM10 - select STM32_HAVE_TIM11 - select STM32_HAVE_SPI2 - select STM32_HAVE_SPI3 - select STM32_HAVE_SPI4 - select STM32_HAVE_SPI5 - select STM32_HAVE_I2S3 - select STM32_HAVE_I2C3 - select STM32_HAVE_OTGFS - -config STM32_STM32F412 - bool - default n - select STM32_HAVE_TIM1 - select STM32_HAVE_TIM2 - select STM32_HAVE_TIM3 - select STM32_HAVE_TIM4 - select STM32_HAVE_TIM5 - select STM32_HAVE_TIM8 - select STM32_HAVE_TIM9 - select STM32_HAVE_TIM12 - select STM32_HAVE_TIM13 - select STM32_HAVE_TIM14 - select STM32_HAVE_USART3 - select STM32_HAVE_USART2 - select STM32_HAVE_USART6 - select STM32_HAVE_I2C1 - select STM32_HAVE_I2C2 - select STM32_HAVE_I2C3 - select STM32_HAVE_SPI1 - select STM32_HAVE_SPI2 - select STM32_HAVE_SPI3 - select STM32_HAVE_CAN1 - select STM32_HAVE_CAN2 - select STM32_HAVE_OTGFS - select STM32_HAVE_I2SPLL - -config STM32_STM32F405 - bool - default n - select STM32_HAVE_FSMC - select STM32_HAVE_CCM - select STM32_HAVE_USART3 - select STM32_HAVE_UART4 - select STM32_HAVE_UART5 - select STM32_HAVE_USART6 - select STM32_HAVE_TIM1 - select STM32_HAVE_TIM3 - select STM32_HAVE_TIM4 - select STM32_HAVE_TIM5 - select STM32_HAVE_TIM6 - select STM32_HAVE_TIM7 - select STM32_HAVE_TIM8 - select STM32_HAVE_TIM9 - select STM32_HAVE_TIM10 - select STM32_HAVE_TIM11 - select STM32_HAVE_TIM12 - select STM32_HAVE_TIM13 - select STM32_HAVE_TIM14 - select STM32_HAVE_ADC2 - select STM32_HAVE_ADC3 - select STM32_HAVE_CAN1 - select STM32_HAVE_CAN2 - select STM32_HAVE_DAC1 - select STM32_HAVE_DAC2 - select STM32_HAVE_SPI3 - select STM32_HAVE_I2S3 - select STM32_HAVE_I2C3 - select STM32_HAVE_RNG - select STM32_HAVE_OTGFS - -config STM32_STM32F407 - bool - default n - select STM32_HAVE_FSMC - select STM32_HAVE_CCM - select STM32_HAVE_USART3 - select STM32_HAVE_UART4 - select STM32_HAVE_UART5 - select STM32_HAVE_USART6 - select STM32_HAVE_TIM1 - select STM32_HAVE_TIM2 - select STM32_HAVE_TIM3 - select STM32_HAVE_TIM4 - select STM32_HAVE_TIM5 - select STM32_HAVE_TIM6 - select STM32_HAVE_TIM7 - select STM32_HAVE_TIM8 - select STM32_HAVE_TIM9 - select STM32_HAVE_TIM10 - select STM32_HAVE_TIM11 - select STM32_HAVE_TIM12 - select STM32_HAVE_TIM13 - select STM32_HAVE_TIM14 - select STM32_HAVE_ADC2 - select STM32_HAVE_ADC3 - select STM32_HAVE_CAN1 - select STM32_HAVE_CAN2 - select STM32_HAVE_DAC1 - select STM32_HAVE_SPI3 - select STM32_HAVE_I2S3 - select STM32_HAVE_I2C3 - select STM32_HAVE_RNG - select STM32_HAVE_ETHMAC - select STM32_HAVE_OTGFS - -# This is really 427/437, but we treat the two the same. - -config STM32_STM32F427 - bool - default n - select STM32_HAVE_OVERDRIVE - select STM32_HAVE_FMC - select STM32_HAVE_CCM - select STM32_HAVE_USART3 - select STM32_HAVE_UART4 - select STM32_HAVE_UART5 - select STM32_HAVE_USART6 - select STM32_HAVE_UART7 - select STM32_HAVE_UART8 - select STM32_HAVE_TIM1 - select STM32_HAVE_TIM3 - select STM32_HAVE_TIM4 - select STM32_HAVE_TIM5 - select STM32_HAVE_TIM6 - select STM32_HAVE_TIM7 - select STM32_HAVE_TIM8 - select STM32_HAVE_TIM9 - select STM32_HAVE_TIM10 - select STM32_HAVE_TIM11 - select STM32_HAVE_TIM12 - select STM32_HAVE_TIM13 - select STM32_HAVE_TIM14 - select STM32_HAVE_ADC2 - select STM32_HAVE_ADC3 - select STM32_HAVE_CAN1 - select STM32_HAVE_CAN2 - select STM32_HAVE_DAC1 - select STM32_HAVE_RNG - select STM32_HAVE_ETHMAC - select STM32_HAVE_SPI2 - select STM32_HAVE_SPI3 - select STM32_HAVE_SPI4 - select STM32_HAVE_SPI5 - select STM32_HAVE_I2S3 - select STM32_HAVE_I2C3 - select STM32_HAVE_OTGFS - select STM32_HAVE_SPI6 - select STM32_HAVE_I2SPLL - -# This is really 429/439, but we treat the two the same. - -config STM32_STM32F429 - bool - default n - select STM32_HAVE_OVERDRIVE - select STM32_HAVE_FMC - select STM32_HAVE_LTDC - select STM32_HAVE_CCM - select STM32_HAVE_USART3 - select STM32_HAVE_UART4 - select STM32_HAVE_UART5 - select STM32_HAVE_USART6 - select STM32_HAVE_UART7 - select STM32_HAVE_UART8 - select STM32_HAVE_TIM1 - select STM32_HAVE_TIM3 - select STM32_HAVE_TIM4 - select STM32_HAVE_TIM5 - select STM32_HAVE_TIM6 - select STM32_HAVE_TIM7 - select STM32_HAVE_TIM8 - select STM32_HAVE_TIM9 - select STM32_HAVE_TIM10 - select STM32_HAVE_TIM11 - select STM32_HAVE_TIM12 - select STM32_HAVE_TIM13 - select STM32_HAVE_TIM14 - select STM32_HAVE_ADC2 - select STM32_HAVE_ADC3 - select STM32_HAVE_CAN1 - select STM32_HAVE_CAN2 - select STM32_HAVE_DAC1 - select STM32_HAVE_RNG - select STM32_HAVE_ETHMAC - select STM32_HAVE_SPI2 - select STM32_HAVE_SPI3 - select STM32_HAVE_I2S3 - select STM32_HAVE_SPI4 - select STM32_HAVE_SPI5 - select STM32_HAVE_SPI6 - select STM32_HAVE_I2S3 - select STM32_HAVE_I2C3 - select STM32_HAVE_OTGFS - -config STM32_STM32F446 - bool - default n - select STM32_HAVE_OVERDRIVE - select STM32_HAVE_USART3 - select STM32_HAVE_UART4 - select STM32_HAVE_UART5 - select STM32_HAVE_USART6 - select STM32_HAVE_TIM1 - select STM32_HAVE_TIM2 - select STM32_HAVE_TIM3 - select STM32_HAVE_TIM4 - select STM32_HAVE_TIM5 - select STM32_HAVE_TIM6 - select STM32_HAVE_TIM7 - select STM32_HAVE_TIM8 - select STM32_HAVE_TIM9 - select STM32_HAVE_TIM10 - select STM32_HAVE_TIM11 - select STM32_HAVE_TIM12 - select STM32_HAVE_TIM13 - select STM32_HAVE_TIM14 - select STM32_HAVE_ADC2 - select STM32_HAVE_ADC3 - select STM32_HAVE_CAN1 - select STM32_HAVE_CAN2 - select STM32_HAVE_DAC1 - select STM32_HAVE_SPI3 - select STM32_HAVE_SPI4 - select STM32_HAVE_I2S3 - select STM32_HAVE_I2C3 - select STM32_HAVE_OTGFS - select STM32_HAVE_SAIPLL - select STM32_HAVE_I2SPLL - -# This is really 469/479, but we treat the two the same. - -config STM32_STM32F469 - bool - default n - select STM32_HAVE_OVERDRIVE - select STM32_HAVE_FMC - select STM32_HAVE_LTDC - select STM32_HAVE_CCM - select STM32_HAVE_USART3 - select STM32_HAVE_UART4 - select STM32_HAVE_UART5 - select STM32_HAVE_USART6 - select STM32_HAVE_UART7 - select STM32_HAVE_UART8 - select STM32_HAVE_TIM1 - select STM32_HAVE_TIM2 - select STM32_HAVE_TIM3 - select STM32_HAVE_TIM4 - select STM32_HAVE_TIM5 - select STM32_HAVE_TIM6 - select STM32_HAVE_TIM7 - select STM32_HAVE_TIM8 - select STM32_HAVE_TIM9 - select STM32_HAVE_TIM10 - select STM32_HAVE_TIM11 - select STM32_HAVE_TIM12 - select STM32_HAVE_TIM13 - select STM32_HAVE_TIM14 - select STM32_HAVE_ADC2 - select STM32_HAVE_ADC3 - select STM32_HAVE_CAN1 - select STM32_HAVE_CAN2 - select STM32_HAVE_DAC1 - select STM32_HAVE_RNG - select STM32_HAVE_SPI3 - select STM32_HAVE_SPI4 - select STM32_HAVE_SPI5 - select STM32_HAVE_SPI6 - select STM32_HAVE_OTGFS - select STM32_HAVE_SAIPLL - select STM32_HAVE_I2SPLL - select STM32_HAVE_I2S3 - select STM32_HAVE_I2C3 - -config STM32_STM32G4XXX - bool - default n - select ARCH_CORTEXM4 - select ARCH_HAVE_FPU - select STM32_HAVE_DMAMUX - select STM32_HAVE_IP_DBGMCU_V3 - select STM32_HAVE_IP_ADC_V2 - select STM32_HAVE_IP_COMP_V2 - select STM32_HAVE_IP_DAC_V2 - select STM32_HAVE_IP_DMA_V1 - select STM32_HAVE_IP_I2C_V2 - select STM32_HAVE_IP_TIMERS_V3 - -config STM32_STM32G4_CAT2 - bool - default n - -config STM32_STM32G4_CAT3 - bool - default n - -config STM32_STM32G4_CAT4 - bool - default n - -config STM32_STM32G4XXK - bool - default n - -config STM32_STM32G4XXC - bool - default n - -config STM32_STM32G4XXR - bool - default n - -config STM32_STM32G4XXM - bool - default n - -config STM32_STM32G4XXV - bool - default n - -config STM32_STM32G4XXP - bool - default n - -config STM32_STM32G4XXQ - bool - default n - -config STM32_STM32G43XX - bool - default n - select STM32_STM32G4XXX - select STM32_STM32G4_CAT2 - select STM32_HAVE_ADC2 - select STM32_HAVE_CCM - select STM32_HAVE_COMP1 - select STM32_HAVE_COMP2 - select STM32_HAVE_COMP3 - select STM32_HAVE_COMP4 - select STM32_HAVE_CORDIC - select STM32_HAVE_CRS - select STM32_HAVE_DAC1 - select STM32_HAVE_DAC3 - select STM32_HAVE_FMAC - select STM32_HAVE_FDCAN1 - select STM32_HAVE_I2C2 - select STM32_HAVE_I2C3 - select STM32_HAVE_LPTIM1 - select STM32_HAVE_LPUART1 - select STM32_HAVE_OPAMP1 - select STM32_HAVE_OPAMP2 - select STM32_HAVE_OPAMP3 - select STM32_HAVE_RNG - select STM32_HAVE_SPI2 - select STM32_HAVE_SPI3 - select STM32_HAVE_TIM1 - select STM32_HAVE_TIM15 - select STM32_HAVE_TIM16 - select STM32_HAVE_TIM17 - select STM32_HAVE_TIM2 - select STM32_HAVE_TIM3 - select STM32_HAVE_TIM4 - select STM32_HAVE_TIM8 - select STM32_HAVE_UCPD - select STM32_HAVE_USBDEV - -config STM32_STM32G431K - bool - default n - -config STM32_STM32G431C - bool - default n - select STM32_HAVE_USART3 - -config STM32_STM32G431R - bool - default n - select STM32_HAVE_USART3 - select STM32_HAVE_UART4 - -config STM32_STM32G431M - bool - default n - select STM32_HAVE_USART3 - select STM32_HAVE_UART4 - -config STM32_STM32G431V - bool - default n - select STM32_HAVE_USART3 - select STM32_HAVE_UART4 - -config STM32_STM32G47XX - bool - default n - select STM32_STM32G4XXX - select STM32_STM32G4_CAT3 - select STM32_HAVE_ADC2 - select STM32_HAVE_ADC3 - select STM32_HAVE_ADC4 - select STM32_HAVE_ADC5 - select STM32_HAVE_CCM - select STM32_HAVE_COMP1 - select STM32_HAVE_COMP2 - select STM32_HAVE_COMP3 - select STM32_HAVE_COMP4 - select STM32_HAVE_COMP5 - select STM32_HAVE_COMP6 - select STM32_HAVE_COMP7 - select STM32_HAVE_CORDIC - select STM32_HAVE_CRS - select STM32_HAVE_DAC1 - select STM32_HAVE_DAC2 - select STM32_HAVE_DAC3 - select STM32_HAVE_DAC4 - select STM32_HAVE_DMA1_CHAN8 - select STM32_HAVE_DMA2_CHAN678 - select STM32_HAVE_FSMC - select STM32_HAVE_FMAC - select STM32_HAVE_FDCAN1 - select STM32_HAVE_FDCAN2 - select STM32_HAVE_HRTIM1 - select STM32_HAVE_I2C2 - select STM32_HAVE_I2C3 - select STM32_HAVE_I2C4 - select STM32_HAVE_I2S3 - select STM32_HAVE_LPTIM1 - select STM32_HAVE_LPUART1 - select STM32_HAVE_OPAMP1 - select STM32_HAVE_OPAMP2 - select STM32_HAVE_OPAMP3 - select STM32_HAVE_OPAMP4 - select STM32_HAVE_OPAMP5 - select STM32_HAVE_OPAMP6 - select STM32_HAVE_QSPI - select STM32_HAVE_RNG - select STM32_HAVE_SPI2 - select STM32_HAVE_SPI3 - select STM32_HAVE_TIM1 - select STM32_HAVE_TIM15 - select STM32_HAVE_TIM16 - select STM32_HAVE_TIM17 - select STM32_HAVE_TIM2 - select STM32_HAVE_TIM20 - select STM32_HAVE_TIM3 - select STM32_HAVE_TIM4 - select STM32_HAVE_TIM5 - select STM32_HAVE_TIM8 - select STM32_HAVE_USART3 - select STM32_HAVE_UCPD - select STM32_HAVE_USBDEV - -config STM32_STM32G474C - bool - default n - select STM32_HAVE_FDCAN3 - -config STM32_STM32G474M - bool - default n - select STM32_HAVE_FDCAN3 - select STM32_HAVE_SPI4 - select STM32_HAVE_UART4 - select STM32_HAVE_UART5 - -config STM32_STM32G474R - bool - default n - select STM32_HAVE_FDCAN3 - select STM32_HAVE_UART4 - select STM32_HAVE_UART5 - -config STM32_STM32G474Q - bool - default n - select STM32_HAVE_FDCAN3 - select STM32_HAVE_FMC - select STM32_HAVE_SPI4 - select STM32_HAVE_UART4 - select STM32_HAVE_UART5 - -config STM32_STM32G474V - bool - default n - select STM32_HAVE_FDCAN3 - select STM32_HAVE_FMC - select STM32_HAVE_SPI4 - select STM32_HAVE_UART4 - select STM32_HAVE_UART5 - -config STM32_DFU - bool "DFU bootloader" - default n - depends on !STM32_VALUELINE - ---help--- - Configure and position code for use with the STMicro DFU bootloader. Do - not select this option if you will load code using JTAG/SWM. - -menu "STM32 Peripheral Support" - -# These "hidden" settings determine whether a peripheral option is available -# for the selected MCU - -config STM32_HAVE_FLASH_ICACHE - bool - default n - -config STM32_HAVE_FLASH_DCACHE - bool - default n - -config STM32_HAVE_OVERDRIVE - bool - default n - -config STM32_HAVE_AES - bool - default n - -config STM32_HAVE_CRYP - bool - default n - -config STM32_HAVE_CCM - bool - default n - -config STM32_HAVE_DMA1_CHAN8 - bool - default n - -config STM32_HAVE_DMA2_CHAN678 - bool - default n - -config STM32_HAVE_DMAMUX - bool - default n - -config STM32_HAVE_UCPD - bool - default n - -config STM32_HAVE_USBDEV - bool - default n - -config STM32_HAVE_USBFS - bool - default n - -config STM32_HAVE_OTGFS - bool - default n - -config STM32_HAVE_FMC - bool - default n - -config STM32_HAVE_FMAC - bool - default n - -config STM32_HAVE_FSMC - bool - default n - -config STM32_HAVE_FDCAN1 - bool - default n - -config STM32_HAVE_FDCAN2 - bool - default n - -config STM32_HAVE_FDCAN3 - bool - default n - -config STM32_HAVE_IOCOMPENSATION - bool - default n - -config STM32_HAVE_HRTIM1 - bool - default n - -config STM32_HAVE_HRTIM1_PLLCLK - bool - default n - -config STM32_HAVE_LTDC - bool - default n - -config STM32_HAVE_USART3 - bool - default n - -config STM32_HAVE_UART4 - bool - default n - -config STM32_HAVE_UART5 - bool - default n - -config STM32_HAVE_USART6 - bool - default n - -config STM32_HAVE_UART7 - bool - default n - -config STM32_HAVE_UART8 - bool - default n - -config STM32_HAVE_TIM1 - bool - default n - -config STM32_HAVE_TIM2 - bool - default n - -config STM32_HAVE_TIM3 - bool - default n - -config STM32_HAVE_TIM4 - bool - default n - -config STM32_HAVE_TIM5 - bool - default n - -config STM32_HAVE_TIM6 - bool - default n - -config STM32_HAVE_TIM7 - bool - default n - -config STM32_HAVE_TIM8 - bool - default n - -config STM32_HAVE_TIM9 - bool - default n - -config STM32_HAVE_TIM10 - bool - default n - -config STM32_HAVE_TIM11 - bool - default n - -config STM32_HAVE_TIM12 - bool - default n - -config STM32_HAVE_TIM13 - bool - default n - -config STM32_HAVE_TIM14 - bool - default n - -config STM32_HAVE_TIM15 - bool - default n - -config STM32_HAVE_TIM16 - bool - default n - -config STM32_HAVE_TIM17 - bool - default n - -config STM32_HAVE_TIM18 - bool - default n - -config STM32_HAVE_TIM19 - bool - default n - -config STM32_HAVE_TIM20 - bool - default n - -config STM32_HAVE_TSC - bool - default n - -config STM32_HAVE_ADC1 - bool - default y - -config STM32_HAVE_ADC2 - bool - default n - -config STM32_HAVE_ADC3 - bool - default n - -config STM32_HAVE_ADC4 - bool - default n - -config STM32_HAVE_ADC5 - bool - default n - -config STM32_HAVE_ADC1_DMA - bool - default n - -config STM32_HAVE_ADC2_DMA - bool - default n - -config STM32_HAVE_ADC3_DMA - bool - default n - -config STM32_HAVE_ADC4_DMA - bool - default n - -config STM32_HAVE_ADC5_DMA - bool - default n - -config STM32_HAVE_SDADC1 - bool - default n - -config STM32_HAVE_SDADC2 - bool - default n - -config STM32_HAVE_SDADC3 - bool - default n - -config STM32_HAVE_SDADC1_DMA - bool - default n - -config STM32_HAVE_SDADC2_DMA - bool - default n - -config STM32_HAVE_SDADC3_DMA - bool - default n - -config STM32_HAVE_CAN1 - bool - default n - -config STM32_HAVE_CAN2 - bool - default n - -config STM32_HAVE_COMP1 - bool - default n - -config STM32_HAVE_COMP2 - bool - default n - -config STM32_HAVE_COMP3 - bool - default n - -config STM32_HAVE_COMP4 - bool - default n - -config STM32_HAVE_COMP5 - bool - default n - -config STM32_HAVE_COMP6 - bool - default n - -config STM32_HAVE_COMP7 - bool - default n - -config STM32_HAVE_CORDIC - bool - default n - -config STM32_HAVE_CRS - bool - default n - -config STM32_HAVE_DAC1 - bool - default n - -config STM32_HAVE_DAC2 - bool - default n - -config STM32_HAVE_DAC3 - bool - default n - -config STM32_HAVE_DAC4 - bool - default n - -config STM32_HAVE_QSPI - bool - default n - -config STM32_HAVE_RNG - bool - default n - -config STM32_HAVE_ETHMAC - bool - default n - -config STM32_HAVE_I2C2 - bool - default n - -config STM32_HAVE_I2C3 - bool - default n - -config STM32_HAVE_I2C4 - bool - default n - -config STM32_HAVE_LPTIM1 - bool - default n - -config STM32_HAVE_LPUART1 - bool - default n - -config STM32_HAVE_SPI2 - bool - default n - -config STM32_HAVE_SPI3 - bool - default n - -config STM32_HAVE_I2S3 - bool - default n - -config STM32_HAVE_SPI4 - bool - default n - -config STM32_HAVE_SPI5 - bool - default n - -config STM32_HAVE_SPI6 - bool - default n - -config STM32_HAVE_SAIPLL - bool - default n - -config STM32_HAVE_I2SPLL - bool - default n - -config STM32_HAVE_OPAMP1 - bool - default n - -config STM32_HAVE_OPAMP2 - bool - default n - -config STM32_HAVE_OPAMP3 - bool - default n - -config STM32_HAVE_OPAMP4 - bool - default n - -config STM32_HAVE_OPAMP5 - bool - default n - -config STM32_HAVE_OPAMP6 - bool - default n - -# These are STM32 peripherals IP blocks - -config STM32_HAVE_IP_DBGMCU_V1 - bool - default n - -config STM32_HAVE_IP_DBGMCU_V2 - bool - default n - -config STM32_HAVE_IP_DBGMCU_V3 - bool - default n - -config STM32_HAVE_IP_I2C_V1 - bool - default n - -config STM32_HAVE_IP_I2C_V2 - bool - default n - -config STM32_HAVE_IP_DMA_V1 - bool - default n - -config STM32_HAVE_IP_DMA_V2 - bool - default n - -config STM32_HAVE_IP_TIMERS_V1 - bool - default n - -config STM32_HAVE_IP_TIMERS_V2 - bool - default n - -config STM32_HAVE_IP_TIMERS_V3 - bool - default n - -config STM32_HAVE_IP_ADC_V1 - bool - default n - -config STM32_HAVE_IP_ADC_V1_BASIC - bool - default n - select STM32_HAVE_IP_ADC_V1 - -config STM32_HAVE_IP_ADC_V2 - bool - default n - -config STM32_HAVE_IP_ADC_V2_BASIC - bool - default n - select STM32_HAVE_IP_ADC_V2 - -config STM32_HAVE_IP_COMP_V1 - bool - default n - -config STM32_HAVE_IP_COMP_V2 - bool - default n - -config STM32_HAVE_IP_DAC_V1 - bool - default n - -config STM32_HAVE_IP_DAC_V2 - bool - default n - -# These are the peripheral selections proper - -config STM32_ADC1 - bool "ADC1" - default n - select STM32_ADC - select STM32_HAVE_ADC1_DMA if STM32_STM32F10XX && STM32_DMA1 - select STM32_HAVE_ADC1_DMA if STM32_STM32F37XX && STM32_DMA1 - select STM32_HAVE_ADC1_DMA if !STM32_STM32F10XX && STM32_DMA2 - select STM32_HAVE_ADC1_DMA if STM32_DMAMUX - -config STM32_ADC2 - bool "ADC2" - default n - select STM32_ADC - depends on STM32_HAVE_ADC2 - select STM32_HAVE_ADC2_DMA if STM32_DMA2 - select STM32_HAVE_ADC2_DMA if STM32_DMAMUX - -config STM32_ADC3 - bool "ADC3" - default n - select STM32_ADC - depends on STM32_HAVE_ADC3 - select STM32_HAVE_ADC3_DMA if STM32_DMA2 - select STM32_HAVE_ADC3_DMA if STM32_DMAMUX - -config STM32_ADC4 - bool "ADC4" - default n - select STM32_ADC - depends on STM32_HAVE_ADC4 - select STM32_HAVE_ADC4_DMA if STM32_DMA2 - select STM32_HAVE_ADC4_DMA if STM32_DMAMUX - -config STM32_ADC5 - bool "ADC5" - default n - select STM32_ADC - depends on STM32_HAVE_ADC5 - select STM32_HAVE_ADC5_DMA if STM32_DMA2 - select STM32_HAVE_ADC5_DMA if STM32_DMAMUX - -config STM32_SDADC1 - bool "SDADC1" - default n - select STM32_SDADC - depends on STM32_HAVE_SDADC1 - select STM32_HAVE_SDADC1_DMA if STM32_DMA2 - -config STM32_SDADC2 - bool "SDADC2" - default n - select STM32_SDADC - depends on STM32_HAVE_SDADC2 - select STM32_HAVE_SDADC2_DMA if STM32_DMA2 - -config STM32_SDADC3 - bool "SDADC3" - default n - select STM32_SDADC - depends on STM32_HAVE_SDADC3 - select STM32_HAVE_SDADC3_DMA if STM32_DMA2 - -config STM32_COMP1 - bool "COMP1" - default n - select STM32_COMP - depends on STM32_HAVE_COMP1 - -config STM32_COMP2 - bool "COMP2" - default n - select STM32_COMP - depends on STM32_HAVE_COMP2 - -config STM32_COMP3 - bool "COMP3" - default n - select STM32_COMP - depends on STM32_HAVE_COMP3 - -config STM32_COMP4 - bool "COMP4" - default n - select STM32_COMP - depends on STM32_HAVE_COMP4 - -config STM32_COMP5 - bool "COMP5" - default n - select STM32_COMP - depends on STM32_HAVE_COMP5 - -config STM32_COMP6 - bool "COMP6" - default n - select STM32_COMP - depends on STM32_HAVE_COMP6 - -config STM32_COMP7 - bool "COMP7" - default n - select STM32_COMP - depends on STM32_HAVE_COMP7 - -config STM32_CORDIC - bool "CORDIC Accelerator" - default n - depends on STM32_HAVE_CORDIC - depends on MATH_CORDIC_USE_Q31 - -config STM32_BKP - bool "BKP" - default n - depends on STM32_STM32F10XX - -config STM32_BKPSRAM - bool "Enable BKP RAM Domain" - default n - depends on STM32_STM32F20XX || STM32_STM32F4XXX - -config STM32_CAN1 - bool "CAN1" - default n - select STM32_CAN - depends on STM32_HAVE_CAN1 - -config STM32_CAN2 - bool "CAN2" - default n - select STM32_CAN - depends on STM32_HAVE_CAN2 - -config STM32_CCMDATARAM - bool "CMD/DATA RAM" - default n - depends on STM32_STM32F4XXX - -config STM32_AES - bool "128-bit AES" - default n - depends on STM32_HAVE_AES - select CRYPTO_AES192_DISABLE if CRYPTO_ALGTEST - select CRYPTO_AES256_DISABLE if CRYPTO_ALGTEST - -config STM32_CEC - bool "CEC" - default n - depends on STM32_VALUELINE - -config STM32_CRC - bool "CRC" - default n - -config STM32_CRS - bool "CRS (Clock Recovery System)" - default n - depends on STM32_HAVE_CRS - -config STM32_CRYP - bool "CRYP" - default n - depends on STM32_HAVE_CRYP - -config STM32_DMA1 - bool "DMA1" - default n - select STM32_DMA - select ARCH_DMA - -config STM32_DMA2 - bool "DMA2" - default n - select STM32_DMA - select ARCH_DMA - depends on !STM32_VALUELINE || (STM32_VALUELINE && STM32_HIGHDENSITY) - -config STM32_DMAMUX1 - bool "DMAMUX1" - default n - depends on STM32_HAVE_DMAMUX - select STM32_DMAMUX - -config STM32_DAC1 - bool "DAC1" - default n - depends on STM32_HAVE_DAC1 - select STM32_DAC - -if STM32_DAC1 - -config STM32_DAC1CH1 - bool "DAC1CH1" - default n - -config STM32_DAC1CH2 - bool "DAC1CH2" - default n - -endif #STM32_DAC1 - -config STM32_DAC2 - bool "DAC2" - default n - depends on STM32_HAVE_DAC2 - select STM32_DAC - -if STM32_DAC2 - -config STM32_DAC2CH1 - bool "DAC2CH1" - default n - -endif #STM32_DAC2 - -config STM32_DAC3 - bool "DAC3" - default n - depends on STM32_HAVE_DAC3 - select STM32_DAC - -if STM32_DAC3 - -config STM32_DAC3CH1 - bool "DAC3CH1 Internal" - default n - -config STM32_DAC3CH2 - bool "DAC3CH2 Internal" - default n - -endif #STM32_DAC3 - -config STM32_DAC4 - bool "DAC4" - default n - depends on STM32_HAVE_DAC4 - select STM32_DAC - -if STM32_DAC4 - -config STM32_DAC4CH1 - bool "DAC4CH1 Internal" - default n - -config STM32_DAC4CH2 - bool "DAC4CH2 Internal" - default n - -endif #STM32_DAC4 - -config STM32_DCMI - bool "DCMI" - default n - depends on STM32_STM32F20XX || STM32_STM32F4XXX - -config STM32_ETHMAC - bool "Ethernet MAC" - default n - depends on STM32_HAVE_ETHMAC - select NETDEVICES - select ARCH_HAVE_PHY - -config STM32_FDCAN1 - bool "FDCAN1" - default n - depends on STM32_HAVE_FDCAN1 - select STM32_FDCAN - -config STM32_FDCAN2 - bool "FDCAN2" - default n - depends on STM32_HAVE_FDCAN2 - select STM32_FDCAN - -config STM32_FDCAN3 - bool "FDCAN3" - default n - depends on STM32_HAVE_FDCAN3 - select STM32_FDCAN - -config STM32_FSMC - bool "FSMC" - default n - depends on STM32_HAVE_FSMC - -config STM32_FMC - bool "FMC" - default n - depends on STM32_HAVE_FMC - -config STM32_FMAC - bool "FMAC (Filter Math Accelerator)" - default n - depends on STM32_HAVE_FMAC - -config STM32_HASH - bool "HASH" - default n - depends on STM32_STM32F20XX || STM32_STM32F4XXX - -config STM32_HRTIM - bool - default n - -config STM32_HRTIM1 - bool "HRTIM1" - default n - depends on STM32_HAVE_HRTIM1 - select STM32_HRTIM - -if STM32_HRTIM1 - -config STM32_HRTIM_MASTER - bool "HRTIM MASTER" - default n - ---help--- - Enable HRTIM Master Timer - -config STM32_HRTIM_TIMA - bool "HRTIM TIMA" - default n - ---help--- - Enable HRTIM Timer A - -config STM32_HRTIM_TIMB - bool "HRTIM TIMB" - default n - ---help--- - Enable HRTIM Timer B - -config STM32_HRTIM_TIMC - bool "HRTIM TIMC" - default n - ---help--- - Enable HRTIM Timer C - -config STM32_HRTIM_TIMD - bool "HRTIM TIMD" - default n - ---help--- - Enable HRTIM Timer D - -config STM32_HRTIM_TIME - bool "HRTIM TIME" - default n - ---help--- - Enable HRTIM Timer E - -endif # STM32_HRTIM - -config STM32_I2C1 - bool "I2C1" - default n - select STM32_I2C - -config STM32_I2C2 - bool "I2C2" - default n - depends on STM32_HAVE_I2C2 - select STM32_I2C - -config STM32_I2C3 - bool "I2C3" - default n - depends on STM32_HAVE_I2C3 - select STM32_I2C - -config STM32_I2C1_SLAVE - bool "I2C1 Slave" - default n - depends on !STM32_I2C1 && I2C_SLAVE - select STM32_I2C_SLAVE - -config STM32_I2C2_SLAVE - bool "I2C2 Slave" - default n - depends on STM32_HAVE_I2C2 && !STM32_I2C2 && I2C_SLAVE - select STM32_I2C_SLAVE - -config STM32_I2C3_SLAVE - bool "I2C3 Slave" - default n - depends on STM32_HAVE_I2C3 && !STM32_I2C3 && I2C_SLAVE - select STM32_I2C_SLAVE - -config STM32_LPTIM1 - bool "LPTIM1" - default n - depends on STM32_HAVE_LPTIM1 - -config STM32_LPUART1 - bool "LPUART1" - default n - depends on STM32_HAVE_LPUART1 - select STM32_USART - -config STM32_LTDC - bool "LTDC" - default n - select FB - depends on STM32_HAVE_LTDC - ---help--- - The STM32 LTDC is an LCD-TFT Display Controller available on - the STM32F429 and STM32F439 devices. It is a standard parallel - video interface (HSYNC, VSYNC, etc.) for controlling TFT - LCD displays. - -config STM32_DMA2D - bool "DMA2D" - default n - select FB - select FB_OVERLAY - depends on STM32_STM32F429 - ---help--- - The STM32 DMA2D is an Chrom-Art Accelerator for image manipulation - available on the STM32F429 and STM32F439 devices. - -config STM32_OPAMP1 - bool "OPAMP1" - default n - select STM32_OPAMP - depends on STM32_HAVE_OPAMP1 - -config STM32_OPAMP2 - bool "OPAMP2" - default n - select STM32_OPAMP - depends on STM32_HAVE_OPAMP2 - -config STM32_OPAMP3 - bool "OPAMP3" - default n - select STM32_OPAMP - depends on STM32_HAVE_OPAMP3 - -config STM32_OPAMP4 - bool "OPAMP4" - default n - select STM32_OPAMP - depends on STM32_HAVE_OPAMP4 - -config STM32_RTC - bool "RTC" - default n - select RTC - -config STM32_OTGFS - bool "OTG FS" - default n - depends on STM32_HAVE_OTGFS - select USBHOST_HAVE_ASYNCH if STM32_USBHOST - -config STM32_OTGHS - bool "OTG HS" - default n - depends on STM32_STM32F20XX || STM32_STM32F4XXX - select USBHOST_HAVE_ASYNCH if STM32_USBHOST - -config STM32_PWR - bool "PWR" - default n - -config STM32_QSPI - bool "QSPI (QUADSPI)" - depends on STM32_HAVE_QSPI - default n - -config STM32_RNG - bool "RNG" - default n - depends on STM32_HAVE_RNG - select ARCH_HAVE_RNG - -# REVISIT: There are some lower-end STM32F401 parts without SDIO too. Others? - -config STM32_SDIO - bool "SDIO" - default n - depends on !STM32_CONNECTIVITYLINE && !STM32_VALUELINE - select ARCH_HAVE_SDIO - select ARCH_HAVE_SDIOWAIT_WRCOMPLETE - select ARCH_HAVE_SDIO_PREFLIGHT - -config STM32_SPI1 - bool "SPI1" - default n - select SPI - select STM32_SPI - -config STM32_SPI2 - bool "SPI2" - default n - depends on STM32_HAVE_SPI2 - select SPI - select STM32_SPI - -config STM32_SPI3 - bool "SPI3" - default n - depends on STM32_HAVE_SPI3 - select SPI - select STM32_SPI - -config STM32_I2S3 - bool "I2S3" - default n - depends on STM32_HAVE_I2S3 - select I2S - select STM32_I2S - -config STM32_SPI4 - bool "SPI4" - default n - depends on STM32_HAVE_SPI4 - select SPI - select STM32_SPI - -config STM32_SPI5 - bool "SPI5" - default n - depends on STM32_HAVE_SPI5 - select SPI - select STM32_SPI - -config STM32_SPI6 - bool "SPI6" - default n - depends on STM32_HAVE_SPI6 - select SPI - select STM32_SPI - -config STM32_SYSCFG - bool "SYSCFG" - default y - depends on STM32_STM32L15XX || STM32_STM32F30XX || STM32_STM32F33XX || STM32_STM32F37XX || STM32_STM32F20XX || STM32_STM32F4XXX || STM32_STM32G4XXX || STM32_CONNECTIVITYLINE - -config STM32_TIM1 - bool "TIM1" - default n - depends on STM32_HAVE_TIM1 - select STM32_TIM - -config STM32_TIM2 - bool "TIM2" - default n - select STM32_TIM - -config STM32_TIM3 - bool "TIM3" - default n - depends on STM32_HAVE_TIM3 - select STM32_TIM - -config STM32_TIM4 - bool "TIM4" - default n - depends on STM32_HAVE_TIM4 - select STM32_TIM - -config STM32_TIM5 - bool "TIM5" - default n - depends on STM32_HAVE_TIM5 - select STM32_TIM - -config STM32_TIM6 - bool "TIM6" - default n - depends on STM32_HAVE_TIM6 - select STM32_TIM - -config STM32_TIM7 - bool "TIM7" - default n - depends on STM32_HAVE_TIM7 - select STM32_TIM - -config STM32_TIM8 - bool "TIM8" - default n - depends on STM32_HAVE_TIM8 - select STM32_TIM - -config STM32_TIM9 - bool "TIM9" - default n - depends on STM32_HAVE_TIM9 - select STM32_TIM - -config STM32_TIM10 - bool "TIM10" - default n - depends on STM32_HAVE_TIM10 - select STM32_TIM - -config STM32_TIM11 - bool "TIM11" - default n - depends on STM32_HAVE_TIM11 - select STM32_TIM - -config STM32_TIM12 - bool "TIM12" - default n - depends on STM32_HAVE_TIM12 - select STM32_TIM - -config STM32_TIM13 - bool "TIM13" - default n - depends on STM32_HAVE_TIM13 - select STM32_TIM - -config STM32_TIM14 - bool "TIM14" - default n - depends on STM32_HAVE_TIM14 - select STM32_TIM - -config STM32_TIM15 - bool "TIM15" - default n - depends on STM32_HAVE_TIM15 - select STM32_TIM - -config STM32_TIM16 - bool "TIM16" - default n - depends on STM32_HAVE_TIM16 - select STM32_TIM - -config STM32_TIM17 - bool "TIM17" - default n - depends on STM32_HAVE_TIM17 - select STM32_TIM - -config STM32_TSC - bool "TSC" - default n - depends on STM32_HAVE_TSC - -config STM32_USART1 - bool "USART1" - default n - select STM32_USART - -config STM32_USART2 - bool "USART2" - default n - select STM32_USART - -config STM32_USART3 - bool "USART3" - default n - depends on STM32_HAVE_USART3 - select STM32_USART - -config STM32_UART4 - bool "UART4" - default n - depends on STM32_HAVE_UART4 - select STM32_USART - -config STM32_UART5 - bool "UART5" - default n - depends on STM32_HAVE_UART5 - select STM32_USART - -config STM32_USART6 - bool "USART6" - default n - depends on STM32_HAVE_USART6 - select STM32_USART - -config STM32_UART7 - bool "UART7" - default n - depends on STM32_HAVE_UART7 - select STM32_USART - -config STM32_UART8 - bool "UART8" - default n - depends on STM32_HAVE_UART8 - select STM32_USART - -config STM32_USB - bool "USB Device" - default n - depends on STM32_HAVE_USBDEV - select USBDEV - -config STM32_USBFS - bool "USB Full Speed Device" - default n - depends on STM32_HAVE_USBFS - select USBDEV - -config STM32_UCPD - bool "UCPD (USB Type C Power Delivery)" - default n - depends on STM32_HAVE_UCPD - select USBDEV - -config STM32_LCD - bool "Segment LCD" - default n - depends on STM32_STM32L15XX - -# -# STM32 LCD Clock Selection -# - -if STM32_LCD - -choice - prompt "Segment LCD Clock Source" - default LCD_LSECLOCK - -config LCD_LSICLOCK - bool "Internal Low Speed Clock" - -config LCD_LSECLOCK - bool "External Low Speed Clock" - -config LCD_HSECLOCK - bool "External High Speed Clock" - -endchoice -endif # STM32_LCD - -config STM32_IWDG - bool "IWDG" - default n - select WATCHDOG - -config STM32_WWDG - bool "WWDG" - default n - select WATCHDOG - -endmenu - -config STM32_ADC - bool - default n - -config STM32_SDADC - bool - default n - -config STM32_DAC - bool - default n - -config STM32_DMA - bool - default n - -config STM32_DMAMUX - bool - default n - -config STM32_SPI - bool - default n - -config STM32_SPI_DMA - bool - default n - -config STM32_I2S - bool - default n - select STM32_SPI_DMA - -config STM32_I2C - bool - default n - -config STM32_I2C_SLAVE - bool - default n - -config STM32_CAN - bool - default n - -config STM32_FDCAN - bool - default n - -config STM32_TIM - bool - default n - -config STM32_PWM - bool - default n - -config STM32_CAP - bool - default n - -config STM32_COMP - bool - default n - depends on STM32_STM32L15XX || STM32_STM32F33XX || STM32_STM32G4XXX - -config STM32_OPAMP - bool - default n - -config STM32_NOEXT_VECTORS - bool "Disable the ARMv7-M EXT vectors" - default n - ---help--- - Sometimes you may not need any Vector support beyond SysTick - and wish to save memory. This applies only to ARMv7-M architectures. - -config STM32_SYSCFG_IOCOMPENSATION - bool "SYSCFG I/O Compensation" - default n - depends on STM32_HAVE_IOCOMPENSATION - ---help--- - By default the I/O compensation cell is not used. However when the I/O - output buffer speed is configured in 50 MHz or 100 MHz mode, it is - recommended to use the compensation cell for slew rate control on I/O - tf(IO)out)/tr(IO)out commutation to reduce the I/O noise on power supply. - - The I/O compensation cell can be used only when the supply voltage ranges - from 2.4 to 3.6 V. - -menu "Alternate Pin Mapping" - depends on STM32_STM32F10XX || STM32_CONNECTIVITYLINE - -choice - prompt "CAN1 Alternate Pin Mappings" - depends on STM32_STM32F10XX && STM32_CAN1 - default STM32_CAN1_NO_REMAP - -config STM32_CAN1_NO_REMAP - bool "No pin remapping" - -config STM32_CAN1_REMAP1 - bool "CAN1 alternate pin remapping #1" - -config STM32_CAN1_REMAP2 - bool "CAN1 alternate pin remapping #2" - -endchoice - -config STM32_CAN2_REMAP - bool "CAN2 Alternate Pin Mapping" - default n - depends on STM32_CONNECTIVITYLINE && STM32_CAN2 - -config STM32_CEC_REMAP - bool "CEC Alternate Pin Mapping" - default n - depends on STM32_STM32F10XX && STM32_CEC - -config STM32_ETH_REMAP - bool "Ethernet Alternate Pin Mapping" - default n - depends on STM32_CONNECTIVITYLINE && STM32_ETHMAC - -config STM32_I2C1_REMAP - bool "I2C1 Alternate Pin Mapping" - default n - depends on STM32_STM32F10XX && STM32_I2C1 - -config STM32_SPI1_REMAP - bool "SPI1 Alternate Pin Mapping" - default n - depends on STM32_STM32F10XX && STM32_SPI1 - -config STM32_SPI3_REMAP - bool "SPI3 Alternate Pin Mapping" - default n - depends on STM32_STM32F10XX && STM32_SPI3 && !STM32_VALUELINE - -config STM32_I2S3_REMAP - bool "I2S3 Alternate Pin Mapping" - default n - depends on STM32_STM32F10XX && STM32_I2S3 && !STM32_VALUELINE - -choice - prompt "TIM1 Alternate Pin Mappings" - depends on STM32_STM32F10XX && STM32_TIM1 - default STM32_TIM1_NO_REMAP - -config STM32_TIM1_NO_REMAP - bool "No pin remapping" - -config STM32_TIM1_FULL_REMAP - bool "Full pin remapping" - -config STM32_TIM1_PARTIAL_REMAP - bool "Partial pin remapping" - -endchoice - -choice - prompt "TIM2 Alternate Pin Mappings" - depends on STM32_STM32F10XX && STM32_TIM2 - default STM32_TIM2_NO_REMAP - -config STM32_TIM2_NO_REMAP - bool "No pin remapping" - -config STM32_TIM2_FULL_REMAP - bool "Full pin remapping" - -config STM32_TIM2_PARTIAL_REMAP_1 - bool "Partial pin remapping #1" - -config STM32_TIM2_PARTIAL_REMAP_2 - bool "Partial pin remapping #2" - -endchoice - -choice - prompt "TIM3 Alternate Pin Mappings" - depends on STM32_STM32F10XX && STM32_TIM3 - default STM32_TIM3_NO_REMAP - -config STM32_TIM3_NO_REMAP - bool "No pin remapping" - -config STM32_TIM3_FULL_REMAP - bool "Full pin remapping" - -config STM32_TIM3_PARTIAL_REMAP - bool "Partial pin remapping" - -endchoice - -config STM32_TIM4_REMAP - bool "TIM4 Alternate Pin Mapping" - default n - depends on STM32_STM32F10XX && STM32_TIM4 - -config STM32_TIM9_REMAP - bool "TIM9 Alternate Pin Mapping" - default n - depends on STM32_STM32F10XX && STM32_TIM9 - -config STM32_TIM10_REMAP - bool "TIM10 Alternate Pin Mapping" - default n - depends on STM32_STM32F10XX && STM32_TIM10 - -config STM32_TIM11_REMAP - bool "TIM11 Alternate Pin Mapping" - default n - depends on STM32_STM32F10XX && STM32_TIM11 - -config STM32_TIM12_REMAP - bool "TIM12 Alternate Pin Mapping" - default n - depends on STM32_STM32F10XX && STM32_TIM12 - -config STM32_TIM13_REMAP - bool "TIM13 Alternate Pin Mapping" - default n - depends on STM32_STM32F10XX && STM32_TIM13 - -config STM32_TIM14_REMAP - bool "TIM14 Alternate Pin Mapping" - default n - depends on STM32_STM32F10XX && STM32_TIM14 - -config STM32_TIM15_REMAP - bool "TIM15 Alternate Pin Mapping" - default n - depends on STM32_STM32F10XX && STM32_TIM15 - -config STM32_TIM16_REMAP - bool "TIM16 Alternate Pin Mapping" - default n - depends on STM32_STM32F10XX && STM32_TIM16 - -config STM32_TIM17_REMAP - bool "TIM17 Alternate Pin Mapping" - default n - depends on STM32_STM32F10XX && STM32_TIM17 - -config STM32_USART1_REMAP - bool "USART1 Alternate Pin Mapping" - default n - depends on STM32_STM32F10XX && STM32_USART1 - -config STM32_USART2_REMAP - bool "USART2 Alternate Pin Mapping" - default n - depends on STM32_STM32F10XX && STM32_USART2 - -choice - prompt "USART3 Alternate Pin Mappings" - depends on STM32_STM32F10XX && STM32_USART3 - default STM32_USART3_NO_REMAP - -config STM32_USART3_NO_REMAP - bool "No pin remapping" - -config STM32_USART3_FULL_REMAP - bool "Full pin remapping" - -config STM32_USART3_PARTIAL_REMAP - bool "Partial pin remapping" - -endchoice - -endmenu - -config STM32_FLASH_ICACHE - bool "Enable FLASH Instruction Cache" - default y - depends on STM32_HAVE_FLASH_ICACHE - ---help--- - Enable the FLASH instruction cache. - -config STM32_FLASH_DCACHE - bool "Enable FLASH Data Cache" - default y - depends on STM32_HAVE_FLASH_DCACHE - ---help--- - Enable the FLASH data cache. - -config STM32_FLASH_WORKAROUND_DATA_CACHE_CORRUPTION_ON_RWW - bool "Workaround for FLASH data cache corruption" - default n - depends on (STM32_STM32F20XX || STM32_STM32F4XXX) && STM32_FLASH_DCACHE - ---help--- - Enable the workaround to fix flash data cache corruption when reading - from one flash bank while writing on other flash bank. See your STM32 - errata to check if your STM32 is affected by this problem. - -config STM32_FLASH_PREFETCH - bool "Enable FLASH Pre-fetch" - default STM32_STM32F427 || STM32_STM32F429 || STM32_STM32F446 - default n - depends on STM32_STM32F20XX || STM32_STM32F4XXX - ---help--- - Enable FLASH prefetch in F2 and F4 parts (FLASH pre-fetch is always enabled - on F1 parts). Some early revisions of F4 parts do not support FLASH pre-fetch - properly and enabling this option may interfere with ADC accuracy. - -choice - prompt "JTAG Configuration" - default STM32_JTAG_DISABLE - ---help--- - JTAG Enable settings (by default JTAG-DP and SW-DP are disabled) - -config STM32_JTAG_DISABLE - bool "Disable all JTAG clocking" - -config STM32_JTAG_FULL_ENABLE - bool "Enable full SWJ (JTAG-DP + SW-DP)" - -config STM32_JTAG_NOJNTRST_ENABLE - bool "Enable full SWJ (JTAG-DP + SW-DP) but without JNTRST" - -config STM32_JTAG_SW_ENABLE - bool "Set JTAG-DP disabled and SW-DP enabled" - -endchoice - -config STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG - bool "Disable IDLE Sleep (WFI) in debug mode" - default n - ---help--- - In debug configuration, disables the WFI instruction in the IDLE loop - to prevent the JTAG from disconnecting. With some JTAG debuggers, such - as the ST-LINK2 with OpenOCD, if the ARM is put to sleep via the WFI - instruction, the debugger will disconnect, terminating the debug session. - -config STM32_FORCEPOWER - bool "Force power" - default n - ---help--- - Timer and I2C devices may need to the following to force power to be applied - unconditionally at power up. (Otherwise, the device is powered when it is - initialized). - -config ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG - bool "Custom clock configuration" - default n - ---help--- - Enables special, board-specific STM32 clock configuration. - -config STM32_SAIPLL - bool "SAIPLL" - default n - depends on STM32_HAVE_SAIPLL - ---help--- - The STM32F446 has a separate PLL for the SAI block. - Set this true and provide configuration parameters in - board.h to use this PLL. - -config STM32_I2SPLL - bool "I2SPLL" - default n - depends on STM32_HAVE_I2SPLL - ---help--- - The STM32F446 has a separate PLL for the I2S block. - Set this true and provide configuration parameters in - board.h to use this PLL. - -config STM32_CCMEXCLUDE - bool "Exclude CCM SRAM from the heap" - default ARCH_DMA || LIBC_ARCH_ELF - depends on STM32_HAVE_CCM - ---help--- - Exclude CCM SRAM from the HEAP because (1) it cannot be used for DMA - and (2) it appears to be impossible to execute ELF modules from CCM - RAM. - -config STM32_CCM_PROCFS - bool "CCM PROCFS support" - default n - depends on !DISABLE_MOUNTPOINT && FS_PROCFS && FS_PROCFS_REGISTER - ---help--- - Select to build in support for /proc/ccm. Reading from /proc/ccm - will provide statistics about CCM memory use similar to what you - would get from mallinfo() for the user heap. - -config STM32_DMACAPABLE - bool "Workaround non-DMA capable memory" - depends on ARCH_DMA - default STM32_STM32F4XXX && !STM32_CCMEXCLUDE - ---help--- - This option enables the DMA interface stm32_dmacapable that can be - used to check if it is possible to do DMA from the selected address. - Drivers then may use this information to determine if they should - attempt the DMA or fall back to a different transfer method. - -config STM32_EXTERNAL_RAM - bool "External RAM on FSMC/FMC" - default n - depends on STM32_FSMC || STM32_FMC - select ARCH_HAVE_HEAP2 - ---help--- - In addition to internal SRAM, external RAM may be available through the FSMC/FMC. - -menu "Timer Configuration" - depends on STM32_TIM - -if SCHED_TICKLESS - -config STM32_TICKLESS_TIMER - int "Tickless hardware timer" - default 2 - range 1 14 - ---help--- - If the Tickless OS feature is enabled, then one clock must be - assigned to provided the timer needed by the OS. - -config STM32_TICKLESS_CHANNEL - int "Tickless timer channel" - default 1 - range 1 4 - ---help--- - If the Tickless OS feature is enabled, the one clock must be - assigned to provided the free-running timer needed by the OS - and one channel on that clock is needed to handle intervals. - -endif # SCHED_TICKLESS - -config STM32_ONESHOT - bool "TIM one-shot wrapper" - default n - ---help--- - Enable a wrapper around the low level timer/counter functions to - support one-shot timer. - -config STM32_FREERUN - bool "TIM free-running wrapper" - default n - ---help--- - Enable a wrapper around the low level timer/counter functions to - support a free-running timer. - -config STM32_ONESHOT_MAXTIMERS - int "Maximum number of oneshot timers" - default 1 - range 1 8 - depends on STM32_ONESHOT - ---help--- - Determines the maximum number of oneshot timers that can be - supported. This setting pre-allocates some minimal support for each - of the timers and places an upper limit on the number of oneshot - timers that you can use. - -config STM32_PWM_LL_OPS - bool "PWM low-level operations" - default n - ---help--- - Enable low-level PWM ops. - -config STM32_TIM1_PWM - bool "TIM1 PWM" - default n - depends on STM32_TIM1 - select STM32_PWM - ---help--- - Reserve timer 1 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32_TIM1 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32_TIM1_PWM - -config STM32_TIM1_MODE - int "TIM1 Mode" - default 0 - range 0 4 - ---help--- - Specifies the timer mode. - -config STM32_TIM1_LOCK - int "TIM1 Lock Level Configuration" - default 0 - range 0 3 - ---help--- - Timer 1 lock level configuration - -config STM32_TIM1_TDTS - int "TIM1 t_DTS Division" - default 0 - range 0 2 - ---help--- - Timer 1 dead-time and sampling clock (t_DTS) division - -config STM32_TIM1_DEADTIME - int "TIM1 Initial Dead-time" - default 0 - range 0 255 - ---help--- - Timer 1 initial dead-time - -if STM32_PWM_MULTICHAN - -config STM32_TIM1_CHANNEL1 - bool "TIM1 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32_TIM1_CHANNEL1 - -config STM32_TIM1_CH1MODE - int "TIM1 Channel 1 Mode" - default 6 - range 0 11 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM1_CH1OUT - bool "TIM1 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -config STM32_TIM1_CH1NOUT - bool "TIM1 Channel 1 Complementary Output" - default n - ---help--- - Enables channel 1 Complementary Output. - -endif # STM32_TIM1_CHANNEL1 - -config STM32_TIM1_CHANNEL2 - bool "TIM1 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32_TIM1_CHANNEL2 - -config STM32_TIM1_CH2MODE - int "TIM1 Channel 2 Mode" - default 6 - range 0 11 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM1_CH2OUT - bool "TIM1 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -config STM32_TIM1_CH2NOUT - bool "TIM1 Channel 2 Complementary Output" - default n - ---help--- - Enables channel 2 Complementary Output. - -endif # STM32_TIM1_CHANNEL2 - -config STM32_TIM1_CHANNEL3 - bool "TIM1 Channel 3" - default n - ---help--- - Enables channel 3. - -if STM32_TIM1_CHANNEL3 - -config STM32_TIM1_CH3MODE - int "TIM1 Channel 3 Mode" - default 6 - range 0 11 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM1_CH3OUT - bool "TIM1 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -config STM32_TIM1_CH3NOUT - bool "TIM1 Channel 3 Complementary Output" - default n - ---help--- - Enables channel 3 Complementary Output. - -endif # STM32_TIM1_CHANNEL3 - -config STM32_TIM1_CHANNEL4 - bool "TIM1 Channel 4" - default n - ---help--- - Enables channel 4. - -if STM32_TIM1_CHANNEL4 - -config STM32_TIM1_CH4MODE - int "TIM1 Channel 4 Mode" - default 6 - range 0 11 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM1_CH4OUT - bool "TIM1 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32_TIM1_CHANNEL4 - -config STM32_TIM1_CHANNEL5 - bool "TIM1 Channel 5 (internal)" - default n - depends on STM32_HAVE_IP_TIMERS_V2 - ---help--- - Enables channel 5 (not available externally) - -if STM32_TIM1_CHANNEL5 - -config STM32_TIM1_CH5MODE - int "TIM1 Channel 5 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM1_CH5OUT - bool "TIM1 Channel 5 Output" - default n - ---help--- - Enables channel 5 output. - -endif # STM32_TIM1_CHANNEL5 - -config STM32_TIM1_CHANNEL6 - bool "TIM1 Channel 6 (internal)" - default n - depends on STM32_HAVE_IP_TIMERS_V2 - ---help--- - Enables channel 6 (not available externally) - -if STM32_TIM1_CHANNEL6 - -config STM32_TIM1_CH6MODE - int "TIM1 Channel 6 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM1_CH6OUT - bool "TIM1 Channel 6 Output" - default n - ---help--- - Enables channel 6 output. - -endif # STM32_TIM1_CHANNEL6 - -endif # STM32_PWM_MULTICHAN - -if !STM32_PWM_MULTICHAN - -config STM32_TIM1_CHANNEL - int "TIM1 PWM Output Channel" - default 1 - range 1 4 - ---help--- - If TIM1 is enabled for PWM usage, you also need specifies the timer output - channel {1,..,4} - -if STM32_TIM1_CHANNEL = 1 - -config STM32_TIM1_CH1OUT - bool "TIM1 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -config STM32_TIM1_CH1NOUT - bool "TIM1 Channel 1 Complementary Output" - default n - ---help--- - Enables channel 1 Complementary Output. - -endif # STM32_TIM1_CHANNEL = 1 - -if STM32_TIM1_CHANNEL = 2 - -config STM32_TIM1_CH2OUT - bool "TIM1 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -config STM32_TIM1_CH2NOUT - bool "TIM1 Channel 2 Complementary Output" - default n - ---help--- - Enables channel 2 Complementary Output. - -endif # STM32_TIM1_CHANNEL = 2 - -if STM32_TIM1_CHANNEL = 3 - -config STM32_TIM1_CH3OUT - bool "TIM1 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -config STM32_TIM1_CH3NOUT - bool "TIM1 Channel 3 Complementary Output" - default n - ---help--- - Enables channel 3 Complementary Output. - -endif # STM32_TIM1_CHANNEL = 3 - -if STM32_TIM1_CHANNEL = 4 - -config STM32_TIM1_CH4OUT - bool "TIM1 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32_TIM1_CHANNEL = 4 - -config STM32_TIM1_CHMODE - int "TIM1 Channel Mode" - default 6 - range 0 11 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32_PWM_MULTICHAN - -endif # STM32_TIM1_PWM - -config STM32_TIM2_PWM - bool "TIM2 PWM" - default n - depends on STM32_TIM2 - select STM32_PWM - ---help--- - Reserve timer 2 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32_TIM2 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32_TIM2_PWM - -config STM32_TIM2_MODE - int "TIM2 Mode" - default 0 - range 0 4 - ---help--- - Specifies the timer mode. - -if STM32_PWM_MULTICHAN - -config STM32_TIM2_CHANNEL1 - bool "TIM2 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32_TIM2_CHANNEL1 - -config STM32_TIM2_CH1MODE - int "TIM2 Channel 1 Mode" - default 6 - range 0 11 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM2_CH1OUT - bool "TIM2 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32_TIM2_CHANNEL1 - -config STM32_TIM2_CHANNEL2 - bool "TIM2 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32_TIM2_CHANNEL2 - -config STM32_TIM2_CH2MODE - int "TIM2 Channel 2 Mode" - default 6 - range 0 11 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM2_CH2OUT - bool "TIM2 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32_TIM2_CHANNEL2 - -config STM32_TIM2_CHANNEL3 - bool "TIM2 Channel 3" - default n - ---help--- - Enables channel 3. - -if STM32_TIM2_CHANNEL3 - -config STM32_TIM2_CH3MODE - int "TIM2 Channel 3 Mode" - default 6 - range 0 11 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM2_CH3OUT - bool "TIM2 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -endif # STM32_TIM2_CHANNEL3 - -config STM32_TIM2_CHANNEL4 - bool "TIM2 Channel 4" - default n - ---help--- - Enables channel 4. - -if STM32_TIM2_CHANNEL4 - -config STM32_TIM2_CH4MODE - int "TIM2 Channel 4 Mode" - default 6 - range 0 11 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM2_CH4OUT - bool "TIM2 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32_TIM2_CHANNEL4 - -endif # STM32_PWM_MULTICHAN - -if !STM32_PWM_MULTICHAN - -config STM32_TIM2_CHANNEL - int "TIM2 PWM Output Channel" - default 1 - range 1 4 - ---help--- - If TIM2 is enabled for PWM usage, you also need specifies the timer output - channel {1,..,4} - -if STM32_TIM2_CHANNEL = 1 - -config STM32_TIM2_CH1OUT - bool "TIM2 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32_TIM2_CHANNEL = 1 - -if STM32_TIM2_CHANNEL = 2 - -config STM32_TIM2_CH2OUT - bool "TIM2 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32_TIM2_CHANNEL = 2 - -if STM32_TIM2_CHANNEL = 3 - -config STM32_TIM2_CH3OUT - bool "TIM2 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -endif # STM32_TIM2_CHANNEL = 3 - -if STM32_TIM2_CHANNEL = 4 - -config STM32_TIM2_CH4OUT - bool "TIM2 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32_TIM2_CHANNEL = 4 - -config STM32_TIM2_CHMODE - int "TIM2 Channel Mode" - default 6 - range 0 11 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32_PWM_MULTICHAN - -endif # STM32_TIM2_PWM - -config STM32_TIM3_PWM - bool "TIM3 PWM" - default n - depends on STM32_TIM3 - select STM32_PWM - ---help--- - Reserve timer 3 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32_TIM3 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32_TIM3_PWM - -config STM32_TIM3_MODE - int "TIM3 Mode" - default 0 - range 0 4 - ---help--- - Specifies the timer mode. - -if STM32_PWM_MULTICHAN - -config STM32_TIM3_CHANNEL1 - bool "TIM3 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32_TIM3_CHANNEL1 - -config STM32_TIM3_CH1MODE - int "TIM3 Channel 1 Mode" - default 6 - range 0 11 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM3_CH1OUT - bool "TIM3 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32_TIM3_CHANNEL1 - -config STM32_TIM3_CHANNEL2 - bool "TIM3 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32_TIM3_CHANNEL2 - -config STM32_TIM3_CH2MODE - int "TIM3 Channel 2 Mode" - default 6 - range 0 11 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM3_CH2OUT - bool "TIM3 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32_TIM3_CHANNEL2 - -config STM32_TIM3_CHANNEL3 - bool "TIM3 Channel 3" - default n - ---help--- - Enables channel 3. - -if STM32_TIM3_CHANNEL3 - -config STM32_TIM3_CH3MODE - int "TIM3 Channel 3 Mode" - default 6 - range 0 11 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM3_CH3OUT - bool "TIM3 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -endif # STM32_TIM3_CHANNEL3 - -config STM32_TIM3_CHANNEL4 - bool "TIM3 Channel 4" - default n - ---help--- - Enables channel 4. - -if STM32_TIM3_CHANNEL4 - -config STM32_TIM3_CH4MODE - int "TIM3 Channel 4 Mode" - default 6 - range 0 11 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM3_CH4OUT - bool "TIM3 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32_TIM3_CHANNEL4 - -endif # STM32_PWM_MULTICHAN - -if !STM32_PWM_MULTICHAN - -config STM32_TIM3_CHANNEL - int "TIM3 PWM Output Channel" - default 1 - range 1 4 - ---help--- - If TIM3 is enabled for PWM usage, you also need specifies the timer output - channel {1,..,4} - -if STM32_TIM3_CHANNEL = 1 - -config STM32_TIM3_CH1OUT - bool "TIM3 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32_TIM3_CHANNEL = 1 - -if STM32_TIM3_CHANNEL = 2 - -config STM32_TIM3_CH2OUT - bool "TIM3 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32_TIM3_CHANNEL = 2 - -if STM32_TIM3_CHANNEL = 3 - -config STM32_TIM3_CH3OUT - bool "TIM3 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -endif # STM32_TIM3_CHANNEL = 3 - -if STM32_TIM3_CHANNEL = 4 - -config STM32_TIM3_CH4OUT - bool "TIM3 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32_TIM3_CHANNEL = 4 - -config STM32_TIM3_CHMODE - int "TIM3 Channel Mode" - default 6 - range 0 11 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32_PWM_MULTICHAN - -endif # STM32_TIM3_PWM - -config STM32_TIM4_PWM - bool "TIM4 PWM" - default n - depends on STM32_TIM4 - select STM32_PWM - ---help--- - Reserve timer 4 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32_TIM4 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32_TIM4_PWM - -config STM32_TIM4_MODE - int "TIM4 Mode" - default 0 - range 0 4 - ---help--- - Specifies the timer mode. - -if STM32_PWM_MULTICHAN - -config STM32_TIM4_CHANNEL1 - bool "TIM4 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32_TIM4_CHANNEL1 - -config STM32_TIM4_CH1MODE - int "TIM4 Channel 1 Mode" - default 6 - range 0 11 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM4_CH1OUT - bool "TIM4 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32_TIM4_CHANNEL1 - -config STM32_TIM4_CHANNEL2 - bool "TIM4 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32_TIM4_CHANNEL2 - -config STM32_TIM4_CH2MODE - int "TIM4 Channel 2 Mode" - default 6 - range 0 11 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM4_CH2OUT - bool "TIM4 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32_TIM4_CHANNEL2 - -config STM32_TIM4_CHANNEL3 - bool "TIM4 Channel 3" - default n - ---help--- - Enables channel 3. - -if STM32_TIM4_CHANNEL3 - -config STM32_TIM4_CH3MODE - int "TIM4 Channel 3 Mode" - default 6 - range 0 11 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM4_CH3OUT - bool "TIM4 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -endif # STM32_TIM4_CHANNEL3 - -config STM32_TIM4_CHANNEL4 - bool "TIM4 Channel 4" - default n - ---help--- - Enables channel 4. - -if STM32_TIM4_CHANNEL4 - -config STM32_TIM4_CH4MODE - int "TIM4 Channel 4 Mode" - default 6 - range 0 11 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM4_CH4OUT - bool "TIM4 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32_TIM4_CHANNEL4 - -endif # STM32_PWM_MULTICHAN - -if !STM32_PWM_MULTICHAN - -config STM32_TIM4_CHANNEL - int "TIM4 PWM Output Channel" - default 1 - range 1 4 - ---help--- - If TIM4 is enabled for PWM usage, you also need specifies the timer output - channel {1,..,4} - -if STM32_TIM4_CHANNEL = 1 - -config STM32_TIM4_CH1OUT - bool "TIM4 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32_TIM4_CHANNEL = 1 - -if STM32_TIM4_CHANNEL = 2 - -config STM32_TIM4_CH2OUT - bool "TIM4 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32_TIM4_CHANNEL = 2 - -if STM32_TIM4_CHANNEL = 3 - -config STM32_TIM4_CH3OUT - bool "TIM4 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -endif # STM32_TIM4_CHANNEL = 3 - -if STM32_TIM4_CHANNEL = 4 - -config STM32_TIM4_CH4OUT - bool "TIM4 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32_TIM4_CHANNEL = 4 - -config STM32_TIM4_CHMODE - int "TIM4 Channel Mode" - default 6 - range 0 11 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32_PWM_MULTICHAN - -endif # STM32_TIM4_PWM - -config STM32_TIM5_PWM - bool "TIM5 PWM" - default n - depends on STM32_TIM5 - select STM32_PWM - ---help--- - Reserve timer 5 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32_TIM5 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32_TIM5_PWM - -config STM32_TIM5_MODE - int "TIM5 Mode" - default 0 - range 0 4 - ---help--- - Specifies the timer mode. - -if STM32_PWM_MULTICHAN - -config STM32_TIM5_CHANNEL1 - bool "TIM5 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32_TIM5_CHANNEL1 - -config STM32_TIM5_CH1MODE - int "TIM5 Channel 1 Mode" - default 6 - range 0 11 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM5_CH1OUT - bool "TIM5 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32_TIM5_CHANNEL1 - -config STM32_TIM5_CHANNEL2 - bool "TIM5 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32_TIM5_CHANNEL2 - -config STM32_TIM5_CH2MODE - int "TIM5 Channel 2 Mode" - default 6 - range 0 11 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM5_CH2OUT - bool "TIM5 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32_TIM5_CHANNEL2 - -config STM32_TIM5_CHANNEL3 - bool "TIM5 Channel 3" - default n - ---help--- - Enables channel 3. - -if STM32_TIM5_CHANNEL3 - -config STM32_TIM5_CH3MODE - int "TIM5 Channel 3 Mode" - default 6 - range 0 11 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM5_CH3OUT - bool "TIM5 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -endif # STM32_TIM5_CHANNEL3 - -config STM32_TIM5_CHANNEL4 - bool "TIM5 Channel 4" - default n - ---help--- - Enables channel 4. - -if STM32_TIM5_CHANNEL4 - -config STM32_TIM5_CH4MODE - int "TIM5 Channel 4 Mode" - default 6 - range 0 11 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM5_CH4OUT - bool "TIM5 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32_TIM5_CHANNEL4 - -endif # STM32_PWM_MULTICHAN - -if !STM32_PWM_MULTICHAN - -config STM32_TIM5_CHANNEL - int "TIM5 PWM Output Channel" - default 1 - range 1 4 - ---help--- - If TIM5 is enabled for PWM usage, you also need specifies the timer output - channel {1,..,4} - -if STM32_TIM5_CHANNEL = 1 - -config STM32_TIM5_CH1OUT - bool "TIM5 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32_TIM5_CHANNEL = 1 - -if STM32_TIM5_CHANNEL = 2 - -config STM32_TIM5_CH2OUT - bool "TIM5 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32_TIM5_CHANNEL = 2 - -if STM32_TIM5_CHANNEL = 3 - -config STM32_TIM5_CH3OUT - bool "TIM5 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -endif # STM32_TIM5_CHANNEL = 3 - -if STM32_TIM5_CHANNEL = 4 - -config STM32_TIM5_CH4OUT - bool "TIM5 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32_TIM5_CHANNEL = 4 - -config STM32_TIM5_CHMODE - int "TIM5 Channel Mode" - default 6 - range 0 11 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32_PWM_MULTICHAN - -endif # STM32_TIM5_PWM - -config STM32_TIM8_PWM - bool "TIM8 PWM" - default n - depends on STM32_TIM8 - select STM32_PWM - ---help--- - Reserve timer 8 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32_TIM8 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32_TIM8_PWM - -config STM32_TIM8_MODE - int "TIM8 Mode" - default 0 - range 0 4 - ---help--- - Specifies the timer mode. - -config STM32_TIM8_LOCK - int "TIM8 Lock Level Configuration" - default 0 - range 0 3 - ---help--- - Timer 8 lock level configuration - -config STM32_TIM8_DEADTIME - int "TIM8 Initial Dead-time" - default 0 - range 0 255 - ---help--- - Timer 8 initial dead-time - -config STM32_TIM8_TDTS - int "TIM8 t_DTS Division" - default 0 - range 0 2 - ---help--- - Timer 8 dead-time and sampling clock (t_DTS) division - -if STM32_PWM_MULTICHAN - -config STM32_TIM8_CHANNEL1 - bool "TIM8 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32_TIM8_CHANNEL1 - -config STM32_TIM8_CH1MODE - int "TIM8 Channel 1 Mode" - default 6 - range 0 11 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM8_CH1OUT - bool "TIM8 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -config STM32_TIM8_CH1NOUT - bool "TIM8 Channel 1 Complementary Output" - default n - ---help--- - Enables channel 1 Complementary Output. - -endif # STM32_TIM8_CHANNEL1 - -config STM32_TIM8_CHANNEL2 - bool "TIM8 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32_TIM8_CHANNEL2 - -config STM32_TIM8_CH2MODE - int "TIM8 Channel 2 Mode" - default 6 - range 0 11 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM8_CH2OUT - bool "TIM8 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -config STM32_TIM8_CH2NOUT - bool "TIM8 Channel 2 Complementary Output" - default n - ---help--- - Enables channel 2 Complementary Output. - -endif # STM32_TIM8_CHANNEL2 - -config STM32_TIM8_CHANNEL3 - bool "TIM8 Channel 3" - default n - ---help--- - Enables channel 3. - -if STM32_TIM8_CHANNEL3 - -config STM32_TIM8_CH3MODE - int "TIM8 Channel 3 Mode" - default 6 - range 0 11 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM8_CH3OUT - bool "TIM8 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -config STM32_TIM8_CH3NOUT - bool "TIM8 Channel 3 Complementary Output" - default n - ---help--- - Enables channel 3 Complementary Output. - -endif # STM32_TIM8_CHANNEL3 - -config STM32_TIM8_CHANNEL4 - bool "TIM8 Channel 4" - default n - ---help--- - Enables channel 4. - -if STM32_TIM8_CHANNEL4 - -config STM32_TIM8_CH4MODE - int "TIM8 Channel 4 Mode" - default 6 - range 0 11 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM8_CH4OUT - bool "TIM8 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32_TIM8_CHANNEL4 - -config STM32_TIM8_CHANNEL5 - bool "TIM8 Channel 5 (internal)" - default n - depends on STM32_HAVE_IP_TIMERS_V2 - ---help--- - Enables channel 5 (not available externally) - -if STM32_TIM8_CHANNEL5 - -config STM32_TIM8_CH5MODE - int "TIM8 Channel 5 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM8_CH5OUT - bool "TIM8 Channel 5 Output" - default n - ---help--- - Enables channel 5 output. - -endif # STM32_TIM8_CHANNEL5 - -config STM32_TIM8_CHANNEL6 - bool "TIM8 Channel 6 (internal)" - default n - depends on STM32_HAVE_IP_TIMERS_V2 - ---help--- - Enables channel 6 (not available externally) - -if STM32_TIM8_CHANNEL6 - -config STM32_TIM8_CH6MODE - int "TIM8 Channel 6 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM8_CH6OUT - bool "TIM8 Channel 6 Output" - default n - ---help--- - Enables channel 6 output. - -endif # STM32_TIM8_CHANNEL6 - -endif # STM32_PWM_MULTICHAN - -if !STM32_PWM_MULTICHAN - -config STM32_TIM8_CHANNEL - int "TIM8 PWM Output Channel" - default 1 - range 1 4 - ---help--- - If TIM8 is enabled for PWM usage, you also need specifies the timer output - channel {1,..,4} - -if STM32_TIM8_CHANNEL = 1 - -config STM32_TIM8_CH1OUT - bool "TIM8 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -config STM32_TIM8_CH1NOUT - bool "TIM8 Channel 1 Complementary Output" - default n - ---help--- - Enables channel 1 Complementary Output. - -endif # STM32_TIM8_CHANNEL = 1 - -if STM32_TIM8_CHANNEL = 2 - -config STM32_TIM8_CH2OUT - bool "TIM8 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -config STM32_TIM8_CH2NOUT - bool "TIM8 Channel 2 Complementary Output" - default n - ---help--- - Enables channel 2 Complementary Output. - -endif # STM32_TIM8_CHANNEL = 2 - -if STM32_TIM8_CHANNEL = 3 - -config STM32_TIM8_CH3OUT - bool "TIM8 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -config STM32_TIM8_CH3NOUT - bool "TIM8 Channel 3 Complementary Output" - default n - ---help--- - Enables channel 3 Complementary Output. - -endif # STM32_TIM8_CHANNEL = 3 - -if STM32_TIM8_CHANNEL = 4 - -config STM32_TIM8_CH4OUT - bool "TIM8 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32_TIM8_CHANNEL = 4 - -config STM32_TIM8_CHMODE - int "TIM8 Channel Mode" - default 6 - range 0 11 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32_PWM_MULTICHAN - -endif # STM32_TIM8_PWM - -config STM32_TIM9_PWM - bool "TIM9 PWM" - default n - depends on STM32_TIM9 - select STM32_PWM - ---help--- - Reserve timer 9 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32_TIM9 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32_TIM9_PWM - -if STM32_PWM_MULTICHAN - -config STM32_TIM9_CHANNEL1 - bool "TIM9 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32_TIM9_CHANNEL1 - -config STM32_TIM9_CH1MODE - int "TIM9 Channel 1 Mode" - default 6 - range 0 11 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM9_CH1OUT - bool "TIM9 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32_TIM9_CHANNEL1 - -config STM32_TIM9_CHANNEL2 - bool "TIM9 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32_TIM9_CHANNEL2 - -config STM32_TIM9_CH2MODE - int "TIM9 Channel 2 Mode" - default 6 - range 0 11 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM9_CH2OUT - bool "TIM9 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32_TIM9_CHANNEL2 - -endif # STM32_PWM_MULTICHAN - -if !STM32_PWM_MULTICHAN - -config STM32_TIM9_CHANNEL - int "TIM9 PWM Output Channel" - default 1 - range 1 2 - ---help--- - If TIM9 is enabled for PWM usage, you also need specifies the timer output - channel {1,2} - -if STM32_TIM9_CHANNEL = 1 - -config STM32_TIM9_CH1OUT - bool "TIM9 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32_TIM9_CHANNEL = 1 - -if STM32_TIM9_CHANNEL = 2 - -config STM32_TIM9_CH2OUT - bool "TIM9 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32_TIM9_CHANNEL = 2 - -config STM32_TIM9_CHMODE - int "TIM9 Channel Mode" - default 6 - range 0 11 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32_PWM_MULTICHAN - -endif # STM32_TIM9_PWM - -config STM32_TIM10_PWM - bool "TIM10 PWM" - default n - depends on STM32_TIM10 - select STM32_PWM - ---help--- - Reserve timer 10 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32_TIM10 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32_TIM10_PWM - -if STM32_PWM_MULTICHAN - -config STM32_TIM10_CHANNEL1 - bool "TIM10 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32_TIM10_CHANNEL1 - -config STM32_TIM10_CH1MODE - int "TIM10 Channel 1 Mode" - default 6 - range 0 11 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM10_CH1OUT - bool "TIM10 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32_TIM10_CHANNEL1 - -endif # STM32_PWM_MULTICHAN - -if !STM32_PWM_MULTICHAN - -config STM32_TIM10_CHANNEL - int "TIM10 PWM Output Channel" - default 1 - range 1 1 - ---help--- - If TIM10 is enabled for PWM usage, you also need specifies the timer output - channel {1} - -if STM32_TIM10_CHANNEL = 1 - -config STM32_TIM10_CH1OUT - bool "TIM10 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32_TIM10_CHANNEL = 1 - -config STM32_TIM10_CHMODE - int "TIM10 Channel Mode" - default 6 - range 0 11 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32_PWM_MULTICHAN - -endif # STM32_TIM10_PWM - -config STM32_TIM11_PWM - bool "TIM11 PWM" - default n - depends on STM32_TIM11 - select STM32_PWM - ---help--- - Reserve timer 11 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32_TIM11 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32_TIM11_PWM - -if STM32_PWM_MULTICHAN - -config STM32_TIM11_CHANNEL1 - bool "TIM11 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32_TIM11_CHANNEL1 - -config STM32_TIM11_CH1MODE - int "TIM11 Channel 1 Mode" - default 6 - range 0 11 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM11_CH1OUT - bool "TIM11 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32_TIM11_CHANNEL1 - -endif # STM32_PWM_MULTICHAN - -if !STM32_PWM_MULTICHAN - -config STM32_TIM11_CHANNEL - int "TIM11 PWM Output Channel" - default 1 - range 1 1 - ---help--- - If TIM11 is enabled for PWM usage, you also need specifies the timer output - channel {1} - -if STM32_TIM11_CHANNEL = 1 - -config STM32_TIM11_CH1OUT - bool "TIM11 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32_TIM11_CHANNEL = 1 - -config STM32_TIM11_CHMODE - int "TIM11 Channel Mode" - default 6 - range 0 11 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32_PWM_MULTICHAN - -endif # STM32_TIM11_PWM - -config STM32_TIM12_PWM - bool "TIM12 PWM" - default n - depends on STM32_TIM12 - select STM32_PWM - ---help--- - Reserve timer 12 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32_TIM12 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32_TIM12_PWM - -if STM32_PWM_MULTICHAN - -config STM32_TIM12_CHANNEL1 - bool "TIM12 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32_TIM12_CHANNEL1 - -config STM32_TIM12_CH1MODE - int "TIM12 Channel 1 Mode" - default 6 - range 0 11 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM12_CH1OUT - bool "TIM12 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32_TIM12_CHANNEL1 - -config STM32_TIM12_CHANNEL2 - bool "TIM12 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32_TIM12_CHANNEL2 - -config STM32_TIM12_CH2MODE - int "TIM12 Channel 2 Mode" - default 6 - range 0 11 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM12_CH2OUT - bool "TIM12 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32_TIM12_CHANNEL2 - -endif # STM32_PWM_MULTICHAN - -if !STM32_PWM_MULTICHAN - -config STM32_TIM12_CHANNEL - int "TIM12 PWM Output Channel" - default 1 - range 1 2 - ---help--- - If TIM12 is enabled for PWM usage, you also need specifies the timer output - channel {1,2} - -if STM32_TIM12_CHANNEL = 1 - -config STM32_TIM12_CH1OUT - bool "TIM12 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32_TIM12_CHANNEL = 1 - -if STM32_TIM12_CHANNEL = 2 - -config STM32_TIM12_CH2OUT - bool "TIM12 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32_TIM12_CHANNEL = 2 - -config STM32_TIM12_CHMODE - int "TIM12 Channel Mode" - default 6 - range 0 11 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32_PWM_MULTICHAN - -endif # STM32_TIM12_PWM - -config STM32_TIM13_PWM - bool "TIM13 PWM" - default n - depends on STM32_TIM13 - select STM32_PWM - ---help--- - Reserve timer 13 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32_TIM13 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32_TIM13_PWM - -if STM32_PWM_MULTICHAN - -config STM32_TIM13_CHANNEL1 - bool "TIM13 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32_TIM13_CHANNEL1 - -config STM32_TIM13_CH1MODE - int "TIM13 Channel 1 Mode" - default 6 - range 0 11 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM13_CH1OUT - bool "TIM13 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32_TIM13_CHANNEL1 - -endif # STM32_PWM_MULTICHAN - -if !STM32_PWM_MULTICHAN - -config STM32_TIM13_CHANNEL - int "TIM13 PWM Output Channel" - default 1 - range 1 1 - ---help--- - If TIM13 is enabled for PWM usage, you also need specifies the timer output - channel {1} - -if STM32_TIM13_CHANNEL = 1 - -config STM32_TIM13_CH1OUT - bool "TIM13 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32_TIM13_CHANNEL = 1 - -config STM32_TIM13_CHMODE - int "TIM13 Channel Mode" - default 6 - range 0 11 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32_PWM_MULTICHAN - -endif # STM32_TIM13_PWM - -config STM32_TIM14_PWM - bool "TIM14 PWM" - default n - depends on STM32_TIM14 - select STM32_PWM - ---help--- - Reserve timer 14 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32_TIM14 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32_TIM14_PWM - -if STM32_PWM_MULTICHAN - -config STM32_TIM14_CHANNEL1 - bool "TIM14 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32_TIM14_CHANNEL1 - -config STM32_TIM14_CH1MODE - int "TIM14 Channel 1 Mode" - default 6 - range 0 11 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM14_CH1OUT - bool "TIM14 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32_TIM14_CHANNEL1 - -endif # STM32_PWM_MULTICHAN - -if !STM32_PWM_MULTICHAN - -config STM32_TIM14_CHANNEL - int "TIM14 PWM Output Channel" - default 1 - range 1 1 - ---help--- - If TIM14 is enabled for PWM usage, you also need specifies the timer output - channel {1} - -if STM32_TIM14_CHANNEL = 1 - -config STM32_TIM14_CH1OUT - bool "TIM14 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32_TIM14_CHANNEL = 1 - -config STM32_TIM14_CHMODE - int "TIM14 Channel Mode" - default 6 - range 0 11 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32_PWM_MULTICHAN - -endif # STM32_TIM14_PWM - -config STM32_TIM15_PWM - bool "TIM15 PWM" - default n - depends on STM32_TIM15 - select STM32_PWM - ---help--- - Reserve timer 15 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32_TIM15 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32_TIM15_PWM - -config STM32_TIM15_LOCK - int "TIM15 Lock Level Configuration" - default 0 - range 0 3 - ---help--- - Timer 15 lock level configuration - -config STM32_TIM15_TDTS - int "TIM15 t_DTS Division" - default 0 - range 0 2 - ---help--- - Timer 15 dead-time and sampling clock (t_DTS) division - -config STM32_TIM15_DEADTIME - int "TIM15 Initial Dead-time" - default 0 - range 0 255 - ---help--- - Timer 15 initial dead-time - -if STM32_PWM_MULTICHAN - -config STM32_TIM15_CHANNEL1 - bool "TIM15 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32_TIM15_CHANNEL1 - -config STM32_TIM15_CH1MODE - int "TIM15 Channel 1 Mode" - default 6 - range 0 9 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM15_CH1OUT - bool "TIM15 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -config STM32_TIM15_CH1NOUT - bool "TIM15 Channel 1 Complementary Output" - default n - ---help--- - Enables channel 1 Complementary Output. - -endif # STM32_TIM15_CHANNEL1 - -config STM32_TIM15_CHANNEL2 - bool "TIM15 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32_TIM15_CHANNEL2 - -config STM32_TIM15_CH2MODE - int "TIM15 Channel 2 Mode" - default 6 - range 0 9 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM15_CH2OUT - bool "TIM15 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32_TIM15_CHANNEL2 - -endif # STM32_PWM_MULTICHAN - -if !STM32_PWM_MULTICHAN - -config STM32_TIM15_CHANNEL - int "TIM15 PWM Output Channel" - default 1 - range 1 2 - ---help--- - If TIM15 is enabled for PWM usage, you also need specifies the timer output - channel {1,2} - -if STM32_TIM15_CHANNEL = 1 - -config STM32_TIM15_CH1OUT - bool "TIM15 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -config STM32_TIM15_CH1NOUT - bool "TIM15 Channel 1 Complementary Output" - default n - ---help--- - Enables channel 1 Complementary Output. - -endif # STM32_TIM15_CHANNEL = 1 - -if STM32_TIM15_CHANNEL = 2 - -config STM32_TIM15_CH2OUT - bool "TIM15 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -config STM32_TIM15_CH2NOUT - bool "TIM15 Channel 2 Complementary Output" - default n - ---help--- - Enables channel 2 Complementary Output. - -endif # STM32_TIM15_CHANNEL = 2 - -config STM32_TIM15_CHMODE - int "TIM15 Channel Mode" - default 6 - range 0 9 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32_PWM_MULTICHAN - -endif # STM32_TIM15_PWM - -config STM32_TIM16_PWM - bool "TIM16 PWM" - default n - depends on STM32_TIM16 - select STM32_PWM - ---help--- - Reserve timer 16 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32_TIM16 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32_TIM16_PWM - -config STM32_TIM16_LOCK - int "TIM16 Lock Level Configuration" - default 0 - range 0 3 - ---help--- - Timer 16 lock level configuration - -config STM32_TIM16_TDTS - int "TIM16 t_DTS division" - default 0 - range 0 2 - ---help--- - Timer 16 dead-time and sampling clock (t_DTS) division - -config STM32_TIM16_DEADTIME - int "TIM16 Initial Dead-time" - default 0 - range 0 255 - ---help--- - Timer 16 initial dead-time - -if STM32_PWM_MULTICHAN - -config STM32_TIM16_CHANNEL1 - bool "TIM16 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32_TIM16_CHANNEL1 - -config STM32_TIM16_CH1MODE - int "TIM16 Channel 1 Mode" - default 6 - range 0 7 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM16_CH1OUT - bool "TIM16 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32_TIM16_CHANNEL1 - -endif # STM32_PWM_MULTICHAN - -if !STM32_PWM_MULTICHAN - -config STM32_TIM16_CHANNEL - int "TIM16 PWM Output Channel" - default 1 - range 1 1 - ---help--- - If TIM16 is enabled for PWM usage, you also need specifies the timer output - channel {1} - -if STM32_TIM16_CHANNEL = 1 - -config STM32_TIM16_CH1OUT - bool "TIM16 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32_TIM16_CHANNEL = 1 - -config STM32_TIM16_CHMODE - int "TIM16 Channel Mode" - default 6 - range 0 7 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32_PWM_MULTICHAN - -endif # STM32_TIM16_PWM - -config STM32_TIM17_PWM - bool "TIM17 PWM" - default n - depends on STM32_TIM17 - select STM32_PWM - ---help--- - Reserve timer 17 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32_TIM17 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32_TIM17_PWM - -config STM32_TIM17_LOCK - int "TIM17 Lock Level Configuration" - default 0 - range 0 3 - ---help--- - Timer 17 lock level configuration - -config STM32_TIM17_TDTS - int "TIM17 t_DTS Division" - default 0 - range 0 2 - ---help--- - Timer 17 dead-time and sampling clock (t_DTS) division - -config STM32_TIM17_DEADTIME - int "TIM17 Initial Dead-time" - default 0 - range 0 255 - ---help--- - Timer 17 initial dead-time - -if STM32_PWM_MULTICHAN - -config STM32_TIM17_CHANNEL1 - bool "TIM17 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32_TIM17_CHANNEL1 - -config STM32_TIM17_CH1MODE - int "TIM17 Channel 1 Mode" - default 6 - range 0 7 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM17_CH1OUT - bool "TIM17 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32_TIM17_CHANNEL1 - -endif # STM32_PWM_MULTICHAN - -if !STM32_PWM_MULTICHAN - -config STM32_TIM17_CHANNEL - int "TIM17 PWM Output Channel" - default 1 - range 1 1 - ---help--- - If TIM17 is enabled for PWM usage, you also need specifies the timer output - channel {1} - -if STM32_TIM17_CHANNEL = 1 - -config STM32_TIM17_CH1OUT - bool "TIM17 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32_TIM17_CHANNEL = 1 - -config STM32_TIM17_CHMODE - int "TIM17 Channel Mode" - default 6 - range 0 7 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32_PWM_MULTICHAN - -endif # STM32_TIM17_PWM - -config STM32_PWM_MULTICHAN - bool "PWM Multiple Output Channels" - default n - depends on STM32_PWM - ---help--- - Specifies that the PWM driver supports multiple output - channels per timer. - -config STM32_PWM_TRGO - bool "TIM PWM TRGO support" - default n - depends on STM32_PWM - ---help--- - Enable TRGO support for PWM driver - -config STM32_PULSECOUNT - bool - default n - select ARCH_HAVE_PULSECOUNT - select PULSECOUNT - -config STM32_TIM1_PULSECOUNT - bool "TIM1 pulse count" - default n - depends on STM32_TIM1 - select STM32_PULSECOUNT - ---help--- - Reserve timer 1 for pulse count output. - -if STM32_TIM1_PULSECOUNT - -config STM32_TIM1_PULSECOUNT_TDTS - int "TIM1 pulse count clock division" - default 0 - range 0 2 - -config STM32_TIM1_PULSECOUNT_CHANNEL - int "TIM1 pulse count channel" - default 1 - range 1 4 - ---help--- - Specifies the timer channel {1,..,4}. - -config STM32_TIM1_PULSECOUNT_POL - int "TIM1 pulse count output polarity" - default 0 - range 0 1 - -config STM32_TIM1_PULSECOUNT_IDLE - int "TIM1 pulse count idle state" - default 0 - range 0 1 - -endif # STM32_TIM1_PULSECOUNT - -config STM32_TIM8_PULSECOUNT - bool "TIM8 pulse count" - default n - depends on STM32_TIM8 - select STM32_PULSECOUNT - ---help--- - Reserve timer 8 for pulse count output. - -if STM32_TIM8_PULSECOUNT - -config STM32_TIM8_PULSECOUNT_TDTS - int "TIM8 pulse count clock division" - default 0 - range 0 2 - -config STM32_TIM8_PULSECOUNT_CHANNEL - int "TIM8 pulse count channel" - default 1 - range 1 4 - ---help--- - Specifies the timer channel {1,..,4}. - -config STM32_TIM8_PULSECOUNT_POL - int "TIM8 pulse count output polarity" - default 0 - range 0 1 - -config STM32_TIM8_PULSECOUNT_IDLE - int "TIM8 pulse count idle state" - default 0 - range 0 1 - -endif # STM32_TIM8_PULSECOUNT -config STM32_TIM1_ADC - bool "TIM1 ADC" - default n - depends on STM32_TIM1 && STM32_ADC - ---help--- - Reserve timer 1 for use by ADC - - Timer devices may be used for different purposes. If STM32_TIM1 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - -choice - prompt "Select TIM1 ADC channel" - default STM32_TIM1_ADC1 - depends on STM32_TIM1_ADC - -config STM32_TIM1_ADC1 - bool "TIM1 ADC channel 1" - depends on STM32_ADC1 - select STM32_HAVE_ADC1_TIMER - ---help--- - Reserve TIM1 to trigger ADC1 - -config STM32_TIM1_ADC2 - bool "TIM1 ADC channel 2" - depends on STM32_ADC2 - select STM32_HAVE_ADC2_TIMER - ---help--- - Reserve TIM1 to trigger ADC2 - -config STM32_TIM1_ADC3 - bool "TIM1 ADC channel 3" - depends on STM32_ADC3 - select STM32_HAVE_ADC3_TIMER - ---help--- - Reserve TIM1 to trigger ADC3 - -endchoice - -config STM32_TIM2_ADC - bool "TIM2 ADC" - default n - depends on STM32_TIM2 && STM32_ADC - ---help--- - Reserve timer 1 for use by ADC - - Timer devices may be used for different purposes. If STM32_TIM2 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - -choice - prompt "Select TIM2 ADC channel" - default STM32_TIM2_ADC1 - depends on STM32_TIM2_ADC - -config STM32_TIM2_ADC1 - bool "TIM2 ADC channel 1" - depends on STM32_ADC1 - select STM32_HAVE_ADC1_TIMER - ---help--- - Reserve TIM2 to trigger ADC1 - -config STM32_TIM2_ADC2 - bool "TIM2 ADC channel 2" - depends on STM32_ADC2 - select STM32_HAVE_ADC2_TIMER - ---help--- - Reserve TIM2 to trigger ADC2 - -config STM32_TIM2_ADC3 - bool "TIM2 ADC channel 3" - depends on STM32_ADC3 - select STM32_HAVE_ADC3_TIMER - ---help--- - Reserve TIM2 to trigger ADC3 - -endchoice - -config STM32_TIM3_ADC - bool "TIM3 ADC" - default n - depends on STM32_TIM3 && STM32_ADC - ---help--- - Reserve timer 1 for use by ADC - - Timer devices may be used for different purposes. If STM32_TIM3 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - -choice - prompt "Select TIM3 ADC channel" - default STM32_TIM3_ADC1 - depends on STM32_TIM3_ADC - -config STM32_TIM3_ADC1 - bool "TIM3 ADC channel 1" - depends on STM32_ADC1 - select STM32_HAVE_ADC1_TIMER - ---help--- - Reserve TIM3 to trigger ADC1 - -config STM32_TIM3_ADC2 - bool "TIM3 ADC channel 2" - depends on STM32_ADC2 - select STM32_HAVE_ADC2_TIMER - ---help--- - Reserve TIM3 to trigger ADC2 - -config STM32_TIM3_ADC3 - bool "TIM3 ADC channel 3" - depends on STM32_ADC3 - select STM32_HAVE_ADC3_TIMER - ---help--- - Reserve TIM3 to trigger ADC3 - -endchoice - -config STM32_TIM4_ADC - bool "TIM4 ADC" - default n - depends on STM32_TIM4 && STM32_ADC - ---help--- - Reserve timer 1 for use by ADC - - Timer devices may be used for different purposes. If STM32_TIM4 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - -choice - prompt "Select TIM4 ADC channel" - default STM32_TIM4_ADC1 - depends on STM32_TIM4_ADC - -config STM32_TIM4_ADC1 - bool "TIM4 ADC channel 1" - depends on STM32_ADC1 - select STM32_HAVE_ADC1_TIMER - ---help--- - Reserve TIM4 to trigger ADC1 - -config STM32_TIM4_ADC2 - bool "TIM4 ADC channel 2" - depends on STM32_ADC2 - select STM32_HAVE_ADC2_TIMER - ---help--- - Reserve TIM4 to trigger ADC2 - -config STM32_TIM4_ADC3 - bool "TIM4 ADC channel 3" - depends on STM32_ADC3 - select STM32_HAVE_ADC3_TIMER - ---help--- - Reserve TIM4 to trigger ADC3 - -endchoice - -config STM32_TIM5_ADC - bool "TIM5 ADC" - default n - depends on STM32_TIM5 && STM32_ADC - ---help--- - Reserve timer 1 for use by ADC - - Timer devices may be used for different purposes. If STM32_TIM5 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - -choice - prompt "Select TIM5 ADC channel" - default STM32_TIM5_ADC1 - depends on STM32_TIM5_ADC - -config STM32_TIM5_ADC1 - bool "TIM5 ADC channel 1" - depends on STM32_ADC1 - select STM32_HAVE_ADC1_TIMER - ---help--- - Reserve TIM5 to trigger ADC1 - -config STM32_TIM5_ADC2 - bool "TIM5 ADC channel 2" - depends on STM32_ADC2 - select STM32_HAVE_ADC2_TIMER - ---help--- - Reserve TIM5 to trigger ADC2 - -config STM32_TIM5_ADC3 - bool "TIM5 ADC channel 3" - depends on STM32_ADC3 - select STM32_HAVE_ADC3_TIMER - ---help--- - Reserve TIM5 to trigger ADC3 - -endchoice - -config STM32_TIM8_ADC - bool "TIM8 ADC" - default n - depends on STM32_TIM8 && STM32_ADC - ---help--- - Reserve timer 1 for use by ADC - - Timer devices may be used for different purposes. If STM32_TIM8 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - -choice - prompt "Select TIM8 ADC channel" - default STM32_TIM8_ADC1 - depends on STM32_TIM8_ADC - -config STM32_TIM8_ADC1 - bool "TIM8 ADC channel 1" - depends on STM32_ADC1 - select STM32_HAVE_ADC1_TIMER - ---help--- - Reserve TIM8 to trigger ADC1 - -config STM32_TIM8_ADC2 - bool "TIM8 ADC channel 2" - depends on STM32_ADC2 - select STM32_HAVE_ADC2_TIMER - ---help--- - Reserve TIM8 to trigger ADC2 - -config STM32_TIM8_ADC3 - bool "TIM8 ADC channel 3" - depends on STM32_ADC3 - select STM32_HAVE_ADC3_TIMER - ---help--- - Reserve TIM8 to trigger ADC3 - -endchoice - -config STM32_HAVE_ADC1_TIMER - bool - -config STM32_HAVE_ADC2_TIMER - bool - -config STM32_HAVE_ADC3_TIMER - bool - -config STM32_HAVE_ADC4_TIMER - bool - -config STM32_HAVE_ADC5_TIMER - bool - -config STM32_ADC1_SAMPLE_FREQUENCY - int "ADC1 Sampling Frequency" - default 100 - depends on STM32_HAVE_ADC1_TIMER - ---help--- - ADC1 sampling frequency. Default: 100Hz - -config STM32_ADC1_TIMTRIG - int "ADC1 Timer Trigger" - default 0 - range 0 5 - depends on STM32_HAVE_ADC1_TIMER - ---help--- - Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO 5:TRGO2 - -config STM32_ADC2_SAMPLE_FREQUENCY - int "ADC2 Sampling Frequency" - default 100 - depends on STM32_HAVE_ADC2_TIMER - ---help--- - ADC2 sampling frequency. Default: 100Hz - -config STM32_ADC2_TIMTRIG - int "ADC2 Timer Trigger" - default 0 - range 0 5 - depends on STM32_HAVE_ADC2_TIMER - ---help--- - Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO 5:TRGO2 - -config STM32_ADC3_SAMPLE_FREQUENCY - int "ADC3 Sampling Frequency" - default 100 - depends on STM32_HAVE_ADC3_TIMER - ---help--- - ADC3 sampling frequency. Default: 100Hz - -config STM32_ADC3_TIMTRIG - int "ADC3 Timer Trigger" - default 0 - range 0 5 - depends on STM32_HAVE_ADC3_TIMER - ---help--- - Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO 5:TRGO2 - -config STM32_TIM1_DAC - bool "TIM1 DAC" - default n - depends on STM32_TIM1 && STM32_DAC - ---help--- - Reserve timer 1 for use by DAC - - Timer devices may be used for different purposes. If STM32_TIM1 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -choice - prompt "Select TIM1 DAC channel" - default STM32_TIM1_DAC1 - depends on STM32_TIM1_DAC - -config STM32_TIM1_DAC1 - bool "TIM1 DAC channel 1" - ---help--- - Reserve TIM1 to trigger DAC1 - -config STM32_TIM1_DAC2 - bool "TIM1 DAC channel 2" - ---help--- - Reserve TIM1 to trigger DAC2 - -endchoice - -config STM32_TIM2_DAC - bool "TIM2 DAC" - default n - depends on STM32_TIM2 && STM32_DAC - ---help--- - Reserve timer 2 for use by DAC - - Timer devices may be used for different purposes. If STM32_TIM2 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -choice - prompt "Select TIM2 DAC channel" - default STM32_TIM2_DAC1 - depends on STM32_TIM2_DAC - -config STM32_TIM2_DAC1 - bool "TIM2 DAC channel 1" - ---help--- - Reserve TIM2 to trigger DAC1 - -config STM32_TIM2_DAC2 - bool "TIM2 DAC channel 2" - ---help--- - Reserve TIM2 to trigger DAC2 - -endchoice - -config STM32_TIM3_DAC - bool "TIM3 DAC" - default n - depends on STM32_TIM3 && STM32_DAC - ---help--- - Reserve timer 3 for use by DAC - - Timer devices may be used for different purposes. If STM32_TIM3 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -choice - prompt "Select TIM3 DAC channel" - default STM32_TIM3_DAC1 - depends on STM32_TIM3_DAC - -config STM32_TIM3_DAC1 - bool "TIM3 DAC channel 1" - ---help--- - Reserve TIM3 to trigger DAC1 - -config STM32_TIM3_DAC2 - bool "TIM3 DAC channel 2" - ---help--- - Reserve TIM3 to trigger DAC2 - -endchoice - -config STM32_TIM4_DAC - bool "TIM4 DAC" - default n - depends on STM32_TIM4 && STM32_DAC - ---help--- - Reserve timer 4 for use by DAC - - Timer devices may be used for different purposes. If STM32_TIM4 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -choice - prompt "Select TIM4 DAC channel" - default STM32_TIM4_DAC1 - depends on STM32_TIM4_DAC - -config STM32_TIM4_DAC1 - bool "TIM4 DAC channel 1" - ---help--- - Reserve TIM4 to trigger DAC1 - -config STM32_TIM4_DAC2 - bool "TIM4 DAC channel 2" - ---help--- - Reserve TIM4 to trigger DAC2 - -endchoice - -config STM32_TIM5_DAC - bool "TIM5 DAC" - default n - depends on STM32_TIM5 && STM32_DAC - ---help--- - Reserve timer 5 for use by DAC - - Timer devices may be used for different purposes. If STM32_TIM5 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -choice - prompt "Select TIM5 DAC channel" - default STM32_TIM5_DAC1 - depends on STM32_TIM5_DAC - -config STM32_TIM5_DAC1 - bool "TIM5 DAC channel 1" - ---help--- - Reserve TIM5 to trigger DAC1 - -config STM32_TIM5_DAC2 - bool "TIM5 DAC channel 2" - ---help--- - Reserve TIM5 to trigger DAC2 - -endchoice - -config STM32_TIM6_DAC - bool "TIM6 DAC" - default n - depends on STM32_TIM6 && STM32_DAC - ---help--- - Reserve timer 6 for use by DAC - - Timer devices may be used for different purposes. If STM32_TIM6 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -choice - prompt "Select TIM6 DAC channel" - default STM32_TIM6_DAC1 - depends on STM32_TIM6_DAC - -config STM32_TIM6_DAC1 - bool "TIM6 DAC channel 1" - ---help--- - Reserve TIM6 to trigger DAC1 - -config STM32_TIM6_DAC2 - bool "TIM6 DAC channel 2" - ---help--- - Reserve TIM6 to trigger DAC2 - -endchoice - -config STM32_TIM7_DAC - bool "TIM7 DAC" - default n - depends on STM32_TIM7 && STM32_DAC - ---help--- - Reserve timer 7 for use by DAC - - Timer devices may be used for different purposes. If STM32_TIM7 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -choice - prompt "Select TIM7 DAC channel" - default STM32_TIM7_DAC1 - depends on STM32_TIM7_DAC - -config STM32_TIM7_DAC1 - bool "TIM7 DAC channel 1" - ---help--- - Reserve TIM7 to trigger DAC1 - -config STM32_TIM7_DAC2 - bool "TIM7 DAC channel 2" - ---help--- - Reserve TIM7 to trigger DAC2 - -endchoice - -config STM32_TIM8_DAC - bool "TIM8 DAC" - default n - depends on STM32_TIM8 && STM32_DAC - ---help--- - Reserve timer 8 for use by DAC - - Timer devices may be used for different purposes. If STM32_TIM8 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -choice - prompt "Select TIM8 DAC channel" - default STM32_TIM8_DAC1 - depends on STM32_TIM8_DAC - -config STM32_TIM8_DAC1 - bool "TIM8 DAC channel 1" - ---help--- - Reserve TIM8 to trigger DAC1 - -config STM32_TIM8_DAC2 - bool "TIM8 DAC channel 2" - ---help--- - Reserve TIM8 to trigger DAC2 - -endchoice - -config STM32_TIM9_DAC - bool "TIM9 DAC" - default n - depends on STM32_TIM9 && STM32_DAC - ---help--- - Reserve timer 9 for use by DAC - - Timer devices may be used for different purposes. If STM32_TIM9 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -choice - prompt "Select TIM9 DAC channel" - default STM32_TIM9_DAC1 - depends on STM32_TIM9_DAC - -config STM32_TIM9_DAC1 - bool "TIM9 DAC channel 1" - ---help--- - Reserve TIM9 to trigger DAC1 - -config STM32_TIM9_DAC2 - bool "TIM9 DAC channel 2" - ---help--- - Reserve TIM9 to trigger DAC2 - -endchoice - -config STM32_TIM10_DAC - bool "TIM10 DAC" - default n - depends on STM32_TIM10 && STM32_DAC - ---help--- - Reserve timer 10 for use by DAC - - Timer devices may be used for different purposes. If STM32_TIM10 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -choice - prompt "Select TIM10 DAC channel" - default STM32_TIM10_DAC1 - depends on STM32_TIM10_DAC - -config STM32_TIM10_DAC1 - bool "TIM10 DAC channel 1" - ---help--- - Reserve TIM10 to trigger DAC1 - -config STM32_TIM10_DAC2 - bool "TIM10 DAC channel 2" - ---help--- - Reserve TIM10 to trigger DAC2 - -endchoice - -config STM32_TIM11_DAC - bool "TIM11 DAC" - default n - depends on STM32_TIM11 && STM32_DAC - ---help--- - Reserve timer 11 for use by DAC - - Timer devices may be used for different purposes. If STM32_TIM11 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -choice - prompt "Select TIM11 DAC channel" - default STM32_TIM11_DAC1 - depends on STM32_TIM11_DAC - -config STM32_TIM11_DAC1 - bool "TIM11 DAC channel 1" - ---help--- - Reserve TIM11 to trigger DAC1 - -config STM32_TIM11_DAC2 - bool "TIM11 DAC channel 2" - ---help--- - Reserve TIM11 to trigger DAC2 - -endchoice - -config STM32_TIM12_DAC - bool "TIM12 DAC" - default n - depends on STM32_TIM12 && STM32_DAC - ---help--- - Reserve timer 12 for use by DAC - - Timer devices may be used for different purposes. If STM32_TIM12 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -choice - prompt "Select TIM12 DAC channel" - default STM32_TIM12_DAC1 - depends on STM32_TIM12_DAC - -config STM32_TIM12_DAC1 - bool "TIM12 DAC channel 1" - ---help--- - Reserve TIM12 to trigger DAC1 - -config STM32_TIM12_DAC2 - bool "TIM12 DAC channel 2" - ---help--- - Reserve TIM12 to trigger DAC2 - -endchoice - -config STM32_TIM13_DAC - bool "TIM13 DAC" - default n - depends on STM32_TIM13 && STM32_DAC - ---help--- - Reserve timer 13 for use by DAC - - Timer devices may be used for different purposes. If STM32_TIM13 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -choice - prompt "Select TIM13 DAC channel" - default STM32_TIM13_DAC1 - depends on STM32_TIM13_DAC - -config STM32_TIM13_DAC1 - bool "TIM13 DAC channel 1" - ---help--- - Reserve TIM13 to trigger DAC1 - -config STM32_TIM13_DAC2 - bool "TIM13 DAC channel 2" - ---help--- - Reserve TIM13 to trigger DAC2 - -endchoice - -config STM32_TIM14_DAC - bool "TIM14 DAC" - default n - depends on STM32_TIM14 && STM32_DAC - ---help--- - Reserve timer 14 for use by DAC - - Timer devices may be used for different purposes. If STM32_TIM14 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -choice - prompt "Select TIM14 DAC channel" - default STM32_TIM14_DAC1 - depends on STM32_TIM14_DAC - -config STM32_TIM14_DAC1 - bool "TIM14 DAC channel 1" - ---help--- - Reserve TIM14 to trigger DAC1 - -config STM32_TIM14_DAC2 - bool "TIM14 DAC channel 2" - ---help--- - Reserve TIM14 to trigger DAC2 - -endchoice - -config STM32_TIM1_CAP - bool "TIM1 Capture" - default n - depends on STM32_TIM1 - select STM32_CAP - ---help--- - Reserve timer 1 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -if STM32_TIM1_CAP - -config STM32_TIM1_CHANNEL - int "TIM1 Capture Input Channel" - default 1 - range 1 4 - ---help--- - If TIM1 is enabled for capture usage, you also need specifies the timer input - channel {1,..,4} - -config STM32_TIM1_CLOCK - int "TIM1 work frequency for capture" - default 1000000 - ---help--- - This clock frequency limiting the count rate at the expense of resolution. - -endif # STM32_TIM1_CAP - -config STM32_TIM2_CAP - bool "TIM2 Capture" - default n - depends on STM32_TIM2 - select STM32_CAP - ---help--- - Reserve timer 2 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -if STM32_TIM2_CAP - -config STM32_TIM2_CHANNEL - int "TIM2 Capture Input Channel" - default 1 - range 1 4 - ---help--- - If TIM2 is enabled for capture usage, you also need specifies the timer input - channel {1,..,4} - -config STM32_TIM2_CLOCK - int "TIM2 work frequency for capture" - default 1000000 - ---help--- - This clock frequency limiting the count rate at the expense of resolution. - -endif # STM32_TIM2_CAP - -config STM32_TIM3_CAP - bool "TIM3 Capture" - default n - depends on STM32_TIM3 - select STM32_CAP - ---help--- - Reserve timer 3 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -if STM32_TIM3_CAP - -config STM32_TIM3_CHANNEL - int "TIM3 Capture Input Channel" - default 1 - range 1 4 - ---help--- - If TIM3 is enabled for capture usage, you also need specifies the timer input - channel {1,..,4} - -config STM32_TIM3_CLOCK - int "TIM3 work frequency for capture" - default 1000000 - ---help--- - This clock frequency limiting the count rate at the expense of resolution. - -endif # STM32_TIM3_CAP - -config STM32_TIM4_CAP - bool "TIM4 Capture" - default n - depends on STM32_TIM4 - select STM32_CAP - ---help--- - Reserve timer 4 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -if STM32_TIM4_CAP - -config STM32_TIM4_CHANNEL - int "TIM4 Capture Input Channel" - default 1 - range 1 4 - ---help--- - If TIM4 is enabled for capture usage, you also need specifies the timer input - channel {1,..,4} - -config STM32_TIM4_CLOCK - int "TIM4 work frequency for capture" - default 1000000 - ---help--- - This clock frequency limiting the count rate at the expense of resolution. - -endif # STM32_TIM4_CAP - -config STM32_TIM5_CAP - bool "TIM5 Capture" - default n - depends on STM32_TIM5 - select STM32_CAP - ---help--- - Reserve timer 5 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -if STM32_TIM5_CAP - -config STM32_TIM5_CHANNEL - int "TIM5 Capture Input Channel" - default 1 - range 1 4 - ---help--- - If TIM5 is enabled for capture usage, you also need specifies the timer input - channel {1,..,4} - -config STM32_TIM5_CLOCK - int "TIM5 work frequency for capture" - default 1000000 - ---help--- - This clock frequency limiting the count rate at the expense of resolution. - -endif # STM32_TIM5_CAP - -config STM32_TIM8_CAP - bool "TIM8 Capture" - default n - depends on STM32_TIM8 - select STM32_CAP - ---help--- - Reserve timer 8 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -if STM32_TIM8_CAP - -config STM32_TIM8_CHANNEL - int "TIM8 Capture Input Channel" - default 1 - range 1 4 - ---help--- - If TIM8 is enabled for capture usage, you also need specifies the timer input - channel {1,..,4} - -config STM32_TIM8_CLOCK - int "TIM8 work frequency for capture" - default 1000000 - ---help--- - This clock frequency limiting the count rate at the expense of resolution. - -endif # STM32_TIM8_CAP - -config STM32_TIM9_CAP - bool "TIM9 Capture" - default n - depends on STM32_TIM9 - select STM32_CAP - ---help--- - Reserve timer 9 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -if STM32_TIM9_CAP - -config STM32_TIM9_CHANNEL - int "TIM9 Capture Input Channel" - default 1 - range 1 4 - ---help--- - If TIM9 is enabled for capture usage, you also need specifies the timer input - channel {1,..,4} - -config STM32_TIM9_CLOCK - int "TIM9 work frequency for capture" - default 1000000 - ---help--- - This clock frequency limiting the count rate at the expense of resolution. - -endif # STM32_TIM9_CAP - -config STM32_TIM10_CAP - bool "TIM10 Capture" - default n - depends on STM32_TIM10 - select STM32_CAP - ---help--- - Reserve timer 10 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -if STM32_TIM10_CAP - -config STM32_TIM10_CHANNEL - int "TIM10 Capture Input Channel" - default 1 - range 1 4 - ---help--- - If TIM10 is enabled for capture usage, you also need specifies the timer input - channel {1,..,4} - -config STM32_TIM10_CLOCK - int "TIM10 work frequency for capture" - default 1000000 - ---help--- - This clock frequency limiting the count rate at the expense of resolution. - -endif # STM32_TIM10_CAP - -config STM32_TIM11_CAP - bool "TIM11 Capture" - default n - depends on STM32_TIM11 - select STM32_CAP - ---help--- - Reserve timer 11 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -if STM32_TIM11_CAP - -config STM32_TIM11_CHANNEL - int "TIM11 Capture Input Channel" - default 1 - range 1 4 - ---help--- - If TIM11 is enabled for capture usage, you also need specifies the timer input - channel {1,..,4} - -config STM32_TIM11_CLOCK - int "TIM11 work frequency for capture" - default 1000000 - ---help--- - This clock frequency limiting the count rate at the expense of resolution. - -endif # STM32_TIM11_CAP - -config STM32_TIM12_CAP - bool "TIM12 Capture" - default n - depends on STM32_TIM12 - select STM32_CAP - ---help--- - Reserve timer 12 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -if STM32_TIM12_CAP - -config STM32_TIM12_CHANNEL - int "TIM12 Capture Input Channel" - default 1 - range 1 4 - ---help--- - If TIM12 is enabled for capture usage, you also need specifies the timer input - channel {1,..,4} - -config STM32_TIM12_CLOCK - int "TIM12 work frequency for capture" - default 1000000 - ---help--- - This clock frequency limiting the count rate at the expense of resolution. - -endif # STM32_TIM12_CAP - -config STM32_TIM13_CAP - bool "TIM13 Capture" - default n - depends on STM32_TIM13 - select STM32_CAP - ---help--- - Reserve timer 13 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -if STM32_TIM13_CAP - -config STM32_TIM13_CHANNEL - int "TIM13 Capture Input Channel" - default 1 - range 1 4 - ---help--- - If TIM13 is enabled for capture usage, you also need specifies the timer input - channel {1,..,4} - -config STM32_TIM13_CLOCK - int "TIM13 work frequency for capture" - default 1000000 - ---help--- - This clock frequency limiting the count rate at the expense of resolution. - -endif # STM32_TIM13_CAP - -config STM32_TIM14_CAP - bool "TIM14 Capture" - default n - depends on STM32_TIM14 - select STM32_CAP - ---help--- - Reserve timer 14 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -if STM32_TIM14_CAP - -config STM32_TIM14_CHANNEL - int "TIM14 Capture Input Channel" - default 1 - range 1 4 - ---help--- - If TIM14 is enabled for capture usage, you also need specifies the timer input - channel {1,..,4} - -config STM32_TIM14_CLOCK - int "TIM14 work frequency for capture" - default 1000000 - ---help--- - This clock frequency limiting the count rate at the expense of resolution. - -endif # STM32_TIM14_CAP - -menu "STM32 TIMx Outputs Configuration" - -config STM32_TIM1_CH1POL - int "TIM1 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32_TIM1_CH1OUT - ---help--- - TIM1 Channel 1 output polarity - -config STM32_TIM1_CH1IDLE - int "TIM1 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM1_CH1OUT - ---help--- - TIM1 Channel 1 output IDLE - -config STM32_TIM1_CH1NPOL - int "TIM1 Channel 1 Complementary Output polarity" - default 0 - range 0 1 - depends on STM32_TIM1_CH1NOUT - ---help--- - TIM1 Channel 1 Complementary Output polarity - -config STM32_TIM1_CH1NIDLE - int "TIM1 Channel 1 Complementary Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM1_CH1NOUT - ---help--- - TIM1 Channel 1 Complementary Output IDLE - -config STM32_TIM1_CH2POL - int "TIM1 Channel 2 Output polarity" - default 0 - range 0 1 - depends on STM32_TIM1_CH2OUT - ---help--- - TIM1 Channel 2 output polarity - -config STM32_TIM1_CH2IDLE - int "TIM1 Channel 2 Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM1_CH2OUT - ---help--- - TIM1 Channel 2 output IDLE - -config STM32_TIM1_CH2NPOL - int "TIM1 Channel 2 Complementary Output polarity" - default 0 - range 0 1 - depends on STM32_TIM1_CH2NOUT - ---help--- - TIM1 Channel 2 Complementary Output polarity - -config STM32_TIM1_CH2NIDLE - int "TIM1 Channel 2 Complementary Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM1_CH2NOUT - ---help--- - TIM1 Channel 2 Complementary Output IDLE - -config STM32_TIM1_CH3POL - int "TIM1 Channel 3 Output polarity" - default 0 - range 0 1 - depends on STM32_TIM1_CH3OUT - ---help--- - TIM1 Channel 3 output polarity - -config STM32_TIM1_CH3IDLE - int "TIM1 Channel 3 Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM1_CH3OUT - ---help--- - TIM1 Channel 3 output IDLE - -config STM32_TIM1_CH3NPOL - int "TIM1 Channel 3 Complementary Output polarity" - default 0 - range 0 1 - depends on STM32_TIM1_CH3NOUT - ---help--- - TIM1 Channel 3 Complementary Output polarity - -config STM32_TIM1_CH3NIDLE - int "TIM1 Channel 3 Complementary Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM1_CH3NOUT - ---help--- - TIM1 Channel 3 Complementary Output IDLE - -config STM32_TIM1_CH4POL - int "TIM1 Channel 4 Output polarity" - default 0 - range 0 1 - depends on STM32_TIM1_CH4OUT - ---help--- - TIM1 Channel 4 output polarity - -config STM32_TIM1_CH4IDLE - int "TIM1 Channel 4 Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM1_CH4OUT - ---help--- - TIM1 Channel 4 output IDLE - -config STM32_TIM1_CH5POL - int "TIM1 Channel 5 Output polarity" - default 0 - range 0 1 - depends on STM32_TIM1_CH5OUT - ---help--- - TIM1 Channel 5 output polarity - -config STM32_TIM1_CH5IDLE - int "TIM1 Channel 5 Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM1_CH5OUT - ---help--- - TIM1 Channel 5 output IDLE - -config STM32_TIM1_CH6POL - int "TIM1 Channel 6 Output polarity" - default 0 - range 0 1 - depends on STM32_TIM1_CH6OUT - ---help--- - TIM1 Channel 6 output polarity - -config STM32_TIM1_CH6IDLE - int "TIM1 Channel 6 Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM1_CH6OUT - ---help--- - TIM1 Channel 6 output IDLE - -config STM32_TIM2_CH1POL - int "TIM2 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32_TIM2_CH1OUT - ---help--- - TIM2 Channel 1 output polarity - -config STM32_TIM2_CH1IDLE - int "TIM2 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM2_CH1OUT - ---help--- - TIM2 Channel 1 output IDLE - -config STM32_TIM2_CH2POL - int "TIM2 Channel 2 Output polarity" - default 0 - range 0 1 - depends on STM32_TIM2_CH2OUT - ---help--- - TIM2 Channel 2 output polarity - -config STM32_TIM2_CH2IDLE - int "TIM2 Channel 2 Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM2_CH2OUT - ---help--- - TIM2 Channel 2 output IDLE - -config STM32_TIM2_CH3POL - int "TIM2 Channel 3 Output polarity" - default 0 - range 0 1 - depends on STM32_TIM2_CH3OUT - ---help--- - TIM2 Channel 3 output polarity - -config STM32_TIM2_CH3IDLE - int "TIM2 Channel 3 Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM2_CH3OUT - ---help--- - TIM2 Channel 3 output IDLE - -config STM32_TIM2_CH4POL - int "TIM2 Channel 4 Output polarity" - default 0 - range 0 1 - depends on STM32_TIM2_CH4OUT - ---help--- - TIM2 Channel 4 output polarity - -config STM32_TIM2_CH4IDLE - int "TIM2 Channel 4 Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM2_CH4OUT - ---help--- - TIM2 Channel 4 output IDLE - -config STM32_TIM3_CH1POL - int "TIM3 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32_TIM3_CH1OUT - ---help--- - TIM3 Channel 1 output polarity - -config STM32_TIM3_CH1IDLE - int "TIM3 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM3_CH1OUT - ---help--- - TIM3 Channel 1 output IDLE - -config STM32_TIM3_CH2POL - int "TIM3 Channel 2 Output polarity" - default 0 - range 0 1 - depends on STM32_TIM3_CH2OUT - ---help--- - TIM3 Channel 2 output polarity - -config STM32_TIM3_CH2IDLE - int "TIM3 Channel 2 Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM3_CH2OUT - ---help--- - TIM3 Channel 2 output IDLE - -config STM32_TIM3_CH3POL - int "TIM3 Channel 3 Output polarity" - default 0 - range 0 1 - depends on STM32_TIM3_CH3OUT - ---help--- - TIM3 Channel 3 output polarity - -config STM32_TIM3_CH3IDLE - int "TIM3 Channel 3 Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM3_CH3OUT - ---help--- - TIM3 Channel 3 output IDLE - -config STM32_TIM3_CH4POL - int "TIM3 Channel 4 Output polarity" - default 0 - range 0 1 - depends on STM32_TIM3_CH4OUT - ---help--- - TIM3 Channel 4 output polarity - -config STM32_TIM3_CH4IDLE - int "TIM3 Channel 4 Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM3_CH4OUT - ---help--- - TIM3 Channel 4 output IDLE - -config STM32_TIM4_CH1POL - int "TIM4 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32_TIM4_CH1OUT - ---help--- - TIM4 Channel 1 output polarity - -config STM32_TIM4_CH1IDLE - int "TIM4 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM4_CH1OUT - ---help--- - TIM4 Channel 1 output IDLE - -config STM32_TIM4_CH2POL - int "TIM4 Channel 2 Output polarity" - default 0 - range 0 1 - depends on STM32_TIM4_CH2OUT - ---help--- - TIM4 Channel 2 output polarity - -config STM32_TIM4_CH2IDLE - int "TIM4 Channel 2 Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM4_CH2OUT - ---help--- - TIM4 Channel 2 output IDLE - -config STM32_TIM4_CH3POL - int "TIM4 Channel 3 Output polarity" - default 0 - range 0 1 - depends on STM32_TIM4_CH3OUT - ---help--- - TIM4 Channel 3 output polarity - -config STM32_TIM4_CH3IDLE - int "TIM4 Channel 3 Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM4_CH3OUT - ---help--- - TIM4 Channel 3 output IDLE - -config STM32_TIM4_CH4POL - int "TIM4 Channel 4 Output polarity" - default 0 - range 0 1 - depends on STM32_TIM4_CH4OUT - ---help--- - TIM4 Channel 4 output polarity - -config STM32_TIM4_CH4IDLE - int "TIM4 Channel 4 Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM4_CH4OUT - ---help--- - TIM4 Channel 4 output IDLE - -config STM32_TIM5_CH1POL - int "TIM5 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32_TIM5_CH1OUT - ---help--- - TIM5 Channel 1 output polarity - -config STM32_TIM5_CH1IDLE - int "TIM5 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM5_CH1OUT - ---help--- - TIM5 Channel 1 output IDLE - -config STM32_TIM5_CH2POL - int "TIM5 Channel 2 Output polarity" - default 0 - range 0 1 - depends on STM32_TIM5_CH2OUT - ---help--- - TIM5 Channel 2 output polarity - -config STM32_TIM5_CH2IDLE - int "TIM5 Channel 2 Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM5_CH2OUT - ---help--- - TIM5 Channel 2 output IDLE - -config STM32_TIM5_CH3POL - int "TIM5 Channel 3 Output polarity" - default 0 - range 0 1 - depends on STM32_TIM5_CH3OUT - ---help--- - TIM5 Channel 3 output polarity - -config STM32_TIM5_CH3IDLE - int "TIM5 Channel 3 Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM5_CH3OUT - ---help--- - TIM5 Channel 3 output IDLE - -config STM32_TIM5_CH4POL - int "TIM5 Channel 4 Output polarity" - default 0 - range 0 1 - depends on STM32_TIM5_CH4OUT - ---help--- - TIM5 Channel 4 output polarity - -config STM32_TIM5_CH4IDLE - int "TIM5 Channel 4 Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM5_CH4OUT - ---help--- - TIM5 Channel 4 output IDLE - -config STM32_TIM8_CH1POL - int "TIM8 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32_TIM8_CH1OUT - ---help--- - TIM8 Channel 1 output polarity - -config STM32_TIM8_CH1IDLE - int "TIM8 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM8_CH1OUT - ---help--- - TIM8 Channel 1 output IDLE - -config STM32_TIM8_CH1NPOL - int "TIM8 Channel 1 Complementary Output polarity" - default 0 - range 0 1 - depends on STM32_TIM8_CH1NOUT - ---help--- - TIM8 Channel 1 Complementary Output polarity - -config STM32_TIM8_CH1NIDLE - int "TIM8 Channel 1 Complementary Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM8_CH1NOUT - ---help--- - TIM8 Channel 1 Complementary Output IDLE - -config STM32_TIM8_CH2POL - int "TIM8 Channel 2 Output polarity" - default 0 - range 0 1 - depends on STM32_TIM8_CH2OUT - ---help--- - TIM8 Channel 2 output polarity - -config STM32_TIM8_CH2IDLE - int "TIM8 Channel 2 Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM8_CH2OUT - ---help--- - TIM8 Channel 2 output IDLE - -config STM32_TIM8_CH2NPOL - int "TIM8 Channel 2 Complementary Output polarity" - default 0 - range 0 1 - depends on STM32_TIM8_CH2NOUT - ---help--- - TIM8 Channel 2 Complementary Output polarity - -config STM32_TIM8_CH2NIDLE - int "TIM8 Channel 2 Complementary Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM8_CH2NOUT - ---help--- - TIM8 Channel 2 Complementary Output IDLE - -config STM32_TIM8_CH3POL - int "TIM8 Channel 3 Output polarity" - default 0 - range 0 1 - depends on STM32_TIM8_CH3OUT - ---help--- - TIM8 Channel 3 output polarity - -config STM32_TIM8_CH3IDLE - int "TIM8 Channel 3 Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM8_CH3OUT - ---help--- - TIM8 Channel 3 output IDLE - -config STM32_TIM8_CH3NPOL - int "TIM8 Channel 3 Complementary Output polarity" - default 0 - range 0 1 - depends on STM32_TIM8_CH3NOUT - ---help--- - TIM8 Channel 3 Complementary Output polarity - -config STM32_TIM8_CH3NIDLE - int "TIM8 Channel 3 Complementary Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM8_CH3NOUT - ---help--- - TIM8 Channel 3 Complementary Output IDLE - -config STM32_TIM8_CH4POL - int "TIM8 Channel 4 Output polarity" - default 0 - range 0 1 - depends on STM32_TIM8_CH4OUT - ---help--- - TIM8 Channel 4 output polarity - -config STM32_TIM8_CH4IDLE - int "TIM8 Channel 4 Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM8_CH4OUT - ---help--- - TIM8 Channel 4 output IDLE - -config STM32_TIM8_CH5POL - int "TIM8 Channel 5 Output polarity" - default 0 - range 0 1 - depends on STM32_TIM8_CH5OUT - ---help--- - TIM8 Channel 5 output polarity - -config STM32_TIM8_CH5IDLE - int "TIM8 Channel 5 Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM8_CH5OUT - ---help--- - TIM8 Channel 5 output IDLE - -config STM32_TIM8_CH6POL - int "TIM8 Channel 6 Output polarity" - default 0 - range 0 1 - depends on STM32_TIM8_CH6OUT - ---help--- - TIM8 Channel 6 output polarity - -config STM32_TIM8_CH6IDLE - int "TIM8 Channel 6 Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM8_CH6OUT - ---help--- - TIM8 Channel 6 output IDLE - -config STM32_TIM9_CH1POL - int "TIM9 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32_TIM9_CH1OUT - ---help--- - TIM9 Channel 1 output polarity - -config STM32_TIM9_CH1IDLE - int "TIM9 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM9_CH1OUT - ---help--- - TIM9 Channel 1 output IDLE - -config STM32_TIM9_CH2POL - int "TIM9 Channel 2 Output polarity" - default 0 - range 0 1 - depends on STM32_TIM9_CH2OUT - ---help--- - TIM9 Channel 2 output polarity - -config STM32_TIM9_CH2IDLE - int "TIM9 Channel 2 Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM9_CH2OUT - ---help--- - TIM9 Channel 2 output IDLE - -config STM32_TIM10_CH1POL - int "TIM10 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32_TIM10_CH1OUT - ---help--- - TIM10 Channel 1 output polarity - -config STM32_TIM10_CH1IDLE - int "TIM10 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM10_CH1OUT - ---help--- - TIM10 Channel 1 output IDLE - -config STM32_TIM11_CH1POL - int "TIM11 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32_TIM11_CH1OUT - ---help--- - TIM11 Channel 1 output polarity - -config STM32_TIM11_CH1IDLE - int "TIM11 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM11_CH1OUT - ---help--- - TIM11 Channel 1 output IDLE - -config STM32_TIM12_CH1POL - int "TIM12 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32_TIM12_CH1OUT - ---help--- - TIM12 Channel 1 output polarity - -config STM32_TIM12_CH1IDLE - int "TIM12 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM12_CH1OUT - ---help--- - TIM12 Channel 1 output IDLE - -config STM32_TIM12_CH2POL - int "TIM12 Channel 2 Output polarity" - default 0 - range 0 1 - depends on STM32_TIM12_CH2OUT - ---help--- - TIM12 Channel 2 output polarity - -config STM32_TIM12_CH2IDLE - int "TIM12 Channel 2 Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM12_CH2OUT - ---help--- - TIM12 Channel 2 output IDLE - -config STM32_TIM13_CH1POL - int "TIM13 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32_TIM13_CH1OUT - ---help--- - TIM13 Channel 1 output polarity - -config STM32_TIM13_CH1IDLE - int "TIM13 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM13_CH1OUT - ---help--- - TIM13 Channel 1 output IDLE - -config STM32_TIM14_CH1POL - int "TIM14 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32_TIM14_CH1OUT - ---help--- - TIM14 Channel 1 output polarity - -config STM32_TIM14_CH1IDLE - int "TIM14 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM14_CH1OUT - ---help--- - TIM14 Channel 1 output IDLE - -config STM32_TIM15_CH1POL - int "TIM15 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32_TIM15_CH1OUT - ---help--- - TIM15 Channel 1 output polarity - -config STM32_TIM15_CH1IDLE - int "TIM15 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM15_CH1OUT - ---help--- - TIM15 Channel 1 output IDLE - -config STM32_TIM15_CH1NPOL - int "TIM15 Channel 1 Complementary Output polarity" - default 0 - range 0 1 - depends on STM32_TIM15_CH1NOUT - ---help--- - TIM15 Channel 1 Complementary Output polarity - -config STM32_TIM15_CH1NIDLE - int "TIM15 Channel 1 Complementary Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM15_CH1NOUT - ---help--- - TIM15 Channel 1 Complementary Output IDLE - -config STM32_TIM15_CH2POL - int "TIM15 Channel 2 Output polarity" - default 0 - range 0 1 - depends on STM32_TIM15_CH2OUT - ---help--- - TIM15 Channel 2 output polarity - -config STM32_TIM15_CH2IDLE - int "TIM15 Channel 2 Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM15_CH2OUT - ---help--- - TIM15 Channel 2 output IDLE - -config STM32_TIM15_CH2NPOL - int "TIM15 Channel 2 Complementary Output polarity" - default 0 - range 0 1 - depends on STM32_TIM15_CH2NOUT - ---help--- - TIM15 Channel 2 Complementary Output polarity - -config STM32_TIM15_CH2NIDLE - int "TIM15 Channel 2 Complementary Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM15_CH2NOUT - ---help--- - TIM15 Channel 2 Complementary Output IDLE - -config STM32_TIM16_CH1POL - int "TIM16 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32_TIM16_CH1OUT - ---help--- - TIM16 Channel 1 output polarity - -config STM32_TIM16_CH1IDLE - int "TIM16 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM16_CH1OUT - ---help--- - TIM16 Channel 1 output IDLE - -config STM32_TIM17_CH1POL - int "TIM17 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32_TIM17_CH1OUT - ---help--- - TIM17 Channel 1 output polarity - -config STM32_TIM17_CH1IDLE - int "TIM17 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM17_CH1OUT - ---help--- - TIM17 Channel 1 output IDLE - -endmenu #STM32 TIMx Outputs Configuration - -endmenu # Timer Configuration - -menu "HRTIM Configuration" - depends on STM32_HRTIM - -config STM32_HRTIM_DISABLE_CHARDRV - bool "HRTIM Disable Character Driver" - default n - ---help--- - In most cases we do not need HRTIM Character Driver, so we can disable it - and save some memory. - -config STM32_HRTIM_NO_ENABLE_TIMERS - bool "Do not enable HRTIM timers at startup" - default n - ---help--- - Do not enable HRTIM timers at startup - -menuconfig STM32_HRTIM_ADC - bool "HRTIM ADC Triggering" - default n - ---help--- - Enable HRTIM ADC Triggering support. - -if STM32_HRTIM_ADC - -config STM32_HRTIM_ADC1_TRG1 - bool "HRTIM ADC1 Trigger 1" - default n - -config STM32_HRTIM_ADC1_TRG2 - bool "HRTIM ADC1 Trigger 2" - default n - -config STM32_HRTIM_ADC1_TRG3 - bool "HRTIM ADC1 Trigger 3" - default n - -config STM32_HRTIM_ADC1_TRG4 - bool "HRTIM ADC1 Trigger 4" - default n - -config STM32_HRTIM_ADC2_TRG1 - bool "HRTIM ADC2 Trigger 1" - default n - -config STM32_HRTIM_ADC2_TRG2 - bool "HRTIM ADC2 Trigger 2" - default n - -config STM32_HRTIM_ADC2_TRG3 - bool "HRTIM ADC2 Trigger 3" - default n - -config STM32_HRTIM_ADC2_TRG4 - bool "HRTIM ADC2 Trigger 4" - default n - -endif # STM32_HRTIM_ADC - -config STM32_HRTIM_DAC - bool "HRTIM DAC Triggering" - default n - ---help--- - Enable HRTIM DAC Triggering support. - -config STM32_HRTIM_PWM - bool "HRTIM PWM Outputs" - default n - ---help--- - Enable HRTIM PWM Outputs support. - -config STM32_HRTIM_CAP - bool "HRTIM Capture" - default n - ---help--- - Enable HRTIM Capture support. - -config STM32_HRTIM_INTERRUPTS - bool "HRTIM Interrupts" - default n - ---help--- - Enable HRTIM Interrupts support. - -config STM32_HRTIM_BURST - bool "HRTIM Burst Mode" - depends on STM32_HRTIM_PWM - default n - ---help--- - Enable HRTIM Burst Mode support for PWM outputs. - -config STM32_HRTIM_DEADTIME - bool "HRTIM Dead-time" - depends on STM32_HRTIM_PWM - default n - ---help--- - Enable HRTIM Deadtime support for PWM outputs. - -config STM32_HRTIM_PUSHPULL - bool "HRTIM Push-Pull Mode" - depends on STM32_HRTIM_PWM - default n - ---help--- - Enable HRTIM Push-Pull Mode support for PWM outputs. - -config STM32_HRTIM_CHOPPER - bool "HRTIM Chopper" - depends on STM32_HRTIM_PWM - default n - ---help--- - Enable HRTIM Chopper Mode for PWM outputs. - -config STM32_HRTIM_DMA - bool "HRTIM DMA" - default n - -config STM32_HRTIM_DMABURST - bool "HRTIM DMA Burst" - default n - -config STM32_HRTIM_AUTODELAY - bool "HRTIM Autodelay" - depends on STM32_HRTIM_PWM - default n - -menuconfig STM32_HRTIM_EVENTS - bool "HRTIM Events Configuration" - default n - ---help--- - Enable HRTIM Events support. - -if STM32_HRTIM_EVENTS - -config STM32_HRTIM_EEV1 - bool "HRTIM EEV1" - default n - -config STM32_HRTIM_EEV2 - bool "HRTIM EEV2" - default n - -config STM32_HRTIM_EEV3 - bool "HRTIM EEV3" - default n - -config STM32_HRTIM_EEV4 - bool "HRTIM EEV4" - default n - -config STM32_HRTIM_EEV5 - bool "HRTIM EEV5" - default n - -config STM32_HRTIM_EEV6 - bool "HRTIM EEV6" - default n - -config STM32_HRTIM_EEV7 - bool "HRTIM EEV7" - default n - -config STM32_HRTIM_EEV8 - bool "HRTIM EEV8" - default n - -config STM32_HRTIM_EEV9 - bool "HRTIM EEV9" - default n - -config STM32_HRTIM_EEV10 - bool "HRTIM EEV10" - default n - -endif # STM32_HRTIM_EVENTS - -menuconfig STM32_HRTIM_FAULTS - bool "HRTIM Faults Configuration" - default n - ---help--- - Enable HRTIM Faults support. - -if STM32_HRTIM_FAULTS - -config STM32_HRTIM_FAULT1 - bool "HRTIM Fault 1" - default n - -config STM32_HRTIM_FAULT2 - bool "HRTIM Fault 2" - default n - -config STM32_HRTIM_FAULT3 - bool "HRTIM Fault 3" - default n - -config STM32_HRTIM_FAULT4 - bool "HRTIM Fault 4" - default n - -endif # STM32_HRTIM_FAULTS - -config STM32_HRTIM_CLK_FROM_PLL - bool "HRTIM Clock from PLL" - default n - depends on STM32_HAVE_HRTIM1_PLLCLK - ---help--- - Set PLL as the clock source for HRTIM. - This configuration requires the following conditions: - 1) system clock is PLL, - 2) SYSCLK and PCLK2 ratio must be 1 o 2. - -menu "HRTIM Master Configuration" - depends on STM32_HRTIM_MASTER - -config STM32_HRTIM_MASTER_DAC - bool "HRTIM Master DAC Triggering" - default n - depends on STM32_HRTIM_DAC - -config STM32_HRTIM_MASTER_DMA - bool "HRTIM MASTER DMA" - default n - depends on STM32_HRTIM_DMA - -config STM32_HRTIM_MASTER_IRQ - bool "HRTIM MASTER Interrupts" - default n - depends on STM32_HRTIM_INTERRUPTS - -endmenu # "HRTIM Master Configuration" - -menu "HRTIM Timer A Configuration" - depends on STM32_HRTIM_TIMA - -config STM32_HRTIM_TIMA_CAP - bool "HRTIM TIMA Capture" - default n - depends on STM32_HRTIM_CAPTURE - -config STM32_HRTIM_TIMA_DAC - bool "HRTIM TIMA DAC Triggering" - default n - depends on STM32_HRTIM_DAC - -config STM32_HRTIM_TIMA_DMA - bool "HRTIM TIMA DMA" - default n - depends on STM32_HRTIM_DMA - -config STM32_HRTIM_TIMA_IRQ - bool "HRTIM TIMA Interrupts" - default n - depends on STM32_HRTIM_INTERRUPTS - -config STM32_HRTIM_TIMA_PWM - bool "HRTIM TIMA PWM Outputs" - default n - depends on STM32_HRTIM_PWM - -config STM32_HRTIM_TIMA_PWM_CH1 - bool "HRTIM TIMA PWM Output 1" - default n - depends on STM32_HRTIM_TIMA_PWM - -config STM32_HRTIM_TIMA_PWM_CH2 - bool "HRTIM TIMA PWM Output 2" - default n - depends on STM32_HRTIM_TIMA_PWM - -config STM32_HRTIM_TIMA_BURST - bool "HRTIM TIMA Burst" - default n - depends on (STM32_HRTIM_BURST && STM32_HRTIM_TIMA_PWM) - -config STM32_HRTIM_TIMA_BURST_CH1 - bool "HRTIM TIMA Output 1 Burst Mode" - default n - depends on (STM32_HRTIM_TIMA_BURST && STM32_HRTIM_TIMA_PWM_CH1) - -config STM32_HRTIM_TIMA_BURST_CH2 - bool "HRTIM TIMA Output 2 Burst Mode" - default n - depends on (STM32_HRTIM_TIMA_BURST && STM32_HRTIM_TIMA_PWM_CH2) - -config STM32_HRTIM_TIMA_CHOP - bool "HRTIM TIMA PWM Chopper" - default n - depends on (STM32_HRTIM_CHOPPER && STM32_HRTIM_TIMA_PWM) - -config STM32_HRTIM_TIMA_DT - bool "HRTIM TIMA PWM Dead-time" - default n - depends on (STM32_HRTIM_DEADTIME && STM32_HRTIM_TIMA_PWM) - -config STM32_HRTIM_TIMA_PSHPLL - bool "HRTIM TIMA PWM Push-pull mode" - default n - depends on (STM32_HRTIM_PUSHPULL && STM32_HRTIM_TIMA_PWM) - -endmenu # "HRTIM Timer A Configuration" - -menu "HRTIM Timer B Configuration" - depends on STM32_HRTIM_TIMB - -config STM32_HRTIM_TIMB_CAP - bool "HRTIM TIMB Capture" - default n - depends on STM32_HRTIM_CAPTURE - -config STM32_HRTIM_TIMB_DAC - bool "HRTIM TIMB DAC Triggering" - default n - depends on STM32_HRTIM_DAC - -config STM32_HRTIM_TIMB_DMA - bool "HRTIM TIMB DMA" - default n - depends on STM32_HRTIM_DMA - -config STM32_HRTIM_TIMB_IRQ - bool "HRTIM TIMB Interrupts" - default n - depends on STM32_HRTIM_INTERRUPTS - -config STM32_HRTIM_TIMB_PWM - bool "HRTIM TIMB PWM Outputs" - default n - depends on STM32_HRTIM_PWM - -config STM32_HRTIM_TIMB_PWM_CH1 - bool "HRTIM TIMB PWM Output 1" - default n - depends on STM32_HRTIM_TIMB_PWM - -config STM32_HRTIM_TIMB_PWM_CH2 - bool "HRTIM TIMB PWM Output 2" - default n - depends on STM32_HRTIM_TIMB_PWM - -config STM32_HRTIM_TIMB_BURST - bool "HRTIM TIMB Burst" - default n - depends on (STM32_HRTIM_BURST && STM32_HRTIM_TIMB_PWM) - -config STM32_HRTIM_TIMB_BURST_CH1 - bool "HRTIM TIMB Output 1 Burst Mode" - default n - depends on (STM32_HRTIM_TIMB_BURST && STM32_HRTIM_TIMB_PWM_CH1) - -config STM32_HRTIM_TIMB_BURST_CH2 - bool "HRTIM TIMB Output 2 Burst Mode" - default n - depends on (STM32_HRTIM_TIMB_BURST && STM32_HRTIM_TIMB_PWM_CH2) - -config STM32_HRTIM_TIMB_CHOP - bool "HRTIM TIMB PWM Chopper" - default n - depends on (STM32_HRTIM_CHOPPER && STM32_HRTIM_TIMB_PWM) - -config STM32_HRTIM_TIMB_DT - bool "HRTIM TIMB PWM Dead-time" - default n - depends on (STM32_HRTIM_DEADTIME && STM32_HRTIM_TIMB_PWM) - -config STM32_HRTIM_TIMB_PSHPLL - bool "HRTIM TIMB PWM Push-pull mode" - default n - depends on (STM32_HRTIM_PUSHPULL && STM32_HRTIM_TIMB_PWM) - -endmenu # "HRTIM Timer B Configuration" - -menu "HRTIM Timer C Configuration" - depends on STM32_HRTIM_TIMC - -config STM32_HRTIM_TIMC_CAP - bool "HRTIM TIMC Capture" - default n - depends on STM32_HRTIM_CAPTURE - -config STM32_HRTIM_TIMC_DAC - bool "HRTIM TIMC DAC Triggering" - default n - depends on STM32_HRTIM_DAC - -config STM32_HRTIM_TIMC_DMA - bool "HRTIM TIMC DMA" - default n - depends on STM32_HRTIM_DMA - -config STM32_HRTIM_TIMC_IRQ - bool "HRTIM TIMC Interrupts" - default n - depends on STM32_HRTIM_INTERRUPTS - -config STM32_HRTIM_TIMC_PWM - bool "HRTIM TIMC PWM Outputs" - default n - depends on STM32_HRTIM_PWM - -config STM32_HRTIM_TIMC_PWM_CH1 - bool "HRTIM TIMC PWM Output 1" - default n - depends on STM32_HRTIM_TIMC_PWM - -config STM32_HRTIM_TIMC_PWM_CH2 - bool "HRTIM TIMC PWM Output 2" - default n - depends on STM32_HRTIM_TIMC_PWM - -config STM32_HRTIM_TIMC_BURST - bool "HRTIM TIMC Burst" - default n - depends on (STM32_HRTIM_BURST && STM32_HRTIM_TIMC_PWM) - -config STM32_HRTIM_TIMC_BURST_CH1 - bool "HRTIM TIMC Output 1 Burst Mode" - default n - depends on (STM32_HRTIM_TIMC_BURST && STM32_HRTIM_TIMC_PWM_CH1) - -config STM32_HRTIM_TIMC_BURST_CH2 - bool "HRTIM TIMC Output 2 Burst Mode" - default n - depends on (STM32_HRTIM_TIMC_BURST && STM32_HRTIM_TIMC_PWM_CH2) - -config STM32_HRTIM_TIMC_CHOP - bool "HRTIM TIMC PWM Chopper" - default n - depends on (STM32_HRTIM_CHOPPER && STM32_HRTIM_TIMC_PWM) - -config STM32_HRTIM_TIMC_DT - bool "HRTIM TIMC PWM Dead-time" - default n - depends on (STM32_HRTIM_DEADTIME && STM32_HRTIM_TIMC_PWM) - -config STM32_HRTIM_TIMC_PSHPLL - bool "HRTIM TIMC PWM Push-pull mode" - default n - depends on (STM32_HRTIM_PUSHPULL && STM32_HRTIM_TIMC_PWM) - -endmenu # "HRTIM Timer C Configuration" - -menu "HRTIM Timer D Configuration" - depends on STM32_HRTIM_TIMD - -config STM32_HRTIM_TIMD_CAP - bool "HRTIM TIMD Capture" - default n - depends on STM32_HRTIM_CAPTURE - -config STM32_HRTIM_TIMD_DAC - bool "HRTIM TIMD DAC Triggering" - default n - depends on STM32_HRTIM_DAC - -config STM32_HRTIM_TIMD_DMA - bool "HRTIM TIMD DMA" - default n - depends on STM32_HRTIM_DMA - -config STM32_HRTIM_TIMD_IRQ - bool "HRTIM TIMD Interrupts" - default n - depends on STM32_HRTIM_INTERRUPTS - -config STM32_HRTIM_TIMD_PWM - bool "HRTIM TIMD PWM Outputs" - default n - depends on STM32_HRTIM_PWM - -config STM32_HRTIM_TIMD_PWM_CH1 - bool "HRTIM TIMD PWM Output 1" - default n - depends on STM32_HRTIM_TIMD_PWM - -config STM32_HRTIM_TIMD_PWM_CH2 - bool "HRTIM TIMD PWM Output 2" - default n - depends on STM32_HRTIM_TIMD_PWM - -config STM32_HRTIM_TIMD_BURST - bool "HRTIM TIMD Burst" - default n - depends on (STM32_HRTIM_BURST && STM32_HRTIM_TIMD_PWM) - -config STM32_HRTIM_TIMD_BURST_CH1 - bool "HRTIM TIMD Output 1 Burst Mode" - default n - depends on (STM32_HRTIM_TIMD_BURST && STM32_HRTIM_TIMD_PWM_CH1) - -config STM32_HRTIM_TIMD_BURST_CH2 - bool "HRTIM TIMD Output 2 Burst Mode" - default n - depends on (STM32_HRTIM_TIMD_BURST && STM32_HRTIM_TIMD_PWM_CH2) - -config STM32_HRTIM_TIMD_CHOP - bool "HRTIM TIMD PWM Chopper" - default n - depends on (STM32_HRTIM_CHOPPER && STM32_HRTIM_TIMD_PWM) - -config STM32_HRTIM_TIMD_DT - bool "HRTIM TIMD PWM Dead-time" - default n - depends on (STM32_HRTIM_DEADTIME && STM32_HRTIM_TIMD_PWM) - -config STM32_HRTIM_TIMD_PSHPLL - bool "HRTIM TIMD PWM Push-pull mode" - default n - depends on (STM32_HRTIM_PUSHPULL && STM32_HRTIM_TIMD_PWM) - -endmenu # "HRTIM Timer D Configuration" - -menu "HRTIM Timer E Configuration" - depends on STM32_HRTIM_TIME - -config STM32_HRTIM_TIME_CAP - bool "HRTIM TIME Capture" - default n - depends on STM32_HRTIM_CAPTURE - -config STM32_HRTIM_TIME_DAC - bool "HRTIM TIME DAC Triggering" - default n - depends on STM32_HRTIM_DAC - -config STM32_HRTIM_TIME_DMA - bool "HRTIM TIME DMA" - default n - depends on STM32_HRTIM_DMA - -config STM32_HRTIM_TIME_IRQ - bool "HRTIM TIME Interrupts" - default n - depends on STM32_HRTIM_INTERRUPTS - -config STM32_HRTIM_TIME_PWM - bool "HRTIM TIME PWM Outputs" - default n - depends on STM32_HRTIM_PWM - -config STM32_HRTIM_TIME_PWM_CH1 - bool "HRTIM TIME PWM Output 1" - default n - depends on STM32_HRTIM_TIME_PWM - -config STM32_HRTIM_TIME_PWM_CH2 - bool "HRTIM TIME PWM Output 2" - default n - depends on STM32_HRTIM_TIME_PWM - -config STM32_HRTIM_TIME_BURST - bool "HRTIM TIME Burst" - default n - depends on (STM32_HRTIM_BURST && STM32_HRTIM_TIME_PWM) - -config STM32_HRTIM_TIME_BURST_CH1 - bool "HRTIM TIME Output 1 Burst Mode" - default n - depends on (STM32_HRTIM_TIME_BURST && STM32_HRTIM_TIME_PWM_CH1) - -config STM32_HRTIM_TIME_BURST_CH2 - bool "HRTIM TIME Output 2 Burst Mode" - default n - depends on (STM32_HRTIM_TIME_BURST && STM32_HRTIM_TIME_PWM_CH2) - -config STM32_HRTIM_TIME_CHOP - bool "HRTIM TIME PWM Chopper" - default n - depends on (STM32_HRTIM_CHOPPER && STM32_HRTIM_TIME_PWM) - -config STM32_HRTIM_TIME_DT - bool "HRTIM TIME PWM Dead-time" - default n - depends on (STM32_HRTIM_DEADTIME && STM32_HRTIM_TIME_PWM) - -config STM32_HRTIM_TIME_PSHPLL - bool "HRTIM TIME PWM Push-pull mode" - default n - depends on (STM32_HRTIM_PUSHPULL && STM32_HRTIM_TIME_PWM) - -endmenu # "HRTIM Timer E Configuration" - -endmenu # "HRTIM Configuration" - -menu "ADC Configuration" - depends on STM32_ADC - -config STM32_ADC1_RESOLUTION - int "ADC1 resolution" - depends on STM32_ADC1 && !STM32_HAVE_IP_ADC_V1_BASIC - default 0 - range 0 3 - ---help--- - ADC1 resolution. 0 - 12 bit, 1 - 10 bit, 2 - 8 bit, 3 - 6 bit - -config STM32_ADC2_RESOLUTION - int "ADC2 resolution" - depends on STM32_ADC2 && !STM32_HAVE_IP_ADC_V1_BASIC - default 0 - range 0 3 - ---help--- - ADC2 resolution. 0 - 12 bit, 1 - 10 bit, 2 - 8 bit, 3 - 6 bit - -config STM32_ADC3_RESOLUTION - int "ADC3 resolution" - depends on STM32_ADC3 && !STM32_HAVE_IP_ADC_V1_BASIC - default 0 - range 0 3 - ---help--- - ADC3 resolution. 0 - 12 bit, 1 - 10 bit, 2 - 8 bit, 3 - 6 bit - -config STM32_ADC4_RESOLUTION - int "ADC4 resolution" - depends on STM32_ADC4 && !STM32_HAVE_IP_ADC_V1_BASIC - default 0 - range 0 3 - ---help--- - ADC4 resolution. 0 - 12 bit, 1 - 10 bit, 2 - 8 bit, 3 - 6 bit - -config STM32_ADC5_RESOLUTION - int "ADC5 resolution" - depends on STM32_ADC5 && !STM32_HAVE_IP_ADC_V1_BASIC - default 0 - range 0 3 - ---help--- - ADC5 resolution. 0 - 12 bit, 1 - 10 bit, 2 - 8 bit, 3 - 6 bit - -config STM32_ADC_MAX_SAMPLES - int "The maximum number of channels that can be sampled" - default 16 - ---help--- - The maximum number of samples which can be handled without - overrun depends on various factors. This is the user's - responsibility to correctly select this value. - Since the interface to update the sampling time is available - for all supported devices, the user can change the default - values in the board initialization logic and avoid ADC overrun. - -config STM32_ADC_NO_STARTUP_CONV - bool "Do not start conversion when opening ADC device" - default n - ---help--- - Do not start conversion when opening ADC device. - -config STM32_ADC_NOIRQ - bool "Do not use default ADC interrupts" - default n - ---help--- - Do not use default ADC interrupts handlers. - -config STM32_ADC_LL_OPS - bool "ADC low-level operations" - default n - ---help--- - Enable low-level ADC ops. - -config STM32_ADC_CHANGE_SAMPLETIME - bool "ADC sample time configuration" - default n - depends on STM32_ADC_LL_OPS - ---help--- - Enable ADC sample time configuration (SMPRx registers). - -config STM32_ADC1_DMA - bool "ADC1 DMA" - depends on STM32_ADC1 && STM32_HAVE_ADC1_DMA - default n - ---help--- - If DMA is selected, then the ADC may be configured to support - DMA transfer, which is necessary if multiple channels are read - or if very high trigger frequencies are used. - -config STM32_ADC1_SCAN - bool "ADC1 scan mode" - depends on STM32_ADC1 && STM32_HAVE_IP_ADC_V1 - default STM32_ADC1_DMA - default n - -config STM32_ADC1_DMA_CFG - int "ADC1 DMA configuration" - depends on STM32_ADC1_DMA && !STM32_HAVE_IP_ADC_V1_BASIC - range 0 1 - default 0 - ---help--- - 0 - ADC1 DMA in One Shot Mode, 1 - ADC1 DMA in Circular Mode - -config STM32_ADC1_DMA_BATCH - int "ADC1 DMA number of conversions" - depends on STM32_ADC1 && STM32_ADC1_DMA - default 1 - ---help--- - This option allows you to select the number of regular group conversions - that will trigger a DMA callback transerring data to the upper-half driver. - By default, this value is 1, which means that data is transferred after - each group conversion. - -config STM32_ADC1_ANIOC_TRIGGER - int "ADC1 software trigger (ANIOC_TRIGGER) configuration" - depends on STM32_ADC1 - range 1 3 - default 3 - ---help--- - 1 - ANIOC_TRIGGER only starts regular conversion - 2 - ANIOC_TRIGGER only starts injected conversion - 3 - ANIOC_TRIGGER starts both regular and injected conversions - -config STM32_ADC2_DMA - bool "ADC2 DMA" - depends on STM32_ADC2 && STM32_HAVE_ADC2_DMA - default n - ---help--- - If DMA is selected, then the ADC may be configured to support - DMA transfer, which is necessary if multiple channels are read - or if very high trigger frequencies are used. - -config STM32_ADC2_SCAN - bool "ADC2 scan mode" - depends on STM32_ADC2 && STM32_HAVE_IP_ADC_V1 - default STM32_ADC2_DMA - default n - -config STM32_ADC2_DMA_CFG - int "ADC2 DMA configuration" - depends on STM32_ADC2_DMA && !STM32_HAVE_IP_ADC_V1_BASIC - range 0 1 - default 0 - ---help--- - 0 - ADC2 DMA in One Shot Mode, 1 - ADC2 DMA in Circular Mode - -config STM32_ADC2_DMA_BATCH - int "ADC2 DMA number of conversions" - depends on STM32_ADC2 && STM32_ADC2_DMA - default 1 - ---help--- - This option allows you to select the number of regular group conversions - that will trigger a DMA callback transerring data to the upper-half driver. - By default, this value is 1, which means that data is transferred after - each group conversion. - -config STM32_ADC2_ANIOC_TRIGGER - int "ADC2 software trigger (ANIOC_TRIGGER) configuration" - depends on STM32_ADC2 - range 1 3 - default 3 - ---help--- - 1 - ANIOC_TRIGGER only starts regular conversion - 2 - ANIOC_TRIGGER only starts injected conversion - 3 - ANIOC_TRIGGER starts both regular and injected conversions - -config STM32_ADC3_DMA - bool "ADC3 DMA" - depends on STM32_ADC3 && STM32_HAVE_ADC3_DMA - default n - ---help--- - If DMA is selected, then the ADC may be configured to support - DMA transfer, which is necessary if multiple channels are read - or if very high trigger frequencies are used. - -config STM32_ADC3_SCAN - bool "ADC3 scan mode" - depends on STM32_ADC3 && STM32_HAVE_IP_ADC_V1 - default STM32_ADC3_DMA - default n - -config STM32_ADC3_DMA_CFG - int "ADC3 DMA configuration" - depends on STM32_ADC3_DMA && !STM32_HAVE_IP_ADC_V1_BASIC - range 0 1 - default 0 - ---help--- - 0 - ADC3 DMA in One Shot Mode, 1 - ADC3 DMA in Circular Mode - -config STM32_ADC3_DMA_BATCH - int "ADC3 DMA number of conversions" - depends on STM32_ADC3 && STM32_ADC3_DMA - default 1 - ---help--- - This option allows you to select the number of regular group conversions - that will trigger a DMA callback transerring data to the upper-half driver. - By default, this value is 1, which means that data is transferred after - each group conversion. - -config STM32_ADC3_ANIOC_TRIGGER - int "ADC3 software trigger (ANIOC_TRIGGER) configuration" - depends on STM32_ADC3 - range 1 3 - default 3 - ---help--- - 1 - ANIOC_TRIGGER only starts regular conversion - 2 - ANIOC_TRIGGER only starts injected conversion - 3 - ANIOC_TRIGGER starts both regular and injected conversions - -config STM32_ADC4_DMA - bool "ADC4 DMA" - depends on STM32_ADC4 && STM32_HAVE_ADC4_DMA - default n - ---help--- - If DMA is selected, then the ADC may be configured to support - DMA transfer, which is necessary if multiple channels are read - or if very high trigger frequencies are used. - -config STM32_ADC4_DMA_CFG - int "ADC4 DMA configuration" - depends on STM32_ADC4_DMA && !STM32_HAVE_IP_ADC_V1_BASIC - range 0 1 - default 0 - ---help--- - 0 - ADC4 DMA in One Shot Mode, 1 - ADC4 DMA in Circular Mode - -config STM32_ADC4_DMA_BATCH - int "ADC4 DMA number of conversions" - depends on STM32_ADC4 && STM32_ADC4_DMA - default 1 - ---help--- - This option allows you to select the number of regular group conversions - that will trigger a DMA callback transerring data to the upper-half driver. - By default, this value is 1, which means that data is transferred after - each group conversion. - -config STM32_ADC4_ANIOC_TRIGGER - int "ADC4 software trigger (ANIOC_TRIGGER) configuration" - depends on STM32_ADC4 - range 1 3 - default 3 - ---help--- - 1 - ANIOC_TRIGGER only starts regular conversion - 2 - ANIOC_TRIGGER only starts injected conversion - 3 - ANIOC_TRIGGER starts both regular and injected conversions - -config STM32_ADC5_DMA - bool "ADC5 DMA" - depends on STM32_ADC5 && STM32_HAVE_ADC5_DMA - default n - ---help--- - If DMA is selected, then the ADC may be configured to support - DMA transfer, which is necessary if multiple channels are read - or if very high trigger frequencies are used. - -config STM32_ADC5_DMA_CFG - int "ADC5 DMA configuration" - depends on STM32_ADC5_DMA && !STM32_HAVE_IP_ADC_V1_BASIC - range 0 1 - default 0 - ---help--- - 0 - ADC5 DMA in One Shot Mode, 1 - ADC5 DMA in Circular Mode - -config STM32_ADC5_DMA_BATCH - int "ADC5 DMA number of conversions" - depends on STM32_ADC5 && STM32_ADC5_DMA - default 1 - ---help--- - This option allows you to select the number of regular group conversions - that will trigger a DMA callback transerring data to the upper-half driver. - By default, this value is 1, which means that data is transferred after - each group conversion. - -config STM32_ADC1_INJECTED_CHAN - int "ADC1 injected channels" - depends on STM32_ADC1 - range 0 4 - default 0 - ---help--- - Support for ADC1 injected channels. - -config STM32_ADC2_INJECTED_CHAN - int "ADC2 injected channels" - depends on STM32_ADC2 - range 0 4 - default 0 - ---help--- - Support for ADC2 injected channels. - -config STM32_ADC3_INJECTED_CHAN - int "ADC3 injected channels" - depends on STM32_ADC3 - range 0 4 - default 0 - ---help--- - Support for ADC3 injected channels. - -config STM32_ADC4_INJECTED_CHAN - int "ADC4 injected channels" - depends on STM32_ADC4 - range 0 4 - default 0 - ---help--- - Support for ADC4 injected channels. - -config STM32_ADC5_INJECTED_CHAN - int "ADC5 injected channels" - depends on STM32_ADC5 - range 0 4 - default 0 - ---help--- - Support for ADC5 injected channels. - -config STM32_ADC1_EXTSEL - bool "ADC1 external trigger for regular group" - depends on STM32_ADC1 && !STM32_HAVE_ADC1_TIMER - default n - ---help--- - Enable EXTSEL for ADC1. - -config STM32_ADC2_EXTSEL - bool "ADC2 external trigger for regular group" - depends on STM32_ADC2 && !STM32_HAVE_ADC2_TIMER - default n - ---help--- - Enable EXTSEL for ADC2. - -config STM32_ADC3_EXTSEL - bool "ADC3 external trigger for regular group" - depends on STM32_ADC3 && !STM32_HAVE_ADC3_TIMER - default n - ---help--- - Enable EXTSEL for ADC3. - -config STM32_ADC4_EXTSEL - bool "ADC4 external trigger for regular group" - depends on STM32_ADC4 && !STM32_HAVE_ADC4_TIMER - default n - ---help--- - Enable EXTSEL for ADC4. - -config STM32_ADC5_EXTSEL - bool "ADC5 external trigger for regular group" - depends on STM32_ADC5 && !STM32_HAVE_ADC5_TIMER - default n - ---help--- - Enable EXTSEL for ADC5. - -config STM32_ADC1_JEXTSEL - bool "ADC1 external trigger for injected group" - depends on STM32_ADC1 - default n - ---help--- - Enable JEXTSEL for ADC1. - -config STM32_ADC2_JEXTSEL - bool "ADC2 external trigger for injected group" - depends on STM32_ADC2 - default n - ---help--- - Enable JEXTSEL for ADC2. - -config STM32_ADC3_JEXTSEL - bool "ADC3 external trigger for injected group" - depends on STM32_ADC3 - default n - ---help--- - Enable JEXTSEL for ADC3. - -config STM32_ADC4_JEXTSEL - bool "ADC4 external trigger for injected group" - depends on STM32_ADC4 - default n - ---help--- - Enable JEXTSEL for ADC4. - -config STM32_ADC5_JEXTSEL - bool "ADC5 external trigger for injected group" - depends on STM32_ADC5 - default n - ---help--- - Enable JEXTSEL for ADC5. - -endmenu - -menu "COMP Configuration" - depends on STM32_COMP && STM32_HAVE_IP_COMP_V2 - -config STM32_COMP1_OUT - bool "COMP1 GPIO Output" - depends on STM32_COMP1 - default n - ---help--- - Enables COMP1 output. - -config STM32_COMP1_INM - int "COMP1 inverting input assignment" - depends on STM32_COMP1 - range 0 7 - default 0 - ---help--- - Selects COMP1 inverting input pin. - -config STM32_COMP1_INP - int "COMP1 non-inverting input assignment" - depends on STM32_COMP1 - range 0 1 - default 0 - ---help--- - Selects COMP1 non-inverting input pin. - -config STM32_COMP1_POL - int "COMP1 polarity" - depends on STM32_COMP1 - range 0 1 - default 0 - ---help--- - Selects COMP1 output polarity. - -config STM32_COMP1_HYST - int "COMP1 hysteresis" - depends on STM32_STM32G4XXX && STM32_COMP1 - range 0 7 - default 0 - ---help--- - Selects the hysteresis of the COMP1. - -config STM32_COMP1_BLANKSEL - int "COMP1 blanking signal select" - depends on STM32_COMP1 - range 0 7 - default 0 - ---help--- - Selects the blanking signal for comparator COMP1. - -config STM32_COMP1_LOCK - int "COMP1 COMP_CxCSR register lock" - depends on STM32_COMP1 - range 0 1 - default 0 - ---help--- - Locks COMP_CxCSR register. - 0 - Unlock 1 - Lock - -config STM32_COMP2_OUT - bool "COMP2 GPIO Output" - depends on STM32_COMP2 - default n - ---help--- - Enables COMP2 output. - -config STM32_COMP2_INM - int "COMP2 inverting input assignment" - depends on STM32_COMP2 - range 0 7 - default 0 - ---help--- - Selects COMP2 inverting input pin. - -config STM32_COMP2_INP - int "COMP2 non-inverting input assignment" - depends on STM32_COMP2 - range 0 1 - default 0 - ---help--- - Selects COMP2 non-inverting input pin. - -config STM32_COMP2_POL - int "COMP2 polarity" - depends on STM32_COMP2 - range 0 1 - default 0 - ---help--- - Selects COMP2 output polarity. - -config STM32_COMP2_HYST - int "COMP2 hysteresis" - depends on STM32_STM32G4XXX && STM32_COMP2 - range 0 7 - default 0 - ---help--- - Selects the hysteresis of the COMP2. - -config STM32_COMP2_BLANKSEL - int "COMP2 blanking signal select" - depends on STM32_COMP2 - range 0 7 - default 0 - ---help--- - Selects the blanking signal for comparator COMP2. - -config STM32_COMP2_LOCK - int "COMP2 COMP_CxCSR register lock" - depends on STM32_COMP2 - range 0 1 - default 0 - ---help--- - Locks COMP_CxCSR register. - 0 - Unlock 1 - Lock - -config STM32_COMP3_OUT - bool "COMP3 GPIO Output" - depends on STM32_COMP3 - default n - ---help--- - Enables COMP3 output. - -config STM32_COMP3_INM - int "COMP3 inverting input assignment" - depends on STM32_COMP3 - range 0 7 - default 0 - ---help--- - Selects COMP3 inverting input pin. - -config STM32_COMP3_INP - int "COMP3 non-inverting input assignment" - depends on STM32_COMP3 - range 0 1 - default 0 - ---help--- - Selects COMP3 non-inverting input pin. - -config STM32_COMP3_POL - int "COMP3 polarity" - depends on STM32_COMP3 - range 0 1 - default 0 - ---help--- - Selects COMP3 output polarity. - -config STM32_COMP3_HYST - int "COMP3 hysteresis" - depends on STM32_STM32G4XXX && STM32_COMP3 - range 0 7 - default 0 - ---help--- - Selects the hysteresis of the COMP3. - -config STM32_COMP3_BLANKSEL - int "COMP3 blanking signal select" - depends on STM32_COMP3 - range 0 7 - default 0 - ---help--- - Selects the blanking signal for comparator COMP3. - -config STM32_COMP3_LOCK - int "COMP3 COMP_CxCSR register lock" - depends on STM32_COMP3 - range 0 1 - default 0 - ---help--- - Locks COMP_CxCSR register. - 0 - Unlock 1 - Lock - -config STM32_COMP4_OUT - bool "COMP4 GPIO Output" - depends on STM32_COMP4 - default n - ---help--- - Enables COMP4 output. - -config STM32_COMP4_INM - int "COMP4 inverting input assignment" - depends on STM32_COMP4 - range 0 7 - default 0 - ---help--- - Selects COMP4 inverting input pin. - -config STM32_COMP4_INP - int "COMP4 non-inverting input assignment" - depends on STM32_COMP4 - range 0 1 - default 0 - ---help--- - Selects COMP4 non-inverting input pin. - -config STM32_COMP4_POL - int "COMP4 polarity" - depends on STM32_COMP4 - range 0 1 - default 0 - ---help--- - Selects COMP4 output polarity. - -config STM32_COMP4_HYST - int "COMP4 hysteresis" - depends on STM32_STM32G4XXX && STM32_COMP4 - range 0 7 - default 0 - ---help--- - Selects the hysteresis of the COMP4. - -config STM32_COMP4_BLANKSEL - int "COMP4 blanking signal select" - depends on STM32_COMP4 - range 0 7 - default 0 - ---help--- - Selects the blanking signal for comparator COMP4. - -config STM32_COMP4_LOCK - int "COMP4 COMP_CxCSR register lock" - depends on STM32_COMP4 - range 0 1 - default 0 - ---help--- - Locks COMP_CxCSR register. - 0 - Unlock 1 - Lock - -config STM32_COMP5_OUT - bool "COMP5 GPIO Output" - depends on STM32_COMP5 - default n - ---help--- - Enables COMP5 output. - -config STM32_COMP5_INM - int "COMP5 inverting input assignment" - depends on STM32_COMP5 - range 0 7 - default 0 - ---help--- - Selects COMP5 inverting input pin. - -config STM32_COMP5_INP - int "COMP5 non-inverting input assignment" - depends on STM32_COMP5 - range 0 1 - default 0 - ---help--- - Selects COMP5 non-inverting input pin. - -config STM32_COMP5_POL - int "COMP5 polarity" - depends on STM32_COMP5 - range 0 1 - default 0 - ---help--- - Selects COMP5 output polarity. - -config STM32_COMP5_HYST - int "COMP5 hysteresis" - depends on STM32_STM32G4XXX && STM32_COMP5 - range 0 7 - default 0 - ---help--- - Selects the hysteresis of the COMP5. - -config STM32_COMP5_BLANKSEL - int "COMP5 blanking signal select" - depends on STM32_COMP5 - range 0 7 - default 0 - ---help--- - Selects the blanking signal for comparator COMP5. - -config STM32_COMP5_LOCK - int "COMP5 COMP_CxCSR register lock" - depends on STM32_COMP5 - range 0 1 - default 0 - ---help--- - Locks COMP_CxCSR register. - 0 - Unlock 1 - Lock - -config STM32_COMP6_OUT - bool "COMP6 GPIO Output" - depends on STM32_COMP6 - default n - ---help--- - Enables COMP6 output. - -config STM32_COMP6_INM - int "COMP6 inverting input assignment" - depends on STM32_COMP6 - range 0 7 - default 0 - ---help--- - Selects COMP6 inverting input pin. - -config STM32_COMP6_INP - int "COMP6 non-inverting input assignment" - depends on STM32_COMP6 - range 0 1 - default 0 - ---help--- - Selects COMP6 non-inverting input pin. - -config STM32_COMP6_POL - int "COMP6 polarity" - depends on STM32_COMP6 - range 0 1 - default 0 - ---help--- - Selects COMP6 output polarity. - -config STM32_COMP6_HYST - int "COMP6 hysteresis" - depends on STM32_STM32G4XXX && STM32_COMP6 - range 0 7 - default 0 - ---help--- - Selects the hysteresis of the COMP6. - -config STM32_COMP6_BLANKSEL - int "COMP6 blanking signal select" - depends on STM32_COMP6 - range 0 7 - default 0 - ---help--- - Selects the blanking signal for comparator COMP6. - -config STM32_COMP6_LOCK - int "COMP6 COMP_CxCSR register lock" - depends on STM32_COMP6 - range 0 1 - default 0 - ---help--- - Locks COMP_CxCSR register. - 0 - Unlock 1 - Lock - -config STM32_COMP7_OUT - bool "COMP7 GPIO Output" - depends on STM32_COMP7 - default n - ---help--- - Enables COMP7 output. - -config STM32_COMP7_INM - int "COMP7 inverting input assignment" - depends on STM32_COMP7 - range 0 7 - default 0 - ---help--- - Selects COMP7 inverting input pin. - -config STM32_COMP7_INP - int "COMP7 non-inverting input assignment" - depends on STM32_COMP7 - range 0 1 - default 0 - ---help--- - Selects COMP7 non-inverting input pin. - -config STM32_COMP7_POL - int "COMP7 polarity" - depends on STM32_COMP7 - range 0 1 - default 0 - ---help--- - Selects COMP7 output polarity. - -config STM32_COMP7_HYST - int "COMP7 hysteresis" - depends on STM32_STM32G4XXX && STM32_COMP7 - range 0 7 - default 0 - ---help--- - Selects the hysteresis of the COMP7. - -config STM32_COMP7_BLANKSEL - int "COMP7 blanking signal select" - depends on STM32_COMP7 - range 0 7 - default 0 - ---help--- - Selects the blanking signal for comparator COMP7. - -config STM32_COMP7_LOCK - int "COMP7 COMP_CxCSR register lock" - depends on STM32_COMP7 - range 0 1 - default 0 - ---help--- - Locks COMP_CxCSR register. - 0 - Unlock 1 - Lock - -endmenu - -menu "SDADC Configuration" - depends on STM32_SDADC - -config STM32_SDADC1_DMA - bool "SDADC1 DMA" - depends on STM32_SDADC1 && STM32_HAVE_SDADC1_DMA - default n - ---help--- - If DMA is selected, then the SDADC may be configured to support - DMA transfer, which is advisable if multiple channels are read - or if very high trigger frequencies are used. - -config STM32_SDADC2_DMA - bool "SDADC2 DMA" - depends on STM32_SDADC2 && STM32_HAVE_SDADC2_DMA - default n - ---help--- - If DMA is selected, then the SDADC may be configured to support - DMA transfer, which is advisable if multiple channels are read - or if very high trigger frequencies are used. - -config STM32_SDADC3_DMA - bool "SDADC3 DMA" - depends on STM32_SDADC3 && STM32_HAVE_SDADC3_DMA - default n - ---help--- - If DMA is selected, then the SDADC may be configured to support - DMA transfer, which is advisable if multiple channels are read - or if very high trigger frequencies are used. - -endmenu - -menu "DAC Configuration" - depends on STM32_DAC1 || STM32_DAC2 || STM32_DAC3 || STM32_DAC4 - -config STM32_DAC1CH1_MODE - int "DAC1CH1 channel mode" - depends on STM32_DAC1CH1 && STM32_HAVE_IP_DAC_V2 - default 0 - range 0 7 - ---help--- - – DAC channel in Normal mode - 0: DAC channel is connected to external pin with Buffer enabled - 1: DAC channel is connected to external pin and to on chip peripherals with buffer enabled - 2: DAC channel2 is connected to external pin with buffer disabled - 3: DAC channel is connected to on chip peripherals with Buffer disabled - - DAC channel in Sample and hold mode - 4: DAC channel is connected to external pin with Buffer enabled - 5: DAC channel is connected to external pin and to on chip peripherals with Buffer enabled - 6: DAC channel is connected to external pin and to on chip peripherals with Buffer disabled - 7: DAC channel is connected to on chip peripherals with Buffer disabled - -config STM32_DAC1CH1_DMA - bool "DAC1CH1 DMA" - depends on STM32_DAC1CH1 - default n - ---help--- - If DMA is selected, then a timer and output frequency must also be - provided to support the DMA transfer. The DMA transfer could be - supported by and EXTI trigger, but this feature is not currently - supported by the driver. - -if STM32_DAC1CH1_DMA - -config STM32_DAC1CH1_DMA_BUFFER_SIZE - int "DAC1CH1 DMA buffer size" - default 256 - -config STM32_DAC1CH1_DMA_EXTERNAL - bool "DAC1CH1 DMA External Trigger" - default n - -if STM32_HRTIM_DAC - -config STM32_DAC1CH1_HRTIM_TRG1 - bool "DAC1CH1 HRTIM Trigger 1" - default n - -config STM32_DAC1CH1_HRTIM_TRG2 - bool "DAC1CH1 HRTIM Trigger 2" - default n - -endif # STM32_HRTIM_DAC - -config STM32_DAC1CH1_TIMER - int "DAC1CH1 timer" - depends on !STM32_DAC1CH1_DMA_EXTERNAL - range 2 8 - -config STM32_DAC1CH1_TIMER_FREQUENCY - int "DAC1CH1 timer frequency" - depends on !STM32_DAC1CH1_DMA_EXTERNAL - default 0 - -endif - -config STM32_DAC1CH2_MODE - int "DAC1CH2 channel mode" - depends on STM32_DAC1CH2 && STM32_HAVE_IP_DAC_V2 - default 0 - range 0 7 - ---help--- - – DAC channel in Normal mode - 0: DAC channel is connected to external pin with Buffer enabled - 1: DAC channel is connected to external pin and to on chip peripherals with buffer enabled - 2: DAC channel2 is connected to external pin with buffer disabled - 3: DAC channel is connected to on chip peripherals with Buffer disabled - - DAC channel in Sample and hold mode - 4: DAC channel is connected to external pin with Buffer enabled - 5: DAC channel is connected to external pin and to on chip peripherals with Buffer enabled - 6: DAC channel is connected to external pin and to on chip peripherals with Buffer disabled - 7: DAC channel is connected to on chip peripherals with Buffer disabled - -config STM32_DAC1CH2_DMA - bool "DAC1CH2 DMA" - depends on STM32_DAC1CH2 - default n - ---help--- - If DMA is selected, then a timer and output frequency must also be - provided to support the DMA transfer. The DMA transfer could be - supported by and EXTI trigger, but this feature is not currently - supported by the driver. - -if STM32_DAC1CH2_DMA - -config STM32_DAC1CH2_DMA_BUFFER_SIZE - int "DAC1CH2 DMA buffer size" - default 256 - -config STM32_DAC1CH2_DMA_EXTERNAL - bool "DAC1CH2 DMA External Trigger" - default n - -if STM32_HRTIM_DAC - -config STM32_DAC1CH2_HRTIM_TRG1 - bool "DAC1CH2 HRTIM Trigger 1" - default n - -config STM32_DAC1CH2_HRTIM_TRG2 - bool "DAC1CH2 HRTIM Trigger 2" - default n - -endif # STM32_HRTIM_DAC - -config STM32_DAC1CH2_TIMER - int "DAC1CH2 timer" - depends on !STM32_DAC1CH2_DMA_EXTERNAL - range 2 8 - -config STM32_DAC1CH2_TIMER_FREQUENCY - int "DAC1CH2 timer frequency" - depends on !STM32_DAC1CH2_DMA_EXTERNAL - default 0 - -endif - -config STM32_DAC2CH1_MODE - int "DAC2CH1 channel mode" - depends on STM32_DAC2CH1 && STM32_HAVE_IP_DAC_V2 - default 0 - range 0 7 - ---help--- - – DAC channel in Normal mode - 0: DAC channel is connected to external pin with Buffer enabled - 1: DAC channel is connected to external pin and to on chip peripherals with buffer enabled - 2: DAC channel2 is connected to external pin with buffer disabled - 3: DAC channel is connected to on chip peripherals with Buffer disabled - - DAC channel in Sample and hold mode - 4: DAC channel is connected to external pin with Buffer enabled - 5: DAC channel is connected to external pin and to on chip peripherals with Buffer enabled - 6: DAC channel is connected to external pin and to on chip peripherals with Buffer disabled - 7: DAC channel is connected to on chip peripherals with Buffer disabled - -config STM32_DAC2CH1_DMA - bool "DAC2CH1 DMA" - depends on STM32_DAC2CH1 - default n - ---help--- - If DMA is selected, then a timer and output frequency must also be - provided to support the DMA transfer. The DMA transfer could be - supported by and EXTI trigger, but this feature is not currently - supported by the driver. - -if STM32_DAC2CH1_DMA - -config STM32_DAC2CH1_DMA_BUFFER_SIZE - int "DAC2CH1 DMA buffer size" - default 256 - -config STM32_DAC2CH1_DMA_EXTERNAL - bool "DAC2CH1 DMA External Trigger" - default n - -if STM32_HRTIM_DAC - -config STM32_DAC2CH1_HRTIM_TRG3 - bool "DAC2CH1 HRTIM Trigger 3" - default n - -endif # STM32_HRTIM_DAC - -config STM32_DAC2CH1_TIMER - int "DAC2CH1 timer" - depends on !STM32_DAC2CH1_DMA_EXTERNAL - default 0 - range 2 8 - -config STM32_DAC2CH1_TIMER_FREQUENCY - int "DAC2CH1 timer frequency" - depends on !STM32_DAC2CH1_DMA_EXTERNAL - default 0 - -endif - -config STM32_DAC3CH1_MODE - int "DAC3CH1 channel mode" - depends on STM32_DAC3CH1 && STM32_HAVE_IP_DAC_V2 - default 0 - range 0 7 - ---help--- - – DAC channel in Normal mode - 0: DAC channel is connected to external pin with Buffer enabled - 1: DAC channel is connected to external pin and to on chip peripherals with buffer enabled - 2: DAC channel is connected to external pin with buffer disabled - 3: DAC channel is connected to on chip peripherals with Buffer disabled - - DAC channel in Sample and hold mode - 4: DAC channel is connected to external pin with Buffer enabled - 5: DAC channel is connected to external pin and to on chip peripherals with Buffer enabled - 6: DAC channel is connected to external pin and to on chip peripherals with Buffer disabled - 7: DAC channel is connected to on chip peripherals with Buffer disabled - -config STM32_DAC3CH1_DMA - bool "DAC3CH1 DMA" - depends on STM32_DAC3CH1 - default n - ---help--- - If DMA is selected, then a timer and output frequency must also be - provided to support the DMA transfer. The DMA transfer could be - supported by an EXTI trigger, but this feature is not currently - supported by the driver. - -if STM32_DAC3CH1_DMA - -config STM32_DAC3CH1_DMA_BUFFER_SIZE - int "DAC3CH1 DMA buffer size" - default 256 - -config STM32_DAC3CH1_DMA_EXTERNAL - bool "DAC3CH1 DMA External Trigger" - default n - -if STM32_HRTIM_DAC - -config STM32_DAC3CH1_HRTIM_TRG3 - bool "DAC3CH1 HRTIM Trigger 3" - default n - -endif # STM32_HRTIM_DAC - -config STM32_DAC3CH1_TIMER - int "DAC3CH1 timer" - depends on !STM32_DAC3CH1_DMA_EXTERNAL - default 0 - range 2 8 - -config STM32_DAC3CH1_TIMER_FREQUENCY - int "DAC3CH1 timer frequency" - depends on !STM32_DAC3CH1_DMA_EXTERNAL - default 0 - -endif - -config STM32_DAC3CH2_MODE - int "DAC3CH2 channel mode" - depends on STM32_DAC3CH2 && STM32_HAVE_IP_DAC_V2 - default 0 - range 0 7 - ---help--- - – DAC channel in Normal mode - 0: DAC channel is connected to external pin with Buffer enabled - 1: DAC channel is connected to external pin and to on chip peripherals with buffer enabled - 2: DAC channel2 is connected to external pin with buffer disabled - 3: DAC channel is connected to on chip peripherals with Buffer disabled - - DAC channel in Sample and hold mode - 4: DAC channel is connected to external pin with Buffer enabled - 5: DAC channel is connected to external pin and to on chip peripherals with Buffer enabled - 6: DAC channel is connected to external pin and to on chip peripherals with Buffer disabled - 7: DAC channel is connected to on chip peripherals with Buffer disabled - -config STM32_DAC3CH2_DMA - bool "DAC3CH2 DMA" - depends on STM32_DAC3CH2 - default n - ---help--- - If DMA is selected, then a timer and output frequency must also be - provided to support the DMA transfer. The DMA transfer could be - supported by an EXTI trigger, but this feature is not currently - supported by the driver. - -if STM32_DAC3CH2_DMA - -config STM32_DAC3CH2_DMA_BUFFER_SIZE - int "DAC3CH2 DMA buffer size" - default 256 - -config STM32_DAC3CH2_DMA_EXTERNAL - bool "DAC3CH1 DMA External Trigger" - default n - -if STM32_HRTIM_DAC - -config STM32_DAC3CH2_HRTIM_TRG3 - bool "DAC3CH2 HRTIM Trigger 3" - default n - -endif # STM32_HRTIM_DAC - -config STM32_DAC3CH2_TIMER - int "DAC3CH2 timer" - depends on !STM32_DAC3CH2_DMA_EXTERNAL - default 0 - range 2 8 - -config STM32_DAC3CH2_TIMER_FREQUENCY - int "DAC3CH2 timer frequency" - depends on !STM32_DAC3CH2_DMA_EXTERNAL - default 0 - -endif - -endmenu - -config STM32_USART - bool - default n - -config STM32_SERIALDRIVER - bool - default n - -config STM32_1WIREDRIVER - bool - default n - -config STM32_HCIUART - bool - default n - -config STM32_HCIUART_RXDMA - bool - default n - -menu "U[S]ART Configuration" - depends on STM32_USART - -comment "U[S]ART Device Configuration" - -choice - prompt "USART1 Driver Configuration" - default STM32_USART1_SERIALDRIVER - depends on STM32_USART1 - -config STM32_USART1_SERIALDRIVER - bool "Standard serial driver" - select USART1_SERIALDRIVER - select ARCH_HAVE_SERIAL_TERMIOS - select STM32_SERIALDRIVER - -config STM32_USART1_1WIREDRIVER - bool "1-Wire driver" - select STM32_1WIREDRIVER - -config STM32_USART1_HCIUART - bool "Bluetooth HCI-UART" - select STM32_HCIUART - depends on WIRELESS_BLUETOOTH - -endchoice # USART1 Driver Configuration - -if STM32_USART1_SERIALDRIVER - -config USART1_RS485 - bool "RS-485 on USART1" - default n - ---help--- - Enable RS-485 interface on USART1. Your board config will have to - provide GPIO_USART1_RS485_DIR pin definition. Currently it cannot be - used with USART1_RXDMA. - -config USART1_RS485_DIR_POLARITY - int "USART1 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on USART1_RS485 - ---help--- - Polarity of DIR pin for RS-485 on USART1. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config USART1_RXDMA - bool "USART1 Rx DMA" - default n - depends on (((STM32_STM32F10XX || STM32_STM32L15XX) && STM32_DMA1) || (!STM32_STM32F10XX && STM32_DMA2)) - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -config USART1_TXDMA - bool "USART1 Tx DMA" - default n - depends on (((STM32_STM32F10XX || STM32_STM32L15XX) && STM32_DMA1) || (!STM32_STM32F10XX && STM32_DMA2)) - ---help--- - In high data rate usage, Tx DMA may reduce CPU load - -endif # STM32_USART1_SERIALDRIVER - -if STM32_USART1_HCIUART - -config STM32_HCIUART1_RXBUFSIZE - int "HCI UART1 Rx buffer size" - default 80 - ---help--- - Characters are buffered as they are received. This specifies - the size of the receive buffer. Ideally this should be at least - the size of the largest frame that can be received - -config STM32_HCIUART1_TXBUFSIZE - int "HCI UART1 Transmit buffer size" - default 80 - ---help--- - Characters are buffered before being sent. This specifies - the size of the transmit buffer. Ideally this should be at least - the size of the largest frame that can be sent - -config STM32_HCIUART1_BAUD - int "HCI UART1 initial BAUD rate" - default 115200 - ---help--- - The configured initial BAUD of the HCIR USART used during bringup. - In most cases this initial rate can be increased by the upper half - HCI UART driver using vendor-specifi HCI UART commands. - -config STM32_HCIUART1_RXDMA - bool "HCI UART1 Rx DMA" - default n - depends on (((STM32_STM32F10XX || STM32_STM32L15XX) && STM32_DMA1) || (!STM32_STM32F10XX && STM32_DMA2)) - select STM32_HCIUART_RXDMA - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -endif # STM32_USART1_HCIUART - -choice - prompt "USART2 Driver Configuration" - default STM32_USART2_SERIALDRIVER - depends on STM32_USART2 - -config STM32_USART2_SERIALDRIVER - bool "Standard serial driver" - select USART2_SERIALDRIVER - select ARCH_HAVE_SERIAL_TERMIOS - select STM32_SERIALDRIVER - -config STM32_USART2_1WIREDRIVER - bool "1-Wire driver" - select STM32_1WIREDRIVER - -config STM32_USART2_HCIUART - bool "Bluetooth HCI-UART" - select STM32_HCIUART - depends on WIRELESS_BLUETOOTH - -endchoice # USART2 Driver Configuration - -if STM32_USART2_SERIALDRIVER - -config USART2_RS485 - bool "RS-485 on USART2" - default n - ---help--- - Enable RS-485 interface on USART2. Your board config will have to - provide GPIO_USART2_RS485_DIR pin definition. Currently it cannot be - used with USART2_RXDMA. - -config USART2_RS485_DIR_POLARITY - int "USART2 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on USART2_RS485 - ---help--- - Polarity of DIR pin for RS-485 on USART2. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config USART2_RXDMA - bool "USART2 Rx DMA" - default n - depends on STM32_DMA1 - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -config USART2_TXDMA - bool "USART2 Tx DMA" - default n - depends on STM32_DMA1 - ---help--- - In high data rate usage, Tx DMA may reduce CPU load - -endif # STM32_USART2_SERIALDRIVER - -if STM32_USART2_HCIUART - -config STM32_HCIUART2_RXBUFSIZE - int "HCI UART2 Rx buffer size" - default 80 - ---help--- - Characters are buffered as they are received. This specifies - the size of the receive buffer. Ideally this should be at least - the size of the largest frame that can be received - -config STM32_HCIUART2_TXBUFSIZE - int "HCI UART2 Transmit buffer size" - default 80 - ---help--- - Characters are buffered before being sent. This specifies - the size of the transmit buffer. Ideally this should be at least - the size of the largest frame that can be sent - -config STM32_HCIUART2_BAUD - int "HCI UART2 initial BAUD rate" - default 115200 - ---help--- - The configured initial BAUD of the HCIR USART used during bringup. - In most cases this initial rate can be increased by the upper half - HCI UART driver using vendor-specifi HCI UART commands. - -config STM32_HCIUART2_RXDMA - bool "HCI UART2 Rx DMA" - default n - depends on STM32_DMA1 - select STM32_HCIUART_RXDMA - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -endif # STM32_USART2_HCIUART - -choice - prompt "USART3 Driver Configuration" - default STM32_USART3_SERIALDRIVER - depends on STM32_USART3 - -config STM32_USART3_SERIALDRIVER - bool "Standard serial driver" - select USART3_SERIALDRIVER - select ARCH_HAVE_SERIAL_TERMIOS - select STM32_SERIALDRIVER - -config STM32_USART3_1WIREDRIVER - bool "1-Wire driver" - select STM32_1WIREDRIVER - -config STM32_USART3_HCIUART - bool "Bluetooth HCI-UART" - select STM32_HCIUART - depends on WIRELESS_BLUETOOTH - -endchoice # USART3 Driver Configuration - -if STM32_USART3_SERIALDRIVER - -config USART3_RS485 - bool "RS-485 on USART3" - default n - ---help--- - Enable RS-485 interface on USART3. Your board config will have to - provide GPIO_USART3_RS485_DIR pin definition. Currently it cannot be - used with USART3_RXDMA. - -config USART3_RS485_DIR_POLARITY - int "USART3 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on USART3_RS485 - ---help--- - Polarity of DIR pin for RS-485 on USART3. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config USART3_RXDMA - bool "USART3 Rx DMA" - default n - depends on STM32_DMA1 - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -config USART3_TXDMA - bool "USART3 Tx DMA" - default n - depends on STM32_DMA1 - ---help--- - In high data rate usage, Tx DMA may reduce CPU load - -endif # STM32_USART3_SERIALDRIVER - -if STM32_USART3_HCIUART - -config STM32_HCIUART3_RXBUFSIZE - int "HCI UART3 Rx buffer size" - default 80 - ---help--- - Characters are buffered as they are received. This specifies - the size of the receive buffer. Ideally this should be at least - the size of the largest frame that can be received - -config STM32_HCIUART3_TXBUFSIZE - int "HCI UART3 Transmit buffer size" - default 80 - ---help--- - Characters are buffered before being sent. This specifies - the size of the transmit buffer. Ideally this should be at least - the size of the largest frame that can be sent - -config STM32_HCIUART3_BAUD - int "HCI UART3 initial BAUD rate" - default 115200 - ---help--- - The configured initial BAUD of the HCIR USART used during bringup. - In most cases this initial rate can be increased by the upper half - HCI UART driver using vendor-specifi HCI UART commands. - -config STM32_HCIUART3_RXDMA - bool "HCI UART3 Rx DMA" - default n - depends on STM32_DMA1 - select STM32_HCIUART_RXDMA - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -endif # STM32_USART3_HCIUART - -choice - prompt "UART4 Driver Configuration" - default STM32_UART4_SERIALDRIVER - depends on STM32_UART4 - -config STM32_UART4_SERIALDRIVER - bool "Standard serial driver" - select UART4_SERIALDRIVER - select ARCH_HAVE_SERIAL_TERMIOS - select STM32_SERIALDRIVER - -config STM32_UART4_1WIREDRIVER - bool "1-Wire driver" - select STM32_1WIREDRIVER - -endchoice # UART1 Driver Configuration - -if STM32_UART4_SERIALDRIVER - -config UART4_RS485 - bool "RS-485 on UART4" - default n - ---help--- - Enable RS-485 interface on UART4. Your board config will have to - provide GPIO_UART4_RS485_DIR pin definition. Currently it cannot be - used with UART4_RXDMA. - -config UART4_RS485_DIR_POLARITY - int "UART4 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on UART4_RS485 - ---help--- - Polarity of DIR pin for RS-485 on UART4. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config UART4_RXDMA - bool "UART4 Rx DMA" - default n - depends on STM32_DMA1 - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -config UART4_TXDMA - bool "UART4 Tx DMA" - default n - depends on STM32_DMA1 - ---help--- - In high data rate usage, Tx DMA may reduce CPU load - -endif # STM32_UART4_SERIALDRIVER - -choice - prompt "UART5 Driver Configuration" - default STM32_UART5_SERIALDRIVER - depends on STM32_UART5 - -config STM32_UART5_SERIALDRIVER - bool "Standard serial driver" - select UART5_SERIALDRIVER - select ARCH_HAVE_SERIAL_TERMIOS - select STM32_SERIALDRIVER - -config STM32_UART5_1WIREDRIVER - bool "1-Wire driver" - select STM32_1WIREDRIVER - -endchoice # UART5 Driver Configuration - -if STM32_UART5_SERIALDRIVER - -config UART5_RS485 - bool "RS-485 on UART5" - default n - ---help--- - Enable RS-485 interface on UART5. Your board config will have to - provide GPIO_UART5_RS485_DIR pin definition. Currently it cannot be - used with UART5_RXDMA. - -config UART5_RS485_DIR_POLARITY - int "UART5 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on UART5_RS485 - ---help--- - Polarity of DIR pin for RS-485 on UART5. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config UART5_RXDMA - bool "UART5 Rx DMA" - default n - depends on STM32_DMA1 - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -config UART5_TXDMA - bool "UART5 Tx DMA" - default n - depends on STM32_DMA1 - ---help--- - In high data rate usage, Tx DMA may reduce CPU load - -endif # STM32_UART5_SERIALDRIVER - -choice - prompt "USART6 Driver Configuration" - default STM32_USART6_SERIALDRIVER - depends on STM32_USART6 - -config STM32_USART6_SERIALDRIVER - bool "Standard serial driver" - select USART6_SERIALDRIVER - select ARCH_HAVE_SERIAL_TERMIOS - select STM32_SERIALDRIVER - -config STM32_USART6_1WIREDRIVER - bool "1-Wire driver" - select STM32_1WIREDRIVER - -config STM32_USART6_HCIUART - bool "Bluetooth HCI-UART" - select STM32_HCIUART - depends on WIRELESS_BLUETOOTH - -endchoice # USART6 Driver Configuration - -if STM32_USART6_SERIALDRIVER - -config USART6_RS485 - bool "RS-485 on USART6" - default n - ---help--- - Enable RS-485 interface on USART6. Your board config will have to - provide GPIO_USART6_RS485_DIR pin definition. Currently it cannot be - used with USART6_RXDMA. - -config USART6_RS485_DIR_POLARITY - int "USART6 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on USART6_RS485 - ---help--- - Polarity of DIR pin for RS-485 on USART6. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config USART6_RXDMA - bool "USART6 Rx DMA" - default n - depends on STM32_DMA2 - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -config USART6_TXDMA - bool "USART6 Tx DMA" - default n - depends on STM32_DMA2 - ---help--- - In high data rate usage, Tx DMA may reduce CPU load - -endif # STM32_USART6_SERIALDRIVER - -if STM32_USART6_HCIUART - -config STM32_HCIUART6_RXBUFSIZE - int "HCI UART6 Rx buffer size" - default 80 - ---help--- - Characters are buffered as they are received. This specifies - the size of the receive buffer. Ideally this should be at least - the size of the largest frame that can be received - -config STM32_HCIUART6_TXBUFSIZE - int "HCI UART6 Transmit buffer size" - default 80 - ---help--- - Characters are buffered before being sent. This specifies - the size of the transmit buffer. Ideally this should be at least - the size of the largest frame that can be sent - -config STM32_HCIUART6_BAUD - int "HCI UART6 initial BAUD rate" - default 115200 - ---help--- - The configured initial BAUD of the HCIR USART used during bringup. - In most cases this initial rate can be increased by the upper half - HCI UART driver using vendor-specifi HCI UART commands. - -config STM32_HCIUART6_RXDMA - bool "HCI UART6 Rx DMA" - default n - depends on STM32_DMA1 - select STM32_HCIUART_RXDMA - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -endif # STM32_USART6_HCIUART - -choice - prompt "UART7 Driver Configuration" - default STM32_UART7_SERIALDRIVER - depends on STM32_UART7 - -config STM32_UART7_SERIALDRIVER - bool "Standard serial driver" - select UART7_SERIALDRIVER - select ARCH_HAVE_SERIAL_TERMIOS - select STM32_SERIALDRIVER - -config STM32_UART7_1WIREDRIVER - bool "1-Wire driver" - select STM32_1WIREDRIVER - -config STM32_UART7_HCIUART - bool "Bluetooth HCI-UART" - select STM32_HCIUART - depends on WIRELESS_BLUETOOTH - -endchoice # UART7 Driver Configuration - -if STM32_UART7_SERIALDRIVER - -config UART7_RS485 - bool "RS-485 on UART7" - default n - ---help--- - Enable RS-485 interface on UART7. Your board config will have to - provide GPIO_UART7_RS485_DIR pin definition. Currently it cannot be - used with UART7_RXDMA. - -config UART7_RS485_DIR_POLARITY - int "UART7 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on UART7_RS485 - ---help--- - Polarity of DIR pin for RS-485 on UART7. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config UART7_RXDMA - bool "UART7 Rx DMA" - default n - depends on STM32_DMA1 - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -config UART7_TXDMA - bool "UART7 Tx DMA" - default n - depends on STM32_DMA1 - ---help--- - In high data rate usage, Tx DMA may reduce CPU load - -endif # STM32_UART7_SERIALDRIVER - -if STM32_UART7_HCIUART - -config STM32_HCIUART7_RXBUFSIZE - int "HCI UART7 Rx buffer size" - default 80 - ---help--- - Characters are buffered as they are received. This specifies - the size of the receive buffer. Ideally this should be at least - the size of the largest frame that can be received - -config STM32_HCIUART7_TXBUFSIZE - int "HCI UART7 Transmit buffer size" - default 80 - ---help--- - Characters are buffered before being sent. This specifies - the size of the transmit buffer. Ideally this should be at least - the size of the largest frame that can be sent - -config STM32_HCIUART7_BAUD - int "HCI UART7 initial BAUD rate" - default 115200 - ---help--- - The configured initial BAUD of the HCIR USART used during bringup. - In most cases this initial rate can be increased by the upper half - HCI UART driver using vendor-specifi HCI UART commands. - -config STM32_HCIUART7_RXDMA - bool "HCI UART7 Rx DMA" - default n - depends on STM32_DMA2 - select STM32_HCIUART_RXDMA - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -endif # STM32_UART7_HCIUART - -choice - prompt "UART8 Driver Configuration" - default STM32_UART8_SERIALDRIVER - depends on STM32_UART8 - -config STM32_UART8_SERIALDRIVER - bool "Standard serial driver" - select UART8_SERIALDRIVER - select ARCH_HAVE_SERIAL_TERMIOS - select STM32_SERIALDRIVER - -config STM32_UART8_1WIREDRIVER - bool "1-Wire driver" - select STM32_1WIREDRIVER - -config STM32_UART8_HCIUART - bool "Bluetooth HCI-UART" - select STM32_HCIUART - depends on WIRELESS_BLUETOOTH - -endchoice # UART8 Driver Configuration - -if STM32_UART8_SERIALDRIVER - -config UART8_RS485 - bool "RS-485 on UART8" - default n - ---help--- - Enable RS-485 interface on UART8. Your board config will have to - provide GPIO_UART8_RS485_DIR pin definition. Currently it cannot be - used with UART8_RXDMA. - -config UART8_RS485_DIR_POLARITY - int "UART8 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on UART8_RS485 - ---help--- - Polarity of DIR pin for RS-485 on UART8. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config UART8_RXDMA - bool "UART8 Rx DMA" - default n - depends on STM32_DMA1 - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -config UART8_TXDMA - bool "UART8 Tx DMA" - default n - depends on STM32_DMA1 - ---help--- - In high data rate usage, Tx DMA may reduce CPU load - -endif # STM32_UART8_SERIALDRIVER - -if STM32_UART8_HCIUART - -config STM32_HCIUART8_RXBUFSIZE - int "HCI UART8 Rx buffer size" - default 80 - ---help--- - Characters are buffered as they are received. This specifies - the size of the receive buffer. Ideally this should be at least - the size of the largest frame that can be received - -config STM32_HCIUART8_TXBUFSIZE - int "HCI UART8 Transmit buffer size" - default 80 - ---help--- - Characters are buffered before being sent. This specifies - the size of the transmit buffer. Ideally this should be at least - the size of the largest frame that can be sent - -config STM32_HCIUART8_BAUD - int "HCI UART8 initial BAUD rate" - default 115200 - ---help--- - The configured initial BAUD of the HCIR USART used during bringup. - In most cases this initial rate can be increased by the upper half - HCI UART driver using vendor-specifi HCI UART commands. - -config STM32_HCIUART8_RXDMA - bool "HCI UART8 Rx DMA" - default n - depends on STM32_DMA2 - select STM32_HCIUART_RXDMA - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -endif # STM32_UART8_HCIUART - -choice - prompt "LPUART1 Driver Configuration" - default STM32_LPUART1_SERIALDRIVER - depends on STM32_LPUART1 - -config STM32_LPUART1_SERIALDRIVER - bool "Standard serial driver" - select LPUART1_SERIALDRIVER - select ARCH_HAVE_SERIAL_TERMIOS - select STM32_SERIALDRIVER - -endchoice # LPUART1 Driver Configuration - -if STM32_LPUART1_SERIALDRIVER - -config LPUART1_RS485 - bool "RS-485 on LPUART1" - default n - ---help--- - Enable RS-485 interface on LPUART1. Your board config will have to - provide GPIO_LPUART1_RS485_DIR pin definition. Currently it cannot be - used with LPUART1_RXDMA. - -config LPUART1_RS485_DIR_POLARITY - int "LPUART1 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on LPUART1_RS485 - ---help--- - Polarity of DIR pin for RS-485 on LPUART1. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config LPUART1_RXDMA - bool "LPUART1 Rx DMA" - default n - depends on STM32_DMA1 - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -config LPUART1_TXDMA - bool "LPUART1 Tx DMA" - default n - depends on STM32_DMA1 - ---help--- - In high data rate usage, Tx DMA may reduce CPU load - -endif # STM32_LPUART1_SERIALDRIVER - -menu "Serial Driver Configuration" - depends on STM32_SERIALDRIVER - -config STM32_SERIAL_RXDMA_BUFFER_SIZE - int "Rx DMA buffer size" - default 32 - range 32 4096 - ---help--- - The DMA buffer size when using RX DMA to emulate a FIFO. - - When streaming data, the generic serial layer will be called - every time the FIFO receives half or this number of bytes. - - Value given here will be rounded up to next multiple of 4 bytes. - -config STM32_SERIAL_DISABLE_REORDERING - bool "Disable reordering of ttySx devices." - default n - ---help--- - NuttX per default reorders the serial ports (/dev/ttySx) so that the - console is always on /dev/ttyS0. If more than one UART is in use this - can, however, have the side-effect that all port mappings - (hardware USART1 -> /dev/ttyS0) change if the console is moved to another - UART. This is in particular relevant if a project uses the USB console - in some boards and a serial console in other boards, but does not - want the side effect of having all serial port names change when just - the console is moved from serial to USB. - -config STM32_FLOWCONTROL_BROKEN - bool "Use Software UART RTS flow control" - default n - ---help--- - Enable UART RTS flow control using Software. Because STM - Current STM32 have broken HW based RTS behavior (they assert - nRTS after every byte received) Enable this setting workaround - this issue by using software based management of RTS - -config STM32_USART_BREAKS - bool "Add TIOxSBRK to support sending Breaks" - default n - ---help--- - Add TIOCxBRK routines to send a line break per the STM32 manual, the - break will be a pulse based on the value M. This is not a BSD compatible - break. - -config STM32_SERIALBRK_BSDCOMPAT - bool "Use GPIO To send Break" - depends on STM32_USART_BREAKS - default n - ---help--- - Enable using GPIO on the TX pin to send a BSD compatible break: - TIOCSBRK will start the break and TIOCCBRK will end the break. - The current STM32 U[S]ARTS have no way to leave the break on - (TX=LOW) because software starts the break and then the hardware - automatically clears the break. This makes it difficult to send - a long break. - -config STM32_USART_SINGLEWIRE - bool "Single Wire Support" - default n - depends on STM32_USART - ---help--- - Enable single wire UART support. The option enables support for the - TIOCSSINGLEWIRE ioctl in the STM32 serial driver. - -endmenu # Serial Driver Configuration - -menu "HCI UART Driver Configuration" - depends on STM32_SERIALDRIVER - -config STM32_HCIUART_RXDMA_BUFSIZE - int "Rx DMA buffer size" - default 32 - range 32 4096 - depends on STM32_HCIUART_RXDMA - ---help--- - The DMA buffer size when using RX DMA to emulate a FIFO. - - When streaming data, the generic serial layer will be called - every time the FIFO receives half or this number of bytes. - - Value given here will be rounded up to next multiple of 4 bytes. - -config STM32_HCIUART_RXDMAPRIO - hex "HCI UART DMA priority" - default 0x00001000 if STM32_STM32F10XX - default 0x00010000 if !STM32_STM32F10XX - depends on STM32_HCIUART_RXDMA - ---help--- - Select HCI UART DMA priority. - - For STM32 F1 family, options are: 0x00000000 low, 0x00001000 medium, - 0x00002000 high, 0x00003000 very high. Default: medium. - - For other STM32's, options are: 0x00000000 low, 0x00010000 medium, - 0x00020000 high, 0x00030000 very high. Default: medium. - -config STM32_HCIUART_SW_RXFLOW - bool "Use Software UART RTS flow control" - default n - ---help--- - Enable UART RTS flow control using Software. Current STM32 have - broken HW based RTS behavior (they assert nRTS after every byte - received) Enable this setting workaround this issue by using - software based management of RTS - - If HCI UART DMA is enabled, this is probably the better selection - as well. In that case, the Rx DMA buffer will avoid Rx overrun due - to short, bursty activity. Software RTS management will probably - result in overall better throughput and should still avoid Rx data - overrun conditions. - -config STM32_HCIUART_UPPER_WATERMARK - int "RTS flow control upper watermark (%)" - default 75 - range 2 100 - depends on STM32_HCIUART_SW_RXFLOW - ---help--- - If software RTS flow control is enable, then RTS will be asserted - when this amount of Rx data has been buffered. The amount is - expressed as a percentage of the Rx buffer size. - -config STM32_HCIUART_LOWER_WATERMARK - int "RTS flow control lower watermark (%)" - default 25 - range 1 99 - depends on STM32_HCIUART_SW_RXFLOW - ---help--- - If software RTS flow control is enable, then RTS will be de-asserted - when there is less than this amount ofdata in the Rx buffere. The - amount is expressed as a percentage of the Rx buffer size. - -endmenu # HCI UART Driver Configuration - -if PM - -config STM32_PM_SERIAL_ACTIVITY - int "PM serial activity" - default 10 - ---help--- - PM activity reported to power management logic on every serial - interrupt. - -endif - -endmenu # U[S]ART Configuration - -menu "SPI Configuration" - depends on STM32_SPI - -config STM32_SPI_INTERRUPTS - bool "Interrupt driver SPI" - default n - ---help--- - Select to enable interrupt driven SPI support. Non-interrupt-driven, - poll-waiting is recommended if the interrupt rate would be to high in - the interrupt driven case. - -config STM32_SPI1_DMA - bool "SPI1 DMA" - default n - depends on STM32_SPI1 && !STM32_SPI_INTERRUPT - select STM32_SPI_DMA - ---help--- - Use DMA to improve SPI1 transfer performance. Cannot be used with STM32_SPI_INTERRUPT. - -config STM32_SPI1_DMA_BUFFER - int "SPI1 DMA buffer size" - default 0 - depends on STM32_SPI1_DMA - ---help--- - Add a properly aligned DMA buffer for RX and TX DMA for SPI1. - -config STM32_SPI_DMATHRESHOLD - int "SPI DMA threshold" - default 4 - depends on STM32_SPI_DMA - ---help--- - When SPI DMA is enabled, small DMA transfers will still be performed - by polling logic. But we need a threshold value to determine what - is small. - -config STM32_SPI2_DMA - bool "SPI2 DMA" - default n - depends on STM32_SPI2 && !STM32_SPI_INTERRUPT - select STM32_SPI_DMA - ---help--- - Use DMA to improve SPI2 transfer performance. Cannot be used with STM32_SPI_INTERRUPT. - -config STM32_SPI2_DMA_BUFFER - int "SPI2 DMA buffer size" - default 0 - depends on STM32_SPI2_DMA - ---help--- - Add a properly aligned DMA buffer for RX and TX DMA for SPI2. - -config STM32_SPI3_DMA - bool "SPI3 DMA" - default n - depends on STM32_SPI3 && !STM32_SPI_INTERRUPT - select STM32_SPI_DMA - ---help--- - Use DMA to improve SPI3 transfer performance. Cannot be used with STM32_SPI_INTERRUPT. - -config STM32_SPI3_DMA_BUFFER - int "SPI3 DMA buffer size" - default 0 - depends on STM32_SPI3_DMA - ---help--- - Add a properly aligned DMA buffer for RX and TX DMA for SPI3. - -config STM32_SPI4_DMA - bool "SPI4 DMA" - default n - depends on STM32_SPI4 && !STM32_SPI_INTERRUPT - select STM32_SPI_DMA - ---help--- - Use DMA to improve SPI4 transfer performance. Cannot be used with STM32_SPI_INTERRUPT. - -config STM32_SPI4_DMA_BUFFER - int "SPI4 DMA buffer size" - default 0 - depends on STM32_SPI4_DMA - ---help--- - Add a properly aligned DMA buffer for RX and TX DMA for SPI4. - -config STM32_SPI5_DMA - bool "SPI5 DMA" - default n - depends on STM32_SPI5 && !STM32_SPI_INTERRUPT - select STM32_SPI_DMA - ---help--- - Use DMA to improve SPI5 transfer performance. Cannot be used with STM32_SPI_INTERRUPT. - -config STM32_SPI5_DMA_BUFFER - int "SPI5 DMA buffer size" - default 0 - depends on STM32_SPI5_DMA - ---help--- - Add a properly aligned DMA buffer for RX and TX DMA for SPI5. - -config STM32_SPI6_DMA - bool "SPI6 DMA" - default n - depends on STM32_SPI6 && !STM32_SPI_INTERRUPT - select STM32_SPI_DMA - ---help--- - Use DMA to improve SPI6 transfer performance. Cannot be used with STM32_SPI_INTERRUPT. - -config STM32_SPI5_DMA_BUFFER - int "SPI5 DMA buffer size" - default 0 - depends on STM32_SPI5_DMA - ---help--- - Add a properly aligned DMA buffer for RX and TX DMA for SPI6. - -endmenu # SPI Configuration - -menu "I2S Configuration" - depends on STM32_I2S3 - -config STM32_I2S_MCK - bool "I2S_MCK" - default n - ---help--- - TBD. - -config STM32_I2S_MAXINFLIGHT - int "I2S queue size" - default 16 - ---help--- - This is the total number of transfers, both RX and TX, that can be - enqueue before the caller is required to wait. This setting - determines the number certain queue data structures that will be - pre-allocated. - -comment "I2S3 Configuration" - -config STM32_I2S3_DATALEN - int "Data width (bits)" - default 16 - ---help--- - Data width in bits. This is a default value and may be change - via the I2S interface - -#if STM32_I2S -config STM32_I2S3_RX - bool "Enable I2S receiver" - default n - ---help--- - Enable I2S receipt logic - -config STM32_I2S3_TX - bool "Enable I2S transmitter" - default n - ---help--- - Enable I2S transmission logic - -config STM32_I2S_DMADEBUG - bool "I2S DMA transfer debug" - depends on DEBUG_DMA - default n - ---help--- - Enable special debug instrumentation analyze I2S DMA data transfers. - This logic is as non-invasive as possible: It samples DMA - registers at key points in the data transfer and then dumps all of - the registers at the end of the transfer. - -config STM32_I2S_REGDEBUG - bool "SSC Register level debug" - depends on DEBUG - default n - ---help--- - Output detailed register-level SSC device debug information. - Very invasive! Requires also DEBUG. - -endmenu # I2S Configuration - -menu "I2C Configuration" - depends on STM32_I2C - -config STM32_I2C_ALT - bool "Alternate I2C implementation" - default STM32_PERFORMANCELINE - depends on !STM32_STM32F30XX - ---help--- - This selection enables an alternative I2C driver. This alternate - driver implements some rather complex workarounds for errata against - the STM32 F103 "Performance Line". This selection is an option - because: (1) It has not yet been fully verified and (2) It is not - certain that he scope of this workaround is needed only for the F103. - -config STM32_I2C_DYNTIMEO - bool "Use dynamic timeouts" - default n - depends on STM32_I2C - -config STM32_I2C_DYNTIMEO_USECPERBYTE - int "Timeout Microseconds per Byte" - default 500 - depends on STM32_I2C_DYNTIMEO - -config STM32_I2C_DYNTIMEO_STARTSTOP - int "Timeout for Start/Stop (Milliseconds)" - default 1000 - depends on STM32_I2C_DYNTIMEO - -config STM32_I2CTIMEOSEC - int "Timeout seconds" - default 0 - depends on STM32_I2C - -config STM32_I2CTIMEOMS - int "Timeout Milliseconds" - default 500 - depends on STM32_I2C && !STM32_I2C_DYNTIMEO - -config STM32_I2CTIMEOTICKS - int "Timeout for Done and Stop (ticks)" - default 500 - depends on STM32_I2C && !STM32_I2C_DYNTIMEO - -config STM32_I2C_DUTY16_9 - bool "Frequency with Tlow/Thigh = 16/9" - default n - depends on STM32_I2C - -config STM32_I2C_DMA - bool "I2C DMA Support" - default n - depends on STM32_I2C && STM32_STM32F4XXX && STM32_DMA1 && !I2C_POLLED - ---help--- - This option enables the DMA for I2C transfers. - Note: The user can define CONFIG_I2C_DMAPRIO: a custom priority value for the - I2C dma streams, else the default priority level is set to medium. - -endmenu - -menu "I2C Slave Configuration" - depends on STM32_I2C_SLAVE - -config STM32_I2C_SLAVE_DEFAULT_TX - hex "Default TX byte to be sent when the TX buffer is empty" - default 0xFF - -config STM32_I2C_SLAVE_USEWQ - bool "Use work queue to delegate the isr completion status" - default n - ---help--- - With the current upperhalf I2C slave driver implementation, the user - should delegate the callback completion status using a work queue. - However, work queues introduce a delay, so in certain scenarios - it is better to use a custom driver without using a work queue. - -config STM32_I2C_SLAVE_RETRANSFER - bool "The frame is retransferred when stop is issued beforehand" - default n - ---help--- - If stop is issued before the whole frame is transferred, - the tx pointer is reset to 0. - -endmenu - -menu "SDIO Configuration" - depends on STM32_SDIO - -config STM32_SDIO_CARD - bool "SDIO Card support" - default n - ---help--- - Build in additional support needed only for SDIO cards (vs. SD - memory cards) - -config STM32_SDIO_PULLUP - bool "Enable internal Pull-Ups" - default n - ---help--- - If you are using an external SDCard module that does not have the - pull-up resistors for the SDIO interface (like the Gadgeteer SD Card - Module) then enable this option to activate the internal pull-up - resistors. - -config STM32_SDIO_DMA - bool "Support DMA data transfers" - default STM32_DMA2 - select SDIO_DMA - depends on STM32_DMA2 - ---help--- - Support DMA data transfers. Requires STM32_SDIO and config STM32_DMA2. - -config STM32_SDIO_DMAPRIO - hex "SDIO DMA priority" - default 0x00001000 if STM32_STM32F10XX - default 0x00010000 if !STM32_STM32F10XX - ---help--- - Select SDIO DMA priority. - - For STM32 F1 family, options are: 0x00000000 low, 0x00001000 medium, - 0x00002000 high, 0x00003000 very high. Default: medium. - - For other STM32's, options are: 0x00000000 low, 0x00010000 medium, - 0x00020000 high, 0x00030000 very high. Default: medium. - -config STM32_SDIO_WIDTH_D1_ONLY - bool "Use D1 only" - default n - ---help--- - Select 1-bit transfer mode. Default: 4-bit transfer mode. - -endmenu - -if STM32_BKPSRAM - -config STM32_BBSRAM - bool "BBSRAM File Support" - default n - -config STM32_BBSRAM_FILES - int "Max Files to support in BBSRAM" - default 4 - -config STM32_SAVE_CRASHDUMP - bool "Enable Saving Panic to BBSRAM" - default n - -endif # STM32_BKPSRAM - -config STM32_HAVE_RTC_COUNTER - bool - default n - -config STM32_HAVE_RTC_SUBSECONDS - bool - select ARCH_HAVE_RTC_SUBSECONDS - default n - -menu "RTC Configuration" - depends on STM32_RTC - -config STM32_RTC_MAGIC_REG - int "BKP register" - default 0 - range 0 19 - depends on !STM32_HAVE_RTC_COUNTER - ---help--- - The BKP register used to store/check the Magic value to determine if - RTC is already setup - -config STM32_RTC_MAGIC - hex "RTC Magic 1" - default 0xfacefeed - depends on !STM32_HAVE_RTC_COUNTER - ---help--- - Value used as Magic to determine if the RTC is already setup - -config STM32_RTC_MAGIC_TIME_SET - hex "RTC Magic 2" - default 0xf00dface - depends on !STM32_HAVE_RTC_COUNTER - ---help--- - Value used as Magic to determine if the RTC has been setup and has - time set - -choice - prompt "RTC clock source" - default STM32_RTC_LSECLOCK - -config STM32_RTC_LSECLOCK - bool "LSE clock" - ---help--- - Drive the RTC with the LSE clock - -config STM32_RTC_LSICLOCK - bool "LSI clock" - ---help--- - Drive the RTC with the LSI clock - -config STM32_RTC_HSECLOCK - bool "HSE clock" - ---help--- - Drive the RTC with the HSE clock, divided down to 1MHz. - -endchoice # RTC clock source -endmenu # RTC configuration - -menu "Ethernet MAC configuration" - depends on STM32_ETHMAC - -config STM32_PHYADDR - int "PHY address" - default 1 - ---help--- - The 5-bit address of the PHY on the board. Default: 1 - -config STM32_PHYINIT - bool "Board-specific PHY Initialization" - default n - ---help--- - Some boards require specialized initialization of the PHY before it can be used. - This may include such things as configuring GPIOs, resetting the PHY, etc. If - STM32_PHYINIT is defined in the configuration then the board specific logic must - provide stm32_phyinitialize(); The STM32 Ethernet driver will call this function - one time before it first uses the PHY. - -config STM32_MII - bool "Use MII interface" - default n - ---help--- - Support Ethernet MII interface. - -choice - prompt "MII clock configuration" - default STM32_MII_MCO if STM32_STM32F10XX - default STM32_MII_MCO1 if STM32_STM32F20XX || STM32_STM32F4XXX - depends on STM32_MII - -config STM32_MII_MCO - bool "Use MC0 as MII clock" - depends on STM32_STM32F10XX - ---help--- - Use MCO to clock the MII interface. Default: Use MC0 - -config STM32_MII_MCO1 - bool "Use MC01 as MII clock" - depends on (STM32_STM32F20XX || STM32_STM32F4XXX) - ---help--- - Use MCO1 to clock the MII interface. Default: Use MC01 - -config STM32_MII_MCO2 - bool "Use MC02 as MII clock" - depends on (STM32_STM32F20XX || STM32_STM32F4XXX) - ---help--- - Use MCO2 to clock the MII interface. Default: Use MC01 - -config STM32_MII_EXTCLK - bool "External MII clock" - ---help--- - Clocking is provided by external logic. Don't use MCO for MII - clock. Default: Use MC0[1] - -endchoice - -config STM32_AUTONEG - bool "Use autonegotiation" - default y - ---help--- - Use PHY autonegotiation to determine speed and mode - -config STM32_ETHFD - bool "Full duplex" - default n - depends on !STM32_AUTONEG - ---help--- - If STM32_AUTONEG is not defined, then this may be defined to select full duplex - mode. Default: half-duplex - -config STM32_ETH100MBPS - bool "100 Mbps" - default n - depends on !STM32_AUTONEG - ---help--- - If STM32_AUTONEG is not defined, then this may be defined to select 100 MBps - speed. Default: 10 Mbps - -config STM32_PHYSR - int "PHY Status Register Address (decimal)" - depends on STM32_AUTONEG - ---help--- - This must be provided if STM32_AUTONEG is defined. The PHY status register - address may diff from PHY to PHY. This configuration sets the address of - the PHY status register. - -config STM32_PHYSR_ALTCONFIG - bool "PHY Status Alternate Bit Layout" - default n - depends on STM32_AUTONEG - ---help--- - Different PHYs present speed and mode information in different ways. Some - will present separate information for speed and mode (this is the default). - Those PHYs, for example, may provide a 10/100 Mbps indication and a separate - full/half duplex indication. This options selects an alternative representation - where speed and mode information are combined. This might mean, for example, - separate bits for 10HD, 100HD, 10FD and 100FD. - -config STM32_PHYSR_SPEED - hex "PHY Speed Mask" - depends on STM32_AUTONEG && !STM32_PHYSR_ALTCONFIG - ---help--- - This must be provided if STM32_AUTONEG is defined. This provides bit mask - for isolating the 10 or 100MBps speed indication. - -config STM32_PHYSR_100MBPS - hex "PHY 100Mbps Speed Value" - depends on STM32_AUTONEG && !STM32_PHYSR_ALTCONFIG - ---help--- - This must be provided if STM32_AUTONEG is defined. This provides the value - of the speed bit(s) indicating 100MBps speed. - -config STM32_PHYSR_MODE - hex "PHY Mode Mask" - depends on STM32_AUTONEG && !STM32_PHYSR_ALTCONFIG - ---help--- - This must be provided if STM32_AUTONEG is defined. This provide bit mask - for isolating the full or half duplex mode bits. - -config STM32_PHYSR_FULLDUPLEX - hex "PHY Full Duplex Mode Value" - depends on STM32_AUTONEG && !STM32_PHYSR_ALTCONFIG - ---help--- - This must be provided if STM32_AUTONEG is defined. This provides the - value of the mode bits indicating full duplex mode. - -config STM32_PHYSR_ALTMODE - hex "PHY Mode Mask" - depends on STM32_AUTONEG && STM32_PHYSR_ALTCONFIG - ---help--- - This must be provided if STM32_AUTONEG is defined. This provide bit mask - for isolating the speed and full/half duplex mode bits. - -config STM32_PHYSR_10HD - hex "10MBase-T Half Duplex Value" - depends on STM32_AUTONEG && STM32_PHYSR_ALTCONFIG - ---help--- - This must be provided if STM32_AUTONEG is defined. This is the value - under the bit mask that represents the 10Mbps, half duplex setting. - -config STM32_PHYSR_100HD - hex "100Base-T Half Duplex Value" - depends on STM32_AUTONEG && STM32_PHYSR_ALTCONFIG - ---help--- - This must be provided if STM32_AUTONEG is defined. This is the value - under the bit mask that represents the 100Mbps, half duplex setting. - -config STM32_PHYSR_10FD - hex "10Base-T Full Duplex Value" - depends on STM32_AUTONEG && STM32_PHYSR_ALTCONFIG - ---help--- - This must be provided if STM32_AUTONEG is defined. This is the value - under the bit mask that represents the 10Mbps, full duplex setting. - -config STM32_PHYSR_100FD - hex "100Base-T Full Duplex Value" - depends on STM32_AUTONEG && STM32_PHYSR_ALTCONFIG - ---help--- - This must be provided if STM32_AUTONEG is defined. This is the value - under the bit mask that represents the 100Mbps, full duplex setting. - -config STM32_ETH_ENHANCEDDESC - bool "Enable enhanced RX/TX descriptors" - default n - ---help--- - Enables double-length DMA descriptors that have space for packet - timestamps and checksum offloading. - -config STM32_ETH_PTP - bool "Precision Time Protocol (PTP)" - default n - ---help--- - Enables Precision Time Protocol (PTP) hardware timer. - -config STM32_ETH_PTP_GPIO - bool "PTP pulse-per-second output signal" - depends on STM32_ETH_PTP - default n - ---help--- - Enables pulse-per-second output on GPIO pin. - -config STM32_ETH_PTP_RTC_HIRES - bool "Use PTP timer as system high-resolution RTC" - depends on STM32_ETH_PTP - default n - ---help--- - Uses the Ethernet peripheral PTP timer as the CONFIG_RTC_HIRES source. - This provides high resolution timestamps to clock_gettime(). - Note that PTP timer is disabled when Ethernet interface is down or - being reset. During this time g_rtc_enabled is set to false and system - uses the lower resolution system tick counter. - -config STM32_ETH_TIMESTAMP_RX - bool "Hardware timestamping of received packets" - depends on STM32_ETH_PTP && NET_TIMESTAMP && STM32_ETH_ENHANCEDDESC - select ARCH_HAVE_NETDEV_TIMESTAMP - default n - ---help--- - Timestamp all received Ethernet packets. - Timestamp is available to application through SO_TIMESTAMP socket option. - -config STM32_RMII - bool - default !STM32_MII - -choice - prompt "RMII clock configuration" - default STM32_RMII_MCO if STM32_STM32F10XX - default STM32_RMII_MCO1 if STM32_STM32F20XX || STM32_STM32F4XXX - depends on STM32_RMII - -config STM32_RMII_MCO - bool "Use MC0 as RMII clock" - depends on STM32_STM32F10XX - ---help--- - Use MCO to clock the RMII interface. Default: Use MC0 - -config STM32_RMII_MCO1 - bool "Use MC01 as RMII clock" - depends on (STM32_STM32F20XX || STM32_STM32F4XXX) - ---help--- - Use MCO1 to clock the RMII interface. Default: Use MC01 - -config STM32_RMII_MCO2 - bool "Use MC02 as RMII clock" - depends on (STM32_STM32F20XX || STM32_STM32F4XXX) - ---help--- - Use MCO2 to clock the RMII interface. Default: Use MC01 - -config STM32_RMII_EXTCLK - bool "External RMII clock" - ---help--- - Clocking is provided by external logic. Don't use MCO for RMII - clock. Default: Use MC0[1] - -endchoice - -config STM32_ETHMAC_REGDEBUG - bool "Register-Level Debug" - default n - depends on DEBUG_NET_INFO - ---help--- - Enable very low-level register access debug. Depends on CONFIG_DEBUG_FEATURES. - -endmenu # Ethernet MAC configuration - -config STM32_USBHOST - bool "Enable USB Host Support" - depends on STM32_OTGFS || STM32_OTGHS - default n - select USBHOST - -menu "USB FS Host Configuration" - depends on STM32_OTGFS && STM32_USBHOST - -config STM32_OTGFS_RXFIFO_SIZE - int "Rx Packet Size" - default 128 - ---help--- - Size of the RX FIFO in 32-bit words. Default 128 (512 bytes) - -config STM32_OTGFS_NPTXFIFO_SIZE - int "Non-periodic Tx FIFO Size" - default 96 - ---help--- - Size of the non-periodic Tx FIFO in 32-bit words. Default 96 (384 bytes) - -config STM32_OTGFS_PTXFIFO_SIZE - int "Periodic Tx FIFO size" - default 128 - ---help--- - Size of the periodic Tx FIFO in 32-bit words. Default 96 (384 bytes) - -config STM32_OTGFS_DESCSIZE - int "Descriptor Size" - default 128 - ---help--- - Maximum size to allocate for descriptor memory descriptor. Default: 128 - -config STM32_OTGFS_SOFINTR - bool "Enable SOF interrupts" - default n - ---help--- - Enable SOF interrupts. Why would you ever want to do that? - -config STM32_OTGFS_VBUS_CONTROL - bool "Enable VBus Control" - default y - ---help--- - Enable VBus control. Used when the board has VBus sensing and - a power switch for the OTG FS USB port. Disable this config - if the board lacks this USB VBus control circuitry. - -endmenu - -menu "USB HS Host Configuration" - depends on STM32_OTGHS && STM32_USBHOST - -config STM32_OTGHS_RXFIFO_SIZE - int "Rx Packet Size" - default 128 - ---help--- - Size of the RX FIFO in 32-bit words. Default 128 (512 bytes) - -config STM32_OTGHS_NPTXFIFO_SIZE - int "Non-periodic Tx FIFO Size" - default 96 - ---help--- - Size of the non-periodic Tx FIFO in 32-bit words. Default 96 (384 bytes) - -config STM32_OTGHS_PTXFIFO_SIZE - int "Periodic Tx FIFO size" - default 128 - ---help--- - Size of the periodic Tx FIFO in 32-bit words. Default 96 (384 bytes) - -config STM32_OTGHS_DESCSIZE - int "Descriptor Size" - default 128 - ---help--- - Maximum size to allocate for descriptor memory descriptor. Default: 128 - -config STM32_OTGHS_SOFINTR - bool "Enable SOF interrupts" - default n - ---help--- - Enable SOF interrupts. Why would you ever want to do that? - -config STM32_OTGHS_VBUS_CONTROL - bool "Enable VBus Control" - default y - ---help--- - Enable VBus control. Used when the board has VBus sensing and - a power switch for the OTG HS USB port. Disable this config - if the board lacks this USB VBus control circuitry. - -endmenu - -menu "USB Host Debug Configuration" - depends on STM32_USBHOST - -config STM32_USBHOST_REGDEBUG - bool "Register-Level Debug" - default n - depends on STM32_USBHOST && DEBUG_USB_INFO - ---help--- - Enable very low-level register access debug. - -config STM32_USBHOST_PKTDUMP - bool "Packet Dump Debug" - default n - depends on STM32_USBHOST && DEBUG_USB_INFO - ---help--- - Dump all incoming and outgoing USB packets. - -endmenu - -comment "USB Device Configuration" - -menu "USB Full Speed Debug Configuration" - depends on STM32_USBFS - -config STM32_USBFS_REGDEBUG - bool "Register-Level Debug" - default n - depends on STM32_USBFS && DEBUG_USB_INFO - ---help--- - Enable very low-level register access debug. - -endmenu - -menu "OTG Configuration" - depends on STM32_OTGFS - -config OTG_ID_GPIO_DISABLE - bool "Disable the use of GPIO_OTG_ID pin." - default n - ---help--- - Disables/Enables the use of GPIO_OTG_ID pin. This allows non OTG use - cases to reuse this GPIO pin and ensure it is not set incorrectlty - during OS boot. - -endmenu - -config STM32_USB_ITRMP - bool "Re-map USB interrupt" - default STM32_CAN1 - depends on STM32_USB && STM32_STM32F30XX - ---help--- - The legacy USB in the F1 series shared interrupt lines with USB - device and CAN1. In the F3 series, a hardware options was added to - either retain the legacy F1 behavior or to map the USB interrupts to - their own dedicated vectors. The option is available only for the - F3 family and selects the use of the dedicated USB interrupts. - -menu "CAN driver configuration" - depends on STM32_CAN - -choice - prompt "CAN character driver or SocketCAN support" - default STM32_CAN_CHARDRIVER - -config STM32_CAN_CHARDRIVER - bool "STM32 CAN character driver support" - select ARCH_HAVE_CAN_ERRORS - select CAN - -config STM32_CAN_SOCKET - bool "STM32 CAN SocketCAN support" - select NET_CAN_HAVE_ERRORS - -endchoice # CAN character driver or SocketCAN support - -config STM32_CAN1_BAUD - int "CAN1 BAUD" - default 250000 - depends on STM32_CAN1 - ---help--- - CAN1 BAUD rate. Required if CONFIG_STM32_CAN1 is defined. - -config STM32_CAN2_BAUD - int "CAN2 BAUD" - default 250000 - depends on STM32_CAN2 - ---help--- - CAN2 BAUD rate. Required if CONFIG_STM32_CAN2 is defined. - -config STM32_CAN_TSEG1 - int "TSEG1 quanta" - default 6 - ---help--- - The number of CAN time quanta in segment 1. Default: 6 - -config STM32_CAN_TSEG2 - int "TSEG2 quanta" - default 7 - ---help--- - The number of CAN time quanta in segment 2. Default: 7 - -config STM32_CAN_REGDEBUG - bool "CAN Register level debug" - depends on DEBUG_CAN_INFO - default n - ---help--- - Output detailed register-level CAN device debug information. - Requires also CONFIG_DEBUG_CAN_INFO. - -endmenu # "CAN driver configuration" - -menu "FDCAN driver configuration" - depends on STM32_FDCAN - -choice - prompt "FDCAN character driver or SocketCAN support" - default STM32_FDCAN_CHARDRIVER - -config STM32_FDCAN_CHARDRIVER - bool "STM32 FDCAN character driver support" - select ARCH_HAVE_CAN_ERRORS - select CAN - -config STM32_FDCAN_SOCKET - bool "STM32 FDCAN SocketCAN support" - select NET_CAN_HAVE_ERRORS - select NET_CAN_HAVE_CANFD - -endchoice # FDCAN character driver or SocketCAN support - -config STM32_FDCAN_REGDEBUG - bool "CAN Register level debug" - depends on DEBUG_CAN_INFO - default n - ---help--- - Output detailed register-level CAN device debug information. - Requires also CONFIG_DEBUG_CAN_INFO. - -config STM32_FDCAN_QUEUE_MODE - bool "FDCAN QUEUE mode (vs FIFO mode)" - default n - -menu "FDCAN1 device driver options" - depends on STM32_FDCAN1 - -choice - prompt "FDCAN1 frame format" - default STM32_FDCAN1_ISO11898_1 - -config STM32_FDCAN1_ISO11898_1 - bool "ISO11898-1" - ---help--- - Enable ISO11898-1 frame format - -config STM32_FDCAN1_NONISO_FORMAT - bool "Non ISO" - ---help--- - Enable Non ISO, Bosch CAN FD Specification V1.0 - -endchoice # FDCAN1 frame format - -choice - prompt "FDCAN1 mode" - default STM32_FDCAN1_CLASSIC - -config STM32_FDCAN1_CLASSIC - bool "Classic CAN" - ---help--- - Enable Classic CAN mode - -config STM32_FDCAN1_FD - bool "CAN FD" - depends on CAN_FD || NET_CAN_CANFD - ---help--- - Enable CAN FD mode - -config STM32_FDCAN1_FD_BRS - bool "CAN FD with fast bit rate switching" - depends on CAN_FD || NET_CAN_CANFD - ---help--- - Enable CAN FD mode with fast bit rate switching mode. - -endchoice # FDCAN1 mode - -config STM32_FDCAN1_LOOPBACK - bool "Enable FDCAN1 loopback mode" - default n - ---help--- - Enable the FDCAN1 local loopback mode for testing purposes. - -comment "Nominal Bit Timing" - -config STM32_FDCAN1_BITRATE - int "FDCAN bitrate" - default 500000 - range 0 1000000 - ---help--- - FDCAN1 bitrate in bits per second. Required if STM32_FDCAN1 is defined. - -config STM32_FDCAN1_NTSEG1 - int "FDCAN1 NTSEG1 (PropSeg + PhaseSeg1)" - default 6 - range 1 256 if STM32_STM32G4XXX - ---help--- - The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). - -config STM32_FDCAN1_NTSEG2 - int "FDCAN1 NTSEG2 (PhaseSeg2)" - default 7 - range 1 128 if STM32_STM32G4XXX - ---help--- - The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). - -config STM32_FDCAN1_NSJW - int "FDCAN1 synchronization jump width" - default 1 - range 1 128 if STM32_STM32G4XXX - ---help--- - The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). - -comment "Data Bit Timing" - depends on CAN_FD && STM32_FDCAN1_FD_BRS - -config STM32_FDCAN1_DBITRATE - int "FDCAN1 data bitrate" - default 2000000 - depends on CAN_FD && STM32_FDCAN1_FD_BRS - ---help--- - FDCAN1 bitrate in bits per second. Required if operating in FD mode with bit rate switching (BRS). - -config STM32_FDCAN1_DTSEG1 - int "FDCAN1 DTSEG1 (PropSeg + PhaseSeg1 of data phase)" - default 4 - range 1 31 if STM32_STM32G4XXX - depends on CAN_FD && STM32_FDCAN1_FD_BRS - ---help--- - The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). - -config STM32_FDCAN1_DTSEG2 - int "FDCAN1 DTSEG2 (PhaseSeg2 of data phase)" - default 4 - range 1 15 if STM32_STM32G4XXX - depends on CAN_FD && STM32_FDCAN1_FD_BRS - ---help--- - The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). - -config STM32_FDCAN1_DSJW - int "FDCAN1 fast synchronization jump width" - default 2 - range 1 15 if STM32_STM32G4XXX - depends on CAN_FD && STM32_FDCAN1_FD_BRS - ---help--- - The duration of a synchronization jump is Tcan_clk x DSJW. - -endmenu # FDCAN1 device driver options - -menu "FDCAN2 device driver options" - depends on STM32_FDCAN2 - -choice - prompt "FDCAN2 frame format" - default STM32_FDCAN2_ISO11898_1 - -config STM32_FDCAN2_ISO11898_1 - bool "ISO11898-1" - ---help--- - Enable ISO11898-1 frame format - -config STM32_FDCAN2_NONISO_FORMAT - bool "Non ISO" - ---help--- - Enable Non ISO, Bosch CAN FD Specification V1.0 - -endchoice # FDCAN2 frame format - -choice - prompt "FDCAN2 mode" - default STM32_FDCAN2_CLASSIC - -config STM32_FDCAN2_CLASSIC - bool "Classic CAN" - ---help--- - Enable Classic CAN mode - -config STM32_FDCAN2_FD - bool "CAN FD" - depends on CAN_FD || NET_CAN_CANFD - ---help--- - Enable CAN FD mode - -config STM32_FDCAN2_FD_BRS - bool "CAN FD with fast bit rate switching" - depends on CAN_FD || NET_CAN_CANFD - ---help--- - Enable CAN FD mode with fast bit rate switching mode. - -endchoice # FDCAN2 mode - -config STM32_FDCAN2_LOOPBACK - bool "Enable FDCAN2 loopback mode" - default n - ---help--- - Enable the FDCAN2 local loopback mode for testing purposes. - -comment "Nominal Bit Timing" - -config STM32_FDCAN2_BITRATE - int "FDCAN bitrate" - default 500000 - range 0 1000000 - ---help--- - FDCAN2 bitrate in bits per second. Required if STM32_FDCAN2 is defined. - -config STM32_FDCAN2_NTSEG1 - int "FDCAN2 NTSEG1 (PropSeg + PhaseSeg1)" - default 6 - range 1 256 if STM32_STM32G4XXX - ---help--- - The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). - -config STM32_FDCAN2_NTSEG2 - int "FDCAN2 NTSEG2 (PhaseSeg2)" - default 7 - range 1 128 if STM32_STM32G4XXX - ---help--- - The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). - -config STM32_FDCAN2_NSJW - int "FDCAN2 synchronization jump width" - default 1 - range 1 128 if STM32_STM32G4XXX - ---help--- - The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). - -comment "Data Bit Timing" - depends on CAN_FD && STM32_FDCAN2_FD_BRS - -config STM32_FDCAN2_DBITRATE - int "FDCAN2 data bitrate" - default 2000000 - depends on CAN_FD && STM32_FDCAN2_FD_BRS - ---help--- - FDCAN2 bitrate in bits per second. Required if operating in FD mode with bit rate switching (BRS). - -config STM32_FDCAN2_DTSEG1 - int "FDCAN2 DTSEG1 (PropSeg + PhaseSeg1 of data phase)" - default 4 - range 1 31 if STM32_STM32G4XXX - depends on CAN_FD && STM32_FDCAN2_FD_BRS - ---help--- - The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). - -config STM32_FDCAN2_DTSEG2 - int "FDCAN2 DTSEG2 (PhaseSeg2 of data phase)" - default 4 - range 1 15 if STM32_STM32G4XXX - depends on CAN_FD && STM32_FDCAN2_FD_BRS - ---help--- - The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). - -config STM32_FDCAN2_DSJW - int "FDCAN2 fast synchronization jump width" - default 2 - range 1 15 if STM32_STM32G4XXX - depends on CAN_FD && STM32_FDCAN2_FD_BRS - ---help--- - The duration of a synchronization jump is Tcan_clk x DSJW. - -endmenu # FDCAN2 device driver options - -menu "FDCAN3 device driver options" - depends on STM32_FDCAN3 - -choice - prompt "FDCAN3 frame format" - default STM32_FDCAN3_ISO11898_1 - -config STM32_FDCAN3_ISO11898_1 - bool "ISO11898-1" - ---help--- - Enable ISO11898-1 frame format - -config STM32_FDCAN3_NONISO_FORMAT - bool "Non ISO" - ---help--- - Enable Non ISO, Bosch CAN FD Specification V1.0 - -endchoice # FDCAN3 frame format - -choice - prompt "FDCAN3 mode" - default STM32_FDCAN3_CLASSIC - -config STM32_FDCAN3_CLASSIC - bool "Classic CAN" - ---help--- - Enable Classic CAN mode - -config STM32_FDCAN3_FD - bool "CAN FD" - depends on CAN_FD || NET_CAN_CANFD - ---help--- - Enable CAN FD mode - -config STM32_FDCAN3_FD_BRS - bool "CAN FD with fast bit rate switching" - depends on CAN_FD || NET_CAN_CANFD - ---help--- - Enable CAN FD mode with fast bit rate switching mode. - -endchoice # FDCAN3 mode - -config STM32_FDCAN3_LOOPBACK - bool "Enable FDCAN3 loopback mode" - default n - ---help--- - Enable the FDCAN3 local loopback mode for testing purposes. - -comment "Nominal Bit Timing" - -config STM32_FDCAN3_BITRATE - int "FDCAN bitrate" - default 500000 - range 0 1000000 - ---help--- - FDCAN3 bitrate in bits per second. Required if STM32_FDCAN3 is defined. - -config STM32_FDCAN3_NTSEG1 - int "FDCAN3 NTSEG1 (PropSeg + PhaseSeg1)" - default 6 - range 1 256 if STM32_STM32G4XXX - ---help--- - The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). - -config STM32_FDCAN3_NTSEG2 - int "FDCAN3 NTSEG2 (PhaseSeg2)" - default 7 - range 1 128 if STM32_STM32G4XXX - ---help--- - The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). - -config STM32_FDCAN3_NSJW - int "FDCAN3 synchronization jump width" - default 1 - range 1 128 if STM32_STM32G4XXX - ---help--- - The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). - -comment "Data Bit Timing" - depends on CAN_FD && STM32_FDCAN3_FD_BRS - -config STM32_FDCAN3_DBITRATE - int "FDCAN3 data bitrate" - default 2000000 - depends on CAN_FD && STM32_FDCAN3_FD_BRS - ---help--- - FDCAN3 bitrate in bits per second. Required if operating in FD mode with bit rate switching (BRS). - -config STM32_FDCAN3_DTSEG1 - int "FDCAN3 DTSEG1 (PropSeg + PhaseSeg1 of data phase)" - default 4 - range 1 31 if STM32_STM32G4XXX - depends on CAN_FD && STM32_FDCAN3_FD_BRS - ---help--- - The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). - -config STM32_FDCAN3_DTSEG2 - int "FDCAN3 DTSEG2 (PhaseSeg2 of data phase)" - default 4 - range 1 15 if STM32_STM32G4XXX - depends on CAN_FD && STM32_FDCAN3_FD_BRS - ---help--- - The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). - -config STM32_FDCAN3_DSJW - int "FDCAN3 fast synchronization jump width" - default 2 - range 1 15 if STM32_STM32G4XXX - depends on CAN_FD && STM32_FDCAN3_FD_BRS - ---help--- - The duration of a synchronization jump is Tcan_clk x DSJW. - -endmenu # FDCAN3 device driver options - -endmenu # "FDCAN driver configuration" - -if STM32_LTDC - -menu "LTDC Configuration" - -config STM32_LTDC_BACKLIGHT - bool "Backlight support" - default y - -config STM32_LTDC_DEFBACKLIGHT - hex "Default backlight level" - default 0xf0 - -config STM32_LTDC_BACKCOLOR - hex "Background color" - default 0x0 - ---help--- - This is the background color that will be used as the LTDC - background layer color. It is an RGB888 format value. - -config STM32_LTDC_DITHER - bool "Dither support" - default n - -config STM32_LTDC_DITHER_RED - depends on STM32_LTDC_DITHER - int "Dither red width" - range 0 7 - default 2 - ---help--- - This is the dither red width. - -config STM32_LTDC_DITHER_GREEN - depends on STM32_LTDC_DITHER - int "Dither green width" - range 0 7 - default 2 - ---help--- - This is the dither green width. - -config STM32_LTDC_DITHER_BLUE - depends on STM32_LTDC_DITHER - int "Dither blue width" - range 0 7 - default 2 - ---help--- - This is the dither blue width. - -config STM32_LTDC_FB_BASE - hex "Framebuffer memory start address" - default 0 - ---help--- - If you are using the LTDC, then you must provide the address - of the start of the framebuffer. This address will typically - be in the SRAM or SDRAM memory region of the FSMC/FMC. - -config STM32_LTDC_FB_SIZE - int "Framebuffer memory size (bytes)" - default 0 - ---help--- - Must be the whole size of the active LTDC layer. - -config STM32_LTDC_L1_CHROMAKEYEN - bool "Enable chromakey support for layer 1" - default y - -config STM32_LTDC_L1_CHROMAKEY - hex "Layer L1 initial chroma key" - default 0x00000000 - -config STM32_LTDC_L1_COLOR - hex "Layer L1 default color" - default 0x00000000 - -choice - prompt "Layer 1 color format" - default STM32_LTDC_L1_RGB565 - -config STM32_LTDC_L1_L8 - bool "8 bpp L8 (8-bit CLUT)" - depends on STM32_FB_CMAP - -config STM32_LTDC_L1_AL44 - bool "8 bpp AL44 (4-bit alpha + 4-bit CLUT)" - depends on STM32_FB_CMAP - -config STM32_LTDC_L1_AL88 - bool "16 bpp AL88 (8-bit alpha + 8-bit CLUT)" - depends on STM32_FB_CMAP - -config STM32_LTDC_L1_RGB565 - bool "16 bpp RGB 565" - depends on !STM32_FB_CMAP - -config STM32_LTDC_L1_ARGB4444 - bool "16 bpp ARGB 4444" - depends on !STM32_FB_CMAP - -config STM32_LTDC_L1_ARGB1555 - bool "16 bpp ARGB 1555" - depends on !STM32_FB_CMAP - -config STM32_LTDC_L1_RGB888 - bool "24 bpp RGB 888" - depends on !STM32_FB_CMAP - -config STM32_LTDC_L1_ARGB8888 - bool "32 bpp ARGB 8888" - depends on !STM32_FB_CMAP - -endchoice # Layer 1 color format - -config STM32_LTDC_L2 - bool "Enable Layer 2 support" - default y - -if STM32_LTDC_L2 - -config STM32_LTDC_L2_COLOR - hex "Layer L2 default color" - default 0x00000000 - -config STM32_LTDC_L2_CHROMAKEYEN - bool "Enable chromakey support for layer 2" - default y - -config STM32_LTDC_L2_CHROMAKEY - hex "Layer L2 initial chroma key" - default 0x00000000 - -choice - prompt "Layer 2 (top layer) color format" - default STM32_LTDC_L2_RGB565 - -config STM32_LTDC_L2_L8 - depends on STM32_LTDC_L1_L8 - bool "8 bpp L8 (8-bit CLUT)" - -config STM32_LTDC_L2_AL44 - depends on STM32_LTDC_L1_AL44 - bool "8 bpp AL44 (4-bit alpha + 4-bit CLUT)" - -config STM32_LTDC_L2_AL88 - depends on STM32_LTDC_L1_AL88 - bool "16 bpp AL88 (8-bit alpha + 8-bit CLUT)" - -config STM32_LTDC_L2_RGB565 - depends on STM32_LTDC_L1_RGB565 - bool "16 bpp RGB 565" - -config STM32_LTDC_L2_ARGB4444 - depends on STM32_LTDC_L1_ARGB4444 - bool "16 bpp ARGB 4444" - -config STM32_LTDC_L2_ARGB1555 - depends on STM32_LTDC_L1_ARGB1555 - bool "16 bpp ARGB 1555" - -config STM32_LTDC_L2_RGB888 - depends on STM32_LTDC_L1_RGB888 - bool "24 bpp RGB 888" - -config STM32_LTDC_L2_ARGB8888 - depends on STM32_LTDC_L1_ARGB8888 - bool "32 bpp ARGB 8888" - -endchoice # Layer 2 color format - -endif # STM32_LTDC_L2 - -config STM32_FB_CMAP - bool "Color map support" - default y - select FB_CMAP - ---help--- - Enabling color map support is necessary for LTDC L8 format. - -config STM32_FB_TRANSPARENCY - bool "Transparency color map support" - default y - depends on STM32_FB_CMAP - select FB_TRANSPARENCY - ---help--- - Enabling transparency color map support is necessary for LTDC L8 format. - -config STM32_LTDC_REGDEBUG - bool "LTDC Register level debug" - depends on DEBUG_INFO && DEBUG_LCD - default n - ---help--- - Output detailed register-level LTDC device debug information. -endmenu - -endif # STM32_LTDC - -if STM32_DMA2D - -menu "DMA2D Configuration" - -config STM32_DMA2D_NLAYERS - int "Number DMA2D overlays" - default 1 - range 1 256 - ---help--- - Number of supported DMA2D layer. - -config STM32_DMA2D_LAYER_SHARED - bool "Overlays shared memory region" - default n - ---help--- - Several overlays can share the same memory region. - Setup a whole memory area (usually multiple size of the visible screen) - allows image preprocessing before they become visible by blit operation. - -config STM32_DMA2D_LAYER_PPLINE - int "Pixel per line" - default 1 - range 1 65535 - ---help--- - If you are using the DMA2D, then you must provide the pixel per line or - width of the overlay. - -config STM32_DMA2D_FB_BASE - hex "Framebuffer memory start address" - default 0 - ---help--- - If you are using the DMA2D, then you must provide the address - of the start of the DMA2D overlays framebuffer. This address will typically - be in the SRAM or SDRAM memory region of the FSMC/FMC. - -config STM32_DMA2D_FB_SIZE - int "Framebuffer memory size (bytes)" - default 0 - ---help--- - Must be the whole size of all DMA2D overlays. - -menu "Supported pixel format" - -config STM32_DMA2D_L8 - depends on STM32_FB_CMAP && STM32_LTDC_L1_L8 - bool "8 bpp L8 (8-bit CLUT)" - default y - -config STM32_DMA2D_AL44 - depends on STM32_FB_CMAP && STM32_LTDC_L1_AL44 - bool "8 bpp AL44 (4-bit alpha + 4-bit CLUT)" - default y - -config STM32_DMA2D_AL88 - depends on STM32_FB_CMAP && STM32_LTDC_L1_AL88 - bool "16 bpp AL88 (8-bit alpha + 8-bit CLUT)" - default y - -config STM32_DMA2D_RGB565 - bool "16 bpp RGB 565" - depends on STM32_LTDC_L1_RGB565 - default y - -config STM32_DMA2D_ARGB4444 - bool "16 bpp ARGB 4444" - depends on STM32_LTDC_L1_ARGB4444 - default y - -config STM32_DMA2D_ARGB1555 - bool "16 bpp ARGB 1555" - depends on STM32_LTDC_L1_ARGB15555 - default y - -config STM32_DMA2D_RGB888 - bool "24 bpp RGB 888" - depends on STM32_LTDC_L1_RGB888 - default y - -config STM32_DMA2D_ARGB8888 - bool "32 bpp ARGB 8888" - depends on STM32_LTDC_L1_ARGB8888 - default y - -endmenu - -config STM32_DMA2D_REGDEBUG - bool "DMA2D Register level debug" - depends on DEBUG_INFO && DEBUG_LCD - default n - ---help--- - Output detailed register-level DMA2D device debug information. - -endmenu -endif # STM32_DMA2D - -config STM32_QE - bool - default n - -menu "STM32 QEncoder Driver" - depends on SENSORS_QENCODER - depends on STM32_TIM1 || STM32_TIM2 || STM32_TIM3 || STM32_TIM4 || STM32_TIM5 || STM32_TIM8 - -config STM32_QENCODER_DISABLE_EXTEND16BTIMERS - bool "Disable QEncoder timers extension from 16-bit to 32-bit" - default n - -config STM32_QENCODER_INDEX_PIN - bool "Enable QEncoder timers support for index pin" - default n - -config STM32_TIM1_QE - bool "TIM1 QE" - default n - depends on STM32_TIM1 - select STM32_QE - ---help--- - Reserve TIM1 for use by QEncoder. - -if STM32_TIM1_QE - -config STM32_TIM1_QEPSC - int "TIM1 QE pulse prescaler" - default 1 - ---help--- - This prescaler divides the number of recorded encoder pulses, - limiting the count rate at the expense of resolution. - -endif - -config STM32_TIM2_QE - bool "TIM2 QE" - default n - depends on STM32_TIM2 - select STM32_QE - ---help--- - Reserve TIM2 for use by QEncoder. - -if STM32_TIM2_QE - -config STM32_TIM2_QEPSC - int "TIM2 QE pulse prescaler" - default 1 - ---help--- - This prescaler divides the number of recorded encoder pulses, - limiting the count rate at the expense of resolution. - -endif - -config STM32_TIM3_QE - bool "TIM3 QE" - default n - depends on STM32_TIM3 - select STM32_QE - ---help--- - Reserve TIM3 for use by QEncoder. - -if STM32_TIM3_QE - -config STM32_TIM3_QEPSC - int "TIM3 QE pulse prescaler" - default 1 - ---help--- - This prescaler divides the number of recorded encoder pulses, - limiting the count rate at the expense of resolution. - -endif - -config STM32_TIM4_QE - bool "TIM4 QE" - default n - depends on STM32_TIM4 - select STM32_QE - ---help--- - Reserve TIM4 for use by QEncoder. - -if STM32_TIM4_QE - -config STM32_TIM4_QEPSC - int "TIM4 QE pulse prescaler" - default 1 - ---help--- - This prescaler divides the number of recorded encoder pulses, - limiting the count rate at the expense of resolution. - -endif - -config STM32_TIM5_QE - bool "TIM5 QE" - default n - depends on STM32_TIM5 - select STM32_QE - ---help--- - Reserve TIM5 for use by QEncoder. - -if STM32_TIM5_QE - -config STM32_TIM5_QEPSC - int "TIM5 QE pulse prescaler" - default 1 - ---help--- - This prescaler divides the number of recorded encoder pulses, - limiting the count rate at the expense of resolution. - -endif - -config STM32_TIM8_QE - bool "TIM8 QE" - default n - depends on STM32_TIM8 - select STM32_QE - ---help--- - Reserve TIM8 for use by QEncoder. - -if STM32_TIM8_QE - -config STM32_TIM8_QEPSC - int "TIM8 QE pulse prescaler" - default 1 - ---help--- - This prescaler divides the number of recorded encoder pulses, - limiting the count rate at the expense of resolution. - -endif - -config STM32_QENCODER_FILTER - bool "Enable filtering on STM32 QEncoder input" - default y - -choice - depends on STM32_QENCODER_FILTER - prompt "Input channel sampling frequency" - default STM32_QENCODER_SAMPLE_FDTS_4 - -config STM32_QENCODER_SAMPLE_FDTS - bool "fDTS" - -config STM32_QENCODER_SAMPLE_CKINT - bool "fCK_INT" - -config STM32_QENCODER_SAMPLE_FDTS_2 - bool "fDTS/2" - -config STM32_QENCODER_SAMPLE_FDTS_4 - bool "fDTS/4" - -config STM32_QENCODER_SAMPLE_FDTS_8 - bool "fDTS/8" - -config STM32_QENCODER_SAMPLE_FDTS_16 - bool "fDTS/16" - -config STM32_QENCODER_SAMPLE_FDTS_32 - bool "fDTS/32" - -endchoice - -choice - depends on STM32_QENCODER_FILTER - prompt "Input channel event count" - default STM32_QENCODER_SAMPLE_EVENT_6 - -config STM32_QENCODER_SAMPLE_EVENT_1 - depends on STM32_QENCODER_SAMPLE_FDTS - bool "1" - -config STM32_QENCODER_SAMPLE_EVENT_2 - depends on STM32_QENCODER_SAMPLE_CKINT - bool "2" - -config STM32_QENCODER_SAMPLE_EVENT_4 - depends on STM32_QENCODER_SAMPLE_CKINT - bool "4" - -config STM32_QENCODER_SAMPLE_EVENT_5 - depends on STM32_QENCODER_SAMPLE_FDTS_16 || STM32_QENCODER_SAMPLE_FDTS_32 - bool "5" - -config STM32_QENCODER_SAMPLE_EVENT_6 - depends on !STM32_QENCODER_SAMPLE_FDTS && !STM32_QENCODER_SAMPLE_CKINT - bool "6" - -config STM32_QENCODER_SAMPLE_EVENT_8 - depends on !STM32_QENCODER_SAMPLE_FDTS - bool "8" - -endchoice - -endmenu - -menuconfig STM32_FOC - bool "STM32 lower-half FOC support" - default n - select ARCH_IRQPRIO - select STM32_PWM_MULTICHAN - select STM32_PWM_LL_OPS - select STM32_ADC_LL_OPS - select STM32_ADC_CHANGE_SAMPLETIME - select STM32_ADC_NO_STARTUP_CONV - -if STM32_FOC - -config STM32_FOC_FOC0 - bool "FOC0 device (TIM1 for PWM modulation)" - default n - depends on STM32_HAVE_TIM1 - select STM32_FOC_USE_TIM1 - ---help--- - Enable support for FOC0 device that uses TIM1 for PWM modulation - -config STM32_FOC_FOC1 - bool "FOC1 device (TIM8 for PWM modulation)" - default n - depends on STM32_HAVE_TIM8 - select STM32_FOC_USE_TIM8 - ---help--- - Enable support for FOC1 device that uses TIM8 for PWM modulation - -choice - prompt "FOC ADC trigger selection" - default STM32_FOC_ADC_TRGO - -config STM32_FOC_ADC_CCR4 - bool "FOC uses CCR4 as ADC trigger" - ---help--- - This option uses the software frequency prescaler and is - not possible for 4-phase output. - -config STM32_FOC_ADC_TRGO - bool "FOC uses TRGO as ADC trigger" - depends on STM32_HAVE_IP_ADC_V2 || (STM32_HAVE_IP_ADC_V1 && !STM32_FOC_FOC1) - select STM32_PWM_TRGO - ---help--- - This option allows you to use higher PWM frequency and works for 4-phase output. - It is not possible for ADC IPv1 if FOC1 enabled (no T8TRGO in JEXTSEL). - -endchoice # "FOC ADC trigger selection" - -if STM32_FOC_FOC0 - -choice - prompt "FOC0 device ADC selection" - default STM32_FOC_FOC0_ADC1 - -config STM32_FOC_FOC0_ADC1 - bool "FOC0 uses ADC1" - depends on STM32_HAVE_ADC1 - select STM32_FOC_USE_ADC1 - -config STM32_FOC_FOC0_ADC2 - bool "FOC0 uses ADC2" - depends on STM32_HAVE_ADC2 - select STM32_FOC_USE_ADC2 - -config STM32_FOC_FOC0_ADC3 - bool "FOC0 uses ADC3" - depends on STM32_HAVE_ADC3 - select STM32_FOC_USE_ADC3 - -config STM32_FOC_FOC0_ADC4 - bool "FOC0 uses ADC4" - depends on STM32_HAVE_ADC4 - select STM32_FOC_USE_ADC4 - -endchoice # "FOC0 device ADC selection" - -endif # STM32_FOC_FOC0 - -if STM32_FOC_FOC1 - -choice - prompt "FOC1 device ADC selection" - default STM32_FOC_FOC1_ADC2 - -config STM32_FOC_FOC1_ADC1 - bool "FOC1 uses ADC1" - depends on STM32_HAVE_ADC1 - select STM32_FOC_USE_ADC1 - -config STM32_FOC_FOC1_ADC2 - bool "FOC1 uses ADC2" - depends on STM32_HAVE_ADC2 - select STM32_FOC_USE_ADC2 - -config STM32_FOC_FOC1_ADC3 - bool "FOC1 uses ADC3" - depends on STM32_HAVE_ADC3 - select STM32_FOC_USE_ADC3 - -config STM32_FOC_FOC1_ADC4 - bool "FOC1 uses ADC4" - depends on STM32_HAVE_ADC4 - select STM32_FOC_USE_ADC4 - -endchoice # "FOC0 device ADC selection" - -endif # STM32_FOC_FOC1 - -config STM32_FOC_HAS_PWM_COMPLEMENTARY - bool "FOC PWM has complementary outputs" - default n - ---help--- - Enable complementary outputs for the FOC PWM (sometimes called 6-PWM mode) - -# hidden variables and automatic configuration - -config STM32_FOC_USE_TIM1 - bool - default n - select STM32_TIM1 - select STM32_TIM1_PWM - select STM32_TIM1_CHANNEL1 - select STM32_TIM1_CHANNEL2 - select STM32_TIM1_CHANNEL3 - select STM32_TIM1_CHANNEL4 if STM32_FOC_ADC_CCR4 - select STM32_TIM1_CH1OUT - select STM32_TIM1_CH2OUT - select STM32_TIM1_CH3OUT - select STM32_TIM1_CH4OUT if STM32_FOC_ADC_CCR4 - select STM32_TIM1_CH1NOUT if STM32_FOC_HAS_PWM_COMPLEMENTARY - select STM32_TIM1_CH2NOUT if STM32_FOC_HAS_PWM_COMPLEMENTARY - select STM32_TIM1_CH3NOUT if STM32_FOC_HAS_PWM_COMPLEMENTARY - ---help--- - The TIM1 generates PWM for the FOC - -config STM32_FOC_USE_TIM8 - bool - default n - select STM32_TIM8 - select STM32_TIM8_PWM - select STM32_TIM8_CHANNEL1 - select STM32_TIM8_CHANNEL2 - select STM32_TIM8_CHANNEL3 - select STM32_TIM8_CHANNEL4 if STM32_FOC_ADC_CCR4 - select STM32_TIM8_CH1OUT - select STM32_TIM8_CH2OUT - select STM32_TIM8_CH3OUT - select STM32_TIM8_CH4OUT if STM32_FOC_ADC_CCR4 - select STM32_TIM8_CH1NOUT if STM32_FOC_HAS_PWM_COMPLEMENTARY - select STM32_TIM8_CH2NOUT if STM32_FOC_HAS_PWM_COMPLEMENTARY - select STM32_TIM8_CH3NOUT if STM32_FOC_HAS_PWM_COMPLEMENTARY - ---help--- - The TIM8 generates PWM for the FOC - -config STM32_FOC_USE_ADC1 - bool - default n - select STM32_ADC1 - select STM32_ADC1_SCAN if STM32_HAVE_IP_ADC_V1 - select STM32_ADC1_JEXTSEL - -config STM32_FOC_USE_ADC2 - bool - default n - select STM32_ADC2 - select STM32_ADC2_SCAN if STM32_HAVE_IP_ADC_V1 - select STM32_ADC2_JEXTSEL - -config STM32_FOC_USE_ADC3 - bool - default n - select STM32_ADC3 - select STM32_ADC3_SCAN if STM32_HAVE_IP_ADC_V1 - select STM32_ADC3_JEXTSEL - -config STM32_FOC_USE_ADC4 - bool - default n - select STM32_ADC4 - select STM32_ADC3_JEXTSEL - -config STM32_FOC_G4_ADCCHAN0_WORKAROUND - bool "FOC G4 ADC channel 0 unwanted conversion workaround" - default n - depends on STM32_STM32G4XXX - ---help--- - Some STM32G4 family chips have an issue that causes unwanted ADC channel 0 - conversion when a regular conversion is interrupted by an injected conversion. - This FOC implementation uses injected conversion to sample phase currents - and allows user to use regular conversion as an auxiliary analog conversion. - In this case, there is a certain probability that regular conversion will be - interrupted by an injected conversion that will lead to an incorrect reading - of phase currents. - - This workaround inserts a dummy conversion at the beginning of the injected - sequence. For more details look at the chip errata documents. - -endif #STM32_FOC diff --git a/arch/arm/src/stm32/Make.defs b/arch/arm/src/stm32/Make.defs deleted file mode 100644 index 32c30a76ee74e..0000000000000 --- a/arch/arm/src/stm32/Make.defs +++ /dev/null @@ -1,261 +0,0 @@ -############################################################################ -# arch/arm/src/stm32/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include armv7-m/Make.defs - -CHIP_CSRCS = stm32_allocateheap.c stm32_start.c stm32_rcc.c stm32_lse.c -CHIP_CSRCS += stm32_lsi.c stm32_gpio.c stm32_exti_gpio.c stm32_flash.c -CHIP_CSRCS += stm32_irq.c stm32_lowputc.c -CHIP_CSRCS += stm32_spi.c stm32_i2s.c stm32_sdio.c stm32_tim.c -CHIP_CSRCS += stm32_waste.c stm32_ccm.c stm32_uid.c stm32_capture.c -CHIP_CSRCS += stm32_dfumode.c - -ifeq ($(CONFIG_STM32_USART),y) -CHIP_CSRCS += stm32_serial.c -endif - -ifeq ($(CONFIG_STM32_DMA),y) -CHIP_CSRCS += stm32_dma.c -endif - -ifeq ($(CONFIG_TIMER),y) -CHIP_CSRCS += stm32_tim_lowerhalf.c -endif - -ifdef CONFIG_STM32_TICKLESS_TIMER -CHIP_CSRCS += stm32_tickless.c -else -CHIP_CSRCS += stm32_timerisr.c -endif - -ifeq ($(CONFIG_STM32_ONESHOT),y) -CHIP_CSRCS += stm32_oneshot.c stm32_oneshot_lowerhalf.c -endif - -ifeq ($(CONFIG_STM32_FREERUN),y) -CHIP_CSRCS += stm32_freerun.c -endif - -ifeq ($(CONFIG_BUILD_PROTECTED),y) -CHIP_CSRCS += stm32_userspace.c stm32_mpuinit.c -endif - -ifeq ($(CONFIG_STM32_HAVE_IP_I2C_V1),y) -ifeq ($(CONFIG_STM32_I2C_ALT),y) -CHIP_CSRCS += stm32_i2c_alt.c -else ifeq ($(CONFIG_STM32_STM32F4XXX),y) -CHIP_CSRCS += stm32f40xxx_i2c.c -else -CHIP_CSRCS += stm32_i2c.c -endif -else ifeq ($(CONFIG_STM32_HAVE_IP_I2C_V2),y) -CHIP_CSRCS += stm32_i2c_v2.c -ifeq ($(CONFIG_STM32_I2C_SLAVE),y) -CHIP_CSRCS += stm32_i2cslave_v2.c -endif -endif - -ifeq ($(CONFIG_USBDEV),y) -ifeq ($(CONFIG_STM32_USB),y) -CHIP_CSRCS += stm32_usbdev.c -endif -ifeq ($(CONFIG_STM32_USBFS),y) -CHIP_CSRCS += stm32_usbfs.c -endif -ifeq ($(CONFIG_STM32_OTGFS),y) -CHIP_CSRCS += stm32_otgfsdev.c -endif -ifeq ($(CONFIG_STM32_OTGHS),y) -CHIP_CSRCS += stm32_otghsdev.c -endif -endif - -ifeq ($(CONFIG_STM32_USBHOST),y) -ifeq ($(CONFIG_STM32_OTGFS),y) -CHIP_CSRCS += stm32_otgfshost.c -endif -ifeq ($(CONFIG_STM32_OTGHS),y) -CHIP_CSRCS += stm32_otghshost.c -endif -ifeq ($(CONFIG_USBHOST_TRACE),y) -CHIP_CSRCS += stm32_usbhost.c -else -ifeq ($(CONFIG_DEBUG_USB),y) -CHIP_CSRCS += stm32_usbhost.c -endif -endif -endif - -ifneq ($(CONFIG_ARCH_IDLE_CUSTOM),y) -CHIP_CSRCS += stm32_idle.c -endif - -CHIP_CSRCS += stm32_pmstop.c stm32_pmstandby.c stm32_pmsleep.c - -ifneq ($(CONFIG_ARCH_CUSTOM_PMINIT),y) -CHIP_CSRCS += stm32_pminitialize.c -endif - -ifeq ($(CONFIG_STM32_ETHMAC),y) -CHIP_CSRCS += stm32_eth.c -endif - -ifeq ($(CONFIG_STM32_PWR),y) -CHIP_CSRCS += stm32_pwr.c stm32_exti_pwr.c -endif - -ifeq ($(CONFIG_STM32_RTC),y) -CHIP_CSRCS += stm32_rtc.c -ifeq ($(CONFIG_RTC_ALARM),y) -CHIP_CSRCS += stm32_exti_alarm.c -endif -ifeq ($(CONFIG_RTC_PERIODIC),y) -CHIP_CSRCS += stm32_exti_wakeup.c -endif -ifeq ($(CONFIG_RTC_DRIVER),y) -CHIP_CSRCS += stm32_rtc_lowerhalf.c -endif -endif - -ifeq ($(CONFIG_STM32_ADC),y) -CHIP_CSRCS += stm32_adc.c -endif - -ifeq ($(CONFIG_STM32_SDADC),y) -CHIP_CSRCS += stm32_sdadc.c -endif - -ifeq ($(CONFIG_STM32_DAC),y) -CHIP_CSRCS += stm32_dac.c -endif - -ifeq ($(CONFIG_STM32_COMP),y) -CHIP_CSRCS += stm32_comp.c -endif - -ifeq ($(CONFIG_STM32_OPAMP),y) -CHIP_CSRCS += stm32_opamp.c -endif - -ifeq ($(CONFIG_STM32_HRTIM),y) -CHIP_CSRCS += stm32_hrtim.c -endif - -ifeq ($(CONFIG_STM32_1WIREDRIVER),y) -CHIP_CSRCS += stm32_1wire.c -endif - -ifeq ($(CONFIG_STM32_HCIUART),y) -CHIP_CSRCS += stm32_hciuart.c -endif - -ifeq ($(CONFIG_STM32_RNG),y) -CHIP_CSRCS += stm32_rng.c -endif - -ifeq ($(CONFIG_STM32_LTDC),y) -CHIP_CSRCS += stm32_ltdc.c -endif - -ifeq ($(CONFIG_STM32_DMA2D),y) -CHIP_CSRCS += stm32_dma2d.c -endif - -ifeq ($(CONFIG_STM32_PWM),y) -CHIP_CSRCS += stm32_pwm.c -endif - -ifeq ($(CONFIG_STM32_PULSECOUNT),y) -CHIP_CSRCS += stm32_pulsecount.c -endif - -ifeq ($(CONFIG_STM32_CAP),y) -CHIP_CSRCS += stm32_capture_lowerhalf.c -endif - -ifeq ($(CONFIG_SENSORS_QENCODER),y) - ifeq ($(CONFIG_STM32_QE),y) - CHIP_CSRCS += stm32_qencoder.c - endif -endif - -ifeq ($(CONFIG_SENSORS_HALL3PHASE),y) -CHIP_CSRCS += stm32_hall3ph.c -endif - -ifeq ($(CONFIG_STM32_CAN),y) -ifeq ($(CONFIG_STM32_CAN_CHARDRIVER),y) -CHIP_CSRCS += stm32_can.c -endif -ifeq ($(CONFIG_STM32_CAN_SOCKET),y) -CHIP_CSRCS += stm32_can_sock.c -endif -endif - -ifeq ($(CONFIG_STM32_FDCAN),y) -ifeq ($(CONFIG_STM32_FDCAN_CHARDRIVER),y) -CHIP_CSRCS += stm32_fdcan.c -endif -ifeq ($(CONFIG_STM32_FDCAN_SOCKET),y) -CHIP_CSRCS += stm32_fdcan_sock.c -endif -endif - -ifeq ($(CONFIG_STM32_IWDG),y) -CHIP_CSRCS += stm32_iwdg.c -endif - -ifeq ($(CONFIG_STM32_WWDG),y) -CHIP_CSRCS += stm32_wwdg.c -endif - -ifeq ($(CONFIG_DEBUG_FEATURES),y) -CHIP_CSRCS += stm32_dumpgpio.c -endif - -ifeq ($(CONFIG_STM32_AES),y) -CHIP_CSRCS += stm32_aes.c -endif - -ifeq ($(CONFIG_CRYPTO_CRYPTODEV_HARDWARE),y) -CHIP_CSRCS += stm32_crypto.c -endif - -ifeq ($(CONFIG_STM32_BBSRAM),y) -CHIP_CSRCS += stm32_bbsram.c -endif - -ifeq ($(CONFIG_STM32_FMC),y) -CHIP_CSRCS += stm32_fmc.c -endif - -ifeq ($(CONFIG_STM32_FSMC),y) -CHIP_CSRCS += stm32_fsmc.c -endif - -ifeq ($(CONFIG_STM32_FOC),y) -CHIP_CSRCS += stm32_foc.c -endif - -ifeq ($(CONFIG_STM32_CORDIC),y) -CHIP_CSRCS += stm32_cordic.c -endif diff --git a/arch/arm/src/stm32/chip.h b/arch/arm/src/stm32/chip.h deleted file mode 100644 index 295751fca513a..0000000000000 --- a/arch/arm/src/stm32/chip.h +++ /dev/null @@ -1,59 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/chip.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32_CHIP_H -#define __ARCH_ARM_SRC_STM32_CHIP_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -/* Include the chip capabilities file */ - -#include - -/* Include the chip interrupt definition file */ - -#include - -/* Include the chip memory map */ - -#include "hardware/stm32_memorymap.h" - -/* Include the chip pinmap */ - -#include "hardware/stm32_pinmap.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Provide the required number of peripheral interrupt vector - * definitions as * well. The definition STM32_IRQ_NEXTINTS simply comes - * from the chip-specific * IRQ header file included by arch/stm32/irq.h. - */ - -#define ARMV7M_PERIPHERAL_INTERRUPTS STM32_IRQ_NEXTINTS - -#endif /* __ARCH_ARM_SRC_STM32_CHIP_H */ diff --git a/arch/arm/src/stm32/hardware/stm32_adc.h b/arch/arm/src/stm32/hardware/stm32_adc.h deleted file mode 100644 index 4bfee933c6e95..0000000000000 --- a/arch/arm/src/stm32/hardware/stm32_adc.h +++ /dev/null @@ -1,70 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/hardware/stm32_adc.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_ADC_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_ADC_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "chip.h" - -/* There are 2 main types of ADC IP cores among STM32 chips: - * 1. STM32 ADC IPv1: - * a) basic version for F1 and F37x - * b) extended version for F2, F4, F7, L1: - * 2. STM32 ADC IPv2: - * a) basic version for F0 and L0 - * b) extended version for F3 (without F37x), G4, H7, L4, L4+ - * - * We also distinguish these variants: - * 1. The modified STM32 ADC IPv1 core for the L1 family, which differs - * too much to keep it in the same file as ADC IPv1. - * 2. The modified STM32 ADC IPv2 core for the G4 family, which differs - * too much to keep it in the same file as ADC IPv2. - */ - -#if defined(CONFIG_STM32_HAVE_IP_ADC_V1) && \ - defined(CONFIG_STM32_HAVE_IP_ADC_V2) -# error Only one STM32 ADC IP version must be selected -#endif - -#if defined(CONFIG_STM32_HAVE_IP_ADC_V1) -# if defined(CONFIG_STM32_STM32L15XX) -# include "stm32_adc_v1l1.h" /* Special case for L1 */ -# else -# include "stm32_adc_v1.h" -# endif -#elif defined(CONFIG_STM32_HAVE_IP_ADC_V2) -# if defined(CONFIG_STM32_STM32G4XXX) -# include "stm32_adc_v2g4.h" /* Special case for G4 */ -# else -# include "stm32_adc_v2.h" -# endif -#else -# error "STM32 ADC IP version not specified" -#endif - -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_ADC_H */ diff --git a/arch/arm/src/stm32/hardware/stm32_bkp.h b/arch/arm/src/stm32/hardware/stm32_bkp.h deleted file mode 100644 index a06ed4085dc81..0000000000000 --- a/arch/arm/src/stm32/hardware/stm32_bkp.h +++ /dev/null @@ -1,177 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/hardware/stm32_bkp.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_BKP_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_BKP_H - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#if defined(CONFIG_STM32_HIGHDENSITY) || defined(CONFIG_STM32_CONNECTIVITYLINE) -# define CONFIG_STM32_NBKP_BYTES 84 -# define CONFIG_STM32_NBKP_REGS 42 -#else -# define CONFIG_STM32_NBKP_BYTES 20 -# define CONFIG_STM32_NBKP_REGS 10 -#endif - -/* Register Offsets *********************************************************/ - -#if defined(CONFIG_STM32_HIGHDENSITY) || defined(CONFIG_STM32_CONNECTIVITYLINE) -# define STM32_BKP_DR_OFFSET(n) ((n) > 10 ? 0x0040+4*((n)-10) : 0x0004+4*(n)) -#else -# define STM32_BKP_DR_OFFSET(n) (0x0004+4*(n)) -#endif - -#define STM32_BKP_DR1_OFFSET 0x0004 /* Backup data register 1 */ -#define STM32_BKP_DR2_OFFSET 0x0008 /* Backup data register 2 */ -#define STM32_BKP_DR3_OFFSET 0x000c /* Backup data register 3 */ -#define STM32_BKP_DR4_OFFSET 0x0010 /* Backup data register 4 */ -#define STM32_BKP_DR5_OFFSET 0x0014 /* Backup data register 5 */ -#define STM32_BKP_DR6_OFFSET 0x0018 /* Backup data register 6 */ -#define STM32_BKP_DR7_OFFSET 0x001c /* Backup data register 7 */ -#define STM32_BKP_DR8_OFFSET 0x0020 /* Backup data register 8 */ -#define STM32_BKP_DR9_OFFSET 0x0024 /* Backup data register 9 */ -#define STM32_BKP_DR10_OFFSET 0x0028 /* Backup data register 10 */ - -#define STM32_BKP_RTCCR_OFFSET 0x002c /* RTC clock calibration register */ -#define STM32_BKP_CR_OFFSET 0x0030 /* Backup control register */ -#define STM32_BKP_CSR_OFFSET 0x0034 /* Backup control/status register */ - -#if defined(CONFIG_STM32_HIGHDENSITY) || defined(CONFIG_STM32_CONNECTIVITYLINE) -# define STM32_BKP_DR11_OFFSET 0x0040 /* Backup data register 11 */ -# define STM32_BKP_DR12_OFFSET 0x0044 /* Backup data register 12 */ -# define STM32_BKP_DR13_OFFSET 0x0048 /* Backup data register 13 */ -# define STM32_BKP_DR14_OFFSET 0x004c /* Backup data register 14 */ -# define STM32_BKP_DR15_OFFSET 0x0050 /* Backup data register 15 */ -# define STM32_BKP_DR16_OFFSET 0x0054 /* Backup data register 16 */ -# define STM32_BKP_DR17_OFFSET 0x0058 /* Backup data register 17 */ -# define STM32_BKP_DR18_OFFSET 0x005c /* Backup data register 18 */ -# define STM32_BKP_DR19_OFFSET 0x0060 /* Backup data register 19 */ -# define STM32_BKP_DR20_OFFSET 0x0064 /* Backup data register 20 */ -# define STM32_BKP_DR21_OFFSET 0x0068 /* Backup data register 21 */ -# define STM32_BKP_DR22_OFFSET 0x006c /* Backup data register 22 */ -# define STM32_BKP_DR23_OFFSET 0x0070 /* Backup data register 23 */ -# define STM32_BKP_DR24_OFFSET 0x0074 /* Backup data register 24 */ -# define STM32_BKP_DR25_OFFSET 0x0078 /* Backup data register 25 */ -# define STM32_BKP_DR26_OFFSET 0x007c /* Backup data register 26 */ -# define STM32_BKP_DR27_OFFSET 0x0080 /* Backup data register 27 */ -# define STM32_BKP_DR28_OFFSET 0x0084 /* Backup data register 28 */ -# define STM32_BKP_DR29_OFFSET 0x0088 /* Backup data register 29 */ -# define STM32_BKP_DR30_OFFSET 0x008c /* Backup data register 30 */ -# define STM32_BKP_DR31_OFFSET 0x0090 /* Backup data register 31 */ -# define STM32_BKP_DR32_OFFSET 0x0094 /* Backup data register 32 */ -# define STM32_BKP_DR33_OFFSET 0x0098 /* Backup data register 33 */ -# define STM32_BKP_DR34_OFFSET 0x009c /* Backup data register 34 */ -# define STM32_BKP_DR35_OFFSET 0x00a0 /* Backup data register 35 */ -# define STM32_BKP_DR36_OFFSET 0x00a4 /* Backup data register 36 */ -# define STM32_BKP_DR37_OFFSET 0x00a8 /* Backup data register 37 */ -# define STM32_BKP_DR38_OFFSET 0x00ac /* Backup data register 38 */ -# define STM32_BKP_DR39_OFFSET 0x00b0 /* Backup data register 39 */ -# define STM32_BKP_DR40_OFFSET 0x00b4 /* Backup data register 40 */ -# define STM32_BKP_DR41_OFFSET 0x00b8 /* Backup data register 41 */ -# define STM32_BKP_DR42_OFFSET 0x00bc /* Backup data register 42 */ -#endif - -/* Register Addresses *******************************************************/ - -#define STM32_BKP_RTCCR (STM32_BKP_BASE+STM32_BKP_RTCCR_OFFSET) -#define STM32_BKP_CR (STM32_BKP_BASE+STM32_BKP_CR_OFFSET) -#define STM32_BKP_CSR (STM32_BKP_BASE+STM32_BKP_CSR_OFFSET) - -#define STM32_BKP_DR(n) (STM32_BKP_BASE+STM32_BKP_DR_OFFSET(n)) -#define STM32_BKP_DR1 (STM32_BKP_BASE+STM32_BKP_DR1_OFFSET) -#define STM32_BKP_DR2 (STM32_BKP_BASE+STM32_BKP_DR2_OFFSET) -#define STM32_BKP_DR3 (STM32_BKP_BASE+STM32_BKP_DR3_OFFSET) -#define STM32_BKP_DR4 (STM32_BKP_BASE+STM32_BKP_DR4_OFFSET) -#define STM32_BKP_DR5 (STM32_BKP_BASE+STM32_BKP_DR5_OFFSET) -#define STM32_BKP_DR6 (STM32_BKP_BASE+STM32_BKP_DR6_OFFSET) -#define STM32_BKP_DR7 (STM32_BKP_BASE+STM32_BKP_DR7_OFFSET) -#define STM32_BKP_DR8 (STM32_BKP_BASE+STM32_BKP_DR8_OFFSET) -#define STM32_BKP_DR9 (STM32_BKP_BASE+STM32_BKP_DR9_OFFSET) -#define STM32_BKP_DR10 (STM32_BKP_BASE+STM32_BKP_DR10_OFFSET) - -#if defined(CONFIG_STM32_HIGHDENSITY) || defined(CONFIG_STM32_CONNECTIVITYLINE) -# define STM32_BKP_DR11 (STM32_BKP_BASE+STM32_BKP_DR11_OFFSET) -# define STM32_BKP_DR12 (STM32_BKP_BASE+STM32_BKP_DR12_OFFSET) -# define STM32_BKP_DR13 (STM32_BKP_BASE+STM32_BKP_DR13_OFFSET) -# define STM32_BKP_DR14 (STM32_BKP_BASE+STM32_BKP_DR14_OFFSET) -# define STM32_BKP_DR15 (STM32_BKP_BASE+STM32_BKP_DR15_OFFSET) -# define STM32_BKP_DR16 (STM32_BKP_BASE+STM32_BKP_DR16_OFFSET) -# define STM32_BKP_DR17 (STM32_BKP_BASE+STM32_BKP_DR17_OFFSET) -# define STM32_BKP_DR18 (STM32_BKP_BASE+STM32_BKP_DR18_OFFSET) -# define STM32_BKP_DR19 (STM32_BKP_BASE+STM32_BKP_DR19_OFFSET) -# define STM32_BKP_DR20 (STM32_BKP_BASE+STM32_BKP_DR20_OFFSET) -# define STM32_BKP_DR21 (STM32_BKP_BASE+STM32_BKP_DR21_OFFSET) -# define STM32_BKP_DR22 (STM32_BKP_BASE+STM32_BKP_DR22_OFFSET) -# define STM32_BKP_DR23 (STM32_BKP_BASE+STM32_BKP_DR23_OFFSET) -# define STM32_BKP_DR24 (STM32_BKP_BASE+STM32_BKP_DR24_OFFSET) -# define STM32_BKP_DR25 (STM32_BKP_BASE+STM32_BKP_DR25_OFFSET) -# define STM32_BKP_DR26 (STM32_BKP_BASE+STM32_BKP_DR26_OFFSET) -# define STM32_BKP_DR27 (STM32_BKP_BASE+STM32_BKP_DR27_OFFSET) -# define STM32_BKP_DR28 (STM32_BKP_BASE+STM32_BKP_DR28_OFFSET) -# define STM32_BKP_DR29 (STM32_BKP_BASE+STM32_BKP_DR29_OFFSET) -# define STM32_BKP_DR30 (STM32_BKP_BASE+STM32_BKP_DR30_OFFSET) -# define STM32_BKP_DR31 (STM32_BKP_BASE+STM32_BKP_DR31_OFFSET) -# define STM32_BKP_DR32 (STM32_BKP_BASE+STM32_BKP_DR32_OFFSET) -# define STM32_BKP_DR33 (STM32_BKP_BASE+STM32_BKP_DR33_OFFSET) -# define STM32_BKP_DR34 (STM32_BKP_BASE+STM32_BKP_DR34_OFFSET) -# define STM32_BKP_DR35 (STM32_BKP_BASE+STM32_BKP_DR35_OFFSET) -# define STM32_BKP_DR36 (STM32_BKP_BASE+STM32_BKP_DR36_OFFSET) -# define STM32_BKP_DR37 (STM32_BKP_BASE+STM32_BKP_DR37_OFFSET) -# define STM32_BKP_DR38 (STM32_BKP_BASE+STM32_BKP_DR38_OFFSET) -# define STM32_BKP_DR39 (STM32_BKP_BASE+STM32_BKP_DR39_OFFSET) -# define STM32_BKP_DR40 (STM32_BKP_BASE+STM32_BKP_DR40_OFFSET) -# define STM32_BKP_DR41 (STM32_BKP_BASE+STM32_BKP_DR41_OFFSET) -# define STM32_BKP_DR42 (STM32_BKP_BASE+STM32_BKP_DR42_OFFSET) -#endif - -/* Register Bitfield Definitions ********************************************/ - -/* RTC clock calibration register */ - -#define BKP_RTCCR_CAL_SHIFT (0) /* Bits 6-0: Calibration value */ -#define BKP_RTCCR_CAL_MASK (0x7f << BKP_RTCCR_CAL_SHIFT) -#define BKP_RTCCR_CCO (1 << 7) /* Bit 7: Calibration Clock Output */ -#define BKP_RTCCR_ASOE (1 << 8) /* Bit 8: Alarm or Second Output Enable */ -#define BKP_RTCCR_ASOS (1 << 9) /* Bit 9: Alarm or Second Output Selection */ - -/* Backup control register */ - -#define BKP_CR_TPE (1 << 0) /* Bit 0: TAMPER pin enable */ -#define BKP_CR_TPAL (1 << 1) /* Bit 1: TAMPER pin active level */ - -/* Backup control/status register */ - -#define BKP_CSR_CTE (1 << 0) /* Bit 0: Clear Tamper event */ -#define BKP_CSR_CTI (1 << 1) /* Bit 1: Clear Tamper Interrupt */ -#define BKP_CSR_TPIE (1 << 2) /* Bit 2: TAMPER Pin interrupt enable */ -#define BKP_CSR_TEF (1 << 8) /* Bit 8: Tamper Event Flag */ -#define BKP_CSR_TIF (1 << 9) /* Bit 9: Tamper Interrupt Flag */ - -/* Backup data register */ - -#define BKP_DR_SHIFT (0) /* Bits 1510: Backup data */ -#define BKP_DR_MASK (0xffff << BKP_DR_SHIFT) - -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_BKP_H */ diff --git a/arch/arm/src/stm32/hardware/stm32_can.h b/arch/arm/src/stm32/hardware/stm32_can.h deleted file mode 100644 index f1c0fa67523b0..0000000000000 --- a/arch/arm/src/stm32/hardware/stm32_can.h +++ /dev/null @@ -1,497 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/hardware/stm32_can.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_CAN_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_CAN_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "chip.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* 3 TX mailboxes */ - -#define CAN_TXMBOX1 0 -#define CAN_TXMBOX2 1 -#define CAN_TXMBOX3 2 - -/* 2 RX mailboxes */ - -#define CAN_RXMBOX1 0 -#define CAN_RXMBOX2 1 - -/* Number of filters depends on silicon */ - -#if defined(CONFIG_STM32_CONNECTIVITYLINE) || defined(CONFIG_STM32_STM32F20XX) || \ - defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F4XXX) -# define CAN_NFILTERS 28 -#else -# define CAN_NFILTERS 14 -#endif - -/* Register Offsets *********************************************************/ - -/* CAN control and status registers */ - -#define STM32_CAN_MCR_OFFSET 0x0000 /* CAN master control register */ -#define STM32_CAN_MSR_OFFSET 0x0004 /* CAN master status register */ -#define STM32_CAN_TSR_OFFSET 0x0008 /* CAN transmit status register */ - -#define STM32_CAN_RFR_OFFSET(m) (0x000c+((m)<<2)) -#define STM32_CAN_RF0R_OFFSET 0x000c /* CAN receive FIFO 0 register */ -#define STM32_CAN_RF1R_OFFSET 0x0010 /* CAN receive FIFO 1 register */ - -#define STM32_CAN_IER_OFFSET 0x0014 /* CAN interrupt enable register */ -#define STM32_CAN_ESR_OFFSET 0x0018 /* CAN error status register */ -#define STM32_CAN_BTR_OFFSET 0x001c /* CAN bit timing register */ - -/* CAN mailbox registers (3 TX and 2 RX) */ - -#define STM32_CAN_TIR_OFFSET(m) (0x0180+((m)<<4)) -#define STM32_CAN_TI0R_OFFSET 0x0180 /* TX mailbox identifier register 0 */ -#define STM32_CAN_TI1R_OFFSET 0x0190 /* TX mailbox identifier register 1 */ -#define STM32_CAN_TI2R_OFFSET 0x01a0 /* TX mailbox identifier register 2 */ - -#define STM32_CAN_TDTR_OFFSET(m) (0x0184+((m)<<4)) -#define STM32_CAN_TDT0R_OFFSET 0x0184 /* Mailbox data length control and time stamp register 0 */ -#define STM32_CAN_TDT1R_OFFSET 0x0194 /* Mailbox data length control and time stamp register 1 */ -#define STM32_CAN_TDT2R_OFFSET 0x01a4 /* Mailbox data length control and time stamp register 2 */ - -#define STM32_CAN_TDLR_OFFSET(m) (0x0188+((m)<<4)) -#define STM32_CAN_TDL0R_OFFSET 0x0188 /* Mailbox data low register 0 */ -#define STM32_CAN_TDL1R_OFFSET 0x0198 /* Mailbox data low register 1 */ -#define STM32_CAN_TDL2R_OFFSET 0x01a8 /* Mailbox data low register 2 */ - -#define STM32_CAN_TDHR_OFFSET(m) (0x018c+((m)<<4)) -#define STM32_CAN_TDH0R_OFFSET 0x018c /* Mailbox data high register 0 */ -#define STM32_CAN_TDH1R_OFFSET 0x019c /* Mailbox data high register 1 */ -#define STM32_CAN_TDH2R_OFFSET 0x01ac /* Mailbox data high register 2 */ - -#define STM32_CAN_RIR_OFFSET(m) (0x01b0+((m)<<4)) -#define STM32_CAN_RI0R_OFFSET 0x01b0 /* Rx FIFO mailbox identifier register 0 */ -#define STM32_CAN_RI1R_OFFSET 0x01c0 /* Rx FIFO mailbox identifier register 1 */ - -#define STM32_CAN_RDTR_OFFSET(m) (0x01b4+((m)<<4)) -#define STM32_CAN_RDT0R_OFFSET 0x01b4 /* Rx FIFO mailbox data length control and time stamp register 0 */ -#define STM32_CAN_RDT1R_OFFSET 0x01c4 /* Rx FIFO mailbox data length control and time stamp register 1 */ - -#define STM32_CAN_RDLR_OFFSET(m) (0x01b8+((m)<<4)) -#define STM32_CAN_RDL0R_OFFSET 0x01b8 /* Receive FIFO mailbox data low register 0 */ -#define STM32_CAN_RDL1R_OFFSET 0x01c8 /* Receive FIFO mailbox data low register 1 */ - -#define STM32_CAN_RDHR_OFFSET(m) (0x01bc+((m)<<4)) -#define STM32_CAN_RDH0R_OFFSET 0x01bc /* Receive FIFO mailbox data high register 0 */ -#define STM32_CAN_RDH1R_OFFSET 0x01cc /* Receive FIFO mailbox data high register 1 */ - -/* CAN filter registers */ - -#define STM32_CAN_FMR_OFFSET 0x0200 /* CAN filter master register */ -#define STM32_CAN_FM1R_OFFSET 0x0204 /* CAN filter mode register */ -#define STM32_CAN_FS1R_OFFSET 0x020c /* CAN filter scale register */ -#define STM32_CAN_FFA1R_OFFSET 0x0214 /* CAN filter FIFO assignment register */ -#define STM32_CAN_FA1R_OFFSET 0x021c /* CAN filter activation register */ - -/* There are 14 or 28 filter banks (depending) on the device. - * Each filter bank is composed of two 32-bit registers, CAN_FiR: - * F0R1 Offset 0x240 - * F0R2 Offset 0x244 - * F1R1 Offset 0x248 - * F1R2 Offset 0x24c - * ... - */ - -#define STM32_CAN_FIR_OFFSET(f,i) (0x240+((f)<<3)+(((i)-1)<<2)) - -/* Register Addresses *******************************************************/ - -#if STM32_NCAN > 0 -# define STM32_CAN1_MCR (STM32_CAN1_BASE+STM32_CAN_MCR_OFFSET) -# define STM32_CAN1_MSR (STM32_CAN1_BASE+STM32_CAN_MSR_OFFSET) -# define STM32_CAN1_TSR (STM32_CAN1_BASE+STM32_CAN_TSR_OFFSET) -# define STM32_CAN1_RF0R (STM32_CAN1_BASE+STM32_CAN_RF0R_OFFSET) -# define STM32_CAN1_RF1R (STM32_CAN1_BASE+STM32_CAN_RF1R_OFFSET) -# define STM32_CAN1_IER (STM32_CAN1_BASE+STM32_CAN_IER_OFFSET) -# define STM32_CAN1_ESR (STM32_CAN1_BASE+STM32_CAN_ESR_OFFSET) -# define STM32_CAN1_BTR (STM32_CAN1_BASE+STM32_CAN_BTR_OFFSET) - -# define STM32_CAN1_TIR(m) (STM32_CAN1_BASE+STM32_CAN_TIR_OFFSET(m)) -# define STM32_CAN1_TI0R (STM32_CAN1_BASE+STM32_CAN_TI0R_OFFSET) -# define STM32_CAN1_TI1R (STM32_CAN1_BASE+STM32_CAN_TI1R_OFFSET) -# define STM32_CAN1_TI2R (STM32_CAN1_BASE+STM32_CAN_TI2R_OFFSET) - -# define STM32_CAN1_TDTR(m) (STM32_CAN1_BASE+STM32_CAN_TDTR_OFFSET(m)) -# define STM32_CAN1_TDT0R (STM32_CAN1_BASE+STM32_CAN_TDT0R_OFFSET) -# define STM32_CAN1_TDT1R (STM32_CAN1_BASE+STM32_CAN_TDT1R_OFFSET) -# define STM32_CAN1_TDT2R (STM32_CAN1_BASE+STM32_CAN_TDT2R_OFFSET) - -# define STM32_CAN1_TDLR(m) (STM32_CAN1_BASE+STM32_CAN_TDLR_OFFSET(m)) -# define STM32_CAN1_TDL0R (STM32_CAN1_BASE+STM32_CAN_TDL0R_OFFSET) -# define STM32_CAN1_TDL1R (STM32_CAN1_BASE+STM32_CAN_TDL1R_OFFSET) -# define STM32_CAN1_TDL2R (STM32_CAN1_BASE+STM32_CAN_TDL2R_OFFSET) - -# define STM32_CAN1_TDHR(m) (STM32_CAN1_BASE+STM32_CAN_TDHR_OFFSET(m)) -# define STM32_CAN1_TDH0R (STM32_CAN1_BASE+STM32_CAN_TDH0R_OFFSET) -# define STM32_CAN1_TDH1R (STM32_CAN1_BASE+STM32_CAN_TDH1R_OFFSET) -# define STM32_CAN1_TDH2R (STM32_CAN1_BASE+STM32_CAN_TDH2R_OFFSET) - -# define STM32_CAN1_RIR(m) (STM32_CAN1_BASE+STM32_CAN_RIR_OFFSET(m)) -# define STM32_CAN1_RI0R (STM32_CAN1_BASE+STM32_CAN_RI0R_OFFSET) -# define STM32_CAN1_RI1R (STM32_CAN1_BASE+STM32_CAN_RI1R_OFFSET) - -# define STM32_CAN1_RDTR(m) (STM32_CAN1_BASE+STM32_CAN_RDTR_OFFSET(m)) -# define STM32_CAN1_RDT0R (STM32_CAN1_BASE+STM32_CAN_RDT0R_OFFSET) -# define STM32_CAN1_RDT1R (STM32_CAN1_BASE+STM32_CAN_RDT1R_OFFSET) - -# define STM32_CAN1_RDLR(m) (STM32_CAN1_BASE+STM32_CAN_RDLR_OFFSET(m)) -# define STM32_CAN1_RDL0R (STM32_CAN1_BASE+STM32_CAN_RDL0R_OFFSET) -# define STM32_CAN1_RDL1R (STM32_CAN1_BASE+STM32_CAN_RDL1R_OFFSET) - -# define STM32_CAN1_RDHR(m) (STM32_CAN1_BASE+STM32_CAN_RDHR_OFFSET(m)) -# define STM32_CAN1_RDH0R (STM32_CAN1_BASE+STM32_CAN_RDH0R_OFFSET) -# define STM32_CAN1_RDH1R (STM32_CAN1_BASE+STM32_CAN_RDH1R_OFFSET) - -# define STM32_CAN1_FMR (STM32_CAN1_BASE+STM32_CAN_FMR_OFFSET) -# define STM32_CAN1_FM1R (STM32_CAN1_BASE+STM32_CAN_FM1R_OFFSET) -# define STM32_CAN1_FS1R (STM32_CAN1_BASE+STM32_CAN_FS1R_OFFSET) -# define STM32_CAN1_FFA1R (STM32_CAN1_BASE+STM32_CAN_FFA1R_OFFSET) -# define STM32_CAN1_FA1R (STM32_CAN1_BASE+STM32_CAN_FA1R_OFFSET) -# define STM32_CAN1_FIR(b,i) (STM32_CAN1_BASE+STM32_CAN_FIR_OFFSET(b,i)) -#endif - -#if STM32_NCAN > 1 -# define STM32_CAN2_MCR (STM32_CAN2_BASE+STM32_CAN_MCR_OFFSET) -# define STM32_CAN2_MSR (STM32_CAN2_BASE+STM32_CAN_MSR_OFFSET) -# define STM32_CAN2_TSR (STM32_CAN2_BASE+STM32_CAN_TSR_OFFSET) -# define STM32_CAN2_RF0R (STM32_CAN2_BASE+STM32_CAN_RF0R_OFFSET) -# define STM32_CAN2_RF1R (STM32_CAN2_BASE+STM32_CAN_RF1R_OFFSET) -# define STM32_CAN2_IER (STM32_CAN2_BASE+STM32_CAN_IER_OFFSET) -# define STM32_CAN2_ESR (STM32_CAN2_BASE+STM32_CAN_ESR_OFFSET) -# define STM32_CAN2_BTR (STM32_CAN2_BASE+STM32_CAN_BTR_OFFSET) - -# define STM32_CAN2_TIR(m) (STM32_CAN2_BASE+STM32_CAN_TIR_OFFSET(m)) -# define STM32_CAN2_TI0R (STM32_CAN2_BASE+STM32_CAN_TI0R_OFFSET) -# define STM32_CAN2_TI1R (STM32_CAN2_BASE+STM32_CAN_TI1R_OFFSET) -# define STM32_CAN2_TI2R (STM32_CAN2_BASE+STM32_CAN_TI2R_OFFSET) - -# define STM32_CAN2_TDTR(m) (STM32_CAN2_BASE+STM32_CAN_TDTR_OFFSET(m)) -# define STM32_CAN2_TDT0R (STM32_CAN2_BASE+STM32_CAN_TDT0R_OFFSET) -# define STM32_CAN2_TDT1R (STM32_CAN2_BASE+STM32_CAN_TDT1R_OFFSET) -# define STM32_CAN2_TDT2R (STM32_CAN2_BASE+STM32_CAN_TDT2R_OFFSET) - -# define STM32_CAN2_TDLR(m) (STM32_CAN2_BASE+STM32_CAN_TDLR_OFFSET(m)) -# define STM32_CAN2_TDL0R (STM32_CAN2_BASE+STM32_CAN_TDL0R_OFFSET) -# define STM32_CAN2_TDL1R (STM32_CAN2_BASE+STM32_CAN_TDL1R_OFFSET) -# define STM32_CAN2_TDL2R (STM32_CAN2_BASE+STM32_CAN_TDL2R_OFFSET) - -# define STM32_CAN2_TDHR(m) (STM32_CAN2_BASE+STM32_CAN_TDHR_OFFSET(m)) -# define STM32_CAN2_TDH0R (STM32_CAN2_BASE+STM32_CAN_TDH0R_OFFSET) -# define STM32_CAN2_TDH1R (STM32_CAN2_BASE+STM32_CAN_TDH1R_OFFSET) -# define STM32_CAN2_TDH2R (STM32_CAN2_BASE+STM32_CAN_TDH2R_OFFSET) - -# define STM32_CAN2_RIR(m) (STM32_CAN2_BASE+STM32_CAN_RIR_OFFSET(m)) -# define STM32_CAN2_RI0R (STM32_CAN2_BASE+STM32_CAN_RI0R_OFFSET) -# define STM32_CAN2_RI1R (STM32_CAN2_BASE+STM32_CAN_RI1R_OFFSET) - -# define STM32_CAN2_RDTR(m) (STM32_CAN2_BASE+STM32_CAN_RDTR_OFFSET(m)) -# define STM32_CAN2_RDT0R (STM32_CAN2_BASE+STM32_CAN_RDT0R_OFFSET) -# define STM32_CAN2_RDT1R (STM32_CAN2_BASE+STM32_CAN_RDT1R_OFFSET) - -# define STM32_CAN2_RDLR(m) (STM32_CAN2_BASE+STM32_CAN_RDLR_OFFSET(m)) -# define STM32_CAN2_RDL0R (STM32_CAN2_BASE+STM32_CAN_RDL0R_OFFSET) -# define STM32_CAN2_RDL1R (STM32_CAN2_BASE+STM32_CAN_RDL1R_OFFSET) - -# define STM32_CAN2_RDHR(m) (STM32_CAN2_BASE+STM32_CAN_RDHR_OFFSET(m)) -# define STM32_CAN2_RDH0R (STM32_CAN2_BASE+STM32_CAN_RDH0R_OFFSET) -# define STM32_CAN2_RDH1R (STM32_CAN2_BASE+STM32_CAN_RDH1R_OFFSET) - -# define STM32_CAN2_FMR (STM32_CAN2_BASE+STM32_CAN_FMR_OFFSET) -# define STM32_CAN2_FM1R (STM32_CAN2_BASE+STM32_CAN_FM1R_OFFSET) -# define STM32_CAN2_FS1R (STM32_CAN2_BASE+STM32_CAN_FS1R_OFFSET) -# define STM32_CAN2_FFA1R (STM32_CAN2_BASE+STM32_CAN_FFA1R_OFFSET) -# define STM32_CAN2_FA1R (STM32_CAN2_BASE+STM32_CAN_FA1R_OFFSET) -# define STM32_CAN2_FIR(b,i) (STM32_CAN2_BASE+STM32_CAN_FIR_OFFSET(b,i)) -#endif - -/* Register Bitfield Definitions ********************************************/ - -/* CAN master control register */ - -#define CAN_MCR_INRQ (1 << 0) /* Bit 0: Initialization Request */ -#define CAN_MCR_SLEEP (1 << 1) /* Bit 1: Sleep Mode Request */ -#define CAN_MCR_TXFP (1 << 2) /* Bit 2: Transmit FIFO Priority */ -#define CAN_MCR_RFLM (1 << 3) /* Bit 3: Receive FIFO Locked Mode */ -#define CAN_MCR_NART (1 << 4) /* Bit 4: No Automatic Retransmission */ -#define CAN_MCR_AWUM (1 << 5) /* Bit 5: Automatic Wakeup Mode */ -#define CAN_MCR_ABOM (1 << 6) /* Bit 6: Automatic Bus-Off Management */ -#define CAN_MCR_TTCM (1 << 7) /* Bit 7: Time Triggered Communication Mode Enable */ -#define CAN_MCR_RESET (1 << 15) /* Bit 15: bxCAN software master reset */ -#define CAN_MCR_DBF (1 << 16) /* Bit 16: Debug freeze */ - -/* CAN master status register */ - -#define CAN_MSR_INAK (1 << 0) /* Bit 0: Initialization Acknowledge */ -#define CAN_MSR_SLAK (1 << 1) /* Bit 1: Sleep Acknowledge */ -#define CAN_MSR_ERRI (1 << 2) /* Bit 2: Error Interrupt */ -#define CAN_MSR_WKUI (1 << 3) /* Bit 3: Wakeup Interrupt */ -#define CAN_MSR_SLAKI (1 << 4) /* Bit 4: Sleep acknowledge interrupt */ -#define CAN_MSR_TXM (1 << 8) /* Bit 8: Transmit Mode */ -#define CAN_MSR_RXM (1 << 9) /* Bit 9: Receive Mode */ -#define CAN_MSR_SAMP (1 << 10) /* Bit 10: Last Sample Point */ -#define CAN_MSR_RX (1 << 11) /* Bit 11: CAN Rx Signal */ - -/* CAN transmit status register */ - -#define CAN_TSR_RQCP0 (1 << 0) /* Bit 0: Request Completed Mailbox 0 */ -#define CAN_TSR_TXOK0 (1 << 1) /* Bit 1 : Transmission OK of Mailbox 0 */ -#define CAN_TSR_ALST0 (1 << 2) /* Bit 2 : Arbitration Lost for Mailbox 0 */ -#define CAN_TSR_TERR0 (1 << 3) /* Bit 3 : Transmission Error of Mailbox 0 */ -#define CAN_TSR_ABRQ0 (1 << 7) /* Bit 7 : Abort Request for Mailbox 0 */ -#define CAN_TSR_RQCP1 (1 << 8) /* Bit 8 : Request Completed Mailbox 1 */ -#define CAN_TSR_TXOK1 (1 << 9) /* Bit 9 : Transmission OK of Mailbox 1 */ -#define CAN_TSR_ALST1 (1 << 10) /* Bit 10 : Arbitration Lost for Mailbox 1 */ -#define CAN_TSR_TERR1 (1 << 11) /* Bit 11 : Transmission Error of Mailbox 1 */ -#define CAN_TSR_ABRQ1 (1 << 15) /* Bit 15 : Abort Request for Mailbox 1 */ -#define CAN_TSR_RQCP2 (1 << 16) /* Bit 16 : Request Completed Mailbox 2 */ -#define CAN_TSR_TXOK2 (1 << 17) /* Bit 17 : Transmission OK of Mailbox 2 */ -#define CAN_TSR_ALST2 (1 << 18) /* Bit 18: Arbitration Lost for Mailbox 2 */ -#define CAN_TSR_TERR2 (1 << 19) /* Bit 19: Transmission Error of Mailbox 2 */ -#define CAN_TSR_ABRQ2 (1 << 23) /* Bit 23: Abort Request for Mailbox 2 */ -#define CAN_TSR_CODE_SHIFT (24) /* Bits 25-24: Mailbox Code */ -#define CAN_TSR_CODE_MASK (3 << CAN_TSR_CODE_SHIFT) -#define CAN_TSR_TME0 (1 << 26) /* Bit 26: Transmit Mailbox 0 Empty */ -#define CAN_TSR_TME1 (1 << 27) /* Bit 27: Transmit Mailbox 1 Empty */ -#define CAN_TSR_TME2 (1 << 28) /* Bit 28: Transmit Mailbox 2 Empty */ -#define CAN_TSR_LOW0 (1 << 29) /* Bit 29: Lowest Priority Flag for Mailbox 0 */ -#define CAN_TSR_LOW1 (1 << 30) /* Bit 30: Lowest Priority Flag for Mailbox 1 */ -#define CAN_TSR_LOW2 (1 << 31) /* Bit 31: Lowest Priority Flag for Mailbox 2 */ - -/* CAN receive FIFO 0/1 registers */ - -#define CAN_RFR_FMP_SHIFT (0) /* Bits 1-0: FIFO Message Pending */ -#define CAN_RFR_FMP_MASK (3 << CAN_RFR_FMP_SHIFT) -#define CAN_RFR_FULL (1 << 3) /* Bit 3: FIFO 0 Full */ -#define CAN_RFR_FOVR (1 << 4) /* Bit 4: FIFO 0 Overrun */ -#define CAN_RFR_RFOM (1 << 5) /* Bit 5: Release FIFO 0 Output Mailbox */ - -/* CAN interrupt enable register */ - -#define CAN_IER_TMEIE (1 << 0) /* Bit 0: Transmit Mailbox Empty Interrupt Enable */ -#define CAN_IER_FMPIE0 (1 << 1) /* Bit 1: FIFO Message Pending Interrupt Enable */ -#define CAN_IER_FFIE0 (1 << 2) /* Bit 2: FIFO Full Interrupt Enable */ -#define CAN_IER_FOVIE0 (1 << 3) /* Bit 3: FIFO Overrun Interrupt Enable */ -#define CAN_IER_FMPIE1 (1 << 4) /* Bit 4: FIFO Message Pending Interrupt Enable */ -#define CAN_IER_FFIE1 (1 << 5) /* Bit 5: FIFO Full Interrupt Enable */ -#define CAN_IER_FOVIE1 (1 << 6) /* Bit 6: FIFO Overrun Interrupt Enable */ -#define CAN_IER_EWGIE (1 << 8) /* Bit 8: Error Warning Interrupt Enable */ -#define CAN_IER_EPVIE (1 << 9) /* Bit 9: Error Passive Interrupt Enable */ -#define CAN_IER_BOFIE (1 << 10) /* Bit 10: Bus-Off Interrupt Enable */ -#define CAN_IER_LECIE (1 << 11) /* Bit 11: Last Error Code Interrupt Enable */ -#define CAN_IER_ERRIE (1 << 15) /* Bit 15: Error Interrupt Enable */ -#define CAN_IER_WKUIE (1 << 16) /* Bit 16: Wakeup Interrupt Enable */ -#define CAN_IER_SLKIE (1 << 17) /* Bit 17: Sleep Interrupt Enable */ - -/* CAN error status register */ - -#define CAN_ESR_EWGF (1 << 0) /* Bit 0: Error Warning Flag */ -#define CAN_ESR_EPVF (1 << 1) /* Bit 1: Error Passive Flag */ -#define CAN_ESR_BOFF (1 << 2) /* Bit 2: Bus-Off Flag */ -#define CAN_ESR_LEC_SHIFT (4) /* Bits 6-4: Last Error Code */ -#define CAN_ESR_LEC_MASK (7 << CAN_ESR_LEC_SHIFT) -# define CAN_ESR_NOERROR (0 << CAN_ESR_LEC_SHIFT) /* 000: No Error */ -# define CAN_ESR_STUFFERROR (1 << CAN_ESR_LEC_SHIFT) /* 001: Stuff Error */ -# define CAN_ESR_FORMERROR (2 << CAN_ESR_LEC_SHIFT) /* 010: Form Error */ -# define CAN_ESR_ACKERROR (3 << CAN_ESR_LEC_SHIFT) /* 011: Acknowledgment Error */ -# define CAN_ESR_BRECERROR (4 << CAN_ESR_LEC_SHIFT) /* 100: Bit recessive Error */ -# define CAN_ESR_BDOMERROR (5 << CAN_ESR_LEC_SHIFT) /* 101: Bit dominant Error */ -# define CAN_ESR_CRCERRPR (6 << CAN_ESR_LEC_SHIFT) /* 110: CRC Error */ -# define CAN_ESR_SWERROR (7 << CAN_ESR_LEC_SHIFT) /* 111: Set by software */ - -#define CAN_ESR_TEC_SHIFT (16) /* Bits 23-16: LS byte of the 9-bit Transmit Error Counter */ -#define CAN_ESR_TEC_MASK (0xff << CAN_ESR_TEC_SHIF) -#define CAN_ESR_REC_SHIFT (24) /* Bits 31-24: Receive Error Counter */ -#define CAN_ESR_REC_MASK (0xff << CAN_ESR_REC_SHIFT) - -/* CAN bit timing register */ - -#define CAN_BTR_BRP_SHIFT (0) /* Bits 9-0: Baud Rate Prescaler */ -#define CAN_BTR_BRP_MASK (0x03ff << CAN_BTR_BRP_SHIFT) -#define CAN_BTR_TS1_SHIFT (16) /* Bits 19-16: Time Segment 1 */ -#define CAN_BTR_TS1_MASK (0x0f << CAN_BTR_TS1_SHIFT) -#define CAN_BTR_TS2_SHIFT (20) /* Bits 22-20: Time Segment 2 */ -#define CAN_BTR_TS2_MASK (7 << CAN_BTR_TS2_SHIFT) -#define CAN_BTR_SJW_SHIFT (24) /* Bits 25-24: Resynchronization Jump Width */ -#define CAN_BTR_SJW_MASK (3 << CAN_BTR_SJW_SHIFT) -#define CAN_BTR_LBKM (1 << 30) /* Bit 30: Loop Back Mode (Debug) */ -#define CAN_BTR_SILM (1ul << 31) /* Bit 31: Silent Mode (Debug) */ - -#define CAN_BTR_BRP_MAX (1024) /* Maximum BTR value (without decrement) */ -#define CAN_BTR_TSEG1_MAX (16) /* Maximum TSEG1 value (without decrement) */ -#define CAN_BTR_TSEG2_MAX (8) /* Maximum TSEG2 value (without decrement) */ - -/* TX mailbox identifier register */ - -#define CAN_TIR_TXRQ (1 << 0) /* Bit 0: Transmit Mailbox Request */ -#define CAN_TIR_RTR (1 << 1) /* Bit 1: Remote Transmission Request */ -#define CAN_TIR_IDE (1 << 2) /* Bit 2: Identifier Extension */ -#define CAN_TIR_EXID_SHIFT (3) /* Bit 3-31: Extended Identifier */ -#define CAN_TIR_EXID_MASK (0x1fffffff << CAN_TIR_EXID_SHIFT) -#define CAN_TIR_STID_SHIFT (21) /* Bits 21-31: Standard Identifier */ -#define CAN_TIR_STID_MASK (0x07ff << CAN_TIR_STID_SHIFT) - -/* Mailbox data length control and time stamp register */ - -#define CAN_TDTR_DLC_SHIFT (0) /* Bits 3:0: Data Length Code */ -#define CAN_TDTR_DLC_MASK (0x0f << CAN_TDTR_DLC_SHIFT) -#define CAN_TDTR_TGT (1 << 8) /* Bit 8: Transmit Global Time */ -#define CAN_TDTR_TIME_SHIFT (16) /* Bits 31:16: Message Time Stamp */ -#define CAN_TDTR_TIME_MASK (0xffff << CAN_TDTR_TIME_SHIFT) - -/* Mailbox data low register */ - -#define CAN_TDLR_DATA0_SHIFT (0) /* Bits 7-0: Data Byte 0 */ -#define CAN_TDLR_DATA0_MASK (0xff << CAN_TDLR_DATA0_SHIFT) -#define CAN_TDLR_DATA1_SHIFT (8) /* Bits 15-8: Data Byte 1 */ -#define CAN_TDLR_DATA1_MASK (0xff << CAN_TDLR_DATA1_SHIFT) -#define CAN_TDLR_DATA2_SHIFT (16) /* Bits 23-16: Data Byte 2 */ -#define CAN_TDLR_DATA2_MASK (0xff << CAN_TDLR_DATA2_SHIFT) -#define CAN_TDLR_DATA3_SHIFT (24) /* Bits 31-24: Data Byte 3 */ -#define CAN_TDLR_DATA3_MASK (0xff << CAN_TDLR_DATA3_SHIFT) - -/* Mailbox data high register */ - -#define CAN_TDHR_DATA4_SHIFT (0) /* Bits 7-0: Data Byte 4 */ -#define CAN_TDHR_DATA4_MASK (0xff << CAN_TDHR_DATA4_SHIFT) -#define CAN_TDHR_DATA5_SHIFT (8) /* Bits 15-8: Data Byte 5 */ -#define CAN_TDHR_DATA5_MASK (0xff << CAN_TDHR_DATA5_SHIFT) -#define CAN_TDHR_DATA6_SHIFT (16) /* Bits 23-16: Data Byte 6 */ -#define CAN_TDHR_DATA6_MASK (0xff << CAN_TDHR_DATA6_SHIFT) -#define CAN_TDHR_DATA7_SHIFT (24) /* Bits 31-24: Data Byte 7 */ -#define CAN_TDHR_DATA7_MASK (0xff << CAN_TDHR_DATA7_SHIFT) - -/* Rx FIFO mailbox identifier register */ - -#define CAN_RIR_RTR (1 << 1) /* Bit 1: Remote Transmission Request */ -#define CAN_RIR_IDE (1 << 2) /* Bit 2: Identifier Extension */ -#define CAN_RIR_EXID_SHIFT (3) /* Bit 3-31: Extended Identifier */ -#define CAN_RIR_EXID_MASK (0x1fffffff << CAN_RIR_EXID_SHIFT) -#define CAN_RIR_STID_SHIFT (21) /* Bits 21-31: Standard Identifier */ -#define CAN_RIR_STID_MASK (0x07ff << CAN_RIR_STID_SHIFT) - -/* Receive FIFO mailbox data length control and time stamp register */ - -#define CAN_RDTR_DLC_SHIFT (0) /* Bits 3:0: Data Length Code */ -#define CAN_RDTR_DLC_MASK (0x0f << CAN_RDTR_DLC_SHIFT) -#define CAN_RDTR_FM_SHIFT (8) /* Bits 15-8: Filter Match Index */ -#define CAN_RDTR_FM_MASK (0xff << CAN_RDTR_FM_SHIFT) -#define CAN_RDTR_TIME_SHIFT (16) /* Bits 31:16: Message Time Stamp */ -#define CAN_RDTR_TIME_MASK (0xffff << CAN_RDTR_TIME_SHIFT) - -/* Receive FIFO mailbox data low register */ - -#define CAN_RDLR_DATA0_SHIFT (0) /* Bits 7-0: Data Byte 0 */ -#define CAN_RDLR_DATA0_MASK (0xff << CAN_RDLR_DATA0_SHIFT) -#define CAN_RDLR_DATA1_SHIFT (8) /* Bits 15-8: Data Byte 1 */ -#define CAN_RDLR_DATA1_MASK (0xff << CAN_RDLR_DATA1_SHIFT) -#define CAN_RDLR_DATA2_SHIFT (16) /* Bits 23-16: Data Byte 2 */ -#define CAN_RDLR_DATA2_MASK (0xff << CAN_RDLR_DATA2_SHIFT) -#define CAN_RDLR_DATA3_SHIFT (24) /* Bits 31-24: Data Byte 3 */ -#define CAN_RDLR_DATA3_MASK (0xff << CAN_RDLR_DATA3_SHIFT) - -/* Receive FIFO mailbox data high register */ - -#define CAN_RDHR_DATA4_SHIFT (0) /* Bits 7-0: Data Byte 4 */ -#define CAN_RDHR_DATA4_MASK (0xff << CAN_RDHR_DATA4_SHIFT) -#define CAN_RDHR_DATA5_SHIFT (8) /* Bits 15-8: Data Byte 5 */ -#define CAN_RDHR_DATA5_MASK (0xff << CAN_RDHR_DATA5_SHIFT) -#define CAN_RDHR_DATA6_SHIFT (16) /* Bits 23-16: Data Byte 6 */ -#define CAN_RDHR_DATA6_MASK (0xff << CAN_RDHR_DATA6_SHIFT) -#define CAN_RDHR_DATA7_SHIFT (24) /* Bits 31-24: Data Byte 7 */ -#define CAN_RDHR_DATA7_MASK (0xff << CAN_RDHR_DATA7_SHIFT) - -/* CAN filter master register */ - -#define CAN_FMR_FINIT (1 << 0) /* Bit 0: Filter Init Mode */ -#if defined(CONFIG_STM32_CONNECTIVITYLINE) || defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) -# define CAN_FMR_CAN2SB_SHIFT (8) /* Bits 13-8: CAN2 start bank */ -# define CAN_FMR_CAN2SB_MASK (0x3f << CAN_FMR_CAN2SB_SHIFT) -#endif - -/* CAN filter mode register */ - -#if defined(CONFIG_STM32_CONNECTIVITYLINE) || defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) -# define CAN_FM1R_FBM_SHIFT (0) /* Bits 13:0: Filter Mode */ -# define CAN_FM1R_FBM_MASK (0x3fff << CAN_FM1R_FBM_SHIFT) -#else -# define CAN_FM1R_FBM_SHIFT (0) /* Bits 27:0: Filter Mode */ -# define CAN_FM1R_FBM_MASK (0x0fffffff << CAN_FM1R_FBM_SHIFT) -#endif - -/* CAN filter scale register */ - -#if defined(CONFIG_STM32_CONNECTIVITYLINE) || defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) -# define CAN_FS1R_FSC_SHIFT (0) /* Bits 13:0: Filter Scale Configuration */ -# define CAN_FS1R_FSC_MASK (0x3fff << CAN_FS1R_FSC_SHIFT) -#else -# define CAN_FS1R_FSC_SHIFT (0) /* Bits 27:0: Filter Scale Configuration */ -# define CAN_FS1R_FSC_MASK (0x0fffffff << CAN_FS1R_FSC_SHIFT) -#endif - -/* CAN filter FIFO assignment register */ - -#if defined(CONFIG_STM32_CONNECTIVITYLINE) || defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) -# define CAN_FFA1R_FFA_SHIFT (0) /* Bits 13:0: Filter FIFO Assignment */ -# define CAN_FFA1R_FFA_MASK (0x3fff << CAN_FFA1R_FFA_SHIFT) -#else -# define CAN_FFA1R_FFA_SHIFT (0) /* Bits 27:0: Filter FIFO Assignment */ -# define CAN_FFA1R_FFA_MASK (0x0fffffff << CAN_FFA1R_FFA_SHIFT) -#endif - -/* CAN filter activation register */ - -#if defined(CONFIG_STM32_CONNECTIVITYLINE) || defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) -# define CAN_FA1R_FACT_SHIFT (0) /* Bits 13:0: Filter Active */ -# define CAN_FA1R_FACT_MASK (0x3fff << CAN_FA1R_FACT_SHIFT) -#else -# define CAN_FA1R_FACT_SHIFT (0) /* Bits 27:0: Filter Active */ -# define CAN_FA1R_FACT_MASK (0x0fffffff << CAN_FA1R_FACT_SHIFT) -#endif - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/**************************************************************************** - * Public Functions Prototypes - ****************************************************************************/ - -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_CAN_H */ diff --git a/arch/arm/src/stm32/hardware/stm32_comp.h b/arch/arm/src/stm32/hardware/stm32_comp.h deleted file mode 100644 index 414f7e62739eb..0000000000000 --- a/arch/arm/src/stm32/hardware/stm32_comp.h +++ /dev/null @@ -1,60 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/hardware/stm32_comp.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_COMP_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_COMP_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "chip.h" - -#ifdef CONFIG_STM32_COMP - -/* Include the correct COMP register definitions for - * selected STM32 COMP IP core: - */ - -/* If more than one COMP IP ensure that only one is selected */ - -#if defined(CONFIG_STM32_HAVE_IP_COMP_V1) -# if defined(CONFIG_STM32_STM32F33XX) -# include "stm32f33xxx_comp.h" -# else -# error "Device not supported." -# endif -#elif defined(CONFIG_STM32_HAVE_IP_COMP_V2) -# if defined(CONFIG_STM32_STM32G4XXX) -# include "stm32g4xxxx_comp.h" -# else -# error "Device not supported." -# endif -#else -# error "STM32 COMP IP not supported." -#endif - -#endif /* CONFIG_STM32_COMP */ - -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_COMP_H */ diff --git a/arch/arm/src/stm32/hardware/stm32_dac.h b/arch/arm/src/stm32/hardware/stm32_dac.h deleted file mode 100644 index b04b56b3d16ff..0000000000000 --- a/arch/arm/src/stm32/hardware/stm32_dac.h +++ /dev/null @@ -1,56 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/hardware/stm32_dac.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_DAC_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_DAC_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "chip.h" - -/* There are 2 main types of DAC IP cores among STM32 chips: - * 1. STM32 DAC IPv1: F1, F2, F3, F4, F7, L1, L4 - * 2. STM32 DAC IPv2: G4 - */ - -#if defined(CONFIG_STM32_HAVE_IP_DAC_V1) && \ - defined(CONFIG_STM32_HAVE_IP_DAC_V2) -# error Only one STM32 DAC IP version must be selected -#endif - -#if defined(CONFIG_STM32_HAVE_IP_DAC_V1) -# include "stm32_dac_v1.h" -#elif defined(CONFIG_STM32_HAVE_IP_DAC_V2) -# if defined(CONFIG_STM32_STM32G4XXX) -# include "stm32gxxxxx_dac.h" /* Special case for G4 */ -# else -# error "STM32 DAC device not supported" -# endif -#else -# error "STM32 DAC IP version not specified" -#endif - -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_DAC_H */ diff --git a/arch/arm/src/stm32/hardware/stm32_dbgmcu.h b/arch/arm/src/stm32/hardware/stm32_dbgmcu.h deleted file mode 100644 index d1b6946f8bdc3..0000000000000 --- a/arch/arm/src/stm32/hardware/stm32_dbgmcu.h +++ /dev/null @@ -1,197 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/hardware/stm32_dbgmcu.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_DBGMCU_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_DBGMCU_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "chip.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Register Addresses *******************************************************/ - -#define STM32_DBGMCU_IDCODE 0xe0042000 /* MCU identifier */ -#define STM32_DBGMCU_CR 0xe0042004 /* MCU debug */ -#ifdef CONFIG_STM32_HAVE_IP_DBGMCU_V2 -# define STM32_DBGMCU_APB1_FZ 0xe0042008 /* Debug MCU APB1 freeze register */ -# define STM32_DBGMCU_APB2_FZ 0xe004200c /* Debug MCU APB2 freeze register */ -#endif -#ifdef CONFIG_STM32_HAVE_IP_DBGMCU_V3 -# define STM32_DBGMCU_APB1_FZ1 0xe0042008 /* Debug MCU APB1 freeze 1 register */ -# define STM32_DBGMCU_APB1_FZ2 0xe004200c /* Debug MCU APB1 freeze 2 register */ -# define STM32_DBGMCU_APB2_FZ 0xe0042010 /* Debug MCU APB2 freeze register */ -#endif - -/* Register Bitfield Definitions ********************************************/ - -/* MCU identifier */ - -#define DBGMCU_IDCODE_DEVID_SHIFT (0) /* Bits 11-0: Device Identifier */ -#define DBGMCU_IDCODE_DEVID_MASK (0x0fff << DBGMCU_IDCODE_DEVID_SHIFT) -#define DBGMCU_IDCODE_REVID_SHIFT (16) /* Bits 31-16: Revision Identifier */ -#define DBGMCU_IDCODE_REVID_MASK (0xffff << DBGMCU_IDCODE_REVID_SHIFT) - -/* MCU debug */ - -#define DBGMCU_CR_SLEEP (1 << 0) /* Bit 0: Debug Sleep Mode */ -#define DBGMCU_CR_STOP (1 << 1) /* Bit 1: Debug Stop Mode */ -#define DBGMCU_CR_STANDBY (1 << 2) /* Bit 2: Debug Standby mode */ -#define DBGMCU_CR_TRACEIOEN (1 << 5) /* Bit 5: Trace enabled */ - -#define DBGMCU_CR_TRACEMODE_SHIFT (6) /* Bits 7-6: Trace mode pin assignment */ -#define DBGMCU_CR_TRACEMODE_MASK (3 << DBGMCU_CR_TRACEMODE_SHIFT) -# define DBGMCU_CR_ASYNCH (0 << DBGMCU_CR_TRACEMODE_SHIFT) /* Asynchronous Mode */ -# define DBGMCU_CR_SYNCH1 (1 << DBGMCU_CR_TRACEMODE_SHIFT) /* Synchronous Mode, TRACEDATA size=1 */ -# define DBGMCU_CR_SYNCH2 (2 << DBGMCU_CR_TRACEMODE_SHIFT) /* Synchronous Mode, TRACEDATA size=2 */ -# define DBGMCU_CR_SYNCH4 (3 << DBGMCU_CR_TRACEMODE_SHIFT) /* Synchronous Mode, TRACEDATA size=4 */ - -#ifdef CONFIG_STM32_HAVE_IP_DBGMCU_V1 -# define DBGMCU_CR_IWDGSTOP (1 << 8) /* Bit 8: Independent Watchdog stopped when core is halted */ -# define DBGMCU_CR_WWDGSTOP (1 << 9) /* Bit 9: Window Watchdog stopped when core is halted */ -# define DBGMCU_CR_TIM1STOP (1 << 10) /* Bit 10: TIM1 stopped when core is halted */ -# define DBGMCU_CR_TIM2STOP (1 << 11) /* Bit 11: TIM2 stopped when core is halted */ -# define DBGMCU_CR_TIM3STOP (1 << 12) /* Bit 12: TIM3 stopped when core is halted */ -# define DBGMCU_CR_TIM4STOP (1 << 13) /* Bit 13: TIM4 stopped when core is halted */ -# define DBGMCU_CR_CAN1STOP (1 << 14) /* Bit 14: CAN1 stopped when core is halted */ -# define DBGMCU_CR_SMBUS1STOP (1 << 15) /* Bit 15: I2C1 SMBUS timeout mode stopped when core is halted */ -# define DBGMCU_CR_SMBUS2STOP (1 << 16) /* Bit 16: I2C2 SMBUS timeout mode stopped when core is halted */ -# define DBGMCU_CR_TIM8STOP (1 << 17) /* Bit 17: TIM8 stopped when core is halted */ -# define DBGMCU_CR_TIM5STOP (1 << 18) /* Bit 18: TIM5 stopped when core is halted */ -# define DBGMCU_CR_TIM6STOP (1 << 19) /* Bit 19: TIM6 stopped when core is halted */ -# define DBGMCU_CR_TIM7STOP (1 << 20) /* Bit 20: TIM7 stopped when core is halted */ -# define DBGMCU_CR_CAN2STOP (1 << 21) /* Bit 21: CAN2 stopped when core is halted */ -#endif /* CONFIG_STM32_HAVE_IP_DBGMCU_V1 */ - -#ifdef CONFIG_STM32_HAVE_IP_DBGMCU_V2 - -/* Debug MCU APB1 freeze register */ - -#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) -# define DBGMCU_APB1_TIM2STOP (1 << 0) /* Bit 0: TIM2 stopped when core is halted */ -# define DBGMCU_APB1_TIM3STOP (1 << 1) /* Bit 1: TIM3 stopped when core is halted */ -# define DBGMCU_APB1_TIM4STOP (1 << 2) /* Bit 2: TIM4 stopped when core is halted */ -# define DBGMCU_APB1_TIM5STOP (1 << 3) /* Bit 3: TIM5 stopped when core is halted */ -# define DBGMCU_APB1_TIM6STOP (1 << 4) /* Bit 4: TIM6 stopped when core is halted */ -# define DBGMCU_APB1_TIM7STOP (1 << 5) /* Bit 5: TIM7 stopped when core is halted */ -# define DBGMCU_APB1_TIM12STOP (1 << 6) /* Bit 6: TIM12 stopped when core is halted */ -# define DBGMCU_APB1_TIM13STOP (1 << 7) /* Bit 7: TIM13 stopped when core is halted */ -# define DBGMCU_APB1_TIM14STOP (1 << 8) /* Bit 7: TIM14 stopped when core is halted */ -# define DBGMCU_APB1_RTCSTOP (1 << 10) /* Bit 10: RTC stopped when Core is halted */ -# define DBGMCU_APB1_WWDGSTOP (1 << 11) /* Bit 11: Window Watchdog stopped when core is halted */ -# define DBGMCU_APB1_IWDGSTOP (1 << 12) /* Bit 12: Independent Watchdog stopped when core is halted */ -# define DBGMCU_APB1_I2C1STOP (1 << 21) /* Bit 21: SMBUS timeout mode stopped when Core is halted */ -# define DBGMCU_APB1_I2C2STOP (1 << 22) /* Bit 22: SMBUS timeout mode stopped when Core is halted */ -# define DBGMCU_APB1_I2C3STOP (1 << 23) /* Bit 23: SMBUS timeout mode stopped when Core is halted */ -# define DBGMCU_APB1_CAN1STOP (1 << 25) /* Bit 25: CAN1 stopped when core is halted */ -# define DBGMCU_APB1_CAN2STOP (1 << 26) /* Bit 26: CAN2 stopped when core is halted */ -#elif defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) || \ - defined(CONFIG_STM32_STM32L15XX) -# define DBGMCU_APB1_TIM2STOP (1 << 0) /* Bit 0: TIM2 stopped when core is halted */ -# define DBGMCU_APB1_TIM3STOP (1 << 1) /* Bit 1: TIM3 stopped when core is halted */ -# define DBGMCU_APB1_TIM4STOP (1 << 2) /* Bit 2: TIM4 stopped when core is halted */ -# define DBGMCU_APB1_TIM6STOP (1 << 4) /* Bit 4: TIM6 stopped when core is halted */ -# define DBGMCU_APB1_TIM7STOP (1 << 5) /* Bit 5: TIM7 stopped when core is halted */ -# define DBGMCU_APB1_RTCSTOP (1 << 10) /* Bit 10: RTC stopped when Core is halted */ -# define DBGMCU_APB1_WWDGSTOP (1 << 11) /* Bit 11: Window Watchdog stopped when core is halted */ -# define DBGMCU_APB1_IWDGSTOP (1 << 12) /* Bit 12: Independent Watchdog stopped when core is halted */ -# define DBGMCU_APB1_I2C1STOP (1 << 21) /* Bit 21: SMBUS timeout mode stopped when Core is halted */ -# define DBGMCU_APB1_I2C2STOP (1 << 22) /* Bit 22: SMBUS timeout mode stopped when Core is halted */ -# if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) -# define DBGMCU_APB1_CAN1STOP (1 << 25) /* Bit 25: CAN1 stopped when core is halted */ -# endif -#endif - -/* Debug MCU APB2 freeze register */ - -#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) -# define DBGMCU_APB2_TIM1STOP (1 << 0) /* Bit 0: TIM1 stopped when core is halted */ -# define DBGMCU_APB2_TIM8STOP (1 << 1) /* Bit 1: TIM8 stopped when core is halted */ -# define DBGMCU_APB2_TIM9STOP (1 << 16) /* Bit 16: TIM9 stopped when core is halted */ -# define DBGMCU_APB2_TIM10STOP (1 << 17) /* Bit 17: TIM10 stopped when core is halted */ -# define DBGMCU_APB2_TIM11STOP (1 << 18) /* Bit 18: TIM11 stopped when core is halted */ -#elif defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) -# define DBGMCU_APB2_TIM1STOP (1 << 0) /* Bit 0: TIM1 stopped when core is halted */ -# define DBGMCU_APB2_TIM8STOP (1 << 1) /* Bit 1: TIM8 stopped when core is halted */ -# define DBGMCU_APB2_TIM15STOP (1 << 2) /* Bit 2: TIM15 stopped when core is halted */ -# define DBGMCU_APB2_TIM16STOP (1 << 3) /* Bit 3: TIM16 stopped when core is halted */ -# define DBGMCU_APB2_TIM17STOP (1 << 4) /* Bit 4: TIM17 stopped when core is halted */ -#elif defined(CONFIG_STM32_STM32L15XX) -# define DBGMCU_APB2_TIM9STOP (1 << 2) /* Bit 2: TIM9 stopped when core is halted */ -# define DBGMCU_APB2_TIM10STOP (1 << 3) /* Bit 3: TIM10 stopped when core is halted */ -# define DBGMCU_APB2_TIM11STOP (1 << 4) /* Bit 4: TIM11 stopped when core is halted */ -#endif -#endif /* CONFIG_STM32_HAVE_IP_DBGMCU_V2 */ - -#ifdef CONFIG_STM32_HAVE_IP_DBGMCU_V3 - -/* Debug MCU APB1 freeze 1 register */ - -# define DBGMCU_APB1FZ1_TIM2STOP (1 << 0) /* Bit 0: TIM2 stopped when core is halted */ -# define DBGMCU_APB1FZ1_TIM3STOP (1 << 1) /* Bit 1: TIM3 stopped when core is halted */ -# define DBGMCU_APB1FZ1_TIM4STOP (1 << 2) /* Bit 2: TIM4 stopped when core is halted */ -# define DBGMCU_APB1FZ1_TIM6STOP (1 << 4) /* Bit 4: TIM6 stopped when core is halted */ -# define DBGMCU_APB1FZ1_TIM7STOP (1 << 5) /* Bit 5: TIM7 stopped when core is halted */ -# define DBGMCU_APB1FZ1_RTCSTOP (1 << 10) /* Bit 10: RTC stopped when Core is halted */ -# define DBGMCU_APB1FZ1_WWDGSTOP (1 << 11) /* Bit 11: Window Watchdog stopped when core is halted */ -# define DBGMCU_APB1FZ1_IWDGSTOP (1 << 12) /* Bit 12: Independent Watchdog stopped when core is halted */ -# define DBGMCU_APB1FZ1_I2C1STOP (1 << 21) /* Bit 21: SMBUS timeout mode stopped when Core is halted */ -# define DBGMCU_APB1FZ1_I2C2STOP (1 << 22) /* Bit 22: SMBUS timeout mode stopped when Core is halted */ -# define DBGMCU_APB1FZ1_I2C3STOP (1 << 30) /* Bit 30: SMBUS timeout mode stopped when Core is halted */ -# define DBGMCU_APB1FZ1_LPTIM1STOP (1 << 31) /* Bit 31: LPTIM1 counter stopped when Core is halted */ - -/* Debug MCU APB1 freeze 2 register */ - -# define DBGMCU_APB1FZ2_I2C4STOP (1 << 1) /* Bit 30: SMBUS timeout mode stopped when Core is halted */ - -/* Debug MCU APB2 freeze register */ - -# define DBGMCU_APB2_TIM1STOP (1 << 11) /* Bit 11: TIM1 stopped when core is halted */ -# define DBGMCU_APB2_TIM8STOP (1 << 13) /* Bit 14: TIM8 stopped when core is halted */ -# define DBGMCU_APB2_TIM15STOP (1 << 16) /* Bit 16: TIM15 stopped when core is halted */ -# define DBGMCU_APB2_TIM16STOP (1 << 17) /* Bit 17: TIM16 stopped when core is halted */ -# define DBGMCU_APB2_TIM17STOP (1 << 18) /* Bit 18: TIM17 stopped when core is halted */ -# define DBGMCU_APB2_TIM20STOP (1 << 20) /* Bit 20: TIM20 stopped when core is halted */ -# define DBGMCU_APB2_HRTIMSTOP (1 << 26) /* Bit 20: HRTIM stopped when core is halted */ - -#endif /* CONFIG_STM32_HAVE_IP_DBGMCU_V3 */ - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/**************************************************************************** - * Public Functions Prototypes - ****************************************************************************/ - -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_DBGMCU_H */ diff --git a/arch/arm/src/stm32/hardware/stm32_dma.h b/arch/arm/src/stm32/hardware/stm32_dma.h deleted file mode 100644 index a34478f90294c..0000000000000 --- a/arch/arm/src/stm32/hardware/stm32_dma.h +++ /dev/null @@ -1,52 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/hardware/stm32_dma.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_DMA_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_DMA_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "chip.h" - -/* Include the correct DMA register definitions for - * selected STM32 DMA IP core: - * - STM32 DMA IP version 1 - F0, F1, F3, G4, L0, L1, L4 - * - STM32 DMA IP version 2 - F2, F4, F7, H7 - */ - -#if defined(CONFIG_STM32_HAVE_IP_DMA_V1) && defined(CONFIG_STM32_HAVE_IP_DMA_V2) -# error Only one STM32 DMA IP version must be selected -#endif - -#if defined(CONFIG_STM32_HAVE_IP_DMA_V1) -# include "stm32_dma_v1.h" -#elif defined(CONFIG_STM32_HAVE_IP_DMA_V2) -# include "stm32_dma_v2.h" -#else -# error "STM32 DMA IP version not specified" -#endif - -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_DMA_H */ diff --git a/arch/arm/src/stm32/hardware/stm32_dma2d.h b/arch/arm/src/stm32/hardware/stm32_dma2d.h deleted file mode 100644 index 5f885095e2eaa..0000000000000 --- a/arch/arm/src/stm32/hardware/stm32_dma2d.h +++ /dev/null @@ -1,237 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/hardware/stm32_dma2d.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_DMA2D_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_DMA2D_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include "hardware/stm32_memorymap.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#define STM32_DMA2D_NCLUT 256 /* Number of entries in the CLUT */ - -/* DMA2D Register Offsets ***************************************************/ - -#define STM32_DMA2D_CR_OFFSET 0x0000 /* DMA2D Control Register */ -#define STM32_DMA2D_ISR_OFFSET 0x0004 /* DMA2D Interrupt Status Register */ -#define STM32_DMA2D_IFCR_OFFSET 0x0008 /* DMA2D Interrupt Flag Clear Register */ -#define STM32_DMA2D_FGMAR_OFFSET 0x000c /* DMA2D Foreground Memory Address Register */ -#define STM32_DMA2D_FGOR_OFFSET 0x0010 /* DMA2D Foreground Offset Register */ -#define STM32_DMA2D_BGMAR_OFFSET 0x0014 /* DMA2D Background Memory Address Register */ -#define STM32_DMA2D_BGOR_OFFSET 0x0018 /* DMA2D Background Offset Register */ -#define STM32_DMA2D_FGPFCCR_OFFSET 0x001c /* DMA2D Foreground PFC Control Register */ -#define STM32_DMA2D_FGCOLR_OFFSET 0x0020 /* DMA2D Foreground Color Register */ -#define STM32_DMA2D_BGPFCCR_OFFSET 0x0024 /* DMA2D Background PFC Control Register */ -#define STM32_DMA2D_BGCOLR_OFFSET 0x0028 /* DMA2D Background Color Register */ -#define STM32_DMA2D_FGCMAR_OFFSET 0x002c /* DMA2D Foreground CLUT Memory Address Register */ -#define STM32_DMA2D_BGCMAR_OFFSET 0x0030 /* DMA2D Background CLUT Memory Address Register */ -#define STM32_DMA2D_OPFCCR_OFFSET 0x0034 /* DMA2D Output PFC Control Register */ -#define STM32_DMA2D_OCOLR_OFFSET 0x0038 /* DMA2D Output Color Register */ -#define STM32_DMA2D_OMAR_OFFSET 0x003c /* DMA2D Output Memory Address Register */ -#define STM32_DMA2D_OOR_OFFSET 0x0040 /* DMA2D Output Offset Register */ -#define STM32_DMA2D_NLR_OFFSET 0x0044 /* DMA2D Number Of Line Register */ -#define STM32_DMA2D_LWR_OFFSET 0x0048 /* DMA2D Line Watermark Register */ -#define STM32_DMA2D_AMTCR_OFFSET 0x004c /* DMA2D AHB Master Time Configuration Register */ - -/* DMA2D Register Addresses *************************************************/ - -#define STM32_DMA2D_CR (STM32_DMA2D_BASE + STM32_DMA2D_CR_OFFSET) -#define STM32_DMA2D_ISR (STM32_DMA2D_BASE + STM32_DMA2D_ISR_OFFSET) -#define STM32_DMA2D_IFCR (STM32_DMA2D_BASE + STM32_DMA2D_IFCR_OFFSET) -#define STM32_DMA2D_FGMAR (STM32_DMA2D_BASE + STM32_DMA2D_FGMAR_OFFSET) -#define STM32_DMA2D_FGOR (STM32_DMA2D_BASE + STM32_DMA2D_FGOR_OFFSET) -#define STM32_DMA2D_BGMAR (STM32_DMA2D_BASE + STM32_DMA2D_BGMAR_OFFSET) -#define STM32_DMA2D_BGOR (STM32_DMA2D_BASE + STM32_DMA2D_BGOR_OFFSET) -#define STM32_DMA2D_FGPFCCR (STM32_DMA2D_BASE + STM32_DMA2D_FGPFCCR_OFFSET) -#define STM32_DMA2D_FGCOLR (STM32_DMA2D_BASE + STM32_DMA2D_FGCOLR_OFFSET) -#define STM32_DMA2D_BGPFCCR (STM32_DMA2D_BASE + STM32_DMA2D_BGPFCCR_OFFSET) -#define STM32_DMA2D_BGCOLR (STM32_DMA2D_BASE + STM32_DMA2D_BGCOLR_OFFSET) -#define STM32_DMA2D_FGCMAR (STM32_DMA2D_BASE + STM32_DMA2D_FGCMAR_OFFSET) -#define STM32_DMA2D_BGCMAR (STM32_DMA2D_BASE + STM32_DMA2D_BGCMAR_OFFSET) -#define STM32_DMA2D_OPFCCR (STM32_DMA2D_BASE + STM32_DMA2D_OPFCCR_OFFSET) -#define STM32_DMA2D_OCOLR (STM32_DMA2D_BASE + STM32_DMA2D_OCOLR_OFFSET) -#define STM32_DMA2D_OMAR (STM32_DMA2D_BASE + STM32_DMA2D_OMAR_OFFSET) -#define STM32_DMA2D_OOR (STM32_DMA2D_BASE + STM32_DMA2D_OOR_OFFSET) -#define STM32_DMA2D_NLR (STM32_DMA2D_BASE + STM32_DMA2D_NLR_OFFSET) -#define STM32_DMA2D_LWR (STM32_DMA2D_BASE + STM32_DMA2D_LWR_OFFSET) - -/* DMA2D Register Bit Definitions *******************************************/ - -/* DMA2D Control Register */ - -#define DMA2D_CR_START (1 << 0) /* Start Bit */ -#define DMA2D_CR_SUSP (1 << 1) /* Suspend Bit */ -#define DMA2D_CR_ABORT (1 << 2) /* Abort Bit */ -#define DMA2D_CR_TEIE (1 << 8) /* Transfer Error Interrupt Enable Bit */ -#define DMA2D_CR_TCIE (1 << 9) /* Transfer Complete Interrupt Enable Bit */ -#define DMA2D_CR_TWIE (1 << 10) /* Transfer Watermark Interrupt Enable Bit */ -#define DMA2D_CR_CAEIE (1 << 11) /* CLUT Access Error Interrupt Enable Bit */ -#define DMA2D_CR_CTCIE (1 << 12) /* CLUT Transfer Complete Interrupt Enable Bit */ -#define DMA2D_CR_CEIE (1 << 13) /* Configuration Error Interrupt Enable Bit */ -#define DMA2D_CR_MODE_SHIFT (16) /* Bits 16-17 DMA2D mode Bits */ -#define DMA2D_CR_MODE_MASK (3 << DMA2D_CR_MODE_SHIFT) -#define DMA2D_CR_MODE(n) ((uint32_t)(n) << DMA2D_CR_MODE_SHIFT) - -/* DMA2D Interrupt Status Register */ - -#define DMA2D_ISR_TEIF (1 << 0) /* Transfer error interrupt flag */ -#define DMA2D_ISR_TCIF (1 << 1) /* Transfer Complete Interrupt flag */ -#define DMA2D_ISR_TWIF (1 << 2) /* Transfer Watermark Interrupt flag */ -#define DMA2D_ISR_CAEIF (1 << 3) /* CLUT Access Error Interrupt flag */ -#define DMA2D_ISR_CTCIF (1 << 4) /* CLUT Transfer Complete Interrupt flag */ -#define DMA2D_ISR_CEIF (1 << 5) /* Configuration Error Interrupt flag */ - -/* DMA2D Interrupt Flag Clear Register */ - -#define DMA2D_IFCR_CTEIF (1 << 0) /* Clear Transfer Interrupt Flag */ -#define DMA2D_IFCR_CTCIF (1 << 1) /* Clear Transfer Complete Interrupt Flag */ -#define DMA2D_IFCR_CTWIF (1 << 2) /* Clear Transfer Watermark Interrupt Flag */ -#define DMA2D_IFCR_CAECIF (1 << 3) /* Clear CLUT Access Error Interrupt Flag */ -#define DMA2D_IFCR_CCTCIF (1 << 4) /* Clear CLUT Transfer Complete Interrupt Flag */ -#define DMA2D_IFCR_CCEIF (1 << 5) /* Clear Configuration Error Interrupt Flag */ - -/* DMA2D Foreground Memory Access Register */ - -/* DMA2D Background Memory Access Register */ - -/* DMA2D Foreground/Background Offset Register */ - -#define DMA2D_XGOR_SHIFT (0) /* Bits 0-13 Line Offset */ -#define DMA2D_XGOR_MASK (0x3fff << DMA2D_XGOR_SHIFT) -#define DMA2D_XGOR(n) ((uint32_t)(n) << DMA2D_XGOR_SHIFT) - -/* DMA2D Foreground/Background PFC Control Register */ - -#define DMA2D_XGPFCCR_CM_SHIFT (0) /* Bits 0-3 Color Mode */ -#define DMA2D_XGPFCCR_CM_MASK (0xf << DMA2D_XGPFCCR_CM_SHIFT) -#define DMA2D_XGPFCCR_CM(n) ((uint32_t)(n) << DMA2D_XGPFCCR_CM_SHIFT) -#define DMA2D_XGPFCCR_CCM (1 << 4) /* CLUT Color Mode */ -#define DMA2D_XGPFCCR_START (1 << 5) /* Start */ -#define DMA2D_XGPFCCR_CS_SHIFT (8) /* Bits 8-15 CLUT Size */ -#define DMA2D_XGPFCCR_CS_MASK (0xff << DMA2D_XGPFCCR_CS_SHIFT) -#define DMA2D_XGPFCCR_CS(n) ((uint32_t)(n) << DMA2D_XGPFCCR_CS_SHIFT) -#define DMA2D_XGPFCCR_AM_SHIFT (16) /* Bits 16-17 Alpha Mode */ -#define DMA2D_XGPFCCR_AM_MASK (3 << DMA2D_XGPFCCR_AM_SHIFT) -#define DMA2D_XGPFCCR_AM(n) ((uint32_t)(n) << DMA2D_XGPFCCR_AM_SHIFT) -#define DMA2D_XGPFCCR_ALPHA_SHIFT (24) /* Bits 24-31 Alpha Value */ -#define DMA2D_XGPFCCR_ALPHA_MASK (0xff << DMA2D_XGPFCCR_ALPHA_SHIFT) -#define DMA2D_XGPFCCR_ALPHA(n) ((uint32_t)(n) << DMA2D_XGPFCCR_ALPHA_SHIFT) - -/* DMA2D PFC alpha mode */ - -#define STM32_DMA2D_PFCCR_AM_NONE 0 -#define STM32_DMA2D_PFCCR_AM_CONST 1 -#define STM32_DMA2D_PFCCR_AM_PIXEL 2 - -/* DMA2D Foreground/Background Color Register */ - -#define DMA2D_XGCOLR_BLUE_SHIFT (0) /* Bits 0-7 Blue Value */ -#define DMA2D_XGCOLR_BLUE_MASK (0xff << DMA2D_XGCOLR_BLUE_SHIFT) -#define DMA2D_XGCOLR_BLUE(n) ((uint32_t)(n) << DMA2D_XGCOLR_BLUE_SHIFT) -#define DMA2D_XGCOLR_GREEN_SHIFT (8) /* Bits 8-15 Green Value */ -#define DMA2D_XGCOLR_GREEN_MASK (0xff << DMA2D_XGCOLR_GREEN_SHIFT) -#define DMA2D_XGCOLR_GREEN(n) ((uint32_t)(n) << DMA2D_XGCOLR_GREEN_SHIFT) -#define DMA2D_XGCOLR_RED_SHIFT (16) /* Bits 16-23 Red Value */ -#define DMA2D_XGCOLR_RED_MASK (0xff << DMA2D_XGCOLR_RED_SHIFT) -#define DMA2D_XGCOLR_RED(n) ((uint32_t)(n) << DMA2D_XGCOLR_RED_SHIFT) - -/* DMA2D Foreground CLUT Memory Address Register */ - -/* DMA2D Background CLUT Memory Address Register */ - -/* DMA2D Output PFC Control Register */ - -#define DMA2D_OPFCCR_CM_SHIFT (0) /* Bits 0-2 Color Mode */ -#define DMA2D_OPFCCR_CM_MASK (7 << DMA2D_OPFCCR_CM_SHIFT) -#define DMA2D_OPFCCR_CM(n) ((uint32_t)(n) << DMA2D_OPFCCR_CM_SHIFT) - -/* DMA2D PFC Pixel Format */ - -#define DMA2D_PF_ARGB8888 0 -#define DMA2D_PF_RGB888 1 -#define DMA2D_PF_RGB565 2 -#define DMA2D_PF_ARGB1555 3 -#define DMA2D_PF_ARGB14444 4 -#define DMA2D_PF_L8 5 -#define DMA2D_PF_AL44 6 -#define DMA2D_PF_AL88 7 -#define DMA2D_PF_L4 8 -#define DMA2D_PF_A8 9 -#define DMA2D_PF_A4 10 - -/* DMA2D Output Color Register */ - -#define DMA2D_OCOLR_BLUE_SHIFT (0) /* Bits 0-7 Blue Value */ -#define DMA2D_OCOLR_BLUE_MASK (0xff << DMA2D_OCOLR_BLUE_SHIFT) -#define DMA2D_OCOLR_BLUE(n) ((uint32_t)(n) << DMA2D_OCOLR_BLUE_SHIFT) -#define DMA2D_OCOLR_GREEN_SHIFT (8) /* Bits 8-15 Green Value */ -#define DMA2D_OCOLR_GREEN_MASK (0xff << DMA2D_OCOLR_GREEN_SHIFT) -#define DMA2D_OCOLR_GREEN(n) ((uint32_t)(n) << DMA2D_OCOLR_GREEN_SHIFT) -#define DMA2D_OCOLR_RED_SHIFT (16) /* Bits 16-23 Red Value */ -#define DMA2D_OCOLR_RED_MASK (0xff << DMA2D_OCOLR_RED_SHIFT) -#define DMA2D_OCOLR_RED(n) ((uint32_t)(n) << DMA2D_OCOLR_RED_SHIFT) -#define DMA2D_OCOLR_ALPHA_SHIFT (24) /* Bits 24-31 Alpha Value */ -#define DMA2D_OCOLR_ALPHA_MASK (0xff << DMA2D_OCOLR_ALPHA_SHIFT) -#define DMA2D_OCOLR_ALPHA(n) ((uint32_t)(n) << DMA2D_OCOLR_ALPHA_SHIFT) - -/* DMA2D Output Memory Address Register */ - -/* DMA2D Output Offset Register */ - -#define DMA2D_OOR_LO_SHIFT (0) /* Bits 0-13 Line Offset */ -#define DMA2D_OOR_LO_MASK (0x3fff << DMA2D_OOR_LO_SHIFT) -#define DMA2D_OOR_LO(n) ((uint32_t)(n) << DMA2D_OOR_LO_SHIFT) - -/* DMA2D Number Of Line Register */ - -#define DMA2D_NLR_NL_SHIFT (0) /* Bits 0-15 Number Of Lines */ -#define DMA2D_NLR_NL_MASK (0xffff << DMA2D_NLR_NL_SHIFT) -#define DMA2D_NLR_NL(n) ((uint32_t)(n) << DMA2D_NLR_NL_SHIFT) -#define DMA2D_NLR_PL_SHIFT (16) /* Bits 16-29 Pixel per Lines */ -#define DMA2D_NLR_PL_MASK (0x3fff << DMA2D_NLR_PL_SHIFT) -#define DMA2D_NLR_PL(n) ((uint32_t)(n) << DMA2D_NLR_PL_SHIFT) - -/* DMA2D Line Watermark Register */ - -#define DMA2D_LWR_LW_SHIFT (0) /* Bits 0-15 Line Watermark */ -#define DMA2D_LWR_LW_MASK (0xffff << DMA2D_LWR_LW_SHIFT) -#define DMA2D_LWR_LW(n) ((uint32_t)(n) << DMA2D_LWR_LW_SHIFT) - -/* DMA2D AHB Master Timer Configuration Register */ - -#define DMA2D_AMTCR_EN (1 << 0) /* Enable */ -#define DMA2D_AMTCR_DT_SHIFT (0) /* Bits 8-15 Dead Time */ -#define DMA2D_AMTCR_DT_MASK (0xff << DMA2D_AMTCR_DT_SHIFT) -#define DMA2D_AMTCR_DT(n) ((uint32_t)(n) << DMA2D_AMTCR_DT_SHIFT) - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_DMA2D_H */ diff --git a/arch/arm/src/stm32/hardware/stm32_dma_v1.h b/arch/arm/src/stm32/hardware/stm32_dma_v1.h deleted file mode 100644 index 0f73d267096b8..0000000000000 --- a/arch/arm/src/stm32/hardware/stm32_dma_v1.h +++ /dev/null @@ -1,773 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/hardware/stm32_dma_v1.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_DMA_V1_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_DMA_V1_H - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* This is implementation for STM32 DMA IP - * version 1 - F0, F1, F3, G4, L0, L1, L4 - */ - -#define HAVE_IP_DMA_V1 1 -#undef HAVE_IP_DMA_V2 - -/* F0, L0, L4 have additional CSELR register */ - -#undef DMA_HAVE_CSELR - -/* 2 DMA controllers */ - -#define DMA1 (0) -#define DMA2 (1) - -/* These definitions apply to multiple STM32 families. - * - * The STM32 F1 and F3 families have 12 channels total: - * 7 DMA1 channels(1-7) and 5 DMA2 channels (1-5). - * - * The STM32 G4 family has 16 channels total: - * 8 DMA1 channels(1-8) and 8 DMA2 channels (1-8). - */ - -#define DMA_CHAN1 (0) -#define DMA_CHAN2 (1) -#define DMA_CHAN3 (2) -#define DMA_CHAN4 (3) -#define DMA_CHAN5 (4) -#define DMA_CHAN6 (5) -#define DMA_CHAN7 (6) -#define DMA_CHAN8 (7) - -/* Register Offsets *********************************************************/ - -#define STM32_DMA_ISR_OFFSET 0x0000 /* DMA interrupt status register */ -#define STM32_DMA_IFCR_OFFSET 0x0004 /* DMA interrupt flag clear register */ - -#define STM32_DMACHAN_OFFSET(n) (0x0014*(n)) -#define STM32_DMACHAN1_OFFSET 0x0000 -#define STM32_DMACHAN2_OFFSET 0x0014 -#define STM32_DMACHAN3_OFFSET 0x0028 -#define STM32_DMACHAN4_OFFSET 0x003c -#define STM32_DMACHAN5_OFFSET 0x0050 -#define STM32_DMACHAN6_OFFSET 0x0064 -#define STM32_DMACHAN7_OFFSET 0x0078 -#define STM32_DMACHAN8_OFFSET 0x008c - -#define STM32_DMACHAN_CCR_OFFSET 0x0008 /* DMA channel configuration register */ -#define STM32_DMACHAN_CNDTR_OFFSET 0x000c /* DMA channel number of data register */ -#define STM32_DMACHAN_CPAR_OFFSET 0x0010 /* DMA channel peripheral address register */ -#define STM32_DMACHAN_CMAR_OFFSET 0x0014 /* DMA channel 1 memory address register */ - -#define STM32_DMA_CCR_OFFSET(n) (STM32_DMACHAN_CCR_OFFSET+STM32_DMACHAN_OFFSET(n)) -#define STM32_DMA_CNDTR_OFFSET(n) (STM32_DMACHAN_CNDTR_OFFSET+STM32_DMACHAN_OFFSET(n)) -#define STM32_DMA_CPAR_OFFSET(n) (STM32_DMACHAN_CPAR_OFFSET+STM32_DMACHAN_OFFSET(n)) -#define STM32_DMA_CMAR_OFFSET(n) (STM32_DMACHAN_CMAR_OFFSET+STM32_DMACHAN_OFFSET(n)) - -#define STM32_DMA_CCR1_OFFSET 0x0008 /* DMA channel 1 configuration register */ -#define STM32_DMA_CCR2_OFFSET 0x001c /* DMA channel 2 configuration register */ -#define STM32_DMA_CCR3_OFFSET 0x0030 /* DMA channel 3 configuration register */ -#define STM32_DMA_CCR4_OFFSET 0x0044 /* DMA channel 4 configuration register */ -#define STM32_DMA_CCR5_OFFSET 0x0058 /* DMA channel 5 configuration register */ -#define STM32_DMA_CCR6_OFFSET 0x006c /* DMA channel 6 configuration register */ -#define STM32_DMA_CCR7_OFFSET 0x0080 /* DMA channel 7 configuration register */ -#define STM32_DMA_CCR8_OFFSET 0x0094 /* DMA channel 8 configuration register */ - -#define STM32_DMA_CNDTR1_OFFSET 0x000c /* DMA channel 1 number of data register */ -#define STM32_DMA_CNDTR2_OFFSET 0x0020 /* DMA channel 2 number of data register */ -#define STM32_DMA_CNDTR3_OFFSET 0x0034 /* DMA channel 3 number of data register */ -#define STM32_DMA_CNDTR4_OFFSET 0x0048 /* DMA channel 4 number of data register */ -#define STM32_DMA_CNDTR5_OFFSET 0x005c /* DMA channel 5 number of data register */ -#define STM32_DMA_CNDTR6_OFFSET 0x0070 /* DMA channel 6 number of data register */ -#define STM32_DMA_CNDTR7_OFFSET 0x0084 /* DMA channel 7 number of data register */ -#define STM32_DMA_CNDTR8_OFFSET 0x0098 /* DMA channel 8 number of data register */ - -#define STM32_DMA_CPAR1_OFFSET 0x0010 /* DMA channel 1 peripheral address register */ -#define STM32_DMA_CPAR2_OFFSET 0x0024 /* DMA channel 2 peripheral address register */ -#define STM32_DMA_CPAR3_OFFSET 0x0038 /* DMA channel 3 peripheral address register */ -#define STM32_DMA_CPAR4_OFFSET 0x004c /* DMA channel 4 peripheral address register */ -#define STM32_DMA_CPAR5_OFFSET 0x0060 /* DMA channel 5 peripheral address register */ -#define STM32_DMA_CPAR6_OFFSET 0x0074 /* DMA channel 6 peripheral address register */ -#define STM32_DMA_CPAR7_OFFSET 0x0088 /* DMA channel 7 peripheral address register */ -#define STM32_DMA_CPAR8_OFFSET 0x009c /* DMA channel 8 peripheral address register */ - -#define STM32_DMA_CMAR1_OFFSET 0x0014 /* DMA channel 1 memory address register */ -#define STM32_DMA_CMAR2_OFFSET 0x0028 /* DMA channel 2 memory address register */ -#define STM32_DMA_CMAR3_OFFSET 0x003c /* DMA channel 3 memory address register */ -#define STM32_DMA_CMAR4_OFFSET 0x0050 /* DMA channel 4 memory address register */ -#define STM32_DMA_CMAR5_OFFSET 0x0064 /* DMA channel 5 memory address register */ -#define STM32_DMA_CMAR6_OFFSET 0x0078 /* DMA channel 6 memory address register */ -#define STM32_DMA_CMAR7_OFFSET 0x008c /* DMA channel 7 memory address register */ -#define STM32_DMA_CMAR8_OFFSET 0x00a0 /* DMA channel 8 memory address register */ - -#ifdef DMA_HAVE_CSELR -# define STM32_DMA_CSELR_OFFSET 0x00a8 /* DMA channel selection register */ -#endif - -/* Register Addresses *******************************************************/ - -#define STM32_DMA1_ISRC (STM32_DMA1_BASE+STM32_DMA_ISR_OFFSET) -#define STM32_DMA1_IFCR (STM32_DMA1_BASE+STM32_DMA_IFCR_OFFSET) - -#define STM32_DMA1_CCR(n) (STM32_DMA1_BASE+STM32_DMA_CCR_OFFSET(n)) -#define STM32_DMA1_CCR1 (STM32_DMA1_BASE+STM32_DMA_CCR1_OFFSET) -#define STM32_DMA1_CCR2 (STM32_DMA1_BASE+STM32_DMA_CCR2_OFFSET) -#define STM32_DMA1_CCR3 (STM32_DMA1_BASE+STM32_DMA_CCR3_OFFSET) -#define STM32_DMA1_CCR4 (STM32_DMA1_BASE+STM32_DMA_CCR4_OFFSET) -#define STM32_DMA1_CCR5 (STM32_DMA1_BASE+STM32_DMA_CCR5_OFFSET) -#define STM32_DMA1_CCR6 (STM32_DMA1_BASE+STM32_DMA_CCR6_OFFSET) -#define STM32_DMA1_CCR7 (STM32_DMA1_BASE+STM32_DMA_CCR7_OFFSET) -#if defined(CONFIG_STM32_HAVE_DMA1_CHAN8) -# define STM32_DMA1_CCR8 (STM32_DMA1_BASE+STM32_DMA_CCR8_OFFSET) -#endif - -#define STM32_DMA1_CNDTR(n) (STM32_DMA1_BASE+STM32_DMA_CNDTR_OFFSET(n)) -#define STM32_DMA1_CNDTR1 (STM32_DMA1_BASE+STM32_DMA_CNDTR1_OFFSET) -#define STM32_DMA1_CNDTR2 (STM32_DMA1_BASE+STM32_DMA_CNDTR2_OFFSET) -#define STM32_DMA1_CNDTR3 (STM32_DMA1_BASE+STM32_DMA_CNDTR3_OFFSET) -#define STM32_DMA1_CNDTR4 (STM32_DMA1_BASE+STM32_DMA_CNDTR4_OFFSET) -#define STM32_DMA1_CNDTR5 (STM32_DMA1_BASE+STM32_DMA_CNDTR5_OFFSET) -#define STM32_DMA1_CNDTR6 (STM32_DMA1_BASE+STM32_DMA_CNDTR6_OFFSET) -#define STM32_DMA1_CNDTR7 (STM32_DMA1_BASE+STM32_DMA_CNDTR7_OFFSET) -#if defined(CONFIG_STM32_HAVE_DMA1_CHAN8) -# define STM32_DMA1_CNDTR8 (STM32_DMA1_BASE+STM32_DMA_CNDTR8_OFFSET) -#endif - -#define STM32_DMA1_CPAR(n) (STM32_DMA1_BASE+STM32_DMA_CPAR_OFFSET(n)) -#define STM32_DMA1_CPAR1 (STM32_DMA1_BASE+STM32_DMA_CPAR1_OFFSET) -#define STM32_DMA1_CPAR2 (STM32_DMA1_BASE+STM32_DMA_CPAR2_OFFSET) -#define STM32_DMA1_CPAR3 (STM32_DMA1_BASE+STM32_DMA_CPAR3_OFFSET) -#define STM32_DMA1_CPAR4 (STM32_DMA1_BASE+STM32_DMA_CPAR4_OFFSET) -#define STM32_DMA1_CPAR5 (STM32_DMA1_BASE+STM32_DMA_CPAR5_OFFSET) -#define STM32_DMA1_CPAR6 (STM32_DMA1_BASE+STM32_DMA_CPAR6_OFFSET) -#define STM32_DMA1_CPAR7 (STM32_DMA1_BASE+STM32_DMA_CPAR7_OFFSET) -#if defined(CONFIG_STM32_HAVE_DMA1_CHAN8) -# define STM32_DMA1_CPAR8 (STM32_DMA1_BASE+STM32_DMA_CPAR8_OFFSET) -#endif - -#define STM32_DMA1_CMAR(n) (STM32_DMA1_BASE+STM32_DMA_CMAR_OFFSET(n)) -#define STM32_DMA1_CMAR1 (STM32_DMA1_BASE+STM32_DMA_CMAR1_OFFSET) -#define STM32_DMA1_CMAR2 (STM32_DMA1_BASE+STM32_DMA_CMAR2_OFFSET) -#define STM32_DMA1_CMAR3 (STM32_DMA1_BASE+STM32_DMA_CMAR3_OFFSET) -#define STM32_DMA1_CMAR4 (STM32_DMA1_BASE+STM32_DMA_CMAR4_OFFSET) -#define STM32_DMA1_CMAR5 (STM32_DMA1_BASE+STM32_DMA_CMAR5_OFFSET) -#define STM32_DMA1_CMAR6 (STM32_DMA1_BASE+STM32_DMA_CMAR6_OFFSET) -#define STM32_DMA1_CMAR7 (STM32_DMA1_BASE+STM32_DMA_CMAR7_OFFSET) -#if defined(CONFIG_STM32_HAVE_DMA1_CHAN8) -# define STM32_DMA1_CMAR8 (STM32_DMA1_BASE+STM32_DMA_CMAR8_OFFSET) -#endif - -#define STM32_DMA2_ISRC (STM32_DMA2_BASE+STM32_DMA_ISR_OFFSET) -#define STM32_DMA2_IFCR (STM32_DMA2_BASE+STM32_DMA_IFCR_OFFSET) - -#define STM32_DMA2_CCR(n) (STM32_DMA2_BASE+STM32_DMA_CCR_OFFSET(n)) -#define STM32_DMA2_CCR1 (STM32_DMA2_BASE+STM32_DMA_CCR1_OFFSET) -#define STM32_DMA2_CCR2 (STM32_DMA2_BASE+STM32_DMA_CCR2_OFFSET) -#define STM32_DMA2_CCR3 (STM32_DMA2_BASE+STM32_DMA_CCR3_OFFSET) -#define STM32_DMA2_CCR4 (STM32_DMA2_BASE+STM32_DMA_CCR4_OFFSET) -#define STM32_DMA2_CCR5 (STM32_DMA2_BASE+STM32_DMA_CCR5_OFFSET) -#if defined(CONFIG_STM32_HAVE_DMA2_CHAN678) -# define STM32_DMA2_CCR6 (STM32_DMA2_BASE+STM32_DMA_CCR6_OFFSET) -# define STM32_DMA2_CCR7 (STM32_DMA2_BASE+STM32_DMA_CCR7_OFFSET) -# define STM32_DMA2_CCR8 (STM32_DMA2_BASE+STM32_DMA_CCR8_OFFSET) -#endif - -#define STM32_DMA2_CNDTR(n) (STM32_DMA2_BASE+STM32_DMA_CNDTR_OFFSET(n)) -#define STM32_DMA2_CNDTR1 (STM32_DMA2_BASE+STM32_DMA_CNDTR1_OFFSET) -#define STM32_DMA2_CNDTR2 (STM32_DMA2_BASE+STM32_DMA_CNDTR2_OFFSET) -#define STM32_DMA2_CNDTR3 (STM32_DMA2_BASE+STM32_DMA_CNDTR3_OFFSET) -#define STM32_DMA2_CNDTR4 (STM32_DMA2_BASE+STM32_DMA_CNDTR4_OFFSET) -#define STM32_DMA2_CNDTR5 (STM32_DMA2_BASE+STM32_DMA_CNDTR5_OFFSET) -#if defined(CONFIG_STM32_HAVE_DMA2_CHAN678) -# define STM32_DMA2_CNDTR6 (STM32_DMA2_BASE+STM32_DMA_CNDTR6_OFFSET) -# define STM32_DMA2_CNDTR7 (STM32_DMA2_BASE+STM32_DMA_CNDTR7_OFFSET) -# define STM32_DMA2_CNDTR8 (STM32_DMA2_BASE+STM32_DMA_CNDTR8_OFFSET) -#endif - -#define STM32_DMA2_CPAR(n) (STM32_DMA2_BASE+STM32_DMA_CPAR_OFFSET(n)) -#define STM32_DMA2_CPAR1 (STM32_DMA2_BASE+STM32_DMA_CPAR1_OFFSET) -#define STM32_DMA2_CPAR2 (STM32_DMA2_BASE+STM32_DMA_CPAR2_OFFSET) -#define STM32_DMA2_CPAR3 (STM32_DMA2_BASE+STM32_DMA_CPAR3_OFFSET) -#define STM32_DMA2_CPAR4 (STM32_DMA2_BASE+STM32_DMA_CPAR4_OFFSET) -#define STM32_DMA2_CPAR5 (STM32_DMA2_BASE+STM32_DMA_CPAR5_OFFSET) -#if defined(CONFIG_STM32_HAVE_DMA2_CHAN678) -# define STM32_DMA2_CPAR6 (STM32_DMA2_BASE+STM32_DMA_CPAR6_OFFSET) -# define STM32_DMA2_CPAR7 (STM32_DMA2_BASE+STM32_DMA_CPAR7_OFFSET) -# define STM32_DMA2_CPAR8 (STM32_DMA2_BASE+STM32_DMA_CPAR8_OFFSET) -#endif - -#define STM32_DMA2_CMAR(n) (STM32_DMA2_BASE+STM32_DMA_CMAR_OFFSET(n)) -#define STM32_DMA2_CMAR1 (STM32_DMA2_BASE+STM32_DMA_CMAR1_OFFSET) -#define STM32_DMA2_CMAR2 (STM32_DMA2_BASE+STM32_DMA_CMAR2_OFFSET) -#define STM32_DMA2_CMAR3 (STM32_DMA2_BASE+STM32_DMA_CMAR3_OFFSET) -#define STM32_DMA2_CMAR4 (STM32_DMA2_BASE+STM32_DMA_CMAR4_OFFSET) -#define STM32_DMA2_CMAR5 (STM32_DMA2_BASE+STM32_DMA_CMAR5_OFFSET) -#if defined(CONFIG_STM32_HAVE_DMA2_CHAN678) -# define STM32_DMA2_CMAR6 (STM32_DMA2_BASE+STM32_DMA_CMAR6_OFFSET) -# define STM32_DMA2_CMAR7 (STM32_DMA2_BASE+STM32_DMA_CMAR7_OFFSET) -# define STM32_DMA2_CMAR8 (STM32_DMA2_BASE+STM32_DMA_CMAR8_OFFSET) -#endif - -/* Register Bitfield Definitions ********************************************/ - -#define DMA_CHAN_SHIFT(n) ((n) << 2) -#define DMA_CHAN_MASK 0x0f -#define DMA_CHAN_GIF_BIT (1 << 0) /* Bit 0: Channel Global interrupt flag */ -#define DMA_CHAN_TCIF_BIT (1 << 1) /* Bit 1: Channel Transfer Complete flag */ -#define DMA_CHAN_HTIF_BIT (1 << 2) /* Bit 2: Channel Half Transfer flag */ -#define DMA_CHAN_TEIF_BIT (1 << 3) /* Bit 3: Channel Transfer Error flag */ - -/* DMA interrupt status register */ - -#define DMA_ISR_CHAN_SHIFT(n) DMA_CHAN_SHIFT(n) -#define DMA_ISR_CHAN_MASK(n) (DMA_CHAN_MASK << DMA_ISR_CHAN_SHIFT(n)) -#define DMA_ISR_CHAN1_SHIFT (0) /* Bits 3-0: DMA Channel 1 interrupt status */ -#define DMA_ISR_CHAN1_MASK (DMA_CHAN_MASK << DMA_ISR_CHAN1_SHIFT) -#define DMA_ISR_CHAN2_SHIFT (4) /* Bits 7-4: DMA Channel 2 interrupt status */ -#define DMA_ISR_CHAN2_MASK (DMA_CHAN_MASK << DMA_ISR_CHAN2_SHIFT) -#define DMA_ISR_CHAN3_SHIFT (8) /* Bits 11-8: DMA Channel 3 interrupt status */ -#define DMA_ISR_CHAN3_MASK (DMA_CHAN_MASK << DMA_ISR_CHAN3_SHIFT) -#define DMA_ISR_CHAN4_SHIFT (12) /* Bits 15-12: DMA Channel 4 interrupt status */ -#define DMA_ISR_CHAN4_MASK (DMA_CHAN_MASK << DMA_ISR_CHAN4_SHIFT) -#define DMA_ISR_CHAN5_SHIFT (16) /* Bits 19-16: DMA Channel 5 interrupt status */ -#define DMA_ISR_CHAN5_MASK (DMA_CHAN_MASK << DMA_ISR_CHAN5_SHIFT) -#define DMA_ISR_CHAN6_SHIFT (20) /* Bits 23-20: DMA Channel 6 interrupt status */ -#define DMA_ISR_CHAN6_MASK (DMA_CHAN_MASK << DMA_ISR_CHAN6_SHIFT) -#define DMA_ISR_CHAN7_SHIFT (24) /* Bits 27-24: DMA Channel 7 interrupt status */ -#define DMA_ISR_CHAN7_MASK (DMA_CHAN_MASK << DMA_ISR_CHAN7_SHIFT) -#define DMA_ISR_CHAN8_SHIFT (28) /* Bits 31-28: DMA Channel 8 interrupt status */ -#define DMA_ISR_CHAN8_MASK (DMA_CHAN_MASK << DMA_ISR_CHAN8_SHIFT) - -#define DMA_ISR_GIF(n) (DMA_CHAN_GIF_BIT << DMA_ISR_CHAN_SHIFT(n)) -#define DMA_ISR_TCIF(n) (DMA_CHAN_TCIF_BIT << DMA_ISR_CHAN_SHIFT(n)) -#define DMA_ISR_HTIF(n) (DMA_CHAN_HTIF_BIT << DMA_ISR_CHAN_SHIFT(n)) -#define DMA_ISR_TEIF(n) (DMA_CHAN_TEIF_BIT << DMA_ISR_CHAN_SHIFT(n)) - -/* DMA interrupt flag clear register */ - -#define DMA_IFCR_CHAN_SHIFT(n) DMA_CHAN_SHIFT(n) -#define DMA_IFCR_CHAN_MASK(n) (DMA_CHAN_MASK << DMA_IFCR_CHAN_SHIFT(n)) -#define DMA_IFCR_CHAN1_SHIFT (0) /* Bits 3-0: DMA Channel 1 interrupt flag clear */ -#define DMA_IFCR_CHAN1_MASK (DMA_CHAN_MASK << DMA_IFCR_CHAN1_SHIFT) -#define DMA_IFCR_CHAN2_SHIFT (4) /* Bits 7-4: DMA Channel 2 interrupt flag clear */ -#define DMA_IFCR_CHAN2_MASK (DMA_CHAN_MASK << DMA_IFCR_CHAN2_SHIFT) -#define DMA_IFCR_CHAN3_SHIFT (8) /* Bits 11-8: DMA Channel 3 interrupt flag clear */ -#define DMA_IFCR_CHAN3_MASK (DMA_CHAN_MASK << DMA_IFCR_CHAN3_SHIFT) -#define DMA_IFCR_CHAN4_SHIFT (12) /* Bits 15-12: DMA Channel 4 interrupt flag clear */ -#define DMA_IFCR_CHAN4_MASK (DMA_CHAN_MASK << DMA_IFCR_CHAN4_SHIFT) -#define DMA_IFCR_CHAN5_SHIFT (16) /* Bits 19-16: DMA Channel 5 interrupt flag clear */ -#define DMA_IFCR_CHAN5_MASK (DMA_CHAN_MASK << DMA_IFCR_CHAN5_SHIFT) -#define DMA_IFCR_CHAN6_SHIFT (20) /* Bits 23-20: DMA Channel 6 interrupt flag clear */ -#define DMA_IFCR_CHAN6_MASK (DMA_CHAN_MASK << DMA_IFCR_CHAN6_SHIFT) -#define DMA_IFCR_CHAN7_SHIFT (24) /* Bits 27-24: DMA Channel 7 interrupt flag clear */ -#define DMA_IFCR_CHAN7_MASK (DMA_CHAN_MASK << DMA_IFCR_CHAN7_SHIFT) -#define DMA_IFCR_CHAN8_SHIFT (28) /* Bits 31-28: DMA Channel 8 interrupt flag clear */ -#define DMA_IFCR_CHAN8_MASK (DMA_CHAN_MASK << DMA_IFCR_CHAN8_SHIFT) - -#if defined(CONFIG_STM32_HAVE_DMA1_CHAN8) || defined(CONFIG_STM32_HAVE_DMA2_CHAN678) -# define DMA_IFCR_ALLCHANNELS (0xffffffff) -#else -# define DMA_IFCR_ALLCHANNELS (0x0fffffff) -#endif - -#define DMA_IFCR_CGIF(n) (DMA_CHAN_GIF_BIT << DMA_IFCR_CHAN_SHIFT(n)) -#define DMA_IFCR_CTCIF(n) (DMA_CHAN_TCIF_BIT << DMA_IFCR_CHAN_SHIFT(n)) -#define DMA_IFCR_CHTIF(n) (DMA_CHAN_HTIF_BIT << DMA_IFCR_CHAN_SHIFT(n)) -#define DMA_IFCR_CTEIF(n) (DMA_CHAN_TEIF_BIT << DMA_IFCR_CHAN_SHIFT(n)) - -/* DMA channel configuration register */ - -#define DMA_CCR_EN (1 << 0) /* Bit 0: Channel enable */ -#define DMA_CCR_TCIE (1 << 1) /* Bit 1: Transfer complete interrupt enable */ -#define DMA_CCR_HTIE (1 << 2) /* Bit 2: Half Transfer interrupt enable */ -#define DMA_CCR_TEIE (1 << 3) /* Bit 3: Transfer error interrupt enable */ -#define DMA_CCR_DIR (1 << 4) /* Bit 4: Data transfer direction */ -#define DMA_CCR_CIRC (1 << 5) /* Bit 5: Circular mode */ -#define DMA_CCR_PINC (1 << 6) /* Bit 6: Peripheral increment mode */ -#define DMA_CCR_MINC (1 << 7) /* Bit 7: Memory increment mode */ -#define DMA_CCR_PSIZE_SHIFT (8) /* Bits 8-9: Peripheral size */ -#define DMA_CCR_PSIZE_MASK (3 << DMA_CCR_PSIZE_SHIFT) -# define DMA_CCR_PSIZE_8BITS (0 << DMA_CCR_PSIZE_SHIFT) /* 00: 8-bits */ -# define DMA_CCR_PSIZE_16BITS (1 << DMA_CCR_PSIZE_SHIFT) /* 01: 16-bits */ -# define DMA_CCR_PSIZE_32BITS (2 << DMA_CCR_PSIZE_SHIFT) /* 10: 32-bits */ -#define DMA_CCR_MSIZE_SHIFT (10) /* Bits 10-11: Memory size */ -#define DMA_CCR_MSIZE_MASK (3 << DMA_CCR_MSIZE_SHIFT) -# define DMA_CCR_MSIZE_8BITS (0 << DMA_CCR_MSIZE_SHIFT) /* 00: 8-bits */ -# define DMA_CCR_MSIZE_16BITS (1 << DMA_CCR_MSIZE_SHIFT) /* 01: 16-bits */ -# define DMA_CCR_MSIZE_32BITS (2 << DMA_CCR_MSIZE_SHIFT) /* 10: 32-bits */ -#define DMA_CCR_PL_SHIFT (12) /* Bits 12-13: Channel Priority level */ -#define DMA_CCR_PL_MASK (3 << DMA_CCR_PL_SHIFT) -# define DMA_CCR_PRILO (0 << DMA_CCR_PL_SHIFT) /* 00: Low */ -# define DMA_CCR_PRIMED (1 << DMA_CCR_PL_SHIFT) /* 01: Medium */ -# define DMA_CCR_PRIHI (2 << DMA_CCR_PL_SHIFT) /* 10: High */ -# define DMA_CCR_PRIVERYHI (3 << DMA_CCR_PL_SHIFT) /* 11: Very high */ -#define DMA_CCR_MEM2MEM (1 << 14) /* Bit 14: Memory to memory mode */ - -#define DMA_CCR_ALLINTS (DMA_CCR_TEIE|DMA_CCR_HTIE|DMA_CCR_TCIE) - -/* DMA channel number of data register */ - -#define DMA_CNDTR_NDT_SHIFT (0) /* Bits 15-0: Number of data to Transfer */ -#define DMA_CNDTR_NDT_MASK (0xffff << DMA_CNDTR_NDT_SHIFT) - -/* DMA Channel mapping. - * Each DMA channel has a mapping to several possible sources/sinks of data. - * The requests from peripherals assigned to a channel are simply OR'ed - * together before entering the DMA block. This means that onlyone request - * on a given channel can be enabled at once. - * - * Alternative DMA channel selections are provided with a numeric suffix like - * _1, _2, etc. Drivers, however, will use the pin selection without the - * numeric suffix. Additional definitions are required in the board.h file. - */ - -#define STM32_DMA1_CHAN1 (0) -#define STM32_DMA1_CHAN2 (1) -#define STM32_DMA1_CHAN3 (2) -#define STM32_DMA1_CHAN4 (3) -#define STM32_DMA1_CHAN5 (4) -#define STM32_DMA1_CHAN6 (5) -#define STM32_DMA1_CHAN7 (6) -#if defined(CONFIG_STM32_HAVE_DMA1_CHAN8) -# define STM32_DMA1_CHAN8 (7) -# define STM32_DMA2_CHAN1 (8) -# define STM32_DMA2_CHAN2 (9) -# define STM32_DMA2_CHAN3 (10) -# define STM32_DMA2_CHAN4 (11) -# define STM32_DMA2_CHAN5 (12) -# if defined(CONFIG_STM32_HAVE_DMA2_CHAN678) -# define STM32_DMA2_CHAN6 (13) -# define STM32_DMA2_CHAN7 (14) -# define STM32_DMA2_CHAN8 (15) -# endif -#else -# define STM32_DMA2_CHAN1 (7) -# define STM32_DMA2_CHAN2 (8) -# define STM32_DMA2_CHAN3 (9) -# define STM32_DMA2_CHAN4 (10) -# define STM32_DMA2_CHAN5 (11) -# if defined(CONFIG_STM32_HAVE_DMA2_CHAN678) -# define STM32_DMA2_CHAN6 (12) -# define STM32_DMA2_CHAN7 (13) -# define STM32_DMA2_CHAN8 (14) -# endif -#endif - -#ifdef DMA_HAVE_CSELR -# define DMACHAN_SETTING(chan, sel) ((((sel) & 0xff) << 8) | ((chan) & 0xff)) -# define DMACHAN_SETTING_CHANNEL_MASK 0x00ff -# define DMACHAN_SETTING_CHANNEL_SHIFT (0) -# define DMACHAN_SETTING_FUNCTION_MASK 0xff00 -# define DMACHAN_SETTING_FUNCTION_SHIFT (8) -#endif - -#if defined(CONFIG_STM32_STM32L15XX) - -# define DMACHAN_ADC1 STM32_DMA1_CHAN1 -# define DMACHAN_TIM2_CH3 STM32_DMA1_CHAN1 -# define DMACHAN_TIM4_CH1 STM32_DMA1_CHAN1 - -# define DMACHAN_SPI1_RX STM32_DMA1_CHAN2 -# define DMACHAN_USART3_TX STM32_DMA1_CHAN2 -# define DMACHAN_TIM2_UP STM32_DMA1_CHAN2 -# define DMACHAN_TIM3_CH3 STM32_DMA1_CHAN2 -# define DMACHAN_TIM6_UP STM32_DMA1_CHAN2 -# define DMACHAN_DAC1_CH1 STM32_DMA1_CHAN2 - -# define DMACHAN_SPI1_TX STM32_DMA1_CHAN3 -# define DMACHAN_USART3_RX STM32_DMA1_CHAN3 -# define DMACHAN_TIM3_CH4 STM32_DMA1_CHAN3 -# define DMACHAN_TIM3_UP STM32_DMA1_CHAN3 -# define DMACHAN_TIM7_UP STM32_DMA1_CHAN3 -# define DMACHAN_DAC1_CH2 STM32_DMA1_CHAN3 - -# define DMACHAN_SPI2_RX STM32_DMA1_CHAN4 -# define DMACHAN_USART1_TX STM32_DMA1_CHAN4 -# define DMACHAN_I2C2_TX STM32_DMA1_CHAN4 -# define DMACHAN_TIM4_CH2 STM32_DMA1_CHAN4 - -# define DMACHAN_SPI2_TX STM32_DMA1_CHAN5 -# define DMACHAN_USART1_RX STM32_DMA1_CHAN5 -# define DMACHAN_I2C2_RX STM32_DMA1_CHAN5 -# define DMACHAN_TIM2_CH1 STM32_DMA1_CHAN5 -# define DMACHAN_TIM4_CH3 STM32_DMA1_CHAN5 - -# define DMACHAN_USART2_RX STM32_DMA1_CHAN6 -# define DMACHAN_I2C1_TX STM32_DMA1_CHAN6 -# define DMACHAN_TIM3_CH1 STM32_DMA1_CHAN6 -# define DMACHAN_TIM3_TRIG STM32_DMA1_CHAN6 - -# define DMACHAN_USART2_TX STM32_DMA1_CHAN7 -# define DMACHAN_I2C1_RX STM32_DMA1_CHAN7 -# define DMACHAN_TIM2_CH2 STM32_DMA1_CHAN7 -# define DMACHAN_TIM2_CH4 STM32_DMA1_CHAN7 -# define DMACHAN_TIM4_UP STM32_DMA1_CHAN7 - -# define DMACHAN_SPI3_RX STM32_DMA2_CHAN1 -# define DMACHAN_UART5_TX STM32_DMA2_CHAN1 -# define DMACHAN_TIM5_CH4 STM32_DMA2_CHAN1 -# define DMACHAN_TIM5_TRIG STM32_DMA2_CHAN1 -# define DMACHAN_TIM5_COM STM32_DMA2_CHAN1 - -# define DMACHAN_SPI3_TX STM32_DMA2_CHAN2 -# define DMACHAN_UART5_RX STM32_DMA2_CHAN2 -# define DMACHAN_TIM5_CH3 STM32_DMA2_CHAN2 -# define DMACHAN_TIM5_UP STM32_DMA2_CHAN2 - -# define DMACHAN_UART4_RX STM32_DMA2_CHAN3 -# define DMACHAN_AES_OUT STM32_DMA2_CHAN3 - -# define DMACHAN_TIM5_CH2 STM32_DMA2_CHAN4 -# define DMACHAN_SDIO STM32_DMA2_CHAN4 - -# define DMACHAN_UART4_TX STM32_DMA2_CHAN5 -# define DMACHAN_TIM5_CH1 STM32_DMA2_CHAN5 -# define DMACHAN_AES_IN STM32_DMA2_CHAN5 - -#elif defined(CONFIG_STM32_STM32F10XX) - -# define DMACHAN_ADC1 STM32_DMA1_CHAN1 -# define DMACHAN_TIM2_CH3 STM32_DMA1_CHAN1 -# define DMACHAN_TIM4_CH1 STM32_DMA1_CHAN1 - -# define DMACHAN_SPI1_RX STM32_DMA1_CHAN2 -# define DMACHAN_USART3_TX STM32_DMA1_CHAN2 -# define DMACHAN_TIM1_CH1 STM32_DMA1_CHAN2 -# define DMACHAN_TIM2_UP STM32_DMA1_CHAN2 -# define DMACHAN_TIM3_CH3 STM32_DMA1_CHAN2 - -# define DMACHAN_SPI1_TX STM32_DMA1_CHAN3 -# define DMACHAN_USART3_RX STM32_DMA1_CHAN3 -# define DMACHAN_TIM1_CH2 STM32_DMA1_CHAN3 -# define DMACHAN_TIM3_CH4 STM32_DMA1_CHAN3 -# define DMACHAN_TIM3_UP STM32_DMA1_CHAN3 - -# define DMACHAN_SPI2_RX STM32_DMA1_CHAN4 -# define DMACHAN_I2S2_RX STM32_DMA1_CHAN4 -# define DMACHAN_USART1_TX STM32_DMA1_CHAN4 -# define DMACHAN_I2C2_TX STM32_DMA1_CHAN4 -# define DMACHAN_TIM1_CH4 STM32_DMA1_CHAN4 -# define DMACHAN_TIM1_TRIG STM32_DMA1_CHAN4 -# define DMACHAN_TIM1_COM STM32_DMA1_CHAN4 -# define DMACHAN_TIM4_CH2 STM32_DMA1_CHAN4 - -# define DMACHAN_SPI2_TX STM32_DMA1_CHAN5 -# define DMACHAN_I2S2_TX STM32_DMA1_CHAN5 -# define DMACHAN_USART1_RX STM32_DMA1_CHAN5 -# define DMACHAN_I2C2_RX STM32_DMA1_CHAN5 -# define DMACHAN_TIM1_UP STM32_DMA1_CHAN5 -# define DMACHAN_TIM2_CH1 STM32_DMA1_CHAN5 -# define DMACHAN_TIM4_CH3 STM32_DMA1_CHAN5 - -# define DMACHAN_USART2_RX STM32_DMA1_CHAN6 -# define DMACHAN_I2C1_TX STM32_DMA1_CHAN6 -# define DMACHAN_TIM1_CH3 STM32_DMA1_CHAN6 -# define DMACHAN_TIM3_CH1 STM32_DMA1_CHAN6 -# define DMACHAN_TIM3_TRIG STM32_DMA1_CHAN6 - -# define DMACHAN_USART2_TX STM32_DMA1_CHAN7 -# define DMACHAN_I2C1_RX STM32_DMA1_CHAN7 -# define DMACHAN_TIM2_CH2 STM32_DMA1_CHAN7 -# define DMACHAN_TIM2_CH4 STM32_DMA1_CHAN7 -# define DMACHAN_TIM4_UP STM32_DMA1_CHAN7 - -# define DMACHAN_SPI3_RX STM32_DMA2_CHAN1 -# define DMACHAN_I2S3_RX STM32_DMA2_CHAN1 -# define DMACHAN_TIM5_CH4 STM32_DMA2_CHAN1 -# define DMACHAN_TIM5_TRIG STM32_DMA2_CHAN1 -# define DMACHAN_TIM8_CH3 STM32_DMA2_CHAN1 -# define DMACHAN_TIM8_UP STM32_DMA2_CHAN1 - -# define DMACHAN_SPI3_TX STM32_DMA2_CHAN2 -# define DMACHAN_I2S3_TX STM32_DMA2_CHAN2 -# define DMACHAN_TIM5_CH3 STM32_DMA2_CHAN2 -# define DMACHAN_TIM5_UP STM32_DMA2_CHAN2 -# define DMACHAN_TIM8_TRIG STM32_DMA2_CHAN2 -# define DMACHAN_TIM8_COM STM32_DMA2_CHAN2 - -# define DMACHAN_UART4_RX STM32_DMA2_CHAN3 -# define DMACHAN_TIM6_UP STM32_DMA2_CHAN3 -# define DMACHAN_DAC1_CH1 STM32_DMA2_CHAN3 -# define DMACHAN_TIM8_CH1 STM32_DMA2_CHAN3 - -# define DMACHAN_SDIO STM32_DMA2_CHAN4 -# define DMACHAN_TIM5_CH2 STM32_DMA2_CHAN4 -# define DMACHAN_TIM7_UP STM32_DMA2_CHAN4 -# define DMACHAN_DAC1_CH2 STM32_DMA2_CHAN4 - -# define DMACHAN_ADC3 STM32_DMA2_CHAN5 -# define DMACHAN_UART4_TX STM32_DMA2_CHAN5 -# define DMACHAN_TIM5_CH1 STM32_DMA2_CHAN5 -# define DMACHAN_TIM8_CH2 STM32_DMA2_CHAN5 - -#elif defined(CONFIG_STM32_STM32F30XX) - -# define DMACHAN_ADC1 STM32_DMA1_CHAN1 -# define DMACHAN_TIM2_CH3 STM32_DMA1_CHAN1 -# define DMACHAN_TIM4_CH1 STM32_DMA1_CHAN1 -# define DMACHAN_TIM17_CH1 STM32_DMA1_CHAN1 -# define DMACHAN_TIM17_UP STM32_DMA1_CHAN1 - -# define DMACHAN_SPI1_RX STM32_DMA1_CHAN2 -# define DMACHAN_USART3_TX STM32_DMA1_CHAN2 -# define DMACHAN_TIM1_CH1 STM32_DMA1_CHAN2 -# define DMACHAN_TIM2_UP STM32_DMA1_CHAN2 -# define DMACHAN_TIM3_CH3 STM32_DMA1_CHAN2 - -# define DMACHAN_SPI1_TX STM32_DMA1_CHAN3 -# define DMACHAN_USART3_RX STM32_DMA1_CHAN3 -# define DMACHAN_TIM1_CH2_1 STM32_DMA1_CHAN3 -# define DMACHAN_TIM3_CH4 STM32_DMA1_CHAN3 -# define DMACHAN_TIM3_UP_2 STM32_DMA1_CHAN3 -# define DMACHAN_DAC1_CH1_1 STM32_DMA1_CHAN3 - -# define DMACHAN_SPI2_RX STM32_DMA1_CHAN4 -# define DMACHAN_I2S2_RX STM32_DMA1_CHAN4 -# define DMACHAN_USART1_TX STM32_DMA1_CHAN4 -# define DMACHAN_I2C2_TX STM32_DMA1_CHAN4 -# define DMACHAN_TIM1_CH4 STM32_DMA1_CHAN4 -# define DMACHAN_TIM1_TRIG STM32_DMA1_CHAN4 -# define DMACHAN_TIM1_COM STM32_DMA1_CHAN4 -# define DMACHAN_TIM4_CH2 STM32_DMA1_CHAN4 -# define DMACHAN_TIM7_UP_1 STM32_DMA1_CHAN4 -# define DMACHAN_DAC1_CH2_1 STM32_DMA1_CHAN4 /* NOTE: a typo in the ref manual */ - -# define DMACHAN_SPI2_TX STM32_DMA1_CHAN5 -# define DMACHAN_I2S2_TX STM32_DMA1_CHAN5 -# define DMACHAN_USART1_RX STM32_DMA1_CHAN5 -# define DMACHAN_I2C2_RX STM32_DMA1_CHAN5 -# define DMACHAN_TIM1_UP STM32_DMA1_CHAN5 -# define DMACHAN_TIM2_CH1 STM32_DMA1_CHAN5 -# define DMACHAN_TIM4_CH3 STM32_DMA1_CHAN5 -# define DMACHAN_TIM15_CH1 STM32_DMA1_CHAN5 -# define DMACHAN_TIM15_UP STM32_DMA1_CHAN5 -# define DMACHAN_TIM15_TRIG STM32_DMA1_CHAN5 -# define DMACHAN_TIM15_COM STM32_DMA1_CHAN5 -# define DMACHAN_DAC2_CH1 STM32_DMA1_CHAN5 - -# define DMACHAN_USART2_RX STM32_DMA1_CHAN6 -# define DMACHAN_I2C1_TX STM32_DMA1_CHAN6 -# define DMACHAN_TIM1_CH3 STM32_DMA1_CHAN6 -# define DMACHAN_TIM3_CH1 STM32_DMA1_CHAN6 -# define DMACHAN_TIM3_TRIG STM32_DMA1_CHAN6 -# define DMACHAN_TIM16_CH1 STM32_DMA1_CHAN6 -# define DMACHAN_TIM16_UP STM32_DMA1_CHAN6 - -# define DMACHAN_USART2_TX STM32_DMA1_CHAN7 -# define DMACHAN_I2C1_RX STM32_DMA1_CHAN7 -# define DMACHAN_TIM2_CH2 STM32_DMA1_CHAN7 -# define DMACHAN_TIM2_CH4 STM32_DMA1_CHAN7 -# define DMACHAN_TIM4_UP STM32_DMA1_CHAN7 -# define DMACHAN_TIM17_CH1_2 STM32_DMA1_CHAN7 -# define DMACHAN_TIM17_UP_2 STM32_DMA1_CHAN7 - -# define DMACHAN_ADC2_1 STM32_DMA2_CHAN1 -# define DMACHAN_SPI3_RX STM32_DMA2_CHAN1 -# define DMACHAN_I2S3_RX STM32_DMA2_CHAN1 -# define DMACHAN_TIM8_CH3 STM32_DMA2_CHAN1 -# define DMACHAN_TIM8_UP STM32_DMA2_CHAN1 - -# define DMACHAN_ADC4_1 STM32_DMA2_CHAN2 -# define DMACHAN_SPI3_TX STM32_DMA2_CHAN2 -# define DMACHAN_I2S3_TX STM32_DMA2_CHAN2 -# define DMACHAN_TIM8_CH4 STM32_DMA2_CHAN2 -# define DMACHAN_TIM8_TRIG STM32_DMA2_CHAN2 -# define DMACHAN_TIM8_COM STM32_DMA2_CHAN2 - -# define DMACHAN_ADC2_2 STM32_DMA2_CHAN3 -# define DMACHAN_UART4_RX STM32_DMA2_CHAN3 -# define DMACHAN_TIM6_UP STM32_DMA2_CHAN3 -# define DMACHAN_DAC1_CH1_2 STM32_DMA2_CHAN3 -# define DMACHAN_TIM8_CH1 STM32_DMA2_CHAN3 - -# define DMACHAN_ADC4_2 STM32_DMA2_CHAN4 -# define DMACHAN_TIM7_UP_2 STM32_DMA2_CHAN4 -# define DMACHAN_DAC1_CH2_2 STM32_DMA2_CHAN4 - -# define DMACHAN_ADC3 STM32_DMA2_CHAN5 -# define DMACHAN_UART4_TX STM32_DMA2_CHAN5 -# define DMACHAN_TIM8_CH2 STM32_DMA2_CHAN5 - -#elif defined(CONFIG_STM32_STM32F33XX) - -# define DMACHAN_ADC1 STM32_DMA1_CHAN1 -# define DMACHAN_TIM2_CH3 STM32_DMA1_CHAN1 -# define DMACHAN_TIM17_CH1_1 STM32_DMA1_CHAN1 -# define DMACHAN_TIM17_UP_1 STM32_DMA1_CHAN1 - -# define DMACHAN_ADC2_1 STM32_DMA1_CHAN2 -# define DMACHAN_SPI1_RX_1 STM32_DMA1_CHAN2 -# define DMACHAN_USART3_TX STM32_DMA1_CHAN2 -# define DMACHAN_I2C1_TX_3 STM32_DMA1_CHAN4 -# define DMACHAN_TIM1_CH1 STM32_DMA1_CHAN2 -# define DMACHAN_TIM2_UP STM32_DMA1_CHAN2 -# define DMACHAN_TIM3_CH3 STM32_DMA1_CHAN2 -# define DMACHAN_HRTIM1_M STM32_DMA1_CHAN2 - -# define DMACHAN_SPI1_TX_1 STM32_DMA1_CHAN3 -# define DMACHAN_USART3_RX STM32_DMA1_CHAN3 -# define DMACHAN_I2C1_RX_2 STM32_DMA1_CHAN3 -# define DMACHAN_TIM3_CH4 STM32_DMA1_CHAN3 -# define DMACHAN_TIM3_UP STM32_DMA1_CHAN3 -# define DMACHAN_TIM6_UP STM32_DMA1_CHAN3 -# define DMACHAN_DAC1_CH1 STM32_DMA1_CHAN3 -# define DMACHAN_TIM16_CH1_1 STM32_DMA1_CHAN3 -# define DMACHAN_TIM16_UP_1 STM32_DMA1_CHAN3 -# define DMACHAN_HRTIM1_A STM32_DMA1_CHAN3 - -# define DMACHAN_ADC2_2 STM32_DMA1_CHAN4 -# define DMACHAN_SPI1_RX_2 STM32_DMA1_CHAN4 -# define DMACHAN_USART1_TX STM32_DMA1_CHAN4 -# define DMACHAN_I2C1_TX_3 STM32_DMA1_CHAN4 -# define DMACHAN_TIM1_CH4 STM32_DMA1_CHAN4 -# define DMACHAN_TIM1_TRIG STM32_DMA1_CHAN4 -# define DMACHAN_TIM1_COM STM32_DMA1_CHAN4 -# define DMACHAN_TIM7_UP STM32_DMA1_CHAN4 -# define DMACHAN_DAC1_CH2 STM32_DMA1_CHAN4 -# define DMACHAN_HRTIM1_B STM32_DMA1_CHAN4 - -# define DMACHAN_SPI1_TX_2 STM32_DMA1_CHAN5 -# define DMACHAN_USART1_RX STM32_DMA1_CHAN5 -# define DMACHAN_I2C1_RX_3 STM32_DMA1_CHAN5 -# define DMACHAN_TIM1_UP STM32_DMA1_CHAN5 -# define DMACHAN_TIM2_CH1 STM32_DMA1_CHAN5 -# define DMACHAN_DAC2_CH1 STM32_DMA1_CHAN5 -# define DMACHAN_TIM15_CH1 STM32_DMA1_CHAN5 -# define DMACHAN_TIM15_UP STM32_DMA1_CHAN5 -# define DMACHAN_TIM15_TRIG STM32_DMA1_CHAN5 -# define DMACHAN_TIM15_COM STM32_DMA1_CHAN5 -# define DMACHAN_HRTIM1_C STM32_DMA1_CHAN5 - -# define DMACHAN_SPI1_RX_3 STM32_DMA1_CHAN6 -# define DMACHAN_USART2_RX STM32_DMA1_CHAN6 -# define DMACHAN_I2C1_TX_1 STM32_DMA1_CHAN6 -# define DMACHAN_TIM1_CH3 STM32_DMA1_CHAN6 -# define DMACHAN_TIM3_CH1 STM32_DMA1_CHAN6 -# define DMACHAN_TIM3_TRIG STM32_DMA1_CHAN6 -# define DMACHAN_TIM16_CH1_2 STM32_DMA1_CHAN6 -# define DMACHAN_TIM16_UP_2 STM32_DMA1_CHAN6 -# define DMACHAN_HRTIM1_D STM32_DMA1_CHAN6 - -# define DMACHAN_SPI1_TX_3 STM32_DMA1_CHAN7 -# define DMACHAN_USART2_TX STM32_DMA1_CHAN7 -# define DMACHAN_I2C1_RX_1 STM32_DMA1_CHAN7 -# define DMACHAN_TIM2_CH2 STM32_DMA1_CHAN7 -# define DMACHAN_TIM2_CH4 STM32_DMA1_CHAN7 -# define DMACHAN_TIM17_CH1_2 STM32_DMA1_CHAN7 -# define DMACHAN_TIM17_UP_2 STM32_DMA1_CHAN7 -# define DMACHAN_HRTIM1_E STM32_DMA1_CHAN7 - -#elif defined(CONFIG_STM32_STM32F37XX) - -# define DMACHAN_ADC1 STM32_DMA1_CHAN1 -# define DMACHAN_TIM2_CH3 STM32_DMA1_CHAN1 -# define DMACHAN_TIM4_CH1 STM32_DMA1_CHAN1 -# define DMACHAN_TIM17_CH1 STM32_DMA1_CHAN1 -# define DMACHAN_TIM17_UP STM32_DMA1_CHAN1 - -# define DMACHAN_SPI1_RX STM32_DMA1_CHAN2 -# define DMACHAN_USART3_TX STM32_DMA1_CHAN2 -# define DMACHAN_TIM2_UP STM32_DMA1_CHAN2 -# define DMACHAN_TIM3_CH3 STM32_DMA1_CHAN2 -# define DMACHAN_TIM19_CH1 STM32_DMA1_CHAN2 - -# define DMACHAN_SPI1_TX STM32_DMA1_CHAN3 -# define DMACHAN_USART3_RX STM32_DMA1_CHAN3 -# define DMACHAN_TIM3_CH4 STM32_DMA1_CHAN3 -# define DMACHAN_TIM3_UP STM32_DMA1_CHAN3 -# define DMACHAN_TIM6_UP STM32_DMA1_CHAN3 -# define DMACHAN_DAC1_CH1 STM32_DMA1_CHAN3 -# define DMACHAN_TIM16_CH1 STM32_DMA1_CHAN3 -# define DMACHAN_TIM16_UP STM32_DMA1_CHAN3 -# define DMACHAN_TIM19_CH2 STM32_DMA1_CHAN3 - -# define DMACHAN_SPI2_RX STM32_DMA1_CHAN4 -# define DMACHAN_USART1_TX STM32_DMA1_CHAN4 -# define DMACHAN_I2C2_TX STM32_DMA1_CHAN4 -# define DMACHAN_TIM4_CH2 STM32_DMA1_CHAN4 -# define DMACHAN_TIM7_UP STM32_DMA1_CHAN4 -# define DMACHAN_DAC1_CH2 STM32_DMA1_CHAN4 -# define DMACHAN_TIM19_UP STM32_DMA1_CHAN4 - -# define DMACHAN_SPI2_TX STM32_DMA1_CHAN5 -# define DMACHAN_USART1_RX STM32_DMA1_CHAN5 -# define DMACHAN_I2C2_RX STM32_DMA1_CHAN5 -# define DMACHAN_TIM2_CH1 STM32_DMA1_CHAN5 -# define DMACHAN_TIM4_CH3 STM32_DMA1_CHAN5 -# define DMACHAN_TIM18_UP STM32_DMA1_CHAN5 -# define DMACHAN_DAC2_CH1 STM32_DMA1_CHAN5 -# define DMACHAN_TIM15_CH1 STM32_DMA1_CHAN5 -# define DMACHAN_TIM15_UP STM32_DMA1_CHAN5 -# define DMACHAN_TIM15_TRIG STM32_DMA1_CHAN5 -# define DMACHAN_TIM15_COM STM32_DMA1_CHAN5 - -# define DMACHAN_USART2_RX STM32_DMA1_CHAN6 -# define DMACHAN_I2C1_TX STM32_DMA1_CHAN6 -# define DMACHAN_TIM3_CH1 STM32_DMA1_CHAN6 -# define DMACHAN_TIM3_TRIG STM32_DMA1_CHAN6 -# define DMACHAN_TIM16_CH1_2 STM32_DMA1_CHAN6 -# define DMACHAN_TIM16_UP_2 STM32_DMA1_CHAN6 - -# define DMACHAN_USART2_TX STM32_DMA1_CHAN7 -# define DMACHAN_I2C1_RX STM32_DMA1_CHAN6 -# define DMACHAN_TIM2_CH2 STM32_DMA1_CHAN6 -# define DMACHAN_TIM2_CH4 STM32_DMA1_CHAN6 -# define DMACHAN_TIM4_UP STM32_DMA1_CHAN6 -# define DMACHAN_TIM17_CH1_2 STM32_DMA1_CHAN6 -# define DMACHAN_TIM17_UP_2 STM32_DMA1_CHAN6 - -# define DMACHAN_SPI3_RX STM32_DMA2_CHAN1 -# define DMACHAN_TIM5_CH4 STM32_DMA2_CHAN1 -# define DMACHAN_TIM5_TRIG STM32_DMA2_CHAN1 - -# define DMACHAN_SPI3_TX STM32_DMA2_CHAN2 -# define DMACHAN_TIM5_CH3 STM32_DMA2_CHAN2 -# define DMACHAN_TIM5_UP STM32_DMA2_CHAN2 - -# define DMACHAN_SDADC1 STM32_DMA2_CHAN3 -# define DMACHAN_TIM6_UP_2 STM32_DMA2_CHAN3 -# define DMACHAN_DAC1_CH1_2 STM32_DMA2_CHAN3 - -# define DMACHAN_SDADC2 STM32_DMA2_CHAN4 -# define DMACHAN_TIM5_CH2 STM32_DMA2_CHAN4 -# define DMACHAN_TIM7_UP_2 STM32_DMA2_CHAN4 -# define DMACHAN_DAC1_CH2_2 STM32_DMA2_CHAN4 - -# define DMACHAN_SDADC3 STM32_DMA2_CHAN5 -# define DMACHAN_TIM5_CH1 STM32_DMA2_CHAN5 -# define DMACHAN_TIM18_UP_2 STM32_DMA2_CHAN5 -# define DMACHAN_DAC2_CH1_2 STM32_DMA2_CHAN5 - -#elif defined(CONFIG_STM32_STM32G4XXX) - -/* This family uses a DMAMUX. The code to support this needs to be ported - * to this family from STM32L4R. - */ - -#else -# error "Unknown DMA channel assignments" -#endif - -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_DMA_V1_H */ diff --git a/arch/arm/src/stm32/hardware/stm32_dmamux.h b/arch/arm/src/stm32/hardware/stm32_dmamux.h deleted file mode 100644 index 18fd66b1498f2..0000000000000 --- a/arch/arm/src/stm32/hardware/stm32_dmamux.h +++ /dev/null @@ -1,179 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/hardware/stm32_dmamux.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_DMAMUX_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_DMAMUX_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include "chip.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#define DMAMUX1 0 - -/* Register Offsets *********************************************************/ - -#define STM32_DMAMUX_CXCR_OFFSET(x) (0x0000 + (0x0004 * (x))) /* DMAMUX1 request line multiplexer channel x configuration register */ -#define STM32_DMAMUX_C0CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(0) /* 0x000 */ -#define STM32_DMAMUX_C1CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(1) /* 0x004 */ -#define STM32_DMAMUX_C2CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(2) /* 0x008 */ -#define STM32_DMAMUX_C3CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(3) /* 0x00c */ -#define STM32_DMAMUX_C4CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(4) /* 0x010 */ -#define STM32_DMAMUX_C5CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(5) /* 0x014 */ -#define STM32_DMAMUX_C6CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(6) /* 0x018 */ -#define STM32_DMAMUX_C7CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(7) /* 0x01c */ -#define STM32_DMAMUX_C8CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(8) /* 0x020 */ -#define STM32_DMAMUX_C9CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(9) /* 0x024 */ -#define STM32_DMAMUX_C10CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(10) /* 0x028 */ -#define STM32_DMAMUX_C11CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(11) /* 0x02c */ -#define STM32_DMAMUX_C12CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(12) /* 0x030 */ -#define STM32_DMAMUX_C13CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(13) /* 0x034 */ -#define STM32_DMAMUX_C14CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(14) /* 0x038 */ -#define STM32_DMAMUX_C15CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(15) /* 0x03c */ - /* 0x040-0x07C: Reserved */ -#define STM32_DMAMUX_CSR_OFFSET 0x0080 /* DMAMUX1 request line multiplexer interrupt channel status register */ -#define STM32_DMAMUX_CFR_OFFSET 0x0084 /* DMAMUX1 request line multiplexer interrupt clear flag register */ - /* 0x088-0x0FC: Reserved */ -#define STM32_DMAMUX_RGXCR_OFFSET(x) (0x0100 + (0x004 * (x))) /* DMAMUX1 request generator channel x configuration register */ -#define STM32_DMAMUX_RG0CR_OFFSET STM32_DMAMUX_RGXCR_OFFSET(0) -#define STM32_DMAMUX_RG1CR_OFFSET STM32_DMAMUX_RGXCR_OFFSET(1) -#define STM32_DMAMUX_RG2CR_OFFSET STM32_DMAMUX_RGXCR_OFFSET(2) -#define STM32_DMAMUX_RG3CR_OFFSET STM32_DMAMUX_RGXCR_OFFSET(3) -#define STM32_DMAMUX_RGSR_OFFSET 0x0140 /* DMAMUX1 request generator interrupt status register */ -#define STM32_DMAMUX_RGCFR_OFFSET 0x0144 /* DMAMUX1 request generator interrupt clear flag register */ - /* 0x148-0x3FC: Reserved */ - -/* Register Addresses *******************************************************/ - -#define STM32_DMAMUX1_CXCR(x) (STM32_DMAMUX1_BASE + STM32_DMAMUX_CXCR_OFFSET(x)) -#define STM32_DMAMUX1_C0CR (STM32_DMAMUX1_BASE + STM32_DMAMUX_C0CR_OFFSET) -#define STM32_DMAMUX1_C1CR (STM32_DMAMUX1_BASE + STM32_DMAMUX_C1CR_OFFSET) -#define STM32_DMAMUX1_C2CR (STM32_DMAMUX1_BASE + STM32_DMAMUX_C2CR_OFFSET) -#define STM32_DMAMUX1_C3CR (STM32_DMAMUX1_BASE + STM32_DMAMUX_C3CR_OFFSET) -#define STM32_DMAMUX1_C4CR (STM32_DMAMUX1_BASE + STM32_DMAMUX_C4CR_OFFSET) -#define STM32_DMAMUX1_C5CR (STM32_DMAMUX1_BASE + STM32_DMAMUX_C5CR_OFFSET) -#define STM32_DMAMUX1_C6CR (STM32_DMAMUX1_BASE + STM32_DMAMUX_C6CR_OFFSET) -#define STM32_DMAMUX1_C7CR (STM32_DMAMUX1_BASE + STM32_DMAMUX_C7CR_OFFSET) -#define STM32_DMAMUX1_C8CR (STM32_DMAMUX1_BASE + STM32_DMAMUX_C8CR_OFFSET) -#define STM32_DMAMUX1_C9CR (STM32_DMAMUX1_BASE + STM32_DMAMUX_C9CR_OFFSET) -#define STM32_DMAMUX1_C10CR (STM32_DMAMUX1_BASE + STM32_DMAMUX_C10CR_OFFSET) -#define STM32_DMAMUX1_C11CR (STM32_DMAMUX1_BASE + STM32_DMAMUX_C11CR_OFFSET) -#define STM32_DMAMUX1_C12CR (STM32_DMAMUX1_BASE + STM32_DMAMUX_C12CR_OFFSET) -#define STM32_DMAMUX1_C13CR (STM32_DMAMUX1_BASE + STM32_DMAMUX_C13CR_OFFSET) -#define STM32_DMAMUX1_C14CR (STM32_DMAMUX1_BASE + STM32_DMAMUX_C14CR_OFFSET) -#define STM32_DMAMUX1_C15CR (STM32_DMAMUX1_BASE + STM32_DMAMUX_C15CR_OFFSET) - -#define STM32_DMAMUX1_CSR (STM32_DMAMUX1_BASE + STM32_DMAMUX_CSR_OFFSET) -#define STM32_DMAMUX1_CFR (STM32_DMAMUX1_BASE + STM32_DMAMUX_CFR_OFFSET) - -#define STM32_DMAMUX1_RGXCR(x) (STM32_DMAMUX1_BASE + STM32_DMAMUX_RGXCR_OFFSET(x)) -#define STM32_DMAMUX1_RG0CR (STM32_DMAMUX1_BASE + STM32_DMAMUX_RG0CR_OFFSET) -#define STM32_DMAMUX1_RG1CR (STM32_DMAMUX1_BASE + STM32_DMAMUX_RG1CR_OFFSET) -#define STM32_DMAMUX1_RG2CR (STM32_DMAMUX1_BASE + STM32_DMAMUX_RG2CR_OFFSET) -#define STM32_DMAMUX1_RG3CR (STM32_DMAMUX1_BASE + STM32_DMAMUX_RG3CR_OFFSET) - -#define STM32_DMAMUX1_RGSR (STM32_DMAMUX1_BASE + STM32_DMAMUX_RGSR_OFFSET) -#define STM32_DMAMUX1_RGCFR (STM32_DMAMUX1_BASE + STM32_DMAMUX_RGCFR_OFFSET) - -/* Register Bitfield Definitions ********************************************/ - -/* DMAMUX1 CxCR - request line multiplexer channel x configuration register */ - -#define DMAMUX_CCR_DMAREQID_SHIFT (0) /* Bits 0-6: DMA request identification */ -#define DMAMUX_CCR_DMAREQID_MASK (0x7f << DMAMUX_CCR_DMAREQID_SHIFT) -# define DMAMUX_CCR_DMAREQID(x) ((x) << DMAMUX_CCR_DMAREQID_SHIFT) -#define DMAMUX_CCR_SOIE (8) /* Bit 8: Synchronization overrun interrupt enable */ -#define DMAMUX_CCR_EGE (9) /* Bit 9: Event generation enable */ -#define DMAMUX_CCR_SE (16) /* Bit 16: Synchronization enable */ -#define DMAMUX_CCR_SPOL_SHIFT (17) /* Bits 17-18: Synchronization polarity */ -#define DMAMUX_CCR_SPOL_MASK (3 << DMAMUX_CCR_SPOL_SHIFT) -# define DMAMUX_CCR_SPOL_NONE (0x0 << DMAMUX_CCR_SPOL_SHIFT) /* No event: No trigger detection or generation */ -# define DMAMUX_CCR_SPOL_RISING (0x1 << DMAMUX_CCR_SPOL_SHIFT) /* Rising edge */ -# define DMAMUX_CCR_SPOL_FALLING (0x2 << DMAMUX_CCR_SPOL_SHIFT) /* Falling edge */ -# define DMAMUX_CCR_SPOL_BOTH (0x3 << DMAMUX_CCR_SPOL_SHIFT) /* Both rising and falling edges */ -#define DMAMUX_CCR_NBREQ_SHIFT (19) /* Bits 19-23: Number of DMA request - 1 to forward */ -#define DMAMUX_CCR_NBREQ_MASK (0x1f << DMAMUX_CCR_NBREQ_SHIFT) -#define DMAMUX_CCR_SYNCID_SHIFT (24) /* Bits 24-26: Synchronization identification */ -#define DMAMUX_CCR_SYNCID_MASK (7 << DMAMUX_CCR_SYNCID_SHIFT) - -/* DMAMUX1 CSR - request line multiplexer interrupt channel status register */ - -#define DMAMUX1_CSR_SOF(x) (1 << (x)) /* Synchronization overrun event flag */ - -/* DMAMUX1 CFR - request line multiplexer interrupt clear flag register */ - -#define DMAMUX1_CFR_SOF(x) (1 << (x)) /* Clear synchronization overrun event flag */ - -/* DMAMUX1 RGCR - request generator channel x configuration register */ - -#define DMAMUX_RGCR_SIGID_SHIFT (0) /* Bits 0-4: Signal identification */ -#define DMAMUX_RGCR_SIGID_MASK (0x1f << DMAMUX_RGCR_SIGID_SHIFT) -#define DMAMUX_RGCR_OIE (8) /* Bit 8: Trigger overrun interrupt enable */ -#define DMAMUX_RGCR_GE (16) /* Bit 16: DMA request generator channel X enable*/ -#define DMAMUX_RGCR_GPOL_SHIFT (17) /* Bits 17-18: DMA request generator trigger polarity */ -#define DMAMUX_RGCR_GPOL_MASK (0x3 << DMAMUX_RGCR_GPOL_SHIFT) -# define DMAMUX_RGCR_GPOL_NONE (0x0 << DMAMUX_RGCR_GPOL_SHIFT) /* No event: No trigger detection or generation */ -# define DMAMUX_RGCR_GPOL_RISING (0x1 << DMAMUX_RGCR_GPOL_SHIFT) /* Rising edge */ -# define DMAMUX_RGCR_GPOL_FALLING (0x2 << DMAMUX_RGCR_GPOL_SHIFT) /* Falling edge */ -# define DMAMUX_RGCR_GPOL_BOTH (0x3 << DMAMUX_RGCR_GPOL_SHIFT) /* Both rising and falling edges */ -#define DMAMUX_RGCR_GNBREQ_SHIFT (19) /* Bits 19-23: Number of DMA requests to be generated -1 */ -#define DMAMUX_RGCR_GNBREQ_MASK (0x1f << DMAMUX_RGCR_GNBREQ_SHIFT) - -/* DMAMUX1 RGSR - request generator interrupt status register */ - -#define DMAMUX1_RGSR_OF(x) (1 << (x)) /* Trigger overrun event flag */ - -/* DMAMUX1 RGCFR - request generator interrupt clear flag register */ - -#define DMAMUX1_RGCFR_COF(x) (1 << (x)) /* Clear trigger overrun event flag */ - -/* DMA channel mapping - * - * XXXXX.DDD.CCCCCCCC - * C - DMAMUX request - * D - DMA controller - * X - free bits - */ - -#define DMAMAP_MAP(d,c) ((d) << 8 | (c)) -#define DMAMAP_CONTROLLER(m) ((m) >> 8 & 0x07) -#define DMAMAP_REQUEST(m) ((m) >> 0 & 0xff) - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -/* Import DMAMUX map */ - -#if defined(CONFIG_STM32_STM32G4XXX) -# include "hardware/stm32g4xxxx_dmamux.h" -#else -# error "Unsupported STM32 sub family" -#endif - -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_DMAMUX_H */ diff --git a/arch/arm/src/stm32/hardware/stm32_eth.h b/arch/arm/src/stm32/hardware/stm32_eth.h deleted file mode 100644 index d95a6441c49a2..0000000000000 --- a/arch/arm/src/stm32/hardware/stm32_eth.h +++ /dev/null @@ -1,877 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/hardware/stm32_eth.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_ETH_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_ETH_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "chip.h" - -#if STM32_NETHERNET > 0 - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Register Offsets *********************************************************/ - -/* MAC Registers */ - -#define STM32_ETH_MACCR_OFFSET 0x0000 /* Ethernet MAC configuration register */ -#define STM32_ETH_MACFFR_OFFSET 0x0004 /* Ethernet MAC frame filter register */ -#define STM32_ETH_MACHTHR_OFFSET 0x0008 /* Ethernet MAC hash table high register */ -#define STM32_ETH_MACHTLR_OFFSET 0x000c /* Ethernet MAC hash table low register */ -#define STM32_ETH_MACMIIAR_OFFSET 0x0010 /* Ethernet MAC MII address register */ -#define STM32_ETH_MACMIIDR_OFFSET 0x0014 /* Ethernet MAC MII data register */ -#define STM32_ETH_MACFCR_OFFSET 0x0018 /* Ethernet MAC flow control register */ -#define STM32_ETH_MACVLANTR_OFFSET 0x001c /* Ethernet MAC VLAN tag register */ -#define STM32_ETH_MACRWUFFR_OFFSET 0x0028 /* Ethernet MAC remote wakeup frame filter reg */ -#define STM32_ETH_MACPMTCSR_OFFSET 0x002c /* Ethernet MAC PMT control and status register */ -#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) -# define STM32_ETH_MACDBGR_OFFSET 0x0034 /* Ethernet MAC debug register */ -#endif -#define STM32_ETH_MACSR_OFFSET 0x0038 /* Ethernet MAC interrupt status register */ -#define STM32_ETH_MACIMR_OFFSET 0x003c /* Ethernet MAC interrupt mask register */ -#define STM32_ETH_MACA0HR_OFFSET 0x0040 /* Ethernet MAC address 0 high register */ -#define STM32_ETH_MACA0LR_OFFSET 0x0044 /* Ethernet MAC address 0 low register */ -#define STM32_ETH_MACA1HR_OFFSET 0x0048 /* Ethernet MAC address 1 high register */ -#define STM32_ETH_MACA1LR_OFFSET 0x004c /* Ethernet MAC address1 low register */ -#define STM32_ETH_MACA2HR_OFFSET 0x0050 /* Ethernet MAC address 2 high register */ -#define STM32_ETH_MACA2LR_OFFSET 0x0054 /* Ethernet MAC address 2 low register */ -#define STM32_ETH_MACA3HR_OFFSET 0x0058 /* Ethernet MAC address 3 high register */ -#define STM32_ETH_MACA3LR_OFFSET 0x005c /* Ethernet MAC address 3 low register */ - -/* MMC Registers */ - -#define STM32_ETH_MMCCR_OFFSET 0x0100 /* Ethernet MMC control register */ -#define STM32_ETH_MMCRIR_OFFSET 0x0104 /* Ethernet MMC receive interrupt register */ -#define STM32_ETH_MMCTIR_OFFSET 0x0108 /* Ethernet MMC transmit interrupt register */ -#define STM32_ETH_MMCRIMR_OFFSET 0x010c /* Ethernet MMC receive interrupt mask register */ -#define STM32_ETH_MMCTIMR_OFFSET 0x0110 /* Ethernet MMC transmit interrupt mask register */ -#define STM32_ETH_MMCTGFSCCR_OFFSET 0x014c /* Ethernet MMC transmitted good frames counter register (single collision) */ -#define STM32_ETH_MMCTGFMSCCR_OFFSET 0x0150 /* Ethernet MMC transmitted good frames counter register (multiple-collision) */ -#define STM32_ETH_MMCTGFCR_OFFSET 0x0168 /* Ethernet MMC transmitted good frames counter register */ -#define STM32_ETH_MMCRFCECR_OFFSET 0x0194 /* Ethernet MMC received frames with CRC error counter register */ -#define STM32_ETH_MMCRFAECR_OFFSET 0x0198 /* Ethernet MMC received frames with alignment error counter */ -#define STM32_ETH_MMCRGUFCR_OFFSET 0x01c4 /* MMC received good unicast frames counter register */ - -/* IEEE 1588 time stamp registers */ - -#define STM32_ETH_PTPTSCR_OFFSET 0x0700 /* Ethernet PTP time stamp control register */ -#define STM32_ETH_PTPSSIR_OFFSET 0x0704 /* Ethernet PTP subsecond increment register */ -#define STM32_ETH_PTPTSHR_OFFSET 0x0708 /* Ethernet PTP time stamp high register */ -#define STM32_ETH_PTPTSLR_OFFSET 0x070c /* Ethernet PTP time stamp low register */ -#define STM32_ETH_PTPTSHUR_OFFSET 0x0710 /* Ethernet PTP time stamp high update register */ -#define STM32_ETH_PTPTSLUR_OFFSET 0x0714 /* Ethernet PTP time stamp low update register */ -#define STM32_ETH_PTPTSAR_OFFSET 0x0718 /* Ethernet PTP time stamp addend register */ -#define STM32_ETH_PTPTTHR_OFFSET 0x071c /* Ethernet PTP target time high register */ -#define STM32_ETH_PTPTTLR_OFFSET 0x0720 /* Ethernet PTP target time low register */ -#define STM32_ETH_PTPTSSR_OFFSET 0x0728 /* Ethernet PTP time stamp status register */ -#define STM32_ETH_PTPPPSCR_OFFSET 0x072c /* Ethernet PTP PPS control register */ - -/* DMA Registers */ - -#define STM32_ETH_DMABMR_OFFSET 0x1000 /* Ethernet DMA bus mode register */ -#define STM32_ETH_DMATPDR_OFFSET 0x1004 /* Ethernet DMA transmit poll demand register */ -#define STM32_ETH_DMARPDR_OFFSET 0x1008 /* Ethernet DMA receive poll demand register */ -#define STM32_ETH_DMARDLAR_OFFSET 0x100c /* Ethernet DMA receive descriptor list address register */ -#define STM32_ETH_DMATDLAR_OFFSET 0x1010 /* Ethernet DMA transmit descriptor list address register */ -#define STM32_ETH_DMASR_OFFSET 0x1014 /* Ethernet DMA status register */ -#define STM32_ETH_DMAOMR_OFFSET 0x1018 /* Ethernet DMA operation mode register */ -#define STM32_ETH_DMAIER_OFFSET 0x101c /* Ethernet DMA interrupt enable register */ -#define STM32_ETH_DMAMFBOC_OFFSET 0x1020 /* Ethernet DMA missed frame and buffer overflow counter register */ -#define STM32_ETH_DMARSWTR_OFFSET 0x1024 /* Ethernet DMA receive status watchdog timer register */ -#define STM32_ETH_DMACHTDR_OFFSET 0x1048 /* Ethernet DMA current host transmit descriptor register */ -#define STM32_ETH_DMACHRDR_OFFSET 0x104c /* Ethernet DMA current host receive descriptor register */ -#define STM32_ETH_DMACHTBAR_OFFSET 0x1050 /* Ethernet DMA current host transmit buffer address register */ -#define STM32_ETH_DMACHRBAR_OFFSET 0x1054 /* Ethernet DMA current host receive buffer address register */ - -/* Register Base Addresses **************************************************/ - -/* MAC Registers */ - -#define STM32_ETH_MACCR (STM32_ETHERNET_BASE+STM32_ETH_MACCR_OFFSET) -#define STM32_ETH_MACFFR (STM32_ETHERNET_BASE+STM32_ETH_MACFFR_OFFSET) -#define STM32_ETH_MACHTHR (STM32_ETHERNET_BASE+STM32_ETH_MACHTHR_OFFSET) -#define STM32_ETH_MACHTLR (STM32_ETHERNET_BASE+STM32_ETH_MACHTLR_OFFSET) -#define STM32_ETH_MACMIIAR (STM32_ETHERNET_BASE+STM32_ETH_MACMIIAR_OFFSET) -#define STM32_ETH_MACMIIDR (STM32_ETHERNET_BASE+STM32_ETH_MACMIIDR_OFFSET) -#define STM32_ETH_MACFCR (STM32_ETHERNET_BASE+STM32_ETH_MACFCR_OFFSET) -#define STM32_ETH_MACVLANTR (STM32_ETHERNET_BASE+STM32_ETH_MACVLANTR_OFFSET) -#define STM32_ETH_MACRWUFFR (STM32_ETHERNET_BASE+STM32_ETH_MACRWUFFR_OFFSET) -#define STM32_ETH_MACPMTCSR (STM32_ETHERNET_BASE+STM32_ETH_MACPMTCSR_OFFSET) -#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) -# define STM32_ETH_MACDBGR (STM32_ETHERNET_BASE+STM32_ETH_MACDBGR_OFFSET) -#endif -#define STM32_ETH_MACSR (STM32_ETHERNET_BASE+STM32_ETH_MACSR_OFFSET) -#define STM32_ETH_MACIMR (STM32_ETHERNET_BASE+STM32_ETH_MACIMR_OFFSET) -#define STM32_ETH_MACA0HR (STM32_ETHERNET_BASE+STM32_ETH_MACA0HR_OFFSET) -#define STM32_ETH_MACA0LR (STM32_ETHERNET_BASE+STM32_ETH_MACA0LR_OFFSET) -#define STM32_ETH_MACA1HR (STM32_ETHERNET_BASE+STM32_ETH_MACA1HR_OFFSET) -#define STM32_ETH_MACA1LR (STM32_ETHERNET_BASE+STM32_ETH_MACA1LR_OFFSET) -#define STM32_ETH_MACA2HR (STM32_ETHERNET_BASE+STM32_ETH_MACA2HR_OFFSET) -#define STM32_ETH_MACA2LR (STM32_ETHERNET_BASE+STM32_ETH_MACA2LR_OFFSET) -#define STM32_ETH_MACA3HR (STM32_ETHERNET_BASE+STM32_ETH_MACA3HR_OFFSET) -#define STM32_ETH_MACA3LR (STM32_ETHERNET_BASE+STM32_ETH_MACA3LR_OFFSET) - -/* MMC Registers */ - -#define STM32_ETH_MMCC (STM32_ETHERNET_BASE+STM32_ETH_MMCCR_OFFSET) -#define STM32_ETH_MMCRIR (STM32_ETHERNET_BASE+STM32_ETH_MMCRIR_OFFSET) -#define STM32_ETH_MMCTIR (STM32_ETHERNET_BASE+STM32_ETH_MMCTIR_OFFSET) -#define STM32_ETH_MMCRIMR (STM32_ETHERNET_BASE+STM32_ETH_MMCRIMR_OFFSET) -#define STM32_ETH_MMCTIMR (STM32_ETHERNET_BASE+STM32_ETH_MMCTIMR_OFFSET) -#define STM32_ETH_MMCTGFSCCR (STM32_ETHERNET_BASE+STM32_ETH_MMCTGFSCCR_OFFSET) -#define STM32_ETH_MMCTGFMSCCR (STM32_ETHERNET_BASE+STM32_ETH_MMCTGFMSCCR_OFFSET) -#define STM32_ETH_MMCTGFCR (STM32_ETHERNET_BASE+STM32_ETH_MMCTGFCR_OFFSET) -#define STM32_ETH_MMCRFCECR (STM32_ETHERNET_BASE+STM32_ETH_MMCRFCECR_OFFSET) -#define STM32_ETH_MMCRFAECR (STM32_ETHERNET_BASE+STM32_ETH_MMCRFAECR_OFFSET) -#define STM32_ETH_MMCRGUFCR (STM32_ETHERNET_BASE+STM32_ETH_MMCRGUFCR_OFFSET) - -/* IEEE 1588 time stamp registers */ - -#define STM32_ETH_PTPTSCR (STM32_ETHERNET_BASE+STM32_ETH_PTPTSCR_OFFSET) -#define STM32_ETH_PTPSSIR (STM32_ETHERNET_BASE+STM32_ETH_PTPSSIR_OFFSET) -#define STM32_ETH_PTPTSHR (STM32_ETHERNET_BASE+STM32_ETH_PTPTSHR_OFFSET) -#define STM32_ETH_PTPTSLR (STM32_ETHERNET_BASE+STM32_ETH_PTPTSLR_OFFSET) -#define STM32_ETH_PTPTSHUR (STM32_ETHERNET_BASE+STM32_ETH_PTPTSHUR_OFFSET) -#define STM32_ETH_PTPTSLUR (STM32_ETHERNET_BASE+STM32_ETH_PTPTSLUR_OFFSET) -#define STM32_ETH_PTPTSAR (STM32_ETHERNET_BASE+STM32_ETH_PTPTSAR_OFFSET) -#define STM32_ETH_PTPTTHR (STM32_ETHERNET_BASE+STM32_ETH_PTPTTHR_OFFSET) -#define STM32_ETH_PTPTTLR (STM32_ETHERNET_BASE+STM32_ETH_PTPTTLR_OFFSET) -#define STM32_ETH_PTPTSSR (STM32_ETHERNET_BASE+STM32_ETH_PTPTSSR_OFFSET) -#define STM32_ETH_PTPPPSCR (STM32_ETHERNET_BASE+STM32_ETH_PTPPPSCR_OFFSET) - -/* DMA Registers */ - -#define STM32_ETH_DMABMR (STM32_ETHERNET_BASE+STM32_ETH_DMABMR_OFFSET) -#define STM32_ETH_DMATPDR (STM32_ETHERNET_BASE+STM32_ETH_DMATPDR_OFFSET) -#define STM32_ETH_DMARPDR (STM32_ETHERNET_BASE+STM32_ETH_DMARPDR_OFFSET) -#define STM32_ETH_DMARDLAR (STM32_ETHERNET_BASE+STM32_ETH_DMARDLAR_OFFSET) -#define STM32_ETH_DMATDLAR (STM32_ETHERNET_BASE+STM32_ETH_DMATDLAR_OFFSET) -#define STM32_ETH_DMASR (STM32_ETHERNET_BASE+STM32_ETH_DMASR_OFFSET) -#define STM32_ETH_DMAOMR (STM32_ETHERNET_BASE+STM32_ETH_DMAOMR_OFFSET) -#define STM32_ETH_DMAIER (STM32_ETHERNET_BASE+STM32_ETH_DMAIER_OFFSET) -#define STM32_ETH_DMAMFBOC (STM32_ETHERNET_BASE+STM32_ETH_DMAMFBOC_OFFSET) -#define STM32_ETH_DMARSWTR (STM32_ETHERNET_BASE+STM32_ETH_DMARSWTR_OFFSET) -#define STM32_ETH_DMACHTDR (STM32_ETHERNET_BASE+STM32_ETH_DMACHTDR_OFFSET) -#define STM32_ETH_DMACHRDR (STM32_ETHERNET_BASE+STM32_ETH_DMACHRDR_OFFSET) -#define STM32_ETH_DMACHTBAR (STM32_ETHERNET_BASE+STM32_ETH_DMACHTBAR_OFFSET) -#define STM32_ETH_DMACHRBAR (STM32_ETHERNET_BASE+STM32_ETH_DMACHRBAR_OFFSET) - -/* Register Bit-Field Definitions *******************************************/ - -/* MAC Registers */ - -/* Ethernet MAC configuration register */ - -#define ETH_MACCR_RE (1 << 2) /* Bit 2: Receiver enable */ -#define ETH_MACCR_TE (1 << 3) /* Bit 3: Transmitter enable */ -#define ETH_MACCR_DC (1 << 4) /* Bit 4: Deferral check */ -#define ETH_MACCR_BL_SHIFT (5) /* Bits 5-6: Back-off limit */ -#define ETH_MACCR_BL_MASK (3 << ETH_MACCR_BL_SHIFT) -# define ETH_MACCR_BL_10 (0 << ETH_MACCR_BL_SHIFT) /* 00: k = min (n, 10) */ -# define ETH_MACCR_BL_8 (1 << ETH_MACCR_BL_SHIFT) /* 01: k = min (n, 8) */ -# define ETH_MACCR_BL_4 (2 << ETH_MACCR_BL_SHIFT) /* 10: k = min (n, 4) */ -# define ETH_MACCR_BL_1 (3 << ETH_MACCR_BL_SHIFT) /* 11: k = min (n, 1) */ - -#define ETH_MACCR_APCS (1 << 7) /* Bit 7: Automatic pad/CRC stripping */ -#define ETH_MACCR_RD (1 << 9) /* Bit 9: Retry disable */ -#define ETH_MACCR_IPCO (1 << 10) /* Bit 10: IPv4 checksum offload */ -#define ETH_MACCR_DM (1 << 11) /* Bit 11: Duplex mode */ -#define ETH_MACCR_LM (1 << 12) /* Bit 12: Loopback mode */ -#define ETH_MACCR_ROD (1 << 13) /* Bit 13: Receive own disable */ -#define ETH_MACCR_FES (1 << 14) /* Bit 14: Fast Ethernet speed */ -#define ETH_MACCR_CSD (1 << 16) /* Bit 16: Carrier sense disable */ -#define ETH_MACCR_IFG_SHIFT (17) /* Bits 17-19: Interframe gap */ -#define ETH_MACCR_IFG_MASK (7 << ETH_MACCR_IFG_SHIFT) -# define ETH_MACCR_IFG(n) ((12-((n) >> 3)) << ETH_MACCR_IFG_SHIFT) /* n bit times, n=40,48,..96 */ - -#define ETH_MACCR_JD (1 << 22) /* Bit 22: Jabber disable */ -#define ETH_MACCR_WD (1 << 23) /* Bit 23: Watchdog disable */ -#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) -# define ETH_MACCR_CSTF (1 << 25) /* Bits 25: CRC stripping for Type frames */ -#endif - -/* Ethernet MAC frame filter register */ - -#define ETH_MACFFR_PM (1 << 0) /* Bit 0: Promiscuous mode */ -#define ETH_MACFFR_HU (1 << 1) /* Bit 1: Hash unicast */ -#define ETH_MACFFR_HM (1 << 2) /* Bit 2: Hash multicast */ -#define ETH_MACFFR_DAIF (1 << 3) /* Bit 3: Destination address inverse filtering */ -#define ETH_MACFFR_PAM (1 << 4) /* Bit 4: Pass all multicast */ -#define ETH_MACFFR_BFD (1 << 5) /* Bit 5: Broadcast frames disable */ -#define ETH_MACFFR_PCF_SHIFT (6) /* Bits 6-7: Pass control frames */ -#define ETH_MACFFR_PCF_MASK (3 << ETH_MACFFR_PCF_SHIFT) -# define ETH_MACFFR_PCF_NONE (0 << ETH_MACFFR_PCF_SHIFT) /* Prevents all control frames */ -# define ETH_MACFFR_PCF_PAUSE (1 << ETH_MACFFR_PCF_SHIFT) /* Prevents all except Pause control frames */ -# define ETH_MACFFR_PCF_ALL (2 << ETH_MACFFR_PCF_SHIFT) /* Forwards all control frames */ -# define ETH_MACFFR_PCF_FILTER (3 << ETH_MACFFR_PCF_SHIFT) /* Forwards all that pass address filter */ - -#define ETH_MACFFR_SAIF (1 << 8) /* Bit 8: Source address inverse filtering */ -#define ETH_MACFFR_SAF (1 << 9) /* Bit 9: Source address filter */ -#define ETH_MACFFR_HPF (1 << 10) /* Bit 10: Hash or perfect filter */ -#define ETH_MACFFR_RA (1 << 31) /* Bit 31: Receive all */ - -/* Ethernet MAC hash table high/low registers (32-bit values) */ - -/* Ethernet MAC MII address register */ - -#define ETH_MACMIIAR_MB (1 << 0) /* Bit 0: MII busy */ -#define ETH_MACMIIAR_MW (1 << 1) /* Bit 1: MII write */ -#define ETH_MACMIIAR_CR_SHIFT (2) /* Bits 2-4: Clock range */ -#define ETH_MACMIIAR_CR_MASK (7 << ETH_MACMIIAR_CR_SHIFT) -#if 0 /* Per the reference manual */ -# define ETH_MACMIIAR_CR_60_100 (0 << ETH_MACMIIAR_CR_SHIFT) /* 000 60-100 MHzHCLK/42 */ -# define ETH_MACMIIAR_CR_100_168 (1 << ETH_MACMIIAR_CR_SHIFT) /* 001 100-168 MHz HCLK/62 */ -# define ETH_MACMIIAR_CR_20_35 (2 << ETH_MACMIIAR_CR_SHIFT) /* 010 20-35 MHz HCLK/16 */ -# define ETH_MACMIIAR_CR_35_60 (3 << ETH_MACMIIAR_CR_SHIFT) /* 011 35-60 MHz HCLK/26 */ -#else /* Per the driver example */ -# define ETH_MACMIIAR_CR_60_100 (0 << ETH_MACMIIAR_CR_SHIFT) /* 000 60-100 MHz HCLK/42 */ -# define ETH_MACMIIAR_CR_100_150 (1 << ETH_MACMIIAR_CR_SHIFT) /* 001 100-150 MHz HCLK/62 */ -# define ETH_MACMIIAR_CR_20_35 (2 << ETH_MACMIIAR_CR_SHIFT) /* 010 20-35 MHz HCLK/16 */ -# define ETH_MACMIIAR_CR_35_60 (3 << ETH_MACMIIAR_CR_SHIFT) /* 011 35-60 MHz HCLK/26 */ -# define ETH_MACMIIAR_CR_150_180 (4 << ETH_MACMIIAR_CR_SHIFT) /* 100 150-180 MHz HCLK/102 */ -#endif -#define ETH_MACMIIAR_MR_SHIFT (6) /* Bits 6-10: MII register */ -#define ETH_MACMIIAR_MR_MASK (31 << ETH_MACMIIAR_MR_SHIFT) -#define ETH_MACMIIAR_PA_SHIFT (11) /* Bits 11-15: PHY address */ -#define ETH_MACMIIAR_PA_MASK (31 << ETH_MACMIIAR_PA_SHIFT) - -/* Ethernet MAC MII data register */ - -#define ETH_MACMIIDR_MASK (0xffff) - -/* Ethernet MAC flow control register */ - -#define ETH_MACFCR_FCB_BPA (1 << 0) /* Bit 0: Flow control busy/back pressure activate */ -#define ETH_MACFCR_TFCE (1 << 1) /* Bit 1: Transmit flow control enable */ -#define ETH_MACFCR_RFCE (1 << 2) /* Bit 2: Receive flow control enable */ -#define ETH_MACFCR_UPFD (1 << 3) /* Bit 3: Unicast pause frame detect */ -#define ETH_MACFCR_PLT_SHIFT (4) /* Bits 4-5: Pause low threshold */ -#define ETH_MACFCR_PLT_MASK (3 << ETH_MACFCR_PLT_SHIFT) -# define ETH_MACFCR_PLT_M4 (0 << ETH_MACFCR_PLT_SHIFT) /* 00 Pause - 4 slot times */ -# define ETH_MACFCR_PLT_M28 (1 << ETH_MACFCR_PLT_SHIFT) /* 01 Pause - 28 slot times */ -# define ETH_MACFCR_PLT_M144 (2 << ETH_MACFCR_PLT_SHIFT) /* 10 Pause - 144 slot times */ -# define ETH_MACFCR_PLT_M256 (3 << ETH_MACFCR_PLT_SHIFT) /* 11 Pause -s 256 slot times */ - -#define ETH_MACFCR_ZQPD (1 << 7) /* Bit 7: Zero-quanta pause disable */ -#define ETH_MACFCR_PT_SHIFT (16) /* Bits 16-31: Pause time */ -#define ETH_MACFCR_PT_MASK (0xffff << ETH_MACFCR_PT_SHIFT) - -/* Ethernet MAC VLAN tag register */ - -#define ETH_MACVLANTR_VLANTI_SHIFT (0) /* Bits 0-15: VLAN tag identifier (for receive frames) */ -#define ETH_MACVLANTR_VLANTI_MASK (0xffff << ETH_MACVLANTR_VLANTI_SHIFT) -#define ETH_MACVLANTR_VLANTC (1 << 16) /* Bit 16: 12-bit VLAN tag comparison */ - -/* Ethernet MAC remote wakeup frame filter reg. Provides 32-bit access to - * remote remote wake-up filters. - */ - -/* Ethernet MAC PMT control and status register */ - -#define ETH_MACPMTCSR_PD (1 << 0) /* Bit 0: Power down */ -#define ETH_MACPMTCSR_MPE (1 << 1) /* Bit 1: Magic Packet enable */ -#define ETH_MACPMTCSR_WFE (1 << 2) /* Bit 2: Wakeup frame enable */ -#define ETH_MACPMTCSR_MPR (1 << 5) /* Bit 5: Magic packet received */ -#define ETH_MACPMTCSR_WFR (1 << 6) /* Bit 6: Wakeup frame received */ -#define ETH_MACPMTCSR_GU (1 << 9) /* Bit 9: Global unicast */ - -/* Ethernet MAC debug register */ - -#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) - -#define ETH_MACDBGR_MMRPEA (1 << 0) /* Bit 0: MAC MII receive protocol engine active */ -#define ETH_MACDBGR_MSFRWCS_SHIFT (1) /* Bits 1-2: MAC small FIFO read / write controllers status */ -#define ETH_MACDBGR_MSFRWCS_MASK (3 << ETH_MACDBGR_MSFRWCS_SHIFT) - -#define ETH_MACDBGR_RFWRA (1 << 4) /* Bit 4: Rx FIFO write controller active */ -#define ETH_MACDBGR_RFRCS_SHIFT (5) /* Bits 5-6: Rx FIFO read controller status */ -#define ETH_MACDBGR_RFRCS_MASK (3 << ETH_MACDBGR_RFRCS_SHIFT) -# define ETH_MACDBGR_RFRCS_IDLE (0 << ETH_MACDBGR_RFRCS_SHIFT) /* 00: IDLE state */ -# define ETH_MACDBGR_RFRCS_RFRAME (1 << ETH_MACDBGR_RFRCS_SHIFT) /* 01: Reading frame data */ -# define ETH_MACDBGR_RFRCS_RSTATUS (2 << ETH_MACDBGR_RFRCS_SHIFT) /* 10: Reading frame status (or time-stamp) */ -# define ETH_MACDBGR_RFRCS_FLUSHING (3 << ETH_MACDBGR_RFRCS_SHIFT) /* 11: Flushing the frame data and status */ - -#define ETH_MACDBGR_RFFL_SHIFT (8) /* Bits 8-9: Rx FIFO fill level */ -#define ETH_MACDBGR_RFFL_MASK (3 << ETH_MACDBGR_RFFL_SHIFT) -# define ETH_MACDBGR_RFFL_EMPTY (0 << ETH_MACDBGR_RFFL_SHIFT) /* 00: RxFIFO empty */ -# define ETH_MACDBGR_RFFL_DEACT (1 << ETH_MACDBGR_RFFL_SHIFT) /* 01: RxFIFO fill-level below flow-control de-activate threshold */ -# define ETH_MACDBGR_RFFL_ACTIV (2 << ETH_MACDBGR_RFFL_SHIFT) /* 10: RxFIFO fill-level above flow-control activate threshold */ -# define ETH_MACDBGR_RFFL_FULL (3 << ETH_MACDBGR_RFFL_SHIFT) /* 11: RxFIFO full */ - -#define ETH_MACDBGR_MMTEA (1 << 16) /* Bit 16: MAC MII transmit engine active */ -#define ETH_MACDBGR_MTFCS_SHIFT (17) /* Bits 17-18: MAC transmit frame controller status */ -#define ETH_MACDBGR_MTFCS_MASK (3 << ETH_MACDBGR_MTFCS_SHIFT) -# define ETH_MACDBGR_MTFCS_IDLE (0 << ETH_MACDBGR_MTFCS_SHIFT) /* 00: Idle */ -# define ETH_MACDBGR_MTFCS_WAITING (1 << ETH_MACDBGR_MTFCS_SHIFT) /* 01: Waiting for Status of previous frame or IFG/backoff period to be over */ -# define ETH_MACDBGR_MTFCS_PAUSE (2 << ETH_MACDBGR_MTFCS_SHIFT) /* 10: Generating and transmitting a Pause control frame */ -# define ETH_MACDBGR_MTFCS_FRAME (3 << ETH_MACDBGR_MTFCS_SHIFT) /* 11: Transferring input frame for transmission */ - -#define ETH_MACDBGR_MTP (1 << 19) /* Bit 19: MAC transmitter in pause */ -#define ETH_MACDBGR_TFRS_SHIFT (20) /* Bits 20-21: Tx FIFO read status */ -#define ETH_MACDBGR_TFRS_MASK (3 << ETH_MACDBGR_TFRS_SHIFT) -# define ETH_MACDBGR_TFRS_IDLE (0 << ETH_MACDBGR_TFRS_SHIFT) /* 00: Idle state */ -# define ETH_MACDBGR_TFRS_READ (1 << ETH_MACDBGR_TFRS_SHIFT) /* 01: Read state */ -# define ETH_MACDBGR_TFRS_WAITING (2 << ETH_MACDBGR_TFRS_SHIFT) /* 10: Waiting for TxStatus from MAC transmitter */ -# define ETH_MACDBGR_TFRS_WRITING (3 << ETH_MACDBGR_TFRS_SHIFT) /* 11: Writing the received TxStatus or flushing the TxFIFO */ - -#define ETH_MACDBGR_TFWA (1 << 22) /* Bit 22: Tx FIFO write active */ -#define ETH_MACDBGR_TFNE (1 << 24) /* Bit 24: Tx FIFO not empty */ -#define ETH_MACDBGR_TFF (1 << 25) /* Bit 25: Tx FIFO full */ - -#endif - -/* Ethernet MAC interrupt status register */ - -#define ETH_MACSR_PMTS (1 << 3) /* Bit 3: PMT status */ -#define ETH_MACSR_MMCS (1 << 4) /* Bit 4: MMC status */ -#define ETH_MACSR_MMCRS (1 << 5) /* Bit 5: MMC receive status */ -#define ETH_MACSR_MMCTS (1 << 6) /* Bit 6: MMC transmit status */ -#define ETH_MACSR_TSTS (1 << 9) /* Bit 9: Time stamp trigger status */ - -/* Ethernet MAC interrupt mask register */ - -#define ETH_MACIMR_PMTIM (1 << 3) /* Bit 3: PMT interrupt mask */ -#define ETH_MACIMR_TSTIM (1 << 9) /* Bit 9: Time stamp trigger interrupt mask */ -#define ETH_MACIMR_ALLINTS (ETH_MACIMR_PMTIM|ETH_MACIMR_TSTIM) - -/* Ethernet MAC address 0 high register */ - -#define ETH_MACA0HR_MACA0H_SHIFT (0) /* Bits 0-15: MAC address0 high [47:32] */ -#define ETH_MACA0HR_MACA0H_MASK (0xffff << ETH_MACA0HR_MACA0H_SHIFT) -#define ETH_MACA0HR_MO (1 << 31) /* Bit 31:Always */ - -/* Ethernet MAC address 0 low register (MAC address0 low [31:0]) */ - -/* Ethernet MAC address 1 high register */ - -#define ETH_MACA1HR_MACA1H_SHIFT (0) /* Bits 0-15: MAC address1 high [47:32] */ -#define ETH_MACA1HR_MACA1H_MASK (0xffff << ETH_MACA1HR_MACA1H_SHIFT) -#define ETH_MACA1HR_MBC_SHIFT (24) /* Bits 24-29: Mask byte control */ -#define ETH_MACA1HR_MBC_MASK (0x3f << ETH_MACA1HR_MBC_SHIFT) -# define ETH_MACA1HR_MBC_40_47 (0x20 << ETH_MACA1HR_MBC_SHIFT) /* Bit 29: ETH_MACA1HR [8-15] */ -# define ETH_MACA1HR_MBC_32_39 (0x10 << ETH_MACA1HR_MBC_SHIFT) /* Bit 28: ETH_MACA1HR [0-7] */ -# define ETH_MACA1HR_MBC_24_31 (0x08 << ETH_MACA1HR_MBC_SHIFT) /* Bit 27: ETH_MACA1LR [24-31] */ -# define ETH_MACA1HR_MBC_16_23 (0x04 << ETH_MACA1HR_MBC_SHIFT) /* Bit 26: ETH_MACA1LR [16-23] */ -# define ETH_MACA1HR_MBC_8_15 (0x02 << ETH_MACA1HR_MBC_SHIFT) /* Bit 25: ETH_MACA1LR [8-15] */ -# define ETH_MACA1HR_MBC_0_7 (0x01 << ETH_MACA1HR_MBC_SHIFT) /* Bit 24: ETH_MACA1LR [0-7] */ - -#define ETH_MACA1HR_SA (1 << 30) /* Bit 30: Source address */ -#define ETH_MACA1HR_AE (1 << 31) /* Bit 31: Address enable */ - -/* Ethernet MAC address1 low register (MAC address1 low [31:0]) */ - -/* Ethernet MAC address 2 high register */ - -#define ETH_MACA2HR_MACA2H_SHIFT (0) /* Bits 0-15: MAC address2 high [47:32] */ -#define ETH_MACA2HR_MACA2H_MASK (0xffff << ETH_MACA2HR_MACA2H_SHIFT) -#define ETH_MACA2HR_MBC_SHIFT (24) /* Bits 24-29: Mask byte control */ -#define ETH_MACA2HR_MBC_MASK (0x3f << ETH_MACA2HR_MBC_SHIFT) -# define ETH_MACA2HR_MBC_40_47 (0x20 << ETH_MACA2HR_MBC_SHIFT) /* Bit 29: ETH_MACA2HR [8-15] */ -# define ETH_MACA2HR_MBC_32_39 (0x10 << ETH_MACA2HR_MBC_SHIFT) /* Bit 28: ETH_MACA2HR [0-7] */ -# define ETH_MACA2HR_MBC_24_31 (0x08 << ETH_MACA2HR_MBC_SHIFT) /* Bit 27: ETH_MACA2LR [24-31] */ -# define ETH_MACA2HR_MBC_16_23 (0x04 << ETH_MACA2HR_MBC_SHIFT) /* Bit 26: ETH_MACA2LR [16-23] */ -# define ETH_MACA2HR_MBC_8_15 (0x02 << ETH_MACA2HR_MBC_SHIFT) /* Bit 25: ETH_MACA2LR [8-15] */ -# define ETH_MACA2HR_MBC_0_7 (0x01 << ETH_MACA2HR_MBC_SHIFT) /* Bit 24: ETH_MACA2LR [0-7] */ - -#define ETH_MACA2HR_SA (1 << 30) /* Bit 30: Source address */ -#define ETH_MACA2HR_AE (1 << 31) /* Bit 31: Address enable */ - -/* Ethernet MAC address 2 low register (MAC address2 low [31:0]) */ - -/* Ethernet MAC address 3 high register */ - -#define ETH_MACA3HR_MACA3H_SHIFT (0) /* Bits 0-15: MAC address3 high [47:32] */ -#define ETH_MACA3HR_MACA3H_MASK (0xffff << ETH_MACA3HR_MACA3H_SHIFT) -#define ETH_MACA3HR_MBC_SHIFT (24) /* Bits 24-29: Mask byte control */ -#define ETH_MACA3HR_MBC_MASK (0x3f << ETH_MACA3HR_MBC_SHIFT) -# define ETH_MACA3HR_MBC_40_47 (0x20 << ETH_MACA3HR_MBC_SHIFT) /* Bit 29: ETH_MACA3HR [8-15] */ -# define ETH_MACA3HR_MBC_32_39 (0x10 << ETH_MACA3HR_MBC_SHIFT) /* Bit 28: ETH_MACA3HR [0-7] */ -# define ETH_MACA3HR_MBC_24_31 (0x08 << ETH_MACA3HR_MBC_SHIFT) /* Bit 27: ETH_MACA3LR [24-31] */ -# define ETH_MACA3HR_MBC_16_23 (0x04 << ETH_MACA3HR_MBC_SHIFT) /* Bit 26: ETH_MACA3LR [16-23] */ -# define ETH_MACA3HR_MBC_8_15 (0x02 << ETH_MACA3HR_MBC_SHIFT) /* Bit 25: ETH_MACA3LR [8-15] */ -# define ETH_MACA3HR_MBC_0_7 (0x01 << ETH_MACA3HR_MBC_SHIFT) /* Bit 24: ETH_MACA3LR [0-7] */ - -#define ETH_MACA3HR_SA (1 << 30) /* Bit 30: Source address */ -#define ETH_MACA3HR_AE (1 << 31) /* Bit 31: Address enable */ - -/* Ethernet MAC address 3 low register (MAC address3 low [31:0]) */ - -/* MMC Registers */ - -/* Ethernet MMC control register */ - -#define ETH_MMCCR_CR (1 << 0) /* Bit 0: Counter reset */ -#define ETH_MMCCR_CSR (1 << 1) /* Bit 1: Counter stop rollover */ -#define ETH_MMCCR_ROR (1 << 2) /* Bit 2: Reset on read */ -#define ETH_MMCCR_MCF (1 << 3) /* Bit 3: MMC counter freeze */ -#define ETH_MMCCR_MCP (1 << 4) /* Bit 4: MMC counter preset */ -#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) -# define ETH_MMCCR_MCFHP (1 << 5) /* Bit 5: MMC counter Full-Half preset */ -#endif - -/* Ethernet MMC receive interrupt and interrupt mask registers */ - -#define ETH_MMCRI_RFCE (1 << 5) /* Bit 5: Received frame CRC error */ -#define ETH_MMCRI_RFAE (1 << 6) /* Bit 6: Received frames alignment error */ -#define ETH_MMCRI_RGUF (1 << 17) /* Bit 17: Received good unicast frames */ - -/* Ethernet MMC transmit interrupt and interrupt mask register */ - -#define ETH_MMCTI_TGFSC (1 << 14) /* Bit 14: Transmitted good frames single collision */ -#define ETH_MMCTI_TGFMSC (1 << 15) /* Bit 15: Transmitted good frames more single collision */ -#define ETH_MMCTI_TGF (1 << 21) /* Bit 21: Transmitted good frames */ - -/* 32-bit counters: - * - * Ethernet MMC transmitted good frames counter register (single collision) - * Ethernet MMC transmitted good frames counter register (multiple-collision) - * Ethernet MMC transmitted good frames counter register - * Ethernet MMC received frames with CRC error counter register - * Ethernet MMC received frames with alignment error counter - * MMC received good unicast frames counter register - */ - -/* IEEE 1588 time stamp registers */ - -/* Ethernet PTP time stamp control register */ - -#define ETH_PTPTSCR_TSE (1 << 0) /* Bit 0: Time stamp enable */ -#define ETH_PTPTSCR_TSFCU (1 << 1) /* Bit 1: Time stamp fine or coarse update */ -#define ETH_PTPTSCR_TSSTI (1 << 2) /* Bit 2: Time stamp system time initialize */ -#define ETH_PTPTSCR_TSSTU (1 << 3) /* Bit 3: Time stamp system time update */ -#define ETH_PTPTSCR_TSITE (1 << 4) /* Bit 4: Time stamp interrupt trigger enable */ -#define ETH_PTPTSCR_TSARU (1 << 5) /* Bit 5: Time stamp addend register update */ - -#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) -#define ETH_PTPTSCR_TSSARFE (1 << 8) /* Bit 8: Time stamp snapshot for all received frames enable */ -#define ETH_PTPTSCR_TSSSR (1 << 9) /* Bit 9: Time stamp subsecond rollover: digital or binary rollover control */ -#define ETH_PTPTSCR_TSPTPPSV2E (1 << 10) /* Bit 10: Time stamp PTP packet snooping for version2 format enable */ -#define ETH_PTPTSCR_TSSPTPOEFE (1 << 11) /* Bit 11: Time stamp snapshot for PTP over ethernet frames enable */ -#define ETH_PTPTSCR_TSSIPV6FE (1 << 12) /* Bit 12: Time stamp snapshot for IPv6 frames enable */ -#define ETH_PTPTSCR_TSSIPV4FE (1 << 13) /* Bit 13: Time stamp snapshot for IPv4 frames enable */ -#define ETH_PTPTSCR_TSSEME (1 << 14) /* Bit 14: Time stamp snapshot for event message enable */ -#define ETH_PTPTSCR_TSSMRME (1 << 15) /* Bit 15: Time stamp snapshot for message relevant to master enable */ -#define ETH_PTPTSCR_TSCNT_SHIFT (16) /* Bits 16-17: Time stamp clock node type */ -#define ETH_PTPTSCR_TSCNT_MASK (3 << ETH_PTPTSCR_TSCNT_SHIFT) -# define ETH_PTPTSCR_TSCNT_ORDINARY (0 << ETH_PTPTSCR_TSCNT_SHIFT) /* 00: Ordinary clock */ -# define ETH_PTPTSCR_TSCNT_BOUNDARY (1 << ETH_PTPTSCR_TSCNT_SHIFT) /* 01: Boundary clock */ -# define ETH_PTPTSCR_TSCNT_E2E (2 << ETH_PTPTSCR_TSCNT_SHIFT) /* 10: End-to-end transparent clock */ -# define ETH_PTPTSCR_TSCNT_P2P (3 << ETH_PTPTSCR_TSCNT_SHIFT) /* 11: Peer-to-peer transparent clock */ - -#define ETH_PTPTSCR_TSPFFMAE (1 << 18) /* Bit 18: Time stamp PTP frame filtering MAC address enable */ -#endif - -/* Ethernet PTP subsecond increment register */ - -#define ETH_PTPSSIR_MASK (0xff) - -/* Ethernet PTP time stamp high register (32-bit) */ - -/* Ethernet PTP time stamp low register */ - -#define ETH_PTPTSLR_STPNS (1 << 31) /* Bit 31: System time positive or negative sign */ -#define ETH_PTPTSLR_MASK (0x7fffffff) /* Bits 0-30: System time subseconds */ - -/* Ethernet PTP time stamp high update register (32-bit) */ - -/* Ethernet PTP time stamp low update register */ - -#define ETH_PTPTSLU_TSUPNS (1 << 31) /* Bit 31: System time positive or negative sign */ -#define ETH_PTPTSLU_MASK (0x7fffffff) /* Bits 0-30: Time stamp update subsecond */ - -/* Ethernet PTP time stamp addend register (32-bit) */ - -/* Ethernet PTP target time high register (32-bit) */ - -/* Ethernet PTP target time low register (32-bit) */ - -/* Ethernet PTP time stamp status register */ - -#define ETH_PTPTSSR_TSSO (1 << 0) /* Bit 0: Time stamp second overflow */ -#define ETH_PTPTSSR_TSTTR (1 << 1) /* Bit 1: Time stamp target time reached */ - -/* Ethernet PTP PPS control register */ - -#define ETH_PTPPPSCR_PPSFREQ_SHIFT (0) /* Bits 0-3: PPS frequency selection */ -#define ETH_PTPPPSCR_PPSFREQ_MASK (15 << ETH_PTPPPSCR_PPSFREQ_SHIFT) -# define ETH_PTPPPSCR_PPSFREQ_1HZ (0 << ETH_PTPPPSCR_PPSFREQ_SHIFT) /* 1 Hz with pulse width of 125/100 ms for binary/digital rollover */ -# define ETH_PTPPPSCR_PPSFREQ_2HZ (1 << ETH_PTPPPSCR_PPSFREQ_SHIFT) /* 2 Hz with 50% duty cycle */ -# define ETH_PTPPPSCR_PPSFREQ_4HZ (2 << ETH_PTPPPSCR_PPSFREQ_SHIFT) /* 4 Hz with 50% duty cycle */ -# define ETH_PTPPPSCR_PPSFREQ_8HZ (3 << ETH_PTPPPSCR_PPSFREQ_SHIFT) /* 8 Hz with 50% duty cycle */ -# define ETH_PTPPPSCR_PPSFREQ_16HZ (4 << ETH_PTPPPSCR_PPSFREQ_SHIFT) /* 16 Hz with 50% duty cycle */ -# define ETH_PTPPPSCR_PPSFREQ_32HZ (5 << ETH_PTPPPSCR_PPSFREQ_SHIFT) /* 32 Hz with 50% duty cycle */ -# define ETH_PTPPPSCR_PPSFREQ_64HZ (6 << ETH_PTPPPSCR_PPSFREQ_SHIFT) /* 64 Hz with 50% duty cycle */ -# define ETH_PTPPPSCR_PPSFREQ_128HZ (7 << ETH_PTPPPSCR_PPSFREQ_SHIFT) /* 128 Hz with 50% duty cycle */ -# define ETH_PTPPPSCR_PPSFREQ_256HZ (8 << ETH_PTPPPSCR_PPSFREQ_SHIFT) /* 256 Hz with 50% duty cycle */ -# define ETH_PTPPPSCR_PPSFREQ_512HZ (9 << ETH_PTPPPSCR_PPSFREQ_SHIFT) /* 512 Hz with 50% duty cycle */ -# define ETH_PTPPPSCR_PPSFREQ_1KHZ (10 << ETH_PTPPPSCR_PPSFREQ_SHIFT) /* 1024 Hz with 50% duty cycle */ -# define ETH_PTPPPSCR_PPSFREQ_2KHZ (11 << ETH_PTPPPSCR_PPSFREQ_SHIFT) /* 2048 Hz with 50% duty cycle */ -# define ETH_PTPPPSCR_PPSFREQ_4KHZ (12 << ETH_PTPPPSCR_PPSFREQ_SHIFT) /* 4096 Hz with 50% duty cycle */ -# define ETH_PTPPPSCR_PPSFREQ_8KHZ (13 << ETH_PTPPPSCR_PPSFREQ_SHIFT) /* 8192 Hz with 50% duty cycle */ -# define ETH_PTPPPSCR_PPSFREQ_16KHZ (14 << ETH_PTPPPSCR_PPSFREQ_SHIFT) /* 16384 Hz with 50% duty cycle */ -# define ETH_PTPPPSCR_PPSFREQ_32KHZ (15 << ETH_PTPPPSCR_PPSFREQ_SHIFT) /* 32768 Hz with 50% duty cycle */ - -/* DMA Registers */ - -/* Ethernet DMA bus mode register */ - -#define ETH_DMABMR_SR (1 << 0) /* Bit 0: Software reset */ -#define ETH_DMABMR_DA (1 << 1) /* Bit 1: DMA Arbitration */ -#define ETH_DMABMR_DSL_SHIFT (2) /* Bits 2-6: Descriptor skip length */ -#define ETH_DMABMR_DSL_MASK (31 << ETH_DMABMR_DSL_SHIFT) -# define ETH_DMABMR_DSL(n) ((n) << ETH_DMABMR_DSL_SHIFT) -#define ETH_DMABMR_EDFE (1 << 7) /* Bit 7: Enhanced descriptor format enable */ -#define ETH_DMABMR_PBL_SHIFT (8) /* Bits 8-13: Programmable burst length */ - -# define ETH_DMABMR_PBL(n) ((n) << ETH_DMABMR_PBL_SHIFT) /* n=1, 2, 4, 8, 16, 32 */ -#define ETH_DMABMR_PBL_MASK (0x3f << ETH_DMABMR_PBL_SHIFT) - -#define ETH_DMABMR_RTPR_SHIFT (14) /* Bits 14-15: Rx Tx priority ratio */ -#define ETH_DMABMR_RTPR_MASK (3 << ETH_DMABMR_RTPR_SHIFT) -# define ETH_DMABMR_RTPR_1TO1 (0 << ETH_DMABMR_RTPR_SHIFT) /* 00: 1:1 */ -# define ETH_DMABMR_RTPR_2TO1 (1 << ETH_DMABMR_RTPR_SHIFT) /* 01: 2:1 */ -# define ETH_DMABMR_RTPR_3TO1 (2 << ETH_DMABMR_RTPR_SHIFT) /* 10: 3:1 */ -# define ETH_DMABMR_RTPR_4TO1 (3 << ETH_DMABMR_RTPR_SHIFT) /* 11: 4:1 */ - -#define ETH_DMABMR_FB (1 << 16) /* Bit 16: Fixed burst */ -#define ETH_DMABMR_RDP_SHIFT (17) /* Bits 17-22: Rx DMA PBL */ -#define ETH_DMABMR_RDP_MASK (0x3f << ETH_DMABMR_RDP_SHIFT) -# define ETH_DMABMR_RDP(n) ((n) << ETH_DMABMR_RDP_SHIFT) /* n=1, 2, 4, 8, 16, 32 */ - -#define ETH_DMABMR_USP (1 << 23) /* Bit 23: Use separate PBL */ -#define ETH_DMABMR_FPM (1 << 24) /* Bit 24: 4xPBL mode */ -#define ETH_DMABMR_AAB (1 << 25) /* Bit 25: Address-aligned beats */ -#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) -# define ETH_DMABMR_MB (1 << 26) /* Bit 26: Mixed burst */ -#endif - -/* Ethernet DMA transmit poll demand register (32-bit) */ - -/* Ethernet DMA receive poll demand register (32-bit) */ - -/* Ethernet DMA receive descriptor list address register (32-bit address) */ - -/* Ethernet DMA transmit descriptor list address register (32-bit address) */ - -/* Interrupt bit definitions common between the DMA status register (DMASR) - * and the DMA interrupt enable register (DMAIER). - */ - -#define ETH_DMAINT_TI (1 << 0) /* Bit 0: Transmit interrupt */ -#define ETH_DMAINT_TPSI (1 << 1) /* Bit 1: Transmit process stopped interrupt */ -#define ETH_DMAINT_TBUI (1 << 2) /* Bit 2: Transmit buffer unavailable interrupt */ -#define ETH_DMAINT_TJTI (1 << 3) /* Bit 3: Transmit jabber timeout interrupt */ -#define ETH_DMAINT_ROI (1 << 4) /* Bit 4: Overflow interrupt */ -#define ETH_DMAINT_TUI (1 << 5) /* Bit 5: Underflow interrupt */ -#define ETH_DMAINT_RI (1 << 6) /* Bit 6: Receive interrupt */ -#define ETH_DMAINT_RBUI (1 << 7) /* Bit 7: Receive buffer unavailable interrupt */ -#define ETH_DMAINT_RPSI (1 << 8) /* Bit 8: Receive process stopped interrupt */ -#define ETH_DMAINT_RWTI (1 << 9) /* Bit 9: Receive watchdog timeout interrupt */ -#define ETH_DMAINT_ETI (1 << 10) /* Bit 10: Early transmit interrupt */ -#define ETH_DMAINT_FBEI (1 << 13) /* Bit 13: Fatal bus error interrupt */ -#define ETH_DMAINT_ERI (1 << 14) /* Bit 14: Early receive interrupt */ -#define ETH_DMAINT_AIS (1 << 15) /* Bit 15: Abnormal interrupt summary */ -#define ETH_DMAINT_NIS (1 << 16) /* Bit 16: Normal interrupt summary */ - -/* Ethernet DMA status register (in addition to the interrupt bits above */ - -#define ETH_DMASR_RPS_SHIFT (17) /* Bits 17-19: Receive process state */ -#define ETH_DMASR_RPS_MASK (7 << ETH_DMASR_RPS_SHIFT) -# define ETH_DMASR_RPS_STOPPED (0 << ETH_DMASR_RPS_SHIFT) /* 000: Stopped: Reset or Stop Receive Command issued */ -# define ETH_DMASR_RPS_RXDESC (1 << ETH_DMASR_RPS_SHIFT) /* 001: Running: Fetching receive transfer descriptor */ -# define ETH_DMASR_RPS_WAITING (3 << ETH_DMASR_RPS_SHIFT) /* 011: Running: Waiting for receive packet */ -# define ETH_DMASR_RPS_SUSPENDED (4 << ETH_DMASR_RPS_SHIFT) /* 100: Suspended: Receive descriptor unavailable */ -# define ETH_DMASR_RPS_CLOSING (5 << ETH_DMASR_RPS_SHIFT) /* 101: Running: Closing receive descriptor */ -# define ETH_DMASR_RPS_TRANSFER (6 << ETH_DMASR_RPS_SHIFT) /* 111: Running: Transferring the receive data to memory */ - -#define ETH_DMASR_TPS_SHIFT (20) /* Bits 20-22: Transmit process state */ -#define ETH_DMASR_TPS_MASK (7 << ETH_DMASR_TPS_SHIFT) -# define ETH_DMASR_TPS_STOPPED (0 << ETH_DMASR_TPS_SHIFT) /* 000: Stopped; Reset or Stop Transmit Command issued */ -# define ETH_DMASR_TPS_TXDESC (1 << ETH_DMASR_TPS_SHIFT) /* 001: Running; Fetching transmit transfer descriptor */ -# define ETH_DMASR_TPS_WAITING (2 << ETH_DMASR_TPS_SHIFT) /* 010: Running; Waiting for status */ -# define ETH_DMASR_TPS_TRANSFER (3 << ETH_DMASR_TPS_SHIFT) /* 011: Running; Reading data and queuing to transmit (TxFIFO) */ -# define ETH_DMASR_TPS_SUSPENDED (6 << ETH_DMASR_TPS_SHIFT) /* 110: Suspended; Transmit descriptor unavailable or buffer underflow */ -# define ETH_DMASR_TPS_CLOSING (7 << ETH_DMASR_TPS_SHIFT) /* 111: Running; Closing transmit descriptor */ - -#define ETH_DMASR_EBS_SHIFT (23) /* Bits 23-25: Error bits status */ -#define ETH_DMASR_EBS_MASK (7 << ETH_DMASR_EBS_SHIFT) -#define ETH_DMASR_EBS_TXDMS (1 << ETH_DMASR_EBS_SHIFT) /* Bit 23 1 Error during data transfer by TxDMA */ -#define ETH_DMASR_EBS_READ (2 << ETH_DMASR_EBS_SHIFT) /* Bit 24 1 Error during read transfer */ -#define ETH_DMASR_EBS_DESC (4 << ETH_DMASR_EBS_SHIFT) /* Bit 25 1 Error during descriptor access */ - -#define ETH_DMASR_MMCS (1 << 27) /* Bit 27: MMC status */ -#define ETH_DMASR_PMTS (1 << 28) /* Bit 28: PMT status */ -#define ETH_DMASR_TSTS (1 << 29) /* Bit 29: Time stamp trigger status */ - -/* Ethernet DMA operation mode register */ - -#define ETH_DMAOMR_SR (1 << 1) /* Bit 1: Start/stop receive */ -#define ETH_DMAOMR_OSF (1 << 2) /* Bit 2: Operate on second frame */ -#define ETH_DMAOMR_RTC_SHIFT (3) /* Bits 3-4: Receive threshold control */ -#define ETH_DMAOMR_RTC_MASK (3 << ETH_DMAOMR_RTC_SHIFT) -# define ETH_DMAOMR_RTC_64 (0 << ETH_DMAOMR_RTC_SHIFT) -# define ETH_DMAOMR_RTC_32 (1 << ETH_DMAOMR_RTC_SHIFT) -# define ETH_DMAOMR_RTC_96 (2 << ETH_DMAOMR_RTC_SHIFT) -# define ETH_DMAOMR_RTC_128 (3 << ETH_DMAOMR_RTC_SHIFT) -#define ETH_DMAOMR_FUGF (1 << 6) /* Bit 6: Forward undersized good frames */ -#define ETH_DMAOMR_FEF (1 << 7) /* Bit 7: Forward error frames */ -#define ETH_DMAOMR_ST (1 << 13) /* Bit 13: Start/stop transmission */ -#define ETH_DMAOMR_TTC_SHIFT (14) /* Bits 14-16: Transmit threshold control */ -#define ETH_DMAOMR_TTC_MASK (7 << ETH_DMAOMR_TTC_SHIFT) -# define ETH_DMAOMR_TTC_64 (0 << ETH_DMAOMR_TTC_SHIFT) -# define ETH_DMAOMR_TTC_128 (1 << ETH_DMAOMR_TTC_SHIFT) -# define ETH_DMAOMR_TTC_192 (2 << ETH_DMAOMR_TTC_SHIFT) -# define ETH_DMAOMR_TTC_256 (3 << ETH_DMAOMR_TTC_SHIFT) -# define ETH_DMAOMR_TTC_40 (4 << ETH_DMAOMR_TTC_SHIFT) -# define ETH_DMAOMR_TTC_32 (5 << ETH_DMAOMR_TTC_SHIFT) -# define ETH_DMAOMR_TTC_24 (6 << ETH_DMAOMR_TTC_SHIFT) -# define ETH_DMAOMR_TTC_16 (7 << ETH_DMAOMR_TTC_SHIFT) -#define ETH_DMAOMR_FTF (1 << 20) /* Bit 20: Flush transmit FIFO */ -#define ETH_DMAOMR_TSF (1 << 21) /* Bit 21: Transmit store and forward */ -#define ETH_DMAOMR_DFRF (1 << 24) /* Bit 24: Disable flushing of received frames */ -#define ETH_DMAOMR_RSF (1 << 25) /* Bit 25: Receive store and forward */ -#define ETH_DMAOMR_DTCEFD (1 << 26) /* Bit 26: Dropping of TCP/IP checksum error frames disable */ - -/* Ethernet DMA missed frame and buffer overflow counter register */ - -#define ETH_DMAMFBOC_MFC_SHIFT (0) /* Bits 0-15: Missed frames by the controller */ -#define ETH_DMAMFBOC_MFC_MASK (0xffff << ETH_DMAMFBOC_MFC_SHIFT) -#define ETH_DMAMFBOC_OMFC (1 << 16) /* Bit 16: Overflow bit for missed frame counter */ -#define ETH_DMAMFBOC_MFA_SHIFT (17) /* Bits 17-27: Missed frames by the application */ -#define ETH_DMAMFBOC_MFA_MASK (0x7ff << ETH_DMAMFBOC_MFA_SHIFT) -#define ETH_DMAMFBOC_OFOC (1 << 28) /* Bit 28: Overflow bit for FIFO overflow counter */ - -/* Ethernet DMA receive status watchdog timer register */ - -#define ETH_DMARSWTR_MASK (0xff) - -/* Ethernet DMA current host transmit descriptor register - * (32-bit address) - */ - -/* Ethernet DMA current host receive descriptor register - * (32-bit address) - */ - -/* Ethernet DMA current host transmit buffer address register - * (32-bit address) - */ - -/* Ethernet DMA current host receive buffer address register - * (32-bit address) - */ - -/* DMA Descriptors **********************************************************/ - -/* TDES0: Transmit descriptor Word0 */ - -#define ETH_TDES0_DB (1 << 0) /* Bit 0: Deferred bit */ -#define ETH_TDES0_UF (1 << 1) /* Bit 1: Underflow error */ -#define ETH_TDES0_ED (1 << 2) /* Bit 2: Excessive deferral */ -#define ETH_TDES0_CC_SHIFT (3) /* Bits 3-6: Collision count */ -#define ETH_TDES0_CC_MASK (15 << ETH_TDES0_CC_SHIFT) -#define ETH_TDES0_VF (1 << 7) /* Bit 7: VLAN frame */ -#define ETH_TDES0_EC (1 << 8) /* Bit 8: Excessive collision */ -#define ETH_TDES0_LCO (1 << 9) /* Bit 9: Late collision */ -#define ETH_TDES0_NC (1 << 10) /* Bit 10: No carrier */ -#define ETH_TDES0_LCA (1 << 11) /* Bit 11: Loss of carrier */ -#define ETH_TDES0_IPE (1 << 12) /* Bit 12: IP payload error */ -#define ETH_TDES0_FF (1 << 13) /* Bit 13: Frame flushed */ -#define ETH_TDES0_JT (1 << 14) /* Bit 14: Jabber timeout */ -#define ETH_TDES0_ES (1 << 15) /* Bit 15: Error summary */ -#define ETH_TDES0_IHE (1 << 16) /* Bit 16: IP header error */ -#define ETH_TDES0_TTSS (1 << 17) /* Bit 17: Transmit time stamp status */ -#define ETH_TDES0_TCH (1 << 20) /* Bit 20: Second address chained */ -#define ETH_TDES0_TER (1 << 21) /* Bit 21: Transmit end of ring */ -#define ETH_TDES0_CIC_SHIFT (22) /* Bits 22-23: Checksum insertion control */ -#define ETH_TDES0_CIC_MASK (3 << ETH_TDES0_CIC_SHIFT) -# define ETH_TDES0_CIC_DISABLED (0 << ETH_TDES0_CIC_SHIFT) /* Checksum disabled */ -# define ETH_TDES0_CIC_IH (1 << ETH_TDES0_CIC_SHIFT) /* IP header checksum enabled */ -# define ETH_TDES0_CIC_IHPL (2 << ETH_TDES0_CIC_SHIFT) /* IP header and payload checksum enabled */ -# define ETH_TDES0_CIC_ALL (3 << ETH_TDES0_CIC_SHIFT) /* IP Header, payload, and pseudo-header checksum enabled */ - -#define ETH_TDES0_TTSE (1 << 25) /* Bit 25: Transmit time stamp enable */ -#define ETH_TDES0_DP (1 << 26) /* Bit 26: Disable pad */ -#define ETH_TDES0_DC (1 << 27) /* Bit 27: Disable CRC */ -#define ETH_TDES0_FS (1 << 28) /* Bit 28: First segment */ -#define ETH_TDES0_LS (1 << 29) /* Bit 29: Last segment */ -#define ETH_TDES0_IC (1 << 30) /* Bit 30: Interrupt on completion */ -#define ETH_TDES0_OWN (1 << 31) /* Bit 31: Own bit */ - -/* TDES1: Transmit descriptor Word1 */ - -#define ETH_TDES1_TBS1_SHIFT (0) /* Bits 0-12: Transmit buffer 1 size */ -#define ETH_TDES1_TBS1_MASK (0x1fff << ETH_TDES1_TBS1_SHIFT) -#define ETH_TDES1_TBS2_SHIFT (16) /* Bits 16-28: Transmit buffer 2 size */ -#define ETH_TDES1_TBS2_MASK (0x1fff << ETH_TDES1_TBS2_SHIFT) - -/* TDES2: Transmit descriptor Word2 (32-bit address) */ - -/* TDES3: Transmit descriptor Word3 (32-bit address) */ - -/* TDES6: Transmit descriptor Word6 (32-bit time stamp) */ - -/* TDES7: Transmit descriptor Word7 (32-bit time stamp) */ - -/* RDES0: Receive descriptor Word0 */ - -#define ETH_RDES0_PCE (1 << 0) /* Bit 0: Payload checksum error */ -#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) -# define ETH_RDES0_ESA (1 << 0) /* Bit 0: Extended status available */ -#endif -#define ETH_RDES0_CE (1 << 1) /* Bit 1: CRC error */ -#define ETH_RDES0_DBE (1 << 2) /* Bit 2: Dribble bit error */ -#define ETH_RDES0_RE (1 << 3) /* Bit 3: Receive error */ -#define ETH_RDES0_RWT (1 << 4) /* Bit 4: Receive watchdog timeout */ -#define ETH_RDES0_FT (1 << 5) /* Bit 5: Frame type */ -#define ETH_RDES0_LCO (1 << 6) /* Bit 6: Late collision */ -#define ETH_RDES0_TSV (1 << 7) /* Bit 7: Time stamp valid */ -#define ETH_RDES0_IPHCE (1 << 7) /* Bit 7: IPv header checksum error */ -#define ETH_RDES0_LS (1 << 8) /* Bit 8: Last descriptor */ -#define ETH_RDES0_FS (1 << 9) /* Bit 9: First descriptor */ -#define ETH_RDES0_VLAN (1 << 10) /* Bit 10: VLAN tag */ -#define ETH_RDES0_OE (1 << 11) /* Bit 11: Overflow error */ -#define ETH_RDES0_LE (1 << 12) /* Bit 12: Length error */ -#define ETH_RDES0_SAF (1 << 13) /* Bit 13: Source address filter fail */ -#define ETH_RDES0_DE (1 << 14) /* Bit 14: Descriptor error */ -#define ETH_RDES0_ES (1 << 15) /* Bit 15: Error summary */ -#define ETH_RDES0_FL_SHIFT (16) /* Bits 16-29: Frame length */ -#define ETH_RDES0_FL_MASK (0x3fff << ETH_RDES0_FL_SHIFT) -#define ETH_RDES0_AFM (1 << 30) /* Bit 30: Destination address filter fail */ -#define ETH_RDES0_OWN (1 << 31) /* Bit 31: Own bit */ - -/* RDES1: Receive descriptor Word1 */ - -#define ETH_RDES1_RBS1_SHIFT (0) /* Bits 0-12: Receive buffer 1 size */ -#define ETH_RDES1_RBS1_MASK (0x1fff << ETH_RDES1_RBS1_SHIFT) - /* Bit 13: Reserved */ -#define ETH_RDES1_RCH (1 << 14) /* Bit 14: Second address chained */ -#define ETH_RDES1_RER (1 << 15) /* Bit 15: Receive end of ring */ -#define ETH_RDES1_RBS2_SHIFT (16) /* Bits 16-28: Receive buffer 2 size */ -#define ETH_RDES1_RBS2_MASK (0x1fff << ETH_RDES1_RBS2_SHIFT) -#define ETH_RDES1_DIC (1 << 31) /* Bit 31: Disable interrupt on completion */ - -/* RDES2: Receive descriptor Word2 (32-bit address) */ - -/* RDES3: Receive descriptor Word3 (32-bit address) */ - -/* RDES4: Receive descriptor Word4 */ - -#define ETH_RDES4_IPPT_SHIFT (0) /* Bits 0-2: IP payload type */ -#define ETH_RDES4_IPPT_MASK (7 << ETH_RDES4_IPPT_SHIFT) -# define ETH_RDES4_IPPT_UDP (1 << ETH_RDES4_IPPT_SHIFT) /* UDP payload in IP datagram */ -# define ETH_RDES4_IPPT_TCP (2 << ETH_RDES4_IPPT_SHIFT) /* TCP payload in IP datagram */ -# define ETH_RDES4_IPPT_ICMP (3 << ETH_RDES4_IPPT_SHIFT) /* ICMP payload in IP datagram */ - -#define ETH_RDES4_IPHE (1 << 3) /* Bit 3: IP header error */ -#define ETH_RDES4_IPPE (1 << 4) /* Bit 4: IP payload error */ -#define ETH_RDES4_IPCB (1 << 5) /* Bit 5: IP checksum bypassed */ -#define ETH_RDES4_IPV4PR (1 << 6) /* Bit 6: IPv4 packet received */ -#define ETH_RDES4_IPV6PR (1 << 7) /* Bit 7: IPv6 packet received */ -#define ETH_RDES4_PMT_SHIFT (8) /* Bits 8-11: PTP message type */ -#define ETH_RDES4_PMT_MASK (15 << ETH_RDES4_PMT_SHIFT) -# define ETH_RDES4_PMT_NONE (0 << ETH_RDES4_PMT_SHIFT) /* No PTP message received */ -# define ETH_RDES4_PMT_SYNC (1 << ETH_RDES4_PMT_SHIFT) /* SYNC (all clock types) */ -# define ETH_RDES4_PMT_FOLLOWUP (2 << ETH_RDES4_PMT_SHIFT) /* Follow_Up (all clock types) */ -# define ETH_RDES4_PMT_DELAYREQ (3 << ETH_RDES4_PMT_SHIFT) /* Delay_Req (all clock types) */ -# define ETH_RDES4_PMT_DELAYRESP (4 << ETH_RDES4_PMT_SHIFT) /* Delay_Resp (all clock types) */ -# define ETH_RDES4_PMT_PDELREQAM (5 << ETH_RDES4_PMT_SHIFT) /* Pdelay_Req (in peer-to-peer - * transparent clock) or Announce (in - * ordinary or boundary clock) */ -# define ETH_RDES4_PMT_PDELREQMM (6 << ETH_RDES4_PMT_SHIFT) /* Pdelay_Resp (in peer-to-peer - * transparent clock) or Management (in - * ordinary or boundary clock) */ -# define ETH_RDES4_PMT_PDELREQFUS (7 << ETH_RDES4_PMT_SHIFT) /* Pdelay_Resp_Follow_Up (in - * peer-to-peer transparent clock) or - * Signaling (for ordinary or boundary - * clock) */ - -#define ETH_RDES4_PFT (1 << 12) /* Bit 12: PTP frame type */ -#define ETH_RDES4_PV (1 << 13) /* Bit 13: PTP version */ - -/* RDES5: Receive descriptor Word5 - Reserved */ - -/* RDES6: Receive descriptor Word6 (32-bit time stamp) */ - -/* RDES7: Receive descriptor Word7 (32-bit time stamp) */ - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -#ifndef __ASSEMBLY__ - -/* Ethernet TX DMA Descriptor */ - -struct eth_txdesc_s -{ - /* Normal DMA descriptor words */ - - volatile uint32_t tdes0; /* Status */ - volatile uint32_t tdes1; /* Control and buffer1/2 lengths */ - volatile uint32_t tdes2; /* Buffer1 address pointer */ - volatile uint32_t tdes3; /* Buffer2 or next descriptor address pointer */ - - /* Enhanced DMA descriptor words with time stamp */ - -#ifdef CONFIG_STM32_ETH_ENHANCEDDESC - volatile uint32_t tdes4; /* Reserved */ - volatile uint32_t tdes5; /* Reserved */ - volatile uint32_t tdes6; /* Time Stamp Low value for transmit and receive */ - volatile uint32_t tdes7; /* Time Stamp High value for transmit and receive */ -#endif -}; - -/* Ethernet RX DMA Descriptor */ - -struct eth_rxdesc_s -{ - volatile uint32_t rdes0; /* Status */ - volatile uint32_t rdes1; /* Control and buffer1/2 lengths */ - volatile uint32_t rdes2; /* Buffer1 address pointer */ - volatile uint32_t rdes3; /* Buffer2 or next descriptor address pointer */ - - /* Enhanced DMA descriptor words with time stamp and PTP support */ - -#ifdef CONFIG_STM32_ETH_ENHANCEDDESC - volatile uint32_t rdes4; /* Extended status for PTP receive descriptor */ - volatile uint32_t rdes5; /* Reserved */ - volatile uint32_t rdes6; /* Time Stamp Low value for transmit and receive */ - volatile uint32_t rdes7; /* Time Stamp High value for transmit and receive */ -#endif -}; - -/**************************************************************************** - * Public Functions Prototypes - ****************************************************************************/ - -#endif /* __ASSEMBLY__ */ -#endif /* STM32_NETHERNET > 0 */ -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_ETH_H */ diff --git a/arch/arm/src/stm32/hardware/stm32_exti.h b/arch/arm/src/stm32/hardware/stm32_exti.h deleted file mode 100644 index 80d2d9c4bce55..0000000000000 --- a/arch/arm/src/stm32/hardware/stm32_exti.h +++ /dev/null @@ -1,231 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/hardware/stm32_exti.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_EXTI_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_EXTI_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include "chip.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#if defined(CONFIG_STM32_STM32F10XX) -# ifdef CONFIG_STM32_CONNECTIVITYLINE -# define STM32_NEXTI 20 -# define STM32_EXTI_MASK 0x000fffff -# else -# define STM32_NEXTI 19 -# define STM32_EXTI_MASK 0x0007ffff -# endif -#elif defined(CONFIG_STM32_STM32L15XX) -# if defined(CONFIG_STM32_LOWDENSITY) || defined(CONFIG_STM32_MEDIUMDENSITY) -# define STM32_NEXTI 23 -# define STM32_EXTI_MASK 0x007fffff -# else -# define STM32_NEXTI 24 -# define STM32_EXTI_MASK 0x00ffffff -# endif -#elif defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) -# define STM32_NEXTI1 31 -# define STM32_EXTI1_MASK 0xffffffff -# define STM32_NEXTI2 4 -# define STM32_EXTI2_MASK 0x0000000f -#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) -# define STM32_NEXTI 23 -# define STM32_EXTI_MASK 0x007fffff -#endif - -#define STM32_EXTI_BIT(n) (1 << (n)) - -/* Register Offsets *********************************************************/ - -#if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) -# define STM32_EXTI1_OFFSET 0x0000 /* Offset to EXTI1 registers */ -# define STM32_EXTI2_OFFSET 0x0020 /* Offset to EXTI2 registers */ -#endif - -#define STM32_EXTI_IMR_OFFSET 0x0000 /* Interrupt mask register */ -#define STM32_EXTI_EMR_OFFSET 0x0004 /* Event mask register */ -#define STM32_EXTI_RTSR_OFFSET 0x0008 /* Rising Trigger selection register */ -#define STM32_EXTI_FTSR_OFFSET 0x000c /* Falling Trigger selection register */ -#define STM32_EXTI_SWIER_OFFSET 0x0010 /* Software interrupt event register */ -#define STM32_EXTI_PR_OFFSET 0x0014 /* Pending register */ - -/* Register Addresses *******************************************************/ - -#if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) -# define STM32_EXTI1_BASE (STM32_EXTI_BASE+STM32_EXTI1_OFFSET) -# define STM32_EXTI2_BASE (STM32_EXTI_BASE+STM32_EXTI2_OFFSET) - -# define STM32_EXTI1_IMR (STM32_EXTI1_BASE+STM32_EXTI_IMR_OFFSET) -# define STM32_EXTI1_EMR (STM32_EXTI1_BASE+STM32_EXTI_EMR_OFFSET) -# define STM32_EXTI1_RTSR (STM32_EXTI1_BASE+STM32_EXTI_RTSR_OFFSET) -# define STM32_EXTI1_FTSR (STM32_EXTI1_BASE+STM32_EXTI_FTSR_OFFSET) -# define STM32_EXTI1_SWIER (STM32_EXTI1_BASE+STM32_EXTI_SWIER_OFFSET) -# define STM32_EXTI1_PR (STM32_EXTI1_BASE+STM32_EXTI_PR_OFFSET) - -# define STM32_EXTI2_IMR (STM32_EXTI2_BASE+STM32_EXTI_IMR_OFFSET) -# define STM32_EXTI2_EMR (STM32_EXTI2_BASE+STM32_EXTI_EMR_OFFSET) -# define STM32_EXTI2_RTSR (STM32_EXTI2_BASE+STM32_EXTI_RTSR_OFFSET) -# define STM32_EXTI2_FTSR (STM32_EXTI2_BASE+STM32_EXTI_FTSR_OFFSET) -# define STM32_EXTI2_SWIER (STM32_EXTI2_BASE+STM32_EXTI_SWIER_OFFSET) -# define STM32_EXTI2_PR (STM32_EXTI2_BASE+STM32_EXTI_PR_OFFSET) - -# define STM32_EXTI_IMR STM32_EXTI1_IMR -# define STM32_EXTI_EMR STM32_EXTI1_EMR -# define STM32_EXTI_RTSR STM32_EXTI1_RTSR -# define STM32_EXTI_FTSR STM32_EXTI1_FTSR -# define STM32_EXTI_SWIER STM32_EXTI1_SWIER -# define STM32_EXTI_PR STM32_EXTI1_PR - -#else -# define STM32_EXTI_IMR (STM32_EXTI_BASE+STM32_EXTI_IMR_OFFSET) -# define STM32_EXTI_EMR (STM32_EXTI_BASE+STM32_EXTI_EMR_OFFSET) -# define STM32_EXTI_RTSR (STM32_EXTI_BASE+STM32_EXTI_RTSR_OFFSET) -# define STM32_EXTI_FTSR (STM32_EXTI_BASE+STM32_EXTI_FTSR_OFFSET) -# define STM32_EXTI_SWIER (STM32_EXTI_BASE+STM32_EXTI_SWIER_OFFSET) -# define STM32_EXTI_PR (STM32_EXTI_BASE+STM32_EXTI_PR_OFFSET) -#endif - -/* Register Bitfield Definitions ********************************************/ - -/* EXTI lines > 15 are associated with internal devices: */ - -#if defined(CONFIG_STM32_STM32F10XX) -# define EXTI_PVD_LINE (1 << 16) /* EXTI line 16 is connected to the PVD output */ -# define EXTI_RTC_ALARM (1 << 17) /* EXTI line 17 is connected to the RTC Alarm event */ -# define EXTI_USB_WAKEUP (1 << 18) /* EXTI line 18 is connected to the USB Wakeup event */ -# ifdef CONFIG_STM32_CONNECTIVITYLINE -# define EXTI_ETH_WAKEUP (1 << 19) /* EXTI line 19 is connected to the Ethernet Wakeup event */ -# endif -#elif defined(CONFIG_STM32_STM32L15XX) -# define EXTI_PVD_LINE (1 << 16) /* EXTI line 16 is connected to the PVD output */ -# define EXTI_RTC_ALARM (1 << 17) /* EXTI line 17 is connected to the RTC Alarm event */ -# define EXTI_USB_WAKEUP (1 << 18) /* EXTI line 18 is connected to the USB Device FS Wakeup event */ -# define EXTI_RTC_TAMPER (1 << 19) /* EXTI line 19 is connected to the RTC Tamper and TimeStamp events */ -# define EXTI_RTC_WAKEUP (1 << 20) /* EXTI line 20 is connected to the RTC Wakeup event */ -# define EXTI_COMP1 (1 << 21) /* EXTI line 21 is connected to the Comparator 1 wakeup event */ -# define EXTI_COMP2 (1 << 22) /* EXTI line 22 is connected to the Comparator 2 wakeup event */ -# define EXTI_RTC_ACQUIRE (1 << 23) /* EXTI line 23 is connected to the channel acquisition interrupt */ -#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) -# define EXTI_PVD_LINE (1 << 16) /* EXTI line 16 is connected to the PVD output */ -# define EXTI_RTC_ALARM (1 << 17) /* EXTI line 17 is connected to the RTC Alarm event */ -# define EXTI_OTGFS_WAKEUP (1 << 18) /* EXTI line 18 is connected to the USB OTG FS Wakeup event */ -# define EXTI_ETH_WAKEUP (1 << 19) /* EXTI line 19 is connected to the Ethernet Wakeup event */ -# define EXTI_OTGHS_WAKEUP (1 << 20) /* EXTI line 20 is connected to the USB OTG HS Wakeup event */ -# define EXTI_RTC_TAMPER (1 << 21) /* EXTI line 21 is connected to the RTC Tamper and TimeStamp events */ -# define EXTI_RTC_TIMESTAMP (1 << 21) /* EXTI line 21 is connected to the RTC Tamper and TimeStamp events */ -# define EXTI_RTC_WAKEUP (1 << 22) /* EXTI line 22 is connected to the RTC Wakeup event */ -#elif defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) || \ - defined(CONFIG_STM32_STM32F37XX) -# define EXTI_PVD_LINE (1 << 16) /* EXTI line 16 is connected to the PVD output */ -# define EXTI_RTC_ALARM (1 << 17) /* EXTI line 17 is connected to the RTC Alarm event */ -# define EXTI_OTGFS_WAKEUP (1 << 18) /* EXTI line 18 is connected to the USB OTG FS Wakeup event */ -# define EXTI_RTC_TAMPER (1 << 19) /* EXTI line 19 is connected to the RTC Tamper and TimeStamp events */ -# define EXTI_RTC_TIMESTAMP (1 << 19) /* EXTI line 19 is connected to the RTC Tamper and TimeStamp events */ -# define EXTI_RTC_WAKEUP (1 << 20) /* EXTI line 20 is connected to the RTC Wakeup event */ -#elif defined(CONFIG_STM32_STM32G47XX) -# define EXTI_PVD_LINE (1 << 16) /* EXTI line 16 is connected to the PVD output */ -# define EXTI_RTC_ALARM (1 << 17) /* EXTI line 17 is connected to the RTC Alarm event */ -# define EXTI_USB_WAKEUP (1 << 18) /* EXTI line 18 is connected to the USB Device FS Wakeup event */ -# define EXTI_RTC_TIMESTAMP (1 << 19) /* EXTI line 19 is connected to the Timestamp or CSS_LSE events */ -# define EXTI_CSS_LSE (1 << 19) /* EXTI line 19 is connected to the Timestamp or CSS_LSE events */ -# define EXTI_RTC_WAKEUP (1 << 20) /* EXTI line 20 is connected to the RTC Wakeup event */ -# define EXTI_COMP1 (1 << 21) /* EXTI line 21 is connected to the Comparator 1 wakeup event */ -# define EXTI_COMP2 (1 << 22) /* EXTI line 22 is connected to the Comparator 2 wakeup event */ -# define EXTI_I2C1 (1 << 23) /* EXTI line 23 is connected to the I2C1 wakeup event */ -# define EXTI_I2C2 (1 << 24) /* EXTI line 24 is connected to the I2C2 wakeup event */ -# define EXTI_USART1 (1 << 25) /* EXTI line 25 is connected to the USART1 wakeup event */ -# define EXTI_USART2 (1 << 26) /* EXTI line 26 is connected to the USART2 wakeup event */ -# define EXTI_I2C3 (1 << 27) /* EXTI line 27 is connected to the I2C3 wakeup event */ -# define EXTI_USART3 (1 << 28) /* EXTI line 28 is connected to the USART3 wakeup event */ -# define EXTI_COMP3 (1 << 29) /* EXTI line 29 is connected to the Comparator 3 wakeup event */ -# define EXTI_COMP4 (1 << 30) /* EXTI line 30 is connected to the Comparator 4 wakeup event */ -# define EXTI_COMP5 (1 << 31) /* EXTI line 31 is connected to the Comparator 5 wakeup event */ -# define EXTI_COMP6 (1 << 0) /* EXTI line 32 is connected to the Comparator 6 wakeup event */ -# define EXTI_COMP7 (1 << 1) /* EXTI line 33 is connected to the Comparator 7 wakeup event */ -# define EXTI_USART4 (1 << 2) /* EXTI line 34 is connected to the USART4 wakeup event */ -# define EXTI_USART5 (1 << 3) /* EXTI line 35 is connected to the USART5 wakeup event */ -# define EXTI_LPUART1 (1 << 4) /* EXTI line 36 is connected to the LPUART1 wakeup event */ -# define EXTI_LPTIM1 (1 << 5) /* EXTI line 37 is connected to the LPTIM1 wakeup event */ -# define EXTI_PVM1 (1 << 8) /* EXTI line 40 is connected to the PVM1 wakeup event */ -# define EXTI_PVM2 (1 << 9) /* EXTI line 41 is connected to the PVM2 wakeup event */ -# define EXTI_I2C4 (1 << 10) /* EXTI line 42 is connected to the I2C4 wakeup event */ -# define EXTI_UCPD1 (1 << 11) /* EXTI line 43 is connected to the UCPD1 wakeup event */ -#endif - -/* Interrupt mask register */ - -#define EXTI_IMR_BIT(n) STM32_EXTI_BIT(n) /* 1=Interrupt request from line x is not masked */ -#define EXTI_IMR_SHIFT (0) /* Bits 0-X: Interrupt Mask for all lines */ -#define EXTI_IMR_MASK STM32_EXTI_MASK - -/* Event mask register */ - -#define EXTI_EMR_BIT(n) STM32_EXTI_BIT(n) /* 1=Event request from line x is not mask */ -#define EXTI_EMR_SHIFT (0) /* Bits Bits 0-X: Event Mask for all lines */ -#define EXTI_EMR_MASK STM32_EXTI_MASK - -/* Rising Trigger selection register */ - -#define EXTI_RTSR_BIT(n) STM32_EXTI_BIT(n) /* 1=Rising trigger enabled (for Event and Interrupt) for input line */ -#define EXTI_RTSR_SHIFT (0) /* Bits 0-X: Rising trigger event configuration bit for all lines */ -#define EXTI_RTSR_MASK STM32_EXTI_MASK - -/* Falling Trigger selection register */ - -#define EXTI_FTSR_BIT(n) STM32_EXTI_BIT(n) /* 1=Falling trigger enabled (for Event and Interrupt) for input line */ -#define EXTI_FTSR_SHIFT (0) /* Bits 0-X: Falling trigger event configuration bitfor all lines */ -#define EXTI_FTSR_MASK STM32_EXTI_MASK - -/* Software interrupt event register */ - -#define EXTI_SWIER_BIT(n) STM32_EXTI_BIT(n) /* 1=Sets the corresponding pending bit in EXTI_PR */ -#define EXTI_SWIER_SHIFT (0) /* Bits 0-X: Software Interrupt for all lines */ -#define EXTI_SWIER_MASK STM32_EXTI_MASK - -/* Pending register */ - -#define EXTI_PR_BIT(n) STM32_EXTI_BIT(n) /* 1=Selected trigger request occurred */ -#define EXTI_PR_SHIFT (0) /* Bits 0-X: Pending bit for all lines */ -#define EXTI_PR_MASK STM32_EXTI_MASK - -/* Compatibility Definitions ************************************************/ - -#if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) -# define STM32_NEXTI STM32_NEXTI1 -# define STM32_EXTI_MASK STM32_EXTI1_MASK -# define STM32_EXTI_IMR STM32_EXTI1_IMR -# define STM32_EXTI_EMR STM32_EXTI1_EMR -# define STM32_EXTI_RTSR STM32_EXTI1_RTSR -# define STM32_EXTI_FTSR STM32_EXTI1_FTSR -# define STM32_EXTI_SWIER STM32_EXTI1_SWIER -# define STM32_EXTI_PR STM32_EXTI1_PR -#endif - -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_EXTI_H */ diff --git a/arch/arm/src/stm32/hardware/stm32_fdcan.h b/arch/arm/src/stm32/hardware/stm32_fdcan.h deleted file mode 100644 index 11885bc6b57a3..0000000000000 --- a/arch/arm/src/stm32/hardware/stm32_fdcan.h +++ /dev/null @@ -1,588 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/hardware/stm32_fdcan.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_FDCAN_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_FDCAN_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "chip.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Only for STM32G4 */ - -#ifndef CONFIG_STM32_STM32G4XXX -# error STM32 FDCAN was tested only for STM32G4 -#endif - -/* Register Offsets *********************************************************/ - -#define STM32_FDCAN_CREL_OFFSET 0x0000 /* FDCAN core release register */ -#define STM32_FDCAN_ENDN_OFFSET 0x0004 /* FDCAN endian register */ - /* 0x0008 Reserved */ -#define STM32_FDCAN_DBTP_OFFSET 0x000c /* FDCAN data bit timing and prescaler register */ -#define STM32_FDCAN_TEST_OFFSET 0x0010 /* FDCAN test register */ -#define STM32_FDCAN_RWD_OFFSET 0x0014 /* FDCAN RAM watchdog register */ -#define STM32_FDCAN_CCCR_OFFSET 0x0018 /* FDCAN CC control register */ -#define STM32_FDCAN_NBTP_OFFSET 0x001c /* FDCAN nominal bit timing and prescaler register */ -#define STM32_FDCAN_TSCC_OFFSET 0x0020 /* FDCAN timestamp counter configuration register */ -#define STM32_FDCAN_TSCV_OFFSET 0x0024 /* FDCAN timestamp counter value register */ -#define STM32_FDCAN_TOCC_OFFSET 0x0028 /* FDCAN timeout counter configuration register */ -#define STM32_FDCAN_TOCV_OFFSET 0x002c /* FDCAN timeout counter value register */ - /* 0x0030 to 0x003c Reserved */ -#define STM32_FDCAN_ECR_OFFSET 0x0040 /* FDCAN error counter register */ -#define STM32_FDCAN_PSR_OFFSET 0x0044 /* FDCAN protocol status register */ -#define STM32_FDCAN_TDCR_OFFSET 0x0048 /* FDCAN transmitter delay compensation register */ - /* 0x004c Reserved */ -#define STM32_FDCAN_IR_OFFSET 0x0050 /* FDCAN interrupt register */ -#define STM32_FDCAN_IE_OFFSET 0x0054 /* FDCAN interrupt enable register */ -#define STM32_FDCAN_ILS_OFFSET 0x0058 /* FDCAN interrupt line select register */ -#define STM32_FDCAN_ILE_OFFSET 0x005c /* FDCAN interrupt line enable register */ - /* 0x0060 to 0x007c Reserved */ -#define STM32_FDCAN_RXGFC_OFFSET 0x0080 /* FDCAN global filter configuration register */ -#define STM32_FDCAN_XIDAM_OFFSET 0x0084 /* FDCAN extended ID and mask register */ -#define STM32_FDCAN_HPMS_OFFSET 0x0088 /* FDCAN high-priority message status register */ -#define STM32_FDCAN_RXFS_OFFSET(f) (0x0090 + ((f) << 3) -#define STM32_FDCAN_RXFA_OFFSET(f) (0x0094 + ((f) << 3) -#define STM32_FDCAN_RXF0S_OFFSET 0x0090 /* FDCAN Rx FIFO 0 status register */ -#define STM32_FDCAN_RXF0A_OFFSET 0x0094 /* CAN Rx FIFO 0 acknowledge register */ -#define STM32_FDCAN_RXF1S_OFFSET 0x0098 /* FDCAN Rx FIFO 1 status register */ -#define STM32_FDCAN_RXF1A_OFFSET 0x009c /* FDCAN Rx FIFO 1 acknowledge register */ - /* 0x00a0 to 0x00bc Reserved */ -#define STM32_FDCAN_TXBC_OFFSET 0x00c0 /* FDCAN Tx buffer configuration register */ -#define STM32_FDCAN_TXFQS_OFFSET 0x00c4 /* FDCAN Tx FIFO/queue status register */ -#define STM32_FDCAN_TXBRP_OFFSET 0x00c8 /* FDCAN Tx buffer request pending register */ -#define STM32_FDCAN_TXBAR_OFFSET 0x00cc /* FDCAN Tx buffer add request register */ -#define STM32_FDCAN_TXBCR_OFFSET 0x00d0 /* FDCAN Tx buffer cancellation request register */ -#define STM32_FDCAN_TXBTO_OFFSET 0x00d4 /* FDCAN Tx buffer transmission occurred register */ -#define STM32_FDCAN_TXBCNF_OFFSET 0x00d8 /* FDCAN Tx buffer cancellation finished register */ -#define STM32_FDCAN_TXBTIE_OFFSET 0x00dc /* FDCAN Tx buffer transmission interrupt enable register */ -#define STM32_FDCAN_TXBCIE_OFFSET 0x00e0 /* FDCAN Tx buffer cancellation finished interrupt enable register */ -#define STM32_FDCAN_TXEFS_OFFSET 0x00e4 /* FDCAN Tx event FIFO status register */ -#define STM32_FDCAN_TXEFA_OFFSET 0x00e8 /* FDCAN Tx event FIFO acknowledge register */ -#define STM32_FDCAN_CKDIV_OFFSET 0x0100 /* FDCAN CFG clock divider register */ - -/* Register Bitfield Definitions ********************************************/ - -/* FDCAN core release register */ - -#define FDCAN_CREL_DAY_SHIFT (0) /* Bits 0-7: DAY */ -#define FDCAN_CREL_DAY_MASK (0xff << FDCAN_CREL_DAY_SHIFT) -#define FDCAN_CREL_MON_SHIFT (8) /* Bits 8-15: MON */ -#define FDCAN_CREL_MON_MASK (0xff << FDCAN_CREL_MON_SHIFT) -#define FDCAN_CREL_YEAR_SHIFT (16) /* Bits 8-15: YEAR */ -#define FDCAN_CREL_YEAR_MASK (0x0f << FDCAN_CREL_YEAR_SHIFT) -#define FDCAN_CREL_SUBSTEP_SHIFT (20) /* Bits 20-23: SUBSTEP */ -#define FDCAN_CREL_SUBSTEP_MASK (0x0f << FDCAN_CREL_SUBSTEP_SHIFT) -#define FDCAN_CREL_STEP_SHIFT (24) /* Bits 24-27: STEP */ -#define FDCAN_CREL_STEP_MASK (0x0f << FDCAN_CREL_STEP_SHIFT) -#define FDCAN_CREL_REL_SHIFT (28) /* Bits 28-31: REL */ -#define FDCAN_CREL_REL_MASK (0x0f << FDCAN_CREL_REL_SHIFT) - -/* FDCAN data bit timing and prescaler register */ - -#define FDCAN_DBTP_DSJW_SHIFT (0) /* Bits 0-3: Synchronization jump width */ -#define FDCAN_DBTP_DSJW_MASK (0x0f << FDCAN_DBTP_DSJW_SHIFT) -# define FDCAN_DBTP_DSJW(value) ((value) << FDCAN_DBTP_DSJW_SHIFT) -# define FDCAN_DBTP_DSJW_MAX (15) -#define FDCAN_DBTP_DTSEG2_SHIFT (4) /* Bits 4-7: Data time segment after sample point*/ -#define FDCAN_DBTP_DTSEG2_MASK (0x0f << FDCAN_DBTP_DTSEG2_SHIFT) -# define FDCAN_DBTP_DTSEG2(value) ((value) << FDCAN_DBTP_DTSEG2_SHIFT) -# define FDCAN_DBTP_DTSEG2_MAX (15) -#define FDCAN_DBTP_DTSEG1_SHIFT (8) /* Bits 8-12: Data time segment before sample point*/ -#define FDCAN_DBTP_DTSEG1_MASK (0x1f << FDCAN_DBTP_DTSEG1_SHIFT) -# define FDCAN_DBTP_DTSEG1(value) ((value) << FDCAN_DBTP_DTSEG1_SHIFT) -# define FDCAN_DBTP_DTSEG1_MAX (31) -#define FDCAN_DBTP_DBRP_SHIFT (16) /* Bits 16-20: Data bitrate prescaler */ -#define FDCAN_DBTP_DBRP_MASK (0x1f << FDCAN_DBTP_DBRP_SHIFT) -# define FDCAN_DBTP_DBRP(value) ((value) << FDCAN_DBTP_DBRP_SHIFT) -# define FDCAN_DBTP_DBRP_MAX (31) -#define FDCAN_DBTP_TDC_EN (1 << 23) /* Bit 23: Transceiver delay compensation enable */ - -/* FDCAN test register */ - -#define FDCAN_TEST_LBCK (1 << 4) /* Bit 4: Loop back mode */ -#define FDCAN_TEST_TX_SHIFT (5) /* Bits 5-6: Control of transmit pin */ -#define FDCAN_TEST_TX_MASK (0x3 << FDCAN_TEST_TX_SHIFT) -# define FDCAN_TEST_TX_RESET (0 << FDCAN_TEST_TX_SHIFT) /* 00: TX is controlled by CAN core */ -# define FDCAN_TEST_TX_SP (1 << FDCAN_TEST_TX_SHIFT) /* 01: Sample point can be monitored at TX pin */ -# define FDCAN_TEST_TX_DLVL (2 << FDCAN_TEST_TX_SHIFT) /* 10: Dominant (0) level at TX pin */ -# define FDCAN_TEST_TX_RLVL (3 << FDCAN_TEST_TX_SHIFT) /* 11: Recesive (1) level at TX pin */ -#define FDCAN_TEST_RX (1 << 7) /* Bit 7: Receive pin */ - -/* FDCAN RAM watchdog register */ - -#define FDCAN_RWD_WDC_SHIFT (0) /* Bits 0-7: RAM watchdog counter start value */ -#define FDCAN_RWD_WDC_MASK (0xff << FDCAN_RWD_WDC_SHIFT) -# define FDCAN_RWD_WDC_DIS (0 << FDCAN_RWD_WDC_SHIFT) /* Counter disabled */ -# define FDCAN_RWD_WDC(value) ((value) << FDCAN_RWD_WDC_SHIFT) -#define FDCAN_RWD_WDV_SHIFT (8) /* Bits 8-15: RAM watchdog counter value */ -#define FDCAN_RWD_WDV_MASK (0xff << FDCAN_RWD_WDV_SHIFT) - -/* FDCAN CC control register */ - -#define FDCAN_CCCR_INIT (1 << 0) /* Bit 0: Initialization */ -#define FDCAN_CCCR_CCE (1 << 1) /* Bit 1: Configuration change enable */ -#define FDCAN_CCCR_ASM (1 << 2) /* Bit 2: ASM restricted operation mode */ -#define FDCAN_CCCR_CSA (1 << 3) /* Bit 3: Clock stop acknowledge */ -#define FDCAN_CCCR_CSR (1 << 4) /* Bit 4: Clock stop request */ -#define FDCAN_CCCR_MON (1 << 5) /* Bit 5: Bus monitoring mode */ -#define FDCAN_CCCR_DAR (1 << 6) /* Bit 6: Disable automatic retransmission */ -#define FDCAN_CCCR_TEST (1 << 7) /* Bit 7: Test mode enable */ -#define FDCAN_CCCR_FDOE (1 << 8) /* Bit 8: FD operation enable */ -#define FDCAN_CCCR_BRSE (1 << 9) /* Bit 9: FDCAN Bitrate switching */ - /* Bits 10-11: Reserved */ -#define FDCAN_CCCR_PXHD (1 << 12) /* Bit 12: Protocol exception handling disable */ -#define FDCAN_CCCR_EFBI (1 << 13) /* Bit 13: Edge filtering during bus integration */ -#define FDCAN_CCCR_TXP (1 << 14) /* Bit 14: Tx pause */ -#define FDCAN_CCCR_NISO (1 << 15) /* Bit 15: Non ISO operation */ - -/* FDCAN nominal bit timing and prescaler register */ - -#define FDCAN_NBTP_NTSEG2_SHIFT (0) /* Bits 0-6: Nominal time segment after sample point */ -#define FDCAN_NBTP_NTSEG2_MASK (0x7f << FDCAN_NBTP_NTSEG2_SHIFT) -# define FDCAN_NBTP_NTSEG2(value) ((value) << FDCAN_NBTP_NTSEG2_SHIFT) -# define FDCAN_NBTP_NTSEG2_MAX (127) -#define FDCAN_NBTP_NTSEG1_SHIFT (8) /* Bits 8-15: Nominal time segment before sample point */ -#define FDCAN_NBTP_NTSEG1_MASK (0xff << FDCAN_NBTP_NTSEG1_SHIFT) -# define FDCAN_NBTP_NTSEG1(value) ((value) << FDCAN_NBTP_NTSEG1_SHIFT) -# define FDCAN_NBTP_NTSEG1_MAX (255) -#define FDCAN_NBTP_NBRP_SHIFT (16) /* Bits 16-24: Bitrate prescaler */ -#define FDCAN_NBTP_NBRP_MASK (0x1ff << FDCAN_NBTP_NBRP_SHIFT) -# define FDCAN_NBTP_NBRP(value) ((value) << FDCAN_NBTP_NBRP_SHIFT) -# define FDCAN_NBTP_NBRP_MAX (511) -#define FDCAN_NBTP_NSJW_SHIFT (25) /* Bits 25-31: Nominal (re)synchronization jump width */ -#define FDCAN_NBTP_NSJW_MASK (0x7f << FDCAN_NBTP_NSJW_SHIFT) -# define FDCAN_NBTP_NSJW(value) ((value) << FDCAN_NBTP_NSJW_SHIFT) -# define FDCAN_NBTP_NSJW_MAX (127) - -/* FDCAN timestamp counter configuration register */ - -#define FDCAN_TSCC_TSS_SHIFT (0) /* Bits 0-1: Timestamp counter select */ -#define FDCAN_TSCC_TSS_MASK (0x3 << FDCAN_TSCC_TSS_SHIFT) -# define FDCAN_TSCC_TSS_ZERO (0 << FDCAN_TSCC_TSS_SHIFT) /* 00: Always 0 */ -# define FDCAN_TSCC_TSS_TCP (1 << FDCAN_TSCC_TSS_SHIFT) /* 01: Incremented based on TCP */ -# define FDCAN_TSCC_TSS_TIM3 (2 << FDCAN_TSCC_TSS_SHIFT) /* 10: Value from TIM3 used */ -#define FDCAN_TSCC_TCP_SHIFT (16) /* Bits 16-19: Timestamp counter prescaler */ -#define FDCAN_TSCC_TCP_MASK (0x0f << FDCAN_TSCC_TCP_SHIFT) -# define FDCAN_TSCC_TCP(value) ((value) << FDCAN_TSCC_TCP_SHIFT) - -/* FDCAN timestamp counter value register */ - -#define FDCAN_TSCV_TSC_SHIFT (0) /* Bits 0-15: Timestamp counter */ -#define FDCAN_TSCV_TSC_MASK (0xffff << FDCAN_TSCV_TSC_SHIFT) - -/* FDCAN timeout counter configuration register */ - -#define FDCAN_TOCC_ETOC (1 << 0) /* Bit 0: Enable timeout counter */ -#define FDCAN_TOCC_TOS_SHIFT (1) /* Bits 1-2: Timeout select */ -#define FDCAN_TOCC_TOS_MASK (0x03 << FDCAN_TOCC_TOS_SHIFT) -# define FDCAN_TOCC_TOS_CONT (0 << FDCAN_TOCC_TOS_SHIFT) /* 00: Continuous operation */ -# define FDCAN_TOCC_TOS_TXFIFO (1 << FDCAN_TOCC_TOS_SHIFT) /* 01: Tx event FIFO */ -# define FDCAN_TOCC_TOS_RX_FIFO0 (2 << FDCAN_TOCC_TOS_SHIFT) /* 10: Rx FIFO 0 */ -# define FDCAN_TOCC_TOS_RX_FIFO1 (3 << FDCAN_TOCC_TOS_SHIFT) /* 11: Rx FIFO 1 */ -#define FDCAN_TOCC_TOP_SHIFT (16) /* Bits 16-31: Timeout period counter start value */ -#define FDCAN_TOCC_TOP_MASK (0xffff << FDCAN_TOCC_TOP_SHIFT) -# define FDCAN_TOCC_TOP(value) ((value) << FDCAN_TOCC_TOP_SHIFT) - -/* FDCAN timeout counter value register */ - -#define FDCAN_TOCV_TOC_SHIFT (0) /* Bits 0-15: Timestamp counter */ -#define FDCAN_TOCV_TOC_MASK (0xffff << FDCAN_TOCV_TOC_SHIFT) - -/* FDCAN error counter register */ - -#define FDCAN_ECR_TEC_SHIFT (0) /* Bits 0-7: Transmit error counter */ -#define FDCAN_CR_TEC_MASK (0xff << FDCAN_ECR_TEC_SHIFT) -#define FDCAN_ECR_REC_SHIFT (8) /* Bits 8-14: Receive error counter */ -#define FDCAN_ECR_REC_MASK (0x7f << FDCAN_ECR_REC_SHIFT) -#define FDCAN_ECR_RP (1 << 15) /* Bit 15: Receive error passive */ -#define FDCAN_ECR_CEL_SHIFT (16) /* Bits 16-23: CAN error logging */ -#define FDCAN_ECR_CEL_MASK (0xff << FDCAN_ECR_CEL_SHIFT) - -/* FDCAN protocol status register */ - -/* Error codes */ - -#define FDCAN_PSR_EC_NO_ERROR (0) /* No error occurred since LEC has been reset */ -#define FDCAN_PSR_EC_STUFF_ERROR (1) /* More than 5 equal bits in a sequence */ -#define FDCAN_PSR_EC_FORM_ERROR (2) /* Part of a received frame has wrong format */ -#define FDCAN_PSR_EC_ACK_ERROR (3) /* Message not acknowledged by another node */ -#define FDCAN_PSR_EC_BIT1_ERROR (4) /* Send with recessive level, but bus value was dominant */ -#define FDCAN_PSR_EC_BIT0_ERROR (5) /* Send with dominant level, but bus value was recessive */ -#define FDCAN_PSR_EC_CRC_ERROR (6) /* CRC received message incorrect */ -#define FDCAN_PSR_EC_NO_CHANGE (7) /* No CAN bus event was detected since last read */ - -#define FDCAN_PSR_LEC_SHIFT (0) /* Bits 0-2: Last error code */ -#define FDCAN_PSR_LEC_MASK (0x7 << FDCAN_PSR_LEC_SHIFT) -# define FDCAN_PSR_LEC(n) ((uint32_t)(n) << FDCAN_PSR_LEC_SHIFT) /* See error codes above */ -#define FDCAN_PSR_ACT_SHIFT (3) /* Bits 3-4: Activity */ -#define FDCAN_PSR_ACT_MASK (3 << FDCAN_PSR_ACT_SHIFT) -# define FDCAN_PSR_ACT_SYNC (0 << FDCAN_PSR_ACT_SHIFT) /* 00: Synchronizing */ -# define FDCAN_PSR_ACT_IDLE (1 << FDCAN_PSR_ACT_SHIFT) /* 01: Idle */ -# define FDCAN_PSR_ACT_RECV (2 << FDCAN_PSR_ACT_SHIFT) /* 10: Receiver */ -# define FDCAN_PSR_ACT_TRANS (3 << FDCAN_PSR_ACT_SHIFT) /* 11: Transmitter */ -#define FDCAN_PSR_EP (1 << 5) /* Bit 5: Error passive */ -#define FDCAN_PSR_EW (1 << 6) /* Bit 6: Warning status */ -#define FDCAN_PSR_BO (1 << 7) /* Bit 7: Bus_off status */ -#define FDCAN_PSR_DLEC_SHIFT (8) /* Bits 8-10: Data last error code */ -#define FDCAN_PSR_DLEC_MASK (0x7 << FDCAN_PSR_DLEC_SHIFT) -# define FDCAN_PSR_DLEC(n) ((uint32_t)(n) << FDCAN_PSR_DLEC_SHIFT) /* See error codes above */ -#define FDCAN_PSR_RESI (1 << 11) /* Bit 11: ESI flag of last message */ -#define FDCAN_PSR_RBRS (1 << 12) /* Bit 12: BRS flag of last message */ -#define FDCAN_PSR_REDL (1 << 13) /* Bit 13: Received message */ -#define FDCAN_PSR_PXE (1 << 14) /* Bit 14: Protocol exception event */ -#define FDCAN_PSR_TDCV_SHIFT (16) /* Bits 16-22: Transmitter delay compensation */ -#define FDCAN_PSR_TDCV_MASK (0x7f << FDCAN_PSR_TDCV_SHIFT) - -/* FDCAN transmitter delay compensation register */ - -#define FDCAN_TDCR_TDCF_SHIFT (0) /* Bits 0-6: Transmitter delay compensation filter window length */ -#define FDCAN_TDCR_TDCF_MASK (0x7f << FDCAN_TDCR_TDCF_SHIFT) -# define FDCAN_TDCR_TDCF(value) ((value) << FDCAN_TDCR_TDCF_SHIFT) -#define FDCAN_TDCR_TDCO_SHIFT (8) /* Bits 8-14: Transmiiter delay compensation offset */ -#define FDCAN_TDCR_TDCO_MASK (0x7f << FDCAN_TDCR_TDCO_SHIFT) -# define FDCAN_TDCR_TDCO(value) ((value) << FDCAN_TDCR_TDCO_SHIFT) - -/* FDCAN interrupt register and interrupt enable register */ - -#define FDCAN_INT_RF0N (1 << 0) /* Bit 0: Rx FIFO 0 new message */ -#define FDCAN_INT_RF0F (1 << 1) /* Bit 1: Rx FIFO 0 full */ -#define FDCAN_INT_RF0L (1 << 2) /* Bit 2: Rx FIFO 0 message lost */ -#define FDCAN_INT_RF1N (1 << 3) /* Bit 3: Rx FIFO 1 new message */ -#define FDCAN_INT_RF1F (1 << 4) /* Bit 4: Rx FIFO 1 full */ -#define FDCAN_INT_RF1L (1 << 5) /* Bit 5: Rx FIFO 1 message lost */ -#define FDCAN_INT_HPM (1 << 6) /* Bit 6: High priority message */ -#define FDCAN_INT_TC (1 << 7) /* Bit 7: Transmission completed */ -#define FDCAN_INT_TCF (1 << 8) /* Bit 8: Transmission cancellation finished */ -#define FDCAN_INT_TFE (1 << 9) /* Bit 9: Tx FIFO empty */ -#define FDCAN_INT_TEFN (1 << 10) /* Bit 10: Tx event FIFO new entry */ -#define FDCAN_INT_TEFF (1 << 11) /* Bit 11: Tx event FIFO full */ -#define FDCAN_INT_TEFL (1 << 12) /* Bit 12: Tx event FIFO element lost */ -#define FDCAN_INT_TSW (1 << 13) /* Bit 13: Timestamp wraparound */ -#define FDCAN_INT_MRAF (1 << 14) /* Bit 14: Message RAM access failure */ -#define FDCAN_INT_TOO (1 << 15) /* Bit 15: Timeout occurred */ -#define FDCAN_INT_ELO (1 << 16) /* Bit 16: Error logging overflow */ -#define FDCAN_INT_EP (1 << 17) /* Bit 17: Error_passive status */ -#define FDCAN_INT_EW (1 << 18) /* Bit 18: Error_warning status */ -#define FDCAN_INT_BO (1 << 19) /* Bit 19: Buss_off status */ -#define FDCAN_INT_WDI (1 << 20) /* Bit 20: Watchdog interrupt */ -#define FDCAN_INT_PEA (1 << 21) /* Bit 21: Protocol error arbitration phase */ -#define FDCAN_INT_PED (1 << 22) /* Bit 22: Protocol error data phase */ -#define FDCAN_INT_ARA (1 << 23) /* Bit 23: Access to reserved address */ - -/* FDCAN interrupt line select register */ - -#define FDCAN_ILS_RXFIFO0 (1 << 0) /* Bit 0: RXFIFO 0 */ -#define FDCAN_ILS_RXFIFO1 (1 << 1) /* Bit 1: RXFIFO 1 */ -#define FDCAN_ILS_SMG (1 << 2) /* Bit 2: SMSG */ -#define FDCAN_ILS_TFERR (1 << 3) /* Bit 3: TFERR */ -#define FDCAN_ILS_MISC (1 << 4) /* Bit 4: MISC */ -#define FDCAN_ILS_BERR (1 << 5) /* Bit 5: BERR */ -#define FDCAN_ILS_PERR (1 << 6) /* Bit 6: PERR */ - -/* FDCAN interrupt line enable register */ - -#define FDCAN_ILE_EINT0 (1 << 0) /* Bit 0: Enable interrupt line 0 */ -#define FDCAN_ILE_EINT1 (1 << 1) /* Bit 1: Enable interrupt line 1 */ - -/* FDCAN global filter configuration register */ - -#define FDCAN_RXGFC_RRFE (1 << 0) /* Bit 0: Reject remote frames ext */ -#define FDCAN_RXGFC_RRFS (1 << 1) /* Bit 1: Reject remote frames std */ -#define FDCAN_RXGFC_ANFE_SHIFT (2) /* Bits 2-3: Accept non-matching frames ext */ -#define FDCAN_RXGFC_ANFE_MASK (0x3 << FDCAN_RXGFC_ANFE_SHIFT) -# define FDCAN_RXGFC_ANFE_RX_FIFO0 (0 << FDCAN_RXGFC_ANFE_SHIFT) /* 00: Accept in Rx FIFO 0 */ -# define FDCAN_RXGFC_ANFE_RX_FIFO1 (1 << FDCAN_RXGFC_ANFE_SHIFT) /* 01: Accept in Rx FIFO 1 */ -# define FDCAN_RXGFC_ANFE_REJECTED (2 << FDCAN_RXGFC_ANFE_SHIFT) /* 10: Reject */ -#define FDCAN_RXGFC_ANFS_SHIFT (4) /* Bits 5-4: Accept non-matching frames std */ -#define FDCAN_RXGFC_ANFS_MASK (0x3 << FDCAN_RXGFC_ANFS_SHIFT) -# define FDCAN_RXGFC_ANFS_RX_FIFO0 (0 << FDCAN_RXGFC_ANFS_SHIFT) /* 00: Accept in Rx FIFO 0 */ -# define FDCAN_RXGFC_ANFS_RX_FIFO1 (1 << FDCAN_RXGFC_ANFS_SHIFT) /* 01: Accept in Rx FIFO 1 */ -# define FDCAN_RXGFC_ANFS_REJECTED (2 << FDCAN_RXGFC_ANFS_SHIFT) /* 10: Reject */ -#define FDCAN_RXGFC_F1OM (1 << 8) /* Bit 8: FIFO 1 operation mode */ -#define FDCAN_RXGFC_F0OM (1 << 9) /* Bit 9: FIFO 0 operation mode */ -#define FDCAN_RXGFC_LSS_SHIFT (16) /* Bits 16-20: List size std */ -#define FDCAN_RXGFC_LSS_MASK (0x1f << FDCAN_RXGFC_LSS_SHIFT) -# define FDCAN_RXGFC_LSS(value) ((value) << FDCAN_RXGFC_LSS_SHIFT) -# define FDCAN_RXGFC_LSS_MAX (28) -#define FDCAN_RXGFC_LSE_SHIFT (24) /* Bits 24-27: List size ext */ -#define FDCAN_RXGFC_LSE_MASK (0x1f << FDCAN_RXGFC_LSE_SHIFT) -# define FDCAN_RXGFC_LSE(value) ((value) << FDCAN_RXGFC_LSE_SHIFT) -# define FDCAN_RXGFC_LSE_MAX (8) - -/* FDCAN extended ID and mask register */ - -#define FDCAN_XIDAM_EIDM_SHIFT (0) /* Bits 0-28: Extended ID mask */ -#define FDCAN_XIDAM_EIDM_MASK (0x1fffffff << FDCAN_XIDAM_EIDM_SHIFT) - -/* FDCAN high-priority message status register */ - -#define FDCAN_HPMS_BIDX_SHIFT (0) /* Bits 0-2: Buffer index */ -#define FDCAN_HPMS_BIDX_MASK (0x7 << FDCAN_HPMS_BIDX_SHIFT) -# define FDCAN_HPMS_BIDX(value) ((value) << FDCAN_HPMS_BIDX_SHIFT) -#define FDCAN_HPMS_MSI_SHIFT (6) /* Bits 6-7: Message storage indicator */ -#define FDCAN_HPMS_MSI_MASK (0x3 << FDCAN_HPMS_MSI_SHIFT) -# define FDCAN_HPMS_MSI(value) ((value) << FDCAN_HPMS_MSI_SHIFT) -#define FDCAN_HPMS_FIDX_SHIFT (8) /* Bits 8-12: Filter index */ -#define FDCAN_HPMS_FIDX_MASK (0x1f << FDCAN_HPMS_FIDX_SHIFT) -# define FDCAN_HPMS_FIDX(value) ((value) << FDCAN_HPMS_FIDX_SHIFT) -#define FDCAN_HPMS_FLST (1 << 15) /* Bit 15: Filter list */ - -/* FDCAN Rx FIFO x status register */ - -#define FDCAN_RXFS_FFL_SHIFT (0) /* Bits 0-3: FIFO fill level */ -#define FDCAN_RXFS_FFL_MASK (0xf << FDCAN_RXFS_FFL_SHIFT) -# define FDCAN_RXFS_FFL(value) ((value) << FDCAN_RXFS_FFL_SHIFT) -#define FDCAN_RXFS_FGI_SHIFT (8) /* Bits 8-9: FIFO get index */ -#define FDCAN_RXFS_FGI_MASK (0x3 << FDCAN_RXFS_FGI_SHIFT) -# define FDCAN_RXFS_FGI(value) ((value) << FDCAN_RXFS_FGI_SHIFT) -#define FDCAN_RXFS_FPI_SHIFT (16) /* Bits 16-17: FIFO put index */ -#define FDCAN_RXFS_FPI_MASK (0x3 << FDCAN_RXFS_FPI_SHIFT) -# define FDCAN_RXFS_FPI(value) ((value) << FDCAN_RXFS_FPI_SHIFT) -#define FDCAN_RXFS_FF (1 << 24) /* Bit 24: FIFO full */ -#define FDCAN_RXFS_RFL (1 << 25) /* Bit 25: FIFO message lost */ - -/* FDCAN Rx FIFO x acknowledge register */ - -#define FDCAN_RXFA_FAI_SHIFT (0) /* Bits 0-2: FIFO 0 acknowledge index */ -#define FDCAN_RXFA_FAI_MASK (0x7 << FDCAN_RXFA_FAI_SHIFT) - -/* FDCAN Tx buffer configuration register */ - -#define FDCAN_TXBC_TFQM (1 << 24) /* Bit 24: FIFO/queue mode */ - -/* FDCAN Tx FIFO/queue status register */ - -#define FDCAN_TXFQS_TFFL_SHIFT (0) /* Bits 0-2: FIFO free level */ -#define FDCAN_TXFQS_TFFL_MASK (0x7 << FDCAN_TXFQS_TFFL_SHIFT) -#define FDCAN_TXFQS_TFGI_SHIFT (8) /* Bits 8-9: FIFO get index */ -#define FDCAN_TXFQS_TFGI_MASK (0x3 << FDCAN_TXFQS_TFGI_SHIFT) -#define FDCAN_TXFQS_TFQPI_SHIFT (16) /* Bits 20-16: FIFO/queue put index */ -#define FDCAN_TXFQS_TFQPI_MASK (0x3 << FDCAN_TXFQS_TFQPI_SHIFT) -#define FDCAN_TXFQS_TFQF (1 << 21) /* Bit 21: FIFO/queue full */ - -/* FDCAN Tx buffer request pending register */ - -#define FDCAN_TXBRP_TRP_SHIFT (0) /* Bits 0-2: Transmission request pending */ -#define FDCAN_TXBRP_TRP_MASK (0x7 << FDCAN_TXBRP_TRP_SHIFT) -# define FDCAN_TXBRP_TRP(value) ((value) << FDCAN_TXBRP_TRP_SHIFT) - -/* FDCAN Tx buffer add request register */ - -#define FDCAN_TXBAR_AR_SHIFT (0) /* Bits 0-2: Add request */ -#define FDCAN_TXBAR_AR_MASK (0x7 << FDCAN_TXBAR_AR_SHIFT) -# define FDCAN_TXBAR_AR(value) ((value) << FDCAN_TXBAR_AR_SHIFT) - -/* FDCAN Tx buffer cancellation request register */ - -#define FDCAN_TXBCR_CR_SHIFT (0) /* Bits 0-2: Cancellation request */ -#define FDCAN_TXBCR_CR_MASK (0x7 << FDCAN_TXBCR_CR_SHIFT) -# define FDCAN_TXBCR_CR(value) ((value) << FDCAN_TXBCR_CR_SHIFT) - -/* FDCAN Tx buffer transmission occurred register */ - -#define FDCAN_TXBTO_TO_SHIFT (0) /* Bits 0-2: Transmission occurred */ -#define FDCAN_TXBTO_TO_MASK (0x7 << FDCAN_TXBTO_TO_SHIFT) - -/* FDCAN Tx buffer cancellation finished register */ - -#define FDCAN_TXBCF_CF_SHIFT (0) /* Bits 0-2: Cancellation finished */ -#define FDCAN_TXBCF_CF_MASK (0x7 << FDCAN_TXBCF_CF_SHIFT) - -/* FDCAN Tx buffer transmission interrupt enable register */ - -#define FDCAN_TXBTIE_TIE_SHIFT (0) /* Bits 0-2: Transmission interrupt enable */ -#define FDCAN_TXBTIE_TIE_MASK (0x7 << FDCAN_TXBTIE_TIE_SHIFT) -# define FDCAN_TXBTIE_TIE(value) ((value) << FDCAN_TXBTIE_TIE_SHIFT) - -/* FDCAN Tx buffer cancellation finished interrupt enable register */ - -#define FDCAN_TXBCIE_CFIE_SHIFT (0) /* Bits 0-2: Cancellation finished interrupt enable */ -#define FDCAN_TXBCIE_CFIE_MASK (0x7 << FDCAN_TXBCIE_CFIE_SHIFT) -# define FDCAN_TXBCIE_CFIE(value) ((value) << FDCAN_TXBCIE_CFIE_SHIFT) - -/* FDCAN Tx event FIFO status register */ - -#define FDCAN_TXEFS_EFFL_SHIFT (2) /* Bits 0-2: Event FIFO fill level */ -#define FDCAN_TXEFS_EFFL_MASK (0x7 << FDCAN_TXEFC_EFFL_SHIFT) -# define FDCAN_TXEFC_EFFL(value) ((value) << FDCAN_TXEFC_EFFL_SHIFT) -#define FDCAN_TXEFS_EFGI_SHIFT (8) /* Bits 8-9: Event FIFO get index */ -#define FDCAN_TXEFS_EFGI_MASK (0x3 << FDCAN_TXEFS_EFGI_SHIFT) -# define FDCAN_TXEFS_EFGI(value) ((value) << FDCAN_TXEFS_EFGI_SHIFT) -#define FDCAN_TXEFS_EFPI_SHIFT (16) /* Bits 16-17: Event FIFO put index */ -#define FDCAN_TXEFS_EFPI_MASK (0x3 << FDCAN_TXEFS_EFPI_SHIFT) -# define FDCAN_TXEFS_EFPI(value) ((value) << FDCAN_TXEFS_EFPI_SHIFT) -#define FDCAN_TXEFS_EFF (1 << 24) /* Bit 24: Event FIFO full */ -#define FDCAN_TXEFS_TEFL (1 << 25) /* Bit 25: Tx Event FIFO element lost */ - /* Bits 26-31: Reserved */ - -/* FDCAN Tx event FIFO acknowledge register */ - -#define FDCAN_TXEFA_EFAI_SHIFT (0) /* Bits 0-3: Event FIFO acknowledge index */ -#define FDCAN_TXEFA_EFAI_MASK (0x3 << FDCAN_TXEFA_EFAI_SHIFT) - -/* FDCAN CFG clock divider register */ - -#define FDCAN_CKDIV_PDIV_SHIFT (0) /* Bits 0-3: Input clock divider */ -#define FDCAN_CKDIV_PDIV_MASK (0xf << FDCAN_CKDIV_PDIV_SHIFT) - -/* Message RAM Definitions **************************************************/ - -/* Common Buffer and FIFO element bit definitions: - * - * --------------- ------------------- -------------------------------- - * RESOURCE R0 R1 - * --------------- ------------------- -------------------------------- - * RX FIFO: ESI, XTD, RTR, ID, ANMF, FIDX, EDL, BRS, DLC, RXTS - * TX buffer: XTD, RTR, ID, MM, EFC, DLC - * TX Event FIFO: ESI, XTD, RTR, ID, MM, ET, EDL, BRS, DLC, TXTS - * --------------- ------------------- -------------------------------- - */ - -/* Common */ - -#define BUFFER_R0_EXTID_SHIFT (0) /* Bits 0-28: Extended identifier */ -#define BUFFER_R0_EXTID_MASK (0x1fffffff << BUFFER_R0_EXTID_SHIFT) -# define BUFFER_R0_EXTID(n) ((uint32_t)(n) << BUFFER_R0_EXTID_SHIFT) -#define BUFFER_R0_STDID_SHIFT (18) /* Bits 18-28: Standard identifier */ -#define BUFFER_R0_STDID_MASK (0x7ff << BUFFER_R0_STDID_SHIFT) -# define BUFFER_R0_STDID(n) ((uint32_t)(n) << BUFFER_R0_STDID_SHIFT) -#define BUFFER_R0_RTR (1 << 29) /* Bit 29: Remote Transmission Request */ -#define BUFFER_R0_XTD (1 << 30) /* Bit 30: Extended Identifier */ -#define BUFFER_R0_ESI (1 << 31) /* Bit 31: Error State Indicator */ - -/* Common */ - -#define BUFFER_R1_DLC_SHIFT (16) /* Bits 16-19: Date length code */ -#define BUFFER_R1_DLC_MASK (15 << BUFFER_R1_DLC_SHIFT) -# define BUFFER_R1_DLC(n) ((uint32_t)(n) << BUFFER_R1_DLC_SHIFT) -#define BUFFER_R1_BRS (1 << 20) /* Bit 20: Bit Rate Switch */ -#define BUFFER_R1_FDF (1 << 21) /* Bit 21: FD Format */ - -/* RX buffer/RX FIFOs */ - -#define BUFFER_R1_RXTS_SHIFT (0) /* Bits 0-15: RX Timestamp */ -#define BUFFER_R1_RXTS_MASK (0xffff << BUFFER_R1_RXTS_SHIFT) -# define BUFFER_R1_RXTS(n) ((uint32_t)(n) << BUFFER_R1_RXTS_SHIFT) -#define BUFFER_R1_FIDX_SHIFT (24) /* Bits 24-30: Filter index */ -#define BUFFER_R1_FIDX_MASK (0x7f << BUFFER_R1_FIDX_SHIFT) -# define BUFFER_R1_FIDX(n) ((uint32_t)(n) << BUFFER_R1_FIDX_SHIFT) -#define BUFFER_R1_ANMF (1 << 31) /* Bit 31: Accepted Non-matching Frame */ - -/* TX buffer/TX Event FIFO */ - -#define BUFFER_R1_MM_SHIFT (24) /* Bits 24-31: Message Marker */ -#define BUFFER_R1_MM_MASK (0xff << BUFFER_R1_MM_SHIFT) -# define BUFFER_R1_MM(n) ((uint32_t)(n) << BUFFER_R1_MM_SHIFT) - -/* TX buffer */ - -#define BUFFER_R1_EFC (1 << 23) /* Bit 23: Event FIFO Control */ - -/* TX Event FIFO */ - -#define BUFFER_R1_TXTS_SHIFT (0) /* Bits 0-15: TX Timestamp */ -#define BUFFER_R1_TXTS_MASK (0xffff << BUFFER_R1_TXTS_SHIFT) -# define BUFFER_R1_TXTS(n) ((uint32_t)(n) << BUFFER_R1_TXTS_SHIFT) -#define BUFFER_R1_EDL (1 << 21) /* Bit 21: Extended Data Length */ -#define BUFFER_R1_ET_SHIFT (22) /* Bits 22-23: Event Type */ -#define BUFFER_R1_ET_MASK (3 << BUFFER_R1_ET_SHIFT) -# define BUFFER_R1_ET_TXEVENT (1 << BUFFER_R1_ET_SHIFT) /* Tx event */ -# define BUFFER_R1_ET_TXCANCEL (2 << BUFFER_R1_ET_SHIFT) /* Transmission despite cancellation */ - -/* Standard Message ID Filter Element */ - -#define STDFILTER_S0_SFID2_SHIFT (0) /* Bits 0-10: Standard Filter ID 2 */ -#define STDFILTER_S0_SFID2_MASK (0x7ff << STDFILTER_S0_SFID2_SHIFT) -# define STDFILTER_S0_SFID2(n ) ((uint32_t)(n) << STDFILTER_S0_SFID2_SHIFT) -#define STDFILTER_S0_BUFFER_SHIFT (0) /* Bits 0-5: RX buffer start address */ -#define STDFILTER_S0_BUFFER_MASK (63 << STDFILTER_S0_BUFFER_SHIFT) -# define STDFILTER_S0_BUFFER(n) ((uint32_t)(n) << STDFILTER_S0_BUFFER_SHIFT) -#define STDFILTER_S0_ACTION_SHIFT (9) /* Bits 9-10: Action taken */ -#define STDFILTER_S0_ACTION_MASK (3 << STDFILTER_S0_ACTION_SHIFT) -# define STDFILTER_S0_RXBUFFER (0 << STDFILTER_S0_ACTION_SHIFT) /* Store message in a Rx buffer */ -# define STDFILTER_S0_DEBUGA (1 << STDFILTER_S0_ACTION_SHIFT) /* Debug Message A */ -# define STDFILTER_S0_DEBUGB (2 << STDFILTER_S0_ACTION_SHIFT) /* Debug Message B */ -# define STDFILTER_S0_DEBUGC (3 << STDFILTER_S0_ACTION_SHIFT) /* Debug Message C */ -#define STDFILTER_S0_SFID1_SHIFT (16) /* Bits 16-26: Standard Filter ID 2 */ -#define STDFILTER_S0_SFID1_MASK (0x7ff << STDFILTER_S0_SFID1_SHIFT) -# define STDFILTER_S0_SFID1(n) ((uint32_t)(n) << STDFILTER_S0_SFID1_SHIFT) -#define STDFILTER_S0_SFEC_SHIFT (27) /* Bits 27-29: Standard Filter Element Configuration */ -#define STDFILTER_S0_SFEC_MASK (7 << STDFILTER_S0_SFEC_SHIFT) -# define STDFILTER_S0_SFEC_DISABLE (0 << STDFILTER_S0_SFEC_SHIFT) /* Disable filter element */ -# define STDFILTER_S0_SFEC_FIFO0 (1 << STDFILTER_S0_SFEC_SHIFT) /* Store in Rx FIFO 0 on match */ -# define STDFILTER_S0_SFEC_FIFO1 (2 << STDFILTER_S0_SFEC_SHIFT) /* Store in Rx FIFO 1 on match */ -# define STDFILTER_S0_SFEC_REJECT (3 << STDFILTER_S0_SFEC_SHIFT) /* Reject ID on match */ -# define STDFILTER_S0_SFEC_PRIORITY (4 << STDFILTER_S0_SFEC_SHIFT) /* Set priority ion match */ -# define STDFILTER_S0_SFEC_PRIOFIFO0 (5 << STDFILTER_S0_SFEC_SHIFT) /* Set priority and store in FIFO 0 on match */ -# define STDFILTER_S0_SFEC_PRIOFIFO1 (6 << STDFILTER_S0_SFEC_SHIFT) /* Set priority and store in FIFO 1 on match */ -# define STDFILTER_S0_SFEC_BUFFER (7 << STDFILTER_S0_SFEC_SHIFT) /* Store into Rx Buffer or as debug message */ -#define STDFILTER_S0_SFT_SHIFT (30) /* Bits 30-31: Standard Filter Type */ -#define STDFILTER_S0_SFT_MASK (3 << STDFILTER_S0_SFT_SHIFT) -# define STDFILTER_S0_SFT_RANGE (0 << STDFILTER_S0_SFT_SHIFT) /* Range filter from SF1ID to SF2ID */ -# define STDFILTER_S0_SFT_DUAL (1 << STDFILTER_S0_SFT_SHIFT) /* Dual ID filter for SF1ID or SF2ID */ -# define STDFILTER_S0_SFT_CLASSIC (2 << STDFILTER_S0_SFT_SHIFT) /* Classic filter: SF1ID=filter SF2ID=mask */ - -/* Extended Message ID Filter Element */ - -#define EXTFILTER_F0_EFID1_SHIFT (0) /* Bits 0-28: Extended Filter ID 1 */ -#define EXTFILTER_F0_EFID1_MASK (0x1fffffff << EXTFILTER_F0_EFID1_SHIFT) -# define EXTFILTER_F0_EFID1(n) ((uint32_t)(n) << EXTFILTER_F0_EFID1_SHIFT) -#define EXTFILTER_F0_EFEC_SHIFT (29) /* Bits 29-31: Extended Filter Element Configuration */ -#define EXTFILTER_F0_EFEC_MASK (7 << EXTFILTER_F0_EFEC_SHIFT) -# define EXTFILTER_F0_EFEC_DISABLE (0 << EXTFILTER_F0_EFEC_SHIFT) /* Disable filter element */ -# define EXTFILTER_F0_EFEC_FIFO0 (1 << EXTFILTER_F0_EFEC_SHIFT) /* Store in Rx FIFO 0 on match */ -# define EXTFILTER_F0_EFEC_FIFO1 (2 << EXTFILTER_F0_EFEC_SHIFT) /* Store in Rx FIFO 1 on match */ -# define EXTFILTER_F0_EFEC_REJECT (3 << EXTFILTER_F0_EFEC_SHIFT) /* Reject ID on match */ -# define EXTFILTER_F0_EFEC_PRIORITY (4 << EXTFILTER_F0_EFEC_SHIFT) /* Set priority on match */ -# define EXTFILTER_F0_EFEC_PRIOFIFO0 (5 << EXTFILTER_F0_EFEC_SHIFT) /* Set priority and store in FIFO 0 on match */ -# define EXTFILTER_F0_EFEC_PRIOFIFO1 (6 << EXTFILTER_F0_EFEC_SHIFT) /* Set priority and store in FIFO 1 on match */ -# define EXTFILTER_F0_EFEC_BUFFER (7 << EXTFILTER_F0_EFEC_SHIFT) /* Store into Rx Buffer or as debug message */ - -#define EXTFILTER_F1_EFID2_SHIFT (0) /* Bits 0-28: Extended Filter ID 2 */ -#define EXTFILTER_F1_EFID2_MASK (0x1fffffff << EXTFILTER_F1_EFID2_SHIFT) -# define EXTFILTER_F1_EFID2(n) ((uint32_t)(n) << EXTFILTER_F1_EFID2_SHIFT) -#define EXTFILTER_F1_BUFFER_SHIFT (0) /* Bits 0-5: RX buffer start address */ -#define EXTFILTER_F1_BUFFER_MASK (63 << EXTFILTER_F1_BUFFER_SHIFT) -# define EXTFILTER_F1_BUFFER(n) ((uint32_t)(n) << EXTFILTER_F1_BUFFER_SHIFT) -#define EXTFILTER_F1_ACTION_SHIFT (9) /* Bits 9-10: Action taken */ -#define EXTFILTER_F1_ACTION_MASK (3 << EXTFILTER_F1_ACTION_SHIFT) -# define EXTFILTER_F1_RXBUFFER (0 << EXTFILTER_F1_ACTION_SHIFT) /* Store message in a Rx buffer */ -# define EXTFILTER_F1_DEBUGA (1 << EXTFILTER_F1_ACTION_SHIFT) /* Debug Message A */ -# define EXTFILTER_F1_DEBUGB (2 << EXTFILTER_F1_ACTION_SHIFT) /* Debug Message B */ -# define EXTFILTER_F1_DEBUGC (3 << EXTFILTER_F1_ACTION_SHIFT) /* Debug Message C */ -#define EXTFILTER_F1_EFT_SHIFT (30) /* Bits 30-31: Extended Filter Type */ -#define EXTFILTER_F1_EFT_MASK (3 << EXTFILTER_F1_EFT_SHIFT) -# define EXTFILTER_F1_EFT_RANGE (0 << EXTFILTER_F1_EFT_SHIFT) /* Range filter from SF1ID to SF2ID */ -# define EXTFILTER_F1_EFT_DUAL (1 << EXTFILTER_F1_EFT_SHIFT) /* Dual ID filter for SF1ID or SF2ID */ -# define EXTFILTER_F1_EFT_CLASSIC (2 << EXTFILTER_F1_EFT_SHIFT) /* Classic filter: SF1ID=filter SF2ID=mask */ -# define EXTFILTER_F1_EFT_NOXIDAM (3 << EXTFILTER_F1_EFT_SHIFT) /* Range filter from EF1ID to EF2ID, no XIDAM */ - -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_FDCAN_H */ diff --git a/arch/arm/src/stm32/hardware/stm32_flash.h b/arch/arm/src/stm32/hardware/stm32_flash.h deleted file mode 100644 index 2da31815084ed..0000000000000 --- a/arch/arm/src/stm32/hardware/stm32_flash.h +++ /dev/null @@ -1,793 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/hardware/stm32_flash.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_FLASH_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_FLASH_H - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#define _K(x) ((x)*1024) - -#if !defined(CONFIG_STM32_FLASH_CONFIG_DEFAULT) && \ - !defined(CONFIG_STM32_FLASH_CONFIG_4) && \ - !defined(CONFIG_STM32_FLASH_CONFIG_6) && \ - !defined(CONFIG_STM32_FLASH_CONFIG_8) && \ - !defined(CONFIG_STM32_FLASH_CONFIG_B) && \ - !defined(CONFIG_STM32_FLASH_CONFIG_C) && \ - !defined(CONFIG_STM32_FLASH_CONFIG_D) && \ - !defined(CONFIG_STM32_FLASH_CONFIG_E) && \ - !defined(CONFIG_STM32_FLASH_CONFIG_F) && \ - !defined(CONFIG_STM32_FLASH_CONFIG_G) && \ - !defined(CONFIG_STM32_FLASH_CONFIG_I) -# define CONFIG_STM32_FLASH_CONFIG_DEFAULT -#endif - -#if defined(CONFIG_STM32_FLASH_CONFIG_DEFAULT) -# if defined(CONFIG_STM32_STM32L15XX) -# if defined(CONFIG_STM32_HIGHDENSITY) - -/* Different STM32L1xxx MCU version are now called by different 'categories' - * instead of 'densities'. Cat.5 MCU can have up to 512KB of FLASH. - * STM32L1xxx also have data EEPROM, up to 16KB. - */ - -# define STM32_FLASH_NPAGES 2048 -# define STM32_FLASH_PAGESIZE 256 -# else - -/* The STM32 (< Cat.5) L15xx/L16xx can support up to 384KB of FLASH. - * (In reality, most supported L15xx parts have no more than 128KB). - * The program memory block is divided into 96 sectors of 4 Kbytes each, - * and each sector is further split up into 16 pages of 256 bytes each. - * The sector is the write protection granularity. In total, the program - * memory block contains 1536 pages. - */ - -# define STM32_FLASH_NPAGES 1536 -# define STM32_FLASH_PAGESIZE 256 -# endif - -/* Maximum EEPROM size on Cat.5 MCU. TODO: this should be in chip config. */ - -# ifndef STM32_EEPROM_SIZE -# define STM32_EEPROM_SIZE (16 * 1024) -# endif - -# elif defined(CONFIG_STM32_LOWDENSITY) -# define STM32_FLASH_NPAGES 32 -# define STM32_FLASH_PAGESIZE 1024 - -# elif defined(CONFIG_STM32_MEDIUMDENSITY) -# define STM32_FLASH_NPAGES 128 -# define STM32_FLASH_PAGESIZE 1024 - -# elif defined(CONFIG_STM32_CONNECTIVITYLINE) -# define STM32_FLASH_NPAGES 128 -# define STM32_FLASH_PAGESIZE 2048 - -# elif defined(CONFIG_STM32_HIGHDENSITY) -# define STM32_FLASH_NPAGES 256 -# define STM32_FLASH_PAGESIZE 2048 - -# elif defined(CONFIG_STM32_STM32F30XX) -# define STM32_FLASH_NPAGES 128 -# define STM32_FLASH_PAGESIZE 2048 - -# elif defined(CONFIG_STM32_STM32F33XX) -# define STM32_FLASH_NPAGES 32 -# define STM32_FLASH_PAGESIZE 2048 - -# elif defined(CONFIG_STM32_STM32F37XX) -# define STM32_FLASH_NPAGES 128 -# define STM32_FLASH_PAGESIZE 2048 - -# elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) -# define STM32_FLASH_NPAGES 8 -# define STM32_FLASH_SIZE _K((4 * 16) + (1 * 64) + (3 * 128)) -# define STM32_FLASH_SIZES {_K(16), _K(16), _K(16), _K(16), \ - _K(64),_K(128), _K(128), _K(128)} - - /* STM32F4 has mixed page size */ - -# undef STM32_FLASH_PAGESIZE - -# elif defined(CONFIG_STM32_STM32G4XXX) -# define STM32_FLASH_NPAGES 32 -# define STM32_FLASH_PAGESIZE 4096 - -# endif -#endif /* CONFIG_STM32_FLASH_CONFIG_DEFAULT */ - -/* Override of the Flash Has been Chosen */ - -#if !defined(CONFIG_STM32_FLASH_CONFIG_DEFAULT) - -/* Define the Valid Configuration the F2 and F4 */ - -# if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) - -# if defined(CONFIG_STM32_FLASH_CONFIG_B) -# define STM32_FLASH_NPAGES 5 -# define STM32_FLASH_SIZE _K((4 * 16) + (1 * 64)) -# define STM32_FLASH_SIZES {_K(16), _K(16), _K(16), _K(16), \ - _K(64)} - -# elif defined(CONFIG_STM32_FLASH_CONFIG_C) -# define STM32_FLASH_NPAGES 6 -# define STM32_FLASH_SIZE _K((4 * 16) + (1 * 64) + (1 * 128)) -# define STM32_FLASH_SIZES {_K(16), _K(16), _K(16), _K(16), \ - _K(64), _K(128)} - -# elif defined(CONFIG_STM32_FLASH_CONFIG_D) && defined(CONFIG_STM32_STM32F4XXX) -# define STM32_FLASH_NPAGES 7 -# define STM32_FLASH_SIZE _K((4 * 16) + (1 * 64) + (2 * 128)) -# define STM32_FLASH_SIZES {_K(16), _K(16), _K(16), _K(16), \ - _K(64), _K(128), _K(128)} - -# elif defined(CONFIG_STM32_FLASH_CONFIG_E) -# define STM32_FLASH_NPAGES 8 -# define STM32_FLASH_SIZE _K((4 * 16) + (1 * 64) + (3 * 128)) -# define STM32_FLASH_SIZES {_K(16), _K(16), _K(16), _K(16), \ - _K(64), _K(128), _K(128), _K(128)} - -# elif defined(CONFIG_STM32_FLASH_CONFIG_F) && defined(CONFIG_STM32_STM32F20XX) -# define STM32_FLASH_NPAGES 9 -# define STM32_FLASH_SIZE _K((4 * 16) + (1 * 64) + (4 * 128)) -# define STM32_FLASH_SIZES {_K(16), _K(16), _K(16), _K(16), \ - _K(64), _K(128), _K(128), _K(128), \ - _K(128)} - -# elif defined(CONFIG_STM32_FLASH_CONFIG_G) -# define STM32_FLASH_NPAGES 12 -# define STM32_FLASH_SIZE _K((4 * 16) + (1 * 64) + (7 * 128)) -# define STM32_FLASH_SIZES {_K(16), _K(16), _K(16), _K(16), \ - _K(64), _K(128), _K(128), _K(128), \ - _K(128), _K(128), _K(128), _K(128)} - -# elif defined(CONFIG_STM32_FLASH_CONFIG_I) && defined(CONFIG_STM32_STM32F4XXX) -# define STM32_FLASH_NPAGES 24 -# define STM32_FLASH_SIZE _K((4 * 16) + (1 * 64) + (7 * 128)) + \ - _K((4 * 16) + (1 * 64) + (7 * 128)) -# define STM32_FLASH_SIZES {_K(16), _K(16), _K(16), _K(16), \ - _K(64), _K(128), _K(128), _K(128), \ - _K(128), _K(128), _K(128), _K(128), \ - _K(16), _K(16), _K(16), _K(16), \ - _K(64), _K(128), _K(128), _K(128), \ - _K(128), _K(128), _K(128), _K(128)} -# endif - -/* Define the Valid Configuration the G4 */ - -# elif defined(CONFIG_STM32_STM32G4XXX) -# if defined(CONFIG_STM32_STM32G43XX) -# if defined(CONFIG_STM32_FLASH_CONFIG_6) -# define STM32_FLASH_NPAGES 16 -# define STM32_FLASH_PAGESIZE 2048 - -# elif defined(CONFIG_STM32_FLASH_CONFIG_8) -# define STM32_FLASH_NPAGES 32 -# define STM32_FLASH_PAGESIZE 2048 - -# elif defined(CONFIG_STM32_FLASH_CONFIG_B) -# define STM32_FLASH_NPAGES 64 -# define STM32_FLASH_PAGESIZE 2048 -# endif -# elif defined(CONFIG_STM32_STM32G47XX) || defined(CONFIG_STM32_STM32G48XX) -# if defined(CONFIG_STM32_FLASH_CONFIG_B) -# define STM32_FLASH_SIZE 32 * 4096 - -# elif defined(CONFIG_STM32_FLASH_CONFIG_C) -# define STM32_FLASH_SIZE 64 * 4096 - -# elif defined(CONFIG_STM32_FLASH_CONFIG_E) -# define STM32_FLASH_SIZE 128 * 4096 -# endif -# elif defined(CONFIG_STM32_STM32G49XX) -# elif defined(CONFIG_STM32_FLASH_CONFIG_C) -# define STM32_FLASH_NPAGES 128 -# define STM32_FLASH_PAGESIZE 2048 - -# elif defined(CONFIG_STM32_FLASH_CONFIG_E) -# define STM32_FLASH_NPAGES 256 -# define STM32_FLASH_PAGESIZE 2048 -# endif - -/* Define the Valid Configuration the F1 and F3 */ - -# else -# if defined(CONFIG_STM32_FLASH_CONFIG_4) -# define STM32_FLASH_NPAGES 16 -# define STM32_FLASH_PAGESIZE 1024 -# elif defined(CONFIG_STM32_FLASH_CONFIG_6) -# define STM32_FLASH_NPAGES 32 -# define STM32_FLASH_PAGESIZE 1024 -# elif defined(CONFIG_STM32_FLASH_CONFIG_8) -# define STM32_FLASH_NPAGES 64 -# define STM32_FLASH_PAGESIZE 1024 -# elif defined(CONFIG_STM32_FLASH_CONFIG_B) -# define STM32_FLASH_NPAGES 128 -# define STM32_FLASH_PAGESIZE 1024 -# elif defined(CONFIG_STM32_FLASH_CONFIG_C) -# define STM32_FLASH_NPAGES 128 -# define STM32_FLASH_PAGESIZE 2048 -# elif defined(CONFIG_STM32_FLASH_CONFIG_D) -# define STM32_FLASH_NPAGES 192 -# define STM32_FLASH_PAGESIZE 2048 -# elif defined(CONFIG_STM32_FLASH_CONFIG_E) -# define STM32_FLASH_NPAGES 256 -# define STM32_FLASH_PAGESIZE 2048 -# elif defined(CONFIG_STM32_FLASH_CONFIG_F) -# define STM32_FLASH_NPAGES 384 -# define STM32_FLASH_PAGESIZE 2048 -# elif defined(CONFIG_STM32_FLASH_CONFIG_G) -# define STM32_FLASH_NPAGES 512 -# define STM32_FLASH_PAGESIZE 2048 -# elif defined(CONFIG_STM32_FLASH_CONFIG_I) -# endif -# endif -#endif /* !defined(CONFIG_STM32_FLASH_CONFIG_DEFAULT) */ - -#ifdef STM32_FLASH_PAGESIZE -# define STM32_FLASH_SIZE (STM32_FLASH_NPAGES * STM32_FLASH_PAGESIZE) -#endif - -/* STM32F101 and STM32F103 with flash size > 512kB are dual-bank devices. - * where bank 0 contains pages 0..255 and bank 1 contains the rest. - */ - -#if defined(CONFIG_STM32_STM32F10XX) && (STM32_FLASH_NPAGES > 256) -# define STM32_FLASH_DUAL_BANK 1 -# define STM32_FLASH_BANK0_NPAGES 256 -# define STM32_FLASH_BANK1_NPAGES (STM32_FLASH_NPAGES - STM32_FLASH_BANK0_NPAGES) -# define STM32_FLASH_BANK0_BASE (STM32_FLASH_BASE) -# define STM32_FLASH_BANK1_BASE \ - (STM32_FLASH_BASE + STM32_FLASH_PAGESIZE * STM32_FLASH_BANK0_NPAGES) -#endif - -/* Register Offsets *********************************************************/ - -#define STM32_FLASH_ACR_OFFSET 0x0000 -#if defined(CONFIG_STM32_STM32L15XX) -# define STM32_FLASH_PECR_OFFSET 0x0004 -# define STM32_FLASH_PDKEYR_OFFSET 0x0008 -# define STM32_FLASH_PEKEYR_OFFSET 0x000c -# define STM32_FLASH_PRGKEYR_OFFSET 0x0010 -# define STM32_FLASH_OPTKEYR_OFFSET 0x0014 -# define STM32_FLASH_SR_OFFSET 0x0018 -# define STM32_FLASH_OBR_OFFSET 0x001c -# define STM32_FLASH_WRPR1_OFFSET 0x0020 -# define STM32_FLASH_WRPR2_OFFSET 0x0080 -# define STM32_FLASH_WRPR3_OFFSET 0x0084 -# define STM32_FLASH_WRPR4_OFFSET 0x0088 -#elif defined(CONFIG_STM32_STM32G4XXX) -# define STM32_FLASH_PDKEYR_OFFSET 0x0004 -# define STM32_FLASH_KEYR_OFFSET 0x0008 -# define STM32_FLASH_OPTKEYR_OFFSET 0x000c -# define STM32_FLASH_SR_OFFSET 0x0010 -# define STM32_FLASH_CR_OFFSET 0x0014 -# define STM32_FLASH_ECCR_OFFSET 0x0018 -# define STM32_FLASH_OPTR_OFFSET 0x0020 -# define STM32_FLASH_PCROP1SR_OFFSET 0x0024 -# define STM32_FLASH_PCROP1ER_OFFSET 0x0028 -# define STM32_FLASH_WRP1AR_OFFSET 0x002c -# define STM32_FLASH_WRP1BR_OFFSET 0x0030 -# define STM32_FLASH_PCROP2SR_OFFSET 0x0044 -# define STM32_FLASH_PCROP2ER_OFFSET 0x0048 -# define STM32_FLASH_WRP2AR_OFFSET 0x004c -# define STM32_FLASH_WRP2BR_OFFSET 0x0050 -# define STM32_FLASH_SEC1R_OFFSET 0x0070 -# define STM32_FLASH_SEC2R_OFFSET 0x0074 -#else -# define STM32_FLASH_KEYR_OFFSET 0x0004 -# define STM32_FLASH_OPTKEYR_OFFSET 0x0008 -# define STM32_FLASH_SR_OFFSET 0x000c -# define STM32_FLASH_CR_OFFSET 0x0010 -# if defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F30XX) || \ - defined(CONFIG_STM32_STM32F33XX) || defined(CONFIG_STM32_STM32F37XX) -# define STM32_FLASH_AR_OFFSET 0x0014 -# define STM32_FLASH_OBR_OFFSET 0x001c -# define STM32_FLASH_WRPR_OFFSET 0x0020 -# elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) -# define STM32_FLASH_OPTCR_OFFSET 0x0014 -# endif -#endif - -#if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429) || \ - defined(CONFIG_STM32_STM32F469) -# define STM32_FLASH_OPTCR1_OFFSET 0x0018 -#endif - -#if defined(CONFIG_STM32_STM32F10XX) && defined(STM32_FLASH_DUAL_BANK) -# define STM32_FLASH_BANK0_REGS_OFFSET 0 -# define STM32_FLASH_BANK1_REGS_OFFSET 0x40 - -# define STM32_FLASH_KEYR1_OFFSET 0x0044 -# define STM32_FLASH_SR1_OFFSET 0x004c -# define STM32_FLASH_CR1_OFFSET 0x0050 -# define STM32_FLASH_AR2_OFFSET 0x0054 -#endif - -/* Register Addresses *******************************************************/ - -#define STM32_FLASH_ACR (STM32_FLASHIF_BASE+STM32_FLASH_ACR_OFFSET) -#if defined(CONFIG_STM32_STM32L15XX) -# define STM32_FLASH_PECR (STM32_FLASHIF_BASE+STM32_FLASH_PECR_OFFSET) -# define STM32_FLASH_PDKEYR (STM32_FLASHIF_BASE+STM32_FLASH_PDKEYR_OFFSET) -# define STM32_FLASH_PEKEYR (STM32_FLASHIF_BASE+STM32_FLASH_PEKEYR_OFFSET) -# define STM32_FLASH_PRGKEYR (STM32_FLASHIF_BASE+STM32_FLASH_PRGKEYR_OFFSET) -# define STM32_FLASH_OPTKEYR (STM32_FLASHIF_BASE+STM32_FLASH_OPTKEYR_OFFSET) -# define STM32_FLASH_SR (STM32_FLASHIF_BASE+STM32_FLASH_SR_OFFSET) -# define STM32_FLASH_OBR (STM32_FLASHIF_BASE+STM32_FLASH_OBR_OFFSET) -# define STM32_FLASH_WRPR1 (STM32_FLASHIF_BASE+STM32_FLASH_WRPR1_OFFSET) -# define STM32_FLASH_WRPR2 (STM32_FLASHIF_BASE+STM32_FLASH_WRPR2_OFFSET) -# define STM32_FLASH_WRPR3 (STM32_FLASHIF_BASE+STM32_FLASH_WRPR3_OFFSET) -# define STM32_FLASH_WRPR4 (STM32_FLASHIF_BASE+STM32_FLASH_WRPR4_OFFSET) -#elif defined(CONFIG_STM32_STM32G4XXX) -# define STM32_FLASH_PDKEYR (STM32_FLASHIF_BASE+STM32_FLASH_PDKEYR_OFFSET) -# define STM32_FLASH_KEYR (STM32_FLASHIF_BASE+STM32_FLASH_KEYR_OFFSET) -# define STM32_FLASH_OPTKEYR (STM32_FLASHIF_BASE+STM32_FLASH_OPTKEYR_OFFSET) -# define STM32_FLASH_SR (STM32_FLASHIF_BASE+STM32_FLASH_SR_OFFSET) -# define STM32_FLASH_CR (STM32_FLASHIF_BASE+STM32_FLASH_CR_OFFSET) -# define STM32_FLASH_ECCR (STM32_FLASHIF_BASE+STM32_FLASH_ECCR_OFFSET) -# define STM32_FLASH_OPTR (STM32_FLASHIF_BASE+STM32_FLASH_OPTR_OFFSET) -# define STM32_FLASH_PCROP1SR (STM32_FLASHIF_BASE+STM32_FLASH_PCROP1SR_OFFSET) -# define STM32_FLASH_PCROP1ER (STM32_FLASHIF_BASE+STM32_FLASH_PCROP1ER_OFFSET) -# define STM32_FLASH_WRP1AR (STM32_FLASHIF_BASE+STM32_FLASH_WRP1AR_OFFSET) -# define STM32_FLASH_WRP1BR (STM32_FLASHIF_BASE+STM32_FLASH_WRP1BR_OFFSET) -# define STM32_FLASH_PCROP2SR (STM32_FLASHIF_BASE+STM32_FLASH_PCROP2SR_OFFSET) -# define STM32_FLASH_PCROP2ER (STM32_FLASHIF_BASE+STM32_FLASH_PCROP2ER_OFFSET) -# define STM32_FLASH_WRP2AR (STM32_FLASHIF_BASE+STM32_FLASH_WRP2AR_OFFSET) -# define STM32_FLASH_WRP2BR (STM32_FLASHIF_BASE+STM32_FLASH_WRP2BR_OFFSET) -# define STM32_FLASH_SEC1R (STM32_FLASHIF_BASE+STM32_FLASH_SEC1R_OFFSET) -# define STM32_FLASH_SEC2R (STM32_FLASHIF_BASE+STM32_FLASH_SEC2R_OFFSET) -#else -# define STM32_FLASH_KEYR (STM32_FLASHIF_BASE+STM32_FLASH_KEYR_OFFSET) -# define STM32_FLASH_OPTKEYR (STM32_FLASHIF_BASE+STM32_FLASH_OPTKEYR_OFFSET) -# define STM32_FLASH_SR (STM32_FLASHIF_BASE+STM32_FLASH_SR_OFFSET) -# define STM32_FLASH_CR (STM32_FLASHIF_BASE+STM32_FLASH_CR_OFFSET) - -# if defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F30XX) || \ - defined(CONFIG_STM32_STM32F33XX) || defined(CONFIG_STM32_STM32F37XX) -# define STM32_FLASH_AR (STM32_FLASHIF_BASE+STM32_FLASH_AR_OFFSET) -# define STM32_FLASH_OBR (STM32_FLASHIF_BASE+STM32_FLASH_OBR_OFFSET) -# define STM32_FLASH_WRPR (STM32_FLASHIF_BASE+STM32_FLASH_WRPR_OFFSET) -# elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) -# define STM32_FLASH_OPTCR (STM32_FLASHIF_BASE+STM32_FLASH_OPTCR_OFFSET) -# endif -# if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429) || \ - defined(CONFIG_STM32_STM32F469) -# define STM32_FLASH_OPTCR1 (STM32_FLASHIF_BASE+STM32_FLASH_OPTCR1_OFFSET) -# endif -#endif - -#if defined(CONFIG_STM32_STM32F10XX) && defined(STM32_FLASH_DUAL_BANK) -# define STM32_FLASH_KEYR1 (STM32_FLASHIF_BASE+STM32_FLASH_KEYR1_OFFSET) -# define STM32_FLASH_SR1 (STM32_FLASHIF_BASE+STM32_FLASH_SR1_OFFSET) -# define STM32_FLASH_CR1 (STM32_FLASHIF_BASE+STM32_FLASH_CR1_OFFSET) -# define STM32_FLASH_AR2 (STM32_FLASHIF_BASE+STM32_FLASH_AR1_OFFSET) -#endif - -/* Register Bitfield Definitions ********************************************/ - -/* Flash Access Control Register (ACR) */ - -#if defined(CONFIG_STM32_STM32L15XX) -# define FLASH_ACR_LATENCY (1 << 0) /* Bit 0: Latency */ -# define FLASH_ACR_PRFTEN (1 << 1) /* Bit 1: Prefetch enable */ -# define FLASH_ACR_ACC64 (1 << 2) /* Bit 2: 64-bit access */ -# define FLASH_ACR_SLEEP_PD (1 << 3) /* Bit 3: Flash mode during Sleep */ -# define FLASH_ACR_RUN_PD (1 << 4) /* Bit 4: Flash mode during Run */ -#elif defined(CONFIG_STM32_STM32G4XXX) -# define FLASH_ACR_LATENCY_SHIFT (0) -# define FLASH_ACR_LATENCY_MASK (0xf << FLASH_ACR_LATENCY_SHIFT) -# define FLASH_ACR_LATENCY(n) ((n) << FLASH_ACR_LATENCY_SHIFT) /* n wait states = 0..15 */ -# define FLASH_ACR_LATENCY_0 (0 << FLASH_ACR_LATENCY_SHIFT) /* 0000: Zero wait states */ -# define FLASH_ACR_LATENCY_1 (1 << FLASH_ACR_LATENCY_SHIFT) /* 0001: One wait state */ -# define FLASH_ACR_LATENCY_2 (2 << FLASH_ACR_LATENCY_SHIFT) /* 0010: Two wait states */ -# define FLASH_ACR_LATENCY_3 (3 << FLASH_ACR_LATENCY_SHIFT) /* 0011: Three wait states */ -# define FLASH_ACR_LATENCY_4 (4 << FLASH_ACR_LATENCY_SHIFT) /* 0100: Four wait states */ -# define FLASH_ACR_LATENCY_5 (5 << FLASH_ACR_LATENCY_SHIFT) /* 0101: Five wait states */ -# define FLASH_ACR_LATENCY_6 (6 << FLASH_ACR_LATENCY_SHIFT) /* 0110: Six wait states */ -# define FLASH_ACR_LATENCY_7 (7 << FLASH_ACR_LATENCY_SHIFT) /* 0111: Seven wait states */ -# define FLASH_ACR_LATENCY_8 (8 << FLASH_ACR_LATENCY_SHIFT) /* 1000: Eight wait states */ -# define FLASH_ACR_LATENCY_9 (9 << FLASH_ACR_LATENCY_SHIFT) /* 1001: Nine wait state */ -# define FLASH_ACR_LATENCY_10 (10 << FLASH_ACR_LATENCY_SHIFT) /* 1010: Ten wait states */ -# define FLASH_ACR_LATENCY_11 (11 << FLASH_ACR_LATENCY_SHIFT) /* 1011: Eleven wait states */ -# define FLASH_ACR_LATENCY_12 (12 << FLASH_ACR_LATENCY_SHIFT) /* 1100: Twelve wait states */ -# define FLASH_ACR_LATENCY_13 (13 << FLASH_ACR_LATENCY_SHIFT) /* 1101: Thirteen wait states */ -# define FLASH_ACR_LATENCY_14 (14 << FLASH_ACR_LATENCY_SHIFT) /* 1110: Fourteen wait states */ -# define FLASH_ACR_LATENCY_15 (15 << FLASH_ACR_LATENCY_SHIFT) /* 1111: Fifteen wait states */ -# define FLASH_ACR_PRFTEN (1 << 8) /* Bit 8: FLASH prefetch enable */ -# define FLASH_ACR_ICEN (1 << 9) /* Bit 9: Instruction cache enable */ -# define FLASH_ACR_DCEN (1 << 10) /* Bit 10: Data cache enable */ -# define FLASH_ACR_ICRST (1 << 11) /* Bit 11: Instruction cache reset */ -# define FLASH_ACR_DCRST (1 << 12) /* Bit 12: Data cache reset */ -# define FLASH_ACR_RUNPD (1 << 13) /* Bit 13: Flash Power Down Mode During Run or Low Power Run */ -# define FLASH_ACR_SLEEPPD (1 << 14) /* Bit 14: Flash Power Down Mode During Sleep or Low Power Sleep */ -# define FLASH_ACR_DBG_SWEN (1 << 18) /* Bit 18: Debug Software Enable */ -#else -# define FLASH_ACR_LATENCY_SHIFT (0) -# define FLASH_ACR_LATENCY_MASK (7 << FLASH_ACR_LATENCY_SHIFT) -# define FLASH_ACR_LATENCY(n) ((n) << FLASH_ACR_LATENCY_SHIFT) /* n wait states */ -# define FLASH_ACR_LATENCY_0 (0 << FLASH_ACR_LATENCY_SHIFT) /* 000: Zero wait states */ -# define FLASH_ACR_LATENCY_1 (1 << FLASH_ACR_LATENCY_SHIFT) /* 001: One wait state */ -# define FLASH_ACR_LATENCY_2 (2 << FLASH_ACR_LATENCY_SHIFT) /* 010: Two wait states */ -# define FLASH_ACR_LATENCY_3 (3 << FLASH_ACR_LATENCY_SHIFT) /* 011: Three wait states */ -# define FLASH_ACR_LATENCY_4 (4 << FLASH_ACR_LATENCY_SHIFT) /* 100: Four wait states */ -# define FLASH_ACR_LATENCY_5 (5 << FLASH_ACR_LATENCY_SHIFT) /* 101: Five wait states */ -# define FLASH_ACR_LATENCY_6 (6 << FLASH_ACR_LATENCY_SHIFT) /* 110: Six wait states */ -# define FLASH_ACR_LATENCY_7 (7 << FLASH_ACR_LATENCY_SHIFT) /* 111: Seven wait states */ - -# if defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F30XX) || \ - defined(CONFIG_STM32_STM32F33XX) || defined(CONFIG_STM32_STM32F37XX) -# define FLASH_ACR_HLFCYA (1 << 3) /* Bit 3: FLASH half cycle access */ -# define FLASH_ACR_PRTFBE (1 << 4) /* Bit 4: FLASH prefetch enable */ -# if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) || \ - defined(CONFIG_STM32_STM32F37XX) -# define FLASH_ACR_PRFTBS (1 << 5) /* Bit 5: FLASH prefetch buffer status */ -# endif -# elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) -# define FLASH_ACR_PRFTEN (1 << 8) /* FLASH prefetch enable */ -# define FLASH_ACR_ICEN (1 << 9) /* Bit 9: Instruction cache enable */ -# define FLASH_ACR_DCEN (1 << 10) /* Bit 10: Data cache enable */ -# define FLASH_ACR_ICRST (1 << 11) /* Bit 11: Instruction cache reset */ -# define FLASH_ACR_DCRST (1 << 12) /* Bit 12: Data cache reset */ -# endif -#endif - -/* Flash Status Register (SR) */ - -#if defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F30XX) || \ - defined(CONFIG_STM32_STM32F33XX) || defined(CONFIG_STM32_STM32F37XX) -# define FLASH_SR_BSY (1 << 0) /* Busy */ -# define FLASH_SR_PGERR (1 << 2) /* Programming Error */ -# define FLASH_SR_WRPRT_ERR (1 << 4) /* Write Protection Error */ -# define FLASH_SR_EOP (1 << 5) /* End of Operation */ -#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) -# define FLASH_SR_EOP (1 << 0) /* Bit 0: End of operation */ -# define FLASH_SR_OPERR (1 << 1) /* Bit 1: Operation error */ -# define FLASH_SR_WRPERR (1 << 4) /* Bit 4: Write protection error */ -# define FLASH_SR_PGAERR (1 << 5) /* Bit 5: Programming alignment error */ -# define FLASH_SR_PGPERR (1 << 6) /* Bit 6: Programming parallelism error */ -# define FLASH_SR_PGSERR (1 << 7) /* Bit 7: Programming sequence error */ -# define FLASH_SR_BSY (1 << 16) /* Bit 16: Busy */ -#elif defined(CONFIG_STM32_STM32L15XX) -# define FLASH_SR_BSY (1 << 0) /* Bit 0: Busy */ -# define FLASH_SR_EOP (1 << 1) /* Bit 1: End of operation */ -# define FLASH_SR_ENDHV (1 << 2) /* Bit 2: End of high voltage */ -# define FLASH_SR_READY (1 << 3) /* Bit 3: Flash memory module ready after low power mode */ -# define FLASH_SR_WRPERR (1 << 8) /* Bit 8: Write protection error */ -# define FLASH_SR_PGAERR (1 << 9) /* Bit 9: Programming alignment error */ -# define FLASH_SR_SIZERR (1 << 10) /* Bit 10: Size error */ -# define FLASH_SR_OPTVERR (1 << 11) /* Bit 11: Option validity error */ -# define FLASH_SR_OPTVERRUSR (1 << 12) /* Bit 12: Option UserValidity Error */ -# define FLASH_SR_RDERR (1 << 13) /* Bit 13: Read protected error */ -#elif defined(CONFIG_STM32_STM32G4XXX) -# define FLASH_SR_EOP (1 << 0) /* Bit 0: End of operation */ -# define FLASH_SR_OPERR (1 << 1) /* Bit 1: Operation error */ -# define FLASH_SR_PROGERR (1 << 3) /* Bit 3: Programming error */ -# define FLASH_SR_WRPERR (1 << 4) /* Bit 4: Write protection error */ -# define FLASH_SR_PGAERR (1 << 5) /* Bit 5: Programming alignment error */ -# define FLASH_SR_SIZERR (1 << 6) /* Bit 6: Size error */ -# define FLASH_SR_PGSERR (1 << 7) /* Bit 7: Programming sequence error */ -# define FLASH_SR_MISERR (1 << 8) /* Bit 8: Fast programming data miss error */ -# define FLASH_SR_FASTERR (1 << 9) /* Bit 9: Fast programming error */ -# define FLASH_SR_RDERR (1 << 14) /* Bit 14: PCROP read error */ -# define FLASH_SR_OPTVERR (1 << 15) /* Bit 15: Option validity error */ -# define FLASH_SR_BSY (1 << 16) /* Bit 16: Busy */ -#endif - -/* Program/Erase Control Register (PECR) */ - -#if defined(CONFIG_STM32_STM32L15XX) -# define FLASH_PECR_PELOCK (1 << 0) /* Bit 0: PECR and data EEPROM lock */ -# define FLASH_PECR_PRGLOCK (1 << 1) /* Bit 1: Program memory lock */ -# define FLASH_PECR_OPTLOCK (1 << 2) /* Bit 2: Option bytes block lock */ -# define FLASH_PECR_PROG (1 << 3) /* Bit 3: Program memory selection */ -# define FLASH_PECR_DATA (1 << 4) /* Bit 4: Data EEPROM selection */ -# define FLASH_PECR_FTDW (1 << 8) /* Bit 8: Fixed time data write for Byte, Half Word and Word programming */ -# define FLASH_PECR_ERASE (1 << 9) /* Bit 9: Page or Double Word erase mode */ -# define FLASH_PECR_FPRG (1 << 10) /* Bit 10: Half Page/Double Word programming mode */ -# define FLASH_PECR_PARALLBANK (1 << 15) /* Bit 15: Parallel bank mode */ -# define FLASH_PECR_EOPIE (1 << 16) /* Bit 16: End of programming interrupt enable */ -# define FLASH_PECR_ERRIE (1 << 17) /* Bit 17: Error interrupt enable */ -# define FLASH_PECR_OBL_LAUNCH (1 << 18) /* Bit 18: Launch the option byte loading */ -#endif - -/* Flash Control Register (CR) */ - -#if defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F30XX) || \ - defined(CONFIG_STM32_STM32F33XX) || defined(CONFIG_STM32_STM32F37XX) -# define FLASH_CR_PG (1 << 0) /* Bit 0: Program Page */ -# define FLASH_CR_PER (1 << 1) /* Bit 1: Page Erase */ -# define FLASH_CR_MER (1 << 2) /* Bit 2: Mass Erase */ -# define FLASH_CR_OPTPG (1 << 4) /* Bit 4: Option Byte Programming */ -# define FLASH_CR_OPTER (1 << 5) /* Bit 5: Option Byte Erase */ -# define FLASH_CR_STRT (1 << 6) /* Bit 6: Start Erase */ -# define FLASH_CR_LOCK (1 << 7) /* Bit 7: Page Locked or Lock Page */ -# define FLASH_CR_OPTWRE (1 << 9) /* Bit 8: Option Bytes Write Enable */ -# define FLASH_CR_ERRIE (1 << 10) /* Bit 10: Error Interrupt Enable */ -# define FLASH_CR_EOPIE (1 << 12) /* Bit 12: End of Program Interrupt Enable */ -# if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) || \ - defined(CONFIG_STM32_STM32F37XX) -# define FLASH_CR_OBL_LAUNCH (1 << 13) /* Bit 13: Force option byte loading */ -# endif -#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) -# define FLASH_CR_PG (1 << 0) /* Bit 0: Programming */ -# define FLASH_CR_SER (1 << 1) /* Bit 1: Sector Erase */ -# define FLASH_CR_MER (1 << 2) /* Bit 2: Mass Erase sectors 0..11 */ -# define FLASH_CR_SNB_SHIFT (3) /* Bits 3-6: Sector number */ -# if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429) -# define FLASH_CR_SNB_MASK (31 << FLASH_CR_SNB_SHIFT) -# define FLASH_CR_SNB(n) (((n % 12) << FLASH_CR_SNB_SHIFT) | ((n / 12) << 7)) /* Sector n, n=0..23 */ -# else -# define FLASH_CR_SNB_MASK (15 << FLASH_CR_SNB_SHIFT) -# define FLASH_CR_SNB(n) ((n) << FLASH_CR_SNB_SHIFT) /* Sector n, n=0..11 */ -# endif -# define FLASH_CR_PSIZE_SHIFT (8) /* Bits 8-9: Program size */ -# define FLASH_CR_PSIZE_MASK (3 << FLASH_CR_PSIZE_SHIFT) -# define FLASH_CR_PSIZE_X8 (0 << FLASH_CR_PSIZE_SHIFT) /* 00 program x8 */ -# define FLASH_CR_PSIZE_X16 (1 << FLASH_CR_PSIZE_SHIFT) /* 01 program x16 */ -# define FLASH_CR_PSIZE_X32 (2 << FLASH_CR_PSIZE_SHIFT) /* 10 program x32 */ -# define FLASH_CR_PSIZE_X64 (3 << FLASH_CR_PSIZE_SHIFT) /* 11 program x64 */ -# define FLASH_CR_STRT (1 << 16) /* Bit 16: Start Erase */ -# define FLASH_CR_EOPIE (1 << 24) /* Bit 24: End of operation interrupt enable */ -# define FLASH_CR_ERRIE (1 << 25) /* Bit 25: Error interrupt enable */ -# define FLASH_CR_LOCK (1 << 31) /* Bit 31: Lock */ -#elif defined(CONFIG_STM32_STM32G4XXX) -# define FLASH_CR_PG (1 << 0) -# define FLASH_CR_PER (1 << 1) -# define FLASH_CR_MER1 (1 << 2) -# define FLASH_CR_PNB_SHIFT (3) -# if defined(CONFIG_STM32_STM32G43XX) -# define FLASH_CR_PNB_MASK (0x3f << FLASH_CR_PNB_SHIFT) -# elif defined(CONFIG_STM32_STM32G47XX) || defined (CONFIG_STM32_STM32G48XX) -# define FLASH_CR_PNB_MASK (0x7f << FLASH_CR_PNB_SHIFT) -# elif defined(CONFIG_STM32_STM32G49XX) -# define FLASH_CR_PNB_MASK (0xff << FLASH_CR_PNB_SHIFT) -# endif -# define FLASH_CR_PNB(n) (((n) << FLASH_CR_PNB_SHIFT) & FLASH_CR_PNB_MASK) -# if defined(CONFIG_STM32_STM32G47XX) || defined (CONFIG_STM32_STM32G48XX) -# define FLASH_CR_BKER (1 << 11) -# define FLASH_CR_MER2 (1 << 15) -# endif -# define FLASH_CR_START (1 << 16) -# define FLASH_CR_OPTSTRT (1 << 17) -# define FLASH_CR_FSTPG (1 << 18) -# define FLASH_CR_EOPIE (1 << 24) -# define FLASH_CR_ERRIE (1 << 25) -# define FLASH_CR_RDERRIE (1 << 26) -# define FLASH_CR_OBL_LAUNCH (1 << 27) -# define FLASH_CR_SEC_PROT1 (1 << 28) -# if defined(CONFIG_STM32_STM32G47XX) || defined (CONFIG_STM32_STM32G48XX) -# define FLASH_CR_SEC_PROT2 (1 << 29) -# endif -# define FLASH_CR_OPTLOCK (1 << 30) -# define FLASH_CR_LOCK (1 << 31) -#endif -#if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429) -# define FLASH_CR_MER1 (1 << 15) /* Bit 15: Mass Erase sectors 12..23 */ -#endif - -/* Flash ECC register (ECCR) */ - -#if defined(CONFIG_STM32_STM32G4XXX) -# define FLASH_ECCR_ADDR_ECC_SHIFT (0) -# define FLASH_ECCR_ADDR_ECC_MASK (0x7ffff << FLASH_ECCR_ADDR_ECC_SHIFT) -# define FLASH_ECCR_ADDR_ECC(n) (((n) << FLASH_ECCR_ADDR_ECC_SHIFT) & FLASH_ECCR_ADDR_ECC_MASK) - -# define FLASH_ECCR_BK_ECC (1 << 21) -# define FLASH_ECCR_SYSF_ECC (1 << 22) -# define FLASH_ECCR_ECCIE (1 << 24) -# if defined(CONFIG_STM32_STM32G47XX) || defined (CONFIG_STM32_STM32G48XX) -# define FLASH_ECCR_ECCC2 (1 << 28) -# define FLASH_ECCR_ECCD2 (1 << 29) -# endif -# define FLASH_ECCR_ECCC (1 << 30) -# define FLASH_ECCR_ECCD (1 << 31) -#endif - -/* Flash Option Control Register (OPTCR) */ - -#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) -# define FLASH_OPTCR_OPTLOCK (1 << 0) /* Bit 0: Option lock */ -# define FLASH_OPTCR_OPTSTRT (1 << 1) /* Bit 1: Option start */ -# define FLASH_OPTCR_BORLEV_SHIFT (2) /* Bits 2-3: BOR reset Level */ -# define FLASH_OPTCR_BORLEV_MASK (3 << FLASH_OPTCR_BORLEV_SHIFT) -# define FLASH_OPTCR_VBOR3 (0 << FLASH_OPTCR_BORLEV_SHIFT) /* 00: BOR Level 3 */ -# define FLASH_OPTCR_VBOR2 (1 << FLASH_OPTCR_BORLEV_SHIFT) /* 01: BOR Level 2 */ -# define FLASH_OPTCR_VBOR1 (2 << FLASH_OPTCR_BORLEV_SHIFT) /* 10: BOR Level 1 */ -# define FLASH_OPTCR_VBOR0 (3 << FLASH_OPTCR_BORLEV_SHIFT) /* 11: BOR off */ -# define FLASH_OPTCR_USER_SHIFT (5) /* Bits 5-7: User option bytes */ -# define FLASH_OPTCR_USER_MASK (7 << FLASH_OPTCR_USER_SHIFT) -# define FLASH_OPTCR_NRST_STDBY (1 << 7) /* Bit 7: nRST_STDBY */ -# define FLASH_OPTCR_NRST_STOP (1 << 6) /* Bit 6: nRST_STOP */ -# define FLASH_OPTCR_WDG_SW (1 << 5) /* Bit 5: WDG_SW */ -# define FLASH_OPTCR_RDP_SHIFT (8) /* Bits 8-15: Read protect */ -# define FLASH_OPTCR_RDP_MASK (0xff << FLASH_OPTCR_RDP_SHIFT) -# define FLASH_OPTCR_RDP(n) ((uint32_t)(n) << FLASH_OPTCR_RDP_SHIFT) -# define FLASH_OPTCR_NWRP_SHIFT (16) /* Bits 16-27: Not write protect */ -# define FLASH_OPTCR_NWRP_MASK (0xfff << FLASH_OPTCR_NWRP_SHIFT) -#endif - -/* Flash Option Control Register (OPTCR1) */ - -#if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429) -# define FLASH_OPTCR1_NWRP_SHIFT (16) /* Bits 16-27: Not write protect (high bank) */ -# define FLASH_OPTCR1_NWRP_MASK (0xfff << FLASH_OPTCR_NWRP_SHIFT) - -# define FLASH_OPTCR1_BFB2_SHIFT (4) /* Bits 4: Dual-bank Boot option byte */ -# define FLASH_OPTCR1_BFB2_MASK (1 << FLASH_OPTCR_NWRP_SHIFT) -#endif - -#if defined(CONFIG_STM32_STM32F446) -# define FLASH_OPTCR1_NWRP_SHIFT (16) /* Bits 16-23: Not write protect (high bank) */ -# define FLASH_OPTCR1_NWRP_MASK (0xff << FLASH_OPTCR_NWRP_SHIFT) -#endif - -/* Flash option register (OPTR) */ - -#if defined(CONFIG_STM32_STM32G4XXX) -# define FLASH_OPTR_RDP_SHIFT (0) -# define FLASH_OPTR_RDP_MASK (0xff << FLASH_OPTR_RDP_SHIFT) -# define FLASH_OPTR_RDP (((n) << FLASH_OPTR_RDP_SHIFT) & FLASH_OPTR_RDP_MASK) -# define FLASH_OPTR_BOR_LEV_SHIFT (8) -# define FLASH_OPTR_BOR_LEV_MASK (0x7 << FLASH_OPTR_BOR_LEV_SHIFT) -# define FLASH_OPTR_BOR_LEV_1_7V (0x0 << FLASH_OPTR_BOR_LEV_SHIFT) -# define FLASH_OPTR_BOR_LEV_2_0V (0x1 << FLASH_OPTR_BOR_LEV_SHIFT) -# define FLASH_OPTR_BOR_LEV_2_2V (0x2 << FLASH_OPTR_BOR_LEV_SHIFT) -# define FLASH_OPTR_BOR_LEV_2_5V (0x3 << FLASH_OPTR_BOR_LEV_SHIFT) -# define FLASH_OPTR_BOR_LEV_2_8V (0x4 << FLASH_OPTR_BOR_LEV_SHIFT) -# define FLASH_OPTR_NRST_STOP (1 << 12) -# define FLASH_OPTR_NRST_STDBY (1 << 13) -# define FLASH_OPTR_NRST_SHDW (1 << 14) -# define FLASH_OPTR_IWDG_SW (1 << 16) -# define FLASH_OPTR_IWDG_STOP (1 << 17) -# define FLASH_OPTR_IWDG_STDBY (1 << 18) -# define FLASH_OPTR_WWDG_SW (1 << 19) -# define FLASH_OPTR_BFB2 (1 << 20) -# if defined(CONFIG_STM32_STM32G47XX) || defined (CONFIG_STM32_STM32G48XX) -# define FLASH_OPTR_DBANK (1 << 22) -# elif defined (CONFIG_STM32_STM32G49XX) -# define FLASH_OPTR_PB4_PUPEN (1 << 22) -# endif -# define FLASH_OPTR_NBOOT1 (1 << 23) -# define FLASH_OPTR_SRAM_PE (1 << 24) -# define FLASH_OPTR_CCMSRAM_RST (1 << 25) -# define FLASH_OPTR_NSWBOOT0 (1 << 26) -# define FLASH_OPTR_NBOOT0 (1 << 27) -# define FLASH_OPTR_NRST_MODE_SHIFT (28) -# define FLASH_OPTR_NRST_MODE_MASK (0x3 << FLASH_OPTR_NRST_MODE_SHIFT) -# define FLASH_OPTR_NRST_MODE_NRST (0x1 << FLASH_OPTR_NRST_MODE_SHIFT) -# define FLASH_OPTR_NRST_MODE_GPIO (0x2 << FLASH_OPTR_NRST_MODE_SHIFT) -# define FLASH_OPTR_NRST_MODE_BIDI_NRST (0x3 << FLASH_OPTR_NRST_MODE_SHIFT) -# define FLASH_OPTR_IRHEN (1 << 30) -#endif - -/* Flash PCROP1 Start Address Register (PCROP1SR) */ - -#if defined(CONFIG_STM32_STM32G4XXX) -# define FLASH_PCROP1SR_PCROP1_STRT_SHIFT (0) -# define FLASH_PCROP1SR_PCROP1_STRT_MASK (0x7fff << FLASH_PCROP1SR_PCROP1_STRT_SHIFT) -# define FLASH_PCROP1SR_PCROP1_STRT(n) (((n) << FLASH_PCROP1SR_PCROP1_STRT_SHIFT) & FLASH_PCROP1SR_PCROP1_STRT_MASK) -#endif - -/* Flash PCROP1 End Address Register (PCROP1ER) */ - -#if defined(CONFIG_STM32_STM32G4XXX) -# define FLASH_PCROP1ER_PCROP1_END_SHIFT (0) -# define FLASH_PCROP1ER_PCROP1_END_MASK (0x7fff << FLASH_PCROP1ER_PCROP1_END_SHIFT) -# define FLASH_PCROP1ER_PCROP1_END(n) (((n) << FLASH_PCROP1ER_PCROP1_END_SHIFT) & FLASH_PCROP1ER_PCROP1_END_MASK) -# define FLASH_PCROP1ER_PCROP_RDP (1 << 31) -#endif - -/* Flash Bank 1 WRP Area A Address Register (WRP1AR) */ - -#if defined(CONFIG_STM32_STM32G4XXX) -# define FLASH_WRP1AR_WRP1A_STRT_SHIFT (0) -# define FLASH_WRP1AR_WRP1A_STRT_MASK (0x7f << FLASH_WRP1AR_WRP1A_STRT_SHIFT) -# define FLASH_WRP1AR_WRP1A_STRT(n) (((n) << FLASH_WRP1AR_WRP1A_STRT_SHIFT) & FLASH_WRP1AR_WRP1A_STRT_MASK) -# define FLASH_WRP1AR_WRP1A_END_SHIFT (16) -# define FLASH_WRP1AR_WRP1A_END_MASK (0x7f << FLASH_WRP1AR_WRP1A_END_SHIFT) -# define FLASH_WRP1AR_WRP1A_END(n) (((n) << FLASH_WRP1AR_WRP1A_END_SHIFT) & FLASH_WRP1AR_WRP1A_END_MASK) -#endif - -/* Flash Bank 1 WRP Area B Address Register (WRPB1R) */ - -#if defined(CONFIG_STM32_STM32G4XXX) -# define FLASH_WRP1BR_WRP1B_STRT_SHIFT (0) -# define FLASH_WRP1BR_WRP1B_STRT_MASK (0x7f << FLASH_WRP1BR_WRP1B_STRT_SHIFT) -# define FLASH_WRP1BR_WRP1B_STRT(n) (((n) << FLASH_WRP1BR_WRP1B_STRT_SHIFT) & FLASH_WRP1BR_WRP1B_STRT_MASK) -# define FLASH_WRP1BR_WRP1B_END_SHIFT (16) -# define FLASH_WRP1BR_WRP1B_END_MASK (0x7f << FLASH_WRP1BR_WRP1B_END_SHIFT) -# define FLASH_WRP1BR_WRP1B_END(n) (((n) << FLASH_WRP1BR_WRP1B_END_SHIFT) & FLASH_WRP1BR_WRP1B_END_MASK) -#endif - -/* Flash PCROP2 Start Address Register (PCROP2SR) */ - -#if defined(CONFIG_STM32_STM32G4XXX) -# define FLASH_PCROP2SR_PCROP2_STRT_SHIFT (0) -# define FLASH_PCROP2SR_PCROP2_STRT_MASK (0x7fff << FLASH_PCROP2SR_PCROP2_STRT_SHIFT) -# define FLASH_PCROP2SR_PCROP2_STRT(n) (((n) << FLASH_PCROP2SR_PCROP2_STRT_SHIFT) & FLASH_PCROP2SR_PCROP2_STRT_MASK) -#endif - -/* Flash PCROP2 End Address Register (PCROP2ER) */ - -#if defined(CONFIG_STM32_STM32G4XXX) -# define FLASH_PCROP2ER_PCROP2_END_SHIFT (0) -# define FLASH_PCROP2ER_PCROP2_END_MASK (0x7fff << FLASH_PCROP2ER_PCROP2_END_SHIFT) -# define FLASH_PCROP2ER_PCROP2_END(n) (((n) << FLASH_PCROP2ER_PCROP2_END_SHIFT) & FLASH_PCROP2ER_PCROP2_END_MASK) -#endif - -/* Flash Bank 2 WRP Area A Address Register (WRP2AR) */ - -#if defined(CONFIG_STM32_STM32G4XXX) -# define FLASH_WRP2AR_WRP2A_STRT_SHIFT (0) -# define FLASH_WRP2AR_WRP2A_STRT_MASK (0x7f << FLASH_WRP2AR_WRP2A_STRT_SHIFT) -# define FLASH_WRP2AR_WRP2A_STRT(n) (((n) << FLASH_WRP2AR_WRP2A_STRT_SHIFT) & FLASH_WRP2AR_WRP2A_STRT_MASK) -# define FLASH_WRP2AR_WRP2A_END_SHIFT (16) -# define FLASH_WRP2AR_WRP2A_END_MASK (0x7f << FLASH_WRP2AR_WRP2A_END_SHIFT) -# define FLASH_WRP2AR_WRP2A_END(n) (((n) << FLASH_WRP2AR_WRP2A_END_SHIFT) & FLASH_WRP2AR_WRP2A_END_MASK) -#endif - -/* Flash Bank 2 WRP Area B Address Register (WRP2BR) */ - -#if defined(CONFIG_STM32_STM32G4XXX) -# define FLASH_WRP2BR_WRP2B_STRT_SHIFT (0) -# define FLASH_WRP2BR_WRP2B_STRT_MASK (0x7f << FLASH_WRP2BR_WRP2B_STRT_SHIFT) -# define FLASH_WRP2BR_WRP2B_STRT(n) (((n) << FLASH_WRP2BR_WRP2B_STRT_SHIFT) & FLASH_WRP2BR_WRP2B_STRT_SHIFT) -# define FLASH_WRP2BR_WRP2B_END_SHIFT (16) -# define FLASH_WRP2BR_WRP2B_END_MASK (0x7f << FLASH_WRP2BR_WRP2B_END_SHIFT) -# define FLASH_WRP2BR_WRP2B_END(n) (((n) << FLASH_WRP2BR_WRP2B_END_SHIFT) & FLASH_WRP2BR_WRP2B_END_MASK) -#endif - -/* Flash Securable Area Bank 1 Register (SEC1R) */ - -#if defined(CONFIG_STM32_STM32G4XXX) -# define FLASH_SEC1R_SEC_SIZE1_SHIFT (0) -# define FLASH_SEC1R_SEC_SIZE1_MASK (0xff << FLASH_SEC1R_SEC_SIZE1_SHIFT) -# define FLASH_SEC1R_SEC_SIZE1(n) (((n) << FLASH_SEC1R_SEC_SIZE1_SHIFT) & FLASH_SEC1R_SEC_SIZE1_MASK) -# define FLASH_SEC1R_BOOT_LOCK (1 << 16) -#endif - -/* Flash Securable Area Bank 2 Register (SEC2R) */ - -#if defined(CONFIG_STM32_STM32G4XXX) -# define FLASH_SEC2R_SEC_SIZE2_SHIFT (0) -# define FLASH_SEC2R_SEC_SIZE2_MASK (0xff << FLASH_SEC2R_SEC_SIZE2_SHIFT) -# define FLASH_SEC2R_SEC_SIZE2(n) (((n) << FLASH_SEC2R_SEC_SIZE2_SHIFT) & FLASH_SEC2R_SEC_SIZE2_MASK) -#endif - -/**************************************************************************** - * Public Functions Prototypes - ****************************************************************************/ - -int stm32_flash_lock(void); -int stm32_flash_unlock(void); - -#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) -int stm32_flash_writeprotect(size_t page, bool enabled); -#endif - -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_FLASH_H */ diff --git a/arch/arm/src/stm32/hardware/stm32_fmc.h b/arch/arm/src/stm32/hardware/stm32_fmc.h deleted file mode 100644 index 149b3ab6de91a..0000000000000 --- a/arch/arm/src/stm32/hardware/stm32_fmc.h +++ /dev/null @@ -1,392 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/hardware/stm32_fmc.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_FMC_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_FMC_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "chip.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Register Offsets *********************************************************/ - -#define STM32_FMC_BCR_OFFSET(n) (8 * ((n) - 1)) -#define STM32_FMC_BCR1_OFFSET 0x0000 /* SRAM/NOR-Flash chip-select control registers 1 */ -#define STM32_FMC_BCR2_OFFSET 0x0008 /* SRAM/NOR-Flash chip-select control registers 2 */ -#define STM32_FMC_BCR3_OFFSET 0x0010 /* SRAM/NOR-Flash chip-select control registers 3 */ -#define STM32_FMC_BCR4_OFFSET 0x0018 /* SRAM/NOR-Flash chip-select control registers 4 */ - -#define STM32_FMC_BTR_OFFSET(n) (8 * ((n) - 1) + 0x0004) -#define STM32_FMC_BTR1_OFFSET 0x0004 /* SRAM/NOR-Flash chip-select timing registers 1 */ -#define STM32_FMC_BTR2_OFFSET 0x000c /* SRAM/NOR-Flash chip-select timing registers 2 */ -#define STM32_FMC_BTR3_OFFSET 0x0014 /* SRAM/NOR-Flash chip-select timing registers 3 */ -#define STM32_FMC_BTR4_OFFSET 0x001c /* SRAM/NOR-Flash chip-select timing registers 4 */ - -#define STM32_FMC_BWTR_OFFSET(n) (8 * ((n) - 1) + 0x0104) -#define STM32_FMC_BWTR1_OFFSET 0x0104 /* SRAM/NOR-Flash write timing registers 1 */ -#define STM32_FMC_BWTR2_OFFSET 0x010c /* SRAM/NOR-Flash write timing registers 2 */ -#define STM32_FMC_BWTR3_OFFSET 0x0114 /* SRAM/NOR-Flash write timing registers 3 */ -#define STM32_FMC_BWTR4_OFFSET 0x011c /* SRAM/NOR-Flash write timing registers 4 */ - -#define STM32_FMC_PCR_OFFSET(n) (0x0020 * ((n) - 1) + 0x0040) -#define STM32_FMC_PCR2_OFFSET 0x0060 /* NAND Flash/PC Card controller register 2 */ -#define STM32_FMC_PCR3_OFFSET 0x0080 /* NAND Flash/PC Card controller register 3 */ -#define STM32_FMC_PCR4_OFFSET 0x00a0 /* NAND Flash/PC Card controller register 4 */ - -#define STM32_FMC_SR_OFFSET(n) (0x0020 * ((n) - 1) + 0x0044) -#define STM32_FMC_SR2_OFFSET 0x0064 /* NAND Flash/PC Card controller register 2 */ -#define STM32_FMC_SR3_OFFSET 0x0084 /* NAND Flash/PC Card controller register 3 */ -#define STM32_FMC_SR4_OFFSET 0x00a4 /* NAND Flash/PC Card controller register 4 */ - -#define STM32_FMC_PMEM_OFFSET(n) (0x0020 * ((n) - 1) + 0x0048) -#define STM32_FMC_PMEM2_OFFSET 0x0068 /* Common memory space timing register 2 */ -#define STM32_FMC_PMEM3_OFFSET 0x0088 /* Common memory space timing register 3 */ -#define STM32_FMC_PMEM4_OFFSET 0x00a8 /* Common memory space timing register 4 */ - -#define STM32_FMC_PATT_OFFSET(n) (0x0020 * ((n) - 1) + 0x004c) -#define STM32_FMC_PATT2_OFFSET 0x006c /* Attribute memory space timing register 2 */ -#define STM32_FMC_PATT3_OFFSET 0x008c /* Attribute memory space timing register 3 */ -#define STM32_FMC_PATT4_OFFSET 0x00ac /* Attribute memory space timing register 4 */ - -#define STM32_FMC_PIO4_OFFSET 0x00b0 /* I/O space timing register 4 */ - -#define STM32_FMC_ECCR_OFFSET(n) (0x0020 * ((n) - 1) + 0x0054) -#define STM32_FMC_ECCR2_OFFSET 0x0074 /* ECC result register 2 */ -#define STM32_FMC_ECCR3_OFFSET 0x0094 /* ECC result register 3 */ - -#define STM32_FMC_SDCR1_OFFSET 0x0140 /* SDRAM Control Register, Bank 1 */ -#define STM32_FMC_SDCR2_OFFSET 0x0144 /* SDRAM Control Register, Bank 2 */ - -#define STM32_FMC_SDTR1_OFFSET 0x0148 /* SDRAM Timing Register, Bank 1 */ -#define STM32_FMC_SDTR2_OFFSET 0x014c /* SDRAM Timing Register, Bank 2 */ - -#define STM32_FMC_SDCMR_OFFSET 0x0150 /* SDRAM Config Memory register */ -#define STM32_FMC_SDRTR_OFFSET 0x0154 /* SDRAM Refresh Timing Register maybe */ -#define STM32_FMC_SDSR_OFFSET 0x0158 /* SDRAM Status Register */ - -/* Register Addresses *******************************************************/ - -#define STM32_FMC_BCR(n) (STM32_FMC_BASE + STM32_FMC_BCR_OFFSET(n)) -#define STM32_FMC_BCR1 (STM32_FMC_BASE + STM32_FMC_BCR1_OFFSET) -#define STM32_FMC_BCR2 (STM32_FMC_BASE + STM32_FMC_BCR2_OFFSET) -#define STM32_FMC_BCR3 (STM32_FMC_BASE + STM32_FMC_BCR3_OFFSET) -#define STM32_FMC_BCR4 (STM32_FMC_BASE + STM32_FMC_BCR4_OFFSET) - -#define STM32_FMC_BTR(n) (STM32_FMC_BASE + STM32_FMC_BTR_OFFSET(n)) -#define STM32_FMC_BTR1 (STM32_FMC_BASE + STM32_FMC_BTR1_OFFSET) -#define STM32_FMC_BTR2 (STM32_FMC_BASE + STM32_FMC_BTR2_OFFSET) -#define STM32_FMC_BTR3 (STM32_FMC_BASE + STM32_FMC_BTR3_OFFSET) -#define STM32_FMC_BTR4 (STM32_FMC_BASE + STM32_FMC_BTR4_OFFSET) - -#define STM32_FMC_BWTR(n) (STM32_FMC_BASE + STM32_FMC_BWTR_OFFSET(n)) -#define STM32_FMC_BWTR1 (STM32_FMC_BASE + STM32_FMC_BWTR1_OFFSET) -#define STM32_FMC_BWTR2 (STM32_FMC_BASE + STM32_FMC_BWTR2_OFFSET) -#define STM32_FMC_BWTR3 (STM32_FMC_BASE + STM32_FMC_BWTR3_OFFSET) -#define STM32_FMC_BWTR4 (STM32_FMC_BASE + STM32_FMC_BWTR4_OFFSET) - -#define STM32_FMC_PCR(n) (STM32_FMC_BASE + STM32_FMC_PCR_OFFSET(n)) -#define STM32_FMC_PCR2 (STM32_FMC_BASE + STM32_FMC_PCR2_OFFSET) -#define STM32_FMC_PCR3 (STM32_FMC_BASE + STM32_FMC_PCR3_OFFSET) -#define STM32_FMC_PCR4 (STM32_FMC_BASE + STM32_FMC_PCR4_OFFSET) - -#define STM32_FMC_SR(n) (STM32_FMC_BASE + STM32_FMC_SR_OFFSET(n)) -#define STM32_FMC_SR2 (STM32_FMC_BASE + STM32_FMC_SR2_OFFSET) -#define STM32_FMC_SR3 (STM32_FMC_BASE + STM32_FMC_SR3_OFFSET) -#define STM32_FMC_SR4 (STM32_FMC_BASE + STM32_FMC_SR4_OFFSET) - -#define STM32_FMC_PMEM(n) (STM32_FMC_BASE + STM32_FMC_PMEM_OFFSET(n)) -#define STM32_FMC_PMEM2 (STM32_FMC_BASE + STM32_FMC_PMEM2_OFFSET) -#define STM32_FMC_PMEM3 (STM32_FMC_BASE + STM32_FMC_PMEM3_OFFSET) -#define STM32_FMC_PMEM4 (STM32_FMC_BASE + STM32_FMC_PMEM4_OFFSET) - -#define STM32_FMC_PATT(n) (STM32_FMC_BASE + STM32_FMC_PATT_OFFSET(n)) -#define STM32_FMC_PATT2 (STM32_FMC_BASE + STM32_FMC_PATT2_OFFSET) -#define STM32_FMC_PATT3 (STM32_FMC_BASE + STM32_FMC_PATT3_OFFSET) -#define STM32_FMC_PATT4 (STM32_FMC_BASE + STM32_FMC_PATT4_OFFSET) - -#define STM32_FMC_PIO4 (STM32_FMC_BASE + STM32_FMC_PIO4_OFFSET) - -#define STM32_FMC_ECCR(n) (STM32_FMC_BASE + STM32_FMC_ECCR_OFFSET(n)) -#define STM32_FMC_ECCR2 (STM32_FMC_BASE + STM32_FMC_ECCR2_OFFSET) -#define STM32_FMC_ECCR3 (STM32_FMC_BASE + STM32_FMC_ECCR3_OFFSET) - -#define STM32_FMC_SDCR1 (STM32_FMC_BASE + STM32_FMC_SDCR1_OFFSET) -#define STM32_FMC_SDCR2 (STM32_FMC_BASE + STM32_FMC_SDCR2_OFFSET) - -#define STM32_FMC_SDTR1 (STM32_FMC_BASE + STM32_FMC_SDTR1_OFFSET) -#define STM32_FMC_SDTR2 (STM32_FMC_BASE + STM32_FMC_SDTR2_OFFSET) - -#define STM32_FMC_SDCMR (STM32_FMC_BASE + STM32_FMC_SDCMR_OFFSET) -#define STM32_FMC_SDRTR (STM32_FMC_BASE + STM32_FMC_SDRTR_OFFSET) -#define STM32_FMC_SDSR (STM32_FMC_BASE + STM32_FMC_SDSR_OFFSET) - -/* Register Bitfield Definitions ********************************************/ - -#define FMC_BCR_MBKEN (1 << 0) /* Memory bank enable bit */ -#define FMC_BCR_MUXEN (1 << 1) /* Address/data multiplexing enable bit */ -#define FMC_BCR_MTYP_SHIFT (2) /* Memory type */ -#define FMC_BCR_MTYP_MASK (3 << FMC_BCR_MTYP_SHIFT) -# define FMC_BCR_SRAM (0 << FMC_BCR_MTYP_SHIFT) -# define FMC_BCR_ROM (0 << FMC_BCR_MTYP_SHIFT) -# define FMC_BCR_PSRAM (1 << FMC_BCR_MTYP_SHIFT) -# define FMC_BCR_CRAM (1 << FMC_BCR_MTYP_SHIFT) -# define FMC_BCR_NOR (2 << FMC_BCR_MTYP_SHIFT) -#define FMC_BCR_MWID_SHIFT (4) /* Memory data bus width */ -#define FMC_BCR_MWID_MASK (3 << FMC_BCR_MWID_SHIFT) -# define FMC_BCR_MWID8 (0 << FMC_BCR_MWID_SHIFT) -# define FMC_BCR_MWID16 (1 << FMC_BCR_MWID_SHIFT) -#define FMC_BCR_FACCEN (1 << 6) /* Flash access enable */ -#define FMC_BCR_BURSTEN (1 << 8) /* Burst enable bit */ -#define FMC_BCR_WAITPOL (1 << 9) /* Wait signal polarity bit */ -#define FMC_BCR_WRAPMOD (1 << 10) /* Wrapped burst mode support */ -#define FMC_BCR_WAITCFG (1 << 11) /* Wait timing configuration */ -#define FMC_BCR_WREN (1 << 12) /* Write enable bit */ -#define FMC_BCR_WAITEN (1 << 13) /* Wait enable bit */ -#define FMC_BCR_EXTMOD (1 << 14) /* Extended mode enable */ -#define FMC_BCR_ASYNCWAIT (1 << 15) /* Wait signal during asynchronous transfers */ -#define FMC_BCR_CBURSTRW (1 << 19) /* Write burst enable */ - -#define FMC_BCR_RSTVALUE 0x000003d2 - -#define FMC_BTR_ADDSET_SHIFT (0) /* Address setup phase duration */ -#define FMC_BTR_ADDSET_MASK (15 << FMC_BTR_ADDSET_SHIFT) -# define FMC_BTR_ADDSET(n) ((n-1) << FMC_BTR_ADDSET_SHIFT) /* (n)xHCLK n=1..16 */ - -#define FMC_BTR_ADDHLD_SHIFT (4) /* Address-hold phase duration */ -#define FMC_BTR_ADDHLD_MASK (15 << FMC_BTR_ADDHLD_SHIFT) -# define FMC_BTR_ADDHLD(n) ((n-1) << FMC_BTR_ADDHLD_SHIFT) /* (n)xHCLK n=2..16*/ - -#define FMC_BTR_DATAST_SHIFT (8) /* Data-phase duration */ -#define FMC_BTR_DATAST_MASK (255 << FMC_BTR_DATAST_SHIFT) -# define FMC_BTR_DATAST(n) ((n-1) << FMC_BTR_DATAST_SHIFT) /* (n)xHCLK n=2..256 */ - -#define FMC_BTR_BUSTURN_SHIFT (16) /* Bus turnaround phase duration */ -#define FMC_BTR_BUSTURN_MASK (15 << FMC_BTR1_BUSTURN_SHIFT) -# define FMC_BTR_BUSTURN(n) ((n-1) << FMC_BTR_BUSTURN_SHIFT) /* (n)xHCLK n=1..16 */ - -#define FMC_BTR_CLKDIV_SHIFT (20) /* Clock divide ratio */ -#define FMC_BTR_CLKDIV_MASK (15 << FMC_BTR_CLKDIV_SHIFT) -# define FMC_BTR_CLKDIV(n) ((n-1) << FMC_BTR_CLKDIV_SHIFT) /* (n)xHCLK n=2..16 */ - -#define FMC_BTR_DATLAT_SHIFT (24) /* Data latency */ -#define FMC_BTR_DATLAT_MASK (15 << FMC_BTR_DATLAT_SHIFT) -# define FMC_BTR_DATLAT(n) ((n-2) << FMC_BTR_DATLAT_SHIFT) /* (n)xHCLK n=2..17 */ - -#define FMC_BTR_ACCMOD_SHIFT (28) /* Access mode */ -#define FMC_BTR_ACCMOD_MASK (3 << FMC_BTR_ACCMOD_SHIFT) -# define FMC_BTR_ACCMODA (0 << FMC_BTR_ACCMOD_SHIFT) -# define FMC_BTR_ACCMODB (1 << FMC_BTR_ACCMOD_SHIFT) -# define FMC_BTR_ACCMODC (2 << FMC_BTR_ACCMOD_SHIFT) -# define FMC_BTR_ACCMODD (3 << FMC_BTR_ACCMOD_SHIFT) - -#define FMC_BTR_RSTVALUE 0xffffffff - -#define FMC_BWTR_ADDSET_SHIFT (0) /* Address setup phase duration */ -#define FMC_BWTR_ADDSET_MASK (15 << FMC_BWTR_ADDSET_SHIFT) -# define FMC_BWTR_ADDSET(n) ((n-1) << FMC_BWTR_ADDSET_SHIFT) /* (n)xHCLK n=1..16 */ - -#define FMC_BWTR_ADDHLD_SHIFT (4) /* Address-hold phase duration */ -#define FMC_BWTR_ADDHLD_MASK (15 << FMC_BWTR_ADDHLD_SHIFT) -# define FMC_BWTR_ADDHLD(n) ((n-1) << FMC_BWTR_ADDHLD_SHIFT) /* (n)xHCLK n=2..16*/ - -#define FMC_BWTR_DATAST_SHIFT (8) /* Data-phase duration */ -#define FMC_BWTR_DATAST_MASK (255 << FMC_BWTR_DATAST_SHIFT) -# define FMC_BWTR_DATAST(n) ((n-1) << FMC_BWTR_DATAST_SHIFT) /* (n)xHCLK n=2..256 */ - -#define FMC_BWTR_CLKDIV_SHIFT (20) /* Clock divide ratio */ -#define FMC_BWTR_CLKDIV_MASK (15 << FMC_BWTR_CLKDIV_SHIFT) -# define FMC_BWTR_CLKDIV(n) ((n-1) << FMC_BWTR_CLKDIV_SHIFT) /* (n)xHCLK n=2..16 */ - -#define FMC_BWTR_DATLAT_SHIFT (24) /* Data latency */ -#define FMC_BWTR_DATLAT_MASK (15 << FMC_BWTR_DATLAT_SHIFT) -# define FMC_BWTR_DATLAT(n) ((n-2) << FMC_BWTR_DATLAT_SHIFT) /* (n)xHCLK n=2..17 */ - -#define FMC_BWTR_ACCMOD_SHIFT (28) /* Access mode */ -#define FMC_BWTR_ACCMOD_MASK (3 << FMC_BWTR_ACCMOD_SHIFT) -# define FMC_BWTR_ACCMODA (0 << FMC_BWTR_ACCMOD_SHIFT) -# define FMC_BWTR_ACCMODB (1 << FMC_BWTR_ACCMOD_SHIFT) -# define FMC_BWTR_ACCMODC (2 << FMC_BWTR_ACCMOD_SHIFT) -# define FMC_BWTR_ACCMODD (3 << FMC_BTR_ACCMOD_SHIFT) - -#define FMC_PCR_PWAITEN (1 << 1) /* Wait feature enable bit */ -#define FMC_PCR_PBKEN (1 << 2) /* PC Card/NAND Flash memory bank enable bit */ -#define FMC_PCR_PTYP (1 << 3) /* Memory type */ -#define FMC_PCR_PWID_SHIFT (4) /* NAND Flash databus width */ -#define FMC_PCR_PWID_MASK (3 << FMC_PCR_PWID_SHIFT) -# define FMC_PCR_PWID8 (0 << FMC_PCR_PWID_SHIFT) -# define FMC_PCR_PWID16 (1 << FMC_PCR_PWID_SHIFT) -#define FMC_PCR_ECCEN (1 << 6) /* ECC computation logic enable bit */ -#define FMC_PCR_TCLR_SHIFT (9) /* CLE to RE delay */ -#define FMC_PCR_TCLR_MASK (15 << FMC_PCR_TCLR_SHIFT) -# define FMC_PCR_TCLR(n) ((n-1) << FMC_PCR_TCLR_SHIFT) /* (n)xHCLK n=1..16 */ - -#define FMC_PCR_TAR_SHIFT (13) /* ALE to RE delay */ -#define FMC_PCR_TAR_MASK (15 << FMC_PCR_TAR_MASK) -# define FMC_PCR_TAR(n) ((n-1) << FMC_PCR_TAR_SHIFT) /* (n)xHCLK n=1..16 */ - -#define FMC_PCR_ECCPS_SHIFT (17) /* ECC page size */ -#define FMC_PCR_ECCPS_MASK (7 << FMC_PCR_ECCPS_SHIFT) -# define FMC_PCR_ECCPS256 (0 << FMC_PCR_ECCPS_SHIFT) /* 256 bytes */ -# define FMC_PCR_ECCPS512 (1 << FMC_PCR_ECCPS_SHIFT) /* 512 bytes */ -# define FMC_PCR_ECCPS1024 (2 << FMC_PCR_ECCPS_SHIFT) /* 1024 bytes */ -# define FMC_PCR_ECCPS2048 (3 << FMC_PCR_ECCPS_SHIFT) /* 2048 bytes */ -# define FMC_PCR_ECCPS4096 (4 << FMC_PCR_ECCPS_SHIFT) /* 8192 bytes */ -# define FMC_PCR_ECCPS8192 (5 << FMC_PCR_ECCPS_SHIFT) /* 1024 bytes */ - -#define FMC_SR_IRS (1 << 0) /* Interrupt Rising Edge status */ -#define FMC_SR_ILS (1 << 1) /* Interrupt Level status */ -#define FMC_SR_IFS (1 << 2) /* Interrupt Falling Edge status */ -#define FMC_SR_IREN (1 << 3) /* Interrupt Rising Edge detection Enable bit */ -#define FMC_SR_ILEN (1 << 4) /* Interrupt Level detection Enable bit */ -#define FMC_SR_IFEN (1 << 5) /* Interrupt Falling Edge detection Enable bit */ -#define FMC_SR_FEMPT (1 << 6) /* FIFO empty */ - -#define FMC_PMEM_MEMSET_SHIFT (0) /* Common memory setup time */ -#define FMC_PMEM_MEMSET_MASK (255 << FMC_PMEM_MEMSET_SHIFT) -# define FMC_PMEM_MEMSET(n) ((n-1) << FMC_PMEM_MEMSET_SHIFT) /* (n)xHCLK n=1..256 */ - -#define FMC_PMEM_MEMWAIT_SHIFT (8) /* Common memory wait time */ -#define FMC_PMEM_MEMWAIT_MASK (255 << FMC_PMEM_MEMWAIT_SHIFT) -# define FMC_PMEM_MEMWAIT(n) ((n-1) << FMC_PMEM_MEMWAIT_SHIFT) /* (n)xHCLK n=2..256 */ - -#define FMC_PMEM_MEMHOLD_SHIFT (16) /* Common memoryhold time */ -#define FMC_PMEM_MEMHOLD_MASK (255 << FMC_PMEM_MEMHOLD_SHIFT) -# define FMC_PMEM_MEMHOLD(n) ((n) << FMC_PMEM_MEMHOLD_SHIFT) /* (n)xHCLK n=1..255 */ - -#define FMC_PMEM_MEMHIZ_SHIFT (24) /* Common memory databus HiZ time */ -#define FMC_PMEM_MEMHIZ_MASK (255 << FMC_PMEM_MEMHIZ_SHIFT) -# define FMC_PMEM_MEMHIZ(n) ((n) << FMC_PMEM_MEMHIZ_SHIFT) /* (n)xHCLK n=0..255 */ - -#define FMC_PATT_ATTSET_SHIFT (0) /* Attribute memory setup time */ -#define FMC_PATT_ATTSET_MASK (255 << FMC_PATT_ATTSET_SHIFT) -# define FMC_PATT_ATTSET(n) ((n-1) << FMC_PATT_ATTSET_SHIFT) /* (n)xHCLK n=1..256 */ - -#define FMC_PATT_ATTWAIT_SHIFT (8) /* Attribute memory wait time */ -#define FMC_PATT_ATTWAIT_MASK (255 << FMC_PATT_ATTWAIT_SHIFT) -# define FMC_PATT_ATTWAIT(n) ((n-1) << FMC_PATT_ATTWAIT_SHIFT) /* (n)xHCLK n=2..256 */ - -#define FMC_PATT_ATTHOLD_SHIFT (16) /* Attribute memory hold time */ -#define FMC_PATT_ATTHOLD_MASK (255 << FMC_PATT_ATTHOLD_SHIFT) -# define FMC_PATT_ATTHOLD(n) ((n) << FMC_PATT_ATTHOLD_SHIFT) /* (n)xHCLK n=1..255 */ - -#define FMC_PATT_ATTHIZ_SHIFT (24) /* Attribute memory databus HiZ time */ -#define FMC_PATT_ATTHIZ_MASK (255 << FMC_PATT_ATTHIZ_SHIFT) -# define FMC_PATT_ATTHIZ(n) ((n) << FMC_PATT_ATTHIZ_SHIFT) /* (n)xHCLK n=0..255 */ - -#define FMC_PIO4_IOSET_SHIFT (0) /* IO memory setup time */ -#define FMC_PIO4_IOSET_MASK (255 << FMC_PIO4_IOSET_SHIFT) -# define FMC_PIO4_IOSET(n) ((n-1) << FMC_PIO4_IOSET_SHIFT) /* (n)xHCLK n=1..256 */ - -#define FMC_PIO4_IOWAIT_SHIFT (8) /* IO memory wait time */ -#define FMC_PIO4_IOWAIT_MASK (255 << FMC_PIO4_IOWAIT_SHIFT) -# define FMC_PIO4_IOWAIT(n) ((n-1) << FMC_PIO4_IOWAIT_SHIFT) /* (n)xHCLK n=2..256 */ - -#define FMC_PIO4_IOHOLD_SHIFT (16) /* IO memory hold time */ -#define FMC_PIO4_IOHOLD_MASK (255 << FMC_PIO4_IOHOLD_SHIFT) -# define FMC_PIO4_IOHOLD(n) ((n) << FMC_PIO4_IOHOLD_SHIFT) /* (n)xHCLK n=1..255 */ - -#define FMC_PIO4_IOHIZ_SHIFT (24) /* IO memory databus HiZ time */ -#define FMC_PIO4_IOHIZ_MASK (255 << FMC_PIO4_IOHIZ_SHIFT) -# define FMC_PIO4_IOHIZ(n) ((n) << FMC_PIO4_IOHIZ_SHIFT) /* (n)xHCLK n=0..255 */ - -#define FMC_SDCR_RESERVED (0x1ffff << 15) /* reserved bits */ - -#define FMC_SDCR_RPIPE_0 (0 << 13) /* read pipe */ -#define FMC_SDCR_RPIPE_1 (1 << 13) -#define FMC_SDCR_RPIPE_2 (2 << 13) -#define FMC_SDCR_READBURST (1 << 12) /* read burst */ -#define FMC_SDCR_SDCLK_DISABLE (0 << 10) /* sdram clock */ -#define FMC_SDCR_SDCLK_2X (2 << 10) -#define FMC_SDCR_SDCLK_3X (3 << 10) -#define FMC_SDCR_WP (1 << 9) /* write protect */ -#define FMC_SDCR_CAS_LATENCY_1 (1 << 7) /* cas latency */ -#define FMC_SDCR_CAS_LATENCY_2 (2 << 7) -#define FMC_SDCR_CAS_LATENCY_3 (3 << 7) -#define FMC_SDCR_NBANKS_2 (0 << 6) /* number of internal banks */ -#define FMC_SDCR_NBANKS_4 (1 << 6) -#define FMC_SDCR_WIDTH_8 (0 << 4) /* memory width */ -#define FMC_SDCR_WIDTH_16 (1 << 4) -#define FMC_SDCR_WIDTH_32 (2 << 4) -#define FMC_SDCR_ROWS_11 (0 << 2) /* number of rows */ -#define FMC_SDCR_ROWS_12 (1 << 2) -#define FMC_SDCR_ROWS_13 (2 << 2) -#define FMC_SDCR_COLS_8 (0 << 0) /* number of columns */ -#define FMC_SDCR_COLS_9 (1 << 0) -#define FMC_SDCR_COLS_10 (2 << 0) -#define FMC_SDCR_COLS_11 (3 << 0) - -#define FMC_SDTR_RESERVED (15 << 28) /* reserved bits */ -#define FMC_SDTR_TMRD(n) (((n & 15) - 1) << 0) -#define FMC_SDTR_TXSR(n) (((n & 15) - 1) << 4) -#define FMC_SDTR_TRAS(n) (((n & 15) - 1) << 8) -#define FMC_SDTR_TRC(n) (((n & 15) - 1) << 12) -#define FMC_SDTR_TWR(n) (((n & 15) - 1) << 16) -#define FMC_SDTR_TRP(n) (((n & 15) - 1) << 20) -#define FMC_SDTR_TRCD(n) (((n & 15) - 1) << 24) - -/* Note: The FMC_SDCMR_MDR_x values can be found in the SDRAM datasheet. - * They should be standard, but it's probably a good idea to review - * the datasheet for your SDRAM device. - */ -#define FMC_SDCMR_RESERVED (0x3ff << 22) /* reserved bits */ -#define FMC_SDCMR_MDR_BURST_LENGTH_1 ((0 << 0) << 9) -#define FMC_SDCMR_MDR_BURST_LENGTH_2 ((1 << 0) << 9) -#define FMC_SDCMR_MDR_BURST_LENGTH_4 ((2 << 0) << 9) -#define FMC_SDCMR_MDR_BURST_LENGTH_8 ((3 << 0) << 9) -#define FMC_SDCMR_MDR_BURST_LENGTH_FULL ((7 << 0) << 9) -#define FMC_SDCMR_MDR_BURST_TYPE_SEQUENTIAL ((0 << 3) << 9) -#define FMC_SDCMR_MDR_BURST_TYPE_INTERLEAVE ((1 << 3) << 9) -#define FMC_SDCMR_MDR_CAS_LATENCY_1 ((1 << 4) << 9) -#define FMC_SDCMR_MDR_CAS_LATENCY_2 ((2 << 4) << 9) -#define FMC_SDCMR_MDR_CAS_LATENCY_3 ((3 << 4) << 9) -#define FMC_SDCMR_MDR_MODE_NORMAL ((0 << 7) << 9) -#define FMC_SDCMR_MDR_WBL_BURST ((0 << 9) << 9) -#define FMC_SDCMR_MDR_WBL_SINGLE ((1 << 9) << 9) -#define FMC_SDCMR_NRFS(n) (((n & 15) - 1) << 5) -#define FMC_SDCMR_BANK_1 (1 << 4) -#define FMC_SDCMR_BANK_2 (1 << 3) -#define FMC_SDCMR_CMD_NORMAL (0 << 0) -#define FMC_SDCMR_CMD_CLK_ENABLE (1 << 0) -#define FMC_SDCMR_CMD_PALL (2 << 0) -#define FMC_SDCMR_CMD_AUTO_REFRESH (3 << 0) -#define FMC_SDCMR_CMD_LOAD_MODE (4 << 0) -#define FMC_SDCMR_CMD_SELF_REFRESH (5 << 0) -#define FMC_SDCMR_CMD_POWER_DOWN (6 << 0) - -#define FMC_SDSR_RE (1 << 0) -#define FMC_SDSR_BUSY (1 << 5) -#define FMC_SDSR_MODES1_NORMAL (0 << 1) -#define FMC_SDSR_MODES1_SELF_REFRESH (1 << 1) -#define FMC_SDSR_MODES1_POWER_DOWN (2 << 1) -#define FMC_SDSR_MODES2_NORMAL (0 << 3) -#define FMC_SDSR_MODES2_SELF_REFRESH (1 << 3) -#define FMC_SDSR_MODES2_POWER_DOWN (2 << 3) - -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_FMC_H */ diff --git a/arch/arm/src/stm32/hardware/stm32_fsmc.h b/arch/arm/src/stm32/hardware/stm32_fsmc.h deleted file mode 100644 index b53230f351c5a..0000000000000 --- a/arch/arm/src/stm32/hardware/stm32_fsmc.h +++ /dev/null @@ -1,301 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/hardware/stm32_fsmc.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_FMSC_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_FMSC_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "chip.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Register Offsets *********************************************************/ - -#define STM32_FSMC_BCR_OFFSET(n) (8 * ((n) - 1)) -#define STM32_FSMC_BCR1_OFFSET 0x0000 /* SRAM/NOR-Flash chip-select control registers 1 */ -#define STM32_FSMC_BCR2_OFFSET 0x0008 /* SRAM/NOR-Flash chip-select control registers 2 */ -#define STM32_FSMC_BCR3_OFFSET 0x0010 /* SRAM/NOR-Flash chip-select control registers 3 */ -#define STM32_FSMC_BCR4_OFFSET 0x0018 /* SRAM/NOR-Flash chip-select control registers 4 */ - -#define STM32_FSMC_BTR_OFFSET(n) (8 * ((n) - 1) + 0x0004) -#define STM32_FSMC_BTR1_OFFSET 0x0004 /* SRAM/NOR-Flash chip-select timing registers 1 */ -#define STM32_FSMC_BTR2_OFFSET 0x000c /* SRAM/NOR-Flash chip-select timing registers 2 */ -#define STM32_FSMC_BTR3_OFFSET 0x0014 /* SRAM/NOR-Flash chip-select timing registers 3 */ -#define STM32_FSMC_BTR4_OFFSET 0x001c /* SRAM/NOR-Flash chip-select timing registers 4 */ - -#define STM32_FSMC_BWTR_OFFSET(n) (8 * ((n) - 1) + 0x0104) -#define STM32_FSMC_BWTR1_OFFSET 0x0104 /* SRAM/NOR-Flash write timing registers 1 */ -#define STM32_FSMC_BWTR2_OFFSET 0x010c /* SRAM/NOR-Flash write timing registers 2 */ -#define STM32_FSMC_BWTR3_OFFSET 0x0114 /* SRAM/NOR-Flash write timing registers 3 */ -#define STM32_FSMC_BWTR4_OFFSET 0x011c /* SRAM/NOR-Flash write timing registers 4 */ - -#define STM32_FSMC_PCR_OFFSET(n) (0x0020 * ((n) - 1) + 0x0040) -#define STM32_FSMC_PCR2_OFFSET 0x0060 /* NAND Flash/PC Card controller register 2 */ -#define STM32_FSMC_PCR3_OFFSET 0x0080 /* NAND Flash/PC Card controller register 3 */ -#define STM32_FSMC_PCR4_OFFSET 0x00a0 /* NAND Flash/PC Card controller register 4 */ - -#define STM32_FSMC_SR_OFFSET(n) (0x0020 * ((n) - 1) + 0x0044) -#define STM32_FSMC_SR2_OFFSET 0x0064 /* NAND Flash/PC Card controller register 2 */ -#define STM32_FSMC_SR3_OFFSET 0x0084 /* NAND Flash/PC Card controller register 3 */ -#define STM32_FSMC_SR4_OFFSET 0x00a4 /* NAND Flash/PC Card controller register 4 */ - -#define STM32_FSMC_PMEM_OFFSET(n) (0x0020 * ((n) - 1) + 0x0048) -#define STM32_FSMC_PMEM2_OFFSET 0x0068 /* Common memory space timing register 2 */ -#define STM32_FSMC_PMEM3_OFFSET 0x0088 /* Common memory space timing register 3 */ -#define STM32_FSMC_PMEM4_OFFSET 0x00a8 /* Common memory space timing register 4 */ - -#define STM32_FSMC_PATT_OFFSET(n) (0x0020 * ((n) - 1) + 0x004c) -#define STM32_FSMC_PATT2_OFFSET 0x006c /* Attribute memory space timing register 2 */ -#define STM32_FSMC_PATT3_OFFSET 0x008c /* Attribute memory space timing register 3 */ -#define STM32_FSMC_PATT4_OFFSET 0x00ac /* Attribute memory space timing register 4 */ - -#define STM32_FSMC_PIO4_OFFSET 0x00b0 /* I/O space timing register 4 */ - -#define STM32_FSMC_ECCR_OFFSET(n) (0x0020 * ((n) - 1) + 0x0054) -#define STM32_FSMC_ECCR2_OFFSET 0x0074 /* ECC result register 2 */ -#define STM32_FSMC_ECCR3_OFFSET 0x0094 /* ECC result register 3 */ - -/* Register Addresses *******************************************************/ - -#define STM32_FSMC_BCR(n) (STM32_FSMC_BASE + STM32_FSMC_BCR_OFFSET(n)) -#define STM32_FSMC_BCR1 (STM32_FSMC_BASE + STM32_FSMC_BCR1_OFFSET) -#define STM32_FSMC_BCR2 (STM32_FSMC_BASE + STM32_FSMC_BCR2_OFFSET) -#define STM32_FSMC_BCR3 (STM32_FSMC_BASE + STM32_FSMC_BCR3_OFFSET) -#define STM32_FSMC_BCR4 (STM32_FSMC_BASE + STM32_FSMC_BCR4_OFFSET) - -#define STM32_FSMC_BTR(n) (STM32_FSMC_BASE + STM32_FSMC_BTR_OFFSET(n)) -#define STM32_FSMC_BTR1 (STM32_FSMC_BASE + STM32_FSMC_BTR1_OFFSET) -#define STM32_FSMC_BTR2 (STM32_FSMC_BASE + STM32_FSMC_BTR2_OFFSET) -#define STM32_FSMC_BTR3 (STM32_FSMC_BASE + STM32_FSMC_BTR3_OFFSET) -#define STM32_FSMC_BTR4 (STM32_FSMC_BASE + STM32_FSMC_BTR4_OFFSET) - -#define STM32_FSMC_BWTR(n) (STM32_FSMC_BASE + STM32_FSMC_BWTR_OFFSET(n)) -#define STM32_FSMC_BWTR1 (STM32_FSMC_BASE + STM32_FSMC_BWTR1_OFFSET) -#define STM32_FSMC_BWTR2 (STM32_FSMC_BASE + STM32_FSMC_BWTR2_OFFSET) -#define STM32_FSMC_BWTR3 (STM32_FSMC_BASE + STM32_FSMC_BWTR3_OFFSET) -#define STM32_FSMC_BWTR4 (STM32_FSMC_BASE + STM32_FSMC_BWTR4_OFFSET) - -#define STM32_FSMC_PCR(n) (STM32_FSMC_BASE + STM32_FSMC_PCR_OFFSET(n)) -#define STM32_FSMC_PCR2 (STM32_FSMC_BASE + STM32_FSMC_PCR2_OFFSET) -#define STM32_FSMC_PCR3 (STM32_FSMC_BASE + STM32_FSMC_PCR3_OFFSET) -#define STM32_FSMC_PCR4 (STM32_FSMC_BASE + STM32_FSMC_PCR4_OFFSET) - -#define STM32_FSMC_SR(n) (STM32_FSMC_BASE + STM32_FSMC_SR_OFFSET(n)) -#define STM32_FSMC_SR2 (STM32_FSMC_BASE + STM32_FSMC_SR2_OFFSET) -#define STM32_FSMC_SR3 (STM32_FSMC_BASE + STM32_FSMC_SR3_OFFSET) -#define STM32_FSMC_SR4 (STM32_FSMC_BASE + STM32_FSMC_SR4_OFFSET) - -#define STM32_FSMC_PMEM(n) (STM32_FSMC_BASE + STM32_FSMC_PMEM_OFFSET(n)) -#define STM32_FSMC_PMEM2 (STM32_FSMC_BASE + STM32_FSMC_PMEM2_OFFSET) -#define STM32_FSMC_PMEM3 (STM32_FSMC_BASE + STM32_FSMC_PMEM3_OFFSET) -#define STM32_FSMC_PMEM4 (STM32_FSMC_BASE + STM32_FSMC_PMEM4_OFFSET) - -#define STM32_FSMC_PATT(n) (STM32_FSMC_BASE + STM32_FSMC_PATT_OFFSET(n)) -#define STM32_FSMC_PATT2 (STM32_FSMC_BASE + STM32_FSMC_PATT2_OFFSET) -#define STM32_FSMC_PATT3 (STM32_FSMC_BASE + STM32_FSMC_PATT3_OFFSET) -#define STM32_FSMC_PATT4 (STM32_FSMC_BASE + STM32_FSMC_PATT4_OFFSET) - -#define STM32_FSMC_PIO4 (STM32_FSMC_BASE + STM32_FSMC_PIO4_OFFSET) - -#define STM32_FSMC_ECCR(n) (STM32_FSMC_BASE + STM32_FSMC_ECCR_OFFSET(n)) -#define STM32_FSMC_ECCR2 (STM32_FSMC_BASE + STM32_FSMC_ECCR2_OFFSET) -#define STM32_FSMC_ECCR3 (STM32_FSMC_BASE + STM32_FSMC_ECCR3_OFFSET) - -/* Register Bitfield Definitions ********************************************/ - -#define FSMC_BCR_MBKEN (1 << 0) /* Memory bank enable bit */ -#define FSMC_BCR_MUXEN (1 << 1) /* Address/data multiplexing enable bit */ -#define FSMC_BCR_MTYP_SHIFT (2) /* Memory type */ -#define FSMC_BCR_MTYP_MASK (3 << FSMC_BCR_MTYP_SHIFT) -# define FSMC_BCR_SRAM (0 << FSMC_BCR_MTYP_SHIFT) -# define FSMC_BCR_ROM (0 << FSMC_BCR_MTYP_SHIFT) -# define FSMC_BCR_PSRAM (1 << FSMC_BCR_MTYP_SHIFT) -# define FSMC_BCR_CRAM (1 << FSMC_BCR_MTYP_SHIFT) -# define FSMC_BCR_NOR (2 << FSMC_BCR_MTYP_SHIFT) -#define FSMC_BCR_MWID_SHIFT (4) /* Memory data bus width */ -#define FSMC_BCR_MWID_MASK (3 << FSMC_BCR_MWID_SHIFT) -# define FSMC_BCR_MWID8 (0 << FSMC_BCR_MWID_SHIFT) -# define FSMC_BCR_MWID16 (1 << FSMC_BCR_MWID_SHIFT) -#define FSMC_BCR_FACCEN (1 << 6) /* Flash access enable */ -#define FSMC_BCR_BURSTEN (1 << 8) /* Burst enable bit */ -#define FSMC_BCR_WAITPOL (1 << 9) /* Wait signal polarity bit */ -#define FSMC_BCR_WRAPMOD (1 << 10) /* Wrapped burst mode support */ -#define FSMC_BCR_WAITCFG (1 << 11) /* Wait timing configuration */ -#define FSMC_BCR_WREN (1 << 12) /* Write enable bit */ -#define FSMC_BCR_WAITEN (1 << 13) /* Wait enable bit */ -#define FSMC_BCR_EXTMOD (1 << 14) /* Extended mode enable */ -#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) -# define FSMC_BCR_ASYNCWAIT (1 << 15) /* Wait signal during asynchronous transfers */ -#endif -#define FSMC_BCR_CBURSTRW (1 << 19) /* Write burst enable */ - -#define FSMC_BCR_RSTVALUE 0x000003d2 - -#define FSMC_BTR_ADDSET_SHIFT (0) /* Address setup phase duration */ -#define FSMC_BTR_ADDSET_MASK (15 << FSMC_BTR_ADDSET_SHIFT) -# define FSMC_BTR_ADDSET(n) ((n-1) << FSMC_BTR_ADDSET_SHIFT) /* (n)xHCLK n=1..16 */ - -#define FSMC_BTR_ADDHLD_SHIFT (4) /* Address-hold phase duration */ -#define FSMC_BTR_ADDHLD_MASK (15 << FSMC_BTR_ADDHLD_SHIFT) -# define FSMC_BTR_ADDHLD(n) ((n-1) << FSMC_BTR_ADDHLD_SHIFT) /* (n)xHCLK n=2..16*/ - -#define FSMC_BTR_DATAST_SHIFT (8) /* Data-phase duration */ -#define FSMC_BTR_DATAST_MASK (255 << FSMC_BTR_DATAST_SHIFT) -# define FSMC_BTR_DATAST(n) ((n-1) << FSMC_BTR_DATAST_SHIFT) /* (n)xHCLK n=2..256 */ - -#define FSMC_BTR_BUSTURN_SHIFT (16) /* Bus turnaround phase duration */ -#define FSMC_BTR_BUSTURN_MASK (15 << FSMC_BTR1_BUSTURN_SHIFT) -# define FSMC_BTR_BUSTURN(n) ((n-1) << FSMC_BTR_BUSTURN_SHIFT) /* (n)xHCLK n=1..16 */ - -#define FSMC_BTR_CLKDIV_SHIFT (20) /* Clock divide ratio */ -#define FSMC_BTR_CLKDIV_MASK (15 << FSMC_BTR_CLKDIV_SHIFT) -# define FSMC_BTR_CLKDIV(n) ((n-1) << FSMC_BTR_CLKDIV_SHIFT) /* (n)xHCLK n=2..16 */ - -#define FSMC_BTR_DATLAT_SHIFT (24) /* Data latency */ -#define FSMC_BTR_DATLAT_MASK (15 << FSMC_BTR_DATLAT_SHIFT) -# define FSMC_BTR_DATLAT(n) ((n-2) << FSMC_BTR_DATLAT_SHIFT) /* (n)xHCLK n=2..17 */ - -#define FSMC_BTR_ACCMOD_SHIFT (28) /* Access mode */ -#define FSMC_BTR_ACCMOD_MASK (3 << FSMC_BTR_ACCMOD_SHIFT) -# define FSMC_BTR_ACCMODA (0 << FSMC_BTR_ACCMOD_SHIFT) -# define FSMC_BTR_ACCMODB (1 << FSMC_BTR_ACCMOD_SHIFT) -# define FSMC_BTR_ACCMODC (2 << FSMC_BTR_ACCMOD_SHIFT) -# define FSMC_BTR_ACCMODD (3 << FSMC_BTR_ACCMOD_SHIFT) - -#define FSMC_BTR_RSTVALUE 0xffffffff - -#define FSMC_BWTR_ADDSET_SHIFT (0) /* Address setup phase duration */ -#define FSMC_BWTR_ADDSET_MASK (15 << FSMC_BWTR_ADDSET_SHIFT) -# define FSMC_BWTR_ADDSET(n) ((n-1) << FSMC_BWTR_ADDSET_SHIFT) /* (n)xHCLK n=1..16 */ - -#define FSMC_BWTR_ADDHLD_SHIFT (4) /* Address-hold phase duration */ -#define FSMC_BWTR_ADDHLD_MASK (15 << FSMC_BWTR_ADDHLD_SHIFT) -# define FSMC_BWTR_ADDHLD(n) ((n-1) << FSMC_BWTR_ADDHLD_SHIFT) /* (n)xHCLK n=2..16*/ - -#define FSMC_BWTR_DATAST_SHIFT (8) /* Data-phase duration */ -#define FSMC_BWTR_DATAST_MASK (255 << FSMC_BWTR_DATAST_SHIFT) -# define FSMC_BWTR_DATAST(n) ((n-1) << FSMC_BWTR_DATAST_SHIFT) /* (n)xHCLK n=2..256 */ - -#define FSMC_BWTR_CLKDIV_SHIFT (20) /* Clock divide ratio */ -#define FSMC_BWTR_CLKDIV_MASK (15 << FSMC_BWTR_CLKDIV_SHIFT) -# define FSMC_BWTR_CLKDIV(n) ((n-1) << FSMC_BWTR_CLKDIV_SHIFT) /* (n)xHCLK n=2..16 */ - -#define FSMC_BWTR_DATLAT_SHIFT (24) /* Data latency */ -#define FSMC_BWTR_DATLAT_MASK (15 << FSMC_BWTR_DATLAT_SHIFT) -# define FSMC_BWTR_DATLAT(n) ((n-2) << FSMC_BWTR_DATLAT_SHIFT) /* (n)xHCLK n=2..17 */ - -#define FSMC_BWTR_ACCMOD_SHIFT (28) /* Access mode */ -#define FSMC_BWTR_ACCMOD_MASK (3 << FSMC_BWTR_ACCMOD_SHIFT) -# define FSMC_BWTR_ACCMODA (0 << FSMC_BWTR_ACCMOD_SHIFT) -# define FSMC_BWTR_ACCMODB (1 << FSMC_BWTR_ACCMOD_SHIFT) -# define FSMC_BWTR_ACCMODC (2 << FSMC_BWTR_ACCMOD_SHIFT) -# define FSMC_BWTR_ACCMODD (3 << FSMC_BTR_ACCMOD_SHIFT) - -#define FSMC_PCR_PWAITEN (1 << 1) /* Wait feature enable bit */ -#define FSMC_PCR_PBKEN (1 << 2) /* PC Card/NAND Flash memory bank enable bit */ -#define FSMC_PCR_PTYP (1 << 3) /* Memory type */ -#define FSMC_PCR_PWID_SHIFT (4) /* NAND Flash databus width */ -#define FSMC_PCR_PWID_MASK (3 << FSMC_PCR_PWID_SHIFT) -# define FSMC_PCR_PWID8 (0 << FSMC_PCR_PWID_SHIFT) -# define FSMC_PCR_PWID16 (1 << FSMC_PCR_PWID_SHIFT) -#define FSMC_PCR_ECCEN (1 << 6) /* ECC computation logic enable bit */ -#define FSMC_PCR_TCLR_SHIFT (9) /* CLE to RE delay */ -#define FSMC_PCR_TCLR_MASK (15 << FSMC_PCR_TCLR_SHIFT) -# define FSMC_PCR_TCLR(n) ((n-1) << FSMC_PCR_TCLR_SHIFT) /* (n)xHCLK n=1..16 */ - -#define FSMC_PCR_TAR_SHIFT (13) /* ALE to RE delay */ -#define FSMC_PCR_TAR_MASK (15 << FSMC_PCR_TAR_MASK) -# define FSMC_PCR_TAR(n) ((n-1) << FSMC_PCR_TAR_SHIFT) /* (n)xHCLK n=1..16 */ - -#define FSMC_PCR_ECCPS_SHIFT (17) /* ECC page size */ -#define FSMC_PCR_ECCPS_MASK (7 << FSMC_PCR_ECCPS_SHIFT) -# define FSMC_PCR_ECCPS256 (0 << FSMC_PCR_ECCPS_SHIFT) /* 256 bytes */ -# define FSMC_PCR_ECCPS512 (1 << FSMC_PCR_ECCPS_SHIFT) /* 512 bytes */ -# define FSMC_PCR_ECCPS1024 (2 << FSMC_PCR_ECCPS_SHIFT) /* 1024 bytes */ -# define FSMC_PCR_ECCPS2048 (3 << FSMC_PCR_ECCPS_SHIFT) /* 2048 bytes */ -# define FSMC_PCR_ECCPS4096 (4 << FSMC_PCR_ECCPS_SHIFT) /* 8192 bytes */ -# define FSMC_PCR_ECCPS8192 (5 << FSMC_PCR_ECCPS_SHIFT) /* 1024 bytes */ - -#define FSMC_SR_IRS (1 << 0) /* Interrupt Rising Edge status */ -#define FSMC_SR_ILS (1 << 1) /* Interrupt Level status */ -#define FSMC_SR_IFS (1 << 2) /* Interrupt Falling Edge status */ -#define FSMC_SR_IREN (1 << 3) /* Interrupt Rising Edge detection Enable bit */ -#define FSMC_SR_ILEN (1 << 4) /* Interrupt Level detection Enable bit */ -#define FSMC_SR_IFEN (1 << 5) /* Interrupt Falling Edge detection Enable bit */ -#define FSMC_SR_FEMPT (1 << 6) /* FIFO empty */ - -#define FSMC_PMEM_MEMSET_SHIFT (0) /* Common memory setup time */ -#define FSMC_PMEM_MEMSET_MASK (255 << FSMC_PMEM_MEMSET_SHIFT) -# define FSMC_PMEM_MEMSET(n) ((n-1) << FSMC_PMEM_MEMSET_SHIFT) /* (n)xHCLK n=1..256 */ - -#define FSMC_PMEM_MEMWAIT_SHIFT (8) /* Common memory wait time */ -#define FSMC_PMEM_MEMWAIT_MASK (255 << FSMC_PMEM_MEMWAIT_SHIFT) -# define FSMC_PMEM_MEMWAIT(n) ((n-1) << FSMC_PMEM_MEMWAIT_SHIFT) /* (n)xHCLK n=2..256 */ - -#define FSMC_PMEM_MEMHOLD_SHIFT (16) /* Common memoryhold time */ -#define FSMC_PMEM_MEMHOLD_MASK (255 << FSMC_PMEM_MEMHOLD_SHIFT) -# define FSMC_PMEM_MEMHOLD(n) ((n) << FSMC_PMEM_MEMHOLD_SHIFT) /* (n)xHCLK n=1..255 */ - -#define FSMC_PMEM_MEMHIZ_SHIFT (24) /* Common memory databus HiZ time */ -#define FSMC_PMEM_MEMHIZ_MASK (255 << FSMC_PMEM_MEMHIZ_SHIFT) -# define FSMC_PMEM_MEMHIZ(n) ((n) << FSMC_PMEM_MEMHIZ_SHIFT) /* (n)xHCLK n=0..255 */ - -#define FSMC_PATT_ATTSET_SHIFT (0) /* Attribute memory setup time */ -#define FSMC_PATT_ATTSET_MASK (255 << FSMC_PATT_ATTSET_SHIFT) -# define FSMC_PATT_ATTSET(n) ((n-1) << FSMC_PATT_ATTSET_SHIFT) /* (n)xHCLK n=1..256 */ - -#define FSMC_PATT_ATTWAIT_SHIFT (8) /* Attribute memory wait time */ -#define FSMC_PATT_ATTWAIT_MASK (255 << FSMC_PATT_ATTWAIT_SHIFT) -# define FSMC_PATT_ATTWAIT(n) ((n-1) << FSMC_PATT_ATTWAIT_SHIFT) /* (n)xHCLK n=2..256 */ - -#define FSMC_PATT_ATTHOLD_SHIFT (16) /* Attribute memory hold time */ -#define FSMC_PATT_ATTHOLD_MASK (255 << FSMC_PATT_ATTHOLD_SHIFT) -# define FSMC_PATT_ATTHOLD(n) ((n) << FSMC_PATT_ATTHOLD_SHIFT) /* (n)xHCLK n=1..255 */ - -#define FSMC_PATT_ATTHIZ_SHIFT (24) /* Attribute memory databus HiZ time */ -#define FSMC_PATT_ATTHIZ_MASK (255 << FSMC_PATT_ATTHIZ_SHIFT) -# define FSMC_PATT_ATTHIZ(n) ((n) << FSMC_PATT_ATTHIZ_SHIFT) /* (n)xHCLK n=0..255 */ - -#define FSMC_PIO4_IOSET_SHIFT (0) /* IO memory setup time */ -#define FSMC_PIO4_IOSET_MASK (255 << FSMC_PIO4_IOSET_SHIFT) -# define FSMC_PIO4_IOSET(n) ((n-1) << FSMC_PIO4_IOSET_SHIFT) /* (n)xHCLK n=1..256 */ - -#define FSMC_PIO4_IOWAIT_SHIFT (8) /* IO memory wait time */ -#define FSMC_PIO4_IOWAIT_MASK (255 << FSMC_PIO4_IOWAIT_SHIFT) -# define FSMC_PIO4_IOWAIT(n) ((n-1) << FSMC_PIO4_IOWAIT_SHIFT) /* (n)xHCLK n=2..256 */ - -#define FSMC_PIO4_IOHOLD_SHIFT (16) /* IO memory hold time */ -#define FSMC_PIO4_IOHOLD_MASK (255 << FSMC_PIO4_IOHOLD_SHIFT) -# define FSMC_PIO4_IOHOLD(n) ((n) << FSMC_PIO4_IOHOLD_SHIFT) /* (n)xHCLK n=1..255 */ - -#define FSMC_PIO4_IOHIZ_SHIFT (24) /* IO memory databus HiZ time */ -#define FSMC_PIO4_IOHIZ_MASK (255 << FSMC_PIO4_IOHIZ_SHIFT) -# define FSMC_PIO4_IOHIZ(n) ((n) << FSMC_PIO4_IOHIZ_SHIFT) /* (n)xHCLK n=0..255 */ - -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_FMSC_H */ diff --git a/arch/arm/src/stm32/hardware/stm32_i2c.h b/arch/arm/src/stm32/hardware/stm32_i2c.h deleted file mode 100644 index 18c5f75cfa51f..0000000000000 --- a/arch/arm/src/stm32/hardware/stm32_i2c.h +++ /dev/null @@ -1,43 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/hardware/stm32_i2c.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_I2C_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_I2C_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -/* There are 2 main types of I2C IP cores among STM32 chips: - * 1. STM32 I2C IPv1 - F1, F2, F4 and L1 - * 2. STM32 I2C IPv2 - F0, F3, F7, G0, G4, H7, L0 and L4 - */ - -#if defined(CONFIG_STM32_HAVE_IP_I2C_V1) -# include "stm32_i2c_v1.h" -#elif defined(CONFIG_STM32_HAVE_IP_I2C_V2) -# include "stm32_i2c_v2.h" -#else -# error STM32 I2C IP version not specified -#endif - -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_I2C_H */ diff --git a/arch/arm/src/stm32/hardware/stm32_ltdc.h b/arch/arm/src/stm32/hardware/stm32_ltdc.h deleted file mode 100644 index 3d7b9fd3d0233..0000000000000 --- a/arch/arm/src/stm32/hardware/stm32_ltdc.h +++ /dev/null @@ -1,368 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/hardware/stm32_ltdc.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_LTDC_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_LTDC_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include "hardware/stm32_memorymap.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#define STM32_LTDC_NCLUT 256 /* Number of entries in the CLUTs */ - -/* LCDC Register Offsets ****************************************************/ - -#define STM32_LTDC_SSCR_OFFSET 0x0008 /* LTDC Synchronization Size Config Register */ -#define STM32_LTDC_BPCR_OFFSET 0x000c /* LTDC Back Porch Configuration Register */ -#define STM32_LTDC_AWCR_OFFSET 0x0010 /* LTDC Active Width Configuration Register */ -#define STM32_LTDC_TWCR_OFFSET 0x0014 /* LTDC Total Width Configuration Register */ -#define STM32_LTDC_GCR_OFFSET 0x0018 /* LTDC Global Control Register */ - /* 0x0020 Reserved */ -#define STM32_LTDC_SRCR_OFFSET 0x0024 /* LTDC Shadow Reload Configuration Register */ - /* 0x0028 Reserved */ -#define STM32_LTDC_BCCR_OFFSET 0x002c /* LTDC Background Color Configuration Register */ - /* 0x0030 Reserved */ -#define STM32_LTDC_IER_OFFSET 0x0034 /* LTDC Interrupt Enable Register */ -#define STM32_LTDC_ISR_OFFSET 0x0038 /* LTDC Interrupt Status Register */ -#define STM32_LTDC_ICR_OFFSET 0x003c /* LTDC Interrupt Clear Register */ -#define STM32_LTDC_LIPCR_OFFSET 0x0040 /* LTDC Line Interrupt Position Config Register */ -#define STM32_LTDC_CPSR_OFFSET 0x0044 /* LTDC Current Position Status Register */ -#define STM32_LTDC_CDSR_OFFSET 0x0048 /* LTDC Current Display Status Register */ - /* 0x004c-0x0080 Reserved */ - -#define STM32_LTDC_L1CR_OFFSET 0x0084 /* LTDC Layer 1 Control Register */ -#define STM32_LTDC_L1WHPCR_OFFSET 0x0088 /* LTDC Layer 1 Window Horiz Pos Config Register */ -#define STM32_LTDC_L1WVPCR_OFFSET 0x008c /* LTDC Layer 1 Window Vert Pos Config Register */ -#define STM32_LTDC_L1CKCR_OFFSET 0x0090 /* LTDC Layer 1 Color Keying Config Register */ -#define STM32_LTDC_L1PFCR_OFFSET 0x0094 /* LTDC Layer 1 Pixel Format Configuration Register */ -#define STM32_LTDC_L1CACR_OFFSET 0x0098 /* LTDC Layer 1 Constant Alpha Config Register */ -#define STM32_LTDC_L1DCCR_OFFSET 0x009c /* LTDC Layer 1 Default Color Config Register */ -#define STM32_LTDC_L1BFCR_OFFSET 0x00a0 /* LTDC Layer 1 Blending Factors Config Register */ - /* 0x00A4-0x00A8 Reserved */ -#define STM32_LTDC_L1CFBAR_OFFSET 0x00ac /* LTDC Layer 1 Color Frame Buffer Address Register */ -#define STM32_LTDC_L1CFBLR_OFFSET 0x00b0 /* LTDC Layer 1 Color Frame Buffer Length Register */ -#define STM32_LTDC_L1CFBLNR_OFFSET 0x00b4 /* LTDC Layer 1 Color Frame Buffer Line Number Register */ - /* 0x00B8-0x00C0 Reserved */ -#define STM32_LTDC_L1CLUTWR_OFFSET 0x00c4 /* LTDC Layer 1 CLUT Write Register */ - /* 0x00C8-0x0100 Reserved */ -#define STM32_LTDC_L2CR_OFFSET 0x0104 /* LTDC Layer 2 Control Register */ -#define STM32_LTDC_L2WHPCR_OFFSET 0x0108 /* LTDC Layer 2 Window Horiz Pos Config Register */ -#define STM32_LTDC_L2WVPCR_OFFSET 0x010c /* LTDC Layer 2 Window Vert Pos Config Register */ -#define STM32_LTDC_L2CKCR_OFFSET 0x0110 /* LTDC Layer 2 Color Keying Config Register */ -#define STM32_LTDC_L2PFCR_OFFSET 0x0114 /* LTDC Layer 2 Pixel Format Configuration Register */ -#define STM32_LTDC_L2CACR_OFFSET 0x0118 /* LTDC Layer 2 Constant Alpha Config Register */ -#define STM32_LTDC_L2DCCR_OFFSET 0x011c /* LTDC Layer 2 Default Color Config Register */ -#define STM32_LTDC_L2BFCR_OFFSET 0x0120 /* LTDC Layer 2 Blending Factors Config Register */ - /* 0x0124-0x0128 Reserved */ -#define STM32_LTDC_L2CFBAR_OFFSET 0x012c /* LTDC Layer 2 Color Frame Buffer Address Register */ -#define STM32_LTDC_L2CFBLR_OFFSET 0x0130 /* LTDC Layer 2 Color Frame Buffer Length Register */ -#define STM32_LTDC_L2CFBLNR_OFFSET 0x0134 /* LTDC Layer 2 Color Frame Buffer Line Number Register */ - /* 0x0138-0x0130 Reserved */ -#define STM32_LTDC_L2CLUTWR_OFFSET 0x0144 /* LTDC Layer 2 CLUT Write Register */ - /* 0x0148-0x03ff Reserved */ - -/* LTDC Register Addresses **************************************************/ - -#define STM32_LTDC_SSCR (STM32_LTDC_BASE + STM32_LTDC_SSCR_OFFSET) -#define STM32_LTDC_BPCR (STM32_LTDC_BASE + STM32_LTDC_BPCR_OFFSET) -#define STM32_LTDC_AWCR (STM32_LTDC_BASE + STM32_LTDC_AWCR_OFFSET) -#define STM32_LTDC_TWCR (STM32_LTDC_BASE + STM32_LTDC_TWCR_OFFSET) -#define STM32_LTDC_GCR (STM32_LTDC_BASE + STM32_LTDC_GCR_OFFSET) -#define STM32_LTDC_SRCR (STM32_LTDC_BASE + STM32_LTDC_SRCR_OFFSET) -#define STM32_LTDC_BCCR (STM32_LTDC_BASE + STM32_LTDC_BCCR_OFFSET) -#define STM32_LTDC_IER (STM32_LTDC_BASE + STM32_LTDC_IER_OFFSET) -#define STM32_LTDC_ISR (STM32_LTDC_BASE + STM32_LTDC_ISR_OFFSET) -#define STM32_LTDC_ICR (STM32_LTDC_BASE + STM32_LTDC_ICR_OFFSET) -#define STM32_LTDC_LIPCR (STM32_LTDC_BASE + STM32_LTDC_LIPCR_OFFSET) -#define STM32_LTDC_CPSR (STM32_LTDC_BASE + STM32_LTDC_CPSR_OFFSET) -#define STM32_LTDC_CDSR (STM32_LTDC_BASE + STM32_LTDC_CDSR_OFFSET) - -#define STM32_LTDC_L1CR (STM32_LTDC_BASE + STM32_LTDC_L1CR_OFFSET) -#define STM32_LTDC_L1WHPCR (STM32_LTDC_BASE + STM32_LTDC_L1WHPCR_OFFSET) -#define STM32_LTDC_L1WVPCR (STM32_LTDC_BASE + STM32_LTDC_L1WVPCR_OFFSET) -#define STM32_LTDC_L1CKCR (STM32_LTDC_BASE + STM32_LTDC_L1CKCR_OFFSET) -#define STM32_LTDC_L1PFCR (STM32_LTDC_BASE + STM32_LTDC_L1PFCR_OFFSET) -#define STM32_LTDC_L1CACR (STM32_LTDC_BASE + STM32_LTDC_L1CACR_OFFSET) -#define STM32_LTDC_L1DCCR (STM32_LTDC_BASE + STM32_LTDC_L1DCCR_OFFSET) -#define STM32_LTDC_L1BFCR (STM32_LTDC_BASE + STM32_LTDC_L1BFCR_OFFSET) -#define STM32_LTDC_L1CFBAR (STM32_LTDC_BASE + STM32_LTDC_L1CFBAR_OFFSET) -#define STM32_LTDC_L1CFBLR (STM32_LTDC_BASE + STM32_LTDC_L1CFBLR_OFFSET) -#define STM32_LTDC_L1CFBLNR (STM32_LTDC_BASE + STM32_LTDC_L1CFBLNR_OFFSET) -#define STM32_LTDC_L1CLUTWR (STM32_LTDC_BASE + STM32_LTDC_L1CLUTWR_OFFSET) - -#define STM32_LTDC_L2CR (STM32_LTDC_BASE + STM32_LTDC_L2CR_OFFSET) -#define STM32_LTDC_L2WHPCR (STM32_LTDC_BASE + STM32_LTDC_L2WHPCR_OFFSET) -#define STM32_LTDC_L2WVPCR (STM32_LTDC_BASE + STM32_LTDC_L2WVPCR_OFFSET) -#define STM32_LTDC_L2CKCR (STM32_LTDC_BASE + STM32_LTDC_L2CKCR_OFFSET) -#define STM32_LTDC_L2PFCR (STM32_LTDC_BASE + STM32_LTDC_L2PFCR_OFFSET) -#define STM32_LTDC_L2CACR (STM32_LTDC_BASE + STM32_LTDC_L2CACR_OFFSET) -#define STM32_LTDC_L2DCCR (STM32_LTDC_BASE + STM32_LTDC_L2DCCR_OFFSET) -#define STM32_LTDC_L2BFCR (STM32_LTDC_BASE + STM32_LTDC_L2BFCR_OFFSET) -#define STM32_LTDC_L2CFBAR (STM32_LTDC_BASE + STM32_LTDC_L2CFBAR_OFFSET) -#define STM32_LTDC_L2CFBLR (STM32_LTDC_BASE + STM32_LTDC_L2CFBLR_OFFSET) -#define STM32_LTDC_L2CFBLNR (STM32_LTDC_BASE + STM32_LTDC_L2CFBLNR_OFFSET) -#define STM32_LTDC_L2CLUTWR (STM32_LTDC_BASE + STM32_LTDC_L2CLUTWR_OFFSET) - -/* LTDC Register Bit Definitions ********************************************/ - -/* LTDC Synchronization Size Configuration Register */ - -#define LTDC_SSCR_VSH_SHIFT (0) /* Bits 0-10: Vertical Sync Height (scan lines) */ -#define LTDC_SSCR_VSH_MASK (0x7ff << LTDC_SSCR_VSH_SHIFT) -# define LTDC_SSCR_VSH(n) ((uint32_t)(n) << LTDC_SSCR_VSH_SHIFT) -#define LTDC_SSCR_HSW_SHIFT (16) /* Bits 16-27: Horizontal Sync Width (pixel clocks) */ -#define LTDC_SSCR_HSW_MASK (0xfff << LTDC_SSCR_HSW_SHIFT) -# define LTDC_SSCR_HSW(n) ((uint32_t)(n) << LTDC_SSCR_HSW_SHIFT) - -/* LTDC Back Porch Configuration Register */ - -#define LTDC_BPCR_AVBP_SHIFT (0) /* Bits 0-10: Accumulated Vertical back porch (scan lines) */ -#define LTDC_BPCR_AVBP_MASK (0x7ff << LTDC_BPCR_AVBP_SHIFT) -# define LTDC_BPCR_AVBP(n) ((uint32_t)(n) << LTDC_BPCR_AVBP_SHIFT) -#define LTDC_BPCR_AHBP_SHIFT (16) /* Bits 16-27: Accumulated Horizontal back porch (pixel clocks) */ -#define LTDC_BPCR_AHBP_MASK (0xfff << LTDC_BPCR_AVBP_SHIFT) -# define LTDC_BPCR_AHBP(n) ((uint32_t)(n) << LTDC_BPCR_AHBP_SHIFT) - -/* LTDC Active Width Configuration Register */ - -#define LTDC_AWCR_AAH_SHIFT (0) /* Bits 0-10: Accumulated Active Height (scan lines) */ -#define LTDC_AWCR_AAH_MASK (0x7ff << LTDC_AWCR_AAH_SHIFT) -# define LTDC_AWCR_AAH(n) ((uint32_t)(n) << LTDC_AWCR_AAH_SHIFT) -#define LTDC_AWCR_AAW_SHIFT (16) /* Bits 16-27: Accumulated Active Width (pixel clocks) */ -#define LTDC_AWCR_AAW_MASK (0xfff << LTDC_AWCR_AAW_SHIFT) -# define LTDC_AWCR_AAW(n) ((uint32_t)(n) << LTDC_AWCR_AAW_SHIFT) - -/* LTDC Total Width Configuration Register */ - -#define LTDC_TWCR_TOTALH_SHIFT (0) /* Bits 0-10: Total Height (scan lines) */ -#define LTDC_TWCR_TOTALH_MASK (0x7ff << LTDC_TWCR_TOTALH_SHIFT) -# define LTDC_TWCR_TOTALH(n) ((uint32_t)(n) << LTDC_TWCR_TOTALH_SHIFT) -#define LTDC_TWCR_TOTALW_SHIFT (16) /* Bits 16-27: Total Width (pixel clocks) */ -#define LTDC_TWCR_TOTALW_MASK (0xfff << LTDC_TWCR_TOTALW_SHIFT) -# define LTDC_TWCR_TOTALW(n) ((uint32_t)(n) << LTDC_TWCR_TOTALW_SHIFT) - -/* LTDC Global Control Register */ - -#define LTDC_GCR_LTDCEN (1 << 0) /* Bit 0: LCD-TFT Controller Enable Bit */ -#define LTDC_GCR_DBW_SHIFT (4) /* Bits 4-6: Dither Blue Width */ -#define LTDC_GCR_DBW_MASK (0x7 << LTDC_GCR_DBW_SHIFT) -# define LTDC_GCR_DBW(n) ((uint32_t)(n) << LTDC_GCR_DBW_SHIFT) -#define LTDC_GCR_DGW_SHIFT (8) /* Bits 8-10: Dither Green Width */ -#define LTDC_GCR_DGW_MASK (0x7 << LTDC_GCR_DGW_SHIFT) -# define LTDC_GCR_DGW(n) ((uint32_t)(n) << LTDC_GCR_DGW_SHIFT) -#define LTDC_GCR_DRW_SHIFT (12) /* Bits 12-14: Dither Red Width */ -#define LTDC_GCR_DRW_MASK (0x7 << LTDC_GCR_DRW_SHIFT) -# define LTDC_GCR_DRW(n) ((uint32_t)(n) << LTDC_GCR_DRW_SHIFT) -#define LTDC_GCR_DEN (1 << 16) /* Bit 16: Dither Enable */ -#define LTDC_GCR_PCPOL (1 << 28) /* Bit 28: Pixel Clock Polarity */ -#define LTDC_GCR_DEPOL (1 << 29) /* Bit 29: Data Enable Polarity */ -#define LTDC_GCR_VSPOL (1 << 30) /* Bit 30: Vertical Sync Polarity */ -#define LTDC_GCR_HSPOL (1 << 31) /* Bit 31: Horizontal Sync Polarity */ - -/* LTDC Shadow Reload Configuration Register */ - -#define LTDC_SRCR_IMR (1 << 0) /* Bit 0: Immediate Reload */ -#define LTDC_SRCR_VBR (1 << 1) /* Bit 1: Vertical Blanking Reload */ - -/* LTDC Background Color Configuration Register */ - -#define LTDC_BCCR_BCBLUE_SHIFT (0) /* Bits 0-7: Background Color Blue Value */ -#define LTDC_BCCR_BCBLUE_MASK (0xff << LTDC_BCCR_BCBLUE_SHIFT) -# define LTDC_BCCR_BCBLUE(n) ((uint32_t)(n) << LTDC_BCCR_BCBLUE_SHIFT) -#define LTDC_BCCR_BCGREEN_SHIFT (8) /* Bits 8-15: Background Color Green Value */ -#define LTDC_BCCR_BCGREEN_MASK (0xff << LTDC_BCCR_BCGREEN_SHIFT) -# define LTDC_BCCR_BCGREEN(n) ((uint32_t)(n) << LTDC_BCCR_BCGREEN_SHIFT) -#define LTDC_BCCR_BCRED_SHIFT (16) /* Bits 16-23: Background Color Red Value */ -#define LTDC_BCCR_BCRED_MASK (0xff << LTDC_BCCR_BCRED_SHIFT) -# define LTDC_BCCR_BCRED(n) ((uint32_t)(n) << LTDC_BCCR_BCRED_SHIFT) - -/* LTDC Interrupt Enable Register */ - -#define LTDC_IER_LIE (1 << 0) /* Bit 0: Line Interrupt Enable */ -#define LTDC_IER_FUIE (1 << 1) /* Bit 1: FIFO Underrun Interrupt Enable */ -#define LTDC_IER_TERRIE (1 << 2) /* Bit 2: Transfer Error Interrupt Enable */ -#define LTDC_IER_RRIE (1 << 3) /* Bit 3: Register Reload Interrupt Enable */ - -/* LTDC Interrupt Status Register */ - -#define LTDC_ISR_LIF (1 << 0) /* Bit 0: Line Interrupt Flag */ -#define LTDC_ISR_FUIF (1 << 1) /* Bit 1: FIFO Underrun Interrupt Flag */ -#define LTDC_IER_TERRIF (1 << 2) /* Bit 2: Transfer Error Interrupt Flag */ -#define LTDC_ISR_RRIF (1 << 3) /* Bit 3: Register Reload Interrupt Flag */ - -/* LTDC Interrupt Clear Register */ - -#define LTDC_ICR_CLIF (1 << 0) /* Bit 0: Clear Line Interrupt Flag */ -#define LTDC_ICR_CFUIF (1 << 1) /* Bit 1: Clear FIFO Underrun Interrupt Flag */ -#define LTDC_ICR_CTERRIF (1 << 2) /* Bit 2: Clear Transfer Error Interrupt Flag */ -#define LTDC_ICR_CRRIF (1 << 3) /* Bit 3: Clear Register Reload Interrupt Flag */ - -/* LTDC Line Interrupt Posittion Configuration Register */ - -#define LTDC_LIPCR_LIPOS_SHIFT (0) /* Bits 0-10: Line Interrupt Position */ -#define LTDC_LIPCR_LIPOS_MASK (0x7ff << LTDC_LIPCR_LIPOS_SHIFT) -# define LTDC_LIPCR_LIPOS(n) ((uint32_t)(n) << LTDC_LIPCR_LIPOS_SHIFT) - -/* LTDC Current Position Status Register */ - -#define LTDC_CPSR_CYPOS_SHIFT (0) /* Bits 0-15: Current Y Position */ -#define LTDC_CPSR_CYPOS_MASK (0xffff << LTDC_CPSR_CYPOS_SHIFT) -# define LTDC_CPSR_CYPOS(n) ((uint32_t)(n) << LTDC_CPSR_CYPOS_SHIFT) -#define LTDC_CPSR_CXPOS_SHIFT (16) /* Bits 15-31: Current X Position */ -#define LTDC_CPSR_CXPOS_MASK (0xffff << LTDC_CPSR_CXPOS_SHIFT) -# define LTDC_CPSR_CXPOS(n) ((uint32_t)(n) << LTDC_CPSR_CXPOS_SHIFT) - -/* LTDC Current Display Status Register */ - -#define LTDC_CDSR_VDES (1 << 0) /* Bit 0: Vertical Data Enable display Status */ -#define LTDC_CDSR_HDES (1 << 1) /* Bit 1: Horizontal Data Enable display Status */ -#define LTDC_CDSR_VSYNCS (1 << 2) /* Bit 2: Vertical Sync display Status */ -#define LTDC_CDSR_HSYNCS (1 << 3) /* Bit 3: Horizontal Sync display Status */ - -/* LTDC Layer x Control Register */ - -#define LTDC_LXCR_LEN (1 << 0) /* Bit 0: Layer Enable */ -#define LTDC_LXCR_COLKEN (1 << 1) /* Bit 1: Color Keying Enable */ -#define LTDC_LXCR_CLUTEN (1 << 4) /* Bit 4: Color Look-Up Table Enable */ - -/* LTDC Layer x Window Horizontal Position Configuration Register */ - -#define LTDC_LXWHPCR_WHSTPOS_SHIFT (0) /* Bits 0-11: Window Horizontal Start Position */ -#define LTDC_LXWHPCR_WHSTPOS_MASK (0xFFF << LTDC_LXWHPCR_WHSTPOS_SHIFT) -# define LTDC_LXWHPCR_WHSTPOS(n) ((uint32_t)(n) << LTDC_LXWHPCR_WHSTPOS_SHIFT) -#define LTDC_LXWHPCR_WHSPPOS_SHIFT (16) /* Bits 16-27: Window Horizontal Stop Position */ -#define LTDC_LXWHPCR_WHSPPOS_MASK (0xFFF << LTDC_LXWHPCR_WHSPPOS_SHIFT) -# define LTDC_LXWHPCR_WHSPPOS(n) ((uint32_t)(n) << LTDC_LXWHPCR_WHSPPOS_SHIFT) - -/* LTDC Layer x Window Vertical Position Configuration Register */ - -#define LTDC_LXWVPCR_WVSTPOS_SHIFT (0) /* Bits 0-10: Window Vertical Start Position */ -#define LTDC_LXWVPCR_WVSTPOS_MASK (0x7ff << LTDC_LXWVPCR_WVSTPOS_SHIFT) -# define LTDC_LXWVPCR_WVSTPOS(n) ((uint32_t)(n) << LTDC_LXWVPCR_WVSTPOS_SHIFT) -#define LTDC_LXWVPCR_WVSPPOS_SHIFT (16) /* Bits 16-26: Window Vertical Stop Position */ -#define LTDC_LXWVPCR_WVSPPOS_MASK (0x7ff << LTDC_LXWVPCR_WVSPPOS_SHIFT) -# define LTDC_LXWVPCR_WVSPPOS(n) ((uint32_t)(n) << LTDC_LXWVPCR_WVSPPOS_SHIFT) - -/* LTDC Layer x Color Keying Configuration Register */ - -#define LTDC_LXCKCR_CKBLUE_SHIFT (0) /* Bits 0-7: Color Key Blue Value */ -#define LTDC_LXCKCR_CKBLUE_MASK (0xff << LTDC_LXCKCR_CKBLUE_SHIFT) -# define LTDC_LXCKCR_CKBLUE(n) ((uint32_t)(n) << LTDC_LXCKCR_CKBLUE_SHIFT) -#define LTDC_LXCKCR_CKGREEN_SHIFT (8) /* Bits 8-15: Color Key Green Value */ -#define LTDC_LXCKCR_CKGREEN_MASK (0xff << LTDC_LXCKCR_CKGREEN_SHIFT) -# define LTDC_LXCKCR_CKGREEN(n) ((uint32_t)(n) << LTDC_LXCKCR_CKGREEN_SHIFT) -#define LTDC_LXCKCR_CKRED_SHIFT (16) /* Bits 16-23: Color Key Red Value */ -#define LTDC_LXCKCR_CKRED_MASK (0xff << LTDC_LXCKCR_CKRED_SHIFT) -# define LTDC_LXCKCR_CKRED(n) ((uint32_t)(n) << LTDC_LXCKCR_CKRED_SHIFT) - -/* LTDC Layer x Pixel Format Configuration Register */ - -#define LTDC_LXPFCR_PF_SHIFT (0) /* Bits 0-2: Pixel Format */ -#define LTDC_LXPFCR_PF_MASK (0x7 << LTDC_LXPFCR_PF_SHIFT) -# define LTDC_LXPFCR_PF(n) ((uint32_t)(n) << LTDC_LXPFCR_PF_SHIFT) - -#define LTDC_PF_ARGB8888 0 -#define LTDC_PF_RGB888 1 -#define LTDC_PF_RGB565 2 -#define LTDC_PF_ARGB1555 3 -#define LTDC_PF_ARGB4444 4 -#define LTDC_PF_L8 5 /* 8-bit Luninance (CLUT lookup) */ -#define LTDC_PF_AL44 6 /* 4-bit Alpha, 4-bit Luminance */ -#define LTDC_PF_AL88 7 /* 8-bit Alpha, 8-bit Luminance */ - -/* LTDC Layer x Constant Alpha Configuration Register */ - -#define LTDC_LXCACR_CONSTA_SHIFT (0) /* Bits 0-7: Constant Alpha */ -#define LTDC_LXCACR_CONSTA_MASK (0x7 << LTDC_LXCACR_CONSTA_SHIFT) -# define LTDC_LXCACR_CONSTA(n) ((uint32_t)(n) << LTDC_LXCACR_CONSTA_SHIFT) - -/* LTDC Layer x Default Color Configuration Register */ - -#define LTDC_LXDCCR_DCBLUE_SHIFT (0) /* Bits 0-7: Default Color Blue Value */ -#define LTDC_LXDCCR_DCBLUE_MASK (0xff << LTDC_LXDCCR_DCBLUE_SHIFT) -# define LTDC_LXDCCR_DCBLUE(n) ((uint32_t)(n) << LTDC_LXDCCR_DCBLUE_SHIFT) -#define LTDC_LXDCCR_DCGREEN_SHIFT (8) /* Bits 8-15: Default Color Green Value */ -#define LTDC_LXDCCR_DCGREEN_MASK (0xff << LTDC_LXDCCR_DCGREEN_SHIFT) -# define LTDC_LXDCCR_DCGREEN(n) ((uint32_t)(n) << LTDC_LXDCCR_DCGREEN_SHIFT) -#define LTDC_LXDCCR_DCRED_SHIFT (16) /* Bits 16-23: Default Color Red Value */ -#define LTDC_LXDCCR_DCRED_MASK (0xff << LTDC_LXDCCR_DCRED_SHIFT) -# define LTDC_LXDCCR_DCRED(n) ((uint32_t)(n) << LTDC_LXDCCR_DCRED_SHIFT) -#define LTDC_LXDCCR_DCALPHA_SHIFT (24) /* Bits 24-31: Default Color Alpha Value */ -#define LTDC_LXDCCR_DCALPHA_MASK (0xff << LTDC_LXDCCR_DCALPHA_SHIFT) -# define LTDC_LXDCCR_DCALPHA(n) ((uint32_t)(n) << LTDC_LXDCCR_DCALPHA_SHIFT) - -/* LTDC Layer x Blending Factors Configuration Register */ - -#define LTDC_LXBFCR_BF2_SHIFT (0) /* Bits 0-2: Blending Factor 2 */ -#define LTDC_LXBFCR_BF2_MASK (0x7 << LTDC_LXBFCR_BF2_SHIFT) -# define LTDC_LXBFCR_BF2(n) ((uint32_t)(n) << LTDC_LXBFCR_BF2_SHIFT) -#define LTDC_LXBFCR_BF1_SHIFT (8) /* Bits 8-10: Blending Factor 1 */ -#define LTDC_LXBFCR_BF1_MASK (0x7 << LTDC_LXBFCR_BF1_SHIFT) -# define LTDC_LXBFCR_BF1(n) ((uint32_t)(n) << LTDC_LXBFCR_BF1_SHIFT) - -#define LTDC_BF1_CONST_ALPHA 0x04 /* Constant Alpha */ -#define LTDC_BF1_PIXEL_ALPHA 0x06 /* Pixel Alpha x Constant Alpha */ -#define LTDC_BF2_CONST_ALPHA 0x05 /* Constant Alpha */ -#define LTDC_BF2_PIXEL_ALPHA 0x07 /* Pixel Alpha x Constant Alpha */ - -/* LTDC Layer x Color Frame Buffer Length Configuration Register */ - -#define LTDC_LXCFBLR_CFBLL_SHIFT (0) /* Bits 0-12: Color Frame Buffer Line Length */ -#define LTDC_LXCFBLR_CFBLL_MASK (0x1fff << LTDC_LXCFBLR_CFBLL_SHIFT) -# define LTDC_LXCFBLR_CFBLL(n) ((uint32_t)(n) << LTDC_LXCFBLR_CFBLL_SHIFT) -#define LTDC_LXCFBLR_CFBP_SHIFT (16) /* Bits 16-28: Color Frame Buffer Pitch */ -#define LTDC_LXCFBLR_CFBP_MASK (0x1fff << LTDC_LXCFBLR_CFBP_SHIFT) -# define LTDC_LXCFBLR_CFBP(n) ((uint32_t)(n) << LTDC_LXCFBLR_CFBP_SHIFT) - -/* LTDC Layer x Color Frame Buffer Line Number Register */ - -#define LTDC_LXCFBLNR_LN_SHIFT (0) /* Bits 0-10: Color Frame Buffer Line Number */ -#define LTDC_LXCFBLNR_LN_MASK (0x7ff << LTDC_LXCFBLNR_LN_SHIFT) -# define LTDC_LXCFBLNR_LN(n) ((uint32_t)(n) << LTDC_LXCFBLNR_LN_SHIFT) - -/* LTDC Layer x CLUT Write Register */ - -#define LTDC_LXCLUTWR_BLUE_SHIFT (0) /* Bits 0-7: Default Color Blue Value */ -#define LTDC_LXCLUTWR_BLUE_MASK (0xff << LTDC_LXCLUTWR_BLUE_SHIFT) -# define LTDC_LXCLUTWR_BLUE(n) ((uint32_t)(n) << LTDC_LXCLUTWR_BLUE_SHIFT) -#define LTDC_LXCLUTWR_GREEN_SHIFT (8) /* Bits 8-15: Default Color Green Value */ -#define LTDC_LXCLUTWR_GREEN_MASK (0xff << LTDC_LXCLUTWR_GREEN_SHIFT) -# define LTDC_LXCLUTWR_GREEN(n) ((uint32_t)(n) << LTDC_LXCLUTWR_GREEN_SHIFT) -#define LTDC_LXCLUTWR_RED_SHIFT (16) /* Bits 16-23: Default Color Red Value */ -#define LTDC_LXCLUTWR_RED_MASK (0xff << LTDC_LXCLUTWR_RED_SHIFT) -# define LTDC_LXCLUTWR_RED(n) ((uint32_t)(n) << LTDC_LXCLUTWR_RED_SHIFT) -#define LTDC_LXCLUTWR_CLUTADD_SHIFT (24) /* Bits 24-31: CLUT Address */ -#define LTDC_LXCLUTWR_CLUTADD_MASK (0xff << LTDC_LXCLUTWR_CLUTADD_SHIFT) -# define LTDC_LXCLUTWR_CLUTADD(n) ((uint32_t)(n) << LTDC_LXCLUTWR_CLUTADD_SHIFT) - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_LTDC_H */ diff --git a/arch/arm/src/stm32/hardware/stm32_memorymap.h b/arch/arm/src/stm32/hardware/stm32_memorymap.h deleted file mode 100644 index 5fd8733f4f660..0000000000000 --- a/arch/arm/src/stm32/hardware/stm32_memorymap.h +++ /dev/null @@ -1,53 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/hardware/stm32_memorymap.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_MEMORYMAP_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_MEMORYMAP_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include "chip.h" - -#if defined(CONFIG_STM32_STM32L15XX) -# include "hardware/stm32l15xxx_memorymap.h" -#elif defined(CONFIG_STM32_STM32F10XX) -# include "hardware/stm32f10xxx_memorymap.h" -#elif defined(CONFIG_STM32_STM32F20XX) -# include "hardware/stm32f20xxx_memorymap.h" -#elif defined(CONFIG_STM32_STM32F30XX) -# include "hardware/stm32f30xxx_memorymap.h" -#elif defined(CONFIG_STM32_STM32F33XX) -# include "hardware/stm32f33xxx_memorymap.h" -#elif defined(CONFIG_STM32_STM32F37XX) -# include "hardware/stm32f37xxx_memorymap.h" -#elif defined(CONFIG_STM32_STM32F4XXX) -# include "hardware/stm32f40xxx_memorymap.h" -#elif defined(CONFIG_STM32_STM32G4XXX) -# include "hardware/stm32g4xxxx_memorymap.h" -#else -# error "Unsupported STM32 memory map" -#endif - -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_MEMORYMAP_H */ diff --git a/arch/arm/src/stm32/hardware/stm32_otghs.h b/arch/arm/src/stm32/hardware/stm32_otghs.h deleted file mode 100644 index 59583ad96997d..0000000000000 --- a/arch/arm/src/stm32/hardware/stm32_otghs.h +++ /dev/null @@ -1,1111 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/hardware/stm32_otghs.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_OTGHS_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_OTGHS_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include "chip.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* General definitions */ - -#define OTGHS_EPTYPE_CTRL (0) /* Control */ -#define OTGHS_EPTYPE_ISOC (1) /* Isochronous */ -#define OTGHS_EPTYPE_BULK (2) /* Bulk */ -#define OTGHS_EPTYPE_INTR (3) /* Interrupt */ - -#define OTGHS_PID_DATA0 (0) -#define OTGHS_PID_DATA2 (1) -#define OTGHS_PID_DATA1 (2) -#define OTGHS_PID_MDATA (3) /* Non-control */ -#define OTGHS_PID_SETUP (3) /* Control */ - -/* Register Offsets *********************************************************/ - -/* Core global control and status registers */ - -#define STM32_OTGHS_GOTGCTL_OFFSET 0x0000 /* Control and status register */ -#define STM32_OTGHS_GOTGINT_OFFSET 0x0004 /* Interrupt register */ -#define STM32_OTGHS_GAHBCFG_OFFSET 0x0008 /* AHB configuration register */ -#define STM32_OTGHS_GUSBCFG_OFFSET 0x000c /* USB configuration register */ -#define STM32_OTGHS_GRSTCTL_OFFSET 0x0010 /* Reset register */ -#define STM32_OTGHS_GINTSTS_OFFSET 0x0014 /* Core interrupt register */ -#define STM32_OTGHS_GINTMSK_OFFSET 0x0018 /* Interrupt mask register */ -#define STM32_OTGHS_GRXSTSR_OFFSET 0x001c /* Receive status debug read/OTG status read register */ -#define STM32_OTGHS_GRXSTSP_OFFSET 0x0020 /* Receive status debug read/OTG status pop register */ -#define STM32_OTGHS_GRXFSIZ_OFFSET 0x0024 /* Receive FIFO size register */ -#define STM32_OTGHS_HNPTXFSIZ_OFFSET 0x0028 /* Host non-periodic transmit FIFO size register */ -#define STM32_OTGHS_DIEPTXF0_OFFSET 0x0028 /* Endpoint 0 Transmit FIFO size */ -#define STM32_OTGHS_HNPTXSTS_OFFSET 0x002c /* Non-periodic transmit FIFO/queue status register */ -#define STM32_OTGHS_GCCFG_OFFSET 0x0038 /* general core configuration register */ -#define STM32_OTGHS_CID_OFFSET 0x003c /* Core ID register */ -#define STM32_OTGHS_HPTXFSIZ_OFFSET 0x0100 /* Host periodic transmit FIFO size register */ - -#define STM32_OTGHS_DIEPTXF_OFFSET(n) (0x0104+(((n)-1) << 2)) -#define STM32_OTGHS_DIEPTXF1_OFFSET 0x0104 /* Device IN endpoint transmit FIFO1 size register */ -#define STM32_OTGHS_DIEPTXF2_OFFSET 0x0108 /* Device IN endpoint transmit FIFO2 size register */ -#define STM32_OTGHS_DIEPTXF3_OFFSET 0x010c /* Device IN endpoint transmit FIFO3 size register */ - -/* Host-mode control and status registers */ - -#define STM32_OTGHS_HCFG_OFFSET 0x0400 /* Host configuration register */ -#define STM32_OTGHS_HFIR_OFFSET 0x0404 /* Host frame interval register */ -#define STM32_OTGHS_HFNUM_OFFSET 0x0408 /* Host frame number/frame time remaining register */ -#define STM32_OTGHS_HPTXSTS_OFFSET 0x0410 /* Host periodic transmit FIFO/queue status register */ -#define STM32_OTGHS_HAINT_OFFSET 0x0414 /* Host all channels interrupt register */ -#define STM32_OTGHS_HAINTMSK_OFFSET 0x0418 /* Host all channels interrupt mask register */ -#define STM32_OTGHS_HPRT_OFFSET 0x0440 /* Host port control and status register */ - -#define STM32_OTGHS_CHAN_OFFSET(n) (0x500 + ((n) << 5) -#define STM32_OTGHS_HCCHAR_CHOFFSET 0x0000 /* Host channel characteristics register */ -#define STM32_OTGHS_HCINT_CHOFFSET 0x0008 /* Host channel interrupt register */ -#define STM32_OTGHS_HCINTMSK_CHOFFSET 0x000c /* Host channel interrupt mask register */ -#define STM32_OTGHS_HCTSIZ_CHOFFSET 0x0010 /* Host channel interrupt register */ - -#define STM32_OTGHS_HCCHAR_OFFSET(n) (0x500 + ((n) << 5)) -#define STM32_OTGHS_HCCHAR0_OFFSET 0x0500 /* Host channel-0 characteristics register */ -#define STM32_OTGHS_HCCHAR1_OFFSET 0x0520 /* Host channel-1 characteristics register */ -#define STM32_OTGHS_HCCHAR2_OFFSET 0x0540 /* Host channel-2 characteristics register */ -#define STM32_OTGHS_HCCHAR3_OFFSET 0x0560 /* Host channel-3 characteristics register */ -#define STM32_OTGHS_HCCHAR4_OFFSET 0x0580 /* Host channel-4 characteristics register */ -#define STM32_OTGHS_HCCHAR5_OFFSET 0x05a0 /* Host channel-5 characteristics register */ -#define STM32_OTGHS_HCCHAR6_OFFSET 0x05c0 /* Host channel-6 characteristics register */ -#define STM32_OTGHS_HCCHAR7_OFFSET 0x05e0 /* Host channel-7 characteristics register */ -#define STM32_OTGHS_HCCHAR8_OFFSET 0x0600 /* Host channel-8 characteristics register */ -#define STM32_OTGHS_HCCHAR9_OFFSET 0x0620 /* Host channel-9 characteristics register */ -#define STM32_OTGHS_HCCHAR10_OFFSET 0x0640 /* Host channel-10 characteristics register */ -#define STM32_OTGHS_HCCHAR11_OFFSET 0x0660 /* Host channel-11 characteristics register */ - -#define STM32_OTGHS_HCINT_OFFSET(n) (0x508 + ((n) << 5)) -#define STM32_OTGHS_HCINT0_OFFSET 0x0508 /* Host channel-0 interrupt register */ -#define STM32_OTGHS_HCINT1_OFFSET 0x0528 /* Host channel-1 interrupt register */ -#define STM32_OTGHS_HCINT2_OFFSET 0x0548 /* Host channel-2 interrupt register */ -#define STM32_OTGHS_HCINT3_OFFSET 0x0568 /* Host channel-3 interrupt register */ -#define STM32_OTGHS_HCINT4_OFFSET 0x0588 /* Host channel-4 interrupt register */ -#define STM32_OTGHS_HCINT5_OFFSET 0x05a8 /* Host channel-5 interrupt register */ -#define STM32_OTGHS_HCINT6_OFFSET 0x05c8 /* Host channel-6 interrupt register */ -#define STM32_OTGHS_HCINT7_OFFSET 0x05e8 /* Host channel-7 interrupt register */ -#define STM32_OTGHS_HCINT8_OFFSET 0x0608 /* Host channel-8 interrupt register */ -#define STM32_OTGHS_HCINT9_OFFSET 0x0628 /* Host channel-9 interrupt register */ -#define STM32_OTGHS_HCINT10_OFFSET 0x0648 /* Host channel-10 interrupt register */ -#define STM32_OTGHS_HCINT11_OFFSET 0x0668 /* Host channel-11 interrupt register */ - -#define STM32_OTGHS_HCINTMSK_OFFSET(n) (0x50c + ((n) << 5)) -#define STM32_OTGHS_HCINTMSK0_OFFSET 0x050c /* Host channel-0 interrupt mask register */ -#define STM32_OTGHS_HCINTMSK1_OFFSET 0x052c /* Host channel-1 interrupt mask register */ -#define STM32_OTGHS_HCINTMSK2_OFFSET 0x054c /* Host channel-2 interrupt mask register */ -#define STM32_OTGHS_HCINTMSK3_OFFSET 0x056c /* Host channel-3 interrupt mask register */ -#define STM32_OTGHS_HCINTMSK4_OFFSET 0x058c /* Host channel-4 interrupt mask register */ -#define STM32_OTGHS_HCINTMSK5_OFFSET 0x05ac /* Host channel-5 interrupt mask register */ -#define STM32_OTGHS_HCINTMSK6_OFFSET 0x05cc /* Host channel-6 interrupt mask register */ -#define STM32_OTGHS_HCINTMSK7_OFFSET 0x05ec /* Host channel-7 interrupt mask register */ -#define STM32_OTGHS_HCINTMSK8_OFFSET 0x060c /* Host channel-8 interrupt mask register */ -#define STM32_OTGHS_HCINTMSK9_OFFSET 0x062c /* Host channel-9 interrupt mask register */ -#define STM32_OTGHS_HCINTMSK10_OFFSET 0x064c /* Host channel-10 interrupt mask register */ -#define STM32_OTGHS_HCINTMSK11_OFFSET 0x068c /* Host channel-11 interrupt mask register */ - -#define STM32_OTGHS_HCTSIZ_OFFSET(n) (0x510 + ((n) << 5)) -#define STM32_OTGHS_HCTSIZ0_OFFSET 0x0510 /* Host channel-0 interrupt register */ -#define STM32_OTGHS_HCTSIZ1_OFFSET 0x0530 /* Host channel-1 interrupt register */ -#define STM32_OTGHS_HCTSIZ2_OFFSET 0x0550 /* Host channel-2 interrupt register */ -#define STM32_OTGHS_HCTSIZ3_OFFSET 0x0570 /* Host channel-3 interrupt register */ -#define STM32_OTGHS_HCTSIZ4_OFFSET 0x0590 /* Host channel-4 interrupt register */ -#define STM32_OTGHS_HCTSIZ5_OFFSET 0x05b0 /* Host channel-5 interrupt register */ -#define STM32_OTGHS_HCTSIZ6_OFFSET 0x05d0 /* Host channel-6 interrupt register */ -#define STM32_OTGHS_HCTSIZ7_OFFSET 0x06f0 /* Host channel-7 interrupt register */ -#define STM32_OTGHS_HCTSIZ8_OFFSET 0x0610 /* Host channel-8 interrupt register */ -#define STM32_OTGHS_HCTSIZ9_OFFSET 0x0630 /* Host channel-9 interrupt register */ -#define STM32_OTGHS_HCTSIZ10_OFFSET 0x0650 /* Host channel-10 interrupt register */ -#define STM32_OTGHS_HCTSIZ11_OFFSET 0x05f0 /* Host channel-11 interrupt register */ - -/* Device-mode control and status registers */ - -#define STM32_OTGHS_DCFG_OFFSET 0x0800 /* Device configuration register */ -#define STM32_OTGHS_DCTL_OFFSET 0x0804 /* Device control register */ -#define STM32_OTGHS_DSTS_OFFSET 0x0808 /* Device status register */ -#define STM32_OTGHS_DIEPMSK_OFFSET 0x0810 /* Device IN endpoint common interrupt mask register */ -#define STM32_OTGHS_DOEPMSK_OFFSET 0x0814 /* Device OUT endpoint common interrupt mask register */ -#define STM32_OTGHS_DAINT_OFFSET 0x0818 /* Device all endpoints interrupt register */ -#define STM32_OTGHS_DAINTMSK_OFFSET 0x081c /* All endpoints interrupt mask register */ -#define STM32_OTGHS_DVBUSDIS_OFFSET 0x0828 /* Device VBUS discharge time register */ -#define STM32_OTGHS_DVBUSPULSE_OFFSET 0x082c /* Device VBUS pulsing time register */ -#define STM32_OTGHS_DIEPEMPMSK_OFFSET 0x0834 /* Device IN endpoint FIFO empty interrupt mask register */ - -#define STM32_OTGHS_DIEP_OFFSET(n) (0x0900 + ((n) << 5)) -#define STM32_OTGHS_DIEPCTL_EPOFFSET 0x0000 /* Device endpoint control register */ -#define STM32_OTGHS_DIEPINT_EPOFFSET 0x0008 /* Device endpoint interrupt register */ -#define STM32_OTGHS_DIEPTSIZ_EPOFFSET 0x0010 /* Device IN endpoint transfer size register */ -#define STM32_OTGHS_DTXFSTS_EPOFFSET 0x0018 /* Device IN endpoint transmit FIFO status register */ - -#define STM32_OTGHS_DIEPCTL_OFFSET(n) (0x0900 + ((n) << 5)) -#define STM32_OTGHS_DIEPCTL0_OFFSET 0x0900 /* Device control IN endpoint 0 control register */ -#define STM32_OTGHS_DIEPCTL1_OFFSET 0x0920 /* Device control IN endpoint 2 control register */ -#define STM32_OTGHS_DIEPCTL2_OFFSET 0x0940 /* Device control IN endpoint 3 control register */ -#define STM32_OTGHS_DIEPCTL3_OFFSET 0x0960 /* Device control IN endpoint 4 control register */ - -#define STM32_OTGHS_DIEPINT_OFFSET(n) (0x0908 + ((n) << 5)) -#define STM32_OTGHS_DIEPINT0_OFFSET 0x0908 /* Device endpoint-0 interrupt register */ -#define STM32_OTGHS_DIEPINT1_OFFSET 0x0928 /* Device endpoint-1 interrupt register */ -#define STM32_OTGHS_DIEPINT2_OFFSET 0x0948 /* Device endpoint-2 interrupt register */ -#define STM32_OTGHS_DIEPINT3_OFFSET 0x0968 /* Device endpoint-3 interrupt register */ - -#define STM32_OTGHS_DIEPTSIZ_OFFSET(n) (0x910 + ((n) << 5)) -#define STM32_OTGHS_DIEPTSIZ0_OFFSET 0x0910 /* Device IN endpoint 0 transfer size register */ -#define STM32_OTGHS_DIEPTSIZ1_OFFSET 0x0930 /* Device IN endpoint 1 transfer size register */ -#define STM32_OTGHS_DIEPTSIZ2_OFFSET 0x0950 /* Device IN endpoint 2 transfer size register */ -#define STM32_OTGHS_DIEPTSIZ3_OFFSET 0x0970 /* Device IN endpoint 3 transfer size register */ - -#define STM32_OTGHS_DTXFSTS_OFFSET(n) (0x0918 + ((n) << 5)) -#define STM32_OTGHS_DTXFSTS0_OFFSET 0x0918 /* Device OUT endpoint-0 TxFIFO status register */ -#define STM32_OTGHS_DTXFSTS1_OFFSET 0x0938 /* Device OUT endpoint-1 TxFIFO status register */ -#define STM32_OTGHS_DTXFSTS2_OFFSET 0x0958 /* Device OUT endpoint-2 TxFIFO status register */ -#define STM32_OTGHS_DTXFSTS3_OFFSET 0x0978 /* Device OUT endpoint-3 TxFIFO status register */ - -#define STM32_OTGHS_DOEP_OFFSET(n) (0x0b00 + ((n) << 5)) -#define STM32_OTGHS_DOEPCTL_EPOFFSET 0x0000 /* Device control OUT endpoint 0 control register */ -#define STM32_OTGHS_DOEPINT_EPOFFSET 0x0008 /* Device endpoint-x interrupt register */ - -#define STM32_OTGHS_DOEPCTL_OFFSET(n) (0x0b00 + ((n) << 5)) -#define STM32_OTGHS_DOEPCTL0_OFFSET 0x00b00 /* Device OUT endpoint 0 control register */ -#define STM32_OTGHS_DOEPCTL1_OFFSET 0x00b20 /* Device OUT endpoint 1 control register */ -#define STM32_OTGHS_DOEPCTL2_OFFSET 0x00b40 /* Device OUT endpoint 2 control register */ -#define STM32_OTGHS_DOEPCTL3_OFFSET 0x00b60 /* Device OUT endpoint 3 control register */ - -#define STM32_OTGHS_DOEPINT_OFFSET(n) (0x0b08 + ((n) << 5)) -#define STM32_OTGHS_DOEPINT0_OFFSET 0x00b08 /* Device endpoint-0 interrupt register */ -#define STM32_OTGHS_DOEPINT1_OFFSET 0x00b28 /* Device endpoint-1 interrupt register */ -#define STM32_OTGHS_DOEPINT2_OFFSET 0x00b48 /* Device endpoint-2 interrupt register */ -#define STM32_OTGHS_DOEPINT3_OFFSET 0x00b68 /* Device endpoint-3 interrupt register */ - -#define STM32_OTGHS_DOEPTSIZ_OFFSET(n) (0x0b10 + ((n) << 5)) -#define STM32_OTGHS_DOEPTSIZ0_OFFSET 0x00b10 /* Device OUT endpoint-0 transfer size register */ -#define STM32_OTGHS_DOEPTSIZ1_OFFSET 0x00b30 /* Device OUT endpoint-1 transfer size register */ -#define STM32_OTGHS_DOEPTSIZ2_OFFSET 0x00b50 /* Device OUT endpoint-2 transfer size register */ -#define STM32_OTGHS_DOEPTSIZ3_OFFSET 0x00b70 /* Device OUT endpoint-3 transfer size register */ - -/* Power and clock gating registers */ - -#define STM32_OTGHS_PCGCCTL_OFFSET 0x0e00 /* Power and clock gating control register */ - -/* Data FIFO (DFIFO) access registers */ - -#define STM32_OTGHS_DFIFO_DEP_OFFSET(n) (0x1000 + ((n) << 12)) -#define STM32_OTGHS_DFIFO_HCH_OFFSET(n) (0x1000 + ((n) << 12)) - -#define STM32_OTGHS_DFIFO_DEP0_OFFSET 0x1000 /* 0x1000-0x1ffc Device IN/OUT Endpoint 0 DFIFO Write/Read Access */ -#define STM32_OTGHS_DFIFO_HCH0_OFFSET 0x1000 /* 0x1000-0x1ffc Host OUT/IN Channel 0 DFIFO Read/Write Access */ - -#define STM32_OTGHS_DFIFO_DEP1_OFFSET 0x2000 /* 0x2000-0x2ffc Device IN/OUT Endpoint 1 DFIFO Write/Read Access */ -#define STM32_OTGHS_DFIFO_HCH1_OFFSET 0x2000 /* 0x2000-0x2ffc Host OUT/IN Channel 1 DFIFO Read/Write Access */ - -#define STM32_OTGHS_DFIFO_DEP2_OFFSET 0x3000 /* 0x3000-0x3ffc Device IN/OUT Endpoint 2 DFIFO Write/Read Access */ -#define STM32_OTGHS_DFIFO_HCH2_OFFSET 0x3000 /* 0x3000-0x3ffc Host OUT/IN Channel 2 DFIFO Read/Write Access */ - -#define STM32_OTGHS_DFIFO_DEP3_OFFSET 0x4000 /* 0x4000-0x4ffc Device IN/OUT Endpoint 3 DFIFO Write/Read Access */ -#define STM32_OTGHS_DFIFO_HCH3_OFFSET 0x4000 /* 0x4000-0x4ffc Host OUT/IN Channel 3 DFIFO Read/Write Access */ - -/* Register Addresses *******************************************************/ - -#define STM32_OTGHS_GOTGCTL (STM32_OTGHS_BASE+STM32_OTGHS_GOTGCTL_OFFSET) -#define STM32_OTGHS_GOTGINT (STM32_OTGHS_BASE+STM32_OTGHS_GOTGINT_OFFSET) -#define STM32_OTGHS_GAHBCFG (STM32_OTGHS_BASE+STM32_OTGHS_GAHBCFG_OFFSET) -#define STM32_OTGHS_GUSBCFG (STM32_OTGHS_BASE+STM32_OTGHS_GUSBCFG_OFFSET) -#define STM32_OTGHS_GRSTCTL (STM32_OTGHS_BASE+STM32_OTGHS_GRSTCTL_OFFSET) -#define STM32_OTGHS_GINTSTS (STM32_OTGHS_BASE+STM32_OTGHS_GINTSTS_OFFSET) -#define STM32_OTGHS_GINTMSK (STM32_OTGHS_BASE+STM32_OTGHS_GINTMSK_OFFSET) -#define STM32_OTGHS_GRXSTSR (STM32_OTGHS_BASE+STM32_OTGHS_GRXSTSR_OFFSET) -#define STM32_OTGHS_GRXSTSP (STM32_OTGHS_BASE+STM32_OTGHS_GRXSTSP_OFFSET) -#define STM32_OTGHS_GRXFSIZ (STM32_OTGHS_BASE+STM32_OTGHS_GRXFSIZ_OFFSET) -#define STM32_OTGHS_HNPTXFSIZ (STM32_OTGHS_BASE+STM32_OTGHS_HNPTXFSIZ_OFFSET) -#define STM32_OTGHS_DIEPTXF0 (STM32_OTGHS_BASE+STM32_OTGHS_DIEPTXF0_OFFSET) -#define STM32_OTGHS_HNPTXSTS (STM32_OTGHS_BASE+STM32_OTGHS_HNPTXSTS_OFFSET) -#define STM32_OTGHS_GCCFG (STM32_OTGHS_BASE+STM32_OTGHS_GCCFG_OFFSET) -#define STM32_OTGHS_CID (STM32_OTGHS_BASE+STM32_OTGHS_CID_OFFSET) -#define STM32_OTGHS_HPTXFSIZ (STM32_OTGHS_BASE+STM32_OTGHS_HPTXFSIZ_OFFSET) - -#define STM32_OTGHS_DIEPTXF(n) (STM32_OTGHS_BASE+STM32_OTGHS_DIEPTXF_OFFSET(n)) -#define STM32_OTGHS_DIEPTXF1 (STM32_OTGHS_BASE+STM32_OTGHS_DIEPTXF1_OFFSET) -#define STM32_OTGHS_DIEPTXF2 (STM32_OTGHS_BASE+STM32_OTGHS_DIEPTXF2_OFFSET) -#define STM32_OTGHS_DIEPTXF3 (STM32_OTGHS_BASE+STM32_OTGHS_DIEPTXF3_OFFSET) - -/* Host-mode control and status registers */ - -#define STM32_OTGHS_HCFG (STM32_OTGHS_BASE+STM32_OTGHS_HCFG_OFFSET) -#define STM32_OTGHS_HFIR (STM32_OTGHS_BASE+STM32_OTGHS_HFIR_OFFSET) -#define STM32_OTGHS_HFNUM (STM32_OTGHS_BASE+STM32_OTGHS_HFNUM_OFFSET) -#define STM32_OTGHS_HPTXSTS (STM32_OTGHS_BASE+STM32_OTGHS_HPTXSTS_OFFSET) -#define STM32_OTGHS_HAINT (STM32_OTGHS_BASE+STM32_OTGHS_HAINT_OFFSET) -#define STM32_OTGHS_HAINTMSK (STM32_OTGHS_BASE+STM32_OTGHS_HAINTMSK_OFFSET) -#define STM32_OTGHS_HPRT (STM32_OTGHS_BASE+STM32_OTGHS_HPRT_OFFSET) - -#define STM32_OTGHS_CHAN(n) (STM32_OTGHS_BASE+STM32_OTGHS_CHAN_OFFSET(n)) - -#define STM32_OTGHS_HCCHAR(n) (STM32_OTGHS_BASE+STM32_OTGHS_HCCHAR_OFFSET(n)) -#define STM32_OTGHS_HCCHAR0 (STM32_OTGHS_BASE+STM32_OTGHS_HCCHAR0_OFFSET) -#define STM32_OTGHS_HCCHAR1 (STM32_OTGHS_BASE+STM32_OTGHS_HCCHAR1_OFFSET) -#define STM32_OTGHS_HCCHAR2 (STM32_OTGHS_BASE+STM32_OTGHS_HCCHAR2_OFFSET) -#define STM32_OTGHS_HCCHAR3 (STM32_OTGHS_BASE+STM32_OTGHS_HCCHAR3_OFFSET) -#define STM32_OTGHS_HCCHAR4 (STM32_OTGHS_BASE+STM32_OTGHS_HCCHAR4_OFFSET) -#define STM32_OTGHS_HCCHAR5 (STM32_OTGHS_BASE+STM32_OTGHS_HCCHAR5_OFFSET) -#define STM32_OTGHS_HCCHAR6 (STM32_OTGHS_BASE+STM32_OTGHS_HCCHAR6_OFFSET) -#define STM32_OTGHS_HCCHAR7 (STM32_OTGHS_BASE+STM32_OTGHS_HCCHAR7_OFFSET) -#define STM32_OTGHS_HCCHAR8 (STM32_OTGHS_BASE+STM32_OTGHS_HCCHAR8_OFFSET) -#define STM32_OTGHS_HCCHAR9 (STM32_OTGHS_BASE+STM32_OTGHS_HCCHAR9_OFFSET) -#define STM32_OTGHS_HCCHAR10 (STM32_OTGHS_BASE+STM32_OTGHS_HCCHAR10_OFFSET) -#define STM32_OTGHS_HCCHAR11 (STM32_OTGHS_BASE+STM32_OTGHS_HCCHAR11_OFFSET) - -#define STM32_OTGHS_HCINT(n) (STM32_OTGHS_BASE+STM32_OTGHS_HCINT_OFFSET(n)) -#define STM32_OTGHS_HCINT0 (STM32_OTGHS_BASE+STM32_OTGHS_HCINT0_OFFSET) -#define STM32_OTGHS_HCINT1 (STM32_OTGHS_BASE+STM32_OTGHS_HCINT1_OFFSET) -#define STM32_OTGHS_HCINT2 (STM32_OTGHS_BASE+STM32_OTGHS_HCINT2_OFFSET) -#define STM32_OTGHS_HCINT3 (STM32_OTGHS_BASE+STM32_OTGHS_HCINT3_OFFSET) -#define STM32_OTGHS_HCINT4 (STM32_OTGHS_BASE+STM32_OTGHS_HCINT4_OFFSET) -#define STM32_OTGHS_HCINT5 (STM32_OTGHS_BASE+STM32_OTGHS_HCINT5_OFFSET) -#define STM32_OTGHS_HCINT6 (STM32_OTGHS_BASE+STM32_OTGHS_HCINT6_OFFSET) -#define STM32_OTGHS_HCINT7 (STM32_OTGHS_BASE+STM32_OTGHS_HCINT7_OFFSET) -#define STM32_OTGHS_HCINT8 (STM32_OTGHS_BASE+STM32_OTGHS_HCINT8_OFFSET) -#define STM32_OTGHS_HCINT9 (STM32_OTGHS_BASE+STM32_OTGHS_HCINT9_OFFSET) -#define STM32_OTGHS_HCINT10 (STM32_OTGHS_BASE+STM32_OTGHS_HCINT10_OFFSET) -#define STM32_OTGHS_HCINT11 (STM32_OTGHS_BASE+STM32_OTGHS_HCINT11_OFFSET) - -#define STM32_OTGHS_HCINTMSK(n) (STM32_OTGHS_BASE+STM32_OTGHS_HCINTMSK_OFFSET(n)) -#define STM32_OTGHS_HCINTMSK0 (STM32_OTGHS_BASE+STM32_OTGHS_HCINTMSK0_OFFSET) -#define STM32_OTGHS_HCINTMSK1 (STM32_OTGHS_BASE+STM32_OTGHS_HCINTMSK1_OFFSET) -#define STM32_OTGHS_HCINTMSK2 (STM32_OTGHS_BASE+STM32_OTGHS_HCINTMSK2_OFFSET) -#define STM32_OTGHS_HCINTMSK3 (STM32_OTGHS_BASE+STM32_OTGHS_HCINTMSK3_OFFSET) -#define STM32_OTGHS_HCINTMSK4 (STM32_OTGHS_BASE+STM32_OTGHS_HCINTMSK4_OFFSET) -#define STM32_OTGHS_HCINTMSK5 (STM32_OTGHS_BASE+STM32_OTGHS_HCINTMSK5_OFFSET) -#define STM32_OTGHS_HCINTMSK6 (STM32_OTGHS_BASE+STM32_OTGHS_HCINTMSK6_OFFSET) -#define STM32_OTGHS_HCINTMSK7 (STM32_OTGHS_BASE+STM32_OTGHS_HCINTMSK7_OFFSET) -#define STM32_OTGHS_HCINTMSK8 (STM32_OTGHS_BASE+STM32_OTGHS_HCINTMSK8_OFFSET) -#define STM32_OTGHS_HCINTMSK9 (STM32_OTGHS_BASE+STM32_OTGHS_HCINTMSK9_OFFSET) -#define STM32_OTGHS_HCINTMSK10 (STM32_OTGHS_BASE+STM32_OTGHS_HCINTMSK10_OFFSET) -#define STM32_OTGHS_HCINTMSK11 (STM32_OTGHS_BASE+STM32_OTGHS_HCINTMSK11_OFFSET) - -#define STM32_OTGHS_HCTSIZ(n) (STM32_OTGHS_BASE+STM32_OTGHS_HCTSIZ_OFFSET(n)) -#define STM32_OTGHS_HCTSIZ0 (STM32_OTGHS_BASE+STM32_OTGHS_HCTSIZ0_OFFSET) -#define STM32_OTGHS_HCTSIZ1 (STM32_OTGHS_BASE+STM32_OTGHS_HCTSIZ1_OFFSET) -#define STM32_OTGHS_HCTSIZ2 (STM32_OTGHS_BASE+STM32_OTGHS_HCTSIZ2_OFFSET) -#define STM32_OTGHS_HCTSIZ3 (STM32_OTGHS_BASE+STM32_OTGHS_HCTSIZ3_OFFSET) -#define STM32_OTGHS_HCTSIZ4 (STM32_OTGHS_BASE+STM32_OTGHS_HCTSIZ4_OFFSET) -#define STM32_OTGHS_HCTSIZ5 (STM32_OTGHS_BASE+STM32_OTGHS_HCTSIZ5_OFFSET) -#define STM32_OTGHS_HCTSIZ6 (STM32_OTGHS_BASE+STM32_OTGHS_HCTSIZ6_OFFSET) -#define STM32_OTGHS_HCTSIZ7 (STM32_OTGHS_BASE+STM32_OTGHS_HCTSIZ7_OFFSET) -#define STM32_OTGHS_HCTSIZ8 (STM32_OTGHS_BASE+STM32_OTGHS_HCTSIZ8_OFFSET) -#define STM32_OTGHS_HCTSIZ9 (STM32_OTGHS_BASE+STM32_OTGHS_HCTSIZ9_OFFSET) -#define STM32_OTGHS_HCTSIZ10 (STM32_OTGHS_BASE+STM32_OTGHS_HCTSIZ10_OFFSET) -#define STM32_OTGHS_HCTSIZ11 (STM32_OTGHS_BASE+STM32_OTGHS_HCTSIZ11_OFFSET) - -/* Device-mode control and status registers */ - -#define STM32_OTGHS_DCFG (STM32_OTGHS_BASE+STM32_OTGHS_DCFG_OFFSET) -#define STM32_OTGHS_DCTL (STM32_OTGHS_BASE+STM32_OTGHS_DCTL_OFFSET) -#define STM32_OTGHS_DSTS (STM32_OTGHS_BASE+STM32_OTGHS_DSTS_OFFSET) -#define STM32_OTGHS_DIEPMSK (STM32_OTGHS_BASE+STM32_OTGHS_DIEPMSK_OFFSET) -#define STM32_OTGHS_DOEPMSK (STM32_OTGHS_BASE+STM32_OTGHS_DOEPMSK_OFFSET) -#define STM32_OTGHS_DAINT (STM32_OTGHS_BASE+STM32_OTGHS_DAINT_OFFSET) -#define STM32_OTGHS_DAINTMSK (STM32_OTGHS_BASE+STM32_OTGHS_DAINTMSK_OFFSET) -#define STM32_OTGHS_DVBUSDIS (STM32_OTGHS_BASE+STM32_OTGHS_DVBUSDIS_OFFSET) -#define STM32_OTGHS_DVBUSPULSE (STM32_OTGHS_BASE+STM32_OTGHS_DVBUSPULSE_OFFSET) -#define STM32_OTGHS_DIEPEMPMSK (STM32_OTGHS_BASE+STM32_OTGHS_DIEPEMPMSK_OFFSET) - -#define STM32_OTGHS_DIEP(n) (STM32_OTGHS_BASE+STM32_OTGHS_DIEP_OFFSET(n)) - -#define STM32_OTGHS_DIEPCTL(n) (STM32_OTGHS_BASE+STM32_OTGHS_DIEPCTL_OFFSET(n)) -#define STM32_OTGHS_DIEPCTL0 (STM32_OTGHS_BASE+STM32_OTGHS_DIEPCTL0_OFFSET) -#define STM32_OTGHS_DIEPCTL1 (STM32_OTGHS_BASE+STM32_OTGHS_DIEPCTL1_OFFSET) -#define STM32_OTGHS_DIEPCTL2 (STM32_OTGHS_BASE+STM32_OTGHS_DIEPCTL2_OFFSET) -#define STM32_OTGHS_DIEPCTL3 (STM32_OTGHS_BASE+STM32_OTGHS_DIEPCTL3_OFFSET) - -#define STM32_OTGHS_DIEPINT(n) (STM32_OTGHS_BASE+STM32_OTGHS_DIEPINT_OFFSET(n)) -#define STM32_OTGHS_DIEPINT0 (STM32_OTGHS_BASE+STM32_OTGHS_DIEPINT0_OFFSET) -#define STM32_OTGHS_DIEPINT1 (STM32_OTGHS_BASE+STM32_OTGHS_DIEPINT1_OFFSET) -#define STM32_OTGHS_DIEPINT2 (STM32_OTGHS_BASE+STM32_OTGHS_DIEPINT2_OFFSET) -#define STM32_OTGHS_DIEPINT3 (STM32_OTGHS_BASE+STM32_OTGHS_DIEPINT3_OFFSET) - -#define STM32_OTGHS_DIEPTSIZ(n) (STM32_OTGHS_BASE+STM32_OTGHS_DIEPTSIZ_OFFSET(n)) -#define STM32_OTGHS_DIEPTSIZ0 (STM32_OTGHS_BASE+STM32_OTGHS_DIEPTSIZ0_OFFSET) -#define STM32_OTGHS_DIEPTSIZ1 (STM32_OTGHS_BASE+STM32_OTGHS_DIEPTSIZ1_OFFSET) -#define STM32_OTGHS_DIEPTSIZ2 (STM32_OTGHS_BASE+STM32_OTGHS_DIEPTSIZ2_OFFSET) -#define STM32_OTGHS_DIEPTSIZ3 (STM32_OTGHS_BASE+STM32_OTGHS_DIEPTSIZ3_OFFSET) - -#define STM32_OTGHS_DTXFSTS(n) (STM32_OTGHS_BASE+STM32_OTGHS_DTXFSTS_OFFSET(n)) -#define STM32_OTGHS_DTXFSTS0 (STM32_OTGHS_BASE+STM32_OTGHS_DTXFSTS0_OFFSET) -#define STM32_OTGHS_DTXFSTS1 (STM32_OTGHS_BASE+STM32_OTGHS_DTXFSTS1_OFFSET) -#define STM32_OTGHS_DTXFSTS2 (STM32_OTGHS_BASE+STM32_OTGHS_DTXFSTS2_OFFSET) -#define STM32_OTGHS_DTXFSTS3 (STM32_OTGHS_BASE+STM32_OTGHS_DTXFSTS3_OFFSET) - -#define STM32_OTGHS_DOEP(n) (STM32_OTGHS_BASE+STM32_OTGHS_DOEP_OFFSET(n)) - -#define STM32_OTGHS_DOEPCTL(n) (STM32_OTGHS_BASE+STM32_OTGHS_DOEPCTL_OFFSET(n)) -#define STM32_OTGHS_DOEPCTL0 (STM32_OTGHS_BASE+STM32_OTGHS_DOEPCTL0_OFFSET) -#define STM32_OTGHS_DOEPCTL1 (STM32_OTGHS_BASE+STM32_OTGHS_DOEPCTL1_OFFSET) -#define STM32_OTGHS_DOEPCTL2 (STM32_OTGHS_BASE+STM32_OTGHS_DOEPCTL2_OFFSET) -#define STM32_OTGHS_DOEPCTL3 (STM32_OTGHS_BASE+STM32_OTGHS_DOEPCTL3_OFFSET) - -#define STM32_OTGHS_DOEPINT(n) (STM32_OTGHS_BASE+STM32_OTGHS_DOEPINT_OFFSET(n)) -#define STM32_OTGHS_DOEPINT0 (STM32_OTGHS_BASE+STM32_OTGHS_DOEPINT0_OFFSET) -#define STM32_OTGHS_DOEPINT1 (STM32_OTGHS_BASE+STM32_OTGHS_DOEPINT1_OFFSET) -#define STM32_OTGHS_DOEPINT2 (STM32_OTGHS_BASE+STM32_OTGHS_DOEPINT2_OFFSET) -#define STM32_OTGHS_DOEPINT3 (STM32_OTGHS_BASE+STM32_OTGHS_DOEPINT3_OFFSET) - -#define STM32_OTGHS_DOEPTSIZ(n) (STM32_OTGHS_BASE+STM32_OTGHS_DOEPTSIZ_OFFSET(n)) -#define STM32_OTGHS_DOEPTSIZ0 (STM32_OTGHS_BASE+STM32_OTGHS_DOEPTSIZ0_OFFSET) -#define STM32_OTGHS_DOEPTSIZ1 (STM32_OTGHS_BASE+STM32_OTGHS_DOEPTSIZ1_OFFSET) -#define STM32_OTGHS_DOEPTSIZ2 (STM32_OTGHS_BASE+STM32_OTGHS_DOEPTSIZ2_OFFSET) -#define STM32_OTGHS_DOEPTSIZ3 (STM32_OTGHS_BASE+STM32_OTGHS_DOEPTSIZ3_OFFSET) - -/* Power and clock gating registers */ - -#define STM32_OTGHS_PCGCCTL (STM32_OTGHS_BASE+STM32_OTGHS_PCGCCTL_OFFSET) - -/* Data FIFO (DFIFO) access registers */ - -#define STM32_OTGHS_DFIFO_DEP(n) (STM32_OTGHS_BASE+STM32_OTGHS_DFIFO_DEP_OFFSET(n)) -#define STM32_OTGHS_DFIFO_HCH(n) (STM32_OTGHS_BASE+STM32_OTGHS_DFIFO_HCH_OFFSET(n)) - -#define STM32_OTGHS_DFIFO_DEP0 (STM32_OTGHS_BASE+STM32_OTGHS_DFIFO_DEP0_OFFSET) -#define STM32_OTGHS_DFIFO_HCH0 (STM32_OTGHS_BASE+STM32_OTGHS_DFIFO_HCH0_OFFSET) - -#define STM32_OTGHS_DFIFO_DEP1 (STM32_OTGHS_BASE+STM32_OTGHS_DFIFO_DEP1_OFFSET) -#define STM32_OTGHS_DFIFO_HCH1 (STM32_OTGHS_BASE+STM32_OTGHS_DFIFO_HCH1_OFFSET) - -#define STM32_OTGHS_DFIFO_DEP2 (STM32_OTGHS_BASE+STM32_OTGHS_DFIFO_DEP2_OFFSET) -#define STM32_OTGHS_DFIFO_HCH2 (STM32_OTGHS_BASE+STM32_OTGHS_DFIFO_HCH2_OFFSET) - -#define STM32_OTGHS_DFIFO_DEP3 (STM32_OTGHS_BASE+STM32_OTGHS_DFIFO_DEP3_OFFSET) -#define STM32_OTGHS_DFIFO_HCH3 (STM32_OTGHS_BASE+STM32_OTGHS_DFIFO_HCH3_OFFSET) - -/* Register Bitfield Definitions ********************************************/ - -/* Core global control and status registers */ - -/* Control and status register */ - -#define OTGHS_GOTGCTL_SRQSCS (1 << 0) /* Bit 0: Session request success */ -#define OTGHS_GOTGCTL_SRQ (1 << 1) /* Bit 1: Session request */ - /* Bits 2-72 Reserved, must be kept at reset value */ -#define OTGHS_GOTGCTL_HNGSCS (1 << 8) /* Bit 8: Host negotiation success */ -#define OTGHS_GOTGCTL_HNPRQ (1 << 9) /* Bit 9: HNP request */ -#define OTGHS_GOTGCTL_HSHNPEN (1 << 10) /* Bit 10: host set HNP enable */ -#define OTGHS_GOTGCTL_DHNPEN (1 << 11) /* Bit 11: Device HNP enabled */ - /* Bits 12-15: Reserved, must be kept at reset value */ -#define OTGHS_GOTGCTL_CIDSTS (1 << 16) /* Bit 16: Connector ID status */ -#define OTGHS_GOTGCTL_DBCT (1 << 17) /* Bit 17: Long/short debounce time */ -#define OTGHS_GOTGCTL_ASVLD (1 << 18) /* Bit 18: A-session valid */ -#define OTGHS_GOTGCTL_BSVLD (1 << 19) /* Bit 19: B-session valid */ - /* Bits 20-31: Reserved, must be kept at reset value */ - -/* Interrupt register */ - -/* Bits 1:0 Reserved, - * must be kept at reset value - */ -#define OTGHS_GOTGINT_SEDET (1 << 2) /* Bit 2: Session end detected */ - /* Bits 3-7: Reserved, must be kept at reset value */ -#define OTGHS_GOTGINT_SRSSCHG (1 << 8) /* Bit 8: Session request success status change */ -#define OTGHS_GOTGINT_HNSSCHG (1 << 9) /* Bit 9: Host negotiation success status change */ - /* Bits 16:10 Reserved, must be kept at reset value */ -#define OTGHS_GOTGINT_HNGDET (1 << 17) /* Bit 17: Host negotiation detected */ -#define OTGHS_GOTGINT_ADTOCHG (1 << 18) /* Bit 18: A-device timeout change */ -#define OTGHS_GOTGINT_DBCDNE (1 << 19) /* Bit 19: Debounce done */ - /* Bits 2-31: Reserved, must be kept at reset value */ - -/* AHB configuration register */ - -#define OTGHS_GAHBCFG_GINTMSK (1 << 0) /* Bit 0: Global interrupt mask */ - /* Bits 1-6: Reserved, must be kept at reset value */ -#define OTGHS_GAHBCFG_TXFELVL (1 << 7) /* Bit 7: TxFIFO empty level */ -#define OTGHS_GAHBCFG_PTXFELVL (1 << 8) /* Bit 8: Periodic TxFIFO empty level */ - /* Bits 20-31: Reserved, must be kept at reset value */ - -/* USB configuration register */ - -#define OTGHS_GUSBCFG_TOCAL_SHIFT (0) /* Bits 0-2: FS timeout calibration */ -#define OTGHS_GUSBCFG_TOCAL_MASK (7 << OTGHS_GUSBCFG_TOCAL_SHIFT) - /* Bits 3-5: Reserved, must be kept at reset value */ -#define OTGHS_GUSBCFG_PHYSEL (1 << 6) /* Bit 6: Full Speed serial transceiver select */ - /* Bit 7: Reserved, must be kept at reset value */ -#define OTGHS_GUSBCFG_SRPCAP (1 << 8) /* Bit 8: SRP-capable */ -#define OTGHS_GUSBCFG_HNPCAP (1 << 9) /* Bit 9: HNP-capable */ -#define OTGHS_GUSBCFG_TRDT_SHIFT (10) /* Bits 10-13: USB turnaround time */ -#define OTGHS_GUSBCFG_TRDT_MASK (15 << OTGHS_GUSBCFG_TRDT_SHIFT) -# define OTGHS_GUSBCFG_TRDT(n) ((n) << OTGHS_GUSBCFG_TRDT_SHIFT) - /* Bits 14-28: Reserved, must be kept at reset value */ -#define OTGHS_GUSBCFG_FHMOD (1 << 29) /* Bit 29: Force host mode */ -#define OTGHS_GUSBCFG_FDMOD (1 << 30) /* Bit 30: Force device mode */ -#define OTGHS_GUSBCFG_CTXPKT (1 << 31) /* Bit 31: Corrupt Tx packet */ - /* Bits 20-31: Reserved, must be kept at reset value */ - -/* Reset register */ - -#define OTGHS_GRSTCTL_CSRST (1 << 0) /* Bit 0: Core soft reset */ -#define OTGHS_GRSTCTL_HSRST (1 << 1) /* Bit 1: HCLK soft reset */ -#define OTGHS_GRSTCTL_FCRST (1 << 2) /* Bit 2: Host frame counter reset */ - /* Bit 3 Reserved, must be kept at reset value */ -#define OTGHS_GRSTCTL_RXFFLSH (1 << 4) /* Bit 4: RxFIFO flush */ -#define OTGHS_GRSTCTL_TXFFLSH (1 << 5) /* Bit 5: TxFIFO flush */ -#define OTGHS_GRSTCTL_TXFNUM_SHIFT (10) /* Bits 6-10: TxFIFO number */ -#define OTGHS_GRSTCTL_TXFNUM_MASK (31 << OTGHS_GRSTCTL_TXFNUM_SHIFT) -# define OTGHS_GRSTCTL_TXFNUM_HNONPER (0 << OTGHS_GRSTCTL_TXFNUM_SHIFT) /* Non-periodic TxFIFO flush in host mode */ -# define OTGHS_GRSTCTL_TXFNUM_HPER (1 << OTGHS_GRSTCTL_TXFNUM_SHIFT) /* Periodic TxFIFO flush in host mode */ -# define OTGHS_GRSTCTL_TXFNUM_HALL (16 << OTGHS_GRSTCTL_TXFNUM_SHIFT) /* Flush all the transmit FIFOs in host mode.*/ -# define OTGHS_GRSTCTL_TXFNUM_D(n) ((n) << OTGHS_GRSTCTL_TXFNUM_SHIFT) /* TXFIFO n flush in device mode, n=0-15 */ -# define OTGHS_GRSTCTL_TXFNUM_DALL (16 << OTGHS_GRSTCTL_TXFNUM_SHIFT) /* Flush all the transmit FIFOs in device mode.*/ - -/* Bits 11-31: Reserved, - * must be kept at reset value - */ -#define OTGHS_GRSTCTL_AHBIDL (1 << 31) /* Bit 31: AHB master idle */ - -/* Core interrupt and Interrupt mask registers */ - -#define OTGHS_GINTSTS_CMOD (1 << 0) /* Bit 0: Current mode of operation */ -# define OTGHS_GINTSTS_DEVMODE (0) -# define OTGHS_GINTSTS_HOSTMODE (OTGHS_GINTSTS_CMOD) -#define OTGHS_GINT_MMIS (1 << 1) /* Bit 1: Mode mismatch interrupt */ -#define OTGHS_GINT_OTG (1 << 2) /* Bit 2: OTG interrupt */ -#define OTGHS_GINT_SOF (1 << 3) /* Bit 3: Start of frame */ -#define OTGHS_GINT_RXFLVL (1 << 4) /* Bit 4: RxFIFO non-empty */ -#define OTGHS_GINT_NPTXFE (1 << 5) /* Bit 5: Non-periodic TxFIFO empty */ -#define OTGHS_GINT_GINAKEFF (1 << 6) /* Bit 6: Global IN non-periodic NAK effective */ -#define OTGHS_GINT_GONAKEFF (1 << 7) /* Bit 7: Global OUT NAK effective */ - /* Bits 8-9: Reserved, must be kept at reset value */ -#define OTGHS_GINT_ESUSP (1 << 10) /* Bit 10: Early suspend */ -#define OTGHS_GINT_USBSUSP (1 << 11) /* Bit 11: USB suspend */ -#define OTGHS_GINT_USBRST (1 << 12) /* Bit 12: USB reset */ -#define OTGHS_GINT_ENUMDNE (1 << 13) /* Bit 13: Enumeration done */ -#define OTGHS_GINT_ISOODRP (1 << 14) /* Bit 14: Isochronous OUT packet dropped interrupt */ -#define OTGHS_GINT_EOPF (1 << 15) /* Bit 15: End of periodic frame interrupt */ - /* Bits 16 Reserved, must be kept at reset value */ -#define OTGHS_GINTMSK_EPMISM (1 << 17) /* Bit 17: Endpoint mismatch interrupt mask */ -#define OTGHS_GINT_IEP (1 << 18) /* Bit 18: IN endpoint interrupt */ -#define OTGHS_GINT_OEP (1 << 19) /* Bit 19: OUT endpoint interrupt */ -#define OTGHS_GINT_IISOIXFR (1 << 20) /* Bit 20: Incomplete isochronous IN transfer */ -#define OTGHS_GINT_IISOOXFR (1 << 21) /* Bit 21: Incomplete isochronous OUT transfer */ -#define OTGHS_GINT_IPXFR (1 << 21) /* Bit 21: Incomplete periodic transfer (host) */ - /* Bits 22-23: Reserved, must be kept at reset value */ -#define OTGHS_GINT_HPRT (1 << 24) /* Bit 24: Host port interrupt */ -#define OTGHS_GINT_HC (1 << 25) /* Bit 25: Host channels interrupt */ -#define OTGHS_GINT_PTXFE (1 << 26) /* Bit 26: Periodic TxFIFO empty */ - /* Bit 27 Reserved, must be kept at reset value */ -#define OTGHS_GINT_CIDSCHG (1 << 28) /* Bit 28: Connector ID status change */ -#define OTGHS_GINT_DISC (1 << 29) /* Bit 29: Disconnect detected interrupt */ -#define OTGHS_GINT_SRQ (1 << 30) /* Bit 30: Session request/new session detected interrupt */ -#define OTGHS_GINT_WKUP (1 << 31) /* Bit 31: Resume/remote wakeup detected interrupt */ - -/* Receive status debug read/OTG status read and pop registers (host mode) */ - -#define OTGHS_GRXSTSH_CHNUM_SHIFT (0) /* Bits 0-3: Channel number */ -#define OTGHS_GRXSTSH_CHNUM_MASK (15 << OTGHS_GRXSTSH_CHNUM_SHIFT) -#define OTGHS_GRXSTSH_BCNT_SHIFT (4) /* Bits 4-14: Byte count */ -#define OTGHS_GRXSTSH_BCNT_MASK (0x7ff << OTGHS_GRXSTSH_BCNT_SHIFT) -#define OTGHS_GRXSTSH_DPID_SHIFT (15) /* Bits 15-16: Data PID */ -#define OTGHS_GRXSTSH_DPID_MASK (3 << OTGHS_GRXSTSH_DPID_SHIFT) -# define OTGHS_GRXSTSH_DPID_DATA0 (0 << OTGHS_GRXSTSH_DPID_SHIFT) -# define OTGHS_GRXSTSH_DPID_DATA2 (1 << OTGHS_GRXSTSH_DPID_SHIFT) -# define OTGHS_GRXSTSH_DPID_DATA1 (2 << OTGHS_GRXSTSH_DPID_SHIFT) -# define OTGHS_GRXSTSH_DPID_MDATA (3 << OTGHS_GRXSTSH_DPID_SHIFT) -#define OTGHS_GRXSTSH_PKTSTS_SHIFT (17) /* Bits 17-20: Packet status */ -#define OTGHS_GRXSTSH_PKTSTS_MASK (15 << OTGHS_GRXSTSH_PKTSTS_SHIFT) -# define OTGHS_GRXSTSH_PKTSTS_INRECVD (2 << OTGHS_GRXSTSH_PKTSTS_SHIFT) /* IN data packet received */ -# define OTGHS_GRXSTSH_PKTSTS_INDONE (3 << OTGHS_GRXSTSH_PKTSTS_SHIFT) /* IN transfer completed */ -# define OTGHS_GRXSTSH_PKTSTS_DTOGERR (5 << OTGHS_GRXSTSH_PKTSTS_SHIFT) /* Data toggle error */ -# define OTGHS_GRXSTSH_PKTSTS_HALTED (7 << OTGHS_GRXSTSH_PKTSTS_SHIFT) /* Channel halted */ - -/* Bits 21-31: Reserved, - * must be kept at reset value - */ - -/* Receive status debug read/OTG status read and pop registers - * (device mode) - */ - -#define OTGHS_GRXSTSD_EPNUM_SHIFT (0) /* Bits 0-3: Endpoint number */ -#define OTGHS_GRXSTSD_EPNUM_MASK (15 << OTGHS_GRXSTSD_EPNUM_SHIFT) -#define OTGHS_GRXSTSD_BCNT_SHIFT (4) /* Bits 4-14: Byte count */ -#define OTGHS_GRXSTSD_BCNT_MASK (0x7ff << OTGHS_GRXSTSD_BCNT_SHIFT) -#define OTGHS_GRXSTSD_DPID_SHIFT (15) /* Bits 15-16: Data PID */ -#define OTGHS_GRXSTSD_DPID_MASK (3 << OTGHS_GRXSTSD_DPID_SHIFT) -# define OTGHS_GRXSTSD_DPID_DATA0 (0 << OTGHS_GRXSTSD_DPID_SHIFT) -# define OTGHS_GRXSTSD_DPID_DATA2 (1 << OTGHS_GRXSTSD_DPID_SHIFT) -# define OTGHS_GRXSTSD_DPID_DATA1 (2 << OTGHS_GRXSTSD_DPID_SHIFT) -# define OTGHS_GRXSTSD_DPID_MDATA (3 << OTGHS_GRXSTSD_DPID_SHIFT) -#define OTGHS_GRXSTSD_PKTSTS_SHIFT (17) /* Bits 17-20: Packet status */ -#define OTGHS_GRXSTSD_PKTSTS_MASK (15 << OTGHS_GRXSTSD_PKTSTS_SHIFT) -# define OTGHS_GRXSTSD_PKTSTS_OUTNAK (1 << OTGHS_GRXSTSD_PKTSTS_SHIFT) /* Global OUT NAK */ -# define OTGHS_GRXSTSD_PKTSTS_OUTRECVD (2 << OTGHS_GRXSTSD_PKTSTS_SHIFT) /* OUT data packet received */ -# define OTGHS_GRXSTSD_PKTSTS_OUTDONE (3 << OTGHS_GRXSTSD_PKTSTS_SHIFT) /* OUT transfer completed */ -# define OTGHS_GRXSTSD_PKTSTS_SETUPDONE (4 << OTGHS_GRXSTSD_PKTSTS_SHIFT) /* SETUP transaction completed */ -# define OTGHS_GRXSTSD_PKTSTS_SETUPRECVD (6 << OTGHS_GRXSTSD_PKTSTS_SHIFT) /* SETUP data packet received */ - -#define OTGHS_GRXSTSD_FRMNUM_SHIFT (21) /* Bits 21-24: Frame number */ -#define OTGHS_GRXSTSD_FRMNUM_MASK (15 << OTGHS_GRXSTSD_FRMNUM_SHIFT) - /* Bits 25-31: Reserved, must be kept at reset value */ - -/* Receive FIFO size register */ - -#define OTGHS_GRXFSIZ_MASK (0xffff) - -/* Host non-periodic transmit FIFO size register */ - -#define OTGHS_HNPTXFSIZ_NPTXFSA_SHIFT (0) /* Bits 0-15: Non-periodic transmit RAM start address */ -#define OTGHS_HNPTXFSIZ_NPTXFSA_MASK (0xffff << OTGHS_HNPTXFSIZ_NPTXFSA_SHIFT) -#define OTGHS_HNPTXFSIZ_NPTXFD_SHIFT (16) /* Bits 16-31: Non-periodic TxFIFO depth */ -#define OTGHS_HNPTXFSIZ_NPTXFD_MASK (0xffff << OTGHS_HNPTXFSIZ_NPTXFD_SHIFT) -# define OTGHS_HNPTXFSIZ_NPTXFD_MIN (16 << OTGHS_HNPTXFSIZ_NPTXFD_SHIFT) -# define OTGHS_HNPTXFSIZ_NPTXFD_MAX (256 << OTGHS_HNPTXFSIZ_NPTXFD_SHIFT) - -/* Endpoint 0 Transmit FIFO size */ - -#define OTGHS_DIEPTXF0_TX0FD_SHIFT (0) /* Bits 0-15: Endpoint 0 transmit RAM start address */ -#define OTGHS_DIEPTXF0_TX0FD_MASK (0xffff << OTGHS_DIEPTXF0_TX0FD_SHIFT) -#define OTGHS_DIEPTXF0_TX0FSA_SHIFT (16) /* Bits 16-31: Endpoint 0 TxFIFO depth */ -#define OTGHS_DIEPTXF0_TX0FSA_MASK (0xffff << OTGHS_DIEPTXF0_TX0FSA_SHIFT) -# define OTGHS_DIEPTXF0_TX0FSA_MIN (16 << OTGHS_DIEPTXF0_TX0FSA_SHIFT) -# define OTGHS_DIEPTXF0_TX0FSA_MAX (256 << OTGHS_DIEPTXF0_TX0FSA_SHIFT) - -/* Non-periodic transmit FIFO/queue status register */ - -#define OTGHS_HNPTXSTS_NPTXFSAV_SHIFT (0) /* Bits 0-15: Non-periodic TxFIFO space available */ -#define OTGHS_HNPTXSTS_NPTXFSAV_MASK (0xffff << OTGHS_HNPTXSTS_NPTXFSAV_SHIFT) -# define OTGHS_HNPTXSTS_NPTXFSAV_FULL (0 << OTGHS_HNPTXSTS_NPTXFSAV_SHIFT) -#define OTGHS_HNPTXSTS_NPTQXSAV_SHIFT (16) /* Bits 16-23: Non-periodic transmit request queue space available */ -#define OTGHS_HNPTXSTS_NPTQXSAV_MASK (0xff << OTGHS_HNPTXSTS_NPTQXSAV_SHIFT) -# define OTGHS_HNPTXSTS_NPTQXSAV_FULL (0 << OTGHS_HNPTXSTS_NPTQXSAV_SHIFT) -#define OTGHS_HNPTXSTS_NPTXQTOP_SHIFT (24) /* Bits 24-30: Top of the non-periodic transmit request queue */ -#define OTGHS_HNPTXSTS_NPTXQTOP_MASK (0x7f << OTGHS_HNPTXSTS_NPTXQTOP_SHIFT) -# define OTGHS_HNPTXSTS_TERMINATE (1 << 24) /* Bit 24: Terminate (last entry for selected channel/endpoint) */ -# define OTGHS_HNPTXSTS_TYPE_SHIFT (25) /* Bits 25-26: Status */ -# define OTGHS_HNPTXSTS_TYPE_MASK (3 << OTGHS_HNPTXSTS_TYPE_SHIFT) -# define OTGHS_HNPTXSTS_TYPE_INOUT (0 << OTGHS_HNPTXSTS_TYPE_SHIFT) /* IN/OUT token */ -# define OTGHS_HNPTXSTS_TYPE_ZLP (1 << OTGHS_HNPTXSTS_TYPE_SHIFT) /* Zero-length transmit packet (device IN/host OUT) */ -# define OTGHS_HNPTXSTS_TYPE_HALT (3 << OTGHS_HNPTXSTS_TYPE_SHIFT) /* Channel halt command */ - -# define OTGHS_HNPTXSTS_CHNUM_SHIFT (27) /* Bits 27-30: Channel number */ -# define OTGHS_HNPTXSTS_CHNUM_MASK (15 << OTGHS_HNPTXSTS_CHNUM_SHIFT) -# define OTGHS_HNPTXSTS_EPNUM_SHIFT (27) /* Bits 27-30: Endpoint number */ -# define OTGHS_HNPTXSTS_EPNUM_MASK (15 << OTGHS_HNPTXSTS_EPNUM_SHIFT) - /* Bit 31 Reserved, must be kept at reset value */ - -/* General core configuration register */ - -/* Bits 15:0 Reserved, - * must be kept at reset value - */ -#define OTGHS_GCCFG_PWRDWN (1 << 16) /* Bit 16: Power down */ - /* Bit 17 Reserved, must be kept at reset value */ -#define OTGHS_GCCFG_VBUSASEN (1 << 18) /* Bit 18: Enable the VBUS sensing “A” device */ -#define OTGHS_GCCFG_VBUSBSEN (1 << 19) /* Bit 19: Enable the VBUS sensing “B” device */ -#define OTGHS_GCCFG_SOFOUTEN (1 << 20) /* Bit 20: SOF output enable */ -#define OTGHS_GCCFG_NOVBUSSENS (1 << 21) /* Bit 21: VBUS sensing disable option */ - /* Bits 31:22 Reserved, must be kept at reset value */ - -/* Core ID register (32-bit product ID) */ - -/* Host periodic transmit FIFO size register */ - -#define OTGHS_HPTXFSIZ_PTXSA_SHIFT (0) /* Bits 0-15: Host periodic TxFIFO start address */ -#define OTGHS_HPTXFSIZ_PTXSA_MASK (0xffff << OTGHS_HPTXFSIZ_PTXSA_SHIFT) -#define OTGHS_HPTXFSIZ_PTXFD_SHIFT (16) /* Bits 16-31: Host periodic TxFIFO depth */ -#define OTGHS_HPTXFSIZ_PTXFD_MASK (0xffff << OTGHS_HPTXFSIZ_PTXFD_SHIFT) - -/* Device IN endpoint transmit FIFOn size register */ - -#define OTGHS_DIEPTXF_INEPTXSA_SHIFT (0) /* Bits 0-15: IN endpoint FIFOx transmit RAM start address */ -#define OTGHS_DIEPTXF_INEPTXSA_MASK (0xffff << OTGHS_DIEPTXF_INEPTXSA_SHIFT) -#define OTGHS_DIEPTXF_INEPTXFD_SHIFT (16) /* Bits 16-31: IN endpoint TxFIFO depth */ -#define OTGHS_DIEPTXF_INEPTXFD_MASK (0xffff << OTGHS_DIEPTXF_INEPTXFD_SHIFT) -# define OTGHS_DIEPTXF_INEPTXFD_MIN (16 << OTGHS_DIEPTXF_INEPTXFD_MASK) - -/* Host-mode control and status registers */ - -/* Host configuration register */ - -#define OTGHS_HCFG_FSLSPCS_SHIFT (0) /* Bits 0-1: FS/LS PHY clock select */ -#define OTGHS_HCFG_FSLSPCS_MASK (3 << OTGHS_HCFG_FSLSPCS_SHIFT) -# define OTGHS_HCFG_FSLSPCS_FS48MHz (1 << OTGHS_HCFG_FSLSPCS_SHIFT) /* FS host mode, PHY clock is running at 48 MHz */ -# define OTGHS_HCFG_FSLSPCS_LS48MHz (1 << OTGHS_HCFG_FSLSPCS_SHIFT) /* LS host mode, Select 48 MHz PHY clock frequency */ -# define OTGHS_HCFG_FSLSPCS_LS6MHz (2 << OTGHS_HCFG_FSLSPCS_SHIFT) /* LS host mode, Select 6 MHz PHY clock frequency */ - -#define OTGHS_HCFG_FSLSS (1 << 2) /* Bit 2: FS- and LS-only support */ - /* Bits 31:3 Reserved, must be kept at reset value */ - -/* Host frame interval register */ - -#define OTGHS_HFIR_MASK (0xffff) - -/* Host frame number/frame time remaining register */ - -#define OTGHS_HFNUM_FRNUM_SHIFT (0) /* Bits 0-15: Frame number */ -#define OTGHS_HFNUM_FRNUM_MASK (0xffff << OTGHS_HFNUM_FRNUM_SHIFT) -#define OTGHS_HFNUM_FTREM_SHIFT (16) /* Bits 16-31: Frame time remaining */ -#define OTGHS_HFNUM_FTREM_MASK (0xffff << OTGHS_HFNUM_FTREM_SHIFT) - -/* Host periodic transmit FIFO/queue status register */ - -#define OTGHS_HPTXSTS_PTXFSAVL_SHIFT (0) /* Bits 0-15: Periodic transmit data FIFO space available */ -#define OTGHS_HPTXSTS_PTXFSAVL_MASK (0xffff << OTGHS_HPTXSTS_PTXFSAVL_SHIFT) -# define OTGHS_HPTXSTS_PTXFSAVL_FULL (0 << OTGHS_HPTXSTS_PTXFSAVL_SHIFT) -#define OTGHS_HPTXSTS_PTXQSAV_SHIFT (16) /* Bits 16-23: Periodic transmit request queue space available */ -#define OTGHS_HPTXSTS_PTXQSAV_MASK (0xff << OTGHS_HPTXSTS_PTXQSAV_SHIFT) -# define OTGHS_HPTXSTS_PTXQSAV_FULL (0 << OTGHS_HPTXSTS_PTXQSAV_SHIFT) -#define OTGHS_HPTXSTS_PTXQTOP_SHIFT (24) /* Bits 24-31: Top of the periodic transmit request queue */ -#define OTGHS_HPTXSTS_PTXQTOP_MASK (0x7f << OTGHS_HPTXSTS_PTXQTOP_SHIFT) -# define OTGHS_HPTXSTS_TERMINATE (1 << 24) /* Bit 24: Terminate (last entry for selected channel/endpoint) */ -# define OTGHS_HPTXSTS_TYPE_SHIFT (25) /* Bits 25-26: Type */ -# define OTGHS_HPTXSTS_TYPE_MASK (3 << OTGHS_HPTXSTS_TYPE_SHIFT) -# define OTGHS_HPTXSTS_TYPE_INOUT (0 << OTGHS_HPTXSTS_TYPE_SHIFT) /* IN/OUT token */ -# define OTGHS_HPTXSTS_TYPE_ZLP (1 << OTGHS_HPTXSTS_TYPE_SHIFT) /* Zero-length transmit packet */ -# define OTGHS_HPTXSTS_TYPE_HALT (3 << OTGHS_HPTXSTS_TYPE_SHIFT) /* Disable channel command */ - -# define OTGHS_HPTXSTS_EPNUM_SHIFT (27) /* Bits 27-30: Endpoint number */ -# define OTGHS_HPTXSTS_EPNUM_MASK (15 << OTGHS_HPTXSTS_EPNUM_SHIFT) -# define OTGHS_HPTXSTS_CHNUM_SHIFT (27) /* Bits 27-30: Channel number */ -# define OTGHS_HPTXSTS_CHNUM_MASK (15 << OTGHS_HPTXSTS_CHNUM_SHIFT) -# define OTGHS_HPTXSTS_ODD (1 << 24) /* Bit 31: Send in odd (vs even) frame */ - -/* Host all channels interrupt and all channels interrupt mask registers */ - -#define OTGHS_HAINT(n) (1 << (n)) /* Bits 15:0 HAINTM: Channel interrupt */ - -/* Host port control and status register */ - -#define OTGHS_HPRT_PCSTS (1 << 0) /* Bit 0: Port connect status */ -#define OTGHS_HPRT_PCDET (1 << 1) /* Bit 1: Port connect detected */ -#define OTGHS_HPRT_PENA (1 << 2) /* Bit 2: Port enable */ -#define OTGHS_HPRT_PENCHNG (1 << 3) /* Bit 3: Port enable/disable change */ -#define OTGHS_HPRT_POCA (1 << 4) /* Bit 4: Port overcurrent active */ -#define OTGHS_HPRT_POCCHNG (1 << 5) /* Bit 5: Port overcurrent change */ -#define OTGHS_HPRT_PRES (1 << 6) /* Bit 6: Port resume */ -#define OTGHS_HPRT_PSUSP (1 << 7) /* Bit 7: Port suspend */ -#define OTGHS_HPRT_PRST (1 << 8) /* Bit 8: Port reset */ - /* Bit 9: Reserved, must be kept at reset value */ -#define OTGHS_HPRT_PLSTS_SHIFT (10) /* Bits 10-11: Port line status */ -#define OTGHS_HPRT_PLSTS_MASK (3 << OTGHS_HPRT_PLSTS_SHIFT) -# define OTGHS_HPRT_PLSTS_DP (1 << 10) /* Bit 10: Logic level of OTG_FS_FS_DP */ -# define OTGHS_HPRT_PLSTS_DM (1 << 11) /* Bit 11: Logic level of OTG_FS_FS_DM */ -#define OTGHS_HPRT_PPWR (1 << 12) /* Bit 12: Port power */ -#define OTGHS_HPRT_PTCTL_SHIFT (13) /* Bits 13-16: Port test control */ -#define OTGHS_HPRT_PTCTL_MASK (15 << OTGHS_HPRT_PTCTL_SHIFT) -# define OTGHS_HPRT_PTCTL_DISABLED (0 << OTGHS_HPRT_PTCTL_SHIFT) /* Test mode disabled */ -# define OTGHS_HPRT_PTCTL_J (1 << OTGHS_HPRT_PTCTL_SHIFT) /* Test_J mode */ -# define OTGHS_HPRT_PTCTL_L (2 << OTGHS_HPRT_PTCTL_SHIFT) /* Test_K mode */ -# define OTGHS_HPRT_PTCTL_SE0_NAK (3 << OTGHS_HPRT_PTCTL_SHIFT) /* Test_SE0_NAK mode */ -# define OTGHS_HPRT_PTCTL_PACKET (4 << OTGHS_HPRT_PTCTL_SHIFT) /* Test_Packet mode */ -# define OTGHS_HPRT_PTCTL_FORCE (5 << OTGHS_HPRT_PTCTL_SHIFT) /* Test_Force_Enable */ - -#define OTGHS_HPRT_PSPD_SHIFT (17) /* Bits 17-18: Port speed */ -#define OTGHS_HPRT_PSPD_MASK (3 << OTGHS_HPRT_PSPD_SHIFT) -# define OTGHS_HPRT_PSPD_FS (1 << OTGHS_HPRT_PSPD_SHIFT) /* Full speed */ -# define OTGHS_HPRT_PSPD_LS (2 << OTGHS_HPRT_PSPD_SHIFT) /* Low speed */ - -/* Bits 19-31: Reserved, - * must be kept at reset value - */ - -/* Host channel-n characteristics register */ - -#define OTGHS_HCCHAR_MPSIZ_SHIFT (0) /* Bits 0-10: Maximum packet size */ -#define OTGHS_HCCHAR_MPSIZ_MASK (0x7ff << OTGHS_HCCHAR_MPSIZ_SHIFT) -#define OTGHS_HCCHAR_EPNUM_SHIFT (11) /* Bits 11-14: Endpoint number */ -#define OTGHS_HCCHAR_EPNUM_MASK (15 << OTGHS_HCCHAR_EPNUM_SHIFT) -#define OTGHS_HCCHAR_EPDIR (1 << 15) /* Bit 15: Endpoint direction */ -# define OTGHS_HCCHAR_EPDIR_OUT (0) -# define OTGHS_HCCHAR_EPDIR_IN OTGHS_HCCHAR_EPDIR - /* Bit 16 Reserved, must be kept at reset value */ -#define OTGHS_HCCHAR_LSDEV (1 << 17) /* Bit 17: Low-speed device */ -#define OTGHS_HCCHAR_EPTYP_SHIFT (18) /* Bits 18-19: Endpoint type */ -#define OTGHS_HCCHAR_EPTYP_MASK (3 << OTGHS_HCCHAR_EPTYP_SHIFT) -# define OTGHS_HCCHAR_EPTYP_CTRL (0 << OTGHS_HCCHAR_EPTYP_SHIFT) /* Control */ -# define OTGHS_HCCHAR_EPTYP_ISOC (1 << OTGHS_HCCHAR_EPTYP_SHIFT) /* Isochronous */ -# define OTGHS_HCCHAR_EPTYP_BULK (2 << OTGHS_HCCHAR_EPTYP_SHIFT) /* Bulk */ -# define OTGHS_HCCHAR_EPTYP_INTR (3 << OTGHS_HCCHAR_EPTYP_SHIFT) /* Interrupt */ - -#define OTGHS_HCCHAR_MCNT_SHIFT (20) /* Bits 20-21: Multicount */ -#define OTGHS_HCCHAR_MCNT_MASK (3 << OTGHS_HCCHAR_MCNT_SHIFT) -#define OTGHS_HCCHAR_DAD_SHIFT (22) /* Bits 22-28: Device address */ -#define OTGHS_HCCHAR_DAD_MASK (0x7f << OTGHS_HCCHAR_DAD_SHIFT) -#define OTGHS_HCCHAR_ODDFRM (1 << 29) /* Bit 29: Odd frame */ -#define OTGHS_HCCHAR_CHDIS (1 << 30) /* Bit 30: Channel disable */ -#define OTGHS_HCCHAR_CHENA (1 << 31) /* Bit 31: Channel enable */ - -/* Host channel-n interrupt and Host channel-0 interrupt mask registers */ - -#define OTGHS_HCINT_XFRC (1 << 0) /* Bit 0: Transfer completed */ -#define OTGHS_HCINT_CHH (1 << 1) /* Bit 1: Channel halted */ - /* Bit 2: Reserved, must be kept at reset value */ -#define OTGHS_HCINT_STALL (1 << 3) /* Bit 3: STALL response received interrupt */ -#define OTGHS_HCINT_NAK (1 << 4) /* Bit 4: NAK response received interrupt */ -#define OTGHS_HCINT_ACK (1 << 5) /* Bit 5: ACK response received/transmitted interrupt */ -#define OTGHS_HCINT_NYET (1 << 6) /* Bit 6: Response received interrupt */ -#define OTGHS_HCINT_TXERR (1 << 7) /* Bit 7: Transaction error */ -#define OTGHS_HCINT_BBERR (1 << 8) /* Bit 8: Babble error */ -#define OTGHS_HCINT_FRMOR (1 << 9) /* Bit 9: Frame overrun */ -#define OTGHS_HCINT_DTERR (1 << 10) /* Bit 10: Data toggle error */ - /* Bits 11-31 Reserved, must be kept at reset value */ - -/* Host channel-n interrupt register */ - -#define OTGHS_HCTSIZ_XFRSIZ_SHIFT (0) /* Bits 0-18: Transfer size */ -#define OTGHS_HCTSIZ_XFRSIZ_MASK (0x7ffff << OTGHS_HCTSIZ_XFRSIZ_SHIFT) -#define OTGHS_HCTSIZ_PKTCNT_SHIFT (19) /* Bits 19-28: Packet count */ -#define OTGHS_HCTSIZ_PKTCNT_MASK (0x3ff << OTGHS_HCTSIZ_PKTCNT_SHIFT) -#define OTGHS_HCTSIZ_DPID_SHIFT (29) /* Bits 29-30: Data PID */ -#define OTGHS_HCTSIZ_DPID_MASK (3 << OTGHS_HCTSIZ_DPID_SHIFT) -# define OTGHS_HCTSIZ_DPID_DATA0 (0 << OTGHS_HCTSIZ_DPID_SHIFT) -# define OTGHS_HCTSIZ_DPID_DATA2 (1 << OTGHS_HCTSIZ_DPID_SHIFT) -# define OTGHS_HCTSIZ_DPID_DATA1 (2 << OTGHS_HCTSIZ_DPID_SHIFT) -# define OTGHS_HCTSIZ_DPID_MDATA (3 << OTGHS_HCTSIZ_DPID_SHIFT) /* Non-control */ -# define OTGHS_HCTSIZ_PID_SETUP (3 << OTGHS_HCTSIZ_DPID_SHIFT) /* Control */ - -/* Bit 31 Reserved, - * must be kept at reset value - */ - -/* Device-mode control and status registers */ - -/* Device configuration register */ - -#define OTGHS_DCFG_DSPD_SHIFT (0) /* Bits 0-1: Device speed */ -#define OTGHS_DCFG_DSPD_MASK (3 << OTGHS_DCFG_DSPD_SHIFT) -# define OTGHS_DCFG_DSPD_FS (3 << OTGHS_DCFG_DSPD_SHIFT) /* Full speed */ - -#define OTGHS_DCFG_NZLSOHSK (1 << 2) /* Bit 2: Non-zero-length status OUT handshake */ - /* Bit 3: Reserved, must be kept at reset value */ -#define OTGHS_DCFG_DAD_SHIFT (4) /* Bits 4-10: Device address */ -#define OTGHS_DCFG_DAD_MASK (0x7f << OTGHS_DCFG_DAD_SHIFT) -#define OTGHS_DCFG_PFIVL_SHIFT (11) /* Bits 11-12: Periodic frame interval */ -#define OTGHS_DCFG_PFIVL_MASK (3 << OTGHS_DCFG_PFIVL_SHIFT) -# define OTGHS_DCFG_PFIVL_80PCT (0 << OTGHS_DCFG_PFIVL_SHIFT) /* 80% of the frame interval */ -# define OTGHS_DCFG_PFIVL_85PCT (1 << OTGHS_DCFG_PFIVL_SHIFT) /* 85% of the frame interval */ -# define OTGHS_DCFG_PFIVL_90PCT (2 << OTGHS_DCFG_PFIVL_SHIFT) /* 90% of the frame interval */ -# define OTGHS_DCFG_PFIVL_95PCT (3 << OTGHS_DCFG_PFIVL_SHIFT) /* 95% of the frame interval */ - -/* Bits 13-31 Reserved, - * must be kept at reset value - */ - -/* Device control register */ - -#define OTGHS_TESTMODE_DISABLED (0) /* Test mode disabled */ -#define OTGHS_TESTMODE_J (1) /* Test_J mode */ -#define OTGHS_TESTMODE_K (2) /* Test_K mode */ -#define OTGHS_TESTMODE_SE0_NAK (3) /* Test_SE0_NAK mode */ -#define OTGHS_TESTMODE_PACKET (4) /* Test_Packet mode */ -#define OTGHS_TESTMODE_FORCE (5) /* Test_Force_Enable */ - -#define OTGHS_DCTL_RWUSIG (1 << 0) /* Bit 0: Remote wakeup signaling */ -#define OTGHS_DCTL_SDIS (1 << 1) /* Bit 1: Soft disconnect */ -#define OTGHS_DCTL_GINSTS (1 << 2) /* Bit 2: Global IN NAK status */ -#define OTGHS_DCTL_GONSTS (1 << 3) /* Bit 3: Global OUT NAK status */ -#define OTGHS_DCTL_TCTL_SHIFT (4) /* Bits 4-6: Test control */ -#define OTGHS_DCTL_TCTL_MASK (7 << OTGHS_DCTL_TCTL_SHIFT) -# define OTGHS_DCTL_TCTL_DISABLED (0 << OTGHS_DCTL_TCTL_SHIFT) /* Test mode disabled */ -# define OTGHS_DCTL_TCTL_J (1 << OTGHS_DCTL_TCTL_SHIFT) /* Test_J mode */ -# define OTGHS_DCTL_TCTL_K (2 << OTGHS_DCTL_TCTL_SHIFT) /* Test_K mode */ -# define OTGHS_DCTL_TCTL_SE0_NAK (3 << OTGHS_DCTL_TCTL_SHIFT) /* Test_SE0_NAK mode */ -# define OTGHS_DCTL_TCTL_PACKET (4 << OTGHS_DCTL_TCTL_SHIFT) /* Test_Packet mode */ -# define OTGHS_DCTL_TCTL_FORCE (5 << OTGHS_DCTL_TCTL_SHIFT) /* Test_Force_Enable */ - -#define OTGHS_DCTL_SGINAK (1 << 7) /* Bit 7: Set global IN NAK */ -#define OTGHS_DCTL_CGINAK (1 << 8) /* Bit 8: Clear global IN NAK */ -#define OTGHS_DCTL_SGONAK (1 << 9) /* Bit 9: Set global OUT NAK */ -#define OTGHS_DCTL_CGONAK (1 << 10) /* Bit 10: Clear global OUT NAK */ -#define OTGHS_DCTL_POPRGDNE (1 << 11) /* Bit 11: Power-on programming done */ - /* Bits 12-31: Reserved, must be kept at reset value */ - -/* Device status register */ - -#define OTGHS_DSTS_SUSPSTS (1 << 0) /* Bit 0: Suspend status */ -#define OTGHS_DSTS_ENUMSPD_SHIFT (1) /* Bits 1-2: Enumerated speed */ -#define OTGHS_DSTS_ENUMSPD_MASK (3 << OTGHS_DSTS_ENUMSPD_SHIFT) -# define OTGHS_DSTS_ENUMSPD_FS (3 << OTGHS_DSTS_ENUMSPD_MASK) /* Full speed */ - -/* Bits 4-7: Reserved, - * must be kept at reset value - */ -#define OTGHS_DSTS_EERR (1 << 3) /* Bit 3: Erratic error */ -#define OTGHS_DSTS_SOFFN_SHIFT (8) /* Bits 8-21: Frame number of the received SOF */ -#define OTGHS_DSTS_SOFFN_MASK (0x3fff << OTGHS_DSTS_SOFFN_SHIFT) -#define OTGHS_DSTS_SOFFN0 (1 << 8) /* Bits 8: Frame number even/odd bit */ -#define OTGHS_DSTS_SOFFN_EVEN 0 -#define OTGHS_DSTS_SOFFN_ODD OTGHS_DSTS_SOFFN0 - /* Bits 22-31: Reserved, must be kept at reset value */ - -/* Device IN endpoint common interrupt mask register */ - -#define OTGHS_DIEPMSK_XFRCM (1 << 0) /* Bit 0: Transfer completed interrupt mask */ -#define OTGHS_DIEPMSK_EPDM (1 << 1) /* Bit 1: Endpoint disabled interrupt mask */ - /* Bit 2: Reserved, must be kept at reset value */ -#define OTGHS_DIEPMSK_TOM (1 << 3) /* Bit 3: Timeout condition mask (Non-isochronous endpoints) */ -#define OTGHS_DIEPMSK_ITTXFEMSK (1 << 4) /* Bit 4: IN token received when TxFIFO empty mask */ -#define OTGHS_DIEPMSK_INEPNMM (1 << 5) /* Bit 5: IN token received with EP mismatch mask */ -#define OTGHS_DIEPMSK_INEPNEM (1 << 6) /* Bit 6: IN endpoint NAK effective mask */ - /* Bits 7-31: Reserved, must be kept at reset value */ - -/* Device OUT endpoint common interrupt mask register */ - -#define OTGHS_DOEPMSK_XFRCM (1 << 0) /* Bit 0: Transfer completed interrupt mask */ -#define OTGHS_DOEPMSK_EPDM (1 << 1) /* Bit 1: Endpoint disabled interrupt mask */ - /* Bit 2: Reserved, must be kept at reset value */ -#define OTGHS_DOEPMSK_STUPM (1 << 3) /* Bit 3: SETUP phase done mask */ -#define OTGHS_DOEPMSK_OTEPDM (1 << 4) /* Bit 4: OUT token received when endpoint disabled mask */ - /* Bits 5-31: Reserved, must be kept at reset value */ - -/* Device all endpoints interrupt and All endpoints interrupt - * mask registers - */ - -#define OTGHS_DAINT_IEP_SHIFT (0) /* Bits 0-15: IN endpoint interrupt bits */ -#define OTGHS_DAINT_IEP_MASK (0xffff << OTGHS_DAINT_IEP_SHIFT) -# define OTGHS_DAINT_IEP(n) (1 << (n)) -#define OTGHS_DAINT_OEP_SHIFT (16) /* Bits 16-31: OUT endpoint interrupt bits */ -#define OTGHS_DAINT_OEP_MASK (0xffff << OTGHS_DAINT_OEP_SHIFT) -# define OTGHS_DAINT_OEP(n) (1 << ((n)+16)) - -/* Device VBUS discharge time register */ - -#define OTGHS_DVBUSDIS_MASK (0xffff) - -/* Device VBUS pulsing time register */ - -#define OTGHS_DVBUSPULSE_MASK (0xfff) - -/* Device IN endpoint FIFO empty interrupt mask register */ - -#define OTGHS_DIEPEMPMSK(n) (1 << (n)) - -/* Device control IN endpoint 0 control register */ - -#define OTGHS_DIEPCTL0_MPSIZ_SHIFT (0) /* Bits 0-1: Maximum packet size */ -#define OTGHS_DIEPCTL0_MPSIZ_MASK (3 << OTGHS_DIEPCTL0_MPSIZ_SHIFT) -# define OTGHS_DIEPCTL0_MPSIZ_64 (0 << OTGHS_DIEPCTL0_MPSIZ_SHIFT) /* 64 bytes */ -# define OTGHS_DIEPCTL0_MPSIZ_32 (1 << OTGHS_DIEPCTL0_MPSIZ_SHIFT) /* 32 bytes */ -# define OTGHS_DIEPCTL0_MPSIZ_16 (2 << OTGHS_DIEPCTL0_MPSIZ_SHIFT) /* 16 bytes */ -# define OTGHS_DIEPCTL0_MPSIZ_8 (3 << OTGHS_DIEPCTL0_MPSIZ_SHIFT) /* 8 bytes */ - -/* Bits 2-14: Reserved, - * must be kept at reset value - */ -#define OTGHS_DIEPCTL0_USBAEP (1 << 15) /* Bit 15: USB active endpoint */ - /* Bit 16: Reserved, must be kept at reset value */ -#define OTGHS_DIEPCTL0_NAKSTS (1 << 17) /* Bit 17: NAK status */ -#define OTGHS_DIEPCTL0_EPTYP_SHIFT (18) /* Bits 18-19: Endpoint type */ -#define OTGHS_DIEPCTL0_EPTYP_MASK (3 << OTGHS_DIEPCTL0_EPTYP_SHIFT) -# define OTGHS_DIEPCTL0_EPTYP_CTRL (0 << OTGHS_DIEPCTL0_EPTYP_SHIFT) /* Control (hard-coded) */ - -/* Bit 20: Reserved, - * must be kept at reset value - */ -#define OTGHS_DIEPCTL0_STALL (1 << 21) /* Bit 21: STALL handshake */ -#define OTGHS_DIEPCTL0_TXFNUM_SHIFT (22) /* Bits 22-25: TxFIFO number */ -#define OTGHS_DIEPCTL0_TXFNUM_MASK (15 << OTGHS_DIEPCTL0_TXFNUM_SHIFT) -#define OTGHS_DIEPCTL0_CNAK (1 << 26) /* Bit 26: Clear NAK */ -#define OTGHS_DIEPCTL0_SNAK (1 << 27) /* Bit 27: Set NAK */ - /* Bits 28-29: Reserved, must be kept at reset value */ -#define OTGHS_DIEPCTL0_EPDIS (1 << 30) /* Bit 30: Endpoint disable */ -#define OTGHS_DIEPCTL0_EPENA (1 << 31) /* Bit 31: Endpoint enable */ - -/* Device control IN endpoint n control register */ - -#define OTGHS_DIEPCTL_MPSIZ_SHIFT (0) /* Bits 0-10: Maximum packet size */ -#define OTGHS_DIEPCTL_MPSIZ_MASK (0x7ff << OTGHS_DIEPCTL_MPSIZ_SHIFT) - /* Bits 11-14: Reserved, must be kept at reset value */ -#define OTGHS_DIEPCTL_USBAEP (1 << 15) /* Bit 15: USB active endpoint */ -#define OTGHS_DIEPCTL_EONUM (1 << 16) /* Bit 16: Even/odd frame */ -# define OTGHS_DIEPCTL_EVEN (0) -# define OTGHS_DIEPCTL_ODD OTGHS_DIEPCTL_EONUM -# define OTGHS_DIEPCTL_DATA0 (0) -# define OTGHS_DIEPCTL_DATA1 OTGHS_DIEPCTL_EONUM -#define OTGHS_DIEPCTL_NAKSTS (1 << 17) /* Bit 17: NAK status */ -#define OTGHS_DIEPCTL_EPTYP_SHIFT (18) /* Bits 18-19: Endpoint type */ -#define OTGHS_DIEPCTL_EPTYP_MASK (3 << OTGHS_DIEPCTL_EPTYP_SHIFT) -# define OTGHS_DIEPCTL_EPTYP_CTRL (0 << OTGHS_DIEPCTL_EPTYP_SHIFT) /* Control */ -# define OTGHS_DIEPCTL_EPTYP_ISOC (1 << OTGHS_DIEPCTL_EPTYP_SHIFT) /* Isochronous */ -# define OTGHS_DIEPCTL_EPTYP_BULK (2 << OTGHS_DIEPCTL_EPTYP_SHIFT) /* Bulk */ -# define OTGHS_DIEPCTL_EPTYP_INTR (3 << OTGHS_DIEPCTL_EPTYP_SHIFT) /* Interrupt */ - -/* Bit 20: Reserved, - * must be kept at reset value - */ -#define OTGHS_DIEPCTL_STALL (1 << 21) /* Bit 21: STALL handshake */ -#define OTGHS_DIEPCTL_TXFNUM_SHIFT (22) /* Bits 22-25: TxFIFO number */ -#define OTGHS_DIEPCTL_TXFNUM_MASK (15 << OTGHS_DIEPCTL_TXFNUM_SHIFT) -#define OTGHS_DIEPCTL_CNAK (1 << 26) /* Bit 26: Clear NAK */ -#define OTGHS_DIEPCTL_SNAK (1 << 27) /* Bit 27: Set NAK */ -#define OTGHS_DIEPCTL_SD0PID (1 << 28) /* Bit 28: Set DATA0 PID (interrupt/bulk) */ -#define OTGHS_DIEPCTL_SEVNFRM (1 << 28) /* Bit 28: Set even frame (isochronous)) */ -#define OTGHS_DIEPCTL_SODDFRM (1 << 29) /* Bit 29: Set odd frame (isochronous) */ -#define OTGHS_DIEPCTL_EPDIS (1 << 30) /* Bit 30: Endpoint disable */ -#define OTGHS_DIEPCTL_EPENA (1 << 31) /* Bit 31: Endpoint enable */ - -/* Device endpoint-n interrupt register */ - -#define OTGHS_DIEPINT_XFRC (1 << 0) /* Bit 0: Transfer completed interrupt */ -#define OTGHS_DIEPINT_EPDISD (1 << 1) /* Bit 1: Endpoint disabled interrupt */ - /* Bit 2: Reserved, must be kept at reset value */ -#define OTGHS_DIEPINT_TOC (1 << 3) /* Bit 3: Timeout condition */ -#define OTGHS_DIEPINT_ITTXFE (1 << 4) /* Bit 4: IN token received when TxFIFO is empty */ - /* Bit 5: Reserved, must be kept at reset value */ -#define OTGHS_DIEPINT_INEPNE (1 << 6) /* Bit 6: IN endpoint NAK effective */ -#define OTGHS_DIEPINT_TXFE (1 << 7) /* Bit 7: Transmit FIFO empty */ - /* Bits 8-31: Reserved, must be kept at reset value */ - -/* Device IN endpoint 0 transfer size register */ - -#define OTGHS_DIEPTSIZ0_XFRSIZ_SHIFT (0) /* Bits 0-6: Transfer size */ -#define OTGHS_DIEPTSIZ0_XFRSIZ_MASK (0x7f << OTGHS_DIEPTSIZ0_XFRSIZ_SHIFT) - /* Bits 7-18: Reserved, must be kept at reset value */ -#define OTGHS_DIEPTSIZ0_PKTCNT_SHIFT (19) /* Bits 19-20: Packet count */ -#define OTGHS_DIEPTSIZ0_PKTCNT_MASK (3 << OTGHS_DIEPTSIZ0_PKTCNT_SHIFT) - /* Bits 21-31: Reserved, must be kept at reset value */ - -/* Device IN endpoint n transfer size register */ - -#define OTGHS_DIEPTSIZ_XFRSIZ_SHIFT (0) /* Bits 0-18: Transfer size */ -#define OTGHS_DIEPTSIZ_XFRSIZ_MASK (0x7ffff << OTGHS_DIEPTSIZ_XFRSIZ_SHIFT) -#define OTGHS_DIEPTSIZ_PKTCNT_SHIFT (19) /* Bit 19-28: Packet count */ -#define OTGHS_DIEPTSIZ_PKTCNT_MASK (0x3ff << OTGHS_DIEPTSIZ_PKTCNT_SHIFT) -#define OTGHS_DIEPTSIZ_MCNT_SHIFT (29) /* Bits 29-30: Multi count */ -#define OTGHS_DIEPTSIZ_MCNT_MASK (3 << OTGHS_DIEPTSIZ_MCNT_SHIFT) - /* Bit 31: Reserved, must be kept at reset value */ - -/* Device OUT endpoint TxFIFO status register */ - -#define OTGHS_DTXFSTS_MASK (0xffff) - -/* Device OUT endpoint 0 control register */ - -#define OTGHS_DOEPCTL0_MPSIZ_SHIFT (0) /* Bits 0-1: Maximum packet size */ -#define OTGHS_DOEPCTL0_MPSIZ_MASK (3 << OTGHS_DOEPCTL0_MPSIZ_SHIFT) -# define OTGHS_DOEPCTL0_MPSIZ_64 (0 << OTGHS_DOEPCTL0_MPSIZ_SHIFT) /* 64 bytes */ -# define OTGHS_DOEPCTL0_MPSIZ_32 (1 << OTGHS_DOEPCTL0_MPSIZ_SHIFT) /* 32 bytes */ -# define OTGHS_DOEPCTL0_MPSIZ_16 (2 << OTGHS_DOEPCTL0_MPSIZ_SHIFT) /* 16 bytes */ -# define OTGHS_DOEPCTL0_MPSIZ_8 (3 << OTGHS_DOEPCTL0_MPSIZ_SHIFT) /* 8 bytes */ - -/* Bits 2-14: Reserved, - * must be kept at reset value - */ -#define OTGHS_DOEPCTL0_USBAEP (1 << 15) /* Bit 15: USB active endpoint */ - /* Bit 16: Reserved, must be kept at reset value */ -#define OTGHS_DOEPCTL0_NAKSTS (1 << 17) /* Bit 17: NAK status */ -#define OTGHS_DOEPCTL0_EPTYP_SHIFT (18) /* Bits 18-19: Endpoint type */ -#define OTGHS_DOEPCTL0_EPTYP_MASK (3 << OTGHS_DOEPCTL0_EPTYP_SHIFT) -# define OTGHS_DOEPCTL0_EPTYP_CTRL (0 << OTGHS_DOEPCTL0_EPTYP_SHIFT) /* Control (hard-coded) */ - -#define OTGHS_DOEPCTL0_SNPM (1 << 20) /* Bit 20: Snoop mode */ -#define OTGHS_DOEPCTL0_STALL (1 << 21) /* Bit 21: STALL handshake */ - /* Bits 22-25: Reserved, must be kept at reset value */ -#define OTGHS_DOEPCTL0_CNAK (1 << 26) /* Bit 26: Clear NAK */ -#define OTGHS_DOEPCTL0_SNAK (1 << 27) /* Bit 27: Set NAK */ - /* Bits 28-29: Reserved, must be kept at reset value */ -#define OTGHS_DOEPCTL0_EPDIS (1 << 30) /* Bit 30: Endpoint disable */ -#define OTGHS_DOEPCTL0_EPENA (1 << 31) /* Bit 31: Endpoint enable */ - -/* Device OUT endpoint n control register */ - -#define OTGHS_DOEPCTL_MPSIZ_SHIFT (0) /* Bits 0-10: Maximum packet size */ -#define OTGHS_DOEPCTL_MPSIZ_MASK (0x7ff << OTGHS_DOEPCTL_MPSIZ_SHIFT) - /* Bits 11-14: Reserved, must be kept at reset value */ -#define OTGHS_DOEPCTL_USBAEP (1 << 15) /* Bit 15: USB active endpoint */ -#define OTGHS_DOEPCTL_DPID (1 << 16) /* Bit 16: Endpoint data PID (interrupt/bulk) */ -# define OTGHS_DOEPCTL_DATA0 (0) -# define OTGHS_DOEPCTL_DATA1 OTGHS_DOEPCTL_DPID -#define OTGHS_DOEPCTL_EONUM (1 << 16) /* Bit 16: Even/odd frame (isochronous) */ -# define OTGHS_DOEPCTL_EVEN (0) -# define OTGHS_DOEPCTL_ODD OTGHS_DOEPCTL_EONUM -#define OTGHS_DOEPCTL_NAKSTS (1 << 17) /* Bit 17: NAK status */ -#define OTGHS_DOEPCTL_EPTYP_SHIFT (18) /* Bits 18-19: Endpoint type */ -#define OTGHS_DOEPCTL_EPTYP_MASK (3 << OTGHS_DOEPCTL_EPTYP_SHIFT) -# define OTGHS_DOEPCTL_EPTYP_CTRL (0 << OTGHS_DOEPCTL_EPTYP_SHIFT) /* Control */ -# define OTGHS_DOEPCTL_EPTYP_ISOC (1 << OTGHS_DOEPCTL_EPTYP_SHIFT) /* Isochronous */ -# define OTGHS_DOEPCTL_EPTYP_BULK (2 << OTGHS_DOEPCTL_EPTYP_SHIFT) /* Bulk */ -# define OTGHS_DOEPCTL_EPTYP_INTR (3 << OTGHS_DOEPCTL_EPTYP_SHIFT) /* Interrupt */ - -#define OTGHS_DOEPCTL_SNPM (1 << 20) /* Bit 20: Snoop mode */ -#define OTGHS_DOEPCTL_STALL (1 << 21) /* Bit 21: STALL handshake */ - /* Bits 22-25: Reserved, must be kept at reset value */ -#define OTGHS_DOEPCTL_CNAK (1 << 26) /* Bit 26: Clear NAK */ -#define OTGHS_DOEPCTL_SNAK (1 << 27) /* Bit 27: Set NAK */ -#define OTGHS_DOEPCTL_SD0PID (1 << 28) /* Bit 28: Set DATA0 PID (interrupt/bulk) */ -#define OTGHS_DOEPCTL_SEVNFRM (1 << 28) /* Bit 28: Set even frame (isochronous) */ -#define OTGHS_DOEPCTL_SD1PID (1 << 29) /* Bit 29: Set DATA1 PID (interrupt/bulk) */ -#define OTGHS_DOEPCTL_SODDFRM (1 << 29) /* Bit 29: Set odd frame (isochronous */ -#define OTGHS_DOEPCTL_EPDIS (1 << 30) /* Bit 30: Endpoint disable */ -#define OTGHS_DOEPCTL_EPENA (1 << 31) /* Bit 31: Endpoint enable */ - -/* Device endpoint-n interrupt register */ - -#define OTGHS_DOEPINT_XFRC (1 << 0) /* Bit 0: Transfer completed interrupt */ -#define OTGHS_DOEPINT_EPDISD (1 << 1) /* Bit 1: Endpoint disabled interrupt */ - /* Bit 2: Reserved, must be kept at reset value */ -#define OTGHS_DOEPINT_SETUP (1 << 3) /* Bit 3: SETUP phase done */ -#define OTGHS_DOEPINT_OTEPDIS (1 << 4) /* Bit 4: OUT token received when endpoint disabled */ - /* Bit 5: Reserved, must be kept at reset value */ -#define OTGHS_DOEPINT_B2BSTUP (1 << 6) /* Bit 6: Back-to-back SETUP packets received */ - /* Bits 7-31: Reserved, must be kept at reset value */ - -/* Device OUT endpoint-0 transfer size register */ - -#define OTGHS_DOEPTSIZ0_XFRSIZ_SHIFT (0) /* Bits 0-6: Transfer size */ -#define OTGHS_DOEPTSIZ0_XFRSIZ_MASK (0x7f << OTGHS_DOEPTSIZ0_XFRSIZ_SHIFT) - /* Bits 7-18: Reserved, must be kept at reset value */ -#define OTGHS_DOEPTSIZ0_PKTCNT (1 << 19) /* Bit 19 PKTCNT: Packet count */ - /* Bits 20-28: Reserved, must be kept at reset value */ -#define OTGHS_DOEPTSIZ0_STUPCNT_SHIFT (29) /* Bits 29-30: SETUP packet count */ -#define OTGHS_DOEPTSIZ0_STUPCNT_MASK (3 << OTGHS_DOEPTSIZ0_STUPCNT_SHIFT) - /* Bit 31: Reserved, must be kept at reset value */ - -/* Device OUT endpoint-n transfer size register */ - -#define OTGHS_DOEPTSIZ_XFRSIZ_SHIFT (0) /* Bits 0-18: Transfer size */ -#define OTGHS_DOEPTSIZ_XFRSIZ_MASK (0x7ffff << OTGHS_DOEPTSIZ_XFRSIZ_SHIFT) -#define OTGHS_DOEPTSIZ_PKTCNT_SHIFT (19) /* Bit 19-28: Packet count */ -#define OTGHS_DOEPTSIZ_PKTCNT_MASK (0x3ff << OTGHS_DOEPTSIZ_PKTCNT_SHIFT) -#define OTGHS_DOEPTSIZ_STUPCNT_SHIFT (29) /* Bits 29-30: SETUP packet count */ -#define OTGHS_DOEPTSIZ_STUPCNT_MASK (3 << OTGHS_DOEPTSIZ_STUPCNT_SHIFT) -#define OTGHS_DOEPTSIZ_RXDPID_SHIFT (29) /* Bits 29-30: Received data PID */ -#define OTGHS_DOEPTSIZ_RXDPID_MASK (3 << OTGHS_DOEPTSIZ_RXDPID_SHIFT) -# define OTGHS_DOEPTSIZ_RXDPID_DATA0 (0 << OTGHS_DOEPTSIZ_RXDPID_SHIFT) -# define OTGHS_DOEPTSIZ_RXDPID_DATA2 (1 << OTGHS_DOEPTSIZ_RXDPID_SHIFT) -# define OTGHS_DOEPTSIZ_RXDPID_DATA1 (2 << OTGHS_DOEPTSIZ_RXDPID_SHIFT) -# define OTGHS_DOEPTSIZ_RXDPID_MDATA (3 << OTGHS_DOEPTSIZ_RXDPID_SHIFT) - /* Bit 31: Reserved, must be kept at reset value */ - -/* Power and clock gating control register */ - -#define OTGHS_PCGCCTL_STPPCLK (1 << 0) /* Bit 0: Stop PHY clock */ -#define OTGHS_PCGCCTL_GATEHCLK (1 << 1) /* Bit 1: Gate HCLK */ - /* Bits 2-3: Reserved, must be kept at reset value */ -#define OTGHS_PCGCCTL_PHYSUSP (1 << 4) /* Bit 4: PHY Suspended */ - /* Bits 5-31: Reserved, must be kept at reset value */ - -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_OTGHS_H */ diff --git a/arch/arm/src/stm32/hardware/stm32_pinmap.h b/arch/arm/src/stm32/hardware/stm32_pinmap.h deleted file mode 100644 index 7e35c3b9b755c..0000000000000 --- a/arch/arm/src/stm32/hardware/stm32_pinmap.h +++ /dev/null @@ -1,136 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/hardware/stm32_pinmap.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_PINMAP_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_PINMAP_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -/* STM32L EnergyLite Line ***************************************************/ - -#if defined(CONFIG_STM32_ENERGYLITE) - -/* STM32L15xx family */ - -# if defined(CONFIG_STM32_STM32L15XX) -# include "hardware/stm32l15xxx_pinmap.h" -# else -# error "Unsupported EnergyLite chip" -# endif - -/* STM32 F1 Family **********************************************************/ - -#elif defined(CONFIG_STM32_STM32F10XX) - -/* STM32F100 Value Line */ - -# if defined(CONFIG_STM32_VALUELINE) -# include "hardware/stm32f100_pinmap.h" - -/* STM32 F102 USB Access Medium Density Family */ -# elif defined(CONFIG_ARCH_CHIP_STM32F102CB) -# include "hardware/stm32f102_pinmap.h" - -/* STM32 F103 Low / Medium Density Family */ -# elif defined(CONFIG_ARCH_CHIP_STM32F103C4) || \ - defined(CONFIG_ARCH_CHIP_STM32F103C8) || \ - defined(CONFIG_ARCH_CHIP_STM32F103CB) -# include "hardware/stm32f103c_pinmap.h" - -/* STM32 F103 High Density Family */ - -/* STM32F103RC, STM32F103RD, and STM32F103RE are all provided in 64 pin - * packages and differ only in the available FLASH and SRAM. - */ - -# elif defined(CONFIG_ARCH_CHIP_STM32F103RB) || \ - defined(CONFIG_ARCH_CHIP_STM32F103RC) || \ - defined(CONFIG_ARCH_CHIP_STM32F103RD) || \ - defined(CONFIG_ARCH_CHIP_STM32F103RE) || \ - defined(CONFIG_ARCH_CHIP_STM32F103RG) -# include "hardware/stm32f103r_pinmap.h" - -/* STM32F103VC, STM32F103VD, and STM32F103VE are all provided in 100 pin - * packages and differ only in the available FLASH and SRAM. - */ - -# elif defined(CONFIG_ARCH_CHIP_STM32F103VC) || defined(CONFIG_ARCH_CHIP_STM32F103VE) -# include "hardware/stm32f103v_pinmap.h" - -/* STM32F103ZC, STM32F103ZD, and STM32F103ZE are all provided in 144 pin - * packages and differ only in the available FLASH and SRAM. - */ -# elif defined(CONFIG_ARCH_CHIP_STM32F103ZE) -# include "hardware/stm32f103z_pinmap.h" - -/* STM32 F105/F107 Connectivity Line */ - -# elif defined(CONFIG_ARCH_CHIP_STM32F105VB) -# include "hardware/stm32f105v_pinmap.h" - -# elif defined(CONFIG_ARCH_CHIP_STM32F105RB) -# include "hardware/stm32f105r_pinmap.h" - -# elif defined(CONFIG_ARCH_CHIP_STM32F107VC) -# include "hardware/stm32f107v_pinmap.h" -# else -# error "Unsupported STM32F10XXX chip" -# endif - -/* STM32 F2 Family **********************************************************/ - -#elif defined(CONFIG_STM32_STM32F20XX) -# include "hardware/stm32f20xxx_pinmap.h" - -/* STM32 F3 Family **********************************************************/ - -#elif defined(CONFIG_STM32_STM32F30XX) -# include "hardware/stm32f30xxx_pinmap.h" -#elif defined(CONFIG_STM32_STM32F33XX) -# include "hardware/stm32f33xxx_pinmap.h" -#elif defined(CONFIG_STM32_STM32F37XX) -# include "hardware/stm32f37xxx_pinmap.h" - -/* STM32 F412 Family ********************************************************/ - -#elif defined(CONFIG_STM32_STM32F412) -# include "hardware/stm32f412xx_pinmap.h" - -/* STM32 F4 Family **********************************************************/ - -#elif defined(CONFIG_STM32_STM32F4XXX) -# include "hardware/stm32f40xxx_pinmap.h" - -/* STM32 G4 Family **********************************************************/ - -#elif defined(CONFIG_STM32_STM32G4XXX) -# include "hardware/stm32g4xxxx_pinmap.h" - -#else -# error "No pinmap file for this STM32 chip" -#endif - -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_PINMAP_H */ diff --git a/arch/arm/src/stm32/hardware/stm32_pwr.h b/arch/arm/src/stm32/hardware/stm32_pwr.h deleted file mode 100644 index 18598c7716769..0000000000000 --- a/arch/arm/src/stm32/hardware/stm32_pwr.h +++ /dev/null @@ -1,165 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/hardware/stm32_pwr.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_PWR_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_PWR_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include "chip.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Register Offsets *********************************************************/ - -#define STM32_PWR_CR_OFFSET 0x0000 /* Power control register */ -#define STM32_PWR_CSR_OFFSET 0x0004 /* Power control/status register */ - -/* Register Addresses *******************************************************/ - -#define STM32_PWR_CR (STM32_PWR_BASE+STM32_PWR_CR_OFFSET) -#define STM32_PWR_CSR (STM32_PWR_BASE+STM32_PWR_CSR_OFFSET) - -/* Register Bitfield Definitions ********************************************/ - -/* Power control register */ - -#define PWR_CR_LPDS (1 << 0) /* Bit 0: Low-Power Deepsleep/sleep; low power run */ -#define PWR_CR_PDDS (1 << 1) /* Bit 1: Power Down Deepsleep */ -#define PWR_CR_CWUF (1 << 2) /* Bit 2: Clear Wakeup Flag */ -#define PWR_CR_CSBF (1 << 3) /* Bit 3: Clear Standby Flag */ -#define PWR_CR_PVDE (1 << 4) /* Bit 4: Power Voltage Detector Enable */ - -#define PWR_CR_PLS_SHIFT (5) /* Bits 7-5: PVD Level Selection */ -#define PWR_CR_PLS_MASK (7 << PWR_CR_PLS_SHIFT) -# if defined(CONFIG_STM32_STM32L15XX) -# define PWR_CR_1p9V (0 << PWR_CR_PLS_SHIFT) /* 000: 1.9 V */ -# define PWR_CR_2p1V (1 << PWR_CR_PLS_SHIFT) /* 001: 2.1 V */ -# define PWR_CR_2p3V (2 << PWR_CR_PLS_SHIFT) /* 010: 2.3 V */ -# define PWR_CR_2p5V (3 << PWR_CR_PLS_SHIFT) /* 011: 2.5 V */ -# define PWR_CR_2p7V (4 << PWR_CR_PLS_SHIFT) /* 100: 2.7 V */ -# define PWR_CR_2p9V (5 << PWR_CR_PLS_SHIFT) /* 101: 2.9 V */ -# define PWR_CR_3p1V (6 << PWR_CR_PLS_SHIFT) /* 110: 3.1 V */ -# define PWR_CR_EXT (7 << PWR_CR_PLS_SHIFT) /* 111: External input analog voltage */ -# else -# define PWR_CR_2p2V (0 << PWR_CR_PLS_SHIFT) /* 000: 2.2V */ -# define PWR_CR_2p3V (1 << PWR_CR_PLS_SHIFT) /* 001: 2.3V */ -# define PWR_CR_2p4V (2 << PWR_CR_PLS_SHIFT) /* 010: 2.4V */ -# define PWR_CR_2p5V (3 << PWR_CR_PLS_SHIFT) /* 011: 2.5V */ -# define PWR_CR_2p6V (4 << PWR_CR_PLS_SHIFT) /* 100: 2.6V */ -# define PWR_CR_2p7V (5 << PWR_CR_PLS_SHIFT) /* 101: 2.7V */ -# define PWR_CR_2p8V (6 << PWR_CR_PLS_SHIFT) /* 110: 2.8V */ -# define PWR_CR_2p9V (7 << PWR_CR_PLS_SHIFT) /* 111: 2.9V */ -# endif -#define PWR_CR_DBP (1 << 8) /* Bit 8: Disable Backup Domain write protection */ - -#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) -# define PWR_CR_FPDS (1 << 9) /* Bit 9: Flash power down in Stop mode */ -# if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429) || \ - defined(CONFIG_STM32_STM32F446) || defined(CONFIG_STM32_STM32F469) || \ - defined(CONFIG_STM32_STM32F412) -# define PWR_CR_ADCDC1 (1 << 13) /* Bit 13: see AN4073 for details */ -# define PWR_CR_VOS_MASK (3 << 14) /* Bits 14-15: Regulator voltage scaling output selection */ -# define PWR_CR_VOS_SCALE_1 (3 << 14) /* Fmax = 168MHz */ -# define PWR_CR_VOS_SCALE_2 (2 << 14) /* Fmax = 144MHz */ -# define PWR_CR_VOS_SCALE_3 (1 << 14) /* Fmax = 120MHz */ -# else -# define PWR_CR_VOS (1 << 14) /* Bit 14: Regulator voltage scaling output selection */ - /* 0: Fmax = 144MHz 1: Fmax = 168MHz */ -# endif -#endif - -#if defined(CONFIG_STM32_STM32F37XX) -#define PWR_CR_ENSD1 (1 << 9) /* Bit 9: Enable SDADC1 */ -#define PWR_CR_ENSD2 (1 << 10) /* Bit 10: Enable SDADC2 */ -#define PWR_CR_ENSD3 (1 << 11) /* Bit 11: Enable SDADC3 */ -#endif - -#if defined(CONFIG_STM32_STM32L15XX) -# define PWR_CR_ULP (1 << 9) /* Ultralow power mode */ -# define PWR_CR_FWU (1 << 10) /* Fast wake-up */ -# define PWR_CR_VOS_MASK (3 << 11) /* Bits 11-12: Regulator voltage scaling output selection */ -# define PWR_CR_VOS_SCALE_1 (1 << 11) /* 1.8 V (range 1) PLL VCO Max = 96MHz */ -# define PWR_CR_VOS_SCALE_2 (2 << 11) /* 1.5 V (range 2) PLL VCO Max = 64MHz */ -# define PWR_CR_VOS_SCALE_3 (3 << 11) /* 1.2 V (range 3) PLL VCO Max = 24MHz */ -# define PWR_CR_LPRUN (1 << 14) /* Low power run mode */ -#endif - -#if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429) || \ - defined(CONFIG_STM32_STM32F446) || defined(CONFIG_STM32_STM32F469) -# define PWR_CR_ODEN (1 << 16) /* Over Drive enable */ -# define PWR_CR_ODSWEN (1 << 17) /* Over Drive switch enabled */ -#endif - -#if defined(CONFIG_STM32_STM32F446) || defined(CONFIG_STM32_STM32F412) -# define PWR_CR_FMSSR (1 << 20) /* Flash Memory Stop while System Run */ -# define PWR_CR_FISSR (1 << 21) /* Flash Interface Stop while System Run*/ -#endif - -/* Power control/status register */ - -#define PWR_CSR_WUF (1 << 0) /* Bit 0: Wakeup Flag */ -#define PWR_CSR_SBF (1 << 1) /* Bit 1: Standby Flag */ -#define PWR_CSR_PVDO (1 << 2) /* Bit 2: PVD Output */ - -#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F37XX) || \ - defined(CONFIG_STM32_STM32F4XXX) -# define PWR_CSR_BRR (1 << 3) /* Bit 3: Backup regulator ready */ -#elif defined(CONFIG_STM32_STM32L15XX) -# define PWR_CSR_VREFINTRDYF (1 << 3) /* Bit 3: Internal voltage reference (VREFINT) ready flag */ -# define PWR_CSR_VOSF (1 << 4) /* Bit 4: Voltage Scaling select flag */ -# define PWR_CSR_REGLPF (1 << 5) /* Bit 5: Regulator LP flag */ -#endif - -#if defined(CONFIG_STM32_STM32F30XX) -# define PWR_CSR_EWUP1 (1 << 8) /* Bit 8: Enable WKUP1 pin */ -# define PWR_CSR_EWUP2 (1 << 9) /* Bit 9: Enable WKUP2 pin */ -#elif defined(CONFIG_STM32_STM32L15XX) || defined(CONFIG_STM32_STM32F33XX) || \ - defined(CONFIG_STM32_STM32F37XX) -# define PWR_CSR_EWUP1 (1 << 8) /* Bit 8: Enable WKUP1 pin */ -# define PWR_CSR_EWUP2 (1 << 9) /* Bit 9: Enable WKUP2 pin */ -# define PWR_CSR_EWUP3 (1 << 10) /* Bit 10: Enable WKUP3 pin */ -#elif defined(CONFIG_STM32_STM32F412) -# define PWR_CSR_EWUP3 (1 << 6) /* Bit 6: Enable WKUP3 pin */ -# define PWR_CSR_EWUP2 (1 << 7) /* Bit 7: Enable WKUP2 pin */ -# define PWR_CSR_EWUP1 (1 << 8) /* Bit 8: Enable WKUP1 pin */ -#else -# define PWR_CSR_EWUP (1 << 8) /* Bit 8: Enable WKUP pin */ -#endif - -#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) -# define PWR_CSR_BRE (1 << 9) /* Bit 9: Backup regulator enable */ -# define PWR_CSR_VOSRDY (1 << 14) /* Bit 14: Regulator voltage scaling output selection ready bite */ -#endif - -#if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429) || \ - defined(CONFIG_STM32_STM32F446) || defined(CONFIG_STM32_STM32F469) -# define PWR_CSR_ODRDY (1 << 16) /* Bit 16: Over Drive generator ready */ -# define PWR_CSR_ODSWRDY (1 << 17) /* Bit 17: Over Drive Switch ready */ -#endif - -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_PWR_H */ diff --git a/arch/arm/src/stm32/hardware/stm32_rng.h b/arch/arm/src/stm32/hardware/stm32_rng.h deleted file mode 100644 index 645994e2f66eb..0000000000000 --- a/arch/arm/src/stm32/hardware/stm32_rng.h +++ /dev/null @@ -1,64 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/hardware/stm32_rng.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_RNG_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_RNG_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include "chip.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Register Offsets *********************************************************/ - -#define STM32_RNG_CR_OFFSET 0x0000 /* RNG Control Register */ -#define STM32_RNG_SR_OFFSET 0x0004 /* RNG Status Register */ -#define STM32_RNG_DR_OFFSET 0x0008 /* RNG Data Register */ - -/* Register Addresses *******************************************************/ - -#define STM32_RNG_CR (STM32_RNG_BASE+STM32_RNG_CR_OFFSET) -#define STM32_RNG_SR (STM32_RNG_BASE+STM32_RNG_SR_OFFSET) -#define STM32_RNG_DR (STM32_RNG_BASE+STM32_RNG_DR_OFFSET) - -/* Register Bitfield Definitions ********************************************/ - -/* RNG Control Register */ - -#define RNG_CR_RNGEN (1 << 2) /* Bit 2: RNG enable */ -#define RNG_CR_IE (1 << 3) /* Bit 3: Interrupt enable */ - -/* RNG Status Register */ - -#define RNG_SR_DRDY (1 << 0) /* Bit 0: Data ready */ -#define RNG_SR_CECS (1 << 1) /* Bit 1: Clock error current status */ -#define RNG_SR_SECS (1 << 2) /* Bit 2: Seed error current status */ -#define RNG_SR_CEIS (1 << 5) /* Bit 5: Clock error interrupt status */ -#define RNG_SR_SEIS (1 << 6) /* Bit 6: Seed error interrupt status */ - -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_RNG_H */ diff --git a/arch/arm/src/stm32/hardware/stm32_rtc.h b/arch/arm/src/stm32/hardware/stm32_rtc.h deleted file mode 100644 index fc768d7aa027d..0000000000000 --- a/arch/arm/src/stm32/hardware/stm32_rtc.h +++ /dev/null @@ -1,83 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/hardware/stm32_rtc.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_RTC_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_RTC_H - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Register Offsets *********************************************************/ - -#define STM32_RTC_CRH_OFFSET 0x0000 /* RTC control register High (16-bit) */ -#define STM32_RTC_CRL_OFFSET 0x0004 /* RTC control register low (16-bit) */ -#define STM32_RTC_PRLH_OFFSET 0x0008 /* RTC prescaler load register high (16-bit) */ -#define STM32_RTC_PRLL_OFFSET 0x000c /* RTC prescaler load register low (16-bit) */ -#define STM32_RTC_DIVH_OFFSET 0x0010 /* RTC prescaler divider register high (16-bit) */ -#define STM32_RTC_DIVL_OFFSET 0x0014 /* RTC prescaler divider register low (16-bit) */ -#define STM32_RTC_CNTH_OFFSET 0x0018 /* RTC counter register high (16-bit) */ -#define STM32_RTC_CNTL_OFFSET 0x001c /* RTC counter register low (16-bit) */ -#define STM32_RTC_ALRH_OFFSET 0x0020 /* RTC alarm register high (16-bit) */ -#define STM32_RTC_ALRL_OFFSET 0x0024 /* RTC alarm register low (16-bit) */ - -/* Register Addresses *******************************************************/ - -#define STM32_RTC_CRH (STM32_RTC_BASE+STM32_RTC_CRH_OFFSET) -#define STM32_RTC_CRL (STM32_RTC_BASE+STM32_RTC_CRL_OFFSET) -#define STM32_RTC_PRLH (STM32_RTC_BASE+STM32_RTC_PRLH_OFFSET) -#define STM32_RTC_PRLL (STM32_RTC_BASE+STM32_RTC_PRLL_OFFSET) -#define STM32_RTC_DIVH (STM32_RTC_BASE+STM32_RTC_DIVH_OFFSET) -#define STM32_RTC_DIVL (STM32_RTC_BASE+STM32_RTC_DIVL_OFFSET) -#define STM32_RTC_CNTH (STM32_RTC_BASE+STM32_RTC_CNTH_OFFSET) -#define STM32_RTC_CNTL (STM32_RTC_BASE+STM32_RTC_CNTL_OFFSET) -#define STM32_RTC_ALRH (STM32_RTC_BASE+STM32_RTC_ALRH_OFFSET) -#define STM32_RTC_ALRL (STM32_RTC_BASE+STM32_RTC_ALRL_OFFSET) - -/* Register Bitfield Definitions ********************************************/ - -/* RTC control register High (16-bit) */ - -#define RTC_CRH_SECIE (1 << 0) /* Bit 0 : Second Interrupt Enable */ -#define RTC_CRH_ALRIE (1 << 1) /* Bit 1: Alarm Interrupt Enable */ -#define RTC_CRH_OWIE (1 << 2) /* Bit 2: OverfloW Interrupt Enable */ - -/* RTC control register low (16-bit) */ - -#define RTC_CRL_SECF (1 << 0) /* Bit 0: Second Flag */ -#define RTC_CRL_ALRF (1 << 1) /* Bit 1: Alarm Flag */ -#define RTC_CRL_OWF (1 << 2) /* Bit 2: Overflow Flag */ -#define RTC_CRL_RSF (1 << 3) /* Bit 3: Registers Synchronized Flag */ -#define RTC_CRL_CNF (1 << 4) /* Bit 4: Configuration Flag */ -#define RTC_CRL_RTOFF (1 << 5) /* Bit 5: RTC operation OFF */ - -/* RTC prescaler load register high (16-bit) */ - -#define RTC_PRLH_PRL_SHIFT (0) /* Bits 3-0: RTC Prescaler Reload Value High */ -#define RTC_PRLH_PRL_MASK (0x0f << RTC_PRLH_PRL_SHIFT) - -/* RTC prescaler divider register high (16-bit) */ - -#define RTC_DIVH_RTC_DIV_SHIFT (0) /* Bits 3-0: RTC Clock Divider High */ -#define RTC_DIVH_RTC_DIV_MASK (0x0f << RTC_DIVH_RTC_DIV_SHIFT) - -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_RTC_H */ diff --git a/arch/arm/src/stm32/hardware/stm32_rtcc.h b/arch/arm/src/stm32/hardware/stm32_rtcc.h deleted file mode 100644 index e939a1214ea38..0000000000000 --- a/arch/arm/src/stm32/hardware/stm32_rtcc.h +++ /dev/null @@ -1,408 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/hardware/stm32_rtcc.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_RTCC_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_RTCC_H - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Register Offsets *********************************************************/ - -#define STM32_RTC_TR_OFFSET 0x0000 /* RTC time register */ -#define STM32_RTC_DR_OFFSET 0x0004 /* RTC date register */ -#define STM32_RTC_CR_OFFSET 0x0008 /* RTC control register */ -#define STM32_RTC_ISR_OFFSET 0x000c /* RTC initialization and status register */ -#define STM32_RTC_PRER_OFFSET 0x0010 /* RTC prescaler register */ -#define STM32_RTC_WUTR_OFFSET 0x0014 /* RTC wakeup timer register */ -#ifndef CONFIG_STM32_STM32F30XX -# define STM32_RTC_CALIBR_OFFSET 0x0018 /* RTC calibration register */ -#endif -#define STM32_RTC_ALRMAR_OFFSET 0x001c /* RTC alarm A register */ -#define STM32_RTC_ALRMBR_OFFSET 0x0020 /* RTC alarm B register */ -#define STM32_RTC_WPR_OFFSET 0x0024 /* RTC write protection register */ -#define STM32_RTC_SSR_OFFSET 0x0028 /* RTC sub second register */ -#define STM32_RTC_SHIFTR_OFFSET 0x002c /* RTC shift control register */ -#define STM32_RTC_TSTR_OFFSET 0x0030 /* RTC time stamp time register */ -#define STM32_RTC_TSDR_OFFSET 0x0034 /* RTC time stamp date register */ -#define STM32_RTC_TSSSR_OFFSET 0x0038 /* RTC timestamp sub second register */ -#define STM32_RTC_CALR_OFFSET 0x003c /* RTC calibration register */ -#define STM32_RTC_TAFCR_OFFSET 0x0040 /* RTC tamper and alternate function configuration register */ -#define STM32_RTC_ALRMASSR_OFFSET 0x0044 /* RTC alarm A sub second register */ -#define STM32_RTC_ALRMBSSR_OFFSET 0x0048 /* RTC alarm B sub second register */ - -#define STM32_RTC_BKR_OFFSET(n) (0x0050+((n)<<2)) -#define STM32_RTC_BK0R_OFFSET 0x0050 /* RTC backup register 0 */ -#define STM32_RTC_BK1R_OFFSET 0x0054 /* RTC backup register 1 */ -#define STM32_RTC_BK2R_OFFSET 0x0058 /* RTC backup register 2 */ -#define STM32_RTC_BK3R_OFFSET 0x005c /* RTC backup register 3 */ -#define STM32_RTC_BK4R_OFFSET 0x0060 /* RTC backup register 4 */ -#define STM32_RTC_BK5R_OFFSET 0x0064 /* RTC backup register 5 */ -#define STM32_RTC_BK6R_OFFSET 0x0068 /* RTC backup register 6 */ -#define STM32_RTC_BK7R_OFFSET 0x006c /* RTC backup register 7 */ -#define STM32_RTC_BK8R_OFFSET 0x0070 /* RTC backup register 8 */ -#define STM32_RTC_BK9R_OFFSET 0x0074 /* RTC backup register 9 */ -#define STM32_RTC_BK10R_OFFSET 0x0078 /* RTC backup register 10 */ -#define STM32_RTC_BK11R_OFFSET 0x007c /* RTC backup register 11 */ -#define STM32_RTC_BK12R_OFFSET 0x0080 /* RTC backup register 12 */ -#define STM32_RTC_BK13R_OFFSET 0x0084 /* RTC backup register 13 */ -#define STM32_RTC_BK14R_OFFSET 0x0088 /* RTC backup register 14 */ -#define STM32_RTC_BK15R_OFFSET 0x008c /* RTC backup register 15 */ -#ifndef CONFIG_STM32_STM32F30XX -# define STM32_RTC_BK16R_OFFSET 0x0090 /* RTC backup register 16 */ -# define STM32_RTC_BK17R_OFFSET 0x0094 /* RTC backup register 17 */ -# define STM32_RTC_BK18R_OFFSET 0x0098 /* RTC backup register 18 */ -# define STM32_RTC_BK19R_OFFSET 0x009c /* RTC backup register 19 */ -#endif -#ifdef CONFIG_STM32_STM32L15XX -# define STM32_RTC_BK20R_OFFSET 0x00a0 /* RTC backup register 20 */ -# define STM32_RTC_BK21R_OFFSET 0x00a4 /* RTC backup register 21 */ -# define STM32_RTC_BK22R_OFFSET 0x00a8 /* RTC backup register 22 */ -# define STM32_RTC_BK23R_OFFSET 0x00ac /* RTC backup register 23 */ -# define STM32_RTC_BK24R_OFFSET 0x00b0 /* RTC backup register 24 */ -# define STM32_RTC_BK25R_OFFSET 0x00b4 /* RTC backup register 25 */ -# define STM32_RTC_BK26R_OFFSET 0x00b8 /* RTC backup register 26 */ -# define STM32_RTC_BK27R_OFFSET 0x00bc /* RTC backup register 27 */ -# define STM32_RTC_BK28R_OFFSET 0x00c0 /* RTC backup register 28 */ -# define STM32_RTC_BK29R_OFFSET 0x00c4 /* RTC backup register 29 */ -# define STM32_RTC_BK30R_OFFSET 0x00c8 /* RTC backup register 30 */ -# define STM32_RTC_BK31R_OFFSET 0x00cc /* RTC backup register 31 */ -#endif - -/* Register Addresses *******************************************************/ - -#define STM32_RTC_TR (STM32_RTC_BASE+STM32_RTC_TR_OFFSET) -#define STM32_RTC_DR (STM32_RTC_BASE+STM32_RTC_DR_OFFSET) -#define STM32_RTC_CR (STM32_RTC_BASE+STM32_RTC_CR_OFFSET) -#define STM32_RTC_ISR (STM32_RTC_BASE+STM32_RTC_ISR_OFFSET) -#define STM32_RTC_PRER (STM32_RTC_BASE+STM32_RTC_PRER_OFFSET) -#define STM32_RTC_WUTR (STM32_RTC_BASE+STM32_RTC_WUTR_OFFSET) -#ifndef CONFIG_STM32_STM32F30XX -# define STM32_RTC_CALIBR (STM32_RTC_BASE+STM32_RTC_CALIBR_OFFSET) -#endif -#define STM32_RTC_ALRMAR (STM32_RTC_BASE+STM32_RTC_ALRMAR_OFFSET) -#define STM32_RTC_ALRMBR (STM32_RTC_BASE+STM32_RTC_ALRMBR_OFFSET) -#define STM32_RTC_WPR (STM32_RTC_BASE+STM32_RTC_WPR_OFFSET) -#define STM32_RTC_SSR (STM32_RTC_BASE+STM32_RTC_SSR_OFFSET) -#define STM32_RTC_SHIFTR (STM32_RTC_BASE+STM32_RTC_SHIFTR_OFFSET) -#define STM32_RTC_TSTR (STM32_RTC_BASE+STM32_RTC_TSTR_OFFSET) -#define STM32_RTC_TSDR (STM32_RTC_BASE+STM32_RTC_TSDR_OFFSET) -#define STM32_RTC_TSSSR (STM32_RTC_BASE+STM32_RTC_TSSSR_OFFSET) -#define STM32_RTC_CALR (STM32_RTC_BASE+STM32_RTC_CALR_OFFSET) -#define STM32_RTC_TAFCR (STM32_RTC_BASE+STM32_RTC_TAFCR_OFFSET) -#define STM32_RTC_ALRMASSR (STM32_RTC_BASE+STM32_RTC_ALRMASSR_OFFSET) -#define STM32_RTC_ALRMBSSR (STM32_RTC_BASE+STM32_RTC_ALRMBSSR_OFFSET) - -#define STM32_RTC_BKR(n) (STM32_RTC_BASE+STM32_RTC_BKR_OFFSET(n)) -#define STM32_RTC_BK0R (STM32_RTC_BASE+STM32_RTC_BK0R_OFFSET) -#define STM32_RTC_BK1R (STM32_RTC_BASE+STM32_RTC_BK1R_OFFSET) -#define STM32_RTC_BK2R (STM32_RTC_BASE+STM32_RTC_BK2R_OFFSET) -#define STM32_RTC_BK3R (STM32_RTC_BASE+STM32_RTC_BK3R_OFFSET) -#define STM32_RTC_BK4R (STM32_RTC_BASE+STM32_RTC_BK4R_OFFSET) -#define STM32_RTC_BK5R (STM32_RTC_BASE+STM32_RTC_BK5R_OFFSET) -#define STM32_RTC_BK6R (STM32_RTC_BASE+STM32_RTC_BK6R_OFFSET) -#define STM32_RTC_BK7R (STM32_RTC_BASE+STM32_RTC_BK7R_OFFSET) -#define STM32_RTC_BK8R (STM32_RTC_BASE+STM32_RTC_BK8R_OFFSET) -#define STM32_RTC_BK9R (STM32_RTC_BASE+STM32_RTC_BK9R_OFFSET) -#define STM32_RTC_BK10R (STM32_RTC_BASE+STM32_RTC_BK10R_OFFSET) -#define STM32_RTC_BK11R (STM32_RTC_BASE+STM32_RTC_BK11R_OFFSET) -#define STM32_RTC_BK12R (STM32_RTC_BASE+STM32_RTC_BK12R_OFFSET) -#define STM32_RTC_BK13R (STM32_RTC_BASE+STM32_RTC_BK13R_OFFSET) -#define STM32_RTC_BK14R (STM32_RTC_BASE+STM32_RTC_BK14R_OFFSET) -#define STM32_RTC_BK15R (STM32_RTC_BASE+STM32_RTC_BK15R_OFFSET) -#ifndef CONFIG_STM32_STM32F30XX -# define STM32_RTC_BK16R (STM32_RTC_BASE+STM32_RTC_BK16R_OFFSET) -# define STM32_RTC_BK17R (STM32_RTC_BASE+STM32_RTC_BK17R_OFFSET) -# define STM32_RTC_BK18R (STM32_RTC_BASE+STM32_RTC_BK18R_OFFSET) -# define STM32_RTC_BK19R (STM32_RTC_BASE+STM32_RTC_BK19R_OFFSET) -#endif -#ifdef CONFIG_STM32_STM32L15XX -# define STM32_RTC_BK20R (STM32_RTC_BASE+STM32_RTC_BK20R_OFFSET) -# define STM32_RTC_BK21R (STM32_RTC_BASE+STM32_RTC_BK21R_OFFSET) -# define STM32_RTC_BK22R (STM32_RTC_BASE+STM32_RTC_BK22R_OFFSET) -# define STM32_RTC_BK23R (STM32_RTC_BASE+STM32_RTC_BK23R_OFFSET) -# define STM32_RTC_BK24R (STM32_RTC_BASE+STM32_RTC_BK24R_OFFSET) -# define STM32_RTC_BK25R (STM32_RTC_BASE+STM32_RTC_BK25R_OFFSET) -# define STM32_RTC_BK26R (STM32_RTC_BASE+STM32_RTC_BK26R_OFFSET) -# define STM32_RTC_BK27R (STM32_RTC_BASE+STM32_RTC_BK27R_OFFSET) -# define STM32_RTC_BK28R (STM32_RTC_BASE+STM32_RTC_BK28R_OFFSET) -# define STM32_RTC_BK29R (STM32_RTC_BASE+STM32_RTC_BK29R_OFFSET) -# define STM32_RTC_BK30R (STM32_RTC_BASE+STM32_RTC_BK30R_OFFSET) -# define STM32_RTC_BK31R (STM32_RTC_BASE+STM32_RTC_BK31R_OFFSET) -#endif - -#ifdef CONFIG_STM32_STM32F30XX -# define STM32_RTC_BKCOUNT 16 -#elif defined(CONFIG_STM32_STM32L15XX) -# define STM32_RTC_BKCOUNT 32 -#else -# define STM32_RTC_BKCOUNT 20 -#endif - -/* Register Bitfield Definitions ********************************************/ - -/* RTC time register */ - -#define RTC_TR_SU_SHIFT (0) /* Bits 0-3: Second units in BCD format */ -#define RTC_TR_SU_MASK (15 << RTC_TR_SU_SHIFT) -#define RTC_TR_ST_SHIFT (4) /* Bits 4-6: Second tens in BCD format */ -#define RTC_TR_ST_MASK (7 << RTC_TR_ST_SHIFT) -#define RTC_TR_MNU_SHIFT (8) /* Bit 8-11: Minute units in BCD format */ -#define RTC_TR_MNU_MASK (15 << RTC_TR_MNU_SHIFT) -#define RTC_TR_MNT_SHIFT (12) /* Bits 12-14: Minute tens in BCD format */ -#define RTC_TR_MNT_MASK (7 << RTC_TR_MNT_SHIFT) -#define RTC_TR_HU_SHIFT (16) /* Bit 16-19: Hour units in BCD format */ -#define RTC_TR_HU_MASK (15 << RTC_TR_HU_SHIFT) -#define RTC_TR_HT_SHIFT (20) /* Bits 20-21: Hour tens in BCD format */ -#define RTC_TR_HT_MASK (3 << RTC_TR_HT_SHIFT) -#define RTC_TR_PM (1 << 22) /* Bit 22: AM/PM notation */ -#define RTC_TR_RESERVED_BITS (0xff808080) - -/* RTC date register */ - -#define RTC_DR_DU_SHIFT (0) /* Bits 0-3: Date units in BCD format */ -#define RTC_DR_DU_MASK (15 << RTC_DR_DU_SHIFT) -#define RTC_DR_DT_SHIFT (4) /* Bits 4-5: Date tens in BCD format */ -#define RTC_DR_DT_MASK (3 << RTC_DR_DT_SHIFT) -#define RTC_DR_MU_SHIFT (8) /* Bits 8-11: Month units in BCD format */ -#define RTC_DR_MU_MASK (15 << RTC_DR_MU_SHIFT) -#define RTC_DR_MT (1 << 12) /* Bit 12: Month tens in BCD format */ -#define RTC_DR_WDU_SHIFT (13) /* Bits 13-15: Week day units */ -#define RTC_DR_WDU_MASK (7 << RTC_DR_WDU_SHIFT) -# define RTC_DR_WDU_MONDAY (1 << RTC_DR_WDU_SHIFT) -# define RTC_DR_WDU_TUESDAY (2 << RTC_DR_WDU_SHIFT) -# define RTC_DR_WDU_WEDNESDAY (3 << RTC_DR_WDU_SHIFT) -# define RTC_DR_WDU_THURSDAY (4 << RTC_DR_WDU_SHIFT) -# define RTC_DR_WDU_FRIDAY (5 << RTC_DR_WDU_SHIFT) -# define RTC_DR_WDU_SATURDAY (6 << RTC_DR_WDU_SHIFT) -# define RTC_DR_WDU_SUNDAY (7 << RTC_DR_WDU_SHIFT) -#define RTC_DR_YU_SHIFT (16) /* Bits 16-19: Year units in BCD format */ -#define RTC_DR_YU_MASK (15 << RTC_DR_YU_SHIFT) -#define RTC_DR_YT_SHIFT (20) /* Bits 20-23: Year tens in BCD format */ -#define RTC_DR_YT_MASK (15 << RTC_DR_YT_SHIFT) -#define RTC_DR_RESERVED_BITS (0xff0000c0) - -/* RTC control register */ - -#define RTC_CR_WUCKSEL_SHIFT (0) /* Bits 0-2: Wakeup clock selection */ -#define RTC_CR_WUCKSEL_MASK (7 << RTC_CR_WUCKSEL_SHIFT) -# define RTC_CR_WUCKSEL_RTCDIV16 (0 << RTC_CR_WUCKSEL_SHIFT) /* 000: RTC/16 clock is selected */ -# define RTC_CR_WUCKSEL_RTCDIV8 (1 << RTC_CR_WUCKSEL_SHIFT) /* 001: RTC/8 clock is selected */ -# define RTC_CR_WUCKSEL_RTCDIV4 (2 << RTC_CR_WUCKSEL_SHIFT) /* 010: RTC/4 clock is selected */ -# define RTC_CR_WUCKSEL_RTCDIV2 (3 << RTC_CR_WUCKSEL_SHIFT) /* 011: RTC/2 clock is selected */ -# define RTC_CR_WUCKSEL_CKSPRE (4 << RTC_CR_WUCKSEL_SHIFT) /* 10x: ck_spre clock is selected */ -# define RTC_CR_WUCKSEL_CKSPREADD (6 << RTC_CR_WUCKSEL_SHIFT) /* 11x: ck_spr clock and 216 added WUT counter */ - -#define RTC_CR_TSEDGE (1 << 3) /* Bit 3: Timestamp event active edge */ -#define RTC_CR_REFCKON (1 << 4) /* Bit 4: Reference clock detection enable (50 or 60 Hz) */ -#define RTC_CR_BYPSHAD (1 << 5) /* Bit 5: Bypass the shadow registers */ -#define RTC_CR_FMT (1 << 6) /* Bit 6: Hour format */ -#define RTC_CR_DCE (1 << 7) /* Bit 7: Coarse digital calibration enable */ -#define RTC_CR_ALRAE (1 << 8) /* Bit 8: Alarm A enable */ -#define RTC_CR_ALRBE (1 << 9) /* Bit 9: Alarm B enable */ -#define RTC_CR_WUTE (1 << 10) /* Bit 10: Wakeup timer enable */ -#define RTC_CR_TSE (1 << 11) /* Bit 11: Time stamp enable */ -#define RTC_CR_ALRAIE (1 << 12) /* Bit 12: Alarm A interrupt enable */ -#define RTC_CR_ALRBIE (1 << 13) /* Bit 13: Alarm B interrupt enable */ -#define RTC_CR_WUTIE (1 << 14) /* Bit 14: Wakeup timer interrupt enable */ -#define RTC_CR_TSIE (1 << 15) /* Bit 15: Timestamp interrupt enable */ -#define RTC_CR_ADD1H (1 << 16) /* Bit 16: Add 1 hour (summer time change) */ -#define RTC_CR_SUB1H (1 << 17) /* Bit 17: Subtract 1 hour (winter time change) */ -#define RTC_CR_BKP (1 << 18) /* Bit 18: Backup */ -#define RTC_CR_COSEL (1 << 19) /* Bit 19: Calibration output selection */ -#define RTC_CR_POL (1 << 20) /* Bit 20: Output polarity */ -#define RTC_CR_OSEL_SHIFT (21) /* Bits 21-22: Output selection */ -#define RTC_CR_OSEL_MASK (3 << RTC_CR_OSEL_SHIFT) -# define RTC_CR_OSEL_DISABLED (0 << RTC_CR_OSEL_SHIFT) /* 00: Output disabled */ -# define RTC_CR_OSEL_ALRMA (1 << RTC_CR_OSEL_SHIFT) /* 01: Alarm A output enabled */ -# define RTC_CR_OSEL_ALRMB (2 << RTC_CR_OSEL_SHIFT) /* 10: Alarm B output enabled */ -# define RTC_CR_OSEL_WUT (3 << RTC_CR_OSEL_SHIFT) /* 11: Wakeup output enabled */ - -#define RTC_CR_COE (1 << 23) /* Bit 23: Calibration output enable */ - -/* RTC initialization and status register */ - -#define RTC_ISR_ALRAWF (1 << 0) /* Bit 0: Alarm A write flag */ -#define RTC_ISR_ALRBWF (1 << 1) /* Bit 1: Alarm B write flag */ -#define RTC_ISR_WUTWF (1 << 2) /* Bit 2: Wakeup timer write flag */ -#define RTC_ISR_SHPF (1 << 3) /* Bit 3: Shift operation pending */ -#define RTC_ISR_INITS (1 << 4) /* Bit 4: Initialization status flag */ -#define RTC_ISR_RSF (1 << 5) /* Bit 5: Registers synchronization flag */ -#define RTC_ISR_INITF (1 << 6) /* Bit 6: Initialization flag */ -#define RTC_ISR_INIT (1 << 7) /* Bit 7: Initialization mode */ -#define RTC_ISR_ALRAF (1 << 8) /* Bit 8: Alarm A flag */ -#define RTC_ISR_ALRBF (1 << 9) /* Bit 9: Alarm B flag */ -#define RTC_ISR_WUTF (1 << 10) /* Bit 10: Wakeup timer flag */ -#define RTC_ISR_TSF (1 << 11) /* Bit 11: Timestamp flag */ -#define RTC_ISR_TSOVF (1 << 12) /* Bit 12: Timestamp overflow flag */ -#define RTC_ISR_TAMP1F (1 << 13) /* Bit 13: Tamper detection flag */ -#define RTC_ISR_TAMP2F (1 << 14) /* Bit 14: TAMPER2 detection flag */ -#ifdef CONFIG_STM32_STM32L15XX -# define RTC_ISR_TAMP3F (1 << 15) /* Bit 15: TAMPER3 detection flag */ -#endif -#define RTC_ISR_RECALPF (1 << 16) /* Bit 16: Recalibration pending flag */ -#define RTC_ISR_ALLFLAGS (0x00017fff) - -/* RTC prescaler register */ - -#define RTC_PRER_PREDIV_S_SHIFT (0) /* Bits 0-14: Synchronous prescaler factor */ -#define RTC_PRER_PREDIV_S_MASK (0x7fff << RTC_PRER_PREDIV_S_SHIFT) -#define RTC_PRER_PREDIV_A_SHIFT (16) /* Bits 16-22: Asynchronous prescaler factor */ -#define RTC_PRER_PREDIV_A_MASK (0x7f << RTC_PRER_PREDIV_A_SHIFT) - -/* RTC wakeup timer register */ - -#define RTC_WUTR_MASK (0xffff) /* Bits 15:0 Wakeup auto-reload value bits */ - -/* RTC calibration register */ - -#ifndef CONFIG_STM32_STM32F30XX -# define RTC_CALIBR_DCS (1 << 7) /* Bit 7 Digital calibration sign */ -# define RTC_CALIBR_DC_SHIFT (0) /* Bits 4:0 0-4: Digital calibration */ -# define RTC_CALIBR_DC_MASK (31 << RTC_CALIBR_DC_SHIFT) -# define RTC_CALIBR_DC(n) (((n) >> 2) << RTC_CALIBR_DC_SHIFT) /* n= 0, 4, 8, ... 126 */ -#endif - -/* RTC alarm A/B registers */ - -#define RTC_ALRMR_SU_SHIFT (0) /* Bits 0-3: Second units in BCD format. */ -#define RTC_ALRMR_SU_MASK (15 << RTC_ALRMR_SU_SHIFT) -#define RTC_ALRMR_ST_SHIFT (4) /* Bits 4-6: Second tens in BCD format. */ -#define RTC_ALRMR_ST_MASK (7 << RTC_ALRMR_ST_SHIFT) -#define RTC_ALRMR_MSK1 (1 << 7) /* Bit 7 : Alarm A seconds mask */ -#define RTC_ALRMR_MNU_SHIFT (8) /* Bits 8-11: Minute units in BCD format. */ -#define RTC_ALRMR_MNU_MASK (15 << RTC_ALRMR_MNU_SHIFT) -#define RTC_ALRMR_MNT_SHIFT (12) /* Bits 12-14: Minute tens in BCD format. */ -#define RTC_ALRMR_MNT_MASK (7 << RTC_ALRMR_MNT_SHIFT) -#define RTC_ALRMR_MSK2 (1 << 15) /* Bit 15 : Alarm A minutes mask */ -#define RTC_ALRMR_HU_SHIFT (16) /* Bits 16-19: Hour units in BCD format. */ -#define RTC_ALRMR_HU_MASK (15 << RTC_ALRMR_HU_SHIFT) -#define RTC_ALRMR_HT_SHIFT (20) /* Bits 20-21: Hour tens in BCD format. */ -#define RTC_ALRMR_HT_MASK (3 << RTC_ALRMR_HT_SHIFT) -#define RTC_ALRMR_PM (1 << 22) /* Bit 22 : AM/PM notation */ -#define RTC_ALRMR_MSK3 (1 << 23) /* Bit 23 : Alarm A hours mask */ -#define RTC_ALRMR_DU_SHIFT (24) /* Bits 24-27: Date units or day in BCD format. */ -#define RTC_ALRMR_DU_MASK (15 << RTC_ALRMR_DU_SHIFT) -#define RTC_ALRMR_DT_SHIFT (28) /* Bits 28-29: Date tens in BCD format. */ -#define RTC_ALRMR_DT_MASK (3 << RTC_ALRMR_DT_SHIFT) -#define RTC_ALRMR_WDSEL (1 << 30) /* Bit 30: Week day selection */ -#define RTC_ALRMR_MSK4 (1 << 31) /* Bit 31: Alarm A date mask */ - -/* RTC write protection register */ - -#define RTC_WPR_MASK (0xff) /* Bits 0-7: Write protection key */ - -/* RTC sub second register */ - -#define RTC_SSR_MASK (0xffff) /* Bits 0-15: Sub second value */ - -/* RTC shift control register */ - -#define RTC_SHIFTR_SUBFS_SHIFT (0) /* Bits 0-14: Subtract a fraction of a second */ -#define RTC_SHIFTR_SUBFS_MASK (0x7fff << RTC_SHIFTR_SUBFS_SHIFT) -#define RTC_SHIFTR_ADD1S (1 << 31) /* Bit 31: Add one second */ - -/* RTC time stamp time register */ - -#define RTC_TSTR_SU_SHIFT (0) /* Bits 0-3: Second units in BCD format. */ -#define RTC_TSTR_SU_MASK (15 << RTC_TSTR_SU_SHIFT) -#define RTC_TSTR_ST_SHIFT (4) /* Bits 4-6: Second tens in BCD format. */ -#define RTC_TSTR_ST_MASK (7 << RTC_TSTR_ST_SHIFT) -#define RTC_TSTR_MNU_SHIFT (8) /* Bits 8-11: Minute units in BCD format. */ -#define RTC_TSTR_MNU_MASK (15 << RTC_TSTR_MNU_SHIFT) -#define RTC_TSTR_MNT_SHIFT (12) /* Bits 12-14: Minute tens in BCD format. */ -#define RTC_TSTR_MNT_MASK (7 << RTC_TSTR_MNT_SHIFT) -#define RTC_TSTR_HU_SHIFT (16) /* Bits 16-19: Hour units in BCD format. */ -#define RTC_TSTR_HU_MASK (15 << RTC_TSTR_HU_SHIFT) -#define RTC_TSTR_HT_SHIFT (20) /* Bits 20-21: Hour tens in BCD format. */ -#define RTC_TSTR_HT_MASK (3 << RTC_TSTR_HT_SHIFT) -#define RTC_TSTR_PM (1 << 22) /* Bit 22: AM/PM notation */ - -/* RTC time stamp date register */ - -#define RTC_TSDR_DU_SHIFT (0) /* Bit 0-3: Date units in BCD format */ -#define RTC_TSDR_DU_MASK (15 << RTC_TSDR_DU_SHIFT) -#define RTC_TSDR_DT_SHIFT (4) /* Bits 4-5: Date tens in BCD format */ -#define RTC_TSDR_DT_MASK (3 << RTC_TSDR_DT_SHIFT) -#define RTC_TSDR_MU_SHIFT (8) /* Bits 8-11: Month units in BCD format */ -#define RTC_TSDR_MU_MASK (15 << RTC_TSDR_MU_SHIFT) -#define RTC_TSDR_MT (1 << 12) /* Bit 12: Month tens in BCD format */ -#define RTC_TSDR_WDU_SHIFT (13) /* Bits 13-15: Week day units */ -#define RTC_TSDR_WDU_MASK (7 << RTC_TSDR_WDU_SHIFT) - -/* RTC timestamp sub second register */ - -#define RTC_TSSSR_MASK (0xffff) /* Bits 0-15: Sub second value */ - -/* RTC calibration register */ - -#define RTC_CALR_CALM_SHIFT (0) /* Bits 0-8: Calibration minus */ -#define RTC_CALR_CALM_MASK (0x1ff << RTC_CALR_CALM_SHIFT) -#define RTC_CALR_CALW16 (1 << 13) /* Bit 13: Use a 16-second calibration cycle period */ -#define RTC_CALR_CALW8 (1 << 14) /* Bit 14: Use an 8-second calibration cycle period */ -#define RTC_CALR_CALP (1 << 15) /* Bit 15: Increase frequency of RTC by 488.5 ppm */ - -/* RTC tamper and alternate function configuration register */ - -#define RTC_TAFCR_TAMP1E (1 << 0) /* Bit 0: RTC_TAMP1 input detection enable */ -#define RTC_TAFCR_TAMP1TRG (1 << 1) /* Bit 1: Active level for RTC_TAMP1 input */ -#define RTC_TAFCR_TAMPIE (1 << 2) /* Bit 2: Tamper interrupt enable */ -#define RTC_TAFCR_TAMP3E (1 << 5) /* Bit 5: RTC_TAMP3 detection enable */ -#define RTC_TAFCR_TAMP3TRG (1 << 6) /* Bit 6: Active level for RTC_TAMP3 input */ -#define RTC_TAFCR_TAMPTS (1 << 7) /* Bit 7: Activate timestamp on tamper detection event */ -#define RTC_TAFCR_TAMPFREQ_SHIFT (8) /* Bits 8-10: Tamper sampling frequency */ -#define RTC_TAFCR_TAMPFREQ_MASK (7 << RTC_TAFCR_TAMPFREQ_SHIFT) -# define RTC_TAFCR_TAMPFREQ_DIV32768 (0 << RTC_TAFCR_TAMPFREQ_SHIFT) /* RTCCLK / 32768 (1 Hz) */ -# define RTC_TAFCR_TAMPFREQ_DIV16384 (1 << RTC_TAFCR_TAMPFREQ_SHIFT) /* RTCCLK / 16384 (2 Hz) */ -# define RTC_TAFCR_TAMPFREQ_DIV8192 (2 << RTC_TAFCR_TAMPFREQ_SHIFT) /* RTCCLK / 8192 (4 Hz) */ -# define RTC_TAFCR_TAMPFREQ_DIV4096 (3 << RTC_TAFCR_TAMPFREQ_SHIFT) /* RTCCLK / 4096 (8 Hz) */ -# define RTC_TAFCR_TAMPFREQ_DIV2048 (4 << RTC_TAFCR_TAMPFREQ_SHIFT) /* RTCCLK / 2048 (16 Hz) */ -# define RTC_TAFCR_TAMPFREQ_DIV1024 (5 << RTC_TAFCR_TAMPFREQ_SHIFT) /* RTCCLK / 1024 (32 Hz) */ -# define RTC_TAFCR_TAMPFREQ_DIV512 (6 << RTC_TAFCR_TAMPFREQ_SHIFT) /* RTCCLK / 512 (64 Hz) */ -# define RTC_TAFCR_TAMPFREQ_DIV256 (7 << RTC_TAFCR_TAMPFREQ_SHIFT) /* RTCCLK / 256 (128 Hz) */ - -#define RTC_TAFCR_TAMPFLT_SHIFT (11) /* Bits 11-12: RTC_TAMPx filter count */ -#define RTC_TAFCR_TAMPFLT_MASK (3 << RTC_TAFCR_TAMPFLT_SHIFT) -#define RTC_TAFCR_TAMPPRCH_SHIFT (13) /* Bits 13-14: RTC_TAMPx precharge duration */ -#define RTC_TAFCR_TAMPPRCH_MASK (3 << RTC_TAFCR_TAMPPRCH_SHIFT) -# define RTC_TAFCR_TAMPPRCH_1CYCLE (0 << RTC_TAFCR_TAMPPRCH_SHIFT) /* 1 RTCCLK cycle */ -# define RTC_TAFCR_TAMPPRCH_2CYCLES (1 << RTC_TAFCR_TAMPPRCH_SHIFT) /* 2 RTCCLK cycles */ -# define RTC_TAFCR_TAMPPRCH_4CYCLES (2 << RTC_TAFCR_TAMPPRCH_SHIFT) /* 4 RTCCLK cycles */ -# define RTC_TAFCR_TAMPPRCH_5CYCLES (3 << RTC_TAFCR_TAMPPRCH_SHIFT) /* 8 RTCCLK cycles */ - -#define RTC_TAFCR_TAMPPUDIS (1 << 15) /* Bit 15: RTC_TAMPx pull-up disable */ -#define RTC_TAFCR_PC13VALUE (1 << 18) /* Bit 18: RTC_ALARM output type/PC13 value */ -#define RTC_TAFCR_PC13MODE (1 << 19) /* Bit 19: PC13 mode */ -#define RTC_TAFCR_PC14VALUE (1 << 20) /* Bit 20: PC14 value */ -#define RTC_TAFCR_PC14MODE (1 << 21) /* Bit 21: PC14 mode */ -#define RTC_TAFCR_PC15VALUE (1 << 22) /* Bit 22: PC15 value */ -#define RTC_TAFCR_PC15MODE (1 << 23) /* Bit 23: PC15 mode */ - -/* RTC alarm A/B sub second register */ - -#define RTC_ALRMSSR_SS_SHIFT (0) /* Bits 0-14: Sub second value */ -#define RTC_ALRMSSR_SS_MASK (0x7fff << RTC_ALRMSSR_SS_SHIFT) -#define RTC_ALRMSSR_MASKSS_SHIFT (24) /* Bits 24-27: Mask the most-significant bits starting at this bit */ -#define RTC_ALRMSSR_MASKSS_MASK (0xf << RTC_ALRMSSR_MASKSS_SHIFT) - -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_RTCC_H */ diff --git a/arch/arm/src/stm32/hardware/stm32_sdio.h b/arch/arm/src/stm32/hardware/stm32_sdio.h deleted file mode 100644 index 4c732893275c8..0000000000000 --- a/arch/arm/src/stm32/hardware/stm32_sdio.h +++ /dev/null @@ -1,279 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/hardware/stm32_sdio.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_SDIO_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_SDIO_H - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Register Offsets *********************************************************/ - -#define STM32_SDIO_POWER_OFFSET 0x0000 /* SDIO power control register */ -#define STM32_SDIO_CLKCR_OFFSET 0x0004 /* SDI clock control register */ -#define STM32_SDIO_ARG_OFFSET 0x0008 /* SDIO argument register */ -#define STM32_SDIO_CMD_OFFSET 0x000c /* SDIO command register */ -#define STM32_SDIO_RESPCMD_OFFSET 0x0010 /* SDIO command response register */ -#define STM32_SDIO_RESP_OFFSET(n) (0x0010+4*(n)) -#define STM32_SDIO_RESP1_OFFSET 0x0014 /* SDIO response 1 register */ -#define STM32_SDIO_RESP2_OFFSET 0x0018 /* SDIO response 2 register */ -#define STM32_SDIO_RESP3_OFFSET 0x001c /* SDIO response 3 register */ -#define STM32_SDIO_RESP4_OFFSET 0x0020 /* SDIO response 4 register */ -#define STM32_SDIO_DTIMER_OFFSET 0x0024 /* SDIO data timer register */ -#define STM32_SDIO_DLEN_OFFSET 0x0028 /* SDIO data length register */ -#define STM32_SDIO_DCTRL_OFFSET 0x002c /* SDIO data control register */ -#define STM32_SDIO_DCOUNT_OFFSET 0x0030 /* SDIO data counter register */ -#define STM32_SDIO_STA_OFFSET 0x0034 /* SDIO status register */ -#define STM32_SDIO_ICR_OFFSET 0x0038 /* SDIO interrupt clear register */ -#define STM32_SDIO_MASK_OFFSET 0x003c /* SDIO mask register */ -#define STM32_SDIO_FIFOCNT_OFFSET 0x0048 /* SDIO FIFO counter register */ -#define STM32_SDIO_FIFO_OFFSET 0x0080 /* SDIO data FIFO register */ - -/* Register Addresses *******************************************************/ - -#define STM32_SDIO_POWER (STM32_SDIO_BASE+STM32_SDIO_POWER_OFFSET) -#define STM32_SDIO_CLKCR (STM32_SDIO_BASE+STM32_SDIO_CLKCR_OFFSET) -#define STM32_SDIO_ARG (STM32_SDIO_BASE+STM32_SDIO_ARG_OFFSET) -#define STM32_SDIO_CMD (STM32_SDIO_BASE+STM32_SDIO_CMD_OFFSET) -#define STM32_SDIO_RESPCMD (STM32_SDIO_BASE+STM32_SDIO_RESPCMD_OFFSET) -#define STM32_SDIO_RESP(n) (STM32_SDIO_BASE+STM32_SDIO_RESP_OFFSET(n)) -#define STM32_SDIO_RESP1 (STM32_SDIO_BASE+STM32_SDIO_RESP1_OFFSET) -#define STM32_SDIO_RESP2 (STM32_SDIO_BASE+STM32_SDIO_RESP2_OFFSET) -#define STM32_SDIO_RESP3 (STM32_SDIO_BASE+STM32_SDIO_RESP3_OFFSET) -#define STM32_SDIO_RESP4 (STM32_SDIO_BASE+STM32_SDIO_RESP4_OFFSET) -#define STM32_SDIO_DTIMER (STM32_SDIO_BASE+STM32_SDIO_DTIMER_OFFSET) -#define STM32_SDIO_DLEN (STM32_SDIO_BASE+STM32_SDIO_DLEN_OFFSET) -#define STM32_SDIO_DCTRL (STM32_SDIO_BASE+STM32_SDIO_DCTRL_OFFSET) -#define STM32_SDIO_DCOUNT (STM32_SDIO_BASE+STM32_SDIO_DCOUNT_OFFSET) -#define STM32_SDIO_STA (STM32_SDIO_BASE+STM32_SDIO_STA_OFFSET) -#define STM32_SDIO_ICR (STM32_SDIO_BASE+STM32_SDIO_ICR_OFFSET) -#define STM32_SDIO_MASK (STM32_SDIO_BASE+STM32_SDIO_MASK_OFFSET) -#define STM32_SDIO_FIFOCNT (STM32_SDIO_BASE+STM32_SDIO_FIFOCNT_OFFSET) -#define STM32_SDIO_FIFO (STM32_SDIO_BASE+STM32_SDIO_FIFO_OFFSET) - -/* Bit-band (BB) base addresses *********************************************/ - -#define STM32_SDIO_OFFSET (STM32_SDIO_BASE-STM32_PERIPH_BASE) - -#define STM32_SDIO_POWER_BB (STM32_PERIPHBB_BASE+((STM32_SDIO_OFFSET+STM32_SDIO_POWER_OFFSET)<<5)) -#define STM32_SDIO_CLKCR_BB (STM32_PERIPHBB_BASE+((STM32_SDIO_OFFSET+STM32_SDIO_CLKCR_OFFSET)<<5)) -#define STM32_SDIO_ARG_BB (STM32_PERIPHBB_BASE+((STM32_SDIO_OFFSET+STM32_SDIO_ARG_OFFSET)<<5)) -#define STM32_SDIO_CMD_BB (STM32_PERIPHBB_BASE+((STM32_SDIO_OFFSET+STM32_SDIO_CMD_OFFSET)<<5)) -#define STM32_SDIO_RESPCMD_BB (STM32_PERIPHBB_BASE+((STM32_SDIO_OFFSET+STM32_SDIO_RESPCMD_OFFSET)<<5)) -#define STM32_SDIO_RESP_BB(n) (STM32_PERIPHBB_BASE+((STM32_SDIO_OFFSET+STM32_SDIO_RESP_OFFSET(n))<<5)) -#define STM32_SDIO_RESP1_BB (STM32_PERIPHBB_BASE+((STM32_SDIO_OFFSET+STM32_SDIO_RESP1_OFFSET)<<5)) -#define STM32_SDIO_RESP2_BB (STM32_PERIPHBB_BASE+((STM32_SDIO_OFFSET+STM32_SDIO_RESP2_OFFSET)<<5)) -#define STM32_SDIO_RESP3_BB (STM32_PERIPHBB_BASE+((STM32_SDIO_OFFSET+STM32_SDIO_RESP3_OFFSET)<<5)) -#define STM32_SDIO_RESP4_BB (STM32_PERIPHBB_BASE+((STM32_SDIO_OFFSET+STM32_SDIO_RESP4_OFFSET)<<5)) -#define STM32_SDIO_DTIMER_BB (STM32_PERIPHBB_BASE+((STM32_SDIO_OFFSET+STM32_SDIO_DTIMER_OFFSET)<<5)) -#define STM32_SDIO_DLEN_BB (STM32_PERIPHBB_BASE+((STM32_SDIO_OFFSET+STM32_SDIO_DLEN_OFFSET)<<5)) -#define STM32_SDIO_DCTRL_BB (STM32_PERIPHBB_BASE+((STM32_SDIO_OFFSET+STM32_SDIO_DCTRL_OFFSET)<<5)) -#define STM32_SDIO_DCOUNT_BB (STM32_PERIPHBB_BASE+((STM32_SDIO_OFFSET+STM32_SDIO_DCOUNT_OFFSET)<<5)) -#define STM32_SDIO_STA_BB (STM32_PERIPHBB_BASE+((STM32_SDIO_OFFSET+STM32_SDIO_STA_OFFSET)<<5)) -#define STM32_SDIO_ICR_BB (STM32_PERIPHBB_BASE+((STM32_SDIO_OFFSET+STM32_SDIO_ICR_OFFSET)<<5)) -#define STM32_SDIO_MASK_BB (STM32_PERIPHBB_BASE+((STM32_SDIO_OFFSET+STM32_SDIO_MASK_OFFSET)<<5)) -#define STM32_SDIO_FIFOCNT_BB (STM32_PERIPHBB_BASE+((STM32_SDIO_OFFSET+STM32_SDIO_FIFOCNT_OFFSET)<<5)) -#define STM32_SDIO_FIFO_BB (STM32_PERIPHBB_BASE+((STM32_SDIO_OFFSET+STM32_SDIO_FIFO_OFFSET)<<5)) - -/* Register Bitfield Definitions ********************************************/ - -#define SDIO_POWER_PWRCTRL_SHIFT (0) /* Bits 0-1: Power supply control bits */ -#define SDIO_POWER_PWRCTRL_MASK (3 << SDIO_POWER_PWRCTRL_SHIFT) -# define SDIO_POWER_PWRCTRL_OFF (0 << SDIO_POWER_PWRCTRL_SHIFT) /* 00: Power-off: card clock stopped */ -# define SDIO_POWER_PWRCTRL_PWRUP (2 << SDIO_POWER_PWRCTRL_SHIFT) /* 10: Reserved power-up */ -# define SDIO_POWER_PWRCTRL_ON (3 << SDIO_POWER_PWRCTRL_SHIFT) /* 11: Power-on: card is clocked */ - -#define SDIO_POWER_RESET (0) /* Reset value */ - -#define SDIO_CLKCR_CLKDIV_SHIFT (0) /* Bits 7-0: Clock divide factor */ -#define SDIO_CLKCR_CLKDIV_MASK (0xff << SDIO_CLKCR_CLKDIV_SHIFT) -#define SDIO_CLKCR_CLKEN (1 << 8) /* Bit 8: Clock enable bit */ -#define SDIO_CLKCR_PWRSAV (1 << 9) /* Bit 9: Power saving configuration bit */ -#define SDIO_CLKCR_BYPASS (1 << 10) /* Bit 10: Clock divider bypass enable bit */ -#define SDIO_CLKCR_WIDBUS_SHIFT (11) /* Bits 12-11: Wide bus mode enable bits */ -#define SDIO_CLKCR_WIDBUS_MASK (3 << SDIO_CLKCR_WIDBUS_SHIFT) -# define SDIO_CLKCR_WIDBUS_D1 (0 << SDIO_CLKCR_WIDBUS_SHIFT) /* 00: Default (SDIO_D0) */ -# define SDIO_CLKCR_WIDBUS_D4 (1 << SDIO_CLKCR_WIDBUS_SHIFT) /* 01: 4-wide (SDIO_D[3:0]) */ -# define SDIO_CLKCR_WIDBUS_D8 (2 << SDIO_CLKCR_WIDBUS_SHIFT) /* 10: 8-wide (SDIO_D[7:0]) */ - -#define SDIO_CLKCR_NEGEDGE (1 << 13) /* Bit 13: SDIO_CK dephasing selection bit */ -#define SDIO_CLKCR_HWFC_EN (1 << 14) /* Bit 14: HW Flow Control enable */ - -#define SDIO_CLKCR_RESET (0) /* Reset value */ -#define SDIO_ARG_RESET (0) /* Reset value */ - -#define SDIO_CLKCR_CLKEN_BB (STM32_SDIO_CLKCR_BB + (8 * 4)) -#define SDIO_CLKCR_PWRSAV_BB (STM32_SDIO_CLKCR_BB + (9 * 4)) -#define SDIO_CLKCR_BYPASS_BB (STM32_SDIO_CLKCR_BB + (10 * 4)) -#define SDIO_CLKCR_NEGEDGE_BB (STM32_SDIO_CLKCR_BB + (13 * 4)) -#define SDIO_CLKCR_HWFC_EN_BB (STM32_SDIO_CLKCR_BB + (14 * 4)) - -#define SDIO_CMD_CMDINDEX_SHIFT (0) -#define SDIO_CMD_CMDINDEX_MASK (0x3f << SDIO_CMD_CMDINDEX_SHIFT) -#define SDIO_CMD_WAITRESP_SHIFT (6) /* Bits 7-6: Wait for response bits */ -#define SDIO_CMD_WAITRESP_MASK (3 << SDIO_CMD_WAITRESP_SHIFT) -# define SDIO_CMD_NORESPONSE (0 << SDIO_CMD_WAITRESP_SHIFT) /* 00/10: No response */ -# define SDIO_CMD_SHORTRESPONSE (1 << SDIO_CMD_WAITRESP_SHIFT) /* 01: Short response */ -# define SDIO_CMD_LONGRESPONSE (3 << SDIO_CMD_WAITRESP_SHIFT) /* 11: Long response */ - -#define SDIO_CMD_WAITINT (1 << 8) /* Bit 8: CPSM waits for interrupt request */ -#define SDIO_CMD_WAITPEND (1 << 9) /* Bit 9: CPSM Waits for ends of data transfer */ -#define SDIO_CMD_CPSMEN (1 << 10) /* Bit 10: Command path state machine enable */ -#define SDIO_CMD_SUSPEND (1 << 11) /* Bit 11: SD I/O suspend command */ -#define SDIO_CMD_ENDCMD (1 << 12) /* Bit 12: Enable CMD completion */ -#define SDIO_CMD_NIEN (1 << 13) /* Bit 13: not Interrupt Enable */ -#define SDIO_CMD_ATACMD (1 << 14) /* Bit 14: CE-ATA command */ - -#define SDIO_CMD_RESET (0) /* Reset value */ - -#define SDIO_CMD_WAITINT_BB (STM32_SDIO_CMD_BB + (8 * 4)) -#define SDIO_CMD_WAITPEND_BB (STM32_SDIO_CMD_BB + (9 * 4)) -#define SDIO_CMD_CPSMEN_BB (STM32_SDIO_CMD_BB + (10 * 4)) -#define SDIO_CMD_SUSPEND_BB (STM32_SDIO_CMD_BB + (11 * 4)) -#define SDIO_CMD_ENCMD_BB (STM32_SDIO_CMD_BB + (12 * 4)) -#define SDIO_CMD_NIEN_BB (STM32_SDIO_CMD_BB + (13 * 4)) -#define SDIO_CMD_ATACMD_BB (STM32_SDIO_CMD_BB + (14 * 4)) - -#define SDIO_RESPCMD_SHIFT (0) -#define SDIO_RESPCMD_MASK (0x3f << SDIO_RESPCMD_SHIFT) - -#define SDIO_DTIMER_RESET (0) /* Reset value */ - -#define SDIO_DLEN_SHIFT (0) -#define SDIO_DLEN_MASK (0x01ffffff << SDIO_DLEN_SHIFT) - -#define SDIO_DLEN_RESET (0) /* Reset value */ - -#define SDIO_DCTRL_DTEN (1 << 0) /* Bit 0: Data transfer enabled bit */ -#define SDIO_DCTRL_DTDIR (1 << 1) /* Bit 1: Data transfer direction */ -#define SDIO_DCTRL_DTMODE (1 << 2) /* Bit 2: Data transfer mode */ -#define SDIO_DCTRL_DMAEN (1 << 3) /* Bit 3: DMA enable bit */ -#define SDIO_DCTRL_DBLOCKSIZE_SHIFT (4) /* Bits 7-4: Data block size */ -#define SDIO_DCTRL_DBLOCKSIZE_MASK (15 << SDIO_DCTRL_DBLOCKSIZE_SHIFT) -# define SDIO_DCTRL_1BYTE (0 << SDIO_DCTRL_DBLOCKSIZE_SHIFT) -# define SDIO_DCTRL_2BYTES (1 << SDIO_DCTRL_DBLOCKSIZE_SHIFT) -# define SDIO_DCTRL_4BYTES (2 << SDIO_DCTRL_DBLOCKSIZE_SHIFT) -# define SDIO_DCTRL_8BYTES (3 << SDIO_DCTRL_DBLOCKSIZE_SHIFT) -# define SDIO_DCTRL_16BYTES (4 << SDIO_DCTRL_DBLOCKSIZE_SHIFT) -# define SDIO_DCTRL_32BYTES (5 << SDIO_DCTRL_DBLOCKSIZE_SHIFT) -# define SDIO_DCTRL_64BYTES (6 << SDIO_DCTRL_DBLOCKSIZE_SHIFT) -# define SDIO_DCTRL_128BYTES (7 << SDIO_DCTRL_DBLOCKSIZE_SHIFT) -# define SDIO_DCTRL_256BYTES (8 << SDIO_DCTRL_DBLOCKSIZE_SHIFT) -# define SDIO_DCTRL_512BYTES (9 << SDIO_DCTRL_DBLOCKSIZE_SHIFT) -# define SDIO_DCTRL_1KBYTE (10 << SDIO_DCTRL_DBLOCKSIZE_SHIFT) -# define SDIO_DCTRL_2KBYTES (11 << SDIO_DCTRL_DBLOCKSIZE_SHIFT) -# define SDIO_DCTRL_4KBYTES (12 << SDIO_DCTRL_DBLOCKSIZE_SHIFT) -# define SDIO_DCTRL_8KBYTES (13 << SDIO_DCTRL_DBLOCKSIZE_SHIFT) -# define SDIO_DCTRL_16KBYTES (14 << SDIO_DCTRL_DBLOCKSIZE_SHIFT) -#define SDIO_DCTRL_RWSTART (1 << 8) /* Bit 8: Read wait start */ -#define SDIO_DCTRL_RWSTOP (1 << 9) /* Bit 9: Read wait stop */ -#define SDIO_DCTRL_RWMOD (1 << 10) /* Bit 10: Read wait mode */ -#define SDIO_DCTRL_SDIOEN (1 << 11) /* Bit 11: SD I/O enable functions */ - -#define SDIO_DCTRL_RESET (0) /* Reset value */ - -#define SDIO_DCTRL_DTEN_BB (STM32_SDIO_DCTRL_BB + (0 * 4)) -#define SDIO_DCTRL_DTDIR_BB (STM32_SDIO_DCTRL_BB + (1 * 4)) -#define SDIO_DCTRL_DTMODE_BB (STM32_SDIO_DCTRL_BB + (2 * 4)) -#define SDIO_DCTRL_DMAEN_BB (STM32_SDIO_DCTRL_BB + (3 * 4)) -#define SDIO_DCTRL_RWSTART_BB (STM32_SDIO_DCTRL_BB + (8 * 4)) -#define SDIO_DCTRL_RWSTOP_BB (STM32_SDIO_DCTRL_BB + (9 * 4)) -#define SDIO_DCTRL_RWMOD_BB (STM32_SDIO_DCTRL_BB + (10 * 4)) -#define SDIO_DCTRL_SDIOEN_BB (STM32_SDIO_DCTRL_BB + (11 * 4)) - -#define SDIO_DATACOUNT_SHIFT (0) -#define SDIO_DATACOUNT_MASK (0x01ffffff << SDIO_DATACOUNT_SHIFT) - -#define SDIO_STA_CCRCFAIL (1 << 0) /* Bit 0: Command response CRC fail */ -#define SDIO_STA_DCRCFAIL (1 << 1) /* Bit 1: Data block CRC fail */ -#define SDIO_STA_CTIMEOUT (1 << 2) /* Bit 2: Command response timeout */ -#define SDIO_STA_DTIMEOUT (1 << 3) /* Bit 3: Data timeout */ -#define SDIO_STA_TXUNDERR (1 << 4) /* Bit 4: Transmit FIFO underrun error */ -#define SDIO_STA_RXOVERR (1 << 5) /* Bit 5: Received FIFO overrun error */ -#define SDIO_STA_CMDREND (1 << 6) /* Bit 6: Command response received */ -#define SDIO_STA_CMDSENT (1 << 7) /* Bit 7: Command sent */ -#define SDIO_STA_DATAEND (1 << 8) /* Bit 8: Data end */ -#define SDIO_STA_STBITERR (1 << 9) /* Bit 9: Start bit not detected */ -#define SDIO_STA_DBCKEND (1 << 10) /* Bit 10: Data block sent/received */ -#define SDIO_STA_CMDACT (1 << 11) /* Bit 11: Command transfer in progress */ -#define SDIO_STA_TXACT (1 << 12) /* Bit 12: Data transmit in progress */ -#define SDIO_STA_RXACT (1 << 13) /* Bit 13: Data receive in progress */ -#define SDIO_STA_TXFIFOHE (1 << 14) /* Bit 14: Transmit FIFO half empty */ -#define SDIO_STA_RXFIFOHF (1 << 15) /* Bit 15: Receive FIFO half full */ -#define SDIO_STA_TXFIFOF (1 << 16) /* Bit 16: Transmit FIFO full */ -#define SDIO_STA_RXFIFOF (1 << 17) /* Bit 17: Receive FIFO full */ -#define SDIO_STA_TXFIFOE (1 << 18) /* Bit 18: Transmit FIFO empty */ -#define SDIO_STA_RXFIFOE (1 << 19) /* Bit 19: Receive FIFO empty */ -#define SDIO_STA_TXDAVL (1 << 20) /* Bit 20: Data available in transmit FIFO */ -#define SDIO_STA_RXDAVL (1 << 21) /* Bit 21: Data available in receive FIFO */ -#define SDIO_STA_SDIOIT (1 << 22) /* Bit 22: SDIO interrupt received */ -#define SDIO_STA_CEATAEND (1 << 23) /* Bit 23: CMD6 CE-ATA command completion */ - -#define SDIO_ICR_CCRCFAILC (1 << 0) /* Bit 0: CCRCFAIL flag clear bit */ -#define SDIO_ICR_DCRCFAILC (1 << 1) /* Bit 1: DCRCFAIL flag clear bit */ -#define SDIO_ICR_CTIMEOUTC (1 << 2) /* Bit 2: CTIMEOUT flag clear bit */ -#define SDIO_ICR_DTIMEOUTC (1 << 3) /* Bit 3: DTIMEOUT flag clear bit */ -#define SDIO_ICR_TXUNDERRC (1 << 4) /* Bit 4: TXUNDERR flag clear bit */ -#define SDIO_ICR_RXOVERRC (1 << 5) /* Bit 5: RXOVERR flag clear bit */ -#define SDIO_ICR_CMDRENDC (1 << 6) /* Bit 6: CMDREND flag clear bit */ -#define SDIO_ICR_CMDSENTC (1 << 7) /* Bit 7: CMDSENT flag clear bit */ -#define SDIO_ICR_DATAENDC (1 << 8) /* Bit 8: DATAEND flag clear bit */ -#define SDIO_ICR_STBITERRC (1 << 9) /* Bit 9: STBITERR flag clear bit */ -#define SDIO_ICR_DBCKENDC (1 << 10) /* Bit 10: DBCKEND flag clear bit */ -#define SDIO_ICR_SDIOITC (1 << 22) /* Bit 22: SDIOIT flag clear bit */ -#define SDIO_ICR_CEATAENDC (1 << 23) /* Bit 23: CEATAEND flag clear bit */ - -#define SDIO_ICR_RESET 0x00c007ff -#define SDIO_ICR_STATICFLAGS 0x000005ff - -#define SDIO_MASK_CCRCFAILIE (1 << 0) /* Bit 0: Command CRC fail interrupt enable */ -#define SDIO_MASK_DCRCFAILIE (1 << 1) /* Bit 1: Data CRC fail interrupt enable */ -#define SDIO_MASK_CTIMEOUTIE (1 << 2) /* Bit 2: Command timeout interrupt enable */ -#define SDIO_MASK_DTIMEOUTIE (1 << 3) /* Bit 3: Data timeout interrupt enable */ -#define SDIO_MASK_TXUNDERRIE (1 << 4) /* Bit 4: Tx FIFO underrun error interrupt enable */ -#define SDIO_MASK_RXOVERRIE (1 << 5) /* Bit 5: Rx FIFO overrun error interrupt enable */ -#define SDIO_MASK_CMDRENDIE (1 << 6) /* Bit 6: Command response received interrupt enable */ -#define SDIO_MASK_CMDSENTIE (1 << 7) /* Bit 7: Command sent interrupt enable */ -#define SDIO_MASK_DATAENDIE (1 << 8) /* Bit 8: Data end interrupt enable */ -#define SDIO_MASK_STBITERRIE (1 << 9) /* Bit 9: Start bit error interrupt enable */ -#define SDIO_MASK_DBCKENDIE (1 << 10) /* Bit 10: Data block end interrupt enable */ -#define SDIO_MASK_CMDACTIE (1 << 11) /* Bit 11: Command acting interrupt enable */ -#define SDIO_MASK_TXACTIE (1 << 12) /* Bit 12: Data transmit acting interrupt enable */ -#define SDIO_MASK_RXACTIE (1 << 13) /* Bit 13: Data receive acting interrupt enable */ -#define SDIO_MASK_TXFIFOHEIE (1 << 14) /* Bit 14: Tx FIFO half empty interrupt enable */ -#define SDIO_MASK_RXFIFOHFIE (1 << 15) /* Bit 15: Rx FIFO half full interrupt enable */ -#define SDIO_MASK_TXFIFOFIE (1 << 16) /* Bit 16: Tx FIFO full interrupt enable */ -#define SDIO_MASK_RXFIFOFIE (1 << 17) /* Bit 17: Rx FIFO full interrupt enable */ -#define SDIO_MASK_TXFIFOEIE (1 << 18) /* Bit 18: Tx FIFO empty interrupt enable */ -#define SDIO_MASK_RXFIFOEIE (1 << 19) /* Bit 19: Rx FIFO empty interrupt enable */ -#define SDIO_MASK_TXDAVLIE (1 << 20) /* Bit 20: Data available in Tx FIFO interrupt enable */ -#define SDIO_MASK_RXDAVLIE (1 << 21) /* Bit 21: Data available in Rx FIFO interrupt enable */ -#define SDIO_MASK_SDIOITIE (1 << 22) /* Bit 22: SDIO mode interrupt received interrupt enable */ -#define SDIO_MASK_CEATAENDIE (1 << 23) /* Bit 23: CE-ATA command completion interrupt enable */ - -#define SDIO_MASK_RESET (0) - -#define SDIO_FIFOCNT_SHIFT (0) -#define SDIO_FIFOCNT_MASK (0x01ffffff << SDIO_FIFOCNT_SHIFT) - -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_SDIO_H */ diff --git a/arch/arm/src/stm32/hardware/stm32_spi.h b/arch/arm/src/stm32/hardware/stm32_spi.h deleted file mode 100644 index b52e278e38083..0000000000000 --- a/arch/arm/src/stm32/hardware/stm32_spi.h +++ /dev/null @@ -1,283 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/hardware/stm32_spi.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_SPI_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_SPI_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include "chip.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* SPI version **************************************************************/ - -/* SPI IP v1 is default unless v2 or greater is specified for this chip */ - -#undef HAVE_SPI_I2S /* No I2S mode in the SPI peripheral */ -#undef HAVE_SPI_I2S_ASTRT /* No I2S asynchronous start capability */ -#undef HAVE_SPI_TI_MODE /* Motorola frame mode only; no TI mode */ -#undef HAVE_SPI_ARB_DATA_SIZE /* Data size 8 or 16 bit; not arbitrary 4-16 bit */ -#undef HAVE_SPI_FIFOS /* No Tx/Rx FIFOs */ -#undef HAVE_SPI_NSSP /* No NSS Pulse Management in master mode */ - -#if defined(STM32_HAVE_IP_SPI_V2) -# define HAVE_SPI_I2S /* Some SPI peripherals have I2S mode */ -# undef HAVE_SPI_I2S_ASTRT /* No I2S asynchronous start capability */ -# define HAVE_SPI_TI_MODE /* Have Motorola and TI frame modes */ -# undef HAVE_SPI_ARB_DATA_SIZE /* Data size 8 or 16 bit; not arbitrary 4-16 bit */ -# undef HAVE_SPI_FIFOS /* No Tx/Rx FIFOs */ -# undef HAVE_SPI_NSSP /* No NSS Pulse Management in master mode */ -#endif - -#if defined(STM32_HAVE_IP_SPI_V3) -# define HAVE_SPI_I2S /* Some SPI peripherals have I2S mode */ -# undef HAVE_SPI_I2S_ASTRT /* No I2S asynchronous start capability */ -# define HAVE_SPI_TI_MODE /* Have Motorola and TI frame modes */ -# define HAVE_SPI_ARB_DATA_SIZE /* Supports arbitrary data size from 4-16 bits */ -# define HAVE_SPI_FIFOS /* Have Tx/Rx FIFOs */ -# undef HAVE_SPI_NSSP /* No NSS Pulse Management in master mode */ -#endif - -#if defined(STM32_HAVE_IP_SPI_V4) -# define HAVE_SPI_I2S /* Some SPI peripherals have I2S mode */ -# define HAVE_SPI_I2S_ASTRT /* Supports I2S asynchronous start capability */ -# define HAVE_SPI_TI_MODE /* Have Motorola and TI frame modes */ -# define HAVE_SPI_ARB_DATA_SIZE /* Supports arbitrary data size from 4-16 bits */ -# define HAVE_SPI_FIFOS /* Have Tx/Rx FIFOs */ -# define HAVE_SPI_NSSP /* Have NSS Pulse Management in master mode */ -#endif - -/* Maximum allowed speed as per specifications for all SPIs */ - -#if defined(CONFIG_STM32_STM32F4XXX) -# define STM32_SPI_CLK_MAX 37500000UL -#else -# define STM32_SPI_CLK_MAX 18000000UL -#endif - -/* Register Offsets *********************************************************/ - -#define STM32_SPI_CR1_OFFSET 0x0000 /* SPI Control Register 1 (16-bit) */ -#define STM32_SPI_CR2_OFFSET 0x0004 /* SPI control register 2 (16-bit) */ -#define STM32_SPI_SR_OFFSET 0x0008 /* SPI status register (16-bit) */ -#define STM32_SPI_DR_OFFSET 0x000c /* SPI data register (16-bit) */ -#define STM32_SPI_CRCPR_OFFSET 0x0010 /* SPI CRC polynomial register (16-bit) */ -#define STM32_SPI_RXCRCR_OFFSET 0x0014 /* SPI Rx CRC register (16-bit) */ -#define STM32_SPI_TXCRCR_OFFSET 0x0018 /* SPI Tx CRC register (16-bit) */ - -#if defined(HAVE_SPI_I2S) -# define STM32_SPI_I2SCFGR_OFFSET 0x001c /* I2S configuration register */ -# define STM32_SPI_I2SPR_OFFSET 0x0020 /* I2S prescaler register */ -#endif - -/* Register Addresses *******************************************************/ - -#if STM32_NSPI > 0 -# define STM32_SPI1_CR1 (STM32_SPI1_BASE + STM32_SPI_CR1_OFFSET) -# define STM32_SPI1_CR2 (STM32_SPI1_BASE + STM32_SPI_CR2_OFFSET) -# define STM32_SPI1_SR (STM32_SPI1_BASE + STM32_SPI_SR_OFFSET) -# define STM32_SPI1_DR (STM32_SPI1_BASE + STM32_SPI_DR_OFFSET) -# define STM32_SPI1_CRCPR (STM32_SPI1_BASE + STM32_SPI_CRCPR_OFFSET) -# define STM32_SPI1_RXCRCR (STM32_SPI1_BASE + STM32_SPI_RXCRCR_OFFSET) -# define STM32_SPI1_TXCRCR (STM32_SPI1_BASE + STM32_SPI_TXCRCR_OFFSET) -#endif - -#if STM32_NSPI > 1 -# define STM32_SPI2_CR1 (STM32_SPI2_BASE + STM32_SPI_CR1_OFFSET) -# define STM32_SPI2_CR2 (STM32_SPI2_BASE + STM32_SPI_CR2_OFFSET) -# define STM32_SPI2_SR (STM32_SPI2_BASE + STM32_SPI_SR_OFFSET) -# define STM32_SPI2_DR (STM32_SPI2_BASE + STM32_SPI_DR_OFFSET) -# define STM32_SPI2_CRCPR (STM32_SPI2_BASE + STM32_SPI_CRCPR_OFFSET) -# define STM32_SPI2_RXCRCR (STM32_SPI2_BASE + STM32_SPI_RXCRCR_OFFSET) -# define STM32_SPI2_TXCRCR (STM32_SPI2_BASE + STM32_SPI_TXCRCR_OFFSET) -# if defined(HAVE_SPI_I2S) -# define STM32_SPI2_I2SCFGR (STM32_SPI2_BASE + STM32_SPI_I2SCFGR_OFFSET) -# define STM32_SPI2_I2SPR (STM32_SPI2_BASE + STM32_SPI_I2SPR_OFFSET) -# endif -#endif - -#if STM32_NSPI > 2 -# define STM32_SPI3_CR1 (STM32_SPI3_BASE + STM32_SPI_CR1_OFFSET) -# define STM32_SPI3_CR2 (STM32_SPI3_BASE + STM32_SPI_CR2_OFFSET) -# define STM32_SPI3_SR (STM32_SPI3_BASE + STM32_SPI_SR_OFFSET) -# define STM32_SPI3_DR (STM32_SPI3_BASE + STM32_SPI_DR_OFFSET) -# define STM32_SPI3_CRCPR (STM32_SPI3_BASE + STM32_SPI_CRCPR_OFFSET) -# define STM32_SPI3_RXCRCR (STM32_SPI3_BASE + STM32_SPI_RXCRCR_OFFSET) -# define STM32_SPI3_TXCRCR (STM32_SPI3_BASE + STM32_SPI_TXCRCR_OFFSET) -# if defined(HAVE_SPI_I2S) -# define STM32_SPI3_I2SCFGR (STM32_SPI3_BASE + STM32_SPI_I2SCFGR_OFFSET) -# define STM32_SPI3_I2SPR (STM32_SPI3_BASE + STM32_SPI_I2SPR_OFFSET) -# endif -#endif - -/* Register Bitfield Definitions ********************************************/ - -/* SPI Control Register 1 */ - -#define SPI_CR1_CPHA (1 << 0) /* Bit 0: Clock Phase */ -#define SPI_CR1_CPOL (1 << 1) /* Bit 1: Clock Polarity */ -#define SPI_CR1_MSTR (1 << 2) /* Bit 2: Master Selection */ -#define SPI_CR1_BR_SHIFT (3) /* Bits 5:3 Baud Rate Control */ -#define SPI_CR1_BR_MASK (7 << SPI_CR1_BR_SHIFT) -# define SPI_CR1_FPCLCKd2 (0 << SPI_CR1_BR_SHIFT) /* 000: fPCLK/2 */ -# define SPI_CR1_FPCLCKd4 (1 << SPI_CR1_BR_SHIFT) /* 001: fPCLK/4 */ -# define SPI_CR1_FPCLCKd8 (2 << SPI_CR1_BR_SHIFT) /* 010: fPCLK/8 */ -# define SPI_CR1_FPCLCKd16 (3 << SPI_CR1_BR_SHIFT) /* 011: fPCLK/16 */ -# define SPI_CR1_FPCLCKd32 (4 << SPI_CR1_BR_SHIFT) /* 100: fPCLK/32 */ -# define SPI_CR1_FPCLCKd64 (5 << SPI_CR1_BR_SHIFT) /* 101: fPCLK/64 */ -# define SPI_CR1_FPCLCKd128 (6 << SPI_CR1_BR_SHIFT) /* 110: fPCLK/128 */ -# define SPI_CR1_FPCLCKd256 (7 << SPI_CR1_BR_SHIFT) /* 111: fPCLK/256 */ -#define SPI_CR1_SPE (1 << 6) /* Bit 6: SPI Enable */ -#define SPI_CR1_LSBFIRST (1 << 7) /* Bit 7: Frame Format */ -#define SPI_CR1_SSI (1 << 8) /* Bit 8: Internal slave select */ -#define SPI_CR1_SSM (1 << 9) /* Bit 9: Software slave management */ -#define SPI_CR1_RXONLY (1 << 10) /* Bit 10: Receive only */ -#if defined(HAVE_SPI_ARB_DATA_SIZE) -# define SPI_CR1_CRCL (1 << 11) /* Bit 11: CRC length */ -#else -# define SPI_CR1_DFF (1 << 11) /* Bit 11: Data Frame Format */ -#endif -#define SPI_CR1_CRCNEXT (1 << 12) /* Bit 12: Transmit CRC next */ -#define SPI_CR1_CRCEN (1 << 13) /* Bit 13: Hardware CRC calculation enable */ -#define SPI_CR1_BIDIOE (1 << 14) /* Bit 14: Output enable in bidirectional mode */ -#define SPI_CR1_BIDIMODE (1 << 15) /* Bit 15: Bidirectional data mode enable */ - -/* SPI Control Register 2 */ - -#define SPI_CR2_RXDMAEN (1 << 0) /* Bit 0: Rx Buffer DMA Enable */ -#define SPI_CR2_TXDMAEN (1 << 1) /* Bit 1: Tx Buffer DMA Enable */ -#define SPI_CR2_SSOE (1 << 2) /* Bit 2: SS Output Enable */ - -#if defined(HAVE_SPI_NSSP) -# define SPI_CR2_NSSP (1 << 3) /* Bit 3: NSS Pulse Management (Master mode only) */ -#endif - -#if defined(HAVE_SPI_TI_MODE) -# define SPI_CR2_FRF (1 << 4) /* Bit 4: Frame format: 0=Motorola, 1=TI */ -#endif - -#define SPI_CR2_ERRIE (1 << 5) /* Bit 5: Error interrupt enable */ -#define SPI_CR2_RXNEIE (1 << 6) /* Bit 6: RX buffer not empty interrupt enable */ -#define SPI_CR2_TXEIE (1 << 7) /* Bit 7: Tx buffer empty interrupt enable */ - -#if defined(HAVE_SPI_ARB_DATA_SIZE) -# define SPI_CR2_DS_SHIFT (8) /* Bits 8-11: Data size */ -# define SPI_CR2_DS_MASK (15 << SPI_CR2_DS_SHIFT) -# define SPI_CR2_DS(n) ((uint32_t)((n) - 1) << SPI_CR2_DS_SHIFT) -# define SPI_CR2_DS_4BIT (3 << SPI_CR2_DS_SHIFT) -# define SPI_CR2_DS_5BIT (4 << SPI_CR2_DS_SHIFT) -# define SPI_CR2_DS_6BIT (5 << SPI_CR2_DS_SHIFT) -# define SPI_CR2_DS_7BIT (6 << SPI_CR2_DS_SHIFT) -# define SPI_CR2_DS_8BIT (7 << SPI_CR2_DS_SHIFT) -# define SPI_CR2_DS_9BIT (8 << SPI_CR2_DS_SHIFT) -# define SPI_CR2_DS_10BIT (9 << SPI_CR2_DS_SHIFT) -# define SPI_CR2_DS_11BIT (10 << SPI_CR2_DS_SHIFT) -# define SPI_CR2_DS_12BIT (11 << SPI_CR2_DS_SHIFT) -# define SPI_CR2_DS_13BIT (12 << SPI_CR2_DS_SHIFT) -# define SPI_CR2_DS_14BIT (13 << SPI_CR2_DS_SHIFT) -# define SPI_CR2_DS_15BIT (14 << SPI_CR2_DS_SHIFT) -# define SPI_CR2_DS_16BIT (15 << SPI_CR2_DS_SHIFT) -# define SPI_CR2_FRXTH (1 << 12) /* Bit 12: FIFO reception threshold */ -# define SPI_CR2_LDMARX (1 << 13) /* Bit 13: Last DMA transfer for reception */ -# define SPI_CR2_LDMATX (1 << 14) /* Bit 14: Last DMA transfer for transmission */ -#endif - -/* SPI status register */ - -#define SPI_SR_RXNE (1 << 0) /* Bit 0: Receive buffer not empty */ -#define SPI_SR_TXE (1 << 1) /* Bit 1: Transmit buffer empty */ - -#if defined(HAVE_SPI_I2S) -# define SPI_SR_CHSIDE (1 << 2) /* Bit 2: Channel side */ -# define SPI_SR_UDR (1 << 3) /* Bit 3: Underrun flag */ -#endif - -#define SPI_SR_CRCERR (1 << 4) /* Bit 4: CRC error flag */ -#define SPI_SR_MODF (1 << 5) /* Bit 5: Mode fault */ -#define SPI_SR_OVR (1 << 6) /* Bit 6: Overrun flag */ -#define SPI_SR_BSY (1 << 7) /* Bit 7: Busy flag */ - -#if defined(HAVE_SPI_I2S) || defined(HAVE_SPI_TI_MODE) -# define SPI_SR_FRE (1 << 8) /* Bit 8: TI frame format error */ -#endif - -#if defined(HAVE_SPI_FIFOS) -# define SPI_SR_FRLVL_SHIFT (9) /* Bits 9-10: FIFO reception level */ -# define SPI_SR_FRLVL_MASK (3 << SPI_SR_FRLVL_SHIFT) -# define SPI_SR_FRLVL_EMPTY (0 << SPI_SR_FRLVL_SHIFT) /* FIFO empty */ -# define SPI_SR_FRLVL_QUARTER (1 << SPI_SR_FRLVL_SHIFT) /* 1/4 FIFO */ -# define SPI_SR_FRLVL_HALF (2 << SPI_SR_FRLVL_SHIFT) /* 1/2 FIFO */ -# define SPI_SR_FRLVL_FULL (3 << SPI_SR_FRLVL_SHIFT) /* FIFO full */ -# define SPI_SR_FTLVL_SHIFT (11) /* Bits 11-12: FIFO transmission level */ -# define SPI_SR_FTLVL_MASK (3 << SPI_SR_FTLVL_SHIFT) -# define SPI_SR_FTLVL_EMPTY (0 << SPI_SR_FTLVL_SHIFT) /* FIFO empty */ -# define SPI_SR_FTLVL_QUARTER (1 << SPI_SR_FTLVL_SHIFT) /* 1/4 FIFO */ -# define SPI_SR_FTLVL_HALF (2 << SPI_SR_FTLVL_SHIFT) /* 1/2 FIFO */ -# define SPI_SR_FTLVL_FULL (3 << SPI_SR_FTLVL_SHIFT) /* FIFO full */ -#endif - -/* I2S configuration register */ - -#if defined(HAVE_SPI_I2S) -# define SPI_I2SCFGR_CHLEN (1 << 0) /* Bit 0: Channel length (number of bits per audio channel) */ -# define SPI_I2SCFGR_DATLEN_SHIFT (1) /* Bit 1-2: Data length to be transferred */ -# define SPI_I2SCFGR_DATLEN_MASK (3 << SPI_I2SCFGR_DATLEN_SHIFT) -# define SPI_I2SCFGR_DATLEN_16BIT (0 << SPI_I2SCFGR_DATLEN_SHIFT) /* 00: 16-bit data length */ -# define SPI_I2SCFGR_DATLEN_8BIT (1 << SPI_I2SCFGR_DATLEN_SHIFT) /* 01: 24-bit data length */ -# define SPI_I2SCFGR_DATLEN_32BIT (2 << SPI_I2SCFGR_DATLEN_SHIFT) /* 10: 32-bit data length */ -# define SPI_I2SCFGR_CKPOL (1 << 3) /* Bit 3: Steady state clock polarity */ -# define SPI_I2SCFGR_I2SSTD_SHIFT (4) /* Bit 4-5: I2S standard selection */ -# define SPI_I2SCFGR_I2SSTD_MASK (3 << SPI_I2SCFGR_I2SSTD_SHIFT) -# define SPI_I2SCFGR_I2SSTD_PHILLIPS (0 << SPI_I2SCFGR_I2SSTD_SHIFT) /* 00: I2S Phillips standard. */ -# define SPI_I2SCFGR_I2SSTD_MSB (1 << SPI_I2SCFGR_I2SSTD_SHIFT) /* 01: MSB justified standard (left justified) */ -# define SPI_I2SCFGR_I2SSTD_LSB (2 << SPI_I2SCFGR_I2SSTD_SHIFT) /* 10: LSB justified standard (right justified) */ -# define SPI_I2SCFGR_I2SSTD_PCM (3 << SPI_I2SCFGR_I2SSTD_SHIFT) /* 11: PCM standard */ -# define SPI_I2SCFGR_PCMSYNC (1 << 7) /* Bit 7: PCM frame synchronization */ -# define SPI_I2SCFGR_I2SCFG_SHIFT (8) /* Bit 8-9: I2S configuration mode */ -# define SPI_I2SCFGR_I2SCFG_MASK (3 << SPI_I2SCFGR_I2SCFG_SHIFT) -# define SPI_I2SCFGR_I2SCFG_STX (0 << SPI_I2SCFGR_I2SCFG_SHIFT) /* 00: Slave - transmit */ -# define SPI_I2SCFGR_I2SCFG_SRX (1 << SPI_I2SCFGR_I2SCFG_SHIFT) /* 01: Slave - receive */ -# define SPI_I2SCFGR_I2SCFG_MTX (2 << SPI_I2SCFGR_I2SCFG_SHIFT) /* 10: Master - transmit */ -# define SPI_I2SCFGR_I2SCFG_MRX (3 << SPI_I2SCFGR_I2SCFG_SHIFT) /* 11: Master - receive */ -# define SPI_I2SCFGR_I2SE (1 << 10) /* Bit 10: I2S Enable */ -# define SPI_I2SCFGR_I2SMOD (1 << 11) /* Bit 11: I2S mode selection */ -# if defined(HAVE_SPI_I2S_ASTRT) -# define SPI_I2SCFGR_ASTRTEN (1 << 12) /* Bit 12: Asynchronous start enable */ -# endif -#endif - -/* I2S prescaler register */ - -#if defined(HAVE_SPI_I2S) -# define SPI_I2SPR_I2SDIV_SHIFT (0) /* Bit 0-7: I2S Linear prescaler */ -# define SPI_I2SPR_I2SDIV_MASK (0xff << SPI_I2SPR_I2SDIV_SHIFT) -# define SPI_I2SPR_ODD (1 << 8) /* Bit 8: Odd factor for the prescaler */ -# define SPI_I2SPR_MCKOE (1 << 9) /* Bit 9: Master clock output enable */ -#endif - -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_SPI_H */ diff --git a/arch/arm/src/stm32/hardware/stm32_tim.h b/arch/arm/src/stm32/hardware/stm32_tim.h deleted file mode 100644 index 7adb23e656706..0000000000000 --- a/arch/arm/src/stm32/hardware/stm32_tim.h +++ /dev/null @@ -1,39 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/hardware/stm32_tim.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_TIM_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_TIM_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#if defined(CONFIG_STM32_HAVE_IP_TIMERS_V1) || \ - defined(CONFIG_STM32_HAVE_IP_TIMERS_V2) -# include "stm32_tim_v1v2.h" -#elif defined(CONFIG_STM32_HAVE_IP_TIMERS_V3) -# include "stm32_tim_v3.h" -#else -# error "STM32 TIMER IP version not specified" -#endif - -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_TIM_H */ diff --git a/arch/arm/src/stm32/hardware/stm32_usbdev.h b/arch/arm/src/stm32/hardware/stm32_usbdev.h deleted file mode 100644 index a2c0e40029465..0000000000000 --- a/arch/arm/src/stm32/hardware/stm32_usbdev.h +++ /dev/null @@ -1,227 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/hardware/stm32_usbdev.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_USBDEV_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_USBDEV_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include "chip.h" - -#if defined(CONFIG_STM32_STM32L15XX) || defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F30XX) \ - || defined(CONFIG_STM32_STM32F37XX) - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Register Offsets *********************************************************/ - -/* Endpoint Registers */ - -#define STM32_USB_EPR_OFFSET(n) ((n) << 2) /* USB endpoint n register (16-bits) */ - -#define STM32_USB_EP0R_OFFSET 0x0000 /* USB endpoint 0 register (16-bits) */ -#define STM32_USB_EP1R_OFFSET 0x0004 /* USB endpoint 1 register (16-bits) */ -#define STM32_USB_EP2R_OFFSET 0x0008 /* USB endpoint 2 register (16-bits) */ -#define STM32_USB_EP3R_OFFSET 0x000c /* USB endpoint 3 register (16-bits) */ -#define STM32_USB_EP4R_OFFSET 0x0010 /* USB endpoint 4 register (16-bits) */ -#define STM32_USB_EP5R_OFFSET 0x0014 /* USB endpoint 5 register (16-bits) */ -#define STM32_USB_EP6R_OFFSET 0x0018 /* USB endpoint 6 register (16-bits) */ -#define STM32_USB_EP7R_OFFSET 0x001c /* USB endpoint 7 register (16-bits) */ - -/* Common Registers */ - -#define STM32_USB_CNTR_OFFSET 0x0040 /* USB control register (16-bits) */ -#define STM32_USB_ISTR_OFFSET 0x0044 /* USB interrupt status register (16-bits) */ -#define STM32_USB_FNR_OFFSET 0x0048 /* USB frame number register (16-bits) */ -#define STM32_USB_DADDR_OFFSET 0x004c /* USB device address (16-bits) */ -#define STM32_USB_BTABLE_OFFSET 0x0050 /* Buffer table address (16-bits) */ - -/* Buffer Descriptor Table (Relatative to BTABLE address) */ - -#define STM32_USB_ADDR_TX_WOFFSET (0) /* Transmission buffer address n (16-bits) */ -#define STM32_USB_COUNT_TX_WOFFSET (2) /* Transmission byte count n (16-bits) */ -#define STM32_USB_ADDR_RX_WOFFSET (4) /* Reception buffer address n (16-bits) */ -#define STM32_USB_COUNT_RX_WOFFSET (6) /* Reception byte count n (16-bits) */ - -#define STM32_USB_BTABLE_RADDR(ep,o) ((((uint32_t)getreg16(STM32_USB_BTABLE) + ((ep) << 3)) + (o)) << 1) -#define STM32_USB_ADDR_TX_OFFSET(ep) STM32_USB_BTABLE_RADDR(ep,STM32_USB_ADDR_TX_WOFFSET) -#define STM32_USB_COUNT_TX_OFFSET(ep) STM32_USB_BTABLE_RADDR(ep,STM32_USB_COUNT_TX_WOFFSET) -#define STM32_USB_ADDR_RX_OFFSET(ep) STM32_USB_BTABLE_RADDR(ep,STM32_USB_ADDR_RX_WOFFSET) -#define STM32_USB_COUNT_RX_OFFSET(ep) STM32_USB_BTABLE_RADDR(ep,STM32_USB_COUNT_RX_WOFFSET) - -/* Register Addresses *******************************************************/ - -/* Endpoint Registers */ - -#define STM32_USB_EPR(n) (STM32_USB_BASE+STM32_USB_EPR_OFFSET(n)) -#define STM32_USB_EP0R (STM32_USB_BASE+STM32_USB_EP0R_OFFSET) -#define STM32_USB_EP1R (STM32_USB_BASE+STM32_USB_EP1R_OFFSET) -#define STM32_USB_EP2R (STM32_USB_BASE+STM32_USB_EP2R_OFFSET) -#define STM32_USB_EP3R (STM32_USB_BASE+STM32_USB_EP3R_OFFSET) -#define STM32_USB_EP4R (STM32_USB_BASE+STM32_USB_EP4R_OFFSET) -#define STM32_USB_EP5R (STM32_USB_BASE+STM32_USB_EP5R_OFFSET) -#define STM32_USB_EP6R (STM32_USB_BASE+STM32_USB_EP6R_OFFSET) -#define STM32_USB_EP7R (STM32_USB_BASE+STM32_USB_EP7R_OFFSET) - -/* Common Registers */ - -#define STM32_USB_CNTR (STM32_USB_BASE+STM32_USB_CNTR_OFFSET) -#define STM32_USB_ISTR (STM32_USB_BASE+STM32_USB_ISTR_OFFSET) -#define STM32_USB_FNR (STM32_USB_BASE+STM32_USB_FNR_OFFSET) -#define STM32_USB_DADDR (STM32_USB_BASE+STM32_USB_DADDR_OFFSET) -#define STM32_USB_BTABLE (STM32_USB_BASE+STM32_USB_BTABLE_OFFSET) - -/* Buffer Descriptor Table (Relatative to BTABLE address) */ - -#define STM32_USB_BTABLE_ADDR(ep,o) (STM32_USBRAM_BASE+STM32_USB_BTABLE_RADDR(ep,o)) -#define STM32_USB_ADDR_TX(ep) STM32_USB_BTABLE_ADDR(ep,STM32_USB_ADDR_TX_WOFFSET) -#define STM32_USB_COUNT_TX(ep) STM32_USB_BTABLE_ADDR(ep,STM32_USB_COUNT_TX_WOFFSET) -#define STM32_USB_ADDR_RX(ep) STM32_USB_BTABLE_ADDR(ep,STM32_USB_ADDR_RX_WOFFSET) -#define STM32_USB_COUNT_RX(ep) STM32_USB_BTABLE_ADDR(ep,STM32_USB_COUNT_RX_WOFFSET) - -/* Register Bitfield Definitions ********************************************/ - -/* USB endpoint register */ - -#define USB_EPR_EA_SHIFT (0) /* Bits 3:0 [3:0]: Endpoint Address */ -#define USB_EPR_EA_MASK (0X0f << USB_EPR_EA_SHIFT) -#define USB_EPR_STATTX_SHIFT (4) /* Bits 5-4: Status bits, for transmission transfers */ -#define USB_EPR_STATTX_MASK (3 << USB_EPR_STATTX_SHIFT) -# define USB_EPR_STATTX_DIS (0 << USB_EPR_STATTX_SHIFT) /* EndPoint TX DISabled */ -# define USB_EPR_STATTX_STALL (1 << USB_EPR_STATTX_SHIFT) /* EndPoint TX STALLed */ -# define USB_EPR_STATTX_NAK (2 << USB_EPR_STATTX_SHIFT) /* EndPoint TX NAKed */ -# define USB_EPR_STATTX_VALID (3 << USB_EPR_STATTX_SHIFT) /* EndPoint TX VALID */ -# define USB_EPR_STATTX_DTOG1 (1 << USB_EPR_STATTX_SHIFT) /* EndPoint TX Data Toggle bit1 */ -# define USB_EPR_STATTX_DTOG2 (2 << USB_EPR_STATTX_SHIFT) /* EndPoint TX Data Toggle bit2 */ - -#define USB_EPR_DTOG_TX (1 << 6) /* Bit 6: Data Toggle, for transmission transfers */ -#define USB_EPR_CTR_TX (1 << 7) /* Bit 7: Correct Transfer for transmission */ -#define USB_EPR_EP_KIND (1 << 8) /* Bit 8: Endpoint Kind */ -#define USB_EPR_EPTYPE_SHIFT (9) /* Bits 10-9: Endpoint type */ -#define USB_EPR_EPTYPE_MASK (3 << USB_EPR_EPTYPE_SHIFT) -# define USB_EPR_EPTYPE_BULK (0 << USB_EPR_EPTYPE_SHIFT) /* EndPoint BULK */ -# define USB_EPR_EPTYPE_CONTROL (1 << USB_EPR_EPTYPE_SHIFT) /* EndPoint CONTROL */ -# define USB_EPR_EPTYPE_ISOC (2 << USB_EPR_EPTYPE_SHIFT) /* EndPoint ISOCHRONOUS */ -# define USB_EPR_EPTYPE_INTERRUPT (3 << USB_EPR_EPTYPE_SHIFT) /* EndPoint INTERRUPT */ - -#define USB_EPR_SETUP (1 << 11) /* Bit 11: Setup transaction completed */ -#define USB_EPR_STATRX_SHIFT (12) /* Bits 13-12: Status bits, for reception transfers */ -#define USB_EPR_STATRX_MASK (3 << USB_EPR_STATRX_SHIFT) -# define USB_EPR_STATRX_DIS (0 << USB_EPR_STATRX_SHIFT) /* EndPoint RX DISabled */ -# define USB_EPR_STATRX_STALL (1 << USB_EPR_STATRX_SHIFT) /* EndPoint RX STALLed */ -# define USB_EPR_STATRX_NAK (2 << USB_EPR_STATRX_SHIFT) /* EndPoint RX NAKed */ -# define USB_EPR_STATRX_VALID (3 << USB_EPR_STATRX_SHIFT) /* EndPoint RX VALID */ -# define USB_EPR_STATRX_DTOG1 (1 << USB_EPR_STATRX_SHIFT) /* EndPoint RX Data TOGgle bit1 */ -# define USB_EPR_STATRX_DTOG2 (2 << USB_EPR_STATRX_SHIFT) /* EndPoint RX Data TOGgle bit1 */ - -#define USB_EPR_DTOG_RX (1 << 14) /* Bit 14: Data Toggle, for reception transfers */ -#define USB_EPR_CTR_RX (1 << 15) /* Bit 15: Correct Transfer for reception */ - -/* USB control register */ - -#define USB_CNTR_FRES (1 << 0) /* Bit 0: Force USB Reset */ -#define USB_CNTR_PDWN (1 << 1) /* Bit 1: Power down */ -#define USB_CNTR_LPMODE (1 << 2) /* Bit 2: Low-power mode */ -#define USB_CNTR_FSUSP (1 << 3) /* Bit 3: Force suspend */ -#define USB_CNTR_RESUME (1 << 4) /* Bit 4: Resume request */ -#define USB_CNTR_ESOFM (1 << 8) /* Bit 8: Expected Start Of Frame Interrupt Mask */ -#define USB_CNTR_SOFM (1 << 9) /* Bit 9: Start Of Frame Interrupt Mask */ -#define USB_CNTR_RESETM (1 << 10) /* Bit 10: USB Reset Interrupt Mask */ -#define USB_CNTR_SUSPM (1 << 11) /* Bit 11: Suspend mode Interrupt Mask */ -#define USB_CNTR_WKUPM (1 << 12) /* Bit 12: Wakeup Interrupt Mask */ -#define USB_CNTR_ERRM (1 << 13) /* Bit 13: Error Interrupt Mask */ -#define USB_CNTR_DMAOVRNM (1 << 14) /* Bit 14: Packet Memory Area Over / Underrun Interrupt Mask */ -#define USB_CNTR_CTRM (1 << 15) /* Bit 15: Correct Transfer Interrupt Mask */ - -#define USB_CNTR_ALLINTS (USB_CNTR_ESOFM|USB_CNTR_SOFM|USB_CNTR_RESETM|USB_CNTR_SUSPM|\ - USB_CNTR_WKUPM|USB_CNTR_ERRM|USB_CNTR_DMAOVRNM|USB_CNTR_CTRM) - -/* USB interrupt status register */ - -#define USB_ISTR_EPID_SHIFT (0) /* Bits 3-0: Endpoint Identifier */ -#define USB_ISTR_EPID_MASK (0x0f << USB_ISTR_EPID_SHIFT) -#define USB_ISTR_DIR (1 << 4) /* Bit 4: Direction of transaction */ -#define USB_ISTR_ESOF (1 << 8) /* Bit 8: Expected Start Of Frame */ -#define USB_ISTR_SOF (1 << 9) /* Bit 9: Start Of Frame */ -#define USB_ISTR_RESET (1 << 10) /* Bit 10: USB RESET request */ -#define USB_ISTR_SUSP (1 << 11) /* Bit 11: Suspend mode request */ -#define USB_ISTR_WKUP (1 << 12) /* Bit 12: Wake up */ -#define USB_ISTR_ERR (1 << 13) /* Bit 13: Error */ -#define USB_ISTR_DMAOVRN (1 << 14) /* Bit 14: Packet Memory Area Over / Underrun */ -#define USB_ISTR_CTR (1 << 15) /* Bit 15: Correct Transfer */ - -#define USB_ISTR_ALLINTS (USB_ISTR_ESOF|USB_ISTR_SOF|USB_ISTR_RESET|USB_ISTR_SUSP|\ - USB_ISTR_WKUP|USB_ISTR_ERR|USB_ISTR_DMAOVRN|USB_ISTR_CTR) - -/* USB frame number register */ - -#define USB_FNR_FN_SHIFT (0) /* Bits 10-0: Frame Number */ -#define USB_FNR_FN_MASK (0x07ff << USB_FNR_FN_SHIFT) -#define USB_FNR_LSOF_SHIFT (11) /* Bits 12-11: Lost SOF */ -#define USB_FNR_LSOF_MASK (3 << USB_FNR_LSOF_SHIFT) -#define USB_FNR_LCK (1 << 13) /* Bit 13: Locked */ -#define USB_FNR_RXDM (1 << 14) /* Bit 14: Receive Data - Line Status */ -#define USB_FNR_RXDP (1 << 15) /* Bit 15: Receive Data + Line Status */ - -/* USB device address */ - -#define USB_DADDR_ADD_SHIFT (0) /* Bits 6-0: Device Address */ -#define USB_DADDR_ADD_MASK (0x7f << USB_DADDR_ADD_SHIFT) -#define USB_DADDR_EF (1 << 7) /* Bit 7: Enable Function */ - -/* Buffer table address */ - -#define USB_BTABLE_SHIFT (3) /* Bits 15:3: Buffer Table */ -#define USB_BTABLE_MASK (0x1fff << USB_BTABLE_SHIFT) - -/* Transmission buffer address */ - -#define USB_ADDR_TX_ZERO (1 << 0) /* Bit 0 Must always be written as ‘0’ */ -#define USB_ADDR_TX_SHIFT (1) /* Bits 15-1: Transmission Buffer Address */ -#define USB_ADDR_TX_MASK (0x7fff << USB_ADDR_ADDR_TX_SHIFT) - -/* Transmission byte count */ - -#define USB_COUNT_TX_SHIFT (0) /* Bits 9-0: Transmission Byte Count */ -#define USB_COUNT_TX_MASK (0x03ff << USB_COUNT_COUNT_TX_SHIFT) - -/* Reception buffer address */ - -#define USB_ADDR_RX_ZERO (1 << 0) /* Bit 0 This bit must always be written as ‘0’ */ -#define USB_ADDR_RX_SHIFT (1) /* Bits 15:1 ADDRn_RX[15:1]: Reception Buffer Address */ -#define USB_ADDR_RX_MASK (0x7fff << USB_ADDR_RX_SHIFT) - -/* Reception byte count */ - -#define USB_COUNT_RX_BL_SIZE (1 << 15) /* Bit 15: BLock SIZE. */ -#define USB_COUNT_RX_NUM_BLOCK_SHIFT (10) /* Bits 14-10: Number of blocks */ -#define USB_COUNT_RX_NUM_BLOCK_MASK (0x1f << USB_COUNT_RX_NUM_BLOCK_SHIFT) -#define USB_COUNT_RX_SHIFT (0) /* Bits 9-0: Reception Byte Count */ -#define USB_COUNT_RX_MASK (0x03ff << USB_COUNT_RX_SHIFT) - -#endif /* CONFIG_STM32_STM32F10XX || CONFIG_STM32_STM32F30XX || CONFIG_STM32_STM32F37XX */ -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_USBDEV_H */ diff --git a/arch/arm/src/stm32/hardware/stm32_usbfs.h b/arch/arm/src/stm32/hardware/stm32_usbfs.h deleted file mode 100644 index 1d83a91e3f0d2..0000000000000 --- a/arch/arm/src/stm32/hardware/stm32_usbfs.h +++ /dev/null @@ -1,250 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/hardware/stm32_usbfs.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_USBFS_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_USBFS_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include "chip.h" - -#if defined(CONFIG_STM32_USBFS) - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Register Offsets *********************************************************/ - -/* Endpoint Registers */ - -#define STM32_USB_EPR_OFFSET(n) ((n) << 2) /* USB endpoint n register (16-bits) */ - -#define STM32_USB_EP0R_OFFSET 0x0000 /* USB endpoint 0 register (16-bits) */ -#define STM32_USB_EP1R_OFFSET 0x0004 /* USB endpoint 1 register (16-bits) */ -#define STM32_USB_EP2R_OFFSET 0x0008 /* USB endpoint 2 register (16-bits) */ -#define STM32_USB_EP3R_OFFSET 0x000c /* USB endpoint 3 register (16-bits) */ -#define STM32_USB_EP4R_OFFSET 0x0010 /* USB endpoint 4 register (16-bits) */ -#define STM32_USB_EP5R_OFFSET 0x0014 /* USB endpoint 5 register (16-bits) */ -#define STM32_USB_EP6R_OFFSET 0x0018 /* USB endpoint 6 register (16-bits) */ -#define STM32_USB_EP7R_OFFSET 0x001c /* USB endpoint 7 register (16-bits) */ - -/* Common Registers */ - -#define STM32_USB_CNTR_OFFSET 0x0040 /* USB control register (16-bits) */ -#define STM32_USB_ISTR_OFFSET 0x0044 /* USB interrupt status register (16-bits) */ -#define STM32_USB_FNR_OFFSET 0x0048 /* USB frame number register (16-bits) */ -#define STM32_USB_DADDR_OFFSET 0x004c /* USB device address (16-bits) */ -#define STM32_USB_BTABLE_OFFSET 0x0050 /* Buffer table address (16-bits) */ -#define STM32_USB_LPMCSR_OFFSET 0x0054 /* LPM control and status register */ -#define STM32_USB_BCDR_OFFSET 0x0058 /* Battery charging detector */ - -/* Buffer Descriptor Table (Relatative to BTABLE address) */ - -#define STM32_USB_ADDR_TX_WOFFSET (0) /* Transmission buffer address n (16-bits) */ -#define STM32_USB_COUNT_TX_WOFFSET (2) /* Transmission byte count n (16-bits) */ -#define STM32_USB_ADDR_RX_WOFFSET (4) /* Reception buffer address n (16-bits) */ -#define STM32_USB_COUNT_RX_WOFFSET (6) /* Reception byte count n (16-bits) */ - -#define STM32_USB_BTABLE_RADDR(ep,o) (((uint32_t)getreg16(STM32_USB_BTABLE) + ((ep) << 3)) + (o)) -#define STM32_USB_ADDR_TX_OFFSET(ep) STM32_USB_BTABLE_RADDR(ep,STM32_USB_ADDR_TX_WOFFSET) -#define STM32_USB_COUNT_TX_OFFSET(ep) STM32_USB_BTABLE_RADDR(ep,STM32_USB_COUNT_TX_WOFFSET) -#define STM32_USB_ADDR_RX_OFFSET(ep) STM32_USB_BTABLE_RADDR(ep,STM32_USB_ADDR_RX_WOFFSET) -#define STM32_USB_COUNT_RX_OFFSET(ep) STM32_USB_BTABLE_RADDR(ep,STM32_USB_COUNT_RX_WOFFSET) - -/* Register Addresses *******************************************************/ - -/* Endpoint Registers */ - -#define STM32_USB_EPR(n) (STM32_USB_BASE+STM32_USB_EPR_OFFSET(n)) -#define STM32_USB_EP0R (STM32_USB_BASE+STM32_USB_EP0R_OFFSET) -#define STM32_USB_EP1R (STM32_USB_BASE+STM32_USB_EP1R_OFFSET) -#define STM32_USB_EP2R (STM32_USB_BASE+STM32_USB_EP2R_OFFSET) -#define STM32_USB_EP3R (STM32_USB_BASE+STM32_USB_EP3R_OFFSET) -#define STM32_USB_EP4R (STM32_USB_BASE+STM32_USB_EP4R_OFFSET) -#define STM32_USB_EP5R (STM32_USB_BASE+STM32_USB_EP5R_OFFSET) -#define STM32_USB_EP6R (STM32_USB_BASE+STM32_USB_EP6R_OFFSET) -#define STM32_USB_EP7R (STM32_USB_BASE+STM32_USB_EP7R_OFFSET) - -/* Common Registers */ - -#define STM32_USB_CNTR (STM32_USB_BASE+STM32_USB_CNTR_OFFSET) -#define STM32_USB_ISTR (STM32_USB_BASE+STM32_USB_ISTR_OFFSET) -#define STM32_USB_FNR (STM32_USB_BASE+STM32_USB_FNR_OFFSET) -#define STM32_USB_DADDR (STM32_USB_BASE+STM32_USB_DADDR_OFFSET) -#define STM32_USB_BTABLE (STM32_USB_BASE+STM32_USB_BTABLE_OFFSET) -#define STM32_USB_LPMCSR (STM32_USB_BASE+STM32_USB_LPMCSR_OFFSET) -#define STM32_USB_BCDR (STM32_USB_BASE+STM32_USB_BCDR_OFFSET) - -/* Buffer Descriptor Table (Relatative to BTABLE address) */ - -#define STM32_USB_BTABLE_ADDR(ep,o) (STM32_USBRAM_BASE+STM32_USB_BTABLE_RADDR(ep,o)) -#define STM32_USB_ADDR_TX(ep) STM32_USB_BTABLE_ADDR(ep,STM32_USB_ADDR_TX_WOFFSET) -#define STM32_USB_COUNT_TX(ep) STM32_USB_BTABLE_ADDR(ep,STM32_USB_COUNT_TX_WOFFSET) -#define STM32_USB_ADDR_RX(ep) STM32_USB_BTABLE_ADDR(ep,STM32_USB_ADDR_RX_WOFFSET) -#define STM32_USB_COUNT_RX(ep) STM32_USB_BTABLE_ADDR(ep,STM32_USB_COUNT_RX_WOFFSET) - -/* Register Bitfield Definitions ********************************************/ - -/* USB endpoint register */ - -#define USB_EPR_EA_SHIFT (0) /* Bits 3:0 [3:0]: Endpoint Address */ -#define USB_EPR_EA_MASK (0X0f << USB_EPR_EA_SHIFT) -#define USB_EPR_STATTX_SHIFT (4) /* Bits 5-4: Status bits, for transmission transfers */ -#define USB_EPR_STATTX_MASK (3 << USB_EPR_STATTX_SHIFT) -# define USB_EPR_STATTX_DIS (0 << USB_EPR_STATTX_SHIFT) /* EndPoint TX DISabled */ -# define USB_EPR_STATTX_STALL (1 << USB_EPR_STATTX_SHIFT) /* EndPoint TX STALLed */ -# define USB_EPR_STATTX_NAK (2 << USB_EPR_STATTX_SHIFT) /* EndPoint TX NAKed */ -# define USB_EPR_STATTX_VALID (3 << USB_EPR_STATTX_SHIFT) /* EndPoint TX VALID */ -# define USB_EPR_STATTX_DTOG1 (1 << USB_EPR_STATTX_SHIFT) /* EndPoint TX Data Toggle bit1 */ -# define USB_EPR_STATTX_DTOG2 (2 << USB_EPR_STATTX_SHIFT) /* EndPoint TX Data Toggle bit2 */ - -#define USB_EPR_DTOG_TX (1 << 6) /* Bit 6: Data Toggle, for transmission transfers */ -#define USB_EPR_CTR_TX (1 << 7) /* Bit 7: Correct Transfer for transmission */ -#define USB_EPR_EP_KIND (1 << 8) /* Bit 8: Endpoint Kind */ -#define USB_EPR_EPTYPE_SHIFT (9) /* Bits 10-9: Endpoint type */ -#define USB_EPR_EPTYPE_MASK (3 << USB_EPR_EPTYPE_SHIFT) -# define USB_EPR_EPTYPE_BULK (0 << USB_EPR_EPTYPE_SHIFT) /* EndPoint BULK */ -# define USB_EPR_EPTYPE_CONTROL (1 << USB_EPR_EPTYPE_SHIFT) /* EndPoint CONTROL */ -# define USB_EPR_EPTYPE_ISOC (2 << USB_EPR_EPTYPE_SHIFT) /* EndPoint ISOCHRONOUS */ -# define USB_EPR_EPTYPE_INTERRUPT (3 << USB_EPR_EPTYPE_SHIFT) /* EndPoint INTERRUPT */ - -#define USB_EPR_SETUP (1 << 11) /* Bit 11: Setup transaction completed */ -#define USB_EPR_STATRX_SHIFT (12) /* Bits 13-12: Status bits, for reception transfers */ -#define USB_EPR_STATRX_MASK (3 << USB_EPR_STATRX_SHIFT) -# define USB_EPR_STATRX_DIS (0 << USB_EPR_STATRX_SHIFT) /* EndPoint RX DISabled */ -# define USB_EPR_STATRX_STALL (1 << USB_EPR_STATRX_SHIFT) /* EndPoint RX STALLed */ -# define USB_EPR_STATRX_NAK (2 << USB_EPR_STATRX_SHIFT) /* EndPoint RX NAKed */ -# define USB_EPR_STATRX_VALID (3 << USB_EPR_STATRX_SHIFT) /* EndPoint RX VALID */ -# define USB_EPR_STATRX_DTOG1 (1 << USB_EPR_STATRX_SHIFT) /* EndPoint RX Data TOGgle bit1 */ -# define USB_EPR_STATRX_DTOG2 (2 << USB_EPR_STATRX_SHIFT) /* EndPoint RX Data TOGgle bit1 */ - -#define USB_EPR_DTOG_RX (1 << 14) /* Bit 14: Data Toggle, for reception transfers */ -#define USB_EPR_CTR_RX (1 << 15) /* Bit 15: Correct Transfer for reception */ - -/* USB control register */ - -#define USB_CNTR_FRES (1 << 0) /* Bit 0: Force USB Reset */ -#define USB_CNTR_PDWN (1 << 1) /* Bit 1: Power down */ -#define USB_CNTR_LPMODE (1 << 2) /* Bit 2: Low-power mode */ -#define USB_CNTR_FSUSP (1 << 3) /* Bit 3: Force suspend */ -#define USB_CNTR_RESUME (1 << 4) /* Bit 4: Resume request */ -#define USB_CNTR_ESOFM (1 << 8) /* Bit 8: Expected Start Of Frame Interrupt Mask */ -#define USB_CNTR_SOFM (1 << 9) /* Bit 9: Start Of Frame Interrupt Mask */ -#define USB_CNTR_RESETM (1 << 10) /* Bit 10: USB Reset Interrupt Mask */ -#define USB_CNTR_SUSPM (1 << 11) /* Bit 11: Suspend mode Interrupt Mask */ -#define USB_CNTR_WKUPM (1 << 12) /* Bit 12: Wakeup Interrupt Mask */ -#define USB_CNTR_ERRM (1 << 13) /* Bit 13: Error Interrupt Mask */ -#define USB_CNTR_DMAOVRNM (1 << 14) /* Bit 14: Packet Memory Area Over / Underrun Interrupt Mask */ -#define USB_CNTR_CTRM (1 << 15) /* Bit 15: Correct Transfer Interrupt Mask */ - -#define USB_CNTR_ALLINTS (USB_CNTR_ESOFM|USB_CNTR_SOFM|USB_CNTR_RESETM|USB_CNTR_SUSPM|\ - USB_CNTR_WKUPM|USB_CNTR_ERRM|USB_CNTR_DMAOVRNM|USB_CNTR_CTRM) - -/* USB interrupt status register */ - -#define USB_ISTR_EPID_SHIFT (0) /* Bits 3-0: Endpoint Identifier */ -#define USB_ISTR_EPID_MASK (0x0f << USB_ISTR_EPID_SHIFT) -#define USB_ISTR_DIR (1 << 4) /* Bit 4: Direction of transaction */ -#define USB_ISTR_ESOF (1 << 8) /* Bit 8: Expected Start Of Frame */ -#define USB_ISTR_SOF (1 << 9) /* Bit 9: Start Of Frame */ -#define USB_ISTR_RESET (1 << 10) /* Bit 10: USB RESET request */ -#define USB_ISTR_SUSP (1 << 11) /* Bit 11: Suspend mode request */ -#define USB_ISTR_WKUP (1 << 12) /* Bit 12: Wake up */ -#define USB_ISTR_ERR (1 << 13) /* Bit 13: Error */ -#define USB_ISTR_DMAOVRN (1 << 14) /* Bit 14: Packet Memory Area Over / Underrun */ -#define USB_ISTR_CTR (1 << 15) /* Bit 15: Correct Transfer */ - -#define USB_ISTR_ALLINTS (USB_ISTR_ESOF|USB_ISTR_SOF|USB_ISTR_RESET|USB_ISTR_SUSP|\ - USB_ISTR_WKUP|USB_ISTR_ERR|USB_ISTR_DMAOVRN|USB_ISTR_CTR) - -/* USB frame number register */ - -#define USB_FNR_FN_SHIFT (0) /* Bits 10-0: Frame Number */ -#define USB_FNR_FN_MASK (0x07ff << USB_FNR_FN_SHIFT) -#define USB_FNR_LSOF_SHIFT (11) /* Bits 12-11: Lost SOF */ -#define USB_FNR_LSOF_MASK (3 << USB_FNR_LSOF_SHIFT) -#define USB_FNR_LCK (1 << 13) /* Bit 13: Locked */ -#define USB_FNR_RXDM (1 << 14) /* Bit 14: Receive Data - Line Status */ -#define USB_FNR_RXDP (1 << 15) /* Bit 15: Receive Data + Line Status */ - -/* USB device address */ - -#define USB_DADDR_ADD_SHIFT (0) /* Bits 6-0: Device Address */ -#define USB_DADDR_ADD_MASK (0x7f << USB_DADDR_ADD_SHIFT) -#define USB_DADDR_EF (1 << 7) /* Bit 7: Enable Function */ - -/* Buffer table address */ - -#define USB_BTABLE_SHIFT (3) /* Bits 15:3: Buffer Table */ -#define USB_BTABLE_MASK (0x1fff << USB_BTABLE_SHIFT) - -/* Transmission buffer address */ - -#define USB_ADDR_TX_ZERO (1 << 0) /* Bit 0 Must always be written as ‘0’ */ -#define USB_ADDR_TX_SHIFT (1) /* Bits 15-1: Transmission Buffer Address */ -#define USB_ADDR_TX_MASK (0x7fff << USB_ADDR_ADDR_TX_SHIFT) - -/* Transmission byte count */ - -#define USB_COUNT_TX_SHIFT (0) /* Bits 9-0: Transmission Byte Count */ -#define USB_COUNT_TX_MASK (0x03ff << USB_COUNT_COUNT_TX_SHIFT) - -/* Reception buffer address */ - -#define USB_ADDR_RX_ZERO (1 << 0) /* Bit 0 This bit must always be written as ‘0’ */ -#define USB_ADDR_RX_SHIFT (1) /* Bits 15:1 ADDRn_RX[15:1]: Reception Buffer Address */ -#define USB_ADDR_RX_MASK (0x7fff << USB_ADDR_RX_SHIFT) - -/* Reception byte count */ - -#define USB_COUNT_RX_BL_SIZE (1 << 15) /* Bit 15: BLock SIZE. */ -#define USB_COUNT_RX_NUM_BLOCK_SHIFT (10) /* Bits 14-10: Number of blocks */ -#define USB_COUNT_RX_NUM_BLOCK_MASK (0x1f << USB_COUNT_RX_NUM_BLOCK_SHIFT) -#define USB_COUNT_RX_SHIFT (0) /* Bits 9-0: Reception Byte Count */ -#define USB_COUNT_RX_MASK (0x03ff << USB_COUNT_RX_SHIFT) - -/* LPM control and status register */ - -#define USB_LPMCSR_LPMEN (1 << 0) /* Bit 0: LPM support enable */ -#define USB_LPMCSR_LPMACK (1 << 1) /* Bit 1: LPM Token acknowledge enable */ -#define USB_LPMCSR_REMWAKE (1 << 3) /* Bit 3: bRemoteWake value */ -#define USB_LPMCSR_BESL_SHIFT (4) /* Bits 7-4: BESL value */ -#define USB_LPMCSR_BESL_MASK (0x0f << USB_LPMCSR_BESL_SHIFT) - -/* Battery charging detector */ - -#define USB_BCDR_BCDEN (1 << 0) /* Bit 0: Battery charging detector (BCD) enable */ -#define USB_BCDR_DCDEN (1 << 1) /* Bit 1: Data contact detection (DCD) mode enable */ -#define USB_BCDR_PDEN (1 << 2) /* Bit 2: Primary detection (PD) mode enable */ -#define USB_BCDR_SDEN (1 << 3) /* Bit 3: Secondary detection (SD) mode enable */ -#define USB_BCDR_DCDET (1 << 4) /* Bit 4: Data contact detection (DCD) status */ -#define USB_BCDR_PDET (1 << 5) /* Bit 5: Primary detection (PD) status */ -#define USB_BCDR_SDET (1 << 6) /* Bit 6: Secondary detection (SD) status */ -#define USB_BCDR_PS2DET (1 << 7) /* Bit 7: DM pull-up detection status */ -#define USB_BCDR_DPPU (1 << 15) /* Bit 15: DP pull-up control */ - -#endif /* CONFIG_STM32_USBFS */ -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_USBFS_H */ diff --git a/arch/arm/src/stm32/hardware/stm32_wdg.h b/arch/arm/src/stm32/hardware/stm32_wdg.h deleted file mode 100644 index 55ac57d3b64de..0000000000000 --- a/arch/arm/src/stm32/hardware/stm32_wdg.h +++ /dev/null @@ -1,150 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/hardware/stm32_wdg.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_WDG_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_WDG_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "chip.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Register Offsets *********************************************************/ - -#define STM32_IWDG_KR_OFFSET 0x0000 /* Key register (32-bit) */ -#define STM32_IWDG_PR_OFFSET 0x0004 /* Prescaler register (32-bit) */ -#define STM32_IWDG_RLR_OFFSET 0x0008 /* Reload register (32-bit) */ -#define STM32_IWDG_SR_OFFSET 0x000c /* Status register (32-bit) */ -#if defined(CONFIG_STM32_STM32F30XX) -# define STM32_IWDG_WINR_OFFSET 0x000c /* Window register (32-bit) */ -#endif - -#define STM32_WWDG_CR_OFFSET 0x0000 /* Control Register (32-bit) */ -#define STM32_WWDG_CFR_OFFSET 0x0004 /* Configuration register (32-bit) */ -#define STM32_WWDG_SR_OFFSET 0x0008 /* Status register (32-bit) */ - -/* Register Addresses *******************************************************/ - -#define STM32_IWDG_KR (STM32_IWDG_BASE+STM32_IWDG_KR_OFFSET) -#define STM32_IWDG_PR (STM32_IWDG_BASE+STM32_IWDG_PR_OFFSET) -#define STM32_IWDG_RLR (STM32_IWDG_BASE+STM32_IWDG_RLR_OFFSET) -#define STM32_IWDG_SR (STM32_IWDG_BASE+STM32_IWDG_SR_OFFSET) -#if defined(CONFIG_STM32_STM32F30XX) -# define STM32_IWDG_WINR (STM32_IWDG_BASE+STM32_IWDG_WINR_OFFSET) -#endif - -#define STM32_WWDG_CR (STM32_WWDG_BASE+STM32_WWDG_CR_OFFSET) -#define STM32_WWDG_CFR (STM32_WWDG_BASE+STM32_WWDG_CFR_OFFSET) -#define STM32_WWDG_SR (STM32_WWDG_BASE+STM32_WWDG_SR_OFFSET) - -/* Register Bitfield Definitions ********************************************/ - -/* Key register (32-bit) */ - -#define IWDG_KR_KEY_SHIFT (0) /* Bits 15-0: Key value (write only, read 0000h) */ -#define IWDG_KR_KEY_MASK (0xffff << IWDG_KR_KEY_SHIFT) - -#define IWDG_KR_KEY_ENABLE (0x5555) /* Enable register access */ -#define IWDG_KR_KEY_DISABLE (0x0000) /* Disable register access */ -#define IWDG_KR_KEY_RELOAD (0xaaaa) /* Reload the counter */ -#define IWDG_KR_KEY_START (0xcccc) /* Start the watchdog */ - -/* Prescaler register (32-bit) */ - -#define IWDG_PR_SHIFT (0) /* Bits 2-0: Prescaler divider */ -#define IWDG_PR_MASK (7 << IWDG_PR_SHIFT) -# define IWDG_PR_DIV4 (0 << IWDG_PR_SHIFT) /* 000: divider /4 */ -# define IWDG_PR_DIV8 (1 << IWDG_PR_SHIFT) /* 001: divider /8 */ -# define IWDG_PR_DIV16 (2 << IWDG_PR_SHIFT) /* 010: divider /16 */ -# define IWDG_PR_DIV32 (3 << IWDG_PR_SHIFT) /* 011: divider /32 */ -# define IWDG_PR_DIV64 (4 << IWDG_PR_SHIFT) /* 100: divider /64 */ -# define IWDG_PR_DIV128 (5 << IWDG_PR_SHIFT) /* 101: divider /128 */ -# define IWDG_PR_DIV256 (6 << IWDG_PR_SHIFT) /* 11x: divider /256 */ - -/* Reload register (32-bit) */ - -#define IWDG_RLR_RL_SHIFT (0) /* Bits11:0 RL[11:0]: Watchdog counter reload value */ -#define IWDG_RLR_RL_MASK (0x0fff << IWDG_RLR_RL_SHIFT) - -#define IWDG_RLR_MAX (0xfff) - -/* Status register (32-bit) */ - -#define IWDG_SR_PVU (1 << 0) /* Bit 0: Watchdog prescaler value update */ -#define IWDG_SR_RVU (1 << 1) /* Bit 1: Watchdog counter reload value update */ - -#if defined(CONFIG_STM32_STM32F30XX) -# define IWDG_SR_WVU (1 << 2) /* Bit 2: */ -#endif - -/* Window register (32-bit) */ - -#if defined(CONFIG_STM32_STM32F30XX) -# define IWDG_WINR_SHIFT (0) -# define IWDG_WINR_MASK (0x0fff << IWDG_WINR_SHIFT) -#endif - -/* Control Register (32-bit) */ - -#define WWDG_CR_T_SHIFT (0) /* Bits 6:0 T[6:0]: 7-bit counter (MSB to LSB) */ -#define WWDG_CR_T_MASK (0x7f << WWDG_CR_T_SHIFT) -# define WWDG_CR_T_MAX (0x3f << WWDG_CR_T_SHIFT) -# define WWDG_CR_T_RESET (0x40 << WWDG_CR_T_SHIFT) -#define WWDG_CR_WDGA (1 << 7) /* Bit 7: Activation bit */ - -/* Configuration register (32-bit) */ - -#define WWDG_CFR_W_SHIFT (0) /* Bits 6:0 W[6:0] 7-bit window value */ -#define WWDG_CFR_W_MASK (0x7f << WWDG_CFR_W_SHIFT) -#define WWDG_CFR_WDGTB_SHIFT (7) /* Bits 8:7 [1:0]: Timer Base */ -#define WWDG_CFR_WDGTB_MASK (3 << WWDG_CFR_WDGTB_SHIFT) -# define WWDG_CFR_PCLK1 (0 << WWDG_CFR_WDGTB_SHIFT) /* 00: CK Counter Clock (PCLK1 div 4096) div 1 */ -# define WWDG_CFR_PCLK1d2 (1 << WWDG_CFR_WDGTB_SHIFT) /* 01: CK Counter Clock (PCLK1 div 4096) div 2 */ -# define WWDG_CFR_PCLK1d4 (2 << WWDG_CFR_WDGTB_SHIFT) /* 10: CK Counter Clock (PCLK1 div 4096) div 4 */ -# define WWDG_CFR_PCLK1d8 (3 << WWDG_CFR_WDGTB_SHIFT) /* 11: CK Counter Clock (PCLK1 div 4096) div 8 */ - -#define WWDG_CFR_EWI (1 << 9) /* Bit 9: Early Wakeup Interrupt */ - -/* Status register (32-bit) */ - -#define WWDG_SR_EWIF (1 << 0) /* Bit 0: Early Wakeup Interrupt Flag */ - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/**************************************************************************** - * Public Functions Prototypes - ****************************************************************************/ - -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_WDG_H */ diff --git a/arch/arm/src/stm32/hardware/stm32f10xxx_uart.h b/arch/arm/src/stm32/hardware/stm32f10xxx_uart.h deleted file mode 100644 index b499a2cc55714..0000000000000 --- a/arch/arm/src/stm32/hardware/stm32f10xxx_uart.h +++ /dev/null @@ -1,206 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/hardware/stm32f10xxx_uart.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32F10XXX_UART_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32F10XXX_UART_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "chip.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Register Offsets *********************************************************/ - -#define STM32_USART_SR_OFFSET 0x0000 /* Status register (32-bits) */ -#define STM32_USART_DR_OFFSET 0x0004 /* Data register (32-bits) */ -#define STM32_USART_BRR_OFFSET 0x0008 /* Baud Rate Register (32-bits) */ -#define STM32_USART_CR1_OFFSET 0x000c /* Control register 1 (32-bits) */ -#define STM32_USART_CR2_OFFSET 0x0010 /* Control register 2 (32-bits) */ -#define STM32_USART_CR3_OFFSET 0x0014 /* Control register 3 (32-bits) */ -#define STM32_USART_GTPR_OFFSET 0x0018 /* Guard time and prescaler register (32-bits) */ - -/* Register Addresses *******************************************************/ - -#if STM32_NUSART > 0 -# define STM32_USART1_SR (STM32_USART1_BASE+STM32_USART_SR_OFFSET) -# define STM32_USART1_DR (STM32_USART1_BASE+STM32_USART_DR_OFFSET) -# define STM32_USART1_BRR (STM32_USART1_BASE+STM32_USART_BRR_OFFSET) -# define STM32_USART1_CR1 (STM32_USART1_BASE+STM32_USART_CR1_OFFSET) -# define STM32_USART1_CR2 (STM32_USART1_BASE+STM32_USART_CR2_OFFSET) -# define STM32_USART1_CR3 (STM32_USART1_BASE+STM32_USART_CR3_OFFSET) -# define STM32_USART1_GTPR (STM32_USART1_BASE+STM32_USART_GTPR_OFFSET) -#endif - -#if STM32_NUSART > 1 -# define STM32_USART2_SR (STM32_USART2_BASE+STM32_USART_SR_OFFSET) -# define STM32_USART2_DR (STM32_USART2_BASE+STM32_USART_DR_OFFSET) -# define STM32_USART2_BRR (STM32_USART2_BASE+STM32_USART_BRR_OFFSET) -# define STM32_USART2_CR1 (STM32_USART2_BASE+STM32_USART_CR1_OFFSET) -# define STM32_USART2_CR2 (STM32_USART2_BASE+STM32_USART_CR2_OFFSET) -# define STM32_USART2_CR3 (STM32_USART2_BASE+STM32_USART_CR3_OFFSET) -# define STM32_USART2_GTPR (STM32_USART2_BASE+STM32_USART_GTPR_OFFSET) -#endif - -#if STM32_NUSART > 2 -# define STM32_USART3_SR (STM32_USART3_BASE+STM32_USART_SR_OFFSET) -# define STM32_USART3_DR (STM32_USART3_BASE+STM32_USART_DR_OFFSET) -# define STM32_USART3_BRR (STM32_USART3_BASE+STM32_USART_BRR_OFFSET) -# define STM32_USART3_CR1 (STM32_USART3_BASE+STM32_USART_CR1_OFFSET) -# define STM32_USART3_CR2 (STM32_USART3_BASE+STM32_USART_CR2_OFFSET) -# define STM32_USART3_CR3 (STM32_USART3_BASE+STM32_USART_CR3_OFFSET) -# define STM32_USART3_GTPR (STM32_USART3_BASE+STM32_USART_GTPR_OFFSET) -#endif - -#if STM32_NUSART > 3 -# define STM32_UART4_SR (STM32_UART4_BASE+STM32_USART_SR_OFFSET) -# define STM32_UART4_DR (STM32_UART4_BASE+STM32_USART_DR_OFFSET) -# define STM32_UART4_BRR (STM32_UART4_BASE+STM32_USART_BRR_OFFSET) -# define STM32_UART4_CR1 (STM32_UART4_BASE+STM32_USART_CR1_OFFSET) -# define STM32_UART4_CR2 (STM32_UART4_BASE+STM32_USART_CR2_OFFSET) -# define STM32_UART4_CR3 (STM32_UART4_BASE+STM32_USART_CR3_OFFSET) -#endif - -#if STM32_NUSART > 4 -# define STM32_UART5_SR (STM32_UART5_BASE+STM32_USART_SR_OFFSET) -# define STM32_UART5_DR (STM32_UART5_BASE+STM32_USART_DR_OFFSET) -# define STM32_UART5_BRR (STM32_UART5_BASE+STM32_USART_BRR_OFFSET) -# define STM32_UART5_CR1 (STM32_UART5_BASE+STM32_USART_CR1_OFFSET) -# define STM32_UART5_CR2 (STM32_UART5_BASE+STM32_USART_CR2_OFFSET) -# define STM32_UART5_CR3 (STM32_UART5_BASE+STM32_USART_CR3_OFFSET) -#endif - -/* Register Bitfield Definitions ********************************************/ - -/* Status register */ - -#define USART_SR_PE (1 << 0) /* Bit 0: Parity Error */ -#define USART_SR_FE (1 << 1) /* Bit 1: Framing Error */ -#define USART_SR_NE (1 << 2) /* Bit 2: Noise Error Flag */ -#define USART_SR_ORE (1 << 3) /* Bit 3: OverRun Error */ -#define USART_SR_IDLE (1 << 4) /* Bit 4: IDLE line detected */ -#define USART_SR_RXNE (1 << 5) /* Bit 5: Read Data Register Not Empty */ -#define USART_SR_TC (1 << 6) /* Bit 6: Transmission Complete */ -#define USART_SR_TXE (1 << 7) /* Bit 7: Transmit Data Register Empty */ -#define USART_SR_LBD (1 << 8) /* Bit 8: LIN Break Detection Flag */ -#define USART_SR_CTS (1 << 9) /* Bit 9: CTS Flag */ - -#define USART_SR_ALLBITS (0x03ff) -#define USART_SR_CLRBITS (USART_SR_CTS|USART_SR_LBD) /* Cleared by SW write to SR */ - -/* Data register */ - -#define USART_DR_SHIFT (0) /* Bits 8:0: Data value */ -#define USART_DR_MASK (0xff << USART_DR_SHIFT) - -/* Baud Rate Register */ - -#define USART_BRR_FRAC_SHIFT (0) /* Bits 3-0: fraction of USARTDIV */ -#define USART_BRR_FRAC_MASK (0x0f << USART_BRR_FRAC_SHIFT) -#define USART_BRR_MANT_SHIFT (4) /* Bits 15-4: mantissa of USARTDIV */ -#define USART_BRR_MANT_MASK (0x0fff << USART_BRR_MANT_SHIFT) - -/* Control register 1 */ - -#define USART_CR1_SBK (1 << 0) /* Bit 0: Send Break */ -#define USART_CR1_RWU (1 << 1) /* Bit 1: Receiver wakeup */ -#define USART_CR1_RE (1 << 2) /* Bit 2: Receiver Enable */ -#define USART_CR1_TE (1 << 3) /* Bit 3: Transmitter Enable */ -#define USART_CR1_IDLEIE (1 << 4) /* Bit 4: IDLE Interrupt Enable */ -#define USART_CR1_RXNEIE (1 << 5) /* Bit 5: RXNE Interrupt Enable */ -#define USART_CR1_TCIE (1 << 6) /* Bit 6: Transmission Complete Interrupt Enable */ -#define USART_CR1_TXEIE (1 << 7) /* Bit 7: TXE Interrupt Enable */ -#define USART_CR1_PEIE (1 << 8) /* Bit 8: PE Interrupt Enable */ -#define USART_CR1_PS (1 << 9) /* Bit 9: Parity Selection */ -#define USART_CR1_PCE (1 << 10) /* Bit 10: Parity Control Enable */ -#define USART_CR1_WAKE (1 << 11) /* Bit 11: Wakeup method */ -#define USART_CR1_M (1 << 12) /* Bit 12: word length */ -#define USART_CR1_UE (1 << 13) /* Bit 13: USART Enable */ - -#define USART_CR1_ALLINTS (USART_CR1_IDLEIE|USART_CR1_RXNEIE|USART_CR1_TCIE|USART_CR1_PEIE) - -/* Control register 2 */ - -#define USART_CR2_ADD_SHIFT (0) /* Bits 3-0: Address of the USART node */ -#define USART_CR2_ADD_MASK (0x0f << USART_CR2_ADD_SHIFT) -#define USART_CR2_LBDL (1 << 5) /* Bit 5: LIN Break Detection Length */ -#define USART_CR2_LBDIE (1 << 6) /* Bit 6: LIN Break Detection Interrupt Enable */ -#define USART_CR2_LBCL (1 << 8) /* Bit 8: Last Bit Clock pulse */ -#define USART_CR2_CPHA (1 << 9) /* Bit 9: Clock Phase */ -#define USART_CR2_CPOL (1 << 10) /* Bit 10: Clock Polarity */ -#define USART_CR2_CLKEN (1 << 11) /* Bit 11: Clock Enable */ -#define USART_CR2_STOP_SHIFT (12) /* Bits 13-12: STOP bits */ -#define USART_CR2_STOP_MASK (3 << USART_CR2_STOP_SHIFT) -# define USART_CR2_STOP1 (0 << USART_CR2_STOP_SHIFT) /* 00: 1 Stop bit */ -# define USART_CR2_STOP0p5 (1 << USART_CR2_STOP_SHIFT) /* 01: 0.5 Stop bit */ -# define USART_CR2_STOP2 (2 << USART_CR2_STOP_SHIFT) /* 10: 2 Stop bits */ -# define USART_CR2_STOP1p5 (3 << USART_CR2_STOP_SHIFT) /* 11: 1.5 Stop bit */ - -#define USART_CR2_LINEN (1 << 14) /* Bit 14: LIN mode enable */ - -/* Control register 3 */ - -#define USART_CR3_EIE (1 << 0) /* Bit 0: Error Interrupt Enable */ -#define USART_CR3_IREN (1 << 1) /* Bit 1: IrDA mode Enable */ -#define USART_CR3_IRLP (1 << 2) /* Bit 2: IrDA Low-Power */ -#define USART_CR3_HDSEL (1 << 3) /* Bit 3: Half-Duplex Selection */ -#define USART_CR3_NACK (1 << 4) /* Bit 4: Smartcard NACK enable */ -#define USART_CR3_SCEN (1 << 5) /* Bit 5: Smartcard mode enable */ -#define USART_CR3_DMAR (1 << 6) /* Bit 6: DMA Enable Receiver */ -#define USART_CR3_DMAT (1 << 7) /* Bit 7: DMA Enable Transmitter */ -#define USART_CR3_RTSE (1 << 8) /* Bit 8: RTS Enable */ -#define USART_CR3_CTSE (1 << 9) /* Bit 9: CTS Enable */ -#define USART_CR3_CTSIE (1 << 10) /* Bit 10: CTS Interrupt Enable */ - -/* Guard time and prescaler register */ - -#define USART_GTPR_PSC_SHIFT (0) /* Bits 0-7: Prescaler value */ -#define USART_GTPR_PSC_MASK (0xff << USART_GTPR_PSC_SHIFT) -#define USART_GTPR_GT_SHIFT (8) /* Bits 8-15: Guard time value */ -#define USART_GTPR_GT_MASK (0xff << USART_GTPR_GT_SHIFT) - -/* Compatibility definitions ************************************************/ - -/* F3 Transmit/Read registers */ - -#define STM32_USART_RDR_OFFSET STM32_USART_DR_OFFSET /* Receive data register */ -#define STM32_USART_TDR_OFFSET STM32_USART_DR_OFFSET /* Transmit data register */ - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/**************************************************************************** - * Public Functions Prototypes - ****************************************************************************/ - -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32F10XXX_UART_H */ diff --git a/arch/arm/src/stm32/hardware/stm32f20xxx_uart.h b/arch/arm/src/stm32/hardware/stm32f20xxx_uart.h deleted file mode 100644 index ee01472c30a48..0000000000000 --- a/arch/arm/src/stm32/hardware/stm32f20xxx_uart.h +++ /dev/null @@ -1,218 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/hardware/stm32f20xxx_uart.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32F20XXX_UART_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32F20XXX_UART_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "chip.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Register Offsets *********************************************************/ - -#define STM32_USART_SR_OFFSET 0x0000 /* Status register (32-bits) */ -#define STM32_USART_DR_OFFSET 0x0004 /* Data register (32-bits) */ -#define STM32_USART_BRR_OFFSET 0x0008 /* Baud Rate Register (32-bits) */ -#define STM32_USART_CR1_OFFSET 0x000c /* Control register 1 (32-bits) */ -#define STM32_USART_CR2_OFFSET 0x0010 /* Control register 2 (32-bits) */ -#define STM32_USART_CR3_OFFSET 0x0014 /* Control register 3 (32-bits) */ -#define STM32_USART_GTPR_OFFSET 0x0018 /* Guard time and prescaler register (32-bits) */ - -/* Register Addresses *******************************************************/ - -#if STM32_NUSART > 0 -# define STM32_USART1_SR (STM32_USART1_BASE+STM32_USART_SR_OFFSET) -# define STM32_USART1_DR (STM32_USART1_BASE+STM32_USART_DR_OFFSET) -# define STM32_USART1_BRR (STM32_USART1_BASE+STM32_USART_BRR_OFFSET) -# define STM32_USART1_CR1 (STM32_USART1_BASE+STM32_USART_CR1_OFFSET) -# define STM32_USART1_CR2 (STM32_USART1_BASE+STM32_USART_CR2_OFFSET) -# define STM32_USART1_CR3 (STM32_USART1_BASE+STM32_USART_CR3_OFFSET) -# define STM32_USART1_GTPR (STM32_USART1_BASE+STM32_USART_GTPR_OFFSET) -#endif - -#if STM32_NUSART > 1 -# define STM32_USART2_SR (STM32_USART2_BASE+STM32_USART_SR_OFFSET) -# define STM32_USART2_DR (STM32_USART2_BASE+STM32_USART_DR_OFFSET) -# define STM32_USART2_BRR (STM32_USART2_BASE+STM32_USART_BRR_OFFSET) -# define STM32_USART2_CR1 (STM32_USART2_BASE+STM32_USART_CR1_OFFSET) -# define STM32_USART2_CR2 (STM32_USART2_BASE+STM32_USART_CR2_OFFSET) -# define STM32_USART2_CR3 (STM32_USART2_BASE+STM32_USART_CR3_OFFSET) -# define STM32_USART2_GTPR (STM32_USART2_BASE+STM32_USART_GTPR_OFFSET) -#endif - -#if STM32_NUSART > 2 -# define STM32_USART3_SR (STM32_USART3_BASE+STM32_USART_SR_OFFSET) -# define STM32_USART3_DR (STM32_USART3_BASE+STM32_USART_DR_OFFSET) -# define STM32_USART3_BRR (STM32_USART3_BASE+STM32_USART_BRR_OFFSET) -# define STM32_USART3_CR1 (STM32_USART3_BASE+STM32_USART_CR1_OFFSET) -# define STM32_USART3_CR2 (STM32_USART3_BASE+STM32_USART_CR2_OFFSET) -# define STM32_USART3_CR3 (STM32_USART3_BASE+STM32_USART_CR3_OFFSET) -# define STM32_USART3_GTPR (STM32_USART3_BASE+STM32_USART_GTPR_OFFSET) -#endif - -#if STM32_NUSART > 3 -# define STM32_UART4_SR (STM32_UART4_BASE+STM32_USART_SR_OFFSET) -# define STM32_UART4_DR (STM32_UART4_BASE+STM32_USART_DR_OFFSET) -# define STM32_UART4_BRR (STM32_UART4_BASE+STM32_USART_BRR_OFFSET) -# define STM32_UART4_CR1 (STM32_UART4_BASE+STM32_USART_CR1_OFFSET) -# define STM32_UART4_CR2 (STM32_UART4_BASE+STM32_USART_CR2_OFFSET) -# define STM32_UART4_CR3 (STM32_UART4_BASE+STM32_USART_CR3_OFFSET) -#endif - -#if STM32_NUSART > 4 -# define STM32_UART5_SR (STM32_UART5_BASE+STM32_USART_SR_OFFSET) -# define STM32_UART5_DR (STM32_UART5_BASE+STM32_USART_DR_OFFSET) -# define STM32_UART5_BRR (STM32_UART5_BASE+STM32_USART_BRR_OFFSET) -# define STM32_UART5_CR1 (STM32_UART5_BASE+STM32_USART_CR1_OFFSET) -# define STM32_UART5_CR2 (STM32_UART5_BASE+STM32_USART_CR2_OFFSET) -# define STM32_UART5_CR3 (STM32_UART5_BASE+STM32_USART_CR3_OFFSET) -#endif - -#if STM32_NUSART > 5 -# define STM32_USART6_SR (STM32_USART6_BASE+STM32_USART_SR_OFFSET) -# define STM32_USART6_DR (STM32_USART6_BASE+STM32_USART_DR_OFFSET) -# define STM32_USART6_BRR (STM32_USART6_BASE+STM32_USART_BRR_OFFSET) -# define STM32_USART6_CR1 (STM32_USART6_BASE+STM32_USART_CR1_OFFSET) -# define STM32_USART6_CR2 (STM32_USART6_BASE+STM32_USART_CR2_OFFSET) -# define STM32_USART6_CR3 (STM32_USART6_BASE+STM32_USART_CR3_OFFSET) -# define STM32_USART6_GTPR (STM32_USART6_BASE+STM32_USART_GTPR_OFFSET) -#endif - -/* Register Bitfield Definitions ********************************************/ - -/* Status register */ - -#define USART_SR_PE (1 << 0) /* Bit 0: Parity Error */ -#define USART_SR_FE (1 << 1) /* Bit 1: Framing Error */ -#define USART_SR_NE (1 << 2) /* Bit 2: Noise Error Flag */ -#define USART_SR_ORE (1 << 3) /* Bit 3: OverRun Error */ -#define USART_SR_IDLE (1 << 4) /* Bit 4: IDLE line detected */ -#define USART_SR_RXNE (1 << 5) /* Bit 5: Read Data Register Not Empty */ -#define USART_SR_TC (1 << 6) /* Bit 6: Transmission Complete */ -#define USART_SR_TXE (1 << 7) /* Bit 7: Transmit Data Register Empty */ -#define USART_SR_LBD (1 << 8) /* Bit 8: LIN Break Detection Flag */ -#define USART_SR_CTS (1 << 9) /* Bit 9: CTS Flag */ - -#define USART_SR_ALLBITS (0x03ff) -#define USART_SR_CLRBITS (USART_SR_CTS|USART_SR_LBD) /* Cleared by SW write to SR */ - -/* Data register */ - -#define USART_DR_SHIFT (0) /* Bits 8:0: Data value */ -#define USART_DR_MASK (0xff << USART_DR_SHIFT) - -/* Baud Rate Register */ - -#define USART_BRR_FRAC_SHIFT (0) /* Bits 3-0: fraction of USARTDIV */ -#define USART_BRR_FRAC_MASK (0x0f << USART_BRR_FRAC_SHIFT) -#define USART_BRR_MANT_SHIFT (4) /* Bits 15-4: mantissa of USARTDIV */ -#define USART_BRR_MANT_MASK (0x0fff << USART_BRR_MANT_SHIFT) - -/* Control register 1 */ - -#define USART_CR1_SBK (1 << 0) /* Bit 0: Send Break */ -#define USART_CR1_RWU (1 << 1) /* Bit 1: Receiver wakeup */ -#define USART_CR1_RE (1 << 2) /* Bit 2: Receiver Enable */ -#define USART_CR1_TE (1 << 3) /* Bit 3: Transmitter Enable */ -#define USART_CR1_IDLEIE (1 << 4) /* Bit 4: IDLE Interrupt Enable */ -#define USART_CR1_RXNEIE (1 << 5) /* Bit 5: RXNE Interrupt Enable */ -#define USART_CR1_TCIE (1 << 6) /* Bit 6: Transmission Complete Interrupt Enable */ -#define USART_CR1_TXEIE (1 << 7) /* Bit 7: TXE Interrupt Enable */ -#define USART_CR1_PEIE (1 << 8) /* Bit 8: PE Interrupt Enable */ -#define USART_CR1_PS (1 << 9) /* Bit 9: Parity Selection */ -#define USART_CR1_PCE (1 << 10) /* Bit 10: Parity Control Enable */ -#define USART_CR1_WAKE (1 << 11) /* Bit 11: Wakeup method */ -#define USART_CR1_M (1 << 12) /* Bit 12: word length */ -#define USART_CR1_UE (1 << 13) /* Bit 13: USART Enable */ -#define USART_CR1_OVER8 (1 << 15) /* Bit 15: Oversampling mode */ - -#define USART_CR1_ALLINTS (USART_CR1_IDLEIE|USART_CR1_RXNEIE|USART_CR1_TCIE|USART_CR1_PEIE) - -/* Control register 2 */ - -#define USART_CR2_ADD_SHIFT (0) /* Bits 3-0: Address of the USART node */ -#define USART_CR2_ADD_MASK (0x0f << USART_CR2_ADD_SHIFT) -#define USART_CR2_LBDL (1 << 5) /* Bit 5: LIN Break Detection Length */ -#define USART_CR2_LBDIE (1 << 6) /* Bit 6: LIN Break Detection Interrupt Enable */ -#define USART_CR2_LBCL (1 << 8) /* Bit 8: Last Bit Clock pulse */ -#define USART_CR2_CPHA (1 << 9) /* Bit 9: Clock Phase */ -#define USART_CR2_CPOL (1 << 10) /* Bit 10: Clock Polarity */ -#define USART_CR2_CLKEN (1 << 11) /* Bit 11: Clock Enable */ -#define USART_CR2_STOP_SHIFT (12) /* Bits 13-12: STOP bits */ -#define USART_CR2_STOP_MASK (3 << USART_CR2_STOP_SHIFT) -# define USART_CR2_STOP1 (0 << USART_CR2_STOP_SHIFT) /* 00: 1 Stop bit */ -# define USART_CR2_STOP0p5 (1 << USART_CR2_STOP_SHIFT) /* 01: 0.5 Stop bit */ -# define USART_CR2_STOP2 (2 << USART_CR2_STOP_SHIFT) /* 10: 2 Stop bits */ -# define USART_CR2_STOP1p5 (3 << USART_CR2_STOP_SHIFT) /* 11: 1.5 Stop bit */ - -#define USART_CR2_LINEN (1 << 14) /* Bit 14: LIN mode enable */ - -/* Control register 3 */ - -#define USART_CR3_EIE (1 << 0) /* Bit 0: Error Interrupt Enable */ -#define USART_CR3_IREN (1 << 1) /* Bit 1: IrDA mode Enable */ -#define USART_CR3_IRLP (1 << 2) /* Bit 2: IrDA Low-Power */ -#define USART_CR3_HDSEL (1 << 3) /* Bit 3: Half-Duplex Selection */ -#define USART_CR3_NACK (1 << 4) /* Bit 4: Smartcard NACK enable */ -#define USART_CR3_SCEN (1 << 5) /* Bit 5: Smartcard mode enable */ -#define USART_CR3_DMAR (1 << 6) /* Bit 6: DMA Enable Receiver */ -#define USART_CR3_DMAT (1 << 7) /* Bit 7: DMA Enable Transmitter */ -#define USART_CR3_RTSE (1 << 8) /* Bit 8: RTS Enable */ -#define USART_CR3_CTSE (1 << 9) /* Bit 9: CTS Enable */ -#define USART_CR3_CTSIE (1 << 10) /* Bit 10: CTS Interrupt Enable */ -#define USART_CR3_ONEBIT (1 << 11) /* Bit 11: One sample bit method enable */ - -/* Guard time and prescaler register */ - -#define USART_GTPR_PSC_SHIFT (0) /* Bits 0-7: Prescaler value */ -#define USART_GTPR_PSC_MASK (0xff << USART_GTPR_PSC_SHIFT) -#define USART_GTPR_GT_SHIFT (8) /* Bits 8-15: Guard time value */ -#define USART_GTPR_GT_MASK (0xff << USART_GTPR_GT_SHIFT) - -/* Compatibility definitions ************************************************/ - -/* F3 Transmit/Read registers */ - -#define STM32_USART_RDR_OFFSET STM32_USART_DR_OFFSET /* Receive data register */ -#define STM32_USART_TDR_OFFSET STM32_USART_DR_OFFSET /* Transmit data register */ - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/**************************************************************************** - * Public Functions Prototypes - ****************************************************************************/ - -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32F20XXX_UART_H */ diff --git a/arch/arm/src/stm32/hardware/stm32f30xxx_uart.h b/arch/arm/src/stm32/hardware/stm32f30xxx_uart.h deleted file mode 100644 index 18fc6f1b8b974..0000000000000 --- a/arch/arm/src/stm32/hardware/stm32f30xxx_uart.h +++ /dev/null @@ -1,341 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/hardware/stm32f30xxx_uart.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32F30XXX_UART_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32F30XXX_UART_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "chip.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Register Offsets *********************************************************/ - -#define STM32_USART_CR1_OFFSET 0x0000 /* Control register 1 */ -#define STM32_USART_CR2_OFFSET 0x0004 /* Control register 2 */ -#define STM32_USART_CR3_OFFSET 0x0008 /* Control register 3 */ -#define STM32_USART_BRR_OFFSET 0x000c /* Baud Rate Register (32-bits) */ -#define STM32_USART_GTPR_OFFSET 0x0010 /* Guard time and prescaler register */ -#define STM32_USART_RTOR_OFFSET 0x0014 /* Receiver timeout register */ -#define STM32_USART_RQR_OFFSET 0x0018 /* Request register */ -#define STM32_USART_ISR_OFFSET 0x001c /* Interrupt & status register */ -#define STM32_USART_ICR_OFFSET 0x0020 /* Interrupt flag clear register */ -#define STM32_USART_RDR_OFFSET 0x0024 /* Receive data register */ -#define STM32_USART_TDR_OFFSET 0x0028 /* Transmit data register */ - -/* Register Addresses *******************************************************/ - -#if STM32_NUSART > 0 -# define STM32_USART1_CR1 (STM32_USART1_BASE+STM32_USART_CR1_OFFSET) -# define STM32_USART1_CR2 (STM32_USART1_BASE+STM32_USART_CR2_OFFSET) -# define STM32_USART1_CR3 (STM32_USART1_BASE+STM32_USART_CR3_OFFSET) -# define STM32_USART1_BRR (STM32_USART1_BASE+STM32_USART_BRR_OFFSET) -# define STM32_USART1_GTPR (STM32_USART1_BASE+STM32_USART_GTPR_OFFSET) -# define STM32_USART1_RTOR (STM32_USART1_BASE+STM32_USART_RTOR_OFFSET) -# define STM32_USART1_RQR (STM32_USART1_BASE+STM32_USART_RQR_OFFSET) -# define STM32_USART1_GTPR (STM32_USART1_BASE+STM32_USART_GTPR_OFFSET) -# define STM32_USART1_ISR (STM32_USART1_BASE+STM32_USART_ISR_OFFSET) -# define STM32_USART1_ICR (STM32_USART1_BASE+STM32_USART_ICR_OFFSET) -# define STM32_USART1_RDR (STM32_USART1_BASE+STM32_USART_RDR_OFFSET) -# define STM32_USART1_TDR (STM32_USART1_BASE+STM32_USART_TDR_OFFSET) -#endif - -#if STM32_NUSART > 1 -# define STM32_USART2_CR1 (STM32_USART2_BASE+STM32_USART_CR1_OFFSET) -# define STM32_USART2_CR2 (STM32_USART2_BASE+STM32_USART_CR2_OFFSET) -# define STM32_USART2_CR3 (STM32_USART2_BASE+STM32_USART_CR3_OFFSET) -# define STM32_USART2_BRR (STM32_USART2_BASE+STM32_USART_BRR_OFFSET) -# define STM32_USART2_GTPR (STM32_USART2_BASE+STM32_USART_GTPR_OFFSET) -# define STM32_USART2_RTOR (STM32_USART2_BASE+STM32_USART_RTOR_OFFSET) -# define STM32_USART2_RQR (STM32_USART2_BASE+STM32_USART_RQR_OFFSET) -# define STM32_USART2_GTPR (STM32_USART2_BASE+STM32_USART_GTPR_OFFSET) -# define STM32_USART2_ISR (STM32_USART2_BASE+STM32_USART_ISR_OFFSET) -# define STM32_USART2_ICR (STM32_USART2_BASE+STM32_USART_ICR_OFFSET) -# define STM32_USART2_RDR (STM32_USART2_BASE+STM32_USART_RDR_OFFSET) -# define STM32_USART2_TDR (STM32_USART2_BASE+STM32_USART_TDR_OFFSET) -#endif - -#if STM32_NUSART > 2 -# define STM32_USART3_CR1 (STM32_USART3_BASE+STM32_USART_CR1_OFFSET) -# define STM32_USART3_CR2 (STM32_USART3_BASE+STM32_USART_CR2_OFFSET) -# define STM32_USART3_CR3 (STM32_USART3_BASE+STM32_USART_CR3_OFFSET) -# define STM32_USART3_BRR (STM32_USART3_BASE+STM32_USART_BRR_OFFSET) -# define STM32_USART3_GTPR (STM32_USART3_BASE+STM32_USART_GTPR_OFFSET) -# define STM32_USART3_RTOR (STM32_USART3_BASE+STM32_USART_RTOR_OFFSET) -# define STM32_USART3_RQR (STM32_USART3_BASE+STM32_USART_RQR_OFFSET) -# define STM32_USART3_GTPR (STM32_USART3_BASE+STM32_USART_GTPR_OFFSET) -# define STM32_USART3_ISR (STM32_USART3_BASE+STM32_USART_ISR_OFFSET) -# define STM32_USART3_ICR (STM32_USART3_BASE+STM32_USART_ICR_OFFSET) -# define STM32_USART3_RDR (STM32_USART3_BASE+STM32_USART_RDR_OFFSET) -# define STM32_USART3_TDR (STM32_USART3_BASE+STM32_USART_TDR_OFFSET) -#endif - -#if STM32_NUSART > 3 -# define STM32_UART4_CR1 (STM32_UART4_BASE+STM32_USART_CR1_OFFSET) -# define STM32_UART4_CR2 (STM32_UART4_BASE+STM32_USART_CR2_OFFSET) -# define STM32_UART4_CR3 (STM32_UART4_BASE+STM32_USART_CR3_OFFSET) -# define STM32_UART4_BRR (STM32_UART4_BASE+STM32_USART_BRR_OFFSET) -# define STM32_UART4_GTPR (STM32_UART4_BASE+STM32_USART_GTPR_OFFSET) -# define STM32_UART4_RTOR (STM32_UART4_BASE+STM32_USART_RTOR_OFFSET) -# define STM32_UART4_RQR (STM32_UART4_BASE+STM32_USART_RQR_OFFSET) -# define STM32_UART4_GTPR (STM32_UART4_BASE+STM32_USART_GTPR_OFFSET) -# define STM32_UART4_ISR (STM32_UART4_BASE+STM32_USART_ISR_OFFSET) -# define STM32_UART4_ICR (STM32_UART4_BASE+STM32_USART_ICR_OFFSET) -# define STM32_UART4_RDR (STM32_UART4_BASE+STM32_USART_RDR_OFFSET) -# define STM32_UART4_TDR (STM32_UART4_BASE+STM32_USART_TDR_OFFSET) -#endif - -#if STM32_NUSART > 4 -# define STM32_UART5_CR1 (STM32_UART5_BASE+STM32_USART_CR1_OFFSET) -# define STM32_UART5_CR2 (STM32_UART5_BASE+STM32_USART_CR2_OFFSET) -# define STM32_UART5_CR3 (STM32_UART5_BASE+STM32_USART_CR3_OFFSET) -# define STM32_UART5_BRR (STM32_UART5_BASE+STM32_USART_BRR_OFFSET) -# define STM32_UART5_GTPR (STM32_UART5_BASE+STM32_USART_GTPR_OFFSET) -# define STM32_UART5_RTOR (STM32_UART5_BASE+STM32_USART_RTOR_OFFSET) -# define STM32_UART5_RQR (STM32_UART5_BASE+STM32_USART_RQR_OFFSET) -# define STM32_UART5_GTPR (STM32_UART5_BASE+STM32_USART_GTPR_OFFSET) -# define STM32_UART5_ISR (STM32_UART5_BASE+STM32_USART_ISR_OFFSET) -# define STM32_UART5_ICR (STM32_UART5_BASE+STM32_USART_ICR_OFFSET) -# define STM32_UART5_RDR (STM32_UART5_BASE+STM32_USART_RDR_OFFSET) -# define STM32_UART5_TDR (STM32_UART5_BASE+STM32_USART_TDR_OFFSET) -#endif - -/* Register Bitfield Definitions ********************************************/ - -/* Control register 1 */ - -#define USART_CR1_UE (1 << 0) /* Bit 0: USART enable */ -#define USART_CR1_UESM (1 << 1) /* Bit 1: USART enable in Stop mode */ -#define USART_CR1_RE (1 << 2) /* Bit 2: Receiver Enable */ -#define USART_CR1_TE (1 << 3) /* Bit 3: Transmitter Enable */ -#define USART_CR1_IDLEIE (1 << 4) /* Bit 4: IDLE Interrupt Enable */ -#define USART_CR1_RXNEIE (1 << 5) /* Bit 5: RXNE Interrupt Enable */ -#define USART_CR1_TCIE (1 << 6) /* Bit 6: Transmission Complete Interrupt Enable */ -#define USART_CR1_TXEIE (1 << 7) /* Bit 7: TXE Interrupt Enable */ -#define USART_CR1_PEIE (1 << 8) /* Bit 8: PE Interrupt Enable */ - -#define USART_CR1_PS (1 << 9) /* Bit 9: Parity Selection */ -#define USART_CR1_PCE (1 << 10) /* Bit 10: Parity Control Enable */ -#define USART_CR1_WAKE (1 << 11) /* Bit 11: Receiver wakeup method */ -#define USART_CR1_M (1 << 12) /* Bit 12: Word length */ -#define USART_CR1_MME (1 << 13) /* Bit 13: Mute mode enable */ -#define USART_CR1_CMIE (1 << 14) /* Bit 14: Character match interrupt enable */ -#define USART_CR1_OVER8 (1 << 15) /* Bit 15: Oversampling mode */ -#define USART_CR1_DEDT_SHIFT (16) /* Bits 16-20: Driver Enable deassertion time */ -#define USART_CR1_DEDT_MASK (31 << USART_CR1_DEDT_SHIFT) -#define USART_CR1_DEAT_SHIFT (21) /* Bits 21-25: Driver Enable assertion time */ -#define USART_CR1_DEAT_MASK (31 << USART_CR1_DEAT_SHIFT) -#define USART_CR1_RTOIE (1 << 26) /* Bit 26: Receiver timeout interrupt enable */ -#define USART_CR1_EOBIE (1 << 27) /* Bit 27: End of Block interrupt enable */ - -#define USART_CR1_ALLINTS \ - (USART_CR1_IDLEIE | USART_CR1_RXNEIE | USART_CR1_TCIE | USART_CR1_TXEIE |\ - USART_CR1_PEIE | USART_CR1_CMIE |USART_CR1_RTOIE | USART_CR1_EOBIE) - -/* Control register 2 */ - -#define USART_CR2_ADDM7 (1 << 4) /* Bit 4: :7-/4-bit Address Detection */ -#define USART_CR2_LBDL (1 << 5) /* Bit 5: LIN Break Detection Length */ -#define USART_CR2_LBDIE (1 << 6) /* Bit 6: LIN Break Detection Interrupt Enable */ -#define USART_CR2_LBCL (1 << 8) /* Bit 8: Last Bit Clock pulse */ -#define USART_CR2_CPHA (1 << 9) /* Bit 9: Clock Phase */ -#define USART_CR2_CPOL (1 << 10) /* Bit 10: Clock Polarity */ -#define USART_CR2_CLKEN (1 << 11) /* Bit 11: Clock Enable */ -#define USART_CR2_STOP_SHIFT (12) /* Bits 13-12: STOP bits */ -#define USART_CR2_STOP_MASK (3 << USART_CR2_STOP_SHIFT) -# define USART_CR2_STOP1 (0 << USART_CR2_STOP_SHIFT) /* 00: 1 Stop bit */ -# define USART_CR2_STOP2 (2 << USART_CR2_STOP_SHIFT) /* 10: 2 Stop bits */ -# define USART_CR2_STOP1p5 (3 << USART_CR2_STOP_SHIFT) /* 11: 1.5 Stop bit */ - -#define USART_CR2_LINEN (1 << 14) /* Bit 14: LIN mode enable */ -#define USART_CR2_RXINV (1 << 16) /* Bit 16: RX pin active level inversion */ -#define USART_CR2_TXINV (1 << 17) /* Bit 17: TX pin active level inversion */ -#define USART_CR2_DATAINV (1 << 18) /* Bit 18: Binary data inversion */ -#define USART_CR2_MSBFIRST (1 << 19) /* Bit 19: Most significant bit first */ -#define USART_CR2_ABREN (1 << 20) /* Bit 20: Auto baud rate enable */ -#define USART_CR2_ABRMOD_SHIFT (21) /* Bits 21-22: Auto baud rate mode */ -#define USART_CR2_ABRMOD_MASK (3 << USART_CR2_ABRMOD_SHIFT) -# define USART_CR2_ABRMOD_START (0 << USART_CR2_ABRMOD_SHIFT) /* Start bit */ -# define USART_CR2_ABRMOD_FALL (1 << USART_CR2_ABRMOD_SHIFT) /* Falling edge measurement */ -# define USART_CR2_ABRMOD_7F (2 << USART_CR2_ABRMOD_SHIFT) /* 0x7F frame detection */ -# define USART_CR2_ABRMOD_55 (3 << USART_CR2_ABRMOD_SHIFT) /* 0x55 frame detection */ - -#define USART_CR2_RTOEN (1 << 23) /* Bit 23: Receiver timeout enable */ -#define USART_CR2_ADD4L_SHIFT (24) /* Bits 24-17: Address[3:0]:of the USART node */ -#define USART_CR2_ADD4L_MASK (15 << USART_CR2_ADD4_SHIFT) -#define USART_CR2_ADD4H_SHIFT (28) /* Bits 28-31: Address[4:0] of the USART node */ -#define USART_CR2_ADD4H_MASK (15 << USART_CR2_ADD4_SHIFT) -#define USART_CR2_ADD8_SHIFT (24) /* Bits 24-31: Address[7:0] of the USART node */ -#define USART_CR2_ADD8_MASK (255 << USART_CR2_ADD8_SHIFT) - -/* Control register 3 */ - -#define USART_CR3_EIE (1 << 0) /* Bit 0: Error Interrupt Enable */ -#define USART_CR3_IREN (1 << 1) /* Bit 1: IrDA mode Enable */ -#define USART_CR3_IRLP (1 << 2) /* Bit 2: IrDA Low-Power */ -#define USART_CR3_HDSEL (1 << 3) /* Bit 3: Half-Duplex Selection */ -#define USART_CR3_NACK (1 << 4) /* Bit 4: Smartcard NACK enable */ -#define USART_CR3_SCEN (1 << 5) /* Bit 5: Smartcard mode enable */ -#define USART_CR3_DMAR (1 << 6) /* Bit 6: DMA Enable Receiver */ -#define USART_CR3_DMAT (1 << 7) /* Bit 7: DMA Enable Transmitter */ -#define USART_CR3_RTSE (1 << 8) /* Bit 8: RTS Enable */ -#define USART_CR3_CTSE (1 << 9) /* Bit 9: CTS Enable */ -#define USART_CR3_CTSIE (1 << 10) /* Bit 10: CTS Interrupt Enable */ -#define USART_CR3_ONEBIT (1 << 11) /* Bit 11: One sample bit method enable */ -#define USART_CR3_OVRDIS (1 << 12) /* Bit 12: Overrun Disable */ -#define USART_CR3_DDRE (1 << 13) /* Bit 13: DMA Disable on Reception Error */ -#define USART_CR3_DEM (1 << 14) /* Bit 14: Driver enable mode */ -#define USART_CR3_DEP (1 << 15) /* Bit 15: Driver enable polarity selection */ -#define USART_CR3_SCARCNT_SHIFT (17) /* Bit 17-19: Smartcard auto-retry count */ -#define USART_CR3_SCARCNT_MASK (7 << USART_CR3_SCARCNT_SHIFT) -#define USART_CR3_WUS_SHIFT (20) /* Bit 20-21: Wakeup from Stop mode interrupt */ -#define USART_CR3_WUS_MASK (3 << USART_CR3_WUS_SHIFT) -# define USART_CR3_WUS_ADDRMAT (0 << USART_CR3_WUS_SHIFT) /* Active on address match */ -# define USART_CR3_WUS_STARTBIT (2 << USART_CR3_WUS_SHIFT) /* Active on Start bit */ -# define USART_CR3_WUS_RXNE (3 << USART_CR3_WUS_SHIFT) /* Active on RXNE */ - -#define USART_CR3_WUFIE (1 << 22) /* Bit 22: Wakeup from Stop mode interrupt enable */ - -/* Baud Rate Register */ - -#define USART_BRR_SHIFT (0) /* Bits 0-15: USARTDIV[15:0] OVER8=0*/ -#define USART_BRR_MASK (0xffff << USART_BRR_SHIFT) -#define USART_BRR_0_3_SHIFT (0) /* Bits 0-2: USARTDIV[3:0] OVER8=1 */ -#define USART_BRR_0_3_MASK (0x0fff << USART_BRR_0_3_SHIFT) -#define USART_BRR_4_7_SHIFT (0) /* Bits 4-15: USARTDIV[15:4] OVER8=1*/ -#define USART_BRR_4_7_MASK (0xffff << USART_BRR_4_7_SHIFT) - -/* Guard time and prescaler register */ - -#define USART_GTPR_PSC_SHIFT (0) /* Bits 0-7: Prescaler value */ -#define USART_GTPR_PSC_MASK (0xff << USART_GTPR_PSC_SHIFT) -#define USART_GTPR_GT_SHIFT (8) /* Bits 8-15: Guard time value */ -#define USART_GTPR_GT_MASK (0xff << USART_GTPR_GT_SHIFT) - -/* Receiver timeout register */ - -#define USART_RTOR_RTO_SHIFT (0) /* Bits 0-23: Receiver timeout value */ -#define USART_RTOR_RTO_MASK (0xffffff << USART_RTOR_RTO_SHIFT) -#define USART_RTOR_BLEN_SHIFT (24) /* Bits 24-31: Block Length */ -#define USART_RTOR_BLEN_MASK (0xff << USART_RTOR_BLEN_SHIFT) - -/* Request register */ - -#define USART_RQR_ABRRQ (1 << 0) /* Bit 0: Auto baud rate request */ -#define USART_RQR_SBKRQ (1 << 1) /* Bit 1: Send break request */ -#define USART_RQR_MMRQ (1 << 2) /* Bit 2: Mute mode request */ -#define USART_RQR_RXFRQ (1 << 3) /* Bit 3: Receive data flush request */ -#define USART_RQR_TXFRQ (1 << 4) /* Bit 4: Transmit data flush request */ - -/* Interrupt & status register */ - -#define USART_ISR_PE (1 << 0) /* Bit 0: Parity error */ -#define USART_ISR_FE (1 << 1) /* Bit 1: Framing error */ -#define USART_ISR_NF (1 << 2) /* Bit 2: Noise detected flag */ -#define USART_ISR_ORE (1 << 3) /* Bit 3: Overrun error */ -#define USART_ISR_IDLE (1 << 4) /* Bit 4: Idle line detected */ -#define USART_ISR_RXNE (1 << 5) /* Bit 5: Read data register not empty */ -#define USART_ISR_TC (1 << 6) /* Bit 6: Transmission complete */ -#define USART_ISR_TXE (1 << 7) /* Bit 7: Transmit data register empty */ -#define USART_ISR_LBDF (1 << 8) /* Bit 8: LIN break detection flag */ -#define USART_ISR_CTSIF (1 << 9) /* Bit 9: CTS interrupt flag */ -#define USART_ISR_CTS (1 << 10) /* Bit 10: CTS flag */ -#define USART_ISR_RTOF (1 << 11) /* Bit 11: Receiver timeout */ -#define USART_ISR_EOBF (1 << 12) /* Bit 12: End of block flag */ -#define USART_ISR_ABRE (1 << 14) /* Bit 14: Auto baud rate error */ -#define USART_ISR_ABRF (1 << 15) /* Bit 15: Auto baud rate flag */ -#define USART_ISR_BUSY (1 << 16) /* Bit 16: Busy flag */ -#define USART_ISR_CMF (1 << 17) /* Bit 17: Character match flag */ -#define USART_ISR_SBKF (1 << 18) /* Bit 18: Send break flag */ -#define USART_ISR_ISRRWU (1 << 19) /* Bit 19: Receiver wakeup from Mute mode */ -#define USART_ISR_WUF (1 << 20) /* Bit 20: Wakeup from Stop mode flag */ -#define USART_ISR_TEACK (1 << 21) /* Bit 21: Transmit enable acknowledge flag */ -#define USART_ISR_REACK (1 << 22) /* Bit 22: Receive enable acknowledge flag */ - -#define USART_ISR_ALLBITS (0x007fdfff) - -/* Interrupt flag clear register */ - -#define USART_ICR_PECF (1 << 0) /* Bit 0: Parity error clear flag */ -#define USART_ICR_FECF (1 << 1) /* Bit 1: Framing error clear flag */ -#define USART_ICR_NCF (1 << 2) /* Bit 2: Noise detected flag *clear flag */ -#define USART_ICR_ORECF (1 << 3) /* Bit 3: Overrun error clear flag */ -#define USART_ICR_IDLECF (1 << 4) /* Bit 4: Idle line detected clear flag */ -#define USART_ICR_TCCF (1 << 6) /* Bit 6: Transmission complete */ -#define USART_ICR_LBDCF (1 << 8) /* Bit 8: LIN break detection clear flag */ -#define USART_ICR_CTSCF (1 << 9) /* Bit 9: CTS interrupt clear flag */ -#define USART_ICR_RTOCF (1 << 11) /* Bit 11: Receiver timeout clear flag */ -#define USART_ICR_EOBCF (1 << 12) /* Bit 12: End of block clear flag */ -#define USART_ICR_CMCF (1 << 17) /* Bit 17: Character match clear flag */ -#define USART_ICR_WUCF (1 << 20) /* Bit 20: Wakeup from Stop mode clear flag */ - -#define USART_ICR_ALLBITS (0x00121b5f) - -/* Receive data register */ - -#define USART_RDR_SHIFT (0) /* Bits 8:0: Receive data value */ -#define USART_RDR_MASK (0x1ff << USART_RDR_SHIFT) - -/* Transmit data register */ - -#define USART_TDR_SHIFT (0) /* Bits 8:0: Transmit data value */ -#define USART_TDR_MASK (0x1ff << USART_TDR_SHIFT) - -/* Compatibility definitions ************************************************/ - -/* F1/F2/F4 Status register */ - -#define STM32_USART_SR_OFFSET STM32_USART_ISR_OFFSET - -#define USART_SR_PE USART_ISR_PE /* Parity Error */ -#define USART_SR_FE USART_ISR_FE /* Framing error */ -#define USART_SR_NE USART_ISR_NF /* Noise detected flag */ -#define USART_SR_ORE USART_ISR_ORE /* Overrun error */ -#define USART_SR_IDLE USART_ISR_IDLE /* IDLE line detected */ -#define USART_SR_RXNE USART_ISR_RXNE /* Read Data Register Not Empty */ -#define USART_SR_TC USART_ISR_TC /* Transmission Complete */ -#define USART_SR_TXE USART_ISR_TXE /* Transmit Data Register Empty */ -#define USART_SR_LBD USART_ISR_LBDF /* LIN Break Detection Flag */ -#define USART_SR_CTS USART_ISR_CTS /* Bit 9: CTS Flag */ - -#define USART_SR_ALLBITS USART_ISR_ALLBITS - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/**************************************************************************** - * Public Functions Prototypes - ****************************************************************************/ - -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32F30XXX_UART_H */ diff --git a/arch/arm/src/stm32/hardware/stm32f40xxx_uart.h b/arch/arm/src/stm32/hardware/stm32f40xxx_uart.h deleted file mode 100644 index edfb2a0cc7159..0000000000000 --- a/arch/arm/src/stm32/hardware/stm32f40xxx_uart.h +++ /dev/null @@ -1,236 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/hardware/stm32f40xxx_uart.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32F40XXX_UART_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32F40XXX_UART_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "chip.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Register Offsets *********************************************************/ - -#define STM32_USART_SR_OFFSET 0x0000 /* Status register (32-bits) */ -#define STM32_USART_DR_OFFSET 0x0004 /* Data register (32-bits) */ -#define STM32_USART_BRR_OFFSET 0x0008 /* Baud Rate Register (32-bits) */ -#define STM32_USART_CR1_OFFSET 0x000c /* Control register 1 (32-bits) */ -#define STM32_USART_CR2_OFFSET 0x0010 /* Control register 2 (32-bits) */ -#define STM32_USART_CR3_OFFSET 0x0014 /* Control register 3 (32-bits) */ -#define STM32_USART_GTPR_OFFSET 0x0018 /* Guard time and prescaler register (32-bits) */ - -/* Register Addresses *******************************************************/ - -#if STM32_NUSART > 0 -# define STM32_USART1_SR (STM32_USART1_BASE+STM32_USART_SR_OFFSET) -# define STM32_USART1_DR (STM32_USART1_BASE+STM32_USART_DR_OFFSET) -# define STM32_USART1_BRR (STM32_USART1_BASE+STM32_USART_BRR_OFFSET) -# define STM32_USART1_CR1 (STM32_USART1_BASE+STM32_USART_CR1_OFFSET) -# define STM32_USART1_CR2 (STM32_USART1_BASE+STM32_USART_CR2_OFFSET) -# define STM32_USART1_CR3 (STM32_USART1_BASE+STM32_USART_CR3_OFFSET) -# define STM32_USART1_GTPR (STM32_USART1_BASE+STM32_USART_GTPR_OFFSET) -#endif - -#if STM32_NUSART > 1 -# define STM32_USART2_SR (STM32_USART2_BASE+STM32_USART_SR_OFFSET) -# define STM32_USART2_DR (STM32_USART2_BASE+STM32_USART_DR_OFFSET) -# define STM32_USART2_BRR (STM32_USART2_BASE+STM32_USART_BRR_OFFSET) -# define STM32_USART2_CR1 (STM32_USART2_BASE+STM32_USART_CR1_OFFSET) -# define STM32_USART2_CR2 (STM32_USART2_BASE+STM32_USART_CR2_OFFSET) -# define STM32_USART2_CR3 (STM32_USART2_BASE+STM32_USART_CR3_OFFSET) -# define STM32_USART2_GTPR (STM32_USART2_BASE+STM32_USART_GTPR_OFFSET) -#endif - -#if STM32_NUSART > 2 -# define STM32_USART3_SR (STM32_USART3_BASE+STM32_USART_SR_OFFSET) -# define STM32_USART3_DR (STM32_USART3_BASE+STM32_USART_DR_OFFSET) -# define STM32_USART3_BRR (STM32_USART3_BASE+STM32_USART_BRR_OFFSET) -# define STM32_USART3_CR1 (STM32_USART3_BASE+STM32_USART_CR1_OFFSET) -# define STM32_USART3_CR2 (STM32_USART3_BASE+STM32_USART_CR2_OFFSET) -# define STM32_USART3_CR3 (STM32_USART3_BASE+STM32_USART_CR3_OFFSET) -# define STM32_USART3_GTPR (STM32_USART3_BASE+STM32_USART_GTPR_OFFSET) -#endif - -#if STM32_NUSART > 3 -# define STM32_UART4_SR (STM32_UART4_BASE+STM32_USART_SR_OFFSET) -# define STM32_UART4_DR (STM32_UART4_BASE+STM32_USART_DR_OFFSET) -# define STM32_UART4_BRR (STM32_UART4_BASE+STM32_USART_BRR_OFFSET) -# define STM32_UART4_CR1 (STM32_UART4_BASE+STM32_USART_CR1_OFFSET) -# define STM32_UART4_CR2 (STM32_UART4_BASE+STM32_USART_CR2_OFFSET) -# define STM32_UART4_CR3 (STM32_UART4_BASE+STM32_USART_CR3_OFFSET) -#endif - -#if STM32_NUSART > 4 -# define STM32_UART5_SR (STM32_UART5_BASE+STM32_USART_SR_OFFSET) -# define STM32_UART5_DR (STM32_UART5_BASE+STM32_USART_DR_OFFSET) -# define STM32_UART5_BRR (STM32_UART5_BASE+STM32_USART_BRR_OFFSET) -# define STM32_UART5_CR1 (STM32_UART5_BASE+STM32_USART_CR1_OFFSET) -# define STM32_UART5_CR2 (STM32_UART5_BASE+STM32_USART_CR2_OFFSET) -# define STM32_UART5_CR3 (STM32_UART5_BASE+STM32_USART_CR3_OFFSET) -#endif - -#if STM32_NUSART > 5 -# define STM32_USART6_SR (STM32_USART6_BASE+STM32_USART_SR_OFFSET) -# define STM32_USART6_DR (STM32_USART6_BASE+STM32_USART_DR_OFFSET) -# define STM32_USART6_BRR (STM32_USART6_BASE+STM32_USART_BRR_OFFSET) -# define STM32_USART6_CR1 (STM32_USART6_BASE+STM32_USART_CR1_OFFSET) -# define STM32_USART6_CR2 (STM32_USART6_BASE+STM32_USART_CR2_OFFSET) -# define STM32_USART6_CR3 (STM32_USART6_BASE+STM32_USART_CR3_OFFSET) -# define STM32_USART6_GTPR (STM32_USART6_BASE+STM32_USART_GTPR_OFFSET) -#endif - -#if STM32_NUSART > 6 -# define STM32_UART7_SR (STM32_UART7_BASE+STM32_USART_SR_OFFSET) -# define STM32_UART7_DR (STM32_UART7_BASE+STM32_USART_DR_OFFSET) -# define STM32_UART7_BRR (STM32_UART7_BASE+STM32_USART_BRR_OFFSET) -# define STM32_UART7_CR1 (STM32_UART7_BASE+STM32_USART_CR1_OFFSET) -# define STM32_UART7_CR2 (STM32_UART7_BASE+STM32_USART_CR2_OFFSET) -# define STM32_UART7_CR3 (STM32_UART7_BASE+STM32_USART_CR3_OFFSET) -#endif - -#if STM32_NUSART > 7 -# define STM32_UART8_SR (STM32_UART8_BASE+STM32_USART_SR_OFFSET) -# define STM32_UART8_DR (STM32_UART8_BASE+STM32_USART_DR_OFFSET) -# define STM32_UART8_BRR (STM32_UART8_BASE+STM32_USART_BRR_OFFSET) -# define STM32_UART8_CR1 (STM32_UART8_BASE+STM32_USART_CR1_OFFSET) -# define STM32_UART8_CR2 (STM32_UART8_BASE+STM32_USART_CR2_OFFSET) -# define STM32_UART8_CR3 (STM32_UART8_BASE+STM32_USART_CR3_OFFSET) -#endif - -/* Register Bitfield Definitions ********************************************/ - -/* Status register */ - -#define USART_SR_PE (1 << 0) /* Bit 0: Parity Error */ -#define USART_SR_FE (1 << 1) /* Bit 1: Framing Error */ -#define USART_SR_NE (1 << 2) /* Bit 2: Noise Error Flag */ -#define USART_SR_ORE (1 << 3) /* Bit 3: OverRun Error */ -#define USART_SR_IDLE (1 << 4) /* Bit 4: IDLE line detected */ -#define USART_SR_RXNE (1 << 5) /* Bit 5: Read Data Register Not Empty */ -#define USART_SR_TC (1 << 6) /* Bit 6: Transmission Complete */ -#define USART_SR_TXE (1 << 7) /* Bit 7: Transmit Data Register Empty */ -#define USART_SR_LBD (1 << 8) /* Bit 8: LIN Break Detection Flag */ -#define USART_SR_CTS (1 << 9) /* Bit 9: CTS Flag */ - -#define USART_SR_ALLBITS (0x03ff) -#define USART_SR_CLRBITS (USART_SR_CTS|USART_SR_LBD) /* Cleared by SW write to SR */ - -/* Data register */ - -#define USART_DR_SHIFT (0) /* Bits 8:0: Data value */ -#define USART_DR_MASK (0xff << USART_DR_SHIFT) - -/* Baud Rate Register */ - -#define USART_BRR_FRAC_SHIFT (0) /* Bits 3-0: fraction of USARTDIV */ -#define USART_BRR_FRAC_MASK (0x0f << USART_BRR_FRAC_SHIFT) -#define USART_BRR_MANT_SHIFT (4) /* Bits 15-4: mantissa of USARTDIV */ -#define USART_BRR_MANT_MASK (0x0fff << USART_BRR_MANT_SHIFT) - -/* Control register 1 */ - -#define USART_CR1_SBK (1 << 0) /* Bit 0: Send Break */ -#define USART_CR1_RWU (1 << 1) /* Bit 1: Receiver wakeup */ -#define USART_CR1_RE (1 << 2) /* Bit 2: Receiver Enable */ -#define USART_CR1_TE (1 << 3) /* Bit 3: Transmitter Enable */ -#define USART_CR1_IDLEIE (1 << 4) /* Bit 4: IDLE Interrupt Enable */ -#define USART_CR1_RXNEIE (1 << 5) /* Bit 5: RXNE Interrupt Enable */ -#define USART_CR1_TCIE (1 << 6) /* Bit 6: Transmission Complete Interrupt Enable */ -#define USART_CR1_TXEIE (1 << 7) /* Bit 7: TXE Interrupt Enable */ -#define USART_CR1_PEIE (1 << 8) /* Bit 8: PE Interrupt Enable */ -#define USART_CR1_PS (1 << 9) /* Bit 9: Parity Selection */ -#define USART_CR1_PCE (1 << 10) /* Bit 10: Parity Control Enable */ -#define USART_CR1_WAKE (1 << 11) /* Bit 11: Wakeup method */ -#define USART_CR1_M (1 << 12) /* Bit 12: word length */ -#define USART_CR1_UE (1 << 13) /* Bit 13: USART Enable */ -#define USART_CR1_OVER8 (1 << 15) /* Bit 15: Oversampling mode */ - -#define USART_CR1_ALLINTS (USART_CR1_IDLEIE|USART_CR1_RXNEIE|USART_CR1_TCIE|USART_CR1_PEIE) - -/* Control register 2 */ - -#define USART_CR2_ADD_SHIFT (0) /* Bits 3-0: Address of the USART node */ -#define USART_CR2_ADD_MASK (0x0f << USART_CR2_ADD_SHIFT) -#define USART_CR2_LBDL (1 << 5) /* Bit 5: LIN Break Detection Length */ -#define USART_CR2_LBDIE (1 << 6) /* Bit 6: LIN Break Detection Interrupt Enable */ -#define USART_CR2_LBCL (1 << 8) /* Bit 8: Last Bit Clock pulse */ -#define USART_CR2_CPHA (1 << 9) /* Bit 9: Clock Phase */ -#define USART_CR2_CPOL (1 << 10) /* Bit 10: Clock Polarity */ -#define USART_CR2_CLKEN (1 << 11) /* Bit 11: Clock Enable */ -#define USART_CR2_STOP_SHIFT (12) /* Bits 13-12: STOP bits */ -#define USART_CR2_STOP_MASK (3 << USART_CR2_STOP_SHIFT) -# define USART_CR2_STOP1 (0 << USART_CR2_STOP_SHIFT) /* 00: 1 Stop bit */ -# define USART_CR2_STOP0p5 (1 << USART_CR2_STOP_SHIFT) /* 01: 0.5 Stop bit */ -# define USART_CR2_STOP2 (2 << USART_CR2_STOP_SHIFT) /* 10: 2 Stop bits */ -# define USART_CR2_STOP1p5 (3 << USART_CR2_STOP_SHIFT) /* 11: 1.5 Stop bit */ - -#define USART_CR2_LINEN (1 << 14) /* Bit 14: LIN mode enable */ - -/* Control register 3 */ - -#define USART_CR3_EIE (1 << 0) /* Bit 0: Error Interrupt Enable */ -#define USART_CR3_IREN (1 << 1) /* Bit 1: IrDA mode Enable */ -#define USART_CR3_IRLP (1 << 2) /* Bit 2: IrDA Low-Power */ -#define USART_CR3_HDSEL (1 << 3) /* Bit 3: Half-Duplex Selection */ -#define USART_CR3_NACK (1 << 4) /* Bit 4: Smartcard NACK enable */ -#define USART_CR3_SCEN (1 << 5) /* Bit 5: Smartcard mode enable */ -#define USART_CR3_DMAR (1 << 6) /* Bit 6: DMA Enable Receiver */ -#define USART_CR3_DMAT (1 << 7) /* Bit 7: DMA Enable Transmitter */ -#define USART_CR3_RTSE (1 << 8) /* Bit 8: RTS Enable */ -#define USART_CR3_CTSE (1 << 9) /* Bit 9: CTS Enable */ -#define USART_CR3_CTSIE (1 << 10) /* Bit 10: CTS Interrupt Enable */ -#define USART_CR3_ONEBIT (1 << 11) /* Bit 11: One sample bit method enable */ - -/* Guard time and prescaler register */ - -#define USART_GTPR_PSC_SHIFT (0) /* Bits 0-7: Prescaler value */ -#define USART_GTPR_PSC_MASK (0xff << USART_GTPR_PSC_SHIFT) -#define USART_GTPR_GT_SHIFT (8) /* Bits 8-15: Guard time value */ -#define USART_GTPR_GT_MASK (0xff << USART_GTPR_GT_SHIFT) - -/* Compatibility definitions ************************************************/ - -/* F3 Transmit/Read registers */ - -#define STM32_USART_RDR_OFFSET STM32_USART_DR_OFFSET /* Receive data register */ -#define STM32_USART_TDR_OFFSET STM32_USART_DR_OFFSET /* Transmit data register */ - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/**************************************************************************** - * Public Functions Prototypes - ****************************************************************************/ - -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32F40XXX_UART_H */ diff --git a/arch/arm/src/stm32/hardware/stm32g4xxxx_uart.h b/arch/arm/src/stm32/hardware/stm32g4xxxx_uart.h deleted file mode 100644 index 98990ba21e39e..0000000000000 --- a/arch/arm/src/stm32/hardware/stm32g4xxxx_uart.h +++ /dev/null @@ -1,439 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/hardware/stm32g4xxxx_uart.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32G4XXXX_UART_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32G4XXXX_UART_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "chip.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Register Offsets *********************************************************/ - -#define STM32_USART_CR1_OFFSET 0x0000 /* Control Register 1 */ -#define STM32_USART_CR2_OFFSET 0x0004 /* Control Register 2 */ -#define STM32_USART_CR3_OFFSET 0x0008 /* Control Register 3 */ -#define STM32_USART_BRR_OFFSET 0x000c /* BAUD Rate Register */ -#define STM32_USART_GTPR_OFFSET 0x0010 /* Guard Time and Prescaler Register */ -#define STM32_USART_RTOR_OFFSET 0x0014 /* Receiver Timeout Register */ -#define STM32_USART_RQR_OFFSET 0x0018 /* Request Register */ -#define STM32_USART_ISR_OFFSET 0x001c /* Interrupt and Status Register */ -#define STM32_USART_ICR_OFFSET 0x0020 /* Interrupt Flag Clear Register */ -#define STM32_USART_RDR_OFFSET 0x0024 /* Receive Data Register */ -#define STM32_USART_TDR_OFFSET 0x0028 /* Transmit Data Register */ -#define STM32_USART_PRESC_OFFSET 0x002c /* Prescaler Register */ - -/* Register Addresses *******************************************************/ -#if (STM32_NLPUART > 0) -# define STM32_LPUART1_CR1 (STM32_LPUART1_BASE + STM32_USART_CR1_OFFSET) -# define STM32_LPUART1_CR2 (STM32_LPUART1_BASE + STM32_USART_CR2_OFFSET) -# define STM32_LPUART1_CR3 (STM32_LPUART1_BASE + STM32_USART_CR3_OFFSET) -# define STM32_LPUART1_BRR (STM32_LPUART1_BASE + STM32_USART_BRR_OFFSET) -# define STM32_LPUART1_RQR (STM32_LPUART1_BASE + STM32_USART_RQR_OFFSET) -# define STM32_LPUART1_ISR (STM32_LPUART1_BASE + STM32_USART_ISR_OFFSET) -# define STM32_LPUART1_ICR (STM32_LPUART1_BASE + STM32_USART_ICR_OFFSET) -# define STM32_LPUART1_RDR (STM32_LPUART1_BASE + STM32_USART_RDR_OFFSET) -# define STM32_LPUART1_TDR (STM32_LPUART1_BASE + STM32_USART_TDR_OFFSET) -# define STM32_LPUART1_PRESC (STM32_LPUART1_BASE + STM32_USART_PRESC_OFFSET) -#endif - -#if (STM32_NUSART > 0) -# define STM32_USART1_CR1 (STM32_USART1_BASE + STM32_USART_CR1_OFFSET) -# define STM32_USART1_CR2 (STM32_USART1_BASE + STM32_USART_CR2_OFFSET) -# define STM32_USART1_CR3 (STM32_USART1_BASE + STM32_USART_CR3_OFFSET) -# define STM32_USART1_BRR (STM32_USART1_BASE + STM32_USART_BRR_OFFSET) -# define STM32_USART1_GTPR (STM32_USART1_BASE + STM32_USART_GTPR_OFFSET) -# define STM32_USART1_RTOR (STM32_USART1_BASE + STM32_USART_RTOR_OFFSET) -# define STM32_USART1_RQR (STM32_USART1_BASE + STM32_USART_RQR_OFFSET) -# define STM32_USART1_ISR (STM32_USART1_BASE + STM32_USART_ISR_OFFSET) -# define STM32_USART1_ICR (STM32_USART1_BASE + STM32_USART_ICR_OFFSET) -# define STM32_USART1_RDR (STM32_USART1_BASE + STM32_USART_RDR_OFFSET) -# define STM32_USART1_TDR (STM32_USART1_BASE + STM32_USART_TDR_OFFSET) -# define STM32_USART1_PRESC (STM32_USART1_BASE + STM32_USART_PRESC_OFFSET) -#endif - -#if (STM32_NUSART > 1) -# define STM32_USART2_CR1 (STM32_USART2_BASE + STM32_USART_CR1_OFFSET) -# define STM32_USART2_CR2 (STM32_USART2_BASE + STM32_USART_CR2_OFFSET) -# define STM32_USART2_CR3 (STM32_USART2_BASE + STM32_USART_CR3_OFFSET) -# define STM32_USART2_BRR (STM32_USART2_BASE + STM32_USART_BRR_OFFSET) -# define STM32_USART2_GTPR (STM32_USART2_BASE + STM32_USART_GTPR_OFFSET) -# define STM32_USART2_RTOR (STM32_USART2_BASE + STM32_USART_RTOR_OFFSET) -# define STM32_USART2_RQR (STM32_USART2_BASE + STM32_USART_RQR_OFFSET) -# define STM32_USART2_ISR (STM32_USART2_BASE + STM32_USART_ISR_OFFSET) -# define STM32_USART2_ICR (STM32_USART2_BASE + STM32_USART_ICR_OFFSET) -# define STM32_USART2_RDR (STM32_USART2_BASE + STM32_USART_RDR_OFFSET) -# define STM32_USART2_TDR (STM32_USART2_BASE + STM32_USART_TDR_OFFSET) -# define STM32_USART2_PRESC (STM32_USART2_BASE + STM32_USART_PRESC_OFFSET) -#endif - -#if (STM32_NUSART > 2) -# define STM32_USART3_CR1 (STM32_USART3_BASE + STM32_USART_CR1_OFFSET) -# define STM32_USART3_CR2 (STM32_USART3_BASE + STM32_USART_CR2_OFFSET) -# define STM32_USART3_CR3 (STM32_USART3_BASE + STM32_USART_CR3_OFFSET) -# define STM32_USART3_BRR (STM32_USART3_BASE + STM32_USART_BRR_OFFSET) -# define STM32_USART3_GTPR (STM32_USART3_BASE + STM32_USART_GTPR_OFFSET) -# define STM32_USART3_RTOR (STM32_USART3_BASE + STM32_USART_RTOR_OFFSET) -# define STM32_USART3_RQR (STM32_USART3_BASE + STM32_USART_RQR_OFFSET) -# define STM32_USART3_ISR (STM32_USART3_BASE + STM32_USART_ISR_OFFSET) -# define STM32_USART3_ICR (STM32_USART3_BASE + STM32_USART_ICR_OFFSET) -# define STM32_USART3_RDR (STM32_USART3_BASE + STM32_USART_RDR_OFFSET) -# define STM32_USART3_TDR (STM32_USART3_BASE + STM32_USART_TDR_OFFSET) -# define STM32_USART3_PRESC (STM32_USART3_BASE + STM32_USART_PRESC_OFFSET) -#endif - -#if (STM32_NUSART > 3) -# define STM32_UART4_CR1 (STM32_UART4_BASE + STM32_USART_CR1_OFFSET) -# define STM32_UART4_CR2 (STM32_UART4_BASE + STM32_USART_CR2_OFFSET) -# define STM32_UART4_CR3 (STM32_UART4_BASE + STM32_USART_CR3_OFFSET) -# define STM32_UART4_BRR (STM32_UART4_BASE + STM32_USART_BRR_OFFSET) -# define STM32_UART4_GTPR (STM32_UART4_BASE + STM32_USART_GTPR_OFFSET) -# define STM32_UART4_RTOR (STM32_UART4_BASE + STM32_USART_RTOR_OFFSET) -# define STM32_UART4_RQR (STM32_UART4_BASE + STM32_USART_RQR_OFFSET) -# define STM32_UART4_ISR (STM32_UART4_BASE + STM32_USART_ISR_OFFSET) -# define STM32_UART4_ICR (STM32_UART4_BASE + STM32_USART_ICR_OFFSET) -# define STM32_UART4_RDR (STM32_UART4_BASE + STM32_USART_RDR_OFFSET) -# define STM32_UART4_TDR (STM32_UART4_BASE + STM32_USART_TDR_OFFSET) -# define STM32_UART4_PRESC (STM32_UART4_BASE + STM32_USART_PRESC_OFFSET) -#endif - -#if (STM32_NUSART > 4) -# define STM32_UART5_CR1 (STM32_UART5_BASE + STM32_USART_CR1_OFFSET) -# define STM32_UART5_CR2 (STM32_UART5_BASE + STM32_USART_CR2_OFFSET) -# define STM32_UART5_CR3 (STM32_UART5_BASE + STM32_USART_CR3_OFFSET) -# define STM32_UART5_BRR (STM32_UART5_BASE + STM32_USART_BRR_OFFSET) -# define STM32_UART5_GTPR (STM32_UART5_BASE + STM32_USART_GTPR_OFFSET) -# define STM32_UART5_RTOR (STM32_UART5_BASE + STM32_USART_RTOR_OFFSET) -# define STM32_UART5_RQR (STM32_UART5_BASE + STM32_USART_RQR_OFFSET) -# define STM32_UART5_ISR (STM32_UART5_BASE + STM32_USART_ISR_OFFSET) -# define STM32_UART5_ICR (STM32_UART5_BASE + STM32_USART_ICR_OFFSET) -# define STM32_UART5_RDR (STM32_UART5_BASE + STM32_USART_RDR_OFFSET) -# define STM32_UART5_TDR (STM32_UART5_BASE + STM32_USART_TDR_OFFSET) -# define STM32_UART5_PRESC (STM32_UART5_BASE + STM32_USART_PRESC_OFFSET) -#endif - -/* Register Bitfield Definitions ********************************************/ - -/* Control Register 1 */ - -#define USART_CR1_UE (1 << 0) /* Bit 0 - USART Enable */ -#define USART_CR1_UESM (1 << 1) /* Bit 1 - USART Enable in low power Mode */ -#define USART_CR1_RE (1 << 2) /* Bit 2 - Receiver Enable */ -#define USART_CR1_TE (1 << 3) /* Bit 3 - Transmitter Enable */ -#define USART_CR1_IDLEIE (1 << 4) /* Bit 4 - IDLE Interrupt Enable */ -#define USART_CR1_RXFNEIE (1 << 5) /* Bit 5 in FIFO mode - Rx FIFO Not Empty Interrupt Enable */ -#define USART_CR1_RXNEIE (1 << 5) /* Bit 5 in Non-FIFO mode - Rx Data Register Not Empty Interrupt Enable */ -#define USART_CR1_TCIE (1 << 6) /* Bit 6 - Transmission Complete Interrupt Enable */ -#define USART_CR1_TXFNFIE (1 << 7) /* Bit 7 in FIFO mode - Tx FIFO Not Full Interrupt Enable */ -#define USART_CR1_TXEIE (1 << 7) /* Bit 7 in Non-FIFO mode - Tx Data Register Empty Interrupt Enable */ -#define USART_CR1_PEIE (1 << 8) /* Bit 8 - PE Interrupt Enable */ -#define USART_CR1_PS (1 << 9) /* Bit 9 - Parity Selection */ -#define USART_CR1_PCE (1 << 10) /* Bit 10 - Parity Control Enable */ -#define USART_CR1_WAKE (1 << 11) /* Bit 11 - Receiver Wakeup method */ -#define USART_CR1_M0 (1 << 12) /* Bit 12 - Word length - Bit 0 */ -#define USART_CR1_MME (1 << 13) /* Bit 13 - Mute Mode Enable */ -#define USART_CR1_CMIE (1 << 14) /* Bit 14 - Character match interrupt enable */ -#define USART_CR1_OVER8 (1 << 15) /* Bit 15 - Oversampling by 8-bit or 16-bit mode */ -#define USART_CR1_DEDT_SHIFT (16) /* Bits 20:16 - Driver Enable Deassertion Time, in 1/16ths or 1/8ths bit time */ -#define USART_CR1_DEDT_MASK (0x1f << USART_CR1_DEDT_SHIFT) -# define USART_CR1_DEDT(n) (((n) << USART_CR1_DEDT_SHIFT) & USART_CR1_DEDT_MASK) -#define USART_CR1_DEAT_SHIFT (21) /* Bits 25:21 - Driver Enable Assertion Time, in 1/16ths or 1/8ths bit time */ -#define USART_CR1_DEAT_MASK (0x1f << USART_CR1_DEAT_SHIFT) -# define USART_CR1_DEAT(n) (((n) << USART_CR1_DEAT_SHIFT) & USART_CR1_DEAT_MASK) -#define USART_CR1_RTOIE (1 << 26) /* Bit 26 - Receive Time Out interrupt enable */ -#define USART_CR1_EOBIE (1 << 27) /* Bit 27 - End of Block interrupt enable */ -#define USART_CR1_M1 (1 << 28) /* Bit 28 - Word length - Bit 1 */ -#define USART_CR1_FIFOEN (1 << 29) /* Bit 29 - FIFO mode enable */ -#define USART_CR1_TXFEIE (1 << 30) /* Bit 30 - TXFIFO empty interrupt enable */ -#define USART_CR1_RXFFIE (1 << 31) /* Bit 31 - RXFIFO Full interrupt enable */ - -#define USART_CR1_M_MASK (USART_CR1_M0 | USART_CR1_M1) - -#define USART_CR1_ALLINTS \ - (USART_CR1_IDLEIE | USART_CR1_RXNEIE | USART_CR1_TCIE | \ - USART_CR1_TXEIE | USART_CR1_PEIE | USART_CR1_CMIE | USART_CR1_RTOIE | \ - USART_CR1_EOBIE | USART_CR1_TXFEIE | USART_CR1_RXFFIE) - -#define LPUART_CR1_ALLINTS \ - (USART_CR1_IDLEIE | USART_CR1_RXNEIE | USART_CR1_TCIE | \ - USART_CR1_TXEIE | USART_CR1_PEIE | USART_CR1_CMIE | \ - USART_CR1_TXFEIE | USART_CR1_RXFFIE) - -/* Control Register 2 */ - -#define USART_CR2_SLVEN (1 << 0) /* Synchronous Slave Mode Enable */ -#define USART_CR2_DIS_NSS (1 << 3) /* Slave Select (NSS) Pin Ignore For SPI */ -#define USART_CR2_ADDM7 (1 << 4) /* 7-Bit / 4-Bit Address Detection */ -#define USART_CR2_LBDL (1 << 5) /* LIN Break Detection Length */ -#define USART_CR2_LBDIE (1 << 6) /* LIN Break Detection Interrupt Enable */ -#define USART_CR2_LBCL (1 << 8) /* Last Bit Clock pulse */ -#define USART_CR2_CPHA (1 << 9) /* Clock Phase */ -#define USART_CR2_CPOL (1 << 10) /* Clock Polarity */ -#define USART_CR2_CLKEN (1 << 11) /* Clock Enable */ -#define USART_CR2_STOP_SHIFT (12) /* Stop Bit Mode */ -#define USART_CR2_STOP_MASK (0x3 << USART_CR2_STOP_SHIFT) -# define USART_CR2_STOP1 (0x0 << USART_CR2_STOP_SHIFT) /* 1 Stop Bit */ -# define USART_CR2_STOP0p5 (0x1 << USART_CR2_STOP_SHIFT) /* 0.5 Stop Bit */ -# define USART_CR2_STOP2 (0x2 << USART_CR2_STOP_SHIFT) /* 2 Stop Bits */ -# define USART_CR2_STOP1p5 (0x3 << USART_CR2_STOP_SHIFT) /* 1.5 Stop Bits */ -#define USART_CR2_LINEN (1 << 14) /* LIN Mode Enable */ -#define USART_CR2_SWAP (1 << 15) /* Swap TX/RX Pins */ -#define USART_CR2_RXINV (1 << 16) /* RX Pin Active Level Inversion */ -#define USART_CR2_TXINV (1 << 17) /* TX Pin Active Level Inversion */ -#define USART_CR2_DATAINV (1 << 18) /* Binary Data Inversion */ -#define USART_CR2_MSBFIRST (1 << 19) /* MSB First */ -#define USART_CR2_ABREN (1 << 20) /* Auto BAUD-Rate Enable */ -#define USART_CR2_ABRMOD_SHIFT (21) /* Auto BAUD-Rate Detection Mode */ -#define USART_CR2_ABRMOD_MASK (0x3 << USART_CR2_ABRMOD_SHIFT) -# define USART_CR2_ABRMOD_STARTBIT (0x0 << USART_CR2_ABRMOD_SHIFT) /* Measurement of Start Bit */ -# define USART_CR2_ABRMOD_FALLEDGE (0x1 << USART_CR2_ABRMOD_SHIFT) /* Falling Edge To Falling Edge */ -# define USART_CR2_ABRMOD_7F_FRAME (0x2 << USART_CR2_ABRMOD_SHIFT) /* 0X7F Frame Detection */ -# define USART_CR2_ABRMOD_55_FRAME (0x3 << USART_CR2_ABRMOD_SHIFT) /* 0X55 Frame Detection */ -#define USART_CR2_RTOEN (1 << 23) /* Receiver Time-Out Enable */ -#define USART_CR2_ADD8_SHIFT (24) /* Address of the USART Node */ -#define USART_CR2_ADD8_MASK (0xff << USART_CR2_ADD8_SHIFT) - -/* Control Register 3 */ - -#define USART_CR3_EIE (1 << 0) /* Error Interrupt Enable */ -#define USART_CR3_IREN (1 << 1) /* IrDA Mode Enable */ -#define USART_CR3_IRLP (1 << 2) /* IrDA Low-Power */ -#define USART_CR3_HDSEL (1 << 3) /* Half-Duplex Selection */ -#define USART_CR3_NACK (1 << 4) /* SmartCard NACK Enable */ -#define USART_CR3_SCEN (1 << 5) /* SmartCard Mode Enable */ -#define USART_CR3_DMAR (1 << 6) /* DMA Enable Receiver */ -#define USART_CR3_DMAT (1 << 7) /* DMA Enable Transmitter */ -#define USART_CR3_RTSE (1 << 8) /* RTS Enable */ -#define USART_CR3_CTSE (1 << 9) /* CTS Enable */ -#define USART_CR3_CTSIE (1 << 10) /* CTS Interrupt Enable */ -#define USART_CR3_ONEBIT (1 << 11) /* One Sample Bit Method Enable */ -#define USART_CR3_OVRDIS (1 << 12) /* Overrun Disable */ -#define USART_CR3_DDRE (1 << 13) /* DMA Disable on Reception Error */ -#define USART_CR3_DEM (1 << 14) /* Driver Enable Mode */ -#define USART_CR3_DEP (1 << 15) -#define USART_CR3_SCARCNT_SHIFT (17) /* SmartCard Auto-Retry Count */ -#define USART_CR3_SCARCNT_MASK (0x7 << USART_CR3_SCARCNT_SHIFT) -# define USART_CR3_SCARCNT(n) (((n) << USART_CR3_SCARCNT_SHIFT) & USART_CR3_SCARCNT_MASK) -#define USART_CR3_WUS_SHIFT (20) /* Wake Up From Low Power Mode Interrupt Flag Selection) */ -#define USART_CR3_WUS_MASK (0x3 << USART_CR3_WUS_SHIFT) -# define USART_CR3_WUS_ADDR (0x0 << USART_CR3_WUS_SHIFT) /* On Address Match */ -# define USART_CR3_WUS_STARTBIT (0x2 << USART_CR3_WUS_SHIFT) /* On Start Bit Detection */ -# define USART_CR3_WUS_RXFNE (0x3 << USART_CR3_WUS_SHIFT) /* On RXNE/RXFNE */ -#define USART_CR3_WUFIE (1 << 22) /* Wake Up From Low Power Mode Interrupt Enable */ -#define USART_CR3_TXFTIE (1 << 23) /* Transmit FIFO Threshold Interrupt Enable */ -#define USART_CR3_TCBGTIE (1 << 24) /* Transmit Complete Before Guard Time Interrupt Enable */ -#define USART_CR3_RXFTCFG_SHIFT (25) /* Receive FIFO Threshold Configuration */ -#define USART_CR3_RXFTCFG_MASK (0x7 << USART_CR3_RXFTCFG_SHIFT) -# define USART_CR3_RXFTCFG_1_8 (0x0 << USART_CR3_RXFTCFG_SHIFT) /* When Rx FIFO Reaches 1/8Th Depth */ -# define USART_CR3_RXFTCFG_1_4 (0x1 << USART_CR3_RXFTCFG_SHIFT) /* When Rx FIFO Reaches 1/4Th Depth */ -# define USART_CR3_RXFTCFG_1_2 (0x2 << USART_CR3_RXFTCFG_SHIFT) /* When Rx FIFO Reaches 1/2 Depth */ -# define USART_CR3_RXFTCFG_3_4 (0x3 << USART_CR3_RXFTCFG_SHIFT) /* When Rx FIFO Reaches 3/4Ths Depth */ -# define USART_CR3_RXFTCFG_7_8 (0x4 << USART_CR3_RXFTCFG_SHIFT) /* When Rx FIFO Reaches 7/8Ths Depth */ -# define USART_CR3_RXFTCFG_FULL (0x5 << USART_CR3_RXFTCFG_SHIFT) /* When Rx FIFO Is Full */ -#define USART_CR3_RXFTIE (1 << 28) /* Receive FIFO Threshold Interrupt Enable */ -#define USART_CR3_TXFTCFG_SHIFT (29) /* Transmit FIFO Threshold Configuration */ -#define USART_CR3_TXFTCFG_MASK (0x7 << USART_CR3_TXFTCFG_SHIFT) -# define USART_CR3_TXFTCFG_1_8 (0x0 << USART_CR3_TXFTCFG_SHIFT) /* When Tx FIFO Reaches 1/8Th Depth */ -# define USART_CR3_TXFTCFG_1_4 (0x1 << USART_CR3_TXFTCFG_SHIFT) /* When Tx FIFO Reaches 1/4Th Depth */ -# define USART_CR3_TXFTCFG_1_2 (0x2 << USART_CR3_TXFTCFG_SHIFT) /* When Tx FIFO Reaches 1/2 Depth */ -# define USART_CR3_TXFTCFG_3_4 (0x3 << USART_CR3_TXFTCFG_SHIFT) /* When Tx FIFO Reaches 3/4Ths Depth */ -# define USART_CR3_TXFTCFG_7_8 (0x4 << USART_CR3_TXFTCFG_SHIFT) /* When Tx FIFO Reaches 7/8Ths Depth */ -# define USART_CR3_TXFTCFG_FULL (0x5 << USART_CR3_TXFTCFG_SHIFT) /* When Tx FIFO Is Full */ - -/* BAUD Rate Register */ - -/* Full BRR field */ - -#define USART_BRR_SHIFT (0) -#define USART_BRR_MASK (0xffff << USART_BRR_BRR_SHIFT) -# define USART_BRR(n) (((n) << USART_BRR_BRR_SHIFT) & USART_BRR_BRR_MASK) - -/* Partial BRR field BRR[3:0]: - * - * When OVER8 = 0: BRR[3:0] = USARTDIV[3:0] - * - * When OVER8 = 1: BRR[2:0] = (USARTDIV[3:0] >> 1) and - * BRR[3] must be kept cleared. - */ - -#define USART_BRR_0_3_SHIFT (0) -#define USART_BRR_0_3_MASK (0xf << USART_BRR_0_3_SHIFT) -# define USART_BRR_0_3(n) (((n) << USART_BRR_0_3_SHIFT) & USART_BRR_0_3_MASK) - -/* Partial BRR field BRR[15:4]: - * BRR[15:4] = USARTDIV[15:4] - */ - -#define USART_BRR_4_15_SHIFT (4) -#define USART_BRR_4_15_MASK (0xfff << USART_BRR_4_15_SHIFT) -# define USART_BRR_4_15(n) (((n) << USART_BRR_4_15_SHIFT) & USART_BRR_4_15_MASK) - -/* Guard Time and Prescaler Register */ - -#define USART_GTPR_PSC_SHIFT (0) /* Prescaler Value */ -#define USART_GTPR_PSC_MASK (0xff << USART_GTPR_PSC_SHIFT) -# define USART_GTPR_PSC(n) (((n) << USART_GTPR_PSC_SHIFT) & USART_GTPR_PSC_MASK) -#define USART_GTPR_GT_SHIFT (8) /* Guard Time Value */ -#define USART_GTPR_GT_MASK (0xff << USART_GTPR_GT_SHIFT) -# define USART_GTPR_GT(n) (((n) << USART_GTPR_GT_SHIFT) & USART_GTPR_GT_MASK) - -/* Receiver Timeout Register */ - -#define USART_RTOR_RTO_SHIFT (0) /* Receiver Time Out Value */ -#define USART_RTOR_RTO_MASK (0xffffff << USART_RTOR_RTO_SHIFT) -# define USART_RTOR_RTO(n) (((n) << USART_RTOR_RTO_SHIFT) & USART_RTOR_RTO_MASK) -#define USART_RTOR_BLEN_SHIFT (24) /* Block Length */ -#define USART_RTOR_BLEN_MASK (0xff << USART_RTOR_BLEN_SHIFT) -# define USART_RTOR_BLEN(n) (((n) << USART_RTOR_BLEN_SHIFT) & USART_RTOR_BLEN_MASK) - -/* Request Register */ - -#define USART_RQR_ABRRQ (1 << 0) /* Bit 0 - Auto-Baud Rate Request */ -#define USART_RQR_SBKRQ (1 << 1) /* Bit 1 - Send Break Request */ -#define USART_RQR_MMRQ (1 << 2) /* Bit 2 - Mute Mode Request */ -#define USART_RQR_RXFRQ (1 << 3) /* Bit 3 - Receive Data Flush Request */ -#define USART_RQR_TXFRQ (1 << 4) /* Bit 4 - Transmit Data Flush Request */ - -/* Interrupt and Status Register */ - -#define USART_ISR_PE (1 << 0) /* Bit 0 - Parity Error */ -#define USART_ISR_FE (1 << 1) /* Bit 1 - Framing Error */ -#define USART_ISR_NE (1 << 2) /* Bit 2 - Noise Detected Flag */ -#define USART_ISR_ORE (1 << 3) /* Bit 3 - Overrun Error */ -#define USART_ISR_IDLE (1 << 4) /* Bit 4 - Idle Line Detected */ -#define USART_ISR_RXFNE (1 << 5) /* Bit 5 (When FIFO in use) - Rx FIFO Not Empty */ -#define USART_ISR_RXNE (1 << 5) /* Bit 5 (When FIFO not in use) - Rx Data Register Not Empty */ -#define USART_ISR_TC (1 << 6) /* Bit 6 - Transmission Complete */ -#define USART_ISR_TXFNF (1 << 7) /* Bit 7 (When FIFO in use) - Tx FIFO Not Full */ -#define USART_ISR_TXE (1 << 7) /* Bit 7 (When FIFO not in use) - Tx Data Register Empty */ -#define USART_ISR_LBDF (1 << 8) /* Bit 8 - LIN Break Detection Flag */ -#define USART_ISR_CTSIF (1 << 9) /* Bit 9 - CTS Interrupt Flag */ -#define USART_ISR_CTS (1 << 10) /* Bit 10 - CTS Flag */ -#define USART_ISR_RTOF (1 << 11) /* Bit 11 - Receiver Time Out */ -#define USART_ISR_EOBF (1 << 12) /* Bit 12 - End of Block Flag */ -#define USART_ISR_UDR (1 << 13) /* Bit 13 - SPI Slave Underrun Error Flag */ -#define USART_ISR_ABRE (1 << 14) /* Bit 14 - Auto BAUD Rate Error */ -#define USART_ISR_ABRF (1 << 15) /* Bit 15 - Auto BAUD Rate Flag */ -#define USART_ISR_BUSY (1 << 16) /* Bit 16 - Busy Flag */ -#define USART_ISR_CMF (1 << 17) /* Bit 17 - Character Match Flag */ -#define USART_ISR_SBKF (1 << 18) /* Bit 18 - Send Break Flag */ -#define USART_ISR_RWU (1 << 19) /* Bit 19 - Receive Wake Up From Mute Mode Flag */ -#define USART_ISR_WUF (1 << 20) /* Bit 20 - Wake Up From Stop Mode Flag */ -#define USART_ISR_TEACK (1 << 21) /* Bit 21 - Transmit Enable Acknowledge Flag */ -#define USART_ISR_REACK (1 << 22) /* Bit 22 - Receive Enable Acknowledge Flag */ -#define USART_ISR_TXFE (1 << 23) /* Bit 23 (When FIFO in use) - Tx FIFO Empty */ -#define USART_ISR_RXFF (1 << 24) /* Bit 24 (When FIFO in use) - Rx FIFO Full */ -#define USART_ISR_TCBGT (1 << 25) /* Bit 25 - Transmission Complete Before Guard Time Completion */ -#define USART_ISR_RXFT (1 << 26) /* Bit 26 (When FIFO in use) - Rx FIFO Threshold Flag */ -#define USART_ISR_TXFT (1 << 27) /* Bit 27 (When FIFO in use) - Tx FIFO Threshold Flag */ - -#define USART_ISR_ALLBITS (0x0fffffff) - -/* Interrupt Flag Clear Register */ - -#define USART_ICR_PECF (1 << 0) /* Bit 0 - Parity Error Clear Flag */ -#define USART_ICR_FECF (1 << 1) /* Bit 1 - Framing Error Clear Flag */ -#define USART_ICR_NCF (1 << 2) /* Bit 2 - Noise detected Clear Flag */ -#define USART_ICR_ORECF (1 << 3) /* Bit 3 - OverRun Error Clear Flag */ -#define USART_ICR_IDLECF (1 << 4) /* Bit 4 - Idle Line Detected Clear Flag */ -#define USART_ICR_TXFECF (1 << 5) /* Bit 5 - Tx FIFO Empty Clear Flag */ -#define USART_ICR_TCCF (1 << 6) /* Bit 6 - Transmission Complete Clear Flag */ -#define USART_ICR_TCBGTCF (1 << 7) /* Bit 7 - Transmission Complete Before Guard Time Clear Flag */ -#define USART_ICR_LBDCF (1 << 8) /* Bit 8 - LIN Break Detection Clear Flag */ -#define USART_ICR_CTSCF (1 << 9) /* Bit 9 - CTS Interrupt Clear Flag */ -#define USART_ICR_RTOCF (1 << 11) /* Bit 11 - Receiver Timeout Clear Flag */ -#define USART_ICR_EOBCF (1 << 12) /* Bit 12 - End of Block Clear Flag */ -#define USART_ICR_UDRCF (1 << 13) /* Bit 13 - SPI Slave Underrun Clear Flag */ -#define USART_ICR_CMCF (1 << 17) /* Bit 17 - Character Match Clear Flag */ -#define USART_ICR_WUCF (1 << 20) /* Bit 20 - Wake Up From Stop Mode Clear Flag */ - -/* Receive Data Register */ - -#define USART_RDR_SHIFT (0) -#define USART_RDR_MASK (0x1ff << USART_RDR_SHIFT) -# define USART_RDR(n) (((n) << USART_RDR_SHIFT) & USART_RDR_MASK) - -/* Transmit Data Register */ - -#define USART_TDR_SHIFT (0) -#define USART_TDR_MASK (0x1ff << USART_TDR_SHIFT) -# define USART_TDR(n) (((n) << USART_TDR_SHIFT) & USART_TDR_MASK) - -/* Prescaler Register */ - -#define USART_PRESC_PRESCALER_SHIFT (0) -#define USART_PRESC_PRESCALER_MASK (0xf << USART_PRESC_PRESCALER_SHIFT) -#define USART_PRESC_PRESCALER_1 (0x0 << USART_PRESC_PRESCALER_SHIFT) -#define USART_PRESC_PRESCALER_2 (0x1 << USART_PRESC_PRESCALER_SHIFT) -#define USART_PRESC_PRESCALER_4 (0x2 << USART_PRESC_PRESCALER_SHIFT) -#define USART_PRESC_PRESCALER_6 (0x3 << USART_PRESC_PRESCALER_SHIFT) -#define USART_PRESC_PRESCALER_8 (0x4 << USART_PRESC_PRESCALER_SHIFT) -#define USART_PRESC_PRESCALER_10 (0x5 << USART_PRESC_PRESCALER_SHIFT) -#define USART_PRESC_PRESCALER_12 (0x6 << USART_PRESC_PRESCALER_SHIFT) -#define USART_PRESC_PRESCALER_16 (0x7 << USART_PRESC_PRESCALER_SHIFT) -#define USART_PRESC_PRESCALER_32 (0x8 << USART_PRESC_PRESCALER_SHIFT) -#define USART_PRESC_PRESCALER_64 (0x9 << USART_PRESC_PRESCALER_SHIFT) -#define USART_PRESC_PRESCALER_128 (0xa << USART_PRESC_PRESCALER_SHIFT) -#define USART_PRESC_PRESCALER_256 (0xb << USART_PRESC_PRESCALER_SHIFT) - -/* Compatibility definitions ************************************************/ - -/* Compatibility with F1/F2/F4 Status Register names */ - -#define STM32_USART_SR_OFFSET STM32_USART_ISR_OFFSET - -#define USART_SR_PE USART_ISR_PE /* Parity Error */ -#define USART_SR_FE USART_ISR_FE /* Framing error */ -#define USART_SR_NE USART_ISR_NE /* Noise detected flag */ -#define USART_SR_ORE USART_ISR_ORE /* Overrun error */ -#define USART_SR_IDLE USART_ISR_IDLE /* IDLE line detected */ -#define USART_SR_RXNE USART_ISR_RXNE /* Read Data Register Not Empty */ -#define USART_SR_TC USART_ISR_TC /* Transmission Complete */ -#define USART_SR_TXE USART_ISR_TXE /* Transmit Data Register Empty */ -#define USART_SR_LBD USART_ISR_LBDF /* LIN Break Detection Flag */ -#define USART_SR_CTS USART_ISR_CTS /* CTS Flag */ - -#define USART_SR_ALLBITS USART_ISR_ALLBITS - -#define USART_CR1_M USART_CR1_M0 - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32G4XXXX_UART_H */ diff --git a/arch/arm/src/stm32/hardware/stm32l15xxx_uart.h b/arch/arm/src/stm32/hardware/stm32l15xxx_uart.h deleted file mode 100644 index f3cb64060db67..0000000000000 --- a/arch/arm/src/stm32/hardware/stm32l15xxx_uart.h +++ /dev/null @@ -1,208 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/hardware/stm32l15xxx_uart.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32L15XXX_UART_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32L15XXX_UART_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "chip.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Register Offsets *********************************************************/ - -#define STM32_USART_SR_OFFSET 0x0000 /* Status register (32-bits) */ -#define STM32_USART_DR_OFFSET 0x0004 /* Data register (32-bits) */ -#define STM32_USART_BRR_OFFSET 0x0008 /* Baud Rate Register (32-bits) */ -#define STM32_USART_CR1_OFFSET 0x000c /* Control register 1 (32-bits) */ -#define STM32_USART_CR2_OFFSET 0x0010 /* Control register 2 (32-bits) */ -#define STM32_USART_CR3_OFFSET 0x0014 /* Control register 3 (32-bits) */ -#define STM32_USART_GTPR_OFFSET 0x0018 /* Guard time and prescaler register (32-bits) */ - -/* Register Addresses *******************************************************/ - -#if STM32_NUSART > 0 -# define STM32_USART1_SR (STM32_USART1_BASE+STM32_USART_SR_OFFSET) -# define STM32_USART1_DR (STM32_USART1_BASE+STM32_USART_DR_OFFSET) -# define STM32_USART1_BRR (STM32_USART1_BASE+STM32_USART_BRR_OFFSET) -# define STM32_USART1_CR1 (STM32_USART1_BASE+STM32_USART_CR1_OFFSET) -# define STM32_USART1_CR2 (STM32_USART1_BASE+STM32_USART_CR2_OFFSET) -# define STM32_USART1_CR3 (STM32_USART1_BASE+STM32_USART_CR3_OFFSET) -# define STM32_USART1_GTPR (STM32_USART1_BASE+STM32_USART_GTPR_OFFSET) -#endif - -#if STM32_NUSART > 1 -# define STM32_USART2_SR (STM32_USART2_BASE+STM32_USART_SR_OFFSET) -# define STM32_USART2_DR (STM32_USART2_BASE+STM32_USART_DR_OFFSET) -# define STM32_USART2_BRR (STM32_USART2_BASE+STM32_USART_BRR_OFFSET) -# define STM32_USART2_CR1 (STM32_USART2_BASE+STM32_USART_CR1_OFFSET) -# define STM32_USART2_CR2 (STM32_USART2_BASE+STM32_USART_CR2_OFFSET) -# define STM32_USART2_CR3 (STM32_USART2_BASE+STM32_USART_CR3_OFFSET) -# define STM32_USART2_GTPR (STM32_USART2_BASE+STM32_USART_GTPR_OFFSET) -#endif - -#if STM32_NUSART > 2 -# define STM32_USART3_SR (STM32_USART3_BASE+STM32_USART_SR_OFFSET) -# define STM32_USART3_DR (STM32_USART3_BASE+STM32_USART_DR_OFFSET) -# define STM32_USART3_BRR (STM32_USART3_BASE+STM32_USART_BRR_OFFSET) -# define STM32_USART3_CR1 (STM32_USART3_BASE+STM32_USART_CR1_OFFSET) -# define STM32_USART3_CR2 (STM32_USART3_BASE+STM32_USART_CR2_OFFSET) -# define STM32_USART3_CR3 (STM32_USART3_BASE+STM32_USART_CR3_OFFSET) -# define STM32_USART3_GTPR (STM32_USART3_BASE+STM32_USART_GTPR_OFFSET) -#endif - -#if STM32_NUSART > 3 -# define STM32_UART4_SR (STM32_UART4_BASE+STM32_USART_SR_OFFSET) -# define STM32_UART4_DR (STM32_UART4_BASE+STM32_USART_DR_OFFSET) -# define STM32_UART4_BRR (STM32_UART4_BASE+STM32_USART_BRR_OFFSET) -# define STM32_UART4_CR1 (STM32_UART4_BASE+STM32_USART_CR1_OFFSET) -# define STM32_UART4_CR2 (STM32_UART4_BASE+STM32_USART_CR2_OFFSET) -# define STM32_UART4_CR3 (STM32_UART4_BASE+STM32_USART_CR3_OFFSET) -#endif - -#if STM32_NUSART > 4 -# define STM32_UART5_SR (STM32_UART5_BASE+STM32_USART_SR_OFFSET) -# define STM32_UART5_DR (STM32_UART5_BASE+STM32_USART_DR_OFFSET) -# define STM32_UART5_BRR (STM32_UART5_BASE+STM32_USART_BRR_OFFSET) -# define STM32_UART5_CR1 (STM32_UART5_BASE+STM32_USART_CR1_OFFSET) -# define STM32_UART5_CR2 (STM32_UART5_BASE+STM32_USART_CR2_OFFSET) -# define STM32_UART5_CR3 (STM32_UART5_BASE+STM32_USART_CR3_OFFSET) -#endif - -/* Register Bitfield Definitions ********************************************/ - -/* Status register */ - -#define USART_SR_PE (1 << 0) /* Bit 0: Parity Error */ -#define USART_SR_FE (1 << 1) /* Bit 1: Framing Error */ -#define USART_SR_NE (1 << 2) /* Bit 2: Noise Error Flag */ -#define USART_SR_ORE (1 << 3) /* Bit 3: OverRun Error */ -#define USART_SR_IDLE (1 << 4) /* Bit 4: IDLE line detected */ -#define USART_SR_RXNE (1 << 5) /* Bit 5: Read Data Register Not Empty */ -#define USART_SR_TC (1 << 6) /* Bit 6: Transmission Complete */ -#define USART_SR_TXE (1 << 7) /* Bit 7: Transmit Data Register Empty */ -#define USART_SR_LBD (1 << 8) /* Bit 8: LIN Break Detection Flag */ -#define USART_SR_CTS (1 << 9) /* Bit 9: CTS Flag */ - -#define USART_SR_ALLBITS (0x03ff) -#define USART_SR_CLRBITS (USART_SR_CTS|USART_SR_LBD) /* Cleared by SW write to SR */ - -/* Data register */ - -#define USART_DR_SHIFT (0) /* Bits 8:0: Data value */ -#define USART_DR_MASK (0x1ff << USART_DR_SHIFT) - -/* Baud Rate Register */ - -#define USART_BRR_FRAC_SHIFT (0) /* Bits 3-0: fraction of USARTDIV */ -#define USART_BRR_FRAC_MASK (0x0f << USART_BRR_FRAC_SHIFT) -#define USART_BRR_MANT_SHIFT (4) /* Bits 15-4: mantissa of USARTDIV */ -#define USART_BRR_MANT_MASK (0x0fff << USART_BRR_MANT_SHIFT) - -/* Control register 1 */ - -#define USART_CR1_SBK (1 << 0) /* Bit 0: Send Break */ -#define USART_CR1_RWU (1 << 1) /* Bit 1: Receiver wakeup */ -#define USART_CR1_RE (1 << 2) /* Bit 2: Receiver Enable */ -#define USART_CR1_TE (1 << 3) /* Bit 3: Transmitter Enable */ -#define USART_CR1_IDLEIE (1 << 4) /* Bit 4: IDLE Interrupt Enable */ -#define USART_CR1_RXNEIE (1 << 5) /* Bit 5: RXNE Interrupt Enable */ -#define USART_CR1_TCIE (1 << 6) /* Bit 6: Transmission Complete Interrupt Enable */ -#define USART_CR1_TXEIE (1 << 7) /* Bit 7: TXE Interrupt Enable */ -#define USART_CR1_PEIE (1 << 8) /* Bit 8: PE Interrupt Enable */ -#define USART_CR1_PS (1 << 9) /* Bit 9: Parity Selection */ -#define USART_CR1_PCE (1 << 10) /* Bit 10: Parity Control Enable */ -#define USART_CR1_WAKE (1 << 11) /* Bit 11: Wakeup method */ -#define USART_CR1_M (1 << 12) /* Bit 12: word length */ -#define USART_CR1_UE (1 << 13) /* Bit 13: USART Enable */ -#define USART_CR1_OVER8 (1 << 15) /* Bit 15: Oversampling mode */ - -#define USART_CR1_ALLINTS (USART_CR1_IDLEIE|USART_CR1_RXNEIE|USART_CR1_TCIE|USART_CR1_PEIE) - -/* Control register 2 */ - -#define USART_CR2_ADD_SHIFT (0) /* Bits 3-0: Address of the USART node */ -#define USART_CR2_ADD_MASK (0x0f << USART_CR2_ADD_SHIFT) -#define USART_CR2_LBDL (1 << 5) /* Bit 5: LIN Break Detection Length */ -#define USART_CR2_LBDIE (1 << 6) /* Bit 6: LIN Break Detection Interrupt Enable */ -#define USART_CR2_LBCL (1 << 8) /* Bit 8: Last Bit Clock pulse */ -#define USART_CR2_CPHA (1 << 9) /* Bit 9: Clock Phase */ -#define USART_CR2_CPOL (1 << 10) /* Bit 10: Clock Polarity */ -#define USART_CR2_CLKEN (1 << 11) /* Bit 11: Clock Enable */ -#define USART_CR2_STOP_SHIFT (12) /* Bits 13-12: STOP bits */ -#define USART_CR2_STOP_MASK (3 << USART_CR2_STOP_SHIFT) -# define USART_CR2_STOP1 (0 << USART_CR2_STOP_SHIFT) /* 00: 1 Stop bit */ -# define USART_CR2_STOP0p5 (1 << USART_CR2_STOP_SHIFT) /* 01: 0.5 Stop bit */ -# define USART_CR2_STOP2 (2 << USART_CR2_STOP_SHIFT) /* 10: 2 Stop bits */ -# define USART_CR2_STOP1p5 (3 << USART_CR2_STOP_SHIFT) /* 11: 1.5 Stop bit */ - -#define USART_CR2_LINEN (1 << 14) /* Bit 14: LIN mode enable */ - -/* Control register 3 */ - -#define USART_CR3_EIE (1 << 0) /* Bit 0: Error Interrupt Enable */ -#define USART_CR3_IREN (1 << 1) /* Bit 1: IrDA mode Enable */ -#define USART_CR3_IRLP (1 << 2) /* Bit 2: IrDA Low-Power */ -#define USART_CR3_HDSEL (1 << 3) /* Bit 3: Half-Duplex Selection */ -#define USART_CR3_NACK (1 << 4) /* Bit 4: Smartcard NACK enable */ -#define USART_CR3_SCEN (1 << 5) /* Bit 5: Smartcard mode enable */ -#define USART_CR3_DMAR (1 << 6) /* Bit 6: DMA Enable Receiver */ -#define USART_CR3_DMAT (1 << 7) /* Bit 7: DMA Enable Transmitter */ -#define USART_CR3_RTSE (1 << 8) /* Bit 8: RTS Enable */ -#define USART_CR3_CTSE (1 << 9) /* Bit 9: CTS Enable */ -#define USART_CR3_CTSIE (1 << 10) /* Bit 10: CTS Interrupt Enable */ -#define USART_CR3_ONEBIT (1 << 11) /* Bit 11: One sample bit method enable */ - -/* Guard time and prescaler register */ - -#define USART_GTPR_PSC_SHIFT (0) /* Bits 0-7: Prescaler value */ -#define USART_GTPR_PSC_MASK (0xff << USART_GTPR_PSC_SHIFT) -#define USART_GTPR_GT_SHIFT (8) /* Bits 8-15: Guard time value */ -#define USART_GTPR_GT_MASK (0xff << USART_GTPR_GT_SHIFT) - -/* Compatibility definitions ************************************************/ - -/* L15 Transmit/Read registers */ - -#define STM32_USART_RDR_OFFSET STM32_USART_DR_OFFSET /* Receive data register */ -#define STM32_USART_TDR_OFFSET STM32_USART_DR_OFFSET /* Transmit data register */ - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/**************************************************************************** - * Public Functions Prototypes - ****************************************************************************/ - -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32L15XXX_UART_H */ diff --git a/arch/arm/src/stm32/stm32.h b/arch/arm/src/stm32/stm32.h deleted file mode 100644 index 66b91b72e864a..0000000000000 --- a/arch/arm/src/stm32/stm32.h +++ /dev/null @@ -1,69 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32_STM32_H -#define __ARCH_ARM_SRC_STM32_STM32_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include -#include -#include - -#include "arm_internal.h" - -/* Peripherals **************************************************************/ - -#include "chip.h" -#include "stm32_adc.h" -#include "stm32_can.h" -#include "stm32_comp.h" -#include "stm32_dbgmcu.h" -#include "stm32_dma.h" -#include "stm32_dac.h" -#include "stm32_exti.h" -#include "stm32_flash.h" -#include "stm32_fmc.h" -#include "stm32_fsmc.h" -#include "stm32_gpio.h" -#include "stm32_i2c.h" -#include "stm32_ltdc.h" -#include "stm32_opamp.h" -#include "stm32_pwr.h" -#include "stm32_rcc.h" -#include "stm32_rtc.h" -#include "stm32_sdio.h" -#include "stm32_spi.h" -#include "stm32_i2s.h" -#include "stm32_tim.h" -#include "stm32_uart.h" -#if defined(CONFIG_USBDEV) && defined(CONFIG_STM32_USB) -# include "stm32_usbdev.h" -#endif -#include "stm32_wdg.h" -#include "stm32_lowputc.h" -#include "stm32_eth.h" - -#endif /* __ARCH_ARM_SRC_STM32_STM32_H */ diff --git a/arch/arm/src/stm32/stm32_1wire.c b/arch/arm/src/stm32/stm32_1wire.c deleted file mode 100644 index e3c27f32354ed..0000000000000 --- a/arch/arm/src/stm32/stm32_1wire.c +++ /dev/null @@ -1,1292 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_1wire.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* Links: - * https://www.maximintegrated.com/en/app-notes/index.mvp/id/214 - */ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include - -#include - -#include "arm_internal.h" -#include "stm32_rcc.h" -#include "stm32_1wire.h" - -#ifdef HAVE_1WIREDRIVER - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#define BUS_TIMEOUT 5 /* tv_sec */ - -#define RESET_BAUD 9600 -#define RESET_TX 0xF0 -#define TIMESLOT_BAUD 115200 -#define READ_TX 0xFF -#define READ_RX1 0xFF -#define WRITE_TX0 0x00 -#define WRITE_TX1 0xFF - -#if defined(CONFIG_STM32_STM32F10XX) -# define PIN_OPENDRAIN(GPIO) ((GPIO) | GPIO_CNF_OUTOD) -#else -# define PIN_OPENDRAIN(GPIO) ((GPIO) | GPIO_OPENDRAIN) -#endif - -#if defined(CONFIG_STM32_STM32F10XX) -# define USART_CR3_ONEBIT (0) -#endif - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/* 1-Wire bus task */ - -enum stm32_1wire_msg_e -{ - ONEWIRETASK_NONE = 0, - ONEWIRETASK_RESET, - ONEWIRETASK_WRITE, - ONEWIRETASK_READ, - ONEWIRETASK_WRITEBIT, - ONEWIRETASK_READBIT -}; - -struct stm32_1wire_msg_s -{ - enum stm32_1wire_msg_e task; /* Task */ - uint8_t *buffer; /* Task buffer */ - int buflen; /* Buffer length */ -}; - -/* 1-Wire device hardware configuration */ - -struct stm32_1wire_config_s -{ - const uint32_t usartbase; /* Base address of USART registers */ - const uint32_t apbclock; /* PCLK 1 or 2 frequency */ - const uint32_t data_pin; /* GPIO configuration for DATA */ - const uint8_t irq; /* IRQ associated with this USART */ -}; - -/* 1-Wire device Private Data */ - -struct stm32_1wire_priv_s -{ - const struct stm32_1wire_config_s *config; /* Port configuration */ - volatile int refs; /* Reference count */ - mutex_t lock; /* Mutual exclusion mutex */ - sem_t sem_isr; /* Interrupt wait semaphore */ - int baud; /* Baud rate */ - const struct stm32_1wire_msg_s *msgs; /* Messages data */ - uint8_t *byte; /* Current byte */ - uint8_t bit; /* Current bit */ - volatile int result; /* Exchange result */ -}; - -/* 1-Wire device, Instance */ - -struct stm32_1wire_inst_s -{ - const struct onewire_ops_s *ops; /* Standard 1-Wire operations */ - struct stm32_1wire_priv_s *priv; /* Common driver private data structure */ -}; - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -static inline uint32_t stm32_1wire_in(struct stm32_1wire_priv_s *priv, - int offset); -static inline void stm32_1wire_out(struct stm32_1wire_priv_s *priv, - int offset, uint32_t value); -static int stm32_1wire_recv(struct stm32_1wire_priv_s *priv); -static void stm32_1wire_send(struct stm32_1wire_priv_s *priv, int ch); -static void stm32_1wire_set_baud(struct stm32_1wire_priv_s *priv); -static void stm32_1wire_set_apb_clock(struct stm32_1wire_priv_s *priv, - bool on); -static int stm32_1wire_init(struct stm32_1wire_priv_s *priv); -static int stm32_1wire_deinit(struct stm32_1wire_priv_s *priv); -static int stm32_1wire_process(struct stm32_1wire_priv_s *priv, - const struct stm32_1wire_msg_s *msgs, - int count); -static int stm32_1wire_isr(int irq, void *context, void *arg); -static int stm32_1wire_reset(struct onewire_dev_s *dev); -static int stm32_1wire_write(struct onewire_dev_s *dev, - const uint8_t *buffer, int buflen); -static int stm32_1wire_read(struct onewire_dev_s *dev, uint8_t *buffer, - int buflen); -static int stm32_1wire_exchange(struct onewire_dev_s *dev, bool reset, - const uint8_t *txbuffer, int txbuflen, - uint8_t *rxbuffer, int rxbuflen); -static int stm32_1wire_writebit(struct onewire_dev_s *dev, - const uint8_t *bit); -static int stm32_1wire_readbit(struct onewire_dev_s *dev, uint8_t *bit); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* 1-Wire device structures */ - -#ifdef CONFIG_STM32_USART1_1WIREDRIVER - -static const struct stm32_1wire_config_s stm32_1wire1_config = -{ - .usartbase = STM32_USART1_BASE, - .apbclock = STM32_PCLK2_FREQUENCY, - .data_pin = PIN_OPENDRAIN(GPIO_USART1_TX), - .irq = STM32_IRQ_USART1, -}; - -static struct stm32_1wire_priv_s stm32_1wire1_priv = -{ - .config = &stm32_1wire1_config, - .refs = 0, - .lock = NXMUTEX_INITIALIZER, - .sem_isr = SEM_INITIALIZER(0), - .msgs = NULL -}; - -#endif - -#ifdef CONFIG_STM32_USART2_1WIREDRIVER - -static const struct stm32_1wire_config_s stm32_1wire2_config = -{ - .usartbase = STM32_USART2_BASE, - .apbclock = STM32_PCLK1_FREQUENCY, - .data_pin = PIN_OPENDRAIN(GPIO_USART2_TX), - .irq = STM32_IRQ_USART2, -}; - -static struct stm32_1wire_priv_s stm32_1wire2_priv = -{ - .config = &stm32_1wire2_config, - .refs = 0, - .lock = NXMUTEX_INITIALIZER, - .sem_isr = SEM_INITIALIZER(0), - .msgs = NULL -}; - -#endif - -#ifdef CONFIG_STM32_USART3_1WIREDRIVER - -static const struct stm32_1wire_config_s stm32_1wire3_config = -{ - .usartbase = STM32_USART3_BASE, - .apbclock = STM32_PCLK1_FREQUENCY, - .data_pin = PIN_OPENDRAIN(GPIO_USART3_TX), - .irq = STM32_IRQ_USART3, -}; - -static struct stm32_1wire_priv_s stm32_1wire3_priv = -{ - .config = &stm32_1wire3_config, - .refs = 0, - .lock = NXMUTEX_INITIALIZER, - .sem_isr = SEM_INITIALIZER(0), - .msgs = NULL -}; - -#endif - -#ifdef CONFIG_STM32_UART4_1WIREDRIVER - -static const struct stm32_1wire_config_s stm32_1wire4_config = -{ - .usartbase = STM32_UART4_BASE, - .apbclock = STM32_PCLK1_FREQUENCY, - .data_pin = PIN_OPENDRAIN(GPIO_UART4_TX), - .irq = STM32_IRQ_UART4, -}; - -static struct stm32_1wire_priv_s stm32_1wire4_priv = -{ - .config = &stm32_1wire4_config, - .refs = 0, - .lock = NXMUTEX_INITIALIZER, - .sem_isr = SEM_INITIALIZER(0), - .msgs = NULL -}; - -#endif - -#ifdef CONFIG_STM32_UART5_1WIREDRIVER - -static const struct stm32_1wire_config_s stm32_1wire5_config = -{ - .usartbase = STM32_UART5_BASE, - .apbclock = STM32_PCLK1_FREQUENCY, - .data_pin = PIN_OPENDRAIN(GPIO_UART5_TX), - .irq = STM32_IRQ_UART5, -}; - -static struct stm32_1wire_priv_s stm32_1wire5_priv = -{ - .config = &stm32_1wire5_config, - .refs = 0, - .lock = NXMUTEX_INITIALIZER, - .sem_isr = SEM_INITIALIZER(0), - .msgs = NULL -}; - -#endif - -#ifdef CONFIG_STM32_USART6_1WIREDRIVER - -static const struct stm32_1wire_config_s stm32_1wire6_config = -{ - .usartbase = STM32_USART6_BASE, - .apbclock = STM32_PCLK2_FREQUENCY, - .data_pin = PIN_OPENDRAIN(GPIO_USART6_TX), - .irq = STM32_IRQ_USART6, -}; - -static struct stm32_1wire_priv_s stm32_1wire6_priv = -{ - .config = &stm32_1wire6_config, - .refs = 0, - .lock = NXMUTEX_INITIALIZER, - .sem_isr = SEM_INITIALIZER(0), - .msgs = NULL -}; - -#endif - -#ifdef CONFIG_STM32_UART7_1WIREDRIVER - -static const struct stm32_1wire_config_s stm32_1wire7_config = -{ - .usartbase = STM32_UART7_BASE, - .apbclock = STM32_PCLK1_FREQUENCY, - .data_pin = PIN_OPENDRAIN(GPIO_UART7_TX), - .irq = STM32_IRQ_UART7, -}; - -static struct stm32_1wire_priv_s stm32_1wire7_priv = -{ - .config = &stm32_1wire7_config, - .refs = 0, - .lock = NXMUTEX_INITIALIZER, - .sem_isr = SEM_INITIALIZER(0), - .msgs = NULL -}; - -#endif - -#ifdef CONFIG_STM32_UART8_1WIREDRIVER - -static const struct stm32_1wire_config_s stm32_1wire8_config = -{ - .usartbase = STM32_UART8_BASE, - .apbclock = STM32_PCLK1_FREQUENCY, - .data_pin = PIN_OPENDRAIN(GPIO_UART8_TX), - .irq = STM32_IRQ_UART8, -}; - -static struct stm32_1wire_priv_s stm32_1wire8_priv = -{ - .config = &stm32_1wire8_config, - .refs = 0, - .lock = NXMUTEX_INITIALIZER, - .sem_isr = SEM_INITIALIZER(0), - .msgs = NULL -}; - -#endif - -/* Device Structures, Instantiation */ - -static const struct onewire_ops_s stm32_1wire_ops = -{ - .reset = stm32_1wire_reset, - .write = stm32_1wire_write, - .read = stm32_1wire_read, - .exchange = stm32_1wire_exchange, - .writebit = stm32_1wire_writebit, - .readbit = stm32_1wire_readbit -}; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_1wire_in - ****************************************************************************/ - -static inline uint32_t stm32_1wire_in(struct stm32_1wire_priv_s *priv, - int offset) -{ - return getreg32(priv->config->usartbase + offset); -} - -/**************************************************************************** - * Name: stm32_1wire_out - ****************************************************************************/ - -static inline void stm32_1wire_out(struct stm32_1wire_priv_s *priv, - int offset, uint32_t value) -{ - putreg32(value, priv->config->usartbase + offset); -} - -/**************************************************************************** - * Name: stm32_1wire_recv - * - * Description: - * This method will recv one byte on the USART - * - ****************************************************************************/ - -static int stm32_1wire_recv(struct stm32_1wire_priv_s *priv) -{ - return stm32_1wire_in(priv, STM32_USART_RDR_OFFSET) & 0xff; -} - -/**************************************************************************** - * Name: stm32_1wire_send - * - * Description: - * This method will send one byte on the USART - * - ****************************************************************************/ - -static void stm32_1wire_send(struct stm32_1wire_priv_s *priv, int ch) -{ - stm32_1wire_out(priv, STM32_USART_TDR_OFFSET, (uint32_t)(ch & 0xff)); -} - -/**************************************************************************** - * Name: stm32_1wire_set_baud - * - * Description: - * Set the serial line baud. - * - ****************************************************************************/ - -static void stm32_1wire_set_baud(struct stm32_1wire_priv_s *priv) -{ -#if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX) - /* This first implementation is for U[S]ARTs that support oversampling - * by 8 in additional to the standard oversampling by 16. - */ - - uint32_t usartdiv8; - uint32_t cr1; - uint32_t brr; - - /* In case of oversampling by 8, the equation is: - * - * baud = 2 * fCK / usartdiv8 - * usartdiv8 = 2 * fCK / baud - */ - - usartdiv8 = ((priv->config->apbclock << 1) + (priv->baud >> 1)) / - priv->baud; - - /* Baud rate for standard USART (SPI mode included): - * - * In case of oversampling by 16, the equation is: - * baud = fCK / usartdiv16 - * usartdiv16 = fCK / baud - * = 2 * usartdiv8 - */ - - /* Use oversamply by 8 only if the divisor is small. But what is small? */ - - cr1 = stm32_1wire_in(priv, STM32_USART_CR1_OFFSET); - if (usartdiv8 > 100) - { - /* Use usartdiv16 */ - - brr = (usartdiv8 + 1) >> 1; - - /* Clear oversampling by 8 to enable oversampling by 16 */ - - cr1 &= ~USART_CR1_OVER8; - } - else - { - DEBUGASSERT(usartdiv8 >= 8); - - /* Perform mysterious operations on bits 0-3 */ - - brr = ((usartdiv8 & 0xfff0) | ((usartdiv8 & 0x000f) >> 1)); - - /* Set oversampling by 8 */ - - cr1 |= USART_CR1_OVER8; - } - - stm32_1wire_out(priv, STM32_USART_CR1_OFFSET, cr1); - stm32_1wire_out(priv, STM32_USART_BRR_OFFSET, brr); - -#else - - /* This second implementation is for U[S]ARTs that support fractional - * dividers. - */ - - uint32_t usartdiv32; - uint32_t mantissa; - uint32_t fraction; - uint32_t brr; - - /* Configure the USART Baud Rate. The baud rate for the receiver and - * transmitter (Rx and Tx) are both set to the same value as programmed - * in the Mantissa and Fraction values of USARTDIV. - * - * baud = fCK / (16 * usartdiv) - * usartdiv = fCK / (16 * baud) - * - * Where fCK is the input clock to the peripheral (PCLK1 for USART2, 3, 4, - * 5 or PCLK2 for USART1) - * - * First calculate (NOTE: all stand baud values are even so dividing by two - * does not lose precision): - * - * usartdiv32 = 32 * usartdiv = fCK / (baud/2) - */ - - usartdiv32 = priv->config->apbclock / (priv->baud >> 1); - - /* The mantissa part is then */ - - mantissa = usartdiv32 >> 5; - brr = mantissa << USART_BRR_MANT_SHIFT; - - /* The fractional remainder (with rounding) */ - - fraction = (usartdiv32 - (mantissa << 5) + 1) >> 1; - brr |= fraction << USART_BRR_FRAC_SHIFT; - stm32_1wire_out(priv, STM32_USART_BRR_OFFSET, brr); -#endif -} - -/**************************************************************************** - * Name: stm32_1wire_set_apb_clock - * - * Description: - * Enable or disable APB clock for the USART peripheral - * - * Input Parameters: - * priv - A reference to the 1-Wire driver state structure - * on - Enable clock if 'on' is 'true' and disable if 'false' - * - ****************************************************************************/ - -static void stm32_1wire_set_apb_clock(struct stm32_1wire_priv_s *priv, - bool on) -{ - const struct stm32_1wire_config_s *config = priv->config; - uint32_t rcc_en; - uint32_t regaddr; - - /* Determine which USART to configure */ - - switch (config->usartbase) - { - default: - return; - -#ifdef CONFIG_STM32_USART1_1WIREDRIVER - case STM32_USART1_BASE: - rcc_en = RCC_APB2ENR_USART1EN; - regaddr = STM32_RCC_APB2ENR; - break; -#endif -#ifdef CONFIG_STM32_USART2_1WIREDRIVER - case STM32_USART2_BASE: - rcc_en = RCC_APB1ENR_USART2EN; - regaddr = STM32_RCC_APB1ENR; - break; -#endif -#ifdef CONFIG_STM32_USART3_1WIREDRIVER - case STM32_USART3_BASE: - rcc_en = RCC_APB1ENR_USART3EN; - regaddr = STM32_RCC_APB1ENR; - break; -#endif -#ifdef CONFIG_STM32_UART4_1WIREDRIVER - case STM32_UART4_BASE: - rcc_en = RCC_APB1ENR_UART4EN; - regaddr = STM32_RCC_APB1ENR; - break; -#endif -#ifdef CONFIG_STM32_UART5_1WIREDRIVER - case STM32_UART5_BASE: - rcc_en = RCC_APB1ENR_UART5EN; - regaddr = STM32_RCC_APB1ENR; - break; -#endif -#ifdef CONFIG_STM32_USART6_1WIREDRIVER - case STM32_USART6_BASE: - rcc_en = RCC_APB2ENR_USART6EN; - regaddr = STM32_RCC_APB2ENR; - break; -#endif -#ifdef CONFIG_STM32_UART7_1WIREDRIVER - case STM32_UART7_BASE: - rcc_en = RCC_APB1ENR_UART7EN; - regaddr = STM32_RCC_APB1ENR; - break; -#endif -#ifdef CONFIG_STM32_UART8_1WIREDRIVER - case STM32_UART8_BASE: - rcc_en = RCC_APB1ENR_UART8EN; - regaddr = STM32_RCC_APB1ENR; - break; -#endif - } - - /* Enable/disable APB 1/2 clock for USART */ - - if (on) - { - modifyreg32(regaddr, 0, rcc_en); - } - else - { - modifyreg32(regaddr, rcc_en, 0); - } -} - -/**************************************************************************** - * Name: stm32_1wire_init - * - * Description: - * Setup the 1-Wire hardware, ready for operation with defaults - * - ****************************************************************************/ - -static int stm32_1wire_init(struct stm32_1wire_priv_s *priv) -{ - const struct stm32_1wire_config_s *config = priv->config; - uint32_t regval; - int ret; - - /* Enable USART APB1/2 clock */ - - stm32_1wire_set_apb_clock(priv, true); - - /* Configure CR2 - * Clear STOP, CLKEN, CPOL, CPHA, LBCL, and interrupt enable bits - * Set LBDIE - */ - - regval = stm32_1wire_in(priv, STM32_USART_CR2_OFFSET); - regval &= ~(USART_CR2_STOP_MASK | USART_CR2_CLKEN | USART_CR2_CPOL | - USART_CR2_CPHA | USART_CR2_LBCL | USART_CR2_LBDIE); - regval |= USART_CR2_LBDIE; - stm32_1wire_out(priv, STM32_USART_CR2_OFFSET, regval); - - /* Configure CR1 - * Clear TE, REm, all interrupt enable bits, PCE, PS and M - * Set RXNEIE - */ - - regval = stm32_1wire_in(priv, STM32_USART_CR1_OFFSET); - regval &= ~(USART_CR1_TE | USART_CR1_RE | USART_CR1_ALLINTS | - USART_CR1_PCE | USART_CR1_PS | USART_CR1_M); - regval |= USART_CR1_RXNEIE; - stm32_1wire_out(priv, STM32_USART_CR1_OFFSET, regval); - - /* Configure CR3 - * Clear CTSE, RTSE, and all interrupt enable bits - * Set ONEBIT, HDSEL and EIE - */ - - regval = stm32_1wire_in(priv, STM32_USART_CR3_OFFSET); - regval &= ~(USART_CR3_CTSIE | USART_CR3_CTSE | USART_CR3_RTSE | - USART_CR3_EIE); - regval |= (USART_CR3_ONEBIT | USART_CR3_HDSEL | USART_CR3_EIE); - stm32_1wire_out(priv, STM32_USART_CR3_OFFSET, regval); - - /* Set baud rate */ - - priv->baud = RESET_BAUD; - stm32_1wire_set_baud(priv); - - /* Enable Rx, Tx, and the USART */ - - regval = stm32_1wire_in(priv, STM32_USART_CR1_OFFSET); - regval |= (USART_CR1_UE | USART_CR1_TE | USART_CR1_RE); - stm32_1wire_out(priv, STM32_USART_CR1_OFFSET, regval); - - /* Configure pins for USART use */ - - stm32_configgpio(config->data_pin); - - ret = irq_attach(config->irq, stm32_1wire_isr, priv); - if (ret == OK) - { - up_enable_irq(config->irq); - } - - return ret; -} - -/**************************************************************************** - * Name: stm32_1wire_deinit - * - * Description: - * Shutdown the 1-Wire hardware - * - ****************************************************************************/ - -static int stm32_1wire_deinit(struct stm32_1wire_priv_s *priv) -{ - const struct stm32_1wire_config_s *config = priv->config; - uint32_t regval; - - up_disable_irq(config->irq); - irq_detach(config->irq); - - /* Unconfigure GPIO pins */ - - stm32_unconfiggpio(config->data_pin); - - /* Disable RXNEIE, Rx, Tx, and the USART */ - - regval = stm32_1wire_in(priv, STM32_USART_CR1_OFFSET); - regval &= ~(USART_CR1_UE | USART_CR1_TE | USART_CR1_RE | USART_CR1_RXNEIE); - stm32_1wire_out(priv, STM32_USART_CR1_OFFSET, regval); - - /* Clear LBDIE */ - - regval = stm32_1wire_in(priv, STM32_USART_CR2_OFFSET); - regval &= ~USART_CR2_LBDIE; - stm32_1wire_out(priv, STM32_USART_CR2_OFFSET, regval); - - /* Clear ONEBIT, HDSEL and EIE */ - - regval = stm32_1wire_in(priv, STM32_USART_CR3_OFFSET); - regval &= ~(USART_CR3_ONEBIT | USART_CR3_HDSEL | USART_CR3_EIE); - stm32_1wire_out(priv, STM32_USART_CR3_OFFSET, regval); - - /* Disable USART APB1/2 clock */ - - stm32_1wire_set_apb_clock(priv, false); - - return OK; -} - -/**************************************************************************** - * Name: stm32_1wire_exec - * - * Description: - * Execute 1-Wire task - ****************************************************************************/ - -static int stm32_1wire_process(struct stm32_1wire_priv_s *priv, - const struct stm32_1wire_msg_s *msgs, - int count) -{ - irqstate_t irqs; - int index; - int ret; - - /* Lock out other clients */ - - ret = nxmutex_lock(&priv->lock); - if (ret < 0) - { - return ret; - } - - priv->result = ERROR; - - for (index = 0; index < count; index++) - { - switch (msgs[index].task) - { - case ONEWIRETASK_NONE: - priv->result = OK; - break; - - case ONEWIRETASK_RESET: - - /* Set baud rate */ - - priv->baud = RESET_BAUD; - stm32_1wire_set_baud(priv); - - /* Atomic */ - - irqs = enter_critical_section(); - priv->msgs = &msgs[index]; - stm32_1wire_send(priv, RESET_TX); - leave_critical_section(irqs); - - /* Wait. Break on timeout if TX line closed to GND */ - - nxsem_tickwait(&priv->sem_isr, SEC2TICK(BUS_TIMEOUT)); - break; - - case ONEWIRETASK_WRITE: - case ONEWIRETASK_WRITEBIT: - - /* Set baud rate */ - - priv->baud = TIMESLOT_BAUD; - stm32_1wire_set_baud(priv); - - /* Atomic */ - - irqs = enter_critical_section(); - priv->msgs = &msgs[index]; - priv->byte = priv->msgs->buffer; - priv->bit = 0; - stm32_1wire_send(priv, (*priv->byte & (1 << priv->bit)) ? - WRITE_TX1 : WRITE_TX0); - leave_critical_section(irqs); - - /* Wait. Break on timeout if TX line closed to GND */ - - nxsem_tickwait(&priv->sem_isr, SEC2TICK(BUS_TIMEOUT)); - break; - - case ONEWIRETASK_READ: - case ONEWIRETASK_READBIT: - - /* Set baud rate */ - - priv->baud = TIMESLOT_BAUD; - stm32_1wire_set_baud(priv); - - /* Atomic */ - - irqs = enter_critical_section(); - priv->msgs = &msgs[index]; - priv->byte = priv->msgs->buffer; - priv->bit = 0; - stm32_1wire_send(priv, READ_TX); - leave_critical_section(irqs); - - /* Wait. Break on timeout if TX line closed to GND */ - - nxsem_tickwait(&priv->sem_isr, SEC2TICK(BUS_TIMEOUT)); - break; - } - - if (priv->result != OK) /* break if error */ - { - break; - } - } - - /* Atomic */ - - irqs = enter_critical_section(); - priv->msgs = NULL; - ret = priv->result; - leave_critical_section(irqs); - - /* Release the port for reuse by other clients */ - - nxmutex_unlock(&priv->lock); - return ret; -} - -/**************************************************************************** - * Name: stm32_1wire_isr - * - * Description: - * Common Interrupt Service Routine - ****************************************************************************/ - -static int stm32_1wire_isr(int irq, void *context, void *arg) -{ - struct stm32_1wire_priv_s *priv = (struct stm32_1wire_priv_s *)arg; - uint32_t sr; - uint32_t dr; - - DEBUGASSERT(priv != NULL); - - /* Get the masked USART status word. */ - - sr = stm32_1wire_in(priv, STM32_USART_SR_OFFSET); - - /* Receive loop */ - - if ((sr & USART_SR_RXNE) != 0) - { - dr = stm32_1wire_recv(priv); - - if (priv->msgs != NULL) - { - switch (priv->msgs->task) - { - case ONEWIRETASK_NONE: - break; - - case ONEWIRETASK_RESET: - priv->msgs = NULL; - priv->result = (dr != RESET_TX) ? OK : -ENODEV; /* if read RESET_TX then no slave */ - nxsem_post(&priv->sem_isr); - break; - - case ONEWIRETASK_WRITE: - if (++priv->bit >= 8) - { - priv->bit = 0; - if (++priv->byte >= (priv->msgs->buffer + priv->msgs->buflen)) /* Done? */ - { - priv->msgs = NULL; - priv->result = OK; - nxsem_post(&priv->sem_isr); - break; - } - } - - /* Send next bit */ - - stm32_1wire_send(priv, (*priv->byte & (1 << priv->bit)) ? - WRITE_TX1 : WRITE_TX0); - break; - - case ONEWIRETASK_READ: - if (dr == READ_RX1) - { - *priv->byte |= (1 << priv->bit); - } - else - { - *priv->byte &= ~(1 << priv->bit); - } - - if (++priv->bit >= 8) - { - priv->bit = 0; - if (++priv->byte >= (priv->msgs->buffer + priv->msgs->buflen)) /* Done? */ - { - priv->msgs = NULL; - priv->result = OK; - nxsem_post(&priv->sem_isr); - break; - } - } - - /* Recv next bit */ - - stm32_1wire_send(priv, READ_TX); - break; - - case ONEWIRETASK_READBIT: - *priv->byte = (dr == READ_RX1) ? 1 : 0; - - /* Fall through */ - - case ONEWIRETASK_WRITEBIT: - priv->msgs = NULL; - priv->result = OK; - nxsem_post(&priv->sem_isr); - break; - } - } - } - - /* Bounce check. */ - - if ((sr & (USART_SR_ORE | USART_SR_NE | USART_SR_FE)) != 0) - { -#if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX) - /* These errors are cleared by writing the corresponding bit to the - * interrupt clear register (ICR). - */ - - stm32_1wire_out(priv, STM32_USART_ICR_OFFSET, - (USART_ICR_NCF | USART_ICR_ORECF | USART_ICR_FECF)); -#else - /* If an error occurs, read from DR to clear the error (data has - * been lost). If ORE is set along with RXNE then it tells you - * that the byte *after* the one in the data register has been - * lost, but the data register value is correct. That case will - * be handled above if interrupts are enabled. Otherwise, that - * good byte will be lost. - */ - - stm32_1wire_recv(priv); -#endif - - if (priv->msgs != NULL) - { - priv->msgs = NULL; - priv->result = ERROR; - nxsem_post(&priv->sem_isr); - } - } - - /* Bounce check. LIN break detection */ - - if ((sr & USART_SR_LBD) != 0) - { - sr &= ~USART_SR_LBD; - stm32_1wire_out(priv, STM32_USART_SR_OFFSET, sr); - - if (priv->msgs != NULL) - { - priv->msgs = NULL; - priv->result = ERROR; - nxsem_post(&priv->sem_isr); - } - } - - return OK; -} - -/**************************************************************************** - * Name: stm32_1wire_reset - * - * Description: - * 1-Wire reset pulse and presence detect. - * - ****************************************************************************/ - -static int stm32_1wire_reset(struct onewire_dev_s *dev) -{ - struct stm32_1wire_priv_s *priv = ((struct stm32_1wire_inst_s *)dev)->priv; - const struct stm32_1wire_msg_s msgs[1] = - { - [0].task = ONEWIRETASK_RESET - }; - - return stm32_1wire_process(priv, msgs, 1); -} - -/**************************************************************************** - * Name: stm32_1wire_write - * - * Description: - * Write 1-Wire data - * - ****************************************************************************/ - -static int stm32_1wire_write(struct onewire_dev_s *dev, - const uint8_t *buffer, int buflen) -{ - struct stm32_1wire_priv_s *priv = ((struct stm32_1wire_inst_s *)dev)->priv; - const struct stm32_1wire_msg_s msgs[1] = - { - [0].task = ONEWIRETASK_WRITE, - [0].buffer = (uint8_t *)buffer, - [0].buflen = buflen - }; - - return stm32_1wire_process(priv, msgs, 1); -} - -/**************************************************************************** - * Name: stm32_1wire_read - * - * Description: - * Read 1-Wire data - * - ****************************************************************************/ - -static int stm32_1wire_read(struct onewire_dev_s *dev, uint8_t *buffer, - int buflen) -{ - struct stm32_1wire_priv_s *priv = ((struct stm32_1wire_inst_s *)dev)->priv; - const struct stm32_1wire_msg_s msgs[1] = - { - [0].task = ONEWIRETASK_READ, - [0].buffer = buffer, - [0].buflen = buflen - }; - - return stm32_1wire_process(priv, msgs, 1); -} - -/**************************************************************************** - * Name: stm32_1wire_exchange - * - * Description: - * 1-Wire reset pulse and presence detect, - * Write 1-Wire data, - * Read 1-Wire data - * - ****************************************************************************/ - -static int stm32_1wire_exchange(struct onewire_dev_s *dev, bool reset, - const uint8_t *txbuffer, int txbuflen, - uint8_t *rxbuffer, int rxbuflen) -{ - int result = ERROR; - struct stm32_1wire_priv_s *priv = ((struct stm32_1wire_inst_s *)dev)->priv; - - if (reset) - { - const struct stm32_1wire_msg_s msgs[3] = - { - [0].task = ONEWIRETASK_RESET, - - [1].task = ONEWIRETASK_WRITE, - [1].buffer = (uint8_t *)txbuffer, - [1].buflen = txbuflen, - - [2].task = ONEWIRETASK_READ, - [2].buffer = rxbuffer, - [2].buflen = rxbuflen - }; - - result = stm32_1wire_process(priv, msgs, 3); - } - else - { - const struct stm32_1wire_msg_s msgs[2] = - { - [0].task = ONEWIRETASK_WRITE, - [0].buffer = (uint8_t *)txbuffer, - [0].buflen = txbuflen, - - [1].task = ONEWIRETASK_READ, - [1].buffer = rxbuffer, - [1].buflen = rxbuflen - }; - - result = stm32_1wire_process(priv, msgs, 2); - } - - return result; -} - -/**************************************************************************** - * Name: stm32_1wire_writebit - * - * Description: - * Write one bit of 1-Wire data - * - ****************************************************************************/ - -static int stm32_1wire_writebit(struct onewire_dev_s *dev, - const uint8_t *bit) -{ - struct stm32_1wire_priv_s *priv = ((struct stm32_1wire_inst_s *)dev)->priv; - const struct stm32_1wire_msg_s msgs[1] = - { - [0].task = ONEWIRETASK_WRITEBIT, - [0].buffer = (uint8_t *)bit, - [0].buflen = 1 - }; - - DEBUGASSERT(*bit == 0 || *bit == 1); - - return stm32_1wire_process(priv, msgs, 1); -} - -/**************************************************************************** - * Name: stm32_1wire_readbit - * - * Description: - * Sample one bit of 1-Wire data - * - ****************************************************************************/ - -static int stm32_1wire_readbit(struct onewire_dev_s *dev, uint8_t *bit) -{ - struct stm32_1wire_priv_s *priv = ((struct stm32_1wire_inst_s *)dev)->priv; - const struct stm32_1wire_msg_s msgs[1] = - { - [0].task = ONEWIRETASK_READBIT, - [0].buffer = bit, - [0].buflen = 1 - }; - - return stm32_1wire_process(priv, msgs, 1); -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_1wireinitialize - * - * Description: - * Initialize the selected 1-Wire port. And return a unique instance of - * struct onewire_dev_s. This function may be called to obtain multiple - * instances of the interface, each of which may be set up with a - * different frequency and slave address. - * - * Input Parameters: - * Port number (for hardware that has multiple 1-Wire interfaces) - * - * Returned Value: - * Valid 1-Wire device structure reference on success; a NULL on failure - * - ****************************************************************************/ - -struct onewire_dev_s *stm32_1wireinitialize(int port) -{ - struct stm32_1wire_priv_s *priv = NULL; /* Private data of device with multiple instances */ - struct stm32_1wire_inst_s *inst = NULL; /* Device, single instance */ - - /* Get 1-Wire private structure */ - - switch (port) - { -#ifdef CONFIG_STM32_USART1_1WIREDRIVER - case 1: - priv = &stm32_1wire1_priv; - break; -#endif -#ifdef CONFIG_STM32_USART2_1WIREDRIVER - case 2: - priv = &stm32_1wire2_priv; - break; -#endif -#ifdef CONFIG_STM32_USART3_1WIREDRIVER - case 3: - priv = &stm32_1wire3_priv; - break; -#endif -#ifdef CONFIG_STM32_UART4_1WIREDRIVER - case 4: - priv = &stm32_1wire4_priv; - break; -#endif -#ifdef CONFIG_STM32_UART5_1WIREDRIVER - case 5: - priv = &stm32_1wire5_priv; - break; -#endif -#ifdef CONFIG_STM32_USART6_1WIREDRIVER - case 6: - priv = &stm32_1wire6_priv; - break; -#endif -#ifdef CONFIG_STM32_UART7_1WIREDRIVER - case 7: - priv = &stm32_1wire7_priv; - break; -#endif -#ifdef CONFIG_STM32_UART8_1WIREDRIVER - case 8: - priv = &stm32_1wire8_priv; - break; -#endif - default: - return NULL; - } - - /* Allocate instance */ - - inst = kmm_malloc(sizeof(*inst)); - if (inst == NULL) - { - return NULL; - } - - /* Initialize instance */ - - inst->ops = &stm32_1wire_ops; - inst->priv = priv; - - /* Initialize private data for the first time, increment reference count, - * power-up hardware and configure GPIOs. - */ - - nxmutex_lock(&priv->lock); - if (priv->refs++ == 0) - { - stm32_1wire_init(priv); - } - - nxmutex_unlock(&priv->lock); - return (struct onewire_dev_s *)inst; -} - -/**************************************************************************** - * Name: stm32_1wireuninitialize - * - * Description: - * De-initialize the selected 1-Wire port, and power down the device. - * - * Input Parameters: - * Device structure as returned by the stm32_1wireinitialize() - * - * Returned Value: - * OK on success, ERROR when internal reference count mismatch or dev - * points to invalid hardware device. - * - ****************************************************************************/ - -int stm32_1wireuninitialize(struct onewire_dev_s *dev) -{ - struct stm32_1wire_priv_s *priv = ((struct stm32_1wire_inst_s *)dev)->priv; - - DEBUGASSERT(priv); - - /* Decrement reference count and check for underflow */ - - if (priv->refs == 0) - { - return ERROR; - } - - nxmutex_lock(&priv->lock); - if (--priv->refs) - { - nxmutex_unlock(&priv->lock); - return OK; - } - - /* Disable power and other HW resource (GPIO's) */ - - stm32_1wire_deinit(priv); - nxmutex_unlock(&priv->lock); - - /* Free instance */ - - kmm_free(dev); - return OK; -} - -#endif /* HAVE_1WIREDRIVER */ diff --git a/arch/arm/src/stm32/stm32_adc.c b/arch/arm/src/stm32/stm32_adc.c deleted file mode 100644 index cd53b780eb463..0000000000000 --- a/arch/arm/src/stm32/stm32_adc.c +++ /dev/null @@ -1,5001 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_adc.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include - -#include "arm_internal.h" -#include "chip.h" -#include "stm32_rcc.h" -#include "stm32_tim.h" -#include "stm32_dma.h" -#include "stm32_adc.h" - -/* The STM32 ADC lower-half driver functionality overview: - * - one lower-half driver for all STM32 ADC IP cores, - * - general lower-half logic for the NuttX upper-half ADC driver, - * - lower-half ADC driver can be used not only with the upper-half ADC - * driver, but also in the lower-half logic for special-case custom - * drivers (eg. power-control, custom sensors), - * - ADC can be used in time-critical operations (eg. control loop for - * converters or motor drivers) therefore it is necessary to support the - * high performance, zero latency ADC interrupts, - * - ADC triggering from different sources (EXTSEL and JEXTSEL), - * - regular sequence conversion (supported in upper-half ADC driver) - * - injected sequence conversion (not supported in upper-half ADC driver) - */ - -/* STM32 ADC "lower-half" support must be enabled */ - -#ifdef CONFIG_STM32_ADC - -/* This implementation is for the STM32 ADC IP version 1 and 2 */ - -#if !defined(HAVE_IP_ADC_V1) && !defined(HAVE_IP_ADC_V2) -# error "STM32 ADC IP version not specified" -#endif - -/* Supported ADC modes: - * - SW triggering with/without DMA transfer - * - TIM triggering with/without DMA transfer - * - external triggering with/without DMA transfer - * - * (tested with ADC example app from NuttX apps repo). - */ - -/* At the moment there is no proper implementation for timers external - * trigger in STM32L15XX may be added later - */ - -#if defined(ADC_HAVE_TIMER) && defined(CONFIG_STM32_STM32L15XX) -# warning "There is no proper implementation for TIMER TRIGGERS at the moment" -#endif - -/* If ADC use HSI as clock-source and HSI is not used for PLL and system - * clock, then we can control it directly from ADC driver. - */ - -#if defined(HAVE_ADC_CLOCK_HSI) && \ - (STM32_CFGR_PLLSRC != 0 || STM32_SYSCLK_SW != RCC_CFGR_SW_HSI) -# define HAVE_HSI_CONTROL -#endif - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* RCC reset ****************************************************************/ - -#if defined(HAVE_IP_ADC_V1) -# ifdef HAVE_BASIC_ADC -# define STM32_RCC_RSTR STM32_RCC_APB2RSTR -# define RCC_RSTR_ADC1RST RCC_APB2RSTR_ADC1RST -# define RCC_RSTR_ADC2RST RCC_APB2RSTR_ADC2RST -# define RCC_RSTR_ADC3RST RCC_APB2RSTR_ADC3RST -# else -# define STM32_RCC_RSTR STM32_RCC_APB2RSTR -# define RCC_RSTR_ADC123RST RCC_APB2RSTR_ADCRST -# endif -#elif defined(HAVE_IP_ADC_V2) -# ifdef STM32_RCC_AHB2RSTR_OFFSET -# define STM32_RCC_RSTR STM32_RCC_AHB2RSTR -# define RCC_RSTR_ADC12RST RCC_AHB2RSTR_ADC12RST -# define RCC_RSTR_ADC34RST RCC_AHB2RSTR_ADC345RST -# else -# define STM32_RCC_RSTR STM32_RCC_AHBRSTR -# define RCC_RSTR_ADC12RST RCC_AHBRSTR_ADC12RST -# define RCC_RSTR_ADC34RST RCC_AHBRSTR_ADC34RST -# endif -#endif - -/* ADC Channels/DMA *********************************************************/ - -/* DMA values differs according to STM32 DMA IP core version */ - -#if defined(HAVE_IP_DMA_V2) -# define ADC_DMA_CONTROL_WORD (DMA_SCR_MSIZE_16BITS | \ - DMA_SCR_PSIZE_16BITS | \ - DMA_SCR_MINC | \ - DMA_SCR_CIRC | \ - DMA_SCR_DIR_P2M) -#elif defined(HAVE_IP_DMA_V1) -# define ADC_DMA_CONTROL_WORD (DMA_CCR_MSIZE_16BITS | \ - DMA_CCR_PSIZE_16BITS | \ - DMA_CCR_MINC | \ - DMA_CCR_CIRC) -#endif - -/* Sample time default configuration - * - * REVISIT: simplify this, use adc_sampletime_write() function. - * REVISIT: default SMPR configurable from Kconfig - */ - -#if defined(CONFIG_STM32_STM32F10XX) -# define ADC_SMPR_DEFAULT ADC_SMPR_55p5 -# define ADC_SMPR1_DEFAULT ((ADC_SMPR_DEFAULT << ADC_SMPR1_SMP10_SHIFT) | \ - (ADC_SMPR_DEFAULT << ADC_SMPR1_SMP11_SHIFT) | \ - (ADC_SMPR_DEFAULT << ADC_SMPR1_SMP12_SHIFT) | \ - (ADC_SMPR_DEFAULT << ADC_SMPR1_SMP13_SHIFT) | \ - (ADC_SMPR_DEFAULT << ADC_SMPR1_SMP14_SHIFT) | \ - (ADC_SMPR_DEFAULT << ADC_SMPR1_SMP15_SHIFT) | \ - (ADC_SMPR_DEFAULT << ADC_SMPR1_SMP16_SHIFT) | \ - (ADC_SMPR_DEFAULT << ADC_SMPR1_SMP17_SHIFT)) -# define ADC_SMPR2_DEFAULT ((ADC_SMPR_DEFAULT << ADC_SMPR2_SMP0_SHIFT) | \ - (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP1_SHIFT) | \ - (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP2_SHIFT) | \ - (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP3_SHIFT) | \ - (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP4_SHIFT) | \ - (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP5_SHIFT) | \ - (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP6_SHIFT) | \ - (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP7_SHIFT) | \ - (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP8_SHIFT) | \ - (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP9_SHIFT)) -#elif defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) -# if defined(ADC_HAVE_DMA) || (CONFIG_STM32_ADC_MAX_SAMPLES == 1) -# define ADC_SMPR_DEFAULT ADC_SMPR_61p5 -# else /* Slow down sampling frequency */ -# define ADC_SMPR_DEFAULT ADC_SMPR_601p5 -# endif -# define ADC_SMPR1_DEFAULT ((ADC_SMPR_DEFAULT << ADC_SMPR1_SMP1_SHIFT) | \ - (ADC_SMPR_DEFAULT << ADC_SMPR1_SMP2_SHIFT) | \ - (ADC_SMPR_DEFAULT << ADC_SMPR1_SMP3_SHIFT) | \ - (ADC_SMPR_DEFAULT << ADC_SMPR1_SMP4_SHIFT) | \ - (ADC_SMPR_DEFAULT << ADC_SMPR1_SMP5_SHIFT) | \ - (ADC_SMPR_DEFAULT << ADC_SMPR1_SMP6_SHIFT) | \ - (ADC_SMPR_DEFAULT << ADC_SMPR1_SMP7_SHIFT) | \ - (ADC_SMPR_DEFAULT << ADC_SMPR1_SMP8_SHIFT) | \ - (ADC_SMPR_DEFAULT << ADC_SMPR1_SMP9_SHIFT)) -# define ADC_SMPR2_DEFAULT ((ADC_SMPR_DEFAULT << ADC_SMPR2_SMP10_SHIFT) | \ - (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP11_SHIFT) | \ - (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP12_SHIFT) | \ - (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP13_SHIFT) | \ - (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP14_SHIFT) | \ - (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP15_SHIFT) | \ - (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP16_SHIFT) | \ - (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP17_SHIFT) | \ - (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP18_SHIFT)) -#elif defined(CONFIG_STM32_STM32G4XXX) -# if defined(ADC_HAVE_DMA) || (CONFIG_STM32_ADC_MAX_SAMPLES == 1) -# define ADC_SMPR_DEFAULT ADC_SMPR_47p5 -# else /* Slow down sampling frequency */ -# define ADC_SMPR_DEFAULT ADC_SMPR_640p5 -# endif -# define ADC_SMPR1_DEFAULT ((ADC_SMPR_DEFAULT << ADC_SMPR1_SMP0_SHIFT) | \ - (ADC_SMPR_DEFAULT << ADC_SMPR1_SMP1_SHIFT) | \ - (ADC_SMPR_DEFAULT << ADC_SMPR1_SMP2_SHIFT) | \ - (ADC_SMPR_DEFAULT << ADC_SMPR1_SMP3_SHIFT) | \ - (ADC_SMPR_DEFAULT << ADC_SMPR1_SMP4_SHIFT) | \ - (ADC_SMPR_DEFAULT << ADC_SMPR1_SMP5_SHIFT) | \ - (ADC_SMPR_DEFAULT << ADC_SMPR1_SMP6_SHIFT) | \ - (ADC_SMPR_DEFAULT << ADC_SMPR1_SMP7_SHIFT) | \ - (ADC_SMPR_DEFAULT << ADC_SMPR1_SMP8_SHIFT) | \ - (ADC_SMPR_DEFAULT << ADC_SMPR1_SMP9_SHIFT)) -# define ADC_SMPR2_DEFAULT ((ADC_SMPR_DEFAULT << ADC_SMPR2_SMP10_SHIFT) | \ - (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP11_SHIFT) | \ - (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP12_SHIFT) | \ - (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP13_SHIFT) | \ - (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP14_SHIFT) | \ - (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP15_SHIFT) | \ - (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP16_SHIFT) | \ - (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP17_SHIFT) | \ - (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP18_SHIFT)) -#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F37XX) || \ - defined(CONFIG_STM32_STM32F4XXX) -# if defined(CONFIG_STM32_STM32F37XX) -# define ADC_SMPR_DEFAULT ADC_SMPR_239p5 /* TODO choose 1p5? */ -# else -# define ADC_SMPR_DEFAULT ADC_SMPR_112 -# endif -# define ADC_SMPR1_DEFAULT ((ADC_SMPR_DEFAULT << ADC_SMPR1_SMP10_SHIFT) | \ - (ADC_SMPR_DEFAULT << ADC_SMPR1_SMP11_SHIFT) | \ - (ADC_SMPR_DEFAULT << ADC_SMPR1_SMP12_SHIFT) | \ - (ADC_SMPR_DEFAULT << ADC_SMPR1_SMP13_SHIFT) | \ - (ADC_SMPR_DEFAULT << ADC_SMPR1_SMP14_SHIFT) | \ - (ADC_SMPR_DEFAULT << ADC_SMPR1_SMP15_SHIFT) | \ - (ADC_SMPR_DEFAULT << ADC_SMPR1_SMP16_SHIFT) | \ - (ADC_SMPR_DEFAULT << ADC_SMPR1_SMP17_SHIFT) | \ - (ADC_SMPR_DEFAULT << ADC_SMPR1_SMP18_SHIFT)) -# define ADC_SMPR2_DEFAULT ((ADC_SMPR_DEFAULT << ADC_SMPR2_SMP0_SHIFT) | \ - (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP1_SHIFT) | \ - (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP2_SHIFT) | \ - (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP3_SHIFT) | \ - (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP4_SHIFT) | \ - (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP5_SHIFT) | \ - (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP6_SHIFT) | \ - (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP7_SHIFT) | \ - (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP8_SHIFT) | \ - (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP9_SHIFT)) -#elif defined(CONFIG_STM32_STM32L15XX) -# define ADC_SMPR_DEFAULT ADC_SMPR_384 -# define ADC_SMPR1_DEFAULT ((ADC_SMPR_DEFAULT << ADC_SMPR1_SMP20_SHIFT) | \ - (ADC_SMPR_DEFAULT << ADC_SMPR1_SMP21_SHIFT) | \ - (ADC_SMPR_DEFAULT << ADC_SMPR1_SMP22_SHIFT) | \ - (ADC_SMPR_DEFAULT << ADC_SMPR1_SMP23_SHIFT) | \ - (ADC_SMPR_DEFAULT << ADC_SMPR1_SMP24_SHIFT) | \ - (ADC_SMPR_DEFAULT << ADC_SMPR1_SMP25_SHIFT) | \ - (ADC_SMPR_DEFAULT << ADC_SMPR1_SMP26_SHIFT) | \ - (ADC_SMPR_DEFAULT << ADC_SMPR1_SMP27_SHIFT) | \ - (ADC_SMPR_DEFAULT << ADC_SMPR1_SMP28_SHIFT) | \ - (ADC_SMPR_DEFAULT << ADC_SMPR1_SMP29_SHIFT)) -# define ADC_SMPR2_DEFAULT ((ADC_SMPR_DEFAULT << ADC_SMPR2_SMP10_SHIFT) | \ - (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP11_SHIFT) | \ - (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP12_SHIFT) | \ - (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP13_SHIFT) | \ - (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP14_SHIFT) | \ - (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP15_SHIFT) | \ - (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP16_SHIFT) | \ - (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP17_SHIFT) | \ - (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP18_SHIFT) | \ - (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP19_SHIFT)) -# define ADC_SMPR3_DEFAULT ((ADC_SMPR_DEFAULT << ADC_SMPR3_SMP0_SHIFT) | \ - (ADC_SMPR_DEFAULT << ADC_SMPR3_SMP1_SHIFT) | \ - (ADC_SMPR_DEFAULT << ADC_SMPR3_SMP2_SHIFT) | \ - (ADC_SMPR_DEFAULT << ADC_SMPR3_SMP3_SHIFT) | \ - (ADC_SMPR_DEFAULT << ADC_SMPR3_SMP4_SHIFT) | \ - (ADC_SMPR_DEFAULT << ADC_SMPR3_SMP5_SHIFT) | \ - (ADC_SMPR_DEFAULT << ADC_SMPR3_SMP6_SHIFT) | \ - (ADC_SMPR_DEFAULT << ADC_SMPR3_SMP7_SHIFT) | \ - (ADC_SMPR_DEFAULT << ADC_SMPR3_SMP8_SHIFT) | \ - (ADC_SMPR_DEFAULT << ADC_SMPR3_SMP9_SHIFT)) -# define ADC_SMPR0_DEFAULT ((ADC_SMPR_DEFAULT << ADC_SMPR0_SMP30_SHIFT) | \ - (ADC_SMPR_DEFAULT << ADC_SMPR0_SMP31_SHIFT)) -#endif - -/* Number of channels per ADC: - * - F0, L0 - 19, but single SMP for all channels - * - F1 - 18 - * - F2,F3,F4,F7,L4,L4+ - 19 - * - H7 - 20 - * - L1 - 32 - * - * NOTE: this value can be obtained from SMPRx register description - * (ST manual) - */ - -#if defined(CONFIG_STM32_STM32F10XX) -# define ADC_CHANNELS_NUMBER 18 -#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F30XX) || \ - defined(CONFIG_STM32_STM32F33XX) || defined(CONFIG_STM32_STM32F4XXX) || \ - defined(CONFIG_STM32_STM32G4XXX) -# define ADC_CHANNELS_NUMBER 19 -#elif defined(CONFIG_STM32_STM32L15XX) -# define ADC_CHANNELS_NUMBER 32 -#else -# error "Not supported" -#endif - -/* ADC resolution. Not supported for basic STM32 ADC IPv1 */ - -#ifndef CONFIG_STM32_HAVE_IP_ADC_V1_BASIC -# define HAVE_ADC_RESOLUTION -#else -# undef HAVE_ADC_RESOLUTION -#endif - -/* ADC have common registers for all cores except basic ADC IPv1 (F1, F37x) */ - -#ifdef CONFIG_STM32_HAVE_IP_ADC_V1_BASIC -# undef HAVE_ADC_CMN_REGS -#else -# define HAVE_ADC_CMN_REGS -#endif -#if defined(HAVE_ADC_CMN_REGS) && STM32_NADC > 1 -# define HAVE_ADC_CMN_DATA -#else -# undef HAVE_ADC_CMN_DATA -#endif - -/* Max 4 injected channels */ - -#define ADC_INJ_MAX_SAMPLES 4 - -/* ADC DMA configuration bit support */ - -#ifndef CONFIG_STM32_HAVE_IP_ADC_V1_BASIC -# define ADC_HAVE_DMACFG 1 -#else -# undef ADC_HAVE_DMACFG -#endif - -/* ADC scan mode support - only for ADCv1 */ - -#ifdef CONFIG_STM32_HAVE_IP_ADC_V1 -# define ADC_HAVE_SCAN 1 -# ifndef CONFIG_STM32_ADC1_SCAN -# define CONFIG_STM32_ADC1_SCAN 0 -# endif -# ifndef CONFIG_STM32_ADC2_SCAN -# define CONFIG_STM32_ADC2_SCAN 0 -# endif -# ifndef CONFIG_STM32_ADC3_SCAN -# define CONFIG_STM32_ADC3_SCAN 0 -# endif -#else -# undef ADC_HAVE_SCAN -#endif - -/* We have to support ADC callbacks if default ADC interrupts or - * DMA transfer are enabled - */ - -#if !defined(CONFIG_STM32_ADC_NOIRQ) || defined(ADC_HAVE_DMA) -# define ADC_HAVE_CB -#else -# undef ADC_HAVE_CB -#endif - -/* ADC software trigger configuration */ - -#define ANIOC_TRIGGER_REGULAR (1 << 0) -#define ANIOC_TRIGGER_INJECTED (1 << 1) - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/* Data common to all ADC instances */ - -#ifdef HAVE_ADC_CMN_DATA -struct adccmn_data_s -{ - uint8_t refcount; /* How many ADC instances are currently in use */ - mutex_t lock; /* Exclusive access to common ADC data */ -}; -#endif - -/* This structure describes the state of one ADC block - * REVISIT: save some space with bit fields. - */ - -struct stm32_dev_s -{ -#ifdef CONFIG_STM32_ADC_LL_OPS - const struct stm32_adc_ops_s *llops; /* Low-level ADC ops */ - struct adc_dev_s *dev; /* Upper-half ADC reference */ -#endif -#ifdef ADC_HAVE_CB - const struct adc_callback_s *cb; - uint8_t irq; /* Interrupt generated by this ADC block */ -#endif -#ifdef HAVE_ADC_CMN_DATA - struct adccmn_data_s *cmn; /* Common ADC data */ -#endif - uint8_t rnchannels; /* Number of regular channels */ - uint8_t cr_channels; /* Number of configured regular channels */ -#ifdef ADC_HAVE_INJECTED - uint8_t cj_channels; /* Number of configured injected channels */ -#endif - uint8_t intf; /* ADC interface number */ - uint8_t initialized; /* ADC interface initialization counter */ - uint8_t current; /* Current ADC channel being converted */ - uint8_t anioc_trg; /* ANIOC_TRIGGER configuration */ -#ifdef HAVE_ADC_RESOLUTION - uint8_t resolution; /* ADC resolution (0-3) */ -#endif -#ifdef ADC_HAVE_DMA - uint8_t dmachan; /* DMA channel needed by this ADC */ -# ifdef ADC_HAVE_DMACFG - uint8_t dmacfg; /* DMA channel configuration, only for ADC IPv2 */ -# endif - bool hasdma; /* True: This channel supports DMA */ - uint16_t dmabatch; /* Number of conversions for DMA batch */ -#endif -#ifdef ADC_HAVE_SCAN - bool scan; /* True: Scan mode */ -#endif -#ifdef CONFIG_STM32_ADC_CHANGE_SAMPLETIME - /* Sample time selection. These bits must be written only when ADON=0. - * REVISIT: this takes too much space. We need only 3 bits per channel. - */ - - uint8_t sample_rate[ADC_CHANNELS_NUMBER]; - uint8_t adc_channels; /* ADC channels number */ -#endif -#ifdef ADC_HAVE_TIMER - uint8_t trigger; /* Timer trigger channel: 0=CC1, 1=CC2, 2=CC3, - * 3=CC4, 4=TRGO, 5=TRGO2 - */ -#endif - xcpt_t isr; /* Interrupt handler for this ADC block */ - uint32_t base; /* Base address of registers unique to this ADC - * block */ -#ifdef ADC_HAVE_EXTCFG - uint32_t extcfg; /* External event configuration for regular group */ -#endif -#ifdef ADC_HAVE_JEXTCFG - uint32_t jextcfg; /* External event configuration for injected group */ -#endif -#ifdef ADC_HAVE_TIMER - uint32_t tbase; /* Base address of timer used by this ADC block */ - uint32_t pclck; /* The PCLK frequency that drives this timer */ - uint32_t freq; /* The desired frequency of conversions */ -#endif -#ifdef ADC_HAVE_DMA - DMA_HANDLE dma; /* Allocated DMA channel */ - - /* DMA transfer buffer */ - - uint16_t *r_dmabuffer; -#endif - - /* List of selected ADC channels to sample */ - - uint8_t r_chanlist[CONFIG_STM32_ADC_MAX_SAMPLES]; - -#ifdef ADC_HAVE_INJECTED - /* List of selected ADC injected channels to sample */ - - uint8_t j_chanlist[ADC_INJ_MAX_SAMPLES]; -#endif -}; - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -/* ADC Register access */ - -#ifndef HAVE_BASIC_ADC -static void stm32_modifyreg32(unsigned int addr, uint32_t clrbits, - uint32_t setbits); -#endif -static uint32_t adc_getreg(struct stm32_dev_s *priv, int offset); -static void adc_putreg(struct stm32_dev_s *priv, int offset, - uint32_t value); -static void adc_modifyreg(struct stm32_dev_s *priv, int offset, - uint32_t clrbits, uint32_t setbits); -#ifdef HAVE_ADC_CMN_REGS -static uint32_t adccmn_base_get(struct stm32_dev_s *priv); -static void adccmn_modifyreg(struct stm32_dev_s *priv, uint32_t offset, - uint32_t clrbits, uint32_t setbits); -static uint32_t adccmn_getreg(struct stm32_dev_s *priv, uint32_t offset); -#endif -#ifdef ADC_HAVE_TIMER -static uint16_t tim_getreg(struct stm32_dev_s *priv, int offset); -static void tim_putreg(struct stm32_dev_s *priv, int offset, - uint16_t value); -static void tim_modifyreg(struct stm32_dev_s *priv, int offset, - uint16_t clrbits, uint16_t setbits); -#ifdef HAVE_IP_TIMERS_V2 -static void tim_modifyreg32(struct stm32_dev_s *priv, int offset, - uint32_t clrbits, uint32_t setbits); -#endif -static void tim_dumpregs(struct stm32_dev_s *priv, const char *msg); -#endif - -static void adc_rccreset(struct stm32_dev_s *priv, bool reset); - -/* ADC Interrupt Handler */ - -#ifndef CONFIG_STM32_ADC_NOIRQ -static int adc_interrupt(struct adc_dev_s *dev); -# if defined(STM32_IRQ_ADC1) && defined(CONFIG_STM32_ADC1) -static int adc1_interrupt(int irq, void *context, void *arg); -# endif -# if defined(STM32_IRQ_ADC12) && (defined(CONFIG_STM32_ADC1) || \ - defined(CONFIG_STM32_ADC2)) -static int adc12_interrupt(int irq, void *context, void *arg); -# endif -# if (defined(STM32_IRQ_ADC3) && defined(CONFIG_STM32_ADC3)) -static int adc3_interrupt(int irq, void *context, void *arg); -# endif -# if defined(STM32_IRQ_ADC4) && defined(CONFIG_STM32_ADC4) -static int adc4_interrupt(int irq, void *context, void *arg); -# endif -# if defined(STM32_IRQ_ADC) -static int adc123_interrupt(int irq, void *context, void *arg); -# endif -#endif /* CONFIG_STM32_ADC_NOIRQ */ - -/* ADC Driver Methods */ - -static int adc_bind(struct adc_dev_s *dev, - const struct adc_callback_s *callback); -static void adc_reset(struct adc_dev_s *dev); -static int adc_setup(struct adc_dev_s *dev); -static void adc_shutdown(struct adc_dev_s *dev); -static void adc_rxint(struct adc_dev_s *dev, bool enable); -static int adc_ioctl(struct adc_dev_s *dev, int cmd, unsigned long arg); -static void adc_enable(struct stm32_dev_s *priv, bool enable); - -static uint32_t adc_sqrbits(struct stm32_dev_s *priv, int first, - int last, int offset); -static int adc_set_ch(struct adc_dev_s *dev, uint8_t ch); - -static int adc_ioc_change_ints(struct adc_dev_s *dev, int cmd, - bool arg); - -#ifdef HAVE_ADC_RESOLUTION -static int adc_resolution_set(struct adc_dev_s *dev, uint8_t res); -#endif -#ifdef HAVE_ADC_VBAT -static void adc_enable_vbat_channel(struct adc_dev_s *dev, bool enable); -#endif -#ifdef HAVE_ADC_POWERDOWN -static int adc_ioc_change_sleep_between_opers(struct adc_dev_s *dev, - int cmd, bool arg); -static void adc_power_down_idle(struct stm32_dev_s *priv, - bool pdi_high); -static void adc_power_down_delay(struct stm32_dev_s *priv, - bool pdd_high); -#endif - -#ifdef CONFIG_STM32_STM32L15XX -static void adc_dels_after_conversion(struct stm32_dev_s *priv, - uint32_t delay); -static void adc_select_ch_bank(struct stm32_dev_s *priv, - bool chb_selected); -#endif - -#ifdef HAVE_HSI_CONTROL -static void adc_enable_hsi(bool enable); -static void adc_reset_hsi_disable(struct adc_dev_s *dev); -#endif - -#ifdef ADC_HAVE_TIMER -static void adc_timstart(struct stm32_dev_s *priv, bool enable); -static int adc_timinit(struct stm32_dev_s *priv); -#endif - -#if defined(ADC_HAVE_DMA) && !defined(CONFIG_STM32_ADC_NOIRQ) -static void adc_dmaconvcallback(DMA_HANDLE handle, uint8_t isr, - void *arg); -#endif - -static void adc_reg_startconv(struct stm32_dev_s *priv, bool enable); -#ifdef ADC_HAVE_INJECTED -static void adc_inj_startconv(struct stm32_dev_s *priv, bool enable); -static int adc_inj_set_ch(struct adc_dev_s *dev, uint8_t ch); -#endif - -#ifdef ADC_HAVE_EXTCFG -static int adc_extcfg_set(struct stm32_dev_s *priv, uint32_t extcfg); -#endif -#ifdef ADC_HAVE_JEXTCFG -static int adc_jextcfg_set(struct stm32_dev_s *priv, uint32_t jextcfg); -#endif - -static void adc_dumpregs(struct stm32_dev_s *priv); - -#ifdef CONFIG_STM32_ADC_LL_OPS -static int adc_llops_setup(struct stm32_adc_dev_s *dev); -static void adc_llops_shutdown(struct stm32_adc_dev_s *dev); -static void adc_intack(struct stm32_adc_dev_s *dev, uint32_t source); -static void adc_inten(struct stm32_adc_dev_s *dev, uint32_t source); -static void adc_intdis(struct stm32_adc_dev_s *dev, uint32_t source); -static uint32_t adc_intget(struct stm32_adc_dev_s *dev); -static uint32_t adc_regget(struct stm32_adc_dev_s *dev); -static void adc_llops_reg_startconv(struct stm32_adc_dev_s *dev, - bool enable); -static int adc_offset_set(struct stm32_adc_dev_s *dev, uint8_t ch, - uint8_t i, uint16_t offset); -# ifdef ADC_HAVE_EXTCFG -static void adc_llops_extcfg_set(struct stm32_adc_dev_s *dev, - uint32_t extcfg); -# endif -# ifdef ADC_HAVE_JEXTCFG -static void adc_llops_jextcfg_set(struct stm32_adc_dev_s *dev, - uint32_t jextcfg); -# endif -# ifdef ADC_HAVE_DMA -static int adc_regbufregister(struct stm32_adc_dev_s *dev, - uint16_t *buffer, uint8_t len); -# endif -# ifdef ADC_HAVE_INJECTED -static uint32_t adc_injget(struct stm32_adc_dev_s *dev, uint8_t chan); -static void adc_llops_inj_startconv(struct stm32_adc_dev_s *dev, - bool enable); -# endif -# ifdef CONFIG_STM32_ADC_CHANGE_SAMPLETIME -static void adc_sampletime_set(struct stm32_adc_dev_s *dev, - struct adc_sample_time_s *time_samples); -static void adc_sampletime_write(struct stm32_adc_dev_s *dev); -# endif -static void adc_llops_dumpregs(struct stm32_adc_dev_s *dev); -static int adc_llops_multicfg(struct stm32_adc_dev_s *dev, uint8_t mode); -static void adc_llops_enable(struct stm32_adc_dev_s *dev, bool enable); -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* ADC interface operations */ - -static const struct adc_ops_s g_adcops = -{ - .ao_bind = adc_bind, -#ifdef HAVE_HSI_CONTROL - .ao_reset = adc_reset_hsi_disable, -#else - .ao_reset = adc_reset, -#endif - .ao_setup = adc_setup, - .ao_shutdown = adc_shutdown, - .ao_rxint = adc_rxint, - .ao_ioctl = adc_ioctl, -}; - -/* Publicly visible ADC lower-half operations */ - -#ifdef CONFIG_STM32_ADC_LL_OPS -static const struct stm32_adc_ops_s g_adc_llops = -{ - .setup = adc_llops_setup, - .shutdown = adc_llops_shutdown, - .int_ack = adc_intack, - .int_get = adc_intget, - .int_en = adc_inten, - .int_dis = adc_intdis, - .val_get = adc_regget, - .reg_startconv = adc_llops_reg_startconv, - .offset_set = adc_offset_set, -# ifdef ADC_HAVE_DMA - .regbuf_reg = adc_regbufregister, -# endif -# ifdef ADC_HAVE_EXTCFG - .extcfg_set = adc_llops_extcfg_set, -# endif -# ifdef ADC_HAVE_JEXTCFG - .jextcfg_set = adc_llops_jextcfg_set, -# endif -# ifdef ADC_HAVE_INJECTED - .inj_get = adc_injget, - .inj_startconv = adc_llops_inj_startconv, -# endif -# ifdef CONFIG_STM32_ADC_CHANGE_SAMPLETIME - .stime_set = adc_sampletime_set, - .stime_write = adc_sampletime_write, -# endif - .dump_regs = adc_llops_dumpregs, - .multi_cfg = adc_llops_multicfg, - .enable = adc_llops_enable -}; -#endif - -/* ADC instances are coupled in blocks for all IP versions except - * basic ADC IPv1 (F1, F37x). - */ - -#ifdef HAVE_ADC_CMN_DATA -# ifdef HAVE_IP_ADC_V1 -# define ADC1CMN_DATA g_adc123_cmn -# define ADC2CMN_DATA g_adc123_cmn -# define ADC3CMN_DATA g_adc123_cmn - -/* ADC123 common data */ - -struct adccmn_data_s g_adc123_cmn = -{ - .refcount = 0, - .lock = NXMUTEX_INITIALIZER, -}; - -# elif defined(HAVE_IP_ADC_V2) -# define ADC1CMN_DATA g_adc12_cmn -# define ADC2CMN_DATA g_adc12_cmn -# define ADC3CMN_DATA g_adc34_cmn -# define ADC4CMN_DATA g_adc34_cmn -# if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) - -/* ADC12 common data */ - -struct adccmn_data_s g_adc12_cmn = -{ - .refcount = 0, - .lock = NXMUTEX_INITIALIZER, -}; - -# endif -# if defined(CONFIG_STM32_ADC3) || defined(CONFIG_STM32_ADC4) - -/* ADC34 common data */ - -struct adccmn_data_s g_adc34_cmn = -{ - .refcount = 0, - .lock = NXMUTEX_INITIALIZER, -}; - -# endif -# endif /* !HAVE_IP_ADC_V1 */ -#endif /* HAVE_ADC_CMN_DATA */ - -/* ADC1 state */ - -#ifdef CONFIG_STM32_ADC1 - -#ifdef ADC1_HAVE_DMA -static uint16_t g_adc1_dmabuffer[CONFIG_STM32_ADC_MAX_SAMPLES * - CONFIG_STM32_ADC1_DMA_BATCH]; -#endif - -static struct stm32_dev_s g_adcpriv1 = -{ -#ifdef CONFIG_STM32_ADC_LL_OPS - .llops = &g_adc_llops, -#endif -#ifndef CONFIG_STM32_ADC_NOIRQ -# if defined(STM32_IRQ_ADC1) - .irq = STM32_IRQ_ADC1, - .isr = adc1_interrupt, -# elif defined(STM32_IRQ_ADC12) - .irq = STM32_IRQ_ADC12, - .isr = adc12_interrupt, -# elif defined(STM32_IRQ_ADC) - .irq = STM32_IRQ_ADC, - .isr = adc123_interrupt, -# else -# error "No STM32_IRQ_ADC1 STM32_IRQ_ADC12 or STM32_IRQ_ADC defined for CONFIG_STM32_ADC1" -# endif -#endif /* CONFIG_STM32_ADC_NOIRQ */ -#ifdef HAVE_ADC_CMN_DATA - .cmn = &ADC1CMN_DATA, -#endif - .intf = 1, - .initialized = 0, - .anioc_trg = CONFIG_STM32_ADC1_ANIOC_TRIGGER, -#ifdef HAVE_ADC_RESOLUTION - .resolution = CONFIG_STM32_ADC1_RESOLUTION, -#endif - .base = STM32_ADC1_BASE, -#ifdef ADC1_HAVE_EXTCFG - .extcfg = ADC1_EXTCFG_VALUE, -#endif -#ifdef ADC1_HAVE_JEXTCFG - .jextcfg = ADC1_JEXTCFG_VALUE, -#endif -#ifdef ADC1_HAVE_TIMER - .trigger = CONFIG_STM32_ADC1_TIMTRIG, - .tbase = ADC1_TIMER_BASE, - .pclck = ADC1_TIMER_PCLK_FREQUENCY, - .freq = CONFIG_STM32_ADC1_SAMPLE_FREQUENCY, -#endif -#ifdef ADC1_HAVE_DMA - .dmachan = ADC1_DMA_CHAN, -# ifdef ADC_HAVE_DMACFG - .dmacfg = CONFIG_STM32_ADC1_DMA_CFG, -# endif - .hasdma = true, - .r_dmabuffer = g_adc1_dmabuffer, - .dmabatch = CONFIG_STM32_ADC1_DMA_BATCH, -#endif -#ifdef ADC_HAVE_SCAN - .scan = CONFIG_STM32_ADC1_SCAN, -#endif -}; - -static struct adc_dev_s g_adcdev1 = -{ - .ad_ops = &g_adcops, - .ad_priv = &g_adcpriv1, -}; -#endif - -/* ADC2 state */ - -#ifdef CONFIG_STM32_ADC2 - -#ifdef ADC2_HAVE_DMA -static uint16_t g_adc2_dmabuffer[CONFIG_STM32_ADC_MAX_SAMPLES * - CONFIG_STM32_ADC2_DMA_BATCH]; -#endif - -static struct stm32_dev_s g_adcpriv2 = -{ -#ifdef CONFIG_STM32_ADC_LL_OPS - .llops = &g_adc_llops, -#endif -#ifndef CONFIG_STM32_ADC_NOIRQ -# if defined(STM32_IRQ_ADC12) - .irq = STM32_IRQ_ADC12, - .isr = adc12_interrupt, -# elif defined(STM32_IRQ_ADC) - .irq = STM32_IRQ_ADC, - .isr = adc123_interrupt, -# else -# error "No STM32_IRQ_ADC12 or STM32_IRQ_ADC defined for CONFIG_STM32_ADC2" -# endif -#endif /* CONFIG_STM32_ADC_NOIRQ */ -#ifdef HAVE_ADC_CMN_DATA - .cmn = &ADC2CMN_DATA, -#endif - .intf = 2, - .initialized = 0, - .anioc_trg = CONFIG_STM32_ADC2_ANIOC_TRIGGER, -#ifdef HAVE_ADC_RESOLUTION - .resolution = CONFIG_STM32_ADC2_RESOLUTION, -#endif - .base = STM32_ADC2_BASE, -#ifdef ADC2_HAVE_EXTCFG - .extcfg = ADC2_EXTCFG_VALUE, -#endif -#ifdef ADC2_HAVE_JEXTCFG - .jextcfg = ADC2_JEXTCFG_VALUE, -#endif -#ifdef ADC2_HAVE_TIMER - .trigger = CONFIG_STM32_ADC2_TIMTRIG, - .tbase = ADC2_TIMER_BASE, - .pclck = ADC2_TIMER_PCLK_FREQUENCY, - .freq = CONFIG_STM32_ADC2_SAMPLE_FREQUENCY, -#endif -#ifdef ADC2_HAVE_DMA - .dmachan = ADC2_DMA_CHAN, -# ifdef ADC_HAVE_DMACFG - .dmacfg = CONFIG_STM32_ADC2_DMA_CFG, -# endif - .hasdma = true, - .r_dmabuffer = g_adc2_dmabuffer, - .dmabatch = CONFIG_STM32_ADC2_DMA_BATCH, -#endif -#ifdef ADC_HAVE_SCAN - .scan = CONFIG_STM32_ADC2_SCAN, -#endif -}; - -static struct adc_dev_s g_adcdev2 = -{ - .ad_ops = &g_adcops, - .ad_priv = &g_adcpriv2, -}; -#endif - -/* ADC3 state */ - -#ifdef CONFIG_STM32_ADC3 - -#ifdef ADC3_HAVE_DMA -static uint16_t g_adc3_dmabuffer[CONFIG_STM32_ADC_MAX_SAMPLES * - CONFIG_STM32_ADC3_DMA_BATCH]; -#endif - -static struct stm32_dev_s g_adcpriv3 = -{ -#ifdef CONFIG_STM32_ADC_LL_OPS - .llops = &g_adc_llops, -#endif -#ifndef CONFIG_STM32_ADC_NOIRQ -# if defined(STM32_IRQ_ADC3) - .irq = STM32_IRQ_ADC3, - .isr = adc3_interrupt, -# elif defined(STM32_IRQ_ADC) - .irq = STM32_IRQ_ADC, - .isr = adc123_interrupt, -# else -# error "No STM32_IRQ_ADC3 or STM32_IRQ_ADC defined for CONFIG_STM32_ADC3" -# endif -#endif /* CONFIG_STM32_ADC_NOIRQ */ -#ifdef HAVE_ADC_CMN_DATA - .cmn = &ADC3CMN_DATA, -#endif - .intf = 3, - .initialized = 0, - .anioc_trg = CONFIG_STM32_ADC3_ANIOC_TRIGGER, -#ifdef HAVE_ADC_RESOLUTION - .resolution = CONFIG_STM32_ADC3_RESOLUTION, -#endif - .base = STM32_ADC3_BASE, -#ifdef ADC3_HAVE_EXTCFG - .extcfg = ADC3_EXTCFG_VALUE, -#endif -#ifdef ADC3_HAVE_JEXTCFG - .jextcfg = ADC3_JEXTCFG_VALUE, -#endif -#ifdef ADC3_HAVE_TIMER - .trigger = CONFIG_STM32_ADC3_TIMTRIG, - .tbase = ADC3_TIMER_BASE, - .pclck = ADC3_TIMER_PCLK_FREQUENCY, - .freq = CONFIG_STM32_ADC3_SAMPLE_FREQUENCY, -#endif -#ifdef ADC3_HAVE_DMA - .dmachan = ADC3_DMA_CHAN, -# ifdef ADC_HAVE_DMACFG - .dmacfg = CONFIG_STM32_ADC3_DMA_CFG, -# endif - .hasdma = true, - .r_dmabuffer = g_adc3_dmabuffer, - .dmabatch = CONFIG_STM32_ADC3_DMA_BATCH, -#endif -#ifdef ADC_HAVE_SCAN - .scan = CONFIG_STM32_ADC3_SCAN, -#endif -}; - -static struct adc_dev_s g_adcdev3 = -{ - .ad_ops = &g_adcops, - .ad_priv = &g_adcpriv3, -}; -#endif - -/* ADC4 state */ - -#ifdef CONFIG_STM32_ADC4 - -#ifdef ADC4_HAVE_DMA -static uint16_t g_adc4_dmabuffer[CONFIG_STM32_ADC_MAX_SAMPLES * - CONFIG_STM32_ADC4_DMA_BATCH]; -#endif - -static struct stm32_dev_s g_adcpriv4 = -{ -#ifdef CONFIG_STM32_ADC_LL_OPS - .llops = &g_adc_llops, -#endif -#ifndef CONFIG_STM32_ADC_NOIRQ - .irq = STM32_IRQ_ADC4, - .isr = adc4_interrupt, -#endif -#ifdef HAVE_ADC_CMN_DATA - .cmn = &ADC4CMN_DATA, -#endif - .intf = 4, - .initialized = 0, - .anioc_trg = CONFIG_STM32_ADC4_ANIOC_TRIGGER, -#ifdef HAVE_ADC_RESOLUTION - .resolution = CONFIG_STM32_ADC4_RESOLUTION, -#endif - .base = STM32_ADC4_BASE, -#ifdef ADC4_HAVE_EXTCFG - .extcfg = ADC4_EXTCFG_VALUE, -#endif -#ifdef ADC4_HAVE_JEXTCFG - .jextcfg = ADC4_JEXTCFG_VALUE, -#endif -#ifdef ADC4_HAVE_TIMER - .trigger = CONFIG_STM32_ADC4_TIMTRIG, - .tbase = ADC4_TIMER_BASE, - .pclck = ADC4_TIMER_PCLK_FREQUENCY, - .freq = CONFIG_STM32_ADC4_SAMPLE_FREQUENCY, -#endif -#ifdef ADC4_HAVE_DMA - .dmachan = ADC4_DMA_CHAN, -# ifdef ADC_HAVE_DMACFG - .dmacfg = CONFIG_STM32_ADC4_DMA_CFG, -# endif - .hasdma = true, - .r_dmabuffer = g_adc4_dmabuffer, - .dmabatch = CONFIG_STM32_ADC4_DMA_BATCH -#endif -}; - -static struct adc_dev_s g_adcdev4 = -{ - .ad_ops = &g_adcops, - .ad_priv = &g_adcpriv4, -}; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_modifyreg32 - * - * Description: - * Modify the value of a 32-bit register (not atomic). - * - * Input Parameters: - * addr - The address of the register - * clrbits - The bits to clear - * setbits - The bits to set - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifndef HAVE_BASIC_ADC -static void stm32_modifyreg32(unsigned int addr, uint32_t clrbits, - uint32_t setbits) -{ - putreg32((getreg32(addr) & ~clrbits) | setbits, addr); -} -#endif - -/**************************************************************************** - * Name: adc_getreg - * - * Description: - * Read the value of an ADC register. - * - * Input Parameters: - * priv - A reference to the ADC block status - * offset - The offset to the register to read - * - * Returned Value: - * The current contents of the specified register - * - ****************************************************************************/ - -static uint32_t adc_getreg(struct stm32_dev_s *priv, int offset) -{ - return getreg32(priv->base + offset); -} - -/**************************************************************************** - * Name: adc_putreg - * - * Description: - * Write a value to an ADC register. - * - * Input Parameters: - * priv - A reference to the ADC block status - * offset - The offset to the register to write to - * value - The value to write to the register - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void adc_putreg(struct stm32_dev_s *priv, int offset, - uint32_t value) -{ - putreg32(value, priv->base + offset); -} - -/**************************************************************************** - * Name: adc_modifyreg - * - * Description: - * Modify the value of an ADC register (not atomic). - * - * Input Parameters: - * priv - A reference to the ADC block status - * offset - The offset to the register to modify - * clrbits - The bits to clear - * setbits - The bits to set - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void adc_modifyreg(struct stm32_dev_s *priv, int offset, - uint32_t clrbits, uint32_t setbits) -{ - adc_putreg(priv, offset, (adc_getreg(priv, offset) & ~clrbits) | setbits); -} - -#ifdef HAVE_ADC_CMN_REGS - -/**************************************************************************** - * Name: adccmn_base_get - ****************************************************************************/ - -static uint32_t adccmn_base_get(struct stm32_dev_s *priv) -{ - uint32_t base = 0; - -#if defined(HAVE_IP_ADC_V2) - if (priv->base == STM32_ADC1_BASE || priv->base == STM32_ADC2_BASE) - { - base = STM32_ADC12CMN_BASE; - } -# if defined(CONFIG_STM32_ADC3) || defined(CONFIG_STM32_ADC4) - else - { - base = STM32_ADC34CMN_BASE; - } -# endif - -#elif defined(HAVE_IP_ADC_V1) - base = STM32_ADCCMN_BASE; - UNUSED(priv); -#endif - - return base; -} - -/**************************************************************************** - * Name: adccmn_modifyreg - ****************************************************************************/ - -static void adccmn_modifyreg(struct stm32_dev_s *priv, uint32_t offset, - uint32_t clrbits, uint32_t setbits) -{ - uint32_t base = 0; - - /* Get base address for ADC common register */ - - base = adccmn_base_get(priv); - - /* Modify register */ - - stm32_modifyreg32(offset + base, clrbits, setbits); -} - -/**************************************************************************** - * Name: adccmn_getreg - ****************************************************************************/ - -static uint32_t adccmn_getreg(struct stm32_dev_s *priv, uint32_t offset) -{ - uint32_t base = 0; - - /* Get base address for ADC common register */ - - base = adccmn_base_get(priv); - - /* Return register value */ - - return getreg32(base + offset); -} -#endif /* HAVE_ADC_CMN_REGS */ - -#ifdef ADC_HAVE_TIMER -/**************************************************************************** - * Name: tim_getreg - * - * Description: - * Read the value of an ADC timer register. - * - * Input Parameters: - * priv - A reference to the ADC block status - * offset - The offset to the register to read - * - * Returned Value: - * The current contents of the specified register - * - ****************************************************************************/ - -static uint16_t tim_getreg(struct stm32_dev_s *priv, int offset) -{ - return getreg16(priv->tbase + offset); -} - -/**************************************************************************** - * Name: tim_putreg - * - * Description: - * Write a value to an ADC timer register. - * - * Input Parameters: - * priv - A reference to the ADC block status - * offset - The offset to the register to write to - * value - The value to write to the register - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void tim_putreg(struct stm32_dev_s *priv, int offset, - uint16_t value) -{ - putreg16(value, priv->tbase + offset); -} - -/**************************************************************************** - * Name: tim_modifyreg - * - * Description: - * Modify the value of an ADC timer register (not atomic). - * - * Input Parameters: - * priv - A reference to the ADC block status - * offset - The offset to the register to modify - * clrbits - The bits to clear - * setbits - The bits to set - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void tim_modifyreg(struct stm32_dev_s *priv, int offset, - uint16_t clrbits, uint16_t setbits) -{ - tim_putreg(priv, offset, (tim_getreg(priv, offset) & ~clrbits) | setbits); -} - -#ifdef HAVE_IP_TIMERS_V2 -/**************************************************************************** - * Name: tim_modifyreg32 - * - * Description: - * Modify the value of an ADC timer register (not atomic). - * - * Input Parameters: - * priv - A reference to the ADC block status - * offset - The offset to the register to modify - * clrbits - The bits to clear - * setbits - The bits to set - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void tim_modifyreg32(struct stm32_dev_s *priv, int offset, - uint32_t clrbits, uint32_t setbits) -{ - uint32_t addr = priv->tbase + offset; - putreg32((getreg32(addr) & ~clrbits) | setbits, addr); -} -#endif - -/**************************************************************************** - * Name: tim_dumpregs - * - * Description: - * Dump all timer registers. - * - * Input Parameters: - * priv - A reference to the ADC block status - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void tim_dumpregs(struct stm32_dev_s *priv, const char *msg) -{ - ainfo("%s:\n", msg); - ainfo(" CR1: %04x CR2: %04x SMCR: %04x DIER: %04x\n", - tim_getreg(priv, STM32_GTIM_CR1_OFFSET), - tim_getreg(priv, STM32_GTIM_CR2_OFFSET), - tim_getreg(priv, STM32_GTIM_SMCR_OFFSET), - tim_getreg(priv, STM32_GTIM_DIER_OFFSET)); - ainfo(" SR: %04x EGR: 0000 CCMR1: %04x CCMR2: %04x\n", - tim_getreg(priv, STM32_GTIM_SR_OFFSET), - tim_getreg(priv, STM32_GTIM_CCMR1_OFFSET), - tim_getreg(priv, STM32_GTIM_CCMR2_OFFSET)); - ainfo(" CCER: %04x CNT: %04x PSC: %04x ARR: %04x\n", - tim_getreg(priv, STM32_GTIM_CCER_OFFSET), - tim_getreg(priv, STM32_GTIM_CNT_OFFSET), - tim_getreg(priv, STM32_GTIM_PSC_OFFSET), - tim_getreg(priv, STM32_GTIM_ARR_OFFSET)); - ainfo(" CCR1: %04x CCR2: %04x CCR3: %04x CCR4: %04x\n", - tim_getreg(priv, STM32_GTIM_CCR1_OFFSET), - tim_getreg(priv, STM32_GTIM_CCR2_OFFSET), - tim_getreg(priv, STM32_GTIM_CCR3_OFFSET), - tim_getreg(priv, STM32_GTIM_CCR4_OFFSET)); -#if STM32_NATIM > 0 - if (priv->tbase == STM32_TIM1_BASE -# ifdef STM32_TIM8_BASE - || priv->tbase == STM32_TIM8_BASE -# endif - ) - { - ainfo(" RCR: %04x BDTR: %04x DCR: %04x DMAR: %04x\n", - tim_getreg(priv, STM32_ATIM_RCR_OFFSET), - tim_getreg(priv, STM32_ATIM_BDTR_OFFSET), - tim_getreg(priv, STM32_ATIM_DCR_OFFSET), - tim_getreg(priv, STM32_ATIM_DMAR_OFFSET)); - } - else -#endif - { - ainfo(" DCR: %04x DMAR: %04x\n", - tim_getreg(priv, STM32_GTIM_DCR_OFFSET), - tim_getreg(priv, STM32_GTIM_DMAR_OFFSET)); - } -} - -/**************************************************************************** - * Name: adc_timstart - * - * Description: - * Start (or stop) the timer counter - * - * Input Parameters: - * priv - A reference to the ADC block status - * enable - True: Start conversion - * - * Returned Value: - * - ****************************************************************************/ - -static void adc_timstart(struct stm32_dev_s *priv, bool enable) -{ - ainfo("enable: %d\n", enable ? 1 : 0); - - if (enable) - { - /* Start the counter */ - - tim_modifyreg(priv, STM32_GTIM_CR1_OFFSET, 0, GTIM_CR1_CEN); - } - else - { - /* Disable the counter */ - - tim_modifyreg(priv, STM32_GTIM_CR1_OFFSET, GTIM_CR1_CEN, 0); - } -} - -/**************************************************************************** - * Name: adc_timinit - * - * Description: - * Initialize the timer that drivers the ADC sampling for this channel - * using the pre-calculated timer divider definitions. - * - * Input Parameters: - * priv - A reference to the ADC block status - * - * Returned Value: - * Zero on success; a negated errno value on failure. - * - ****************************************************************************/ - -static int adc_timinit(struct stm32_dev_s *priv) -{ - uint32_t prescaler; - uint32_t reload; - uint32_t timclk; - - uint16_t clrbits = 0; - uint16_t setbits = 0; - uint16_t cr2; - uint16_t ccmr1; - uint16_t ccmr2; - uint16_t ocmode1; - uint16_t ocmode2; - uint16_t ccenable; - uint16_t ccer; - uint16_t egr; - - /* If the timer base address is zero, then this ADC was not configured to - * use a timer. - */ - - if (priv->tbase == 0) - { - return ERROR; - } - - /* NOTE: EXTSEL configuration is done in adc_reset function */ - - /* Configure the timer channel to drive the ADC */ - - /* Calculate optimal values for the timer prescaler and for the timer - * reload register. If freq is the desired frequency, then - * - * reload = timclk / freq - * reload = (pclck / prescaler) / freq - * - * There are many solutions to do this, but the best solution will be the - * one that has the largest reload value and the smallest prescaler value. - * That is the solution that should give us the most accuracy in the timer - * control. Subject to: - * - * 0 <= prescaler <= 65536 - * 1 <= reload <= 65535 - * - * So (prescaler = pclck / 65535 / freq) would be optimal. - */ - - prescaler = (priv->pclck / priv->freq + 65534) / 65535; - - /* We need to decrement the prescaler value by one, but only, the value - * does not underflow. - */ - - if (prescaler < 1) - { - awarn("WARNING: Prescaler underflowed.\n"); - prescaler = 1; - } - - /* Check for overflow */ - - else if (prescaler > 65536) - { - awarn("WARNING: Prescaler overflowed.\n"); - prescaler = 65536; - } - - timclk = priv->pclck / prescaler; - - reload = timclk / priv->freq; - if (reload < 1) - { - awarn("WARNING: Reload value underflowed.\n"); - reload = 1; - } - else if (reload > 65535) - { - awarn("WARNING: Reload value overflowed.\n"); - reload = 65535; - } - - /* Disable the timer until we get it configured */ - - adc_timstart(priv, false); - - /* Set up the timer CR1 register. - * - * Select the Counter Mode == count up: - * - * ATIM_CR1_EDGE: The counter counts up or down depending on the - * direction bit(DIR). - * ATIM_CR1_DIR: 0: count up, 1: count down - * - * Set the clock division to zero for all - */ - - clrbits = GTIM_CR1_DIR | GTIM_CR1_CMS_MASK | GTIM_CR1_CKD_MASK; - setbits = GTIM_CR1_EDGE; - tim_modifyreg(priv, STM32_GTIM_CR1_OFFSET, clrbits, setbits); - - /* Set the reload and prescaler values */ - - tim_putreg(priv, STM32_GTIM_PSC_OFFSET, prescaler - 1); - tim_putreg(priv, STM32_GTIM_ARR_OFFSET, reload); - - /* Clear the advanced timers repetition counter in TIM1 */ - -#if STM32_NATIM > 0 - if (priv->tbase == STM32_TIM1_BASE -# ifdef STM32_TIM8_BASE - || priv->tbase == STM32_TIM8_BASE -# endif - ) - { - tim_putreg(priv, STM32_ATIM_RCR_OFFSET, 0); - tim_putreg(priv, STM32_ATIM_BDTR_OFFSET, ATIM_BDTR_MOE); /* Check me */ - } -#endif - - /* TIMx event generation: Bit 0 UG: Update generation */ - - tim_putreg(priv, STM32_GTIM_EGR_OFFSET, GTIM_EGR_UG); - - /* Handle channel specific setup */ - - ocmode1 = 0; - ocmode2 = 0; - - switch (priv->trigger) - { - case 0: /* TimerX CC1 event */ - { - ccenable = ATIM_CCER_CC1E; - ocmode1 = (ATIM_CCMR_CCS_CCOUT << ATIM_CCMR1_CC1S_SHIFT) | - (ATIM_CCMR_MODE_PWM1 << ATIM_CCMR1_OC1M_SHIFT) | - ATIM_CCMR1_OC1PE; - - /* Set the event CC1 */ - - egr = ATIM_EGR_CC1G; - - /* Set the duty cycle by writing to the CCR register for this - * channel - */ - - tim_putreg(priv, STM32_GTIM_CCR1_OFFSET, (uint16_t)(reload >> 1)); - } - break; - - case 1: /* TimerX CC2 event */ - { - ccenable = ATIM_CCER_CC2E; - ocmode1 = (ATIM_CCMR_CCS_CCOUT << ATIM_CCMR1_CC2S_SHIFT) | - (ATIM_CCMR_MODE_PWM1 << ATIM_CCMR1_OC2M_SHIFT) | - ATIM_CCMR1_OC2PE; - - /* Set the event CC2 */ - - egr = ATIM_EGR_CC2G; - - /* Set the duty cycle by writing to the CCR register for this - * channel - */ - - tim_putreg(priv, STM32_GTIM_CCR2_OFFSET, (uint16_t)(reload >> 1)); - } - break; - - case 2: /* TimerX CC3 event */ - { - ccenable = ATIM_CCER_CC3E; - ocmode2 = (ATIM_CCMR_CCS_CCOUT << ATIM_CCMR2_CC3S_SHIFT) | - (ATIM_CCMR_MODE_PWM1 << ATIM_CCMR2_OC3M_SHIFT) | - ATIM_CCMR2_OC3PE; - - /* Set the event CC3 */ - - egr = ATIM_EGR_CC3G; - - /* Set the duty cycle by writing to the CCR register for this - * channel - */ - - tim_putreg(priv, STM32_GTIM_CCR3_OFFSET, (uint16_t)(reload >> 1)); - } - break; - - case 3: /* TimerX CC4 event */ - { - ccenable = ATIM_CCER_CC4E; - ocmode2 = (ATIM_CCMR_CCS_CCOUT << ATIM_CCMR2_CC4S_SHIFT) | - (ATIM_CCMR_MODE_PWM1 << ATIM_CCMR2_OC4M_SHIFT) | - ATIM_CCMR2_OC4PE; - - /* Set the event CC4 */ - - egr = ATIM_EGR_CC4G; - - /* Set the duty cycle by writing to the CCR register for this - * channel - */ - - tim_putreg(priv, STM32_GTIM_CCR4_OFFSET, (uint16_t)(reload >> 1)); - } - break; - - case 4: /* TimerX TRGO event */ - { - /* Set the event TRGO */ - - ccenable = 0; - egr = GTIM_EGR_TG; - - tim_modifyreg(priv, STM32_GTIM_CR2_OFFSET, clrbits, - GTIM_CR2_MMS_UPDATE); - } - break; - -#ifdef HAVE_IP_TIMERS_V2 - case 5: /* TimerX TRGO2 event */ - { - /* Set the event TRGO2 */ - - ccenable = 0; - egr = GTIM_EGR_TG; - - tim_modifyreg32(priv, STM32_ATIM_CR2_OFFSET, clrbits, - ATIM_CR2_MMS2_UPDATE); - } - break; -#endif - - default: - aerr("ERROR: No such trigger: %d\n", priv->trigger); - return -EINVAL; - } - - /* Disable the Channel by resetting the CCxE Bit in the CCER register */ - - ccer = tim_getreg(priv, STM32_GTIM_CCER_OFFSET); - ccer &= ~ccenable; - tim_putreg(priv, STM32_GTIM_CCER_OFFSET, ccer); - - /* Fetch the CR2, CCMR1, and CCMR2 register (already have ccer) */ - - cr2 = tim_getreg(priv, STM32_GTIM_CR2_OFFSET); - ccmr1 = tim_getreg(priv, STM32_GTIM_CCMR1_OFFSET); - ccmr2 = tim_getreg(priv, STM32_GTIM_CCMR2_OFFSET); - - /* Reset the Output Compare Mode Bits and set the select output compare - * mode - */ - - ccmr1 &= ~(ATIM_CCMR1_CC1S_MASK | ATIM_CCMR1_OC1M_MASK | ATIM_CCMR1_OC1PE | - ATIM_CCMR1_CC2S_MASK | ATIM_CCMR1_OC2M_MASK | ATIM_CCMR1_OC2PE); - ccmr2 &= ~(ATIM_CCMR2_CC3S_MASK | ATIM_CCMR2_OC3M_MASK | ATIM_CCMR2_OC3PE | - ATIM_CCMR2_CC4S_MASK | ATIM_CCMR2_OC4M_MASK | ATIM_CCMR2_OC4PE); - ccmr1 |= ocmode1; - ccmr2 |= ocmode2; - - /* Reset the output polarity level of all channels (selects high - * polarity) - */ - - ccer &= ~(ATIM_CCER_CC1P | ATIM_CCER_CC2P | - ATIM_CCER_CC3P | ATIM_CCER_CC4P); - - /* Enable the output state of the selected channel (only) */ - - ccer &= ~(ATIM_CCER_CC1E | ATIM_CCER_CC2E | - ATIM_CCER_CC3E | ATIM_CCER_CC4E); - ccer |= ccenable; - - /* TODO: revisit and simplify logic below */ - -#if STM32_NATIM > 0 - if (priv->tbase == STM32_TIM1_BASE -# ifdef STM32_TIM8_BASE - || priv->tbase == STM32_TIM8_BASE -# endif - ) - { - /* Reset output N polarity level, output N state, output compare state, - * output compare N idle state. - */ - - ccer &= ~(ATIM_CCER_CC1NE | ATIM_CCER_CC1NP | - ATIM_CCER_CC2NE | ATIM_CCER_CC2NP | - ATIM_CCER_CC3NE | ATIM_CCER_CC3NP); - - /* Reset the output compare and output compare N IDLE State */ - - cr2 &= ~(ATIM_CR2_OIS1 | ATIM_CR2_OIS1N | - ATIM_CR2_OIS2 | ATIM_CR2_OIS2N | - ATIM_CR2_OIS3 | ATIM_CR2_OIS3N | - ATIM_CR2_OIS4); - } -# if defined(HAVE_GTIM_CCXNP) - else - { - ccer &= ~(GTIM_CCER_CC1NP | GTIM_CCER_CC2NP | GTIM_CCER_CC3NP | - GTIM_CCER_CC4NP); - } -# endif - -#else /* No ADV TIM */ - - /* For the STM32L15XX family only these timers can be used: 2-4, 6, 7, 9, - * 10. Reset the output compare and output compare N IDLE State - */ - - if (priv->tbase >= STM32_TIM2_BASE && priv->tbase <= STM32_TIM4_BASE) - { - /* Reset output N polarity level, output N state, output compare state, - * output compare N idle state. - */ - - ccer &= ~(GTIM_CCER_CC1NE | GTIM_CCER_CC1NP | - GTIM_CCER_CC2NE | GTIM_CCER_CC2NP | - GTIM_CCER_CC3NE | GTIM_CCER_CC3NP | - GTIM_CCER_CC4NP); - } -#endif - - /* Save the modified register values */ - - tim_putreg(priv, STM32_GTIM_CR2_OFFSET, cr2); - tim_putreg(priv, STM32_GTIM_CCMR1_OFFSET, ccmr1); - tim_putreg(priv, STM32_GTIM_CCMR2_OFFSET, ccmr2); - tim_putreg(priv, STM32_GTIM_CCER_OFFSET, ccer); - tim_putreg(priv, STM32_GTIM_EGR_OFFSET, egr); - - /* Set the ARR Preload Bit */ - - tim_modifyreg(priv, STM32_GTIM_CR1_OFFSET, 0, GTIM_CR1_ARPE); - - /* Enable the timer counter */ - - adc_timstart(priv, true); - - tim_dumpregs(priv, "After starting timers"); - - return OK; -} -#endif - -/**************************************************************************** - * Name: adc_reg_startconv - * - * Description: - * Start (or stop) the ADC regular conversion process - * - * Input Parameters: - * priv - A reference to the ADC block status - * enable - True: Start conversion - * - * Returned Value: - * - ****************************************************************************/ - -#if defined(HAVE_IP_ADC_V2) -static void adc_reg_startconv(struct stm32_dev_s *priv, bool enable) -{ - uint32_t regval; - - ainfo("reg enable: %d\n", enable ? 1 : 0); - - if (enable) - { - /* Start the conversion of regular channels */ - - adc_modifyreg(priv, STM32_ADC_CR_OFFSET, 0, ADC_CR_ADSTART); - } - else - { - regval = adc_getreg(priv, STM32_ADC_CR_OFFSET); - - /* Is a conversion ongoing? */ - - if ((regval & ADC_CR_ADSTART) != 0) - { - /* Stop the conversion */ - - adc_putreg(priv, STM32_ADC_CR_OFFSET, regval | ADC_CR_ADSTP); - - /* Wait for the conversion to stop */ - - while ((adc_getreg(priv, STM32_ADC_CR_OFFSET) & - ADC_CR_ADSTP) != 0); - } - } -} -#elif defined(HAVE_IP_ADC_V1) && !defined(HAVE_BASIC_ADC) -static void adc_reg_startconv(struct stm32_dev_s *priv, bool enable) -{ - ainfo("reg enable: %d\n", enable ? 1 : 0); - - if (enable) - { - /* Start the conversion of regular channels */ - - adc_modifyreg(priv, STM32_ADC_CR2_OFFSET, 0, ADC_CR2_SWSTART); - } - else - { - /* Stop the conversion */ - - adc_modifyreg(priv, STM32_ADC_CR2_OFFSET, ADC_CR2_SWSTART, 0); - } -} -#else /* ADV IPv1 BASIC */ -static void adc_reg_startconv(struct stm32_dev_s *priv, bool enable) -{ - ainfo("reg enable: %d\n", enable ? 1 : 0); - - if (!enable) - { - /* Clear ADON to stop the conversion and put the ADC in the - * power down state. - */ - - adc_enable(priv, false); - } - - /* If the ADC is already on, set ADON again to start the conversion. - * Otherwise, set ADON once to wake up the ADC from the power down state. - */ - - adc_enable(priv, true); -} -#endif - -#ifdef ADC_HAVE_INJECTED - -/**************************************************************************** - * Name: adc_inj_startconv - * - * Description: - * Start (or stop) the ADC injected conversion process - * - * Input Parameters: - * priv - A reference to the ADC block status - * enable - True: Start conversion - * - * Returned Value: - * - ****************************************************************************/ - -#if defined(HAVE_IP_ADC_V2) -static void adc_inj_startconv(struct stm32_dev_s *priv, bool enable) -{ - uint32_t regval; - - ainfo("inj enable: %d\n", enable ? 1 : 0); - - if (enable) - { - /* Start the conversion of regular channels */ - - adc_modifyreg(priv, STM32_ADC_CR_OFFSET, 0, ADC_CR_JADSTART); - } - else - { - regval = adc_getreg(priv, STM32_ADC_CR_OFFSET); - - /* Is a conversion ongoing? */ - - if ((regval & ADC_CR_JADSTART) != 0) - { - /* Stop the conversion */ - - adc_putreg(priv, STM32_ADC_CR_OFFSET, regval | ADC_CR_JADSTP); - - /* Wait for the conversion to stop */ - - while ((adc_getreg(priv, STM32_ADC_CR_OFFSET) & - ADC_CR_JADSTP) != 0); - } - } -} -#elif defined(HAVE_IP_ADC_V1) -static void adc_inj_startconv(struct stm32_dev_s *priv, bool enable) -{ - ainfo("inj enable: %d\n", enable ? 1 : 0); - - if (enable) - { - /* Start the conversion of injected channels */ - - adc_modifyreg(priv, STM32_ADC_CR2_OFFSET, 0, ADC_CR2_JSWSTART); - } - else - { - /* Stop the conversion */ - - adc_modifyreg(priv, STM32_ADC_CR2_OFFSET, ADC_CR2_JSWSTART, 0); - } -} -#endif - -#endif /* ADC_HAVE_INJECTED */ - -/**************************************************************************** - * Name: adc_rccreset - * - * Description: - * Deinitializes the ADCx peripheral registers to their default - * reset values. It could set all the ADCs configured. - * - * Input Parameters: - * priv - A reference to the ADC block status - * reset - Condition, set or reset - * - * Returned Value: - * - ****************************************************************************/ - -#if defined(HAVE_IP_ADC_V1) && defined(HAVE_BASIC_ADC) -static void adc_rccreset(struct stm32_dev_s *priv, bool reset) -{ - uint32_t adcbit; - - /* Pick the appropriate bit in the RCC reset register. - * For the basic STM32 ADC IPv1, there is an individual bit to reset - * each ADC (ADC12 and ADC34). - */ - - switch (priv->intf) - { -#ifdef CONFIG_STM32_ADC1 - case 1: - { - adcbit = RCC_RSTR_ADC1RST; - break; - } - -#endif -#ifdef CONFIG_STM32_ADC2 - case 2: - { - adcbit = RCC_RSTR_ADC2RST; - break; - } - -#endif -#ifdef CONFIG_STM32_ADC3 - case 3: - { - adcbit = RCC_RSTR_ADC3RST; - break; - } - -#endif -#ifdef CONFIG_STM32_ADC4 - case 4: - { - adcbit = RCC_RSTR_ADC4RST; - break; - } - -#endif - default: - { - return; - } - } - - /* Set or clear the selected bit in the RCC reset register */ - - if (reset) - { - /* Enable ADC reset state */ - - modifyreg32(STM32_RCC_RSTR, 0, adcbit); - } - else - { - /* Release ADC from reset state */ - - modifyreg32(STM32_RCC_RSTR, adcbit, 0); - } -} -#elif defined(HAVE_IP_ADC_V1) -static void adc_rccreset(struct stm32_dev_s *priv, bool reset) -{ - uint32_t adcbit; - - /* Pick the appropriate bit in the RCC reset register. - * For the STM32 ADC IPv1, there is one common reset for all ADCs. - */ - - switch (priv->intf) - { - case 1: - case 2: - case 3: - { - adcbit = RCC_RSTR_ADC123RST; - break; - } - - default: - { - return; - } - } - - /* Set or clear the selected bit in the RCC reset register */ - - if (reset) - { - /* Enable ADC reset state */ - - modifyreg32(STM32_RCC_RSTR, 0, adcbit); - } - else - { - /* Release ADC from reset state */ - - modifyreg32(STM32_RCC_RSTR, adcbit, 0); - } -} -#elif defined(HAVE_IP_ADC_V2) -static void adc_rccreset(struct stm32_dev_s *priv, bool reset) -{ - uint32_t adcbit; - - /* Pick the appropriate bit in the RCC reset register. - * For the STM32 ADC IPv2, there is an individual bit to reset each - * ADC block. - */ - - switch (priv->intf) - { -#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) - case 1: - case 2: - { - adcbit = RCC_RSTR_ADC12RST; - break; - } - -#endif -#if defined(CONFIG_STM32_ADC3) || defined(CONFIG_STM32_ADC4) - case 3: - case 4: - { - adcbit = RCC_RSTR_ADC34RST; - break; - } - -#endif - default: - { - return; - } - } - - /* Set or clear the selected bit in the RCC reset register */ - - if (reset) - { - /* Enable ADC reset state */ - - modifyreg32(STM32_RCC_RSTR, 0, adcbit); - } - else - { - /* Release ADC from reset state */ - - modifyreg32(STM32_RCC_RSTR, adcbit, 0); - } -} -#endif - -/**************************************************************************** - * Name: adc_power_down_idle - * - * Description: - * Enables or disables power down during the idle phase. - * - * Input Parameters: - * - * priv - pointer to the adc device structure - * pdi_high - true: The ADC is powered down when waiting for a start event - * false: The ADC is powered up when waiting for a start event - * - * Returned Value: - * None. - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_STM32L15XX -static void adc_power_down_idle(struct stm32_dev_s *priv, bool pdi_high) -{ - uint32_t regval; - - ainfo("PDI: %d\n", pdi_high ? 1 : 0); - - regval = adc_getreg(priv, STM32_ADC_CR1_OFFSET); - - if ((STM32_ADC1_CR2 & ADC_CR2_ADON) == 0) - { - if (pdi_high) - { - regval |= ADC_CR1_PDI; - } - else - { - regval &= ~ADC_CR1_PDI; - } - - adc_putreg(priv, STM32_ADC_CR1_OFFSET, regval); - } -} -#endif - -/**************************************************************************** - * Name: adc_power_down_delay - * - * Description: - * Enables or disables power down during the delay phase. - * - * Input Parameters: - * - * priv - pointer to the adc device structure - * pdd_high - true: The ADC is powered down when waiting for a start event - * false: The ADC is powered up when waiting for a start event - * - * Returned Value: - * None. - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_STM32L15XX -static void adc_power_down_delay(struct stm32_dev_s *priv, bool pdd_high) -{ - uint32_t regval; - - ainfo("PDD: %d\n", pdd_high ? 1 : 0); - - regval = adc_getreg(priv, STM32_ADC_CR1_OFFSET); - - if ((STM32_ADC1_CR2 & ADC_CR2_ADON) == 0) - { - if (pdd_high) - { - regval |= ADC_CR1_PDD; - } - else - { - regval &= ~ADC_CR1_PDD; - } - - adc_putreg(priv, STM32_ADC_CR1_OFFSET, regval); - } -} -#endif - -/**************************************************************************** - * Name: adc_dels_after_conversion - * - * Description: - * Defines the length of the delay which is applied after a conversion or - * a sequence of conversions. - * - * Input Parameters: - * - * priv - pointer to the adc device structure - * delay - delay selection (see definition in chip/chip/stm32_adc.h - * starting from line 284) - * - * Returned Value: - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_STM32L15XX -static void adc_dels_after_conversion(struct stm32_dev_s *priv, - uint32_t delay) -{ - ainfo("Delay selected: 0x%08" PRIx32 "\n", delay); - - adc_modifyreg(priv, STM32_ADC_CR2_OFFSET, ADC_CR2_DELS_MASK, delay); -} -#endif - -/**************************************************************************** - * Name: adc_select_ch_bank - * - * Description: - * Selects the bank of channels to be converted - * (! Must be modified only when no conversion is on going !) - * - * Input Parameters: - * - * priv - pointer to the adc device structure - * enable - true: bank of channels B selected - * false: bank of channels A selected - * - * Returned Value: - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_STM32L15XX -static void adc_select_ch_bank(struct stm32_dev_s *priv, - bool chb_selected) -{ - ainfo("Bank of channels selected: %c\n", chb_selected ? 'B' : 'A'); - - if (chb_selected) - { - adc_modifyreg(priv, STM32_ADC_CR2_OFFSET, 0, ADC_CR2_CFG); - } - else - { - adc_modifyreg(priv, STM32_ADC_CR2_OFFSET, ADC_CR2_CFG, 0); - } -} -#endif - -/**************************************************************************** - * Name: adc_enable - * - * Description: - * Enables or disables the specified ADC peripheral. Also, starts a - * conversion when the ADC is not triggered by timers - * - * Input Parameters: - * - * enable - true: enable ADC conversion - * false: disable ADC conversion - * - * Returned Value: - * - ****************************************************************************/ - -#if defined(HAVE_IP_ADC_V2) -static void adc_enable(struct stm32_dev_s *priv, bool enable) -{ - uint32_t regval; - - ainfo("enable: %d\n", enable ? 1 : 0); - - regval = adc_getreg(priv, STM32_ADC_CR_OFFSET); - - if (enable) - { - /* Enable the ADC */ - - adc_putreg(priv, STM32_ADC_CR_OFFSET, regval | ADC_CR_ADEN); - - /* Wait for the ADC to be ready */ - - while ((adc_getreg(priv, STM32_ADC_ISR_OFFSET) & ADC_INT_ARDY) == 0); - } - else if ((regval & ADC_CR_ADEN) != 0 && (regval & ADC_CR_ADDIS) == 0) - { - /* Stop ongoing regular conversions */ - - adc_reg_startconv(priv, false); - - /* Disable the ADC */ - - adc_putreg(priv, STM32_ADC_CR_OFFSET, regval | ADC_CR_ADDIS); - - /* Wait for the ADC to be disabled */ - - while ((adc_getreg(priv, STM32_ADC_CR_OFFSET) & ADC_CR_ADEN) != 0); - } -} -#else /* HAVE_IP_ADC_V1 */ -static void adc_enable(struct stm32_dev_s *priv, bool enable) -{ -#ifdef ADC_SR_ADONS - bool enabled = (adc_getreg(priv, STM32_ADC_SR_OFFSET) & ADC_SR_ADONS) != 0; -#else - bool enabled = false; -#endif - - ainfo("enable: %d\n", enable ? 1 : 0); - - if (!enabled && enable) - { - adc_modifyreg(priv, STM32_ADC_CR2_OFFSET, 0, ADC_CR2_ADON); - } - else if (enabled && !enable) - { - adc_modifyreg(priv, STM32_ADC_CR2_OFFSET, ADC_CR2_ADON, 0); - } -} -#endif - -/**************************************************************************** - * Name: adc_dmaconvcallback - * - * Description: - * Callback for DMA. Called from the DMA transfer complete interrupt after - * all channels have been converted and transferred with DMA. - * - * Input Parameters: - * - * handle - handle to DMA - * isr - - * arg - adc device - * - * Returned Value: - * - ****************************************************************************/ - -#if defined(ADC_HAVE_DMA) && !defined(CONFIG_STM32_ADC_NOIRQ) -static void adc_dmaconvcallback(DMA_HANDLE handle, uint8_t isr, - void *arg) -{ - struct adc_dev_s *dev = (struct adc_dev_s *)arg; - struct stm32_dev_s *priv = (struct stm32_dev_s *)dev->ad_priv; - int i; - - /* Verify that the upper-half driver has bound its callback functions */ - - if (priv->cb != NULL) - { - DEBUGASSERT(priv->cb->au_receive != NULL); - - for (i = 0; i < priv->rnchannels * priv->dmabatch; i++) - { - priv->cb->au_receive(dev, priv->r_chanlist[priv->current], - priv->r_dmabuffer[i]); - priv->current++; - if (priv->current >= priv->rnchannels) - { - /* Restart the conversion sequence from the beginning */ - - priv->current = 0; - } - } - } - - /* Restart DMA for the next conversion series */ - - adc_modifyreg(priv, STM32_ADC_DMAREG_OFFSET, ADC_DMAREG_DMA, 0); - adc_modifyreg(priv, STM32_ADC_DMAREG_OFFSET, 0, ADC_DMAREG_DMA); -} -#endif - -/**************************************************************************** - * Name: adc_bind - * - * Description: - * Bind the upper-half driver callbacks to the lower-half implementation. - * This must be called early in order to receive ADC event notifications. - * - ****************************************************************************/ - -static int adc_bind(struct adc_dev_s *dev, - const struct adc_callback_s *callback) -{ -#ifdef ADC_HAVE_CB - struct stm32_dev_s *priv = (struct stm32_dev_s *)dev->ad_priv; - - DEBUGASSERT(priv != NULL); - priv->cb = callback; -#else - UNUSED(dev); - UNUSED(callback); -#endif - - return OK; -} - -/**************************************************************************** - * Name: adc_watchdog_cfg - ****************************************************************************/ - -#if defined(HAVE_IP_ADC_V2) -static void adc_watchdog_cfg(struct stm32_dev_s *priv) -{ - uint32_t clrbits = 0; - uint32_t setbits = 0; - - /* Initialize the watchdog 1 threshold register */ - - adc_putreg(priv, STM32_ADC_TR1_OFFSET, 0x0fff0000); - - /* Enable the analog watchdog */ - - clrbits = ADC_CFGR1_AWD1CH_MASK; - setbits = ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL | - (priv->r_chanlist[0] << ADC_CFGR1_AWD1CH_SHIFT); - - /* Modify CFGR configuration */ - - adc_modifyreg(priv, STM32_ADC_CFGR1_OFFSET, clrbits, setbits); -} -#else -static void adc_watchdog_cfg(struct stm32_dev_s *priv) -{ - uint32_t clrbits = 0; - uint32_t setbits = 0; - - /* Initialize the watchdog high threshold register */ - - adc_putreg(priv, STM32_ADC_HTR_OFFSET, 0x00000fff); - - /* Initialize the watchdog low threshold register */ - - adc_putreg(priv, STM32_ADC_LTR_OFFSET, 0x00000000); - - clrbits = ADC_CR1_AWDCH_MASK; - setbits = ADC_CR1_AWDEN | (priv->r_chanlist[0] << ADC_CR1_AWDCH_SHIFT); - - /* Modify CR1 configuration */ - - adc_modifyreg(priv, STM32_ADC_CR1_OFFSET, clrbits, setbits); -} -#endif - -/**************************************************************************** - * Name: adc_calibrate - ****************************************************************************/ - -#if defined(HAVE_IP_ADC_V2) -static void adc_calibrate(struct stm32_dev_s *priv) -{ -#if 0 /* Doesn't work */ - /* Calibrate the ADC */ - - adc_modifyreg(priv, STM32_ADC_CR_OFFSET, ADC_CR_ADCALDIF, AD_CR_ADCAL); - - /* Wait for the calibration to complete */ - - while ((adc_getreg(priv, STM32_ADC_CR_OFFSET) & ADC_CR_ADCAL) != 0); - -#else - UNUSED(priv); -#endif -} -#elif defined(HAVE_IP_ADC_V1) && defined(HAVE_BASIC_ADC) -static void adc_calibrate(struct stm32_dev_s *priv) -{ - /* Power on the ADC */ - - adc_modifyreg(priv, STM32_ADC_CR2_OFFSET, 0, ADC_CR2_ADON); - - /* Wait for the ADC power on at least 2 ADCCLK cycles */ - - up_udelay(10); - - /* Reset calibration registers */ - - adc_modifyreg(priv, STM32_ADC_CR2_OFFSET, 0, ADC_CR2_RSTCAL); - - /* Wait for the calibration register reset to complete */ - - while ((adc_getreg(priv, STM32_ADC_CR2_OFFSET) & ADC_CR2_RSTCAL) != 0); - - /* Start ADC auto-calibration procedure */ - - adc_modifyreg(priv, STM32_ADC_CR2_OFFSET, 0, ADC_CR2_CAL); - - /* Wait for the calibration procedure to complete */ - - while ((adc_getreg(priv, STM32_ADC_CR2_OFFSET) & ADC_CR2_CAL) != 0); - - /* Power off the ADC */ - - adc_modifyreg(priv, STM32_ADC_CR2_OFFSET, ADC_CR2_ADON, 0); -} -#else -# define adc_calibrate(priv) -#endif - -/**************************************************************************** - * Name: adc_mode_cfg - ****************************************************************************/ - -#ifdef HAVE_IP_ADC_V2 -static void adc_mode_cfg(struct stm32_dev_s *priv) -{ - uint32_t clrbits = 0; - uint32_t setbits = 0; - - /* Disable continuous mode and set align to right */ - - clrbits = ADC_CFGR1_CONT | ADC_CFGR1_ALIGN; - - /* Disable external trigger for regular channels */ - - clrbits |= ADC_CFGR1_EXTEN_MASK; - setbits |= ADC_CFGR1_EXTEN_NONE; - - /* Set CFGR configuration */ - - adc_modifyreg(priv, STM32_ADC_CFGR1_OFFSET, clrbits, setbits); -} -#else -static void adc_mode_cfg(struct stm32_dev_s *priv) -{ - uint32_t clrbits = 0; - uint32_t setbits = 0; - -#ifdef HAVE_BASIC_ADC - /* Set independent mode */ - - clrbits |= ADC_CR1_DUALMOD_MASK; - setbits |= ADC_CR1_IND; -#endif - -#ifdef ADC_HAVE_SCAN - if (priv->scan == true) - { - setbits |= ADC_CR1_SCAN; - } -#endif - - /* Set CR1 configuration */ - - adc_modifyreg(priv, STM32_ADC_CR1_OFFSET, clrbits, setbits); - - /* REVISIT: */ - -#ifdef CONFIG_STM32_STM32L15XX - - /* Select the bank of channels A */ - - adc_select_ch_bank(priv, false); - -# ifdef HAVE_ADC_POWERDOWN - /* Disables power down during the delay phase */ - - adc_power_down_idle(priv, false); - adc_power_down_delay(priv, false); -# endif - - /* Delay until the converted data has been read */ - - adc_dels_after_conversion(priv, ADC_CR2_DELS_TILLRD); -#endif - - /* Disable continuous mode and set align to right */ - - clrbits = ADC_CR2_CONT | ADC_CR2_ALIGN; - setbits = 0; - - /* Disable external trigger for regular channels */ - - clrbits |= ADC_EXTREG_EXTEN_MASK; - setbits |= ADC_EXTREG_EXTEN_NONE; - - /* Enable software trigger for regular channels - * REVISIT: SWSTART must be set if no EXT trigger and basic ADC IPv1 - */ - -#ifdef CONFIG_STM32_STM32F37XX - clrbits |= ADC_CR2_EXTSEL_MASK; - setbits |= ADC_CR2_EXTSEL_SWSTART | ADC_CR2_EXTTRIG; /* SW is considered as external trigger */ -#endif - - /* Set CR2 configuration */ - - adc_modifyreg(priv, STM32_ADC_CR2_OFFSET, clrbits, setbits); -} -#endif - -/**************************************************************************** - * Name: adc_voltreg_cfg - ****************************************************************************/ - -#if defined(HAVE_IP_ADC_V2) -static void adc_voltreg_cfg(struct stm32_dev_s *priv) -{ - /* Set ADC voltage regulator to intermediate state */ - - adc_modifyreg(priv, STM32_ADC_CR_OFFSET, ADC_CR_ADVREGEN_MASK, - ADC_CR_ADVREGEN_INTER); - - /* Enable the ADC voltage regulator */ - - adc_modifyreg(priv, STM32_ADC_CR_OFFSET, ADC_CR_ADVREGEN_MASK, - ADC_CR_ADVREGEN_ENABLED); - - /* Wait for the ADC voltage regulator to startup */ - - up_udelay(10); -} -#else -static void adc_voltreg_cfg(struct stm32_dev_s *priv) -{ - /* Nothing to do here */ - - UNUSED(priv); -} -#endif - -/**************************************************************************** - * Name: adc_sampletime_cfg - ****************************************************************************/ - -static void adc_sampletime_cfg(struct adc_dev_s *dev) -{ - /* Initialize the same sample time for each ADC. - * During sample cycles channel selection bits must remain unchanged. - */ - -#ifdef CONFIG_STM32_ADC_CHANGE_SAMPLETIME - adc_sampletime_write((struct stm32_adc_dev_s *)dev->ad_priv); -#else - struct stm32_dev_s *priv = (struct stm32_dev_s *)dev->ad_priv; - - adc_putreg(priv, STM32_ADC_SMPR1_OFFSET, ADC_SMPR1_DEFAULT); - adc_putreg(priv, STM32_ADC_SMPR2_OFFSET, ADC_SMPR2_DEFAULT); -# ifdef STM32_ADC_SMPR3_OFFSET - adc_putreg(priv, STM32_ADC_SMPR3_OFFSET, ADC_SMPR3_DEFAULT); -# endif -# ifdef STM32_ADC_SMPR0_OFFSET - adc_putreg(priv, STM32_ADC_SMPR0_OFFSET, ADC_SMPR0_DEFAULT); -# endif -#endif -} - -/**************************************************************************** - * Name: adc_common_cfg - ****************************************************************************/ - -#if defined(HAVE_IP_ADC_V2) -static void adc_common_cfg(struct stm32_dev_s *priv) -{ - uint32_t clrbits = 0; - uint32_t setbits = 0; - - /* REVISIT: */ - - clrbits = ADC_CCR_DUAL_MASK | ADC_CCR_DELAY_MASK | ADC_CCR_DMACFG | - ADC_CCR_MDMA_MASK | ADC_CCR_CKMODE_MASK | ADC_CCR_VREFEN | - ADC_CCR_TSEN | ADC_CCR_VBATEN; - setbits = ADC_CCR_DUAL_IND | ADC_CCR_DELAY(1) | ADC_CCR_MDMA_DISABLED | - ADC_CCR_CKMODE_ASYNCH; - - adccmn_modifyreg(priv, STM32_ADC_CCR_OFFSET, clrbits, setbits); -} -#elif defined(HAVE_IP_ADC_V1) && !defined(HAVE_BASIC_ADC) -static void adc_common_cfg(struct stm32_dev_s *priv) -{ - uint32_t clrbits = 0; - uint32_t setbits = 0; - - clrbits = ADC_CCR_ADCPRE_MASK | ADC_CCR_TSVREFE; - setbits = ADC_CCR_ADCPRE_DIV2; - - /* REVISIT: */ - -#if !defined(CONFIG_STM32_STM32L15XX) - clrbits |= ADC_CCR_MULTI_MASK | ADC_CCR_DELAY_MASK | ADC_CCR_DDS | - ADC_CCR_DMA_MASK | ADC_CCR_VBATEN; - setbits |= ADC_CCR_MULTI_NONE | ADC_CCR_DMA_DISABLED; -#endif /* !defined(CONFIG_STM32_STM32L15XX) */ - - adccmn_modifyreg(priv, STM32_ADC_CCR_OFFSET, clrbits, setbits); -} -#else -static void adc_common_cfg(struct stm32_dev_s *priv) -{ - /* Do nothing here */ - - UNUSED(priv); -} -#endif - -#ifdef ADC_HAVE_DMA -/**************************************************************************** - * Name: adc_dma_cfg - ****************************************************************************/ - -#ifdef HAVE_IP_ADC_V2 -static void adc_dma_cfg(struct stm32_dev_s *priv) -{ - uint32_t clrbits = 0; - uint32_t setbits = 0; - - /* Set DMA mode */ - - if (priv->dmacfg == 0) - { - /* One Shot Mode */ - - clrbits |= ADC_CFGR1_DMACFG; - } - else - { - /* Circular Mode */ - - setbits |= ADC_CFGR1_DMACFG; - } - - /* Enable DMA */ - - setbits |= ADC_CFGR1_DMAEN; - - /* Modify CFGR configuration */ - - adc_modifyreg(priv, STM32_ADC_CFGR1_OFFSET, clrbits, setbits); -} -#else -static void adc_dma_cfg(struct stm32_dev_s *priv) -{ - uint32_t clrbits = 0; - uint32_t setbits = 0; - -#ifdef ADC_HAVE_DMACFG - /* Set DMA mode */ - - if (priv->dmacfg == 0) - { - /* One Shot Mode */ - - clrbits |= ADC_CR2_DDS; - } - else - { - /* Circular Mode */ - - setbits |= ADC_CR2_DDS; - } -#endif - - /* Enable DMA */ - - setbits |= ADC_CR2_DMA; - - /* Modify CR2 configuration */ - - adc_modifyreg(priv, STM32_ADC_CR2_OFFSET, clrbits, setbits); -} -#endif - -/**************************************************************************** - * Name: adc_dma_start - ****************************************************************************/ - -static void adc_dma_start(struct adc_dev_s *dev) -{ - struct stm32_dev_s *priv = (struct stm32_dev_s *)dev->ad_priv; - - /* Stop and free DMA if it was started before */ - - if (priv->dma != NULL) - { - stm32_dmastop(priv->dma); - stm32_dmafree(priv->dma); - } - - priv->dma = stm32_dmachannel(priv->dmachan); - -#ifndef CONFIG_STM32_ADC_NOIRQ - /* Start DMA only if standard ADC interrupts used */ - - stm32_dmasetup(priv->dma, - priv->base + STM32_ADC_DR_OFFSET, - (uint32_t)priv->r_dmabuffer, - priv->rnchannels * priv->dmabatch, - ADC_DMA_CONTROL_WORD); - - stm32_dmastart(priv->dma, adc_dmaconvcallback, dev, false); -#endif -} -#endif /* ADC_HAVE_DMA */ - -/**************************************************************************** - * Name: adc_configure - ****************************************************************************/ - -static void adc_configure(struct adc_dev_s *dev) -{ - struct stm32_dev_s *priv = (struct stm32_dev_s *)dev->ad_priv; - - /* Turn off the ADC before configuration */ - - adc_enable(priv, false); - - /* Configure voltage regulator if present */ - - adc_voltreg_cfg(priv); - - /* Calibrate ADC - doesn't work for now */ - - adc_calibrate(priv); - - /* Initialize the ADC watchdog */ - - adc_watchdog_cfg(priv); - - /* Initialize the ADC sample time */ - - adc_sampletime_cfg(dev); - - /* Set ADC working mode */ - - adc_mode_cfg(priv); - - /* Configuration of the channel conversions */ - - if (priv->cr_channels > 0) - { - adc_set_ch(dev, 0); - } - -#ifdef ADC_HAVE_INJECTED - /* Configuration of the injected channel conversions after adc enabled */ - - if (priv->cj_channels > 0) - { - adc_inj_set_ch(dev, 0); - } -#endif - - /* ADC common register configuration */ - - adc_common_cfg(priv); - -#ifdef ADC_HAVE_DMA - /* Configure ADC DMA if enabled */ - - if (priv->hasdma) - { - /* Configure ADC DMA */ - - adc_dma_cfg(priv); - - /* Start ADC DMA */ - - adc_dma_start(dev); - } -#endif - -#ifdef HAVE_ADC_RESOLUTION - /* Configure ADC resolution */ - - adc_resolution_set(dev, priv->resolution); -#endif - -#ifdef ADC_HAVE_EXTCFG - /* Configure external event for regular group */ - - adc_extcfg_set(priv, priv->extcfg); -#endif - - /* Enable ADC */ - - adc_enable(priv, true); - -#ifdef ADC_HAVE_JEXTCFG - /* Configure external event for injected group when ADC enabled */ - - adc_jextcfg_set(priv, priv->jextcfg); - -#if defined(HAVE_IP_ADC_V2) - /* For ADC IPv2 there is queue of context for injected conversion. - * JEXTCFG configuration is the second write to JSQR register which means - * configuration is stored on queue. - * We trigger single INJ conversion here to update context. - */ - - adc_inj_startconv(priv, true); -#endif -#endif - - /* Dump regs */ - - adc_dumpregs(priv); -} - -/**************************************************************************** - * Name: adc_reset - * - * Description: - * Reset the ADC device. Called early to initialize the hardware. - * This is called, before adc_setup() and on error conditions. - * - * Input Parameters: - * - * Returned Value: - * - ****************************************************************************/ - -static void adc_reset(struct adc_dev_s *dev) -{ - struct stm32_dev_s *priv = (struct stm32_dev_s *)dev->ad_priv; - irqstate_t flags; - - ainfo("intf: %d\n", priv->intf); - flags = enter_critical_section(); - - /* Do nothing if ADC instance is currently in use */ - - if (priv->initialized > 0) - { - goto out; - } - -#ifdef HAVE_HSI_CONTROL - /* The STM32L15XX family uses HSI as an independent clock-source - * for the ADC - */ - - adc_enable_hsi(true); -#endif - -#if defined(HAVE_IP_ADC_V2) - /* Turn off the ADC so we can write the RCC bits */ - - adc_enable(priv, false); -#endif - - /* Only if this is the first initialzied ADC instance in the ADC block */ - -#ifdef HAVE_ADC_CMN_DATA - if (nxmutex_lock(&priv->cmn->lock) < 0) - { - goto out; - } - - if (priv->cmn->refcount == 0) -#endif - { - /* Enable ADC reset state */ - - adc_rccreset(priv, true); - - /* Release ADC from reset state */ - - adc_rccreset(priv, false); - } - -#ifdef HAVE_ADC_CMN_DATA - nxmutex_unlock(&priv->cmn->lock); -#endif - -out: - leave_critical_section(flags); -} - -/**************************************************************************** - * Name: adc_reset_hsi_disable - * - * Description: - * Reset the ADC device with HSI and ADC shut down. Called early to - * initialize the hardware. This is called, before adc_setup() and on - * error conditions. In STM32L15XX case sometimes HSI must be shut - * down after the first initialization - * - * Input Parameters: - * - * Returned Value: - * - ****************************************************************************/ - -#ifdef HAVE_HSI_CONTROL -static void adc_reset_hsi_disable(struct adc_dev_s *dev) -{ - adc_reset(dev); - adc_shutdown(dev); -} -#endif - -/**************************************************************************** - * Name: adc_setup - * - * Description: - * Configure the ADC. This method is called the first time that the ADC - * device is opened. This will occur when the port is first opened. - * This setup includes configuring and attaching ADC interrupts. - * Interrupts are all disabled upon return. - * - * Input Parameters: - * - * Returned Value: - * - ****************************************************************************/ - -static int adc_setup(struct adc_dev_s *dev) -{ - struct stm32_dev_s *priv = (struct stm32_dev_s *)dev->ad_priv; - int ret = OK; - - /* Do nothing when the ADC device is already set up */ - - if (priv->initialized > 0) - { - priv->initialized += 1; - return OK; - } - - /* Make sure that the ADC device is in the powered up, reset state */ - - adc_reset(dev); - - /* Configure ADC device */ - - adc_configure(dev); - -#ifdef ADC_HAVE_TIMER - /* Configure timer */ - - if (priv->tbase != 0) - { - ret = adc_timinit(priv); - if (ret < 0) - { - aerr("ERROR: adc_timinit failed: %d\n", ret); - } - } -#endif - - /* As default conversion is started here. - * - * NOTE: for ADC IPv2 (J)ADSTART bit must be set to start ADC conversion - * even if hardware trigger is selected. - * This can be done here during the opening of the ADC device - * or later with ANIOC_TRIGGER ioctl call. - */ - -#ifndef CONFIG_STM32_ADC_NO_STARTUP_CONV - /* Start regular conversion */ - - adc_reg_startconv(priv, true); - -# ifdef ADC_HAVE_INJECTED - /* Start injected conversion */ - - adc_inj_startconv(priv, true); -# endif -#endif - -#ifdef HAVE_ADC_CMN_DATA - /* Increase instances counter */ - - ret = nxmutex_lock(&priv->cmn->lock); - if (ret < 0) - { - return ret; - } - - if (priv->cmn->refcount == 0) -#endif - { -#ifndef CONFIG_STM32_ADC_NOIRQ - /* Attach the ADC interrupt */ - - ret = irq_attach(priv->irq, priv->isr, NULL); - if (ret < 0) - { - ainfo("irq_attach failed: %d\n", ret); - return ret; - } - - /* Enable the ADC interrupt */ - - ainfo("Enable the ADC interrupt: irq=%d\n", priv->irq); - up_enable_irq(priv->irq); -#endif - } - -#ifdef HAVE_ADC_CMN_DATA - priv->cmn->refcount += 1; - nxmutex_unlock(&priv->cmn->lock); -#endif - - /* The ADC device is ready */ - - priv->initialized += 1; - - return ret; -} - -/**************************************************************************** - * Name: adc_shutdown - * - * Description: - * Disable the ADC. This method is called when the ADC device is closed. - * This method reverses the operation the setup method. - * - * Input Parameters: - * - * Returned Value: - * - ****************************************************************************/ - -static void adc_shutdown(struct adc_dev_s *dev) -{ - struct stm32_dev_s *priv = (struct stm32_dev_s *)dev->ad_priv; - - /* Decrement count only when ADC device is in use */ - - if (priv->initialized > 0) - { - priv->initialized -= 1; - } - - /* Shutdown the ADC device only when not in use */ - - if (priv->initialized > 0) - { - return; - } - - /* Disable ADC */ - - adc_enable(priv, false); - -#ifdef HAVE_HSI_CONTROL - adc_enable_hsi(false); -#endif - -#ifdef HAVE_ADC_CMN_DATA - if (nxmutex_lock(&priv->cmn->lock) < 0) - { - return; - } - - if (priv->cmn->refcount <= 1) -#endif - { -#ifndef CONFIG_STM32_ADC_NOIRQ - /* Disable ADC interrupts and detach the ADC interrupt handler */ - - up_disable_irq(priv->irq); - irq_detach(priv->irq); -#endif - - /* Disable and reset the ADC module. - * - * NOTE: The ADC block will be reset to its reset state only if all - * ADC block instances are closed. This means that the closed - * ADC may not be reset which in turn may affect low-power - * applications. (But ADC is turned off here, is not that - * enough?) - */ - - adc_rccreset(priv, true); - } - -#ifdef ADC_HAVE_TIMER - /* Disable timer */ - - if (priv->tbase != 0) - { - adc_timstart(priv, false); - } -#endif - -#ifdef HAVE_ADC_CMN_DATA - /* Decrease instances counter */ - - if (priv->cmn->refcount > 0) - { - priv->cmn->refcount -= 1; - } - - nxmutex_unlock(&priv->cmn->lock); -#endif -} - -/**************************************************************************** - * Name: adc_rxint - * - * Description: - * Call to enable or disable RX interrupts. - * - * Input Parameters: - * - * Returned Value: - * - ****************************************************************************/ - -static void adc_rxint(struct adc_dev_s *dev, bool enable) -{ - struct stm32_dev_s *priv = (struct stm32_dev_s *)dev->ad_priv; - uint32_t regval; - - ainfo("intf: %d enable: %d\n", priv->intf, enable ? 1 : 0); - - if (enable) - { - /* Enable the analog watchdog / overrun interrupts, and if no DMA, - * end-of-conversion ADC. - */ - - regval = ADC_IER_ALLINTS; -#ifdef ADC_HAVE_DMA - if (priv->hasdma) - { - regval &= ~(ADC_IER_EOC | ADC_IER_JEOC); - } -#endif - - adc_modifyreg(priv, STM32_ADC_IER_OFFSET, 0, regval); - } - else - { - /* Disable all ADC interrupts */ - - adc_modifyreg(priv, STM32_ADC_IER_OFFSET, ADC_IER_ALLINTS, 0); - } -} - -/**************************************************************************** - * Name: adc_enable_tvref_register - * - * Description: - * Enable/disable the temperature sensor and the VREFINT channel. - * - * Input Parameters: - * dev - pointer to device structure used by the driver - * enable - true: Temperature sensor and V REFINT channel enabled - * (ch 16 and 17) - * false: Temperature sensor and V REFINT channel disabled - * (ch 16 and 17) - * - * Returned Value: - * None. - * - ****************************************************************************/ - -#if defined(HAVE_IP_ADC_V1) -static void adc_ioc_enable_tvref_register(struct adc_dev_s *dev, - bool enable) -{ - struct stm32_dev_s *priv = (struct stm32_dev_s *)dev->ad_priv; - -#ifdef HAVE_BASIC_ADC -# if defined(CONFIG_STM32_ADC1) - /* TSVREF bit is only available in the STM32_ADC1_CR2 register. */ - - if (priv->intf == 1) - { - if (enable) - { - adc_modifyreg(priv, STM32_ADC_CR2_OFFSET, 0, ADC_CR2_TSVREFE); - } - else - { - adc_modifyreg(priv, STM32_ADC_CR2_OFFSET, ADC_CR2_TSVREFE, 0); - } - } - - ainfo("STM32_ADC_CR2 value: 0x%08" PRIx32 "\n", - adc_getreg(priv, STM32_ADC_CR2_OFFSET)); -# endif /* CONFIG_STM32_ADC1 */ -#else /* !HAVE_BASIC_ADC */ - if (enable) - { - adccmn_modifyreg(priv, STM32_ADC_CCR_OFFSET, 0, ADC_CCR_TSVREFE); - } - else - { - adccmn_modifyreg(priv, STM32_ADC_CCR_OFFSET, ADC_CCR_TSVREFE, 0); - } - - ainfo("STM32_ADC_CCR value: 0x%08" PRIx32 "\n", - adccmn_getreg(priv, STM32_ADC_CCR_OFFSET)); -#endif -} -#endif /* HAVE_IP_ADC_V1 */ - -/**************************************************************************** - * Name: adc_resolution_set - ****************************************************************************/ - -#ifdef HAVE_ADC_RESOLUTION -static int adc_resolution_set(struct adc_dev_s *dev, uint8_t res) -{ - struct stm32_dev_s *priv = (struct stm32_dev_s *)dev->ad_priv; - int ret = OK; - - /* Check input */ - - if (res > 3) - { - ret = -EINVAL; - goto errout; - } - - /* Modify appropriate register */ - -#if defined(HAVE_IP_ADC_V1) - adc_modifyreg(priv, STM32_ADC_CR1_OFFSET, ADC_CR1_RES_MASK, - res << ADC_CR1_RES_SHIFT); -#elif defined(HAVE_IP_ADC_V2) - adc_modifyreg(priv, STM32_ADC_CFGR1_OFFSET, ADC_CFGR1_RES_MASK, - res << ADC_CFGR1_RES_SHIFT); -#endif - -errout: - return ret; -} -#endif - -/**************************************************************************** - * Name: adc_extcfg_set - ****************************************************************************/ - -#ifdef ADC_HAVE_EXTCFG -static int adc_extcfg_set(struct stm32_dev_s *priv, uint32_t extcfg) -{ - uint32_t exten = 0; - uint32_t extsel = 0; - uint32_t setbits = 0; - uint32_t clrbits = 0; - - /* Get EXTEN and EXTSEL from input */ - - exten = extcfg & ADC_EXTREG_EXTEN_MASK; - extsel = extcfg & ADC_EXTREG_EXTSEL_MASK; - - /* EXTSEL selection: These bits select the external event used - * to trigger the start of conversion of a regular group. NOTE: - * - * - The position with of the EXTSEL field varies from one STM32 MCU - * to another. - * - The width of the EXTSEL field varies from one STM32 MCU to another. - */ - - if (exten > 0) - { - setbits = extsel | exten; - clrbits = ADC_EXTREG_EXTEN_MASK | ADC_EXTREG_EXTSEL_MASK; - - ainfo("Initializing extsel = 0x%08" PRIx32 "\n", extsel); - - /* Write register */ - - adc_modifyreg(priv, STM32_ADC_EXTREG_OFFSET, clrbits, setbits); - } - - return OK; -} -#endif - -/**************************************************************************** - * Name: adc_jextcfg_set - ****************************************************************************/ - -#ifdef ADC_HAVE_JEXTCFG -static int adc_jextcfg_set(struct stm32_dev_s *priv, uint32_t jextcfg) -{ - uint32_t jexten = 0; - uint32_t jextsel = 0; - uint32_t setbits = 0; - uint32_t clrbits = 0; - - /* Get JEXTEN and JEXTSEL from input */ - - jexten = jextcfg & ADC_JEXTREG_JEXTEN_MASK; - jextsel = jextcfg & ADC_JEXTREG_JEXTSEL_MASK; - - /* JEXTSEL selection: These bits select the external event used - * to trigger the start of conversion of a injected group. NOTE: - * - * - The position with of the JEXTSEL field varies from one STM32 MCU - * to another. - * - The width of the JEXTSEL field varies from one STM32 MCU to another. - */ - - if (jexten > 0) - { - setbits = jexten | jextsel; - clrbits = ADC_JEXTREG_JEXTEN_MASK | ADC_JEXTREG_JEXTSEL_MASK; - - ainfo("Initializing jextsel = 0x%08" PRIx32 "\n", jextsel); - - /* Write register */ - - adc_modifyreg(priv, STM32_ADC_JEXTREG_OFFSET, clrbits, setbits); - } - - return OK; -} -#endif - -/**************************************************************************** - * Name: adc_dumpregs - ****************************************************************************/ - -static void adc_dumpregs(struct stm32_dev_s *priv) -{ - UNUSED(priv); - -#if defined(HAVE_IP_ADC_V2) - ainfo("ISR: 0x%08" PRIx32 " IER: 0x%08" PRIx32 - " CR: 0x%08" PRIx32 " CFGR1: 0x%08" PRIx32 "\n", - adc_getreg(priv, STM32_ADC_ISR_OFFSET), - adc_getreg(priv, STM32_ADC_IER_OFFSET), - adc_getreg(priv, STM32_ADC_CR_OFFSET), - adc_getreg(priv, STM32_ADC_CFGR1_OFFSET)); -#else - ainfo("SR: 0x%08" PRIx32 " CR1: 0x%08" PRIx32 - " CR2: 0x%08" PRIx32 "\n", - adc_getreg(priv, STM32_ADC_SR_OFFSET), - adc_getreg(priv, STM32_ADC_CR1_OFFSET), - adc_getreg(priv, STM32_ADC_CR2_OFFSET)); -#endif - - ainfo("SQR1: 0x%08" PRIx32 " SQR2: 0x%08" PRIx32 - " SQR3: 0x%08" PRIx32 "\n", - adc_getreg(priv, STM32_ADC_SQR1_OFFSET), - adc_getreg(priv, STM32_ADC_SQR2_OFFSET), - adc_getreg(priv, STM32_ADC_SQR3_OFFSET)); - - ainfo("SMPR1: 0x%08" PRIx32 " SMPR2: 0x%08" PRIx32 "\n", - adc_getreg(priv, STM32_ADC_SMPR1_OFFSET), - adc_getreg(priv, STM32_ADC_SMPR2_OFFSET)); - -#if defined(STM32_ADC_SQR4_OFFSET) - ainfo("SQR4: 0x%08" PRIx32 "\n", - adc_getreg(priv, STM32_ADC_SQR4_OFFSET)); -#endif - -#if defined(STM32_ADC_SQR5_OFFSET) - ainfo("SQR5: 0x%08" PRIx32 "\n", - adc_getreg(priv, STM32_ADC_SQR5_OFFSET)); -#endif - -#ifdef ADC_HAVE_INJECTED - ainfo("JSQR: 0x%08" PRIx32 "\n", adc_getreg(priv, STM32_ADC_JSQR_OFFSET)); -#endif - -#if defined(HAVE_IP_ADC_V2) || (defined(HAVE_IP_ADC_V1) && !defined(HAVE_BASIC_ADC)) - ainfo("CCR: 0x%08" PRIx32 "\n", - adccmn_getreg(priv, STM32_ADC_CCR_OFFSET)); -#endif -} - -/**************************************************************************** - * Name: adc_enable_vbat_channel - * - * Description: - * Enable/disable the Vbat voltage measurement channel. - * - * Input Parameters: - * dev - pointer to device structure used by the driver - * enable - true: Vbat input channel enabled (ch 18) - * false: Vbat input channel disabled (ch 18) - * - * Returned Value: - * None. - * - ****************************************************************************/ - -#ifdef HAVE_ADC_VBAT -static void adc_enable_vbat_channel(struct adc_dev_s *dev, bool enable) -{ - struct stm32_dev_s *priv = (struct stm32_dev_s *)dev->ad_priv; - - if (enable) - { - adccmn_modifyreg(priv, STM32_ADC_CCR_OFFSET, 0, ADC_CCR_VBATEN); - } - else - { - adccmn_modifyreg(priv, STM32_ADC_CCR_OFFSET, ADC_CCR_VBATEN, 0); - } - - ainfo("STM32_ADC_CCR value: 0x%08" PRIx32 "\n", - adccmn_getreg(priv, STM32_ADC_CCR_OFFSET)); -} -#endif - -/**************************************************************************** - * Name: adc_ioc_change_sleep_between_opers - * - * Description: - * Changes PDI and PDD bits to save battery. - * - * Input Parameters: - * dev - pointer to device structure used by the driver - * cmd - command - * arg - arguments passed with command - * - * Returned Value: - * - ****************************************************************************/ - -#ifdef HAVE_ADC_POWERDOWN -static int adc_ioc_change_sleep_between_opers(struct adc_dev_s *dev, - int cmd, bool arg) -{ - struct stm32_dev_s *priv = (struct stm32_dev_s *)dev->ad_priv; - int ret = OK; - - adc_enable(priv, false); - - switch (cmd) - { - case IO_ENABLE_DISABLE_PDI: - adc_power_down_idle(priv, arg); - break; - - case IO_ENABLE_DISABLE_PDD: - adc_power_down_delay(priv, arg); - break; - - case IO_ENABLE_DISABLE_PDD_PDI: - adc_power_down_idle(priv, arg); - adc_power_down_delay(priv, arg); - break; - - default: - ainfo("unknown cmd: %d\n", cmd); - break; - } - - adc_enable(priv, true); - - return ret; -} -#endif - -/**************************************************************************** - * Name: adc_ioc_enable_awd_int - * - * Description: - * Turns ON/OFF ADC analog watchdog interrupt. - * - * Input Parameters: - * dev - pointer to device structure used by the driver - * arg - true: Turn ON interrupt - * false: Turn OFF interrupt - * - * Returned Value: - * - ****************************************************************************/ - -static void adc_ioc_enable_awd_int(struct stm32_dev_s *priv, bool enable) -{ - if (enable) - { - adc_modifyreg(priv, STM32_ADC_IER_OFFSET, 0, ADC_IER_AWD); - } - else - { - adc_modifyreg(priv, STM32_ADC_IER_OFFSET, ADC_IER_AWD, 0); - } -} - -/**************************************************************************** - * Name: adc_ioc_enable_eoc_int - * - * Description: - * Turns ON/OFF ADC EOC interrupt. - * - * Input Parameters: - * dev - pointer to device structure used by the driver - * arg - true: Turn ON interrupt - * false: Turn OFF interrupt - * - * Returned Value: - * - ****************************************************************************/ - -static void adc_ioc_enable_eoc_int(struct stm32_dev_s *priv, bool enable) -{ - if (enable) - { - adc_modifyreg(priv, STM32_ADC_IER_OFFSET, 0, ADC_IER_EOC); - } - else - { - adc_modifyreg(priv, STM32_ADC_IER_OFFSET, ADC_IER_EOC, 0); - } -} - -/**************************************************************************** - * Name: adc_ioc_enable_jeoc_int - * - * Description: - * Turns ON/OFF ADC injected channels interrupt. - * - * Input Parameters: - * dev - pointer to device structure used by the driver - * arg - true: Turn ON interrupt - * false: Turn OFF interrupt - * - * Returned Value: - * - ****************************************************************************/ - -static void adc_ioc_enable_jeoc_int(struct stm32_dev_s *priv, - bool enable) -{ - if (enable) - { - adc_modifyreg(priv, STM32_ADC_IER_OFFSET, 0, ADC_IER_JEOC); - } - else - { - adc_modifyreg(priv, STM32_ADC_IER_OFFSET, ADC_IER_JEOC, 0); - } -} - -/**************************************************************************** - * Name: adc_ioc_enable_ovr_int - * - * Description: - * Turns ON/OFF ADC overrun interrupt. - * - * Input Parameters: - * dev - pointer to device structure used by the driver - * arg - true: Turn ON interrupt - * false: Turn OFF interrupt - * - * Returned Value: - * - ****************************************************************************/ - -static void adc_ioc_enable_ovr_int(struct stm32_dev_s *priv, bool enable) -{ - if (enable) - { - adc_modifyreg(priv, STM32_ADC_IER_OFFSET, 0, ADC_IER_OVR); - } - else - { - adc_modifyreg(priv, STM32_ADC_IER_OFFSET, ADC_IER_OVR, 0); - } -} - -/**************************************************************************** - * Name: adc_ioc_change_ints - * - * Description: - * Turns ON/OFF ADC interrupts. - * - * Input Parameters: - * dev - pointer to device structure used by the driver - * cmd - command - * arg - arguments passed with command - * - * Returned Value: - * - ****************************************************************************/ - -static int adc_ioc_change_ints(struct adc_dev_s *dev, int cmd, bool arg) -{ - struct stm32_dev_s *priv = (struct stm32_dev_s *)dev->ad_priv; - int ret = OK; - - switch (cmd) - { - case IO_ENABLE_DISABLE_AWDIE: - adc_ioc_enable_awd_int(priv, arg); - break; - - case IO_ENABLE_DISABLE_EOCIE: - adc_ioc_enable_eoc_int(priv, arg); - break; - - case IO_ENABLE_DISABLE_JEOCIE: - adc_ioc_enable_jeoc_int(priv, arg); - break; - - case IO_ENABLE_DISABLE_OVRIE: - adc_ioc_enable_ovr_int(priv, arg); - break; - - case IO_ENABLE_DISABLE_ALL_INTS: - adc_ioc_enable_awd_int(priv, arg); - adc_ioc_enable_eoc_int(priv, arg); - adc_ioc_enable_jeoc_int(priv, arg); - adc_ioc_enable_ovr_int(priv, arg); - break; - - default: - ainfo("unknown cmd: %d\n", cmd); - break; - } - - return ret; -} - -/**************************************************************************** - * Name: adc_ioc_wait_rcnr_zeroed - * - * Description: - * For the STM3215XX-family the ADC_SR_RCNR bit must be zeroed, - * before next conversion. - * - * Input Parameters: - * dev - pointer to device structure used by the driver - * - * Returned Value: - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_STM32L15XX -static int adc_ioc_wait_rcnr_zeroed(struct stm32_dev_s *priv) -{ - int i; - - for (i = 0; i < 30000; i++) - { - if ((adc_getreg(priv, STM32_ADC_SR_OFFSET) & ADC_SR_RCNR) == 0) - { - return OK; - } - } - - return -ENODATA; -} -#endif - -/**************************************************************************** - * Name: adc_enable_hsi - * - * Description: - * Enable/Disable HSI clock - * - * Input Parameters: - * enable - true : HSI clock for ADC enabled - * false : HSI clock for ADC disabled - * - * Returned Value: - * - ****************************************************************************/ - -#ifdef HAVE_HSI_CONTROL -static void adc_enable_hsi(bool enable) -{ - if (enable) - { - /* Enable the HSI */ - - stm32_modifyreg32(STM32_RCC_CR, 0, RCC_CR_HSION); - while ((getreg32(STM32_RCC_CR) & RCC_CR_HSIRDY) == 0); - } - else - { - /* Disable the HSI */ - - stm32_modifyreg32(STM32_RCC_CR, RCC_CR_HSION, 0); - } -} -#endif - -/**************************************************************************** - * Name: adc_sqrbits - ****************************************************************************/ - -static uint32_t adc_sqrbits(struct stm32_dev_s *priv, int first, - int last, int offset) -{ - uint32_t bits = 0; - int i; - - for (i = first - 1; - i < priv->rnchannels && i < last; - i++, offset += ADC_SQ_OFFSET) - { - bits |= (uint32_t)priv->r_chanlist[i] << offset; - } - - return bits; -} - -/**************************************************************************** - * Name: adc_set_ch - * - * Description: - * Sets the ADC channel. - * - * Input Parameters: - * dev - pointer to device structure used by the driver - * ch - ADC channel number + 1. 0 reserved for all configured channels - * - * Returned Value: - * int - errno - * - ****************************************************************************/ - -static int adc_set_ch(struct adc_dev_s *dev, uint8_t ch) -{ - struct stm32_dev_s *priv = (struct stm32_dev_s *)dev->ad_priv; - uint32_t bits; - int i; - - if (ch == 0) - { - priv->current = 0; - priv->rnchannels = priv->cr_channels; - } - else - { - for (i = 0; i < priv->cr_channels && priv->r_chanlist[i] != ch - 1; - i++); - - if (i >= priv->cr_channels) - { - return -ENODEV; - } - - priv->current = i; - priv->rnchannels = 1; - } - -#ifdef STM32_ADC_SQR5_OFFSET - bits = adc_sqrbits(priv, ADC_SQR5_FIRST, ADC_SQR5_LAST, - ADC_SQR5_SQ_OFFSET); - adc_modifyreg(priv, STM32_ADC_SQR5_OFFSET, ~ADC_SQR5_RESERVED, bits); -#endif - -#ifdef STM32_ADC_SQR4_OFFSET - bits = adc_sqrbits(priv, ADC_SQR4_FIRST, ADC_SQR4_LAST, - ADC_SQR4_SQ_OFFSET); - adc_modifyreg(priv, STM32_ADC_SQR4_OFFSET, ~ADC_SQR4_RESERVED, bits); -#endif - - bits = adc_sqrbits(priv, ADC_SQR3_FIRST, ADC_SQR3_LAST, - ADC_SQR3_SQ_OFFSET); - adc_modifyreg(priv, STM32_ADC_SQR3_OFFSET, ~ADC_SQR3_RESERVED, bits); - - bits = adc_sqrbits(priv, ADC_SQR2_FIRST, ADC_SQR2_LAST, - ADC_SQR2_SQ_OFFSET); - adc_modifyreg(priv, STM32_ADC_SQR2_OFFSET, ~ADC_SQR2_RESERVED, bits); - - bits = ((uint32_t)priv->rnchannels - 1) << ADC_SQR1_L_SHIFT; - bits |= adc_sqrbits(priv, ADC_SQR1_FIRST, - ADC_SQR1_LAST, ADC_SQR1_SQ_OFFSET); - adc_modifyreg(priv, STM32_ADC_SQR1_OFFSET, ~ADC_SQR1_RESERVED, bits); - - return OK; -} - -#ifdef ADC_HAVE_INJECTED - -/**************************************************************************** - * Name: adc_inj_set_ch - ****************************************************************************/ - -static int adc_inj_set_ch(struct adc_dev_s *dev, uint8_t ch) -{ - struct stm32_dev_s *priv = (struct stm32_dev_s *)dev->ad_priv; - uint32_t clrbits; - uint32_t setbits; - int i; - - /* Configure injected sequence length */ - - setbits = ADC_JSQR_JL(priv->cj_channels); - clrbits = ADC_JEXTREG_JEXTSEL_MASK | ADC_JSQR_JL_MASK; - - /* Configure injected channels */ - - for (i = 0 ; i < priv->cj_channels; i += 1) - { -#if defined(HAVE_IP_ADC_V1) - /* Injected channels sequence for for ADC IPv1: - * - * 1 2 3 4 - * IL=1: JSQR4, - * IL=2: JSQR3, JSQR4 - * IL=3: JSQR2, JSQR3, JSQR4 - * IL=4: JSQR1, JSQR2, JSQR3, JSQR4 - */ - - setbits |= (priv->j_chanlist[priv->cj_channels - 1 - i] << - (ADC_JSQR_JSQ4_SHIFT - ADC_JSQR_JSQ_SHIFT * i)); -#else - setbits |= priv->j_chanlist[i] << (ADC_JSQR_JSQ1_SHIFT + - ADC_JSQR_JSQ_SHIFT * i); -#endif - } - - /* Write register */ - - adc_modifyreg(priv, STM32_ADC_JSQR_OFFSET, clrbits, setbits); - - return OK; -} -#endif - -/**************************************************************************** - * Name: adc_ioctl - * - * Description: - * All ioctl calls will be routed through this method. - * - * Input Parameters: - * dev - pointer to device structure used by the driver - * cmd - command - * arg - arguments passed with command - * - * Returned Value: - * - ****************************************************************************/ - -static int adc_ioctl(struct adc_dev_s *dev, int cmd, unsigned long arg) -{ - struct stm32_dev_s *priv = (struct stm32_dev_s *)dev->ad_priv; - int ret = OK; - - switch (cmd) - { - case ANIOC_TRIGGER: - { - /* Start regular conversion if regular channels configured */ - - if (priv->anioc_trg & ANIOC_TRIGGER_REGULAR) - { - if (priv->cr_channels > 0) - { - adc_reg_startconv(priv, true); - } - } - -#ifdef ADC_HAVE_INJECTED - /* Start injected conversion if injected channels configured */ - - if (priv->anioc_trg & ANIOC_TRIGGER_INJECTED) - { - if (priv->cj_channels > 0) - { - adc_inj_startconv(priv, true); - } - } -#endif - - break; - } - - case ANIOC_GET_NCHANNELS: - { - /* Return the number of configured channels */ - - ret = priv->rnchannels; - } - break; - - case IO_TRIGGER_REG: - { - /* Start regular conversion if regular channels configured */ - - if (priv->cr_channels > 0) - { - adc_reg_startconv(priv, true); - } - - break; - } - -#ifdef ADC_HAVE_INJECTED - case IO_TRIGGER_INJ: - { - /* Start injected conversion if injected channels configured */ - - if (priv->cj_channels > 0) - { - adc_inj_startconv(priv, true); - } - - break; - } -#endif - - case IO_ENABLE_DISABLE_AWDIE: - case IO_ENABLE_DISABLE_EOCIE: - case IO_ENABLE_DISABLE_JEOCIE: - case IO_ENABLE_DISABLE_OVRIE: - case IO_ENABLE_DISABLE_ALL_INTS: - { - adc_ioc_change_ints(dev, cmd, *(bool *)arg); - break; - } - -#if defined(HAVE_IP_ADC_V1) - case IO_ENABLE_TEMPER_VOLT_CH: - { - adc_ioc_enable_tvref_register(dev, *(bool *)arg); - break; - } -#endif - -#ifdef HAVE_ADC_VBAT - case IO_ENABLE_DISABLE_VBAT_CH: - { - adc_enable_vbat_channel(dev, *(bool *)arg); - break; - } -#endif - -#ifdef HAVE_ADC_POWERDOWN - case IO_ENABLE_DISABLE_PDI: - case IO_ENABLE_DISABLE_PDD: - case IO_ENABLE_DISABLE_PDD_PDI: - { - adc_ioc_change_sleep_between_opers(dev, cmd, *(bool *)arg); - break; - } -#endif - - case IO_STOP_ADC: - { - adc_enable(priv, false); -#ifdef HAVE_HSI_CONTROL - adc_enable_hsi(false); -#endif - break; - } - - case IO_START_ADC: - { -#ifdef HAVE_HSI_CONTROL - adc_enable_hsi(true); -#endif - adc_enable(priv, true); - break; - } - - case IO_START_CONV: - { - uint8_t ch = ((uint8_t)arg); - -#ifdef CONFIG_STM32_STM32L15XX - ret = adc_ioc_wait_rcnr_zeroed(priv); - if (ret < 0) - { - return ret; - } -#endif - - ret = adc_set_ch(dev, ch); - if (ret < 0) - { - return ret; - } - -#ifdef CONFIG_ADC - if (ch) - { - /* Clear fifo if upper-half driver enabled */ - - dev->ad_recv.af_head = 0; - dev->ad_recv.af_tail = 0; - } -#endif - - adc_reg_startconv(priv, true); - break; - } - - default: - { - aerr("ERROR: Unknown cmd: %d\n", cmd); - ret = -ENOTTY; - break; - } - } - - return ret; -} - -#ifndef CONFIG_STM32_ADC_NOIRQ - -/**************************************************************************** - * Name: adc_interrupt - * - * Description: - * Common ADC interrupt handler. - * - * Input Parameters: - * - * Returned Value: - * - ****************************************************************************/ - -static int adc_interrupt(struct adc_dev_s *dev) -{ - struct stm32_dev_s *priv = (struct stm32_dev_s *)dev->ad_priv; - uint32_t regval; - uint32_t pending; - int32_t data; - - regval = adc_getreg(priv, STM32_ADC_ISR_OFFSET); - pending = regval & ADC_ISR_ALLINTS; - if (pending == 0) - { - return OK; - } - - /* Identifies the interruption AWD, OVR or EOC */ - - if ((regval & ADC_ISR_AWD) != 0) - { - awarn("WARNING: Analog Watchdog, Value converted out of range!\n"); - } - - if ((regval & ADC_ISR_OVR) != 0) - { - awarn("WARNING: Overrun has occurred!\n"); - } - - /* EOC: End of conversion */ - - if ((regval & ADC_ISR_EOC) != 0) - { - /* Read the converted value and clear EOC bit - * (It is cleared by reading the ADC_DR) - */ - - data = adc_getreg(priv, STM32_ADC_DR_OFFSET) & ADC_DR_RDATA_MASK; - - /* Verify that the upper-half driver has bound its callback functions */ - - if (priv->cb != NULL) - { - /* Give the ADC data to the ADC driver. The ADC receive() method - * accepts 3 parameters: - * - * 1) The first is the ADC device instance for this ADC block. - * 2) The second is the channel number for the data, and - * 3) The third is the converted data for the channel. - */ - - DEBUGASSERT(priv->cb->au_receive != NULL); - priv->cb->au_receive(dev, priv->r_chanlist[priv->current], data); - } - - /* Set the channel number of the next channel that will complete - * conversion. - */ - - priv->current++; - - if (priv->current >= priv->rnchannels) - { - /* Restart the conversion sequence from the beginning */ - - priv->current = 0; - } - } - - /* Clear pending interrupts */ - - adc_putreg(priv, STM32_ADC_ISR_OFFSET, pending); - - return OK; -} - -/**************************************************************************** - * Name: adc1_interrupt - * - * Description: - * ADC interrupt handler for the STM32 L15XX family. - * - * Input Parameters: - * irq - The IRQ number that generated the interrupt. - * context - Architecture specific register save information. - * - * Returned Value: - * - ****************************************************************************/ - -#if defined(STM32_IRQ_ADC1) -static int adc1_interrupt(int irq, void *context, void *arg) -{ - adc_interrupt(&g_adcdev1); - - return OK; -} -#endif - -/**************************************************************************** - * Name: adc12_interrupt - * - * Description: - * ADC1/2 interrupt handler for the STM32 F1/F3 families. - * - * Input Parameters: - * - * Returned Value: - * - ****************************************************************************/ - -#if defined(STM32_IRQ_ADC12) && \ - (defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2)) -static int adc12_interrupt(int irq, void *context, void *arg) -{ -#ifdef CONFIG_STM32_ADC1 - adc_interrupt(&g_adcdev1); -#endif - -#ifdef CONFIG_STM32_ADC2 - adc_interrupt(&g_adcdev2); -#endif - - return OK; -} -#endif - -/**************************************************************************** - * Name: adc3_interrupt - * - * Description: - * ADC3 interrupt handler for the STM32 F1 family. - * - * Input Parameters: - * - * Returned Value: - * - ****************************************************************************/ - -#if defined(STM32_IRQ_ADC3) && defined(CONFIG_STM32_ADC3) -static int adc3_interrupt(int irq, void *context, void *arg) -{ - adc_interrupt(&g_adcdev3); - - return OK; -} -#endif - -/**************************************************************************** - * Name: adc4_interrupt - * - * Description: - * ADC4 interrupt handler for the STM32 F3 family. - * - * Input Parameters: - * - * Returned Value: - * - ****************************************************************************/ - -#if defined(STM32_IRQ_ADC4) && defined(CONFIG_STM32_ADC4) -static int adc4_interrupt(int irq, void *context, void *arg) -{ - adc_interrupt(&g_adcdev4); - - return OK; -} -#endif - -/**************************************************************************** - * Name: adc123_interrupt - * - * Description: - * ADC1/2/3 interrupt handler for the STM32 F2/F4 families. - * - * Input Parameters: - * - * Returned Value: - * - ****************************************************************************/ - -#if defined(STM32_IRQ_ADC) -static int adc123_interrupt(int irq, void *context, void *arg) -{ -#ifdef CONFIG_STM32_ADC1 - adc_interrupt(&g_adcdev1); -#endif - -#ifdef CONFIG_STM32_ADC2 - adc_interrupt(&g_adcdev2); -#endif - -#ifdef CONFIG_STM32_ADC3 - adc_interrupt(&g_adcdev3); -#endif - - return OK; -} -#endif -#endif /* CONFIG_STM32_ADC_NOIRQ */ - -#ifdef CONFIG_STM32_ADC_LL_OPS - -/**************************************************************************** - * Name: adc_llops_setup - ****************************************************************************/ - -static int adc_llops_setup(struct stm32_adc_dev_s *dev) -{ - struct stm32_dev_s *priv = (struct stm32_dev_s *)dev; - - return adc_setup(priv->dev); -} - -/**************************************************************************** - * Name: adc_llops_shutdown - ****************************************************************************/ - -static void adc_llops_shutdown(struct stm32_adc_dev_s *dev) -{ - struct stm32_dev_s *priv = (struct stm32_dev_s *)dev; - - adc_shutdown(priv->dev); -} - -/**************************************************************************** - * Name: adc_intack - ****************************************************************************/ - -static void adc_intack(struct stm32_adc_dev_s *dev, uint32_t source) -{ - struct stm32_dev_s *priv = (struct stm32_dev_s *)dev; - - /* Clear pending interrupts */ - -#ifdef HAVE_IP_ADC_V2 - /* Cleared by writing 1 to it */ - - adc_putreg(priv, STM32_ADC_ISR_OFFSET, (source & ADC_ISR_ALLINTS)); -#else - /* Cleared by writing 0 to it */ - - adc_modifyreg(priv, STM32_ADC_ISR_OFFSET, (source & ADC_ISR_ALLINTS), 0); -#endif -} - -/**************************************************************************** - * Name: adc_inten - ****************************************************************************/ - -static void adc_inten(struct stm32_adc_dev_s *dev, uint32_t source) -{ - struct stm32_dev_s *priv = (struct stm32_dev_s *)dev; - - /* Enable interrupts */ - - adc_modifyreg(priv, STM32_ADC_IER_OFFSET, 0, (source & ADC_IER_ALLINTS)); -} - -/**************************************************************************** - * Name: adc_intdis - ****************************************************************************/ - -static void adc_intdis(struct stm32_adc_dev_s *dev, uint32_t source) -{ - struct stm32_dev_s *priv = (struct stm32_dev_s *)dev; - - /* Disable interrupts */ - - adc_modifyreg(priv, STM32_ADC_IER_OFFSET, (source & ADC_IER_ALLINTS), 0); -} - -/**************************************************************************** - * Name: adc_ackget - ****************************************************************************/ - -static uint32_t adc_intget(struct stm32_adc_dev_s *dev) -{ - struct stm32_dev_s *priv = (struct stm32_dev_s *)dev; - uint32_t regval; - uint32_t pending; - - regval = adc_getreg(priv, STM32_ADC_ISR_OFFSET); - pending = regval & ADC_ISR_ALLINTS; - - return pending; -} - -/**************************************************************************** - * Name: adc_regget - ****************************************************************************/ - -static uint32_t adc_regget(struct stm32_adc_dev_s *dev) -{ - struct stm32_dev_s *priv = (struct stm32_dev_s *)dev; - - return adc_getreg(priv, STM32_ADC_DR_OFFSET) & ADC_DR_RDATA_MASK; -} - -/**************************************************************************** - * Name: adc_llops_reg_startconv - ****************************************************************************/ - -static void adc_llops_reg_startconv(struct stm32_adc_dev_s *dev, - bool enable) -{ - struct stm32_dev_s *priv = (struct stm32_dev_s *)dev; - - adc_reg_startconv(priv, enable); -} - -/**************************************************************************** - * Name: adc_offset_set - ****************************************************************************/ - -#ifdef HAVE_IP_ADC_V2 -static int adc_offset_set(struct stm32_adc_dev_s *dev, uint8_t ch, - uint8_t i, uint16_t offset) -{ - struct stm32_dev_s *priv = (struct stm32_dev_s *)dev; - uint32_t regval = 0; - uint32_t reg = 0; - int ret = OK; - - if (i >= 4) - { - /* There are only four offset registers. */ - - ret = -E2BIG; - goto errout; - } - - reg = STM32_ADC_OFR1_OFFSET + i * 4; - - regval = ADC_OFR_OFFSETY_EN; - adc_putreg(priv, reg, regval); - - regval |= ADC_OFR_OFFSETY_CH(ch) | ADC_OFR_OFFSETY(offset); - adc_putreg(priv, reg, regval); - -errout: - return ret; -} -#else /* HAVE_IP_ADC_V1 */ -static int adc_offset_set(struct stm32_adc_dev_s *dev, uint8_t ch, - uint8_t i, uint16_t offset) -{ - struct stm32_dev_s *priv = (struct stm32_dev_s *)dev; - uint32_t reg = 0; - int ret = OK; - - /* WARNING: Offset only for injected channels! */ - - UNUSED(ch); - - if (i >= 4) - { - /* There are only four offset registers. */ - - ret = -E2BIG; - goto errout; - } - - reg = STM32_ADC_JOFR1_OFFSET + i * 4; - - adc_putreg(priv, reg, offset); - -errout: - return ret; -} -#endif - -/**************************************************************************** - * Name: adc_llops_extcfg_set - ****************************************************************************/ - -#ifdef ADC_HAVE_EXTCFG -static void adc_llops_extcfg_set(struct stm32_adc_dev_s *dev, - uint32_t extcfg) -{ - struct stm32_dev_s *priv = (struct stm32_dev_s *)dev; - - adc_extcfg_set(priv, extcfg); -} -#endif - -/**************************************************************************** - * Name: adc_llops_jextcfg_set - ****************************************************************************/ - -#ifdef ADC_HAVE_JEXTCFG -static void adc_llops_jextcfg_set(struct stm32_adc_dev_s *dev, - uint32_t jextcfg) -{ - struct stm32_dev_s *priv = (struct stm32_dev_s *)dev; - - adc_jextcfg_set(priv, jextcfg); -} -#endif - -/**************************************************************************** - * Name: adc_regbufregister - ****************************************************************************/ - -#ifdef ADC_HAVE_DMA -static int adc_regbufregister(struct stm32_adc_dev_s *dev, - uint16_t *buffer, uint8_t len) -{ - struct stm32_dev_s *priv = (struct stm32_dev_s *)dev; - - stm32_dmasetup(priv->dma, - priv->base + STM32_ADC_DR_OFFSET, - (uint32_t)buffer, - len, - ADC_DMA_CONTROL_WORD); - - /* No DMA callback */ - - stm32_dmastart(priv->dma, NULL, dev, false); - - return OK; -} -#endif /* ADC_HAVE_DMA */ - -/**************************************************************************** - * Name: adc_injget - ****************************************************************************/ - -#ifdef ADC_HAVE_INJECTED -static uint32_t adc_injget(struct stm32_adc_dev_s *dev, uint8_t chan) -{ - struct stm32_dev_s *priv = (struct stm32_dev_s *)dev; - uint32_t regval = 0; - - if (chan > (priv->cj_channels - 1)) - { - /* REVISIT: return valute with MSB set to indicate error ? */ - - goto errout; - } - - regval = adc_getreg(priv, STM32_ADC_JDR1_OFFSET + 4 * (chan)) & - ADC_JDR_JDATA_MASK; - -errout: - return regval; -} - -/**************************************************************************** - * Name: adc_llops_inj_startconv - ****************************************************************************/ - -static void adc_llops_inj_startconv(struct stm32_adc_dev_s *dev, - bool enable) -{ - struct stm32_dev_s *priv = (struct stm32_dev_s *)dev; - - adc_inj_startconv(priv, enable); -} - -#endif /* ADC_HAVE_INJECTED */ - -/**************************************************************************** - * Name: adc_sampletime_write - * - * Description: - * Writes previously defined values into ADC_SMPRx registers. - * - * Input Parameters: - * - * Returned Value: - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_ADC_CHANGE_SAMPLETIME -static void adc_sampletime_write(struct stm32_adc_dev_s *dev) -{ - struct stm32_dev_s *priv = (struct stm32_dev_s *)dev; - uint32_t value = 0; - uint8_t i; - uint8_t shift; - - /* Sampling time individually for each channel. - * It's different for families. - */ - - for (i = 0, shift = 0; i < priv->adc_channels; i++) - { - value |= priv->sample_rate[i] << (shift * 3); - switch (i) - { -#if defined(STM32_ADC_SMPR0_OFFSET) && defined(STM32_ADC_SMPR3_OFFSET) - case 9: - { - adc_putreg(priv, STM32_ADC_SMPR3_OFFSET, value); - shift = 0; - value = 0; - break; - } - - case 19: - { - adc_putreg(priv, STM32_ADC_SMPR2_OFFSET, value); - shift = 0; - value = 0; - break; - } - - case 29: - { - adc_putreg(priv, STM32_ADC_SMPR1_OFFSET, value); - shift = 0; - value = 0; - break; - } - - case (ADC_CHANNELS_NUMBER - 1): - { - adc_putreg(priv, STM32_ADC_SMPR0_OFFSET, value); - shift = 0; - value = 0; - break; - } - -#elif defined(STM32_ADC_SMPR1_OFFSET) && defined(STM32_ADC_SMPR2_OFFSET) - case (ADC_CHANNELS_NUMBER - 1): - { - adc_putreg(priv, STM32_ADC_SMPR2_OFFSET, value); - shift = 0; - value = 0; - break; - } - - case 9: - { - adc_putreg(priv, STM32_ADC_SMPR1_OFFSET, value); - shift = 0; - value = 0; - break; - } -#else -# error "Not supported SMPRx configuration" -#endif - - default: - { - shift++; - break; - } - } - } -} - -/**************************************************************************** - * Name: adc_sampletime_set - * - * Description: - * Changes sample times for specified channels. This method - * doesn't make any register writing. So, it's only stores the information. - * Values provided by user will be written in registers only on the next - * ADC peripheral start, as it was told to do in manual. However, before - * very first start, user can call this method and override default values - * either for every channels or for only some predefined by user channel(s) - * - * Input Parameters: - * dev - pointer to the adc device structure - * time_samples - pointe to the adc sample time configuration data - * - * Returned Value: - * None - * - ****************************************************************************/ - -void adc_sampletime_set(struct stm32_adc_dev_s *dev, - struct adc_sample_time_s *time_samples) -{ - struct stm32_dev_s *priv = (struct stm32_dev_s *)dev; - uint8_t ch_index; - uint8_t i; - - /* Check if user wants to assign the same value for all channels - * or just wants to change sample time values for certain channels - */ - - if (time_samples->all_same) - { - memset(priv->sample_rate, time_samples->all_ch_sample_time, - ADC_CHANNELS_NUMBER); - } - else - { - for (i = 0; i < time_samples->channels_nbr; i++) - { - ch_index = time_samples->channel[i].channel; - if (ch_index >= ADC_CHANNELS_NUMBER) - { - break; - } - - priv->sample_rate[ch_index] = time_samples->channel[i].sample_time; - } - } -} -#endif /* CONFIG_STM32_ADC_CHANGE_SAMPLETIME */ - -/**************************************************************************** - * Name: adc_llops_dumpregs - ****************************************************************************/ - -static void adc_llops_dumpregs(struct stm32_adc_dev_s *dev) -{ - struct stm32_dev_s *priv = (struct stm32_dev_s *)dev; - - adc_dumpregs(priv); -} - -/**************************************************************************** - * Name: adc_llops_multicfg - * - * IMPORTANT: this interface is allowed only when the ADCs are disabled! - * - ****************************************************************************/ - -static int adc_llops_multicfg(struct stm32_adc_dev_s *dev, uint8_t mode) -#if defined(HAVE_IP_ADC_V2) -{ - struct stm32_dev_s *priv = (struct stm32_dev_s *)dev; - int ret = OK; - uint32_t setbits = 0; - uint32_t clrbits = 0; - - switch (mode) - { - case ADC_MULTIMODE_INDEP: - setbits = ADC_CCR_DUAL_IND; - break; - - case ADC_MULTIMODE_RSISM2: - setbits = ADC_CCR_DUAL_SIMALT; - break; - - case ADC_MULTIMODE_RSATM2: - setbits = ADC_CCR_DUAL_SIMALT; - break; - - case ADC_MULTIMODE_IMIS2: - setbits = ADC_CCR_DUAL_INTINJ; - break; - - case ADC_MULTIMODE_ISM2: - setbits = ADC_CCR_DUAL_INJECTED; - break; - - case ADC_MULTIMODE_RSM2: - setbits = ADC_CCR_DUAL_SIM; - break; - - case ADC_MULTIMODE_IM2: - setbits = ADC_CCR_DUAL_INTERLEAVE; - break; - - case ADC_MULTIMODE_ATM2: - setbits = ADC_CCR_DUAL_ALT; - break; - - default: - ret = -EINVAL; - goto errout; - } - - clrbits = ADC_CCR_DUAL_MASK; - adccmn_modifyreg(priv, STM32_ADC_CCR_OFFSET, clrbits, setbits); - -errout: - return ret; -} -#elif defined(HAVE_IP_ADC_V1) && !defined(HAVE_BASIC_ADC) -{ - struct stm32_dev_s *priv = (struct stm32_dev_s *)dev; - int ret = OK; - uint32_t setbits = 0; - uint32_t clrbits = 0; - - switch (mode) - { - case ADC_MULTIMODE_INDEP: - setbits = ADC_CCR_MULTI_NONE; - break; - - case ADC_MULTIMODE_RSISM2: - setbits = ADC_CCR_MULTI_RSISM2; - break; - - case ADC_MULTIMODE_RSATM2: - setbits = ADC_CCR_MULTI_RSATM2; - break; - - case ADC_MULTIMODE_ISM2: - setbits = ADC_CCR_MULTI_ISM2; - break; - - case ADC_MULTIMODE_RSM2: - setbits = ADC_CCR_MULTI_ISM2; - break; - - case ADC_MULTIMODE_IM2: - setbits = ADC_CCR_MULTI_IM2; - break; - - case ADC_MULTIMODE_ATM2: - setbits = ADC_CCR_MULTI_ATM2; - break; - - case ADC_MULTIMODE_RSISM3: - setbits = ADC_CCR_MULTI_RSISM3; - break; - - case ADC_MULTIMODE_RSATM3: - setbits = ADC_CCR_MULTI_RSATM3; - break; - - case ADC_MULTIMODE_ISM3: - setbits = ADC_CCR_MULTI_ISM3; - break; - - case ADC_MULTIMODE_RSM3: - setbits = ADC_CCR_MULTI_ISM3; - break; - - case ADC_MULTIMODE_IM3: - setbits = ADC_CCR_MULTI_IM3; - break; - - case ADC_MULTIMODE_ATM3: - setbits = ADC_CCR_MULTI_ATM3; - break; - - case ADC_MULTIMODE_IMIS2: - case ADC_MULTIMODE_IMIS3: - default: - ret = -EINVAL; - goto errout; - } - - clrbits = ADC_CCR_MULTI_MASK; - adccmn_modifyreg(priv, STM32_ADC_CCR_OFFSET, clrbits, setbits); - -errout: - return ret; -} -#else /* ADV IPv1 BASIC */ -{ - if (mode != ADC_MULTIMODE_INDEP) - { - return -EINVAL; - } - - return OK; -} -#endif - -/**************************************************************************** - * Name: adc_llops_enable - ****************************************************************************/ - -static void adc_llops_enable(struct stm32_adc_dev_s *dev, bool enable) -{ - struct stm32_dev_s *priv = (struct stm32_dev_s *)dev; - - adc_enable(priv, enable); -} - -#endif /* CONFIG_STM32_ADC_LL_OPS */ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_adcinitialize - * - * Description: - * Initialize the ADC. - * - * The logic allow initialize ADC regular and injected channels. - * - * The number of injected channels for given ADC is selected from Kconfig - * with CONFIG_STM32_ADCx_INJECTED_CHAN definitions - * - * The number of regular channels is obtained from the equation: - * - * cr_channels = channels - cj_channels - * - * where: - * cr_channels - regular channels - * cj_channels - injected channels - * channels - this function parameter - * - * The chanlist array store both regular channels and injected channels - * configuration so that regular channels are the first in order: - * - * # regular channels start from here - * chanlist[0] -> ADC_SQRx_SQ1 - * chanlist[1] -> ADC_SQRx_SQ2 - * ... - * # injected channels start from here - * chanlist[channels - (y - 1)] -> ADC_JSQR_JSQ1 - * ... - * chanlist[channels] -> ADC_JSQR_ISQy - * - * where: - * y = CONFIG_STM32_ADCx_INJECTED_CHAN, and y > 0 - * - * If CONFIG_STM32_ADCx_INJECTED_CHAN = 0, then all channels from chanlist - * are regular channels. - * - * Input Parameters: - * intf - Could be {1,2,3,4} for ADC1, ADC2, ADC3 or ADC4 - * chanlist - The list of channels (regular + injected) - * channels - Number of channels (regular + injected) - * - * Returned Value: - * Valid ADC device structure reference on success; a NULL on failure - * - ****************************************************************************/ - -struct adc_dev_s *stm32_adcinitialize(int intf, const uint8_t *chanlist, - int channels) -{ - struct adc_dev_s *dev; - struct stm32_dev_s *priv; - uint8_t cr_channels = 0; - uint8_t cj_channels = 0; -#ifdef ADC_HAVE_INJECTED - uint8_t *j_chanlist = NULL; -#endif - - switch (intf) - { -#ifdef CONFIG_STM32_ADC1 - case 1: - { - ainfo("ADC1 selected\n"); - dev = &g_adcdev1; - cj_channels = CONFIG_STM32_ADC1_INJECTED_CHAN; - cr_channels = channels - cj_channels; -# ifdef ADC_HAVE_INJECTED - if (cj_channels > 0) - { - j_chanlist = (uint8_t *)chanlist + cr_channels; - } -# endif - break; - } - -#endif /* CONFIG_STM32_ADC1 */ -#ifdef CONFIG_STM32_ADC2 - case 2: - { - ainfo("ADC2 selected\n"); - dev = &g_adcdev2; - cj_channels = CONFIG_STM32_ADC2_INJECTED_CHAN; - cr_channels = channels - cj_channels; -# ifdef ADC_HAVE_INJECTED - if (cj_channels > 0) - { - j_chanlist = (uint8_t *)chanlist + cr_channels; - } -# endif - break; - } - -#endif /* CONFIG_STM32_ADC2 */ -#ifdef CONFIG_STM32_ADC3 - case 3: - { - ainfo("ADC3 selected\n"); - dev = &g_adcdev3; - cj_channels = CONFIG_STM32_ADC3_INJECTED_CHAN; - cr_channels = channels - cj_channels; -# ifdef ADC_HAVE_INJECTED - if (cj_channels > 0) - { - j_chanlist = (uint8_t *)chanlist + cr_channels; - } -# endif - break; - } - -#endif /* CONFIG_STM32_ADC3 */ -#ifdef CONFIG_STM32_ADC4 - case 4: - { - ainfo("ADC4 selected\n"); - dev = &g_adcdev4; - cj_channels = CONFIG_STM32_ADC4_INJECTED_CHAN; - cr_channels = channels - cj_channels; -# ifdef ADC_HAVE_INJECTED - if (cj_channels > 0) - { - j_chanlist = (uint8_t *)chanlist + cr_channels; - } -# endif - break; - } - -#endif /* CONFIG_STM32_ADC4 */ - default: - { - aerr("ERROR: No ADC interface defined\n"); - return NULL; - } - } - - /* Configure the selected ADC */ - - priv = (struct stm32_dev_s *)dev->ad_priv; - - /* Configure regular channels */ - - DEBUGASSERT(cr_channels <= CONFIG_STM32_ADC_MAX_SAMPLES); - if (cr_channels > CONFIG_STM32_ADC_MAX_SAMPLES) - { - cr_channels = CONFIG_STM32_ADC_MAX_SAMPLES; - } - - priv->cr_channels = cr_channels; - memcpy(priv->r_chanlist, chanlist, cr_channels); - -#ifdef ADC_HAVE_INJECTED - /* Configure injected channels */ - - DEBUGASSERT(cj_channels <= ADC_INJ_MAX_SAMPLES); - if (cj_channels > ADC_INJ_MAX_SAMPLES) - { - cj_channels = ADC_INJ_MAX_SAMPLES; - } - - priv->cj_channels = cj_channels; - memcpy(priv->j_chanlist, j_chanlist, cj_channels); -#endif - -#ifdef CONFIG_STM32_ADC_CHANGE_SAMPLETIME - /* Assign default values for the sample time table */ - - memset(priv->sample_rate, ADC_SMPR_DEFAULT, ADC_CHANNELS_NUMBER); - priv->adc_channels = ADC_CHANNELS_NUMBER; -#endif - -#ifdef CONFIG_STM32_ADC_LL_OPS - /* Store reference to the upper-half ADC device */ - - priv->dev = dev; -#endif - -#ifdef ADC_HAVE_INJECTED - ainfo("intf: %d cr_channels: %d, cj_channels: %d\n", - intf, priv->cr_channels, priv->cj_channels); -#else - ainfo("intf: %d cr_channels: %d\n", intf, priv->cr_channels); -#endif - - return dev; -} - -#endif /* CONFIG_STM32_ADC */ diff --git a/arch/arm/src/stm32/stm32_adc.h b/arch/arm/src/stm32/stm32_adc.h deleted file mode 100644 index 05c5bdf48013f..0000000000000 --- a/arch/arm/src/stm32/stm32_adc.h +++ /dev/null @@ -1,2345 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_adc.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32_STM32_ADC_H -#define __ARCH_ARM_SRC_STM32_STM32_ADC_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "chip.h" - -#include "hardware/stm32_adc.h" - -#include - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Generalized definitions for ADC *****************************************/ - -#if defined(HAVE_IP_ADC_V1) -# define STM32_ADC_DMAREG_OFFSET STM32_ADC_CR2_OFFSET -# define ADC_DMAREG_DMA ADC_CR2_DMA -# define STM32_ADC_EXTREG_OFFSET STM32_ADC_CR2_OFFSET -# define ADC_EXTREG_EXTSEL_MASK ADC_CR2_EXTSEL_MASK -# define ADC_EXTREG_EXTSEL_SHIFT ADC_CR2_EXTSEL_SHIFT -# define STM32_ADC_JEXTREG_OFFSET STM32_ADC_CR2_OFFSET -# define ADC_JEXTREG_JEXTSEL_MASK ADC_CR2_JEXTSEL_MASK -# define ADC_EXTREG_JEXTSEL_SHIFT ADC_CR2_JEXTSEL_SHIFT -# define STM32_ADC_ISR_OFFSET STM32_ADC_SR_OFFSET -# define STM32_ADC_IER_OFFSET STM32_ADC_CR1_OFFSET -# ifdef HAVE_BASIC_ADC -# define ADC_EXTREG_EXTEN_MASK ADC_CR2_EXTTRIG -# define ADC_EXTREG_EXTEN_NONE 0 -# define ADC_EXTREG_EXTEN_DEFAULT ADC_CR2_EXTTRIG -# define ADC_JEXTREG_JEXTEN_MASK ADC_CR2_JEXTTRIG -# define ADC_JEXTREG_JEXTEN_NONE 0 -# define ADC_JEXTREG_JEXTEN_DEFAULT ADC_CR2_JEXTTRIG -# else -# define ADC_EXTREG_EXTEN_MASK ADC_CR2_EXTEN_MASK -# define ADC_EXTREG_EXTEN_NONE ADC_CR2_EXTEN_NONE -# define ADC_EXTREG_EXTEN_DEFAULT ADC_CR2_EXTEN_RISING -# define ADC_JEXTREG_JEXTEN_MASK ADC_CR2_JEXTEN_MASK -# define ADC_JEXTREG_JEXTEN_NONE ADC_CR2_JEXTEN_NONE -# define ADC_JEXTREG_JEXTEN_DEFAULT ADC_CR2_JEXTEN_RISING -# endif -#elif defined(HAVE_IP_ADC_V2) -# define STM32_ADC_DMAREG_OFFSET STM32_ADC_CFGR1_OFFSET -# define ADC_DMAREG_DMA ADC_CFGR1_DMAEN -# define STM32_ADC_EXTREG_OFFSET STM32_ADC_CFGR1_OFFSET -# define ADC_EXTREG_EXTSEL_MASK ADC_CFGR1_EXTSEL_MASK -# define ADC_EXTREG_EXTSEL_SHIFT ADC_CFGR1_EXTSEL_SHIFT -# define ADC_EXTREG_EXTEN_MASK ADC_CFGR1_EXTEN_MASK -# define ADC_EXTREG_EXTEN_DEFAULT ADC_CFGR1_EXTEN_RISING -# define STM32_ADC_JEXTREG_OFFSET STM32_ADC_JSQR_OFFSET -# define ADC_JEXTREG_JEXTSEL_MASK ADC_JSQR_JEXTSEL_MASK -# define ADC_EXTREG_JEXTSEL_SHIFT ADC_JSQR_JEXTSEL_SHIFT -# define ADC_JEXTREG_JEXTEN_MASK ADC_JSQR_JEXTEN_MASK -# define ADC_JEXTREG_JEXTEN_DEFAULT ADC_JSQR_JEXTEN_RISING -#endif - -/* Configuration ************************************************************/ - -/* Timer devices may be used for different purposes. One special purpose is - * to control periodic ADC sampling. If CONFIG_STM32_TIMn is defined then - * CONFIG_STM32_TIMn_ADC must also be defined to indicate that timer "n" is - * intended to be used for that purpose. - */ - -/* For the STM32 F1 line, timers 1-4 may be used. - * For the STM32 F3 line, timers 1-4, 6-8, 15, 20 may be used. - * For the STM32 F2/F4 lines, timers 1-5 and 8 may be used. - * For the STM32L15XX line, timers 2-4, 6, 7, 9, 10 may be used. - */ - -#ifdef CONFIG_STM32_STM32L15XX -# undef CONFIG_STM32_TIM1_ADC -# undef CONFIG_STM32_TIM1_ADC1 -# undef CONFIG_STM32_TIM1_ADC2 -# undef CONFIG_STM32_TIM1_ADC3 -# undef CONFIG_STM32_TIM1_ADC4 -#else -# ifndef CONFIG_STM32_TIM1 -# undef CONFIG_STM32_TIM1_ADC -# undef CONFIG_STM32_TIM1_ADC1 -# undef CONFIG_STM32_TIM1_ADC2 -# undef CONFIG_STM32_TIM1_ADC3 -# undef CONFIG_STM32_TIM1_ADC4 -# endif -#endif - -#ifndef CONFIG_STM32_TIM2 -# undef CONFIG_STM32_TIM2_ADC -# undef CONFIG_STM32_TIM2_ADC1 -# undef CONFIG_STM32_TIM2_ADC2 -# undef CONFIG_STM32_TIM2_ADC3 -# undef CONFIG_STM32_TIM2_ADC4 -#endif -#ifndef CONFIG_STM32_TIM3 -# undef CONFIG_STM32_TIM3_ADC -# undef CONFIG_STM32_TIM3_ADC1 -# undef CONFIG_STM32_TIM3_ADC2 -# undef CONFIG_STM32_TIM3_ADC3 -# undef CONFIG_STM32_TIM3_ADC4 -#endif -#ifndef CONFIG_STM32_TIM4 -# undef CONFIG_STM32_TIM4_ADC -# undef CONFIG_STM32_TIM4_ADC1 -# undef CONFIG_STM32_TIM4_ADC2 -# undef CONFIG_STM32_TIM4_ADC3 -# undef CONFIG_STM32_TIM4_ADC4 -#endif - -#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) -# ifndef CONFIG_STM32_TIM5 -# undef CONFIG_STM32_TIM5_ADC -# undef CONFIG_STM32_TIM5_ADC1 -# undef CONFIG_STM32_TIM5_ADC2 -# undef CONFIG_STM32_TIM5_ADC3 -# undef CONFIG_STM32_TIM5_ADC4 -# endif -#else -# undef CONFIG_STM32_TIM5_ADC -# undef CONFIG_STM32_TIM5_ADC1 -# undef CONFIG_STM32_TIM5_ADC2 -# undef CONFIG_STM32_TIM5_ADC3 -# undef CONFIG_STM32_TIM5_ADC4 -#endif - -#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F30XX) || \ - defined(CONFIG_STM32_STM32F4XXX) -# ifndef CONFIG_STM32_TIM8 -# undef CONFIG_STM32_TIM8_ADC -# undef CONFIG_STM32_TIM8_ADC1 -# undef CONFIG_STM32_TIM8_ADC2 -# undef CONFIG_STM32_TIM8_ADC3 -# undef CONFIG_STM32_TIM8_ADC4 -# endif -#else -# undef CONFIG_STM32_TIM8_ADC -# undef CONFIG_STM32_TIM8_ADC1 -# undef CONFIG_STM32_TIM8_ADC2 -# undef CONFIG_STM32_TIM8_ADC3 -# undef CONFIG_STM32_TIM8_ADC4 -#endif - -/* Timers 6, 7, 9, 10 used by STM32L15XX family devices. Though there is only - * ADC presented in specification and in device as well, the ADC1 is used - * here in code. See definition of the STM32_NADC - */ - -#if defined(CONFIG_STM32_STM32L15XX) || defined(CONFIG_STM32_STM32F30XX) -# ifndef CONFIG_STM32_TIM6 -# undef CONFIG_STM32_TIM6_ADC -# undef CONFIG_STM32_TIM6_ADC1 -# undef CONFIG_STM32_TIM6_ADC2 -# undef CONFIG_STM32_TIM6_ADC3 -# undef CONFIG_STM32_TIM6_ADC4 -# endif -# ifndef CONFIG_STM32_TIM7 -# undef CONFIG_STM32_TIM7_ADC -# undef CONFIG_STM32_TIM7_ADC1 -# undef CONFIG_STM32_TIM7_ADC2 -# undef CONFIG_STM32_TIM7_ADC3 -# undef CONFIG_STM32_TIM7_ADC4 -# endif -#else -# undef CONFIG_STM32_TIM6_ADC -# undef CONFIG_STM32_TIM6_ADC1 -# undef CONFIG_STM32_TIM6_ADC2 -# undef CONFIG_STM32_TIM6_ADC3 -# undef CONFIG_STM32_TIM6_ADC4 -# undef CONFIG_STM32_TIM7_ADC -# undef CONFIG_STM32_TIM7_ADC1 -# undef CONFIG_STM32_TIM7_ADC2 -# undef CONFIG_STM32_TIM7_ADC3 -# undef CONFIG_STM32_TIM7_ADC4 -#endif - -#if defined(CONFIG_STM32_STM32L15XX) -# ifndef CONFIG_STM32_TIM9 -# undef CONFIG_STM32_TIM9_ADC -# undef CONFIG_STM32_TIM9_ADC1 -# undef CONFIG_STM32_TIM9_ADC2 -# undef CONFIG_STM32_TIM9_ADC3 -# undef CONFIG_STM32_TIM9_ADC4 -# endif -# ifndef CONFIG_STM32_TIM10 -# undef CONFIG_STM32_TIM10_ADC -# undef CONFIG_STM32_TIM10_ADC1 -# undef CONFIG_STM32_TIM10_ADC2 -# undef CONFIG_STM32_TIM10_ADC3 -# undef CONFIG_STM32_TIM10_ADC4 -# endif -#else -# undef CONFIG_STM32_TIM9_ADC -# undef CONFIG_STM32_TIM9_ADC1 -# undef CONFIG_STM32_TIM9_ADC2 -# undef CONFIG_STM32_TIM9_ADC3 -# undef CONFIG_STM32_TIM9_ADC4 -# undef CONFIG_STM32_TIM10_ADC -# undef CONFIG_STM32_TIM10_ADC1 -# undef CONFIG_STM32_TIM10_ADC2 -# undef CONFIG_STM32_TIM10_ADC3 -# undef CONFIG_STM32_TIM10_ADC4 -#endif - -/* Timers 6, 7, and 10-14 are not used with the ADC by any supported family - */ - -#undef CONFIG_STM32_TIM11_ADC -#undef CONFIG_STM32_TIM11_ADC1 -#undef CONFIG_STM32_TIM11_ADC2 -#undef CONFIG_STM32_TIM11_ADC3 -#undef CONFIG_STM32_TIM11_ADC4 -#undef CONFIG_STM32_TIM12_ADC -#undef CONFIG_STM32_TIM12_ADC1 -#undef CONFIG_STM32_TIM12_ADC2 -#undef CONFIG_STM32_TIM12_ADC3 -#undef CONFIG_STM32_TIM12_ADC4 -#undef CONFIG_STM32_TIM13_ADC -#undef CONFIG_STM32_TIM13_ADC1 -#undef CONFIG_STM32_TIM13_ADC2 -#undef CONFIG_STM32_TIM13_ADC3 -#undef CONFIG_STM32_TIM13_ADC4 -#undef CONFIG_STM32_TIM14_ADC -#undef CONFIG_STM32_TIM14_ADC1 -#undef CONFIG_STM32_TIM14_ADC2 -#undef CONFIG_STM32_TIM14_ADC3 -#undef CONFIG_STM32_TIM14_ADC4 - -#ifdef CONFIG_STM32_STM32F30XX -# ifndef CONFIG_STM32_TIM15 -# undef CONFIG_STM32_TIM15_ADC -# undef CONFIG_STM32_TIM15_ADC1 -# undef CONFIG_STM32_TIM15_ADC2 -# undef CONFIG_STM32_TIM15_ADC3 -# undef CONFIG_STM32_TIM15_ADC4 -# endif -# ifndef CONFIG_STM32_TIM20 -# undef CONFIG_STM32_TIM20_ADC -# undef CONFIG_STM32_TIM20_ADC1 -# undef CONFIG_STM32_TIM20_ADC2 -# undef CONFIG_STM32_TIM20_ADC3 -# undef CONFIG_STM32_TIM20_ADC4 -# endif -#else -# undef CONFIG_STM32_TIM15_ADC -# undef CONFIG_STM32_TIM15_ADC1 -# undef CONFIG_STM32_TIM15_ADC2 -# undef CONFIG_STM32_TIM15_ADC3 -# undef CONFIG_STM32_TIM15_ADC4 -# undef CONFIG_STM32_TIM20_ADC -# undef CONFIG_STM32_TIM20_ADC1 -# undef CONFIG_STM32_TIM20_ADC2 -# undef CONFIG_STM32_TIM20_ADC3 -# undef CONFIG_STM32_TIM20_ADC4 -#endif - -/* Up to 4 ADC interfaces are supported */ - -#if STM32_NADC < 4 -# undef CONFIG_STM32_ADC4 -#endif - -#if STM32_NADC < 3 -# undef CONFIG_STM32_ADC3 -#endif - -#if STM32_NADC < 2 -# undef CONFIG_STM32_ADC2 -#endif - -#if STM32_NADC < 1 -# undef CONFIG_STM32_ADC1 -#endif - -#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) || \ - defined(CONFIG_STM32_ADC3) || defined(CONFIG_STM32_ADC4) - -/* DMA support */ - -#undef ADC_HAVE_DMA -#if defined(CONFIG_STM32_ADC1_DMA) || defined(CONFIG_STM32_ADC2_DMA) || \ - defined(CONFIG_STM32_ADC3_DMA) || defined(CONFIG_STM32_ADC4_DMA) -# define ADC_HAVE_DMA 1 -#endif - -#ifdef CONFIG_STM32_ADC1_DMA -# define ADC1_HAVE_DMA 1 -#else -# undef ADC1_HAVE_DMA -#endif - -#ifdef CONFIG_STM32_ADC2_DMA -# define ADC2_HAVE_DMA 1 -#else -# undef ADC2_HAVE_DMA -#endif - -#ifdef CONFIG_STM32_ADC3_DMA -# define ADC3_HAVE_DMA 1 -#else -# undef ADC3_HAVE_DMA -#endif - -#ifdef CONFIG_STM32_ADC4_DMA -# define ADC4_HAVE_DMA 1 -#else -# undef ADC4_HAVE_DMA -#endif - -/* Injected channels support */ - -#if (defined(CONFIG_STM32_ADC1) && (CONFIG_STM32_ADC1_INJECTED_CHAN > 0)) || \ - (defined(CONFIG_STM32_ADC2) && (CONFIG_STM32_ADC2_INJECTED_CHAN > 0)) || \ - (defined(CONFIG_STM32_ADC3) && (CONFIG_STM32_ADC3_INJECTED_CHAN > 0)) || \ - (defined(CONFIG_STM32_ADC4) && (CONFIG_STM32_ADC4_INJECTED_CHAN > 0)) -# define ADC_HAVE_INJECTED -#endif - -/* Timer configuration: If a timer trigger is specified, then get - * information about the timer. - * - * STM32L15XX-family has only one ADC onboard, thus there is no definition - * for other 3 ADC's - */ - -#if defined(CONFIG_STM32_TIM1_ADC1) -# define ADC1_HAVE_TIMER 1 -# define ADC1_TIMER_BASE STM32_TIM1_BASE -# define ADC1_TIMER_PCLK_FREQUENCY STM32_APB2_TIM1_CLKIN -#elif defined(CONFIG_STM32_TIM2_ADC1) -# define ADC1_HAVE_TIMER 1 -# define ADC1_TIMER_BASE STM32_TIM2_BASE -# define ADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM2_CLKIN -#elif defined(CONFIG_STM32_TIM3_ADC1) -# define ADC1_HAVE_TIMER 1 -# define ADC1_TIMER_BASE STM32_TIM3_BASE -# define ADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM3_CLKIN -#elif defined(CONFIG_STM32_TIM4_ADC1) -# define ADC1_HAVE_TIMER 1 -# define ADC1_TIMER_BASE STM32_TIM4_BASE -# define ADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM4_CLKIN -#elif defined(CONFIG_STM32_TIM5_ADC1) -# define ADC1_HAVE_TIMER 1 -# define ADC1_TIMER_BASE STM32_TIM5_BASE -# define ADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM5_CLKIN -#elif defined(CONFIG_STM32_TIM6_ADC1) -# define ADC1_HAVE_TIMER 1 -# define ADC1_TIMER_BASE STM32_TIM6_BASE -# define ADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM6_CLKIN -#elif defined(CONFIG_STM32_TIM7_ADC1) -# define ADC1_HAVE_TIMER 1 -# define ADC1_TIMER_BASE STM32_TIM7_BASE -# define ADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM7_CLKIN -#elif defined(CONFIG_STM32_TIM8_ADC1) -# define ADC1_HAVE_TIMER 1 -# define ADC1_TIMER_BASE STM32_TIM8_BASE -# define ADC1_TIMER_PCLK_FREQUENCY STM32_APB2_TIM8_CLKIN -#elif defined(CONFIG_STM32_TIM9_ADC1) -# define ADC1_HAVE_TIMER 1 -# define ADC1_TIMER_BASE STM32_TIM9_BASE -# define ADC1_TIMER_PCLK_FREQUENCY STM32_APB2_TIM9_CLKIN -#elif defined(CONFIG_STM32_TIM10_ADC1) -# define ADC1_HAVE_TIMER 1 -# define ADC1_TIMER_BASE STM32_TIM10_BASE -# define ADC1_TIMER_PCLK_FREQUENCY STM32_APB2_TIM10_CLKIN -#elif defined(CONFIG_STM32_TIM15_ADC1) -# define ADC1_HAVE_TIMER 1 -# define ADC1_TIMER_BASE STM32_TIM15_BASE -# define ADC1_TIMER_PCLK_FREQUENCY STM32_APB2_TIM15_CLKIN -#else -# undef ADC1_HAVE_TIMER -#endif - -#ifdef ADC1_HAVE_TIMER -# ifndef CONFIG_STM32_ADC1_SAMPLE_FREQUENCY -# error "CONFIG_STM32_ADC1_SAMPLE_FREQUENCY not defined" -# endif -# ifndef CONFIG_STM32_ADC1_TIMTRIG -# error "CONFIG_STM32_ADC1_TIMTRIG not defined" -# warning "Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO 5:TRGO2" -# endif -#endif - -#if defined(CONFIG_STM32_HRTIM_ADC1_TRG1) || defined(CONFIG_STM32_HRTIM_ADC1_TRG2) || \ - defined(CONFIG_STM32_HRTIM_ADC3_TRG3) || defined(CONFIG_STM32_HRTIM_ADC4_TRG4) -# define ADC1_HAVE_HRTIM -#else -# undef ADC1_HAVE_HRTIM -#endif - -#if defined(CONFIG_STM32_TIM1_ADC2) -# define ADC2_HAVE_TIMER 1 -# define ADC2_TIMER_BASE STM32_TIM1_BASE -# define ADC2_TIMER_PCLK_FREQUENCY STM32_APB2_TIM1_CLKIN -#elif defined(CONFIG_STM32_TIM2_ADC2) -# define ADC2_HAVE_TIMER 1 -# define ADC2_TIMER_BASE STM32_TIM2_BASE -# define ADC2_TIMER_PCLK_FREQUENCY STM32_APB1_TIM2_CLKIN -#elif defined(CONFIG_STM32_TIM3_ADC2) -# define ADC2_HAVE_TIMER 1 -# define ADC2_TIMER_BASE STM32_TIM3_BASE -# define ADC2_TIMER_PCLK_FREQUENCY STM32_APB1_TIM3_CLKIN -#elif defined(CONFIG_STM32_TIM4_ADC2) -# define ADC2_HAVE_TIMER 1 -# define ADC2_TIMER_BASE STM32_TIM4_BASE -# define ADC2_TIMER_PCLK_FREQUENCY STM32_APB1_TIM4_CLKIN -#elif defined(CONFIG_STM32_TIM5_ADC2) -# define ADC2_HAVE_TIMER 1 -# define ADC2_TIMER_BASE STM32_TIM5_BASE -# define ADC2_TIMER_PCLK_FREQUENCY STM32_APB1_TIM5_CLKIN -#elif defined(CONFIG_STM32_TIM6_ADC2) -# define ADC2_HAVE_TIMER 1 -# define ADC2_TIMER_BASE STM32_TIM6_BASE -# define ADC2_TIMER_PCLK_FREQUENCY STM32_APB1_TIM6_CLKIN -#elif defined(CONFIG_STM32_TIM8_ADC2) -# define ADC2_HAVE_TIMER 1 -# define ADC2_TIMER_BASE STM32_TIM8_BASE -# define ADC2_TIMER_PCLK_FREQUENCY STM32_APB2_TIM8_CLKIN -#elif defined(CONFIG_STM32_TIM15_ADC2) -# define ADC2_HAVE_TIMER 1 -# define ADC2_TIMER_BASE STM32_TIM15_BASE -# define ADC2_TIMER_PCLK_FREQUENCY STM32_APB2_TIM15_CLKIN -#else -# undef ADC2_HAVE_TIMER -#endif - -#ifdef ADC2_HAVE_TIMER -# ifndef CONFIG_STM32_ADC2_SAMPLE_FREQUENCY -# error "CONFIG_STM32_ADC2_SAMPLE_FREQUENCY not defined" -# endif -# ifndef CONFIG_STM32_ADC2_TIMTRIG -# error "CONFIG_STM32_ADC2_TIMTRIG not defined" -# warning "Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO 5:TRGO2" -# endif -#endif - -#if defined(CONFIG_STM32_HRTIM_ADC2_TRG1) || defined(CONFIG_STM32_HRTIM_ADC2_TRG2) || \ - defined(CONFIG_STM32_HRTIM_ADC2_TRG3) || defined(CONFIG_STM32_HRTIM_ADC2_TRG4) -# define ADC2_HAVE_HRTIM -#else -# undef ADC2_HAVE_HRTIM -#endif - -#if defined(CONFIG_STM32_TIM1_ADC3) -# define ADC3_HAVE_TIMER 1 -# define ADC3_TIMER_BASE STM32_TIM1_BASE -# define ADC3_TIMER_PCLK_FREQUENCY STM32_APB2_TIM1_CLKIN -#elif defined(CONFIG_STM32_TIM2_ADC3) -# define ADC3_HAVE_TIMER 1 -# define ADC3_TIMER_BASE STM32_TIM2_BASE -# define ADC3_TIMER_PCLK_FREQUENCY STM32_APB1_TIM2_CLKIN -#elif defined(CONFIG_STM32_TIM3_ADC3) -# define ADC3_HAVE_TIMER 1 -# define ADC3_TIMER_BASE STM32_TIM3_BASE -# define ADC3_TIMER_PCLK_FREQUENCY STM32_APB1_TIM3_CLKIN -#elif defined(CONFIG_STM32_TIM4_ADC3) -# define ADC3_HAVE_TIMER 1 -# define ADC3_TIMER_BASE STM32_TIM4_BASE -# define ADC3_TIMER_PCLK_FREQUENCY STM32_APB1_TIM4_CLKIN -#elif defined(CONFIG_STM32_TIM5_ADC3) -# define ADC3_HAVE_TIMER 1 -# define ADC3_TIMER_BASE STM32_TIM5_BASE -# define ADC3_TIMER_PCLK_FREQUENCY STM32_APB1_TIM5_CLKIN -#elif defined(CONFIG_STM32_TIM7_ADC3) -# define ADC3_HAVE_TIMER 1 -# define ADC3_TIMER_BASE STM32_TIM7_BASE -# define ADC3_TIMER_PCLK_FREQUENCY STM32_APB1_TIM7_CLKIN -#elif defined(CONFIG_STM32_TIM8_ADC3) -# define ADC3_HAVE_TIMER 1 -# define ADC3_TIMER_BASE STM32_TIM8_BASE -# define ADC3_TIMER_PCLK_FREQUENCY STM32_APB2_TIM8_CLKIN -#elif defined(CONFIG_STM32_TIM15_ADC3) -# define ADC3_HAVE_TIMER 1 -# define ADC3_TIMER_BASE STM32_TIM15_BASE -# define ADC3_TIMER_PCLK_FREQUENCY STM32_APB2_TIM15_CLKIN -#elif defined(CONFIG_STM32_TIM20_ADC3) -# define ADC3_HAVE_TIMER 1 -# define ADC3_TIMER_BASE STM32_TIM20_BASE -# define ADC3_TIMER_PCLK_FREQUENCY STM32_APB2_TIM20_CLKIN -#else -# undef ADC3_HAVE_TIMER -#endif - -#ifdef ADC3_HAVE_TIMER -# ifndef CONFIG_STM32_ADC3_SAMPLE_FREQUENCY -# error "CONFIG_STM32_ADC3_SAMPLE_FREQUENCY not defined" -# endif -# ifndef CONFIG_STM32_ADC3_TIMTRIG -# error "CONFIG_STM32_ADC3_TIMTRIG not defined" -# warning "Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO 5:TRGO2" -# endif -#endif - -#if defined(CONFIG_STM32_TIM1_ADC4) -# define ADC4_HAVE_TIMER 1 -# define ADC4_TIMER_BASE STM32_TIM1_BASE -# define ADC4_TIMER_PCLK_FREQUENCY STM32_APB2_TIM1_CLKIN -#elif defined(CONFIG_STM32_TIM2_ADC4) -# define ADC4_HAVE_TIMER 1 -# define ADC4_TIMER_BASE STM32_TIM2_BASE -# define ADC4_TIMER_PCLK_FREQUENCY STM32_APB1_TIM2_CLKIN -#elif defined(CONFIG_STM32_TIM3_ADC4) -# define ADC4_HAVE_TIMER 1 -# define ADC4_TIMER_BASE STM32_TIM3_BASE -# define ADC4_TIMER_PCLK_FREQUENCY STM32_APB1_TIM3_CLKIN -#elif defined(CONFIG_STM32_TIM4_ADC4) -# define ADC4_HAVE_TIMER 1 -# define ADC4_TIMER_BASE STM32_TIM4_BASE -# define ADC4_TIMER_PCLK_FREQUENCY STM32_APB1_TIM4_CLKIN -#elif defined(CONFIG_STM32_TIM5_ADC4) -# define ADC4_HAVE_TIMER 1 -# define ADC4_TIMER_BASE STM32_TIM5_BASE -# define ADC4_TIMER_PCLK_FREQUENCY STM32_APB1_TIM5_CLKIN -#elif defined(CONFIG_STM32_TIM7_ADC4) -# define ADC4_HAVE_TIMER 1 -# define ADC4_TIMER_BASE STM32_TIM7_BASE -# define ADC4_TIMER_PCLK_FREQUENCY STM32_APB1_TIM7_CLKIN -#elif defined(CONFIG_STM32_TIM8_ADC4) -# define ADC4_HAVE_TIMER 1 -# define ADC4_TIMER_BASE STM32_TIM8_BASE -# define ADC4_TIMER_PCLK_FREQUENCY STM32_APB2_TIM8_CLKIN -#elif defined(CONFIG_STM32_TIM15_ADC4) -# define ADC4_HAVE_TIMER 1 -# define ADC4_TIMER_BASE STM32_TIM15_BASE -# define ADC4_TIMER_PCLK_FREQUENCY STM32_APB2_TIM15_CLKIN -#elif defined(CONFIG_STM32_TIM20_ADC4) -# define ADC4_HAVE_TIMER 1 -# define ADC4_TIMER_BASE STM32_TIM20_BASE -# define ADC4_TIMER_PCLK_FREQUENCY STM32_APB2_TIM20_CLKIN -#else -# undef ADC4_HAVE_TIMER -#endif - -#ifdef ADC4_HAVE_TIMER -# ifndef CONFIG_STM32_ADC4_SAMPLE_FREQUENCY -# error "CONFIG_STM32_ADC4_SAMPLE_FREQUENCY not defined" -# endif -# ifndef CONFIG_STM32_ADC4_TIMTRIG -# error "CONFIG_STM32_ADC4_TIMTRIG not defined" -# warning "Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO 5:TRGO2" -# endif -#endif - -#if defined(ADC1_HAVE_TIMER) || defined(ADC2_HAVE_TIMER) || \ - defined(ADC3_HAVE_TIMER) || defined(ADC4_HAVE_TIMER) -# define ADC_HAVE_TIMER 1 -# if defined(CONFIG_STM32_STM32F10XX) && !defined(CONFIG_STM32_FORCEPOWER) -# warning "CONFIG_STM32_FORCEPOWER must be defined to enable the timer(s)" -# endif -#else -# undef ADC_HAVE_TIMER -#endif - -#if defined(ADC1_HAVE_HRTIM) || defined(ADC2_HAVE_HRTIM) -# define ADC_HAVE_HRTIM -#else -# undef ADC_HAVE_HRTIM -#endif - -/* NOTE: - * The following assumes that all possible combinations of timers and - * values are support EXTSEL. That is not so and it varies from one STM32 - * to another. But this (wrong) assumptions keeps the logic as simple as - * possible. If unsupported combination is used, an error will show up - * later during compilation although it may be difficult to track it back - * to this simplification. - * - * STM32L15XX-family has only one ADC onboard, thus there is no definition - * for other 3 ADC's - */ - -#if defined(HAVE_IP_ADC_V2) -# define ADC1_EXTSEL_T1CC1 ADC12_CFGR1_EXTSEL_T1CC1 -# define ADC1_EXTSEL_T1CC2 ADC12_CFGR1_EXTSEL_T1CC2 -# define ADC1_EXTSEL_T1CC3 ADC12_CFGR1_EXTSEL_T1CC3 -# define ADC1_EXTSEL_T1CC4 ADC12_CFGR1_EXTSEL_T1CC4 -# define ADC1_EXTSEL_T1TRGO ADC12_CFGR1_EXTSEL_T1TRGO -# define ADC1_EXTSEL_T1TRGO2 ADC12_CFGR1_EXTSEL_T1TRGO2 -# define ADC2_EXTSEL_T1CC1 ADC12_CFGR1_EXTSEL_T1CC1 -# define ADC2_EXTSEL_T1CC2 ADC12_CFGR1_EXTSEL_T1CC2 -# define ADC2_EXTSEL_T1CC3 ADC12_CFGR1_EXTSEL_T1CC3 -# define ADC2_EXTSEL_T1CC4 ADC12_CFGR1_EXTSEL_T1CC4 -# define ADC2_EXTSEL_T1TRGO ADC12_CFGR1_EXTSEL_T1TRGO -# define ADC2_EXTSEL_T1TRGO2 ADC12_CFGR1_EXTSEL_T1TRGO2 -# define ADC3_EXTSEL_T1CC1 ADC34_CFGR1_EXTSEL_T1CC1 -# define ADC3_EXTSEL_T1CC2 ADC34_CFGR1_EXTSEL_T1CC2 -# define ADC3_EXTSEL_T1CC3 ADC34_CFGR1_EXTSEL_T1CC3 -# define ADC3_EXTSEL_T1CC4 ADC34_CFGR1_EXTSEL_T1CC4 -# define ADC3_EXTSEL_T1TRGO ADC34_CFGR1_EXTSEL_T1TRGO -# define ADC3_EXTSEL_T1TRGO2 ADC34_CFGR1_EXTSEL_T1TRGO2 -# define ADC4_EXTSEL_T1CC1 ADC34_CFGR1_EXTSEL_T1CC1 -# define ADC4_EXTSEL_T1CC2 ADC34_CFGR1_EXTSEL_T1CC2 -# define ADC4_EXTSEL_T1CC3 ADC34_CFGR1_EXTSEL_T1CC3 -# define ADC4_EXTSEL_T1CC4 ADC34_CFGR1_EXTSEL_T1CC4 -# define ADC4_EXTSEL_T1TRGO ADC34_CFGR1_EXTSEL_T1TRGO -# define ADC4_EXTSEL_T1TRGO2 ADC34_CFGR1_EXTSEL_T1TRGO2 -# define ADC1_EXTSEL_T2CC1 ADC12_CFGR1_EXTSEL_T2CC1 -# define ADC1_EXTSEL_T2CC2 ADC12_CFGR1_EXTSEL_T2CC2 -# define ADC1_EXTSEL_T2CC3 ADC12_CFGR1_EXTSEL_T2CC3 -# define ADC1_EXTSEL_T2CC4 ADC12_CFGR1_EXTSEL_T2CC4 -# define ADC1_EXTSEL_T2TRGO ADC12_CFGR1_EXTSEL_T2TRGO -# define ADC2_EXTSEL_T2CC1 ADC12_CFGR1_EXTSEL_T2CC1 -# define ADC2_EXTSEL_T2CC2 ADC12_CFGR1_EXTSEL_T2CC2 -# define ADC2_EXTSEL_T2CC3 ADC12_CFGR1_EXTSEL_T2CC3 -# define ADC2_EXTSEL_T2CC4 ADC12_CFGR1_EXTSEL_T2CC4 -# define ADC2_EXTSEL_T2TRGO ADC12_CFGR1_EXTSEL_T2TRGO -# define ADC3_EXTSEL_T2CC1 ADC34_CFGR1_EXTSEL_T2CC1 -# define ADC3_EXTSEL_T2CC2 ADC34_CFGR1_EXTSEL_T2CC2 -# define ADC3_EXTSEL_T2CC3 ADC34_CFGR1_EXTSEL_T2CC3 -# define ADC3_EXTSEL_T2CC4 ADC34_CFGR1_EXTSEL_T2CC4 -# define ADC3_EXTSEL_T2TRGO ADC34_CFGR1_EXTSEL_T2TRGO -# define ADC4_EXTSEL_T2CC1 ADC34_CFGR1_EXTSEL_T2CC1 -# define ADC4_EXTSEL_T2CC2 ADC34_CFGR1_EXTSEL_T2CC2 -# define ADC4_EXTSEL_T2CC3 ADC34_CFGR1_EXTSEL_T2CC3 -# define ADC4_EXTSEL_T2CC4 ADC34_CFGR1_EXTSEL_T2CC4 -# define ADC4_EXTSEL_T2TRGO ADC34_CFGR1_EXTSEL_T2TRGO -# define ADC1_EXTSEL_T3CC1 ADC12_CFGR1_EXTSEL_T3CC1 -# define ADC1_EXTSEL_T3CC2 ADC12_CFGR1_EXTSEL_T3CC2 -# define ADC1_EXTSEL_T3CC3 ADC12_CFGR1_EXTSEL_T3CC3 -# define ADC1_EXTSEL_T3CC4 ADC12_CFGR1_EXTSEL_T3CC4 -# define ADC1_EXTSEL_T3TRGO ADC12_CFGR1_EXTSEL_T3TRGO -# define ADC2_EXTSEL_T3CC1 ADC12_CFGR1_EXTSEL_T3CC1 -# define ADC2_EXTSEL_T3CC2 ADC12_CFGR1_EXTSEL_T3CC2 -# define ADC2_EXTSEL_T3CC3 ADC12_CFGR1_EXTSEL_T3CC3 -# define ADC2_EXTSEL_T3CC4 ADC12_CFGR1_EXTSEL_T3CC4 -# define ADC2_EXTSEL_T3TRGO ADC12_CFGR1_EXTSEL_T3TRGO -# define ADC3_EXTSEL_T3CC1 ADC34_CFGR1_EXTSEL_T3CC1 -# define ADC3_EXTSEL_T3CC2 ADC34_CFGR1_EXTSEL_T3CC2 -# define ADC3_EXTSEL_T3CC3 ADC34_CFGR1_EXTSEL_T3CC3 -# define ADC3_EXTSEL_T3CC4 ADC34_CFGR1_EXTSEL_T3CC4 -# define ADC3_EXTSEL_T3TRGO ADC34_CFGR1_EXTSEL_T3TRGO -# define ADC4_EXTSEL_T3CC1 ADC34_CFGR1_EXTSEL_T3CC1 -# define ADC4_EXTSEL_T3CC2 ADC34_CFGR1_EXTSEL_T3CC2 -# define ADC4_EXTSEL_T3CC3 ADC34_CFGR1_EXTSEL_T3CC3 -# define ADC4_EXTSEL_T3CC4 ADC34_CFGR1_EXTSEL_T3CC4 -# define ADC4_EXTSEL_T3TRGO ADC34_CFGR1_EXTSEL_T3TRGO -# define ADC1_EXTSEL_T4CC1 ADC12_CFGR1_EXTSEL_T4CC1 -# define ADC1_EXTSEL_T4CC2 ADC12_CFGR1_EXTSEL_T4CC2 -# define ADC1_EXTSEL_T4CC3 ADC12_CFGR1_EXTSEL_T4CC3 -# define ADC1_EXTSEL_T4CC4 ADC12_CFGR1_EXTSEL_T4CC4 -# define ADC1_EXTSEL_T4TRGO ADC12_CFGR1_EXTSEL_T4TRGO -# define ADC2_EXTSEL_T4CC1 ADC12_CFGR1_EXTSEL_T4CC1 -# define ADC2_EXTSEL_T4CC2 ADC12_CFGR1_EXTSEL_T4CC2 -# define ADC2_EXTSEL_T4CC3 ADC12_CFGR1_EXTSEL_T4CC3 -# define ADC2_EXTSEL_T4CC4 ADC12_CFGR1_EXTSEL_T4CC4 -# define ADC2_EXTSEL_T4TRGO ADC12_CFGR1_EXTSEL_T4TRGO -# define ADC3_EXTSEL_T4CC1 ADC34_CFGR1_EXTSEL_T4CC1 -# define ADC3_EXTSEL_T4CC2 ADC34_CFGR1_EXTSEL_T4CC2 -# define ADC3_EXTSEL_T4CC3 ADC34_CFGR1_EXTSEL_T4CC3 -# define ADC3_EXTSEL_T4CC4 ADC34_CFGR1_EXTSEL_T4CC4 -# define ADC3_EXTSEL_T4TRGO ADC34_CFGR1_EXTSEL_T4TRGO -# define ADC4_EXTSEL_T4CC1 ADC34_CFGR1_EXTSEL_T4CC1 -# define ADC4_EXTSEL_T4CC2 ADC34_CFGR1_EXTSEL_T4CC2 -# define ADC4_EXTSEL_T4CC3 ADC34_CFGR1_EXTSEL_T4CC3 -# define ADC4_EXTSEL_T4CC4 ADC34_CFGR1_EXTSEL_T4CC4 -# define ADC4_EXTSEL_T4TRGO ADC34_CFGR1_EXTSEL_T4TRGO -# define ADC1_EXTSEL_T5CC1 ADC12_CFGR1_EXTSEL_T5CC1 -# define ADC1_EXTSEL_T5CC2 ADC12_CFGR1_EXTSEL_T5CC2 -# define ADC1_EXTSEL_T5CC3 ADC12_CFGR1_EXTSEL_T5CC3 -# define ADC1_EXTSEL_T5CC4 ADC12_CFGR1_EXTSEL_T5CC4 -# define ADC1_EXTSEL_T5TRGO ADC12_CFGR1_EXTSEL_T5TRGO -# define ADC2_EXTSEL_T5CC1 ADC12_CFGR1_EXTSEL_T5CC1 -# define ADC2_EXTSEL_T5CC2 ADC12_CFGR1_EXTSEL_T5CC2 -# define ADC2_EXTSEL_T5CC3 ADC12_CFGR1_EXTSEL_T5CC3 -# define ADC2_EXTSEL_T5CC4 ADC12_CFGR1_EXTSEL_T5CC4 -# define ADC2_EXTSEL_T5TRGO ADC12_CFGR1_EXTSEL_T5TRGO -# define ADC3_EXTSEL_T5CC1 ADC34_CFGR1_EXTSEL_T5CC1 -# define ADC3_EXTSEL_T5CC2 ADC34_CFGR1_EXTSEL_T5CC2 -# define ADC3_EXTSEL_T5CC3 ADC34_CFGR1_EXTSEL_T5CC3 -# define ADC3_EXTSEL_T5CC4 ADC34_CFGR1_EXTSEL_T5CC4 -# define ADC3_EXTSEL_T5TRGO ADC34_CFGR1_EXTSEL_T5TRGO -# define ADC4_EXTSEL_T5CC1 ADC34_CFGR1_EXTSEL_T5CC1 -# define ADC4_EXTSEL_T5CC2 ADC34_CFGR1_EXTSEL_T5CC2 -# define ADC4_EXTSEL_T5CC3 ADC34_CFGR1_EXTSEL_T5CC3 -# define ADC4_EXTSEL_T5CC4 ADC34_CFGR1_EXTSEL_T5CC4 -# define ADC4_EXTSEL_T5TRGO ADC34_CFGR1_EXTSEL_T5TRGO -# define ADC1_EXTSEL_T6CC1 ADC12_CFGR1_EXTSEL_T6CC1 -# define ADC1_EXTSEL_T6CC2 ADC12_CFGR1_EXTSEL_T6CC2 -# define ADC1_EXTSEL_T6CC3 ADC12_CFGR1_EXTSEL_T6CC3 -# define ADC1_EXTSEL_T6CC4 ADC12_CFGR1_EXTSEL_T6CC4 -# define ADC1_EXTSEL_T6TRGO ADC12_CFGR1_EXTSEL_T6TRGO -# define ADC2_EXTSEL_T6CC1 ADC12_CFGR1_EXTSEL_T6CC1 -# define ADC2_EXTSEL_T6CC2 ADC12_CFGR1_EXTSEL_T6CC2 -# define ADC2_EXTSEL_T6CC3 ADC12_CFGR1_EXTSEL_T6CC3 -# define ADC2_EXTSEL_T6CC4 ADC12_CFGR1_EXTSEL_T6CC4 -# define ADC2_EXTSEL_T6TRGO ADC12_CFGR1_EXTSEL_T6TRGO -# define ADC3_EXTSEL_T6CC1 ADC34_CFGR1_EXTSEL_T6CC1 -# define ADC3_EXTSEL_T6CC2 ADC34_CFGR1_EXTSEL_T6CC2 -# define ADC3_EXTSEL_T6CC3 ADC34_CFGR1_EXTSEL_T6CC3 -# define ADC3_EXTSEL_T6CC4 ADC34_CFGR1_EXTSEL_T6CC4 -# define ADC3_EXTSEL_T6TRGO ADC34_CFGR1_EXTSEL_T6TRGO -# define ADC4_EXTSEL_T6CC1 ADC34_CFGR1_EXTSEL_T6CC1 -# define ADC4_EXTSEL_T6CC2 ADC34_CFGR1_EXTSEL_T6CC2 -# define ADC4_EXTSEL_T6CC3 ADC34_CFGR1_EXTSEL_T6CC3 -# define ADC4_EXTSEL_T6CC4 ADC34_CFGR1_EXTSEL_T6CC4 -# define ADC4_EXTSEL_T6TRGO ADC34_CFGR1_EXTSEL_T6TRGO -# define ADC1_EXTSEL_T7CC1 ADC12_CFGR1_EXTSEL_T7CC1 -# define ADC1_EXTSEL_T7CC2 ADC12_CFGR1_EXTSEL_T7CC2 -# define ADC1_EXTSEL_T7CC3 ADC12_CFGR1_EXTSEL_T7CC3 -# define ADC1_EXTSEL_T7CC4 ADC12_CFGR1_EXTSEL_T7CC4 -# define ADC1_EXTSEL_T7TRGO ADC12_CFGR1_EXTSEL_T7TRGO -# define ADC2_EXTSEL_T7CC1 ADC12_CFGR1_EXTSEL_T7CC1 -# define ADC2_EXTSEL_T7CC2 ADC12_CFGR1_EXTSEL_T7CC2 -# define ADC2_EXTSEL_T7CC3 ADC12_CFGR1_EXTSEL_T7CC3 -# define ADC2_EXTSEL_T7CC4 ADC12_CFGR1_EXTSEL_T7CC4 -# define ADC2_EXTSEL_T7TRGO ADC12_CFGR1_EXTSEL_T7TRGO -# define ADC3_EXTSEL_T7CC1 ADC34_CFGR1_EXTSEL_T7CC1 -# define ADC3_EXTSEL_T7CC2 ADC34_CFGR1_EXTSEL_T7CC2 -# define ADC3_EXTSEL_T7CC3 ADC34_CFGR1_EXTSEL_T7CC3 -# define ADC3_EXTSEL_T7CC4 ADC34_CFGR1_EXTSEL_T7CC4 -# define ADC3_EXTSEL_T7TRGO ADC34_CFGR1_EXTSEL_T7TRGO -# define ADC4_EXTSEL_T7CC1 ADC34_CFGR1_EXTSEL_T7CC1 -# define ADC4_EXTSEL_T7CC2 ADC34_CFGR1_EXTSEL_T7CC2 -# define ADC4_EXTSEL_T7CC3 ADC34_CFGR1_EXTSEL_T7CC3 -# define ADC4_EXTSEL_T7CC4 ADC34_CFGR1_EXTSEL_T7CC4 -# define ADC4_EXTSEL_T7TRGO ADC34_CFGR1_EXTSEL_T7TRGO -# define ADC1_EXTSEL_T8CC1 ADC12_CFGR1_EXTSEL_T8CC1 -# define ADC1_EXTSEL_T8CC2 ADC12_CFGR1_EXTSEL_T8CC2 -# define ADC1_EXTSEL_T8CC3 ADC12_CFGR1_EXTSEL_T8CC3 -# define ADC1_EXTSEL_T8CC4 ADC12_CFGR1_EXTSEL_T8CC4 -# define ADC1_EXTSEL_T8TRGO ADC12_CFGR1_EXTSEL_T8TRGO -# define ADC1_EXTSEL_T8TRGO2 ADC12_CFGR1_EXTSEL_T8TRGO2 -# define ADC2_EXTSEL_T8CC1 ADC12_CFGR1_EXTSEL_T8CC1 -# define ADC2_EXTSEL_T8CC2 ADC12_CFGR1_EXTSEL_T8CC2 -# define ADC2_EXTSEL_T8CC3 ADC12_CFGR1_EXTSEL_T8CC3 -# define ADC2_EXTSEL_T8CC4 ADC12_CFGR1_EXTSEL_T8CC4 -# define ADC2_EXTSEL_T8TRGO ADC12_CFGR1_EXTSEL_T8TRGO -# define ADC2_EXTSEL_T8TRGO2 ADC12_CFGR1_EXTSEL_T8TRGO2 -# define ADC3_EXTSEL_T8CC1 ADC34_CFGR1_EXTSEL_T8CC1 -# define ADC3_EXTSEL_T8CC2 ADC34_CFGR1_EXTSEL_T8CC2 -# define ADC3_EXTSEL_T8CC3 ADC34_CFGR1_EXTSEL_T8CC3 -# define ADC3_EXTSEL_T8CC4 ADC34_CFGR1_EXTSEL_T8CC4 -# define ADC3_EXTSEL_T8TRGO ADC34_CFGR1_EXTSEL_T8TRGO -# define ADC3_EXTSEL_T8TRGO2 ADC34_CFGR1_EXTSEL_T8TRGO2 -# define ADC4_EXTSEL_T8CC1 ADC34_CFGR1_EXTSEL_T8CC1 -# define ADC4_EXTSEL_T8CC2 ADC34_CFGR1_EXTSEL_T8CC2 -# define ADC4_EXTSEL_T8CC3 ADC34_CFGR1_EXTSEL_T8CC3 -# define ADC4_EXTSEL_T8CC4 ADC34_CFGR1_EXTSEL_T8CC4 -# define ADC4_EXTSEL_T8TRGO ADC34_CFGR1_EXTSEL_T8TRGO -# define ADC4_EXTSEL_T8TRGO2 ADC34_CFGR1_EXTSEL_T8TRGO2 -# define ADC1_EXTSEL_T9CC1 ADC12_CFGR1_EXTSEL_T9CC1 -# define ADC1_EXTSEL_T9CC2 ADC12_CFGR1_EXTSEL_T9CC2 -# define ADC1_EXTSEL_T9CC3 ADC12_CFGR1_EXTSEL_T9CC3 -# define ADC1_EXTSEL_T9CC4 ADC12_CFGR1_EXTSEL_T9CC4 -# define ADC1_EXTSEL_T9TRGO ADC12_CFGR1_EXTSEL_T9TRGO -# define ADC2_EXTSEL_T9CC1 ADC12_CFGR1_EXTSEL_T9CC1 -# define ADC2_EXTSEL_T9CC2 ADC12_CFGR1_EXTSEL_T9CC2 -# define ADC2_EXTSEL_T9CC3 ADC12_CFGR1_EXTSEL_T9CC3 -# define ADC2_EXTSEL_T9CC4 ADC12_CFGR1_EXTSEL_T9CC4 -# define ADC2_EXTSEL_T9TRGO ADC12_CFGR1_EXTSEL_T9TRGO -# define ADC3_EXTSEL_T9CC1 ADC34_CFGR1_EXTSEL_T9CC1 -# define ADC3_EXTSEL_T9CC2 ADC34_CFGR1_EXTSEL_T9CC2 -# define ADC3_EXTSEL_T9CC3 ADC34_CFGR1_EXTSEL_T9CC3 -# define ADC3_EXTSEL_T9CC4 ADC34_CFGR1_EXTSEL_T9CC4 -# define ADC3_EXTSEL_T9TRGO ADC34_CFGR1_EXTSEL_T9TRGO -# define ADC4_EXTSEL_T9CC1 ADC34_CFGR1_EXTSEL_T9CC1 -# define ADC4_EXTSEL_T9CC2 ADC34_CFGR1_EXTSEL_T9CC2 -# define ADC4_EXTSEL_T9CC3 ADC34_CFGR1_EXTSEL_T9CC3 -# define ADC4_EXTSEL_T9CC4 ADC34_CFGR1_EXTSEL_T9CC4 -# define ADC4_EXTSEL_T9TRGO ADC34_CFGR1_EXTSEL_T9TRGO -# define ADC1_EXTSEL_T10CC1 ADC12_CFGR1_EXTSEL_T10CC1 -# define ADC1_EXTSEL_T10CC2 ADC12_CFGR1_EXTSEL_T10CC2 -# define ADC1_EXTSEL_T10CC3 ADC12_CFGR1_EXTSEL_T10CC3 -# define ADC1_EXTSEL_T10CC4 ADC12_CFGR1_EXTSEL_T10CC4 -# define ADC1_EXTSEL_T10TRGO ADC12_CFGR1_EXTSEL_T10TRGO -# define ADC2_EXTSEL_T10CC1 ADC12_CFGR1_EXTSEL_T10CC1 -# define ADC2_EXTSEL_T10CC2 ADC12_CFGR1_EXTSEL_T10CC2 -# define ADC2_EXTSEL_T10CC3 ADC12_CFGR1_EXTSEL_T10CC3 -# define ADC2_EXTSEL_T10CC4 ADC12_CFGR1_EXTSEL_T10CC4 -# define ADC2_EXTSEL_T10TRGO ADC12_CFGR1_EXTSEL_T10TRGO -# define ADC3_EXTSEL_T10CC1 ADC34_CFGR1_EXTSEL_T10CC1 -# define ADC3_EXTSEL_T10CC2 ADC34_CFGR1_EXTSEL_T10CC2 -# define ADC3_EXTSEL_T10CC3 ADC34_CFGR1_EXTSEL_T10CC3 -# define ADC3_EXTSEL_T10CC4 ADC34_CFGR1_EXTSEL_T10CC4 -# define ADC3_EXTSEL_T10TRGO ADC34_CFGR1_EXTSEL_T10TRGO -# define ADC4_EXTSEL_T10CC1 ADC34_CFGR1_EXTSEL_T10CC1 -# define ADC4_EXTSEL_T10CC2 ADC34_CFGR1_EXTSEL_T10CC2 -# define ADC4_EXTSEL_T10CC3 ADC34_CFGR1_EXTSEL_T10CC3 -# define ADC4_EXTSEL_T10CC4 ADC34_CFGR1_EXTSEL_T10CC4 -# define ADC4_EXTSEL_T10TRGO ADC34_CFGR1_EXTSEL_T10TRGO -# define ADC1_EXTSEL_T15CC1 ADC12_CFGR1_EXTSEL_T15CC1 -# define ADC1_EXTSEL_T15CC2 ADC12_CFGR1_EXTSEL_T15CC2 -# define ADC1_EXTSEL_T15CC3 ADC12_CFGR1_EXTSEL_T15CC3 -# define ADC1_EXTSEL_T15CC4 ADC12_CFGR1_EXTSEL_T15CC4 -# define ADC1_EXTSEL_T15TRGO ADC12_CFGR1_EXTSEL_T15TRGO -# define ADC2_EXTSEL_T15CC1 ADC12_CFGR1_EXTSEL_T15CC1 -# define ADC2_EXTSEL_T15CC2 ADC12_CFGR1_EXTSEL_T15CC2 -# define ADC2_EXTSEL_T15CC3 ADC12_CFGR1_EXTSEL_T15CC3 -# define ADC2_EXTSEL_T15CC4 ADC12_CFGR1_EXTSEL_T15CC4 -# define ADC2_EXTSEL_T15TRGO ADC12_CFGR1_EXTSEL_T15TRGO -# define ADC3_EXTSEL_T15CC1 ADC34_CFGR1_EXTSEL_T15CC1 -# define ADC3_EXTSEL_T15CC2 ADC34_CFGR1_EXTSEL_T15CC2 -# define ADC3_EXTSEL_T15CC3 ADC34_CFGR1_EXTSEL_T15CC3 -# define ADC3_EXTSEL_T15CC4 ADC34_CFGR1_EXTSEL_T15CC4 -# define ADC3_EXTSEL_T15TRGO ADC34_CFGR1_EXTSEL_T15TRGO -# define ADC4_EXTSEL_T15CC1 ADC34_CFGR1_EXTSEL_T15CC1 -# define ADC4_EXTSEL_T15CC2 ADC34_CFGR1_EXTSEL_T15CC2 -# define ADC4_EXTSEL_T15CC3 ADC34_CFGR1_EXTSEL_T15CC3 -# define ADC4_EXTSEL_T15CC4 ADC34_CFGR1_EXTSEL_T15CC4 -# define ADC4_EXTSEL_T15TRGO ADC34_CFGR1_EXTSEL_T15TRGO -# define ADC1_EXTSEL_T20CC1 ADC12_CFGR1_EXTSEL_T20CC1 -# define ADC1_EXTSEL_T20CC2 ADC12_CFGR1_EXTSEL_T20CC2 -# define ADC1_EXTSEL_T20CC3 ADC12_CFGR1_EXTSEL_T20CC3 -# define ADC1_EXTSEL_T20CC4 ADC12_CFGR1_EXTSEL_T20CC4 -# define ADC1_EXTSEL_T20TRGO ADC12_CFGR1_EXTSEL_T20TRGO -# define ADC2_EXTSEL_T20CC1 ADC12_CFGR1_EXTSEL_T20CC1 -# define ADC2_EXTSEL_T20CC2 ADC12_CFGR1_EXTSEL_T20CC2 -# define ADC2_EXTSEL_T20CC3 ADC12_CFGR1_EXTSEL_T20CC3 -# define ADC2_EXTSEL_T20CC4 ADC12_CFGR1_EXTSEL_T20CC4 -# define ADC2_EXTSEL_T20TRGO ADC12_CFGR1_EXTSEL_T20TRGO -# define ADC3_EXTSEL_T20CC1 ADC34_CFGR1_EXTSEL_T20CC1 -# define ADC3_EXTSEL_T20CC2 ADC34_CFGR1_EXTSEL_T20CC2 -# define ADC3_EXTSEL_T20CC3 ADC34_CFGR1_EXTSEL_T20CC3 -# define ADC3_EXTSEL_T20CC4 ADC34_CFGR1_EXTSEL_T20CC4 -# define ADC3_EXTSEL_T20TRGO ADC34_CFGR1_EXTSEL_T20TRGO -# define ADC4_EXTSEL_T20CC1 ADC34_CFGR1_EXTSEL_T20CC1 -# define ADC4_EXTSEL_T20CC2 ADC34_CFGR1_EXTSEL_T20CC2 -# define ADC4_EXTSEL_T20CC3 ADC34_CFGR1_EXTSEL_T20CC3 -# define ADC4_EXTSEL_T20CC4 ADC34_CFGR1_EXTSEL_T20CC4 -# define ADC4_EXTSEL_T20TRGO ADC34_CFGR1_EXTSEL_T20TRGO -# define ADC1_EXTSEL_HRTTRG1 ADC12_CFGR1_EXTSEL_HRT1TRG1 -# define ADC1_EXTSEL_HRTTRG3 ADC12_CFGR1_EXTSEL_HRT1TRG3 -# define ADC2_EXTSEL_HRTTRG1 ADC12_CFGR1_EXTSEL_HRT1TRG1 -# define ADC2_EXTSEL_HRTTRG3 ADC12_CFGR1_EXTSEL_HRT1TRG3 -#else -# define ADC1_EXTSEL_T1CC1 ADC_CR2_EXTSEL_T1CC1 -# define ADC1_EXTSEL_T1CC2 ADC_CR2_EXTSEL_T1CC2 -# define ADC1_EXTSEL_T1CC3 ADC_CR2_EXTSEL_T1CC3 -# define ADC1_EXTSEL_T1CC4 ADC_CR2_EXTSEL_T1CC4 -# define ADC1_EXTSEL_T1TRGO ADC_CR2_EXTSEL_T1TRGO -# define ADC2_EXTSEL_T1CC1 ADC_CR2_EXTSEL_T1CC1 -# define ADC2_EXTSEL_T1CC2 ADC_CR2_EXTSEL_T1CC2 -# define ADC2_EXTSEL_T1CC3 ADC_CR2_EXTSEL_T1CC3 -# define ADC2_EXTSEL_T1CC4 ADC_CR2_EXTSEL_T1CC4 -# define ADC2_EXTSEL_T1TRGO ADC_CR2_EXTSEL_T1TRGO -# define ADC3_EXTSEL_T1CC1 ADC_CR2_EXTSEL_T1CC1 -# define ADC3_EXTSEL_T1CC2 ADC_CR2_EXTSEL_T1CC2 -# define ADC3_EXTSEL_T1CC3 ADC_CR2_EXTSEL_T1CC3 -# define ADC3_EXTSEL_T1CC4 ADC_CR2_EXTSEL_T1CC4 -# define ADC3_EXTSEL_T1TRGO ADC_CR2_EXTSEL_T1TRGO -# define ADC4_EXTSEL_T1CC1 ADC_CR2_EXTSEL_T1CC1 -# define ADC4_EXTSEL_T1CC2 ADC_CR2_EXTSEL_T1CC2 -# define ADC4_EXTSEL_T1CC3 ADC_CR2_EXTSEL_T1CC3 -# define ADC4_EXTSEL_T1CC4 ADC_CR2_EXTSEL_T1CC4 -# define ADC4_EXTSEL_T1TRGO ADC_CR2_EXTSEL_T1TRGO -# define ADC1_EXTSEL_T2CC1 ADC_CR2_EXTSEL_T2CC1 -# define ADC1_EXTSEL_T2CC2 ADC_CR2_EXTSEL_T2CC2 -# define ADC1_EXTSEL_T2CC3 ADC_CR2_EXTSEL_T2CC3 -# define ADC1_EXTSEL_T2CC4 ADC_CR2_EXTSEL_T2CC4 -# define ADC1_EXTSEL_T2TRGO ADC_CR2_EXTSEL_T2TRGO -# define ADC2_EXTSEL_T2CC1 ADC_CR2_EXTSEL_T2CC1 -# define ADC2_EXTSEL_T2CC2 ADC_CR2_EXTSEL_T2CC2 -# define ADC2_EXTSEL_T2CC3 ADC_CR2_EXTSEL_T2CC3 -# define ADC2_EXTSEL_T2CC4 ADC_CR2_EXTSEL_T2CC4 -# define ADC2_EXTSEL_T2TRGO ADC_CR2_EXTSEL_T2TRGO -# define ADC3_EXTSEL_T2CC1 ADC_CR2_EXTSEL_T2CC1 -# define ADC3_EXTSEL_T2CC2 ADC_CR2_EXTSEL_T2CC2 -# define ADC3_EXTSEL_T2CC3 ADC_CR2_EXTSEL_T2CC3 -# define ADC3_EXTSEL_T2CC4 ADC_CR2_EXTSEL_T2CC4 -# define ADC3_EXTSEL_T2TRGO ADC_CR2_EXTSEL_T2TRGO -# define ADC4_EXTSEL_T2CC1 ADC_CR2_EXTSEL_T2CC1 -# define ADC4_EXTSEL_T2CC2 ADC_CR2_EXTSEL_T2CC2 -# define ADC4_EXTSEL_T2CC3 ADC_CR2_EXTSEL_T2CC3 -# define ADC4_EXTSEL_T2CC4 ADC_CR2_EXTSEL_T2CC4 -# define ADC4_EXTSEL_T2TRGO ADC_CR2_EXTSEL_T2TRGO -# define ADC1_EXTSEL_T3CC1 ADC_CR2_EXTSEL_T3CC1 -# define ADC1_EXTSEL_T3CC2 ADC_CR2_EXTSEL_T3CC2 -# define ADC1_EXTSEL_T3CC3 ADC_CR2_EXTSEL_T3CC3 -# define ADC1_EXTSEL_T3CC4 ADC_CR2_EXTSEL_T3CC4 -# define ADC1_EXTSEL_T3TRGO ADC_CR2_EXTSEL_T3TRGO -# define ADC2_EXTSEL_T3CC1 ADC_CR2_EXTSEL_T3CC1 -# define ADC2_EXTSEL_T3CC2 ADC_CR2_EXTSEL_T3CC2 -# define ADC2_EXTSEL_T3CC3 ADC_CR2_EXTSEL_T3CC3 -# define ADC2_EXTSEL_T3CC4 ADC_CR2_EXTSEL_T3CC4 -# define ADC2_EXTSEL_T3TRGO ADC_CR2_EXTSEL_T3TRGO -# define ADC3_EXTSEL_T3CC1 ADC_CR2_EXTSEL_T3CC1 -# define ADC3_EXTSEL_T3CC2 ADC_CR2_EXTSEL_T3CC2 -# define ADC3_EXTSEL_T3CC3 ADC_CR2_EXTSEL_T3CC3 -# define ADC3_EXTSEL_T3CC4 ADC_CR2_EXTSEL_T3CC4 -# define ADC3_EXTSEL_T3TRGO ADC_CR2_EXTSEL_T3TRGO -# define ADC4_EXTSEL_T3CC1 ADC_CR2_EXTSEL_T3CC1 -# define ADC4_EXTSEL_T3CC2 ADC_CR2_EXTSEL_T3CC2 -# define ADC4_EXTSEL_T3CC3 ADC_CR2_EXTSEL_T3CC3 -# define ADC4_EXTSEL_T3CC4 ADC_CR2_EXTSEL_T3CC4 -# define ADC4_EXTSEL_T3TRGO ADC_CR2_EXTSEL_T3TRGO -# define ADC1_EXTSEL_T4CC1 ADC_CR2_EXTSEL_T4CC1 -# define ADC1_EXTSEL_T4CC2 ADC_CR2_EXTSEL_T4CC2 -# define ADC1_EXTSEL_T4CC3 ADC_CR2_EXTSEL_T4CC3 -# define ADC1_EXTSEL_T4CC4 ADC_CR2_EXTSEL_T4CC4 -# define ADC1_EXTSEL_T4TRGO ADC_CR2_EXTSEL_T4TRGO -# define ADC2_EXTSEL_T4CC1 ADC_CR2_EXTSEL_T4CC1 -# define ADC2_EXTSEL_T4CC2 ADC_CR2_EXTSEL_T4CC2 -# define ADC2_EXTSEL_T4CC3 ADC_CR2_EXTSEL_T4CC3 -# define ADC2_EXTSEL_T4CC4 ADC_CR2_EXTSEL_T4CC4 -# define ADC2_EXTSEL_T4TRGO ADC_CR2_EXTSEL_T4TRGO -# define ADC3_EXTSEL_T4CC1 ADC_CR2_EXTSEL_T4CC1 -# define ADC3_EXTSEL_T4CC2 ADC_CR2_EXTSEL_T4CC2 -# define ADC3_EXTSEL_T4CC3 ADC_CR2_EXTSEL_T4CC3 -# define ADC3_EXTSEL_T4CC4 ADC_CR2_EXTSEL_T4CC4 -# define ADC3_EXTSEL_T4TRGO ADC_CR2_EXTSEL_T4TRGO -# define ADC4_EXTSEL_T4CC1 ADC_CR2_EXTSEL_T4CC1 -# define ADC4_EXTSEL_T4CC2 ADC_CR2_EXTSEL_T4CC2 -# define ADC4_EXTSEL_T4CC3 ADC_CR2_EXTSEL_T4CC3 -# define ADC4_EXTSEL_T4CC4 ADC_CR2_EXTSEL_T4CC4 -# define ADC4_EXTSEL_T4TRGO ADC_CR2_EXTSEL_T4TRGO -# define ADC1_EXTSEL_T5CC1 ADC_CR2_EXTSEL_T5CC1 -# define ADC1_EXTSEL_T5CC2 ADC_CR2_EXTSEL_T5CC2 -# define ADC1_EXTSEL_T5CC3 ADC_CR2_EXTSEL_T5CC3 -# define ADC1_EXTSEL_T5CC4 ADC_CR2_EXTSEL_T5CC4 -# define ADC1_EXTSEL_T5TRGO ADC_CR2_EXTSEL_T5TRGO -# define ADC2_EXTSEL_T5CC1 ADC_CR2_EXTSEL_T5CC1 -# define ADC2_EXTSEL_T5CC2 ADC_CR2_EXTSEL_T5CC2 -# define ADC2_EXTSEL_T5CC3 ADC_CR2_EXTSEL_T5CC3 -# define ADC2_EXTSEL_T5CC4 ADC_CR2_EXTSEL_T5CC4 -# define ADC2_EXTSEL_T5TRGO ADC_CR2_EXTSEL_T5TRGO -# define ADC3_EXTSEL_T5CC1 ADC_CR2_EXTSEL_T5CC1 -# define ADC3_EXTSEL_T5CC2 ADC_CR2_EXTSEL_T5CC2 -# define ADC3_EXTSEL_T5CC3 ADC_CR2_EXTSEL_T5CC3 -# define ADC3_EXTSEL_T5CC4 ADC_CR2_EXTSEL_T5CC4 -# define ADC3_EXTSEL_T5TRGO ADC_CR2_EXTSEL_T5TRGO -# define ADC4_EXTSEL_T5CC1 ADC_CR2_EXTSEL_T5CC1 -# define ADC4_EXTSEL_T5CC2 ADC_CR2_EXTSEL_T5CC2 -# define ADC4_EXTSEL_T5CC3 ADC_CR2_EXTSEL_T5CC3 -# define ADC4_EXTSEL_T5CC4 ADC_CR2_EXTSEL_T5CC4 -# define ADC4_EXTSEL_T5TRGO ADC_CR2_EXTSEL_T5TRGO -# define ADC1_EXTSEL_T6CC1 ADC_CR2_EXTSEL_T6CC1 -# define ADC1_EXTSEL_T6CC2 ADC_CR2_EXTSEL_T6CC2 -# define ADC1_EXTSEL_T6CC3 ADC_CR2_EXTSEL_T6CC3 -# define ADC1_EXTSEL_T6CC4 ADC_CR2_EXTSEL_T6CC4 -# define ADC1_EXTSEL_T6TRGO ADC_CR2_EXTSEL_T6TRGO -# define ADC2_EXTSEL_T6CC1 ADC_CR2_EXTSEL_T6CC1 -# define ADC2_EXTSEL_T6CC2 ADC_CR2_EXTSEL_T6CC2 -# define ADC2_EXTSEL_T6CC3 ADC_CR2_EXTSEL_T6CC3 -# define ADC2_EXTSEL_T6CC4 ADC_CR2_EXTSEL_T6CC4 -# define ADC2_EXTSEL_T6TRGO ADC_CR2_EXTSEL_T6TRGO -# define ADC3_EXTSEL_T6CC1 ADC_CR2_EXTSEL_T6CC1 -# define ADC3_EXTSEL_T6CC2 ADC_CR2_EXTSEL_T6CC2 -# define ADC3_EXTSEL_T6CC3 ADC_CR2_EXTSEL_T6CC3 -# define ADC3_EXTSEL_T6CC4 ADC_CR2_EXTSEL_T6CC4 -# define ADC3_EXTSEL_T6TRGO ADC_CR2_EXTSEL_T6TRGO -# define ADC4_EXTSEL_T6CC1 ADC_CR2_EXTSEL_T6CC1 -# define ADC4_EXTSEL_T6CC2 ADC_CR2_EXTSEL_T6CC2 -# define ADC4_EXTSEL_T6CC3 ADC_CR2_EXTSEL_T6CC3 -# define ADC4_EXTSEL_T6CC4 ADC_CR2_EXTSEL_T6CC4 -# define ADC4_EXTSEL_T6TRGO ADC_CR2_EXTSEL_T6TRGO -# define ADC1_EXTSEL_T7CC1 ADC_CR2_EXTSEL_T7CC1 -# define ADC1_EXTSEL_T7CC2 ADC_CR2_EXTSEL_T7CC2 -# define ADC1_EXTSEL_T7CC3 ADC_CR2_EXTSEL_T7CC3 -# define ADC1_EXTSEL_T7CC4 ADC_CR2_EXTSEL_T7CC4 -# define ADC1_EXTSEL_T7TRGO ADC_CR2_EXTSEL_T7TRGO -# define ADC2_EXTSEL_T7CC1 ADC_CR2_EXTSEL_T7CC1 -# define ADC2_EXTSEL_T7CC2 ADC_CR2_EXTSEL_T7CC2 -# define ADC2_EXTSEL_T7CC3 ADC_CR2_EXTSEL_T7CC3 -# define ADC2_EXTSEL_T7CC4 ADC_CR2_EXTSEL_T7CC4 -# define ADC2_EXTSEL_T7TRGO ADC_CR2_EXTSEL_T7TRGO -# define ADC3_EXTSEL_T7CC1 ADC_CR2_EXTSEL_T7CC1 -# define ADC3_EXTSEL_T7CC2 ADC_CR2_EXTSEL_T7CC2 -# define ADC3_EXTSEL_T7CC3 ADC_CR2_EXTSEL_T7CC3 -# define ADC3_EXTSEL_T7CC4 ADC_CR2_EXTSEL_T7CC4 -# define ADC3_EXTSEL_T7TRGO ADC_CR2_EXTSEL_T7TRGO -# define ADC4_EXTSEL_T7CC1 ADC_CR2_EXTSEL_T7CC1 -# define ADC4_EXTSEL_T7CC2 ADC_CR2_EXTSEL_T7CC2 -# define ADC4_EXTSEL_T7CC3 ADC_CR2_EXTSEL_T7CC3 -# define ADC4_EXTSEL_T7CC4 ADC_CR2_EXTSEL_T7CC4 -# define ADC4_EXTSEL_T7TRGO ADC_CR2_EXTSEL_T7TRGO -# define ADC1_EXTSEL_T8CC1 ADC_CR2_EXTSEL_T8CC1 -# define ADC1_EXTSEL_T8CC2 ADC_CR2_EXTSEL_T8CC2 -# define ADC1_EXTSEL_T8CC3 ADC_CR2_EXTSEL_T8CC3 -# define ADC1_EXTSEL_T8CC4 ADC_CR2_EXTSEL_T8CC4 -# define ADC1_EXTSEL_T8TRGO ADC_CR2_EXTSEL_T8TRGO -# define ADC2_EXTSEL_T8CC1 ADC_CR2_EXTSEL_T8CC1 -# define ADC2_EXTSEL_T8CC2 ADC_CR2_EXTSEL_T8CC2 -# define ADC2_EXTSEL_T8CC3 ADC_CR2_EXTSEL_T8CC3 -# define ADC2_EXTSEL_T8CC4 ADC_CR2_EXTSEL_T8CC4 -# define ADC2_EXTSEL_T8TRGO ADC_CR2_EXTSEL_T8TRGO -# define ADC3_EXTSEL_T8CC1 ADC_CR2_EXTSEL_T8CC1 -# define ADC3_EXTSEL_T8CC2 ADC_CR2_EXTSEL_T8CC2 -# define ADC3_EXTSEL_T8CC3 ADC_CR2_EXTSEL_T8CC3 -# define ADC3_EXTSEL_T8CC4 ADC_CR2_EXTSEL_T8CC4 -# define ADC3_EXTSEL_T8TRGO ADC_CR2_EXTSEL_T8TRGO -# define ADC4_EXTSEL_T8CC1 ADC_CR2_EXTSEL_T8CC1 -# define ADC4_EXTSEL_T8CC2 ADC_CR2_EXTSEL_T8CC2 -# define ADC4_EXTSEL_T8CC3 ADC_CR2_EXTSEL_T8CC3 -# define ADC4_EXTSEL_T8CC4 ADC_CR2_EXTSEL_T8CC4 -# define ADC4_EXTSEL_T8TRGO ADC_CR2_EXTSEL_T8TRGO -# define ADC1_EXTSEL_T9CC1 ADC_CR2_EXTSEL_T9CC1 -# define ADC1_EXTSEL_T9CC2 ADC_CR2_EXTSEL_T9CC2 -# define ADC1_EXTSEL_T9CC3 ADC_CR2_EXTSEL_T9CC3 -# define ADC1_EXTSEL_T9CC4 ADC_CR2_EXTSEL_T9CC4 -# define ADC1_EXTSEL_T9TRGO ADC_CR2_EXTSEL_T9TRGO -# define ADC2_EXTSEL_T9CC1 ADC_CR2_EXTSEL_T9CC1 -# define ADC2_EXTSEL_T9CC2 ADC_CR2_EXTSEL_T9CC2 -# define ADC2_EXTSEL_T9CC3 ADC_CR2_EXTSEL_T9CC3 -# define ADC2_EXTSEL_T9CC4 ADC_CR2_EXTSEL_T9CC4 -# define ADC2_EXTSEL_T9TRGO ADC_CR2_EXTSEL_T9TRGO -# define ADC3_EXTSEL_T9CC1 ADC_CR2_EXTSEL_T9CC1 -# define ADC3_EXTSEL_T9CC2 ADC_CR2_EXTSEL_T9CC2 -# define ADC3_EXTSEL_T9CC3 ADC_CR2_EXTSEL_T9CC3 -# define ADC3_EXTSEL_T9CC4 ADC_CR2_EXTSEL_T9CC4 -# define ADC3_EXTSEL_T9TRGO ADC_CR2_EXTSEL_T9TRGO -# define ADC4_EXTSEL_T9CC1 ADC_CR2_EXTSEL_T9CC1 -# define ADC4_EXTSEL_T9CC2 ADC_CR2_EXTSEL_T9CC2 -# define ADC4_EXTSEL_T9CC3 ADC_CR2_EXTSEL_T9CC3 -# define ADC4_EXTSEL_T9CC4 ADC_CR2_EXTSEL_T9CC4 -# define ADC4_EXTSEL_T9TRGO ADC_CR2_EXTSEL_T9TRGO -# define ADC1_EXTSEL_T10CC1 ADC_CR2_EXTSEL_T10CC1 -# define ADC1_EXTSEL_T10CC2 ADC_CR2_EXTSEL_T10CC2 -# define ADC1_EXTSEL_T10CC3 ADC_CR2_EXTSEL_T10CC3 -# define ADC1_EXTSEL_T10CC4 ADC_CR2_EXTSEL_T10CC4 -# define ADC1_EXTSEL_T10TRGO ADC_CR2_EXTSEL_T10TRGO -# define ADC2_EXTSEL_T10CC1 ADC_CR2_EXTSEL_T10CC1 -# define ADC2_EXTSEL_T10CC2 ADC_CR2_EXTSEL_T10CC2 -# define ADC2_EXTSEL_T10CC3 ADC_CR2_EXTSEL_T10CC3 -# define ADC2_EXTSEL_T10CC4 ADC_CR2_EXTSEL_T10CC4 -# define ADC2_EXTSEL_T10TRGO ADC_CR2_EXTSEL_T10TRGO -# define ADC3_EXTSEL_T10CC1 ADC_CR2_EXTSEL_T10CC1 -# define ADC3_EXTSEL_T10CC2 ADC_CR2_EXTSEL_T10CC2 -# define ADC3_EXTSEL_T10CC3 ADC_CR2_EXTSEL_T10CC3 -# define ADC3_EXTSEL_T10CC4 ADC_CR2_EXTSEL_T10CC4 -# define ADC3_EXTSEL_T10TRGO ADC_CR2_EXTSEL_T10TRGO -# define ADC4_EXTSEL_T10CC1 ADC_CR2_EXTSEL_T10CC1 -# define ADC4_EXTSEL_T10CC2 ADC_CR2_EXTSEL_T10CC2 -# define ADC4_EXTSEL_T10CC3 ADC_CR2_EXTSEL_T10CC3 -# define ADC4_EXTSEL_T10CC4 ADC_CR2_EXTSEL_T10CC4 -# define ADC4_EXTSEL_T10TRGO ADC_CR2_EXTSEL_T10TRGO -# define ADC1_EXTSEL_T15CC1 ADC_CR2_EXTSEL_T15CC1 -# define ADC1_EXTSEL_T15CC2 ADC_CR2_EXTSEL_T15CC2 -# define ADC1_EXTSEL_T15CC3 ADC_CR2_EXTSEL_T15CC3 -# define ADC1_EXTSEL_T15CC4 ADC_CR2_EXTSEL_T15CC4 -# define ADC1_EXTSEL_T15TRGO ADC_CR2_EXTSEL_T15TRGO -# define ADC2_EXTSEL_T15CC1 ADC_CR2_EXTSEL_T15CC1 -# define ADC2_EXTSEL_T15CC2 ADC_CR2_EXTSEL_T15CC2 -# define ADC2_EXTSEL_T15CC3 ADC_CR2_EXTSEL_T15CC3 -# define ADC2_EXTSEL_T15CC4 ADC_CR2_EXTSEL_T15CC4 -# define ADC2_EXTSEL_T15TRGO ADC_CR2_EXTSEL_T15TRGO -# define ADC3_EXTSEL_T15CC1 ADC_CR2_EXTSEL_T15CC1 -# define ADC3_EXTSEL_T15CC2 ADC_CR2_EXTSEL_T15CC2 -# define ADC3_EXTSEL_T15CC3 ADC_CR2_EXTSEL_T15CC3 -# define ADC3_EXTSEL_T15CC4 ADC_CR2_EXTSEL_T15CC4 -# define ADC3_EXTSEL_T15TRGO ADC_CR2_EXTSEL_T15TRGO -# define ADC4_EXTSEL_T15CC1 ADC_CR2_EXTSEL_T15CC1 -# define ADC4_EXTSEL_T15CC2 ADC_CR2_EXTSEL_T15CC2 -# define ADC4_EXTSEL_T15CC3 ADC_CR2_EXTSEL_T15CC3 -# define ADC4_EXTSEL_T15CC4 ADC_CR2_EXTSEL_T15CC4 -# define ADC4_EXTSEL_T15TRGO ADC_CR2_EXTSEL_T15TRGO -# define ADC1_EXTSEL_T20CC1 ADC_CR2_EXTSEL_T20CC1 -# define ADC1_EXTSEL_T20CC2 ADC_CR2_EXTSEL_T20CC2 -# define ADC1_EXTSEL_T20CC3 ADC_CR2_EXTSEL_T20CC3 -# define ADC1_EXTSEL_T20CC4 ADC_CR2_EXTSEL_T20CC4 -# define ADC1_EXTSEL_T20TRGO ADC_CR2_EXTSEL_T20TRGO -# define ADC2_EXTSEL_T20CC1 ADC_CR2_EXTSEL_T20CC1 -# define ADC2_EXTSEL_T20CC2 ADC_CR2_EXTSEL_T20CC2 -# define ADC2_EXTSEL_T20CC3 ADC_CR2_EXTSEL_T20CC3 -# define ADC2_EXTSEL_T20CC4 ADC_CR2_EXTSEL_T20CC4 -# define ADC2_EXTSEL_T20TRGO ADC_CR2_EXTSEL_T20TRGO -# define ADC3_EXTSEL_T20CC1 ADC_CR2_EXTSEL_T20CC1 -# define ADC3_EXTSEL_T20CC2 ADC_CR2_EXTSEL_T20CC2 -# define ADC3_EXTSEL_T20CC3 ADC_CR2_EXTSEL_T20CC3 -# define ADC3_EXTSEL_T20CC4 ADC_CR2_EXTSEL_T20CC4 -# define ADC3_EXTSEL_T20TRGO ADC_CR2_EXTSEL_T20TRGO -# define ADC4_EXTSEL_T20CC1 ADC_CR2_EXTSEL_T20CC1 -# define ADC4_EXTSEL_T20CC2 ADC_CR2_EXTSEL_T20CC2 -# define ADC4_EXTSEL_T20CC3 ADC_CR2_EXTSEL_T20CC3 -# define ADC4_EXTSEL_T20CC4 ADC_CR2_EXTSEL_T20CC4 -# define ADC4_EXTSEL_T20TRGO ADC_CR2_EXTSEL_T20TRGO -#endif - -/* JEXTSEL definitions. - * NOTE: Assumptions like for EXTSEL definitions (look above) - */ - -#if defined(HAVE_IP_ADC_V2) -# define ADC1_JEXTSEL_T1CC1 ADC12_JSQR_JEXTSEL_T1CC1 -# define ADC1_JEXTSEL_T1CC2 ADC12_JSQR_JEXTSEL_T1CC2 -# define ADC1_JEXTSEL_T1CC3 ADC12_JSQR_JEXTSEL_T1CC3 -# define ADC1_JEXTSEL_T1CC4 ADC12_JSQR_JEXTSEL_T1CC4 -# define ADC1_JEXTSEL_T1TRGO ADC12_JSQR_JEXTSEL_T1TRGO -# define ADC2_JEXTSEL_T1CC1 ADC12_JSQR_JEXTSEL_T1CC1 -# define ADC2_JEXTSEL_T1CC2 ADC12_JSQR_JEXTSEL_T1CC2 -# define ADC2_JEXTSEL_T1CC3 ADC12_JSQR_JEXTSEL_T1CC3 -# define ADC2_JEXTSEL_T1CC4 ADC12_JSQR_JEXTSEL_T1CC4 -# define ADC2_JEXTSEL_T1TRGO ADC12_JSQR_JEXTSEL_T1TRGO -# define ADC3_JEXTSEL_T1CC1 ADC34_JSQR_JEXTSEL_T1CC1 -# define ADC3_JEXTSEL_T1CC2 ADC34_JSQR_JEXTSEL_T1CC2 -# define ADC3_JEXTSEL_T1CC3 ADC34_JSQR_JEXTSEL_T1CC3 -# define ADC3_JEXTSEL_T1CC4 ADC34_JSQR_JEXTSEL_T1CC4 -# define ADC3_JEXTSEL_T1TRGO ADC34_JSQR_JEXTSEL_T1TRGO -# define ADC4_JEXTSEL_T1CC1 ADC34_JSQR_JEXTSEL_T1CC1 -# define ADC4_JEXTSEL_T1CC2 ADC34_JSQR_JEXTSEL_T1CC2 -# define ADC4_JEXTSEL_T1CC3 ADC34_JSQR_JEXTSEL_T1CC3 -# define ADC4_JEXTSEL_T1CC4 ADC34_JSQR_JEXTSEL_T1CC4 -# define ADC4_JEXTSEL_T1TRGO ADC34_JSQR_JEXTSEL_T1TRGO -# define ADC1_JEXTSEL_T2CC1 ADC12_JSQR_JEXTSEL_T2CC1 -# define ADC1_JEXTSEL_T2CC2 ADC12_JSQR_JEXTSEL_T2CC2 -# define ADC1_JEXTSEL_T2CC3 ADC12_JSQR_JEXTSEL_T2CC3 -# define ADC1_JEXTSEL_T2CC4 ADC12_JSQR_JEXTSEL_T2CC4 -# define ADC1_JEXTSEL_T2TRGO ADC12_JSQR_JEXTSEL_T2TRGO -# define ADC2_JEXTSEL_T2CC1 ADC12_JSQR_JEXTSEL_T2CC1 -# define ADC2_JEXTSEL_T2CC2 ADC12_JSQR_JEXTSEL_T2CC2 -# define ADC2_JEXTSEL_T2CC3 ADC12_JSQR_JEXTSEL_T2CC3 -# define ADC2_JEXTSEL_T2CC4 ADC12_JSQR_JEXTSEL_T2CC4 -# define ADC2_JEXTSEL_T2TRGO ADC12_JSQR_JEXTSEL_T2TRGO -# define ADC3_JEXTSEL_T2CC1 ADC34_JSQR_JEXTSEL_T2CC1 -# define ADC3_JEXTSEL_T2CC2 ADC34_JSQR_JEXTSEL_T2CC2 -# define ADC3_JEXTSEL_T2CC3 ADC34_JSQR_JEXTSEL_T2CC3 -# define ADC3_JEXTSEL_T2CC4 ADC34_JSQR_JEXTSEL_T2CC4 -# define ADC3_JEXTSEL_T2TRGO ADC34_JSQR_JEXTSEL_T2TRGO -# define ADC4_JEXTSEL_T2CC1 ADC34_JSQR_JEXTSEL_T2CC1 -# define ADC4_JEXTSEL_T2CC2 ADC34_JSQR_JEXTSEL_T2CC2 -# define ADC4_JEXTSEL_T2CC3 ADC34_JSQR_JEXTSEL_T2CC3 -# define ADC4_JEXTSEL_T2CC4 ADC34_JSQR_JEXTSEL_T2CC4 -# define ADC4_JEXTSEL_T2TRGO ADC34_JSQR_JEXTSEL_T2TRGO -# define ADC1_JEXTSEL_T3CC1 ADC12_JSQR_JEXTSEL_T3CC1 -# define ADC1_JEXTSEL_T3CC2 ADC12_JSQR_JEXTSEL_T3CC2 -# define ADC1_JEXTSEL_T3CC3 ADC12_JSQR_JEXTSEL_T3CC3 -# define ADC1_JEXTSEL_T3CC4 ADC12_JSQR_JEXTSEL_T3CC4 -# define ADC1_JEXTSEL_T3TRGO ADC12_JSQR_JEXTSEL_T3TRGO -# define ADC2_JEXTSEL_T3CC1 ADC12_JSQR_JEXTSEL_T3CC1 -# define ADC2_JEXTSEL_T3CC2 ADC12_JSQR_JEXTSEL_T3CC2 -# define ADC2_JEXTSEL_T3CC3 ADC12_JSQR_JEXTSEL_T3CC3 -# define ADC2_JEXTSEL_T3CC4 ADC12_JSQR_JEXTSEL_T3CC4 -# define ADC2_JEXTSEL_T3TRGO ADC12_JSQR_JEXTSEL_T3TRGO -# define ADC3_JEXTSEL_T3CC1 ADC34_JSQR_JEXTSEL_T3CC1 -# define ADC3_JEXTSEL_T3CC2 ADC34_JSQR_JEXTSEL_T3CC2 -# define ADC3_JEXTSEL_T3CC3 ADC34_JSQR_JEXTSEL_T3CC3 -# define ADC3_JEXTSEL_T3CC4 ADC34_JSQR_JEXTSEL_T3CC4 -# define ADC3_JEXTSEL_T3TRGO ADC34_JSQR_JEXTSEL_T3TRGO -# define ADC4_JEXTSEL_T3CC1 ADC34_JSQR_JEXTSEL_T3CC1 -# define ADC4_JEXTSEL_T3CC2 ADC34_JSQR_JEXTSEL_T3CC2 -# define ADC4_JEXTSEL_T3CC3 ADC34_JSQR_JEXTSEL_T3CC3 -# define ADC4_JEXTSEL_T3CC4 ADC34_JSQR_JEXTSEL_T3CC4 -# define ADC4_JEXTSEL_T3TRGO ADC34_JSQR_JEXTSEL_T3TRGO -# define ADC1_JEXTSEL_T4CC1 ADC12_JSQR_JEXTSEL_T4CC1 -# define ADC1_JEXTSEL_T4CC2 ADC12_JSQR_JEXTSEL_T4CC2 -# define ADC1_JEXTSEL_T4CC3 ADC12_JSQR_JEXTSEL_T4CC3 -# define ADC1_JEXTSEL_T4CC4 ADC12_JSQR_JEXTSEL_T4CC4 -# define ADC1_JEXTSEL_T4TRGO ADC12_JSQR_JEXTSEL_T4TRGO -# define ADC2_JEXTSEL_T4CC1 ADC12_JSQR_JEXTSEL_T4CC1 -# define ADC2_JEXTSEL_T4CC2 ADC12_JSQR_JEXTSEL_T4CC2 -# define ADC2_JEXTSEL_T4CC3 ADC12_JSQR_JEXTSEL_T4CC3 -# define ADC2_JEXTSEL_T4CC4 ADC12_JSQR_JEXTSEL_T4CC4 -# define ADC2_JEXTSEL_T4TRGO ADC12_JSQR_JEXTSEL_T4TRGO -# define ADC3_JEXTSEL_T4CC1 ADC34_JSQR_JEXTSEL_T4CC1 -# define ADC3_JEXTSEL_T4CC2 ADC34_JSQR_JEXTSEL_T4CC2 -# define ADC3_JEXTSEL_T4CC3 ADC34_JSQR_JEXTSEL_T4CC3 -# define ADC3_JEXTSEL_T4CC4 ADC34_JSQR_JEXTSEL_T4CC4 -# define ADC3_JEXTSEL_T4TRGO ADC34_JSQR_JEXTSEL_T4TRGO -# define ADC4_JEXTSEL_T4CC1 ADC34_JSQR_JEXTSEL_T4CC1 -# define ADC4_JEXTSEL_T4CC2 ADC34_JSQR_JEXTSEL_T4CC2 -# define ADC4_JEXTSEL_T4CC3 ADC34_JSQR_JEXTSEL_T4CC3 -# define ADC4_JEXTSEL_T4CC4 ADC34_JSQR_JEXTSEL_T4CC4 -# define ADC4_JEXTSEL_T4TRGO ADC34_JSQR_JEXTSEL_T4TRGO -# define ADC1_JEXTSEL_T5CC1 ADC12_JSQR_JEXTSEL_T5CC1 -# define ADC1_JEXTSEL_T5CC2 ADC12_JSQR_JEXTSEL_T5CC2 -# define ADC1_JEXTSEL_T5CC3 ADC12_JSQR_JEXTSEL_T5CC3 -# define ADC1_JEXTSEL_T5CC4 ADC12_JSQR_JEXTSEL_T5CC4 -# define ADC1_JEXTSEL_T5TRGO ADC12_JSQR_JEXTSEL_T5TRGO -# define ADC2_JEXTSEL_T5CC1 ADC12_JSQR_JEXTSEL_T5CC1 -# define ADC2_JEXTSEL_T5CC2 ADC12_JSQR_JEXTSEL_T5CC2 -# define ADC2_JEXTSEL_T5CC3 ADC12_JSQR_JEXTSEL_T5CC3 -# define ADC2_JEXTSEL_T5CC4 ADC12_JSQR_JEXTSEL_T5CC4 -# define ADC2_JEXTSEL_T5TRGO ADC12_JSQR_JEXTSEL_T5TRGO -# define ADC3_JEXTSEL_T5CC1 ADC34_JSQR_JEXTSEL_T5CC1 -# define ADC3_JEXTSEL_T5CC2 ADC34_JSQR_JEXTSEL_T5CC2 -# define ADC3_JEXTSEL_T5CC3 ADC34_JSQR_JEXTSEL_T5CC3 -# define ADC3_JEXTSEL_T5CC4 ADC34_JSQR_JEXTSEL_T5CC4 -# define ADC3_JEXTSEL_T5TRGO ADC34_JSQR_JEXTSEL_T5TRGO -# define ADC4_JEXTSEL_T5CC1 ADC34_JSQR_JEXTSEL_T5CC1 -# define ADC4_JEXTSEL_T5CC2 ADC34_JSQR_JEXTSEL_T5CC2 -# define ADC4_JEXTSEL_T5CC3 ADC34_JSQR_JEXTSEL_T5CC3 -# define ADC4_JEXTSEL_T5CC4 ADC34_JSQR_JEXTSEL_T5CC4 -# define ADC4_JEXTSEL_T5TRGO ADC34_JSQR_JEXTSEL_T5TRGO -# define ADC1_JEXTSEL_T6CC1 ADC12_JSQR_JEXTSEL_T6CC1 -# define ADC1_JEXTSEL_T6CC2 ADC12_JSQR_JEXTSEL_T6CC2 -# define ADC1_JEXTSEL_T6CC3 ADC12_JSQR_JEXTSEL_T6CC3 -# define ADC1_JEXTSEL_T6CC4 ADC12_JSQR_JEXTSEL_T6CC4 -# define ADC1_JEXTSEL_T6TRGO ADC12_JSQR_JEXTSEL_T6TRGO -# define ADC2_JEXTSEL_T6CC1 ADC12_JSQR_JEXTSEL_T6CC1 -# define ADC2_JEXTSEL_T6CC2 ADC12_JSQR_JEXTSEL_T6CC2 -# define ADC2_JEXTSEL_T6CC3 ADC12_JSQR_JEXTSEL_T6CC3 -# define ADC2_JEXTSEL_T6CC4 ADC12_JSQR_JEXTSEL_T6CC4 -# define ADC2_JEXTSEL_T6TRGO ADC12_JSQR_JEXTSEL_T6TRGO -# define ADC3_JEXTSEL_T6CC1 ADC34_JSQR_JEXTSEL_T6CC1 -# define ADC3_JEXTSEL_T6CC2 ADC34_JSQR_JEXTSEL_T6CC2 -# define ADC3_JEXTSEL_T6CC3 ADC34_JSQR_JEXTSEL_T6CC3 -# define ADC3_JEXTSEL_T6CC4 ADC34_JSQR_JEXTSEL_T6CC4 -# define ADC3_JEXTSEL_T6TRGO ADC34_JSQR_JEXTSEL_T6TRGO -# define ADC4_JEXTSEL_T6CC1 ADC34_JSQR_JEXTSEL_T6CC1 -# define ADC4_JEXTSEL_T6CC2 ADC34_JSQR_JEXTSEL_T6CC2 -# define ADC4_JEXTSEL_T6CC3 ADC34_JSQR_JEXTSEL_T6CC3 -# define ADC4_JEXTSEL_T6CC4 ADC34_JSQR_JEXTSEL_T6CC4 -# define ADC4_JEXTSEL_T6TRGO ADC34_JSQR_JEXTSEL_T6TRGO -# define ADC1_JEXTSEL_T7CC1 ADC12_JSQR_JEXTSEL_T7CC1 -# define ADC1_JEXTSEL_T7CC2 ADC12_JSQR_JEXTSEL_T7CC2 -# define ADC1_JEXTSEL_T7CC3 ADC12_JSQR_JEXTSEL_T7CC3 -# define ADC1_JEXTSEL_T7CC4 ADC12_JSQR_JEXTSEL_T7CC4 -# define ADC1_JEXTSEL_T7TRGO ADC12_JSQR_JEXTSEL_T7TRGO -# define ADC2_JEXTSEL_T7CC1 ADC12_JSQR_JEXTSEL_T7CC1 -# define ADC2_JEXTSEL_T7CC2 ADC12_JSQR_JEXTSEL_T7CC2 -# define ADC2_JEXTSEL_T7CC3 ADC12_JSQR_JEXTSEL_T7CC3 -# define ADC2_JEXTSEL_T7CC4 ADC12_JSQR_JEXTSEL_T7CC4 -# define ADC2_JEXTSEL_T7TRGO ADC12_JSQR_JEXTSEL_T7TRGO -# define ADC3_JEXTSEL_T7CC1 ADC34_JSQR_JEXTSEL_T7CC1 -# define ADC3_JEXTSEL_T7CC2 ADC34_JSQR_JEXTSEL_T7CC2 -# define ADC3_JEXTSEL_T7CC3 ADC34_JSQR_JEXTSEL_T7CC3 -# define ADC3_JEXTSEL_T7CC4 ADC34_JSQR_JEXTSEL_T7CC4 -# define ADC3_JEXTSEL_T7TRGO ADC34_JSQR_JEXTSEL_T7TRGO -# define ADC4_JEXTSEL_T7CC1 ADC34_JSQR_JEXTSEL_T7CC1 -# define ADC4_JEXTSEL_T7CC2 ADC34_JSQR_JEXTSEL_T7CC2 -# define ADC4_JEXTSEL_T7CC3 ADC34_JSQR_JEXTSEL_T7CC3 -# define ADC4_JEXTSEL_T7CC4 ADC34_JSQR_JEXTSEL_T7CC4 -# define ADC4_JEXTSEL_T7TRGO ADC34_JSQR_JEXTSEL_T7TRGO -# define ADC1_JEXTSEL_T8CC1 ADC12_JSQR_JEXTSEL_T8CC1 -# define ADC1_JEXTSEL_T8CC2 ADC12_JSQR_JEXTSEL_T8CC2 -# define ADC1_JEXTSEL_T8CC3 ADC12_JSQR_JEXTSEL_T8CC3 -# define ADC1_JEXTSEL_T8CC4 ADC12_JSQR_JEXTSEL_T8CC4 -# define ADC1_JEXTSEL_T8TRGO ADC12_JSQR_JEXTSEL_T8TRGO -# define ADC2_JEXTSEL_T8CC1 ADC12_JSQR_JEXTSEL_T8CC1 -# define ADC2_JEXTSEL_T8CC2 ADC12_JSQR_JEXTSEL_T8CC2 -# define ADC2_JEXTSEL_T8CC3 ADC12_JSQR_JEXTSEL_T8CC3 -# define ADC2_JEXTSEL_T8CC4 ADC12_JSQR_JEXTSEL_T8CC4 -# define ADC2_JEXTSEL_T8TRGO ADC12_JSQR_JEXTSEL_T8TRGO -# define ADC3_JEXTSEL_T8CC1 ADC34_JSQR_JEXTSEL_T8CC1 -# define ADC3_JEXTSEL_T8CC2 ADC34_JSQR_JEXTSEL_T8CC2 -# define ADC3_JEXTSEL_T8CC3 ADC34_JSQR_JEXTSEL_T8CC3 -# define ADC3_JEXTSEL_T8CC4 ADC34_JSQR_JEXTSEL_T8CC4 -# define ADC3_JEXTSEL_T8TRGO ADC34_JSQR_JEXTSEL_T8TRGO -# define ADC4_JEXTSEL_T8CC1 ADC34_JSQR_JEXTSEL_T8CC1 -# define ADC4_JEXTSEL_T8CC2 ADC34_JSQR_JEXTSEL_T8CC2 -# define ADC4_JEXTSEL_T8CC3 ADC34_JSQR_JEXTSEL_T8CC3 -# define ADC4_JEXTSEL_T8CC4 ADC34_JSQR_JEXTSEL_T8CC4 -# define ADC4_JEXTSEL_T8TRGO ADC34_JSQR_JEXTSEL_T8TRGO -# define ADC1_JEXTSEL_T9CC1 ADC12_JSQR_JEXTSEL_T9CC1 -# define ADC1_JEXTSEL_T9CC2 ADC12_JSQR_JEXTSEL_T9CC2 -# define ADC1_JEXTSEL_T9CC3 ADC12_JSQR_JEXTSEL_T9CC3 -# define ADC1_JEXTSEL_T9CC4 ADC12_JSQR_JEXTSEL_T9CC4 -# define ADC1_JEXTSEL_T9TRGO ADC12_JSQR_JEXTSEL_T9TRGO -# define ADC2_JEXTSEL_T9CC1 ADC12_JSQR_JEXTSEL_T9CC1 -# define ADC2_JEXTSEL_T9CC2 ADC12_JSQR_JEXTSEL_T9CC2 -# define ADC2_JEXTSEL_T9CC3 ADC12_JSQR_JEXTSEL_T9CC3 -# define ADC2_JEXTSEL_T9CC4 ADC12_JSQR_JEXTSEL_T9CC4 -# define ADC2_JEXTSEL_T9TRGO ADC12_JSQR_JEXTSEL_T9TRGO -# define ADC3_JEXTSEL_T9CC1 ADC34_JSQR_JEXTSEL_T9CC1 -# define ADC3_JEXTSEL_T9CC2 ADC34_JSQR_JEXTSEL_T9CC2 -# define ADC3_JEXTSEL_T9CC3 ADC34_JSQR_JEXTSEL_T9CC3 -# define ADC3_JEXTSEL_T9CC4 ADC34_JSQR_JEXTSEL_T9CC4 -# define ADC3_JEXTSEL_T9TRGO ADC34_JSQR_JEXTSEL_T9TRGO -# define ADC4_JEXTSEL_T9CC1 ADC34_JSQR_JEXTSEL_T9CC1 -# define ADC4_JEXTSEL_T9CC2 ADC34_JSQR_JEXTSEL_T9CC2 -# define ADC4_JEXTSEL_T9CC3 ADC34_JSQR_JEXTSEL_T9CC3 -# define ADC4_JEXTSEL_T9CC4 ADC34_JSQR_JEXTSEL_T9CC4 -# define ADC4_JEXTSEL_T9TRGO ADC34_JSQR_JEXTSEL_T9TRGO -# define ADC1_JEXTSEL_T10CC1 ADC12_JSQR_JEXTSEL_T10CC1 -# define ADC1_JEXTSEL_T10CC2 ADC12_JSQR_JEXTSEL_T10CC2 -# define ADC1_JEXTSEL_T10CC3 ADC12_JSQR_JEXTSEL_T10CC3 -# define ADC1_JEXTSEL_T10CC4 ADC12_JSQR_JEXTSEL_T10CC4 -# define ADC1_JEXTSEL_T10TRGO ADC12_JSQR_JEXTSEL_T10TRGO -# define ADC2_JEXTSEL_T10CC1 ADC12_JSQR_JEXTSEL_T10CC1 -# define ADC2_JEXTSEL_T10CC2 ADC12_JSQR_JEXTSEL_T10CC2 -# define ADC2_JEXTSEL_T10CC3 ADC12_JSQR_JEXTSEL_T10CC3 -# define ADC2_JEXTSEL_T10CC4 ADC12_JSQR_JEXTSEL_T10CC4 -# define ADC2_JEXTSEL_T10TRGO ADC12_JSQR_JEXTSEL_T10TRGO -# define ADC3_JEXTSEL_T10CC1 ADC34_JSQR_JEXTSEL_T10CC1 -# define ADC3_JEXTSEL_T10CC2 ADC34_JSQR_JEXTSEL_T10CC2 -# define ADC3_JEXTSEL_T10CC3 ADC34_JSQR_JEXTSEL_T10CC3 -# define ADC3_JEXTSEL_T10CC4 ADC34_JSQR_JEXTSEL_T10CC4 -# define ADC3_JEXTSEL_T10TRGO ADC34_JSQR_JEXTSEL_T10TRGO -# define ADC4_JEXTSEL_T10CC1 ADC34_JSQR_JEXTSEL_T10CC1 -# define ADC4_JEXTSEL_T10CC2 ADC34_JSQR_JEXTSEL_T10CC2 -# define ADC4_JEXTSEL_T10CC3 ADC34_JSQR_JEXTSEL_T10CC3 -# define ADC4_JEXTSEL_T10CC4 ADC34_JSQR_JEXTSEL_T10CC4 -# define ADC4_JEXTSEL_T10TRGO ADC34_JSQR_JEXTSEL_T10TRGO -# define ADC1_JEXTSEL_T15CC1 ADC12_JSQR_JEXTSEL_T15CC1 -# define ADC1_JEXTSEL_T15CC2 ADC12_JSQR_JEXTSEL_T15CC2 -# define ADC1_JEXTSEL_T15CC3 ADC12_JSQR_JEXTSEL_T15CC3 -# define ADC1_JEXTSEL_T15CC4 ADC12_JSQR_JEXTSEL_T15CC4 -# define ADC1_JEXTSEL_T15TRGO ADC12_JSQR_JEXTSEL_T15TRGO -# define ADC2_JEXTSEL_T15CC1 ADC12_JSQR_JEXTSEL_T15CC1 -# define ADC2_JEXTSEL_T15CC2 ADC12_JSQR_JEXTSEL_T15CC2 -# define ADC2_JEXTSEL_T15CC3 ADC12_JSQR_JEXTSEL_T15CC3 -# define ADC2_JEXTSEL_T15CC4 ADC12_JSQR_JEXTSEL_T15CC4 -# define ADC2_JEXTSEL_T15TRGO ADC12_JSQR_JEXTSEL_T15TRGO -# define ADC3_JEXTSEL_T15CC1 ADC34_JSQR_JEXTSEL_T15CC1 -# define ADC3_JEXTSEL_T15CC2 ADC34_JSQR_JEXTSEL_T15CC2 -# define ADC3_JEXTSEL_T15CC3 ADC34_JSQR_JEXTSEL_T15CC3 -# define ADC3_JEXTSEL_T15CC4 ADC34_JSQR_JEXTSEL_T15CC4 -# define ADC3_JEXTSEL_T15TRGO ADC34_JSQR_JEXTSEL_T15TRGO -# define ADC4_JEXTSEL_T15CC1 ADC34_JSQR_JEXTSEL_T15CC1 -# define ADC4_JEXTSEL_T15CC2 ADC34_JSQR_JEXTSEL_T15CC2 -# define ADC4_JEXTSEL_T15CC3 ADC34_JSQR_JEXTSEL_T15CC3 -# define ADC4_JEXTSEL_T15CC4 ADC34_JSQR_JEXTSEL_T15CC4 -# define ADC4_JEXTSEL_T15TRGO ADC34_JSQR_JEXTSEL_T15TRGO -# define ADC1_JEXTSEL_T20CC1 ADC12_JSQR_JEXTSEL_T20CC1 -# define ADC1_JEXTSEL_T20CC2 ADC12_JSQR_JEXTSEL_T20CC2 -# define ADC1_JEXTSEL_T20CC3 ADC12_JSQR_JEXTSEL_T20CC3 -# define ADC1_JEXTSEL_T20CC4 ADC12_JSQR_JEXTSEL_T20CC4 -# define ADC1_JEXTSEL_T20TRGO ADC12_JSQR_JEXTSEL_T20TRGO -# define ADC2_JEXTSEL_T20CC1 ADC12_JSQR_JEXTSEL_T20CC1 -# define ADC2_JEXTSEL_T20CC2 ADC12_JSQR_JEXTSEL_T20CC2 -# define ADC2_JEXTSEL_T20CC3 ADC12_JSQR_JEXTSEL_T20CC3 -# define ADC2_JEXTSEL_T20CC4 ADC12_JSQR_JEXTSEL_T20CC4 -# define ADC2_JEXTSEL_T20TRGO ADC12_JSQR_JEXTSEL_T20TRGO -# define ADC3_JEXTSEL_T20CC1 ADC34_JSQR_JEXTSEL_T20CC1 -# define ADC3_JEXTSEL_T20CC2 ADC34_JSQR_JEXTSEL_T20CC2 -# define ADC3_JEXTSEL_T20CC3 ADC34_JSQR_JEXTSEL_T20CC3 -# define ADC3_JEXTSEL_T20CC4 ADC34_JSQR_JEXTSEL_T20CC4 -# define ADC3_JEXTSEL_T20TRGO ADC34_JSQR_JEXTSEL_T20TRGO -# define ADC4_JEXTSEL_T20CC1 ADC34_JSQR_JEXTSEL_T20CC1 -# define ADC4_JEXTSEL_T20CC2 ADC34_JSQR_JEXTSEL_T20CC2 -# define ADC4_JEXTSEL_T20CC3 ADC34_JSQR_JEXTSEL_T20CC3 -# define ADC4_JEXTSEL_T20CC4 ADC34_JSQR_JEXTSEL_T20CC4 -# define ADC4_JEXTSEL_T20TRGO ADC34_JSQR_JEXTSEL_T20TRGO -# define ADC1_JEXTSEL_HRTTRG2 ADC12_JSQR_JEXTSEL_HRT1TRG2 -# define ADC1_JEXTSEL_HRTTRG4 ADC12_JSQR_JEXTSEL_HRT1TRG4 -# define ADC2_JEXTSEL_HRTTRG2 ADC12_JSQR_JEXTSEL_HRT1TRG2 -# define ADC2_JEXTSEL_HRTTRG4 ADC12_JSQR_JEXTSEL_HRT1TRG4 -#endif - -/* EXTSEL configuration *****************************************************/ - -/* NOTE: - * this configuration if used only if CONFIG_STM32_TIMx_ADCy is selected. - * You can still connect the ADC with a timer trigger using the - * CONFIG_STM32_ADCx_EXTSEL option. - */ - -#if defined(CONFIG_STM32_TIM1_ADC1) -# if CONFIG_STM32_ADC1_TIMTRIG == 0 -# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T1CC1 -# elif CONFIG_STM32_ADC1_TIMTRIG == 1 -# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T1CC2 -# elif CONFIG_STM32_ADC1_TIMTRIG == 2 -# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T1CC3 -# elif CONFIG_STM32_ADC1_TIMTRIG == 3 -# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T1CC4 -# elif CONFIG_STM32_ADC1_TIMTRIG == 4 -# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T1TRGO -# elif CONFIG_STM32_ADC1_TIMTRIG == 5 -# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T1TRGO2 -# else -# error "CONFIG_STM32_ADC1_TIMTRIG is out of range" -# endif -#elif defined(CONFIG_STM32_TIM2_ADC1) -# if CONFIG_STM32_ADC1_TIMTRIG == 0 -# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T2CC1 -# elif CONFIG_STM32_ADC1_TIMTRIG == 1 -# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T2CC2 -# elif CONFIG_STM32_ADC1_TIMTRIG == 2 -# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T2CC3 -# elif CONFIG_STM32_ADC1_TIMTRIG == 3 -# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T2CC4 -# elif CONFIG_STM32_ADC1_TIMTRIG == 4 -# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T2TRGO -# else -# error "CONFIG_STM32_ADC1_TIMTRIG is out of range" -# endif -#elif defined(CONFIG_STM32_TIM3_ADC1) -# if CONFIG_STM32_ADC1_TIMTRIG == 0 -# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T3CC1 -# elif CONFIG_STM32_ADC1_TIMTRIG == 1 -# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T3CC2 -# elif CONFIG_STM32_ADC1_TIMTRIG == 2 -# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T3CC3 -# elif CONFIG_STM32_ADC1_TIMTRIG == 3 -# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T3CC4 -# elif CONFIG_STM32_ADC1_TIMTRIG == 4 -# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T3TRGO -# else -# error "CONFIG_STM32_ADC1_TIMTRIG is out of range" -# endif -#elif defined(CONFIG_STM32_TIM4_ADC1) -# if CONFIG_STM32_ADC1_TIMTRIG == 0 -# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T4CC1 -# elif CONFIG_STM32_ADC1_TIMTRIG == 1 -# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T4CC2 -# elif CONFIG_STM32_ADC1_TIMTRIG == 2 -# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T4CC3 -# elif CONFIG_STM32_ADC1_TIMTRIG == 3 -# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T4CC4 -# elif CONFIG_STM32_ADC1_TIMTRIG == 4 -# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T4TRGO -# else -# error "CONFIG_STM32_ADC1_TIMTRIG is out of range" -# endif -#elif defined(CONFIG_STM32_TIM5_ADC1) -# if CONFIG_STM32_ADC1_TIMTRIG == 0 -# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T5CC1 -# elif CONFIG_STM32_ADC1_TIMTRIG == 1 -# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T5CC2 -# elif CONFIG_STM32_ADC1_TIMTRIG == 2 -# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T5CC3 -# elif CONFIG_STM32_ADC1_TIMTRIG == 3 -# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T5CC4 -# elif CONFIG_STM32_ADC1_TIMTRIG == 4 -# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T5TRGO -# else -# error "CONFIG_STM32_ADC1_TIMTRIG is out of range" -# endif -#elif defined(CONFIG_STM32_TIM6_ADC1) -# if CONFIG_STM32_ADC1_TIMTRIG == 0 -# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T6CC1 -# elif CONFIG_STM32_ADC1_TIMTRIG == 1 -# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T6CC2 -# elif CONFIG_STM32_ADC1_TIMTRIG == 2 -# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T6CC3 -# elif CONFIG_STM32_ADC1_TIMTRIG == 3 -# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T6CC4 -# elif CONFIG_STM32_ADC1_TIMTRIG == 4 -# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T6TRGO -# else -# error "CONFIG_STM32_ADC1_TIMTRIG is out of range" -# endif -#elif defined(CONFIG_STM32_TIM7_ADC1) -# if CONFIG_STM32_ADC1_TIMTRIG == 0 -# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T7CC1 -# elif CONFIG_STM32_ADC1_TIMTRIG == 1 -# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T7CC2 -# elif CONFIG_STM32_ADC1_TIMTRIG == 2 -# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T7CC3 -# elif CONFIG_STM32_ADC1_TIMTRIG == 3 -# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T7CC4 -# elif CONFIG_STM32_ADC1_TIMTRIG == 4 -# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T7TRGO -# else -# error "CONFIG_STM32_ADC1_TIMTRIG is out of range" -# endif -#elif defined(CONFIG_STM32_TIM8_ADC1) -# if CONFIG_STM32_ADC1_TIMTRIG == 0 -# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T8CC1 -# elif CONFIG_STM32_ADC1_TIMTRIG == 1 -# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T8CC2 -# elif CONFIG_STM32_ADC1_TIMTRIG == 2 -# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T8CC3 -# elif CONFIG_STM32_ADC1_TIMTRIG == 3 -# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T8CC4 -# elif CONFIG_STM32_ADC1_TIMTRIG == 4 -# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T8TRGO -# elif CONFIG_STM32_ADC1_TIMTRIG == 5 -# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T8TRGO2 -# else -# error "CONFIG_STM32_ADC1_TIMTRIG is out of range" -# endif -#elif defined(CONFIG_STM32_TIM9_ADC1) -# if CONFIG_STM32_ADC1_TIMTRIG == 0 -# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T9CC1 -# elif CONFIG_STM32_ADC1_TIMTRIG == 1 -# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T9CC2 -# elif CONFIG_STM32_ADC1_TIMTRIG == 2 -# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T9CC3 -# elif CONFIG_STM32_ADC1_TIMTRIG == 3 -# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T9CC4 -# elif CONFIG_STM32_ADC1_TIMTRIG == 4 -# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T9TRGO -# else -# error "CONFIG_STM32_ADC1_TIMTRIG is out of range" -# endif -#elif defined(CONFIG_STM32_TIM10_ADC1) -# if CONFIG_STM32_ADC1_TIMTRIG == 0 -# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T10CC1 -# elif CONFIG_STM32_ADC1_TIMTRIG == 1 -# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T10CC2 -# elif CONFIG_STM32_ADC1_TIMTRIG == 2 -# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T10CC3 -# elif CONFIG_STM32_ADC1_TIMTRIG == 3 -# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T10CC4 -# elif CONFIG_STM32_ADC1_TIMTRIG == 4 -# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T10TRGO -# else -# error "CONFIG_STM32_ADC1_TIMTRIG is out of range" -# endif -#elif defined(CONFIG_STM32_TIM15_ADC1) -# if CONFIG_STM32_ADC1_TIMTRIG == 0 -# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T15CC1 -# elif CONFIG_STM32_ADC1_TIMTRIG == 1 -# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T15CC2 -# elif CONFIG_STM32_ADC1_TIMTRIG == 2 -# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T15CC3 -# elif CONFIG_STM32_ADC1_TIMTRIG == 3 -# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T15CC4 -# elif CONFIG_STM32_ADC1_TIMTRIG == 4 -# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T15TRGO -# else -# error "CONFIG_STM32_ADC1_TIMTRIG is out of range" -# endif -#elif defined(CONFIG_STM32_HRTIM_ADC1_TRG1) -# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_HRTTRG1 -#elif defined(CONFIG_STM32_HRTIM_ADC1_TRG3) -# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_HRTTRG3 -#endif - -#if defined(CONFIG_STM32_TIM1_ADC2) -# if CONFIG_STM32_ADC2_TIMTRIG == 0 -# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T1CC1 -# elif CONFIG_STM32_ADC2_TIMTRIG == 1 -# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T1CC2 -# elif CONFIG_STM32_ADC2_TIMTRIG == 2 -# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T1CC3 -# elif CONFIG_STM32_ADC2_TIMTRIG == 3 -# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T1CC4 -# elif CONFIG_STM32_ADC2_TIMTRIG == 4 -# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T1TRGO -# elif CONFIG_STM32_ADC2_TIMTRIG == 5 -# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T1TRGO2 -# else -# error "CONFIG_STM32_ADC2_TIMTRIG is out of range" -# endif -#elif defined(CONFIG_STM32_TIM2_ADC2) -# if CONFIG_STM32_ADC2_TIMTRIG == 0 -# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T2CC1 -# elif CONFIG_STM32_ADC2_TIMTRIG == 1 -# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T2CC2 -# elif CONFIG_STM32_ADC2_TIMTRIG == 2 -# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T2CC3 -# elif CONFIG_STM32_ADC2_TIMTRIG == 3 -# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T2CC4 -# elif CONFIG_STM32_ADC2_TIMTRIG == 4 -# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T2TRGO -# else -# error "CONFIG_STM32_ADC2_TIMTRIG is out of range" -# endif -#elif defined(CONFIG_STM32_TIM3_ADC2) -# if CONFIG_STM32_ADC2_TIMTRIG == 0 -# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T3CC1 -# elif CONFIG_STM32_ADC2_TIMTRIG == 1 -# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T3CC2 -# elif CONFIG_STM32_ADC2_TIMTRIG == 2 -# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T3CC3 -# elif CONFIG_STM32_ADC2_TIMTRIG == 3 -# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T3CC4 -# elif CONFIG_STM32_ADC2_TIMTRIG == 4 -# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T3TRGO -# else -# error "CONFIG_STM32_ADC2_TIMTRIG is out of range" -# endif -#elif defined(CONFIG_STM32_TIM4_ADC2) -# if CONFIG_STM32_ADC2_TIMTRIG == 0 -# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T4CC1 -# elif CONFIG_STM32_ADC2_TIMTRIG == 1 -# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T4CC2 -# elif CONFIG_STM32_ADC2_TIMTRIG == 2 -# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T4CC3 -# elif CONFIG_STM32_ADC2_TIMTRIG == 3 -# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T4CC4 -# elif CONFIG_STM32_ADC2_TIMTRIG == 4 -# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T4TRGO -# else -# error "CONFIG_STM32_ADC2_TIMTRIG is out of range" -# endif -#elif defined(CONFIG_STM32_TIM5_ADC2) -# if CONFIG_STM32_ADC2_TIMTRIG == 0 -# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T5CC1 -# elif CONFIG_STM32_ADC2_TIMTRIG == 1 -# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T5CC2 -# elif CONFIG_STM32_ADC2_TIMTRIG == 2 -# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T5CC3 -# elif CONFIG_STM32_ADC2_TIMTRIG == 3 -# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T5CC4 -# elif CONFIG_STM32_ADC2_TIMTRIG == 4 -# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T5TRGO -# else -# error "CONFIG_STM32_ADC2_TIMTRIG is out of range" -# endif -#elif defined(CONFIG_STM32_TIM6_ADC2) -# if CONFIG_STM32_ADC2_TIMTRIG == 0 -# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T6CC1 -# elif CONFIG_STM32_ADC2_TIMTRIG == 1 -# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T6CC2 -# elif CONFIG_STM32_ADC2_TIMTRIG == 2 -# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T6CC3 -# elif CONFIG_STM32_ADC2_TIMTRIG == 3 -# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T6CC4 -# elif CONFIG_STM32_ADC2_TIMTRIG == 4 -# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T6TRGO -# else -# error "CONFIG_STM32_ADC2_TIMTRIG is out of range" -# endif -#elif defined(CONFIG_STM32_TIM8_ADC2) -# if CONFIG_STM32_ADC2_TIMTRIG == 0 -# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T8CC1 -# elif CONFIG_STM32_ADC2_TIMTRIG == 1 -# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T8CC2 -# elif CONFIG_STM32_ADC2_TIMTRIG == 2 -# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T8CC3 -# elif CONFIG_STM32_ADC2_TIMTRIG == 3 -# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T8CC4 -# elif CONFIG_STM32_ADC2_TIMTRIG == 4 -# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T8TRGO -# elif CONFIG_STM32_ADC2_TIMTRIG == 5 -# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T8TRGO2 -# else -# error "CONFIG_STM32_ADC2_TIMTRIG is out of range" -# endif -#elif defined(CONFIG_STM32_TIM15_ADC2) -# if CONFIG_STM32_ADC2_TIMTRIG == 0 -# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T15CC1 -# elif CONFIG_STM32_ADC2_TIMTRIG == 1 -# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T15CC2 -# elif CONFIG_STM32_ADC2_TIMTRIG == 2 -# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T15CC3 -# elif CONFIG_STM32_ADC2_TIMTRIG == 3 -# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T15CC4 -# elif CONFIG_STM32_ADC2_TIMTRIG == 4 -# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T15TRGO -# else -# error "CONFIG_STM32_ADC2_TIMTRIG is out of range" -# endif -#elif defined(CONFIG_STM32_HRTIM_ADC2_TRG1) -# define ADC2_EXTSEL_VALUE ADC1_EXTSEL_HRTTRG1 -#elif defined(CONFIG_STM32_HRTIM_ADC1_TRG3) -# define ADC2_EXTSEL_VALUE ADC1_EXTSEL_HRTTRG3 -#endif - -#if defined(CONFIG_STM32_TIM1_ADC3) -# if CONFIG_STM32_ADC3_TIMTRIG == 0 -# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T1CC1 -# elif CONFIG_STM32_ADC3_TIMTRIG == 1 -# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T1CC2 -# elif CONFIG_STM32_ADC3_TIMTRIG == 2 -# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T1CC3 -# elif CONFIG_STM32_ADC3_TIMTRIG == 3 -# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T1CC4 -# elif CONFIG_STM32_ADC3_TIMTRIG == 4 -# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T1TRGO -# elif CONFIG_STM32_ADC3_TIMTRIG == 5 -# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T1TRGO2 -# else -# error "CONFIG_STM32_ADC3_TIMTRIG is out of range" -# endif -#elif defined(CONFIG_STM32_TIM2_ADC3) -# if CONFIG_STM32_ADC3_TIMTRIG == 0 -# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T2CC1 -# elif CONFIG_STM32_ADC3_TIMTRIG == 1 -# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T2CC2 -# elif CONFIG_STM32_ADC3_TIMTRIG == 2 -# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T2CC3 -# elif CONFIG_STM32_ADC3_TIMTRIG == 3 -# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T2CC4 -# elif CONFIG_STM32_ADC3_TIMTRIG == 4 -# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T2TRGO -# else -# error "CONFIG_STM32_ADC3_TIMTRIG is out of range" -# endif -#elif defined(CONFIG_STM32_TIM3_ADC3) -# if CONFIG_STM32_ADC3_TIMTRIG == 0 -# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T3CC1 -# elif CONFIG_STM32_ADC3_TIMTRIG == 1 -# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T3CC2 -# elif CONFIG_STM32_ADC3_TIMTRIG == 2 -# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T3CC3 -# elif CONFIG_STM32_ADC3_TIMTRIG == 3 -# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T3CC4 -# elif CONFIG_STM32_ADC3_TIMTRIG == 4 -# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T3TRGO -# else -# error "CONFIG_STM32_ADC3_TIMTRIG is out of range" -# endif -#elif defined(CONFIG_STM32_TIM4_ADC3) -# if CONFIG_STM32_ADC3_TIMTRIG == 0 -# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T4CC1 -# elif CONFIG_STM32_ADC3_TIMTRIG == 1 -# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T4CC2 -# elif CONFIG_STM32_ADC3_TIMTRIG == 2 -# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T4CC3 -# elif CONFIG_STM32_ADC3_TIMTRIG == 3 -# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T4CC4 -# elif CONFIG_STM32_ADC3_TIMTRIG == 4 -# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T4TRGO -# else -# error "CONFIG_STM32_ADC3_TIMTRIG is out of range" -# endif -#elif defined(CONFIG_STM32_TIM5_ADC3) -# if CONFIG_STM32_ADC3_TIMTRIG == 0 -# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T5CC1 -# elif CONFIG_STM32_ADC3_TIMTRIG == 1 -# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T5CC2 -# elif CONFIG_STM32_ADC3_TIMTRIG == 2 -# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T5CC3 -# elif CONFIG_STM32_ADC3_TIMTRIG == 3 -# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T5CC4 -# elif CONFIG_STM32_ADC3_TIMTRIG == 4 -# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T5TRGO -# else -# error "CONFIG_STM32_ADC3_TIMTRIG is out of range" -# endif -#elif defined(CONFIG_STM32_TIM7_ADC3) -# if CONFIG_STM32_ADC3_TIMTRIG == 0 -# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T7CC1 -# elif CONFIG_STM32_ADC3_TIMTRIG == 1 -# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T7CC2 -# elif CONFIG_STM32_ADC3_TIMTRIG == 2 -# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T7CC3 -# elif CONFIG_STM32_ADC3_TIMTRIG == 3 -# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T7CC4 -# elif CONFIG_STM32_ADC3_TIMTRIG == 4 -# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T7TRGO -# else -# error "CONFIG_STM32_ADC3_TIMTRIG is out of range" -# endif -#elif defined(CONFIG_STM32_TIM8_ADC3) -# if CONFIG_STM32_ADC3_TIMTRIG == 0 -# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T8CC1 -# elif CONFIG_STM32_ADC3_TIMTRIG == 1 -# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T8CC2 -# elif CONFIG_STM32_ADC3_TIMTRIG == 2 -# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T8CC3 -# elif CONFIG_STM32_ADC3_TIMTRIG == 3 -# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T8CC4 -# elif CONFIG_STM32_ADC3_TIMTRIG == 4 -# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T8TRGO -# elif CONFIG_STM32_ADC3_TIMTRIG == 5 -# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T8TRGO2 -# else -# error "CONFIG_STM32_ADC3_TIMTRIG is out of range" -# endif -#elif defined(CONFIG_STM32_TIM15_ADC3) -# if CONFIG_STM32_ADC3_TIMTRIG == 0 -# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T15CC1 -# elif CONFIG_STM32_ADC3_TIMTRIG == 1 -# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T15CC2 -# elif CONFIG_STM32_ADC3_TIMTRIG == 2 -# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T15CC3 -# elif CONFIG_STM32_ADC3_TIMTRIG == 3 -# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T15CC4 -# elif CONFIG_STM32_ADC3_TIMTRIG == 4 -# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T15TRGO -# else -# error "CONFIG_STM32_ADC3_TIMTRIG is out of range" -# endif -#elif defined(CONFIG_STM32_TIM20_ADC3) -# if CONFIG_STM32_ADC3_TIMTRIG == 0 -# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T20CC1 -# elif CONFIG_STM32_ADC3_TIMTRIG == 1 -# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T20CC2 -# elif CONFIG_STM32_ADC3_TIMTRIG == 2 -# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T20CC3 -# elif CONFIG_STM32_ADC3_TIMTRIG == 3 -# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T20CC4 -# elif CONFIG_STM32_ADC3_TIMTRIG == 4 -# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T20TRGO -# else -# error "CONFIG_STM32_ADC3_TIMTRIG is out of range" -# endif -#endif - -#if defined(CONFIG_STM32_TIM1_ADC4) -# if CONFIG_STM32_ADC4_TIMTRIG == 0 -# define ADC4_EXTSEL_VALUE ADC4_EXTSEL_T1CC1 -# elif CONFIG_STM32_ADC4_TIMTRIG == 1 -# define ADC4_EXTSEL_VALUE ADC4_EXTSEL_T1CC2 -# elif CONFIG_STM32_ADC4_TIMTRIG == 2 -# define ADC4_EXTSEL_VALUE ADC4_EXTSEL_T1CC3 -# elif CONFIG_STM32_ADC4_TIMTRIG == 3 -# define ADC4_EXTSEL_VALUE ADC4_EXTSEL_T1CC4 -# elif CONFIG_STM32_ADC4_TIMTRIG == 4 -# define ADC4_EXTSEL_VALUE ADC4_EXTSEL_T1TRGO -# elif CONFIG_STM32_ADC4_TIMTRIG == 5 -# define ADC4_EXTSEL_VALUE ADC4_EXTSEL_T1TRGO2 -# else -# error "CONFIG_STM32_ADC4_TIMTRIG is out of range" -# endif -#elif defined(CONFIG_STM32_TIM2_ADC4) -# if CONFIG_STM32_ADC4_TIMTRIG == 0 -# define ADC4_EXTSEL_VALUE ADC4_EXTSEL_T2CC1 -# elif CONFIG_STM32_ADC4_TIMTRIG == 1 -# define ADC4_EXTSEL_VALUE ADC4_EXTSEL_T2CC2 -# elif CONFIG_STM32_ADC4_TIMTRIG == 2 -# define ADC4_EXTSEL_VALUE ADC4_EXTSEL_T2CC3 -# elif CONFIG_STM32_ADC4_TIMTRIG == 3 -# define ADC4_EXTSEL_VALUE ADC4_EXTSEL_T2CC4 -# elif CONFIG_STM32_ADC4_TIMTRIG == 4 -# define ADC4_EXTSEL_VALUE ADC4_EXTSEL_T2TRGO -# else -# error "CONFIG_STM32_ADC4_TIMTRIG is out of range" -# endif -#elif defined(CONFIG_STM32_TIM3_ADC4) -# if CONFIG_STM32_ADC4_TIMTRIG == 0 -# define ADC4_EXTSEL_VALUE ADC4_EXTSEL_T3CC1 -# elif CONFIG_STM32_ADC4_TIMTRIG == 1 -# define ADC4_EXTSEL_VALUE ADC4_EXTSEL_T3CC2 -# elif CONFIG_STM32_ADC4_TIMTRIG == 2 -# define ADC4_EXTSEL_VALUE ADC4_EXTSEL_T3CC3 -# elif CONFIG_STM32_ADC4_TIMTRIG == 3 -# define ADC4_EXTSEL_VALUE ADC4_EXTSEL_T3CC4 -# elif CONFIG_STM32_ADC4_TIMTRIG == 4 -# define ADC4_EXTSEL_VALUE ADC4_EXTSEL_T3TRGO -# else -# error "CONFIG_STM32_ADC4_TIMTRIG is out of range" -# endif -#elif defined(CONFIG_STM32_TIM4_ADC4) -# if CONFIG_STM32_ADC4_TIMTRIG == 0 -# define ADC4_EXTSEL_VALUE ADC4_EXTSEL_T4CC1 -# elif CONFIG_STM32_ADC4_TIMTRIG == 1 -# define ADC4_EXTSEL_VALUE ADC4_EXTSEL_T4CC2 -# elif CONFIG_STM32_ADC4_TIMTRIG == 2 -# define ADC4_EXTSEL_VALUE ADC4_EXTSEL_T4CC3 -# elif CONFIG_STM32_ADC4_TIMTRIG == 3 -# define ADC4_EXTSEL_VALUE ADC4_EXTSEL_T4CC4 -# elif CONFIG_STM32_ADC4_TIMTRIG == 4 -# define ADC4_EXTSEL_VALUE ADC4_EXTSEL_T4TRGO -# else -# error "CONFIG_STM32_ADC4_TIMTRIG is out of range" -# endif -#elif defined(CONFIG_STM32_TIM5_ADC4) -# if CONFIG_STM32_ADC4_TIMTRIG == 0 -# define ADC4_EXTSEL_VALUE ADC4_EXTSEL_T5CC1 -# elif CONFIG_STM32_ADC4_TIMTRIG == 1 -# define ADC4_EXTSEL_VALUE ADC4_EXTSEL_T5CC2 -# elif CONFIG_STM32_ADC4_TIMTRIG == 2 -# define ADC4_EXTSEL_VALUE ADC4_EXTSEL_T5CC3 -# elif CONFIG_STM32_ADC4_TIMTRIG == 3 -# define ADC4_EXTSEL_VALUE ADC4_EXTSEL_T5CC4 -# elif CONFIG_STM32_ADC4_TIMTRIG == 4 -# define ADC4_EXTSEL_VALUE ADC4_EXTSEL_T5TRGO -# else -# error "CONFIG_STM32_ADC4_TIMTRIG is out of range" -# endif -#elif defined(CONFIG_STM32_TIM7_ADC4) -# if CONFIG_STM32_ADC4_TIMTRIG == 0 -# define ADC4_EXTSEL_VALUE ADC4_EXTSEL_T7CC1 -# elif CONFIG_STM32_ADC4_TIMTRIG == 1 -# define ADC4_EXTSEL_VALUE ADC4_EXTSEL_T7CC2 -# elif CONFIG_STM32_ADC4_TIMTRIG == 2 -# define ADC4_EXTSEL_VALUE ADC4_EXTSEL_T7CC3 -# elif CONFIG_STM32_ADC4_TIMTRIG == 3 -# define ADC4_EXTSEL_VALUE ADC4_EXTSEL_T7CC4 -# elif CONFIG_STM32_ADC4_TIMTRIG == 4 -# define ADC4_EXTSEL_VALUE ADC4_EXTSEL_T7TRGO -# else -# error "CONFIG_STM32_ADC4_TIMTRIG is out of range" -# endif -#elif defined(CONFIG_STM32_TIM8_ADC4) -# if CONFIG_STM32_ADC4_TIMTRIG == 0 -# define ADC4_EXTSEL_VALUE ADC4_EXTSEL_T8CC1 -# elif CONFIG_STM32_ADC4_TIMTRIG == 1 -# define ADC4_EXTSEL_VALUE ADC4_EXTSEL_T8CC2 -# elif CONFIG_STM32_ADC4_TIMTRIG == 2 -# define ADC4_EXTSEL_VALUE ADC4_EXTSEL_T8CC3 -# elif CONFIG_STM32_ADC4_TIMTRIG == 3 -# define ADC4_EXTSEL_VALUE ADC4_EXTSEL_T8CC4 -# elif CONFIG_STM32_ADC4_TIMTRIG == 4 -# define ADC4_EXTSEL_VALUE ADC4_EXTSEL_T8TRGO -# elif CONFIG_STM32_ADC4_TIMTRIG == 5 -# define ADC4_EXTSEL_VALUE ADC4_EXTSEL_T8TRGO2 -# else -# error "CONFIG_STM32_ADC4_TIMTRIG is out of range" -# endif -#elif defined(CONFIG_STM32_TIM15_ADC4) -# if CONFIG_STM32_ADC4_TIMTRIG == 0 -# define ADC4_EXTSEL_VALUE ADC4_EXTSEL_T15CC1 -# elif CONFIG_STM32_ADC4_TIMTRIG == 1 -# define ADC4_EXTSEL_VALUE ADC4_EXTSEL_T15CC2 -# elif CONFIG_STM32_ADC4_TIMTRIG == 2 -# define ADC4_EXTSEL_VALUE ADC4_EXTSEL_T15CC3 -# elif CONFIG_STM32_ADC4_TIMTRIG == 3 -# define ADC4_EXTSEL_VALUE ADC4_EXTSEL_T15CC4 -# elif CONFIG_STM32_ADC4_TIMTRIG == 4 -# define ADC4_EXTSEL_VALUE ADC4_EXTSEL_T15TRGO -# else -# error "CONFIG_STM32_ADC4_TIMTRIG is out of range" -# endif -#elif defined(CONFIG_STM32_TIM20_ADC4) -# if CONFIG_STM32_ADC4_TIMTRIG == 0 -# define ADC4_EXTSEL_VALUE ADC4_EXTSEL_T20CC1 -# elif CONFIG_STM32_ADC4_TIMTRIG == 1 -# define ADC4_EXTSEL_VALUE ADC4_EXTSEL_T20CC2 -# elif CONFIG_STM32_ADC4_TIMTRIG == 2 -# define ADC4_EXTSEL_VALUE ADC4_EXTSEL_T20CC3 -# elif CONFIG_STM32_ADC4_TIMTRIG == 3 -# define ADC4_EXTSEL_VALUE ADC4_EXTSEL_T20CC4 -# elif CONFIG_STM32_ADC4_TIMTRIG == 4 -# define ADC4_EXTSEL_VALUE ADC4_EXTSEL_T20TRGO -# else -# error "CONFIG_STM32_ADC4_TIMTRIG is out of range" -# endif -#endif - -/* Regular channels external trigger support */ - -#ifdef ADC1_EXTSEL_VALUE -# define ADC1_HAVE_EXTCFG 1 -# define ADC1_EXTCFG_VALUE (ADC1_EXTSEL_VALUE | ADC_EXTREG_EXTEN_DEFAULT) -#elif defined(CONFIG_STM32_ADC1_EXTSEL) -# define ADC1_HAVE_EXTCFG 1 -# define ADC1_EXTCFG_VALUE 0 -#else -# undef ADC1_HAVE_EXTCFG -#endif -#ifdef ADC2_EXTSEL_VALUE -# define ADC2_HAVE_EXTCFG 1 -# define ADC2_EXTCFG_VALUE (ADC2_EXTSEL_VALUE | ADC_EXTREG_EXTEN_DEFAULT) -#elif defined(CONFIG_STM32_ADC2_EXTSEL) -# define ADC2_HAVE_EXTCFG 1 -# define ADC2_EXTCFG_VALUE 0 -#else -# undef ADC2_HAVE_EXTCFG -#endif -#ifdef ADC3_EXTSEL_VALUE -# define ADC3_HAVE_EXTCFG 1 -# define ADC3_EXTCFG_VALUE (ADC3_EXTSEL_VALUE | ADC_EXTREG_EXTEN_DEFAULT) -#elif defined(CONFIG_STM32_ADC3_EXTSEL) -# define ADC3_HAVE_EXTCFG 1 -# define ADC3_EXTCFG_VALUE 0 -#else -# undef ADC3_HAVE_EXTCFG -#endif -#ifdef ADC4_EXTSEL_VALUE -# define ADC4_HAVE_EXTCFG 1 -# define ADC4_EXTCFG_VALUE (ADC4_EXTSEL_VALUE | ADC_EXTREG_EXTEN_DEFAULT) -#elif defined(CONFIG_STM32_ADC4_EXTSEL) -# define ADC4_HAVE_EXTCFG 1 -# define ADC4_EXTCFG_VALUE 0 -#else -# undef ADC4_HAVE_EXTCFG -#endif - -#if defined(ADC1_HAVE_EXTCFG) || defined(ADC2_HAVE_EXTCFG) || \ - defined(ADC3_HAVE_EXTCFG) || defined(ADC3_HAVE_EXTCFG) -# define ADC_HAVE_EXTCFG -#endif - -/* JEXTSEL configuration ****************************************************/ - -/* There is no automatic timer tirgger configuration from Kconfig for - * injected channels conversion. - */ - -/* ADC1 HRTIM JEXTSEL trigger */ - -#if defined(CONFIG_STM32_HRTIM_ADC1_TRG2) -# define ADC1_JEXTSEL_VALUE ADC1_JEXTSEL_HRTTRG2 -#elif defined(CONFIG_STM32_HRTIM_ADC1_TRG4) -# define ADC1_JEXTSEL_VALUE ADC1_JEXTSEL_HRTTRG4 -#endif - -/* ADC1 HRTIM JEXTSEL trigger */ - -#if defined(CONFIG_STM32_HRTIM_ADC2_TRG2) -# define ADC2_JEXTSEL_VALUE ADC2_JEXTSEL_HRTTRG2 -#elif defined(CONFIG_STM32_HRTIM_ADC2_TRG4) -# define ADC2_JEXTSEL_VALUE ADC2_JEXTSEL_HRTTRG4 -#endif - -/* Injected channels external trigger support */ - -#ifdef ADC1_JEXTSEL_VALUE -# define ADC1_HAVE_JEXTCFG 1 -# define ADC1_JEXTCFG_VALUE (ADC1_JEXTSEL_VALUE | ADC_JEXTREG_JEXTEN_DEFAULT) -#elif defined(CONFIG_STM32_ADC1_JEXTSEL) -# define ADC1_HAVE_JEXTCFG 1 -# define ADC1_JEXTCFG_VALUE 0 -#else -# undef ADC1_HAVE_JEXTCFG -#endif -#ifdef ADC2_JEXTSEL_VALUE -# define ADC2_HAVE_JEXTCFG 1 -# define ADC2_JEXTCFG_VALUE (ADC2_JEXTSEL_VALUE | ADC_JEXTREG_JEXTEN_DEFAULT) -#elif defined(CONFIG_STM32_ADC2_JEXTSEL) -# define ADC2_HAVE_JEXTCFG 1 -# define ADC2_JEXTCFG_VALUE 0 -#else -# undef ADC2_HAVE_JEXTCFG -#endif -#ifdef ADC3_JEXTSEL_VALUE -# define ADC3_HAVE_JEXTCFG 1 -# define ADC3_JEXTCFG_VALUE (ADC3_JEXTSEL_VALUE | ADC_JEXTREG_JEXTEN_DEFAULT) -#elif defined(CONFIG_STM32_ADC3_JEXTSEL) -# define ADC3_HAVE_JEXTCFG 1 -# define ADC3_JEXTCFG_VALUE 0 -#else -# undef ADC3_HAVE_JEXTCFG -#endif -#ifdef ADC4_JEXTSEL_VALUE -# define ADC4_HAVE_JEXTCFG 1 -# define ADC4_JEXTCFG_VALUE (ADC4_JEXTSEL_VALUE | ADC_JEXTREG_JEXTEN_DEFAULT) -#elif defined(CONFIG_STM32_ADC4_JEXTSEL) -# define ADC4_HAVE_JEXTCFG 1 -# define ADC4_JEXTCFG_VALUE 0 -#else -# undef ADC4_HAVE_JEXTCFG -#endif - -#if defined(ADC1_HAVE_JEXTCFG) || defined(ADC2_HAVE_JEXTCFG) || \ - defined(ADC3_HAVE_JEXTCFG) || defined(ADC4_HAVE_JEXTCFG) -# define ADC_HAVE_JEXTCFG -#endif - -/* ADC interrupts ***********************************************************/ - -#if defined(HAVE_IP_ADC_V1) -# define ADC_ISR_EOC ADC_SR_EOC -# define ADC_IER_EOC ADC_CR1_EOCIE -# define ADC_ISR_AWD ADC_SR_AWD -# define ADC_IER_AWD ADC_CR1_AWDIE -# define ADC_ISR_JEOC ADC_SR_JEOC -# define ADC_IER_JEOC ADC_CR1_JEOCIE -# define ADC_ISR_JEOS 0 /* No JEOS */ -# define ADC_IER_JEOS 0 /* No JEOS */ -# ifdef HAVE_BASIC_ADC -# define ADC_ISR_OVR 0 -# define ADC_IER_OVR 0 -# else -# define ADC_ISR_OVR ADC_SR_OVR -# define ADC_IER_OVR ADC_CR1_OVRIE -# endif -#elif defined(HAVE_IP_ADC_V2) -# define ADC_ISR_EOC ADC_INT_EOC -# define ADC_IER_EOC ADC_INT_EOC -# define ADC_ISR_AWD ADC_INT_AWD1 -# define ADC_IER_AWD ADC_INT_AWD1 -# define ADC_ISR_JEOC ADC_INT_JEOC -# define ADC_IER_JEOC ADC_INT_JEOC -# define ADC_ISR_OVR ADC_INT_OVR -# define ADC_IER_OVR ADC_INT_OVR -# define ADC_ISR_JEOS ADC_INT_JEOS -# define ADC_IER_JEOS ADC_INT_JEOS -#endif - -#define ADC_ISR_ALLINTS (ADC_ISR_EOC | ADC_ISR_AWD | ADC_ISR_JEOC | \ - ADC_ISR_JEOS | ADC_ISR_OVR) -#define ADC_IER_ALLINTS (ADC_IER_EOC | ADC_IER_AWD | ADC_IER_JEOC | \ - ADC_IER_JEOS | ADC_IER_OVR) - -/* Low-level ops helpers ****************************************************/ - -#define STM32_ADC_INT_ACK(adc, source) \ - (adc)->llops->int_ack(adc, source) -#define STM32_ADC_INT_GET(adc) \ - (adc)->llops->int_get(adc) -#define STM32_ADC_INT_ENABLE(adc, source) \ - (adc)->llops->int_en(adc, source) -#define STM32_ADC_INT_DISABLE(adc, source) \ - (adc)->llops->int_dis(adc, source) -#define STM32_ADC_REGDATA_GET(adc) \ - (adc)->llops->val_get(adc) -#define STM32_ADC_REGBUF_REGISTER(adc, buffer, len) \ - (adc)->llops->regbuf_reg(adc, buffer, len) -#define STM32_ADC_REG_STARTCONV(adc, state) \ - (adc)->llops->reg_startconv(adc, state) -#define STM32_ADC_OFFSET_SET(adc, ch, i, o) \ - (adc)->llops->offset_set(adc, ch, i, o) -#define STM32_ADC_EXTCFG_SET(adc, c) \ - (adc)->llops->extcfg_set(adc, c) -#define STM32_ADC_INJ_STARTCONV(adc, state) \ - (adc)->llops->inj_startconv(adc, state) -#define STM32_ADC_INJDATA_GET(adc, chan) \ - (adc)->llops->inj_get(adc, chan) -#define STM32_ADC_JEXTCFG_SET(adc, c) \ - (adc)->llops->jextcfg_set(adc, c) -#define STM32_ADC_SAMPLETIME_SET(adc, time_samples) \ - (adc)->llops->stime_set(adc, time_samples) -#define STM32_ADC_SAMPLETIME_WRITE(adc) \ - (adc)->llops->stime_write(adc) -#define STM32_ADC_DUMP_REGS(adc) \ - (adc)->llops->dump_regs(adc) -#define STM32_ADC_SETUP(adc) \ - (adc)->llops->setup(adc) -#define STM32_ADC_SHUTDOWN(adc) \ - (adc)->llops->shutdown(adc) -#define STM32_ADC_MULTICFG(adc, mode) \ - (adc)->llops->multi_cfg(adc, mode) -#define STM32_ADC_ENABLE(adc, en) \ - (adc)->llops->enable(adc, en) - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -/* On STM32F42xx and STM32F43xx devices,VBAT and temperature sensor are - * connected to the same ADC internal channel (ADC1_IN18). - * Only one conversion, either temperature sensor or VBAT, must be selected - * at a time. When both conversion are enabled simultaneously, - * only the VBAT conversion is performed. - */ - -enum adc_io_cmds_e -{ -#if defined(HAVE_IP_ADC_V1) - IO_ENABLE_TEMPER_VOLT_CH, -#endif -#ifdef HAVE_ADC_VBAT - IO_ENABLE_DISABLE_VBAT_CH, -#endif - IO_ENABLE_DISABLE_AWDIE, - IO_ENABLE_DISABLE_EOCIE, - IO_ENABLE_DISABLE_JEOCIE, - IO_ENABLE_DISABLE_OVRIE, - IO_ENABLE_DISABLE_ALL_INTS, - IO_STOP_ADC, - IO_START_ADC, - IO_START_CONV, - IO_TRIGGER_REG, -#ifdef ADC_HAVE_INJECTED - IO_TRIGGER_INJ, -#endif -#ifdef HAVE_ADC_POWERDOWN - IO_ENABLE_DISABLE_PDI, - IO_ENABLE_DISABLE_PDD, - IO_ENABLE_DISABLE_PDD_PDI -#endif -}; - -/* ADC resolution can be reduced in order to perform faster conversion */ - -enum stm32_adc_resoluton_e -{ - ADC_RESOLUTION_12BIT = 0, /* 12 bit */ - ADC_RESOLUTION_10BIT = 1, /* 10 bit */ - ADC_RESOLUTION_8BIT = 2, /* 8 bit */ - ADC_RESOLUTION_6BIT = 3 /* 6 bit */ -}; - -/* ADC multi mode selection */ - -enum stm32_adc_multimode_e -{ - /* Independent mode */ - - ADC_MULTIMODE_INDEP = 0, /* Independent mode */ - - /* Dual mode */ - - ADC_MULTIMODE_RSISM2 = 1, /* Dual combined regular sim. + injected sim. */ - ADC_MULTIMODE_RSATM2 = 2, /* Dual combined regular sim. + alternate trigger */ - ADC_MULTIMODE_IMIS2 = 3, /* Dual combined interl. mode + injected sim. */ - ADC_MULTIMODE_ISM2 = 4, /* Dual injected simultaneous mode only */ - ADC_MULTIMODE_RSM2 = 5, /* Dual degular simultaneous mode only */ - ADC_MULTIMODE_IM2 = 6, /* Dual interleaved mode only */ - ADC_MULTIMODE_ATM2 = 7, /* Dual alternate trigger mode only */ - - /* Triple mode */ - - ADC_MULTIMODE_RSISM3 = 8, /* Triple combined regular sim. + injected sim. */ - ADC_MULTIMODE_RSATM3 = 9, /* Triple combined regular sim. + alternate trigger */ - ADC_MULTIMODE_IMIS3 = 10, /* Triple combined interl. mode + injected sim. */ - ADC_MULTIMODE_ISM3 = 11, /* Triple injected simultaneous mode only */ - ADC_MULTIMODE_RSM3 = 12, /* Triple degular simultaneous mode only */ - ADC_MULTIMODE_IM3 = 13, /* Triple interleaved mode only */ - ADC_MULTIMODE_ATM3 = 14, /* Triple alternate trigger mode only */ -}; - -#ifdef CONFIG_STM32_ADC_LL_OPS - -#ifdef CONFIG_STM32_ADC_CHANGE_SAMPLETIME - -/* Channel and sample time pair */ - -typedef struct adc_channel_s -{ - uint8_t channel:5; - - /* Sampling time individually for each channel. - * It differs between families - */ - - uint8_t sample_time:3; -} adc_channel_t; - -/* This structure will be used while setting channels to specified by the - * "channel-sample time" pairs' values - */ - -struct adc_sample_time_s -{ - adc_channel_t *channel; /* Array of channels */ - uint8_t channels_nbr:5; /* Number of channels in array */ - bool all_same:1; /* All channels will get the - * same value of the sample time */ - uint8_t all_ch_sample_time:3; /* Sample time for all channels */ -}; -#endif /* CONFIG_STM32_ADC_CHANGE_SAMPLETIME */ - -/* This structure provides the publicly visible representation of the - * "lower-half" ADC driver structure. - */ - -struct stm32_adc_dev_s -{ - /* Publicly visible portion of the "lower-half" ADC driver structure */ - - const struct stm32_adc_ops_s *llops; - - /* Require cast-compatibility with private "lower-half" ADC structure */ -}; - -/* Low-level operations for ADC */ - -struct stm32_adc_ops_s -{ - /* Low-level ADC setup */ - - int (*setup)(struct stm32_adc_dev_s *dev); - - /* Low-level ADC shutdown */ - - void (*shutdown)(struct stm32_adc_dev_s *dev); - - /* Acknowledge interrupts */ - - void (*int_ack)(struct stm32_adc_dev_s *dev, uint32_t source); - - /* Get pending interrupts */ - - uint32_t (*int_get)(struct stm32_adc_dev_s *dev); - - /* Enable interrupts */ - - void (*int_en)(struct stm32_adc_dev_s *dev, uint32_t source); - - /* Disable interrupts */ - - void (*int_dis)(struct stm32_adc_dev_s *dev, uint32_t source); - - /* Get current ADC data register */ - - uint32_t (*val_get)(struct stm32_adc_dev_s *dev); - - /* Register buffer for ADC DMA transfer */ - - int (*regbuf_reg)(struct stm32_adc_dev_s *dev, - uint16_t *buffer, uint8_t len); - - /* Start/stop regular conversion */ - - void (*reg_startconv)(struct stm32_adc_dev_s *dev, bool state); - - /* Set offset for channel */ - - int (*offset_set)(struct stm32_adc_dev_s *dev, uint8_t ch, uint8_t i, - uint16_t offset); - -#ifdef ADC_HAVE_EXTCFG - /* Configure the ADC external trigger for regular conversion */ - - void (*extcfg_set)(struct stm32_adc_dev_s *dev, uint32_t extcfg); -#endif - -#ifdef ADC_HAVE_JEXTCFG - /* Configure the ADC external trigger for injected conversion */ - - void (*jextcfg_set)(struct stm32_adc_dev_s *dev, uint32_t jextcfg); -#endif - -#ifdef ADC_HAVE_INJECTED - /* Get current ADC injected data register */ - - uint32_t (*inj_get)(struct stm32_adc_dev_s *dev, uint8_t chan); - - /* Start/stop injected conversion */ - - void (*inj_startconv)(struct stm32_adc_dev_s *dev, bool state); -#endif - -#ifdef CONFIG_STM32_ADC_CHANGE_SAMPLETIME - /* Set ADC sample time */ - - void (*stime_set)(struct stm32_adc_dev_s *dev, - struct adc_sample_time_s *time_samples); - - /* Write ADC sample time */ - - void (*stime_write)(struct stm32_adc_dev_s *dev); -#endif - - void (*dump_regs)(struct stm32_adc_dev_s *dev); - - /* Configure ADC multi mode */ - - int (*multi_cfg)(struct stm32_adc_dev_s *dev, uint8_t mode); - - /* Enable/disable ADC */ - - void (*enable)(struct stm32_adc_dev_s *dev, bool enable); -}; - -#endif /* CONFIG_STM32_ADC_LL_OPS */ - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -#ifndef __ASSEMBLY__ -#ifdef __cplusplus -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Name: stm32_adcinitialize - * - * Description: - * Initialize the ADC. See stm32_adc.c for more details. - * - * Input Parameters: - * intf - Could be {1,2,3,4} for ADC1, ADC2, ADC3 or ADC4 - * chanlist - The list of channels (regular + injected) - * nchannels - Number of channels (regular + injected) - * - * Returned Value: - * Valid ADC device structure reference on success; a NULL on failure - * - ****************************************************************************/ - -struct adc_dev_s; -struct adc_dev_s *stm32_adcinitialize(int intf, const uint8_t *chanlist, - int channels); - -#undef EXTERN -#ifdef __cplusplus -} -#endif -#endif /* __ASSEMBLY__ */ - -#endif /* CONFIG_STM32_ADC1 || CONFIG_STM32_ADC2 || - * CONFIG_STM32_ADC3 || CONFIG_STM32_ADC4 - */ -#endif /* __ARCH_ARM_SRC_STM32_STM32_ADC_H */ diff --git a/arch/arm/src/stm32/stm32_aes.c b/arch/arm/src/stm32/stm32_aes.c deleted file mode 100644 index ae58ed82c1771..0000000000000 --- a/arch/arm/src/stm32/stm32_aes.c +++ /dev/null @@ -1,322 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_aes.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include - -#include "arm_internal.h" -#include "chip.h" -#include "stm32_rcc.h" -#include "stm32_aes.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#define AES_BLOCK_SIZE 16 - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -static void stm32aes_enable(bool on); -static void stm32aes_ccfc(void); -static void stm32aes_setkey(const void *key, size_t key_len); -static void stm32aes_setiv(const void *iv); -static void stm32aes_encryptblock(void *block_out, - const void *block_in); -static int stm32aes_setup_cr(int mode, int encrypt); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -static mutex_t g_stm32aes_lock = NXMUTEX_INITIALIZER; -static bool g_stm32aes_initdone = false; - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -static void stm32aes_enable(bool on) -{ - uint32_t regval; - - regval = getreg32(STM32_AES_CR); - if (on) - { - regval |= AES_CR_EN; - } - else - { - regval &= ~AES_CR_EN; - } - - putreg32(regval, STM32_AES_CR); -} - -/* Clear AES_SR_CCF status register bit */ - -static void stm32aes_ccfc(void) -{ - uint32_t regval; - - regval = getreg32(STM32_AES_CR); - regval |= AES_CR_CCFC; - putreg32(regval, STM32_AES_CR); -} - -/* TODO: Handle other AES key lengths or fail if length is not valid */ - -static void stm32aes_setkey(const void *key, size_t key_len) -{ - uint32_t *in = (uint32_t *)key; - - putreg32(__builtin_bswap32(*in), STM32_AES_KEYR3); - in++; - putreg32(__builtin_bswap32(*in), STM32_AES_KEYR2); - in++; - putreg32(__builtin_bswap32(*in), STM32_AES_KEYR1); - in++; - putreg32(__builtin_bswap32(*in), STM32_AES_KEYR0); -} - -static void stm32aes_setiv(const void *iv) -{ - uint32_t *in = (uint32_t *)iv; - - putreg32(__builtin_bswap32(*in), STM32_AES_IVR3); - in++; - putreg32(__builtin_bswap32(*in), STM32_AES_IVR2); - in++; - putreg32(__builtin_bswap32(*in), STM32_AES_IVR1); - in++; - putreg32(__builtin_bswap32(*in), STM32_AES_IVR0); -} - -static void stm32aes_encryptblock(void *block_out, - const void *block_in) -{ - uint32_t *in = (uint32_t *)block_in; - uint32_t *out = (uint32_t *)block_out; - - putreg32(*in, STM32_AES_DINR); - in++; - putreg32(*in, STM32_AES_DINR); - in++; - putreg32(*in, STM32_AES_DINR); - in++; - putreg32(*in, STM32_AES_DINR); - - while (!(getreg32(STM32_AES_SR) & AES_SR_CCF)); - stm32aes_ccfc(); - - *out = getreg32(STM32_AES_DOUTR); - out++; - *out = getreg32(STM32_AES_DOUTR); - out++; - *out = getreg32(STM32_AES_DOUTR); - out++; - *out = getreg32(STM32_AES_DOUTR); -} - -static int stm32aes_setup_cr(int mode, int encrypt) -{ - uint32_t regval = 0; - - regval |= AES_CR_DATATYPE_BE; - - switch (mode) - { - case AES_MODE_ECB: - regval |= AES_CR_CHMOD_ECB; - break; - - case AES_MODE_CBC: - regval |= AES_CR_CHMOD_CBC; - break; - - case AES_MODE_CTR: - regval |= AES_CR_CHMOD_CTR; - break; - - default: - return -EINVAL; - } - - if (encrypt) - { - regval |= AES_CR_MODE_ENCRYPT; - } - else - { - if (mode == AES_MODE_CTR) - { - regval |= AES_CR_MODE_DECRYPT; - } - else - { - regval |= AES_CR_MODE_DECRYPT_KEYDERIV; - } - } - - putreg32(regval, STM32_AES_CR); - return OK; -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -int stm32_aesreset(void) -{ - irqstate_t flags; - uint32_t regval; - - flags = enter_critical_section(); - - regval = getreg32(STM32_RCC_AHBRSTR); - regval |= RCC_AHBRSTR_AESRST; - putreg32(regval, STM32_RCC_AHBRSTR); - regval &= ~RCC_AHBRSTR_AESRST; - putreg32(regval, STM32_RCC_AHBRSTR); - - leave_critical_section(flags); - - return OK; -} - -int stm32_aesinitialize(void) -{ - uint32_t regval; - - regval = getreg32(STM32_RCC_AHBENR); - regval |= RCC_AHBENR_AESEN; - putreg32(regval, STM32_RCC_AHBENR); - - stm32aes_enable(false); - - return OK; -} - -int stm32_aesuninitialize(void) -{ - uint32_t regval; - - stm32aes_enable(false); - - regval = getreg32(STM32_RCC_AHBENR); - regval &= ~RCC_AHBENR_AESEN; - putreg32(regval, STM32_RCC_AHBENR); - - return OK; -} - -int aes_cypher(void *out, const void *in, size_t size, - const void *iv, const void *key, size_t keysize, - int mode, int encrypt) -{ - int ret = OK; - - /* Ensure initialization was done */ - - if (!g_stm32aes_initdone) - { - ret = stm32_aesinitialize(); - if (ret < 0) - { - return ret; /* AES init failed */ - } - - g_stm32aes_initdone = true; - } - - if ((size & (AES_BLOCK_SIZE - 1)) != 0) - { - return -EINVAL; - } - - if (keysize != 16) - { - return -EINVAL; - } - - ret = nxmutex_lock(&g_stm32aes_lock); - if (ret < 0) - { - return ret; - } - - /* AES must be disabled before changing mode, key or IV. */ - - stm32aes_enable(false); - ret = stm32aes_setup_cr(mode, encrypt); - if (ret < 0) - { - goto out; - } - - stm32aes_setkey(key, keysize); - if (iv != NULL) - { - stm32aes_setiv(iv); - } - - stm32aes_enable(true); - while (size) - { - stm32aes_encryptblock(out, in); - out = (uint8_t *)out + AES_BLOCK_SIZE; - in = (uint8_t *)in + AES_BLOCK_SIZE; - size -= AES_BLOCK_SIZE; - } - - stm32aes_enable(false); - -out: - nxmutex_unlock(&g_stm32aes_lock); - return ret; -} diff --git a/arch/arm/src/stm32/stm32_aes.h b/arch/arm/src/stm32/stm32_aes.h deleted file mode 100644 index f0de4f5972071..0000000000000 --- a/arch/arm/src/stm32/stm32_aes.h +++ /dev/null @@ -1,58 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_aes.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32_STM32_AES_H -#define __ARCH_ARM_SRC_STM32_STM32_AES_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include "chip.h" - -/* Only the STM32L162 devices have AES, but we don't bother with exact macros - * for simplicity. - */ - -#ifdef CONFIG_STM32_STM32L15XX -# include "hardware/stm32l15xxx_aes.h" -#else -# error "Unknown chip for AES" -#endif - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -/**************************************************************************** - * Inline Functions - ****************************************************************************/ - -#endif /* __ARCH_ARM_SRC_STM32_STM32_AES_H */ diff --git a/arch/arm/src/stm32/stm32_allocateheap.c b/arch/arm/src/stm32/stm32_allocateheap.c deleted file mode 100644 index 69d5a18bb7b04..0000000000000 --- a/arch/arm/src/stm32/stm32_allocateheap.c +++ /dev/null @@ -1,803 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_allocateheap.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -#include - -#include "chip.h" - -#include "mpu.h" -#include "arm_internal.h" -#include "stm32_mpuinit.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Internal SRAM is available in all members of the STM32 family. The - * following definitions must be provided to specify the size and - * location of internal(system) SRAM: - * - * CONFIG_RAM_END : End address (+1) of SRAM (F1 family only, the - * : F4 family uses the a priori end of SRAM) - * - * The F4 family also contains internal CCM SRAM. This SRAM is different - * because it cannot be used for DMA. So if DMA needed, then the following - * should be defined to exclude CCM SRAM from the heap: - * - * CONFIG_STM32_CCMEXCLUDE : Exclude CCM SRAM from the HEAP - * - * In addition to internal SRAM, external RAM may also be available through - * the FMC/FSMC. To use external RAM, the following things need to be present - * in the NuttX configuration file: - * - * CONFIG_STM32_FSMC=y : Enables the FSMC - * CONFIG_STM32_FMC=y : Enables the FMC - * CONFIG_STM32_EXTERNAL_RAM=y : Indicates external RAM is available via the - * FMC/FSMC (as opposed to an LCD or FLASH). - * CONFIG_HEAP2_BASE : The base address of the external RAM - * CONFIG_HEAP2_SIZE : The size of the external RAM - * CONFIG_MM_REGIONS : Must be set to a large enough value to - * include the external RAM (as determined by - * the rules provided below) - */ - -#if !defined(CONFIG_STM32_FSMC) && !defined(CONFIG_STM32_FMC) -# undef CONFIG_STM32_EXTERNAL_RAM -#endif - -/* The STM32L15xxx family has only internal SRAM. The heap is in one - * contiguous block starting at g_idle_topstack and extending through - * CONFIG_RAM_END. - */ - -#if defined(CONFIG_STM32_STM32L15XX) - -/* Set the end of system SRAM */ - -# define SRAM1_END CONFIG_RAM_END - -/* There is no FSMC (Other EnergyLite STM32's do have an FSMC, but not - * the STM32L15X - */ - -# undef CONFIG_STM32_EXTERNAL_RAM - -/* The STM32L EnergyLite family has no CCM SRAM */ - -# undef CONFIG_STM32_CCMEXCLUDE -# define CONFIG_STM32_CCMEXCLUDE 1 - -/* Only one memory region can be support (internal SRAM) */ - -# if CONFIG_MM_REGIONS > 1 -# error "CONFIG_MM_REGIONS > 1. The STM32L15X has only one memory region." -# endif - -/* For the STM312F10xxx family, all internal SRAM is in one contiguous - * block starting at g_idle_topstack and extending through CONFIG_RAM_END - * (my apologies for the bad naming). In addition, external FSMC SRAM - * may be available. - */ - -#elif defined(CONFIG_STM32_STM32F10XX) - -/* Set the end of system SRAM */ - -# define SRAM1_END CONFIG_RAM_END - -/* Check if external FSMC SRAM is provided */ - -# ifdef CONFIG_STM32_EXTERNAL_RAM -# if CONFIG_MM_REGIONS < 2 -# warning "FSMC SRAM not included in the heap" -# undef CONFIG_STM32_EXTERNAL_RAM -# elif CONFIG_MM_REGIONS > 2 -# error "CONFIG_MM_REGIONS > 2 but I don't know what some of the region(s) are" -# undef CONFIG_MM_REGIONS -# define CONFIG_MM_REGIONS 2 -# endif -# elif CONFIG_MM_REGIONS > 1 -# error "CONFIG_MM_REGIONS > 1 but I don't know what the other region(s) are" -# endif - -/* The STM32 F1 has no CCM SRAM */ - -# undef CONFIG_STM32_CCMEXCLUDE -# define CONFIG_STM32_CCMEXCLUDE 1 - -/* Members of the STM32F30xxx family has a variable amount of SRAM from 24 - * to 40Kb plus 8KB if CCM SRAM. No external RAM is supported (the F3 family - * has no FSMC). - * - * As a complication, CCM SRAM cannot be used for DMA. So, if STM32 DMA is - * enabled, CCM SRAM should probably be excluded from the heap. - */ - -#elif defined(CONFIG_STM32_STM32F30XX) - -/* Set the end of system SRAM */ - -# define SRAM1_END CONFIG_RAM_END - -/* Set the range of CCM SRAM as well (although we may not use it) */ - -# define SRAM2_START 0x10000000 -# define SRAM2_END 0x10002000 - -/* There is no FSMC */ - -# undef CONFIG_STM32_EXTERNAL_RAM - -/* There are 2 possible SRAM configurations: - * - * Configuration 1. System SRAM (only) - * CONFIG_MM_REGIONS == 1 - * CONFIG_STM32_CCMEXCLUDE defined - * Configuration 2. System SRAM and CCM SRAM - * CONFIG_MM_REGIONS == 2 - * CONFIG_STM32_CCMEXCLUDE NOT defined - */ - -# if CONFIG_MM_REGIONS < 2 - -/* Only one memory region. Force Configuration 1 */ - -# ifndef CONFIG_STM32_CCMEXCLUDE -# ifdef CONFIG_STM32_HAVE_CCM -# warning "CCM SRAM excluded from the heap" -# endif -# define CONFIG_STM32_CCMEXCLUDE 1 -# endif - -/* CONFIG_MM_REGIONS may be 2 if CCM SRAM is included in the head */ - -# elif CONFIG_MM_REGIONS >= 2 -# if CONFIG_MM_REGIONS > 2 -# error "No more than two memory regions can be supported (CONFIG_MM_REGIONS)" -# undef CONFIG_MM_REGIONS -# define CONFIG_MM_REGIONS 2 -# endif - -/* Two memory regions is okay if CCM SRAM is not disabled. */ - -# ifdef CONFIG_STM32_CCMEXCLUDE - -/* Configuration 1: CONFIG_MM_REGIONS should have been 2 */ - -# error "CONFIG_MM_REGIONS >= 2 but but CCM SRAM is excluded (CONFIG_STM32_CCMEXCLUDE)" -# undef CONFIG_MM_REGIONS -# define CONFIG_MM_REGIONS 1 -# else - -/* Configuration 2: DMA should be disabled */ - -# ifdef CONFIG_ARCH_DMA -# warning "CCM SRAM is included in the heap AND DMA is enabled" -# endif -# endif -# endif - -/* All members of the STM32F33xxx families have 16 Kbi ram and 4 KB CCM SRAM. - * No external RAM is supported (the F3 family has no FSMC). - * - * As a complication, CCM SRAM cannot be used for DMA. So, if STM32 DMA is - * enabled, CCM SRAM should probably be excluded from the heap. - */ -#elif defined(CONFIG_STM32_STM32F33XX) - -/* Set the end of system SRAM */ - -# define SRAM1_END CONFIG_RAM_END - -/* Set the range of CCM SRAM as well (although we may not use it) */ - -# define SRAM2_START 0x10000000 -# define SRAM2_END 0x10001000 - -/* There is no FSMC */ - -# undef CONFIG_STM32_EXTERNAL_RAM - -/* There are 2 possible SRAM configurations: - * - * Configuration 1. System SRAM (only) - * CONFIG_MM_REGIONS == 1 - * CONFIG_STM32_CCMEXCLUDE defined - * Configuration 2. System SRAM and CCM SRAM - * CONFIG_MM_REGIONS == 2 - * CONFIG_STM32_CCMEXCLUDE NOT defined - */ - -# if CONFIG_MM_REGIONS < 2 - -/* Only one memory region. Force Configuration 1 */ - -# ifndef CONFIG_STM32_CCMEXCLUDE -# ifdef CONFIG_STM32_HAVE_CCM -# warning "CCM SRAM excluded from the heap" -# endif -# define CONFIG_STM32_CCMEXCLUDE 1 -# endif - -/* CONFIG_MM_REGIONS may be 2 if CCM SRAM is included in the head */ - -# elif CONFIG_MM_REGIONS >= 2 -# if CONFIG_MM_REGIONS > 2 -# error "No more than two memory regions can be supported (CONFIG_MM_REGIONS)" -# undef CONFIG_MM_REGIONS -# define CONFIG_MM_REGIONS 2 -# endif - -/* Two memory regions is okay if CCM SRAM is not disabled. */ - -# ifdef CONFIG_STM32_CCMEXCLUDE - -/* Configuration 1: CONFIG_MM_REGIONS should have been 2 */ - -# error "CONFIG_MM_REGIONS >= 2 but but CCM SRAM is excluded (CONFIG_STM32_CCMEXCLUDE)" -# undef CONFIG_MM_REGIONS -# define CONFIG_MM_REGIONS 1 -# else - -/* Configuration 2: DMA should be disabled */ - -# ifdef CONFIG_ARCH_DMA -# warning "CCM SRAM is included in the heap AND DMA is enabled" -# endif -# endif -# endif - -/* All members of the STM32F37xxx families have 16-32 Kib ram in a single - * bank. No external RAM is supported (the F3 family has no FSMC). - */ -#elif defined(CONFIG_STM32_STM32F37XX) - -/* Set the end of system SRAM */ - -# define SRAM1_END CONFIG_RAM_END - -/* There is no FSMC */ - -# undef CONFIG_STM32_EXTERNAL_RAM - -/* The STM32 F37xx has no CCM SRAM */ - -# undef CONFIG_STM32_CCMEXCLUDE -# define CONFIG_STM32_CCMEXCLUDE 1 - -/* Only one memory region can be support (internal SRAM) */ - -# if CONFIG_MM_REGIONS > 1 -# error "CONFIG_MM_REGIONS > 1. The STM32L15X has only one memory region." -# endif - -/* Most members of both the STM32F20xxx and STM32F40xxx families have 128Kib - * in two banks: - * - * 1) 112KiB of System SRAM beginning at address 0x2000:0000 - * 2) 16KiB of System SRAM beginning at address 0x2001:c000 - * - * The STM32F401 family is an exception and has only 64KiB or 96Kib total - * on one bank: - * - * 3) 64KiB (STM32F401xB/C) or 96KiB (STM32401xD/E) of System SRAM - * beginning at address 0x2000:0000 - * - * Members of the STM32F40xxx family have an additional 64Kib of CCM RAM - * for a total of 192KB. - * - * 4) 64Kib of CCM SRAM beginning at address 0x1000:0000 - * - * The STM32F427/437/429/439 parts have another 64KiB of System SRAM for - * a total of 256KiB. - * - * 5) 64Kib of System SRAM beginning at address 0x2002:0000 - * - * As determined by the linker script, g_heapbase lies in the 112KiB memory - * region and that extends to 0x2001:0000. But the first and second memory - * regions are contiguous and treated as one in this logic that extends to - * 0x2002:0000 (or 0x2003:0000 for the F427/F437/F429/F439). - * - * As a complication, CCM SRAM cannot be used for DMA. So, if STM32 DMA is - * enabled, CCM SRAM should probably be excluded from the heap or the - * application must take extra care to ensure that DMA buffers are not - * allocated in CCM SRAM. - * - * In addition, external FSMC SRAM may be available. - */ - -#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) - -/* The STM32 F2 and the STM32 F401/F411/F412 have no CCM SRAM */ - -# if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F401) || \ - defined(CONFIG_STM32_STM32F411) || defined(CONFIG_STM32_STM32F410) || \ - defined(CONFIG_STM32_STM32F412) -# undef CONFIG_STM32_CCMEXCLUDE -# define CONFIG_STM32_CCMEXCLUDE 1 -# endif - -/* Set the end of system SRAM */ - -# if defined(CONFIG_STM32_STM32F401xBC) -# define SRAM1_END 0x20010000 -# elif defined(CONFIG_STM32_STM32F401xDE) -# define SRAM1_END 0x20018000 -# elif defined(CONFIG_STM32_STM32F410) -# define SRAM1_END 0x20008000 -# elif defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429) -# define SRAM1_END 0x20030000 -# elif defined(CONFIG_STM32_STM32F446) -# define SRAM1_END 0x20020000 -# elif defined(CONFIG_STM32_STM32F469) -# define SRAM1_END 0x20050000 -# else -# define SRAM1_END 0x20020000 -# endif - -/* Set the range of CCM SRAM as well (although we may not use it) */ - -# define SRAM2_START 0x10000000 -# define SRAM2_END 0x10010000 - -/* There are 4 possible SRAM configurations: - * - * Configuration 1. System SRAM (only) - * CONFIG_MM_REGIONS == 1 - * CONFIG_STM32_EXTERNAL_RAM NOT defined - * CONFIG_STM32_CCMEXCLUDE defined - * Configuration 2. System SRAM and CCM SRAM - * CONFIG_MM_REGIONS == 2 - * CONFIG_STM32_EXTERNAL_RAM NOT defined - * CONFIG_STM32_CCMEXCLUDE NOT defined - * Configuration 3. System SRAM and FSMC SRAM - * CONFIG_MM_REGIONS == 2 - * CONFIG_STM32_EXTERNAL_RAM defined - * CONFIG_STM32_CCMEXCLUDE defined - * Configuration 4. System SRAM, CCM SRAM, and FSMC SRAM - * CONFIG_MM_REGIONS == 3 - * CONFIG_STM32_EXTERNAL_RAM defined - * CONFIG_STM32_CCMEXCLUDE NOT defined - * - * Let's make sure that all definitions are consistent before doing - * anything else - */ - -# if defined(CONFIG_STM32_EXTERNAL_RAM) - -/* Configuration 3 or 4. External SRAM is available. CONFIG_MM_REGIONS - * should be at least 2. - */ - -# if CONFIG_MM_REGIONS < 2 - -/* Only one memory region. Force Configuration 1 */ - -# warning "FSMC SRAM (and CCM SRAM) excluded from the heap" -# undef CONFIG_STM32_EXTERNAL_RAM -# undef CONFIG_STM32_CCMEXCLUDE -# define CONFIG_STM32_CCMEXCLUDE 1 - -/* CONFIG_MM_REGIONS may be 3 if CCM SRAM is included in the head */ - -# elif CONFIG_MM_REGIONS > 2 - -/* More than two memory regions. This is okay if CCM SRAM is not - * disabled. - */ - -# if defined(CONFIG_STM32_CCMEXCLUDE) - -/* Configuration 3: CONFIG_MM_REGIONS should have been 2 */ - -# error "CONFIG_MM_REGIONS > 2 but I don't know what some of the region(s) are" -# undef CONFIG_MM_REGIONS -# define CONFIG_MM_REGIONS 2 -# else - -/* Configuration 4: DMA should be disabled and CONFIG_MM_REGIONS - * should be 3. - */ - -# ifdef CONFIG_ARCH_DMA -# warning "CCM SRAM is included in the heap AND DMA is enabled" -# endif - -# if CONFIG_MM_REGIONS != 3 -# error "CONFIG_MM_REGIONS > 3 but I don't know what some of the region(s) are" -# undef CONFIG_MM_REGIONS -# define CONFIG_MM_REGIONS 3 -# endif -# endif - -/* CONFIG_MM_REGIONS is exactly 2. We cannot support both CCM SRAM and - * FSMC SRAM. - */ - -# elif !defined(CONFIG_STM32_CCMEXCLUDE) -# error "CONFIG_MM_REGIONS == 2, cannot support both CCM SRAM and FSMC SRAM" -# undef CONFIG_STM32_CCMEXCLUDE -# define CONFIG_STM32_CCMEXCLUDE 1 -# endif - -# elif !defined(CONFIG_STM32_CCMEXCLUDE) - -/* Configuration 2: FSMC SRAM is not used, but CCM SRAM is requested. - * DMA should be disabled and CONFIG_MM_REGIONS should be 2. - */ - -# ifdef CONFIG_ARCH_DMA -# warning "CCM SRAM is included in the heap AND DMA is enabled" -# endif - -# if CONFIG_MM_REGIONS < 2 -# ifdef CONFIG_STM32_HAVE_CCM -# warning "CCM SRAM excluded from the heap because CONFIG_MM_REGIONS < 2" -# endif -# undef CONFIG_STM32_CCMEXCLUDE -# define CONFIG_STM32_CCMEXCLUDE 1 -# elif CONFIG_MM_REGIONS > 2 -# error "CONFIG_MM_REGIONS > 2 but I don't know what some of the region(s) are" -# undef CONFIG_MM_REGIONS -# define CONFIG_MM_REGIONS 2 -# endif -# endif - -/* STM32G47xxx family P/Ns have 96KiB of internal RAM in 2 banks, plus 32 KiB - * of CCM SRAM (Routine Booster), and the possibility of external RAM via - * FSMC: - * - * All internal RAM is contiguous from address 0x2000:0000 thru 0x2001:FFFF, - * but consists of these separate regions: - * - * SRAM: - * - * 1) 80 KiB SRAM1 mapped at 0x2000:0000 thru 0x2001:3FFF. - * 2) 16 KiB SRAM2 mapped at 0x2001:4000 thru 0x2001:7FFF. - * - * CCM SRAM: - * - * 3) 32 KiB CCM SRAM mapped at 0x1000:0000 thru 0x1000:7FFF - * but also aliased at at 0x2001:8000 thru 0x2001:FFFF to be contiguous - * with the SRAM1 and SRAM2. - * - * Because SRAM1 and SRAM2 are contiguous, they are treated as one region - * by this logic. - * - * REVISIT: I believe that unlike other parts mentioned in this file, the - * CCM SRAM *is* accessible to DMA. See Reference Manual (RM0440 Rev 2) - * section 2.1.3, DMA-Bus: "This bus connects the AHB master interface of - * the DMA to the BusMatrix. The targets of this bus are the SRAM1, SRAM2 - * and CCM SRAM..." Then, should we exclude CCM SRAM from the heap? - * - * In addition, external FSMC SRAM may be available. - */ - -#elif defined(CONFIG_STM32_STM32G4XXX) - -/* Set the end of system SRAM */ - -#if defined(CONFIG_STM32_STM32G47XX) -# define SRAM1_END 0x20020000 -#elif defined(CONFIG_STM32_STM32G43XX) -# define SRAM1_END 0x20005800 -#else -# error "Unsupported STM32G4 chip" -#endif - -/* Set the range of CCM SRAM as well (although we may not use it) */ - -# define SRAM2_START 0x10000000 - -#if defined(CONFIG_STM32_STM32G47XX) -# define SRAM2_END 0x10008000 -#elif defined(CONFIG_STM32_STM32G43XX) -# define SRAM2_END 0x10002700 -#else -# error "Unsupported STM32G4 chip" -#endif - -/* There are 4 possible SRAM configurations: - * - * Configuration 1. System SRAM (only) - * CONFIG_MM_REGIONS == 1 - * CONFIG_STM32_EXTERNAL_RAM NOT defined - * CONFIG_STM32_CCMEXCLUDE defined - * Configuration 2. System SRAM and CCM SRAM - * CONFIG_MM_REGIONS == 2 - * CONFIG_STM32_EXTERNAL_RAM NOT defined - * CONFIG_STM32_CCMEXCLUDE NOT defined - * Configuration 3. System SRAM and FSMC SRAM - * CONFIG_MM_REGIONS == 2 - * CONFIG_STM32_EXTERNAL_RAM defined - * CONFIG_STM32_CCMEXCLUDE defined - * Configuration 4. System SRAM, CCM SRAM, and FSMC SRAM - * CONFIG_MM_REGIONS == 3 - * CONFIG_STM32_EXTERNAL_RAM defined - * CONFIG_STM32_CCMEXCLUDE NOT defined - * - * Let's make sure that all definitions are consistent before doing - * anything else - */ - -# if defined(CONFIG_STM32_EXTERNAL_RAM) -# if (CONFIG_MM_REGIONS == 2) -/* OK: This is Configuration 3: SRAM and FSMC */ - -# elif (CONFIG_MM_REGIONS == 3) -/* OK: This is Configuration 3: SRAM, CCM, and FSMC */ - -# else -# error "Expected CONFIG_MM_REGIONS to be either 2 (SRAM + FSMC) or 3 (SRAM + CCM + FSMC)!" - -# endif -# else -# if (CONFIG_MM_REGIONS == 1) -/* OK: Configuration 1: SRAM only. */ - -# elif (CONFIG_MM_REGIONS == 2) -/* OK: Configuration 2: SRAM and CCM SRAM. */ - -# else -# error "Expected CONFIG_MM_REGIONS to be either 1 (SRAM) or 2 (SRAM + CCM)!" - -# endif -# endif - -#else -# error "Unsupported STM32 chip" -#endif - -/* If FSMC SRAM is going to be used as heap, then verify that the starting - * address and size of the external SRAM region has been provided in the - * configuration (as CONFIG_HEAP2_BASE and CONFIG_HEAP2_SIZE). - */ - -#ifdef CONFIG_STM32_EXTERNAL_RAM -# if !defined(CONFIG_HEAP2_BASE) || !defined(CONFIG_HEAP2_SIZE) -# error "CONFIG_HEAP2_BASE and CONFIG_HEAP2_SIZE must be provided" -# undef CONFIG_STM32_EXTERNAL_RAM -# endif -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: up_heap_color - * - * Description: - * Set heap memory to a known, non-zero state to checking heap usage. - * - ****************************************************************************/ - -#ifdef CONFIG_HEAP_COLORATION -static inline void up_heap_color(void *start, size_t size) -{ - memset(start, HEAP_COLOR, size); -} -#else -# define up_heap_color(start,size) -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: up_allocate_heap - * - * Description: - * This function will be called to dynamically set aside the heap region. - * - * For the kernel build (CONFIG_BUILD_PROTECTED=y) with both kernel- and - * user-space heaps (CONFIG_MM_KERNEL_HEAP=y), this function provides the - * size of the unprotected, user-space heap. - * - * If a protected kernel-space heap is provided, the kernel heap must be - * allocated (and protected) by an analogous up_allocate_kheap(). - * - * The following memory map is assumed for the flat build: - * - * .data region. Size determined at link time. - * .bss region Size determined at link time. - * IDLE thread stack. Size determined by CONFIG_IDLETHREAD_STACKSIZE. - * Heap. Extends to the end of SRAM. - * - * The following memory map is assumed for the kernel build: - * - * Kernel .data region Size determined at link time - * Kernel .bss region Size determined at link time - * Kernel IDLE thread stack Size determined by - * CONFIG_IDLETHREAD_STACKSIZE - * Padding for alignment - * User .data region Size determined at link time - * User .bss region Size determined at link time - * Kernel heap Size determined by - * CONFIG_MM_KERNEL_HEAPSIZE - * User heap Extends to the end of SRAM - * - ****************************************************************************/ - -void up_allocate_heap(void **heap_start, size_t *heap_size) -{ -#if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP) - /* Get the unaligned size and position of the user-space heap. - * This heap begins after the user-space .bss section at an offset - * of CONFIG_MM_KERNEL_HEAPSIZE (subject to alignment). - */ - - uintptr_t ubase = (uintptr_t)USERSPACE->us_bssend + - CONFIG_MM_KERNEL_HEAPSIZE; - size_t usize = SRAM1_END - ubase; - int log2; - - DEBUGASSERT(ubase < (uintptr_t)SRAM1_END); - - /* Adjust that size to account for MPU alignment requirements. - * NOTE that there is an implicit assumption that the SRAM1_END - * is aligned to the MPU requirement. - */ - - log2 = (int)mpu_log2regionfloor(usize); - - usize = (1 << log2); - ubase = SRAM1_END - usize; - - /* Return the user-space heap settings */ - - board_autoled_on(LED_HEAPALLOCATE); - *heap_start = (void *)ubase; - *heap_size = usize; - - /* Colorize the heap for debug */ - - up_heap_color((void *)ubase, usize); - - /* Allow user-mode access to the user heap memory */ - - stm32_mpu_uheap((uintptr_t)ubase, usize); -#else - - /* Return the heap settings */ - - board_autoled_on(LED_HEAPALLOCATE); - *heap_start = (void *)g_idle_topstack; - *heap_size = SRAM1_END - g_idle_topstack; - - /* Colorize the heap for debug */ - - up_heap_color(*heap_start, *heap_size); -#endif -} - -/**************************************************************************** - * Name: up_allocate_kheap - * - * Description: - * For the kernel build (CONFIG_BUILD_PROTECTED=y) with both kernel- and - * user-space heaps (CONFIG_MM_KERNEL_HEAP=y), this function allocates - * (and protects) the kernel-space heap. - * - ****************************************************************************/ - -#if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP) -void up_allocate_kheap(void **heap_start, size_t *heap_size) -{ - /* Get the unaligned size and position of the user-space heap. - * This heap begins after the user-space .bss section at an offset - * of CONFIG_MM_KERNEL_HEAPSIZE (subject to alignment). - */ - - uintptr_t ubase = (uintptr_t)USERSPACE->us_bssend + - CONFIG_MM_KERNEL_HEAPSIZE; - size_t usize = SRAM1_END - ubase; - int log2; - - DEBUGASSERT(ubase < (uintptr_t)SRAM1_END); - - /* Adjust that size to account for MPU alignment requirements. - * NOTE that there is an implicit assumption that the SRAM1_END - * is aligned to the MPU requirement. - */ - - log2 = (int)mpu_log2regionfloor(usize); - - usize = (1 << log2); - ubase = SRAM1_END - usize; - - /* Return the kernel heap settings (i.e., the part of the heap region - * that was not dedicated to the user heap). - */ - - *heap_start = (void *)USERSPACE->us_bssend; - *heap_size = ubase - (uintptr_t)USERSPACE->us_bssend; -} -#endif - -/**************************************************************************** - * Name: arm_addregion - * - * Description: - * Memory may be added in non-contiguous chunks. Additional chunks are - * added by calling this function. - * - ****************************************************************************/ - -#if CONFIG_MM_REGIONS > 1 -void arm_addregion(void) -{ -#ifndef CONFIG_STM32_CCMEXCLUDE -#if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP) - - /* Allow user-mode access to the STM32F20xxx/STM32F40xxx CCM SRAM heap */ - - stm32_mpu_uheap((uintptr_t)SRAM2_START, SRAM2_END - SRAM2_START); - -#endif - - /* Colorize the heap for debug */ - - up_heap_color((void *)SRAM2_START, SRAM2_END - SRAM2_START); - - /* Add the STM32F20xxx/STM32F40xxx CCM SRAM user heap region. */ - - kumm_addregion((void *)SRAM2_START, SRAM2_END - SRAM2_START); -#endif - -#ifdef CONFIG_STM32_EXTERNAL_RAM -#if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP) - - /* Allow user-mode access to the FSMC SRAM user heap memory */ - - stm32_mpu_uheap((uintptr_t)CONFIG_HEAP2_BASE, CONFIG_HEAP2_SIZE); - -#endif - - /* Colorize the heap for debug */ - - up_heap_color((void *)CONFIG_HEAP2_BASE, CONFIG_HEAP2_SIZE); - - /* Add the external FSMC SRAM user heap region. */ - - kumm_addregion((void *)CONFIG_HEAP2_BASE, CONFIG_HEAP2_SIZE); -#endif -} -#endif diff --git a/arch/arm/src/stm32/stm32_bbsram.c b/arch/arm/src/stm32/stm32_bbsram.c deleted file mode 100644 index b595b37761100..0000000000000 --- a/arch/arm/src/stm32/stm32_bbsram.c +++ /dev/null @@ -1,858 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_bbsram.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* This will driver create a set of files in the STM32's Battery backed up - * SRAM. That can be used to store data retained across power cycles. - * - */ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "stm32_bbsram.h" -#include "chip.h" -#include "stm32_pwr.h" -#include "stm32_rtc.h" - -#ifdef CONFIG_STM32_BBSRAM - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#if !defined(CONFIG_STM32_BKPSRAM) -#error Driver Requires CONFIG_STM32_BKPSRAM to be enabled -#endif - -#define MAX_OPENCNT (255) /* Limit of uint8_t */ - -#ifndef CONFIG_DEBUG_INFO -# undef CONFIG_BBSRAM_DEBUG -#endif - -#if defined(CONFIG_BBSRAM_DEBUG) -# define BBSRAM_DEBUG_READ() stm32_bbsram_rd() -# define BBSRAM_DUMP(p,s) stm32_bbsram_dump(p,s) -#else -# define BBSRAM_DEBUG_READ() -# define BBSRAM_DUMP(p,s) -#endif - -#define BBSRAM_HEADER_SIZE (sizeof(struct bbsramfh_s)) -#define BBSRAM_CRCED_OFFSET (sizeof(((struct bbsramfh_s *)0)->crc)) -#define BBSRAM_CRCED_SIZE(l) (BBSRAM_HEADER_SIZE-(BBSRAM_CRCED_OFFSET)+(l)) -#define BBSRAM_ALIGNMENT (sizeof(((struct bbsramfh_s *)0)->crc)) -#define BBSRAM_ALIGNMENT_MASK (BBSRAM_ALIGNMENT-1) - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/* File Header */ - -struct bbsramfh_s -{ - uint32_t crc; /* CRC calculated over data and this struct - * starting at fileno */ - uint8_t fileno; /* The minor number */ - uint8_t dirty; /* Data has been written to the file */ - uint16_t len; /* Total Bytes in this file */ - struct timespec lastwrite; /* Last write time */ - uint8_t data[]; /* Data in the file */ -}; - -struct stm32_bbsram_s -{ - mutex_t lock; /* For atomic accesses to this structure */ - uint8_t refs; /* Number of references */ - struct bbsramfh_s *bbf; /* File in bbram */ -}; - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -static int stm32_bbsram_open(struct file *filep); -static int stm32_bbsram_close(struct file *filep); -static off_t stm32_bbsram_seek(struct file *filep, off_t offset, - int whence); -static ssize_t stm32_bbsram_read(struct file *filep, char *buffer, - size_t len); -static ssize_t stm32_bbsram_write(struct file *filep, - const char *buffer, size_t len); -static int stm32_bbsram_ioctl(struct file *filep, int cmd, - unsigned long arg); -static int stm32_bbsram_poll(struct file *filep, - struct pollfd *fds, bool setup); -#ifndef CONFIG_DISABLE_PSEUDOFS_OPERATIONS -static int stm32_bbsram_unlink(struct inode *inode); -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -#if defined(CONFIG_BBSRAM_DEBUG) -static uint8_t debug[STM32_BBSRAM_SIZE]; -#endif - -static const struct file_operations g_stm32_bbsram_fops = -{ - .open = stm32_bbsram_open, - .close = stm32_bbsram_close, - .read = stm32_bbsram_read, - .write = stm32_bbsram_write, - .seek = stm32_bbsram_seek, - .ioctl = stm32_bbsram_ioctl, - .poll = stm32_bbsram_poll, -#ifndef CONFIG_DISABLE_PSEUDOFS_OPERATIONS - .unlink = stm32_bbsram_unlink -#endif -}; - -static struct stm32_bbsram_s g_bbsram[CONFIG_STM32_BBSRAM_FILES]; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_bbsram_rd - ****************************************************************************/ - -#if defined(CONFIG_BBSRAM_DEBUG) -static void stm32_bbsram_rd(void) -{ - memcpy(&debug, (uint8_t *)STM32_BKPSRAM_BASE, sizeof debug); -} -#endif - -/**************************************************************************** - * Name: stm32_bbsram_rd - ****************************************************************************/ - -#if defined(CONFIG_BBSRAM_DEBUG) -static void stm32_bbsram_dump(struct bbsramfh_s *bbf, char *op) -{ - BBSRAM_DEBUG_READ(); - _info("%s:\n", op); - _info(" File Address:0x%8x\n", bbf); - _info(" crc:0x%8x\n", bbf->crc); - _info(" fileno:%d\n", (int) bbf->fileno); - _info(" dirty:%d\n", (int) bbf->dirty); - _info(" length:%d\n", (int) bbf->len); - _info(" time:%jd:%ld\n", (intmax_t)bbf->lastwrite.tv_sec, - bbf->lastwrite.tv_nsec); - _info(" data: 0x%2x 0x%2x 0x%2x 0x%2x 0x%2x\n", - bbf->data[0], bbf->data[1], bbf->data[2], bbf->data[3], bbf->data[4]); -} -#endif - -/**************************************************************************** - * Name: stm32_bbsram_unlock - * - * Description: - * Unprotects RTC registers, RTC backup data registers and backup SRAM - * against parasitic write access - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -static inline void stm32_bbsram_unlock(void) -{ - stm32_pwr_enablebkp(true); -} - -/**************************************************************************** - * Name: stm32_bbsram_lock - * - * Description: - * Protects RTC registers, RTC backup data registers and backup SRAM - * against parasitic write access - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -static inline void stm32_bbsram_lock(void) -{ - stm32_pwr_enablebkp(false); -} - -/**************************************************************************** - * Name: stm32_bbsram_crc - * - * Description: - * Calculates the CRC of the block - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -static uint32_t stm32_bbsram_crc(struct bbsramfh_s *pf) -{ - return crc32((uint8_t *)pf + BBSRAM_CRCED_OFFSET, - BBSRAM_CRCED_SIZE(pf->len)); -} - -/**************************************************************************** - * Name: stm32_bbsram_open - * - * Description: Open the device - * - ****************************************************************************/ - -static int stm32_bbsram_open(struct file *filep) -{ - struct inode *inode = filep->f_inode; - struct stm32_bbsram_s *bbr; - int ret; - - DEBUGASSERT(inode->i_private); - bbr = inode->i_private; - - /* Increment the reference count */ - - ret = nxmutex_lock(&bbr->lock); - if (ret < 0) - { - return ret; - } - - if (bbr->refs == MAX_OPENCNT) - { - return -EMFILE; - } - else - { - bbr->refs++; - } - - nxmutex_unlock(&bbr->lock); - return OK; -} - -/**************************************************************************** - * Name: stm32_bbsram_internal_close - * - * Description: - * Close BBSRAM entry; Recalculate the time and crc - * - ****************************************************************************/ - -static int stm32_bbsram_internal_close(struct bbsramfh_s *bbf) -{ - bbf->dirty = 0; - clock_gettime(CLOCK_REALTIME, &bbf->lastwrite); - bbf->crc = stm32_bbsram_crc(bbf); - - BBSRAM_DUMP(bbf, "close done"); - return bbf->len; -} - -/**************************************************************************** - * Name: stm32_bbsram_close - * - * Description: close the device - * - ****************************************************************************/ - -static int stm32_bbsram_close(struct file *filep) -{ - struct inode *inode = filep->f_inode; - struct stm32_bbsram_s *bbr; - int ret = OK; - - DEBUGASSERT(inode->i_private); - bbr = inode->i_private; - - ret = nxmutex_lock(&bbr->lock); - if (ret < 0) - { - return ret; - } - - BBSRAM_DUMP(bbr->bbf, "close"); - - if (bbr->refs == 0) - { - ret = -EIO; - } - else - { - bbr->refs--; - - if (bbr->refs == 0) - { - if (bbr->bbf->dirty) - { - /* Recalculate the time and crc */ - - stm32_bbsram_unlock(); - stm32_bbsram_internal_close(bbr->bbf); - stm32_bbsram_lock(); - } - } - } - - nxmutex_unlock(&bbr->lock); - return ret; -} - -/**************************************************************************** - * Name: stm32_bbsram_seek - ****************************************************************************/ - -static off_t stm32_bbsram_seek(struct file *filep, off_t offset, - int whence) -{ - struct inode *inode = filep->f_inode; - struct stm32_bbsram_s *bbr; - off_t newpos; - int ret; - - DEBUGASSERT(inode->i_private); - bbr = inode->i_private; - - ret = nxmutex_lock(&bbr->lock); - if (ret < 0) - { - return (off_t)ret; - } - - /* Determine the new, requested file position */ - - switch (whence) - { - case SEEK_CUR: - newpos = filep->f_pos + offset; - break; - - case SEEK_SET: - newpos = offset; - break; - - case SEEK_END: - newpos = bbr->bbf->len + offset; - break; - - default: - - /* Return EINVAL if the whence argument is invalid */ - - nxmutex_unlock(&bbr->lock); - return -EINVAL; - } - - /* Opengroup.org: - * - * "The lseek() function shall allow the file offset to be set beyond the - * end of the existing data in the file. If data is later written at this - * point, subsequent reads of data in the gap shall return bytes with the - * value 0 until data is actually written into the gap." - * - * We can conform to the first part, but not the second. But return -EINVAL - * if "...the resulting file offset would be negative for a regular file, - * block special file, or directory." - */ - - if (newpos >= 0) - { - filep->f_pos = newpos; - ret = newpos; - } - else - { - ret = -EINVAL; - } - - nxmutex_unlock(&bbr->lock); - return ret; -} - -/**************************************************************************** - * Name: stm32_bbsram_read - ****************************************************************************/ - -static ssize_t stm32_bbsram_read(struct file *filep, char *buffer, - size_t len) -{ - struct inode *inode = filep->f_inode; - struct stm32_bbsram_s *bbr; - int ret; - - DEBUGASSERT(inode->i_private); - bbr = inode->i_private; - - ret = nxmutex_lock(&bbr->lock); - if (ret < 0) - { - return (ssize_t)ret; - } - - /* Trim len if read would go beyond end of device */ - - if ((filep->f_pos + len) > bbr->bbf->len) - { - len = bbr->bbf->len - filep->f_pos; - } - - memcpy(buffer, &bbr->bbf->data[filep->f_pos], len); - filep->f_pos += len; - nxmutex_unlock(&bbr->lock); - return len; -} - -/**************************************************************************** - * Name: stm32_bbsram_internal_write - ****************************************************************************/ - -static ssize_t stm32_bbsram_internal_write(struct bbsramfh_s *bbf, - const char *buffer, - off_t offset, size_t len) -{ - bbf->dirty = 1; - memcpy(&bbf->data[offset], buffer, len); - return len; -} - -/**************************************************************************** - * Name: stm32_bbsram_write - ****************************************************************************/ - -static ssize_t stm32_bbsram_write(struct file *filep, - const char *buffer, size_t len) -{ - struct inode *inode = filep->f_inode; - struct stm32_bbsram_s *bbr; - int ret = -EFBIG; - - DEBUGASSERT(inode->i_private); - bbr = inode->i_private; - - /* Forbid writes past the end of the device */ - - if (filep->f_pos < bbr->bbf->len) - { - /* Clamp len to avoid crossing the end of the memory */ - - if ((filep->f_pos + len) > bbr->bbf->len) - { - len = bbr->bbf->len - filep->f_pos; - } - - ret = nxmutex_lock(&bbr->lock); - if (ret < 0) - { - return (ssize_t)ret; - } - - ret = len; /* save number of bytes written */ - - BBSRAM_DUMP(bbr->bbf, "write"); - stm32_bbsram_unlock(); - stm32_bbsram_internal_write(bbr->bbf, buffer, filep->f_pos, len); - stm32_bbsram_lock(); - filep->f_pos += len; - BBSRAM_DUMP(bbr->bbf, "write done"); - nxmutex_unlock(&bbr->lock); - } - - BBSRAM_DEBUG_READ(); - return ret; -} - -/**************************************************************************** - * Name: stm32_bbsram_poll - ****************************************************************************/ - -static int stm32_bbsram_poll(struct file *filep, struct pollfd *fds, - bool setup) -{ - if (setup) - { - poll_notify(&fds, 1, POLLIN | POLLOUT); - } - - return OK; -} - -/**************************************************************************** - * Name: stm32_bbsram_ioctl - * - * Description: Return device geometry - * - ****************************************************************************/ - -static int stm32_bbsram_ioctl(struct file *filep, int cmd, - unsigned long arg) -{ - struct inode *inode = filep->f_inode; - struct stm32_bbsram_s *bbr; - int ret = -ENOTTY; - - DEBUGASSERT(inode->i_private); - bbr = inode->i_private; - - if (cmd == STM32_BBSRAM_GETDESC_IOCTL) - { - struct bbsramd_s *bbrr = (struct bbsramd_s *)((uintptr_t)arg); - - ret = nxmutex_lock(&bbr->lock); - if (ret < 0) - { - return ret; - } - - if (!bbrr) - { - ret = -EINVAL; - } - else - { - bbrr->fileno = bbr->bbf->fileno; - bbrr->lastwrite = bbr->bbf->lastwrite; - bbrr->len = bbr->bbf->len; - bbrr->flags = ((bbr->bbf->crc == stm32_bbsram_crc(bbr->bbf)) - ? BBSRAM_CRC_VALID : 0); - bbrr->flags |= ((bbr->bbf->dirty) ? BBSRAM_DIRTY : 0); - ret = OK; - } - - nxmutex_unlock(&bbr->lock); - } - - return ret; -} - -/**************************************************************************** - * Name: stm32_bbsram_unlink - * - * Description: - * This function will remove the remove the file from the file system - * it will zero the contents and time stamp. It will leave the fileno - * and pointer to the BBSRAM intact. - * It should be called called on the file used for the crash dump - * to remove it from visibility in the file system after it is created or - * read thus arming it. - * - ****************************************************************************/ - -#ifndef CONFIG_DISABLE_PSEUDOFS_OPERATIONS -static int stm32_bbsram_unlink(struct inode *inode) -{ - struct stm32_bbsram_s *bbr; - int ret; - - DEBUGASSERT(inode->i_private); - bbr = inode->i_private; - - ret = nxmutex_lock(&bbr->lock); - if (ret < 0) - { - return ret; - } - - stm32_bbsram_unlock(); - memset(bbr->bbf->data, 0, bbr->bbf->len); - bbr->bbf->lastwrite.tv_nsec = 0; - bbr->bbf->lastwrite.tv_sec = 0; - bbr->bbf->crc = stm32_bbsram_crc(bbr->bbf); - stm32_bbsram_lock(); - bbr->refs = 0; - nxmutex_unlock(&bbr->lock); - nxmutex_destroy(&bbr->lock); - - return 0; -} -#endif - -/**************************************************************************** - * Name: stm32_bbsram_probe - * - * Description: Based on the number of files defined and their sizes - * Initializes the base pointers to the file entries. - * - ****************************************************************************/ - -static int stm32_bbsram_probe(int *ent, struct stm32_bbsram_s pdev[]) -{ - int i; - int avail = STM32_BBSRAM_SIZE; - int alloc; - int size; - int ret = -EFBIG; - struct bbsramfh_s *pf = (struct bbsramfh_s *) STM32_BKPSRAM_BASE; - - for (i = 0; (i < CONFIG_STM32_BBSRAM_FILES) && ent[i] && (avail > 0); i++) - { - /* Validate the actual allocations against what is in the BBSRAM */ - - size = ent[i]; - - /* Use all that is left */ - - if (size == -1) - { - size = avail - (BBSRAM_HEADER_SIZE + BBSRAM_ALIGNMENT_MASK); - } - - /* Add in header size and keep aligned */ - - alloc = size + BBSRAM_HEADER_SIZE + BBSRAM_ALIGNMENT_MASK; - alloc &= ~(BBSRAM_ALIGNMENT_MASK); - - /* Does it fit? */ - - if (alloc <= avail) - { - ret = i + 1; - BBSRAM_DUMP(pf, "probe"); - - if (pf->len != size || - pf->fileno != i || - pf->crc != stm32_bbsram_crc(pf)) - { - /* Not Valid so wipe the file in BBSRAM */ - - memset((uint8_t *)pf, 0, alloc); - pf->fileno = i; - pf->len = size; - pf->crc = stm32_bbsram_crc(pf); - BBSRAM_DUMP(pf, "probe reset"); - } - - pdev[i].bbf = pf; - pf = (struct bbsramfh_s *)((uint8_t *)pf + alloc); - nxmutex_init(&g_bbsram[i].lock); - } - - avail -= alloc; - } - - BBSRAM_DEBUG_READ(); - return ret; -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Function: stm32_bbsraminitialize - * - * Description: - * Initialize the Battery Backed up SRAM driver. - * - * Input Parameters: - * devpath - the path to instantiate the files. - * sizes - Pointer to a any array of file sizes to create - * the last entry should be 0 - * A size of -1 will use all the remaining spaces - * - * If the length of sizes is greater then CONFIG_STM32_BBSRAM_FILES - * CONFIG_STM32_BBSRAM_FILES will be returned. - * - * Returned Value: - * Number of files created on success; Negated errno on failure. - * - * Assumptions: - * - ****************************************************************************/ - -int stm32_bbsraminitialize(char *devpath, int *sizes) -{ - int i; - int fcnt; - char devname[32]; - - int ret = OK; - - if (devpath == NULL) - { - return -EINVAL; - } - - i = strlen(devpath); - if (i == 0 || i > sizeof(devname) - 3) - { - return -EINVAL; - } - - memset(g_bbsram, 0, sizeof(g_bbsram)); - - /* Clocking for the PWR block must be provided. However, this is done - * unconditionally in stm32f40xxx_rcc.c on power up. This done - * unconditionally because the PWR block is also needed to set the - * internal voltage regulator for maximum performance. - */ - - /* Enable backup SRAM clock is done in rcc_enableahb1() when - * CONFIG_STM32_BKPSRAM is defined. - */ - - /* Allow Access */ - - stm32_bbsram_unlock(); - - /* Enable backup regulator so that the data is retained in Standby and - * VBAT modes - */ - - stm32_pwr_enablebreg(true); - - fcnt = stm32_bbsram_probe(sizes, g_bbsram); - - for (i = 0; i < fcnt && ret >= OK; i++) - { - snprintf(devname, sizeof(devname), "%s%d", devpath, i); - ret = register_driver(devname, &g_stm32_bbsram_fops, - 0666, &g_bbsram[i]); - } - - /* Disallow Access */ - - stm32_bbsram_lock(); - return ret < OK ? ret : fcnt; -} - -/**************************************************************************** - * Function: stm32_bbsram_savepanic - * - * Description: - * Saves the panic context in a previously allocated BBSRAM file - * - * Input Parameters: - * fileno - the value returned by the ioctl STM32_BBSRAM_GETDESC_IOCTL - * context - Pointer to a any array of bytes to save - * length - The length of the data pointed to byt context - * - * Returned Value: - * Length saved or negated errno. - * - * Assumptions: - * - ****************************************************************************/ - -#if defined(CONFIG_STM32_SAVE_CRASHDUMP) -int stm32_bbsram_savepanic(int fileno, uint8_t *context, int length) -{ - struct bbsramfh_s *bbf; - int fill; - int ret = -ENOSPC; - - /* On a bad day we could panic while panicking, (and we debug assert) - * this is a potential feeble attempt at only writing the first - * panic's context to the file - */ - - static bool once = false; - - if (!once) - { - once = true; - - DEBUGASSERT(fileno > 0 && fileno < CONFIG_STM32_BBSRAM_FILES); - - bbf = g_bbsram[fileno].bbf; - - DEBUGASSERT(bbf); - - /* If the g_bbsram has been nulled out we return ENXIO. - * - * As once ensures we will keep the first dump. Checking the time for - * 0 protects from over writing a previous crash dump that has not - * been saved to long term storage and erased. The dreaded reboot - * loop. - */ - - if (!bbf) - { - ret = -ENXIO; - } - else if ((bbf->lastwrite.tv_sec == 0 && bbf->lastwrite.tv_nsec == 0)) - { - /* Clamp length if too big */ - - if (length > bbf->len) - { - length = bbf->len; - } - - stm32_bbsram_unlock(); - - stm32_bbsram_internal_write(bbf, (char *) context, 0, length); - - /* Fill with 0 if data is less then file size */ - - fill = (int) bbf->len - length; - - if (fill > 0) - { - memset(&bbf->data[length], 0, fill); - } - - /* Seal the file */ - - stm32_bbsram_internal_close(bbf); - - stm32_bbsram_lock(); - ret = length; - } - } - - return ret; -} -#endif - -#endif /* CONFIG_BBSRAM_DRIVER */ diff --git a/arch/arm/src/stm32/stm32_bbsram.h b/arch/arm/src/stm32/stm32_bbsram.h deleted file mode 100644 index bca2251088f56..0000000000000 --- a/arch/arm/src/stm32/stm32_bbsram.h +++ /dev/null @@ -1,152 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_bbsram.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32_STM32_BBSRAM_H -#define __ARCH_ARM_SRC_STM32_STM32_BBSRAM_H - -/**************************************************************************** - * The purpose of this driver is to add battery backup file to the file - * system. There can be CONFIG_STM32_BBRSRAM_COUNT files defined. - * These files are of fixed size up to the maximum of the backing SRAM. - * In the care of the STM32F2 and STM32F4 this is a maximum of 4K Bytes. - * - * If CONFIG_SAVE_CRASHDUMP is defined The driver also supports a feature - * to save the context of a PANIC in one of these files. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) -# define STM32_BBSRAM_SIZE 4096 -#else -# error No backup SRAM on this STM32 -#endif - -#if !defined(CONFIG_STM32_BBSRAM_FILES) -# define CONFIG_STM32_BBSRAM_FILES 4 -#endif - -/* REVISIT: What guarantees that STM32_BBSRAM_GETDESC_IOCTL has a unique - * value among all over _DIOC() values? - */ - -#define STM32_BBSRAM_GETDESC_IOCTL _DIOC(0x0010) /* Returns a bbsramd_s */ - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -#ifndef __ASSEMBLY__ - -enum bbsramdf_e -{ - BBSRAM_CRC_VALID = 1, /* The crc is valid */ - BBSRAM_DIRTY = 2, /* The file was closed */ -}; - -struct bbsramd_s -{ - uint8_t flags; /* The crc is valid and the file was closed */ - uint8_t fileno; /* The minor number */ - uint16_t len; /* Total Bytes in this file */ - struct timespec lastwrite; /* Last write time */ -}; - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -#undef EXTERN -#if defined(__cplusplus) -# define EXTERN extern "C" -extern "C" -{ -#else -# define EXTERN extern -#endif - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Function: stm32_bbsraminitialize - * - * Description: - * Initialize the Battery Backed up SRAM driver. - * - * Input Parameters: - * devpath - the path to instantiate the files. - * sizes - Pointer to a any array of file sizes to create - * the last entry should be 0 - * A size of -1 will use all the remaining spaces - * - * If the length of sizes is greater then CONFIG_STM32_BBSRAM_FILES - * CONFIG_STM32_BBSRAM_FILES will be returned. - * - * Returned Value: - * Number of files created on success; Negated errno on failure. - * - * Assumptions: - * - ****************************************************************************/ - -int stm32_bbsraminitialize(char *devpath, int *sizes); - -/**************************************************************************** - * Function: stm32_bbsram_savepanic - * - * Description: - * Saves the panic context in a previously allocated BBSRAM file - * - * Parameters: - * fileno - the value returned by the ioctl STM32_BBSRAM_GETDESC_IOCTL - * context - Pointer to a any array of bytes to save - * length - The length of the data pointed to byt context - * - * Returned Value: - * Length saved or negated errno. - * - * Assumptions: - * - ****************************************************************************/ - -#if defined(CONFIG_STM32_SAVE_CRASHDUMP) -int stm32_bbsram_savepanic(int fileno, uint8_t *context, int length); -#endif - -#undef EXTERN -#ifdef __cplusplus -} -#endif -#endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32_STM32_BBSRAM_H */ diff --git a/arch/arm/src/stm32/stm32_bkp.h b/arch/arm/src/stm32/stm32_bkp.h deleted file mode 100644 index 1d2c3cc858d73..0000000000000 --- a/arch/arm/src/stm32/stm32_bkp.h +++ /dev/null @@ -1,50 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_bkp.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32_STM32_BKP_H -#define __ARCH_ARM_SRC_STM32_STM32_BKP_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -/* Only the STM32 F1 family has a dedicated address region for BKP memory. - * For F2, F3, and F4 parts, the bKP registers lie in the same address - * region as the RTCC and the definitions in chip/stm32_rtcc.h should be used - * to access backup registers. - * NOTE: These definitions are not interchangeable! - */ - -#include "chip.h" -#ifdef CONFIG_STM32_STM32F10XX -# include "hardware/stm32_bkp.h" -#else -# include "hardware/stm32_rtcc.h" -#endif - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#endif /* __ARCH_ARM_SRC_STM32_STM32_BKP_H */ diff --git a/arch/arm/src/stm32/stm32_can.c b/arch/arm/src/stm32/stm32_can.c deleted file mode 100644 index d0e8373aa361c..0000000000000 --- a/arch/arm/src/stm32/stm32_can.c +++ /dev/null @@ -1,2540 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_can.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -#include "arm_internal.h" -#include "chip.h" -#include "stm32.h" -#include "stm32_rcc.h" -#include "stm32_can.h" - -#if defined(CONFIG_CAN) && \ - (defined(CONFIG_STM32_CAN1) || defined(CONFIG_STM32_CAN2)) - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Delays *******************************************************************/ - -/* Time out for INAK bit */ - -#define INAK_TIMEOUT 65535 - -/* Bit timing ***************************************************************/ - -#define CAN_BIT_QUANTA (CONFIG_STM32_CAN_TSEG1 + CONFIG_STM32_CAN_TSEG2 + 1) - -#ifndef CONFIG_DEBUG_CAN_INFO -# undef CONFIG_STM32_CAN_REGDEBUG -#endif - -/* CAN error interrupts */ - -#ifdef CONFIG_CAN_ERRORS -# define STM32_CAN_ERRINT (CAN_IER_LECIE | CAN_IER_ERRIE | \ - CAN_IER_BOFIE | CAN_IER_EPVIE | \ - CAN_IER_EWGIE) -#endif - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -struct stm32_can_s -{ - uint8_t port; /* CAN port number (1 or 2) */ - uint8_t canrx[2]; /* CAN RX FIFO 0/1 IRQ number */ - uint8_t cantx; /* CAN TX IRQ number */ -#ifdef CONFIG_CAN_ERRORS - uint8_t cansce; /* CAN SCE IRQ number */ -#endif - uint8_t filter; /* Filter number */ - uint32_t base; /* Base address of the CAN control registers */ - uint32_t fbase; /* Base address of the CAN filter registers */ - uint32_t baud; /* Configured baud */ -}; - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -/* CAN Register access */ - -static uint32_t stm32can_getreg(struct stm32_can_s *priv, - int offset); -static uint32_t stm32can_getfreg(struct stm32_can_s *priv, - int offset); -static void stm32can_putreg(struct stm32_can_s *priv, int offset, - uint32_t value); -static void stm32can_putfreg(struct stm32_can_s *priv, int offset, - uint32_t value); -#ifdef CONFIG_STM32_CAN_REGDEBUG -static void stm32can_dumpctrlregs(struct stm32_can_s *priv, - const char *msg); -static void stm32can_dumpmbregs(struct stm32_can_s *priv, - const char *msg); -static void stm32can_dumpfiltregs(struct stm32_can_s *priv, - const char *msg); -#else -# define stm32can_dumpctrlregs(priv,msg) -# define stm32can_dumpmbregs(priv,msg) -# define stm32can_dumpfiltregs(priv,msg) -#endif - -/* Filtering (todo) */ - -#ifdef CONFIG_CAN_EXTID -static int stm32can_addextfilter(struct stm32_can_s *priv, - struct canioc_extfilter_s *arg); -static int stm32can_delextfilter(struct stm32_can_s *priv, - int arg); -#endif -static int stm32can_addstdfilter(struct stm32_can_s *priv, - struct canioc_stdfilter_s *arg); -static int stm32can_delstdfilter(struct stm32_can_s *priv, - int arg); - -/* CAN driver methods */ - -static void stm32can_reset(struct can_dev_s *dev); -static int stm32can_setup(struct can_dev_s *dev); -static void stm32can_shutdown(struct can_dev_s *dev); -static void stm32can_rxint(struct can_dev_s *dev, bool enable); -static void stm32can_txint(struct can_dev_s *dev, bool enable); -static int stm32can_ioctl(struct can_dev_s *dev, int cmd, - unsigned long arg); -static int stm32can_remoterequest(struct can_dev_s *dev, - uint16_t id); -static int stm32can_send(struct can_dev_s *dev, - struct can_msg_s *msg); -static bool stm32can_txready(struct can_dev_s *dev); -static bool stm32can_txempty(struct can_dev_s *dev); - -#ifdef CONFIG_CAN_ERRORS -static void stm32can_errint(struct can_dev_s *dev, bool enable); -#endif - -/* CAN interrupt handling */ - -static int stm32can_rxinterrupt(struct can_dev_s *dev, int rxmb); -static int stm32can_rx0interrupt(int irq, void *context, void *arg); -static int stm32can_rx1interrupt(int irq, void *context, void *arg); -static int stm32can_txinterrupt(int irq, void *context, void *arg); -#ifdef CONFIG_CAN_ERRORS -static int stm32can_sceinterrupt(int irq, void *context, void *arg); -#endif - -/* Initialization */ - -static int stm32can_enterinitmode(struct stm32_can_s *priv); -static int stm32can_exitinitmode(struct stm32_can_s *priv); -static int stm32can_bittiming(struct stm32_can_s *priv); -static int stm32can_cellinit(struct stm32_can_s *priv); -static int stm32can_filterinit(struct stm32_can_s *priv); - -/* TX mailbox status */ - -static bool stm32can_txmb0empty(uint32_t tsr_regval); -static bool stm32can_txmb1empty(uint32_t tsr_regval); -static bool stm32can_txmb2empty(uint32_t tsr_regval); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -static const struct can_ops_s g_canops = -{ - .co_reset = stm32can_reset, - .co_setup = stm32can_setup, - .co_shutdown = stm32can_shutdown, - .co_rxint = stm32can_rxint, - .co_txint = stm32can_txint, - .co_ioctl = stm32can_ioctl, - .co_remoterequest = stm32can_remoterequest, - .co_send = stm32can_send, - .co_txready = stm32can_txready, - .co_txempty = stm32can_txempty, -}; - -#ifdef CONFIG_STM32_CAN1 -static struct stm32_can_s g_can1priv = -{ - .port = 1, - .canrx = - { - STM32_IRQ_CAN1RX0, - STM32_IRQ_CAN1RX1, - }, - .cantx = STM32_IRQ_CAN1TX, -#ifdef CONFIG_CAN_ERRORS - .cansce = STM32_IRQ_CAN1SCE, -#endif - .filter = 0, - .base = STM32_CAN1_BASE, - .fbase = STM32_CAN1_BASE, - .baud = CONFIG_STM32_CAN1_BAUD, -}; - -static struct can_dev_s g_can1dev = -{ - .cd_ops = &g_canops, - .cd_priv = &g_can1priv, -}; -#endif - -#ifdef CONFIG_STM32_CAN2 -static struct stm32_can_s g_can2priv = -{ - .port = 2, - .canrx = - { - STM32_IRQ_CAN2RX0, - STM32_IRQ_CAN2RX1, - }, - .cantx = STM32_IRQ_CAN2TX, -#ifdef CONFIG_CAN_ERRORS - .cansce = STM32_IRQ_CAN2SCE, -#endif - .filter = CAN_NFILTERS / 2, - .base = STM32_CAN2_BASE, - .fbase = STM32_CAN1_BASE, - .baud = CONFIG_STM32_CAN2_BAUD, -}; - -static struct can_dev_s g_can2dev = -{ - .cd_ops = &g_canops, - .cd_priv = &g_can2priv, -}; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32can_getreg - * Name: stm32can_getfreg - * - * Description: - * Read the value of a CAN register or filter block register. - * - * Input Parameters: - * priv - A reference to the CAN block status - * offset - The offset to the register to read - * - * Returned Value: - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_CAN_REGDEBUG -static uint32_t stm32can_vgetreg(uint32_t addr) -{ - static uint32_t prevaddr = 0; - static uint32_t preval = 0; - static uint32_t count = 0; - - /* Read the value from the register */ - - uint32_t val = getreg32(addr); - - /* Is this the same value that we read from the same register last time? - * Are we polling the register? If so, suppress some of the output. - */ - - if (addr == prevaddr && val == preval) - { - if (count == 0xffffffff || ++count > 3) - { - if (count == 4) - { - caninfo("...\n"); - } - - return val; - } - } - - /* No this is a new address or value */ - - else - { - /* Did we print "..." for the previous value? */ - - if (count > 3) - { - /* Yes.. then show how many times the value repeated */ - - caninfo("[repeats %" PRIu32 " more times]\n", count - 3); - } - - /* Save the new address, value, and count */ - - prevaddr = addr; - preval = val; - count = 1; - } - - /* Show the register value read */ - - caninfo("%08" PRIx32 "->%08" PRIx32 "\n", addr, val); - return val; -} - -static uint32_t stm32can_getreg(struct stm32_can_s *priv, int offset) -{ - return stm32can_vgetreg(priv->base + offset); -} - -static uint32_t stm32can_getfreg(struct stm32_can_s *priv, int offset) -{ - return stm32can_vgetreg(priv->fbase + offset); -} - -#else -static uint32_t stm32can_getreg(struct stm32_can_s *priv, int offset) -{ - return getreg32(priv->base + offset); -} - -static uint32_t stm32can_getfreg(struct stm32_can_s *priv, int offset) -{ - return getreg32(priv->fbase + offset); -} - -#endif - -/**************************************************************************** - * Name: stm32can_putreg - * Name: stm32can_putfreg - * - * Description: - * Set the value of a CAN register or filter block register. - * - * Input Parameters: - * priv - A reference to the CAN block status - * offset - The offset to the register to write - * value - The value to write to the register - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_CAN_REGDEBUG -static void stm32can_vputreg(uint32_t addr, uint32_t value) -{ - /* Show the register value being written */ - - caninfo("%08" PRIx32 "->%08" PRIx32 "\n", addr, value); - - /* Write the value */ - - putreg32(value, addr); -} - -static void stm32can_putreg(struct stm32_can_s *priv, int offset, - uint32_t value) -{ - stm32can_vputreg(priv->base + offset, value); -} - -static void stm32can_putfreg(struct stm32_can_s *priv, int offset, - uint32_t value) -{ - stm32can_vputreg(priv->fbase + offset, value); -} - -#else -static void stm32can_putreg(struct stm32_can_s *priv, int offset, - uint32_t value) -{ - putreg32(value, priv->base + offset); -} - -static void stm32can_putfreg(struct stm32_can_s *priv, int offset, - uint32_t value) -{ - putreg32(value, priv->fbase + offset); -} -#endif - -/**************************************************************************** - * Name: stm32can_dumpctrlregs - * - * Description: - * Dump the contents of all CAN control registers - * - * Input Parameters: - * priv - A reference to the CAN block status - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_CAN_REGDEBUG -static void stm32can_dumpctrlregs(struct stm32_can_s *priv, - const char *msg) -{ - if (msg) - { - caninfo("Control Registers: %s\n", msg); - } - else - { - caninfo("Control Registers:\n"); - } - - /* CAN control and status registers */ - - caninfo(" MCR: %08" PRIx32 " MSR: %08" PRIx32 " TSR: %08" PRIx32 "\n", - getreg32(priv->base + STM32_CAN_MCR_OFFSET), - getreg32(priv->base + STM32_CAN_MSR_OFFSET), - getreg32(priv->base + STM32_CAN_TSR_OFFSET)); - - caninfo(" RF0R: %08" PRIx32 " RF1R: %08" PRIx32 "\n", - getreg32(priv->base + STM32_CAN_RF0R_OFFSET), - getreg32(priv->base + STM32_CAN_RF1R_OFFSET)); - - caninfo(" IER: %08" PRIx32 " ESR: %08" PRIx32 " BTR: %08" PRIx32 "\n", - getreg32(priv->base + STM32_CAN_IER_OFFSET), - getreg32(priv->base + STM32_CAN_ESR_OFFSET), - getreg32(priv->base + STM32_CAN_BTR_OFFSET)); -} -#endif - -/**************************************************************************** - * Name: stm32can_dumpmbregs - * - * Description: - * Dump the contents of all CAN mailbox registers - * - * Input Parameters: - * priv - A reference to the CAN block status - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_CAN_REGDEBUG -static void stm32can_dumpmbregs(struct stm32_can_s *priv, - const char *msg) -{ - if (msg) - { - caninfo("Mailbox Registers: %s\n", msg); - } - else - { - caninfo("Mailbox Registers:\n"); - } - - /* CAN mailbox registers (3 TX and 2 RX) */ - - caninfo(" TI0R: %08" PRIx32 " TDT0R: %08" PRIx32 " TDL0R: %08" - PRIx32 " TDH0R: %08" PRIx32 "\n", - getreg32(priv->base + STM32_CAN_TI0R_OFFSET), - getreg32(priv->base + STM32_CAN_TDT0R_OFFSET), - getreg32(priv->base + STM32_CAN_TDL0R_OFFSET), - getreg32(priv->base + STM32_CAN_TDH0R_OFFSET)); - - caninfo(" TI1R: %08" PRIx32 " TDT1R: %08" PRIx32 " TDL1R: %08" - PRIx32 " TDH1R: %08" PRIx32 "\n", - getreg32(priv->base + STM32_CAN_TI1R_OFFSET), - getreg32(priv->base + STM32_CAN_TDT1R_OFFSET), - getreg32(priv->base + STM32_CAN_TDL1R_OFFSET), - getreg32(priv->base + STM32_CAN_TDH1R_OFFSET)); - - caninfo(" TI2R: %08" PRIx32 " TDT2R: %08" PRIx32 " TDL2R: %08" - PRIx32 " TDH2R: %08" PRIx32 "\n", - getreg32(priv->base + STM32_CAN_TI2R_OFFSET), - getreg32(priv->base + STM32_CAN_TDT2R_OFFSET), - getreg32(priv->base + STM32_CAN_TDL2R_OFFSET), - getreg32(priv->base + STM32_CAN_TDH2R_OFFSET)); - - caninfo(" RI0R: %08" PRIx32 " RDT0R: %08" PRIx32 " RDL0R: %08" - PRIx32 " RDH0R: %08" PRIx32 "\n", - getreg32(priv->base + STM32_CAN_RI0R_OFFSET), - getreg32(priv->base + STM32_CAN_RDT0R_OFFSET), - getreg32(priv->base + STM32_CAN_RDL0R_OFFSET), - getreg32(priv->base + STM32_CAN_RDH0R_OFFSET)); - - caninfo(" RI1R: %08" PRIx32 " RDT1R: %08" PRIx32 " RDL1R: %08" - PRIx32 " RDH1R: %08" PRIx32 "\n", - getreg32(priv->base + STM32_CAN_RI1R_OFFSET), - getreg32(priv->base + STM32_CAN_RDT1R_OFFSET), - getreg32(priv->base + STM32_CAN_RDL1R_OFFSET), - getreg32(priv->base + STM32_CAN_RDH1R_OFFSET)); -} -#endif - -/**************************************************************************** - * Name: stm32can_dumpfiltregs - * - * Description: - * Dump the contents of all CAN filter registers - * - * Input Parameters: - * priv - A reference to the CAN block status - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_CAN_REGDEBUG -static void stm32can_dumpfiltregs(struct stm32_can_s *priv, - const char *msg) -{ - int i; - - if (msg) - { - caninfo("Filter Registers: %s\n", msg); - } - else - { - caninfo("Filter Registers:\n"); - } - - caninfo(" FMR: %08" PRIx32 " FM1R: %08" PRIx32 " FS1R: %08" - PRIx32 " FFA1R: %08" PRIx32 " FA1R: %08" PRIx32 "\n", - getreg32(priv->base + STM32_CAN_FMR_OFFSET), - getreg32(priv->base + STM32_CAN_FM1R_OFFSET), - getreg32(priv->base + STM32_CAN_FS1R_OFFSET), - getreg32(priv->base + STM32_CAN_FFA1R_OFFSET), - getreg32(priv->base + STM32_CAN_FA1R_OFFSET)); - - for (i = 0; i < CAN_NFILTERS; i++) - { - caninfo(" F%dR1: %08" PRIx32 " F%dR2: %08" PRIx32 "\n", - i, getreg32(priv->base + STM32_CAN_FIR_OFFSET(i, 1)), - i, getreg32(priv->base + STM32_CAN_FIR_OFFSET(i, 2))); - } -} -#endif - -/**************************************************************************** - * Name: stm32can_reset - * - * Description: - * Reset the CAN device. Called early to initialize the hardware. This - * function is called, before stm32can_setup() and on error conditions. - * - * Input Parameters: - * dev - An instance of the "upper half" can driver state structure. - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void stm32can_reset(struct can_dev_s *dev) -{ - struct stm32_can_s *priv = dev->cd_priv; - uint32_t regval; - uint32_t regbit = 0; - irqstate_t flags; - - caninfo("CAN%" PRIu8 "\n", priv->port); - - /* Get the bits in the AHB1RSTR register needed to reset this CAN device */ - -#ifdef CONFIG_STM32_CAN1 - if (priv->port == 1) - { - regbit = RCC_APB1RSTR_CAN1RST; - } - else -#endif -#ifdef CONFIG_STM32_CAN2 - if (priv->port == 2) - { - regbit = RCC_APB1RSTR_CAN2RST; - } - else -#endif - { - canerr("ERROR: Unsupported port %d\n", priv->port); - return; - } - - /* Disable interrupts momentarily to stop any ongoing CAN event processing - * and to prevent any concurrent access to the AHB1RSTR register. - */ - - flags = enter_critical_section(); - - /* Reset the CAN */ - - regval = getreg32(STM32_RCC_APB1RSTR); - regval |= regbit; - putreg32(regval, STM32_RCC_APB1RSTR); - - regval &= ~regbit; - putreg32(regval, STM32_RCC_APB1RSTR); - leave_critical_section(flags); -} - -/**************************************************************************** - * Name: stm32can_setup - * - * Description: - * Configure the CAN. This method is called the first time that the CAN - * device is opened. This will occur when the port is first opened. - * This setup includes configuring and attaching CAN interrupts. - * All CAN interrupts are disabled upon return. - * - * Input Parameters: - * dev - An instance of the "upper half" can driver state structure. - * - * Returned Value: - * Zero on success; a negated errno on failure - * - ****************************************************************************/ - -static int stm32can_setup(struct can_dev_s *dev) -{ - struct stm32_can_s *priv = dev->cd_priv; - int ret; - -#ifdef CONFIG_CAN_ERRORS - ninfo("CAN%" PRIu8 " RX0 irq: %" PRIu8 " RX1 irq: %" PRIu8 - " TX irq: %" PRIu8 " SCE irq: %" PRIu8 "\n", - priv->port, priv->canrx[0], priv->canrx[1], priv->cantx, - priv->cansce); -#else - ninfo("CAN%" PRIu8 " RX0 irq: %" PRIu8 " RX1 irq: %" PRIu8 - " TX irq: %" PRIu8 "\n", - priv->port, priv->canrx[0], priv->canrx[1], priv->cantx); -#endif - - /* CAN cell initialization */ - - ret = stm32can_cellinit(priv); - if (ret < 0) - { - canerr("ERROR: CAN%" PRId8 " cell initialization failed: %d\n", - priv->port, ret); - return ret; - } - - stm32can_dumpctrlregs(priv, "After cell initialization"); - stm32can_dumpmbregs(priv, NULL); - - /* CAN filter initialization */ - - ret = stm32can_filterinit(priv); - if (ret < 0) - { - canerr("ERROR: CAN%" PRIu8 " filter initialization failed: %d\n", - priv->port, ret); - return ret; - } - - stm32can_dumpfiltregs(priv, "After filter initialization"); - - /* Attach the CAN RX FIFO 0/1 interrupts and TX interrupts. - * The others are not used. - */ - - ret = irq_attach(priv->canrx[0], stm32can_rx0interrupt, dev); - if (ret < 0) - { - canerr("ERROR: Failed to attach CAN%" PRIu8 " RX0 IRQ (%" PRIu8 ")", - priv->port, priv->canrx[0]); - return ret; - } - - ret = irq_attach(priv->canrx[1], stm32can_rx1interrupt, dev); - if (ret < 0) - { - canerr("ERROR: Failed to attach CAN%" PRIu8 " RX1 IRQ (%" PRIu8 ")", - priv->port, priv->canrx[1]); - return ret; - } - - ret = irq_attach(priv->cantx, stm32can_txinterrupt, dev); - if (ret < 0) - { - canerr("ERROR: Failed to attach CAN%" PRIu8 " TX IRQ (%" PRIu8 ")", - priv->port, priv->cantx); - return ret; - } - -#ifdef CONFIG_CAN_ERRORS - ret = irq_attach(priv->cansce, stm32can_sceinterrupt, dev); - if (ret < 0) - { - nerr("ERROR: Failed to attach CAN%" PRIu8 " SCE IRQ (%" PRIu8 ")", - priv->port, priv->cansce); - return ret; - } - - /* Enable CAN error interrupts */ - - stm32can_errint(dev, true); -#endif - - /* Enable the interrupts at the NVIC. Interrupts are still disabled in - * the CAN module. Since we coming out of reset here, there should be - * no pending interrupts. - */ - - up_enable_irq(priv->canrx[0]); - up_enable_irq(priv->canrx[1]); - up_enable_irq(priv->cantx); -#ifdef CONFIG_CAN_ERRORS - up_enable_irq(priv->cansce); -#endif - return OK; -} - -/**************************************************************************** - * Name: stm32can_shutdown - * - * Description: - * Disable the CAN. This method is called when the CAN device is closed. - * This method reverses the operation the setup method. - * - * Input Parameters: - * dev - An instance of the "upper half" can driver state structure. - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void stm32can_shutdown(struct can_dev_s *dev) -{ - struct stm32_can_s *priv = dev->cd_priv; - - caninfo("CAN%" PRIu8 "\n", priv->port); - - /* Disable the RX FIFO 0/1, TX and SCE interrupts */ - - up_disable_irq(priv->canrx[0]); - up_disable_irq(priv->canrx[1]); - up_disable_irq(priv->cantx); -#ifdef CONFIG_CAN_ERRORS - up_disable_irq(priv->cansce); -#endif - - /* Detach the RX FIFO 0/1, TX and SCE interrupts */ - - irq_detach(priv->canrx[0]); - irq_detach(priv->canrx[1]); - irq_detach(priv->cantx); -#ifdef CONFIG_CAN_ERRORS - irq_detach(priv->cansce); -#endif - - /* And reset the hardware */ - - stm32can_reset(dev); -} - -/**************************************************************************** - * Name: stm32can_rxint - * - * Description: - * Call to enable or disable RX interrupts. - * - * Input Parameters: - * dev - An instance of the "upper half" can driver state structure. - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void stm32can_rxint(struct can_dev_s *dev, bool enable) -{ - struct stm32_can_s *priv = dev->cd_priv; - uint32_t regval; - - caninfo("CAN%" PRIu8 " rxint enable: %d\n", priv->port, enable); - - /* Enable/disable the FIFO 0/1 message pending interrupt */ - - regval = stm32can_getreg(priv, STM32_CAN_IER_OFFSET); - if (enable) - { - regval |= CAN_IER_FMPIE0 | CAN_IER_FMPIE1; - } - else - { - regval &= ~(CAN_IER_FMPIE0 | CAN_IER_FMPIE1); - } - - stm32can_putreg(priv, STM32_CAN_IER_OFFSET, regval); -} - -/**************************************************************************** - * Name: stm32can_txint - * - * Description: - * Call to enable or disable TX interrupts. - * - * Input Parameters: - * dev - An instance of the "upper half" can driver state structure. - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void stm32can_txint(struct can_dev_s *dev, bool enable) -{ - struct stm32_can_s *priv = dev->cd_priv; - uint32_t regval; - - caninfo("CAN%" PRIu8 " txint enable: %d\n", priv->port, enable); - - /* Support only disabling the transmit mailbox interrupt */ - - if (!enable) - { - regval = stm32can_getreg(priv, STM32_CAN_IER_OFFSET); - regval &= ~CAN_IER_TMEIE; - stm32can_putreg(priv, STM32_CAN_IER_OFFSET, regval); - } -} - -#ifdef CONFIG_CAN_ERRORS -/**************************************************************************** - * Name: stm32can_errint - * - * Description: - * Call to enable or disable CAN error interrupts. - * - * Input Parameters: - * dev - An instance of the "upper half" can driver state structure. - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void stm32can_errint(struct can_dev_s *dev, bool enable) -{ - struct stm32_can_s *priv = dev->cd_priv; - uint32_t regval = 0; - - caninfo("CAN%" PRIu8 " errint enable: %d\n", priv->port, enable); - - /* Enable/disable the transmit mailbox interrupt */ - - regval = stm32can_getreg(priv, STM32_CAN_IER_OFFSET); - if (enable) - { - regval |= STM32_CAN_ERRINT; - } - else - { - regval &= ~STM32_CAN_ERRINT; - } - - stm32can_putreg(priv, STM32_CAN_IER_OFFSET, regval); -} -#endif - -/**************************************************************************** - * Name: stm32can_ioctl - * - * Description: - * All ioctl calls will be routed through this method - * - * Input Parameters: - * dev - An instance of the "upper half" can driver state structure. - * - * Returned Value: - * Zero on success; a negated errno on failure - * - ****************************************************************************/ - -static int stm32can_ioctl(struct can_dev_s *dev, int cmd, - unsigned long arg) -{ - struct stm32_can_s *priv; - int ret = -ENOTTY; - - caninfo("cmd=%04x arg=%lu\n", cmd, arg); - - DEBUGASSERT(dev && dev->cd_priv); - priv = dev->cd_priv; - - /* Handle the command */ - - switch (cmd) - { - /* CANIOC_GET_BITTIMING: - * Description: Return the current bit timing settings - * Argument: A pointer to a write-able instance of struct - * canioc_bittiming_s in which current bit timing - * values will be returned. - * Returned Value: Zero (OK) is returned on success. Otherwise -1 - * (ERROR) is returned with the errno variable set - * to indicate the nature of the error. - * Dependencies: None - */ - - case CANIOC_GET_BITTIMING: - { - struct canioc_bittiming_s *bt = - (struct canioc_bittiming_s *)arg; - uint32_t regval; - uint32_t brp; - - DEBUGASSERT(bt != NULL); - regval = stm32can_getreg(priv, STM32_CAN_BTR_OFFSET); - bt->bt_sjw = ((regval & CAN_BTR_SJW_MASK) >> - CAN_BTR_SJW_SHIFT) + 1; - bt->bt_tseg1 = ((regval & CAN_BTR_TS1_MASK) >> - CAN_BTR_TS1_SHIFT) + 1; - bt->bt_tseg2 = ((regval & CAN_BTR_TS2_MASK) >> - CAN_BTR_TS2_SHIFT) + 1; - - brp = ((regval & CAN_BTR_BRP_MASK) >> - CAN_BTR_BRP_SHIFT) + 1; - bt->bt_baud = STM32_PCLK1_FREQUENCY / - (brp * (bt->bt_tseg1 + bt->bt_tseg2 + 1)); - ret = OK; - } - break; - - /* CANIOC_SET_BITTIMING: - * Description: Set new current bit timing values - * Argument: A pointer to a read-able instance of struct - * canioc_bittiming_s in which the new bit timing - * values are provided. - * Returned Value: Zero (OK) is returned on success. Otherwise -1 - * (ERROR)is returned with the errno variable set - * to indicate thenature of the error. - * Dependencies: None - * - * REVISIT: There is probably a limitation here: If there are - * multiple threads trying to send CAN packets, when one of these - * threads reconfigures the bitrate, the MCAN hardware will be reset - * and the context of operation will be lost. Hence, this IOCTL can - * only safely be executed in quiescent time periods. - */ - - case CANIOC_SET_BITTIMING: - { - const struct canioc_bittiming_s *bt = - (const struct canioc_bittiming_s *)arg; - uint32_t brp; - uint32_t can_bit_quanta; - uint32_t tmp; - uint32_t regval; - - DEBUGASSERT(bt != NULL); - DEBUGASSERT(bt->bt_baud < STM32_PCLK1_FREQUENCY); - DEBUGASSERT(bt->bt_sjw > 0 && bt->bt_sjw <= 4); - DEBUGASSERT(bt->bt_tseg1 > 0 && bt->bt_tseg1 <= 16); - DEBUGASSERT(bt->bt_tseg2 > 0 && bt->bt_tseg2 <= 8); - - regval = stm32can_getreg(priv, STM32_CAN_BTR_OFFSET); - - /* Extract bit timing data - * tmp is in clocks per bit time - */ - - tmp = STM32_PCLK1_FREQUENCY / bt->bt_baud; - - /* This value is dynamic as requested by user */ - - can_bit_quanta = bt->bt_tseg1 + bt->bt_tseg2 + 1; - - if (tmp < can_bit_quanta) - { - /* This timing is not possible */ - - ret = -EINVAL; - break; - } - - /* Otherwise, nquanta is can_bit_quanta, ts1 and ts2 are - * provided by the user and we calculate brp to achieve - * can_bit_quanta quanta in the bit times - */ - - else - { - brp = (tmp + (can_bit_quanta / 2)) / can_bit_quanta; - DEBUGASSERT(brp >= 1 && brp <= CAN_BTR_BRP_MAX); - } - - caninfo("TS1: %"PRIu8 " TS2: %" PRIu8 " BRP: %" PRIu32 "\n", - bt->bt_tseg1, bt->bt_tseg2, brp); - - /* Configure bit timing. */ - - regval &= ~(CAN_BTR_BRP_MASK | CAN_BTR_TS1_MASK | - CAN_BTR_TS2_MASK | CAN_BTR_SJW_MASK); - regval |= ((brp - 1) << CAN_BTR_BRP_SHIFT) | - ((bt->bt_tseg1 - 1) << CAN_BTR_TS1_SHIFT) | - ((bt->bt_tseg2 - 1) << CAN_BTR_TS2_SHIFT) | - ((bt->bt_sjw - 1) << CAN_BTR_SJW_SHIFT); - - /* Bit timing can only be configured in init mode. */ - - ret = stm32can_enterinitmode(priv); - if (ret < 0) - { - break; - } - - stm32can_putreg(priv, STM32_CAN_BTR_OFFSET, regval); - - ret = stm32can_exitinitmode(priv); - if (ret >= 0) - { - priv->baud = STM32_PCLK1_FREQUENCY / - (brp * (bt->bt_tseg1 + bt->bt_tseg2 + 1)); - } - } - break; - - /* CANIOC_GET_CONNMODES: - * Description: Get the current bus connection modes - * Argument: A pointer to a write-able instance of struct - * canioc_connmodes_s in which the new bus modes will - * be returned. - * Returned Value: Zero (OK) is returned on success. Otherwise -1 - * (ERROR)is returned with the errno variable set - * to indicate the nature of the error. - * Dependencies: None - */ - - case CANIOC_GET_CONNMODES: - { - struct canioc_connmodes_s *bm = - (struct canioc_connmodes_s *)arg; - uint32_t regval; - - DEBUGASSERT(bm != NULL); - - regval = stm32can_getreg(priv, STM32_CAN_BTR_OFFSET); - - bm->bm_loopback = ((regval & CAN_BTR_LBKM) == CAN_BTR_LBKM); - bm->bm_silent = ((regval & CAN_BTR_SILM) == CAN_BTR_SILM); - ret = OK; - break; - } - - /* CANIOC_SET_CONNMODES: - * Description: Set new bus connection modes values - * Argument: A pointer to a read-able instance of struct - * canioc_connmodes_s in which the new bus modes - * are provided. - * Returned Value: Zero (OK) is returned on success. Otherwise -1 - * (ERROR) is returned with the errno variable set - * to indicate the nature of the error. - * Dependencies: None - */ - - case CANIOC_SET_CONNMODES: - { - struct canioc_connmodes_s *bm = - (struct canioc_connmodes_s *)arg; - uint32_t regval; - - DEBUGASSERT(bm != NULL); - - regval = stm32can_getreg(priv, STM32_CAN_BTR_OFFSET); - - if (bm->bm_loopback) - { - regval |= CAN_BTR_LBKM; - } - else - { - regval &= ~CAN_BTR_LBKM; - } - - if (bm->bm_silent) - { - regval |= CAN_BTR_SILM; - } - else - { - regval &= ~CAN_BTR_SILM; - } - - /* This register can only be configured in init mode. */ - - ret = stm32can_enterinitmode(priv); - if (ret < 0) - { - break; - } - - stm32can_putreg(priv, STM32_CAN_BTR_OFFSET, regval); - - ret = stm32can_exitinitmode(priv); - } - break; - -#ifdef CONFIG_CAN_EXTID - /* CANIOC_ADD_EXTFILTER: - * Description: Add an address filter for a extended 29 bit - * address. - * Argument: A reference to struct canioc_extfilter_s - * Returned Value: A non-negative filter ID is returned on success. - * Otherwise -1 (ERROR) is returned with the errno - * variable set to indicate the nature of the error. - */ - - case CANIOC_ADD_EXTFILTER: - { - DEBUGASSERT(arg != 0); - ret = stm32can_addextfilter(priv, - (struct canioc_extfilter_s *)arg); - } - break; - - /* CANIOC_DEL_EXTFILTER: - * Description: Remove an address filter for a standard 29 bit - * address. - * Argument: The filter index previously returned by the - * CANIOC_ADD_EXTFILTER command - * Returned Value: Zero (OK) is returned on success. Otherwise -1 - * (ERROR)is returned with the errno variable set - * to indicate the nature of the error. - */ - - case CANIOC_DEL_EXTFILTER: - { -#if 0 /* Unimplemented */ - DEBUGASSERT(arg <= priv->config->nextfilters); -#endif - ret = stm32can_delextfilter(priv, (int)arg); - } - break; -#endif - - /* CANIOC_ADD_STDFILTER: - * Description: Add an address filter for a standard 11 bit - * address. - * Argument: A reference to struct canioc_stdfilter_s - * Returned Value: A non-negative filter ID is returned on success. - * Otherwise -1 (ERROR) is returned with the errno - * variable set to indicate the nature of the error. - */ - - case CANIOC_ADD_STDFILTER: - { - DEBUGASSERT(arg != 0); - ret = stm32can_addstdfilter(priv, - (struct canioc_stdfilter_s *)arg); - } - break; - - /* CANIOC_DEL_STDFILTER: - * Description: Remove an address filter for a standard 11 bit - * address. - * Argument: The filter index previously returned by the - * CANIOC_ADD_STDFILTER command - * Returned Value: Zero (OK) is returned on success. Otherwise -1 - * (ERROR) is returned with the errno variable set - * to indicate the nature of the error. - */ - - case CANIOC_DEL_STDFILTER: - { -#if 0 /* Unimplemented */ - DEBUGASSERT(arg <= priv->config->nstdfilters); -#endif - ret = stm32can_delstdfilter(priv, (int)arg); - } - break; - - case CANIOC_SET_NART: - { - uint32_t regval; - - ret = stm32can_enterinitmode(priv); - if (ret != 0) - { - return ret; - } - - regval = stm32can_getreg(priv, STM32_CAN_MCR_OFFSET); - if (arg == 1) - { - regval |= CAN_MCR_NART; - } - else - { - regval &= ~CAN_MCR_NART; - } - - stm32can_putreg(priv, STM32_CAN_MCR_OFFSET, regval); - return stm32can_exitinitmode(priv); - } - break; - - case CANIOC_SET_ABOM: - { - uint32_t regval; - - ret = stm32can_enterinitmode(priv); - if (ret != 0) - { - return ret; - } - - regval = stm32can_getreg(priv, STM32_CAN_MCR_OFFSET); - if (arg == 1) - { - regval |= CAN_MCR_ABOM; - } - else - { - regval &= ~CAN_MCR_ABOM; - } - - stm32can_putreg(priv, STM32_CAN_MCR_OFFSET, regval); - return stm32can_exitinitmode(priv); - } - break; - - /* Unsupported/unrecognized command */ - - default: - canerr("ERROR: Unrecognized command: %04x\n", cmd); - break; - } - - return ret; -} - -/**************************************************************************** - * Name: stm32can_remoterequest - * - * Description: - * Send a remote request - * - * Input Parameters: - * dev - An instance of the "upper half" can driver state structure. - * - * Returned Value: - * Zero on success; a negated errno on failure - * - ****************************************************************************/ - -static int stm32can_remoterequest(struct can_dev_s *dev, uint16_t id) -{ -#warning "Remote request not implemented" - return -ENOSYS; -} - -/**************************************************************************** - * Name: stm32can_send - * - * Description: - * Send one can message. - * - * One CAN-message consists of a maximum of 10 bytes. A message is - * composed of at least the first 2 bytes (when there are no data bytes). - * - * Byte 0: Bits 0-7: Bits 3-10 of the 11-bit CAN identifier - * Byte 1: Bits 5-7: Bits 0-2 of the 11-bit CAN identifier - * Bit 4: Remote Transmission Request (RTR) - * Bits 0-3: Data Length Code (DLC) - * Bytes 2-10: CAN data - * - * Input Parameters: - * dev - An instance of the "upper half" can driver state structure. - * - * Returned Value: - * Zero on success; a negated errno on failure - * - ****************************************************************************/ - -static int stm32can_send(struct can_dev_s *dev, - struct can_msg_s *msg) -{ - struct stm32_can_s *priv = dev->cd_priv; - uint8_t *ptr; - uint32_t regval; - uint32_t tmp; - int dlc; - int txmb; - - caninfo("CAN%" PRIu8 " ID: %" PRIu32 " DLC: %" PRIu8 "\n", - priv->port, (uint32_t)msg->cm_hdr.ch_id, msg->cm_hdr.ch_dlc); - - /* Select one empty transmit mailbox */ - - regval = stm32can_getreg(priv, STM32_CAN_TSR_OFFSET); - if (stm32can_txmb0empty(regval)) - { - txmb = 0; - } - else if (stm32can_txmb1empty(regval)) - { - txmb = 1; - } - else if (stm32can_txmb2empty(regval)) - { - txmb = 2; - } - else - { - canerr("ERROR: No available mailbox\n"); - return -EBUSY; - } - - /* Clear TXRQ, RTR, IDE, EXID, and STID fields */ - - regval = stm32can_getreg(priv, STM32_CAN_TIR_OFFSET(txmb)); - regval &= ~(CAN_TIR_TXRQ | CAN_TIR_RTR | CAN_TIR_IDE | - CAN_TIR_EXID_MASK | CAN_TIR_STID_MASK); - stm32can_putreg(priv, STM32_CAN_TIR_OFFSET(txmb), regval); - - /* Set up the ID, standard 11-bit or extended 29-bit. */ - -#ifdef CONFIG_CAN_EXTID - regval &= ~CAN_TIR_EXID_MASK; - if (msg->cm_hdr.ch_extid) - { - DEBUGASSERT(msg->cm_hdr.ch_id < (1 << 29)); - regval |= (msg->cm_hdr.ch_id << CAN_TIR_EXID_SHIFT) | CAN_TIR_IDE; - } - else - { - DEBUGASSERT(msg->cm_hdr.ch_id < (1 << 11)); - regval |= msg->cm_hdr.ch_id << CAN_TIR_STID_SHIFT; - } - -#else - regval |= (((uint32_t) msg->cm_hdr.ch_id << CAN_TIR_STID_SHIFT) & - CAN_TIR_STID_MASK); - -#endif - -#ifdef CONFIG_CAN_USE_RTR - regval |= (msg->cm_hdr.ch_rtr ? CAN_TIR_RTR : 0); -#endif - - stm32can_putreg(priv, STM32_CAN_TIR_OFFSET(txmb), regval); - - /* Set up the DLC */ - - dlc = msg->cm_hdr.ch_dlc; - regval = stm32can_getreg(priv, STM32_CAN_TDTR_OFFSET(txmb)); - regval &= ~(CAN_TDTR_DLC_MASK | CAN_TDTR_TGT); - regval |= (uint32_t)dlc << CAN_TDTR_DLC_SHIFT; - stm32can_putreg(priv, STM32_CAN_TDTR_OFFSET(txmb), regval); - - /* Set up the data fields */ - - ptr = msg->cm_data; - regval = 0; - - if (dlc > 0) - { - tmp = (uint32_t)*ptr++; - regval = tmp << CAN_TDLR_DATA0_SHIFT; - - if (dlc > 1) - { - tmp = (uint32_t)*ptr++; - regval |= tmp << CAN_TDLR_DATA1_SHIFT; - - if (dlc > 2) - { - tmp = (uint32_t)*ptr++; - regval |= tmp << CAN_TDLR_DATA2_SHIFT; - - if (dlc > 3) - { - tmp = (uint32_t)*ptr++; - regval |= tmp << CAN_TDLR_DATA3_SHIFT; - } - } - } - } - - stm32can_putreg(priv, STM32_CAN_TDLR_OFFSET(txmb), regval); - - regval = 0; - if (dlc > 4) - { - tmp = (uint32_t)*ptr++; - regval = tmp << CAN_TDHR_DATA4_SHIFT; - - if (dlc > 5) - { - tmp = (uint32_t)*ptr++; - regval |= tmp << CAN_TDHR_DATA5_SHIFT; - - if (dlc > 6) - { - tmp = (uint32_t)*ptr++; - regval |= tmp << CAN_TDHR_DATA6_SHIFT; - - if (dlc > 7) - { - tmp = (uint32_t)*ptr++; - regval |= tmp << CAN_TDHR_DATA7_SHIFT; - } - } - } - } - - stm32can_putreg(priv, STM32_CAN_TDHR_OFFSET(txmb), regval); - - /* Enable the transmit mailbox empty interrupt (may already be enabled) */ - - regval = stm32can_getreg(priv, STM32_CAN_IER_OFFSET); - regval |= CAN_IER_TMEIE; - stm32can_putreg(priv, STM32_CAN_IER_OFFSET, regval); - - /* Request transmission */ - - regval = stm32can_getreg(priv, STM32_CAN_TIR_OFFSET(txmb)); - regval |= CAN_TIR_TXRQ; /* Transmit Mailbox Request */ - stm32can_putreg(priv, STM32_CAN_TIR_OFFSET(txmb), regval); - - stm32can_dumpmbregs(priv, "After send"); - return OK; -} - -/**************************************************************************** - * Name: stm32can_txready - * - * Description: - * Return true if the CAN hardware can accept another TX message. - * - * Input Parameters: - * dev - An instance of the "upper half" can driver state structure. - * - * Returned Value: - * True if the CAN hardware is ready to accept another TX message. - * - ****************************************************************************/ - -static bool stm32can_txready(struct can_dev_s *dev) -{ - struct stm32_can_s *priv = dev->cd_priv; - uint32_t regval; - - /* Return true if any mailbox is available */ - - regval = stm32can_getreg(priv, STM32_CAN_TSR_OFFSET); - caninfo("CAN%" PRIu8 " TSR: %08" PRIx32 "\n", priv->port, regval); - - return stm32can_txmb0empty(regval) || stm32can_txmb1empty(regval) || - stm32can_txmb2empty(regval); -} - -/**************************************************************************** - * Name: stm32can_txempty - * - * Description: - * Return true if all message have been sent. If for example, the CAN - * hardware implements FIFOs, then this would mean the transmit FIFO is - * empty. This method is called when the driver needs to make sure that - * all characters are "drained" from the TX hardware before calling - * co_shutdown(). - * - * Input Parameters: - * dev - An instance of the "upper half" can driver state structure. - * - * Returned Value: - * True if there are no pending TX transfers in the CAN hardware. - * - ****************************************************************************/ - -static bool stm32can_txempty(struct can_dev_s *dev) -{ - struct stm32_can_s *priv = dev->cd_priv; - uint32_t regval; - - /* Return true if all mailboxes are available */ - - regval = stm32can_getreg(priv, STM32_CAN_TSR_OFFSET); - caninfo("CAN%" PRIu8 " TSR: %08" PRIx32 "\n", priv->port, regval); - - return stm32can_txmb0empty(regval) && stm32can_txmb1empty(regval) && - stm32can_txmb2empty(regval); -} - -/**************************************************************************** - * Name: stm32can_rxinterrupt - * - * Description: - * CAN RX FIFO 0/1 interrupt handler - * - * Input Parameters: - * irq - The IRQ number of the interrupt. - * context - The register state save array at the time of the interrupt. - * rxmb - The RX mailbox number. - * - * Returned Value: - * Zero on success; a negated errno on failure - * - ****************************************************************************/ - -static int stm32can_rxinterrupt(struct can_dev_s *dev, int rxmb) -{ - struct stm32_can_s *priv; - struct can_hdr_s hdr; - uint8_t data[CAN_MAXDATALEN]; - uint32_t regval; - int npending; - int ret; - - DEBUGASSERT(dev != NULL && dev->cd_priv != NULL); - priv = dev->cd_priv; - - /* Verify that a message is pending in the FIFO */ - - regval = stm32can_getreg(priv, STM32_CAN_RFR_OFFSET(rxmb)); - npending = (regval & CAN_RFR_FMP_MASK) >> CAN_RFR_FMP_SHIFT; - if (npending < 1) - { - canwarn("WARNING: No messages pending\n"); - return OK; - } - - if (rxmb == 0) - { - stm32can_dumpmbregs(priv, "RX0 interrupt"); - } - else - { - stm32can_dumpmbregs(priv, "RX1 interrupt"); - } - - /* Get the CAN identifier. */ - - regval = stm32can_getreg(priv, STM32_CAN_RIR_OFFSET(rxmb)); - -#ifdef CONFIG_CAN_EXTID - if ((regval & CAN_RIR_IDE) != 0) - { - hdr.ch_id = (regval & CAN_RIR_EXID_MASK) >> CAN_RIR_EXID_SHIFT; - hdr.ch_extid = true; - } - else - { - hdr.ch_id = (regval & CAN_RIR_STID_MASK) >> CAN_RIR_STID_SHIFT; - hdr.ch_extid = false; - } -#else - if ((regval & CAN_RIR_IDE) != 0) - { - canerr("ERROR: Received message with extended identifier. Dropped\n"); - ret = -ENOSYS; - goto errout; - } - - hdr.ch_id = (regval & CAN_RIR_STID_MASK) >> CAN_RIR_STID_SHIFT; -#endif - - /* Clear the error indication and unused bits */ - -#ifdef CONFIG_CAN_ERRORS - hdr.ch_error = 0; /* Error reporting not supported */ -#endif - hdr.ch_tcf = 0; - - /* Extract the RTR bit */ - - hdr.ch_rtr = (regval & CAN_RIR_RTR) != 0; - - /* Get the DLC */ - - regval = stm32can_getreg(priv, STM32_CAN_RDTR_OFFSET(rxmb)); - hdr.ch_dlc = (regval & CAN_RDTR_DLC_MASK) >> CAN_RDTR_DLC_SHIFT; - - /* Save the message data */ - - regval = stm32can_getreg(priv, STM32_CAN_RDLR_OFFSET(rxmb)); - data[0] = (regval & CAN_RDLR_DATA0_MASK) >> CAN_RDLR_DATA0_SHIFT; - data[1] = (regval & CAN_RDLR_DATA1_MASK) >> CAN_RDLR_DATA1_SHIFT; - data[2] = (regval & CAN_RDLR_DATA2_MASK) >> CAN_RDLR_DATA2_SHIFT; - data[3] = (regval & CAN_RDLR_DATA3_MASK) >> CAN_RDLR_DATA3_SHIFT; - - regval = stm32can_getreg(priv, STM32_CAN_RDHR_OFFSET(rxmb)); - data[4] = (regval & CAN_RDHR_DATA4_MASK) >> CAN_RDHR_DATA4_SHIFT; - data[5] = (regval & CAN_RDHR_DATA5_MASK) >> CAN_RDHR_DATA5_SHIFT; - data[6] = (regval & CAN_RDHR_DATA6_MASK) >> CAN_RDHR_DATA6_SHIFT; - data[7] = (regval & CAN_RDHR_DATA7_MASK) >> CAN_RDHR_DATA7_SHIFT; - - /* Provide the data to the upper half driver */ - - ret = can_receive(dev, &hdr, data); - - /* Release the FIFO */ - -#ifndef CONFIG_CAN_EXTID -errout: -#endif - regval = stm32can_getreg(priv, STM32_CAN_RFR_OFFSET(rxmb)); - regval |= CAN_RFR_RFOM; - stm32can_putreg(priv, STM32_CAN_RFR_OFFSET(rxmb), regval); - return ret; -} - -/**************************************************************************** - * Name: stm32can_rx0interrupt - * - * Description: - * CAN RX FIFO 0 interrupt handler - * - * Input Parameters: - * irq - The IRQ number of the interrupt. - * context - The register state save array at the time of the interrupt. - * - * Returned Value: - * Zero on success; a negated errno on failure - * - ****************************************************************************/ - -static int stm32can_rx0interrupt(int irq, void *context, void *arg) -{ - struct can_dev_s *dev = (struct can_dev_s *)arg; - return stm32can_rxinterrupt(dev, 0); -} - -/**************************************************************************** - * Name: stm32can_rx1interrupt - * - * Description: - * CAN RX FIFO 1 interrupt handler - * - * Input Parameters: - * irq - The IRQ number of the interrupt. - * context - The register state save array at the time of the interrupt. - * - * Returned Value: - * Zero on success; a negated errno on failure - * - ****************************************************************************/ - -static int stm32can_rx1interrupt(int irq, void *context, void *arg) -{ - struct can_dev_s *dev = (struct can_dev_s *)arg; - return stm32can_rxinterrupt(dev, 1); -} - -/**************************************************************************** - * Name: stm32can_txinterrupt - * - * Description: - * CAN TX mailbox complete interrupt handler - * - * Input Parameters: - * irq - The IRQ number of the interrupt. - * context - The register state save array at the time of the interrupt. - * - * Returned Value: - * Zero on success; a negated errno on failure - * - ****************************************************************************/ - -static int stm32can_txinterrupt(int irq, void *context, void *arg) -{ - struct can_dev_s *dev = (struct can_dev_s *)arg; - struct stm32_can_s *priv; - uint32_t regval; - - DEBUGASSERT(dev != NULL && dev->cd_priv != NULL); - priv = dev->cd_priv; - - /* Get the transmit status */ - - regval = stm32can_getreg(priv, STM32_CAN_TSR_OFFSET); - - /* Check for RQCP0: Request completed mailbox 0 */ - - if ((regval & CAN_TSR_RQCP0) != 0) - { - /* Writing '1' to RCP0 clears RCP0 and all the status bits (TXOK0, - * ALST0 and TERR0) for Mailbox 0. - */ - - stm32can_putreg(priv, STM32_CAN_TSR_OFFSET, CAN_TSR_RQCP0); - - /* Tell the upper half that the transfer is finished. */ - - can_txdone(dev); - } - - /* Check for RQCP1: Request completed mailbox 1 */ - - if ((regval & CAN_TSR_RQCP1) != 0) - { - /* Writing '1' to RCP1 clears RCP1 and all the status bits (TXOK1, - * ALST1 and TERR1) for Mailbox 1. - */ - - stm32can_putreg(priv, STM32_CAN_TSR_OFFSET, CAN_TSR_RQCP1); - - /* Tell the upper half that the transfer is finished. */ - - can_txdone(dev); - } - - /* Check for RQCP2: Request completed mailbox 2 */ - - if ((regval & CAN_TSR_RQCP2) != 0) - { - /* Writing '1' to RCP2 clears RCP2 and all the status bits (TXOK2, - * ALST2 and TERR2) for Mailbox 2. - */ - - stm32can_putreg(priv, STM32_CAN_TSR_OFFSET, CAN_TSR_RQCP2); - - /* Tell the upper half that the transfer is finished. */ - - can_txdone(dev); - } - - return OK; -} - -#ifdef CONFIG_CAN_ERRORS -/**************************************************************************** - * Name: stm32can_sceinterrupt - * - * Description: - * CAN status change interrupt handler - * - * Input Parameters: - * irq - The IRQ number of the interrupt. - * context - The register state save array at the time of the interrupt. - * - * Returned Value: - * Zero on success; a negated errno on failure - * - ****************************************************************************/ - -static int stm32can_sceinterrupt(int irq, void *context, void *arg) -{ - struct can_dev_s *dev = (struct can_dev_s *)arg; - struct stm32_can_s *priv = NULL; - struct can_hdr_s hdr; - uint32_t regval = 0; - uint16_t errbits = 0; - uint8_t data[CAN_ERROR_DLC]; - int ret = OK; - - DEBUGASSERT(dev != NULL && dev->cd_priv != NULL); - priv = dev->cd_priv; - - /* Check Error Interrupt flag */ - - regval = stm32can_getreg(priv, STM32_CAN_MSR_OFFSET); - if (regval & CAN_MSR_ERRI) - { - /* Encode error bits */ - - errbits = 0; - memset(data, 0, sizeof(data)); - - /* Get Error statur register */ - - regval = stm32can_getreg(priv, STM32_CAN_ESR_OFFSET); - - if (regval & CAN_ESR_EWGF) - { - /* Error warning flag */ - - data[1] |= (CAN_ERROR1_RXWARNING | CAN_ERROR1_TXWARNING); - errbits |= CAN_ERROR_CONTROLLER; - } - - if (regval & CAN_ESR_EPVF) - { - /* Error passive flag */ - - data[1] |= (CAN_ERROR1_RXPASSIVE | CAN_ERROR1_TXPASSIVE); - errbits |= CAN_ERROR_CONTROLLER; - } - - if (regval & CAN_ESR_BOFF) - { - /* Bus-off flag */ - - errbits |= CAN_ERROR_BUSOFF; - } - - /* Last error code */ - - if (regval & CAN_ESR_LEC_MASK) - { - if (regval & CAN_ESR_STUFFERROR) - { - /* Stuff Error */ - - errbits |= CAN_ERROR_PROTOCOL; - data[2] |= CAN_ERROR2_STUFF; - } - else if (regval & CAN_ESR_FORMERROR) - { - /* Format Error */ - - errbits |= CAN_ERROR_PROTOCOL; - data[2] |= CAN_ERROR2_FORM; - } - else if (regval & CAN_ESR_ACKERROR) - { - /* Acknowledge Error */ - - errbits |= CAN_ERROR_NOACK; - } - else if (regval & CAN_ESR_BRECERROR) - { - /* Bit recessive Error */ - - errbits |= CAN_ERROR_PROTOCOL; - data[2] |= CAN_ERROR2_BIT1; - } - else if (regval & CAN_ESR_BDOMERROR) - { - /* Bit dominant Error */ - - errbits |= CAN_ERROR_PROTOCOL; - data[2] |= CAN_ERROR2_BIT0; - } - else if (regval & CAN_ESR_CRCERRPR) - { - /* Receive CRC Error */ - - errbits |= CAN_ERROR_PROTOCOL; - data[3] |= CAN_ERROR3_CRCSEQ; - } - } - - /* Get transmit status register */ - - regval = stm32can_getreg(priv, STM32_CAN_TSR_OFFSET); - - if (regval & CAN_TSR_ALST0 || regval & CAN_TSR_ALST1 || - regval & CAN_TSR_ALST2) - { - /* Lost arbitration Error */ - - errbits |= CAN_ERROR_LOSTARB; - } - - /* Clear TSR register */ - - stm32can_putreg(priv, STM32_CAN_TSR_OFFSET, regval); - - /* Clear ERRI flag */ - - stm32can_putreg(priv, STM32_CAN_MSR_OFFSET, CAN_MSR_ERRI); - } - - /* TODO: RX overflow and TX overflow */ - - /* Report a CAN error */ - - if (errbits != 0) - { - canerr("ERROR: errbits = %08" PRIx16 "\n", errbits); - - /* Format the CAN header for the error report. */ - - hdr.ch_id = errbits; - hdr.ch_dlc = CAN_ERROR_DLC; - hdr.ch_rtr = 0; - hdr.ch_error = 1; -#ifdef CONFIG_CAN_EXTID - hdr.ch_extid = 0; -#endif - hdr.ch_tcf = 0; - - /* And provide the error report to the upper half logic */ - - ret = can_receive(dev, &hdr, data); - if (ret < 0) - { - canerr("ERROR: can_receive failed: %d\n", ret); - } - } - - return ret; -} -#endif - -/**************************************************************************** - * Name: stm32can_bittiming - * - * Description: - * Set the CAN bit timing register (BTR) based on the configured BAUD. - * - * "The bit timing logic monitors the serial bus-line and performs sampling - * and adjustment of the sample point by synchronizing on the start-bit edge - * and resynchronizing on the following edges. - * - * "Its operation may be explained simply by splitting nominal bit time into - * three segments as follows: - * - * 1. "Synchronization segment (SYNC_SEG): a bit change is expected to occur - * within this time segment. It has a fixed length of one time quantum - * (1 x tCAN). - * 2. "Bit segment 1 (BS1): defines the location of the sample point. It - * includes the PROP_SEG and PHASE_SEG1 of the CAN standard. Its duration - * is programmable between 1 and 16 time quanta but may be automatically - * lengthened to compensate for positive phase drifts due to differences - * in the frequency of the various nodes of the network. - * 3. "Bit segment 2 (BS2): defines the location of the transmit point. It - * represents the PHASE_SEG2 of the CAN standard. Its duration is - * programmable between 1 and 8 time quanta but may also be automatically - * shortened to compensate for negative phase drifts." - * - * Pictorially: - * - * |<----------------- NOMINAL BIT TIME ----------------->| - * |<- SYNC_SEG ->|<------ BS1 ------>|<------ BS2 ------>| - * |<---- Tq ---->|<----- Tbs1 ------>|<----- Tbs2 ------>| - * - * Where - * Tbs1 is the duration of the BS1 segment - * Tbs2 is the duration of the BS2 segment - * Tq is the "Time Quantum" - * - * Relationships: - * - * baud = 1 / bit_time - * bit_time = Tq + Tbs1 + Tbs2 - * Tbs1 = Tq * ts1 - * Tbs2 = Tq * ts2 - * Tq = brp * Tpclk1 - * baud = Fpclk1 / (brp * (1 + ts1 + ts2)) - * - * Where: - * Tpclk1 is the period of the APB1 clock (PCLK1). - * - * Input Parameters: - * priv - A reference to the CAN block status - * - * Returned Value: - * Zero on success; a negated errno on failure - * - ****************************************************************************/ - -static int stm32can_bittiming(struct stm32_can_s *priv) -{ - uint32_t tmp; - uint32_t brp; - uint32_t ts1; - uint32_t ts2; - - caninfo("CAN%" PRIu8 " PCLK1: %lu baud: %" PRIu32 "\n", - priv->port, (unsigned long) STM32_PCLK1_FREQUENCY, priv->baud); - - /* Try to get CAN_BIT_QUANTA quanta in one bit_time. - * - * bit_time = Tq*(ts1 + ts2 + 1) - * nquanta = bit_time / Tq - * nquanta = (ts1 + ts2 + 1) - * - * bit_time = brp * Tpclk1 * (ts1 + ts2 + 1) - * nquanta = bit_time / brp / Tpclk1 - * = PCLK1 / baud / brp - * brp = PCLK1 / baud / nquanta; - * - * Example: - * PCLK1 = 42,000,000 baud = 1,000,000 nquanta = 14 : brp = 3 - * PCLK1 = 42,000,000 baud = 700,000 nquanta = 14 : brp = 4 - */ - - tmp = STM32_PCLK1_FREQUENCY / priv->baud; - if (tmp < CAN_BIT_QUANTA) - { - /* At the smallest brp value (1), there are already too few bit times - * (PCLCK1 / baud) to meet our goal. brp must be one and we need - * make some reasonable guesses about ts1 and ts2. - */ - - brp = 1; - - /* In this case, we have to guess a good value for ts1 and ts2 */ - - ts1 = (tmp - 1) >> 1; - ts2 = tmp - ts1 - 1; - if (ts1 == ts2 && ts1 > 1 && ts2 < CAN_BTR_TSEG2_MAX) - { - ts1--; - ts2++; - } - } - - /* Otherwise, nquanta is CAN_BIT_QUANTA, ts1 is CONFIG_STM32_CAN_TSEG1, - * ts2 is CONFIG_STM32_CAN_TSEG2 and we calculate brp to achieve - * CAN_BIT_QUANTA quanta in the bit time - */ - - else - { - ts1 = CONFIG_STM32_CAN_TSEG1; - ts2 = CONFIG_STM32_CAN_TSEG2; - brp = (tmp + (CAN_BIT_QUANTA / 2)) / CAN_BIT_QUANTA; - DEBUGASSERT(brp >= 1 && brp <= CAN_BTR_BRP_MAX); - } - - caninfo("TS1: %" PRIu32 " TS2: %" PRIu32 " BRP: %" PRIu32 "\n", - ts1, ts2, brp); - - /* Configure bit timing. This also does the following, less obvious - * things. Unless loopback mode is enabled, it: - * - * - Disables silent mode. - * - Disables loopback mode. - * - * NOTE that for the time being, SJW is set to 1 just because I don't - * know any better. - */ - - tmp = ((brp - 1) << CAN_BTR_BRP_SHIFT) | ((ts1 - 1) << CAN_BTR_TS1_SHIFT) | - ((ts2 - 1) << CAN_BTR_TS2_SHIFT) | ((1 - 1) << CAN_BTR_SJW_SHIFT); -#ifdef CONFIG_CAN_LOOPBACK - /* tmp |= (CAN_BTR_LBKM | CAN_BTR_SILM); */ - - tmp |= CAN_BTR_LBKM; -#endif - - stm32can_putreg(priv, STM32_CAN_BTR_OFFSET, tmp); - return OK; -} - -/**************************************************************************** - * Name: stm32can_enterinitmode - * - * Description: - * Put the CAN cell in Initialization mode. This only disconnects the CAN - * peripheral, no registers are changed. The initialization mode is - * required to change the baud rate. - * - * Input Parameters: - * priv - A pointer to the private data structure for this CAN block - * - * Returned Value: - * Zero on success; a negated errno value on failure. - * - ****************************************************************************/ - -static int stm32can_enterinitmode(struct stm32_can_s *priv) -{ - uint32_t regval; - volatile uint32_t timeout; - - caninfo("CAN%" PRIu8 "\n", priv->port); - - /* Enter initialization mode */ - - regval = stm32can_getreg(priv, STM32_CAN_MCR_OFFSET); - regval |= CAN_MCR_INRQ; - stm32can_putreg(priv, STM32_CAN_MCR_OFFSET, regval); - - /* Wait until initialization mode is acknowledged */ - - for (timeout = INAK_TIMEOUT; timeout > 0; timeout--) - { - regval = stm32can_getreg(priv, STM32_CAN_MSR_OFFSET); - if ((regval & CAN_MSR_INAK) != 0) - { - /* We are in initialization mode */ - - break; - } - } - - /* Check for a timeout */ - - if (timeout < 1) - { - canerr("ERROR: Timed out waiting to enter initialization mode\n"); - return -ETIMEDOUT; - } - - return OK; -} - -/**************************************************************************** - * Name: stm32can_exitinitmode - * - * Description: - * Put the CAN cell out of the Initialization mode (to Normal mode) - * - * Input Parameters: - * priv - A pointer to the private data structure for this CAN block - * - * Returned Value: - * Zero on success; a negated errno value on failure. - * - ****************************************************************************/ - -static int stm32can_exitinitmode(struct stm32_can_s *priv) -{ - uint32_t regval; - volatile uint32_t timeout; - - /* Exit Initialization mode, enter Normal mode */ - - regval = stm32can_getreg(priv, STM32_CAN_MCR_OFFSET); - regval &= ~CAN_MCR_INRQ; - stm32can_putreg(priv, STM32_CAN_MCR_OFFSET, regval); - - /* Wait until the initialization mode exit is acknowledged */ - - for (timeout = INAK_TIMEOUT; timeout > 0; timeout--) - { - regval = stm32can_getreg(priv, STM32_CAN_MSR_OFFSET); - if ((regval & CAN_MSR_INAK) == 0) - { - /* We are out of initialization mode */ - - break; - } - } - - /* Check for a timeout */ - - if (timeout < 1) - { - canerr("ERROR: Timed out waiting to exit initialization mode: %08" - PRIx32 "\n", regval); - return -ETIMEDOUT; - } - - return OK; -} - -/**************************************************************************** - * Name: stm32can_cellinit - * - * Description: - * CAN cell initialization - * - * Input Parameters: - * priv - A pointer to the private data structure for this CAN block - * - * Returned Value: - * Zero on success; a negated errno value on failure. - * - ****************************************************************************/ - -static int stm32can_cellinit(struct stm32_can_s *priv) -{ - uint32_t regval; - int ret; - - caninfo("CAN%" PRIu8 "\n", priv->port); - - /* Exit from sleep mode */ - - regval = stm32can_getreg(priv, STM32_CAN_MCR_OFFSET); - regval &= ~CAN_MCR_SLEEP; - stm32can_putreg(priv, STM32_CAN_MCR_OFFSET, regval); - - ret = stm32can_enterinitmode(priv); - if (ret != 0) - { - return ret; - } - - /* Disable the following modes: - * - * - Time triggered communication mode - * - Automatic bus-off management - * - Automatic wake-up mode - * - No automatic retransmission - * - Receive FIFO locked mode - * - * Enable: - * - * - Transmit FIFO priority - */ - - regval = stm32can_getreg(priv, STM32_CAN_MCR_OFFSET); - regval &= ~(CAN_MCR_RFLM | CAN_MCR_NART | CAN_MCR_AWUM | - CAN_MCR_ABOM | CAN_MCR_TTCM); - regval |= CAN_MCR_TXFP; - stm32can_putreg(priv, STM32_CAN_MCR_OFFSET, regval); - - /* Configure bit timing. */ - - ret = stm32can_bittiming(priv); - if (ret < 0) - { - canerr("ERROR: Failed to set bit timing: %d\n", ret); - return ret; - } - - return stm32can_exitinitmode(priv); -} - -/**************************************************************************** - * Name: stm32can_filterinit - * - * Description: - * CAN filter initialization. CAN filters are not currently used by this - * driver. The CAN filters can be configured in a different way: - * - * 1. As a match of specific IDs in a list (IdList mode), or as - * 2. And ID and a mask (IdMask mode). - * - * Filters can also be configured as: - * - * 3. 16- or 32-bit. The advantage of 16-bit filters is that you get - * more filters; The advantage of 32-bit filters is that you get - * finer control of the filtering. - * - * One filter is set up for each CAN. The filter resources are shared - * between the two CAN modules: CAN1 uses only filter 0 (but reserves - * 0 through CAN_NFILTERS/2-1); CAN2 uses only filter CAN_NFILTERS/2 - * (but reserves CAN_NFILTERS/2 through CAN_NFILTERS-1). - * - * 32-bit IdMask mode is configured. However, both the ID and the MASK - * are set to zero thus suppressing all filtering because anything masked - * with zero matches zero. - * - * Input Parameters: - * priv - A pointer to the private data structure for this CAN block - * - * Returned Value: - * Zero on success; a negated errno value on failure. - * - ****************************************************************************/ - -static int stm32can_filterinit(struct stm32_can_s *priv) -{ - uint32_t regval; - uint32_t bitmask; - - caninfo("CAN%" PRIu8 " filter: %" PRIu8 "\n", priv->port, priv->filter); - - /* Get the bitmask associated with the filter used by this CAN block */ - - bitmask = (uint32_t)1 << priv->filter; - - /* Enter filter initialization mode */ - - regval = stm32can_getfreg(priv, STM32_CAN_FMR_OFFSET); - regval |= CAN_FMR_FINIT; - stm32can_putfreg(priv, STM32_CAN_FMR_OFFSET, regval); - - /* Assign half the filters to CAN1, half to CAN2 */ - -#if defined(CONFIG_STM32_CONNECTIVITYLINE) || \ - defined(CONFIG_STM32_STM32F20XX) || \ - defined(CONFIG_STM32_STM32F4XXX) - regval = stm32can_getfreg(priv, STM32_CAN_FMR_OFFSET); - regval &= CAN_FMR_CAN2SB_MASK; - regval |= (CAN_NFILTERS / 2) << CAN_FMR_CAN2SB_SHIFT; - stm32can_putfreg(priv, STM32_CAN_FMR_OFFSET, regval); -#endif - - /* Disable the filter */ - - regval = stm32can_getfreg(priv, STM32_CAN_FA1R_OFFSET); - regval &= ~bitmask; - stm32can_putfreg(priv, STM32_CAN_FA1R_OFFSET, regval); - - /* Select the 32-bit scale for the filter */ - - regval = stm32can_getfreg(priv, STM32_CAN_FS1R_OFFSET); - regval |= bitmask; - stm32can_putfreg(priv, STM32_CAN_FS1R_OFFSET, regval); - - /* There are 14 or 28 filter banks (depending) on the device. - * Each filter bank is composed of two 32-bit registers, CAN_FiR: - */ - - stm32can_putfreg(priv, STM32_CAN_FIR_OFFSET(priv->filter, 1), 0); - stm32can_putfreg(priv, STM32_CAN_FIR_OFFSET(priv->filter, 2), 0); - - /* Set Id/Mask mode for the filter */ - - regval = stm32can_getfreg(priv, STM32_CAN_FM1R_OFFSET); - regval &= ~bitmask; - stm32can_putfreg(priv, STM32_CAN_FM1R_OFFSET, regval); - - /* Assign FIFO 0 for the filter */ - - regval = stm32can_getfreg(priv, STM32_CAN_FFA1R_OFFSET); - regval &= ~bitmask; - stm32can_putfreg(priv, STM32_CAN_FFA1R_OFFSET, regval); - - /* Enable the filter */ - - regval = stm32can_getfreg(priv, STM32_CAN_FA1R_OFFSET); - regval |= bitmask; - stm32can_putfreg(priv, STM32_CAN_FA1R_OFFSET, regval); - - /* Exit filter initialization mode */ - - regval = stm32can_getfreg(priv, STM32_CAN_FMR_OFFSET); - regval &= ~CAN_FMR_FINIT; - stm32can_putfreg(priv, STM32_CAN_FMR_OFFSET, regval); - return OK; -} - -/**************************************************************************** - * Name: stm32can_addextfilter - * - * Description: - * Add a filter for extended CAN IDs - * - * Input Parameters: - * priv - A pointer to the private data structure for this CAN block - * arg - A pointer to a structure describing the filter - * - * Returned Value: - * A non-negative filter ID is returned on success. - * Otherwise -1 (ERROR) is returned with the errno - * set to indicate the nature of the error. - * - ****************************************************************************/ - -#ifdef CONFIG_CAN_EXTID -static int stm32can_addextfilter(struct stm32_can_s *priv, - struct canioc_extfilter_s *arg) -{ - return -ENOTTY; -} -#endif - -/**************************************************************************** - * Name: stm32can_delextfilter - * - * Description: - * Remove a filter for extended CAN IDs - * - * Input Parameters: - * priv - A pointer to the private data structure for this CAN block - * arg - The filter index previously returned by the - * CANIOC_ADD_EXTFILTER command - * - * Returned Value: - * Zero (OK) is returned on success. Otherwise -1 (ERROR) - * returned with the errno variable set to indicate the - * of the error. - * - ****************************************************************************/ - -#ifdef CONFIG_CAN_EXTID -static int stm32can_delextfilter(struct stm32_can_s *priv, int arg) -{ - return -ENOTTY; -} -#endif - -/**************************************************************************** - * Name: stm32can_addstdfilter - * - * Description: - * Add a filter for standard CAN IDs - * - * Input Parameters: - * priv - A pointer to the private data structure for this CAN block - * arg - A pointer to a structure describing the filter - * - * Returned Value: - * A non-negative filter ID is returned on success. - * Otherwise -1 (ERROR) is returned with the errno - * set to indicate the nature of the error. - * - ****************************************************************************/ - -static int stm32can_addstdfilter(struct stm32_can_s *priv, - struct canioc_stdfilter_s *arg) -{ - return -ENOTTY; -} - -/**************************************************************************** - * Name: stm32can_delstdfilter - * - * Description: - * Remove a filter for standard CAN IDs - * - * Input Parameters: - * priv - A pointer to the private data structure for this CAN block - * arg - The filter index previously returned by the - * CANIOC_ADD_STDFILTER command - * - * Returned Value: - * Zero (OK) is returned on success. Otherwise -1 (ERROR) - * returned with the errno variable set to indicate the - * of the error. - * - ****************************************************************************/ - -static int stm32can_delstdfilter(struct stm32_can_s *priv, int arg) -{ - return -ENOTTY; -} - -/**************************************************************************** - * Name: stm32can_txmb0empty - * - * Input Parameters: - * tsr_regval - value of CAN transmit status register - * - * Returned Value: - * Returns true if mailbox 0 is empty and can be used for sending. - * - ****************************************************************************/ - -static bool stm32can_txmb0empty(uint32_t tsr_regval) -{ - return (tsr_regval & CAN_TSR_TME0) != 0 && - (tsr_regval & CAN_TSR_RQCP0) == 0; -} - -/**************************************************************************** - * Name: stm32can_txmb1empty - * - * Input Parameters: - * tsr_regval - value of CAN transmit status register - * - * Returned Value: - * Returns true if mailbox 1 is empty and can be used for sending. - * - ****************************************************************************/ - -static bool stm32can_txmb1empty(uint32_t tsr_regval) -{ - return (tsr_regval & CAN_TSR_TME1) != 0 && - (tsr_regval & CAN_TSR_RQCP1) == 0; -} - -/**************************************************************************** - * Name: stm32can_txmb2empty - * - * Input Parameters: - * tsr_regval - value of CAN transmit status register - * - * Returned Value: - * Returns true if mailbox 2 is empty and can be used for sending. - * - ****************************************************************************/ - -static bool stm32can_txmb2empty(uint32_t tsr_regval) -{ - return (tsr_regval & CAN_TSR_TME2) != 0 && - (tsr_regval & CAN_TSR_RQCP2) == 0; -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_caninitialize - * - * Description: - * Initialize the selected CAN port - * - * Input Parameters: - * Port number (for hardware that has multiple CAN interfaces) - * - * Returned Value: - * Valid CAN device structure reference on success; a NULL on failure - * - ****************************************************************************/ - -struct can_dev_s *stm32_caninitialize(int port) -{ - struct can_dev_s *dev = NULL; - - caninfo("CAN%" PRIu8 "\n", port); - - /* NOTE: Peripherical clocking for CAN1 and/or CAN2 was already provided - * by stm32_clockconfig() early in the reset sequence. - */ - -#ifdef CONFIG_STM32_CAN1 - if (port == 1) - { - /* Select the CAN1 device structure */ - - dev = &g_can1dev; - - /* Configure CAN1 pins. The ambiguous settings in the stm32*_pinmap.h - * file must have been disambiguated in the board.h file. - */ - - stm32_configgpio(GPIO_CAN1_RX); - stm32_configgpio(GPIO_CAN1_TX); - } - else -#endif -#ifdef CONFIG_STM32_CAN2 - if (port == 2) - { - /* Select the CAN2 device structure */ - - dev = &g_can2dev; - - /* Configure CAN2 pins. The ambiguous settings in the stm32*_pinmap.h - * file must have been disambiguated in the board.h file. - */ - - stm32_configgpio(GPIO_CAN2_RX); - stm32_configgpio(GPIO_CAN2_TX); - } - else -#endif - { - canerr("ERROR: Unsupported port %d\n", port); - return NULL; - } - - return dev; -} - -#endif /* CONFIG_CAN && (CONFIG_STM32_CAN1 || CONFIG_STM32_CAN2) */ diff --git a/arch/arm/src/stm32/stm32_can.h b/arch/arm/src/stm32/stm32_can.h deleted file mode 100644 index e9f906a92e183..0000000000000 --- a/arch/arm/src/stm32/stm32_can.h +++ /dev/null @@ -1,154 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_can.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32_STM32_CAN_H -#define __ARCH_ARM_SRC_STM32_STM32_CAN_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "chip.h" -#include "hardware/stm32_can.h" - -#include - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -/* Up to 2 CAN interfaces are supported */ - -#if STM32_NCAN < 2 -# undef CONFIG_STM32_CAN2 -#endif - -#if STM32_NCAN < 1 -# undef CONFIG_STM32_CAN1 -#endif - -/* CAN BAUD */ - -#if defined(CONFIG_STM32_CAN1) && !defined(CONFIG_STM32_CAN1_BAUD) -# error "CONFIG_STM32_CAN1_BAUD is not defined" -#endif - -#if defined(CONFIG_STM32_CAN2) && !defined(CONFIG_STM32_CAN2_BAUD) -# error "CONFIG_STM32_CAN2_BAUD is not defined" -#endif - -/* User-defined TSEG1 and TSEG2 settings may be used. - * - * CONFIG_STM32_CAN_TSEG1 = the number of CAN time quanta in segment 1 - * CONFIG_STM32_CAN_TSEG2 = the number of CAN time quanta in segment 2 - * CAN_BIT_QUANTA = The number of CAN time quanta in on bit time - */ - -#ifndef CONFIG_STM32_CAN_TSEG1 -# define CONFIG_STM32_CAN_TSEG1 6 -#endif - -#if CONFIG_STM32_CAN_TSEG1 < 1 || CONFIG_STM32_CAN_TSEG1 > CAN_BTR_TSEG1_MAX -# error "CONFIG_STM32_CAN_TSEG1 is out of range" -#endif - -#ifndef CONFIG_STM32_CAN_TSEG2 -# define CONFIG_STM32_CAN_TSEG2 7 -#endif - -#if CONFIG_STM32_CAN_TSEG2 < 1 || CONFIG_STM32_CAN_TSEG2 > CAN_BTR_TSEG2_MAX -# error "CONFIG_STM32_CAN_TSEG2 is out of range" -#endif - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -#ifndef __ASSEMBLY__ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -#ifdef CONFIG_STM32_CAN_CHARDRIVER - -/**************************************************************************** - * Name: stm32_caninitialize - * - * Description: - * Initialize the selected CAN port as character device - * - * Input Parameters: - * Port number (for hardware that has multiple CAN interfaces) - * - * Returned Value: - * Valid CAN device structure reference on success; a NULL on failure - * - ****************************************************************************/ - -struct can_dev_s; -struct can_dev_s *stm32_caninitialize(int port); -#endif - -#ifdef CONFIG_STM32_CAN_SOCKET - -/**************************************************************************** - * Name: stm32_cansockinitialize - * - * Description: - * Initialize the selected CAN port as SocketCAN interface - * - * Input Parameters: - * Port number (for hardware that has multiple CAN interfaces) - * - * Returned Value: - * OK on success; Negated errno on failure. - * - ****************************************************************************/ - -int stm32_cansockinitialize(int port); -#endif - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32_STM32_CAN_H */ diff --git a/arch/arm/src/stm32/stm32_can_sock.c b/arch/arm/src/stm32/stm32_can_sock.c deleted file mode 100644 index 433ec29e15318..0000000000000 --- a/arch/arm/src/stm32/stm32_can_sock.c +++ /dev/null @@ -1,2490 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_can_sock.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -#include -#include -#include - -#include "arm_internal.h" -#include "chip.h" -#include "stm32.h" -#include "stm32_rcc.h" -#include "stm32_can.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Delays *******************************************************************/ - -/* Time out for INAK bit */ - -#define INAK_TIMEOUT 65535 - -/* Bit timing ***************************************************************/ - -#define CAN_BIT_QUANTA (CONFIG_STM32_CAN_TSEG1 + CONFIG_STM32_CAN_TSEG2 + 1) - -#ifndef CONFIG_DEBUG_CAN_INFO -# undef CONFIG_STM32_CAN_REGDEBUG -#endif - -/* Pool configuration *******************************************************/ - -#define POOL_SIZE (1) - -/* Work queue support is required. */ - -#if !defined(CONFIG_SCHED_WORKQUEUE) -# error Work queue support is required -#endif - -/* The low priority work queue is preferred. If it is not enabled, LPWORK - * will be the same as HPWORK. - * - * NOTE: However, the network should NEVER run on the high priority work - * queue! That queue is intended only to service short back end interrupt - * processing that never suspends. Suspending the high priority work queue - * may bring the system to its knees! - */ - -#define CANWORK LPWORK - -/* CAN error interrupts */ - -#ifdef CONFIG_NET_CAN_ERRORS -# define STM32_CAN_ERRINT (CAN_IER_LECIE | CAN_IER_ERRIE | \ - CAN_IER_BOFIE | CAN_IER_EPVIE | \ - CAN_IER_EWGIE) -#endif - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -struct stm32_can_s -{ - uint8_t port; /* CAN port number (1 or 2) */ - uint8_t canrx[2]; /* CAN RX FIFO 0/1 IRQ number */ - uint8_t cantx; /* CAN TX IRQ number */ -#ifdef CONFIG_NET_CAN_ERRORS - uint8_t cansce; /* CAN SCE IRQ number */ -#endif - uint8_t filter; /* Filter number */ - uint32_t base; /* Base address of the CAN control registers */ - uint32_t fbase; /* Base address of the CAN filter registers */ - uint32_t baud; /* Configured baud */ - - bool bifup; /* true:ifup false:ifdown */ - struct net_driver_s dev; /* Interface understood by the network */ - - struct work_s irqwork; /* For deferring interrupt work to the wq */ - struct work_s pollwork; /* For deferring poll work to the work wq */ - - /* A pointers to the list of TX/RX descriptors */ - - struct can_frame *txdesc; - struct can_frame *rxdesc; - - /* TX/RX pool */ - - uint8_t tx_pool[sizeof(struct can_frame)*POOL_SIZE]; - uint8_t rx_pool[sizeof(struct can_frame)*POOL_SIZE]; -}; - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -/* CAN Register access */ - -static uint32_t stm32can_getreg(struct stm32_can_s *priv, - int offset); -static uint32_t stm32can_getfreg(struct stm32_can_s *priv, - int offset); -static void stm32can_putreg(struct stm32_can_s *priv, int offset, - uint32_t value); -static void stm32can_putfreg(struct stm32_can_s *priv, int offset, - uint32_t value); -#ifdef CONFIG_STM32_CAN_REGDEBUG -static void stm32can_dumpctrlregs(struct stm32_can_s *priv, - const char *msg); -static void stm32can_dumpmbregs(struct stm32_can_s *priv, - const char *msg); -static void stm32can_dumpfiltregs(struct stm32_can_s *priv, - const char *msg); -#else -# define stm32can_dumpctrlregs(priv,msg) -# define stm32can_dumpmbregs(priv,msg) -# define stm32can_dumpfiltregs(priv,msg) -#endif - -/* CAN interrupt enable functions */ - -static void stm32can_rx0int(struct stm32_can_s *priv, bool enable); -static void stm32can_rx1int(struct stm32_can_s *priv, bool enable); -static void stm32can_txint(struct stm32_can_s *priv, bool enable); -#ifdef CONFIG_NET_CAN_ERRORS -static void stm32can_errint(struct stm32_can_s *priv, bool enable); -#endif - -/* Common TX logic */ - -static int stm32can_transmit(struct stm32_can_s *priv); -static bool stm32can_txready(struct stm32_can_s *priv); -static int stm32can_txpoll(struct net_driver_s *dev); - -/* CAN RX interrupt handling */ - -static int stm32can_rxinterrupt_work(struct stm32_can_s *priv, - int rxmb); - -static void stm32can_rx0interrupt_work(void *arg); -static void stm32can_rx1interrupt_work(void *arg); -static int stm32can_rxinterrupt(struct stm32_can_s *priv, int rxmb); - -static int stm32can_rx0interrupt(int irq, void *context, void *arg); -static int stm32can_rx1interrupt(int irq, void *context, void *arg); - -/* CAN TX interrupt handling */ - -static int stm32can_txinterrupt(int irq, void *context, void *arg); -static void stm32can_txdone_work(void *arg); -static void stm32can_txdone(struct stm32_can_s *priv); - -#ifdef CONFIG_NET_CAN_ERRORS -/* CAN errors interrupt handling */ - -static void stm32can_sceinterrupt_work(void *arg); -static int stm32can_sceinterrupt(int irq, void *context, void *arg); -#endif - -/* Initialization */ - -static int stm32can_setup(struct stm32_can_s *priv); -static void stm32can_shutdown(struct stm32_can_s *priv); -static void stm32can_reset(struct stm32_can_s *priv); -static int stm32can_enterinitmode(struct stm32_can_s *priv); -static int stm32can_exitinitmode(struct stm32_can_s *priv); -static int stm32can_bittiming(struct stm32_can_s *priv); -static int stm32can_cellinit(struct stm32_can_s *priv); -static int stm32can_filterinit(struct stm32_can_s *priv); - -/* TX mailbox status */ - -static bool stm32can_txmb0empty(uint32_t tsr_regval); -static bool stm32can_txmb1empty(uint32_t tsr_regval); -static bool stm32can_txmb2empty(uint32_t tsr_regval); - -/* NuttX callback functions */ - -static int stm32can_ifup(struct net_driver_s *dev); -static int stm32can_ifdown(struct net_driver_s *dev); - -static void stm32can_txavail_work(void *arg); -static int stm32can_txavail(struct net_driver_s *dev); - -#ifdef CONFIG_NETDEV_IOCTL -static int stm32can_netdev_ioctl(struct net_driver_s *dev, int cmd, - unsigned long arg); -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -#ifdef CONFIG_STM32_CAN1 - -static struct stm32_can_s g_can1priv = -{ - .port = 1, - .canrx = - { - STM32_IRQ_CAN1RX0, - STM32_IRQ_CAN1RX1, - }, - .cantx = STM32_IRQ_CAN1TX, -#ifdef CONFIG_NET_CAN_ERRORS - .cansce = STM32_IRQ_CAN1SCE, -#endif - .filter = 0, - .base = STM32_CAN1_BASE, - .fbase = STM32_CAN1_BASE, - .baud = CONFIG_STM32_CAN1_BAUD, -}; - -#endif - -#ifdef CONFIG_STM32_CAN2 - -static struct stm32_can_s g_can2priv = -{ - .port = 2, - .canrx = - { - STM32_IRQ_CAN2RX0, - STM32_IRQ_CAN2RX1, - }, - .cantx = STM32_IRQ_CAN2TX, -#ifdef CONFIG_NET_CAN_ERRORS - .cansce = STM32_IRQ_CAN2SCE, -#endif - .filter = CAN_NFILTERS / 2, - .base = STM32_CAN2_BASE, - .fbase = STM32_CAN1_BASE, - .baud = CONFIG_STM32_CAN2_BAUD, -}; - -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32can_getreg - * Name: stm32can_getfreg - * - * Description: - * Read the value of a CAN register or filter block register. - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_CAN_REGDEBUG -static uint32_t stm32can_vgetreg(uint32_t addr) -{ - static uint32_t prevaddr = 0; - static uint32_t preval = 0; - static uint32_t count = 0; - - /* Read the value from the register */ - - uint32_t val = getreg32(addr); - - /* Is this the same value that we read from the same register last time? - * Are we polling the register? If so, suppress some of the output. - */ - - if (addr == prevaddr && val == preval) - { - if (count == 0xffffffff || ++count > 3) - { - if (count == 4) - { - ninfo("...\n"); - } - - return val; - } - } - - /* No this is a new address or value */ - - else - { - /* Did we print "..." for the previous value? */ - - if (count > 3) - { - /* Yes.. then show how many times the value repeated */ - - ninfo("[repeats %" PRIu32 " more times]\n", count - 3); - } - - /* Save the new address, value, and count */ - - prevaddr = addr; - preval = val; - count = 1; - } - - /* Show the register value read */ - - ninfo("%08" PRIx32 "->%08" PRIx32 "\n", addr, val); - return val; -} - -static uint32_t stm32can_getreg(struct stm32_can_s *priv, int offset) -{ - return stm32can_vgetreg(priv->base + offset); -} - -static uint32_t stm32can_getfreg(struct stm32_can_s *priv, int offset) -{ - return stm32can_vgetreg(priv->fbase + offset); -} - -#else -static uint32_t stm32can_getreg(struct stm32_can_s *priv, int offset) -{ - return getreg32(priv->base + offset); -} - -static uint32_t stm32can_getfreg(struct stm32_can_s *priv, int offset) -{ - return getreg32(priv->fbase + offset); -} - -#endif - -/**************************************************************************** - * Name: stm32can_putreg - * Name: stm32can_putfreg - * - * Description: - * Set the value of a CAN register or filter block register. - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_CAN_REGDEBUG -static void stm32can_vputreg(uint32_t addr, uint32_t value) -{ - /* Show the register value being written */ - - ninfo("%08" PRIx32 "->%08" PRIx32 "\n", addr, val); - - /* Write the value */ - - putreg32(value, addr); -} - -static void stm32can_putreg(struct stm32_can_s *priv, int offset, - uint32_t value) -{ - stm32can_vputreg(priv->base + offset, value); -} - -static void stm32can_putfreg(struct stm32_can_s *priv, int offset, - uint32_t value) -{ - stm32can_vputreg(priv->fbase + offset, value); -} - -#else -static void stm32can_putreg(struct stm32_can_s *priv, int offset, - uint32_t value) -{ - putreg32(value, priv->base + offset); -} - -static void stm32can_putfreg(struct stm32_can_s *priv, int offset, - uint32_t value) -{ - putreg32(value, priv->fbase + offset); -} -#endif - -/**************************************************************************** - * Name: stm32can_dumpctrlregs - * - * Description: - * Dump the contents of all CAN control registers - * - * Input Parameters: - * priv - reference to the private CAN driver state structure - * msg - message - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_CAN_REGDEBUG -static void stm32can_dumpctrlregs(struct stm32_can_s *priv, - const char *msg) -{ - if (msg) - { - ninfo("Control Registers: %s\n", msg); - } - else - { - ninfo("Control Registers:\n"); - } - - /* CAN control and status registers */ - - ninfo(" MCR: %08" PRIx32 " MSR: %08" PRIx32 " TSR: %08" PRIx32 "\n", - getreg32(priv->base + STM32_CAN_MCR_OFFSET), - getreg32(priv->base + STM32_CAN_MSR_OFFSET), - getreg32(priv->base + STM32_CAN_TSR_OFFSET)); - - ninfo(" RF0R: %08" PRIx32 " RF1R: %08" PRIx32 "\n", - getreg32(priv->base + STM32_CAN_RF0R_OFFSET), - getreg32(priv->base + STM32_CAN_RF1R_OFFSET)); - - ninfo(" IER: %08" PRIx32 " ESR: %08" PRIx32 " BTR: %08" PRIx32 "\n", - getreg32(priv->base + STM32_CAN_IER_OFFSET), - getreg32(priv->base + STM32_CAN_ESR_OFFSET), - getreg32(priv->base + STM32_CAN_BTR_OFFSET)); -} -#endif - -/**************************************************************************** - * Name: stm32can_dumpmbregs - * - * Description: - * Dump the contents of all CAN mailbox registers - * - * Input Parameters: - * priv - reference to the private CAN driver state structure - * msg - message - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_CAN_REGDEBUG -static void stm32can_dumpmbregs(struct stm32_can_s *priv, - const char *msg) -{ - if (msg) - { - ninfo("Mailbox Registers: %s\n", msg); - } - else - { - ninfo("Mailbox Registers:\n"); - } - - /* CAN mailbox registers (3 TX and 2 RX) */ - - ninfo(" TI0R: %08" PRIx32 " TDT0R: %08" PRIx32 " TDL0R: %08" - PRIx32 " TDH0R: %08" PRIx32 "\n", - getreg32(priv->base + STM32_CAN_TI0R_OFFSET), - getreg32(priv->base + STM32_CAN_TDT0R_OFFSET), - getreg32(priv->base + STM32_CAN_TDL0R_OFFSET), - getreg32(priv->base + STM32_CAN_TDH0R_OFFSET)); - - ninfo(" TI1R: %08" PRIx32 " TDT1R: %08" PRIx32 " TDL1R: %08" - PRIx32 " TDH1R: %08" PRIx32 "\n", - getreg32(priv->base + STM32_CAN_TI1R_OFFSET), - getreg32(priv->base + STM32_CAN_TDT1R_OFFSET), - getreg32(priv->base + STM32_CAN_TDL1R_OFFSET), - getreg32(priv->base + STM32_CAN_TDH1R_OFFSET)); - - ninfo(" TI2R: %08" PRIx32 " TDT2R: %08" PRIx32 " TDL2R: %08" - PRIx32 " TDH2R: %08" PRIx32 "\n", - getreg32(priv->base + STM32_CAN_TI2R_OFFSET), - getreg32(priv->base + STM32_CAN_TDT2R_OFFSET), - getreg32(priv->base + STM32_CAN_TDL2R_OFFSET), - getreg32(priv->base + STM32_CAN_TDH2R_OFFSET)); - - ninfo(" RI0R: %08" PRIx32 " RDT0R: %08" PRIx32 " RDL0R: %08" - PRIx32 " RDH0R: %08" PRIx32 "\n", - getreg32(priv->base + STM32_CAN_RI0R_OFFSET), - getreg32(priv->base + STM32_CAN_RDT0R_OFFSET), - getreg32(priv->base + STM32_CAN_RDL0R_OFFSET), - getreg32(priv->base + STM32_CAN_RDH0R_OFFSET)); - - ninfo(" RI1R: %08" PRIx32 " RDT1R: %08" PRIx32 " RDL1R: %08" - PRIx32 " RDH1R: %08" PRIx32 "\n", - getreg32(priv->base + STM32_CAN_RI1R_OFFSET), - getreg32(priv->base + STM32_CAN_RDT1R_OFFSET), - getreg32(priv->base + STM32_CAN_RDL1R_OFFSET), - getreg32(priv->base + STM32_CAN_RDH1R_OFFSET)); -} -#endif - -/**************************************************************************** - * Name: stm32can_dumpfiltregs - * - * Description: - * Dump the contents of all CAN filter registers - * - * Input Parameters: - * priv - reference to the private CAN driver state structure - * msg - message - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_CAN_REGDEBUG -static void stm32can_dumpfiltregs(struct stm32_can_s *priv, - const char *msg) -{ - int i; - - if (msg) - { - ninfo("Filter Registers: %s\n", msg); - } - else - { - ninfo("Filter Registers:\n"); - } - - ninfo(" FMR: %08" PRIx32 " FM1R: %08" PRIx32 " FS1R: %08" - PRIx32 " FFA1R: %08" PRIx32 " FA1R: %08" PRIx32 "\n", - getreg32(priv->base + STM32_CAN_FMR_OFFSET), - getreg32(priv->base + STM32_CAN_FM1R_OFFSET), - getreg32(priv->base + STM32_CAN_FS1R_OFFSET), - getreg32(priv->base + STM32_CAN_FFA1R_OFFSET), - getreg32(priv->base + STM32_CAN_FA1R_OFFSET)); - - for (i = 0; i < CAN_NFILTERS; i++) - { - ninfo(" F%dR1: %08" PRIx32 " F%dR2: %08" PRIx32 "\n", - i, getreg32(priv->base + STM32_CAN_FIR_OFFSET(i, 1)), - i, getreg32(priv->base + STM32_CAN_FIR_OFFSET(i, 2))); - } -} -#endif - -/**************************************************************************** - * Name: stm32can_rx0int - * - * Description: - * Call to enable or disable RX0 interrupts. - * - * Input Parameters: - * priv - reference to the private CAN driver state structure - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void stm32can_rx0int(struct stm32_can_s *priv, bool enable) -{ - uint32_t regval = 0; - - ninfo("CAN%" PRIu8 "RX0 enable: %d\n", priv->port, enable); - - /* Enable/disable the FIFO 0 message pending interrupt */ - - regval = stm32can_getreg(priv, STM32_CAN_IER_OFFSET); - if (enable) - { - regval |= CAN_IER_FMPIE0; - } - else - { - regval &= ~CAN_IER_FMPIE0; - } - - stm32can_putreg(priv, STM32_CAN_IER_OFFSET, regval); -} - -/**************************************************************************** - * Name: stm32can_rx1int - * - * Description: - * Call to enable or disable RX1 interrupts. - * - * Input Parameters: - * priv - reference to the private CAN driver state structure - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void stm32can_rx1int(struct stm32_can_s *priv, bool enable) -{ - uint32_t regval = 0; - - ninfo("CAN%" PRIu8 "RX1 enable: %d\n", priv->port, enable); - - /* Enable/disable the FIFO 1 message pending interrupt */ - - regval = stm32can_getreg(priv, STM32_CAN_IER_OFFSET); - if (enable) - { - regval |= CAN_IER_FMPIE1; - } - else - { - regval &= ~CAN_IER_FMPIE1; - } - - stm32can_putreg(priv, STM32_CAN_IER_OFFSET, regval); -} - -/**************************************************************************** - * Name: stm32can_txint - * - * Description: - * Call to enable or disable TX interrupts. - * - * Input Parameters: - * priv - reference to the private CAN driver state structure - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void stm32can_txint(struct stm32_can_s *priv, bool enable) -{ - uint32_t regval = 0; - - ninfo("CAN%" PRIu8 " txint enable: %d\n", priv->port, enable); - - /* Enable/disable the transmit mailbox interrupt */ - - regval = stm32can_getreg(priv, STM32_CAN_IER_OFFSET); - if (enable) - { - regval |= CAN_IER_TMEIE; - } - else - { - regval &= ~CAN_IER_TMEIE; - } - - stm32can_putreg(priv, STM32_CAN_IER_OFFSET, regval); -} - -#ifdef CONFIG_NET_CAN_ERRORS -/**************************************************************************** - * Name: stm32can_txint - * - * Description: - * Call to enable or disable CAN SCE interrupts. - * - * Input Parameters: - * priv - reference to the private CAN driver state structure - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void stm32can_errint(struct stm32_can_s *priv, bool enable) -{ - uint32_t regval = 0; - - /* Enable/disable the transmit mailbox interrupt */ - - regval = stm32can_getreg(priv, STM32_CAN_IER_OFFSET); - if (enable) - { - regval |= STM32_CAN_ERRINT; - } - else - { - regval &= ~STM32_CAN_ERRINT; - } - - stm32can_putreg(priv, STM32_CAN_IER_OFFSET, regval); -} -#endif - -/**************************************************************************** - * Function: stm32can_ifup - * - * Description: - * NuttX Callback: Bring up the Ethernet interface when an IP address is - * provided - * - * Input Parameters: - * dev - Reference to the NuttX driver state structure - * - * Returned Value: - * None - * - * Assumptions: - * - ****************************************************************************/ - -static int stm32can_ifup(struct net_driver_s *dev) -{ - struct stm32_can_s *priv = (struct stm32_can_s *)dev->d_private; - - /* Setup CAN */ - - stm32can_setup(priv); - - /* Enable interrupts */ - - stm32can_rx0int(priv, true); - stm32can_rx1int(priv, true); - stm32can_txint(priv, true); -#ifdef CONFIG_NET_CAN_ERRORS - stm32can_errint(priv, true); -#endif - - /* Enable the interrupts at the NVIC */ - - up_enable_irq(priv->canrx[0]); - up_enable_irq(priv->canrx[1]); - up_enable_irq(priv->cantx); -#ifdef CONFIG_NET_CAN_ERRORS - up_enable_irq(priv->cansce); -#endif - - priv->bifup = true; - - priv->txdesc = (struct can_frame *)priv->tx_pool; - priv->rxdesc = (struct can_frame *)priv->rx_pool; - - priv->dev.d_buf = (uint8_t *)priv->txdesc; - - netdev_carrier_on(dev); - - return OK; -} - -/**************************************************************************** - * Function: stm32can_ifdown - * - * Description: - * NuttX Callback: Stop the interface. - * - * Input Parameters: - * dev - Reference to the NuttX driver state structure - * - * Returned Value: - * None - * - * Assumptions: - * - ****************************************************************************/ - -static int stm32can_ifdown(struct net_driver_s *dev) -{ - struct stm32_can_s *priv = (struct stm32_can_s *)dev->d_private; - - /* Disable CAN interrupts */ - - stm32can_shutdown(priv); - - /* Reset CAN */ - - stm32can_reset(priv); - - netdev_carrier_off(dev); - - return OK; -} - -/**************************************************************************** - * Name: stm32can_txready - * - * Description: - * Return true if the CAN hardware can accept another TX message. - * - ****************************************************************************/ - -static bool stm32can_txready(struct stm32_can_s *priv) -{ - uint32_t regval; - - /* Return true if any mailbox is available */ - - regval = stm32can_getreg(priv, STM32_CAN_TSR_OFFSET); - ninfo("CAN%" PRIu8 " TSR: %08" PRIx32 "\n", priv->port, regval); - - return (stm32can_txmb0empty(regval) || stm32can_txmb1empty(regval) || - stm32can_txmb2empty(regval)); -} - -/**************************************************************************** - * Name: stm32can_transmit - * - * Description: - * Start hardware transmission. Called either from the txdone interrupt - * handling or from watchdog based polling. - * - * Input Parameters: - * priv - reference to the private CAN driver state structure - * - * Returned Value: - * OK on success; a negated errno on failure - * - * Assumptions: - * May or may not be called from an interrupt handler. In either case, - * global interrupts are disabled, either explicitly or indirectly through - * interrupt handling logic. - * - ****************************************************************************/ - -static int stm32can_transmit(struct stm32_can_s *priv) -{ - struct can_frame *frame = (struct can_frame *)priv->dev.d_buf; - uint8_t *ptr; - uint32_t regval; - uint32_t tmp; - int dlc; - int txmb; - - ninfo("CAN%" PRIu8 " ID: %" PRIu32 " DLC: %" PRIu8 "\n", - priv->port, (uint32_t)frame->can_id, frame->can_dlc); - - /* Select one empty transmit mailbox */ - - regval = stm32can_getreg(priv, STM32_CAN_TSR_OFFSET); - if (stm32can_txmb0empty(regval)) - { - txmb = 0; - } - else if (stm32can_txmb1empty(regval)) - { - txmb = 1; - } - else if (stm32can_txmb2empty(regval)) - { - txmb = 2; - } - else - { - canerr("ERROR: No available mailbox\n"); - return -EBUSY; - } - - /* Clear TXRQ, RTR, IDE, EXID, and STID fields */ - - regval = stm32can_getreg(priv, STM32_CAN_TIR_OFFSET(txmb)); - regval &= ~(CAN_TIR_TXRQ | CAN_TIR_RTR | CAN_TIR_IDE | - CAN_TIR_EXID_MASK | CAN_TIR_STID_MASK); - stm32can_putreg(priv, STM32_CAN_TIR_OFFSET(txmb), regval); - - /* Set up the ID, standard 11-bit or extended 29-bit. */ - -#ifdef CONFIG_NET_CAN_EXTID - regval &= ~CAN_TIR_EXID_MASK; - if (frame->can_id & CAN_EFF_FLAG) - { - DEBUGASSERT((frame->can_id ^ CAN_EFF_FLAG) < (1 << 29)); - regval |= (frame->can_id << CAN_TIR_EXID_SHIFT) | CAN_TIR_IDE; - } - else - { - DEBUGASSERT(frame->can_id < (1 << 11)); - regval |= frame->can_id << CAN_TIR_STID_SHIFT; - } - -#else - regval |= (((uint32_t) frame->can_id << CAN_TIR_STID_SHIFT) & - CAN_TIR_STID_MASK); - -#endif - -#ifdef CONFIG_CAN_USE_RTR - regval |= ((frame->can_id & CAN_RTR_FLAG) ? CAN_TIR_RTR : 0); -#endif - - stm32can_putreg(priv, STM32_CAN_TIR_OFFSET(txmb), regval); - - /* Set up the DLC */ - - dlc = frame->can_dlc; - regval = stm32can_getreg(priv, STM32_CAN_TDTR_OFFSET(txmb)); - regval &= ~(CAN_TDTR_DLC_MASK | CAN_TDTR_TGT); - regval |= (uint32_t)dlc << CAN_TDTR_DLC_SHIFT; - stm32can_putreg(priv, STM32_CAN_TDTR_OFFSET(txmb), regval); - - /* Set up the data fields */ - - ptr = frame->data; - regval = 0; - - if (dlc > 0) - { - tmp = (uint32_t)*ptr++; - regval = tmp << CAN_TDLR_DATA0_SHIFT; - - if (dlc > 1) - { - tmp = (uint32_t)*ptr++; - regval |= tmp << CAN_TDLR_DATA1_SHIFT; - - if (dlc > 2) - { - tmp = (uint32_t)*ptr++; - regval |= tmp << CAN_TDLR_DATA2_SHIFT; - - if (dlc > 3) - { - tmp = (uint32_t)*ptr++; - regval |= tmp << CAN_TDLR_DATA3_SHIFT; - } - } - } - } - - stm32can_putreg(priv, STM32_CAN_TDLR_OFFSET(txmb), regval); - - regval = 0; - if (dlc > 4) - { - tmp = (uint32_t)*ptr++; - regval = tmp << CAN_TDHR_DATA4_SHIFT; - - if (dlc > 5) - { - tmp = (uint32_t)*ptr++; - regval |= tmp << CAN_TDHR_DATA5_SHIFT; - - if (dlc > 6) - { - tmp = (uint32_t)*ptr++; - regval |= tmp << CAN_TDHR_DATA6_SHIFT; - - if (dlc > 7) - { - tmp = (uint32_t)*ptr++; - regval |= tmp << CAN_TDHR_DATA7_SHIFT; - } - } - } - } - - stm32can_putreg(priv, STM32_CAN_TDHR_OFFSET(txmb), regval); - - /* Enable the transmit mailbox empty interrupt (may already be enabled) */ - - regval = stm32can_getreg(priv, STM32_CAN_IER_OFFSET); - regval |= CAN_IER_TMEIE; - stm32can_putreg(priv, STM32_CAN_IER_OFFSET, regval); - - /* Request transmission */ - - regval = stm32can_getreg(priv, STM32_CAN_TIR_OFFSET(txmb)); - regval |= CAN_TIR_TXRQ; /* Transmit Mailbox Request */ - stm32can_putreg(priv, STM32_CAN_TIR_OFFSET(txmb), regval); - - stm32can_dumpmbregs(priv, "After send"); - return OK; -} - -/**************************************************************************** - * Function: stm32can_txpoll - * - * Description: - * The transmitter is available, check if the network has any outgoing - * packets ready to send. This is a callback from devif_poll(). - * devif_poll() may be called: - * - * 1. When the preceding TX packet send is complete, - * 2. When the preceding TX packet send timesout and the interface is reset - * 3. During normal TX polling - * - * Input Parameters: - * dev - Reference to the NuttX driver state structure - * - * Returned Value: - * OK on success; a negated errno on failure - * - * Assumptions: - * May or may not be called from an interrupt handler. In either case, - * global interrupts are disabled, either explicitly or indirectly through - * interrupt handling logic. - * - ****************************************************************************/ - -static int stm32can_txpoll(struct net_driver_s *dev) -{ - struct stm32_can_s *priv = (struct stm32_can_s *)dev->d_private; - - /* If the polling resulted in data that should be sent out on the network, - * the field d_len is set to a value > 0. - */ - - if (priv->dev.d_len > 0) - { - stm32can_txdone(priv); - - /* Send the packet */ - - stm32can_transmit(priv); - - /* Check if there is room in the device to hold another packet. If - * not, return a non-zero value to terminate the poll. - */ - - if (stm32can_txready(priv) == false) - { - return -EBUSY; - } - } - - /* If zero is returned, the polling will continue until all connections - * have been examined. - */ - - return 0; -} - -/**************************************************************************** - * Function: stm32can_txavail_work - * - * Description: - * Perform an out-of-cycle poll on the worker thread. - * - * Input Parameters: - * arg - Reference to the NuttX driver state structure (cast to void*) - * - * Returned Value: - * None - * - * Assumptions: - * Called on the higher priority worker thread. - * - ****************************************************************************/ - -static void stm32can_txavail_work(void *arg) -{ - struct stm32_can_s *priv = (struct stm32_can_s *)arg; - - /* Ignore the notification if the interface is not yet up */ - - net_lock(); - if (priv->bifup) - { - /* Check if there is room in the hardware to hold another outgoing - * packet. - */ - - if (stm32can_txready(priv)) - { - /* No, there is space for another transfer. Poll the network for - * new XMIT data. - */ - - devif_poll(&priv->dev, stm32can_txpoll); - } - } - - net_unlock(); -} - -/**************************************************************************** - * Function: stm32can_txavail - * - * Description: - * Driver callback invoked when new TX data is available. This is a - * stimulus perform an out-of-cycle poll and, thereby, reduce the TX - * latency. - * - * Input Parameters: - * dev - Reference to the NuttX driver state structure - * - * Returned Value: - * None - * - * Assumptions: - * Called in normal user mode - * - ****************************************************************************/ - -static int stm32can_txavail(struct net_driver_s *dev) -{ - struct stm32_can_s *priv = (struct stm32_can_s *)dev->d_private; - - /* Is our single work structure available? It may not be if there are - * pending interrupt actions and we will have to ignore the Tx - * availability action. - */ - - if (work_available(&priv->pollwork)) - { - /* Schedule to serialize the poll on the worker thread. */ - - stm32can_txavail_work(priv); - } - - return OK; -} - -/**************************************************************************** - * Function: stm32can_ioctl - * - * Description: - * PHY ioctl command handler - * - * Input Parameters: - * dev - Reference to the NuttX driver state structure - * cmd - ioctl command - * arg - Argument accompanying the command - * - * Returned Value: - * Zero (OK) on success; a negated errno value on failure. - * - * Assumptions: - * - ****************************************************************************/ - -#ifdef CONFIG_NETDEV_IOCTL -static int stm32can_netdev_ioctl(struct net_driver_s *dev, int cmd, - unsigned long arg) -{ - struct stm32_can_s *priv = (struct stm32_can_s *)dev->d_private; - int ret = OK; - - switch (cmd) - { - /* TODO */ - - default: - ret = -ENOTTY; - break; - } - - return ret; -} -#endif /* CONFIG_NETDEV_IOCTL */ - -/**************************************************************************** - * Name: stm32can_rxinterrupt_work - * - * Description: - * CAN RX FIFO 0/1 interrupt handler - * - * Input Parameters: - * irq - The IRQ number of the interrupt. - * context - The register state save array at the time of the interrupt. - * rxmb - The RX mailbox number. - * - * Returned Value: - * Zero on success; a negated errno on failure - * - ****************************************************************************/ - -static int stm32can_rxinterrupt_work(struct stm32_can_s *priv, int rxmb) -{ - struct can_frame *frame = (struct can_frame *)priv->rxdesc; - uint32_t regval; - int ret = OK; - - DEBUGASSERT(priv != NULL); - - if (rxmb == 0) - { - stm32can_dumpmbregs(priv, "RX0 interrupt"); - } - else - { - stm32can_dumpmbregs(priv, "RX1 interrupt"); - } - - /* Get the CAN identifier. */ - - regval = stm32can_getreg(priv, STM32_CAN_RIR_OFFSET(rxmb)); - -#ifdef CONFIG_NET_CAN_EXTID - if ((regval & CAN_RIR_IDE) != 0) - { - frame->can_id = (regval & CAN_RIR_EXID_MASK) >> CAN_RIR_EXID_SHIFT; - frame->can_id |= CAN_EFF_FLAG; - } - else - { - frame->can_id = (regval & CAN_RIR_STID_MASK) >> CAN_RIR_STID_SHIFT; - } -#else - if ((regval & CAN_RIR_IDE) != 0) - { - nerr("ERROR: Received message with extended identifier. Dropped\n"); - ret = -ENOSYS; - goto errout; - } - - frame->can_id = (regval & CAN_RIR_STID_MASK) >> CAN_RIR_STID_SHIFT; -#endif - - /* Extract the RTR bit */ - - if ((regval & CAN_RIR_RTR) != 0) - { - frame->can_id |= CAN_RTR_FLAG; - } - - /* Get the DLC */ - - regval = stm32can_getreg(priv, STM32_CAN_RDTR_OFFSET(rxmb)); - frame->can_dlc = (regval & CAN_RDTR_DLC_MASK) >> CAN_RDTR_DLC_SHIFT; - - /* Save the message data */ - - regval = stm32can_getreg(priv, STM32_CAN_RDLR_OFFSET(rxmb)); - frame->data[0] = (regval & CAN_RDLR_DATA0_MASK) >> CAN_RDLR_DATA0_SHIFT; - frame->data[1] = (regval & CAN_RDLR_DATA1_MASK) >> CAN_RDLR_DATA1_SHIFT; - frame->data[2] = (regval & CAN_RDLR_DATA2_MASK) >> CAN_RDLR_DATA2_SHIFT; - frame->data[3] = (regval & CAN_RDLR_DATA3_MASK) >> CAN_RDLR_DATA3_SHIFT; - - regval = stm32can_getreg(priv, STM32_CAN_RDHR_OFFSET(rxmb)); - frame->data[4] = (regval & CAN_RDHR_DATA4_MASK) >> CAN_RDHR_DATA4_SHIFT; - frame->data[5] = (regval & CAN_RDHR_DATA5_MASK) >> CAN_RDHR_DATA5_SHIFT; - frame->data[6] = (regval & CAN_RDHR_DATA6_MASK) >> CAN_RDHR_DATA6_SHIFT; - frame->data[7] = (regval & CAN_RDHR_DATA7_MASK) >> CAN_RDHR_DATA7_SHIFT; - - /* Copy the buffer pointer to priv->dev.. Set amount of data - * in priv->dev.d_len - */ - - priv->dev.d_len = sizeof(struct can_frame); - priv->dev.d_buf = (uint8_t *)frame; - - /* Send to socket interface */ - - NETDEV_RXPACKETS(&priv->dev); - - can_input(&priv->dev); - - /* Point the packet buffer back to the next Tx buffer that will be - * used during the next write. If the write queue is full, then - * this will point at an active buffer, which must not be written - * to. This is OK because devif_poll won't be called unless the - * queue is not full. - */ - - priv->dev.d_buf = (uint8_t *)priv->txdesc; - - /* Release the FIFO */ - -#ifndef CONFIG_NET_CAN_EXTID -errout: -#endif - regval = stm32can_getreg(priv, STM32_CAN_RFR_OFFSET(rxmb)); - regval |= CAN_RFR_RFOM; - stm32can_putreg(priv, STM32_CAN_RFR_OFFSET(rxmb), regval); - - /* Re-enable CAN RX interrupts */ - - if (rxmb == 0) - { - stm32can_rx0int(priv, true); - } - else if (rxmb == 1) - { - stm32can_rx1int(priv, true); - } - else - { - DEBUGPANIC(); - } - - return ret; -} - -/**************************************************************************** - * Name: stm32can_rx0interrupt_work - ****************************************************************************/ - -static void stm32can_rx0interrupt_work(void *arg) -{ - struct stm32_can_s *priv = (struct stm32_can_s *)arg; - stm32can_rxinterrupt_work(priv, 0); -} - -/**************************************************************************** - * Name: stm32can_rx1interrupt_work - ****************************************************************************/ - -static void stm32can_rx1interrupt_work(void *arg) -{ - struct stm32_can_s *priv = (struct stm32_can_s *)arg; - stm32can_rxinterrupt_work(priv, 1); -} - -/**************************************************************************** - * Name: stm32can_rxinterrupt - * - * Description: - * CAN RX FIFO common interrupt handler - * - ****************************************************************************/ - -static int stm32can_rxinterrupt(struct stm32_can_s *priv, int rxmb) -{ - uint32_t regval = 0; - int npending = 0; - - /* Verify that a message is pending in the FIFO */ - - regval = stm32can_getreg(priv, STM32_CAN_RFR_OFFSET(rxmb)); - npending = (regval & CAN_RFR_FMP_MASK) >> CAN_RFR_FMP_SHIFT; - if (npending < 1) - { - nwarn("WARNING: No messages pending\n"); - return OK; - } - - /* Disable further CAN RX interrupts and schedule to perform the - * interrupt processing on the worker thread - */ - - if (rxmb == 0) - { - stm32can_rx0int(priv, false); - work_queue(CANWORK, &priv->irqwork, - stm32can_rx0interrupt_work, priv, 0); - } - else if (rxmb == 1) - { - stm32can_rx1int(priv, false); - work_queue(CANWORK, &priv->irqwork, - stm32can_rx1interrupt_work, priv, 0); - } - else - { - DEBUGPANIC(); - } - - return OK; -} - -/**************************************************************************** - * Name: stm32can_rx0interrupt - * - * Description: - * CAN RX FIFO 0 interrupt handler - * - * Input Parameters: - * irq - The IRQ number of the interrupt. - * context - The register state save array at the time of the interrupt. - * - * Returned Value: - * Zero on success; a negated errno on failure - * - ****************************************************************************/ - -static int stm32can_rx0interrupt(int irq, void *context, void *arg) -{ - struct stm32_can_s *priv = (struct stm32_can_s *)arg; - return stm32can_rxinterrupt(priv, 0); -} - -/**************************************************************************** - * Name: stm32can_rx1interrupt - * - * Description: - * CAN RX FIFO 1 interrupt handler - * - * Input Parameters: - * irq - The IRQ number of the interrupt. - * context - The register state save array at the time of the interrupt. - * - * Returned Value: - * Zero on success; a negated errno on failure - * - ****************************************************************************/ - -static int stm32can_rx1interrupt(int irq, void *context, void *arg) -{ - struct stm32_can_s *priv = (struct stm32_can_s *)arg; - return stm32can_rxinterrupt(priv, 1); -} - -/**************************************************************************** - * Name: stm32can_txinterrupt - * - * Description: - * CAN TX mailbox complete interrupt handler - * - * Input Parameters: - * irq - The IRQ number of the interrupt. - * context - The register state save array at the time of the interrupt. - * - * Returned Value: - * Zero on success; a negated errno on failure - * - ****************************************************************************/ - -static int stm32can_txinterrupt(int irq, void *context, void *arg) -{ - struct stm32_can_s *priv = (struct stm32_can_s *)arg; - uint32_t regval; - - DEBUGASSERT(priv != NULL); - - /* Get the transmit status */ - - regval = stm32can_getreg(priv, STM32_CAN_TSR_OFFSET); - - /* Check for RQCP0: Request completed mailbox 0 */ - - if ((regval & CAN_TSR_RQCP0) != 0) - { - /* Writing '1' to RCP0 clears RCP0 and all the status bits (TXOK0, - * ALST0 and TERR0) for Mailbox 0. - */ - - stm32can_putreg(priv, STM32_CAN_TSR_OFFSET, CAN_TSR_RQCP0); - - /* Tell the upper half that the transfer is finished. */ - - /* Disable further TX CAN interrupts. here can be no race - * condition here. - */ - - stm32can_txint(priv, false); - work_queue(CANWORK, &priv->irqwork, stm32can_txdone_work, priv, 0); - } - - /* Check for RQCP1: Request completed mailbox 1 */ - - if ((regval & CAN_TSR_RQCP1) != 0) - { - /* Writing '1' to RCP1 clears RCP1 and all the status bits (TXOK1, - * ALST1 and TERR1) for Mailbox 1. - */ - - stm32can_putreg(priv, STM32_CAN_TSR_OFFSET, CAN_TSR_RQCP1); - - /* Tell the upper half that the transfer is finished. */ - - /* Disable further TX CAN interrupts. here can be no race - * condition here. - */ - - stm32can_txint(priv, false); - work_queue(CANWORK, &priv->irqwork, stm32can_txdone_work, priv, 0); - } - - /* Check for RQCP2: Request completed mailbox 2 */ - - if ((regval & CAN_TSR_RQCP2) != 0) - { - /* Writing '1' to RCP2 clears RCP2 and all the status bits (TXOK2, - * ALST2 and TERR2) for Mailbox 2. - */ - - stm32can_putreg(priv, STM32_CAN_TSR_OFFSET, CAN_TSR_RQCP2); - - /* Disable further TX CAN interrupts. here can be no race - * condition here. - */ - - stm32can_txint(priv, false); - work_queue(CANWORK, &priv->irqwork, stm32can_txdone_work, priv, 0); - } - - return OK; -} - -/**************************************************************************** - * Name: stm32can_txdone_work - ****************************************************************************/ - -static void stm32can_txdone_work(void *arg) -{ - struct stm32_can_s *priv = (struct stm32_can_s *)arg; - - stm32can_txdone(priv); - - /* There should be space for a new TX in any event. Poll the network for - * new XMIT data - */ - - net_lock(); - devif_poll(&priv->dev, stm32can_txpoll); - net_unlock(); -} - -/**************************************************************************** - * Name: stm32can_txdone - ****************************************************************************/ - -static void stm32can_txdone(struct stm32_can_s *priv) -{ - stm32can_txint(priv, true); - - NETDEV_TXDONE(&priv->dev); -} - -#ifdef CONFIG_NET_CAN_ERRORS - -/**************************************************************************** - * Name: stm32can_sceinterrupt_work - * - * Description: - * CAN status change interrupt work - * - * Input Parameters: - * arg - reference to the driver state structure - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void stm32can_sceinterrupt_work(void *arg) -{ - struct stm32_can_s *priv = (struct stm32_can_s *)arg; - struct can_frame *frame = (struct can_frame *)priv->rxdesc; - uint32_t regval = 0; - uint16_t errbits = 0; - uint8_t data[CAN_ERR_DLC]; - - DEBUGASSERT(priv != NULL); - - /* Check Error Interrupt flag */ - - regval = stm32can_getreg(priv, STM32_CAN_MSR_OFFSET); - if (regval & CAN_MSR_ERRI) - { - /* Encode error bits */ - - errbits = 0; - memset(data, 0, sizeof(data)); - - /* Get Error statur register */ - - regval = stm32can_getreg(priv, STM32_CAN_ESR_OFFSET); - - if (regval & CAN_ESR_EWGF) - { - /* Error warning flag */ - - data[1] |= (CAN_ERR_CRTL_RX_WARNING | CAN_ERR_CRTL_TX_WARNING); - errbits |= CAN_ERR_CRTL; - } - - if (regval & CAN_ESR_EPVF) - { - /* Error passive flag */ - - data[1] |= (CAN_ERR_CRTL_RX_PASSIVE | CAN_ERR_CRTL_TX_PASSIVE); - errbits |= CAN_ERR_CRTL; - } - - if (regval & CAN_ESR_BOFF) - { - /* Bus-off flag */ - - errbits |= CAN_ERR_BUSOFF; - } - - /* Last error code */ - - if (regval & CAN_ESR_LEC_MASK) - { - if (regval & CAN_ESR_STUFFERROR) - { - /* Stuff Error */ - - errbits |= CAN_ERR_PROT; - data[2] |= CAN_ERR_PROT_STUFF; - } - else if (regval & CAN_ESR_FORMERROR) - { - /* Format Error */ - - errbits |= CAN_ERR_PROT; - data[2] |= CAN_ERR_PROT_FORM; - } - else if (regval & CAN_ESR_ACKERROR) - { - /* Acknowledge Error */ - - errbits |= CAN_ERR_ACK; - } - else if (regval & CAN_ESR_BRECERROR) - { - /* Bit recessive Error */ - - errbits |= CAN_ERR_PROT; - data[2] |= CAN_ERR_PROT_BIT1; - } - else if (regval & CAN_ESR_BDOMERROR) - { - /* Bit dominant Error */ - - errbits |= CAN_ERR_PROT; - data[2] |= CAN_ERR_PROT_BIT0; - } - else if (regval & CAN_ESR_CRCERRPR) - { - /* Receive CRC Error */ - - errbits |= CAN_ERR_PROT; - data[3] |= CAN_ERR_PROT_LOC_CRC_SEQ; - } - } - - /* Get transmit status register */ - - regval = stm32can_getreg(priv, STM32_CAN_TSR_OFFSET); - - if (regval & CAN_TSR_ALST0 || regval & CAN_TSR_ALST1 || - regval & CAN_TSR_ALST2) - { - /* Lost arbitration Error */ - - errbits |= CAN_ERR_LOSTARB; - } - - /* Clear TSR register */ - - stm32can_putreg(priv, STM32_CAN_TSR_OFFSET, regval); - - /* Clear ERRI flag */ - - stm32can_putreg(priv, STM32_CAN_MSR_OFFSET, CAN_MSR_ERRI); - } - - /* Report a CAN error */ - - if (errbits != 0) - { - canerr("ERROR: errbits = %08" PRIx16 "\n", errbits); - - /* Copy frame */ - - frame->can_id = errbits; - frame->can_dlc = CAN_ERR_DLC; - - memcpy(frame->data, data, CAN_ERR_DLC); - - net_lock(); - - /* Copy the buffer pointer to priv->dev.. Set amount of data - * in priv->dev.d_len - */ - - priv->dev.d_len = sizeof(struct can_frame); - priv->dev.d_buf = (uint8_t *)frame; - - /* Send to socket interface */ - - NETDEV_ERRORS(&priv->dev); - - can_input(&priv->dev); - - /* Point the packet buffer back to the next Tx buffer that will be - * used during the next write. If the write queue is full, then - * this will point at an active buffer, which must not be written - * to. This is OK because devif_poll won't be called unless the - * queue is not full. - */ - - priv->dev.d_buf = (uint8_t *)priv->txdesc; - net_unlock(); - } - - /* Re-enable CAN SCE interrupts */ - - stm32can_errint(priv, true); -} - -/**************************************************************************** - * Name: stm32can_sceinterrupt - * - * Description: - * CAN status change interrupt handler - * - * Input Parameters: - * irq - The IRQ number of the interrupt. - * context - The register state save array at the time of the interrupt. - * - * Returned Value: - * Zero on success; a negated errno on failure - * - ****************************************************************************/ - -static int stm32can_sceinterrupt(int irq, void *context, void *arg) -{ - struct stm32_can_s *priv = (struct stm32_can_s *)arg; - - /* Disable further CAN SCE interrupts and schedule to perform the - * interrupt processing on the worker thread - */ - - stm32can_errint(priv, false); - work_queue(CANWORK, &priv->irqwork, - stm32can_sceinterrupt_work, priv, 0); - - return OK; -} -#endif - -/**************************************************************************** - * Name: stm32can_bittiming - * - * Description: - * Set the CAN bit timing register (BTR) based on the configured BAUD. - * - * "The bit timing logic monitors the serial bus-line and performs sampling - * and adjustment of the sample point by synchronizing on the start-bit edge - * and resynchronizing on the following edges. - * - * "Its operation may be explained simply by splitting nominal bit time into - * three segments as follows: - * - * 1. "Synchronization segment (SYNC_SEG): a bit change is expected to occur - * within this time segment. It has a fixed length of one time quantum - * (1 x tCAN). - * 2. "Bit segment 1 (BS1): defines the location of the sample point. It - * includes the PROP_SEG and PHASE_SEG1 of the CAN standard. Its duration - * is programmable between 1 and 16 time quanta but may be automatically - * lengthened to compensate for positive phase drifts due to differences - * in the frequency of the various nodes of the network. - * 3. "Bit segment 2 (BS2): defines the location of the transmit point. It - * represents the PHASE_SEG2 of the CAN standard. Its duration is - * programmable between 1 and 8 time quanta but may also be automatically - * shortened to compensate for negative phase drifts." - * - * Pictorially: - * - * |<----------------- NOMINAL BIT TIME ----------------->| - * |<- SYNC_SEG ->|<------ BS1 ------>|<------ BS2 ------>| - * |<---- Tq ---->|<----- Tbs1 ------>|<----- Tbs2 ------>| - * - * Where - * Tbs1 is the duration of the BS1 segment - * Tbs2 is the duration of the BS2 segment - * Tq is the "Time Quantum" - * - * Relationships: - * - * baud = 1 / bit_time - * bit_time = Tq + Tbs1 + Tbs2 - * Tbs1 = Tq * ts1 - * Tbs2 = Tq * ts2 - * Tq = brp * Tpclk1 - * baud = Fpclk1 / (brp * (1 + ts1 + ts2)) - * - * Where: - * Tpclk1 is the period of the APB1 clock (PCLK1). - * - * Input Parameters: - * priv - reference to the private CAN driver state structure - * - * Returned Value: - * Zero on success; a negated errno on failure - * - ****************************************************************************/ - -static int stm32can_bittiming(struct stm32_can_s *priv) -{ - uint32_t tmp; - uint32_t brp; - uint32_t ts1; - uint32_t ts2; - - ninfo("CAN%" PRIu8 " PCLK1: %lu baud: %" PRIu32 "\n", - priv->port, (unsigned long) STM32_PCLK1_FREQUENCY, priv->baud); - - /* Try to get CAN_BIT_QUANTA quanta in one bit_time. - * - * bit_time = Tq*(ts1 + ts2 + 1) - * nquanta = bit_time / Tq - * nquanta = (ts1 + ts2 + 1) - * - * bit_time = brp * Tpclk1 * (ts1 + ts2 + 1) - * nquanta = bit_time / brp / Tpclk1 - * = PCLK1 / baud / brp - * brp = PCLK1 / baud / nquanta; - * - * Example: - * PCLK1 = 42,000,000 baud = 1,000,000 nquanta = 14 : brp = 3 - * PCLK1 = 42,000,000 baud = 700,000 nquanta = 14 : brp = 4 - */ - - tmp = STM32_PCLK1_FREQUENCY / priv->baud; - if (tmp < CAN_BIT_QUANTA) - { - /* At the smallest brp value (1), there are already too few bit times - * (PCLCK1 / baud) to meet our goal. brp must be one and we need - * make some reasonable guesses about ts1 and ts2. - */ - - brp = 1; - - /* In this case, we have to guess a good value for ts1 and ts2 */ - - ts1 = (tmp - 1) >> 1; - ts2 = tmp - ts1 - 1; - if (ts1 == ts2 && ts1 > 1 && ts2 < CAN_BTR_TSEG2_MAX) - { - ts1--; - ts2++; - } - } - - /* Otherwise, nquanta is CAN_BIT_QUANTA, ts1 is CONFIG_STM32_CAN_TSEG1, - * ts2 is CONFIG_STM32_CAN_TSEG2 and we calculate brp to achieve - * CAN_BIT_QUANTA quanta in the bit time - */ - - else - { - ts1 = CONFIG_STM32_CAN_TSEG1; - ts2 = CONFIG_STM32_CAN_TSEG2; - brp = (tmp + (CAN_BIT_QUANTA / 2)) / CAN_BIT_QUANTA; - DEBUGASSERT(brp >= 1 && brp <= CAN_BTR_BRP_MAX); - } - - ninfo("TS1: %" PRIu32 " TS2: %" PRIu32 " BRP: %" PRIu32 "\n", - ts1, ts2, brp); - - /* Configure bit timing. This also does the following, less obvious - * things. Unless loopback mode is enabled, it: - * - * - Disables silent mode. - * - Disables loopback mode. - * - * NOTE that for the time being, SJW is set to 1 just because I don't - * know any better. - */ - - tmp = ((brp - 1) << CAN_BTR_BRP_SHIFT) | ((ts1 - 1) << CAN_BTR_TS1_SHIFT) | - ((ts2 - 1) << CAN_BTR_TS2_SHIFT) | ((1 - 1) << CAN_BTR_SJW_SHIFT); -#ifdef CONFIG_CAN_LOOPBACK - /* tmp |= (CAN_BTR_LBKM | CAN_BTR_SILM); */ - - tmp |= CAN_BTR_LBKM; -#endif - - stm32can_putreg(priv, STM32_CAN_BTR_OFFSET, tmp); - return OK; -} - -/**************************************************************************** - * Name: stm32can_setup - ****************************************************************************/ - -static int stm32can_setup(struct stm32_can_s *priv) -{ - int ret; - -#ifdef CONFIG_NET_CAN_ERRORS - ninfo("CAN%" PRIu8 " RX0 irq: %" PRIu8 " RX1 irq: %" PRIu8 - " TX irq: %" PRIu8 " SCE irq: %" PRIu8 "\n", - priv->port, priv->canrx[0], priv->canrx[1], priv->cantx, - priv->cansce); -#else - ninfo("CAN%" PRIu8 " RX0 irq: %" PRIu8 " RX1 irq: %" PRIu8 - " TX irq: %" PRIu8 "\n", - priv->port, priv->canrx[0], priv->canrx[1], priv->cantx); -#endif - - /* CAN cell initialization */ - - ret = stm32can_cellinit(priv); - if (ret < 0) - { - nerr("ERROR: CAN%" PRId8 " cell initialization failed: %d\n", - priv->port, ret); - return ret; - } - - stm32can_dumpctrlregs(priv, "After cell initialization"); - stm32can_dumpmbregs(priv, NULL); - - /* CAN filter initialization */ - - ret = stm32can_filterinit(priv); - if (ret < 0) - { - nerr("ERROR: CAN%" PRIu8 " filter initialization failed: %d\n", - priv->port, ret); - return ret; - } - - stm32can_dumpfiltregs(priv, "After filter initialization"); - - /* Attach the CAN RX FIFO 0/1 interrupts and TX interrupts. - * The others are not used. - */ - - ret = irq_attach(priv->canrx[0], stm32can_rx0interrupt, priv); - if (ret < 0) - { - nerr("ERROR: Failed to attach CAN%" PRIu8 " RX0 IRQ (%" PRIu8 ")", - priv->port, priv->canrx[0]); - return ret; - } - - ret = irq_attach(priv->canrx[1], stm32can_rx1interrupt, priv); - if (ret < 0) - { - nerr("ERROR: Failed to attach CAN%" PRIu8 " RX1 IRQ (%" PRIu8 ")", - priv->port, priv->canrx[1]); - return ret; - } - - ret = irq_attach(priv->cantx, stm32can_txinterrupt, priv); - if (ret < 0) - { - nerr("ERROR: Failed to attach CAN%" PRIu8 " TX IRQ (%" PRIu8 ")", - priv->port, priv->cantx); - return ret; - } - -#ifdef CONFIG_NET_CAN_ERRORS - ret = irq_attach(priv->cansce, stm32can_sceinterrupt, priv); - if (ret < 0) - { - nerr("ERROR: Failed to attach CAN%" PRIu8 " SCE IRQ (%" PRIu8 ")", - priv->port, priv->cansce); - return ret; - } -#endif - - return OK; -} - -/**************************************************************************** - * Name: stm32can_shutdown - ****************************************************************************/ - -static void stm32can_shutdown(struct stm32_can_s *priv) -{ - ninfo("CAN%" PRIu8 "\n", priv->port); - - /* Disable the RX FIFO 0/1 and TX interrupts */ - - up_disable_irq(priv->canrx[0]); - up_disable_irq(priv->canrx[1]); - up_disable_irq(priv->cantx); -#ifdef CONFIG_NET_CAN_ERRORS - up_disable_irq(priv->cansce); -#endif - - /* Detach the RX FIFO 0/1 and TX interrupts */ - - irq_detach(priv->canrx[0]); - irq_detach(priv->canrx[1]); - irq_detach(priv->cantx); -#ifdef CONFIG_NET_CAN_ERRORS - irq_detach(priv->cansce); -#endif -} - -/**************************************************************************** - * Name: stm32can_reset - * - * Description: - * Put the CAN device in the non-operational, reset state - * - * Input Parameters: - * priv - reference to the private CAN driver state structure - * - * Returned Value: - * None - * - * Assumptions: - * - ****************************************************************************/ - -static void stm32can_reset(struct stm32_can_s *priv) -{ - uint32_t regval; - uint32_t regbit = 0; - irqstate_t flags; - - ninfo("CAN%" PRIu8 "\n", priv->port); - - /* Get the bits in the AHB1RSTR register needed to reset this CAN device */ - -#ifdef CONFIG_STM32_CAN1 - if (priv->port == 1) - { - regbit = RCC_APB1RSTR_CAN1RST; - } - else -#endif -#ifdef CONFIG_STM32_CAN2 - if (priv->port == 2) - { - regbit = RCC_APB1RSTR_CAN2RST; - } - else -#endif - { - nerr("ERROR: Unsupported port %d\n", priv->port); - return; - } - - /* Disable interrupts momentarily to stop any ongoing CAN event processing - * and to prevent any concurrent access to the AHB1RSTR register. - */ - - flags = enter_critical_section(); - - /* Reset the CAN */ - - regval = getreg32(STM32_RCC_APB1RSTR); - regval |= regbit; - putreg32(regval, STM32_RCC_APB1RSTR); - - regval &= ~regbit; - putreg32(regval, STM32_RCC_APB1RSTR); - leave_critical_section(flags); -} - -/**************************************************************************** - * Name: stm32can_enterinitmode - * - * Description: - * Put the CAN cell in Initialization mode. This only disconnects the CAN - * peripheral, no registers are changed. The initialization mode is - * required to change the baud rate. - * - * Input Parameters: - * priv - reference to the private CAN driver state structure - * - * Returned Value: - * Zero on success; a negated errno value on failure. - * - ****************************************************************************/ - -static int stm32can_enterinitmode(struct stm32_can_s *priv) -{ - uint32_t regval; - volatile uint32_t timeout; - - ninfo("CAN%" PRIu8 "\n", priv->port); - - /* Enter initialization mode */ - - regval = stm32can_getreg(priv, STM32_CAN_MCR_OFFSET); - regval |= CAN_MCR_INRQ; - stm32can_putreg(priv, STM32_CAN_MCR_OFFSET, regval); - - /* Wait until initialization mode is acknowledged */ - - for (timeout = INAK_TIMEOUT; timeout > 0; timeout--) - { - regval = stm32can_getreg(priv, STM32_CAN_MSR_OFFSET); - if ((regval & CAN_MSR_INAK) != 0) - { - /* We are in initialization mode */ - - break; - } - } - - /* Check for a timeout */ - - if (timeout < 1) - { - nerr("ERROR: Timed out waiting to enter initialization mode\n"); - return -ETIMEDOUT; - } - - return OK; -} - -/**************************************************************************** - * Name: stm32can_exitinitmode - * - * Description: - * Put the CAN cell out of the Initialization mode (to Normal mode) - * - * Input Parameters: - * priv - reference to the private CAN driver state structure - * - * Returned Value: - * Zero on success; a negated errno value on failure. - * - ****************************************************************************/ - -static int stm32can_exitinitmode(struct stm32_can_s *priv) -{ - uint32_t regval; - volatile uint32_t timeout; - - /* Exit Initialization mode, enter Normal mode */ - - regval = stm32can_getreg(priv, STM32_CAN_MCR_OFFSET); - regval &= ~CAN_MCR_INRQ; - stm32can_putreg(priv, STM32_CAN_MCR_OFFSET, regval); - - /* Wait until the initialization mode exit is acknowledged */ - - for (timeout = INAK_TIMEOUT; timeout > 0; timeout--) - { - regval = stm32can_getreg(priv, STM32_CAN_MSR_OFFSET); - if ((regval & CAN_MSR_INAK) == 0) - { - /* We are out of initialization mode */ - - break; - } - } - - /* Check for a timeout */ - - if (timeout < 1) - { - nerr("ERROR: Timed out waiting to exit initialization mode: %08" - PRIx32 "\n", regval); - return -ETIMEDOUT; - } - - return OK; -} - -/**************************************************************************** - * Name: stm32can_cellinit - * - * Description: - * CAN cell initialization - * - * Input Parameters: - * priv - reference to the private CAN driver state structure - * - * Returned Value: - * Zero on success; a negated errno value on failure. - * - ****************************************************************************/ - -static int stm32can_cellinit(struct stm32_can_s *priv) -{ - uint32_t regval; - int ret; - - ninfo("CAN%" PRIu8 "\n", priv->port); - - /* Exit from sleep mode */ - - regval = stm32can_getreg(priv, STM32_CAN_MCR_OFFSET); - regval &= ~CAN_MCR_SLEEP; - stm32can_putreg(priv, STM32_CAN_MCR_OFFSET, regval); - - ret = stm32can_enterinitmode(priv); - if (ret != 0) - { - return ret; - } - - /* Disable the following modes: - * - * - Time triggered communication mode - * - Automatic bus-off management - * - Automatic wake-up mode - * - No automatic retransmission - * - Receive FIFO locked mode - * - * Enable: - * - * - Transmit FIFO priority - */ - - regval = stm32can_getreg(priv, STM32_CAN_MCR_OFFSET); - regval &= ~(CAN_MCR_RFLM | CAN_MCR_NART | CAN_MCR_AWUM | - CAN_MCR_ABOM | CAN_MCR_TTCM); - regval |= CAN_MCR_TXFP; - stm32can_putreg(priv, STM32_CAN_MCR_OFFSET, regval); - - /* Configure bit timing. */ - - ret = stm32can_bittiming(priv); - if (ret < 0) - { - nerr("ERROR: Failed to set bit timing: %d\n", ret); - return ret; - } - - return stm32can_exitinitmode(priv); -} - -/**************************************************************************** - * Name: stm32can_filterinit - * - * Description: - * CAN filter initialization. CAN filters are not currently used by this - * driver. The CAN filters can be configured in a different way: - * - * 1. As a match of specific IDs in a list (IdList mode), or as - * 2. And ID and a mask (IdMask mode). - * - * Filters can also be configured as: - * - * 3. 16- or 32-bit. The advantage of 16-bit filters is that you get - * more filters; The advantage of 32-bit filters is that you get - * finer control of the filtering. - * - * One filter is set up for each CAN. The filter resources are shared - * between the two CAN modules: CAN1 uses only filter 0 (but reserves - * 0 through CAN_NFILTERS/2-1); CAN2 uses only filter CAN_NFILTERS/2 - * (but reserves CAN_NFILTERS/2 through CAN_NFILTERS-1). - * - * 32-bit IdMask mode is configured. However, both the ID and the MASK - * are set to zero thus suppressing all filtering because anything masked - * with zero matches zero. - * - * Input Parameters: - * priv - reference to the private CAN driver state structure - * - * Returned Value: - * Zero on success; a negated errno value on failure. - * - ****************************************************************************/ - -static int stm32can_filterinit(struct stm32_can_s *priv) -{ - uint32_t regval; - uint32_t bitmask; - - ninfo("CAN%" PRIu8 " filter: %" PRIu8 "\n", priv->port, priv->filter); - - /* Get the bitmask associated with the filter used by this CAN block */ - - bitmask = (uint32_t)1 << priv->filter; - - /* Enter filter initialization mode */ - - regval = stm32can_getfreg(priv, STM32_CAN_FMR_OFFSET); - regval |= CAN_FMR_FINIT; - stm32can_putfreg(priv, STM32_CAN_FMR_OFFSET, regval); - - /* Assign half the filters to CAN1, half to CAN2 */ - -#if defined(CONFIG_STM32_CONNECTIVITYLINE) || \ - defined(CONFIG_STM32_STM32F20XX) || \ - defined(CONFIG_STM32_STM32F4XXX) - regval = stm32can_getfreg(priv, STM32_CAN_FMR_OFFSET); - regval &= CAN_FMR_CAN2SB_MASK; - regval |= (CAN_NFILTERS / 2) << CAN_FMR_CAN2SB_SHIFT; - stm32can_putfreg(priv, STM32_CAN_FMR_OFFSET, regval); -#endif - - /* Disable the filter */ - - regval = stm32can_getfreg(priv, STM32_CAN_FA1R_OFFSET); - regval &= ~bitmask; - stm32can_putfreg(priv, STM32_CAN_FA1R_OFFSET, regval); - - /* Select the 32-bit scale for the filter */ - - regval = stm32can_getfreg(priv, STM32_CAN_FS1R_OFFSET); - regval |= bitmask; - stm32can_putfreg(priv, STM32_CAN_FS1R_OFFSET, regval); - - /* There are 14 or 28 filter banks (depending) on the device. - * Each filter bank is composed of two 32-bit registers, CAN_FiR: - */ - - stm32can_putfreg(priv, STM32_CAN_FIR_OFFSET(priv->filter, 1), 0); - stm32can_putfreg(priv, STM32_CAN_FIR_OFFSET(priv->filter, 2), 0); - - /* Set Id/Mask mode for the filter */ - - regval = stm32can_getfreg(priv, STM32_CAN_FM1R_OFFSET); - regval &= ~bitmask; - stm32can_putfreg(priv, STM32_CAN_FM1R_OFFSET, regval); - - /* Assign FIFO 0 for the filter */ - - regval = stm32can_getfreg(priv, STM32_CAN_FFA1R_OFFSET); - regval &= ~bitmask; - stm32can_putfreg(priv, STM32_CAN_FFA1R_OFFSET, regval); - - /* Enable the filter */ - - regval = stm32can_getfreg(priv, STM32_CAN_FA1R_OFFSET); - regval |= bitmask; - stm32can_putfreg(priv, STM32_CAN_FA1R_OFFSET, regval); - - /* Exit filter initialization mode */ - - regval = stm32can_getfreg(priv, STM32_CAN_FMR_OFFSET); - regval &= ~CAN_FMR_FINIT; - stm32can_putfreg(priv, STM32_CAN_FMR_OFFSET, regval); - return OK; -} - -/**************************************************************************** - * Name: stm32can_txmb0empty - * - * Input Parameters: - * tsr_regval - value of CAN transmit status register - * - * Returned Value: - * Returns true if mailbox 0 is empty and can be used for sending. - * - ****************************************************************************/ - -static bool stm32can_txmb0empty(uint32_t tsr_regval) -{ - return (tsr_regval & CAN_TSR_TME0) != 0 && - (tsr_regval & CAN_TSR_RQCP0) == 0; -} - -/**************************************************************************** - * Name: stm32can_txmb1empty - * - * Input Parameters: - * tsr_regval - value of CAN transmit status register - * - * Returned Value: - * Returns true if mailbox 1 is empty and can be used for sending. - * - ****************************************************************************/ - -static bool stm32can_txmb1empty(uint32_t tsr_regval) -{ - return (tsr_regval & CAN_TSR_TME1) != 0 && - (tsr_regval & CAN_TSR_RQCP1) == 0; -} - -/**************************************************************************** - * Name: stm32can_txmb2empty - * - * Input Parameters: - * tsr_regval - value of CAN transmit status register - * - * Returned Value: - * Returns true if mailbox 2 is empty and can be used for sending. - * - ****************************************************************************/ - -static bool stm32can_txmb2empty(uint32_t tsr_regval) -{ - return (tsr_regval & CAN_TSR_TME2) != 0 && - (tsr_regval & CAN_TSR_RQCP2) == 0; -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_cansockinitialize - * - * Description: - * Initialize the selected CAN port as CAN socket interface - * - * Input Parameters: - * Port number (for hardware that has multiple CAN interfaces) - * - * Returned Value: - * OK on success; Negated errno on failure. - * - ****************************************************************************/ - -int stm32_cansockinitialize(int port) -{ - struct stm32_can_s *priv = NULL; - int ret = OK; - - ninfo("CAN%" PRIu8 "\n", port); - - /* NOTE: Peripherical clocking for CAN1 and/or CAN2 was already provided - * by stm32_clockconfig() early in the reset sequence. - */ - -#ifdef CONFIG_STM32_CAN1 - if (port == 1) - { - /* Select the CAN1 device structure */ - - priv = &g_can1priv; - - /* Configure CAN1 pins. The ambiguous settings in the stm32*_pinmap.h - * file must have been disambiguated in the board.h file. - */ - - stm32_configgpio(GPIO_CAN1_RX); - stm32_configgpio(GPIO_CAN1_TX); - } - else -#endif -#ifdef CONFIG_STM32_CAN2 - if (port == 2) - { - /* Select the CAN2 device structure */ - - priv = &g_can2priv; - - /* Configure CAN2 pins. The ambiguous settings in the stm32*_pinmap.h - * file must have been disambiguated in the board.h file. - */ - - stm32_configgpio(GPIO_CAN2_RX); - stm32_configgpio(GPIO_CAN2_TX); - } - else -#endif - { - nerr("ERROR: Unsupported port %d\n", port); - ret = -EINVAL; - goto errout; - } - - /* Initialize the driver structure */ - - priv->dev.d_ifup = stm32can_ifup; - priv->dev.d_ifdown = stm32can_ifdown; - priv->dev.d_txavail = stm32can_txavail; -#ifdef CONFIG_NETDEV_IOCTL - priv->dev.d_ioctl = stm32can_netdev_ioctl; -#endif - priv->dev.d_private = priv; - - /* Put the interface in the down state. This usually amounts to resetting - * the device and/or calling stm32can_ifdown(). - */ - - ninfo("callbacks done\n"); - - stm32can_ifdown(&priv->dev); - - /* Register the device with the OS so that socket IOCTLs can be performed */ - - ret = netdev_register(&priv->dev, NET_LL_CAN); - -errout: - return ret; -} - -/**************************************************************************** - * Name: arm_netinitialize - * - * Description: - * Initialize the CAN device interfaces. If there is more than one device - * interface in the chip, then board-specific logic will have to provide - * this function to determine which, if any, CAN interfaces should be - * initialized. - * - ****************************************************************************/ - -#if !defined(CONFIG_NETDEV_LATEINIT) -void arm_netinitialize(void) -{ -#ifdef CONFIG_STM32_CAN1 - stm32_cansockinitialize(1); -#endif - -#ifdef CONFIG_STM32_CAN2 - stm32_cansockinitialize(2); -#endif -} -#endif diff --git a/arch/arm/src/stm32/stm32_capture.c b/arch/arm/src/stm32/stm32_capture.c deleted file mode 100644 index 966f41a0a439f..0000000000000 --- a/arch/arm/src/stm32/stm32_capture.c +++ /dev/null @@ -1,1522 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_capture.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include -#include - -#include -#include -#include -#include -#include -#include - -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32.h" -#include "stm32_gpio.h" -#include "stm32_capture.h" - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/* Configuration ************************************************************/ - -#if defined(GPIO_TIM1_CH1IN) || defined(GPIO_TIM2_CH1IN) || defined(GPIO_TIM3_CH1IN) || \ - defined(GPIO_TIM4_CH1IN) || defined(GPIO_TIM5_CH1IN) || defined(GPIO_TIM8_CH1IN) || \ - defined(GPIO_TIM9_CH1IN) || defined(GPIO_TIM10_CH1IN) || defined(GPIO_TIM11_CH1IN) || \ - defined(GPIO_TIM12_CH1IN) || defined(GPIO_TIM13_CH1IN) || defined(GPIO_TIM14_CH1IN) -# define HAVE_CH1IN 1 -#endif - -#if defined(GPIO_TIM1_CH2IN) || defined(GPIO_TIM2_CH2IN) || defined(GPIO_TIM3_CH2IN) || \ - defined(GPIO_TIM4_CH2IN) || defined(GPIO_TIM5_CH2IN) || defined(GPIO_TIM8_CH2IN) || \ - defined(GPIO_TIM9_CH2IN) || defined(GPIO_TIM12_CH2IN) -# define HAVE_CH2IN 1 -#endif - -#if defined(GPIO_TIM1_CH3IN) || defined(GPIO_TIM2_CH3IN) || defined(GPIO_TIM3_CH3IN) || \ - defined(GPIO_TIM4_CH3IN) || defined(GPIO_TIM5_CH3IN) || defined(GPIO_TIM8_CH3IN) -# define HAVE_CH3IN 1 -#endif - -#if defined(GPIO_TIM1_CH4IN) || defined(GPIO_TIM2_CH4IN) || defined(GPIO_TIM3_CH4IN) || \ - defined(GPIO_TIM4_CH4IN) || defined(GPIO_TIM5_CH4IN) || defined(GPIO_TIM8_CH4IN) -# define HAVE_CH4IN 1 -#endif - -#if defined(CONFIG_STM32_TIM1_CAP) || defined(CONFIG_STM32_TIM8_CAP) -#define USE_ADVENCED_TIM 1 -#endif - -#if defined(GPIO_TIM1_EXT_CLK_IN) || defined(GPIO_TIM2_EXT_CLK_IN) || \ - defined(GPIO_TIM3_EXT_CLK_IN) || defined(GPIO_TIM4_EXT_CLK_IN) || \ - defined(GPIO_TIM5_EXT_CLK_IN) || defined(GPIO_TIM8_EXT_CLK_IN) || \ - defined(GPIO_TIM9_EXT_CLK_IN) || defined(GPIO_TIM12_EXT_CLK_IN) -# define USE_EXT_CLOCK 1 -#endif - -/* This module then only compiles if there are enabled timers that are not - * intended for some other purpose. - */ - -#if defined(CONFIG_STM32_TIM1_CAP) || defined(CONFIG_STM32_TIM2_CAP) || \ - defined(CONFIG_STM32_TIM3_CAP) || defined(CONFIG_STM32_TIM4_CAP) || \ - defined(CONFIG_STM32_TIM5_CAP) || defined(CONFIG_STM32_TIM8_CAP) || \ - defined(CONFIG_STM32_TIM9_CAP) || defined(CONFIG_STM32_TIM10_CAP) || \ - defined(CONFIG_STM32_TIM11_CAP) || defined(CONFIG_STM32_TIM12_CAP) || \ - defined(CONFIG_STM32_TIM13_CAP) || defined(CONFIG_STM32_TIM14_CAP) - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/* TIM Device Structure */ - -struct stm32_cap_priv_s -{ - const struct stm32_cap_ops_s *ops; - const uint32_t base; /* TIMn base address */ -#ifdef USE_EXT_CLOCK - const uint32_t gpio_clk; /* TIMn base address */ -#endif - const int irq; /* irq vector */ -#ifdef USE_ADVENCED_TIM - const int irq_of; /* irq timer overflow is deferent in advanced timer */ -#endif -}; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/* Get a 16-bit register value by offset */ - -static inline -uint16_t stm32_getreg16(const struct stm32_cap_priv_s *priv, - uint8_t offset) -{ - return getreg16(priv->base + offset); -} - -/* Put a 16-bit register value by offset */ - -static inline void stm32_putreg16(const struct stm32_cap_priv_s *priv, - uint8_t offset, uint16_t value) -{ - putreg16(value, priv->base + offset); -} - -/* Modify a 16-bit register value by offset */ - -static inline void stm32_modifyreg16(const struct stm32_cap_priv_s *priv, - uint8_t offset, uint16_t clearbits, - uint16_t setbits) -{ - modifyreg16(priv->base + offset, clearbits, setbits); -} - -/* Get a 32-bit register value by offset. This applies only for the STM32 F4 - * 32-bit registers (CNT, ARR, CRR1-4) in the 32-bit timers TIM2 and TIM5. - */ - -static inline -uint32_t stm32_getreg32(const struct stm32_cap_priv_s *priv, - uint8_t offset) -{ - return getreg32(priv->base + offset); -} - -/* Put a 32-bit register value by offset. This applies only for the STM32 F4 - * 32-bit registers (CNT, ARR, CRR1-4) in the 32-bit timers TIM2 and TIM5. - */ - -static inline void stm32_putreg32(const struct stm32_cap_priv_s *priv, - uint8_t offset, uint32_t value) -{ - putreg32(value, priv->base + offset); -} - -/**************************************************************************** - * gpio Functions - ****************************************************************************/ - -static inline -uint32_t stm32_cap_gpio(const struct stm32_cap_priv_s *priv, - int channel) -{ - switch (priv->base) - { -#ifdef CONFIG_STM32_TIM1_CAP - case STM32_TIM1_BASE: - switch (channel) - { -#ifdef GPIO_TIM1_EXT_CLK_IN - case STM32_CAP_CHANNEL_COUNTER: - return GPIO_TIM1_EXT_CLK_IN; -#endif -#ifdef GPIO_TIM1_CH1IN - case 1: - return GPIO_TIM1_CH1IN; -#endif -#ifdef GPIO_TIM1_CH2IN - case 2: - return GPIO_TIM1_CH2IN; -#endif -#ifdef GPIO_TIM1_CH3IN - case 3: - return GPIO_TIM1_CH3IN; -#endif -#ifdef GPIO_TIM1_CH4IN - case 4: - return GPIO_TIM1_CH4IN; -#endif - } - break; -#endif -#ifdef CONFIG_STM32_TIM2_CAP - case STM32_TIM2_BASE: - switch (channel) - { -#ifdef GPIO_TIM2_EXT_CLK_IN - case STM32_CAP_CHANNEL_COUNTER: - return GPIO_TIM2_EXT_CLK_IN; -#endif -#ifdef GPIO_TIM2_CH1IN - case 1: - return GPIO_TIM2_CH1IN; -#endif -#ifdef GPIO_TIM2_CH2IN - case 2: - return GPIO_TIM2_CH2IN; -#endif -#ifdef GPIO_TIM2_CH3IN - case 3: - return GPIO_TIM2_CH3IN; -#endif -#ifdef GPIO_TIM2_CH4IN - case 4: - return GPIO_TIM2_CH4IN; -#endif - } - break; -#endif -#ifdef CONFIG_STM32_TIM3_CAP - case STM32_TIM3_BASE: - switch (channel) - { -#ifdef GPIO_TIM3_EXT_CLK_IN - case STM32_CAP_CHANNEL_COUNTER: - return GPIO_TIM3_EXT_CLK_IN; -#endif -#ifdef GPIO_TIM3_CH1IN - case 1: - return GPIO_TIM3_CH1IN; -#endif -#ifdef GPIO_TIM3_CH2IN - case 2: - return GPIO_TIM3_CH2IN; -#endif -#ifdef GPIO_TIM3_CH3IN - case 3: - return GPIO_TIM3_CH3IN; -#endif -#ifdef GPIO_TIM3_CH4IN - case 4: - return GPIO_TIM3_CH4IN; -#endif - } - break; -#endif -#ifdef CONFIG_STM32_TIM4_CAP - case STM32_TIM4_BASE: - switch (channel) - { -#ifdef GPIO_TIM4_EXT_CLK_IN - case STM32_CAP_CHANNEL_COUNTER: - return GPIO_TIM4_EXT_CLK_IN; -#endif -#ifdef GPIO_TIM4_CH1IN - case 1: - return GPIO_TIM4_CH1IN; -#endif -#ifdef GPIO_TIM4_CH2IN - case 2: - return GPIO_TIM4_CH2IN; -#endif -#ifdef GPIO_TIM4_CH3IN - case 3: - return GPIO_TIM4_CH3IN; -#endif -#ifdef GPIO_TIM4_CH4IN - case 4: - return GPIO_TIM4_CH4IN; -#endif - } - break; -#endif -#ifdef CONFIG_STM32_TIM5_CAP - case STM32_TIM5_BASE: - switch (channel) - { -#ifdef GPIO_TIM5_EXT_CLK_IN - case STM32_CAP_CHANNEL_COUNTER: - return GPIO_TIM5_EXT_CLK_IN; -#endif -#ifdef GPIO_TIM5_CH1IN - case 1: - return GPIO_TIM5_CH1IN; -#endif -#ifdef GPIO_TIM5_CH2IN - case 2: - return GPIO_TIM5_CH2IN; -#endif -#ifdef GPIO_TIM5_CH3IN - case 3: - return GPIO_TIM5_CH3IN; -#endif -#ifdef GPIO_TIM5_CH4IN - case 4: - return GPIO_TIM5_CH4IN; -#endif - } - break; -#endif - - /* TIM6 and TIM7 cannot be used in capture */ - -#ifdef CONFIG_STM32_TIM8_CAP - case STM32_TIM8_BASE: - switch (channel) - { -#ifdef GPIO_TIM8_EXT_CLK_IN - case STM32_CAP_CHANNEL_COUNTER: - return GPIO_TIM8_EXT_CLK_IN; -#endif -#ifdef GPIO_TIM8_CH1IN - case 1: - return GPIO_TIM8_CH1IN; -#endif -#ifdef GPIO_TIM8_CH2IN - case 2: - return GPIO_TIM8_CH2IN; -#endif -#ifdef GPIO_TIM8_CH3IN - case 3: - return GPIO_TIM8_CH3IN; -#endif -#ifdef GPIO_TIM8_CH4IN - case 4: - return GPIO_TIM8_CH4IN; -#endif - } - break; -#endif - -#ifdef CONFIG_STM32_TIM9_CAP - case STM32_TIM9_BASE: - switch (channel) - { -#ifdef GPIO_TIM9_EXT_CLK_IN - case STM32_CAP_CHANNEL_COUNTER: - return GPIO_TIM9_EXT_CLK_IN; -#endif -#ifdef GPIO_TIM9_CH1IN - case 1: - return GPIO_TIM9_CH1IN; -#endif -#ifdef GPIO_TIM9_CH2IN - case 2: - return GPIO_TIM9_CH2IN; -#endif -#ifdef GPIO_TIM9_CH3IN - case 3: - return GPIO_TIM9_CH3IN; -#endif -#ifdef GPIO_TIM9_CH4IN - case 4: - return GPIO_TIM9_CH4IN; -#endif - } - break; -#endif - -#ifdef CONFIG_STM32_TIM10_CAP - case STM32_TIM10_BASE: - switch (channel) - { -#ifdef GPIO_TIM10_EXT_CLK_IN - case STM32_CAP_CHANNEL_COUNTER: - return GPIO_TIM10_EXT_CLK_IN; -#endif -#ifdef GPIO_TIM10_CH1IN - case 1: - return GPIO_TIM10_CH1IN; -#endif -#ifdef GPIO_TIM10_CH2IN - case 2: - return GPIO_TIM10_CH2IN; -#endif -#ifdef GPIO_TIM10_CH4IN - case 3: - return GPIO_TIM10_CH4IN; -#endif -#ifdef GPIO_TIM10_CH5IN - case 4: - return GPIO_TIM10_CH5IN; -#endif - } - break; -#endif - -#ifdef CONFIG_STM32_TIM11_CAP - case STM32_TIM11_BASE: - switch (channel) - { -#ifdef GPIO_TIM11_EXT_CLK_IN - case STM32_CAP_CHANNEL_COUNTER: - return GPIO_TIM11_EXT_CLK_IN; -#endif -#ifdef GPIO_TIM11_CH1IN - case 1: - return GPIO_TIM11_CH1IN; -#endif -#ifdef GPIO_TIM11_CH2IN - case 2: - return GPIO_TIM11_CH2IN; -#endif -#ifdef GPIO_TIM11_CH4IN - case 3: - return GPIO_TIM11_CH4IN; -#endif -#ifdef GPIO_TIM11_CH5IN - case 4: - return GPIO_TIM11_CH5IN; -#endif - } - break; -#endif - -#ifdef CONFIG_STM32_TIM12_CAP - case STM32_TIM12_BASE: - switch (channel) - { -#ifdef GPIO_TIM12_EXT_CLK_IN - case STM32_CAP_CHANNEL_COUNTER: - return GPIO_TIM12_EXT_CLK_IN; -#endif -#ifdef GPIO_TIM12_CH1IN - case 1: - return GPIO_TIM12_CH1IN; -#endif -#ifdef GPIO_TIM12_CH2IN - case 2: - return GPIO_TIM12_CH2IN; -#endif -#ifdef GPIO_TIM12_CH4IN - case 3: - return GPIO_TIM12_CH4IN; -#endif -#ifdef GPIO_TIM12_CH5IN - case 4: - return GPIO_TIM12_CH5IN; -#endif - } - break; -#endif - -#ifdef CONFIG_STM32_TIM13_CAP - case STM32_TIM13_BASE: - switch (channel) - { -#ifdef GPIO_TIM13_EXT_CLK_IN - case STM32_CAP_CHANNEL_COUNTER: - return GPIO_TIM13_EXT_CLK_IN; -#endif -#ifdef GPIO_TIM13_CH1IN - case 1: - return GPIO_TIM13_CH1IN; -#endif -#ifdef GPIO_TIM13_CH2IN - case 2: - return GPIO_TIM13_CH2IN; -#endif -#ifdef GPIO_TIM13_CH4IN - case 3: - return GPIO_TIM13_CH4IN; -#endif -#ifdef GPIO_TIM13_CH5IN - case 4: - return GPIO_TIM13_CH5IN; -#endif - } - break; -#endif - -#ifdef CONFIG_STM32_TIM14_CAP - case STM32_TIM14_BASE: - switch (channel) - { -#ifdef GPIO_TIM14_EXT_CLK_IN - case STM32_CAP_CHANNEL_COUNTER: - return GPIO_TIM14_EXT_CLK_IN; -#endif -#ifdef GPIO_TIM14_CH1IN - case 1: - return GPIO_TIM14_CH1IN; -#endif -#ifdef GPIO_TIM14_CH2IN - case 2: - return GPIO_TIM14_CH2IN; -#endif -#ifdef GPIO_TIM14_CH4IN - case 3: - return GPIO_TIM14_CH4IN; -#endif -#ifdef GPIO_TIM14_CH5IN - case 4: - return GPIO_TIM14_CH5IN; -#endif - } - break; -#endif - } - - return 0; -} - -static inline int stm32_cap_set_rcc(const struct stm32_cap_priv_s *priv, - bool on) -{ - uint32_t offset = 0; - uint32_t mask = 0; - - switch (priv->base) - { -#ifdef CONFIG_STM32_TIM1_CAP - case STM32_TIM1_BASE: - offset = STM32_RCC_APB2ENR; - mask = RCC_APB2ENR_TIM1EN; - break; -#endif -#ifdef CONFIG_STM32_TIM2_CAP - case STM32_TIM2_BASE: - offset = STM32_RCC_APB1ENR; - mask = RCC_APB1ENR_TIM2EN; - break; -#endif -#ifdef CONFIG_STM32_TIM3_CAP - case STM32_TIM3_BASE: - offset = STM32_RCC_APB1ENR; - mask = RCC_APB1ENR_TIM3EN; - break; -#endif -#ifdef CONFIG_STM32_TIM4_CAP - case STM32_TIM4_BASE: - offset = STM32_RCC_APB1ENR; - mask = RCC_APB1ENR_TIM4EN; - break; -#endif -#ifdef CONFIG_STM32_TIM5_CAP - case STM32_TIM5_BASE: - offset = STM32_RCC_APB1ENR; - mask = RCC_APB1ENR_TIM5EN; - break; -#endif - - /* TIM6 and TIM7 cannot be used in capture */ - -#ifdef CONFIG_STM32_TIM8_CAP - case STM32_TIM8_BASE: - offset = STM32_RCC_APB2ENR; - mask = RCC_APB2ENR_TIM8EN; - break; -#endif -#ifdef CONFIG_STM32_TIM9_CAP - case STM32_TIM9_BASE: - offset = STM32_RCC_APB2ENR; - mask = RCC_APB2ENR_TIM9EN; - break; -#endif -#ifdef CONFIG_STM32_TIM10_CAP - case STM32_TIM10_BASE: - offset = STM32_RCC_APB2ENR; - mask = RCC_APB2ENR_TIM10EN; - break; -#endif -#ifdef CONFIG_STM32_TIM11_CAP - case STM32_TIM11_BASE: - offset = STM32_RCC_APB2ENR; - mask = RCC_APB2ENR_TIM11EN; - break; -#endif -#ifdef CONFIG_STM32_TIM12_CAP - case STM32_TIM12_BASE: - offset = STM32_RCC_APB1ENR; - mask = RCC_APB1ENR_TIM12EN; - break; -#endif -#ifdef CONFIG_STM32_TIM13_CAP - case STM32_TIM13_BASE: - offset = STM32_RCC_APB1ENR; - mask = RCC_APB1ENR_TIM13EN; - break; -#endif -#ifdef CONFIG_STM32_TIM14_CAP - case STM32_TIM14_BASE: - offset = STM32_RCC_APB1ENR; - mask = RCC_APB1ENR_TIM14EN; - break; -#endif - } - - if (mask == 0) - { - return ERROR; - } - - if (on) - { - modifyreg32(offset, 0, mask); - } - else - { - modifyreg32(offset, mask, 0); - } - - return OK; -} - -/**************************************************************************** - * Basic Functions - ****************************************************************************/ - -static int stm32_cap_setclock(struct stm32_cap_dev_s *dev, - uint32_t freq, uint32_t max) -{ - const struct stm32_cap_priv_s *priv = (const struct stm32_cap_priv_s *)dev; - uint32_t freqin; - int prescaler; - - /* Disable Timer? */ - - if (freq == 0) - { - /* Disable Timer */ - - stm32_modifyreg16(priv, STM32_BTIM_CR1_OFFSET, ATIM_CR1_CEN, 0); - return 0; - } - - /* Get the input clock frequency for this timer. These vary with - * different timer clock sources, MCU-specific timer configuration, and - * board-specific clock configuration. The correct input clock frequency - * must be defined in the board.h header file. - */ - - switch (priv->base) - { -#ifdef CONFIG_STM32_TIM1 - case STM32_TIM1_BASE: - freqin = STM32_APB2_TIM1_CLKIN; - break; -#endif -#ifdef CONFIG_STM32_TIM2 - case STM32_TIM2_BASE: - freqin = STM32_APB1_TIM2_CLKIN; - break; -#endif -#ifdef CONFIG_STM32_TIM3 - case STM32_TIM3_BASE: - freqin = STM32_APB1_TIM3_CLKIN; - break; -#endif -#ifdef CONFIG_STM32_TIM4 - case STM32_TIM4_BASE: - freqin = STM32_APB1_TIM4_CLKIN; - break; -#endif -#ifdef CONFIG_STM32_TIM5 - case STM32_TIM5_BASE: - freqin = STM32_APB1_TIM5_CLKIN; - break; -#endif -#ifdef CONFIG_STM32_TIM8 - case STM32_TIM8_BASE: - freqin = STM32_APB2_TIM8_CLKIN; - break; -#endif -#ifdef CONFIG_STM32_TIM9 - case STM32_TIM9_BASE: - freqin = STM32_APB2_TIM9_CLKIN; - break; -#endif -#ifdef CONFIG_STM32_TIM10 - case STM32_TIM10_BASE: - freqin = STM32_APB2_TIM10_CLKIN; - break; -#endif -#ifdef CONFIG_STM32_TIM11 - case STM32_TIM11_BASE: - freqin = STM32_APB2_TIM11_CLKIN; - break; -#endif -#ifdef CONFIG_STM32_TIM12 - case STM32_TIM12_BASE: - freqin = STM32_APB1_TIM12_CLKIN; - break; -#endif -#ifdef CONFIG_STM32_TIM13 - case STM32_TIM13_BASE: - freqin = STM32_APB1_TIM13_CLKIN; - break; -#endif -#ifdef CONFIG_STM32_TIM14 - case STM32_TIM14_BASE: - freqin = STM32_APB1_TIM14_CLKIN; - break; -#endif - - default: - return -EINVAL; - } - - /* Select a pre-scaler value for this timer using the input clock - * frequency. - */ - - prescaler = freqin / freq; - - /* We need to decrement value for '1', but only, if we are allowed to - * not to cause underflow. Check for overflow. - */ - - if (prescaler > 0) - { - prescaler--; - } - - if (prescaler > 0xffff) - { - prescaler = 0xffff; - } - - /* Set Maximum */ - - stm32_putreg32(priv, STM32_BTIM_ARR_OFFSET, max); - - /* Set prescaler */ - - stm32_putreg16(priv, STM32_BTIM_PSC_OFFSET, prescaler); - - /* Reset counter timer */ - - stm32_modifyreg16(priv, STM32_BTIM_EGR_OFFSET, 0, BTIM_EGR_UG); - - /* Enable timer */ - - stm32_modifyreg16(priv, STM32_BTIM_CR1_OFFSET, 0, BTIM_CR1_CEN); - -#ifdef USE_ADVENCED_TIM - /* Advanced registers require Main Output Enable */ - - if (priv->base == STM32_TIM1_BASE || priv->base == STM32_TIM8_BASE) - { - stm32_modifyreg16(priv, STM32_ATIM_BDTR_OFFSET, 0, ATIM_BDTR_MOE); - } -#endif - - return prescaler; -} - -/**************************************************************************** - * Name: stm32_cap_setsmc - * - * Description: - * set slave mode control register - * - * Input Parameters: - * dev - A pointer of the stm32 capture device structure. - * cfg - Slave mode control register configure of timer. - * - * Returned Value: - * Zero on success; a negated errno value on failure. - * - ****************************************************************************/ - -static int stm32_cap_setsmc(struct stm32_cap_dev_s *dev, - stm32_cap_smc_cfg_t cfg) -{ - const struct stm32_cap_priv_s *priv = (const struct stm32_cap_priv_s *)dev; - uint16_t regval = 0; - uint16_t mask = 0; - - switch (cfg & STM32_CAP_SMS_MASK) - { - case STM32_CAP_SMS_INT: - regval |= GTIM_SMCR_DISAB; - break; - - case STM32_CAP_SMS_ENC1: - regval |= GTIM_SMCR_ENCMD1; - break; - - case STM32_CAP_SMS_ENC2: - regval |= GTIM_SMCR_ENCMD2; - break; - - case STM32_CAP_SMS_ENC3: - regval |= GTIM_SMCR_ENCMD3; - break; - - case STM32_CAP_SMS_RST: - regval |= GTIM_SMCR_RESET; - break; - - case STM32_CAP_SMS_GAT: - regval |= GTIM_SMCR_GATED; - break; - - case STM32_CAP_SMS_TRG: - regval |= GTIM_SMCR_TRIGGER; - break; - - case STM32_CAP_SMS_EXT: - regval |= GTIM_SMCR_EXTCLK1; - break; - - default: - break; - } - - switch (cfg & STM32_CAP_TS_MASK) - { - case STM32_CAP_TS_ITR0: - regval |= GTIM_SMCR_ITR0; - break; - - case STM32_CAP_TS_ITR1: - regval |= GTIM_SMCR_ITR1; - break; - - case STM32_CAP_TS_ITR2: - regval |= GTIM_SMCR_ITR2; - break; - - case STM32_CAP_TS_ITR3: - regval |= GTIM_SMCR_ITR3; - break; - - case STM32_CAP_TS_TI1FED: - regval |= GTIM_SMCR_TI1FED; - break; - - case STM32_CAP_TS_TI1FP1: - regval |= GTIM_SMCR_TI1FP1; - break; - - case STM32_CAP_TS_TI2FP2: - regval |= GTIM_SMCR_TI2FP2; - break; - - case STM32_CAP_TS_ETRF: - regval |= GTIM_SMCR_ETRF; - break; - - default: - break; - } - - if (cfg & STM32_CAP_MSM_MASK) - { - regval |= STM32_CAP_MSM_MASK; - } - - mask = (STM32_CAP_SMS_MASK | STM32_CAP_TS_MASK | STM32_CAP_MSM_MASK); - stm32_modifyreg16(priv, STM32_GTIM_SMCR_OFFSET, mask, regval); - - return OK; -} - -static int stm32_cap_setisr(struct stm32_cap_dev_s *dev, xcpt_t handler, - void *arg) -{ - const struct stm32_cap_priv_s *priv = (const struct stm32_cap_priv_s *)dev; - int irq; -#ifdef USE_ADVENCED_TIM - int irq_of; -#endif - - DEBUGASSERT(dev != NULL); - - irq = priv->irq; -#ifdef USE_ADVENCED_TIM - irq_of = priv->irq_of; -#endif - - /* Disable interrupt when callback is removed */ - - if (!handler) - { - up_disable_irq(irq); - irq_detach(irq); - -#ifdef USE_ADVENCED_TIM - if (priv->irq_of) - { - up_disable_irq(irq_of); - irq_detach(irq_of); - } -#endif - - return OK; - } - - /* Otherwise set callback and enable interrupt */ - - irq_attach(irq, handler, arg); - up_enable_irq(irq); - -#ifdef USE_ADVENCED_TIM - if (priv->irq_of) - { - irq_attach(priv->irq_of, handler, arg); - up_enable_irq(priv->irq_of); - } -#endif - - return OK; -} - -static void stm32_cap_enableint(struct stm32_cap_dev_s *dev, - stm32_cap_flags_t src, bool on) -{ - const struct stm32_cap_priv_s *priv = (const struct stm32_cap_priv_s *)dev; - uint16_t mask = 0; - - DEBUGASSERT(dev != NULL); - - if (src & STM32_CAP_FLAG_IRQ_COUNTER) - { - mask |= ATIM_DIER_UIE; - } - - if (src & STM32_CAP_FLAG_IRQ_CH_1) - { - mask |= ATIM_DIER_CC1IE; - } - - if (src & STM32_CAP_FLAG_IRQ_CH_2) - { - mask |= ATIM_DIER_CC2IE; - } - - if (src & STM32_CAP_FLAG_IRQ_CH_3) - { - mask |= ATIM_DIER_CC3IE; - } - - if (src & STM32_CAP_FLAG_IRQ_CH_4) - { - mask |= ATIM_DIER_CC4IE; - } - - /* Not IRQ on channel overflow */ - - if (on) - { - stm32_modifyreg16(priv, STM32_BTIM_DIER_OFFSET, 0, mask); - } - else - { - stm32_modifyreg16(priv, STM32_BTIM_DIER_OFFSET, mask, 0); - } -} - -static void stm32_cap_ackflags(struct stm32_cap_dev_s *dev, int flags) -{ - const struct stm32_cap_priv_s *priv = (const struct stm32_cap_priv_s *)dev; - uint16_t mask = 0; - - if (flags & STM32_CAP_FLAG_IRQ_COUNTER) - { - mask |= ATIM_SR_UIF; - } - - if (flags & STM32_CAP_FLAG_IRQ_CH_1) - { - mask |= ATIM_SR_CC1IF; - } - - if (flags & STM32_CAP_FLAG_IRQ_CH_2) - { - mask |= ATIM_SR_CC2IF; - } - - if (flags & STM32_CAP_FLAG_IRQ_CH_3) - { - mask |= ATIM_SR_CC3IF; - } - - if (flags & STM32_CAP_FLAG_IRQ_CH_4) - { - mask |= ATIM_SR_CC4IF; - } - - if (flags & STM32_CAP_FLAG_OF_CH_1) - { - mask |= ATIM_SR_CC1OF; - } - - if (flags & STM32_CAP_FLAG_OF_CH_2) - { - mask |= ATIM_SR_CC2OF; - } - - if (flags & STM32_CAP_FLAG_OF_CH_3) - { - mask |= ATIM_SR_CC3OF; - } - - if (flags & STM32_CAP_FLAG_OF_CH_4) - { - mask |= ATIM_SR_CC4OF; - } - - stm32_putreg16(priv, STM32_BTIM_SR_OFFSET, ~mask); -} - -static stm32_cap_flags_t stm32_cap_getflags(struct stm32_cap_dev_s *dev) -{ - const struct stm32_cap_priv_s *priv = (const struct stm32_cap_priv_s *)dev; - uint16_t regval = 0; - stm32_cap_flags_t flags = 0; - - regval = stm32_getreg16(priv, STM32_BTIM_SR_OFFSET); - - if (regval & ATIM_SR_UIF) - { - flags |= STM32_CAP_FLAG_IRQ_COUNTER; - } - - if (regval & ATIM_SR_CC1IF) - { - flags |= STM32_CAP_FLAG_IRQ_CH_1; - } - - if (regval & ATIM_SR_CC2IF) - { - flags |= STM32_CAP_FLAG_IRQ_CH_2; - } - - if (regval & ATIM_SR_CC3IF) - { - flags |= STM32_CAP_FLAG_IRQ_CH_3; - } - - if (regval & ATIM_SR_CC4IF) - { - flags |= STM32_CAP_FLAG_IRQ_CH_4; - } - - if (regval & ATIM_SR_CC1OF) - { - flags |= STM32_CAP_FLAG_OF_CH_1; - } - - if (regval & ATIM_SR_CC2OF) - { - flags |= STM32_CAP_FLAG_OF_CH_2; - } - - if (regval & ATIM_SR_CC3OF) - { - flags |= STM32_CAP_FLAG_OF_CH_3; - } - - if (regval & ATIM_SR_CC4OF) - { - flags |= STM32_CAP_FLAG_OF_CH_4; - } - - return flags; -} - -/**************************************************************************** - * General Functions - ****************************************************************************/ - -static int stm32_cap_setchannel(struct stm32_cap_dev_s *dev, - uint8_t channel, - stm32_cap_ch_cfg_t cfg) -{ - const struct stm32_cap_priv_s *priv = (const struct stm32_cap_priv_s *)dev; - uint32_t gpio = 0; - uint16_t mask; - uint16_t regval; - uint16_t ccer_en_bit; - - DEBUGASSERT(dev != NULL); - - gpio = stm32_cap_gpio(priv, channel); - - if (gpio == 0) - { - return ERROR; - } - - if ((cfg & STM32_CAP_MAPPED_MASK) == 0) - { - return ERROR; /* MAPPED not selected */ - } - - /* Change to zero base index */ - - channel--; - - /* Set ccer : - * - * GTIM_CCER_CCxE Is written latter to allow writing CCxS bits. - * - */ - - switch (cfg & STM32_CAP_EDGE_MASK) - { - case STM32_CAP_EDGE_DISABLED: - ccer_en_bit = 0; - regval = 0; - break; - - case STM32_CAP_EDGE_RISING: - ccer_en_bit = GTIM_CCER_CC1E; - regval = 0; - break; - - case STM32_CAP_EDGE_FALLING: - ccer_en_bit = GTIM_CCER_CC1E; - regval = GTIM_CCER_CC1P; - break; - - case STM32_CAP_EDGE_BOTH: - ccer_en_bit = GTIM_CCER_CC1E; -#ifdef HAVE_GTIM_CCXNP - regval = GTIM_CCER_CC1P | GTIM_CCER_CC1NP; -#else - regval = GTIM_CCER_CC1P; -#endif - break; - - default: - return ERROR; - } - - /* Shift all CCER bits to corresponding channel */ -#ifdef HAVE_GTIM_CCXNP - mask = (GTIM_CCER_CC1E | GTIM_CCER_CC1P | GTIM_CCER_CC1NP); -#else - mask = (GTIM_CCER_CC1E | GTIM_CCER_CC1P); -#endif - mask <<= GTIM_CCER_CCXBASE(channel); - regval <<= GTIM_CCER_CCXBASE(channel); - ccer_en_bit <<= GTIM_CCER_CCXBASE(channel); - - stm32_modifyreg16(priv, STM32_GTIM_CCER_OFFSET, mask, regval); - - /* Set ccmr */ - - regval = cfg; - mask = (GTIM_CCMR1_IC1F_MASK | - GTIM_CCMR1_IC1PSC_MASK | - GTIM_CCMR1_CC1S_MASK); - regval &= mask; - - if (channel & 1) - { - regval <<= 8; - mask <<= 8; - } - - if (channel < 2) - { - stm32_modifyreg16(priv, STM32_GTIM_CCMR1_OFFSET, mask, regval); - } - else - { - stm32_modifyreg16(priv, STM32_GTIM_CCMR2_OFFSET, mask, regval); - } - - /* Set GPIO */ - - if ((cfg & STM32_CAP_EDGE_MASK) == STM32_CAP_EDGE_DISABLED) - { - stm32_unconfiggpio(gpio); - } - else - { - stm32_configgpio(gpio); - } - - /* Enable this channel timer */ - - stm32_modifyreg16(priv, STM32_GTIM_CCER_OFFSET, 0, ccer_en_bit); - return OK; -} - -static uint32_t stm32_cap_getcapture(struct stm32_cap_dev_s *dev, - uint8_t channel) -{ - const struct stm32_cap_priv_s *priv = (const struct stm32_cap_priv_s *)dev; - uint32_t offset; - - DEBUGASSERT(dev != NULL); - - switch (channel) - { - case STM32_CAP_CHANNEL_COUNTER: - offset = STM32_GTIM_CNT_OFFSET; - break; -#ifdef HAVE_CH1IN - case 1: - offset = STM32_GTIM_CCR1_OFFSET; - break; -#endif -#ifdef HAVE_CH2IN - case 2: - offset = STM32_GTIM_CCR2_OFFSET; - break; -#endif -#ifdef HAVE_CH3IN - case 3: - offset = STM32_GTIM_CCR3_OFFSET; - break; -#endif -#ifdef HAVE_CH4IN - case 4: - offset = STM32_GTIM_CCR4_OFFSET; - break; -#endif - default: - return ERROR; - } - - if (priv->base == STM32_TIM2_BASE || priv->base == STM32_TIM5_BASE) - { - return stm32_getreg32(priv, offset); - } - - return stm32_getreg16(priv, offset); -} - -static uint32_t stm32_cap_rstcounter(struct stm32_cap_dev_s *dev) -{ - const struct stm32_cap_priv_s *priv = (const struct stm32_cap_priv_s *)dev; - - stm32_modifyreg16(priv, STM32_BTIM_EGR_OFFSET, 0, BTIM_EGR_UG); - return OK; -} - -/**************************************************************************** - * Advanced Functions - ****************************************************************************/ - -/* TODO: Advanced functions for the STM32_ATIM */ - -/**************************************************************************** - * Device Structures, Instantiation - ****************************************************************************/ - -struct stm32_cap_ops_s stm32_cap_ops = -{ - .setsmc = &stm32_cap_setsmc, - .setclock = &stm32_cap_setclock, - .setchannel = &stm32_cap_setchannel, - .getcapture = &stm32_cap_getcapture, - .setisr = &stm32_cap_setisr, - .enableint = &stm32_cap_enableint, - .ackflags = &stm32_cap_ackflags, - .getflags = &stm32_cap_getflags, - .rstcounter = &stm32_cap_rstcounter, -}; - -#ifdef CONFIG_STM32_TIM1_CAP -const struct stm32_cap_priv_s stm32_tim1_priv = -{ - .ops = &stm32_cap_ops, - .base = STM32_TIM1_BASE, - .irq = STM32_IRQ_TIM1CC, -#ifdef USE_ADVENCED_TIM - .irq_of = STM32_IRQ_TIM1UP, -#endif -}; -#endif - -#ifdef CONFIG_STM32_TIM2_CAP -const struct stm32_cap_priv_s stm32_tim2_priv = -{ - .ops = &stm32_cap_ops, - .base = STM32_TIM2_BASE, - .irq = STM32_IRQ_TIM2, -#ifdef USE_ADVENCED_TIM - .irq_of = 0, -#endif -}; -#endif - -#ifdef CONFIG_STM32_TIM3_CAP -const struct stm32_cap_priv_s stm32_tim3_priv = -{ - .ops = &stm32_cap_ops, - .base = STM32_TIM3_BASE, - .irq = STM32_IRQ_TIM3, -#ifdef USE_ADVENCED_TIM - .irq_of = 0, -#endif -}; -#endif - -#ifdef CONFIG_STM32_TIM4_CAP -const struct stm32_cap_priv_s stm32_tim4_priv = -{ - .ops = &stm32_cap_ops, - .base = STM32_TIM4_BASE, - .irq = STM32_IRQ_TIM4, -#ifdef USE_ADVENCED_TIM - .irq_of = 0, -#endif -}; -#endif - -#ifdef CONFIG_STM32_TIM5_CAP -const struct stm32_cap_priv_s stm32_tim5_priv = -{ - .ops = &stm32_cap_ops, - .base = STM32_TIM5_BASE, - .irq = STM32_IRQ_TIM5, -#ifdef USE_ADVENCED_TIM - .irq_of = 0, -#endif -}; -#endif - -/* TIM6 and TIM7 cannot be used in capture */ - -#ifdef CONFIG_STM32_TIM8_CAP -const struct stm32_cap_priv_s stm32_tim8_priv = -{ - .ops = &stm32_cap_ops, - .base = STM32_TIM8_BASE, - .irq = STM32_IRQ_TIM8CC, -#ifdef USE_ADVENCED_TIM - .irq_of = STM32_IRQ_TIM8UP, -#endif -}; -#endif - -#ifdef CONFIG_STM32_TIM9_CAP -const struct stm32_cap_priv_s stm32_tim9_priv = -{ - .ops = &stm32_cap_ops, - .base = STM32_TIM9_BASE, - .irq = STM32_IRQ_TIM9, -#ifdef USE_ADVENCED_TIM - .irq_of = 0, -#endif -}; -#endif - -#ifdef CONFIG_STM32_TIM10_CAP -const struct stm32_cap_priv_s stm32_tim10_priv = -{ - .ops = &stm32_cap_ops, - .base = STM32_TIM10_BASE, - .irq = STM32_IRQ_TIM10, -#ifdef USE_ADVENCED_TIM - .irq_of = 0, -#endif -}; -#endif - -#ifdef CONFIG_STM32_TIM11_CAP -const struct stm32_cap_priv_s stm32_tim11_priv = -{ - .ops = &stm32_cap_ops, - .base = STM32_TIM11_BASE, - .irq = STM32_IRQ_TIM11, -#ifdef USE_ADVENCED_TIM - .irq_of = 0, -#endif -}; -#endif - -#ifdef CONFIG_STM32_TIM12_CAP -const struct stm32_cap_priv_s stm32_tim12_priv = -{ - .ops = &stm32_cap_ops, - .base = STM32_TIM12_BASE, - .irq = STM32_IRQ_TIM12, -#ifdef USE_ADVENCED_TIM - .irq_of = 0, -#endif -}; -#endif - -#ifdef CONFIG_STM32_TIM13_CAP -const struct stm32_cap_priv_s stm32_tim13_priv = -{ - .ops = &stm32_cap_ops, - .base = STM32_TIM13_BASE, - .irq = STM32_IRQ_TIM13, -#ifdef USE_ADVENCED_TIM - .irq_of = 0, -#endif -}; -#endif - -#ifdef CONFIG_STM32_TIM14_CAP -const struct stm32_cap_priv_s stm32_tim14_priv = -{ - .ops = &stm32_cap_ops, - .base = STM32_TIM14_BASE, - .irq = STM32_IRQ_TIM14, -#ifdef USE_ADVENCED_TIM - .irq_of = 0, -#endif -}; -#endif - -static inline const struct stm32_cap_priv_s * stm32_cap_get_priv(int timer) -{ - switch (timer) - { -#ifdef CONFIG_STM32_TIM1_CAP - case 1: - return &stm32_tim1_priv; -#endif -#ifdef CONFIG_STM32_TIM2_CAP - case 2: - return &stm32_tim2_priv; -#endif -#ifdef CONFIG_STM32_TIM3_CAP - case 3: - return &stm32_tim3_priv; -#endif -#ifdef CONFIG_STM32_TIM4_CAP - case 4: - return &stm32_tim4_priv; -#endif -#ifdef CONFIG_STM32_TIM5_CAP - case 5: - return &stm32_tim5_priv; -#endif - - /* TIM6 and TIM7 cannot be used in capture */ - -#ifdef CONFIG_STM32_TIM8_CAP - case 8: - return &stm32_tim8_priv; -#endif -#ifdef CONFIG_STM32_TIM9_CAP - case 9: - return &stm32_tim9_priv; -#endif -#ifdef CONFIG_STM32_TIM10_CAP - case 10: - return &stm32_tim10_priv; -#endif -#ifdef CONFIG_STM32_TIM11_CAP - case 11: - return &stm32_tim11_priv; -#endif -#ifdef CONFIG_STM32_TIM12_CAP - case 12: - return &stm32_tim12_priv; -#endif -#ifdef CONFIG_STM32_TIM13_CAP - case 13: - return &stm32_tim13_priv; -#endif -#ifdef CONFIG_STM32_TIM14_CAP - case 14: - return &stm32_tim14_priv; -#endif - } - - return NULL; -} - -/**************************************************************************** - * Public Function - Initialization - ****************************************************************************/ - -struct stm32_cap_dev_s *stm32_cap_init(int timer) -{ - const struct stm32_cap_priv_s *priv = stm32_cap_get_priv(timer); - uint32_t gpio; - - if (priv) - { - stm32_cap_set_rcc(priv, true); - - gpio = stm32_cap_gpio(priv, STM32_CAP_CHANNEL_COUNTER); - if (gpio) - { - stm32_configgpio(gpio); - } - - /* Disable timer while is not configured */ - - stm32_modifyreg16(priv, STM32_BTIM_CR1_OFFSET, ATIM_CR1_CEN, 0); - } - - return (struct stm32_cap_dev_s *)priv; -} - -int stm32_cap_deinit(struct stm32_cap_dev_s * dev) -{ - const struct stm32_cap_priv_s *priv = (struct stm32_cap_priv_s *)dev; - uint32_t gpio; - - DEBUGASSERT(dev != NULL); - - /* Disable timer while is not configured */ - - stm32_modifyreg16(priv, STM32_BTIM_CR1_OFFSET, ATIM_CR1_CEN, 0); - - gpio = stm32_cap_gpio(priv, STM32_CAP_CHANNEL_COUNTER); - if (gpio) - { - stm32_unconfiggpio(gpio); - } - - stm32_cap_set_rcc(priv, false); - return OK; -} - -#endif /* defined(CONFIG_STM32_TIM1 || ... || TIM14) */ diff --git a/arch/arm/src/stm32/stm32_capture_lowerhalf.c b/arch/arm/src/stm32/stm32_capture_lowerhalf.c deleted file mode 100644 index 0246f5e28f983..0000000000000 --- a/arch/arm/src/stm32/stm32_capture_lowerhalf.c +++ /dev/null @@ -1,577 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_capture_lowerhalf.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include -#include -#include - -#include -#include - -#include - -#include "stm32_capture.h" - -#if defined(CONFIG_STM32_CAP) - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#define STM32_TIM1_RES 16 -#if defined(CONFIG_STM32_STM32L15XX) || defined(CONFIG_STM32_STM32F10XX) -# define STM32_TIM2_RES 16 -#else -# define STM32_TIM2_RES 32 -#endif -#define STM32_TIM3_RES 16 -#define STM32_TIM4_RES 16 -#if defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F30XX) -# define STM32_TIM5_RES 16 -#else -# define STM32_TIM5_RES 32 -#endif -#define STM32_TIM8_RES 16 -#define STM32_TIM9_RES 16 -#define STM32_TIM10_RES 16 -#define STM32_TIM11_RES 16 -#define STM32_TIM12_RES 16 -#define STM32_TIM13_RES 16 -#define STM32_TIM14_RES 16 - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/* This structure provides the private representation of the "lower-half" - * driver state structure. This structure must be cast-compatible with the - * cap_lowerhalf_s structure. - */ - -struct stm32_lowerhalf_s -{ - const struct cap_ops_s *ops; /* Lower half operations */ - struct stm32_cap_dev_s *cap; /* stm32 capture driver */ - bool started; /* True: Timer has been started */ - const uint8_t resolution; /* Number of bits in the timer */ - uint8_t channel; /* pwm input channel */ - uint32_t clock; /* Timer clock frequency */ - uint8_t duty; /* Result pwm frequency */ - uint32_t freq; /* Result pwm frequency */ -}; - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -static int stm32_cap_handler(int irq, void * context, void * arg); - -/* "Lower half" driver methods **********************************************/ - -static int stm32_start(struct cap_lowerhalf_s *lower); -static int stm32_stop(struct cap_lowerhalf_s *lower); -static int stm32_getduty(struct cap_lowerhalf_s *lower, uint8_t *duty); -static int stm32_getfreq(struct cap_lowerhalf_s *lower, uint32_t *freq); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* "Lower half" driver methods */ - -static const struct cap_ops_s g_cap_ops = -{ - .start = stm32_start, - .stop = stm32_stop, - .getduty = stm32_getduty, - .getfreq = stm32_getfreq, -}; - -#ifdef CONFIG_STM32_TIM1_CAP -static struct stm32_lowerhalf_s g_cap1_lowerhalf = -{ - .ops = &g_cap_ops, - .resolution = STM32_TIM1_RES, - .channel = CONFIG_STM32_TIM1_CHANNEL, - .clock = CONFIG_STM32_TIM1_CLOCK, -}; -#endif - -#ifdef CONFIG_STM32_TIM2_CAP -static struct stm32_lowerhalf_s g_cap2_lowerhalf = -{ - .ops = &g_cap_ops, - .resolution = STM32_TIM2_RES, - .channel = CONFIG_STM32_TIM2_CHANNEL, - .clock = CONFIG_STM32_TIM2_CLOCK, -}; -#endif - -#ifdef CONFIG_STM32_TIM3_CAP -static struct stm32_lowerhalf_s g_cap3_lowerhalf = -{ - .ops = &g_cap_ops, - .resolution = STM32_TIM3_RES, - .channel = CONFIG_STM32_TIM3_CHANNEL, - .clock = CONFIG_STM32_TIM3_CLOCK, -}; -#endif - -#ifdef CONFIG_STM32_TIM4_CAP -static struct stm32_lowerhalf_s g_cap4_lowerhalf = -{ - .ops = &g_cap_ops, - .resolution = STM32_TIM4_RES, - .channel = CONFIG_STM32_TIM4_CHANNEL, - .clock = CONFIG_STM32_TIM4_CLOCK, -}; -#endif - -#ifdef CONFIG_STM32_TIM5_CAP -static struct stm32_lowerhalf_s g_cap5_lowerhalf = -{ - .ops = &g_cap_ops, - .resolution = STM32_TIM5_RES, - .channel = CONFIG_STM32_TIM5_CHANNEL, - .clock = CONFIG_STM32_TIM5_CLOCK, -}; -#endif - -#ifdef CONFIG_STM32_TIM8_CAP -static struct stm32_lowerhalf_s g_cap8_lowerhalf = -{ - .ops = &g_cap_ops, - .resolution = STM32_TIM8_RES, - .channel = CONFIG_STM32_TIM8_CHANNEL, - .clock = CONFIG_STM32_TIM8_CLOCK, -}; -#endif - -#ifdef CONFIG_STM32_TIM9_CAP -static struct stm32_lowerhalf_s g_cap9_lowerhalf = -{ - .ops = &g_cap_ops, - .resolution = STM32_TIM9_RES, - .channel = CONFIG_STM32_TIM9_CHANNEL, - .clock = CONFIG_STM32_TIM9_CLOCK, -}; -#endif - -#ifdef CONFIG_STM32_TIM10_CAP -static struct stm32_lowerhalf_s g_cap10_lowerhalf = -{ - .ops = &g_cap_ops, - .resolution = STM32_TIM10_RES, - .channel = CONFIG_STM32_TIM10_CHANNEL, - .clock = CONFIG_STM32_TIM10_CLOCK, -}; -#endif - -#ifdef CONFIG_STM32_TIM11_CAP -static struct stm32_lowerhalf_s g_cap11_lowerhalf = -{ - .ops = &g_cap_ops, - .resolution = STM32_TIM11_RES, - .channel = CONFIG_STM32_TIM11_CHANNEL, - .clock = CONFIG_STM32_TIM11_CLOCK, -}; -#endif - -#ifdef CONFIG_STM32_TIM12_CAP -static struct stm32_lowerhalf_s g_cap12_lowerhalf = -{ - .ops = &g_cap_ops, - .resolution = STM32_TIM12_RES, - .channel = CONFIG_STM32_TIM12_CHANNEL, - .clock = CONFIG_STM32_TIM12_CLOCK, -}; -#endif - -#ifdef CONFIG_STM32_TIM13_CAP -static struct stm32_lowerhalf_s g_cap13_lowerhalf = -{ - .ops = &g_cap_ops, - .resolution = STM32_TIM13_RES, - .channel = CONFIG_STM32_TIM13_CHANNEL, - .clock = CONFIG_STM32_TIM13_CLOCK, -}; -#endif - -#ifdef CONFIG_STM32_TIM14_CAP -static struct stm32_lowerhalf_s g_cap14_lowerhalf = -{ - .ops = &g_cap_ops, - .resolution = STM32_TIM14_RES, - .channel = CONFIG_STM32_TIM14_CHANNEL, - .clock = CONFIG_STM32_TIM14_CLOCK, -}; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_cap_handler - * - * Description: - * timer interrupt handler - * - * Input Parameters: - * - * Returned Value: - * - ****************************************************************************/ - -static int stm32_cap_handler(int irq, void * context, void * arg) -{ - struct stm32_lowerhalf_s *lower = (struct stm32_lowerhalf_s *) arg; - uint8_t ch = 0x3 & lower->channel; - int period = 0; - int flags = 0; - - flags = (int)STM32_CAP_GETFLAGS(lower->cap) ; - - STM32_CAP_ACKFLAGS(lower->cap, flags); - - period = STM32_CAP_GETCAPTURE(lower->cap, ch); - - if (period != 0) - { - lower->duty = (100 * STM32_CAP_GETCAPTURE(lower->cap, 0x3 & (~ch))) / - period; - } - else - { - lower->duty = 0; - } - - lower->freq = lower->clock / period; - - return OK; -} - -/**************************************************************************** - * Name: stm32_start - * - * Description: - * Start the timer, resetting the time to the current timeout, - * - * Input Parameters: - * lower - A pointer the publicly visible representation of the - * "lower-half" driver state structure. - * - * Returned Value: - * Zero on success; a negated errno value on failure. - * - ****************************************************************************/ - -static int stm32_start(struct cap_lowerhalf_s *lower) -{ - struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; - int flags = 0; - uint32_t maxtimeout = (1 << priv->resolution) - 1; - - if (priv->started) - { - /* Return EBUSY to indicate that the timer was already running */ - - return -EBUSY; - } - - switch (priv->channel) - { - case 1: - STM32_CAP_SETSMC(priv->cap, STM32_CAP_SMS_RST | - STM32_CAP_TS_TI1FP1 | - STM32_CAP_MSM_MASK); - - STM32_CAP_SETCLOCK(priv->cap, priv->clock, maxtimeout); - - STM32_CAP_SETCHANNEL(priv->cap, 1, - STM32_CAP_EDGE_RISING | - STM32_CAP_MAPPED_TI1); - STM32_CAP_SETCHANNEL(priv->cap, 2, - STM32_CAP_EDGE_FALLING | - STM32_CAP_MAPPED_TI2); - - flags = (int)STM32_CAP_GETFLAGS(priv->cap); - STM32_CAP_ACKFLAGS(priv->cap, flags); - - STM32_CAP_SETISR(priv->cap, stm32_cap_handler, priv); - STM32_CAP_ENABLEINT(priv->cap, STM32_CAP_FLAG_IRQ_CH_1, true); - - priv->started = true; - break; - - case 2: - STM32_CAP_SETSMC(priv->cap, STM32_CAP_SMS_RST | - STM32_CAP_TS_TI2FP2 | - STM32_CAP_MSM_MASK); - - STM32_CAP_SETCLOCK(priv->cap, priv->clock, maxtimeout); - - STM32_CAP_SETCHANNEL(priv->cap, 2, - STM32_CAP_EDGE_RISING | - STM32_CAP_MAPPED_TI1); - STM32_CAP_SETCHANNEL(priv->cap, 1, - STM32_CAP_EDGE_FALLING | - STM32_CAP_MAPPED_TI2); - - flags = (int)STM32_CAP_GETFLAGS(priv->cap); - STM32_CAP_ACKFLAGS(priv->cap, flags); - - STM32_CAP_SETISR(priv->cap, stm32_cap_handler, priv); - STM32_CAP_ENABLEINT(priv->cap, STM32_CAP_FLAG_IRQ_CH_2, true); - - priv->started = true; - break; - - default: - return ERROR; - } - - return OK; -} - -/**************************************************************************** - * Name: stm32_stop - * - * Description: - * Stop the capture - * - * Input Parameters: - * lower - A pointer the publicly visible representation of the - * "lower-half" driver state structure. - * - * Returned Value: - * Zero on success; a negated errno value on failure. - * - ****************************************************************************/ - -static int stm32_stop(struct cap_lowerhalf_s *lower) -{ - struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; - - if (priv->started) - { - STM32_CAP_SETCHANNEL(priv->cap, STM32_CAP_FLAG_IRQ_COUNTER, - STM32_CAP_EDGE_DISABLED); - switch (priv->channel) - { - case 1: - STM32_CAP_ENABLEINT(priv->cap, STM32_CAP_FLAG_IRQ_CH_1, false); - break; - - case 2: - STM32_CAP_ENABLEINT(priv->cap, STM32_CAP_FLAG_IRQ_CH_2, false); - break; - - default: - return ERROR; - } - - STM32_CAP_SETISR(priv->cap, NULL, NULL); - priv->started = false; - return OK; - } - - /* Return ENODEV to indicate that the timer was not running */ - - return -ENODEV; -} - -/**************************************************************************** - * Name: stm32_getduty - * - * Description: - * get result duty - * - * Input Parameters: - * lower - A pointer the publicly visible representation of the - * "lower-half" driver state structure. - * duty - DutyCycle * 100. - * - * Returned Value: - * Zero on success; a negated errno value on failure. - * - ****************************************************************************/ - -static int stm32_getduty(struct cap_lowerhalf_s *lower, uint8_t *duty) -{ - struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; - - irqstate_t flags = enter_critical_section(); - - *duty = priv->duty; - - leave_critical_section(flags); - - return OK; -} - -/**************************************************************************** - * Name: stm32_getfreq - * - * Description: - * get result freq - * - * Input Parameters: - * lower - A pointer the publicly visible representation of the - * "lower-half" driver state structure. - * freq - Frequency in Hz. - * - * Returned Value: - * Zero on success; a negated errno value on failure. - * - ****************************************************************************/ - -static int stm32_getfreq(struct cap_lowerhalf_s *lower, uint32_t *freq) -{ - struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; - - irqstate_t flags = enter_critical_section(); - - *freq = priv->freq; - - leave_critical_section(flags); - - return OK; -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_cap_initialize - * - * Description: - * Initialize one timer for use with the upper_level capture driver. - * - * Input Parameters: - * timer - A number identifying the timer use. The number of valid timer - * IDs varies with the STM32 MCU and MCU family but is somewhere in - * the range of {1,..,5 8,...,14}. - * - * Returned Value: - * On success, a pointer to the STM32 lower half capture driver returned. - * NULL is returned on any failure. - * - ****************************************************************************/ - -struct cap_lowerhalf_s *stm32_cap_initialize(int timer) -{ - struct stm32_lowerhalf_s *lower = NULL; - - switch (timer) - { -#ifdef CONFIG_STM32_TIM1_CAP - case 1: - lower = &g_cap1_lowerhalf; - break; -#endif -#ifdef CONFIG_STM32_TIM2_CAP - case 2: - lower = &g_cap2_lowerhalf; - break; -#endif -#ifdef CONFIG_STM32_TIM3_CAP - case 3: - lower = &g_cap3_lowerhalf; - break; -#endif -#ifdef CONFIG_STM32_TIM4_CAP - case 4: - lower = &g_cap4_lowerhalf; - break; -#endif -#ifdef CONFIG_STM32_TIM5_CAP - case 5: - lower = &g_cap5_lowerhalf; - break; -#endif -#ifdef CONFIG_STM32_TIM6_CAP - case 6: - lower = &g_cap6_lowerhalf; - break; -#endif -#ifdef CONFIG_STM32_TIM9_CAP - case 9: - lower = &g_cap9_lowerhalf; - break; -#endif -#ifdef CONFIG_STM32_TIM10_CAP - case 10: - lower = &g_cap10_lowerhalf; - break; -#endif -#ifdef CONFIG_STM32_TIM11_CAP - case 11: - lower = &g_cap11_lowerhalf; - break; -#endif -#ifdef CONFIG_STM32_TIM12_CAP - case 12: - lower = &g_cap12_lowerhalf; - break; -#endif -#ifdef CONFIG_STM32_TIM13_CAP - case 13: - lower = &g_cap13_lowerhalf; - break; -#endif -#ifdef CONFIG_STM32_TIM14_CAP - case 14: - lower = &g_cap14_lowerhalf; - break; -#endif - default: - { - lower = NULL; - goto errout; - } - } - - /* Initialize the elements of lower half state structure */ - - lower->started = false; - lower->cap = stm32_cap_init(timer); - - if (lower->cap == NULL) - { - lower = NULL; - } - -errout: - return (struct cap_lowerhalf_s *)lower; -} - -#endif /* CONFIG_STM32_CAP */ diff --git a/arch/arm/src/stm32/stm32_ccm.c b/arch/arm/src/stm32/stm32_ccm.c deleted file mode 100644 index 9c87b61d4aff6..0000000000000 --- a/arch/arm/src/stm32/stm32_ccm.c +++ /dev/null @@ -1,43 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_ccm.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "stm32_ccm.h" - -#ifdef HAVE_CCM_HEAP - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -struct mm_heap_s *g_ccm_heap; - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -#endif /* HAVE_CCM_HEAP */ diff --git a/arch/arm/src/stm32/stm32_ccm.h b/arch/arm/src/stm32/stm32_ccm.h deleted file mode 100644 index f5a38d3d41be6..0000000000000 --- a/arch/arm/src/stm32/stm32_ccm.h +++ /dev/null @@ -1,125 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_ccm.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32_STM32_CCM_H -#define __ARCH_ARM_SRC_STM32_STM32_CCM_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -/* Assume that we can support the CCM heap */ - -#define HAVE_CCM_HEAP 1 - -/* Only the STM32 F2, F3, and F4 have CCM memory */ - -#if defined(CONFIG_STM32_STM32F30XX) -# define CCM_START 0x10000000 -# define CCM_END 0x10002000 -#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) || \ - defined(CONFIG_STM32_STM32F33XX) -# define CCM_START 0x10000000 -# define CCM_END 0x10010000 -#else -# undef HAVE_CCM_HEAP -#endif - -/* In order to use the CCM heap, it had to have been excluded from the main - * heap. - */ - -#ifndef CONFIG_STM32_CCMEXCLUDE -# undef HAVE_CCM_HEAP -#endif - -/* Can we support the CCM heap? */ - -#ifdef HAVE_CCM_HEAP - -/* ccm_initialize must be called early in initialization in order to - * initialize the CCM heap. - */ - -#define ccm_initialize() \ - g_ccm_heap = mm_initialize("ccm", (void *)CCM_START, CCM_END-CCM_START) - -/* The ccm_addregion interface could be used if, for example, you want to - * add some other memory region to the CCM heap. I don't really know why - * you might want to do that, but the functionality is essentially free. - */ - -#define ccm_addregion(b,s) mm_addregion(g_ccm_heap, b, s); - -/* Then, once g_ccm_heap has been setup by ccm_initialize(), these memory - * allocators can be used just like the standard memory allocators. - */ - -#define ccm_malloc(s) mm_malloc(g_ccm_heap, s) -#define ccm_zalloc(s) mm_zalloc(g_ccm_heap, s) -#define ccm_calloc(n,s) mm_calloc(g_ccm_heap, n,s) -#define ccm_free(p) mm_free(g_ccm_heap, p) -#define ccm_realloc(p,s) mm_realloc(g_ccm_heap, p, s) -#define ccm_memalign(a,s) mm_memalign(g_ccm_heap, a, s) - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -#ifndef __ASSEMBLY__ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -#ifdef __cplusplus -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -EXTERN struct mm_heap_s *g_ccm_heap; - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -#undef EXTERN -#ifdef __cplusplus -} -#endif - -#endif /* __ASSEMBLY__ */ -#endif /* HAVE_CCM_HEAP */ -#endif /* __ARCH_ARM_SRC_STM32_STM32_CCM_H */ diff --git a/arch/arm/src/stm32/stm32_comp.c b/arch/arm/src/stm32/stm32_comp.c deleted file mode 100644 index 2f25d07a5a37d..0000000000000 --- a/arch/arm/src/stm32/stm32_comp.c +++ /dev/null @@ -1,60 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_comp.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include - -#include -#include -#include - -#include "arm_internal.h" -#include "chip.h" -#include "stm32_comp.h" -#include "stm32_gpio.h" - -/* This file is only a thin shell that includes the correct COMP - * implementation. At this moment STM32 COMP IP versions 1 and 2 are - * supported. - * - STM32 COMP IP version 1: SMT32F33XX - * - STM32 COMP IP version 2: SMT32G4XXX - */ - -#if defined(CONFIG_STM32_HAVE_IP_COMP_V1) -# include "stm32_comp_v1.c" -#elif defined(CONFIG_STM32_HAVE_IP_COMP_V2) -# include "stm32_comp_v2.c" -#else -# error "STM32 COMP IP version not supported." -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ \ No newline at end of file diff --git a/arch/arm/src/stm32/stm32_comp.h b/arch/arm/src/stm32/stm32_comp.h deleted file mode 100644 index 5f3ae2c74e916..0000000000000 --- a/arch/arm/src/stm32/stm32_comp.h +++ /dev/null @@ -1,89 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_comp.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32_STM32_COMP_H -#define __ARCH_ARM_SRC_STM32_STM32_COMP_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "chip.h" - -#include "hardware/stm32_comp.h" - -#if defined(CONFIG_STM32_HAVE_IP_COMP_V1) -# include "stm32_comp_v1.h" -#elif defined(CONFIG_STM32_HAVE_IP_COMP_V2) -# include "stm32_comp_v2.h" -#endif - -/**************************************************************************** - * Pre-processor definitions - ****************************************************************************/ - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -#ifndef __ASSEMBLY__ -#ifdef __cplusplus -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Name: stm32_compinitialize - * - * Description: - * Initialize the COMP. - * - * Input Parameters: - * intf - The COMP interface number. - * - * Returned Value: - * Valid COMP device structure reference on success; a NULL on failure. - * - * Assumptions: - * 1. Clock to the COMP block has enabled, - * 2. Board-specific logic has already configured - * - ****************************************************************************/ - -struct comp_dev_s *stm32_compinitialize(int intf); - -#undef EXTERN -#ifdef __cplusplus -} -#endif -#endif /* __ASSEMBLY__ */ - -#endif /* __ARCH_ARM_SRC_STM32_STM32_COMP_H */ diff --git a/arch/arm/src/stm32/stm32_comp_v1.c b/arch/arm/src/stm32/stm32_comp_v1.c deleted file mode 100644 index 17e5ccefab23a..0000000000000 --- a/arch/arm/src/stm32/stm32_comp_v1.c +++ /dev/null @@ -1,1065 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_comp_v1.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Some COMP peripheral must be enabled */ - -/* Up to 7 comparators in STM32F3 Series */ - -#if defined(CONFIG_STM32_COMP1) || defined(CONFIG_STM32_COMP2) || \ - defined(CONFIG_STM32_COMP3) || defined(CONFIG_STM32_COMP4) || \ - defined(CONFIG_STM32_COMP5) || defined(CONFIG_STM32_COMP6) || \ - defined(CONFIG_STM32_COMP7) - -#ifndef CONFIG_STM32_SYSCFG -# error "SYSCFG clock enable must be set" -#endif - -/* @TODO: support for STM32F30XX and STM32F37XX comparators */ - -#if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) || \ - defined(CONFIG_STM32_STM32F37XX) - -/* Currently only STM32F33XX supported */ - -#if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX) -# error "Not supported yet" -#endif - -#if defined(CONFIG_STM32_STM32F33XX) -# if defined(CONFIG_STM32_COMP1) || defined(CONFIG_STM32_COMP3) || \ - defined(CONFIG_STM32_COMP5) || defined(CONFIG_STM32_COMP7) -# error "STM32F33 supports only COMP2, COMP4 and COMP6" -# endif -#endif - -/* COMP2 default configuration **********************************************/ - -#ifdef CONFIG_STM32_COMP2 -# ifndef COMP2_BLANLKING -# define COMP2_BLANKING COMP_BLANKING_DEFAULT -# endif -# ifndef COMP2_POL -# define COMP2_POL COMP_BLANKING_DEFAULT -# endif -# ifndef COMP2_INM -# define COMP2_INM COMP_INM_DEFAULT -# endif -# ifndef COMP2_OUTSEL -# define COMP2_OUTSEL COMP_OUTSEL_DEFAULT -# endif -# ifndef COMP2_LOCK -# define COMP2_LOCK COMP_LOCK_DEFAULT -# endif -# ifndef GPIO_COMP2_INM -# warning "GPIO_COMP2_INM not selected. Set default value to GPIO_COMP2_INM1" -# define GPIO_COMP2_INM GPIO_COMP2_INM_1 -# endif -#endif - -/* COMP4 default configuration **********************************************/ - -#ifdef CONFIG_STM32_COMP4 -# ifndef COMP4_BLANLKING -# define COMP4_BLANKING COMP_BLANKING_DEFAULT -# endif -# ifndef COMP4_POL -# define COMP4_POL COMP_BLANKING_DEFAULT -# endif -# ifndef COMP4_INM -# define COMP4_INM COMP_INM_DEFAULT -# endif -# ifndef COMP4_OUTSEL -# define COMP4_OUTSEL COMP_OUTSEL_DEFAULT -# endif -# ifndef COMP4_LOCK -# define COMP4_LOCK COMP_LOCK_DEFAULT -# endif -# ifndef GPIO_COMP4_INM -# warning "GPIO_COMP4_INM not selected. Set default value to GPIO_COMP4_INM1" -# define GPIO_COMP4_INM GPIO_COMP4_INM_1 -# endif -#endif - -/* COMP6 default configuration **********************************************/ - -#ifdef CONFIG_STM32_COMP6 -# ifndef COMP6_BLANLKING -# define COMP6_BLANKING COMP_BLANKING_DEFAULT -# endif -# ifndef COMP6_POL -# define COMP6_POL COMP_BLANKING_DEFAULT -# endif -# ifndef COMP6_INM -# define COMP6_INM COMP_INM_DEFAULT -# endif -# ifndef COMP6_OUTSEL -# define COMP6_OUTSEL COMP_OUTSEL_DEFAULT -# endif -# ifndef COMP6_LOCK -# define COMP6_LOCK COMP_LOCK_DEFAULT -# endif -# ifndef GPIO_COMP6_INM -# warning "GPIO_COMP6_INM not selected. Set default value to GPIO_COMP6_INM1" -# define GPIO_COMP6_INM GPIO_COMP6_INM_1 -# endif -#endif - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/* This structure describes the configuration of one COMP device */ - -struct stm32_comp_s -{ - uint8_t blanking; /* Blanking source */ - uint8_t pol; /* Output polarity */ - uint8_t inm; /* Inverting input selection */ - uint8_t out; /* Comparator output */ - uint8_t lock; /* Comparator Lock */ - uint32_t csr; /* Control and status register */ -#ifndef CONFIG_STM32_STM32F33XX - uint8_t mode; /* Comparator mode */ - uint8_t hyst; /* Comparator hysteresis */ - /* @TODO: Window mode + INP selection */ -#endif -}; - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -/* COMP Register access */ - -static inline void comp_modify_csr(struct stm32_comp_s *priv, - uint32_t clearbits, uint32_t setbits); -static inline uint32_t comp_getreg_csr(struct stm32_comp_s *priv); -static inline void comp_putreg_csr(struct stm32_comp_s *priv, - uint32_t value); -static bool stm32_complock_get(struct stm32_comp_s *priv); -static int stm32_complock(struct stm32_comp_s *priv, bool lock); - -/* COMP Driver Methods */ - -static void comp_shutdown(struct comp_dev_s *dev); -static int comp_setup(struct comp_dev_s *dev); -static int comp_read(struct comp_dev_s *dev); -static int comp_ioctl(struct comp_dev_s *dev, int cmd, - unsigned long arg); - -/* Initialization */ - -static int stm32_compconfig(struct stm32_comp_s *priv); -static int stm32_compenable(struct stm32_comp_s *priv, bool enable); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -static const struct comp_ops_s g_compops = -{ - .ao_shutdown = comp_shutdown, - .ao_setup = comp_setup, - .ao_read = comp_read, - .ao_ioctl = comp_ioctl, -}; - -#ifdef CONFIG_STM32_COMP1 -static struct stm32_comp_s g_comp1priv = -{ - .blanking = COMP1_BLANKING, - .pol = COMP1_POL, - .inm = COMP1_INM, - .out = COMP1_OUTSEL, - .lock = COMP1_LOCK, - .csr = STM32_COMP1_CSR, -#ifndef CONFIG_STM32_STM32F33XX - .mode = COMP1_MODE, - .hyst = COMP1_HYST, -#endif -}; - -static struct comp_dev_s g_comp1dev = -{ - .ad_ops = &g_compops, - .ad_priv = &g_comp1priv, -}; -#endif - -#ifdef CONFIG_STM32_COMP2 -static struct stm32_comp_s g_comp2priv = -{ - .blanking = COMP2_BLANKING, - .pol = COMP2_POL, - .inm = COMP2_INM, - .out = COMP2_OUTSEL, - .lock = COMP2_LOCK, - .csr = STM32_COMP2_CSR, -#ifndef CONFIG_STM32_STM32F33XX - .mode = COMP2_MODE, - .hyst = COMP2_HYST, -#endif -}; - -static struct comp_dev_s g_comp2dev = -{ - .ad_ops = &g_compops, - .ad_priv = &g_comp2priv, -}; -#endif - -#ifdef CONFIG_STM32_COMP3 -static struct stm32_comp_s g_comp3priv = -{ - .blanking = COMP3_BLANKING, - .pol = COMP3_POL, - .inm = COMP3_INM, - .out = COMP3_OUTSEL, - .lock = COMP3_LOCK, - .csr = STM32_COMP3_CSR, -#ifndef CONFIG_STM32_STM32F33XX - .mode = COMP3_MODE, - .hyst = COMP3_HYST, -#endif -}; - -static struct comp_dev_s g_comp3dev = -{ - .ad_ops = &g_compops, - .ad_priv = &g_comp3priv, -}; -#endif - -#ifdef CONFIG_STM32_COMP4 -static struct stm32_comp_s g_comp4priv = -{ - .blanking = COMP4_BLANKING, - .pol = COMP4_POL, - .inm = COMP4_INM, - .out = COMP4_OUTSEL, - .lock = COMP4_LOCK, - .csr = STM32_COMP4_CSR, -#ifndef CONFIG_STM32_STM32F33XX - .mode = COMP4_MODE, - .hyst = COMP4_HYST, -#endif -}; - -static struct comp_dev_s g_comp4dev = -{ - .ad_ops = &g_compops, - .ad_priv = &g_comp4priv, -}; -#endif - -#ifdef CONFIG_STM32_COMP5 -static struct stm32_comp_s g_comp5priv = -{ - .blanking = COMP5_BLANKING, - .pol = COMP5_POL, - .inm = COMP5_INM, - .out = COMP5_OUTSEL, - .lock = COMP5_LOCK, - .csr = STM32_COMP5_CSR, -#ifndef CONFIG_STM32_STM32F33XX - .mode = COMP5_MODE, - .hyst = COMP5_HYST, -#endif -}; - -static struct comp_dev_s g_comp5dev = -{ - .ad_ops = &g_compops, - .ad_priv = &g_comp5priv, -}; -#endif - -#ifdef CONFIG_STM32_COMP6 -static struct stm32_comp_s g_comp6priv = -{ - .blanking = COMP6_BLANKING, - .pol = COMP6_POL, - .inm = COMP6_INM, - .out = COMP6_OUTSEL, - .lock = COMP6_LOCK, - .csr = STM32_COMP6_CSR, -#ifndef CONFIG_STM32_STM32F33XX - .mode = COMP6_MODE, - .hyst = COMP6_HYST, -#endif -}; - -static struct comp_dev_s g_comp6dev = -{ - .ad_ops = &g_compops, - .ad_priv = &g_comp6priv, -}; -#endif - -#ifdef CONFIG_STM32_COMP7 -static struct stm32_comp_s g_comp7priv = -{ - .blanking = COMP7_BLANKING, - .pol = COMP7_POL, - .inm = COMP7_INM, - .out = COMP7_OUTSEL, - .lock = COMP7_LOCK, - .csr = STM32_COMP7_CSR, -#ifndef CONFIG_STM32_STM32F33XX - .mode = COMP7_MODE, - .hyst = COMP7_HYST, -#endif -}; - -static struct comp_dev_s g_comp7dev = -{ - .ad_ops = &g_compops, - .ad_priv = &g_comp7priv, -}; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: comp_modify_csr - * - * Description: - * Modify the value of a 32-bit COMP CSR register (not atomic). - * - * Input Parameters: - * priv - A reference to the COMP structure - * clrbits - The bits to clear - * setbits - The bits to set - * - * Returned Value: - * None - * - ****************************************************************************/ - -static inline void comp_modify_csr(struct stm32_comp_s *priv, - uint32_t clearbits, uint32_t setbits) -{ - uint32_t csr = priv->csr; - - modifyreg32(csr, clearbits, setbits); -} - -/**************************************************************************** - * Name: comp_getreg_csr - * - * Description: - * Read the value of an COMP CSR register - * - * Input Parameters: - * priv - A reference to the COMP structure - * - * Returned Value: - * The current contents of the COMP CSR register - * - ****************************************************************************/ - -static inline uint32_t comp_getreg_csr(struct stm32_comp_s *priv) -{ - uint32_t csr = priv->csr; - - return getreg32(csr); -} - -/**************************************************************************** - * Name: comp_putreg_csr - * - * Description: - * Write a value to an COMP register. - * - * Input Parameters: - * priv - A reference to the COMP structure - * value - The value to write to the COMP CSR register - * - * Returned Value: - * None - * - ****************************************************************************/ - -static inline void comp_putreg_csr(struct stm32_comp_s *priv, - uint32_t value) -{ - uint32_t csr = priv->csr; - - putreg32(value, csr); -} - -/**************************************************************************** - * Name: stm32_comp_complock_get - * - * Description: - * Get COMP lock bit state - * - * Input Parameters: - * priv - A reference to the COMP structure - * - * Returned Value: - * True if COMP locked, false if not locked - * - ****************************************************************************/ - -static bool stm32_complock_get(struct stm32_comp_s *priv) -{ - uint32_t regval; - - regval = comp_getreg_csr(priv); - - return (((regval & COMP_CSR_LOCK) == 0) ? false : true); -} - -/**************************************************************************** - * Name: stm32_complock - * - * Description: - * Lock comparator CSR register - * - * Input Parameters: - * priv - A reference to the COMP structure - * enable - lock flag - * - * Returned Value: - * 0 on success, a negated errno value on failure - * - ****************************************************************************/ - -static int stm32_complock(struct stm32_comp_s *priv, bool lock) -{ - bool current; - - current = stm32_complock_get(priv); - - if (current) - { - if (lock == false) - { - aerr("ERROR: COMP LOCK can be cleared only by a system reset\n"); - - return -EPERM; - } - } - else - { - if (lock == true) - { - comp_modify_csr(priv, 0, COMP_CSR_LOCK); - - priv->lock = COMP_LOCK_RO; - } - } - - return OK; -} - -/**************************************************************************** - * Name: stm32_compconfig - * - * Description: - * Configure comparator and used I/Os - * - * Input Parameters: - * priv - A reference to the COMP structure - * - * Returned Value: - * 0 on success, a negated errno value on failure - * - * REVISIT: Where to config comparator output pin ? - * - ****************************************************************************/ - -static int stm32_compconfig(struct stm32_comp_s *priv) -{ - uint32_t regval = 0; - int index; - - /* Get comparator index */ - - switch (priv->csr) - { -#ifdef CONFIG_STM32_COMP1 - case STM32_COMP1_CSR: - index = 1; - break; -#endif - -#ifdef CONFIG_STM32_COMP2 - case STM32_COMP2_CSR: - index = 2; - break; -#endif - -#ifdef CONFIG_STM32_COMP3 - case STM32_COMP3_CSR: - index = 3; - break; -#endif - -#ifdef CONFIG_STM32_COMP4 - case STM32_COMP4_CSR: - index = 4; - break; -#endif - -#ifdef CONFIG_STM32_COMP5 - case STM32_COMP5_CSR: - index = 5; - break; -#endif - -#ifdef CONFIG_STM32_COMP6 - case STM32_COMP6_CSR: - index = 6; - break; -#endif - -#ifdef CONFIG_STM32_COMP7 - case STM32_COMP7_CSR: - index = 7; - break; -#endif - - default: - return -EINVAL; - } - - /* Configure non inverting input */ - - switch (index) - { -#ifdef CONFIG_STM32_COMP1 - case 1: - stm32_configgpio(GPIO_COMP1_INP); - break; -#endif - -#ifdef CONFIG_STM32_COMP2 - case 2: - stm32_configgpio(GPIO_COMP2_INP); - break; -#endif - -#ifdef CONFIG_STM32_COMP3 - case 3: - stm32_configgpio(GPIO_COMP3_INP); - break; -#endif - -#ifdef CONFIG_STM32_COMP4 - case 4: - stm32_configgpio(GPIO_COMP4_INP); - break; -#endif - -#ifdef CONFIG_STM32_COMP5 - case 5: - stm32_configgpio(GPIO_COMP5_INP); - break; -#endif - -#ifdef CONFIG_STM32_COMP6 - case 6: - stm32_configgpio(GPIO_COMP6_INP); - break; -#endif - -#ifdef CONFIG_STM32_COMP7 - case 7: - stm32_configgpio(GPIO_COMP7_INP); - break; -#endif - - default: - return -EINVAL; - } - - /* Set Comparator inverting input */ - - switch (priv->inm) - { - case COMP_INMSEL_1P4VREF: - regval |= COMP_CSR_INMSEL_1P4VREF; - break; - - case COMP_INMSEL_1P2VREF: - regval |= COMP_CSR_INMSEL_1P2VREF; - break; - - case COMP_INMSEL_3P4VREF: - regval |= COMP_CSR_INMSEL_3P4VREF; - break; - - case COMP_INMSEL_VREF: - regval |= COMP_CSR_INMSEL_VREF; - break; - - case COMP_INMSEL_DAC1CH1: - regval |= COMP_CSR_INMSEL_DAC1CH1; - break; - - case COMP_INMSEL_DAC1CH2: - regval |= COMP_CSR_INMSEL_DAC1CH2; - break; - - case COMP_INMSEL_PIN: - { - /* INMSEL PIN configuration dependent on COMP index */ - - switch (index) - { - /* TODO: Inverting input pin configuration for COMP1/3/5/7 */ - -#ifdef CONFIG_STM32_COMP2 - case 2: - { - /* COMP2_INM can be PA2 or PA4 */ - - stm32_configgpio(GPIO_COMP2_INM); - regval |= (GPIO_COMP2_INM == GPIO_COMP2_INM_1 ? - COMP_CSR_INMSEL_PA2 : COMP_CSR_INMSEL_PA4); - break; - } -#endif - -#ifdef CONFIG_STM32_COMP4 - case 4: - { - /* COMP4_INM can be PB2 or PA4 */ - - stm32_configgpio(GPIO_COMP4_INM); - regval |= (GPIO_COMP4_INM == GPIO_COMP4_INM_1 ? - COMP_CSR_INMSEL_PB2 : COMP_CSR_INMSEL_PA4); - break; - } -#endif - -#ifdef CONFIG_STM32_COMP6 - case 6: - { - /* COMP6_INM can be PB15 or PA4 */ - - stm32_configgpio(GPIO_COMP6_INM); - regval |= (GPIO_COMP6_INM == GPIO_COMP6_INM_1 ? - COMP_CSR_INMSEL_PB15 : COMP_CSR_INMSEL_PA4); - break; - } -#endif - - default: - return -EINVAL; - } - - break; - } - - default: - return -EINVAL; - } - - /* Set Comparator output selection */ - - switch (priv->out) - { - case COMP_OUTSEL_NOSEL: - regval |= COMP_CSR_OUTSEL_NOSEL; - break; - - case COMP_OUTSEL_BRKACTH: - regval |= COMP_CSR_OUTSEL_BRKACTH; - break; - - case COMP_OUTSEL_BRK2: - regval |= COMP_CSR_OUTSEL_BRK2; - break; - - case COMP_OUTSEL_T1OCC: - regval |= COMP_CSR_OUTSEL_T1OCC; - break; - - case COMP_OUTSEL_T3CAP3: - regval |= COMP_CSR_OUTSEL_T3CAP3; - break; - - case COMP_OUTSEL_T2CAP2: - regval |= COMP_CSR_OUTSEL_T2CAP2; - break; - - case COMP_OUTSEL_T1CAP1: - regval |= COMP_CSR_OUTSEL_T1CAP1; - break; - - case COMP_OUTSEL_T2CAP4: - regval |= COMP_CSR_OUTSEL_T2CAP4; - break; - - case COMP_OUTSEL_T15CAP2: - regval |= COMP_CSR_OUTSEL_T15CAP2; - break; - - case COMP_OUTSEL_T2OCC: - if (index == 2) - { - regval |= COMP2_CSR_OUTSEL_T2OCC; - } - else if (index == 6) - { - regval |= COMP6_CSR_OUTSEL_T2OCC; - } - - break; - - case COMP_OUTSEL_T16OCC: - regval |= COMP_CSR_OUTSEL_T16OCC; - break; - - case COMP_OUTSEL_T3CAP1: - regval |= COMP_CSR_OUTSEL_T3CAP1; - break; - - case COMP_OUTSEL_T15OCC: - regval |= COMP_CSR_OUTSEL_T15OCC; - break; - - case COMP_OUTSEL_T16CAP1: - regval |= COMP_CSR_OUTSEL_T16CAP1; - break; - - case COMP_OUTSEL_T3OCC: - regval |= COMP_CSR_OUTSEL_T3OCC; - break; - - default: - return -EINVAL; - } - - /* Set Comparator output polarity */ - - regval |= (priv->pol == COMP_POL_INVERTED ? COMP_CSR_POL : 0); - - /* Set Comparator output blanking source */ - - switch (priv->blanking) - { - case COMP_BLANKING_DIS: - regval |= COMP_CSR_BLANKING_DIS; - break; - - case COMP_BLANKING_T1OC5: - regval |= COMP_CSR_BLANKING_T1OC5; - break; - - case COMP_BLANKING_T3OC4: - regval |= COMP_CSR_BLANKING_T3OC4; - break; - - case COMP_BLANKING_T2OC3: - regval |= COMP_CSR_BLANKING_T2OC3; - break; - - case COMP_BLANKING_T15OC1: - regval |= COMP_CSR_BLANKING_T15OC1; - break; - - case COMP_BLANKING_T2OC4: - regval |= COMP_CSR_BLANKING_T2OC4; - break; - - case COMP_BLANKING_T15OC2: - regval |= COMP_CSR_BLANKING_T15OC1; - break; - - default: - return -EINVAL; - } - - /* Save CSR register */ - - comp_putreg_csr(priv, regval); - - /* Enable Comparator */ - - stm32_compenable(priv, true); - - /* Lock Comparator if needed */ - - if (priv->lock == COMP_LOCK_RO) - { - stm32_complock(priv, true); - } - - return OK; -} - -/**************************************************************************** - * Name: stm32_compenable - * - * Description: - * Enable/disable comparator - * - * Input Parameters: - * priv - A reference to the COMP structure - * enable - enable/disable flag - * - * Returned Value: - * 0 on success, a negated errno value on failure - * - ****************************************************************************/ - -static int stm32_compenable(struct stm32_comp_s *priv, bool enable) -{ - bool lock; - - ainfo("enable: %d\n", enable ? 1 : 0); - - lock = stm32_complock_get(priv); - - if (lock) - { - aerr("ERROR: Comparator locked!\n"); - - return -EPERM; - } - else - { - if (enable) - { - /* Enable the COMP */ - - comp_modify_csr(priv, 0, COMP_CSR_COMPEN); - } - else - { - /* Disable the COMP */ - - comp_modify_csr(priv, COMP_CSR_COMPEN, 0); - } - } - - return OK; -} - -/**************************************************************************** - * Name: adc_setup - * - * Description: - * Configure the COMP. This method is called the first time that the COMP - * device is opened. This will occur when the port is first opened. - * This setup includes configuring and attaching COMP interrupts. - * Interrupts are all disabled upon return. - * - * Input Parameters: - * - * Returned Value: - * - ****************************************************************************/ - -static int comp_setup(struct comp_dev_s *dev) -{ -#warning "Missing logic" - - return OK; -} - -/**************************************************************************** - * Name: comp_shutdown - * - * Description: - * Disable the COMP. This method is called when the COMP device is closed. - * This method reverses the operation the setup method. - * Works only if COMP device is not locked. - * - * Input Parameters: - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void comp_shutdown(struct comp_dev_s *dev) -{ -#warning "Missing logic" -} - -/**************************************************************************** - * Name: comp_read - * - * Description: - * Get the COMP output state. - * - * Input Parameters: - * - * Returned Value: - * 0 if output is low (non-inverting input below inverting input), - * 1 if output is high (non inverting input above inverting input). - * - ****************************************************************************/ - -static int comp_read(struct comp_dev_s *dev) -{ - struct stm32_comp_s *priv; - uint32_t regval; - - priv = dev->ad_priv; - regval = comp_getreg_csr(priv); - - return (((regval & COMP_CSR_OUT) == 0) ? 0 : 1); -} - -/**************************************************************************** - * Name: comp_ioctl - * - * Description: - * All ioctl calls will be routed through this method. - * - * Input Parameters: - * dev - pointer to device structure used by the driver - * cmd - command - * arg - arguments passed with command - * - * Returned Value: - * Zero on success; a negated errno value on failure. - * - ****************************************************************************/ - -static int comp_ioctl(struct comp_dev_s *dev, int cmd, unsigned long arg) -{ -#warning "Missing logic" - return -ENOTTY; -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_compinitialize - * - * Description: - * Initialize the COMP. - * - * Input Parameters: - * intf - The COMP interface number. - * - * Returned Value: - * Valid COMP device structure reference on success; a NULL on failure. - * - * Assumptions: - * 1. Clock to the COMP block has enabled, - * 2. Board-specific logic has already configured - * - ****************************************************************************/ - -struct comp_dev_s *stm32_compinitialize(int intf) -{ - struct comp_dev_s *dev; - struct stm32_comp_s *comp; - int ret; - - switch (intf) - { -#ifdef CONFIG_STM32_COMP1 - case 1: - ainfo("COMP1 selected\n"); - dev = &g_comp1dev; - break; -#endif - -#ifdef CONFIG_STM32_COMP2 - case 2: - ainfo("COMP2 selected\n"); - dev = &g_comp2dev; - break; -#endif - -#ifdef CONFIG_STM32_COMP3 - case 3: - ainfo("COMP3 selected\n"); - dev = &g_comp3dev; - break; -#endif - -#ifdef CONFIG_STM32_COMP4 - case 4: - ainfo("COMP4 selected\n"); - dev = &g_comp4dev; - break; -#endif - -#ifdef CONFIG_STM32_COMP5 - case 5: - ainfo("COMP5 selected\n"); - dev = &g_comp5dev; - break; -#endif - -#ifdef CONFIG_STM32_COMP6 - case 6: - ainfo("COMP6 selected\n"); - dev = &g_comp6dev; - break; -#endif - -#ifdef CONFIG_STM32_COMP7 - case 7: - ainfo("COMP7 selected\n"); - dev = &g_comp7dev; - break; -#endif - - default: - aerr("ERROR: No COMP interface defined\n"); - return NULL; - } - - /* Configure selected comparator */ - - comp = dev->ad_priv; - - ret = stm32_compconfig(comp); - if (ret < 0) - { - aerr("ERROR: Failed to initialize COMP%d: %d\n", intf, ret); - return NULL; - } - - return dev; -} - -#endif /* CONFIG_STM32_STM32F30XX || CONFIG_STM32_STM32F33XX || - * CONFIG_STM32_STM32F37XX - */ - -#endif /* CONFIG_STM32_COMP2 || CONFIG_STM32_COMP4 || - * CONFIG_STM32_COMP6 - */ diff --git a/arch/arm/src/stm32/stm32_comp_v1.h b/arch/arm/src/stm32/stm32_comp_v1.h deleted file mode 100644 index 5389e5ddca15b..0000000000000 --- a/arch/arm/src/stm32/stm32_comp_v1.h +++ /dev/null @@ -1,153 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_comp_v1.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32_STM32_COMP_V1_H -#define __ARCH_ARM_SRC_STM32_STM32_COMP_V1_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#ifdef CONFIG_STM32_COMP - -/**************************************************************************** - * Pre-processor definitions - ****************************************************************************/ - -#define COMP_BLANKING_DEFAULT COMP_BLANKING_DIS /* No blanking */ -#define COMP_POL_DEFAULT COMP_POL_NONINVERT /* Output is not inverted */ -#define COMP_INM_DEFAULT COMP_INMSEL_1P4VREF /* 1/4 of Vrefint as INM */ -#define COMP_OUTSEL_DEFAULT COMP_OUTSEL_NOSEL /* Output not selected */ -#define COMP_LOCK_DEFAULT COMP_LOCK_RW /* Do not lock CSR register */ - -#ifndef CONFIG_STM32_STM32F33XX -#define COMP_MODE_DEFAULT -#define COMP_HYST_DEFAULT -#define COMP_WINMODE_DEFAULT -#endif - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -/* Blanking source */ - -enum stm32_comp_blanking_e -{ - COMP_BLANKING_DIS, -#if defined(CONFIG_STM32_STM32F33XX) - COMP_BLANKING_T1OC5, - COMP_BLANKING_T3OC4, - COMP_BLANKING_T2OC3, - COMP_BLANKING_T3OC3, - COMP_BLANKING_T15OC1, - COMP_BLANKING_T2OC4, - COMP_BLANKING_T15OC2, -#endif -}; - -/* Output polarisation */ - -enum stm32_comp_pol_e -{ - COMP_POL_NONINVERT, - COMP_POL_INVERTED -}; - -/* Inverting input */ - -enum stm32_comp_inm_e -{ - COMP_INMSEL_1P4VREF, - COMP_INMSEL_1P2VREF, - COMP_INMSEL_3P4VREF, - COMP_INMSEL_VREF, - COMP_INMSEL_DAC1CH1, - COMP_INMSEL_DAC1CH2, - COMP_INMSEL_PIN -}; - -/* Output selection */ - -enum stm32_comp_outsel_e -{ - COMP_OUTSEL_NOSEL, -#if defined(CONFIG_STM32_STM32F33XX) - COMP_OUTSEL_BRKACTH, - COMP_OUTSEL_BRK2, - COMP_OUTSEL_T1OCC, /* COMP2 only */ - COMP_OUTSEL_T3CAP3, /* COMP4 only */ - COMP_OUTSEL_T2CAP2, /* COMP6 only */ - COMP_OUTSEL_T1CAP1, /* COMP2 only */ - COMP_OUTSEL_T2CAP4, /* COMP2 only */ - COMP_OUTSEL_T15CAP2, /* COMP4 only */ - COMP_OUTSEL_T2OCC, /* COMP6 only */ - COMP_OUTSEL_T16OCC, /* COMP2 only */ - COMP_OUTSEL_T3CAP1, /* COMP2 only */ - COMP_OUTSEL_T15OCC, /* COMP4 only */ - COMP_OUTSEL_T16CAP1, /* COMP6 only */ - COMP_OUTSEL_T3OCC, /* COMP2 and COMP4 only */ -#endif -}; - -/* CSR register lock state */ - -enum stm32_comp_lock_e -{ - COMP_LOCK_RW, - COMP_LOCK_RO -}; - -#ifndef CONFIG_STM32_STM32F33XX - -/* Hysteresis */ - -enum stm32_comp_hyst_e -{ - COMP_HYST_DIS, - COMP_HYST_LOW, - COMP_HYST_MEDIUM, - COMP_HYST_HIGH -}; - -/* Power/Speed Modes */ - -enum stm32_comp_mode_e -{ - COMP_MODE_HIGHSPEED, - COMP_MODE_MEDIUMSPEED, - COMP_MODE_LOWPOWER, - COMP_MODE_ULTRALOWPOWER -}; - -/* Window mode */ - -enum stm32_comp_winmode_e -{ - COMP_WINMODE_DIS, - COMP_WINMODE_EN -}; - -#endif - -#endif /* CONFIG_STM23_COMP */ -#endif /* __ARCH_ARM_SRC_STM32_STM32_COMP_V1_H */ diff --git a/arch/arm/src/stm32/stm32_comp_v2.c b/arch/arm/src/stm32/stm32_comp_v2.c deleted file mode 100644 index d6fbae9c202ad..0000000000000 --- a/arch/arm/src/stm32/stm32_comp_v2.c +++ /dev/null @@ -1,1007 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_comp_v2.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Some COMP peripheral must be enabled and the device must be supported */ - -#define DEVICE_NOT_SUPPORTED - -#if defined(CONFIG_STM32_COMP) - -#ifndef CONFIG_STM32_SYSCFG -# error "SYSCFG clock enable must be set" -#endif - -#if defined(CONFIG_STM32_STM32G43XX) -# undef DEVICE_NOT_SUPPORTED -# if defined(CONFIG_STM32_COMP5) || defined(CONFIG_STM32_COMP6) || \ - defined(CONFIG_STM32_COMP7) -# error "STM32G43XX supports only COMP1, COMP2, COMP3 and COMP4" -# endif -#endif - -#if defined(DEVICE_NOT_SUPPORTED) -# error "Device not supported" -#endif - -#if defined(CONFIG_STM32_COMP1_OUT) || defined(CONFIG_STM32_COMP2_OUT) || \ - defined(CONFIG_STM32_COMP3_OUT) || defined(CONFIG_STM32_COMP4_OUT) || \ - defined(CONFIG_STM32_COMP5_OUT) || defined(CONFIG_STM32_COMP6_OUT) || \ - defined(CONFIG_STM32_COMP7_OUT) -# define COMP_OUT_GPIO -#endif - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/* This structure describes the configuration of one COMP device */ - -struct stm32_comp_s -{ - uint8_t inm; /* Inverting input selection */ - uint32_t gpio_inm; /* Inverting input pin */ - uint8_t inp; /* Non inverting input selection */ - uint32_t gpio_inp; /* Non-inverting input pin */ - uint8_t pol; /* Output polarity */ - uint8_t hyst; /* Comparator hysteresis */ - uint8_t blanking; /* Blanking source */ - uint8_t lock; /* Comparator Lock */ - uint32_t csr; /* Control and status register */ -}; - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -/* COMP Register access */ - -static inline void comp_modify_csr(struct stm32_comp_s *priv, - uint32_t clearbits, uint32_t setbits); -static inline uint32_t comp_getreg_csr(struct stm32_comp_s *priv); -static inline void comp_putreg_csr(struct stm32_comp_s *priv, - uint32_t value); - -/* COMP Driver Methods */ - -#if defined (CONFIG_COMP) -static void comp_shutdown(struct comp_dev_s *dev); -static int comp_setup(struct comp_dev_s *dev); -static int comp_read(struct comp_dev_s *dev); -static int comp_ioctl(struct comp_dev_s *dev, int cmd, - unsigned long arg); -#endif - -static int comp_config(struct stm32_comp_s *priv); -static int comp_enable(struct stm32_comp_s *priv, bool enable); -static bool comp_lock_get(struct stm32_comp_s *priv); -static int comp_lock_set(struct stm32_comp_s *priv, bool lock); - -static int comp_config_inmpin(struct stm32_comp_s *priv); -static int comp_config_inppin(struct stm32_comp_s *priv); -#if defined(COMP_OUT_GPIO) -static int comp_config_outpin(struct stm32_comp_s *priv); -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -#ifdef CONFIG_COMP -static const struct comp_ops_s g_compops = -{ - .ao_shutdown = comp_shutdown, - .ao_setup = comp_setup, - .ao_read = comp_read, - .ao_ioctl = comp_ioctl, -}; -#endif - -#ifdef CONFIG_STM32_COMP1 -static struct stm32_comp_s g_comp1priv = -{ - .inm = CONFIG_STM32_COMP1_INM, - .inp = CONFIG_STM32_COMP1_INP, - .pol = CONFIG_STM32_COMP1_POL, - .hyst = CONFIG_STM32_COMP1_HYST, - .blanking = CONFIG_STM32_COMP1_BLANKSEL, - .lock = CONFIG_STM32_COMP1_LOCK, - .gpio_inp = GPIO_COMP1_INP, - .csr = STM32_COMP1_CSR -}; - -static struct comp_dev_s g_comp1dev = -{ -#ifdef CONFIG_COMP - .ad_ops = &g_compops, -#endif - .ad_priv = &g_comp1priv, -}; -#endif - -#ifdef CONFIG_STM32_COMP2 -static struct stm32_comp_s g_comp2priv = -{ - .inm = CONFIG_STM32_COMP2_INM, - .inp = CONFIG_STM32_COMP2_INP, - .pol = CONFIG_STM32_COMP2_POL, - .hyst = CONFIG_STM32_COMP2_HYST, - .blanking = CONFIG_STM32_COMP2_BLANKSEL, - .lock = CONFIG_STM32_COMP2_LOCK, - .gpio_inp = GPIO_COMP2_INP, - .csr = STM32_COMP2_CSR -}; - -static struct comp_dev_s g_comp2dev = -{ -#ifdef CONFIG_COMP - .ad_ops = &g_compops, -#endif - .ad_priv = &g_comp2priv, -}; -#endif - -#ifdef CONFIG_STM32_COMP3 -static struct stm32_comp_s g_comp3priv = -{ - .inm = CONFIG_STM32_COMP3_INM, - .inp = CONFIG_STM32_COMP3_INP, - .pol = CONFIG_STM32_COMP3_POL, - .hyst = CONFIG_STM32_COMP3_HYST, - .blanking = CONFIG_STM32_COMP3_BLANKSEL, - .lock = CONFIG_STM32_COMP3_LOCK, - .gpio_inp = GPIO_COMP3_INP, - .csr = STM32_COMP3_CSR -}; - -static struct comp_dev_s g_comp3dev = -{ -#ifdef CONFIG_COMP - .ad_ops = &g_compops, -#endif - .ad_priv = &g_comp3priv, -}; -#endif - -#ifdef CONFIG_STM32_COMP4 -static struct stm32_comp_s g_comp4priv = -{ - .inm = CONFIG_STM32_COMP4_INM, - .inp = CONFIG_STM32_COMP4_INP, - .pol = CONFIG_STM32_COMP4_POL, - .hyst = CONFIG_STM32_COMP4_HYST, - .blanking = CONFIG_STM32_COMP4_BLANKSEL, - .lock = CONFIG_STM32_COMP4_LOCK, - .gpio_inp = GPIO_COMP4_INP, - .csr = STM32_COMP4_CSR -}; - -static struct comp_dev_s g_comp4dev = -{ -#ifdef CONFIG_COMP - .ad_ops = &g_compops, -#endif - .ad_priv = &g_comp4priv, -}; -#endif - -#ifdef CONFIG_STM32_COMP5 -static struct stm32_comp_s g_comp5priv = -{ - .inm = CONFIG_STM32_COMP5_INM, - .inp = CONFIG_STM32_COMP5_INP, - .pol = CONFIG_STM32_COMP5_POL, - .hyst = CONFIG_STM32_COMP5_HYST, - .blanking = CONFIG_STM32_COMP5_BLANKSEL, - .lock = CONFIG_STM32_COMP5_LOCK, - .gpio_inp = GPIO_COMP5_INP, - .csr = STM32_COMP5_CSR -}; - -static struct comp_dev_s g_comp5dev = -{ -#ifdef CONFIG_COMP - .ad_ops = &g_compops, -#endif - .ad_priv = &g_comp5priv, -}; -#endif - -#ifdef CONFIG_STM32_COMP6 -static struct stm32_comp_s g_comp6priv = -{ - .inm = CONFIG_STM32_COMP6_INM, - .inp = CONFIG_STM32_COMP6_INP, - .pol = CONFIG_STM32_COMP6_POL, - .hyst = CONFIG_STM32_COMP6_HYST, - .blanking = CONFIG_STM32_COMP6_BLANKSEL, - .lock = CONFIG_STM32_COMP6_LOCK, - .gpio_inp = GPIO_COMP6_INP, - .csr = STM32_COMP6_CSR -}; - -static struct comp_dev_s g_comp6dev = -{ -#ifdef CONFIG_COMP - .ad_ops = &g_compops, -#endif - .ad_priv = &g_comp6priv, -}; -#endif - -#ifdef CONFIG_STM32_COMP7 -static struct stm32_comp_s g_comp7priv = -{ - .inm = CONFIG_STM32_COMP7_INM, - .inp = CONFIG_STM32_COMP7_INP, - .pol = CONFIG_STM32_COMP7_POL, - .hyst = CONFIG_STM32_COMP7_HYST, - .blanking = CONFIG_STM32_COMP7_BLANKSEL, - .lock = CONFIG_STM32_COMP7_LOCK, - .gpio_inp = GPIO_COMP7_INP, - .csr = STM32_COMP7_CSR -}; - -static struct comp_dev_s g_comp7dev = -{ -#ifdef CONFIG_COMP - .ad_ops = &g_compops, -#endif - .ad_priv = &g_comp7priv, -}; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: comp_modify_csr - * - * Description: - * Modify the value of a 32-bit COMP CSR register (not atomic). - * - * Input Parameters: - * priv - A reference to the COMP structure - * clrbits - The bits to clear - * setbits - The bits to set - * - * Returned Value: - * None - * - ****************************************************************************/ - -static inline void comp_modify_csr(struct stm32_comp_s *priv, - uint32_t clearbits, uint32_t setbits) -{ - uint32_t csr = priv->csr; - - modifyreg32(csr, clearbits, setbits); -} - -/**************************************************************************** - * Name: comp_getreg_csr - * - * Description: - * Read the value of an COMP CSR register - * - * Input Parameters: - * priv - A reference to the COMP structure - * - * Returned Value: - * The current contents of the COMP CSR register - * - ****************************************************************************/ - -static inline uint32_t comp_getreg_csr(struct stm32_comp_s *priv) -{ - uint32_t csr = priv->csr; - - return getreg32(csr); -} - -/**************************************************************************** - * Name: comp_putreg_csr - * - * Description: - * Write a value to an COMP register. - * - * Input Parameters: - * priv - A reference to the COMP structure - * value - The value to write to the COMP CSR register - * - * Returned Value: - * None - * - ****************************************************************************/ - -static inline void comp_putreg_csr(struct stm32_comp_s *priv, - uint32_t value) -{ - uint32_t csr = priv->csr; - - putreg32(value, csr); -} - -/**************************************************************************** - * Name: comp_lock_get - * - * Description: - * Get COMP lock bit state - * - * Input Parameters: - * priv - A reference to the COMP structure - * - * Returned Value: - * True if COMP locked, false if not locked - * - ****************************************************************************/ - -static bool comp_lock_get(struct stm32_comp_s *priv) -{ - uint32_t regval; - - regval = comp_getreg_csr(priv); - - return (((regval & COMP_CSR_LOCK) == 0) ? false : true); -} - -/**************************************************************************** - * Name: comp_lock_set - * - * Description: - * Lock comparator CSR register - * - * Input Parameters: - * priv - A reference to the COMP structure - * enable - lock flag - * - * Returned Value: - * 0 on success, a negated errno value on failure - * - ****************************************************************************/ - -static int comp_lock_set(struct stm32_comp_s *priv, bool lock) -{ - if (comp_lock_get(priv)) - { - if (lock == false) - { - aerr("ERROR: COMP LOCK can be cleared only by a system reset\n"); - - return -EPERM; - } - } - else - { - if (lock == true) - { - comp_modify_csr(priv, 0, COMP_CSR_LOCK); - - priv->lock = 1; - } - } - - return OK; -} - -/**************************************************************************** - * Name: comp_config_inmpin - * - * Description: - * Configure comparator inverting input pin. The GPIO that COMPx inverting - * input will be assigned is dependent of comparator number and must be - * defined in board.h file. See table 196 in RM0440. - * - * Input Parameters: - * priv - A reference to the COMP structure - * - * Returned Value: - * 0 on success, a negated errno value on failure - * - ****************************************************************************/ - -static int comp_config_inmpin(struct stm32_comp_s *priv) -{ -# if defined(CONFIG_STM32_COMP1) - if (priv->csr == STM32_COMP1_CSR) - { - stm32_configgpio(GPIO_COMP1_INM); - } -# endif - -# if defined(CONFIG_STM32_COMP2) - if (priv->csr == STM32_COMP2_CSR) - { - stm32_configgpio(GPIO_COMP2_INM); - } -# endif - -# if defined(CONFIG_STM32_COMP3) - if (priv->csr == STM32_COMP3_CSR) - { - stm32_configgpio(GPIO_COMP3_INM); - } -# endif - -# if defined(CONFIG_STM32_COMP4) - if (priv->csr == STM32_COMP4_CSR) - { - stm32_configgpio(GPIO_COMP4_INM); - } -# endif - -# if defined(CONFIG_STM32_COMP5) - if (priv->csr == STM32_COMP5_CSR) - { - stm32_configgpio(GPIO_COMP5_INM); - } -# endif - -# if defined(CONFIG_STM32_COMP6) - if (priv->csr == STM32_COMP6_CSR) - { - stm32_configgpio(GPIO_COMP6_INM); - } -# endif - -# if defined(CONFIG_STM32_COMP7) - if (priv->csr == STM32_COMP7_CSR) - { - stm32_configgpio(GPIO_COMP7_INM); - } -# endif - - return OK; -} - -/**************************************************************************** - * Name: comp_config_inppin - * - * Description: - * Configure comparator non-inverting input pin. The IO pin that COMPx - * non-inverting input will be assigned is dependent of comparator number - * and must be defined in board.h file. - * - * Input Parameters: - * priv - A reference to the COMP structure - * - * Returned Value: - * 0 on success, a negated errno value on failure - * - ****************************************************************************/ - -static int comp_config_inppin(struct stm32_comp_s *priv) -{ -# if defined(CONFIG_STM32_COMP1) - if (priv->csr == STM32_COMP1_CSR) - { - stm32_configgpio(GPIO_COMP1_INP); - } -# endif - -# if defined(CONFIG_STM32_COMP2) - if (priv->csr == STM32_COMP2_CSR) - { - stm32_configgpio(GPIO_COMP2_INP); - } -# endif - -# if defined(CONFIG_STM32_COMP3) - if (priv->csr == STM32_COMP3_CSR) - { - stm32_configgpio(GPIO_COMP3_INP); - } -# endif - -# if defined(CONFIG_STM32_COMP4) - if (priv->csr == STM32_COMP4_CSR) - { - stm32_configgpio(GPIO_COMP4_INP); - } -# endif - -# if defined(CONFIG_STM32_COMP5) - if (priv->csr == STM32_COMP5_CSR) - { - stm32_configgpio(GPIO_COMP5_INP); - } -# endif - -# if defined(CONFIG_STM32_COMP6) - if (priv->csr == STM32_COMP6_CSR) - { - stm32_configgpio(GPIO_COMP6_INP); - } -# endif - -# if defined(CONFIG_STM32_COMP7) - if (priv->csr == STM32_COMP7_CSR) - { - stm32_configgpio(GPIO_COMP7_INP); - } -# endif - - return OK; -} - -/**************************************************************************** - * Name: comp_config_outpin - * - * Description: - * Configure comparator output GPIO pin. - * - * Input Parameters: - * priv - A reference to the COMP structure - * - * Returned Value: - * 0 on success, a negated errno value on failure - * - ****************************************************************************/ - -#if defined(COMP_OUT_GPIO) -static int comp_config_outpin(struct stm32_comp_s *priv) -{ -# if defined(CONFIG_STM32_COMP1_OUT) - if (priv->csr == STM32_COMP1_CSR) - { - stm32_configgpio(GPIO_COMP1_OUT); - } -# endif - -# if defined(CONFIG_STM32_COMP2_OUT) - if (priv->csr == STM32_COMP2_CSR) - { - ainfo("\tOUT assigned to: GPIO\n"); - stm32_configgpio(GPIO_COMP2_OUT); - } -# endif - -# if defined(CONFIG_STM32_COMP3_OUT) - if (priv->csr == STM32_COMP3_CSR) - { - stm32_configgpio(GPIO_COMP3_OUT); - } -# endif - -# if defined(CONFIG_STM32_COMP4_OUT) - if (priv->csr == STM32_COMP4_CSR) - { - stm32_configgpio(GPIO_COMP4_OUT); - } -# endif - -# if defined(CONFIG_STM32_COMP5_OUT) - if (priv->csr == STM32_COMP5_CSR) - { - stm32_configgpio(GPIO_COMP5_OUT); - } -# endif - -# if defined(CONFIG_STM32_COMP6_OUT) - if (priv->csr == STM32_COMP6_CSR) - { - stm32_configgpio(GPIO_COMP6_OUT); - } -# endif - -# if defined(CONFIG_STM32_COMP7_OUT) - if (priv->csr == STM32_COMP7_CSR) - { - stm32_configgpio(GPIO_COMP7_OUT); - } -# endif - - return OK; -} -#endif /* COMP_OUT_GPIO */ - -/**************************************************************************** - * Name: comp_config - * - * Description: - * Configure comparator and used I/Os. The pin configuration and the input - * assignments are COMP index dependent. - * - * Input Parameters: - * priv - A reference to the COMP structure - * - * Returned Value: - * 0 on success, a negated errno value on failure - * - * REVISIT: Where to config comparator output pin ? - * - ****************************************************************************/ - -static int comp_config(struct stm32_comp_s *priv) -{ - uint32_t regval = 0; - uint32_t value = 0; - - /* Configure COMPx inverting input. */ - - value = priv->inm << COMP_CSR_INMSEL_SHIFT; - - switch (priv->inm) - { - case COMP_INM_1_4_VREF: - case COMP_INM_1_2_VREF: - case COMP_INM_3_4_VREF: - - value |= COMP_CSR_BRGEN; /* scaler resistor bridge enable */ - - case COMP_INM_VREF: - - value |= COMP_CSR_SCALEN; /* VREFINT scaler enable */ - break; - - case COMP_INM_DAC_1: - case COMP_INM_DAC_2: - - break; - - case COMP_INM_PIN_1: - case COMP_INM_PIN_2: - - comp_config_inmpin(priv); - break; - - default: - return -EINVAL; - } - - regval |= value; - - /* Configure COMPx non-inverting input. */ - - ainfo("\tINP assigned to GPIO%d\n", priv->inp); - - value = priv->inp << COMP_CSR_INPSEL_SHIFT; - regval |= value; - - comp_config_inppin(priv); - - /* Configure COMPx polarity */ - - if (priv->pol == COMP_POL_INVERTED) - { - value = COMP_CSR_POL; - regval |= value; - } - - /* Configure COMPx hysteresis */ - - switch (priv->hyst) - { - case COMP_HYST_DIS: - case COMP_HYST_10MV: - case COMP_HYST_20MV: - case COMP_HYST_30MV: - case COMP_HYST_40MV: - case COMP_HYST_50MV: - case COMP_HYST_60MV: - case COMP_HYST_70MV: - - value = priv->hyst << COMP_CSR_HYST_SHIFT; - regval |= value; - break; - - default: - return -EINVAL; - } - - /* Configure COMPx blanking signal source */ - - switch (priv->blanking) - { - case COMP_BLANKING_DIS: - case COMP_BLANKING_TIMX_OCY_1: - case COMP_BLANKING_TIMX_OCY_2: - case COMP_BLANKING_TIMX_OCY_3: - case COMP_BLANKING_TIMX_OCY_4: - case COMP_BLANKING_TIMX_OCY_5: - case COMP_BLANKING_TIMX_OCY_6: - case COMP_BLANKING_TIMX_OCY_7: - - value = priv->blanking << COMP_CSR_BLANKING_SHIFT; - regval |= value; - break; - - default: - return -EINVAL; - } - - /* Set Comparator output selection */ - -#if defined(COMP_OUT_GPIO) - comp_config_outpin(priv); -#endif - - /* Save CSR register */ - - comp_putreg_csr(priv, regval); - - /* Enable Comparator */ - - comp_enable(priv, true); - - /* Lock Comparator if needed */ - - if (priv->lock) - { - comp_lock_set(priv, true); - } - - return OK; -} - -/**************************************************************************** - * Name: comp_enable - * - * Description: - * Enable/disable comparator - * - * Input Parameters: - * priv - A reference to the COMP structure - * enable - enable/disable flag - * - * Returned Value: - * 0 on success, a negated errno value on failure - * - ****************************************************************************/ - -static int comp_enable(struct stm32_comp_s *priv, bool enable) -{ - bool lock; - - ainfo("enable: %d\n", enable ? 1 : 0); - - lock = comp_lock_get(priv); - - if (lock) - { - aerr("ERROR: Comparator locked!\n"); - - return -EPERM; - } - else - { - if (enable) - { - /* Enable the COMP */ - - comp_modify_csr(priv, 0, COMP_CSR_COMPEN); - } - else - { - /* Disable the COMP */ - - comp_modify_csr(priv, COMP_CSR_COMPEN, 0); - } - } - - return OK; -} - -/**************************************************************************** - * Name: comp_setup - * - * Description: - * Configure the COMP. This method is called the first time that the COMP - * device is opened. This will occur when the port is first opened. This - * setup includes configuring and attaching COMP interrupts. - * Interrupts are all disabled upon return. - * - * Input Parameters: - * - * Returned Value: - * - ****************************************************************************/ - -#ifdef CONFIG_COMP -static int comp_setup(struct comp_dev_s *dev) -{ -#warning "Missing logic" - - return OK; -} -#endif - -/**************************************************************************** - * Name: comp_shutdown - * - * Description: - * Disable the COMP. This method is called when the COMP device is closed. - * This method reverses the operation the setup method. - * Works only if COMP device is not locked. - * - * Input Parameters: - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef CONFIG_COMP -static void comp_shutdown(struct comp_dev_s *dev) -{ -# warning "Missing logic" -} -#endif - -/**************************************************************************** - * Name: comp_read - * - * Description: - * Get the COMP output state. - * - * Input Parameters: - * - * Returned Value: - * 0 if output is low (non-inverting input below inverting input), - * 1 if output is high (non inverting input above inverting input). - * - ****************************************************************************/ - -#ifdef CONFIG_COMP -static int comp_read(struct comp_dev_s *dev) -{ - struct stm32_comp_s *priv; - uint32_t regval; - - priv = dev->ad_priv; - regval = comp_getreg_csr(priv); - - return (((regval & COMP_CSR_VALUE) == 0) ? 0 : 1); -} -#endif - -/**************************************************************************** - * Name: comp_ioctl - * - * Description: - * All ioctl calls will be routed through this method. - * - * Input Parameters: - * dev - pointer to device structure used by the driver - * cmd - command - * arg - arguments passed with command - * - * Returned Value: - * Zero on success; a negated errno value on failure. - * - ****************************************************************************/ - -#ifdef CONFIG_COMP -static int comp_ioctl(struct comp_dev_s *dev, int cmd, unsigned long arg) -{ -#warning "Missing logic" - return -ENOTTY; -} -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_compinitialize - * - * Description: - * Initialize the COMP. - * - * Input Parameters: - * intf - The COMP interface number. - * - * Returned Value: - * Valid COMP device structure reference on success; a NULL on failure. - * - * Assumptions: - * 1. Clock to the COMP block has enabled, - * 2. Board-specific logic has already configured - * - ****************************************************************************/ - -struct comp_dev_s *stm32_compinitialize(int intf) -{ - struct comp_dev_s *dev; - struct stm32_comp_s *comp; - int ret; - - switch (intf) - { -#ifdef CONFIG_STM32_COMP1 - case 1: - ainfo("COMP1 selected\n"); - dev = &g_comp1dev; - break; -#endif - -#ifdef CONFIG_STM32_COMP2 - case 2: - ainfo("COMP2 selected\n"); - dev = &g_comp2dev; - break; -#endif - -#ifdef CONFIG_STM32_COMP3 - case 3: - ainfo("COMP3 selected\n"); - dev = &g_comp3dev; - break; -#endif - -#ifdef CONFIG_STM32_COMP4 - case 4: - ainfo("COMP4 selected\n"); - dev = &g_comp4dev; - break; -#endif - -#ifdef CONFIG_STM32_COMP5 - case 5: - ainfo("COMP5 selected\n"); - dev = &g_comp5dev; - break; -#endif - -#ifdef CONFIG_STM32_COMP6 - case 6: - ainfo("COMP6 selected\n"); - dev = &g_comp6dev; - break; -#endif - -#ifdef CONFIG_STM32_COMP7 - case 7: - ainfo("COMP7 selected\n"); - dev = &g_comp7dev; - break; -#endif - - default: - aerr("ERROR: No COMP interface defined\n"); - return NULL; - } - - /* Configure selected comparator */ - - comp = dev->ad_priv; - - ret = comp_config(comp); - if (ret < 0) - { - aerr("ERROR: Failed to initialize COMP%d: %d\n", intf, ret); - return NULL; - } - - return dev; -} - -#endif /* CONFIG_STM32_COMP */ diff --git a/arch/arm/src/stm32/stm32_comp_v2.h b/arch/arm/src/stm32/stm32_comp_v2.h deleted file mode 100644 index 3b748b01a9eff..0000000000000 --- a/arch/arm/src/stm32/stm32_comp_v2.h +++ /dev/null @@ -1,99 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_comp_v2.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32_STM32_COMP_V2_H -#define __ARCH_ARM_SRC_STM32_STM32_COMP_V2_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#ifdef CONFIG_STM32_COMP - -/**************************************************************************** - * Pre-processor definitions - ****************************************************************************/ - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -/* Inverting input. See Table 196 in RM0440 */ - -enum stm32_comp_inm_e -{ - COMP_INM_1_4_VREF, - COMP_INM_1_2_VREF, - COMP_INM_3_4_VREF, - COMP_INM_VREF, - COMP_INM_DAC_1, - COMP_INM_DAC_2, - COMP_INM_PIN_1, - COMP_INM_PIN_2, -}; - -/* Non-inverting input. See Table 195 in RM0440 */ - -enum stm32_comp_inp_e -{ - COMP_INP_PIN_1, - COMP_INP_PIN_2, -}; - -/* Output polarity */ - -enum stm32_comp_pol_e -{ - COMP_POL_NONINVERT, - COMP_POL_INVERTED -}; - -/* Hysteresis */ - -enum stm32_comp_hyst_e -{ - COMP_HYST_DIS, - COMP_HYST_10MV, - COMP_HYST_20MV, - COMP_HYST_30MV, - COMP_HYST_40MV, - COMP_HYST_50MV, - COMP_HYST_60MV, - COMP_HYST_70MV, -}; - -/* Blanking source */ - -enum stm32_comp_blanking_e -{ - COMP_BLANKING_DIS, - COMP_BLANKING_TIMX_OCY_1, - COMP_BLANKING_TIMX_OCY_2, - COMP_BLANKING_TIMX_OCY_3, - COMP_BLANKING_TIMX_OCY_4, - COMP_BLANKING_TIMX_OCY_5, - COMP_BLANKING_TIMX_OCY_6, - COMP_BLANKING_TIMX_OCY_7, -}; - -#endif /* CONFIG_STM32_COMP */ -#endif /* __ARCH_ARM_SRC_STM32_STM32_COMP_V2_H */ diff --git a/arch/arm/src/stm32/stm32_cordic.c b/arch/arm/src/stm32/stm32_cordic.c deleted file mode 100644 index a9ab089a7fbf4..0000000000000 --- a/arch/arm/src/stm32/stm32_cordic.c +++ /dev/null @@ -1,332 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_cordic.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include - -#include -#include - -#include "arm_internal.h" -#include "chip.h" - -#include "hardware/stm32g4xxxx_cordic.h" - -#include "stm32_cordic.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#define STM32_CORDIC_PRECISION (3) -#define STM32_CORDIC_ARGSIZE (0) /* Argument size is 32-bit */ -#define STM32_CORDIC_RESSIZE (0) /* Result size is 32-bit */ - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/* This structure represents the state of one PWM timer */ - -struct stm32_cordic_s -{ - const struct cordic_ops_s *ops; /* Lower half operations */ - uint32_t base; /* The base address of the CORDIC */ - bool inuse; /* True: driver is in-use */ -}; - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -/* Register access */ - -static uint32_t cordic_getreg(struct stm32_cordic_s *priv, int offset); -static void cordic_putreg(struct stm32_cordic_s *priv, int offset, - uint32_t value); - -/* Ops */ - -int cordic_calc(struct cordic_lowerhalf_s *lower, - struct cordic_calc_s *calc); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* STM32 specific CORDIC ops */ - -struct cordic_ops_s g_stm32_cordic_ops = -{ - .calc = cordic_calc -}; - -/* STM32 CORDIC device */ - -struct stm32_cordic_s g_stm32_cordic_dev = -{ - .ops = &g_stm32_cordic_ops, - .base = STM32_CORDIC_BASE, - .inuse = false -}; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: cordic_getreg - ****************************************************************************/ - -static uint32_t cordic_getreg(struct stm32_cordic_s *priv, int offset) -{ - return getreg32(priv->base + offset); -} - -/**************************************************************************** - * Name: cordic_putreg - ****************************************************************************/ - -static void cordic_putreg(struct stm32_cordic_s *priv, int offset, - uint32_t value) -{ - putreg32(value, priv->base + offset); -} - -/**************************************************************************** - * Name: cordic_calc - ****************************************************************************/ - -int cordic_calc(struct cordic_lowerhalf_s *lower, - struct cordic_calc_s *calc) -{ - struct stm32_cordic_s *priv = (struct stm32_cordic_s *)lower; - int ret = OK; - uint32_t csr = 0; - bool arg2_inc = false; - uint8_t scale = 0; - - DEBUGASSERT(lower); - DEBUGASSERT(calc); - - /* Configure CORDIC function */ - - switch (calc->func) - { - case CORDIC_CALC_FUNC_COS: - { - csr |= CORDIC_CSR_FUNC_COS; - arg2_inc = true; - scale = 0; - break; - } - - case CORDIC_CALC_FUNC_SIN: - { - csr |= CORDIC_CSR_FUNC_SIN; - arg2_inc = true; - scale = 0; - break; - } - - case CORDIC_CALC_FUNC_PHASE: - { - csr |= CORDIC_CSR_FUNC_PHASE; - arg2_inc = true; - scale = 0; - break; - } - - case CORDIC_CALC_FUNC_MOD: - { - csr |= CORDIC_CSR_FUNC_MOD; - arg2_inc = true; - scale = 0; - break; - } - - case CORDIC_CALC_FUNC_ARCTAN: - { - csr |= CORDIC_CSR_FUNC_ARCTAN; - arg2_inc = true; - scale = 0; - break; - } - - case CORDIC_CALC_FUNC_HCOS: - { - csr |= CORDIC_CSR_FUNC_HCOS; - arg2_inc = false; - scale = 1; - break; - } - - case CORDIC_CALC_FUNC_HSIN: - { - csr |= CORDIC_CSR_FUNC_HSIN; - arg2_inc = false; - scale = 1; - break; - } - - case CORDIC_CALC_FUNC_HARCTAN: - { - csr |= CORDIC_CSR_FUNC_HARCTAN; - arg2_inc = false; - scale = 1; - break; - } - - case CORDIC_CALC_FUNC_LN: - { - csr |= CORDIC_CSR_FUNC_LN; - arg2_inc = false; - scale = 1; - break; - } - - case CORDIC_CALC_FUNC_SQRT: - { - csr |= CORDIC_CSR_FUNC_SQRT; - arg2_inc = false; - scale = 1; - break; - } - - default: - { - ret = -EINVAL; - goto errout; - } - } - - /* Configure precision */ - - csr |= ((STM32_CORDIC_PRECISION << CORDIC_CSR_PRECISION_SHIFT) & - CORDIC_CSR_PRECISION_MASK); - - /* Configure scale */ - - csr |= ((scale << CORDIC_CSR_SCALE_SHIFT) & CORDIC_CSR_SCALE_MASK); - - /* Configure width of output data */ - - csr |= STM32_CORDIC_RESSIZE; - - /* Configure width of input data */ - - csr |= STM32_CORDIC_ARGSIZE; - - /* Include secondary argument */ - - if (arg2_inc == true) - { - csr |= CORDIC_CSR_NARGS; - } - - /* Include secondary result */ - - if (calc->res2_incl == true) - { - csr |= CORDIC_CSR_NRES; - } - - /* Write CSR */ - - cordic_putreg(priv, STM32_CORDIC_CSR_OFFSET, csr); - - /* Write arguments */ - - cordic_putreg(priv, STM32_CORDIC_WDATA_OFFSET, calc->arg1); - - if (arg2_inc == true) - { - cordic_putreg(priv, STM32_CORDIC_WDATA_OFFSET, calc->arg2); - } - - /* Read results - blocking. - * NOTE: We don't need to wait for RRDY flag as wait states are - * inserted automatically on RDATA read. - */ - - calc->res1 = cordic_getreg(priv, STM32_CORDIC_RDATA_OFFSET); - - if (calc->res2_incl == true) - { - calc->res2 = cordic_getreg(priv, STM32_CORDIC_RDATA_OFFSET); - } - else - { - calc->res2 = 0; - } - -errout: - return ret; -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_cordicinitialize - * - * Description: - * Initialize a CORDIC device. This function must be called - * from board-specific logic. - * - * Returned Value: - * On success, a pointer to the lower half CORDIC driver is returned. - * NULL is returned on any failure. - * - ****************************************************************************/ - -struct cordic_lowerhalf_s *stm32_cordicinitialize(void) -{ - struct cordic_lowerhalf_s *lower = NULL; - - if (g_stm32_cordic_dev.inuse == true) - { - _err("STM32 CORDIC device already in use\n"); - set_errno(EBUSY); - goto errout; - } - - /* Get lower-half device */ - - lower = (struct cordic_lowerhalf_s *) &g_stm32_cordic_dev; - - /* The driver is now in-use */ - - g_stm32_cordic_dev.inuse = true; - -errout: - return lower; -} diff --git a/arch/arm/src/stm32/stm32_cordic.h b/arch/arm/src/stm32/stm32_cordic.h deleted file mode 100644 index be6da8d85ef36..0000000000000 --- a/arch/arm/src/stm32/stm32_cordic.h +++ /dev/null @@ -1,57 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_cordic.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32_STM32_CORDIC_H -#define __ARCH_ARM_SRC_STM32_STM32_CORDIC_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "chip.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_cordicinitialize - * - * Description: - * Initialize a CORDIC device. This function must be called - * from board-specific logic. - * - * Returned Value: - * On success, a pointer to the lower half CORDIC driver is returned. - * NULL is returned on any failure. - * - ****************************************************************************/ - -struct cordic_lowerhalf_s *stm32_cordicinitialize(void); - -#endif /* __ARCH_ARM_SRC_STM32_STM32_CORDIC_H */ diff --git a/arch/arm/src/stm32/stm32_crypto.c b/arch/arm/src/stm32/stm32_crypto.c deleted file mode 100644 index cf4646e04ee6a..0000000000000 --- a/arch/arm/src/stm32/stm32_crypto.c +++ /dev/null @@ -1,154 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_crypto.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include - -#include -#include -#include - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -static uint32_t g_stm32_sesnum = 0; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_newsession - * - * Description: - * create new session for crypto. - * - ****************************************************************************/ - -static int stm32_newsession(uint32_t *sid, struct cryptoini *cri) -{ - if (sid == NULL || cri == NULL) - { - return -EINVAL; - } - - switch (cri->cri_alg) - { - case CRYPTO_AES_CBC: - *sid = g_stm32_sesnum++; - break; - case CRYPTO_AES_CTR: - if ((cri->cri_klen / 8 - 4) != 16) - { - /* stm32 aes-ctr key bits just support 128 */ - - return -EINVAL; - } - - *sid = g_stm32_sesnum++; - break; - default: - return -EINVAL; - } - - return OK; -} - -/**************************************************************************** - * Name: stm32_freesession - * - * Description: - * free session. - * - ****************************************************************************/ - -static int stm32_freesession(uint64_t tid) -{ - return 0; -} - -/**************************************************************************** - * Name: stm32_process - * - * Description: - * process session to use hardware algorithm. - * - ****************************************************************************/ - -static int stm32_process(struct cryptop *crp) -{ - struct cryptodesc *crd; - uint8_t iv[AESCTR_BLOCKSIZE]; - - for (crd = crp->crp_desc; crd; crd = crd->crd_next) - { - switch (crd->crd_alg) - { - case CRYPTO_AES_CBC: - return aes_cypher(crp->crp_dst, crp->crp_buf, crd->crd_len, - crd->crd_iv, crd->crd_key, 16, - AES_MODE_CBC, crd->crd_flags & CRD_F_ENCRYPT); - case CRYPTO_AES_CTR: - - memcpy(iv, crd->crd_key + crd->crd_klen / 8 - AESCTR_NONCESIZE, - AESCTR_NONCESIZE); - memcpy(iv + AESCTR_NONCESIZE, crd->crd_iv, AESCTR_IVSIZE); - memset(iv + AESCTR_NONCESIZE + AESCTR_IVSIZE , 0, 4); - - return aes_cypher(crp->crp_dst, crp->crp_buf, crd->crd_len, - iv, crd->crd_key, crd->crd_klen / 8 - 4, - AES_MODE_CTR, crd->crd_flags & CRD_F_ENCRYPT); - default: - return -EINVAL; - } - } -} - -/**************************************************************************** - * Name: hwcr_init - * - * Description: - * register the hardware crypto driver. - * - ****************************************************************************/ - -void hwcr_init(void) -{ - int hwcr_id; - int algs[CRYPTO_ALGORITHM_MAX + 1]; - - hwcr_id = crypto_get_driverid(0); - DEBUGASSERT(hwcr_id >= 0); - - memset(algs, 0, sizeof(algs)); - - algs[CRYPTO_AES_CBC] = CRYPTO_ALG_FLAG_SUPPORTED; - algs[CRYPTO_AES_CTR] = CRYPTO_ALG_FLAG_SUPPORTED; - - crypto_register(hwcr_id, algs, stm32_newsession, - stm32_freesession, stm32_process); -} diff --git a/arch/arm/src/stm32/stm32_dac.c b/arch/arm/src/stm32/stm32_dac.c deleted file mode 100644 index 873e3af543152..0000000000000 --- a/arch/arm/src/stm32/stm32_dac.c +++ /dev/null @@ -1,1797 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_dac.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -#include "arm_internal.h" -#include "chip.h" -#include "stm32.h" -#include "stm32_dac.h" -#include "stm32_rcc.h" -#include "stm32_dma.h" -#include "stm32_syscfg.h" - -#ifdef CONFIG_DAC - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* RCC reset ****************************************************************/ - -#if defined(HAVE_IP_DAC_V1) -# define STM32_RCC_RSTR STM32_RCC_APB1RSTR -# define RCC_RSTR_DAC1RST RCC_APB1RSTR_DAC1RST -# define RCC_RSTR_DAC2RST RCC_APB1RSTR_DAC2RST -#elif defined(HAVE_IP_DAC_V2) -# define STM32_RCC_RSTR STM32_RCC_AHB2RSTR -# define RCC_RSTR_DAC1RST RCC_AHB2RSTR_DAC1RST -# define RCC_RSTR_DAC2RST RCC_AHB2RSTR_DAC2RST -# define RCC_RSTR_DAC3RST RCC_AHB2RSTR_DAC3RST -# define RCC_RSTR_DAC4RST RCC_AHB2RSTR_DAC4RST -#endif - -/* Configuration ************************************************************/ - -/* Up to 2 DAC interfaces for up to 3 channels are supported - * - * NOTE: STM32_NDAC tells how many channels chip supports. - * ST is not consistent in the naming of DAC interfaces, so we - * introduce our own naming convention. We distinguish DAC1 and DAC2 - * only if the chip has two separate areas in memory map to support DAC - * channels. - */ - -#if STM32_NDAC < 3 -# warning -# undef CONFIG_STM32_DAC2CH1 -# undef CONFIG_STM32_DAC2CH1_DMA -# undef CONFIG_STM32_DAC2CH1_TIMER -# undef CONFIG_STM32_DAC2CH1_TIMER_FREQUENCY -#endif - -#if STM32_NDAC < 2 -# warning -# undef CONFIG_STM32_DAC1CH2 -# undef CONFIG_STM32_DAC1CH2_DMA -# undef CONFIG_STM32_DAC1CH2_TIMER -# undef CONFIG_STM32_DAC1CH2_TIMER_FREQUENCY -#endif - -#if STM32_NDAC < 1 -# warning -# undef CONFIG_STM32_DAC1CH1 -# undef CONFIG_STM32_DAC1CH1_DMA -# undef CONFIG_STM32_DAC1CH1_TIMER -# undef CONFIG_STM32_DAC1CH1_TIMER_FREQUENCY -#endif - -/* Sanity checking */ - -#ifdef CONFIG_STM32_DAC1 -# if !defined(CONFIG_STM32_DAC1CH1) && !defined(CONFIG_STM32_DAC1CH2) -# error "DAC1 enabled but no channel was selected" -# endif -#endif - -#ifdef CONFIG_STM32_DAC2 -# if !defined(CONFIG_STM32_DAC2CH1) -# error "DAC2 enabled but no channel was selected" -# endif -#endif - -#ifdef CONFIG_STM32_DAC3 -# if !defined(CONFIG_STM32_DAC3CH1) && !defined(CONFIG_STM32_DAC3CH2) -# error "DAC3 enabled but no channel was selected" -# endif -#endif - -#ifdef CONFIG_STM32_DAC4 -# if !defined(CONFIG_STM32_DAC4CH1) && !defined(CONFIG_STM32_DAC4CH2) -# error "DAC4 enabled but no channel was selected" -# endif -#endif - -/* DMA configuration. */ - -#if defined(CONFIG_STM32_DAC1CH1_DMA) || defined(CONFIG_STM32_DAC1CH2_DMA) || \ - defined(CONFIG_STM32_DAC2CH1_DMA) -# if defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F30XX) -# ifndef CONFIG_STM32_DMA2 -# warning "STM32 F1/F3 DAC DMA support requires CONFIG_STM32_DMA2" -# undef CONFIG_STM32_DAC1CH1_DMA -# undef CONFIG_STM32_DAC1CH2_DMA -# undef CONFIG_STM32_DAC2CH1_DMA -# endif -# elif defined(CONFIG_STM32_STM32F33XX) -# ifndef CONFIG_STM32_DMA1 -# warning "STM32 F334 DAC DMA support requires CONFIG_STM32_DMA1" -# undef CONFIG_STM32_DAC1CH1_DMA -# undef CONFIG_STM32_DAC1CH2_DMA -# undef CONFIG_STM32_DAC2CH1_DMA -# endif -# elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) -# ifndef CONFIG_STM32_DMA1 -# warning "STM32 F4 DAC DMA support requires CONFIG_STM32_DMA1" -# undef CONFIG_STM32_DAC1CH1_DMA -# undef CONFIG_STM32_DAC1CH2_DMA -# undef CONFIG_STM32_DAC2CH1_DMA -# endif -# else -# warning "No DAC DMA information for this STM32 family" -# undef CONFIG_STM32_DAC1CH1_DMA -# undef CONFIG_STM32_DAC1CH2_DMA -# undef CONFIG_STM32_DAC2CH1_DMA -# endif -#endif - -#if defined(CONFIG_STM32_DAC1CH1_HRTIM_TRG1) || defined(CONFIG_STM32_DAC1CH1_HRTIM_TRG2) -# define DAC1CH1_HRTIM -#endif -#if defined(CONFIG_STM32_DAC1CH2_HRTIM_TRG1) || defined(CONFIG_STM32_DAC1CH2_HRTIM_TRG2) -# define DAC1CH2_HRTIM -#endif -#if defined(CONFIG_STM32_DAC2CH1_HRTIM_TRG3) -# define DAC2CH1_HRTIM -#endif - -/* If DMA is selected, then a timer and output frequency must also be - * provided to support the DMA transfer. The DMA transfer could be - * supported by and EXTI trigger, but this feature is not currently - * supported by the driver. - */ - -#if defined(CONFIG_STM32_DAC1CH1_DMA) && !defined(DAC1CH1_HRTIM) && \ - !defined(CONFIG_STM32_DAC1CH1_DMA_EXTERNAL) -# if !defined(CONFIG_STM32_DAC1CH1_TIMER) -# warning "A timer number must be specified in CONFIG_STM32_DAC1CH1_TIMER" -# undef CONFIG_STM32_DAC1CH1_DMA -# undef CONFIG_STM32_DAC1CH1_TIMER_FREQUENCY -# elif !defined(CONFIG_STM32_DAC1CH1_TIMER_FREQUENCY) -# warning "A timer frequency must be specified in CONFIG_STM32_DAC1CH1_TIMER_FREQUENCY" -# undef CONFIG_STM32_DAC1CH1_DMA -# undef CONFIG_STM32_DAC1CH1_TIMER -# endif -#endif - -#if defined(CONFIG_STM32_DAC1CH2_DMA) && !defined(DAC1CH2_HRTIM) && \ - !defined(CONFIG_STM32_DAC1CH2_DMA_EXTERNAL) -# if !defined(CONFIG_STM32_DAC1CH2_TIMER) -# warning "A timer number must be specified in CONFIG_STM32_DAC1CH2_TIMER" -# undef CONFIG_STM32_DAC1CH2_DMA -# undef CONFIG_STM32_DAC1CH2_TIMER_FREQUENCY -# elif !defined(CONFIG_STM32_DAC1CH2_TIMER_FREQUENCY) -# warning "A timer frequency must be specified in CONFIG_STM32_DAC1CH2_TIMER_FREQUENCY" -# undef CONFIG_STM32_DAC1CH2_DMA -# undef CONFIG_STM32_DAC1CH2_TIMER -# endif -#endif - -#if defined(CONFIG_STM32_DAC2CH1_DMA) && !defined(DAC2CH1_HRTIM) && \ - !defined(CONFIG_STM32_DAC2CH1_DMA_EXTERNAL) -# if !defined(CONFIG_STM32_DAC2CH1_TIMER) -# warning "A timer number must be specified in CONFIG_STM32_DAC2CH1_TIMER" -# undef CONFIG_STM32_DAC2CH1_DMA -# undef CONFIG_STM32_DAC2CH1_TIMER_FREQUENCY -# elif !defined(CONFIG_STM32_DAC2CH1_TIMER_FREQUENCY) -# warning "A timer frequency must be specified in CONFIG_STM32_DAC2CH1_TIMER_FREQUENCY" -# undef CONFIG_STM32_DAC2CH1_DMA -# undef CONFIG_STM32_DAC2CH1_TIMER -# endif -#endif - -/* DMA **********************************************************************/ - -/* DMA channels and interface values differ for the F1 and F4 families */ - -#undef HAVE_DMA -#if defined(CONFIG_STM32_DAC1CH1_DMA) || defined(CONFIG_STM32_DAC1CH2_DMA) || \ - defined(CONFIG_STM32_DAC2CH1_DMA) -# if defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F30XX) || \ - defined(CONFIG_STM32_STM32F33XX) -# define HAVE_DMA 1 -# define DAC_DMA 2 -# if defined(CONFIG_STM32_DAC1CH1) && !defined(CONFIG_STM32_DAC1CH1_DMA_EXTERNAL) -# define DAC1CH1_DMA_CHAN DMACHAN_DAC1_CH1 -# endif -# if defined(CONFIG_STM32_DAC1CH2) && !defined(CONFIG_STM32_DAC1CH2_DMA_EXTERNAL) -# define DAC1CH2_DMA_CHAN DMACHAN_DAC1_CH2 -# endif -# if defined(CONFIG_STM32_DAC2CH1) && !defined(CONFIG_STM32_DAC2CH1_DMA_EXTERNAL) -# define DAC2CH1_DMA_CHAN DMACHAN_DAC2_CH1 -# endif -# elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) -# define HAVE_DMA 1 -# define DAC_DMA 1 -# if defined(CONFIG_STM32_DAC1CH1) && !defined(CONFIG_STM32_DAC1CH1_DMA_EXTERNAL) -# define DAC1CH1_DMA_CHAN DMAMAP_DAC1 -# endif -# if defined(CONFIG_STM32_DAC1CH2) && !defined(CONFIG_STM32_DAC1CH2_DMA_EXTERNAL) -# define DAC1CH2_DMA_CHAN DMAMAP_DAC1 -# endif -# if defined(CONFIG_STM32_DAC2CH1) && !defined(CONFIG_STM32_DAC2CH1_DMA_EXTERNAL) -# define DAC2CH1_DMA_CHAN DMAMAP_DAC2 -# endif -# endif -#endif - -/* Timer configuration. The STM32 supports 8 different trigger for DAC - * output: - * - * TSEL SOURCE DEVICES - * ---- ----------------------- ------------------------------------- - * 000 Timer 6 TRGO event ALL - * 001 Timer 3 TRGO event STM32 F1 Connectivity Line and STM32 F3 - * Timer 8 TRGO event Other STM32 F1 and all STM32 F4 - * 010 Timer 7 TRGO event ALL - * 011 Timer 5 TRGO event ALL - * Timer 15 TRGO event STM32 F3 - * HRTIM1_DACTRG1 event STM32F33XX (DAC1 only) - * 100 Timer 2 TRGO event ALL - * 101 Timer 4 TRGO event ALL - * HRTIM1_DACTRG2 event STM32F33XX (DAC1 only) - * HRTIM1_DACTRG3 event STM32F33XX (DAC2 only) - * 110 EXTI line9 ALL - * 111 SWTRIG Software control ALL - * - * This driver does not support the EXTI trigger. - */ - -/* DMA transfer from DMA buffer to DAC register can also be triggered by an - * external to the DAC block events. In this case, the DAC trigger (TEN bit) - * must be reset and board configuration must provide DACxCHy_DMA_CHAN. - */ - -#undef NEED_TIM6 -#undef NEED_TIM3 -#undef NEED_TIM8 -#undef NEED_TIM7 -#undef NEED_TIM5 -#undef NEED_TIM2 -#undef NEED_TIM4 - -#ifdef CONFIG_STM32_DAC1CH1_DMA -# if defined(CONFIG_STM32_DAC1CH1_DMA_EXTERNAL) -# elif defined(CONFIG_STM32_DAC1CH1_HRTIM_TRG1) -# ifndef CONFIG_STM32_HRTIM_DAC -# error "CONFIG_STM32_HRTIM_DAC required for DAC1CH1" -# endif -# define DAC1CH1_TSEL_VALUE DAC_CR_TSEL_HRT1TRG1 -# elif defined(CONFIG_STM32_DAC1CH1_HRTIM_TRG2) -# ifndef CONFIG_STM32_HRTIM_DAC -# error "CONFIG_STM32_HRTIM_DAC required for DAC1CH2" -# endif -# define DAC1CH1_TSEL_VALUE DAC_CR_TSEL_HRT1TRG2 -# elif CONFIG_STM32_DAC1CH1_TIMER == 6 -# ifndef CONFIG_STM32_TIM6_DAC -# error "CONFIG_STM32_TIM6_DAC required for DAC1CH1" -# endif -# define NEED_TIM6 -# define DAC1CH1_TSEL_VALUE DAC_CR_TSEL_TIM6 -# define DAC1CH1_TIMER_BASE STM32_TIM6_BASE -# define DAC1CH1_TIMER_PCLK_FREQUENCY STM32_PCLK1_FREQUENCY -# elif CONFIG_STM32_DAC1CH1_TIMER == 3 && defined(CONFIG_STM32_CONNECTIVITYLINE) -# ifndef CONFIG_STM32_TIM3_DAC -# error "CONFIG_STM32_TIM3_DAC required for DAC1CH1" -# endif -# define NEED_TIM3 -# define DAC1CH1_TSEL_VALUE DAC_CR_TSEL_TIM3 -# define DAC1CH1_TIMER_BASE STM32_TIM3_BASE -# define DAC1CH1_TIMER_PCLK_FREQUENCY STM32_PCLK1_FREQUENCY -# elif CONFIG_STM32_DAC1CH1_TIMER == 8 && !defined(CONFIG_STM32_CONNECTIVITYLINE) -# ifndef CONFIG_STM32_TIM8_DAC -# error "CONFIG_STM32_TIM8_DAC required for DAC1CH1" -# endif -# define NEED_TIM8 -# define DAC1CH1_TSEL_VALUE DAC_CR_TSEL_TIM8 -# define DAC1CH1_TIMER_BASE STM32_TIM8_BASE -# define DAC1CH1_TIMER_PCLK_FREQUENCY STM32_PCLK2_FREQUENCY -# elif CONFIG_STM32_DAC1CH1_TIMER == 7 -# ifndef CONFIG_STM32_TIM7_DAC -# error "CONFIG_STM32_TIM7_DAC required for DAC1CH1" -# endif -# define NEED_TIM7 -# define DAC1CH1_TSEL_VALUE DAC_CR_TSEL_TIM7 -# define DAC1CH1_TIMER_BASE STM32_TIM7_BASE -# elif CONFIG_STM32_DAC1CH1_TIMER == 5 -# ifndef CONFIG_STM32_TIM5_DAC -# error "CONFIG_STM32_TIM5_DAC required for DAC1CH1" -# endif -# define NEED_TIM5 -# define DAC1CH1_TSEL_VALUE DAC_CR_TSEL_TIM5 -# define DAC1CH1_TIMER_BASE STM32_TIM5_BASE -# define DAC1CH1_TIMER_PCLK_FREQUENCY STM32_PCLK1_FREQUENCY -# elif CONFIG_STM32_DAC1CH1_TIMER == 2 -# ifndef CONFIG_STM32_TIM2_DAC -# error "CONFIG_STM32_TIM2_DAC required for DAC1CH1" -# endif -# define NEED_TIM2 -# define DAC1CH1_TSEL_VALUE DAC_CR_TSEL_TIM2 -# define DAC1CH1_TIMER_BASE STM32_TIM2_BASE -# define DAC1CH1_TIMER_PCLK_FREQUENCY STM32_PCLK1_FREQUENCY -# elif CONFIG_STM32_DAC1CH1_TIMER == 4 -# ifndef CONFIG_STM32_TIM4_DAC -# error "CONFIG_STM32_TIM4_DAC required for DAC1CH1" -# endif -# define NEED_TIM4 -# define DAC1CH1_TSEL_VALUE DAC_CR_TSEL_TIM4 -# define DAC1CH1_TIMER_BASE STM32_TIM4_BASE -# define DAC1CH1_TIMER_PCLK_FREQUENCY STM32_PCLK1_FREQUENCY -# else -# error "Unsupported CONFIG_STM32_DAC1CH1_TIMER" -# endif -#else -# define DAC1CH1_TSEL_VALUE DAC_CR_TSEL_SW -#endif - -#if defined(NEED_TIM2) || defined(NEED_TIM3) || defined(NEED_TIM4) || \ - defined(NEED_TIM5) || defined(NEED_TIM6) || defined(NEED_TIM7) || \ - defined(NEED_TIM8) -# define HAVE_TIMER -#endif - -#ifdef CONFIG_STM32_DAC1CH2_DMA -# if defined(CONFIG_STM32_DAC1CH2_DMA_EXTERNAL) -# elif defined(CONFIG_STM32_DAC1CH2_HRTIM_TRG1) -# ifndef CONFIG_STM32_HRTIM_DAC -# error "CONFIG_STM32_HRTIM_DAC required for DAC1CH2" -# endif -# define DAC1CH2_TSEL_VALUE DAC_CR_TSEL_HRT1TRG1 -# elif defined(CONFIG_STM32_DAC1CH2_HRTIM_TRG2) -# ifndef CONFIG_STM32_HRTIM_DAC -# error "CONFIG_STM32_HRTIM_DAC required for DAC1CH2" -# endif -# define DAC1CH2_TSEL_VALUE DAC_CR_TSEL_HRT1TRG2 -# elif CONFIG_STM32_DAC1CH2_TIMER == 6 -# ifndef CONFIG_STM32_TIM6_DAC -# error "CONFIG_STM32_TIM6_DAC required for DAC1CH2" -# endif -# define DAC1CH2_TSEL_VALUE DAC_CR_TSEL_TIM6 -# define DAC1CH2_TIMER_BASE STM32_TIM6_BASE -# define DAC1CH2_TIMER_PCLK_FREQUENCY STM32_PCLK1_FREQUENCY -# elif CONFIG_STM32_DAC1CH2_TIMER == 3 && defined(CONFIG_STM32_CONNECTIVITYLINE) -# ifndef CONFIG_STM32_TIM3_DAC -# error "CONFIG_STM32_TIM3_DAC required for DAC1CH2" -# endif -# define DAC1CH2_TSEL_VALUE DAC_CR_TSEL_TIM3 -# define DAC1CH2_TIMER_BASE STM32_TIM3_BASE -# define DAC1CH2_TIMER_PCLK_FREQUENCY STM32_PCLK1_FREQUENCY -# elif CONFIG_STM32_DAC1CH2_TIMER == 8 && !defined(CONFIG_STM32_CONNECTIVITYLINE) -# ifndef CONFIG_STM32_TIM8_DAC -# error "CONFIG_STM32_TIM8_DAC required for DAC1CH2" -# endif -# define DAC1CH2_TSEL_VALUE DAC_CR_TSEL_TIM8 -# define DAC1CH2_TIMER_BASE STM32_TIM8_BASE -# define DAC1CH2_TIMER_PCLK_FREQUENCY STM32_PCLK2_FREQUENCY -# elif CONFIG_STM32_DAC1CH2_TIMER == 7 -# ifndef CONFIG_STM32_TIM7_DAC -# error "CONFIG_STM32_TIM7_DAC required for DAC1CH2" -# endif -# define DAC1CH2_TSEL_VALUE DAC_CR_TSEL_TIM7 -# define DAC1CH2_TIMER_BASE STM32_TIM7_BASE -# define DAC1CH2_TIMER_PCLK_FREQUENCY STM32_PCLK1_FREQUENCY -# elif CONFIG_STM32_DAC1CH2_TIMER == 5 -# ifndef CONFIG_STM32_TIM5_DAC -# error "CONFIG_STM32_TIM5_DAC required for DAC1CH2" -# endif -# define DAC1CH2_TSEL_VALUE DAC_CR_TSEL_TIM5 -# define DAC1CH2_TIMER_BASE STM32_TIM5_BASE -# define DAC1CH2_TIMER_PCLK_FREQUENCY STM32_PCLK1_FREQUENCY -# elif CONFIG_STM32_DAC1CH2_TIMER == 2 -# ifndef CONFIG_STM32_TIM2_DAC -# error "CONFIG_STM32_TIM2_DAC required for DAC1CH2" -# endif -# define DAC1CH2_TSEL_VALUE DAC_CR_TSEL_TIM2 -# define DAC1CH2_TIMER_BASE STM32_TIM2_BASE -# define DAC1CH2_TIMER_PCLK_FREQUENCY STM32_PCLK1_FREQUENCY -# elif CONFIG_STM32_DAC1CH2_TIMER == 4 -# ifndef CONFIG_STM32_TIM4_DAC -# error "CONFIG_STM32_TIM4_DAC required for DAC1CH2" -# endif -# define DAC1CH2_TSEL_VALUE DAC_CR_TSEL_TIM4 -# define DAC1CH2_TIMER_BASE STM32_TIM4_BASE -# define DAC1CH2_TIMER_PCLK_FREQUENCY STM32_PCLK1_FREQUENCY -# else -# error "Unsupported CONFIG_STM32_DAC1CH2_TIMER" -# endif -#else -# define DAC1CH2_TSEL_VALUE DAC_CR_TSEL_SW -#endif - -#ifdef CONFIG_STM32_DAC2CH1_DMA -# if defined(CONFIG_STM32_DAC2CH1_DMA_EXTERNAL) -# elif defined(CONFIG_STM32_DAC2CH1_HRTIM_TRG3) -# ifndef CONFIG_STM32_HRTIM_DAC -# error "CONFIG_STM32_HRTIM_DAC required for DAC2CH1" -# endif -# define DAC2CH1_TSEL_VALUE DAC_CR_TSEL_HRT1TRG3 -# elif CONFIG_STM32_DAC2CH1_TIMER == 6 -# ifndef CONFIG_STM32_TIM6_DAC -# error "CONFIG_STM32_TIM6_DAC required for DAC2CH1" -# endif -# define DAC2CH1_TSEL_VALUE DAC_CR_TSEL_TIM6 -# define DAC2CH1_TIMER_BASE STM32_TIM6_BASE -# define DAC2CH1_TIMER_PCLK_FREQUENCY STM32_PCLK1_FREQUENCY -# elif CONFIG_STM32_DAC2CH1_TIMER == 3 && defined(CONFIG_STM32_CONNECTIVITYLINE) -# ifndef CONFIG_STM32_TIM3_DAC -# error "CONFIG_STM32_TIM3_DAC required for DAC2CH1" -# endif -# define DAC2CH1_TSEL_VALUE DAC_CR_TSEL_TIM3 -# define DAC2CH1_TIMER_BASE STM32_TIM3_BASE -# define DAC2CH1_TIMER_PCLK_FREQUENCY STM32_PCLK1_FREQUENCY -# elif CONFIG_STM32_DAC2CH1_TIMER == 8 && !defined(CONFIG_STM32_CONNECTIVITYLINE) -# ifndef CONFIG_STM32_TIM8_DAC -# error "CONFIG_STM32_TIM8_DAC required for DAC2CH1" -# endif -# define DAC2CH1_TSEL_VALUE DAC_CR_TSEL_TIM8 -# define DAC2CH1_TIMER_BASE STM32_TIM8_BASE -# define DAC2CH1_TIMER_PCLK_FREQUENCY STM32_PCLK2_FREQUENCY -# elif CONFIG_STM32_DAC2CH1_TIMER == 7 -# ifndef CONFIG_STM32_TIM7_DAC -# error "CONFIG_STM32_TIM7_DAC required for DAC2CH1" -# endif -# define DAC2CH1_TSEL_VALUE DAC_CR_TSEL_TIM7 -# define DAC2CH1_TIMER_BASE STM32_TIM7_BASE -# define DAC2CH1_TIMER_PCLK_FREQUENCY STM32_PCLK1_FREQUENCY -# elif CONFIG_STM32_DAC2CH1_TIMER == 5 -# ifndef CONFIG_STM32_TIM5_DAC -# error "CONFIG_STM32_TIM5_DAC required for DAC2CH1" -# endif -# define DAC2CH1_TSEL_VALUE DAC_CR_TSEL_TIM5 -# define DAC2CH1_TIMER_BASE STM32_TIM5_BASE -# define DAC2CH1_TIMER_PCLK_FREQUENCY STM32_PCLK1_FREQUENCY -# elif CONFIG_STM32_DAC2CH1_TIMER == 2 -# ifndef CONFIG_STM32_TIM2_DAC -# error "CONFIG_STM32_TIM2_DAC required for DAC2CH1" -# endif -# define DAC2CH1_TSEL_VALUE DAC_CR_TSEL_TIM2 -# define DAC2CH1_TIMER_BASE STM32_TIM2_BASE -# define DAC2CH1_TIMER_PCLK_FREQUENCY STM32_PCLK1_FREQUENCY -# elif CONFIG_STM32_DAC2CH1_TIMER == 4 -# ifndef CONFIG_STM32_TIM4_DAC -# error "CONFIG_STM32_TIM4_DAC required for DAC2CH1" -# endif -# define DAC2CH1_TSEL_VALUE DAC_CR_TSEL_TIM4 -# define DAC2CH1_TIMER_BASE STM32_TIM4_BASE -# define DAC2CH1_TIMER_PCLK_FREQUENCY STM32_PCLK1_FREQUENCY -# else -# error "Unsupported CONFIG_STM32_DAC2CH1_TIMER" -# endif -#else -# define DAC2CH1_TSEL_VALUE DAC_CR_TSEL_SW -#endif - -/* We need index which describes when HRTIM is selected as trigger. - * It will be used to skip timer configuration where needed. - */ - -#define TIM_INDEX_HRTIM 255 - -#if defined(DAC1CH1_HRTIM) || defined(DAC1CH2_HRTIM) || defined(DAC2CH1_HRTIM) -# define HAVE_HRTIM -#endif - -/* DMA buffers default size */ - -#if !defined(CONFIG_STM32_DAC1CH1_DMA_BUFFER_SIZE) && defined(CONFIG_STM32_DAC1CH1_DMA) -# error "DAC1CH1 buffer size must be provided" -#endif -#if !defined(CONFIG_STM32_DAC1CH2_DMA_BUFFER_SIZE) && defined(CONFIG_STM32_DAC1CH2_DMA) -# error "DAC1CH2 buffer size must be provided" -#endif -#if !defined(CONFIG_STM32_DAC2CH1_DMA_BUFFER_SIZE) && defined(CONFIG_STM32_DAC2CH1_DMA) -# error "DAC2CH1 buffer size must be provided" -#endif - -/* Calculate timer divider values based upon DACn_TIMER_PCLK_FREQUENCY and - * CONFIG_STM32_DACn_TIMER_FREQUENCY. - */ - -#warning "Missing Logic" - -/* DMA stream/channel configuration */ - -#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) -# define DAC_DMA_CONTROL_WORD (DMA_SCR_MSIZE_16BITS | \ - DMA_SCR_PSIZE_16BITS | \ - DMA_SCR_MINC | \ - DMA_SCR_CIRC | \ - DMA_SCR_DIR_M2P) -#else -# define DAC_DMA_CONTROL_WORD (DMA_CCR_MSIZE_16BITS | \ - DMA_CCR_PSIZE_16BITS | \ - DMA_CCR_MINC | \ - DMA_CCR_CIRC | \ - DMA_CCR_DIR) -#endif - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/* This structure represents the internal state of the single STM32 DAC - * block - */ - -struct stm32_dac_s -{ - uint8_t init : 1; /* True, the DAC block has been initialized */ -}; - -/* This structure represents the internal state of one STM32 DAC channel */ - -struct stm32_chan_s -{ - uint8_t inuse : 1; /* True, the driver is in use and not available */ -#ifdef HAVE_DMA - uint8_t hasdma : 1; /* True, this channel supports DMA */ - uint8_t text : 1; /* True, DMA triggering from external source */ - uint8_t timer; /* Timer number 2-8 */ -#endif - uint8_t intf; /* DAC zero-based interface number (0 or 1) */ - uint32_t pin; /* Pin configuration */ -#ifdef HAVE_IP_DAC_V2 - uint32_t mode; /* DAC channel mode */ -#endif - uint32_t dro; /* Data output register */ - uint32_t cr; /* Control register */ - uint32_t tsel; /* CR trigger select value */ -#ifdef HAVE_IP_DAC_V2 - uint32_t sr; /* Status register */ - uint32_t mcr; /* Mode Control register */ -#endif -#ifdef HAVE_DMA - uint16_t dmachan; /* DMA channel needed by this DAC */ - uint16_t buffer_len; /* DMA buffer length */ - DMA_HANDLE dma; /* Allocated DMA channel */ -# ifdef HAVE_TIMER - uint32_t tbase; /* Timer base address */ - uint32_t tfrequency; /* Timer frequency */ -# endif - uint16_t *dmabuffer; /* DMA transfer buffer */ -#endif -}; - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -/* DAC Register access */ - -#ifdef HAVE_TIMER -static uint32_t tim_getreg(struct stm32_chan_s *chan, int offset); -static void tim_putreg(struct stm32_chan_s *chan, int offset, - uint32_t value); -static void tim_modifyreg(struct stm32_chan_s *chan, int offset, - uint32_t clearbits, uint32_t setbits); -#endif - -/* Interrupt handler */ - -#if 0 /* defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) */ -static int dac_interrupt(int irq, void *context, void *arg); -#endif - -/* DAC methods */ - -static void dac_reset(struct dac_dev_s *dev); -static int dac_setup(struct dac_dev_s *dev); -static void dac_shutdown(struct dac_dev_s *dev); -static void dac_txint(struct dac_dev_s *dev, bool enable); -static int dac_send(struct dac_dev_s *dev, struct dac_msg_s *msg); -static int dac_ioctl(struct dac_dev_s *dev, int cmd, unsigned long arg); - -/* Initialization */ - -#ifdef HAVE_DMA -# ifdef HAVE_TIMER -static int dac_timinit(struct stm32_chan_s *chan); -# endif -static int dma_remap(struct stm32_chan_s *chan); -static void dma_bufferinit(struct stm32_chan_s *chan, uint16_t *buffer, - uint16_t len); -#endif -static int dac_chaninit(struct stm32_chan_s *chan); -static int dac_blockinit(void); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -static const struct dac_ops_s g_dacops = -{ - .ao_reset = dac_reset, - .ao_setup = dac_setup, - .ao_shutdown = dac_shutdown, - .ao_txint = dac_txint, - .ao_send = dac_send, - .ao_ioctl = dac_ioctl, -}; - -#ifdef CONFIG_STM32_DAC1 -#ifdef CONFIG_STM32_DAC1CH1 -/* Channel 1: DAC1 channel 1 */ - -#ifdef CONFIG_STM32_DAC1CH1_DMA -uint16_t dac1ch1_buffer[CONFIG_STM32_DAC1CH1_DMA_BUFFER_SIZE]; -#endif - -static struct stm32_chan_s g_dac1ch1priv = -{ - .intf = 0, - .pin = GPIO_DAC1_OUT1, -#ifdef HAVE_IP_DAC_V2 - .mode = CONFIG_STM32_DAC1CH1_MODE; -#endif - .dro = STM32_DAC1_DHR12R1, - .cr = STM32_DAC1_CR, -#ifdef HAVE_IP_DAC_V2 - .sr = STM32_DAC1_SR, - .mcr = STM32_DAC1_MCR, -#endif -#ifdef CONFIG_STM32_DAC1CH1_DMA - .hasdma = 1, - .dmachan = DAC1CH1_DMA_CHAN, - .buffer_len = CONFIG_STM32_DAC1CH1_DMA_BUFFER_SIZE, - .dmabuffer = dac1ch1_buffer, -# ifdef CONFIG_STM32_DAC1CH1_DMA_EXTERNAL - .text = 1, -# else - .text = 0, - .tsel = DAC1CH1_TSEL_VALUE, -# ifdef DAC1CH1_HRTIM - .timer = TIM_INDEX_HRTIM, -# else - .timer = CONFIG_STM32_DAC1CH1_TIMER, - .tbase = DAC1CH1_TIMER_BASE, - .tfrequency = CONFIG_STM32_DAC1CH1_TIMER_FREQUENCY, -# endif -# endif -#endif -}; - -static struct dac_dev_s g_dac1ch1dev = -{ - .ad_ops = &g_dacops, - .ad_priv = &g_dac1ch1priv, -}; -#endif /* CONFIG_STM32_DAC1CH1 */ - -#ifdef CONFIG_STM32_DAC1CH2 -/* Channel 2: DAC1 channel 2 */ - -#ifdef CONFIG_STM32_DAC1CH2_DMA -uint16_t dac1ch2_buffer[CONFIG_STM32_DAC1CH2_DMA_BUFFER_SIZE]; -#endif - -static struct stm32_chan_s g_dac1ch2priv = -{ - .intf = 1, - .pin = GPIO_DAC1_OUT2, -#ifdef HAVE_IP_DAC_V2 - .mode = CONFIG_STM32_DAC1CH2_MODE << 16; -#endif - .dro = STM32_DAC1_DHR12R2, - .cr = STM32_DAC1_CR, -#ifdef HAVE_IP_DAC_V2 - .sr = STM32_DAC1_SR, - .mcr = STM32_DAC1_MCR, -#endif -#ifdef CONFIG_STM32_DAC1CH2_DMA - .hasdma = 1, - .dmachan = DAC1CH2_DMA_CHAN, - .buffer_len = CONFIG_STM32_DAC1CH2_DMA_BUFFER_SIZE, - .dmabuffer = dac1ch2_buffer, -# ifdef CONFIG_STM32_DAC1CH2_DMA_EXTERNAL - .text = 1, -# else - .text = 0, - .tsel = DAC1CH2_TSEL_VALUE, -# ifdef DAC1CH2_HRTIM - .timer = TIM_INDEX_HRTIM, -# else - .timer = CONFIG_STM32_DAC1CH2_TIMER, - .tbase = DAC1CH2_TIMER_BASE, - .tfrequency = CONFIG_STM32_DAC1CH2_TIMER_FREQUENCY, -# endif -# endif -#endif -}; - -static struct dac_dev_s g_dac1ch2dev = -{ - .ad_ops = &g_dacops, - .ad_priv = &g_dac1ch2priv, -}; -#endif /* CONFIG_STM32_DAC1CH2 */ - -#endif /* CONFIG_STM32_DAC1 */ - -#ifdef CONFIG_STM32_DAC2 -#ifdef CONFIG_STM32_DAC2CH1 -/* Channel 3: DAC2 channel 1 */ - -#ifdef CONFIG_STM32_DAC2CH1_DMA -uint16_t dac2ch1_buffer[CONFIG_STM32_DAC2CH1_DMA_BUFFER_SIZE]; -#endif - -static struct stm32_chan_s g_dac2ch1priv = -{ - .intf = 2, - .pin = GPIO_DAC2_OUT1, -#ifdef HAVE_IP_DAC_V2 - .mode = CONFIG_STM32_DAC2CH1_MODE; -#endif - .dro = STM32_DAC2_DHR12R1, - .cr = STM32_DAC2_CR, -#ifdef HAVE_IP_DAC_V2 - .sr = STM32_DAC2_SR, - .mcr = STM32_DAC2_MCR, -#endif -#ifdef CONFIG_STM32_DAC2CH1_DMA - .hasdma = 1, - .dmachan = DAC2CH1_DMA_CHAN, - .buffer_len = CONFIG_STM32_DAC2CH1_DMA_BUFFER_SIZE, - .dmabuffer = dac2ch1_buffer, -# ifdef CONFIG_STM32_DAC2CH1_DMA_EXTERNAL - .text = 1, -# else - .text = 0, - .tsel = DAC2CH1_TSEL_VALUE, -# ifdef DAC2CH1_HRTIM - .timer = TIM_INDEX_HRTIM, -# else - .timer = CONFIG_STM32_DAC2CH1_TIMER, - .tbase = DAC2CH1_TIMER_BASE, - .tfrequency = CONFIG_STM32_DAC2CH1_TIMER_FREQUENCY, -# endif -# endif -#endif -}; - -static struct dac_dev_s g_dac2ch1dev = -{ - .ad_ops = &g_dacops, - .ad_priv = &g_dac2ch1priv, -}; -#endif /* CONFIG_STM32_DAC2CH1 */ -#endif /* CONFIG_STM32_DAC2 */ - -#ifdef CONFIG_STM32_DAC3 -#ifdef CONFIG_STM32_DAC3CH1 -/* Channel 4: DAC3 channel 1 */ - -#ifdef CONFIG_STM32_DAC3CH1_DMA -# error "STM32_DAC3 DMA not supported" -#endif - -static struct stm32_chan_s g_dac3ch1priv = -{ - .intf = 4, - .dro = STM32_DAC3_DHR12R1, -#ifdef HAVE_IP_DAC_V2 - .mode = CONFIG_STM32_DAC3CH1_MODE; -#endif - .cr = STM32_DAC3_CR, -#ifdef HAVE_IP_DAC_V2 - .sr = STM32_DAC3_SR, - .mcr = STM32_DAC3_MCR, -#endif -}; - -static struct dac_dev_s g_dac3ch1dev = -{ - .ad_ops = &g_dacops, - .ad_priv = &g_dac3ch1priv, -}; -#endif /* CONFIG_STM32_DAC3CH1 */ - -#ifdef CONFIG_STM32_DAC3CH2 -/* Channel 5: DAC3 channel 1 */ - -#ifdef CONFIG_STM32_DAC3CH2_DMA -# error "STM32_DAC3 DMA not supported" -#endif - -static struct stm32_chan_s g_dac3ch2priv = -{ - .intf = 5, - .dro = STM32_DAC3_DHR12R2, -#ifdef HAVE_IP_DAC_V2 - .mode = CONFIG_STM32_DAC3CH2_MODE << 16, -#endif - .cr = STM32_DAC3_CR, -#ifdef HAVE_IP_DAC_V2 - .sr = STM32_DAC3_SR, - .mcr = STM32_DAC3_MCR, -#endif -}; - -static struct dac_dev_s g_dac3ch2dev = -{ - .ad_ops = &g_dacops, - .ad_priv = &g_dac3ch2priv, -}; -#endif /* CONFIG_STM32_DAC3CH2 */ -#endif /* CONFIG_STM32_DAC3 */ - -static struct stm32_dac_s g_dacblock; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_dac_modify_cr - * - * Description: - * Modify the contents of the DAC control register. - * - * Input Parameters: - * priv - Driver state instance - * clearbits - Bits in the control register to be cleared - * setbits - Bits in the control register to be set - * - * Returned Value: - * None - * - ****************************************************************************/ - -static inline void stm32_dac_modify_cr(struct stm32_chan_s *chan, - uint32_t clearbits, uint32_t setbits) -{ - unsigned int shift; - - /* DAC1 channels 1 and 2 share the STM32_DAC[1]_CR control register. DAC2 - * channel 1 (and perhaps channel 2) uses the STM32_DAC2_CR control - * register. In either case, bit 0 of the interface number provides the - * correct shift. - * - * Bit 0 = 0: Shift = 0 - * Bit 0 = 1: Shift = 16 - */ - - shift = (chan->intf & 1) << 4; - modifyreg32(chan->cr, clearbits << shift, setbits << shift); -} - -#ifdef HAVE_TIMER - -/**************************************************************************** - * Name: tim_getreg - * - * Description: - * Read the value of an DMA timer register. - * - * Input Parameters: - * chan - A reference to the DAC block status - * offset - The offset to the register to read - * - * Returned Value: - * The current contents of the specified register - * - ****************************************************************************/ - -static uint32_t tim_getreg(struct stm32_chan_s *chan, int offset) -{ - return getreg32(chan->tbase + offset); -} - -/**************************************************************************** - * Name: tim_putreg - * - * Description: - * Read the value of an DMA timer register. - * - * Input Parameters: - * chan - A reference to the DAC block status - * offset - The offset to the register to read - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void tim_putreg(struct stm32_chan_s *chan, int offset, - uint32_t value) -{ - putreg32(value, chan->tbase + offset); -} - -/**************************************************************************** - * Name: tim_modifyreg - * - * Description: - * Modify the value of an DMA timer register. - * - * Input Parameters: - * priv - Driver state instance - * offset - The timer register offset - * clearbits - Bits in the control register to be cleared - * setbits - Bits in the control register to be set - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void tim_modifyreg(struct stm32_chan_s *chan, int offset, - uint32_t clearbits, uint32_t setbits) -{ - modifyreg32(chan->tbase + offset, clearbits, setbits); -} -#endif /* HAVE_TIMER */ - -/**************************************************************************** - * Name: dac_interrupt - * - * Description: - * DAC interrupt handler. The STM32 F4 family supports a only a DAC - * underrun interrupt. - * - * Input Parameters: - * - * Returned Value: - * OK - * - ****************************************************************************/ - -#if 0 /* defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) */ -static int dac_interrupt(int irq, void *context, void *arg) -{ -#warning "Missing logic" - return OK; -} -#endif - -/**************************************************************************** - * Name: dac_reset - * - * Description: - * Reset the DAC channel. Called early to initialize the hardware. This - * is called, before dac_setup() and on error conditions. - * - * NOTE: DAC reset will reset both DAC channels! - * - * Input Parameters: - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void dac_reset(struct dac_dev_s *dev) -{ - irqstate_t flags; - - /* Reset only the selected DAC channel; the other DAC channel must remain - * functional. - */ - - flags = enter_critical_section(); - -#warning "Missing logic" - - leave_critical_section(flags); -} - -/**************************************************************************** - * Name: dac_setup - * - * Description: - * Configure the DAC. This method is called the first time that the DAC - * device is opened. This will occur when the port is first opened. - * This setup includes configuring and attaching DAC interrupts. - * Interrupts are all disabled upon return. - * - * Input Parameters: - * - * Returned Value: - * Zero on success; a negated errno value on failure. - * - ****************************************************************************/ - -static int dac_setup(struct dac_dev_s *dev) -{ -#warning "Missing logic" - return OK; -} - -/**************************************************************************** - * Name: dac_shutdown - * - * Description: - * Disable the DAC. This method is called when the DAC device is closed. - * This method reverses the operation the setup method. - * - * Input Parameters: - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void dac_shutdown(struct dac_dev_s *dev) -{ -#warning "Missing logic" -} - -/**************************************************************************** - * Name: dac_txint - * - * Description: - * Call to enable or disable TX interrupts. - * - * Input Parameters: - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void dac_txint(struct dac_dev_s *dev, bool enable) -{ -#warning "Missing logic" -} - -/**************************************************************************** - * Name: dac_dmatxcallback - * - * Description: - * DMA callback function. - * - * Input Parameters: - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef HAVE_DMA -static void dac_dmatxcallback(DMA_HANDLE handle, uint8_t isr, void *arg) -{ -} -#endif - -/**************************************************************************** - * Name: dac_send - * - * Description: - * Set the DAC output. - * - * Input Parameters: - * - * Returned Value: - * Zero on success; a negated errno value on failure. - * - ****************************************************************************/ - -static int dac_send(struct dac_dev_s *dev, struct dac_msg_s *msg) -{ - struct stm32_chan_s *chan = dev->ad_priv; - - /* Enable DAC Channel */ - -#if defined(CONFIG_STM32_STM32F33XX) - /* For STM32F33XX we have to set BOFF/OUTEN bit for DAC1CH2 and DAC2CH1 - * REVISIT: what if we connect DAC internally with comparator ? - */ - - if (chan->intf > 0) - { - stm32_dac_modify_cr(chan, 0, DAC_CR_EN | DAC_CR_BOFF); - } - else -#endif - { - stm32_dac_modify_cr(chan, 0, DAC_CR_EN); - } - -#if defined(HAVE_IP_DAC_V2) - /* Check channelx ready status bit */ - - uint32_t regval; - uint32_t dac = (chan->intf >> 1); - do - { - regval = getreg32(chan->sr); - } - while (!(regval & DAC_SR_DACRDY(dac))); -#endif - -#ifdef HAVE_DMA - if (chan->hasdma) - { - /* Configure the DMA stream/channel. - * - * - Channel number - * - Peripheral address - * - Direction: Memory to peripheral - * - Disable peripheral address increment - * - Enable memory address increment - * - Peripheral data size: half word - * - Mode: circular??? - * - Priority: ? - * - FIFO mode: disable - * - FIFO threshold: half full - * - Memory Burst: single - * - Peripheral Burst: single - */ - - stm32_dmasetup(chan->dma, chan->dro, (uint32_t)chan->dmabuffer, - chan->buffer_len, DAC_DMA_CONTROL_WORD); - - /* Enable DMA */ - - stm32_dmastart(chan->dma, dac_dmatxcallback, chan, false); - - /* Enable DMA for DAC Channel */ - - stm32_dac_modify_cr(chan, 0, DAC_CR_DMAEN); - } - else -#endif - { - /* Non-DMA transfer */ - -#if defined(HAVE_IP_DAC_V1) - putreg16(msg->am_data, chan->dro); -#else - putreg32(msg->am_data, chan->dro); -#endif - dac_txdone(dev); - } - - /* Reset counters (generate an update). Only when timer is not HRTIM */ - -#ifdef HAVE_TIMER - if (chan->timer != TIM_INDEX_HRTIM) - { - tim_modifyreg(chan, STM32_GTIM_EGR_OFFSET, 0, GTIM_EGR_UG); - } -#endif - - return OK; -} - -/**************************************************************************** - * Name: dac_ioctl - * - * Description: - * All ioctl calls will be routed through this method. - * - * Input Parameters: - * - * Returned Value: - * Zero on success; a negated errno value on failure. - * - ****************************************************************************/ - -static int dac_ioctl(struct dac_dev_s *dev, int cmd, unsigned long arg) -{ - struct stm32_chan_s *chan = dev->ad_priv; - int ret = OK; - - switch (cmd) - { -#ifdef HAVE_DMA - case IO_DMABUFFER_INIT: - { - uint16_t *buffer = (uint16_t *)arg; - - /* The caller is responsible for providing buffer with - * suitable length equal to CONFIG_STM32_DACxCHy_DMA_BUFFER_SIZE - */ - - dma_bufferinit(chan, buffer, chan->buffer_len * sizeof(buffer)); - break; - } -#endif - - default: - { - aerr("ERROR: Unknown cmd: %d\n", cmd); - ret = -ENOTTY; - break; - } - } - - UNUSED(chan); - return ret; -} - -#ifdef HAVE_DMA - -/**************************************************************************** - * Name: dma_bufferinit - ****************************************************************************/ - -static void dma_bufferinit(struct stm32_chan_s *chan, uint16_t *buffer, - uint16_t len) -{ - memcpy(chan->dmabuffer, buffer, len); -} - -/**************************************************************************** - * Name: dma_remap - ****************************************************************************/ - -static int dma_remap(struct stm32_chan_s *chan) -{ -#if defined(CONFIG_STM32_STM32F33XX) || defined(CONFIG_STM32_STM32F30XX) || \ - defined(CONFIG_STM32_STM32F37XX) - uint32_t regval = 0; - - switch (chan->intf) - { - case 0: - { - /* Remap DMA1CH3 to DAC1CH1 */ - - regval |= SYSCFG_CFGR1_DAC1CH1_DMARMP; - - /* Remap DAC trigger for STM32F33XX if needed */ - -# ifdef CONFIG_STM32_STM32F33XX -# if defined(CONFIG_STM32_DAC1CH1_HRTIM_TRG1) - modifyreg32(STM32_SYSCFG_CFGR3, 0, SYSCFG_CFGR3_DAC1_TRIG3_RMP); -# elif defined(CONFIG_STM32_DAC1CH1_HRTIM_TRG2) - modifyreg32(STM32_SYSCFG_CFGR3, 0, SYSCFG_CFGR3_DAC1_TRIG5_RMP); -# endif -# endif - break; - } - - case 1: - { - /* Remap DMA1CH4 to DAC1CH2 */ - - regval |= SYSCFG_CFGR1_DAC1CH2_DMARMP; - - /* Remap DAC trigger for STM32F33XX if needed */ - -# ifdef CONFIG_STM32_STM32F33XX -# if defined(CONFIG_STM32_DAC1CH2_HRTIM_TRG1) - modifyreg32(STM32_SYSCFG_CFGR3, 0, SYSCFG_CFGR3_DAC1_TRIG3_RMP); -# elif defined(CONFIG_STM32_DAC1CH2_HRTIM_TRG2) - modifyreg32(STM32_SYSCFG_CFGR3, 0, SYSCFG_CFGR3_DAC1_TRIG5_RMP); -# endif -# endif - break; - } - - case 2: - { - /* Remap DMA1CH5 to DAC2CH1 */ - - regval |= SYSCFG_CFGR1_DAC2CH1_DMARMP; - break; - } - - default: - { - return -EINVAL; - } - } - - modifyreg32(STM32_SYSCFG_BASE, 0, regval); - -#endif - - return OK; -} - -/**************************************************************************** - * Name: dac_timinit - * - * Description: - * Initialize the timer that drivers the DAC DMA for this channel using - * the pre-calculated timer divider definitions. - * - * Input Parameters: - * chan - A reference to the DAC channel state data - * - * Returned Value: - * Zero on success; a negated errno value on failure. - * - ****************************************************************************/ - -#ifdef HAVE_TIMER -static int dac_timinit(struct stm32_chan_s *chan) -{ - uint32_t pclk; - uint32_t prescaler; - uint32_t timclk; - uint32_t reload; - uint32_t regaddr; - uint32_t setbits; - - /* Configure the time base: Timer period, prescaler, clock division, - * counter mode (up). - */ - - /* Enable the timer. At most, two of the following cases (pulse the - * default) will be enabled - */ - - regaddr = STM32_RCC_APB1ENR; - - switch (chan->timer) - { -#ifdef NEED_TIM2 - case 2: - setbits = RCC_APB1ENR_TIM2EN; - pclk = BOARD_TIM2_FREQUENCY; - break; -#endif -#ifdef NEED_TIM3 - case 3: - setbits = RCC_APB1ENR_TIM3EN; - pclk = BOARD_TIM3_FREQUENCY; - break; -#endif -#ifdef NEED_TIM4 - case 4: - setbits = RCC_APB1ENR_TIM4EN; - pclk = BOARD_TIM4_FREQUENCY; - break; -#endif -#ifdef NEED_TIM5 - case 5: - setbits = RCC_APB1ENR_TIM5EN; - pclk = BOARD_TIM5_FREQUENCY; - break; -#endif -#ifdef NEED_TIM6 - case 6: - setbits = RCC_APB1ENR_TIM6EN; - pclk = BOARD_TIM6_FREQUENCY; - break; -#endif -#ifdef NEED_TIM7 - case 7: - setbits = RCC_APB1ENR_TIM7EN; - pclk = BOARD_TIM7_FREQUENCY; - break; -#endif -#ifdef NEED_TIM8 - case 8: - regaddr = STM32_RCC_APB2ENR; - setbits = RCC_APB2ENR_TIM8EN; - pclk = BOARD_TIM8_FREQUENCY; - break; -#endif - default: - aerr("ERROR: Could not enable timer\n"); - return -EINVAL; - } - - /* Enable the timer. */ - - modifyreg32(regaddr, 0, setbits); - - /* Calculate optimal values for the timer prescaler and for the timer - * reload register. If 'frequency' is the desired frequency, then - * - * reload = timclk / frequency - * timclk = pclk / presc - * - * Or, - * - * reload = pclk / presc / frequency - * - * There are many solutions to this, but the best solution will be the one - * that has the largest reload value and the smallest prescaler value. - * That is the solution that should give us the most accuracy in the timer - * control. Subject to: - * - * 0 <= presc <= 65536 - * 1 <= reload <= 65535 - * - * So presc = pclk / 65535 / frequency would be optimal. - * - * Example: - * - * pclk = 42 MHz - * frequency = 100 Hz - * - * prescaler = 42,000,000 / 65,535 / 100 - * = 6.4 (or 7 -- taking the ceiling always) - * timclk = 42,000,000 / 7 - * = 6,000,000 - * reload = 6,000,000 / 100 - * = 60,000 - */ - - prescaler = (pclk / chan->tfrequency + 65534) / 65535; - if (prescaler < 1) - { - prescaler = 1; - } - else if (prescaler > 65536) - { - prescaler = 65536; - } - - timclk = pclk / prescaler; - - reload = timclk / chan->tfrequency; - if (reload < 1) - { - reload = 1; - } - else if (reload > 65535) - { - reload = 65535; - } - - /* Set the reload and prescaler values */ - - tim_putreg(chan, STM32_GTIM_ARR_OFFSET, (uint16_t)reload); - tim_putreg(chan, STM32_GTIM_PSC_OFFSET, (uint16_t)(prescaler - 1)); - - /* Count mode up, auto reload */ - - tim_modifyreg(chan, STM32_GTIM_CR1_OFFSET, 0, GTIM_CR1_ARPE); - - /* Selection TRGO selection: update */ - - tim_modifyreg(chan, STM32_GTIM_CR2_OFFSET, GTIM_CR2_MMS_MASK, - GTIM_CR2_MMS_UPDATE); - - /* Update DMA request enable ???? */ -#if 0 - tim_modifyreg(chan, STM32_GTIM_DIER_OFFSET, 0, GTIM_DIER_UDE); -#endif - - /* Enable the counter */ - - tim_modifyreg(chan, STM32_GTIM_CR1_OFFSET, 0, GTIM_CR1_CEN); - return OK; -} -#endif -#endif /* HAVE_DMA */ - -/**************************************************************************** - * Name: dac_chaninit - * - * Description: - * Initialize the DAC channel. - * - * Input Parameters: - * chan - A reference to the DAC channel state data - * - * Returned Value: - * Zero on success; a negated errno value on failure. - * - ****************************************************************************/ - -static int dac_chaninit(struct stm32_chan_s *chan) -{ - uint16_t clearbits; - uint16_t setbits; -#if defined(HAVE_IP_DAC_V2) - uint32_t regval; -#endif -#ifdef HAVE_TIMER - int ret; -#endif - - /* Is the selected channel already in-use? */ - - if (chan->inuse) - { - /* Yes.. then return EBUSY */ - - return -EBUSY; - } - - /* Configure the DAC output pin: - * - * DAC -" Once the DAC channelx is enabled, the corresponding GPIO pin - * (PA4 or PA5) is automatically connected to the analog converter output - * (DAC_OUTx). In order to avoid parasitic consumption, the PA4 or PA5 pin - * should first be configured to analog (AIN)". - */ - - /* Only DAC1 and DAC2 have external pins */ - - if (chan->intf < 4) - { - stm32_configgpio(chan->pin); - } - - /* DAC channel configuration: - * - * - Set the trigger selection based upon the configuration. - * - Set wave generation == None. - * - Enable the output buffer. - */ - - /* Disable before change */ - - stm32_dac_modify_cr(chan, DAC_CR_EN, 0); - - clearbits = DAC_CR_TSEL_MASK | - DAC_CR_MAMP_MASK | - DAC_CR_WAVE_MASK; -#if defined (HAVE_IP_DAC_V1) - clearbits |= DAC_CR_BOFF; -#endif - - setbits = - chan->tsel | /* Set trigger source (SW or timer TRGO event) */ - DAC_CR_MAMP_AMP1 | /* Set waveform characteristics */ - DAC_CR_WAVE_DISABLED; /* Set wave generation disabled */ -#if defined (HAVE_IP_DAC_V1) - setbits |= DAC_CR_BOFF_EN; /* Enable output buffer */ -#endif - - stm32_dac_modify_cr(chan, clearbits, setbits); - -#if defined(HAVE_IP_DAC_V2) - /* High frequency interface mode selection */ - - if (STM32_SYSCLK_FREQUENCY > 160000000) - { - regval = DAC_MCR_HFSEL_AHB_160MHz; - } - else if (STM32_SYSCLK_FREQUENCY > 80000000) - { - regval = DAC_MCR_HFSEL_AHB_80MHz; - } - else - { - regval = DAC_MCR_HFSEL_DISABLED; - } - - /* DAC mode selection */ - - regval |= chan->mode; - - putreg32(regval, chan->mcr); -#endif - -#ifdef HAVE_DMA - /* Determine if DMA is supported by this channel */ - - if (chan->hasdma) - { - /* Remap DMA request if necessary */ - - dma_remap(chan); - - /* DAC trigger enable if not external triggering */ - - if (!chan->text) - { - stm32_dac_modify_cr(chan, 0, DAC_CR_TEN); - } - - /* Allocate a DMA channel */ - - chan->dma = stm32_dmachannel(chan->dmachan); - if (!chan->dma) - { - aerr("ERROR: Failed to allocate a DMA channel\n"); - return -EBUSY; - } - - /* Configure the timer that supports the DMA operation - * Do nothing if HRTIM is selected as trigger. - * All necessary configuration is done in the HRTIM driver. - */ - -#ifdef HAVE_TIMER - if (chan->timer != TIM_INDEX_HRTIM) - { - ret = dac_timinit(chan); - if (ret < 0) - { - aerr("ERROR: Failed to initialize the DMA timer: %d\n", ret); - return ret; - } - } -#endif - } -#endif - - /* Mark the DAC channel "in-use" */ - - chan->inuse = 1; - return OK; -} - -/**************************************************************************** - * Name: dac_blockinit - * - * Description: - * Initialize the DAC block. - * - * Input Parameters: - * - * Returned Value: - * Zero on success; a negated errno value on failure. - * - ****************************************************************************/ - -static int dac_blockinit(void) -{ - irqstate_t flags; - uint32_t regval; - - /* Has the DAC block already been initialized? */ - - if (g_dacblock.init) - { - /* Yes.. then return success We only have to do this once */ - - return OK; - } - - /* Put the entire DAC block in reset state */ - - flags = enter_critical_section(); - regval = getreg32(STM32_RCC_RSTR); -#ifdef CONFIG_STM32_DAC1 - regval |= RCC_RSTR_DAC1RST; -#endif -#ifdef CONFIG_STM32_DAC2 - regval |= RCC_RSTR_DAC2RST; -#endif -#ifdef CONFIG_STM32_DAC3 - regval |= RCC_RSTR_DAC3RST; -#endif - putreg32(regval, STM32_RCC_RSTR); - - /* Take the DAC out of reset state */ - -#ifdef CONFIG_STM32_DAC1 - regval &= ~RCC_RSTR_DAC1RST; -#endif -#ifdef CONFIG_STM32_DAC2 - regval &= ~RCC_RSTR_DAC2RST; -#endif -#ifdef CONFIG_STM32_DAC3 - regval &= ~RCC_RSTR_DAC3RST; -#endif - putreg32(regval, STM32_RCC_RSTR); - leave_critical_section(flags); - - /* Mark the DAC block as initialized */ - - g_dacblock.init = 1; - return OK; -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_dacinitialize - * - * Description: - * Initialize the DAC. - * - * Input Parameters: - * intf - The DAC interface number. - * - * Returned Value: - * Valid DAC device structure reference on success; a NULL on failure. - * - * Assumptions: - * 1. Clock to the DAC block has enabled, - * 2. Board-specific logic has already configured - * - ****************************************************************************/ - -struct dac_dev_s *stm32_dacinitialize(int intf) -{ - struct dac_dev_s *dev; - struct stm32_chan_s *chan; - int ret; - -#ifdef CONFIG_STM32_DAC1CH1 - if (intf == 1) - { - ainfo("DAC1-1 Selected\n"); - dev = &g_dac1ch1dev; - } - else -#endif /* CONFIG_STM32_DAC1CH1 */ -#ifdef CONFIG_STM32_DAC1CH2 - if (intf == 2) - { - ainfo("DAC1-2 Selected\n"); - dev = &g_dac1ch2dev; - } - else -#endif /* CONFIG_STM32_DAC1CH2 */ -#ifdef CONFIG_STM32_DAC2CH1 - if (intf == 3) - { - ainfo("DAC2-1 Selected\n"); - dev = &g_dac2ch1dev; - } - else -#endif /* CONFIG_STM32_DAC2CH1 */ -#ifdef CONFIG_STM32_DAC3CH1 - if (intf == 4) - { - ainfo("DAC3-1 Selected\n"); - dev = &g_dac3ch1dev; - } - else -#endif /* CONFIG_STM32_DAC3CH1 */ -#ifdef CONFIG_STM32_DAC3CH2 - if (intf == 5) - { - ainfo("DAC3-2 Selected\n"); - dev = &g_dac3ch2dev; - } - else -#endif /* CONFIG_STM32_DAC3CH2 */ - { - aerr("ERROR: No such DAC interface: %d\n", intf); - return NULL; - } - - /* Make sure that the DAC block has been initialized */ - - ret = dac_blockinit(); - if (ret < 0) - { - aerr("ERROR: Failed to initialize the DAC block: %d\n", ret); - return NULL; - } - - /* Configure the selected DAC channel */ - - chan = dev->ad_priv; - ret = dac_chaninit(chan); - if (ret < 0) - { - aerr("ERROR: Failed to initialize DAC channel %d: %d\n", intf, ret); - return NULL; - } - - return dev; -} - -#endif /* CONFIG_DAC */ diff --git a/arch/arm/src/stm32/stm32_dac.h b/arch/arm/src/stm32/stm32_dac.h deleted file mode 100644 index b031fa463d8ee..0000000000000 --- a/arch/arm/src/stm32/stm32_dac.h +++ /dev/null @@ -1,139 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_dac.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32_STM32_DAC_H -#define __ARCH_ARM_SRC_STM32_STM32_DAC_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "chip.h" -#include "hardware/stm32_dac.h" - -#include - -/**************************************************************************** - * Pre-processor definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -/* Timer devices may be used for different purposes. One special purpose is - * to control periodic DAC outputs. If CONFIG_STM32_TIMn is defined then - * CONFIG_STM32_TIMn_DAC must also be defined to indicate that timer "n" is - * intended to be used for that purpose. - */ - -#ifndef CONFIG_STM32_TIM1 -# undef CONFIG_STM32_TIM1_DAC -#endif -#ifndef CONFIG_STM32_TIM2 -# undef CONFIG_STM32_TIM2_DAC -#endif -#ifndef CONFIG_STM32_TIM3 -# undef CONFIG_STM32_TIM3_DAC -#endif -#ifndef CONFIG_STM32_TIM4 -# undef CONFIG_STM32_TIM4_DAC -#endif -#ifndef CONFIG_STM32_TIM5 -# undef CONFIG_STM32_TIM5_DAC -#endif -#ifndef CONFIG_STM32_TIM6 -# undef CONFIG_STM32_TIM6_DAC -#endif -#ifndef CONFIG_STM32_TIM7 -# undef CONFIG_STM32_TIM7_DAC -#endif -#ifndef CONFIG_STM32_TIM8 -# undef CONFIG_STM32_TIM8_DAC -#endif -#ifndef CONFIG_STM32_TIM9 -# undef CONFIG_STM32_TIM9_DAC -#endif -#ifndef CONFIG_STM32_TIM10 -# undef CONFIG_STM32_TIM10_DAC -#endif -#ifndef CONFIG_STM32_TIM11 -# undef CONFIG_STM32_TIM11_DAC -#endif -#ifndef CONFIG_STM32_TIM12 -# undef CONFIG_STM32_TIM12_DAC -#endif -#ifndef CONFIG_STM32_TIM13 -# undef CONFIG_STM32_TIM13_DAC -#endif -#ifndef CONFIG_STM32_TIM14 -# undef CONFIG_STM32_TIM14_DAC -#endif - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -/* IOCTL commands specific to this driver */ - -enum dac_io_cmds -{ - IO_DMABUFFER_INIT = 0, -}; - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -#ifndef __ASSEMBLY__ -#ifdef __cplusplus -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Name: stm32_dacinitialize - * - * Description: - * Initialize the DAC - * - * Input Parameters: - * intf - The DAC interface number. - * - * Returned Value: - * Valid DAC device structure reference on success; a NULL on failure - * - ****************************************************************************/ - -struct dac_dev_s; -struct dac_dev_s *stm32_dacinitialize(int intf); - -#undef EXTERN -#ifdef __cplusplus -} -#endif -#endif /* __ASSEMBLY__ */ - -#endif /* __ARCH_ARM_SRC_STM32_STM32_DAC_H */ diff --git a/arch/arm/src/stm32/stm32_dbgmcu.h b/arch/arm/src/stm32/stm32_dbgmcu.h deleted file mode 100644 index 1695141ff16b0..0000000000000 --- a/arch/arm/src/stm32/stm32_dbgmcu.h +++ /dev/null @@ -1,51 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_dbgmcu.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32_STM32_DBGMCU_H -#define __ARCH_ARM_SRC_STM32_STM32_DBGMCU_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "chip.h" -#include "hardware/stm32_dbgmcu.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -#endif /* __ARCH_ARM_SRC_STM32_STM32_DBGMCU_H */ diff --git a/arch/arm/src/stm32/stm32_dfumode.c b/arch/arm/src/stm32/stm32_dfumode.c deleted file mode 100644 index 45b8b0e9cd4cd..0000000000000 --- a/arch/arm/src/stm32/stm32_dfumode.c +++ /dev/null @@ -1,80 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_dfumode.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include - -#include "stm32_dfumode.h" - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_dfumode - * - * Description: - * Reboot the part in DFU mode (GCC only). - * - * https://community.st.com/s/question/ - * 0D50X00009XkhAzSAJ/calling-stm32429ieval-bootloader - * - * REVISIT: STM32_SYSMEM_BASE is not 0x1fff000 for all STM32's. For F3's - * The SYSMEM base is at 0x1fffd800 - * - * REVISIT: RCC_APB2ENR_SYSCFGEN is not bit 14 for all STM32's. For F3's - * and L15's, it is bit 0. - * - * REVISIT: STM32 F3's do not support the SYSCFG_MEMRMP register. - * - ****************************************************************************/ - -#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) -void stm32_dfumode(void) -{ -#ifdef CONFIG_DEBUG_WARN - _warn("Entering DFU mode...\n"); - nxsched_sleep(1); -#endif - - asm("ldr r0, =0x40023844\n\t" /* RCC_APB2ENR */ - "ldr r1, =0x00004000\n\t" /* Enable SYSCFG clock */ - "str r1, [r0, #0]\n\t" - "ldr r0, =0x40013800\n\t" /* SYSCFG_MEMRMP */ - "ldr r1, =0x00000001\n\t" /* Map ROM at zero */ - "str r1, [r0, #0]\n\t" - "ldr r0, =0x1fff0000\n\t" /* ROM base */ - "ldr sp,[r0, #0]\n\t" /* SP @ 0 */ - "ldr r0,[r0, #4]\n\t" /* PC @ 4 */ - "bx r0\n"); - - __builtin_unreachable(); /* Tell compiler we will not return */ -} -#endif /* CONFIG_STM32_STM32F20XX || CONFIG_STM32_STM32F4XXX */ diff --git a/arch/arm/src/stm32/stm32_dfumode.h b/arch/arm/src/stm32/stm32_dfumode.h deleted file mode 100644 index 332ef05c0974b..0000000000000 --- a/arch/arm/src/stm32/stm32_dfumode.h +++ /dev/null @@ -1,51 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_dfumode.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32_STM32_DFUMODE_H -#define __ARCH_ARM_SRC_STM32_STM32_DFUMODE_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_dfumode - * - * Description: - * Reboot the part in DFU mode. - * - * https://community.st.com/s/question/0D50X00009XkhAzSAJ/ - * calling-stm32429ieval-bootloader - * - ****************************************************************************/ - -#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) -void stm32_dfumode(void) noreturn_function; -#endif - -#endif /* __ARCH_ARM_SRC_STM32_STM32_DFUMODE_H */ diff --git a/arch/arm/src/stm32/stm32_dma.c b/arch/arm/src/stm32/stm32_dma.c deleted file mode 100644 index f5d1f1047a89b..0000000000000 --- a/arch/arm/src/stm32/stm32_dma.c +++ /dev/null @@ -1,53 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_dma.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "chip.h" - -/* This file is only a thin shell that includes the correct DMA - * implementation for the selected STM32 IP core: - * - STM32 DMA IP version 1 - F0, F1, F3, G4, L0, L1, L4 - * - STM32 DMA IP version 2 - F2, F4, F7, H7 - * - * The STM32 DMA IPv2 differs from the STM32 DMA IPv1 primarily in that it - * adds the concept of "streams" that are used to associate DMA sources with - * DMA channels. - */ - -#if defined(CONFIG_STM32_HAVE_IP_DMA_V1) -# if defined(CONFIG_STM32_HAVE_DMAMUX) -# include "stm32_dma_v1mux.c" -# else -# include "stm32_dma_v1.c" -# endif -#elif defined(CONFIG_STM32_HAVE_IP_DMA_V2) -# include "stm32_dma_v2.c" -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ diff --git a/arch/arm/src/stm32/stm32_dma.h b/arch/arm/src/stm32/stm32_dma.h deleted file mode 100644 index f7eb641ef8623..0000000000000 --- a/arch/arm/src/stm32/stm32_dma.h +++ /dev/null @@ -1,352 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_dma.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32_STM32_DMA_H -#define __ARCH_ARM_SRC_STM32_STM32_DMA_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include - -#include "chip.h" - -#include "hardware/stm32_dma.h" - -#ifdef CONFIG_STM32_HAVE_DMAMUX -# include "hardware/stm32_dmamux.h" -#endif - -/* These definitions provide the bit encoding of the 'status' parameter - * passed to the DMA callback function (see dma_callback_t). - */ - -#if defined(HAVE_IP_DMA_V1) -# define DMA_STATUS_FEIF 0 /* (Not available in F1) */ -# define DMA_STATUS_DMEIF 0 /* (Not available in F1) */ -# define DMA_STATUS_TEIF DMA_CHAN_TEIF_BIT /* Channel Transfer Error */ -# define DMA_STATUS_HTIF DMA_CHAN_HTIF_BIT /* Channel Half Transfer */ -# define DMA_STATUS_TCIF DMA_CHAN_TCIF_BIT /* Channel Transfer Complete */ -#elif defined(HAVE_IP_DMA_V2) -# define DMA_STATUS_FEIF 0 /* Stream FIFO error (ignored) */ -# define DMA_STATUS_DMEIF DMA_STREAM_DMEIF_BIT /* Stream direct mode error */ -# define DMA_STATUS_TEIF DMA_STREAM_TEIF_BIT /* Stream Transfer Error */ -# define DMA_STATUS_HTIF DMA_STREAM_HTIF_BIT /* Stream Half Transfer */ -# define DMA_STATUS_TCIF DMA_STREAM_TCIF_BIT /* Stream Transfer Complete */ -#endif - -#define DMA_STATUS_ERROR (DMA_STATUS_FEIF | DMA_STATUS_DMEIF | DMA_STATUS_TEIF) -#define DMA_STATUS_SUCCESS (DMA_STATUS_TCIF | DMA_STATUS_HTIF) - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -/* DMA_HANDLE provides an opaque reference that can be used to represent a - * DMA channel (F1) or a DMA stream (F4). - */ - -typedef void *DMA_HANDLE; - -/* Description: - * This is the type of the callback that is used to inform the user of the - * completion of the DMA. - * - * Input Parameters: - * handle - Refers to the DMA channel or stream - * status - A bit encoded value that provides the completion status. See - * the DMASTATUS_* definitions above. - * arg - A user-provided value that was provided when stm32_dmastart() - * was called. - */ - -typedef void (*dma_callback_t)(DMA_HANDLE handle, uint8_t status, void *arg); - -#ifdef CONFIG_DEBUG_DMA_INFO - -#if defined(HAVE_IP_DMA_V1) -struct stm32_dmaregs_s -{ - uint32_t isr; - uint32_t ccr; - uint32_t cndtr; - uint32_t cpar; - uint32_t cmar; -}; -#elif defined(HAVE_IP_DMA_V2) -struct stm32_dmaregs_s -{ - uint32_t lisr; - uint32_t hisr; - uint32_t scr; - uint32_t sndtr; - uint32_t spar; - uint32_t sm0ar; - uint32_t sm1ar; - uint32_t sfcr; -}; -#else -# error "Unknown STM32 DMA" -#endif -#endif - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -#ifndef __ASSEMBLY__ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_dmachannel - * - * Description: - * Allocate a DMA channel. This function gives the caller mutually - * exclusive access to the DMA channel specified by the 'chan' argument. - * DMA channels are shared on the STM32: Devices sharing the same DMA - * channel cannot do DMA concurrently! See the DMACHAN_* definitions in - * stm32_dma.h. - * - * If the DMA channel is not available, then stm32_dmachannel() will wait - * until the holder of the channel relinquishes the channel by calling - * stm32_dmafree(). WARNING: If you have two devices sharing a DMA - * channel and the code never releases the channel, the stm32_dmachannel - * call for the other will hang forever in this function! Don't let your - * design do that! - * - * Hmm.. I suppose this interface could be extended to make a non-blocking - * version. Feel free to do that if that is what you need. - * - * Input Parameters: - * chan - Identifies the stream/channel resource - * For the STM32 F1, this is simply the channel number as provided by - * the DMACHAN_* definitions in chip/stm32f10xxx_dma.h. - * For the STM32 F4, this is a bit encoded value as provided by the - * the DMAMAP_* definitions in chip/stm32f40xxx_dma.h - * - * Returned Value: - * Provided that 'chan' is valid, this function ALWAYS returns a non-NULL, - * void* DMA channel handle. (If 'chan' is invalid, the function will - * assert if debug is enabled or do something ignorant otherwise). - * - * Assumptions: - * - The caller does not hold he DMA channel. - * - The caller can wait for the DMA channel to be freed if it is no - * available. - * - ****************************************************************************/ - -DMA_HANDLE stm32_dmachannel(unsigned int chan); - -/**************************************************************************** - * Name: stm32_dmafree - * - * Description: - * Release a DMA channel. If another thread is waiting for this DMA - * channel in a call to stm32_dmachannel, then this function will re- - * assign the DMA channel to that thread and wake it up. - * - * NOTE: The 'handle' used in this argument must NEVER be used again - * until stm32_dmachannel() is called again to re-gain access to the - * channel. - * - * Returned Value: - * None - * - * Assumptions: - * - The caller holds the DMA channel. - * - There is no DMA in progress - * - ****************************************************************************/ - -void stm32_dmafree(DMA_HANDLE handle); - -/**************************************************************************** - * Name: stm32_dmasetup - * - * Description: - * Configure DMA before using - * - ****************************************************************************/ - -void stm32_dmasetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr, - size_t ntransfers, uint32_t ccr); - -/**************************************************************************** - * Name: stm32_dmastart - * - * Description: - * Start the DMA transfer - * - * Assumptions: - * - DMA handle allocated by stm32_dmachannel() - * - No DMA in progress - * - ****************************************************************************/ - -void stm32_dmastart(DMA_HANDLE handle, dma_callback_t callback, void *arg, - bool half); - -/**************************************************************************** - * Name: stm32_dmastop - * - * Description: - * Cancel the DMA. After stm32_dmastop() is called, the DMA channel is - * reset and stm32_dmasetup() must be called before stm32_dmastart() can be - * called again - * - * Assumptions: - * - DMA handle allocated by stm32_dmachannel() - * - ****************************************************************************/ - -void stm32_dmastop(DMA_HANDLE handle); - -/**************************************************************************** - * Name: stm32_dmaresidual - * - * Description: - * Returns the number of bytes remaining to be transferred - * - * Assumptions: - * - DMA handle allocated by stm32_dmachannel() - * - ****************************************************************************/ - -size_t stm32_dmaresidual(DMA_HANDLE handle); - -/**************************************************************************** - * Name: stm32_dmacapable - * - * Description: - * Check if the DMA controller can transfer data to/from given memory - * address with the given configuration. This depends on the internal - * connections in the ARM bus matrix of the processor. Note that this only - * applies to memory addresses, it will return false for any peripheral - * address. - * - * Returned Value: - * True, if transfer is possible. - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_DMACAPABLE -bool stm32_dmacapable(uintptr_t maddr, uint32_t count, uint32_t ccr); -#else -# define stm32_dmacapable(maddr, count, ccr) (true) -#endif - -/**************************************************************************** - * Name: stm32_dmasample - * - * Description: - * Sample DMA register contents - * - * Assumptions: - * - DMA handle allocated by stm32_dmachannel() - * - ****************************************************************************/ - -#ifdef CONFIG_DEBUG_DMA_INFO -void stm32_dmasample(DMA_HANDLE handle, struct stm32_dmaregs_s *regs); -#else -# define stm32_dmasample(handle,regs) -#endif - -/**************************************************************************** - * Name: stm32_dmadump - * - * Description: - * Dump previously sampled DMA register contents - * - * Assumptions: - * - DMA handle allocated by stm32_dmachannel() - * - ****************************************************************************/ - -#ifdef CONFIG_DEBUG_DMA_INFO -void stm32_dmadump(DMA_HANDLE handle, const struct stm32_dmaregs_s *regs, - const char *msg); -#else -# define stm32_dmadump(handle,regs,msg) -#endif - -/* High performance, zero latency DMA interrupts need some additional - * interfaces. - * - * TODO: For now the interface is different for STM32 DMAv1 and STM32 DMAv2. - * It should be unified somehow. - */ - -#ifdef CONFIG_ARCH_HIPRI_INTERRUPT - -/**************************************************************************** - * Name: stm32_dma_intack - * - * Description: - * Public visible interface to acknowledge interrupts on DMA channel - * - ****************************************************************************/ - -#if defined(HAVE_IP_DMA_V1) -void stm32_dma_intack(unsigned int chndx, uint32_t isr); -#elif defined(HAVE_IP_DMA_V2) -void stm32_dma_intack(unsigned int controller, uint8_t stream, uint32_t isr); -#endif - -/**************************************************************************** - * Name: stm32_dma_intget - * - * Description: - * Public visible interface to get pending interrupts from DMA channel - * - ****************************************************************************/ - -#if defined(HAVE_IP_DMA_V1) -uint32_t stm32_dma_intget(unsigned int chndx); -#elif defined(HAVE_IP_DMA_V2) -uint8_t stm32_dma_intget(unsigned int controller, uint8_t stream); -#endif - -#endif /* CONFIG_ARCH_HIPRI_INTERRUPT */ - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32_STM32_DMA_H */ diff --git a/arch/arm/src/stm32/stm32_dma2d.c b/arch/arm/src/stm32/stm32_dma2d.c deleted file mode 100644 index 83b98668454d7..0000000000000 --- a/arch/arm/src/stm32/stm32_dma2d.c +++ /dev/null @@ -1,1168 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_dma2d.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* References: - * STM32F429 Technical Reference Manual - */ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include - -#include - -#include "arm_internal.h" -#include "stm32.h" -#include "hardware/stm32_ltdc.h" -#include "hardware/stm32_dma2d.h" -#include "stm32_ccm.h" -#include "stm32_dma2d.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* DMA2D supported operation layer (output, foreground, background) */ - -#define DMA2D_NLAYERS 3 - -/* DMA2D blender control */ - -#define STM32_DMA2D_CR_MODE_BLIT DMA2D_CR_MODE(0) -#define STM32_DMA2D_CR_MODE_BLITPFC DMA2D_CR_MODE(1) -#define STM32_DMA2D_CR_MODE_BLEND DMA2D_CR_MODE(2) -#define STM32_DMA2D_CR_MODE_COLOR DMA2D_CR_MODE(3) -#define STM32_DMA2D_CR_MODE_CLEAR STM32_DMA2D_CR_MODE_BLITPFC | \ - STM32_DMA2D_CR_MODE_BLEND | \ - STM32_DMA2D_CR_MODE_COLOR - -/* Only 8 bit per pixel overall supported */ - -#define DMA2D_PF_BYPP(n) ((n) / 8) - -/* CC clut size */ - -#define DMA2D_CLUT_SIZE STM32_DMA2D_NCLUT - 1 - -/* Layer argb cmap conversion */ - -#define DMA2D_CLUT_ALPHA(n) ((uint32_t)(n) << 24) -#define DMA2D_CLUT_RED(n) ((uint32_t)(n) << 16) -#define DMA2D_CLUT_GREEN(n) ((uint32_t)(n) << 8) -#define DMA2D_CLUT_BLUE(n) ((uint32_t)(n) << 0) - -#define DMA2D_CMAP_ALPHA(n) ((uint32_t)(n) >> 24) -#define DMA2D_CMAP_RED(n) ((uint32_t)(n) >> 16) -#define DMA2D_CMAP_GREEN(n) ((uint32_t)(n) >> 8) -#define DMA2D_CMAP_BLUE(n) ((uint32_t)(n) >> 0) - -/* Debug option */ - -#ifdef CONFIG_STM32_DMA2D_REGDEBUG -# define regerr lcderr -# define reginfo lcdinfo -#else -# define regerr(x...) -# define reginfo(x...) -#endif - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/* DMA2D General layer information */ - -struct stm32_dma2d_s -{ - struct dma2d_layer_s dma2d; /* Public dma2d interface */ - -#ifdef CONFIG_STM32_FB_CMAP - uint32_t *clut; /* Color lookup table */ -#endif - mutex_t *lock; /* Ensure mutually exclusive access */ -}; - -/* Interrupt handling */ - -struct stm32_interrupt_s -{ - int irq; /* irq number */ - int error; /* Interrupt error */ - sem_t *sem; /* Semaphore for waiting for irq */ -}; - -/* This enumeration foreground and background layer supported by the dma2d - * controller - */ - -enum stm32_layer_e -{ - DMA2D_LAYER_LFORE = 0, /* Foreground Layer */ - DMA2D_LAYER_LBACK, /* Background Layer */ - DMA2D_LAYER_LOUT, /* Output Layer */ -}; - -/* DMA2D memory address register */ - -static const uintptr_t stm32_mar_layer_t[DMA2D_NLAYERS] = -{ - STM32_DMA2D_FGMAR, - STM32_DMA2D_BGMAR, - STM32_DMA2D_OMAR -}; - -/* DMA2D offset register */ - -static const uintptr_t stm32_or_layer_t[DMA2D_NLAYERS] = -{ - STM32_DMA2D_FGOR, - STM32_DMA2D_BGOR, - STM32_DMA2D_OOR -}; - -/* DMA2D pfc control register */ - -static const uintptr_t stm32_pfccr_layer_t[DMA2D_NLAYERS] = -{ - STM32_DMA2D_FGPFCCR, - STM32_DMA2D_BGPFCCR, - STM32_DMA2D_OPFCCR -}; - -/* DMA2D color register */ - -static const uintptr_t stm32_color_layer_t[DMA2D_NLAYERS] = -{ - STM32_DMA2D_FGCOLR, - STM32_DMA2D_BGCOLR, - STM32_DMA2D_OCOLR -}; - -/* DMA2D clut memory address register */ - -#ifdef CONFIG_STM32_FB_CMAP -static const uintptr_t stm32_cmar_layer_t[DMA2D_NLAYERS - 1] = -{ - STM32_DMA2D_FGCMAR, - STM32_DMA2D_BGCMAR -}; -#endif - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -/* Private functions */ - -static void stm32_dma2d_control(uint32_t setbits, uint32_t clrbits); -static int stm32_dma2dirq(int irq, void *context, void *arg); -static int stm32_dma2d_waitforirq(void); -static int stm32_dma2d_start(void); -#ifdef CONFIG_STM32_FB_CMAP -static int stm32_dma2d_loadclut(uintptr_t reg); -#endif -static uint32_t stm32_dma2d_memaddress( - struct stm32_dma2d_overlay_s *oinfo, - uint32_t xpos, uint32_t ypos); -static uint32_t stm32_dma2d_lineoffset( - struct stm32_dma2d_overlay_s *oinfo, - const struct fb_area_s *area); -static void stm32_dma2d_lfifo(struct stm32_dma2d_overlay_s *oinfo, - int lid, - uint32_t xpos, uint32_t ypos, - const struct fb_area_s *area); -static void stm32_dma2d_lcolor(int lid, uint32_t argb); -static void stm32_dma2d_llnr(const struct fb_area_s *area); -static int stm32_dma2d_loutpfc(uint8_t fmt); -static void stm32_dma2d_lpfc(int lid, uint32_t blendmode, uint8_t alpha, - uint8_t fmt); - -/* Public Functions */ - -#ifdef CONFIG_STM32_FB_CMAP -static int stm32_dma2d_setclut(const struct fb_cmap_s *cmap); -#endif -static int stm32_dma2d_fillcolor(struct stm32_dma2d_overlay_s *oinfo, - const struct fb_area_s *area, - uint32_t argb); -static int stm32_dma2d_blit(struct stm32_dma2d_overlay_s *doverlay, - uint32_t destxpos, uint32_t destypos, - struct stm32_dma2d_overlay_s *soverlay, - const struct fb_area_s *sarea); -static int stm32_dma2d_blend(struct stm32_dma2d_overlay_s *doverlay, - uint32_t destxpos, uint32_t destypos, - struct stm32_dma2d_overlay_s *foverlay, - uint32_t forexpos, uint32_t foreypos, - struct stm32_dma2d_overlay_s *boverlay, - const struct fb_area_s *barea); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* The initialized state of the driver */ - -static bool g_initialized; - -/* Allocate clut */ - -#ifdef CONFIG_STM32_FB_CMAP -static uint32_t g_clut[STM32_DMA2D_NCLUT * -# ifdef CONFIG_STM32_FB_TRANSPARENCY - 4 -# else - 3 -# endif - / 4]; -#endif /* CONFIG_STM32_FB_CMAP */ - -/* The DMA2D mutex that enforces mutually exclusive access */ - -static mutex_t g_lock = NXMUTEX_INITIALIZER; - -/* Semaphore for interrupt handling */ - -static sem_t g_semirq = SEM_INITIALIZER(0); - -/* This structure provides irq handling */ - -static struct stm32_interrupt_s g_interrupt = -{ - .irq = STM32_IRQ_DMA2D, - .error = OK, - .sem = &g_semirq -}; - -static struct stm32_dma2d_s g_dma2ddev = -{ - .dma2d = - { -#ifdef CONFIG_STM32_FB_CMAP - .setclut = stm32_dma2d_setclut, -#endif - .fillcolor = stm32_dma2d_fillcolor, - .blit = stm32_dma2d_blit, - .blend = stm32_dma2d_blend - }, -#ifdef CONFIG_STM32_FB_CMAP - .clut = g_clut, -#endif - .lock = &g_lock -}; - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_dma2d_control - * - * Description: - * Change the DMA2D control register - * - * Input Parameters: - * setbits - The bits to set - * clrbits - The bits to clear - * - ****************************************************************************/ - -static void stm32_dma2d_control(uint32_t setbits, uint32_t clrbits) -{ - uint32_t cr; - - lcdinfo("setbits=%08" PRIx32 ", clrbits=%08" PRIx32 "\n", - setbits, clrbits); - - cr = getreg32(STM32_DMA2D_CR); - cr &= ~clrbits; - cr |= setbits; - - lcdinfo("cr=%08" PRIx32 "\n", cr); - putreg32(cr, STM32_DMA2D_CR); -} - -/**************************************************************************** - * Name: stm32_dma2dirq - * - * Description: - * DMA2D interrupt handler - * - ****************************************************************************/ - -static int stm32_dma2dirq(int irq, void *context, void *arg) -{ - int ret; - uint32_t regval = getreg32(STM32_DMA2D_ISR); - struct stm32_interrupt_s *priv = &g_interrupt; - - reginfo("irq = %d, regval = %08" PRIx32 "\n", irq, regval); - - if (regval & DMA2D_ISR_TCIF) - { - /* Transfer complete interrupt */ - - /* Clear the interrupt status register */ - - reginfo("DMA transfer complete\n"); - putreg32(DMA2D_IFCR_CTCIF, STM32_DMA2D_IFCR); - priv->error = OK; - } -#ifdef CONFIG_STM32_DMA2D_L8 - else if (regval & DMA2D_ISR_CTCIF) - { - /* CLUT transfer complete interrupt */ - - /* Clear the interrupt status register */ - - reginfo("CLUT transfer complete\n"); - putreg32(DMA2D_IFCR_CCTCIF, STM32_DMA2D_IFCR); - priv->error = OK; - } -#endif - else if (regval & DMA2D_ISR_TWIF) - { - /* Watermark transfer complete interrupt */ - - /* Clear the interrupt status register */ - - reginfo("Watermark transfer complete\n"); - putreg32(DMA2D_IFCR_CTWIF, STM32_DMA2D_IFCR); - priv->error = OK; - } - else if (regval & DMA2D_ISR_TEIF) - { - /* Transfer error interrupt */ - - /* Clear the interrupt status register */ - - reginfo("ERROR: transfer\n"); - putreg32(DMA2D_IFCR_CTEIF, STM32_DMA2D_IFCR); - priv->error = -ECANCELED; - } - else if (regval & DMA2D_ISR_CAEIF) - { - /* CLUT access error interrupt */ - - /* Clear the interrupt status register */ - - reginfo("ERROR: clut access\n"); - putreg32(DMA2D_IFCR_CAECIF, STM32_DMA2D_IFCR); - priv->error = -ECANCELED; - } - else if (regval & DMA2D_ISR_CEIF) - { - /* Configuration error interrupt */ - - /* Clear the interrupt status register */ - - reginfo("ERROR: configuration\n"); - putreg32(DMA2D_IFCR_CCEIF, STM32_DMA2D_IFCR); - priv->error = -ECANCELED; - } - else - { - /* Unknown irq, should not occur */ - - DEBUGASSERT("Unknown interrupt error\n"); - } - - /* Unlock the semaphore if locked */ - - ret = nxsem_post(priv->sem); - - if (ret < 0) - { - lcderr("ERROR: nxsem_post() failed\n"); - } - - return OK; -} - -/**************************************************************************** - * Name: stm32_dma2d_waitforirq - * - * Description: - * Helper waits until the dma2d irq occurs. That means that an ongoing clut - * loading or dma transfer was completed. - * Note! The caller must use this function within a critical section. - * - * Returned Value: - * On success OK otherwise ERROR - * - ****************************************************************************/ - -static int stm32_dma2d_waitforirq(void) -{ - int ret; - struct stm32_interrupt_s *priv = &g_interrupt; - - ret = nxsem_wait(priv->sem); - - if (ret < 0) - { - lcderr("ERROR: nxsem_wait() failed\n"); - return ret; - } - - ret = priv->error; - - return ret; -} - -/**************************************************************************** - * Name: stm32_dma2d_loadclut - * - * Description: - * Starts clut loading but doesn't wait until loading is complete! - * - * Input Parameters: - * pfcreg - PFC control Register - * - * Returned Value: - * On success - OK - * On error - -EINVAL - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_DMA2D_L8 -static int stm32_dma2d_loadclut(uintptr_t pfcreg) -{ - int ret; - uint32_t regval; - - /* Start clut loading */ - - regval = getreg32(pfcreg); - regval |= DMA2D_XGPFCCR_START; - reginfo("set regval=%08" PRIx32 "\n", regval); - putreg32(regval, pfcreg); - reginfo("configured regval=%08" PRIx32 "\n", getreg32(pfcreg)); - - /* Wait until clut is finished */ - - ret = stm32_dma2d_waitforirq(); - - return ret; -} -#endif - -/**************************************************************************** - * Name: stm32_dma2d_start - * - * Description: - * Starts the dma transfer and waits until completed. - * - * Input Parameters: - * reg - Register to set the start - * startflag - The related flag to start the dma transfer - * irqflag - The interrupt enable flag in the DMA2D_CR register - * - ****************************************************************************/ - -static int stm32_dma2d_start(void) -{ - int ret; - - /* Start dma transfer */ - - stm32_dma2d_control(DMA2D_CR_START, 0); - - /* wait until transfer is complete */ - - ret = stm32_dma2d_waitforirq(); - - return ret; -} - -/**************************************************************************** - * Name: stm32_dma2d_memaddress - * - * Description: - * Helper to calculate the layer memory address - * - * Input Parameters: - * oinfo - Reference to overlay information - * xpos - x-Offset - * ypos - y-Offset - * - * Returned Value: - * memory address - * - ****************************************************************************/ - -static uint32_t stm32_dma2d_memaddress( - struct stm32_dma2d_overlay_s *oinfo, - uint32_t xpos, uint32_t ypos) -{ - uint32_t offset; - struct fb_overlayinfo_s *poverlay = oinfo->oinfo; - - offset = xpos * DMA2D_PF_BYPP(poverlay->bpp) + poverlay->stride * ypos; - - lcdinfo("%" PRIx32 ", offset=%" PRId32 "\n", - ((uint32_t) poverlay->fbmem) + offset, offset); - return ((uint32_t) poverlay->fbmem) + offset; -} - -/**************************************************************************** - * Name: stm32_dma2d_lineoffset - * - * Description: - * Helper to calculate the layer line offset - * - * Input Parameters: - * oinfo - Reference to overlay information - * - * Returned Value: - * line offset - * - ****************************************************************************/ - -static uint32_t stm32_dma2d_lineoffset( - struct stm32_dma2d_overlay_s *oinfo, - const struct fb_area_s *area) -{ - uint32_t loffset; - - /* offset at the end of each line in the context to the area layer */ - - loffset = oinfo->xres - area->w; - - lcdinfo("%" PRId32 "\n", loffset); - return loffset; -} - -/**************************************************************************** - * Name: stm32_dma2d_lfifo - * - * Description: - * Set the fifo for the foreground, background and output layer - * Configures the memory address register - * Configures the line offset register - * - * Input Parameters: - * layer - Reference to the common layer state structure - * - ****************************************************************************/ - -static void stm32_dma2d_lfifo(struct stm32_dma2d_overlay_s *oinfo, - int lid, uint32_t xpos, uint32_t ypos, - const struct fb_area_s *area) -{ - lcdinfo("oinfo=%p, lid=%d, xpos=%" PRId32 ", ypos=%" PRId32 ", area=%p\n", - oinfo, lid, xpos, ypos, area); - - putreg32(stm32_dma2d_memaddress(oinfo, xpos, ypos), - stm32_mar_layer_t[lid]); - putreg32(stm32_dma2d_lineoffset(oinfo, area), stm32_or_layer_t[lid]); -} - -/**************************************************************************** - * Name: stm32_dma2d_lcolor - * - * Description: - * Set the color for the layer - * - * Input Parameters: - * lid - Layer type (output, foreground, background) - * argb - argb8888 color - * - ****************************************************************************/ - -static void stm32_dma2d_lcolor(int lid, uint32_t argb) -{ - lcdinfo("lid=%d, argb=%08" PRIx32 "\n", lid, argb); - putreg32(argb, stm32_color_layer_t[lid]); -} - -/**************************************************************************** - * Name: stm32_dma2d_llnr - * - * Description: - * Set the number of line register - * - * Input Parameters: - * area - Reference to area information - * - ****************************************************************************/ - -static void stm32_dma2d_llnr(const struct fb_area_s *area) -{ - uint32_t nlrreg; - - lcdinfo("pixel per line: %d, number of lines: %d\n", area->w, area->h); - - nlrreg = getreg32(STM32_DMA2D_NLR); - nlrreg = (DMA2D_NLR_PL(area->w) | DMA2D_NLR_NL(area->h)); - putreg32(nlrreg, STM32_DMA2D_NLR); -} - -/**************************************************************************** - * Name: stm32_dma2d_loutpfc - * - * Description: - * Set the output PFC control register - * - * Input Parameters: - * fmt - DMA2D pixel format - * - ****************************************************************************/ - -static int stm32_dma2d_loutpfc(uint8_t fmt) -{ - lcdinfo("pixel format: %d\n", fmt); - - /* Set the mapped pixel format of the destination layer */ - - putreg32(DMA2D_OPFCCR_CM(fmt), STM32_DMA2D_OPFCCR); - - return OK; -} - -/**************************************************************************** - * Name: stm32_dma2d_lpfc - * - * Description: - * Configure foreground and background layer PFC control register - * - * Input Parameters: - * lid - Layer id (output, foreground, background) - * blendmode - Layer blendmode (dma2d register values) - * alpha - Transparency - * - ****************************************************************************/ - -static void stm32_dma2d_lpfc(int lid, uint32_t blendmode, uint8_t alpha, - uint8_t fmt) -{ - uint32_t pfccrreg; - - lcdinfo("lid=%d, blendmode=%08" PRIx32 ", alpha=%02x, fmt=%d\n", - lid, blendmode, alpha, fmt); - - /* Set color format */ - - pfccrreg = DMA2D_XGPFCCR_CM(fmt); - -#ifdef CONFIG_STM32_FB_CMAP - if (fmt == DMA2D_PF_L8) - { - struct stm32_dma2d_s *layer = &g_dma2ddev; - - /* Load CLUT automatically */ - - pfccrreg |= DMA2D_XGPFCCR_START; - - /* Set the CLUT color mode */ - -# ifndef CONFIG_STM32_FB_TRANSPARENCY - pfccrreg |= DMA2D_XGPFCCR_CCM; -# endif - - /* Set CLUT size */ - - pfccrreg |= DMA2D_XGPFCCR_CS(DMA2D_CLUT_SIZE); - - /* Set the CLUT memory address */ - - putreg32((uint32_t) layer->clut, stm32_cmar_layer_t[lid]); - - /* Start async clut loading */ - - stm32_dma2d_loadclut(stm32_pfccr_layer_t[lid]); - } -#endif /* CONFIG_STM32_FB_CMAP */ - - /* Set alpha blend mode */ - - pfccrreg |= DMA2D_XGPFCCR_AM(blendmode); - - if (blendmode == STM32_DMA2D_PFCCR_AM_CONST || - blendmode == STM32_DMA2D_PFCCR_AM_PIXEL) - { - /* Set alpha value */ - - pfccrreg |= DMA2D_XGPFCCR_ALPHA(alpha); - } - - putreg32(pfccrreg, stm32_pfccr_layer_t[lid]); -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_dma2d_setclut - * - * Description: - * Configure layer clut (color lookup table). - * - * Input Parameters: - * cmap - Color lookup table with up the 256 entries - * - * Returned Value: - * On success - OK - * On error - -EINVAL - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_FB_CMAP -static int stm32_dma2d_setclut(const struct fb_cmap_s *cmap) -{ - int n; - struct stm32_dma2d_s *priv = &g_dma2ddev; - - lcdinfo("cmap=%p\n", cmap); - - nxmutex_lock(priv->lock); - - for (n = cmap->first; n < cmap->len - 1 && n < STM32_DMA2D_NCLUT; n++) - { - /* Update the layer clut entry, will be automatically loaded before - * blit operation becomes active - */ - -# ifndef CONFIG_STM32_FB_TRANSPARENCY - uint8_t *clut = (uint8_t *)g_dma2ddev.clut; - uint16_t offset = 3 * n; - - clut[offset] = cmap->blue[n]; - clut[offset + 1] = cmap->green[n]; - clut[offset + 2] = cmap->red[n]; - - reginfo("n=%d, red=%02x, green=%02x, blue=%02x\n", n, clut[offset], - clut[offset + 1], clut[offset + 2]); -# else - uint32_t *clut = g_dma2ddev.clut; - - clut[n] = (uint32_t)DMA2D_CLUT_ALPHA(cmap->transp[n]) | - (uint32_t)DMA2D_CLUT_RED(cmap->red[n]) | - (uint32_t)DMA2D_CLUT_GREEN(cmap->green[n]) | - (uint32_t)DMA2D_CLUT_BLUE(cmap->blue[n]); - - reginfo("n=%d, alpha=%02x, red=%02x, green=%02x, blue=%02x\n", n, - DMA2D_CLUT_ALPHA(cmap->transp[n]), - DMA2D_CLUT_RED(cmap->red[n]), - DMA2D_CLUT_GREEN(cmap->green[n]), - DMA2D_CLUT_BLUE(cmap->blue[n])); -# endif - } - - nxmutex_unlock(priv->lock); - return OK; -} -#endif /* CONFIG_STM32_FB_CMAP */ - -/**************************************************************************** - * Name: stm32_dma2d_fillcolor - * - * Description: - * Fill the selected area of the whole overlay with a specific color. - * The caller must ensure that the area is within the entire overlay. - * - * Input Parameters: - * oinfo - Overlay to fill - * area - Reference to the valid area structure select the area - * argb - Color to fill the selected area. Color must be argb8888 - * formatted. - * - * Returned Value: - * OK - On success - * -EINVAL - If one of the parameter invalid or if the size of the - * selected area outside the visible area of the layer. - * -ECANCELED - Operation cancelled, something goes wrong. - * - ****************************************************************************/ - -static int stm32_dma2d_fillcolor(struct stm32_dma2d_overlay_s *oinfo, - const struct fb_area_s *area, - uint32_t argb) -{ - int ret; - struct stm32_dma2d_s *priv = &g_dma2ddev; - DEBUGASSERT(oinfo != NULL && oinfo->oinfo != NULL && area != NULL); - - lcdinfo("oinfo=%p, argb=%08" PRIx32 "\n", oinfo, argb); - -#ifdef CONFIG_STM32_FB_CMAP - if (oinfo->fmt == DMA2D_PF_L8) - { - /* CLUT output not supported */ - - lcderr("ERROR: Returning ENOSYS, " - "output to layer with CLUT format not supported.\n"); - return -ENOSYS; - } -#endif - - nxmutex_lock(priv->lock); - - /* Set output pfc */ - - stm32_dma2d_loutpfc(oinfo->fmt); - - /* Set output fifo */ - - stm32_dma2d_lfifo(oinfo, DMA2D_LAYER_LOUT, area->x, area->y, area); - - /* Set the output color register */ - - stm32_dma2d_lcolor(DMA2D_LAYER_LOUT, argb); - - /* Set number of lines and pixel per line */ - - stm32_dma2d_llnr(area); - - /* Set register to memory transfer */ - - stm32_dma2d_control(STM32_DMA2D_CR_MODE_COLOR, STM32_DMA2D_CR_MODE_CLEAR); - - /* Start DMA2D and wait until completed */ - - ret = stm32_dma2d_start(); - - if (ret != OK) - { - ret = -ECANCELED; - lcderr("ERROR: Returning ECANCELED\n"); - } - - nxmutex_unlock(priv->lock); - return ret; -} - -/**************************************************************************** - * Name: stm32_dma2d_blit - * - * Description: - * Copy memory from a source overlay (defined by sarea) to destination - * overlay position (defined by destxpos and destypos). - * - * Input Parameters: - * doverlay - Valid reference to the destination overlay - * destxpos - Valid selected x position of the destination overlay - * destypos - Valid selected y position of the destination overlay - * soverlay - Valid reference to the source overlay - * sarea - Valid reference to the selected area of the source overlay - * - * Returned Value: - * OK - On success - * -EINVAL - If one of the parameter invalid or if the size of the - * selected source area outside the visible area of the - * destination layer. - * (The visible area usually represents the display size) - * -ECANCELED - Operation cancelled, something goes wrong. - * - ****************************************************************************/ - -static int stm32_dma2d_blit(struct stm32_dma2d_overlay_s *doverlay, - uint32_t destxpos, uint32_t destypos, - struct stm32_dma2d_overlay_s *soverlay, - const struct fb_area_s *sarea) -{ - int ret; - uint32_t mode; - struct stm32_dma2d_s *priv = &g_dma2ddev; - - lcdinfo("doverlay=%p, destxpos=%" PRId32 ", destypos=%" PRId32 - ", soverlay=%p, sarea=%p\n", - doverlay, destxpos, destypos, soverlay, sarea); - - nxmutex_lock(priv->lock); - - /* Set output pfc */ - - stm32_dma2d_loutpfc(doverlay->fmt); - - /* Set foreground pfc */ - - stm32_dma2d_lpfc(DMA2D_LAYER_LFORE, STM32_DMA2D_PFCCR_AM_NONE, 0, - soverlay->fmt); - - /* Set foreground fifo */ - - stm32_dma2d_lfifo(soverlay, DMA2D_LAYER_LFORE, sarea->x, sarea->y, sarea); - - /* Set output fifo */ - - stm32_dma2d_lfifo(doverlay, DMA2D_LAYER_LOUT, destxpos, destypos, sarea); - - /* Set number of lines and pixel per line */ - - stm32_dma2d_llnr(sarea); - - /* Set dma2d mode for blit operation */ - - if (doverlay->fmt == soverlay->fmt) - { - /* Blit without pfc */ - - mode = STM32_DMA2D_CR_MODE_BLIT; - } - else - { - /* Blit with pfc */ - - mode = STM32_DMA2D_CR_MODE_BLITPFC; - } - - stm32_dma2d_control(mode, STM32_DMA2D_CR_MODE_CLEAR); - - /* Start DMA2D and wait until completed */ - - ret = stm32_dma2d_start(); - - if (ret != OK) - { - ret = -ECANCELED; - lcderr("ERROR: Returning ECANCELED\n"); - } - - nxmutex_unlock(priv->lock); - return ret; -} - -/**************************************************************************** - * Name: stm32_dma2d_blend - * - * Description: - * Blends the selected area from a background layer with selected position - * of the foreground layer. Copies the result to the selected position of - * the destination layer. Note! The content of the foreground and - * background layer keeps unchanged as long destination layer is unequal to - * the foreground and background layer. - * - * Input Parameters: - * doverlay - Destination overlay - * destxpos - x-Offset destination overlay - * destypos - y-Offset destination overlay - * foverlay - Foreground overlay - * forexpos - x-Offset foreground overlay - * foreypos - y-Offset foreground overlay - * boverlay - Background overlay - * barea - x-Offset, y-Offset, x-resolution and y-resolution of - * background overlay - * - * Returned Value: - * OK - On success - * -EINVAL - If one of the parameter invalid or if the size of the - * selected source area outside the visible area of the - * destination layer. - * (The visible area usually represents the display size) - * -ECANCELED - Operation cancelled, something goes wrong. - * - ****************************************************************************/ - -static int stm32_dma2d_blend(struct stm32_dma2d_overlay_s *doverlay, - uint32_t destxpos, uint32_t destypos, - struct stm32_dma2d_overlay_s *foverlay, - uint32_t forexpos, uint32_t foreypos, - struct stm32_dma2d_overlay_s *boverlay, - const struct fb_area_s *barea) -{ - int ret; - struct stm32_dma2d_s *priv = &g_dma2ddev; - - lcdinfo("doverlay=%p, destxpos=%" PRId32 ", destypos=%" PRId32 ", " - "foverlay=%p, forexpos=%" PRId32 ", foreypos=%" PRId32 ", " - "boverlay=%p, barea=%p, barea.x=%d, barea.y=%d, barea.w=%d, " - "barea.h=%d\n", doverlay, destxpos, destypos, foverlay, forexpos, - foreypos, boverlay, barea, barea->x, barea->y, barea->w, barea->h); - -#ifdef CONFIG_STM32_FB_CMAP - if (doverlay->fmt == DMA2D_PF_L8) - { - /* CLUT output not supported */ - - lcderr("ERROR: Returning ENOSYS, " - "output to layer with CLUT format not supported.\n"); - return -ENOSYS; - } -#endif - - nxmutex_lock(priv->lock); - - /* Set output pfc */ - - stm32_dma2d_loutpfc(doverlay->fmt); - - /* Set background pfc */ - - stm32_dma2d_lpfc(DMA2D_LAYER_LBACK, boverlay->transp_mode, - boverlay->oinfo->transp.transp, boverlay->fmt); - - /* Set foreground pfc */ - - stm32_dma2d_lpfc(DMA2D_LAYER_LFORE, foverlay->transp_mode, - foverlay->oinfo->transp.transp, foverlay->fmt); - - /* Set background fifo */ - - stm32_dma2d_lfifo(boverlay, DMA2D_LAYER_LBACK, barea->x, barea->y, barea); - - /* Set foreground fifo */ - - stm32_dma2d_lfifo(foverlay, DMA2D_LAYER_LFORE, forexpos, foreypos, barea); - - /* Set output fifo */ - - stm32_dma2d_lfifo(doverlay, DMA2D_LAYER_LOUT, destxpos, destypos, barea); - - /* Set number of lines and pixel per line */ - - stm32_dma2d_llnr(barea); - - /* Set watermark */ - - /* Enable DMA2D blender */ - - stm32_dma2d_control(STM32_DMA2D_CR_MODE_BLEND, STM32_DMA2D_CR_MODE_CLEAR); - - /* Start DMA2D and wait until completed */ - - ret = stm32_dma2d_start(); - - if (ret != OK) - { - ret = -ECANCELED; - lcderr("ERROR: Returning ECANCELED\n"); - } - - nxmutex_unlock(priv->lock); - return ret; -} - -/**************************************************************************** - * Name: stm32_dma2dinitialize - * - * Description: - * Initialize the dma2d controller - * - * Returned Value: - * OK - On success - * An error if initializing failed. - * - ****************************************************************************/ - -int stm32_dma2dinitialize(void) -{ - lcdinfo("Initialize DMA2D driver\n"); - - if (g_initialized == false) - { - /* Abort current dma2d data transfer */ - - stm32_dma2duninitialize(); - - /* Enable dma2d is done in rcc_enableahb1, see - * arch/arm/src/stm32/stm32f40xxx_rcc.c - */ - -#ifdef CONFIG_STM32_FB_CMAP - /* Enable dma2d transfer and clut loading interrupts only */ - - stm32_dma2d_control(DMA2D_CR_TCIE | DMA2D_CR_CTCIE, DMA2D_CR_TEIE | - DMA2D_CR_TWIE | DMA2D_CR_CAEIE | DMA2D_CR_CEIE); -#else - /* Enable dma transfer interrupt only */ - - stm32_dma2d_control(DMA2D_CR_TCIE, DMA2D_CR_TEIE | DMA2D_CR_TWIE | - DMA2D_CR_CAEIE | DMA2D_CR_CTCIE | DMA2D_CR_CEIE); -#endif - - stm32_dma2d_control(DMA2D_CR_TCIE | DMA2D_CR_CTCIE | DMA2D_CR_TEIE | - DMA2D_CR_CAEIE | DMA2D_CR_CTCIE | DMA2D_CR_CEIE, - 0); - - /* Attach DMA2D interrupt vector */ - - irq_attach(g_interrupt.irq, stm32_dma2dirq, NULL); - - /* Enable the IRQ at the NVIC */ - - up_enable_irq(g_interrupt.irq); - - g_initialized = true; - } - - return OK; -} - -/**************************************************************************** - * Name: stm32_dma2duninitialize - * - * Description: - * Uninitialize the dma2d controller - * - ****************************************************************************/ - -void stm32_dma2duninitialize(void) -{ - /* Disable DMA2D interrupts */ - - up_disable_irq(g_interrupt.irq); - irq_detach(g_interrupt.irq); - - /* Abort current dma2d transfer */ - - stm32_dma2d_control(DMA2D_CR_ABORT, 0); - - /* Set initialized state */ - - g_initialized = false; -} - -/**************************************************************************** - * Name: stm32_dma2ddev - * - * Description: - * Get a reference to the dma2d controller. - * - * Returned Value: - * On success - A valid dma2d layer reference - * On error - NULL - * - ****************************************************************************/ - -struct dma2d_layer_s *stm32_dma2ddev(void) -{ - return &g_dma2ddev.dma2d; -} diff --git a/arch/arm/src/stm32/stm32_dma2d.h b/arch/arm/src/stm32/stm32_dma2d.h deleted file mode 100644 index f8627cfe1058e..0000000000000 --- a/arch/arm/src/stm32/stm32_dma2d.h +++ /dev/null @@ -1,192 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_dma2d.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32_STM32_DMA2D_H -#define __ARCH_ARM_SRC_STM32_STM32_DMA2D_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include - -#ifdef CONFIG_FB_OVERLAY - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -/* This structure describes DMA2D overlay information */ - -struct stm32_dma2d_overlay_s -{ - uint8_t fmt; /* DMA2D pixel format */ - uint8_t transp_mode; /* DMA2D transparency mode */ - fb_coord_t xres; /* X-resolution overlay */ - fb_coord_t yres; /* Y-resolution overlay */ - struct fb_overlayinfo_s *oinfo; /* Framebuffer overlay information */ -}; - -/* DMA2D is controlled by the following interface */ - -struct dma2d_layer_s -{ - /* Name: setclut - * - * Description: - * Set the cmap table for both foreground and background layer. - * Up to 256 colors supported. - * - * Parameter: - * cmap - Reference to the cmap table - * - * Returned Value: - * On success - OK - * On error - -EINVAL - */ - -#ifdef CONFIG_STM32_FB_CMAP - int (*setclut)(const struct fb_cmap_s * cmap); -#endif - - /* Name: fillcolor - * - * Description: - * Fill a specific memory region with a color. - * The caller must ensure that the memory region (area) is within the - * entire overlay. - * - * Parameter: - * oinfo - Reference to overlay information - * area - Reference to the area to fill - * argb - argb8888 color - * - * Returned Value: - * On success - OK - * On error - -EINVAL - */ - - int (*fillcolor)(struct stm32_dma2d_overlay_s *oinfo, - const struct fb_area_s *area, uint32_t argb); - - /* Name: blit - * - * Description: - * Copies memory from a source overlay (defined by sarea) to destination - * overlay position (defined by destxpos and destypos) without - * pixelformat conversion. The caller must ensure that the memory region - * (area) is within the entire overlay. - * - * Parameter: - * doverlay - Reference destination overlay - * destxpos - x-Offset destination overlay - * destypos - y-Offset destination overlay - * soverlay - Reference source overlay - * sarea - Reference source area - * - * Returned Value: - * On success - OK - * On error - -EINVAL - */ - - int (*blit)(struct stm32_dma2d_overlay_s *doverlay, - uint32_t destxpos, uint32_t destypos, - struct stm32_dma2d_overlay_s *soverlay, - const struct fb_area_s *sarea); - - /* Name: blend - * - * Description: - * Blends two source memory areas to a destination memory area with - * pixelformat conversion if necessary. The caller must ensure that the - * memory region (area) is within the entire overlays. - * - * Parameter: - * doverlay - Destination overlay - * destxpos - x-Offset destination overlay - * destypos - y-Offset destination overlay - * foverlay - Foreground overlay - * forexpos - x-Offset foreground overlay - * foreypos - y-Offset foreground overlay - * boverlay - Background overlay - * barea - x-Offset, y-Offset, x-resolution and y-resolution of - * background overlay - * - * Returned Value: - * On success - OK - * On error - -EINVAL or -ECANCELED - */ - - int (*blend)(struct stm32_dma2d_overlay_s *doverlay, - uint32_t destxpos, uint32_t destypos, - struct stm32_dma2d_overlay_s *foverlay, - uint32_t forexpos, uint32_t foreypos, - struct stm32_dma2d_overlay_s *boverlay, - const struct fb_area_s *barea); -}; - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_dma2ddev - * - * Description: - * Get a reference to the DMA2D controller. - * - * Returned Value: - * On success - A valid DMA2D controller reference - * On error - NULL and errno is set to - * -EINVAL if one of the parameter is invalid - * - ****************************************************************************/ - -struct dma2d_layer_s *stm32_dma2ddev(void); - -/**************************************************************************** - * Name: up_dma2dinitialize - * - * Description: - * Initialize the DMA2D controller - * - * Returned Value: - * OK - On success - * An error if initializing failed. - * - ****************************************************************************/ - -int stm32_dma2dinitialize(void); - -/**************************************************************************** - * Name: up_dma2duninitialize - * - * Description: - * Uninitialize the DMA2D controller - * - ****************************************************************************/ - -void stm32_dma2duninitialize(void); - -#endif /* CONFIG_FB_OVERLAY */ -#endif /* __ARCH_ARM_SRC_STM32_STM32_DMA2D_H */ diff --git a/arch/arm/src/stm32/stm32_dma_v1.c b/arch/arm/src/stm32/stm32_dma_v1.c deleted file mode 100644 index ebd0f3d0af521..0000000000000 --- a/arch/arm/src/stm32/stm32_dma_v1.c +++ /dev/null @@ -1,899 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_dma_v1.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include - -#include -#include -#include - -#include "arm_internal.h" -#include "sched/sched.h" -#include "chip.h" -#include "stm32_dma.h" -#include "stm32.h" - -/* This file supports the STM32 DMA IP core version 1 - F0, F1, F3, G4, L0, - * L1, L4. - * - * F0, L0 and L4 have the additional CSELR register which is used to remap - * the DMA requests for each channel. - * - * G4 has additional channels in DMA1 and DMA2. - */ - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#if defined(CONFIG_STM32_HAVE_DMA1_CHAN8) -# define DMA1_NCHANNELS 8 -#else -# define DMA1_NCHANNELS 7 -#endif - -#if STM32_NDMA > 1 -# if defined(CONFIG_STM32_HAVE_DMA2_CHAN678) -# define DMA2_NCHANNELS 8 -# else -# define DMA2_NCHANNELS 5 -# endif -# define DMA_NCHANNELS (DMA1_NCHANNELS + DMA2_NCHANNELS) -#else -# define DMA_NCHANNELS DMA1_NCHANNELS -#endif - -/* Convert the DMA channel base address to the DMA register block address */ - -#define DMA_BASE(ch) (ch & 0xfffffc00) - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/* This structure describes one DMA channel */ - -struct stm32_dma_s -{ - uint8_t chan; /* DMA channel number (0-6) */ -#ifdef DMA_HAVE_CSELR - uint8_t function; /* DMA peripheral connected to this channel (0-7) */ -#endif - uint8_t irq; /* DMA channel IRQ number */ - sem_t sem; /* Used to wait for DMA channel to become available */ - uint32_t base; /* DMA register channel base address */ - dma_callback_t callback; /* Callback invoked when the DMA completes */ - void *arg; /* Argument passed to callback function */ -}; - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* This array describes the state of each DMA */ - -static struct stm32_dma_s g_dma[DMA_NCHANNELS] = -{ -#if DMA1_NCHANNELS > 0 - { - .chan = 0, - .irq = STM32_IRQ_DMA1CH1, - .sem = SEM_INITIALIZER(1), - .base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(0), - }, -#endif /* DMA1_NCHANNELS > 0 */ -#if DMA1_NCHANNELS > 1 - { - .chan = 1, - .irq = STM32_IRQ_DMA1CH2, - .sem = SEM_INITIALIZER(1), - .base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(1), - }, -#endif /* DMA1_NCHANNELS > 1 */ -#if DMA1_NCHANNELS > 2 - { - .chan = 2, - .irq = STM32_IRQ_DMA1CH3, - .sem = SEM_INITIALIZER(1), - .base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(2), - }, -#endif /* DMA1_NCHANNELS > 2 */ -#if DMA1_NCHANNELS > 3 - { - .chan = 3, - .irq = STM32_IRQ_DMA1CH4, - .sem = SEM_INITIALIZER(1), - .base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(3), - }, -#endif /* DMA1_NCHANNELS > 3 */ -#if DMA1_NCHANNELS > 4 - { - .chan = 4, - .irq = STM32_IRQ_DMA1CH5, - .sem = SEM_INITIALIZER(1), - .base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(4), - }, -#endif /* DMA1_NCHANNELS > 4 */ -#if DMA1_NCHANNELS > 5 - { - .chan = 5, - .irq = STM32_IRQ_DMA1CH6, - .sem = SEM_INITIALIZER(1), - .base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(5), - }, -#endif /* DMA1_NCHANNELS > 5 */ -#if DMA1_NCHANNELS > 6 - { - .chan = 6, - .irq = STM32_IRQ_DMA1CH7, - .sem = SEM_INITIALIZER(1), - .base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(6), - }, -#endif /* DMA1_NCHANNELS > 6 */ -#if DMA1_NCHANNELS > 7 - { - .chan = 7, - .irq = STM32_IRQ_DMA1CH8, - .sem = SEM_INITIALIZER(1), - .base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(7), - }, -#endif /* DMA1_NCHANNELS > 7 */ -#if STM32_NDMA > 1 -#if DMA2_NCHANNELS > 0 - { - .chan = 0, - .irq = STM32_IRQ_DMA2CH1, - .sem = SEM_INITIALIZER(1), - .base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(0), - }, -#endif /* DMA2_NCHANNELS > 0 */ -#if DMA2_NCHANNELS > 1 - { - .chan = 1, - .irq = STM32_IRQ_DMA2CH2, - .sem = SEM_INITIALIZER(1), - .base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(1), - }, -#endif /* DMA2_NCHANNELS > 1 */ -#if DMA2_NCHANNELS > 2 - { - .chan = 2, - .irq = STM32_IRQ_DMA2CH3, - .sem = SEM_INITIALIZER(1), - .base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(2), - }, -#endif /* DMA2_NCHANNELS > 2 */ -#if DMA2_NCHANNELS > 3 - { - .chan = 3, -#if defined(CONFIG_STM32_CONNECTIVITYLINE) || \ - defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX) || \ - defined(CONFIG_STM32_STM32G4XXX) || defined(CONFIG_STM32_STM32L15XX) - .irq = STM32_IRQ_DMA2CH4, -#else - .irq = STM32_IRQ_DMA2CH45, -#endif - .sem = SEM_INITIALIZER(1), - .base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(3), - }, -#endif /* DMA2_NCHANNELS > 3 */ -#if DMA2_NCHANNELS > 4 - { - .chan = 4, -#if defined(CONFIG_STM32_CONNECTIVITYLINE) || \ - defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX) || \ - defined(CONFIG_STM32_STM32G4XXX) || defined(CONFIG_STM32_STM32L15XX) - .irq = STM32_IRQ_DMA2CH5, -#else - .irq = STM32_IRQ_DMA2CH45, -#endif - .sem = SEM_INITIALIZER(1), - .base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(4), - }, -#endif /* DMA2_NCHANNELS > 4 */ -#if DMA2_NCHANNELS > 5 - { - .chan = 5, - .irq = STM32_IRQ_DMA2CH5, - .sem = SEM_INITIALIZER(1), - .base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(5), - }, -#endif /* DMA2_NCHANNELS > 5 */ -#if DMA2_NCHANNELS > 6 - { - .chan = 6, - .irq = STM32_IRQ_DMA2CH6, - .sem = SEM_INITIALIZER(1), - .base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(6), - }, -#endif /* DMA2_NCHANNELS > 6 */ -#if DMA2_NCHANNELS > 7 - { - .chan = 7, - .irq = STM32_IRQ_DMA2CH7, - .sem = SEM_INITIALIZER(1), - .base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(7), - }, -#endif /* DMA2_NCHANNELS > 7 */ -#endif /* STM32_NDMA > 1 */ -}; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * DMA register access functions - ****************************************************************************/ - -/* Get non-channel register from DMA1 or DMA2 */ - -static inline uint32_t dmabase_getreg(struct stm32_dma_s *dmach, - uint32_t offset) -{ - return getreg32(DMA_BASE(dmach->base) + offset); -} - -/* Write to non-channel register in DMA1 or DMA2 */ - -static inline void dmabase_putreg(struct stm32_dma_s *dmach, - uint32_t offset, uint32_t value) -{ - putreg32(value, DMA_BASE(dmach->base) + offset); -} - -/* Get channel register from DMA1 or DMA2 */ - -static inline uint32_t dmachan_getreg(struct stm32_dma_s *dmach, - uint32_t offset) -{ - return getreg32(dmach->base + offset); -} - -/* Write to channel register in DMA1 or DMA2 */ - -static inline void dmachan_putreg(struct stm32_dma_s *dmach, - uint32_t offset, uint32_t value) -{ - putreg32(value, dmach->base + offset); -} - -/**************************************************************************** - * Name: stm32_dmachandisable - * - * Description: - * Disable the DMA channel - * - ****************************************************************************/ - -static void stm32_dmachandisable(struct stm32_dma_s *dmach) -{ - uint32_t regval; - - /* Disable all interrupts at the DMA controller */ - - regval = dmachan_getreg(dmach, STM32_DMACHAN_CCR_OFFSET); - regval &= ~DMA_CCR_ALLINTS; - - /* Disable the DMA channel */ - - regval &= ~DMA_CCR_EN; - dmachan_putreg(dmach, STM32_DMACHAN_CCR_OFFSET, regval); - - /* Clear pending channel interrupts */ - - dmabase_putreg(dmach, STM32_DMA_IFCR_OFFSET, - DMA_ISR_CHAN_MASK(dmach->chan)); -} - -/**************************************************************************** - * Name: irq_to_channel_index - * - * Description: - * Given an IRQ number, find the channel index in the g_dma array. - * - * Parameters: - * irq: IRQ number as passed to stm32_dmainterrupt. - * - * Returned Value: - * On success (IRQ matches a DMA channel), returns index in the g_dma - * array from 0 to DMA_NCHANNELS - 1. On failure (IRQ does not match - * a DMA channel), returns -1. - * - ****************************************************************************/ - -static int irq_to_channel_index(int irq) -{ - int chndx; - - /* Find the DMA channel that matches this IRQ */ - - for (chndx = 0; chndx < DMA_NCHANNELS; chndx++) - { - if (irq == g_dma[chndx].irq) - { - return chndx; - } - } - - /* Failed to find the DMA channel for this IRQ */ - - return -1; -} - -/**************************************************************************** - * Name: stm32_dmainterrupt - * - * Description: - * DMA interrupt handler - * - ****************************************************************************/ - -static int stm32_dmainterrupt(int irq, void *context, void *arg) -{ - struct stm32_dma_s *dmach; - uint32_t isr; - int chndx = 0; - - /* Get the channel structure from the interrupt number */ - - chndx = irq_to_channel_index(irq); - if (chndx < 0) - { - DEBUGPANIC(); - } - - dmach = &g_dma[chndx]; - - /* Get the interrupt status (for this channel only) */ - - isr = dmabase_getreg(dmach, STM32_DMA_ISR_OFFSET) & - DMA_ISR_CHAN_MASK(dmach->chan); - - /* Clear the interrupts we are handling */ - - dmabase_putreg(dmach, STM32_DMA_IFCR_OFFSET, isr); - - /* Invoke the callback */ - - if (dmach->callback) - { - dmach->callback(dmach, isr >> DMA_ISR_CHAN_SHIFT(dmach->chan), - dmach->arg); - } - - return OK; -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_dmainitialize - * - * Description: - * Initialize the DMA subsystem - * - * Returned Value: - * None - * - ****************************************************************************/ - -void weak_function arm_dma_initialize(void) -{ - struct stm32_dma_s *dmach; - int chndx; - - /* Initialize each DMA channel */ - - for (chndx = 0; chndx < DMA_NCHANNELS; chndx++) - { - dmach = &g_dma[chndx]; - - /* Attach DMA interrupt vectors */ - - irq_attach(dmach->irq, stm32_dmainterrupt, NULL); - - /* Disable the DMA channel */ - - stm32_dmachandisable(dmach); - - /* Enable the IRQ at the NVIC (still disabled at the DMA controller) */ - - up_enable_irq(dmach->irq); - } -} - -/**************************************************************************** - * Name: stm32_dmachannel - * - * Description: - * Allocate a DMA channel. This function gives the caller mutually - * exclusive access to the DMA channel specified by the 'chndx' argument. - * DMA channels are shared on the STM32: Devices sharing the same DMA - * channel cannot do DMA concurrently! See the DMACHAN_* definitions in - * stm32_dma.h. - * - * If the DMA channel is not available, then stm32_dmachannel() will wait - * until the holder of the channel relinquishes the channel by calling - * stm32_dmafree(). WARNING: If you have two devices sharing a DMA - * channel and the code never releases the channel, the stm32_dmachannel - * call for the other will hang forever in this function! Don't let your - * design do that! - * - * Hmm.. I suppose this interface could be extended to make a non-blocking - * version. Feel free to do that if that is what you need. - * - * Input Parameters: - * chndx - Identifies the stream/channel resource. For the STM32 F1, this - * is simply the channel number as provided by the DMACHAN_* definitions - * in chip/stm32f10xxx_dma.h. - * - * Returned Value: - * Provided that 'chndx' is valid, this function ALWAYS returns a non-NULL, - * void* DMA channel handle. (If 'chndx' is invalid, the function will - * assert if debug is enabled or do something ignorant otherwise). - * - * Assumptions: - * - The caller does not hold he DMA channel. - * - The caller can wait for the DMA channel to be freed if it is no - * available. - * - ****************************************************************************/ - -DMA_HANDLE stm32_dmachannel(unsigned int chndef) -{ - int chndx = 0; - struct stm32_dma_s *dmach = NULL; - int ret; - -#ifdef DMA_HAVE_CSELR - chndx = (chndef & DMACHAN_SETTING_CHANNEL_MASK) >> - DMACHAN_SETTING_CHANNEL_SHIFT; -#else - chndx = chndef; -#endif - - dmach = &g_dma[chndx]; - - DEBUGASSERT(chndx < DMA_NCHANNELS); - - /* Get exclusive access to the DMA channel -- OR wait until the channel - * is available if it is currently being used by another driver - */ - - ret = nxsem_wait_uninterruptible(&dmach->sem); - if (ret < 0) - { - return NULL; - } - - /* The caller now has exclusive use of the DMA channel */ - -#ifdef DMA_HAVE_CSELR - /* Define the peripheral that will use the channel. This is stored until - * dmasetup is called. - */ - - dmach->function = (chndef & DMACHAN_SETTING_FUNCTION_MASK) >> - DMACHAN_SETTING_FUNCTION_SHIFT; -#endif - - return (DMA_HANDLE)dmach; -} - -/**************************************************************************** - * Name: stm32_dmafree - * - * Description: - * Release a DMA channel. If another thread is waiting for this DMA channel - * in a call to stm32_dmachannel, then this function will re-assign the - * DMA channel to that thread and wake it up. NOTE: The 'handle' used - * in this argument must NEVER be used again until stm32_dmachannel() is - * called again to re-gain access to the channel. - * - * Returned Value: - * None - * - * Assumptions: - * - The caller holds the DMA channel. - * - There is no DMA in progress - * - ****************************************************************************/ - -void stm32_dmafree(DMA_HANDLE handle) -{ - struct stm32_dma_s *dmach = (struct stm32_dma_s *)handle; - - DEBUGASSERT(handle != NULL); - - /* Release the channel */ - - nxsem_post(&dmach->sem); -} - -/**************************************************************************** - * Name: stm32_dmasetup - * - * Description: - * Configure DMA before using - * - ****************************************************************************/ - -void stm32_dmasetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr, - size_t ntransfers, uint32_t ccr) -{ - struct stm32_dma_s *dmach = (struct stm32_dma_s *)handle; - uint32_t regval; - - /* Then DMA_CNDTRx register can only be modified if the DMA channel is - * disabled. - */ - - regval = dmachan_getreg(dmach, STM32_DMACHAN_CCR_OFFSET); - regval &= ~(DMA_CCR_EN); - dmachan_putreg(dmach, STM32_DMACHAN_CCR_OFFSET, regval); - - /* Set the peripheral register address in the DMA_CPARx register. The data - * will be moved from/to this address to/from the memory after the - * peripheral event. - */ - - dmachan_putreg(dmach, STM32_DMACHAN_CPAR_OFFSET, paddr); - - /* Set the memory address in the DMA_CMARx register. The data will be - * written to or read from this memory after the peripheral event. - */ - - dmachan_putreg(dmach, STM32_DMACHAN_CMAR_OFFSET, maddr); - - /* Configure the total number of data to be transferred in the DMA_CNDTRx - * register. After each peripheral event, this value will be decremented. - */ - - dmachan_putreg(dmach, STM32_DMACHAN_CNDTR_OFFSET, ntransfers); - - /* Configure the channel priority using the PL[1:0] bits in the DMA_CCRx - * register. Configure data transfer direction, circular mode, - * peripheral & memory incremented mode, peripheral & memory data size, - * and interrupt after half and/or full transfer in the DMA_CCRx register. - */ - - regval = dmachan_getreg(dmach, STM32_DMACHAN_CCR_OFFSET); - regval &= ~(DMA_CCR_MEM2MEM | DMA_CCR_PL_MASK | DMA_CCR_MSIZE_MASK | - DMA_CCR_PSIZE_MASK | DMA_CCR_MINC | DMA_CCR_PINC | - DMA_CCR_CIRC | DMA_CCR_DIR); - ccr &= (DMA_CCR_MEM2MEM | DMA_CCR_PL_MASK | DMA_CCR_MSIZE_MASK | - DMA_CCR_PSIZE_MASK | DMA_CCR_MINC | DMA_CCR_PINC | - DMA_CCR_CIRC | DMA_CCR_DIR); - regval |= ccr; - dmachan_putreg(dmach, STM32_DMACHAN_CCR_OFFSET, regval); - -#ifdef DMA_HAVE_CSELR - /* Define peripheral indicated in dmach->function */ - - regval = dmabase_getreg(dmach, STM32_DMA_CSELR_OFFSET); - regval &= ~(0x0f << (dmach->chan << 2)); - regval |= (dmach->function << (dmach->chan << 2)); - dmabase_putreg(dmach, STM32_DMA_CSELR_OFFSET, regval); -#endif -} - -/**************************************************************************** - * Name: stm32_dmastart - * - * Description: - * Start the DMA transfer - * - * Assumptions: - * - DMA handle allocated by stm32_dmachannel() - * - No DMA in progress - * - ****************************************************************************/ - -void stm32_dmastart(DMA_HANDLE handle, dma_callback_t callback, - void *arg, bool half) -{ - struct stm32_dma_s *dmach = (struct stm32_dma_s *)handle; - uint32_t ccr; - - DEBUGASSERT(handle != NULL); - - /* Save the callback info. This will be invoked when the DMA completes. */ - - dmach->callback = callback; - dmach->arg = arg; - - /* Activate the channel by setting the ENABLE bit in the DMA_CCRx register. - * As soon as the channel is enabled, it can serve any DMA request from the - * peripheral connected on the channel. - */ - - ccr = dmachan_getreg(dmach, STM32_DMACHAN_CCR_OFFSET); - ccr |= DMA_CCR_EN; - - /* In normal mode, interrupt at either half or full completion. In circular - * mode, always interrupt on buffer wrap, and optionally interrupt at the - * halfway point. - */ - - if ((ccr & DMA_CCR_CIRC) == 0) - { - /* Once half of the bytes are transferred, the half-transfer flag - * (HTIF) is set and an interrupt is generated if the Half-Transfer - * Interrupt Enable bit (HTIE) is set. At the end of the transfer, the - * Transfer Complete Flag (TCIF) is set and an interrupt is generated - * if the Transfer Complete Interrupt Enable bit (TCIE) is set. - */ - - ccr |= (half ? - (DMA_CCR_HTIE | DMA_CCR_TEIE) : (DMA_CCR_TCIE | DMA_CCR_TEIE)); - } - else - { - /* In nonstop mode, when the transfer completes it immediately resets - * and starts again. The transfer-complete interrupt is thus always - * enabled, and the half-complete interrupt can be used in circular - * mode to determine when the buffer is half-full or in double-buffered - * mode to determine when one of the two buffers is full. - */ - - ccr |= (half ? DMA_CCR_HTIE : 0) | DMA_CCR_TCIE | DMA_CCR_TEIE; - } - - dmachan_putreg(dmach, STM32_DMACHAN_CCR_OFFSET, ccr); -} - -/**************************************************************************** - * Name: stm32_dmastop - * - * Description: - * Cancel the DMA. After stm32_dmastop() is called, the DMA channel is - * reset and stm32_dmasetup() must be called before stm32_dmastart() can be - * called again - * - * Assumptions: - * - DMA handle allocated by stm32_dmachannel() - * - ****************************************************************************/ - -void stm32_dmastop(DMA_HANDLE handle) -{ - struct stm32_dma_s *dmach = (struct stm32_dma_s *)handle; - stm32_dmachandisable(dmach); -} - -/**************************************************************************** - * Name: stm32_dmaresidual - * - * Description: - * Returns the number of bytes remaining to be transferred - * - * Assumptions: - * - DMA handle allocated by stm32_dmachannel() - * - ****************************************************************************/ - -size_t stm32_dmaresidual(DMA_HANDLE handle) -{ - struct stm32_dma_s *dmach = (struct stm32_dma_s *)handle; - - return dmachan_getreg(dmach, STM32_DMACHAN_CNDTR_OFFSET); -} - -/**************************************************************************** - * Name: stm32_dmacapable - * - * Description: - * Check if the DMA controller can transfer data to/from given memory - * address. This depends on the internal connections in the ARM bus matrix - * of the processor. Note that this only applies to memory addresses, it - * will return false for any peripheral address. - * - * Returned Value: - * True, if transfer is possible. - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_DMACAPABLE -bool stm32_dmacapable(uintptr_t maddr, uint32_t count, uint32_t ccr) -{ - uint32_t transfer_size; - uint32_t mend; - - /* Verify that the address conforms to the memory transfer size. - * Transfers to/from memory performed by the DMA controller are - * required to be aligned to their size. - * - * See ST RM0090 rev4, section 9.3.11 - * - * Compute mend inline to avoid a possible non-constant integer - * multiply. - */ - - switch (ccr & DMA_CCR_MSIZE_MASK) - { - case DMA_CCR_MSIZE_8BITS: - transfer_size = 1; - mend = maddr + count - 1; - break; - - case DMA_CCR_MSIZE_16BITS: - transfer_size = 2; - mend = maddr + (count << 1) - 1; - break; - - case DMA_CCR_MSIZE_32BITS: - transfer_size = 4; - mend = maddr + (count << 2) - 1; - break; - - default: - return false; - } - - if ((maddr & (transfer_size - 1)) != 0) - { - return false; - } - - /* Verify that the transfer is to a memory region that supports DMA. */ - - if ((maddr & STM32_REGION_MASK) != (mend & STM32_REGION_MASK)) - { - return false; - } - - switch (maddr & STM32_REGION_MASK) - { -#if defined(CONFIG_STM32_STM32F10XX) - case STM32_FSMC_BANK1: - case STM32_FSMC_BANK2: - case STM32_FSMC_BANK3: - case STM32_FSMC_BANK4: -#endif - case STM32_SRAM_BASE: - case STM32_CODE_BASE: - - /* All RAM and flash is supported */ - - return true; - - default: - - /* Everything else is unsupported by DMA */ - - return false; - } -} -#endif - -/**************************************************************************** - * Name: stm32_dmasample - * - * Description: - * Sample DMA register contents - * - * Assumptions: - * - DMA handle allocated by stm32_dmachannel() - * - ****************************************************************************/ - -#ifdef CONFIG_DEBUG_DMA_INFO -void stm32_dmasample(DMA_HANDLE handle, struct stm32_dmaregs_s *regs) -{ - struct stm32_dma_s *dmach = (struct stm32_dma_s *)handle; - irqstate_t flags; - - flags = enter_critical_section(); - regs->isr = dmabase_getreg(dmach, STM32_DMA_ISR_OFFSET); -#ifdef DMA_HAVE_CSELR - regs->cselr = dmabase_getreg(dmach, STM32_DMA_CSELR_OFFSET); -#endif - regs->ccr = dmachan_getreg(dmach, STM32_DMACHAN_CCR_OFFSET); - regs->cndtr = dmachan_getreg(dmach, STM32_DMACHAN_CNDTR_OFFSET); - regs->cpar = dmachan_getreg(dmach, STM32_DMACHAN_CPAR_OFFSET); - regs->cmar = dmachan_getreg(dmach, STM32_DMACHAN_CMAR_OFFSET); - leave_critical_section(flags); -} -#endif - -/**************************************************************************** - * Name: stm32_dmadump - * - * Description: - * Dump previously sampled DMA register contents - * - * Assumptions: - * - DMA handle allocated by stm32_dmachannel() - * - ****************************************************************************/ - -#ifdef CONFIG_DEBUG_DMA_INFO -void stm32_dmadump(DMA_HANDLE handle, const struct stm32_dmaregs_s *regs, - const char *msg) -{ - struct stm32_dma_s *dmach = (struct stm32_dma_s *)handle; - uint32_t dmabase = DMA_BASE(dmach->base); - - dmainfo("DMA Registers: %s\n", msg); - dmainfo(" ISRC[%08" PRIx32 "]: %08" PRIx32 "\n", - dmabase + STM32_DMA_ISR_OFFSET, regs->isr); -#ifdef DMA_HAVE_CSELR - dmainfo(" CSELR[%08" PRIx32 "]: %08" PRIx32 "\n", - dmabase + STM32_DMA_CSELR_OFFSET, regs->cselr); -#endif - dmainfo(" CCR[%08" PRIx32 "]: %08" PRIx32 "\n", - dmach->base + STM32_DMACHAN_CCR_OFFSET, regs->ccr); - dmainfo(" CNDTR[%08" PRIx32 "]: %08" PRIx32 "\n", - dmach->base + STM32_DMACHAN_CNDTR_OFFSET, regs->cndtr); - dmainfo(" CPAR[%08" PRIx32 "]: %08" PRIx32 "\n", - dmach->base + STM32_DMACHAN_CPAR_OFFSET, regs->cpar); - dmainfo(" CMAR[%08" PRIx32 "]: %08" PRIx32 "\n", - dmach->base + STM32_DMACHAN_CMAR_OFFSET, regs->cmar); -} -#endif - -#ifdef CONFIG_ARCH_HIPRI_INTERRUPT - -/**************************************************************************** - * Name: stm32_dma_intack - * - * Description: - * Public visible interface to acknowledge interrupts on DMA channel - * - ****************************************************************************/ - -void stm32_dma_intack(unsigned int chndx, uint32_t isr) -{ - struct stm32_dma_s *dmach = &g_dma[chndx]; - - dmabase_putreg(dmach, STM32_DMA_IFCR_OFFSET, isr); -} - -/**************************************************************************** - * Name: stm32_dma_intget - * - * Description: - * Public visible interface to get pending interrupts from DMA channel - * - ****************************************************************************/ - -uint32_t stm32_dma_intget(unsigned int chndx) -{ - struct stm32_dma_s *dmach = &g_dma[chndx]; - - return dmabase_getreg(dmach, STM32_DMA_ISR_OFFSET) & - DMA_ISR_CHAN_MASK(dmach->chan); -} -#endif /* CONFIG_ARCH_HIPRI_INTERRUPT */ diff --git a/arch/arm/src/stm32/stm32_dma_v1mux.c b/arch/arm/src/stm32/stm32_dma_v1mux.c deleted file mode 100644 index d518dcf801c0c..0000000000000 --- a/arch/arm/src/stm32/stm32_dma_v1mux.c +++ /dev/null @@ -1,1457 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_dma_v1mux.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -#include "arm_internal.h" -#include "sched/sched.h" -#include "stm32_dma.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#ifndef CONFIG_STM32_DMAMUX -# error "Configuration error, CONFIG_STM32_DMAMUX not defined!" -#endif - -#ifndef CONFIG_STM32_DMAMUX1 -# error "Configuration error, CONFIG_STM32_DMAMUX1 not defined!" -#endif - -#define DMAMUX_NUM 1 -#define DMA_CONTROLLERS 2 - -#ifdef CONFIG_STM32_DMA1 -# if defined(CONFIG_STM32_STM32G4_CAT2) -# define DMA1_NCHAN 7 -# elif defined(CONFIG_STM32_STM32G4_CAT3) || defined(CONFIG_STM32_STM32G4_CAT4) -# define DMA1_NCHAN 8 -# else -# error -# endif -#else -# define DMA1_NCHAN 0 -#endif -#ifdef CONFIG_STM32_DMA2 -# if defined(CONFIG_STM32_STM32G4_CAT2) -# define DMA2_NCHAN 6 -# elif defined(CONFIG_STM32_STM32G4_CAT3) || defined(CONFIG_STM32_STM32G4_CAT4) -# define DMA2_NCHAN 8 -# else -# error -# endif -#else -# define DMA2_NCHAN 0 -#endif - -#define DMA1_FIRST (0) -#define DMA1_LAST (DMA1_FIRST+DMA1_NCHAN) -#define DMA2_FIRST (DMA1_LAST) -#define DMA2_LAST (DMA2_FIRST+DMA2_NCHAN) - -/* All available DMA channels */ - -#define DMA_NCHANNELS (DMA1_NCHAN + DMA2_NCHAN) - -/* DMAMUX channels */ - -#if defined(CONFIG_STM32_STM32G4_CAT2) -# define DMAMUX_NCHANNELS 12 -#elif defined(CONFIG_STM32_STM32G4_CAT3) || defined(CONFIG_STM32_STM32G4_CAT4) -# define DMAMUX_NCHANNELS 16 -#else -# error -#endif - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/* This structure described one DMAMUX device */ - -struct stm32_dmamux_s -{ - uint8_t id; /* DMAMUX id */ - uint8_t nchan; /* DMAMUX channels */ - uint32_t base; /* DMAMUX base address */ -}; - -typedef const struct stm32_dmamux_s *DMA_MUX; - -/* This structure describes one DMA controller */ - -struct stm32_dma_s -{ - uint8_t first; /* Offset in stm32_dmach_s array */ - uint8_t nchan; /* Number of channels */ - uint8_t dmamux_offset; /* DMAMUX channel offset */ - uint32_t base; /* Base address */ - DMA_MUX dmamux; /* DMAMUX associated with controller */ -}; - -/* This structure describes one DMA channel (DMA1, DMA2) */ - -struct stm32_dmach_s -{ - bool used; /* Channel in use */ - uint8_t dmamux_req; /* Configured DMAMUX input request */ - uint8_t ctrl; /* DMA controller */ - uint8_t chan; /* DMA channel channel id */ - uint8_t irq; /* DMA channel IRQ number */ - uint8_t shift; /* IFCR bit shift value */ - uint32_t base; /* DMA register channel base address */ - dma_callback_t callback; /* Callback invoked when the DMA completes */ - void *arg; /* Argument passed to callback function */ -}; - -typedef struct stm32_dmach_s *DMA_CHANNEL; - -/* DMA operations */ - -struct stm32_dma_ops_s -{ - /* Disable the DMA transfer */ - - void (*dma_disable)(DMA_CHANNEL dmachan); - - /* DMA interrupt */ - - int (*dma_interrupt)(int irq, void *context, void *arg); - - /* Setup the DMA */ - - void (*dma_setup)(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr, - size_t ntransfers, uint32_t ccr); - - /* Start the DMA */ - - void (*dma_start)(DMA_HANDLE handle, dma_callback_t callback, - void *arg, bool half); - - /* Read remaining DMA bytes */ - - size_t (*dma_residual)(DMA_HANDLE handle); - - /* Check the DMA configuration */ - - bool (*dma_capable)(uint32_t maddr, uint32_t count, uint32_t ccr); - -#ifdef CONFIG_DEBUG_DMA_INFO - /* Sample the DMA registers */ - - void (*dma_sample)(DMA_HANDLE handle, struct stm32_dmaregs_s *regs); - - /* Dump the DMA registers */ - - void (*dma_dump)(DMA_HANDLE handle, - const struct stm32_dmaregs_s *regs, - const char *msg); -#endif -}; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -#if defined(CONFIG_STM32_DMA1) || defined(CONFIG_STM32_DMA2) -static void stm32_dma12_disable(DMA_CHANNEL dmachan); -static int stm32_dma12_interrupt(int irq, void *context, void *arg); -static void stm32_dma12_setup(DMA_HANDLE handle, uint32_t paddr, - uint32_t maddr, size_t ntransfers, - uint32_t ccr); -static void stm32_dma12_start(DMA_HANDLE handle, dma_callback_t callback, - void *arg, bool half); -static size_t stm32_dma12_residual(DMA_HANDLE handle); -#ifdef CONFIG_DEBUG_DMA_INFO -static void stm32_dma12_sample(DMA_HANDLE handle, - struct stm32_dmaregs_s *regs); -static void stm32_dma12_dump(DMA_HANDLE handle, - const struct stm32_dmaregs_s *regs, - const char *msg); -#endif -#endif - -static uint32_t dmachan_getbase(DMA_CHANNEL dmachan); -static uint32_t dmabase_getreg(DMA_CHANNEL dmachan, uint32_t offset); -static void dmabase_putreg(DMA_CHANNEL dmachan, uint32_t offset, - uint32_t value); -static uint32_t dmachan_getreg(DMA_CHANNEL dmachan, uint32_t offset); -static void dmachan_putreg(DMA_CHANNEL dmachan, uint32_t offset, - uint32_t value); -static void dmamux_putreg(DMA_MUX dmamux, uint32_t offset, uint32_t value); -#ifdef CONFIG_DEBUG_DMA_INFO -static uint32_t dmamux_getreg(DMA_MUX dmamux, uint32_t offset); -static void stm32_dmamux_sample(DMA_MUX dmamux, uint8_t chan, - struct stm32_dmaregs_s *regs); -static void stm32_dmamux_dump(DMA_MUX dmamux, uint8_t channel, - const struct stm32_dmaregs_s *regs); -#endif -static DMA_CHANNEL stm32_dma_channel_get(uint8_t channel, - uint8_t controller); -static void stm32_gdma_limits_get(uint8_t controller, uint8_t *first, - uint8_t *last); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* Operations specific to DMA controller */ - -static const struct stm32_dma_ops_s g_dma_ops[DMA_CONTROLLERS] = -{ -#ifdef CONFIG_STM32_DMA1 - /* 0 - DMA1 */ - - { - .dma_disable = stm32_dma12_disable, - .dma_interrupt = stm32_dma12_interrupt, - .dma_setup = stm32_dma12_setup, - .dma_start = stm32_dma12_start, - .dma_residual = stm32_dma12_residual, -#ifdef CONFIG_DEBUG_DMA_INFO - .dma_sample = stm32_dma12_sample, - .dma_dump = stm32_dma12_dump, -#endif - }, -#else - { - NULL - }, -#endif - -#ifdef CONFIG_STM32_DMA2 - /* 1 - DMA2 */ - - { - .dma_disable = stm32_dma12_disable, - .dma_interrupt = stm32_dma12_interrupt, - .dma_setup = stm32_dma12_setup, - .dma_start = stm32_dma12_start, - .dma_residual = stm32_dma12_residual, -#ifdef CONFIG_DEBUG_DMA_INFO - .dma_sample = stm32_dma12_sample, - .dma_dump = stm32_dma12_dump, -#endif - } -#else - { - NULL - } -#endif -}; - -/* This array describes the state of DMAMUX controller */ - -static const struct stm32_dmamux_s g_dmamux[DMAMUX_NUM] = -{ - { - .id = 1, - .nchan = DMAMUX_NCHANNELS, - .base = STM32_DMAMUX1_BASE - } -}; - -/* This array describes the state of each controller */ - -static const struct stm32_dma_s g_dma[DMA_NCHANNELS] = -{ - /* 0 - DMA1 */ - - { - .base = STM32_DMA1_BASE, - .first = DMA1_FIRST, - .nchan = DMA1_NCHAN, - .dmamux = &g_dmamux[DMAMUX1], /* DMAMUX1 channels 0-6 */ - .dmamux_offset = 0 - }, - - /* 1 - DMA2 */ - - { - .base = STM32_DMA2_BASE, - .first = DMA2_FIRST, - .nchan = DMA2_NCHAN, - .dmamux = &g_dmamux[DMAMUX1], /* DMAMUX1 channels 7-13 */ - .dmamux_offset = 7 - } -}; - -/* This array describes the state of each DMA channel. */ - -static struct stm32_dmach_s g_dmach[DMA_NCHANNELS] = -{ -#ifdef CONFIG_STM32_DMA1 - /* DMA1 */ - - { - .ctrl = DMA1, - .chan = 0, - .irq = STM32_IRQ_DMA1CH1, - .shift = DMA_CHAN_SHIFT(0), - .base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(0), - }, - - { - .ctrl = DMA1, - .chan = 1, - .irq = STM32_IRQ_DMA1CH2, - .shift = DMA_CHAN_SHIFT(1), - .base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(1), - }, - - { - .ctrl = DMA1, - .chan = 2, - .irq = STM32_IRQ_DMA1CH3, - .shift = DMA_CHAN_SHIFT(2), - .base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(2), - }, - - { - .ctrl = DMA1, - .chan = 3, - .irq = STM32_IRQ_DMA1CH4, - .shift = DMA_CHAN_SHIFT(3), - .base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(3), - }, - - { - .ctrl = DMA1, - .chan = 4, - .irq = STM32_IRQ_DMA1CH5, - .shift = DMA_CHAN_SHIFT(4), - .base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(4), - }, - - { - .ctrl = DMA1, - .chan = 5, - .irq = STM32_IRQ_DMA1CH6, - .shift = DMA_CHAN_SHIFT(5), - .base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(5), - }, - - { - .ctrl = DMA1, - .chan = 6, - .irq = STM32_IRQ_DMA1CH7, - .shift = DMA_CHAN_SHIFT(6), - .base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(6), - }, - -# if DMA1_NCHAN > 7 - { - .ctrl = DMA1, - .chan = 7, - .irq = STM32_IRQ_DMA1CH8, - .shift = DMA_CHAN_SHIFT(7), - .base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(7), - }, -# endif -#endif - -#ifdef CONFIG_STM32_DMA2 - /* DMA2 */ - - { - .ctrl = DMA2, - .chan = 0, - .irq = STM32_IRQ_DMA2CH1, - .shift = DMA_CHAN_SHIFT(0), - .base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(0), - }, - - { - .ctrl = DMA2, - .chan = 1, - .irq = STM32_IRQ_DMA2CH2, - .shift = DMA_CHAN_SHIFT(1), - .base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(1), - }, - - { - .ctrl = DMA2, - .chan = 2, - .irq = STM32_IRQ_DMA2CH3, - .shift = DMA_CHAN_SHIFT(2), - .base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(2), - }, - - { - .ctrl = DMA2, - .chan = 3, - .irq = STM32_IRQ_DMA2CH4, - .shift = DMA_CHAN_SHIFT(3), - .base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(3), - }, - - { - .ctrl = DMA2, - .chan = 4, - .irq = STM32_IRQ_DMA2CH5, - .shift = DMA_CHAN_SHIFT(4), - .base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(4), - }, - - { - .ctrl = DMA2, - .chan = 5, - .irq = STM32_IRQ_DMA2CH6, - .shift = DMA_CHAN_SHIFT(5), - .base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(5), - }, - -# if DMA2_NCHAN > 6 - { - .ctrl = DMA2, - .chan = 6, - .irq = STM32_IRQ_DMA2CH7, - .shift = DMA_CHAN_SHIFT(6), - .base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(6), - }, -# endif - -# if DMA2_NCHAN > 7 - { - .ctrl = DMA2, - .chan = 7, - .irq = STM32_IRQ_DMA2CH8, - .shift = DMA_CHAN_SHIFT(7), - .base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(7), - }, -# endif -#endif -}; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * DMA register access functions - ****************************************************************************/ - -/**************************************************************************** - * Name: dmachan_getbase - * - * Description: - * Get base DMA address for dmachan - * - ****************************************************************************/ - -static uint32_t dmachan_getbase(DMA_CHANNEL dmachan) -{ - uint8_t controller = dmachan->ctrl; - - return g_dma[controller].base; -} - -/**************************************************************************** - * Name: dmabase_getreg - * - * Description: - * Get non-channel register from DMA controller - * - ****************************************************************************/ - -static uint32_t dmabase_getreg(DMA_CHANNEL dmachan, uint32_t offset) -{ - uint32_t dmabase = dmachan_getbase(dmachan); - - return getreg32(dmabase + offset); -} - -/**************************************************************************** - * Name: dmabase_putreg - * - * Description: - * Write to non-channel register in DMA controller - * - ****************************************************************************/ - -static void dmabase_putreg(DMA_CHANNEL dmachan, uint32_t offset, - uint32_t value) -{ - uint32_t dmabase = dmachan_getbase(dmachan); - - putreg32(value, dmabase + offset); -} - -/**************************************************************************** - * Name: dmachan_getreg - * - * Description: - * Get channel register. - * - ****************************************************************************/ - -static uint32_t dmachan_getreg(DMA_CHANNEL dmachan, uint32_t offset) -{ - return getreg32(dmachan->base + offset); -} - -/**************************************************************************** - * Name: dmachan_putreg - * - * Description: - * Write to channel register. - * - ****************************************************************************/ - -static void dmachan_putreg(DMA_CHANNEL dmachan, uint32_t offset, - uint32_t value) -{ - putreg32(value, dmachan->base + offset); -} - -/**************************************************************************** - * Name: dmamux_getreg - * - * Description: - * Write to DMAMUX - * - ****************************************************************************/ - -static void dmamux_putreg(DMA_MUX dmamux, uint32_t offset, uint32_t value) -{ - putreg32(value, dmamux->base + offset); -} - -/**************************************************************************** - * Name: dmamux_getreg - * - * Description: - * Get DMAMUX register. - * - ****************************************************************************/ - -#ifdef CONFIG_DEBUG_DMA_INFO -static uint32_t dmamux_getreg(DMA_MUX dmamux, uint32_t offset) -{ - return getreg32(dmamux->base + offset); -} -#endif - -/**************************************************************************** - * Name: stm32_dma_channel_get - * - * Description: - * Get the g_dmach table entry associated with a given DMA controller - * and channel number. - * - ****************************************************************************/ - -static DMA_CHANNEL stm32_dma_channel_get(uint8_t channel, - uint8_t controller) -{ - uint8_t first = 0; - uint8_t nchan = 0; - - /* Get limits for g_dma array */ - - stm32_gdma_limits_get(controller, &first, &nchan); - - DEBUGASSERT(channel <= nchan); - - return &g_dmach[first + channel]; -} - -/**************************************************************************** - * Name: stm32_gdma_limits_get - * - * Description: - * Get g_dma array limits for a given DMA controller. - * - ****************************************************************************/ - -static void stm32_gdma_limits_get(uint8_t controller, uint8_t *first, - uint8_t *nchan) -{ - DEBUGASSERT(first != NULL); - DEBUGASSERT(nchan != NULL); - - DEBUGASSERT(controller >= DMA1 && controller <= DMA2); - - *first = g_dma[controller].first; - *nchan = g_dma[controller].nchan; -} - -/**************************************************************************** - * DMA controller functions - ****************************************************************************/ - -#if defined(CONFIG_STM32_DMA1) || defined(CONFIG_STM32_DMA2) - -/**************************************************************************** - * Name: stm32_dma12_disable - * - * Description: - * Disable DMA channel (DMA1/DMA2) - * - ****************************************************************************/ - -static void stm32_dma12_disable(DMA_CHANNEL dmachan) -{ - uint32_t regval; - - DEBUGASSERT(dmachan->ctrl == DMA1 || dmachan->ctrl == DMA2); - - /* Disable all interrupts at the DMA controller */ - - regval = dmachan_getreg(dmachan, STM32_DMACHAN_CCR_OFFSET); - regval &= ~DMA_CCR_ALLINTS; - - /* Disable the DMA channel */ - - regval &= ~DMA_CCR_EN; - dmachan_putreg(dmachan, STM32_DMACHAN_CCR_OFFSET, regval); - - /* Clear pending channel interrupts */ - - dmabase_putreg(dmachan, STM32_DMA_IFCR_OFFSET, - DMA_ISR_CHAN_MASK(dmachan->chan)); -} - -/**************************************************************************** - * Name: stm32_dma12_interrupt - * - * Description: - * DMA channel interrupt handler - * - ****************************************************************************/ - -static int stm32_dma12_interrupt(int irq, void *context, void *arg) -{ - DMA_CHANNEL dmachan; - uint32_t isr; - uint8_t channel; - uint8_t controller; - - /* Get the channel and the controller that generated the interrupt */ - - if (0) - { - } -#ifdef CONFIG_STM32_DMA1 - else if (irq >= STM32_IRQ_DMA1CH1 && irq <= STM32_IRQ_DMA1CH7) - { - channel = irq - STM32_IRQ_DMA1CH1; - controller = DMA1; - } -#endif -#ifdef CONFIG_STM32_DMA2 - else if (irq >= STM32_IRQ_DMA2CH1 && irq <= STM32_IRQ_DMA2CH5) - { - channel = irq - STM32_IRQ_DMA2CH1; - controller = DMA2; - } - else if (irq >= STM32_IRQ_DMA2CH6 && irq <= STM32_IRQ_DMA2CH7) - { - channel = irq - STM32_IRQ_DMA2CH6 + (6 - 1); - controller = DMA2; - } -#endif - else - { - DEBUGPANIC(); - return OK; - } - - /* Get the channel structure from the stream and controller numbers */ - - dmachan = stm32_dma_channel_get(channel, controller); - - /* Get the interrupt status (for this channel only) */ - - isr = dmabase_getreg(dmachan, STM32_DMA_ISR_OFFSET) & - DMA_ISR_CHAN_MASK(dmachan->chan); - - /* Invoke the callback */ - - if (dmachan->callback) - { - dmachan->callback(dmachan, isr >> DMA_ISR_CHAN_SHIFT(dmachan->chan), - dmachan->arg); - } - - /* Clear the interrupts we are handling */ - - dmabase_putreg(dmachan, STM32_DMA_IFCR_OFFSET, isr); - - return OK; -} - -/**************************************************************************** - * Name: stm32_dma12_setup - * - * Description: - * Configure DMA before using - * - ****************************************************************************/ - -static void stm32_dma12_setup(DMA_HANDLE handle, uint32_t paddr, - uint32_t maddr, size_t ntransfers, - uint32_t ccr) -{ - DMA_CHANNEL dmachan = (DMA_CHANNEL)handle; - uint32_t regval; - - DEBUGASSERT(handle != NULL); - DEBUGASSERT(ntransfers < 65536); - - DEBUGASSERT(dmachan->ctrl == DMA1 || dmachan->ctrl == DMA2); - - dmainfo("paddr: %08" PRIx32 " maddr: %08" PRIx32 - " ntransfers: %zd ccr: %08" PRIx32 "\n", - paddr, maddr, ntransfers, ccr); - -#ifdef CONFIG_STM32_DMACAPABLE - DEBUGASSERT(g_dma_ops[dmachan->ctrl].dma_capable(maddr, ntransfers, ccr)); -#endif - - /* Then DMA_CNDTRx register can only be modified if the DMA channel is - * disabled. - */ - - regval = dmachan_getreg(dmachan, STM32_DMACHAN_CCR_OFFSET); - regval &= ~(DMA_CCR_EN); - dmachan_putreg(dmachan, STM32_DMACHAN_CCR_OFFSET, regval); - - /* Set the peripheral register address in the DMA_CPARx register. The data - * will be moved from/to this address to/from the memory after the - * peripheral event. - */ - - dmachan_putreg(dmachan, STM32_DMACHAN_CPAR_OFFSET, paddr); - - /* Set the memory address in the DMA_CMARx register. The data will be - * written to or read from this memory after the peripheral event. - */ - - dmachan_putreg(dmachan, STM32_DMACHAN_CMAR_OFFSET, maddr); - - /* Configure the total number of data to be transferred in the DMA_CNDTRx - * register. After each peripheral event, this value will be decremented. - */ - - dmachan_putreg(dmachan, STM32_DMACHAN_CNDTR_OFFSET, ntransfers); - - /* Configure the channel priority using the PL[1:0] bits in the DMA_CCRx - * register. Configure data transfer direction, circular mode, peripheral - * & memory incremented mode, peripheral & memory data size, and interrupt - * after half and/or full transfer in the DMA_CCRx register. - */ - - regval = dmachan_getreg(dmachan, STM32_DMACHAN_CCR_OFFSET); - regval &= ~(DMA_CCR_MEM2MEM | DMA_CCR_PL_MASK | DMA_CCR_MSIZE_MASK | - DMA_CCR_PSIZE_MASK | DMA_CCR_MINC | DMA_CCR_PINC | - DMA_CCR_CIRC | DMA_CCR_DIR); - ccr &= (DMA_CCR_MEM2MEM | DMA_CCR_PL_MASK | DMA_CCR_MSIZE_MASK | - DMA_CCR_PSIZE_MASK | DMA_CCR_MINC | DMA_CCR_PINC | - DMA_CCR_CIRC | DMA_CCR_DIR); - regval |= ccr; - dmachan_putreg(dmachan, STM32_DMACHAN_CCR_OFFSET, regval); -} - -/**************************************************************************** - * Name: stm32_dma12_start - * - * Description: - * Start the standard DMA transfer - ****************************************************************************/ - -static void stm32_dma12_start(DMA_HANDLE handle, dma_callback_t callback, - void *arg, bool half) -{ - DMA_CHANNEL dmachan = (DMA_CHANNEL)handle; - uint32_t ccr; - - DEBUGASSERT(dmachan->ctrl == DMA1 || dmachan->ctrl == DMA2); - - /* Save the callback info. This will be invoked when the DMA completes */ - - dmachan->callback = callback; - dmachan->arg = arg; - - /* Activate the channel by setting the ENABLE bit in the DMA_CCRx register. - * As soon as the channel is enabled, it can serve any DMA request from the - * peripheral connected on the channel. - */ - - ccr = dmachan_getreg(dmachan, STM32_DMACHAN_CCR_OFFSET); - ccr |= DMA_CCR_EN; - - /* In normal mode, interrupt at either half or full completion. In circular - * mode, always interrupt on buffer wrap, and optionally interrupt at the - * halfway point. - */ - - if ((ccr & DMA_CCR_CIRC) == 0) - { - /* Once half of the bytes are transferred, the half-transfer flag - * (HTIF) is set and an interrupt is generated if the Half-Transfer - * Interrupt Enable bit (HTIE) is set. At the end of the transfer, - * the Transfer Complete Flag (TCIF) is set and an interrupt is - * generated if the Transfer Complete Interrupt Enable bit (TCIE) - * is set. - */ - - ccr |= (half ? (DMA_CCR_HTIE | DMA_CCR_TEIE) : - (DMA_CCR_TCIE | DMA_CCR_TEIE)); - } - else - { - /* In nonstop mode, when the transfer completes it immediately resets - * and starts again. The transfer-complete interrupt is thus always - * enabled, and the half-complete interrupt can be used in circular - * mode to determine when the buffer is half-full, or in - * double-buffered mode to determine when one of the two buffers - * is full. - */ - - ccr |= (half ? DMA_CCR_HTIE : 0) | DMA_CCR_TCIE | DMA_CCR_TEIE; - } - - dmachan_putreg(dmachan, STM32_DMACHAN_CCR_OFFSET, ccr); -} - -/**************************************************************************** - * Name: stm32_dma12_residual - ****************************************************************************/ - -static size_t stm32_dma12_residual(DMA_HANDLE handle) -{ - DMA_CHANNEL dmachan = (DMA_CHANNEL)handle; - - DEBUGASSERT(dmachan->ctrl == DMA1 || dmachan->ctrl == DMA2); - - return dmachan_getreg(dmachan, STM32_DMACHAN_CNDTR_OFFSET); -} - -/**************************************************************************** - * Name: stm32_dma12_sample - ****************************************************************************/ - -#ifdef CONFIG_DEBUG_DMA_INFO -void stm32_dma12_sample(DMA_HANDLE handle, struct stm32_dmaregs_s *regs) -{ - DMA_CHANNEL dmachan = (DMA_CHANNEL)handle; - irqstate_t flags; - - flags = enter_critical_section(); - - regs->isr = dmabase_getreg(dmachan, STM32_DMA_ISR_OFFSET); - regs->ccr = dmachan_getreg(dmachan, STM32_DMACHAN_CCR_OFFSET); - regs->cndtr = dmachan_getreg(dmachan, STM32_DMACHAN_CNDTR_OFFSET); - regs->cpar = dmachan_getreg(dmachan, STM32_DMACHAN_CPAR_OFFSET); - regs->cmar = dmachan_getreg(dmachan, STM32_DMACHAN_CMAR_OFFSET); - - stm32_dmamux_sample(g_dma[dmachan->ctrl].dmamux, - dmachan->chan + g_dma[dmachan->ctrl].dmamux_offset, - regs); - - leave_critical_section(flags); -} -#endif - -/**************************************************************************** - * Name: stm32_dma12_dump - ****************************************************************************/ - -#ifdef CONFIG_DEBUG_DMA_INFO -static void stm32_dma12_dump(DMA_HANDLE handle, - const struct stm32_dmaregs_s *regs, - const char *msg) -{ - DMA_CHANNEL dmachan = (DMA_CHANNEL)handle; - - DEBUGASSERT(dmachan->ctrl == DMA1 || dmachan->ctrl == DMA2); - - uint32_t dmabase = dmachan_getbase(dmachan); - - dmainfo("DMA%d Registers: %s\n", - dmachan->ctrl + 1, - msg); - dmainfo(" ISR[%08" PRIx32 "]: %08" PRIx32 "\n", - dmabase + STM32_DMA_ISR_OFFSET, - regs->isr); - dmainfo(" CCR[%08" PRIx32 "]: %08" PRIx32 "\n", - dmachan->base + STM32_DMACHAN_CCR_OFFSET, - regs->ccr); - dmainfo(" CNDTR[%08" PRIx32 "]: %08" PRIx32 "\n", - dmachan->base + STM32_DMACHAN_CNDTR_OFFSET, - regs->cndtr); - dmainfo(" CPAR[%08" PRIx32 "]: %08" PRIx32 "\n", - dmachan->base + STM32_DMACHAN_CPAR_OFFSET, - regs->cpar); - dmainfo(" CMAR[%08" PRIx32 "]: %08" PRIx32 "\n", - dmachan->base + STM32_DMACHAN_CMAR_OFFSET, - regs->cmar); - - stm32_dmamux_dump(g_dma[dmachan->ctrl].dmamux, - dmachan->chan + g_dma[dmachan->ctrl].dmamux_offset, - regs); -} -#endif - -#endif /* CONFIG_STM32_DMA1 || CONFIG_STM32_DMA2 */ - -/**************************************************************************** - * Name: stm32_dmamux_sample - ****************************************************************************/ - -#ifdef CONFIG_DEBUG_DMA_INFO -static void stm32_dmamux_sample(DMA_MUX dmamux, uint8_t chan, - struct stm32_dmaregs_s *regs) -{ - regs->dmamux.ccr = dmamux_getreg(dmamux, STM32_DMAMUX_CXCR_OFFSET(chan)); - regs->dmamux.csr = dmamux_getreg(dmamux, STM32_DMAMUX_CSR_OFFSET); - regs->dmamux.rg0cr = dmamux_getreg(dmamux, STM32_DMAMUX_RG0CR_OFFSET); - regs->dmamux.rg1cr = dmamux_getreg(dmamux, STM32_DMAMUX_RG1CR_OFFSET); - regs->dmamux.rg2cr = dmamux_getreg(dmamux, STM32_DMAMUX_RG2CR_OFFSET); - regs->dmamux.rg3cr = dmamux_getreg(dmamux, STM32_DMAMUX_RG3CR_OFFSET); - regs->dmamux.rgsr = dmamux_getreg(dmamux, STM32_DMAMUX_RGSR_OFFSET); -} -#endif - -/**************************************************************************** - * Name: stm32_dmamux_dump - ****************************************************************************/ - -#ifdef CONFIG_DEBUG_DMA_INFO -static void stm32_dmamux_dump(DMA_MUX dmamux, uint8_t channel, - const struct stm32_dmaregs_s *regs) -{ - dmainfo("DMAMUX%d CH=%d\n", dmamux->id, channel); - dmainfo(" CCR[%08" PRIx32 "]: %08" PRIx32 "\n", - dmamux->base + STM32_DMAMUX_CXCR_OFFSET(channel), - regs->dmamux.ccr); - dmainfo(" CSR[%08" PRIx32 "]: %08" PRIx32 "\n", - dmamux->base + STM32_DMAMUX_CSR_OFFSET, regs->dmamux.csr); - dmainfo(" RG0CR[%08" PRIx32 "]: %08" PRIx32 "\n", - dmamux->base + STM32_DMAMUX_RG0CR_OFFSET, regs->dmamux.rg0cr); - dmainfo(" RG1CR[%08" PRIx32 "]: %08" PRIx32 "\n", - dmamux->base + STM32_DMAMUX_RG1CR_OFFSET, regs->dmamux.rg1cr); - dmainfo(" RG2CR[%08" PRIx32 "]: %08" PRIx32 "\n", - dmamux->base + STM32_DMAMUX_RG2CR_OFFSET, regs->dmamux.rg2cr); - dmainfo(" RG3CR[%08" PRIx32 "]: %08" PRIx32 "\n", - dmamux->base + STM32_DMAMUX_RG3CR_OFFSET, regs->dmamux.rg3cr); - dmainfo(" RGSR[%08" PRIx32 "]: %08" PRIx32 "\n", - dmamux->base + STM32_DMAMUX_RGSR_OFFSET, regs->dmamux.rgsr); -}; -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: arm_dma_initialize - * - * Description: - * Initialize the DMA subsystem (DMA1, DMA2) - * - * Returned Value: - * None - * - ****************************************************************************/ - -void weak_function arm_dma_initialize(void) -{ - DMA_CHANNEL dmachan; - uint8_t controller; - int channel; - - dmainfo("Initialize DMA\n"); - - /* Initialize DMA channels */ - - for (channel = 0; channel < DMA_NCHANNELS; channel++) - { - dmachan = &g_dmach[channel]; - - /* Initialize flag */ - - dmachan->used = false; - - /* Get DMA controller associated with channel */ - - controller = dmachan->ctrl; - - DEBUGASSERT(controller >= DMA1 && controller <= DMA2); - - /* Attach standard DMA interrupt vectors */ - - irq_attach(dmachan->irq, g_dma_ops[controller].dma_interrupt, - dmachan); - - /* Disable the DMA channel */ - - g_dma_ops[controller].dma_disable(dmachan); - - /* Enable the IRQ at the NVIC (still disabled at the DMA controller) */ - - up_enable_irq(dmachan->irq); - } -} - -/**************************************************************************** - * Name: stm32_dmachannel - * - * Description: - * Allocate a DMA channel. This function gives the caller mutually - * exclusive access to the DMA channel specified by the 'dmamap' argument. - * It is common for both DMA controllers (DMA1 and DMA2). - * - * Input Parameters: - * dmamap - Identifies the stream/channel resource. For the STM32+, this - * is a bit-encoded value as provided by the DMAMAP_* definitions - * in hardware/stm32g4xxxx_dmamux.h - * - * Returned Value: - * On success, this function returns a non-NULL, void* DMA channel handle. - * NULL is returned on any failure. This function can fail only if no DMA - * channel is available. - * - * Assumptions: - * - The caller does not hold he DMA channel. - * - The caller can wait for the DMA channel to be freed if it is not - * available. - * - ****************************************************************************/ - -DMA_HANDLE stm32_dmachannel(unsigned int dmamap) -{ - DMA_CHANNEL dmachan; - uint8_t dmamux_req; - irqstate_t flags; - uint8_t controller; - uint8_t first = 0; - uint8_t nchan = 0; - int item = -1; - int i; - - /* Get DMA controller from encoded DMAMAP value */ - - controller = DMAMAP_CONTROLLER(dmamap); - DEBUGASSERT(controller >= DMA1 && controller <= DMA2); - - /* Get DMAMUX channel from encoded DMAMAP value */ - - dmamux_req = DMAMAP_REQUEST(dmamap); - - /* Get g_dma array limits for given controller */ - - stm32_gdma_limits_get(controller, &first, &nchan); - - /* Find available channel for given controller */ - - flags = enter_critical_section(); - for (i = first; i < first + nchan; i += 1) - { - if (g_dmach[i].used == false) - { - item = i; - g_dmach[i].used = true; - g_dmach[i].dmamux_req = dmamux_req; - break; - } - } - - leave_critical_section(flags); - - dmainfo("ctrl=%d item=%d\n", controller, item); - - if (item == -1) - { - dmainfo("No available DMA chan for CTRL=%d\n", - controller); - - /* No available channel */ - - return NULL; - } - - /* Assign DMA item */ - - dmachan = &g_dmach[item]; - - dmainfo("Get g_dmach[%d] CTRL=%d CH=%d\n", i, controller, dmachan->chan); - - /* Be sure that we have proper DMA controller */ - - DEBUGASSERT(dmachan->ctrl == controller); - - return (DMA_HANDLE)dmachan; -} - -/**************************************************************************** - * Name: stm32_dmafree - * - * Description: - * Release a DMA channel and unmap DMAMUX if required. - * - * NOTE: The 'handle' used in this argument must NEVER be used again - * until stm32_dmachannel() is called again to re-gain access to the - * channel. - * - * Returned Value: - * None - * - * Assumptions: - * - The caller holds the DMA channel. - * - There is no DMA in progress - * - ****************************************************************************/ - -void stm32_dmafree(DMA_HANDLE handle) -{ - DMA_CHANNEL dmachan = (DMA_CHANNEL)handle; - uint8_t controller; - irqstate_t flags; - - DEBUGASSERT(handle != NULL); - - /* Get DMA controller */ - - controller = dmachan->ctrl; - DEBUGASSERT(controller >= DMA1 && controller <= DMA2); - - dmainfo("Free g_dmach[%d] CTRL=%d CH=%d\n", dmachan - g_dmach, controller, - dmachan->chan); - UNUSED(controller); - - /* Release the channel */ - - flags = enter_critical_section(); - dmachan->used = false; - dmachan->dmamux_req = 0; - leave_critical_section(flags); -} - -/**************************************************************************** - * Name: stm32_dmasetup - * - * Description: - * Configure DMA before using - * - ****************************************************************************/ - -void stm32_dmasetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr, - size_t ntransfers, uint32_t ccr) -{ - DMA_CHANNEL dmachan = (DMA_CHANNEL)handle; - uint8_t controller; - - DEBUGASSERT(handle != NULL); - - /* Get DMA controller */ - - controller = dmachan->ctrl; - DEBUGASSERT(controller >= DMA1 && controller <= DMA2); - - g_dma_ops[controller].dma_setup(handle, paddr, maddr, ntransfers, ccr); -} - -/**************************************************************************** - * Name: stm32_dmastart - * - * Description: - * Start the DMA transfer - * - * Assumptions: - * - DMA handle allocated by stm32_dmachannel() - * - No DMA in progress - * - ****************************************************************************/ - -void stm32_dmastart(DMA_HANDLE handle, dma_callback_t callback, void *arg, - bool half) -{ - DMA_CHANNEL dmachan = (DMA_CHANNEL)handle; - DMA_MUX dmamux; - uint32_t regval; - uint8_t dmamux_chan; - uint8_t controller; - - DEBUGASSERT(handle != NULL); - - /* Get DMA controller */ - - controller = dmachan->ctrl; - DEBUGASSERT(controller >= DMA1 && controller <= DMA2); - - /* Recommended channel configure procedure in reference manual: - * 1. Set and configure the DMA channel y, except enabling the channel y. - * 2. Set and configure the related DMAMUX y channel. - * 3. Last, activate the DMA channel y. - */ - - /* Get DMAMUX associated with DMA controller */ - - dmamux = g_dma[controller].dmamux; - dmamux_chan = dmachan->chan + g_dma[controller].dmamux_offset; - - /* DMAMUX Set DMA channel source */ - - regval = dmachan->dmamux_req << DMAMUX_CCR_DMAREQID_SHIFT; - dmamux_putreg(dmamux, STM32_DMAMUX_CXCR_OFFSET(dmamux_chan), regval); - - /* Enable DMA channel */ - - g_dma_ops[controller].dma_start(handle, callback, arg, half); -} - -/**************************************************************************** - * Name: stm32_dmastop - * - * Description: - * Cancel the DMA. After stm32_dmastop() is called, the DMA channel is - * reset and stm32_dmasetup() must be called before stm32_dmastart() - * can be called again - * - * Assumptions: - * - DMA handle allocated by stm32_dmachannel() - * - ****************************************************************************/ - -void stm32_dmastop(DMA_HANDLE handle) -{ - DMA_CHANNEL dmachan = (DMA_CHANNEL)handle; - DMA_MUX dmamux; - uint8_t dmamux_chan; - uint8_t controller; - - DEBUGASSERT(handle != NULL); - - /* Get DMA controller */ - - controller = dmachan->ctrl; - DEBUGASSERT(controller >= DMA1 && controller <= DMA2); - - /* Get DMAMUX associated with DMA controller */ - - dmamux = g_dma[controller].dmamux; - dmamux_chan = dmachan->chan + g_dma[controller].dmamux_offset; - - /* Disable DMA channel */ - - g_dma_ops[controller].dma_disable(dmachan); - - /* DMAMUX Clear DMA channel source */ - - dmamux_putreg(dmamux, STM32_DMAMUX_CXCR_OFFSET(dmamux_chan), 0); -} - -/**************************************************************************** - * Name: stm32_dmaresidual - * - * Description: - * Read the DMA bytes-remaining register. - * - * Assumptions: - * - DMA handle allocated by stm32_dmachannel() - * - ****************************************************************************/ - -size_t stm32_dmaresidual(DMA_HANDLE handle) -{ - DMA_CHANNEL dmachan = (DMA_CHANNEL)handle; - uint8_t controller; - - DEBUGASSERT(handle != NULL); - - /* Get DMA controller */ - - controller = dmachan->ctrl; - DEBUGASSERT(controller >= DMA1 && controller <= DMA2); - - return g_dma_ops[controller].dma_residual(handle); -} - -/**************************************************************************** - * Name: stm32_dmacapable - * - * Description: - * Check if the DMA controller can transfer data to/from given memory - * address. This depends on the internal connections in the ARM bus matrix - * of the processor. Note that this only applies to memory addresses, it - * will return false for any peripheral address. - * - * Input Parameters: - * cfg - DMA transfer configuration - * - * Returned Value: - * True, if transfer is possible. - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_DMACAPABLE -bool stm32_dmacapable(uint32_t maddr, uint32_t count, uint32_t ccr) -{ - unsigned int msize_shift; - uint32_t transfer_size; - uint32_t mend; - - /* Verify that the address conforms to the memory transfer size. - * Transfers to/from memory performed by the DMA controller are - * required to be aligned to their size. - * - * Datasheet 3.13 claims - * "Access to Flash, SRAM, APB and AHB peripherals as source - * and destination" - */ - - switch (ccr & DMA_CCR_MSIZE_MASK) - { - case DMA_CCR_MSIZE_8BITS: - msize_shift = 0; - break; - - case DMA_CCR_MSIZE_16BITS: - msize_shift = 1; - break; - - case DMA_CCR_MSIZE_32BITS: - msize_shift = 2; - break; - - default: - return false; - } - - transfer_size = 1 << msize_shift; - - if ((maddr & (transfer_size - 1)) != 0) - { - return false; - } - - /* Verify that the transfer is to a memory region that supports DMA. */ - - mend = maddr + (count << msize_shift) - 1; - - if ((maddr & STM32_REGION_MASK) != (mend & STM32_REGION_MASK)) - { - return false; - } - - switch (maddr & STM32_REGION_MASK) - { - case STM32_PERIPH_BASE: - case STM32_FSMC_BASE: - case STM32_FSMC_BANK1: - case STM32_FSMC_BANK2: - case STM32_FSMC_BANK3: - case STM32_QSPI_BANK: - case STM32_SRAM_BASE: - case STM32_SRAM2_BASE: - case STM32_SRAM3_BASE: - case STM32_CODE_BASE: - - /* All RAM and flash is supported */ - - return true; - - default: - - /* Everything else is unsupported by DMA */ - - return false; - } -} -#endif - -/**************************************************************************** - * Name: stm32_dmasample - * - * Description: - * Sample DMA register contents - * - * Assumptions: - * - DMA handle allocated by stm32_dmachannel() - * - ****************************************************************************/ - -#ifdef CONFIG_DEBUG_DMA_INFO -void stm32_dmasample(DMA_HANDLE handle, struct stm32_dmaregs_s *regs) -{ - DMA_CHANNEL dmachan = (DMA_CHANNEL)handle; - uint8_t controller; - - DEBUGASSERT(handle != NULL); - - /* Get DMA controller */ - - controller = dmachan->ctrl; - DEBUGASSERT(controller >= DMA1 && controller <= DMA2); - - g_dma_ops[controller].dma_sample(handle, regs); -} -#endif - -/**************************************************************************** - * Name: stm32_dmadump - * - * Description: - * Dump previously sampled DMA register contents - * - * Assumptions: - * - DMA handle allocated by stm32_dmachannel() - * - ****************************************************************************/ - -#ifdef CONFIG_DEBUG_DMA_INFO -void stm32_dmadump(DMA_HANDLE handle, const struct stm32_dmaregs_s *regs, - const char *msg) -{ - DMA_CHANNEL dmachan = (DMA_CHANNEL)handle; - uint8_t controller; - - DEBUGASSERT(handle != NULL); - - /* Get DMA controller */ - - controller = dmachan->ctrl; - DEBUGASSERT(controller >= DMA1 && controller <= DMA2); - - dmainfo("DMA %d CH%d Registers: %s\n", dmachan->ctrl, dmachan->ctrl, msg); - - g_dma_ops[controller].dma_dump(handle, regs, msg); -} -#endif diff --git a/arch/arm/src/stm32/stm32_dma_v2.c b/arch/arm/src/stm32/stm32_dma_v2.c deleted file mode 100644 index ed3784d53881c..0000000000000 --- a/arch/arm/src/stm32/stm32_dma_v2.c +++ /dev/null @@ -1,1166 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_dma_v2.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -#include "arm_internal.h" -#include "sched/sched.h" -#include "chip.h" -#include "stm32_dma.h" -#include "stm32.h" - -/* This file supports the STM32 DMA IP core version 2 - F2, F4, F7, H7 - * NOTE: F7 and H7 need support for DCACHE which is not implemented here - * but otherwise DMA IP cores look the same. - */ - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#define DMA1_NSTREAMS 8 -#if STM32_NDMA > 1 -# define DMA2_NSTREAMS 8 -# define DMA_NSTREAMS (DMA1_NSTREAMS+DMA2_NSTREAMS) -#else -# define DMA_NSTREAMS DMA1_NSTREAMS -#endif - -/* Convert the DMA stream base address to the DMA register block address */ - -#define DMA_BASE(ch) (ch & 0xfffffc00) - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/* This structure describes one DMA channel */ - -struct stm32_dma_s -{ - uint8_t stream; /* DMA stream number (0-7) */ - uint8_t irq; /* DMA stream IRQ number */ - uint8_t shift; /* ISR/IFCR bit shift value */ - uint8_t channel; /* DMA channel number (0-7) */ - sem_t sem; /* Used to wait for DMA channel to become available */ - uint32_t base; /* DMA register channel base address */ - dma_callback_t callback; /* Callback invoked when the DMA completes */ - void *arg; /* Argument passed to callback function */ -}; - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* This array describes the state of each DMA */ - -static struct stm32_dma_s g_dma[DMA_NSTREAMS] = -{ - { - .stream = 0, - .irq = STM32_IRQ_DMA1S0, - .shift = DMA_INT_STREAM0_SHIFT, - .sem = SEM_INITIALIZER(1), - .base = STM32_DMA1_BASE + STM32_DMA_OFFSET(0), - }, - { - .stream = 1, - .irq = STM32_IRQ_DMA1S1, - .shift = DMA_INT_STREAM1_SHIFT, - .sem = SEM_INITIALIZER(1), - .base = STM32_DMA1_BASE + STM32_DMA_OFFSET(1), - }, - { - .stream = 2, - .irq = STM32_IRQ_DMA1S2, - .shift = DMA_INT_STREAM2_SHIFT, - .sem = SEM_INITIALIZER(1), - .base = STM32_DMA1_BASE + STM32_DMA_OFFSET(2), - }, - { - .stream = 3, - .irq = STM32_IRQ_DMA1S3, - .shift = DMA_INT_STREAM3_SHIFT, - .sem = SEM_INITIALIZER(1), - .base = STM32_DMA1_BASE + STM32_DMA_OFFSET(3), - }, - { - .stream = 4, - .irq = STM32_IRQ_DMA1S4, - .shift = DMA_INT_STREAM4_SHIFT, - .sem = SEM_INITIALIZER(1), - .base = STM32_DMA1_BASE + STM32_DMA_OFFSET(4), - }, - { - .stream = 5, - .irq = STM32_IRQ_DMA1S5, - .shift = DMA_INT_STREAM5_SHIFT, - .sem = SEM_INITIALIZER(1), - .base = STM32_DMA1_BASE + STM32_DMA_OFFSET(5), - }, - { - .stream = 6, - .irq = STM32_IRQ_DMA1S6, - .shift = DMA_INT_STREAM6_SHIFT, - .sem = SEM_INITIALIZER(1), - .base = STM32_DMA1_BASE + STM32_DMA_OFFSET(6), - }, - { - .stream = 7, - .irq = STM32_IRQ_DMA1S7, - .shift = DMA_INT_STREAM7_SHIFT, - .sem = SEM_INITIALIZER(1), - .base = STM32_DMA1_BASE + STM32_DMA_OFFSET(7), - }, -#if STM32_NDMA > 1 - { - .stream = 0, - .irq = STM32_IRQ_DMA2S0, - .shift = DMA_INT_STREAM0_SHIFT, - .sem = SEM_INITIALIZER(1), - .base = STM32_DMA2_BASE + STM32_DMA_OFFSET(0), - }, - { - .stream = 1, - .irq = STM32_IRQ_DMA2S1, - .shift = DMA_INT_STREAM1_SHIFT, - .sem = SEM_INITIALIZER(1), - .base = STM32_DMA2_BASE + STM32_DMA_OFFSET(1), - }, - { - .stream = 2, - .irq = STM32_IRQ_DMA2S2, - .shift = DMA_INT_STREAM2_SHIFT, - .sem = SEM_INITIALIZER(1), - .base = STM32_DMA2_BASE + STM32_DMA_OFFSET(2), - }, - { - .stream = 3, - .irq = STM32_IRQ_DMA2S3, - .shift = DMA_INT_STREAM3_SHIFT, - .sem = SEM_INITIALIZER(1), - .base = STM32_DMA2_BASE + STM32_DMA_OFFSET(3), - }, - { - .stream = 4, - .irq = STM32_IRQ_DMA2S4, - .sem = SEM_INITIALIZER(1), - .base = STM32_DMA2_BASE + STM32_DMA_OFFSET(4), - }, - { - .stream = 5, - .irq = STM32_IRQ_DMA2S5, - .shift = DMA_INT_STREAM5_SHIFT, - .sem = SEM_INITIALIZER(1), - .base = STM32_DMA2_BASE + STM32_DMA_OFFSET(5), - }, - { - .stream = 6, - .irq = STM32_IRQ_DMA2S6, - .shift = DMA_INT_STREAM6_SHIFT, - .sem = SEM_INITIALIZER(1), - .base = STM32_DMA2_BASE + STM32_DMA_OFFSET(6), - }, - { - .stream = 7, - .irq = STM32_IRQ_DMA2S7, - .shift = DMA_INT_STREAM7_SHIFT, - .sem = SEM_INITIALIZER(1), - .base = STM32_DMA2_BASE + STM32_DMA_OFFSET(7), - }, -#endif -}; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * DMA register access functions - ****************************************************************************/ - -/* Get non-channel register from DMA1 or DMA2 */ - -static inline uint32_t dmabase_getreg(struct stm32_dma_s *dmast, - uint32_t offset) -{ - return getreg32(DMA_BASE(dmast->base) + offset); -} - -/* Write to non-channel register in DMA1 or DMA2 */ - -static inline void dmabase_putreg(struct stm32_dma_s *dmast, uint32_t offset, - uint32_t value) -{ - putreg32(value, DMA_BASE(dmast->base) + offset); -} - -/* Get channel register from DMA1 or DMA2 */ - -static inline uint32_t dmast_getreg(struct stm32_dma_s *dmast, - uint32_t offset) -{ - return getreg32(dmast->base + offset); -} - -/* Write to channel register in DMA1 or DMA2 */ - -static inline void dmast_putreg(struct stm32_dma_s *dmast, uint32_t offset, - uint32_t value) -{ - putreg32(value, dmast->base + offset); -} - -static inline void dmast_modifyreg32(struct stm32_dma_s *dmast, - uint32_t offset, uint32_t clrbits, - uint32_t setbits) -{ - modifyreg32(dmast->base + offset, clrbits, setbits); -} - -/**************************************************************************** - * Name: stm32_dmastream - * - * Description: - * Get the g_dma table entry associated with a DMA controller and a stream - * number - * - ****************************************************************************/ - -static inline struct stm32_dma_s *stm32_dmastream(unsigned int stream, - unsigned int controller) -{ - int index; - - DEBUGASSERT(stream < DMA_NSTREAMS && controller < STM32_NDMA); - - /* Convert the controller + stream based on the fact that there are - * 8 streams per controller. - */ - -#if STM32_NDMA > 1 - index = controller << 3 | stream; -#else - index = stream; -#endif - - /* Then return the stream structure associated with the stream index */ - - return &g_dma[index]; -} - -/**************************************************************************** - * Name: stm32_dmamap - * - * Description: - * Get the g_dma table entry associated with a bit-encoded DMA selection - * - ****************************************************************************/ - -static inline struct stm32_dma_s *stm32_dmamap(unsigned long dmamap) -{ - /* Extract the DMA controller number from the bit encoded value */ - - unsigned int controller = STM32_DMA_CONTROLLER(dmamap); - - /* Extract the stream number from the bit encoded value */ - - unsigned int stream = STM32_DMA_STREAM(dmamap); - - /* Return the table entry associated with the controller + stream */ - - return stm32_dmastream(stream, controller); -} - -/**************************************************************************** - * Name: stm32_dmastreamdisable - * - * Description: - * Disable the DMA stream - * - ****************************************************************************/ - -static void stm32_dmastreamdisable(struct stm32_dma_s *dmast) -{ - uint32_t regoffset; - uint32_t regval; - - /* Disable all interrupts at the DMA controller */ - - regval = dmast_getreg(dmast, STM32_DMA_SCR_OFFSET); - regval &= ~DMA_SCR_ALLINTS; - - /* Disable the DMA stream */ - - regval &= ~DMA_SCR_EN; - dmast_putreg(dmast, STM32_DMA_SCR_OFFSET, regval); - - /* Clear pending stream interrupts by setting bits in the upper or lower - * IFCR register. - */ - - if (dmast->stream < 4) - { - regoffset = STM32_DMA_LIFCR_OFFSET; - } - else - { - regoffset = STM32_DMA_HIFCR_OFFSET; - } - - dmabase_putreg(dmast, regoffset, (DMA_STREAM_MASK << dmast->shift)); -} - -/**************************************************************************** - * Name: stm32_dmainterrupt - * - * Description: - * DMA interrupt handler - * - ****************************************************************************/ - -static int stm32_dmainterrupt(int irq, void *context, void *arg) -{ - struct stm32_dma_s *dmast; - uint32_t status; - uint32_t regoffset = 0; - unsigned int stream = 0; - unsigned int controller = 0; - - /* Get the stream and the controller that generated the interrupt */ - - if (irq >= STM32_IRQ_DMA1S0 && irq <= STM32_IRQ_DMA1S6) - { - stream = irq - STM32_IRQ_DMA1S0; - controller = DMA1; - } - else if (irq == STM32_IRQ_DMA1S7) - { - stream = 7; - controller = DMA1; - } - else -#if STM32_NDMA > 1 - if (irq >= STM32_IRQ_DMA2S0 && irq <= STM32_IRQ_DMA2S4) - { - stream = irq - STM32_IRQ_DMA2S0; - controller = DMA2; - } - else if (irq >= STM32_IRQ_DMA2S5 && irq <= STM32_IRQ_DMA2S7) - { - stream = irq - STM32_IRQ_DMA2S5 + 5; - controller = DMA2; - } - else -#endif - { - DEBUGPANIC(); - } - - /* Get the stream structure from the stream and controller numbers */ - - dmast = stm32_dmastream(stream, controller); - - /* Select the interrupt status register (either the LISR or HISR) - * based on the stream number that caused the interrupt. - */ - - if (stream < 4) - { - regoffset = STM32_DMA_LISR_OFFSET; - } - else - { - regoffset = STM32_DMA_HISR_OFFSET; - } - - /* Get the interrupt status for this stream */ - - status = (dmabase_getreg(dmast, regoffset) >> dmast->shift) & - DMA_STREAM_MASK; - - /* Clear fetched stream interrupts by setting bits in the upper or lower - * IFCR register. - */ - - if (stream < 4) - { - regoffset = STM32_DMA_LIFCR_OFFSET; - } - else - { - regoffset = STM32_DMA_HIFCR_OFFSET; - } - - dmabase_putreg(dmast, regoffset, (status << dmast->shift)); - - /* Invoke the callback */ - - if (dmast->callback) - { - dmast->callback(dmast, status, dmast->arg); - } - - return OK; -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_dmainitialize - * - * Description: - * Initialize the DMA subsystem - * - * Returned Value: - * None - * - ****************************************************************************/ - -void weak_function arm_dma_initialize(void) -{ - struct stm32_dma_s *dmast; - int stream; - - /* Initialize each DMA stream */ - - for (stream = 0; stream < DMA_NSTREAMS; stream++) - { - dmast = &g_dma[stream]; - - /* Attach DMA interrupt vectors */ - - irq_attach(dmast->irq, stm32_dmainterrupt, dmast); - - /* Disable the DMA stream */ - - stm32_dmastreamdisable(dmast); - - /* Enable the IRQ at the NVIC (still disabled at the DMA controller) */ - - up_enable_irq(dmast->irq); - } -} - -/**************************************************************************** - * Name: stm32_dmachannel - * - * Description: - * Allocate a DMA channel. This function gives the caller mutually - * exclusive access to the DMA channel specified by the 'dmamap' argument. - * DMA channels are shared on the STM32: Devices sharing the same DMA - * channel cannot do DMA concurrently! See the DMACHAN_* definitions in - * stm32_dma.h. - * - * If the DMA channel is not available, then stm32_dmachannel() will wait - * until the holder of the channel relinquishes the channel by calling - * stm32_dmafree(). WARNING: If you have two devices sharing a DMA - * channel and the code never releases the channel, the stm32_dmachannel - * call for the other will hang forever in this function! Don't let your - * design do that! - * - * Hmm.. I suppose this interface could be extended to make a non-blocking - * version. Feel free to do that if that is what you need. - * - * Input Parameters: - * dmamap - Identifies the stream/channel resource. For the STM32 F4, this - * is a bit-encoded value as provided by the DMAMAP_* definitions - * in chip/stm32f40xxx_dma.h - * - * Returned Value: - * Provided that 'dmamap' is valid, this function ALWAYS returns a non-NULL - * void* DMA channel handle. (If 'dmamap' is invalid, the function will - * assert if debug is enabled or do something ignorant otherwise). - * - * Assumptions: - * - The caller does not hold he DMA channel. - * - The caller can wait for the DMA channel to be freed if it is no - * available. - * - ****************************************************************************/ - -DMA_HANDLE stm32_dmachannel(unsigned int dmamap) -{ - struct stm32_dma_s *dmast; - int ret; - - /* Get the stream index from the bit-encoded channel value */ - - dmast = stm32_dmamap(dmamap); - DEBUGASSERT(dmast != NULL); - - /* Get exclusive access to the DMA channel -- OR wait until the channel - * is available if it is currently being used by another driver - */ - - ret = nxsem_wait_uninterruptible(&dmast->sem); - if (ret < 0) - { - return NULL; - } - - /* The caller now has exclusive use of the DMA channel. Assign the - * channel to the stream and return an opaque reference to the stream - * structure. - */ - - dmast->channel = STM32_DMA_CHANNEL(dmamap); - return (DMA_HANDLE)dmast; -} - -/**************************************************************************** - * Name: stm32_dmafree - * - * Description: - * Release a DMA channel. If another thread is waiting for this DMA - * channel in a call to stm32_dmachannel, then this function will re-assign - * the DMA channel to that thread and wake it up. NOTE: The 'handle' used - * in this argument must NEVER be used again until stm32_dmachannel() is - * called again to re-gain access to the channel. - * - * Returned Value: - * None - * - * Assumptions: - * - The caller holds the DMA channel. - * - There is no DMA in progress - * - ****************************************************************************/ - -void stm32_dmafree(DMA_HANDLE handle) -{ - struct stm32_dma_s *dmast = (struct stm32_dma_s *)handle; - - DEBUGASSERT(handle != NULL); - - /* Release the channel */ - - nxsem_post(&dmast->sem); -} - -/**************************************************************************** - * Name: stm32_dmasetup - * - * Description: - * Configure DMA before using - * - ****************************************************************************/ - -void stm32_dmasetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr, - size_t ntransfers, uint32_t scr) -{ - struct stm32_dma_s *dmast = (struct stm32_dma_s *)handle; - uint32_t regoffset; - uint32_t regval; - uint32_t timeout; - - dmainfo("paddr: %08" PRIx32 " maddr: %08" PRIx32 - " ntransfers: %zu scr: %08" PRIx32 "\n", - paddr, maddr, ntransfers, scr); - -#ifdef CONFIG_STM32_DMACAPABLE - DEBUGASSERT(stm32_dmacapable(maddr, ntransfers, scr)); -#endif - - /* "If the stream is enabled, disable it by resetting the EN bit in the - * DMA_SxCR register, then read this bit in order to confirm that there is - * no ongoing stream operation. Writing this bit to 0 is not immediately - * effective since it is actually written to 0 once all the current - * transfers have finished. When the EN bit is read as 0, this means that - * the stream is ready to be configured. It is therefore necessary to wait - * for the EN bit to be cleared before starting any stream - * configuration. ..." - */ - - /* Drivers using DMA should manage the streams. If a DMA request - * is not made on an error or an abort occurs. The driver should - * stop the DMA. If it fails to do so we can not just hang waiting - * on the HW that will not change state. - * - * If at the end of waiting the HW is still not ready there is a HW problem - * or a SW usage problem. - * - * Enable DEBUGASSERT to detect this. - */ - - if ((dmast_getreg(dmast, STM32_DMA_SCR_OFFSET) & DMA_SCR_EN) != 0) - { - /* Attempt to disable the DMA stream and wait up to a 100 us for it - * to stop. - */ - - dmast_modifyreg32(dmast, STM32_DMA_SCR_OFFSET, DMA_SCR_EN, 0); - timeout = 100; - while (timeout != 0 && - (dmast_getreg(dmast, STM32_DMA_SCR_OFFSET) & DMA_SCR_EN) != 0) - { - up_udelay(1); - timeout--; - } - - DEBUGASSERT(timeout != 0 && - (dmast_getreg(dmast, STM32_DMA_SCR_OFFSET) & - DMA_SCR_EN) == 0); - } - - /* "... All the stream dedicated bits set in the status register (DMA_LISR - * and DMA_HISR) from the previous data block DMA transfer should be - * cleared before the stream can be re-enabled." - * - * Clear pending stream interrupts by setting bits in the upper or lower - * IFCR register. - */ - - if (dmast->stream < 4) - { - regoffset = STM32_DMA_LIFCR_OFFSET; - } - else - { - regoffset = STM32_DMA_HIFCR_OFFSET; - } - - dmabase_putreg(dmast, regoffset, (DMA_STREAM_MASK << dmast->shift)); - - /* "Set the peripheral register address in the DMA_SPARx register. The data - * will be moved from/to this address to/from the memory after the - * peripheral event. - */ - - dmast_putreg(dmast, STM32_DMA_SPAR_OFFSET, paddr); - - /* "Set the memory address in the DMA_SM0ARx ... register. The data will be - * written to or read from this memory after the peripheral event." - * - * Note that in double-buffered mode it is explicitly assumed that the - * second buffer immediately follows the first. - */ - - dmast_putreg(dmast, STM32_DMA_SM0AR_OFFSET, maddr); - if (scr & DMA_SCR_DBM) - { - dmast_putreg(dmast, STM32_DMA_SM1AR_OFFSET, maddr + ntransfers); - } - - /* "Configure the total number of data items to be transferred in the - * DMA_SNDTRx register. After each peripheral event, this value will be - * decremented." - * - * "When the peripheral flow controller is used for a given stream, - * the value written into the DMA_SxNDTR has no effect on the DMA - * transfer. Actually, whatever the value written, it will be forced by - * hardware to 0xFFFF as soon as the stream is enabled..." - */ - - dmast_putreg(dmast, STM32_DMA_SNDTR_OFFSET, ntransfers); - - /* "Select the DMA channel (request) using CHSEL[2:0] in the DMA_SxCR - * register." - * - * "Configure the stream priority using the PL[1:0] bits in the DMA_SCRx" - * register." - */ - - regval = dmast_getreg(dmast, STM32_DMA_SCR_OFFSET); - regval &= ~(DMA_SCR_PL_MASK | DMA_SCR_CHSEL_MASK); - regval |= scr & DMA_SCR_PL_MASK; - regval |= (uint32_t)dmast->channel << DMA_SCR_CHSEL_SHIFT; - dmast_putreg(dmast, STM32_DMA_SCR_OFFSET, regval); - - /* "Configure the FIFO usage (enable or disable, threshold in transmission - * and reception)" - * - * "Caution is required when choosing the FIFO threshold (bits FTH[1:0] of - * the DMA_SxFCR register) and the size of the memory burst (MBURST[1:0] - * of the DMA_SxCR register): The content pointed by the FIFO threshold - * must exactly match to an integer number of memory burst transfers. - * If this is not in the case, a FIFO error (flag FEIFx of the DMA_HISR - * or DMA_LISR register) will be generated when the stream is enabled, - * then the stream will be automatically disabled." - * - * The FIFO is disabled in circular mode when transferring data from a - * peripheral to memory, as in this case it is usually desirable to know - * that every byte from the peripheral is transferred immediately to memory - * It is not practical to flush the DMA FIFO, as this requires disabling - * the channel which triggers the transfer-complete interrupt. - * - * NOTE: The FEIFx error interrupt is not enabled because the FEIFx seems - * to be reported spuriously causing good transfers to be marked as - * failures. - */ - - regval = dmast_getreg(dmast, STM32_DMA_SFCR_OFFSET); - regval &= ~(DMA_SFCR_FTH_MASK | DMA_SFCR_FS_MASK | DMA_SFCR_FEIE); - if (!((scr & (DMA_SCR_CIRC | DMA_SCR_DIR_MASK)) == - (DMA_SCR_CIRC | DMA_SCR_DIR_P2M))) - { - regval |= (DMA_SFCR_FTH_FULL | DMA_SFCR_DMDIS); - } - - dmast_putreg(dmast, STM32_DMA_SFCR_OFFSET, regval); - - /* "Configure data transfer direction, circular mode, peripheral & memory - * incremented mode, peripheral & memory data size, and interrupt after - * half and/or full transfer in the DMA_CCRx register." - * - * Note: The CT bit is always reset. - */ - - regval = dmast_getreg(dmast, STM32_DMA_SCR_OFFSET); - regval &= ~(DMA_SCR_PFCTRL | DMA_SCR_DIR_MASK | DMA_SCR_PINC | - DMA_SCR_MINC | DMA_SCR_PSIZE_MASK | DMA_SCR_MSIZE_MASK | - DMA_SCR_PINCOS | DMA_SCR_CIRC | DMA_SCR_DBM | DMA_SCR_CT | - DMA_SCR_PBURST_MASK | DMA_SCR_MBURST_MASK); - scr &= (DMA_SCR_PFCTRL | DMA_SCR_DIR_MASK | DMA_SCR_PINC | - DMA_SCR_MINC | DMA_SCR_PSIZE_MASK | DMA_SCR_MSIZE_MASK | - DMA_SCR_PINCOS | DMA_SCR_DBM | DMA_SCR_CIRC | - DMA_SCR_PBURST_MASK | DMA_SCR_MBURST_MASK); - regval |= scr; - dmast_putreg(dmast, STM32_DMA_SCR_OFFSET, regval); -} - -/**************************************************************************** - * Name: stm32_dmastart - * - * Description: - * Start the DMA transfer - * - * Assumptions: - * - DMA handle allocated by stm32_dmachannel() - * - No DMA in progress - * - ****************************************************************************/ - -void stm32_dmastart(DMA_HANDLE handle, dma_callback_t callback, void *arg, - bool half) -{ - struct stm32_dma_s *dmast = (struct stm32_dma_s *)handle; - uint32_t scr; - - DEBUGASSERT(handle != NULL); - - /* Save the callback info. This will be invoked when the DMA completes. */ - - dmast->callback = callback; - dmast->arg = arg; - - /* Activate the stream by setting the ENABLE bit in the DMA_SCRx register. - * As soon as the stream is enabled, it can serve any DMA request from the - * peripheral connected on the stream. - */ - - scr = dmast_getreg(dmast, STM32_DMA_SCR_OFFSET); - scr |= DMA_SCR_EN; - - /* In normal mode, interrupt at either half or full completion. In circular - * and double-buffered modes, always interrupt on buffer wrap, and - * optionally interrupt at the halfway point. - */ - - if ((scr & (DMA_SCR_DBM | DMA_SCR_CIRC)) == 0) - { - /* Once half of the bytes are transferred, the half-transfer flag - * (HTIF) is set and an interrupt is generated if the Half-Transfer - * Interrupt Enable bit (HTIE) is set. At the end of the transfer, - * the Transfer Complete Flag (TCIF) is set and an interrupt is - * generated if the Transfer Complete Interrupt Enable bit (TCIE) - * is set. - */ - - scr |= (half ? - (DMA_SCR_HTIE | DMA_SCR_TEIE) : (DMA_SCR_TCIE | DMA_SCR_TEIE)); - } - else - { - /* In non-stop modes, when the transfer completes it immediately resets - * and starts again. The transfer-complete interrupt is thus always - * enabled, and the half-complete interrupt can be used in circular - * mode to determine when the buffer is half-full or in double-buffered - * mode to determine when one of the two buffers is full. - */ - - scr |= (half ? DMA_SCR_HTIE : 0) | DMA_SCR_TCIE | DMA_SCR_TEIE; - } - - dmast_putreg(dmast, STM32_DMA_SCR_OFFSET, scr); -} - -/**************************************************************************** - * Name: stm32_dmastop - * - * Description: - * Cancel the DMA. After stm32_dmastop() is called, the DMA channel is - * reset and stm32_dmasetup() must be called before stm32_dmastart() can be - * called again - * - * Assumptions: - * - DMA handle allocated by stm32_dmachannel() - * - ****************************************************************************/ - -void stm32_dmastop(DMA_HANDLE handle) -{ - struct stm32_dma_s *dmast = (struct stm32_dma_s *)handle; - stm32_dmastreamdisable(dmast); -} - -/**************************************************************************** - * Name: stm32_dmaresidual - * - * Description: - * Read the DMA bytes-remaining register. - * - * Assumptions: - * - DMA handle allocated by stm32_dmachannel() - * - ****************************************************************************/ - -size_t stm32_dmaresidual(DMA_HANDLE handle) -{ - struct stm32_dma_s *dmast = (struct stm32_dma_s *)handle; - uint32_t residual; - - /* Fetch the count of bytes remaining to be transferred. - * - * If the FIFO is enabled, this count may be inaccurate. ST don't - * appear to document whether this counts the peripheral or the memory - * side of the channel, and they don't make the memory pointer - * available either. - * - * For reception in circular mode the FIFO is disabled in order that - * this value can be useful. - */ - - residual = dmast_getreg(dmast, STM32_DMA_SNDTR_OFFSET); - - return (size_t)residual; -} - -/**************************************************************************** - * Name: stm32_dmacapable - * - * Description: - * Check if the DMA controller can transfer data to/from given memory - * address. This depends on the internal connections in the ARM bus matrix - * of the processor. Note that this only applies to memory addresses, it - * will return false for any peripheral address. - * - * Returned Value: - * True, if transfer is possible. - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_DMACAPABLE -bool stm32_dmacapable(uintptr_t maddr, uint32_t count, uint32_t ccr) -{ - uint32_t transfer_size; - uint32_t burst_length; - uint32_t mend; - - dmainfo("stm32_dmacapable: 0x%08" PRIxPTR "/%" PRIu32 " 0x%08" PRIx32 "\n", - maddr, count, ccr); - - /* Verify that the address conforms to the memory transfer size. - * Transfers to/from memory performed by the DMA controller are - * required to be aligned to their size. - * - * See ST RM0090 rev4, section 9.3.11 - * - * Compute mend inline to avoid a possible non-constant integer - * multiply. - */ - - switch (ccr & DMA_SCR_MSIZE_MASK) - { - case DMA_SCR_MSIZE_8BITS: - transfer_size = 1; - mend = maddr + count - 1; - break; - - case DMA_SCR_MSIZE_16BITS: - transfer_size = 2; - mend = maddr + (count << 1) - 1; - break; - - case DMA_SCR_MSIZE_32BITS: - transfer_size = 4; - mend = maddr + (count << 2) - 1; - break; - - default: - dmainfo("stm32_dmacapable: bad transfer size in CCR\n"); - return false; - } - - if ((maddr & (transfer_size - 1)) != 0) - { - dmainfo("stm32_dmacapable: transfer unaligned\n"); - return false; - } - - /* Verify that burst transfers do not cross a 1KiB boundary. */ - - if ((maddr / 1024) != (mend / 1024)) - { - /* The transfer as a whole crosses a 1KiB boundary. - * Verify that no burst does by asserting that the address - * is aligned to the burst length. - */ - - switch (ccr & DMA_SCR_MBURST_MASK) - { - case DMA_SCR_MBURST_SINGLE: - burst_length = transfer_size; - break; - - case DMA_SCR_MBURST_INCR4: - burst_length = transfer_size << 2; - break; - - case DMA_SCR_MBURST_INCR8: - burst_length = transfer_size << 3; - break; - - case DMA_SCR_MBURST_INCR16: - burst_length = transfer_size << 4; - break; - - default: - dmainfo("stm32_dmacapable: bad burst size in CCR\n"); - return false; - } - - if ((maddr & (burst_length - 1)) != 0) - { - dmainfo("stm32_dmacapable: burst crosses 1KiB\n"); - return false; - } - } - - /* Verify that the transfer is to a memory region that supports DMA. */ - - if ((maddr & STM32_REGION_MASK) != (mend & STM32_REGION_MASK)) - { - dmainfo("stm32_dmacapable: transfer crosses memory region\n"); - return false; - } - - switch (maddr & STM32_REGION_MASK) - { - case STM32_FSMC_BANK1: - case STM32_FSMC_BANK2: - case STM32_FSMC_BANK3: - case STM32_FSMC_BANK4: - case STM32_SRAM_BASE: - - /* All RAM is supported */ - - break; - - case STM32_CODE_BASE: - - /* Everything except the CCM ram is supported */ - - if (maddr >= STM32_CCMRAM_BASE && - (maddr - STM32_CCMRAM_BASE) < 65536) - { - dmainfo("stm32_dmacapable: transfer targets CCMRAM\n"); - return false; - } - - break; - - default: - - /* Everything else is unsupported by DMA */ - - dmainfo("stm32_dmacapable:" - " transfer targets unknown/unsupported region\n"); - return false; - } - - dmainfo("stm32_dmacapable: transfer OK\n"); - return true; -} -#endif - -/**************************************************************************** - * Name: stm32_dmasample - * - * Description: - * Sample DMA register contents - * - * Assumptions: - * - DMA handle allocated by stm32_dmachannel() - * - ****************************************************************************/ - -#ifdef CONFIG_DEBUG_DMA_INFO -void stm32_dmasample(DMA_HANDLE handle, struct stm32_dmaregs_s *regs) -{ - struct stm32_dma_s *dmast = (struct stm32_dma_s *)handle; - irqstate_t flags; - - flags = enter_critical_section(); - regs->lisr = dmabase_getreg(dmast, STM32_DMA_LISR_OFFSET); - regs->hisr = dmabase_getreg(dmast, STM32_DMA_HISR_OFFSET); - regs->scr = dmast_getreg(dmast, STM32_DMA_SCR_OFFSET); - regs->sndtr = dmast_getreg(dmast, STM32_DMA_SNDTR_OFFSET); - regs->spar = dmast_getreg(dmast, STM32_DMA_SPAR_OFFSET); - regs->sm0ar = dmast_getreg(dmast, STM32_DMA_SM0AR_OFFSET); - regs->sm1ar = dmast_getreg(dmast, STM32_DMA_SM1AR_OFFSET); - regs->sfcr = dmast_getreg(dmast, STM32_DMA_SFCR_OFFSET); - leave_critical_section(flags); -} -#endif - -/**************************************************************************** - * Name: stm32_dmadump - * - * Description: - * Dump previously sampled DMA register contents - * - * Assumptions: - * - DMA handle allocated by stm32_dmachannel() - * - ****************************************************************************/ - -#ifdef CONFIG_DEBUG_DMA_INFO -void stm32_dmadump(DMA_HANDLE handle, const struct stm32_dmaregs_s *regs, - const char *msg) -{ - struct stm32_dma_s *dmast = (struct stm32_dma_s *)handle; - uint32_t dmabase = DMA_BASE(dmast->base); - - dmainfo("DMA Registers: %s\n", msg); - dmainfo(" LISR[%08" PRIx32 "]: %08" PRIx32 "\n", - dmabase + STM32_DMA_LISR_OFFSET, regs->lisr); - dmainfo(" HISR[%08" PRIx32 "]: %08" PRIx32 "\n", - dmabase + STM32_DMA_HISR_OFFSET, regs->hisr); - dmainfo(" SCR[%08" PRIx32 "]: %08" PRIx32 "\n", - dmast->base + STM32_DMA_SCR_OFFSET, regs->scr); - dmainfo(" SNDTR[%08" PRIx32 "]: %08" PRIx32 "\n", - dmast->base + STM32_DMA_SNDTR_OFFSET, regs->sndtr); - dmainfo(" SPAR[%08" PRIx32 "]: %08" PRIx32 "\n", - dmast->base + STM32_DMA_SPAR_OFFSET, regs->spar); - dmainfo(" SM0AR[%08" PRIx32 "]: %08" PRIx32 "\n", - dmast->base + STM32_DMA_SM0AR_OFFSET, regs->sm0ar); - dmainfo(" SM1AR[%08" PRIx32 "]: %08" PRIx32 "\n", - dmast->base + STM32_DMA_SM1AR_OFFSET, regs->sm1ar); - dmainfo(" SFCR[%08" PRIx32 "]: %08" PRIx32 "\n", - dmast->base + STM32_DMA_SFCR_OFFSET, regs->sfcr); -} -#endif - -#ifdef CONFIG_ARCH_HIPRI_INTERRUPT - -/**************************************************************************** - * Name: stm32_dma_intack - * - * Description: - * Public visible interface to acknowledge interrupts on DMA stream - * - ****************************************************************************/ - -void stm32_dma_intack(unsigned int controller, uint8_t stream, uint32_t isr) -{ - struct stm32_dma_s *dmast = stm32_dmastream(stream, controller); - uint32_t regval = 0; - uint32_t offset = 0; - - /* Select the interrupt flag clear register (either the LIFCR or HIFCR) - * based on the stream number - */ - - if (stream < 4) - { - offset = STM32_DMA_LIFCR_OFFSET; - } - else - { - offset = STM32_DMA_HIFCR_OFFSET; - } - - /* Get value to write */ - - regval |= ((isr & DMA_STREAM_MASK) << dmast->shift); - - /* Write register */ - - dmabase_putreg(dmast, offset, regval); -} - -/**************************************************************************** - * Name: stm32_dma_intget - * - * Description: - * Public visible interface to get pending interrupts from DMA stream - * - ****************************************************************************/ - -uint8_t stm32_dma_intget(unsigned int controller, uint8_t stream) -{ - struct stm32_dma_s *dmast = stm32_dmastream(stream, controller); - uint32_t regval = 0; - uint32_t offset = 0; - - /* Select the interrupt status register (either the LISR or HISR) - * based on the stream number - */ - - if (stream < 4) - { - offset = STM32_DMA_LISR_OFFSET; - } - else - { - offset = STM32_DMA_HISR_OFFSET; - } - - /* Get register value */ - - regval = dmabase_getreg(dmast, offset); - - /* Get stream status */ - - regval = ((regval >> dmast->shift) & DMA_STREAM_MASK); - - return (uint8_t)regval; -} -#endif /* CONFIG_ARCH_HIPRI_INTERRUPT */ diff --git a/arch/arm/src/stm32/stm32_dumpgpio.c b/arch/arm/src/stm32/stm32_dumpgpio.c deleted file mode 100644 index 1f21684650bad..0000000000000 --- a/arch/arm/src/stm32/stm32_dumpgpio.c +++ /dev/null @@ -1,263 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_dumpgpio.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -/* Output debug info even if debug output is not selected. */ - -#undef CONFIG_DEBUG_INFO -#define CONFIG_DEBUG_INFO 1 - -#include -#include - -#include -#include - -#include "arm_internal.h" -#include "chip.h" -#include "stm32_gpio.h" -#include "stm32_rcc.h" - -#ifdef CONFIG_DEBUG_FEATURES - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* Port letters for prettier debug output */ - -static const char g_portchar[STM32_NGPIO_PORTS] = -{ -#if STM32_NGPIO_PORTS > 11 -# error "Additional support required for this number of GPIOs" -#elif STM32_NGPIO_PORTS > 10 - 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 'I', 'J', 'K' -#elif STM32_NGPIO_PORTS > 9 - 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 'I', 'J' -#elif STM32_NGPIO_PORTS > 8 - 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 'I' -#elif STM32_NGPIO_PORTS > 7 - 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H' -#elif STM32_NGPIO_PORTS > 6 - 'A', 'B', 'C', 'D', 'E', 'F', 'G' -#elif STM32_NGPIO_PORTS > 5 - 'A', 'B', 'C', 'D', 'E', 'F' -#elif STM32_NGPIO_PORTS > 4 - 'A', 'B', 'C', 'D', 'E' -#elif STM32_NGPIO_PORTS > 3 - 'A', 'B', 'C', 'D' -#elif STM32_NGPIO_PORTS > 2 - 'A', 'B', 'C' -#elif STM32_NGPIO_PORTS > 1 - 'A', 'B' -#elif STM32_NGPIO_PORTS > 0 - 'A' -#else -# error "Bad number of GPIOs" -#endif -}; - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Function: stm32_dumpgpio - * - * Description: - * Dump all GPIO registers associated with the provided base address - * - ****************************************************************************/ - -int stm32_dumpgpio(uint32_t pinset, const char *msg) -{ - irqstate_t flags; - uint32_t base; - unsigned int port; - - /* Get the base address associated with the GPIO port */ - - port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; - base = g_gpiobase[port]; - - /* The following requires exclusive access to the GPIO registers */ - - flags = enter_critical_section(); - -#if defined(CONFIG_STM32_STM32F10XX) - _info("GPIO%c pinset: %08" PRIx32 " base: %08" PRIx32 " -- %s\n", - g_portchar[port], pinset, base, msg); - - if ((getreg32(STM32_RCC_APB2ENR) & RCC_APB2ENR_IOPEN(port)) != 0) - { - _info(" CR: %08" PRIx32 " %08" PRIx32 " IDR: %04" PRIx32 - " ODR: %04" PRIx32 " LCKR: %04" PRIx32 "\n", - getreg32(base + STM32_GPIO_CRH_OFFSET), - getreg32(base + STM32_GPIO_CRL_OFFSET), - getreg32(base + STM32_GPIO_IDR_OFFSET), - getreg32(base + STM32_GPIO_ODR_OFFSET), - getreg32(base + STM32_GPIO_LCKR_OFFSET)); - _info(" EVCR: %02" PRIx32 " MAPR: %08" PRIx32 " CR: %04" PRIx32 - " %04" PRIx32 " %04" PRIx32 " %04" PRIx32 "\n", - getreg32(STM32_AFIO_EVCR), getreg32(STM32_AFIO_MAPR), - getreg32(STM32_AFIO_EXTICR1), - getreg32(STM32_AFIO_EXTICR2), - getreg32(STM32_AFIO_EXTICR3), - getreg32(STM32_AFIO_EXTICR4)); - } - else - { - _info(" GPIO%c not enabled: APB2ENR: %08" PRIx32 "\n", - g_portchar[port], getreg32(STM32_RCC_APB2ENR)); - } - -#elif defined(CONFIG_STM32_STM32L15XX) - DEBUGASSERT(port < STM32_NGPIO_PORTS); - - _info("GPIO%c pinset: %08" PRIx32 " base: %08" PRIx32 " -- %s\n", - g_portchar[port], pinset, base, msg); - - if ((getreg32(STM32_RCC_AHBENR) & RCC_AHBENR_GPIOEN(port)) != 0) - { - _info(" MODE: %08" PRIx32 " OTYPE: %04" PRIx32 - " OSPEED: %08" PRIx32 " PUPDR: %08" PRIx32 "\n", - getreg32(base + STM32_GPIO_MODER_OFFSET), - getreg32(base + STM32_GPIO_OTYPER_OFFSET), - getreg32(base + STM32_GPIO_OSPEED_OFFSET), - getreg32(base + STM32_GPIO_PUPDR_OFFSET)); - _info(" IDR: %04" PRIx32 " ODR: %04" PRIx32 - " BSRR: %08" PRIx32 " LCKR: %04" PRIx32 "\n", - getreg32(base + STM32_GPIO_IDR_OFFSET), - getreg32(base + STM32_GPIO_ODR_OFFSET), - getreg32(base + STM32_GPIO_BSRR_OFFSET), - getreg32(base + STM32_GPIO_LCKR_OFFSET)); - _info(" AFRH: %08" PRIx32 " AFRL: %08" PRIx32 "\n", - getreg32(base + STM32_GPIO_AFRH_OFFSET), - getreg32(base + STM32_GPIO_AFRL_OFFSET)); - } - else - { - _info(" GPIO%c not enabled: AHBENR: %08" PRIx32 "\n", - g_portchar[port], getreg32(STM32_RCC_AHBENR)); - } - -#elif defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX) || \ - defined(CONFIG_STM32_STM32F33XX) - DEBUGASSERT(port < STM32_NGPIO_PORTS); - - _info("GPIO%c pinset: %08" PRIx32 " base: %08" PRIx32 " -- %s\n", - g_portchar[port], pinset, base, msg); - - /* GPIOs are always enabled */ - - _info(" MODE: %08" PRIx32 " OTYPE: %04" PRIx32 - " OSPEED: %08" PRIx32 " PUPDR: %08" PRIx32 "\n", - getreg32(base + STM32_GPIO_MODER_OFFSET), - getreg32(base + STM32_GPIO_OTYPER_OFFSET), - getreg32(base + STM32_GPIO_OSPEED_OFFSET), - getreg32(base + STM32_GPIO_PUPDR_OFFSET)); - _info(" IDR: %04" PRIx32 " ODR: %04" PRIx32 - " BSRR: %08" PRIx32 " LCKR: %04" PRIx32 "\n", - getreg32(base + STM32_GPIO_IDR_OFFSET), - getreg32(base + STM32_GPIO_ODR_OFFSET), - getreg32(base + STM32_GPIO_BSRR_OFFSET), - getreg32(base + STM32_GPIO_LCKR_OFFSET)); - _info(" AFRH: %08" PRIx32 " AFRL: %08" PRIx32 " BRR: %04" PRIx32 "\n", - getreg32(base + STM32_GPIO_AFRH_OFFSET), - getreg32(base + STM32_GPIO_AFRL_OFFSET), - getreg32(base + STM32_GPIO_BRR_OFFSET)); - -#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) - DEBUGASSERT(port < STM32_NGPIO_PORTS); - - _info("GPIO%c pinset: %08" PRIx32 " base: %08" PRIx32 " -- %s\n", - g_portchar[port], pinset, base, msg); - - if ((getreg32(STM32_RCC_AHB1ENR) & RCC_AHB1ENR_GPIOEN(port)) != 0) - { - _info(" MODE: %08" PRIx32 " OTYPE: %04" PRIx32 - " OSPEED: %08" PRIx32 " PUPDR: %08" PRIx32 "\n", - getreg32(base + STM32_GPIO_MODER_OFFSET), - getreg32(base + STM32_GPIO_OTYPER_OFFSET), - getreg32(base + STM32_GPIO_OSPEED_OFFSET), - getreg32(base + STM32_GPIO_PUPDR_OFFSET)); - _info(" IDR: %04" PRIx32 " ODR: %04" PRIx32 - " BSRR: %08" PRIx32 " LCKR: %04" PRIx32 "\n", - getreg32(base + STM32_GPIO_IDR_OFFSET), - getreg32(base + STM32_GPIO_ODR_OFFSET), - getreg32(base + STM32_GPIO_BSRR_OFFSET), - getreg32(base + STM32_GPIO_LCKR_OFFSET)); - _info(" AFRH: %08" PRIx32 " AFRL: %08" PRIx32 "\n", - getreg32(base + STM32_GPIO_AFRH_OFFSET), - getreg32(base + STM32_GPIO_AFRL_OFFSET)); - } - else - { - _info(" GPIO%c not enabled: AHB1ENR: %08" PRIx32 "\n", - g_portchar[port], getreg32(STM32_RCC_AHB1ENR)); - } - -#elif defined(CONFIG_STM32_STM32G4XXX) - DEBUGASSERT(port < STM32_NGPIO_PORTS); - - _info("GPIO%c pinset: %08" PRIx32 " base: %08" PRIx32 " -- %s\n", - g_portchar[port], pinset, base, msg); - - if ((getreg32(STM32_RCC_AHB2ENR) & RCC_AHB2ENR_GPIOEN(port)) != 0) - { - _info(" MODE: %08" PRIx32 " OTYPE: %04" PRIx32 - " OSPEED: %08" PRIx32 " PUPDR: %08" PRIx32 "\n", - getreg32(base + STM32_GPIO_MODER_OFFSET), - getreg32(base + STM32_GPIO_OTYPER_OFFSET), - getreg32(base + STM32_GPIO_OSPEED_OFFSET), - getreg32(base + STM32_GPIO_PUPDR_OFFSET)); - _info(" IDR: %04" PRIx32 " ODR: %04" PRIx32 - " BSRR: %08" PRIx32 " LCKR: %04" PRIx32 "\n", - getreg32(base + STM32_GPIO_IDR_OFFSET), - getreg32(base + STM32_GPIO_ODR_OFFSET), - getreg32(base + STM32_GPIO_BSRR_OFFSET), - getreg32(base + STM32_GPIO_LCKR_OFFSET)); - _info(" AFRH: %08" PRIx32 " AFRL: %08" PRIx32 - " BRR: %04" PRIx32 "\n", - getreg32(base + STM32_GPIO_AFRH_OFFSET), - getreg32(base + STM32_GPIO_AFRL_OFFSET), - getreg32(base + STM32_GPIO_BRR_OFFSET)); - } - else - { - _info(" GPIO%c not enabled: AHB2ENR: %08" PRIx32 "\n", - g_portchar[port], getreg32(STM32_RCC_AHB2ENR)); - } - -#else -# error "Unsupported STM32 chip" -#endif - leave_critical_section(flags); - return OK; -} - -#endif /* CONFIG_DEBUG_FEATURES */ diff --git a/arch/arm/src/stm32/stm32_eth.c b/arch/arm/src/stm32/stm32_eth.c deleted file mode 100644 index 3f1fdf514a366..0000000000000 --- a/arch/arm/src/stm32/stm32_eth.c +++ /dev/null @@ -1,4410 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_eth.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#if defined(CONFIG_NET) && defined(CONFIG_STM32_ETHMAC) - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#if defined(CONFIG_NET_PKT) -# include -#endif - -#include "arm_internal.h" -#include "chip.h" -#include "stm32_gpio.h" -#include "stm32_rcc.h" -#include "stm32_syscfg.h" -#include "stm32_eth.h" - -#include - -/* STM32_NETHERNET determines the number of physical interfaces - * that will be supported. - */ - -#if STM32_NETHERNET > 0 - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -#if STM32_NETHERNET > 1 -# error "Logic to support multiple Ethernet interfaces is incomplete" -#endif - -/* Work queue support is required. */ - -#if !defined(CONFIG_SCHED_WORKQUEUE) -# error Work queue support is required -#endif - -/* The low priority work queue is preferred. If it is not enabled, LPWORK - * will be the same as HPWORK. - * - * NOTE: However, the network should NEVER run on the high priority work - * queue! That queue is intended only to service short back end interrupt - * processing that never suspends. Suspending the high priority work queue - * may bring the system to its knees! - */ - -#define ETHWORK LPWORK - -#if !defined(CONFIG_STM32_SYSCFG) && !defined(CONFIG_STM32_CONNECTIVITYLINE) -# error "CONFIG_STM32_SYSCFG must be defined in the NuttX configuration" -#endif - -#ifndef CONFIG_STM32_PHYADDR -# error "CONFIG_STM32_PHYADDR must be defined in the NuttX configuration" -#endif - -#if !defined(CONFIG_STM32_MII) && !defined(CONFIG_STM32_RMII) -# warning "Neither CONFIG_STM32_MII nor CONFIG_STM32_RMII defined" -#endif - -#if defined(CONFIG_STM32_MII) && defined(CONFIG_STM32_RMII) -# error "Both CONFIG_STM32_MII and CONFIG_STM32_RMII defined" -#endif - -#ifdef CONFIG_STM32_MII -# if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) -# if !defined(CONFIG_STM32_MII_MCO1) && !defined(CONFIG_STM32_MII_MCO2) && !defined(CONFIG_STM32_MII_EXTCLK) -# warning "Neither CONFIG_STM32_MII_MCO1, CONFIG_STM32_MII_MCO2, nor CONFIG_STM32_MII_EXTCLK defined" -# endif -# if defined(CONFIG_STM32_MII_MCO1) && defined(CONFIG_STM32_MII_MCO2) -# error "Both CONFIG_STM32_MII_MCO1 and CONFIG_STM32_MII_MCO2 defined" -# endif -# elif defined(CONFIG_STM32_CONNECTIVITYLINE) -# if !defined(CONFIG_STM32_MII_MCO) && !defined(CONFIG_STM32_MII_EXTCLK) -# warning "Neither CONFIG_STM32_MII_MCO nor CONFIG_STM32_MII_EXTCLK defined" -# endif -# endif -#endif - -#ifdef CONFIG_STM32_RMII -# if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) -# if !defined(CONFIG_STM32_RMII_MCO1) && !defined(CONFIG_STM32_RMII_MCO2) && !defined(CONFIG_STM32_RMII_EXTCLK) -# warning "Neither CONFIG_STM32_RMII_MCO1, CONFIG_STM32_RMII_MCO2, nor CONFIG_STM32_RMII_EXTCLK defined" -# endif -# if defined(CONFIG_STM32_RMII_MCO1) && defined(CONFIG_STM32_RMII_MCO2) -# error "Both CONFIG_STM32_RMII_MCO1 and CONFIG_STM32_RMII_MCO2 defined" -# endif -# elif defined(CONFIG_STM32_CONNECTIVITYLINE) -# if !defined(CONFIG_STM32_RMII_MCO) && !defined(CONFIG_STM32_RMII_EXTCLK) -# warning "Neither CONFIG_STM32_RMII_MCO nor CONFIG_STM32_RMII_EXTCLK defined" -# endif -# endif -#endif - -#ifdef CONFIG_STM32_AUTONEG -# ifndef CONFIG_STM32_PHYSR -# error "CONFIG_STM32_PHYSR must be defined in the NuttX configuration" -# endif -# ifdef CONFIG_STM32_PHYSR_ALTCONFIG -# ifndef CONFIG_STM32_PHYSR_ALTMODE -# error "CONFIG_STM32_PHYSR_ALTMODE must be defined in the NuttX configuration" -# endif -# ifndef CONFIG_STM32_PHYSR_10HD -# error "CONFIG_STM32_PHYSR_10HD must be defined in the NuttX configuration" -# endif -# ifndef CONFIG_STM32_PHYSR_100HD -# error "CONFIG_STM32_PHYSR_100HD must be defined in the NuttX configuration" -# endif -# ifndef CONFIG_STM32_PHYSR_10FD -# error "CONFIG_STM32_PHYSR_10FD must be defined in the NuttX configuration" -# endif -# ifndef CONFIG_STM32_PHYSR_100FD -# error "CONFIG_STM32_PHYSR_100FD must be defined in the NuttX configuration" -# endif -# else -# ifndef CONFIG_STM32_PHYSR_SPEED -# error "CONFIG_STM32_PHYSR_SPEED must be defined in the NuttX configuration" -# endif -# ifndef CONFIG_STM32_PHYSR_100MBPS -# error "CONFIG_STM32_PHYSR_100MBPS must be defined in the NuttX configuration" -# endif -# ifndef CONFIG_STM32_PHYSR_MODE -# error "CONFIG_STM32_PHYSR_MODE must be defined in the NuttX configuration" -# endif -# ifndef CONFIG_STM32_PHYSR_FULLDUPLEX -# error "CONFIG_STM32_PHYSR_FULLDUPLEX must be defined in the NuttX configuration" -# endif -# endif -#endif - -/* These definitions are used to enable the PHY interrupts */ - -#if defined(CONFIG_NETDEV_PHY_IOCTL) && defined(CONFIG_ARCH_PHY_INTERRUPT) -# if defined( CONFIG_ETH0_PHY_AM79C874) -# error missing logic -# elif defined( CONFIG_ETH0_PHY_KS8721) -# error missing logic -# elif defined( CONFIG_ETH0_PHY_KSZ8041) -# error missing logic -# elif defined( CONFIG_ETH0_PHY_KSZ8051) -# error missing logic -# elif defined( CONFIG_ETH0_PHY_KSZ8061) -# error missing logic -# elif defined( CONFIG_ETH0_PHY_KSZ8081) -# define MII_INT_REG MII_KSZ8081_INT -# define MII_INT_SETEN MII_KSZ80X1_INT_LDEN | MII_KSZ80X1_INT_LUEN -# define MII_INT_CLREN 0 -# elif defined( CONFIG_ETH0_PHY_KSZ90x1) -# error missing logic -# elif defined( CONFIG_ETH0_PHY_DP83848C) -# define MII_INT_REG MII_DP83848C_MISR -# define MII_INT_SETEN MII_DP83848C_LINK_INT_EN -# define MII_INT_CLREN 0 -# elif defined( CONFIG_ETH0_PHY_LAN8720) -# error missing logic -# elif defined( CONFIG_ETH0_PHY_LAN8740) -# error missing logic -# elif defined( CONFIG_ETH0_PHY_LAN8740A) -# error missing logic -# elif defined( CONFIG_ETH0_PHY_LAN8742A) -# error missing logic -# elif defined( CONFIG_ETH0_PHY_DM9161) -# error missing logic -# else -# error unknown PHY -# endif -#endif - -/* This driver does not use IPv4 checksum offloading. */ - -#undef CONFIG_STM32_ETH_HWCHECKSUM - -/* Add 4 to the configured buffer size to account for the 2 byte checksum - * memory needed at the end of the maximum size packet. Buffer sizes must - * be an even multiple of 4, 8, or 16 bytes (depending on buswidth). We - * will use the 16-byte alignment in all cases. - */ - -#define OPTIMAL_ETH_BUFSIZE ((CONFIG_NET_ETH_PKTSIZE + 4 + 15) & ~15) - -#ifndef CONFIG_STM32_ETH_BUFSIZE -# define CONFIG_STM32_ETH_BUFSIZE OPTIMAL_ETH_BUFSIZE -#endif - -#if CONFIG_STM32_ETH_BUFSIZE > ETH_TDES1_TBS1_MASK -# error "CONFIG_STM32_ETH_BUFSIZE is too large" -#endif - -#if (CONFIG_STM32_ETH_BUFSIZE & 15) != 0 -# error "CONFIG_STM32_ETH_BUFSIZE must be aligned" -#endif - -#if CONFIG_STM32_ETH_BUFSIZE != OPTIMAL_ETH_BUFSIZE -# warning "You using an incomplete/untested configuration" -#endif - -#ifndef CONFIG_STM32_ETH_NRXDESC -# define CONFIG_STM32_ETH_NRXDESC 8 -#endif -#ifndef CONFIG_STM32_ETH_NTXDESC -# define CONFIG_STM32_ETH_NTXDESC 4 -#endif - -/* We need at least one more free buffer than transmit buffers */ - -#define STM32_ETH_NFREEBUFFERS (CONFIG_STM32_ETH_NTXDESC+1) - -/* Extremely detailed register debug that you would normally never want - * enabled. - */ - -#ifndef CONFIG_DEBUG_NET_INFO -# undef CONFIG_STM32_ETHMAC_REGDEBUG -#endif - -/* Clocking *****************************************************************/ - -/* Set MACMIIAR CR bits depending on HCLK setting */ - -#if STM32_HCLK_FREQUENCY >= 20000000 && STM32_HCLK_FREQUENCY < 35000000 -# define ETH_MACMIIAR_CR ETH_MACMIIAR_CR_20_35 -#elif STM32_HCLK_FREQUENCY >= 35000000 && STM32_HCLK_FREQUENCY < 60000000 -# define ETH_MACMIIAR_CR ETH_MACMIIAR_CR_35_60 -#elif STM32_HCLK_FREQUENCY >= 60000000 && STM32_HCLK_FREQUENCY < 100000000 -# define ETH_MACMIIAR_CR ETH_MACMIIAR_CR_60_100 -#elif STM32_HCLK_FREQUENCY >= 100000000 && STM32_HCLK_FREQUENCY < 150000000 -# define ETH_MACMIIAR_CR ETH_MACMIIAR_CR_100_150 -#elif STM32_HCLK_FREQUENCY >= 150000000 && STM32_HCLK_FREQUENCY <= 180000000 -# define ETH_MACMIIAR_CR ETH_MACMIIAR_CR_150_180 -#else -# error "STM32_HCLK_FREQUENCY not supportable" -#endif - -/* Timing *******************************************************************/ - -/* TX timeout = 1 minute */ - -#define STM32_TXTIMEOUT (60*CLK_TCK) - -/* PHY reset/configuration delays in milliseconds */ - -#define PHY_RESET_DELAY (65) -#define PHY_CONFIG_DELAY (1000) - -/* PHY read/write delays in loop counts */ - -#define PHY_READ_TIMEOUT (0x0004ffff) -#define PHY_WRITE_TIMEOUT (0x0004ffff) -#define PHY_RETRY_TIMEOUT (0x0004ffff) - -/* Register values **********************************************************/ - -/* Clear the MACCR bits that will be setup during MAC initialization (or that - * are cleared unconditionally). Per the reference manual, all reserved bits - * must be retained at their reset value. - * - * ETH_MACCR_RE Bit 2: Receiver enable - * ETH_MACCR_TE Bit 3: Transmitter enable - * ETH_MACCR_DC Bit 4: Deferral check - * ETH_MACCR_BL Bits 5-6: Back-off limit - * ETH_MACCR_APCS Bit 7: Automatic pad/CRC stripping - * ETH_MACCR_RD Bit 9: Retry disable - * ETH_MACCR_IPCO Bit 10: IPv4 checksum offload - * ETH_MACCR_DM Bit 11: Duplex mode - * ETH_MACCR_LM Bit 12: Loopback mode - * ETH_MACCR_ROD Bit 13: Receive own disable - * ETH_MACCR_FES Bit 14: Fast Ethernet speed - * ETH_MACCR_CSD Bit 16: Carrier sense disable - * ETH_MACCR_IFG Bits 17-19: Interframe gap - * ETH_MACCR_JD Bit 22: Jabber disable - * ETH_MACCR_WD Bit 23: Watchdog disable - * ETH_MACCR_CSTF Bits 25: CRC stripping for Type frames (F2/F4 only) - */ - -#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) -#define MACCR_CLEAR_BITS \ - (ETH_MACCR_RE | ETH_MACCR_TE | ETH_MACCR_DC | ETH_MACCR_BL_MASK | \ - ETH_MACCR_APCS | ETH_MACCR_RD | ETH_MACCR_IPCO | ETH_MACCR_DM | \ - ETH_MACCR_LM | ETH_MACCR_ROD | ETH_MACCR_FES | ETH_MACCR_CSD | \ - ETH_MACCR_IFG_MASK | ETH_MACCR_JD | ETH_MACCR_WD | ETH_MACCR_CSTF) -#else -#define MACCR_CLEAR_BITS \ - (ETH_MACCR_RE | ETH_MACCR_TE | ETH_MACCR_DC | ETH_MACCR_BL_MASK | \ - ETH_MACCR_APCS | ETH_MACCR_RD | ETH_MACCR_IPCO | ETH_MACCR_DM | \ - ETH_MACCR_LM | ETH_MACCR_ROD | ETH_MACCR_FES | ETH_MACCR_CSD | \ - ETH_MACCR_IFG_MASK | ETH_MACCR_JD | ETH_MACCR_WD) -#endif - -/* The following bits are set or left zero unconditionally in all modes. - * - * ETH_MACCR_RE Receiver enable 0 (disabled) - * ETH_MACCR_TE Transmitter enable 0 (disabled) - * ETH_MACCR_DC Deferral check 0 (disabled) - * ETH_MACCR_BL Back-off limit 0 (10) - * ETH_MACCR_APCS Automatic pad/CRC stripping 0 (disabled) - * ETH_MACCR_RD Retry disable 1 (disabled) - * ETH_MACCR_IPCO IPv4 checksum offload Depends on - * CONFIG_STM32_ETH_HWCHECKSUM - * ETH_MACCR_LM Loopback mode 0 (disabled) - * ETH_MACCR_ROD Receive own disable 0 (enabled) - * ETH_MACCR_CSD Carrier sense disable 0 (enabled) - * ETH_MACCR_IFG Interframe gap 0 (96 bits) - * ETH_MACCR_JD Jabber disable 0 (enabled) - * ETH_MACCR_WD Watchdog disable 0 (enabled) - * ETH_MACCR_CSTF CRC stripping for Type frames 0 (disabled, F2/F4 only) - * - * The following are set conditioinally based on mode and speed. - * - * ETH_MACCR_DM Duplex mode Depends on priv->fduplex - * ETH_MACCR_FES Fast Ethernet speed Depends on priv->mbps100 - */ - -#ifdef CONFIG_STM32_ETH_HWCHECKSUM -# define MACCR_SET_BITS \ - (ETH_MACCR_BL_10 | ETH_MACCR_RD | ETH_MACCR_IPCO | ETH_MACCR_IFG(96)) -#else -# define MACCR_SET_BITS \ - (ETH_MACCR_BL_10 | ETH_MACCR_RD | ETH_MACCR_IFG(96)) -#endif - -/* Clear the MACCR bits that will be setup during MAC initialization (or that - * are cleared unconditionally). Per the reference manual, all reserved bits - * must be retained at their reset value. - * - * ETH_MACFFR_PM Bit 0: Promiscuous mode - * ETH_MACFFR_HU Bit 1: Hash unicast - * ETH_MACFFR_HM Bit 2: Hash multicast - * ETH_MACFFR_DAIF Bit 3: Destination address inverse filtering - * ETH_MACFFR_PAM Bit 4: Pass all multicast - * ETH_MACFFR_BFD Bit 5: Broadcast frames disable - * ETH_MACFFR_PCF Bits 6-7: Pass control frames - * ETH_MACFFR_SAIF Bit 8: Source address inverse filtering - * ETH_MACFFR_SAF Bit 9: Source address filter - * ETH_MACFFR_HPF Bit 10: Hash or perfect filter - * ETH_MACFFR_RA Bit 31: Receive all - */ - -#define MACFFR_CLEAR_BITS \ - (ETH_MACFFR_PM | ETH_MACFFR_HU | ETH_MACFFR_HM | ETH_MACFFR_DAIF | \ - ETH_MACFFR_PAM | ETH_MACFFR_BFD | ETH_MACFFR_PCF_MASK | ETH_MACFFR_SAIF | \ - ETH_MACFFR_SAF | ETH_MACFFR_HPF | ETH_MACFFR_RA) - -/* The following bits are set or left zero unconditionally in all modes. - * - * ETH_MACFFR_HU Hash unicast 0 (perfect dest filtering) - * ETH_MACFFR_HM Hash multicast 0 (perfect dest filtering) - * ETH_MACFFR_DAIF Destination address 0 (normal) - * inverse filtering - * ETH_MACFFR_PAM Pass all multicast 0 (Depends on HM bit) - * ETH_MACFFR_BFD Broadcast frames disable 0 (enabled) - * ETH_MACFFR_PCF Pass control frames 1 (block all but PAUSE) - * ETH_MACFFR_SAIF Source address inverse 0 (not used) - * filtering - * ETH_MACFFR_SAF Source address filter 0 (disabled) - * ETH_MACFFR_HPF Hash or perfect filter 0 (Only matching frames passed) - * ETH_MACFFR_RA Receive all 0 (disabled) - */ - -#ifdef CONFIG_NET_PROMISCUOUS -# define MACFFR_SET_BITS (ETH_MACFFR_PCF_PAUSE | ETH_MACFFR_PM) -#else -# define MACFFR_SET_BITS (ETH_MACFFR_PCF_PAUSE) -#endif - -/* Clear the MACFCR bits that will be setup during MAC initialization (or - * that are cleared unconditionally). Per the reference manual, all reserved - * bits must be retained at their reset value. - * - * ETH_MACFCR_FCB_BPA Bit 0: Flow control busy/back pressure activate - * ETH_MACFCR_TFCE Bit 1: Transmit flow control enable - * ETH_MACFCR_RFCE Bit 2: Receive flow control enable - * ETH_MACFCR_UPFD Bit 3: Unicast pause frame detect - * ETH_MACFCR_PLT Bits 4-5: Pause low threshold - * ETH_MACFCR_ZQPD Bit 7: Zero-quanta pause disable - * ETH_MACFCR_PT Bits 16-31: Pause time - */ - -#define MACFCR_CLEAR_MASK \ - (ETH_MACFCR_FCB_BPA | ETH_MACFCR_TFCE | ETH_MACFCR_RFCE | ETH_MACFCR_UPFD | \ - ETH_MACFCR_PLT_MASK | ETH_MACFCR_ZQPD | ETH_MACFCR_PT_MASK) - -/* The following bits are set or left zero unconditionally in all modes. - * - * ETH_MACFCR_FCB_BPA Flow control busy/back 0 (no pause control frame) - * activate pressure - * ETH_MACFCR_TFCE Transmit flow control enable 0 (disabled) - * ETH_MACFCR_RFCE Receive flow control enable 0 (disabled) - * ETH_MACFCR_UPFD Unicast pause frame detect 0 (disabled) - * ETH_MACFCR_PLT Pause low threshold 0 (pause time - 4) - * ETH_MACFCR_ZQPD Zero-quanta pause disable 1 (disabled) - * ETH_MACFCR_PT Pause time 0 - */ - -#define MACFCR_SET_MASK (ETH_MACFCR_PLT_M4 | ETH_MACFCR_ZQPD) - -/* Clear the DMAOMR bits that will be setup during MAC initialization (or - * that are cleared unconditionally). Per the reference manual, all reserved - * bits must be retained at their reset value. - * - * ETH_DMAOMR_SR Bit 1: Start/stop receive - * TH_DMAOMR_OSF Bit 2: Operate on second frame - * ETH_DMAOMR_RTC Bits 3-4: Receive threshold control - * ETH_DMAOMR_FUGF Bit 6: Forward undersized good frames - * ETH_DMAOMR_FEF Bit 7: Forward error frames - * ETH_DMAOMR_ST Bit 13: Start/stop transmission - * ETH_DMAOMR_TTC Bits 14-16: Transmit threshold control - * ETH_DMAOMR_FTF Bit 20: Flush transmit FIFO - * ETH_DMAOMR_TSF Bit 21: Transmit store and forward - * ETH_DMAOMR_DFRF Bit 24: Disable flushing of received frames - * ETH_DMAOMR_RSF Bit 25: Receive store and forward - * TH_DMAOMR_DTCEFD Bit 26: Dropping of TCP/IP checksum error frames disable - */ - -#define DMAOMR_CLEAR_MASK \ - (ETH_DMAOMR_SR | ETH_DMAOMR_OSF | ETH_DMAOMR_RTC_MASK | ETH_DMAOMR_FUGF | \ - ETH_DMAOMR_FEF | ETH_DMAOMR_ST | ETH_DMAOMR_TTC_MASK | ETH_DMAOMR_FTF | \ - ETH_DMAOMR_TSF | ETH_DMAOMR_DFRF | ETH_DMAOMR_RSF | ETH_DMAOMR_DTCEFD) - -/* The following bits are set or left zero unconditionally in all modes. - * - * ETH_DMAOMR_SR Start/stop receive 0 (not running) - * TH_DMAOMR_OSF Operate on second frame 1 (enabled) - * ETH_DMAOMR_RTC Receive threshold control 0 (64 bytes) - * ETH_DMAOMR_FUGF Forward undersized good 0 (disabled) - * frames - * ETH_DMAOMR_FEF Forward error frames 0 (disabled) - * ETH_DMAOMR_ST Start/stop transmission 0 (not running) - * ETH_DMAOMR_TTC Transmit threshold control 0 (64 bytes) - * ETH_DMAOMR_FTF Flush transmit FIFO 0 (no flush) - * ETH_DMAOMR_TSF Transmit store and forward 1 (enabled) - * ETH_DMAOMR_DFRF Disable flushing of received 0 (enabled) - * frames - * ETH_DMAOMR_RSF Receive store and forward 1 (enabled) - * TH_DMAOMR_DTCEFD Dropping of TCP/IP checksum Depends on - * error frames disable CONFIG_STM32_ETH_HWCHECKSUM - * - * When the checksum offload feature is enabled, we need to enable the Store - * and Forward mode: the store and forward guarantee that a whole frame is - * stored in the FIFO, so the MAC can insert/verify the checksum, if the - * checksum is OK the DMA can handle the frame otherwise the frame is dropped - */ - -#ifdef CONFIG_STM32_ETH_HWCHECKSUM -# define DMAOMR_SET_MASK \ - (ETH_DMAOMR_OSF | ETH_DMAOMR_RTC_64 | ETH_DMAOMR_TTC_64 | \ - ETH_DMAOMR_TSF | ETH_DMAOMR_RSF) -#else -# define DMAOMR_SET_MASK \ - (ETH_DMAOMR_OSF | ETH_DMAOMR_RTC_64 | ETH_DMAOMR_TTC_64 | \ - ETH_DMAOMR_TSF | ETH_DMAOMR_RSF | ETH_DMAOMR_DTCEFD) -#endif - -/* Clear the DMABMR bits that will be setup during MAC initialization (or - * that are cleared unconditionally). Per the reference manual, all reserved - * bits must be retained at their reset value. - * - * ETH_DMABMR_SR Bit 0: Software reset - * ETH_DMABMR_DA Bit 1: DMA Arbitration - * ETH_DMABMR_DSL Bits 2-6: Descriptor skip length - * ETH_DMABMR_EDFE Bit 7: Enhanced descriptor format enable - * ETH_DMABMR_PBL Bits 8-13: Programmable burst length - * ETH_DMABMR_RTPR Bits 14-15: RX TX priority ratio - * ETH_DMABMR_FB Bit 16: Fixed burst - * ETH_DMABMR_RDP Bits 17-22: RX DMA PBL - * ETH_DMABMR_USP Bit 23: Use separate PBL - * ETH_DMABMR_FPM Bit 24: 4xPBL mode - * ETH_DMABMR_AAB Bit 25: Address-aligned beats - * ETH_DMABMR_MB Bit 26: Mixed burst (F2/F4 only) - */ - -#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) -#define DMABMR_CLEAR_MASK \ - (ETH_DMABMR_SR | ETH_DMABMR_DA | ETH_DMABMR_DSL_MASK | ETH_DMABMR_EDFE | \ - ETH_DMABMR_PBL_MASK | ETH_DMABMR_RTPR_MASK | ETH_DMABMR_FB | ETH_DMABMR_RDP_MASK | \ - ETH_DMABMR_USP | ETH_DMABMR_FPM | ETH_DMABMR_AAB | ETH_DMABMR_MB) -#else -#define DMABMR_CLEAR_MASK \ - (ETH_DMABMR_SR | ETH_DMABMR_DA | ETH_DMABMR_DSL_MASK | ETH_DMABMR_EDFE | \ - ETH_DMABMR_PBL_MASK | ETH_DMABMR_RTPR_MASK | ETH_DMABMR_FB | ETH_DMABMR_RDP_MASK | \ - ETH_DMABMR_USP | ETH_DMABMR_FPM | ETH_DMABMR_AAB) -#endif - -/* The following bits are set or left zero unconditionally in all modes. - * - * - * ETH_DMABMR_SR Software reset 0 (no reset) - * ETH_DMABMR_DA DMA Arbitration 0 (round robin) - * ETH_DMABMR_DSL Descriptor skip length 0 - * ETH_DMABMR_EDFE Enhanced descriptor format Depends on - * enable CONFIG_STM32_ETH_ENHANCEDDESC - * ETH_DMABMR_PBL Programmable burst length 32 beats - * ETH_DMABMR_RTPR RX TX priority ratio 2:1 - * ETH_DMABMR_FB Fixed burst 1 (enabled) - * ETH_DMABMR_RDP RX DMA PBL 32 beats - * ETH_DMABMR_USP Use separate PBL 1 (enabled) - * ETH_DMABMR_FPM 4xPBL mode 0 (disabled) - * ETH_DMABMR_AAB Address-aligned beats 1 (enabled) - * ETH_DMABMR_MB Mixed burst 0 (disabled, F2/F4 only) - */ - -#ifdef CONFIG_STM32_ETH_ENHANCEDDESC -# define DMABMR_SET_MASK \ - (ETH_DMABMR_DSL(0) | ETH_DMABMR_PBL(32) | ETH_DMABMR_EDFE | ETH_DMABMR_RTPR_2TO1 | \ - ETH_DMABMR_FB | ETH_DMABMR_RDP(32) | ETH_DMABMR_USP | ETH_DMABMR_AAB) -#else -# define DMABMR_SET_MASK \ - (ETH_DMABMR_DSL(0) | ETH_DMABMR_PBL(32) | ETH_DMABMR_RTPR_2TO1 | ETH_DMABMR_FB | \ - ETH_DMABMR_RDP(32) | ETH_DMABMR_USP | ETH_DMABMR_AAB) -#endif - -/* Interrupt bit sets *******************************************************/ - -/* All interrupts in the normal and abnormal interrupt summary. Early - * transmit interrupt (ETI) is excluded from the abnormal set because it - * causes too many interrupts and is not interesting. - */ - -#define ETH_DMAINT_NORMAL \ - (ETH_DMAINT_TI | ETH_DMAINT_TBUI | ETH_DMAINT_RI | ETH_DMAINT_ERI) - -#define ETH_DMAINT_ABNORMAL \ - (ETH_DMAINT_TPSI | ETH_DMAINT_TJTI | ETH_DMAINT_ROI | ETH_DMAINT_TUI | \ - ETH_DMAINT_RBUI | ETH_DMAINT_RPSI | ETH_DMAINT_RWTI | /* ETH_DMAINT_ETI | */ \ - ETH_DMAINT_FBEI) - -/* Normal receive, transmit, error interrupt enable bit sets */ - -#define ETH_DMAINT_RECV_ENABLE (ETH_DMAINT_NIS | ETH_DMAINT_RI) -#define ETH_DMAINT_XMIT_ENABLE (ETH_DMAINT_NIS | ETH_DMAINT_TI) -#define ETH_DMAINT_XMIT_DISABLE (ETH_DMAINT_TI) - -#define ETH_DMAINT_ERROR_ENABLE (ETH_DMAINT_AIS | ETH_DMAINT_ABNORMAL) - -/* Helpers ******************************************************************/ - -/* This is a helper pointer for accessing the contents of the Ethernet - * header - */ - -#define BUF ((struct eth_hdr_s *)priv->dev.d_buf) - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/* The stm32_ethmac_s encapsulates all state information for a single - * hardware interface - */ - -struct stm32_ethmac_s -{ - uint8_t ifup : 1; /* true:ifup false:ifdown */ - uint8_t mbps100 : 1; /* 100MBps operation (vs 10 MBps) */ - uint8_t fduplex : 1; /* Full (vs. half) duplex */ - struct wdog_s txtimeout; /* TX timeout timer */ - struct work_s irqwork; /* For deferring interrupt work to the work queue */ - struct work_s pollwork; /* For deferring poll work to the work queue */ - - /* This holds the information visible to the NuttX network */ - - struct net_driver_s dev; /* Interface understood by the network */ - - /* Used to track transmit and receive descriptors */ - - struct eth_txdesc_s *txhead; /* Next available TX descriptor */ - struct eth_rxdesc_s *rxhead; /* Next available RX descriptor */ - - struct eth_txdesc_s *txtail; /* First "in_flight" TX descriptor */ - struct eth_rxdesc_s *rxcurr; /* First RX descriptor of the segment */ - uint16_t segments; /* RX segment count */ - uint16_t inflight; /* Number of TX transfers "in_flight" */ - sq_queue_t freeb; /* The free buffer list */ - -#ifdef CONFIG_STM32_ETH_TIMESTAMP_RX - uint32_t rxtimelow; /* Received packet timestamp subsecond */ - uint32_t rxtimehigh; /* Received packet timestamp seconds */ -#endif -}; - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* Descriptor allocations */ - -static struct eth_rxdesc_s g_rxtable[CONFIG_STM32_ETH_NRXDESC] - aligned_data(4); -static struct eth_txdesc_s g_txtable[CONFIG_STM32_ETH_NTXDESC] - aligned_data(4); - -/* Buffer allocations */ - -static uint8_t g_rxbuffer[CONFIG_STM32_ETH_NRXDESC * - CONFIG_STM32_ETH_BUFSIZE] aligned_data(4); -static uint8_t g_alloc[STM32_ETH_NFREEBUFFERS * - CONFIG_STM32_ETH_BUFSIZE] aligned_data(4); - -static struct stm32_ethmac_s g_stm32ethmac[STM32_NETHERNET]; - -#ifdef CONFIG_STM32_ETH_PTP_RTC_HIRES -static spinlock_t g_rtc_lock = SP_UNLOCKED; -volatile bool g_rtc_enabled; -static struct timespec g_stm32_eth_ptp_basetime; -#endif - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -/* Register operations ******************************************************/ - -#if defined(CONFIG_STM32_ETHMAC_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES) -static uint32_t stm32_getreg(uint32_t addr); -static void stm32_putreg(uint32_t val, uint32_t addr); -static void stm32_checksetup(void); -#else -# define stm32_getreg(addr) getreg32(addr) -# define stm32_putreg(val,addr) putreg32(val,addr) -# define stm32_checksetup() -#endif - -/* Free buffer management */ - -static void stm32_initbuffer(struct stm32_ethmac_s *priv, uint8_t *alloc); -static inline uint8_t *stm32_allocbuffer(struct stm32_ethmac_s *priv); -static inline void stm32_freebuffer(struct stm32_ethmac_s *priv, - uint8_t *buffer); -static inline bool stm32_isfreebuffer(struct stm32_ethmac_s *priv); - -/* Common TX logic */ - -static int stm32_transmit(struct stm32_ethmac_s *priv); -static int stm32_txpoll(struct net_driver_s *dev); -static void stm32_dopoll(struct stm32_ethmac_s *priv); - -/* Interrupt handling */ - -static void stm32_enableint(struct stm32_ethmac_s *priv, - uint32_t ierbit); -static void stm32_disableint(struct stm32_ethmac_s *priv, - uint32_t ierbit); - -static void stm32_freesegment(struct stm32_ethmac_s *priv, - struct eth_rxdesc_s *rxfirst, int segments); -static int stm32_recvframe(struct stm32_ethmac_s *priv); -static void stm32_receive(struct stm32_ethmac_s *priv); -static void stm32_freeframe(struct stm32_ethmac_s *priv); -static void stm32_txdone(struct stm32_ethmac_s *priv); - -static void stm32_interrupt_work(void *arg); -static int stm32_interrupt(int irq, void *context, void *arg); - -/* Watchdog timer expirations */ - -static void stm32_txtimeout_work(void *arg); -static void stm32_txtimeout_expiry(wdparm_t arg); - -/* NuttX callback functions */ - -static int stm32_ifup(struct net_driver_s *dev); -static int stm32_ifdown(struct net_driver_s *dev); - -static void stm32_txavail_work(void *arg); -static int stm32_txavail(struct net_driver_s *dev); - -#if defined(CONFIG_NET_MCASTGROUP) || defined(CONFIG_NET_ICMPv6) -static int stm32_addmac(struct net_driver_s *dev, const uint8_t *mac); -#endif -#ifdef CONFIG_NET_MCASTGROUP -static int stm32_rmmac(struct net_driver_s *dev, const uint8_t *mac); -#endif -#ifdef CONFIG_NETDEV_IOCTL -static int stm32_ioctl(struct net_driver_s *dev, int cmd, - unsigned long arg); -#endif - -/* Descriptor Initialization */ - -static void stm32_txdescinit(struct stm32_ethmac_s *priv, - struct eth_txdesc_s *txtable); -static void stm32_rxdescinit(struct stm32_ethmac_s *priv, - struct eth_rxdesc_s *rxtable, - uint8_t *rxbuffer); - -/* PHY Initialization */ - -#if defined(CONFIG_NETDEV_PHY_IOCTL) && defined(CONFIG_ARCH_PHY_INTERRUPT) -static int stm32_phyintenable(struct stm32_ethmac_s *priv); -#endif -#if defined(CONFIG_STM32_AUTONEG) || defined(CONFIG_NETDEV_PHY_IOCTL) || \ - defined(CONFIG_ETH0_PHY_DM9161) -static int stm32_phyread(uint16_t phydevaddr, uint16_t phyregaddr, - uint16_t *value); -#endif -static int stm32_phywrite(uint16_t phydevaddr, uint16_t phyregaddr, - uint16_t value); -#ifdef CONFIG_ETH0_PHY_DM9161 -static inline int stm32_dm9161(struct stm32_ethmac_s *priv); -#endif -static int stm32_phyinit(struct stm32_ethmac_s *priv); - -/* MAC/DMA Initialization */ - -#ifdef CONFIG_STM32_MII -static inline void stm32_selectmii(void); -#endif -#ifdef CONFIG_STM32_RMII -static inline void stm32_selectrmii(void); -#endif -static inline void stm32_ethgpioconfig(struct stm32_ethmac_s *priv); -static int stm32_ethreset(struct stm32_ethmac_s *priv); -static int stm32_macconfig(struct stm32_ethmac_s *priv); -static void stm32_macaddress(struct stm32_ethmac_s *priv); -static int stm32_macenable(struct stm32_ethmac_s *priv); -static int stm32_ethconfig(struct stm32_ethmac_s *priv); - -/* PTP initialization and access */ - -#ifdef CONFIG_STM32_ETH_PTP -static int stm32_eth_ptp_adjust(long ppb); -static void stm32_eth_ptp_init(uint64_t timestamp); -static uint64_t stm32_eth_ptp_gettime(void); -#endif - -#ifdef CONFIG_STM32_ETH_TIMESTAMP_RX -static void stm32_eth_ptp_convert_rxtime(struct stm32_ethmac_s *priv); -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_getreg - * - * Description: - * This function may to used to intercept an monitor all register accesses. - * Clearly this is nothing you would want to do unless you are debugging - * this driver. - * - * Input Parameters: - * addr - The register address to read - * - * Returned Value: - * The value read from the register - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_ETHMAC_REGDEBUG -static uint32_t stm32_getreg(uint32_t addr) -{ - static uint32_t prevaddr = 0; - static uint32_t preval = 0; - static uint32_t count = 0; - - /* Read the value from the register */ - - uint32_t val = getreg32(addr); - - /* Is this the same value that we read from the same register last time? - * Are we polling the register? If so, suppress some of the output. - */ - - if (addr == prevaddr && val == preval) - { - if (count == 0xffffffff || ++count > 3) - { - if (count == 4) - { - ninfo("...\n"); - } - - return val; - } - } - - /* No this is a new address or value */ - - else - { - /* Did we print "..." for the previous value? */ - - if (count > 3) - { - /* Yes.. then show how many times the value repeated */ - - ninfo("[repeats %d more times]\n", count - 3); - } - - /* Save the new address, value, and count */ - - prevaddr = addr; - preval = val; - count = 1; - } - - /* Show the register value read */ - - ninfo("%08" PRIx32 "->%08" PRIx32 "\n", addr, val); - return val; -} -#endif - -/**************************************************************************** - * Name: stm32_putreg - * - * Description: - * This function may to used to intercept an monitor all register accesses. - * Clearly this is nothing you would want to do unless you are debugging - * this driver. - * - * Input Parameters: - * val - The value to write to the register - * addr - The register address to read - * - * Returned Value: - * None - * - ****************************************************************************/ - -#if defined(CONFIG_STM32_ETHMAC_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES) -static void stm32_putreg(uint32_t val, uint32_t addr) -{ - /* Show the register value being written */ - - ninfo("%08" PRIx32 "<-%08" PRIx32 "\n", addr, val); - - /* Write the value */ - - putreg32(val, addr); -} -#endif - -/**************************************************************************** - * Name: stm32_checksetup - * - * Description: - * Show the state of critical configuration registers. - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_ETHMAC_REGDEBUG -static void stm32_checksetup(void) -{ -} -#endif - -/**************************************************************************** - * Function: stm32_initbuffer - * - * Description: - * Initialize the free buffer list. - * - * Input Parameters: - * priv - Reference to the driver state structure - * - * Returned Value: - * None - * - * Assumptions: - * Called during early driver initialization before Ethernet interrupts - * are enabled. - * - ****************************************************************************/ - -static void stm32_initbuffer(struct stm32_ethmac_s *priv, uint8_t *alloc) -{ - uint8_t *buffer; - int i; - - /* Initialize the head of the free buffer list */ - - sq_init(&priv->freeb); - - /* Add all of the pre-allocated buffers to the free buffer list */ - - for (i = 0, buffer = alloc; - i < STM32_ETH_NFREEBUFFERS; - i++, buffer += CONFIG_STM32_ETH_BUFSIZE) - { - sq_addlast((sq_entry_t *)buffer, &priv->freeb); - } -} - -/**************************************************************************** - * Function: stm32_allocbuffer - * - * Description: - * Allocate one buffer from the free buffer list. - * - * Input Parameters: - * priv - Reference to the driver state structure - * - * Returned Value: - * Pointer to the allocated buffer on success; NULL on failure - * - * Assumptions: - * May or may not be called from an interrupt handler. In either case, - * global interrupts are disabled, either explicitly or indirectly through - * interrupt handling logic. - * - ****************************************************************************/ - -static inline uint8_t *stm32_allocbuffer(struct stm32_ethmac_s *priv) -{ - /* Allocate a buffer by returning the head of the free buffer list */ - - return (uint8_t *)sq_remfirst(&priv->freeb); -} - -/**************************************************************************** - * Function: stm32_freebuffer - * - * Description: - * Return a buffer to the free buffer list. - * - * Input Parameters: - * priv - Reference to the driver state structure - * buffer - A pointer to the buffer to be freed - * - * Returned Value: - * None - * - * Assumptions: - * May or may not be called from an interrupt handler. In either case, - * global interrupts are disabled, either explicitly or indirectly through - * interrupt handling logic. - * - ****************************************************************************/ - -static inline void stm32_freebuffer(struct stm32_ethmac_s *priv, - uint8_t *buffer) -{ - /* Free the buffer by adding it to the end of the free buffer list */ - - sq_addlast((sq_entry_t *)buffer, &priv->freeb); -} - -/**************************************************************************** - * Function: stm32_isfreebuffer - * - * Description: - * Return TRUE if the free buffer list is not empty. - * - * Input Parameters: - * priv - Reference to the driver state structure - * - * Returned Value: - * True if there are one or more buffers in the free buffer list; - * false if the free buffer list is empty - * - * Assumptions: - * None. - * - ****************************************************************************/ - -static inline bool stm32_isfreebuffer(struct stm32_ethmac_s *priv) -{ - /* Return TRUE if the free buffer list is not empty */ - - return !sq_empty(&priv->freeb); -} - -/**************************************************************************** - * Function: stm32_transmit - * - * Description: - * Start hardware transmission. Called either from the txdone interrupt - * handling or from watchdog based polling. - * - * Input Parameters: - * priv - Reference to the driver state structure - * - * Returned Value: - * OK on success; a negated errno on failure - * - * Assumptions: - * May or may not be called from an interrupt handler. In either case, - * global interrupts are disabled, either explicitly or indirectly through - * interrupt handling logic. - * - ****************************************************************************/ - -static int stm32_transmit(struct stm32_ethmac_s *priv) -{ - struct eth_txdesc_s *txdesc; - struct eth_txdesc_s *txfirst; - - /* The internal (optimal) network buffer size may be configured to be - * larger than the Ethernet buffer size. - */ - -#if OPTIMAL_ETH_BUFSIZE > CONFIG_STM32_ETH_BUFSIZE - uint8_t *buffer; - int bufcount; - int lastsize; - int i; -#endif - - /* Verify that the hardware is ready to send another packet. If we get - * here, then we are committed to sending a packet; Higher level logic - * must have assured that there is no transmission in progress. - */ - - txdesc = priv->txhead; - txfirst = txdesc; - - ninfo("d_len: %d d_buf: %p txhead: %p tdes0: %08" PRIx32 "\n", - priv->dev.d_len, priv->dev.d_buf, txdesc, txdesc->tdes0); - - DEBUGASSERT(txdesc && (txdesc->tdes0 & ETH_TDES0_OWN) == 0); - - /* Is the size to be sent greater than the size of the Ethernet buffer? */ - - DEBUGASSERT(priv->dev.d_len > 0 && priv->dev.d_buf != NULL); - -#if OPTIMAL_ETH_BUFSIZE > CONFIG_STM32_ETH_BUFSIZE - if (priv->dev.d_len > CONFIG_STM32_ETH_BUFSIZE) - { - /* Yes... how many buffers will be need to send the packet? */ - - bufcount = (priv->dev.d_len + (CONFIG_STM32_ETH_BUFSIZE - 1)) / - CONFIG_STM32_ETH_BUFSIZE; - lastsize = priv->dev.d_len - (bufcount - 1) * CONFIG_STM32_ETH_BUFSIZE; - - ninfo("bufcount: %d lastsize: %d\n", bufcount, lastsize); - - /* Set the first segment bit in the first TX descriptor */ - - txdesc->tdes0 |= ETH_TDES0_FS; - - /* Set up all but the last TX descriptor */ - - buffer = priv->dev.d_buf; - - for (i = 0; i < bufcount; i++) - { - /* This could be a normal event but the design does not handle it */ - - DEBUGASSERT((txdesc->tdes0 & ETH_TDES0_OWN) == 0); - - /* Set the Buffer1 address pointer */ - - txdesc->tdes2 = (uint32_t)buffer; - - /* Set the buffer size in all TX descriptors */ - - if (i == (bufcount - 1)) - { - /* This is the last segment. Set the last segment bit in the - * last TX descriptor and ask for an interrupt when this - * segment transfer completes. - */ - - txdesc->tdes0 |= (ETH_TDES0_LS | ETH_TDES0_IC); - - /* This segment is, most likely, of fractional buffersize */ - - txdesc->tdes1 = lastsize; - buffer += lastsize; - } - else - { - /* This is not the last segment. We don't want an interrupt - * when this segment transfer completes. - */ - - txdesc->tdes0 &= ~ETH_TDES0_IC; - - /* The size of the transfer is the whole buffer */ - - txdesc->tdes1 = CONFIG_STM32_ETH_BUFSIZE; - buffer += CONFIG_STM32_ETH_BUFSIZE; - } - - /* Give the descriptor to DMA */ - - txdesc->tdes0 |= ETH_TDES0_OWN; - txdesc = (struct eth_txdesc_s *)txdesc->tdes3; - } - } - else -#endif - { - /* The single descriptor is both the first and last segment. And we do - * want an interrupt when the transfer completes. - */ - - txdesc->tdes0 |= (ETH_TDES0_FS | ETH_TDES0_LS | ETH_TDES0_IC); - - /* Set frame size */ - - DEBUGASSERT(priv->dev.d_len <= CONFIG_STM32_ETH_BUFSIZE); - txdesc->tdes1 = priv->dev.d_len; - - /* Set the Buffer1 address pointer */ - - txdesc->tdes2 = (uint32_t)priv->dev.d_buf; - - /* Set OWN bit of the TX descriptor tdes0. This gives the buffer to - * Ethernet DMA - */ - - txdesc->tdes0 |= ETH_TDES0_OWN; - - /* Point to the next available TX descriptor */ - - txdesc = (struct eth_txdesc_s *)txdesc->tdes3; - } - - /* Remember where we left off in the TX descriptor chain */ - - priv->txhead = txdesc; - - /* Detach the buffer from priv->dev structure. That buffer is now - * "in-flight". - */ - - priv->dev.d_buf = NULL; - priv->dev.d_len = 0; - - /* If there is no other TX buffer, in flight, then remember the location - * of the TX descriptor. This is the location to check for TX done events. - */ - - if (!priv->txtail) - { - DEBUGASSERT(priv->inflight == 0); - priv->txtail = txfirst; - } - - /* Increment the number of TX transfer in-flight */ - - priv->inflight++; - - ninfo("txhead: %p txtail: %p inflight: %d\n", - priv->txhead, priv->txtail, priv->inflight); - - /* If all TX descriptors are in-flight, then we have to disable receive - * interrupts too. This is because receive events can trigger more - * un-stoppable transmit events. - */ - - if (priv->inflight >= CONFIG_STM32_ETH_NTXDESC) - { - stm32_disableint(priv, ETH_DMAINT_RI); - } - - /* Check if the TX Buffer unavailable flag is set */ - - if ((stm32_getreg(STM32_ETH_DMASR) & ETH_DMAINT_TBUI) != 0) - { - /* Clear TX Buffer unavailable flag */ - - stm32_putreg(ETH_DMAINT_TBUI, STM32_ETH_DMASR); - - /* Resume DMA transmission */ - - stm32_putreg(0, STM32_ETH_DMATPDR); - } - - /* Enable TX interrupts */ - - stm32_enableint(priv, ETH_DMAINT_TI); - - /* Setup the TX timeout watchdog (perhaps restarting the timer) */ - - wd_start(&priv->txtimeout, STM32_TXTIMEOUT, - stm32_txtimeout_expiry, (wdparm_t)priv); - return OK; -} - -/**************************************************************************** - * Function: stm32_txpoll - * - * Description: - * The transmitter is available, check if the network has any outgoing - * packets ready to send. This is a callback from devif_poll(). - * devif_poll() may be called: - * - * 1. When the preceding TX packet send is complete, - * 2. When the preceding TX packet send timesout and the interface is reset - * 3. During normal TX polling - * - * Input Parameters: - * dev - Reference to the NuttX driver state structure - * - * Returned Value: - * OK on success; a negated errno on failure - * - * Assumptions: - * May or may not be called from an interrupt handler. In either case, - * global interrupts are disabled, either explicitly or indirectly through - * interrupt handling logic. - * - ****************************************************************************/ - -static int stm32_txpoll(struct net_driver_s *dev) -{ - struct stm32_ethmac_s *priv = - (struct stm32_ethmac_s *)dev->d_private; - - DEBUGASSERT(priv->dev.d_buf != NULL); - - /* Send the packet */ - - stm32_transmit(priv); - DEBUGASSERT(dev->d_len == 0 && dev->d_buf == NULL); - - /* Check if the next TX descriptor is owned by the Ethernet DMA or - * CPU. We cannot perform the TX poll if we are unable to accept - * another packet for transmission. - * - * In a race condition, ETH_TDES0_OWN may be cleared BUT still - * not available because stm32_freeframe() has not yet run. If - * stm32_freeframe() has run, the buffer1 pointer (tdes2) will be - * nullified (and inflight should be < CONFIG_STM32_ETH_NTXDESC). - */ - - if ((priv->txhead->tdes0 & ETH_TDES0_OWN) != 0 || - priv->txhead->tdes2 != 0) - { - /* We have to terminate the poll if we have no more descriptors - * available for another transfer. - */ - - return -EBUSY; - } - - /* We have the descriptor, we can continue the poll. Allocate a new - * buffer for the poll. - */ - - dev->d_buf = stm32_allocbuffer(priv); - - /* We can't continue the poll if we have no buffers */ - - if (dev->d_buf == NULL) - { - /* Terminate the poll. */ - - return -ENOMEM; - } - - /* If zero is returned, the polling will continue until all connections - * have been examined. - */ - - return 0; -} - -/**************************************************************************** - * Function: stm32_dopoll - * - * Description: - * The function is called in order to perform an out-of-sequence TX poll. - * This is done: - * - * 1. After completion of a transmission (stm32_txdone), - * 2. When new TX data is available (stm32_txavail_process), and - * 3. After a TX timeout to restart the sending process - * (stm32_txtimeout_process). - * - * Input Parameters: - * priv - Reference to the driver state structure - * - * Returned Value: - * None - * - * Assumptions: - * Global interrupts are disabled by interrupt handling logic. - * - ****************************************************************************/ - -static void stm32_dopoll(struct stm32_ethmac_s *priv) -{ - struct net_driver_s *dev = &priv->dev; - - /* Check if the next TX descriptor is owned by the Ethernet DMA or - * CPU. We cannot perform the TX poll if we are unable to accept - * another packet for transmission. - * - * In a race condition, ETH_TDES0_OWN may be cleared BUT still - * not available because stm32_freeframe() has not yet run. If - * stm32_freeframe() has run, the buffer1 pointer (tdes2) will be - * nullified (and inflight should be < CONFIG_STM32_ETH_NTXDESC). - */ - - if ((priv->txhead->tdes0 & ETH_TDES0_OWN) == 0 && - priv->txhead->tdes2 == 0) - { - /* If we have the descriptor, then poll the network for new XMIT data. - * Allocate a buffer for the poll. - */ - - DEBUGASSERT(dev->d_len == 0 && dev->d_buf == NULL); - dev->d_buf = stm32_allocbuffer(priv); - - /* We can't poll if we have no buffers */ - - if (dev->d_buf) - { - devif_poll(dev, stm32_txpoll); - - /* We will, most likely end up with a buffer to be freed. But it - * might not be the same one that we allocated above. - */ - - if (dev->d_buf) - { - DEBUGASSERT(dev->d_len == 0); - stm32_freebuffer(priv, dev->d_buf); - dev->d_buf = NULL; - } - } - } -} - -/**************************************************************************** - * Function: stm32_enableint - * - * Description: - * Enable a "normal" interrupt - * - * Input Parameters: - * priv - Reference to the driver state structure - * - * Returned Value: - * None - * - * Assumptions: - * Global interrupts are disabled by interrupt handling logic. - * - ****************************************************************************/ - -static void stm32_enableint(struct stm32_ethmac_s *priv, - uint32_t ierbit) -{ - uint32_t regval; - - /* Enable the specified "normal" interrupt */ - - regval = stm32_getreg(STM32_ETH_DMAIER); - regval |= (ETH_DMAINT_NIS | ierbit); - stm32_putreg(regval, STM32_ETH_DMAIER); -} - -/**************************************************************************** - * Function: stm32_disableint - * - * Description: - * Disable a normal interrupt. - * - * Input Parameters: - * priv - Reference to the driver state structure - * - * Returned Value: - * None - * - * Assumptions: - * Global interrupts are disabled by interrupt handling logic. - * - ****************************************************************************/ - -static void stm32_disableint(struct stm32_ethmac_s *priv, - uint32_t ierbit) -{ - uint32_t regval; - - /* Disable the "normal" interrupt */ - - regval = stm32_getreg(STM32_ETH_DMAIER); - regval &= ~ierbit; - - /* Are all "normal" interrupts now disabled? */ - - if ((regval & ETH_DMAINT_NORMAL) == 0) - { - /* Yes.. disable normal interrupts */ - - regval &= ~ETH_DMAINT_NIS; - } - - stm32_putreg(regval, STM32_ETH_DMAIER); -} - -/**************************************************************************** - * Function: stm32_freesegment - * - * Description: - * The function is called when a frame is received using the DMA receive - * interrupt. It scans the RX descriptors to the received frame. - * - * Input Parameters: - * priv - Reference to the driver state structure - * - * Returned Value: - * None - * - * Assumptions: - * Global interrupts are disabled by interrupt handling logic. - * - ****************************************************************************/ - -static void stm32_freesegment(struct stm32_ethmac_s *priv, - struct eth_rxdesc_s *rxfirst, int segments) -{ - struct eth_rxdesc_s *rxdesc; - int i; - - ninfo("rxfirst: %p segments: %d\n", rxfirst, segments); - - /* Set OWN bit in RX descriptors. This gives the buffers back to DMA */ - - rxdesc = rxfirst; - for (i = 0; i < segments; i++) - { - rxdesc->rdes0 = ETH_RDES0_OWN; - rxdesc = (struct eth_rxdesc_s *)rxdesc->rdes3; - } - - /* Reset the segment management logic */ - - priv->rxcurr = NULL; - priv->segments = 0; - - /* Check if the RX Buffer unavailable flag is set */ - - if ((stm32_getreg(STM32_ETH_DMASR) & ETH_DMAINT_RBUI) != 0) - { - /* Clear RBUS Ethernet DMA flag */ - - stm32_putreg(ETH_DMAINT_RBUI, STM32_ETH_DMASR); - - /* Resume DMA reception */ - - stm32_putreg(0, STM32_ETH_DMARPDR); - } -} - -/**************************************************************************** - * Function: stm32_recvframe - * - * Description: - * The function is called when a frame is received using the DMA receive - * interrupt. It scans the RX descriptors of the received frame. - * - * NOTE: This function will silently discard any packets containing errors. - * - * Input Parameters: - * priv - Reference to the driver state structure - * - * Returned Value: - * OK if a packet was successfully returned; -EAGAIN if there are no - * further packets available - * - * Assumptions: - * Global interrupts are disabled by interrupt handling logic. - * - ****************************************************************************/ - -static int stm32_recvframe(struct stm32_ethmac_s *priv) -{ - struct eth_rxdesc_s *rxdesc; - struct eth_rxdesc_s *rxcurr; - uint8_t *buffer; - int i; - - ninfo("rxhead: %p rxcurr: %p segments: %d\n", - priv->rxhead, priv->rxcurr, priv->segments); - - /* Check if there are free buffers. We cannot receive new frames in this - * design unless there is at least one free buffer. - */ - - if (!stm32_isfreebuffer(priv)) - { - nerr("ERROR: No free buffers\n"); - return -ENOMEM; - } - - /* Scan descriptors owned by the CPU. Scan until: - * - * 1) We find a descriptor still owned by the DMA, - * 2) We have examined all of the RX descriptors, or - * 3) All of the TX descriptors are in flight. - * - * This last case is obscure. It is due to that fact that each packet - * that we receive can generate an unstoppable transmission. So we have - * to stop receiving when we can not longer transmit. In this case, the - * transmit logic should also have disabled further RX interrupts. - */ - - rxdesc = priv->rxhead; - for (i = 0; - (rxdesc->rdes0 & ETH_RDES0_OWN) == 0 && - i < CONFIG_STM32_ETH_NRXDESC && - priv->inflight < CONFIG_STM32_ETH_NTXDESC; - i++) - { - /* Check if this is the first segment in the frame */ - - if ((rxdesc->rdes0 & ETH_RDES0_FS) != 0 && - (rxdesc->rdes0 & ETH_RDES0_LS) == 0) - { - priv->rxcurr = rxdesc; - priv->segments = 1; - } - - /* Check if this is an intermediate segment in the frame */ - - else if (((rxdesc->rdes0 & ETH_RDES0_LS) == 0) && - ((rxdesc->rdes0 & ETH_RDES0_FS) == 0)) - { - priv->segments++; - } - - /* Otherwise, it is the last segment in the frame */ - - else - { - priv->segments++; - - /* Check if there is only one segment in the frame */ - - if (priv->segments == 1) - { - rxcurr = rxdesc; - } - else - { - rxcurr = priv->rxcurr; - } - - ninfo("rxhead: %p rxcurr: %p segments: %d\n", - priv->rxhead, priv->rxcurr, priv->segments); - - /* Check if any errors are reported in the frame */ - - if ((rxdesc->rdes0 & ETH_RDES0_ES) == 0) - { - struct net_driver_s *dev = &priv->dev; - - /* Get the Frame Length of the received packet: substruct 4 - * bytes of the CRC - */ - - dev->d_len = ((rxdesc->rdes0 & ETH_RDES0_FL_MASK) >> - ETH_RDES0_FL_SHIFT) - 4; - - if (priv->segments > 1 || - dev->d_len > CONFIG_STM32_ETH_BUFSIZE) - { - /* The Frame is to big, it spans segments */ - - nerr("ERROR: Dropped, RX descriptor Too big: %d in %d " - "segments\n", dev->d_len, priv->segments); - - stm32_freesegment(priv, rxcurr, priv->segments); - } - - else - { - /* Get a buffer from the free list. We don't even check if - * this is successful because we already assure the free - * list is not empty above. - */ - - buffer = stm32_allocbuffer(priv); - - /* Take the buffer from the RX descriptor of the first free - * segment, put it into the network device structure, then - * replace the buffer in the RX descriptor with the newly - * allocated buffer. - */ - - DEBUGASSERT(dev->d_buf == NULL); - dev->d_buf = (uint8_t *)rxcurr->rdes2; - rxcurr->rdes2 = (uint32_t)buffer; - -#ifdef CONFIG_STM32_ETH_TIMESTAMP_RX - priv->rxtimelow = rxcurr->rdes6; - priv->rxtimehigh = rxcurr->rdes7; -#endif - - /* Return success, remembering where we should re-start - * scanning and resetting the segment scanning logic - */ - - priv->rxhead = (struct eth_rxdesc_s *)rxdesc->rdes3; - stm32_freesegment(priv, rxcurr, priv->segments); - - ninfo("rxhead: %p d_buf: %p d_len: %d\n", - priv->rxhead, dev->d_buf, dev->d_len); - - return OK; - } - } - else - { - /* Drop the frame that contains the errors, reset the segment - * scanning logic, and continue scanning with the next frame. - */ - - nerr("ERROR: Dropped, RX descriptor errors: %08" PRIx32 "\n", - rxdesc->rdes0); - stm32_freesegment(priv, rxcurr, priv->segments); - } - } - - /* Try the next descriptor */ - - rxdesc = (struct eth_rxdesc_s *)rxdesc->rdes3; - } - - /* We get here after all of the descriptors have been scanned or when - * rxdesc points to the first descriptor owned by the DMA. Remember - * where we left off. - */ - - priv->rxhead = rxdesc; - - ninfo("rxhead: %p rxcurr: %p segments: %d\n", - priv->rxhead, priv->rxcurr, priv->segments); - - return -EAGAIN; -} - -/**************************************************************************** - * Function: stm32_receive - * - * Description: - * An interrupt was received indicating the availability of a new RX packet - * - * Input Parameters: - * priv - Reference to the driver state structure - * - * Returned Value: - * None - * - * Assumptions: - * Global interrupts are disabled by interrupt handling logic. - * - ****************************************************************************/ - -static void stm32_receive(struct stm32_ethmac_s *priv) -{ - struct net_driver_s *dev = &priv->dev; - - /* Loop while while stm32_recvframe() successfully retrieves valid - * Ethernet frames. - */ - - while (stm32_recvframe(priv) == OK) - { -#ifdef CONFIG_NET_PKT - /* When packet sockets are enabled, feed the frame into the tap */ - - pkt_input(&priv->dev); -#endif - - /* Check if the packet is a valid size for the network buffer - * configuration (this should not happen) - */ - - if (dev->d_len > CONFIG_NET_ETH_PKTSIZE) - { - nwarn("WARNING: DROPPED Too big: %d\n", dev->d_len); - - /* Free dropped packet buffer */ - - if (dev->d_buf) - { - stm32_freebuffer(priv, dev->d_buf); - dev->d_buf = NULL; - dev->d_len = 0; - } - - continue; - } - -#ifdef CONFIG_STM32_ETH_TIMESTAMP_RX - stm32_eth_ptp_convert_rxtime(priv); -#endif - - /* We only accept IP packets of the configured type and ARP packets */ - -#ifdef CONFIG_NET_IPv4 - if (BUF->type == HTONS(ETHTYPE_IP)) - { - ninfo("IPv4 frame\n"); - - /* Receive an IPv4 packet from the network device */ - - ipv4_input(&priv->dev); - - /* If the above function invocation resulted in data that should be - * sent out on the network, d_len field will set to a value > 0. - */ - - if (priv->dev.d_len > 0) - { - /* And send the packet */ - - stm32_transmit(priv); - } - } - else -#endif -#ifdef CONFIG_NET_IPv6 - if (BUF->type == HTONS(ETHTYPE_IP6)) - { - ninfo("IPv6 frame\n"); - - /* Give the IPv6 packet to the network layer */ - - ipv6_input(&priv->dev); - - /* If the above function invocation resulted in data that should be - * sent out on the network, d_len field will set to a value > 0. - */ - - if (priv->dev.d_len > 0) - { - /* And send the packet */ - - stm32_transmit(priv); - } - } - else -#endif -#ifdef CONFIG_NET_ARP - if (BUF->type == HTONS(ETHTYPE_ARP)) - { - ninfo("ARP frame\n"); - - /* Handle ARP packet */ - - arp_input(&priv->dev); - - /* If the above function invocation resulted in data that should be - * sent out on the network, d_len field will set to a value > 0. - */ - - if (priv->dev.d_len > 0) - { - stm32_transmit(priv); - } - } - else -#endif - { - nerr("ERROR: Dropped, Unknown type: %04x\n", BUF->type); - } - - /* We are finished with the RX buffer. NOTE: If the buffer is - * reused for transmission, the dev->d_buf field will have been - * nullified. - */ - - if (dev->d_buf) - { - /* Free the receive packet buffer */ - - stm32_freebuffer(priv, dev->d_buf); - dev->d_buf = NULL; - dev->d_len = 0; - } - } -} - -/**************************************************************************** - * Function: stm32_freeframe - * - * Description: - * Scans the TX descriptors and frees the buffers of completed transfers. - * - * Input Parameters: - * priv - Reference to the driver state structure - * - * Returned Value: - * None. - * - * Assumptions: - * Global interrupts are disabled by interrupt handling logic. - * - ****************************************************************************/ - -static void stm32_freeframe(struct stm32_ethmac_s *priv) -{ - struct eth_txdesc_s *txdesc; - - ninfo("txhead: %p txtail: %p inflight: %d\n", - priv->txhead, priv->txtail, priv->inflight); - - /* Scan for "in-flight" descriptors owned by the CPU */ - - txdesc = priv->txtail; - if (txdesc) - { - DEBUGASSERT(priv->inflight > 0); - - while ((txdesc->tdes0 & ETH_TDES0_OWN) == 0) - { - /* There should be a buffer assigned to all in-flight - * TX descriptors. - */ - - ninfo("txtail: %p tdes0: %08" PRIx32 - " tdes2: %08" PRIx32 " tdes3: %08" PRIx32 "\n", - txdesc, txdesc->tdes0, txdesc->tdes2, txdesc->tdes3); - - DEBUGASSERT(txdesc->tdes2 != 0); - - /* Check if this is the first segment of a TX frame. */ - - if ((txdesc->tdes0 & ETH_TDES0_FS) != 0) - { - /* Yes.. Free the buffer */ - - stm32_freebuffer(priv, (uint8_t *)txdesc->tdes2); - } - - /* In any event, make sure that TDES2 is nullified. */ - - txdesc->tdes2 = 0; - - /* Check if this is the last segment of a TX frame */ - - if ((txdesc->tdes0 & ETH_TDES0_LS) != 0) - { - /* Yes.. Decrement the number of frames "in-flight". */ - - priv->inflight--; - - /* If all of the TX descriptors were in-flight, - * then RX interrupts may have been disabled... - * we can re-enable them now. - */ - - stm32_enableint(priv, ETH_DMAINT_RI); - - /* If there are no more frames in-flight, then bail. */ - - if (priv->inflight <= 0) - { - priv->txtail = NULL; - priv->inflight = 0; - return; - } - } - - /* Try the next descriptor in the TX chain */ - - txdesc = (struct eth_txdesc_s *)txdesc->tdes3; - } - - /* We get here if (1) there are still frames "in-flight". Remember - * where we left off. - */ - - priv->txtail = txdesc; - - ninfo("txhead: %p txtail: %p inflight: %d\n", - priv->txhead, priv->txtail, priv->inflight); - } -} - -/**************************************************************************** - * Function: stm32_txdone - * - * Description: - * An interrupt was received indicating that the last TX packet - * transfer(s) are complete. - * - * Input Parameters: - * priv - Reference to the driver state structure - * - * Returned Value: - * None - * - * Assumptions: - * Global interrupts are disabled by the watchdog logic. - * - ****************************************************************************/ - -static void stm32_txdone(struct stm32_ethmac_s *priv) -{ - DEBUGASSERT(priv->txtail != NULL); - - /* Scan the TX descriptor change, returning buffers to free list */ - - stm32_freeframe(priv); - - /* If no further xmits are pending, then cancel the TX timeout */ - - if (priv->inflight <= 0) - { - /* Cancel the TX timeout */ - - wd_cancel(&priv->txtimeout); - - /* And disable further TX interrupts. */ - - stm32_disableint(priv, ETH_DMAINT_TI); - } - - /* Then poll the network for new XMIT data */ - - stm32_dopoll(priv); -} - -/**************************************************************************** - * Function: stm32_interrupt_work - * - * Description: - * Perform interrupt related work from the worker thread - * - * Input Parameters: - * arg - The argument passed when work_queue() was called. - * - * Returned Value: - * OK on success - * - * Assumptions: - * Ethernet interrupts are disabled - * - ****************************************************************************/ - -static void stm32_interrupt_work(void *arg) -{ - struct stm32_ethmac_s *priv = (struct stm32_ethmac_s *)arg; - uint32_t dmasr; - - DEBUGASSERT(priv); - - /* Process pending Ethernet interrupts */ - - net_lock(); - - /* Get the DMA interrupt status bits (no MAC interrupts are expected) */ - - dmasr = stm32_getreg(STM32_ETH_DMASR); - - /* Mask only enabled interrupts. This depends on the fact that the - * interrupt related bits (0-16) correspond in these two registers. - */ - - dmasr &= stm32_getreg(STM32_ETH_DMAIER); - - /* Check if there are pending "normal" interrupts */ - - if ((dmasr & ETH_DMAINT_NIS) != 0) - { - /* Yes.. Check if we received an incoming packet, if so, call - * stm32_receive() - */ - - if ((dmasr & ETH_DMAINT_RI) != 0) - { - /* Clear the pending receive interrupt */ - - stm32_putreg(ETH_DMAINT_RI, STM32_ETH_DMASR); - - /* Handle the received package */ - - stm32_receive(priv); - } - - /* Check if a packet transmission just completed. If so, call - * stm32_txdone(). This may disable further TX interrupts if there - * are no pending transmissions. - */ - - if ((dmasr & ETH_DMAINT_TI) != 0) - { - /* Clear the pending receive interrupt */ - - stm32_putreg(ETH_DMAINT_TI, STM32_ETH_DMASR); - - /* Check if there are pending transmissions */ - - stm32_txdone(priv); - } - - /* Clear the pending normal summary interrupt */ - - stm32_putreg(ETH_DMAINT_NIS, STM32_ETH_DMASR); - } - - /* Check if there are pending "abnormal" interrupts */ - - if ((dmasr & ETH_DMAINT_AIS) != 0) - { - /* Just let the user know what happened */ - - nerr("ERROR: Abnormal event(s): %08" PRIx32 "\n", dmasr); - - /* Clear all pending abnormal events */ - - stm32_putreg(ETH_DMAINT_ABNORMAL, STM32_ETH_DMASR); - - /* Clear the pending abnormal summary interrupt */ - - stm32_putreg(ETH_DMAINT_AIS, STM32_ETH_DMASR); - - /* In case of any error that stops the DMA, reset the MAC. */ - - if (dmasr & (ETH_DMAINT_FBEI | ETH_DMAINT_RPSI | - ETH_DMAINT_TJTI | ETH_DMAINT_TPSI)) - { - /* As per the datasheet's recommendation, the MAC - * needs to be reset for all fatal errors. The - * scheduled job will take the interface down and - * up again. - */ - - work_queue(ETHWORK, &priv->irqwork, stm32_txtimeout_work, priv, 0); - - /* Interrupts need to remain disabled, no other - * processing will take place. After reset - * everything will be restored. - */ - - net_unlock(); - return; - } - } - - net_unlock(); - - /* Re-enable Ethernet interrupts at the NVIC */ - - up_enable_irq(STM32_IRQ_ETH); -} - -/**************************************************************************** - * Function: stm32_interrupt - * - * Description: - * Hardware interrupt handler - * - * Input Parameters: - * irq - Number of the IRQ that generated the interrupt - * context - Interrupt register state save info (architecture-specific) - * - * Returned Value: - * OK on success - * - * Assumptions: - * - ****************************************************************************/ - -static int stm32_interrupt(int irq, void *context, void *arg) -{ - struct stm32_ethmac_s *priv = &g_stm32ethmac[0]; - uint32_t dmasr; - - /* Get the DMA interrupt status bits (no MAC interrupts are expected) */ - - dmasr = stm32_getreg(STM32_ETH_DMASR); - if (dmasr != 0) - { - /* Disable further Ethernet interrupts. Because Ethernet interrupts - * are also disabled if the TX timeout event occurs, there can be no - * race condition here. - */ - - up_disable_irq(STM32_IRQ_ETH); - - /* Check if a packet transmission just completed. */ - - if ((dmasr & ETH_DMAINT_TI) != 0) - { - /* If a TX transfer just completed, then cancel the TX timeout so - * there will be no race condition between any subsequent timeout - * expiration and the deferred interrupt processing. - */ - - wd_cancel(&priv->txtimeout); - } - - /* Schedule to perform the interrupt processing on the worker thread. */ - - work_queue(ETHWORK, &priv->irqwork, stm32_interrupt_work, priv, 0); - } - - return OK; -} - -/**************************************************************************** - * Function: stm32_txtimeout_work - * - * Description: - * Perform TX timeout related work from the worker thread - * - * Input Parameters: - * arg - The argument passed when work_queue() as called. - * - * Returned Value: - * OK on success - * - * Assumptions: - * Ethernet interrupts are disabled - * - ****************************************************************************/ - -static void stm32_txtimeout_work(void *arg) -{ - struct stm32_ethmac_s *priv = (struct stm32_ethmac_s *)arg; - - /* Reset the hardware. Just take the interface down, then back up again. */ - - net_lock(); - stm32_ifdown(&priv->dev); - stm32_ifup(&priv->dev); - - /* Then poll for new XMIT data */ - - stm32_dopoll(priv); - net_unlock(); -} - -/**************************************************************************** - * Function: stm32_txtimeout_expiry - * - * Description: - * Our TX watchdog timed out. Called from the timer interrupt handler. - * The last TX never completed. Reset the hardware and start again. - * - * Input Parameters: - * arg - The argument - * - * Returned Value: - * None - * - * Assumptions: - * Global interrupts are disabled by the watchdog logic. - * - ****************************************************************************/ - -static void stm32_txtimeout_expiry(wdparm_t arg) -{ - struct stm32_ethmac_s *priv = (struct stm32_ethmac_s *)arg; - - nerr("ERROR: Timeout!\n"); - - /* Disable further Ethernet interrupts. This will prevent some race - * conditions with interrupt work. There is still a potential race - * condition with interrupt work that is already queued and in progress. - * - * Interrupts will be re-enabled when stm32_ifup() is called. - */ - - up_disable_irq(STM32_IRQ_ETH); - - /* Schedule to perform the TX timeout processing on the worker thread, - * perhaps canceling any pending IRQ processing. - */ - - work_queue(ETHWORK, &priv->irqwork, stm32_txtimeout_work, priv, 0); -} - -/**************************************************************************** - * Function: stm32_ifup - * - * Description: - * NuttX Callback: Bring up the Ethernet interface when an IP address is - * provided - * - * Input Parameters: - * dev - Reference to the NuttX driver state structure - * - * Returned Value: - * Zero is returned on success; a negated errno value is returned on any - * failure. - * - * Assumptions: - * - ****************************************************************************/ - -static int stm32_ifup(struct net_driver_s *dev) -{ - struct stm32_ethmac_s *priv = - (struct stm32_ethmac_s *)dev->d_private; - int ret; - -#ifdef CONFIG_NET_IPv4 - ninfo("Bringing up: %u.%u.%u.%u\n", - ip4_addr1(dev->d_ipaddr), ip4_addr2(dev->d_ipaddr), - ip4_addr3(dev->d_ipaddr), ip4_addr4(dev->d_ipaddr)); -#endif -#ifdef CONFIG_NET_IPv6 - ninfo("Bringing up: %04x:%04x:%04x:%04x:%04x:%04x:%04x:%04x\n", - dev->d_ipv6addr[0], dev->d_ipv6addr[1], dev->d_ipv6addr[2], - dev->d_ipv6addr[3], dev->d_ipv6addr[4], dev->d_ipv6addr[5], - dev->d_ipv6addr[6], dev->d_ipv6addr[7]); -#endif - - /* Configure the Ethernet interface for DMA operation. */ - - ret = stm32_ethconfig(priv); - if (ret < 0) - { - return ret; - } - -#ifdef CONFIG_STM32_ETH_PTP - /* Enable PTP timer */ - - stm32_eth_ptp_init(0); - -#ifdef CONFIG_STM32_ETH_PTP_RTC_HIRES - if (!g_rtc_enabled) - { - /* Transfer time from system low-resolution timer to PTP basetime */ - - struct timespec ts; - clock_gettime(CLOCK_REALTIME, &ts); - up_rtc_settime(&ts); - g_rtc_enabled = true; - } -#endif /* CONFIG_STM32_ETH_PTP_RTC_HIRES */ - -#endif /* CONFIG_STM32_ETH_PTP */ - - /* Enable the Ethernet interrupt */ - - priv->ifup = true; - up_enable_irq(STM32_IRQ_ETH); - - stm32_checksetup(); - netdev_carrier_on(dev); - return OK; -} - -/**************************************************************************** - * Function: stm32_ifdown - * - * Description: - * NuttX Callback: Stop the interface. - * - * Input Parameters: - * dev - Reference to the NuttX driver state structure - * - * Returned Value: - * Returns zero on success; a negated errno value is returned on any - * failure. - * - * Assumptions: - * - ****************************************************************************/ - -static int stm32_ifdown(struct net_driver_s *dev) -{ - struct stm32_ethmac_s *priv = - (struct stm32_ethmac_s *)dev->d_private; - irqstate_t flags; - int ret = OK; - - ninfo("Taking the network down\n"); - - /* Disable the Ethernet interrupt */ - - flags = enter_critical_section(); - up_disable_irq(STM32_IRQ_ETH); - - /* Cancel the TX timeout timers */ - - wd_cancel(&priv->txtimeout); - -#ifdef CONFIG_STM32_ETH_PTP_RTC_HIRES - if (g_rtc_enabled) - { - /* Transfer back to system low-resolution timer */ - - struct timespec ts; - up_rtc_gettime(&ts); - g_rtc_enabled = false; - clock_settime(CLOCK_REALTIME, &ts); - } -#endif - - /* Put the EMAC in its reset, non-operational state. This should be - * a known configuration that will guarantee the stm32_ifup() always - * successfully brings the interface back up. - */ - - ret = stm32_ethreset(priv); - if (ret < 0) - { - nerr("ERROR: stm32_ethreset failed (timeout), " - "still assuming it's going down.\n"); - } - - /* Mark the device "down" */ - - priv->ifup = false; - netdev_carrier_off(dev); - leave_critical_section(flags); - return ret; -} - -/**************************************************************************** - * Function: stm32_txavail_work - * - * Description: - * Perform an out-of-cycle poll on the worker thread. - * - * Input Parameters: - * arg - Reference to the NuttX driver state structure (cast to void*) - * - * Returned Value: - * None - * - * Assumptions: - * Called on the higher priority worker thread. - * - ****************************************************************************/ - -static void stm32_txavail_work(void *arg) -{ - struct stm32_ethmac_s *priv = (struct stm32_ethmac_s *)arg; - - ninfo("ifup: %d\n", priv->ifup); - - /* Ignore the notification if the interface is not yet up */ - - net_lock(); - if (priv->ifup) - { - /* Poll the network for new XMIT data */ - - stm32_dopoll(priv); - } - - net_unlock(); -} - -/**************************************************************************** - * Function: stm32_txavail - * - * Description: - * Driver callback invoked when new TX data is available. This is a - * stimulus perform an out-of-cycle poll and, thereby, reduce the TX - * latency. - * - * Input Parameters: - * dev - Reference to the NuttX driver state structure - * - * Returned Value: - * None - * - * Assumptions: - * Called in normal user mode - * - ****************************************************************************/ - -static int stm32_txavail(struct net_driver_s *dev) -{ - struct stm32_ethmac_s *priv = - (struct stm32_ethmac_s *)dev->d_private; - - /* Is our single work structure available? It may not be if there are - * pending interrupt actions and we will have to ignore the Tx - * availability action. - */ - - if (work_available(&priv->pollwork)) - { - /* Schedule to serialize the poll on the worker thread. */ - - work_queue(ETHWORK, &priv->pollwork, stm32_txavail_work, priv, 0); - } - - return OK; -} - -/**************************************************************************** - * Function: stm32_calcethcrc - * - * Description: - * Function to calculate the CRC used by STM32 to check an ethernet frame - * - * Input Parameters: - * data - the data to be checked - * length - length of the data - * - * Returned Value: - * None - * - * Assumptions: - * - ****************************************************************************/ - -#if defined(CONFIG_NET_MCASTGROUP) || defined(CONFIG_NET_ICMPv6) -static uint32_t stm32_calcethcrc(const uint8_t *data, size_t length) -{ - uint32_t crc = 0xffffffff; - size_t i; - int j; - - for (i = 0; i < length; i++) - { - for (j = 0; j < 8; j++) - { - if (((crc >> 31) ^ (data[i] >> j)) & 0x01) - { - /* x^26+x^23+x^22+x^16+x^12+x^11+x^10+x^8+x^7+x^5+x^4+x^2+x+1 */ - - crc = (crc << 1) ^ 0x04c11db7; - } - else - { - crc = crc << 1; - } - } - } - - return ~crc; -} -#endif - -/**************************************************************************** - * Function: stm32_addmac - * - * Description: - * NuttX Callback: Add the specified MAC address to the hardware multicast - * address filtering - * - * Input Parameters: - * dev - Reference to the NuttX driver state structure - * mac - The MAC address to be added - * - * Returned Value: - * None - * - * Assumptions: - * - ****************************************************************************/ - -#if defined(CONFIG_NET_MCASTGROUP) || defined(CONFIG_NET_ICMPv6) -static int stm32_addmac(struct net_driver_s *dev, const uint8_t *mac) -{ - uint32_t crc; - uint32_t hashindex; - uint32_t temp; - uint32_t registeraddress; - - ninfo("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n", - mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]); - - /* Add the MAC address to the hardware multicast hash table */ - - crc = stm32_calcethcrc(mac, 6); - - hashindex = (crc >> 26) & 0x3f; - - if (hashindex > 31) - { - registeraddress = STM32_ETH_MACHTHR; - hashindex -= 32; - } - else - { - registeraddress = STM32_ETH_MACHTLR; - } - - temp = stm32_getreg(registeraddress); - temp |= 1 << hashindex; - stm32_putreg(temp, registeraddress); - - temp = stm32_getreg(STM32_ETH_MACFFR); - temp |= (ETH_MACFFR_HM | ETH_MACFFR_HPF); - stm32_putreg(temp, STM32_ETH_MACFFR); - - return OK; -} -#endif /* CONFIG_NET_MCASTGROUP || CONFIG_NET_ICMPv6 */ - -/**************************************************************************** - * Function: stm32_rmmac - * - * Description: - * NuttX Callback: Remove the specified MAC address from the hardware - * multicast address filtering - * - * Input Parameters: - * dev - Reference to the NuttX driver state structure - * mac - The MAC address to be removed - * - * Returned Value: - * None - * - * Assumptions: - * - ****************************************************************************/ - -#ifdef CONFIG_NET_MCASTGROUP -static int stm32_rmmac(struct net_driver_s *dev, const uint8_t *mac) -{ - uint32_t crc; - uint32_t hashindex; - uint32_t temp; - uint32_t registeraddress; - - ninfo("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n", - mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]); - - /* Remove the MAC address to the hardware multicast hash table */ - - crc = stm32_calcethcrc(mac, 6); - - hashindex = (crc >> 26) & 0x3f; - - if (hashindex > 31) - { - registeraddress = STM32_ETH_MACHTHR; - hashindex -= 32; - } - else - { - registeraddress = STM32_ETH_MACHTLR; - } - - temp = stm32_getreg(registeraddress); - temp &= ~(1 << hashindex); - stm32_putreg(temp, registeraddress); - - /* If there is no address registered any more, delete multicast filtering */ - - if (stm32_getreg(STM32_ETH_MACHTHR) == 0 && - stm32_getreg(STM32_ETH_MACHTLR) == 0) - { - temp = stm32_getreg(STM32_ETH_MACFFR); - temp &= ~(ETH_MACFFR_HM | ETH_MACFFR_HPF); - stm32_putreg(temp, STM32_ETH_MACFFR); - } - - return OK; -} -#endif - -/**************************************************************************** - * Function: stm32_txdescinit - * - * Description: - * Initializes the DMA TX descriptors in chain mode. - * - * Input Parameters: - * priv - Reference to the driver state structure - * - * Returned Value: - * None - * - * Assumptions: - * - ****************************************************************************/ - -static void stm32_txdescinit(struct stm32_ethmac_s *priv, - struct eth_txdesc_s *txtable) -{ - struct eth_txdesc_s *txdesc; - int i; - - /* priv->txhead point to the first, available TX descriptor in the chain. - * Set the priv->txhead pointer to the first descriptor in the table. - */ - - priv->txhead = txtable; - - /* priv->txtail will point to the first segment of the oldest pending - * "in-flight" TX transfer. NULL means that there are no active TX - * transfers. - */ - - priv->txtail = NULL; - priv->inflight = 0; - - /* Initialize each TX descriptor */ - - for (i = 0; i < CONFIG_STM32_ETH_NTXDESC; i++) - { - txdesc = &txtable[i]; - - /* Set Second Address Chained bit */ - - txdesc->tdes0 = ETH_TDES0_TCH; - -#ifdef CHECKSUM_BY_HARDWARE - /* Enable the checksum insertion for the TX frames */ - - txdesc->tdes0 |= ETH_TDES0_CIC_ALL; -#endif - - /* Clear Buffer1 address pointer (buffers will be assigned as they - * are used) - */ - - txdesc->tdes2 = 0; - - /* Initialize the next descriptor with - * the Next Descriptor Polling Enable - */ - - if (i < (CONFIG_STM32_ETH_NTXDESC - 1)) - { - /* Set next descriptor address register with next descriptor base - * address - */ - - txdesc->tdes3 = (uint32_t)&txtable[i + 1]; - } - else - { - /* For last descriptor, set next descriptor address register equal - * to the first descriptor base address - */ - - txdesc->tdes3 = (uint32_t)txtable; - } - } - - /* Set Transmit Descriptor List Address Register */ - - stm32_putreg((uint32_t)txtable, STM32_ETH_DMATDLAR); -} - -/**************************************************************************** - * Function: stm32_rxdescinit - * - * Description: - * Initializes the DMA RX descriptors in chain mode. - * - * Input Parameters: - * priv - Reference to the driver state structure - * - * Returned Value: - * None - * - * Assumptions: - * - ****************************************************************************/ - -static void stm32_rxdescinit(struct stm32_ethmac_s *priv, - struct eth_rxdesc_s *rxtable, - uint8_t *rxbuffer) -{ - struct eth_rxdesc_s *rxdesc; - int i; - - /* priv->rxhead will point to the first, RX descriptor in the chain. - * This will be where we receive the first incomplete frame. - */ - - priv->rxhead = rxtable; - - /* If we accumulate the frame in segments, priv->rxcurr points to the - * RX descriptor of the first segment in the current TX frame. - */ - - priv->rxcurr = NULL; - priv->segments = 0; - - /* Initialize each TX descriptor */ - - for (i = 0; i < CONFIG_STM32_ETH_NRXDESC; i++) - { - rxdesc = &rxtable[i]; - - /* Set Own bit of the RX descriptor rdes0 */ - - rxdesc->rdes0 = ETH_RDES0_OWN; - - /* Set Buffer1 size and Second Address Chained bit and enabled DMA - * RX desc receive interrupt - */ - - rxdesc->rdes1 = ETH_RDES1_RCH | (uint32_t)CONFIG_STM32_ETH_BUFSIZE; - - /* Set Buffer1 address pointer */ - - rxdesc->rdes2 = (uint32_t)&rxbuffer[i * CONFIG_STM32_ETH_BUFSIZE]; - - /* Initialize the next descriptor with - * the Next Descriptor Polling Enable - */ - - if (i < (CONFIG_STM32_ETH_NRXDESC - 1)) - { - /* Set next descriptor address register with next descriptor base - * address - */ - - rxdesc->rdes3 = (uint32_t)&rxtable[i + 1]; - } - else - { - /* For last descriptor, set next descriptor address register equal - * to the first descriptor base address - */ - - rxdesc->rdes3 = (uint32_t)rxtable; - } - } - - /* Set Receive Descriptor List Address Register */ - - stm32_putreg((uint32_t)rxtable, STM32_ETH_DMARDLAR); -} - -/**************************************************************************** - * Function: stm32_ioctl - * - * Description: - * Executes the SIOCxMIIxxx command and responds using the request struct - * that must be provided as its 2nd parameter. - * - * When called with SIOCGMIIPHY it will get the PHY address for the device - * and write it to the req->phy_id field of the request struct. - * - * When called with SIOCGMIIREG it will read a register of the PHY that is - * specified using the req->reg_no struct field and then write its output - * to the req->val_out field. - * - * When called with SIOCSMIIREG it will write to a register of the PHY that - * is specified using the req->reg_no struct field and use req->val_in as - * its input. - * - * Input Parameters: - * dev - Ethernet device structure - * cmd - SIOCxMIIxxx command code - * arg - Request structure also used to return values - * - * Returned Value: Negated errno on failure. - * - * Assumptions: - * - ****************************************************************************/ - -#ifdef CONFIG_NETDEV_IOCTL -static int stm32_ioctl(struct net_driver_s *dev, int cmd, unsigned long arg) -{ -#if defined(CONFIG_NETDEV_PHY_IOCTL) && defined(CONFIG_ARCH_PHY_INTERRUPT) - struct stm32_ethmac_s *priv = - (struct stm32_ethmac_s *)dev->d_private; -#endif - int ret; - - switch (cmd) - { -#ifdef CONFIG_NETDEV_PHY_IOCTL -#ifdef CONFIG_ARCH_PHY_INTERRUPT - case SIOCMIINOTIFY: /* Set up for PHY event notifications */ - { - struct mii_ioctl_notify_s *req = - (struct mii_ioctl_notify_s *)((uintptr_t)arg); - - ret = phy_notify_subscribe(dev->d_ifname, req->pid, &req->event); - if (ret == OK) - { - /* Enable PHY link up/down interrupts */ - - ret = stm32_phyintenable(priv); - } - } - break; -#endif - - case SIOCGMIIPHY: /* Get MII PHY address */ - { - struct mii_ioctl_data_s *req = - (struct mii_ioctl_data_s *)((uintptr_t)arg); - req->phy_id = CONFIG_STM32_PHYADDR; - ret = OK; - } - break; - - case SIOCGMIIREG: /* Get register from MII PHY */ - { - struct mii_ioctl_data_s *req = - (struct mii_ioctl_data_s *)((uintptr_t)arg); - ret = stm32_phyread(req->phy_id, req->reg_num, &req->val_out); - } - break; - - case SIOCSMIIREG: /* Set register in MII PHY */ - { - struct mii_ioctl_data_s *req = - (struct mii_ioctl_data_s *)((uintptr_t)arg); - ret = stm32_phywrite(req->phy_id, req->reg_num, req->val_in); - } - break; -#endif /* CONFIG_NETDEV_PHY_IOCTL */ - - default: - ret = -ENOTTY; - break; - } - - return ret; -} -#endif /* CONFIG_NETDEV_IOCTL */ - -/**************************************************************************** - * Function: stm32_phyintenable - * - * Description: - * Enable link up/down PHY interrupts. The interrupt protocol is like this: - * - * - Interrupt status is cleared when the interrupt is enabled. - * - Interrupt occurs. Interrupt is disabled (at the processor level) when - * is received. - * - Interrupt status is cleared when the interrupt is re-enabled. - * - * Input Parameters: - * priv - A reference to the private driver state structure - * - * Returned Value: - * OK on success; Negated errno (-ETIMEDOUT) on failure. - * - ****************************************************************************/ - -#if defined(CONFIG_NETDEV_PHY_IOCTL) && defined(CONFIG_ARCH_PHY_INTERRUPT) -static int stm32_phyintenable(struct stm32_ethmac_s *priv) -{ - uint16_t phyval; - int ret; - - ret = stm32_phyread(CONFIG_STM32_PHYADDR, MII_INT_REG, &phyval); - if (ret == OK) - { - /* Enable link up/down interrupts */ - -#ifdef CONFIG_ETH0_PHY_DP83848C - ret = stm32_phywrite(CONFIG_STM32_PHYADDR, MII_DP83848C_MICR, - MII_DP83848C_INT_EN | MII_DP83848C_INT_OEN); -#endif - ret = stm32_phywrite(CONFIG_STM32_PHYADDR, MII_INT_REG, - (phyval & ~MII_INT_CLREN) | MII_INT_SETEN); - } - - return ret; -} -#endif - -/**************************************************************************** - * Function: stm32_phyread - * - * Description: - * Read a PHY register. - * - * Input Parameters: - * phydevaddr - The PHY device address - * phyregaddr - The PHY register address - * value - The location to return the 16-bit PHY register value. - * - * Returned Value: - * OK on success; Negated errno on failure. - * - * Assumptions: - * - ****************************************************************************/ - -#if defined(CONFIG_STM32_AUTONEG) || defined(CONFIG_NETDEV_PHY_IOCTL) || \ - defined(CONFIG_ETH0_PHY_DM9161) -static int stm32_phyread(uint16_t phydevaddr, - uint16_t phyregaddr, uint16_t *value) -{ - volatile uint32_t timeout; - uint32_t regval; - - regval = stm32_getreg(STM32_ETH_MACMIIAR); - - /* Clear the busy bit before accessing the MACMIIAR register. */ - - regval &= ~ETH_MACMIIAR_MB; - stm32_putreg(regval, STM32_ETH_MACMIIAR); - - /* Configure the MACMIIAR register, - * preserving CSR Clock Range CR[2:0] bits - */ - - regval &= ETH_MACMIIAR_CR_MASK; - - /* Set the PHY device address, PHY register address, and set the busy bit. - * the ETH_MACMIIAR_MW is clear, indicating a read operation. - */ - - regval |= (phydevaddr << ETH_MACMIIAR_PA_SHIFT) & ETH_MACMIIAR_PA_MASK; - regval |= (phyregaddr << ETH_MACMIIAR_MR_SHIFT) & ETH_MACMIIAR_MR_MASK; - regval |= ETH_MACMIIAR_MB; - - stm32_putreg(regval, STM32_ETH_MACMIIAR); - - /* Wait for the transfer to complete */ - - for (timeout = 0; timeout < PHY_READ_TIMEOUT; timeout++) - { - if ((stm32_getreg(STM32_ETH_MACMIIAR) & ETH_MACMIIAR_MB) == 0) - { - *value = (uint16_t)stm32_getreg(STM32_ETH_MACMIIDR); - return OK; - } - } - - nerr("ERROR: MII transfer timed out: phydevaddr: %04x phyregaddr: %04x\n", - phydevaddr, phyregaddr); - - return -ETIMEDOUT; -} -#endif - -/**************************************************************************** - * Function: stm32_phywrite - * - * Description: - * Write to a PHY register. - * - * Input Parameters: - * phydevaddr - The PHY device address - * phyregaddr - The PHY register address - * value - The 16-bit value to write to the PHY register value. - * - * Returned Value: - * OK on success; Negated errno on failure. - * - * Assumptions: - * - ****************************************************************************/ - -static int stm32_phywrite(uint16_t phydevaddr, - uint16_t phyregaddr, uint16_t value) -{ - volatile uint32_t timeout; - uint32_t regval; - - regval = stm32_getreg(STM32_ETH_MACMIIAR); - - /* Clear the busy bit before accessing the MACMIIAR register. */ - - regval &= ~ETH_MACMIIAR_MB; - stm32_putreg(regval, STM32_ETH_MACMIIAR); - - /* Configure the MACMIIAR register, - * preserving CSR Clock Range CR[2:0] bits - */ - - regval &= ETH_MACMIIAR_CR_MASK; - - /* Set the PHY device address, PHY register address, and set the busy bit. - * the ETH_MACMIIAR_MW is set, indicating a write operation. - */ - - regval |= (phydevaddr << ETH_MACMIIAR_PA_SHIFT) & ETH_MACMIIAR_PA_MASK; - regval |= (phyregaddr << ETH_MACMIIAR_MR_SHIFT) & ETH_MACMIIAR_MR_MASK; - regval |= (ETH_MACMIIAR_MB | ETH_MACMIIAR_MW); - - /* Write the value into the MACIIDR register before setting the new - * MACMIIAR register value. - */ - - stm32_putreg(value, STM32_ETH_MACMIIDR); - stm32_putreg(regval, STM32_ETH_MACMIIAR); - - /* Wait for the transfer to complete */ - - for (timeout = 0; timeout < PHY_WRITE_TIMEOUT; timeout++) - { - if ((stm32_getreg(STM32_ETH_MACMIIAR) & ETH_MACMIIAR_MB) == 0) - { - return OK; - } - } - - nerr("ERROR: MII transfer timed out: " - "phydevaddr: %04x phyregaddr: %04x value: %04x\n", - phydevaddr, phyregaddr, value); - - return -ETIMEDOUT; -} - -/**************************************************************************** - * Function: stm32_dm9161 - * - * Description: - * Special workaround for the Davicom DM9161 PHY is required. On power, - * up, the PHY is not usually configured correctly but will work after - * a powered-up reset. This is really a workaround for some more - * fundamental issue with the PHY clocking initialization, but the - * root cause has not been studied (nor will it be with this workaround). - * - * Input Parameters: - * priv - A reference to the private driver state structure - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef CONFIG_ETH0_PHY_DM9161 -static inline int stm32_dm9161(struct stm32_ethmac_s *priv) -{ - uint16_t phyval; - int ret; - - /* Read the PHYID1 register; A failure to read the PHY ID is one - * indication that check if the DM9161 PHY CHIP is not ready. - */ - - ret = stm32_phyread(CONFIG_STM32_PHYADDR, MII_PHYID1, &phyval); - if (ret < 0) - { - nerr("ERROR: Failed to read the PHY ID1: %d\n", ret); - return ret; - } - - /* If we failed to read the PHY ID1 register, - * then reset the MCU to recover - */ - - else if (phyval == 0xffff) - { - up_systemreset(); - } - - ninfo("PHY ID1: 0x%04X\n", phyval); - - /* Now check the "DAVICOM Specified Configuration Register (DSCR)"(16) */ - - ret = stm32_phyread(CONFIG_STM32_PHYADDR, 16, &phyval); - if (ret < 0) - { - nerr("ERROR: Failed to read the PHY Register 0x10: %d\n", ret); - return ret; - } - - /* Bit 8 of the DSCR register is zero, then the DM9161 has not selected - * RMII. If RMII is not selected, then reset the MCU to recover. - */ - - else if ((phyval & (1 << 8)) == 0) - { - up_systemreset(); - } - - return OK; -} -#endif - -/**************************************************************************** - * Function: stm32_phyinit - * - * Description: - * Configure the PHY and determine the link speed/duplex. - * - * Input Parameters: - * priv - A reference to the private driver state structure - * - * Returned Value: - * OK on success; Negated errno on failure. - * - * Assumptions: - * - ****************************************************************************/ - -static int stm32_phyinit(struct stm32_ethmac_s *priv) -{ -#ifdef CONFIG_STM32_AUTONEG - volatile uint32_t timeout; -#endif - - uint32_t regval; - uint16_t phyval; - int ret; - - /* Assume 10MBps and half duplex */ - - priv->mbps100 = 0; - priv->fduplex = 0; - - /* Setup up PHY clocking by setting the SR field in the MACMIIAR register */ - - regval = stm32_getreg(STM32_ETH_MACMIIAR); - regval &= ~ETH_MACMIIAR_CR_MASK; - regval |= ETH_MACMIIAR_CR; - stm32_putreg(regval, STM32_ETH_MACMIIAR); - - /* Put the PHY in reset mode */ - - ret = stm32_phywrite(CONFIG_STM32_PHYADDR, MII_MCR, MII_MCR_RESET); - if (ret < 0) - { - nerr("ERROR: Failed to reset the PHY: %d\n", ret); - return ret; - } - - up_mdelay(PHY_RESET_DELAY); - - /* Perform any necessary, board-specific PHY initialization */ - -#ifdef CONFIG_STM32_PHYINIT - ret = stm32_phy_boardinitialize(0); - if (ret < 0) - { - nerr("ERROR: Failed to initialize the PHY: %d\n", ret); - return ret; - } -#endif - - /* Special workaround for the Davicom DM9161 PHY is required. */ - -#ifdef CONFIG_ETH0_PHY_DM9161 - ret = stm32_dm9161(priv); - if (ret < 0) - { - return ret; - } -#endif - - /* Perform auto-negotiation if so configured */ - -#ifdef CONFIG_STM32_AUTONEG - /* Wait for link status */ - - for (timeout = 0; timeout < PHY_RETRY_TIMEOUT; timeout++) - { - ret = stm32_phyread(CONFIG_STM32_PHYADDR, MII_MSR, &phyval); - if (ret < 0) - { - nerr("ERROR: Failed to read the PHY MSR: %d\n", ret); - return ret; - } - else if ((phyval & MII_MSR_LINKSTATUS) != 0) - { - break; - } - } - - if (timeout >= PHY_RETRY_TIMEOUT) - { - nerr("ERROR: Timed out waiting for link status: %04x\n", phyval); - return -ETIMEDOUT; - } - - /* Enable auto-gegotiation */ - - ret = stm32_phywrite(CONFIG_STM32_PHYADDR, MII_MCR, MII_MCR_ANENABLE); - if (ret < 0) - { - nerr("ERROR: Failed to enable auto-negotiation: %d\n", ret); - return ret; - } - - /* Wait until auto-negotiation completes */ - - for (timeout = 0; timeout < PHY_RETRY_TIMEOUT; timeout++) - { - ret = stm32_phyread(CONFIG_STM32_PHYADDR, MII_MSR, &phyval); - if (ret < 0) - { - nerr("ERROR: Failed to read the PHY MSR: %d\n", ret); - return ret; - } - else if ((phyval & MII_MSR_ANEGCOMPLETE) != 0) - { - break; - } - } - - if (timeout >= PHY_RETRY_TIMEOUT) - { - nerr("ERROR: Timed out waiting for auto-negotiation\n"); - return -ETIMEDOUT; - } - - /* Read the result of the auto-negotiation from the PHY-specific register */ - - ret = stm32_phyread(CONFIG_STM32_PHYADDR, CONFIG_STM32_PHYSR, &phyval); - if (ret < 0) - { - nerr("ERROR: Failed to read PHY status register\n"); - return ret; - } - - /* Remember the selected speed and duplex modes */ - - ninfo("PHYSR[%d]: %04x\n", CONFIG_STM32_PHYSR, phyval); - - /* Different PHYs present speed and mode information in different ways. - * IF This CONFIG_STM32_PHYSR_ALTCONFIG is selected, this indicates that - * the PHY represents speed and mode information are combined, for example, - * with separate bits for 10HD, 100HD, 10FD and 100FD. - */ - -#ifdef CONFIG_STM32_PHYSR_ALTCONFIG - switch (phyval & CONFIG_STM32_PHYSR_ALTMODE) - { - default: - case CONFIG_STM32_PHYSR_10HD: - priv->fduplex = 0; - priv->mbps100 = 0; - break; - - case CONFIG_STM32_PHYSR_100HD: - priv->fduplex = 0; - priv->mbps100 = 1; - break; - - case CONFIG_STM32_PHYSR_10FD: - priv->fduplex = 1; - priv->mbps100 = 0; - break; - - case CONFIG_STM32_PHYSR_100FD: - priv->fduplex = 1; - priv->mbps100 = 1; - break; - } - - /* Different PHYs present speed and mode information in different ways. - * Some will present separate information for speed and mode (this is the - * default). Those PHYs, for example, may provide a 10/100 Mbps indication - * and a separate full/half duplex indication. - */ - -#else - if ((phyval & CONFIG_STM32_PHYSR_MODE) == CONFIG_STM32_PHYSR_FULLDUPLEX) - { - priv->fduplex = 1; - } - - if ((phyval & CONFIG_STM32_PHYSR_SPEED) == CONFIG_STM32_PHYSR_100MBPS) - { - priv->mbps100 = 1; - } -#endif - -#else /* Auto-negotiation not selected */ - - phyval = 0; -#ifdef CONFIG_STM32_ETHFD - phyval |= MII_MCR_FULLDPLX; -#endif -#ifdef CONFIG_STM32_ETH100MBPS - phyval |= MII_MCR_SPEED100; -#endif - - ret = stm32_phywrite(CONFIG_STM32_PHYADDR, MII_MCR, phyval); - if (ret < 0) - { - nerr("ERROR: Failed to write the PHY MCR: %d\n", ret); - return ret; - } - - up_mdelay(PHY_CONFIG_DELAY); - - /* Remember the selected speed and duplex modes */ - -#ifdef CONFIG_STM32_ETHFD - priv->fduplex = 1; -#endif -#ifdef CONFIG_STM32_ETH100MBPS - priv->mbps100 = 1; -#endif -#endif - - ninfo("Duplex: %s Speed: %d MBps\n", - priv->fduplex ? "FULL" : "HALF", - priv->mbps100 ? 100 : 10); - - return OK; -} - -/**************************************************************************** - * Name: stm32_selectmii - * - * Description: - * Selects the MII interface. - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_MII -static inline void stm32_selectmii(void) -{ - uint32_t regval; - -#ifdef CONFIG_STM32_CONNECTIVITYLINE - regval = getreg32(STM32_AFIO_MAPR); - regval &= ~AFIO_MAPR_MII_RMII_SEL; - putreg32(regval, STM32_AFIO_MAPR); -#else - regval = getreg32(STM32_SYSCFG_PMC); - regval &= ~SYSCFG_PMC_MII_RMII_SEL; - putreg32(regval, STM32_SYSCFG_PMC); -#endif -} -#endif - -/**************************************************************************** - * Name: stm32_selectrmii - * - * Description: - * Selects the RMII interface. - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_RMII -static inline void stm32_selectrmii(void) -{ - uint32_t regval; - -#ifdef CONFIG_STM32_CONNECTIVITYLINE - regval = getreg32(STM32_AFIO_MAPR); - regval |= AFIO_MAPR_MII_RMII_SEL; - putreg32(regval, STM32_AFIO_MAPR); -#else - regval = getreg32(STM32_SYSCFG_PMC); - regval |= SYSCFG_PMC_MII_RMII_SEL; - putreg32(regval, STM32_SYSCFG_PMC); -#endif -} -#endif - -/**************************************************************************** - * Function: stm32_ethgpioconfig - * - * Description: - * Configure GPIOs for the Ethernet interface. - * - * Input Parameters: - * priv - A reference to the private driver state structure - * - * Returned Value: - * None. - * - * Assumptions: - * - ****************************************************************************/ - -static inline void stm32_ethgpioconfig(struct stm32_ethmac_s *priv) -{ - /* Configure GPIO pins to support Ethernet */ - -#if defined(CONFIG_STM32_MII) || defined(CONFIG_STM32_RMII) - - /* MDC and MDIO are common to both modes */ - - stm32_configgpio(GPIO_ETH_MDC); - stm32_configgpio(GPIO_ETH_MDIO); - - /* Set up the MII interface */ - -# if defined(CONFIG_STM32_MII) - - /* Select the MII interface */ - - stm32_selectmii(); - - /* Provide clocking via MCO, MCO1 or MCO2: - * - * "MCO1 (microcontroller clock output), used to output HSI, LSE, HSE or - * PLL clock (through a configurable prescaler) on PA8 pin." - * - * "MCO2 (microcontroller clock output), used to output HSE, PLL, SYSCLK or - * PLLI2S clock (through a configurable prescaler) on PC9 pin." - */ - -# if defined(CONFIG_STM32_MII_MCO1) - /* Configure MC01 to drive the PHY. Board logic must provide MC01 clocking - * info. - */ - - stm32_configgpio(GPIO_MCO1); - stm32_mco1config(BOARD_CFGR_MC01_SOURCE, BOARD_CFGR_MC01_DIVIDER); - -# elif defined(CONFIG_STM32_MII_MCO2) - /* Configure MC02 to drive the PHY. Board logic must provide MC02 clocking - * info. - */ - - stm32_configgpio(GPIO_MCO2); - stm32_mco2config(BOARD_CFGR_MC02_SOURCE, BOARD_CFGR_MC02_DIVIDER); - -# elif defined(CONFIG_STM32_MII_MCO) - /* Setup MCO pin for alternative usage */ - - stm32_configgpio(GPIO_MCO); - stm32_mcoconfig(BOARD_CFGR_MCO_SOURCE); -# endif - - /* MII interface pins (17): - * - * MII_TX_CLK, MII_TXD[3:0], MII_TX_EN, MII_RX_CLK, MII_RXD[3:0], - * MII_RX_ER, MII_RX_DV, MII_CRS, MII_COL, MDC, MDIO - */ - - stm32_configgpio(GPIO_ETH_MII_COL); - stm32_configgpio(GPIO_ETH_MII_CRS); - stm32_configgpio(GPIO_ETH_MII_RXD0); - stm32_configgpio(GPIO_ETH_MII_RXD1); - stm32_configgpio(GPIO_ETH_MII_RXD2); - stm32_configgpio(GPIO_ETH_MII_RXD3); - stm32_configgpio(GPIO_ETH_MII_RX_CLK); - stm32_configgpio(GPIO_ETH_MII_RX_DV); - stm32_configgpio(GPIO_ETH_MII_RX_ER); - stm32_configgpio(GPIO_ETH_MII_TXD0); - stm32_configgpio(GPIO_ETH_MII_TXD1); - stm32_configgpio(GPIO_ETH_MII_TXD2); - stm32_configgpio(GPIO_ETH_MII_TXD3); - stm32_configgpio(GPIO_ETH_MII_TX_CLK); - stm32_configgpio(GPIO_ETH_MII_TX_EN); - - /* Set up the RMII interface. */ - -# elif defined(CONFIG_STM32_RMII) - - /* Select the RMII interface */ - - stm32_selectrmii(); - - /* Provide clocking via MCO, MCO1 or MCO2: - * - * "MCO1 (microcontroller clock output), used to output HSI, LSE, HSE or - * PLL clock (through a configurable prescaler) on PA8 pin." - * - * "MCO2 (microcontroller clock output), used to output HSE, PLL, SYSCLK or - * PLLI2S clock (through a configurable prescaler) on PC9 pin." - */ - -# if defined(CONFIG_STM32_RMII_MCO1) - /* Configure MC01 to drive the PHY. Board logic must provide MC01 clocking - * info. - */ - - stm32_configgpio(GPIO_MCO1); - stm32_mco1config(BOARD_CFGR_MC01_SOURCE, BOARD_CFGR_MC01_DIVIDER); - -# elif defined(CONFIG_STM32_RMII_MCO2) - /* Configure MC02 to drive the PHY. Board logic must provide MC02 clocking - * info. - */ - - stm32_configgpio(GPIO_MCO2); - stm32_mco2config(BOARD_CFGR_MC02_SOURCE, BOARD_CFGR_MC02_DIVIDER); - -# elif defined(CONFIG_STM32_RMII_MCO) - /* Setup MCO pin for alternative usage */ - - stm32_configgpio(GPIO_MCO); - stm32_mcoconfig(BOARD_CFGR_MCO_SOURCE); -# endif - - /* RMII interface pins (7): - * - * RMII_TXD[1:0], RMII_TX_EN, RMII_RXD[1:0], RMII_CRS_DV, MDC, MDIO, - * RMII_REF_CLK - */ - - stm32_configgpio(GPIO_ETH_RMII_CRS_DV); - stm32_configgpio(GPIO_ETH_RMII_REF_CLK); - stm32_configgpio(GPIO_ETH_RMII_RXD0); - stm32_configgpio(GPIO_ETH_RMII_RXD1); - stm32_configgpio(GPIO_ETH_RMII_TXD0); - stm32_configgpio(GPIO_ETH_RMII_TXD1); - stm32_configgpio(GPIO_ETH_RMII_TX_EN); - -# endif -#endif - -#ifdef CONFIG_STM32_ETH_PTP_GPIO - /* Enable pulse-per-second (PPS) output signal */ - - stm32_configgpio(GPIO_ETH_PPS_OUT); -#endif -} - -#ifdef CONFIG_STM32_ETH_PTP - -/**************************************************************************** - * Function: stm32_eth_ptp_adjust - * - * Description: - * Adjust PTP timer run rate. - * - * Input Parameters: - * ppb - Adjustment in parts per billion (nanoseconds per second). - * Zero is default rate, positive value makes clock run faster - * and negative value slower. - * - * Returned Value: - * OK on success, negated errno on failure. - * - * Assumptions: - * Adjustment is between -0.5e9 and +0.5e9 (+- 50%) - * - ****************************************************************************/ - -static int stm32_eth_ptp_adjust(long ppb) -{ - uint32_t regval; - uint64_t addend; - uint32_t increment; - - /* Compute addend value to achieve nominal timer rate. - * Increment is set by stm32_eth_ptp_init() and remains constants after - * that. - */ - - increment = stm32_getreg(STM32_ETH_PTPSSIR) & ETH_PTPSSIR_MASK; - addend = ((uint64_t)1 << (32 + 31)) / (STM32_SYSCLK_FREQUENCY * increment); - - /* Apply rate adjustment, if any */ - - if (ppb != 0) - { - addend += addend * ppb / NSEC_PER_SEC; - } - - /* Check for overflows */ - - if (addend == 0 || (uint32_t)addend != addend) - { - nerr("PTP adjustment out of range: ppb=%ld, addend=%lld\n", - ppb, addend); - return -EINVAL; - } - - /* Perform addend register update */ - - stm32_putreg((uint32_t)addend, STM32_ETH_PTPTSAR); - regval = stm32_getreg(STM32_ETH_PTPTSCR); - stm32_putreg(regval | ETH_PTPTSCR_TSARU, STM32_ETH_PTPTSCR); - up_udelay(1); - if (stm32_getreg(STM32_ETH_PTPTSCR) & ETH_PTPTSCR_TSARU) - { - /* This can happen if Ethernet PHY clock is stopped */ - - nerr("PTP addend update failed\n"); - return -EBUSY; - } - - return OK; -} - -/**************************************************************************** - * Function: stm32_eth_ptp_init - * - * Description: - * Configure the PTP timestamp counter of the Ethernet peripheral. - * - * Input Parameters: - * timestamp: Initial timestamp - * - * Returned Value: - * None - * - * Assumptions: - * - ****************************************************************************/ - -static void stm32_eth_ptp_init(uint64_t timestamp) -{ - uint32_t regval; - uint32_t increment; - - /* The PPS timestamp counter consists of a 32-bit seconds counter and - * 31-bit subsecond counter. The PTP input clock (SYSCLK) is divided by - * 2^32 / ADDEND and multiplied by INCREMENT. This calculation aims for - * ADDEND of 2^31 to provide +- 50% rate adjustment range. - * - * ADDEND value is then adjusted to compensate for rounding errors in - * the 8-bit INCREMENT value. The final rounding error will be less than - * 1 ppb. The timer frequency is approximately half of SYSCLK frequency, - * with phase jitter of one SYSCLK period. - */ - - increment = ((uint32_t)1 << 31) / (STM32_SYSCLK_FREQUENCY / 2); - DEBUGASSERT(increment > 0 && (increment & ETH_PTPSSIR_MASK) == increment); - - /* Timestamp counter initialization process - * (STM32F407 reference manual section 33.5.9 - * "Programming steps for system time generation initialization") - */ - - regval = ETH_PTPTSCR_TSE; - stm32_putreg(regval, STM32_ETH_PTPTSCR); - stm32_putreg(increment, STM32_ETH_PTPSSIR); - - /* Update addend value to default rate */ - - stm32_eth_ptp_adjust(0); - - /* Enable fine update mode */ - - regval |= ETH_PTPTSCR_TSFCU; - stm32_putreg(regval, STM32_ETH_PTPTSCR); - - /* Initialize counter value */ - - stm32_putreg((uint32_t)(timestamp >> 32), STM32_ETH_PTPTSHUR); - stm32_putreg((uint32_t)(timestamp >> 1), STM32_ETH_PTPTSLUR); - stm32_putreg(regval | ETH_PTPTSCR_TSSTI, STM32_ETH_PTPTSCR); - up_udelay(1); - - /* Initialization should complete within a few clock cycles. - * If not, there is probably something wrong with the PHY clock domain. - */ - - if (stm32_getreg(STM32_ETH_PTPTSCR) & ETH_PTPTSCR_TSSTI) - { - nerr("PTP timestamp initialization failed\n"); - } - - /* Enable packet timestamping */ - -#ifdef CONFIG_STM32_ETH_TIMESTAMP_RX - regval |= ETH_PTPTSCR_TSSARFE; - stm32_putreg(regval, STM32_ETH_PTPTSCR); -#endif -} - -/**************************************************************************** - * Name: stm32_eth_ptp_gettime - * - * Description: - * Read PTP timestamp registers. The 64-bit timestamp consists of two - * registers that are updated continuously. This function employs - * double-read pattern to correctly handle overflow of the lower register. - * - * Input Parameters: - * None - * - * Returned Value: - * 64-bit timestamp, where upper 32 bits are the second count and lower - * 32-bits are the subsecond count. - * If timer is not yet initialized, returns 0. - * - * Assumptions: - * Can be called from interrupt or task context. - * - ****************************************************************************/ - -static uint64_t stm32_eth_ptp_gettime(void) -{ - uint32_t high1; - uint32_t low; - uint32_t high2; - - high1 = getreg32(STM32_ETH_PTPTSHR); - low = getreg32(STM32_ETH_PTPTSLR); - high2 = getreg32(STM32_ETH_PTPTSHR); - - if (high1 == high2) - { - return ((uint64_t)high2 << 32) | ((low & ETH_PTPTSLR_MASK) << 1); - } - else - { - /* Lower counter overflowed between the two register reads. - * Take its value as 0. - */ - - return ((uint64_t)high2 << 32); - } -} - -static inline void ptp_to_timespec(uint64_t timestamp, struct timespec *ts) -{ - ts->tv_sec = (timestamp >> 32); - ts->tv_nsec = ((uint32_t)timestamp * (uint64_t)NSEC_PER_SEC) >> 32; -} - -/* Convert RX timestamp to CLOCK_REALTIME */ -#ifdef CONFIG_STM32_ETH_TIMESTAMP_RX -static void stm32_eth_ptp_convert_rxtime(struct stm32_ethmac_s *priv) -{ - uint64_t timestamp; - struct timespec rxtime; - - timestamp = ((uint64_t)priv->rxtimehigh << 32) - | ((priv->rxtimelow & ETH_PTPTSLR_MASK) << 1); - - /* Timestamp of 0 indicates that Ethernet peripheral didn't store the - * timestamp. Timestamp of all ones indicates "corrupt timestamp" - * according to reference manual. In either case, we pass along - * a timestamp of all zeros to application. - */ - - if (timestamp == 0 || timestamp >= UINT64_MAX - 1) - { - nerr("Packet RX timestamp is invalid\n"); - priv->dev.d_rxtime.tv_sec = 0; - priv->dev.d_rxtime.tv_nsec = 0; - return; - } - -#ifdef CONFIG_STM32_ETH_PTP_RTC_HIRES - /* PTP is the system time reference, just add the base time */ - - ptp_to_timespec(timestamp, &rxtime); - clock_timespec_add(&rxtime, &g_stm32_eth_ptp_basetime, - &priv->dev.d_rxtime); - -#else - { - struct timespec realtime; - uint64_t ptptime; - irqstate_t flags; - - /* Sample PTP and CLOCK_REALTIME close to each other */ - - clock_gettime(CLOCK_REALTIME, &realtime); - flags = spin_lock_irqsave(&g_rtc_lock); - ptptime = stm32_eth_ptp_gettime(); - spin_unlock_irqrestore(&g_rtc_lock, flags); - - /* Compute how much time has elapsed since packet reception - * and add that to current time. - */ - - timestamp = ptptime - timestamp; - ptp_to_timespec(timestamp, &rxtime); - clock_timespec_add(&rxtime, &realtime, &priv->dev.d_rxtime); - } -#endif /* CONFIG_STM32_ETH_PTP_RTC_HIRES */ -} -#endif /* CONFIG_STM32_ETH_TIMESTAMP_RX */ - -#endif /* CONFIG_STM32_ETH_PTP */ - -/**************************************************************************** - * Function: stm32_ethreset - * - * Description: - * Reset the Ethernet block. - * - * Input Parameters: - * priv - A reference to the private driver state structure - * - * Returned Value: - * Zero on success, or a negated errno value on any failure. - * - * Assumptions: - * - ****************************************************************************/ - -static int stm32_ethreset(struct stm32_ethmac_s *priv) -{ - uint32_t regval; - uint32_t retries; - - /* Reset the Ethernet on the AHB bus (F1 Connectivity Line) or AHB1 bus (F2 - * and F4) - */ - -#if defined(CONFIG_STM32_CONNECTIVITYLINE) - regval = stm32_getreg(STM32_RCC_AHBRSTR); - regval |= RCC_AHBRSTR_ETHMACRST; - stm32_putreg(regval, STM32_RCC_AHBRSTR); - - regval &= ~RCC_AHBRSTR_ETHMACRST; - stm32_putreg(regval, STM32_RCC_AHBRSTR); -#else - regval = stm32_getreg(STM32_RCC_AHB1RSTR); - regval |= RCC_AHB1RSTR_ETHMACRST; - stm32_putreg(regval, STM32_RCC_AHB1RSTR); - - regval &= ~RCC_AHB1RSTR_ETHMACRST; - stm32_putreg(regval, STM32_RCC_AHB1RSTR); -#endif - - /* Perform a software reset by setting the SR bit in the DMABMR register. - * This Resets all MAC subsystem internal registers and logic. After this - * reset all the registers holds their reset values. - */ - - regval = stm32_getreg(STM32_ETH_DMABMR); - regval |= ETH_DMABMR_SR; - stm32_putreg(regval, STM32_ETH_DMABMR); - - /* Wait for software reset to complete. The SR bit is cleared automatically - * after the reset operation has completed in all core clock domains. - * Should take at most a few clock ticks of the 50 MHz domain. - */ - - retries = 10; - while (((stm32_getreg(STM32_ETH_DMABMR) & ETH_DMABMR_SR) != 0) && - retries > 0) - { - retries--; - up_udelay(1); - } - - if (retries == 0) - { - return -ETIMEDOUT; - } - - return 0; -} - -/**************************************************************************** - * Function: stm32_macconfig - * - * Description: - * Configure the Ethernet MAC for DMA operation. - * - * Input Parameters: - * priv - A reference to the private driver state structure - * - * Returned Value: - * OK on success; Negated errno on failure. - * - * Assumptions: - * - ****************************************************************************/ - -static int stm32_macconfig(struct stm32_ethmac_s *priv) -{ - uint32_t regval; - - /* Set up the MACCR register */ - - regval = stm32_getreg(STM32_ETH_MACCR); - regval &= ~MACCR_CLEAR_BITS; - regval |= MACCR_SET_BITS; - - if (priv->fduplex) - { - /* Set the DM bit for full duplex support */ - - regval |= ETH_MACCR_DM; - } - - if (priv->mbps100) - { - /* Set the FES bit for 100Mbps fast ethernet support */ - - regval |= ETH_MACCR_FES; - } - - stm32_putreg(regval, STM32_ETH_MACCR); - - /* Set up the MACFFR register */ - - regval = stm32_getreg(STM32_ETH_MACFFR); - regval &= ~MACFFR_CLEAR_BITS; - regval |= MACFFR_SET_BITS; - stm32_putreg(regval, STM32_ETH_MACFFR); - - /* Set up the MACHTHR and MACHTLR registers */ - - stm32_putreg(0, STM32_ETH_MACHTHR); - stm32_putreg(0, STM32_ETH_MACHTLR); - - /* Setup up the MACFCR register */ - - regval = stm32_getreg(STM32_ETH_MACFCR); - regval &= ~MACFCR_CLEAR_MASK; - regval |= MACFCR_SET_MASK; - stm32_putreg(regval, STM32_ETH_MACFCR); - - /* Setup up the MACVLANTR register */ - - stm32_putreg(0, STM32_ETH_MACVLANTR); - - /* DMA Configuration */ - - /* Set up the DMAOMR register */ - - regval = stm32_getreg(STM32_ETH_DMAOMR); - regval &= ~DMAOMR_CLEAR_MASK; - regval |= DMAOMR_SET_MASK; - stm32_putreg(regval, STM32_ETH_DMAOMR); - - /* Set up the DMABMR register */ - - regval = stm32_getreg(STM32_ETH_DMABMR); - regval &= ~DMABMR_CLEAR_MASK; - regval |= DMABMR_SET_MASK; - stm32_putreg(regval, STM32_ETH_DMABMR); - - return OK; -} - -/**************************************************************************** - * Function: stm32_macaddress - * - * Description: - * Configure the selected MAC address. - * - * Input Parameters: - * priv - A reference to the private driver state structure - * - * Returned Value: - * OK on success; Negated errno on failure. - * - * Assumptions: - * - ****************************************************************************/ - -static void stm32_macaddress(struct stm32_ethmac_s *priv) -{ - struct net_driver_s *dev = &priv->dev; - uint32_t regval; - - ninfo("%s MAC: %02x:%02x:%02x:%02x:%02x:%02x\n", - dev->d_ifname, - dev->d_mac.ether.ether_addr_octet[0], - dev->d_mac.ether.ether_addr_octet[1], - dev->d_mac.ether.ether_addr_octet[2], - dev->d_mac.ether.ether_addr_octet[3], - dev->d_mac.ether.ether_addr_octet[4], - dev->d_mac.ether.ether_addr_octet[5]); - - /* Set the MAC address high register */ - - regval = ((uint32_t)dev->d_mac.ether.ether_addr_octet[5] << 8) | - (uint32_t)dev->d_mac.ether.ether_addr_octet[4]; - stm32_putreg(regval, STM32_ETH_MACA0HR); - - /* Set the MAC address low register */ - - regval = ((uint32_t)dev->d_mac.ether.ether_addr_octet[3] << 24) | - ((uint32_t)dev->d_mac.ether.ether_addr_octet[2] << 16) | - ((uint32_t)dev->d_mac.ether.ether_addr_octet[1] << 8) | - (uint32_t)dev->d_mac.ether.ether_addr_octet[0]; - stm32_putreg(regval, STM32_ETH_MACA0LR); -} - -/**************************************************************************** - * Function: stm32_macenable - * - * Description: - * Enable normal MAC operation. - * - * Input Parameters: - * priv - A reference to the private driver state structure - * - * Returned Value: - * OK on success; Negated errno on failure. - * - * Assumptions: - * - ****************************************************************************/ - -static int stm32_macenable(struct stm32_ethmac_s *priv) -{ - uint32_t regval; - - /* Set the MAC address */ - - stm32_macaddress(priv); - - /* Enable transmit state machine of the MAC for transmission on the MII */ - - regval = stm32_getreg(STM32_ETH_MACCR); - regval |= ETH_MACCR_TE; - stm32_putreg(regval, STM32_ETH_MACCR); - - /* Flush Transmit FIFO */ - - regval = stm32_getreg(STM32_ETH_DMAOMR); - regval |= ETH_DMAOMR_FTF; - stm32_putreg(regval, STM32_ETH_DMAOMR); - - /* Enable receive state machine of the MAC for reception from the MII */ - - /* Enables or disables the MAC reception. */ - - regval = stm32_getreg(STM32_ETH_MACCR); - regval |= ETH_MACCR_RE; - stm32_putreg(regval, STM32_ETH_MACCR); - - /* Start DMA transmission */ - - regval = stm32_getreg(STM32_ETH_DMAOMR); - regval |= ETH_DMAOMR_ST; - stm32_putreg(regval, STM32_ETH_DMAOMR); - - /* Start DMA reception */ - - regval = stm32_getreg(STM32_ETH_DMAOMR); - regval |= ETH_DMAOMR_SR; - stm32_putreg(regval, STM32_ETH_DMAOMR); - - /* Enable Ethernet DMA interrupts. - * - * The STM32 hardware supports two interrupts: (1) one dedicated to normal - * Ethernet operations and the other, used only for the Ethernet wakeup - * event. The wake-up interrupt is not used by this driver. - * - * The first Ethernet vector is reserved for interrupts generated by the - * MAC and the DMA. The MAC provides PMT and time stamp trigger interrupts, - * neither of which are used by this driver. - */ - - stm32_putreg(ETH_MACIMR_ALLINTS, STM32_ETH_MACIMR); - - /* Ethernet DMA supports two classes of interrupts: Normal interrupt - * summary (NIS) and Abnormal interrupt summary (AIS) with a variety - * individual normal and abnormal interrupting events. Here only - * the normal receive event is enabled (unless DEBUG is enabled). Transmit - * events will only be enabled when a transmit interrupt is expected. - */ - - stm32_putreg(ETH_DMAINT_RECV_ENABLE | ETH_DMAINT_ERROR_ENABLE, - STM32_ETH_DMAIER); - return OK; -} - -/**************************************************************************** - * Function: stm32_ethconfig - * - * Description: - * Configure the Ethernet interface for DMA operation. - * - * Input Parameters: - * priv - A reference to the private driver state structure - * - * Returned Value: - * OK on success; Negated errno on failure. - * - * Assumptions: - * - ****************************************************************************/ - -static int stm32_ethconfig(struct stm32_ethmac_s *priv) -{ - int ret; - - /* NOTE: The Ethernet clocks were initialized early in the boot-up - * sequence in stm32_rcc.c. - */ - - /* Reset the Ethernet block */ - - ninfo("Reset the Ethernet block\n"); - ret = stm32_ethreset(priv); - if (ret < 0) - { - nerr("ERROR: Reset of Ethernet block failed\n"); - return ret; - } - - /* Initialize the PHY */ - - ninfo("Initialize the PHY\n"); - ret = stm32_phyinit(priv); - if (ret < 0) - { - return ret; - } - - /* Initialize the MAC and DMA */ - - ninfo("Initialize the MAC and DMA\n"); - ret = stm32_macconfig(priv); - if (ret < 0) - { - return ret; - } - - /* Initialize the free buffer list */ - - stm32_initbuffer(priv, g_alloc); - - /* Initialize TX Descriptors list: Chain Mode */ - - stm32_txdescinit(priv, g_txtable); - - /* Initialize RX Descriptors list: Chain Mode */ - - stm32_rxdescinit(priv, g_rxtable, g_rxbuffer); - - /* Enable normal MAC operation */ - - ninfo("Enable normal operation\n"); - return stm32_macenable(priv); -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Function: stm32_ethinitialize - * - * Description: - * Initialize the Ethernet driver for one interface. If the STM32 chip - * supports multiple Ethernet controllers, then board specific logic - * must implement arm_netinitialize() and call this function to initialize - * the desired interfaces. - * - * Input Parameters: - * intf - In the case where there are multiple EMACs, this value - * identifies which EMAC is to be initialized. - * - * Returned Value: - * OK on success; Negated errno on failure. - * - * Assumptions: - * - ****************************************************************************/ - -#if STM32_NETHERNET == 1 || defined(CONFIG_NETDEV_LATEINIT) -static inline -#endif -int stm32_ethinitialize(int intf) -{ - struct stm32_ethmac_s *priv; - int ret; - - ninfo("intf: %d\n", intf); - - /* Get the interface structure associated with this interface number. */ - - DEBUGASSERT(intf < STM32_NETHERNET); - priv = &g_stm32ethmac[intf]; - - /* Initialize the driver structure */ - - memset(priv, 0, sizeof(struct stm32_ethmac_s)); - priv->dev.d_ifup = stm32_ifup; /* I/F up (new IP address) callback */ - priv->dev.d_ifdown = stm32_ifdown; /* I/F down callback */ - priv->dev.d_txavail = stm32_txavail; /* New TX data callback */ -#ifdef CONFIG_NET_MCASTGROUP - priv->dev.d_addmac = stm32_addmac; /* Add multicast MAC address */ - priv->dev.d_rmmac = stm32_rmmac; /* Remove multicast MAC address */ -#endif -#ifdef CONFIG_NETDEV_IOCTL - priv->dev.d_ioctl = stm32_ioctl; /* Support PHY ioctl() calls */ -#endif - priv->dev.d_private = g_stm32ethmac; /* Used to recover private state from dev */ - - /* Configure GPIO pins to support Ethernet */ - - stm32_ethgpioconfig(priv); - - /* Attach the IRQ to the driver */ - - if (irq_attach(STM32_IRQ_ETH, stm32_interrupt, NULL)) - { - /* We could not attach the ISR to the interrupt */ - - return -EAGAIN; - } - - /* Put the interface in the down state. */ - - ret = stm32_ifdown(&priv->dev); - if (ret < 0) - { - nerr("ERROR: Initialization of Ethernet block failed: %d\n", ret); - return ret; - } - - /* Register the device with the OS so that socket IOCTLs can be performed */ - - netdev_register(&priv->dev, NET_LL_ETHERNET); - return OK; -} - -/**************************************************************************** - * Function: arm_netinitialize - * - * Description: - * This is the "standard" network initialization logic called from the - * low-level initialization logic in arm_initialize.c. If STM32_NETHERNET - * greater than one, then board specific logic will have to supply a - * version of arm_netinitialize() that calls stm32_ethinitialize() with - * the appropriate interface number. - * - * Input Parameters: - * None. - * - * Returned Value: - * None. - * - * Assumptions: - * - ****************************************************************************/ - -#if STM32_NETHERNET == 1 && !defined(CONFIG_NETDEV_LATEINIT) -void arm_netinitialize(void) -{ - stm32_ethinitialize(0); -} -#endif - -#ifdef CONFIG_STM32_ETH_PTP_RTC_HIRES - -/**************************************************************************** - * Name: up_rtc_initialize - * - * Description: - * Initialize the builtin, MCU hardware RTC per the selected - * configuration. This function is called once very early in the OS - * initialization sequence. - * - * NOTE that initialization of external RTC hardware that depends on the - * availability of OS resources (such as SPI or I2C) must be deferred - * until the system has fully booted. Other, RTC-specific initialization - * functions are used in that case. - * - * Input Parameters: - * None - * - * Returned Value: - * Zero (OK) on success; a negated errno on failure - * - ****************************************************************************/ - -int up_rtc_initialize(void) -{ - /* Nothing to do, the PTP RTC is not available until Ethernet peripheral - * is enabled. - */ - - return OK; -} - -/**************************************************************************** - * Name: up_rtc_gettime - * - * Description: - * Get the current time from the high resolution RTC clock/counter. This - * interface is only supported by the high-resolution RTC/counter hardware - * implementation. - * It is used to replace the system timer. - * - * Input Parameters: - * tp - The location to return the high resolution time value. - * - * Returned Value: - * Zero (OK) on success; a negated errno value on failure. - * - ****************************************************************************/ - -int up_rtc_gettime(struct timespec *tp) -{ - irqstate_t flags; - uint64_t timestamp; - - flags = spin_lock_irqsave(&g_rtc_lock); - timestamp = stm32_eth_ptp_gettime(); - - if (timestamp == 0) - { - /* PTP timer is not initialized yet. - * Normally we shouldn't end up here because g_rtc_enabled is false. - */ - - spin_unlock_irqrestore(&g_rtc_lock, flags); - DEBUGASSERT(!g_rtc_enabled); - return -EBUSY; - } - - ptp_to_timespec(timestamp, tp); - clock_timespec_add(tp, &g_stm32_eth_ptp_basetime, tp); - spin_unlock_irqrestore(&g_rtc_lock, flags); - - return OK; -} - -/**************************************************************************** - * Name: up_rtc_settime - * - * Description: - * Set the RTC to the provided time. All RTC implementations must be able - * to set their time based on a standard timespec. - * - * Input Parameters: - * tp - the time to use - * - * Returned Value: - * Zero (OK) on success; a negated errno value on failure. - * - ****************************************************************************/ - -int up_rtc_settime(const struct timespec *tp) -{ - struct timespec ptptime; - uint64_t timestamp; - irqstate_t flags; - - flags = spin_lock_irqsave(&g_rtc_lock); - timestamp = stm32_eth_ptp_gettime(); - - if (timestamp == 0) - { - /* PTP timer is not initialized yet. - * Normally we shouldn't end up here because g_rtc_enabled is false. - */ - - spin_unlock_irqrestore(&g_rtc_lock, flags); - DEBUGASSERT(!g_rtc_enabled); - return -EBUSY; - } - - /* Compute new basetime to get from PTP timestamp to wall clock time. - * We keep the PTP timer 0-based to avoid 32-bit seconds count - * overflow issues. - */ - - ptp_to_timespec(timestamp, &ptptime); - clock_timespec_subtract(tp, &ptptime, &g_stm32_eth_ptp_basetime); - spin_unlock_irqrestore(&g_rtc_lock, flags); - - return OK; -} - -/**************************************************************************** - * Name: up_rtc_adjtime - * - * Description: - * Adjust RTC frequency (running rate). Used by adjtime() when RTC is used - * as system time source. - * - * Input Parameters: - * ppb - Adjustment in parts per billion (nanoseconds per second). - * Zero is default rate, positive value makes clock run faster - * and negative value slower. - * - * Returned Value: - * Zero (OK) on success; a negated errno value on failure. - * - * Assumptions: - * Called from within a critical section. - * - ****************************************************************************/ - -int up_rtc_adjtime(long ppb) -{ - return stm32_eth_ptp_adjust(ppb); -} - -#endif /* CONFIG_STM32_ETH_PTP_RTC_HIRES */ - -#endif /* STM32_NETHERNET > 0 */ -#endif /* CONFIG_NET && CONFIG_STM32_ETHMAC */ diff --git a/arch/arm/src/stm32/stm32_eth.h b/arch/arm/src/stm32/stm32_eth.h deleted file mode 100644 index 68515b800068b..0000000000000 --- a/arch/arm/src/stm32/stm32_eth.h +++ /dev/null @@ -1,109 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_eth.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32_STM32_ETH_H -#define __ARCH_ARM_SRC_STM32_STM32_ETH_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "chip.h" - -#if STM32_NETHERNET > 0 - -#include "hardware/stm32_eth.h" - -#ifndef __ASSEMBLY__ - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Function: stm32_ethinitialize - * - * Description: - * Initialize the Ethernet driver for one interface. If the STM32 chip - * supports multiple Ethernet controllers, then board specific logic must - * implement arm_netinitialize() and call this function to initialize the - * desired interfaces. - * - * Input Parameters: - * intf - In the case where there are multiple EMACs, this value - * identifies which EMAC is to be initialized. - * - * Returned Value: - * OK on success; Negated errno on failure. - * - * Assumptions: - * - ****************************************************************************/ - -#if STM32_NETHERNET > 1 || defined(CONFIG_NETDEV_LATEINIT) -int stm32_ethinitialize(int intf); -#endif - -/**************************************************************************** - * Function: stm32_phy_boardinitialize - * - * Description: - * Some boards require specialized initialization of the PHY before it can - * be used. This may include such things as configuring GPIOs, resetting - * the PHY, etc. If CONFIG_STM32_PHYINIT is defined in the configuration - * then the board specific logic must provide stm32_phyinitialize(); The - * STM32 Ethernet driver will call this function one time before it first - * uses the PHY. - * - * Input Parameters: - * intf - Always zero for now. - * - * Returned Value: - * OK on success; Negated errno on failure. - * - * Assumptions: - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_PHYINIT -int stm32_phy_boardinitialize(int intf); -#endif - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ -#endif /* STM32_NETHERNET > 0 */ -#endif /* __ARCH_ARM_SRC_STM32_STM32_ETH_H */ diff --git a/arch/arm/src/stm32/stm32_exti.h b/arch/arm/src/stm32/stm32_exti.h deleted file mode 100644 index ae9ac9dba4ccf..0000000000000 --- a/arch/arm/src/stm32/stm32_exti.h +++ /dev/null @@ -1,130 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_exti.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32_STM32_EXTI_H -#define __ARCH_ARM_SRC_STM32_STM32_EXTI_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include "chip.h" -#include "hardware/stm32_exti.h" - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -#ifndef __ASSEMBLY__ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_gpiosetevent - * - * Description: - * Sets/clears GPIO based event and interrupt triggers. - * - * Input Parameters: - * - pinset: gpio pin configuration - * - rising/falling edge: enables - * - event: generate event when set - * - func: when non-NULL, generate interrupt - * - arg: Argument passed to the interrupt callback - * - * Returned Value: - * Zero (OK) on success; a negated errno value on failure indicating the - * nature of the failure. - * - ****************************************************************************/ - -int stm32_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, - bool event, xcpt_t func, void *arg); - -/**************************************************************************** - * Name: stm32_exti_alarm - * - * Description: - * Sets/clears EXTI alarm interrupt. - * - * Input Parameters: - * - rising/falling edge: enables interrupt on rising/falling edges - * - event: generate event when set - * - func: when non-NULL, generate interrupt - * - arg: Argument passed to the interrupt callback - * - * Returned Value: - * Zero (OK) on success; a negated errno value on failure indicating the - * nature of the failure. - * - ****************************************************************************/ - -#ifdef CONFIG_RTC_ALARM -int stm32_exti_alarm(bool risingedge, bool fallingedge, bool event, - xcpt_t func, void *arg); -#endif - -/**************************************************************************** - * Name: stm32_exti_wakeup - * - * Description: - * Sets/clears EXTI wakeup interrupt. - * - * Input Parameters: - * - rising/falling edge: enables interrupt on rising/falling edges - * - event: generate event when set - * - func: when non-NULL, generate interrupt - * - arg: Argument passed to the interrupt callback - * - * Returned Value: - * Zero (OK) on success; a negated errno value on failure indicating the - * nature of the failure. - * - ****************************************************************************/ - -#ifdef CONFIG_RTC_PERIODIC -int stm32_exti_wakeup(bool risingedge, bool fallingedge, bool event, - xcpt_t func, void *arg); -#endif - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32_STM32_EXTI_H */ diff --git a/arch/arm/src/stm32/stm32_exti_alarm.c b/arch/arm/src/stm32/stm32_exti_alarm.c deleted file mode 100644 index e908fbae17fc8..0000000000000 --- a/arch/arm/src/stm32/stm32_exti_alarm.c +++ /dev/null @@ -1,140 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_exti_alarm.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include -#include - -#include -#include -#include - -#include - -#include "arm_internal.h" -#include "chip.h" -#include "stm32_gpio.h" -#include "stm32_exti.h" - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* Interrupt handlers attached to the ALARM EXTI */ - -static xcpt_t g_alarm_callback; -static void *g_callback_arg; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_exti_alarm_isr - * - * Description: - * EXTI ALARM interrupt service routine/dispatcher - * - ****************************************************************************/ - -static int stm32_exti_alarm_isr(int irq, void *context, void *arg) -{ - int ret = OK; - - /* Clear the pending EXTI interrupt */ - - putreg32(EXTI_RTC_ALARM, STM32_EXTI_PR); - - /* And dispatch the interrupt to the handler */ - - if (g_alarm_callback) - { - ret = g_alarm_callback(irq, context, g_callback_arg); - } - - return ret; -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_exti_alarm - * - * Description: - * Sets/clears EXTI alarm interrupt. - * - * Input Parameters: - * - rising/falling edge: enables interrupt on rising/falling edge - * - event: generate event when set - * - func: when non-NULL, generate interrupt - * - arg: Argument passed to the interrupt callback - * - * Returned Value: - * Zero (OK) on success; a negated errno value on failure indicating the - * nature of the failure. - * - ****************************************************************************/ - -int stm32_exti_alarm(bool risingedge, bool fallingedge, bool event, - xcpt_t func, void *arg) -{ - g_alarm_callback = func; - g_callback_arg = arg; - - /* Install external interrupt handlers (if not already attached) */ - - if (func) - { - irq_attach(STM32_IRQ_RTCALRM, stm32_exti_alarm_isr, NULL); - up_enable_irq(STM32_IRQ_RTCALRM); - } - else - { - up_disable_irq(STM32_IRQ_RTCALRM); - } - - /* Configure rising/falling edges */ - - modifyreg32(STM32_EXTI_RTSR, - risingedge ? 0 : EXTI_RTC_ALARM, - risingedge ? EXTI_RTC_ALARM : 0); - modifyreg32(STM32_EXTI_FTSR, - fallingedge ? 0 : EXTI_RTC_ALARM, - fallingedge ? EXTI_RTC_ALARM : 0); - - /* Enable Events and Interrupts */ - - modifyreg32(STM32_EXTI_EMR, - event ? 0 : EXTI_RTC_ALARM, - event ? EXTI_RTC_ALARM : 0); - modifyreg32(STM32_EXTI_IMR, - func ? 0 : EXTI_RTC_ALARM, - func ? EXTI_RTC_ALARM : 0); - - return OK; -} diff --git a/arch/arm/src/stm32/stm32_exti_gpio.c b/arch/arm/src/stm32/stm32_exti_gpio.c deleted file mode 100644 index abe6146c0be82..0000000000000 --- a/arch/arm/src/stm32/stm32_exti_gpio.c +++ /dev/null @@ -1,370 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_exti_gpio.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include -#include - -#include -#include -#include -#include - -#include - -#include "arm_internal.h" -#include "chip.h" -#include "stm32_gpio.h" -#include "stm32_exti.h" - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -struct gpio_callback_s -{ - xcpt_t callback; - void *arg; -}; - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* Interrupt handlers attached to each EXTI */ - -static struct gpio_callback_s g_gpio_callbacks[16]; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Interrupt Service Routines - Dispatchers - ****************************************************************************/ - -static int stm32_exti0_isr(int irq, void *context, void *arg) -{ - int ret = OK; - - /* Clear the pending interrupt */ - - putreg32(0x0001, STM32_EXTI_PR); - - /* And dispatch the interrupt to the handler */ - - if (g_gpio_callbacks[0].callback != NULL) - { - xcpt_t callback = g_gpio_callbacks[0].callback; - void *cbarg = g_gpio_callbacks[0].arg; - - ret = callback(irq, context, cbarg); - } - - return ret; -} - -static int stm32_exti1_isr(int irq, void *context, void *arg) -{ - int ret = OK; - - /* Clear the pending interrupt */ - - putreg32(0x0002, STM32_EXTI_PR); - - /* And dispatch the interrupt to the handler */ - - if (g_gpio_callbacks[1].callback != NULL) - { - xcpt_t callback = g_gpio_callbacks[1].callback; - void *cbarg = g_gpio_callbacks[1].arg; - - ret = callback(irq, context, cbarg); - } - - return ret; -} - -static int stm32_exti2_isr(int irq, void *context, void *arg) -{ - int ret = OK; - - /* Clear the pending interrupt */ - - putreg32(0x0004, STM32_EXTI_PR); - - /* And dispatch the interrupt to the handler */ - - if (g_gpio_callbacks[2].callback != NULL) - { - xcpt_t callback = g_gpio_callbacks[2].callback; - void *cbarg = g_gpio_callbacks[2].arg; - - ret = callback(irq, context, cbarg); - } - - return ret; -} - -static int stm32_exti3_isr(int irq, void *context, void * arg) -{ - int ret = OK; - - /* Clear the pending interrupt */ - - putreg32(0x0008, STM32_EXTI_PR); - - /* And dispatch the interrupt to the handler */ - - if (g_gpio_callbacks[3].callback != NULL) - { - xcpt_t callback = g_gpio_callbacks[3].callback; - void *cbarg = g_gpio_callbacks[3].arg; - - ret = callback(irq, context, cbarg); - } - - return ret; -} - -static int stm32_exti4_isr(int irq, void *context, void *arg) -{ - int ret = OK; - - /* Clear the pending interrupt */ - - putreg32(0x0010, STM32_EXTI_PR); - - /* And dispatch the interrupt to the handler */ - - if (g_gpio_callbacks[4].callback != NULL) - { - xcpt_t callback = g_gpio_callbacks[4].callback; - void *cbarg = g_gpio_callbacks[4].arg; - - ret = callback(irq, context, cbarg); - } - - return ret; -} - -static int stm32_exti_multiisr(int irq, void *context, void *arg, - int first, int last) -{ - uint32_t pr; - int pin; - int ret = OK; - - /* Examine the state of each pin in the group */ - - pr = getreg32(STM32_EXTI_PR); - - /* And dispatch the interrupt to the handler */ - - for (pin = first; pin <= last; pin++) - { - /* Is an interrupt pending on this pin? */ - - uint32_t mask = (1 << pin); - if ((pr & mask) != 0) - { - /* Clear the pending interrupt */ - - putreg32(mask, STM32_EXTI_PR); - - /* And dispatch the interrupt to the handler */ - - if (g_gpio_callbacks[pin].callback != NULL) - { - xcpt_t callback = g_gpio_callbacks[pin].callback; - void *cbarg = g_gpio_callbacks[pin].arg; - int tmp; - - tmp = callback(irq, context, cbarg); - if (tmp < 0) - { - ret = tmp; - } - } - } - } - - return ret; -} - -static int stm32_exti95_isr(int irq, void *context, void *arg) -{ - return stm32_exti_multiisr(irq, context, arg, 5, 9); -} - -static int stm32_exti1510_isr(int irq, void *context, void *arg) -{ - return stm32_exti_multiisr(irq, context, arg, 10, 15); -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_gpiosetevent - * - * Description: - * Sets/clears GPIO based event and interrupt triggers. - * - * Input Parameters: - * - pinset: GPIO pin configuration - * - risingedge: Enables interrupt on rising edges - * - fallingedge: Enables interrupt on falling edges - * - event: Generate event when set - * - func: When non-NULL, generate interrupt - * - arg: Argument passed to the interrupt callback - * - * Returned Value: - * Zero (OK) on success; a negated errno value on failure indicating the - * nature of the failure. - * - ****************************************************************************/ - -int stm32_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, - bool event, xcpt_t func, void *arg) -{ - struct gpio_callback_s *shared_cbs; - uint32_t pin = pinset & GPIO_PIN_MASK; - uint32_t exti = STM32_EXTI_BIT(pin); - int irq; - xcpt_t handler; - int nshared; - int i; - - /* Select the interrupt handler for this EXTI pin */ - - if (pin < 5) - { - irq = pin + STM32_IRQ_EXTI0; - nshared = 1; - shared_cbs = &g_gpio_callbacks[pin]; - switch (pin) - { - case 0: - handler = stm32_exti0_isr; - break; - - case 1: - handler = stm32_exti1_isr; - break; - - case 2: - handler = stm32_exti2_isr; - break; - - case 3: - handler = stm32_exti3_isr; - break; - - default: - handler = stm32_exti4_isr; - break; - } - } - else if (pin < 10) - { - irq = STM32_IRQ_EXTI95; - handler = stm32_exti95_isr; - shared_cbs = &g_gpio_callbacks[5]; - nshared = 5; - } - else - { - irq = STM32_IRQ_EXTI1510; - handler = stm32_exti1510_isr; - shared_cbs = &g_gpio_callbacks[10]; - nshared = 6; - } - - /* Get the previous GPIO IRQ handler; Save the new IRQ handler. */ - - g_gpio_callbacks[pin].callback = func; - g_gpio_callbacks[pin].arg = arg; - - /* Install external interrupt handlers */ - - if (func) - { - irq_attach(irq, handler, NULL); - up_enable_irq(irq); - } - else - { - /* Only disable IRQ if shared handler does not have any active - * callbacks. - */ - - for (i = 0; i < nshared; i++) - { - if (shared_cbs[i].callback != NULL) - { - break; - } - } - - if (i == nshared) - { - up_disable_irq(irq); - } - } - - /* Configure GPIO, enable EXTI line enabled if event or interrupt is - * enabled. - */ - - if (event || func) - { - pinset |= GPIO_EXTI; - } - - stm32_configgpio(pinset); - - /* Configure rising/falling edges */ - - modifyreg32(STM32_EXTI_RTSR, - risingedge ? 0 : exti, - risingedge ? exti : 0); - modifyreg32(STM32_EXTI_FTSR, - fallingedge ? 0 : exti, - fallingedge ? exti : 0); - - /* Enable Events and Interrupts */ - - modifyreg32(STM32_EXTI_EMR, - event ? 0 : exti, - event ? exti : 0); - modifyreg32(STM32_EXTI_IMR, - func ? 0 : exti, - func ? exti : 0); - - return OK; -} diff --git a/arch/arm/src/stm32/stm32_exti_pwr.c b/arch/arm/src/stm32/stm32_exti_pwr.c deleted file mode 100644 index 97b0060ac8c9e..0000000000000 --- a/arch/arm/src/stm32/stm32_exti_pwr.c +++ /dev/null @@ -1,147 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_exti_pwr.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include -#include - -#include -#include -#include - -#include - -#include "arm_internal.h" -#include "chip.h" -#include "stm32_gpio.h" -#include "stm32_exti.h" -#include "stm32_exti_pwr.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* Interrupt handlers attached to the PVD EXTI */ - -static xcpt_t g_pvd_callback; -static void *g_callback_arg; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_exti_pvd_isr - * - * Description: - * EXTI PVD interrupt service routine/dispatcher - * - ****************************************************************************/ - -static int stm32_exti_pvd_isr(int irq, void *context, void *arg) -{ - int ret = OK; - - /* Clear the pending EXTI interrupt */ - - putreg32(EXTI_PVD_LINE, STM32_EXTI_PR); - - /* And dispatch the interrupt to the handler */ - - if (g_pvd_callback != NULL) - { - ret = g_pvd_callback(irq, context, g_callback_arg); - } - - return ret; -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_exti_pvd - * - * Description: - * Sets/clears EXTI PVD interrupt. - * - * Input Parameters: - * - rising/falling edge: enables interrupt on rising/falling edge - * - event: generate event when set - * - func: when non-NULL, generate interrupt - * - arg: Argument passed to the interrupt callback - * - * Returned Value: - * Zero (OK) returned on success; a negated errno value is returned on - * failure. - * - ****************************************************************************/ - -int stm32_exti_pvd(bool risingedge, bool fallingedge, bool event, - xcpt_t func, void *arg) -{ - /* Get the previous GPIO IRQ handler; Save the new IRQ handler. */ - - g_pvd_callback = func; - g_callback_arg = arg; - - /* Install external interrupt handlers (if not already attached) */ - - if (func) - { - irq_attach(STM32_IRQ_PVD, stm32_exti_pvd_isr, NULL); - up_enable_irq(STM32_IRQ_PVD); - } - else - { - up_disable_irq(STM32_IRQ_PVD); - } - - /* Configure rising/falling edges */ - - modifyreg32(STM32_EXTI_RTSR, - risingedge ? 0 : EXTI_PVD_LINE, - risingedge ? EXTI_PVD_LINE : 0); - modifyreg32(STM32_EXTI_FTSR, - fallingedge ? 0 : EXTI_PVD_LINE, - fallingedge ? EXTI_PVD_LINE : 0); - - /* Enable Events and Interrupts */ - - modifyreg32(STM32_EXTI_EMR, - event ? 0 : EXTI_PVD_LINE, - event ? EXTI_PVD_LINE : 0); - modifyreg32(STM32_EXTI_IMR, - func ? 0 : EXTI_PVD_LINE, - func ? EXTI_PVD_LINE : 0); - - return OK; -} diff --git a/arch/arm/src/stm32/stm32_exti_pwr.h b/arch/arm/src/stm32/stm32_exti_pwr.h deleted file mode 100644 index 9eb22090c6004..0000000000000 --- a/arch/arm/src/stm32/stm32_exti_pwr.h +++ /dev/null @@ -1,58 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_exti_pwr.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef STM32_EXTI_PWR_H_ -#define STM32_EXTI_PWR_H_ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_exti_pvd - * - * Description: - * Sets/clears EXTI PVD interrupt. - * - * Input Parameters: - * - rising/falling edge: enables interrupt on rising/falling edge - * - event: generate event when set - * - func: when non-NULL, generate interrupt - * - arg: Argument passed to the interrupt callback - * - * Returned Value: - * Zero (OK) returned on success; a negated errno value is returned on - * failure. - * - ****************************************************************************/ - -int stm32_exti_pvd(bool risingedge, bool fallingedge, bool event, - xcpt_t func, void *arg); - -#endif /* STM32_EXTI_PWR_H_ */ diff --git a/arch/arm/src/stm32/stm32_exti_wakeup.c b/arch/arm/src/stm32/stm32_exti_wakeup.c deleted file mode 100644 index dce70638d43ee..0000000000000 --- a/arch/arm/src/stm32/stm32_exti_wakeup.c +++ /dev/null @@ -1,139 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_exti_wakeup.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include -#include - -#include -#include -#include - -#include - -#include "arm_internal.h" -#include "chip.h" -#include "stm32_gpio.h" -#include "stm32_exti.h" - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* Interrupt handlers attached to the RTC WAKEUP EXTI */ - -static xcpt_t g_wakeup_callback; -static void *g_callback_arg; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_exti_wakeup_isr - * - * Description: - * EXTI periodic WAKEUP interrupt service routine/dispatcher - * - ****************************************************************************/ - -static int stm32_exti_wakeup_isr(int irq, void *context, void *arg) -{ - int ret = OK; - - /* Dispatch the interrupt to the handler */ - - if (g_wakeup_callback != NULL) - { - ret = g_wakeup_callback(irq, context, g_callback_arg); - } - - /* Clear the pending EXTI interrupt */ - - putreg32(EXTI_RTC_WAKEUP, STM32_EXTI_PR); - - return ret; -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_exti_wakeup - * - * Description: - * Sets/clears EXTI wakeup interrupt. - * - * Input Parameters: - * - rising/falling edge: enables interrupt on rising/falling edges - * - event: generate event when set - * - func: when non-NULL, generate interrupt - * - * Returned Value: - * Zero (OK) on success; a negated errno value on failure indicating the - * nature of the failure. - * - ****************************************************************************/ - -int stm32_exti_wakeup(bool risingedge, bool fallingedge, bool event, - xcpt_t func, void *arg) -{ - g_wakeup_callback = func; - g_callback_arg = arg; - - /* Install external interrupt handlers (if not already attached) */ - - if (func) - { - irq_attach(STM32_IRQ_RTC_WKUP, stm32_exti_wakeup_isr, NULL); - up_enable_irq(STM32_IRQ_RTC_WKUP); - } - else - { - up_disable_irq(STM32_IRQ_RTC_WKUP); - } - - /* Configure rising/falling edges */ - - modifyreg32(STM32_EXTI_RTSR, - risingedge ? 0 : EXTI_RTC_WAKEUP, - risingedge ? EXTI_RTC_WAKEUP : 0); - modifyreg32(STM32_EXTI_FTSR, - fallingedge ? 0 : EXTI_RTC_WAKEUP, - fallingedge ? EXTI_RTC_WAKEUP : 0); - - /* Enable Events and Interrupts */ - - modifyreg32(STM32_EXTI_EMR, - event ? 0 : EXTI_RTC_WAKEUP, - event ? EXTI_RTC_WAKEUP : 0); - modifyreg32(STM32_EXTI_IMR, - func ? 0 : EXTI_RTC_WAKEUP, - func ? EXTI_RTC_WAKEUP : 0); - - return OK; -} diff --git a/arch/arm/src/stm32/stm32_fdcan.c b/arch/arm/src/stm32/stm32_fdcan.c deleted file mode 100644 index 519b77626e933..0000000000000 --- a/arch/arm/src/stm32/stm32_fdcan.c +++ /dev/null @@ -1,3550 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_fdcan.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - *s - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include - -#include "arm_internal.h" -#include "stm32_fdcan.h" -#include "hardware/stm32_pinmap.h" -#include "stm32_gpio.h" -#include "stm32_rcc.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Clock source *************************************************************/ - -#define FDCANCLK_PDIV (0) - -#if FDCANCLK_PDIV == 0 -# define STM32_FDCANCLK_FREQUENCY (STM32_FDCAN_FREQUENCY / (1)) -#else -# define STM32_FDCANCLK_FREQUENCY (STM32_FDCAN_FREQUENCY / (2 * FDCANCLK_PDIV)) -#endif - -/* General Configuration ****************************************************/ - -#if defined(CONFIG_STM32_STM32G4XXX) - -/* FDCAN Message RAM */ - -# define FDCAN_MSGRAM_WORDS (212) -# define STM32_CANRAM1_BASE (STM32_CANRAM_BASE + 0x0000) -# define STM32_CANRAM2_BASE (STM32_CANRAM_BASE + 1*(FDCAN_MSGRAM_WORDS * 4) + 4) -# define STM32_CANRAM3_BASE (STM32_CANRAM_BASE + 2*(FDCAN_MSGRAM_WORDS * 4) + 4) - -# ifdef CONFIG_STM32_FDCAN1 -# define FDCAN1_STDFILTER_SIZE (28) -# define FDCAN1_EXTFILTER_SIZE (8) -# define FDCAN1_RXFIFO0_SIZE (3) -# define FDCAN1_RXFIFO1_SIZE (3) -# define FDCAN1_TXEVENTFIFO_SIZE (3) -# define FDCAN1_TXFIFIOQ_SIZE (3) - -# define FDCAN1_STDFILTER_WORDS (28) -# define FDCAN1_EXTFILTER_WORDS (16) -# define FDCAN1_RXFIFO0_WORDS (54) -# define FDCAN1_RXFIFO1_WORDS (54) -# define FDCAN1_TXEVENTFIFO_WORDS (6) -# define FDCAN1_TXFIFIOQ_WORDS (54) -# endif -# ifdef CONFIG_STM32_FDCAN2 -# define FDCAN2_STDFILTER_SIZE (28) -# define FDCAN2_EXTFILTER_SIZE (8) -# define FDCAN2_RXFIFO0_SIZE (3) -# define FDCAN2_RXFIFO1_SIZE (3) -# define FDCAN2_TXEVENTFIFO_SIZE (3) -# define FDCAN2_TXFIFIOQ_SIZE (3) - -# define FDCAN2_STDFILTER_WORDS (28) -# define FDCAN2_EXTFILTER_WORDS (16) -# define FDCAN2_RXFIFO0_WORDS (54) -# define FDCAN2_RXFIFO1_WORDS (54) -# define FDCAN2_TXEVENTFIFO_WORDS (6) -# define FDCAN2_TXFIFIOQ_WORDS (54) -# endif -# ifdef CONFIG_STM32_FDCAN3 -# define FDCAN3_STDFILTER_SIZE (28) -# define FDCAN3_EXTFILTER_SIZE (8) -# define FDCAN3_RXFIFO0_SIZE (3) -# define FDCAN3_RXFIFO1_SIZE (3) -# define FDCAN3_TXEVENTFIFO_SIZE (3) -# define FDCAN3_TXFIFIOQ_SIZE (3) - -# define FDCAN3_STDFILTER_WORDS (28) -# define FDCAN3_EXTFILTER_WORDS (16) -# define FDCAN3_RXFIFO0_WORDS (54) -# define FDCAN3_RXFIFO1_WORDS (54) -# define FDCAN3_TXEVENTFIFO_WORDS (6) -# define FDCAN3_TXFIFIOQ_WORDS (54) -# endif -#else -# error -#endif - -/* FDCAN1 Configuration *****************************************************/ - -#ifdef CONFIG_STM32_FDCAN1 - -/* Bit timing */ - -# define FDCAN1_NTSEG1 (CONFIG_STM32_FDCAN1_NTSEG1 - 1) -# define FDCAN1_NTSEG2 (CONFIG_STM32_FDCAN1_NTSEG2 - 1) -# define FDCAN1_NBRP ((STM32_FDCANCLK_FREQUENCY / \ - ((FDCAN1_NTSEG1 + FDCAN1_NTSEG2 + 3) * \ - CONFIG_STM32_FDCAN1_BITRATE)) - 1) -# define FDCAN1_NSJW (CONFIG_STM32_FDCAN1_NSJW - 1) - -# if FDCAN1_NTSEG1 > FDCAN_NBTP_NTSEG1_MAX -# error Invalid FDCAN1 NTSEG1 -# endif -# if FDCAN1_NTSEG2 > FDCAN_NBTP_NTSEG2_MAX -# error Invalid FDCAN1 NTSEG2 -# endif -# if FDCAN1_NSJW > FDCAN_NBTP_NSJW_MAX -# error Invalid FDCAN1 NSJW -# endif -# if FDCAN1_NBRP > FDCAN_NBTP_NBRP_MAX -# error Invalid FDCAN1 NBRP -# endif - -# ifdef CONFIG_STM32_FDCAN1_FD_BRS -# define FDCAN1_DTSEG1 (CONFIG_STM32_FDCAN1_DTSEG1 - 1) -# define FDCAN1_DTSEG2 (CONFIG_STM32_FDCAN1_DTSEG2 - 1) -# define FDCAN1_DBRP ((STM32_FDCANCLK_FREQUENCY / \ - ((FDCAN1_DTSEG1 + FDCAN1_DTSEG2 + 3) * \ - CONFIG_STM32_FDCAN1_DBITRATE)) - 1) -# define FDCAN1_DSJW (CONFIG_STM32_FDCAN1_DSJW - 1) -# else -# define FDCAN1_DTSEG1 1 -# define FDCAN1_DTSEG2 1 -# define FDCAN1_DBRP 1 -# define FDCAN1_DSJW 1 -# endif /* CONFIG_STM32_FDCAN1_FD_BRS */ - -# if FDCAN1_DTSEG1 > FDCAN_DBTP_DTSEG1_MAX -# error Invalid FDCAN1 DTSEG1 -# endif -# if FDCAN1_DTSEG2 > FDCAN_DBTP_DTSEG2_MAX -# error Invalid FDCAN1 DTSEG2 -# endif -# if FDCAN1_DBRP > FDCAN_DBTP_DBRP_MAX -# error Invalid FDCAN1 DBRP -# endif -# if FDCAN1_DSJW > FDCAN_DBTP_DSJW_MAX -# error Invalid FDCAN1 DSJW -# endif - -/* FDCAN1 Message RAM Configuration *****************************************/ - -/* FDCAN1 Message RAM Layout */ - -# define FDCAN1_STDFILTER_INDEX 0 -# define FDCAN1_EXTFILTERS_INDEX (FDCAN1_STDFILTER_INDEX + FDCAN1_STDFILTER_WORDS) -# define FDCAN1_RXFIFO0_INDEX (FDCAN1_EXTFILTERS_INDEX + FDCAN1_EXTFILTER_WORDS) -# define FDCAN1_RXFIFO1_INDEX (FDCAN1_RXFIFO0_INDEX + FDCAN1_RXFIFO0_WORDS) -# define FDCAN1_TXEVENTFIFO_INDEX (FDCAN1_RXFIFO1_INDEX + FDCAN1_RXFIFO1_WORDS) -# define FDCAN1_TXFIFOQ_INDEX (FDCAN1_TXEVENTFIFO_INDEX + FDCAN1_TXEVENTFIFO_WORDS) -# define FDCAN1_MSGRAM_WORDS (FDCAN1_TXFIFOQ_INDEX + FDCAN1_TXFIFIOQ_WORDS) - -#endif /* CONFIG_STM32_FDCAN1 */ - -/* FDCAN2 Configuration *****************************************************/ - -#ifdef CONFIG_STM32_FDCAN2 - -/* Bit timing */ - -# define FDCAN2_NTSEG1 (CONFIG_STM32_FDCAN2_NTSEG1 - 1) -# define FDCAN2_NTSEG2 (CONFIG_STM32_FDCAN2_NTSEG2 - 1) -# define FDCAN2_NBRP (((STM32_FDCANCLK_FREQUENCY / \ - ((FDCAN2_NTSEG1 + FDCAN2_NTSEG2 + 3) * \ - CONFIG_STM32_FDCAN2_BITRATE)) - 1)) -# define FDCAN2_NSJW (CONFIG_STM32_FDCAN2_NSJW - 1) - -# if FDCAN2_NTSEG1 > FDCAN_NBTP_NTSEG1_MAX -# error Invalid FDCAN2 NTSEG1 -# endif -# if FDCAN2_NTSEG2 > FDCAN_NBTP_NTSEG2_MAX -# error Invalid FDCAN2 NTSEG2 -# endif -# if FDCAN2_NSJW > FDCAN_NBTP_NSJW_MAX -# error Invalid FDCAN2 NSJW -# endif -# if FDCAN2_NBRP > FDCAN_NBTP_NBRP_MAX -# error Invalid FDCAN1 NBRP -# endif - -# ifdef CONFIG_STM32_FDCAN2_FD_BRS -# define FDCAN2_DTSEG1 (CONFIG_STM32_FDCAN2_DTSEG1 - 1) -# define FDCAN2_DTSEG2 (CONFIG_STM32_FDCAN2_DTSEG2 - 1) -# define FDCAN2_DBRP (((STM32_FDCANCLK_FREQUENCY / \ - ((FDCAN2_DTSEG1 + FDCAN2_DTSEG2 + 3) * \ - CONFIG_STM32_FDCAN2_DBITRATE)) - 1)) -# define FDCAN2_DSJW (CONFIG_STM32_FDCAN2_DSJW - 1) -# else -# define FDCAN2_DTSEG1 1 -# define FDCAN2_DTSEG2 1 -# define FDCAN2_DBRP 1 -# define FDCAN2_DSJW 1 -# endif /* CONFIG_STM32_FDCAN2_FD_BRS */ - -# if FDCAN2_DTSEG1 > FDCAN_DBTP_DTSEG1_MAX -# error Invalid FDCAN2 DTSEG1 -# endif -# if FDCAN2_DTSEG2 > FDCAN_DBTP_DTSEG2_MAX -# error Invalid FDCAN2 DTSEG2 -# endif -# if FDCAN2_DBRP > FDCAN_DBTP_DBRP_MAX -# error Invalid FDCAN2 DBRP -# endif -# if FDCAN2_DSJW > FDCAN_DBTP_DSJW_MAX -# error Invalid FDCAN2 DSJW -# endif - -/* FDCAN2 Message RAM Configuration *****************************************/ - -/* FDCAN2 Message RAM Layout */ - -# define FDCAN2_STDFILTER_INDEX 0 -# define FDCAN2_EXTFILTERS_INDEX (FDCAN2_STDFILTER_INDEX + FDCAN2_STDFILTER_WORDS) -# define FDCAN2_RXFIFO0_INDEX (FDCAN2_EXTFILTERS_INDEX + FDCAN2_EXTFILTER_WORDS) -# define FDCAN2_RXFIFO1_INDEX (FDCAN2_RXFIFO0_INDEX + FDCAN2_RXFIFO0_WORDS) -# define FDCAN2_TXEVENTFIFO_INDEX (FDCAN2_RXFIFO1_INDEX + FDCAN2_RXFIFO1_WORDS) -# define FDCAN2_TXFIFOQ_INDEX (FDCAN2_TXEVENTFIFO_INDEX + FDCAN2_TXEVENTFIFO_WORDS) -# define FDCAN2_MSGRAM_WORDS (FDCAN2_TXFIFOQ_INDEX + FDCAN2_TXFIFIOQ_WORDS) - -#endif /* CONFIG_STM32_FDCAN2 */ - -/* FDCAN3 Configuration *****************************************************/ - -#ifdef CONFIG_STM32_FDCAN3 - -/* Bit timing */ - -# define FDCAN3_NTSEG1 (CONFIG_STM32_FDCAN3_NTSEG1 - 1) -# define FDCAN3_NTSEG2 (CONFIG_STM32_FDCAN3_NTSEG2 - 1) -# define FDCAN3_NBRP (((STM32_FDCANCLK_FREQUENCY / \ - ((FDCAN3_NTSEG1 + FDCAN3_NTSEG2 + 3) * \ - CONFIG_STM32_FDCAN3_BITRATE)) - 1)) -# define FDCAN3_NSJW (CONFIG_STM32_FDCAN3_NSJW - 1) - -# if FDCAN3_NTSEG1 > FDCAN_NBTP_NTSEG1_MAX -# error Invalid FDCAN3 NTSEG1 -# endif -# if FDCAN3_NTSEG2 > FDCAN_NBTP_NTSEG2_MAX -# error Invalid FDCAN3 NTSEG2 -# endif -# if FDCAN3_NSJW > FDCAN_NBTP_NSJW_MAX -# error Invalid FDCAN3 NSJW -# endif -# if FDCAN3_NBRP > FDCAN_NBTP_NBRP_MAX -# error Invalid FDCAN1 NBRP -# endif - -# ifdef CONFIG_STM32_FDCAN3_FD_BRS -# define FDCAN3_DTSEG1 (CONFIG_STM32_FDCAN3_DTSEG1 - 1) -# define FDCAN3_DTSEG2 (CONFIG_STM32_FDCAN3_DTSEG2 - 1) -# define FDCAN3_DBRP (((STM32_FDCANCLK_FREQUENCY / \ - ((FDCAN3_DTSEG1 + FDCAN3_DTSEG2 + 3) * \ - CONFIG_STM32_FDCAN3_DBITRATE)) - 1)) -# define FDCAN3_DSJW (CONFIG_STM32_FDCAN3_DSJW - 1) -# else -# define FDCAN3_DTSEG1 1 -# define FDCAN3_DTSEG2 1 -# define FDCAN3_DBRP 1 -# define FDCAN3_DSJW 1 -# endif /* CONFIG_STM32_FDCAN3_FD_BRS */ - -# if FDCAN3_DTSEG1 > FDCAN_DBTP_DTSEG1_MAX -# error Invalid FDCAN3 DTSEG1 -# endif -# if FDCAN3_DTSEG2 > FDCAN_DBTP_DTSEG2_MAX -# error Invalid FDCAN3 DTSEG2 -# endif -# if FDCAN3_DBRP > FDCAN_DBTP_DBRP_MAX -# error Invalid FDCAN3 DBRP -# endif -# if FDCAN3_DSJW > FDCAN_DBTP_DSJW_MAX -# error Invalid FDCAN3 DSJW -# endif - -/* FDCAN3 Message RAM Configuration *****************************************/ - -/* FDCAN3 Message RAM Layout */ - -# define FDCAN3_STDFILTER_INDEX 0 -# define FDCAN3_EXTFILTERS_INDEX (FDCAN3_STDFILTER_INDEX + FDCAN3_STDFILTER_WORDS) -# define FDCAN3_RXFIFO0_INDEX (FDCAN3_EXTFILTERS_INDEX + FDCAN3_EXTFILTER_WORDS) -# define FDCAN3_RXFIFO1_INDEX (FDCAN3_RXFIFO0_INDEX + FDCAN3_RXFIFO0_WORDS) -# define FDCAN3_TXEVENTFIFO_INDEX (FDCAN3_RXFIFO1_INDEX + FDCAN3_RXFIFO1_WORDS) -# define FDCAN3_TXFIFOQ_INDEX (FDCAN3_TXEVENTFIFO_INDEX + FDCAN3_TXEVENTFIFO_WORDS) -# define FDCAN3_MSGRAM_WORDS (FDCAN3_TXFIFOQ_INDEX + FDCAN3_TXFIFIOQ_WORDS) - -#endif /* CONFIG_STM32_FDCAN3 */ - -/* Loopback mode */ - -#undef STM32_FDCAN_LOOPBACK -#if defined(CONFIG_STM32_FDCAN1_LOOPBACK) || \ - defined(CONFIG_STM32_FDCAN2_LOOPBACK) || \ - defined(CONFIG_STM32_FDCAN3_LOOPBACK) -# define STM32_FDCAN_LOOPBACK 1 -#endif - -/* Interrupts ***************************************************************/ - -/* Common interrupts - * - * FDCAN_INT_TSW - Timestamp Wraparound - * FDCAN_INT_MRAF - Message RAM Access Failure - * FDCAN_INT_TOO - Timeout Occurred - * FDCAN_INT_ELO - Error Logging Overflow - * FDCAN_INT_EP - Error Passive - * FDCAN_INT_EW - Warning Status - * FDCAN_INT_BO - Bus_Off Status - * FDCAN_INT_WDI - Watchdog Interrupt - * FDCAN_INT_PEA - Protocol Error in Arbritration Phase - * FDCAN_INT_PED - Protocol Error in Data Phase - */ - -#define FDCAN_CMNERR_INTS (FDCAN_INT_MRAF | FDCAN_INT_TOO | FDCAN_INT_EP | \ - FDCAN_INT_BO | FDCAN_INT_WDI | FDCAN_INT_PEA | \ - FDCAN_INT_PED) -#define FDCAN_COMMON_INTS FDCAN_CMNERR_INTS - -/* RXFIFO mode interrupts - * - * FDCAN_INT_RF0N - Receive FIFO 0 New Message - * FDCAN_INT_RF0F - Receive FIFO 0 Full - * FDCAN_INT_RF0L - Receive FIFO 0 Message Lost - * FDCAN_INT_RF1N - Receive FIFO 1 New Message - * FDCAN_INT_RF1F - Receive FIFO 1 Full - * FDCAN_INT_RF1L - Receive FIFO 1 Message Lost - * FDCAN_INT_HPM - High Priority Message Received - * - */ - -#define FDCAN_RXCOMMON_INTS 0 -#define FDCAN_RXFIFO0_INTS (FDCAN_INT_RF0N | FDCAN_INT_RF0L) -#define FDCAN_RXFIFO1_INTS (FDCAN_INT_RF1N | FDCAN_INT_RF1L) -#define FDCAN_RXFIFO_INTS (FDCAN_RXFIFO0_INTS | FDCAN_RXFIFO1_INTS | \ - FDCAN_INT_HPM | FDCAN_RXCOMMON_INTS) - -#define FDCAN_RXERR_INTS (FDCAN_INT_RF0L | FDCAN_INT_RF1L) - -/* TX FIFOQ mode interrupts - * - * FDCAN_INT_TFE - Tx FIFO Empty - * - * TX Event FIFO interrupts - * - * FDCAN_INT_TEFN - Tx Event FIFO New Entry - * FDCAN_INT_TEFF - Tx Event FIFO Full - * FDCAN_INT_TEFL - Tx Event FIFO Element Lost - * - * Mode-independent TX-related interrupts - * - * FDCAN_INT_TC - Transmission Completed - * FDCAN_INT_TCF - Transmission Cancellation Finished - */ - -#define FDCAN_TXCOMMON_INTS (FDCAN_INT_TC | FDCAN_INT_TCF) -#define FDCAN_TXFIFOQ_INTS (FDCAN_INT_TFE | FDCAN_TXCOMMON_INTS) -#define FDCAN_TXEVFIFO_INTS (FDCAN_INT_TEFN | FDCAN_INT_TEFF | \ - FDCAN_INT_TEFL) -#define FDCAN_TXDEDBUF_INTS FDCAN_TXCOMMON_INTS - -#define FDCAN_TXERR_INTS (FDCAN_INT_TEFL | FDCAN_INT_PEA | FDCAN_INT_PED) - -/* Common-, TX- and RX-Error-Mask */ - -#define FDCAN_ANYERR_INTS (FDCAN_CMNERR_INTS | FDCAN_RXERR_INTS | FDCAN_TXERR_INTS) - -/* Convenience macro for clearing all interrupts */ - -#define FDCAN_INT_ALL 0x3fcfffff - -/* Debug ********************************************************************/ - -/* Debug configurations that may be enabled just for testing FDCAN */ - -#ifndef CONFIG_DEBUG_CAN_INFO -# undef CONFIG_STM32_FDCAN_REGDEBUG -#endif - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/* CAN frame format */ - -enum stm32_frameformat_e -{ - FDCAN_ISO11898_1_FORMAT = 0, /* Frame format according to ISO11898-1 */ - FDCAN_NONISO_BOSCH_V1_FORMAT = 1 /* Frame format according to Bosch CAN FD V1.0 */ -}; - -/* CAN mode of operation */ - -enum stm32_canmode_e -{ - FDCAN_CLASSIC_MODE = 0, /* Classic CAN operation */ -#ifdef CONFIG_CAN_FD - FDCAN_FD_MODE = 1, /* CAN FD operation */ - FDCAN_FD_BRS_MODE = 2 /* CAN FD operation with bit rate switching */ -#endif -}; - -/* CAN driver state */ - -enum can_state_s -{ - FDCAN_STATE_UNINIT = 0, /* Not yet initialized */ - FDCAN_STATE_RESET, /* Initialized, reset state */ - FDCAN_STATE_SETUP, /* fdcan_setup() has been called */ - FDCAN_STATE_DISABLED /* Disabled by a fdcan_shutdown() */ -}; - -/* This structure describes the FDCAN message RAM layout */ - -struct stm32_msgram_s -{ - volatile uint32_t *stdfilters; /* Standard filters */ - volatile uint32_t *extfilters; /* Extended filters */ - volatile uint32_t *rxfifo0; /* RX FIFO0 */ - volatile uint32_t *rxfifo1; /* RX FIFO1 */ - volatile uint32_t *txeventfifo; /* TX event FIFO */ - volatile uint32_t *txfifoq; /* TX FIFO queue */ -}; - -/* This structure provides the constant configuration of a FDCAN peripheral */ - -struct stm32_config_s -{ - uint32_t rxpinset; /* RX pin configuration */ - uint32_t txpinset; /* TX pin configuration */ - uintptr_t base; /* Base address of the FDCAN registers */ - uint32_t baud; /* Configured baud */ - uint32_t nbtp; /* Nominal bit timing/prescaler register setting */ - uint32_t dbtp; /* Data bit timing/prescaler register setting */ - uint8_t port; /* FDCAN port number (1 or 2) */ - uint8_t irq0; /* FDCAN peripheral IRQ number for interrupt line 0 */ - uint8_t irq1; /* FDCAN peripheral IRQ number for interrupt line 1 */ - uint8_t mode; /* See enum stm32_canmode_e */ - uint8_t format; /* See enum stm32_frameformat_e */ - uint8_t nstdfilters; /* Number of standard filters */ - uint8_t nextfilters; /* Number of extended filters */ - uint8_t nrxfifo0; /* Number of RX FIFO0 elements */ - uint8_t nrxfifo1; /* Number of RX FIFO1 elements */ - uint8_t ntxeventfifo; /* Number of TXevent FIFO elements */ - uint8_t ntxfifoq; /* Number of TX FIFO queue elements */ - uint8_t rxfifo0esize; /* RX FIFO0 element size (words) */ - uint8_t rxfifo1esize; /* RX FIFO1 element size (words) */ - uint8_t txeventesize; /* TXevent element size (words) */ - uint8_t txbufferesize; /* TX buffer element size (words) */ -#ifdef STM32_FDCAN_LOOPBACK - bool loopback; /* True: Loopback mode */ -#endif - - /* FDCAN message RAM layout */ - - struct stm32_msgram_s msgram; -}; - -/* This structure provides the current state of a FDCAN peripheral */ - -struct stm32_fdcan_s -{ - /* The constant configuration */ - - const struct stm32_config_s *config; - - uint8_t state; /* See enum can_state_s */ -#ifdef CONFIG_CAN_EXTID - uint8_t nextalloc; /* Number of allocated extended filters */ -#endif - uint8_t nstdalloc; /* Number of allocated standard filters */ - uint32_t nbtp; /* Current nominal bit timing */ - uint32_t dbtp; /* Current data bit timing */ - uint32_t rxints; /* Configured RX interrupts */ - uint32_t txints; /* Configured TX interrupts */ - -#ifdef CONFIG_CAN_EXTID - uint32_t extfilters[2]; /* Extended filter bit allocator. 2*32=64 */ -#endif - uint32_t stdfilters[4]; /* Standard filter bit allocator. 4*32=128 */ - -#ifdef CONFIG_STM32_FDCAN_REGDEBUG - uintptr_t regaddr; /* Last register address read */ - uint32_t regval; /* Last value read from the register */ - unsigned int count; /* Number of times that the value was read */ -#endif -}; - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -/* FDCAN Register access */ - -static uint32_t fdcan_getreg(struct stm32_fdcan_s *priv, int offset); -static void fdcan_putreg(struct stm32_fdcan_s *priv, int offset, - uint32_t regval); -#ifdef CONFIG_STM32_FDCAN_REGDEBUG -static void fdcan_dumpregs(struct stm32_fdcan_s *priv, - const char *msg); -static void fdcan_dumprxregs(struct stm32_fdcan_s *priv, - const char *msg); -static void fdcan_dumptxregs(struct stm32_fdcan_s *priv, - const char *msg); -static void fdcan_dumpramlayout(struct stm32_fdcan_s *priv); -#else -# define fdcan_dumpregs(priv,msg) -# define fdcan_dumprxregs(priv,msg) -# define fdcan_dumptxregs(priv,msg) -# define fdcan_dumpramlayout(priv) -#endif - -/* FDCAN helpers */ - -static uint8_t fdcan_dlc2bytes(struct stm32_fdcan_s *priv, uint8_t dlc); - -#ifdef CONFIG_CAN_EXTID -static int fdcan_add_extfilter(struct stm32_fdcan_s *priv, - struct canioc_extfilter_s *extconfig); -static int fdcan_del_extfilter(struct stm32_fdcan_s *priv, int ndx); -#endif -static int fdcan_add_stdfilter(struct stm32_fdcan_s *priv, - struct canioc_stdfilter_s *stdconfig); -static int fdcan_del_stdfilter(struct stm32_fdcan_s *priv, int ndx); - -static int -fdcan_start_busoff_recovery_sequence(struct stm32_fdcan_s *priv); - -/* CAN driver methods */ - -static void fdcan_reset(struct can_dev_s *dev); -static int fdcan_setup(struct can_dev_s *dev); -static void fdcan_shutdown(struct can_dev_s *dev); -static void fdcan_rxint(struct can_dev_s *dev, bool enable); -static void fdcan_txint(struct can_dev_s *dev, bool enable); -static int fdcan_ioctl(struct can_dev_s *dev, int cmd, - unsigned long arg); -static int fdcan_remoterequest(struct can_dev_s *dev, uint16_t id); -static int fdcan_send(struct can_dev_s *dev, struct can_msg_s *msg); -static bool fdcan_txready(struct can_dev_s *dev); -static bool fdcan_txempty(struct can_dev_s *dev); - -/* FDCAN interrupt handling */ - -#ifdef CONFIG_CAN_ERRORS -static void fdcan_error(struct can_dev_s *dev, uint32_t status); -#endif -static void fdcan_receive(struct can_dev_s *dev, - volatile uint32_t *rxbuffer, - unsigned long nwords); -static int fdcan_interrupt(int irq, void *context, void *arg); - -/* Hardware initialization */ - -static int fdcan_hw_initialize(struct stm32_fdcan_s *priv); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -static const struct can_ops_s g_fdcanops = -{ - .co_reset = fdcan_reset, - .co_setup = fdcan_setup, - .co_shutdown = fdcan_shutdown, - .co_rxint = fdcan_rxint, - .co_txint = fdcan_txint, - .co_ioctl = fdcan_ioctl, - .co_remoterequest = fdcan_remoterequest, - .co_send = fdcan_send, - .co_txready = fdcan_txready, - .co_txempty = fdcan_txempty, -}; - -#ifdef CONFIG_STM32_FDCAN1 -/* Message RAM allocation */ - -/* Constant configuration */ - -static const struct stm32_config_s g_fdcan1const = -{ - .rxpinset = GPIO_FDCAN1_RX, - .txpinset = GPIO_FDCAN1_TX, - .base = STM32_FDCAN1_BASE, - .baud = CONFIG_STM32_FDCAN1_BITRATE, - .nbtp = FDCAN_NBTP_NBRP(FDCAN1_NBRP) | - FDCAN_NBTP_NTSEG1(FDCAN1_NTSEG1) | - FDCAN_NBTP_NTSEG2(FDCAN1_NTSEG2) | - FDCAN_NBTP_NSJW(FDCAN1_NSJW), - .dbtp = FDCAN_DBTP_DBRP(FDCAN1_DBRP) | - FDCAN_DBTP_DTSEG1(FDCAN1_DTSEG1) | - FDCAN_DBTP_DTSEG2(FDCAN1_DTSEG2) | - FDCAN_DBTP_DSJW(FDCAN1_DSJW), - .port = 1, - .irq0 = STM32_IRQ_FDCAN1_0, - .irq1 = STM32_IRQ_FDCAN1_1, -#if defined(CONFIG_STM32_FDCAN1_CLASSIC) - .mode = FDCAN_CLASSIC_MODE, -#elif defined(CONFIG_STM32_FDCAN1_FD) - .mode = FDCAN_FD_MODE, -#else - .mode = FDCAN_FD_BRS_MODE, -#endif -#if defined(CONFIG_STM32_FDCAN1_NONISO_FORMAT) - .format = FDCAN_NONISO_BOSCH_V1_FORMAT, -#else - .format = FDCAN_ISO11898_1_FORMAT, -#endif - .nstdfilters = FDCAN1_STDFILTER_SIZE, - .nextfilters = FDCAN1_EXTFILTER_SIZE, - .nrxfifo0 = FDCAN1_RXFIFO0_SIZE, - .nrxfifo1 = FDCAN1_RXFIFO1_SIZE, - .ntxeventfifo = FDCAN1_TXEVENTFIFO_SIZE, - .ntxfifoq = FDCAN1_TXFIFIOQ_SIZE, - .rxfifo0esize = (FDCAN1_RXFIFO0_WORDS / FDCAN1_RXFIFO0_SIZE), - .rxfifo1esize = (FDCAN1_RXFIFO1_WORDS / FDCAN1_RXFIFO1_SIZE), - .txeventesize = (FDCAN1_TXEVENTFIFO_WORDS / FDCAN1_TXEVENTFIFO_SIZE), - .txbufferesize = (FDCAN1_TXFIFIOQ_WORDS / FDCAN1_TXFIFIOQ_SIZE), - -#ifdef CONFIG_STM32_FDCAN1_LOOPBACK - .loopback = true, -#endif - - /* FDCAN1 Message RAM */ - - .msgram = - { - (uint32_t *)(STM32_CANRAM1_BASE + (FDCAN1_STDFILTER_INDEX << 2)), - (uint32_t *)(STM32_CANRAM1_BASE + (FDCAN1_EXTFILTERS_INDEX << 2)), - (uint32_t *)(STM32_CANRAM1_BASE + (FDCAN1_RXFIFO0_INDEX << 2)), - (uint32_t *)(STM32_CANRAM1_BASE + (FDCAN1_RXFIFO1_INDEX << 2)), - (uint32_t *)(STM32_CANRAM1_BASE + (FDCAN1_TXEVENTFIFO_INDEX << 2)), - (uint32_t *)(STM32_CANRAM1_BASE + (FDCAN1_TXFIFOQ_INDEX << 2)) - } -}; - -/* FDCAN1 variable driver state */ - -static struct stm32_fdcan_s g_fdcan1priv; -static struct can_dev_s g_fdcan1dev; - -#endif /* CONFIG_STM32_FDCAN1 */ - -#ifdef CONFIG_STM32_FDCAN2 -/* FDCAN2 message RAM allocation */ - -/* FDCAN2 constant configuration */ - -static const struct stm32_config_s g_fdcan2const = -{ - .rxpinset = GPIO_FDCAN2_RX, - .txpinset = GPIO_FDCAN2_TX, - .base = STM32_FDCAN2_BASE, - .baud = CONFIG_STM32_FDCAN2_BITRATE, - .nbtp = FDCAN_NBTP_NBRP(FDCAN2_NBRP) | - FDCAN_NBTP_NTSEG1(FDCAN2_NTSEG1) | - FDCAN_NBTP_NTSEG2(FDCAN2_NTSEG2) | - FDCAN_NBTP_NSJW(FDCAN2_NSJW), - .dbtp = FDCAN_DBTP_DBRP(FDCAN2_DBRP) | - FDCAN_DBTP_DTSEG1(FDCAN2_DTSEG1) | - FDCAN_DBTP_DTSEG2(FDCAN2_DTSEG2) | - FDCAN_DBTP_DSJW(FDCAN2_DSJW), - .port = 2, - .irq0 = STM32_IRQ_FDCAN2_0, - .irq1 = STM32_IRQ_FDCAN2_1, -#if defined(CONFIG_STM32_FDCAN2_CLASSIC) - .mode = FDCAN_CLASSIC_MODE, -#elif defined(CONFIG_STM32_FDCAN2_FD) - .mode = FDCAN_FD_MODE, -#else - .mode = FDCAN_FD_BRS_MODE, -#endif -#if defined(CONFIG_STM32_FDCAN2_NONISO_FORMAT) - .format = FDCAN_NONISO_BOSCH_V1_FORMAT, -#else - .format = FDCAN_ISO11898_1_FORMAT, -#endif - .nstdfilters = FDCAN2_STDFILTER_SIZE, - .nextfilters = FDCAN2_EXTFILTER_SIZE, - .nrxfifo0 = FDCAN2_RXFIFO0_SIZE, - .nrxfifo1 = FDCAN2_RXFIFO1_SIZE, - .ntxeventfifo = FDCAN2_TXEVENTFIFO_SIZE, - .ntxfifoq = FDCAN2_TXFIFIOQ_SIZE, - .rxfifo0esize = (FDCAN2_RXFIFO0_WORDS / FDCAN2_RXFIFO0_SIZE), - .rxfifo1esize = (FDCAN2_RXFIFO1_WORDS / FDCAN2_RXFIFO1_SIZE), - .txeventesize = (FDCAN2_TXEVENTFIFO_WORDS / FDCAN2_TXEVENTFIFO_SIZE), - .txbufferesize = (FDCAN2_TXFIFIOQ_WORDS / FDCAN2_TXFIFIOQ_SIZE), - -#ifdef CONFIG_STM32_FDCAN2_LOOPBACK - .loopback = true, -#endif - - /* FDCAN2 Message RAM */ - - .msgram = - { - (uint32_t *)(STM32_CANRAM2_BASE + (FDCAN2_STDFILTER_INDEX << 2)), - (uint32_t *)(STM32_CANRAM2_BASE + (FDCAN2_EXTFILTERS_INDEX << 2)), - (uint32_t *)(STM32_CANRAM2_BASE + (FDCAN2_RXFIFO0_INDEX << 2)), - (uint32_t *)(STM32_CANRAM2_BASE + (FDCAN2_RXFIFO1_INDEX << 2)), - (uint32_t *)(STM32_CANRAM2_BASE + (FDCAN2_TXEVENTFIFO_INDEX << 2)), - (uint32_t *)(STM32_CANRAM2_BASE + (FDCAN2_TXFIFOQ_INDEX << 2)) - } -}; - -/* FDCAN2 variable driver state */ - -static struct stm32_fdcan_s g_fdcan2priv; -static struct can_dev_s g_fdcan2dev; - -#endif /* CONFIG_STM32_FDCAN2 */ - -#ifdef CONFIG_STM32_FDCAN3 -/* FDCAN3 message RAM allocation */ - -/* FDCAN3 constant configuration */ - -static const struct stm32_config_s g_fdcan3const = -{ - .rxpinset = GPIO_FDCAN3_RX, - .txpinset = GPIO_FDCAN3_TX, - .base = STM32_FDCAN3_BASE, - .baud = CONFIG_STM32_FDCAN3_BITRATE, - .nbtp = FDCAN_NBTP_NBRP(FDCAN3_NBRP) | - FDCAN_NBTP_NTSEG1(FDCAN3_NTSEG1) | - FDCAN_NBTP_NTSEG2(FDCAN3_NTSEG2) | - FDCAN_NBTP_NSJW(FDCAN3_NSJW), - .dbtp = FDCAN_DBTP_DBRP(FDCAN3_DBRP) | - FDCAN_DBTP_DTSEG1(FDCAN3_DTSEG1) | - FDCAN_DBTP_DTSEG2(FDCAN3_DTSEG2) | - FDCAN_DBTP_DSJW(FDCAN3_DSJW), - .port = 3, - .irq0 = STM32_IRQ_FDCAN3_0, - .irq1 = STM32_IRQ_FDCAN3_1, -#if defined(CONFIG_STM32_FDCAN3_CLASSIC) - .mode = FDCAN_CLASSIC_MODE, -#elif defined(CONFIG_STM32_FDCAN3_FD) - .mode = FDCAN_FD_MODE, -#else - .mode = FDCAN_FD_BRS_MODE, -#endif -#if defined(CONFIG_STM32_FDCAN3_NONISO_FORMAT) - .format = FDCAN_NONISO_BOSCH_V1_FORMAT, -#else - .format = FDCAN_ISO11898_1_FORMAT, -#endif - .nstdfilters = FDCAN3_STDFILTER_SIZE, - .nextfilters = FDCAN3_EXTFILTER_SIZE, - .nrxfifo0 = FDCAN3_RXFIFO0_SIZE, - .nrxfifo1 = FDCAN3_RXFIFO1_SIZE, - .ntxeventfifo = FDCAN3_TXEVENTFIFO_SIZE, - .ntxfifoq = FDCAN3_TXFIFIOQ_SIZE, - .rxfifo0esize = (FDCAN3_RXFIFO0_WORDS / FDCAN3_RXFIFO0_SIZE), - .rxfifo1esize = (FDCAN3_RXFIFO1_WORDS / FDCAN3_RXFIFO1_SIZE), - .txeventesize = (FDCAN3_TXEVENTFIFO_WORDS / FDCAN3_TXEVENTFIFO_SIZE), - .txbufferesize = (FDCAN3_TXFIFIOQ_WORDS / FDCAN3_TXFIFIOQ_SIZE), - -#ifdef CONFIG_STM32_FDCAN3_LOOPBACK - .loopback = true, -#endif - - /* FDCAN3 Message RAM */ - - .msgram = - { - (uint32_t *)(STM32_CANRAM3_BASE + (FDCAN3_STDFILTER_INDEX << 2)), - (uint32_t *)(STM32_CANRAM3_BASE + (FDCAN3_EXTFILTERS_INDEX << 2)), - (uint32_t *)(STM32_CANRAM3_BASE + (FDCAN3_RXFIFO0_INDEX << 2)), - (uint32_t *)(STM32_CANRAM3_BASE + (FDCAN3_RXFIFO1_INDEX << 2)), - (uint32_t *)(STM32_CANRAM3_BASE + (FDCAN3_TXEVENTFIFO_INDEX << 2)), - (uint32_t *)(STM32_CANRAM3_BASE + (FDCAN3_TXFIFOQ_INDEX << 2)) - } -}; - -/* FDCAN3 variable driver state */ - -static struct stm32_fdcan_s g_fdcan3priv; -static struct can_dev_s g_fdcan3dev; - -#endif /* CONFIG_STM32_FDCAN3 */ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: fdcan_getreg - * - * Description: - * Read the value of a FDCAN register. - * - * Input Parameters: - * priv - A reference to the FDCAN peripheral state - * offset - The offset to the register to read - * - * Returned Value: - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_FDCAN_REGDEBUG -static uint32_t fdcan_getreg(struct stm32_fdcan_s *priv, int offset) -{ - const struct stm32_config_s *config = priv->config; - uintptr_t regaddr = 0; - uint32_t regval = 0; - - /* Read the value from the register */ - - regaddr = config->base + offset; - regval = getreg32(regaddr); - - /* Is this the same value that we read from the same register last time? - * Are we polling the register? If so, suppress some of the output. - */ - - if (regaddr == priv->regaddr && regval == priv->regval) - { - if (priv->count == 0xffffffff || ++priv->count > 3) - { - if (priv->count == 4) - { - caninfo("...\n"); - } - - return regval; - } - } - - /* No this is a new address or value */ - - else - { - /* Did we print "..." for the previous value? */ - - if (priv->count > 3) - { - /* Yes.. then show how many times the value repeated */ - - caninfo("[repeats %d more times]\n", priv->count - 3); - } - - /* Save the new address, value, and count */ - - priv->regaddr = regaddr; - priv->regval = regval; - priv->count = 1; - } - - /* Show the register value read */ - - caninfo("%08" PRIx32 "->%08" PRIx32 "\n", regaddr, regval); - return regval; -} - -#else -static uint32_t fdcan_getreg(struct stm32_fdcan_s *priv, int offset) -{ - const struct stm32_config_s *config = priv->config; - return getreg32(config->base + offset); -} - -#endif - -/**************************************************************************** - * Name: fdcan_putreg - * - * Description: - * Set the value of a FDCAN register. - * - * Input Parameters: - * priv - A reference to the FDCAN peripheral state - * offset - The offset to the register to write - * regval - The value to write to the register - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_FDCAN_REGDEBUG -static void fdcan_putreg(struct stm32_fdcan_s *priv, int offset, - uint32_t regval) -{ - const struct stm32_config_s *config = priv->config; - uintptr_t regaddr = config->base + offset; - - /* Show the register value being written */ - - caninfo("%08" PRIx32 "->%08" PRIx32 "\n", regaddr, regval); - - /* Write the value */ - - putreg32(regval, regaddr); -} - -#else -static void fdcan_putreg(struct stm32_fdcan_s *priv, int offset, - uint32_t regval) -{ - const struct stm32_config_s *config = priv->config; - putreg32(regval, config->base + offset); -} - -#endif - -/**************************************************************************** - * Name: fdcan_dumpctrlregs - * - * Description: - * Dump the contents of all CAN control registers - * - * Input Parameters: - * priv - A reference to the CAN block status - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_FDCAN_REGDEBUG -static void fdcan_dumpregs(struct stm32_fdcan_s *priv, - const char *msg) -{ - const struct stm32_config_s *config = priv->config; - - caninfo("CAN%d Control and Status Registers: %s\n", config->port, msg); - caninfo(" Base: %08" PRIx32 "\n", config->base); - - /* CAN control and status registers */ - - caninfo(" CCCR: %08" PRIx32 " TEST: %08" PRIx32 "\n", - getreg32(config->base + STM32_FDCAN_CCCR_OFFSET), - getreg32(config->base + STM32_FDCAN_TEST_OFFSET)); - - caninfo(" NBTP: %08" PRIx32 " DBTP: %08" PRIx32 "\n", - getreg32(config->base + STM32_FDCAN_NBTP_OFFSET), - getreg32(config->base + STM32_FDCAN_DBTP_OFFSET)); - - caninfo(" IE: %08" PRIx32 " TIE: %08" PRIx32 "\n", - getreg32(config->base + STM32_FDCAN_IE_OFFSET), - getreg32(config->base + STM32_FDCAN_TXBTIE_OFFSET)); - - caninfo(" ILE: %08" PRIx32 " ILS: %08" PRIx32 "\n", - getreg32(config->base + STM32_FDCAN_ILE_OFFSET), - getreg32(config->base + STM32_FDCAN_ILS_OFFSET)); - - caninfo(" TXBC: %08" PRIx32 "\n", - getreg32(config->base + STM32_FDCAN_TXBC_OFFSET)); -} -#endif - -/**************************************************************************** - * Name: stm32can_dumprxregs - * - * Description: - * Dump the contents of all Rx status registers - * - * Input Parameters: - * priv - A reference to the CAN block status - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_FDCAN_REGDEBUG -static void fdcan_dumprxregs(struct stm32_fdcan_s *priv, - const char *msg) -{ - const struct stm32_config_s *config = priv->config; - - caninfo("CAN%d Rx Registers: %s\n", config->port, msg); - caninfo(" Base: %08" PRIx32 "\n", config->base); - - caninfo(" PSR: %08" PRIx32 " ECR: %08" PRIx32 - " HPMS: %08" PRIx32 "\n", - getreg32(config->base + STM32_FDCAN_PSR_OFFSET), - getreg32(config->base + STM32_FDCAN_ECR_OFFSET), - getreg32(config->base + STM32_FDCAN_HPMS_OFFSET)); - - caninfo(" RXF0S: %08" PRIx32 " RXF0A: %08" PRIx32 "\n", - getreg32(config->base + STM32_FDCAN_RXF0S_OFFSET), - getreg32(config->base + STM32_FDCAN_RXF0A_OFFSET)); - - caninfo(" RXF1S: %08" PRIx32 " RXF1A: %08" PRIx32 "\n", - getreg32(config->base + STM32_FDCAN_RXF1S_OFFSET), - getreg32(config->base + STM32_FDCAN_RXF1A_OFFSET)); - - caninfo(" IR: %08" PRIx32 " IE: %08" PRIx32 "\n", - getreg32(config->base + STM32_FDCAN_IR_OFFSET), - getreg32(config->base + STM32_FDCAN_IE_OFFSET)); -} -#endif - -/**************************************************************************** - * Name: stm32can_dumptxregs - * - * Description: - * Dump the contents of all Tx buffer registers - * - * Input Parameters: - * priv - A reference to the CAN block status - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_FDCAN_REGDEBUG -static void fdcan_dumptxregs(struct stm32_fdcan_s *priv, - const char *msg) -{ - const struct stm32_config_s *config = priv->config; - - caninfo("CAN%d Tx Registers: %s\n", config->port, msg); - caninfo(" Base: %08" PRIx32 "\n", config->base); - - caninfo(" PSR: %08" PRIx32 " ECR: %08" PRIx32 "\n", - getreg32(config->base + STM32_FDCAN_PSR_OFFSET), - getreg32(config->base + STM32_FDCAN_ECR_OFFSET)); - - caninfo(" TXQFS: %08" PRIx32 " TXBAR: %08" PRIx32 - " TXBRP: %08" PRIx32 "\n", - getreg32(config->base + STM32_FDCAN_TXFQS_OFFSET), - getreg32(config->base + STM32_FDCAN_TXBAR_OFFSET), - getreg32(config->base + STM32_FDCAN_TXBRP_OFFSET)); - - caninfo(" TXBTO: %08" PRIx32 " TXBCR: %08" PRIx32 "\n", - getreg32(config->base + STM32_FDCAN_TXBTO_OFFSET), - getreg32(config->base + STM32_FDCAN_TXBCR_OFFSET)); - - caninfo(" TXEFS: %08" PRIx32 " TXEFA: %08" PRIx32 "\n", - getreg32(config->base + STM32_FDCAN_TXEFS_OFFSET), - getreg32(config->base + STM32_FDCAN_TXEFA_OFFSET)); - - caninfo(" IR: %08" PRIx32 " IE: %08" PRIx32 - " TIE: %08" PRIx32 "\n", - getreg32(config->base + STM32_FDCAN_IR_OFFSET), - getreg32(config->base + STM32_FDCAN_IE_OFFSET), - getreg32(config->base + STM32_FDCAN_TXBTIE_OFFSET)); -} -#endif - -/**************************************************************************** - * Name: stm32can_dumpramlayout - * - * Description: - * Print the layout of the message RAM - * - * Input Parameters: - * priv - A reference to the CAN block status - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_FDCAN_REGDEBUG -static void fdcan_dumpramlayout(struct stm32_fdcan_s *priv) -{ - const struct stm32_config_s *config = priv->config; - - caninfo(" ******* FDCAN%d Message RAM layout *******\n", config->port); - caninfo(" Start # Elmnt Elmnt size (words)\n"); - - if (config->nstdfilters > 0) - { - caninfo("STD filters %p %4d %2d\n", - config->msgram.stdfilters, - config->nstdfilters, - 1); - } - - if (config->nextfilters > 0) - { - caninfo("EXT filters %p %4d %2d\n", - config->msgram.extfilters, - config->nextfilters, - 2); - } - - if (config->nrxfifo0 > 0) - { - caninfo("RX FIFO 0 %p %4d %2d\n", - config->msgram.rxfifo0, - config->nrxfifo0, - config->rxfifo0esize); - } - - if (config->nrxfifo1 > 0) - { - caninfo("RX FIFO 1 %p %4d %2d\n", - config->msgram.rxfifo1, - config->nrxfifo1, - config->rxfifo1esize); - } - - if (config->ntxeventfifo > 0) - { - caninfo("TX EVENT %p %4d %2d\n", - config->msgram.txeventfifo, - config->ntxeventfifo, - config->txeventesize); - } - - if (config->ntxfifoq > 0) - { - caninfo("TX FIFO %p %4d %2d\n", - config->msgram.txfifoq, - config->ntxfifoq, - config->txbufferesize); - } -} -#endif - -/**************************************************************************** - * Name: fdcan_dlc2bytes - * - * Description: - * In the CAN FD format, the coding of the DLC differs from the standard - * CAN format. The DLC codes 0 to 8 have the same coding as in standard - * CAN. But the codes 9 to 15 all imply a data field of 8 bytes with - * standard CAN. In CAN FD mode, the values 9 to 15 are encoded to values - * in the range 12 to 64. - * - * Input Parameters: - * dlc - the DLC value to convert to a byte count - * - * Returned Value: - * The number of bytes corresponding to the DLC value. - * - ****************************************************************************/ - -static uint8_t fdcan_dlc2bytes(struct stm32_fdcan_s *priv, uint8_t dlc) -{ - if (dlc > 8) - { -#ifdef CONFIG_CAN_FD - if (priv->config->mode == FDCAN_CLASSIC_MODE) - { - return 8; - } - else - { - switch (dlc) - { - case 9: - return 12; - case 10: - return 16; - case 11: - return 20; - case 12: - return 24; - case 13: - return 32; - case 14: - return 48; - default: - case 15: - return 64; - } - } -#else - return 8; -#endif - } - - return dlc; -} - -/**************************************************************************** - * Name: fdcan_add_extfilter - * - * Description: - * Add an address filter for a extended 29 bit address. - * - * Input Parameters: - * priv - An instance of the FDCAN driver state structure. - * extconfig - The configuration of the extended filter - * - * Returned Value: - * A non-negative filter ID is returned on success. Otherwise a negated - * errno value is returned to indicate the nature of the error. - * - ****************************************************************************/ - -#ifdef CONFIG_CAN_EXTID -static int fdcan_add_extfilter(struct stm32_fdcan_s *priv, - struct canioc_extfilter_s *extconfig) -{ - const struct stm32_config_s *config = NULL; - volatile uint32_t *extfilter = NULL; - uint32_t regval = 0; - int word = 0; - int bit = 0; - int ndx = 0; - - DEBUGASSERT(priv != NULL && priv->config != NULL && extconfig != NULL); - config = priv->config; - - /* Find an unused standard filter */ - - for (ndx = 0; ndx < config->nextfilters; ndx++) - { - /* Is this filter assigned? */ - - word = ndx >> 5; - bit = ndx & 0x1f; - - if ((priv->extfilters[word] & (1 << bit)) == 0) - { - /* No, assign the filter */ - - DEBUGASSERT(priv->nextalloc < priv->config->nstdfilters); - priv->extfilters[word] |= (1 << bit); - priv->nextalloc++; - - extfilter = config->msgram.extfilters + (ndx << 1); - - /* Format and write filter word F0 */ - - DEBUGASSERT(extconfig->xf_id1 <= CAN_MAX_EXTMSGID); - regval = EXTFILTER_F0_EFID1(extconfig->xf_id1); - - if (extconfig->xf_prio == 0) - { - regval |= EXTFILTER_F0_EFEC_FIFO0; - } - else - { - regval |= EXTFILTER_F0_EFEC_FIFO1; - } - - extfilter[0] = regval; - - /* Format and write filter word F1 */ - - DEBUGASSERT(extconfig->xf_id2 <= CAN_MAX_EXTMSGID); - regval = EXTFILTER_F1_EFID2(extconfig->xf_id2); - - switch (extconfig->xf_type) - { - case CAN_FILTER_DUAL: - { - regval |= EXTFILTER_F1_EFT_DUAL; - break; - } - - case CAN_FILTER_MASK: - { - regval |= EXTFILTER_F1_EFT_CLASSIC; - break; - } - - case CAN_FILTER_RANGE: - { - regval |= EXTFILTER_F1_EFT_RANGE; - break; - } - - default: - { - return -EINVAL; - } - } - - extfilter[1] = regval; - - /* Is this the first extended filter? */ - - if (priv->nextalloc == 1) - { - /* Enable the Initialization state */ - - regval = fdcan_getreg(priv, STM32_FDCAN_CCCR_OFFSET); - regval |= FDCAN_CCCR_INIT; - fdcan_putreg(priv, STM32_FDCAN_CCCR_OFFSET, regval); - - /* Wait for initialization mode to take effect */ - - while ((fdcan_getreg(priv, STM32_FDCAN_CCCR_OFFSET) & - FDCAN_CCCR_INIT) == 0); - - /* Enable writing to configuration registers */ - - regval = fdcan_getreg(priv, STM32_FDCAN_CCCR_OFFSET); - regval |= (FDCAN_CCCR_INIT | FDCAN_CCCR_CCE); - fdcan_putreg(priv, STM32_FDCAN_CCCR_OFFSET, regval); - - /* Update the Global Filter Configuration so that received - * messages are rejected if they do not match the acceptance - * filter. - * - * ANFE=2: Discard all rejected frames - */ - - regval = fdcan_getreg(priv, STM32_FDCAN_RXGFC_OFFSET); - regval &= ~FDCAN_RXGFC_ANFE_MASK; - regval |= FDCAN_RXGFC_ANFE_REJECTED; - fdcan_putreg(priv, STM32_FDCAN_RXGFC_OFFSET, regval); - - /* Disable writing to configuration registers */ - - regval = fdcan_getreg(priv, STM32_FDCAN_CCCR_OFFSET); - regval &= ~(FDCAN_CCCR_INIT | FDCAN_CCCR_CCE); - fdcan_putreg(priv, STM32_FDCAN_CCCR_OFFSET, regval); - } - - return ndx; - } - } - - DEBUGASSERT(priv->nextalloc == priv->config->nextfilters); - - return -EAGAIN; -} -#endif - -/**************************************************************************** - * Name: fdcan_del_extfilter - * - * Description: - * Remove an address filter for a standard 29 bit address. - * - * Input Parameters: - * priv - An instance of the FDCAN driver state structure. - * ndx - The filter index previously returned by the - * fdcan_add_extfilter(). - * - * Returned Value: - * Zero (OK) is returned on success. Otherwise a negated errno value is - * returned to indicate the nature of the error. - * - ****************************************************************************/ - -#ifdef CONFIG_CAN_EXTID -static int fdcan_del_extfilter(struct stm32_fdcan_s *priv, int ndx) -{ - const struct stm32_config_s *config = NULL; - volatile uint32_t *extfilter = NULL; - uint32_t regval = 0; - int word = 0; - int bit = 0; - - DEBUGASSERT(priv != NULL && priv->config != NULL); - config = priv->config; - - /* Check user Parameters */ - - DEBUGASSERT(ndx >= 0 || ndx < config->nextfilters); - - if (ndx < 0 || ndx >= config->nextfilters) - { - return -EINVAL; - } - - word = ndx >> 5; - bit = ndx & 0x1f; - - /* Check if this filter is really assigned */ - - if ((priv->extfilters[word] & (1 << bit)) == 0) - { - /* No, error out */ - - return -ENOENT; - } - - /* Release the filter */ - - priv->extfilters[word] &= ~(1 << bit); - - DEBUGASSERT(priv->nextalloc > 0); - priv->nextalloc--; - - /* Was that the last extended filter? */ - - if (priv->nextalloc == 0) - { - /* Enable the Initialization state */ - - regval = fdcan_getreg(priv, STM32_FDCAN_CCCR_OFFSET); - regval |= FDCAN_CCCR_INIT; - fdcan_putreg(priv, STM32_FDCAN_CCCR_OFFSET, regval); - - /* Wait for initialization mode to take effect */ - - while ((fdcan_getreg(priv, STM32_FDCAN_CCCR_OFFSET) & - FDCAN_CCCR_INIT) == 0); - - /* Enable writing to configuration registers */ - - regval = fdcan_getreg(priv, STM32_FDCAN_CCCR_OFFSET); - regval |= (FDCAN_CCCR_INIT | FDCAN_CCCR_CCE); - fdcan_putreg(priv, STM32_FDCAN_CCCR_OFFSET, regval); - - /* If there are no extended filters, then modify Global Filter - * Configuration so that all rejected messages are places in RX - * FIFO0. - * - * ANFE=0: Store all rejected extended frame in RX FIFO0 - */ - - regval = fdcan_getreg(priv, STM32_FDCAN_RXGFC_OFFSET); - regval &= ~FDCAN_RXGFC_ANFE_MASK; - regval |= FDCAN_RXGFC_ANFE_RX_FIFO0; - fdcan_putreg(priv, STM32_FDCAN_RXGFC_OFFSET, regval); - - /* Disable writing to configuration registers */ - - regval = fdcan_getreg(priv, STM32_FDCAN_CCCR_OFFSET); - regval &= ~(FDCAN_CCCR_INIT | FDCAN_CCCR_CCE); - fdcan_putreg(priv, STM32_FDCAN_CCCR_OFFSET, regval); - } - - /* Deactivate the filter last so that no messages are lost. */ - - extfilter = config->msgram.extfilters + (ndx << 1); - *extfilter++ = 0; - *extfilter = 0; - - return OK; -} -#endif - -/**************************************************************************** - * Name: fdcan_add_stdfilter - * - * Description: - * Add an address filter for a standard 11 bit address. - * - * Input Parameters: - * priv - An instance of the FDCAN driver state structure. - * stdconfig - The configuration of the standard filter - * - * Returned Value: - * A non-negative filter ID is returned on success. Otherwise a negated - * errno value is returned to indicate the nature of the error. - * - ****************************************************************************/ - -static int fdcan_add_stdfilter(struct stm32_fdcan_s *priv, - struct canioc_stdfilter_s *stdconfig) -{ - const struct stm32_config_s *config = NULL; - volatile uint32_t *stdfilter = NULL; - uint32_t regval = 0; - int word = 0; - int bit = 0; - int ndx = 0; - - DEBUGASSERT(priv != NULL && priv->config != NULL); - config = priv->config; - - /* Find an unused standard filter */ - - for (ndx = 0; ndx < config->nstdfilters; ndx++) - { - /* Is this filter assigned? */ - - word = ndx >> 5; - bit = ndx & 0x1f; - - if ((priv->stdfilters[word] & (1 << bit)) == 0) - { - /* No, assign the filter */ - - DEBUGASSERT(priv->nstdalloc < priv->config->nstdfilters); - priv->stdfilters[word] |= (1 << bit); - priv->nstdalloc++; - - /* Format and write filter word S0 */ - - stdfilter = config->msgram.stdfilters + ndx; - - DEBUGASSERT(stdconfig->sf_id1 <= CAN_MAX_STDMSGID); - regval = STDFILTER_S0_SFID1(stdconfig->sf_id1); - - DEBUGASSERT(stdconfig->sf_id2 <= CAN_MAX_STDMSGID); - regval |= STDFILTER_S0_SFID2(stdconfig->sf_id2); - - if (stdconfig->sf_prio == 0) - { - regval |= STDFILTER_S0_SFEC_FIFO0; - } - else - { - regval |= STDFILTER_S0_SFEC_FIFO1; - } - - switch (stdconfig->sf_type) - { - case CAN_FILTER_DUAL: - { - regval |= STDFILTER_S0_SFT_DUAL; - break; - } - - case CAN_FILTER_MASK: - { - regval |= STDFILTER_S0_SFT_CLASSIC; - break; - } - - case CAN_FILTER_RANGE: - { - regval |= STDFILTER_S0_SFT_RANGE; - break; - } - - default: - { - return -EINVAL; - } - } - - *stdfilter = regval; - - /* Is this the first standard filter? */ - - if (priv->nstdalloc == 1) - { - /* Enable the Initialization state */ - - regval = fdcan_getreg(priv, STM32_FDCAN_CCCR_OFFSET); - regval |= FDCAN_CCCR_INIT; - fdcan_putreg(priv, STM32_FDCAN_CCCR_OFFSET, regval); - - /* Wait for initialization mode to take effect */ - - while ((fdcan_getreg(priv, STM32_FDCAN_CCCR_OFFSET) & - FDCAN_CCCR_INIT) == 0); - - /* Enable writing to configuration registers */ - - regval = fdcan_getreg(priv, STM32_FDCAN_CCCR_OFFSET); - regval |= (FDCAN_CCCR_INIT | FDCAN_CCCR_CCE); - fdcan_putreg(priv, STM32_FDCAN_CCCR_OFFSET, regval); - - /* Update the Global Filter Configuration so that received - * messages are rejected if they do not match the acceptance - * filter. - * - * ANFS=2: Discard all rejected frames - */ - - regval = fdcan_getreg(priv, STM32_FDCAN_RXGFC_OFFSET); - regval &= ~FDCAN_RXGFC_ANFS_MASK; - regval |= FDCAN_RXGFC_ANFS_REJECTED; - fdcan_putreg(priv, STM32_FDCAN_RXGFC_OFFSET, regval); - - /* Disable writing to configuration registers */ - - regval = fdcan_getreg(priv, STM32_FDCAN_CCCR_OFFSET); - regval &= ~(FDCAN_CCCR_INIT | FDCAN_CCCR_CCE); - fdcan_putreg(priv, STM32_FDCAN_CCCR_OFFSET, regval); - } - - return ndx; - } - } - - DEBUGASSERT(priv->nstdalloc == priv->config->nstdfilters); - return -EAGAIN; -} - -/**************************************************************************** - * Name: fdcan_del_stdfilter - * - * Description: - * Remove an address filter for a standard 29 bit address. - * - * Input Parameters: - * priv - An instance of the FDCAN driver state structure. - * ndx - The filter index previously returned by the - * fdcan_add_stdfilter(). - * - * Returned Value: - * Zero (OK) is returned on success. Otherwise a negated errno value is - * returned to indicate the nature of the error. - * - ****************************************************************************/ - -static int fdcan_del_stdfilter(struct stm32_fdcan_s *priv, int ndx) -{ - const struct stm32_config_s *config = NULL; - volatile uint32_t *stdfilter = NULL; - uint32_t regval = 0; - int word = 0; - int bit = 0; - - DEBUGASSERT(priv != NULL && priv->config != NULL); - config = priv->config; - - /* Check Userspace Parameters */ - - DEBUGASSERT(ndx >= 0 || ndx < config->nstdfilters); - - if (ndx < 0 || ndx >= config->nstdfilters) - { - return -EINVAL; - } - - word = ndx >> 5; - bit = ndx & 0x1f; - - /* Check if this filter is really assigned */ - - if ((priv->stdfilters[word] & (1 << bit)) == 0) - { - /* No, error out */ - - return -ENOENT; - } - - /* Release the filter */ - - priv->stdfilters[word] &= ~(1 << bit); - - DEBUGASSERT(priv->nstdalloc > 0); - priv->nstdalloc--; - - /* Was that the last standard filter? */ - - if (priv->nstdalloc == 0) - { - /* Enable the Initialization state */ - - regval = fdcan_getreg(priv, STM32_FDCAN_CCCR_OFFSET); - regval |= FDCAN_CCCR_INIT; - fdcan_putreg(priv, STM32_FDCAN_CCCR_OFFSET, regval); - - /* Wait for initialization mode to take effect */ - - while ((fdcan_getreg(priv, STM32_FDCAN_CCCR_OFFSET) & - FDCAN_CCCR_INIT) == 0); - - /* Enable writing to configuration registers */ - - regval = fdcan_getreg(priv, STM32_FDCAN_CCCR_OFFSET); - regval |= (FDCAN_CCCR_INIT | FDCAN_CCCR_CCE); - fdcan_putreg(priv, STM32_FDCAN_CCCR_OFFSET, regval); - - /* If there are no standard filters, then modify Global Filter - * Configuration so that all rejected messages are places in RX - * FIFO0. - * - * ANFS=0: Store all rejected extended frame in RX FIFO0 - */ - - regval = fdcan_getreg(priv, STM32_FDCAN_RXGFC_OFFSET); - regval &= ~FDCAN_RXGFC_ANFS_MASK; - regval |= FDCAN_RXGFC_ANFS_RX_FIFO0; - fdcan_putreg(priv, STM32_FDCAN_RXGFC_OFFSET, regval); - - /* Disable writing to configuration registers */ - - regval = fdcan_getreg(priv, STM32_FDCAN_CCCR_OFFSET); - regval &= ~(FDCAN_CCCR_INIT | FDCAN_CCCR_CCE); - fdcan_putreg(priv, STM32_FDCAN_CCCR_OFFSET, regval); - } - - /* Deactivate the filter last so that no messages are lost. */ - - stdfilter = config->msgram.stdfilters + ndx; - *stdfilter = 0; - - return OK; -} - -/**************************************************************************** - * Name: fdcan_start_busoff_recovery_sequence - * - * Description: - * This function initiates the BUS-OFF recovery sequence. - * CAN Specification Rev. 2.0 or ISO11898-1:2015. - * According the STM32G4 datasheet section 44.3.2 Software initialziation. - * - * Input Parameters: - * priv - An instance of the FDCAN driver state structure. - * - * Returned Value: - * Zero (OK) is returned on success. Otherwise a negated errno value is - * returned to indicate the nature of the error. - * - ****************************************************************************/ - -static int -fdcan_start_busoff_recovery_sequence(struct stm32_fdcan_s *priv) -{ - uint32_t regval = 0; - - DEBUGASSERT(priv); - - /* Only start BUS-OFF recovery if we are in BUS-OFF state */ - - regval = fdcan_getreg(priv, STM32_FDCAN_PSR_OFFSET); - if ((regval & FDCAN_PSR_BO) == 0) - { - return -EPERM; - } - - /* Disable initialization mode to issue the recovery sequence */ - - regval = fdcan_getreg(priv, STM32_FDCAN_CCCR_OFFSET); - regval &= ~FDCAN_CCCR_INIT; - fdcan_putreg(priv, STM32_FDCAN_CCCR_OFFSET, regval); - - return OK; -} - -/**************************************************************************** - * Name: fdcan_reset - * - * Description: - * Reset the FDCAN device. Called early to initialize the hardware. This - * function is called, before fdcan_setup() and on error conditions. - * - * Input Parameters: - * dev - An instance of the "upper half" can driver state structure. - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void fdcan_reset(struct can_dev_s *dev) -{ - struct stm32_fdcan_s *priv = NULL; - const struct stm32_config_s *config = NULL; - uint32_t regval = 0; - irqstate_t flags; - - DEBUGASSERT(dev); - priv = dev->cd_priv; - DEBUGASSERT(priv); - config = priv->config; - DEBUGASSERT(config); - - caninfo("FDCAN%d\n", config->port); - UNUSED(config); - - /* Disable all interrupts */ - - fdcan_putreg(priv, STM32_FDCAN_IE_OFFSET, 0); - fdcan_putreg(priv, STM32_FDCAN_TXBTIE_OFFSET, 0); - - /* Make sure that all buffers are released. - * - * REVISIT: What if a thread is waiting for a buffer? The following - * will not wake up any waiting threads. - */ - - /* Disable the FDCAN controller. - * REVISIT: Should fdcan_shutdown() be called here? - */ - - /* Reset the FD CAN. - * REVISIT: Since there is only a single reset for both FDCAN - * controllers, do we really want to use the RCC reset here? - * This will nuke operation of the second controller if another - * device is registered. - */ - - flags = enter_critical_section(); - regval = getreg32(STM32_RCC_APB1RSTR1); - regval |= RCC_APB1RSTR1_FDCANRST; - putreg32(regval, STM32_RCC_APB1RSTR1); - - regval &= ~RCC_APB1RSTR1_FDCANRST; - putreg32(regval, STM32_RCC_APB1RSTR1); - leave_critical_section(flags); - - priv->state = FDCAN_STATE_RESET; -} - -/**************************************************************************** - * Name: fdcan_setup - * - * Description: - * Configure the FDCAN. This method is called the first time that the FDCAN - * device is opened. This will occur when the port is first opened. - * This setup includes configuring and attaching FDCAN interrupts. - * All FDCAN interrupts are disabled upon return. - * - * Input Parameters: - * dev - An instance of the "upper half" can driver state structure. - * - * Returned Value: - * Zero on success; a negated errno on failure - * - ****************************************************************************/ - -static int fdcan_setup(struct can_dev_s *dev) -{ - struct stm32_fdcan_s *priv = NULL; - const struct stm32_config_s *config = NULL; - int ret = 0; - - DEBUGASSERT(dev); - priv = dev->cd_priv; - DEBUGASSERT(priv); - config = priv->config; - DEBUGASSERT(config); - - caninfo("FDCAN%d\n", config->port); - - /* FDCAN hardware initialization */ - - ret = fdcan_hw_initialize(priv); - if (ret < 0) - { - canerr("ERROR: FDCAN%d H/W initialization failed: %d\n", - config->port, ret); - return ret; - } - - fdcan_dumpregs(priv, "After hardware initialization"); - - /* Attach the FDCAN interrupt handlers */ - - ret = irq_attach(config->irq0, fdcan_interrupt, dev); - if (ret < 0) - { - canerr("ERROR: Failed to attach FDCAN%d line 0 IRQ (%d)", - config->port, config->irq0); - return ret; - } - - ret = irq_attach(config->irq1, fdcan_interrupt, dev); - if (ret < 0) - { - canerr("ERROR: Failed to attach FDCAN%d line 1 IRQ (%d)", - config->port, config->irq1); - return ret; - } - - priv->state = FDCAN_STATE_SETUP; - - /* Enable the interrupts at the NVIC (they are still disabled at the FDCAN - * peripheral). - */ - - up_enable_irq(config->irq0); - up_enable_irq(config->irq1); - - return OK; -} - -/**************************************************************************** - * Name: fdcan_shutdown - * - * Description: - * Disable the FDCAN. This method is called when the FDCAN device - * is closed. This method reverses the operation the setup method. - * - * Input Parameters: - * dev - An instance of the "upper half" can driver state structure. - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void fdcan_shutdown(struct can_dev_s *dev) -{ - struct stm32_fdcan_s *priv = NULL; - const struct stm32_config_s *config = NULL; - uint32_t regval = 0; - - DEBUGASSERT(dev); - priv = dev->cd_priv; - DEBUGASSERT(priv); - config = priv->config; - DEBUGASSERT(config); - - caninfo("FDCAN%d\n", config->port); - - /* Disable FDCAN interrupts at the NVIC */ - - up_disable_irq(config->irq0); - up_disable_irq(config->irq1); - - /* Disable all interrupts from the FDCAN peripheral */ - - fdcan_putreg(priv, STM32_FDCAN_IE_OFFSET, 0); - fdcan_putreg(priv, STM32_FDCAN_TXBTIE_OFFSET, 0); - - /* Detach the FDCAN interrupt handler */ - - irq_detach(config->irq0); - irq_detach(config->irq1); - - /* Disable device by setting the Clock Stop Request bit */ - - regval = fdcan_getreg(priv, STM32_FDCAN_CCCR_OFFSET); - regval |= FDCAN_CCCR_CSR; - fdcan_putreg(priv, STM32_FDCAN_CCCR_OFFSET, regval); - - /* Wait for Init and Clock Stop Acknowledge bits to verify - * device is in the powered down state - */ - - while ((fdcan_getreg(priv, STM32_FDCAN_CCCR_OFFSET) & FDCAN_CCCR_INIT) - == 0); - while ((fdcan_getreg(priv, STM32_FDCAN_CCCR_OFFSET) & FDCAN_CCCR_CSA) - == 0); - priv->state = FDCAN_STATE_DISABLED; -} - -/**************************************************************************** - * Name: fdcan_rxint - * - * Description: - * Call to enable or disable RX interrupts. - * - * Input Parameters: - * dev - An instance of the "upper half" can driver state structure. - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void fdcan_rxint(struct can_dev_s *dev, bool enable) -{ - struct stm32_fdcan_s *priv = dev->cd_priv; - uint32_t regval = 0; - - DEBUGASSERT(priv && priv->config); - - caninfo("FDCAN%d enable: %d\n", priv->config->port, enable); - - /* Enable/disable the receive interrupts */ - - regval = fdcan_getreg(priv, STM32_FDCAN_IE_OFFSET); - - if (enable) - { - regval |= priv->rxints | FDCAN_COMMON_INTS; - } - else - { - regval &= ~priv->rxints; - } - - fdcan_putreg(priv, STM32_FDCAN_IE_OFFSET, regval); -} - -/**************************************************************************** - * Name: fdcan_txint - * - * Description: - * Call to enable or disable TX interrupts. - * - * Input Parameters: - * dev - An instance of the "upper half" can driver state structure. - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void fdcan_txint(struct can_dev_s *dev, bool enable) -{ - struct stm32_fdcan_s *priv = dev->cd_priv; - uint32_t regval = 0; - - DEBUGASSERT(priv && priv->config); - - caninfo("FDCAN%d enable: %d\n", priv->config->port, enable); - - /* Enable/disable the receive interrupts */ - - regval = fdcan_getreg(priv, STM32_FDCAN_IE_OFFSET); - - if (enable) - { - regval |= priv->txints | FDCAN_COMMON_INTS; - } - else - { - regval &= ~priv->txints; - } - - fdcan_putreg(priv, STM32_FDCAN_IE_OFFSET, regval); -} - -/**************************************************************************** - * Name: fdcan_ioctl - * - * Description: - * All ioctl calls will be routed through this method - * - * Input Parameters: - * dev - An instance of the "upper half" can driver state structure. - * - * Returned Value: - * Zero on success; a negated errno on failure - * - ****************************************************************************/ - -static int fdcan_ioctl(struct can_dev_s *dev, int cmd, unsigned long arg) -{ - struct stm32_fdcan_s *priv = NULL; - int ret = -ENOTTY; - - caninfo("cmd=%04x arg=%lu\n", cmd, arg); - - DEBUGASSERT(dev && dev->cd_priv); - priv = dev->cd_priv; - - /* Handle the command */ - - switch (cmd) - { - /* CANIOC_GET_BITTIMING: - * Description: Return the current bit timing settings - * Argument: A pointer to a write-able instance of struct - * canioc_bittiming_s in which current bit timing - * values will be returned. - * Returned Value: Zero (OK) is returned on success. Otherwise -1 - * (ERROR) is returned with the errno variable set - * to indicate the nature of the error. - * Dependencies: None - */ - - case CANIOC_GET_BITTIMING: - { - struct canioc_bittiming_s *bt = - (struct canioc_bittiming_s *)arg; - uint32_t regval; - uint32_t nbrp; - - DEBUGASSERT(bt != NULL); - -#ifdef CONFIG_CAN_FD - if (bt->type == CAN_BITTIMING_DATA) - { - regval = fdcan_getreg(priv, STM32_FDCAN_DBTP_OFFSET); - bt->bt_sjw = ((regval & FDCAN_DBTP_DSJW_MASK) >> - FDCAN_DBTP_DSJW_SHIFT) + 1; - bt->bt_tseg1 = ((regval & FDCAN_DBTP_DTSEG1_MASK) >> - FDCAN_DBTP_DTSEG1_SHIFT) + 1; - bt->bt_tseg2 = ((regval & FDCAN_DBTP_DTSEG2_MASK) >> - FDCAN_DBTP_DTSEG2_SHIFT) + 1; - - nbrp = ((regval & FDCAN_DBTP_DBRP_MASK) >> - FDCAN_DBTP_DBRP_SHIFT) + 1; - bt->bt_baud = STM32_FDCANCLK_FREQUENCY / nbrp / - (bt->bt_tseg1 + bt->bt_tseg2 + 1); - } - else -#endif - { - regval = fdcan_getreg(priv, STM32_FDCAN_NBTP_OFFSET); - bt->bt_sjw = ((regval & FDCAN_NBTP_NSJW_MASK) >> - FDCAN_NBTP_NSJW_SHIFT) + 1; - bt->bt_tseg1 = ((regval & FDCAN_NBTP_NTSEG1_MASK) >> - FDCAN_NBTP_NTSEG1_SHIFT) + 1; - bt->bt_tseg2 = ((regval & FDCAN_NBTP_NTSEG2_MASK) >> - FDCAN_NBTP_NTSEG2_SHIFT) + 1; - - nbrp = ((regval & FDCAN_NBTP_NBRP_MASK) >> - FDCAN_NBTP_NBRP_SHIFT) + 1; - bt->bt_baud = STM32_FDCANCLK_FREQUENCY / nbrp / - (bt->bt_tseg1 + bt->bt_tseg2 + 1); - } - - ret = OK; - } - break; - - /* CANIOC_SET_BITTIMING: - * Description: Set new current bit timing values - * Argument: A pointer to a read-able instance of struct - * canioc_bittiming_s in which the new bit timing - * values are provided. - * Returned Value: Zero (OK) is returned on success. Otherwise -1 - * (ERROR) is returned with the errno variable set - * to indicate the nature of the error. - * Dependencies: None - * - * REVISIT: There is probably a limitation here: If there are - * multiple threads trying to send CAN packets, when one of these - * threads reconfigures the bitrate, the FDCAN hardware will be reset - * and the context of operation will be lost. Hence, this IOCTL can - * only safely be executed in quiescent time periods. - */ - - case CANIOC_SET_BITTIMING: - { - const struct canioc_bittiming_s *bt = - (const struct canioc_bittiming_s *)arg; - uint32_t nbrp; - uint32_t ntseg1; - uint32_t ntseg2; - uint32_t nsjw; - uint32_t ie; - uint8_t state; - - DEBUGASSERT(bt != NULL); - DEBUGASSERT(bt->bt_baud < STM32_FDCANCLK_FREQUENCY); - DEBUGASSERT(bt->bt_sjw > 0 && bt->bt_sjw <= 16); - DEBUGASSERT(bt->bt_tseg1 > 1 && bt->bt_tseg1 <= 64); - DEBUGASSERT(bt->bt_tseg2 > 0 && bt->bt_tseg2 <= 16); - - /* Extract bit timing data */ - - ntseg1 = bt->bt_tseg1 - 1; - ntseg2 = bt->bt_tseg2 - 1; - nsjw = bt->bt_sjw - 1; - - nbrp = (uint32_t) - (((float) STM32_FDCANCLK_FREQUENCY / - ((float)(ntseg1 + ntseg2 + 3) * (float)bt->bt_baud)) - 1); - - /* Save the value of the new bit timing register */ - -#ifdef CONFIG_CAN_FD - if (bt->type == CAN_BITTIMING_DATA) - { - priv->dbtp = FDCAN_NBTP_DBRP(nbrp) | - FDCAN_NBTP_DTSEG1(ntseg1) | - FDCAN_DBTP_DTSEG2(ntseg2) | - FDCAN_DBTP_DSJW(nsjw); - } - else -#endif - { - priv->nbtp = FDCAN_NBTP_NBRP(nbrp) | - FDCAN_NBTP_NTSEG1(ntseg1) | - FDCAN_NBTP_NTSEG2(ntseg2) | - FDCAN_NBTP_NSJW(nsjw); - } - - /* We need to reset to instantiate the new timing. Save - * current state information so that recover to this - * state. - */ - - ie = fdcan_getreg(priv, STM32_FDCAN_IE_OFFSET); - state = priv->state; - - /* Reset the FDCAN */ - - fdcan_reset(dev); - ret = OK; - - /* If we have previously been setup, then setup again */ - - if (state == FDCAN_STATE_SETUP) - { - ret = fdcan_setup(dev); - } - - /* We we have successfully re-initialized, then restore the - * interrupt state. - * - * REVISIT: Since the hardware was reset, any pending TX - * activity was lost. Should we disable TX interrupts? - */ - - if (ret == OK) - { - fdcan_putreg(priv, STM32_FDCAN_IE_OFFSET, ie & ~priv->txints); - } - } - break; - -#ifdef CONFIG_CAN_EXTID - /* CANIOC_ADD_EXTFILTER: - * Description: Add an address filter for a extended 29 bit - * address. - * Argument: A reference to struct canioc_extfilter_s - * Returned Value: A non-negative filter ID is returned on success. - * Otherwise -1 (ERROR) is returned with the errno - * variable set to indicate the nature of the error. - */ - - case CANIOC_ADD_EXTFILTER: - { - DEBUGASSERT(arg != 0); - - ret = fdcan_add_extfilter(priv, - (struct canioc_extfilter_s *)arg); - } - break; - - /* CANIOC_DEL_EXTFILTER: - * Description: Remove an address filter for a standard 29 bit - * address. - * Argument: The filter index previously returned by the - * CANIOC_ADD_EXTFILTER command - * Returned Value: Zero (OK) is returned on success. Otherwise -1 - * (ERROR) is returned with the errno variable set - * to indicate the nature of the error. - */ - - case CANIOC_DEL_EXTFILTER: - { - DEBUGASSERT(arg <= priv->config->nextfilters); - ret = fdcan_del_extfilter(priv, (int)arg); - } - break; -#endif - - /* CANIOC_ADD_STDFILTER: - * Description: Add an address filter for a standard 11 bit - * address. - * Argument: A reference to struct canioc_stdfilter_s - * Returned Value: A non-negative filter ID is returned on success. - * Otherwise -1 (ERROR) is returned with the errno - * variable set to indicate the nature of the error. - */ - - case CANIOC_ADD_STDFILTER: - { - DEBUGASSERT(arg != 0); - - ret = fdcan_add_stdfilter(priv, - (struct canioc_stdfilter_s *)arg); - } - break; - - /* CANIOC_DEL_STDFILTER: - * Description: Remove an address filter for a standard 11 bit - * address. - * Argument: The filter index previously returned by the - * CANIOC_ADD_STDFILTER command - * Returned Value: Zero (OK) is returned on success. Otherwise -1 - * (ERROR) is returned with the errno variable set - * to indicate the nature of the error. - */ - - case CANIOC_DEL_STDFILTER: - { - DEBUGASSERT(arg <= priv->config->nstdfilters); - ret = fdcan_del_stdfilter(priv, (int)arg); - } - break; - - /* CANIOC_BUSOFF_RECOVERY: - * Description : Initiates the BUS - OFF recovery sequence - * Argument : None - * Returned Value : Zero (OK) is returned on success. Otherwise -1 - * (ERROR) is returned with the errno variable set - * to indicate the nature of the error. - * Dependencies : None - */ - - case CANIOC_BUSOFF_RECOVERY: - { - ret = fdcan_start_busoff_recovery_sequence(priv); - } - break; - - /* Unsupported/unrecognized command */ - - default: - canerr("ERROR: Unrecognized command: %04x\n", cmd); - break; - } - - return ret; -} - -/**************************************************************************** - * Name: fdcan_remoterequest - * - * Description: - * Send a remote request - * - * Input Parameters: - * dev - An instance of the "upper half" can driver state structure. - * - * Returned Value: - * Zero on success; a negated errno on failure - * - ****************************************************************************/ - -static int fdcan_remoterequest(struct can_dev_s *dev, uint16_t id) -{ - /* REVISIT: Remote request not implemented */ - - return -ENOSYS; -} - -/**************************************************************************** - * Name: fdcan_send - * - * Description: - * Send one can message. - * - * One CAN-message consists of a maximum of 10 bytes. A message is - * composed of at least the first 2 bytes (when there are no data bytes). - * - * Byte 0: Bits 0-7: Bits 3-10 of the 11-bit CAN identifier - * Byte 1: Bits 5-7: Bits 0-2 of the 11-bit CAN identifier - * Bit 4: Remote Transmission Request (RTR) - * Bits 0-3: Data Length Code (DLC) - * Bytes 2-10: CAN data - * - * Input Parameters: - * dev - An instance of the "upper half" can driver state structure. - * - * Returned Value: - * Zero on success; a negated errno on failure - * - ****************************************************************************/ - -static int fdcan_send(struct can_dev_s *dev, struct can_msg_s *msg) -{ - struct stm32_fdcan_s *priv = NULL; - const struct stm32_config_s *config = NULL; - volatile uint32_t *txbuffer = NULL; - const uint8_t *src = NULL; - uint32_t *dest = NULL; - uint32_t regval = 0; - unsigned int ndx = 0; - unsigned int nbytes = 0; - uint32_t wordbuffer = 0; - unsigned int i = 0; - - DEBUGASSERT(dev); - priv = dev->cd_priv; - DEBUGASSERT(priv && priv->config); - config = priv->config; - - caninfo("CAN%" PRIu8 " ID: %" PRIu32 " DLC: %" PRIu8 "\n", - config->port, (uint32_t)msg->cm_hdr.ch_id, msg->cm_hdr.ch_dlc); - - fdcan_dumptxregs(priv, "Before send"); - - /* That that FIFO elements were configured */ - - DEBUGASSERT(config->ntxfifoq > 0); - - /* Get our reserved Tx FIFO/queue put index */ - - regval = fdcan_getreg(priv, STM32_FDCAN_TXFQS_OFFSET); - DEBUGASSERT((regval & FDCAN_TXFQS_TFQF) == 0); - - ndx = (regval & FDCAN_TXFQS_TFQPI_MASK) >> FDCAN_TXFQS_TFQPI_SHIFT; - - /* And the TX buffer corresponding to this index */ - - txbuffer = (config->msgram.txfifoq + ndx * config->txbufferesize); - - /* Format the TX FIFOQ entry - * - * Format word T0: - * Transfer message ID (ID) - Value from message structure - * Remote Transmission Request (RTR) - Value from message structure - * Extended Identifier (XTD) - Depends on configuration. - * Error state indicator (ESI) - ESI bit in CAN FD - * - * Format word T1: - * Data Length Code (DLC) - Value from message structure - * Bit Rate Switch (BRS) - Bit rate switching for CAN FD - * FD format (FDF) - Frame transmitted in CAN FD format - * Event FIFO Control (EFC) - Do not store events. - * Message Marker (MM) - Always zero - */ - - txbuffer[0] = 0; - txbuffer[1] = 0; - -#ifdef CONFIG_CAN_EXTID - if (msg->cm_hdr.ch_extid == 1) - { - DEBUGASSERT(msg->cm_hdr.ch_id <= CAN_MAX_EXTMSGID); - - txbuffer[0] |= BUFFER_R0_EXTID(msg->cm_hdr.ch_id) | BUFFER_R0_XTD; - } - else -#endif - { - DEBUGASSERT(msg->cm_hdr.ch_id <= CAN_MAX_STDMSGID); - - txbuffer[0] |= BUFFER_R0_STDID(msg->cm_hdr.ch_id); - } - - if (msg->cm_hdr.ch_rtr == 1) - { - txbuffer[0] |= BUFFER_R0_RTR; - } - - txbuffer[1] |= BUFFER_R1_DLC(msg->cm_hdr.ch_dlc); - -#ifdef CONFIG_CAN_FD - /* CAN FD Format */ - - if (msg->cm_hdr.ch_edl == 1) - { - txbuffer[1] |= BUFFER_R1_FDF; - - if (msg->cm_hdr.ch_brs == 1) - { - txbuffer[1] |= BUFFER_R1_BRS; - } - - if (msg->cm_hdr.ch_esi == 1) - { - txbuffer[0] |= BUFFER_R0_ESI; - } - } - else -#else - { - txbuffer[0] &= ~BUFFER_R0_ESI; - txbuffer[1] &= ~BUFFER_R1_FDF; - txbuffer[1] &= ~BUFFER_R1_BRS; - } -#endif - - /* Followed by the amount of data corresponding to the DLC (T2..) */ - - dest = (uint32_t *)&txbuffer[2]; - src = msg->cm_data; - nbytes = fdcan_dlc2bytes(priv, msg->cm_hdr.ch_dlc); - - /* Writes must be word length */ - - for (i = 0; i < nbytes; i += 4) - { - /* Little endian is assumed */ - - wordbuffer = src[0] | - (src[1] << 8) | - (src[2] << 16) | - (src[3] << 24); - src += 4; - - *dest++ = wordbuffer; - } - - /* Enable transmit interrupts from the TX FIFOQ buffer by setting TC - * interrupt bit in IR (also requires that the TC interrupt is enabled) - */ - - fdcan_putreg(priv, STM32_FDCAN_TXBTIE_OFFSET, (1 << ndx)); - - /* And request to send the packet */ - - fdcan_putreg(priv, STM32_FDCAN_TXBAR_OFFSET, (1 << ndx)); - - return OK; -} - -/**************************************************************************** - * Name: fdcan_txready - * - * Description: - * Return true if the FDCAN hardware can accept another TX message. - * - * Input Parameters: - * dev - An instance of the "upper half" can driver state structure. - * - * Returned Value: - * True if the FDCAN hardware is ready to accept another TX message. - * - ****************************************************************************/ - -static bool fdcan_txready(struct can_dev_s *dev) -{ - struct stm32_fdcan_s *priv = dev->cd_priv; - uint32_t regval = 0; - bool notfull = false; - - /* Return the state of the TX FIFOQ. Return TRUE if the TX FIFO/Queue is - * not full. - */ - - regval = fdcan_getreg(priv, STM32_FDCAN_TXFQS_OFFSET); - notfull = ((regval & FDCAN_TXFQS_TFQF) == 0); - - return notfull; -} - -/**************************************************************************** - * Name: fdcan_txempty - * - * Description: - * Return true if all message have been sent. If for example, the FDCAN - * hardware implements FIFOs, then this would mean the transmit FIFO is - * empty. This method is called when the driver needs to make sure that - * all characters are "drained" from the TX hardware before calling - * co_shutdown(). - * - * Input Parameters: - * dev - An instance of the "upper half" can driver state structure. - * - * Returned Value: - * True if there are no pending TX transfers in the FDCAN hardware. - * - ****************************************************************************/ - -static bool fdcan_txempty(struct can_dev_s *dev) -{ - struct stm32_fdcan_s *priv = dev->cd_priv; - uint32_t regval = 0; - int tffl = 0; - bool empty = false; - - DEBUGASSERT(priv != NULL && priv->config != NULL); - - /* Return the state of the TX FIFOQ. Return TRUE if the TX FIFO/Queue is - * empty. We don't have a reliable indication that the FIFO is empty, so - * we have to use some heuristics. - */ - - regval = fdcan_getreg(priv, STM32_FDCAN_TXFQS_OFFSET); - if ((regval & FDCAN_TXFQS_TFQF) != 0) - { - return false; - } - - /* Tx FIFO Free Level */ - - tffl = (regval & FDCAN_TXFQS_TFFL_MASK) >> FDCAN_TXFQS_TFFL_SHIFT; - empty = (tffl >= priv->config->ntxfifoq); - - return empty; -} - -/**************************************************************************** - * Name: fdcan_error - * - * Description: - * Report a CAN error - * - * Input Parameters: - * dev - CAN-common state data - * status - Interrupt status with error bits set - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef CONFIG_CAN_ERRORS -static void fdcan_error(struct can_dev_s *dev, uint32_t status) -{ - struct stm32_fdcan_s *priv = dev->cd_priv; - struct can_hdr_s hdr; - uint32_t psr = 0; - uint16_t errbits = 0; - uint8_t data[CAN_ERROR_DLC]; - int ret = 0; - - /* Encode error bits */ - - errbits = 0; - memset(data, 0, sizeof(data)); - - /* Always fill in "static" error conditions, but set the signaling bit - * only if the condition has changed (see IRQ-Flags below) - * They have to be filled in every time CAN_ERROR_CONTROLLER is set. - */ - - psr = fdcan_getreg(priv, STM32_FDCAN_PSR_OFFSET); - if ((psr & FDCAN_PSR_EP) != 0) - { - data[1] |= (CAN_ERROR1_RXPASSIVE | CAN_ERROR1_TXPASSIVE); - } - - if ((psr & FDCAN_PSR_EW) != 0) - { - data[1] |= (CAN_ERROR1_RXWARNING | CAN_ERROR1_TXWARNING); - } - - if ((status & (FDCAN_INT_EP | FDCAN_INT_EW)) != 0) - { - /* "Error Passive" or "Error Warning" status changed */ - - errbits |= CAN_ERROR_CONTROLLER; - } - - if ((status & FDCAN_INT_PEA) != 0) - { - /* Protocol Error in Arbitration Phase */ - - if ((psr & FDCAN_PSR_LEC_MASK) != 0) - { - /* Error code present */ - - if ((psr & FDCAN_PSR_LEC(FDCAN_PSR_EC_STUFF_ERROR)) != 0) - { - /* Stuff Error */ - - errbits |= CAN_ERROR_PROTOCOL; - data[2] |= CAN_ERROR2_STUFF; - } - - if ((psr & FDCAN_PSR_LEC(FDCAN_PSR_EC_FORM_ERROR)) != 0) - { - /* Format Error */ - - errbits |= CAN_ERROR_PROTOCOL; - data[2] |= CAN_ERROR2_FORM; - } - - if ((psr & FDCAN_PSR_LEC(FDCAN_PSR_EC_ACK_ERROR)) != 0) - { - /* Acknowledge Error */ - - errbits |= CAN_ERROR_NOACK; - } - - if ((psr & FDCAN_PSR_LEC(FDCAN_PSR_EC_BIT0_ERROR)) != 0) - { - /* Bit0 Error */ - - errbits |= CAN_ERROR_PROTOCOL; - data[2] |= CAN_ERROR2_BIT0; - } - - if ((psr & FDCAN_PSR_LEC(FDCAN_PSR_EC_BIT1_ERROR)) != 0) - { - /* Bit1 Error */ - - errbits |= CAN_ERROR_PROTOCOL; - data[2] |= CAN_ERROR2_BIT1; - } - - if ((psr & FDCAN_PSR_LEC(FDCAN_PSR_EC_CRC_ERROR)) != 0) - { - /* Receive CRC Error */ - - errbits |= CAN_ERROR_PROTOCOL; - data[3] |= (CAN_ERROR3_CRCSEQ | CAN_ERROR3_CRCDEL); - } - - if ((psr & FDCAN_PSR_LEC(FDCAN_PSR_EC_NO_CHANGE)) != 0) - { - /* No Change in Error */ - - errbits |= CAN_ERROR_PROTOCOL; - data[2] |= CAN_ERROR2_UNSPEC; - } - } - } - - if ((status & FDCAN_INT_PED) != 0) - { - /* Protocol Error in Data Phase */ - - if ((psr & FDCAN_PSR_DLEC_MASK) != 0) - { - /* Error code present */ - - if ((psr & FDCAN_PSR_DLEC(FDCAN_PSR_EC_STUFF_ERROR)) != 0) - { - /* Stuff Error */ - - errbits |= CAN_ERROR_PROTOCOL; - data[2] |= CAN_ERROR2_STUFF; - } - - if ((psr & FDCAN_PSR_DLEC(FDCAN_PSR_EC_FORM_ERROR)) != 0) - { - /* Format Error */ - - errbits |= CAN_ERROR_PROTOCOL; - data[2] |= CAN_ERROR2_FORM; - } - - if ((psr & FDCAN_PSR_DLEC(FDCAN_PSR_EC_ACK_ERROR)) != 0) - { - /* Acknowledge Error */ - - errbits |= CAN_ERROR_NOACK; - } - - if ((psr & FDCAN_PSR_DLEC(FDCAN_PSR_EC_BIT0_ERROR)) != 0) - { - /* Bit0 Error */ - - errbits |= CAN_ERROR_PROTOCOL; - data[2] |= CAN_ERROR2_BIT0; - } - - if ((psr & FDCAN_PSR_DLEC(FDCAN_PSR_EC_BIT1_ERROR)) != 0) - { - /* Bit1 Error */ - - errbits |= CAN_ERROR_PROTOCOL; - data[2] |= CAN_ERROR2_BIT1; - } - - if ((psr & FDCAN_PSR_DLEC(FDCAN_PSR_EC_CRC_ERROR)) != 0) - { - /* Receive CRC Error */ - - errbits |= CAN_ERROR_PROTOCOL; - data[3] |= (CAN_ERROR3_CRCSEQ | CAN_ERROR3_CRCDEL); - } - - if ((psr & FDCAN_PSR_DLEC(FDCAN_PSR_EC_NO_CHANGE)) != 0) - { - /* No Change in Error */ - - errbits |= CAN_ERROR_PROTOCOL; - data[2] |= CAN_ERROR2_UNSPEC; - } - } - } - - if ((status & FDCAN_INT_BO) != 0) - { - /* Bus_Off Status changed */ - - if ((psr & FDCAN_PSR_BO) != 0) - { - errbits |= CAN_ERROR_BUSOFF; - } - else - { - errbits |= CAN_ERROR_RESTARTED; - } - } - - if ((status & (FDCAN_INT_RF0L | FDCAN_INT_RF1L)) != 0) - { - /* Receive FIFO 0/1 Message Lost - * Receive FIFO 1 Message Lost - */ - - errbits |= CAN_ERROR_CONTROLLER; - data[1] |= CAN_ERROR1_RXOVERFLOW; - } - - if ((status & FDCAN_INT_TEFL) != 0) - { - /* Tx Event FIFO Element Lost */ - - errbits |= CAN_ERROR_CONTROLLER; - data[1] |= CAN_ERROR1_TXOVERFLOW; - } - - if ((status & FDCAN_INT_TOO) != 0) - { - /* Timeout Occurred */ - - errbits |= CAN_ERROR_TXTIMEOUT; - } - - if ((status & (FDCAN_INT_MRAF | FDCAN_INT_ELO)) != 0) - { - /* Message RAM Access Failure - * Error Logging Overflow - */ - - errbits |= CAN_ERROR_CONTROLLER; - data[1] |= CAN_ERROR1_UNSPEC; - } - - if (errbits != 0) - { - /* Format the CAN header for the error report. */ - - hdr.ch_id = errbits; - hdr.ch_dlc = CAN_ERROR_DLC; - hdr.ch_rtr = 0; - hdr.ch_error = 1; -#ifdef CONFIG_CAN_EXTID - hdr.ch_extid = 0; -#endif - hdr.ch_tcf = 0; - - /* And provide the error report to the upper half logic */ - - ret = can_receive(dev, &hdr, data); - if (ret < 0) - { - canerr("ERROR: can_receive failed: %d\n", ret); - } - } -} -#endif /* CONFIG_CAN_ERRORS */ - -/**************************************************************************** - * Name: fdcan_receive - * - * Description: - * Receive an FDCAN messages - * - * Input Parameters: - * dev - CAN-common state data - * rxbuffer - The RX buffer containing the received messages - * nwords - The length of the RX buffer (element size in words). - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void fdcan_receive(struct can_dev_s *dev, - volatile uint32_t *rxbuffer, - unsigned long nwords) -{ - struct can_hdr_s hdr; - int ret = 0; - - fdcan_dumprxregs(dev->cd_priv, "Before receive"); - - /* Format the CAN header */ - - /* Word R0 contains the CAN ID */ - -#ifdef CONFIG_CAN_ERRORS - hdr.ch_error = 0; -#endif - hdr.ch_tcf = 0; - - /* Extract the RTR bit */ - - hdr.ch_rtr = ((rxbuffer[0] & BUFFER_R0_RTR) != 0); - -#ifdef CONFIG_CAN_EXTID - if ((rxbuffer[0] & BUFFER_R0_XTD) != 0) - { - /* Save the extended ID of the newly received message */ - - hdr.ch_id = (rxbuffer[0] & BUFFER_R0_EXTID_MASK) >> - BUFFER_R0_EXTID_SHIFT; - hdr.ch_extid = 1; - } - else - { - hdr.ch_id = (rxbuffer[0] & BUFFER_R0_STDID_MASK) >> - BUFFER_R0_STDID_SHIFT; - hdr.ch_extid = 0; - } - -#else - if ((rxbuffer[0] & BUFFER_R0_XTD) != 0) - { - /* Drop any messages with extended IDs */ - - canerr("ERROR: Received message with extended identifier. Dropped\n"); - - return; - } - - /* Save the standard ID of the newly received message */ - - hdr.ch_id = (rxbuffer[0] & BUFFER_R0_STDID_MASK) >> BUFFER_R0_STDID_SHIFT; -#endif - - /* Word R1 contains the DLC and timestamp */ - - hdr.ch_dlc = (rxbuffer[1] & BUFFER_R1_DLC_MASK) >> BUFFER_R1_DLC_SHIFT; - -#ifdef CONFIG_CAN_FD - /* CAN FD format */ - - hdr.ch_esi = ((rxbuffer[0] & BUFFER_R0_ESI) != 0); - hdr.ch_edl = ((rxbuffer[1] & BUFFER_R1_FDF) != 0); - hdr.ch_brs = ((rxbuffer[1] & BUFFER_R1_BRS) != 0); -#else - if ((rxbuffer[1] & BUFFER_R1_FDF) != 0) - { - /* Drop any FD CAN messages if not supported */ - - canerr("ERROR: Received CAN FD message. Dropped\n"); - - return; - } -#endif - - /* And provide the CAN message to the upper half logic */ - - ret = can_receive(dev, &hdr, (uint8_t *)&rxbuffer[2]); - if (ret < 0) - { - canerr("ERROR: can_receive failed: %d\n", ret); - } -} - -/**************************************************************************** - * Name: fdcan_interrupt - * - * Description: - * Common FDCAN interrupt handler - * - * Input Parameters: - * dev - CAN-common state data - * - * Returned Value: - * None - * - ****************************************************************************/ - -static int fdcan_interrupt(int irq, void *context, void *arg) -{ - struct can_dev_s *dev = (struct can_dev_s *)arg; - struct stm32_fdcan_s *priv = NULL; - const struct stm32_config_s *config = NULL; - uint32_t ir = 0; - uint32_t ie = 0; - uint32_t pending = 0; - uint32_t regval = 0; - uint32_t psr = 0; - unsigned int nelem = 0; - unsigned int ndx = 0; - - DEBUGASSERT(dev != NULL); - priv = dev->cd_priv; - DEBUGASSERT(priv && priv->config); - config = priv->config; - - /* Get the set of pending interrupts. */ - - ir = fdcan_getreg(priv, STM32_FDCAN_IR_OFFSET); - ie = fdcan_getreg(priv, STM32_FDCAN_IE_OFFSET); - - pending = (ir & ie); - - /* Check for any errors */ - - if ((pending & FDCAN_ANYERR_INTS) != 0) - { - /* Check for common errors */ - - if ((pending & FDCAN_CMNERR_INTS) != 0) - { - canerr("ERROR: Common %08" PRIx32 "\n", - pending & FDCAN_CMNERR_INTS); - - /* When a protocol error occurs, the problem is recorded in - * the LEC/DLEC fields of the PSR register. In lieu of - * separate interrupt flags for each error, the hardware - * groups protocol errors under a single interrupt each for - * arbitration and data phases. - * - * These errors have a tendency to flood the system with - * interrupts, so they are disabled here until we get a - * successful transfer/receive on the hardware - */ - - psr = fdcan_getreg(priv, STM32_FDCAN_PSR_OFFSET); - - if ((psr & FDCAN_PSR_LEC_MASK) != 0) - { - canerr("ERROR: PSR %08" PRIx32 "\n", psr); - ie &= ~(FDCAN_INT_PEA | FDCAN_INT_PED); - fdcan_putreg(priv, STM32_FDCAN_IE_OFFSET, ie); - caninfo("disabled protocol error interrupts\n"); - } - - /* Clear the error indications */ - - fdcan_putreg(priv, STM32_FDCAN_IR_OFFSET, FDCAN_CMNERR_INTS); - } - - /* Check for transmission errors */ - - if ((pending & FDCAN_TXERR_INTS) != 0) - { - canerr("ERROR: TX %08" PRIx32 "\n", - pending & FDCAN_TXERR_INTS); - - /* An Acknowledge-Error will occur if for example the device - * is not connected to the bus. - * - * The CAN-Standard states that the Chip has to retry the - * message forever, which will produce an ACKE every time. - * To prevent this Interrupt-Flooding and the high CPU-Load - * we disable the ACKE here as long we didn't transfer at - * least one message successfully (see FDCAN_INT_TC below). - */ - - /* Clear the error indications */ - - fdcan_putreg(priv, STM32_FDCAN_IR_OFFSET, FDCAN_TXERR_INTS); - } - - /* Check for reception errors */ - - if ((pending & FDCAN_RXERR_INTS) != 0) - { - canerr("ERROR: RX %08" PRIx32 "\n", - pending & FDCAN_RXERR_INTS); - - /* To prevent Interrupt-Flooding the current active - * RX error interrupts are disabled. After successfully - * receiving at least one CAN packet all RX error interrupts - * are turned back on. - * - * The Interrupt-Flooding can for example occur if the - * configured CAN speed does not match the speed of the other - * CAN nodes in the network. - */ - - ie &= ~(pending & FDCAN_RXERR_INTS); - fdcan_putreg(priv, STM32_FDCAN_IE_OFFSET, ie); - - /* Clear the error indications */ - - fdcan_putreg(priv, STM32_FDCAN_IR_OFFSET, FDCAN_RXERR_INTS); - } - -#ifdef CONFIG_CAN_ERRORS - /* Report errors */ - - fdcan_error(dev, pending & FDCAN_ANYERR_INTS); -#endif - } - - /* Check for successful completion of a transmission */ - - if ((pending & FDCAN_INT_TC) != 0) - { - /* Check if we have disabled the ACKE in the error-handling above - * (see FDCAN_TXERR_INTS) to prevent Interrupt-Flooding and - * re-enable the error interrupt here again. - */ - - if ((ie & (FDCAN_INT_PEA | FDCAN_INT_PED)) == 0) - { - ie |= (FDCAN_INT_PEA | FDCAN_INT_PED); - fdcan_putreg(priv, STM32_FDCAN_IE_OFFSET, ie); - caninfo("Re-enabled protocol error interrupts\n"); - } - - /* Clear the pending TX completion interrupt (and all - * other TX-related interrupts) - */ - - fdcan_putreg(priv, STM32_FDCAN_IR_OFFSET, priv->txints); - - /* Check all TX buffers */ - - regval = fdcan_getreg(priv, STM32_FDCAN_TXBTO_OFFSET); - for (ndx = 0; ndx < config->ntxfifoq; ndx++) - { - if ((regval & (1 << ndx)) != 0) - { - /* Tell the upper half that the transfer is finished. */ - - can_txdone(dev); - } - } - } - else if ((pending & priv->txints) != 0) - { - /* Clear unhandled TX events */ - - fdcan_putreg(priv, STM32_FDCAN_IR_OFFSET, priv->txints); - } - - /* Clear the RX FIFO1 new message interrupt */ - - fdcan_putreg(priv, STM32_FDCAN_IR_OFFSET, FDCAN_INT_RF1N); - pending &= ~FDCAN_INT_RF1N; - - /* We treat RX FIFO1 as the "high priority" queue: We will process - * all messages in RX FIFO1 before processing any message from RX - * FIFO0. - */ - - for (; ; ) - { - /* Check if there is anything in RX FIFO1 */ - - regval = fdcan_getreg(priv, STM32_FDCAN_RXF1S_OFFSET); - nelem = (regval & FDCAN_RXFS_FFL_MASK) >> FDCAN_RXFS_FFL_SHIFT; - if (nelem == 0) - { - /* Break out of the loop if RX FIFO1 is empty */ - - break; - } - - /* Clear the RX FIFO1 interrupt (and all other FIFO1-related - * interrupts) - */ - - /* Handle the newly received message in FIFO1 */ - - ndx = (regval & FDCAN_RXFS_FGI_MASK) >> FDCAN_RXFS_FGI_SHIFT; - - if ((regval & FDCAN_RXFS_RFL) != 0) - { - canerr("ERROR: Message lost: %08" PRIx32 "\n", regval); - } - else - { - fdcan_receive(dev, - config->msgram.rxfifo1 + - (ndx * priv->config->rxfifo1esize), - priv->config->rxfifo1esize); - - /* Turning back on all configured RX error interrupts */ - - ie |= (priv->rxints & FDCAN_RXERR_INTS); - fdcan_putreg(priv, STM32_FDCAN_IE_OFFSET, ie); - } - - /* Acknowledge reading the FIFO entry */ - - fdcan_putreg(priv, STM32_FDCAN_RXF1A_OFFSET, ndx); - } - - /* Check for successful reception of a new message in RX FIFO0 */ - - /* Clear the RX FIFO0 new message interrupt */ - - fdcan_putreg(priv, STM32_FDCAN_IR_OFFSET, FDCAN_INT_RF0N); - pending &= ~FDCAN_INT_RF0N; - - /* Check if there is anything in RX FIFO0 */ - - regval = fdcan_getreg(priv, STM32_FDCAN_RXF0S_OFFSET); - nelem = (regval & FDCAN_RXFS_FFL_MASK) >> FDCAN_RXFS_FFL_SHIFT; - if (nelem > 0) - { - /* Handle the newly received message in FIFO0 */ - - ndx = (regval & FDCAN_RXFS_FGI_MASK) >> FDCAN_RXFS_FGI_SHIFT; - - if ((regval & FDCAN_RXFS_RFL) != 0) - { - canerr("ERROR: Message lost: %08" PRIx32 "\n", regval); - } - else - { - fdcan_receive(dev, - config->msgram.rxfifo0 + - (ndx * priv->config->rxfifo0esize), - priv->config->rxfifo0esize); - - /* Turning back on all configured RX error interrupts */ - - ie |= (priv->rxints & FDCAN_RXERR_INTS); - fdcan_putreg(priv, STM32_FDCAN_IE_OFFSET, ie); - } - - /* Acknowledge reading the FIFO entry */ - - fdcan_putreg(priv, STM32_FDCAN_RXF0A_OFFSET, ndx); - } - - /* Clear unhandled RX interrupts */ - - if ((pending & priv->rxints) != 0) - { - fdcan_putreg(priv, STM32_FDCAN_IR_OFFSET, priv->rxints); - } - - return OK; -} - -/**************************************************************************** - * Name: fdcan_hw_initialize - * - * Description: - * FDCAN hardware initialization - * - * Input Parameters: - * priv - A pointer to the private data structure for this FDCAN peripheral - * - * Returned Value: - * Zero on success; a negated errno value on failure. - * - ****************************************************************************/ - -static int fdcan_hw_initialize(struct stm32_fdcan_s *priv) -{ - const struct stm32_config_s *config = priv->config; - volatile uint32_t *msgram = NULL; - uint32_t regval = 0; - uint32_t cntr = 0; - - caninfo("FDCAN%d\n", config->port); - - /* Clean message RAM */ - - msgram = config->msgram.stdfilters; - cntr = (FDCAN_MSGRAM_WORDS + 1); - while (cntr > 0) - { - *msgram++ = 0; - cntr--; - } - - /* Configure FDCAN pins */ - - stm32_configgpio(config->rxpinset); - stm32_configgpio(config->txpinset); - - /* Re-enable device if previously disabled in fdcan_shutdown() */ - - if (priv->state == FDCAN_STATE_DISABLED) - { - /* Reset Clock Stop Request bit */ - - regval = fdcan_getreg(priv, STM32_FDCAN_CCCR_OFFSET); - regval &= ~FDCAN_CCCR_CSR; - fdcan_putreg(priv, STM32_FDCAN_CCCR_OFFSET, regval); - - /* Wait for Clock Stop Acknowledge bit reset to indicate - * device is operational - */ - - while ((fdcan_getreg(priv, STM32_FDCAN_CCCR_OFFSET) & FDCAN_CCCR_CSA) - != 0); - } - - /* Enable the Initialization state */ - - regval = fdcan_getreg(priv, STM32_FDCAN_CCCR_OFFSET); - regval |= FDCAN_CCCR_INIT; - fdcan_putreg(priv, STM32_FDCAN_CCCR_OFFSET, regval); - - /* Wait for initialization mode to take effect */ - - while ((fdcan_getreg(priv, STM32_FDCAN_CCCR_OFFSET) & FDCAN_CCCR_INIT) - == 0); - - /* Enable writing to configuration registers */ - - regval = fdcan_getreg(priv, STM32_FDCAN_CCCR_OFFSET); - regval |= FDCAN_CCCR_CCE; - fdcan_putreg(priv, STM32_FDCAN_CCCR_OFFSET, regval); - - /* Global Filter Configuration: - * - * ANFS=0: Store all non matching standard frame in RX FIFO0 - * ANFE=0: Store all non matching extended frame in RX FIFO0 - */ - - regval = FDCAN_RXGFC_ANFE_RX_FIFO0 | FDCAN_RXGFC_ANFS_RX_FIFO0; - fdcan_putreg(priv, STM32_FDCAN_RXGFC_OFFSET, regval); - - /* Extended ID Filter AND mask */ - - fdcan_putreg(priv, STM32_FDCAN_XIDAM_OFFSET, 0x1fffffff); - - /* Disable all interrupts */ - - fdcan_putreg(priv, STM32_FDCAN_IE_OFFSET, 0); - fdcan_putreg(priv, STM32_FDCAN_TXBTIE_OFFSET, 0); - - /* All interrupts directed to Line 0. But disable both interrupt lines 0 - * and 1 for now. - * - * REVISIT: Only interrupt line 0 is used by this driver. - */ - - fdcan_putreg(priv, STM32_FDCAN_ILS_OFFSET, 0); - fdcan_putreg(priv, STM32_FDCAN_ILE_OFFSET, 0); - - /* Clear all pending interrupts. */ - - fdcan_putreg(priv, STM32_FDCAN_IR_OFFSET, FDCAN_INT_ALL); - - /* Configure FDCAN bit timing */ - - fdcan_putreg(priv, STM32_FDCAN_NBTP_OFFSET, priv->nbtp); - fdcan_putreg(priv, STM32_FDCAN_DBTP_OFFSET, priv->dbtp); - - /* Configure message RAM starting addresses and sizes. */ - - regval = FDCAN_RXGFC_LSS(config->nstdfilters); - regval |= FDCAN_RXGFC_LSE(config->nextfilters); - fdcan_putreg(priv, STM32_FDCAN_RXGFC_OFFSET, regval); - - /* Dump RAM layout */ - - fdcan_dumpramlayout(priv); - - /* Configure Message Filters */ - - /* Disable all standard filters */ - - msgram = config->msgram.stdfilters; - cntr = config->nstdfilters; - while (cntr > 0) - { - *msgram++ = STDFILTER_S0_SFEC_DISABLE; - cntr--; - } - - /* Disable all extended filters */ - - msgram = config->msgram.extfilters; - cntr = config->nextfilters; - while (cntr > 0) - { - *msgram = EXTFILTER_F0_EFEC_DISABLE; - msgram = msgram + 2; - cntr--; - } - - /* Input clock divider configuration */ - - regval = FDCANCLK_PDIV; - fdcan_putreg(priv, STM32_FDCAN_CKDIV_OFFSET, regval); - - /* CC control register */ - - regval = fdcan_getreg(priv, STM32_FDCAN_CCCR_OFFSET); - regval &= ~(FDCAN_CCCR_NISO | FDCAN_CCCR_FDOE | FDCAN_CCCR_BRSE); - - /* Select ISO11898-1 or Non ISO Bosch CAN FD Specification V1.0 */ - - switch (config->format) - { - case FDCAN_ISO11898_1_FORMAT: - { - break; - } - - case FDCAN_NONISO_BOSCH_V1_FORMAT: - { - regval |= FDCAN_CCCR_NISO; - break; - } - - default: - { - return -EINVAL; - } - } - - /* Select Classic CAN mode or FD mode with or without fast bit rate - * switching - */ - - switch (config->mode) - { - case FDCAN_CLASSIC_MODE: - { - break; - } - -#ifdef CONFIG_CAN_FD - case FDCAN_FD_MODE: - { - regval |= FDCAN_CCCR_FDOE; - break; - } - - case FDCAN_FD_BRS_MODE: - { - regval |= (FDCAN_CCCR_FDOE | FDCAN_CCCR_BRSE); - break; - } -#endif - - default: - { - return -EINVAL; - } - } - - /* Set the initial CAN mode */ - - fdcan_putreg(priv, STM32_FDCAN_CCCR_OFFSET, regval); - - /* Enable FIFO/Queue mode */ - - regval = fdcan_getreg(priv, STM32_FDCAN_TXBC_OFFSET); -#ifdef CONFIG_STM32_FDCAN_QUEUE_MODE - regval |= FDCAN_TXBC_TFQM; -#else - regval &= ~FDCAN_TXBC_TFQM; -#endif - fdcan_putreg(priv, STM32_FDCAN_TXBC_OFFSET, regval); - -#ifdef STM32_FDCAN_LOOPBACK - /* Is loopback mode selected for this peripheral? */ - - if (config->loopback) - { - /* FDCAN_CCCR_TEST - Test mode enable - * FDCAN_CCCR_MON - Bus monitoring mode (for internal loopback) - * FDCAN_TEST_LBCK - Loopback mode - */ - - regval = fdcan_getreg(priv, STM32_FDCAN_CCCR_OFFSET); - regval |= (FDCAN_CCCR_TEST | FDCAN_CCCR_MON); - fdcan_putreg(priv, STM32_FDCAN_CCCR_OFFSET, regval); - - regval = fdcan_getreg(priv, STM32_FDCAN_TEST_OFFSET); - regval |= FDCAN_TEST_LBCK; - fdcan_putreg(priv, STM32_FDCAN_TEST_OFFSET, regval); - } -#endif - - /* Configure interrupt lines */ - - /* Select RX-related interrupts */ - - priv->rxints = FDCAN_RXFIFO_INTS; - - /* Select TX-related interrupts */ - - priv->txints = FDCAN_TXFIFOQ_INTS; - - /* Direct all interrupts to Line 0. - * - * Bits in the ILS register correspond to each FDCAN interrupt; A bit - * set to '1' is directed to interrupt line 1; a bit cleared to '0' - * is directed interrupt line 0. - * - * REVISIT: Nothing is done here. Only interrupt line 0 is used by - * this driver and ILS was already cleared above. - */ - - /* Enable only interrupt line 0. */ - - fdcan_putreg(priv, STM32_FDCAN_ILE_OFFSET, FDCAN_ILE_EINT0); - - /* Disable initialization mode to enable normal operation */ - - regval = fdcan_getreg(priv, STM32_FDCAN_CCCR_OFFSET); - regval &= ~FDCAN_CCCR_INIT; - fdcan_putreg(priv, STM32_FDCAN_CCCR_OFFSET, regval); - - return OK; -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_fdcaninitialize - * - * Description: - * Initialize the selected FDCAN port - * - * Input Parameters: - * port - Port number (for hardware that has multiple FDCAN interfaces), - * 1=FDCAN1, 2=FDCAN2, 3=FDCAN3 - * - * Returned Value: - * Valid CAN device structure reference on success; a NULL on failure - * - ****************************************************************************/ - -struct can_dev_s *stm32_fdcaninitialize(int port) -{ - struct can_dev_s *dev = NULL; - struct stm32_fdcan_s *priv = NULL; - const struct stm32_config_s *config = NULL; - - caninfo("FDCAN%d\n", port); - - /* Select FDCAN peripheral to be initialized */ - -#ifdef CONFIG_STM32_FDCAN1 - if (port == FDCAN1) - { - /* Select the FDCAN1 device structure */ - - dev = &g_fdcan1dev; - priv = &g_fdcan1priv; - config = &g_fdcan1const; - } - else -#endif -#ifdef CONFIG_STM32_FDCAN2 - if (port == FDCAN2) - { - /* Select the FDCAN2 device structure */ - - dev = &g_fdcan2dev; - priv = &g_fdcan2priv; - config = &g_fdcan2const; - } - else -#endif -#ifdef CONFIG_STM32_FDCAN3 - if (port == FDCAN3) - { - /* Select the FDCAN3 device structure */ - - dev = &g_fdcan3dev; - priv = &g_fdcan3priv; - config = &g_fdcan3const; - } - else -#endif - { - canerr("ERROR: Unsupported port %d\n", port); - return NULL; - } - - /* Perform one time data initialization */ - - memset(priv, 0, sizeof(struct stm32_fdcan_s)); - priv->config = config; - - /* Set the initial bit timing. This might change subsequently - * due to IOCTL command processing. - */ - - priv->nbtp = config->nbtp; - priv->dbtp = config->dbtp; - - dev->cd_ops = &g_fdcanops; - dev->cd_priv = (void *)priv; - - /* And put the hardware in the initial state */ - - fdcan_reset(dev); - - return dev; -} diff --git a/arch/arm/src/stm32/stm32_fdcan.h b/arch/arm/src/stm32/stm32_fdcan.h deleted file mode 100644 index f157213828d9b..0000000000000 --- a/arch/arm/src/stm32/stm32_fdcan.h +++ /dev/null @@ -1,114 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_fdcan.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32_STM32_FDCAN_H -#define __ARCH_ARM_SRC_STM32_STM32_FDCAN_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "chip.h" -#include "hardware/stm32_fdcan.h" - -#include - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Port numbers for use with stm32_fdcan_initialize() */ - -#define FDCAN1 1 -#define FDCAN2 2 -#define FDCAN3 3 - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -#ifndef __ASSEMBLY__ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -#ifdef CONFIG_STM32_FDCAN_CHARDRIVER - -/**************************************************************************** - * Name: stm32_fdcaninitialize - * - * Description: - * Initialize the selected FDCAN port - * - * Input Parameters: - * Port number (for hardware that has multiple FDCAN interfaces) - * - * Returned Value: - * Valid FDCAN device structure reference on success; a NULL on failure - * - ****************************************************************************/ - -struct can_dev_s *stm32_fdcaninitialize(int port); -#endif - -#ifdef CONFIG_STM32_FDCAN_SOCKET - -/**************************************************************************** - * Name: stm32_fdcansockinitialize - * - * Description: - * Initialize the selected FDCAN port as SocketCAN interface - * - * Input Parameters: - * Port number (for hardware that has multiple FDCAN interfaces) - * - * Returned Value: - * OK on success; Negated errno on failure. - * - ****************************************************************************/ - -int stm32_fdcansockinitialize(int port); -#endif - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32_STM32_FDCAN_H */ diff --git a/arch/arm/src/stm32/stm32_fdcan_sock.c b/arch/arm/src/stm32/stm32_fdcan_sock.c deleted file mode 100644 index b4f37e29c6588..0000000000000 --- a/arch/arm/src/stm32/stm32_fdcan_sock.c +++ /dev/null @@ -1,3327 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_fdcan_sock.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -#include -#include -#include - -#include "arm_internal.h" -#include "stm32_fdcan.h" -#include "hardware/stm32_pinmap.h" -#include "stm32_gpio.h" -#include "stm32_rcc.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Pool configuration *******************************************************/ - -#define POOL_SIZE (1) - -/* Work queue support is required. */ - -#if !defined(CONFIG_SCHED_WORKQUEUE) -# error Work queue support is required -#endif - -/* The low priority work queue is preferred. If it is not enabled, LPWORK - * will be the same as HPWORK. - * - * NOTE: However, the network should NEVER run on the high priority work - * queue! That queue is intended only to service short back end interrupt - * processing that never suspends. Suspending the high priority work queue - * may bring the system to its knees! - */ - -#define CANWORK LPWORK - -/* Clock source *************************************************************/ - -#define FDCANCLK_PDIV (0) - -#if FDCANCLK_PDIV == 0 -# define STM32_FDCANCLK_FREQUENCY (STM32_FDCAN_FREQUENCY / (1)) -#else -# define STM32_FDCANCLK_FREQUENCY (STM32_FDCAN_FREQUENCY / (2 * FDCANCLK_PDIV)) -#endif - -/* General Configuration ****************************************************/ - -#if defined(CONFIG_STM32_STM32G4XXX) - -/* FDCAN Message RAM */ - -# define FDCAN_MSGRAM_WORDS (212) -# define STM32_CANRAM1_BASE (STM32_CANRAM_BASE + 0x0000) -# define STM32_CANRAM2_BASE (STM32_CANRAM_BASE + 1*(FDCAN_MSGRAM_WORDS * 4) + 4) -# define STM32_CANRAM3_BASE (STM32_CANRAM_BASE + 2*(FDCAN_MSGRAM_WORDS * 4) + 4) - -# ifdef CONFIG_STM32_FDCAN1 -# define FDCAN1_STDFILTER_SIZE (28) -# define FDCAN1_EXTFILTER_SIZE (8) -# define FDCAN1_RXFIFO0_SIZE (3) -# define FDCAN1_RXFIFO1_SIZE (3) -# define FDCAN1_TXEVENTFIFO_SIZE (3) -# define FDCAN1_TXFIFIOQ_SIZE (3) - -# define FDCAN1_STDFILTER_WORDS (28) -# define FDCAN1_EXTFILTER_WORDS (16) -# define FDCAN1_RXFIFO0_WORDS (54) -# define FDCAN1_RXFIFO1_WORDS (54) -# define FDCAN1_TXEVENTFIFO_WORDS (6) -# define FDCAN1_TXFIFIOQ_WORDS (54) -# endif -# ifdef CONFIG_STM32_FDCAN2 -# define FDCAN2_STDFILTER_SIZE (28) -# define FDCAN2_EXTFILTER_SIZE (8) -# define FDCAN2_RXFIFO0_SIZE (3) -# define FDCAN2_RXFIFO1_SIZE (3) -# define FDCAN2_TXEVENTFIFO_SIZE (3) -# define FDCAN2_TXFIFIOQ_SIZE (3) - -# define FDCAN2_STDFILTER_WORDS (28) -# define FDCAN2_EXTFILTER_WORDS (16) -# define FDCAN2_RXFIFO0_WORDS (54) -# define FDCAN2_RXFIFO1_WORDS (54) -# define FDCAN2_TXEVENTFIFO_WORDS (6) -# define FDCAN2_TXFIFIOQ_WORDS (54) -# endif -# ifdef CONFIG_STM32_FDCAN3 -# define FDCAN3_STDFILTER_SIZE (28) -# define FDCAN3_EXTFILTER_SIZE (8) -# define FDCAN3_RXFIFO0_SIZE (3) -# define FDCAN3_RXFIFO1_SIZE (3) -# define FDCAN3_TXEVENTFIFO_SIZE (3) -# define FDCAN3_TXFIFIOQ_SIZE (3) - -# define FDCAN3_STDFILTER_WORDS (28) -# define FDCAN3_EXTFILTER_WORDS (16) -# define FDCAN3_RXFIFO0_WORDS (54) -# define FDCAN3_RXFIFO1_WORDS (54) -# define FDCAN3_TXEVENTFIFO_WORDS (6) -# define FDCAN3_TXFIFIOQ_WORDS (54) -# endif -#else -# error -#endif - -/* FDCAN1 Configuration *****************************************************/ - -#ifdef CONFIG_STM32_FDCAN1 - -/* Bit timing */ - -# define FDCAN1_NTSEG1 (CONFIG_STM32_FDCAN1_NTSEG1 - 1) -# define FDCAN1_NTSEG2 (CONFIG_STM32_FDCAN1_NTSEG2 - 1) -# define FDCAN1_NBRP ((STM32_FDCANCLK_FREQUENCY / \ - ((FDCAN1_NTSEG1 + FDCAN1_NTSEG2 + 3) * \ - CONFIG_STM32_FDCAN1_BITRATE)) - 1) -# define FDCAN1_NSJW (CONFIG_STM32_FDCAN1_NSJW - 1) - -# if FDCAN1_NTSEG1 > FDCAN_NBTP_NTSEG1_MAX -# error Invalid FDCAN1 NTSEG1 -# endif -# if FDCAN1_NTSEG2 > FDCAN_NBTP_NTSEG2_MAX -# error Invalid FDCAN1 NTSEG2 -# endif -# if FDCAN1_NSJW > FDCAN_NBTP_NSJW_MAX -# error Invalid FDCAN1 NSJW -# endif -# if FDCAN1_NBRP > FDCAN_NBTP_NBRP_MAX -# error Invalid FDCAN1 NBRP -# endif - -# ifdef CONFIG_STM32_FDCAN1_FD_BRS -# define FDCAN1_DTSEG1 (CONFIG_STM32_FDCAN1_DTSEG1 - 1) -# define FDCAN1_DTSEG2 (CONFIG_STM32_FDCAN1_DTSEG2 - 1) -# define FDCAN1_DBRP ((STM32_FDCANCLK_FREQUENCY / \ - ((FDCAN1_DTSEG1 + FDCAN1_DTSEG2 + 3) * \ - CONFIG_STM32_FDCAN1_DBITRATE)) - 1) -# define FDCAN1_DSJW (CONFIG_STM32_FDCAN1_DSJW - 1) -# else -# define FDCAN1_DTSEG1 1 -# define FDCAN1_DTSEG2 1 -# define FDCAN1_DBRP 1 -# define FDCAN1_DSJW 1 -# endif /* CONFIG_STM32_FDCAN1_FD_BRS */ - -# if FDCAN1_DTSEG1 > FDCAN_DBTP_DTSEG1_MAX -# error Invalid FDCAN1 DTSEG1 -# endif -# if FDCAN1_DTSEG2 > FDCAN_DBTP_DTSEG2_MAX -# error Invalid FDCAN1 DTSEG2 -# endif -# if FDCAN1_DBRP > FDCAN_DBTP_DBRP_MAX -# error Invalid FDCAN1 DBRP -# endif -# if FDCAN1_DSJW > FDCAN_DBTP_DSJW_MAX -# error Invalid FDCAN1 DSJW -# endif - -/* FDCAN1 Message RAM Configuration *****************************************/ - -/* FDCAN1 Message RAM Layout */ - -# define FDCAN1_STDFILTER_INDEX 0 -# define FDCAN1_EXTFILTERS_INDEX (FDCAN1_STDFILTER_INDEX + FDCAN1_STDFILTER_WORDS) -# define FDCAN1_RXFIFO0_INDEX (FDCAN1_EXTFILTERS_INDEX + FDCAN1_EXTFILTER_WORDS) -# define FDCAN1_RXFIFO1_INDEX (FDCAN1_RXFIFO0_INDEX + FDCAN1_RXFIFO0_WORDS) -# define FDCAN1_TXEVENTFIFO_INDEX (FDCAN1_RXFIFO1_INDEX + FDCAN1_RXFIFO1_WORDS) -# define FDCAN1_TXFIFOQ_INDEX (FDCAN1_TXEVENTFIFO_INDEX + FDCAN1_TXEVENTFIFO_WORDS) -# define FDCAN1_MSGRAM_WORDS (FDCAN1_TXFIFOQ_INDEX + FDCAN1_TXFIFIOQ_WORDS) - -#endif /* CONFIG_STM32_FDCAN1 */ - -/* FDCAN2 Configuration *****************************************************/ - -#ifdef CONFIG_STM32_FDCAN2 - -/* Bit timing */ - -# define FDCAN2_NTSEG1 (CONFIG_STM32_FDCAN2_NTSEG1 - 1) -# define FDCAN2_NTSEG2 (CONFIG_STM32_FDCAN2_NTSEG2 - 1) -# define FDCAN2_NBRP (((STM32_FDCANCLK_FREQUENCY / \ - ((FDCAN2_NTSEG1 + FDCAN2_NTSEG2 + 3) * \ - CONFIG_STM32_FDCAN2_BITRATE)) - 1)) -# define FDCAN2_NSJW (CONFIG_STM32_FDCAN2_NSJW - 1) - -# if FDCAN2_NTSEG1 > FDCAN_NBTP_NTSEG1_MAX -# error Invalid FDCAN2 NTSEG1 -# endif -# if FDCAN2_NTSEG2 > FDCAN_NBTP_NTSEG2_MAX -# error Invalid FDCAN2 NTSEG2 -# endif -# if FDCAN2_NSJW > FDCAN_NBTP_NSJW_MAX -# error Invalid FDCAN2 NSJW -# endif -# if FDCAN2_NBRP > FDCAN_NBTP_NBRP_MAX -# error Invalid FDCAN1 NBRP -# endif - -# ifdef CONFIG_STM32_FDCAN2_FD_BRS -# define FDCAN2_DTSEG1 (CONFIG_STM32_FDCAN2_DTSEG1 - 1) -# define FDCAN2_DTSEG2 (CONFIG_STM32_FDCAN2_DTSEG2 - 1) -# define FDCAN2_DBRP (((STM32_FDCANCLK_FREQUENCY / \ - ((FDCAN2_DTSEG1 + FDCAN2_DTSEG2 + 3) * \ - CONFIG_STM32_FDCAN2_DBITRATE)) - 1)) -# define FDCAN2_DSJW (CONFIG_STM32_FDCAN2_DSJW - 1) -# else -# define FDCAN2_DTSEG1 1 -# define FDCAN2_DTSEG2 1 -# define FDCAN2_DBRP 1 -# define FDCAN2_DSJW 1 -# endif /* CONFIG_STM32_FDCAN2_FD_BRS */ - -# if FDCAN2_DTSEG1 > FDCAN_DBTP_DTSEG1_MAX -# error Invalid FDCAN2 DTSEG1 -# endif -# if FDCAN2_DTSEG2 > FDCAN_DBTP_DTSEG2_MAX -# error Invalid FDCAN2 DTSEG2 -# endif -# if FDCAN2_DBRP > FDCAN_DBTP_DBRP_MAX -# error Invalid FDCAN2 DBRP -# endif -# if FDCAN2_DSJW > FDCAN_DBTP_DSJW_MAX -# error Invalid FDCAN2 DSJW -# endif - -/* FDCAN2 Message RAM Configuration *****************************************/ - -/* FDCAN2 Message RAM Layout */ - -# define FDCAN2_STDFILTER_INDEX 0 -# define FDCAN2_EXTFILTERS_INDEX (FDCAN2_STDFILTER_INDEX + FDCAN2_STDFILTER_WORDS) -# define FDCAN2_RXFIFO0_INDEX (FDCAN2_EXTFILTERS_INDEX + FDCAN2_EXTFILTER_WORDS) -# define FDCAN2_RXFIFO1_INDEX (FDCAN2_RXFIFO0_INDEX + FDCAN2_RXFIFO0_WORDS) -# define FDCAN2_TXEVENTFIFO_INDEX (FDCAN2_RXFIFO1_INDEX + FDCAN2_RXFIFO1_WORDS) -# define FDCAN2_TXFIFOQ_INDEX (FDCAN2_TXEVENTFIFO_INDEX + FDCAN2_TXEVENTFIFO_WORDS) -# define FDCAN2_MSGRAM_WORDS (FDCAN2_TXFIFOQ_INDEX + FDCAN2_TXFIFIOQ_WORDS) - -#endif /* CONFIG_STM32_FDCAN2 */ - -/* FDCAN3 Configuration *****************************************************/ - -#ifdef CONFIG_STM32_FDCAN3 - -/* Bit timing */ - -# define FDCAN3_NTSEG1 (CONFIG_STM32_FDCAN3_NTSEG1 - 1) -# define FDCAN3_NTSEG2 (CONFIG_STM32_FDCAN3_NTSEG2 - 1) -# define FDCAN3_NBRP (((STM32_FDCANCLK_FREQUENCY / \ - ((FDCAN3_NTSEG1 + FDCAN3_NTSEG2 + 3) * \ - CONFIG_STM32_FDCAN3_BITRATE)) - 1)) -# define FDCAN3_NSJW (CONFIG_STM32_FDCAN3_NSJW - 1) - -# if FDCAN3_NTSEG1 > FDCAN_NBTP_NTSEG1_MAX -# error Invalid FDCAN3 NTSEG1 -# endif -# if FDCAN3_NTSEG2 > FDCAN_NBTP_NTSEG2_MAX -# error Invalid FDCAN3 NTSEG2 -# endif -# if FDCAN3_NSJW > FDCAN_NBTP_NSJW_MAX -# error Invalid FDCAN3 NSJW -# endif -# if FDCAN3_NBRP > FDCAN_NBTP_NBRP_MAX -# error Invalid FDCAN1 NBRP -# endif - -# ifdef CONFIG_STM32_FDCAN3_FD_BRS -# define FDCAN3_DTSEG1 (CONFIG_STM32_FDCAN3_DTSEG1 - 1) -# define FDCAN3_DTSEG2 (CONFIG_STM32_FDCAN3_DTSEG2 - 1) -# define FDCAN3_DBRP (((STM32_FDCANCLK_FREQUENCY / \ - ((FDCAN3_DTSEG1 + FDCAN3_DTSEG2 + 3) * \ - CONFIG_STM32_FDCAN3_DBITRATE)) - 1)) -# define FDCAN3_DSJW (CONFIG_STM32_FDCAN3_DSJW - 1) -# else -# define FDCAN3_DTSEG1 1 -# define FDCAN3_DTSEG2 1 -# define FDCAN3_DBRP 1 -# define FDCAN3_DSJW 1 -# endif /* CONFIG_STM32_FDCAN3_FD_BRS */ - -# if FDCAN3_DTSEG1 > FDCAN_DBTP_DTSEG1_MAX -# error Invalid FDCAN3 DTSEG1 -# endif -# if FDCAN3_DTSEG2 > FDCAN_DBTP_DTSEG2_MAX -# error Invalid FDCAN3 DTSEG2 -# endif -# if FDCAN3_DBRP > FDCAN_DBTP_DBRP_MAX -# error Invalid FDCAN3 DBRP -# endif -# if FDCAN3_DSJW > FDCAN_DBTP_DSJW_MAX -# error Invalid FDCAN3 DSJW -# endif - -/* FDCAN3 Message RAM Configuration *****************************************/ - -/* FDCAN3 Message RAM Layout */ - -# define FDCAN3_STDFILTER_INDEX 0 -# define FDCAN3_EXTFILTERS_INDEX (FDCAN3_STDFILTER_INDEX + FDCAN3_STDFILTER_WORDS) -# define FDCAN3_RXFIFO0_INDEX (FDCAN3_EXTFILTERS_INDEX + FDCAN3_EXTFILTER_WORDS) -# define FDCAN3_RXFIFO1_INDEX (FDCAN3_RXFIFO0_INDEX + FDCAN3_RXFIFO0_WORDS) -# define FDCAN3_TXEVENTFIFO_INDEX (FDCAN3_RXFIFO1_INDEX + FDCAN3_RXFIFO1_WORDS) -# define FDCAN3_TXFIFOQ_INDEX (FDCAN3_TXEVENTFIFO_INDEX + FDCAN3_TXEVENTFIFO_WORDS) -# define FDCAN3_MSGRAM_WORDS (FDCAN3_TXFIFOQ_INDEX + FDCAN3_TXFIFIOQ_WORDS) - -#endif /* CONFIG_STM32_FDCAN3 */ - -/* Loopback mode */ - -#undef STM32_FDCAN_LOOPBACK -#if defined(CONFIG_STM32_FDCAN1_LOOPBACK) || \ - defined(CONFIG_STM32_FDCAN2_LOOPBACK) || \ - defined(CONFIG_STM32_FDCAN3_LOOPBACK) -# define STM32_FDCAN_LOOPBACK 1 -#endif - -/* Interrupts ***************************************************************/ - -/* Common interrupts - * - * FDCAN_INT_TSW - Timestamp Wraparound - * FDCAN_INT_MRAF - Message RAM Access Failure - * FDCAN_INT_TOO - Timeout Occurred - * FDCAN_INT_ELO - Error Logging Overflow - * FDCAN_INT_EP - Error Passive - * FDCAN_INT_EW - Warning Status - * FDCAN_INT_BO - Bus_Off Status - * FDCAN_INT_WDI - Watchdog Interrupt - * FDCAN_INT_PEA - Protocol Error in Arbritration Phase - * FDCAN_INT_PED - Protocol Error in Data Phase - */ - -#define FDCAN_CMNERR_INTS (FDCAN_INT_MRAF | FDCAN_INT_TOO | FDCAN_INT_EP | \ - FDCAN_INT_BO | FDCAN_INT_WDI | FDCAN_INT_PEA | \ - FDCAN_INT_PED) - -/* RXFIFO mode interrupts - * - * FDCAN_INT_RF0N - Receive FIFO 0 New Message - * FDCAN_INT_RF0F - Receive FIFO 0 Full - * FDCAN_INT_RF0L - Receive FIFO 0 Message Lost - * FDCAN_INT_RF1N - Receive FIFO 1 New Message - * FDCAN_INT_RF1F - Receive FIFO 1 Full - * FDCAN_INT_RF1L - Receive FIFO 1 Message Lost - * FDCAN_INT_HPM - High Priority Message Received - * - */ - -#define FDCAN_RXFIFO0_INTS (FDCAN_INT_RF0N | FDCAN_INT_RF0L) -#define FDCAN_RXFIFO1_INTS (FDCAN_INT_RF1N | FDCAN_INT_RF1L) - -#define FDCAN_RXERR_INTS (FDCAN_INT_RF0L | FDCAN_INT_RF1L) - -/* TX FIFOQ mode interrupts - * - * FDCAN_INT_TFE - Tx FIFO Empty - * - * TX Event FIFO interrupts - * - * FDCAN_INT_TEFN - Tx Event FIFO New Entry - * FDCAN_INT_TEFF - Tx Event FIFO Full - * FDCAN_INT_TEFL - Tx Event FIFO Element Lost - * - * Mode-independent TX-related interrupts - * - * FDCAN_INT_TC - Transmission Completed - * FDCAN_INT_TCF - Transmission Cancellation Finished - */ - -#define FDCAN_TXCOMMON_INTS (FDCAN_INT_TC | FDCAN_INT_TCF) -#define FDCAN_TXFIFOQ_INTS (FDCAN_INT_TFE | FDCAN_TXCOMMON_INTS) -#define FDCAN_TXEVFIFO_INTS (FDCAN_INT_TEFN | FDCAN_INT_TEFF | \ - FDCAN_INT_TEFL) - -#define FDCAN_TXERR_INTS (FDCAN_INT_TEFL | FDCAN_INT_PEA | FDCAN_INT_PED) - -/* Common-, TX- and RX-Error-Mask */ - -#define FDCAN_ANYERR_INTS (FDCAN_CMNERR_INTS | FDCAN_RXERR_INTS | FDCAN_TXERR_INTS) - -/* Convenience macro for clearing all interrupts */ - -#define FDCAN_INT_ALL 0x3fcfffff - -/* Debug ********************************************************************/ - -/* Debug configurations that may be enabled just for testing FDCAN */ - -#ifndef CONFIG_DEBUG_NET_INFO -# undef CONFIG_STM32_FDCAN_REGDEBUG -#endif - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/* CAN frame format */ - -enum stm32_frameformat_e -{ - FDCAN_ISO11898_1_FORMAT = 0, /* Frame format according to ISO11898-1 */ - FDCAN_NONISO_BOSCH_V1_FORMAT = 1 /* Frame format according to Bosch CAN FD V1.0 */ -}; - -/* CAN mode of operation */ - -enum stm32_canmode_e -{ - FDCAN_CLASSIC_MODE = 0, /* Classic CAN operation */ -#ifdef CONFIG_NET_CAN_CANFD - FDCAN_FD_MODE = 1, /* CAN FD operation */ - FDCAN_FD_BRS_MODE = 2 /* CAN FD operation with bit rate switching */ -#endif -}; - -/* CAN driver state */ - -enum can_state_s -{ - FDCAN_STATE_UNINIT = 0, /* Not yet initialized */ - FDCAN_STATE_RESET, /* Initialized, reset state */ - FDCAN_STATE_SETUP, /* fdcan_setup() has been called */ - FDCAN_STATE_DISABLED /* Disabled by a fdcan_shutdown() */ -}; - -/* This structure describes the FDCAN message RAM layout */ - -struct stm32_msgram_s -{ - volatile uint32_t *stdfilters; /* Standard filters */ - volatile uint32_t *extfilters; /* Extended filters */ - volatile uint32_t *rxfifo0; /* RX FIFO0 */ - volatile uint32_t *rxfifo1; /* RX FIFO1 */ - volatile uint32_t *txeventfifo; /* TX event FIFO */ - volatile uint32_t *txfifoq; /* TX FIFO queue */ -}; - -/* This structure provides the constant configuration of a FDCAN peripheral */ - -struct stm32_config_s -{ - uint32_t rxpinset; /* RX pin configuration */ - uint32_t txpinset; /* TX pin configuration */ - uintptr_t base; /* Base address of the FDCAN registers */ - uint32_t baud; /* Configured baud */ - uint32_t nbtp; /* Nominal bit timing/prescaler register setting */ - uint32_t dbtp; /* Data bit timing/prescaler register setting */ - uint8_t port; /* FDCAN port number (1 or 2) */ - uint8_t irq0; /* FDCAN peripheral IRQ number for interrupt line 0 */ - uint8_t irq1; /* FDCAN peripheral IRQ number for interrupt line 1 */ - uint8_t mode; /* See enum stm32_canmode_e */ - uint8_t format; /* See enum stm32_frameformat_e */ - uint8_t nstdfilters; /* Number of standard filters */ - uint8_t nextfilters; /* Number of extended filters */ - uint8_t nrxfifo0; /* Number of RX FIFO0 elements */ - uint8_t nrxfifo1; /* Number of RX FIFO1 elements */ - uint8_t ntxeventfifo; /* Number of TXevent FIFO elements */ - uint8_t ntxfifoq; /* Number of TX FIFO queue elements */ - uint8_t rxfifo0esize; /* RX FIFO0 element size (words) */ - uint8_t rxfifo1esize; /* RX FIFO1 element size (words) */ - uint8_t txeventesize; /* TXevent element size (words) */ - uint8_t txbufferesize; /* TX buffer element size (words) */ -#ifdef STM32_FDCAN_LOOPBACK - bool loopback; /* True: Loopback mode */ -#endif - - /* FDCAN message RAM layout */ - - struct stm32_msgram_s msgram; -}; - -/* This structure provides the current state of a FDCAN peripheral */ - -struct stm32_fdcan_s -{ - /* The constant configuration */ - - const struct stm32_config_s *config; - - uint8_t state; /* See enum can_state_s */ -#ifdef CONFIG_NET_CAN_EXTID - uint8_t nextalloc; /* Number of allocated extended filters */ -#endif - uint8_t nstdalloc; /* Number of allocated standard filters */ - uint32_t nbtp; /* Current nominal bit timing */ - uint32_t dbtp; /* Current data bit timing */ - -#ifdef CONFIG_NET_CAN_EXTID - uint32_t extfilters[2]; /* Extended filter bit allocator. 2*32=64 */ -#endif - uint32_t stdfilters[4]; /* Standard filter bit allocator. 4*32=128 */ - -#ifdef CONFIG_STM32_FDCAN_REGDEBUG - uintptr_t regaddr; /* Last register address read */ - uint32_t regval; /* Last value read from the register */ - unsigned int count; /* Number of times that the value was read */ -#endif - - bool bifup; /* true:ifup false:ifdown */ - struct net_driver_s dev; /* Interface understood by the network */ - - struct work_s irqwork; /* For deferring interrupt work to the wq */ - struct work_s pollwork; /* For deferring poll work to the work wq */ - - /* A pointers to the list of TX/RX descriptors */ - - struct can_frame *txdesc; - struct can_frame *rxdesc; - - /* TX/RX pool */ - -#ifdef CONFIG_NET_CAN_CANFD - uint8_t tx_pool[sizeof(struct canfd_frame)*POOL_SIZE]; - uint8_t rx_pool[sizeof(struct canfd_frame)*POOL_SIZE]; -#else - uint8_t tx_pool[sizeof(struct can_frame)*POOL_SIZE]; - uint8_t rx_pool[sizeof(struct can_frame)*POOL_SIZE]; -#endif -}; - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -/* FDCAN Register access */ - -static uint32_t fdcan_getreg(struct stm32_fdcan_s *priv, int offset); -static void fdcan_putreg(struct stm32_fdcan_s *priv, int offset, - uint32_t regval); -#ifdef CONFIG_STM32_FDCAN_REGDEBUG -static void fdcan_dumpregs(struct stm32_fdcan_s *priv, - const char *msg); -static void fdcan_dumprxregs(struct stm32_fdcan_s *priv, - const char *msg); -static void fdcan_dumptxregs(struct stm32_fdcan_s *priv, - const char *msg); -static void fdcan_dumpramlayout(struct stm32_fdcan_s *priv); -#else -# define fdcan_dumpregs(priv,msg) -# define fdcan_dumprxregs(priv,msg) -# define fdcan_dumptxregs(priv,msg) -# define fdcan_dumpramlayout(priv) -#endif - -/* CAN interrupt enable functions */ - -static void fdcan_rx0int(struct stm32_fdcan_s *priv, bool enable); -static void fdcan_rx1int(struct stm32_fdcan_s *priv, bool enable); -static void fdcan_txint(struct stm32_fdcan_s *priv, bool enable); -#ifdef CONFIG_NET_CAN_ERRORS -static void fdcan_errint(struct stm32_fdcan_s *priv, bool enable); -#endif - -/* Common TX logic */ - -static int fdcan_send(struct stm32_fdcan_s *priv); -static bool fdcan_txready(struct stm32_fdcan_s *priv); -static int fdcan_txpoll(struct net_driver_s *dev); - -/* CAN RX interrupt handling */ - -static void fdcan_rx0interrupt_work(void *arg); -static void fdcan_rx1interrupt_work(void *arg); - -/* CAN TX interrupt handling */ - -static void fdcan_txdone_work(void *arg); -static void fdcan_txdone(struct stm32_fdcan_s *priv); - -#ifdef CONFIG_NET_CAN_ERRORS -/* CAN errors interrupt handling */ - -static void fdcan_error_work(void *arg); -#endif - -/* FDCAN interrupt handling */ - -#ifdef CONFIG_NET_CAN_ERRORS -static void fdcan_error(struct stm32_fdcan_s *priv, uint32_t status); -#endif -static void fdcan_receive(struct stm32_fdcan_s *priv, - volatile uint32_t *rxbuffer, - unsigned long nwords); -static int fdcan_interrupt(int irq, void *context, void *arg); - -/* Initialization */ - -static void fdcan_reset(struct stm32_fdcan_s *priv); -static int fdcan_setup(struct stm32_fdcan_s *priv); -static void fdcan_shutdown(struct stm32_fdcan_s *priv); - -/* FDCAN helpers */ - -#if 0 /* not used for now */ -static int -fdcan_start_busoff_recovery_sequence(struct stm32_fdcan_s *priv); -#endif - -/* Hardware initialization */ - -static int fdcan_hw_initialize(struct stm32_fdcan_s *priv); - -/* NuttX callback functions */ - -static int fdcan_ifup(struct net_driver_s *dev); -static int fdcan_ifdown(struct net_driver_s *dev); - -static void fdcan_txavail_work(void *arg); -static int fdcan_txavail(struct net_driver_s *dev); - -#ifdef CONFIG_NETDEV_IOCTL -static int fdcan_netdev_ioctl(struct net_driver_s *dev, int cmd, - unsigned long arg); -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -#ifdef CONFIG_STM32_FDCAN1 -/* Message RAM allocation */ - -/* Constant configuration */ - -static const struct stm32_config_s g_fdcan1const = -{ - .rxpinset = GPIO_FDCAN1_RX, - .txpinset = GPIO_FDCAN1_TX, - .base = STM32_FDCAN1_BASE, - .baud = CONFIG_STM32_FDCAN1_BITRATE, - .nbtp = FDCAN_NBTP_NBRP(FDCAN1_NBRP) | - FDCAN_NBTP_NTSEG1(FDCAN1_NTSEG1) | - FDCAN_NBTP_NTSEG2(FDCAN1_NTSEG2) | - FDCAN_NBTP_NSJW(FDCAN1_NSJW), - .dbtp = FDCAN_DBTP_DBRP(FDCAN1_DBRP) | - FDCAN_DBTP_DTSEG1(FDCAN1_DTSEG1) | - FDCAN_DBTP_DTSEG2(FDCAN1_DTSEG2) | - FDCAN_DBTP_DSJW(FDCAN1_DSJW), - .port = 1, - .irq0 = STM32_IRQ_FDCAN1_0, - .irq1 = STM32_IRQ_FDCAN1_1, -#if defined(CONFIG_STM32_FDCAN1_CLASSIC) - .mode = FDCAN_CLASSIC_MODE, -#elif defined(CONFIG_STM32_FDCAN1_FD) - .mode = FDCAN_FD_MODE, -#else - .mode = FDCAN_FD_BRS_MODE, -#endif -#if defined(CONFIG_STM32_FDCAN1_NONISO_FORMAT) - .format = FDCAN_NONISO_BOSCH_V1_FORMAT, -#else - .format = FDCAN_ISO11898_1_FORMAT, -#endif - .nstdfilters = FDCAN1_STDFILTER_SIZE, - .nextfilters = FDCAN1_EXTFILTER_SIZE, - .nrxfifo0 = FDCAN1_RXFIFO0_SIZE, - .nrxfifo1 = FDCAN1_RXFIFO1_SIZE, - .ntxeventfifo = FDCAN1_TXEVENTFIFO_SIZE, - .ntxfifoq = FDCAN1_TXFIFIOQ_SIZE, - .rxfifo0esize = (FDCAN1_RXFIFO0_WORDS / FDCAN1_RXFIFO0_SIZE), - .rxfifo1esize = (FDCAN1_RXFIFO1_WORDS / FDCAN1_RXFIFO1_SIZE), - .txeventesize = (FDCAN1_TXEVENTFIFO_WORDS / FDCAN1_TXEVENTFIFO_SIZE), - .txbufferesize = (FDCAN1_TXFIFIOQ_WORDS / FDCAN1_TXFIFIOQ_SIZE), - -#ifdef CONFIG_STM32_FDCAN1_LOOPBACK - .loopback = true, -#endif - - /* FDCAN1 Message RAM */ - - .msgram = - { - (uint32_t *)(STM32_CANRAM1_BASE + (FDCAN1_STDFILTER_INDEX << 2)), - (uint32_t *)(STM32_CANRAM1_BASE + (FDCAN1_EXTFILTERS_INDEX << 2)), - (uint32_t *)(STM32_CANRAM1_BASE + (FDCAN1_RXFIFO0_INDEX << 2)), - (uint32_t *)(STM32_CANRAM1_BASE + (FDCAN1_RXFIFO1_INDEX << 2)), - (uint32_t *)(STM32_CANRAM1_BASE + (FDCAN1_TXEVENTFIFO_INDEX << 2)), - (uint32_t *)(STM32_CANRAM1_BASE + (FDCAN1_TXFIFOQ_INDEX << 2)) - } -}; - -/* FDCAN1 variable driver state */ - -static struct stm32_fdcan_s g_fdcan1priv; - -#endif /* CONFIG_STM32_FDCAN1 */ - -#ifdef CONFIG_STM32_FDCAN2 -/* FDCAN2 message RAM allocation */ - -/* FDCAN2 constant configuration */ - -static const struct stm32_config_s g_fdcan2const = -{ - .rxpinset = GPIO_FDCAN2_RX, - .txpinset = GPIO_FDCAN2_TX, - .base = STM32_FDCAN2_BASE, - .baud = CONFIG_STM32_FDCAN2_BITRATE, - .nbtp = FDCAN_NBTP_NBRP(FDCAN2_NBRP) | - FDCAN_NBTP_NTSEG1(FDCAN2_NTSEG1) | - FDCAN_NBTP_NTSEG2(FDCAN2_NTSEG2) | - FDCAN_NBTP_NSJW(FDCAN2_NSJW), - .dbtp = FDCAN_DBTP_DBRP(FDCAN2_DBRP) | - FDCAN_DBTP_DTSEG1(FDCAN2_DTSEG1) | - FDCAN_DBTP_DTSEG2(FDCAN2_DTSEG2) | - FDCAN_DBTP_DSJW(FDCAN2_DSJW), - .port = 2, - .irq0 = STM32_IRQ_FDCAN2_0, - .irq1 = STM32_IRQ_FDCAN2_1, -#if defined(CONFIG_STM32_FDCAN2_CLASSIC) - .mode = FDCAN_CLASSIC_MODE, -#elif defined(CONFIG_STM32_FDCAN2_FD) - .mode = FDCAN_FD_MODE, -#else - .mode = FDCAN_FD_BRS_MODE, -#endif -#if defined(CONFIG_STM32_FDCAN2_NONISO_FORMAT) - .format = FDCAN_NONISO_BOSCH_V1_FORMAT, -#else - .format = FDCAN_ISO11898_1_FORMAT, -#endif - .nstdfilters = FDCAN2_STDFILTER_SIZE, - .nextfilters = FDCAN2_EXTFILTER_SIZE, - .nrxfifo0 = FDCAN2_RXFIFO0_SIZE, - .nrxfifo1 = FDCAN2_RXFIFO1_SIZE, - .ntxeventfifo = FDCAN2_TXEVENTFIFO_SIZE, - .ntxfifoq = FDCAN2_TXFIFIOQ_SIZE, - .rxfifo0esize = (FDCAN2_RXFIFO0_WORDS / FDCAN2_RXFIFO0_SIZE), - .rxfifo1esize = (FDCAN2_RXFIFO1_WORDS / FDCAN2_RXFIFO1_SIZE), - .txeventesize = (FDCAN2_TXEVENTFIFO_WORDS / FDCAN2_TXEVENTFIFO_SIZE), - .txbufferesize = (FDCAN2_TXFIFIOQ_WORDS / FDCAN2_TXFIFIOQ_SIZE), - -#ifdef CONFIG_STM32_FDCAN2_LOOPBACK - .loopback = true, -#endif - - /* FDCAN2 Message RAM */ - - .msgram = - { - (uint32_t *)(STM32_CANRAM2_BASE + (FDCAN2_STDFILTER_INDEX << 2)), - (uint32_t *)(STM32_CANRAM2_BASE + (FDCAN2_EXTFILTERS_INDEX << 2)), - (uint32_t *)(STM32_CANRAM2_BASE + (FDCAN2_RXFIFO0_INDEX << 2)), - (uint32_t *)(STM32_CANRAM2_BASE + (FDCAN2_RXFIFO1_INDEX << 2)), - (uint32_t *)(STM32_CANRAM2_BASE + (FDCAN2_TXEVENTFIFO_INDEX << 2)), - (uint32_t *)(STM32_CANRAM2_BASE + (FDCAN2_TXFIFOQ_INDEX << 2)) - } -}; - -/* FDCAN2 variable driver state */ - -static struct stm32_fdcan_s g_fdcan2priv; - -#endif /* CONFIG_STM32_FDCAN2 */ - -#ifdef CONFIG_STM32_FDCAN3 -/* FDCAN3 message RAM allocation */ - -/* FDCAN3 constant configuration */ - -static const struct stm32_config_s g_fdcan3const = -{ - .rxpinset = GPIO_FDCAN3_RX, - .txpinset = GPIO_FDCAN3_TX, - .base = STM32_FDCAN3_BASE, - .baud = CONFIG_STM32_FDCAN3_BITRATE, - .nbtp = FDCAN_NBTP_NBRP(FDCAN3_NBRP) | - FDCAN_NBTP_NTSEG1(FDCAN3_NTSEG1) | - FDCAN_NBTP_NTSEG2(FDCAN3_NTSEG2) | - FDCAN_NBTP_NSJW(FDCAN3_NSJW), - .dbtp = FDCAN_DBTP_DBRP(FDCAN3_DBRP) | - FDCAN_DBTP_DTSEG1(FDCAN3_DTSEG1) | - FDCAN_DBTP_DTSEG2(FDCAN3_DTSEG2) | - FDCAN_DBTP_DSJW(FDCAN3_DSJW), - .port = 3, - .irq0 = STM32_IRQ_FDCAN3_0, - .irq1 = STM32_IRQ_FDCAN3_1, -#if defined(CONFIG_STM32_FDCAN3_CLASSIC) - .mode = FDCAN_CLASSIC_MODE, -#elif defined(CONFIG_STM32_FDCAN3_FD) - .mode = FDCAN_FD_MODE, -#else - .mode = FDCAN_FD_BRS_MODE, -#endif -#if defined(CONFIG_STM32_FDCAN3_NONISO_FORMAT) - .format = FDCAN_NONISO_BOSCH_V1_FORMAT, -#else - .format = FDCAN_ISO11898_1_FORMAT, -#endif - .nstdfilters = FDCAN3_STDFILTER_SIZE, - .nextfilters = FDCAN3_EXTFILTER_SIZE, - .nrxfifo0 = FDCAN3_RXFIFO0_SIZE, - .nrxfifo1 = FDCAN3_RXFIFO1_SIZE, - .ntxeventfifo = FDCAN3_TXEVENTFIFO_SIZE, - .ntxfifoq = FDCAN3_TXFIFIOQ_SIZE, - .rxfifo0esize = (FDCAN3_RXFIFO0_WORDS / FDCAN3_RXFIFO0_SIZE), - .rxfifo1esize = (FDCAN3_RXFIFO1_WORDS / FDCAN3_RXFIFO1_SIZE), - .txeventesize = (FDCAN3_TXEVENTFIFO_WORDS / FDCAN3_TXEVENTFIFO_SIZE), - .txbufferesize = (FDCAN3_TXFIFIOQ_WORDS / FDCAN3_TXFIFIOQ_SIZE), - -#ifdef CONFIG_STM32_FDCAN3_LOOPBACK - .loopback = true, -#endif - - /* FDCAN3 Message RAM */ - - .msgram = - { - (uint32_t *)(STM32_CANRAM3_BASE + (FDCAN3_STDFILTER_INDEX << 2)), - (uint32_t *)(STM32_CANRAM3_BASE + (FDCAN3_EXTFILTERS_INDEX << 2)), - (uint32_t *)(STM32_CANRAM3_BASE + (FDCAN3_RXFIFO0_INDEX << 2)), - (uint32_t *)(STM32_CANRAM3_BASE + (FDCAN3_RXFIFO1_INDEX << 2)), - (uint32_t *)(STM32_CANRAM3_BASE + (FDCAN3_TXEVENTFIFO_INDEX << 2)), - (uint32_t *)(STM32_CANRAM3_BASE + (FDCAN3_TXFIFOQ_INDEX << 2)) - } -}; - -/* FDCAN3 variable driver state */ - -static struct stm32_fdcan_s g_fdcan3priv; - -#endif /* CONFIG_STM32_FDCAN3 */ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: fdcan_getreg - * - * Description: - * Read the value of a FDCAN register. - * - * Input Parameters: - * priv - A reference to the FDCAN peripheral state - * offset - The offset to the register to read - * - * Returned Value: - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_FDCAN_REGDEBUG -static uint32_t fdcan_getreg(struct stm32_fdcan_s *priv, int offset) -{ - const struct stm32_config_s *config = priv->config; - uintptr_t regaddr = 0; - uint32_t regval = 0; - - /* Read the value from the register */ - - regaddr = config->base + offset; - regval = getreg32(regaddr); - - /* Is this the same value that we read from the same register last time? - * Are we polling the register? If so, suppress some of the output. - */ - - if (regaddr == priv->regaddr && regval == priv->regval) - { - if (priv->count == 0xffffffff || ++priv->count > 3) - { - if (priv->count == 4) - { - ninfo("...\n"); - } - - return regval; - } - } - - /* No this is a new address or value */ - - else - { - /* Did we print "..." for the previous value? */ - - if (priv->count > 3) - { - /* Yes.. then show how many times the value repeated */ - - ninfo("[repeats %d more times]\n", priv->count - 3); - } - - /* Save the new address, value, and count */ - - priv->regaddr = regaddr; - priv->regval = regval; - priv->count = 1; - } - - /* Show the register value read */ - - ninfo("%08" PRIx32 "->%08" PRIx32 "\n", regaddr, regval); - return regval; -} - -#else -static uint32_t fdcan_getreg(struct stm32_fdcan_s *priv, int offset) -{ - const struct stm32_config_s *config = priv->config; - return getreg32(config->base + offset); -} - -#endif - -/**************************************************************************** - * Name: fdcan_putreg - * - * Description: - * Set the value of a FDCAN register. - * - * Input Parameters: - * priv - A reference to the FDCAN peripheral state - * offset - The offset to the register to write - * regval - The value to write to the register - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_FDCAN_REGDEBUG -static void fdcan_putreg(struct stm32_fdcan_s *priv, int offset, - uint32_t regval) -{ - const struct stm32_config_s *config = priv->config; - uintptr_t regaddr = config->base + offset; - - /* Show the register value being written */ - - ninfo("%08" PRIx32 "->%08" PRIx32 "\n", regaddr, regval); - - /* Write the value */ - - putreg32(regval, regaddr); -} - -#else -static void fdcan_putreg(struct stm32_fdcan_s *priv, int offset, - uint32_t regval) -{ - const struct stm32_config_s *config = priv->config; - putreg32(regval, config->base + offset); -} - -#endif - -/**************************************************************************** - * Name: fdcan_dumpctrlregs - * - * Description: - * Dump the contents of all CAN control registers - * - * Input Parameters: - * priv - A reference to the CAN block status - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_FDCAN_REGDEBUG -static void fdcan_dumpregs(struct stm32_fdcan_s *priv, - const char *msg) -{ - const struct stm32_config_s *config = priv->config; - - ninfo("CAN%d Control and Status Registers: %s\n", config->port, msg); - ninfo(" Base: %08" PRIx32 "\n", config->base); - - /* CAN control and status registers */ - - ninfo(" CCCR: %08" PRIx32 " TEST: %08" PRIx32 "\n", - getreg32(config->base + STM32_FDCAN_CCCR_OFFSET), - getreg32(config->base + STM32_FDCAN_TEST_OFFSET)); - - ninfo(" NBTP: %08" PRIx32 " DBTP: %08" PRIx32 "\n", - getreg32(config->base + STM32_FDCAN_NBTP_OFFSET), - getreg32(config->base + STM32_FDCAN_DBTP_OFFSET)); - - ninfo(" IE: %08" PRIx32 " TIE: %08" PRIx32 "\n", - getreg32(config->base + STM32_FDCAN_IE_OFFSET), - getreg32(config->base + STM32_FDCAN_TXBTIE_OFFSET)); - - ninfo(" ILE: %08" PRIx32 " ILS: %08" PRIx32 "\n", - getreg32(config->base + STM32_FDCAN_ILE_OFFSET), - getreg32(config->base + STM32_FDCAN_ILS_OFFSET)); - - ninfo(" TXBC: %08" PRIx32 "\n", - getreg32(config->base + STM32_FDCAN_TXBC_OFFSET)); -} -#endif - -/**************************************************************************** - * Name: fdcan_dumprxregs - * - * Description: - * Dump the contents of all Rx status registers - * - * Input Parameters: - * priv - A reference to the CAN block status - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_FDCAN_REGDEBUG -static void fdcan_dumprxregs(struct stm32_fdcan_s *priv, - const char *msg) -{ - const struct stm32_config_s *config = priv->config; - - ninfo("CAN%d Rx Registers: %s\n", config->port, msg); - ninfo(" Base: %08" PRIx32 "\n", config->base); - - ninfo(" PSR: %08" PRIx32 " ECR: %08" PRIx32 - " HPMS: %08" PRIx32 "\n", - getreg32(config->base + STM32_FDCAN_PSR_OFFSET), - getreg32(config->base + STM32_FDCAN_ECR_OFFSET), - getreg32(config->base + STM32_FDCAN_HPMS_OFFSET)); - - ninfo(" RXF0S: %08" PRIx32 " RXF0A: %08" PRIx32 "\n", - getreg32(config->base + STM32_FDCAN_RXF0S_OFFSET), - getreg32(config->base + STM32_FDCAN_RXF0A_OFFSET)); - - ninfo(" RXF1S: %08" PRIx32 " RXF1A: %08" PRIx32 "\n", - getreg32(config->base + STM32_FDCAN_RXF1S_OFFSET), - getreg32(config->base + STM32_FDCAN_RXF1A_OFFSET)); - - ninfo(" IR: %08" PRIx32 " IE: %08" PRIx32 "\n", - getreg32(config->base + STM32_FDCAN_IR_OFFSET), - getreg32(config->base + STM32_FDCAN_IE_OFFSET)); -} -#endif - -/**************************************************************************** - * Name: fdcan_dumptxregs - * - * Description: - * Dump the contents of all Tx buffer registers - * - * Input Parameters: - * priv - A reference to the CAN block status - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_FDCAN_REGDEBUG -static void fdcan_dumptxregs(struct stm32_fdcan_s *priv, - const char *msg) -{ - const struct stm32_config_s *config = priv->config; - - ninfo("CAN%d Tx Registers: %s\n", config->port, msg); - ninfo(" Base: %08" PRIx32 "\n", config->base); - - ninfo(" PSR: %08" PRIx32 " ECR: %08" PRIx32 "\n", - getreg32(config->base + STM32_FDCAN_PSR_OFFSET), - getreg32(config->base + STM32_FDCAN_ECR_OFFSET)); - - ninfo(" TXQFS: %08" PRIx32 " TXBAR: %08" PRIx32 - " TXBRP: %08" PRIx32 "\n", - getreg32(config->base + STM32_FDCAN_TXFQS_OFFSET), - getreg32(config->base + STM32_FDCAN_TXBAR_OFFSET), - getreg32(config->base + STM32_FDCAN_TXBRP_OFFSET)); - - ninfo(" TXBTO: %08" PRIx32 " TXBCR: %08" PRIx32 "\n", - getreg32(config->base + STM32_FDCAN_TXBTO_OFFSET), - getreg32(config->base + STM32_FDCAN_TXBCR_OFFSET)); - - ninfo(" TXEFS: %08" PRIx32 " TXEFA: %08" PRIx32 "\n", - getreg32(config->base + STM32_FDCAN_TXEFS_OFFSET), - getreg32(config->base + STM32_FDCAN_TXEFA_OFFSET)); - - ninfo(" IR: %08" PRIx32 " IE: %08" PRIx32 - " TIE: %08" PRIx32 "\n", - getreg32(config->base + STM32_FDCAN_IR_OFFSET), - getreg32(config->base + STM32_FDCAN_IE_OFFSET), - getreg32(config->base + STM32_FDCAN_TXBTIE_OFFSET)); -} -#endif - -/**************************************************************************** - * Name: fdcan_dumpramlayout - * - * Description: - * Print the layout of the message RAM - * - * Input Parameters: - * priv - A reference to the CAN block status - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_FDCAN_REGDEBUG -static void fdcan_dumpramlayout(struct stm32_fdcan_s *priv) -{ - const struct stm32_config_s *config = priv->config; - - ninfo(" ******* FDCAN%d Message RAM layout *******\n", config->port); - ninfo(" Start # Elmnt Elmnt size (words)\n"); - - if (config->nstdfilters > 0) - { - ninfo("STD filters %p %4d %2d\n", - config->msgram.stdfilters, - config->nstdfilters, - 1); - } - - if (config->nextfilters > 0) - { - ninfo("EXT filters %p %4d %2d\n", - config->msgram.extfilters, - config->nextfilters, - 2); - } - - if (config->nrxfifo0 > 0) - { - ninfo("RX FIFO 0 %p %4d %2d\n", - config->msgram.rxfifo0, - config->nrxfifo0, - config->rxfifo0esize); - } - - if (config->nrxfifo1 > 0) - { - ninfo("RX FIFO 1 %p %4d %2d\n", - config->msgram.rxfifo1, - config->nrxfifo1, - config->rxfifo1esize); - } - - if (config->ntxeventfifo > 0) - { - ninfo("TX EVENT %p %4d %2d\n", - config->msgram.txeventfifo, - config->ntxeventfifo, - config->txeventesize); - } - - if (config->ntxfifoq > 0) - { - ninfo("TX FIFO %p %4d %2d\n", - config->msgram.txfifoq, - config->ntxfifoq, - config->txbufferesize); - } -} -#endif - -/**************************************************************************** - * Name: fdcan_start_busoff_recovery_sequence - * - * Description: - * This function initiates the BUS-OFF recovery sequence. - * CAN Specification Rev. 2.0 or ISO11898-1:2015. - * According the STM32G4 datasheet section 44.3.2 Software initialziation. - * - * Input Parameters: - * priv - An instance of the FDCAN driver state structure. - * - * Returned Value: - * Zero (OK) is returned on success. Otherwise a negated errno value is - * returned to indicate the nature of the error. - * - ****************************************************************************/ - -#if 0 /* not used for now */ -static int -fdcan_start_busoff_recovery_sequence(struct stm32_fdcan_s *priv) -{ - uint32_t regval = 0; - - DEBUGASSERT(priv); - - /* Only start BUS-OFF recovery if we are in BUS-OFF state */ - - regval = fdcan_getreg(priv, STM32_FDCAN_PSR_OFFSET); - if ((regval & FDCAN_PSR_BO) == 0) - { - return -EPERM; - } - - /* Disable initialization mode to issue the recovery sequence */ - - regval = fdcan_getreg(priv, STM32_FDCAN_CCCR_OFFSET); - regval &= ~FDCAN_CCCR_INIT; - fdcan_putreg(priv, STM32_FDCAN_CCCR_OFFSET, regval); - - return OK; -} -#endif - -/**************************************************************************** - * Name: fdcan_reset - * - * Description: - * Reset the FDCAN device. Called early to initialize the hardware. This - * function is called, before fdcan_setup() and on error conditions. - * - * Input Parameters: - * dev - An instance of the "upper half" can driver state structure. - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void fdcan_reset(struct stm32_fdcan_s *priv) -{ - const struct stm32_config_s *config = NULL; - uint32_t regval = 0; - irqstate_t flags; - - DEBUGASSERT(priv); - config = priv->config; - DEBUGASSERT(config); - - ninfo("FDCAN%d\n", config->port); - UNUSED(config); - - /* Disable all interrupts */ - - fdcan_putreg(priv, STM32_FDCAN_IE_OFFSET, 0); - fdcan_putreg(priv, STM32_FDCAN_TXBTIE_OFFSET, 0); - - /* Make sure that all buffers are released. - * - * REVISIT: What if a thread is waiting for a buffer? The following - * will not wake up any waiting threads. - */ - - /* Disable the FDCAN controller. - * REVISIT: Should fdcan_shutdown() be called here? - */ - - /* Reset the FD CAN. - * REVISIT: Since there is only a single reset for both FDCAN - * controllers, do we really want to use the RCC reset here? - * This will nuke operation of the second controller if another - * device is registered. - */ - - flags = enter_critical_section(); - regval = getreg32(STM32_RCC_APB1RSTR1); - regval |= RCC_APB1RSTR1_FDCANRST; - putreg32(regval, STM32_RCC_APB1RSTR1); - - regval &= ~RCC_APB1RSTR1_FDCANRST; - putreg32(regval, STM32_RCC_APB1RSTR1); - leave_critical_section(flags); - - priv->state = FDCAN_STATE_RESET; -} - -/**************************************************************************** - * Name: fdcan_setup - * - * Description: - * Configure the FDCAN. This method is called the first time that the FDCAN - * device is opened. This will occur when the port is first opened. - * This setup includes configuring and attaching FDCAN interrupts. - * All FDCAN interrupts are disabled upon return. - * - * Input Parameters: - * dev - An instance of the "upper half" can driver state structure. - * - * Returned Value: - * Zero on success; a negated errno on failure - * - ****************************************************************************/ - -static int fdcan_setup(struct stm32_fdcan_s *priv) -{ - const struct stm32_config_s *config = NULL; - int ret = 0; - - DEBUGASSERT(priv); - config = priv->config; - DEBUGASSERT(config); - - ninfo("FDCAN%d\n", config->port); - - /* FDCAN hardware initialization */ - - ret = fdcan_hw_initialize(priv); - if (ret < 0) - { - nerr("ERROR: FDCAN%d H/W initialization failed: %d\n", - config->port, ret); - return ret; - } - - fdcan_dumpregs(priv, "After hardware initialization"); - - /* Attach the FDCAN interrupt handlers */ - - ret = irq_attach(config->irq0, fdcan_interrupt, priv); - if (ret < 0) - { - nerr("ERROR: Failed to attach FDCAN%d line 0 IRQ (%d)", - config->port, config->irq0); - return ret; - } - - ret = irq_attach(config->irq1, fdcan_interrupt, priv); - if (ret < 0) - { - nerr("ERROR: Failed to attach FDCAN%d line 1 IRQ (%d)", - config->port, config->irq1); - return ret; - } - - priv->state = FDCAN_STATE_SETUP; - - /* Enable the interrupts at the NVIC (they are still disabled at the FDCAN - * peripheral). - */ - - up_enable_irq(config->irq0); - up_enable_irq(config->irq1); - - return OK; -} - -/**************************************************************************** - * Name: fdcan_shutdown - * - * Description: - * Disable the FDCAN. This method is called when the FDCAN device - * is closed. This method reverses the operation the setup method. - * - * Input Parameters: - * dev - An instance of the "upper half" can driver state structure. - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void fdcan_shutdown(struct stm32_fdcan_s *priv) -{ - const struct stm32_config_s *config = NULL; - uint32_t regval = 0; - - DEBUGASSERT(priv); - config = priv->config; - DEBUGASSERT(config); - - ninfo("FDCAN%d\n", config->port); - - /* Disable FDCAN interrupts at the NVIC */ - - up_disable_irq(config->irq0); - up_disable_irq(config->irq1); - - /* Disable all interrupts from the FDCAN peripheral */ - - fdcan_putreg(priv, STM32_FDCAN_IE_OFFSET, 0); - fdcan_putreg(priv, STM32_FDCAN_TXBTIE_OFFSET, 0); - - /* Detach the FDCAN interrupt handler */ - - irq_detach(config->irq0); - irq_detach(config->irq1); - - /* Disable device by setting the Clock Stop Request bit */ - - regval = fdcan_getreg(priv, STM32_FDCAN_CCCR_OFFSET); - regval |= FDCAN_CCCR_CSR; - fdcan_putreg(priv, STM32_FDCAN_CCCR_OFFSET, regval); - - /* Wait for Init and Clock Stop Acknowledge bits to verify - * device is in the powered down state - */ - - while ((fdcan_getreg(priv, STM32_FDCAN_CCCR_OFFSET) & FDCAN_CCCR_INIT) - == 0); - while ((fdcan_getreg(priv, STM32_FDCAN_CCCR_OFFSET) & FDCAN_CCCR_CSA) - == 0); - priv->state = FDCAN_STATE_DISABLED; -} - -/**************************************************************************** - * Name: fdcan_rx0int - * - * Description: - * Call to enable or disable RX0 interrupts. - * - * Input Parameters: - * priv - reference to the private CAN driver state structure - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void fdcan_rx0int(struct stm32_fdcan_s *priv, bool enable) -{ - const struct stm32_config_s *config = NULL; - uint32_t regval = 0; - - DEBUGASSERT(priv); - config = priv->config; - DEBUGASSERT(config); - - ninfo("CAN%" PRIu8 "RX0 enable: %d\n", config->port, enable); - - /* Enable/disable the FIFO 0 message pending interrupt */ - - regval = fdcan_getreg(priv, STM32_FDCAN_IE_OFFSET); - - if (enable) - { - regval |= FDCAN_RXFIFO0_INTS; - } - else - { - regval &= ~FDCAN_RXFIFO0_INTS; - } - - fdcan_putreg(priv, STM32_FDCAN_IE_OFFSET, regval); -} - -/**************************************************************************** - * Name: fdcan_rx1int - * - * Description: - * Call to enable or disable RX1 interrupts. - * - * Input Parameters: - * priv - reference to the private CAN driver state structure - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void fdcan_rx1int(struct stm32_fdcan_s *priv, bool enable) -{ - const struct stm32_config_s *config = NULL; - uint32_t regval = 0; - - DEBUGASSERT(priv); - config = priv->config; - DEBUGASSERT(config); - - ninfo("CAN%" PRIu8 "RX1 enable: %d\n", config->port, enable); - - /* Enable/disable the FIFO 1 message pending interrupt */ - - regval = fdcan_getreg(priv, STM32_FDCAN_IE_OFFSET); - - if (enable) - { - regval |= FDCAN_RXFIFO1_INTS; - } - else - { - regval &= ~FDCAN_RXFIFO1_INTS; - } - - fdcan_putreg(priv, STM32_FDCAN_IE_OFFSET, regval); -} - -/**************************************************************************** - * Name: fdcan_txint - * - * Description: - * Call to enable or disable TX interrupts. - * - * Input Parameters: - * dev - An instance of the "upper half" can driver state structure. - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void fdcan_txint(struct stm32_fdcan_s *priv, bool enable) -{ - const struct stm32_config_s *config = NULL; - uint32_t regval = 0; - - DEBUGASSERT(priv); - config = priv->config; - DEBUGASSERT(config); - - ninfo("CAN%" PRIu8 "TX enable: %d\n", config->port, enable); - - /* Enable/disable the receive interrupts */ - - regval = fdcan_getreg(priv, STM32_FDCAN_IE_OFFSET); - - if (enable) - { - regval |= FDCAN_TXFIFOQ_INTS; - } - else - { - regval &= ~FDCAN_TXFIFOQ_INTS; - } - - fdcan_putreg(priv, STM32_FDCAN_IE_OFFSET, regval); -} - -#ifdef CONFIG_NET_CAN_ERRORS -/**************************************************************************** - * Name: fdcan_txint - * - * Description: - * Call to enable or disable CAN SCE interrupts. - * - * Input Parameters: - * priv - reference to the private CAN driver state structure - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void fdcan_errint(struct stm32_fdcan_s *priv, bool enable) -{ - const struct stm32_config_s *config = NULL; - uint32_t regval = 0; - - DEBUGASSERT(priv); - config = priv->config; - DEBUGASSERT(config); - - ninfo("CAN%" PRIu8 "ERR enable: %d\n", config->port, enable); - - /* Enable/disable the transmit mailbox interrupt */ - - regval = fdcan_getreg(priv, STM32_FDCAN_IE_OFFSET); - if (enable) - { - regval |= FDCAN_ANYERR_INTS; - } - else - { - regval &= ~FDCAN_ANYERR_INTS; - } - - fdcan_putreg(priv, STM32_FDCAN_IE_OFFSET, regval); -} -#endif - -/**************************************************************************** - * Name: fdcan_send - * - * Description: - * Send one can message. - * - * One CAN-message consists of a maximum of 10 bytes. A message is - * composed of at least the first 2 bytes (when there are no data bytes). - * - * Byte 0: Bits 0-7: Bits 3-10 of the 11-bit CAN identifier - * Byte 1: Bits 5-7: Bits 0-2 of the 11-bit CAN identifier - * Bit 4: Remote Transmission Request (RTR) - * Bits 0-3: Data Length Code (DLC) - * Bytes 2-10: CAN data - * - * Input Parameters: - * dev - An instance of the "upper half" can driver state structure. - * - * Returned Value: - * Zero on success; a negated errno on failure - * - ****************************************************************************/ - -static int fdcan_send(struct stm32_fdcan_s *priv) -{ - const struct stm32_config_s *config = NULL; - volatile uint32_t *txbuffer = NULL; - const uint8_t *src = NULL; - uint32_t *dest = NULL; - uint32_t regval = 0; - unsigned int ndx = 0; - unsigned int nbytes = 0; - uint32_t wordbuffer = 0; - unsigned int i = 0; - - DEBUGASSERT(priv); - config = priv->config; - DEBUGASSERT(config); - - fdcan_dumptxregs(priv, "Before send"); - - /* That that FIFO elements were configured */ - - DEBUGASSERT(config->ntxfifoq > 0); - - /* Get our reserved Tx FIFO/queue put index */ - - regval = fdcan_getreg(priv, STM32_FDCAN_TXFQS_OFFSET); - DEBUGASSERT((regval & FDCAN_TXFQS_TFQF) == 0); - - ndx = (regval & FDCAN_TXFQS_TFQPI_MASK) >> FDCAN_TXFQS_TFQPI_SHIFT; - - /* And the TX buffer corresponding to this index */ - - txbuffer = (config->msgram.txfifoq + ndx * config->txbufferesize); - - /* Format the TX FIFOQ entry - * - * Format word T0: - * Transfer message ID (ID) - Value from message structure - * Remote Transmission Request (RTR) - Value from message structure - * Extended Identifier (XTD) - Depends on configuration. - * Error state indicator (ESI) - ESI bit in CAN FD - * - * Format word T1: - * Data Length Code (DLC) - Value from message structure - * Bit Rate Switch (BRS) - Bit rate switching for CAN FD - * FD format (FDF) - Frame transmitted in CAN FD format - * Event FIFO Control (EFC) - Do not store events. - * Message Marker (MM) - Always zero - */ - - txbuffer[0] = 0; - txbuffer[1] = 0; - - /* CAN 2.0 or CAN FD */ - - if (priv->dev.d_len == sizeof(struct can_frame)) - { - struct can_frame *frame = NULL; - - frame = (struct can_frame *)priv->dev.d_buf; - - ninfo("CAN%" PRIu8 " 2.0 ID: %" PRIu32 " DLC: %" PRIu8 "\n", - config->port, (uint32_t)frame->can_id, frame->can_dlc); - - /* Extended or standard ID */ - -#ifdef CONFIG_NET_CAN_EXTID - if ((frame->can_id & CAN_EFF_FLAG) != 0) - { - DEBUGASSERT((frame->can_id ^ CAN_EFF_FLAG) < (1 << 29)); - - txbuffer[0] |= BUFFER_R0_EXTID(frame->can_id) | BUFFER_R0_XTD; - } - else -#endif - { - DEBUGASSERT(frame->can_id < (1 << 11)); - - txbuffer[0] |= BUFFER_R0_STDID(frame->can_id); - } - - /* Set DLC */ - - txbuffer[1] |= BUFFER_R1_DLC(frame->can_dlc); - - /* Set flags */ - - if ((frame->can_id & CAN_RTR_FLAG) != 0) - { - txbuffer[0] |= BUFFER_R0_RTR; - } - - /* Reset CAN FD bits */ - - txbuffer[0] &= ~BUFFER_R0_ESI; - txbuffer[1] &= ~BUFFER_R1_FDF; - txbuffer[1] &= ~BUFFER_R1_BRS; - - /* Followed by the amount of data corresponding to the DLC (T2..) */ - - src = frame->data; - nbytes = frame->can_dlc; - } -#ifdef CONFIG_NET_CAN_CANFD - else /* CAN FD frame */ - { - struct canfd_frame *frame = (struct canfd_frame *)priv->dev.d_buf; - - frame = (struct canfd_frame *)priv->dev.d_buf; - - ninfo("CAN%" PRIu8 " FD ID: %" PRIu32 " len: %" PRIu8 "\n", - config->port, (uint32_t)frame->can_id, frame->len); - - /* Extended or standard ID */ - -#ifdef CONFIG_NET_CAN_EXTID - if ((frame->can_id & CAN_EFF_FLAG) != 0) - { - DEBUGASSERT(frame->can_id < (1 << 29)); - - txbuffer[0] |= BUFFER_R0_EXTID(frame->can_id) | BUFFER_R0_XTD; - } - else -#endif - { - DEBUGASSERT(frame->can_id < (1 << 11)); - - txbuffer[0] |= BUFFER_R0_STDID(frame->can_id); - } - - /* CANFD frame */ - - txbuffer[1] |= BUFFER_R1_FDF; - - /* Set DLC */ - - txbuffer[1] |= BUFFER_R1_DLC(g_len_to_can_dlc[frame->len]); - - /* Set flags */ - - if ((frame->can_id & CAN_RTR_FLAG) != 0) - { - txbuffer[0] |= BUFFER_R0_RTR; - } - - if ((frame->flags & CANFD_BRS) != 0) - { - txbuffer[1] |= BUFFER_R1_BRS; - } - - if ((frame->flags & CANFD_ESI) != 0) - { - txbuffer[0] |= BUFFER_R0_ESI; - } - - /* Followed by the amount of data corresponding to the DLC (T2..) */ - - src = frame->data; - nbytes = frame->len; - } -#endif - - dest = (uint32_t *)&txbuffer[2]; - - /* Writes must be word length */ - - for (i = 0; i < nbytes; i += 4) - { - /* Little endian is assumed */ - - wordbuffer = src[0] | - (src[1] << 8) | - (src[2] << 16) | - (src[3] << 24); - src += 4; - - *dest++ = wordbuffer; - } - - /* Enable transmit interrupts from the TX FIFOQ buffer by setting TC - * interrupt bit in IR (also requires that the TC interrupt is enabled) - */ - - fdcan_putreg(priv, STM32_FDCAN_TXBTIE_OFFSET, (1 << ndx)); - - /* And request to send the packet */ - - fdcan_putreg(priv, STM32_FDCAN_TXBAR_OFFSET, (1 << ndx)); - - return OK; -} - -/**************************************************************************** - * Name: fdcan_txready - * - * Description: - * Return true if the FDCAN hardware can accept another TX message. - * - * Input Parameters: - * dev - An instance of the "upper half" can driver state structure. - * - * Returned Value: - * True if the FDCAN hardware is ready to accept another TX message. - * - ****************************************************************************/ - -static bool fdcan_txready(struct stm32_fdcan_s *priv) -{ - uint32_t regval = 0; - bool notfull = false; - - /* Return the state of the TX FIFOQ. Return TRUE if the TX FIFO/Queue is - * not full. - */ - - regval = fdcan_getreg(priv, STM32_FDCAN_TXFQS_OFFSET); - notfull = ((regval & FDCAN_TXFQS_TFQF) == 0); - - return notfull; -} - -/**************************************************************************** - * Name: fdcan_rx0interrupt_work - * - * Description: - * CAN RX FIFO 0 worker - * - ****************************************************************************/ - -static void fdcan_rx0interrupt_work(void *arg) -{ - struct stm32_fdcan_s *priv = (struct stm32_fdcan_s *)arg; - const struct stm32_config_s *config = NULL; - uint32_t regval = 0; - unsigned int nelem = 0; - unsigned int ndx = 0; - - DEBUGASSERT(priv); - config = priv->config; - DEBUGASSERT(config); - - /* Clear the RX FIFO0 new message interrupt */ - - fdcan_putreg(priv, STM32_FDCAN_IR_OFFSET, FDCAN_INT_RF0N); - - regval = fdcan_getreg(priv, STM32_FDCAN_RXF0S_OFFSET); - nelem = (regval & FDCAN_RXFS_FFL_MASK) >> FDCAN_RXFS_FFL_SHIFT; - if (nelem > 0) - { - /* Handle the newly received message in FIFO0 */ - - ndx = (regval & FDCAN_RXFS_FGI_MASK) >> FDCAN_RXFS_FGI_SHIFT; - - if ((regval & FDCAN_RXFS_RFL) != 0) - { - nerr("ERROR: Message lost: %08" PRIx32 "\n", regval); - } - else - { - fdcan_receive(priv, - config->msgram.rxfifo0 + - (ndx * priv->config->rxfifo0esize), - priv->config->rxfifo0esize); - -#ifdef CONFIG_NET_CAN_ERRORS - /* Turning back on all configured RX error interrupts */ - - regval = fdcan_getreg(priv, STM32_FDCAN_IE_OFFSET); - regval |= FDCAN_RXERR_INTS; - fdcan_putreg(priv, STM32_FDCAN_IE_OFFSET, regval); -#endif - } - - /* Acknowledge reading the FIFO entry */ - - fdcan_putreg(priv, STM32_FDCAN_RXF0A_OFFSET, ndx); - } - - /* Re-enable CAN RX interrupts */ - - fdcan_rx0int(priv, true); -} - -/**************************************************************************** - * Name: fdcan_rx1interrupt_work - * - * Description: - * CAN RX FIFO 1 worker - * - ****************************************************************************/ - -static void fdcan_rx1interrupt_work(void *arg) -{ - struct stm32_fdcan_s *priv = (struct stm32_fdcan_s *)arg; - const struct stm32_config_s *config = NULL; - uint32_t regval = 0; - unsigned int nelem = 0; - unsigned int ndx = 0; - - DEBUGASSERT(priv); - config = priv->config; - DEBUGASSERT(config); - - /* Clear the RX FIFO1 new message interrupt */ - - fdcan_putreg(priv, STM32_FDCAN_IR_OFFSET, FDCAN_INT_RF1N); - - /* Check if there is anything in RX FIFO1 */ - - regval = fdcan_getreg(priv, STM32_FDCAN_RXF1S_OFFSET); - nelem = (regval & FDCAN_RXFS_FFL_MASK) >> FDCAN_RXFS_FFL_SHIFT; - if (nelem == 0) - { - /* Clear the RX FIFO1 interrupt (and all other FIFO1-related - * interrupts) - */ - - /* Handle the newly received message in FIFO1 */ - - ndx = (regval & FDCAN_RXFS_FGI_MASK) >> FDCAN_RXFS_FGI_SHIFT; - - if ((regval & FDCAN_RXFS_RFL) != 0) - { - nerr("ERROR: Message lost: %08" PRIx32 "\n", regval); - } - else - { - fdcan_receive(priv, - config->msgram.rxfifo1 + - (ndx * priv->config->rxfifo1esize), - priv->config->rxfifo1esize); - -#ifdef CONFIG_NET_CAN_ERRORS - /* Turning back on all configured RX error interrupts */ - - regval = fdcan_getreg(priv, STM32_FDCAN_IE_OFFSET); - regval |= FDCAN_RXERR_INTS; - fdcan_putreg(priv, STM32_FDCAN_IE_OFFSET, regval); -#endif - } - - /* Acknowledge reading the FIFO entry */ - - fdcan_putreg(priv, STM32_FDCAN_RXF1A_OFFSET, ndx); - } - - /* Re-enable CAN RX interrupts */ - - fdcan_rx1int(priv, true); -} - -/**************************************************************************** - * Name: fdcan_txdone_work - ****************************************************************************/ - -static void fdcan_txdone_work(void *arg) -{ - struct stm32_fdcan_s *priv = (struct stm32_fdcan_s *)arg; - - fdcan_txdone(priv); - - /* There should be space for a new TX in any event. Poll the network for - * new XMIT data - */ - - net_lock(); - devif_poll(&priv->dev, fdcan_txpoll); - net_unlock(); -} - -/**************************************************************************** - * Name: fdcan_txdone - ****************************************************************************/ - -static void fdcan_txdone(struct stm32_fdcan_s *priv) -{ - const struct stm32_config_s *config = NULL; - unsigned int ndx = 0; - uint32_t regval = 0; - - DEBUGASSERT(priv); - config = priv->config; - DEBUGASSERT(config); - - /* Clear the pending TX completion interrupt (and all - * other TX-related interrupts) - */ - - fdcan_putreg(priv, STM32_FDCAN_IR_OFFSET, FDCAN_TXFIFOQ_INTS); - - /* Check all TX buffers */ - - regval = fdcan_getreg(priv, STM32_FDCAN_TXBTO_OFFSET); - for (ndx = 0; ndx < config->ntxfifoq; ndx++) - { - if ((regval & (1 << ndx)) != 0) - { - /* Tell the upper half that the transfer is finished. */ - - NETDEV_TXDONE(&priv->dev); - } - } - -#ifdef CONFIG_NET_CAN_ERRORS - /* Turning back on PEA and PED error interrupts */ - - regval = fdcan_getreg(priv, STM32_FDCAN_IE_OFFSET); - regval |= (FDCAN_INT_PEA | FDCAN_INT_PED); - fdcan_putreg(priv, STM32_FDCAN_IE_OFFSET, regval); -#endif - - /* Re-enable TX interrupts */ - - fdcan_txint(priv, true); -} - -#ifdef CONFIG_NET_CAN_ERRORS -/**************************************************************************** - * Name: fdcan_error_work - ****************************************************************************/ - -static void fdcan_error_work(void *arg) -{ - struct stm32_fdcan_s *priv = (struct stm32_fdcan_s *)arg; - uint32_t pending = 0; - uint32_t ir = 0; - uint32_t ie = 0; - uint32_t psr = 0; - - /* Get the set of pending interrupts. */ - - ir = fdcan_getreg(priv, STM32_FDCAN_IR_OFFSET); - ie = fdcan_getreg(priv, STM32_FDCAN_IE_OFFSET); - - pending = (ir & ie); - ie |= FDCAN_ANYERR_INTS; - - /* Check for common errors */ - - if ((pending & FDCAN_CMNERR_INTS) != 0) - { - /* When a protocol error occurs, the problem is recorded in - * the LEC/DLEC fields of the PSR register. In lieu of - * separate interrupt flags for each error, the hardware - * groups protocol errors under a single interrupt each for - * arbitration and data phases. - * - * These errors have a tendency to flood the system with - * interrupts, so they are disabled here until we get a - * successful transfer/receive on the hardware - */ - - psr = fdcan_getreg(priv, STM32_FDCAN_PSR_OFFSET); - - if ((psr & FDCAN_PSR_LEC_MASK) != 0) - { - ie &= ~(FDCAN_INT_PEA | FDCAN_INT_PED); - } - - /* Clear the error indications */ - - fdcan_putreg(priv, STM32_FDCAN_IR_OFFSET, FDCAN_CMNERR_INTS); - } - - /* Check for transmission errors */ - - if ((pending & FDCAN_TXERR_INTS) != 0) - { - /* An Acknowledge-Error will occur if for example the device - * is not connected to the bus. - * - * The CAN-Standard states that the Chip has to retry the - * message forever, which will produce an ACKE every time. - * To prevent this Interrupt-Flooding and the high CPU-Load - * we disable the ACKE here as long we didn't transfer at - * least one message successfully (see FDCAN_INT_TC below). - */ - - /* Clear the error indications */ - - fdcan_putreg(priv, STM32_FDCAN_IR_OFFSET, FDCAN_TXERR_INTS); - } - - /* Check for reception errors */ - - if ((pending & FDCAN_RXERR_INTS) != 0) - { - /* To prevent Interrupt-Flooding the current active - * RX error interrupts are disabled. After successfully - * receiving at least one CAN packet all RX error interrupts - * are turned back on. - * - * The Interrupt-Flooding can for example occur if the - * configured CAN speed does not match the speed of the other - * CAN nodes in the network. - */ - - ie &= ~(pending & FDCAN_RXERR_INTS); - - /* Clear the error indications */ - - fdcan_putreg(priv, STM32_FDCAN_IR_OFFSET, FDCAN_RXERR_INTS); - } - - /* Report errors */ - - net_lock(); - fdcan_error(priv, pending & FDCAN_ANYERR_INTS); - net_unlock(); - - /* Re-enable ERROR interrupts */ - - fdcan_putreg(priv, STM32_FDCAN_IE_OFFSET, ie); -} - -/**************************************************************************** - * Name: fdcan_error - * - * Description: - * Report a CAN error - * - * Input Parameters: - * dev - CAN-common state data - * status - Interrupt status with error bits set - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void fdcan_error(struct stm32_fdcan_s *priv, uint32_t status) -{ - struct can_frame *frame = (struct can_frame *)priv->rxdesc; - uint32_t psr = 0; - uint16_t errbits = 0; - uint8_t data[CAN_ERR_DLC]; - - DEBUGASSERT(priv != NULL); - - /* Encode error bits */ - - errbits = 0; - memset(data, 0, sizeof(data)); - - /* Always fill in "static" error conditions, but set the signaling bit - * only if the condition has changed (see IRQ-Flags below) - * They have to be filled in every time CAN_ERROR_CONTROLLER is set. - */ - - psr = fdcan_getreg(priv, STM32_FDCAN_PSR_OFFSET); - if ((psr & FDCAN_PSR_EP) != 0) - { - data[1] |= (CAN_ERR_CRTL_RX_PASSIVE | CAN_ERR_CRTL_TX_PASSIVE); - } - - if ((psr & FDCAN_PSR_EW) != 0) - { - data[1] |= (CAN_ERR_CRTL_RX_WARNING | CAN_ERR_CRTL_TX_WARNING); - } - - if ((status & (FDCAN_INT_EP | FDCAN_INT_EW)) != 0) - { - /* "Error Passive" or "Error Warning" status changed */ - - errbits |= CAN_ERR_CRTL; - } - - if ((status & FDCAN_INT_PEA) != 0) - { - /* Protocol Error in Arbitration Phase */ - - if ((psr & FDCAN_PSR_LEC_MASK) != 0) - { - /* Error code present */ - - if ((psr & FDCAN_PSR_LEC(FDCAN_PSR_EC_STUFF_ERROR)) != 0) - { - /* Stuff Error */ - - errbits |= CAN_ERR_PROT; - data[2] |= CAN_ERR_PROT_STUFF; - } - - if ((psr & FDCAN_PSR_LEC(FDCAN_PSR_EC_FORM_ERROR)) != 0) - { - /* Format Error */ - - errbits |= CAN_ERR_PROT; - data[2] |= CAN_ERR_PROT_FORM; - } - - if ((psr & FDCAN_PSR_LEC(FDCAN_PSR_EC_ACK_ERROR)) != 0) - { - /* Acknowledge Error */ - - errbits |= CAN_ERR_ACK; - } - - if ((psr & FDCAN_PSR_LEC(FDCAN_PSR_EC_BIT0_ERROR)) != 0) - { - /* Bit0 Error */ - - errbits |= CAN_ERR_PROT; - data[2] |= CAN_ERR_PROT_BIT0; - } - - if ((psr & FDCAN_PSR_LEC(FDCAN_PSR_EC_BIT1_ERROR)) != 0) - { - /* Bit1 Error */ - - errbits |= CAN_ERR_PROT; - data[2] |= CAN_ERR_PROT_BIT1; - } - - if ((psr & FDCAN_PSR_LEC(FDCAN_PSR_EC_CRC_ERROR)) != 0) - { - /* Receive CRC Error */ - - errbits |= CAN_ERR_PROT; - data[3] |= (CAN_ERR_PROT_LOC_CRC_SEQ | - CAN_ERR_PROT_LOC_CRC_DEL); - } - - if ((psr & FDCAN_PSR_LEC(FDCAN_PSR_EC_NO_CHANGE)) != 0) - { - /* No Change in Error */ - - errbits |= CAN_ERR_PROT; - data[2] |= CAN_ERR_PROT_UNSPEC; - } - } - } - - if ((status & FDCAN_INT_PED) != 0) - { - /* Protocol Error in Data Phase */ - - if ((psr & FDCAN_PSR_DLEC_MASK) != 0) - { - /* Error code present */ - - if ((psr & FDCAN_PSR_DLEC(FDCAN_PSR_EC_STUFF_ERROR)) != 0) - { - /* Stuff Error */ - - errbits |= CAN_ERR_PROT; - data[2] |= CAN_ERR_PROT_STUFF; - } - - if ((psr & FDCAN_PSR_DLEC(FDCAN_PSR_EC_FORM_ERROR)) != 0) - { - /* Format Error */ - - errbits |= CAN_ERR_PROT; - data[2] |= CAN_ERR_PROT_FORM; - } - - if ((psr & FDCAN_PSR_DLEC(FDCAN_PSR_EC_ACK_ERROR)) != 0) - { - /* Acknowledge Error */ - - errbits |= CAN_ERR_ACK; - } - - if ((psr & FDCAN_PSR_DLEC(FDCAN_PSR_EC_BIT0_ERROR)) != 0) - { - /* Bit0 Error */ - - errbits |= CAN_ERR_PROT; - data[2] |= CAN_ERR_PROT_BIT0; - } - - if ((psr & FDCAN_PSR_DLEC(FDCAN_PSR_EC_BIT1_ERROR)) != 0) - { - /* Bit1 Error */ - - errbits |= CAN_ERR_PROT; - data[2] |= CAN_ERR_PROT_BIT1; - } - - if ((psr & FDCAN_PSR_DLEC(FDCAN_PSR_EC_CRC_ERROR)) != 0) - { - /* Receive CRC Error */ - - errbits |= CAN_ERR_PROT; - data[3] |= (CAN_ERR_PROT_LOC_CRC_SEQ | - CAN_ERR_PROT_LOC_CRC_DEL); - } - - if ((psr & FDCAN_PSR_DLEC(FDCAN_PSR_EC_NO_CHANGE)) != 0) - { - /* No Change in Error */ - - errbits |= CAN_ERR_PROT; - data[2] |= CAN_ERR_PROT_UNSPEC; - } - } - } - - if ((status & FDCAN_INT_BO) != 0) - { - /* Bus_Off Status changed */ - - if ((psr & FDCAN_PSR_BO) != 0) - { - errbits |= CAN_ERR_BUSOFF; - } - else - { - errbits |= CAN_ERR_RESTARTED; - } - } - - if ((status & (FDCAN_INT_RF0L | FDCAN_INT_RF1L)) != 0) - { - /* Receive FIFO 0/1 Message Lost - * Receive FIFO 1 Message Lost - */ - - errbits |= CAN_ERR_CRTL; - data[1] |= CAN_ERR_CRTL_RX_OVERFLOW; - } - - if ((status & FDCAN_INT_TEFL) != 0) - { - /* Tx Event FIFO Element Lost */ - - errbits |= CAN_ERR_CRTL; - data[1] |= CAN_ERR_CRTL_TX_OVERFLOW; - } - - if ((status & FDCAN_INT_TOO) != 0) - { - /* Timeout Occurred */ - - errbits |= CAN_ERR_TX_TIMEOUT; - } - - if ((status & (FDCAN_INT_MRAF | FDCAN_INT_ELO)) != 0) - { - /* Message RAM Access Failure - * Error Logging Overflow - */ - - errbits |= CAN_ERR_CRTL; - data[1] |= CAN_ERR_CRTL_UNSPEC; - } - - if (errbits != 0) - { - nerr("ERROR: errbits = %08" PRIx16 "\n", errbits); - - /* Copy frame */ - - frame->can_id = errbits; - frame->can_dlc = CAN_ERR_DLC; - - memcpy(frame->data, data, CAN_ERR_DLC); - - /* Copy the buffer pointer to priv->dev.. Set amount of data - * in priv->dev.d_len - */ - - priv->dev.d_len = sizeof(struct can_frame); - priv->dev.d_buf = (uint8_t *)frame; - - /* Send to socket interface */ - - NETDEV_ERRORS(&priv->dev); - - can_input(&priv->dev); - - /* Point the packet buffer back to the next Tx buffer that will be - * used during the next write. If the write queue is full, then - * this will point at an active buffer, which must not be written - * to. This is OK because devif_poll won't be called unless the - * queue is not full. - */ - - priv->dev.d_buf = (uint8_t *)priv->txdesc; - } -} -#endif /* CONFIG_NET_CAN_ERRORS */ - -/**************************************************************************** - * Name: fdcan_receive - * - * Description: - * Receive an FDCAN messages - * - * Input Parameters: - * dev - CAN-common state data - * rxbuffer - The RX buffer containing the received messages - * nwords - The length of the RX buffer (element size in words). - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void fdcan_receive(struct stm32_fdcan_s *priv, - volatile uint32_t *rxbuffer, - unsigned long nwords) -{ - fdcan_dumprxregs(dev->cd_priv, "Before receive"); - - /* CAN 2.0 or CAN FD */ - -#ifdef CONFIG_NET_CAN_CANFD - if ((rxbuffer[1] & BUFFER_R1_FDF) != 0) - { - struct canfd_frame *frame = (struct canfd_frame *)priv->rxdesc; - - /* Format the CAN FD header */ - - /* Extract the RTR bit */ - - if ((rxbuffer[0] & BUFFER_R0_RTR) != 0) - { - frame->can_id |= CAN_RTR_FLAG; - } - -#ifdef CONFIG_NET_CAN_EXTID - if ((rxbuffer[0] & BUFFER_R0_XTD) != 0) - { - /* Save the extended ID of the newly received message */ - - frame->can_id = ((rxbuffer[0] & BUFFER_R0_EXTID_MASK) >> - BUFFER_R0_EXTID_SHIFT); - frame->can_id |= CAN_EFF_FLAG; - } - else - { - frame->can_id = ((rxbuffer[0] & BUFFER_R0_STDID_MASK) >> - BUFFER_R0_STDID_SHIFT); - frame->can_id &= ~CAN_EFF_FLAG; - } -#else - if ((rxbuffer[0] & BUFFER_R0_XTD) != 0) - { - /* Drop any messages with extended IDs */ - - return; - } - - /* Save the standard ID of the newly received message */ - - frame->can_id = ((rxbuffer[0] & BUFFER_R0_STDID_MASK) >> - BUFFER_R0_STDID_SHIFT); -#endif - - /* Word R1 contains the DLC and timestamp */ - - frame->len = g_can_dlc_to_len[((rxbuffer[1] & BUFFER_R1_DLC_MASK) >> - BUFFER_R1_DLC_SHIFT)]; - - /* Get CANFD flags */ - - frame->flags = 0; - - if ((rxbuffer[0] & BUFFER_R0_ESI) != 0) - { - frame->flags |= CANFD_ESI; - } - - if ((rxbuffer[1] & BUFFER_R1_BRS) != 0) - { - frame->flags |= CANFD_BRS; - } - - /* Save the message data */ - - memcpy(frame->data, (void *)&rxbuffer[2], frame->len); - - /* Copy the buffer pointer to priv->dev.. Set amount of data - * in priv->dev.d_len - */ - - priv->dev.d_len = sizeof(struct canfd_frame); - priv->dev.d_buf = (uint8_t *)frame; - } - else -#endif - { - struct can_frame *frame = (struct can_frame *)priv->rxdesc; - - /* Format the CAN header */ - - /* Extract the RTR bit */ - - if ((rxbuffer[0] & BUFFER_R0_RTR) != 0) - { - frame->can_id |= CAN_RTR_FLAG; - } - -#ifdef CONFIG_NET_CAN_EXTID - if ((rxbuffer[0] & BUFFER_R0_XTD) != 0) - { - /* Save the extended ID of the newly received message */ - - frame->can_id = ((rxbuffer[0] & BUFFER_R0_EXTID_MASK) >> - BUFFER_R0_EXTID_SHIFT); - frame->can_id |= CAN_EFF_FLAG; - } - else - { - frame->can_id = ((rxbuffer[0] & BUFFER_R0_STDID_MASK) >> - BUFFER_R0_STDID_SHIFT); - frame->can_id &= ~CAN_EFF_FLAG; - } -#else - if ((rxbuffer[0] & BUFFER_R0_XTD) != 0) - { - /* Drop any messages with extended IDs */ - - return; - } - - /* Save the standard ID of the newly received message */ - - frame->can_id = ((rxbuffer[0] & BUFFER_R0_STDID_MASK) >> - BUFFER_R0_STDID_SHIFT); -#endif - - /* Word R1 contains the DLC and timestamp */ - - frame->can_dlc = ((rxbuffer[1] & BUFFER_R1_DLC_MASK) >> - BUFFER_R1_DLC_SHIFT); - - /* Save the message data */ - - memcpy(frame->data, (void *)&rxbuffer[2], frame->can_dlc); - - /* Copy the buffer pointer to priv->dev.. Set amount of data - * in priv->dev.d_len - */ - - priv->dev.d_len = sizeof(struct can_frame); - priv->dev.d_buf = (uint8_t *)frame; - } - - /* Send to socket interface */ - - NETDEV_RXPACKETS(&priv->dev); - - can_input(&priv->dev); - - /* Point the packet buffer back to the next Tx buffer that will be - * used during the next write. If the write queue is full, then - * this will point at an active buffer, which must not be written - * to. This is OK because devif_poll won't be called unless the - * queue is not full. - */ - - priv->dev.d_buf = (uint8_t *)priv->txdesc; -} - -/**************************************************************************** - * Name: fdcan_interrupt - * - * Description: - * Common FDCAN interrupt handler - * - * irq - The IRQ number of the interrupt. - * context - The register state save array at the time of the interrupt. - * - * Returned Value: - * Zero on success; a negated errno on failure - * - ****************************************************************************/ - -static int fdcan_interrupt(int irq, void *context, void *arg) -{ - struct stm32_fdcan_s *priv = (struct stm32_fdcan_s *)arg; - uint32_t pending = 0; - - DEBUGASSERT(priv != NULL); - - /* Get the set of pending interrupts. */ - - pending = fdcan_getreg(priv, STM32_FDCAN_IR_OFFSET); - -#ifdef CONFIG_NET_CAN_ERRORS - /* Check for any errors */ - - if ((pending & FDCAN_ANYERR_INTS) != 0) - { - /* Disable further CAN ERROR interrupts and schedule to perform the - * interrupt processing on the worker thread - */ - - fdcan_errint(priv, false); - work_queue(CANWORK, &priv->irqwork, fdcan_error_work, priv, 0); - } -#endif - - /* Check for successful completion of a transmission */ - - if ((pending & FDCAN_INT_TC) != 0) - { - /* Disable further TX CAN interrupts. here can be no race - * condition here. - */ - - fdcan_txint(priv, false); - work_queue(CANWORK, &priv->irqwork, fdcan_txdone_work, priv, 0); - } - else if ((pending & FDCAN_TXFIFOQ_INTS) != 0) - { - /* Clear unhandled TX events */ - - fdcan_putreg(priv, STM32_FDCAN_IR_OFFSET, FDCAN_TXFIFOQ_INTS); - } - - if (pending & FDCAN_INT_RF1N) - { - /* Disable further CAN RX interrupts and schedule to perform the - * interrupt processing on the worker thread - */ - - fdcan_rx1int(priv, false); - work_queue(CANWORK, &priv->irqwork, - fdcan_rx1interrupt_work, priv, 0); - } - - /* Clear the RX FIFO0 new message interrupt */ - - if (pending & FDCAN_INT_RF0N) - { - /* Disable further CAN RX interrupts and schedule to perform the - * interrupt processing on the worker thread - */ - - fdcan_rx0int(priv, false); - work_queue(CANWORK, &priv->irqwork, - fdcan_rx0interrupt_work, priv, 0); - } - - return OK; -} - -/**************************************************************************** - * Name: fdcan_hw_initialize - * - * Description: - * FDCAN hardware initialization - * - * Input Parameters: - * priv - A pointer to the private data structure for this FDCAN peripheral - * - * Returned Value: - * Zero on success; a negated errno value on failure. - * - ****************************************************************************/ - -static int fdcan_hw_initialize(struct stm32_fdcan_s *priv) -{ - const struct stm32_config_s *config = NULL; - volatile uint32_t *msgram = NULL; - uint32_t regval = 0; - uint32_t cntr = 0; - - DEBUGASSERT(priv); - config = priv->config; - DEBUGASSERT(config); - - ninfo("FDCAN%d\n", config->port); - - /* Clean message RAM */ - - msgram = config->msgram.stdfilters; - cntr = (FDCAN_MSGRAM_WORDS + 1); - while (cntr > 0) - { - *msgram++ = 0; - cntr--; - } - - /* Configure FDCAN pins */ - - stm32_configgpio(config->rxpinset); - stm32_configgpio(config->txpinset); - - /* Re-enable device if previously disabled in fdcan_shutdown() */ - - if (priv->state == FDCAN_STATE_DISABLED) - { - /* Reset Clock Stop Request bit */ - - regval = fdcan_getreg(priv, STM32_FDCAN_CCCR_OFFSET); - regval &= ~FDCAN_CCCR_CSR; - fdcan_putreg(priv, STM32_FDCAN_CCCR_OFFSET, regval); - - /* Wait for Clock Stop Acknowledge bit reset to indicate - * device is operational - */ - - while ((fdcan_getreg(priv, STM32_FDCAN_CCCR_OFFSET) & FDCAN_CCCR_CSA) - != 0); - } - - /* Enable the Initialization state */ - - regval = fdcan_getreg(priv, STM32_FDCAN_CCCR_OFFSET); - regval |= FDCAN_CCCR_INIT; - fdcan_putreg(priv, STM32_FDCAN_CCCR_OFFSET, regval); - - /* Wait for initialization mode to take effect */ - - while ((fdcan_getreg(priv, STM32_FDCAN_CCCR_OFFSET) & FDCAN_CCCR_INIT) - == 0); - - /* Enable writing to configuration registers */ - - regval = fdcan_getreg(priv, STM32_FDCAN_CCCR_OFFSET); - regval |= FDCAN_CCCR_CCE; - fdcan_putreg(priv, STM32_FDCAN_CCCR_OFFSET, regval); - - /* Global Filter Configuration: - * - * ANFS=0: Store all non matching standard frame in RX FIFO0 - * ANFE=0: Store all non matching extended frame in RX FIFO0 - */ - - regval = FDCAN_RXGFC_ANFE_RX_FIFO0 | FDCAN_RXGFC_ANFS_RX_FIFO0; - fdcan_putreg(priv, STM32_FDCAN_RXGFC_OFFSET, regval); - - /* Extended ID Filter AND mask */ - - fdcan_putreg(priv, STM32_FDCAN_XIDAM_OFFSET, 0x1fffffff); - - /* Disable all interrupts */ - - fdcan_putreg(priv, STM32_FDCAN_IE_OFFSET, 0); - fdcan_putreg(priv, STM32_FDCAN_TXBTIE_OFFSET, 0); - - /* All interrupts directed to Line 0. But disable both interrupt lines 0 - * and 1 for now. - * - * REVISIT: Only interrupt line 0 is used by this driver. - */ - - fdcan_putreg(priv, STM32_FDCAN_ILS_OFFSET, 0); - fdcan_putreg(priv, STM32_FDCAN_ILE_OFFSET, 0); - - /* Clear all pending interrupts. */ - - fdcan_putreg(priv, STM32_FDCAN_IR_OFFSET, FDCAN_INT_ALL); - - /* Configure FDCAN bit timing */ - - fdcan_putreg(priv, STM32_FDCAN_NBTP_OFFSET, priv->nbtp); - fdcan_putreg(priv, STM32_FDCAN_DBTP_OFFSET, priv->dbtp); - - /* Configure message RAM starting addresses and sizes. */ - - regval = FDCAN_RXGFC_LSS(config->nstdfilters); - regval |= FDCAN_RXGFC_LSE(config->nextfilters); - fdcan_putreg(priv, STM32_FDCAN_RXGFC_OFFSET, regval); - - /* Dump RAM layout */ - - fdcan_dumpramlayout(priv); - - /* Configure Message Filters */ - - /* Disable all standard filters */ - - msgram = config->msgram.stdfilters; - cntr = config->nstdfilters; - while (cntr > 0) - { - *msgram++ = STDFILTER_S0_SFEC_DISABLE; - cntr--; - } - - /* Disable all extended filters */ - - msgram = config->msgram.extfilters; - cntr = config->nextfilters; - while (cntr > 0) - { - *msgram = EXTFILTER_F0_EFEC_DISABLE; - msgram = msgram + 2; - cntr--; - } - - /* Input clock divider configuration */ - - regval = FDCANCLK_PDIV; - fdcan_putreg(priv, STM32_FDCAN_CKDIV_OFFSET, regval); - - /* CC control register */ - - regval = fdcan_getreg(priv, STM32_FDCAN_CCCR_OFFSET); - regval &= ~(FDCAN_CCCR_NISO | FDCAN_CCCR_FDOE | FDCAN_CCCR_BRSE); - - /* Select ISO11898-1 or Non ISO Bosch CAN FD Specification V1.0 */ - - switch (config->format) - { - case FDCAN_ISO11898_1_FORMAT: - { - break; - } - - case FDCAN_NONISO_BOSCH_V1_FORMAT: - { - regval |= FDCAN_CCCR_NISO; - break; - } - - default: - { - return -EINVAL; - } - } - - /* Select Classic CAN mode or FD mode with or without fast bit rate - * switching - */ - - switch (config->mode) - { - case FDCAN_CLASSIC_MODE: - { - break; - } - -#ifdef CONFIG_NET_CAN_CANFD - case FDCAN_FD_MODE: - { - regval |= FDCAN_CCCR_FDOE; - break; - } - - case FDCAN_FD_BRS_MODE: - { - regval |= (FDCAN_CCCR_FDOE | FDCAN_CCCR_BRSE); - break; - } -#endif - - default: - { - return -EINVAL; - } - } - - /* Set the initial CAN mode */ - - fdcan_putreg(priv, STM32_FDCAN_CCCR_OFFSET, regval); - - /* Enable FIFO/Queue mode */ - - regval = fdcan_getreg(priv, STM32_FDCAN_TXBC_OFFSET); -#ifdef CONFIG_STM32_FDCAN_QUEUE_MODE - regval |= FDCAN_TXBC_TFQM; -#else - regval &= ~FDCAN_TXBC_TFQM; -#endif - fdcan_putreg(priv, STM32_FDCAN_TXBC_OFFSET, regval); - -#ifdef STM32_FDCAN_LOOPBACK - /* Is loopback mode selected for this peripheral? */ - - if (config->loopback) - { - /* FDCAN_CCCR_TEST - Test mode enable - * FDCAN_CCCR_MON - Bus monitoring mode (for internal loopback) - * FDCAN_TEST_LBCK - Loopback mode - */ - - regval = fdcan_getreg(priv, STM32_FDCAN_CCCR_OFFSET); - regval |= (FDCAN_CCCR_TEST | FDCAN_CCCR_MON); - fdcan_putreg(priv, STM32_FDCAN_CCCR_OFFSET, regval); - - regval = fdcan_getreg(priv, STM32_FDCAN_TEST_OFFSET); - regval |= FDCAN_TEST_LBCK; - fdcan_putreg(priv, STM32_FDCAN_TEST_OFFSET, regval); - } -#endif - - /* Configure interrupt lines */ - - /* Direct all interrupts to Line 0. - * - * Bits in the ILS register correspond to each FDCAN interrupt; A bit - * set to '1' is directed to interrupt line 1; a bit cleared to '0' - * is directed interrupt line 0. - * - * REVISIT: Nothing is done here. Only interrupt line 0 is used by - * this driver and ILS was already cleared above. - */ - - /* Enable only interrupt line 0. */ - - fdcan_putreg(priv, STM32_FDCAN_ILE_OFFSET, FDCAN_ILE_EINT0); - - /* Disable initialization mode to enable normal operation */ - - regval = fdcan_getreg(priv, STM32_FDCAN_CCCR_OFFSET); - regval &= ~FDCAN_CCCR_INIT; - fdcan_putreg(priv, STM32_FDCAN_CCCR_OFFSET, regval); - - return OK; -} - -/**************************************************************************** - * Function: fdcan_ifup - * - * Description: - * NuttX Callback: Bring up the Ethernet interface when an IP address is - * provided - * - * Input Parameters: - * dev - Reference to the NuttX driver state structure - * - * Returned Value: - * None - * - * Assumptions: - * - ****************************************************************************/ - -static int fdcan_ifup(struct net_driver_s *dev) -{ - struct stm32_fdcan_s *priv = - (struct stm32_fdcan_s *)dev->d_private; - const struct stm32_config_s *config = NULL; - - DEBUGASSERT(priv); - config = priv->config; - DEBUGASSERT(config); - - /* Setup CAN */ - - fdcan_setup(priv); - - /* Enable interrupts */ - - fdcan_rx0int(priv, true); - fdcan_rx1int(priv, true); - fdcan_txint(priv, true); -#ifdef CONFIG_NET_CAN_ERRORS - fdcan_errint(priv, true); -#endif - - /* Enable the interrupts at the NVIC */ - - up_enable_irq(config->irq0); - up_enable_irq(config->irq1); - - priv->bifup = true; - - priv->txdesc = (struct can_frame *)priv->tx_pool; - priv->rxdesc = (struct can_frame *)priv->rx_pool; - - priv->dev.d_buf = (uint8_t *)priv->txdesc; - - netdev_carrier_on(dev); - - return OK; -} - -/**************************************************************************** - * Function: fdcan_ifdown - * - * Description: - * NuttX Callback: Stop the interface. - * - * Input Parameters: - * dev - Reference to the NuttX driver state structure - * - * Returned Value: - * None - * - * Assumptions: - * - ****************************************************************************/ - -static int fdcan_ifdown(struct net_driver_s *dev) -{ - struct stm32_fdcan_s *priv = - (struct stm32_fdcan_s *)dev->d_private; - - /* Disable CAN interrupts */ - - fdcan_shutdown(priv); - - /* Reset CAN */ - - fdcan_reset(priv); - - netdev_carrier_off(dev); - - return OK; -} - -/**************************************************************************** - * Function: fdcan_txpoll - * - * Description: - * The transmitter is available, check if the network has any outgoing - * packets ready to send. This is a callback from devif_poll(). - * devif_poll() may be called: - * - * 1. When the preceding TX packet send is complete, - * 2. When the preceding TX packet send timesout and the interface is reset - * 3. During normal TX polling - * - * Input Parameters: - * dev - Reference to the NuttX driver state structure - * - * Returned Value: - * OK on success; a negated errno on failure - * - * Assumptions: - * May or may not be called from an interrupt handler. In either case, - * global interrupts are disabled, either explicitly or indirectly through - * interrupt handling logic. - * - ****************************************************************************/ - -static int fdcan_txpoll(struct net_driver_s *dev) -{ - struct stm32_fdcan_s *priv = - (struct stm32_fdcan_s *)dev->d_private; - - /* If the polling resulted in data that should be sent out on the network, - * the field d_len is set to a value > 0. - */ - - if (priv->dev.d_len > 0) - { - fdcan_txdone(priv); - - /* Send the packet */ - - fdcan_send(priv); - - /* Check if there is room in the device to hold another packet. If - * not, return a non-zero value to terminate the poll. - */ - - if (fdcan_txready(priv) == false) - { - return -EBUSY; - } - } - - /* If zero is returned, the polling will continue until all connections - * have been examined. - */ - - return 0; -} - -/**************************************************************************** - * Function: fdcan_txavail_work - * - * Description: - * Perform an out-of-cycle poll on the worker thread. - * - * Input Parameters: - * arg - Reference to the NuttX driver state structure (cast to void*) - * - * Returned Value: - * None - * - * Assumptions: - * Called on the higher priority worker thread. - * - ****************************************************************************/ - -static void fdcan_txavail_work(void *arg) -{ - struct stm32_fdcan_s *priv = (struct stm32_fdcan_s *)arg; - - /* Ignore the notification if the interface is not yet up */ - - net_lock(); - if (priv->bifup) - { - /* Check if there is room in the hardware to hold another outgoing - * packet. - */ - - if (fdcan_txready(priv)) - { - /* No, there is space for another transfer. Poll the network for - * new XMIT data. - */ - - devif_poll(&priv->dev, fdcan_txpoll); - } - } - - net_unlock(); -} - -/**************************************************************************** - * Function: fdcan_txavail - * - * Description: - * Driver callback invoked when new TX data is available. This is a - * stimulus perform an out-of-cycle poll and, thereby, reduce the TX - * latency. - * - * Input Parameters: - * dev - Reference to the NuttX driver state structure - * - * Returned Value: - * None - * - * Assumptions: - * Called in normal user mode - * - ****************************************************************************/ - -static int fdcan_txavail(struct net_driver_s *dev) -{ - struct stm32_fdcan_s *priv = - (struct stm32_fdcan_s *)dev->d_private; - - /* Is our single work structure available? It may not be if there are - * pending interrupt actions and we will have to ignore the Tx - * availability action. - */ - - if (work_available(&priv->pollwork)) - { - /* Schedule to serialize the poll on the worker thread. */ - - fdcan_txavail_work(priv); - } - - return OK; -} - -/**************************************************************************** - * Function: fdcan_ioctl - * - * Description: - * PHY ioctl command handler - * - * Input Parameters: - * dev - Reference to the NuttX driver state structure - * cmd - ioctl command - * arg - Argument accompanying the command - * - * Returned Value: - * Zero (OK) on success; a negated errno value on failure. - * - * Assumptions: - * - ****************************************************************************/ - -#ifdef CONFIG_NETDEV_IOCTL -static int fdcan_netdev_ioctl(struct net_driver_s *dev, int cmd, - unsigned long arg); -{ - struct stm32_fdcan_s *priv = - (struct stm32_fdcan_s *)dev->d_private; - int ret = OK; - - DEBUGASSERT(priv); - - switch (cmd) - { - /* TODO */ - - default: - ret = -ENOTTY; - break; - } - - return ret; -} -#endif /* CONFIG_NETDEV_IOCTL */ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_cansockinitialize - * - * Description: - * Initialize the selected FDCAN port as CAN socket interface - * - * Input Parameters: - * Port number (for hardware that has multiple FDCAN interfaces) - * - * Returned Value: - * OK on success; Negated errno on failure. - * - ****************************************************************************/ - -int stm32_fdcansockinitialize(int port) -{ - struct stm32_fdcan_s *priv = NULL; - const struct stm32_config_s *config = NULL; - int ret = OK; - - ninfo("FDCAN%d\n", port); - - /* Select FDCAN peripheral to be initialized */ - -#ifdef CONFIG_STM32_FDCAN1 - if (port == FDCAN1) - { - /* Select the FDCAN1 device structure */ - - priv = &g_fdcan1priv; - config = &g_fdcan1const; - } - else -#endif -#ifdef CONFIG_STM32_FDCAN2 - if (port == FDCAN2) - { - /* Select the FDCAN2 device structure */ - - priv = &g_fdcan2priv; - config = &g_fdcan2const; - } - else -#endif -#ifdef CONFIG_STM32_FDCAN3 - if (port == FDCAN3) - { - /* Select the FDCAN3 device structure */ - - priv = &g_fdcan3priv; - config = &g_fdcan3const; - } - else -#endif - { - nerr("ERROR: Unsupported port %d\n", port); - ret = -EINVAL; - goto errout; - } - - /* Perform one time data initialization */ - - memset(priv, 0, sizeof(struct stm32_fdcan_s)); - priv->config = config; - - /* Set the initial bit timing. This might change subsequently - * due to IOCTL command processing. - */ - - priv->nbtp = config->nbtp; - priv->dbtp = config->dbtp; - - /* Initialize the driver structure */ - - priv->dev.d_ifup = fdcan_ifup; - priv->dev.d_ifdown = fdcan_ifdown; - priv->dev.d_txavail = fdcan_txavail; -#ifdef CONFIG_NETDEV_IOCTL - priv->dev.d_ioctl = fdcan_netdev_ioctl; -#endif - priv->dev.d_private = priv; - - /* Put the interface in the down state. This usually amounts to resetting - * the device and/or calling fdcan_ifdown(). - */ - - ninfo("callbacks done\n"); - - fdcan_ifdown(&priv->dev); - - /* Register the device with the OS so that socket IOCTLs can be performed */ - - ret = netdev_register(&priv->dev, NET_LL_CAN); - -errout: - return ret; -} - -/**************************************************************************** - * Name: arm_netinitialize - * - * Description: - * Initialize the CAN device interfaces. If there is more than one device - * interface in the chip, then board-specific logic will have to provide - * this function to determine which, if any, CAN interfaces should be - * initialized. - * - ****************************************************************************/ - -#if !defined(CONFIG_NETDEV_LATEINIT) -void arm_netinitialize(void) -{ -#ifdef CONFIG_STM32_CAN1 - stm32_fdcansockinitialize(FDCAN1); -#endif - -#ifdef CONFIG_STM32_CAN2 - stm32_fdcansockinitialize(FDCAN2); -#endif - -#ifdef CONFIG_STM32_CAN3 - stm32_fdcansockinitialize(FDCAN3); -#endif -} -#endif diff --git a/arch/arm/src/stm32/stm32_flash.c b/arch/arm/src/stm32/stm32_flash.c deleted file mode 100644 index 0afd013d87243..0000000000000 --- a/arch/arm/src/stm32/stm32_flash.c +++ /dev/null @@ -1,49 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_flash.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* Provides standard flash access functions, to be used by the flash mtd - * driver. The interface is defined in the include/nuttx/progmem.h - */ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -/* Include the correct FLASH implementation for the selection STM32 part */ - -#if defined(CONFIG_STM32_STM32L15XX) -# include "stm32l15xx_flash.c" -#elif defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F30XX) -# include "stm32f10xxf30xx_flash.c" -#elif defined(CONFIG_STM32_STM32F20XX) || defined (CONFIG_STM32_STM32F4XXX) -# include "stm32f20xxf40xx_flash.c" -#elif defined(CONFIG_STM32_STM32G4XXX) -# include "stm32g4xxx_flash.c" -#else -# warning "No FLASH support for the selected part" -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ diff --git a/arch/arm/src/stm32/stm32_flash.h b/arch/arm/src/stm32/stm32_flash.h deleted file mode 100644 index 6a67d7b2ce6a7..0000000000000 --- a/arch/arm/src/stm32/stm32_flash.h +++ /dev/null @@ -1,114 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_flash.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32_STM32_FLASH_H -#define __ARCH_ARM_SRC_STM32_STM32_FLASH_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include - -#include "chip.h" -#include "hardware/stm32_flash.h" - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -int stm32_flash_lock(void); -int stm32_flash_unlock(void); - -/**************************************************************************** - * Name: stm32_flash_user_optbytes - * - * Description: - * Modify the contents of the user option bytes (USR OPT) on the flash. - * This does not set OBL_LAUNCH so new options take effect only after - * next power reset. - * - * Input Parameters: - * clrbits - Bits in the option bytes to be cleared - * setbits - Bits in the option bytes to be set - * - * Returned Value: - * Option bytes after operation is completed - * - ****************************************************************************/ - -uint32_t stm32_flash_users_optbytes(uint32_t clrbits, uint32_t setbits); - -/**************************************************************************** - * Name: stm32_eeprom_size - * - * Description: - * Get EEPROM data memory size - * - * Returned Value: - * Length of EEPROM memory region - * - ****************************************************************************/ - -size_t stm32_eeprom_size(void); - -/**************************************************************************** - * Name: stm32_eeprom_getaddress - * - * Description: - * Get EEPROM data memory address - * - * Returned Value: - * Address of EEPROM memory region - * - ****************************************************************************/ - -size_t stm32_eeprom_getaddress(void); - -/**************************************************************************** - * Name: stm32_eeprom_write - * - * Description: - * Write buffer to EEPROM data memory address - * - * Returned Value: - * Number of written bytes or error code. - * - ****************************************************************************/ - -ssize_t stm32_eeprom_write(size_t addr, const void *buf, size_t buflen); - -/**************************************************************************** - * Name: stm32_eeprom_erase - * - * Description: - * Erase memory on EEPROM data memory address - * - * Returned Value: - * Number of erased bytes or error code. - * - ****************************************************************************/ - -ssize_t stm32_eeprom_erase(size_t addr, size_t eraselen); - -#endif /* __ARCH_ARM_SRC_STM32_STM32_FLASH_H */ diff --git a/arch/arm/src/stm32/stm32_fmc.c b/arch/arm/src/stm32/stm32_fmc.c deleted file mode 100644 index 4f0ac88e2a165..0000000000000 --- a/arch/arm/src/stm32/stm32_fmc.c +++ /dev/null @@ -1,212 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_fmc.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include "stm32.h" - -#if defined(CONFIG_STM32_FMC) - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_fmc_sdram_wait - * - * Description: - * Wait for the SDRAM controller to be ready. - * - ****************************************************************************/ - -void stm32_fmc_sdram_wait(void) -{ - int timeout = 0xffff; - while (timeout > 0) - { - if ((getreg32(STM32_FMC_SDSR) & FMC_SDSR_BUSY) == 0) - { - break; - } - - timeout--; - } - - DEBUGASSERT(timeout > 0); -} - -/**************************************************************************** - * Name: stm32_fmc_enable - * - * Description: - * Enable clocking to the FMC. - * - ****************************************************************************/ - -void stm32_fmc_enable(void) -{ - modifyreg32(STM32_RCC_AHB3ENR, 0, RCC_AHB3ENR_FMCEN); -} - -/**************************************************************************** - * Name: stm32_fmc_disable - * - * Description: - * Disable clocking to the FMC. - * - ****************************************************************************/ - -void stm32_fmc_disable(void) -{ - modifyreg32(STM32_RCC_AHB3ENR, RCC_AHB3ENR_FMCEN, 0); -} - -/**************************************************************************** - * Name: stm32_fmc_sdram_write_protect - * - * Description: - * Enable/Disable writes to an SDRAM. - * - ****************************************************************************/ - -void stm32_fmc_sdram_write_protect(int bank, bool state) -{ - uint32_t val; - uint32_t sdcr; - - DEBUGASSERT(bank == 1 || bank == 2); - sdcr = (bank == 1) ? STM32_FMC_SDCR1 : STM32_FMC_SDCR2; - - stm32_fmc_sdram_wait(); - - val = getreg32(sdcr); - if (state) - { - val |= FMC_SDCR_WP; /* wp == 1 */ - } - else - { - val &= ~FMC_SDCR_WP; /* wp == 0 */ - } - - putreg32(val, sdcr); -} - -/**************************************************************************** - * Name: stm32_fmc_sdram_set_refresh_rate - * - * Description: - * Set the SDRAM refresh rate. - * - ****************************************************************************/ - -void stm32_fmc_sdram_set_refresh_rate(int count) -{ - uint32_t val; - - DEBUGASSERT(count <= 0x1fff && count >= 0x29); - - stm32_fmc_sdram_wait(); - - val = getreg32(STM32_FMC_SDRTR); - val &= ~(0x1fff << 1); /* preserve non-count bits */ - val |= (count << 1); - putreg32(val, STM32_FMC_SDRTR); -} - -/**************************************************************************** - * Name: stm32_fmc_sdram_set_timing - * - * Description: - * Set the SDRAM timing parameters. - * - ****************************************************************************/ - -void stm32_fmc_sdram_set_timing(int bank, uint32_t timing) -{ - uint32_t val; - uint32_t sdtr; - - DEBUGASSERT((bank == 1) || (bank == 2)); - DEBUGASSERT((timing & FMC_SDTR_RESERVED) == 0); - - sdtr = (bank == 1) ? STM32_FMC_SDTR1 : STM32_FMC_SDTR2; - val = getreg32(sdtr); - val &= FMC_SDTR_RESERVED; /* preserve reserved bits */ - val |= timing; - putreg32(val, sdtr); -} - -/**************************************************************************** - * Name: stm32_fmc_sdram_set_control - * - * Description: - * Set the SDRAM control parameters. - * - ****************************************************************************/ - -void stm32_fmc_sdram_set_control(int bank, uint32_t ctrl) -{ - uint32_t val; - uint32_t sdcr; - - DEBUGASSERT((bank == 1) || (bank == 2)); - DEBUGASSERT((ctrl & FMC_SDCR_RESERVED) == 0); - - sdcr = (bank == 1) ? STM32_FMC_SDCR1 : STM32_FMC_SDCR2; - val = getreg32(sdcr); - val &= FMC_SDCR_RESERVED; /* preserve reserved bits */ - val |= ctrl; - putreg32(val, sdcr); -} - -/**************************************************************************** - * Name: stm32_fmc_sdram_command - * - * Description: - * Send a command to the SDRAM. - * - ****************************************************************************/ - -void stm32_fmc_sdram_command(uint32_t cmd) -{ - uint32_t val; - - DEBUGASSERT((cmd & FMC_SDCMR_RESERVED) == 0); - - /* Wait for the controller to be ready */ - - stm32_fmc_sdram_wait(); - - val = getreg32(STM32_FMC_SDCMR); - val &= FMC_SDCMR_RESERVED; /* Preserve reserved bits */ - val |= cmd; - putreg32(val, STM32_FMC_SDCMR); -} - -#endif /* CONFIG_STM32_FMC */ diff --git a/arch/arm/src/stm32/stm32_fmc.h b/arch/arm/src/stm32/stm32_fmc.h deleted file mode 100644 index 9644068d0ee66..0000000000000 --- a/arch/arm/src/stm32/stm32_fmc.h +++ /dev/null @@ -1,136 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_fmc.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_STC_STM32_STM32_FMC_H -#define __ARCH_ARM_STC_STM32_STM32_FMC_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "chip.h" -#include "hardware/stm32_fmc.h" - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -#ifndef __ASSEMBLY__ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Name: stm32_fmc_sdram_wait - * - * Description: - * Wait for the SDRAM controller to be ready. - * - ****************************************************************************/ - -void stm32_fmc_sdram_wait(void); - -/**************************************************************************** - * Name: stm32_fmc_enable - * - * Description: - * Enable clocking to the FMC. - * - ****************************************************************************/ - -void stm32_fmc_enable(void); - -/**************************************************************************** - * Name: stm32_fmc_disable - * - * Description: - * Disable clocking to the FMC. - * - ****************************************************************************/ - -void stm32_fmc_disable(void); - -/**************************************************************************** - * Name: stm32_fmc_sdram_write_protect - * - * Description: - * Enable/Disable writes to an SDRAM. - * - ****************************************************************************/ - -void stm32_fmc_sdram_write_protect(int bank, bool state); - -/**************************************************************************** - * Name: stm32_fmc_sdram_set_refresh_rate - * - * Description: - * Set the SDRAM refresh rate. - * - ****************************************************************************/ - -void stm32_fmc_sdram_set_refresh_rate(int count); - -/**************************************************************************** - * Name: stm32_fmc_sdram_set_timing - * - * Description: - * Set the SDRAM timing parameters. - * - ****************************************************************************/ - -void stm32_fmc_sdram_set_timing(int bank, uint32_t timing); - -/**************************************************************************** - * Name: stm32_fmc_sdram_set_control - * - * Description: - * Set the SDRAM control parameters. - * - ****************************************************************************/ - -void stm32_fmc_sdram_set_control(int bank, uint32_t ctrl); - -/**************************************************************************** - * Name: stm32_fmc_sdram_command - * - * Description: - * Send a command to the SDRAM. - * - ****************************************************************************/ - -void stm32_fmc_sdram_command(uint32_t cmd); - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_STC_STM32_STM32_FMC_H */ diff --git a/arch/arm/src/stm32/stm32_foc.c b/arch/arm/src/stm32/stm32_foc.c deleted file mode 100644 index edced961d9af3..0000000000000 --- a/arch/arm/src/stm32/stm32_foc.c +++ /dev/null @@ -1,2751 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_foc.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include -#include - -#include -#include - -#include "arm_internal.h" -#include "stm32_pwm.h" -#include "stm32_adc.h" -#include "stm32_dma.h" - -#include -#include - -#include "stm32_foc.h" - -#include "hardware/stm32_dbgmcu.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Verify peripheral configuration ******************************************/ - -/* This is the lower-half implementation for the STM32 FOC devices. - * - * We currently support a current sensing topology with two and three shunts. - * Configuration with a single-shunt is not supported at the moment and will - * require additional current reconstruction logic. - * - * A single FOC device uses one advanced timer to generate a center-aligned - * PWM which control phase switches bridge. Phase currents must be sampled - * at vector 0 (all low-side switches are on and the current flows through - * current sensors). - * - * This implementation uses one ADC per controller and we only use injected - * conversion to sample currents. ADC regular conversion is not used - * and can be used to other tasks with the help of DMA transfer. - * For ADC regular conversion, only DMA transfer is possible since ADC - * interrupt handler is reserved for the FOC only. - * - * The ADC conversion trigger is configurable. Available options are: - * 1. TRGO events generated on update event - * 2. CCR4 events - * - * There are some differences in implementation depending on the peripherals - * supported by the chip. - * - * There is no differences according to TIMER IPv1 and IPv2 affecting - * this implementation. - * - * For STM32 ADC cores there are some dissimilarities that had to be taken - * into account. It is: - * - * 1. For ADC IPv1 (F2, F4, F7, L1) - * - all ADC instances coupled in single block - * - single entry point for ADC123 interrupts - * - * 2. For ADC IPv1 basic (F1, F37x) - * - ADC instances are no coupled in blocks - * - common interrupts for ADC1 and ADC2 - * - * 3. For ADC IPv2 (F3 (without F37x), H7, L4, L4+, G4) - * - ADC grouped in slave-master configuration (ADC12, ADC34) - * - * This code will not work for chips with ADC IPv2 basic (F0, L0, G0). - * For these, only regular channels are available and we cannot use injected - * conversion. - * - * Currently, up to two FOC instances are supported. - */ - -/* Verify system configuration **********************************************/ - -/* This is not for ADC IPv2 basic */ - -#if defined(CONFIG_STM32_HAVE_IP_ADC_V2) && defined(HAVE_BASIC_ADC) -# error Not supported ADC IP core -#endif - -/* Multi instances support tested only on IP_ADC_V1 */ - -#if CONFIG_MOTOR_FOC_INST > 1 -# if defined(CONFIG_STM32_HAVE_IP_ADC_V2) -# error Not tested yet -# endif -#endif - -/* PWM lower-half ops and ADC lower-half ops must be enabled */ - -#ifndef CONFIG_STM32_PWM_LL_OPS -# error PWM low-level operations interface must be enabled -#endif -#ifndef CONFIG_STM32_ADC_LL_OPS -# error ADC low-level operations interface must be enabled -#endif - -/* We don't want start conversion during ADC setup */ - -#ifndef CONFIG_STM32_ADC_NO_STARTUP_CONV -# error ADC startup conversion must be disabled -#endif - -/* We need interface to change ADC sample-time */ - -#ifndef CONFIG_STM32_ADC_CHANGE_SAMPLETIME -# error ADC sample-time configuration interface must be enabled -#endif - -/* Debug register for PWM timers */ - -#if defined(CONFIG_STM32_HAVE_IP_DBGMCU_V2) || \ - defined(CONFIG_STM32_HAVE_IP_DBGMCU_V3) -# define FOC_PWM_FZ_REG (STM32_DBGMCU_APB2_FZ) -#elif defined(CONFIG_STM32_HAVE_IP_DBGMCU_V1) -# define FOC_PWM_FZ_REG (STM32_DBGMCU_CR) -#endif - -/* FOC0 always use TIMER1 for PWM */ - -#ifdef CONFIG_STM32_FOC_FOC0 -# define FOC0_PWM (1) -# define FOC0_PWM_NCHANNELS (PWM_TIM1_NCHANNELS) -# define FOC0_PWM_BASE (STM32_TIM1_BASE) -# if defined(CONFIG_STM32_HAVE_IP_DBGMCU_V2) || \ - defined(CONFIG_STM32_HAVE_IP_DBGMCU_V3) -# define FOC0_PWM_FZ_BIT (DBGMCU_APB2_TIM1STOP) -# elif defined(CONFIG_STM32_HAVE_IP_DBGMCU_V1) -# define FOC0_PWM_FZ_BIT (DBGMCU_CR_TIM1STOP) -# endif -# if CONFIG_STM32_TIM1_MODE != 2 -# error TIM1 must be configured in center-aligned mode 1 -# endif -#endif /* CONFIG_STM32_FOC_FOC0 */ - -/* FOC1 always use TIMER8 for PWM */ - -#ifdef CONFIG_STM32_FOC_FOC1 -# define FOC1_PWM (8) -# define FOC1_PWM_NCHANNELS (PWM_TIM8_NCHANNELS) -# define FOC1_PWM_BASE (STM32_TIM8_BASE) -# if defined(CONFIG_STM32_HAVE_IP_DBGMCU_V2) || \ - defined(CONFIG_STM32_HAVE_IP_DBGMCU_V3) -# define FOC1_PWM_FZ_BIT (DBGMCU_APB2_TIM8STOP) -# elif defined(CONFIG_STM32_HAVE_IP_DBGMCU_V1) -# define FOC1_PWM_FZ_BIT (DBGMCU_CR_TIM8STOP) -# endif -# if CONFIG_STM32_TIM8_MODE != 2 -# error TIM8 must be configured in center-aligned mode 1 -# endif -#endif - -/* The maximum supported number of phases depends on the ADC trigger */ - -#if defined(CONFIG_STM32_FOC_ADC_CCR4) -# if CONFIG_MOTOR_FOC_PHASES > 3 -# error max 3 phases supported -# endif -#elif defined(CONFIG_STM32_FOC_ADC_TRGO) -# if CONFIG_MOTOR_FOC_PHASES > 4 -# error max 4 phases supported -# endif -#else -# error -#endif - -/* Tested only for 3-phase devices */ - -#if CONFIG_MOTOR_FOC_PHASES != 3 -# error Tested only for 3-phase devices -#endif - -/* Only one ADC trigger must be selected */ - -#if defined(CONFIG_STM32_FOC_ADC_CCR4) && defined(CONFIG_STM32_FOC_ADC_TRGO) -# error Invalid ADC trigger configuration -#endif - -/* Phase currents can only be sampled when all low-side switches are off. - * This is only valid for the V0 vector in the SVM. - * - * For PWM mode 1: - * V7 for CNTR = 0 - * V0 for CNTR = ARR - * - * For PWM mode 2: - * V7 for CNTR = ARR - * V0 for CNTR = 0 - */ - -#if defined(CONFIG_STM32_FOC_ADC_CCR4) - -/* FOC ADC trigger on CCR4 **************************************************/ - -/* PWM channels configuration: - * - 3 channels for phases PWM (CCR1, CCR2, CCR3) - * - 1 channel for ADC injection sequence trigger (CCR4) - */ - -# if defined(CONFIG_STM32_FOC_FOC0) -# if FOC0_PWM_NCHANNELS != (CONFIG_MOTOR_FOC_PHASES + 1) -# error Invalid channels configuration -# endif -# endif -# if defined(CONFIG_STM32_FOC_FOC1) -# if FOC1_PWM_NCHANNELS != (CONFIG_MOTOR_FOC_PHASES + 1) -# error Invalid channels configuration -# endif -# endif - -/* Generalize JEXTSEL bits for CCR4 trigger. - * - * ADC trigger event on PWM timer CCR4 (rising edge). - * - * This implementation uses PWM mode 1 so: - * TIMx CCR4 = (ARR - trigger_offset) - */ - -# if defined(CONFIG_STM32_HAVE_IP_ADC_V2) -# ifdef CONFIG_STM32_FOC_USE_TIM1 -# define ADC_JEXTSEL_T1CC4 (ADC12_JSQR_JEXTSEL_T1CC4) -# endif -# ifdef CONFIG_STM32_FOC_USE_TIM8 -# define ADC_JEXTSEL_T8CC4 (ADC12_JSQR_JEXTSEL_T8CC4) -# endif -# elif defined(CONFIG_STM32_HAVE_IP_ADC_V1) -# ifdef CONFIG_STM32_FOC_USE_TIM1 -# define ADC_JEXTSEL_T1CC4 (ADC_CR2_JEXTSEL_T1CC4) -# endif -# ifdef CONFIG_STM32_FOC_USE_TIM8 -# define ADC_JEXTSEL_T8CC4 (ADC_CR2_JEXTSEL_T8CC4) -# endif -# else -# error Not supported -# endif - -/* ADC trigger offset - must be greater than 0! */ - -# define ADC_TRIGGER_OFFSET (1) - -# ifdef CONFIG_STM32_FOC_FOC0 -# define FOC0_ADC_JEXTSEL (ADC_JEXTSEL_T1CC4) -# endif -# ifdef CONFIG_STM32_FOC_FOC1 -# define FOC1_ADC_JEXTSEL (ADC_JEXTSEL_T8CC4) -# endif - -#elif defined(CONFIG_STM32_FOC_ADC_TRGO) - -/* FOC ADC trigger on TRGO **************************************************/ - -/* PWM TRGO support must be enabled */ - -# ifndef CONFIG_STM32_PWM_TRGO -# error PWM TRGO support must be enabled -# endif - -/* TRGO on update event = ATIM_CR2_MMS_UPDATE (2) */ - -# define FOC_PWM_TRGO (2) - -/* PWM channels configuration: - * - n channels for phases PWM (CCR1, CCR2, CCR3, CCR4) - */ - -# if defined(CONFIG_STM32_FOC_FOC0) -# if FOC0_PWM_NCHANNELS != (CONFIG_MOTOR_FOC_PHASES) -# error Invalid channels configuration -# endif -# endif -# if defined(CONFIG_STM32_FOC_FOC1) -# if FOC1_PWM_NCHANNELS != (CONFIG_MOTOR_FOC_PHASES) -# error Invalid channels configuration -# endif -# endif - -/* Generalize JEXTSEL bits for TRGO trigger. - * - * ADC trigger event on PWM timer TRGO (rising edge). - * - * This implementation uses PWM mode 1 so: - * TIMx TRGO = (ARR) - */ - -# if defined(CONFIG_STM32_HAVE_IP_ADC_V2) -# ifdef CONFIG_STM32_FOC_USE_TIM1 -# define ADC_JEXTSEL_T1TRGO (ADC12_JSQR_JEXTSEL_T1TRGO) -# endif -# ifdef CONFIG_STM32_FOC_USE_TIM8 -# define ADC_JEXTSEL_T8TRGO (ADC12_JSQR_JEXTSEL_T8TRGO) -# endif -# elif defined(CONFIG_STM32_HAVE_IP_ADC_V1) -# ifdef CONFIG_STM32_FOC_USE_TIM1 -# define ADC_JEXTSEL_T1TRGO (ADC_CR2_JEXTSEL_T1TRGO) -# endif -# ifdef CONFIG_STM32_FOC_USE_TIM8 -# error TIM8 and TRGO trigger not supported for ADC IPv1 -# endif -# else -# error Not supported -# endif - -# ifdef CONFIG_STM32_FOC_FOC0 -# define FOC0_ADC_JEXTSEL (ADC_JEXTSEL_T1TRGO) -# endif -# ifdef CONFIG_STM32_FOC_FOC1 -# define FOC1_ADC_JEXTSEL (ADC_JEXTSEL_T8TRGO) -# endif - -#else - -/* No trigger selected ******************************************************/ - -# error Invalid FOC ADC trigger -#endif - -/* Phase current samples for FOC0 */ - -#ifdef CONFIG_STM32_FOC_FOC0 -# ifdef CONFIG_STM32_FOC_FOC0_ADC1 -# define FOC0_ADC 1 -# endif -# ifdef CONFIG_STM32_FOC_FOC0_ADC2 -# define FOC0_ADC 2 -# endif -# ifdef CONFIG_STM32_FOC_FOC0_ADC3 -# define FOC0_ADC 3 -# endif -# ifdef CONFIG_STM32_FOC_FOC0_ADC4 -# define FOC0_ADC 4 -# endif -#endif - -/* Phase current samples for FOC1 */ - -#ifdef CONFIG_STM32_FOC_FOC1 -# ifdef CONFIG_STM32_FOC_FOC1_ADC1 -# define FOC1_ADC 1 -# endif -# ifdef CONFIG_STM32_FOC_FOC1_ADC2 -# define FOC1_ADC 2 -# endif -# ifdef CONFIG_STM32_FOC_FOC1_ADC3 -# define FOC1_ADC 3 -# endif -# ifdef CONFIG_STM32_FOC_FOC1_ADC4 -# define FOC1_ADC 4 -# endif -#endif - -/* The number of required injected channels */ - -#ifdef CONFIG_STM32_FOC_G4_ADCCHAN0_WORKAROUND -# define FOC_ADC_INJ_CHAN_REQUIRED (CONFIG_MOTOR_FOC_SHUNTS + 1) -#else -# define FOC_ADC_INJ_CHAN_REQUIRED (CONFIG_MOTOR_FOC_SHUNTS) -#endif - -/* Validate ADC configuration: - * 1. ADC must be supported by chip, - * 2. ADC support for injected channels must be enabled, - * 3. ADC software trigger starts only regular conversion. - */ - -#ifdef CONFIG_STM32_FOC_USE_ADC1 -# ifndef CONFIG_STM32_ADC1 -# error ADC1 not supported ! -# endif -# ifndef ADC1_HAVE_JEXTCFG -# error ADC1 must support JEXTCFG -# endif -# if CONFIG_STM32_ADC1_ANIOC_TRIGGER != 1 -# error CONFIG_STM32_ADC1_ANIOC_TRIGGER must be 1 -# endif -# if CONFIG_STM32_ADC1_INJECTED_CHAN != FOC_ADC_INJ_CHAN_REQUIRED -# error Invalid configuration for ADC1 injected channels -# endif -#endif -#ifdef CONFIG_STM32_FOC_USE_ADC2 -# ifndef CONFIG_STM32_ADC2 -# error ADC2 not supported ! -# endif -# ifndef ADC2_HAVE_JEXTCFG -# error ADC2 must support JEXTCFG -# endif -# if CONFIG_STM32_ADC2_ANIOC_TRIGGER != 1 -# error CONFIG_STM32_ADC2_ANIOC_TRIGGER must be 1 -# endif -# if CONFIG_STM32_ADC2_INJECTED_CHAN != FOC_ADC_INJ_CHAN_REQUIRED -# error Invalid configuration for ADC2 injected channels -# endif -#endif -#ifdef CONFIG_STM32_FOC_USE_ADC3 -# ifndef CONFIG_STM32_ADC3 -# error ADC3 not supported ! -# endif -# ifndef ADC3_HAVE_JEXTCFG -# error ADC3 must support JEXTCFG -# endif -# if CONFIG_STM32_ADC3_ANIOC_TRIGGER != 1 -# error CONFIG_STM32_ADC3_ANIOC_TRIGGER must be 1 -# endif -# if CONFIG_STM32_ADC3_INJECTED_CHAN != FOC_ADC_INJ_CHAN_REQUIRED -# error Invalid configuration for ADC3 injected channels -# endif -#endif -#ifdef CONFIG_STM32_FOC_USE_ADC4 -# ifndef CONFIG_STM32_ADC4 -# error ADC4 not supported ! -# endif -# ifndef ADC4_HAVE_JEXTCFG -# error ADC4 must support JEXTCFG -# endif -# if CONFIG_STM32_ADC4_ANIOC_TRIGGER != 1 -# error CONFIG_STM32_ADC4_ANIOC_TRIGGER must be 1 -# endif -# if CONFIG_STM32_ADC4_INJECTED_CHAN != FOC_ADC_INJ_CHAN_REQUIRED -# error Invalid configuration for ADC4 injected channels -# endif -#endif - -/* Max 3 shunts supported if STM32G4 ADC CHAN0 workaround enabled */ - -#ifdef CONFIG_STM32_FOC_G4_ADCCHAN0_WORKAROUND -# if CONFIG_MOTOR_FOC_SHUNTS > 3 -# error -# endif -#endif - -/* Combine JEXTSEL with JEXTEN default */ - -#ifdef CONFIG_STM32_FOC_FOC0 -# define FOC0_ADC_JEXT (ADC_JEXTREG_JEXTEN_DEFAULT | FOC0_ADC_JEXTSEL) -#endif -#ifdef CONFIG_STM32_FOC_FOC1 -# define FOC1_ADC_JEXT (ADC_JEXTREG_JEXTEN_DEFAULT | FOC1_ADC_JEXTSEL) -#endif - -/* Generalize ADC interrupt flags */ - -#if defined(CONFIG_STM32_HAVE_IP_ADC_V2) -# define FOC_ADC_ISR_FOC ADC_ISR_JEOS -# define FOC_ADC_IER_FOC ADC_IER_JEOS -# define FOC_ADC_ISR_OVR ADC_INT_OVR -#elif defined(CONFIG_STM32_HAVE_IP_ADC_V1) -# define FOC_ADC_ISR_FOC ADC_ISR_JEOC -# define FOC_ADC_IER_FOC ADC_IER_JEOC -# define FOC_ADC_ISR_OVR ADC_SR_OVR -#else -# error Not supported -#endif - -/* We have 3 possible ADC IRQ configuration */ - -#if defined(STM32_IRQ_ADC1) - -/* Only ADC1 supported */ - -# define STM32_IRQ_ADC1_FOC STM32_IRQ_ADC1 - -#elif defined(STM32_IRQ_ADC12) - -/* ADC1 + ADC2 interrupt */ - -# define STM32_IRQ_ADC1_FOC STM32_IRQ_ADC12 -# define STM32_IRQ_ADC2_FOC STM32_IRQ_ADC12 - -/* ADC3 + ADC4 interrupt */ - -# define STM32_IRQ_ADC3_FOC STM32_IRQ_ADC34 -# define STM32_IRQ_ADC4_FOC STM32_IRQ_ADC34 - -#elif defined(STM32_IRQ_ADC) - -/* ADC1 + ADC2 + ADC3 interrupt */ - -# define STM32_IRQ_ADC1_FOC STM32_IRQ_ADC -# define STM32_IRQ_ADC2_FOC STM32_IRQ_ADC -# define STM32_IRQ_ADC3_FOC STM32_IRQ_ADC -#endif - -/* ADC common ***************************************************************/ - -/* Common for ADCv1 */ - -#if defined(CONFIG_STM32_HAVE_IP_ADC_V1) && !defined(HAVE_BASIC_ADC) -# define FOC_ADC_HAVE_CMN (1) -# ifdef CONFIG_STM32_FOC_USE_ADC1 -# define FOC_ADC1_CMN (&g_stm32_foc_adccmn123) -# endif -# ifdef CONFIG_STM32_FOC_USE_ADC2 -# define FOC_ADC2_CMN (&g_stm32_foc_adccmn123) -# endif -# ifdef CONFIG_STM32_FOC_USE_ADC3 -# define FOC_ADC3_CMN (&g_stm32_foc_adccmn123) -# endif -#endif - -/* Common for ADCv1 basic */ - -#if defined(CONFIG_STM32_HAVE_IP_ADC_V1) && defined(HAVE_BASIC_ADC) -# undef FOC_ADC_HAVE_CMN -# ifdef CONFIG_STM32_FOC_USE_ADC1 -# define FOC_ADC1_CMN (0) -# endif -# ifdef CONFIG_STM32_FOC_USE_ADC2 -# define FOC_ADC2_CMN (0) -# endif -# ifdef CONFIG_STM32_FOC_USE_ADC3 -# define FOC_ADC3_CMN (0) -# endif -#endif - -/* Common for ADCv2 */ - -#ifdef CONFIG_STM32_HAVE_IP_ADC_V2 -# define FOC_ADC_HAVE_CMN (1) -# ifdef CONFIG_STM32_FOC_USE_ADC1 -# define FOC_ADC1_CMN (&g_stm32_foc_adccmn12) -# endif -# ifdef CONFIG_STM32_FOC_USE_ADC2 -# define FOC_ADC2_CMN (&g_stm32_foc_adccmn12) -# endif -# ifdef CONFIG_STM32_FOC_USE_ADC3 -# define FOC_ADC3_CMN (&g_stm32_foc_adccmn34) -# endif -# ifdef CONFIG_STM32_FOC_USE_ADC4 -# define FOC_ADC4_CMN (&g_stm32_foc_adccmn34) -# endif -#endif - -/* FOC ADC configuration ****************************************************/ - -#ifdef CONFIG_STM32_FOC_FOC0 -# ifdef CONFIG_STM32_FOC_FOC0_ADC1 -# define FOC0_ADC_IRQ STM32_IRQ_ADC1_FOC -# define FOC0_ADC_CMN FOC_ADC1_CMN -# endif -# ifdef CONFIG_STM32_FOC_FOC0_ADC2 -# define FOC0_ADC_IRQ STM32_IRQ_ADC2_FOC -# define FOC0_ADC_CMN FOC_ADC2_CMN -# endif -# ifdef CONFIG_STM32_FOC_FOC0_ADC3 -# define FOC0_ADC_IRQ STM32_IRQ_ADC3_FOC -# define FOC0_ADC_CMN FOC_ADC3_CMN -# endif -# ifdef CONFIG_STM32_FOC_FOC0_ADC4 -# define FOC0_ADC_IRQ STM32_IRQ_ADC4_FOC -# define FOC0_ADC_CMN FOC_ADC4_CMN -# endif -#endif - -#ifdef CONFIG_STM32_FOC_FOC1 -# ifdef CONFIG_STM32_FOC_FOC1_ADC1 -# define FOC1_ADC_IRQ STM32_IRQ_ADC1_FOC -# define FOC1_ADC_CMN FOC_ADC1_CMN -# endif -# ifdef CONFIG_STM32_FOC_FOC1_ADC2 -# define FOC1_ADC_IRQ STM32_IRQ_ADC2_FOC -# define FOC1_ADC_CMN FOC_ADC2_CMN -# endif -# ifdef CONFIG_STM32_FOC_FOC1_ADC3 -# define FOC1_ADC_IRQ STM32_IRQ_ADC3_FOC -# define FOC1_ADC_CMN FOC_ADC3_CMN -# endif -# ifdef CONFIG_STM32_FOC_FOC1_ADC4 -# define FOC1_ADC_IRQ STM32_IRQ_ADC4_FOC -# define FOC1_ADC_CMN FOC_ADC4_CMN -# endif -#endif - -#ifdef CONFIG_MOTOR_FOC_BEMF_SENSE - -/* Additional checks for BEMF sensing */ - -# if defined(CONFIG_STM32_FOC_FOC0) && defined(CONFIG_STM32_FOC_FOC1) -# error BEMF sensing supported only for one FOC instance enabled -# endif - -# if defined(CONFIG_STM32_FOC_FOC0_ADC2) || defined(CONFIG_STM32_FOC_FOC0_ADC3) -# error FOC must use ADC master -# endif -# if defined(CONFIG_STM32_FOC_FOC1_ADC2) || defined(CONFIG_STM32_FOC_FOC1_ADC3) -# error FOC must use ADC master -# endif - -/* Additional ADC slave in use */ - -# if defined(CONFIG_STM32_FOC_FOC0_ADC1) || defined(CONFIG_STM32_FOC_FOC1_ADC1) -# define CONFIG_STM32_FOC_USE_ADC2 -# endif -# if defined(CONFIG_STM32_FOC_FOC0_ADC3) || defined(CONFIG_STM32_FOC_FOC1_ADC3) -# define CONFIG_STM32_FOC_USE_ADC4 -# endif - -/* The number of required injected channels */ - -# ifdef CONFIG_STM32_FOC_G4_ADCCHAN0_WORKAROUND -# define FOC_VADC_INJ_CHAN_REQUIRED (CONFIG_MOTOR_FOC_PHASES + 1) -# else -# define FOC_VADC_INJ_CHAN_REQUIRED (CONFIG_MOTOR_FOC_PHASES) -# endif - -/* Slave ADC2 */ - -# ifdef CONFIG_STM32_FOC_USE_ADC2 -# ifndef CONFIG_STM32_ADC2 -# error ADC2 not supported ! -# endif -# ifndef ADC2_HAVE_JEXTCFG -# error ADC2 must support JEXTCFG -# endif -# if CONFIG_STM32_ADC2_ANIOC_TRIGGER != 1 -# error CONFIG_STM32_ADC2_ANIOC_TRIGGER must be 1 -# endif -# if CONFIG_STM32_ADC2_INJECTED_CHAN != FOC_VADC_INJ_CHAN_REQUIRED -# error Invalid configuration for ADC2 injected channels -# endif -# endif - -/* Slave ADC4 */ - -# ifdef CONFIG_STM32_FOC_USE_ADC4 -# ifndef CONFIG_STM32_ADC4 -# error ADC4 not supported ! -# endif -# ifndef ADC4_HAVE_JEXTCFG -# error ADC4 must support JEXTCFG -# endif -# if CONFIG_STM32_ADC4_ANIOC_TRIGGER != 1 -# error CONFIG_STM32_ADC4_ANIOC_TRIGGER must be 1 -# endif -# if CONFIG_STM32_ADC4_INJECTED_CHAN != FOC_VADC_INJ_CHAN_REQUIRED -# error Invalid configuration for ADC4 injected channels -# endif -# endif - -#endif - -/* Helper macros ************************************************************/ - -/* Get arch-specific FOC private part */ - -#define STM32_FOCPIRV_FROM_DEV_GET(d) \ - ((struct stm32_foc_priv_s *)(d)->lower->data) - -/* Get board-specific FOC data */ - -#define STM32_FOCBOARD_FROM_DEV_GET(d) \ - ((STM32_FOCPIRV_FROM_DEV_GET(d))->board) - -/* Get arch-specific FOC devices */ - -#define STM32_FOCDEV_FROM_DEV_GET(d) \ - ((STM32_FOCPIRV_FROM_DEV_GET(d))->dev) - -/* Get PWM device */ - -#define PWM_FROM_FOC_DEV_GET(d) (STM32_FOCDEV_FROM_DEV_GET(d)->pwm) - -/* Get ADC device */ - -#define ADC_FROM_FOC_DEV_GET(d) (STM32_FOCDEV_FROM_DEV_GET(d)->adc) -#define VADC_FROM_FOC_DEV_GET(d) (STM32_FOCDEV_FROM_DEV_GET(d)->vadc) - -/* Define PWM all outputs */ - -#ifdef CONFIG_STM32_FOC_HAS_PWM_COMPLEMENTARY -# define PMW_OUTPUTS_ALL_COMP (STM32_PWM_OUT1N| \ - STM32_PWM_OUT2N| \ - STM32_PWM_OUT3N) -#else -# define PMW_OUTPUTS_ALL_COMP (0) -#endif - -#if defined(CONFIG_STM32_FOC_ADC_CCR4) || (CONFIG_MOTOR_FOC_PHASES > 3) -# define PMW_OUTPUTS_ALL_OUT4 (STM32_PWM_OUT4) -#else -# define PMW_OUTPUTS_ALL_OUT4 (0) -#endif - -#define PWM_OUTPUTS_ALL (STM32_PWM_OUT1| \ - STM32_PWM_OUT2| \ - STM32_PWM_OUT3| \ - PMW_OUTPUTS_ALL_COMP| \ - PMW_OUTPUTS_ALL_OUT4) - -/* Enable all PWM outputs at once (include CHAN4 for ADC trigger) */ - -#define PWM_ALL_OUTPUTS_ENABLE(pwm, state) \ - PWM_OUTPUTS_ENABLE(pwm, PWM_OUTPUTS_ALL, state); - -/* Enable/disable ADC interrupts (FOC worker loop) */ - -#define STM32_ADC_ENABLEINT(adc) STM32_ADC_INT_ENABLE(adc, FOC_ADC_IER_FOC) -#define STM32_ADC_DISABLEINT(adc) STM32_ADC_INT_DISABLE(adc, FOC_ADC_IER_FOC) - -/* ADC calibration samples */ - -#define CAL_SAMPLES (5000) - -/* ADC calibration frequency */ - -#define CAL_FREQ (10000) - -/* Define PWM modes to control H-bridge. - * - * Any H-bridge specific configuration can be done with PWM_CHxPOL - * and PWM_CHxIDLE configuration options - */ - -#define PWM_MODE_FOC STM32_CHANMODE_PWM1 -#define PWM_MODE_ADC_TRG STM32_CHANMODE_PWM1 -#define PWM_MODE_HSLO_LSHI STM32_CHANMODE_OCREFHI -#define PWM_MODE_HSHI_LSLO STM32_CHANMODE_OCREFLO - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/* STM32 FOC devices. - * This structure gathers all low level drivers required by FOC device. - */ - -struct stm32_foc_dev_s -{ - uint8_t pwm_inst; /* PWM timer instance */ - uint8_t adc_inst; /* ADC timer instance */ - uint32_t pwm_base; /* PWM timer base */ - uint32_t adc_irq; /* ADC irq */ - uint32_t jextval; /* JEXT configuration */ - - struct stm32_pwm_dev_s *pwm; /* PWM device reference */ - struct adc_dev_s *adc_dev; /* ADC device reference */ - struct stm32_adc_dev_s *adc; /* STM32 ADC device reference */ - - /* Interrupt handler for FOC device */ - - int (*adc_isr)(struct foc_dev_s *dev); - -#ifdef CONFIG_MOTOR_FOC_BEMF_SENSE - struct adc_dev_s *vadc_dev; /* ADC device reference (voltage ) */ - struct stm32_adc_dev_s *vadc; /* STM32 ADC device reference (voltage) */ -#endif -}; - -/* STM32 FOC common data */ - -struct stm32_foc_adccmn_s -{ - uint8_t cntr; /* ADC common counter */ - mutex_t lock; /* Lock data */ -}; - -/* STM32 FOC volatile data */ - -struct stm32_foc_data_s -{ - foc_current_t curr[CONFIG_MOTOR_FOC_PHASES]; /* Current */ - uint8_t notifier_div; /* FOC notifier prescaler */ - uint32_t adc_freq; /* ADC interrupts frequency */ - uint32_t per; /* PWM timer period (ARR) */ - uint32_t adcint_cntr; /* ADC interrupt counter */ - uint32_t curr_offset[CONFIG_MOTOR_FOC_SHUNTS]; /* ADC current offset */ - int16_t curr_raw[CONFIG_MOTOR_FOC_SHUNTS]; /* ADC current RAW */ -#ifdef CONFIG_MOTOR_FOC_BEMF_SENSE - foc_voltage_t volt[CONFIG_MOTOR_FOC_PHASES]; /* Voltage */ - uint32_t volt_offset[CONFIG_MOTOR_FOC_PHASES]; /* ADC voltage offset */ - int16_t volt_raw[CONFIG_MOTOR_FOC_PHASES]; /* ADC voltage RAW */ -#endif -}; - -/* STM32 FOC private */ - -struct stm32_foc_priv_s -{ - /* Volatile data */ - - struct stm32_foc_data_s data; - - /* ADC calbration done */ - - sem_t cal_done_sem; - - /* STM32 FOC devices */ - - struct stm32_foc_dev_s *dev; - - /* Board-specific data */ - - struct stm32_foc_board_s *board; - - /* Upper-half FOC controller callbacks */ - - const struct foc_callbacks_s *cb; - -#ifdef FOC_ADC_HAVE_CMN - /* Common data */ - - struct stm32_foc_adccmn_s *adc_cmn; -#endif -}; - -/**************************************************************************** - * Private Function Protototypes - ****************************************************************************/ - -/* FOC lower-half operations */ - -static int stm32_foc_configure(struct foc_dev_s *dev, - struct foc_cfg_s *cfg); -static int stm32_foc_setup(struct foc_dev_s *dev); -static int stm32_foc_shutdown(struct foc_dev_s *dev); -static int stm32_foc_start(struct foc_dev_s *dev, bool state); -static int stm32_foc_pwm_duty_set(struct foc_dev_s *dev, - foc_duty_t *duty); -static int stm32_foc_pwm_off(struct foc_dev_s *dev, bool off); -static int stm32_foc_info_get(struct foc_dev_s *dev, - struct foc_info_s *info); -static int stm32_foc_ioctl(struct foc_dev_s *dev, int cmd, - unsigned long arg); -static int stm32_foc_bind(struct foc_dev_s *dev, - struct foc_callbacks_s *cb); -static int stm32_foc_fault_clear(struct foc_dev_s *dev); -#ifdef CONFIG_MOTOR_FOC_TRACE -int stm32_foc_trace_init(struct foc_dev_s *dev); -void stm32_foc_trace(struct foc_dev_s *dev, int type, bool state); -#endif - -/* ADC handlers */ - -static int stm32_foc_adc_handler(int irq, void *context, void *arg); -static int stm32_foc_adc_calibration_handler(struct foc_dev_s *dev); -static int stm32_foc_worker_handler(struct foc_dev_s *dev); - -/* Helpers */ - -static void stm32_foc_curr_get(struct foc_dev_s *dev, - int16_t *curr, int shunts); -#ifdef CONFIG_MOTOR_FOC_BEMF_SENSE -static void stm32_foc_volt_get(struct foc_dev_s *dev, int16_t *volt); -#endif -static int stm32_foc_notifier_cfg(struct foc_dev_s *dev, uint32_t freq); -static int stm32_foc_pwm_cfg(struct foc_dev_s *dev, uint32_t freq); -static int stm32_foc_adc_cfg(struct foc_dev_s *dev); -static int stm32_foc_pwm_start(struct foc_dev_s *dev, bool state); -static int stm32_foc_adc_start(struct foc_dev_s *dev, bool state); -static int stm32_foc_calibration_start(struct foc_dev_s *dev); -static int stm32_foc_pwm_freq_set(struct foc_dev_s *dev, uint32_t freq); - -#if defined(CONFIG_STM32_FOC_ADC_CCR4) -static void stm32_foc_adc_ccr4_trg_set(struct foc_dev_s *dev, - uint32_t offset); -#elif defined(CONFIG_STM32_FOC_ADC_TRGO) -static void stm32_foc_adc_trgo_trg_set(struct foc_dev_s *dev, - uint8_t rcr); -#else -# error Invalid FOC ADC trigger -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -#ifdef FOC_ADC_HAVE_CMN -# ifdef CONFIG_STM32_HAVE_IP_ADC_V1 -/* Common for ADC123 */ - -static struct stm32_foc_adccmn_s g_stm32_foc_adccmn123 = -{ - .cntr = 0, - .lock = NXMUTEX_INITIALIZER, -}; -# endif /* CONFIG_STM32_HAVE_IP_ADC_V1 */ - -# ifdef CONFIG_STM32_HAVE_IP_ADC_V2 -# if defined(CONFIG_STM32_HAVE_ADC1) || defined(CONFIG_STM32_HAVE_ADC2) -/* Common for ADC12 */ - -static struct stm32_foc_adccmn_s g_stm32_foc_adccmn12 = -{ - .cntr = 0, - .lock = NXMUTEX_INITIALIZER, -}; -# endif /* CONFIG_STM32_HAVE_ADC1 || CONFIG_STM32_HAVE_ADC2 */ -# if defined(CONFIG_STM32_HAVE_ADC3) || defined(CONFIG_STM32_HAVE_ADC4) -/* Common for ADC34 */ - -static struct stm32_foc_adccmn_s g_stm32_foc_adccmn34 = -{ - .cntr = 0, - .lock = NXMUTEX_INITIALIZER, -}; -# endif /* CONFIG_STM32_HAVE_ADC3 || CONFIG_STM32_HAVE_ADC4 */ -# endif /* CONFIG_STM32_HAVE_IP_ADC_V2 */ -#endif /* FOC_ADC_HAVE_CMN */ - -/* STM32 specific FOC data */ - -static struct stm32_foc_dev_s g_stm32_foc_dev[CONFIG_MOTOR_FOC_INST]; -static struct stm32_foc_priv_s g_stm32_foc_priv[CONFIG_MOTOR_FOC_INST]; - -/* STM32 specific FOC ops */ - -static struct foc_lower_ops_s g_stm32_foc_ops = -{ - .configure = stm32_foc_configure, - .setup = stm32_foc_setup, - .shutdown = stm32_foc_shutdown, - .start = stm32_foc_start, - .pwm_duty_set = stm32_foc_pwm_duty_set, - .pwm_off = stm32_foc_pwm_off, - .info_get = stm32_foc_info_get, - .ioctl = stm32_foc_ioctl, - .bind = stm32_foc_bind, - .fault_clear = stm32_foc_fault_clear, -#ifdef CONFIG_MOTOR_FOC_TRACE - .trace = stm32_foc_trace -#endif -}; - -/* FOC lower-half */ - -static struct foc_lower_s g_stm32_foc_lower[CONFIG_MOTOR_FOC_INST]; - -/* FOC upper-half device data */ - -static struct foc_dev_s g_foc_dev[CONFIG_MOTOR_FOC_INST]; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -#if (CONFIG_MOTOR_FOC_INST > 1) - -/**************************************************************************** - * Name: stm32_foc_sync_all - * - * Description: - * Synchronise all FOC PWM timers - * - ****************************************************************************/ - -void stm32_foc_sync_all(void) -{ - struct foc_dev_s *dev = NULL; - struct stm32_foc_dev_s *foc_dev = NULL; - uint32_t egr_reg[CONFIG_MOTOR_FOC_INST]; - int i = 0; - - /* Get registers to write */ - - for (i = 0; i < CONFIG_MOTOR_FOC_INST; i += 1) - { - /* Get FOC device */ - - dev = &g_foc_dev[i]; - - /* Get FOC lower half devices */ - - foc_dev = STM32_FOCDEV_FROM_DEV_GET(dev); - - /* Store EGR register address */ - - egr_reg[i] = foc_dev->pwm_base + STM32_GTIM_EGR_OFFSET; - } - - /* Write all registers at once */ - - for (i = 0; i < CONFIG_MOTOR_FOC_INST; i += 1) - { - /* Force update event to reset CNTR */ - - putreg32(GTIM_EGR_UG, egr_reg[i]); - } -} -#endif - -/**************************************************************************** - * Name: stm32_foc_pwm_cfg - * - * Description: - * PWM configuration for the FOC device - * - ****************************************************************************/ - -static int stm32_foc_pwm_cfg(struct foc_dev_s *dev, uint32_t freq) -{ - struct stm32_foc_board_s *board = STM32_FOCBOARD_FROM_DEV_GET(dev); - struct stm32_pwm_dev_s *pwm = PWM_FROM_FOC_DEV_GET(dev); - int ret = OK; - - DEBUGASSERT(dev); - DEBUGASSERT(board); - DEBUGASSERT(pwm); - DEBUGASSERT(freq > 0); - - /* Set phases PWM frequency */ - - ret = stm32_foc_pwm_freq_set(dev, freq); - if (ret < 0) - { - goto errout; - } - -#ifdef CONFIG_STM32_FOC_HAS_PWM_COMPLEMENTARY - /* Configure deadtime */ - - PWM_DT_UPDATE(pwm, (uint8_t)board->data->pwm_dt); -#else - UNUSED(board); -#endif - - /* Configure PWM mode for PWM outputs */ - - PWM_MODE_UPDATE(pwm, STM32_PWM_CHAN1, PWM_MODE_FOC); - PWM_MODE_UPDATE(pwm, STM32_PWM_CHAN2, PWM_MODE_FOC); -#if CONFIG_MOTOR_FOC_PHASES > 2 - PWM_MODE_UPDATE(pwm, STM32_PWM_CHAN3, PWM_MODE_FOC); -#endif -#if CONFIG_MOTOR_FOC_PHASES > 3 - PWM_MODE_UPDATE(pwm, STM32_PWM_CHAN4, PWM_MODE_FOC); -#endif - - /* Dump PWM regs */ - - PWM_DUMP_REGS(pwm, NULL); - -errout: - return ret; -} - -/**************************************************************************** - * Name: stm32_foc_pwm_freq_set - * - * Description: - * Configure the PWM frequency for the FOC device - * - ****************************************************************************/ - -static int stm32_foc_pwm_freq_set(struct foc_dev_s *dev, uint32_t freq) -{ - struct stm32_foc_priv_s *priv = STM32_FOCPIRV_FROM_DEV_GET(dev); - struct stm32_pwm_dev_s *pwm = PWM_FROM_FOC_DEV_GET(dev); - int ret = OK; - - DEBUGASSERT(dev); - DEBUGASSERT(priv); - DEBUGASSERT(pwm); - DEBUGASSERT(freq > 0); - - /* Update the PWM frequency. - * IMPORTANT: must be x2 as the PWM is in center-aligned mode. - */ - - ret = PWM_FREQ_UPDATE(pwm, (freq * 2)); - if (ret < 0) - { - goto errout; - } - - /* Store the PWM period to improve some future calculations */ - - priv->data.per = PWM_ARR_GET(pwm); - -errout: - return ret; -} - -/**************************************************************************** - * Name: stm32_foc_start - * - * Description: - * Start or stop the FOC lower-half operations - * - ****************************************************************************/ - -static int stm32_foc_start(struct foc_dev_s *dev, bool state) -{ - int ret = OK; - - DEBUGASSERT(dev); - - /* Start PWM */ - - ret = stm32_foc_pwm_start(dev, state); - if (ret < 0) - { - mtrerr("stm32_foc_pwm_start failed %d\n", ret); - goto errout; - } - - /* Start ADC */ - - ret = stm32_foc_adc_start(dev, state); - if (ret < 0) - { - mtrerr("stm32_foc_adc_start failed %d\n", ret); - goto errout; - } - -errout: - return ret; -} - -/**************************************************************************** - * Name: stm32_foc_pwm_start - * - * Description: - * Start or stop PWM - * - ****************************************************************************/ - -static int stm32_foc_pwm_start(struct foc_dev_s *dev, bool state) -{ - struct stm32_foc_board_s *board = STM32_FOCBOARD_FROM_DEV_GET(dev); - struct stm32_pwm_dev_s *pwm = PWM_FROM_FOC_DEV_GET(dev); - - DEBUGASSERT(dev); - DEBUGASSERT(board); - DEBUGASSERT(pwm); - - if (!dev->state.pwm_off) - { - /* Enable PWM outputs */ - - PWM_ALL_OUTPUTS_ENABLE(pwm, state); - } - - /* Call board-specific logic */ - - board->ops->pwm_start(dev, state); - - return OK; -} - -/**************************************************************************** - * Name: stm32_foc_adc_start - * - * Description: - * Start or stop ADC - * - ****************************************************************************/ - -static int stm32_foc_adc_start(struct foc_dev_s *dev, bool state) -{ - struct stm32_foc_dev_s *foc_dev = STM32_FOCDEV_FROM_DEV_GET(dev); - struct stm32_adc_dev_s *adc = ADC_FROM_FOC_DEV_GET(dev); - - DEBUGASSERT(dev); - DEBUGASSERT(foc_dev); - DEBUGASSERT(adc); - - if (state == false) - { - /* Disable ADC interrupts */ - - STM32_ADC_DISABLEINT(adc); - - /* Disable ADC injected conversion */ - - STM32_ADC_INJ_STARTCONV(adc, false); - - /* Reset ADC injected trigger */ - - STM32_ADC_JEXTCFG_SET(adc, foc_dev->jextval); - } - else - { - /* Configure ADC injected trigger */ - - STM32_ADC_JEXTCFG_SET(adc, foc_dev->jextval); - - /* Enable ADC interrupts */ - - STM32_ADC_ENABLEINT(adc); - - /* Enable ADC injected conversion */ - - STM32_ADC_INJ_STARTCONV(adc, true); - } - - return OK; -} - -/**************************************************************************** - * Name: stm32_foc_adc_cfg - * - * Description: - * Configure ADC for FOC worker - * - ****************************************************************************/ - -static int stm32_foc_adc_cfg(struct foc_dev_s *dev) -{ - struct stm32_foc_dev_s *foc_dev = STM32_FOCDEV_FROM_DEV_GET(dev); - - DEBUGASSERT(dev); - DEBUGASSERT(foc_dev); - - /* Set ADC interrupt handler to FOC worker */ - - foc_dev->adc_isr = stm32_foc_worker_handler; - - return OK; -} - -#if defined(CONFIG_STM32_FOC_ADC_CCR4) - -/**************************************************************************** - * Name: stm32_foc_adc_ccr4_trg_set - * - * Description: - * Configure ADC CCR4 trigger for FOC controller - * - ****************************************************************************/ - -static void stm32_foc_adc_ccr4_trg_set(struct foc_dev_s *dev, - uint32_t offset) -{ - struct stm32_pwm_dev_s *pwm = PWM_FROM_FOC_DEV_GET(dev); - - DEBUGASSERT(dev); - DEBUGASSERT(pwm); - DEBUGASSERT(offset > 0); - - /* Configure PWM mode for ADC trigger - * NOTE: - * For PWM mode 1 we have V7 when CRR=0 and V0 when CRR = ARR - * For PWM mode 2 we have V7 when CRR=ARR and V0 when CRR = 0 - */ - - PWM_MODE_UPDATE(pwm, STM32_PWM_CHAN4, PWM_MODE_ADC_TRG); - - /* Set CCR4 */ - - PWM_CCR_UPDATE(pwm, STM32_PWM_CHAN4, offset); -} - -#elif defined(CONFIG_STM32_FOC_ADC_TRGO) - -/**************************************************************************** - * Name: stm32_foc_adc_trgo_trg_set - * - * Description: - * Configure ADC TRGO trigger for FOC controller - * - ****************************************************************************/ - -static void stm32_foc_adc_trgo_trg_set(struct foc_dev_s *dev, - uint8_t rcr) -{ - struct stm32_pwm_dev_s *pwm = PWM_FROM_FOC_DEV_GET(dev); - - DEBUGASSERT(dev); - DEBUGASSERT(pwm); - - /* We want TRGO on update events only if overflow (ARR): - * 1. RCR must be configured when timer is enabled - * 2. RCR must be odd value - */ - - if (rcr % 2 == 0) - { - rcr -= 1; - } - - /* Configure RCR */ - - PWM_RCR_UPDATE(pwm, rcr); - - /* Configure TRGO */ - - PWM_TRGO_SET(pwm, FOC_PWM_TRGO); -} -#else -# error Invalid FOC ADC trigger -#endif - -/**************************************************************************** - * Name: stm32_foc_configure - * - * Description: - * Arch-specific FOC device configuration - * - ****************************************************************************/ - -static int stm32_foc_configure(struct foc_dev_s *dev, - struct foc_cfg_s *cfg) -{ - struct stm32_foc_priv_s *priv = STM32_FOCPIRV_FROM_DEV_GET(dev); - struct stm32_foc_board_s *board = STM32_FOCBOARD_FROM_DEV_GET(dev); - int ret = OK; - - DEBUGASSERT(dev); - DEBUGASSERT(cfg); - DEBUGASSERT(priv); - DEBUGASSERT(board); - DEBUGASSERT(cfg->pwm_freq > 0); - DEBUGASSERT(cfg->notifier_freq > 0); - - /* Configure ADC */ - - ret = stm32_foc_adc_cfg(dev); - if (ret < 0) - { - mtrerr("stm32_foc_adc_cfg failed %d\n", ret); - goto errout; - } - - /* Configure PWM */ - - ret = stm32_foc_pwm_cfg(dev, cfg->pwm_freq); - if (ret < 0) - { - mtrerr("stm32_foc_pwm_cfg failed %d\n", ret); - goto errout; - } - - /* Configure FOC notifier */ - - ret = stm32_foc_notifier_cfg(dev, cfg->notifier_freq); - if (ret < 0) - { - mtrerr("stm32_foc_notifier_cfg failed %d\n", ret); - goto errout; - } - - /* Configure ADC trigger - must be after PWM frequency set */ - - DEBUGASSERT(priv->data.per != 0); - -#if defined(CONFIG_STM32_FOC_ADC_CCR4) - stm32_foc_adc_ccr4_trg_set(dev, (priv->data.per - ADC_TRIGGER_OFFSET)); -#elif defined(CONFIG_STM32_FOC_ADC_TRGO) - stm32_foc_adc_trgo_trg_set(dev, (dev->cfg.pwm_freq / - priv->data.adc_freq) * 2); -#else -# error Invalid FOC ADC trigger -#endif - - /* Reset ADC interrupts counter */ - - priv->data.adcint_cntr = 0; - - /* REVISIT: synchronise instances if TRGO trigger selected */ - -#if (CONFIG_MOTOR_FOC_INST > 1) -# if defined(CONFIG_STM32_FOC_ADC_TRGO) -# error stm32_foc_sync_all breaks TRGO event on V0 vector -# endif - - /* Sync all FOC PWM timers instances. - * IMPORTANT: This must be done after PWM frequency update ! - */ - - stm32_foc_sync_all(); -#endif - -errout: - return ret; -} - -/**************************************************************************** - * Name: stm32_foc_setup - * - * Description: - * Arch-specific FOC device setup - * - ****************************************************************************/ - -static int stm32_foc_setup(struct foc_dev_s *dev) -{ - struct stm32_foc_dev_s *foc_dev = STM32_FOCDEV_FROM_DEV_GET(dev); - struct stm32_foc_board_s *board = STM32_FOCBOARD_FROM_DEV_GET(dev); - struct stm32_foc_priv_s *priv = STM32_FOCPIRV_FROM_DEV_GET(dev); - struct stm32_adc_dev_s *adc = ADC_FROM_FOC_DEV_GET(dev); -#ifdef CONFIG_MOTOR_FOC_BEMF_SENSE - struct stm32_adc_dev_s *vadc = VADC_FROM_FOC_DEV_GET(dev); -#endif - struct adc_sample_time_s stime; - int ret = OK; - - DEBUGASSERT(dev); - DEBUGASSERT(foc_dev); - DEBUGASSERT(board); - DEBUGASSERT(priv); - DEBUGASSERT(adc); -#ifdef FOC_ADC_HAVE_CMN - DEBUGASSERT(priv->adc_cmn); -#endif - - /* Call board-specific setup - must be done before TIM enable */ - - ret = board->ops->setup(dev); - if (ret < 0) - { - mtrerr("board->setup failed %d\n", ret); - goto errout; - } - - /* Setup ADC */ - - STM32_ADC_SETUP(foc_dev->adc); - -#ifdef CONFIG_MOTOR_FOC_BEMF_SENSE - /* Setup slave ADC */ - - STM32_ADC_SETUP(foc_dev->vadc); - - /* Disable interrupts for slave ADC */ - - STM32_ADC_DISABLEINT(foc_dev->vadc); - - /* Disable master and slave ADC */ - - STM32_ADC_ENABLE(foc_dev->adc, false); - STM32_ADC_ENABLE(foc_dev->vadc, false); - - /* Configure dual injected simultaneous only mode */ - - STM32_ADC_MULTICFG(foc_dev->vadc, ADC_MULTIMODE_ISM2); - - /* Enable master and slave ADC */ - - STM32_ADC_ENABLE(foc_dev->adc, true); - STM32_ADC_ENABLE(foc_dev->vadc, true); -#endif - -#ifdef FOC_ADC_HAVE_CMN - /* Lock ADC common data */ - - ret = nxmutex_lock(&priv->adc_cmn->lock); - if (ret < 0) - { - goto errout; - } - - /* Only if first device */ - - if (priv->adc_cmn->cntr == 0) - { - /* Enable ADC interrupts */ - - up_enable_irq(foc_dev->adc_irq); - } - - /* Increase counter */ - - priv->adc_cmn->cntr += 1; - - /* Unlock ADC common data */ - - nxmutex_unlock(&priv->adc_cmn->lock); -#endif - - /* Setup PWM */ - - PWM_SETUP(foc_dev->pwm); - PWM_TIM_ENABLE(foc_dev->pwm, true); - - /* Stop ADC and PWM */ - - stm32_foc_pwm_start(dev, false); - stm32_foc_adc_start(dev, false); - - /* Reset ADC handler */ - - foc_dev->adc_isr = NULL; - - /* Configure sample times for ADC channels */ - - memset(&stime, 0, sizeof(struct adc_sample_time_s)); - - stime.channels_nbr = board->data->adc_cfg->nchan; - stime.channel = board->data->adc_cfg->stime; - - STM32_ADC_SAMPLETIME_SET(adc, &stime); - STM32_ADC_SAMPLETIME_WRITE(adc); - -#ifdef CONFIG_MOTOR_FOC_BEMF_SENSE - /* Configure sample times for BEMF channels */ - - memset(&stime, 0, sizeof(struct adc_sample_time_s)); - - stime.channels_nbr = board->data->vadc_cfg->nchan; - stime.channel = board->data->vadc_cfg->stime; - - STM32_ADC_SAMPLETIME_SET(vadc, &stime); - STM32_ADC_SAMPLETIME_WRITE(vadc); -#endif - - /* Set the priority of the ADC interrupt vector */ - - ret = up_prioritize_irq(foc_dev->adc_irq, NVIC_SYSH_PRIORITY_DEFAULT); - if (ret < 0) - { - mtrerr("up_prioritize_irq failed: %d\n", ret); - goto errout; - } - - /* Attach the ADC interrupt handler */ - - ret = irq_attach(foc_dev->adc_irq, stm32_foc_adc_handler, NULL); - if (ret < 0) - { - mtrerr("irq_attach failed: %d\n", ret); - goto errout; - } - -#ifdef CONFIG_MOTOR_FOC_TRACE - /* Initialize trace interface */ - - ret = stm32_foc_trace_init(dev); - if (ret < 0) - { - mtrerr("stm32_foc_trace_init failed %d\n", ret); - goto errout; - } -#endif - - /* Start hardware calibration */ - - ret = stm32_foc_calibration_start(dev); - if (ret < 0) - { - mtrerr("stm32_foc_calibration_start failed %d\n", ret); - goto errout; - } - - /* Dump ADC regs */ - - STM32_ADC_DUMP_REGS(adc); -#ifdef CONFIG_MOTOR_FOC_BEMF_SENSE - STM32_ADC_DUMP_REGS(vadc); -#endif - -errout: - return ret; -} - -/**************************************************************************** - * Name: stm32_foc_shutdown - * - * Description: - * Arch-specific FOC device shutdown - * - ****************************************************************************/ - -static int stm32_foc_shutdown(struct foc_dev_s *dev) -{ - struct stm32_foc_dev_s *foc_dev = STM32_FOCDEV_FROM_DEV_GET(dev); - struct stm32_foc_board_s *board = STM32_FOCBOARD_FROM_DEV_GET(dev); - struct stm32_foc_priv_s *priv = STM32_FOCPIRV_FROM_DEV_GET(dev); - int ret = OK; - - DEBUGASSERT(dev); - DEBUGASSERT(foc_dev); - DEBUGASSERT(board); - DEBUGASSERT(priv); - - /* Disable PWM */ - - PWM_TIM_ENABLE(foc_dev->pwm, false); - PWM_SHUTDOWN(foc_dev->pwm); - - /* Reset ADC interrupt handler */ - - foc_dev->adc_isr = NULL; - - /* Deinitialize ADC */ - - STM32_ADC_SHUTDOWN(foc_dev->adc); - -#ifdef FOC_ADC_HAVE_CMN - /* Lock ADC common data */ - - ret = nxmutex_lock(&priv->adc_cmn->lock); - if (ret < 0) - { - goto errout; - } - - /* Decrease counter */ - - priv->adc_cmn->cntr -= 1; - - /* Deinitialize ADC only if last device */ - - if (priv->adc_cmn->cntr == 0) -#endif - { - /* Disable ADC interrupts */ - - up_disable_irq(foc_dev->adc_irq); - } - -#ifdef FOC_ADC_HAVE_CMN - /* Unlock ADC common data */ - - nxmutex_unlock(&priv->adc_cmn->lock); -#endif - - /* Call board-specific shutdown */ - - board->ops->shutdown(dev); - - /* Reset STM32 FOC volatile data */ - - memset(&priv->data, 0, sizeof(struct stm32_foc_data_s)); - -#ifdef FOC_ADC_HAVE_CMN -errout: -#endif - return ret; -} - -/**************************************************************************** - * Name: stm32_foc_ioctl - * - * Description: - * Arch-specific FOC device IOCTL - * - ****************************************************************************/ - -static int stm32_foc_ioctl(struct foc_dev_s *dev, int cmd, - unsigned long arg) -{ - struct stm32_foc_board_s *board = STM32_FOCBOARD_FROM_DEV_GET(dev); - - if (board->ops->ioctl != NULL) - { - return board->ops->ioctl(dev, cmd, arg); - } - - return -ENOTTY; -} - -/**************************************************************************** - * Name: stm32_foc_calibration_handler - * - * Description: - * ADC interrupt handler for FOC calibration - * - ****************************************************************************/ - -static int stm32_foc_adc_calibration_handler(struct foc_dev_s *dev) -{ - struct stm32_foc_priv_s *priv = STM32_FOCPIRV_FROM_DEV_GET(dev); - int i = 0; - - DEBUGASSERT(dev); - DEBUGASSERT(priv); - - if (priv->data.adcint_cntr < CAL_SAMPLES) - { - /* Get raw current samples */ - - stm32_foc_curr_get(dev, priv->data.curr_raw, CONFIG_MOTOR_FOC_SHUNTS); - - /* Get sum */ - - for (i = 0; i < CONFIG_MOTOR_FOC_SHUNTS; i += 1) - { - priv->data.curr_offset[i] += priv->data.curr_raw[i]; - } - } - - else if (priv->data.adcint_cntr == CAL_SAMPLES) - { - /* Get average offset */ - - for (i = 0; i < CONFIG_MOTOR_FOC_SHUNTS; i += 1) - { - priv->data.curr_offset[i] = - (priv->data.curr_offset[i] / CAL_SAMPLES); - } - - /* Post semaphore that calibration is done */ - - nxsem_post(&priv->cal_done_sem); - } - else - { - /* Calibration completed */ - } - - return OK; -} - -/**************************************************************************** - * Name: stm32_foc_adc_handler - * - * Description: - * ADC interrupt handler - * - ****************************************************************************/ - -static int stm32_foc_adc_handler(int irq, void *context, void *arg) -{ - struct foc_dev_s *dev = NULL; - struct stm32_foc_priv_s *priv = NULL; -#ifdef CONFIG_MOTOR_FOC_TRACE - struct stm32_foc_board_s *board = NULL; -#endif - struct stm32_adc_dev_s *adc = NULL; - struct stm32_foc_dev_s *foc_dev = NULL; - uint32_t pending = 0; - int ret = OK; - int i = 0; - - UNUSED(irq); - UNUSED(context); - UNUSED(arg); - - /* Loop through all FOC instances to prevent context switching if - * all instances are synchronized. - */ - - for (i = 0; i < CONFIG_MOTOR_FOC_INST; i += 1) - { - /* Reset pointer to a device */ - - dev = NULL; - - /* Get ADC device associated with FOC device */ - - adc = ADC_FROM_FOC_DEV_GET(&g_foc_dev[i]); - DEBUGASSERT(adc); - - /* Get ADC pending interrupts */ - - pending = STM32_ADC_INT_GET(adc); - - /* Only if end of injected sequence */ - - if (pending & FOC_ADC_ISR_FOC) - { - /* Found device with penidng ADC interrupt */ - - dev = &g_foc_dev[i]; - } - - /* Handle pending interrupt for device */ - - if (dev != NULL) - { - priv = STM32_FOCPIRV_FROM_DEV_GET(dev); - DEBUGASSERT(priv); - - foc_dev = STM32_FOCDEV_FROM_DEV_GET(dev); - DEBUGASSERT(foc_dev); - -#ifdef CONFIG_MOTOR_FOC_TRACE - board = STM32_FOCBOARD_FROM_DEV_GET(dev); - DEBUGASSERT(board); - - board->ops->trace(dev, FOC_TRACE_LOWER, true); -#endif - /* Clear pending */ - - STM32_ADC_INT_ACK(adc, pending); - - /* Call interrupt handler if registered */ - - if (foc_dev->adc_isr != NULL) - { - ret = foc_dev->adc_isr(dev); - if (ret < 0) - { - DEBUGPANIC(); - } - } - - /* Increase interrupt counter */ - - priv->data.adcint_cntr += 1; - -#ifdef CONFIG_MOTOR_FOC_TRACE - board->ops->trace(dev, FOC_TRACE_LOWER, false); -#endif - } - } - - return ret; -} - -/**************************************************************************** - * Name: stm32_foc_worker_handler - * - * Description: - * Handle ADC conversion and do FOC device work. - * - ****************************************************************************/ - -static int stm32_foc_worker_handler(struct foc_dev_s *dev) -{ - struct stm32_foc_priv_s *priv = STM32_FOCPIRV_FROM_DEV_GET(dev); - struct stm32_foc_board_s *board = STM32_FOCBOARD_FROM_DEV_GET(dev); - struct stm32_adc_dev_s *adc = ADC_FROM_FOC_DEV_GET(dev); - int ret = OK; - - DEBUGASSERT(dev); - DEBUGASSERT(priv); - DEBUGASSERT(adc); - DEBUGASSERT(board); - DEBUGASSERT(priv->cb); - DEBUGASSERT(priv->cb->notifier); - - if (priv->data.adcint_cntr % priv->data.notifier_div == 0) - { - /* Get raw current samples */ - - stm32_foc_curr_get(dev, priv->data.curr_raw, CONFIG_MOTOR_FOC_SHUNTS); - - /* Get phase currents */ - - ret = board->ops->current_get(dev, - priv->data.curr_raw, - priv->data.curr); - -#ifdef CONFIG_MOTOR_FOC_BEMF_SENSE - /* Get raw voltage samples */ - - stm32_foc_volt_get(dev, priv->data.volt_raw); - - /* Get BEMF voltages */ - - ret = board->ops->voltage_get(dev, - priv->data.volt_raw, - priv->data.volt); -#endif - - /* Call upper-half worker callback */ - -#ifdef CONFIG_MOTOR_FOC_BEMF_SENSE - priv->cb->notifier(dev, priv->data.curr, priv->data.volt); -#else - priv->cb->notifier(dev, priv->data.curr, NULL); -#endif - } - - return ret; -} - -/**************************************************************************** - * Name: stm32_foc_calibration_start - * - * Description: - * Start FOC hardware calibration (ADC offsets) - * - ****************************************************************************/ - -static int stm32_foc_calibration_start(struct foc_dev_s *dev) -{ - struct stm32_foc_dev_s *foc_dev = STM32_FOCDEV_FROM_DEV_GET(dev); - struct stm32_foc_priv_s *priv = STM32_FOCPIRV_FROM_DEV_GET(dev); - struct stm32_foc_board_s *board = STM32_FOCBOARD_FROM_DEV_GET(dev); - struct stm32_pwm_dev_s *pwm = PWM_FROM_FOC_DEV_GET(dev); - struct stm32_adc_dev_s *adc = ADC_FROM_FOC_DEV_GET(dev); -#ifdef CONFIG_MOTOR_FOC_BEMF_SENSE - struct stm32_adc_dev_s *vadc = VADC_FROM_FOC_DEV_GET(dev); -#endif - uint8_t i = 0; - uint8_t ch = 0; - int ret = OK; - - DEBUGASSERT(dev); - DEBUGASSERT(foc_dev); - DEBUGASSERT(priv); - DEBUGASSERT(board); - DEBUGASSERT(pwm); - DEBUGASSERT(adc); - - /* Call board-specific */ - - board->ops->calibration(dev, true); - - /* Force high side transistors to low state and - * low side tranisstors to high state - */ - - PWM_MODE_UPDATE(pwm, STM32_PWM_CHAN1, PWM_MODE_HSLO_LSHI); - PWM_MODE_UPDATE(pwm, STM32_PWM_CHAN2, PWM_MODE_HSLO_LSHI); -#if CONFIG_MOTOR_FOC_PHASES > 2 - PWM_MODE_UPDATE(pwm, STM32_PWM_CHAN3, PWM_MODE_HSLO_LSHI); -#endif -#if CONFIG_MOTOR_FOC_PHASES > 3 - PWM_MODE_UPDATE(pwm, STM32_PWM_CHAN4, PWM_MODE_HSLO_LSHI); -#endif - - /* Set PWM to trigger ADC */ - - ret = stm32_foc_pwm_freq_set(dev, CAL_FREQ); - if (ret < 0) - { - goto errout; - } - - /* Configure ADC interrupt handler to calibration */ - - foc_dev->adc_isr = stm32_foc_adc_calibration_handler; - - /* Configure ADC trigger - must be after PWM frequency set */ - - DEBUGASSERT(priv->data.per != 0); - -#if defined(CONFIG_STM32_FOC_ADC_CCR4) - stm32_foc_adc_ccr4_trg_set(dev, (priv->data.per - ADC_TRIGGER_OFFSET)); -#elif defined(CONFIG_STM32_FOC_ADC_TRGO) - stm32_foc_adc_trgo_trg_set(dev, 1); -#else -# error Invalid FOC ADC trigger -#endif - - /* Reset ADC interrupts counter */ - - priv->data.adcint_cntr = 0; - - /* Start ADC and PWM */ - - stm32_foc_adc_start(dev, true); - stm32_foc_pwm_start(dev, true); - - /* Wait for calibration done semaphore - * All work is done in adc_calibration_handler - */ - - ret = nxsem_wait_uninterruptible(&priv->cal_done_sem); - if (ret < 0) - { - goto errout; - } - - /* Stop ADC and PWM */ - - stm32_foc_pwm_start(dev, false); - stm32_foc_adc_start(dev, false); - - /* Reset ADC interrupt handler */ - - foc_dev->adc_isr = NULL; - - /* Clear last ADC data */ - - for (i = 0; i < CONFIG_MOTOR_FOC_SHUNTS; i += 1) - { - priv->data.curr_raw[i] = 0; - } - - /* Set ADC hardware offset for current channels (only injected channels) */ - - for (i = 0; i < CONFIG_MOTOR_FOC_SHUNTS; i += 1) - { - /* Get channel */ - - ch = board->data->adc_cfg->chan[board->data->adc_cfg->regch + i]; - - /* Write offset */ - - STM32_ADC_OFFSET_SET(adc, ch, i, priv->data.curr_offset[i]); - } - -#ifdef CONFIG_MOTOR_FOC_BEMF_SENSE - - /* TODO: BEMF sensing calibartion */ - - for (i = 0; i < CONFIG_MOTOR_FOC_PHASES; i += 1) - { - priv->data.volt_offset[i] = 0; - } - - /* Clear last ADC data */ - - for (i = 0; i < CONFIG_MOTOR_FOC_PHASES; i += 1) - { - priv->data.volt_raw[i] = 0; - } - - /* Set ADC hardware offset for voltage channels (only injected channels) */ - - for (i = 0; i < CONFIG_MOTOR_FOC_PHASES; i += 1) - { - /* Get channel */ - - ch = board->data->vadc_cfg->chan[board->data->vadc_cfg->regch + i]; - - /* Write offset */ - - STM32_ADC_OFFSET_SET(vadc, ch, i, priv->data.volt_offset[i]); - } -#endif - - mtrinfo("ADC offset calibration - DONE!\n"); - -errout: - - /* Call board-specific */ - - board->ops->calibration(dev, false); - - /* Reset ADC interrupts counter */ - - priv->data.adcint_cntr = 0; - - return ret; -} - -/**************************************************************************** - * Name: stm32_foc_pwm_duty_set - * - * Description: - * Set the 3-phase PWM duty cycle - * - ****************************************************************************/ - -static int stm32_foc_pwm_duty_set(struct foc_dev_s *dev, - foc_duty_t *duty) -{ - struct stm32_foc_priv_s *priv = STM32_FOCPIRV_FROM_DEV_GET(dev); - struct stm32_foc_dev_s *foc_dev = STM32_FOCDEV_FROM_DEV_GET(dev); - uint16_t ccr[CONFIG_MOTOR_FOC_PHASES]; - - DEBUGASSERT(dev); - DEBUGASSERT(duty); - DEBUGASSERT(priv); - DEBUGASSERT(foc_dev); - DEBUGASSERT(priv->data.per != 0); - - /* Get the CCR for a given duty cycle */ - - DEBUGASSERT(duty[0] >= 0); - DEBUGASSERT(duty[1] >= 0); -#if CONFIG_MOTOR_FOC_PHASES > 2 - DEBUGASSERT(duty[2] >= 0); -#endif -#if CONFIG_MOTOR_FOC_PHASES > 3 - DEBUGASSERT(duty[3] >= 0); -#endif - - ccr[0] = (uint16_t)b16toi(b16muli(duty[0], priv->data.per)); - ccr[1] = (uint16_t)b16toi(b16muli(duty[1], priv->data.per)); -#if CONFIG_MOTOR_FOC_PHASES > 2 - ccr[2] = (uint16_t)b16toi(b16muli(duty[2], priv->data.per)); -#endif -#if CONFIG_MOTOR_FOC_PHASES > 3 - ccr[3] = (uint16_t)b16toi(b16muli(duty[3], priv->data.per)); -#endif - - /* Write directly to timer registers. - * We are not using the PWM_CCR_UPDATE interface as it is too slow - */ - - putreg32(ccr[0], (foc_dev->pwm_base + STM32_GTIM_CCR1_OFFSET)); - putreg32(ccr[1], (foc_dev->pwm_base + STM32_GTIM_CCR2_OFFSET)); -#if CONFIG_MOTOR_FOC_PHASES > 2 - putreg32(ccr[2], (foc_dev->pwm_base + STM32_GTIM_CCR3_OFFSET)); -#endif -#if CONFIG_MOTOR_FOC_PHASES > 3 - putreg32(ccr[3], (foc_dev->pwm_base + STM32_GTIM_CCR4_OFFSET)); -#endif - - return OK; -} - -/**************************************************************************** - * Name: stm32_foc_pwm_off - * - * Description: - * Set the 3-phase bridge switches in off state. - * - ****************************************************************************/ - -static int stm32_foc_pwm_off(struct foc_dev_s *dev, bool off) -{ - struct stm32_pwm_dev_s *pwm = PWM_FROM_FOC_DEV_GET(dev); - - if (off) - { - /* Force all transistors to low state */ - - PWM_MODE_UPDATE(pwm, STM32_PWM_CHAN1, PWM_MODE_HSHI_LSLO); - PWM_MODE_UPDATE(pwm, STM32_PWM_CHAN2, PWM_MODE_HSHI_LSLO); -#if CONFIG_MOTOR_FOC_PHASES > 2 - PWM_MODE_UPDATE(pwm, STM32_PWM_CHAN3, PWM_MODE_HSHI_LSLO); -#endif -#if CONFIG_MOTOR_FOC_PHASES > 3 - PWM_MODE_UPDATE(pwm, STM32_PWM_CHAN4, PWM_MODE_HSHI_LSLO); -#endif - - /* Disable complementary outputs */ - - PWM_OUTPUTS_ENABLE(pwm, PMW_OUTPUTS_ALL_COMP, false); - } - else - { - /* Restore FOC operation modes */ - - PWM_ALL_OUTPUTS_ENABLE(pwm, true); - - PWM_MODE_UPDATE(pwm, STM32_PWM_CHAN1, PWM_MODE_FOC); - PWM_MODE_UPDATE(pwm, STM32_PWM_CHAN2, PWM_MODE_FOC); -#if CONFIG_MOTOR_FOC_PHASES > 2 - PWM_MODE_UPDATE(pwm, STM32_PWM_CHAN3, PWM_MODE_FOC); -#endif -#if CONFIG_MOTOR_FOC_PHASES > 3 - PWM_MODE_UPDATE(pwm, STM32_PWM_CHAN4, PWM_MODE_FOC); -#endif - } - - return OK; -} - -/**************************************************************************** - * Name: stm32_foc_info_get - * - * Description: - * Get HW configuration for FOC device - * - ****************************************************************************/ - -static int stm32_foc_info_get(struct foc_dev_s *dev, struct foc_info_s *info) -{ - struct stm32_foc_board_s *board = STM32_FOCBOARD_FROM_DEV_GET(dev); - - DEBUGASSERT(dev); - DEBUGASSERT(board); - - /* Get data from board configuration */ - - return board->ops->info_get(dev, info); -} - -/**************************************************************************** - * Name: stm32_foc_curr_get - * - * Description: - * Get current samples from ADC - * - ****************************************************************************/ - -static void stm32_foc_curr_get(struct foc_dev_s *dev, - int16_t *curr, int shunts) -{ - struct stm32_foc_priv_s *priv = STM32_FOCPIRV_FROM_DEV_GET(dev); - struct stm32_adc_dev_s *adc = ADC_FROM_FOC_DEV_GET(dev); - int i = 0; - - DEBUGASSERT(dev); - DEBUGASSERT(priv); - DEBUGASSERT(adc); - DEBUGASSERT(curr); - - for (i = 0; i < shunts; i += 1) - { - /* Get raw current samples. - * We have ADC offset enabled for injected channels so this - * gives us signed values. - * NOTE: ADC value is 11 bits + sign. - */ - -#ifdef CONFIG_STM32_FOC_G4_ADCCHAN0_WORKAROUND - /* Ignore first channel */ - - curr[i] = (int16_t)STM32_ADC_INJDATA_GET(adc, (i + 1)); -#else - curr[i] = (int16_t)STM32_ADC_INJDATA_GET(adc, i); -#endif - } -} - -#ifdef CONFIG_MOTOR_FOC_BEMF_SENSE -/**************************************************************************** - * Name: stm32_foc_volt_get - * - * Description: - * Get voltage samples from ADC - * - ****************************************************************************/ - -static void stm32_foc_volt_get(struct foc_dev_s *dev, int16_t *volt) -{ - struct stm32_foc_priv_s *priv = STM32_FOCPIRV_FROM_DEV_GET(dev); - struct stm32_adc_dev_s *vadc = VADC_FROM_FOC_DEV_GET(dev); - int i = 0; - - DEBUGASSERT(dev); - DEBUGASSERT(priv); - DEBUGASSERT(vadc); - DEBUGASSERT(volt); - - /* Make sure the conversion is complete. - * It is possible that the ADC master sequence will end in front of - * the slave sequence. In that case we just busy-wait. - * In the worst case scenario the slave conversion is one channel behind - * the master conversion (2 current channels vs 3 voltage channels). - * - * Another solution is to make sure that both conversions has the same - * length, but this makes the code much more complex. - */ - - while ((FOC_ADC_ISR_FOC & STM32_ADC_INT_GET(vadc)) == 0); - - /* Clear status */ - - STM32_ADC_INT_ACK(vadc, FOC_ADC_ISR_FOC); - - for (i = 0; i < CONFIG_MOTOR_FOC_PHASES; i += 1) - { - /* Get raw voltage samples. - * We have ADC offset enabled for injected channels so this - * gives us signed values. - * NOTE: ADC value is 11 bits + sign. - */ - -#ifdef CONFIG_STM32_FOC_G4_ADCCHAN0_WORKAROUND - /* Ignore first channel */ - - volt[i] = (int16_t)STM32_ADC_INJDATA_GET(vadc, (i + 1)); -#else - volt[i] = (int16_t)STM32_ADC_INJDATA_GET(vadc, i); -#endif - } -} -#endif - -/**************************************************************************** - * Name: stm32_foc_notifier_cfg - * - * Description: - * Configure FOC notifier - * - ****************************************************************************/ - -static int stm32_foc_notifier_cfg(struct foc_dev_s *dev, uint32_t freq) -{ - struct stm32_foc_priv_s *priv = STM32_FOCPIRV_FROM_DEV_GET(dev); - int ret = OK; - - DEBUGASSERT(dev); - DEBUGASSERT(priv); - DEBUGASSERT(freq > 0); - DEBUGASSERT(dev->cfg.pwm_freq > 0); - - /* Validate input: - * 1. must be fraction of PWM frequency - */ - - if (dev->cfg.pwm_freq % freq != 0) - { - ret = -EINVAL; - goto errout; - } - -#if defined(CONFIG_STM32_FOC_ADC_CCR4) - /* ADC interrupts frequency is PWM frequency */ - - priv->data.adc_freq = dev->cfg.pwm_freq; - - /* Get worker divider */ - - priv->data.notifier_div = (dev->cfg.pwm_freq / freq); - -#elif defined(CONFIG_STM32_FOC_ADC_TRGO) - /* Call work on every ADC interrupt */ - - priv->data.notifier_div = 1; - - /* ADC interrupts frequency is notifier frequency */ - - priv->data.adc_freq = freq; -#else -# error Invalid FOC ADC trigger -#endif - -errout: - return ret; -} - -/**************************************************************************** - * Name: stm32_foc_bind - * - * Description: - * Bind lower-half FOC device with upper-half FOC logic - * - ****************************************************************************/ - -static int stm32_foc_bind(struct foc_dev_s *dev, - struct foc_callbacks_s *cb) -{ - struct stm32_foc_priv_s *priv = STM32_FOCPIRV_FROM_DEV_GET(dev); - int ret = OK; - - DEBUGASSERT(dev); - DEBUGASSERT(cb); - DEBUGASSERT(priv); - - /* Validate callbacks */ - - DEBUGASSERT(cb->notifier); - - /* Bind upper-half FOC device callbacks */ - - priv->cb = cb; - return ret; -} - -/**************************************************************************** - * Name: stm32_foc_fault_clear - * - * Description: - * Arch-specific fault clear - * - ****************************************************************************/ - -static int stm32_foc_fault_clear(struct foc_dev_s *dev) -{ - struct stm32_foc_board_s *board = STM32_FOCBOARD_FROM_DEV_GET(dev); - - DEBUGASSERT(dev); - DEBUGASSERT(board); - - return board->ops->fault_clear(dev); -} - -#ifdef CONFIG_MOTOR_FOC_TRACE - -/**************************************************************************** - * Name: stm32_foc_trace - * - * Description: - * Arch-specific trace initialization - * - ****************************************************************************/ - -int stm32_foc_trace_init(struct foc_dev_s *dev) -{ - struct stm32_foc_board_s *board = STM32_FOCBOARD_FROM_DEV_GET(dev); - - DEBUGASSERT(dev); - DEBUGASSERT(board); - - /* Call board-specific logic */ - - return board->ops->trace_init(dev); -} - -/**************************************************************************** - * Name: stm32_foc_trace - * - * Description: - * Arch-specific trace - * - ****************************************************************************/ - -void stm32_foc_trace(struct foc_dev_s *dev, int type, bool state) -{ - struct stm32_foc_board_s *board = STM32_FOCBOARD_FROM_DEV_GET(dev); - - DEBUGASSERT(dev); - DEBUGASSERT(board); - - /* Call board-specific logic */ - - board->ops->trace(dev, type, state); -} -#endif - -/**************************************************************************** - * Name: stm32_foc_adc_init - * - * Description: - * Initialize ADC instance - * - ****************************************************************************/ - -struct adc_dev_s *stm32_foc_adc_init(struct stm32_foc_adc_s *adc_cfg) -{ - struct adc_dev_s *adc_dev = NULL; - int i = 0; -#ifdef CONFIG_STM32_FOC_G4_ADCCHAN0_WORKAROUND - uint8_t *adc_chan = NULL; - uint8_t adc_nchan = 0; -#endif - - DEBUGASSERT(adc_cfg); - DEBUGASSERT(adc_cfg != NULL); - DEBUGASSERT(adc_cfg->pins != NULL); - DEBUGASSERT(adc_cfg->chan != NULL); - - /* Configure pins as analog inputs for the selected channels */ - - for (i = 0; i < adc_cfg->nchan; i++) - { - stm32_configgpio(adc_cfg->pins[i]); - } - - /* STM32G4 ADC channel 0 unwanted conversion workaround */ - -#ifdef CONFIG_STM32_FOC_G4_ADCCHAN0_WORKAROUND - /* Add one dummy channel to conversion */ - - adc_nchan = (adc_cfg->nchan + 1); - - /* Allocate memory for the extended list of channels */ - - adc_chan = zalloc(adc_nchan); - if (adc_chan == NULL) - { - goto errout; - } - - /* Copy regular channels first */ - - for (i = 0; i < adc_cfg->regch; i += 1) - { - adc_chan[i] = adc_cfg->chan[i]; - } - - /* Add dummy channel at the beginning of injected channels */ - - adc_chan[adc_cfg->regch] = 0; - - /* Copy injected channels */ - - for (i = (adc_cfg->regch + 1); i < adc_nchan; i += 1) - { - adc_chan[i] = adc_cfg->chan[i - 1]; - } -#endif /* CONFIG_STM32_FOC_G4_ADCCHAN0_WORKAROUND */ - - /* Get the ADC interface */ - -#ifdef CONFIG_STM32_FOC_G4_ADCCHAN0_WORKAROUND - adc_dev = stm32_adcinitialize(adc_cfg->intf, - adc_chan, - adc_nchan); - - free(adc_chan); -#else - adc_dev = stm32_adcinitialize(adc_cfg->intf, - adc_cfg->chan, - adc_cfg->nchan); -#endif - - return adc_dev; - -#ifdef CONFIG_STM32_FOC_G4_ADCCHAN0_WORKAROUND -errout: - return NULL; -#endif -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_foc_initialize - * - * Description: - * Initialize the FOC lower-half. - * - * Input Parameters: - * inst - FOC instance number - * board - FOC board-specific data - * - * Returned Value: - * Valid lower-half FOC controller structure reference on success; - * NULL on failure - * - ****************************************************************************/ - -struct foc_dev_s * -stm32_foc_initialize(int inst, struct stm32_foc_board_s *board) -{ - struct foc_dev_s *dev = NULL; - struct stm32_foc_adc_s *adc_cfg = NULL; - struct foc_lower_s *foc_lower = NULL; - struct stm32_foc_dev_s *foc_dev = NULL; - struct stm32_foc_priv_s *foc_priv = NULL; -#ifdef FOC_ADC_HAVE_CMN - struct stm32_foc_adccmn_s *adc_cmn = NULL; -#endif - uint32_t adc_irq = 0; - uint32_t pwm_base = 0; - uint32_t jextval = 0; - uint8_t pwm_inst = 0; - uint8_t adc_inst = 0; - uint32_t pwmfzbit = 0; - - DEBUGASSERT(board != NULL); - DEBUGASSERT(board->ops != NULL); - DEBUGASSERT(board->data != NULL); - - /* Assert board-specific ops */ - - DEBUGASSERT(board->ops->setup); - DEBUGASSERT(board->ops->shutdown); - DEBUGASSERT(board->ops->calibration); - DEBUGASSERT(board->ops->fault_clear); - DEBUGASSERT(board->ops->pwm_start); - DEBUGASSERT(board->ops->current_get); - DEBUGASSERT(board->ops->info_get); -#ifdef CONFIG_MOTOR_FOC_TRACE - DEBUGASSERT(board->ops->trace_init); - DEBUGASSERT(board->ops->trace); -#endif - - /* Get FOC instance configuration */ - - switch (inst) - { -#ifdef CONFIG_STM32_FOC_FOC0 - case 0: - { - pwm_inst = FOC0_PWM; - adc_inst = FOC0_ADC; - adc_irq = FOC0_ADC_IRQ; - pwm_base = FOC0_PWM_BASE; - jextval = FOC0_ADC_JEXT; - pwmfzbit = FOC0_PWM_FZ_BIT; -#ifdef FOC_ADC_HAVE_CMN - adc_cmn = FOC0_ADC_CMN; -#endif - break; - } -#endif - -#ifdef CONFIG_STM32_FOC_FOC1 - case 1: - { - pwm_inst = FOC1_PWM; - adc_inst = FOC1_ADC; - adc_irq = FOC1_ADC_IRQ; - pwm_base = FOC1_PWM_BASE; - jextval = FOC1_ADC_JEXT; - pwmfzbit = FOC1_PWM_FZ_BIT; -#ifdef FOC_ADC_HAVE_CMN - adc_cmn = FOC1_ADC_CMN; -#endif - break; - } -#endif - - default: - { - mtrerr("Unsupported STM32 FOC instance %d\n", inst); - set_errno(EINVAL); - goto errout; - } - } - - /* Get STM32 FOC lower-half */ - - foc_lower = &g_stm32_foc_lower[inst]; - - /* Connect STM32 FOC private data with ops and data */ - - foc_lower->data = &g_stm32_foc_priv[inst]; - foc_lower->ops = &g_stm32_foc_ops; - foc_priv = foc_lower->data; - - /* Reset STM32 FOC private data */ - - memset(foc_lower->data, 0, sizeof(struct stm32_foc_priv_s)); - - /* Connect STM32 FOC devices */ - - foc_priv->dev = &g_stm32_foc_dev[inst]; - - /* Connect board data */ - - foc_priv->board = board; - -#ifdef FOC_ADC_HAVE_CMN - /* Connect ADC common data */ - - foc_priv->adc_cmn = adc_cmn; -#endif - - /* Get arch-specific device */ - - foc_dev = (struct stm32_foc_dev_s *)foc_priv->dev; - DEBUGASSERT(foc_dev); - - /* Store STM32 FOC devices data */ - - foc_dev->adc_inst = adc_inst; - foc_dev->pwm_inst = pwm_inst; - foc_dev->pwm_base = pwm_base; - foc_dev->jextval = jextval; - foc_dev->adc_irq = adc_irq; - - /* Get the advanced timer PWM interface */ - - foc_dev->pwm = (struct stm32_pwm_dev_s *)stm32_pwminitialize(pwm_inst); - if (foc_dev->pwm == NULL) - { - mtrerr("Failed to get PWM%d interface\n", pwm_inst); - set_errno(EINVAL); - goto errout; - } - - /* Get ADC configuration */ - - adc_cfg = board->data->adc_cfg; - - /* Make sure that we are using the appropriate ADC interface */ - - if (adc_inst != adc_cfg->intf) - { - mtrerr("FOC ADC configuration doesn't match %d, %d\n", - adc_inst, adc_cfg->intf); - set_errno(EINVAL); - goto errout; - } - - /* Get ADC instance */ - - foc_dev->adc_dev = stm32_foc_adc_init(adc_cfg); - if (foc_dev->adc_dev == NULL) - { - mtrerr("Failed to initialize FOC ADC%d interface\n", adc_cfg->intf); - set_errno(EINVAL); - goto errout; - } - - /* Get ADC private part */ - - foc_dev->adc = (struct stm32_adc_dev_s *)foc_dev->adc_dev->ad_priv; - -#ifdef CONFIG_MOTOR_FOC_BEMF_SENSE - /* Get ADC configuration */ - - adc_cfg = board->data->vadc_cfg; - - /* Make sure that we are using the slave ADC */ - - if (adc_inst != adc_cfg->intf - 1) - { - mtrerr("BEMF ADC must be the first slave instance of the main ADC!"); - set_errno(EINVAL); - goto errout; - } - - /* Get ADC instance */ - - foc_dev->vadc_dev = stm32_foc_adc_init(adc_cfg); - if (foc_dev->vadc_dev == NULL) - { - mtrerr("Failed to initialize BEMF ADC%d interface\n", adc_cfg->intf); - set_errno(EINVAL); - goto errout; - } - - /* Get ADC private part */ - - foc_dev->vadc = (struct stm32_adc_dev_s *)foc_dev->vadc_dev->ad_priv; -#endif - - /* Froze timer and reset outputs when core is halted. - * TODO: move this to stm32_pwm.c and configure from Kconfig - */ - - modifyreg32(FOC_PWM_FZ_REG, 0, pwmfzbit); - - /* Initialize calibration semaphore */ - - nxsem_init(&foc_priv->cal_done_sem, 0, 0); - - /* Get FOC device */ - - dev = &g_foc_dev[inst]; - - /* Connect the lower-half device with the upper-half device */ - - dev->lower = (void *)foc_lower; - - /* Return upper-half driver instance */ - - return dev; - -errout: - return NULL; -} - -/**************************************************************************** - * Name: stm32_foc_adcget - * - * Description: - * Get a handler for ADC device associated with a given FOC device. - * - * The FOC lower-half logic uses only injected ADC channels for operations. - * We are using a custom ADC interrupt logic that cannot handle - * additional regular channels conversion. This limitation can be overcome - * with the DMA transfer. - * With this function we can get a handler to the ADC device and use it - * to register a standard ADC character device. - * - * Input Parameters: - * lower - a pointer to the uperr-half FOC device - * - * Returned Value: - * Valid ADC device structure reference on success; a NULL on failure - * - ****************************************************************************/ - -struct adc_dev_s *stm32_foc_adcget(struct foc_dev_s *dev) -{ - struct stm32_foc_dev_s *foc_dev = STM32_FOCDEV_FROM_DEV_GET(dev); - - DEBUGASSERT(dev); - DEBUGASSERT(foc_dev); - - /* Return STM32 ADC device */ - - return foc_dev->adc_dev; -} diff --git a/arch/arm/src/stm32/stm32_foc.h b/arch/arm/src/stm32/stm32_foc.h deleted file mode 100644 index bfc145dbda8a1..0000000000000 --- a/arch/arm/src/stm32/stm32_foc.h +++ /dev/null @@ -1,203 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_foc.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32_STM32_FOC_H -#define __ARCH_ARM_SRC_STM32_STM32_FOC_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include - -#include "stm32_adc.h" - -#include - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -/* ADC configuration for the FOC device */ - -struct stm32_foc_adc_s -{ - /* ADC interface used by the FOC */ - - uint8_t intf; - - /* The number of ADC channels (regular + injected) */ - - uint8_t nchan; - - /* The number of auxiliary regular channels (only for DMA transfer) */ - - uint8_t regch; - - /* The list of ADC channels (regular first, then injected) */ - - uint8_t *chan; - - /* The list of ADC pins */ - - uint32_t *pins; - - /* The list of ADC channels sample time configuration */ - - adc_channel_t *stime; -}; - -/* Board-specific operations. - * - * These are calls from the lower-half to the board-specific logic. - * They must be provided by board-specific logic even if not used. - */ - -struct stm32_foc_board_ops_s -{ - /* Board-specific setup */ - - int (*setup)(struct foc_dev_s *dev); - - /* Board-specific shutdown */ - - int (*shutdown)(struct foc_dev_s *dev); - - /* Board-specific ioctl (optional) */ - - int (*ioctl)(struct foc_dev_s *dev, int cmd, unsigned long arg); - - /* Board-specific calibration setup */ - - int (*calibration)(struct foc_dev_s *dev, bool state); - - /* Board-specific fault clear */ - - int (*fault_clear)(struct foc_dev_s *dev); - - /* Board-specific PWM start */ - - int (*pwm_start)(struct foc_dev_s *dev, bool state); - - /* Get phase currents */ - - int (*current_get)(struct foc_dev_s *dev, int16_t *curr_raw, - foc_current_t *curr); - - /* Board-specific info */ - - int (*info_get)(struct foc_dev_s *dev, struct foc_info_s *cfg); - -#ifdef CONFIG_MOTOR_FOC_BEMF_SENSE - /* Get BEMF voltage */ - - int (*voltage_get)(struct foc_dev_s *dev, int16_t *volt_raw, - foc_voltage_t *volt); -#endif - -#ifdef CONFIG_MOTOR_FOC_TRACE - /* FOC trace interface setup */ - - int (*trace_init)(struct foc_dev_s *dev); - - /* FOC trace */ - - void (*trace)(struct foc_dev_s *dev, int type, bool state); -#endif -}; - -/* Board-specific FOC data */ - -struct stm32_foc_board_data_s -{ - /* ADC configuration */ - - struct stm32_foc_adc_s *adc_cfg; - -#ifdef CONFIG_MOTOR_FOC_BEMF_SENSE - /* BEMF voltage ADC configuration */ - - struct stm32_foc_adc_s *vadc_cfg; -#endif - - /* PWM deadtime register value */ - - uint8_t pwm_dt; -}; - -/* Board-specific FOC configuration */ - -struct stm32_foc_board_s -{ - /* Board-specific FOC operations */ - - struct stm32_foc_board_ops_s *ops; - - /* Board-specific FOC data */ - - struct stm32_foc_board_data_s *data; -}; - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -#ifndef __ASSEMBLY__ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Name: stm32_foc_initialize - ****************************************************************************/ - -struct foc_dev_s * -stm32_foc_initialize(int inst, struct stm32_foc_board_s *board); - -/**************************************************************************** - * Name: stm32_foc_adcget - ****************************************************************************/ - -struct adc_dev_s *stm32_foc_adcget(struct foc_dev_s *dev); - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32_STM32_FOC_H */ diff --git a/arch/arm/src/stm32/stm32_freerun.c b/arch/arm/src/stm32/stm32_freerun.c deleted file mode 100644 index af5599a931452..0000000000000 --- a/arch/arm/src/stm32/stm32_freerun.c +++ /dev/null @@ -1,301 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_freerun.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include -#include - -#include -#include - -#include "stm32_freerun.h" - -#ifdef CONFIG_STM32_FREERUN - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_freerun_handler - * - * Description: - * Timer interrupt callback. When the freerun timer counter overflows, - * this interrupt will occur. We will just increment an overflow count. - * - * Input Parameters: - * tch - The handle that represents the timer state - * arg - An opaque argument provided when the interrupt was registered - * sr - The value of the timer interrupt status register at the time - * that the interrupt occurred. - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifndef CONFIG_CLOCK_TIMEKEEPING -static int stm32_freerun_handler(int irq, void *context, void *arg) -{ - struct stm32_freerun_s *freerun = (struct stm32_freerun_s *) arg; - - DEBUGASSERT(freerun != NULL && freerun->overflow < UINT32_MAX); - freerun->overflow++; - - STM32_TIM_ACKINT(freerun->tch, GTIM_SR_UIF); - return OK; -} -#endif /* CONFIG_CLOCK_TIMEKEEPING */ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_freerun_initialize - * - * Description: - * Initialize the freerun timer wrapper - * - * Input Parameters: - * freerun Caller allocated instance of the freerun state structure - * chan Timer counter channel to be used. - * resolution The required resolution of the timer in units of - * microseconds. NOTE that the range is restricted to the - * range of uint16_t (excluding zero). - * - * Returned Value: - * Zero (OK) is returned on success; a negated errno value is returned - * on failure. - * - ****************************************************************************/ - -int stm32_freerun_initialize(struct stm32_freerun_s *freerun, int chan, - uint16_t resolution) -{ - uint32_t frequency; - - tmrinfo("chan=%d resolution=%d usec\n", chan, resolution); - DEBUGASSERT(freerun != NULL && resolution > 0); - - /* Get the TC frequency the corresponds to the requested resolution */ - - frequency = USEC_PER_SEC / (uint32_t)resolution; - freerun->frequency = frequency; - - freerun->tch = stm32_tim_init(chan); - if (!freerun->tch) - { - tmrerr("ERROR: Failed to allocate TIM%d\n", chan); - return -EBUSY; - } - - STM32_TIM_SETCLOCK(freerun->tch, frequency); - - /* Initialize the remaining fields in the state structure and return - * success. - */ - - freerun->chan = chan; - freerun->width = STM32_TIM_GETWIDTH(freerun->tch); - -#ifdef CONFIG_CLOCK_TIMEKEEPING - freerun->counter_mask = 0xffffffffull; -#endif - -#ifndef CONFIG_CLOCK_TIMEKEEPING - freerun->overflow = 0; - - /* Set up to receive the callback when the counter overflow occurs */ - - STM32_TIM_SETISR(freerun->tch, stm32_freerun_handler, freerun, 0); -#endif - - /* Set timer period */ - - STM32_TIM_SETPERIOD(freerun->tch, - (uint32_t)((1ull << freerun->width) - 1)); - - /* Start the counter */ - - STM32_TIM_SETMODE(freerun->tch, STM32_TIM_MODE_UP); - -#ifndef CONFIG_CLOCK_TIMEKEEPING - STM32_TIM_ACKINT(freerun->tch, GTIM_SR_UIF); - STM32_TIM_ENABLEINT(freerun->tch, GTIM_DIER_UIE); -#endif - - return OK; -} - -/**************************************************************************** - * Name: stm32_freerun_counter - * - * Description: - * Read the counter register of the free-running timer. - * - * Input Parameters: - * freerun Caller allocated instance of the freerun state structure. This - * structure must have been previously initialized via a call to - * stm32_freerun_initialize(); - * ts The location in which to return the time from the free-running - * timer. - * - * Returned Value: - * Zero (OK) is returned on success; a negated errno value is returned - * on failure. - * - ****************************************************************************/ - -#ifndef CONFIG_CLOCK_TIMEKEEPING - -int stm32_freerun_counter(struct stm32_freerun_s *freerun, - struct timespec *ts) -{ - uint64_t usec; - uint32_t counter; - uint32_t verify; - uint32_t overflow; - uint32_t sec; - int pending; - irqstate_t flags; - - DEBUGASSERT(freerun && freerun->tch && ts); - - /* Temporarily disable the overflow counter. NOTE that we have to be - * careful here because stm32_tc_getpending() will reset the pending - * interrupt status. If we do not handle the overflow here then, it will - * be lost. - */ - - flags = enter_critical_section(); - - overflow = freerun->overflow; - counter = STM32_TIM_GETCOUNTER(freerun->tch); - pending = STM32_TIM_CHECKINT(freerun->tch, 0); - verify = STM32_TIM_GETCOUNTER(freerun->tch); - - /* If an interrupt was pending before we re-enabled interrupts, - * then the overflow needs to be incremented. - */ - - if (pending) - { - STM32_TIM_ACKINT(freerun->tch, GTIM_SR_UIF); - - /* Increment the overflow count and use the value of the - * guaranteed to be AFTER the overflow occurred. - */ - - overflow++; - counter = verify; - - /* Update freerun overflow counter. */ - - freerun->overflow = overflow; - } - - leave_critical_section(flags); - - tmrinfo("counter=%" PRIu32 " (%" PRIu32 ") overflow=%" PRIu32 - ", pending=%i\n", - counter, verify, overflow, pending); - tmrinfo("frequency=%" PRIu32 "\n", freerun->frequency); - - /* Convert the whole thing to units of microseconds. - * - * frequency = ticks / second - * seconds = ticks * frequency - * usecs = (ticks * USEC_PER_SEC) / frequency; - */ - - usec = ((((uint64_t)overflow << freerun->width) + - (uint64_t)counter) * USEC_PER_SEC) / - freerun->frequency; - - /* And return the value of the timer */ - - sec = (uint32_t)(usec / USEC_PER_SEC); - ts->tv_sec = sec; - ts->tv_nsec = (usec - (sec * USEC_PER_SEC)) * NSEC_PER_USEC; - - tmrinfo("usec=%llu ts=(%jd, %ld)\n", - usec, (intmax_t)ts->tv_sec, ts->tv_nsec); - - return OK; -} - -#else /* CONFIG_CLOCK_TIMEKEEPING */ - -int stm32_freerun_counter(struct stm32_freerun_s *freerun, uint64_t *counter) -{ - *counter = STM32_TIM_GETCOUNTER(freerun->tch); - return OK; -} - -#endif /* CONFIG_CLOCK_TIMEKEEPING */ - -/**************************************************************************** - * Name: stm32_freerun_uninitialize - * - * Description: - * Stop the free-running timer and release all resources that it uses. - * - * Input Parameters: - * freerun Caller allocated instance of the freerun state structure. This - * structure must have been previously initialized via a call to - * stm32_freerun_initialize(); - * - * Returned Value: - * Zero (OK) is returned on success; a negated errno value is returned - * on failure. - * - ****************************************************************************/ - -int stm32_freerun_uninitialize(struct stm32_freerun_s *freerun) -{ - DEBUGASSERT(freerun && freerun->tch); - - /* Now we can disable the timer interrupt and disable the timer. */ - - STM32_TIM_DISABLEINT(freerun->tch, GTIM_DIER_UIE); - STM32_TIM_SETMODE(freerun->tch, STM32_TIM_MODE_DISABLED); - STM32_TIM_SETISR(freerun->tch, NULL, NULL, 0); - - /* Free the timer */ - - stm32_tim_deinit(freerun->tch); - freerun->tch = NULL; - - return OK; -} - -#endif /* CONFIG_STM32_ONESHOT */ diff --git a/arch/arm/src/stm32/stm32_freerun.h b/arch/arm/src/stm32/stm32_freerun.h deleted file mode 100644 index 4dbaadeee3c5e..0000000000000 --- a/arch/arm/src/stm32/stm32_freerun.h +++ /dev/null @@ -1,161 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_freerun.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32_STM32_FREERUN_H -#define __ARCH_ARM_SRC_STM32_STM32_FREERUN_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include "stm32_tim.h" - -#ifdef CONFIG_STM32_FREERUN - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -/* The freerun client must allocate an instance of this structure and called - * stm32_freerun_initialize() before using the freerun facilities. The - * client should not access the contents of this structure directly since - * the contents are subject to change. - */ - -struct stm32_freerun_s -{ - uint8_t chan; /* The timer/counter in use */ - uint8_t width; /* Width of timer (16- or 32-bits) */ - struct stm32_tim_dev_s *tch; /* Handle returned by stm32_tim_init() */ - uint32_t frequency; - -#ifndef CONFIG_CLOCK_TIMEKEEPING - uint32_t overflow; /* Timer counter overflow */ -#endif - -#ifdef CONFIG_CLOCK_TIMEKEEPING - uint64_t counter_mask; -#endif -}; - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_freerun_initialize - * - * Description: - * Initialize the freerun timer wrapper - * - * Input Parameters: - * freerun Caller allocated instance of the freerun state structure - * chan Timer counter channel to be used. - * resolution The required resolution of the timer in units of - * microseconds. NOTE that the range is restricted to the - * range of uint16_t (excluding zero). - * - * Returned Value: - * Zero (OK) is returned on success; a negated errno value is returned - * on failure. - * - ****************************************************************************/ - -int stm32_freerun_initialize(struct stm32_freerun_s *freerun, int chan, - uint16_t resolution); - -/**************************************************************************** - * Name: stm32_freerun_counter - * - * Description: - * Read the counter register of the free-running timer. - * - * Input Parameters: - * freerun Caller allocated instance of the freerun state structure. This - * structure must have been previously initialized via a call to - * stm32_freerun_initialize(); - * ts The location in which to return the time remaining on the - * oneshot timer. - * - * Returned Value: - * Zero (OK) is returned on success; a negated errno value is returned - * on failure. - * - ****************************************************************************/ - -#ifndef CONFIG_CLOCK_TIMEKEEPING - -int stm32_freerun_counter(struct stm32_freerun_s *freerun, - struct timespec *ts); - -#else /* CONFIG_CLOCK_TIMEKEEPING */ - -int stm32_freerun_counter(struct stm32_freerun_s *freerun, - uint64_t *counter); - -#endif /* CONFIG_CLOCK_TIMEKEEPING */ - -/**************************************************************************** - * Name: stm32_freerun_uninitialize - * - * Description: - * Stop the free-running timer and release all resources that it uses. - * - * Input Parameters: - * freerun Caller allocated instance of the freerun state structure. This - * structure must have been previously initialized via a call to - * stm32_freerun_initialize(); - * - * Returned Value: - * Zero (OK) is returned on success; a negated errno value is returned - * on failure. - * - ****************************************************************************/ - -int stm32_freerun_uninitialize(struct stm32_freerun_s *freerun); - -#undef EXTERN -#ifdef __cplusplus -} -#endif - -#endif /* CONFIG_STM32_FREERUN */ -#endif /* __ARCH_ARM_SRC_STM32_STM32_FREERUN_H */ diff --git a/arch/arm/src/stm32/stm32_fsmc.c b/arch/arm/src/stm32/stm32_fsmc.c deleted file mode 100644 index 5bfc967a9614f..0000000000000 --- a/arch/arm/src/stm32/stm32_fsmc.c +++ /dev/null @@ -1,85 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_fsmc.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "stm32.h" - -#if defined(CONFIG_STM32_FSMC) - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_fsmc_enable - * - * Description: - * Enable clocking to the FSMC. - * - ****************************************************************************/ - -#if defined(CONFIG_STM32_STM32L15XX) || defined(CONFIG_STM32_STM32F10XX) - -void stm32_fsmc_enable(void) -{ - modifyreg32(STM32_RCC_AHBENR, 0, RCC_AHBENR_FSMCEN); -} - -#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) - -void stm32_fsmc_enable(void) -{ - modifyreg32(STM32_RCC_AHB3ENR, 0, RCC_AHB3ENR_FSMCEN); -} - -#endif - -/**************************************************************************** - * Name: stm32_fsmc_disable - * - * Description: - * Disable clocking to the FSMC. - * - ****************************************************************************/ - -#if defined(CONFIG_STM32_STM32L15XX) || defined(CONFIG_STM32_STM32F10XX) - -void stm32_fsmc_disable(void) -{ - modifyreg32(STM32_RCC_AHBENR, RCC_AHBENR_FSMCEN, 0); -} - -#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) - -void stm32_fsmc_disable(void) -{ - modifyreg32(STM32_RCC_AHB3ENR, RCC_AHB3ENR_FSMCEN, 0); -} - -#endif - -#endif /* CONFIG_STM32_FSMC */ diff --git a/arch/arm/src/stm32/stm32_fsmc.h b/arch/arm/src/stm32/stm32_fsmc.h deleted file mode 100644 index df340763016cc..0000000000000 --- a/arch/arm/src/stm32/stm32_fsmc.h +++ /dev/null @@ -1,76 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_fsmc.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32_STM32_FSMC_H -#define __ARCH_ARM_SRC_STM32_STM32_FSMC_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "chip.h" -#include "hardware/stm32_fsmc.h" - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -#ifndef __ASSEMBLY__ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Name: stm32_fsmc_enable - * - * Description: - * Enable clocking to the FSMC. - * - ****************************************************************************/ - -void stm32_fsmc_enable(void); - -/**************************************************************************** - * Name: stm32_fsmc_disable - * - * Description: - * Disable clocking to the FSMC. - * - ****************************************************************************/ - -void stm32_fsmc_disable(void); - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32_STM32_FSMC_H */ diff --git a/arch/arm/src/stm32/stm32_gpio.c b/arch/arm/src/stm32/stm32_gpio.c deleted file mode 100644 index 947d75bf042c4..0000000000000 --- a/arch/arm/src/stm32/stm32_gpio.c +++ /dev/null @@ -1,877 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_gpio.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include - -#include -#include -#include - -#include "arm_internal.h" -#include "chip.h" -#include "stm32_syscfg.h" -#include "stm32_gpio.h" - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -static spinlock_t g_configgpio_lock = SP_UNLOCKED; - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/* Base addresses for each GPIO block */ - -const uint32_t g_gpiobase[STM32_NGPIO_PORTS] = -{ -#if STM32_NGPIO_PORTS > 0 - STM32_GPIOA_BASE, -#endif -#if STM32_NGPIO_PORTS > 1 - STM32_GPIOB_BASE, -#endif -#if STM32_NGPIO_PORTS > 2 - STM32_GPIOC_BASE, -#endif -#if STM32_NGPIO_PORTS > 3 - STM32_GPIOD_BASE, -#endif -#if STM32_NGPIO_PORTS > 4 - STM32_GPIOE_BASE, -#endif - -#if defined(CONFIG_STM32_STM32L15XX) - -#if STM32_NGPIO_PORTS > 5 - STM32_GPIOH_BASE, -#endif -#if STM32_NGPIO_PORTS > 6 - STM32_GPIOF_BASE, -#endif -#if STM32_NGPIO_PORTS > 7 - STM32_GPIOG_BASE, -#endif - -#else - -#if STM32_NGPIO_PORTS > 5 - STM32_GPIOF_BASE, -#endif -#if STM32_NGPIO_PORTS > 6 - STM32_GPIOG_BASE, -#endif -#if STM32_NGPIO_PORTS > 7 - STM32_GPIOH_BASE, -#endif -#if STM32_NGPIO_PORTS > 8 - STM32_GPIOI_BASE, -#endif -#if STM32_NGPIO_PORTS > 9 - STM32_GPIOJ_BASE, -#endif -#if STM32_NGPIO_PORTS > 10 - STM32_GPIOK_BASE, -#endif - -#endif /* CONFIG_STM32_STM32L15XX */ -}; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Function: stm32_gpioremap - * - * Description: - * - * Based on configuration within the .config file, this function will - * remaps positions of alternative functions. - * - ****************************************************************************/ - -static inline void stm32_gpioremap(void) -{ -#if defined(CONFIG_STM32_STM32F10XX) - - /* Remap according to the configuration within .config file */ - - uint32_t val = 0; - -#ifdef CONFIG_STM32_SPI1_REMAP - val |= AFIO_MAPR_SPI1_REMAP; -#endif -#ifdef CONFIG_STM32_SPI3_REMAP - val |= AFIO_MAPR_SPI3_REMAP; -#endif - -#ifdef CONFIG_STM32_I2C1_REMAP - val |= AFIO_MAPR_I2C1_REMAP; -#endif - -#ifdef CONFIG_STM32_USART1_REMAP - val |= AFIO_MAPR_USART1_REMAP; -#endif -#ifdef CONFIG_STM32_USART2_REMAP - val |= AFIO_MAPR_USART2_REMAP; -#endif -#ifdef CONFIG_STM32_USART3_FULL_REMAP - val |= AFIO_MAPR_USART3_FULLREMAP; -#endif -#ifdef CONFIG_STM32_USART3_PARTIAL_REMAP - val |= AFIO_MAPR_USART3_PARTREMAP; -#endif - -#ifdef CONFIG_STM32_TIM1_FULL_REMAP - val |= AFIO_MAPR_TIM1_FULLREMAP; -#endif -#ifdef CONFIG_STM32_TIM1_PARTIAL_REMAP - val |= AFIO_MAPR_TIM1_PARTREMAP; -#endif -#ifdef CONFIG_STM32_TIM2_FULL_REMAP - val |= AFIO_MAPR_TIM2_FULLREMAP; -#endif -#ifdef CONFIG_STM32_TIM2_PARTIAL_REMAP_1 - val |= AFIO_MAPR_TIM2_PARTREMAP1; -#endif -#ifdef CONFIG_STM32_TIM2_PARTIAL_REMAP_2 - val |= AFIO_MAPR_TIM2_PARTREMAP2; -#endif -#ifdef CONFIG_STM32_TIM3_FULL_REMAP - val |= AFIO_MAPR_TIM3_FULLREMAP; -#endif -#ifdef CONFIG_STM32_TIM3_PARTIAL_REMAP - val |= AFIO_MAPR_TIM3_PARTREMAP; -#endif -#ifdef CONFIG_STM32_TIM4_REMAP - val |= AFIO_MAPR_TIM4_REMAP; -#endif - -#ifdef CONFIG_STM32_CAN1_REMAP1 - val |= AFIO_MAPR_PB89; -#endif -#ifdef CONFIG_STM32_CAN1_REMAP2 - val |= AFIO_MAPR_PD01; -#endif -#ifdef CONFIG_STM32_CAN2_REMAP /* Connectivity line only */ - val |= AFIO_MAPR_CAN2_REMAP; -#endif - -#ifdef CONFIG_STM32_ETH_REMAP /* Connectivity line only */ - val |= AFIO_MAPR_ETH_REMAP; -#endif - -#ifdef CONFIG_STM32_JTAG_FULL_ENABLE - /* The reset default */ -#elif defined(CONFIG_STM32_JTAG_NOJNTRST_ENABLE) - val |= AFIO_MAPR_SWJ; /* enabled but without JNTRST */ -#elif defined(CONFIG_STM32_JTAG_SW_ENABLE) - val |= AFIO_MAPR_SWDP; /* set JTAG-DP disabled and SW-DP enabled */ -#else - val |= AFIO_MAPR_DISAB; /* set JTAG-DP and SW-DP Disabled */ -#endif - - putreg32(val, STM32_AFIO_MAPR); -#endif -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Function: stm32_gpioinit - * - * Description: - * Based on configuration within the .config file, it does: - * - Remaps positions of alternative functions. - * - * Typically called from stm32_start(). - * - * Assumptions: - * This function is called early in the initialization sequence so that - * no mutual exclusion is necessary. - * - ****************************************************************************/ - -void stm32_gpioinit(void) -{ - /* Remap according to the configuration within .config file */ - - stm32_gpioremap(); -} - -/**************************************************************************** - * Name: stm32_configgpio - * - * Description: - * Configure a GPIO pin based on bit-encoded description of the pin. - * Once it is configured as Alternative (GPIO_ALT|GPIO_CNF_AFPP|...) - * function, it must be unconfigured with stm32_unconfiggpio() with - * the same cfgset first before it can be set to non-alternative function. - * - * Returned Value: - * OK on success - * A negated errno value on invalid port, or when pin is locked as ALT - * function. - * - * To-Do: Auto Power Enable - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_configgpio (for the STM32F10xxx family) - ****************************************************************************/ - -#if defined(CONFIG_STM32_STM32F10XX) -int stm32_configgpio(uint32_t cfgset) -{ - uint32_t base; - uint32_t cr; - uint32_t regval; - uint32_t regaddr; - unsigned int port; - unsigned int pin; - unsigned int pos; - unsigned int modecnf; - irqstate_t flags; - bool input; - - /* Verify that this hardware supports the select GPIO port */ - - port = (cfgset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; - if (port >= STM32_NGPIO_PORTS) - { - return -EINVAL; - } - - /* Get the port base address */ - - base = g_gpiobase[port]; - - /* Get the pin number and select the port configuration register for that - * pin - */ - - pin = (cfgset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT; - if (pin < 8) - { - cr = base + STM32_GPIO_CRL_OFFSET; - pos = pin; - } - else - { - cr = base + STM32_GPIO_CRH_OFFSET; - pos = pin - 8; - } - - /* Input or output? */ - - input = ((cfgset & GPIO_INPUT) != 0); - - /* Interrupts must be disabled from here on out so that we have mutually - * exclusive access to all of the GPIO configuration registers. - */ - - flags = spin_lock_irqsave(&g_configgpio_lock); - - /* Decode the mode and configuration */ - - regval = getreg32(cr); - - if (input) - { - /* Input.. force mode = INPUT */ - - modecnf = 0; - } - else - { - /* Output or alternate function */ - - modecnf = (cfgset & GPIO_MODE_MASK) >> GPIO_MODE_SHIFT; - } - - modecnf |= ((cfgset & GPIO_CNF_MASK) >> GPIO_CNF_SHIFT) << 2; - - /* Set the port configuration register */ - - regval &= ~(GPIO_CR_MODECNF_MASK(pos)); - regval |= (modecnf << GPIO_CR_MODECNF_SHIFT(pos)); - putreg32(regval, cr); - - /* Set or reset the corresponding BRR/BSRR bit */ - - if (!input) - { - /* It is an output or an alternate function. We have to look at - * the CNF bits to know which. - */ - - unsigned int cnf = (cfgset & GPIO_CNF_MASK); - if (cnf != GPIO_CNF_OUTPP && cnf != GPIO_CNF_OUTOD) - { - /* Its an alternate function pin... we can return early */ - - spin_unlock_irqrestore(&g_configgpio_lock, flags); - return OK; - } - } - else - { - /* It is an input pin... Should it configured as an EXTI interrupt? */ - - if ((cfgset & GPIO_EXTI) != 0) - { - int shift; - - /* Yes.. Set the bits in the EXTI CR register */ - - regaddr = STM32_AFIO_EXTICR(pin); - regval = getreg32(regaddr); - shift = AFIO_EXTICR_EXTI_SHIFT(pin); - regval &= ~(AFIO_EXTICR_PORT_MASK << shift); - regval |= (((uint32_t)port) << shift); - - putreg32(regval, regaddr); - } - - if ((cfgset & GPIO_CNF_MASK) != GPIO_CNF_INPULLUD) - { - /* Neither... we can return early */ - - spin_unlock_irqrestore(&g_configgpio_lock, flags); - return OK; - } - } - - /* If it is an output... set the pin to the correct initial state. - * If it is pull-down or pull up, then we need to set the ODR - * appropriately for that function. - */ - - if ((cfgset & GPIO_OUTPUT_SET) != 0) - { - /* Use the BSRR register to set the output */ - - regaddr = base + STM32_GPIO_BSRR_OFFSET; - } - else - { - /* Use the BRR register to clear */ - - regaddr = base + STM32_GPIO_BRR_OFFSET; - } - - regval = getreg32(regaddr); - regval |= (1 << pin); - putreg32(regval, regaddr); - - spin_unlock_irqrestore(&g_configgpio_lock, flags); - return OK; -} -#endif - -/**************************************************************************** - * Name: stm32_configgpio (for the STM32L15xxx, STM32F20xxx, STM32F40xxx, - * and STM32G4XXX families). - ****************************************************************************/ - -#if defined(CONFIG_STM32_STM32L15XX) || defined(CONFIG_STM32_STM32F20XX) || \ - defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) || \ - defined(CONFIG_STM32_STM32F37XX) || defined(CONFIG_STM32_STM32F4XXX) || \ - defined(CONFIG_STM32_STM32G4XXX) -int stm32_configgpio(uint32_t cfgset) -{ - uintptr_t base; - uint32_t regval; - uint32_t setting; - uint32_t alt_setting; - unsigned int regoffset; - unsigned int port; - unsigned int pin; - unsigned int pos; - unsigned int pinmode; - irqstate_t flags; - - /* Verify that this hardware supports the select GPIO port */ - - port = (cfgset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; - if (port >= STM32_NGPIO_PORTS) - { - return -EINVAL; - } - - /* Get the port base address */ - - base = g_gpiobase[port]; - - /* Get the pin number and select the port configuration register for that - * pin - */ - - pin = (cfgset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT; - - /* Set up the mode register (and remember whether the pin mode) */ - - switch (cfgset & GPIO_MODE_MASK) - { - default: - case GPIO_INPUT: /* Input mode */ - pinmode = GPIO_MODER_INPUT; - break; - - case GPIO_OUTPUT: /* General purpose output mode */ - - /* Set the initial output value */ - - stm32_gpiowrite(cfgset, (cfgset & GPIO_OUTPUT_SET) != 0); - pinmode = GPIO_MODER_OUTPUT; - break; - - case GPIO_ALT: /* Alternate function mode */ - pinmode = GPIO_MODER_ALT; - break; - - case GPIO_ANALOG: /* Analog mode */ - pinmode = GPIO_MODER_ANALOG; - break; - } - - /* Interrupts must be disabled from here on out so that we have mutually - * exclusive access to all of the GPIO configuration registers. - */ - - flags = spin_lock_irqsave(&g_configgpio_lock); - - /* Determine the alternate function (Only alternate function pins) */ - - if (pinmode == GPIO_MODER_ALT) - { - alt_setting = (cfgset & GPIO_AF_MASK) >> GPIO_AF_SHIFT; - } - else - { - alt_setting = 0; - } - - /* Set the alternate function (Only alternate function pins) - * This is done before configuring the Outputs on a change to - * an Alternate function. - */ - - if (alt_setting != 0) - { - if (pin < 8) - { - regoffset = STM32_GPIO_AFRL_OFFSET; - pos = pin; - } - else - { - regoffset = STM32_GPIO_AFRH_OFFSET; - pos = pin - 8; - } - - regval = getreg32(base + regoffset); - regval &= ~GPIO_AFR_MASK(pos); - regval |= (alt_setting << GPIO_AFR_SHIFT(pos)); - putreg32(regval, base + regoffset); - } - - /* Now apply the configuration to the mode register */ - - regval = getreg32(base + STM32_GPIO_MODER_OFFSET); - regval &= ~GPIO_MODER_MASK(pin); - regval |= ((uint32_t)pinmode << GPIO_MODER_SHIFT(pin)); - putreg32(regval, base + STM32_GPIO_MODER_OFFSET); - - /* Set up the pull-up/pull-down configuration (all but analog pins) */ - - setting = GPIO_PUPDR_NONE; - if (pinmode != GPIO_MODER_ANALOG) - { - switch (cfgset & GPIO_PUPD_MASK) - { - default: - case GPIO_FLOAT: /* No pull-up, pull-down */ - break; - - case GPIO_PULLUP: /* Pull-up */ - setting = GPIO_PUPDR_PULLUP; - break; - - case GPIO_PULLDOWN: /* Pull-down */ - setting = GPIO_PUPDR_PULLDOWN; - break; - } - } - - regval = getreg32(base + STM32_GPIO_PUPDR_OFFSET); - regval &= ~GPIO_PUPDR_MASK(pin); - regval |= (setting << GPIO_PUPDR_SHIFT(pin)); - putreg32(regval, base + STM32_GPIO_PUPDR_OFFSET); - - /* Set the alternate function (Only alternate function pins) - * This is done after configuring the pin's connection - * on a change away from an Alternate function. - */ - - if (alt_setting == 0) - { - if (pin < 8) - { - regoffset = STM32_GPIO_AFRL_OFFSET; - pos = pin; - } - else - { - regoffset = STM32_GPIO_AFRH_OFFSET; - pos = pin - 8; - } - - regval = getreg32(base + regoffset); - regval &= ~GPIO_AFR_MASK(pos); - regval |= (alt_setting << GPIO_AFR_SHIFT(pos)); - putreg32(regval, base + regoffset); - } - - /* Set speed (Only outputs and alternate function pins) */ - - if (pinmode == GPIO_MODER_OUTPUT || pinmode == GPIO_MODER_ALT) - { - switch (cfgset & GPIO_SPEED_MASK) - { -#if defined(CONFIG_STM32_STM32L15XX) - default: - case GPIO_SPEED_400KHz: /* 400 kHz Very low speed output */ - setting = GPIO_OSPEED_400KHz; - break; - - case GPIO_SPEED_2MHz: /* 2 MHz Low speed output */ - setting = GPIO_OSPEED_2MHz; - break; - - case GPIO_SPEED_10MHz: /* 10 MHz Medium speed output */ - setting = GPIO_OSPEED_10MHz; - break; - - case GPIO_SPEED_40MHz: /* 40 MHz High speed output */ - setting = GPIO_OSPEED_40MHz; - break; -#elif defined(CONFIG_STM32_STM32G4XXX) - default: - case GPIO_SPEED_5MHz: /* 5 MHz Low speed output */ - setting = GPIO_OSPEED_5MHz; - break; - - case GPIO_SPEED_25MHz: /* 25 MHz Medium speed output */ - setting = GPIO_OSPEED_25MHz; - break; - - case GPIO_SPEED_50MHz: /* 50 MHz Fast speed output */ - setting = GPIO_OSPEED_50MHz; - break; - - case GPIO_SPEED_120MHz: /* 120 MHz High speed output */ - setting = GPIO_OSPEED_120MHz; - break; -#else - default: - case GPIO_SPEED_2MHz: /* 2 MHz Low speed output */ - setting = GPIO_OSPEED_2MHz; - break; - - case GPIO_SPEED_25MHz: /* 25 MHz Medium speed output */ - setting = GPIO_OSPEED_25MHz; - break; - - case GPIO_SPEED_50MHz: /* 50 MHz Fast speed output */ - setting = GPIO_OSPEED_50MHz; - break; - -#if !defined(CONFIG_STM32_STM32F30XX) && !defined(CONFIG_STM32_STM32F33XX) && \ - !defined(CONFIG_STM32_STM32F37XX) - case GPIO_SPEED_100MHz: /* 100 MHz High speed output */ - setting = GPIO_OSPEED_100MHz; - break; -#endif -#endif - } - } - else - { - setting = 0; - } - - regval = getreg32(base + STM32_GPIO_OSPEED_OFFSET); - regval &= ~GPIO_OSPEED_MASK(pin); - regval |= (setting << GPIO_OSPEED_SHIFT(pin)); - putreg32(regval, base + STM32_GPIO_OSPEED_OFFSET); - - /* Set push-pull/open-drain (Only outputs and alternate function pins) */ - - regval = getreg32(base + STM32_GPIO_OTYPER_OFFSET); - setting = GPIO_OTYPER_OD(pin); - - if ((pinmode == GPIO_MODER_OUTPUT || pinmode == GPIO_MODER_ALT) && - (cfgset & GPIO_OPENDRAIN) != 0) - { - regval |= setting; - } - else - { - regval &= ~setting; - } - - putreg32(regval, base + STM32_GPIO_OTYPER_OFFSET); - - /* Otherwise, it is an input pin. Should it configured as an EXTI - * interrupt? - */ - - if (pinmode != GPIO_MODER_OUTPUT && (cfgset & GPIO_EXTI) != 0) - { - /* "In STM32 F1 the selection of the EXTI line source is performed - * through the EXTIx bits in the AFIO_EXTICRx registers, while in F2 - * series this selection is done through the EXTIx bits in the - * SYSCFG_EXTICRx registers. - * - * "Only the mapping of the EXTICRx registers has been changed, - * without any changes to the meaning of the EXTIx bits. However, - * the range of EXTI bits values has been extended to 0b1000 to - * support the two ports added in F2, port H and I (in F1 series - * the maximum value is 0b0110)." - */ - - uint32_t regaddr; - int shift; - - /* Set the bits in the SYSCFG EXTICR register */ - - regaddr = STM32_SYSCFG_EXTICR(pin); - regval = getreg32(regaddr); - shift = SYSCFG_EXTICR_EXTI_SHIFT(pin); - regval &= ~(SYSCFG_EXTICR_PORT_MASK << shift); - regval |= (((uint32_t)port) << shift); - - putreg32(regval, regaddr); - } - - spin_unlock_irqrestore(&g_configgpio_lock, flags); - return OK; -} -#endif - -/**************************************************************************** - * Name: stm32_unconfiggpio - * - * Description: - * Unconfigure a GPIO pin based on bit-encoded description of the pin, set - * it into default HiZ state (and possibly mark it's unused) and unlock it - * whether it was previously selected as an alternative function - * (GPIO_ALT | GPIO_CNF_AFPP | ...). - * - * This is a safety function and prevents hardware from shocks, as - * unexpected write to the Timer Channel Output GPIO to fixed '1' or '0' - * while it should operate in PWM mode could produce excessive on-board - * currents and trigger over-current/alarm function. - * - * Returned Value: - * OK on success - * A negated errno value on invalid port - * - * To-Do: Auto Power Disable - ****************************************************************************/ - -int stm32_unconfiggpio(uint32_t cfgset) -{ - /* Reuse port and pin number and set it to default HiZ INPUT */ - - cfgset &= GPIO_PORT_MASK | GPIO_PIN_MASK; -#if defined(CONFIG_STM32_STM32F10XX) - cfgset |= GPIO_INPUT | GPIO_CNF_INFLOAT | GPIO_MODE_INPUT; -#elif defined(CONFIG_STM32_STM32L15XX) || defined(CONFIG_STM32_STM32F20XX) || \ - defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) || \ - defined(CONFIG_STM32_STM32F37XX) || defined(CONFIG_STM32_STM32F4XXX) || \ - defined(CONFIG_STM32_STM32G4XXX) - cfgset |= GPIO_INPUT | GPIO_FLOAT; -#else -# error "Unsupported STM32 chip" -#endif - - /* To-Do: Mark its unuse for automatic power saving options */ - - return stm32_configgpio(cfgset); -} - -/**************************************************************************** - * Name: stm32_gpiowrite - * - * Description: - * Write one or zero to the selected GPIO pin - * - ****************************************************************************/ - -void stm32_gpiowrite(uint32_t pinset, bool value) -{ - uint32_t base; -#if defined(CONFIG_STM32_STM32F10XX) - uint32_t offset; -#elif defined(CONFIG_STM32_STM32L15XX) || defined(CONFIG_STM32_STM32F20XX) || \ - defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) || \ - defined(CONFIG_STM32_STM32F37XX) || defined(CONFIG_STM32_STM32F4XXX) || \ - defined(CONFIG_STM32_STM32G4XXX) - uint32_t bit; -#endif - unsigned int port; - unsigned int pin; - - port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; - if (port < STM32_NGPIO_PORTS) - { - /* Get the port base address */ - - base = g_gpiobase[port]; - - /* Get the pin number */ - - pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT; - - /* Set or clear the output on the pin */ - -#if defined(CONFIG_STM32_STM32F10XX) - - if (value) - { - offset = STM32_GPIO_BSRR_OFFSET; - } - else - { - offset = STM32_GPIO_BRR_OFFSET; - } - - putreg32((1 << pin), base + offset); - -#elif defined(CONFIG_STM32_STM32L15XX) || defined(CONFIG_STM32_STM32F20XX) || \ - defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) || \ - defined(CONFIG_STM32_STM32F37XX) || defined(CONFIG_STM32_STM32F4XXX) || \ - defined(CONFIG_STM32_STM32G4XXX) - - if (value) - { - bit = GPIO_BSRR_SET(pin); - } - else - { - bit = GPIO_BSRR_RESET(pin); - } - - putreg32(bit, base + STM32_GPIO_BSRR_OFFSET); - -#else -# error "Unsupported STM32 chip" -#endif - } -} - -/**************************************************************************** - * Name: stm32_gpioread - * - * Description: - * Read one or zero from the selected GPIO pin - * - ****************************************************************************/ - -bool stm32_gpioread(uint32_t pinset) -{ - uint32_t base; - unsigned int port; - unsigned int pin; - - port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; - if (port < STM32_NGPIO_PORTS) - { - /* Get the port base address */ - - base = g_gpiobase[port]; - - /* Get the pin number and return the input state of that pin */ - - pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT; - return ((getreg32(base + STM32_GPIO_IDR_OFFSET) & (1 << pin)) != 0); - } - - return 0; -} - -/**************************************************************************** - * Name: stm32_iocompensation - * - * Description: - * Enable I/O compensation. - * - * By default the I/O compensation cell is not used. However when the I/O - * output buffer speed is configured in 50 MHz or 100 MHz mode, it is - * recommended to use the compensation cell for slew rate control on I/O - * tf(IO)out)/tr(IO)out commutation to reduce the I/O noise on power - * supply. - * - * The I/O compensation cell can be used only when the supply voltage - * ranges from 2.4 to 3.6 V. - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_HAVE_IOCOMPENSATION -void stm32_iocompensation(void) -{ -#ifdef STM32_SYSCFG_CMPCR - /* Enable I/O Compensation. Writing '1' to the CMPCR power-down bit - * enables the I/O compensation cell. - */ - - putreg32(SYSCFG_CMPCR_CMPPD, STM32_SYSCFG_CMPCR); - - /* Wait for compensation cell to become ready */ - - while ((getreg32(STM32_SYSCFG_CMPCR) & SYSCFG_CMPCR_READY) == 0) - { - } -#endif -} -#endif diff --git a/arch/arm/src/stm32/stm32_gpio.h b/arch/arm/src/stm32/stm32_gpio.h deleted file mode 100644 index 8fc0ef475ebca..0000000000000 --- a/arch/arm/src/stm32/stm32_gpio.h +++ /dev/null @@ -1,562 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_gpio.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32_STM32_GPIO_H -#define __ARCH_ARM_SRC_STM32_STM32_GPIO_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#ifndef __ASSEMBLY__ -# include -# include -#endif - -#include - -#include "chip.h" - -#if defined(CONFIG_STM32_STM32L15XX) -# include "hardware/stm32l15xxx_gpio.h" -#elif defined(CONFIG_STM32_STM32F10XX) -# include "hardware/stm32f10xxx_gpio.h" -#elif defined(CONFIG_STM32_STM32F20XX) -# include "hardware/stm32f20xxx_gpio.h" -#elif defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) || \ - defined(CONFIG_STM32_STM32F37XX) -# include "hardware/stm32f30xxx_gpio.h" -#elif defined(CONFIG_STM32_STM32F4XXX) -# include "hardware/stm32f40xxx_gpio.h" -#elif defined(CONFIG_STM32_STM32G4XXX) -# include "hardware/stm32g4xxxx_gpio.h" -#else -# error "Unrecognized STM32 chip" -#endif - -/**************************************************************************** - * Pre-Processor Declarations - ****************************************************************************/ - -/* Bit-encoded input to stm32_configgpio() */ - -#if defined(CONFIG_STM32_STM32F10XX) - -/* 16-bit Encoding: - * - * 1111 1100 0000 0000 - * 5432 1098 7654 3210 - * ---- ---- ---- ---- - * OFFS SX.. VPPP BBBB - */ - -/* Output mode: - * - * 1111 1100 0000 0000 - * 5432 1098 7654 3210 - * ---- ---- ---- ---- - * O... .... .... .... - */ - -#define GPIO_INPUT (1 << 15) /* Bit 15: 1=Input mode */ -#define GPIO_OUTPUT (0) /* 0=Output or alternate function */ -#define GPIO_ALT (0) - -/* If the pin is a GPIO digital output, then this identifies the initial - * output value. If the pin is an input, this bit is overloaded to - * provide the qualifier to\ distinguish input pull-up and -down: - * - * 1111 1100 0000 0000 - * 5432 1098 7654 3210 - * ---- ---- ---- ---- - * .... .... V... .... - */ - -#define GPIO_OUTPUT_SET (1 << 7) /* Bit 7: If output, initial value of output */ -#define GPIO_OUTPUT_CLEAR (0) - -/* These bits set the primary function of the pin: - * - * 1111 1100 0000 0000 - * 5432 1098 7654 3210 - * ---- ---- ---- ---- - * .FF. .... .... .... - */ - -#define GPIO_CNF_SHIFT 13 /* Bits 13-14: GPIO function */ -#define GPIO_CNF_MASK (3 << GPIO_CNF_SHIFT) - -# define GPIO_CNF_ANALOGIN (0 << GPIO_CNF_SHIFT) /* Analog input */ -# define GPIO_CNF_INFLOAT (1 << GPIO_CNF_SHIFT) /* Input floating */ -# define GPIO_CNF_INPULLUD (2 << GPIO_CNF_SHIFT) /* Input pull-up/down general bit, since up is composed of two parts */ -# define GPIO_CNF_INPULLDWN (2 << GPIO_CNF_SHIFT) /* Input pull-down */ -# define GPIO_CNF_INPULLUP ((2 << GPIO_CNF_SHIFT) \ - | GPIO_OUTPUT_SET) /* Input pull-up */ - -# define GPIO_CNF_OUTPP (0 << GPIO_CNF_SHIFT) /* Output push-pull */ -# define GPIO_CNF_OUTOD (1 << GPIO_CNF_SHIFT) /* Output open-drain */ -# define GPIO_CNF_AFPP (2 << GPIO_CNF_SHIFT) /* Alternate function push-pull */ -# define GPIO_CNF_AFOD (3 << GPIO_CNF_SHIFT) /* Alternate function open-drain */ - -/* Maximum frequency selection: - * - * 1111 1100 0000 0000 - * 5432 1098 7654 3210 - * ---- ---- ---- ---- - * ...S S... .... .... - */ - -#define GPIO_MODE_SHIFT 11 /* Bits 11-12: GPIO frequency selection */ -#define GPIO_MODE_MASK (3 << GPIO_MODE_SHIFT) -# define GPIO_MODE_INPUT (0 << GPIO_MODE_SHIFT) /* Input mode (reset state) */ -# define GPIO_MODE_10MHz (1 << GPIO_MODE_SHIFT) /* Output mode, max speed 10 MHz */ -# define GPIO_MODE_2MHz (2 << GPIO_MODE_SHIFT) /* Output mode, max speed 2 MHz */ -# define GPIO_MODE_50MHz (3 << GPIO_MODE_SHIFT) /* Output mode, max speed 50 MHz */ - -#define GPIO_ADJUST_MODE(p, m) (((p) & ~GPIO_MODE_MASK) | (m)) - -/* External interrupt selection (GPIO inputs only): - * - * 1111 1100 0000 0000 - * 5432 1098 7654 3210 - * ---- ---- ---- ---- - * .... .X.. .... .... - */ - -#define GPIO_EXTI (1 << 10) /* Bit 10: Configure as EXTI interrupt */ - -/* This identifies the GPIO port: - * - * 1111 1100 0000 0000 - * 5432 1098 7654 3210 - * ---- ---- ---- ---- - * .... .... .PPP .... - */ - -#define GPIO_PORT_SHIFT 4 /* Bit 4-6: Port number */ -#define GPIO_PORT_MASK (7 << GPIO_PORT_SHIFT) -# define GPIO_PORTA (0 << GPIO_PORT_SHIFT) /* GPIOA */ -# define GPIO_PORTB (1 << GPIO_PORT_SHIFT) /* GPIOB */ -# define GPIO_PORTC (2 << GPIO_PORT_SHIFT) /* GPIOC */ -# define GPIO_PORTD (3 << GPIO_PORT_SHIFT) /* GPIOD */ -# define GPIO_PORTE (4 << GPIO_PORT_SHIFT) /* GPIOE */ -# define GPIO_PORTF (5 << GPIO_PORT_SHIFT) /* GPIOF */ -# define GPIO_PORTG (6 << GPIO_PORT_SHIFT) /* GPIOG */ - -/* This identifies the bit in the port: - * - * 1111 1100 0000 0000 - * 5432 1098 7654 3210 - * ---- ---- ---- ---- - * .... .... .... BBBB - */ - -#define GPIO_PIN_SHIFT 0 /* Bits 0-3: GPIO number: 0-15 */ -#define GPIO_PIN_MASK (15 << GPIO_PIN_SHIFT) -#define GPIO_PIN0 (0 << GPIO_PIN_SHIFT) -#define GPIO_PIN1 (1 << GPIO_PIN_SHIFT) -#define GPIO_PIN2 (2 << GPIO_PIN_SHIFT) -#define GPIO_PIN3 (3 << GPIO_PIN_SHIFT) -#define GPIO_PIN4 (4 << GPIO_PIN_SHIFT) -#define GPIO_PIN5 (5 << GPIO_PIN_SHIFT) -#define GPIO_PIN6 (6 << GPIO_PIN_SHIFT) -#define GPIO_PIN7 (7 << GPIO_PIN_SHIFT) -#define GPIO_PIN8 (8 << GPIO_PIN_SHIFT) -#define GPIO_PIN9 (9 << GPIO_PIN_SHIFT) -#define GPIO_PIN10 (10 << GPIO_PIN_SHIFT) -#define GPIO_PIN11 (11 << GPIO_PIN_SHIFT) -#define GPIO_PIN12 (12 << GPIO_PIN_SHIFT) -#define GPIO_PIN13 (13 << GPIO_PIN_SHIFT) -#define GPIO_PIN14 (14 << GPIO_PIN_SHIFT) -#define GPIO_PIN15 (15 << GPIO_PIN_SHIFT) - -#elif defined(CONFIG_STM32_STM32L15XX) || defined(CONFIG_STM32_STM32F20XX) || \ - defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) || \ - defined(CONFIG_STM32_STM32F37XX) || defined(CONFIG_STM32_STM32F4XXX) || \ - defined(CONFIG_STM32_STM32G4XXX) -/* Each port bit of the general-purpose I/O (GPIO) ports can be - * individually configured by software in several modes: - * - * - Input floating - * - Input pull-up - * - Input-pull-down - * - Output open-drain with pull-up or pull-down capability - * - Output push-pull with pull-up or pull-down capability - * - Alternate function push-pull with pull-up or pull-down capability - * - Alternate function open-drain with pull-up or pull-down capability - * - Analog - * - * 20-bit Encoding: 1111 1111 1100 0000 0000 - * 9876 5432 1098 7654 3210 - * ---- ---- ---- ---- ---- - * Inputs: MMUU .... ...X PPPP BBBB - * Outputs: MMUU .... FFOV PPPP BBBB - * Alternate Functions: MMUU AAAA FFO. PPPP BBBB - * Analog: MM.. .... .... PPPP BBBB - */ - -/* Mode: - * - * 1111 1111 1100 0000 0000 - * 9876 5432 1098 7654 3210 - * ---- ---- ---- ---- ---- - * MM.. .... .... .... .... - */ - -#define GPIO_MODE_SHIFT (18) /* Bits 18-19: GPIO port mode */ -#define GPIO_MODE_MASK (3 << GPIO_MODE_SHIFT) -# define GPIO_INPUT (0 << GPIO_MODE_SHIFT) /* Input mode */ -# define GPIO_OUTPUT (1 << GPIO_MODE_SHIFT) /* General purpose output mode */ -# define GPIO_ALT (2 << GPIO_MODE_SHIFT) /* Alternate function mode */ -# define GPIO_ANALOG (3 << GPIO_MODE_SHIFT) /* Analog mode */ - -/* Input/output pull-ups/downs (not used with analog): - * - * 1111 1111 1100 0000 0000 - * 9876 5432 1098 7654 3210 - * ---- ---- ---- ---- ---- - * ..UU .... .... .... .... - */ - -#define GPIO_PUPD_SHIFT (16) /* Bits 16-17: Pull-up/pull down */ -#define GPIO_PUPD_MASK (3 << GPIO_PUPD_SHIFT) -# define GPIO_FLOAT (0 << GPIO_PUPD_SHIFT) /* No pull-up, pull-down */ -# define GPIO_PULLUP (1 << GPIO_PUPD_SHIFT) /* Pull-up */ -# define GPIO_PULLDOWN (2 << GPIO_PUPD_SHIFT) /* Pull-down */ - -/* Alternate Functions: - * - * 1111 1111 1100 0000 0000 - * 9876 5432 1098 7654 3210 - * ---- ---- ---- ---- ---- - * .... AAAA .... .... .... - */ - -#define GPIO_AF_SHIFT (12) /* Bits 12-15: Alternate function */ -#define GPIO_AF_MASK (15 << GPIO_AF_SHIFT) -# define GPIO_AF(n) ((n) << GPIO_AF_SHIFT) -# define GPIO_AF0 (0 << GPIO_AF_SHIFT) -# define GPIO_AF1 (1 << GPIO_AF_SHIFT) -# define GPIO_AF2 (2 << GPIO_AF_SHIFT) -# define GPIO_AF3 (3 << GPIO_AF_SHIFT) -# define GPIO_AF4 (4 << GPIO_AF_SHIFT) -# define GPIO_AF5 (5 << GPIO_AF_SHIFT) -# define GPIO_AF6 (6 << GPIO_AF_SHIFT) -# define GPIO_AF7 (7 << GPIO_AF_SHIFT) -# define GPIO_AF8 (8 << GPIO_AF_SHIFT) -# define GPIO_AF9 (9 << GPIO_AF_SHIFT) -# define GPIO_AF10 (10 << GPIO_AF_SHIFT) -# define GPIO_AF11 (11 << GPIO_AF_SHIFT) -# define GPIO_AF12 (12 << GPIO_AF_SHIFT) -# define GPIO_AF13 (13 << GPIO_AF_SHIFT) -# define GPIO_AF14 (14 << GPIO_AF_SHIFT) -# define GPIO_AF15 (15 << GPIO_AF_SHIFT) - -/* Output/Alt function frequency selection: - * - * 1111 1111 1100 0000 0000 - * 9876 5432 1098 7654 3210 - * ---- ---- ---- ---- ---- - * .... .... FF.. .... .... - */ - -#define GPIO_SPEED_SHIFT (10) /* Bits 10-11: GPIO frequency selection */ -#define GPIO_SPEED_MASK (3 << GPIO_SPEED_SHIFT) -#if defined(CONFIG_STM32_STM32L15XX) -# define GPIO_SPEED_400KHz (0 << GPIO_SPEED_SHIFT) /* 400 kHz Very low speed output */ -# define GPIO_SPEED_2MHz (1 << GPIO_SPEED_SHIFT) /* 2 MHz Low speed output */ -# define GPIO_SPEED_10MHz (2 << GPIO_SPEED_SHIFT) /* 10 MHz Medium speed output */ -# define GPIO_SPEED_40MHz (3 << GPIO_SPEED_SHIFT) /* 40 MHz High speed output */ -#elif defined(CONFIG_STM32_STM32G4XXX) /* With C=50pF, 2.7 - -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include - -#include "arm_internal.h" -#include "chip.h" -#include "stm32_uart.h" -#include "stm32_dma.h" -#include "stm32_rcc.h" -#include "stm32_hciuart.h" - -#include - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Some sanity checks *******************************************************/ - -/* DMA configuration */ - -/* If DMA is enabled on any USART, then very that other pre-requisites - * have also been selected. - */ - -#ifdef CONFIG_STM32_HCIUART_RXDMA - -# if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) -/* Verify that DMA has been enabled and the DMA channel has been defined. - */ - -# if defined(CONFIG_STM32_HCIUART1_RXDMA) || defined(CONFIG_STM32_HCIUART6_RXDMA) -# ifndef CONFIG_STM32_DMA2 -# error STM32 USART1/6 receive DMA requires CONFIG_STM32_DMA2 -# endif -# endif - -# if defined(CONFIG_STM32_HCIUART2_RXDMA) || defined(CONFIG_STM32_HCIUART3_RXDMA) || \ - defined(CONFIG_STM32_HCIUART7_RXDMA) || defined(CONFIG_STM32_HCIUART8_RXDMA) -# ifndef CONFIG_STM32_DMA1 -# error STM32 USART2/3/4/5/7/8 receive DMA requires CONFIG_STM32_DMA1 -# endif -# endif - -/* For the F4, there are alternate DMA channels for USART1 and 6. - * Logic in the board.h file make the DMA channel selection by defining - * the following in the board.h file. - */ - -# if defined(CONFIG_STM32_HCIUART1_RXDMA) && !defined(DMAMAP_USART1_RX) -# error "USART1 DMA channel not defined (DMAMAP_USART1_RX)" -# endif - -# if defined(CONFIG_STM32_HCIUART2_RXDMA) && !defined(DMAMAP_USART2_RX) -# error "USART2 DMA channel not defined (DMAMAP_USART2_RX)" -# endif - -# if defined(CONFIG_STM32_HCIUART3_RXDMA) && !defined(DMAMAP_USART3_RX) -# error "USART3 DMA channel not defined (DMAMAP_USART3_RX)" -# endif - -# if defined(CONFIG_STM32_HCIUART6_RXDMA) && !defined(DMAMAP_USART6_RX) -# error "USART6 DMA channel not defined (DMAMAP_USART6_RX)" -# endif - -# if defined(CONFIG_STM32_HCIUART7_RXDMA) && !defined(DMAMAP_UART7_RX) -# error "UART7 DMA channel not defined (DMAMAP_UART7_RX)" -# endif - -# if defined(CONFIG_STM32_HCIUART8_RXDMA) && !defined(DMAMAP_UART8_RX) -# error "UART8 DMA channel not defined (DMAMAP_UART8_RX)" -# endif - -# elif defined(CONFIG_STM32_STM32L15XX) || defined(CONFIG_STM32_STM32F10XX) || \ - defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) || \ - defined(CONFIG_STM32_STM32F37XX) - -# if defined(CONFIG_STM32_HCIUART1_RXDMA) || defined(CONFIG_STM32_HCIUART2_RXDMA) || \ - defined(CONFIG_STM32_HCIUART3_RXDMA) -# ifndef CONFIG_STM32_DMA1 -# error STM32 USART1/2/3 receive DMA requires CONFIG_STM32_DMA1 -# endif -# endif - -/* There are no optional DMA channel assignments for the F1 */ - -# define DMAMAP_USART1_RX DMACHAN_USART1_RX -# define DMAMAP_USART2_RX DMACHAN_USART2_RX -# define DMAMAP_USART3_RX DMACHAN_USART3_RX - -# endif - -/* The DMA buffer size when using RX DMA to emulate a FIFO. - * - * When streaming data, the generic serial layer will be called - * every time the FIFO receives half this number of bytes. - */ - -# if !defined(CONFIG_STM32_HCIUART_RXDMA_BUFSIZE) -# define CONFIG_STM32_HCIUART_RXDMA_BUFSIZE 32 -# endif -# define RXDMA_MULTIPLE 4 -# define RXDMA_MULTIPLE_MASK (RXDMA_MULTIPLE -1) -# define RXDMA_BUFFER_SIZE ((CONFIG_STM32_HCIUART_RXDMA_BUFSIZE + \ - RXDMA_MULTIPLE_MASK) & ~RXDMA_MULTIPLE_MASK) - -/* DMA priority */ - -# ifndef CONFIG_STM32_HCIUART_RXDMAPRIO -# if defined(CONFIG_STM32_STM32L15XX) || defined(CONFIG_STM32_STM32F10XX) || \ - defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) || \ - defined(CONFIG_STM32_STM32F37XX) -# define CONFIG_STM32_HCIUART_RXDMAPRIO DMA_CCR_PRIMED -# elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) -# define CONFIG_STM32_HCIUART_RXDMAPRIO DMA_SCR_PRIMED -# else -# error "Unknown STM32 DMA" -# endif -# endif -# if defined(CONFIG_STM32_STM32L15XX) || defined(CONFIG_STM32_STM32F10XX) || \ - defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) || \ - defined(CONFIG_STM32_STM32F37XX) -# if (CONFIG_STM32_HCIUART_RXDMAPRIO & ~DMA_CCR_PL_MASK) != 0 -# error "Illegal value for CONFIG_STM32_HCIUART_RXDMAPRIO" -# endif -# elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) -# if (CONFIG_STM32_HCIUART_RXDMAPRIO & ~DMA_SCR_PL_MASK) != 0 -# error "Illegal value for CONFIG_STM32_HCIUART_RXDMAPRIO" -# endif -# else -# error "Unknown STM32 DMA" -# endif - -/* DMA control word */ - -# if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) -# define SERIAL_DMA_CONTROL_WORD \ - (DMA_SCR_DIR_P2M | \ - DMA_SCR_CIRC | \ - DMA_SCR_MINC | \ - DMA_SCR_PSIZE_8BITS | \ - DMA_SCR_MSIZE_8BITS | \ - CONFIG_STM32_HCIUART_RXDMAPRIO | \ - DMA_SCR_PBURST_SINGLE | \ - DMA_SCR_MBURST_SINGLE) -# else -# define SERIAL_DMA_CONTROL_WORD \ - (DMA_CCR_CIRC | \ - DMA_CCR_MINC | \ - DMA_CCR_PSIZE_8BITS | \ - DMA_CCR_MSIZE_8BITS | \ - CONFIG_STM32_HCIUART_RXDMAPRIO) -# endif -#endif - -/* All interrupts */ - -#define HCIUART_ALLINTS (USART_CR1_USED_INTS | USART_CR3_EIE) -#define HCIUART_RXHANDLED (1 << 0) -#define HCIUART_TXHANDLED (1 << 1) - -/* Software flow control */ - -#ifdef CONFIG_STM32_HCIUART_SW_RXFLOW -# if (CONFIG_STM32_HCIUART_UPPER_WATERMARK < CONFIG_STM32_HCIUART_LOWER_WATERMARK) -# error The upper Rx flow control watermark is belong the lower watermake -# endif - -# define RXFLOW_UPPER(a) ((CONFIG_STM32_HCIUART_UPPER_WATERMARK * (a)) / 100) -# define RXFLOW_LOWER(a) ((CONFIG_STM32_HCIUART_LOWER_WATERMARK * (a)) / 100) -#endif - -/* Power management definitions */ - -#if defined(CONFIG_PM) && !defined(CONFIG_STM32_PM_SERIAL_ACTIVITY) -# define CONFIG_STM32_PM_SERIAL_ACTIVITY 10 -#endif - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/* This structure is the variable state of the HCI UART */ - -struct hciuart_state_s -{ - /* Registered Rx callback */ - - btuart_rxcallback_t callback; /* Rx callback function */ - void *arg; /* Rx callback argument */ - - /* Rx/Tx circular buffer management */ - - sem_t rxwait; /* Supports wait for more Rx data */ - sem_t txwait; /* Supports wait for space in Tx buffer */ - - uint32_t baud; /* Current BAUD selection */ - volatile uint16_t rxhead; /* Head and tail index of the Rx buffer */ - uint16_t rxtail; - uint16_t txhead; /* Head and tail index of the Tx buffer */ - volatile uint16_t txtail; - volatile bool rxwaiting; /* A thread is waiting for more Rx data */ - volatile bool txwaiting; /* A thread is waiting for space in the Tx buffer */ -#ifdef CONFIG_STM32_HCIUART_SW_RXFLOW - bool rxflow; /* True: software flow control is enable */ -#endif - - /* RX DMA state */ - -#ifdef CONFIG_STM32_HCIUART_RXDMA - uint16_t dmatail; /* Tail index of the Rx DMA buffer */ - bool rxenable; /* DMA-based reception en/disable */ - DMA_HANDLE rxdmastream; /* currently-open receive DMA stream */ -#endif -}; - -/* This structure is the constant configuration of the HCI UART */ - -struct hciuart_config_s -{ - struct btuart_lowerhalf_s lower; /* Generic HCI-UART lower half */ - struct hciuart_state_s *state; /* Reference to variable state */ - uint8_t *rxbuffer; /* Rx buffer start */ - uint8_t *txbuffer; /* Tx buffer start */ -#ifdef CONFIG_STM32_HCIUART_RXDMA - uint8_t *rxdmabuffer; /* Rx DMA buffer start */ -#endif - uint16_t rxbufsize; /* Size of the Rx buffer */ - uint16_t txbufsize; /* Size of the tx buffer */ -#ifdef CONFIG_STM32_HCIUART_SW_RXFLOW - uint16_t rxupper; /* Upper watermark to enable Rx flow control */ - uint16_t rxlower; /* Lower watermark to disable Rx flow control */ -#endif -#ifdef CONFIG_STM32_HCIUART_RXDMA - uint8_t rxdmachan; /* Rx DMA channel */ -#endif - uint8_t irq; /* IRQ associated with this USART */ - uint32_t baud; /* Configured baud */ - uint32_t apbclock; /* PCLK 1 or 2 frequency */ - uint32_t usartbase; /* Base address of USART registers */ - uint32_t tx_gpio; /* U[S]ART TX GPIO pin configuration */ - uint32_t rx_gpio; /* U[S]ART RX GPIO pin configuration */ - uint32_t cts_gpio; /* U[S]ART CTS GPIO pin configuration */ - uint32_t rts_gpio; /* U[S]ART RTS GPIO pin configuration */ - spinlock_t lock; /* Spinlock */ -}; - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -static inline uint32_t hciuart_getreg32( - const struct hciuart_config_s *config, unsigned int offset); -static inline void hciuart_putreg32(const struct hciuart_config_s *config, - unsigned int offset, uint32_t value); -static void hciuart_enableints(const struct hciuart_config_s *config, - uint32_t intset); -static void hciuart_disableints(const struct hciuart_config_s *config, - uint32_t intset); -static bool hciuart_isenabled(const struct hciuart_config_s *config, - uint32_t intset); -static inline bool hciuart_rxenabled(const struct hciuart_config_s *config); -#ifdef CONFIG_STM32_HCIUART_RXDMA -static int hciuart_dma_nextrx(const struct hciuart_config_s *config); -#endif - -static uint16_t hciuart_rxinuse(const struct hciuart_config_s *config); -static void hciuart_rxflow_enable(const struct hciuart_config_s *config); -static void hciuart_rxflow_disable(const struct hciuart_config_s *config); -static ssize_t hciuart_copytorxbuffer(const struct hciuart_config_s *config); -static ssize_t hciuart_copyfromrxbuffer( - const struct hciuart_config_s *config, uint8_t *dest, - size_t destlen); -static ssize_t hciuart_copytotxfifo(const struct hciuart_config_s *config); -static void hciuart_line_configure(const struct hciuart_config_s *config); -static void hciuart_apbclock_enable(const struct hciuart_config_s *config); -static int hciuart_configure(const struct hciuart_config_s *config); -static int hciuart_interrupt(int irq, void *context, void *arg); - -/* HCI-UART Lower-Half Methods */ - -static void hciuart_rxattach(const struct btuart_lowerhalf_s *lower, - btuart_rxcallback_t callback, void *arg); -static void hciuart_rxenable(const struct btuart_lowerhalf_s *lower, - bool enable); -static int hciuart_setbaud(const struct btuart_lowerhalf_s *lower, - uint32_t baud); -static ssize_t hciuart_read(const struct btuart_lowerhalf_s *lower, - void *buffer, size_t buflen); -static ssize_t hciuart_write(const struct btuart_lowerhalf_s *lower, - const void *buffer, size_t buflen); -static ssize_t hciuart_rxdrain(const struct btuart_lowerhalf_s *lower); - -#ifdef CONFIG_STM32_HCIUART_RXDMA -static void hciuart_dma_rxcallback(DMA_HANDLE handle, uint8_t status, - void *arg); -#endif - -#ifdef CONFIG_PM -static void hciuart_pm_notify(struct pm_callback_s *cb, int dowmin, - enum pm_state_e pmstate); -static int hciuart_pm_prepare(struct pm_callback_s *cb, int domain, - enum pm_state_e pmstate); -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* This describes the state of the STM32 USART1 ports. */ - -#ifdef CONFIG_STM32_USART1_HCIUART -/* I/O buffers */ - -static uint8_t g_usart1_rxbuffer[CONFIG_STM32_HCIUART1_RXBUFSIZE]; -static uint8_t g_usart1_txbuffer[CONFIG_STM32_HCIUART1_TXBUFSIZE]; -# ifdef CONFIG_STM32_HCIUART1_RXDMA -static uint8_t g_usart1_rxdmabuffer[RXDMA_BUFFER_SIZE]; -# endif - -/* HCI USART1 variable state information */ - -static struct hciuart_state_s g_hciusart1_state = -{ - .rxwait = SEM_INITIALIZER(0), - .txwait = SEM_INITIALIZER(0), -}; - -/* HCI USART1 constant configuration information */ - -static const struct hciuart_config_s g_hciusart1_config = -{ - .lower = - { - .rxattach = hciuart_rxattach, - .rxenable = hciuart_rxenable, - .setbaud = hciuart_setbaud, - .read = hciuart_read, - .write = hciuart_write, - .rxdrain = hciuart_rxdrain, - }, - .state = &g_hciusart1_state, - - .rxbuffer = g_usart1_rxbuffer, - .txbuffer = g_usart1_txbuffer, -# ifdef CONFIG_STM32_HCIUART1_RXDMA - .rxdmabuffer = g_usart1_rxdmabuffer, -# endif - .rxbufsize = CONFIG_STM32_HCIUART1_RXBUFSIZE, - .txbufsize = CONFIG_STM32_HCIUART1_TXBUFSIZE, -# ifdef CONFIG_STM32_HCIUART_SW_RXFLOW - .rxupper = RXFLOW_UPPER(CONFIG_STM32_HCIUART1_RXBUFSIZE), - .rxlower = RXFLOW_LOWER(CONFIG_STM32_HCIUART1_RXBUFSIZE), -# endif -# ifdef CONFIG_STM32_HCIUART_RXDMA - .rxdmachan = DMAMAP_USART1_RX, -# endif - - .irq = STM32_IRQ_USART1, - .baud = CONFIG_STM32_HCIUART1_BAUD, -# if defined(CONFIG_STM32_STM32F33XX) - .apbclock = STM32_PCLK1_FREQUENCY, /* Errata 2.5.1 */ -# else - .apbclock = STM32_PCLK2_FREQUENCY, -# endif - .usartbase = STM32_USART1_BASE, - .tx_gpio = GPIO_USART1_TX, - .rx_gpio = GPIO_USART1_RX, - .cts_gpio = GPIO_USART1_CTS, - .rts_gpio = GPIO_USART1_RTS, - .lock = SP_UNLOCKED -}; -#endif - -/* This describes the state of the STM32 USART2 port. */ - -#ifdef CONFIG_STM32_USART2_HCIUART -/* I/O buffers */ - -static uint8_t g_usart2_rxbuffer[CONFIG_STM32_HCIUART2_RXBUFSIZE]; -static uint8_t g_usart2_txbuffer[CONFIG_STM32_HCIUART2_TXBUFSIZE]; -# ifdef CONFIG_STM32_HCIUART2_RXDMA -static uint8_t g_usart2_rxdmabuffer[RXDMA_BUFFER_SIZE]; -# endif - -/* HCI USART2 variable state information */ - -static struct hciuart_state_s g_hciusart2_state = -{ - .rxwait = SEM_INITIALIZER(0), - .txwait = SEM_INITIALIZER(0), -}; - -/* HCI USART2 constant configuration information */ - -static const struct hciuart_config_s g_hciusart2_config = -{ - .lower = - { - .rxattach = hciuart_rxattach, - .rxenable = hciuart_rxenable, - .setbaud = hciuart_setbaud, - .read = hciuart_read, - .write = hciuart_write, - .rxdrain = hciuart_rxdrain, - }, - .state = &g_hciusart2_state, - - .rxbuffer = g_usart2_rxbuffer, - .txbuffer = g_usart2_txbuffer, -# ifdef CONFIG_STM32_HCIUART2_RXDMA - .rxdmabuffer = g_usart2_rxdmabuffer, -# endif - .rxbufsize = CONFIG_STM32_HCIUART2_RXBUFSIZE, - .txbufsize = CONFIG_STM32_HCIUART2_TXBUFSIZE, -# ifdef CONFIG_STM32_HCIUART_SW_RXFLOW - .rxupper = RXFLOW_UPPER(CONFIG_STM32_HCIUART2_RXBUFSIZE), - .rxlower = RXFLOW_LOWER(CONFIG_STM32_HCIUART2_RXBUFSIZE), -# endif -# ifdef CONFIG_STM32_HCIUART_RXDMA - .rxdmachan = DMAMAP_USART2_RX, -# endif - - .irq = STM32_IRQ_USART2, - .baud = CONFIG_STM32_HCIUART2_BAUD, - .apbclock = STM32_PCLK1_FREQUENCY, - .usartbase = STM32_USART2_BASE, - .tx_gpio = GPIO_USART2_TX, - .rx_gpio = GPIO_USART2_RX, - .cts_gpio = GPIO_USART2_CTS, - .rts_gpio = GPIO_USART2_RTS, - .lock = SP_UNLOCKED -}; -#endif - -/* This describes the state of the STM32 USART3 port. */ - -#ifdef CONFIG_STM32_USART3_HCIUART -/* I/O buffers */ - -static uint8_t g_usart3_rxbuffer[CONFIG_STM32_HCIUART3_RXBUFSIZE]; -static uint8_t g_usart3_txbuffer[CONFIG_STM32_HCIUART3_TXBUFSIZE]; -# ifdef CONFIG_STM32_HCIUART3_RXDMA -static uint8_t g_usart3_rxdmabuffer[RXDMA_BUFFER_SIZE]; -# endif - -/* HCI USART3 variable state information */ - -static struct hciuart_state_s g_hciusart3_state = -{ - .rxwait = SEM_INITIALIZER(0), - .txwait = SEM_INITIALIZER(0), -}; - -/* HCI USART3 constant configuration information */ - -static const struct hciuart_config_s g_hciusart3_config = -{ - .lower = - { - .rxattach = hciuart_rxattach, - .rxenable = hciuart_rxenable, - .setbaud = hciuart_setbaud, - .read = hciuart_read, - .write = hciuart_write, - .rxdrain = hciuart_rxdrain, - }, - .state = &g_hciusart3_state, - - .rxbuffer = g_usart3_rxbuffer, - .txbuffer = g_usart3_txbuffer, -# ifdef CONFIG_STM32_HCIUART3_RXDMA - .rxdmabuffer = g_usart3_rxdmabuffer, -# endif - .rxbufsize = CONFIG_STM32_HCIUART3_RXBUFSIZE, - .txbufsize = CONFIG_STM32_HCIUART3_TXBUFSIZE, -# ifdef CONFIG_STM32_HCIUART_SW_RXFLOW - .rxupper = RXFLOW_UPPER(CONFIG_STM32_HCIUART3_RXBUFSIZE), - .rxlower = RXFLOW_LOWER(CONFIG_STM32_HCIUART3_RXBUFSIZE), -# endif -# ifdef CONFIG_STM32_HCIUART_RXDMA - .rxdmachan = DMAMAP_USART3_RX, -# endif - - .irq = STM32_IRQ_USART3, - .baud = CONFIG_STM32_HCIUART3_BAUD, - .apbclock = STM32_PCLK1_FREQUENCY, - .usartbase = STM32_USART3_BASE, - .tx_gpio = GPIO_USART3_TX, - .rx_gpio = GPIO_USART3_RX, - .cts_gpio = GPIO_USART3_CTS, - .rts_gpio = GPIO_USART3_RTS, - .lock = SP_UNLOCKED -}; -#endif - -/* This describes the state of the STM32 USART6 port. */ - -#ifdef CONFIG_STM32_USART6_HCIUART -/* I/O buffers */ - -static uint8_t g_usart6_rxbuffer[CONFIG_STM32_HCIUART6_RXBUFSIZE]; -static uint8_t g_usart6_txbuffer[CONFIG_STM32_HCIUART6_TXBUFSIZE]; -# ifdef CONFIG_STM32_HCIUART6_RXDMA -static uint8_t g_usart6_rxdmabuffer[RXDMA_BUFFER_SIZE]; -# endif - -/* HCI USART6 variable state information */ - -static struct hciuart_state_s g_hciusart6_state = -{ - .rxwait = SEM_INITIALIZER(0), - .txwait = SEM_INITIALIZER(0), -}; - -/* HCI USART6 constant configuration information */ - -static const struct hciuart_config_s g_hciusart6_config = -{ - .lower = - { - .rxattach = hciuart_rxattach, - .rxenable = hciuart_rxenable, - .setbaud = hciuart_setbaud, - .read = hciuart_read, - .write = hciuart_write, - .rxdrain = hciuart_rxdrain, - }, - .state = &g_hciusart6_state, - - .rxbuffer = g_usart6_rxbuffer, - .txbuffer = g_usart6_txbuffer, -# ifdef CONFIG_STM32_HCIUART6_RXDMA - .rxdmabuffer = g_usart6_rxdmabuffer, -# endif - .rxbufsize = CONFIG_STM32_HCIUART6_RXBUFSIZE, - .txbufsize = CONFIG_STM32_HCIUART6_TXBUFSIZE, -# ifdef CONFIG_STM32_HCIUART_SW_RXFLOW - .rxupper = RXFLOW_UPPER(CONFIG_STM32_HCIUART6_RXBUFSIZE), - .rxlower = RXFLOW_LOWER(CONFIG_STM32_HCIUART6_RXBUFSIZE), -# endif -# ifdef CONFIG_STM32_HCIUART_RXDMA - .rxdmachan = DMAMAP_USART6_RX, -# endif - - .irq = STM32_IRQ_USART6, - .baud = CONFIG_STM32_HCIUART6_BAUD, - .apbclock = STM32_PCLK2_FREQUENCY, - .usartbase = STM32_USART6_BASE, - .tx_gpio = GPIO_USART6_TX, - .rx_gpio = GPIO_USART6_RX, - .cts_gpio = GPIO_USART6_CTS, - .rts_gpio = GPIO_USART6_RTS, - .lock = SP_UNLOCKED -}; -#endif - -/* This describes the state of the STM32 UART7 port. */ - -#ifdef CONFIG_STM32_UART7_HCIUART -/* I/O buffers */ - -static uint8_t g_uart7_rxbuffer[CONFIG_STM32_HCIUART7_RXBUFSIZE]; -static uint8_t g_uart7_txbuffer[CONFIG_STM32_HCIUART7_TXBUFSIZE]; -# ifdef CONFIG_STM32_HCIUART7_RXDMA -static uint8_t g_uart7_rxdmabuffer[RXDMA_BUFFER_SIZE]; -# endif - -/* HCI UART7 variable state information */ - -static struct hciuart_state_s g_hciuart7_state = -{ - .rxwait = SEM_INITIALIZER(0), - .txwait = SEM_INITIALIZER(0), -}; - -/* HCI UART7 constant configuration information */ - -static const struct hciuart_config_s g_hciuart7_config = -{ - .lower = - { - .rxattach = hciuart_rxattach, - .rxenable = hciuart_rxenable, - .setbaud = hciuart_setbaud, - .read = hciuart_read, - .write = hciuart_write, - .rxdrain = hciuart_rxdrain, - }, - .state = &g_hciuart7_state, - - .rxbuffer = g_uart7_rxbuffer, - .txbuffer = g_uart7_txbuffer, -# ifdef CONFIG_STM32_HCIUART7_RXDMA - .rxdmabuffer = g_uart7_rxdmabuffer, -# endif - .rxbufsize = CONFIG_STM32_HCIUART7_RXBUFSIZE, - .txbufsize = CONFIG_STM32_HCIUART7_TXBUFSIZE, -# ifdef CONFIG_STM32_HCIUART_SW_RXFLOW - .rxupper = RXFLOW_UPPER(CONFIG_STM32_HCIUART7_RXBUFSIZE), - .rxlower = RXFLOW_LOWER(CONFIG_STM32_HCIUART7_RXBUFSIZE), -# endif -# ifdef CONFIG_STM32_HCIUART_RXDMA - .rxdmachan = DMAMAP_UART7_RX, -# endif - - .irq = STM32_IRQ_UART7, - .baud = CONFIG_STM32_HCIUART7_BAUD, - .apbclock = STM32_PCLK1_FREQUENCY, - .usartbase = STM32_UART7_BASE, - .tx_gpio = GPIO_UART7_TX, - .rx_gpio = GPIO_UART7_RX, - .cts_gpio = GPIO_UART7_CTS, - .rts_gpio = GPIO_UART7_RTS, - .lock = SP_UNLOCKED -}; -#endif - -/* This describes the state of the STM32 UART8 port. */ - -#ifdef CONFIG_STM32_UART8_HCIUART -/* I/O buffers */ - -static uint8_t g_uart8_rxbuffer[CONFIG_STM32_HCIUART8_RXBUFSIZE]; -static uint8_t g_uart8_txbuffer[CONFIG_STM32_HCIUART8_TXBUFSIZE]; -# ifdef CONFIG_STM32_HCIUART8_RXDMA -static uint8_t g_uart8_rxdmabuffer[RXDMA_BUFFER_SIZE]; -# endif - -/* HCI UART8 variable state information */ - -static struct hciuart_state_s g_hciuart8_state = -{ - .rxwait = SEM_INITIALIZER(0), - .txwait = SEM_INITIALIZER(0), -}; - -/* HCI UART8 constant configuration information */ - -static const struct hciuart_config_s g_hciuart8_config = -{ - .lower = - { - .rxattach = hciuart_rxattach, - .rxenable = hciuart_rxenable, - .setbaud = hciuart_setbaud, - .read = hciuart_read, - .write = hciuart_write, - .rxdrain = hciuart_rxdrain, - }, - .state = &g_hciuart8_state, - - .rxbuffer = g_uart8_rxbuffer, - .txbuffer = g_uart8_txbuffer, -# ifdef CONFIG_STM32_HCIUART8_RXDMA - .rxdmabuffer = g_uart8_rxdmabuffer, -# endif - .rxbufsize = CONFIG_STM32_HCIUART8_RXBUFSIZE, - .txbufsize = CONFIG_STM32_HCIUART8_TXBUFSIZE, -# ifdef CONFIG_STM32_HCIUART_SW_RXFLOW - .rxupper = RXFLOW_UPPER(CONFIG_STM32_HCIUART8_RXBUFSIZE), - .rxlower = RXFLOW_LOWER(CONFIG_STM32_HCIUART8_RXBUFSIZE), -# endif -# ifdef CONFIG_STM32_HCIUART_RXDMA - .rxdmachan = DMAMAP_UART8_RX, -# endif - - .irq = STM32_IRQ_UART8, - .baud = CONFIG_STM32_HCIUART8_BAUD, - .apbclock = STM32_PCLK1_FREQUENCY, - .usartbase = STM32_UART8_BASE, - .tx_gpio = GPIO_UART8_TX, - .rx_gpio = GPIO_UART8_RX, - .cts_gpio = GPIO_UART8_CTS, - .rts_gpio = GPIO_UART8_RTS, - .lock = SP_UNLOCKED -}; -#endif - -/* This table lets us iterate over the configured USARTs */ - -static const struct hciuart_config_s * const g_hciuarts[STM32_NUSART] = -{ -#ifdef CONFIG_STM32_USART1_HCIUART - [0] = &g_hciusart1_config, -#endif -#ifdef CONFIG_STM32_USART2_HCIUART - [1] = &g_hciusart2_config, -#endif -#ifdef CONFIG_STM32_USART3_HCIUART - [2] = &g_hciusart3_config, -#endif -#ifdef CONFIG_STM32_USART6_HCIUART - [4] = &g_hciusart6_config, -#endif -#ifdef CONFIG_STM32_UART7_HCIUART - [5] = &g_hciuart7_config, -#endif -#ifdef CONFIG_STM32_UART8_HCIUART - [6] = &g_hciuart8_config, -#endif -}; - -#ifdef CONFIG_PM -static struct pm_callback_s g_serialcb = -{ - .notify = hciuart_pm_notify, - .prepare = hciuart_pm_prepare, -}; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: hciuart_getreg32 - ****************************************************************************/ - -static inline uint32_t - hciuart_getreg32(const struct hciuart_config_s *config, - unsigned int offset) -{ - return getreg32(config->usartbase + offset); -} - -/**************************************************************************** - * Name: hciuart_putreg32 - ****************************************************************************/ - -static inline void hciuart_putreg32(const struct hciuart_config_s *config, - unsigned int offset, uint32_t value) -{ - putreg32(value, config->usartbase + offset); -} - -/**************************************************************************** - * Name: hciuart_enableints - * - * Description: - * Enable interrupts as specified by bits in the 'intset' argument - * - * NOTE: This operation is not atomic. This function should be called - * only from within a critical section. - * - ****************************************************************************/ - -static void hciuart_enableints(const struct hciuart_config_s *config, - uint32_t intset) -{ - uint32_t cr1; - uint32_t cr2; - - /* And restore the interrupt state (see the interrupt enable/usage table - * above) - */ - - cr1 = hciuart_getreg32(config, STM32_USART_CR1_OFFSET); - cr1 |= (intset & USART_CR1_USED_INTS); - hciuart_putreg32(config, STM32_USART_CR1_OFFSET, cr1); - - cr2 = hciuart_getreg32(config, STM32_USART_CR3_OFFSET); - cr2 |= (intset & USART_CR3_EIE); - hciuart_putreg32(config, STM32_USART_CR3_OFFSET, cr2); - - wlinfo("CR1 %08" PRIx32 " CR2 %08" PRIx32 "\n", cr1, cr2); -} - -/**************************************************************************** - * Name: hciuart_disableints - * - * Description: - * Disable interrupts as specified by bits in the 'intset' argument - * - * NOTE: This operation is not atomic. This function should be called - * only from within a critical section. - * - ****************************************************************************/ - -static void hciuart_disableints(const struct hciuart_config_s *config, - uint32_t intset) -{ - uint32_t cr1; - uint32_t cr2; - - /* And restore the interrupt state (see the interrupt enable/usage table - * above) - */ - - cr1 = hciuart_getreg32(config, STM32_USART_CR1_OFFSET); - cr1 &= ~(intset & USART_CR1_USED_INTS); - hciuart_putreg32(config, STM32_USART_CR1_OFFSET, cr1); - - cr2 = hciuart_getreg32(config, STM32_USART_CR3_OFFSET); - cr2 &= ~(intset & USART_CR3_EIE); - hciuart_putreg32(config, STM32_USART_CR3_OFFSET, cr2); - - wlinfo("CR1 %08" PRIx32 " CR2 %08" PRIx32 "\n", cr1, cr2); -} - -/**************************************************************************** - * Name: hciuart_isenabled - * - * Description: - * Return true if any any of the interrupts specified in the 'intset' - * argument are enabled. - * - ****************************************************************************/ - -static bool hciuart_isenabled(const struct hciuart_config_s *config, - uint32_t intset) -{ - uint32_t regval; - - /* And restore the interrupt state (see the interrupt enable/usage table - * above) - */ - - regval = hciuart_getreg32(config, STM32_USART_CR1_OFFSET); - regval &= USART_CR1_USED_INTS; - if ((regval & intset) != 0) - { - return true; - } - - regval = hciuart_getreg32(config, STM32_USART_CR3_OFFSET); - regval &= USART_CR3_EIE; - if ((regval & intset) != 0) - { - return true; - } - - return false; -} - -/**************************************************************************** - * Name: hciuart_rxenabled - * - * Description: - * Check if Rx interrupts are enabled. - * - ****************************************************************************/ - -static inline bool hciuart_rxenabled(const struct hciuart_config_s *config) -{ -#ifdef CONFIG_STM32_HCIUART_RXDMA - const struct hciuart_config_s *state = config->state; - - if (config->rxdmabuffer != NULL) - { - return state->rxenabled; - } - else -#endif - { - return hciuart_isenabled(config, USART_CR1_RXNEIE); - } -} - -/**************************************************************************** - * Name: hciuart_dma_nextrx - * - * Description: - * Returns the index into the RX FIFO where the DMA will place the next - * byte that it receives. - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_HCIUART_RXDMA -static int hciuart_dma_nextrx(const struct hciuart_config_s *config) -{ - struct hciuart_state_s *state = config->state; - size_t dmaresidual; - - dmaresidual = stm32_dmaresidual(state->rxdmastream); - - return (RXDMA_BUFFER_SIZE - (int)dmaresidual); -} -#endif - -/**************************************************************************** - * Name: hciuart_rxinuse - * - * Description: - * Return the number of bytes in the Rx buffer - * - * Example: rxbufsize=4, rxhead = 0, rxtail = 2 - * - * +---+---+---+---+ - * | X | X | | | X = inuse - * +---+---+---+---+ - * | `- rxtail = 2 - * `- rxhead = 0 - * - * inuse = 2 - 0 = 2 - * - * Example: rxbufsize=4, rxhead = 2, rxtail = 0 - * - * +---+---+---+---+ - * | | | X | X | X = inuse - * +---+---+---+---+ - * | `- rxhead = 2 - * `- rxtail = 0 - * - * inuse = (0 + 4) - 2 = 2 - * - ****************************************************************************/ - -static uint16_t hciuart_rxinuse(const struct hciuart_config_s *config) -{ - struct hciuart_state_s *state; - size_t inuse; - - DEBUGASSERT(config != NULL && config->state != NULL); - state = config->state; - - /* Keep track of how much is discarded */ - - if (state->rxtail >= state->rxhead) - { - inuse = state->rxtail - state->rxhead; - } - else - { - inuse = (state->rxtail + config->rxbufsize) - state->rxhead; - } - - wlinfo("inuse %lu\n", (unsigned long)inuse); - return inuse; -} - -/**************************************************************************** - * Name: hciuart_rxflow_enable - * - * Description: - * Enable software Rx flow control, i.e., deassert the RTS output. This - * will be seen as CTS on the other end of the cable and the HCI UART - * device must stop sending data. - * - * NOTE: RTS is logic low - * - ****************************************************************************/ - -static void hciuart_rxflow_enable(const struct hciuart_config_s *config) -{ -#ifdef CONFIG_STM32_HCIUART_SW_RXFLOW - struct hciuart_state_s *state; - - DEBUGASSERT(config != NULL && config->state != NULL); - state = config->state; - - /* Is Rx flow control already enable? */ - - if (!state->rxflow) - { - uint16_t inused = hciuart_rxinuse(config); - - if (inused >= config->rxupper) - { - wlinfo("Enable RTS flow control\n"); - - stm32_gpiowrite(config->rts_gpio, true); - state->rxflow = true; - } - } -#endif -} - -/**************************************************************************** - * Name: hciuart_rxflow_disable - * - * Description: - * Disable software Rx flow control, i.e., assert the RTS output. This - * will be seen as CTS on the other end of the cable and the HCI UART - * device can resume sending data. - * - * NOTE: RTS is logic low - * - ****************************************************************************/ - -static void hciuart_rxflow_disable(const struct hciuart_config_s *config) -{ -#ifdef CONFIG_STM32_HCIUART_SW_RXFLOW - struct hciuart_state_s *state; - - DEBUGASSERT(config != NULL && config->state != NULL); - state = config->state; - - if (state->rxflow) - { - uint16_t inused = hciuart_rxinuse(config); - - if (inused <= config->rxlower) - { - wlinfo("Disable RTS flow control\n"); - - stm32_gpiowrite(config->rts_gpio, false); - state->rxflow = false; - } - } -#endif -} - -/**************************************************************************** - * Name: hciuart_copytorxbuffer - * - * Description: - * Copy data to the driver Rx buffer. The source is either the U[S]ART - * Rx FIFO or the Rx DMA buffer, depending upon the configuration. - * - ****************************************************************************/ - -static ssize_t hciuart_copytorxbuffer(const struct hciuart_config_s *config) -{ - struct hciuart_state_s *state; - ssize_t nbytes = 0; - uint16_t rxhead; - uint16_t rxtail; - uint16_t rxnext; -#ifdef CONFIG_STM32_HCIUART_RXDMA - uint16_t dmatail; -#endif - uint8_t rxbyte; - - /* Get a copy of the rxhead and rxtail indices of the Rx buffer */ - - state = config->state; - rxhead = state->rxhead; - rxtail = state->rxtail; - -#ifdef CONFIG_STM32_HCIUART_RXDMA - if (config->rxdmabuffer != NULL) - { - /* Get a copy of the dmatail index of the Rx DMA buffer */ - - dmatail = state->dmatail; - - /* Compare dmatail to the current DMA pointer, if they do notmatch, - * then there is new Rx data available in the Rx DMA buffer. - */ - - while ((hciuart_dma_nextrx(config) != dmatail)) - { - /* Compare the Rx buffer head and tail indices. If the - * incremented tail index would make the Rx buffer appear empty, - * then we must stop the copy. If there is data pending in the Rx - * DMA buffer, this could be very bad because a data overrun - * condition is likely to occur. - */ - - rxnext = rxtail + 1; - if (rxnext >= config->rxbufsize) - { - rxnext = 0 - } - - /* Would this make the Rx buffer appear full? */ - - if (rxnext == rxhead) - { - /* Yes, stop the copy and update the indices */ - - break; - } - - /* Get a byte from the Rx DMA buffer */ - - rxbyte = config->rxdmabuffer[dmatail]; - - if (++dmatail >= RXDMA_BUFFER_SIZE) - { - dmatail = 0; - } - - /* And add it to the tail of the Rx buffer */ - - config->rxbuffer[rxtail] = rxbyte; - rxtail = rxnext; - nbytes++; - } - - state->dmatail = dmatail; - } - else -#endif - { - /* Is there data available in the Rx FIFO? */ - - while ((hciuart_getreg32(config, STM32_USART_SR_OFFSET) & - USART_SR_RXNE) != 0) - { - /* Compare the Rx buffer head and tail indices. If the - * incremented tail index would make the Rx buffer appear empty, - * then we must stop the copy. If there is data pending in the Rx - * FIFO, this could be very bad because a data overrun condition - * is likely to* occur. - */ - - rxnext = rxtail + 1; - if (rxnext >= config->rxbufsize) - { - rxnext = 0; - } - - /* Would this make the Rx buffer appear full? */ - - if (rxnext == rxhead) - { - /* Yes, stop the copy and update the indices */ - - break; - } - - /* Get a byte from the Rx FIFO buffer */ - - rxbyte = hciuart_getreg32(config, STM32_USART_RDR_OFFSET) & 0xff; - - /* And add it to the tail of the Rx buffer */ - - config->rxbuffer[rxtail] = rxbyte; - rxtail = rxnext; - nbytes++; - } - } - - /* Save the updated Rx buffer tail index */ - - state->rxtail = rxtail; - - /* Check if we need to enable Rx flow control */ - - hciuart_rxflow_enable(config); - - /* Notify any waiting threads that new Rx data is available */ - - if (nbytes > 0 && state->rxwaiting) - { - state->rxwaiting = false; - nxsem_post(&state->rxwait); - } - - wlinfo("rxhead %u rxtail %u nbytes %ld\n", rxhead, rxtail, (long)nbytes); - return nbytes; -} - -/**************************************************************************** - * Name: hciuart_copyfromrxbuffer - * - * Description: - * Copy data from the driver Rx buffer to the caller provided destination - * buffer. - * - ****************************************************************************/ - -static ssize_t - hciuart_copyfromrxbuffer(const struct hciuart_config_s *config, - uint8_t *dest, size_t destlen) -{ - struct hciuart_state_s *state; - ssize_t nbytes; - uint16_t rxhead; - uint16_t rxtail; - uint8_t rxbyte; - - /* Get a copy of the rxhead and rxtail indices of the Rx buffer */ - - state = config->state; - rxhead = state->rxhead; - rxtail = state->rxtail; - nbytes = 0; - - /* Is there data available in the Rx buffer? Is there space in the user - * buffer? - */ - - while (rxhead != rxtail && nbytes < destlen) - { - /* Get a byte from the head of the Rx buffer */ - - rxbyte = config->rxbuffer[rxhead]; - - /* And add it to the caller's buffer buffer */ - - dest[nbytes] = rxbyte; - - /* Update indices and counts */ - - nbytes++; - - if (++rxhead >= config->rxbufsize) - { - rxhead = 0; - } - - /* Check if we need to disable Rx flow control */ - - hciuart_rxflow_disable(config); - } - - /* Save the updated Rx buffer head index */ - - state->rxhead = rxhead; - - wlinfo("rxhead %u rxtail %u nbytes %ld\n", rxhead, rxtail, (long)nbytes); - return nbytes; -} - -/**************************************************************************** - * Name: hciuart_copytotxfifo - * - * Description: - * Copy data from the Tx buffer to the Tx FIFO - * - ****************************************************************************/ - -static ssize_t hciuart_copytotxfifo(const struct hciuart_config_s *config) -{ - struct hciuart_state_s *state; - ssize_t nbytes; - uint16_t txhead; - uint16_t txtail; - uint8_t txbyte; - - /* Get a copy of the txhead and txtail indices of the Rx buffer */ - - state = config->state; - txhead = state->txhead; - txtail = state->txtail; - nbytes = 0; - - /* Compare the Tx buffer head and tail indices. If the Tx buffer is - * empty, then we finished with the copy. - */ - - while (txhead != txtail) - { - /* Is the transmit data register empty? - * - * TXE: Transmit data register empty - * This bit is set by hardware when the content of the TDR register - * has been transferred into the shift register. - */ - - if ((hciuart_getreg32(config, STM32_USART_SR_OFFSET) & - USART_SR_TXE) == 0) - { - break; - } - - /* Get a byte from the head of the Tx buffer */ - - txbyte = config->txbuffer[txhead]; - if (++txhead >= config->txbufsize) - { - txhead = 0; - } - - /* And add it to the of the Tx FIFO */ - - hciuart_putreg32(config, STM32_USART_TDR_OFFSET, (uint32_t)txbyte); - nbytes++; - } - - wlinfo("txhead %u txtail %u nbytes %ld\n", txhead, txtail, (long)nbytes); - state->txhead = txhead; - return nbytes; -} - -/**************************************************************************** - * Name: hciuart_line_configure - * - * Description: - * Set the serial line format and speed. - * - * Per "Specification of the Bluetooth System, Wireless connections made - * easy, Host Controller Interface [Transport Layer]", Volume 4, Revision - * 1.2 or later, 1 January 2006, HCI UART transport uses these settings: - * - * 8 data bits, no parity, 1 stop, RTS/CTS flow control - * - * BAUD and flow control response time are manufacturer specific. - * - ****************************************************************************/ - -static void hciuart_line_configure(const struct hciuart_config_s *config) -{ -#if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) || \ - defined(CONFIG_STM32_STM32F37XX) - uint32_t usartdiv8; -#else - uint32_t usartdiv32; - uint32_t mantissa; - uint32_t fraction; -#endif - uint32_t baud; - uint32_t regval; - uint32_t brr; - - /* The current BAUD selection is part of the variable state data */ - - DEBUGASSERT(config != NULL && config->state != NULL); - baud = config->state->baud; - - wlinfo("baud %lu\n", (unsigned long)baud); - - /* Load CR1 */ - - regval = hciuart_getreg32(config, STM32_USART_CR1_OFFSET); - -#if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX)|| \ - defined(CONFIG_STM32_STM32F37XX) - /* This first implementation is for U[S]ARTs that support oversampling - * by 8 in additional to the standard oversampling by 16. - * With baud rate of fCK / Divider for oversampling by 16. - * and baud rate of 2 * fCK / Divider for oversampling by 8 - * - * In case of oversampling by 8, the equation is: - * - * baud = 2 * fCK / usartdiv8 - * usartdiv8 = 2 * fCK / baud - */ - - usartdiv8 = ((config->apbclock << 1) + (baud >> 1)) / baud; - - /* Baud rate for standard USART (SPI mode included): - * - * In case of oversampling by 16, the equation is: - * baud = fCK / usartdiv16 - * usartdiv16 = fCK / baud - * = 2 * usartdiv8 - * - * Use oversamply by 8 only if the divisor is small. But what is small? - */ - - if (usartdiv8 > 100) - { - /* Use usartdiv16 */ - - brr = (usartdiv8 + 1) >> 1; - - /* Clear oversampling by 8 to enable oversampling by 16 */ - - regval &= ~USART_CR1_OVER8; - } - else - { - DEBUGASSERT(usartdiv8 >= 8); - - /* Perform mysterious operations on bits 0-3 */ - - brr = ((usartdiv8 & 0xfff0) | ((usartdiv8 & 0x000f) >> 1)); - - /* Set oversampling by 8 */ - - regval |= USART_CR1_OVER8; - } - -#else - /* This second implementation is for U[S]ARTs that support fractional - * dividers. - * - * Configure the USART Baud Rate. The baud rate for the receiver and - * transmitter (Rx and Tx) are both set to the same value as programmed - * in the Mantissa and Fraction values of USARTDIV. - * - * baud = fCK / (16 * usartdiv) - * usartdiv = fCK / (16 * baud) - * - * Where fCK is the input clock to the peripheral (PCLK1 for USART2, 3, - * 4, 5 or PCLK2 for USART1) - * - * First calculate (NOTE: all stand baud values are even so dividing by - * two does not lose precision): - * - * usartdiv32 = 32 * usartdiv = fCK / (baud/2) - */ - - usartdiv32 = config->apbclock / (baud >> 1); - - /* The mantissa part is then */ - - mantissa = usartdiv32 >> 5; - - /* The fractional remainder (with rounding) */ - - fraction = (usartdiv32 - (mantissa << 5) + 1) >> 1; - -#if defined(CONFIG_STM32_STM32F4XXX) - /* The F4 supports 8 X in oversampling additional to the - * standard oversampling by 16. - * - * With baud rate of fCK / (16 * Divider) for oversampling by 16. - * and baud rate of fCK / (8 * Divider) for oversampling by 8 - */ - - /* Check if 8x oversampling is necessary */ - - if (mantissa == 0) - { - regval |= USART_CR1_OVER8; - - /* Rescale the mantissa */ - - mantissa = usartdiv32 >> 4; - - /* The fractional remainder (with rounding) */ - - fraction = (usartdiv32 - (mantissa << 4) + 1) >> 1; - } - else - { - /* Use 16x Oversampling */ - - regval &= ~USART_CR1_OVER8; - } -#endif - - brr = mantissa << USART_BRR_MANT_SHIFT; - brr |= fraction << USART_BRR_FRAC_SHIFT; -#endif - - hciuart_putreg32(config, STM32_USART_CR1_OFFSET, regval); - hciuart_putreg32(config, STM32_USART_BRR_OFFSET, brr); - - /* Configure parity mode and word length - * - * HCI UART spec requires: 8 data bits, No parity - */ - - regval &= ~(USART_CR1_PCE | USART_CR1_PS | USART_CR1_M); - hciuart_putreg32(config, STM32_USART_CR1_OFFSET, regval); - - /* Configure STOP bits - * - * HCI UART spec requires: 1 stop bit - */ - - regval = hciuart_getreg32(config, STM32_USART_CR2_OFFSET); - regval &= ~(USART_CR2_STOP_MASK); - hciuart_putreg32(config, STM32_USART_CR2_OFFSET, regval); - - /* Configure hardware flow control */ - - regval = hciuart_getreg32(config, STM32_USART_CR3_OFFSET); - regval &= ~(USART_CR3_CTSE | USART_CR3_RTSE); - - /* Use software controlled RTS flow control. Because STM current STM32 - * have broken HW based RTS behavior (they assert nRTS after every byte - * received) Enable this setting workaround this issue by using software - * based management of RTS. - */ - -#ifndef CONFIG_STM32_HCIUART_SW_RXFLOW - regval |= USART_CR3_RTSE; -#endif - regval |= USART_CR3_CTSE; - - hciuart_putreg32(config, STM32_USART_CR3_OFFSET, regval); -} - -/**************************************************************************** - * Name: hciuart_apbclock_enable - * - * Description: - * Enable or disable APB clock for the USART peripheral - * - * Input Parameters: - * lower - A reference to the UART driver state structure - * on - Enable clock if 'on' is 'true' and disable if 'false' - * - ****************************************************************************/ - -static void hciuart_apbclock_enable(const struct hciuart_config_s *config) -{ - uint32_t rcc_en; - uint32_t regaddr; - - /* Determine which USART to configure */ - - switch (config->usartbase) - { -#ifdef CONFIG_STM32_USART1_HCIUART - case STM32_USART1_BASE: - rcc_en = RCC_APB2ENR_USART1EN; - regaddr = STM32_RCC_APB2ENR; - break; -#endif - -#ifdef CONFIG_STM32_USART2_HCIUART - case STM32_USART2_BASE: - rcc_en = RCC_APB1ENR_USART2EN; - regaddr = STM32_RCC_APB1ENR; - break; -#endif - -#ifdef CONFIG_STM32_USART3_HCIUART - case STM32_USART3_BASE: - rcc_en = RCC_APB1ENR_USART3EN; - regaddr = STM32_RCC_APB1ENR; - break; -#endif - -#ifdef CONFIG_STM32_USART6_HCIUART - case STM32_USART6_BASE: - rcc_en = RCC_APB2ENR_USART6EN; - regaddr = STM32_RCC_APB2ENR; - break; -#endif - -#ifdef CONFIG_STM32_UART7_HCIUART - case STM32_UART7_BASE: - rcc_en = RCC_APB1ENR_UART7EN; - regaddr = STM32_RCC_APB1ENR; - break; -#endif - -#ifdef CONFIG_STM32_UART8_HCIUART - case STM32_UART8_BASE: - rcc_en = RCC_APB1ENR_UART8EN; - regaddr = STM32_RCC_APB1ENR; - break; -#endif - - default: - return; - } - - /* Enable/disable APB 1/2 clock for USART */ - - modifyreg32(regaddr, 0, rcc_en); -} - -/**************************************************************************** - * Name: hciuart_configure - * - * Description: - * Configure the USART clocking, GPIO pins, baud, bits, parity, etc. - * - * Per "Specification of the Bluetooth System, Wireless connections made - * easy, Host Controller Interface [Transport Layer]", Volume 4, Revision - * 1.2 or later, 1 January 2006, HCI UART transport uses these settings: - * - * 8 data bits, no parity, 1 stop, RTS/CTS flow control - * - * BAUD and flow control response time are manufacturer specific. - * - ****************************************************************************/ - -static int hciuart_configure(const struct hciuart_config_s *config) -{ - uint32_t regval; - uint32_t pinset; - - /* Note: The logic here depends on the fact that that the USART module - * was enabled in stm32_lowsetup(). - */ - - wlinfo("config %p\n", config); - - /* Enable USART APB1/2 clock */ - - hciuart_apbclock_enable(config); - - /* Configure pins for USART use */ - - stm32_configgpio(config->tx_gpio); - stm32_configgpio(config->rx_gpio); - stm32_configgpio(config->cts_gpio); - - pinset = config->rts_gpio; - -#ifdef CONFIG_STM32_HCIUART_SW_RXFLOW - /* Use software controlled RTS flow control. Because STM current STM32 - * have broken HW based RTS behavior (they assert nRTS after every byte - * received) Enable this setting workaround this issue by using software - * based management of RTS. - * - * Convert the RTS alternate function pin to a push-pull output with - * initial output value of one, i.e., rx flow control enabled. The HCI - * UART device should not send data until we assert RTS. - */ - - regval = GPIO_MODE_MASK | GPIO_PUPD_MASK | GPIO_OPENDRAIN | GPIO_EXTI; - pinset = (config->rts_gpio & ~regval) | GPIO_OUTPUT | GPIO_OUTPUT_SET; -#endif - stm32_configgpio(pinset); - - /* Configure CR2 */ - - /* Clear STOP, CLKEN, CPOL, CPHA, LBCL, and interrupt enable bits */ - - /* HCI UART spec: 1 stop bit */ - - regval = hciuart_getreg32(config, STM32_USART_CR2_OFFSET); - regval &= ~(USART_CR2_STOP_MASK | USART_CR2_CLKEN | USART_CR2_CPOL | - USART_CR2_CPHA | USART_CR2_LBCL | USART_CR2_LBDIE); - hciuart_putreg32(config, STM32_USART_CR2_OFFSET, regval); - - /* Configure CR1 */ - - /* Clear TE, REm and all interrupt enable bits */ - - regval = hciuart_getreg32(config, STM32_USART_CR1_OFFSET); - regval &= ~(USART_CR1_TE | USART_CR1_RE | USART_CR1_ALLINTS); - - hciuart_putreg32(config, STM32_USART_CR1_OFFSET, regval); - - /* Configure CR3 */ - - /* Clear CTSE, RTSE, and all interrupt enable bits */ - - regval = hciuart_getreg32(config, STM32_USART_CR3_OFFSET); - regval &= ~(USART_CR3_CTSIE | USART_CR3_CTSE | USART_CR3_RTSE | - USART_CR3_EIE); - - hciuart_putreg32(config, STM32_USART_CR3_OFFSET, regval); - - /* Configure the USART line format and speed. Start with the configured - * initial BAUD. - */ - - DEBUGASSERT(config->state != NULL); - config->state->baud = config->baud; - hciuart_line_configure(config); - - /* Enable Rx, Tx, and the USART */ - - regval = hciuart_getreg32(config, STM32_USART_CR1_OFFSET); - regval |= (USART_CR1_UE | USART_CR1_TE | USART_CR1_RE); - hciuart_putreg32(config, STM32_USART_CR1_OFFSET, regval); - -#ifdef CONFIG_STM32_HCIUART_RXDMA - /* Acquire the DMA channel. This should always succeed. */ - - state->rxdmastream = stm32_dmachannel(config->rxdmachan); - - /* Configure for circular DMA reception into the RX fifo */ - - stm32_dmasetup(state->rxdmastream, - config->usartbase + STM32_USART_RDR_OFFSET, - (uint32_t)config->rxdmabuffer, - RXDMA_BUFFER_SIZE, - SERIAL_DMA_CONTROL_WORD); - - /* Reset our DMA shadow pointer to match the address just - * programmed above. - */ - - state->dmatail = 0; - - /* Enable receive DMA for the UART */ - - regval = hciuart_getreg32(config, STM32_USART_CR3_OFFSET); - regval |= USART_CR3_DMAR; - hciuart_putreg32(config, STM32_USART_CR3_OFFSET, regval); - - /* Start the DMA channel, and arrange for callbacks at the half and - * full points in the FIFO. This ensures that we have half a FIFO - * worth of time to claim bytes before they are overwritten. - */ - - stm32_dmastart(state->rxdmastream, hciuart_dma_rxcallback, - (void *)config, true); -#endif - - /* Disable Rx flow control, i.e, assert RTS. */ - - hciuart_rxflow_disable(config); - return OK; -} - -/**************************************************************************** - * Name: hciuart_interrupt - * - * Description: - * This is the HCIUART interrupt handler. It will be invoked when an - * interrupt is received on the 'irq'. It should call - * hciuart_copytotxfifo or hciuart_copytorxbuffer to perform the - * appropriate data transfers. The interrupt handling logic must be able - * to map the 'arg' to the appropriate hciuart_lowerhalf_s structure in - * order to call these functions. - * - ****************************************************************************/ - -static int hciuart_interrupt(int irq, void *context, void *arg) -{ - const struct hciuart_config_s *config = - (const struct hciuart_config_s *)arg; - struct hciuart_state_s *state; - uint32_t status; - uint8_t handled; - int passes; - - DEBUGASSERT(config != NULL && config->state != NULL); - state = config->state; - - /* Report serial activity to the power management logic */ - -#if defined(CONFIG_PM) && CONFIG_STM32_PM_SERIAL_ACTIVITY > 0 - pm_activity(PM_IDLE_DOMAIN, CONFIG_STM32_PM_SERIAL_ACTIVITY); -#endif - - /* Loop until there are no characters to be transferred or, - * until we have been looping for a long time. - */ - - handled = (HCIUART_RXHANDLED | HCIUART_TXHANDLED); - for (passes = 0; passes < 256 && handled != 0; passes++) - { - handled = 0; - - /* Get the masked USART status word. */ - - status = hciuart_getreg32(config, STM32_USART_SR_OFFSET); - wlinfo("status %08" PRIx32 "\n", status); - - /* USART interrupts: - * - * Enable Status Meaning Usage - * ---------------- ------------- ----------------------- ---------- - * USART_CR1_IDLEIE USART_SR_IDLE Idle Line Detected (not used) - * USART_CR1_RXNEIE USART_SR_RXNE Received Data Ready to - * be Read - * " " USART_SR_ORE Overrun Error Detected - * USART_CR1_TCIE USART_SR_TC Transmission Complete (only for - * RS-485) - * USART_CR1_TXEIE USART_SR_TXE Transmit Data Register - * Empty - * USART_CR1_PEIE USART_SR_PE Parity Error (No parity) - * - * USART_CR2_LBDIE USART_SR_LBD Break Flag (not used) - * USART_CR3_EIE USART_SR_FE Framing Error - * " " USART_SR_NE Noise Error - * " " USART_SR_ORE Overrun Error Detected - * USART_CR3_CTSIE USART_SR_CTS CTS flag (not used) - * - * NOTE: Some of these status bits must be cleared by explicitly - * writing zero to the SR register: USART_SR_CTS, USART_SR_LBD. Note - * of those are currently being used. - */ - - /* Handle incoming, receive bytes (non-DMA only) */ - - if ((status & USART_SR_RXNE) != 0 && hciuart_rxenabled(config)) - { - ssize_t nbytes; - - /* Received data ready... copy data from the Rx FIFO to the Rx - * buffer. - */ - - nbytes = hciuart_copytorxbuffer(config); - UNUSED(nbytes); - - /* Is there anything in the Rx buffer? Has the user registered an - * Rx callback function? - */ - - if (state->rxhead != state->rxtail && state->callback != NULL) - { - state->callback(&config->lower, state->arg); - handled = HCIUART_RXHANDLED; - } - } - - /* We may still have to read from the DR register to clear any pending - * error conditions. - */ - - else if ((status & (USART_SR_ORE | USART_SR_NE | USART_SR_FE)) != 0) - { -#if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) || \ - defined(CONFIG_STM32_STM32F37XX) - /* These errors are cleared by writing the corresponding bit to the - * interrupt clear register (ICR). - */ - - hciuart_putreg32(config, STM32_USART_ICR_OFFSET, - (USART_ICR_NCF | USART_ICR_ORECF | USART_ICR_FECF)); -#else - /* If an error occurs, read from DR to clear the error (data has - * been lost). If ORE is set along with RXNE then it tells you - * that the byte *after* the one in the data register has been - * lost, but the data register value is correct. That case will - * be handled above if interrupts are enabled. Otherwise, that - * good byte will be lost. - */ - - hciuart_getreg32(config, STM32_USART_RDR_OFFSET); -#endif - } - - /* Handle outgoing, transmit bytes - * - * TXE: Transmit data register empty - * This bit is set by hardware when the content of the TDR register - * has been transferred into the shift register. - */ - - if ((status & USART_SR_TXE) != 0 && - hciuart_isenabled(config, USART_CR1_TXEIE)) - { - ssize_t nbytes; - uint8_t txhandled; - - /* Transmit data register empty ... copy data from the Tx buffer - * to the Tx FIFO. - */ - - nbytes = hciuart_copytotxfifo(config); - UNUSED(nbytes); - - /* If the Tx buffer is now empty, then disable further Tx - * interrupts. Tx interrupts will only be enabled in the - * following circumstances: - * - * 1. The user is waiting in hciuart_write() for space to become - * available in the Tx FIFO. - * 2. The full, outgoing message has been placed into the Tx - * buffer by hciuart_write(). - * - * In either case, no more Tx interrupts will be needed until more - * data is added to the Tx buffer. - */ - - txhandled = HCIUART_TXHANDLED; - if (state->txhead == state->txtail) - { - /* Disable Tx interrupts and treat the event as unhandled in - * order to terminate looping. - */ - - hciuart_disableints(config, USART_CR1_TXEIE); - txhandled = 0; - } - - /* This copy will free up space in the Tx FIFO. Wake up any - * threads that may have been waiting for space in the Tx - * buffer. - */ - - if (state->txwaiting) - { - state->txwaiting = false; - nxsem_post(&state->txwait); - } - - handled |= txhandled; - } - } - - return OK; -} - -/**************************************************************************** - * Name: hciuart_rxattach - * - * Description: - * Attach/detach the upper half Rx callback. - * - * rxattach() allows the upper half logic to attach a callback function - * that will be used to inform the upper half that an Rx frame is - * available. This callback will, most likely, be invoked in the - * context of an interrupt callback. The receive() method should then - * be invoked in order to receive the obtain the Rx frame data. - * - ****************************************************************************/ - -static void hciuart_rxattach(const struct btuart_lowerhalf_s *lower, - btuart_rxcallback_t callback, void *arg) -{ - const struct hciuart_config_s *config = - (const struct hciuart_config_s *)lower; - struct hciuart_state_s *state; - irqstate_t flags; - - wlinfo("config %p callback %p arg %p\n", config, callback, arg); - - DEBUGASSERT(config != NULL && config->state != NULL); - state = config->state; - - /* If the callback is NULL, then we are detaching */ - - flags = spin_lock_irqsave(&config->lock); - if (callback == NULL) - { - uint32_t intset; - - /* Disable Rx callbacks and detach the Rx callback */ - - intset = USART_CR1_RXNEIE | USART_CR3_EIE; - hciuart_disableints(config, intset); - - state->callback = NULL; - state->arg = NULL; - } - - /* Otherwise, we are attaching */ - - else - { - state->callback = NULL; - state->arg = arg; - state->callback = callback; - } - - spin_unlock_irqrestore(&config->lock, flags); -} - -/**************************************************************************** - * Name: hciuart_rxenable - * - * Description: - * Enable/disable RX callbacks from the HCI UART. - * - * hciuart_rxenable() may be used to enable or disable callback events. - * This probably translates to enabling and disabled Rx interrupts at - * the UART. NOTE: Rx event notification should be done sparingly: - * Rx data overrun may occur when Rx events are disabled! - * - ****************************************************************************/ - -static void hciuart_rxenable(const struct btuart_lowerhalf_s *lower, - bool enable) -{ - const struct hciuart_config_s *config = - (const struct hciuart_config_s *)lower; - - DEBUGASSERT(config != NULL && config->state != NULL); - -#ifdef CONFIG_STM32_HCIUART_RXDMA - struct hciuart_state_s *state = config->state; - - if (config->rxdmabuffer != NULL) - { - wlinfo("config %p enable %u (DMA)\n", config, enable); - - /* En/disable DMA reception. - * - * Note that it is not safe to check for available bytes and - * immediately pass them to uart_recvchars as that could potentially - * recurse back to us again. Instead, bytes must wait until the next - * up_dma_poll or DMA event. - */ - - state->rxenable = enable; - } - else -#else - { - uint32_t intset; - irqstate_t flags; - - wlinfo("config %p enable %u (non-DMA)\n", config, enable); - - /* USART receive interrupts: - * - * Enable Status Meaning Usage - * ---------------- ------------- ----------------------- ---------- - * USART_CR1_IDLEIE USART_SR_IDLE Idle Line Detected (not used) - * USART_CR1_RXNEIE USART_SR_RXNE Received Data Ready to - * be Read - * " " USART_SR_ORE Overrun Error Detected - * USART_CR1_PEIE USART_SR_PE Parity Error (No parity) - * - * USART_CR2_LBDIE USART_SR_LBD Break Flag (not used) - * USART_CR3_EIE USART_SR_FE Framing Error - * " " USART_SR_NE Noise Error - * " " USART_SR_ORE Overrun Error Detected - */ - - flags = spin_lock_irqsave(&config->lock); - if (enable) - { - /* Receive an interrupt when their is anything in the Rx data - * register (or an Rx timeout occurs). - */ - - intset = USART_CR1_RXNEIE | USART_CR3_EIE; - hciuart_enableints(config, intset); - } - else - { - intset = USART_CR1_RXNEIE | USART_CR3_EIE; - hciuart_disableints(config, intset); - } - - spin_unlock_irqrestore(&config->lock, flags); - } -#endif -} - -/**************************************************************************** - * Name: hciuart_setbaud - * - * Description: - * The HCI UART comes up with some initial BAUD rate. Some support - * auto-BAUD detection, some support writing a configuration file to - * select the initial BAUD. The simplest strategy, however, is simply - * to use the HCI UART's default initial BAUD to perform the basic - * bring up, then send a vendor-specific command to increase the HCI - * UARTs BAUD. This method then may be used to adjust the lower half - * driver to the new HCI UART BAUD. - * - ****************************************************************************/ - -static int hciuart_setbaud(const struct btuart_lowerhalf_s *lower, - uint32_t baud) -{ - const struct hciuart_config_s *config = - (const struct hciuart_config_s *)lower; - - DEBUGASSERT(config != NULL && config->state != NULL); - - config->state->baud = baud; - hciuart_line_configure(config); - return OK; -} - -/**************************************************************************** - * Name: hciuart_read - * - * Description: - * Read UART data. - * - * hciuart_read() after receipt of a callback notifying the upper half of - * the availability of Rx frame, the upper half may call the receive() - * method in order to obtain the buffered Rx frame data. - * - ****************************************************************************/ - -static ssize_t hciuart_read(const struct btuart_lowerhalf_s *lower, - void *buffer, size_t buflen) -{ - const struct hciuart_config_s *config = - (const struct hciuart_config_s *)lower; - struct hciuart_state_s *state; - uint8_t *dest; - size_t remaining; - ssize_t ntotal; - ssize_t nbytes; - bool rxenable; - int ret; - - wlinfo("config %p buffer %p buflen %lu\n", - config, buffer, (unsigned long)buflen); - - /* NOTE: This assumes that the caller has exclusive access to the Rx - * buffer, i.e., one lower half instance can server only one upper half! - */ - - DEBUGASSERT(config != NULL && config->state != NULL); - state = config->state; - - /* Read any pending data to the Rx buffer */ - - nbytes = hciuart_copytorxbuffer(config); - UNUSED(nbytes); - - /* Loop copying data to the user buffer while the Rx buffer is not empty - * and the callers buffer is not full. - */ - - dest = (uint8_t *)buffer; - remaining = buflen; - ntotal = 0; - - rxenable = hciuart_rxenabled(config); - hciuart_rxenable(lower, false); - - while (state->rxtail != state->rxhead && ntotal < buflen) - { - nbytes = hciuart_copyfromrxbuffer(config, dest, remaining); - if (nbytes <= 0) - { - DEBUGASSERT(nbytes == 0); - - /* If no data has been received, then we must wait for the arrival - * of new Rx data and try again. - */ - - if (ntotal == 0) - { - DEBUGASSERT(!state->rxwaiting); - state->rxwaiting = true; - do - { - ret = nxsem_wait_uninterruptible(&state->rxwait); - if (ret < 0) - { - ntotal = (ssize_t)ret; - break; - } - } - while (state->rxwaiting); - } - - /* Otherwise, this must be the end of the packet. Just break out - * and return what we have. - */ - - else - { - break; - } - } - else - { - /* More data has been copied. Update pointers, counts, and - * indices. - */ - - ntotal += nbytes; - dest += nbytes; - remaining -= nbytes; - - /* Read any additional pending data into the Rx buffer that may - * have accumulated while we were copying. - */ - - nbytes = hciuart_copytorxbuffer(config); - if (nbytes < 0) - { - /* An error occurred.. this should not really happen */ - - return nbytes; - } - - /* Otherwise, continue looping */ - } - } - - hciuart_rxenable(lower, rxenable); - return ntotal; -} - -/**************************************************************************** - * Name: hciuart_write - * - * Description: - * Write UART data. - * - * hciuart_write() will add the outgoing frame to the Tx buffer and will - * return immediately. This function may block only in the event that - * there is insufficient buffer space to hold the Tx frame data. In that - * case the lower half will block until there is sufficient to buffer - * the entire outgoing packet. - * - ****************************************************************************/ - -static ssize_t hciuart_write(const struct btuart_lowerhalf_s *lower, - const void *buffer, size_t buflen) -{ - const struct hciuart_config_s *config = - (const struct hciuart_config_s *)lower; - struct hciuart_state_s *state; - const uint8_t *src; - ssize_t nbytes = 0; - uint16_t txhead; - uint16_t txtail; - uint16_t txnext; - ssize_t ntotal; - irqstate_t flags; - int ret; - - wlinfo("config %p buffer %p buflen %lu\n", - config, buffer, (unsigned long)buflen); - - DEBUGASSERT(config != NULL && config->state != NULL); - state = config->state; - - /* NOTE: This assumes that the caller has exclusive access to the Tx - * buffer, i.e., one lower half instance can server only one upper half! - */ - - /* Make sure that the Tx Interrupts are disabled. - * USART transmit interrupts: - * - * Enable Status Meaning Usage - * ---------------- ------------- ---------------------- ---------- - * USART_CR1_TCIE USART_SR_TC Transmission Complete (only for RS-485) - * USART_CR1_TXEIE USART_SR_TXE Transmit Data Register - * Empty - * USART_CR3_CTSIE USART_SR_CTS CTS flag (not used) - */ - - flags = spin_lock_irqsave(&config->lock); - hciuart_disableints(config, USART_CR1_TXEIE); - spin_unlock_irqrestore(&config->lock, flags); - - /* Loop until all of the user data have been moved to the Tx buffer */ - - src = buffer; - ntotal = 0; - - while (ntotal < (ssize_t)buflen) - { - /* Copy bytes to the tail of the Tx buffer */ - - /* Get a copy of the rxhead and rxtail indices of the Tx buffer */ - - txhead = state->txhead; - txtail = state->txtail; - - txnext = txtail + 1; - if (txnext >= config->txbufsize) - { - txnext = 0; - } - - /* Is there space available in the Tx buffer? Do have more bytes to - * copy? - */ - - while (txhead != txnext && ntotal < (ssize_t)buflen) - { - /* Yes.. copy one byte to the Tx buffer */ - - config->txbuffer[txtail] = *src++; - - txtail = txnext; - if (++txnext >= config->txbufsize) - { - txnext = 0; - } - - ntotal++; - } - - /* Save the updated Tx buffer tail index */ - - state->txtail = txtail; - - /* Copy bytes from the Tx buffer to the Tx FIFO */ - - nbytes = hciuart_copytotxfifo(config); - - /* If nothing could be copied to the Tx FIFO and we still have user - * data that we have not added to the Tx buffer, then we must wait for - * space in the Tx* buffer then try again. - */ - - if (nbytes <= 0 && ntotal < (ssize_t)buflen) - { - DEBUGASSERT(nbytes == 0); - - /* Enable the Tx interrupt and wait for space open up in the Tx - * buffer. - */ - - flags = enter_critical_section(); - hciuart_enableints(config, USART_CR1_TXEIE); - - DEBUGASSERT(!state->txwaiting); - state->txwaiting = true; - do - { - ret = nxsem_wait_uninterruptible(&state->txwait); - if (ret < 0) - { - if (ntotal == 0) - { - ntotal = (ssize_t)ret; - } - - break; - } - } - while (state->txwaiting); - - /* Disable Tx interrupts again */ - - hciuart_disableints(config, USART_CR1_TXEIE); - leave_critical_section(flags); - } - } - - /* If Tx buffer is not empty, then exit with Tx interrupts enabled. */ - - if (state->txhead != state->txtail) - { - flags = spin_lock_irqsave(&config->lock); - hciuart_enableints(config, USART_CR1_TXEIE); - spin_unlock_irqrestore(&config->lock, flags); - } - - return ntotal; -} - -/**************************************************************************** - * Name: hciuart_rxdrain - * - * Description: - * Flush/drain all buffered RX data - * - ****************************************************************************/ - -static ssize_t hciuart_rxdrain(const struct btuart_lowerhalf_s *lower) -{ - const struct hciuart_config_s *config = - (const struct hciuart_config_s *)lower; - struct hciuart_state_s *state; - size_t ntotal; - ssize_t nbytes; - bool rxenable; - - wlinfo("config %p\n", config); - - DEBUGASSERT(config != NULL && config->state != NULL); - state = config->state; - - /* Read any pending data to the Rx buffer */ - - nbytes = hciuart_copytorxbuffer(config); - UNUSED(nbytes); - - /* Loop discarding in the Rx buffer until the Rx buffer is empty */ - - ntotal = 0; - - rxenable = hciuart_rxenabled(config); - hciuart_rxenable(lower, false); - - while (state->rxtail != state->rxhead) - { - /* Keep track of how much is discarded */ - - ntotal += hciuart_rxinuse(config); - - /* Discard the data in the Rx buffer */ - - state->rxhead = 0; - state->rxtail = 0; - - /* Read any additional pending data into the Rx buffer that may - * have accumulated while we were discarding. - */ - - nbytes = hciuart_copytorxbuffer(config); - UNUSED(nbytes); - } - - hciuart_rxenable(lower, rxenable); - return ntotal; -} - -/**************************************************************************** - * Name: hciuart_dma_rxcallback - * - * Description: - * This function checks the current DMA state and calls the generic - * serial stack when bytes appear to be available. - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_HCIUART_RXDMA -static void hciuart_dma_rxcallback(DMA_HANDLE handle, uint8_t status, - void *arg) -{ - const struct hciuart_config_s *config = - (const struct hciuart_config_s *)arg; - struct hciuart_state_s *state; - irqstate_t flags; - ssize_t nbytes; - - flags = spin_lock_irqsave_nopreempt(&config->lock); - - if (config.state->rxdmastream == NULL) - { - spin_unlock_irqrestore_nopreempt(&config->lock, flags); - return; - } - - wlinfo("status %u config %p\n", status, config); - - DEBUGASSERT(config != NULL && config->state != NULL); - state = config->state; - - /* Received data ready... copy and data from the Rx DMA buffer to the Rx - * buffer. - */ - - nbytes = hciuart_copytorxbuffer(config); - UNUSED(nbytes); - - /* Is there anything in the Rx buffer? Has the user registered an Rx - * callback function? - */ - - if (state->rxhead != state->rxtail && state->callback != NULL) - { - state->callback(config->lower, state->arg); - handled = true; - } - - spin_unlock_irqrestore_nopreempt(&config->lock, flags); -} -#endif - -/**************************************************************************** - * Name: hciuart_pm_notify - * - * Description: - * Notify the driver of new power state. This callback is called after - * all drivers have had the opportunity to prepare for the new power state. - * - * Input Parameters: - * - * cb - Returned to the driver. The driver version of the callback - * structure may include additional, driver-specific state data at - * the end of the structure. - * - * pmstate - Identifies the new PM state - * - * Returned Value: - * None - The driver already agreed to transition to the low power - * consumption state when when it returned OK to the prepare() call. - * - * - ****************************************************************************/ - -#ifdef CONFIG_PM -static void hciuart_pm_notify(struct pm_callback_s *cb, int domain, - enum pm_state_e pmstate) -{ - switch (pmstate) - { - case (PM_NORMAL): - { - /* Logic for PM_NORMAL goes here */ - } - break; - - case (PM_IDLE): - { - /* Logic for PM_IDLE goes here */ - } - break; - - case (PM_STANDBY): - { - /* Logic for PM_STANDBY goes here */ - } - break; - - case (PM_SLEEP): - { - /* Logic for PM_SLEEP goes here */ - } - break; - - default: - - /* Should not get here */ - - break; - } -} -#endif - -/**************************************************************************** - * Name: hciuart_pm_prepare - * - * Description: - * Request the driver to prepare for a new power state. This is a warning - * that the system is about to enter into a new power state. The driver - * should begin whatever operations that may be required to enter power - * state. The driver may abort the state change mode by returning a - * non-zero value from the callback function. - * - * Input Parameters: - * - * cb - Returned to the driver. The driver version of the callback - * structure may include additional, driver-specific state data at - * the end of the structure. - * - * pmstate - Identifies the new PM state - * - * Returned Value: - * Zero - (OK) means the event was successfully processed and that the - * driver is prepared for the PM state change. - * - * Non-zero - means that the driver is not prepared to perform the tasks - * needed achieve this power setting and will cause the state - * change to be aborted. NOTE: The prepare() method will also - * be called when reverting from lower back to higher power - * consumption modes (say because another driver refused a - * lower power state change). Drivers are not permitted to - * return non-zero values when reverting back to higher power - * consumption modes! - * - * - ****************************************************************************/ - -#ifdef CONFIG_PM -static int hciuart_pm_prepare(struct pm_callback_s *cb, int domain, - enum pm_state_e pmstate) -{ - /* Logic to prepare for a reduced power state goes here. */ - - return OK; -} -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: hciuart_instantiate - * - * Description: - * Obtain an instance of the HCI UART interface for the specified HCI UART - * This assumes that hciuart_initialize was called previously. - * - * Input Parameters: - * uart - Identifies the HCI UART to be configured - * - * Returned Value: - * On success, a reference to the HCI UART lower driver for the associated - * U[S]ART - * - ****************************************************************************/ - -const struct btuart_lowerhalf_s * - hciuart_instantiate(enum hciuart_devno_e uart) -{ - const struct hciuart_config_s *config; -#ifdef CONFIG_PM - int ret; -#endif - - wlinfo("Instantiating HCIUART%d\n", (int)uart + 1); - DEBUGASSERT((int)uart >= 0 && (int)uart < 8); - - /* Check if this uart is available in the configuration */ - - config = g_hciuarts[(int)uart]; - if (config == NULL) - { - wlerr("ERROR: UART%d not configured\n", uart + 1); - return NULL; - } - - /* Register to receive power management callbacks */ - -#ifdef CONFIG_PM - ret = pm_register(&g_serialcb); - DEBUGASSERT(ret == OK); - UNUSED(ret); -#endif - - /* Configure and enable the UART */ - - hciuart_configure(config); - return &config->lower; -} - -/**************************************************************************** - * Name: hciuart_initialize - * - * Description: - * Performs the low-level, one-time USART initialization. This must be - * called before hciuart_instantiate. - * - ****************************************************************************/ - -void hciuart_initialize(void) -{ - const struct hciuart_config_s *config; - struct hciuart_state_s *state; - int ret; - int i; - - /* Configure all USARTs */ - - for (i = 0; i < STM32_NUSART; i++) - { - config = g_hciuarts[i]; - if (config != NULL) - { - state = config->state; - - wlinfo("Initializing HCIUART%d\n", i + 1); - - /* Disable U[S]ART interrupts */ - - hciuart_disableints(config, HCIUART_ALLINTS); - - /* Attach and enable the HCI UART IRQ */ - - ret = irq_attach(config->irq, hciuart_interrupt, (void *)config); - if (ret == OK) - { - /* Enable the interrupt (RX and TX interrupts are still - * disabled in the USART) - */ - - up_enable_irq(config->irq); - } - } - } -} - -/**************************************************************************** - * Name: stm32_serial_dma_poll - * - * Description: - * Checks receive DMA buffers for received bytes that have not accumulated - * to the point where the DMA half/full interrupt has triggered. - * - * This function should be called from a timer or other periodic context. - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_HCIUART_RXDMA -void stm32_serial_dma_poll(void) -{ -#ifdef CONFIG_STM32_HCIUART1_RXDMA - hciuart_dma_rxcallback(g_hciusart1_config.state->rxdmastream, 0, - &g_hciusart1_config); -#endif - -#ifdef CONFIG_STM32_HCIUART2_RXDMA - hciuart_dma_rxcallback(g_hciusart2_config.state->rxdmastream, 0, - &g_hciusart2_config); -#endif - -#ifdef CONFIG_STM32_HCIUART3_RXDMA - hciuart_dma_rxcallback(g_hciusart3_config.state->rxdmastream, 0, - &g_hciusart3_config); -#endif - -#ifdef CONFIG_STM32_HCIUART6_RXDMA - hciuart_dma_rxcallback(g_hciusart6_config.state->rxdmastream, 0, - &g_hciusart6_config); -#endif - -#ifdef CONFIG_STM32_HCIUART7_RXDMA - hciuart_dma_rxcallback(g_hciuart7_config.state->rxdmastream, - 0, - &g_hciuart7_config); -#endif - -#ifdef CONFIG_STM32_HCIUART8_RXDMA - hciuart_dma_rxcallback(g_hciuart8.state->rxdmastream, 0, - &g_hciuart8_config); -#endif -} -#endif diff --git a/arch/arm/src/stm32/stm32_hciuart.h b/arch/arm/src/stm32/stm32_hciuart.h deleted file mode 100644 index ccbc7af5f4d8d..0000000000000 --- a/arch/arm/src/stm32/stm32_hciuart.h +++ /dev/null @@ -1,96 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_hciuart.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32_STM32_HCIUART_H -#define __ARCH_ARM_SRC_STM32_STM32_HCIUART_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -enum hciuart_devno_e -{ - HCIUART1 = 0, /* HCI UART on STM32 USART1 */ - HCIUART2 = 1, /* HCI UART on STM32 USART2 */ - HCIUART3 = 2, /* HCI UART on STM32 USART3 */ - /* UARTs 4-5 do not support RTS/CTS flow control */ - HCIUART5 = 5, /* HCI UART on STM32 USART6 */ - HCIUART6 = 6, /* HCI UART on STM32 UART7 */ - HCIUART7 = 7 /* HCI UART on STM32 UART8 */ -}; - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: hciuart_instantiate - * - * Description: - * Obtain an instance of the HCI UART interface for the specified HCI UART - * This assumes that hciuart_initialize was called previously. - * - * Input Parameters: - * uart - Identifies the HCI UART to be configured - * - * Returned Value: - * On success, a reference to the HCI UART lower driver for the associated - * U[S]ART - * - ****************************************************************************/ - -const struct btuart_lowerhalf_s * -hciuart_instantiate(enum hciuart_devno_e uart); - -/**************************************************************************** - * Name: hciuart_initialize - * - * Description: - * Performs the low-level, one-time USART initialization. This must be - * called before hciuart_instantiate. - * - ****************************************************************************/ - -void hciuart_initialize(void); - -/**************************************************************************** - * Name: stm32_serial_dma_poll - * - * Description: - * Checks receive DMA buffers for received bytes that have not accumulated - * to the point where the DMA half/full interrupt has triggered. - * - * This function should be called from a timer or other periodic context. - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_HCIUART_RXDMA -void stm32_serial_dma_poll(void); -#endif - -#endif /* __ARCH_ARM_SRC_STM32_STM32_HCIUART_H */ diff --git a/arch/arm/src/stm32/stm32_hrtim.c b/arch/arm/src/stm32/stm32_hrtim.c deleted file mode 100644 index 86e0a074b2633..0000000000000 --- a/arch/arm/src/stm32/stm32_hrtim.c +++ /dev/null @@ -1,6043 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_hrtim.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include - -#include - -#include "chip.h" -#include "stm32.h" -#include "stm32_gpio.h" -#include "stm32_hrtim.h" - -#if defined(CONFIG_STM32_HRTIM1) - -/* Only STM32F33XXX and STM32G47XXX */ - -#if defined(CONFIG_STM32_STM32F33XX) || defined(CONFIG_STM32_STM32G47XX) - -#if defined(CONFIG_STM32_HRTIM_TIMA_PWM) || defined(CONFIG_STM32_HRTIM_TIMA_DAC) || \ - defined(CONFIG_STM32_HRTIM_TIMA_CAP) || defined(CONFIG_STM32_HRTIM_TIMA_IRQ) || \ - defined(CONFIG_STM32_HRTIM_TIMA_DT) || defined(CONFIG_STM32_HRTIM_TIMA_CHOP) -# ifndef CONFIG_STM32_HRTIM_TIMA -# error "CONFIG_STM32_HRTIM_TIMA must be set" -# endif -#endif -#if defined(CONFIG_STM32_HRTIM_TIMB_PWM) || defined(CONFIG_STM32_HRTIM_TIMB_DAC) || \ - defined(CONFIG_STM32_HRTIM_TIMB_CAP) || defined(CONFIG_STM32_HRTIM_TIMB_IRQ) || \ - defined(CONFIG_STM32_HRTIM_TIMB_DT) || defined(CONFIG_STM32_HRTIM_TIMB_CHOP) -# ifndef CONFIG_STM32_HRTIM_TIMB -# error "CONFIG_STM32_HRTIM_TIMB must be set" -# endif -#endif -#if defined(CONFIG_STM32_HRTIM_TIMC_PWM) || defined(CONFIG_STM32_HRTIM_TIMC_DAC) || \ - defined(CONFIG_STM32_HRTIM_TIMC_CAP) || defined(CONFIG_STM32_HRTIM_TIMC_IRQ) || \ - defined(CONFIG_STM32_HRTIM_TIMC_DT) || defined(CONFIG_STM32_HRTIM_TIMC_CHOP) -# ifndef CONFIG_STM32_HRTIM_TIMC -# error "CONFIG_STM32_HRTIM_TIMC must be set" -# endif -#endif -#if defined(CONFIG_STM32_HRTIM_TIMD_PWM) || defined(CONFIG_STM32_HRTIM_TIMD_DAC) || \ - defined(CONFIG_STM32_HRTIM_TIMD_CAP) || defined(CONFIG_STM32_HRTIM_TIMD_IRQ) || \ - defined(CONFIG_STM32_HRTIM_TIMD_DT) || defined(CONFIG_STM32_HRTIM_TIMD_CHOP) -# ifndef CONFIG_STM32_HRTIM_TIMD -# error "CONFIG_STM32_HRTIM_TIMD must be set" -# endif -#endif -#if defined(CONFIG_STM32_HRTIM_TIME_PWM) || defined(CONFIG_STM32_HRTIM_TIME_DAC) || \ - defined(CONFIG_STM32_HRTIM_TIME_CAP) || defined(CONFIG_STM32_HRTIM_TIME_IRQ) || \ - defined(CONFIG_STM32_HRTIM_TIME_DT) || defined(CONFIG_STM32_HRTIM_TIME_CHOP) -# ifndef CONFIG_STM32_HRTIM_TIME -# error "CONFIG_STM32_HRTIM_TIME must be set" -# endif -#endif - -#if defined(CONFIG_STM32_HRTIM_PWM) -#if !defined(CONFIG_STM32_HRTIM_TIMA_PWM) && !defined(CONFIG_STM32_HRTIM_TIMB_PWM) && \ - !defined(CONFIG_STM32_HRTIM_TIMC_PWM) && !defined(CONFIG_STM32_HRTIM_TIMD_PWM) && \ - !defined(CONFIG_STM32_HRTIM_TIME_PWM) -# warning "CONFIG_STM32_HRTIM_PWM enabled but no timer selected" -# endif -#endif -#if defined(CONFIG_STM32_HRTIM_DAC) -#if !defined(CONFIG_STM32_HRTIM_MASTER_DAC) && !defined(CONFIG_STM32_HRTIM_TIMA_DAC) && \ - !defined(CONFIG_STM32_HRTIM_TIMB_DAC) && !defined(CONFIG_STM32_HRTIM_TIMC_DAC) && \ - !defined(CONFIG_STM32_HRTIM_TIMD_DAC) && !defined(CONFIG_STM32_HRTIM_TIME_DAC) -# warning "CONFIG_STM32_HRTIM_DAC enabled but no timer selected" -# endif -#endif -#if defined(CONFIG_STM32_HRTIM_CAPTURE) -#if !defined(CONFIG_STM32_HRTIM_TIMA_CAP) && !defined(CONFIG_STM32_HRTIM_TIMB_CAP) && \ - !defined(CONFIG_STM32_HRTIM_TIMC_CAP) && !defined(CONFIG_STM32_HRTIM_TIMD_CAP) && \ - !defined(CONFIG_STM32_HRTIM_TIME_CAP) -# warning "CONFIG_STM32_HRTIM_CAPTURE enabled but no timer selected" -# endif -#endif -#if defined(CONFIG_STM32_HRTIM_INTERRUPTS) -#if !defined(CONFIG_STM32_HRTIM_MASTER_IRQ) && !defined(CONFIG_STM32_HRTIM_TIMA_IRQ) && \ - !defined(CONFIG_STM32_HRTIM_TIMB_IRQ) && !defined(CONFIG_STM32_HRTIM_TIMC_IRQ) && \ - !defined(CONFIG_STM32_HRTIM_TIMD_IRQ) && !defined(CONFIG_STM32_HRTIM_TIME_IRQ) && \ - !defined(CONFIG_STM32_HRTIM_COMMON_IRQ) -# warning "CONFIG_STM32_HRTIM_INTERRUPTS enabled but no timer selected" -# endif -#endif -#if defined(CONFIG_STM32_HRTIM_DEADTIME) -#if !defined(CONFIG_STM32_HRTIM_TIMA_DT) && !defined(CONFIG_STM32_HRTIM_TIMB_DT) && \ - !defined(CONFIG_STM32_HRTIM_TIMC_DT) && !defined(CONFIG_STM32_HRTIM_TIMD_DT) && \ - !defined(CONFIG_STM32_HRTIM_TIME_DT) -# warning "CONFIG_STM32_HRTIM_DEADTIME enabled but no timer selected" -# endif -#endif -#if defined(CONFIG_STM32_HRTIM_CHOPPER) -#if !defined(CONFIG_STM32_HRTIM_TIMA_CHOP) && !defined(CONFIG_STM32_HRTIM_TIMB_CHOP) && \ - !defined(CONFIG_STM32_HRTIM_TIMC_CHOP) && !defined(CONFIG_STM32_HRTIM_TIMD_CHOP) && \ - !defined(CONFIG_STM32_HRTIM_TIME_CHOP) -# warning "CONFIG_STM32_HRTIM_CHOPPER enabled but no timer selected" -# endif -#endif - -#if defined(CONFIG_STM32_HRTIM_TIMA_PWM) || defined(CONFIG_STM32_HRTIM_TIMB_PWM) || \ - defined(CONFIG_STM32_HRTIM_TIMC_PWM) || defined(CONFIG_STM32_HRTIM_TIMD_PWM) || \ - defined(CONFIG_STM32_HRTIM_TIME_PWM) -# ifndef CONFIG_STM32_HRTIM_PWM -# error "CONFIG_STM32_HRTIM_PWM must be set" -# endif -#endif -#if defined(CONFIG_STM32_HRTIM_MASTER_DAC) || defined(CONFIG_STM32_HRTIM_TIMA_DAC) || \ - defined(CONFIG_STM32_HRTIM_TIMB_DAC) || defined(CONFIG_STM32_HRTIM_TIMC_DAC) || \ - defined(CONFIG_STM32_HRTIM_TIMD_DAC) || defined(CONFIG_STM32_HRTIM_TIME_DAC) -# ifndef CONFIG_STM32_HRTIM_DAC -# error "CONFIG_STM32_HRTIM_DAC must be set" -# endif -#endif -#if defined(CONFIG_STM32_HRTIM_TIMA_CAP) || defined(CONFIG_STM32_HRTIM_TIMB_CAP) || \ - defined(CONFIG_STM32_HRTIM_TIMC_CAP) || defined(CONFIG_STM32_HRTIM_TIMD_CAP) || \ - defined(CONFIG_STM32_HRTIM_TIME_CAP) -# ifndef CONFIG_STM32_HRTIM_CAPTURE -# error "CONFIG_STM32_HRTIM_CAPTURE must be set" -# endif -#endif -#if defined(CONFIG_STM32_HRTIM_TIMA_IRQ) || defined(CONFIG_STM32_HRTIM_TIMB_IRQ) || \ - defined(CONFIG_STM32_HRTIM_TIMC_IRQ) || defined(CONFIG_STM32_HRTIM_TIMD_IRQ) || \ - defined(CONFIG_STM32_HRTIM_TIME_IRQ) -# ifndef CONFIG_STM32_HRTIM_INTERRUPTS -# error "CONFIG_STM32_HRTIM_INTERRUPTS must be set" -# endif -#endif -#if defined(CONFIG_STM32_HRTIM_TIMA_DT) || defined(CONFIG_STM32_HRTIM_TIMB_DT) || \ - defined(CONFIG_STM32_HRTIM_TIMC_DT) || defined(CONFIG_STM32_HRTIM_TIMD_DT) || \ - defined(CONFIG_STM32_HRTIM_TIME_DT) -# ifndef CONFIG_STM32_HRTIM_DEADTIME -# error "CONFIG_STM32_HRTIM_DEADTIME must be set" -# endif -#endif -#if defined(CONFIG_STM32_HRTIM_TIMA_CHOP) || defined(CONFIG_STM32_HRTIM_TIMB_CHOP) || \ - defined(CONFIG_STM32_HRTIM_TIMC_CHOP) || defined(CONFIG_STM32_HRTIM_TIMD_CHOP) || \ - defined(CONFIG_STM32_HRTIM_TIME_CHOP) -# ifndef CONFIG_STM32_HRTIM_CHOPPER -# error "CONFIG_STM32_HRTIM_CHOPPER must be set" -# endif -#endif -#if defined(CONFIG_STM32_HRTIM_TIMA_PSHPLL) || defined(CONFIG_STM32_HRTIM_TIMB_PSHPLL) || \ - defined(CONFIG_STM32_HRTIM_TIMC_PSHPLL) || defined(CONFIG_STM32_HRTIM_TIMD_PSHPLL) || \ - defined(CONFIG_STM32_HRTIM_TIME_PSHPLL) -# ifndef CONFIG_STM32_HRTIM_PUSHPULL -# error "CONFIG_STM32_HRTIM_PUSHPULL must be set" -# endif -#endif - -#if defined(CONFIG_STM32_HRTIM_TIMA_DT) && defined(CONFIG_STM32_HRTIM_TIMA_PSHPLL) -# error "The deadtime cannot be used simultaneously with the push-pull mode" -#endif -#if defined(CONFIG_STM32_HRTIM_TIMB_DT) && defined(CONFIG_STM32_HRTIM_TIMB_PSHPLL) -# error "The deadtime cannot be used simultaneously with the push-pull mode" -#endif -#if defined(CONFIG_STM32_HRTIM_TIMC_DT) && defined(CONFIG_STM32_HRTIM_TIMC_PSHPLL) -# error "The deadtime cannot be used simultaneously with the push-pull mode" -#endif -#if defined(CONFIG_STM32_HRTIM_TIMD_DT) && defined(CONFIG_STM32_HRTIM_TIMD_PSHPLL) -# error "The deadtime cannot be used simultaneously with the push-pull mode" -#endif -#if defined(CONFIG_STM32_HRTIM_TIME_DT) && defined(CONFIG_STM32_HRTIM_TIME_PSHPLL) -# error "The deadtime cannot be used simultaneously with the push-pull mode" -#endif - -#if defined(CONFIG_STM32_HRTIM_ADC1_TRG1) || defined(CONFIG_STM32_HRTIM_ADC1_TRG2) || \ - defined(CONFIG_STM32_HRTIM_ADC1_TRG3) || defined(CONFIG_STM32_HRTIM_ADC1_TRG4) || \ - defined(CONFIG_STM32_HRTIM_ADC2_TRG1) || defined(CONFIG_STM32_HRTIM_ADC2_TRG2) || \ - defined(CONFIG_STM32_HRTIM_ADC2_TRG3) || defined(CONFIG_STM32_HRTIM_ADC2_TRG4) -# define HRTIM_HAVE_ADC -#endif - -#if defined(CONFIG_STM32_HRTIM_ADC1_TRG1) || defined(CONFIG_STM32_HRTIM_ADC2_TRG1) -# define HRTIM_HAVE_ADC_TRG1 -#endif -#if defined(CONFIG_STM32_HRTIM_ADC1_TRG2) || defined(CONFIG_STM32_HRTIM_ADC2_TRG2) -# define HRTIM_HAVE_ADC_TRG2 -#endif -#if defined(CONFIG_STM32_HRTIM_ADC1_TRG3) || defined(CONFIG_STM32_HRTIM_ADC2_TRG3) -# define HRTIM_HAVE_ADC_TRG3 -#endif -#if defined(CONFIG_STM32_HRTIM_ADC1_TRG4) || defined(CONFIG_STM32_HRTIM_ADC2_TRG4) -# define HRTIM_HAVE_ADC_TRG4 -#endif - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* HRTIM default configuration **********************************************/ - -#if defined(CONFIG_STM32_HRTIM_MASTER) && !defined(HRTIM_MASTER_MODE) -# warning "HRTIM_MASTER_MODE is not set. Set the default value 0" -# define HRTIM_MASTER_MODE 0 -#endif -#if defined(CONFIG_STM32_HRTIM_TIMA) && !defined( HRTIM_TIMA_MODE) -# warning "HRTIM_TIMA_MODE is not set. Set the default value 0" -# define HRTIM_TIMA_MODE 0 -#endif -#if defined(CONFIG_STM32_HRTIM_TIMB) && !defined(HRTIM_TIMB_MODE) -# warning "HRTIM_TIMB_MODE is not set. Set the default value 0" -# define HRTIM_TIMB_MODE 0 -#endif -#if defined(CONFIG_STM32_HRTIM_TIMC) && !defined(HRTIM_TIMC_MODE) -# warning "HRTIM_TIMC_MODE is not set. Set the default value 0" -# define HRTIM_TIMC_MODE 0 -#endif -#if defined(CONFIG_STM32_HRTIM_TIMD) && !defined(HRTIM_TIMD_MODE) -# warning "HRTIM_TIMD_MODE is not set. Set the default value 0" -# define HRTIM_TIMD_MODE 0 -#endif -#if defined(CONFIG_STM32_HRTIM_TIME) && !defined(HRTIM_TIME_MODE) -# warning "HRTIM_TIME_MODE is not set. Set the default value 0" -# define HRTIM_TIME_MODE 0 -#endif - -#if defined(CONFIG_STM32_HRTIM_TIMA) && !defined(HRTIM_TIMA_UPDATE) -# warning "HRTIM_TIMA_UPDATE is not set. Set the default value 0" -# define HRTIM_TIMA_UPDATE 0 -#endif -#if defined(CONFIG_STM32_HRTIM_TIMB) && !defined(HRTIM_TIMB_UPDATE) -# warning "HRTIM_TIMB_UPDATE is not set. Set the default value 0" -# define HRTIM_TIMB_UPDATE 0 -#endif -#if defined(CONFIG_STM32_HRTIM_TIMC) && !defined(HRTIM_TIMC_UPDATE) -# warning "HRTIM_TIMC_UPDATE is not set. Set the default value 0" -# define HRTIM_TIMC_UPDATE 0 -#endif -#if defined(CONFIG_STM32_HRTIM_TIMD) && !defined(HRTIM_TIMD_UPDATE) -# warning "HRTIM_TIMD_UPDATE is not set. Set the default value 0" -# define HRTIM_TIMD_UPDATE 0 -#endif -#if defined(CONFIG_STM32_HRTIM_TIME) && !defined(HRTIM_TIME_UPDATE) -# warning "HRTIM_TIME_UPDATE is not set. Set the default value 0" -# define HRTIM_TIME_UPDATE 0 -#endif - -#if defined(CONFIG_STM32_HRTIM_TIMA) && !defined( HRTIM_TIMA_RESET) -# warning "HRTIM_TIMA_RESET is not set. Set the default value 0" -# define HRTIM_TIMA_RESET 0 -#endif -#if defined(CONFIG_STM32_HRTIM_TIMB) && !defined(HRTIM_TIMB_RESET) -# warning "HRTIM_TIMB_RESET is not set. Set the default value 0" -# define HRTIM_TIMB_RESET 0 -#endif -#if defined(CONFIG_STM32_HRTIM_TIMC) && !defined(HRTIM_TIMC_RESET) -# warning "HRTIM_TIMC_RESET is not set. Set the default value 0" -# define HRTIM_TIMC_RESET 0 -#endif -#if defined(CONFIG_STM32_HRTIM_TIMD) && !defined(HRTIM_TIMD_RESET) -# warning "HRTIM_TIMD_RESET is not set. Set the default value 0" -# define HRTIM_TIMD_RESET 0 -#endif -#if defined(CONFIG_STM32_HRTIM_TIME) && !defined(HRTIM_TIME_RESET) -# warning "HRTIM_TIME_RESET is not set. Set the default value 0" -# define HRTIM_TIME_RESET 0 -#endif - -#ifndef HRTIM_IRQ_COMMON -# define HRTIM_IRQ_COMMON 0 -#endif - -#if defined(CONFIG_STM32_HRTIM_TIMA) && !defined(HRTIM_TIMA_CH1_POL) -# define HRTIM_TIMA_CH1_POL HRTIM_OUT_POL_POS -#endif -#if defined(CONFIG_STM32_HRTIM_TIMA) && !defined(HRTIM_TIMA_CH2_POL) -# define HRTIM_TIMA_CH2_POL HRTIM_OUT_POL_POS -#endif -#if defined(CONFIG_STM32_HRTIM_TIMB) && !defined(HRTIM_TIMB_CH1_POL) -# define HRTIM_TIMB_CH1_POL HRTIM_OUT_POL_POS -#endif -#if defined(CONFIG_STM32_HRTIM_TIMB) && !defined(HRTIM_TIMB_CH2_POL) -# define HRTIM_TIMB_CH2_POL HRTIM_OUT_POL_POS -#endif -#if defined(CONFIG_STM32_HRTIM_TIMC) && !defined(HRTIM_TIMC_CH1_POL) -# define HRTIM_TIMC_CH1_POL HRTIM_OUT_POL_POS -#endif -#if defined(CONFIG_STM32_HRTIM_TIMC) && !defined(HRTIM_TIMC_CH2_POL) -# define HRTIM_TIMC_CH2_POL HRTIM_OUT_POL_POS -#endif -#if defined(CONFIG_STM32_HRTIM_TIMD) && !defined(HRTIM_TIMD_CH1_POL) -# define HRTIM_TIMD_CH1_POL HRTIM_OUT_POL_POS -#endif -#if defined(CONFIG_STM32_HRTIM_TIMD) && !defined(HRTIM_TIMD_CH2_POL) -# define HRTIM_TIMD_CH2_POL HRTIM_OUT_POL_POS -#endif -#if defined(CONFIG_STM32_HRTIM_TIME) && !defined(HRTIM_TIME_CH1_POL) -# define HRTIM_TIME_CH1_POL HRTIM_OUT_POL_POS -#endif -#if defined(CONFIG_STM32_HRTIM_TIME) && !defined(HRTIM_TIME_CH2_POL) -# define HRTIM_TIME_CH2_POL HRTIM_OUT_POL_POS -#endif - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -#ifdef CONFIG_STM32_HRTIM_PWM -/* HRTIM Slave Timer Single Output Set/Reset Configuration */ - -struct stm32_hrtim_timout_s -{ - uint32_t set; /* Set events */ - uint32_t rst; /* Reset events */ - uint8_t pol:1; /* Output polarisation */ -}; - -/* HRTIM Slave Timer Chopper Configuration */ - -#ifdef CONFIG_STM32_HRTIM_CHOPPER -struct stm32_hrtim_chopper_s -{ - uint16_t start_pulse:4; /* Chopper start pulsewidth */ - uint16_t freq:4; /* Chopper carrier frequency value */ - uint16_t duty:3; /* Chopper duty cycle */ - uint16_t _res:5; /* Reserved */ -}; -#endif - -/* HRTIM Slave Timer Deadtime Configuration */ - -#ifdef CONFIG_STM32_HRTIM_DEADTIME -struct stm32_hrtim_deadtime_s -{ - uint8_t en:1; /* Enable deadtime for timer */ - uint8_t fsign_lock:1; /* Deadtime falling sing lock */ - uint8_t rsign_lock:1; /* Deadtime rising sing lock */ - uint8_t falling_lock:1; /* Deadtime falling value lock */ - uint8_t rising_lock:1; /* Deadtime rising value lock */ - uint8_t fsign:1; /* Deadtime falling sign */ - uint8_t rsign:1; /* Deadtime rising sign */ - uint8_t prescaler:3; /* Deadtime prescaler */ - uint16_t rising:9; /* Deadtime rising value */ - uint16_t falling:9; /* Deadtime falling value */ -}; -#endif - -/* HRTIM Timer Burst Mode Configuration */ - -struct stm32_hrtim_tim_burst_s -{ - uint8_t ch1_en:1; /* Enable burst mode operation for CH1 */ - uint8_t ch1_state:1; /* CH1 IDLE state */ - uint8_t ch2_en:1; /* Enable burst mode operation for CH2 */ - uint8_t ch2_state:1; /* CH2 IDLE state */ - uint8_t res:4; -}; - -/* HRTIM Timer PWM structure */ - -struct stm32_hrtim_pwm_s -{ - uint8_t pushpull:1; - uint8_t res:7; - struct stm32_hrtim_timout_s ch1; /* Channel 1 Set/Reset configuration */ - struct stm32_hrtim_timout_s ch2; /* Channel 2 Set/Reset configuration */ - -#ifdef CONFIG_STM32_HRTIM_BURST - struct stm32_hrtim_tim_burst_s burst; -#endif -#ifdef CONFIG_STM32_HRTIM_CHOPPER - struct stm32_hrtim_chopper_s chp; -#endif -#ifdef CONFIG_STM32_HRTIM_DEADTIME - struct stm32_hrtim_deadtime_s dt; -#endif -}; -#endif - -/* HRTIM TIMER Capture structure */ - -#ifdef CONFIG_STM32_HRTIM_CAPTURE -struct stm32_hrtim_capture_s -{ - uint32_t cap1; /* Capture 1 configuration */ - uint32_t cap2; /* Capture 2 configuration */ -}; -#endif - -/* Common data structure for Master Timer and Slave Timers */ - -struct stm32_hrtim_timcmn_s -{ - uint32_t base; /* The base address of the timer */ - uint64_t fclk; /* The frequency of the peripheral clock - * that drives the timer module. - */ - uint8_t prescaler:3; /* Prescaler */ - uint8_t mode; /* Timer mode */ - uint8_t dac:2; /* DAC triggering */ - uint8_t reserved:3; -#ifdef CONFIG_STM32_HRTIM_INTERRUPTS - uint16_t irq; /* interrupts configuration */ -#endif -#ifdef CONFIG_STM32_HRTIM_DMA - uint16_t dma; -#endif -#ifdef CONFIG_STM32_HRTIM_DMABURST - uint32_t dmaburst; -#endif -}; - -/* Master Timer and Slave Timers structure */ - -struct stm32_hrtim_tim_s -{ - struct stm32_hrtim_timcmn_s tim; /* Common Timer data */ - void *priv; /* Timer private data */ -}; - -/* Master Timer private data structure */ - -struct stm32_hrtim_master_priv_s -{ - uint32_t reserved; /* reserved for future use */ -}; - -/* Slave Timer (A-E) private data structure */ - -struct stm32_hrtim_slave_priv_s -{ -#ifdef CONFIG_STM32_HRTIM_FAULTS - uint8_t flt; /* Faults configuration. - * First five bits are fault sources, - * last bit is lock configuration. - */ -#ifdef CONFIG_STM32_HRTIM_AUTODELAYED - uint8_t auto_delayed; /* Auto-delayed mode configuration */ -#endif -#endif - uint16_t update; /* Update configuration */ - uint64_t reset; /* Timer reset events */ -#ifdef CONFIG_STM32_HRTIM_PWM - struct stm32_hrtim_pwm_s pwm; /* PWM configuration */ -#endif -#ifdef CONFIG_STM32_HRTIM_CAPTURE - struct stm32_hrtim_capture_s cap; /* Capture configuration */ -#endif -}; - -#ifdef CONFIG_STM32_HRTIM_FAULTS -/* Structure describes single HRTIM Fault configuration */ - -struct stm32_hrtim_fault_cfg_s -{ - uint8_t pol:1; /* Fault polarity */ - uint8_t src:1; /* Fault source */ - uint8_t filter:4; /* Fault filter */ - uint8_t lock:1; /* Fault lock */ - uint8_t _res:1; /* Reserved */ -}; - -/* Structure describes HRTIM Faults configuration */ - -struct stm32_hrtim_faults_s -{ -#ifdef CONFIG_STM32_HRTIM_FAULT1 - struct stm32_hrtim_fault_cfg_s flt1; -#endif -#ifdef CONFIG_STM32_HRTIM_FAULT2 - struct stm32_hrtim_fault_cfg_s flt2; -#endif -#ifdef CONFIG_STM32_HRTIM_FAULT3 - struct stm32_hrtim_fault_cfg_s flt3; -#endif -#ifdef CONFIG_STM32_HRTIM_FAULT4 - struct stm32_hrtim_fault_cfg_s flt4; -#endif -#ifdef CONFIG_STM32_HRTIM_FAULT5 - struct stm32_hrtim_fault_cfg_s flt5; -#endif -}; -#endif - -#ifdef CONFIG_STM32_HRTIM_EVENTS -/* Structure describes single HRTIM External Event configuration */ - -struct stm32_hrtim_eev_cfg_s -{ - uint8_t filter:4; /* External Event filter */ - uint8_t src:4; /* External Event source */ - uint8_t pol:1; /* External Event polarity */ - uint8_t sen:1; /* External Event sensitivity */ - uint8_t mode:1; /* External Event mode */ - uint8_t _res:5; -}; - -/* Structure describes HRTIM External Events configuration */ - -struct stm32_hrtim_eev_s -{ -#ifdef CONFIG_STM32_HRTIM_EEV1 - struct stm32_hrtim_eev_cfg_s eev1; -#endif -#ifdef CONFIG_STM32_HRTIM_EEV2 - struct stm32_hrtim_eev_cfg_s eev2; -#endif -#ifdef CONFIG_STM32_HRTIM_EEV3 - struct stm32_hrtim_eev_cfg_s eev3; -#endif -#ifdef CONFIG_STM32_HRTIM_EEV4 - struct stm32_hrtim_eev_cfg_s eev4; -#endif -#ifdef CONFIG_STM32_HRTIM_EEV5 - struct stm32_hrtim_eev_cfg_s eev5; -#endif -#ifdef CONFIG_STM32_HRTIM_EEV6 - struct stm32_hrtim_eev_cfg_s eev6; -#endif -#ifdef CONFIG_STM32_HRTIM_EEV7 - struct stm32_hrtim_eev_cfg_s eev7; -#endif -#ifdef CONFIG_STM32_HRTIM_EEV8 - struct stm32_hrtim_eev_cfg_s eev8; -#endif -#ifdef CONFIG_STM32_HRTIM_EEV9 - struct stm32_hrtim_eev_cfg_s eev9; -#endif -#ifdef CONFIG_STM32_HRTIM_EEV10 - struct stm32_hrtim_eev_cfg_s eev10; -#endif -}; -#endif - -#ifdef HRTIM_HAVE_ADC -/* Structure describes HRTIM ADC triggering configuration */ - -struct stm32_hrtim_adc_s -{ -#ifdef HRTIM_HAVE_ADC_TRG1 - uint32_t trg1; -#endif -#ifdef HRTIM_HAVE_ADC_TRG2 - uint32_t trg2; -#endif -#ifdef HRTIM_HAVE_ADC_TRG3 - uint32_t trg3; -#endif -#ifdef HRTIM_HAVE_ADC_TRG4 - uint32_t trg4; -#endif -}; -#endif - -/* Structure describes HRTIM Burst mode configuratione */ - -#ifdef CONFIG_STM32_HRTIM_BURST -struct stm32_hrtim_burst_s -{ - uint8_t clk:4; /* Burst mode clock source */ - uint8_t presc:4; /* Prescaler for f_HRTIM clock */ - uint32_t trg; /* Burst mode triggers */ -}; -#endif - -/* This structure describes the configuration of HRTIM device */ - -struct stm32_hrtim_s -{ - uint32_t base; /* Base address of HRTIM block */ - struct stm32_hrtim_tim_s *master; /* Master Timer */ -#ifdef CONFIG_STM32_HRTIM_TIMA - struct stm32_hrtim_tim_s *tima; /* HRTIM Timer A */ -#endif -#ifdef CONFIG_STM32_HRTIM_TIMB - struct stm32_hrtim_tim_s *timb; /* HRTIM Timer B */ -#endif -#ifdef CONFIG_STM32_HRTIM_TIMC - struct stm32_hrtim_tim_s *timc; /* HRTIM Timer C */ -#endif -#ifdef CONFIG_STM32_HRTIM_TIMD - struct stm32_hrtim_tim_s *timd; /* HRTIM Timer D */ -#endif -#ifdef CONFIG_STM32_HRTIM_TIME - struct stm32_hrtim_tim_s *time; /* HRTIM Timer E */ -#endif -#ifdef CONFIG_STM32_HRTIM_FAULTS - struct stm32_hrtim_faults_s *flt; /* Faults configuration */ -#endif -#ifdef CONFIG_STM32_HRTIM_EVENTS - struct stm32_hrtim_eev_s *eev; /* External Events configuration */ -#endif -#ifdef HRTIM_HAVE_ADC - struct stm32_hrtim_adc_s *adc; /* ADC triggering configuration */ -#endif -#ifdef CONFIG_STM32_HRTIM_BURST - struct stm32_hrtim_burst_s *burst; /* Burst mode configuration */ -#endif -#ifdef CONFIG_STM32_HRTIM_INTERRUPTS - uint32_t irq; /* Common interrupts configuration */ -#endif -}; - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -#ifndef CONFIG_STM32_HRTIM_DISABLE_CHARDRV - -/* HRTIM Driver Methods */ - -static int stm32_hrtim_open(struct file *filep); -static int stm32_hrtim_close(struct file *filep); -static int stm32_hrtim_ioctl(struct file *filep, int cmd, - unsigned long arg); -#endif - -/* HRTIM Register access */ - -static uint32_t hrtim_cmn_getreg(struct stm32_hrtim_s *priv, - uint32_t offset); -static void hrtim_cmn_putreg(struct stm32_hrtim_s *priv, uint32_t offset, - uint32_t value); -#ifdef CONFIG_STM32_HRTIM_BURST -static void hrtim_cmn_modifyreg(struct stm32_hrtim_s *priv, - uint32_t offset, uint32_t clrbits, - uint32_t setbits); -#endif -static void hrtim_tim_putreg(struct stm32_hrtim_s *priv, uint8_t timer, - uint32_t offset, uint32_t value); -static void hrtim_tim_modifyreg(struct stm32_hrtim_s *priv, - uint8_t timer, uint32_t offset, - uint32_t clrbits, uint32_t setbits); - -#ifdef CONFIG_DEBUG_TIMER_INFO -static void hrtim_dumpregs(struct stm32_hrtim_s *priv, uint8_t timer, - const char *msg); -#else -# define hrtim_dumpregs(priv, timer, msg) -#endif - -/* HRTIM helper */ - -static uint32_t hrtim_tim_getreg(struct stm32_hrtim_s *priv, - uint8_t timer, uint32_t offset); -static struct stm32_hrtim_tim_s * - hrtim_tim_get(struct stm32_hrtim_s *priv, - uint8_t timer); -#if defined(CONFIG_STM32_HRTIM_PWM) || defined(CONFIG_STM32_HRTIM_FAULTS) -static struct stm32_hrtim_slave_priv_s * - hrtim_slave_get(struct stm32_hrtim_s *priv, uint8_t timer); -#endif -static uint32_t hrtim_base_get(struct stm32_hrtim_s *priv, - uint8_t timer); - -/* Configuration */ - -static int hrtim_dll_cal(struct stm32_hrtim_s *priv); -static int hrtim_tim_clock_config(struct stm32_hrtim_s *priv, - uint8_t timer, uint8_t pre); -static int hrtim_tim_clocks_config(struct stm32_hrtim_s *priv); -#if defined(CONFIG_STM32_HRTIM_PWM) || defined(CONFIG_STM32_HRTIM_SYNC) -static int hrtim_gpios_config(struct stm32_hrtim_s *priv); -#endif -#if defined(CONFIG_STM32_HRTIM_CAPTURE) -static int hrtim_capture_config(struct stm32_hrtim_s *priv); -static uint16_t hrtim_capture_get(struct hrtim_dev_s *dev, uint8_t timer, - uint8_t index); -static int hrtim_soft_capture(struct hrtim_dev_s *dev, uint8_t timer, - uint8_t index); -#endif -#if defined(CONFIG_STM32_HRTIM_SYNC) -static int hrtim_synch_config(struct stm32_hrtim_s *priv); -#endif -#if defined(CONFIG_STM32_HRTIM_PWM) -static int hrtim_outputs_config(struct stm32_hrtim_s *priv); -static int hrtim_outputs_enable(struct hrtim_dev_s *dev, - uint16_t outputs, bool state); -static int hrtim_output_set_set(struct hrtim_dev_s *dev, uint16_t output, - uint32_t set); -static int hrtim_output_rst_set(struct hrtim_dev_s *dev, uint16_t output, - uint32_t rst); -#endif -#ifdef HRTIM_HAVE_ADC -static int hrtim_adc_config(struct stm32_hrtim_s *priv); -#endif -#ifdef CONFIG_STM32_HRTIM_DAC -static int hrtim_dac_config(struct stm32_hrtim_s *priv); -#endif -#ifdef CONFIG_STM32_HRTIM_DMA -static int hrtim_dma_cfg(struct stm32_hrtim_s *priv); -static int hrtim_tim_dma_cfg(struct stm32_hrtim_s *priv, uint8_t timer, - uint16_t dma); -#endif -#ifdef CONFIG_STM32_HRTIM_DEADTIME -static int hrtim_deadtime_update(struct hrtim_dev_s *dev, uint8_t timer, - uint8_t dt, uint16_t value); -static uint16_t hrtim_deadtime_get(struct hrtim_dev_s *dev, - uint8_t timer, uint8_t dt); -static int hrtim_tim_deadtime_cfg(struct stm32_hrtim_s *priv, - uint8_t timer); -static int hrtim_deadtime_config(struct stm32_hrtim_s *priv); -#endif -#ifdef CONFIG_STM32_HRTIM_CHOPPER -static int hrtim_chopper_enable(struct hrtim_dev_s *dev, uint8_t timer, - uint8_t chan, bool state); -static int hrtim_tim_chopper_cfg(struct stm32_hrtim_s *priv, - uint8_t timer); -static int hrtim_chopper_config(struct stm32_hrtim_s *priv); -#endif -#ifdef CONFIG_STM32_HRTIM_BURST -static int hrtim_burst_enable(struct hrtim_dev_s *dev, bool state); -static int hrtim_burst_cmp_update(struct hrtim_dev_s *dev, uint16_t cmp); -static int hrtim_burst_per_update(struct hrtim_dev_s *dev, uint16_t per); -static uint16_t hrtim_burst_cmp_get(struct hrtim_dev_s *dev); -static uint16_t hrtim_burst_per_get(struct hrtim_dev_s *dev); -static int hrtim_burst_pre_update(struct hrtim_dev_s *dev, uint8_t pre); -static int hrtim_burst_pre_get(struct hrtim_dev_s *dev); -static int hrtim_burst_config(struct stm32_hrtim_s *priv); -#endif -#ifdef CONFIG_STM32_HRTIM_FAULTS -static int hrtim_faults_config(struct stm32_hrtim_s *priv); -static int hrtim_flt_cfg(struct stm32_hrtim_s *priv, uint8_t index); -static int hrtim_tim_faults_cfg(struct stm32_hrtim_s *priv, - uint8_t timer); -#endif -#ifdef CONFIG_STM32_HRTIM_EVENTS -static int hrtim_events_config(struct stm32_hrtim_s *priv); -static int hrtim_eev_cfg(struct stm32_hrtim_s *priv, uint8_t index); -#endif -#ifdef CONFIG_STM32_HRTIM_INTERRUPTS -static int hrtim_irq_config(struct stm32_hrtim_s *priv); -static uint16_t hrtim_irq_get(struct hrtim_dev_s *dev, uint8_t timer); -static int hrtim_irq_ack(struct hrtim_dev_s *dev, uint8_t timer, - int source); -#endif -static int hrtim_cmp_update(struct hrtim_dev_s *dev, uint8_t timer, - uint8_t index, uint16_t cmp); -static int hrtim_per_update(struct hrtim_dev_s *dev, uint8_t timer, - uint16_t per); -static int hrtim_rep_update(struct hrtim_dev_s *dev, uint8_t timer, - uint8_t rep); -static uint16_t hrtim_per_get(struct hrtim_dev_s *dev, uint8_t timer); -static uint16_t hrtim_cmp_get(struct hrtim_dev_s *dev, uint8_t timer, - uint8_t index); -static uint64_t hrtim_fclk_get(struct hrtim_dev_s *dev, uint8_t timer); -static int hrtim_soft_update(struct hrtim_dev_s *dev, uint8_t timer); -static int hrtim_soft_reset(struct hrtim_dev_s *dev, uint8_t timer); -static int hrtim_tim_freq_set(struct hrtim_dev_s *dev, uint8_t timer, - uint64_t freq); -static int hrtim_tim_enable(struct hrtim_dev_s *dev, uint8_t timers, - bool state); -static int hrtim_tim_reset_set(struct stm32_hrtim_s *priv, - uint8_t timer, uint64_t reset); -static int hrtim_reset_config(struct stm32_hrtim_s *priv); -static int hrtim_tim_update_set(struct stm32_hrtim_s *priv, - uint8_t timer, - uint16_t update); -static int hrtim_update_config(struct stm32_hrtim_s *priv); - -static void hrtim_tim_mode_set(struct stm32_hrtim_s *priv, uint8_t timer, - uint8_t mode); -static void hrtim_mode_config(struct stm32_hrtim_s *priv); - -/* Initialization */ - -static int stm32_hrtimconfig(struct stm32_hrtim_s *priv); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -#ifndef CONFIG_STM32_HRTIM_DISABLE_CHARDRV -static const struct file_operations g_hrtim_fops = -{ - stm32_hrtim_open, /* open */ - stm32_hrtim_close, /* close */ - NULL, /* read */ - NULL, /* write */ - NULL, /* seek */ - stm32_hrtim_ioctl, /* ioctl */ -}; -#endif /* CONFIG_STM32_HRTIM_DISABLE_CHARDRV */ - -/* Master Timer data */ - -static struct stm32_hrtim_tim_s g_master = -{ - .tim = - { - .base = STM32_HRTIM1_MASTER_BASE, - - /* If MASTER is disabled, we need only MASTER base */ - -#ifdef CONFIG_STM32_HRTIM_MASTER - .fclk = HRTIM_CLOCK / (1 << HRTIM_MASTER_PRESCALER), - .prescaler = HRTIM_MASTER_PRESCALER, - .mode = HRTIM_MASTER_MODE, -# ifdef CONFIG_STM32_HRTIM_MASTER_DAC - .dac = HRTIM_MASTER_DAC, -# endif -# ifdef CONFIG_STM32_HRTIM_MASTER_IRQ - .irq = HRTIM_MASTER_IRQ -# endif -# ifdef CONFIG_STM32_HRTIM_MASTER_DMA - .dma = HRTIM_MASTER_DMA -# endif -#endif - }, - .priv = NULL, -}; - -#ifdef CONFIG_STM32_HRTIM_TIMA - -/* Timer A private data */ - -static struct stm32_hrtim_slave_priv_s g_tima_priv = -{ - .update = HRTIM_TIMA_UPDATE, - .reset = HRTIM_TIMA_RESET, -#ifdef CONFIG_STM32_HRTIM_TIMA_PWM - .pwm = - { -#ifdef CONFIG_STM32_HRTIM_TIMA_PSHPLL - .pushpull = 1, -#endif -#ifdef CONFIG_STM32_HRTIM_TIMA_PWM_CH1 - .ch1 = - { - .set = HRTIM_TIMA_CH1_SET, - .rst = HRTIM_TIMA_CH1_RST, - .pol = HRTIM_TIMA_CH1_POL - }, -#endif -#ifdef CONFIG_STM32_HRTIM_TIMA_PWM_CH2 - .ch2 = - { - .set = HRTIM_TIMA_CH2_SET, - .rst = HRTIM_TIMA_CH2_RST, - .pol = HRTIM_TIMA_CH2_POL - }, -#endif -#ifdef CONFIG_STM32_HRTIM_TIMA_BURST - .burst = - { -# ifdef CONFIG_STM32_HRTIM_TIMA_BURST_CH1 - .ch1_en = 1, - .ch1_state = HRTIM_TIMA_CH1_IDLE_STATE, -# else - .ch1_en = 0, -# endif -# ifdef CONFIG_STM32_HRTIM_TIMA_BURST_CH2 - .ch2_en = 1, - .ch2_state = HRTIM_TIMA_CH2_IDLE_STATE -# else - .ch2_en = 0, -# endif - }, -#endif -#ifdef CONFIG_STM32_HRTIM_TIMA_CHOP - .chp = - { - .start_pulse = HRTIM_TIMA_CHOP_START, - .duty = HRTIM_TIMA_CHOP_DUTY, - .freq = HRTIM_TIMA_CHOP_FREQ - }, -#endif -#ifdef CONFIG_STM32_HRTIM_TIMA_DT - .dt = - { - .en = 1, - .fsign_lock = HRTIM_TIMA_DT_FSLOCK, - .rsign_lock = HRTIM_TIMA_DT_RSLOCK, - .falling_lock = HRTIM_TIMA_DT_FVLOCK, - .rising_lock = HRTIM_TIMA_DT_RVLOCK, - .fsign = HRTIM_TIMA_DT_FSIGN, - .rsign = HRTIM_TIMA_DT_RSIGN, - .prescaler = HRTIM_TIMA_DT_PRESCALER - } -#endif - }, -#endif -#ifdef CONFIG_STM32_HRTIM_TIMA_CAP - .cap = - { - .cap1 = HRTIM_TIMA_CAPTURE1, - .cap2 = HRTIM_TIMA_CAPTURE2, - } -#endif -}; - -/* Timer A data */ - -static struct stm32_hrtim_tim_s g_tima = -{ - .tim = - { - .base = STM32_HRTIM1_TIMERA_BASE, - .fclk = HRTIM_CLOCK / (1 << HRTIM_TIMA_PRESCALER), - .prescaler = HRTIM_TIMA_PRESCALER, - .mode = HRTIM_TIMA_MODE, -#ifdef CONFIG_STM32_HRTIM_TIMA_DAC - .dac = HRTIM_TIMA_DAC, -#endif -#ifdef CONFIG_STM32_HRTIM_TIMA_IRQ - .irq = HRTIM_TIMA_IRQ, -#endif -#ifdef CONFIG_STM32_HRTIM_TIMA_DMA - .dma = HRTIM_TIMA_DMA -#endif - }, - .priv = &g_tima_priv -}; -#endif - -#ifdef CONFIG_STM32_HRTIM_TIMB -/* Timer B private data */ - -static struct stm32_hrtim_slave_priv_s g_timb_priv = -{ - .update = HRTIM_TIMB_UPDATE, - .reset = HRTIM_TIMB_RESET, -#ifdef CONFIG_STM32_HRTIM_TIMB_PWM - .pwm = - { -#ifdef CONFIG_STM32_HRTIM_TIMB_PSHPLL - .pushpull = 1, -#endif -#ifdef CONFIG_STM32_HRTIM_TIMB_PWM_CH1 - .ch1 = - { - .set = HRTIM_TIMB_CH1_SET, - .rst = HRTIM_TIMB_CH1_RST, - .pol = HRTIM_TIMB_CH1_POL - }, -#endif -#ifdef CONFIG_STM32_HRTIM_TIMB_PWM_CH2 - .ch2 = - { - .set = HRTIM_TIMB_CH2_SET, - .rst = HRTIM_TIMB_CH2_RST, - .pol = HRTIM_TIMB_CH2_POL - }, -#endif -#ifdef CONFIG_STM32_HRTIM_TIMB_BURST - .burst = - { -# ifdef CONFIG_STM32_HRTIM_TIMB_BURST_CH1 - .ch1_en = 1, - .ch1_state = HRTIM_TIMB_CH1_IDLE_STATE, -# else - .ch1_en = 0, -# endif -# ifdef CONFIG_STM32_HRTIM_TIMB_BURST_CH2 - .ch2_en = 1, - .ch2_state = HRTIM_TIMB_CH2_IDLE_STATE -# else - .ch2_en = 0, -# endif - }, -#endif -#ifdef CONFIG_STM32_HRTIM_TIMB_CHOP - .chp = - { - .start_pulse = HRTIM_TIMB_CHOP_START, - .duty = HRTIM_TIMB_CHOP_DUTY, - .freq = HRTIM_TIMB_CHOP_FREQ - }, -#endif -#ifdef CONFIG_STM32_HRTIM_TIMB_DT - .dt = - { - .en = 1, - .fsign_lock = HRTIM_TIMB_DT_FSLOCK, - .rsign_lock = HRTIM_TIMB_DT_RSLOCK, - .falling_lock = HRTIM_TIMB_DT_FVLOCK, - .rising_lock = HRTIM_TIMB_DT_RVLOCK, - .fsign = HRTIM_TIMB_DT_FSIGN, - .rsign = HRTIM_TIMB_DT_RSIGN, - .prescaler = HRTIM_TIMB_DT_PRESCALER - } -#endif - }, -#endif -#ifdef CONFIG_STM32_HRTIM_TIMB_CAP - .cap = - { - .cap1 = HRTIM_TIMB_CAPTURE1, - .cap2 = HRTIM_TIMB_CAPTURE2, - } -#endif -}; - -/* Timer B data */ - -static struct stm32_hrtim_tim_s g_timb = -{ - .tim = - { - .base = STM32_HRTIM1_TIMERB_BASE, - .fclk = HRTIM_CLOCK / (1 << HRTIM_TIMB_PRESCALER), - .prescaler = HRTIM_TIMB_PRESCALER, - .mode = HRTIM_TIMB_MODE, -#ifdef CONFIG_STM32_HRTIM_TIMB_DAC - .dac = HRTIM_TIMB_DAC, -#endif -#ifdef CONFIG_STM32_HRTIM_TIMB_IRQ - .irq = HRTIM_TIMB_IRQ, -#endif -#ifdef CONFIG_STM32_HRTIM_TIMB_DMA - .dma = HRTIM_TIMB_DMA -#endif - }, - .priv = &g_timb_priv -}; -#endif - -#ifdef CONFIG_STM32_HRTIM_TIMC -/* Timer C private data */ - -static struct stm32_hrtim_slave_priv_s g_timc_priv = -{ - .update = HRTIM_TIMC_UPDATE, - .reset = HRTIM_TIMC_RESET, -#ifdef CONFIG_STM32_HRTIM_TIMC_PWM - .pwm = - { -#ifdef CONFIG_STM32_HRTIM_TIMC_PSHPLL - .pushpull = 1, -#endif -#ifdef CONFIG_STM32_HRTIM_TIMC_PWM_CH1 - .ch1 = - { - .set = HRTIM_TIMC_CH1_SET, - .rst = HRTIM_TIMC_CH1_RST, - .pol = HRTIM_TIMC_CH1_POL - }, -#endif -#ifdef CONFIG_STM32_HRTIM_TIMC_PWM_CH2 - .ch2 = - { - .set = HRTIM_TIMC_CH2_SET, - .rst = HRTIM_TIMC_CH2_RST, - .pol = HRTIM_TIMC_CH2_POL - }, -#endif -#ifdef CONFIG_STM32_HRTIM_TIMC_BURST - .burst = - { -# ifdef CONFIG_STM32_HRTIM_TIMC_BURST_CH1 - .ch1_en = 1, - .ch1_state = HRTIM_TIMC_CH1_IDLE_STATE, -# else - .ch1_en = 0, -# endif -# ifdef CONFIG_STM32_HRTIM_TIMC_BURST_CH2 - .ch2_en = 1, - .ch2_state = HRTIM_TIMC_CH2_IDLE_STATE -# else - .ch2_en = 0, -# endif - }, -#endif -#ifdef CONFIG_STM32_HRTIM_TIMC_CHOP - .chp = - { - .start_pulse = HRTIM_TIMC_CHOP_START, - .duty = HRTIM_TIMC_CHOP_DUTY, - .freq = HRTIM_TIMC_CHOP_FREQ - }, -#endif -#ifdef CONFIG_STM32_HRTIM_TIMC_DT - .dt = - { - .en = 1, - .fsign_lock = HRTIM_TIMC_DT_FSLOCK, - .rsign_lock = HRTIM_TIMC_DT_RSLOCK, - .falling_lock = HRTIM_TIMC_DT_FVLOCK, - .rising_lock = HRTIM_TIMC_DT_RVLOCK, - .fsign = HRTIM_TIMC_DT_FSIGN, - .rsign = HRTIM_TIMC_DT_RSIGN, - .prescaler = HRTIM_TIMC_DT_PRESCALER - } -#endif - }, -#endif -#ifdef CONFIG_STM32_HRTIM_TIMC_CAP - .cap = - { - .cap1 = HRTIM_TIMC_CAPTURE1, - .cap2 = HRTIM_TIMC_CAPTURE2, - } -#endif -}; - -/* Timer C data */ - -static struct stm32_hrtim_tim_s g_timc = -{ - .tim = - { - .base = STM32_HRTIM1_TIMERC_BASE, - .fclk = HRTIM_CLOCK / (1 << HRTIM_TIMC_PRESCALER), - .prescaler = HRTIM_TIMC_PRESCALER, - .mode = HRTIM_TIMC_MODE, -#ifdef CONFIG_STM32_HRTIM_TIMC_DAC - .dac = HRTIM_TIMC_DAC, -#endif -#ifdef CONFIG_STM32_HRTIM_TIMC_IRQ - .irq = HRTIM_TIMC_IRQ, -#endif -#ifdef CONFIG_STM32_HRTIM_TIMC_DMA - .dma = HRTIM_TIMC_DMA -#endif - }, - .priv = &g_timc_priv -}; -#endif - -#ifdef CONFIG_STM32_HRTIM_TIMD -/* Timer D private data */ - -static struct stm32_hrtim_slave_priv_s g_timd_priv = -{ - .update = HRTIM_TIMD_UPDATE, - .reset = HRTIM_TIMD_RESET, -#ifdef CONFIG_STM32_HRTIM_TIMD_PWM - .pwm = - { -#ifdef CONFIG_STM32_HRTIM_TIMD_PSHPLL - .pushpull = 1, -#endif -#ifdef CONFIG_STM32_HRTIM_TIMD_PWM_CH1 - .ch1 = - { - .set = HRTIM_TIMD_CH1_SET, - .rst = HRTIM_TIMD_CH1_RST, - .pol = HRTIM_TIMD_CH1_POL - }, -#endif -#ifdef CONFIG_STM32_HRTIM_TIMD_PWM_CH2 - .ch2 = - { - .set = HRTIM_TIMD_CH2_SET, - .rst = HRTIM_TIMD_CH2_RST, - .pol = HRTIM_TIMD_CH2_POL - }, -#endif -#ifdef CONFIG_STM32_HRTIM_TIMD_BURST - .burst = - { -# ifdef CONFIG_STM32_HRTIM_TIMD_BURST_CH1 - .ch1_en = 1, - .ch1_state = HRTIM_TIMD_CH1_IDLE_STATE, -# else - .ch1_en = 0, -# endif -# ifdef CONFIG_STM32_HRTIM_TIMD_BURST_CH2 - .ch2_en = 1, - .ch2_state = HRTIM_TIMD_CH2_IDLE_STATE -# else - .ch2_en = 0, -# endif - }, -#endif -#ifdef CONFIG_STM32_HRTIM_TIMD_CHOP - .chp = - { - .start_pulse = HRTIM_TIMD_CHOP_START, - .duty = HRTIM_TIMD_CHOP_DUTY, - .freq = HRTIM_TIMD_CHOP_FREQ - }, -#endif -#ifdef CONFIG_STM32_HRTIM_TIMD_DT - .dt = - { - .en = 1, - .fsign_lock = HRTIM_TIMD_DT_FSLOCK, - .rsign_lock = HRTIM_TIMD_DT_RSLOCK, - .falling_lock = HRTIM_TIMD_DT_FVLOCK, - .rising_lock = HRTIM_TIMD_DT_RVLOCK, - .fsign = HRTIM_TIMD_DT_FSIGN, - .rsign = HRTIM_TIMD_DT_RSIGN, - .prescaler = HRTIM_TIMD_DT_PRESCALER - } -#endif - }, -#endif -#ifdef CONFIG_STM32_HRTIM_TIMD_CAP - .cap = - { - .cap1 = HRTIM_TIMD_CAPTURE1, - .cap2 = HRTIM_TIMD_CAPTURE2, - } -#endif -}; - -/* Timer D data */ - -static struct stm32_hrtim_tim_s g_timd = -{ - .tim = - { - .base = STM32_HRTIM1_TIMERD_BASE, - .fclk = HRTIM_CLOCK / (1 << HRTIM_TIMD_PRESCALER), - .prescaler = HRTIM_TIMD_PRESCALER, - .mode = HRTIM_TIMD_MODE, -#ifdef CONFIG_STM32_HRTIM_TIMD_DAC - .dac = HRTIM_TIMD_DAC, -#endif -#ifdef CONFIG_STM32_HRTIM_TIMD_IRQ - .irq = HRTIM_TIMD_IRQ, -#endif -#ifdef CONFIG_STM32_HRTIM_TIMD_DMA - .dma = HRTIM_TIMD_DMA -#endif - }, - .priv = &g_timd_priv -}; -#endif - -#ifdef CONFIG_STM32_HRTIM_TIME -/* Timer E private data */ - -static struct stm32_hrtim_slave_priv_s g_time_priv = -{ - .update = HRTIM_TIME_UPDATE, - .reset = HRTIM_TIME_RESET, -#ifdef CONFIG_STM32_HRTIM_TIME_PWM - .pwm = - { -#ifdef CONFIG_STM32_HRTIM_TIME_PSHPLL - .pushpull = 1, -#endif -#ifdef CONFIG_STM32_HRTIM_TIME_PWM_CH1 - .ch1 = - { - .set = HRTIM_TIME_CH1_SET, - .rst = HRTIM_TIME_CH1_RST, - .pol = HRTIM_TIME_CH1_POL - }, -#endif -#ifdef CONFIG_STM32_HRTIM_TIME_PWM_CH2 - .ch2 = - { - .set = HRTIM_TIME_CH2_SET, - .rst = HRTIM_TIME_CH2_RST, - .pol = HRTIM_TIME_CH1_POL - }, -#endif -#ifdef CONFIG_STM32_HRTIM_TIME_BURST - .burst = - { -# ifdef CONFIG_STM32_HRTIM_TIME_BURST_CH1 - .ch1_en = 1, - .ch1_state = HRTIM_TIME_CH1_IDLE_STATE, -# else - .ch1_en = 0, -# endif -# ifdef CONFIG_STM32_HRTIM_TIME_BURST_CH2 - .ch2_en = 1, - .ch2_state = HRTIM_TIME_CH2_IDLE_STATE -# else - .ch2_en = 0, -# endif - }, -#endif -#ifdef CONFIG_STM32_HRTIM_TIME_CHOP - .chp = - { - .start_pulse = HRTIM_TIME_CHOP_START, - .duty = HRTIM_TIME_CHOP_DUTY, - .freq = HRTIM_TIME_CHOP_FREQ - }, -#endif -#ifdef CONFIG_STM32_HRTIM_TIME_DT - .dt = - { - .en = 1, - .fsign_lock = HRTIM_TIME_DT_FSLOCK, - .rsign_lock = HRTIM_TIME_DT_RSLOCK, - .falling_lock = HRTIM_TIME_DT_FVLOCK, - .rising_lock = HRTIM_TIME_DT_RVLOCK, - .fsign = HRTIM_TIME_DT_FSIGN, - .rsign = HRTIM_TIME_DT_RSIGN, - .prescaler = HRTIM_TIME_DT_PRESCALER - } -#endif - }, -#endif -#ifdef CONFIG_STM32_HRTIM_TIME_CAP - .cap = - { - .cap1 = HRTIM_TIME_CAPTURE1, - .cap2 = HRTIM_TIME_CAPTURE2, - } -#endif -}; - -/* Timer E data */ - -static struct stm32_hrtim_tim_s g_time = -{ - .tim = - { - .base = STM32_HRTIM1_TIMERE_BASE, - .fclk = HRTIM_CLOCK / (1 << HRTIM_TIME_PRESCALER), - .prescaler = HRTIM_TIME_PRESCALER, - .mode = HRTIM_TIME_MODE, -#ifdef CONFIG_STM32_HRTIM_TIME_DAC - .dac = HRTIM_TIME_DAC, -#endif -#ifdef CONFIG_STM32_HRTIM_TIME_IRQ - .irq = HRTIM_TIME_IRQ, -#endif -#ifdef CONFIG_STM32_HRTIM_TIME_DMA - .dma = HRTIM_TIME_DMA -#endif - }, - .priv = &g_time_priv -}; -#endif - -/* Faults data */ - -#ifdef CONFIG_STM32_HRTIM_FAULTS -struct stm32_hrtim_faults_s g_flt = -{ -#ifdef CONFIG_STM32_HRTIM_FAULT1 - .flt1 = - { - .pol = HRTIM_FAULT1_POL, - .src = HRTIM_FAULT1_SRC, - .filter = HRTIM_FAULT1_FILTER, - .lock = HRTIM_FAULT1_LOCK, - }, -#endif -#ifdef CONFIG_STM32_HRTIM_FAULT2 - .flt2 = - { - .pol = HRTIM_FAULT2_POL, - .src = HRTIM_FAULT2_SRC, - .filter = HRTIM_FAULT2_FILTER, - .lock = HRTIM_FAULT2_LOCK, - }, -#endif -#ifdef CONFIG_STM32_HRTIM_FAULT3 - .flt3 = - { - .pol = HRTIM_FAULT3_POL, - .src = HRTIM_FAULT3_SRC, - .filter = HRTIM_FAULT3_FILTER, - .lock = HRTIM_FAULT3_LOCK, - }, -#endif -#ifdef CONFIG_STM32_HRTIM_FAULT4 - .flt2 = - { - .pol = HRTIM_FAULT4_POL, - .src = HRTIM_FAULT4_SRC, - .filter = HRTIM_FAULT4_FILTER, - .lock = HRTIM_FAULT4_LOCK, - }, -#endif -#ifdef CONFIG_STM32_HRTIM_FAULT5 - .flt2 = - { - .pol = HRTIM_FAULT5_POL, - .src = HRTIM_FAULT5_SRC, - .filter = HRTIM_FAULT5_FILTER, - .lock = HRTIM_FAULT5_LOCK, - }, -#endif -}; -#endif - -/* External Events data */ - -#ifdef CONFIG_STM32_HRTIM_EVENTS -struct stm32_hrtim_eev_s g_eev = -{ -#ifdef CONFIG_STM32_HRTIM_EEV1 - .eev1 = - { - .filter = HRTIM_EEV1_FILTER, - .src = HRTIM_EEV1_SRC, - .pol = HRTIM_EEV1_POL, - .sen = HRTIM_EEV1_SEN, - .mode = HRTIM_EEV1_MODE, - } -#endif -#ifdef CONFIG_STM32_HRTIM_EEV2 - .eev2 = - { - .filter = HRTIM_EEV2_FILTER, - .src = HRTIM_EEV2_SRC, - .pol = HRTIM_EEV2_POL, - .sen = HRTIM_EEV2_SEN, - .mode = HRTIM_EEV2_MODE, - } -#endif -#ifdef CONFIG_STM32_HRTIM_EEV3 - .eev3 = - { - .filter = HRTIM_EEV3_FILTER, - .src = HRTIM_EEV3_SRC, - .pol = HRTIM_EEV3_POL, - .sen = HRTIM_EEV3_SEN, - .mode = HRTIM_EEV3_MODE, - } -#endif -#ifdef CONFIG_STM32_HRTIM_EEV4 - .eev4 = - { - .filter = HRTIM_EEV4_FILTER, - .src = HRTIM_EEV4_SRC, - .pol = HRTIM_EEV4_POL, - .sen = HRTIM_EEV4_SEN, - .mode = HRTIM_EEV4_MODE, - } -#endif -#ifdef CONFIG_STM32_HRTIM_EEV5 - .eev5 = - { - .filter = HRTIM_EEV5_FILTER, - .src = HRTIM_EEV5_SRC, - .pol = HRTIM_EEV5_POL, - .sen = HRTIM_EEV5_SEN, - .mode = HRTIM_EEV5_MODE, - } -#endif -#ifdef CONFIG_STM32_HRTIM_EEV6 - .eev6 = - { - .filter = HRTIM_EEV6_FILTER, - .src = HRTIM_EEV6_SRC, - .pol = HRTIM_EEV6_POL, - .sen = HRTIM_EEV6_SEN, - .mode = HRTIM_EEV6_MODE, - } -#endif -#ifdef CONFIG_STM32_HRTIM_EEV7 - .eev7 = - { - .filter = HRTIM_EEV7_FILTER, - .src = HRTIM_EEV7_SRC, - .pol = HRTIM_EEV7_POL, - .sen = HRTIM_EEV7_SEN, - .mode = HRTIM_EEV7_MODE, - } -#endif -#ifdef CONFIG_STM32_HRTIM_EEV8 - .eev8 = - { - .filter = HRTIM_EEV8_FILTER, - .src = HRTIM_EEV8_SRC, - .pol = HRTIM_EEV8_POL, - .sen = HRTIM_EEV8_SEN, - .mode = HRTIM_EEV8_MODE, - } -#endif -#ifdef CONFIG_STM32_HRTIM_EEV9 - .eev9 = - { - .filter = HRTIM_EEV9_FILTER, - .src = HRTIM_EEV9_SRC, - .pol = HRTIM_EEV9_POL, - .sen = HRTIM_EEV9_SEN, - .mode = HRTIM_EEV9_MODE, - } -#endif -#ifdef CONFIG_STM32_HRTIM_EEV10 - .eev10 = - { - .filter = HRTIM_EEV10_FILTER, - .src = HRTIM_EEV10_SRC, - .pol = HRTIM_EEV10_POL, - .sen = HRTIM_EEV10_SEN, - .mode = HRTIM_EEV10_MODE, - } -#endif -}; -#endif - -/* ADC triggering data */ - -#ifdef HRTIM_HAVE_ADC -struct stm32_hrtim_adc_s g_adc = -{ -#ifdef HRTIM_HAVE_ADC_TRG1 - .trg1 = HRTIM_ADC_TRG1, -#endif -#ifdef HRTIM_HAVE_ADC_TRG2 - .trg2 = HRTIM_ADC_TRG2, -#endif -#ifdef HRTIM_HAVE_ADC_TRG3 - .trg3 = HRTIM_ADC_TRG3, -#endif -#ifdef HRTIM_HAVE_ADC_TRG4 - .trg4 = HRTIM_ADC_TRG4 -#endif -}; -#endif - -/* Burst mode data */ - -#ifdef CONFIG_STM32_HRTIM_BURST -struct stm32_hrtim_burst_s g_burst = -{ - .clk = HRTIM_BURST_CLOCK, - .presc = HRTIM_BURST_PRESCALER, - .trg = HRTIM_BURST_TRIGGERS -}; -#endif - -/* HRTIM1 private data */ - -static struct stm32_hrtim_s g_hrtim1priv = -{ - .master = &g_master, - .base = STM32_HRTIM1_BASE, -#ifdef CONFIG_STM32_HRTIM_TIMA - .tima = &g_tima, -#endif -#ifdef CONFIG_STM32_HRTIM_TIMB - .timb = &g_timb, -#endif -#ifdef CONFIG_STM32_HRTIM_TIMC - .timc = &g_timc, -#endif -#ifdef CONFIG_STM32_HRTIM_TIMD - .timd = &g_timd, -#endif -#ifdef CONFIG_STM32_HRTIM_TIME - .time = &g_time, -#endif -#ifdef CONFIG_STM32_HRTIM_FAULTS - .flt = &g_flt, -#endif -#ifdef CONFIG_STM32_HRTIM_EVENTS - .eev = &g_eev, -#endif -#ifdef HRTIM_HAVE_ADC - .adc = &g_adc, -#endif -#ifdef CONFIG_STM32_HRTIM_BURST - .burst = &g_burst, -#endif -#ifdef CONFIG_STM32_HRTIM_COMMON_IRQ - .irq = HRTIM_IRQ_COMMON, -#endif -}; - -/* HRTIM interface */ - -static const struct stm32_hrtim_ops_s g_hrtim1ops = -{ - .cmp_update = hrtim_cmp_update, - .per_update = hrtim_per_update, - .rep_update = hrtim_rep_update, - .per_get = hrtim_per_get, - .cmp_get = hrtim_cmp_get, - .fclk_get = hrtim_fclk_get, - .soft_update = hrtim_soft_update, - .soft_reset = hrtim_soft_reset, - .freq_set = hrtim_tim_freq_set, - .tim_enable = hrtim_tim_enable, -#ifdef CONFIG_STM32_HRTIM_INTERRUPTS - .irq_ack = hrtim_irq_ack, - .irq_get = hrtim_irq_get, -#endif -#ifdef CONFIG_STM32_HRTIM_PWM - .outputs_enable = hrtim_outputs_enable, - .output_rst_set = hrtim_output_rst_set, - .output_set_set = hrtim_output_set_set, -#endif -#ifdef CONFIG_STM32_HRTIM_BURST - .burst_enable = hrtim_burst_enable, - .burst_cmp_set = hrtim_burst_cmp_update, - .burst_per_set = hrtim_burst_per_update, - .burst_pre_set = hrtim_burst_pre_update, - .burst_cmp_get = hrtim_burst_cmp_get, - .burst_per_get = hrtim_burst_per_get, - .burst_pre_get = hrtim_burst_pre_get, -#endif -#ifdef CONFIG_STM32_HRTIM_CHOPPER - .chopper_enable = hrtim_chopper_enable, -#endif -#ifdef CONFIG_STM32_HRTIM_DEADTIME - .deadtime_update = hrtim_deadtime_update, - .deadtime_get = hrtim_deadtime_get, -#endif -#ifdef CONFIG_STM32_HRTIM_CAPTURE - .capture_get = hrtim_capture_get, - .soft_capture = hrtim_soft_capture, -#endif -}; - -/* HRTIM device structure */ - -struct hrtim_dev_s g_hrtim1dev = -{ - .hd_ops = &g_hrtim1ops, - .hd_priv = &g_hrtim1priv, - .initialized = false, -}; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -#ifndef CONFIG_STM32_HRTIM_DISABLE_CHARDRV - -/**************************************************************************** - * Name: stm32_hrtim_open - * - * Description: - * This function is called whenever the HRTIM device is opened. - * - ****************************************************************************/ - -static int stm32_hrtim_open(struct file *filep) -{ -#warning "stm32_hrtim_open: missing logic" - return OK; -} - -/**************************************************************************** - * Name: stm32_hrtim_close - * - * Description: - * This function is called when the HRTIM device is closed. - * - ****************************************************************************/ - -static int stm32_hrtim_close(struct file *filep) -{ -#warning "smt32_hrtim_close: missing logic" - return OK; -} - -/**************************************************************************** - * Name: stm32_hrtim_ioctl - * - * Description: - * The standard ioctl method. This is where ALL of the HRTIM work is done. - * - ****************************************************************************/ - -static int stm32_hrtim_ioctl(struct file *filep, int cmd, - unsigned long arg) -{ - struct inode *inode = filep->f_inode; - struct hrtim_dev_s *dev; - struct stm32_hrtim_s *hrtim; - int ret; - - tmrinfo("cmd: %d arg: %ld\n", cmd, arg); - dev = inode->i_private; - DEBUGASSERT(dev != NULL); - hrtim = dev->hd_priv; - - UNUSED(hrtim); - -#warning "smt32_hrtim_ioctl: missing logic" - - /* Handle HRTIM ioctl commands */ - - switch (cmd) - { - default: - { - ret = -ENOTTY; - break; - } - } - - return ret; -} - -#endif /* CONFIG_STM32_HRTIM_DISABLE_CHARDRV */ - -/**************************************************************************** - * Name: hrtim_cmn_getreg - * - * Description: - * Read the value of an HRTIM register. - * - * Input Parameters: - * priv - A reference to the HRTIM block - * offset - The offset to the register to read - * - * Returned Value: - * The current contents of the specified register - * - ****************************************************************************/ - -static uint32_t hrtim_cmn_getreg(struct stm32_hrtim_s *priv, - uint32_t offset) -{ - return getreg32(priv->base + STM32_HRTIM_CMN_OFFSET + offset); -} - -/**************************************************************************** - * Name: hrtim_cmn_putreg - * - * Description: - * Write a value to an HRTIM register. - * - * Input Parameters: - * priv - A reference to the HRTIM block - * offset - The offset to the register to write to - * value - The value to write to the register - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void hrtim_cmn_putreg(struct stm32_hrtim_s *priv, uint32_t offset, - uint32_t value) -{ - putreg32(value, priv->base + STM32_HRTIM_CMN_OFFSET + offset); -} - -/**************************************************************************** - * Name: hrtim__modifyreg - * - * Description: - * Modify the value of an HRTIM register (not atomic). - * - * Input Parameters: - * priv - A reference to the HRTIM block - * offset - The offset to the register to modify - * clrbits - The bits to clear - * setbits - The bits to set - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_HRTIM_BURST -static void hrtim_cmn_modifyreg(struct stm32_hrtim_s *priv, - uint32_t offset, uint32_t clrbits, - uint32_t setbits) -{ - hrtim_cmn_putreg(priv, offset, - (hrtim_cmn_getreg(priv, offset) & ~clrbits) | setbits); -} -#endif - -/**************************************************************************** - * Name: hrtim_tim_get - * - * Description: - * Get Timer data structure for given HRTIM Timer index - * - * Input Parameters: - * priv - A reference to the HRTIM block - * timer - An HRTIM Timer index to get - * - * Returned Value: - * Pointer to timer structure on success, NULL on failure - * - ****************************************************************************/ - -static struct stm32_hrtim_tim_s * -hrtim_tim_get(struct stm32_hrtim_s *priv, uint8_t timer) -{ - struct stm32_hrtim_tim_s *tim; - - switch (timer) - { - case HRTIM_TIMER_MASTER: - { - tim = priv->master; - break; - } - -#ifdef CONFIG_STM32_HRTIM_TIMA - case HRTIM_TIMER_TIMA: - { - tim = priv->tima; - break; - } -#endif - -#ifdef CONFIG_STM32_HRTIM_TIMB - case HRTIM_TIMER_TIMB: - { - tim = priv->timb; - break; - } -#endif - -#ifdef CONFIG_STM32_HRTIM_TIMC - case HRTIM_TIMER_TIMC: - { - tim = priv->timc; - break; - } -#endif - -#ifdef CONFIG_STM32_HRTIM_TIMD - case HRTIM_TIMER_TIMD: - { - tim = priv->timd; - break; - } -#endif - -#ifdef CONFIG_STM32_HRTIM_TIME - case HRTIM_TIMER_TIME: - { - tim = priv->time; - break; - } -#endif - - default: - { - tmrerr("ERROR: No such timer index: %d\n", timer); - tim = NULL; - } - } - - return tim; -} - -/**************************************************************************** - * Name: hrtim_slave_get - * - * Description: - * Get Slave private data structure for given HRTIM Timer index - * - * Input Parameters: - * priv - A reference to the HRTIM block - * timer - An HRTIM Slave Timer index to get - * - * Returned Value: - * Pointer to slave structure success, NULL on failure - * - ****************************************************************************/ - -#if defined(CONFIG_STM32_HRTIM_PWM) || defined(CONFIG_STM32_HRTIM_FAULTS) -static struct stm32_hrtim_slave_priv_s * -hrtim_slave_get(struct stm32_hrtim_s *priv, uint8_t timer) -{ - struct stm32_hrtim_tim_s *tim; - struct stm32_hrtim_slave_priv_s *slave; - - /* Sanity checking */ - - if (timer == HRTIM_TIMER_MASTER || timer == HRTIM_TIMER_COMMON) - { - slave = NULL; - goto errout; - } - - /* Get Timer data structure */ - - tim = hrtim_tim_get(priv, timer); - if (tim == NULL) - { - slave = NULL; - goto errout; - } - - /* Get Slave Timer data */ - - slave = (struct stm32_hrtim_slave_priv_s *)tim->priv; - -errout: - return slave; -} -#endif - -/**************************************************************************** - * Name: hrtim_base_get - * - * Description: - * Get base address offset for given HRTIM Timer index - * - * Input Parameters: - * priv - A reference to the HRTIM block - * timer - An HRTIM Timer index to get - * - * Returned Value: - * Base address offset for given Timer index - * - ****************************************************************************/ - -static uint32_t hrtim_base_get(struct stm32_hrtim_s *priv, uint8_t timer) -{ - struct stm32_hrtim_tim_s *tim; - uint32_t base = 0; - - tim = hrtim_tim_get(priv, timer); - if (tim == NULL) - { - base = 0; - goto errout; - } - - base = tim->tim.base; - -errout: - return base; -} - -/**************************************************************************** - * Name: hrtim_tim_getreg - * - * Description: - * Read the value of an HRTIM Timer register. - * - * Input Parameters: - * priv - A reference to the HRTIM block - * tim - An HRTIM timer index - * offset - The offset to the register to read - * - * Returned Value: - * The current contents of the specified register - * - ****************************************************************************/ - -static uint32_t hrtim_tim_getreg(struct stm32_hrtim_s *priv, - uint8_t timer, uint32_t offset) -{ - uint32_t base = 0; - - base = hrtim_base_get(priv, timer); - if (base < 0) - { - return 0; - } - - return getreg32(base + offset); -} - -/**************************************************************************** - * Name: hrtim_tim_putreg - * - * Description: - * Write a value to an HRTIM Timer register. - * - * Input Parameters: - * priv - A reference to the HRTIM block - * timer - An HRTIM Timer index - * offset - The offset to the register to write to - * value - The value to write to the register - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void hrtim_tim_putreg(struct stm32_hrtim_s *priv, uint8_t timer, - uint32_t offset, uint32_t value) -{ - uint32_t base = 0; - - base = hrtim_base_get(priv, timer); - if (base > 0) - { - putreg32(value, base + offset); - } -} - -/**************************************************************************** - * Name: hrtim_tim_modifyreg - * - * Description: - * Modify the value of an HRTIM Timer register (not atomic). - * - * Input Parameters: - * priv - A reference to the HRTIM block - * timer - An HRTIM Timer index - * offset - The offset to the register to modify - * clrbits - The bits to clear - * setbits - The bits to set - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void hrtim_tim_modifyreg(struct stm32_hrtim_s *priv, - uint8_t timer, uint32_t offset, - uint32_t clrbits, uint32_t setbits) -{ - hrtim_tim_putreg(priv, timer, offset, - (hrtim_tim_getreg(priv, timer, offset) & ~clrbits) | - setbits); -} - -#ifdef CONFIG_DEBUG_TIMER_INFO -static void hrtim_dumpregs(struct stm32_hrtim_s *priv, uint8_t timer, - const char *msg) -{ - tmrinfo("%s:\n", msg); - - switch (timer) - { - case HRTIM_TIMER_MASTER: - { - tmrinfo("\tCR:\t0x%08" PRIx32 "\tISR:\t0x%08" PRIx32 - "\tICR:\t0x%08" PRIx32 "\n", - hrtim_tim_getreg(priv, timer, STM32_HRTIM_TIM_CR_OFFSET), - hrtim_tim_getreg(priv, timer, STM32_HRTIM_TIM_ISR_OFFSET), - hrtim_tim_getreg(priv, timer, STM32_HRTIM_TIM_ICR_OFFSET)); - - tmrinfo("\tDIER:\t0x%08" PRIx32 "\tCNTR:\t0x%08" PRIx32 - "\tPER:\t0x%08" PRIx32 "\n", - hrtim_tim_getreg(priv, timer, STM32_HRTIM_TIM_DIER_OFFSET), - hrtim_tim_getreg(priv, timer, STM32_HRTIM_TIM_CNTR_OFFSET), - hrtim_tim_getreg(priv, timer, STM32_HRTIM_TIM_PER_OFFSET)); - - tmrinfo("\tREP:\t0x%08" PRIx32 "\tCMP1:\t0x%08" PRIx32 - "\tCMP2:\t0x%08" PRIx32 "\n", - hrtim_tim_getreg(priv, timer, STM32_HRTIM_TIM_REPR_OFFSET), - hrtim_tim_getreg(priv, timer, - STM32_HRTIM_TIM_CMP1R_OFFSET), - hrtim_tim_getreg(priv, timer, - STM32_HRTIM_TIM_CMP2R_OFFSET)); - - tmrinfo("\tCMP3:\t0x%08" PRIx32 "\tCMP4:\t0x%08" PRIx32 "\n", - hrtim_tim_getreg(priv, timer, - STM32_HRTIM_TIM_CMP3R_OFFSET), - hrtim_tim_getreg(priv, timer, - STM32_HRTIM_TIM_CMP4R_OFFSET)); - break; - } - -#ifdef CONFIG_STM32_HRTIM_TIMA - case HRTIM_TIMER_TIMA: -#endif -#ifdef CONFIG_STM32_HRTIM_TIMB - case HRTIM_TIMER_TIMB: -#endif -#ifdef CONFIG_STM32_HRTIM_TIMC - case HRTIM_TIMER_TIMC: -#endif -#ifdef CONFIG_STM32_HRTIM_TIMD - case HRTIM_TIMER_TIMD: -#endif -#ifdef CONFIG_STM32_HRTIM_TIME - case HRTIM_TIMER_TIME: -#endif - { - tmrinfo("\tCR:\t0x%08" PRIx32 "\tISR:\t0x%08" PRIx32 - "\tICR:\t0x%08" PRIx32 "\n", - hrtim_tim_getreg(priv, timer, STM32_HRTIM_TIM_CR_OFFSET), - hrtim_tim_getreg(priv, timer, STM32_HRTIM_TIM_ISR_OFFSET), - hrtim_tim_getreg(priv, timer, STM32_HRTIM_TIM_ICR_OFFSET)); - - tmrinfo("\tDIER:\t0x%08" PRIx32 "\tCNTR:\t0x%08" PRIx32 - "\tPER:\t0x%08" PRIx32 "\n", - hrtim_tim_getreg(priv, timer, STM32_HRTIM_TIM_DIER_OFFSET), - hrtim_tim_getreg(priv, timer, STM32_HRTIM_TIM_CNTR_OFFSET), - hrtim_tim_getreg(priv, timer, STM32_HRTIM_TIM_PER_OFFSET)); - - tmrinfo("\tREP:\t0x%08" PRIx32 "\tCMP1:\t0x%08" PRIx32 - "\tCMP1C:\t0x%08" PRIx32 "\n", - hrtim_tim_getreg(priv, timer, STM32_HRTIM_TIM_REPR_OFFSET), - hrtim_tim_getreg(priv, timer, - STM32_HRTIM_TIM_CMP1R_OFFSET), - hrtim_tim_getreg(priv, timer, - STM32_HRTIM_TIM_CMP1CR_OFFSET)); - - tmrinfo("\tCMP2:\t0x%08" PRIx32 "\tCMP3:\t0x%08" PRIx32 - "\tCMP4:\t0x%08" PRIx32 "\n", - hrtim_tim_getreg(priv, timer, - STM32_HRTIM_TIM_CMP2R_OFFSET), - hrtim_tim_getreg(priv, timer, - STM32_HRTIM_TIM_CMP3R_OFFSET), - hrtim_tim_getreg(priv, timer, - STM32_HRTIM_TIM_CMP4R_OFFSET)); - - tmrinfo("\tCPT1:\t0x%08" PRIx32 "\tCPT2:\t0x%08" PRIx32 - "\tDTR:\t0x%08" PRIx32 "\n", - hrtim_tim_getreg(priv, timer, - STM32_HRTIM_TIM_CPT1R_OFFSET), - hrtim_tim_getreg(priv, timer, - STM32_HRTIM_TIM_CPT2R_OFFSET), - hrtim_tim_getreg(priv, timer, STM32_HRTIM_TIM_DTR_OFFSET)); - - tmrinfo("\tSET1:\t0x%08" PRIx32 "\tRST1:\t0x%08" PRIx32 - "\tSET2:\t0x%08" PRIx32 "\n", - hrtim_tim_getreg(priv, timer, - STM32_HRTIM_TIM_SET1R_OFFSET), - hrtim_tim_getreg(priv, timer, - STM32_HRTIM_TIM_RST1R_OFFSET), - hrtim_tim_getreg(priv, timer, - STM32_HRTIM_TIM_SET2R_OFFSET)); - - tmrinfo("\tRST2:\t0x%08" PRIx32 "\tEEF1:\t0x%08" PRIx32 - "\tEEF2:\t0x%08" PRIx32 "\n", - hrtim_tim_getreg(priv, timer, - STM32_HRTIM_TIM_RST2R_OFFSET), - hrtim_tim_getreg(priv, timer, - STM32_HRTIM_TIM_EEFR1_OFFSET), - hrtim_tim_getreg(priv, timer, - STM32_HRTIM_TIM_EEFR2_OFFSET)); - - tmrinfo("\tRSTR:\t0x%08" PRIx32 "\tCHPR:\t0x%08" PRIx32 - "\tCPT1C:\t0x%08" PRIx32 "\n", - hrtim_tim_getreg(priv, timer, STM32_HRTIM_TIM_RSTR_OFFSET), - hrtim_tim_getreg(priv, timer, STM32_HRTIM_TIM_CHPR_OFFSET), - hrtim_tim_getreg(priv, timer, - STM32_HRTIM_TIM_CPT1CR_OFFSET)); - - tmrinfo("\tCPT2C:\t0x%08" PRIx32 "\tOUT:\t0x%08" PRIx32 - "\tFLT:\t0x%08" PRIx32 "\n", - hrtim_tim_getreg(priv, timer, - STM32_HRTIM_TIM_CPT2CR_OFFSET), - hrtim_tim_getreg(priv, timer, STM32_HRTIM_TIM_OUTR_OFFSET), - hrtim_tim_getreg(priv, timer, - STM32_HRTIM_TIM_FLTR_OFFSET)); - - break; - } - - case HRTIM_TIMER_COMMON: - { - tmrinfo("\tCR1:\t0x%08" PRIx32 "\tCR2:\t0x%08" PRIx32 - "\tISR:\t0x%08" PRIx32 "\n", - hrtim_cmn_getreg(priv, STM32_HRTIM_CMN_CR1_OFFSET), - hrtim_cmn_getreg(priv, STM32_HRTIM_CMN_CR2_OFFSET), - hrtim_cmn_getreg(priv, STM32_HRTIM_CMN_ISR_OFFSET)); - - tmrinfo("\tICR:\t0x%08" PRIx32 "\tIER:\t0x%08" PRIx32 - "\tOENR:\t0x%08" PRIx32 "\n", - hrtim_cmn_getreg(priv, STM32_HRTIM_CMN_ICR_OFFSET), - hrtim_cmn_getreg(priv, STM32_HRTIM_CMN_IER_OFFSET), - hrtim_cmn_getreg(priv, STM32_HRTIM_CMN_OENR_OFFSET)); - - tmrinfo("\tODISR:\t0x%08" PRIx32 "\tODSR:\t0x%08" PRIx32 - "\tBMCR:\t0x%08" PRIx32 "\n", - hrtim_cmn_getreg(priv, STM32_HRTIM_CMN_ODISR_OFFSET), - hrtim_cmn_getreg(priv, STM32_HRTIM_CMN_ODSR_OFFSET), - hrtim_cmn_getreg(priv, STM32_HRTIM_CMN_BMCR_OFFSET)); - - tmrinfo("\tBMTRG:\t0x%08" PRIx32 "\tBMCMPR:\t0x%08" PRIx32 - "\tBMPER:\t0x%08" PRIx32 "\n", - hrtim_cmn_getreg(priv, STM32_HRTIM_CMN_BMTRGR_OFFSET), - hrtim_cmn_getreg(priv, STM32_HRTIM_CMN_BMCMPR_OFFSET), - hrtim_cmn_getreg(priv, STM32_HRTIM_CMN_BMPER_OFFSET)); - - tmrinfo("\tADC1R:\t0x%08" PRIx32 "\tADC2R:\t0x%08" PRIx32 - "\tADC3R:\t0x%08" PRIx32 "\n", - hrtim_cmn_getreg(priv, STM32_HRTIM_CMN_ADC1R_OFFSET), - hrtim_cmn_getreg(priv, STM32_HRTIM_CMN_ADC2R_OFFSET), - hrtim_cmn_getreg(priv, STM32_HRTIM_CMN_ADC3R_OFFSET)); - - tmrinfo("\tADC4R:\t0x%08" PRIx32 "\tDLLCR:\t0x%08" PRIx32 - "\tFLTIN1:\t0x%08" PRIx32 "\n", - hrtim_cmn_getreg(priv, STM32_HRTIM_CMN_ADC4R_OFFSET), - hrtim_cmn_getreg(priv, STM32_HRTIM_CMN_DLLCR_OFFSET), - hrtim_cmn_getreg(priv, STM32_HRTIM_CMN_FLTINR1_OFFSET)); - - tmrinfo("\tFLTIN2:\t0x%08" PRIx32 "\tBDMUPD:\t0x%08" PRIx32 - "\tBDTAUP:\t0x%08" PRIx32 "\n", - hrtim_cmn_getreg(priv, STM32_HRTIM_CMN_FLTINR2_OFFSET), - hrtim_cmn_getreg(priv, STM32_HRTIM_CMN_BDMUPDR_OFFSET), - hrtim_cmn_getreg(priv, STM32_HRTIM_CMN_BDTAUPR_OFFSET)); - - tmrinfo("\tBDTBUP: 0x%08" PRIx32 "\tBDTCUP:\t0x%08" PRIx32 - "\tBDTDUP:\t0x%08" PRIx32 "\n", - hrtim_cmn_getreg(priv, STM32_HRTIM_CMN_BDTBUPR_OFFSET), - hrtim_cmn_getreg(priv, STM32_HRTIM_CMN_BDTCUPR_OFFSET), - hrtim_cmn_getreg(priv, STM32_HRTIM_CMN_BDTDUPR_OFFSET)); - - tmrinfo("\tBDTEUP:\t0x%08" PRIx32 "\tBDMAD:\t0x%08" PRIx32 "\n", - hrtim_cmn_getreg(priv, STM32_HRTIM_CMN_BDTEUPR_OFFSET), - hrtim_cmn_getreg(priv, STM32_HRTIM_CMN_BDMADR_OFFSET)); - - break; - } - - default: - { - tmrerr("ERROR: No such timer index: %d\n", timer); - break; - } - } -} -#endif - -/**************************************************************************** - * Name: hrtim_dll_cal - * - * Description: - * Calibrate HRTIM DLL - * - * Input Parameters: - * priv - A reference to the HRTIM structure - * - * Returned Value: - * 0 on success, a negated errno value on failure - * - ****************************************************************************/ - -static int hrtim_dll_cal(struct stm32_hrtim_s *priv) -{ - uint32_t regval = 0; - -#ifdef CONFIG_STM32_HRTIM_PERIODIC_CAL - /* Configure calibration rate */ - - regval |= HRTIM_DLLCR_CAL_RATE; - - /* Enable Periodic calibration */ - - regval |= HRTIM_DLLCR_CALEN; - - /* CALEN must not be set simultaneously with CAL bit */ - - hrtim_cmn_putreg(priv, STM32_HRTIM_CMN_DLLCR_OFFSET, regval); -#endif - - /* DLL Calibration Start */ - - regval |= HRTIM_DLLCR_CAL; - - hrtim_cmn_putreg(priv, STM32_HRTIM_CMN_DLLCR_OFFSET, regval); - - while ((hrtim_cmn_getreg(priv, STM32_HRTIM_CMN_ISR_OFFSET) & - HRTIM_ISR_DLLRDY) == 0); - - return OK; -} - -/**************************************************************************** - * Name: hrtim_tim_clock_config - * - * Description: - * Configure HRTIM Timer clock - * - * Input Parameters: - * priv - A reference to the HRTIM structure - * timer - An HRTIM Timer index - * - * Returned Value: - * 0 on success, a negated errno value on failure - * - ****************************************************************************/ - -static int hrtim_tim_clock_config(struct stm32_hrtim_s *priv, - uint8_t timer, uint8_t pre) -{ - int ret = OK; - uint32_t regval = 0; - - regval = hrtim_tim_getreg(priv, timer, STM32_HRTIM_TIM_CR_OFFSET); - - switch (pre) - { - case HRTIM_PRESCALER_1: - { - regval |= HRTIM_CMNCR_CKPSC_NODIV; - break; - } - - case HRTIM_PRESCALER_2: - { - regval |= HRTIM_CMNCR_CKPSC_d2; - break; - } - - case HRTIM_PRESCALER_4: - { - regval |= HRTIM_CMNCR_CKPSC_d4; - break; - } - - case HRTIM_PRESCALER_8: - { - regval |= HRTIM_CMNCR_CKPSC_d8; - break; - } - - case HRTIM_PRESCALER_16: - { - regval |= HRTIM_CMNCR_CKPSC_d16; - break; - } - - case HRTIM_PRESCALER_32: - { - regval |= HRTIM_CMNCR_CKPSC_d32; - break; - } - - case HRTIM_PRESCALER_64: - { - regval |= HRTIM_CMNCR_CKPSC_d64; - break; - } - - case HRTIM_PRESCALER_128: - { - regval |= HRTIM_CMNCR_CKPSC_d128; - break; - } - - default: - { - tmrerr("ERROR: invalid prescaler value %d for timer %d\n", timer, - pre); - ret = -EINVAL; - goto errout; - } - } - - /* Write prescaler configuration */ - - hrtim_tim_putreg(priv, timer, STM32_HRTIM_TIM_CR_OFFSET, regval); - -errout: - return ret; -} - -/**************************************************************************** - * Name: hrtim_tim_clocks_config - * - * Description: - * Configure HRTIM Timers Clocks - * - * Input Parameters: - * priv - A reference to the HRTIM structure - * - * Returned Value: - * 0 on success, a negated errno value on failure - * - ****************************************************************************/ - -static int hrtim_tim_clocks_config(struct stm32_hrtim_s *priv) -{ - int ret = OK; - - /* Configure Master Timer clock */ - -#ifdef CONFIG_STM32_HRTIM_MASTER - ret = hrtim_tim_clock_config(priv, HRTIM_TIMER_MASTER, - HRTIM_MASTER_PRESCALER); - if (ret < 0) - { - goto errout; - } -#endif - - /* Configure Timer A clock */ - -#ifdef CONFIG_STM32_HRTIM_TIMA - ret = hrtim_tim_clock_config(priv, HRTIM_TIMER_TIMA, HRTIM_TIMA_PRESCALER); - if (ret < 0) - { - goto errout; - } -#endif - - /* Configure Timer B clock */ - -#ifdef CONFIG_STM32_HRTIM_TIMB - ret = hrtim_tim_clock_config(priv, HRTIM_TIMER_TIMB, HRTIM_TIMB_PRESCALER); - if (ret < 0) - { - goto errout; - } -#endif - - /* Configure Timer C clock */ - -#ifdef CONFIG_STM32_HRTIM_TIMC - ret = hrtim_tim_clock_config(priv, HRTIM_TIMER_TIMC, HRTIM_TIMC_PRESCALER); - if (ret < 0) - { - goto errout; - } -#endif - - /* Configure Timer D clock */ - -#ifdef CONFIG_STM32_HRTIM_TIMD - ret = hrtim_tim_clock_config(priv, HRTIM_TIMER_TIMD, HRTIM_TIMD_PRESCALER); - if (ret < 0) - { - goto errout; - } -#endif - - /* Configure Timer E clock */ - -#ifdef CONFIG_STM32_HRTIM_TIME - ret = hrtim_tim_clock_config(priv, HRTIM_TIMER_TIME, HRTIM_TIME_PRESCALER); - if (ret < 0) - { - goto errout; - } -#endif - -errout: - return ret; -} - -/**************************************************************************** - * Name: hrtim_gpios_config - * - * Description: - * Configure HRTIM GPIO - * - * Input Parameters: - * priv - A reference to the HRTIM structure - * - * Returned Value: - * 0 on success, a negated errno value on failure - * - ****************************************************************************/ - -#if defined(CONFIG_STM32_HRTIM_PWM) || defined(CONFIG_STM32_HRTIM_SYNC) -static int hrtim_gpios_config(struct stm32_hrtim_s *priv) -{ -#ifdef CONFIG_STM32_HRTIM_EVENTS - struct stm32_hrtim_eev_s *eev = priv->eev; -#endif -#ifdef CONFIG_STM32_HRTIM_FAULTS - struct stm32_hrtim_faults_s *flt = priv->flt; -#endif - - /* Configure Timer A Outputs */ - -#ifdef CONFIG_STM32_HRTIM_TIMA_PWM_CH1 - stm32_configgpio(GPIO_HRTIM1_CHA1); -#endif - -#ifdef CONFIG_STM32_HRTIM_TIMA_PWM_CH2 - stm32_configgpio(GPIO_HRTIM1_CHA2); -#endif - - /* Configure Timer B Outputs */ - -#ifdef CONFIG_STM32_HRTIM_TIMB_PWM_CH1 - stm32_configgpio(GPIO_HRTIM1_CHB1); -#endif - -#ifdef CONFIG_STM32_HRTIM_TIMB_PWM_CH2 - stm32_configgpio(GPIO_HRTIM1_CHB2); -#endif - - /* Configure Timer C Outputs */ - -#ifdef CONFIG_STM32_HRTIM_TIMC_PWM_CH1 - stm32_configgpio(GPIO_HRTIM1_CHC1); -#endif - -#ifdef CONFIG_STM32_HRTIM_TIMC_PWM_CH2 - stm32_configgpio(GPIO_HRTIM1_CHC2); -#endif - - /* Configure Timer D Outputs */ - -#ifdef CONFIG_STM32_HRTIM_TIMD_PWM_CH1 - stm32_configgpio(GPIO_HRTIM1_CHD1); -#endif - -#ifdef CONFIG_STM32_HRTIM_TIMD_PWM_CH2 - stm32_configgpio(GPIO_HRTIM1_CHD2); -#endif - - /* Configure Timer E Outputs */ - -#ifdef CONFIG_STM32_HRTIM_TIME_PWM_CH1 - stm32_configgpio(GPIO_HRTIM1_CHE1); -#endif - -#ifdef CONFIG_STM32_HRTIM_TIME_PWM_CH2 - stm32_configgpio(GPIO_HRTIM1_CHE2); -#endif - - /* Configure SCOUT */ - -#ifdef CONFIG_STM32_HRTIM_SCOUT - stm32_configgpio(GPIO_HRTIM1_SCOUT); -#endif - - /* Configure SCIN */ - -#ifdef CONFIG_STM32_HRTIM_SCIN - stm32_configgpio(GPIO_HRTIM1_SCIN); -#endif - - /* Configure Faults Inputs */ - -#ifdef CONFIG_STM32_HRTIM_FAULT1 - if (flt->flt1.src == HRTIM_FAULT_SRC_PIN) - { - stm32_configgpio(GPIO_HRTIM1_FLT1); - } -#endif - -#ifdef CONFIG_STM32_HRTIM_FAULT2 - if (flt->flt2.src == HRTIM_FAULT_SRC_PIN) - { - stm32_configgpio(GPIO_HRTIM1_FLT2); - } -#endif - -#ifdef CONFIG_STM32_HRTIM_FAULT3 - if (flt->flt3.src == HRTIM_FAULT_SRC_PIN) - { - stm32_configgpio(GPIO_HRTIM1_FLT3); - } -#endif - -#ifdef CONFIG_STM32_HRTIM_FAULT4 - if (flt->flt4.src == HRTIM_FAULT_SRC_PIN) - { - stm32_configgpio(GPIO_HRTIM1_FLT4); - } -#endif - -#ifdef CONFIG_STM32_HRTIM_FAULT5 - if (flt->flt5.src == HRTIM_FAULT_SRC_PIN) - { - stm32_configgpio(GPIO_HRTIM1_FLT5); - } -#endif - - /* Configure External Events Inputs */ - -#ifdef CONFIG_STM32_HRTIM_EEV1 - if (eev->eev1.src == HRTIM_EEV_SRC_PIN) - { - stm32_configgpio(GPIO_HRTIM1_EEV1); - } -#endif - -#ifdef CONFIG_STM32_HRTIM_EEV2 - if (eev->eev2.src == HRTIM_EEV_SRC_PIN) - { - stm32_configgpio(GPIO_HRTIM1_EEV2); - } -#endif - -#ifdef CONFIG_STM32_HRTIM_EEV3 - if (eev->eev3.src == HRTIM_EEV_SRC_PIN) - { - stm32_configgpio(GPIO_HRTIM1_EEV3); - } -#endif - -#ifdef CONFIG_STM32_HRTIM_EEV4 - if (eev->eev4.src == HRTIM_EEV_SRC_PIN) - { - stm32_configgpio(GPIO_HRTIM1_EEV4); - } -#endif - -#ifdef CONFIG_STM32_HRTIM_EEV5 - if (eev->eev5.src == HRTIM_EEV_SRC_PIN) - { - stm32_configgpio(GPIO_HRTIM1_EEV5); - } -#endif - -#ifdef CONFIG_STM32_HRTIM_EEV6 - if (eev->eev6.src == HRTIM_EEV_SRC_PIN) - { - stm32_configgpio(GPIO_HRTIM1_EEV6); - } -#endif - -#ifdef CONFIG_STM32_HRTIM_EEV7 - if (eev->eev7.src == HRTIM_EEV_SRC_PIN) - { - stm32_configgpio(GPIO_HRTIM1_EEV7); - } -#endif - -#ifdef CONFIG_STM32_HRTIM_EEV8 - if (eev->eev8.src == HRTIM_EEV_SRC_PIN) - { - stm32_configgpio(GPIO_HRTIM1_EEV8); - } -#endif - -#ifdef CONFIG_STM32_HRTIM_EEV9 - if (eev->eev9.src == HRTIM_EEV_SRC_PIN) - { - stm32_configgpio(GPIO_HRTIM1_EEV9); - } -#endif - -#ifdef CONFIG_STM32_HRTIM_EEV10 - if (eev->eev10.src == HRTIM_EEV_SRC_PIN) - { - stm32_configgpio(GPIO_HRTIM1_EEV10); - } -#endif - - return OK; -} -#endif - -#if defined(CONFIG_STM32_HRTIM_CAPTURE) - -/**************************************************************************** - * Name: hrtim_tim_capture_cfg - * - * Description: - * Configure HRTIM Captures - * - * Input Parameters: - * priv - A reference to the HRTIM block - * timer - HRTIM Timer index - * capture - capture triggers configuration - * - * Returned Value: - * 0 on success, a negated errno value on failure - * - ****************************************************************************/ - -static int hrtim_tim_capture_cfg(struct stm32_hrtim_s *priv, - uint8_t timer, uint8_t index, - uint32_t capture) -{ - int ret = OK; - uint32_t offset = 0; - - /* Sanity checking */ - - if (timer == HRTIM_TIMER_MASTER || timer == HRTIM_TIMER_COMMON) - { - ret = -EINVAL; - goto errout; - } - - switch (index) - { - case HRTIM_CAPTURE1: - { - offset = STM32_HRTIM_TIM_CPT1CR_OFFSET; - break; - } - - case HRTIM_CAPTURE2: - { - offset = STM32_HRTIM_TIM_CPT2CR_OFFSET; - break; - } - - default: - { - ret = -EINVAL; - goto errout; - } - } - - hrtim_tim_putreg(priv, timer, offset, capture); - -errout: - return ret; -} - -/**************************************************************************** - * Name: hrtim_capture_config - * - * Description: - * Configure HRTIM Captures - * - * Input Parameters: - * priv - A reference to the HRTIM block - * - * Returned Value: - * 0 on success, a negated errno value on failure - * - ****************************************************************************/ - -static int hrtim_capture_config(struct stm32_hrtim_s *priv) -{ - struct stm32_hrtim_slave_priv_s *slave; - -#ifdef CONFIG_STM32_HRTIM_TIMA_CAP - slave = (struct stm32_hrtim_slave_priv_s *)priv->tima->priv; - hrtim_tim_capture_cfg(priv, HRTIM_TIMER_TIMA, HRTIM_CAPTURE1, - slave->cap.cap1); - hrtim_tim_capture_cfg(priv, HRTIM_TIMER_TIMA, HRTIM_CAPTURE2, - slave->cap.cap2); -#endif - -#ifdef CONFIG_STM32_HRTIM_TIMB_CAP - slave = (struct stm32_hrtim_slave_priv_s *)priv->timb->priv; - hrtim_tim_capture_cfg(priv, HRTIM_TIMER_TIMB, HRTIM_CAPTURE1, - slave->cap.cap1); - hrtim_tim_capture_cfg(priv, HRTIM_TIMER_TIMB, HRTIM_CAPTURE2, - slave->cap.cap2); -#endif - -#ifdef CONFIG_STM32_HRTIM_TIMC_CAP - slave = (struct stm32_hrtim_slave_priv_s *)priv->timc->priv; - hrtim_tim_capture_cfg(priv, HRTIM_TIMER_TIMC, HRTIM_CAPTURE1, - slave->cap.cap1); - hrtim_tim_capture_cfg(priv, HRTIM_TIMER_TIMC, HRTIM_CAPTURE2, - slave->cap.cap2); -#endif - -#ifdef CONFIG_STM32_HRTIM_TIMD_CAP - slave = (struct stm32_hrtim_slave_priv_s *)priv->timd->priv; - hrtim_tim_capture_cfg(priv, HRTIM_TIMER_TIMD, HRTIM_CAPTURE1, - slave->cap.cap1); - hrtim_tim_capture_cfg(priv, HRTIM_TIMER_TIMD, HRTIM_CAPTURE2, - slave->cap.cap2); -#endif - -#ifdef CONFIG_STM32_HRTIM_TIME_CAP - slave = (struct stm32_hrtim_slave_priv_s *)priv->time->priv; - hrtim_tim_capture_cfg(priv, HRTIM_TIMER_TIME, HRTIM_CAPTURE1, - slave->cap.cap1); - hrtim_tim_capture_cfg(priv, HRTIM_TIMER_TIME, HRTIM_CAPTURE2, - slave->cap.cap2); -#endif - - return OK; -} - -/**************************************************************************** - * Name: hrtim_capture_get - * - * Description: - * Get HRTIM Timer Capture register - * - * Input Parameters: - * priv - A reference to the HRTIM block - * timer - HRTIM Timer index - * index - Capture register index - * - * Returned Value: - * Timer Capture value on success, 0 on failure - * - ****************************************************************************/ - -static uint16_t hrtim_capture_get(struct hrtim_dev_s *dev, uint8_t timer, - uint8_t index) -{ - struct stm32_hrtim_s *priv = (struct stm32_hrtim_s *)dev->hd_priv; - uint32_t regval = 0; - uint32_t offset = 0; - - switch (index) - { - case HRTIM_CAPTURE1: - { - offset = STM32_HRTIM_TIM_CPT1R_OFFSET; - break; - } - - case HRTIM_CAPTURE2: - { - offset = STM32_HRTIM_TIM_CPT2R_OFFSET; - break; - } - - default: - { - regval = 0; - goto errout; - } - } - - regval = (uint16_t)hrtim_tim_getreg(priv, timer, offset); - -errout: - return regval; -} - -/**************************************************************************** - * Name: hrtim_soft_capture - * - * Description: - * HRTIM Timer software capture tirgger. - * - * Input Parameters: - * dev - HRTIM device structure - * timer - HRTIM Timer indexes - * index - HRTIM capture index - * - * Returned Value: - * 0 on success; a negated errno value on failure - * - ****************************************************************************/ - -static int hrtim_soft_capture(struct hrtim_dev_s *dev, uint8_t timer, - uint8_t index) -{ - struct stm32_hrtim_s *priv = (struct stm32_hrtim_s *)dev->hd_priv; - uint32_t offset = 0; - - switch (index) - { - case HRTIM_CAPTURE1: - { - offset = STM32_HRTIM_TIM_CPT1CR_OFFSET; - break; - } - - case HRTIM_CAPTURE2: - { - offset = STM32_HRTIM_TIM_CPT2CR_OFFSET; - break; - } - - default: - { - goto errout; - } - } - - /* Modify register */ - - hrtim_tim_modifyreg(priv, timer, offset, 0, HRTIM_TIMCPT12CR_SWCPT); - -errout: - return OK; -} - -#endif - -/**************************************************************************** - * Name: hrtim_synch_config - * - * Description: - * Configure HRTIM Synchronization Input/Output - * - * Input Parameters: - * priv - A reference to the HRTIM structure - * - * Returned Value: - * 0 on success, a negated errno value on failure - * - ****************************************************************************/ - -#if defined(CONFIG_STM32_HRTIM_SYNC) -static int hrtim_synch_config(struct stm32_hrtim_s *priv) -{ -#warning "hrtim_synch_config: missing logic" - return OK; -} -#endif - -/**************************************************************************** - * Name: hrtim_tim_outputs_config - * - * Description: - * Configure HRTIM Slave Timer Outputs (CH1 and CH2) - * - * Input Parameters: - * priv - A reference to the HRTIM structure - * - * Returned Value: - * 0 on success, a negated errno value on failure - * - ****************************************************************************/ - -#if defined(CONFIG_STM32_HRTIM_PWM) -static int hrtim_tim_outputs_config(struct stm32_hrtim_s *priv, - uint8_t timer) -{ - struct stm32_hrtim_slave_priv_s *slave; - uint32_t regval = 0; - int ret = OK; - - /* Get Slave Timer data structure */ - - slave = hrtim_slave_get(priv, timer); - if (slave == NULL) - { - ret = -EINVAL; - goto errout; - } - - /* Configure CH1 SET events */ - - regval = slave->pwm.ch1.set; - hrtim_tim_putreg(priv, timer, STM32_HRTIM_TIM_SET1R_OFFSET, regval); - - /* Configure CH1 RESET events */ - - regval = slave->pwm.ch1.rst; - hrtim_tim_putreg(priv, timer, STM32_HRTIM_TIM_RST1R_OFFSET, regval); - - /* Configure CH2 SET events */ - - regval = slave->pwm.ch2.set; - hrtim_tim_putreg(priv, timer, STM32_HRTIM_TIM_SET2R_OFFSET, regval); - - /* Configure CH2 RESET events */ - - regval = slave->pwm.ch2.rst; - hrtim_tim_putreg(priv, timer, STM32_HRTIM_TIM_RST2R_OFFSET, regval); - - /* Now we configure OUT register */ - - regval = 0; - -#ifdef CONFIG_STM32_HRTIM_BURST - /* Configure IDLE state for output 1 */ - - if (slave->pwm.burst.ch1_en) - { - /* Set IDLE mode */ - - regval |= HRTIM_TIMOUT_IDLEM1; - - /* Set Idle state */ - - regval |= ((slave->pwm.burst.ch1_state & HRTIM_IDLE_ACTIVE) ? - HRTIM_TIMOUT_IDLES1 : 0); - } - - /* Configure IDLE state for output 2 */ - - if (slave->pwm.burst.ch2_en) - { - /* Set IDLE mode */ - - regval |= HRTIM_TIMOUT_IDLEM1; - - /* Set Idle state */ - - regval |= ((slave->pwm.burst.ch2_state & HRTIM_IDLE_ACTIVE) ? - HRTIM_TIMOUT_IDLES1 : 0); - } -#endif - -#ifdef CONFIG_STM32_HRTIM_DEADTIME - if (slave->pwm.dt.en == 1) - { - /* Set deadtime enable */ - - regval |= HRTIM_TIMOUT_DTEN; - - /* TODO: deadtime upon burst mode Idle entry */ - } -#endif - - /* Configure Output 1 polarisation */ - - regval |= ((slave->pwm.ch1.pol & HRTIM_OUT_POL_NEG) ? - HRTIM_TIMOUT_POL1 : 0); - - /* Configure Output 2 polarisation */ - - regval |= ((slave->pwm.ch2.pol & HRTIM_OUT_POL_NEG) ? - HRTIM_TIMOUT_POL2 : 0); - - /* Write HRTIM Slave Timer Output register */ - - hrtim_tim_modifyreg(priv, timer, STM32_HRTIM_TIM_OUTR_OFFSET, 0, regval); - -#ifdef CONFIG_STM32_HRTIM_PUSHPULL - if (slave->pwm.pushpull == 1) - { - /* Enable push-pull mode */ - - hrtim_tim_modifyreg(priv, timer, STM32_HRTIM_TIM_CR_OFFSET, 0, - HRTIM_TIMCR_PSHPLL); - } -#endif - -errout: - return ret; -} -#endif - -/**************************************************************************** - * Name: hrtim_outputs_config - * - * Description: - * Configure HRTIM Outputs - * - * Input Parameters: - * priv - A reference to the HRTIM structure - * - * Returned Value: - * 0 on success, a negated errno value on failure - * - ****************************************************************************/ - -#if defined(CONFIG_STM32_HRTIM_PWM) -static int hrtim_outputs_config(struct stm32_hrtim_s *priv) -{ - int ret = OK; - - /* Configure HRTIM TIMER A Outputs */ - -#ifdef CONFIG_STM32_HRTIM_TIMA_PWM - ret = hrtim_tim_outputs_config(priv, HRTIM_TIMER_TIMA); - if (ret < 0) - { - goto errout; - } -#endif - - /* Configure HRTIM TIMER B Outputs */ - -#ifdef CONFIG_STM32_HRTIM_TIMB_PWM - ret = hrtim_tim_outputs_config(priv, HRTIM_TIMER_TIMB); - if (ret < 0) - { - goto errout; - } -#endif - - /* Configure HRTIM TIMER C Outputs */ - -#ifdef CONFIG_STM32_HRTIM_TIMC_PWM - ret = hrtim_tim_outputs_config(priv, HRTIM_TIMER_TIMC); - if (ret < 0) - { - goto errout; - } -#endif - - /* Configure HRTIM TIMER D Outputs */ - -#ifdef CONFIG_STM32_HRTIM_TIMD_PWM - ret = hrtim_tim_outputs_config(priv, HRTIM_TIMER_TIMD); - if (ret < 0) - { - goto errout; - } -#endif - - /* Configure HRTIM TIMER E Outputs */ - -#ifdef CONFIG_STM32_HRTIM_TIME_PWM - ret = hrtim_tim_outputs_config(priv, HRTIM_TIMER_TIME); - if (ret < 0) - { - goto errout; - } -#endif - -errout: - return ret; -} - -/**************************************************************************** - * Name: hrtim_outputs_enable - * - * Description: - * Enable/disable HRTIM outputs (bulk operation) - * - * Input Parameters: - * dev - HRTIM device structure - * outputs - outputs to set - * state - Enable/disable operation - * - * Returned Value: - * 0 on success, a negated errno value on failure - * - ****************************************************************************/ - -static int hrtim_outputs_enable(struct hrtim_dev_s *dev, - uint16_t outputs, bool state) -{ - struct stm32_hrtim_s *priv = (struct stm32_hrtim_s *)dev->hd_priv; - uint32_t offset = 0; - - /* Get register offset */ - - if (state == true) - { - offset = STM32_HRTIM_CMN_OENR_OFFSET; - } - else - { - offset = STM32_HRTIM_CMN_ODISR_OFFSET; - } - - /* Write register */ - - hrtim_cmn_putreg(priv, offset, outputs); - - return OK; -} - -/**************************************************************************** - * Name: output_tim_index_get - ****************************************************************************/ - -static uint8_t output_tim_index_get(uint16_t output) -{ - uint8_t timer = 0; - - switch (output) - { -#ifdef CONFIG_STM32_HRTIM_TIMA - case HRTIM_OUT_TIMA_CH1: - case HRTIM_OUT_TIMA_CH2: - { - timer = HRTIM_TIMER_TIMA; - break; - } -#endif - -#ifdef CONFIG_STM32_HRTIM_TIMB - case HRTIM_OUT_TIMB_CH1: - case HRTIM_OUT_TIMB_CH2: - { - timer = HRTIM_TIMER_TIMB; - break; - } -#endif - -#ifdef CONFIG_STM32_HRTIM_TIMC - case HRTIM_OUT_TIMC_CH1: - case HRTIM_OUT_TIMC_CH2: - { - timer = HRTIM_TIMER_TIMC; - break; - } -#endif - -#ifdef CONFIG_STM32_HRTIM_TIMD - case HRTIM_OUT_TIMD_CH1: - case HRTIM_OUT_TIMD_CH2: - { - timer = HRTIM_TIMER_TIMD; - break; - } -#endif - -#ifdef CONFIG_STM32_HRTIM_TIME - case HRTIM_OUT_TIME_CH1: - case HRTIM_OUT_TIME_CH2: - { - timer = HRTIM_TIMER_TIME; - break; - } -#endif - - default: - { - timer = 0; - break; - } - } - - return timer; -} - -/**************************************************************************** - * Name: output_tim_ch_get - ****************************************************************************/ - -static uint8_t output_tim_ch_get(uint16_t output) -{ - uint8_t ch = 0; - - switch (output) - { -#ifdef CONFIG_STM32_HRTIM_TIMA - case HRTIM_OUT_TIMA_CH1: -#endif -#ifdef CONFIG_STM32_HRTIM_TIMB - case HRTIM_OUT_TIMB_CH1: -#endif -#ifdef CONFIG_STM32_HRTIM_TIMC - case HRTIM_OUT_TIMC_CH1: -#endif -#ifdef CONFIG_STM32_HRTIM_TIMD - case HRTIM_OUT_TIMD_CH1: -#endif -#ifdef CONFIG_STM32_HRTIM_TIME - case HRTIM_OUT_TIME_CH1: -#endif - { - ch = HRTIM_OUT_CH1; - break; - } - -#ifdef CONFIG_STM32_HRTIM_TIMA - case HRTIM_OUT_TIMA_CH2: -#endif -#ifdef CONFIG_STM32_HRTIM_TIMB - case HRTIM_OUT_TIMB_CH2: -#endif -#ifdef CONFIG_STM32_HRTIM_TIMC - case HRTIM_OUT_TIMC_CH2: -#endif -#ifdef CONFIG_STM32_HRTIM_TIMD - case HRTIM_OUT_TIMD_CH2: -#endif -#ifdef CONFIG_STM32_HRTIM_TIME - case HRTIM_OUT_TIME_CH2: -#endif - { - ch = HRTIM_OUT_CH2; - break; - } - - default: - { - ch = 0; - break; - } - } - - return ch; -} - -/**************************************************************************** - * Name: hrtim_output_set_set - ****************************************************************************/ - -static int hrtim_output_set_set(struct hrtim_dev_s *dev, uint16_t output, - uint32_t set) -{ - struct stm32_hrtim_s *priv = (struct stm32_hrtim_s *)dev->hd_priv; - struct stm32_hrtim_slave_priv_s *slave; - uint8_t timer = 0; - int ret = OK; - - /* Get timer index from output */ - - timer = output_tim_index_get(output); - - /* Get Slave Timer data structure */ - - slave = hrtim_slave_get(priv, timer); - if (slave == NULL) - { - ret = -EINVAL; - goto errout; - } - - /* Set new SET value */ - - switch (output_tim_ch_get(output)) - { - case HRTIM_OUT_CH1: - { - slave->pwm.ch1.set = set; - hrtim_tim_putreg(priv, timer, STM32_HRTIM_TIM_SET1R_OFFSET, set); - break; - } - - case HRTIM_OUT_CH2: - { - slave->pwm.ch2.set = set; - hrtim_tim_putreg(priv, timer, STM32_HRTIM_TIM_SET2R_OFFSET, set); - break; - } - - default: - { - ret = -EINVAL; - goto errout; - } - } - -errout: - return ret; -} - -/**************************************************************************** - * Name: hrtim_output_rst_set - ****************************************************************************/ - -static int hrtim_output_rst_set(struct hrtim_dev_s *dev, uint16_t output, - uint32_t rst) -{ - struct stm32_hrtim_s *priv = (struct stm32_hrtim_s *)dev->hd_priv; - struct stm32_hrtim_slave_priv_s *slave; - uint8_t timer = 0; - int ret = OK; - - /* Get timer index from output */ - - timer = output_tim_index_get(output); - - /* Get Salve Timer data structure */ - - slave = hrtim_slave_get(priv, timer); - if (slave == NULL) - { - ret = -EINVAL; - goto errout; - } - - /* Set new RST value */ - - switch (output_tim_ch_get(output)) - { - case HRTIM_OUT_CH1: - { - slave->pwm.ch1.rst = rst; - hrtim_tim_putreg(priv, timer, STM32_HRTIM_TIM_RST1R_OFFSET, rst); - } - - case HRTIM_OUT_CH2: - { - slave->pwm.ch2.rst = rst; - hrtim_tim_putreg(priv, timer, STM32_HRTIM_TIM_RST2R_OFFSET, rst); - } - - default: - { - ret = -EINVAL; - goto errout; - } - } - -errout: - return ret; -} - -#endif - -/**************************************************************************** - * Name: hrtim_adc_config - * - * Description: - * Configure HRTIM ADC triggers - * - * Input Parameters: - * priv - A reference to the HRTIM structure - * - * Returned Value: - * 0 on success, a negated errno value on failure - * - ****************************************************************************/ - -#ifdef HRTIM_HAVE_ADC -static int hrtim_adc_config(struct stm32_hrtim_s *priv) -{ - /* Configure ADC Trigger 1 */ - -#ifdef HRTIM_HAVE_ADC_TRG1 - hrtim_cmn_putreg(priv, STM32_HRTIM_CMN_ADC1R_OFFSET, priv->adc->trg1); -#endif - - /* Configure ADC Trigger 2 */ - -#ifdef HRTIM_HAVE_ADC_TRG2 - hrtim_cmn_putreg(priv, STM32_HRTIM_CMN_ADC2R_OFFSET, priv->adc->trg2); -#endif - - /* Configure ADC Trigger 3 */ - -#ifdef HRTIM_HAVE_ADC_TRG3 - hrtim_cmn_putreg(priv, STM32_HRTIM_CMN_ADC3R_OFFSET, priv->adc->trg3); -#endif - - /* Configure ADC Trigger 4 */ - -#ifdef HRTIM_HAVE_ADC_TRG4 - hrtim_cmn_putreg(priv, STM32_HRTIM_CMN_ADC4R_OFFSET, priv->adc->trg4); -#endif - - return OK; -} -#endif - -#ifdef CONFIG_STM32_HRTIM_DAC -/**************************************************************************** - * Name: hrtim_tim_dac_cfg - * - * Description: - * Configure single HRTIM Timer DAC synchronization event - * - * Input Parameters: - * priv - A reference to the HRTIM structure - * timer - Timer index - * dac - DAC synchronisation event configuration - * - * Returned Value: - * 0 on success, a negated errno value on failure - * - ****************************************************************************/ - -static int hrtim_tim_dac_cfg(struct stm32_hrtim_s *priv, uint8_t timer, - uint8_t dac) -{ - struct stm32_hrtim_tim_s *tim; - uint32_t regval = 0; - - tim = hrtim_tim_get(priv, timer); - - regval = hrtim_tim_getreg(priv, timer, STM32_HRTIM_TIM_CR_OFFSET); - - regval |= (dac << HRTIM_CMNCR_DACSYNC_SHIFT); - - hrtim_tim_putreg(priv, timer, STM32_HRTIM_TIM_CR_OFFSET, regval); - - return OK; -} - -/**************************************************************************** - * Name: hrtim_dac_config - * - * Description: - * Configure HRTIM DAC synchronization - * - * Input Parameters: - * priv - A reference to the HRTIM structure - * - * Returned Value: - * 0 on success, a negated errno value on failure - * - ****************************************************************************/ - -static int hrtim_dac_config(struct stm32_hrtim_s *priv) -{ - struct stm32_hrtim_timcmn_s *tim; - - /* Configure DAC synchronization for Master Timer */ - -#ifdef CONFIG_STM32_HRTIM_MASTER_DAC - tim = (struct stm32_hrtim_timcmn_s *)priv->master; - hrtim_tim_dac_cfg(priv, HRTIM_TIMER_MASTER, tim->dac); -#endif - - /* Configure DAC synchronization for Timer A */ - -#ifdef CONFIG_STM32_HRTIM_TIMA_DAC - tim = (struct stm32_hrtim_timcmn_s *)priv->tima; - hrtim_tim_dac_cfg(priv, HRTIM_TIMER_TIMA, tim->dac); -#endif - - /* Configure DAC synchronization for Timer B */ - -#ifdef CONFIG_STM32_HRTIM_TIMB_DAC - tim = (struct stm32_hrtim_timcmn_s *)priv->timb; - hrtim_tim_dac_cfg(priv, HRTIM_TIMER_TIMB, tim->dac); -#endif - - /* Configure DAC synchronization for Timer C */ - -#ifdef CONFIG_STM32_HRTIM_TIMC_DAC - tim = (struct stm32_hrtim_timcmn_s *)priv->timc; - hrtim_tim_dac_cfg(priv, HRTIM_TIMER_TIMC, tim->dac); -#endif - - /* Configure DAC synchronization for Timer D */ - -#ifdef CONFIG_STM32_HRTIM_TIMD_DAC - tim = (struct stm32_hrtim_timcmn_s *)priv->timd; - hrtim_tim_dac_cfg(priv, HRTIM_TIMER_TIMD, tim->dac); -#endif - - /* Configure DAC synchronization for Timer E */ - -#ifdef CONFIG_STM32_HRTIM_TIME_DAC - tim = (struct stm32_hrtim_timcmn_s *)priv->time; - hrtim_tim_dac_cfg(priv, HRTIM_TIMER_TIME, tim->dac); -#endif - - return OK; -} -#endif - -#ifdef CONFIG_STM32_HRTIM_DMA -/**************************************************************************** - * Name: hrtim_dma_cfg - ****************************************************************************/ - -static int hrtim_tim_dma_cfg(struct stm32_hrtim_s *priv, uint8_t timer, - uint16_t dma) -{ - int ret = OK; - uint32_t regval = 0; - - /* Sanity checking */ - - if (timer == HRTIM_TIMER_COMMON) - { - ret = -EINVAL; - goto errout; - } - - if (timer == HRTIM_TIMER_MASTER) - { - /* Master support first 7 DMA requests */ - - if (dma > 0x7f) - { - tmrerr("ERROR: invalid DMA requests 0x%04X for timer %d\n", dma, - timer); - ret = -EINVAL; - goto errout; - } - } - else - { - if (dma & HRTIM_DMA_SYNC) - { - tmrerr("ERROR: timer %d does not support 0x%04X DMA request\n", - timer, HRTIM_DMA_SYNC); - ret = -EINVAL; - goto errout; - } - } - - /* DMA configuration occupies upper half of the DIER register */ - - regval = dma << 16; - - hrtim_tim_putreg(priv, timer, STM32_HRTIM_TIM_DIER_OFFSET, regval); - -errout: - return ret; -} - -/**************************************************************************** - * Name: hrtim_dma_cfg - ****************************************************************************/ - -static int hrtim_dma_cfg(struct stm32_hrtim_s *priv) -{ -#ifdef CONFIG_STM32_HRTIM_MASTER_DMA - hrtim_tim_dma_cfg(priv, HRTIM_TIMER_MASTER, priv->master->tim.dma); -#endif - -#ifdef CONFIG_STM32_HRTIM_TIMA_DMA - hrtim_tim_dma_cfg(priv, HRTIM_TIMER_TIMA, priv->tima->tim.dma); -#endif - -#ifdef CONFIG_STM32_HRTIM_TIMB_DMA - hrtim_tim_dma_cfg(priv, HRTIM_TIMER_TIMB, priv->timb->tim.dma); -#endif - -#ifdef CONFIG_STM32_HRTIM_TIMC_DMA - hrtim_tim_dma_cfg(priv, HRTIM_TIMER_TIMC, priv->timc->tim.dma); -#endif - -#ifdef CONFIG_STM32_HRTIM_TIMD_DMA - hrtim_tim_dma_cfg(priv, HRTIM_TIMER_TIMD, priv->timd->tim.dma); -#endif - -#ifdef CONFIG_STM32_HRTIM_TIME_DMA - hrtim_tim_dma_cfg(priv, HRTIM_TIMER_TIME, priv->time->tim.dma); -#endif - - return OK; -} -#endif /* CONFIG_STM32_HRTIM_DAM */ - -#ifdef CONFIG_STM32_HRTIM_DEADTIME -/**************************************************************************** - * Name: hrtim_deadtime_update - ****************************************************************************/ - -static int hrtim_deadtime_update(struct hrtim_dev_s *dev, uint8_t timer, - uint8_t dt, uint16_t value) -{ - struct stm32_hrtim_s *priv = (struct stm32_hrtim_s *)dev->hd_priv; - int ret = OK; - uint32_t regval = 0; - uint32_t shift = 0; - uint32_t mask = 0; - - /* For safety reasons we saturate deadtime value if it exceeds - * the acceptable range. - */ - - if (value > 0x1ff) - { - value = 0x1ff; - } - - /* Get shift value */ - - switch (dt) - { - case HRTIM_DT_EDGE_RISING: - { - shift = HRTIM_TIMDT_DTR_SHIFT; - mask = HRTIM_TIMDT_DTR_MASK; - break; - } - - case HRTIM_DT_EDGE_FALLING: - { - shift = HRTIM_TIMDT_DTF_SHIFT; - mask = HRTIM_TIMDT_DTF_MASK; - break; - } - - default: - { - ret = -EINVAL; - goto errout; - } - } - - regval = value << shift; - - /* Update register */ - - hrtim_tim_modifyreg(priv, timer, STM32_HRTIM_TIM_DTR_OFFSET, mask, regval); - -errout: - return ret; -} - -/**************************************************************************** - * Name: hrtim_deadtime_get - ****************************************************************************/ - -static uint16_t hrtim_deadtime_get(struct hrtim_dev_s *dev, - uint8_t timer, uint8_t dt) -{ - struct stm32_hrtim_s *priv = (struct stm32_hrtim_s *)dev->hd_priv; - uint16_t regval = 0; - uint32_t shift = 0; - uint32_t mask = 0; - - /* Get shift value */ - - switch (dt) - { - case HRTIM_DT_EDGE_RISING: - { - shift = HRTIM_TIMDT_DTR_SHIFT; - mask = HRTIM_TIMDT_DTR_MASK; - break; - } - - case HRTIM_DT_EDGE_FALLING: - { - shift = HRTIM_TIMDT_DTF_SHIFT; - mask = HRTIM_TIMDT_DTF_MASK; - break; - } - - default: - { - regval = 0; - goto errout; - } - } - - /* Get Deadtime Register */ - - regval = hrtim_tim_getreg(priv, timer, STM32_HRTIM_TIM_DTR_OFFSET); - - /* Get Deadtime value */ - - regval = (regval & mask) >> shift; - -errout: - return regval; -} - -/**************************************************************************** - * Name: hrtim_tim_deadtime_cfg - ****************************************************************************/ - -static int hrtim_tim_deadtime_cfg(struct stm32_hrtim_s *priv, - uint8_t timer) -{ - struct stm32_hrtim_slave_priv_s *slave; - uint32_t regval = 0; - int ret = OK; - - /* Sanity checking */ - - if (timer == HRTIM_TIMER_MASTER || timer == HRTIM_TIMER_COMMON) - { - ret = -EINVAL; - goto errout; - } - - /* Get Slave Timer data structure */ - - slave = hrtim_slave_get(priv, timer); - if (slave == NULL) - { - ret = -EINVAL; - goto errout; - } - - /* Configure deadtime prescaler */ - - regval |= slave->pwm.dt.prescaler << HRTIM_TIMDT_DTPRSC_SHIFT; - - /* Configure rising deadtime */ - - regval |= slave->pwm.dt.rising << HRTIM_TIMDT_DTR_SHIFT; - - /* Configure falling deadtime */ - - regval |= slave->pwm.dt.falling << HRTIM_TIMDT_DTF_SHIFT; - - /* Configure falling deadtime sign */ - - if (slave->pwm.dt.fsign == HRTIM_DT_SIGN_NEGATIVE) - { - regval |= HRTIM_TIMDT_SDTF; - } - - /* Configure risign deadtime sign */ - - if (slave->pwm.dt.rsign == HRTIM_DT_SIGN_NEGATIVE) - { - regval |= HRTIM_TIMDT_SDTR; - } - - /* Configure falling sing lock */ - - if (slave->pwm.dt.fsign_lock == HRTIM_DT_LOCK) - { - regval |= HRTIM_TIMDT_DTFSLK; - } - - /* Configure rising sing lock */ - - if (slave->pwm.dt.rsign_lock == HRTIM_DT_LOCK) - { - regval |= HRTIM_TIMDT_DTRSLK; - } - - /* Configure rising value lock */ - - if (slave->pwm.dt.rising_lock == HRTIM_DT_LOCK) - { - regval |= HRTIM_TIMDT_DTRLK; - } - - /* Configure falling value lock */ - - if (slave->pwm.dt.falling_lock == HRTIM_DT_LOCK) - { - regval |= HRTIM_TIMDT_DTFLK; - } - - /* TODO: configure default deadtime values */ - - /* Write register */ - - hrtim_tim_putreg(priv, timer, STM32_HRTIM_TIM_DTR_OFFSET, regval); - -errout: - return ret; -} - -/**************************************************************************** - * Name: hrtim_deadtime_config - ****************************************************************************/ - -static int hrtim_deadtime_config(struct stm32_hrtim_s *priv) -{ - /* Configure Timer A deadtime */ - -#ifdef CONFIG_STM32_HRTIM_TIMA_DT - hrtim_tim_deadtime_cfg(priv, HRTIM_TIMER_TIMA); -#endif - - /* Configure Timer B deadtime */ - -#ifdef CONFIG_STM32_HRTIM_TIMB_DT - hrtim_tim_deadtime_cfg(priv, HRTIM_TIMER_TIMB); -#endif - - /* Configure Timer C deadtime */ - -#ifdef CONFIG_STM32_HRTIM_TIMC_DT - hrtim_tim_deadtime_cfg(priv, HRTIM_TIMER_TIMC); -#endif - - /* Configure Timer D deadtime */ - -#ifdef CONFIG_STM32_HRTIM_TIMD_DT - hrtim_tim_deadtime_cfg(priv, HRTIM_TIMER_TIMD); -#endif - - /* Configure Timer E deadtime */ - -#ifdef CONFIG_STM32_HRTIM_TIME_DT - hrtim_tim_deadtime_cfg(priv, HRTIM_TIMER_TIME); -#endif - - return OK; -} -#endif /* CONFIG_STM32_HRTIM_DEADTIME */ - -#ifdef CONFIG_STM32_HRTIM_CHOPPER -/**************************************************************************** - * Name: hrtim_chopper_enable - * - * Description: - * Enable/disable HRTIM outputs (bulk operation) - * - * Input Parameters: - * dev - HRTIM device structure - * timer - An HRTIM Timer index - * chan - Output channel - * state - Enable/disable operation - * - * Returned Value: - * 0 on success, a negated errno value on failure - * - ****************************************************************************/ - -static int hrtim_chopper_enable(struct hrtim_dev_s *dev, uint8_t timer, - uint8_t chan, bool state) -{ - struct stm32_hrtim_s *priv = (struct stm32_hrtim_s *)dev->hd_priv; - uint32_t val = 0; - int ret = OK; - - /* Get bit to change */ - - switch (chan) - { - case HRTIM_OUT_CH1: - { - val = HRTIM_TIMOUT_CHP1; - break; - } - - case HRTIM_OUT_CH2: - { - val = HRTIM_TIMOUT_CHP2; - break; - } - - default: - { - ret = -EINVAL; - goto errout; - } - } - - /* Update register */ - - if (state == true) - { - /* Set enable bit */ - - hrtim_tim_modifyreg(priv, timer, STM32_HRTIM_TIM_OUTR_OFFSET, 0, val); - } - else - { - /* Clear enable bit */ - - hrtim_tim_modifyreg(priv, timer, STM32_HRTIM_TIM_OUTR_OFFSET, val, 0); - } - -errout: - return ret; -} - -/**************************************************************************** - * Name: hrtim_chopper_cfg - ****************************************************************************/ - -static int hrtim_tim_chopper_cfg(struct stm32_hrtim_s *priv, - uint8_t timer) -{ - struct stm32_hrtim_slave_priv_s *slave; - - int ret = OK; - uint32_t regval = 0; - - /* Sanity checking */ - - if (timer == HRTIM_TIMER_MASTER || timer == HRTIM_TIMER_COMMON) - { - ret = -EINVAL; - goto errout; - } - - /* Get Slave Timer data structure */ - - slave = hrtim_slave_get(priv, timer); - if (slave == NULL) - { - ret = -EINVAL; - goto errout; - } - - /* Configure start pulsewidth */ - - regval |= slave->pwm.chp.start_pulse << HRTIM_TIMCHP_STRTPW_SHIFT; - - /* Configure chopper duty cycle */ - - regval |= slave->pwm.chp.duty << HRTIM_TIMCHP_CARDTY_SHIFT; - - /* Configure carrier frequency */ - - regval |= slave->pwm.chp.freq << HRTIM_TIMCHP_CARFRQ_SHIFT; - - /* Write register */ - - hrtim_tim_putreg(priv, timer, STM32_HRTIM_TIM_CHPR_OFFSET, regval); - -errout: - return OK; -} - -/**************************************************************************** - * Name: hrtim_chopper_config - ****************************************************************************/ - -static int hrtim_chopper_config(struct stm32_hrtim_s *priv) -{ - /* Configure chopper for Timer A */ - -#ifdef CONFIG_STM32_HRTIM_TIMA_CHOP - hrtim_tim_chopper_cfg(priv, HRTIM_TIMER_TIMA); -#endif - - /* Configure chopper for Timer B */ - -#ifdef CONFIG_STM32_HRTIM_TIMB_CHOP - hrtim_tim_chopper_cfg(priv, HRTIM_TIMER_TIMB); -#endif - - /* Configure chopper for Timer C */ - -#ifdef CONFIG_STM32_HRTIM_TIMC_CHOP - hrtim_tim_chopper_cfg(priv, HRTIM_TIMER_TIMC); -#endif - - /* Configure chopper for Timer D */ - -#ifdef CONFIG_STM32_HRTIM_TIMD_CHOP - hrtim_tim_chopper_cfg(priv, HRTIM_TIMER_TIMD); -#endif - - /* Configure chopper for Timer E */ - -#ifdef CONFIG_STM32_HRTIM_TIME_CHOP - hrtim_tim_chopper_cfg(priv, HRTIM_TIMER_TIME); -#endif - - return OK; -} -#endif - -#ifdef CONFIG_STM32_HRTIM_BURST -/**************************************************************************** - * Name: hrtim_burst_enable - ****************************************************************************/ - -static int hrtim_burst_enable(struct hrtim_dev_s *dev, bool state) -{ - struct stm32_hrtim_s *priv = (struct stm32_hrtim_s *)dev->hd_priv; - - if (state) - { - /* Enable Burst mode */ - - hrtim_cmn_modifyreg(priv, STM32_HRTIM_CMN_BMCR_OFFSET, 0, - HRTIM_BMCR_BME); - - /* Software start */ - - hrtim_cmn_modifyreg(priv, STM32_HRTIM_CMN_BMTRGR_OFFSET, 0, - HRTIM_BMTRGR_SW); - } - else - { - /* Disable Burst mode */ - - hrtim_cmn_modifyreg(priv, STM32_HRTIM_CMN_BMCR_OFFSET, - HRTIM_BMCR_BME, 0); - } - - return OK; -} - -/**************************************************************************** - * Name: hrtim_burst_cmp_update - ****************************************************************************/ - -static int hrtim_burst_cmp_update(struct hrtim_dev_s *dev, uint16_t cmp) -{ - struct stm32_hrtim_s *priv = (struct stm32_hrtim_s *)dev->hd_priv; - - hrtim_cmn_putreg(priv, STM32_HRTIM_CMN_BMCMPR_OFFSET, cmp); - - return OK; -} - -/**************************************************************************** - * Name: hrtim_burst_per_update - ****************************************************************************/ - -static int hrtim_burst_per_update(struct hrtim_dev_s *dev, uint16_t per) -{ - struct stm32_hrtim_s *priv = (struct stm32_hrtim_s *)dev->hd_priv; - - hrtim_cmn_putreg(priv, STM32_HRTIM_CMN_BMPER_OFFSET, per); - - return OK; -} - -/**************************************************************************** - * Name: hrtim_burst_cmp_get - ****************************************************************************/ - -static uint16_t hrtim_burst_cmp_get(struct hrtim_dev_s *dev) -{ - struct stm32_hrtim_s *priv = (struct stm32_hrtim_s *)dev->hd_priv; - - return (uint16_t)hrtim_cmn_getreg(priv, STM32_HRTIM_CMN_BMCMPR_OFFSET); -} - -/**************************************************************************** - * Name: hrtim_burst_per_get - ****************************************************************************/ - -static uint16_t hrtim_burst_per_get(struct hrtim_dev_s *dev) -{ - struct stm32_hrtim_s *priv = (struct stm32_hrtim_s *)dev->hd_priv; - - return (uint16_t)hrtim_cmn_getreg(priv, STM32_HRTIM_CMN_BMPER_OFFSET); -} - -/**************************************************************************** - * Name: hrtim_burst_pre_update - ****************************************************************************/ - -static int hrtim_burst_pre_update(struct hrtim_dev_s *dev, uint8_t pre) -{ - struct stm32_hrtim_s *priv = (struct stm32_hrtim_s *)dev->hd_priv; - int ret = OK; - uint32_t regval = 0; - - /* Sanity checking */ - - if (priv->burst->clk != HRTIM_BURST_CLOCK_HRTIM) - { - ret = -EPERM; - goto errout; - } - - if (pre > HRTIM_BURST_PRESCALER_32768) - { - ret = -EINVAL; - goto errout; - } - - /* Make sure that Burst mode is disabled */ - - hrtim_burst_enable(dev, false); - - /* Change prescaler */ - - priv->burst->presc = pre; - regval = pre << HRTIM_BMCR_BMPRSC_SHIFT; - - hrtim_cmn_modifyreg(priv, STM32_HRTIM_CMN_BMCR_OFFSET, - HRTIM_BMCR_BMPRSC_MASK, regval); - -errout: - return ret; -} - -/**************************************************************************** - * Name: hrtim_burst_pre_get - ****************************************************************************/ - -static int hrtim_burst_pre_get(struct hrtim_dev_s *dev) -{ - struct stm32_hrtim_s *priv = (struct stm32_hrtim_s *)dev->hd_priv; - int ret = OK; - - if (priv->burst->clk != HRTIM_BURST_CLOCK_HRTIM) - { - ret = -EPERM; - goto errout; - } - - ret = priv->burst->presc; - -errout: - return ret; -} - -/**************************************************************************** - * Name: hrtim_burst_config - ****************************************************************************/ - -static int hrtim_burst_config(struct stm32_hrtim_s *priv) -{ - struct stm32_hrtim_burst_s *burst = priv->burst; - uint32_t regval = 0; - - /* Configure triggers */ - - regval = burst->trg; - - /* Write triggers register */ - - hrtim_cmn_putreg(priv, STM32_HRTIM_CMN_BMTRGR_OFFSET, regval); - - /* TODO: timers mode configuration */ - - regval = 0; - - /* Configure burst mode clock source */ - - regval |= (burst->clk << HRTIM_BMCR_BMCLK_SHIFT); - - /* Configure burst mode prescaler if f_HRTIM clock */ - - if (burst->clk == HRTIM_BURST_CLOCK_HRTIM) - { - regval |= (burst->presc << HRTIM_BMCR_BMPRSC_SHIFT); - } - - /* Set continuous mode */ - - regval |= HRTIM_BMCR_BMOM; - - /* Write Burst Mode CR */ - - hrtim_cmn_putreg(priv, STM32_HRTIM_CMN_BMCR_OFFSET, regval); - - return OK; -} -#endif - -#ifdef CONFIG_STM32_HRTIM_FAULTS -/**************************************************************************** - * Name: hrtim_tim_faults_cfg - * - * Description: - * Configure HRTIM Slave Timer faults sources. - * - * Input Parameters: - * priv - A reference to the HRTIM structure - * timer - timer index - * - * Returned Value: - * 0 on success, a negated errno value on failure - * - ****************************************************************************/ - -static int hrtim_tim_faults_cfg(struct stm32_hrtim_s *priv, - uint8_t timer) -{ - struct stm32_hrtim_slave_priv_s *slave; - uint32_t regval = 0; - int ret = OK; - - slave = hrtim_slave_get(priv, timer); - if (slave == NULL) - { - ret = -EINVAL; - goto errout; - } - - /* Get lock configuration */ - - regval = ((slave->flt & HRTIM_TIM_FAULT_LOCK) ? HRTIM_TIMFLT_FLTLCK : 0); - - /* Get sources configuration */ - - regval |= slave->flt & 0x1f; - - /* Write register */ - - hrtim_tim_putreg(priv, timer, STM32_HRTIM_TIM_FLTR_OFFSET, regval); - -errout: - return ret; -} - -/**************************************************************************** - * Name: hrtim_faults_config - * - * Description: - * Configure single HRTIM Fault - * - * Input Parameters: - * priv - A reference to the HRTIM structure - * index - Fault index - * - * Returned Value: - * 0 on success, a negated errno value on failure - * - ****************************************************************************/ - -static int hrtim_flt_cfg(struct stm32_hrtim_s *priv, uint8_t index) -{ - struct stm32_hrtim_fault_cfg_s *flt; - int ret = OK; - uint32_t regval = 0; - - /* Get fault configuration */ - - switch (index) - { -#ifdef CONFIG_STM32_HRTIM_FAULT1 - case 1: - { - flt = &priv->flt->flt1; - break; - } - -#endif -#ifdef CONFIG_STM32_HRTIM_FAULT2 - case 2: - { - flt = &priv->flt->flt2; - break; - } - -#endif -#ifdef CONFIG_STM32_HRTIM_FAULT3 - case 3: - { - flt = &priv->flt->flt3; - break; - } - -#endif -#ifdef CONFIG_STM32_HRTIM_FAULT4 - case 4: - { - flt = &priv->flt->flt4; - break; - } - -#endif -#ifdef CONFIG_STM32_HRTIM_FAULT5 - case 5: - { - flt = &priv->flt->flt5; - break; - } - -#endif - default: - { - ret = -EINVAL; - goto errout; - } - } - - /* Configure fault */ - - switch (index) - { - /* Fault 1-4 Configuration is located in first common fault register */ - - case 1: - case 2: - case 3: - case 4: - { - regval = hrtim_cmn_getreg(priv, STM32_HRTIM_CMN_FLTINR1_OFFSET); - - /* Configure polarity */ - - regval |= (((flt->pol & HRTIM_FAULT_POL_HIGH) ? - HRTIM_FLTINR1_FLT1P : 0) << (index - 1) * 8); - - /* Config source */ - - regval |= (((flt->src & HRTIM_FAULT_SRC_PIN) ? - HRTIM_FLTINR1_FLT1SRC : 0) << (index - 1) * 8); - - /* Config filter */ - - regval |= ((flt->filter << HRTIM_FLTINR1_FLT1F_SHIFT) << - (index - 1) * 8); - - /* Fault enable */ - - regval |= (HRTIM_FLTINR1_FLT1E << (index - 1) * 8); - - /* Write register */ - - hrtim_cmn_putreg(priv, STM32_HRTIM_CMN_FLTINR1_OFFSET, regval); - - break; - } - - /* Fault 5 configuration is located in second common fault - * register - */ - - case 5: - { - regval = hrtim_cmn_getreg(priv, STM32_HRTIM_CMN_FLTINR2_OFFSET); - - /* Configure polarity */ - - regval |= ((flt->pol & HRTIM_FAULT_POL_HIGH) ? - HRTIM_FLTINR2_FLT5P : 0); - - /* Config source */ - - regval |= ((flt->src & HRTIM_FAULT_SRC_PIN) ? - HRTIM_FLTINR2_FLT5SRC : 0); - - /* Config filter */ - - regval |= ((flt->filter << HRTIM_FLTINR2_FLT5F_SHIFT)); - - /* Fault enable */ - - regval |= HRTIM_FLTINR2_FLT5E; - - /* Write register */ - - hrtim_cmn_putreg(priv, STM32_HRTIM_CMN_FLTINR2_OFFSET, regval); - - break; - } - - default: - { - ret = -EINVAL; - goto errout; - } - } - -errout: - return ret; -} - -/**************************************************************************** - * Name: hrtim_faults_config - * - * Description: - * Configure HRTIM Faults - * - * Input Parameters: - * priv - A reference to the HRTIM structure - * - * Returned Value: - * 0 on success, a negated errno value on failure - * - ****************************************************************************/ - -static int hrtim_faults_config(struct stm32_hrtim_s *priv) -{ - uint32_t regval = 0; - - /* Configure faults */ - -#ifdef CONFIG_STM32_HRTIM_FAULT1 - hrtim_flt_cfg(priv, 1); -#endif - -#ifdef CONFIG_STM32_HRTIM_FAULT2 - hrtim_flt_cfg(priv, 2); -#endif - -#ifdef CONFIG_STM32_HRTIM_FAULT3 - hrtim_flt_cfg(priv, 3); -#endif - -#ifdef CONFIG_STM32_HRTIM_FAULT4 - hrtim_flt_cfg(priv, 4); -#endif - -#ifdef CONFIG_STM32_HRTIM_FAULT5 - hrtim_flt_cfg(priv, 5); -#endif - - /* Configure fault sources in Slave Timers */ - -#ifdef CONFIG_STM32_HRTIM_TIMA_FLT - hrtim_tim_faults_cfg(priv, HRTIM_TIMER_TIMA); -#endif - -#ifdef CONFIG_STM32_HRTIM_TIMB_FLT - hrtim_tim_faults_cfg(priv, HRTIM_TIMER_TIMA); -#endif - -#ifdef CONFIG_STM32_HRTIM_TIMC_FLT - hrtim_tim_faults_cfg(priv, HRTIM_TIMER_TIMA); -#endif - -#ifdef CONFIG_STM32_HRTIM_TIMD_FLT - hrtim_tim_faults_cfg(priv, HRTIM_TIMER_TIMA); -#endif - -#ifdef CONFIG_STM32_HRTIM_TIME_FLT - hrtim_tim_faults_cfg(priv, HRTIM_TIMER_TIMA); -#endif - - /* Configure fault sampling clock division */ - - regval = hrtim_cmn_getreg(priv, STM32_HRTIM_CMN_FLTINR2_OFFSET); - regval |= HRTIM_FAULT_SAMPLING << HRTIM_FLTINR1_FLT1F_SHIFT; - hrtim_cmn_putreg(priv, STM32_HRTIM_CMN_FLTINR2_OFFSET, regval); - - return OK; -} -#endif - -#ifdef CONFIG_STM32_HRTIM_EVENTS -/**************************************************************************** - * Name: hrtim_eev_cfg - * - * Description: - * Configure single HRTIM External Event - * - * Input Parameters: - * priv - A reference to the HRTIM structure - * index - External Event index - * - * Returned Value: - * 0 on success, a negated errno value on failure - * - ****************************************************************************/ - -static int hrtim_eev_cfg(struct stm32_hrtim_s *priv, uint8_t index) -{ - struct stm32_hrtim_eev_cfg_s *eev; - int ret = OK; - uint32_t regval = 0; - - /* Get External Event configuration */ - - switch (index) - { -#ifdef CONFIG_STM32_HRTIM_EEV1 - case 1: - { - eev = &priv->eev->eev1; - break; - } - -#endif -#ifdef CONFIG_STM32_HRTIM_EEV2 - case 2: - { - eev = &priv->eev->eev2; - break; - } - -#endif -#ifdef CONFIG_STM32_HRTIM_EEV3 - case 3: - { - eev = &priv->eev->eev3; - break; - } - -#endif -#ifdef CONFIG_STM32_HRTIM_EEV4 - case 4: - { - eev = &priv->eev->eev4; - break; - } - -#endif -#ifdef CONFIG_STM32_HRTIM_EEV5 - case 5: - { - eev = &priv->eev->eev5; - break; - } - -#endif -#ifdef CONFIG_STM32_HRTIM_EEV6 - case 6: - { - eev = &priv->eev->eev6; - break; - } - -#endif -#ifdef CONFIG_STM32_HRTIM_EEV7 - case 7: - { - eev = &priv->eev->eev7; - break; - } - -#endif -#ifdef CONFIG_STM32_HRTIM_EEV8 - case 8: - { - eev = &priv->eev->eev8; - break; - } - -#endif -#ifdef CONFIG_STM32_HRTIM_EEV8 - case 9: - { - eev = &priv->eev->eev9; - break; - } - -#endif -#ifdef CONFIG_STM32_HRTIM_EEV10 - case 10: - { - eev = &priv->eev->eev10; - break; - } - -#endif - default: - { - ret = -EINVAL; - goto errout; - } - } - - switch (index) - { - case 1: - case 2: - case 3: - case 4: - case 5: - case 6: - { - regval = hrtim_cmn_getreg(priv, STM32_HRTIM_CMN_EECR1_OFFSET); - - /* Configure source */ - - regval |= ((eev->src << HRTIM_EECR1_EE1SRC_SHIFT) << - (index - 1) * 6); - - /* Configure polarity */ - - regval |= ((eev->pol & HRTIM_FAULT_POL_HIGH ? - HRTIM_EECR1_EE1POL : 0) << (index - 1) * 6); - - /* Configure sensitivity */ - - regval |= (((eev->sen) << HRTIM_EECR1_EE1SNS_SHIFT) << - (index - 1) * 6); - - /* Configure mode */ - - regval |= (((eev->mode & HRTIM_EEV_MODE_FAST) ? - HRTIM_EECR1_EE1FAST : 0) << (index - 1) * 6); - - /* Write register */ - - hrtim_cmn_putreg(priv, STM32_HRTIM_CMN_EECR1_OFFSET, regval); - - break; - } - - case 7: - case 8: - case 9: - case 10: - { - regval = hrtim_cmn_getreg(priv, STM32_HRTIM_CMN_EECR2_OFFSET); - - /* Configure source */ - - regval |= ((eev->src << HRTIM_EECR2_EE6SRC_SHIFT) << - (index - 6) * 6); - - /* Configure polarity */ - - regval |= ((eev->pol & HRTIM_FAULT_POL_HIGH ? - HRTIM_EECR2_EE6POL : 0) << (index - 6) * 6); - - /* Configure sensitivity */ - - regval |= (((eev->sen) << HRTIM_EECR2_EE6SNS_SHIFT) << - (index - 6) * 6); - - /* Configure External Event filter, only EEV6-10 */ - - regval |= (((eev->filter) << HRTIM_EECR2_EE6SNS_SHIFT) << - (index - 6) * 6); - - /* Write register */ - - hrtim_cmn_putreg(priv, STM32_HRTIM_CMN_EECR2_OFFSET, regval); - - break; - } - - default: - { - ret = -EINVAL; - goto errout; - } - } - -errout: - return ret; -} - -/**************************************************************************** - * Name: hrtim_events_config - * - * Description: - * Configure HRTIM External Events - * - * Input Parameters: - * priv - A reference to the HRTIM structure - * - * Returned Value: - * 0 on success, a negated errno value on failure - * - ****************************************************************************/ - -static int hrtim_events_config(struct stm32_hrtim_s *priv) -{ - uint32_t regval = 0; - - /* Configure Events sources */ - -#ifdef CONFIG_STM32_HRTIM_EEV1 - hrtim_eev_cfg(priv, 1); -#endif - -#ifdef CONFIG_STM32_HRTIM_EEV2 - hrtim_eev_cfg(priv, 2); -#endif - -#ifdef CONFIG_STM32_HRTIM_EEV3 - hrtim_eev_cfg(priv, 3); -#endif - -#ifdef CONFIG_STM32_HRTIM_EEV4 - hrtim_eev_cfg(priv, 4); -#endif - -#ifdef CONFIG_STM32_HRTIM_EEV5 - hrtim_eev_cfg(priv, 5); -#endif - -#ifdef CONFIG_STM32_HRTIM_EEV6 - hrtim_eev_cfg(priv, 6); -#endif - -#ifdef CONFIG_STM32_HRTIM_EEV7 - hrtim_eev_cfg(priv, 7); -#endif - -#ifdef CONFIG_STM32_HRTIM_EEV8 - hrtim_eev_cfg(priv, 8); -#endif - -#ifdef CONFIG_STM32_HRTIM_EEV9 - hrtim_eev_cfg(priv, 9); -#endif - -#ifdef CONFIG_STM32_HRTIM_EEV10 - hrtim_eev_cfg(priv, 10); -#endif - - /* External Event Sampling clock */ - - regval = hrtim_cmn_getreg(priv, STM32_HRTIM_CMN_EECR3_OFFSET); - regval |= (HRTIM_EEV_SAMPLING << HRTIM_EECR3_EEVSD_SHIFT); - hrtim_cmn_putreg(priv, STM32_HRTIM_CMN_EECR3_OFFSET, regval); - - return OK; -} -#endif /* CONFIG_STM32_HRTIM_FAULTS */ - -#ifdef CONFIG_STM32_HRTIM_INTERRUPTS - -/**************************************************************************** - * Name: hrtim_irq_cfg - ****************************************************************************/ - -static int hrtim_irq_cfg(struct stm32_hrtim_s *priv, uint8_t timer, - uint16_t irq) -{ - int ret = OK; - - if (timer == HRTIM_TIMER_COMMON) - { - hrtim_cmn_putreg(priv, STM32_HRTIM_CMN_IER_OFFSET, irq); - } - else - { - hrtim_tim_putreg(priv, timer, STM32_HRTIM_TIM_DIER_OFFSET, irq); - } - - return ret; -} - -/**************************************************************************** - * Name: hrtim_irq_config - * - * Description: - * Configure HRTIM interrupts - * - * Input Parameters: - * priv - A reference to the HRTIM structure - * - * Returned Value: - * 0 on success, a negated errno value on failure - * - ****************************************************************************/ - -static int hrtim_irq_config(struct stm32_hrtim_s *priv) -{ -#ifdef CONFIG_STM32_HRTIM_MASTER_IRQ - hrtim_irq_cfg(priv, HRTIM_TIMER_MASTER, priv->master->tim.irq); -#endif - -#ifdef CONFIG_STM32_HRTIM_TIMA_IRQ - hrtim_irq_cfg(priv, HRTIM_TIMER_TIMA, priv->tima->tim.irq); -#endif - -#ifdef CONFIG_STM32_HRTIM_TIMB_IRQ - hrtim_irq_cfg(priv, HRTIM_TIMER_TIMB, priv->timb->tim.irq); -#endif - -#ifdef CONFIG_STM32_HRTIM_TIMB_IRQ - hrtim_irq_cfg(priv, HRTIM_TIMER_TIMB, priv->timc->tim.irq); -#endif - -#ifdef CONFIG_STM32_HRTIM_TIMB_IRQ - hrtim_irq_cfg(priv, HRTIM_TIMER_TIMB, priv->timd->tim.irq); -#endif - -#ifdef CONFIG_STM32_HRTIM_TIMB_IRQ - hrtim_irq_cfg(priv, HRTIM_TIMER_TIMB, priv->time->tim.irq); -#endif - -#ifdef CONFIG_STM32_HRTIM_COMMON_IRQ - hrtim_irq_cfg(priv, HRTIM_TIMER_COMMON, priv->irq); -#endif - - return OK; -} - -/**************************************************************************** - * Name: hrtim_irq_ack - ****************************************************************************/ - -static int hrtim_irq_ack(struct hrtim_dev_s *dev, uint8_t timer, - int source) -{ - struct stm32_hrtim_s *priv = (struct stm32_hrtim_s *)dev->hd_priv; - - if (timer == HRTIM_TIMER_COMMON) - { - /* Write to the HRTIM common clear interrupt register */ - - hrtim_cmn_putreg(priv, STM32_HRTIM_CMN_ICR_OFFSET, source); - } - else - { - /* Each timer has its own ICR register */ - - hrtim_tim_putreg(priv, timer, STM32_HRTIM_TIM_ICR_OFFSET, source); - } - - return OK; -} - -/**************************************************************************** - * Name: hrtim_irq_get - ****************************************************************************/ - -static uint16_t hrtim_irq_get(struct hrtim_dev_s *dev, uint8_t timer) -{ - struct stm32_hrtim_s *priv = (struct stm32_hrtim_s *)dev->hd_priv; - uint32_t regval = 0; - - if (timer == HRTIM_TIMER_COMMON) - { - /* Get HRTIM common status interrupt register */ - - regval = hrtim_cmn_getreg(priv, STM32_HRTIM_CMN_ISR_OFFSET); - } - else - { - /* Each timer has its own ISR register */ - - regval = hrtim_tim_getreg(priv, timer, STM32_HRTIM_TIM_ISR_OFFSET); - } - - return (uint16_t)regval; -} -#endif /* CONFIG_STM32_HRTIM_INTERRUPTS */ - -/**************************************************************************** - * Name: hrtim_tim_mode_set - * - * Description: - * Set HRTIM Timer mode - * - * Input Parameters: - * priv - A reference to the HRTIM block - * timer - HRTIM Timer index - * mode - Timer mode configuration - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void hrtim_tim_mode_set(struct stm32_hrtim_s *priv, uint8_t timer, - uint8_t mode) -{ - uint32_t regval = 0; - - regval = hrtim_tim_getreg(priv, timer, STM32_HRTIM_TIM_CR_OFFSET); - - /* Configure preload */ - - if (mode & HRTIM_MODE_PRELOAD) - { - regval |= HRTIM_CMNCR_PREEN; - } - - /* Configure half mode */ - - if (mode & HRTIM_MODE_HALF) - { - regval |= HRTIM_CMNCR_HALF; - } - - /* Configure re-triggerable mode */ - - if (mode & HRTIM_MODE_RETRIG) - { - regval |= HRTIM_CMNCR_RETRIG; - } - - /* Configure continuous mode */ - - if (mode & HRTIM_MODE_CONT) - { - regval |= HRTIM_CMNCR_CONT; - } - - /* Write register */ - - hrtim_tim_putreg(priv, timer, STM32_HRTIM_TIM_CR_OFFSET, regval); -} - -/**************************************************************************** - * Name: hrtim_mode_config - * - * Description: - * Configure HRTIM Timers mode - * - * Input Parameters: - * priv - A reference to the HRTIM structure - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void hrtim_mode_config(struct stm32_hrtim_s *priv) -{ -#ifdef CONFIG_STM32_HRTIM_MASTER - hrtim_tim_mode_set(priv, HRTIM_TIMER_MASTER, priv->master->tim.mode); -#endif - -#ifdef CONFIG_STM32_HRTIM_TIMA - hrtim_tim_mode_set(priv, HRTIM_TIMER_TIMA, priv->tima->tim.mode); -#endif - -#ifdef CONFIG_STM32_HRTIM_TIMB - hrtim_tim_mode_set(priv, HRTIM_TIMER_TIMB, priv->timb->tim.mode); -#endif - -#ifdef CONFIG_STM32_HRTIM_TIMC - hrtim_tim_mode_set(priv, HRTIM_TIMER_TIMC, priv->timc->tim.mode); -#endif - -#ifdef CONFIG_STM32_HRTIM_TIMD - hrtim_tim_mode_set(priv, HRTIM_TIMER_TIMD, priv->timd->tim.mode); -#endif - -#ifdef CONFIG_STM32_HRTIM_TIME - hrtim_tim_mode_set(priv, HRTIM_TIMER_TIME, priv->time->tim.mode); -#endif -} - -/**************************************************************************** - * Name: hrtim_cmpcap_mask_get - * - * Description: - * This function returns not significant bits in counter/capture - * registers for given HRTIM Timer index. - * - * Input Parameters: - * priv - A reference to the HRTIM structure - * timer - HRTIM Timer index - * - * Returned Value: - * Not significant bits for counter/capture registers - * - ****************************************************************************/ - -static uint8_t hrtim_cmpcap_mask_get(struct stm32_hrtim_s *priv, - uint8_t timer) -{ - struct stm32_hrtim_tim_s *tim; - uint8_t mask = 0; - - /* Get Timer data structure */ - - tim = hrtim_tim_get(priv, timer); - if (tim == NULL) - { - mask = 0; - goto errout; - } - - /* Not significant bits depens on timer prescaler */ - - switch (tim->tim.prescaler) - { - case HRTIM_PRESCALER_1: - { - mask = 0b11111; - break; - } - - case HRTIM_PRESCALER_2: - { - mask = 0b1111; - break; - } - - case HRTIM_PRESCALER_4: - { - mask = 0b111; - break; - } - - case HRTIM_PRESCALER_8: - { - mask = 0b11; - break; - } - - case HRTIM_PRESCALER_16: - { - mask = 0b1; - break; - } - - default: - { - mask = 0; - break; - } - } - -errout: - return mask; -} - -/**************************************************************************** - * Name: hrtim_cmp_update - * - * Description: - * Try update HRTIM Timer compare register. - * - * Input Parameters: - * dev - HRTIM device structure - * timer - HRTIM Timer index - * index - Compare register timer - * cmp - New compare register value - * - * Returned Value: - * 0 on success, a negated errno value on failure - * - ****************************************************************************/ - -static int hrtim_cmp_update(struct hrtim_dev_s *dev, uint8_t timer, - uint8_t index, uint16_t cmp) -{ - struct stm32_hrtim_s *priv = (struct stm32_hrtim_s *)dev->hd_priv; - int ret = OK; - uint32_t offset = 0; - uint8_t mask = 0; - - switch (index) - { - case HRTIM_CMP1: - { - offset = STM32_HRTIM_TIM_CMP1R_OFFSET; - break; - } - - case HRTIM_CMP2: - { - offset = STM32_HRTIM_TIM_CMP2R_OFFSET; - break; - } - - case HRTIM_CMP3: - { - offset = STM32_HRTIM_TIM_CMP3R_OFFSET; - break; - } - - case HRTIM_CMP4: - { - offset = STM32_HRTIM_TIM_CMP4R_OFFSET; - break; - } - - default: - { - ret = -EINVAL; - goto errout; - } - } - - /* REVISIT: what should we do if cmp value is not significant ? - * At this moment we set compare register to the nearest significant value. - */ - - mask = hrtim_cmpcap_mask_get(priv, timer); - if (cmp <= mask) - { - cmp = mask + 1; - } - - hrtim_tim_putreg(priv, timer, offset, cmp); - -errout: - return ret; -} - -/**************************************************************************** - * Name: hrtim_per_update - * - * Description: - * Try update HRTIM Timer period register. - * - * Input Parameters: - * dev - HRTIM device structure - * timer - HRTIM Timer index - * per - New period register value - * - * Returned Value: - * 0 on success; a negated errno value on failure - * - ****************************************************************************/ - -static int hrtim_per_update(struct hrtim_dev_s *dev, uint8_t timer, - uint16_t per) -{ - struct stm32_hrtim_s *priv = (struct stm32_hrtim_s *)dev->hd_priv; - hrtim_tim_putreg(priv, timer, STM32_HRTIM_TIM_PER_OFFSET, per); - - return OK; -} - -/**************************************************************************** - * Name: hrtim_per_get - * - * Description: - * Get HRTIM Timer period value - * - * Input Parameters: - * dev - HRTIM device structure - * timer - HRTIM Timer index - * - * Returned Value: - * Timer period value - * - ****************************************************************************/ - -static uint16_t hrtim_per_get(struct hrtim_dev_s *dev, uint8_t timer) -{ - struct stm32_hrtim_s *priv = (struct stm32_hrtim_s *)dev->hd_priv; - - return (uint16_t)hrtim_tim_getreg(priv, timer, STM32_HRTIM_TIM_PER_OFFSET); -} - -/**************************************************************************** - * Name: hrtim_rep_update - * - * Description: - * Try update HRTIM Timer repetition register. - * - * Input Parameters: - * dev - HRTIM device structure - * timer - HRTIM Timer index - * rep - New repetition register value - * - * Returned Value: - * 0 on success; a negated errno value on failure - * - ****************************************************************************/ - -static int hrtim_rep_update(struct hrtim_dev_s *dev, uint8_t timer, - uint8_t rep) -{ - struct stm32_hrtim_s *priv = (struct stm32_hrtim_s *)dev->hd_priv; - hrtim_tim_putreg(priv, timer, STM32_HRTIM_TIM_REPR_OFFSET, rep); - - return OK; -} - -/**************************************************************************** - * Name: hrtim_cmp_update - * - * Description: - * Get HRTIM Timer compare register - * - * Input Parameters: - * priv - A reference to the HRTIM block - * timer - HRTIM Timer index - * index - Compare register timer - * - * Returned Value: - * Timer compare value - * - ****************************************************************************/ - -static uint16_t hrtim_cmp_get(struct hrtim_dev_s *dev, uint8_t timer, - uint8_t index) -{ - struct stm32_hrtim_s *priv = (struct stm32_hrtim_s *)dev->hd_priv; - uint16_t cmpx = 0; - uint32_t offset = 0; - - switch (index) - { - case HRTIM_CMP1: - { - offset = STM32_HRTIM_TIM_CMP1R_OFFSET; - break; - } - - case HRTIM_CMP2: - { - offset = STM32_HRTIM_TIM_CMP2R_OFFSET; - break; - } - - case HRTIM_CMP3: - { - offset = STM32_HRTIM_TIM_CMP3R_OFFSET; - break; - } - - case HRTIM_CMP4: - { - offset = STM32_HRTIM_TIM_CMP4R_OFFSET; - break; - } - - default: - { - cmpx = 0; - goto errout; - } - } - - cmpx = (uint16_t)hrtim_tim_getreg(priv, timer, offset); - -errout: - return cmpx; -} - -/**************************************************************************** - * Name: hrtim_fclk_get - * - * Description: - * Get HRTIM Timer clock value - * - * Input Parameters: - * dev - HRTIM device structure - * timer - HRTIM Timer index - * - * Returned Value: - * Timer clock value - * - ****************************************************************************/ - -static uint64_t hrtim_fclk_get(struct hrtim_dev_s *dev, uint8_t timer) -{ - struct stm32_hrtim_s *priv = (struct stm32_hrtim_s *)dev->hd_priv; - struct stm32_hrtim_tim_s *tim; - uint64_t fclk = 0; - - /* Get Timer data structure */ - - tim = hrtim_tim_get(priv, timer); - if (tim == NULL) - { - fclk = 0; - goto errout; - } - - fclk = tim->tim.fclk; - -errout: - return fclk; -} - -/**************************************************************************** - * Name: hrtim_soft_update - * - * Description: - * HRTIM Timer software update. - * This is bulk operation, so we can update many registers at the same - * time. - * - * Input Parameters: - * dev - HRTIM device structure - * timer - HRTIM Timer indexes - * - * Returned Value: - * 0 on success; a negated errno value on failure - * - ****************************************************************************/ - -static int hrtim_soft_update(struct hrtim_dev_s *dev, uint8_t timer) -{ - struct stm32_hrtim_s *priv = (struct stm32_hrtim_s *)dev->hd_priv; - uint32_t regval = 0; - - regval |= (timer & HRTIM_TIMER_MASTER ? HRTIM_CR2_MSWU : 0); -#ifdef CONFIG_STM32_HRTIM_TIMA - regval |= (timer & HRTIM_TIMER_TIMA ? HRTIM_CR2_TASWU : 0); -#endif -#ifdef CONFIG_STM32_HRTIM_TIMB - regval |= (timer & HRTIM_TIMER_TIMB ? HRTIM_CR2_TBSWU : 0); -#endif -#ifdef CONFIG_STM32_HRTIM_TIMC - regval |= (timer & HRTIM_TIMER_TIMC ? HRTIM_CR2_TCSWU : 0); -#endif -#ifdef CONFIG_STM32_HRTIM_TIMD - regval |= (timer & HRTIM_TIMER_TIMD ? HRTIM_CR2_TDSWU : 0); -#endif -#ifdef CONFIG_STM32_HRTIM_TIME - regval |= (timer & HRTIM_TIMER_TIME ? HRTIM_CR2_TESWU : 0); -#endif - - /* Bits in HRTIM CR2 common register are automatically reset, - * so we can just write to it. - */ - - hrtim_cmn_putreg(priv, STM32_HRTIM_CMN_CR2_OFFSET, regval); - - return OK; -} - -/**************************************************************************** - * Name: hrtim_soft_reset - * - * Description: - * HRTIM Timer software reset. - * This is bulk operation, so we can update many registers at the same - * time. - * - * Input Parameters: - * dev - HRTIM device structure - * timer - HRTIM Timer indexes - * - * Returned Value: - * 0 on success; a negated errno value on failure - * - ****************************************************************************/ - -static int hrtim_soft_reset(struct hrtim_dev_s *dev, uint8_t timer) -{ - struct stm32_hrtim_s *priv = (struct stm32_hrtim_s *)dev->hd_priv; - uint32_t regval = 0; - - regval |= (timer & HRTIM_TIMER_MASTER ? HRTIM_CR2_MRST : 0); -#ifdef CONFIG_STM32_HRTIM_TIMA - regval |= (timer & HRTIM_TIMER_TIMA ? HRTIM_CR2_TARST : 0); -#endif -#ifdef CONFIG_STM32_HRTIM_TIMB - regval |= (timer & HRTIM_TIMER_TIMB ? HRTIM_CR2_TBRST : 0); -#endif -#ifdef CONFIG_STM32_HRTIM_TIMC - regval |= (timer & HRTIM_TIMER_TIMC ? HRTIM_CR2_TCRST : 0); -#endif -#ifdef CONFIG_STM32_HRTIM_TIMD - regval |= (timer & HRTIM_TIMER_TIMD ? HRTIM_CR2_TDRST : 0); -#endif -#ifdef CONFIG_STM32_HRTIM_TIME - regval |= (timer & HRTIM_TIMER_TIME ? HRTIM_CR2_TERST : 0); -#endif - - /* Bits in HRTIM CR2 common register are automatically reset, - * so we can just write to it. - */ - - hrtim_cmn_putreg(priv, STM32_HRTIM_CMN_CR2_OFFSET, regval); - - return OK; -} - -/**************************************************************************** - * Name: hrtim_tim_freq_set - * - * Description: - * Set HRTIM Timer frequency - * - * Returned Value: - * 0 on success, a negated errno value on failure - * - ****************************************************************************/ - -static int hrtim_tim_freq_set(struct hrtim_dev_s *dev, uint8_t timer, - uint64_t freq) -{ - uint64_t per = 0; - uint64_t fclk = 0; - int ret = OK; - - /* Get Timer period value for given frequency */ - - fclk = HRTIM_FCLK_GET(dev, timer); - per = fclk / freq; - if (per > HRTIM_PER_MAX) - { - tmrerr("ERROR: can not achieve timer pwm " - "freq=%" PRIu64 " if fclk=%" PRIu64 "\n", - freq, fclk); - ret = -EINVAL; - goto errout; - } - - /* Set Timer period value */ - - HRTIM_PER_SET(dev, timer, (uint16_t)per); - -errout: - return ret; -} - -/**************************************************************************** - * Name: hrtim_tim_enable - * - * Description: - * Enable/disable HRTIM timer counter (bulk operation) - * - * Returned Value: - * 0 on success, a negated errno value on failure - * - ****************************************************************************/ - -static int hrtim_tim_enable(struct hrtim_dev_s *dev, uint8_t timers, - bool state) -{ - struct stm32_hrtim_s *priv = (struct stm32_hrtim_s *)dev->hd_priv; - uint32_t regval = 0; - - regval |= (timers & HRTIM_TIMERS_MASK) << HRTIM_MCR_TCEN_SHIFT; - - if (state == true) - { - /* Set bits */ - - hrtim_tim_modifyreg(priv, HRTIM_TIMER_MASTER, - STM32_HRTIM_TIM_CR_OFFSET, - 0, regval); - } - else - { - /* Clear bits */ - - hrtim_tim_modifyreg(priv, HRTIM_TIMER_MASTER, - STM32_HRTIM_TIM_CR_OFFSET, - regval, 0); - } - - return OK; -} - -/**************************************************************************** - * Name: hrtim_tim_reset_set - * - * Description: - * Set HRTIM Timer Reset events - * - * Input Parameters: - * priv - A reference to the HRTIM block - * timer - HRTIM Timer index - * reset - Reset configuration - * - * Returned Value: - * Zero on success; a negated errno value on failure - * - ****************************************************************************/ - -static int hrtim_tim_reset_set(struct stm32_hrtim_s *priv, uint8_t timer, - uint64_t reset) -{ - int ret = OK; - uint32_t regval = 0; - - /* Sanity checking */ - - if (timer == HRTIM_TIMER_MASTER || timer == HRTIM_TIMER_COMMON) - { - ret = -EINVAL; - goto errout; - } - - /* First 18 bits can be written directly */ - - regval |= (reset & 0x3ffff); - - /* TimerX reset events differ for individual timers */ - - switch (timer) - { -#ifdef CONFIG_STM32_HRTIM_TIMA - case HRTIM_TIMER_TIMA: - { - regval |= ((reset & HRTIM_RST_TBCMP1) ? - HRTIM_TIMARST_TIMBCMP1 : 0); - regval |= ((reset & HRTIM_RST_TBCMP2) ? - HRTIM_TIMARST_TIMBCMP2 : 0); - regval |= ((reset & HRTIM_RST_TBCMP4) ? - HRTIM_TIMARST_TIMBCMP4 : 0); - regval |= ((reset & HRTIM_RST_TCCMP1) ? - HRTIM_TIMARST_TIMCCMP1 : 0); - regval |= ((reset & HRTIM_RST_TCCMP2) ? - HRTIM_TIMARST_TIMCCMP2 : 0); - regval |= ((reset & HRTIM_RST_TCCMP4) ? - HRTIM_TIMARST_TIMCCMP4 : 0); - regval |= ((reset & HRTIM_RST_TDCMP1) ? - HRTIM_TIMARST_TIMDCMP1 : 0); - regval |= ((reset & HRTIM_RST_TDCMP2) ? - HRTIM_TIMARST_TIMDCMP2 : 0); - regval |= ((reset & HRTIM_RST_TDCMP4) ? - HRTIM_TIMARST_TIMDCMP4 : 0); - regval |= ((reset & HRTIM_RST_TECMP1) ? - HRTIM_TIMARST_TIMECMP1 : 0); - regval |= ((reset & HRTIM_RST_TECMP2) ? - HRTIM_TIMARST_TIMECMP2 : 0); - regval |= ((reset & HRTIM_RST_TECMP4) ? - HRTIM_TIMARST_TIMECMP4 : 0); - break; - } -#endif - -#ifdef CONFIG_STM32_HRTIM_TIMB - case HRTIM_TIMER_TIMB: - { - regval |= ((reset & HRTIM_RST_TACMP1) ? - HRTIM_TIMBRST_TIMACMP1 : 0); - regval |= ((reset & HRTIM_RST_TACMP2) ? - HRTIM_TIMBRST_TIMACMP2 : 0); - regval |= ((reset & HRTIM_RST_TACMP4) ? - HRTIM_TIMBRST_TIMACMP4 : 0); - regval |= ((reset & HRTIM_RST_TCCMP1) ? - HRTIM_TIMBRST_TIMCCMP1 : 0); - regval |= ((reset & HRTIM_RST_TCCMP2) ? - HRTIM_TIMBRST_TIMCCMP2 : 0); - regval |= ((reset & HRTIM_RST_TCCMP4) ? - HRTIM_TIMBRST_TIMCCMP4 : 0); - regval |= ((reset & HRTIM_RST_TDCMP1) ? - HRTIM_TIMBRST_TIMDCMP1 : 0); - regval |= ((reset & HRTIM_RST_TDCMP2) ? - HRTIM_TIMBRST_TIMDCMP2 : 0); - regval |= ((reset & HRTIM_RST_TDCMP4) ? - HRTIM_TIMBRST_TIMDCMP4 : 0); - regval |= ((reset & HRTIM_RST_TECMP1) ? - HRTIM_TIMBRST_TIMECMP1 : 0); - regval |= ((reset & HRTIM_RST_TECMP2) ? - HRTIM_TIMBRST_TIMECMP2 : 0); - regval |= ((reset & HRTIM_RST_TECMP4) ? - HRTIM_TIMBRST_TIMECMP4 : 0); - break; - } -#endif - -#ifdef CONFIG_STM32_HRTIM_TIMC - case HRTIM_TIMER_TIMC: - { - regval |= ((reset & HRTIM_RST_TACMP1) ? - HRTIM_TIMCRST_TIMACMP1 : 0); - regval |= ((reset & HRTIM_RST_TACMP2) ? - HRTIM_TIMCRST_TIMACMP2 : 0); - regval |= ((reset & HRTIM_RST_TACMP4) ? - HRTIM_TIMCRST_TIMACMP4 : 0); - regval |= ((reset & HRTIM_RST_TBCMP1) ? - HRTIM_TIMCRST_TIMBCMP1 : 0); - regval |= ((reset & HRTIM_RST_TBCMP2) ? - HRTIM_TIMCRST_TIMBCMP2 : 0); - regval |= ((reset & HRTIM_RST_TBCMP4) ? - HRTIM_TIMCRST_TIMBCMP4 : 0); - regval |= ((reset & HRTIM_RST_TDCMP1) ? - HRTIM_TIMCRST_TIMDCMP1 : 0); - regval |= ((reset & HRTIM_RST_TDCMP2) ? - HRTIM_TIMCRST_TIMDCMP2 : 0); - regval |= ((reset & HRTIM_RST_TDCMP4) ? - HRTIM_TIMCRST_TIMDCMP4 : 0); - regval |= ((reset & HRTIM_RST_TECMP1) ? - HRTIM_TIMCRST_TIMECMP1 : 0); - regval |= ((reset & HRTIM_RST_TECMP2) ? - HRTIM_TIMCRST_TIMECMP2 : 0); - regval |= ((reset & HRTIM_RST_TECMP4) ? - HRTIM_TIMCRST_TIMECMP4 : 0); - break; - } -#endif - -#ifdef CONFIG_STM32_HRTIM_TIMD - case HRTIM_TIMER_TIMD: - { - regval |= ((reset & HRTIM_RST_TACMP1) ? - HRTIM_TIMDRST_TIMACMP1 : 0); - regval |= ((reset & HRTIM_RST_TACMP2) ? - HRTIM_TIMDRST_TIMACMP2 : 0); - regval |= ((reset & HRTIM_RST_TACMP4) ? - HRTIM_TIMDRST_TIMACMP4 : 0); - regval |= ((reset & HRTIM_RST_TBCMP1) ? - HRTIM_TIMDRST_TIMBCMP1 : 0); - regval |= ((reset & HRTIM_RST_TBCMP2) ? - HRTIM_TIMDRST_TIMBCMP2 : 0); - regval |= ((reset & HRTIM_RST_TBCMP4) ? - HRTIM_TIMDRST_TIMBCMP4 : 0); - regval |= ((reset & HRTIM_RST_TCCMP1) ? - HRTIM_TIMDRST_TIMCCMP1 : 0); - regval |= ((reset & HRTIM_RST_TCCMP2) ? - HRTIM_TIMDRST_TIMCCMP2 : 0); - regval |= ((reset & HRTIM_RST_TCCMP4) ? - HRTIM_TIMDRST_TIMCCMP4 : 0); - regval |= ((reset & HRTIM_RST_TECMP1) ? - HRTIM_TIMDRST_TIMECMP1 : 0); - regval |= ((reset & HRTIM_RST_TECMP2) ? - HRTIM_TIMDRST_TIMECMP2 : 0); - regval |= ((reset & HRTIM_RST_TECMP4) ? - HRTIM_TIMDRST_TIMECMP4 : 0); - break; - } -#endif - -#ifdef CONFIG_STM32_HRTIM_TIME - case HRTIM_TIMER_TIME: - { - regval |= ((reset & HRTIM_RST_TACMP1) ? - HRTIM_TIMERST_TIMACMP1 : 0); - regval |= ((reset & HRTIM_RST_TACMP2) ? - HRTIM_TIMERST_TIMACMP2 : 0); - regval |= ((reset & HRTIM_RST_TACMP4) ? - HRTIM_TIMERST_TIMACMP4 : 0); - regval |= ((reset & HRTIM_RST_TBCMP1) ? - HRTIM_TIMERST_TIMBCMP1 : 0); - regval |= ((reset & HRTIM_RST_TBCMP2) ? - HRTIM_TIMERST_TIMBCMP2 : 0); - regval |= ((reset & HRTIM_RST_TBCMP4) ? - HRTIM_TIMERST_TIMBCMP4 : 0); - regval |= ((reset & HRTIM_RST_TCCMP1) ? - HRTIM_TIMERST_TIMCCMP1 : 0); - regval |= ((reset & HRTIM_RST_TCCMP2) ? - HRTIM_TIMERST_TIMCCMP2 : 0); - regval |= ((reset & HRTIM_RST_TCCMP4) ? - HRTIM_TIMERST_TIMCCMP4 : 0); - regval |= ((reset & HRTIM_RST_TDCMP1) ? - HRTIM_TIMERST_TIMDCMP1 : 0); - regval |= ((reset & HRTIM_RST_TDCMP2) ? - HRTIM_TIMERST_TIMDCMP2 : 0); - regval |= ((reset & HRTIM_RST_TDCMP4) ? - HRTIM_TIMERST_TIMDCMP4 : 0); - break; - } -#endif - - default: - { - ret = -EINVAL; - goto errout; - } - } - - hrtim_tim_putreg(priv, timer, STM32_HRTIM_TIM_RSTR_OFFSET, regval); - -errout: - return ret; -} - -static int hrtim_reset_config(struct stm32_hrtim_s *priv) -{ - struct stm32_hrtim_slave_priv_s *slave; - -#ifdef CONFIG_STM32_HRTIM_TIMA - slave = (struct stm32_hrtim_slave_priv_s *)priv->tima->priv; - hrtim_tim_reset_set(priv, HRTIM_TIMER_TIMA, slave->reset); -#endif - -#ifdef CONFIG_STM32_HRTIM_TIMB - slave = (struct stm32_hrtim_slave_priv_s *)priv->timb->priv; - hrtim_tim_reset_set(priv, HRTIM_TIMER_TIMB, slave->reset); -#endif - -#ifdef CONFIG_STM32_HRTIM_TIMC - slave = (struct stm32_hrtim_slave_priv_s *)priv->timc->priv; - hrtim_tim_reset_set(priv, HRTIM_TIMER_TIMC, slave->reset); -#endif - -#ifdef CONFIG_STM32_HRTIM_TIMD - slave = (struct stm32_hrtim_slave_priv_s *)priv->timd->priv; - hrtim_tim_reset_set(priv, HRTIM_TIMER_TIMD, slave->reset); -#endif - -#ifdef CONFIG_STM32_HRTIM_TIME - slave = (struct stm32_hrtim_slave_priv_s *)priv->time->priv; - hrtim_tim_reset_set(priv, HRTIM_TIMER_TIME, slave->reset); -#endif - - return OK; -} - -static int hrtim_tim_update_set(struct stm32_hrtim_s *priv, - uint8_t timer, - uint16_t update) -{ - uint32_t regval = 0; - - regval = hrtim_tim_getreg(priv, timer, STM32_HRTIM_TIM_CR_OFFSET); - - /* Configure update events */ - - regval |= (update & HRTIM_UPDATE_MSTU ? HRTIM_TIMCR_MSTU : 0); - regval |= (update & HRTIM_UPDATE_RSTU ? HRTIM_TIMCR_RSTU : 0); - regval |= (update & HRTIM_UPDATE_REPU ? HRTIM_TIMCR_REPU : 0); - -#ifdef CONFIG_STM32_HRTIM_TIMA - regval |= (update & HRTIM_UPDATE_TAU ? HRTIM_TIMCR_TAU : 0); -#endif - -#ifdef CONFIG_STM32_HRTIM_TIMB - regval |= (update & HRTIM_UPDATE_TBU ? HRTIM_TIMCR_TBU : 0); -#endif - -#ifdef CONFIG_STM32_HRTIM_TIMC - regval |= (update & HRTIM_UPDATE_TCU ? HRTIM_TIMCR_TCU : 0); -#endif - -#ifdef CONFIG_STM32_HRTIM_TIMD - regval |= (update & HRTIM_UPDATE_TDU ? HRTIM_TIMCR_TDU : 0); -#endif - -#ifdef CONFIG_STM32_HRTIM_TIME - regval |= (update & HRTIM_UPDATE_TEU ? HRTIM_TIMCR_TEU : 0); -#endif - - /* TODO: Configure update gating */ - - /* Write register */ - - hrtim_tim_putreg(priv, timer, STM32_HRTIM_TIM_CR_OFFSET, regval); - - return OK; -} - -static int hrtim_update_config(struct stm32_hrtim_s *priv) -{ - struct stm32_hrtim_slave_priv_s *slave; - -#ifdef CONFIG_STM32_HRTIM_TIMA - slave = (struct stm32_hrtim_slave_priv_s *)priv->tima->priv; - hrtim_tim_update_set(priv, HRTIM_TIMER_TIMA, slave->update); -#endif - -#ifdef CONFIG_STM32_HRTIM_TIMB - slave = (struct stm32_hrtim_slave_priv_s *)priv->timb->priv; - hrtim_tim_update_set(priv, HRTIM_TIMER_TIMB, slave->update); -#endif - -#ifdef CONFIG_STM32_HRTIM_TIMC - slave = (struct stm32_hrtim_slave_priv_s *)priv->timc->priv; - hrtim_tim_update_set(priv, HRTIM_TIMER_TIMC, slave->update); -#endif - -#ifdef CONFIG_STM32_HRTIM_TIMD - slave = (struct stm32_hrtim_slave_priv_s *)priv->timd->priv; - hrtim_tim_update_set(priv, HRTIM_TIMER_TIMD, slave->update); -#endif - -#ifdef CONFIG_STM32_HRTIM_TIME - slave = (struct stm32_hrtim_slave_priv_s *)priv->time->priv; - hrtim_tim_update_set(priv, HRTIM_TIMER_TIME, slave->update); -#endif - - return OK; -} - -/**************************************************************************** - * Name: stm32_hrtimconfig - * - * Description: - * Configure HRTIM - * - * Input Parameters: - * priv - A reference to the HRTIM structure - * - * Returned Value: - * 0 on success, a negated errno value on failure - * - ****************************************************************************/ - -static int stm32_hrtimconfig(struct stm32_hrtim_s *priv) -{ - int ret; - uint32_t regval = 0; - - /* HRTIM DLL calibration */ - - ret = hrtim_dll_cal(priv); - if (ret != OK) - { - tmrerr("ERROR: HRTIM DLL calibration failed!\n"); - goto errout; - } - - /* Configure Timers Clocks */ - - ret = hrtim_tim_clocks_config(priv); - if (ret != OK) - { - tmrerr("ERROR: HRTIM timers clock configuration failed!\n"); - goto errout; - } - - /* Configure Timers reset events */ - - hrtim_reset_config(priv); - - /* Configure Timers update events */ - - hrtim_update_config(priv); - - /* Configure Timers mode */ - - hrtim_mode_config(priv); - - /* Configure auto-delayed mode */ - -#ifdef CONFIG_STM32_HRTIM_AUTODELAYED - hrtim_autodelayed_config(priv); -#endif - - /* Configure HRTIM GPIOs */ - -#if defined(CONFIG_STM32_HRTIM_PWM) || defined(CONFIG_STM32_HRTIM_SYNC) - ret = hrtim_gpios_config(priv); - if (ret != OK) - { - tmrerr("ERROR: HRTIM GPIOs configuration failed!\n"); - goto errout; - } -#endif - - /* Configure HRTIM capture */ - -#if defined(CONFIG_STM32_HRTIM_CAPTURE) - ret = hrtim_capture_config(priv); - if (ret != OK) - { - tmrerr("ERROR: HRTIM capture configuration failed!\n"); - goto errout; - } -#endif - - /* Configure Synchronisation IOs */ - -#if defined(CONFIG_STM32_HRTIM_SYNC) - ret = hrtim_synch_config(priv); - if (ret != OK) - { - tmrerr("ERROR: HRTIM synchronisation configuration failed!\n"); - goto errout; - } -#endif - - /* Configure HRTIM outputs deadtime */ - -#if defined(CONFIG_STM32_HRTIM_DEADTIME) - ret = hrtim_deadtime_config(priv); - if (ret != OK) - { - tmrerr("ERROR: HRTIM deadtime configuration failed!\n"); - goto errout; - } -#endif - - /* Configure HRTIM outputs GPIOs */ - -#if defined(CONFIG_STM32_HRTIM_PWM) - ret = hrtim_outputs_config(priv); - if (ret != OK) - { - tmrerr("ERROR: HRTIM outputs configuration failed!\n"); - goto errout; - } -#endif - - /* Configure ADC triggers */ - -#ifdef HRTIM_HAVE_ADC - ret = hrtim_adc_config(priv); - if (ret != OK) - { - tmrerr("ERROR: HRTIM ADC configuration failed!\n"); - goto errout; - } -#endif - - /* Configure DAC synchronization */ - -#ifdef CONFIG_STM32_HRTIM_DAC - ret = hrtim_dac_config(priv); - if (ret != OK) - { - tmrerr("ERROR: HRTIM ADC configuration failed!\n"); - goto errout; - } -#endif - - /* Configure Faults */ - -#ifdef CONFIG_STM32_HRTIM_FAULTS - ret = hrtim_faults_config(priv); - if (ret != OK) - { - tmrerr("ERROR: HRTIM faults configuration failed!\n"); - goto errout; - } -#endif - - /* Configure External Events */ - -#ifdef CONFIG_STM32_HRTIM_EVENTS - ret = hrtim_events_config(priv); - if (ret != OK) - { - tmrerr("ERROR: HRTIM EEV configuration failed!\n"); - goto errout; - } -#endif - - /* Configure interrupts */ - -#ifdef CONFIG_STM32_HRTIM_INTERRUPTS - ret = hrtim_irq_config(priv); - if (ret != OK) - { - tmrerr("ERROR: HRTIM IRQ configuration failed!\n"); - goto errout; - } -#endif - - /* Configure DMA */ - -#ifdef CONFIG_STM32_HRTIM_DMA - ret = hrtim_dma_cfg(priv); - if (ret != OK) - { - tmrerr("ERROR: HRTIM DMA configuration failed!\n"); - goto errout; - } -#endif - - /* Configure burst mode */ - -#ifdef CONFIG_STM32_HRTIM_BURST - ret = hrtim_burst_config(priv); - if (ret != OK) - { - tmrerr("ERROR: HRTIM burst mode configuration failed!\n"); - goto errout; - } -#endif - -#ifndef CONFIG_STM32_HRTIM_NO_ENABLE_TIMERS - /* Enable Master Timer */ - -# ifdef CONFIG_STM32_HRTIM_MASTER - regval |= HRTIM_MCR_MCEN; -# endif - - /* Enable Slave Timers */ - -# ifdef CONFIG_STM32_HRTIM_TIMA - regval |= HRTIM_MCR_TACEN; -# endif - -# ifdef CONFIG_STM32_HRTIM_TIMB - regval |= HRTIM_MCR_TBCEN; -# endif - -# ifdef CONFIG_STM32_HRTIM_TIMC - regval |= HRTIM_MCR_TCCEN; -# endif - -# ifdef CONFIG_STM32_HRTIM_TIMD - regval |= HRTIM_MCR_TDCEN; -# endif - -# ifdef CONFIG_STM32_HRTIM_TIME - regval |= HRTIM_MCR_TECEN; -# endif - -#endif /* CONFIG_STM32_HRTIM_NO_ENABLE_TIMERS */ - - /* Write enable bits at once */ - - hrtim_tim_modifyreg(priv, HRTIM_TIMER_MASTER, STM32_HRTIM_TIM_CR_OFFSET, - 0, regval); - - /* Dump registers for Master */ - - hrtim_dumpregs(priv, HRTIM_TIMER_MASTER, "Master after configuration"); - - /* Dump registers for Timer A */ - -#ifdef CONFIG_STM32_HRTIM_TIMA - hrtim_dumpregs(priv, HRTIM_TIMER_TIMA, "Timer A after configuration"); -#endif - - /* Dump registers for Timer B */ - -#ifdef CONFIG_STM32_HRTIM_TIMB - hrtim_dumpregs(priv, HRTIM_TIMER_TIMB, "Timer B after configuration"); -#endif - - /* Dump registers for Timer C */ - -#ifdef CONFIG_STM32_HRTIM_TIMC - hrtim_dumpregs(priv, HRTIM_TIMER_TIMC, "Timer C after configuration"); -#endif - - /* Dump registers for Timer D */ - -#ifdef CONFIG_STM32_HRTIM_TIMD - hrtim_dumpregs(priv, HRTIM_TIMER_TIMD, "Timer D after configuration"); -#endif - - /* Dump registers for Timer E */ - -#ifdef CONFIG_STM32_HRTIM_TIME - hrtim_dumpregs(priv, HRTIM_TIMER_TIME, "Timer E after configuration"); -#endif - - /* Dump common registers */ - - hrtim_dumpregs(priv, HRTIM_TIMER_COMMON, "Common after configuration"); - -errout: - return ret; -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_hrtiminitialize - * - * Description: - * Initialize the HRTIM. - * - * Returned Value: - * Valid HRTIM device structure reference on success; a NULL on failure. - * - * Assumptions: - * 1. Clock to the HRTIM block has enabled, - * 2. Board-specific logic has already configured - * - ****************************************************************************/ - -struct hrtim_dev_s *stm32_hrtiminitialize(void) -{ - struct hrtim_dev_s *dev; - struct stm32_hrtim_s *hrtim; - int ret; - - dev = &g_hrtim1dev; - - hrtim = dev->hd_priv; - - /* configure HRTIM only once */ - - if (!dev->initialized) - { - ret = stm32_hrtimconfig(hrtim); - if (ret < 0) - { - tmrerr("ERROR: Failed to initialize HRTIM1: %d\n", ret); - return NULL; - } - - dev->initialized = true; - } - - return dev; -} - -/**************************************************************************** - * Name: hrtim_register - ****************************************************************************/ - -#ifndef CONFIG_STM32_HRTIM_DISABLE_CHARDRV -int hrtim_register(const char *path, struct hrtim_dev_s *dev) -{ - /* Initialize the HRTIM device structure */ - - dev->hd_ocount = 0; - - /* Register the HRTIM character driver */ - - return register_driver(path, &g_hrtim_fops, 0444, dev); -} -#endif /* CONFIG_STM32_HRTIM_DISABLE_CHARDRV */ - -#endif /* CONFIG_STM32_STM32F33XX || CONFIG_STM32_STM32G47XX */ -#endif /* CONFIG_STM32_HRTIM1 */ diff --git a/arch/arm/src/stm32/stm32_hrtim.h b/arch/arm/src/stm32/stm32_hrtim.h deleted file mode 100644 index 7934ca14bff22..0000000000000 --- a/arch/arm/src/stm32/stm32_hrtim.h +++ /dev/null @@ -1,1139 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_hrtim.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32_STM32_HRTIM_H -#define __ARCH_ARM_SRC_STM32_STM32_HRTIM_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include "chip.h" - -#ifdef CONFIG_STM32_HRTIM1 - -#if defined(CONFIG_STM32_STM32F33XX) -# include "hardware/stm32f33xxx_hrtim.h" -# include "hardware/stm32f33xxx_rcc.h" -#elif defined(CONFIG_STM32_STM32G47XX) -# include "hardware/stm32g47xxx_hrtim.h" -# include "hardware/stm32g4xxxx_rcc.h" -#else -# error -#endif - -/**************************************************************************** - * Pre-processor definitions - ****************************************************************************/ - -#if defined(CONFIG_STM32_HRTIM_TIMA) || defined(CONFIG_STM32_HRTIM_TIMB) || \ - defined(CONFIG_STM32_HRTIM_TIMC) || defined(CONFIG_STM32_HRTIM_TIMD) || \ - defined(CONFIG_STM32_HRTIM_TIME) -# define HRTIM_HAVE_SLAVE 1 -#endif - -#if defined(CONFIG_STM32_HRTIM_TIMA_PWM) || defined(CONFIG_STM32_HRTIM_TIMB_PWM) || \ - defined(CONFIG_STM32_HRTIM_TIMC_PWM) || defined(CONFIG_STM32_HRTIM_TIMD_PWM) || \ - defined(CONFIG_STM32_HRTIM_TIME_PWM) -# ifndef CONFIG_STM32_HRTIM_PWM -# error "CONFIG_STM32_HRTIM_PWM must be set" -# endif -#endif - -#if defined(CONFIG_STM32_HRTIM_TIMA_CAP) || defined(CONFIG_STM32_HRTIM_TIMB_CAP) || \ - defined(CONFIG_STM32_HRTIM_TIMC_CAP) || defined(CONFIG_STM32_HRTIM_TIMD_CAP) || \ - defined(CONFIG_STM32_HRTIM_TIME_CAP) -# ifndef CONFIG_STM32_HRTIM_CAPTURE -# error "CONFIG_STM32_HRTIM_CAPTURE must be set" -# endif -#endif - -#if defined(CONFIG_STM32_HRTIM_TIMA_DT) || defined(CONFIG_STM32_HRTIM_TIMB_DT) || \ - defined(CONFIG_STM32_HRTIM_TIMC_DT) || defined(CONFIG_STM32_HRTIM_TIMD_DT) || \ - defined(CONFIG_STM32_HRTIM_TIME_DT) -# ifndef CONFIG_STM32_HRTIM_DEADTIME -# error "CONFIG_STM32_HRTIM_DEADTIME must be set" -# endif -#endif - -#if defined(CONFIG_STM32_HRTIM_TIMA_CHOP) || defined(CONFIG_STM32_HRTIM_TIMB_CHOP) || \ - defined(CONFIG_STM32_HRTIM_TIMC_CHOP) || defined(CONFIG_STM32_HRTIM_TIMD_CHOP) || \ - defined(CONFIG_STM32_HRTIM_TIME_CHOP) -# ifndef CONFIG_STM32_HRTIM_CHOPPER -# error "CONFIG_STM32_HRTIM_CHOPPER must be set" -# endif -#endif - -#if defined(CONFIG_STM32_HRTIM_TIMA_BURST) || defined(CONFIG_STM32_HRTIM_TIMB_BURST) || \ - defined(CONFIG_STM32_HRTIM_TIMC_BURST) || defined(CONFIG_STM32_HRTIM_TIMD_BURST) || \ - defined(CONFIG_STM32_HRTIM_TIME_BURST) -# ifndef CONFIG_STM32_HRTIM_BURST -# error "CONFIG_STM32_HRTIM_BURST must be set" -# endif -#endif - -#if defined(CONFIG_STM32_HRTIM_SCOUT) || defined(CONFIG_STM32_HRTIM_SCIN) -# ifndef CONFIG_STM32_HRTIM_SYNC -# error "CONFIG_STM32_HRTIM_SYNC must be set" -# endif -#endif - -#if defined(CONFIG_STM32_HRTIM_FAULT1) || defined(CONFIG_STM32_HRTIM_FAULT2) || \ - defined(CONFIG_STM32_HRTIM_FAULT3) || defined(CONFIG_STM32_HRTIM_FAULT4) || \ - defined(CONFIG_STM32_HRTIM_FAULT5) -# ifndef CONFIG_STM32_HRTIM_FAULTS -# error "CONFIG_STM32_HRTIM_FAULTS must be set" -# endif -#endif - -#if defined(CONFIG_STM32_HRTIM_EEV1) || defined(CONFIG_STM32_HRTIM_EEV2) || \ - defined(CONFIG_STM32_HRTIM_EEV3) || defined(CONFIG_STM32_HRTIM_EEV4) || \ - defined(CONFIG_STM32_HRTIM_EEV5) || defined(CONFIG_STM32_HRTIM_EEV6) || \ - defined(CONFIG_STM32_HRTIM_EEV7) || defined(CONFIG_STM32_HRTIM_EEV8) || \ - defined(CONFIG_STM32_HRTIM_EEV9) || defined(CONFIG_STM32_HRTIM_EEV10) -# ifndef CONFIG_STM32_HRTIM_EVENTS -# error "CONFIG_STM32_HRTIM_EVENTS must be set" -# endif -#endif - -#if defined(CONFIG_STM32_HRTIM_MASTER_IRQ) || defined(CONFIG_STM32_HRTIM_TIMA_IRQ) || \ - defined(CONFIG_STM32_HRTIM_TIMB_IRQ) || defined(CONFIG_STM32_HRTIM_TIMC_IRQ) || \ - defined(CONFIG_STM32_HRTIM_TIMD_IRQ) || defined(CONFIG_STM32_HRTIM_TIME_IRQ) || \ - defined(CONFIG_STM32_HRTIM_CMN_IRQ) -# ifndef CONFIG_STM32_HRTIM_INTERRUPTS -# error "CONFIG_STM32_HRTIM_INTERRUPTS must be set" -# endif -#endif - -#if defined(CONFIG_STM32_HRTIM_ADC_TRG1) || defined(CONFIG_STM32_HRTIM_ADC_TRG2) || \ - defined(CONFIG_STM32_HRTIM_ADC_TRG3) || defined(CONFIG_STM32_HRTIM_ADC_TRG4) -# ifndef CONFIG_STM32_HRTIM_ADC -# error "CONFIG_STM32_HRTIM_ADC must be set" -# endif -#endif - -/* TIMX PWM configuration checking */ - -#ifdef CONFIG_STM32_HRTIM_TIMA_PWM -# if !defined(CONFIG_STM32_HRTIM_TIMA_PWM_CH1) && \ - !defined(CONFIG_STM32_HRTIM_TIMA_PWM_CH2) -# error "HRTIM TIMA PWM set but no channel selected" -# endif -#endif -#ifdef CONFIG_STM32_HRTIM_TIMB_PWM -# if !defined(CONFIG_STM32_HRTIM_TIMB_PWM_CH1) && \ - !defined(CONFIG_STM32_HRTIM_TIMB_PWM_CH2) -# error "HRTIM TIMB PWM set but no channel selected" -# endif -#endif -#ifdef CONFIG_STM32_HRTIM_TIMC_PWM -# if !defined(CONFIG_STM32_HRTIM_TIMC_PWM_CH1) && \ - !defined(CONFIG_STM32_HRTIM_TIMC_PWM_CH2) -# error "HRTIM TIMC PWM set but no channel selected" -# endif -#endif -#ifdef CONFIG_STM32_HRTIM_TIMD_PWM -# if !defined(CONFIG_STM32_HRTIM_TIMD_PWM_CH1) && \ - !defined(CONFIG_STM32_HRTIM_TIMD_PWM_CH2) -# error "HRTIM TIMD PWM set but no channel selected" -# endif -#endif -#ifdef CONFIG_STM32_HRTIM_TIME_PWM -# if !defined(CONFIG_STM32_HRTIM_TIME_PWM_CH1) && \ - !defined(CONFIG_STM32_HRTIM_TIME_PWM_CH2) -# error "HRTIM TIME PWM set but no channel selected" -# endif -#endif - -/* HRTIM clock source configuration */ - -#ifdef CONFIG_STM32_HRTIM_CLK_FROM_PLL -# if STM32_SYSCLK_SW == RCC_CFGR_SW_PLL -# if (STM32_RCC_CFGR_PPRE2 != RCC_CFGR_PPRE2_HCLK) && \ - (STM32_RCC_CFGR_PPRE2 != RCC_CFGR_PPRE2_HCLKd2) -# error "APB2 prescaler factor can not be greater than 2" -# else -# define HRTIM_HAVE_CLK_FROM_PLL 1 -# define HRTIM_MAIN_CLOCK 2*STM32_PLL_FREQUENCY -# endif -# else -# error "Clock system must be set to PLL" -# endif -#else -# define HRTIM_HAVE_CLK_FROM_APB2 1 -# if STM32_RCC_CFGR_PPRE2 == RCC_CFGR_PPRE2_HCLK -# define HRTIM_MAIN_CLOCK STM32_PCLK2_FREQUENCY -# else -# error "Not supported yet." -# define HRTIM_MAIN_CLOCK 2*STM32_PCLK2_FREQUENCY -# endif -#endif - -/* High-resolution equivalent clock */ - -#define HRTIM_CLOCK (HRTIM_MAIN_CLOCK*32ull) - -/* Helpers ******************************************************************/ - -#define HRTIM_CMP_SET(hrtim, tim, index, cmp) \ - (hrtim)->hd_ops->cmp_update(hrtim, tim, index, cmp) -#define HRTIM_PER_SET(hrtim, tim, per) \ - (hrtim)->hd_ops->per_update(hrtim, tim, per) -#define HRTIM_REP_SET(hrtim, tim, per) \ - (hrtim)->hd_ops->rep_update(hrtim, tim, per) -#define HRTIM_PER_GET(hrtim, tim) \ - (hrtim)->hd_ops->per_get(hrtim, tim) -#define HRTIM_FCLK_GET(hrtim, tim) \ - (hrtim)->hd_ops->fclk_get(hrtim, tim) -#define HRTIM_IRQ_GET(hrtim, irq) \ - (hrtim)->hd_ops->irq_get(hrtim, irq) -#define HRTIM_CAPTURE_GET(hrtim, timer, cap) \ - (hrtim)->hd_ops->capture_get(hrtim, timer, cap) -#define HRTIM_IRQ_ACK(hrtim, irq, ack) \ - (hrtim)->hd_ops->irq_ack(hrtim, irq, ack) -#define HRTIM_SOFT_UPDATE(hrtim, timer) \ - (hrtim)->hd_ops->soft_update(hrtim, timer) -#define HRTIM_SOFT_CAPTURE(hrtim, timer, index) \ - (hrtim)->hd_ops->soft_capture(hrtim, timer, index) -#define HRTIM_SOFT_RESET(hrtim, timer) \ - (hrtim)->hd_ops->soft_reset(hrtim, timer) -#define HRTIM_FREQ_SET(hrtim, timer,freq) \ - (hrtim)->hd_ops->freq_set(hrtim, timer, freq) -#define HRTIM_TIM_ENABLE(hrtim, timers, state) \ - (hrtim)->hd_ops->tim_enable(hrtim, timers, state) -#define HRTIM_OUTPUTS_ENABLE(hrtim, outputs, state) \ - (hrtim)->hd_ops->outputs_enable(hrtim, outputs, state) -#define HRTIM_OUTPUT_SET_SET(hrtim, output, set) \ - (hrtim)->hd_ops->output_set_set(hrtim, output, set) -#define HRTIM_OUTPUT_RST_SET(hrtim, output, rst) \ - (hrtim)->hd_ops->output_rst_set(hrtim, output, rst) -#define HRTIM_BURST_CMP_SET(hrtim, cmp) \ - (hrtim)->hd_ops->burst_cmp_set(hrtim, cmp) -#define HRTIM_BURST_PER_SET(hrtim, per) \ - (hrtim)->hd_ops->burst_per_set(hrtim, per) -#define HRTIM_BURST_PRE_SET(hrtim, pre) \ - (hrtim)->hd_ops->burst_pre_set(hrtim, pre) -#define HRTIM_BURST_ENABLE(hrtim, state) \ - (hrtim)->hd_ops->burst_enable(hrtim, state) -#define HRTIM_DEADTIME_UPDATE(hrtim, tim, dt, val) \ - (hrtim)->hd_ops->deadtime_update(hrtim, tim, dt, val) - -#define HRTIM_PER_MAX 0xFFFF -#define HRTIM_CMP_MAX 0xFFFF -#define HRTIM_CPT_MAX 0xFFFF -#define HRTIM_REP_MAX 0xFF - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -/* HRTIM Timer X index */ - -enum stm32_hrtim_tim_e -{ - HRTIM_TIMER_MASTER = (1 << 0), -#ifdef CONFIG_STM32_HRTIM_TIMA - HRTIM_TIMER_TIMA = (1 << 1), -#endif -#ifdef CONFIG_STM32_HRTIM_TIMB - HRTIM_TIMER_TIMB = (1 << 2), -#endif -#ifdef CONFIG_STM32_HRTIM_TIMC - HRTIM_TIMER_TIMC = (1 << 3), -#endif -#ifdef CONFIG_STM32_HRTIM_TIMD - HRTIM_TIMER_TIMD = (1 << 4), -#endif -#ifdef CONFIG_STM32_HRTIM_TIME - HRTIM_TIMER_TIME = (1 << 5), -#endif - HRTIM_TIMER_COMMON = (1 << 6), - - HRTIM_TIMERS_MASK = 0x3f -}; - -/* Source which can force the Tx1/Tx2 output to its inactive state */ - -enum stm32_hrtim_out_rst_e -{ - HRTIM_OUT_RST_NONE = 0, - HRTIM_OUT_RST_SOFT = (1 << 0), - HRTIM_OUT_RST_RESYNC = (1 << 1), - HRTIM_OUT_RST_PER = (1 << 2), - HRTIM_OUT_RST_CMP1 = (1 << 3), - HRTIM_OUT_RST_CMP2 = (1 << 4), - HRTIM_OUT_RST_CMP3 = (1 << 5), - HRTIM_OUT_RST_CMP4 = (1 << 6), - HRTIM_OUT_RST_MSTPER = (1 << 7), - HRTIM_OUT_RST_MSTCMP1 = (1 << 8), - HRTIM_OUT_RST_MSTCMP2 = (1 << 9), - HRTIM_OUT_RST_MSTCMP3 = (1 << 10), - HRTIM_OUT_RST_MSTCMP4 = (1 << 11), - HRTIM_OUT_RST_TIMEVNT1 = (1 << 12), - HRTIM_OUT_RST_TIMEVNT2 = (1 << 13), - HRTIM_OUT_RST_TIMEVNT3 = (1 << 14), - HRTIM_OUT_RST_TIMEVNT4 = (1 << 15), - HRTIM_OUT_RST_TIMEVNT5 = (1 << 16), - HRTIM_OUT_RST_TIMEVNT6 = (1 << 17), - HRTIM_OUT_RST_TIMEVNT7 = (1 << 18), - HRTIM_OUT_RST_TIMEVNT8 = (1 << 19), - HRTIM_OUT_RST_TIMEVNT9 = (1 << 20), - HRTIM_OUT_RST_EXTEVNT1 = (1 << 21), - HRTIM_OUT_RST_EXTEVNT2 = (1 << 22), - HRTIM_OUT_RST_EXTEVNT3 = (1 << 23), - HRTIM_OUT_RST_EXTEVNT4 = (1 << 24), - HRTIM_OUT_RST_EXTEVNT5 = (1 << 25), - HRTIM_OUT_RST_EXTEVNT6 = (1 << 26), - HRTIM_OUT_RST_EXTEVNT7 = (1 << 27), - HRTIM_OUT_RST_EXTEVNT8 = (1 << 28), - HRTIM_OUT_RST_EXTEVNT9 = (1 << 29), - HRTIM_OUT_RST_EXTEVNT10 = (1 << 30), - HRTIM_OUT_RST_UPDATE = (1 << 31), -}; - -/* Source which can force the Tx1/Tx2 output to its active state */ - -enum stm32_hrtim_out_set_e -{ - HRTIM_OUT_SET_NONE = 0, - HRTIM_OUT_SET_SOFT = (1 << 0), - HRTIM_OUT_SET_RESYNC = (1 << 1), - HRTIM_OUT_SET_PER = (1 << 2), - HRTIM_OUT_SET_CMP1 = (1 << 3), - HRTIM_OUT_SET_CMP2 = (1 << 4), - HRTIM_OUT_SET_CMP3 = (1 << 5), - HRTIM_OUT_SET_CMP4 = (1 << 6), - HRTIM_OUT_SET_MSTPER = (1 << 7), - HRTIM_OUT_SET_MSTCMP1 = (1 << 8), - HRTIM_OUT_SET_MSTCMP2 = (1 << 9), - HRTIM_OUT_SET_MSTCMP3 = (1 << 10), - HRTIM_OUT_SET_MSTCMP4 = (1 << 11), - HRTIM_OUT_SET_TIMEVNT1 = (1 << 12), - HRTIM_OUT_SET_TIMEVNT2 = (1 << 13), - HRTIM_OUT_SET_TIMEVNT3 = (1 << 14), - HRTIM_OUT_SET_TIMEVNT4 = (1 << 15), - HRTIM_OUT_SET_TIMEVNT5 = (1 << 16), - HRTIM_OUT_SET_TIMEVNT6 = (1 << 17), - HRTIM_OUT_SET_TIMEVNT7 = (1 << 18), - HRTIM_OUT_SET_TIMEVNT8 = (1 << 19), - HRTIM_OUT_SET_TIMEVNT9 = (1 << 20), - HRTIM_OUT_SET_EXTEVNT1 = (1 << 21), - HRTIM_OUT_SET_EXTEVNT2 = (1 << 22), - HRTIM_OUT_SET_EXTEVNT3 = (1 << 23), - HRTIM_OUT_SET_EXTEVNT4 = (1 << 24), - HRTIM_OUT_SET_EXTEVNT5 = (1 << 25), - HRTIM_OUT_SET_EXTEVNT6 = (1 << 26), - HRTIM_OUT_SET_EXTEVNT7 = (1 << 27), - HRTIM_OUT_SET_EXTEVNT8 = (1 << 28), - HRTIM_OUT_SET_EXTEVNT9 = (1 << 29), - HRTIM_OUT_SET_EXTEVNT10 = (1 << 30), - HRTIM_OUT_SET_UPDATE = (1 << 31), -}; - -/* Events that can reset TimerX Counter */ - -enum stm32_hrtim_tim_rst_e -{ - /* Timer owns events */ - - HRTIM_RST_UPDT = (1 << 1), - HRTIM_RST_CMP4 = (1 << 2), - HRTIM_RST_CMP2 = (1 << 3), - - /* Master Timer Events */ - - HRTIM_RST_MSTPER = (1 << 4), - HRTIM_RST_MSTCMP1 = (1 << 5), - HRTIM_RST_MSTCMP2 = (1 << 6), - HRTIM_RST_MSTCMP3 = (1 << 7), - HRTIM_RST_MSTCMP4 = (1 << 8), - - /* External Events */ - - HRTIM_RST_EXTEVNT1 = (1 << 9), - HRTIM_RST_EXTEVNT2 = (1 << 10), - HRTIM_RST_EXTEVNT3 = (1 << 11), - HRTIM_RST_EXTEVNT4 = (1 << 12), - HRTIM_RST_EXTEVNT5 = (1 << 13), - HRTIM_RST_EXTEVNT6 = (1 << 14), - HRTIM_RST_EXTEVNT7 = (1 << 15), - HRTIM_RST_EXTEVNT8 = (1 << 16), - HRTIM_RST_EXTEVNT9 = (1 << 17), - HRTIM_RST_EXTEVNT10 = (1 << 18), - - /* TimerX events */ - - HRTIM_RST_TACMP1 = (1 << 19), - HRTIM_RST_TACMP2 = (1 << 20), - HRTIM_RST_TACMP4 = (1 << 21), - HRTIM_RST_TBCMP1 = (1 << 22), - HRTIM_RST_TBCMP2 = (1 << 23), - HRTIM_RST_TBCMP4 = (1 << 24), - HRTIM_RST_TCCMP1 = (1 << 25), - HRTIM_RST_TCCMP2 = (1 << 26), - HRTIM_RST_TCCMP4 = (1 << 27), - HRTIM_RST_TDCMP1 = (1 << 28), - HRTIM_RST_TDCMP2 = (1 << 29), - HRTIM_RST_TDCMP4 = (1 << 30), - HRTIM_RST_TECMP1 = (1 << 31), -}; - -/* This definitions does not fit to the above 32 bit enum */ - -#define HRTIM_RST_TECMP2 (1ull << 32) -#define HRTIM_RST_TECMP4 (1ull << 33) - -/* HRTIM Timer X prescaler */ - -enum stm32_hrtim_tim_prescaler_e -{ - HRTIM_PRESCALER_1, /* CKPSC = 0 */ - HRTIM_PRESCALER_2, /* CKPSC = 1 */ - HRTIM_PRESCALER_4, /* CKPSC = 2 */ - HRTIM_PRESCALER_8, /* CKPSC = 3 */ - HRTIM_PRESCALER_16, /* CKPSC = 4 */ - HRTIM_PRESCALER_32, /* CKPSC = 5 */ - HRTIM_PRESCALER_64, /* CKPSC = 6 */ - HRTIM_PRESCALER_128 /* CKPSC = 7 */ -}; - -/* HRTIM Timer Master/Slave mode */ - -enum stm32_hrtim_mode_e -{ - HRTIM_MODE_PRELOAD = (1 << 0), /* Preload enable */ - HRTIM_MODE_HALF = (1 << 1), /* Half mode */ - HRTIM_MODE_RETRIG = (1 << 2), /* Re-triggerable mode */ - HRTIM_MODE_CONT = (1 << 3), /* Continuous mode */ -}; - -/* HRTIM Slave Timer auto-delayed mode - * NOTE: details in STM32F334 Manual - */ - -enum stm32_hrtim_autodelayed_e -{ - /* CMP2 auto-delayed mode */ - - HRTIM_AUTODELAYED_CMP2_MODE1 = 1, /* DELCMP2 = 01 */ - HRTIM_AUTODELAYED_CMP2_MODE2 = 2, /* DELCMP2 = 10 */ - HRTIM_AUTODELAYED_CMP2_MODE3 = 3, /* DELCMP2 = 11 */ - - /* CMP4 auto-delayed mode */ - - HRTIM_AUTODELAYED_CMP4_MODE1 = (1 << 2), /* DELCMP4 = 01 */ - HRTIM_AUTODELAYED_CMP4_MODE2 = (2 << 2), /* DELCMP4 = 10 */ - HRTIM_AUTODELAYED_CMP4_MODE3 = (3 << 2), /* DELCMP4 = 11 */ -}; - -/* HRTIM Slave Timer fault sources Lock */ - -enum stm32_hrtim_tim_fault_lock_e -{ - HRTIM_TIM_FAULT_RW = 0, /* Slave Timer fault source are read/write */ - HRTIM_TIM_FAULT_LOCK = (1 << 7) /* Slave Timer fault source are read only */ -}; - -/* HRTIM Slave Timer Fault configuration */ - -enum stm32_hrtim_tim_fault_src_e -{ - HRTIM_TIM_FAULT1 = (1 << 0), - HRTIM_TIM_FAULT2 = (1 << 2), - HRTIM_TIM_FAULT3 = (1 << 3), - HRTIM_TIM_FAULT4 = (1 << 4), - HRTIM_TIM_FAULT5 = (1 << 5) -}; - -/* HRTIM Fault Source */ - -enum stm32_hrtim_fault_src_e -{ - HRTIM_FAULT_SRC_PIN = 0, - HRTIM_FAULT_SRC_INTERNAL = 1 -}; - -/* HRTIM External Event Source - * NOTE: according to Table 82 from STM32F334XX Manual. - */ - -enum stm32_hrtim_eev_src_e -{ - HRTIM_EEV_SRC_PIN = 0, - HRTIM_EEV_SRC_ANALOG = 1, - HRTIM_EEV_SRC_TRGO = 2, - HRTIM_EEV_SRC_ADC = 3 -}; - -/* HRTIM Fault Polarity */ - -enum stm32_hrtim_fault_pol_e -{ - HRTIM_FAULT_POL_LOW = 0, - HRTIM_FAULT_POL_HIGH = 1 -}; - -/* HRTIM External Event Polarity */ - -enum stm32_hrtim_eev_pol_e -{ - HRTIM_EEV_POL_HIGH = 0, /* External Event is active high */ - HRTIM_EEV_POL_LOW = 1 /* External Event is active low */ -}; - -/* HRTIM External Event sensitivity */ - -enum stm32_hrtim_eev_sen_e -{ - HRTIM_EEV_SEN_LEVEL = 0, /* On active level defined by polarity */ - HRTIM_EEV_SEN_RISING = 1, /* Rising edgne */ - HRTIM_EEV_SEN_FALLING = 2, /* Falling edge */ - HRTIM_EEV_SEN_BOTH = 3 /* Both edges */ -}; - -/* External Event Sampling clock division */ - -enum stm32_hrtim_eev_sampling_e -{ - HRTIM_EEV_SAMPLING_d1 = 0, - HRTIM_EEV_SAMPLING_d2 = 1, - HRTIM_EEV_SAMPLING_d4 = 2, - HRTIM_EEV_SAMPLING_d8 = 3 -}; - -/* HRTIM External Event Mode. - * NOTE: supported only for EEV1-5. - */ - -enum stm32_hrtim_eev_mode_e -{ - HRTIM_EEV_MODE_NORMAL = 0, - HRTIM_EEV_MODE_FAST = 1 /* low latency mode */ -}; - -/* External Event filter. - * NOTE: supported only for EEV6-10. - */ - -enum stm32_hrtim_eev_filter_e -{ - HRTIM_EEV_DISABLE = 0, - HRTIM_EEV_HRT_N2 = 1, - HRTIM_EEV_HRT_N4 = 2, - HRTIM_EEV_HRT_N8 = 3, - HRTIM_EEV_EEVSd2_N6 = 4, - HRTIM_EEV_EEVSd2_N8 = 5, - HRTIM_EEV_EEVSd4_N6 = 6, - HRTIM_EEV_EEVSd4_N8 = 7, - HRTIM_EEV_EEVSd8_N6 = 8, - HRTIM_EEV_EEVSd8_N8 = 9, - HRTIM_EEV_EEVSd16_N5 = 10, - HRTIM_EEV_EEVSd16_N6 = 11, - HRTIM_EEV_EEVSd16_N8 = 12, - HRTIM_EEV_EEVSd32_N5 = 13, - HRTIM_EEV_EEVSd32_N6 = 14, - HRTIM_EEV_EEVSd32_N8 = 15 -}; - -/* Compare register index */ - -enum stm32_hrtim_cmp_index_e -{ - HRTIM_CMP1, - HRTIM_CMP2, - HRTIM_CMP3, - HRTIM_CMP4 -}; - -/* HRTIM Slave Timer Outputs index */ - -enum stm32_output_s -{ - HRTIM_OUT_CH1 = (1 << 0), - HRTIM_OUT_CH2 = (1 << 1) -}; - -/* HRTIM Slave Timers Outputs */ - -enum stm32_outputs_e -{ - HRTIM_OUT_TIMA_CH1 = (1 << 0), - HRTIM_OUT_TIMA_CH2 = (1 << 1), - HRTIM_OUT_TIMB_CH1 = (1 << 2), - HRTIM_OUT_TIMB_CH2 = (1 << 3), - HRTIM_OUT_TIMC_CH1 = (1 << 4), - HRTIM_OUT_TIMC_CH2 = (1 << 5), - HRTIM_OUT_TIMD_CH1 = (1 << 6), - HRTIM_OUT_TIMD_CH2 = (1 << 7), - HRTIM_OUT_TIME_CH1 = (1 << 8), - HRTIM_OUT_TIME_CH2 = (1 << 9) -}; - -/* HRTIM Output polarisation */ - -enum stm32_output_polarisation_e -{ - HRTIM_OUT_POL_POS = 0, - HRTIM_OUT_POL_NEG = 1 -}; - -/* HRTIM Deadtime sign */ - -enum stm32_hrtim_deadtime_sign_e -{ - HRTIM_DT_SIGN_POSITIVE = 0, - HRTIM_DT_SIGN_NEGATIVE = 1 -}; - -/* HRTIM Deadtime types */ - -enum stm32_hrtim_deadtime_edge_e -{ - HRTIM_DT_EDGE_RISING = 0, - HRTIM_DT_EDGE_FALLING = 1 -}; - -/* HRTIM Deadtime lock */ - -enum stm32_hrtim_deadtime_lock_e -{ - HRTIM_DT_RW = 0, - HRTIM_DT_LOCK = 1 -}; - -/* HRTIM Deadtime prescaler */ - -enum stm32_hrtim_deadtime_prescaler_e -{ - HRTIM_DEADTIME_PRESCALER_1 = 0, - HRTIM_DEADTIME_PRESCALER_2 = 1, - HRTIM_DEADTIME_PRESCALER_4 = 2, - HRTIM_DEADTIME_PRESCALER_8 = 3, - HRTIM_DEADTIME_PRESCALER_16 = 4, - HRTIM_DEADTIME_PRESCALER_32 = 5, - HRTIM_DEADTIME_PRESCALER_64 = 6, - HRTIM_DEADTIME_PRESCALER_128 = 7 -}; - -/* Chopper start pulsewidth */ - -enum stm32_hrtim_chopper_start_e -{ - HRTIM_CHP_START_16, - HRTIM_CHP_START_32, - HRTIM_CHP_START_48, - HRTIM_CHP_START_64, - HRTIM_CHP_START_80, - HRTIM_CHP_START_96, - HRTIM_CHP_START_112, - HRTIM_CHP_START_128, - HRTIM_CHP_START_144, - HRTIM_CHP_START_160, - HRTIM_CHP_START_176, - HRTIM_CHP_START_192, - HRTIM_CHP_START_208, - HRTIM_CHP_START_224, - HRTIM_CHP_START_256 -}; - -/* Chopper duty cycle */ - -enum stm32_hrtim_chopper_duty_e -{ - HRTIM_CHP_DUTY_0, - HRTIM_CHP_DUTY_1, - HRTIM_CHP_DUTY_2, - HRTIM_CHP_DUTY_3, - HRTIM_CHP_DUTY_4, - HRTIM_CHP_DUTY_5, - HRTIM_CHP_DUTY_6, - HRTIM_CHP_DUTY_7 -}; - -/* Chopper carrier frequency */ - -enum stm32_hrtim_chopper_freq_e -{ - HRTIM_CHP_FREQ_d16, - HRTIM_CHP_FREQ_d32, - HRTIM_CHP_FREQ_d48, - HRTIM_CHP_FREQ_d64, - HRTIM_CHP_FREQ_d80, - HRTIM_CHP_FREQ_d96, - HRTIM_CHP_FREQ_d112, - HRTIM_CHP_FREQ_d128, - HRTIM_CHP_FREQ_d144, - HRTIM_CHP_FREQ_d160, - HRTIM_CHP_FREQ_d176, - HRTIM_CHP_FREQ_d192, - HRTIM_CHP_FREQ_d208, - HRTIM_CHP_FREQ_d224, - HRTIM_CHP_FREQ_d240, - HRTIM_CHP_FREQ_d256 -}; - -/* HRTIM ADC Trigger 1/3 */ - -enum stm32_hrtim_adc_trq13_e -{ - HRTIM_ADCTRG13_NONE = 0, /* No trigger */ - HRTIM_ADCTRG13_MC1 = (1 << 0), /* Trigger on Master Compare 1 */ - HRTIM_ADCTRG13_MC2 = (1 << 1), /* Trigger on Master Compare 2 */ - HRTIM_ADCTRG13_MC3 = (1 << 2), /* Trigger on Master Compare 3 */ - HRTIM_ADCTRG13_MC4 = (1 << 3), /* Trigger on Master Compare 4 */ - HRTIM_ADCTRG13_MPER = (1 << 4), /* Trigger on Master Period */ - - HRTIM_ADCTRG13_EEV1 = (1 << 5), /* Trigger on External Event 1 */ - HRTIM_ADCTRG13_EEV2 = (1 << 6), /* Trigger on External Event 2 */ - HRTIM_ADCTRG13_EEV3 = (1 << 7), /* Trigger on External Event 3 */ - HRTIM_ADCTRG13_EEV4 = (1 << 8), /* Trigger on External Event 4 */ - HRTIM_ADCTRG13_EEV5 = (1 << 9), /* Trigger on External Event 5 */ - - HRTIM_ADCTRG13_AC2 = (1 << 10), /* Trigger on Timer A Compare 2 */ - HRTIM_ADCTRG13_AC3 = (1 << 11), /* Trigger on Timer A Compare 3 */ - HRTIM_ADCTRG13_AC4 = (1 << 12), /* Trigger on Timer A Compare 4 */ - HRTIM_ADCTRG13_APER = (1 << 13), /* Trigger on Timer A Period */ - HRTIM_ADCTRG13_ARST = (1 << 14), /* Trigger on Timer A Reset */ - - HRTIM_ADCTRG13_BC2 = (1 << 15), /* Trigger on Timer B Compare 2 */ - HRTIM_ADCTRG13_BC3 = (1 << 16), /* Trigger on Timer B Compare 3 */ - HRTIM_ADCTRG13_BC4 = (1 << 17), /* Trigger on Timer B Compare 4 */ - HRTIM_ADCTRG13_BPER = (1 << 18), /* Trigger on Timer B Period */ - HRTIM_ADCTRG13_BRST = (1 << 19), /* Trigger on Timer B Reset */ - - HRTIM_ADCTRG13_CC2 = (1 << 20), /* Trigger on Timer C Compare 2 */ - HRTIM_ADCTRG13_CC3 = (1 << 21), /* Trigger on Timer C Compare 3 */ - HRTIM_ADCTRG13_CC4 = (1 << 22), /* Trigger on Timer C Compare 4 */ - HRTIM_ADCTRG13_CPER = (1 << 23), /* Trigger on Timer C Period */ - - HRTIM_ADCTRG13_DC2 = (1 << 24), /* Trigger on Timer D Compare 2 */ - HRTIM_ADCTRG13_DC3 = (1 << 25), /* Trigger on Timer D Compare 3 */ - HRTIM_ADCTRG13_DC4 = (1 << 26), /* Trigger on Timer D Compare 4 */ - HRTIM_ADCTRG13_DPER = (1 << 27), /* Trigger on Timer D Period */ - - HRTIM_ADCTRG13_EC2 = (1 << 28), /* Trigger on Timer E Compare 2 */ - HRTIM_ADCTRG13_EC3 = (1 << 29), /* Trigger on Timer E Compare 3 */ - HRTIM_ADCTRG13_EC4 = (1 << 30), /* Trigger on Timer E Compare 4 */ - HRTIM_ADCTRG13_EPER = (1 << 31), /* Trigger on Timer E Period */ -}; - -/* HRTIM ADC Trigger 2/4 */ - -enum stm32_hrtim_adc_trq24_e -{ - HRTIM_ADCTRG24_NONE = 0, /* No trigger */ - HRTIM_ADCTRG24_MC1 = (1 << 0), /* Trigger on Master Compare 1 */ - HRTIM_ADCTRG24_MC2 = (1 << 1), /* Trigger on Master Compare 2 */ - HRTIM_ADCTRG24_MC3 = (1 << 2), /* Trigger on Master Compare 3 */ - HRTIM_ADCTRG24_MC4 = (1 << 3), /* Trigger on Master Compare 4 */ - HRTIM_ADCTRG24_MPER = (1 << 4), /* Trigger on Master Period */ - - HRTIM_ADCTRG24_EEV6 = (1 << 5), /* Trigger on External Event 6 */ - HRTIM_ADCTRG24_EEV7 = (1 << 6), /* Trigger on External Event 7 */ - HRTIM_ADCTRG24_EEV8 = (1 << 7), /* Trigger on External Event 8 */ - HRTIM_ADCTRG24_EEV9 = (1 << 8), /* Trigger on External Event 9 */ - HRTIM_ADCTRG24_EEV10 = (1 << 9), /* Trigger on External Event 10 */ - - HRTIM_ADCTRG24_AC2 = (1 << 10), /* Trigger on Timer A Compare 2 */ - HRTIM_ADCTRG24_AC3 = (1 << 11), /* Trigger on Timer A Compare 3 */ - HRTIM_ADCTRG24_AC4 = (1 << 12), /* Trigger on Timer A Compare 4 */ - HRTIM_ADCTRG24_APER = (1 << 13), /* Trigger on Timer A Period */ - - HRTIM_ADCTRG24_BC2 = (1 << 14), /* Trigger on Timer B Compare 2 */ - HRTIM_ADCTRG24_BC3 = (1 << 15), /* Trigger on Timer B Compare 3 */ - HRTIM_ADCTRG24_BC4 = (1 << 16), /* Trigger on Timer B Compare 4 */ - HRTIM_ADCTRG24_BPER = (1 << 17), /* Trigger on Timer B Period */ - - HRTIM_ADCTRG24_CC2 = (1 << 18), /* Trigger on Timer C Compare 2 */ - HRTIM_ADCTRG24_CC3 = (1 << 19), /* Trigger on Timer C Compare 3 */ - HRTIM_ADCTRG24_CC4 = (1 << 20), /* Trigger on Timer C Compare 4 */ - HRTIM_ADCTRG24_CPER = (1 << 21), /* Trigger on Timer C Period */ - HRTIM_ADCTRG24_CRST = (1 << 22), /* Trigger on Timer C Reset */ - - HRTIM_ADCTRG24_DC2 = (1 << 23), /* Trigger on Timer D Compare 2 */ - HRTIM_ADCTRG24_DC3 = (1 << 24), /* Trigger on Timer D Compare 3 */ - HRTIM_ADCTRG24_DC4 = (1 << 25), /* Trigger on Timer D Compare 4 */ - HRTIM_ADCTRG24_DPER = (1 << 26), /* Trigger on Timer D Period */ - HRTIM_ADCTRG24_DRST = (1 << 27), /* Trigger on Timer D Reset */ - - HRTIM_ADCTRG24_EC2 = (1 << 28), /* Trigger on Timer E Compare 2 */ - HRTIM_ADCTRG24_EC3 = (1 << 29), /* Trigger on Timer E Compare 3 */ - HRTIM_ADCTRG24_EC4 = (1 << 30), /* Trigger on Timer E Compare 4 */ - HRTIM_ADCTRG24_ERST = (1 << 31), /* Trigger on Timer E Reset */ -}; - -/* HRTIM DAC synchronization events */ - -enum stm32_hrtim_dac_e -{ - HRTIM_DAC_TRIG_DIS = 0, - HRTIM_DAC_TRIG1 = 1, - HRTIM_DAC_TRIG2 = 2, - HRTIM_DAC_TRIG3 = 3 -}; - -/* HRTIM Timer update events */ - -enum stm32_tim_update_e -{ - HRTIM_UPDATE_NONE = 0, - HRTIM_UPDATE_MSTU = (1 << 0), - HRTIM_UPDATE_TAU = (1 << 2), - HRTIM_UPDATE_TBU = (1 << 3), - HRTIM_UPDATE_TCU = (1 << 4), - HRTIM_UPDATE_TDU = (1 << 5), - HRTIM_UPDATE_TEU = (1 << 6), - HRTIM_UPDATE_RSTU = (1 << 7), - HRTIM_UPDATE_REPU = (1 << 8), -}; - -/* HRTIM Master Timer interrupts */ - -enum stm32_irq_master_e -{ - HRTIM_IRQ_MCMP1 = (1 << 0), /* Master Compare 1 Interrupt */ - HRTIM_IRQ_MCMP2 = (1 << 1), /* Master Compare 2 Interrupt */ - HRTIM_IRQ_MCMP3 = (1 << 2), /* Master Compare 3 Interrupt */ - HRTIM_IRQ_MCMP4 = (1 << 3), /* Master Compare 4 Interrupt */ - HRTIM_IRQ_MREP = (1 << 4), /* Master Repetition Interrupt */ - HRTIM_IRQ_MSYNC = (1 << 5), /* Sync Input Interrupt */ - HRTIM_IRQ_MUPD = (1 << 6) /* Master Update Interrupt */ -}; - -/* HRTIM Slave Timer interrupts */ - -enum stm32_irq_slave_e -{ - HRTIM_IRQ_CMP1 = (1 << 0), /* Slave Compare 1 Interrupt */ - HRTIM_IRQ_CMP2 = (1 << 1), /* Slave Compare 2 Interrupt */ - HRTIM_IRQ_CMP3 = (1 << 2), /* Slave Compare 3 Interrupt */ - HRTIM_IRQ_CMP4 = (1 << 3), /* Slave Compare 4 Interrupt */ - HRTIM_IRQ_REP = (1 << 4), /* Slave Repetition Interrupt */ - HRTIM_IRQ_UPD = (1 << 6), /* Slave Update Interrupt */ - HRTIM_IRQ_CPT1 = (1 << 7), /* Slave Capture 1 Interrupt */ - HRTIM_IRQ_CPT2 = (1 << 8), /* Slave Capture 2 Interrupt */ - HRTIM_IRQ_SETX1 = (1 << 9), /* Slave Output 1 Set Interrupt */ - HRTIM_IRQ_RSTX1 = (1 << 10), /* Slave Output 1 Reset Interrupt */ - HRTIM_IRQ_SETX2 = (1 << 11), /* Slave Output 2 Set Interrupt */ - HRTIM_IRQ_RSTX2 = (1 << 12), /* Slave Output 2 Reset Interrupt */ - HRTIM_IRQ_RST = (1 << 13), /* Slave Reset/roll-over Interrupt */ - HRTIM_IRQ_DLYPRT = (1 << 14) /* Slave Delayed Protection Interrupt */ -}; - -/* HRTIM Common Interrupts */ - -enum stm32_irq_cmn_e -{ - HRTIM_IRQ_FLT1 = (1 << 0), /* Fault 1 Interrupt */ - HRTIM_IRQ_FLT2 = (1 << 1), /* Fault 2 Interrupt */ - HRTIM_IRQ_FLT3 = (1 << 2), /* Fault 3 Interrupt */ - HRTIM_IRQ_FLT4 = (1 << 3), /* Fault 4 Interrupt */ - HRTIM_IRQ_FLT5 = (1 << 4), /* Fault 5 Interrupt */ - HRTIM_IRQ_SYSFLT = (1 << 5), /* System Fault Interrupt */ - HRTIM_IRQ_DLLRDY = (1 << 16), /* DLL Ready Interrupt */ - HRTIM_IRQ_BMPER = (1 << 17) /* Burst Mode Period Interrupt */ -}; - -/* HRTIM DMA requests */ - -enum stm32_hrtim_dma_e -{ - HRTIM_DMA_CMP1 = (1 << 0), /* Common: Compare 1 DMA request */ - HRTIM_DMA_CMP2 = (1 << 1), /* Common: Compare 2 DMA request */ - HRTIM_DMA_CMP3 = (1 << 2), /* Common: Compare 3 DMA request */ - HRTIM_DMA_CMP4 = (1 << 3), /* Common:Compare 4 DMA request */ - HRTIM_DMA_REP = (1 << 4), /* Common: Repetition DMA request */ - HRTIM_DMA_SYNC = (1 << 5), /* Master: Sync Input DMA request */ - HRTIM_DMA_UPD = (1 << 6), /* Common: Update DMA request */ - HRTIM_DMA_CPT1 = (1 << 7), /* Slaves: Capture 1 DMA request */ - HRTIM_DMA_CPT2 = (1 << 8), /* Slaves: Capture 2 DMA request */ - HRTIM_DMA_SET1 = (1 << 9), /* Slaves: Output 1 Set DMA request */ - HRTIM_DMA_RST1 = (1 << 10), /* Slaves: Output 1 Reset DMA request */ - HRTIM_DMA_SET2 = (1 << 11), /* Slaves: Output 2 Set DMA request */ - HRTIM_DMA_RST2 = (1 << 12), /* Slaves: Output 2 Reset DMA request */ - HRTIM_DMA_RST = (1 << 13), /* Slaves: Reset DMA request */ - HRTIM_DMA_DLYPRT = (1 << 14) /* Slaves: Delayed Protection DMA request */ -}; - -/* HRTIM Output IDLE state */ - -enum stm32_hrtim_idle_state -{ - HRTIM_IDLE_INACTIVE = 0, /* Output inactive during IDLE state */ - HRTIM_IDLE_ACTIVE = 1 /* Output active during IDLE state */ -}; - -/* HRTIM Burst Mode clock source */ - -enum stm32_hrtim_burst_source_e -{ - HRTIM_BURST_CLOCK_MASTER = 0, /* Master timer counter reset/roll-over */ - HRTIM_BURST_CLOCK_TIMA = 1, /* Timer A counter reset/roll-over */ - HRTIM_BURST_CLOCK_TIMB = 2, /* Timer B counter reset/roll-over */ - HRTIM_BURST_CLOCK_TIMC = 3, /* Timer C counter reset/roll-over */ - HRTIM_BURST_CLOCK_TIMD = 4, /* Timer D counter reset/roll-over */ - HRTIM_BURST_CLOCK_TIME = 5, /* Timer E counter reset/roll-over */ - HRTIM_BURST_CLOCK_EV1 = 6, /* On-chip Event 1 */ - HRTIM_BURST_CLOCK_EV2 = 7, /* On-chip Event 2 */ - HRTIM_BURST_CLOCK_EV3 = 8, /* On-chip Event 3 */ - HRTIM_BURST_CLOCK_EV4 = 9, /* On-chip Event 4 */ - HRTIM_BURST_CLOCK_HRTIM = 10 /* Prescaled f_HRTIM clock */ -}; - -/* HRTIM Burst Mode prescaler for fHRTIM clock */ - -enum stm32_hrtim_burst_precaler_e -{ - HRTIM_BURST_PRESCALER_1 = 0, - HRTIM_BURST_PRESCALER_2 = 1, - HRTIM_BURST_PRESCALER_4 = 2, - HRTIM_BURST_PRESCALER_8 = 3, - HRTIM_BURST_PRESCALER_16 = 4, - HRTIM_BURST_PRESCALER_32 = 5, - HRTIM_BURST_PRESCALER_64 = 6, - HRTIM_BURST_PRESCALER_128 = 7, - HRTIM_BURST_PRESCALER_256 = 8, - HRTIM_BURST_PRESCALER_512 = 9, - HRTIM_BURST_PRESCALER_1024 = 10, - HRTIM_BURST_PRESCALER_2048 = 11, - HRTIM_BURST_PRESCALER_4096 = 12, - HRTIM_BURST_PRESCALER_8192 = 13, - HRTIM_BURST_PRESCALER_16384 = 14, - HRTIM_BURST_PRESCALER_32768 = 15 -}; - -/* HRTIM Burst Mode triggers */ - -enum stm32_hrtim_burst_triggers_e -{ - HRTIM_BURST_TRG_MSTRST = (1 << 1), - HRTIM_BURST_TRG_MSTREP = (1 << 2), - HRTIM_BURST_TRG_MSTCMP1 = (1 << 3), - HRTIM_BURST_TRG_MSTCMP2 = (1 << 4), - HRTIM_BURST_TRG_MSTCMP3 = (1 << 5), - HRTIM_BURST_TRG_MSTCMP4 = (1 << 6), - HRTIM_BURST_TRG_TARST = (1 << 7), - HRTIM_BURST_TRG_TAREP = (1 << 8), - HRTIM_BURST_TRG_TACMP1 = (1 << 9), - HRTIM_BURST_TRG_TACMP2 = (1 << 10), - HRTIM_BURST_TRG_TBRST = (1 << 11), - HRTIM_BURST_TRG_TBREP = (1 << 12), - HRTIM_BURST_TRG_TBCMP1 = (1 << 13), - HRTIM_BURST_TRG_TBCMP2 = (1 << 14), - HRTIM_BURST_TRG_TCRST = (1 << 15), - HRTIM_BURST_TRG_TCREP = (1 << 16), - HRTIM_BURST_TRG_TCCMP1 = (1 << 17), - HRTIM_BURST_TRG_TCCMP2 = (1 << 18), - HRTIM_BURST_TRG_TDRST = (1 << 19), - HRTIM_BURST_TRG_TDREP = (1 << 20), - HRTIM_BURST_TRG_TDCMP1 = (1 << 21), - HRTIM_BURST_TRG_TDCMP2 = (1 << 22), - HRTIM_BURST_TRG_TERST = (1 << 23), - HRTIM_BURST_TRG_TEREP = (1 << 24), - HRTIM_BURST_TRG_TECMP1 = (1 << 25), - HRTIM_BURST_TRG_TECMP2 = (1 << 26), - HRTIM_BURST_TRG_TAEEV7 = (1 << 27), - HRTIM_BURST_TRG_TDEEV8 = (1 << 28), - HRTIM_BURST_TRG_EEV7 = (1 << 29), - HRTIM_BURST_TRG_EEV8 = (1 << 30), - HRTIM_BURST_TRG_OCHPEV = (1 << 31), -}; - -/* HRTIM Capture triggers */ - -enum stm32_hrtim_capture_index_e -{ - HRTIM_CAPTURE1 = 0, - HRTIM_CAPTURE2 = 1 -}; - -/* HRTIM Capture triggers */ - -enum stm32_hrtim_capture_triggers_e -{ - HRTIM_CAPTURE_TRG_SW = (1 << 0), - HRTIM_CAPTURE_TRG_UPD = (1 << 1), - HRTIM_CAPTURE_TRG_EXEV1 = (1 << 2), - HRTIM_CAPTURE_TRG_EXEV2 = (1 << 3), - HRTIM_CAPTURE_TRG_EXEV3 = (1 << 4), - HRTIM_CAPTURE_TRG_EXEV4 = (1 << 5), - HRTIM_CAPTURE_TRG_EXEV5 = (1 << 6), - HRTIM_CAPTURE_TRG_EXEV6 = (1 << 7), - HRTIM_CAPTURE_TRG_EXEV7 = (1 << 8), - HRTIM_CAPTURE_TRG_EXEV8 = (1 << 9), - HRTIM_CAPTURE_TRG_EXEV9 = (1 << 10), - HRTIM_CAPTURE_TRG_EXEV10 = (1 << 11), - HRTIM_CAPTURE_TRG_TA1SET = (1 << 12), - HRTIM_CAPTURE_TRG_TA1RST = (1 << 13), - HRTIM_CAPTURE_TRG_TACMP1 = (1 << 14), - HRTIM_CAPTURE_TRG_TACMP2 = (1 << 15), - HRTIM_CAPTURE_TRG_TB1SET = (1 << 16), - HRTIM_CAPTURE_TRG_TB1RST = (1 << 17), - HRTIM_CAPTURE_TRG_TBCMP1 = (1 << 18), - HRTIM_CAPTURE_TRG_TBCMP2 = (1 << 19), - HRTIM_CAPTURE_TRG_TC1SET = (1 << 20), - HRTIM_CAPTURE_TRG_TC1RST = (1 << 21), - HRTIM_CAPTURE_TRG_TCCMP1 = (1 << 22), - HRTIM_CAPTURE_TRG_TCCMP2 = (1 << 23), - HRTIM_CAPTURE_TRG_TD1SET = (1 << 24), - HRTIM_CAPTURE_TRG_TD1RST = (1 << 25), - HRTIM_CAPTURE_TRG_TDCMP1 = (1 << 26), - HRTIM_CAPTURE_TRG_TDCMP2 = (1 << 27), - HRTIM_CAPTURE_TRG_TE1SET = (1 << 28), - HRTIM_CAPTURE_TRG_TE1RST = (1 << 29), - HRTIM_CAPTURE_TRG_TECMP1 = (1 << 30), - HRTIM_CAPTURE_TRG_TECMP2 = (1 << 31), -}; - -/* HRTIM vtable */ - -struct hrtim_dev_s; -struct stm32_hrtim_ops_s -{ - int (*cmp_update)(struct hrtim_dev_s *dev, uint8_t timer, - uint8_t index, uint16_t cmp); - int (*per_update)(struct hrtim_dev_s *dev, - uint8_t timer, uint16_t per); - int (*rep_update)(struct hrtim_dev_s *dev, - uint8_t timer, uint8_t rep); - uint16_t (*per_get)(struct hrtim_dev_s *dev, uint8_t timer); - uint16_t (*cmp_get)(struct hrtim_dev_s *dev, uint8_t timer, - uint8_t index); - uint64_t (*fclk_get)(struct hrtim_dev_s *dev, uint8_t timer); - int (*soft_update)(struct hrtim_dev_s *dev, uint8_t timer); - int (*soft_reset)(struct hrtim_dev_s *dev, uint8_t timer); - int (*freq_set)(struct hrtim_dev_s *dev, uint8_t timer, - uint64_t freq); - int (*tim_enable)(struct hrtim_dev_s *dev, uint8_t timers, - bool state); - -#ifdef CONFIG_STM32_HRTIM_INTERRUPTS - int (*irq_ack)(struct hrtim_dev_s *dev, - uint8_t timer, int source); - uint16_t (*irq_get)(struct hrtim_dev_s *dev, uint8_t timer); -#endif -#ifdef CONFIG_STM32_HRTIM_PWM - int (*outputs_enable)(struct hrtim_dev_s *dev, uint16_t outputs, - bool state); - int (*output_set_set)(struct hrtim_dev_s *dev, uint16_t output, - uint32_t set); - int (*output_rst_set)(struct hrtim_dev_s *dev, uint16_t output, - uint32_t rst); -#endif -#ifdef CONFIG_STM32_HRTIM_BURST - int (*burst_enable)(struct hrtim_dev_s *dev, bool state); - int (*burst_cmp_set)(struct hrtim_dev_s *dev, uint16_t cmp); - int (*burst_per_set)(struct hrtim_dev_s *dev, uint16_t per); - int (*burst_pre_set)(struct hrtim_dev_s *dev, uint8_t pre); - uint16_t (*burst_cmp_get)(struct hrtim_dev_s *dev); - uint16_t (*burst_per_get)(struct hrtim_dev_s *dev); - int (*burst_pre_get)(struct hrtim_dev_s *dev); -#endif -#ifdef CONFIG_STM32_HRTIM_CHOPPER - int (*chopper_enable)(struct hrtim_dev_s *dev, uint8_t timer, - uint8_t chan, bool state); -#endif -#ifdef CONFIG_STM32_HRTIM_DEADTIME - int (*deadtime_update)(struct hrtim_dev_s *dev, uint8_t timer, - uint8_t dt, uint16_t value); - uint16_t (*deadtime_get)(struct hrtim_dev_s *dev, uint8_t timer, - uint8_t dt); -#endif -#ifdef CONFIG_STM32_HRTIM_CAPTURE - uint16_t (*capture_get)(struct hrtim_dev_s *dev, uint8_t timer, - uint8_t index); - int (*soft_capture)(struct hrtim_dev_s *dev, uint8_t timer, - uint8_t index); - -#endif -}; - -/* HRTIM device structure */ - -struct hrtim_dev_s -{ -#ifdef CONFIG_STM32_HRTIM - /* Fields managed by common upper half HRTIM logic */ - - uint8_t hd_ocount; /* The number of times the device has been opened */ -#endif - - /* Fields provided by lower half HRTIM logic */ - - const struct stm32_hrtim_ops_s *hd_ops; /* HRTIM operations */ - void *hd_priv; /* Used by the arch-specific logic */ - bool initialized; /* true: HRTIM driver has been initialized */ -}; - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -#ifndef __ASSEMBLY__ -#ifdef __cplusplus -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Name: stm32_hrtiminitialize - * - * Description: - * Initialize the HRTIM. - * - * Input Parameters: - * None - * - * Returned Value: - * Valid HRTIM device structure reference on success; a NULL on failure. - * - * Assumptions: - * 1. Clock to the HRTIM block has enabled, - * 2. Board-specific logic has already configured - * - ****************************************************************************/ - -struct hrtim_dev_s *stm32_hrtiminitialize(void); - -/**************************************************************************** - * Name: hrtim_register - ****************************************************************************/ - -#ifndef CONFIG_STM32_HRTIM_DISABLE_CHARDRV -int hrtim_register(const char *path, struct hrtim_dev_s *dev); -#endif - -#undef EXTERN -#ifdef __cplusplus -} -#endif -#endif /* __ASSEMBLY__ */ - -#endif /* CONFIG_STM32_HRTIM1 */ -#endif /* __ARCH_ARM_SRC_STM32_STM32_HRTIM_H */ diff --git a/arch/arm/src/stm32/stm32_i2c.c b/arch/arm/src/stm32/stm32_i2c.c deleted file mode 100644 index da30fd1342d72..0000000000000 --- a/arch/arm/src/stm32/stm32_i2c.c +++ /dev/null @@ -1,1945 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_i2c.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* Supports: - * - Master operation, 100 kHz (standard) and 400 kHz (full speed) - * - Multiple instances (shared bus) - * - Interrupt based operation - * - * Structure naming: - * - Device: structure as defined by the nuttx/i2c/i2c.h - * - Instance: represents each individual access to the I2C driver, obtained - * by the i2c_init(); it extends the Device structure from the - * nuttx/i2c/i2c.h; - * Instance points to OPS, to common I2C Hardware private data and - * contains its own private data, as frequency, address, mode of - * operation (in the future) - * - Private: Private data of an I2C Hardware - * - * TODO - * - Check for all possible deadlocks (as BUSY='1' I2C needs to be reset in - * HW using the I2C_CR1_SWRST) - * - SMBus support (hardware layer timings are already supported) and add - * SMBA gpio pin - * - Slave support with multiple addresses (on multiple instances): - * - 2 x 7-bit address or - * - 1 x 10 bit addresses + 1 x 7 bit address (?) - * - plus the broadcast address (general call) - * - Multi-master support - * - DMA (to get rid of too many CPU wake-ups and interventions) - * - Be ready for IPMI - */ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include - -#include - -#include "arm_internal.h" -#include "stm32_rcc.h" -#include "stm32_i2c.h" -#include "stm32_waste.h" - -/* At least one I2C peripheral must be enabled */ - -#if defined(CONFIG_STM32_I2C1) || defined(CONFIG_STM32_I2C2) || \ - defined(CONFIG_STM32_I2C3) - -/* This implementation is for the STM32 F1, F2, and F4 only. - * Experimentally enabled for STM32L15XX. - */ - -#if defined(CONFIG_STM32_STM32L15XX) || defined(CONFIG_STM32_STM32F10XX) || \ - defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#if STM32_PCLK1_FREQUENCY < 4000000 -# warning "STM32_I2C: Periph clk must be at least 4MHz to support 400kHz." -#endif - -#if STM32_PCLK1_FREQUENCY < 2000000 -# error "STM32_I2C: Periph clk must be at least 2MHz to support 100kHz." -#endif - -/* Configuration ************************************************************/ - -/* CONFIG_I2C_POLLED may be set so that I2C interrupts will not be used. - * Instead, CPU-intensive polling will be used. - */ - -/* Interrupt wait timeout in seconds and milliseconds */ - -#if !defined(CONFIG_STM32_I2CTIMEOSEC) && !defined(CONFIG_STM32_I2CTIMEOMS) -# define CONFIG_STM32_I2CTIMEOSEC 0 -# define CONFIG_STM32_I2CTIMEOMS 500 /* Default is 500 milliseconds */ -#elif !defined(CONFIG_STM32_I2CTIMEOSEC) -# define CONFIG_STM32_I2CTIMEOSEC 0 /* User provided milliseconds */ -#elif !defined(CONFIG_STM32_I2CTIMEOMS) -# define CONFIG_STM32_I2CTIMEOMS 0 /* User provided seconds */ -#endif - -/* Interrupt wait time timeout in system timer ticks */ - -#ifndef CONFIG_STM32_I2CTIMEOTICKS -# define CONFIG_STM32_I2CTIMEOTICKS \ - (SEC2TICK(CONFIG_STM32_I2CTIMEOSEC) + MSEC2TICK(CONFIG_STM32_I2CTIMEOMS)) -#endif - -#ifndef CONFIG_STM32_I2C_DYNTIMEO_STARTSTOP -# define CONFIG_STM32_I2C_DYNTIMEO_STARTSTOP TICK2USEC(CONFIG_STM32_I2CTIMEOTICKS) -#endif - -/* On the STM32F103ZE, there is an internal conflict between I2C1 and FSMC. - * In that case, it is necessary to disable FSMC before each I2C1 access - * and re-enable FSMC when the I2C access completes. - */ - -#undef I2C1_FSMC_CONFLICT -#if defined(CONFIG_STM32_STM32F10XX) && defined(CONFIG_STM32_FSMC) && defined(CONFIG_STM32_I2C1) -# define I2C1_FSMC_CONFLICT -#endif - -/* Macros to convert a I2C pin to a GPIO output */ - -#if defined(CONFIG_STM32_STM32L15XX) -# define I2C_OUTPUT (GPIO_OUTPUT | GPIO_OUTPUT_SET | GPIO_OPENDRAIN | \ - GPIO_SPEED_40MHz) -#elif defined(CONFIG_STM32_STM32F10XX) -# define I2C_OUTPUT (GPIO_OUTPUT | GPIO_OUTPUT_SET | GPIO_CNF_OUTOD | \ - GPIO_MODE_50MHz) -#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) -# define I2C_OUTPUT (GPIO_OUTPUT | GPIO_FLOAT | GPIO_OPENDRAIN |\ - GPIO_SPEED_50MHz | GPIO_OUTPUT_SET) -#endif - -#define MKI2C_OUTPUT(p) (((p) & (GPIO_PORT_MASK | GPIO_PIN_MASK)) | I2C_OUTPUT) - -/* Debug ********************************************************************/ - -/* I2C event trace logic. NOTE: trace uses the internal, non-standard, - * low-level debug interface syslog() but does not require that any other - * debug is enabled. - */ - -#ifndef CONFIG_I2C_TRACE -# define stm32_i2c_tracereset(p) -# define stm32_i2c_tracenew(p,s) -# define stm32_i2c_traceevent(p,e,a) -# define stm32_i2c_tracedump(p) -#endif - -#ifndef CONFIG_I2C_NTRACE -# define CONFIG_I2C_NTRACE 32 -#endif - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/* Interrupt state */ - -enum stm32_intstate_e -{ - INTSTATE_IDLE = 0, /* No I2C activity */ - INTSTATE_WAITING, /* Waiting for completion of interrupt activity */ - INTSTATE_DONE, /* Interrupt activity complete */ -}; - -/* Trace events */ - -enum stm32_trace_e -{ - I2CEVENT_NONE = 0, /* No events have occurred with this status */ - I2CEVENT_SENDADDR, /* Start/Master bit set and address sent, param = msgc */ - I2CEVENT_SENDBYTE, /* Send byte, param = dcnt */ - I2CEVENT_ITBUFEN, /* Enable buffer interrupts, param = 0 */ - I2CEVENT_RCVBYTE, /* Read more dta, param = dcnt */ - I2CEVENT_REITBUFEN, /* Re-enable buffer interrupts, param = 0 */ - I2CEVENT_DISITBUFEN, /* Disable buffer interrupts, param = 0 */ - I2CEVENT_BTFNOSTART, /* BTF on last byte with no restart, param = msgc */ - I2CEVENT_BTFRESTART, /* Last byte sent, re-starting, param = msgc */ - I2CEVENT_BTFSTOP, /* Last byte sten, send stop, param = 0 */ - I2CEVENT_ERROR /* Error occurred, param = 0 */ -}; - -/* Trace data */ - -struct stm32_trace_s -{ - uint32_t status; /* I2C 32-bit SR2|SR1 status */ - uint32_t count; /* Interrupt count when status change */ - enum stm32_intstate_e event; /* Last event that occurred with this status */ - uint32_t parm; /* Parameter associated with the event */ - clock_t time; /* First of event or first status */ -}; - -/* I2C Device hardware configuration */ - -struct stm32_i2c_config_s -{ - uint32_t base; /* I2C base address */ - uint32_t clk_bit; /* Clock enable bit */ - uint32_t reset_bit; /* Reset bit */ - uint32_t scl_pin; /* GPIO configuration for SCL as SCL */ - uint32_t sda_pin; /* GPIO configuration for SDA as SDA */ -#ifndef CONFIG_I2C_POLLED - uint32_t ev_irq; /* Event IRQ */ - uint32_t er_irq; /* Error IRQ */ -#endif -}; - -/* I2C Device Private Data */ - -struct stm32_i2c_priv_s -{ - /* Standard I2C operations */ - - const struct i2c_ops_s *ops; - - /* Port configuration */ - - const struct stm32_i2c_config_s *config; - - int refs; /* Reference count */ - mutex_t lock; /* Mutual exclusion lock */ -#ifndef CONFIG_I2C_POLLED - sem_t sem_isr; /* Interrupt wait semaphore */ -#endif - volatile uint8_t intstate; /* Interrupt handshake (see enum stm32_intstate_e) */ - - uint8_t msgc; /* Message count */ - struct i2c_msg_s *msgv; /* Message list */ - uint8_t *ptr; /* Current message buffer */ - uint32_t frequency; /* Current I2C frequency */ - int dcnt; /* Current message length */ - uint16_t flags; /* Current message flags */ - - /* I2C trace support */ - -#ifdef CONFIG_I2C_TRACE - int tndx; /* Trace array index */ - clock_t start_time; /* Time when the trace was started */ - - /* The actual trace data */ - - struct stm32_trace_s trace[CONFIG_I2C_NTRACE]; -#endif - - uint32_t status; /* End of transfer SR2|SR1 status */ -}; - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -static inline uint16_t stm32_i2c_getreg(struct stm32_i2c_priv_s *priv, - uint8_t offset); -static inline void stm32_i2c_putreg(struct stm32_i2c_priv_s *priv, - uint8_t offset, uint16_t value); -static inline void stm32_i2c_modifyreg(struct stm32_i2c_priv_s *priv, - uint8_t offset, uint16_t clearbits, - uint16_t setbits); - -#ifdef CONFIG_STM32_I2C_DYNTIMEO -static uint32_t stm32_i2c_toticks(int msgc, struct i2c_msg_s *msgs); -#endif /* CONFIG_STM32_I2C_DYNTIMEO */ - -static inline int stm32_i2c_sem_waitdone(struct stm32_i2c_priv_s *priv); -static inline void stm32_i2c_sem_waitstop(struct stm32_i2c_priv_s *priv); - -#ifdef CONFIG_I2C_TRACE -static void stm32_i2c_tracereset(struct stm32_i2c_priv_s *priv); -static void stm32_i2c_tracenew(struct stm32_i2c_priv_s *priv, - uint32_t status); -static void stm32_i2c_traceevent(struct stm32_i2c_priv_s *priv, - enum stm32_trace_e event, uint32_t parm); -static void stm32_i2c_tracedump(struct stm32_i2c_priv_s *priv); -#endif /* CONFIG_I2C_TRACE */ - -static void stm32_i2c_setclock(struct stm32_i2c_priv_s *priv, - uint32_t frequency); -static inline void stm32_i2c_sendstart(struct stm32_i2c_priv_s *priv); -static inline void stm32_i2c_clrstart(struct stm32_i2c_priv_s *priv); -static inline void stm32_i2c_sendstop(struct stm32_i2c_priv_s *priv); -static inline -uint32_t stm32_i2c_getstatus(struct stm32_i2c_priv_s *priv); - -#ifdef I2C1_FSMC_CONFLICT -static inline -uint32_t stm32_i2c_disablefsmc(struct stm32_i2c_priv_s *priv); -static inline void stm32_i2c_enablefsmc(uint32_t ahbenr); -#endif /* I2C1_FSMC_CONFLICT */ - -static int stm32_i2c_isr_process(struct stm32_i2c_priv_s *priv); - -#ifndef CONFIG_I2C_POLLED -static int stm32_i2c_isr(int irq, void *context, void *arg); -#endif /* !CONFIG_I2C_POLLED */ - -static int stm32_i2c_init(struct stm32_i2c_priv_s *priv); -static int stm32_i2c_deinit(struct stm32_i2c_priv_s *priv); -static int stm32_i2c_transfer(struct i2c_master_s *dev, - struct i2c_msg_s *msgs, int count); -#ifdef CONFIG_I2C_RESET -static int stm32_i2c_reset(struct i2c_master_s *dev); -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* Trace events strings */ - -#ifdef CONFIG_I2C_TRACE -static const char *g_trace_names[] = -{ - "NONE ", - "SENDADDR ", - "SENDBYTE ", - "ITBUFEN ", - "RCVBYTE ", - "REITBUFEN ", - "DISITBUFEN", - "BTFNOSTART", - "BTFRESTART", - "BTFSTOP ", - "ERROR " -}; -#endif - -/* I2C interface */ - -static const struct i2c_ops_s stm32_i2c_ops = -{ - .transfer = stm32_i2c_transfer -#ifdef CONFIG_I2C_RESET - , .reset = stm32_i2c_reset -#endif -}; - -/* I2C device structures */ - -#ifdef CONFIG_STM32_I2C1 -static const struct stm32_i2c_config_s stm32_i2c1_config = -{ - .base = STM32_I2C1_BASE, - .clk_bit = RCC_APB1ENR_I2C1EN, - .reset_bit = RCC_APB1RSTR_I2C1RST, - .scl_pin = GPIO_I2C1_SCL, - .sda_pin = GPIO_I2C1_SDA, -#ifndef CONFIG_I2C_POLLED - .ev_irq = STM32_IRQ_I2C1EV, - .er_irq = STM32_IRQ_I2C1ER -#endif -}; - -static struct stm32_i2c_priv_s stm32_i2c1_priv = -{ - .ops = &stm32_i2c_ops, - .config = &stm32_i2c1_config, - .refs = 0, - .lock = NXMUTEX_INITIALIZER, -#ifndef CONFIG_I2C_POLLED - .sem_isr = SEM_INITIALIZER(0), -#endif - .intstate = INTSTATE_IDLE, - .msgc = 0, - .msgv = NULL, - .ptr = NULL, - .dcnt = 0, - .flags = 0, - .status = 0 -}; -#endif - -#ifdef CONFIG_STM32_I2C2 -static const struct stm32_i2c_config_s stm32_i2c2_config = -{ - .base = STM32_I2C2_BASE, - .clk_bit = RCC_APB1ENR_I2C2EN, - .reset_bit = RCC_APB1RSTR_I2C2RST, - .scl_pin = GPIO_I2C2_SCL, - .sda_pin = GPIO_I2C2_SDA, -#ifndef CONFIG_I2C_POLLED - .ev_irq = STM32_IRQ_I2C2EV, - .er_irq = STM32_IRQ_I2C2ER -#endif -}; - -static struct stm32_i2c_priv_s stm32_i2c2_priv = -{ - .ops = &stm32_i2c_ops, - .config = &stm32_i2c2_config, - .refs = 0, - .lock = NXMUTEX_INITIALIZER, -#ifndef CONFIG_I2C_POLLED - .sem_isr = SEM_INITIALIZER(0), -#endif - .intstate = INTSTATE_IDLE, - .msgc = 0, - .msgv = NULL, - .ptr = NULL, - .dcnt = 0, - .flags = 0, - .status = 0 -}; -#endif - -#ifdef CONFIG_STM32_I2C3 -static const struct stm32_i2c_config_s stm32_i2c3_config = -{ - .base = STM32_I2C3_BASE, - .clk_bit = RCC_APB1ENR_I2C3EN, - .reset_bit = RCC_APB1RSTR_I2C3RST, - .scl_pin = GPIO_I2C3_SCL, - .sda_pin = GPIO_I2C3_SDA, -#ifndef CONFIG_I2C_POLLED - .ev_irq = STM32_IRQ_I2C3EV, - .er_irq = STM32_IRQ_I2C3ER -#endif -}; - -static struct stm32_i2c_priv_s stm32_i2c3_priv = -{ - .ops = &stm32_i2c_ops, - .config = &stm32_i2c3_config, - .refs = 0, - .lock = NXMUTEX_INITIALIZER, -#ifndef CONFIG_I2C_POLLED - .sem_isr = SEM_INITIALIZER(0), -#endif - .intstate = INTSTATE_IDLE, - .msgc = 0, - .msgv = NULL, - .ptr = NULL, - .dcnt = 0, - .flags = 0, - .status = 0 -}; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_i2c_getreg - * - * Description: - * Get a 16-bit register value by offset - * - ****************************************************************************/ - -static inline uint16_t stm32_i2c_getreg(struct stm32_i2c_priv_s *priv, - uint8_t offset) -{ - return getreg16(priv->config->base + offset); -} - -/**************************************************************************** - * Name: stm32_i2c_putreg - * - * Description: - * Put a 16-bit register value by offset - * - ****************************************************************************/ - -static inline void stm32_i2c_putreg(struct stm32_i2c_priv_s *priv, - uint8_t offset, uint16_t value) -{ - putreg16(value, priv->config->base + offset); -} - -/**************************************************************************** - * Name: stm32_i2c_modifyreg - * - * Description: - * Modify a 16-bit register value by offset - * - ****************************************************************************/ - -static inline void stm32_i2c_modifyreg(struct stm32_i2c_priv_s *priv, - uint8_t offset, uint16_t clearbits, - uint16_t setbits) -{ - modifyreg16(priv->config->base + offset, clearbits, setbits); -} - -/**************************************************************************** - * Name: stm32_i2c_toticks - * - * Description: - * Return a micro-second delay based on the number of bytes left to be - * processed. - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_I2C_DYNTIMEO -static uint32_t stm32_i2c_toticks(int msgc, struct i2c_msg_s *msgs) -{ - size_t bytecount = 0; - int i; - - /* Count the number of bytes left to process */ - - for (i = 0; i < msgc; i++) - { - bytecount += msgs[i].length; - } - - /* Then return a number of microseconds based on a user provided scaling - * factor. - */ - - return USEC2TICK(CONFIG_STM32_I2C_DYNTIMEO_USECPERBYTE * bytecount); -} -#endif - -/**************************************************************************** - * Name: stm32_i2c_sem_waitdone - * - * Description: - * Wait for a transfer to complete - * - ****************************************************************************/ - -#ifndef CONFIG_I2C_POLLED -static inline int stm32_i2c_sem_waitdone(struct stm32_i2c_priv_s *priv) -{ - irqstate_t flags; - uint32_t regval; - int ret; - - flags = enter_critical_section(); - - /* Enable I2C interrupts */ - - regval = stm32_i2c_getreg(priv, STM32_I2C_CR2_OFFSET); - regval |= (I2C_CR2_ITERREN | I2C_CR2_ITEVFEN); - stm32_i2c_putreg(priv, STM32_I2C_CR2_OFFSET, regval); - - /* Signal the interrupt handler that we are waiting. NOTE: Interrupts - * are currently disabled but will be temporarily re-enabled below when - * nxsem_tickwait_uninterruptible() sleeps. - */ - - priv->intstate = INTSTATE_WAITING; - do - { - /* Wait until either the transfer is complete or the timeout expires */ - -#ifdef CONFIG_STM32_I2C_DYNTIMEO - ret = nxsem_tickwait_uninterruptible(&priv->sem_isr, - stm32_i2c_toticks(priv->msgc, priv->msgv)); -#else - ret = nxsem_tickwait_uninterruptible(&priv->sem_isr, - CONFIG_STM32_I2CTIMEOTICKS); -#endif - if (ret < 0) - { - /* Break out of the loop on irrecoverable errors. This would - * include timeouts and mystery errors reported by - * nxsem_tickwait_uninterruptible. - */ - - break; - } - } - - /* Loop until the interrupt level transfer is complete. */ - - while (priv->intstate != INTSTATE_DONE); - - /* Set the interrupt state back to IDLE */ - - priv->intstate = INTSTATE_IDLE; - - /* Disable I2C interrupts */ - - regval = stm32_i2c_getreg(priv, STM32_I2C_CR2_OFFSET); - regval &= ~I2C_CR2_ALLINTS; - stm32_i2c_putreg(priv, STM32_I2C_CR2_OFFSET, regval); - - leave_critical_section(flags); - return ret; -} -#else -static inline int stm32_i2c_sem_waitdone(struct stm32_i2c_priv_s *priv) -{ - clock_t timeout; - clock_t start; - clock_t elapsed; - int ret; - - /* Get the timeout value */ - -#ifdef CONFIG_STM32_I2C_DYNTIMEO - timeout = stm32_i2c_toticks(priv->msgc, priv->msgv); -#else - timeout = CONFIG_STM32_I2CTIMEOTICKS; -#endif - - /* Signal the interrupt handler that we are waiting. NOTE: Interrupts - * are currently disabled but will be temporarily re-enabled below when - * nxsem_tickwait_uninterruptible() sleeps. - */ - - priv->intstate = INTSTATE_WAITING; - start = clock_systime_ticks(); - - do - { - /* Calculate the elapsed time */ - - elapsed = clock_systime_ticks() - start; - - /* Poll by simply calling the timer interrupt handler until it - * reports that it is done. - */ - - stm32_i2c_isr_process(priv); - } - - /* Loop until the transfer is complete. */ - - while (priv->intstate != INTSTATE_DONE && elapsed < timeout); - - i2cinfo("intstate: %d elapsed: %ld threshold: %ld status: %08" PRIx32 "\n", - priv->intstate, (long)elapsed, (long)timeout, priv->status); - - /* Set the interrupt state back to IDLE */ - - ret = priv->intstate == INTSTATE_DONE ? OK : -ETIMEDOUT; - priv->intstate = INTSTATE_IDLE; - return ret; -} -#endif - -/**************************************************************************** - * Name: stm32_i2c_sem_waitstop - * - * Description: - * Wait for a STOP to complete - * - ****************************************************************************/ - -static inline void stm32_i2c_sem_waitstop(struct stm32_i2c_priv_s *priv) -{ - clock_t start; - clock_t elapsed; - clock_t timeout; - uint32_t cr1; - uint32_t sr1; - - /* Select a timeout */ - -#ifdef CONFIG_STM32_I2C_DYNTIMEO - timeout = USEC2TICK(CONFIG_STM32_I2C_DYNTIMEO_STARTSTOP); -#else - timeout = CONFIG_STM32_I2CTIMEOTICKS; -#endif - - /* Wait as stop might still be in progress; but stop might also - * be set because of a timeout error: "The [STOP] bit is set and - * cleared by software, cleared by hardware when a Stop condition is - * detected, set by hardware when a timeout error is detected." - */ - - start = clock_systime_ticks(); - do - { - /* Calculate the elapsed time */ - - elapsed = clock_systime_ticks() - start; - - /* Check for STOP condition */ - - cr1 = stm32_i2c_getreg(priv, STM32_I2C_CR1_OFFSET); - if ((cr1 & I2C_CR1_STOP) == 0) - { - return; - } - - /* Check for timeout error */ - - sr1 = stm32_i2c_getreg(priv, STM32_I2C_SR1_OFFSET); - if ((sr1 & I2C_SR1_TIMEOUT) != 0) - { - return; - } - } - - /* Loop until the stop is complete or a timeout occurs. */ - - while (elapsed < timeout); - - /* If we get here then a timeout occurred with the STOP condition - * still pending. - */ - - i2cinfo("Timeout with CR1: %04" PRIx32 " SR1: %04" PRIx32 "\n", cr1, sr1); -} - -/**************************************************************************** - * Name: stm32_i2c_trace* - * - * Description: - * I2C trace instrumentation - * - ****************************************************************************/ - -#ifdef CONFIG_I2C_TRACE -static void stm32_i2c_traceclear(struct stm32_i2c_priv_s *priv) -{ - struct stm32_trace_s *trace = &priv->trace[priv->tndx]; - - trace->status = 0; /* I2C 32-bit SR2|SR1 status */ - trace->count = 0; /* Interrupt count when status change */ - trace->event = I2CEVENT_NONE; /* Last event that occurred with this status */ - trace->parm = 0; /* Parameter associated with the event */ - trace->time = 0; /* Time of first status or event */ -} - -static void stm32_i2c_tracereset(struct stm32_i2c_priv_s *priv) -{ - /* Reset the trace info for a new data collection */ - - priv->tndx = 0; - priv->start_time = clock_systime_ticks(); - stm32_i2c_traceclear(priv); -} - -static void stm32_i2c_tracenew(struct stm32_i2c_priv_s *priv, - uint32_t status) -{ - struct stm32_trace_s *trace = &priv->trace[priv->tndx]; - - /* Is the current entry uninitialized? Has the status changed? */ - - if (trace->count == 0 || status != trace->status) - { - /* Yes.. Was it the status changed? */ - - if (trace->count != 0) - { - /* Yes.. bump up the trace index - * (unless we are out of trace entries) - */ - - if (priv->tndx >= (CONFIG_I2C_NTRACE - 1)) - { - i2cerr("ERROR: Trace table overflow\n"); - return; - } - - priv->tndx++; - trace = &priv->trace[priv->tndx]; - } - - /* Initialize the new trace entry */ - - stm32_i2c_traceclear(priv); - trace->status = status; - trace->count = 1; - trace->time = clock_systime_ticks(); - } - else - { - /* Just increment the count of times that we have seen this status */ - - trace->count++; - } -} - -static void stm32_i2c_traceevent(struct stm32_i2c_priv_s *priv, - enum stm32_trace_e event, uint32_t parm) -{ - struct stm32_trace_s *trace; - - if (event != I2CEVENT_NONE) - { - trace = &priv->trace[priv->tndx]; - - /* Initialize the new trace entry */ - - trace->event = event; - trace->parm = parm; - - /* Bump up the trace index (unless we are out of trace entries) */ - - if (priv->tndx >= (CONFIG_I2C_NTRACE - 1)) - { - i2cerr("ERROR: Trace table overflow\n"); - return; - } - - priv->tndx++; - stm32_i2c_traceclear(priv); - } -} - -static void stm32_i2c_tracedump(struct stm32_i2c_priv_s *priv) -{ - struct stm32_trace_s *trace; - int i; - - syslog(LOG_DEBUG, "Elapsed time: %ld\n", - (long)(clock_systime_ticks() - priv->start_time)); - - for (i = 0; i < priv->tndx; i++) - { - trace = &priv->trace[i]; - syslog(LOG_DEBUG, - "%2d. STATUS: %08" PRIx32 " COUNT: %3d EVENT: %s(%2d) PARM:" - " %08" PRIx32 " TIME: %d\n", - i + 1, trace->status, trace->count, g_trace_names[trace->event], - trace->event, trace->parm, trace->time - priv->start_time); - } -} -#endif /* CONFIG_I2C_TRACE */ - -/**************************************************************************** - * Name: stm32_i2c_setclock - * - * Description: - * Set the I2C clock - * - ****************************************************************************/ - -static void stm32_i2c_setclock(struct stm32_i2c_priv_s *priv, - uint32_t frequency) -{ - uint16_t cr1; - uint16_t ccr; - uint16_t trise; - uint16_t freqmhz; - uint16_t speed; - - /* Has the I2C bus frequency changed? */ - - if (frequency != priv->frequency) - { - /* Disable the selected I2C peripheral to configure TRISE */ - - cr1 = stm32_i2c_getreg(priv, STM32_I2C_CR1_OFFSET); - stm32_i2c_putreg(priv, STM32_I2C_CR1_OFFSET, cr1 & ~I2C_CR1_PE); - - /* Update timing and control registers */ - - freqmhz = (uint16_t)(STM32_PCLK1_FREQUENCY / 1000000); - ccr = 0; - - /* Configure speed in standard mode */ - - if (frequency <= 100000) - { - /* Standard mode speed calculation */ - - speed = (uint16_t)(STM32_PCLK1_FREQUENCY / (frequency << 1)); - - /* The CCR fault must be >= 4 */ - - if (speed < 4) - { - /* Set the minimum allowed value */ - - speed = 4; - } - - ccr |= speed; - - /* Set Maximum Rise Time for standard mode */ - - trise = freqmhz + 1; - } - - /* Configure speed in fast mode */ - - else /* (frequency <= 400000) */ - { - /* Fast mode speed calculation with Tlow/Thigh = 16/9 */ - -#ifdef CONFIG_STM32_I2C_DUTY16_9 - speed = (uint16_t)(STM32_PCLK1_FREQUENCY / (frequency * 25)); - - /* Set DUTY and fast speed bits */ - - ccr |= (I2C_CCR_DUTY | I2C_CCR_FS); -#else - /* Fast mode speed calculation with Tlow/Thigh = 2 */ - - speed = (uint16_t)(STM32_PCLK1_FREQUENCY / (frequency * 3)); - - /* Set fast speed bit */ - - ccr |= I2C_CCR_FS; -#endif - - /* Verify that the CCR speed value is nonzero */ - - if (speed < 1) - { - /* Set the minimum allowed value */ - - speed = 1; - } - - ccr |= speed; - - /* Set Maximum Rise Time for fast mode */ - - trise = (uint16_t)(((freqmhz * 300) / 1000) + 1); - } - - /* Write the new values of the CCR and TRISE registers */ - - stm32_i2c_putreg(priv, STM32_I2C_CCR_OFFSET, ccr); - stm32_i2c_putreg(priv, STM32_I2C_TRISE_OFFSET, trise); - - /* Bit 14 of OAR1 must be configured and kept at 1 */ - - stm32_i2c_putreg(priv, STM32_I2C_OAR1_OFFSET, I2C_OAR1_ONE); - - /* Re-enable the peripheral (or not) */ - - stm32_i2c_putreg(priv, STM32_I2C_CR1_OFFSET, cr1); - - /* Save the new I2C frequency */ - - priv->frequency = frequency; - } -} - -/**************************************************************************** - * Name: stm32_i2c_sendstart - * - * Description: - * Send the START conditions/force Master mode - * - ****************************************************************************/ - -static inline void stm32_i2c_sendstart(struct stm32_i2c_priv_s *priv) -{ - /* Disable ACK on receive by default and generate START */ - - stm32_i2c_modifyreg(priv, STM32_I2C_CR1_OFFSET, - I2C_CR1_ACK, I2C_CR1_START); -} - -/**************************************************************************** - * Name: stm32_i2c_clrstart - * - * Description: - * Clear the STOP, START or PEC condition on certain error recovery steps. - * - ****************************************************************************/ - -static inline void stm32_i2c_clrstart(struct stm32_i2c_priv_s *priv) -{ - /* "Note: When the STOP, START or PEC bit is set, the software must - * not perform any write access to I2C_CR1 before this bit is - * cleared by hardware. Otherwise there is a risk of setting a - * second STOP, START or PEC request." - * - * "The [STOP] bit is set and cleared by software, cleared by hardware - * when a Stop condition is detected, set by hardware when a timeout - * error is detected. - * - * "This [START] bit is set and cleared by software and cleared by hardware - * when start is sent or PE=0." The bit must be cleared by software if - * the START is never sent. - * - * "This [PEC] bit is set and cleared by software, and cleared by hardware - * when PEC is transferred or by a START or Stop condition or when PE=0." - */ - - stm32_i2c_modifyreg(priv, STM32_I2C_CR1_OFFSET, - I2C_CR1_START | I2C_CR1_STOP | I2C_CR1_PEC, 0); -} - -/**************************************************************************** - * Name: stm32_i2c_sendstop - * - * Description: - * Send the STOP conditions - * - ****************************************************************************/ - -static inline void stm32_i2c_sendstop(struct stm32_i2c_priv_s *priv) -{ - stm32_i2c_modifyreg(priv, STM32_I2C_CR1_OFFSET, I2C_CR1_ACK, I2C_CR1_STOP); -} - -/**************************************************************************** - * Name: stm32_i2c_getstatus - * - * Description: - * Get 32-bit status (SR1 and SR2 combined) - * - ****************************************************************************/ - -static inline uint32_t stm32_i2c_getstatus(struct stm32_i2c_priv_s *priv) -{ - uint32_t status = stm32_i2c_getreg(priv, STM32_I2C_SR1_OFFSET); - status |= (stm32_i2c_getreg(priv, STM32_I2C_SR2_OFFSET) << 16); - return status; -} - -/**************************************************************************** - * Name: stm32_i2c_disablefsmc - * - * Description: - * FSMC must be disable while accessing I2C1 because it uses a common - * resource (LBAR) - * - * NOTE: - * This is an issue with the STM32F103ZE, but may not be an issue with other - * STM32s. You may need to experiment - * - ****************************************************************************/ - -#ifdef I2C1_FSMC_CONFLICT -static inline -uint32_t stm32_i2c_disablefsmc(struct stm32_i2c_priv_s *priv) -{ - uint32_t ret = 0; - uint32_t regval; - - /* Is this I2C1 */ - -#if defined(CONFIG_STM32_I2C2) || defined(CONFIG_STM32_I2C3) - if (priv->config->base == STM32_I2C1_BASE) -#endif - { - /* Disable FSMC unconditionally */ - - ret = getreg32(STM32_RCC_AHBENR); - regval = ret & ~RCC_AHBENR_FSMCEN; - putreg32(regval, STM32_RCC_AHBENR); - } - - return ret; -} - -/**************************************************************************** - * Name: stm32_i2c_enablefsmc - * - * Description: - * Re-enable the FSMC - * - ****************************************************************************/ - -static inline void stm32_i2c_enablefsmc(uint32_t ahbenr) -{ - uint32_t regval; - - /* Enable AHB clocking to the FSMC only if it was previously enabled. */ - - if ((ahbenr & RCC_AHBENR_FSMCEN) != 0) - { - regval = getreg32(STM32_RCC_AHBENR); - regval |= RCC_AHBENR_FSMCEN; - putreg32(regval, STM32_RCC_AHBENR); - } -} -#else -# define stm32_i2c_disablefsmc(priv) (0) -# define stm32_i2c_enablefsmc(ahbenr) -#endif /* I2C1_FSMC_CONFLICT */ - -/**************************************************************************** - * Name: stm32_i2c_isr_process - * - * Description: - * Common Interrupt Service Routine - * - ****************************************************************************/ - -static int stm32_i2c_isr_process(struct stm32_i2c_priv_s *priv) -{ - uint32_t status = stm32_i2c_getstatus(priv); - - /* Check for new trace setup */ - - stm32_i2c_tracenew(priv, status); - - /* Was start bit sent */ - - if ((status & I2C_SR1_SB) != 0) - { - stm32_i2c_traceevent(priv, I2CEVENT_SENDADDR, priv->msgc); - - /* We check for msgc > 0 here as an unexpected interrupt with - * I2C_SR1_SB set due to noise on the I2C cable can otherwise cause - * msgc to wrap causing memory overwrite - */ - - if (priv->msgc > 0 && priv->msgv != NULL) - { - /* Get run-time data */ - - priv->ptr = priv->msgv->buffer; - priv->dcnt = priv->msgv->length; - priv->flags = priv->msgv->flags; - - /* Send address byte and define addressing mode */ - - stm32_i2c_putreg(priv, STM32_I2C_DR_OFFSET, - (priv->flags & I2C_M_TEN) ? - 0 : ((priv->msgv->addr << 1) | - (priv->flags & I2C_M_READ))); - - /* Set ACK for receive mode */ - - if (priv->dcnt > 1 && (priv->flags & I2C_M_READ) != 0) - { - stm32_i2c_modifyreg(priv, STM32_I2C_CR1_OFFSET, - 0, I2C_CR1_ACK); - } - - /* Increment to next pointer and decrement message count */ - - priv->msgv++; - priv->msgc--; - } - else - { - /* Clear ISR by writing to DR register */ - - stm32_i2c_putreg(priv, STM32_I2C_DR_OFFSET, 0); - } - } - - /* In 10-bit addressing mode, was first byte sent */ - - else if ((status & I2C_SR1_ADD10) != 0) - { - /* TODO: Finish 10-bit mode addressing. - * - * For now just clear ISR by writing to DR register. As we don't do - * 10 bit addressing this must be a spurious ISR - */ - - stm32_i2c_putreg(priv, STM32_I2C_DR_OFFSET, 0); - } - - /* Was address sent, continue with either sending or reading data */ - - else if ((priv->flags & I2C_M_READ) == 0 && - (status & (I2C_SR1_ADDR | I2C_SR1_TXE)) != 0) - { - if (priv->dcnt > 0) - { - /* Send a byte */ - - stm32_i2c_traceevent(priv, I2CEVENT_SENDBYTE, priv->dcnt); - stm32_i2c_putreg(priv, STM32_I2C_DR_OFFSET, *priv->ptr++); - priv->dcnt--; - } - } - - else if ((priv->flags & I2C_M_READ) != 0 && (status & I2C_SR1_ADDR) != 0) - { - /* Enable RxNE and TxE buffers in order to receive one or multiple - * bytes - */ - -#ifndef CONFIG_I2C_POLLED - stm32_i2c_traceevent(priv, I2CEVENT_ITBUFEN, 0); - stm32_i2c_modifyreg(priv, STM32_I2C_CR2_OFFSET, 0, I2C_CR2_ITBUFEN); -#endif - } - - /* More bytes to read */ - - else if ((status & I2C_SR1_RXNE) != 0) - { - /* Read a byte, if dcnt goes < 0, then read dummy bytes to ack ISRs */ - - if (priv->dcnt > 0) - { - stm32_i2c_traceevent(priv, I2CEVENT_RCVBYTE, priv->dcnt); - - /* No interrupts or context switches may occur in the following - * sequence. Otherwise, additional bytes may be sent by the - * device. - */ - -#ifdef CONFIG_I2C_POLLED - irqstate_t flags = enter_critical_section(); -#endif - /* Receive a byte */ - - *priv->ptr++ = stm32_i2c_getreg(priv, STM32_I2C_DR_OFFSET); - - /* Disable acknowledge when last byte is to be received */ - - priv->dcnt--; - if (priv->dcnt == 1) - { - stm32_i2c_modifyreg(priv, STM32_I2C_CR1_OFFSET, - I2C_CR1_ACK, 0); - } - -#ifdef CONFIG_I2C_POLLED - leave_critical_section(flags); -#endif - } - else - { - /* Throw away the unexpected byte */ - - stm32_i2c_getreg(priv, STM32_I2C_DR_OFFSET); - } - } - else if (status & I2C_SR1_TXE) - { - /* This should never happen, but it does happen occasionally with lots - * of noise on the bus. It means the peripheral is expecting more data - * bytes, but we don't have any to give. - */ - - stm32_i2c_putreg(priv, STM32_I2C_DR_OFFSET, 0); - } - else if (status & I2C_SR1_BTF) - { - /* We should have handled all cases where this could happen above, but - * just to ensure it gets ACKed, lets clear it here - */ - - stm32_i2c_getreg(priv, STM32_I2C_DR_OFFSET); - } - else if (status & I2C_SR1_STOPF) - { - /* We should never get this, as we are a master not a slave. Write CR1 - * with its current value to clear the error - */ - - stm32_i2c_modifyreg(priv, STM32_I2C_CR1_OFFSET, 0, 0); - } - - /* Do we have more bytes to send, enable/disable buffer interrupts - * (these ISRs could be replaced by DMAs) - */ - -#ifndef CONFIG_I2C_POLLED - if (priv->dcnt > 0) - { - stm32_i2c_traceevent(priv, I2CEVENT_REITBUFEN, 0); - stm32_i2c_modifyreg(priv, STM32_I2C_CR2_OFFSET, 0, I2C_CR2_ITBUFEN); - } - else if (priv->dcnt == 0) - { - stm32_i2c_traceevent(priv, I2CEVENT_DISITBUFEN, 0); - stm32_i2c_modifyreg(priv, STM32_I2C_CR2_OFFSET, I2C_CR2_ITBUFEN, 0); - } -#endif - - /* Was last byte received or sent? Hmmm... the F2 and F4 seems to differ - * from the F1 in that BTF is not set after data is received (only RXNE). - */ - -#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) || \ - defined(CONFIG_STM32_STM32L15XX) - if (priv->dcnt <= 0 && (status & (I2C_SR1_BTF | I2C_SR1_RXNE)) != 0) -#else - if (priv->dcnt <= 0 && (status & I2C_SR1_BTF) != 0) -#endif - { - stm32_i2c_getreg(priv, STM32_I2C_DR_OFFSET); /* ACK ISR */ - - /* Do we need to terminate or restart after this byte? - * If there are more messages to send, then we may: - * - * - continue with repeated start - * - or just continue sending writeable part - * - or we close down by sending the stop bit - */ - - if (priv->msgc > 0 && priv->msgv != NULL) - { - if (priv->msgv->flags & I2C_M_NOSTART) - { - stm32_i2c_traceevent(priv, I2CEVENT_BTFNOSTART, priv->msgc); - priv->ptr = priv->msgv->buffer; - priv->dcnt = priv->msgv->length; - priv->flags = priv->msgv->flags; - priv->msgv++; - priv->msgc--; - - /* Restart this ISR! */ - -#ifndef CONFIG_I2C_POLLED - stm32_i2c_modifyreg(priv, STM32_I2C_CR2_OFFSET, - 0, I2C_CR2_ITBUFEN); -#endif - } - else - { - stm32_i2c_traceevent(priv, I2CEVENT_BTFRESTART, priv->msgc); - stm32_i2c_sendstart(priv); - } - } - else if (priv->msgv) - { - stm32_i2c_traceevent(priv, I2CEVENT_BTFSTOP, 0); - stm32_i2c_sendstop(priv); - - /* Is there a thread waiting for this event (there should be) */ - -#ifndef CONFIG_I2C_POLLED - if (priv->intstate == INTSTATE_WAITING) - { - /* Yes.. inform the thread that the transfer is complete - * and wake it up. - */ - - nxsem_post(&priv->sem_isr); - priv->intstate = INTSTATE_DONE; - } -#else - priv->intstate = INTSTATE_DONE; -#endif - - /* Mark that we have stopped with this transaction */ - - priv->msgv = NULL; - } - } - - /* Check for errors, in which case, stop the transfer and return - * Note that in master reception mode AF becomes set on last byte - * since ACK is not returned. We should ignore this error. - */ - - if ((status & I2C_SR1_ERRORMASK) != 0) - { - stm32_i2c_traceevent(priv, I2CEVENT_ERROR, 0); - - /* Clear interrupt flags */ - - stm32_i2c_putreg(priv, STM32_I2C_SR1_OFFSET, 0); - - /* Is there a thread waiting for this event (there should be) */ - -#ifndef CONFIG_I2C_POLLED - if (priv->intstate == INTSTATE_WAITING) - { - /* Yes.. inform the thread that the transfer is complete - * and wake it up. - */ - - nxsem_post(&priv->sem_isr); - priv->intstate = INTSTATE_DONE; - } -#else - priv->intstate = INTSTATE_DONE; -#endif - } - - priv->status = status; - return OK; -} - -/**************************************************************************** - * Name: stm32_i2c_isr - * - * Description: - * Common I2C interrupt service routine - * - ****************************************************************************/ - -#ifndef CONFIG_I2C_POLLED -static int stm32_i2c_isr(int irq, void *context, void *arg) -{ - struct stm32_i2c_priv_s *priv = (struct stm32_i2c_priv_s *)arg; - - DEBUGASSERT(priv != NULL); - return stm32_i2c_isr_process(priv); -} -#endif - -/**************************************************************************** - * Name: stm32_i2c_init - * - * Description: - * Setup the I2C hardware, ready for operation with defaults - * - ****************************************************************************/ - -static int stm32_i2c_init(struct stm32_i2c_priv_s *priv) -{ - /* Power-up and configure GPIOs */ - - /* Enable power and reset the peripheral */ - - modifyreg32(STM32_RCC_APB1ENR, 0, priv->config->clk_bit); - modifyreg32(STM32_RCC_APB1RSTR, 0, priv->config->reset_bit); - modifyreg32(STM32_RCC_APB1RSTR, priv->config->reset_bit, 0); - - /* Configure pins */ - - if (stm32_configgpio(priv->config->scl_pin) < 0) - { - return ERROR; - } - - if (stm32_configgpio(priv->config->sda_pin) < 0) - { - stm32_unconfiggpio(priv->config->scl_pin); - return ERROR; - } - - /* Attach ISRs */ - -#ifndef CONFIG_I2C_POLLED - irq_attach(priv->config->ev_irq, stm32_i2c_isr, priv); - irq_attach(priv->config->er_irq, stm32_i2c_isr, priv); - up_enable_irq(priv->config->ev_irq); - up_enable_irq(priv->config->er_irq); -#endif - - /* Set peripheral frequency, where it must be at least 2 MHz for 100 kHz - * or 4 MHz for 400 kHz. This also disables all I2C interrupts. - */ - - stm32_i2c_putreg(priv, STM32_I2C_CR2_OFFSET, - (STM32_PCLK1_FREQUENCY / 1000000)); - - /* Force a frequency update */ - - priv->frequency = 0; - - stm32_i2c_setclock(priv, 100000); - - /* Enable I2C */ - - stm32_i2c_putreg(priv, STM32_I2C_CR1_OFFSET, I2C_CR1_PE); - return OK; -} - -/**************************************************************************** - * Name: stm32_i2c_deinit - * - * Description: - * Shutdown the I2C hardware - * - ****************************************************************************/ - -static int stm32_i2c_deinit(struct stm32_i2c_priv_s *priv) -{ - /* Disable I2C */ - - stm32_i2c_putreg(priv, STM32_I2C_CR1_OFFSET, 0); - - /* Unconfigure GPIO pins */ - - stm32_unconfiggpio(priv->config->scl_pin); - stm32_unconfiggpio(priv->config->sda_pin); - - /* Disable and detach interrupts */ - -#ifndef CONFIG_I2C_POLLED - up_disable_irq(priv->config->ev_irq); - up_disable_irq(priv->config->er_irq); - irq_detach(priv->config->ev_irq); - irq_detach(priv->config->er_irq); -#endif - - /* Disable clocking */ - - modifyreg32(STM32_RCC_APB1ENR, priv->config->clk_bit, 0); - return OK; -} - -/**************************************************************************** - * Device Driver Operations - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_i2c_transfer - * - * Description: - * Generic I2C transfer function - * - ****************************************************************************/ - -static int stm32_i2c_transfer(struct i2c_master_s *dev, - struct i2c_msg_s *msgs, int count) -{ - struct stm32_i2c_priv_s *priv = (struct stm32_i2c_priv_s *)dev; - uint32_t status = 0; -#ifdef I2C1_FSMC_CONFLICT - uint32_t ahbenr; -#endif - int ret; - - DEBUGASSERT(count > 0); - - /* Ensure that address or flags don't change meanwhile */ - - ret = nxmutex_lock(&priv->lock); - if (ret < 0) - { - return ret; - } - -#ifdef I2C1_FSMC_CONFLICT - /* Disable FSMC that shares a pin with I2C1 (LBAR) */ - - ahbenr = stm32_i2c_disablefsmc(priv); - -#else - /* Wait for any STOP in progress. NOTE: If we have to disable the FSMC - * then we cannot do this at the top of the loop, unfortunately. The STOP - * will not complete normally if the FSMC is enabled. - */ - - stm32_i2c_sem_waitstop(priv); -#endif - - /* Clear any pending error interrupts */ - - stm32_i2c_putreg(priv, STM32_I2C_SR1_OFFSET, 0); - - /* "Note: When the STOP, START or PEC bit is set, the software must - * not perform any write access to I2C_CR1 before this bit is - * cleared by hardware. Otherwise there is a risk of setting a - * second STOP, START or PEC request." However, if the bits are - * not cleared by hardware, then we will have to do that from hardware. - */ - - stm32_i2c_clrstart(priv); - - /* Old transfers are done */ - - /* Reset ptr and dcnt to ensure an unexpected data interrupt doesn't - * overwrite stale data. - */ - - priv->dcnt = 0; - priv->ptr = NULL; - - priv->msgv = msgs; - priv->msgc = count; - - /* Reset I2C trace logic */ - - stm32_i2c_tracereset(priv); - - /* Set I2C clock frequency (on change it toggles I2C_CR1_PE !) - * REVISIT: Note that the frequency is set only on the first message. - * This could be extended to support different transfer frequencies for - * each message segment. - */ - - stm32_i2c_setclock(priv, msgs->frequency); - - /* Trigger start condition, then the process moves into the ISR. I2C - * interrupts will be enabled within stm32_i2c_waitdone(). - */ - - priv->status = 0; - stm32_i2c_sendstart(priv); - - /* Wait for an ISR, if there was a timeout, fetch latest status to get - * the BUSY flag. - */ - - if (stm32_i2c_sem_waitdone(priv) < 0) - { - status = stm32_i2c_getstatus(priv); - ret = -ETIMEDOUT; - - i2cerr("ERROR: Timed out: CR1: 0x%04x status: 0x%08" PRIx32 "\n", - stm32_i2c_getreg(priv, STM32_I2C_CR1_OFFSET), status); - - /* "Note: When the STOP, START or PEC bit is set, the software must - * not perform any write access to I2C_CR1 before this bit is - * cleared by hardware. Otherwise there is a risk of setting a - * second STOP, START or PEC request." - */ - - stm32_i2c_clrstart(priv); - - /* Clear busy flag in case of timeout */ - - status = priv->status & 0xffff; - } - else - { - /* clear SR2 (BUSY flag) as we've done successfully */ - - status = priv->status & 0xffff; - } - - /* Check for error status conditions */ - - if ((status & I2C_SR1_ERRORMASK) != 0) - { - /* I2C_SR1_ERRORMASK is the 'OR' of the following individual bits: */ - - if (status & I2C_SR1_BERR) - { - /* Bus Error */ - - ret = -EIO; - } - else if (status & I2C_SR1_ARLO) - { - /* Arbitration Lost (master mode) */ - - ret = -EAGAIN; - } - else if (status & I2C_SR1_AF) - { - /* Acknowledge Failure */ - - ret = -ENXIO; - } - else if (status & I2C_SR1_OVR) - { - /* Overrun/Underrun */ - - ret = -EIO; - } - else if (status & I2C_SR1_PECERR) - { - /* PEC Error in reception */ - - ret = -EPROTO; - } - else if (status & I2C_SR1_TIMEOUT) - { - /* Timeout or Tlow Error */ - - ret = -ETIME; - } - - /* This is not an error and should never happen since SMBus is not - * enabled - */ - - else /* if (status & I2C_SR1_SMBALERT) */ - { - /* SMBus alert is an optional signal with an interrupt line for - * devices that want to trade their ability to master for a pin. - */ - - ret = -EINTR; - } - } - - /* This is not an error, but should not happen. The BUSY signal can hang, - * however, if there are unhealthy devices on the bus that need to be - * reset. - * NOTE: We will only see this busy indication if stm32_i2c_sem_waitdone() - * fails above; Otherwise it is cleared. - */ - - else if ((status & (I2C_SR2_BUSY << 16)) != 0) - { - /* I2C Bus is for some reason busy */ - - ret = -EBUSY; - } - - /* Dump the trace result */ - - stm32_i2c_tracedump(priv); - -#ifdef I2C1_FSMC_CONFLICT - /* Wait for any STOP in progress. NOTE: If we have to disable the FSMC - * then we cannot do this at the top of the loop, unfortunately. The STOP - * will not complete normally if the FSMC is enabled. - */ - - stm32_i2c_sem_waitstop(priv); - - /* Re-enable the FSMC */ - - stm32_i2c_enablefsmc(ahbenr); -#endif - - /* Ensure that any ISR happening after we finish can't overwrite any user - * data - */ - - priv->dcnt = 0; - priv->ptr = NULL; - - nxmutex_unlock(&priv->lock); - return ret; -} - -/**************************************************************************** - * Name: stm32_i2c_reset - * - * Description: - * Perform an I2C bus reset in an attempt to break loose stuck I2C devices. - * - * Input Parameters: - * dev - Device-specific state data - * - * Returned Value: - * Zero (OK) on success; a negated errno value on failure. - * - ****************************************************************************/ - -#ifdef CONFIG_I2C_RESET -static int stm32_i2c_reset(struct i2c_master_s *dev) -{ - struct stm32_i2c_priv_s *priv = (struct stm32_i2c_priv_s *)dev; - unsigned int clock_count; - unsigned int stretch_count; - uint32_t scl_gpio; - uint32_t sda_gpio; - uint32_t frequency; - int ret; - - DEBUGASSERT(dev); - - /* Our caller must own a ref */ - - DEBUGASSERT(priv->refs > 0); - - /* Lock out other clients */ - - ret = nxmutex_lock(&priv->lock); - if (ret < 0) - { - return ret; - } - - ret = -EIO; - - /* Save the current frequency */ - - frequency = priv->frequency; - - /* De-init the port */ - - stm32_i2c_deinit(priv); - - /* Use GPIO configuration to un-wedge the bus */ - - scl_gpio = MKI2C_OUTPUT(priv->config->scl_pin); - sda_gpio = MKI2C_OUTPUT(priv->config->sda_pin); - - stm32_configgpio(scl_gpio); - stm32_configgpio(sda_gpio); - - /* Let SDA go high */ - - stm32_gpiowrite(sda_gpio, 1); - - /* Clock the bus until any slaves currently driving it let it go. */ - - clock_count = 0; - while (!stm32_gpioread(sda_gpio)) - { - /* Give up if we have tried too hard */ - - if (clock_count++ > 10) - { - goto out; - } - - /* Sniff to make sure that clock stretching has finished. - * - * If the bus never relaxes, the reset has failed. - */ - - stretch_count = 0; - while (!stm32_gpioread(scl_gpio)) - { - /* Give up if we have tried too hard */ - - if (stretch_count++ > 10) - { - goto out; - } - - up_udelay(10); - } - - /* Drive SCL low */ - - stm32_gpiowrite(scl_gpio, 0); - up_udelay(10); - - /* Drive SCL high again */ - - stm32_gpiowrite(scl_gpio, 1); - up_udelay(10); - } - - /* Generate a start followed by a stop to reset slave - * state machines. - */ - - stm32_gpiowrite(sda_gpio, 0); - up_udelay(10); - stm32_gpiowrite(scl_gpio, 0); - up_udelay(10); - stm32_gpiowrite(scl_gpio, 1); - up_udelay(10); - stm32_gpiowrite(sda_gpio, 1); - up_udelay(10); - - /* Revert the GPIO configuration. */ - - stm32_unconfiggpio(sda_gpio); - stm32_unconfiggpio(scl_gpio); - - /* Re-init the port */ - - stm32_i2c_init(priv); - - /* Restore the frequency */ - - stm32_i2c_setclock(priv, frequency); - ret = OK; - -out: - - /* Release the port for reuse by other clients */ - - nxmutex_unlock(&priv->lock); - return ret; -} -#endif /* CONFIG_I2C_RESET */ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_i2cbus_initialize - * - * Description: - * Initialize one I2C bus - * - ****************************************************************************/ - -struct i2c_master_s *stm32_i2cbus_initialize(int port) -{ - struct stm32_i2c_priv_s *priv = NULL; - - /* Get I2C private structure */ - - switch (port) - { -#ifdef CONFIG_STM32_I2C1 - case 1: - priv = (struct stm32_i2c_priv_s *)&stm32_i2c1_priv; - break; -#endif -#ifdef CONFIG_STM32_I2C2 - case 2: - priv = (struct stm32_i2c_priv_s *)&stm32_i2c2_priv; - break; -#endif -#ifdef CONFIG_STM32_I2C3 - case 3: - priv = (struct stm32_i2c_priv_s *)&stm32_i2c3_priv; - break; -#endif - default: - return NULL; - } - - /* Initialize private data for the first time, increment reference count, - * power-up hardware and configure GPIOs. - */ - - nxmutex_lock(&priv->lock); - if (priv->refs++ == 0) - { - stm32_i2c_init(priv); - } - - nxmutex_unlock(&priv->lock); - return (struct i2c_master_s *)priv; -} - -/**************************************************************************** - * Name: stm32_i2cbus_uninitialize - * - * Description: - * Uninitialize an I2C bus - * - ****************************************************************************/ - -int stm32_i2cbus_uninitialize(struct i2c_master_s *dev) -{ - struct stm32_i2c_priv_s *priv = (struct stm32_i2c_priv_s *)dev; - - DEBUGASSERT(dev); - - /* Decrement reference count and check for underflow */ - - if (priv->refs == 0) - { - return ERROR; - } - - nxmutex_lock(&priv->lock); - if (--priv->refs) - { - nxmutex_unlock(&priv->lock); - return OK; - } - - /* Disable power and other HW resource (GPIO's) */ - - stm32_i2c_deinit(priv); - nxmutex_unlock(&priv->lock); - - return OK; -} - -#endif /* CONFIG_STM32_STM32F10XX || CONFIG_STM32_STM32F20XX || CONFIG_STM32_STM32F4XXX */ -#endif /* CONFIG_STM32_I2C1 || CONFIG_STM32_I2C2 || CONFIG_STM32_I2C3 */ diff --git a/arch/arm/src/stm32/stm32_i2c.h b/arch/arm/src/stm32/stm32_i2c.h deleted file mode 100644 index 1ad4f2b7f1ae1..0000000000000 --- a/arch/arm/src/stm32/stm32_i2c.h +++ /dev/null @@ -1,125 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_i2c.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32_STM32_I2C_H -#define __ARCH_ARM_SRC_STM32_STM32_I2C_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include - -#include "chip.h" -#include "hardware/stm32_i2c.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* If a dynamic timeout is selected, then a non-negative, non-zero micro- - * seconds per byte value must be provided as well. - */ - -#ifdef CONFIG_STM32_I2C_DYNTIMEO -# if CONFIG_STM32_I2C_DYNTIMEO_USECPERBYTE < 1 -# warning "Ignoring CONFIG_STM32_I2C_DYNTIMEO because of CONFIG_STM32_I2C_DYNTIMEO_USECPERBYTE" -# undef CONFIG_STM32_I2C_DYNTIMEO -# endif -#endif - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_i2cbus_initialize - * - * Description: - * Initialize the selected I2C port. And return a unique instance of struct - * struct i2c_master_s. This function may be called to obtain multiple - * instances of the interface, each of which may be set up with a - * different frequency and slave address. - * - * Input Parameters: - * Port number (for hardware that has multiple I2C interfaces) - * - * Returned Value: - * Valid I2C device structure reference on success; a NULL on failure - * - ****************************************************************************/ - -struct i2c_master_s *stm32_i2cbus_initialize(int port); - -/**************************************************************************** - * Name: stm32_i2cbus_uninitialize - * - * Description: - * De-initialize the selected I2C port, and power down the device. - * - * Input Parameters: - * Device structure as returned by the stm32_i2cbus_initialize() - * - * Returned Value: - * OK on success, ERROR when internal reference count mismatch or dev - * points to invalid hardware device. - * - ****************************************************************************/ - -int stm32_i2cbus_uninitialize(struct i2c_master_s *dev); - -/**************************************************************************** - * Name: stm32_i2cbus_slaveinitialize - * - * Description: - * Initialize the selected I2C port as a slave. Return an unique - * instance of struct i2c_slave_s. - * - * Input Parameters: - * Port number (for hardware that has multiple I2C interfaces) - * - * Returned Value: - * Valid I2C device structure reference on success; a NULL on failure - * - ****************************************************************************/ - -struct i2c_slave_s *stm32_i2cbus_slaveinitialize(int port); - -/**************************************************************************** - * Name: stm32_i2cbus_uninitialize - * - * Description: - * De-initialize the selected I2C port, and power down the device. - * - * Input Parameters: - * Device structure as returned by the stm32_i2cbus_initialize() - * - * Returned Value: - * OK on success, ERROR when internal reference count mismatch or dev - * points to invalid hardware device. - * - ****************************************************************************/ - -int stm32_i2cbus_uninitialize(struct i2c_master_s *dev); - -#endif /* __ARCH_ARM_SRC_STM32_STM32_I2C_H */ diff --git a/arch/arm/src/stm32/stm32_i2c_alt.c b/arch/arm/src/stm32/stm32_i2c_alt.c deleted file mode 100644 index 115a5a8d1033e..0000000000000 --- a/arch/arm/src/stm32/stm32_i2c_alt.c +++ /dev/null @@ -1,2452 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_i2c_alt.c - * - * SPDX-License-Identifier: BSD-3-Clause - * SPDX-FileCopyrightText: 2016-2017 Gregory Nutt. All rights reserved. - * SPDX-FileCopyrightText: 2014 Patrizio Simona. All rights reserved. - * SPDX-FileCopyrightText: 2011-2014 Gregory Nutt. All rights reserved. - * SPDX-FileCopyrightText: 2011 Uros Platise. All rights reserved. - * SPDX-FileContributor: Uros Platise - * SPDX-FileContributor: Gregory Nutt - * SPDX-FileContributor: Patrizio Simona - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -/* Supports: - * - Master operation, 100 kHz (standard) and 400 kHz (full speed) - * - Multiple instances (shared bus) - * - Interrupt based operation - * - * Structure naming: - * - Device: structure as defined by the nuttx/i2c/i2c.h - * - Instance: represents each individual access to the I2C driver, obtained - * by the i2c_init(); it extends the Device structure from the - * nuttx/i2c/i2c.h; - * Instance points to OPS, to common I2C Hardware private data and - * contains its own private data, as frequency, address, mode of - * operation (in the future) - * - Private: Private data of an I2C Hardware - * - * TODO - * - Trace events in polled operation fill trace table very quickly. Events - * 1111 and 1004 get traced in an alternate fashion during polling causing - * multiple entries. - * - Check for all possible deadlocks (as BUSY='1' I2C needs to be reset in - * HW using the I2C_CR1_SWRST) - * - SMBus support (hardware layer timings are already supported) and add - * SMBA gpio pin - * - Slave support with multiple addresses (on multiple instances): - * - 2 x 7-bit address or - * - 1 x 10 bit addresses + 1 x 7 bit address (?) - * - plus the broadcast address (general call) - * - Multi-master support - * - DMA (to get rid of too many CPU wake-ups and interventions) - * - Be ready for IPMI - * - Write trace events to keep track of ISR flow - */ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include - -#include - -#include "arm_internal.h" -#include "stm32_rcc.h" -#include "stm32_i2c.h" -#include "stm32_waste.h" - -/* At least one I2C peripheral must be enabled */ - -#if defined(CONFIG_STM32_I2C1) || defined(CONFIG_STM32_I2C2) || \ - defined(CONFIG_STM32_I2C3) - -/* This implementation is for the STM32 F1, F2, and F4 only. - * Experimentally enabled for STM32L15XX. - */ - -#if defined(CONFIG_STM32_STM32L15XX) || defined(CONFIG_STM32_STM32F10XX) || \ - defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#if STM32_PCLK1_FREQUENCY < 4000000 -# warning STM32_I2C: Peripheral clock must be at least 4 MHz to support 400 kHz operation. -#endif - -#if STM32_PCLK1_FREQUENCY < 2000000 -# error STM32_I2C: Peripheral clock must be at least 2 MHz to support 100 kHz operation. -#endif - -/* Configuration ************************************************************/ - -/* CONFIG_I2C_POLLED may be set so that I2C interrupts will not be used. - * Instead, CPU-intensive polling will be used. - */ - -/* Interrupt wait timeout in seconds and milliseconds */ - -#if !defined(CONFIG_STM32_I2CTIMEOSEC) && !defined(CONFIG_STM32_I2CTIMEOMS) -# define CONFIG_STM32_I2CTIMEOSEC 0 -# define CONFIG_STM32_I2CTIMEOMS 500 /* Default is 500 milliseconds */ -#elif !defined(CONFIG_STM32_I2CTIMEOSEC) -# define CONFIG_STM32_I2CTIMEOSEC 0 /* User provided milliseconds */ -#elif !defined(CONFIG_STM32_I2CTIMEOMS) -# define CONFIG_STM32_I2CTIMEOMS 0 /* User provided seconds */ -#endif - -/* Interrupt wait time timeout in system timer ticks */ - -#ifndef CONFIG_STM32_I2CTIMEOTICKS -# define CONFIG_STM32_I2CTIMEOTICKS \ - (SEC2TICK(CONFIG_STM32_I2CTIMEOSEC) + MSEC2TICK(CONFIG_STM32_I2CTIMEOMS)) -#endif - -#ifndef CONFIG_STM32_I2C_DYNTIMEO_STARTSTOP -# define CONFIG_STM32_I2C_DYNTIMEO_STARTSTOP TICK2USEC(CONFIG_STM32_I2CTIMEOTICKS) -#endif - -/* On the STM32F103ZE, there is an internal conflict between I2C1 and FSMC. - * In that case, it is necessary to disable FSMC before each I2C1 access and - * re-enable FSMC when the I2C access completes. - */ - -#undef I2C1_FSMC_CONFLICT -#if defined(CONFIG_STM32_STM32F10XX) && defined(CONFIG_STM32_FSMC) && defined(CONFIG_STM32_I2C1) -# define I2C1_FSMC_CONFLICT -#endif - -/* Macros to convert a I2C pin to a GPIO output */ - -#if defined(CONFIG_STM32_STM32L15XX) -# define I2C_OUTPUT (GPIO_OUTPUT | GPIO_OUTPUT_SET | GPIO_OPENDRAIN | \ - GPIO_SPEED_40MHz) -#elif defined(CONFIG_STM32_STM32F10XX) -# define I2C_OUTPUT (GPIO_OUTPUT | GPIO_OUTPUT_SET | GPIO_CNF_OUTOD | \ - GPIO_MODE_50MHz) -#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) -# define I2C_OUTPUT (GPIO_OUTPUT | GPIO_FLOAT | GPIO_OPENDRAIN |\ - GPIO_SPEED_50MHz | GPIO_OUTPUT_SET) -#endif - -#define MKI2C_OUTPUT(p) (((p) & (GPIO_PORT_MASK | GPIO_PIN_MASK)) | I2C_OUTPUT) - -/* Debug ********************************************************************/ - -/* I2C event trace logic. NOTE: trace uses the internal, non-standard, - * low-level debug interface syslog() but does not require that any other - * debug is enabled. - */ - -#ifndef CONFIG_I2C_TRACE -# define stm32_i2c_tracereset(p) -# define stm32_i2c_tracenew(p,s) -# define stm32_i2c_traceevent(p,e,a) -# define stm32_i2c_tracedump(p) -#endif - -#ifndef CONFIG_I2C_NTRACE -# define CONFIG_I2C_NTRACE 32 -#endif - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/* Interrupt state */ - -enum stm32_intstate_e -{ - INTSTATE_IDLE = 0, /* No I2C activity */ - INTSTATE_WAITING, /* Waiting for completion of interrupt activity */ - INTSTATE_DONE, /* Interrupt activity complete */ -}; - -/* Trace events */ - -#ifdef CONFIG_I2C_TRACE -static const uint16_t I2CEVENT_NONE = 0; /* No events have occurred with this status */ -static const uint16_t I2CEVENT_STATE_ERROR = 1000; /* No correct state detected, diver cannot handle state */ -static const uint16_t I2CEVENT_ISR_SHUTDOWN = 1001; /* ISR gets shutdown */ -static const uint16_t I2CEVENT_ISR_EMPTY_CALL = 1002; /* ISR gets called but no I2C logic comes into play */ -static const uint16_t I2CEVENT_MSG_HANDLING = 1003; /* Message Handling 1/1: advances the msg processing param = msgc */ -static const uint16_t I2CEVENT_POLL_DEV_NOT_RDY = 1004; /* During polled operation if device is not ready yet */ -static const uint16_t I2CEVENT_ISR_SR1ERROR = 1005; /* ERROR set in SR1 at end of transfer */ -static const uint16_t I2CEVENT_ISR_CALL = 1111; /* ISR called */ - -static const uint16_t I2CEVENT_SENDADDR = 5; /* Start/Master bit set and address sent, param = priv->msgv->addr(EV5 in reference manual) */ -static const uint16_t I2CEVENT_ADDR_HDL_READ_1 = 51; /* Read of length 1 address handling, param = 0 */ -static const uint16_t I2CEVENT_ADDR_HDL_READ_2 = 52; /* Read of length 2 address handling, param = 0 */ -static const uint16_t I2CEVENT_EMPTY_MSG = 5000; /* Empty message detected, param=0 */ - -static const uint16_t I2CEVENT_ADDRESS_ACKED = 6; /* Address has been ACKed(i.e. it's a valid address) param = address */ -static const uint16_t I2CEVENT_ADDRESS_ACKED_READ_1 = 63; /* Event when reading single byte just after address is being ACKed, param = 0 */ -static const uint16_t I2CEVENT_ADDRESS_ACKED_READ_2 = 61; /* Event when reading two bytes just after address is being ACKed, param = 0 */ -static const uint16_t I2CEVENT_ADDRESS_ACKED_WRITE = 681; /* Address has been ACKed(i.e. it's a valid address) in write mode and byte has been written */ -static const uint16_t I2CEVENT_ADDRESS_NACKED = 6000; /* Address has been NACKed(i.e. it's an invalid address) param = address */ - -static const uint16_t I2CEVENT_READ = 7; /* RxNE = 1 therefore can be read, param = dcnt */ -static const uint16_t I2CEVENT_READ_3 = 72; /* EV7_2 reference manual, reading byte N-2 and N-1 when N >=3 */ -static const uint16_t I2CEVENT_READ_2 = 73; /* EV7_3 reference manual, reading byte 1 and 2 when N == 2 */ -static const uint16_t I2CEVENT_READ_SR_EMPTY = 79; /* DR is full but SR is empty, does not read DR and waits for SR to fill in next ISR */ -static const uint16_t I2CEVENT_READ_LAST_BYTE = 72; /* EV7_2 reference manual last two bytes are in SR and DR */ -static const uint16_t I2CEVENT_READ_ERROR = 7000; /* read mode error */ - -static const uint16_t I2CEVENT_WRITE_TO_DR = 8; /* EV8 reference manual, writing into the data register param = byte to send */ -static const uint16_t I2CEVENT_WRITE_STOP = 82; /* EV8_2 reference manual, set stop bit after write is finished */ -static const uint16_t I2CEVENT_WRITE_RESTART = 83; /* Re-send start bit as next packet is a read */ -static const uint16_t I2CEVENT_WRITE_NO_RESTART = 84; /* don't restart as packet flag says so */ -static const uint16_t I2CEVENT_WRITE_ERROR = 8000; /* Error in write mode, param = 0 */ -static const uint16_t I2CEVENT_WRITE_FLAG_ERROR = 8001; /* Next message has unrecognized flag, param = priv->msgv->flags */ -#endif /* CONFIG_I2C_TRACE */ - -/* Trace data */ - -struct stm32_trace_s -{ - uint32_t status; /* I2C 32-bit SR2|SR1 status */ - uint32_t count; /* Interrupt count when status change */ - uint32_t event; /* Last event that occurred with this status */ - uint32_t parm; /* Parameter associated with the event */ - clock_t time; /* First of event or first status */ -}; - -/* I2C Device hardware configuration */ - -struct stm32_i2c_config_s -{ - uint32_t base; /* I2C base address */ - uint32_t clk_bit; /* Clock enable bit */ - uint32_t reset_bit; /* Reset bit */ - uint32_t scl_pin; /* GPIO configuration for SCL as SCL */ - uint32_t sda_pin; /* GPIO configuration for SDA as SDA */ -#ifndef CONFIG_I2C_POLLED - uint32_t ev_irq; /* Event IRQ */ - uint32_t er_irq; /* Error IRQ */ -#endif -}; - -/* I2C Device Private Data */ - -struct stm32_i2c_priv_s -{ - /* Standard I2C operations */ - - const struct i2c_ops_s *ops; - - /* Port configuration */ - - const struct stm32_i2c_config_s *config; - - int refs; /* Reference count */ - mutex_t lock; /* Mutual exclusion mutex */ -#ifndef CONFIG_I2C_POLLED - sem_t sem_isr; /* Interrupt wait semaphore */ -#endif - volatile uint8_t intstate; /* Interrupt handshake (see enum stm32_intstate_e) */ - - uint8_t msgc; /* Message count */ - struct i2c_msg_s *msgv; /* Message list */ - uint8_t *ptr; /* Current message buffer */ - uint32_t frequency; /* Current I2C frequency */ - int dcnt; /* Current message length */ - uint16_t flags; /* Current message flags */ - bool check_addr_ack; /* Flag to signal if on next interrupt address has ACKed */ - uint8_t total_msg_len; /* Flag to signal a short read sequence */ - - /* I2C trace support */ - -#ifdef CONFIG_I2C_TRACE - int tndx; /* Trace array index */ - clock_t start_time; /* Time when the trace was started */ - - /* The actual trace data */ - - struct stm32_trace_s trace[CONFIG_I2C_NTRACE]; -#endif - - uint32_t status; /* End of transfer SR2|SR1 status */ -}; - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -static inline uint16_t stm32_i2c_getreg(struct stm32_i2c_priv_s *priv, - uint8_t offset); -static inline void stm32_i2c_putreg(struct stm32_i2c_priv_s *priv, - uint8_t offset, uint16_t value); -static inline void stm32_i2c_modifyreg(struct stm32_i2c_priv_s *priv, - uint8_t offset, uint16_t clearbits, - uint16_t setbits); - -#ifdef CONFIG_STM32_I2C_DYNTIMEO -static uint32_t stm32_i2c_toticks(int msgc, struct i2c_msg_s *msgs); -#endif /* CONFIG_STM32_I2C_DYNTIMEO */ - -static inline int stm32_i2c_sem_waitdone(struct stm32_i2c_priv_s *priv); -static inline void stm32_i2c_sem_waitstop(struct stm32_i2c_priv_s *priv); - -#ifdef CONFIG_I2C_TRACE -static void stm32_i2c_tracereset(struct stm32_i2c_priv_s *priv); -static void stm32_i2c_tracenew(struct stm32_i2c_priv_s *priv, - uint16_t status); -static void stm32_i2c_traceevent(struct stm32_i2c_priv_s *priv, - uint16_t event, uint32_t parm); -static void stm32_i2c_tracedump(struct stm32_i2c_priv_s *priv); -#endif /* CONFIG_I2C_TRACE */ - -static void stm32_i2c_setclock(struct stm32_i2c_priv_s *priv, - uint32_t frequency); -static inline void stm32_i2c_sendstart(struct stm32_i2c_priv_s *priv); -static inline void stm32_i2c_clrstart(struct stm32_i2c_priv_s *priv); -static inline void stm32_i2c_sendstop(struct stm32_i2c_priv_s *priv); -static inline -uint32_t stm32_i2c_getstatus(struct stm32_i2c_priv_s *priv); - -#ifdef I2C1_FSMC_CONFLICT -static inline -uint32_t stm32_i2c_disablefsmc(struct stm32_i2c_priv_s *priv); -static inline void stm32_i2c_enablefsmc(uint32_t ahbenr); -#endif /* I2C1_FSMC_CONFLICT */ - -static int stm32_i2c_isr_process(struct stm32_i2c_priv_s *priv); - -#ifndef CONFIG_I2C_POLLED -static int stm32_i2c_isr(int irq, void *context, void *arg); -#endif /* !CONFIG_I2C_POLLED */ - -static int stm32_i2c_init(struct stm32_i2c_priv_s *priv); -static int stm32_i2c_deinit(struct stm32_i2c_priv_s *priv); -static int stm32_i2c_transfer(struct i2c_master_s *dev, - struct i2c_msg_s *msgs, int count); -#ifdef CONFIG_I2C_RESET -static int stm32_i2c_reset(struct i2c_master_s *dev); -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* I2C interface */ - -static const struct i2c_ops_s stm32_i2c_ops = -{ - .transfer = stm32_i2c_transfer -#ifdef CONFIG_I2C_RESET - , .reset = stm32_i2c_reset -#endif -}; - -#ifdef CONFIG_STM32_I2C1 -static const struct stm32_i2c_config_s stm32_i2c1_config = -{ - .base = STM32_I2C1_BASE, - .clk_bit = RCC_APB1ENR_I2C1EN, - .reset_bit = RCC_APB1RSTR_I2C1RST, - .scl_pin = GPIO_I2C1_SCL, - .sda_pin = GPIO_I2C1_SDA, -#ifndef CONFIG_I2C_POLLED - .ev_irq = STM32_IRQ_I2C1EV, - .er_irq = STM32_IRQ_I2C1ER -#endif -}; - -static struct stm32_i2c_priv_s stm32_i2c1_priv = -{ - .ops = &stm32_i2c_ops, - .config = &stm32_i2c1_config, - .refs = 0, - .lock = NXMUTEX_INITIALIZER, -#ifndef CONFIG_I2C_POLLED - .sem_isr = SEM_INITIALIZER(0), -#endif - .intstate = INTSTATE_IDLE, - .msgc = 0, - .msgv = NULL, - .ptr = NULL, - .dcnt = 0, - .flags = 0, - .status = 0 -}; -#endif - -#ifdef CONFIG_STM32_I2C2 -static const struct stm32_i2c_config_s stm32_i2c2_config = -{ - .base = STM32_I2C2_BASE, - .clk_bit = RCC_APB1ENR_I2C2EN, - .reset_bit = RCC_APB1RSTR_I2C2RST, - .scl_pin = GPIO_I2C2_SCL, - .sda_pin = GPIO_I2C2_SDA, -#ifndef CONFIG_I2C_POLLED - .ev_irq = STM32_IRQ_I2C2EV, - .er_irq = STM32_IRQ_I2C2ER -#endif -}; - -static struct stm32_i2c_priv_s stm32_i2c2_priv = -{ - .ops = &stm32_i2c_ops, - .config = &stm32_i2c2_config, - .refs = 0, - .lock = NXMUTEX_INITIALIZER, -#ifndef CONFIG_I2C_POLLED - .sem_isr = SEM_INITIALIZER(0), -#endif - .intstate = INTSTATE_IDLE, - .msgc = 0, - .msgv = NULL, - .ptr = NULL, - .dcnt = 0, - .flags = 0, - .status = 0 -}; -#endif - -#ifdef CONFIG_STM32_I2C3 -static const struct stm32_i2c_config_s stm32_i2c3_config = -{ - .base = STM32_I2C3_BASE, - .clk_bit = RCC_APB1ENR_I2C3EN, - .reset_bit = RCC_APB1RSTR_I2C3RST, - .scl_pin = GPIO_I2C3_SCL, - .sda_pin = GPIO_I2C3_SDA, -#ifndef CONFIG_I2C_POLLED - .ev_irq = STM32_IRQ_I2C3EV, - .er_irq = STM32_IRQ_I2C3ER -#endif -}; - -static struct stm32_i2c_priv_s stm32_i2c3_priv = -{ - .ops = &stm32_i2c_ops, - .config = &stm32_i2c3_config, - .refs = 0, - .lock = NXMUTEX_INITIALIZER, -#ifndef CONFIG_I2C_POLLED - .sem_isr = SEM_INITIALIZER(0), -#endif - .intstate = INTSTATE_IDLE, - .msgc = 0, - .msgv = NULL, - .ptr = NULL, - .dcnt = 0, - .flags = 0, - .status = 0 -}; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_i2c_getreg - * - * Description: - * Get a 16-bit register value by offset - * - ****************************************************************************/ - -static inline uint16_t stm32_i2c_getreg(struct stm32_i2c_priv_s *priv, - uint8_t offset) -{ - return getreg16(priv->config->base + offset); -} - -/**************************************************************************** - * Name: stm32_i2c_putreg - * - * Description: - * Put a 16-bit register value by offset - * - ****************************************************************************/ - -static inline void stm32_i2c_putreg(struct stm32_i2c_priv_s *priv, - uint8_t offset, uint16_t value) -{ - putreg16(value, priv->config->base + offset); -} - -/**************************************************************************** - * Name: stm32_i2c_modifyreg - * - * Description: - * Modify a 16-bit register value by offset - * - ****************************************************************************/ - -static inline void stm32_i2c_modifyreg(struct stm32_i2c_priv_s *priv, - uint8_t offset, uint16_t clearbits, - uint16_t setbits) -{ - modifyreg16(priv->config->base + offset, clearbits, setbits); -} - -/**************************************************************************** - * Name: stm32_i2c_toticks - * - * Description: - * Return a micro-second delay based on the number of bytes left to be - * processed. - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_I2C_DYNTIMEO -static uint32_t stm32_i2c_toticks(int msgc, struct i2c_msg_s *msgs) -{ - size_t bytecount = 0; - int i; - - /* Count the number of bytes left to process */ - - for (i = 0; i < msgc; i++) - { - bytecount += msgs[i].length; - } - - /* Then return a number of microseconds based on a user provided scaling - * factor. - */ - - return USEC2TICK(CONFIG_STM32_I2C_DYNTIMEO_USECPERBYTE * bytecount); -} -#endif - -/**************************************************************************** - * Name: stm32_i2c_sem_waitdone - * - * Description: - * Wait for a transfer to complete - * - ****************************************************************************/ - -#ifndef CONFIG_I2C_POLLED -static int stm32_i2c_sem_waitdone(struct stm32_i2c_priv_s *priv) -{ - irqstate_t flags; - uint32_t regval; - int ret; - - flags = enter_critical_section(); - - /* Enable I2C interrupts */ - - regval = stm32_i2c_getreg(priv, STM32_I2C_CR2_OFFSET); - regval |= (I2C_CR2_ITERREN | I2C_CR2_ITEVFEN); - stm32_i2c_putreg(priv, STM32_I2C_CR2_OFFSET, regval); - - /* Signal the interrupt handler that we are waiting. NOTE: Interrupts - * are currently disabled but will be temporarily re-enabled below when - * nxsem_tickwait_uninterruptible() sleeps. - */ - - priv->intstate = INTSTATE_WAITING; - do - { - /* Wait until either the transfer is complete or the timeout expires */ - -#ifdef CONFIG_STM32_I2C_DYNTIMEO - ret = nxsem_tickwait_uninterruptible(&priv->sem_isr, - stm32_i2c_toticks(priv->msgc, priv->msgv)); -#else - ret = nxsem_tickwait_uninterruptible(&priv->sem_isr, - CONFIG_STM32_I2CTIMEOTICKS); -#endif - if (ret < 0) - { - /* Break out of the loop on irrecoverable errors. This would - * include timeouts and mystery errors reported by - * nxsem_tickwait_uninterruptible. - */ - - break; - } - } - - /* Loop until the interrupt level transfer is complete. */ - - while (priv->intstate != INTSTATE_DONE); - - /* Set the interrupt state back to IDLE */ - - priv->intstate = INTSTATE_IDLE; - - /* Disable I2C interrupts */ - - regval = stm32_i2c_getreg(priv, STM32_I2C_CR2_OFFSET); - regval &= ~I2C_CR2_ALLINTS; - stm32_i2c_putreg(priv, STM32_I2C_CR2_OFFSET, regval); - - leave_critical_section(flags); - return ret; -} -#else -static int stm32_i2c_sem_waitdone(struct stm32_i2c_priv_s *priv) -{ - clock_t timeout; - clock_t start; - clock_t elapsed; - int ret; - - /* Get the timeout value */ - -#ifdef CONFIG_STM32_I2C_DYNTIMEO - timeout = stm32_i2c_toticks(priv->msgc, priv->msgv); -#else - timeout = CONFIG_STM32_I2CTIMEOTICKS; -#endif - - /* Signal the interrupt handler that we are waiting. NOTE: Interrupts - * are currently disabled but will be temporarily re-enabled below when - * nxsem_tickwait_uninterruptible() sleeps. - */ - - priv->intstate = INTSTATE_WAITING; - start = clock_systime_ticks(); - - do - { - /* Calculate the elapsed time */ - - elapsed = clock_systime_ticks() - start; - - /* Poll by simply calling the timer interrupt handler until it - * reports that it is done. - */ - - stm32_i2c_isr_process(priv); - } - - /* Loop until the transfer is complete. */ - - while (priv->intstate != INTSTATE_DONE && elapsed < timeout); - - i2cinfo("intstate: %d elapsed: %ld threshold: %ld status: %08" PRIx32 "\n", - priv->intstate, (long)elapsed, (long)timeout, priv->status); - - /* Set the interrupt state back to IDLE */ - - ret = priv->intstate == INTSTATE_DONE ? OK : -ETIMEDOUT; - priv->intstate = INTSTATE_IDLE; - return ret; -} -#endif - -/**************************************************************************** - * Name: stm32_i2c_sem_waitstop - * - * Description: - * Wait for a STOP to complete - * - ****************************************************************************/ - -static inline void stm32_i2c_sem_waitstop(struct stm32_i2c_priv_s *priv) -{ - clock_t start; - clock_t elapsed; - clock_t timeout; - uint32_t cr1; - uint32_t sr1; - - /* Select a timeout */ - -#ifdef CONFIG_STM32_I2C_DYNTIMEO - timeout = USEC2TICK(CONFIG_STM32_I2C_DYNTIMEO_STARTSTOP); -#else - timeout = CONFIG_STM32_I2CTIMEOTICKS; -#endif - - /* Wait as stop might still be in progress; but stop might also - * be set because of a timeout error: "The [STOP] bit is set and - * cleared by software, cleared by hardware when a Stop condition is - * detected, set by hardware when a timeout error is detected." - */ - - start = clock_systime_ticks(); - do - { - /* Calculate the elapsed time */ - - elapsed = clock_systime_ticks() - start; - - /* Check for STOP condition */ - - cr1 = stm32_i2c_getreg(priv, STM32_I2C_CR1_OFFSET); - if ((cr1 & I2C_CR1_STOP) == 0) - { - return; - } - - /* Check for timeout error */ - - sr1 = stm32_i2c_getreg(priv, STM32_I2C_SR1_OFFSET); - if ((sr1 & I2C_SR1_TIMEOUT) != 0) - { - return; - } - } - - /* Loop until the stop is complete or a timeout occurs. */ - - while (elapsed < timeout); - - /* If we get here then a timeout occurred with the STOP condition - * still pending. - */ - - i2cinfo("Timeout with CR1: %04" PRIx32 " SR1: %04" PRIx32 "\n", cr1, sr1); -} - -/**************************************************************************** - * Name: stm32_i2c_trace* - * - * Description: - * I2C trace instrumentation - * - ****************************************************************************/ - -#ifdef CONFIG_I2C_TRACE -static void stm32_i2c_traceclear(struct stm32_i2c_priv_s *priv) -{ - struct stm32_trace_s *trace = &priv->trace[priv->tndx]; - - trace->status = 0; /* I2C 32-bit SR2|SR1 status */ - trace->count = 0; /* Interrupt count when status change */ - trace->event = I2CEVENT_NONE; /* Last event that occurred with this status */ - trace->parm = 0; /* Parameter associated with the event */ - trace->time = 0; /* Time of first status or event */ -} - -static void stm32_i2c_tracereset(struct stm32_i2c_priv_s *priv) -{ - /* Reset the trace info for a new data collection */ - - priv->tndx = 0; - priv->start_time = clock_systime_ticks(); - stm32_i2c_traceclear(priv); -} - -static void stm32_i2c_tracenew(struct stm32_i2c_priv_s *priv, - uint16_t status) -{ - struct stm32_trace_s *trace = &priv->trace[priv->tndx]; - - /* Is the current entry uninitialized? Has the status changed? */ - - if (trace->count == 0 || status != trace->status) - { - /* Yes.. Was it the status changed? */ - - if (trace->count != 0) - { - /* Yes.. bump up the trace index - * (unless we are out of trace entries) - */ - - if (priv->tndx >= (CONFIG_I2C_NTRACE - 1)) - { - i2cerr("ERROR: Trace table overflow\n"); - return; - } - - priv->tndx++; - trace = &priv->trace[priv->tndx]; - } - - /* Initialize the new trace entry */ - - stm32_i2c_traceclear(priv); - trace->status = status; - trace->count = 1; - trace->time = clock_systime_ticks(); - } - else - { - /* Just increment the count of times that we have seen this status */ - - trace->count++; - } -} - -static void stm32_i2c_traceevent(struct stm32_i2c_priv_s *priv, - uint16_t event, uint32_t parm) -{ - struct stm32_trace_s *trace; - - if (event != I2CEVENT_NONE || event != I2CEVENT_POLL_DEV_NOT_RDY) - { - trace = &priv->trace[priv->tndx]; - - /* Initialize the new trace entry */ - - trace->event = event; - trace->parm = parm; - - /* Bump up the trace index (unless we are out of trace entries) */ - - if (priv->tndx >= (CONFIG_I2C_NTRACE - 1)) - { - i2cerr("ERROR: Trace table overflow\n"); - return; - } - - priv->tndx++; - stm32_i2c_traceclear(priv); - } -} - -static void stm32_i2c_tracedump(struct stm32_i2c_priv_s *priv) -{ - struct stm32_trace_s *trace; - int i; - - syslog(LOG_DEBUG, "Elapsed time: %ld\n", - (long)(clock_systime_ticks() - priv->start_time)); - - for (i = 0; i < priv->tndx; i++) - { - trace = &priv->trace[i]; - syslog(LOG_DEBUG, - "%2d. STATUS: %08" PRIx32 " COUNT: %4d EVENT: %4d PARM:" - " %08" PRIx32 " TIME: %d\n", - i + 1, trace->status, trace->count, trace->event, trace->parm, - trace->time - priv->start_time); - } -} -#endif /* CONFIG_I2C_TRACE */ - -/**************************************************************************** - * Name: stm32_i2c_setclock - * - * Description: - * Set the I2C clock - * - ****************************************************************************/ - -static void stm32_i2c_setclock(struct stm32_i2c_priv_s *priv, - uint32_t frequency) -{ - uint16_t cr1; - uint16_t ccr; - uint16_t trise; - uint16_t freqmhz; - uint16_t speed; - - /* Has the I2C bus frequency changed? */ - - if (frequency != priv->frequency) - { - /* Disable the selected I2C peripheral to configure TRISE */ - - cr1 = stm32_i2c_getreg(priv, STM32_I2C_CR1_OFFSET); - stm32_i2c_putreg(priv, STM32_I2C_CR1_OFFSET, cr1 & ~I2C_CR1_PE); - - /* Update timing and control registers */ - - freqmhz = (uint16_t)(STM32_PCLK1_FREQUENCY / 1000000); - ccr = 0; - - /* Configure speed in standard mode */ - - if (frequency <= 100000) - { - /* Standard mode speed calculation */ - - speed = (uint16_t)(STM32_PCLK1_FREQUENCY / (frequency << 1)); - - /* The CCR fault must be >= 4 */ - - if (speed < 4) - { - /* Set the minimum allowed value */ - - speed = 4; - } - - ccr |= speed; - - /* Set Maximum Rise Time for standard mode */ - - trise = freqmhz + 1; - } - - /* Configure speed in fast mode */ - - else /* (frequency <= 400000) */ - { - /* Fast mode speed calculation with Tlow/Thigh = 16/9 */ - -#ifdef CONFIG_STM32_I2C_DUTY16_9 - speed = (uint16_t)(STM32_PCLK1_FREQUENCY / (frequency * 25)); - - /* Set DUTY and fast speed bits */ - - ccr |= (I2C_CCR_DUTY | I2C_CCR_FS); -#else - /* Fast mode speed calculation with Tlow/Thigh = 2 */ - - speed = (uint16_t)(STM32_PCLK1_FREQUENCY / (frequency * 3)); - - /* Set fast speed bit */ - - ccr |= I2C_CCR_FS; -#endif - - /* Verify that the CCR speed value is nonzero */ - - if (speed < 1) - { - /* Set the minimum allowed value */ - - speed = 1; - } - - ccr |= speed; - - /* Set Maximum Rise Time for fast mode */ - - trise = (uint16_t)(((freqmhz * 300) / 1000) + 1); - } - - /* Write the new values of the CCR and TRISE registers */ - - stm32_i2c_putreg(priv, STM32_I2C_CCR_OFFSET, ccr); - stm32_i2c_putreg(priv, STM32_I2C_TRISE_OFFSET, trise); - - /* Bit 14 of OAR1 must be configured and kept at 1 */ - - stm32_i2c_putreg(priv, STM32_I2C_OAR1_OFFSET, I2C_OAR1_ONE); - - /* Re-enable the peripheral (or not) */ - - stm32_i2c_putreg(priv, STM32_I2C_CR1_OFFSET, cr1); - - /* Save the new I2C frequency */ - - priv->frequency = frequency; - } -} - -/**************************************************************************** - * Name: stm32_i2c_sendstart - * - * Description: - * Send the START conditions/force Master mode - * - ****************************************************************************/ - -static inline void stm32_i2c_sendstart(struct stm32_i2c_priv_s *priv) -{ - /* Disable ACK on receive by default and generate START */ - - stm32_i2c_modifyreg(priv, STM32_I2C_CR1_OFFSET, - I2C_CR1_ACK, I2C_CR1_START); -} - -/**************************************************************************** - * Name: stm32_i2c_clrstart - * - * Description: - * Clear the STOP, START or PEC condition on certain error recovery steps. - * - ****************************************************************************/ - -static inline void stm32_i2c_clrstart(struct stm32_i2c_priv_s *priv) -{ - /* "Note: When the STOP, START or PEC bit is set, the software must - * not perform any write access to I2C_CR1 before this bit is - * cleared by hardware. Otherwise there is a risk of setting a - * second STOP, START or PEC request." - * - * "The [STOP] bit is set and cleared by software, cleared by hardware - * when a Stop condition is detected, set by hardware when a timeout - * error is detected. - * - * "This [START] bit is set and cleared by software and cleared by hardware - * when start is sent or PE=0." The bit must be cleared by software if - * the START is never sent. - * - * "This [PEC] bit is set and cleared by software, and cleared by hardware - * when PEC is transferred or by a START or Stop condition or when PE=0." - */ - - stm32_i2c_modifyreg(priv, STM32_I2C_CR1_OFFSET, - I2C_CR1_START | I2C_CR1_STOP | I2C_CR1_PEC, 0); -} - -/**************************************************************************** - * Name: stm32_i2c_sendstop - * - * Description: - * Send the STOP conditions - * - ****************************************************************************/ - -static inline void stm32_i2c_sendstop(struct stm32_i2c_priv_s *priv) -{ - stm32_i2c_modifyreg(priv, STM32_I2C_CR1_OFFSET, I2C_CR1_ACK, I2C_CR1_STOP); -} - -/**************************************************************************** - * Name: stm32_i2c_getstatus - * - * Description: - * Get 32-bit status (SR1 and SR2 combined) - * - ****************************************************************************/ - -static inline uint32_t stm32_i2c_getstatus(struct stm32_i2c_priv_s *priv) -{ - uint32_t status = stm32_i2c_getreg(priv, STM32_I2C_SR1_OFFSET); - status |= (stm32_i2c_getreg(priv, STM32_I2C_SR2_OFFSET) << 16); - return status; -} - -/**************************************************************************** - * Name: stm32_i2c_disablefsmc - * - * Description: - * FSMC must be disable while accessing I2C1 because it uses a common - * resource (LBAR) - * - * NOTE: This is an issue with the STM32F103ZE, but may not be an issue with - * other STM32s. You may need to experiment - * - ****************************************************************************/ - -#ifdef I2C1_FSMC_CONFLICT -static inline -uint32_t stm32_i2c_disablefsmc(struct stm32_i2c_priv_s *priv) -{ - uint32_t ret = 0; - uint32_t regval; - - /* Is this I2C1 */ - -#if defined(CONFIG_STM32_I2C2) || defined(CONFIG_STM32_I2C3) - if (priv->config->base == STM32_I2C1_BASE) -#endif - { - /* Disable FSMC unconditionally */ - - ret = getreg32(STM32_RCC_AHBENR); - regval = ret & ~RCC_AHBENR_FSMCEN; - putreg32(regval, STM32_RCC_AHBENR); - } - - return ret; -} - -/**************************************************************************** - * Name: stm32_i2c_enablefsmc - * - * Description: - * Re-enable the FSMC - * - ****************************************************************************/ - -static inline void stm32_i2c_enablefsmc(uint32_t ahbenr) -{ - uint32_t regval; - - /* Enable AHB clocking to the FSMC only if it was previously enabled. */ - - if ((ahbenr & RCC_AHBENR_FSMCEN) != 0) - { - regval = getreg32(STM32_RCC_AHBENR); - regval |= RCC_AHBENR_FSMCEN; - putreg32(regval, STM32_RCC_AHBENR); - } -} -#else -# define stm32_i2c_disablefsmc(priv) (0) -# define stm32_i2c_enablefsmc(ahbenr) -#endif /* I2C1_FSMC_CONFLICT */ - -/**************************************************************************** - * Name: stm32_i2c_isr_process - * - * Description: - * Common interrupt service routine (ISR) that handles I2C protocol logic. - * - * This ISR is activated and deactivated by stm32_i2c_waitdone(). - * Interrupt fires on(both ITEVFEN and ITBUFEN are set): - * - * - Start bit - * - Address sent - * - 10-bit header sent - * - Data byte transfer finished - * - Receive buffer not empty - * - Transmit buffer empty - * - * Input Parameters: - * priv - The private struct of the I2C driver. - * - * Returned Value: - * - ****************************************************************************/ - -static int stm32_i2c_isr_process(struct stm32_i2c_priv_s *priv) -{ -#ifndef CONFIG_I2C_POLLED - uint32_t regval; -#endif - uint32_t status; - - i2cinfo("I2C ISR called\n"); - - /* Get state of the I2C controller (register SR1 only) - * - * Get control register SR1 only as reading both SR1 and SR2 clears the - * ADDR flag(possibly others) causing the hardware to advance to the - * next state without the proper action being taken. - */ - - status = stm32_i2c_getreg(priv, STM32_I2C_SR1_OFFSET); - - /* Update private version of the state */ - - priv->status = status; - - /* Check if this is a new transmission so to set up the - * trace table accordingly. - */ - - stm32_i2c_tracenew(priv, status); - stm32_i2c_traceevent(priv, I2CEVENT_ISR_CALL, 0); - - /* Messages handling (1/2) - * - * Message handling should only operate when a message has been completely - * sent and after the ISR had the chance to run to set bits after the last - * written/read byte, i.e. priv->dcnt == -1. This is also the case in when - * the ISR is called for the first time. This can seen in - * stm32_i2c_transfer() before entering the stm32_i2c_sem_waitdone() - * waiting process. - * - * Message handling should only operate when: - * - A message has been completely sent and there are still messages - * to send(i.e. msgc > 0). - * - After the ISR had the chance to run to set start bit or - * termination flags after the last written/read byte(after last byte - * dcnt=0, msg handling dcnt = -1). - * - * When the ISR is called for the first time the same conditions hold. - * This can seen in stm32_i2c_transfer() before entering the - * stm32_i2c_sem_waitdone() waiting process. - */ - - if (priv->dcnt == -1 && priv->msgc > 0) - { - i2cinfo("Switch to new message\n"); - - /* Get current message to process data and copy to private structure */ - - priv->ptr = priv->msgv->buffer; /* Copy buffer to private struct */ - priv->dcnt = priv->msgv->length; /* Set counter of current msg length */ - priv->total_msg_len = priv->msgv->length; /* Set total msg length */ - priv->flags = priv->msgv->flags; /* Copy flags to private struct */ - - i2cinfo("Current flags %i\n", priv->flags); - - /* Decrease counter to indicate the number of messages left to - * process - */ - - priv->msgc--; - - /* Decrease message pointer. If last message set next message vector - * to null - */ - - if (priv->msgc == 0) - { - /* No more messages, don't need to increment msgv. This pointer - * will be set to zero when reaching the termination of the ISR - * calls, i.e. Messages handling(2/2). - */ - } - else - { - /* If not last message increment to next message to process */ - - priv->msgv++; - } - - /* Trace event */ - - stm32_i2c_traceevent(priv, I2CEVENT_MSG_HANDLING, priv->msgc); - } - - /* Note the event where we are on the last message and after the last - * byte is handled at the bottom of this function, as it terminates - * the repeated calls to the ISR. - */ - - /* I2C protocol logic - * - * I2C protocol logic follows. It's organized in an if else chain such that - * only one mode of operation is executed every time the ISR is called. - */ - - /* Address Handling - * - * Check if a start bit was set and transmit address with proper format. - * - * Note: - * On first call the start bit has been set by stm32_i2c_waitdone() - * Otherwise it will be set from this ISR. - * - * Remember that after a start bit an address has always to be sent. - */ - - if ((status & I2C_SR1_SB) != 0) - { - /* Start bit is set */ - - i2cinfo("Entering address handling, status = %" PRIi32 "\n", status); - - /* Check for empty message (for robustness) */ - - if (priv->dcnt > 0) - { - /* When reading messages of length 1 or 2 actions have to be taken - * during this event. The following block handles that. - */ - - if (priv->total_msg_len == 1 && (priv->flags & I2C_M_READ)) - { - i2cinfo("short read N=1: setting NACK\n"); - - /* Set POS bit to zero - * (can be up from a previous 2 byte receive) - */ - - stm32_i2c_modifyreg(priv, - STM32_I2C_CR1_OFFSET, I2C_CR1_POS, 0); - - /* Immediately set NACK */ - - stm32_i2c_modifyreg(priv, - STM32_I2C_CR1_OFFSET, I2C_CR1_ACK, 0); - stm32_i2c_traceevent(priv, I2CEVENT_ADDR_HDL_READ_1, 0); - } - else if (priv->total_msg_len == 2 && (priv->flags & I2C_M_READ)) - { - i2cinfo("short read N=2: setting POS and ACK bits\n"); - - stm32_i2c_modifyreg(priv, - STM32_I2C_CR1_OFFSET, 0, I2C_CR1_POS); - stm32_i2c_modifyreg(priv, - STM32_I2C_CR1_OFFSET, 0, I2C_CR1_ACK); - stm32_i2c_traceevent(priv, - I2CEVENT_ADDR_HDL_READ_2, 0); - } - else - { - /* Enable ACK after address byte */ - - i2cinfo("setting ACK\n"); - - /* Set POS bit to zero - * (can be up from a previous 2 byte receive) - */ - - stm32_i2c_modifyreg(priv, - STM32_I2C_CR1_OFFSET, I2C_CR1_POS, 0); - - /* ACK is the expected answer for N>=3 reads and writes */ - - stm32_i2c_modifyreg(priv, - STM32_I2C_CR1_OFFSET, 0, I2C_CR1_ACK); - } - - /* Send address byte with correct 8th bit set(for writing or - * reading) Transmission happens after having written to the - * data register STM32_I2C_DR - */ - - stm32_i2c_putreg(priv, STM32_I2C_DR_OFFSET, - (priv->flags & I2C_M_TEN) ? - 0 : ((priv->msgv->addr << 1) | - (priv->flags & I2C_M_READ))); - - i2cinfo("Address sent. Addr=%#02x Write/Read bit=%i\n", - priv->msgv->addr, (priv->flags & I2C_M_READ)); - - /* Flag that address has just been sent */ - - priv->check_addr_ack = true; - - stm32_i2c_traceevent(priv, I2CEVENT_SENDADDR, priv->msgv->addr); - } - else - { - /* TODO: untested!! */ - - i2cwarn("WARNING: An empty message has been detected, " - "ignoring and passing to next message.\n"); - - /* Trace event */ - - stm32_i2c_traceevent(priv, I2CEVENT_EMPTY_MSG, 0); - - /* Set condition to activate msg handling */ - - priv->dcnt = -1; - - /* Restart ISR by setting an interrupt buffer bit */ - - stm32_i2c_modifyreg(priv, - STM32_I2C_CR2_OFFSET, 0, I2C_CR2_ITBUFEN); - } - } - - /* Address cleared event - * - * Check if the address cleared, i.e. the driver found a valid - * address. - * If a NACK was received the address is invalid, if an ACK was - * received the address is valid and transmission can continue. - */ - - /* Check for NACK after an address */ - -#ifndef CONFIG_I2C_POLLED - /* When polling the i2c ISR it's not possible to determine when - * an address has been ACKed(i.e. the address is valid). - * - * The mechanism to deal a NACKed address is to wait for the I2C - * call to timeout (value defined in defconfig by one of the - * following: CONFIG_STM32_I2C_DYNTIMEO, CONFIG_STM32_I2CTIMEOSEC, - * CONFIG_STM32_I2CTIMEOMS, CONFIG_STM32_I2CTIMEOTICKS). - * - * To be safe in the case of a timeout/NACKed address a stop bit - * is set on the bus to clear it. In POLLED operation it's done - * stm32_i2c_transfer() after the call to stm32_i2c_sem_waitdone(). - * - * In ISR driven operation the stop bit in case of a NACKed address - * is set in the ISR itself. - * - * Note: this commentary is found in both places. - */ - - else if ((status & I2C_SR1_ADDR) == 0 && priv->check_addr_ack) - { - i2cinfo("Invalid Address."); - i2cinfo(" Setting stop bit and clearing message\n"); - i2cinfo("status %" PRIi32 "\n", status); - - /* Set condition to terminate msg chain transmission as address - * is invalid. - */ - - priv->dcnt = -1; - priv->msgc = 0; - - i2cinfo("dcnt %i , msgc %i\n", priv->dcnt, priv->msgc); - - /* Reset flag to check for valid address */ - - priv->check_addr_ack = false; - - /* Send stop bit to clear bus */ - - stm32_i2c_sendstop(priv); - - /* Trace event */ - - stm32_i2c_traceevent(priv, - I2CEVENT_ADDRESS_NACKED, priv->msgv->addr); - } -#endif - - /* ACK in read mode, ACK in write mode is handled separately */ - - else if ((priv->flags & I2C_M_READ) != 0 && (status & I2C_SR1_ADDR) != 0 && - priv->check_addr_ack) - { - /* Reset check addr flag as we are handling this event */ - - priv->check_addr_ack = false; - - /* Clear ADDR flag by reading SR2 and adding it to status */ - - status |= (stm32_i2c_getreg(priv, STM32_I2C_SR2_OFFSET) << 16); - - /* Note: - * - * When reading a single byte the stop condition has to be set - * immediately after clearing the state flags, which happens - * when reading SR2(as SR1 has already been read). - * - * Similarly when reading 2 bytes the NACK bit has to be set as just - * after the clearing of the address. - */ - - if (priv->dcnt == 1 && priv->total_msg_len == 1) - { - /* this should only happen when receiving a message of length 1 */ - - stm32_i2c_modifyreg(priv, - STM32_I2C_CR2_OFFSET, 0, I2C_CR2_ITBUFEN); - stm32_i2c_sendstop(priv); - - i2cinfo("Address ACKed beginning data reception\n"); - i2cinfo("short read N=1: programming stop bit\n"); - priv->dcnt--; - - /* Trace */ - - stm32_i2c_traceevent(priv, I2CEVENT_ADDRESS_ACKED_READ_1, 0); - } - else if (priv->dcnt == 2 && priv->total_msg_len == 2) - { - /* This should only happen when receiving a message of length 2 - * Set NACK - */ - - stm32_i2c_modifyreg(priv, STM32_I2C_CR1_OFFSET, I2C_CR1_ACK, 0); - - i2cinfo("Address ACKed beginning data reception\n"); - i2cinfo("short read N=2: programming NACK\n"); - - /* Trace */ - - stm32_i2c_traceevent(priv, I2CEVENT_ADDRESS_ACKED_READ_2, 0); - } - else - { - i2cinfo("Address ACKed beginning data reception\n"); - - /* Trace */ - - stm32_i2c_traceevent(priv, I2CEVENT_ADDRESS_ACKED, 0); - } - } - - /* Write mode - * - * Handles all write related I2C protocol logic. Also handles the - * ACK event after clearing the ADDR flag as the write has to - * begin immediately after. - */ - - else if ((priv->flags & (I2C_M_READ)) == 0 && - (status & (I2C_SR1_ADDR | I2C_SR1_TXE)) != 0) - { - /* The has cleared(ADDR is set, ACK was received after the address) - * or the transmit buffer is empty flag has been set(TxE) then we can - * transmit the next byte. - */ - - i2cinfo("Entering write mode dcnt = %i msgc = %i\n", - priv->dcnt, priv->msgc); - - /* Clear ADDR flag by reading SR2 and adding it to status */ - - status |= (stm32_i2c_getreg(priv, STM32_I2C_SR2_OFFSET) << 16); - - /* Address has cleared so don't check on next call */ - - priv->check_addr_ack = false; - - /* Check if we have transmitted the whole message or we are after - * the last byte where the stop condition or else(according to the - * msg flags) has to be set. - */ - - if (priv->dcnt >= 1) - { - /* Transmitting message. - * Send byte == write data into write register - */ - - stm32_i2c_putreg(priv, STM32_I2C_DR_OFFSET, *priv->ptr++); - - /* Decrease current message length */ - - stm32_i2c_traceevent(priv, I2CEVENT_WRITE_TO_DR, priv->dcnt); - priv->dcnt--; - } - else if (priv->dcnt == 0) - { - /* After last byte, check what to do based on next message flags */ - - if (priv->msgc == 0) - { - /* If last message send stop bit */ - - stm32_i2c_sendstop(priv); - i2cinfo("Stop sent dcnt = %i msgc = %i\n", - priv->dcnt, priv->msgc); - - /* Decrease counter to get to next message */ - - priv->dcnt--; - i2cinfo("dcnt %i\n", priv->dcnt); - stm32_i2c_traceevent(priv, I2CEVENT_WRITE_STOP, priv->dcnt); - } - - /* If there is a next message with no flags or the read flag - * a restart sequence has to be sent. - * Note msgv already points to the next message. - */ - - else if (priv->msgc > 0 && - (priv->msgv->flags == 0 || - (priv->msgv[0].flags & I2C_M_READ) != 0)) - { - stm32_i2c_sendstart(priv); - - i2cinfo("Restart detected!\n"); - i2cinfo("Nextflag %i\n", priv->msgv[0].flags); - - /* Decrease counter to get to next message */ - - priv->dcnt--; - i2cinfo("dcnt %i\n", priv->dcnt); - stm32_i2c_traceevent(priv, I2CEVENT_WRITE_RESTART, priv->dcnt); - } - - /* If there is a next message with the NO_RESTART flag - * do nothing. - */ - - else if (priv->msgc > 0 && - ((priv->msgv->flags & I2C_M_NOSTART) != 0)) - { - /* Set condition to get to next message */ - - priv->dcnt = -1; - stm32_i2c_traceevent(priv, - I2CEVENT_WRITE_NO_RESTART, priv->dcnt); - } - else - { - i2cerr( - "ERROR: Write mode: next message has an unrecognized flag.\n"); - stm32_i2c_traceevent(priv, I2CEVENT_WRITE_FLAG_ERROR, - priv->msgv->flags); - } - } - else - { - i2cerr("ERROR: Write mode error.\n"); - stm32_i2c_traceevent(priv, I2CEVENT_WRITE_ERROR, 0); - } - } - - /* Read mode - * - * Handles all read related I2C protocol logic. - * - * * * * * * * WARNING STM32F1xx HARDWARE ERRATA * * * * * * * - * source: https://github.com/hikob/openlab/blob/master/drivers/stm32/i2c.c - * - * RXNE-only events should not be handled since it sometimes - * fails. Only BTF & RXNE events should be handled (with the - * consequence of slowing down the transfer). - * - * It seems that when a RXNE interrupt is handled 'around' - * the end of the next byte reception, the DR register read - * is ignored by the i2c controller: it does not flush the - * DR with next byte - * - * Thus we read twice the same byte and we read effectively - * read one byte less than expected from the i2c slave point - * of view. - * - * Example: - * + we want to receive 6 bytes (B1 to B6) - * + the problem appear when reading B3 - * -> we read B1 B2 B3 B3 B4 B5(B3 twice) - * -> the i2c transfer was B1 B2 B3 B4 B5(B6 is not sent) - */ - - else if ((priv->flags & (I2C_M_READ)) != 0 && (status & I2C_SR1_RXNE) != 0) - { - /* When read flag is set and the receive buffer is not empty - * (RXNE is set) then the driver can read from the data register. - */ - - i2cinfo("Entering read mode dcnt = %i msgc = %i, status %" PRIi32 "\n", - priv->dcnt, priv->msgc, status); - - /* Implementation of method 2 for receiving data following - * the stm32f1xx reference manual. - */ - - /* Case total message length = 1 */ - - if (priv->dcnt == 0 && priv->total_msg_len == 1) - { - i2cinfo("short read N=1: Read data from data register(DR)\n"); - - *priv->ptr++ = stm32_i2c_getreg(priv, STM32_I2C_DR_OFFSET); - priv->dcnt--; - stm32_i2c_traceevent(priv, I2CEVENT_READ, 0); - } - - /* Case total message length = 2 */ - - else if (priv->dcnt == 2 && priv->total_msg_len == 2 && - !(status & I2C_SR1_BTF)) - { - i2cinfo("short read N=2: " - "DR full, SR empty. Waiting for more bytes.\n"); - stm32_i2c_traceevent(priv, I2CEVENT_READ_SR_EMPTY, 0); - } - else if (priv->dcnt == 2 && priv->total_msg_len == 2 && - (status & I2C_SR1_BTF)) - { - i2cinfo("short read N=2: " - "DR and SR full setting stop bit and reading twice\n"); - - stm32_i2c_sendstop(priv); - *priv->ptr++ = stm32_i2c_getreg(priv, STM32_I2C_DR_OFFSET); - priv->dcnt--; - *priv->ptr++ = stm32_i2c_getreg(priv, STM32_I2C_DR_OFFSET); - priv->dcnt--; - - /* Stop request already programmed so set dcnt for next message */ - - priv->dcnt--; - - /* Set trace */ - - stm32_i2c_traceevent(priv, I2CEVENT_READ_2, 0); - } - - /* Case total message length >= 3 */ - - else if (priv->total_msg_len >= 3 && !(status & I2C_SR1_BTF)) - { - /* If the shift register is still empty (i.e. BTF is low) - * then do nothing and wait for it to fill in the next ISR. - * (should not happen in ISR mode, but if using polled mode - * this should be able to handle it). - */ - - i2cinfo("DR full, SR empty. Waiting for more bytes.\n"); - stm32_i2c_traceevent(priv, I2CEVENT_READ_SR_EMPTY, 0); - } - else if (priv->dcnt >= 4 && - priv->total_msg_len >= 3 && (status & I2C_SR1_BTF)) - { - /* Read data from data register(DR). Note this clears the - * RXNE(receive buffer not empty) flag. - */ - - i2cinfo("Read data from data register(DR)\n"); - *priv->ptr++ = stm32_i2c_getreg(priv, STM32_I2C_DR_OFFSET); - - /* Decrease current message length */ - - priv->dcnt--; - stm32_i2c_traceevent(priv, I2CEVENT_READ, 0); - } - else if (priv->dcnt == 3 && - (status & I2C_SR1_BTF) && priv->total_msg_len >= 3) - { - /* This means that we are reading dcnt 3 and there is - * already dcnt 2 in the shift register. - * This coincides with EV7_2 in the reference manual. - */ - - i2cinfo("Program NACK\n"); - i2cinfo("Read data from data register(DR) dcnt=3\n"); - - stm32_i2c_traceevent(priv, I2CEVENT_READ_3, priv->dcnt); - - /* Program NACK */ - - stm32_i2c_modifyreg(priv, STM32_I2C_CR1_OFFSET, I2C_CR1_ACK, 0); - - /* Read dcnt = 3, to ensure a BTF event after having received - * in the shift register. - */ - - *priv->ptr++ = stm32_i2c_getreg(priv, STM32_I2C_DR_OFFSET); - - /* Decrease current message length */ - - priv->dcnt--; - } - else if (priv->dcnt == 2 && - (status & I2C_SR1_BTF) && priv->total_msg_len >= 3) - { - i2cinfo("Program stop\n"); - i2cinfo("Read data from data register(DR) dcnt=2\n"); - i2cinfo("Read data from data register(SR) dcnt=1\n"); - i2cinfo("Setting condition to stop ISR dcnt = -1\n"); - - stm32_i2c_traceevent(priv, I2CEVENT_READ_3, priv->dcnt); - - /* Program stop */ - - stm32_i2c_sendstop(priv); - - /* read dcnt = 2 */ - - *priv->ptr++ = stm32_i2c_getreg(priv, STM32_I2C_DR_OFFSET); - - /* read last byte dcnt=1 */ - - *priv->ptr++ = stm32_i2c_getreg(priv, STM32_I2C_DR_OFFSET); - - /* Stop already sent will not get another interrupt set - * condition to stop ISR - */ - - priv->dcnt = -1; - } - - /* Error handling for read mode */ - - else - { - i2cerr("ERROR: I2C read mode no correct state detected\n"); - i2cerr(" state %" PRIi32 ", dcnt=%i\n", status, priv->dcnt); - - /* set condition to terminate ISR and wake waiting thread */ - - priv->dcnt = -1; - priv->msgc = 0; - stm32_i2c_traceevent(priv, I2CEVENT_READ_ERROR, 0); - } - - /* Read rest of the state */ - - status |= (stm32_i2c_getreg(priv, STM32_I2C_SR2_OFFSET) << 16); - } - - /* Empty call handler - * - * Case to handle an empty call to the ISR where it only has to - * Shutdown - */ - - else if (priv->dcnt == -1 && priv->msgc == 0) - { - /* Read rest of the state */ - - status |= (stm32_i2c_getreg(priv, STM32_I2C_SR2_OFFSET) << 16); - i2cwarn("WARNING: Empty call to ISR: Stopping ISR\n"); - stm32_i2c_traceevent(priv, I2CEVENT_ISR_EMPTY_CALL, 0); - } - - /* Error handler - * - * Gets triggered if the driver does not recognize a situation(state) - * it can deal with. - * This should not happen in interrupt based operation(i.e. when - * CONFIG_I2C_POLLED is not set in the defconfig file). - * During polled operation(i.e. CONFIG_I2C_POLLED=y in defconfig) - * this case should do nothing but tracing the event that the - * device wasn't ready yet. - */ - - else - { -#ifdef CONFIG_I2C_POLLED - stm32_i2c_traceevent(priv, I2CEVENT_POLL_DEV_NOT_RDY, 0); -#else - /* Read rest of the state */ - - status |= (stm32_i2c_getreg(priv, STM32_I2C_SR2_OFFSET) << 16); - - i2cerr("ERROR: " - "No correct state detected(start bit, read or write)\n"); - i2cerr(" state %" PRIi32 "\n", status); - - /* Set condition to terminate ISR and wake waiting thread */ - - priv->dcnt = -1; - priv->msgc = 0; - stm32_i2c_traceevent(priv, I2CEVENT_STATE_ERROR, 0); -#endif - } - - /* Messages handling(2/2) - * - * Transmission of the whole message chain has been completed. We have to - * terminate the ISR and wake up stm32_i2c_transfer() that is waiting for - * the ISR cycle to handle the sending/receiving of the messages. - */ - - /* First check for errors */ - - if ((status & I2C_SR1_ERRORMASK) != 0) - { - stm32_i2c_traceevent(priv, - I2CEVENT_ISR_SR1ERROR, - status & I2C_SR1_ERRORMASK); - - /* Clear interrupt flags */ - - stm32_i2c_putreg(priv, STM32_I2C_SR1_OFFSET, 0); - - priv->dcnt = -1; - priv->msgc = 0; - } - - if (priv->dcnt == -1 && priv->msgc == 0) - { - i2cinfo("Shutting down I2C ISR\n"); - - stm32_i2c_traceevent(priv, I2CEVENT_ISR_SHUTDOWN, 0); - - /* Clear internal pointer to the message content. - * Good practice + done by last implementation when messages are - * finished (compatibility concerns) - */ - - priv->msgv = NULL; - -#ifdef CONFIG_I2C_POLLED - priv->intstate = INTSTATE_DONE; -#else - /* Clear all interrupts */ - - regval = stm32_i2c_getreg(priv, STM32_I2C_CR2_OFFSET); - regval &= ~I2C_CR2_ALLINTS; - stm32_i2c_putreg(priv, STM32_I2C_CR2_OFFSET, regval); - - /* Is there a thread waiting for this event(there should be) */ - - if (priv->intstate == INTSTATE_WAITING) - { - /* Yes.. inform the thread that the transfer is complete - * and wake it up. - */ - - nxsem_post(&priv->sem_isr); - priv->intstate = INTSTATE_DONE; - } -#endif - } - - return OK; -} - -/**************************************************************************** - * Name: stm32_i2c_isr - * - * Description: - * Common I2C interrupt service routine - * - ****************************************************************************/ - -#ifndef CONFIG_I2C_POLLED -static int stm32_i2c_isr(int irq, void *context, void *arg) -{ - struct stm32_i2c_priv_s *priv = (struct stm32_i2c_priv_s *)arg; - - DEBUGASSERT(priv != NULL); - return stm32_i2c_isr_process(priv); -} -#endif - -/**************************************************************************** - * Name: stm32_i2c_init - * - * Description: - * Setup the I2C hardware, ready for operation with defaults - * - ****************************************************************************/ - -static int stm32_i2c_init(struct stm32_i2c_priv_s *priv) -{ - /* Power-up and configure GPIOs */ - - /* Enable power and reset the peripheral */ - - modifyreg32(STM32_RCC_APB1ENR, 0, priv->config->clk_bit); - modifyreg32(STM32_RCC_APB1RSTR, 0, priv->config->reset_bit); - modifyreg32(STM32_RCC_APB1RSTR, priv->config->reset_bit, 0); - - /* Configure pins */ - - if (stm32_configgpio(priv->config->scl_pin) < 0) - { - return ERROR; - } - - if (stm32_configgpio(priv->config->sda_pin) < 0) - { - stm32_unconfiggpio(priv->config->scl_pin); - return ERROR; - } - - /* Attach ISRs */ - -#ifndef CONFIG_I2C_POLLED - irq_attach(priv->config->ev_irq, stm32_i2c_isr, priv); - irq_attach(priv->config->er_irq, stm32_i2c_isr, priv); - up_enable_irq(priv->config->ev_irq); - up_enable_irq(priv->config->er_irq); -#endif - - /* Set peripheral frequency, where it must be at least 2 MHz for 100 kHz - * or 4 MHz for 400 kHz. This also disables all I2C interrupts. - */ - - stm32_i2c_putreg(priv, - STM32_I2C_CR2_OFFSET, (STM32_PCLK1_FREQUENCY / 1000000)); - - /* Force a frequency update */ - - priv->frequency = 0; - - stm32_i2c_setclock(priv, 100000); - - /* Enable I2C */ - - stm32_i2c_putreg(priv, STM32_I2C_CR1_OFFSET, I2C_CR1_PE); - return OK; -} - -/**************************************************************************** - * Name: stm32_i2c_deinit - * - * Description: - * Shutdown the I2C hardware - * - ****************************************************************************/ - -static int stm32_i2c_deinit(struct stm32_i2c_priv_s *priv) -{ - /* Disable I2C */ - - stm32_i2c_putreg(priv, STM32_I2C_CR1_OFFSET, 0); - - /* Unconfigure GPIO pins */ - - stm32_unconfiggpio(priv->config->scl_pin); - stm32_unconfiggpio(priv->config->sda_pin); - - /* Disable and detach interrupts */ - -#ifndef CONFIG_I2C_POLLED - up_disable_irq(priv->config->ev_irq); - up_disable_irq(priv->config->er_irq); - irq_detach(priv->config->ev_irq); - irq_detach(priv->config->er_irq); -#endif - - /* Disable clocking */ - - modifyreg32(STM32_RCC_APB1ENR, priv->config->clk_bit, 0); - return OK; -} - -/**************************************************************************** - * Device Driver Operations - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_i2c_transfer - * - * Description: - * Generic I2C transfer function - * - ****************************************************************************/ - -static int stm32_i2c_transfer(struct i2c_master_s *dev, - struct i2c_msg_s *msgs, int count) -{ - struct stm32_i2c_priv_s *priv = (struct stm32_i2c_priv_s *)dev; - uint32_t status = 0; -#ifdef I2C1_FSMC_CONFLICT - uint32_t ahbenr; -#endif - int ret; - - DEBUGASSERT(dev != NULL && msgs != NULL && count > 0); - - /* Ensure that address or flags don't change meanwhile */ - - ret = nxmutex_lock(&priv->lock); - if (ret < 0) - { - return ret; - } - -#ifdef I2C1_FSMC_CONFLICT - /* Disable FSMC that shares a pin with I2C1 (LBAR) */ - - ahbenr = stm32_i2c_disablefsmc(priv); - -#else - /* Wait for any STOP in progress. NOTE: If we have to disable the FSMC - * then we cannot do this at the top of the loop, unfortunately. The STOP - * will not complete normally if the FSMC is enabled. - */ - - stm32_i2c_sem_waitstop(priv); -#endif - - /* Clear any pending error interrupts */ - - stm32_i2c_putreg(priv, STM32_I2C_SR1_OFFSET, 0); - - /* "Note: When the STOP, START or PEC bit is set, the software must - * not perform any write access to I2C_CR1 before this bit is - * cleared by hardware. Otherwise there is a risk of setting a - * second STOP, START or PEC request." However, if the bits are - * not cleared by hardware, then we will have to do that from hardware. - */ - - stm32_i2c_clrstart(priv); - - /* Old transfers are done */ - - priv->msgv = msgs; - priv->msgc = count; - - /* Reset I2C trace logic */ - - stm32_i2c_tracereset(priv); - - /* Set I2C clock frequency (on change it toggles I2C_CR1_PE !) - * REVISIT: Note that the frequency is set only on the first message. - * This could be extended to support different transfer frequencies for - * each message segment. - */ - - stm32_i2c_setclock(priv, msgs->frequency); - - /* Trigger start condition, then the process moves into the ISR. I2C - * interrupts will be enabled within stm32_i2c_waitdone(). - * - * Initialize current message length counter to zero. This is needed to - * process the first message(first priv->msgv entry) correctly. - */ - - priv->dcnt = -1; - priv->status = 0; - stm32_i2c_sendstart(priv); - - /* Wait for an ISR, if there was a timeout, fetch latest status to get - * the BUSY flag. - */ - - if (stm32_i2c_sem_waitdone(priv) < 0) - { - status = stm32_i2c_getstatus(priv); - ret = -ETIMEDOUT; - - i2cerr("ERROR: Timed out: CR1: 0x%04x status: 0x%08" PRIx32 "\n", - stm32_i2c_getreg(priv, STM32_I2C_CR1_OFFSET), status); - - /* "Note: When the STOP, START or PEC bit is set, the software must - * not perform any write access to I2C_CR1 before this bit is - * cleared by hardware. Otherwise there is a risk of setting a - * second STOP, START or PEC request." - */ - - stm32_i2c_clrstart(priv); - -#ifdef CONFIG_I2C_POLLED - /* When polling the i2c ISR it's not possible to determine when - * an address has been ACKed(i.e. the address is valid). - * - * The mechanism to deal a NACKed address is to wait for the I2C - * call to timeout(value defined in defconfig by one of the - * following: CONFIG_STM32_I2C_DYNTIMEO, CONFIG_STM32_I2CTIMEOSEC, - * CONFIG_STM32_I2CTIMEOMS, CONFIG_STM32_I2CTIMEOTICKS). - * - * To be safe in the case of a timeout/NACKed address a stop bit - * is set on the bus to clear it. In POLLED operation it's done - * stm32_i2c_transfer() after the call to stm32_i2c_sem_waitdone(). - * - * In ISR driven operation the stop bit in case of a NACKed address - * is set in the ISR itself. - * - * Note: this commentary is found in both places. - * - */ - - i2cinfo("Check if the address was valid\n"); - stm32_i2c_sendstop(priv); -#endif - /* Clear busy flag in case of timeout */ - - status = priv->status & 0xffff; - } - else - { - /* clear SR2 (BUSY flag) as we've done successfully */ - - status = priv->status & 0xffff; - } - - /* Check for error status conditions */ - - if ((status & I2C_SR1_ERRORMASK) != 0) - { - /* I2C_SR1_ERRORMASK is the 'OR' of the following individual bits: */ - - if (status & I2C_SR1_BERR) - { - /* Bus Error */ - - ret = -EIO; - } - else if (status & I2C_SR1_ARLO) - { - /* Arbitration Lost (master mode) */ - - ret = -EAGAIN; - } - else if (status & I2C_SR1_AF) - { - /* Acknowledge Failure */ - - ret = -ENXIO; - } - else if (status & I2C_SR1_OVR) - { - /* Overrun/Underrun */ - - ret = -EIO; - } - else if (status & I2C_SR1_PECERR) - { - /* PEC Error in reception */ - - ret = -EPROTO; - } - else if (status & I2C_SR1_TIMEOUT) - { - /* Timeout or Tlow Error */ - - ret = -ETIME; - } - - /* This is not an error and should never happen since SMBus is not - * enabled - */ - - else /* if (status & I2C_SR1_SMBALERT) */ - { - /* SMBus alert is an optional signal with an interrupt line for - * devices that want to trade their ability to master for a pin. - */ - - ret = -EINTR; - } - } - - /* This is not an error, but should not happen. The BUSY signal can hang, - * however, if there are unhealthy devices on the bus that need to be - * reset. - * NOTE: We will only see this busy indication if stm32_i2c_sem_waitdone() - * fails above; Otherwise it is cleared. - */ - - else if ((status & (I2C_SR2_BUSY << 16)) != 0) - { - /* I2C Bus is for some reason busy */ - - ret = -EBUSY; - } - - /* Dump the trace result */ - - stm32_i2c_tracedump(priv); - -#ifdef I2C1_FSMC_CONFLICT - /* Wait for any STOP in progress. NOTE: If we have to disable the FSMC - * then we cannot do this at the top of the loop, unfortunately. The STOP - * will not complete normally if the FSMC is enabled. - */ - - stm32_i2c_sem_waitstop(priv); - - /* Re-enable the FSMC */ - - stm32_i2c_enablefsmc(ahbenr); -#endif - - nxmutex_unlock(&priv->lock); - return ret; -} - -/**************************************************************************** - * Name: stm32_i2c_reset - * - * Description: - * Perform an I2C bus reset in an attempt to break loose stuck I2C devices. - * - * Input Parameters: - * dev - Device-specific state data - * - * Returned Value: - * Zero (OK) on success; a negated errno value on failure. - * - ****************************************************************************/ - -#ifdef CONFIG_I2C_RESET -static int stm32_i2c_reset(struct i2c_master_s *dev) -{ - struct stm32_i2c_priv_s *priv = (struct stm32_i2c_priv_s *)dev; - unsigned int clock_count; - unsigned int stretch_count; - uint32_t scl_gpio; - uint32_t sda_gpio; - uint32_t frequency; - int ret; - - DEBUGASSERT(dev); - - /* Our caller must own a ref */ - - DEBUGASSERT(priv->refs > 0); - - /* Lock out other clients */ - - ret = nxmutex_lock(&priv->lock); - if (ret < 0) - { - return ret; - } - - ret = -EIO; - - /* Save the current frequency */ - - frequency = priv->frequency; - - /* De-init the port */ - - stm32_i2c_deinit(priv); - - /* Use GPIO configuration to un-wedge the bus */ - - scl_gpio = MKI2C_OUTPUT(priv->config->scl_pin); - sda_gpio = MKI2C_OUTPUT(priv->config->sda_pin); - - /* Let SDA go high */ - - stm32_gpiowrite(sda_gpio, 1); - - /* Clock the bus until any slaves currently driving it let it go. */ - - clock_count = 0; - while (!stm32_gpioread(sda_gpio)) - { - /* Give up if we have tried too hard */ - - if (clock_count++ > 10) - { - goto out; - } - - /* Sniff to make sure that clock stretching has finished. - * - * If the bus never relaxes, the reset has failed. - */ - - stretch_count = 0; - while (!stm32_gpioread(scl_gpio)) - { - /* Give up if we have tried too hard */ - - if (stretch_count++ > 10) - { - goto out; - } - - up_udelay(10); - } - - /* Drive SCL low */ - - stm32_gpiowrite(scl_gpio, 0); - up_udelay(10); - - /* Drive SCL high again */ - - stm32_gpiowrite(scl_gpio, 1); - up_udelay(10); - } - - /* Generate a start followed by a stop to reset slave - * state machines. - */ - - stm32_gpiowrite(sda_gpio, 0); - up_udelay(10); - stm32_gpiowrite(scl_gpio, 0); - up_udelay(10); - stm32_gpiowrite(scl_gpio, 1); - up_udelay(10); - stm32_gpiowrite(sda_gpio, 1); - up_udelay(10); - - /* Revert the GPIO configuration. */ - - stm32_unconfiggpio(sda_gpio); - stm32_unconfiggpio(scl_gpio); - - /* Re-init the port */ - - stm32_i2c_init(priv); - - /* Restore the frequency */ - - stm32_i2c_setclock(priv, frequency); - ret = OK; - -out: - - /* Release the port for reuse by other clients */ - - nxmutex_unlock(&priv->lock); - return ret; -} -#endif /* CONFIG_I2C_RESET */ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_i2cbus_initialize - * - * Description: - * Initialize one I2C bus - * - ****************************************************************************/ - -struct i2c_master_s *stm32_i2cbus_initialize(int port) -{ - struct stm32_i2c_priv_s *priv = NULL; - - /* Get I2C private structure */ - - switch (port) - { -#ifdef CONFIG_STM32_I2C1 - case 1: - priv = (struct stm32_i2c_priv_s *)&stm32_i2c1_priv; - break; -#endif -#ifdef CONFIG_STM32_I2C2 - case 2: - priv = (struct stm32_i2c_priv_s *)&stm32_i2c2_priv; - break; -#endif -#ifdef CONFIG_STM32_I2C3 - case 3: - priv = (struct stm32_i2c_priv_s *)&stm32_i2c3_priv; - break; -#endif - default: - return NULL; - } - - /* Initialize private data for the first time, increment reference count, - * power-up hardware and configure GPIOs. - */ - - nxmutex_lock(&priv->lock); - if (priv->refs++ == 0) - { - stm32_i2c_init(priv); - } - - nxmutex_unlock(&priv->lock); - return (struct i2c_master_s *)priv; -} - -/**************************************************************************** - * Name: stm32_i2cbus_uninitialize - * - * Description: - * Uninitialize an I2C bus - * - ****************************************************************************/ - -int stm32_i2cbus_uninitialize(struct i2c_master_s *dev) -{ - struct stm32_i2c_priv_s *priv = (struct stm32_i2c_priv_s *)dev; - - DEBUGASSERT(dev); - - /* Decrement reference count and check for underflow */ - - if (priv->refs == 0) - { - return ERROR; - } - - nxmutex_lock(&priv->lock); - if (--priv->refs) - { - nxmutex_unlock(&priv->lock); - return OK; - } - - /* Disable power and other HW resource (GPIO's) */ - - stm32_i2c_deinit(priv); - nxmutex_unlock(&priv->lock); - - return OK; -} - -#endif /* CONFIG_STM32_STM32F10XX || CONFIG_STM32_STM32F20XX || CONFIG_STM32_STM32F4XXX */ -#endif /* CONFIG_STM32_I2C1 || CONFIG_STM32_I2C2 || CONFIG_STM32_I2C3 */ diff --git a/arch/arm/src/stm32/stm32_i2c_v2.c b/arch/arm/src/stm32/stm32_i2c_v2.c deleted file mode 100644 index 87d9a1700e0ba..0000000000000 --- a/arch/arm/src/stm32/stm32_i2c_v2.c +++ /dev/null @@ -1,2829 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_i2c_v2.c - * - * SPDX-License-Identifier: BSD-3-Clause - * SPDX-FileCopyrightText: 2016-2017 Gregory Nutt. All rights reserved. - * SPDX-FileCopyrightText: 2016 Doug Vetter. All rights reserved. - * SPDX-FileCopyrightText: 2011 Uros Platise. All rights reserved. - * SPDX-FileContributor: Uros Platise - * SPDX-FileContributor: Gregory Nutt - * SPDX-FileContributor: John Wharington - * SPDX-FileContributor: David Sidrane - * SPDX-FileContributor: Bob Feretich - * SPDX-FileContributor: Doug Vetter - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -/* -------------------------------------------------------------------------- - * - * STM32 I2C IPv2 I2C Driver - * - * Supports: - * - Master operation: - * Standard-mode (up to 100 kHz) - * Fast-mode (up to 400 kHz) - * Fast-mode Plus (up to 1 MHz) - * fI2CCLK clock source selection is based on STM32_RCC_DCKCFGR2_I2CxSRC - * being set to HSI and the calculations are based on - * STM32_HSI_FREQUENCY of 16mHz - * - * - Multiple instances (shared bus) - * - Interrupt based operation - * - RELOAD support - * - * Unsupported, possible future work: - * - More effective error reporting to higher layers - * - Slave operation - * - Support of fI2CCLK frequencies other than HSI - * - Polled operation (code present but untested) - * - SMBus support - * - Multi-master support - * - IPMI - * - * Test Environment: - * - * - NUCLEO-F303ZE - * - * Operational Status: - * - * All supported features have been tested and found to be operational. - * - * Although the RELOAD capability has been tested as it was required to - * implement the I2C_M_NOSTART flag on F3 hardware, the associated - * logic to support the transfer messages with more than 255 byte - * payloads has not been tested as the author lacked access to a real - * device supporting these types of transfers. - * - * Performance Benchmarks: TBD - * - * Time to transfer two messages, each a byte in length, in addition to the - * START condition, in interrupt mode: - * - * DEBUG enabled (development): TBDms - * Excessive delay here is caused by printing to the console and - * is of no concern. - * - * DEBUG disabled (production): TBSus - * Between Messages: TBDus - * Between Bytes: TBDus - * - * Implementation: - * - * - Device: structure as defined by the nuttx/i2c/i2c.h - * - * - Instance: represents each individual access to the I2C driver, obtained - * by the i2c_init(); it extends the Device structure from the - * nuttx/i2c/i2c.h; Instance points to OPS, to common I2C Hardware - * private data and contains its own private data including frequency, - * address and mode of operation. - * - * - Private: Private data of an I2C Hardware - * - * High Level Functional Description - * - * This driver works with I2C "messages" (struct i2c_msg_s), which carry a - * buffer intended to transfer data to, or store data read from, the I2C bus. - * - * As the hardware can only transmit or receive one byte at a time the basic - * job of the driver (and the ISR specifically) is to process each message in - * the order they are stored in the message list, one byte at a time. When - * no messages are left the ISR exits and returns the result to the caller. - * - * The order of the list of I2C messages provided to the driver is important - * and dependent upon the hardware in use. A typical I2C transaction between - * the F3 as an I2C Master and some other IC as a I2C Slave requires two - * messages that communicate the: - * - * 1) Subaddress (register offset on the slave device) - * 2) Data sent to or read from the device - * - * These messages will typically be one byte in length but may be up to 2^31 - * bytes in length. Incidentally, the maximum length is limited only because - * i2c_msg_s.length is a signed int for some odd reason. - * - * Interrupt mode relies on the following interrupt events: - * - * TXIS - Transmit interrupt - * (data transmitted to bus and acknowledged) - * NACKF - Not Acknowledge Received - * (data transmitted to bus and NOT acknowledged) - * RXNE - Receive interrupt - * (data received from bus) - * TC - Transfer Complete - * (All bytes in message transferred) - * TCR - Transfer Complete (Reload) - * (Current batch of bytes in message transferred) - * - * The driver currently supports Single Master mode only. Slave mode is not - * supported. Additionally, the driver runs in Software End Mode (AUTOEND - * disabled) so the driver is responsible for telling the hardware what to - * do at the end of a transfer. - * - * -------------------------------------------------------------------------- - * - * Configuration: - * - * To use this driver, enable the following configuration variable: - * - * CONFIG_STM32_I2C1 - * CONFIG_STM32_I2C2 - * CONFIG_STM32_I2C3 - * CONFIG_STM32_I2C4 - * - * To configure the ISR timeout using fixed values - * (CONFIG_STM32_I2C_DYNTIMEO=n): - * - * CONFIG_STM32_I2CTIMEOSEC (Timeout in seconds) - * CONFIG_STM32_I2CTIMEOMS (Timeout in milliseconds) - * CONFIG_STM32_I2CTIMEOTICKS (Timeout in ticks) - * - * To configure the ISR timeout using dynamic values - * (CONFIG_STM32_I2C_DYNTIMEO=y): - * - * CONFIG_STM32_I2C_DYNTIMEO_USECPERBYTE - * (Timeout in microseconds per byte) - * CONFIG_STM32_I2C_DYNTIMEO_STARTSTOP - * (Timeout for start/stop in milliseconds) - * - * Debugging output enabled with: - * - * CONFIG_DEBUG_FEATURES and CONFIG_DEBUG_I2C_{ERROR|WARN|INFO} - * - * ISR Debugging output may be enabled with: - * - * CONFIG_DEBUG_FEATURES and CONFIG_DEBUG_I2C_INFO - * - * -------------------------------------------------------------------------- - * - * References: - * - * RM0431: - * ST STM322xxx and STM323xxx Reference Manual - * Document ID: DocID029480 Revision 1, Jan 2017. - * - * RM0316: - * ST STM326xxx and STM327xxx Reference Manual - * Document ID: DocID028270 Revision 2, April 2016. - * - * DATASHEET: - * ST STM3277xx/STM3278Ax/STM3279x Datasheet - * Document ID: DocID028294, Revision 3, May 2016. - * - * ERRATA: - * STM326xxx/STM327xxx Errata sheet Rev A device limitations - * Document ID: DocID028806, Revision 2, April 2016. - * - * I2CSPEC: - * I2C Bus Specification and User Manual - * Document ID: UM10204, Revision 6, April 2014. - * - * -------------------------------------------------------------------------- - */ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include - -#include - -#include "arm_internal.h" -#include "stm32_rcc.h" -#include "stm32_i2c.h" -#include "stm32_gpio.h" - -/* At least one I2C peripheral must be enabled */ - -#if defined(CONFIG_STM32_I2C1) || defined(CONFIG_STM32_I2C2) || \ - defined(CONFIG_STM32_I2C3) || defined(CONFIG_STM32_I2C4) - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#warning TODO: check I2C clock source. It must be HSI! -#undef INVALID_CLOCK_SOURCE - -#if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) || \ - defined(CONFIG_STM32_STM32F37XX) -# if STM32_HSI_FREQUENCY != 8000000 || defined(INVALID_CLOCK_SOURCE) -# error STM32_I2C: Peripheral clock is HSI and it must be 8MHz or the speed/timing calculations need to be redone. -# endif -#elif defined(CONFIG_STM32_STM32G4XXX) -# if STM32_HSI_FREQUENCY != 16000000 || defined(INVALID_CLOCK_SOURCE) -# error STM32_I2C: Peripheral clock is HSI and it must be 16MHz or the speed/timing calculations need to be redone. -# endif -#else -# error STM32_I2C: Device not Supported. -#endif - -/* CONFIG_I2C_POLLED may be set so that I2C interrupts will not be used. - * Instead, CPU-intensive polling will be used. - */ - -/* Interrupt wait timeout in seconds and milliseconds */ - -#if !defined(CONFIG_STM32_I2CTIMEOSEC) && !defined(CONFIG_STM32_I2CTIMEOMS) -# define CONFIG_STM32_I2CTIMEOSEC 0 -# define CONFIG_STM32_I2CTIMEOMS 500 /* Default is 500 milliseconds */ -# warning "Using Default 500 Ms Timeout" -#elif !defined(CONFIG_STM32_I2CTIMEOSEC) -# define CONFIG_STM32_I2CTIMEOSEC 0 /* User provided milliseconds */ -#elif !defined(CONFIG_STM32_I2CTIMEOMS) -# define CONFIG_STM32_I2CTIMEOMS 0 /* User provided seconds */ -#endif - -/* Interrupt wait time timeout in system timer ticks */ - -#ifndef CONFIG_STM32_I2CTIMEOTICKS -# define CONFIG_STM32_I2CTIMEOTICKS \ - (SEC2TICK(CONFIG_STM32_I2CTIMEOSEC) + MSEC2TICK(CONFIG_STM32_I2CTIMEOMS)) -#endif - -#ifndef CONFIG_STM32_I2C_DYNTIMEO_STARTSTOP -# define CONFIG_STM32_I2C_DYNTIMEO_STARTSTOP TICK2USEC(CONFIG_STM32_I2CTIMEOTICKS) -#endif - -/* Macros to convert a I2C pin to a GPIO output */ - -#define I2C_OUTPUT (GPIO_OUTPUT | GPIO_FLOAT | GPIO_OPENDRAIN |\ - GPIO_SPEED_50MHz | GPIO_OUTPUT_SET) - -#define MKI2C_OUTPUT(p) (((p) & (GPIO_PORT_MASK | GPIO_PIN_MASK)) | I2C_OUTPUT) - -#define I2C_CR1_TXRX (I2C_CR1_RXIE | I2C_CR1_TXIE) -#define I2C_CR1_ALLINTS (I2C_CR1_TXRX | I2C_CR1_TCIE | I2C_CR1_ERRIE) - -/* Unused bit in I2c_ISR used to communicate a bad state has occurred in - * the isr processing - */ - -#define I2C_INT_BAD_STATE 0x8000000 - -/* I2C event tracing - * - * To enable tracing statements which show the details of the state machine - * enable the following configuration variable: - * - * CONFIG_I2C_TRACE - * - * Note: This facility uses syslog, which sends output to the console by - * default. No other debug configuration variables are required. - */ - -#ifndef CONFIG_I2C_TRACE -# define stm32_i2c_tracereset(p) -# define stm32_i2c_tracenew(p,s) -# define stm32_i2c_traceevent(p,e,a) -# define stm32_i2c_tracedump(p) -#endif - -#ifndef CONFIG_I2C_NTRACE -# define CONFIG_I2C_NTRACE 32 -#endif - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/* Interrupt state */ - -enum stm32_intstate_e -{ - INTSTATE_IDLE = 0, /* No I2C activity */ - INTSTATE_WAITING, /* Waiting for completion of interrupt activity */ - INTSTATE_DONE, /* Interrupt activity complete */ -}; - -/* Trace events */ - -enum stm32_trace_e -{ - I2CEVENT_NONE = 0, - I2CEVENT_STATE_ERROR, - I2CEVENT_ISR_SHUTDOWN, - I2CEVENT_ISR_CALL, - I2CEVENT_ISR_EMPTY_CALL, - I2CEVENT_MSG_HANDLING, - I2CEVENT_POLL_NOT_READY, - I2CEVENT_EMPTY_MSG, - I2CEVENT_START, - I2CEVENT_ADDRESS_ACKED, - I2CEVENT_ADDRESS_NACKED, - I2CEVENT_NACK, - I2CEVENT_READ, - I2CEVENT_READ_ERROR, - I2CEVENT_WRITE_TO_DR, - I2CEVENT_WRITE_STOP, - I2CEVENT_WRITE_RESTART, - I2CEVENT_WRITE_NO_RESTART, - I2CEVENT_WRITE_ERROR, - I2CEVENT_WRITE_FLAG_ERROR, - I2CEVENT_TC_RESTART, - I2CEVENT_TC_NO_RESTART -}; - -/* Trace data */ - -struct stm32_trace_s -{ - uint32_t status; /* I2C 32-bit SR2|SR1 status */ - uint32_t count; /* Interrupt count when status change */ - enum stm32_intstate_e event; /* Last event that occurred with this status */ - uint32_t parm; /* Parameter associated with the event */ - clock_t time; /* First of event or first status */ -}; - -/* I2C Device hardware configuration */ - -struct stm32_i2c_config_s -{ - uint32_t base; /* I2C base address */ - uint32_t clk_bit; /* Clock enable bit */ - uint32_t reset_bit; /* Reset bit */ - uint32_t scl_pin; /* GPIO configuration for SCL as SCL */ - uint32_t sda_pin; /* GPIO configuration for SDA as SDA */ -#ifndef CONFIG_I2C_POLLED - uint32_t ev_irq; /* Event IRQ */ - uint32_t er_irq; /* Error IRQ */ -#endif -}; - -/* I2C Device Private Data */ - -struct stm32_i2c_priv_s -{ - /* Port configuration */ - - const struct stm32_i2c_config_s *config; - - int refs; /* Reference count */ - mutex_t lock; /* Mutual exclusion mutex */ -#ifndef CONFIG_I2C_POLLED - sem_t sem_isr; /* Interrupt wait semaphore */ -#endif - volatile uint8_t intstate; /* Interrupt handshake (see enum stm32_intstate_e) */ - - uint8_t msgc; /* Message count */ - struct i2c_msg_s *msgv; /* Message list */ - uint8_t *ptr; /* Current message buffer */ - uint32_t frequency; /* Current I2C frequency */ - int dcnt; /* Current message bytes remaining to transfer */ - uint16_t flags; /* Current message flags */ - bool astart; /* START sent */ - - /* I2C trace support */ - -#ifdef CONFIG_I2C_TRACE - int tndx; /* Trace array index */ - clock_t start_time; /* Time when the trace was started */ - - /* The actual trace data */ - - struct stm32_trace_s trace[CONFIG_I2C_NTRACE]; -#endif - - uint32_t status; /* End of transfer SR2|SR1 status */ - -#ifdef CONFIG_PM - struct pm_callback_s pm_cb; /* PM callbacks */ -#endif -}; - -/* I2C Device, Instance */ - -struct stm32_i2c_inst_s -{ - const struct i2c_ops_s *ops; /* Standard I2C operations */ - struct stm32_i2c_priv_s *priv; /* Common driver private data structure */ -}; - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -static inline uint16_t stm32_i2c_getreg(struct stm32_i2c_priv_s *priv, - uint8_t offset); -static inline void stm32_i2c_putreg(struct stm32_i2c_priv_s *priv, - uint8_t offset, uint16_t value); -static inline void stm32_i2c_putreg32(struct stm32_i2c_priv_s *priv, - uint8_t offset, uint32_t value); -static inline void stm32_i2c_modifyreg32(struct stm32_i2c_priv_s *priv, - uint8_t offset, uint32_t clearbits, - uint32_t setbits); -#ifdef CONFIG_STM32_I2C_DYNTIMEO -static uint32_t stm32_i2c_toticks(int msgc, struct i2c_msg_s *msgs); -#endif /* CONFIG_STM32_I2C_DYNTIMEO */ -static inline int stm32_i2c_sem_waitdone(struct stm32_i2c_priv_s *priv); -static inline void stm32_i2c_sem_waitstop(struct stm32_i2c_priv_s *priv); -#ifdef CONFIG_I2C_TRACE -static void stm32_i2c_tracereset(struct stm32_i2c_priv_s *priv); -static void stm32_i2c_tracenew(struct stm32_i2c_priv_s *priv, - uint32_t status); -static void stm32_i2c_traceevent(struct stm32_i2c_priv_s *priv, - enum stm32_trace_e event, uint32_t parm); -static void stm32_i2c_tracedump(struct stm32_i2c_priv_s *priv); -#endif /* CONFIG_I2C_TRACE */ -static void stm32_i2c_setclock(struct stm32_i2c_priv_s *priv, - uint32_t frequency); -static inline void stm32_i2c_sendstart(struct stm32_i2c_priv_s *priv); -static inline void stm32_i2c_sendstop(struct stm32_i2c_priv_s *priv); -static inline -uint32_t stm32_i2c_getstatus(struct stm32_i2c_priv_s *priv); -static int stm32_i2c_isr_process(struct stm32_i2c_priv_s *priv); -#ifndef CONFIG_I2C_POLLED -static int stm32_i2c_isr(int irq, void *context, void *arg); -#endif -static int stm32_i2c_init(struct stm32_i2c_priv_s *priv); -static int stm32_i2c_deinit(struct stm32_i2c_priv_s *priv); - -static int stm32_i2c_process(struct i2c_master_s *dev, - struct i2c_msg_s *msgs, int count); -static int stm32_i2c_transfer(struct i2c_master_s *dev, - struct i2c_msg_s *msgs, int count); -#ifdef CONFIG_I2C_RESET -static int stm32_i2c_reset(struct i2c_master_s *dev); -#endif -#ifdef CONFIG_PM -static int stm32_i2c_pm_prepare(struct pm_callback_s *cb, int domain, - enum pm_state_e pmstate); -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -#ifdef CONFIG_STM32_I2C1 -static const struct stm32_i2c_config_s stm32_i2c1_config = -{ - .base = STM32_I2C1_BASE, - .clk_bit = RCC_APB1ENR_I2C1EN, - .reset_bit = RCC_APB1RSTR_I2C1RST, - .scl_pin = GPIO_I2C1_SCL, - .sda_pin = GPIO_I2C1_SDA, -#ifndef CONFIG_I2C_POLLED - .ev_irq = STM32_IRQ_I2C1EV, - .er_irq = STM32_IRQ_I2C1ER -#endif -}; - -static struct stm32_i2c_priv_s stm32_i2c1_priv = -{ - .config = &stm32_i2c1_config, - .refs = 0, - .lock = NXMUTEX_INITIALIZER, -#ifndef CONFIG_I2C_POLLED - .sem_isr = SEM_INITIALIZER(0), -#endif - .intstate = INTSTATE_IDLE, - .msgc = 0, - .msgv = NULL, - .ptr = NULL, - .frequency = 0, - .dcnt = 0, - .flags = 0, - .status = 0, -#ifdef CONFIG_PM - .pm_cb.prepare = stm32_i2c_pm_prepare, -#endif -}; -#endif - -#ifdef CONFIG_STM32_I2C2 -static const struct stm32_i2c_config_s stm32_i2c2_config = -{ - .base = STM32_I2C2_BASE, - .clk_bit = RCC_APB1ENR_I2C2EN, - .reset_bit = RCC_APB1RSTR_I2C2RST, - .scl_pin = GPIO_I2C2_SCL, - .sda_pin = GPIO_I2C2_SDA, -#ifndef CONFIG_I2C_POLLED - .ev_irq = STM32_IRQ_I2C2EV, - .er_irq = STM32_IRQ_I2C2ER -#endif -}; - -static struct stm32_i2c_priv_s stm32_i2c2_priv = -{ - .config = &stm32_i2c2_config, - .refs = 0, - .lock = NXMUTEX_INITIALIZER, -#ifndef CONFIG_I2C_POLLED - .sem_isr = SEM_INITIALIZER(0), -#endif - .intstate = INTSTATE_IDLE, - .msgc = 0, - .msgv = NULL, - .ptr = NULL, - .frequency = 0, - .dcnt = 0, - .flags = 0, - .status = 0, -#ifdef CONFIG_PM - .pm_cb.prepare = stm32_i2c_pm_prepare, -#endif -}; -#endif - -#ifdef CONFIG_STM32_I2C3 -static const struct stm32_i2c_config_s stm32_i2c3_config = -{ - .base = STM32_I2C3_BASE, - .clk_bit = RCC_APB1ENR_I2C3EN, - .reset_bit = RCC_APB1RSTR_I2C3RST, - .scl_pin = GPIO_I2C3_SCL, - .sda_pin = GPIO_I2C3_SDA, -#ifndef CONFIG_I2C_POLLED - .ev_irq = STM32_IRQ_I2C3EV, - .er_irq = STM32_IRQ_I2C3ER -#endif -}; - -static struct stm32_i2c_priv_s stm32_i2c3_priv = -{ - .config = &stm32_i2c3_config, - .refs = 0, - .lock = NXMUTEX_INITIALIZER, -#ifndef CONFIG_I2C_POLLED - .sem_isr = SEM_INITIALIZER(0), -#endif - .intstate = INTSTATE_IDLE, - .msgc = 0, - .msgv = NULL, - .ptr = NULL, - .frequency = 0, - .dcnt = 0, - .flags = 0, - .status = 0, -#ifdef CONFIG_PM - .pm_cb.prepare = stm32_i2c_pm_prepare, -#endif -}; -#endif - -#ifdef CONFIG_STM32_I2C4 -static const struct stm32_i2c_config_s stm32_i2c4_config = -{ - .base = STM32_I2C4_BASE, - .clk_bit = RCC_APB1ENR_I2C4EN, - .reset_bit = RCC_APB1RSTR_I2C4RST, - .scl_pin = GPIO_I2C4_SCL, - .sda_pin = GPIO_I2C4_SDA, -#ifndef CONFIG_I2C_POLLED - .ev_irq = STM32_IRQ_I2C4EV, - .er_irq = STM32_IRQ_I2C4ER -#endif -}; - -static struct stm32_i2c_priv_s stm32_i2c4_priv = -{ - .config = &stm32_i2c4_config, - .refs = 0, - .lock = NXMUTEX_INITIALIZER, -#ifndef CONFIG_I2C_POLLED - .sem_isr = SEM_INITIALIZER(0), -#endif - .intstate = INTSTATE_IDLE, - .msgc = 0, - .msgv = NULL, - .ptr = NULL, - .frequency = 0, - .dcnt = 0, - .flags = 0, - .status = 0, -#ifdef CONFIG_PM - .pm_cb.prepare = stm32_i2c_pm_prepare, -#endif -}; -#endif - -/* Device Structures, Instantiation */ - -static const struct i2c_ops_s stm32_i2c_ops = -{ - .transfer = stm32_i2c_transfer, -#ifdef CONFIG_I2C_RESET - .reset = stm32_i2c_reset, -#endif -}; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_i2c_getreg - * - * Description: - * Get a 16-bit register value by offset - * - ****************************************************************************/ - -static inline uint16_t stm32_i2c_getreg(struct stm32_i2c_priv_s *priv, - uint8_t offset) -{ - return getreg16(priv->config->base + offset); -} - -/**************************************************************************** - * Name: stm32_i2c_getreg32 - * - * Description: - * Get a 32-bit register value by offset - * - ****************************************************************************/ - -static inline uint32_t stm32_i2c_getreg32(struct stm32_i2c_priv_s *priv, - uint8_t offset) -{ - return getreg32(priv->config->base + offset); -} - -/**************************************************************************** - * Name: stm32_i2c_putreg - * - * Description: - * Put a 16-bit register value by offset - * - ****************************************************************************/ - -static inline void stm32_i2c_putreg(struct stm32_i2c_priv_s *priv, - uint8_t offset, uint16_t value) -{ - putreg16(value, priv->config->base + offset); -} - -/**************************************************************************** - * Name: stm32_i2c_putreg32 - * - * Description: - * Put a 32-bit register value by offset - * - ****************************************************************************/ - -static inline void stm32_i2c_putreg32(struct stm32_i2c_priv_s *priv, - uint8_t offset, uint32_t value) -{ - putreg32(value, priv->config->base + offset); -} - -/**************************************************************************** - * Name: stm32_i2c_modifyreg32 - * - * Description: - * Modify a 32-bit register value by offset - * - ****************************************************************************/ - -static inline void stm32_i2c_modifyreg32(struct stm32_i2c_priv_s *priv, - uint8_t offset, uint32_t clearbits, - uint32_t setbits) -{ - modifyreg32(priv->config->base + offset, clearbits, setbits); -} - -/**************************************************************************** - * Name: stm32_i2c_toticks - * - * Description: - * Return a micro-second delay based on the number of bytes left to be - * processed. - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_I2C_DYNTIMEO -static uint32_t stm32_i2c_toticks(int msgc, struct i2c_msg_s *msgs) -{ - size_t bytecount = 0; - int i; - - /* Count the number of bytes left to process */ - - for (i = 0; i < msgc; i++) - { - bytecount += msgs[i].length; - } - - /* Then return a number of microseconds based on a user provided scaling - * factor. - */ - - return USEC2TICK(CONFIG_STM32_I2C_DYNTIMEO_USECPERBYTE * bytecount); -} -#endif - -/**************************************************************************** - * Name: stm32_i2c_enableinterrupts - * - * Description: - * Enable I2C interrupts - * - ****************************************************************************/ - -#ifndef CONFIG_I2C_POLLED -static inline void stm32_i2c_enableinterrupts(struct stm32_i2c_priv_s *priv) -{ - stm32_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, 0, - (I2C_CR1_TXRX | I2C_CR1_NACKIE)); -} -#endif - -/**************************************************************************** - * Name: stm32_i2c_sem_waitdone - * - * Description: - * Wait for a transfer to complete - * - * There are two versions of this function. The first is included when using - * interrupts while the second is used if polling (CONFIG_I2C_POLLED=y). - * - ****************************************************************************/ - -#ifndef CONFIG_I2C_POLLED -static inline int stm32_i2c_sem_waitdone(struct stm32_i2c_priv_s *priv) -{ - irqstate_t flags; - int ret; - - flags = enter_critical_section(); - - /* Enable I2C interrupts */ - - /* The TXIE and RXIE interrupts are enabled initially in stm32_i2c_process. - * The remainder of the interrupts, including error-related, are enabled - * here. - */ - - stm32_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, 0, - (I2C_CR1_ALLINTS & ~I2C_CR1_TXRX)); - - /* Signal the interrupt handler that we are waiting */ - - priv->intstate = INTSTATE_WAITING; - do - { - /* Wait until either the transfer is complete or the timeout expires */ - -#ifdef CONFIG_STM32_I2C_DYNTIMEO - ret = nxsem_tickwait_uninterruptible(&priv->sem_isr, - stm32_i2c_toticks(priv->msgc, priv->msgv)); -#else - ret = nxsem_tickwait_uninterruptible(&priv->sem_isr, - CONFIG_STM32_I2CTIMEOTICKS); -#endif - if (ret < 0) - { - /* Break out of the loop on irrecoverable errors. This would - * include timeouts and mystery errors reported by - * nxsem_tickwait_uninterruptible. - */ - - break; - } - } - - /* Loop until the interrupt level transfer is complete. */ - - while (priv->intstate != INTSTATE_DONE); - - /* Set the interrupt state back to IDLE */ - - priv->intstate = INTSTATE_IDLE; - - /* Disable I2C interrupts */ - - stm32_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, I2C_CR1_ALLINTS, 0); - - leave_critical_section(flags); - return ret; -} -#else -static inline int stm32_i2c_sem_waitdone(struct stm32_i2c_priv_s *priv) -{ - clock_t timeout; - clock_t start; - clock_t elapsed; - int ret; - - /* Get the timeout value */ - -#ifdef CONFIG_STM32_I2C_DYNTIMEO - timeout = stm32_i2c_toticks(priv->msgc, priv->msgv); -#else - timeout = CONFIG_STM32_I2CTIMEOTICKS; -#endif - - /* Signal the interrupt handler that we are waiting. NOTE: Interrupts - * are currently disabled but will be temporarily re-enabled below when - * nxsem_tickwait_uninterruptible() sleeps. - */ - - priv->intstate = INTSTATE_WAITING; - start = clock_systime_ticks(); - - do - { - /* Calculate the elapsed time */ - - elapsed = clock_systime_ticks() - start; - - /* Poll by simply calling the timer interrupt handler until it - * reports that it is done. - */ - - stm32_i2c_isr_process(priv); - } - - /* Loop until the transfer is complete. */ - - while (priv->intstate != INTSTATE_DONE && elapsed < timeout); - - i2cinfo("intstate: %d elapsed: %ld threshold: %ld status:" - " 0x%08" PRIx32 "\n", - priv->intstate, (long)elapsed, (long)timeout, priv->status); - - /* Set the interrupt state back to IDLE */ - - ret = priv->intstate == INTSTATE_DONE ? OK : -ETIMEDOUT; - priv->intstate = INTSTATE_IDLE; - return ret; -} -#endif - -/**************************************************************************** - * Name: stm32_i2c_set_7bit_address - * - * Description: - * - ****************************************************************************/ - -static inline void -stm32_i2c_set_7bit_address(struct stm32_i2c_priv_s *priv) -{ - stm32_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, I2C_CR2_SADD7_MASK, - ((priv->msgv->addr & 0x7f) << I2C_CR2_SADD7_SHIFT)); -} - -/**************************************************************************** - * Name: stm32_i2c_set_bytes_to_transfer - * - * Description: - * - ****************************************************************************/ - -static inline void -stm32_i2c_set_bytes_to_transfer(struct stm32_i2c_priv_s *priv, - uint8_t n_bytes) -{ - stm32_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, I2C_CR2_NBYTES_MASK, - (n_bytes << I2C_CR2_NBYTES_SHIFT)); -} - -/**************************************************************************** - * Name: stm32_i2c_set_write_transfer_dir - * - * Description: - * - ****************************************************************************/ - -static inline void -stm32_i2c_set_write_transfer_dir(struct stm32_i2c_priv_s *priv) -{ - stm32_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, I2C_CR2_RD_WRN, 0); -} - -/**************************************************************************** - * Name: stm32_i2c_set_read_transfer_dir - * - * Description: - * - ****************************************************************************/ - -static inline void -stm32_i2c_set_read_transfer_dir(struct stm32_i2c_priv_s *priv) -{ - stm32_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, 0, I2C_CR2_RD_WRN); -} - -/**************************************************************************** - * Name: stm32_i2c_enable_reload - * - * Description: - * - ****************************************************************************/ - -static inline void -stm32_i2c_enable_reload(struct stm32_i2c_priv_s *priv) -{ - stm32_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, 0, I2C_CR2_RELOAD); -} - -/**************************************************************************** - * Name: stm32_i2c_disable_reload - * - * Description: - * - ****************************************************************************/ - -static inline void -stm32_i2c_disable_reload(struct stm32_i2c_priv_s *priv) -{ - stm32_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, I2C_CR2_RELOAD, 0); -} - -/**************************************************************************** - * Name: stm32_i2c_sem_waitstop - * - * Description: - * Wait for a STOP to complete - * - ****************************************************************************/ - -static inline void stm32_i2c_sem_waitstop(struct stm32_i2c_priv_s *priv) -{ - clock_t start; - clock_t elapsed; - clock_t timeout; - uint32_t cr; - uint32_t sr; - - /* Select a timeout */ - -#ifdef CONFIG_STM32_I2C_DYNTIMEO - timeout = USEC2TICK(CONFIG_STM32_I2C_DYNTIMEO_STARTSTOP); -#else - timeout = CONFIG_STM32_I2CTIMEOTICKS; -#endif - - /* Wait as stop might still be in progress */ - - start = clock_systime_ticks(); - do - { - /* Calculate the elapsed time */ - - elapsed = clock_systime_ticks() - start; - - /* Check for STOP condition */ - - cr = stm32_i2c_getreg32(priv, STM32_I2C_CR2_OFFSET); - if ((cr & I2C_CR2_STOP) == 0) - { - return; - } - - /* Check for timeout error */ - - sr = stm32_i2c_getreg(priv, STM32_I2C_ISR_OFFSET); - if ((sr & I2C_INT_TIMEOUT) != 0) - { - return; - } - } - - /* Loop until the stop is complete or a timeout occurs. */ - - while (elapsed < timeout); - - /* If we get here then a timeout occurred with the STOP condition - * still pending. - */ - - i2cinfo("Timeout with CR: %04" PRIx32 " SR: %04" PRIx32 "\n", cr, sr); -} - -/**************************************************************************** - * Name: stm32_i2c_trace* - * - * Description: - * I2C trace instrumentation - * - ****************************************************************************/ - -#ifdef CONFIG_I2C_TRACE -static void stm32_i2c_traceclear(struct stm32_i2c_priv_s *priv) -{ - struct stm32_trace_s *trace = &priv->trace[priv->tndx]; - - trace->status = 0; /* I2C 32-bit status */ - trace->count = 0; /* Interrupt count when status change */ - trace->event = I2CEVENT_NONE; /* Last event that occurred with this status */ - trace->parm = 0; /* Parameter associated with the event */ - trace->time = 0; /* Time of first status or event */ -} - -static void stm32_i2c_tracereset(struct stm32_i2c_priv_s *priv) -{ - /* Reset the trace info for a new data collection */ - - priv->tndx = 0; - priv->start_time = clock_systime_ticks(); - stm32_i2c_traceclear(priv); -} - -static void stm32_i2c_tracenew(struct stm32_i2c_priv_s *priv, - uint32_t status) -{ - struct stm32_trace_s *trace = &priv->trace[priv->tndx]; - - /* Is the current entry uninitialized? Has the status changed? */ - - if (trace->count == 0 || status != trace->status) - { - /* Yes.. Was it the status changed? */ - - if (trace->count != 0) - { - /* Yes.. bump up the trace index - * (unless we are out of trace entries) - */ - - if (priv->tndx >= (CONFIG_I2C_NTRACE - 1)) - { - i2cerr("ERROR: Trace table overflow\n"); - return; - } - - priv->tndx++; - trace = &priv->trace[priv->tndx]; - } - - /* Initialize the new trace entry */ - - stm32_i2c_traceclear(priv); - trace->status = status; - trace->count = 1; - trace->time = clock_systime_ticks(); - } - else - { - /* Just increment the count of times that we have seen this status */ - - trace->count++; - } -} - -static void stm32_i2c_traceevent(struct stm32_i2c_priv_s *priv, - enum stm32_trace_e event, uint32_t parm) -{ - struct stm32_trace_s *trace; - - if (event != I2CEVENT_NONE) - { - trace = &priv->trace[priv->tndx]; - - /* Initialize the new trace entry */ - - trace->event = event; - trace->parm = parm; - - /* Bump up the trace index (unless we are out of trace entries) */ - - if (priv->tndx >= (CONFIG_I2C_NTRACE - 1)) - { - i2cerr("ERROR: Trace table overflow\n"); - return; - } - - priv->tndx++; - stm32_i2c_traceclear(priv); - } -} - -static void stm32_i2c_tracedump(struct stm32_i2c_priv_s *priv) -{ - struct stm32_trace_s *trace; - int i; - - syslog(LOG_DEBUG, "Elapsed time: %d\n", - (int)(clock_systime_ticks() - priv->start_time)); - - for (i = 0; i < priv->tndx; i++) - { - trace = &priv->trace[i]; - syslog(LOG_DEBUG, - "%2d. STATUS: %08" PRIx32 " COUNT: %3d EVENT: %2d PARM:" - " %08" PRIx32 " TIME: %d\n", - i + 1, trace->status, trace->count, trace->event, trace->parm, - (int)(trace->time - priv->start_time)); - } -} -#endif /* CONFIG_I2C_TRACE */ - -/**************************************************************************** - * Name: stm32_i2c_setclock - * - * Description: - * - * Sets the I2C bus clock frequency by configuring the I2C_TIMINGR register. - * - * This function supports bus clock frequencies of: - * - * 1000Khz (Fast Mode+) - * 400Khz (Fast Mode) - * 100Khz (Standard Mode) - * 10Khz (Standard Mode) - * - * Attempts to set a different frequency will quietly provision the default - * of 10Khz. - * - * The only differences between the various modes of operation (std, fast, - * fast+) are the bus clock speed and setup/hold times. Setup/hold times - * are specified as a MINIMUM time for the given mode, and naturally std - * mode has the longest minimum times. As a result, by provisioning - * setup/hold times for std mode they are also compatible with fast/fast+, - * though some performance degradation occurs in fast/fast+ as a result of - * the times being somewhat longer than strictly required. The values - * remain as they are because reliability is favored over performance. - * - * Clock Selection: - * - * The I2C peripheral clock can be provided by either PCLK1, SYSCLK or the - * HSI. - * - * PCLK1 >------|\ I2CCLK - * SYSCLK >------| |---------> - * HSI >------|/ - * - * HSI is the default and is always 8Mhz. - * - * SYSCLK can, in turn, be derived from the HSI, HSE, PPLCLK. - * - * HSI >------|\ - * | | SYSCLK - * PLL >------| |---------> - * | | - * HSE >------|/ - * - * - * References: - * - * App Note AN4235 and the associated software STSW-STM32126. - * - ****************************************************************************/ - -static void stm32_i2c_setclock(struct stm32_i2c_priv_s *priv, - uint32_t frequency) -{ - uint8_t presc; - uint8_t scl_delay; - uint8_t sda_delay; - uint8_t scl_h_period; - uint8_t scl_l_period; - - /* I2C peripheral must be disabled to update clocking configuration. - * This will SW reset the device. - */ - - stm32_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, I2C_CR1_PE, 0); - - if (frequency != priv->frequency) - { - /* The Speed and timing calculation are based on the following - * fI2CCLK = HSI and is 16Mhz - * Analog filter is on, - * Digital filter off - * Rise Time is 120 ns and fall is 10ns - * Mode is FastMode - */ - - if (frequency == 100000) - { - presc = 0; - scl_delay = 5; - sda_delay = 0; - scl_h_period = 61; - scl_l_period = 89; - } - else if (frequency == 400000) - { - presc = 0; - scl_delay = 3; - sda_delay = 0; - scl_h_period = 6; - scl_l_period = 24; - } - else if (frequency == 1000000) - { - presc = 0; - scl_delay = 2; - sda_delay = 0; - scl_h_period = 1; - scl_l_period = 5; - } - else - { - presc = 7; - scl_delay = 0; - sda_delay = 0; - scl_h_period = 35; - scl_l_period = 162; - } - - uint32_t timingr = - (presc << I2C_TIMINGR_PRESC_SHIFT) | - (scl_delay << I2C_TIMINGR_SCLDEL_SHIFT) | - (sda_delay << I2C_TIMINGR_SDADEL_SHIFT) | - (scl_h_period << I2C_TIMINGR_SCLH_SHIFT) | - (scl_l_period << I2C_TIMINGR_SCLL_SHIFT); - - stm32_i2c_putreg32(priv, STM32_I2C_TIMINGR_OFFSET, timingr); - priv->frequency = frequency; - } - - /* Enable I2C peripheral */ - - stm32_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, 0, I2C_CR1_PE); -} - -/**************************************************************************** - * Name: stm32_i2c_sendstart - * - * Description: - * Send the START condition / force Master mode - * - * A START condition in I2C consists of a single byte that contains both - * the 7 bit slave address and a read/write bit (0 = WRITE, 1 = READ). - * If the address is recognized by one of the slave devices that slave - * device will ACK the byte so that data transfers can begin. - * - * A RESTART (or repeated START per the I2CSPEC) is simply a START - * condition issued in the middle of a transfer (i.e. after the initial - * START and before a STOP). A RESTART sends a new address byte and R/W - * bit to the bus. A RESTART is optional in most cases but mandatory in - * the event the transfer direction is changed. - * - * Most of the time reading data from an I2C slave requires a WRITE of the - * subaddress followed by a READ (and hence a RESTART in between). Writing - * to an I2C slave typically requires only WRITE operations and hence no - * RESTARTs. - * - * This function is therefore called both at the beginning of a transfer - * (START) and at appropriate times during a transfer (RESTART). - * - ****************************************************************************/ - -static inline void stm32_i2c_sendstart(struct stm32_i2c_priv_s *priv) -{ - bool next_norestart = false; - - /* Set the private "current message" data used in protocol processing. - * - * ptr: A pointer to the start of the current message buffer. This is - * advanced after each byte in the current message is transferred. - * - * dcnt: A running counter of the bytes in the current message waiting to - * be transferred. This is decremented each time a byte is - * transferred. The hardware normally accepts a maximum of 255 bytes - * per transfer but can support more via the RELOAD mechanism. - * If dcnt initially exceeds 255, the RELOAD mechanism will be - * enabled automatically. - * - * flags: Used to characterize handling of the current message. - * - * The default flags value is 0 which specifies: - * - * - A transfer direction of WRITE (R/W bit = 0) - * - RESTARTs between all messages - * - * The following flags can be used to override this behavior as follows: - * - * - I2C_M_READ: Sets the transfer direction to READ (R/W bit = 1) - * - I2C_M_NOSTART: Prevents a RESTART from being issued prior to the - * transfer of the message (where allowed by the protocol). - * - */ - - priv->ptr = priv->msgv->buffer; - priv->dcnt = priv->msgv->length; - priv->flags = priv->msgv->flags; - - if ((priv->flags & I2C_M_NOSTART) == 0) - { - /* Flag the first byte as an address byte */ - - priv->astart = true; - } - - /* Enabling RELOAD allows the transfer of: - * - * - individual messages with a payload exceeding 255 bytes - * - multiple messages back to back without a RESTART in between - * - * so we enable it if either of those conditions exist and disable - * it otherwise. - */ - - /* Check if there are multiple messages and the next is a continuation */ - - if (priv->msgc > 1) - { - next_norestart = (((priv->msgv + 1)->flags & I2C_M_NOSTART) != 0); - } - - if (next_norestart || priv->dcnt > 255) - { - i2cinfo("RELOAD enabled: dcnt = %i msgc = %i\n", - priv->dcnt, priv->msgc); - stm32_i2c_enable_reload(priv); - } - else - { - i2cinfo("RELOAD disable: dcnt = %i msgc = %i\n", - priv->dcnt, priv->msgc); - stm32_i2c_disable_reload(priv); - } - - /* Set the number of bytes to transfer (I2C_CR2->NBYTES) to the number of - * bytes in the current message or 255, whichever is lower so as to not - * exceed the hardware maximum allowed. - */ - - if (priv->dcnt > 255) - { - stm32_i2c_set_bytes_to_transfer(priv, 255); - } - else - { - stm32_i2c_set_bytes_to_transfer(priv, priv->dcnt); - } - - /* Set the (7 bit) address. - * 10 bit addressing is not yet supported. - */ - - stm32_i2c_set_7bit_address(priv); - - /* The flag of the current message is used to determine the direction of - * transfer required for the current message. - */ - - if (priv->flags & I2C_M_READ) - { - stm32_i2c_set_read_transfer_dir(priv); - } - else - { - stm32_i2c_set_write_transfer_dir(priv); - } - - /* Set the I2C_CR2->START bit to 1 to instruct the hardware to send the - * START condition using the address and transfer direction data entered. - */ - - i2cinfo("Sending START: dcnt=%i msgc=%i flags=0x%04x\n", - priv->dcnt, priv->msgc, priv->flags); - - stm32_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, 0, I2C_CR2_START); -} - -/**************************************************************************** - * Name: stm32_i2c_sendstop - * - * Description: - * Send the STOP conditions - * - * A STOP condition can be requested by setting the STOP bit in the I2C_CR2 - * register. Setting the STOP bit clears the TC flag and the STOP condition - * is sent on the bus. - * - ****************************************************************************/ - -static inline void stm32_i2c_sendstop(struct stm32_i2c_priv_s *priv) -{ - i2cinfo("Sending STOP\n"); - stm32_i2c_traceevent(priv, I2CEVENT_WRITE_STOP, 0); - - stm32_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, 0, I2C_CR2_STOP); -} - -/**************************************************************************** - * Name: stm32_i2c_getstatus - * - * Description: - * Get 32-bit status (SR1 and SR2 combined) - * - ****************************************************************************/ - -static inline uint32_t stm32_i2c_getstatus(struct stm32_i2c_priv_s *priv) -{ - return getreg32(priv->config->base + STM32_I2C_ISR_OFFSET); -} - -/**************************************************************************** - * Name: stm32_i2c_clearinterrupts - * - * Description: - * Clear all interrupts - * - ****************************************************************************/ - -static inline void stm32_i2c_clearinterrupts(struct stm32_i2c_priv_s *priv) -{ - stm32_i2c_modifyreg32(priv, STM32_I2C_ICR_OFFSET, 0, I2C_ICR_CLEARMASK); -} - -/**************************************************************************** - * Name: stm32_i2c_isr_process - * - * Description: - * Common interrupt service routine (ISR) that handles I2C protocol logic. - * This is instantiated for each configured I2C interface - * (I2C1, I2C2, I2C3). - * - * This ISR is activated and deactivated by: - * - * stm32_i2c_process - * and - * stm32_i2c_waitdone - * - * Input Parameters: - * priv - The private struct of the I2C driver. - * - ****************************************************************************/ - -static int stm32_i2c_isr_process(struct stm32_i2c_priv_s *priv) -{ - uint32_t status; - - /* Get state of the I2C controller */ - - status = stm32_i2c_getreg32(priv, STM32_I2C_ISR_OFFSET); - - i2cinfo("ENTER: status = 0x%08" PRIx32 "\n", status); - - /* Update private version of the state assuming a good state */ - - priv->status = status & ~I2C_INT_BAD_STATE; - - /* If this is a new transmission set up the trace table accordingly */ - - stm32_i2c_tracenew(priv, status); - stm32_i2c_traceevent(priv, I2CEVENT_ISR_CALL, 0); - - /* ------------------- Start of I2C protocol handling ------------------ */ - - /* I2C protocol logic follows. It's organized in an if else chain such - * that only one mode of operation is executed every time the ISR is - * called. - * - * If you need to add additional states to support new features be sure - * they continue the chain (i.e. begin with "else if") and are placed - * before the empty call / error states at the end of the chain. - */ - - /* NACK Handling - * - * This branch is only triggered when the NACK (Not Acknowledge Received) - * interrupt occurs. This interrupt will only fire when the - * I2C_CR1->NACKIE bit is 1. - * - * I2C_ISR->NACKF is set by hardware when a NACK is received after a - * byte is transmitted and the slave fails to acknowledge it. This is - * the opposite of, and mutually exclusive to, the I2C_ISR->TXIS event. - * - * In response to the NACK the hardware automatically triggers generation - * of a STOP condition, terminating the transfer. The only valid response - * to this state is to exit the ISR and report the failure. - * - * To differentiate an "address NACK" from a NACK that might occur during - * the transfer of other bytes the "priv->astart" parameter is - * used. This flag is set to TRUE in sendstart() and set to FALSE when - * the first TXIS event is received, which would be after the first byte - * (the address) is transmitted successfully (acknowledged). - */ - - if (status & I2C_INT_NACK) - { - if (priv->astart == true) - { - /* NACK received on first (address) byte: address is invalid */ - - i2cinfo("NACK: Address invalid: dcnt=%i msgc=%i " - "status=0x%08" PRIx32 "\n", - priv->dcnt, priv->msgc, status); - stm32_i2c_traceevent(priv, I2CEVENT_ADDRESS_NACKED, - priv->msgv->addr); - } - else - { - /* NACK received on regular byte */ - - i2cinfo("NACK: NACK received: dcnt=%i msgc=%i " - "status=0x%08" PRIx32 "\n", - priv->dcnt, priv->msgc, status); - stm32_i2c_traceevent(priv, I2CEVENT_ADDRESS_NACKED, - priv->msgv->addr); - } - - /* Set flags to terminate message transmission: - * - * set message length to -1 to indicate last byte of message sent - * set message count to 0 to indicate no more messages to send - * - * As we fall through the logic in the ISR the message handling block - * will be triggered by these flags and signal the ISR to terminate. - */ - - priv->dcnt = -1; - priv->msgc = 0; - } - - /* Transmit Interrupt Status (TXIS) Handler - * - * This branch is only triggered when the TXIS interrupt occurs. This - * interrupt will only fire when the I2C_CR1->TXIE bit is 1. - * - * This indicates the transmit data register I2C_TXDR has been emptied - * following the successful transmission of a byte and slave - * acknowledgment. - * In this state the I2C_TXDR register is ready to accept another byte for - * transmission. The TXIS bit will be cleared automatically when the next - * byte is written to I2C_TXDR. - * - * The number of TXIS events during the transfer corresponds to NBYTES. - * - * The TXIS flag is not set when a NACK is received. - * - * When RELOAD is disabled (RELOAD=0) and NBYTES data have been - * transferred: - * - * - In Automatic End Mode (AUTOEND=1), a STOP is automatically sent. - * - * Note: Automatic End Mode is not currently supported. - * - * - In Software End Mode (AUTOEND=0), the TC event occurs and the SCL - * line is stretched low in order to allow software actions (STOP, - * RESTART). - * - * When RELOAD is enabled (RELOAD=1) and NBYTES bytes have been transferred - * a TCR event occurs instead and that handler simply updates NBYTES which - * causes TXIS events to continue. The process repeats until all bytes in - * the message have been transferred. - */ - - else if ((priv->flags & (I2C_M_READ)) == 0 && - (status & (I2C_ISR_TXIS)) != 0) - { - /* TXIS interrupt occurred, address valid, ready to transmit */ - - stm32_i2c_traceevent(priv, I2CEVENT_WRITE, 0); - i2cinfo("TXIS: ENTER dcnt = %i msgc = %i status 0x%08" PRIx32 "\n", - priv->dcnt, priv->msgc, status); - - /* The first event after the address byte is sent will be either TXIS - * or NACKF so it's safe to set the astart flag to false on - * the first TXIS event to indicate that it is no longer necessary to - * check for address validity. - */ - - if (priv->astart == true) - { - i2cinfo("TXIS: Address Valid\n"); - stm32_i2c_traceevent(priv, I2CEVENT_ADDRESS_ACKED, - priv->msgv->addr); - priv->astart = false; - } - - /* If one or more bytes in the current message are ready to transmit */ - - if (priv->dcnt > 0) - { - /* Prepare to transmit the current byte */ - - stm32_i2c_traceevent(priv, I2CEVENT_WRITE_TO_DR, priv->dcnt); - i2cinfo("TXIS: Write Data 0x%02x\n", *priv->ptr); - - /* Decrement byte counter */ - - priv->dcnt--; - - /* If we are about to transmit the last byte in the current - * message - */ - - if (priv->dcnt == 0) - { - /* If this is also the last message to send, disable RELOAD so - * TC fires next and issues STOP condition. If we don't do - * this TCR will fire next, and since there are no bytes to - * send we can't write NBYTES to clear TCR so it will fire - * forever. - */ - - if (priv->msgc == 1) - { - stm32_i2c_disable_reload(priv); - } - } - - /* Transmit current byte */ - - stm32_i2c_putreg(priv, STM32_I2C_TXDR_OFFSET, *priv->ptr); - - /* Advance to next byte */ - - priv->ptr++; - } - else - { - /* Unsupported state */ - - i2cerr("ERROR: TXIS Unsupported state detected, dcnt=%i, " - "status 0x%08" PRIx32 "\n", - priv->dcnt, status); - stm32_i2c_traceevent(priv, I2CEVENT_WRITE_ERROR, 0); - - /* Indicate the bad state, - * so that on termination HW will be reset - */ - - priv->status |= I2C_INT_BAD_STATE; - } - - i2cinfo("TXIS: EXIT dcnt = %i msgc = %i status 0x%08" PRIx32 "\n", - priv->dcnt, priv->msgc, status); - } - - /* Receive Buffer Not Empty (RXNE) State Handler - * - * This branch is only triggered when the RXNE interrupt occurs. This - * interrupt will only fire when the I2C_CR1->RXIE bit is 1. - * - * This indicates data has been received from the bus and is waiting to - * be read from the I2C_RXDR register. When I2C_RXDR is read this bit - * is automatically cleared and then an ACK or NACK is sent depending on - * whether we have more bytes to receive. - * - * When RELOAD is disabled and bytes remain to be transferred an - * acknowledge is automatically sent on the bus and the RXNE events - * continue until the last byte is received. - * - * When RELOAD is disabled (RELOAD=0) and BYTES have been transferred: - * - * - In Automatic End Mode (AUTOEND=1), a NACK and a STOP are - * automatically sent after the last received byte. - * - * Note: Automatic End Mode is not currently supported. - * - * - In Software End Mode (AUTOEND=0), a NACK is automatically sent after - * the last received byte, the TC event occurs and the SCL line is - * stretched low in order to allow software actions (STOP, RESTART). - * - * When RELOAD is enabled (RELOAD=1) and NBYTES bytes have been transferred - * a TCR event occurs and that handler simply updates NBYTES which causes - * RXNE events to continue until all bytes have been transferred. - */ - - else if ((priv->flags & (I2C_M_READ)) != 0 && (status & I2C_ISR_RXNE) != 0) - { - /* When read flag is set and the receive buffer is not empty - * (RXNE is set) then the driver can read from the data register. - */ - - stm32_i2c_traceevent(priv, I2CEVENT_READ, 0); - i2cinfo("RXNE: ENTER dcnt = %i msgc = %i status 0x%08" PRIx32 "\n", - priv->dcnt, priv->msgc, status); - - /* If more bytes in the current message */ - - if (priv->dcnt > 0) - { - stm32_i2c_traceevent(priv, I2CEVENT_RCVBYTE, priv->dcnt); - - /* No interrupts or context switches may occur in the following - * sequence. Otherwise, additional bytes may be received. - */ - -#ifdef CONFIG_I2C_POLLED - irqstate_t state = enter_critical_section(); -#endif - /* Receive a byte */ - - *priv->ptr = stm32_i2c_getreg(priv, STM32_I2C_RXDR_OFFSET); - - i2cinfo("RXNE: Read Data 0x%02x\n", *priv->ptr); - - /* Advance buffer to the next byte in the message */ - - priv->ptr++; - - /* Signal byte received */ - - priv->dcnt--; - -#ifdef CONFIG_I2C_POLLED - leave_critical_section(state); -#endif - } - else - { - /* Unsupported state */ - - stm32_i2c_traceevent(priv, I2CEVENT_READ_ERROR, 0); - status = stm32_i2c_getreg(priv, STM32_I2C_ISR_OFFSET); - i2cerr("ERROR: RXNE Unsupported state detected, dcnt=%i, " - "status 0x%08" PRIx32 "\n", - priv->dcnt, status); - - /* Set signals that will terminate ISR and wake waiting thread */ - - priv->status |= I2C_INT_BAD_STATE; - priv->dcnt = -1; - priv->msgc = 0; - } - - i2cinfo("RXNE: EXIT dcnt = %i msgc = %i status 0x%08" PRIx32 "\n", - priv->dcnt, priv->msgc, status); - } - - /* Transfer Complete (TC) State Handler - * - * This branch is only triggered when the TC interrupt occurs. This - * interrupt will only fire when: - * - * I2C_CR1->TCIE = 1 (Transfer Complete Interrupts Enabled) - * I2C_CR2->RELOAD = 0 (Reload Mode Disabled) - * I2C_CR2->AUTOEND = 0 (Autoend Mode Disabled, i.e. Software End Mode) - * - * This event indicates that the number of bytes initially defined - * in NBYTES, meaning, the number of bytes in the current message - * (priv->dcnt) has been successfully transmitted or received. - * - * When the TC interrupt occurs we have two choices to clear it and - * move on, regardless of the transfer direction: - * - * - if more messages follow, perform a repeated START if required - * and then fall through to transmit or receive the next message. - * - * - if no messages follow, perform a STOP and set flags needed to - * exit the ISR. - * - * The fact that the hardware must either RESTART or STOP when a TC - * event occurs explains why, when messages must be sent back to back - * (i.e. without a restart by specifying the I2C_M_NOSTART flag), - * RELOAD mode must be enabled and TCR event(s) must be generated - * instead. See the TCR handler for more. - */ - - else if ((status & I2C_ISR_TC) != 0) - { - i2cinfo("TC: ENTER dcnt = %i msgc = %i status 0x%08" PRIx32 "\n", - priv->dcnt, priv->msgc, status); - - /* Prior message has been sent successfully. Or there could have - * been an error that set msgc to 0; So test for that case as - * we do not want to decrement msgc less then zero nor move msgv - * past the last message. - */ - - if (priv->msgc > 0) - { - priv->msgc--; - } - - /* Are there additional messages remain to be transmitted / received? */ - - if (priv->msgc > 0) - { - i2cinfo("TC: RESTART: dcnt=%i, msgc=%i\n", - priv->dcnt, priv->msgc); - stm32_i2c_traceevent(priv, I2CEVENT_TC_NO_RESTART, priv->msgc); - - /* Issue a START condition. - * - * Note that the first thing sendstart does is update the - * private structure "current message" data (ptr, dcnt, flags) - * so they all reflect the next message in the list so we - * update msgv before we get there. - */ - - /* Advance to the next message in the list */ - - priv->msgv++; - - stm32_i2c_sendstart(priv); - } - else - { - /* Issue a STOP conditions. - * - * No additional messages to transmit / receive, so the - * transfer is indeed complete. Nothing else to do but - * issue a STOP and exit. - */ - - i2cinfo("TC: STOP: dcnt=%i msgc=%i\n", - priv->dcnt, priv->msgc); - stm32_i2c_traceevent(priv, I2CEVENT_STOP, priv->dcnt); - - stm32_i2c_sendstop(priv); - - /* Set signals that will terminate ISR and wake waiting thread */ - - priv->dcnt = -1; - priv->msgc = 0; - } - - i2cinfo("TC: EXIT dcnt = %i msgc = %i status 0x%08" PRIx32 "\n", - priv->dcnt, priv->msgc, status); - } - - /* Transfer Complete (Reload) State Handler - * - * This branch is only triggered when the TCR interrupt occurs. This - * interrupt will only fire when: - * - * I2C_CR1->TCIE = 1 (Transfer Complete Interrupts Enabled) - * I2C_CR2->RELOAD = 1 (Reload Mode Active) - * I2C_CR2->AUTOEND = 0 (Autoend Mode Disabled, i.e. Software End Mode) - * - * This is similar to the TC event except that TCR assumes that additional - * bytes are available to transfer. So despite what its name might imply - * the transfer really isn't complete. - * - * There are two reasons RELOAD would be enabled: - * - * 1) We're trying to send a message with a payload greater than 255 - * bytes. - * 2) We're trying to send messages back to back, regardless of their - * payload size, to avoid a RESTART (i.e. I2C_M_NOSTART flag is set). - * - * These conditions may be true simultaneously, as would be the case if - * we're sending multiple messages with payloads > 255 bytes. So we - * only advance to the next message if we arrive here and dcnt is 0, - * meaning, we're finished with the last message and ready to move to - * the next. - * - * This logic supports the transfer of bytes limited only by the size of - * the i2c_msg_s length variable. The SCL line will be stretched low - * until NBYTES is written with a non-zero value, allowing the transfer - * to continue. - * - * TODO: RESTARTs are required by the I2CSPEC if the next message transfer - * direction changes. Right now the NORESTART flag overrides this - * behavior. May have to introduce logic to issue sendstart, assuming it's - * legal with the hardware in the TCR state. - */ - - else if ((status & I2C_ISR_TCR) != 0) - { - i2cinfo("TCR: ENTER dcnt = %i msgc = %i status 0x%08" PRIx32 "\n", - priv->dcnt, priv->msgc, status); - - /* If no more bytes in the current message to transfer */ - - if (priv->dcnt == 0) - { - /* Prior message has been sent successfully */ - - priv->msgc--; - - /* Advance to the next message in the list */ - - priv->msgv++; - - /* Update current message data */ - - priv->ptr = priv->msgv->buffer; - priv->dcnt = priv->msgv->length; - priv->flags = priv->msgv->flags; - - /* If this is the last message, disable reload so the - * TC event fires next time. - */ - - if (priv->msgc == 0) - { - i2cinfo("TCR: DISABLE RELOAD: dcnt = %i msgc = %i\n", - priv->dcnt, priv->msgc); - - stm32_i2c_disable_reload(priv); - } - - /* Update NBYTES with length of current message */ - - i2cinfo("TCR: NEXT MSG dcnt = %i msgc = %i\n", - priv->dcnt, priv->msgc); - - stm32_i2c_set_bytes_to_transfer(priv, priv->dcnt); - } - else - { - /* More bytes in the current (greater than 255 byte payload - * length) message, so set NBYTES according to the bytes - * remaining in the message, up to a maximum each cycle of 255. - */ - - if (priv->dcnt > 255) - { - i2cinfo( - "TCR: ENABLE RELOAD: NBYTES = 255 dcnt = %i msgc = %i\n", - priv->dcnt, priv->msgc); - - /* More than 255 bytes to transfer so the RELOAD bit is - * set in order to generate a TCR event rather than a TC - * event when 255 bytes are successfully transferred. - * This forces us to return here to update NBYTES and - * continue until NBYTES is set to less than 255 bytes, - * at which point RELOAD will be disabled and a TC - * event will (eventually) follow to officially terminate - * the transfer. - */ - - stm32_i2c_enable_reload(priv); - - stm32_i2c_set_bytes_to_transfer(priv, 255); - } - else - { - /* Less than 255 bytes left to transfer, which means we'll - * complete the transfer of all bytes in the current message - * the next time around. - * - * This means we need to disable the RELOAD functionality so - * we receive a TC event next time which will allow us to - * either RESTART and continue sending the contents of the - * next message or send a STOP condition and exit the ISR. - */ - - i2cinfo("TCR: DISABLE RELOAD: NBYTES = dcnt = %i msgc = %i\n", - priv->dcnt, priv->msgc); - - stm32_i2c_set_bytes_to_transfer(priv, priv->dcnt); - - stm32_i2c_disable_reload(priv); - } - - i2cinfo("TCR: EXIT dcnt = %i msgc = %i status 0x%08" PRIx32 "\n", - priv->dcnt, priv->msgc, status); - } - } - - /* Empty call handler - * - * Case to handle an empty call to the ISR where it has nothing to - * do and should exit immediately. - */ - - else if (priv->dcnt == -1 && priv->msgc == 0) - { - status = stm32_i2c_getreg(priv, STM32_I2C_ISR_OFFSET); - i2cwarn("WARNING: EMPTY CALL: Stopping ISR: status 0x%08" PRIx32 "\n", - status); - stm32_i2c_traceevent(priv, I2CEVENT_ISR_EMPTY_CALL, 0); - } - - /* Error handler - * - * We get to this branch only if we can't handle the current state. - * - * This can happen in interrupt based operation on ARLO & BUSY. - * - * This will happen during polled operation when the device is not - * in one of the supported states when polled. - */ - - else - { -#ifdef CONFIG_I2C_POLLED - stm32_i2c_traceevent(priv, I2CEVENT_POLL_DEV_NOT_RDY, 0); -#else - /* Read rest of the state */ - - status = stm32_i2c_getreg(priv, STM32_I2C_ISR_OFFSET); - - i2cerr("ERROR: Invalid state detected, status 0x%08" PRIx32 "\n", - status); - - /* set condition to terminate ISR and wake waiting thread */ - - priv->status |= I2C_INT_BAD_STATE; - priv->dcnt = -1; - priv->msgc = 0; - stm32_i2c_traceevent(priv, I2CEVENT_STATE_ERROR, 0); -#endif - } - - /* --------------------- End of I2C protocol handling ------------------ */ - - /* Message Handling - * - * Transmission of the whole message chain has been completed. We have to - * terminate the ISR and wake up stm32_i2c_process() that is waiting for - * the ISR cycle to handle the sending/receiving of the messages. - */ - - if (priv->dcnt == -1 && priv->msgc == 0) - { - i2cinfo("MSG: Shutting down I2C ISR\n"); - - stm32_i2c_traceevent(priv, I2CEVENT_ISR_SHUTDOWN, 0); - - /* Clear pointer to message content to reflect we are done - * with the current transaction. - */ - - priv->msgv = NULL; - -#ifdef CONFIG_I2C_POLLED - priv->intstate = INTSTATE_DONE; -#else - - /* We will update private state to capture NACK which is used in - * combination with the astart flag to report the type of NACK received - * (address vs data) to the upper layers once we exit the ISR. - * - * Note: status is captured prior to clearing interrupts because - * the NACKF flag will naturally be cleared by that process. - */ - - status = stm32_i2c_getreg32(priv, STM32_I2C_ISR_OFFSET); - - /* Clear all interrupts */ - - stm32_i2c_modifyreg32(priv, STM32_I2C_ICR_OFFSET, - 0, I2C_ICR_CLEARMASK); - - /* Was a bad state detected in the processing? */ - - if (priv->status & I2C_INT_BAD_STATE) - { - /* SW reset device */ - - stm32_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, I2C_CR1_PE, 0); - } - - /* Update private status from above sans I2C_INT_BAD_STATE */ - - priv->status = status; - - /* If a thread is waiting then inform it transfer is complete */ - - if (priv->intstate == INTSTATE_WAITING) - { - nxsem_post(&priv->sem_isr); - priv->intstate = INTSTATE_DONE; - } -#endif - } - - status = stm32_i2c_getreg32(priv, STM32_I2C_ISR_OFFSET); - i2cinfo("EXIT: status = 0x%08" PRIx32 "\n", status); - - return OK; -} - -/**************************************************************************** - * Name: stm32_i2c_isr - * - * Description: - * Common I2C interrupt service routine - * - ****************************************************************************/ - -#ifndef CONFIG_I2C_POLLED -static int stm32_i2c_isr(int irq, void *context, void *arg) -{ - struct stm32_i2c_priv_s *priv = (struct stm32_i2c_priv_s *)arg; - - DEBUGASSERT(priv != NULL); - return stm32_i2c_isr_process(priv); -} -#endif - -/**************************************************************************** - * Name: stm32_i2c_init - * - * Description: - * Setup the I2C hardware, ready for operation with defaults - * - ****************************************************************************/ - -static int stm32_i2c_init(struct stm32_i2c_priv_s *priv) -{ - /* Power-up and configure GPIOs */ - - /* Enable power and reset the peripheral */ - - modifyreg32(STM32_RCC_APB1ENR, 0, priv->config->clk_bit); - modifyreg32(STM32_RCC_APB1RSTR, 0, priv->config->reset_bit); - modifyreg32(STM32_RCC_APB1RSTR, priv->config->reset_bit, 0); - - /* Configure pins */ - - if (stm32_configgpio(priv->config->scl_pin) < 0) - { - return ERROR; - } - - if (stm32_configgpio(priv->config->sda_pin) < 0) - { - stm32_unconfiggpio(priv->config->scl_pin); - return ERROR; - } - -#ifndef CONFIG_I2C_POLLED - /* Attach error and event interrupts to the ISRs */ - - irq_attach(priv->config->ev_irq, stm32_i2c_isr, priv); - irq_attach(priv->config->er_irq, stm32_i2c_isr, priv); - up_enable_irq(priv->config->ev_irq); - up_enable_irq(priv->config->er_irq); -#endif - - /* TODO: - * - Provide means to set peripheral clock source via RCC_CFGR3_I2CxSW - * - Set to HSI by default, make Kconfig option - */ - - /* Force a frequency update */ - - priv->frequency = 0; - stm32_i2c_setclock(priv, 100000); - - return OK; -} - -/**************************************************************************** - * Name: stm32_i2c_deinit - * - * Description: - * Shutdown the I2C hardware - * - ****************************************************************************/ - -static int stm32_i2c_deinit(struct stm32_i2c_priv_s *priv) -{ - /* Disable I2C */ - - stm32_i2c_putreg32(priv, STM32_I2C_CR1_OFFSET, 0); - - /* Unconfigure GPIO pins */ - - stm32_unconfiggpio(priv->config->scl_pin); - stm32_unconfiggpio(priv->config->sda_pin); - -#ifndef CONFIG_I2C_POLLED - - /* Disable and detach interrupts */ - - up_disable_irq(priv->config->ev_irq); - up_disable_irq(priv->config->er_irq); - irq_detach(priv->config->ev_irq); - irq_detach(priv->config->er_irq); -#endif - - /* Disable clocking */ - - modifyreg32(STM32_RCC_APB1ENR, priv->config->clk_bit, 0); - - return OK; -} - -/**************************************************************************** - * Name: stm32_i2c_process - * - * Description: - * Common I2C transfer logic - * - * Initiates a master mode transaction on the I2C bus to transfer the - * provided messages to and from the slave devices. - * - ****************************************************************************/ - -static int stm32_i2c_process(struct i2c_master_s *dev, - struct i2c_msg_s *msgs, int count) -{ - struct stm32_i2c_inst_s *inst = (struct stm32_i2c_inst_s *)dev; - struct stm32_i2c_priv_s *priv = inst->priv; - uint32_t status = 0; - uint32_t cr1; - uint32_t cr2; - int errval = 0; - int waitrc = 0; - - DEBUGASSERT(count > 0); - - /* Wait for any STOP in progress */ - - stm32_i2c_sem_waitstop(priv); - - /* Clear any pending error interrupts */ - - stm32_i2c_clearinterrupts(priv); - - /* Old transfers are done */ - - priv->msgv = msgs; - priv->msgc = count; - - /* Reset I2C trace logic */ - - stm32_i2c_tracereset(priv); - - /* Set I2C clock frequency toggles I2C_CR1_PE performing a SW reset! */ - - stm32_i2c_setclock(priv, msgs->frequency); - - /* Trigger start condition, then the process moves into the ISR. I2C - * interrupts will be enabled within stm32_i2c_waitdone(). - */ - - priv->status = 0; - -#ifndef CONFIG_I2C_POLLED - /* Enable transmit and receive interrupts here so when we send the start - * condition below the ISR will fire if the data was sent and some - * response from the slave received. All other interrupts relevant to - * our needs are enabled in stm32_i2c_sem_waitdone() below. - */ - - stm32_i2c_enableinterrupts(priv); -#endif - - /* Trigger START condition generation, which also sends the slave address - * with read/write flag and the data in the first message - */ - - stm32_i2c_sendstart(priv); - - /* Wait for the ISR to tell us that the transfer is complete by attempting - * to grab the semaphore that is initially locked by the ISR. If the ISR - * does not release the lock so we can obtain it here prior to the end of - * the timeout period waitdone returns error and we report a timeout. - */ - - waitrc = stm32_i2c_sem_waitdone(priv); - - cr1 = stm32_i2c_getreg32(priv, STM32_I2C_CR1_OFFSET); - cr2 = stm32_i2c_getreg32(priv, STM32_I2C_CR2_OFFSET); -#if !defined(CONFIG_DEBUG_I2C) - UNUSED(cr1); - UNUSED(cr2); -#endif - - /* Status after a normal / good exit is usually 0x00000001, meaning the TXE - * bit is set. That occurs as a result of the I2C_TXDR register being - * empty, and it naturally will be after the last byte is transmitted. - * This bit is cleared when we attempt communications again and re-enable - * the peripheral. The priv->status field can hold additional information - * like a NACK, so we reset the status field to include that information. - */ - - status = stm32_i2c_getstatus(priv); - - /* The priv->status field can hold additional information like a NACK - * event so we include that information. - */ - - status = priv->status & 0xffffffff; - - if (waitrc < 0) - { - /* Connection timed out */ - - errval = ETIMEDOUT; - i2cerr("ERROR: Waitdone timed out CR1: 0x%08" PRIx32 - " CR2: 0x%08" PRIx32 " status: 0x%08" PRIx32 "\n", - cr1, cr2, status); - } - else - { - i2cinfo("Waitdone success: CR1: 0x%08" PRIx32 - " CR2: 0x%08" PRIx32 " status: 0x%08" PRIx32 "\n", - cr1, cr2, status); - } - - UNUSED(cr1); - UNUSED(cr2); - - i2cinfo("priv->status: 0x%08" PRIx32 "\n", priv->status); - - /* Check for error status conditions */ - - if ((status & (I2C_INT_BERR | - I2C_INT_ARLO | - I2C_INT_OVR | - I2C_INT_PECERR | - I2C_INT_TIMEOUT | - I2C_INT_NACK)) != 0) - - { - /* one or more errors in the mask are present */ - - if (status & I2C_INT_BERR) - { - /* Bus Error, ignore it because of errata (revision A,Z) */ - - i2cerr("ERROR: I2C Bus Error\n"); - - /* errval = EIO; */ - } - else if (status & I2C_INT_ARLO) - { - /* Arbitration Lost (master mode) */ - - i2cerr("ERROR: I2C Arbitration Lost\n"); - errval = EAGAIN; - } - - else if (status & I2C_INT_OVR) - { - /* Overrun/Underrun */ - - i2cerr("ERROR: I2C Overrun/Underrun\n"); - errval = EIO; - } - else if (status & I2C_INT_PECERR) - { - /* PEC Error in reception (SMBus Only) */ - - i2cerr("ERROR: I2C PEC Error\n"); - errval = EPROTO; - } - else if (status & I2C_INT_TIMEOUT) - { - /* Timeout or Tlow Error (SMBus Only) */ - - i2cerr("ERROR: I2C Timeout / Tlow Error\n"); - errval = ETIME; - } - else if (status & I2C_INT_NACK) - { - /* NACK Received, flag as "communication error on send" */ - - if (priv->astart == TRUE) - { - i2cwarn("WARNING: I2C Address NACK\n"); - errval = EADDRNOTAVAIL; - } - else - { - i2cwarn("WARNING: I2C Data NACK\n"); - errval = ECOMM; - } - } - else - { - /* Unrecognized error */ - - i2cerr("ERROR: I2C Unrecognized Error"); - errval = EINTR; - } - } - - /* This is not an error, but should not happen. The BUSY signal can be - * present if devices on the bus are in an odd state and need to be reset. - * NOTE: We will only see this busy indication if stm32_i2c_sem_waitdone() - * fails above; Otherwise it is cleared. - */ - - else if ((status & I2C_ISR_BUSY) != 0) - { - /* I2C Bus Busy - * - * This is a status condition rather than an error. - * - * We will only see this busy indication if stm32_i2c_sem_waitdone() - * fails above; Otherwise it is cleared by the hardware when the ISR - * wraps up the transfer with a STOP condition. - */ - - clock_t start = clock_systime_ticks(); - clock_t timeout = USEC2TICK(USEC_PER_SEC / priv->frequency) + 1; - - status = stm32_i2c_getstatus(priv); - - while (status & I2C_ISR_BUSY) - { - if ((clock_systime_ticks() - start) > timeout) - { - i2cerr("ERROR: I2C Bus busy"); - errval = EBUSY; - break; - } - - status = stm32_i2c_getstatus(priv); - } - } - - /* Dump the trace result */ - - stm32_i2c_tracedump(priv); - nxmutex_unlock(&priv->lock); - - return -errval; -} - -/**************************************************************************** - * Name: stm32_i2c_transfer - * - * Description: - * Generic I2C transfer function - * - ****************************************************************************/ - -static int stm32_i2c_transfer(struct i2c_master_s *dev, - struct i2c_msg_s *msgs, int count) -{ - struct stm32_i2c_priv_s *priv; - int ret; - - DEBUGASSERT(dev); - - /* Get I2C private structure */ - - priv = ((struct stm32_i2c_inst_s *)dev)->priv; - - /* Ensure that address or flags don't change meanwhile */ - - ret = nxmutex_lock(&priv->lock); - if (ret >= 0) - { - ret = stm32_i2c_process(dev, msgs, count); - } - - return ret; -} - -/**************************************************************************** - * Name: stm32_i2c_reset - * - * Description: - * Reset an I2C bus - * - ****************************************************************************/ - -#ifdef CONFIG_I2C_RESET -static int stm32_i2c_reset(struct i2c_master_s *dev) -{ - struct stm32_i2c_priv_s *priv; - unsigned int clock_count; - unsigned int stretch_count; - uint32_t scl_gpio; - uint32_t sda_gpio; - uint32_t frequency; - int ret; - - DEBUGASSERT(dev); - - /* Get I2C private structure */ - - priv = ((struct stm32_i2c_inst_s *)dev)->priv; - - /* Our caller must own a ref */ - - DEBUGASSERT(priv->refs > 0); - - /* Lock out other clients */ - - ret = nxmutex_lock(&priv->lock); - if (ret < 0) - { - return ret; - } - - ret = -EIO; - - /* Save the current frequency */ - - frequency = priv->frequency; - - /* De-init the port */ - - stm32_i2c_deinit(priv); - - /* Use GPIO configuration to un-wedge the bus */ - - scl_gpio = MKI2C_OUTPUT(priv->config->scl_pin); - sda_gpio = MKI2C_OUTPUT(priv->config->sda_pin); - - stm32_configgpio(sda_gpio); - stm32_configgpio(scl_gpio); - - /* Let SDA go high */ - - stm32_gpiowrite(sda_gpio, 1); - - /* Clock the bus until any slaves currently driving it let it go. */ - - clock_count = 0; - while (!stm32_gpioread(sda_gpio)) - { - /* Give up if we have tried too hard */ - - if (clock_count++ > 10) - { - goto out; - } - - /* Sniff to make sure that clock stretching has finished. - * - * If the bus never relaxes, the reset has failed. - */ - - stretch_count = 0; - while (!stm32_gpioread(scl_gpio)) - { - /* Give up if we have tried too hard */ - - if (stretch_count++ > 10) - { - goto out; - } - - up_udelay(10); - } - - /* Drive SCL low */ - - stm32_gpiowrite(scl_gpio, 0); - up_udelay(10); - - /* Drive SCL high again */ - - stm32_gpiowrite(scl_gpio, 1); - up_udelay(10); - } - - /* Generate a start followed by a stop to reset slave - * state machines. - */ - - stm32_gpiowrite(sda_gpio, 0); - up_udelay(10); - stm32_gpiowrite(scl_gpio, 0); - up_udelay(10); - stm32_gpiowrite(scl_gpio, 1); - up_udelay(10); - stm32_gpiowrite(sda_gpio, 1); - up_udelay(10); - - /* Revert the GPIO configuration. */ - - stm32_unconfiggpio(sda_gpio); - stm32_unconfiggpio(scl_gpio); - - /* Re-init the port */ - - stm32_i2c_init(priv); - - /* Restore the frequency */ - - stm32_i2c_setclock(priv, frequency); - ret = OK; - -out: - - /* Release the port for reuse by other clients */ - - nxmutex_unlock(&priv->lock); - return ret; -} -#endif /* CONFIG_I2C_RESET */ - -/**************************************************************************** - * Name: stm32_i2c_pm_prepare - * - * Description: - * Request the driver to prepare for a new power state. This is a - * warning that the system is about to enter into a new power state. The - * driver should begin whatever operations that may be required to enter - * power state. The driver may abort the state change mode by returning - * a non-zero value from the callback function. - * - * Input Parameters: - * cb - Returned to the driver. The driver version of the callback - * structure may include additional, driver-specific state - * data at the end of the structure. - * domain - Identifies the activity domain of the state change - * pmstate - Identifies the new PM state - * - * Returned Value: - * 0 (OK) means the event was successfully processed and that the driver - * is prepared for the PM state change. Non-zero means that the driver - * is not prepared to perform the tasks needed achieve this power setting - * and will cause the state change to be aborted. NOTE: The prepare - * method will also be recalled when reverting from lower back to higher - * power consumption modes (say because another driver refused a lower - * power state change). Drivers are not permitted to return non-zero - * values when reverting back to higher power consumption modes! - * - ****************************************************************************/ - -#ifdef CONFIG_PM -static int stm32_i2c_pm_prepare(struct pm_callback_s *cb, int domain, - enum pm_state_e pmstate) -{ - struct stm32_i2c_priv_s *priv = - (struct stm32_i2c_priv_s *)((char *)cb - - offsetof(struct stm32_i2c_priv_s, pm_cb)); - - /* Logic to prepare for a reduced power state goes here. */ - - switch (pmstate) - { - case PM_NORMAL: - case PM_IDLE: - break; - - case PM_STANDBY: - case PM_SLEEP: - - /* Check if exclusive lock for I2C bus is held. */ - - if (nxmutex_is_locked(&priv->lock)) - { - /* Exclusive lock is held, do not allow entry to deeper PM - * states. - */ - - return -EBUSY; - } - - break; - - default: - - /* Should not get here */ - - break; - } - - return OK; -} -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_i2cbus_initialize - * - * Description: - * Initialize one I2C bus - * - ****************************************************************************/ - -struct i2c_master_s *stm32_i2cbus_initialize(int port) -{ - struct stm32_i2c_priv_s *priv = NULL; /* private data of device with multiple instances */ - struct stm32_i2c_inst_s *inst = NULL; /* device, single instance */ - - /* Get I2C private structure */ - - switch (port) - { -#ifdef CONFIG_STM32_I2C1 - case 1: - priv = (struct stm32_i2c_priv_s *)&stm32_i2c1_priv; - break; -#endif -#ifdef CONFIG_STM32_I2C2 - case 2: - priv = (struct stm32_i2c_priv_s *)&stm32_i2c2_priv; - break; -#endif -#ifdef CONFIG_STM32_I2C3 - case 3: - priv = (struct stm32_i2c_priv_s *)&stm32_i2c3_priv; - break; -#endif -#ifdef CONFIG_STM32_I2C4 - case 4: - priv = (struct stm32_i2c_priv_s *)&stm32_i2c4_priv; - break; -#endif - default: - return NULL; - } - - /* Allocate instance */ - - if (!(inst = kmm_malloc(sizeof(struct stm32_i2c_inst_s)))) - { - return NULL; - } - - /* Initialize instance */ - - inst->ops = &stm32_i2c_ops; - inst->priv = priv; - - /* Init private data for the first time, increment refs count, - * power-up hardware and configure GPIOs. - */ - - nxmutex_lock(&priv->lock); - if (priv->refs++ == 0) - { - stm32_i2c_init(priv); - -#ifdef CONFIG_PM - /* Register to receive power management callbacks */ - - DEBUGVERIFY(pm_register(&priv->pm_cb)); -#endif - } - - nxmutex_unlock(&priv->lock); - return (struct i2c_master_s *)inst; -} - -/**************************************************************************** - * Name: stm32_i2cbus_uninitialize - * - * Description: - * Uninitialize an I2C bus - * - ****************************************************************************/ - -int stm32_i2cbus_uninitialize(struct i2c_master_s *dev) -{ - struct stm32_i2c_priv_s *priv; - - DEBUGASSERT(dev); - priv = ((struct stm32_i2c_inst_s *)dev)->priv; - - /* Decrement refs and check for underflow */ - - if (priv->refs == 0) - { - return ERROR; - } - - nxmutex_lock(&priv->lock); - if (--priv->refs) - { - nxmutex_unlock(&priv->lock); - kmm_free(dev); - return OK; - } - -#ifdef CONFIG_PM - /* Unregister power management callbacks */ - - pm_unregister(&priv->pm_cb); -#endif - - /* Disable power and other HW resource (GPIO's) */ - - stm32_i2c_deinit(priv); - nxmutex_unlock(&priv->lock); - - kmm_free(dev); - return OK; -} - -#endif /* CONFIG_STM32_I2C1 || CONFIG_STM32_I2C2 || \ - * CONFIG_STM32_I2C3 || CONFIG_STM32_I2C4 */ diff --git a/arch/arm/src/stm32/stm32_i2cslave_v2.c b/arch/arm/src/stm32/stm32_i2cslave_v2.c deleted file mode 100644 index bbf86c2e49d68..0000000000000 --- a/arch/arm/src/stm32/stm32_i2cslave_v2.c +++ /dev/null @@ -1,793 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_i2cslave_v2.c - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - * TODO - * - DMA - * - SMBus adaptation - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include - -#include - -#include "arm_internal.h" -#include "hardware/stm32_pinmap.h" -#include "hardware/stm32_i2c_v2.h" -#include "stm32_gpio.h" -#include "stm32_rcc.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#define I2C_CR1_ALLINTS (I2C_CR1_RXIE | I2C_CR1_TXIE | I2C_CR1_ADDRIE | \ - I2C_CR1_STOPIE) - -#ifdef CONFIG_STM32_I2C_SLAVE_USEWQ -# ifdef CONFIG_SCHED_HPWORK -# define I2CSWORK HPWORK -# endif - -# ifndef I2CSWORK -# ifdef CONFIG_SCHED_LPWORK -# define I2CSWORK LPWORK -# endif -# endif - -# ifndef I2CSWORK -# error "For correct operation, you should define LPWORK or HPWORK." -# endif -#endif - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -struct stm32_i2cslave_s -{ - const struct i2c_slaveops_s *ops; - int refs; - mutex_t lock; - uint32_t frequency; - uint32_t base; - uint32_t clk_bit; - uint32_t reset_bit; - uint32_t ev_irq; - uint32_t scl_pin; - uint32_t sda_pin; - const uint8_t *tx_buffer; - uint8_t *rx_buffer; - int rx_buflen; - int rx_curptr; - int tx_buflen; - int tx_curptr; - int rx_received; - i2c_slave_callback_t *callback; - void *callback_arg; - bool read; -#ifdef CONFIG_STM32_I2C_SLAVE_USEWQ - struct work_s irqwork; /* For deferring interrupt work to the wq */ -#endif -}; - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -static int stm32_i2c_setup(struct i2c_slave_s *dev); -static int stm32_i2c_shutdown(struct i2c_slave_s *dev); -static int stm32_i2c_setownaddress(struct i2c_slave_s *dev, int addr, - int nbits); -static int stm32_i2c_write(struct i2c_slave_s *dev, const uint8_t *buffer, - int buflen); -static int stm32_i2c_read(struct i2c_slave_s *dev, uint8_t *buffer, - int buflen); -static int stm32_i2c_registercallback(struct i2c_slave_s *dev, - i2c_slave_callback_t *callback, - void *arg); -static int stm32_i2c_init(struct stm32_i2cslave_s *priv); -static int stm32_i2c_deinit(struct stm32_i2cslave_s *priv); -static int stm32_i2c_isr(int irq, void *context, void *arg); -static int stm32_i2c_isr_impl(struct stm32_i2cslave_s *priv); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -static const struct i2c_slaveops_s stm32_i2cslave_ops = -{ - .setownaddress = stm32_i2c_setownaddress, - .write = stm32_i2c_write, - .read = stm32_i2c_read, - .registercallback = stm32_i2c_registercallback, - .setup = stm32_i2c_setup, - .shutdown = stm32_i2c_shutdown -}; - -#ifdef CONFIG_STM32_I2C1_SLAVE -static struct stm32_i2cslave_s stm32_i2c1_priv = -{ - .ops = &stm32_i2cslave_ops, - .refs = 0, - .lock = NXMUTEX_INITIALIZER, - .frequency = 0, - .base = STM32_I2C1_BASE, - .clk_bit = RCC_APB1ENR_I2C1EN, - .reset_bit = RCC_APB1RSTR_I2C1RST, - .ev_irq = STM32_IRQ_I2C1EV, - .scl_pin = GPIO_I2C1_SCL, - .sda_pin = GPIO_I2C1_SDA, - .tx_buffer = NULL, - .rx_buffer = NULL, - .rx_buflen = 0, - .rx_curptr = 0, - .tx_curptr = 0, -}; -#endif - -#ifdef CONFIG_STM32_I2C2_SLAVE -static struct stm32_i2cslave_s stm32_i2c2_priv = -{ - .ops = &stm32_i2cslave_ops, - .refs = 0, - .lock = NXMUTEX_INITIALIZER, - .frequency = 0, - .base = STM32_I2C2_BASE, - .clk_bit = RCC_APB1ENR_I2C2EN, - .reset_bit = RCC_APB1RSTR_I2C2RST, - .ev_irq = STM32_IRQ_I2C2EV, - .scl_pin = GPIO_I2C2_SCL, - .sda_pin = GPIO_I2C2_SDA, - .tx_buffer = NULL, - .rx_buffer = NULL, - .rx_buflen = 0, - .rx_curptr = 0, - .tx_curptr = 0, -}; -#endif - -#ifdef CONFIG_STM32_I2C3_SLAVE -static struct stm32_i2cslave_s stm32_i2c3_priv = -{ - .ops = &stm32_i2cslave_ops, - .refs = 0, - .lock = NXMUTEX_INITIALIZER, - .frequency = 0, - .base = STM32_I2C3_BASE, - .clk_bit = RCC_APB1ENR_I2C3EN, - .reset_bit = RCC_APB1RSTR_I2C3RST, - .ev_irq = STM32_IRQ_I2C3EV, - .scl_pin = GPIO_I2C3_SCL, - .sda_pin = GPIO_I2C3_SDA, - .tx_buffer = NULL, - .rx_buffer = NULL, - .rx_buflen = 0, - .rx_curptr = 0, - .tx_curptr = 0, -}; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_i2c_getreg - * - * Description: - * Get a 16-bit register value by offset - * - ****************************************************************************/ - -static inline uint16_t stm32_i2c_getreg(struct stm32_i2cslave_s *priv, - uint8_t offset) -{ - return getreg16(priv->base + offset); -} - -/**************************************************************************** - * Name: stm32_i2c_getreg32 - * - * Description: - * Get a 32-bit register value by offset - * - ****************************************************************************/ - -static inline uint32_t stm32_i2c_getreg32(struct stm32_i2cslave_s *priv, - uint8_t offset) -{ - return getreg32(priv->base + offset); -} - -/**************************************************************************** - * Name: stm32_i2c_putreg - * - * Description: - * Put a 16-bit register value by offset - * - ****************************************************************************/ - -static inline void stm32_i2c_putreg(struct stm32_i2cslave_s *priv, - uint8_t offset, uint16_t value) -{ - putreg16(value, priv->base + offset); -} - -/**************************************************************************** - * Name: stm32_i2c_putreg32 - * - * Description: - * Put a 32-bit register value by offset - * - ****************************************************************************/ - -static inline void stm32_i2c_putreg32(struct stm32_i2cslave_s *priv, - uint8_t offset, uint32_t value) -{ - putreg32(value, priv->base + offset); -} - -/**************************************************************************** - * Name: stm32_i2c_isr - * - * Description: - * Common I2C interrupt service routine - * - ****************************************************************************/ - -static int stm32_i2c_isr(int irq, void *context, void *arg) -{ - struct stm32_i2cslave_s *priv = (struct stm32_i2cslave_s *)arg; - DEBUGASSERT(priv != NULL); - return stm32_i2c_isr_impl(priv); -} - -/**************************************************************************** - * Name: stm32_i2c_rxdone_work - * - * Description: - * A routine for delegating frame reception information - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_I2C_SLAVE_USEWQ -static void stm32_i2c_rxdone_work(void *arg) -{ - struct stm32_i2cslave_s *priv = (struct stm32_i2cslave_s *)arg; - priv->callback(priv->callback_arg, I2CS_RX_COMPLETE, - priv->rx_curptr); -} -#endif - -/**************************************************************************** - * Name: stm32_i2c_rxdone_work - * - * Description: - * A routine for delegating tx frame information - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_I2C_SLAVE_USEWQ -static void stm32_i2c_txdone_work(void *arg) -{ - struct stm32_i2cslave_s *priv = (struct stm32_i2cslave_s *)arg; - priv->callback(priv->callback_arg, I2CS_TX_COMPLETE, - priv->tx_curptr); -} -#endif - -/**************************************************************************** - * Name: stm32_i2c_isr_impl - * - * Description: - * Interrupt handler - * - ****************************************************************************/ - -static int stm32_i2c_isr_impl(struct stm32_i2cslave_s *priv) -{ - volatile uint32_t isr; - volatile uint8_t rx; - volatile uint8_t tx; - - /* Get the status register first. */ - - isr = stm32_i2c_getreg32(priv, STM32_I2C_ISR_OFFSET); - - /* Was the TX completed? */ - - if ((isr & I2C_ISR_TXIS) != 0) - { - /* Check, if anything must be sent */ - - if (priv->tx_curptr < priv->tx_buflen - 1) - { - /* Yes... */ - - priv->tx_curptr++; - tx = priv->tx_buffer[priv->tx_curptr]; - } - else if (priv->tx_curptr == priv->tx_buflen - 1) - { - tx = CONFIG_STM32_I2C_SLAVE_DEFAULT_TX; - if (priv->callback) - { -#ifdef CONFIG_STM32_I2C_SLAVE_USEWQ - work_queue(I2CSWORK, &priv->irqwork, - stm32_i2c_txdone_work, priv, 0); -#else - priv->callback(priv->callback_arg, I2CS_TX_COMPLETE, - priv->tx_curptr); -#endif - } - } - else - { - /* No... Send the default value. */ - - tx = CONFIG_STM32_I2C_SLAVE_DEFAULT_TX; - } - - stm32_i2c_putreg(priv, STM32_I2C_TXDR_OFFSET, tx); - } - - /* Was a byte received? */ - - if ((isr & I2C_ISR_RXNE) != 0) - { - /* Write it if not overflowed. RXDR must be read to clear int. */ - - rx = stm32_i2c_getreg(priv, STM32_I2C_RXDR_OFFSET); - if (priv->rx_curptr < priv->rx_buflen) - { - priv->rx_buffer[priv->rx_curptr++] = rx; - } - } - - /* Was the stop condition detected? */ - - if ((isr & I2C_INT_STOP) != 0) - { - /* Clear the interrupt. */ - - stm32_i2c_putreg(priv, STM32_I2C_ICR_OFFSET, I2C_INT_STOP); - - /* If RX was present, notify the upper driver. */ - - if (priv->read) - { - if (priv->callback) - { -#ifdef CONFIG_STM32_I2C_SLAVE_USEWQ - work_queue(I2CSWORK, &priv->irqwork, - stm32_i2c_rxdone_work, priv, 0); -#else - priv->callback(priv->callback_arg, I2CS_RX_COMPLETE, - priv->rx_curptr); - priv->rx_curptr = 0; -#endif - } - } -#ifdef CONFIG_STM32_I2C_SLAVE_RETRANSFER - else - { - priv->tx_curptr = 0; - } -#endif - } - - /* Was an address matched? */ - - if ((isr & I2C_INT_ADDR) != 0) - { - /* Clear the address match flag. */ - - stm32_i2c_putreg(priv, STM32_I2C_ICR_OFFSET, I2C_INT_ADDR); - - /* Repeated Start */ - - if (priv->rx_curptr > 0 && priv->callback) - { -#ifdef CONFIG_STM32_I2C_SLAVE_USEWQ - work_queue(I2CSWORK, &priv->irqwork, - stm32_i2c_rxdone_work, priv, 0); -#else - priv->callback(priv->callback_arg, I2CS_RX_COMPLETE, - priv->rx_curptr); -#endif - } - - /* Check whether RX or TX should be done. */ - - if ((isr & I2C_ISR_DIR) != 0) - { - /* Write transfer. Flush the TX buffer by writing ISR_TXE. - * Then send any remaining data. Or send the default TX byte. - */ - - stm32_i2c_putreg32(priv, STM32_I2C_ISR_OFFSET, I2C_ISR_TXE); - - if (priv->tx_curptr < priv->tx_buflen) - { - tx = priv->tx_buffer[priv->tx_curptr]; - } - else - { - /* Nothing to be sent. */ - - tx = CONFIG_STM32_I2C_SLAVE_DEFAULT_TX; - } - - stm32_i2c_putreg(priv, STM32_I2C_TXDR_OFFSET, tx); - priv->read = false; - } - else - { - /* Initialize the reading. */ - - priv->read = true; - priv->rx_curptr = 0; - } - } - - return OK; -} - -/**************************************************************************** - * Name: stm32_i2c_setownaddress - * - * Description: - * Sets up the address of the I2C Slave - * - ****************************************************************************/ - -static int stm32_i2c_setownaddress(struct i2c_slave_s *dev, int addr, - int nbits) -{ - struct stm32_i2cslave_s *priv = (struct stm32_i2cslave_s *)dev; - uint16_t oar1; - uint32_t cr1; - - i2cinfo("SETOWNADDR %d\n", addr); - - /* STM32 supports up to 2 addresses the slave can respond to. - * However, NuttX supports the setting of only one address. - * Use only the first "OWN ADDRESS" (I2C_OAR1) - * Before this, reset the peripheral by disabling it. - * If the peripheral is launched for the first time, this does nothing. - */ - - cr1 = stm32_i2c_getreg32(priv, STM32_I2C_CR1_OFFSET); - stm32_i2c_putreg32(priv, STM32_I2C_CR1_OFFSET, - cr1 & ~(I2C_CR1_ALLINTS | I2C_CR1_PE)); - - /* Clear I2C_OAR1_OA1EN, then configure I2C_OAR1_OA1[9:0]. - * Afterwards, set I2C_OAR1_{OA1MODE, OA1EN}. - * According to i2c_slave_open in i2c_slave_driver.c, SETOWNADDRESS comes - * after SETUP. Therefore, enable the peripheral and RX and TX interrupts - * here. - * - * Attention: If a 10 bit address is used, all 10 bits are used. - * However, bits 7:1 are used (instead of 6:0) in the 7 bit mode. - * Therefore, the address must be shifted. - */ - - if (nbits == 10) - { - oar1 = ((uint16_t) addr) & 0x03ff; - oar1 |= I2C_OAR1_OA1MODE; - } - else if (nbits == 7) - { - oar1 = ((uint16_t) addr << 1) & 0x00fe; - } - else - { - /* Wrong nbits. */ - - return ERROR; - } - - /* Clear OA1EN (whole register can be cleared) */ - - stm32_i2c_putreg32(priv, STM32_I2C_OAR1_OFFSET, 0); - stm32_i2c_putreg32(priv, STM32_I2C_OAR1_OFFSET, oar1); - - /* Enable the address here. */ - - oar1 |= I2C_OAR1_OA1EN; - stm32_i2c_putreg32(priv, STM32_I2C_OAR1_OFFSET, oar1); - - /* Enable the peripheral and interrupts */ - - priv->read = false; - stm32_i2c_putreg32(priv, STM32_I2C_CR1_OFFSET, - I2C_CR1_ALLINTS | I2C_CR1_PE); - - return OK; -} - -/**************************************************************************** - * Name: stm32_i2c_setup - * - * Description: - * Sets up the STM32 I2C peripheral - * - ****************************************************************************/ - -static int stm32_i2c_setup(struct i2c_slave_s *dev) -{ - struct stm32_i2cslave_s *priv = (struct stm32_i2cslave_s *)dev; - DEBUGASSERT(dev); - - /* Enable the interrupts here. This function is called when the device - * is opened for the first time. - */ - - irq_attach(priv->ev_irq, stm32_i2c_isr, priv); - up_enable_irq(priv->ev_irq); - return OK; -} - -/**************************************************************************** - * Name: stm32_i2c_shutdown - * - * Description: - * Shutdown the STM32 I2C peripheral - * - ****************************************************************************/ - -static int stm32_i2c_shutdown(struct i2c_slave_s *dev) -{ - struct stm32_i2cslave_s *priv = (struct stm32_i2cslave_s *)dev; - uint32_t cr1; - - DEBUGASSERT(dev); - - /* Disable I2C_CR1_PE. Disabling the I2C should have no effect - * on configuration bits, and SCL and SDA lines are released. - * Disable TX and TX interrupts. - */ - - cr1 = stm32_i2c_getreg32(priv, STM32_I2C_CR1_OFFSET); - stm32_i2c_putreg32(priv, STM32_I2C_CR1_OFFSET, - cr1 & ~(I2C_CR1_ALLINTS | I2C_CR1_PE)); - - /* Disable the interrupts here. This function is called when the device - * is closed by the last task. - */ - - up_disable_irq(priv->ev_irq); - irq_detach(priv->ev_irq); - return OK; -} - -/**************************************************************************** - * Name: stm32_i2c_write - * - * Description: - * Receive a pointer to a buffer where to write data to - * - ****************************************************************************/ - -static int stm32_i2c_write(struct i2c_slave_s *dev, const uint8_t *buffer, - int buflen) -{ - struct stm32_i2cslave_s *priv = (struct stm32_i2cslave_s *)dev; - int flags; - - DEBUGASSERT(dev); - flags = enter_critical_section(); - - /* Initialize the TX buffer. */ - - priv->tx_buffer = buffer; - priv->tx_buflen = buflen; - priv->tx_curptr = 0; - - leave_critical_section(flags); - return OK; -} - -/**************************************************************************** - * Name: stm32_i2c_read - * - * Description: - * Receive a pointer to a buffer where to read data to - * - ****************************************************************************/ - -static int stm32_i2c_read(struct i2c_slave_s *dev, uint8_t *buffer, - int buflen) -{ - struct stm32_i2cslave_s *priv = (struct stm32_i2cslave_s *)dev; - int flags; - - DEBUGASSERT(dev); - flags = enter_critical_section(); - - /* Initialize the RX buffer. */ - - priv->rx_buffer = buffer; - priv->rx_buflen = buflen; - - leave_critical_section(flags); - return OK; -} - -/**************************************************************************** - * Name: stm32_i2c_registercallback - * - * Description: - * Register a function which notifies the upperhalf driver - * - ****************************************************************************/ - -static int stm32_i2c_registercallback(struct i2c_slave_s *dev, - i2c_slave_callback_t *callback, - void *arg) -{ - struct stm32_i2cslave_s *priv = (struct stm32_i2cslave_s *)dev; - int flags; - - DEBUGASSERT(dev); - flags = enter_critical_section(); - - /* Initialize the pointer to a callback. */ - - priv->callback = callback; - priv->callback_arg = arg; - - leave_critical_section(flags); - return OK; -} - -/**************************************************************************** - * Name: stm32_i2c_init - * - * Description: - * Initialize STM32 I2C peripheral - clocks and pins - * - ****************************************************************************/ - -static int stm32_i2c_init(struct stm32_i2cslave_s *priv) -{ - DEBUGASSERT(priv); - - modifyreg32(STM32_RCC_APB1ENR, 0, priv->clk_bit); - modifyreg32(STM32_RCC_APB1RSTR, 0, priv->reset_bit); - modifyreg32(STM32_RCC_APB1RSTR, priv->reset_bit, 0); - - if (stm32_configgpio(priv->scl_pin) < 0) - { - return ERROR; - } - - if (stm32_configgpio(priv->sda_pin) < 0) - { - return ERROR; - } - - return OK; -} - -/**************************************************************************** - * Name: stm32_i2c_deinit - * - * Description: - * Deinitialize STM32 I2C peripheral - clocks and pins - * - ****************************************************************************/ - -static int stm32_i2c_deinit(struct stm32_i2cslave_s *priv) -{ - DEBUGASSERT(priv); - - modifyreg32(STM32_RCC_APB1ENR, priv->clk_bit, 0); - modifyreg32(STM32_RCC_APB1RSTR, 0, priv->reset_bit); - stm32_unconfiggpio(priv->scl_pin); - stm32_configgpio(priv->sda_pin); - - return OK; -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_i2cbus_slaveinitialize - * - * Description: - * Initialize on I2C bus as a slave and get pointer to i2c_slave_s struct - * - ****************************************************************************/ - -struct i2c_slave_s *stm32_i2cbus_slaveinitialize(int port) -{ - int ret; - struct stm32_i2cslave_s *priv = NULL; - - i2cinfo("SLAVEINIT"); - - switch (port) - { -#ifdef CONFIG_STM32_I2C1_SLAVE - case 1: - priv = (struct stm32_i2cslave_s *)&stm32_i2c1_priv; - break; -#endif -#ifdef CONFIG_STM32_I2C2_SLAVE - case 2: - priv = (struct stm32_i2cslave_s *)&stm32_i2c2_priv; - break; -#endif -#ifdef CONFIG_STM32_I2C3_SLAVE - case 3: - priv = (struct stm32_i2cslave_s *)&stm32_i2c3_priv; - break; -#endif - default: - return NULL; - } - - nxmutex_lock(&priv->lock); - if (priv->refs++ == 0) - { - ret = stm32_i2c_init(priv); - if (ret < 0) - { - stm32_i2c_deinit(priv); - priv = NULL; - } - } - - nxmutex_unlock(&priv->lock); - return (struct i2c_slave_s *)priv; -} - -/**************************************************************************** - * Name: stm32_i2cbus_slaveunitialize - * - * Description: - * Denitialize a given I2C device. - * - ****************************************************************************/ - -int stm32_i2cbus_slaveunitialize(struct i2c_slave_s *dev) -{ - struct stm32_i2cslave_s *priv = (struct stm32_i2cslave_s *)dev; - stm32_i2c_deinit(priv); - return OK; -} diff --git a/arch/arm/src/stm32/stm32_i2s.c b/arch/arm/src/stm32/stm32_i2s.c deleted file mode 100644 index af156dd8a7eac..0000000000000 --- a/arch/arm/src/stm32/stm32_i2s.c +++ /dev/null @@ -1,2611 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_i2s.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status - * must be provided by board-specific logic. They are implementations of - * the select and status methods of the SPI interface defined by struct - * spi_ops_s (see include/nuttx/spi/spi.h). All other methods (including - * up_spiinitialize()) are provided by common STM32 logic. To use this - * common SPI logic on your board: - * - * 1. Provide logic in stm32_boardinitialize() to configure I2S chip - * select pins. - * 2. Provide stm32_i2s2/3select() and stm32_i2s2/3status() functions in - * your board-specific logic. These functions will perform chip - * selection and status operations using GPIOs in the way your board - * is configured. - * 3. Add a calls to up_spiinitialize() in your low level application - * initialization logic - * 4. The handle returned by stm32_i2sbus_initialize() may then be used to - * bind the I2S driver to higher level logic - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include - -#include "arm_internal.h" -#include "stm32_dma.h" -#include "stm32_spi.h" -#include "stm32_rcc.h" - -#if defined(CONFIG_STM32_I2S2) || defined(CONFIG_STM32_I2S3) - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -#ifndef CONFIG_SCHED_WORKQUEUE -# error Work queue support is required (CONFIG_SCHED_WORKQUEUE) -#endif - -#ifndef CONFIG_AUDIO -# error CONFIG_AUDIO required by this driver -#endif - -#ifndef CONFIG_STM32_I2S_MAXINFLIGHT -# define CONFIG_STM32_I2S_MAXINFLIGHT 16 -#endif - -/* Assume no RX/TX support until we learn better */ - -#undef I2S_HAVE_RX -#undef I2S_HAVE_TX - -/* Check for I2S RX support */ - -# if defined(CONFIG_STM32_I2S3_RX) -# define I2S_HAVE_RX 1 - -# ifdef CONFIG_STM32_I2S_MCK -# define I2S_HAVE_MCK 1 -# endif - -# endif - -/* Check for I2S3 TX support */ - -# if defined(CONFIG_STM32_I2S3_TX) -# define I2S_HAVE_TX 1 - -# ifdef CONFIG_STM32_I2S_MCK -# define I2S_HAVE_MCK 1 -# endif - -# endif - -/* Configuration ************************************************************/ - -/* I2S interrupts */ - -#ifdef CONFIG_STM32_SPI_INTERRUPTS -# error "Interrupt driven I2S not yet supported" -#endif - -/* Can't have both interrupt driven SPI and SPI DMA */ - -#if defined(CONFIG_STM32_SPI_INTERRUPTS) && defined(CONFIG_STM32_SPI_DMA) -# error "Cannot enable both interrupt mode and DMA mode for SPI" -#endif - -/* SPI DMA priority */ - -#ifdef CONFIG_STM32_SPI_DMA - -# if defined(CONFIG_SPI_DMAPRIO) -# define SPI_DMA_PRIO CONFIG_SPI_DMAPRIO -# elif defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32L15XX) -# define SPI_DMA_PRIO DMA_CCR_PRIMED -# elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) -# define SPI_DMA_PRIO DMA_SCR_PRIMED -# else -# error "Unknown STM32 DMA" -# endif - -# if defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32L15XX) -# if (SPI_DMA_PRIO & ~DMA_CCR_PL_MASK) != 0 -# error "Illegal value for CONFIG_SPI_DMAPRIO" -# endif -# elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) -# if (SPI_DMA_PRIO & ~DMA_SCR_PL_MASK) != 0 -# error "Illegal value for CONFIG_SPI_DMAPRIO" -# endif -# else -# error "Unknown STM32 DMA" -# endif - -#endif - -/* DMA channel configuration */ - -#if defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F30XX) || \ - defined(CONFIG_STM32_STM32L15XX) -# define SPI_RXDMA16_CONFIG (SPI_DMA_PRIO|DMA_CCR_MSIZE_16BITS|DMA_CCR_PSIZE_16BITS|DMA_CCR_MINC ) -# define SPI_RXDMA8_CONFIG (SPI_DMA_PRIO|DMA_CCR_MSIZE_8BITS |DMA_CCR_PSIZE_8BITS |DMA_CCR_MINC ) -# define SPI_RXDMA16NULL_CONFIG (SPI_DMA_PRIO|DMA_CCR_MSIZE_8BITS |DMA_CCR_PSIZE_16BITS ) -# define SPI_RXDMA8NULL_CONFIG (SPI_DMA_PRIO|DMA_CCR_MSIZE_8BITS |DMA_CCR_PSIZE_8BITS ) -# define SPI_TXDMA16_CONFIG (SPI_DMA_PRIO|DMA_CCR_MSIZE_16BITS|DMA_CCR_PSIZE_16BITS|DMA_CCR_MINC|DMA_CCR_DIR) -# define SPI_TXDMA8_CONFIG (SPI_DMA_PRIO|DMA_CCR_MSIZE_8BITS |DMA_CCR_PSIZE_8BITS |DMA_CCR_MINC|DMA_CCR_DIR) -# define SPI_TXDMA16NULL_CONFIG (SPI_DMA_PRIO|DMA_CCR_MSIZE_8BITS |DMA_CCR_PSIZE_16BITS |DMA_CCR_DIR) -# define SPI_TXDMA8NULL_CONFIG (SPI_DMA_PRIO|DMA_CCR_MSIZE_8BITS |DMA_CCR_PSIZE_8BITS |DMA_CCR_DIR) -#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) -# define SPI_RXDMA16_CONFIG (SPI_DMA_PRIO|DMA_SCR_MSIZE_16BITS|DMA_SCR_PSIZE_16BITS|DMA_SCR_MINC|DMA_SCR_DIR_P2M) -# define SPI_RXDMA8_CONFIG (SPI_DMA_PRIO|DMA_SCR_MSIZE_8BITS |DMA_SCR_PSIZE_8BITS |DMA_SCR_MINC|DMA_SCR_DIR_P2M) -# define SPI_RXDMA16NULL_CONFIG (SPI_DMA_PRIO|DMA_SCR_MSIZE_8BITS |DMA_SCR_PSIZE_16BITS |DMA_SCR_DIR_P2M) -# define SPI_RXDMA8NULL_CONFIG (SPI_DMA_PRIO|DMA_SCR_MSIZE_8BITS |DMA_SCR_PSIZE_8BITS |DMA_SCR_DIR_P2M) -# define SPI_TXDMA16_CONFIG (SPI_DMA_PRIO|DMA_SCR_MSIZE_16BITS|DMA_SCR_PSIZE_16BITS|DMA_SCR_MINC|DMA_SCR_DIR_M2P) -# define SPI_TXDMA8_CONFIG (SPI_DMA_PRIO|DMA_SCR_MSIZE_8BITS |DMA_SCR_PSIZE_8BITS |DMA_SCR_MINC|DMA_SCR_DIR_M2P) -# define SPI_TXDMA16NULL_CONFIG (SPI_DMA_PRIO|DMA_SCR_MSIZE_8BITS |DMA_SCR_PSIZE_16BITS |DMA_SCR_DIR_M2P) -# define SPI_TXDMA8NULL_CONFIG (SPI_DMA_PRIO|DMA_SCR_MSIZE_8BITS |DMA_SCR_PSIZE_8BITS |DMA_SCR_DIR_M2P) -#else -# error "Unknown STM32 DMA" -#endif - -/* Debug ********************************************************************/ - -/* Check if SSC debug is enabled (non-standard.. no support in - * include/nuttx/debug.h - */ - -#ifndef CONFIG_DEBUG_I2S_INFO -# undef CONFIG_STM32_I2S_DMADEBUG -# undef CONFIG_STM32_I2S_REGDEBUG -# undef CONFIG_STM32_I2S_QDEBUG -# undef CONFIG_STM32_I2S_DUMPBUFFERS -#endif - -/* The I2S can handle most any bit width from 8 to 32. However, the DMA - * logic here is constrained to byte, half-word, and word sizes. - */ - -#ifndef CONFIG_STM32_I2S3_DATALEN -# define CONFIG_STM32_I2S3_DATALEN 16 -#endif - -#if CONFIG_STM32_I2S3_DATALEN == 8 -# define STM32_I2S3_DATAMASK 0 -#elif CONFIG_STM32_I2S3_DATALEN == 16 -# define STM32_I2S3_DATAMASK 1 -#elif CONFIG_STM32_I2S3_DATALEN < 8 || CONFIG_STM32_I2S3_DATALEN > 16 -# error Invalid value for CONFIG_STM32_I2S3_DATALEN -#else -# error Valid but supported value for CONFIG_STM32_I2S3_DATALEN -#endif - -/* Check if we need to build RX and/or TX support */ - -#if defined(I2S_HAVE_RX) || defined(I2S_HAVE_TX) - -#ifndef CONFIG_DEBUG_DMA -# undef CONFIG_STM32_I2S_DMADEBUG -#endif - -#define DMA_INITIAL 0 -#define DMA_AFTER_SETUP 1 -#define DMA_AFTER_START 2 -#define DMA_CALLBACK 3 -#define DMA_TIMEOUT 3 -#define DMA_END_TRANSFER 4 -#define DMA_NSAMPLES 5 - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/* I2S buffer container */ - -struct stm32_buffer_s -{ - struct stm32_buffer_s *flink; /* Supports a singly linked list */ - i2s_callback_t callback; /* Function to call when the transfer - * completes */ - uint32_t timeout; /* The timeout value to use with DMA - * transfers */ - void *arg; /* The argument to be returned with the - * callback */ - struct ap_buffer_s *apb; /* The audio buffer */ - int result; /* The result of the transfer */ -}; - -/* This structure describes the state of one receiver or transmitter - * transport. - */ - -struct stm32_transport_s -{ - DMA_HANDLE dma; /* I2S DMA handle */ - struct wdog_s dog; /* Watchdog that handles DMA timeouts */ - sq_queue_t pend; /* A queue of pending transfers */ - sq_queue_t act; /* A queue of active transfers */ - sq_queue_t done; /* A queue of completed transfers */ - struct work_s work; /* Supports worker thread operations */ - -#ifdef CONFIG_STM32_I2S_DMADEBUG - struct stm32_dmaregs_s dmaregs[DMA_NSAMPLES]; -#endif -}; - -/* The state of the one I2S peripheral */ - -struct stm32_i2s_s -{ - struct i2s_dev_s dev; /* Externally visible I2S interface */ - uintptr_t base; /* I2S controller register base address */ - mutex_t lock; /* Assures mutually exclusive access to I2S */ - bool initialized; /* Has I2S interface been initialized */ - uint8_t datalen; /* Data width (8 or 16) */ - uint8_t align; /* Log2 of data width (0 or 1) */ - uint8_t rxenab:1; /* True: RX transfers enabled */ - uint8_t txenab:1; /* True: TX transfers enabled */ - uint8_t i2sno:6; /* I2S controller number (0 or 1) */ -#ifdef I2S_HAVE_MCK - uint32_t samplerate; /* Data sample rate (determines only MCK - * divider) */ -#endif - uint32_t rxccr; /* DMA control register for RX transfers */ - uint32_t txccr; /* DMA control register for TX transfers */ -#ifdef I2S_HAVE_RX - struct stm32_transport_s rx; /* RX transport state */ -#endif -#ifdef I2S_HAVE_TX - struct stm32_transport_s tx; /* TX transport state */ -#endif - - /* Pre-allocated pool of buffer containers */ - - sem_t bufsem; /* Buffer wait semaphore */ - struct stm32_buffer_s *freelist; /* A list a free buffer containers */ - struct stm32_buffer_s containers[CONFIG_STM32_I2S_MAXINFLIGHT]; - - /* Debug stuff */ - -#ifdef CONFIG_STM32_I2S_REGDEBUG - bool wr; /* Last was a write */ - uint32_t regaddr; /* Last address */ - uint16_t regval; /* Last value */ - int count; /* Number of times */ -#endif -}; - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -/* Register helpers */ - -#ifdef CONFIG_STM32_I2S_REGDEBUG -static bool i2s_checkreg(struct stm32_i2s_s *priv, bool wr, - uint16_t regval, uint32_t regaddr); -#else -# define i2s_checkreg(priv,wr,regval,regaddr) (false) -#endif - -static inline uint16_t i2s_getreg(struct stm32_i2s_s *priv, uint8_t offset); -static inline void i2s_putreg(struct stm32_i2s_s *priv, uint8_t offset, - uint16_t regval); - -#if defined(CONFIG_DEBUG_I2S_INFO) -static void i2s_dump_regs(struct stm32_i2s_s *priv, const char *msg); -#else -# define i2s_dump_regs(s,m) -#endif - -#ifdef CONFIG_STM32_I2S_DUMPBUFFERS -# define i2s_init_buffer(b,s) memset(b, 0x55, s); -# define i2s_dump_buffer(m,b,s) lib_dumpbuffer(m,b,s) -#else -# define i2s_init_buffer(b,s) -# define i2s_dump_buffer(m,b,s) -#endif - -/* Buffer container helpers */ - -static struct stm32_buffer_s * - i2s_buf_allocate(struct stm32_i2s_s *priv); -static void i2s_buf_free(struct stm32_i2s_s *priv, - struct stm32_buffer_s *bfcontainer); -static void i2s_buf_initialize(struct stm32_i2s_s *priv); - -/* DMA support */ - -#ifdef CONFIG_STM32_I2S_DMADEBUG -static void i2s_dma_sampleinit(struct stm32_i2s_s *priv, - struct stm32_transport_s *xpt); -#endif - -#if defined(CONFIG_STM32_I2S_DMADEBUG) && defined(I2S_HAVE_RX) -# define i2s_rxdma_sample(s,i) stm32_dmasample((s)->rx.dma, &(s)->rx.dmaregs[i]) -# define i2s_rxdma_sampleinit(s) i2s_dma_sampleinit(s, &(s)->rx) -static void i2s_rxdma_sampledone(struct stm32_i2s_s *priv, int result); - -#else -# define i2s_rxdma_sample(s,i) -# define i2s_rxdma_sampleinit(s) -# define i2s_rxdma_sampledone(s,r) - -#endif - -#if defined(CONFIG_STM32_I2S_DMADEBUG) && defined(I2S_HAVE_TX) -# define i2s_txdma_sample(s,i) stm32_dmasample((s)->tx.dma, &(s)->tx.dmaregs[i]) -# define i2s_txdma_sampleinit(s) i2s_dma_sampleinit(s, &(s)->tx) -static void i2s_txdma_sampledone(struct stm32_i2s_s *priv, int result); - -#else -# define i2s_txdma_sample(s,i) -# define i2s_txdma_sampleinit(s) -# define i2s_txdma_sampledone(s,r) - -#endif - -#ifdef I2S_HAVE_RX -static void i2s_rxdma_timeout(wdparm_t arg); -static int i2s_rxdma_setup(struct stm32_i2s_s *priv); -static void i2s_rx_worker(void *arg); -static void i2s_rx_schedule(struct stm32_i2s_s *priv, int result); -static void i2s_rxdma_callback(DMA_HANDLE handle, uint8_t result, - void *arg); -#endif -#ifdef I2S_HAVE_TX -static void i2s_txdma_timeout(wdparm_t arg); -static int i2s_txdma_setup(struct stm32_i2s_s *priv); -static void i2s_tx_worker(void *arg); -static void i2s_tx_schedule(struct stm32_i2s_s *priv, int result); -static void i2s_txdma_callback(DMA_HANDLE handle, uint8_t result, - void *arg); -#endif - -/* I2S methods (and close friends) */ - -static int i2s_checkwidth(struct stm32_i2s_s *priv, int bits); - -static uint32_t stm32_i2s_rxsamplerate(struct i2s_dev_s *dev, uint32_t rate); -static uint32_t stm32_i2s_rxdatawidth(struct i2s_dev_s *dev, int bits); -static int stm32_i2s_receive(struct i2s_dev_s *dev, - struct ap_buffer_s *apb, - i2s_callback_t callback, - void *arg, uint32_t timeout); -static uint32_t stm32_i2s_txsamplerate(struct i2s_dev_s *dev, uint32_t rate); -static uint32_t stm32_i2s_txdatawidth(struct i2s_dev_s *dev, int bits); -static int stm32_i2s_send(struct i2s_dev_s *dev, - struct ap_buffer_s *apb, - i2s_callback_t callback, void *arg, - uint32_t timeout); - -/* Initialization */ - -static uint32_t i2s_mckdivider(struct stm32_i2s_s *priv); -static int i2s_dma_flags(struct stm32_i2s_s *priv); -static int i2s_dma_allocate(struct stm32_i2s_s *priv); -static void i2s_dma_free(struct stm32_i2s_s *priv); -#ifdef CONFIG_STM32_I2S2 -static void i2s2_configure(struct stm32_i2s_s *priv); -#endif -#ifdef CONFIG_STM32_I2S3 -static void i2s3_configure(struct stm32_i2s_s *priv); -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* I2S device operations */ - -static const struct i2s_ops_s g_i2sops = -{ - /* Receiver methods */ - - .i2s_rxsamplerate = stm32_i2s_rxsamplerate, - .i2s_rxdatawidth = stm32_i2s_rxdatawidth, - .i2s_receive = stm32_i2s_receive, - - /* Transmitter methods */ - - .i2s_txsamplerate = stm32_i2s_txsamplerate, - .i2s_txdatawidth = stm32_i2s_txdatawidth, - .i2s_send = stm32_i2s_send, -}; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: i2s_checkreg - * - * Description: - * Check if the current register access is a duplicate of the preceding. - * - * Input Parameters: - * regval - The value to be written - * regaddr - The address of the register to write to - * - * Returned Value: - * true: This is the first register access of this type. - * false: This is the same as the preceding register access. - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_I2S_REGDEBUG -static bool i2s_checkreg(struct stm32_i2s_s *priv, bool wr, uint16_t regval, - uint32_t regaddr) -{ - if (wr == priv->wr && /* Same kind of access? */ - regval == priv->regval && /* Same value? */ - regaddr == priv->regaddr) /* Same address? */ - { - /* Yes, then just keep a count of the number of times we did this. */ - - priv->count++; - return false; - } - else - { - /* Did we do the previous operation more than once? */ - - if (priv->count > 0) - { - /* Yes... show how many times we did it */ - - i2sinfo("...[Repeats %d times]...\n", priv->count); - } - - /* Save information about the new access */ - - priv->wr = wr; - priv->regval = regval; - priv->regaddr = regaddr; - priv->count = 0; - } - - /* Return true if this is the first time that we have done this operation */ - - return true; -} -#endif - -/**************************************************************************** - * Name: i2s_getreg - * - * Description: - * Get the contents of the I2S register at offset - * - * Input Parameters: - * priv - private I2S device structure - * offset - offset to the register of interest - * - * Returned Value: - * The contents of the 16-bit register - * - ****************************************************************************/ - -static inline uint16_t i2s_getreg(struct stm32_i2s_s *priv, - uint8_t offset) -{ - uint32_t regaddr = priv->base + offset; - uint16_t regval = getreg16(regaddr); - -#ifdef CONFIG_STM32_I2S_REGDEBUG - if (i2s_checkreg(priv, false, regval, regaddr)) - { - i2sinfo("%08" PRIx32 "->%04x\n", regaddr, regval); - } -#endif - - return regval; -} - -/**************************************************************************** - * Name: spi_putreg - * - * Description: - * Write a 16-bit value to the SPI register at offset - * - * Input Parameters: - * priv - private SPI device structure - * offset - offset to the register of interest - * value - the 16-bit value to be written - * - * Returned Value: - * The contents of the 16-bit register - * - ****************************************************************************/ - -static inline void i2s_putreg(struct stm32_i2s_s *priv, uint8_t offset, - uint16_t regval) -{ - uint32_t regaddr = priv->base + offset; - -#ifdef CONFIG_STM32_I2S_REGDEBUG - if (i2s_checkreg(priv, true, regval, regaddr)) - { - i2sinfo("%08" PRIx32 "<-%04x\n", regaddr, regval); - } -#endif - - putreg16(regval, regaddr); -} - -/**************************************************************************** - * Name: i2s_dump_regs - * - * Description: - * Dump the contents of all I2S registers - * - * Input Parameters: - * priv - The I2S controller to dump - * msg - Message to print before the register data - * - * Returned Value: - * None - * - ****************************************************************************/ - -#if defined(CONFIG_DEBUG_I2S) -static void i2s_dump_regs(struct stm32_i2s_s *priv, const char *msg) -{ - i2sinfo("I2S%d: %s\n", priv->i2sno, msg); - i2sinfo(" CR1:%04x CR2:%04x SR:%04x DR:%04x\n", - i2s_getreg(priv, STM32_SPI_CR1_OFFSET), - i2s_getreg(priv, STM32_SPI_CR2_OFFSET), - i2s_getreg(priv, STM32_SPI_SR_OFFSET), - i2s_getreg(priv, STM32_SPI_DR_OFFSET)); - i2sinfo(" I2SCFGR:%04x I2SPR:%04x\n", - i2s_getreg(priv, STM32_SPI_I2SCFGR_OFFSET), - i2s_getreg(priv, STM32_SPI_I2SPR_OFFSET)); -} -#endif - -/**************************************************************************** - * Name: i2s_buf_allocate - * - * Description: - * Allocate a buffer container by removing the one at the head of the - * free list - * - * Input Parameters: - * priv - I2S state instance - * - * Returned Value: - * A non-NULL pointer to the allocate buffer container on success; NULL if - * there are no available buffer containers. - * - * Assumptions: - * The caller does NOT have exclusive access to the I2S state structure. - * That would result in a deadlock! - * - ****************************************************************************/ - -static struct stm32_buffer_s *i2s_buf_allocate(struct stm32_i2s_s *priv) -{ - struct stm32_buffer_s *bfcontainer; - irqstate_t flags; - int ret; - - /* Set aside a buffer container. By doing this, we guarantee that we will - * have at least one free buffer container. - */ - - ret = nxsem_wait_uninterruptible(&priv->bufsem); - if (ret < 0) - { - return NULL; - } - - /* Get the buffer from the head of the free list */ - - flags = enter_critical_section(); - bfcontainer = priv->freelist; - DEBUGASSERT(bfcontainer); - - /* Unlink the buffer from the freelist */ - - priv->freelist = bfcontainer->flink; - leave_critical_section(flags); - return bfcontainer; -} - -/**************************************************************************** - * Name: i2s_buf_free - * - * Description: - * Free buffer container by adding it to the head of the free list - * - * Input Parameters: - * priv - I2S state instance - * bfcontainer - The buffer container to be freed - * - * Returned Value: - * None - * - * Assumptions: - * The caller has exclusive access to the I2S state structure - * - ****************************************************************************/ - -static void i2s_buf_free(struct stm32_i2s_s *priv, - struct stm32_buffer_s *bfcontainer) -{ - irqstate_t flags; - - /* Put the buffer container back on the free list */ - - flags = enter_critical_section(); - bfcontainer->flink = priv->freelist; - priv->freelist = bfcontainer; - leave_critical_section(flags); - - /* Wake up any threads waiting for a buffer container */ - - nxsem_post(&priv->bufsem); -} - -/**************************************************************************** - * Name: i2s_buf_initialize - * - * Description: - * Initialize the buffer container allocator by adding all of the - * pre-allocated buffer containers to the free list - * - * Input Parameters: - * priv - I2S state instance - * - * Returned Value: - * None - * - * Assumptions: - * Called early in I2S initialization so that there are no issues with - * concurrency. - * - ****************************************************************************/ - -static void i2s_buf_initialize(struct stm32_i2s_s *priv) -{ - int i; - - priv->freelist = NULL; - nxsem_init(&priv->bufsem, 0, CONFIG_STM32_I2S_MAXINFLIGHT); - - for (i = 0; i < CONFIG_STM32_I2S_MAXINFLIGHT; i++) - { - i2s_buf_free(priv, &priv->containers[i]); - } -} - -/**************************************************************************** - * Name: i2s_dma_sampleinit - * - * Description: - * Initialize sampling of DMA registers (if CONFIG_STM32_I2S_DMADEBUG) - * - * Input Parameters: - * priv - I2S state instance - * - * Returned Value: - * None - * - ****************************************************************************/ - -#if defined(CONFIG_STM32_I2S_DMADEBUG) -static void i2s_dma_sampleinit(struct stm32_i2s_s *priv, - struct stm32_transport_s *xpt) -{ - /* Put contents of register samples into a known state */ - - memset(xpt->dmaregs, 0xff, DMA_NSAMPLES * sizeof(struct stm32_dmaregs_s)); - - /* Then get the initial samples */ - - stm32_dmasample(xpt->dma, &xpt->dmaregs[DMA_INITIAL]); -} -#endif - -/**************************************************************************** - * Name: i2s_rxdma_sampledone - * - * Description: - * Dump sampled RX DMA registers - * - * Input Parameters: - * priv - I2S state instance - * - * Returned Value: - * None - * - ****************************************************************************/ - -#if defined(CONFIG_STM32_I2S_DMADEBUG) && defined(I2S_HAVE_RX) -static void i2s_rxdma_sampledone(struct stm32_i2s_s *priv, int result) -{ - i2sinfo("result: %d\n", result); - - /* Sample the final registers */ - - stm32_dmasample(priv->rx.dma, &priv->rx.dmaregs[DMA_END_TRANSFER]); - - /* Then dump the sampled DMA registers */ - - /* Initial register values */ - - stm32_dmadump(priv->rx.dma, &priv->rx.dmaregs[DMA_INITIAL], - "RX: Initial Registers"); - - /* Register values after DMA setup */ - - stm32_dmadump(priv->rx.dma, &priv->rx.dmaregs[DMA_AFTER_SETUP], - "RX: After DMA Setup"); - - /* Register values after DMA start */ - - stm32_dmadump(priv->rx.dma, &priv->rx.dmaregs[DMA_AFTER_START], - "RX: After DMA Start"); - - /* Register values at the time of the TX and RX DMA callbacks - * -OR- DMA timeout. - * - * If the DMA timedout, then there will not be any RX DMA - * callback samples. There is probably no TX DMA callback - * samples either, but we don't know for sure. - */ - - if (result == -ETIMEDOUT || result == -EINTR) - { - stm32_dmadump(priv->rx.dma, &priv->rx.dmaregs[DMA_TIMEOUT], - "RX: At DMA timeout"); - } - else - { - stm32_dmadump(priv->rx.dma, &priv->rx.dmaregs[DMA_CALLBACK], - "RX: At DMA callback"); - } - - stm32_dmadump(priv->rx.dma, &priv->rx.dmaregs[DMA_END_TRANSFER], - "RX: At End-of-Transfer"); - - i2s_dump_regs(priv, "RX: At End-of-Transfer"); -} -#endif - -/**************************************************************************** - * Name: i2s_txdma_sampledone - * - * Description: - * Dump sampled DMA registers - * - * Input Parameters: - * priv - I2S state instance - * - * Returned Value: - * None - * - ****************************************************************************/ - -#if defined(CONFIG_STM32_I2S_DMADEBUG) && defined(I2S_HAVE_TX) -static void i2s_txdma_sampledone(struct stm32_i2s_s *priv, int result) -{ - i2sinfo("result: %d\n", result); - - /* Sample the final registers */ - - stm32_dmasample(priv->tx.dma, &priv->tx.dmaregs[DMA_END_TRANSFER]); - - /* Then dump the sampled DMA registers */ - - /* Initial register values */ - - stm32_dmadump(priv->tx.dma, &priv->tx.dmaregs[DMA_INITIAL], - "TX: Initial Registers"); - - /* Register values after DMA setup */ - - stm32_dmadump(priv->tx.dma, &priv->tx.dmaregs[DMA_AFTER_SETUP], - "TX: After DMA Setup"); - - /* Register values after DMA start */ - - stm32_dmadump(priv->tx.dma, &priv->tx.dmaregs[DMA_AFTER_START], - "TX: After DMA Start"); - - /* Register values at the time of the TX and RX DMA callbacks - * -OR- DMA timeout. - */ - - if (result == -ETIMEDOUT || result == -EINTR) - { - stm32_dmadump(priv->tx.dma, &priv->tx.dmaregs[DMA_TIMEOUT], - "TX: At DMA timeout"); - } - else - { - stm32_dmadump(priv->tx.dma, &priv->tx.dmaregs[DMA_CALLBACK], - "TX: At DMA callback"); - } - - stm32_dmadump(priv->tx.dma, &priv->tx.dmaregs[DMA_END_TRANSFER], - "TX: At End-of-Transfer"); - - i2s_dump_regs(priv, "TX: At End-of-Transfer"); -} -#endif - -/**************************************************************************** - * Name: i2s_rxdma_timeout - * - * Description: - * The RX watchdog timeout without completion of the RX DMA. - * - * Input Parameters: - * arg - The argument - * - * Returned Value: - * None - * - * Assumptions: - * Always called from the interrupt level with interrupts disabled. - * - ****************************************************************************/ - -#ifdef I2S_HAVE_RX -static void i2s_rxdma_timeout(wdparm_t arg) -{ - struct stm32_i2s_s *priv = (struct stm32_i2s_s *)arg; - DEBUGASSERT(priv != NULL); - - /* Sample DMA registers at the time of the timeout */ - - i2s_rxdma_sample(priv, DMA_TIMEOUT); - - /* Cancel the DMA */ - - stm32_dmastop(priv->rx.dma); - - /* Then schedule completion of the transfer to occur on the worker thread. - * NOTE: stm32_dmastop() will call the DMA complete callback with an error - * of -EINTR. So the following is just insurance and should have no - * effect if the worker is already schedule. - */ - - i2s_rx_schedule(priv, -ETIMEDOUT); -} -#endif - -/**************************************************************************** - * Name: i2s_rxdma_setup - * - * Description: - * Setup and initiate the next RX DMA transfer - * - * Input Parameters: - * priv - I2S state instance - * - * Returned Value: - * OK on success; a negated errno value on failure - * - * Assumptions: - * Interrupts are disabled - * - ****************************************************************************/ - -#ifdef I2S_HAVE_RX -static int i2s_rxdma_setup(struct stm32_i2s_s *priv) -{ - struct stm32_buffer_s *bfcontainer; - struct ap_buffer_s *apb; - uintptr_t samp; - uint32_t timeout; - bool notimeout; - int ret; - - /* If there is already an active transmission in progress, then bail - * returning success. - */ - - if (!sq_empty(&priv->rx.act)) - { - return OK; - } - - /* If there are no pending transfer, then bail returning success */ - - if (sq_empty(&priv->rx.pend)) - { - return OK; - } - - /* Initialize DMA register sampling */ - - i2s_rxdma_sampleinit(priv); - - /* Loop, adding each pending DMA */ - - timeout = 0; - notimeout = false; - - do - { - /* Remove the pending RX transfer at the head of the RX pending - * queue. - */ - - bfcontainer = (struct stm32_buffer_s *)sq_remfirst(&priv->rx.pend); - DEBUGASSERT(bfcontainer && bfcontainer->apb); - - apb = bfcontainer->apb; - DEBUGASSERT(((uintptr_t)apb->samp % priv->align) == 0); - - /* No data received yet */ - - apb->nbytes = 0; - apb->curbyte = 0; - samp = (uintptr_t)&apb->samp[apb->curbyte]; - - /* Configure the RX DMA */ - - stm32_dmasetup(priv->rx.dma, priv->base + STM32_SPI_DR_OFFSET, - (uint32_t)samp, apb->nmaxbytes, priv->rxccr); - - /* Increment the DMA timeout */ - - if (bfcontainer->timeout > 0) - { - timeout += bfcontainer->timeout; - } - else - { - notimeout = true; - } - - /* Add the container to the list of active DMAs */ - - sq_addlast((sq_entry_t *)bfcontainer, &priv->rx.act); - } -#if 1 /* REVISIT: Chained RX transfers */ - while (0); -#else - while (!sq_empty(&priv->rx.pend)); -#endif - - /* Sample DMA registers */ - - i2s_rxdma_sample(priv, DMA_AFTER_SETUP); - - /* Start the DMA, saving the container as the current active transfer */ - - stm32_dmastart(priv->rx.dma, i2s_rxdma_callback, priv, false); - - i2s_rxdma_sample(priv, DMA_AFTER_START); - - /* Enable the receiver */ - - i2s_putreg(priv, STM32_SPI_CR2_OFFSET, - i2s_getreg(priv, STM32_SPI_CR2_OFFSET) | SPI_CR2_RXDMAEN); - - /* Start a watchdog to catch DMA timeouts */ - - if (!notimeout) - { - ret = wd_start(&priv->rx.dog, timeout, - i2s_rxdma_timeout, (wdparm_t)priv); - - /* Check if we have successfully started the watchdog timer. Note - * that we do nothing in the case of failure to start the timer. We - * are already committed to the DMA anyway. Let's just hope that the - * DMA does not hang. - */ - - if (ret < 0) - { - i2serr("ERROR: wd_start failed: %d\n", ret); - } - } - - return OK; -} -#endif - -/**************************************************************************** - * Name: i2s_rx_worker - * - * Description: - * RX transfer done worker - * - * Input Parameters: - * arg - the I2S device instance cast to void* - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef I2S_HAVE_RX -static void i2s_rx_worker(void *arg) -{ - struct stm32_i2s_s *priv = (struct stm32_i2s_s *)arg; - struct stm32_buffer_s *bfcontainer; - struct ap_buffer_s *apb; - irqstate_t flags; - - DEBUGASSERT(priv); - - /* When the transfer was started, the active buffer containers were removed - * from the rx.pend queue and saved in the rx.act queue. We get here when - * the DMA is finished... either successfully, with a DMA error, or with a - * DMA timeout. - * - * In any case, the buffer containers in rx.act will be moved to the end - * of the rx.done queue and rx.act queue will be emptied before this worker - * is started. - * - * REVISIT: Normal DMA callback processing should restart the DMA - * immediately to avoid audio artifacts at the boundaries between DMA - * transfers. Unfortunately, the DMA callback occurs at the interrupt - * level and we cannot call dma_rxsetup() from the interrupt level. - * So we have to start the next DMA here. - */ - - i2sinfo("rx.act.head=%p rx.done.head=%p\n", - priv->rx.act.head, priv->rx.done.head); - - /* Check if the DMA is IDLE */ - - if (sq_empty(&priv->rx.act)) - { -#ifdef CONFIG_STM32_I2S_DMADEBUG - bfcontainer = (struct stm32_buffer_s *)sq_peek(&priv->rx.done); - if (bfcontainer) - { - /* Dump the DMA registers */ - - i2s_rxdma_sampledone(priv, bfcontainer->result); - } -#endif - - /* Then start the next DMA. This must be done with interrupts - * disabled. - */ - - flags = enter_critical_section(); - i2s_rxdma_setup(priv); - leave_critical_section(flags); - } - - /* Process each buffer in the rx.done queue */ - - while (sq_peek(&priv->rx.done) != NULL) - { - /* Remove the buffer container from the rx.done queue. NOTE that - * interrupts must be enabled to do this because the rx.done queue is - * also modified from the interrupt level. - */ - - flags = enter_critical_section(); - bfcontainer = (struct stm32_buffer_s *)sq_remfirst(&priv->rx.done); - leave_critical_section(flags); - - DEBUGASSERT(bfcontainer && bfcontainer->apb && bfcontainer->callback); - apb = bfcontainer->apb; - - /* If the DMA was successful, then update the number of valid bytes in - * the audio buffer. - */ - - if (bfcontainer->result == OK) - { - apb->nbytes = apb->nmaxbytes; - } - - i2s_dump_buffer("Received", apb->samp, apb->nbytes); - - /* Perform the RX transfer done callback */ - - bfcontainer->callback(&priv->dev, apb, bfcontainer->arg, - bfcontainer->result); - - /* Release our reference on the audio buffer. This may very likely - * cause the audio buffer to be freed. - */ - - apb_free(apb); - - /* And release the buffer container */ - - i2s_buf_free(priv, bfcontainer); - } -} -#endif - -/**************************************************************************** - * Name: i2s_rx_schedule - * - * Description: - * An RX DMA completion or timeout has occurred. Schedule processing on - * the working thread. - * - * Input Parameters: - * handle - The DMA handler - * arg - A pointer to the chip select struction - * result - The result of the DMA transfer - * - * Returned Value: - * None - * - * Assumptions: - * Interrupts are disabled - * - ****************************************************************************/ - -#ifdef I2S_HAVE_RX -static void i2s_rx_schedule(struct stm32_i2s_s *priv, int result) -{ - struct stm32_buffer_s *bfcontainer; - int ret; - - /* Upon entry, the transfer(s) that just completed are the ones in the - * priv->rx.act queue. NOTE: In certain conditions, this function may - * be called an additional time, hence, we can't assert this to be true. - * For example, in the case of a timeout, this function will be called by - * both indirectly via the stm32_dmastop() logic and directly via the - * i2s_rxdma_timeout() logic. - */ - - /* Move all entries from the rx.act queue to the rx.done queue */ - - while (!sq_empty(&priv->rx.act)) - { - /* Remove the next buffer container from the rx.act list */ - - bfcontainer = (struct stm32_buffer_s *)sq_remfirst(&priv->rx.act); - - /* Report the result of the transfer */ - - bfcontainer->result = result; - - /* Add the completed buffer container to the tail of the rx.done - * queue - */ - - sq_addlast((sq_entry_t *)bfcontainer, &priv->rx.done); - } - - /* If the worker has completed running, then reschedule the working thread. - * REVISIT: There may be a race condition here. So we do nothing is the - * worker is not available. - */ - - if (work_available(&priv->rx.work)) - { - /* Schedule the TX DMA done processing to occur on the worker thread. */ - - ret = work_queue(HPWORK, &priv->rx.work, i2s_rx_worker, priv, 0); - if (ret != 0) - { - i2serr("ERROR: Failed to queue RX work: %d\n", ret); - } - } -} -#endif - -/**************************************************************************** - * Name: i2s_rxdma_callback - * - * Description: - * This callback function is invoked at the completion of the I2S RX DMA. - * - * Input Parameters: - * handle - The DMA handler - * arg - A pointer to the chip select struction - * result - The result of the DMA transfer - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef I2S_HAVE_RX -static void i2s_rxdma_callback(DMA_HANDLE handle, uint8_t result, void *arg) -{ - struct stm32_i2s_s *priv = (struct stm32_i2s_s *)arg; - DEBUGASSERT(priv != NULL); - - /* Cancel the watchdog timeout */ - - wd_cancel(&priv->rx.dog); - - /* Sample DMA registers at the time of the DMA completion */ - - i2s_rxdma_sample(priv, DMA_CALLBACK); - - /* REVISIT: We would like to the next DMA started here so that we do not - * get audio glitches at the boundaries between DMA transfers. - * Unfortunately, we cannot call stm32_dmasetup() from an interrupt - * handler! - */ - - /* Then schedule completion of the transfer to occur on the worker thread */ - - i2s_rx_schedule(priv, result); -} -#endif - -/**************************************************************************** - * Name: i2s_txdma_timeout - * - * Description: - * The RX watchdog timeout without completion of the RX DMA. - * - * Input Parameters: - * arg - The argument - * - * Returned Value: - * None - * - * Assumptions: - * Always called from the interrupt level with interrupts disabled. - * - ****************************************************************************/ - -#ifdef I2S_HAVE_TX -static void i2s_txdma_timeout(wdparm_t arg) -{ - struct stm32_i2s_s *priv = (struct stm32_i2s_s *)arg; - DEBUGASSERT(priv != NULL); - - /* Sample DMA registers at the time of the timeout */ - - i2s_txdma_sample(priv, DMA_TIMEOUT); - - /* Cancel the DMA */ - - stm32_dmastop(priv->tx.dma); - - /* Then schedule completion of the transfer to occur on the worker thread. - * NOTE: stm32_dmastop() will call the DMA complete callback with an error - * of -EINTR. So the following is just insurance and should have no - * effect if the worker is already schedule. - */ - - i2s_tx_schedule(priv, -ETIMEDOUT); -} -#endif - -/**************************************************************************** - * Name: i2s_txdma_setup - * - * Description: - * Setup and initiate the next TX DMA transfer - * - * Input Parameters: - * priv - I2S state instance - * - * Returned Value: - * OK on success; a negated errno value on failure - * - * Assumptions: - * Interrupts are disabled - * - ****************************************************************************/ - -#ifdef I2S_HAVE_TX -static int i2s_txdma_setup(struct stm32_i2s_s *priv) -{ - struct stm32_buffer_s *bfcontainer; - struct ap_buffer_s *apb; - uintptr_t samp; - uint32_t timeout; - apb_samp_t nbytes; - bool notimeout; - int ret; - - /* If there is already an active transmission in progress, then bail - * returning success. - */ - - if (!sq_empty(&priv->tx.act)) - { - return OK; - } - - /* If there are no pending transfer, then bail returning success */ - - if (sq_empty(&priv->tx.pend)) - { - return OK; - } - - /* Initialize DMA register sampling */ - - i2s_txdma_sampleinit(priv); - - /* Loop, adding each pending DMA */ - - timeout = 0; - notimeout = false; - - do - { - /* Remove the pending TX transfer at the head of the TX pending - * queue. - */ - - bfcontainer = (struct stm32_buffer_s *)sq_remfirst(&priv->tx.pend); - DEBUGASSERT(bfcontainer && bfcontainer->apb); - - apb = bfcontainer->apb; - - /* Get the transfer information, accounting for any data offset */ - - samp = (uintptr_t)&apb->samp[apb->curbyte]; - nbytes = apb->nbytes - apb->curbyte; - DEBUGASSERT((samp & priv->align) == 0 && (nbytes & priv->align) == 0); - - /* Configure DMA stream */ - - stm32_dmasetup(priv->tx.dma, priv->base + STM32_SPI_DR_OFFSET, - (uint32_t)samp, nbytes / 2, priv->txccr); - - /* Increment the DMA timeout */ - - if (bfcontainer->timeout > 0) - { - timeout += bfcontainer->timeout; - } - else - { - notimeout = true; - } - - /* Add the container to the list of active DMAs */ - - sq_addlast((sq_entry_t *)bfcontainer, &priv->tx.act); - } -#if 1 /* REVISIT: Chained TX transfers */ - while (0); -#else - while (!sq_empty(&priv->tx.pend)); -#endif - - /* Sample DMA registers */ - - i2s_txdma_sample(priv, DMA_AFTER_SETUP); - - /* Start the DMA, saving the container as the current active transfer */ - - stm32_dmastart(priv->tx.dma, i2s_txdma_callback, priv, true); - - i2s_txdma_sample(priv, DMA_AFTER_START); - - /* Enable the transmitter */ - - i2s_putreg(priv, STM32_SPI_CR2_OFFSET, - i2s_getreg(priv, STM32_SPI_CR2_OFFSET) | SPI_CR2_TXDMAEN); - - /* Start a watchdog to catch DMA timeouts */ - - if (!notimeout) - { - ret = wd_start(&priv->tx.dog, timeout, - i2s_txdma_timeout, (wdparm_t)priv); - - /* Check if we have successfully started the watchdog timer. Note - * that we do nothing in the case of failure to start the timer. We - * are already committed to the DMA anyway. Let's just hope that the - * DMA does not hang. - */ - - if (ret < 0) - { - i2serr("ERROR: wd_start failed: %d\n", ret); - } - } - - return OK; -} -#endif - -/**************************************************************************** - * Name: i2s_tx_worker - * - * Description: - * TX transfer done worker - * - * Input Parameters: - * arg - the I2S device instance cast to void* - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef I2S_HAVE_TX -static void i2s_tx_worker(void *arg) -{ - struct stm32_i2s_s *priv = (struct stm32_i2s_s *)arg; - struct stm32_buffer_s *bfcontainer; - irqstate_t flags; - - DEBUGASSERT(priv); - - /* When the transfer was started, the active buffer containers were removed - * from the tx.pend queue and saved in the tx.act queue. We get here when - * the DMA is finished... either successfully, with a DMA error, or with a - * DMA timeout. - * - * In any case, the buffer containers in tx.act will be moved to the end - * of the tx.done queue and tx.act will be emptied before this worker is - * started. - * - * REVISIT: Normal DMA callback processing should restart the DMA - * immediately to avoid audio artifacts at the boundaries between DMA - * transfers. Unfortunately, the DMA callback occurs at the interrupt - * level and we cannot call dma_txsetup() from the interrupt level. - * So we have to start the next DMA here. - */ - - i2sinfo("tx.act.head=%p tx.done.head=%p\n", - priv->tx.act.head, priv->tx.done.head); - - /* Check if the DMA is IDLE */ - - if (sq_empty(&priv->tx.act)) - { -#ifdef CONFIG_STM32_I2S_DMADEBUG - bfcontainer = (struct stm32_buffer_s *)sq_peek(&priv->tx.done); - if (bfcontainer) - { - /* Dump the DMA registers */ - - i2s_txdma_sampledone(priv, bfcontainer->result); - } -#endif - - /* Then start the next DMA. This must be done with interrupts - * disabled. - */ - - flags = enter_critical_section(); - i2s_txdma_setup(priv); - leave_critical_section(flags); - } - - /* Process each buffer in the tx.done queue */ - - while (sq_peek(&priv->tx.done) != NULL) - { - /* Remove the buffer container from the tx.done queue. NOTE that - * interrupts must be enabled to do this because the tx.done queue is - * also modified from the interrupt level. - */ - - flags = enter_critical_section(); - bfcontainer = (struct stm32_buffer_s *)sq_remfirst(&priv->tx.done); - leave_critical_section(flags); - - /* Perform the TX transfer done callback */ - - DEBUGASSERT(bfcontainer && bfcontainer->callback); - bfcontainer->callback(&priv->dev, bfcontainer->apb, - bfcontainer->arg, bfcontainer->result); - - /* Release our reference on the audio buffer. This may very likely - * cause the audio buffer to be freed. - */ - - apb_free(bfcontainer->apb); - - /* And release the buffer container */ - - i2s_buf_free(priv, bfcontainer); - } -} -#endif - -/**************************************************************************** - * Name: i2s_tx_schedule - * - * Description: - * An TX DMA completion or timeout has occurred. Schedule processing on - * the working thread. - * - * Input Parameters: - * handle - The DMA handler - * arg - A pointer to the chip select struction - * result - The result of the DMA transfer - * - * Returned Value: - * None - * - * Assumptions: - * - Interrupts are disabled - * - The TX timeout has been canceled. - * - ****************************************************************************/ - -#ifdef I2S_HAVE_TX -static void i2s_tx_schedule(struct stm32_i2s_s *priv, int result) -{ - struct stm32_buffer_s *bfcontainer; - int ret; - - /* Upon entry, the transfer(s) that just completed are the ones in the - * priv->tx.act queue. NOTE: In certain conditions, this function may - * be called an additional time, hence, we can't assert this to be true. - * For example, in the case of a timeout, this function will be called by - * both indirectly via the stm32_dmastop() logic and directly via the - * i2s_txdma_timeout() logic. - */ - - /* Move all entries from the tx.act queue to the tx.done queue */ - - while (!sq_empty(&priv->tx.act)) - { - /* Remove the next buffer container from the tx.act list */ - - bfcontainer = (struct stm32_buffer_s *)sq_remfirst(&priv->tx.act); - - /* Report the result of the transfer */ - - bfcontainer->result = result; - - /* Add the completed buffer container to the tail of the tx.done - * queue - */ - - sq_addlast((sq_entry_t *)bfcontainer, &priv->tx.done); - } - - /* If the worker has completed running, then reschedule the working thread. - * REVISIT: There may be a race condition here. So we do nothing is the - * worker is not available. - */ - - if (work_available(&priv->tx.work)) - { - /* Schedule the TX DMA done processing to occur on the worker thread. */ - - ret = work_queue(HPWORK, &priv->tx.work, i2s_tx_worker, priv, 0); - if (ret != 0) - { - i2serr("ERROR: Failed to queue TX work: %d\n", ret); - } - } -} -#endif - -/**************************************************************************** - * Name: i2s_txdma_callback - * - * Description: - * This callback function is invoked at the completion of the I2S TX DMA. - * - * Input Parameters: - * handle - The DMA handler - * arg - A pointer to the chip select struction - * result - The result of the DMA transfer - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef I2S_HAVE_TX -static void i2s_txdma_callback(DMA_HANDLE handle, uint8_t result, void *arg) -{ - struct stm32_i2s_s *priv = (struct stm32_i2s_s *)arg; - DEBUGASSERT(priv != NULL); - - /* Cancel the watchdog timeout */ - - wd_cancel(&priv->tx.dog); - - /* Sample DMA registers at the time of the DMA completion */ - - i2s_txdma_sample(priv, DMA_CALLBACK); - - /* REVISIT: We would like to the next DMA started here so that we do not - * get audio glitches at the boundaries between DMA transfers. - * Unfortunately, we cannot call stm32_dmasetup() from an interrupt - * handler! - */ - - /* Then schedule completion of the transfer to occur on the worker thread */ - - i2s_tx_schedule(priv, result); -} -#endif - -/**************************************************************************** - * Name: i2s_checkwidth - * - * Description: - * Check for a valid bit width. The I2S is capable of handling most any - * bit width from 8 to 16, but the DMA logic in this driver is constrained - * to 8- and 16-bit data widths - * - * Input Parameters: - * dev - Device-specific state data - * rate - The I2S sample rate in samples (not bits) per second - * - * Returned Value: - * Returns the resulting bitrate - * - ****************************************************************************/ - -static int i2s_checkwidth(struct stm32_i2s_s *priv, int bits) -{ - /* The I2S can handle most any bit width from 8 to 32. However, the DMA - * logic here is constrained to byte, half-word, and word sizes. - */ - - switch (bits) - { - case 8: - priv->align = 0; - break; - - case 16: - priv->align = 1; - break; - - default: - i2serr("ERROR: Unsupported or invalid data width: %d\n", bits); - return (bits < 8 || bits > 16) ? -EINVAL : -ENOSYS; - } - - /* Save the new data width */ - - priv->datalen = bits; - return OK; -} - -/**************************************************************************** - * Name: stm32_i2s_rxsamplerate - * - * Description: - * Set the I2S RX sample rate. NOTE: This will have no effect if (1) the - * driver does not support an I2C receiver or if (2) the sample rate is - * driven by the I2S frame clock. This may also have unexpected side- - * effects of the RX sample is coupled with the TX sample rate. - * - * Input Parameters: - * dev - Device-specific state data - * rate - The I2S sample rate in samples (not bits) per second - * - * Returned Value: - * Returns the resulting bitrate - * - ****************************************************************************/ - -static uint32_t stm32_i2s_rxsamplerate(struct i2s_dev_s *dev, uint32_t rate) -{ -#if defined(I2S_HAVE_RX) && defined(I2S_HAVE_MCK) - struct stm32_i2s_s *priv = (struct stm32_i2s_s *)dev; - DEBUGASSERT(priv && priv->samplerate >= 0 && rate > 0); - - /* Check if the receiver is driven by the MCK */ - - if (priv->samplerate != rate) - { - /* Save the new sample rate and update the MCK divider */ - - priv->samplerate = rate; - return i2s_mckdivider(priv); - } -#endif - - return 0; -} - -/**************************************************************************** - * Name: stm32_i2s_rxdatawidth - * - * Description: - * Set the I2S RX data width. The RX bitrate is determined by - * sample_rate * data_width. - * - * Input Parameters: - * dev - Device-specific state data - * width - The I2S data with in bits. - * - * Returned Value: - * Returns the resulting bitrate - * - ****************************************************************************/ - -static uint32_t stm32_i2s_rxdatawidth(struct i2s_dev_s *dev, int bits) -{ -#ifdef I2S_HAVE_RX - struct stm32_i2s_s *priv = (struct stm32_i2s_s *)dev; - int ret; - - DEBUGASSERT(priv && bits > 1); - - /* Check if this is a bit width that we are configured to handle */ - - ret = i2s_checkwidth(priv, bits); - if (ret < 0) - { - i2serr("ERROR: i2s_checkwidth failed: %d\n", ret); - return 0; - } - - /* Update the DMA flags */ - - ret = i2s_dma_flags(priv); - if (ret < 0) - { - i2serr("ERROR: i2s_dma_flags failed: %d\n", ret); - return 0; - } - -#endif - - return 0; -} - -/**************************************************************************** - * Name: stm32_i2s_receive - * - * Description: - * Receive a block of data from I2S. - * - * Input Parameters: - * dev - Device-specific state data - * apb - A pointer to the audio buffer in which to receive data - * callback - A user provided callback function that will be called at - * the completion of the transfer. The callback will be - * performed in the context of the worker thread. - * arg - An opaque argument that will be provided to the callback - * when the transfer complete - * timeout - The timeout value to use. The transfer will be canceled - * and an ETIMEDOUT error will be reported if this timeout - * elapsed without completion of the DMA transfer. Units - * are system clock ticks. Zero means no timeout. - * - * Returned Value: - * OK on success; a negated errno value on failure. NOTE: This function - * only enqueues the transfer and returns immediately. Success here only - * means that the transfer was enqueued correctly. - * - * When the transfer is complete, a 'result' value will be provided as - * an argument to the callback function that will indicate if the transfer - * failed. - * - ****************************************************************************/ - -static int stm32_i2s_receive(struct i2s_dev_s *dev, struct ap_buffer_s *apb, - i2s_callback_t callback, void *arg, uint32_t timeout) -{ - struct stm32_i2s_s *priv = (struct stm32_i2s_s *)dev; -#ifdef I2S_HAVE_RX - struct stm32_buffer_s *bfcontainer; - irqstate_t flags; - int ret; -#endif - - DEBUGASSERT(priv && apb && ((uintptr_t)apb->samp & priv->align) == 0); - i2sinfo("apb=%p nmaxbytes=%d arg=%p timeout=%" PRId32 "\n", - apb, apb->nmaxbytes, arg, timeout); - - i2s_init_buffer(apb->samp, apb->nmaxbytes); - -#ifdef I2S_HAVE_RX - /* Allocate a buffer container in advance */ - - bfcontainer = i2s_buf_allocate(priv); - DEBUGASSERT(bfcontainer); - - /* Get exclusive access to the I2S driver data */ - - ret = nxmutex_lock(&priv->lock); - if (ret < 0) - { - goto errout_with_buf; - } - - /* Has the RX channel been enabled? */ - - if (!priv->rxenab) - { - i2serr("ERROR: I2S%d has no receiver\n", priv->i2sno); - ret = -EAGAIN; - goto errout_with_lock; - } - - /* Add a reference to the audio buffer */ - - apb_reference(apb); - - /* Initialize the buffer container structure */ - - bfcontainer->callback = (void *)callback; - bfcontainer->timeout = timeout; - bfcontainer->arg = arg; - bfcontainer->apb = apb; - bfcontainer->result = -EBUSY; - - /* Add the buffer container to the end of the RX pending queue */ - - flags = enter_critical_section(); - sq_addlast((sq_entry_t *)bfcontainer, &priv->rx.pend); - - /* Then start the next transfer. If there is already a transfer in - * progress, then this will do nothing. - */ - - ret = i2s_rxdma_setup(priv); - DEBUGASSERT(ret == OK); - leave_critical_section(flags); - nxmutex_unlock(&priv->lock); - return OK; - -errout_with_lock: - nxmutex_unlock(&priv->lock); - -errout_with_buf: - i2s_buf_free(priv, bfcontainer); - return ret; - -#else - i2serr("ERROR: I2S%d has no receiver\n", priv->i2sno); - UNUSED(priv); - return -ENOSYS; -#endif -} - -static int stm32_i2s_roundf(float num) -{ - if (((int)(num + 0.5f)) > num) - { - return num + 1; - } - - return num; -} - -/**************************************************************************** - * Name: stm32_i2s_txsamplerate - * - * Description: - * Set the I2S TX sample rate. NOTE: This will have no effect if (1) the - * driver does not support an I2S transmitter or if (2) the sample rate is - * driven by the I2S frame clock. This may also have unexpected side- - * effects of the TX sample is coupled with the RX sample rate. - * - * Input Parameters: - * dev - Device-specific state data - * rate - The I2S sample rate in samples (not bits) per second - * - * Returned Value: - * Returns the resulting bitrate - * - ****************************************************************************/ - -static uint32_t stm32_i2s_txsamplerate(struct i2s_dev_s *dev, uint32_t rate) -{ -#if defined(I2S_HAVE_TX) && defined(I2S_HAVE_MCK) - struct stm32_i2s_s *priv = (struct stm32_i2s_s *)dev; - - DEBUGASSERT(priv && priv->samplerate >= 0 && rate > 0); - - /* Check if the receiver is driven by the MCK/2 */ - - if (priv->samplerate != rate) - { - /* Save the new sample rate and update the MCK/2 divider */ - - priv->samplerate = rate; - return i2s_mckdivider(priv); - } -#endif - - return 0; -} - -/**************************************************************************** - * Name: stm32_i2s_txdatawidth - * - * Description: - * Set the I2S TX data width. The TX bitrate is determined by - * sample_rate * data_width. - * - * Input Parameters: - * dev - Device-specific state data - * width - The I2S data with in bits. - * - * Returned Value: - * Returns the resulting bitrate - * - ****************************************************************************/ - -static uint32_t stm32_i2s_txdatawidth(struct i2s_dev_s *dev, int bits) -{ -#ifdef I2S_HAVE_TX - struct stm32_i2s_s *priv = (struct stm32_i2s_s *)dev; - int ret; - - i2sinfo("Data width bits of tx = %d\n", bits); - DEBUGASSERT(priv && bits > 1); - - /* Check if this is a bit width that we are configured to handle */ - - ret = i2s_checkwidth(priv, bits); - if (ret < 0) - { - i2serr("ERROR: i2s_checkwidth failed: %d\n", ret); - return 0; - } - - /* Update the DMA flags */ - - ret = i2s_dma_flags(priv); - if (ret < 0) - { - i2serr("ERROR: i2s_dma_flags failed: %d\n", ret); - return 0; - } -#endif - - return 0; -} - -/**************************************************************************** - * Name: stm32_i2s_send - * - * Description: - * Send a block of data on I2S. - * - * Input Parameters: - * dev - Device-specific state data - * apb - A pointer to the audio buffer from which to send data - * callback - A user provided callback function that will be called at - * the completion of the transfer. The callback will be - * performed in the context of the worker thread. - * arg - An opaque argument that will be provided to the callback - * when the transfer complete - * timeout - The timeout value to use. The transfer will be canceled - * and an ETIMEDOUT error will be reported if this timeout - * elapsed without completion of the DMA transfer. Units - * are system clock ticks. Zero means no timeout. - * - * Returned Value: - * OK on success; a negated errno value on failure. NOTE: This function - * only enqueues the transfer and returns immediately. Success here only - * means that the transfer was enqueued correctly. - * - * When the transfer is complete, a 'result' value will be provided as - * an argument to the callback function that will indicate if the transfer - * failed. - * - ****************************************************************************/ - -static int stm32_i2s_send(struct i2s_dev_s *dev, struct ap_buffer_s *apb, - i2s_callback_t callback, void *arg, uint32_t timeout) -{ - struct stm32_i2s_s *priv = (struct stm32_i2s_s *)dev; -#ifdef I2S_HAVE_TX - struct stm32_buffer_s *bfcontainer; - irqstate_t flags; - int ret; -#endif - - /* Make sure that we have valid pointers that that the data has uint32_t - * alignment. - */ - - DEBUGASSERT(priv && apb); - i2sinfo("apb=%p nbytes=%d arg=%p timeout=%" PRId32 "\n", - apb, apb->nbytes - apb->curbyte, arg, timeout); - - i2s_dump_buffer("Sending", &apb->samp[apb->curbyte], - apb->nbytes - apb->curbyte); - DEBUGASSERT(((uintptr_t)&apb->samp[apb->curbyte] & priv->align) == 0); - -#ifdef I2S_HAVE_TX - /* Allocate a buffer container in advance */ - - bfcontainer = i2s_buf_allocate(priv); - DEBUGASSERT(bfcontainer); - - /* Get exclusive access to the I2S driver data */ - - ret = nxmutex_lock(&priv->lock); - if (ret < 0) - { - goto errout_with_buf; - } - - /* Has the TX channel been enabled? */ - - if (!priv->txenab) - { - i2serr("ERROR: I2S%d has no transmitter\n", priv->i2sno); - ret = -EAGAIN; - goto errout_with_lock; - } - - /* Add a reference to the audio buffer */ - - apb_reference(apb); - - /* Initialize the buffer container structure */ - - bfcontainer->callback = (void *)callback; - bfcontainer->timeout = timeout; - bfcontainer->arg = arg; - bfcontainer->apb = apb; - bfcontainer->result = -EBUSY; - - /* Add the buffer container to the end of the TX pending queue */ - - flags = enter_critical_section(); - sq_addlast((sq_entry_t *)bfcontainer, &priv->tx.pend); - - /* Then start the next transfer. If there is already a transfer in - * progress, then this will do nothing. - */ - - ret = i2s_txdma_setup(priv); - DEBUGASSERT(ret == OK); - leave_critical_section(flags); - nxmutex_unlock(&priv->lock); - return OK; - -errout_with_lock: - nxmutex_unlock(&priv->lock); - -errout_with_buf: - i2s_buf_free(priv, bfcontainer); - return ret; - -#else - i2serr("ERROR: I2S%d has no transmitter\n", priv->i2sno); - UNUSED(priv); - return -ENOSYS; -#endif -} - -/**************************************************************************** - * Name: i2s_mckdivider - * - * Description: - * Setup the MCK divider based on the currently selected data width and - * the sample rate - * - * Input Parameters: - * priv - I2C device structure (only the sample rate and data length is - * needed at this point). - * - * Returned Value: - * The current bitrate - * - ****************************************************************************/ - -static uint32_t i2s_mckdivider(struct stm32_i2s_s *priv) -{ -#ifdef I2S_HAVE_MCK - uint32_t bitrate; - uint32_t regval; - - uint16_t pllr = 5; - uint16_t plln = 256; - uint16_t div = 12; - uint16_t odd = 1; - - DEBUGASSERT(priv && priv->samplerate >= 0 && priv->datalen > 0); - - /* A zero sample rate means to disable the MCK/2 clock */ - - if (priv->samplerate == 0) - { - bitrate = 0; - regval = 0; - } - else - { - int R; - int n; - int od; - int napprox; - int diff; - int diff_min = 500000000; - - for (od = 0; od <= 1; ++od) - { - for (R = 2; R <= 7; ++R) - { - for (n = 2; n <= 256; ++n) - { - napprox = stm32_i2s_roundf(priv->samplerate / 1000000.0f * - (8 * 32 * R * (2 * n + od))); - if ((napprox > 432) || (napprox < 50)) - { - continue; - } - - diff = abs(priv->samplerate - 1000000 * napprox / - (8 * 32 * R * (2 * n + od))); - if (diff_min > diff) - { - diff_min = diff; - plln = napprox; - pllr = R; - div = n; - odd = od; - } - } - } - } - - /* Calculate the new bitrate in Hz */ - - bitrate = priv->samplerate * priv->datalen; - } - - /* Configure MCK divider */ - - /* Disable I2S */ - - i2s_putreg(priv, STM32_SPI_I2SCFGR_OFFSET, 0); - - /* I2S clock configuration */ - - putreg32((getreg32(STM32_RCC_CR) & (~RCC_CR_PLLI2SON)), STM32_RCC_CR); - - /* PLLI2S clock used as I2S clock source */ - - putreg32(((getreg32(STM32_RCC_CFGR)) & (~RCC_CFGR_I2SSRC)), - STM32_RCC_CFGR); - regval = (pllr << 28) | (plln << 6); - putreg32(regval, STM32_RCC_PLLI2SCFGR); - - /* Enable PLLI2S and wait until it is ready */ - - putreg32((getreg32(STM32_RCC_CR) | RCC_CR_PLLI2SON), STM32_RCC_CR); - while (!(getreg32(STM32_RCC_CR) & RCC_CR_PLLI2SRDY)); - - i2s_putreg(priv, STM32_SPI_I2SPR_OFFSET, - div | (odd << 8) | SPI_I2SPR_MCKOE); - i2s_putreg(priv, STM32_SPI_I2SCFGR_OFFSET, - SPI_I2SCFGR_I2SMOD | SPI_I2SCFGR_I2SCFG_MTX | SPI_I2SCFGR_I2SE); - -#if 0 - putreg32((getreg32(STM32_DMA1_HIFCR) | DMA_HIFCR_CTCIF7), - STM32_DMA1_HIFCR); -#endif - - putreg32((getreg32(STM32_DMA1_HIFCR) | 0x80000000), STM32_DMA1_HIFCR); - - return bitrate; -#else - return 0; -#endif -} - -/**************************************************************************** - * Name: i2s_dma_flags - * - * Description: - * Determine DMA FLAGS based on PID and data width - * - * Input Parameters: - * priv - Partially initialized I2C device structure. - * - * Returned Value: - * OK on success; a negated errno value on failure - * - ****************************************************************************/ - -static int i2s_dma_flags(struct stm32_i2s_s *priv) -{ - switch (priv->datalen) - { - case 8: - - /* Reconfigure the RX DMA (and TX DMA if applicable) */ - - priv->rxccr = SPI_RXDMA8_CONFIG; - priv->txccr = SPI_TXDMA8_CONFIG; - break; - - case 16: - priv->rxccr = SPI_RXDMA16_CONFIG; - priv->txccr = SPI_TXDMA16_CONFIG; - break; - - default: - i2serr("ERROR: Unsupported data width: %d\n", priv->datalen); - return -ENOSYS; - } - - return OK; -} - -/**************************************************************************** - * Name: i2s_dma_allocate - * - * Description: - * Allocate I2S DMA channels - * - * Input Parameters: - * priv - Partially initialized I2S device structure. This function - * will complete the DMA specific portions of the initialization - * - * Returned Value: - * OK on success; A negated errno value on failure. - * - ****************************************************************************/ - -static int i2s_dma_allocate(struct stm32_i2s_s *priv) -{ - int ret; - - /* Get the DMA flags for this channel */ - - ret = i2s_dma_flags(priv); - if (ret < 0) - { - i2serr("ERROR: i2s_dma_flags failed: %d\n", ret); - return ret; - } - - /* Allocate DMA channels. These allocations exploit that fact that - * I2S2 is managed by DMA1 and I2S3 is managed by DMA2. Hence, - * the I2S number (i2sno) is the same as the DMA number. - */ - -#ifdef I2S_HAVE_RX - if (priv->rxenab) - { - /* Allocate an RX DMA channel */ - - priv->rx.dma = stm32_dmachannel(DMACHAN_I2S3_RX); - if (!priv->rx.dma) - { - i2serr("ERROR: Failed to allocate the RX DMA channel\n"); - goto errout; - } - } -#endif - -#ifdef I2S_HAVE_TX - if (priv->txenab) - { - /* Allocate a TX DMA channel */ - - priv->tx.dma = stm32_dmachannel(DMACHAN_I2S3_TX); - if (!priv->tx.dma) - { - i2serr("ERROR: Failed to allocate the TX DMA channel\n"); - goto errout; - } - } -#endif - - /* Success exit */ - - return OK; - - /* Error exit */ - -errout: - i2s_dma_free(priv); - return -ENOMEM; -} - -/**************************************************************************** - * Name: i2s_dma_free - * - * Description: - * Release DMA-related resources allocated by i2s_dma_allocate() - * - * Input Parameters: - * priv - Partially initialized I2C device structure. - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void i2s_dma_free(struct stm32_i2s_s *priv) -{ -#ifdef I2S_HAVE_TX - wd_cancel(&priv->tx.dog); - if (priv->tx.dma) - { - stm32_dmafree(priv->tx.dma); - } -#endif - -#ifdef I2S_HAVE_RX - wd_cancel(&priv->rx.dog); - if (priv->rx.dma) - { - stm32_dmafree(priv->rx.dma); - } -#endif -} - -/**************************************************************************** - * Name: i2s2_configure - * - * Description: - * Configure I2S2 - * - * Input Parameters: - * priv - Partially initialized I2C device structure. These functions - * will complete the I2S specific portions of the initialization - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_I2S2 -static void i2s2_configure(struct stm32_i2s_s *priv) -{ - /* Configure multiplexed pins as connected on the board. Chip - * select pins must be selected by board-specific logic. - */ - - priv->base = STM32_I2S2_BASE; - -#ifdef CONFIG_STM32_I2S2_RX - priv->rxenab = true; - - if (!priv->initialized) - { - /* Configure I2S2 pins: MCK, SD, CK, WS */ - - stm32_configgpio(GPIO_I2S2_MCK); - stm32_configgpio(GPIO_I2S2_SD); - stm32_configgpio(GPIO_I2S2_CK); - stm32_configgpio(GPIO_I2S2_WS); - priv->initialized = true; - } -#endif /* CONFIG_STM32_I2S2_RX */ - -#ifdef CONFIG_STM32_I2S2_TX - priv->txenab = true; - - /* Only configure if the port is not already configured */ - - if (!priv->initialized) - { - /* Configure I2S2 pins: MCK, SD, CK, WS */ - - stm32_configgpio(GPIO_I2S2_MCK); - stm32_configgpio(GPIO_I2S2_SD); - stm32_configgpio(GPIO_I2S2_CK); - stm32_configgpio(GPIO_I2S2_WS); - priv->initialized = true; - } -#endif /* CONFIG_STM32_I2S2_TX */ - - /* Configure driver state specific to this I2S peripheral */ - - priv->datalen = CONFIG_STM32_I2S2_DATALEN; -#ifdef CONFIG_DEBUG - priv->align = STM32_I2S2_DATAMASK; -#endif -} -#endif /* CONFIG_STM32_I2S2 */ - -/**************************************************************************** - * Name: i2s3_configure - * - * Description: - * Configure I2S3 - * - * Input Parameters: - * priv - Partially initialized I2C device structure. These functions - * will complete the I2S specific portions of the initialization - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_I2S3 -static void i2s3_configure(struct stm32_i2s_s *priv) -{ - /* Configure multiplexed pins as connected on the board. Chip - * select pins must be selected by board-specific logic. - */ - - priv->base = STM32_I2S3_BASE; - -#ifdef CONFIG_STM32_I2S3_RX - priv->rxenab = true; - - if (!priv->initialized) - { - /* Configure I2S3 pins: MCK, SD, CK, WS */ - - stm32_configgpio(GPIO_I2S3_MCK); - stm32_configgpio(GPIO_I2S3_SD); - stm32_configgpio(GPIO_I2S3_CK); - stm32_configgpio(GPIO_I2S3_WS); - priv->initialized = true; - } -#endif /* CONFIG_STM32_I2S3_RX */ - -#ifdef CONFIG_STM32_I2S3_TX - priv->txenab = true; - - /* Only configure if the port is not already configured */ - - if (!priv->initialized) - { - /* Configure I2S3 pins: MCK, SD, CK, WS */ - - stm32_configgpio(GPIO_I2S3_MCK); - stm32_configgpio(GPIO_I2S3_SD); - stm32_configgpio(GPIO_I2S3_CK); - stm32_configgpio(GPIO_I2S3_WS); - priv->initialized = true; - } -#endif /* CONFIG_STM32_I2S3_TX */ - - /* Configure driver state specific to this I2S peripheral */ - - priv->datalen = CONFIG_STM32_I2S3_DATALEN; -#ifdef CONFIG_DEBUG - priv->align = STM32_I2S3_DATAMASK; -#endif -} -#endif /* CONFIG_STM32_I2S3 */ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_i2sbus_initialize - * - * Description: - * Initialize the selected i2S port - * - * Input Parameters: - * Port number (for hardware that has multiple I2S interfaces) - * - * Returned Value: - * Valid I2S device structure reference on success; a NULL on failure - * - ****************************************************************************/ - -struct i2s_dev_s *stm32_i2sbus_initialize(int port) -{ - struct stm32_i2s_s *priv = NULL; - irqstate_t flags; - int ret; - - /* The support STM32 parts have only a single I2S port */ - - i2sinfo("port: %d\n", port); - - /* Allocate a new state structure for this chip select. NOTE that there - * is no protection if the same chip select is used in two different - * chip select structures. - */ - - priv = kmm_zalloc(sizeof(struct stm32_i2s_s)); - if (!priv) - { - i2serr("ERROR: Failed to allocate a chip select structure\n"); - return NULL; - } - - /* Set up the initial state for this chip select structure. Other fields - * were zeroed by kmm_zalloc(). - */ - - /* Initialize the common parts for the I2S device structure */ - - nxmutex_init(&priv->lock); - priv->dev.ops = &g_i2sops; - priv->i2sno = port; - - /* Initialize buffering */ - - i2s_buf_initialize(priv); - - flags = enter_critical_section(); - -#ifdef CONFIG_STM32_I2S2 - if (port == 2) - { - /* Select I2S2 */ - - i2s2_configure(priv); - } - else -#endif -#ifdef CONFIG_STM32_I2S3 - if (port == 3) - { - /* Select I2S3 */ - - i2s3_configure(priv); - } - else -#endif - { - i2serr("ERROR: Unsupported I2S port: %d\n", port); - leave_critical_section(flags); - return NULL; - } - - /* Allocate DMA channels */ - - ret = i2s_dma_allocate(priv); - if (ret < 0) - { - goto errout_with_alloc; - } - - leave_critical_section(flags); - i2s_dump_regs(priv, "After initialization"); - - /* Success exit */ - - return &priv->dev; - - /* Failure exits */ - -errout_with_alloc: - leave_critical_section(flags); - nxmutex_destroy(&priv->lock); - nxsem_destroy(&priv->bufsem); - kmm_free(priv); - return NULL; -} -#endif /* I2S_HAVE_RX || I2S_HAVE_TX */ - -#endif /* CONFIG_STM32_I2S2 || CONFIG_STM32_I2S3 */ diff --git a/arch/arm/src/stm32/stm32_idle.c b/arch/arm/src/stm32/stm32_idle.c deleted file mode 100644 index 22f559f276752..0000000000000 --- a/arch/arm/src/stm32/stm32_idle.c +++ /dev/null @@ -1,197 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_idle.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include -#include - -#include -#include -#include - -#include - -#include "chip.h" -#include "stm32_pm.h" -#include "arm_internal.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Does the board support an IDLE LED to indicate that the board is in the - * IDLE state? - */ - -#if defined(CONFIG_ARCH_LEDS) && defined(LED_IDLE) -# define BEGIN_IDLE() board_autoled_on(LED_IDLE) -# define END_IDLE() board_autoled_off(LED_IDLE) -#else -# define BEGIN_IDLE() -# define END_IDLE() -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: up_idlepm - * - * Description: - * Perform IDLE state power management. - * - ****************************************************************************/ - -#ifdef CONFIG_PM -static void up_idlepm(void) -{ - static enum pm_state_e oldstate = PM_NORMAL; - enum pm_state_e newstate; - irqstate_t flags; - int ret; - - /* Decide, which power saving level can be obtained */ - - newstate = pm_checkstate(PM_IDLE_DOMAIN); - - /* Check for state changes */ - - if (newstate != oldstate) - { - flags = enter_critical_section(); - - /* Perform board-specific, state-dependent logic here */ - - _info("newstate= %d oldstate=%d\n", newstate, oldstate); - - /* Then force the global state change */ - - ret = pm_changestate(PM_IDLE_DOMAIN, newstate); - if (ret < 0) - { - /* The new state change failed, revert to the preceding state */ - - pm_changestate(PM_IDLE_DOMAIN, oldstate); - } - else - { - /* Save the new state */ - - oldstate = newstate; - } - - /* MCU-specific power management logic */ - - switch (newstate) - { - case PM_NORMAL: - break; - - case PM_IDLE: - break; - - case PM_STANDBY: - stm32_pmstop(true); - break; - - case PM_SLEEP: - stm32_pmstandby(); - break; - - default: - break; - } - - leave_critical_section(flags); - } -} -#else -# define up_idlepm() -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: up_idle - * - * Description: - * up_idle() is the logic that will be executed when there is no other - * ready-to-run task. This is processor idle time and will continue until - * some interrupt occurs to cause a context switch from the idle task. - * - * Processing in this state may be processor-specific. e.g., this is where - * power management operations might be performed. - * - ****************************************************************************/ - -void up_idle(void) -{ -#if defined(CONFIG_SUPPRESS_INTERRUPTS) || defined(CONFIG_SUPPRESS_TIMER_INTS) - /* If the system is idle and there are no timer interrupts, then process - * "fake" timer interrupts. Hopefully, something will wake up. - */ - - nxsched_process_timer(); -#else - - /* Perform IDLE mode power management */ - - up_idlepm(); - - /* Sleep until an interrupt occurs to save power. - * - * NOTE: There is an STM32F107 errata that is fixed by the following - * workaround: - * - * "2.17.11 Ethernet DMA not working after WFI/WFE instruction - * Description - * If a WFI/WFE instruction is executed to put the system in sleep mode - * while the Ethernet MAC master clock on the AHB bus matrix is ON and - * all remaining masters clocks are OFF, the Ethernet DMA will be not - * able to perform any AHB master accesses during sleep mode." - * - * Workaround - * Enable DMA1 or DMA2 clocks in the RCC_AHBENR register before - * executing the WFI/WFE instruction." - * - * Here the workaround is just to avoid SLEEP mode for the connectivity - * line parts if Ethernet is enabled. The errate recommends a more - * general solution: Enabling DMA1/2 clocking in stm32f10xx_rcc.c if the - * STM32107 Ethernet peripheral is enabled. - */ - -#if !defined(CONFIG_STM32_CONNECTIVITYLINE) || !defined(CONFIG_STM32_ETHMAC) -#if !(defined(CONFIG_DEBUG_SYMBOLS) && defined(CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG)) - BEGIN_IDLE(); - asm("WFI"); - END_IDLE(); -#endif -#endif -#endif -} diff --git a/arch/arm/src/stm32/stm32_irq.c b/arch/arm/src/stm32/stm32_irq.c deleted file mode 100644 index 57ed8ba1a4406..0000000000000 --- a/arch/arm/src/stm32/stm32_irq.c +++ /dev/null @@ -1,542 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_irq.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include -#include -#include -#include - -#include "nvic.h" -#ifdef CONFIG_ARCH_RAMVECTORS -# include "ram_vectors.h" -#endif -#include "arm_internal.h" -#include "stm32.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Get a 32-bit version of the default priority */ - -#define DEFPRIORITY32 \ - (NVIC_SYSH_PRIORITY_DEFAULT << 24 | \ - NVIC_SYSH_PRIORITY_DEFAULT << 16 | \ - NVIC_SYSH_PRIORITY_DEFAULT << 8 | \ - NVIC_SYSH_PRIORITY_DEFAULT) - -/* Given the address of a NVIC ENABLE register, this is the offset to - * the corresponding CLEAR ENABLE register. - */ - -#define NVIC_ENA_OFFSET (0) -#define NVIC_CLRENA_OFFSET (NVIC_IRQ0_31_CLEAR - NVIC_IRQ0_31_ENABLE) - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_dumpnvic - * - * Description: - * Dump some interesting NVIC registers - * - ****************************************************************************/ - -#if defined(CONFIG_DEBUG_IRQ_INFO) -static void stm32_dumpnvic(const char *msg, int irq) -{ - irqstate_t flags; - unsigned int i; - unsigned int j; - unsigned int nregs; - unsigned int off; - unsigned int nintr; - unsigned int nreg_per_line = 4; - unsigned int nenable_per_reg = 32; - unsigned int nenable_per_line = nenable_per_reg * nreg_per_line; - unsigned int nprio_per_reg = 4; - unsigned int nprio_per_line = nprio_per_reg * nreg_per_line; - char buf[64]; - - flags = enter_critical_section(); - nintr = STM32_IRQ_NEXTINTS; - - irqinfo("NVIC (%s, irq=%d):\n", msg, irq); - irqinfo(" INTCTRL: %08" PRIx32 " VECTAB: %08" PRIx32 "\n", - getreg32(NVIC_INTCTRL), getreg32(NVIC_VECTAB)); -#if 0 - irqinfo(" SYSH ENABLE MEMFAULT: %08" PRIx32 " BUSFAULT: %08" - PRIx32 " USGFAULT: %08" PRIx32 " SYSTICK: %08" PRIx32 "\n", - getreg32(NVIC_SYSHCON_MEMFAULTENA), - getreg32(NVIC_SYSHCON_BUSFAULTENA), - getreg32(NVIC_SYSHCON_USGFAULTENA), - getreg32(NVIC_SYSTICK_CTRL_ENABLE)); -#endif - for (i = 0; i < nintr; i += nenable_per_line) - { - if (!i) - { - off = snprintf(buf, sizeof(buf), " IRQ ENAB 0:"); - } - else - { - off = snprintf(buf, sizeof(buf), " %3u:", i); - } - - nregs = nintr - i; - if (nregs > nenable_per_line) - { - nregs = nenable_per_line; - } - - for (j = 0; j < nregs; j += nenable_per_reg) - { - off += snprintf(&buf[off], sizeof(buf)-off, " %08" PRIx32, - getreg32(NVIC_IRQ_ENABLE(i + j))); - } - - irqinfo("%s\n", buf); - } - - irqinfo(" SYSH_PRIO: %08" PRIx32 " %08" PRIx32 " %08" PRIx32 "\n", - getreg32(NVIC_SYSH4_7_PRIORITY), - getreg32(NVIC_SYSH8_11_PRIORITY), - getreg32(NVIC_SYSH12_15_PRIORITY)); - - for (i = 0; - i < nintr; - i += nprio_per_line) - { - if (!i) - { - off = snprintf(buf, sizeof(buf), " IRQ PRIO 0:"); - } - else - { - off = snprintf(buf, sizeof(buf), " %3u:", i); - } - - nregs = nintr - i; - if (nregs > nprio_per_line) - { - nregs = nprio_per_line; - } - - for (j = 0; j < nregs; j += nprio_per_reg) - { - off += snprintf(&buf[off], sizeof(buf)-off, " %08" PRIx32, - getreg32(NVIC_IRQ_PRIORITY(i + j))); - } - - irqinfo("%s\n", buf); - } - - leave_critical_section(flags); -} -#else -# define stm32_dumpnvic(msg, irq) -#endif - -/**************************************************************************** - * Name: stm32_nmi, stm32_pendsv, stm32_pendsv, stm32_reserved - * - * Description: - * Handlers for various exceptions. None are handled and all are fatal - * error conditions. The only advantage these provided over the default - * unexpected interrupt handler is that they provide a diagnostic output. - * - ****************************************************************************/ - -#ifdef CONFIG_DEBUG_FEATURES -static int stm32_nmi(int irq, void *context, void *arg) -{ - up_irq_save(); - _err("PANIC!!! NMI received\n"); - PANIC(); - return 0; -} - -static int stm32_pendsv(int irq, void *context, void *arg) -{ -#ifndef CONFIG_ARCH_HIPRI_INTERRUPT - up_irq_save(); - _err("PANIC!!! PendSV received\n"); - PANIC(); -#endif - return 0; -} - -static int stm32_reserved(int irq, void *context, void *arg) -{ - up_irq_save(); - _err("PANIC!!! Reserved interrupt\n"); - PANIC(); - return 0; -} -#endif - -/**************************************************************************** - * Name: stm32_prioritize_syscall - * - * Description: - * Set the priority of an exception. This function may be needed - * internally even if support for prioritized interrupts is not enabled. - * - ****************************************************************************/ - -static inline void stm32_prioritize_syscall(int priority) -{ - uint32_t regval; - - /* SVCALL is system handler 11 */ - - regval = getreg32(NVIC_SYSH8_11_PRIORITY); - regval &= ~NVIC_SYSH_PRIORITY_PR11_MASK; - regval |= (priority << NVIC_SYSH_PRIORITY_PR11_SHIFT); - putreg32(regval, NVIC_SYSH8_11_PRIORITY); -} - -/**************************************************************************** - * Name: stm32_irqinfo - * - * Description: - * Given an IRQ number, provide the register and bit setting to enable or - * disable the irq. - * - ****************************************************************************/ - -static int stm32_irqinfo(int irq, uintptr_t *regaddr, uint32_t *bit, - uintptr_t offset) -{ - int n; - - DEBUGASSERT(irq >= STM32_IRQ_NMI && irq < NR_IRQS); - - /* Check for external interrupt */ - - if (irq >= STM32_IRQ_FIRST) - { - n = irq - STM32_IRQ_FIRST; - *regaddr = NVIC_IRQ_ENABLE(n) + offset; - *bit = (uint32_t)1 << (n & 0x1f); - } - - /* Handle processor exceptions. Only a few can be disabled */ - - else - { - *regaddr = NVIC_SYSHCON; - if (irq == STM32_IRQ_MEMFAULT) - { - *bit = NVIC_SYSHCON_MEMFAULTENA; - } - else if (irq == STM32_IRQ_BUSFAULT) - { - *bit = NVIC_SYSHCON_BUSFAULTENA; - } - else if (irq == STM32_IRQ_USAGEFAULT) - { - *bit = NVIC_SYSHCON_USGFAULTENA; - } - else if (irq == STM32_IRQ_SYSTICK) - { - *regaddr = NVIC_SYSTICK_CTRL; - *bit = NVIC_SYSTICK_CTRL_ENABLE; - } - else - { - return ERROR; /* Invalid or unsupported exception */ - } - } - - return OK; -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: up_irqinitialize - ****************************************************************************/ - -void up_irqinitialize(void) -{ - uint32_t regaddr; - int num_priority_registers; - int i; - - /* Disable all interrupts */ - - for (i = 0; i < NR_IRQS - STM32_IRQ_FIRST; i += 32) - { - putreg32(0xffffffff, NVIC_IRQ_CLEAR(i)); - } - - /* The standard location for the vector table is at the beginning of FLASH - * at address 0x0800:0000. If we are using the STMicro DFU bootloader, - * then the vector table will be offset to a different location in FLASH - * and we will need to set the NVIC vector location to this alternative - * location. - */ - -#if defined(__ICCARM__) - putreg32((uint32_t)__vector_table, NVIC_VECTAB); -#else - putreg32((uint32_t)_vectors, NVIC_VECTAB); -#endif - -#ifdef CONFIG_ARCH_RAMVECTORS - /* If CONFIG_ARCH_RAMVECTORS is defined, then we are using a RAM-based - * vector table that requires special initialization. - */ - - arm_ramvec_initialize(); -#endif - - /* Set all interrupts (and exceptions) to the default priority */ - - putreg32(DEFPRIORITY32, NVIC_SYSH4_7_PRIORITY); - putreg32(DEFPRIORITY32, NVIC_SYSH8_11_PRIORITY); - putreg32(DEFPRIORITY32, NVIC_SYSH12_15_PRIORITY); - - /* The NVIC ICTR register (bits 0-4) holds the number of interrupt - * lines that the NVIC supports: - * - * 0 -> 32 interrupt lines, 8 priority registers - * 1 -> 64 " " " ", 16 priority registers - * 2 -> 96 " " " ", 32 priority registers - * ... - */ - - num_priority_registers = (getreg32(NVIC_ICTR) + 1) * 8; - - /* Now set all of the interrupt lines to the default priority */ - - regaddr = NVIC_IRQ0_3_PRIORITY; - while (num_priority_registers--) - { - putreg32(DEFPRIORITY32, regaddr); - regaddr += 4; - } - - /* Attach the SVCall and Hard Fault exception handlers. The SVCall - * exception is used for performing context switches; The Hard Fault - * must also be caught because a SVCall may show up as a Hard Fault - * under certain conditions. - */ - - irq_attach(STM32_IRQ_SVCALL, arm_svcall, NULL); - irq_attach(STM32_IRQ_HARDFAULT, arm_hardfault, NULL); - - /* Set the priority of the SVCall interrupt */ - -#ifdef CONFIG_ARCH_IRQPRIO - /* up_prioritize_irq(STM32_IRQ_PENDSV, NVIC_SYSH_PRIORITY_MIN); */ -#endif - - stm32_prioritize_syscall(NVIC_SYSH_SVCALL_PRIORITY); - - /* If the MPU is enabled, then attach and enable the Memory Management - * Fault handler. - */ - -#ifdef CONFIG_ARM_MPU - irq_attach(STM32_IRQ_MEMFAULT, arm_memfault, NULL); - up_enable_irq(STM32_IRQ_MEMFAULT); -#endif - -#if defined(CONFIG_RTC) && !defined(CONFIG_RTC_EXTERNAL) - /* RTC was initialized earlier but IRQs weren't ready at that time */ - - stm32_rtc_irqinitialize(); -#endif - - /* Attach all other processor exceptions (except reset and sys tick) */ - -#ifdef CONFIG_DEBUG_FEATURES - irq_attach(STM32_IRQ_NMI, stm32_nmi, NULL); -#ifndef CONFIG_ARM_MPU - irq_attach(STM32_IRQ_MEMFAULT, arm_memfault, NULL); -#endif - irq_attach(STM32_IRQ_BUSFAULT, arm_busfault, NULL); - irq_attach(STM32_IRQ_USAGEFAULT, arm_usagefault, NULL); - irq_attach(STM32_IRQ_PENDSV, stm32_pendsv, NULL); - arm_enable_dbgmonitor(); - irq_attach(STM32_IRQ_DBGMONITOR, arm_dbgmonitor, NULL); - irq_attach(STM32_IRQ_RESERVED, stm32_reserved, NULL); -#endif - - stm32_dumpnvic("initial", NR_IRQS); - -#ifndef CONFIG_SUPPRESS_INTERRUPTS - - /* And finally, enable interrupts */ - - arm_color_intstack(); - up_irq_enable(); -#endif -} - -/**************************************************************************** - * Name: up_disable_irq - * - * Description: - * Disable the IRQ specified by 'irq' - * - ****************************************************************************/ - -void up_disable_irq(int irq) -{ - uintptr_t regaddr; - uint32_t regval; - uint32_t bit; - - if (stm32_irqinfo(irq, ®addr, &bit, NVIC_CLRENA_OFFSET) == 0) - { - /* Modify the appropriate bit in the register to disable the interrupt. - * For normal interrupts, we need to set the bit in the associated - * Interrupt Clear Enable register. For other exceptions, we need to - * clear the bit in the System Handler Control and State Register. - */ - - if (irq >= STM32_IRQ_FIRST) - { - putreg32(bit, regaddr); - } - else - { - regval = getreg32(regaddr); - regval &= ~bit; - putreg32(regval, regaddr); - } - } -} - -/**************************************************************************** - * Name: up_enable_irq - * - * Description: - * Enable the IRQ specified by 'irq' - * - ****************************************************************************/ - -void up_enable_irq(int irq) -{ - uintptr_t regaddr; - uint32_t regval; - uint32_t bit; - - if (stm32_irqinfo(irq, ®addr, &bit, NVIC_ENA_OFFSET) == 0) - { - /* Modify the appropriate bit in the register to enable the interrupt. - * For normal interrupts, we need to set the bit in the associated - * Interrupt Set Enable register. For other exceptions, we need to - * set the bit in the System Handler Control and State Register. - */ - - if (irq >= STM32_IRQ_FIRST) - { - putreg32(bit, regaddr); - } - else - { - regval = getreg32(regaddr); - regval |= bit; - putreg32(regval, regaddr); - } - } -} - -/**************************************************************************** - * Name: arm_ack_irq - * - * Description: - * Acknowledge the IRQ - * - ****************************************************************************/ - -void arm_ack_irq(int irq) -{ -} - -/**************************************************************************** - * Name: up_prioritize_irq - * - * Description: - * Set the priority of an IRQ. - * - * Since this API is not supported on all architectures, it should be - * avoided in common implementations where possible. - * - ****************************************************************************/ - -#ifdef CONFIG_ARCH_IRQPRIO -int up_prioritize_irq(int irq, int priority) -{ - uint32_t regaddr; - uint32_t regval; - int shift; - - DEBUGASSERT(irq >= STM32_IRQ_MEMFAULT && irq < NR_IRQS && - (unsigned)priority <= NVIC_SYSH_PRIORITY_MIN); - - if (irq < STM32_IRQ_FIRST) - { - /* NVIC_SYSH_PRIORITY() maps {0..15} to one of three priority - * registers (0-3 are invalid) - */ - - regaddr = NVIC_SYSH_PRIORITY(irq); - irq -= 4; - } - else - { - /* NVIC_IRQ_PRIORITY() maps {0..} to one of many priority registers */ - - irq -= STM32_IRQ_FIRST; - regaddr = NVIC_IRQ_PRIORITY(irq); - } - - regval = getreg32(regaddr); - shift = ((irq & 3) << 3); - regval &= ~(0xff << shift); - regval |= (priority << shift); - putreg32(regval, regaddr); - - stm32_dumpnvic("prioritize", irq); - return OK; -} -#endif diff --git a/arch/arm/src/stm32/stm32_iwdg.c b/arch/arm/src/stm32/stm32_iwdg.c deleted file mode 100644 index 8996a9e845e9b..0000000000000 --- a/arch/arm/src/stm32/stm32_iwdg.c +++ /dev/null @@ -1,703 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_iwdg.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include - -#include -#include -#include -#include - -#include -#include -#include -#include -#include - -#include "arm_internal.h" -#include "stm32_rcc.h" -#include "hardware/stm32_dbgmcu.h" -#include "stm32_wdg.h" - -#if defined(CONFIG_WATCHDOG) && defined(CONFIG_STM32_IWDG) - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Clocking *****************************************************************/ - -/* The minimum frequency of the IWDG clock is: - * - * Fmin = Flsi / 256 - * - * So the maximum delay (in milliseconds) is then: - * - * 1000 * IWDG_RLR_MAX / Fmin - * - * For example, if Flsi = 30Khz (the nominal, uncalibrated value), then the - * maximum delay is: - * - * Fmin = 117.1875 - * 1000 * 4095 / Fmin = 34,944 MSec - */ - -#define IWDG_FMIN (STM32_LSI_FREQUENCY / 256) -#define IWDG_MAXTIMEOUT (1000 * IWDG_RLR_MAX / IWDG_FMIN) - -/* Configuration ************************************************************/ - -#ifndef CONFIG_STM32_IWDG_DEFTIMOUT -# define CONFIG_STM32_IWDG_DEFTIMOUT IWDG_MAXTIMEOUT -#endif - -#ifndef CONFIG_DEBUG_WATCHDOG_INFO -# undef CONFIG_STM32_IWDG_REGDEBUG -#endif - -/* REVISIT: It appears that you can only setup the prescaler and reload - * registers once. After that, the SR register's PVU and RVU bits never go - * to zero. So we defer setting up these registers until the watchdog - * is started, then refuse any further attempts to change timeout. - */ - -#define CONFIG_STM32_IWDG_ONETIMESETUP 1 - -/* REVISIT: Another possibility is that we CAN change the prescaler and - * reload values after starting the timer. This option is untested but the - * implementation place conditioned on the following: - */ - -#undef CONFIG_STM32_IWDG_DEFERREDSETUP - -/* But you can only try one at a time */ - -#if defined(CONFIG_STM32_IWDG_ONETIMESETUP) && defined(CONFIG_STM32_IWDG_DEFERREDSETUP) -# error "Both CONFIG_STM32_IWDG_ONETIMESETUP and CONFIG_STM32_IWDG_DEFERREDSETUP are defined" -#endif - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/* This structure provides the private representation of the "lower-half" - * driver state structure. This structure must be cast-compatible with the - * well-known watchdog_lowerhalf_s structure. - */ - -struct stm32_lowerhalf_s -{ - const struct watchdog_ops_s *ops; /* Lower half operations */ - uint32_t lsifreq; /* The calibrated frequency of the LSI oscillator */ - uint32_t timeout; /* The (actual) selected timeout */ - uint32_t lastreset; /* The last reset time */ - bool started; /* true: The watchdog timer has been started */ - uint8_t prescaler; /* Clock prescaler value */ - uint16_t reload; /* Timer reload value */ -}; - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -/* Register operations ******************************************************/ - -#ifdef CONFIG_STM32_IWDG_REGDEBUG -static uint16_t stm32_getreg(uint32_t addr); -static void stm32_putreg(uint16_t val, uint32_t addr); -#else -# define stm32_getreg(addr) getreg16(addr) -# define stm32_putreg(val,addr) putreg16(val,addr) -#endif - -static inline void stm32_setprescaler(struct stm32_lowerhalf_s *priv); - -/* "Lower half" driver methods **********************************************/ - -static int stm32_start(struct watchdog_lowerhalf_s *lower); -static int stm32_stop(struct watchdog_lowerhalf_s *lower); -static int stm32_keepalive(struct watchdog_lowerhalf_s *lower); -static int stm32_getstatus(struct watchdog_lowerhalf_s *lower, - struct watchdog_status_s *status); -static int stm32_settimeout(struct watchdog_lowerhalf_s *lower, - uint32_t timeout); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* "Lower half" driver methods */ - -static const struct watchdog_ops_s g_wdgops = -{ - .start = stm32_start, - .stop = stm32_stop, - .keepalive = stm32_keepalive, - .getstatus = stm32_getstatus, - .settimeout = stm32_settimeout, - .capture = NULL, - .ioctl = NULL, -}; - -/* "Lower half" driver state */ - -static struct stm32_lowerhalf_s g_wdgdev; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_getreg - * - * Description: - * Get the contents of an STM32 IWDG register - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_IWDG_REGDEBUG -static uint16_t stm32_getreg(uint32_t addr) -{ - static uint32_t prevaddr = 0; - static uint32_t count = 0; - static uint16_t preval = 0; - - /* Read the value from the register */ - - uint16_t val = getreg16(addr); - - /* Is this the same value that we read from the same register last time? - * Are we polling the register? If so, suppress some of the output. - */ - - if (addr == prevaddr && val == preval) - { - if (count == 0xffffffff || ++count > 3) - { - if (count == 4) - { - wdinfo("...\n"); - } - - return val; - } - } - - /* No this is a new address or value */ - - else - { - /* Did we print "..." for the previous value? */ - - if (count > 3) - { - /* Yes.. then show how many times the value repeated */ - - wdinfo("[repeats %d more times]\n", count - 3); - } - - /* Save the new address, value, and count */ - - prevaddr = addr; - preval = val; - count = 1; - } - - /* Show the register value read */ - - wdinfo("%08" PRIx32 "->%04x\n", addr, val); - return val; -} -#endif - -/**************************************************************************** - * Name: stm32_putreg - * - * Description: - * Set the contents of an STM32 register to a value - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_IWDG_REGDEBUG -static void stm32_putreg(uint16_t val, uint32_t addr) -{ - /* Show the register value being written */ - - wdinfo("%08" PRIx32 "<-%04x\n", addr, val); - - /* Write the value */ - - putreg16(val, addr); -} -#endif - -/**************************************************************************** - * Name: stm32_setprescaler - * - * Description: - * Set up the prescaler and reload values. This seems to be something - * that can only be done one time. - * - * Input Parameters: - * priv - A pointer the internal representation of the "lower-half" - * driver state structure. - * - ****************************************************************************/ - -static inline void stm32_setprescaler(struct stm32_lowerhalf_s *priv) -{ - /* Enable write access to IWDG_PR and IWDG_RLR registers */ - - stm32_putreg(IWDG_KR_KEY_ENABLE, STM32_IWDG_KR); - - /* Wait for the PVU and RVU bits to be reset be hardware. These bits - * were set the last time that the PR register was written and may not - * yet be cleared. - * - * If the setup is only permitted one time, then this wait should not - * be necessary. - */ - -#ifndef CONFIG_STM32_IWDG_ONETIMESETUP - while ((stm32_getreg(STM32_IWDG_SR) & (IWDG_SR_PVU | IWDG_SR_RVU)) != 0); -#endif - - /* Set the prescaler */ - - stm32_putreg((uint16_t)priv->prescaler << IWDG_PR_SHIFT, STM32_IWDG_PR); - - /* Set the reload value */ - - stm32_putreg((uint16_t)priv->reload, STM32_IWDG_RLR); - - /* Reload the counter (and disable write access) */ - - stm32_putreg(IWDG_KR_KEY_RELOAD, STM32_IWDG_KR); -} - -/**************************************************************************** - * Name: stm32_start - * - * Description: - * Start the watchdog timer, resetting the time to the current timeout, - * - * Input Parameters: - * lower - A pointer the publicly visible representation of the - * "lower-half" driver state structure. - * - * Returned Value: - * Zero on success; a negated errno value on failure. - * - ****************************************************************************/ - -static int stm32_start(struct watchdog_lowerhalf_s *lower) -{ - struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; - irqstate_t flags; - - wdinfo("Entry: started\n"); - DEBUGASSERT(priv); - - /* Have we already been started? */ - - if (!priv->started) - { - /* REVISIT: It appears that you can only setup the prescaler and reload - * registers once. After that, the SR register's PVU and RVU bits never - * go to 0. So we defer setting up these registers until the watchdog - * is started, then refuse any further attempts to change timeout. - */ - - /* Set up prescaler and reload value for the selected timeout before - * starting the watchdog timer. - */ - -#if defined(CONFIG_STM32_IWDG_ONETIMESETUP) || defined(CONFIG_STM32_IWDG_DEFERREDSETUP) - stm32_setprescaler(priv); -#endif - - /* Enable IWDG (the LSI oscillator will be enabled by hardware). NOTE: - * If the "Hardware watchdog" feature is enabled through the device - * option bits, the watchdog is automatically enabled at power-on. - */ - - flags = enter_critical_section(); - stm32_putreg(IWDG_KR_KEY_START, STM32_IWDG_KR); - priv->lastreset = clock_systime_ticks(); - priv->started = true; - leave_critical_section(flags); - } - - return OK; -} - -/**************************************************************************** - * Name: stm32_stop - * - * Description: - * Stop the watchdog timer - * - * Input Parameters: - * lower - A pointer the publicly visible representation of the - * "lower-half" driver state structure. - * - * Returned Value: - * Zero on success; a negated errno value on failure. - * - ****************************************************************************/ - -static int stm32_stop(struct watchdog_lowerhalf_s *lower) -{ - /* There is no way to disable the IDWG timer once it has been started */ - - wdinfo("Entry\n"); - return -ENOSYS; -} - -/**************************************************************************** - * Name: stm32_keepalive - * - * Description: - * Reset the watchdog timer to the current timeout value, prevent any - * imminent watchdog timeouts. This is sometimes referred as "pinging" - * the watchdog timer or "petting the dog". - * - * Input Parameters: - * lower - A pointer the publicly visible representation of the - * "lower-half" driver state structure. - * - * Returned Value: - * Zero on success; a negated errno value on failure. - * - ****************************************************************************/ - -static int stm32_keepalive(struct watchdog_lowerhalf_s *lower) -{ - struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; - irqstate_t flags; - - wdinfo("Entry\n"); - - /* Reload the IWDG timer */ - - flags = enter_critical_section(); - stm32_putreg(IWDG_KR_KEY_RELOAD, STM32_IWDG_KR); - priv->lastreset = clock_systime_ticks(); - leave_critical_section(flags); - - return OK; -} - -/**************************************************************************** - * Name: stm32_getstatus - * - * Description: - * Get the current watchdog timer status - * - * Input Parameters: - * lower - A pointer the publicly visible representation of the - * "lower-half" driver state structure. - * status - The location to return the watchdog status information. - * - * Returned Value: - * Zero on success; a negated errno value on failure. - * - ****************************************************************************/ - -static int stm32_getstatus(struct watchdog_lowerhalf_s *lower, - struct watchdog_status_s *status) -{ - struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; - uint32_t ticks; - uint32_t elapsed; - - wdinfo("Entry\n"); - DEBUGASSERT(priv); - - /* Return the status bit */ - - status->flags = WDFLAGS_RESET; - if (priv->started) - { - status->flags |= WDFLAGS_ACTIVE; - } - - /* Return the actual timeout in milliseconds */ - - status->timeout = priv->timeout; - - /* Get the elapsed time since the last ping */ - - ticks = clock_systime_ticks() - priv->lastreset; - elapsed = (int32_t)TICK2MSEC(ticks); - - if (elapsed > priv->timeout) - { - elapsed = priv->timeout; - } - - /* Return the approximate time until the watchdog timer expiration */ - - status->timeleft = priv->timeout - elapsed; - - wdinfo("Status :\n"); - wdinfo(" flags : %08" PRIx32 "\n", status->flags); - wdinfo(" timeout : %" PRId32 "\n", status->timeout); - wdinfo(" timeleft : %" PRId32 "\n", status->timeleft); - return OK; -} - -/**************************************************************************** - * Name: stm32_settimeout - * - * Description: - * Set a new timeout value (and reset the watchdog timer) - * - * Input Parameters: - * lower - A pointer the publicly visible representation of the - * "lower-half" driver state structure. - * timeout - The new timeout value in milliseconds. - * - * Returned Value: - * Zero on success; a negated errno value on failure. - * - ****************************************************************************/ - -static int stm32_settimeout(struct watchdog_lowerhalf_s *lower, - uint32_t timeout) -{ - struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; - uint32_t fiwdg; - uint64_t reload; - int prescaler; - int shift; - - wdinfo("Entry: timeout=%" PRId32 "\n", timeout); - DEBUGASSERT(priv); - - /* Can this timeout be represented? */ - - if (timeout < 1 || timeout > IWDG_MAXTIMEOUT) - { - wderr("ERROR: Cannot represent timeout=%" PRId32 " > %d\n", - timeout, IWDG_MAXTIMEOUT); - return -ERANGE; - } - - /* REVISIT: It appears that you can only setup the prescaler and reload - * registers once. After that, the SR register's PVU and RVU bits never go - * to zero. - */ - -#ifdef CONFIG_STM32_IWDG_ONETIMESETUP - if (priv->started) - { - wdwarn("WARNING: Timer is already started\n"); - return -EBUSY; - } -#endif - - /* Select the smallest prescaler that will result in a reload value that is - * less than the maximum. - */ - - for (prescaler = 0; ; prescaler++) - { - /* PR = 0 -> Divider = 4 = 1 << 2 - * PR = 1 -> Divider = 8 = 1 << 3 - * PR = 2 -> Divider = 16 = 1 << 4 - * PR = 3 -> Divider = 32 = 1 << 5 - * PR = 4 -> Divider = 64 = 1 << 6 - * PR = 5 -> Divider = 128 = 1 << 7 - * PR = 6 -> Divider = 256 = 1 << 8 - * PR = n -> Divider = 1 << (n+2) - */ - - shift = prescaler + 2; - - /* Get the IWDG counter frequency in Hz. For a nominal 32Khz LSI clock, - * this is value in the range of 7500 and 125. - */ - - fiwdg = priv->lsifreq >> shift; - - /* We want: - * 1000 * reload / Fiwdg = timeout - * Or: - * reload = Fiwdg * timeout / 1000 - */ - - reload = (uint64_t)fiwdg * (uint64_t)timeout / 1000; - - /* If this reload valid is less than the maximum or we are not ready - * at the prescaler value, then break out of the loop to use these - * settings. - */ - - if (reload <= IWDG_RLR_MAX || prescaler == 6) - { - /* Note that we explicitly break out of the loop rather than using - * the 'for' loop termination logic because we do not want the - * value of prescaler to be incremented. - */ - - break; - } - } - - /* Make sure that the final reload value is within range */ - - if (reload > IWDG_RLR_MAX) - { - reload = IWDG_RLR_MAX; - } - - /* Get the actual timeout value in milliseconds. - * - * We have: - * reload = Fiwdg * timeout / 1000 - * So we want: - * timeout = 1000 * reload / Fiwdg - */ - - priv->timeout = (1000 * (uint32_t)reload) / fiwdg; - - /* Save setup values for later use */ - - priv->prescaler = prescaler; - priv->reload = reload; - - /* Write the prescaler and reload values to the IWDG registers. - * - * REVISIT: It appears that you can only setup the prescaler and reload - * registers once. After that, the SR register's PVU and RVU bits never go - * to zero. - */ - -#ifndef CONFIG_STM32_IWDG_ONETIMESETUP - /* If CONFIG_STM32_IWDG_DEFERREDSETUP is selected, then perform the - * register configuration only if the timer has been started. - */ - -#ifdef CONFIG_STM32_IWDG_DEFERREDSETUP - if (priv->started) -#endif - { - stm32_setprescaler(priv); - } -#endif - - wdinfo("prescaler=%d fiwdg=%" PRId32 " reload=%" PRId64 "\n", - prescaler, fiwdg, reload); - - return OK; -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_iwdginitialize - * - * Description: - * Initialize the IWDG watchdog timer. The watchdog timer is initialized - * and registers as 'devpath'. The initial state of the watchdog timer is - * disabled. - * - * Input Parameters: - * devpath - The full path to the watchdog. This should be of the form - * /dev/watchdog0 - * lsifreq - The calibrated LSI clock frequency - * - * Returned Value: - * None - * - ****************************************************************************/ - -void stm32_iwdginitialize(const char *devpath, uint32_t lsifreq) -{ - struct stm32_lowerhalf_s *priv = &g_wdgdev; - - wdinfo("Entry: devpath=%s lsifreq=%" PRId32 "\n", devpath, lsifreq); - - /* NOTE we assume that clocking to the IWDG has already been provided by - * the RCC initialization logic. - */ - - /* Initialize the driver state structure. */ - - priv->ops = &g_wdgops; - priv->lsifreq = lsifreq; - priv->started = false; - - /* Make sure that the LSI oscillator is enabled. NOTE: The LSI oscillator - * is enabled here but is not disabled by this file, because this file does - * not know the global usage of the oscillator. Any clock management - * logic (say, as part of a power management scheme) needs handle other - * LSI controls outside of this file. - */ - - stm32_rcc_enablelsi(); - wdinfo("RCC CSR: %08" PRIx32 "\n", getreg32(STM32_RCC_CSR)); - - /* Select an arbitrary initial timeout value. But don't start the watchdog - * yet. NOTE: If the "Hardware watchdog" feature is enabled through the - * device option bits, the watchdog is automatically enabled at power-on. - */ - - stm32_settimeout((struct watchdog_lowerhalf_s *)priv, - CONFIG_STM32_IWDG_DEFTIMOUT); - - /* Register the watchdog driver as /dev/watchdog0 */ - - watchdog_register(devpath, (struct watchdog_lowerhalf_s *)priv); - - /* When the microcontroller enters debug mode (Cortex-M4F core halted), - * the IWDG counter either continues to work normally or stops, depending - * on DBG_IWDG_STOP configuration bit in DBG module. - */ - -#if defined(CONFIG_STM32_JTAG_FULL_ENABLE) || \ - defined(CONFIG_STM32_JTAG_NOJNTRST_ENABLE) || \ - defined(CONFIG_STM32_JTAG_SW_ENABLE) - { -#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F30XX) || \ - defined(CONFIG_STM32_STM32F4XXX) || defined(CONFIG_STM32_STM32L15XX) - uint32_t cr = getreg32(STM32_DBGMCU_APB1_FZ); - cr |= DBGMCU_APB1_IWDGSTOP; - putreg32(cr, STM32_DBGMCU_APB1_FZ); -#else /* if defined(CONFIG_STM32_STM32F10XX) */ - uint32_t cr = getreg32(STM32_DBGMCU_CR); - cr |= DBGMCU_CR_IWDGSTOP; - putreg32(cr, STM32_DBGMCU_CR); -#endif - } -#endif -} - -#endif /* CONFIG_WATCHDOG && CONFIG_STM32_IWDG */ diff --git a/arch/arm/src/stm32/stm32_lowputc.c b/arch/arm/src/stm32/stm32_lowputc.c deleted file mode 100644 index ff9659c97107e..0000000000000 --- a/arch/arm/src/stm32/stm32_lowputc.c +++ /dev/null @@ -1,694 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_lowputc.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include - -#include "arm_internal.h" -#include "chip.h" - -#include "stm32.h" -#include "stm32_rcc.h" -#include "stm32_gpio.h" -#include "stm32_uart.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Select USART parameters for the selected console */ - -#ifdef HAVE_CONSOLE -# if defined(CONFIG_USART1_SERIAL_CONSOLE) -# define STM32_CONSOLE_BASE STM32_USART1_BASE -# if defined(CONFIG_STM32_STM32F33XX) -# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY /* Errata 2.5.1 */ -# else -# define STM32_APBCLOCK STM32_PCLK2_FREQUENCY -# endif -# define STM32_CONSOLE_APBREG STM32_RCC_APB2ENR -# define STM32_CONSOLE_APBEN RCC_APB2ENR_USART1EN -# define STM32_CONSOLE_BAUD CONFIG_USART1_BAUD -# define STM32_CONSOLE_BITS CONFIG_USART1_BITS -# define STM32_CONSOLE_PARITY CONFIG_USART1_PARITY -# define STM32_CONSOLE_2STOP CONFIG_USART1_2STOP -# define STM32_CONSOLE_TX GPIO_USART1_TX -# define STM32_CONSOLE_RX GPIO_USART1_RX -# ifdef CONFIG_USART1_RS485 -# define STM32_CONSOLE_RS485_DIR GPIO_USART1_RS485_DIR -# if (CONFIG_USART1_RS485_DIR_POLARITY == 0) -# define STM32_CONSOLE_RS485_DIR_POLARITY false -# else -# define STM32_CONSOLE_RS485_DIR_POLARITY true -# endif -# endif -# elif defined(CONFIG_USART2_SERIAL_CONSOLE) -# define STM32_CONSOLE_BASE STM32_USART2_BASE -# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY -# define STM32_CONSOLE_APBREG STM32_RCC_APB1ENR -# define STM32_CONSOLE_APBEN RCC_APB1ENR_USART2EN -# define STM32_CONSOLE_BAUD CONFIG_USART2_BAUD -# define STM32_CONSOLE_BITS CONFIG_USART2_BITS -# define STM32_CONSOLE_PARITY CONFIG_USART2_PARITY -# define STM32_CONSOLE_2STOP CONFIG_USART2_2STOP -# define STM32_CONSOLE_TX GPIO_USART2_TX -# define STM32_CONSOLE_RX GPIO_USART2_RX -# ifdef CONFIG_USART2_RS485 -# define STM32_CONSOLE_RS485_DIR GPIO_USART2_RS485_DIR -# if (CONFIG_USART2_RS485_DIR_POLARITY == 0) -# define STM32_CONSOLE_RS485_DIR_POLARITY false -# else -# define STM32_CONSOLE_RS485_DIR_POLARITY true -# endif -# endif -# elif defined(CONFIG_USART3_SERIAL_CONSOLE) -# define STM32_CONSOLE_BASE STM32_USART3_BASE -# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY -# define STM32_CONSOLE_APBREG STM32_RCC_APB1ENR -# define STM32_CONSOLE_APBEN RCC_APB1ENR_USART3EN -# define STM32_CONSOLE_BAUD CONFIG_USART3_BAUD -# define STM32_CONSOLE_BITS CONFIG_USART3_BITS -# define STM32_CONSOLE_PARITY CONFIG_USART3_PARITY -# define STM32_CONSOLE_2STOP CONFIG_USART3_2STOP -# define STM32_CONSOLE_TX GPIO_USART3_TX -# define STM32_CONSOLE_RX GPIO_USART3_RX -# ifdef CONFIG_USART3_RS485 -# define STM32_CONSOLE_RS485_DIR GPIO_USART3_RS485_DIR -# if (CONFIG_USART3_RS485_DIR_POLARITY == 0) -# define STM32_CONSOLE_RS485_DIR_POLARITY false -# else -# define STM32_CONSOLE_RS485_DIR_POLARITY true -# endif -# endif -# elif defined(CONFIG_UART4_SERIAL_CONSOLE) -# define STM32_CONSOLE_BASE STM32_UART4_BASE -# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY -# define STM32_CONSOLE_APBREG STM32_RCC_APB1ENR -# define STM32_CONSOLE_APBEN RCC_APB1ENR_UART4EN -# define STM32_CONSOLE_BAUD CONFIG_UART4_BAUD -# define STM32_CONSOLE_BITS CONFIG_UART4_BITS -# define STM32_CONSOLE_PARITY CONFIG_UART4_PARITY -# define STM32_CONSOLE_2STOP CONFIG_UART4_2STOP -# define STM32_CONSOLE_TX GPIO_UART4_TX -# define STM32_CONSOLE_RX GPIO_UART4_RX -# ifdef CONFIG_UART4_RS485 -# define STM32_CONSOLE_RS485_DIR GPIO_UART4_RS485_DIR -# if (CONFIG_UART4_RS485_DIR_POLARITY == 0) -# define STM32_CONSOLE_RS485_DIR_POLARITY false -# else -# define STM32_CONSOLE_RS485_DIR_POLARITY true -# endif -# endif -# elif defined(CONFIG_UART5_SERIAL_CONSOLE) -# define STM32_CONSOLE_BASE STM32_UART5_BASE -# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY -# define STM32_CONSOLE_APBREG STM32_RCC_APB1ENR -# define STM32_CONSOLE_APBEN RCC_APB1ENR_UART5EN -# define STM32_CONSOLE_BAUD CONFIG_UART5_BAUD -# define STM32_CONSOLE_BITS CONFIG_UART5_BITS -# define STM32_CONSOLE_PARITY CONFIG_UART5_PARITY -# define STM32_CONSOLE_2STOP CONFIG_UART5_2STOP -# define STM32_CONSOLE_TX GPIO_UART5_TX -# define STM32_CONSOLE_RX GPIO_UART5_RX -# ifdef CONFIG_UART5_RS485 -# define STM32_CONSOLE_RS485_DIR GPIO_UART5_RS485_DIR -# if (CONFIG_UART5_RS485_DIR_POLARITY == 0) -# define STM32_CONSOLE_RS485_DIR_POLARITY false -# else -# define STM32_CONSOLE_RS485_DIR_POLARITY true -# endif -# endif -# elif defined(CONFIG_USART6_SERIAL_CONSOLE) -# define STM32_CONSOLE_BASE STM32_USART6_BASE -# define STM32_APBCLOCK STM32_PCLK2_FREQUENCY -# define STM32_CONSOLE_APBREG STM32_RCC_APB2ENR -# define STM32_CONSOLE_APBEN RCC_APB2ENR_USART6EN -# define STM32_CONSOLE_BAUD CONFIG_USART6_BAUD -# define STM32_CONSOLE_BITS CONFIG_USART6_BITS -# define STM32_CONSOLE_PARITY CONFIG_USART6_PARITY -# define STM32_CONSOLE_2STOP CONFIG_USART6_2STOP -# define STM32_CONSOLE_TX GPIO_USART6_TX -# define STM32_CONSOLE_RX GPIO_USART6_RX -# ifdef CONFIG_USART6_RS485 -# define STM32_CONSOLE_RS485_DIR GPIO_USART6_RS485_DIR -# if (CONFIG_USART6_RS485_DIR_POLARITY == 0) -# define STM32_CONSOLE_RS485_DIR_POLARITY false -# else -# define STM32_CONSOLE_RS485_DIR_POLARITY true -# endif -# endif -# elif defined(CONFIG_UART7_SERIAL_CONSOLE) -# define STM32_CONSOLE_BASE STM32_UART7_BASE -# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY -# define STM32_CONSOLE_APBREG STM32_RCC_APB1ENR -# define STM32_CONSOLE_APBEN RCC_APB1ENR_UART7EN -# define STM32_CONSOLE_BAUD CONFIG_UART7_BAUD -# define STM32_CONSOLE_BITS CONFIG_UART7_BITS -# define STM32_CONSOLE_PARITY CONFIG_UART7_PARITY -# define STM32_CONSOLE_2STOP CONFIG_UART7_2STOP -# define STM32_CONSOLE_TX GPIO_UART7_TX -# define STM32_CONSOLE_RX GPIO_UART7_RX -# ifdef CONFIG_UART7_RS485 -# define STM32_CONSOLE_RS485_DIR GPIO_UART7_RS485_DIR -# if (CONFIG_UART7_RS485_DIR_POLARITY == 0) -# define STM32_CONSOLE_RS485_DIR_POLARITY false -# else -# define STM32_CONSOLE_RS485_DIR_POLARITY true -# endif -# endif -# elif defined(CONFIG_UART8_SERIAL_CONSOLE) -# define STM32_CONSOLE_BASE STM32_UART8_BASE -# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY -# define STM32_CONSOLE_APBREG STM32_RCC_APB1ENR -# define STM32_CONSOLE_APBEN RCC_APB1ENR_UART8EN -# define STM32_CONSOLE_BAUD CONFIG_UART8_BAUD -# define STM32_CONSOLE_BITS CONFIG_UART8_BITS -# define STM32_CONSOLE_PARITY CONFIG_UART8_PARITY -# define STM32_CONSOLE_2STOP CONFIG_UART8_2STOP -# define STM32_CONSOLE_TX GPIO_UART8_TX -# define STM32_CONSOLE_RX GPIO_UART8_RX -# ifdef CONFIG_UART8_RS485 -# define STM32_CONSOLE_RS485_DIR GPIO_UART8_RS485_DIR -# if (CONFIG_UART8_RS485_DIR_POLARITY == 0) -# define STM32_CONSOLE_RS485_DIR_POLARITY false -# else -# define STM32_CONSOLE_RS485_DIR_POLARITY true -# endif -# endif -# elif defined(CONFIG_LPUART1_SERIAL_CONSOLE) -# define STM32_CONSOLE_BASE STM32_LPUART1_BASE -# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY -# define STM32_CONSOLE_APBREG STM32_RCC_APB1ENR2 -# define STM32_CONSOLE_APBEN RCC_APB1ENR2_LPUART1EN -# define STM32_CONSOLE_BAUD CONFIG_LPUART1_BAUD -# define STM32_CONSOLE_BITS CONFIG_LPUART1_BITS -# define STM32_CONSOLE_PARITY CONFIG_LPUART1_PARITY -# define STM32_CONSOLE_2STOP CONFIG_LPUART1_2STOP -# define STM32_CONSOLE_TX GPIO_LPUART1_TX -# define STM32_CONSOLE_RX GPIO_LPUART1_RX -# ifdef CONFIG_LPUART1_RS485 -# define STM32_CONSOLE_RS485_DIR GPIO_LPUART1_RS485_DIR -# if (CONFIG_LPUART1_RS485_DIR_POLARITY == 0) -# define STM32_CONSOLE_RS485_DIR_POLARITY false -# else -# define STM32_CONSOLE_RS485_DIR_POLARITY true -# endif -# endif -# endif - -/* CR1 settings */ - -# if STM32_CONSOLE_BITS == 9 -# define USART_CR1_M_VALUE USART_CR1_M -# else -# define USART_CR1_M_VALUE 0 -# endif - -# if STM32_CONSOLE_PARITY == 1 -# define USART_CR1_PARITY_VALUE (USART_CR1_PCE|USART_CR1_PS) -# elif STM32_CONSOLE_PARITY == 2 -# define USART_CR1_PARITY_VALUE USART_CR1_PCE -# else -# define USART_CR1_PARITY_VALUE 0 -# endif - -# if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) || \ - defined(CONFIG_STM32_STM32F37XX) || defined(CONFIG_STM32_STM32G4XXX) -# define USART_CR1_CLRBITS\ - (USART_CR1_UESM | USART_CR1_RE | USART_CR1_TE | USART_CR1_PS | \ - USART_CR1_PCE | USART_CR1_WAKE | USART_CR1_M | USART_CR1_MME | \ - USART_CR1_OVER8 | USART_CR1_DEDT_MASK | USART_CR1_DEAT_MASK | \ - USART_CR1_ALLINTS) -# else -# define USART_CR1_CLRBITS\ - (USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | \ - USART_CR1_RE | USART_CR1_ALLINTS) -# endif - -# define USART_CR1_SETBITS (USART_CR1_M_VALUE|USART_CR1_PARITY_VALUE) - -/* CR2 settings */ - -# if STM32_CONSOLE_2STOP != 0 -# define USART_CR2_STOP2_VALUE USART_CR2_STOP2 -# else -# define USART_CR2_STOP2_VALUE 0 -# endif - -# if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) || \ - defined(CONFIG_STM32_STM32F37XX) || defined(CONFIG_STM32_STM32G4XXX) -# define USART_CR2_CLRBITS \ - (USART_CR2_ADDM7 | USART_CR2_LBDL | USART_CR2_LBDIE | USART_CR2_LBCL | \ - USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_CLKEN | USART_CR2_STOP_MASK | \ - USART_CR2_LINEN | USART_CR2_RXINV | USART_CR2_TXINV | USART_CR2_DATAINV | \ - USART_CR2_MSBFIRST | USART_CR2_ABREN | USART_CR2_ABRMOD_MASK | \ - USART_CR2_RTOEN | USART_CR2_ADD8_MASK) -# else -# define USART_CR2_CLRBITS \ - (USART_CR2_STOP_MASK | USART_CR2_CLKEN | USART_CR2_CPOL | USART_CR2_CPHA | \ - USART_CR2_LBCL | USART_CR2_LBDIE) -# endif -# define USART_CR2_SETBITS USART_CR2_STOP2_VALUE - -/* CR3 settings */ - -# if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) || \ - defined(CONFIG_STM32_STM32F37XX) || defined(CONFIG_STM32_STM32G4XXX) - -# define USART_CR3_CLRBITS \ - (USART_CR3_EIE | USART_CR3_IREN | USART_CR3_IRLP | USART_CR3_HDSEL | \ - USART_CR3_NACK | USART_CR3_SCEN | USART_CR3_DMAR | USART_CR3_DMAT | \ - USART_CR3_RTSE | USART_CR3_CTSE | USART_CR3_CTSIE | USART_CR3_ONEBIT | \ - USART_CR3_OVRDIS | USART_CR3_DDRE | USART_CR3_DEM | USART_CR3_DEP | \ - USART_CR3_SCARCNT_MASK | USART_CR3_WUS_MASK | USART_CR3_WUFIE) -# else -# define USART_CR3_CLRBITS \ - (USART_CR3_CTSIE | USART_CR3_CTSE | USART_CR3_RTSE | USART_CR3_EIE) -# endif -# define USART_CR3_SETBITS 0 - -/* Only the STM32 F3 supports oversampling by 8 */ - -# undef USE_OVER8 - -/* Calculate USART BAUD rate divider */ -# if CONSOLE_LPUART > 0 && defined(CONFIG_STM32_STM32G4XXX) - - /* BRR = (256 * (APBCLOCK / Prescaler)) / (Baud rate) - * With Prescaler == 16, BRR = (16 * APBCLOCK / (Baud rate) - * Set Prescaler to 16 to support wide range of standard baud rates - */ - -# define STM32_BRR_VALUE \ - (((STM32_APBCLOCK & 0xf0000000) / STM32_CONSOLE_BAUD) << 4) + \ - (((STM32_APBCLOCK & 0x0fffffff) << 4) / STM32_CONSOLE_BAUD) -# define STM32_PRESC_VALUE 0x7 - -# else - -# if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) || \ - defined(CONFIG_STM32_STM32F37XX) || defined(CONFIG_STM32_STM32G4XXX) - - /* Baud rate for standard USART (SPI mode included): - * - * In case of oversampling by 16, the equation is: - * baud = fCK / UARTDIV - * UARTDIV = fCK / baud - * - * In case of oversampling by 8, the equation is: - * - * baud = 2 * fCK / UARTDIV - * UARTDIV = 2 * fCK / baud - */ - -# define STM32_USARTDIV8 \ - (((STM32_APBCLOCK << 1) + (STM32_CONSOLE_BAUD >> 1)) / STM32_CONSOLE_BAUD) -# define STM32_USARTDIV16 \ - ((STM32_APBCLOCK + (STM32_CONSOLE_BAUD >> 1)) / STM32_CONSOLE_BAUD) -/* Use oversamply by 8 only if the divisor is small. But what is small? */ - -# if STM32_USARTDIV8 > 100 -# define STM32_BRR_VALUE STM32_USARTDIV16 -# else -# define USE_OVER8 1 -# define STM32_BRR_VALUE \ - ((STM32_USARTDIV8 & 0xfff0) | ((STM32_USARTDIV8 & 0x000f) >> 1)) -# endif - -# else /* CONFIG_STM32_STM32F30XX */ - -/* The baud rate for the receiver and transmitter (Rx and Tx) are both set - * to the same value as programmed in the Mantissa and Fraction values of - * USARTDIV. - * - * baud = fCK / (16 * usartdiv) - * usartdiv = fCK / (16 * baud) - * - * Where fCK is the input clock to the peripheral (PCLK1 for USART2, 3, 4, - * 5 or PCLK2 for USART1). Example, fCK=72MHz baud=115200, - * usartdiv=39.0625=39 1/16th; - * - * First calculate: - * - * usartdiv32 = 32 * usartdiv = fCK / (baud/2) - * - * (NOTE: all standard baud values are even so dividing by two does not - * lose precision). Eg. (same fCK and baud), usartdiv32 = 1250 - */ - -# define STM32_USARTDIV32 (STM32_APBCLOCK / (STM32_CONSOLE_BAUD >> 1)) - -/* The mantissa is then usartdiv32 / 32: - * - * mantissa = usartdiv32 / 32/ - * - * Eg. usartdiv32=1250, mantissa = 39 - */ - -# define STM32_MANTISSA (STM32_USARTDIV32 >> 5) - -/* And the fraction: - * - * fraction = (usartdiv32 - mantissa*32 + 1) / 2 - * - * Eg., (1,250 - 39*32 + 1)/2 = 1 (or 0.0625) - */ - -# define STM32_FRACTION \ - ((STM32_USARTDIV32 - (STM32_MANTISSA << 5) + 1) >> 1) - - /* And, finally, the BRR value is: */ - - # define STM32_BRR_VALUE \ - ((STM32_MANTISSA << USART_BRR_MANT_SHIFT) | \ - (STM32_FRACTION << USART_BRR_FRAC_SHIFT)) - -# endif /* CONFIG_STM32_STM32F30XX */ -# endif /* CONSOLE_LPUART > 0 */ -#endif /* HAVE_CONSOLE */ - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: arm_lowputc - * - * Description: - * Output one byte on the serial console - * - ****************************************************************************/ - -void arm_lowputc(char ch) -{ -#ifdef HAVE_CONSOLE - /* Wait until the TX data register is empty */ - - while ((getreg32(STM32_CONSOLE_BASE + STM32_USART_SR_OFFSET) & - USART_SR_TC) == 0); -#ifdef STM32_CONSOLE_RS485_DIR - stm32_gpiowrite(STM32_CONSOLE_RS485_DIR, - STM32_CONSOLE_RS485_DIR_POLARITY); -#endif - - /* Then send the character */ - - putreg32((uint32_t)ch, STM32_CONSOLE_BASE + STM32_USART_TDR_OFFSET); - -#ifdef STM32_CONSOLE_RS485_DIR - while ((getreg32(STM32_CONSOLE_BASE + STM32_USART_SR_OFFSET) & - USART_SR_TC) == 0); - stm32_gpiowrite(STM32_CONSOLE_RS485_DIR, - !STM32_CONSOLE_RS485_DIR_POLARITY); -#endif - -#endif /* HAVE_CONSOLE */ -} - -/**************************************************************************** - * Name: stm32_lowsetup - * - * Description: - * This performs basic initialization of the USART used for the serial - * console. Its purpose is to get the console output available as soon - * as possible. - * - ****************************************************************************/ - -#if defined(CONFIG_STM32_STM32F10XX) - -void stm32_lowsetup(void) -{ -#if defined(HAVE_SERIALDRIVER) - uint32_t mapr; -#if defined(HAVE_CONSOLE) && !defined(CONFIG_SUPPRESS_UART_CONFIG) - uint32_t cr; -#endif - - /* Set up the pin mapping registers for the selected U[S]ARTs. - * - * NOTE: Clocking for selected U[S]ARTs was already provided in stm32_rcc.c - */ - - mapr = getreg32(STM32_AFIO_MAPR); - -#ifdef CONFIG_STM32_USART1 - /* Assume default pin mapping: - * - * Alternate USART1_REMAP USART1_REMAP - * Function = 0 = 1 - * ---------- ------------ ------------ - * USART1_TX PA9 PB6 - * USART1_RX PA10 PB7 - */ - -#ifdef CONFIG_STM32_USART1_REMAP - mapr |= AFIO_MAPR_USART1_REMAP; -#else - mapr &= ~AFIO_MAPR_USART1_REMAP; -#endif -#endif /* CONFIG_STM32_USART1 */ - -#ifdef CONFIG_STM32_USART2 - /* Assume default pin mapping: - * - * Alternate USART2_REMAP USART2_REMAP - * Function = 0 = 1 - * ---------- ------------ ------------ - * USART2_CTS PA0 PD3 - * USART2_RTS PA1 PD4 - * USART2_TX PA2 PD5 - * USART2_RX PA3 PD6 - * USART3_CK PA4 PD7 - */ - -#ifdef CONFIG_STM32_USART2_REMAP - mapr |= AFIO_MAPR_USART2_REMAP; -#else - mapr &= ~AFIO_MAPR_USART2_REMAP; -#endif -#endif /* CONFIG_STM32_USART2 */ - - /* Assume default pin mapping: - * - * Alternate USART3_REMAP[1:0] USART3_REMAP[1:0] USART3_REMAP[1:0] - * Function = 00 (no remap) = 01 (partial remap) = 11 (full remap) - * ---------_ ------------------ ---------------------- ----------------- - * USART3_TX PB10 PC10 PD8 - * USART3_RX PB11 PC11 PD9 - * USART3_CK PB12 PC12 PD10 - * USART3_CTS PB13 PB13 PD11 - * USART3_RTS PB14 PB14 PD12 - */ - - mapr &= ~AFIO_MAPR_USART3_REMAP_MASK; - -#ifdef CONFIG_STM32_USART3 -#if defined(CONFIG_STM32_USART3_PARTIAL_REMAP) - mapr |= AFIO_MAPR_USART3_PARTREMAP; -#elif defined(CONFIG_STM32_USART3_FULL_REMAP) - mapr |= AFIO_MAPR_USART3_FULLREMAP; -#endif -#endif /* CONFIG_STM32_USART3 */ - - putreg32(mapr, STM32_AFIO_MAPR); - - /* Configure GPIO pins needed for rx/tx. */ - -#ifdef STM32_CONSOLE_TX - stm32_configgpio(STM32_CONSOLE_TX); -#endif -#ifdef STM32_CONSOLE_RX - stm32_configgpio(STM32_CONSOLE_RX); -#endif - -#ifdef STM32_CONSOLE_RS485_DIR - stm32_configgpio(STM32_CONSOLE_RS485_DIR); - stm32_gpiowrite(STM32_CONSOLE_RS485_DIR, - !STM32_CONSOLE_RS485_DIR_POLARITY); -#endif - - /* Enable and configure the selected console device */ - -#if defined(HAVE_CONSOLE) && !defined(CONFIG_SUPPRESS_UART_CONFIG) - /* Configure CR2 */ - - cr = getreg32(STM32_CONSOLE_BASE + STM32_USART_CR2_OFFSET); - cr &= ~USART_CR2_CLRBITS; - cr |= USART_CR2_SETBITS; - putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR2_OFFSET); - - /* Configure CR1 */ - - cr = getreg32(STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET); - cr &= ~USART_CR1_CLRBITS; - cr |= USART_CR1_SETBITS; - putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET); - - /* Configure CR3 */ - - cr = getreg32(STM32_CONSOLE_BASE + STM32_USART_CR3_OFFSET); - cr &= ~USART_CR3_CLRBITS; - cr |= USART_CR3_SETBITS; - putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR3_OFFSET); - - /* Configure the USART Baud Rate */ - - putreg32(STM32_BRR_VALUE, STM32_CONSOLE_BASE + STM32_USART_BRR_OFFSET); - - /* Enable Rx, Tx, and the USART */ - - cr = getreg32(STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET); - cr |= (USART_CR1_UE | USART_CR1_TE | USART_CR1_RE); - putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET); - -#endif /* HAVE_CONSOLE && !CONFIG_SUPPRESS_UART_CONFIG */ -#endif /* HAVE_SERIALDRIVER */ -} - -#elif defined(CONFIG_STM32_STM32L15XX) || defined(CONFIG_STM32_STM32F20XX) || \ - defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) || \ - defined(CONFIG_STM32_STM32F37XX) || defined(CONFIG_STM32_STM32F4XXX) || \ - defined(CONFIG_STM32_STM32G4XXX) - -void stm32_lowsetup(void) -{ -#if defined(HAVE_SERIALDRIVER) -#if defined(HAVE_CONSOLE) && !defined(CONFIG_SUPPRESS_UART_CONFIG) - uint32_t cr; -#endif - -#if defined(HAVE_CONSOLE) - /* Enable USART APB1/2 clock */ - - modifyreg32(STM32_CONSOLE_APBREG, 0, STM32_CONSOLE_APBEN); -#endif - - /* Enable the console USART and configure GPIO pins needed for rx/tx. - * - * NOTE: Clocking for selected U[S]ARTs was already provided in stm32_rcc.c - */ - -#ifdef STM32_CONSOLE_TX - stm32_configgpio(STM32_CONSOLE_TX); -#endif -#ifdef STM32_CONSOLE_RX - stm32_configgpio(STM32_CONSOLE_RX); -#endif - -#ifdef STM32_CONSOLE_RS485_DIR - stm32_configgpio(STM32_CONSOLE_RS485_DIR); - stm32_gpiowrite(STM32_CONSOLE_RS485_DIR, - !STM32_CONSOLE_RS485_DIR_POLARITY); -#endif - - /* Enable and configure the selected console device */ - -#if defined(HAVE_CONSOLE) && !defined(CONFIG_SUPPRESS_UART_CONFIG) - /* Ensure the USART is disabled because some bits of the following - * registers cannot be modified otherwise. - * - * Although the USART is expected to be disabled at power on reset, this - * might not be the case if we boot from a serial bootloader that does not - * clean up properly. - */ - - cr = getreg32(STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET); - cr &= ~USART_CR1_UE; - putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET); - - /* Configure CR2 */ - - cr = getreg32(STM32_CONSOLE_BASE + STM32_USART_CR2_OFFSET); - cr &= ~USART_CR2_CLRBITS; - cr |= USART_CR2_SETBITS; - putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR2_OFFSET); - - /* Configure CR1 */ - - cr = getreg32(STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET); - cr &= ~USART_CR1_CLRBITS; - cr |= USART_CR1_SETBITS; - putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET); - - /* Configure CR3 */ - - cr = getreg32(STM32_CONSOLE_BASE + STM32_USART_CR3_OFFSET); - cr &= ~USART_CR3_CLRBITS; - cr |= USART_CR3_SETBITS; - putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR3_OFFSET); - - /* Configure the USART Baud Rate */ - -#if CONSOLE_LPUART > 0 && defined(CONFIG_STM32_STM32G4XXX) - putreg32(STM32_PRESC_VALUE, STM32_CONSOLE_BASE + STM32_USART_PRESC_OFFSET); -#endif - - putreg32(STM32_BRR_VALUE, STM32_CONSOLE_BASE + STM32_USART_BRR_OFFSET); - - /* Select oversampling by 8 */ - - cr = getreg32(STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET); -#ifdef USE_OVER8 - cr |= USART_CR1_OVER8; - putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET); -#endif - - /* Enable Rx, Tx, and the USART */ - - cr |= (USART_CR1_UE | USART_CR1_TE | USART_CR1_RE); - putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET); - -#endif /* HAVE_CONSOLE && !CONFIG_SUPPRESS_UART_CONFIG */ -#endif /* HAVE_SERIALDRIVER */ -} - -#else -# error "Unsupported STM32 chip" -#endif diff --git a/arch/arm/src/stm32/stm32_lowputc.h b/arch/arm/src/stm32/stm32_lowputc.h deleted file mode 100644 index 76629be9c542d..0000000000000 --- a/arch/arm/src/stm32/stm32_lowputc.h +++ /dev/null @@ -1,66 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_lowputc.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32_STM32_LOWPUTC_H -#define __ARCH_ARM_SRC_STM32_STM32_LOWPUTC_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "chip.h" - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -#ifndef __ASSEMBLY__ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Name: stm32_lowsetup - * - * Description: - * Called at the very beginning of _start. - * Performs low level initialization of serial console. - * - ****************************************************************************/ - -void stm32_lowsetup(void); - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32_STM32_LOWPUTC_H */ diff --git a/arch/arm/src/stm32/stm32_lse.c b/arch/arm/src/stm32/stm32_lse.c deleted file mode 100644 index 7f4d215ddc1d7..0000000000000 --- a/arch/arm/src/stm32/stm32_lse.c +++ /dev/null @@ -1,91 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_lse.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "arm_internal.h" -#include "stm32_pwr.h" -#include "stm32_rcc.h" -#include "stm32_waste.h" - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_rcc_enablelse - * - * Description: - * Enable the External Low-Speed (LSE) oscillator. - * - * Todo: - * Check for LSE good timeout and return with -1, - * - ****************************************************************************/ - -void stm32_rcc_enablelse(void) -{ - /* The LSE is in the RTC domain and write access is denied to this domain - * after reset, you have to enable write access using DBP bit in the PWR CR - * register before to configuring the LSE. - */ - - stm32_pwr_enablebkp(true); - -#if defined(CONFIG_STM32_STM32L15XX) - /* Enable the External Low-Speed (LSE) oscillator by setting the LSEON bit - * the RCC CSR register. - */ - - modifyreg32(STM32_RCC_CSR, 0, RCC_CSR_LSEON); - - /* Wait for the LSE clock to be ready */ - - while ((getreg32(STM32_RCC_CSR) & RCC_CSR_LSERDY) == 0) - { - stm32_waste(); - } - -#else - /* Enable the External Low-Speed (LSE) oscillator by setting the LSEON bit - * the RCC BDCR register. - */ - - modifyreg16(STM32_RCC_BDCR, 0, RCC_BDCR_LSEON); - - /* Wait for the LSE clock to be ready */ - - while ((getreg16(STM32_RCC_BDCR) & RCC_BDCR_LSERDY) == 0) - { - stm32_waste(); - } - -#endif - - /* Disable backup domain access if it was disabled on entry */ - - stm32_pwr_enablebkp(false); -} diff --git a/arch/arm/src/stm32/stm32_lsi.c b/arch/arm/src/stm32/stm32_lsi.c deleted file mode 100644 index 45d15c8fab1c1..0000000000000 --- a/arch/arm/src/stm32/stm32_lsi.c +++ /dev/null @@ -1,86 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_lsi.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "arm_internal.h" -#include "stm32_rcc.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_rcc_enablelsi - * - * Description: - * Enable the Internal Low-Speed (LSI) RC Oscillator. - * - ****************************************************************************/ - -void stm32_rcc_enablelsi(void) -{ - /* Enable the Internal Low-Speed (LSI) RC Oscillator by setting the LSION - * bit in the RCC CSR register. - */ - - modifyreg32(STM32_RCC_CSR, 0, RCC_CSR_LSION); - - /* Wait for the internal RC 40 kHz oscillator to be stable. */ - - while ((getreg32(STM32_RCC_CSR) & RCC_CSR_LSIRDY) == 0); -} - -/**************************************************************************** - * Name: stm32_rcc_disablelsi - * - * Description: - * Disable the Internal Low-Speed (LSI) RC Oscillator. - * - ****************************************************************************/ - -void stm32_rcc_disablelsi(void) -{ - /* Enable the Internal Low-Speed (LSI) RC Oscillator by setting the LSION - * bit in the RCC CSR register. - */ - - modifyreg32(STM32_RCC_CSR, RCC_CSR_LSION, 0); - - /* LSIRDY should go low after 3 LSI clock cycles */ -} diff --git a/arch/arm/src/stm32/stm32_ltdc.c b/arch/arm/src/stm32/stm32_ltdc.c deleted file mode 100644 index 8e36b797a5e97..0000000000000 --- a/arch/arm/src/stm32/stm32_ltdc.c +++ /dev/null @@ -1,3139 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_ltdc.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* References: - * STM32F429 Technical Reference Manual and Data Sheet - */ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include - -#include - -#include "arm_internal.h" -#include "stm32.h" -#include "hardware/stm32_ltdc.h" -#include "hardware/stm32_dma2d.h" -#include "stm32_ltdc.h" -#include "stm32_dma2d.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Register definition ******************************************************/ - -#ifndef BOARD_LTDC_WIDTH -# error BOARD_LTDC_WIDTH must be defined in the board.h header file -#endif - -#ifndef BOARD_LTDC_HEIGHT -# error BOARD_LTDC_HEIGHT must be defined in the board.h header file -#endif - -#define STM32_LTDC_HEIGHT BOARD_LTDC_HEIGHT -#define STM32_LTDC_WIDTH BOARD_LTDC_WIDTH - -/* Configure LTDC register */ - -/* LTDC_LxWHPCR register */ - -#define STM32_LTDC_LXWHPCR_WHSTPOS (BOARD_LTDC_HSYNC + BOARD_LTDC_HBP - 1) -#define STM32_LTDC_LxWHPCR_WHSPPOS (BOARD_LTDC_HSYNC + BOARD_LTDC_HBP + \ - STM32_LTDC_WIDTH - 1) - -/* LTDC_LxWVPCR register */ - -#define STM32_LTDC_LXWVPCR_WVSTPOS (BOARD_LTDC_VSYNC + BOARD_LTDC_VBP - 1) -#define STM32_LTDC_LxWVPCR_WVSPPOS (BOARD_LTDC_VSYNC + BOARD_LTDC_VBP + \ - STM32_LTDC_HEIGHT - 1) - -/* LTDC_SSCR register */ - -#define STM32_LTDC_SSCR_VSH LTDC_SSCR_VSH(BOARD_LTDC_VSYNC - 1) -#define STM32_LTDC_SSCR_HSW LTDC_SSCR_HSW(BOARD_LTDC_HSYNC - 1) - -/* LTDC_BPCR register */ - -#define STM32_LTDC_BPCR_AVBP LTDC_BPCR_AVBP(STM32_LTDC_LXWVPCR_WVSTPOS) -#define STM32_LTDC_BPCR_AHBP LTDC_BPCR_AHBP(STM32_LTDC_LXWHPCR_WHSTPOS) - -/* LTDC_AWCR register */ - -#define STM32_LTDC_AWCR_AAH LTDC_AWCR_AAH(STM32_LTDC_LxWVPCR_WVSPPOS) -#define STM32_LTDC_AWCR_AAW LTDC_AWCR_AAW(STM32_LTDC_LxWHPCR_WHSPPOS) - -/* LTDC_TWCR register */ - -#define STM32_LTDC_TWCR_TOTALH LTDC_TWCR_TOTALH(BOARD_LTDC_VSYNC + \ - BOARD_LTDC_VBP + \ - STM32_LTDC_HEIGHT + BOARD_LTDC_VFP - 1) -#define STM32_LTDC_TWCR_TOTALW LTDC_TWCR_TOTALW(BOARD_LTDC_HSYNC + \ - BOARD_LTDC_HBP + \ - STM32_LTDC_WIDTH + BOARD_LTDC_HFP - 1) - -/* Global GCR register */ - -/* Synchronisation and Polarity */ - -#define STM32_LTDC_GCR_PCPOL BOARD_LTDC_GCR_PCPOL -#define STM32_LTDC_GCR_DEPOL BOARD_LTDC_GCR_DEPOL -#define STM32_LTDC_GCR_VSPOL BOARD_LTDC_GCR_VSPOL -#define STM32_LTDC_GCR_HSPOL BOARD_LTDC_GCR_HSPOL - -/* Dither */ - -#define STM32_LTDC_GCR_DEN BOARD_LTDC_GCR_DEN -#define STM32_LTDC_GCR_DBW LTDC_GCR_GBW(BOARD_LTDC_GCR_DBW) -#define STM32_LTDC_GCR_DGW LTDC_GCR_DGW(BOARD_LTDC_GCR_DGW) -#define STN32_LTDC_GCR_DRW LTDC_GCR_DBW(BOARD_LTDC_GCR_DRW) - -/* LIPCR register */ - -#define STM32_LTDC_LIPCR_LIPOS LTDC_LIPCR_LIPOS(STM32_LTDC_TWCR_TOTALW) - -/* Configuration ************************************************************/ - -#ifndef CONFIG_STM32_LTDC_DEFBACKLIGHT -# define CONFIG_STM32_LTDC_DEFBACKLIGHT 0xf0 -#endif -#define STM32_LTDC_BACKLIGHT_OFF 0x00 - -/* Color/video formats */ - -/* Layer 1 format */ - -#if defined(CONFIG_STM32_LTDC_L1_L8) -# define STM32_LTDC_L1_BPP 8 -# define STM32_LTDC_L1_COLOR_FMT FB_FMT_RGB8 -# define STM32_LTDC_L1PFCR_PF LTDC_LXPFCR_PF(LTDC_PF_L8) -# define STM32_LTDC_L1_DMA2D_PF DMA2D_PF_L8 -# define STM32_LTDC_L1CMAP -#elif defined(CONFIG_STM32_LTDC_L1_RGB565) -# define STM32_LTDC_L1_BPP 16 -# define STM32_LTDC_L1_COLOR_FMT FB_FMT_RGB16_565 -# define STM32_LTDC_L1PFCR_PF LTDC_LXPFCR_PF(LTDC_PF_RGB565) -# define STM32_LTDC_L1_DMA2D_PF DMA2D_PF_RGB565 -#elif defined(CONFIG_STM32_LTDC_L1_RGB888) -# define STM32_LTDC_L1_BPP 24 -# define STM32_LTDC_L1_COLOR_FMT FB_FMT_RGB24 -# define STM32_LTDC_L1PFCR_PF LTDC_LXPFCR_PF(LTDC_PF_RGB888) -# define STM32_LTDC_L1_DMA2D_PF DMA2D_PF_RGB888 -#elif defined(CONFIG_STM32_LTDC_L1_ARGB8888) -# define STM32_LTDC_L1_BPP 32 -# define STM32_LTDC_L1_COLOR_FMT FB_FMT_RGB32 -# define STM32_LTDC_L1PFCR_PF LTDC_LXPFCR_PF(LTDC_PF_ARGB8888) -# define STM32_LTDC_L1_DMA2D_PF DMA2D_PF_ARGB8888 -#else -# error "LTDC pixel format not supported" -#endif - -/* Layer 2 format */ - -#ifdef CONFIG_STM32_LTDC_L2 -# if defined(CONFIG_STM32_LTDC_L2_L8) -# define STM32_LTDC_L2_BPP 8 -# define STM32_LTDC_L2_COLOR_FMT FB_FMT_RGB8 -# define STM32_LTDC_L2PFCR_PF LTDC_LXPFCR_PF(LTDC_PF_L8) -# define STM32_LTDC_L2_DMA2D_PF DMA2D_PF_L8 -# define STM32_LTDC_L2CMAP -# elif defined(CONFIG_STM32_LTDC_L2_RGB565) -# define STM32_LTDC_L2_BPP 16 -# define STM32_LTDC_L2_COLOR_FMT FB_FMT_RGB16_565 -# define STM32_LTDC_L2PFCR_PF LTDC_LXPFCR_PF(LTDC_PF_RGB565) -# define STM32_LTDC_L2_DMA2D_PF DMA2D_PF_RGB565 -# elif defined(CONFIG_STM32_LTDC_L2_RGB888) -# define STM32_LTDC_L2_BPP 24 -# define STM32_LTDC_L2_COLOR_FMT FB_FMT_RGB24 -# define STM32_LTDC_L2PFCR_PF LTDC_LXPFCR_PF(LTDC_PF_RGB888) -# define STM32_LTDC_L2_DMA2D_PF DMA2D_PF_RGB888 -# elif defined(CONFIG_STM32_LTDC_L2_ARGB8888) -# define STM32_LTDC_L2_BPP 32 -# define STM32_LTDC_L2_COLOR_FMT FB_FMT_RGB32 -# define STM32_LTDC_L2PFCR_PF LTDC_LXPFCR_PF(LTDC_PF_ARGB8888) -# define STM32_LTDC_L2_DMA2D_PF DMA2D_PF_ARGB8888 -# else -# error "LTDC pixel format not supported" -# endif -#endif /* CONFIG_STM32_LTDC_L2 */ - -/* Framebuffer sizes in bytes */ - -#if STM32_LTDC_L1_BPP == 8 -# define STM32_LTDC_L1_STRIDE (STM32_LTDC_WIDTH) -#elif STM32_LTDC_L1_BPP == 16 -# define STM32_LTDC_L1_STRIDE ((STM32_LTDC_WIDTH * 16 + 7) / 8) -#elif STM32_LTDC_L1_BPP == 24 -# define STM32_LTDC_L1_STRIDE ((STM32_LTDC_WIDTH * 24 + 7) / 8) -#elif STM32_LTDC_L1_BPP == 32 -# define STM32_LTDC_L1_STRIDE ((STM32_LTDC_WIDTH * 32 + 7) / 8) -#else -# error Undefined or unrecognized base resolution -#endif - -/* LTDC only supports 8 bit per pixel overall */ - -#define STM32_LTDC_LX_BYPP(n) ((n) / 8) - -#define STM32_LTDC_L1_FBSIZE (STM32_LTDC_L1_STRIDE * STM32_LTDC_HEIGHT) - -#ifdef CONFIG_STM32_LTDC_L2 -# ifndef CONFIG_STM32_LTDC_L2_WIDTH -# define CONFIG_STM32_LTDC_L2_WIDTH STM32_LTDC_WIDTH -# endif - -# if CONFIG_STM32_LTDC_L2_WIDTH > STM32_LTDC_WIDTH -# error Width of Layer 2 exceeds the width of the display -# endif - -# ifndef CONFIG_STM32_LTDC_L2_HEIGHT -# define CONFIG_STM32_LTDC_L2_HEIGHT STM32_LTDC_HEIGHT -# endif - -# if CONFIG_STM32_LTDC_L2_HEIGHT > STM32_LTDC_HEIGHT -# error Height of Layer 2 exceeds the height of the display -# endif - -# if STM32_LTDC_L2_BPP == 8 -# define STM32_LTDC_L2_STRIDE (CONFIG_STM32_LTDC_L2_WIDTH) -# elif STM32_LTDC_L2_BPP == 16 -# define STM32_LTDC_L2_STRIDE ((CONFIG_STM32_LTDC_L2_WIDTH * 16 + 7) / 8) -# elif STM32_LTDC_L2_BPP == 24 -# define STM32_LTDC_L2_STRIDE ((CONFIG_STM32_LTDC_L2_WIDTH * 24 + 7) / 8) -# elif STM32_LTDC_L2_BPP == 32 -# define STM32_LTDC_L2_STRIDE ((CONFIG_STM32_LTDC_L2_WIDTH * 32 + 7) / 8) -# else -# error Undefined or unrecognized base resolution -# endif - -# define STM32_LTDC_L2_FBSIZE (STM32_LTDC_L2_STRIDE * \ - CONFIG_STM32_LTDC_L2_HEIGHT) - -#else -# define STM32_LTDC_L2_FBSIZE (0) -#endif - -/* Total memory used for framebuffers */ - -#define STM32_LTDC_TOTAL_FBSIZE (STM32_LTDC_L1_FBSIZE + \ - STM32_LTDC_L2_FBSIZE) - -/* Debug option */ - -#ifdef CONFIG_STM32_LTDC_REGDEBUG -# define regerr lcderr -# define reginfo lcdinfo -#else -# define regerr(x...) -# define reginfo(x...) -#endif - -/* Preallocated LTDC framebuffers */ - -/* Position the framebuffer memory in the center of the memory set aside. We - * will use any skirts before or after the framebuffer memory as a guard - * against wild framebuffer writes. - */ - -#define STM32_LTDC_BUFFER_SIZE CONFIG_STM32_LTDC_FB_SIZE -#define STM32_LTDC_BUFFER_FREE (STM32_LTDC_BUFFER_SIZE - \ - STM32_LTDC_TOTAL_FBSIZE) -#define STM32_LTDC_BUFFER_START (CONFIG_STM32_LTDC_FB_BASE + \ - STM32_LTDC_BUFFER_FREE/2) - -#if STM32_LTDC_BUFFER_FREE < 0 -# error "STM32_LTDC_BUFFER_SIZE not large enough for frame buffers" -#endif - -/* Layer frame buffer */ - -#define STM32_LTDC_BUFFER_L1 STM32_LTDC_BUFFER_START -#define STM32_LTDC_ENDBUF_L1 (STM32_LTDC_BUFFER_L1 + \ - STM32_LTDC_L1_FBSIZE) - -#ifdef CONFIG_STM32_LTDC_L2 -# define STM32_LTDC_BUFFER_L2 STM32_LTDC_ENDBUF_L1 -# define STM32_LTDC_ENDBUF_L2 (STM32_LTDC_BUFFER_L2 + \ - STM32_LTDC_L2_FBSIZE) -#else -# define STM32_LTDC_ENDBUF_L2 STM32_LTDC_ENDBUF_L1 -#endif - -/* LTDC layer */ - -#ifdef CONFIG_STM32_LTDC_L2 -# define LTDC_NLAYERS 2 -#else -# define LTDC_NLAYERS 1 -#endif - -/* DMA2D layer */ - -#ifdef CONFIG_STM32_DMA2D -# define DMA2D_NLAYERS CONFIG_STM32_DMA2D_NLAYERS -# if DMA2D_NLAYERS < 1 -# error "DMA2D must at least support 1 overlay" -# endif - -#define STM32_DMA2D_WIDTH CONFIG_STM32_DMA2D_LAYER_PPLINE - -# if defined(CONFIG_STM32_DMA2D_L8) -# define STM32_DMA2D_STRIDE (STM32_DMA2D_WIDTH) -# define STM32_DMA2D_BPP 8 -# define STM32_DMA2D_COLOR_FMT DMA2D_PF_L8 -# elif defined(CONFIG_STM32_DMA2D_RGB565) -# define STM32_DMA2D_STRIDE ((STM32_DMA2D_WIDTH * 16 + 7) / 8) -# define STM32_DMA2D_BPP 16 -# define STM32_DMA2D_COLOR_FMT DMA2D_PF_RGB565 -# elif defined(CONFIG_STM32_DMA2D_RGB888) -# define STM32_DMA2D_STRIDE ((STM32_DMA2D_WIDTH * 24 + 7) / 8) -# define STM32_DMA2D_BPP 24 -# define STM32_DMA2D_COLOR_FMT DMA2D_PF_RGB888 -# elif defined(CONFIG_STM32_DMA2D_ARGB8888) -# define STM32_DMA2D_STRIDE ((STM32_DMA2D_WIDTH * 32 + 7) / 8) -# define STM32_DMA2D_BPP 32 -# define STM32_DMA2D_COLOR_FMT DMA2D_PF_ARGB8888 -# else -# error "DMA2D pixel format not supported" -# endif - -# ifdef CONFIG_STM32_DMA2D_LAYER_SHARED -# define STM32_DMA2D_FBSIZE CONFIG_STM32_DMA2D_FB_SIZE -# define STM32_DMA2D_LAYER_SIZE 0 -# else -# define STM32_DMA2D_FBSIZE CONFIG_STM32_DMA2D_FB_SIZE / DMA2D_NLAYERS -# define STM32_DMA2D_LAYER_SIZE STM32_DMA2D_FBSIZE -# if STM32_DMA2D_FBSIZE * DMA2D_NLAYERS > CONFIG_STM32_DMA2D_FB_SIZE -# error "DMA2D framebuffer size to small for configured number of overlays" -# endif -# endif /* CONFIG_STM32_DMA2D_LAYER_SHARED */ - -# define STM32_DMA2D_HEIGHT STM32_DMA2D_FBSIZE / STM32_DMA2D_STRIDE - -# define STM32_DMA2D_BUFFER_START CONFIG_STM32_DMA2D_FB_BASE -#else -# define DMA2D_NLAYERS 0 -#endif /* CONFIG_STM32_DMA2D */ - -#define LTDC_NOVERLAYS LTDC_NLAYERS + DMA2D_NLAYERS - -/* Dithering */ - -#ifndef CONFIG_STM32_LTDC_DITHER_RED -# define STM32_LTDC_DITHER_RED 0 -#else -# define STM32_LTDC_DITHER_RED CONFIG_STM32_LTDC_DITHER_RED -#endif -#ifndef CONFIG_STM32_LTDC_DITHER_GREEN -# define STM32_LTDC_DITHER_GREEN 0 -#else -# define STM32_LTDC_DITHER_GREEN CONFIG_STM32_LTDC_DITHER_GREEN -#endif -#ifndef CONFIG_STM32_LTDC_DITHER_BLUE -# define STM32_LTDC_DITHER_BLUE 0 -#else -# define STM32_LTDC_DITHER_BLUE CONFIG_STM32_LTDC_DITHER_BLUE -#endif - -/* Background color */ - -#ifndef CONFIG_STM32_LTDC_BACKCOLOR -# define STM32_LTDC_BACKCOLOR 0 -#else -# define STM32_LTDC_BACKCOLOR CONFIG_STM32_LTDC_BACKCOLOR -#endif - -/* Layer default color */ - -#ifdef CONFIG_STM32_LTDC_L1_COLOR -# define STM32_LTDC_L1_COLOR CONFIG_STM32_LTDC_L1_COLOR -#else -# define STM32_LTDC_L1_COLOR 0x000000 -#endif - -#ifdef CONFIG_STM32_LTDC_L2 -# ifdef CONFIG_STM32_LTDC_L2_COLOR -# define STM32_LTDC_L2_COLOR CONFIG_STM32_LTDC_L2_COLOR -# else -# define STM32_LTDC_L2_COLOR 0x000000 -# endif -#endif - -/* Internal operation flags */ - -#define LTDC_LAYER_SETAREA (1 << 0) /* Change visible area */ -#define LTDC_LAYER_SETALPHAVALUE (1 << 1) /* Change constant alpha value */ -#define LTDC_LAYER_SETBLENDMODE (1 << 2) /* Change blendmode */ -#define LTDC_LAYER_SETCOLORKEY (1 << 3) /* Change color key */ -#define LTDC_LAYER_ENABLECOLORKEY (1 << 4) /* Enable colorkey */ -#define LTDC_LAYER_SETCOLOR (1 << 5) /* Change default color */ -#define LTDC_LAYER_SETENABLE (1 << 6) /* Change enabled state */ -#define LTDC_LAYER_ENABLE (1 << 7) /* Enable the layer */ - -/* Layer initializing state */ - -#define LTDC_LAYER_INIT LTDC_LAYER_SETAREA | \ - LTDC_LAYER_SETALPHAVALUE | \ - LTDC_LAYER_SETBLENDMODE | \ - LTDC_LAYER_SETCOLORKEY | \ - LTDC_LAYER_SETCOLOR | \ - LTDC_LAYER_SETENABLE | \ - LTDC_LAYER_ENABLE - -/* Blendfactor reset values for flip operation */ - -#define STM32_LTDC_BF1_RESET 6 -#define STM32_LTDC_BF2_RESET 7 - -/* Check pixel format support by DMA2D driver */ - -#ifdef CONFIG_STM32_DMA2D -# if defined(CONFIG_STM32_LTDC_L1_L8) || \ - defined(CONFIG_STM32_LTDC_L2_L8) -# if !defined(CONFIG_STM32_DMA2D_L8) -# error "DMA2D must support FB_FMT_RGB8 pixel format" -# endif -# endif -# if defined(CONFIG_STM32_LTDC_L1_RGB565) || \ - defined(CONFIG_STM32_LTDC_L2_RGB565) -# if !defined(CONFIG_STM32_DMA2D_RGB565) -# error "DMA2D must support FB_FMT_RGB16_565 pixel format" -# endif -# endif -# if defined(CONFIG_STM32_LTDC_L1_RGB888) || \ - defined(CONFIG_STM32_LTDC_L2_RGB888) -# if !defined(CONFIG_STM32_DMA2D_RGB888) -# error "DMA2D must support FB_FMT_RGB24 pixel format" -# endif -# endif -# if defined(CONFIG_STM32_LTDC_L1_ARGB8888) || \ - defined(CONFIG_STM32_LTDC_L2_ARGB8888) -# if !defined(CONFIG_STM32_DMA2D_ARGB8888) -# error "DMA2D must support FB_FMT_RGB32 pixel format" -# endif -# endif -#endif - -/* Calculate the size of the layers clut table */ - -#ifdef CONFIG_STM32_FB_CMAP -# if defined(CONFIG_STM32_DMA2D) && !defined(CONFIG_STM32_DMA2D_L8) -# error "DMA2D must also support L8 CLUT pixel format if supported by LTDC" -# endif -# ifdef STM32_LTDC_L1CMAP -# ifdef CONFIG_STM32_FB_TRANSPARENCY -# define STM32_LAYER_CLUT_SIZE STM32_LTDC_NCLUT * sizeof(uint32_t) -# else -# define STM32_LAYER_CLUT_SIZE STM32_LTDC_NCLUT * 3 * sizeof(uint8_t) -# endif -# endif -# ifdef STM32_LTDC_L2CMAP -# undef STM32_LAYER_CLUT_SIZE -# ifdef CONFIG_STM32_FB_TRANSPARENCY -# define STM32_LAYER_CLUT_SIZE STM32_LTDC_NCLUT * sizeof(uint32_t) * 2 -# else -# define STM32_LAYER_CLUT_SIZE STM32_LTDC_NCLUT * 3 * sizeof(uint8_t) * 2 -# endif -# endif -#endif - -#ifndef CONFIG_STM32_FB_CMAP -# if defined(STM32_LTDC_L1CMAP) || defined(STM32_LTDC_L2CMAP) -# undef STM32_LTDC_L1CMAP -# undef STM32_LTDC_L2CMAP -# error "Enable cmap to support the configured layer format!" -# endif -#endif - -/* Layer clut rgb value positioning */ - -#define LTDC_L1CLUT_REDOFFSET 0 -#define LTDC_L1CLUT_GREENOFFSET 256 -#define LTDC_L1CLUT_BLUEOFFSET 512 -#define LTDC_L2CLUT_REDOFFSET 768 -#define LTDC_L2CLUT_GREENOFFSET 1024 -#define LTDC_L2CLUT_BLUEOFFSET 1280 - -/* Layer argb clut register position */ - -#define LTDC_CLUT_ADD(n) ((uint32_t)(n) << 24) -#define LTDC_CLUT_ALPHA(n) LTDC_CLUT_ADD(n) -#define LTDC_CLUT_RED(n) ((uint32_t)(n) << 16) -#define LTDC_CLUT_GREEN(n) ((uint32_t)(n) << 8) -#define LTDC_CLUT_BLUE(n) ((uint32_t)(n) << 0) -#define LTDC_CLUT_RGB888_MASK 0xffffff - -/* Layer argb cmap conversion */ - -#define LTDC_CMAP_ALPHA(n) ((uint32_t)(n) >> 24) -#define LTDC_CMAP_RED(n) ((uint32_t)(n) >> 16) -#define LTDC_CMAP_GREEN(n) ((uint32_t)(n) >> 8) -#define LTDC_CMAP_BLUE(n) ((uint32_t)(n) >> 0) - -/* Hardware acceleration support */ - -/* Acceleration support for LTDC overlays */ - -#ifdef CONFIG_STM32_LTDC_L1_CHROMAKEYEN -# define STM32_LTDC_L1_CHROMAEN true -# define STM32_LTDC_L1_CHROMAKEY CONFIG_STM32_LTDC_L1_CHROMAKEY -# define LTDC_LTDC_ACCL_L1 FB_ACCL_TRANSP | FB_ACCL_CHROMA -#else -# define STM32_LTDC_L1_CHROMAEN false -# define STM32_LTDC_L1_CHROMAKEY 0 -# define LTDC_LTDC_ACCL_L1 FB_ACCL_TRANSP -#endif - -#ifdef CONFIG_STM32_LTDC_L2_CHROMAKEYEN -# define STM32_LTDC_L2_CHROMAEN true -# define STM32_LTDC_L2_CHROMAKEY CONFIG_STM32_LTDC_L2_CHROMAKEY -# define LTDC_LTDC_ACCL_L2 FB_ACCL_TRANSP | FB_ACCL_CHROMA -#else -# define STM32_LTDC_L2_CHROMAEN false -# define STM32_LTDC_L2_CHROMAKEY 0 -# define LTDC_LTDC_ACCL_L2 FB_ACCL_TRANSP -#endif - -#ifdef CONFIG_STM32_DMA2D -# ifdef CONFIG_FB_OVERLAY_BLIT -# ifdef CONFIG_STM32_FB_CMAP -# define LTDC_BLIT_ACCL FB_ACCL_BLIT -# else -# define LTDC_BLIT_ACCL FB_ACCL_BLIT | FB_ACCL_BLEND -# endif /* CONFIG_STM32_FB_CMAP */ -# else -# define LTDC_BLIT_ACCL 0 -# endif /* CONFIG_FB_OVERLAY_BLIT */ - -# ifdef CONFIG_STM32_FB_CMAP -# define LTDC_DMA2D_ACCL LTDC_BLIT_ACCL -# else -# define LTDC_DMA2D_ACCL FB_ACCL_COLOR | LTDC_BLIT_ACCL -# endif /* CONFIG_STM32_FB_CMAP */ -#else -# define LTDC_DMA2D_ACCL 0 -#endif /* CONFIG_STM32_DMA2D */ - -#define LTDC_L1_ACCL LTDC_LTDC_ACCL_L1 | LTDC_DMA2D_ACCL -#ifdef CONFIG_STM32_LTDC_L2 -# define LTDC_L2_ACCL LTDC_LTDC_ACCL_L2 | LTDC_DMA2D_ACCL -#endif - -/* Acceleration support for DMA2D overlays */ - -#ifdef CONFIG_STM32_FB_CMAP -# ifdef CONFIG_FB_OVERLAY_BLIT -# define DMA2D_ACCL FB_ACCL_BLIT | FB_ACCL_AREA -# else -# define DMA2D_ACCL FB_ACCL_AREA -# endif -#else -# ifdef CONFIG_FB_OVERLAY_BLIT -# define DMA2D_ACCL FB_ACCL_AREA | \ - FB_ACCL_TRANSP | \ - FB_ACCL_COLOR | \ - FB_ACCL_BLIT | \ - FB_ACCL_BLEND -# else -# define DMA2D_ACCL FB_ACCL_AREA | \ - FB_ACCL_TRANSP | \ - FB_ACCL_COLOR -# endif -#endif - -/* Color normalization */ - -#if defined(CONFIG_STM32_LTDC_L1_RGB565) -# define RGB888_R(x) (((((x) >> 11) & 0x1f) * 527 + 23) >> 6) -# define RGB888_G(x) (((((x) >> 5) & 0x3f) * 259 + 33) >> 6) -# define RGB888_B(x) ((((x) & 0x1f) * 527 + 23) >> 6) -# define ARGB8888(x) ((RGB888_R(x) << 16) | \ - (RGB888_G(x) << 8) | \ - RGB888_B(x)) -#else -# define ARGB8888(x) (x) -#endif - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/* This enumeration names each layer supported by the hardware */ - -enum stm32_layer_e -{ - LTDC_LAYER_L1 = 0, /* LCD Layer 1 */ - LTDC_LAYER_L2, /* LCD Layer 2 */ -}; - -/* LTDC General layer information */ - -struct stm32_ltdc_s -{ - int layerno; /* layer number */ - -#ifdef CONFIG_FB_OVERLAY - struct fb_overlayinfo_s oinfo; /* Overlay info */ -#endif - -#ifdef CONFIG_STM32_DMA2D - struct stm32_dma2d_overlay_s dma2dinfo; /* Overlay info for DMA2D */ -#endif - - mutex_t *lock; /* Layer exclusive access */ -}; - -/* This structure provides the overall state of the LTDC layer */ - -struct stm32_ltdcdev_s -{ - /* Framebuffer interface */ - - struct fb_vtable_s vtable; - - /* Framebuffer video information */ - - struct fb_videoinfo_s vinfo; - - /* Framebuffer plane information */ - - struct fb_planeinfo_s pinfo; - - /* Cmap information */ - -#ifdef CONFIG_STM32_FB_CMAP - struct fb_cmap_s cmap; -#endif - - /* Layer information */ - - struct stm32_ltdc_s layer[LTDC_NOVERLAYS]; - -#ifdef CONFIG_STM32_DMA2D - /* Interface to the dma2d controller */ - - struct dma2d_layer_s *dma2d; -#endif -}; - -/* Interrupt handling */ - -struct stm32_interrupt_s -{ - int irq; /* irq number */ - int error; /* Interrupt error */ - sem_t *sem; /* Semaphore for waiting for irq */ -}; - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -/* Overall LTDC helper */ - -static void stm32_ltdc_enable(bool enable); -static void stm32_ltdc_gpioconfig(void); -static void stm32_ltdc_periphconfig(void); -static void stm32_ltdc_bgcolor(uint32_t rgb); -static void stm32_ltdc_dither(bool enable, uint8_t red, - uint8_t green, uint8_t blue); -static int stm32_ltdcirq(int irq, void *context, void *arg); -static int stm32_ltdc_waitforirq(void); -static int stm32_ltdc_reload(uint8_t value, bool waitvblank); - -/* Helper for layer register configuration */ - -static void stm32_ltdc_lpixelformat(struct stm32_ltdc_s *layer); -static void stm32_ltdc_lframebuffer(struct stm32_ltdc_s *layer); -static void stm32_ltdc_lenable(struct stm32_ltdc_s *layer, bool enable); -static void stm32_ltdc_ldefaultcolor(struct stm32_ltdc_s *layer, - uint32_t rgb); -static void stm32_ltdc_ltransp(struct stm32_ltdc_s *layer, - uint8_t transp, - uint32_t mode); -static void stm32_ltdc_lchromakey(struct stm32_ltdc_s *layer, - uint32_t chromakey); -static void stm32_ltdc_lchromakeyenable(struct stm32_ltdc_s *layer, - bool enable); -static void stm32_ltdc_linit(uint8_t lid); - -#ifdef CONFIG_STM32_DMA2D -static void stm32_ltdc_dma2dlinit(void); - -# ifdef CONFIG_FB_OVERLAY_BLIT -static bool stm32_ltdc_lvalidate(const struct stm32_ltdc_s *layer, - const struct fb_area_s *area); -# endif -#endif - -#ifdef CONFIG_STM32_FB_CMAP -static void stm32_ltdc_lputclut(struct stm32_ltdc_s *layer, - const struct fb_cmap_s *cmap); -static void stm32_ltdc_lgetclut(struct stm32_ltdc_s *layer, - struct fb_cmap_s *cmap); -static void stm32_ltdc_lclutenable(struct stm32_ltdc_s *layer, - bool enable); -#endif - -static void stm32_ltdc_lclear(uint8_t overlayno); - -/* Framebuffer interface */ - -static int stm32_getvideoinfo(struct fb_vtable_s *vtable, - struct fb_videoinfo_s *vinfo); -static int stm32_getplaneinfo(struct fb_vtable_s *vtable, - int planeno, - struct fb_planeinfo_s *pinfo); - -/* The following is provided only if the video hardware supports RGB color - * mapping - */ - -#ifdef CONFIG_STM32_FB_CMAP -static int stm32_getcmap(struct fb_vtable_s *vtable, - struct fb_cmap_s *cmap); -static int stm32_putcmap(struct fb_vtable_s *vtable, - const struct fb_cmap_s *cmap); -#endif - -/* The following is provided only if the video hardware signals vertical - * synchronisation - */ - -#ifdef CONFIG_FB_SYNC -static int stm32_waitforvsync(struct fb_vtable_s *vtable); -#endif - -/* The following is provided only if the video hardware supports overlays */ - -#ifdef CONFIG_FB_OVERLAY -static int stm32_getoverlayinfo(struct fb_vtable_s *vtable, - int overlayno, - struct fb_overlayinfo_s *oinfo); -static int stm32_settransp(struct fb_vtable_s *vtable, - const struct fb_overlayinfo_s *oinfo); -static int stm32_setchromakey(struct fb_vtable_s *vtable, - const struct fb_overlayinfo_s *oinfo); -static int stm32_setcolor(struct fb_vtable_s *vtable, - const struct fb_overlayinfo_s *oinfo); -static int stm32_setblank(struct fb_vtable_s *vtable, - const struct fb_overlayinfo_s *oinfo); -static int stm32_setarea(struct fb_vtable_s *vtable, - const struct fb_overlayinfo_s *oinfo); - -/* The following is provided only if the video hardware supports blit and - * blend operation - */ - -# ifdef CONFIG_FB_OVERLAY_BLIT -static int stm32_blit(struct fb_vtable_s *vtable, - const struct fb_overlayblit_s *blit); -static int stm32_blend(struct fb_vtable_s *vtable, - const struct fb_overlayblend_s *blend); -# endif /* CONFIG_FB_OVERLAY_BLIT */ -#endif /* CONFIG_FB_OVERLAY */ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* PIO pin configurations */ - -static const uint32_t g_ltdcpins[] = -{ - GPIO_LTDC_R4, GPIO_LTDC_R5, GPIO_LTDC_R6, GPIO_LTDC_R7, - GPIO_LTDC_G4, GPIO_LTDC_G5, GPIO_LTDC_G6, GPIO_LTDC_G7, - GPIO_LTDC_B4, GPIO_LTDC_B5, GPIO_LTDC_B6, GPIO_LTDC_B7, -#if BOARD_LTDC_OUTPUT_BPP > 12 - GPIO_LTDC_R3, GPIO_LTDC_G2, GPIO_LTDC_G3, GPIO_LTDC_B3, -# if BOARD_LTDC_OUTPUT_BPP > 16 - GPIO_LTDC_R2, GPIO_LTDC_B2, -# if BOARD_LTDC_OUTPUT_BPP > 18 - GPIO_LTDC_R0, GPIO_LTDC_R1, GPIO_LTDC_G0, GPIO_LTDC_G1, - GPIO_LTDC_B0, GPIO_LTDC_B1, -# endif -# endif -#endif - GPIO_LTDC_VSYNC, GPIO_LTDC_HSYNC, GPIO_LTDC_DE, GPIO_LTDC_CLK -}; - -#define STM32_LTDC_NPINCONFIGS (sizeof(g_ltdcpins) / sizeof(uint32_t)) - -#ifdef CONFIG_STM32_FB_CMAP -/* The layers clut table entries */ - -static uint8_t g_redclut[STM32_LTDC_NCLUT]; -static uint8_t g_greenclut[STM32_LTDC_NCLUT]; -static uint8_t g_blueclut[STM32_LTDC_NCLUT]; -# ifdef CONFIG_STM32_FB_TRANSPARENCY -static uint8_t g_transpclut[STM32_LTDC_NCLUT]; -# endif -#endif /* CONFIG_STM32_FB_CMAP */ - -/* The LTDC mutex that enforces mutually exclusive access */ - -static mutex_t g_lock = NXMUTEX_INITIALIZER; - -/* The semaphore for interrupt handling */ - -static sem_t g_semirq = SEM_INITIALIZER(0); - -/* This structure provides irq handling */ - -static struct stm32_interrupt_s g_interrupt = -{ - .irq = STM32_IRQ_LTDCINT, - .error = OK, - .sem = &g_semirq -}; - -/* This structure provides the internal interface */ - -static struct stm32_ltdcdev_s g_vtable = -{ - .vtable = - { - .getvideoinfo = stm32_getvideoinfo, - .getplaneinfo = stm32_getplaneinfo -#ifdef CONFIG_FB_SYNC - , - .waitforvsync = stm32_waitforvsync -#endif - -#ifdef CONFIG_STM32_FB_CMAP - , - .getcmap = stm32_getcmap, - .putcmap = stm32_putcmap -#endif - -#ifdef CONFIG_FB_OVERLAY - , - .getoverlayinfo = stm32_getoverlayinfo, - .settransp = stm32_settransp, - .setchromakey = stm32_setchromakey, - .setcolor = stm32_setcolor, - .setblank = stm32_setblank, - .setarea = stm32_setarea -# ifdef CONFIG_FB_OVERLAY_BLIT - , - .blit = stm32_blit, - .blend = stm32_blend -# endif -#endif /* CONFIG_FB_OVERLAY */ - }, -#ifdef CONFIG_STM32_LTDC_L2 - .pinfo = - { - .fbmem = (uint8_t *)STM32_LTDC_BUFFER_L2, - .fblen = STM32_LTDC_L2_FBSIZE, - .stride = STM32_LTDC_L2_STRIDE, - .display = 0, - .bpp = STM32_LTDC_L2_BPP - }, - .vinfo = - { - .fmt = STM32_LTDC_L2_COLOR_FMT, - .xres = STM32_LTDC_WIDTH, - .yres = STM32_LTDC_HEIGHT, - .nplanes = 1, -# ifdef CONFIG_FB_OVERLAY - .noverlays = LTDC_NOVERLAYS -# endif - } -#else - .pinfo = - { - .fbmem = (uint8_t *)STM32_LTDC_BUFFER_L1, - .fblen = STM32_LTDC_L1_FBSIZE, - .stride = STM32_LTDC_L1_STRIDE, - .display = 0, - .bpp = STM32_LTDC_L1_BPP - }, - .vinfo = - { - .fmt = STM32_LTDC_L1_COLOR_FMT, - .xres = STM32_LTDC_WIDTH, - .yres = STM32_LTDC_HEIGHT, - .nplanes = 1, -# ifdef CONFIG_FB_OVERLAY - .noverlays = LTDC_NOVERLAYS -# endif - } -#endif /* CONFIG_STM32_LTDC_L2 */ - , -#ifdef CONFIG_STM32_FB_CMAP - .cmap = - { - .first = 0, - .len = STM32_LTDC_NCLUT, - .red = g_redclut, - .green = g_greenclut, - .blue = g_blueclut, -# ifdef CONFIG_STM32_FB_TRANSPARENCY - .transp = g_transpclut -# endif - } - , -#endif - .layer[LTDC_LAYER_L1] = - { - .layerno = LTDC_LAYER_L1, -#ifdef CONFIG_FB_OVERLAY - .oinfo = - { - .fbmem = (uint8_t *)STM32_LTDC_BUFFER_L1, - .fblen = STM32_LTDC_L1_FBSIZE, - .stride = STM32_LTDC_L1_STRIDE, - .overlay = LTDC_LAYER_L1, - .bpp = STM32_LTDC_L1_BPP, - .blank = 0, - .chromakey = 0, - .color = 0, - .transp = - { - .transp = 0xff, - .transp_mode = FB_CONST_ALPHA - }, - .sarea = - { - .x = 0, - .y = 0, - .w = STM32_LTDC_WIDTH, - .h = STM32_LTDC_HEIGHT - }, - .accl = LTDC_L1_ACCL - }, -#endif - -#ifdef CONFIG_STM32_DMA2D - .dma2dinfo = - { - .fmt = STM32_LTDC_L1_DMA2D_PF, - .transp_mode = STM32_DMA2D_PFCCR_AM_NONE, - .xres = STM32_LTDC_WIDTH, - .yres = STM32_LTDC_HEIGHT, - .oinfo = &g_vtable.layer[LTDC_LAYER_L1].oinfo - }, -#endif - .lock = &g_lock - } -#ifdef CONFIG_STM32_LTDC_L2 - , - .layer[LTDC_LAYER_L2] = - { - .layerno = LTDC_LAYER_L2, -#ifdef CONFIG_FB_OVERLAY - .oinfo = - { - .overlay = LTDC_LAYER_L2, - .fbmem = (uint8_t *)STM32_LTDC_BUFFER_L2, - .fblen = STM32_LTDC_L2_FBSIZE, - .stride = STM32_LTDC_L2_STRIDE, - .bpp = STM32_LTDC_L2_BPP, - .blank = 0, - .chromakey = 0, - .color = 0, - .transp = - { - .transp = 0xff, - .transp_mode = FB_CONST_ALPHA - }, - .sarea = - { - .x = 0, - .y = 0, - .w = STM32_LTDC_WIDTH, - .h = STM32_LTDC_HEIGHT - }, - .accl = LTDC_L2_ACCL - }, -#endif - -#ifdef CONFIG_STM32_DMA2D - .dma2dinfo = - { - .fmt = STM32_LTDC_L2_DMA2D_PF, - .transp_mode = STM32_DMA2D_PFCCR_AM_NONE, - .xres = STM32_LTDC_WIDTH, - .yres = STM32_LTDC_HEIGHT, - .oinfo = &g_vtable.layer[LTDC_LAYER_L2].oinfo - }, -#endif - .lock = &g_lock - } -#endif -}; - -/* Configuration lookup tables */ - -/* LTDC width */ - -static const uint32_t stm32_width_layer_t[LTDC_NLAYERS] = -{ - STM32_LTDC_WIDTH -#ifdef CONFIG_STM32_LTDC_L2 - , STM32_LTDC_WIDTH -#endif -}; - -/* LTDC height */ - -static const uint32_t stm32_height_layer_t[LTDC_NLAYERS] = -{ - STM32_LTDC_HEIGHT -#ifdef CONFIG_STM32_LTDC_L2 - , STM32_LTDC_HEIGHT -#endif -}; - -/* LTDC stride */ - -static const uint32_t stm32_stride_layer_t[LTDC_NLAYERS] = -{ - STM32_LTDC_L1_STRIDE -#ifdef CONFIG_STM32_LTDC_L2 - , STM32_LTDC_L2_STRIDE -#endif -}; - -/* LTDC bpp */ - -static const uint32_t stm32_bpp_layer_t[LTDC_NLAYERS] = -{ - STM32_LTDC_L1_BPP -#ifdef CONFIG_STM32_LTDC_L2 - , STM32_LTDC_L2_BPP -#endif -}; - -/* LTDC framebuffer len */ - -static const uint32_t stm32_fblen_layer_t[LTDC_NLAYERS] = -{ - STM32_LTDC_L1_FBSIZE -#ifdef CONFIG_STM32_LTDC_L2 - , STM32_LTDC_L2_FBSIZE -#endif -}; - -/* LTDC framebuffer */ - -static const uint32_t stm32_fbmem_layer_t[LTDC_NLAYERS] = -{ - STM32_LTDC_BUFFER_L1 -#ifdef CONFIG_STM32_LTDC_L2 - , STM32_LTDC_BUFFER_L2 -#endif -}; - -/* LTDC default color lookup table */ - -static const uint32_t stm32_defaultcolor_layer_t[LTDC_NLAYERS] = -{ - STM32_LTDC_L1_COLOR -#ifdef CONFIG_STM32_LTDC_L2 - , STM32_LTDC_L2_COLOR -#endif -}; - -/* LTDC default chromakey */ - -static const uint32_t stm32_chromakey_layer_t[LTDC_NLAYERS] = -{ - STM32_LTDC_L1_CHROMAKEY -#ifdef CONFIG_STM32_LTDC_L2 - , STM32_LTDC_L2_CHROMAKEY -#endif -}; - -/* LTDC chromakey enabled state */ - -static const bool stm32_chromakeyen_layer_t[LTDC_NLAYERS] = -{ - STM32_LTDC_L1_CHROMAEN -#ifdef CONFIG_STM32_LTDC_L2 - , STM32_LTDC_L2_CHROMAEN -#endif -}; - -/* LTDC pixel format lookup table */ - -static const uint32_t stm32_fmt_layer_t[LTDC_NLAYERS] = -{ - STM32_LTDC_L1PFCR_PF -#ifdef CONFIG_STM32_LTDC_L2 - , STM32_LTDC_L2PFCR_PF -#endif -}; - -/* Register lookup tables */ - -/* LTDC_LxCR */ - -static const uintptr_t stm32_cr_layer_t[LTDC_NLAYERS] = -{ - STM32_LTDC_L1CR -#ifdef CONFIG_STM32_LTDC_L2 - , STM32_LTDC_L2CR -#endif -}; - -/* LTDC_LxWHPCR */ - -static const uintptr_t stm32_whpcr_layer_t[LTDC_NLAYERS] = -{ - STM32_LTDC_L1WHPCR -#ifdef CONFIG_STM32_LTDC_L2 - , STM32_LTDC_L2WHPCR -#endif -}; - -/* LTDC_LxWVPCR */ - -static const uintptr_t stm32_wvpcr_layer_t[LTDC_NLAYERS] = -{ - STM32_LTDC_L1WVPCR -#ifdef CONFIG_STM32_LTDC_L2 - , STM32_LTDC_L2WVPCR -#endif -}; - -/* LTDC_LxPFCR */ - -static const uintptr_t stm32_pfcr_layer_t[LTDC_NLAYERS] = -{ - STM32_LTDC_L1PFCR -#ifdef CONFIG_STM32_LTDC_L2 - , STM32_LTDC_L2PFCR -#endif -}; - -/* LTDC_LxDCCR */ - -static const uintptr_t stm32_dccr_layer_t[LTDC_NLAYERS] = -{ - STM32_LTDC_L1DCCR -#ifdef CONFIG_STM32_LTDC_L2 - , STM32_LTDC_L2DCCR -#endif -}; - -/* LTDC_LxCKCR */ - -static const uintptr_t stm32_ckcr_layer_t[LTDC_NLAYERS] = -{ - STM32_LTDC_L1CKCR -#ifdef CONFIG_STM32_LTDC_L2 - , STM32_LTDC_L2CKCR -#endif -}; - -/* LTDC_LxCACR */ - -static const uintptr_t stm32_cacr_layer_t[LTDC_NLAYERS] = -{ - STM32_LTDC_L1CACR -#ifdef CONFIG_STM32_LTDC_L2 - , STM32_LTDC_L2CACR -#endif -}; - -/* LTDC_LxBFCR */ - -static const uintptr_t stm32_bfcr_layer_t[LTDC_NLAYERS] = -{ - STM32_LTDC_L1BFCR -#ifdef CONFIG_STM32_LTDC_L2 - , STM32_LTDC_L2BFCR -#endif -}; - -/* LTDC_LxCFBAR */ - -static const uintptr_t stm32_cfbar_layer_t[LTDC_NLAYERS] = -{ - STM32_LTDC_L1CFBAR -#ifdef CONFIG_STM32_LTDC_L2 - , STM32_LTDC_L2CFBAR -#endif -}; - -/* LTDC_LxCFBLR */ - -static const uintptr_t stm32_cfblr_layer_t[LTDC_NLAYERS] = -{ - STM32_LTDC_L1CFBLR -#ifdef CONFIG_STM32_LTDC_L2 - , STM32_LTDC_L2CFBLR -#endif -}; - -/* LTDC_LxCFBLNR */ - -static const uintptr_t stm32_cfblnr_layer_t[LTDC_NLAYERS] = -{ - STM32_LTDC_L1CFBLNR -#ifdef CONFIG_STM32_LTDC_L2 - , STM32_LTDC_L2CFBLNR -#endif -}; - -/* LTDC_LxCLUTWR */ - -#ifdef CONFIG_STM32_FB_CMAP -static const uintptr_t stm32_clutwr_layer_t[LTDC_NLAYERS] = -{ - STM32_LTDC_L1CLUTWR -# ifdef CONFIG_STM32_LTDC_L2 - , STM32_LTDC_L2CLUTWR -# endif -}; -#endif /* CONFIG_STM32_FB_CMAP */ - -/* The initialized state of the driver */ - -static bool g_initialized; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_ltdc_gpioconfig - * - * Description: - * Configure GPIO pins for use with the LTDC - * - ****************************************************************************/ - -static void stm32_ltdc_gpioconfig(void) -{ - int i; - - lcdinfo("Configuring pins\n"); - - /* Configure each pin */ - - for (i = 0; i < STM32_LTDC_NPINCONFIGS; i++) - { - reginfo("set gpio%d = %08" PRIx32 "\n", i, g_ltdcpins[i]); - stm32_configgpio(g_ltdcpins[i]); - } -} - -/**************************************************************************** - * Name: stm32_ltdc_periphconfig - * - * Description: - * Configures the synchronous timings - * Configures the synchronous signals and clock polarity - * - ****************************************************************************/ - -static void stm32_ltdc_periphconfig(void) -{ - uint32_t regval; - - /* Configure GPIO's */ - - stm32_ltdc_gpioconfig(); - - /* Configure APB2 LTDC clock external */ - - reginfo("configured RCC_APB2ENR=%08" PRIx32 "\n", - getreg32(STM32_RCC_APB2ENR)); - - /* Configure the SAI PLL external to provide the LCD_CLK */ - - reginfo("configured RCC_PLLSAI=%08" PRIx32 "\n", - getreg32(STM32_RCC_PLLSAICFGR)); - - /* Configure dedicated clock external */ - - reginfo("configured RCC_DCKCFGR=%08" PRIx32 "\n", - getreg32(STM32_RCC_DCKCFGR)); - - /* Configure LTDC_SSCR */ - - regval = (STM32_LTDC_SSCR_VSH | STM32_LTDC_SSCR_HSW); - reginfo("set LTDC_SSCR=%08" PRIx32 "\n", regval); - putreg32(regval, STM32_LTDC_SSCR); - reginfo("configured LTDC_SSCR=%08" PRIx32 "\n", getreg32(STM32_LTDC_SSCR)); - - /* Configure LTDC_BPCR */ - - regval = (STM32_LTDC_BPCR_AVBP | STM32_LTDC_BPCR_AHBP); - reginfo("set LTDC_BPCR=%08" PRIx32 "\n", regval); - putreg32(regval, STM32_LTDC_BPCR); - reginfo("configured LTDC_BPCR=%08" PRIx32 "\n", getreg32(STM32_LTDC_BPCR)); - - /* Configure LTDC_AWCR */ - - regval = (STM32_LTDC_AWCR_AAH | STM32_LTDC_AWCR_AAW); - reginfo("set LTDC_AWCR=%08" PRIx32 "\n", regval); - putreg32(regval, STM32_LTDC_AWCR); - reginfo("configured LTDC_AWCR=%08" PRIx32 "\n", getreg32(STM32_LTDC_AWCR)); - - /* Configure LTDC_TWCR */ - - regval = (STM32_LTDC_TWCR_TOTALH | STM32_LTDC_TWCR_TOTALW); - reginfo("set LTDC_TWCR=%08" PRIx32 "\n", regval); - putreg32(regval, STM32_LTDC_TWCR); - reginfo("configured LTDC_TWCR=%08" PRIx32 "\n", getreg32(STM32_LTDC_TWCR)); - - /* Configure LTDC_GCR */ - - regval = getreg32(STM32_LTDC_GCR); - regval &= ~(LTDC_GCR_PCPOL | LTDC_GCR_DEPOL | LTDC_GCR_VSPOL | - LTDC_GCR_HSPOL); - regval |= (STM32_LTDC_GCR_PCPOL | STM32_LTDC_GCR_DEPOL | - STM32_LTDC_GCR_VSPOL | STM32_LTDC_GCR_HSPOL); - - reginfo("set LTDC_GCR=%08" PRIx32 "\n", regval); - putreg32(regval, STM32_LTDC_GCR); - reginfo("configured LTDC_GCR=%08" PRIx32 "\n", getreg32(STM32_LTDC_GCR)); -} - -/**************************************************************************** - * Name: stm32_ltdc_ldefaultcolor - * - * Description: - * Configures layer default color. - * - * Input Parameters: - * layer - Reference to the layer control structure - * rgb - RGB888 background color - * - ****************************************************************************/ - -static void stm32_ltdc_ldefaultcolor(struct stm32_ltdc_s *layer, - uint32_t rgb) -{ - DEBUGASSERT(layer->layerno < LTDC_NLAYERS); - reginfo("set LTDC_L%dDCCR=%08" PRIx32 "\n", layer->layerno + 1, rgb); - - putreg32(rgb, stm32_dccr_layer_t[layer->layerno]); - - /* Reload shadow register */ - - stm32_ltdc_reload(LTDC_SRCR_IMR, false); - - reginfo("configured LTDC_L%dDCCR=%08" PRIx32 "\n", layer->layerno + 1, - getreg32(STM32_LTDC_BCCR)); -} - -/**************************************************************************** - * Name: stm32_ltdc_bgcolor - * - * Description: - * Configures background color of the LCD controller. - * - * Input Parameters: - * rgb - RGB888 background color - * - ****************************************************************************/ - -static void stm32_ltdc_bgcolor(uint32_t rgb) -{ - reginfo("set LTDC_BCCR=%08" PRIx32 "\n", rgb); - putreg32(rgb, STM32_LTDC_BCCR); - reginfo("configured LTDC_BCCR=%08" PRIx32 "\n", getreg32(STM32_LTDC_BCCR)); -} - -/**************************************************************************** - * Name: stm32_ltdc_dither - * - * Description: - * Configures dither settings of the LCD controller. - * - * Input Parameters: - * enable - Enable dithering - * red - Red dither width - * green - Green dither width - * blue - Blue dither width - * - ****************************************************************************/ - -static void stm32_ltdc_dither(bool enable, uint8_t red, - uint8_t green, uint8_t blue) -{ - uint32_t regval; - - regval = getreg32(STM32_LTDC_GCR); - - if (enable == true) - { - regval |= LTDC_GCR_DEN; - } - else - { - regval &= ~LTDC_GCR_DEN; - } - - regval &= ~(LTDC_GCR_DBW_MASK | LTDC_GCR_DGW_MASK | LTDC_GCR_DRW_MASK); - regval |= (LTDC_GCR_DRW(red) | LTDC_GCR_DGW(green) | LTDC_GCR_DBW(blue)); - - reginfo("set LTDC_GCR=%08" PRIx32 "\n", regval); - putreg32(regval, STM32_LTDC_GCR); - reginfo("configured LTDC_GCR=%08" PRIx32 "\n", - getreg32(STM32_LTDC_GCR)); -} - -/**************************************************************************** - * Name: stm32_ltdc_linepos - * - * Description: - * Configures line position register - * - ****************************************************************************/ - -static void stm32_ltdc_linepos(void) -{ - /* Configure LTDC_LIPCR */ - - reginfo("set LTDC_LIPCR=%08x\n", STM32_LTDC_LIPCR_LIPOS); - putreg32(STM32_LTDC_LIPCR_LIPOS, STM32_LTDC_LIPCR); - reginfo("configured LTDC_LIPCR=%08" PRIx32 "\n", - getreg32(STM32_LTDC_LIPCR)); -} - -/**************************************************************************** - * Name: stm32_ltdc_irqctrl - * - * Description: - * Control interrupts generated by the ltdc controller - * - * Input Parameters: - * setirqs - set interrupt mask - * clrirqs - clear interrupt mask - * - ****************************************************************************/ - -static void stm32_ltdc_irqctrl(uint32_t setirqs, uint32_t clrirqs) -{ - uint32_t regval; - - regval = getreg32(STM32_LTDC_IER); - regval &= ~clrirqs; - regval |= setirqs; - reginfo("set LTDC_IER=%08" PRIx32 "\n", regval); - putreg32(regval, STM32_LTDC_IER); - reginfo("configured LTDC_IER=%08" PRIx32 "\n", getreg32(STM32_LTDC_IER)); -} - -/**************************************************************************** - * Name: stm32_ltdcirq - * - * Description: - * LTDC interrupt handler - * - ****************************************************************************/ - -static int stm32_ltdcirq(int irq, void *context, void *arg) -{ - int ret; - struct stm32_interrupt_s *priv = &g_interrupt; - uint32_t regval = getreg32(STM32_LTDC_ISR); - - reginfo("irq = %d, regval = %08" PRIx32 "\n", irq, regval); - - if (regval & LTDC_ISR_RRIF) - { - /* Register reload interrupt */ - - /* Clear the interrupt status register */ - - reginfo("Register reloaded\n"); - putreg32(LTDC_ICR_CRRIF, STM32_LTDC_ICR); - priv->error = OK; - } - else if (regval & LTDC_IER_LIE) - { - /* Line interrupt */ - - /* Clear the interrupt status register */ - - reginfo("Line interrupt\n"); - putreg32(LTDC_ICR_CLIF, STM32_LTDC_ICR); - priv->error = OK; - } - else if (regval & LTDC_IER_TERRIE) - { - /* Transfer error interrupt */ - - /* Clear the interrupt status register */ - - reginfo("Error transfer\n"); - putreg32(LTDC_ICR_CTERRIF, STM32_LTDC_ICR); - priv->error = -ECANCELED; - } - else if (regval & LTDC_IER_FUIE) - { - /* Fifo underrun error interrupt */ - - /* Clear the interrupt status register */ - - reginfo("Error fifo underrun\n"); - putreg32(LTDC_ICR_CFUIF, STM32_LTDC_ICR); - priv->error = -ECANCELED; - } - else - { - DEBUGASSERT("Unknown interrupt"); - } - - /* Unlock the semaphore if locked */ - - ret = nxsem_post(priv->sem); - - if (ret < 0) - { - lcderr("ERROR: nxsem_post() failed\n"); - } - - return OK; -} - -/**************************************************************************** - * Name: stm32_ltdc_waitforirq - * - * Description: - * Helper waits until the ltdc irq occurs. In the current design That means - * that a register reload was been completed. - * Note! The caller must use this function within a critical section. - * - * Returned Value: - * OK - On success otherwise ERROR - * - ****************************************************************************/ - -static int stm32_ltdc_waitforirq(void) -{ - int ret = OK; - struct stm32_interrupt_s *priv = &g_interrupt; - - ret = nxsem_wait(priv->sem); - - if (ret < 0) - { - lcderr("ERROR: nxsem_wait() failed\n"); - } - - ret = priv->error; - - return ret; -} - -/**************************************************************************** - * Name: stm32_ltdc_reload - * - * Description: - * Reload the layer shadow register and make layer changes visible. - * Note! The caller must ensure that a previous register reloading has been - * completed. - * - * Input Parameters: - * value - Reload flag (e.g. upon vertical blank or immediately) - * waitvblank - Wait until register reload is finished - * - ****************************************************************************/ - -static int stm32_ltdc_reload(uint8_t value, bool waitvblank) -{ - int ret = OK; - - /* Reloads the shadow register. - * Note! This will not trigger an register reload interrupt if - * immediately reload is set. - */ - - reginfo("set LTDC_SRCR=%08x\n", value); - putreg32(value, STM32_LTDC_SRCR); - reginfo("configured LTDC_SRCR=%08" PRIx32 "\n", getreg32(STM32_LTDC_SRCR)); - - if (value == LTDC_SRCR_VBR && waitvblank) - { - /* Wait upon vertical blanking period */ - - ret = stm32_ltdc_waitforirq(); - } - else - { - /* Wait until register reload hase been done */ - - while (getreg32(STM32_LTDC_SRCR) & value); - } - - return ret; -} - -/**************************************************************************** - * Name: stm32_ltdc_irqconfig - * - * Description: - * Configure interrupts - * - ****************************************************************************/ - -static void stm32_ltdc_irqconfig(void) -{ - /* Attach LTDC interrupt vector */ - - irq_attach(g_interrupt.irq, stm32_ltdcirq, NULL); - - /* Enable the IRQ at the NVIC */ - - up_enable_irq(g_interrupt.irq); - - /* Enable interrupts expect line interrupt */ - - stm32_ltdc_irqctrl(LTDC_IER_RRIE | - LTDC_IER_TERRIE | - LTDC_IER_FUIE, - LTDC_IER_LIE); - - /* Configure line interrupt */ - - stm32_ltdc_linepos(); -} - -/**************************************************************************** - * Name: stm32_ltdc_globalconfig - * - * Description: - * Configure background color - * Configure dithering - * - ****************************************************************************/ - -static void stm32_ltdc_globalconfig(void) -{ - /* Configure dither */ - - stm32_ltdc_dither( -#ifdef CONFIG_STM32_LTDC_DITHER - true, -#else - false, -#endif - STM32_LTDC_DITHER_RED, - STM32_LTDC_DITHER_GREEN, - STM32_LTDC_DITHER_BLUE); - - /* Configure background color */ - - stm32_ltdc_bgcolor(STM32_LTDC_BACKCOLOR); -} - -/**************************************************************************** - * Name: stm32_ltdc_enable - * - * Description: - * Disable the LCD peripheral - * - * Input Parameters: - * enable - Enable or disable - * - ****************************************************************************/ - -static void stm32_ltdc_enable(bool enable) -{ - uint32_t regval; - - regval = getreg32(STM32_LTDC_GCR); - reginfo("get LTDC_GCR=%08" PRIx32 "\n", regval); - - if (enable == true) - { - regval |= LTDC_GCR_LTDCEN; - } - else - { - regval &= ~LTDC_GCR_LTDCEN; - } - - reginfo("set LTDC_GCR=%08" PRIx32 "\n", regval); - putreg32(regval, STM32_LTDC_GCR); - reginfo("configured LTDC_GCR=%08" PRIx32 "\n", getreg32(STM32_LTDC_GCR)); -} - -/**************************************************************************** - * Name: stm32_ltdc_lpixelformat - * - * Description: - * Set the layer pixel format. - * Note! This changes have no effect until the shadow register reload has - * been done. - * - * Input Parameters: - * Reference to the layer control structure - * - ****************************************************************************/ - -static void stm32_ltdc_lpixelformat(struct stm32_ltdc_s *layer) -{ - uint8_t overlay = layer->layerno; - DEBUGASSERT(layer->layerno < LTDC_NLAYERS); - - /* Configure PFCR register */ - - reginfo("set LTDC_L%dPFCR=%08" PRIx32 "\n", overlay + 1, - stm32_fmt_layer_t[overlay]); - putreg32(stm32_fmt_layer_t[overlay], stm32_pfcr_layer_t[overlay]); - - /* Reload shadow register */ - - stm32_ltdc_reload(LTDC_SRCR_IMR, false); -} - -/**************************************************************************** - * Name: stm32_ltdc_lframebuffer - * - * Description: - * Configure layer framebuffer of the entire window. - * Note! This changes have no effect until the shadow register reload has - * been done. - * - * Input Parameters: - * Reference to the layer control structure - * - ****************************************************************************/ - -static void stm32_ltdc_lframebuffer(struct stm32_ltdc_s *layer) -{ - uint32_t cfblr; - uint32_t rxpos; - uint32_t rypos; - uint32_t whpcr; - uint32_t wvpcr; - uint8_t layerno = layer->layerno; - - DEBUGASSERT(layer->layerno < LTDC_NLAYERS); - reginfo("xpos = %d, ypos = %d, xres = %d, yres = %d\n", 0, 0, - stm32_width_layer_t[layerno], stm32_height_layer_t[layerno]); - - /* Calculate register position */ - - rxpos = STM32_LTDC_LXWHPCR_WHSTPOS + 1; - rypos = STM32_LTDC_LXWVPCR_WVSTPOS + 1; - - /* Accumulate horizontal position */ - - whpcr = LTDC_LXWHPCR_WHSTPOS(rxpos); - whpcr |= LTDC_LXWHPCR_WHSPPOS(rxpos + stm32_width_layer_t[layerno] - 1); - - /* Accumulate vertical position */ - - wvpcr = LTDC_LXWVPCR_WVSTPOS(rypos); - wvpcr |= LTDC_LXWVPCR_WVSPPOS(rypos + stm32_height_layer_t[layerno] - 1); - - /* Configure LxWHPCR / LxWVPCR register */ - - reginfo("set LTDC_L%dWHPCR=%08" PRIx32 "\n", layerno + 1, whpcr); - putreg32(whpcr, stm32_whpcr_layer_t[layerno]); - reginfo("set LTDC_L%dWVPCR=%08" PRIx32 "\n", layerno + 1, wvpcr); - putreg32(wvpcr, stm32_wvpcr_layer_t[layerno]); - - /* Configure LxCFBAR register */ - - reginfo("set LTDC_L%dCFBAR=%08" PRIx32 "\n", layerno + 1, - stm32_fbmem_layer_t[layerno]); - putreg32(stm32_fbmem_layer_t[layerno], stm32_cfbar_layer_t[layerno]); - - /* Configure LxCFBLR register */ - - /* Calculate line length */ - - cfblr = LTDC_LXCFBLR_CFBP(stm32_stride_layer_t[layerno]) | - LTDC_LXCFBLR_CFBLL(stm32_width_layer_t[layerno] * - STM32_LTDC_LX_BYPP(stm32_bpp_layer_t[layerno]) + 3); - - reginfo("set LTDC_L%dCFBLR=%08" PRIx32 "\n", layerno + 1, cfblr); - putreg32(cfblr, stm32_cfblr_layer_t[layerno]); - - /* Configure LxCFBLNR register */ - - reginfo("set LTDC_L%dCFBLNR=%08" PRIx32 "\n", layerno + 1, - stm32_height_layer_t[layerno]); - putreg32(stm32_height_layer_t[layerno], stm32_cfblnr_layer_t[layerno]); - - /* Reload shadow register */ - - stm32_ltdc_reload(LTDC_SRCR_IMR, false); -} - -/**************************************************************************** - * Name: stm32_ltdc_lenable - * - * Description: - * Enable or disable layer. - * Note! This changes have no effect until the shadow register reload has - * been done. - * - * Input Parameters: - * layer - Reference to the layer control structure - * enable - Enable or disable layer - * - ****************************************************************************/ - -static void stm32_ltdc_lenable(struct stm32_ltdc_s *layer, bool enable) -{ - uint32_t regval; - DEBUGASSERT(layer->layerno < LTDC_NLAYERS); - - regval = getreg32(stm32_cr_layer_t[layer->layerno]); - - if (enable == true) - { - regval |= LTDC_LXCR_LEN; - } - else - { - regval &= ~LTDC_LXCR_LEN; - } - - /* Enable/Disable layer */ - - reginfo("set LTDC_L%dCR=%08" PRIx32 "\n", layer->layerno + 1, regval); - putreg32(regval, stm32_cr_layer_t[layer->layerno]); - - /* Reload shadow register */ - - stm32_ltdc_reload(LTDC_SRCR_IMR, false); -} - -/**************************************************************************** - * Name: stm32_ltdc_ltransp - * - * Description: - * Change layer transparency. - * Note! This changes have no effect until the shadow register reload has - * been done. - * - * Input Parameters: - * layer - Reference to the layer control structure - * transp - Transparency - * mode - Transparency mode - * - ****************************************************************************/ - -static void stm32_ltdc_ltransp(struct stm32_ltdc_s *layer, - uint8_t transp, - uint32_t mode) -{ - uint32_t bf1; - uint32_t bf2; - - DEBUGASSERT(layer->layerno < LTDC_NLAYERS); - -#ifdef CONFIG_FB_OVERLAY - if (mode == FB_CONST_ALPHA) - { - bf1 = LTDC_BF1_CONST_ALPHA; - bf2 = LTDC_BF2_CONST_ALPHA; - } - else - { - bf1 = LTDC_BF1_PIXEL_ALPHA; - bf2 = LTDC_BF2_PIXEL_ALPHA; - } -#else - bf1 = LTDC_BF1_CONST_ALPHA; - bf2 = LTDC_BF2_CONST_ALPHA; -#endif - - reginfo("set LTDC_L%dBFCR=%08" PRIx32 "\n", layer->layerno + 1, - (LTDC_LXBFCR_BF1(bf1) | LTDC_LXBFCR_BF2(bf2))); - - /* Set blendmode */ - - putreg32((LTDC_LXBFCR_BF1(bf1) | LTDC_LXBFCR_BF2(bf2)), - stm32_bfcr_layer_t[layer->layerno]); - - /* Set alpha */ - - reginfo("set LTDC_L%dCACR=%02x\n", layer->layerno + 1, transp); - putreg32(transp, stm32_cacr_layer_t[layer->layerno]); - - /* Reload shadow register */ - - stm32_ltdc_reload(LTDC_SRCR_IMR, false); -} - -/**************************************************************************** - * Name: stm32_ltdc_lchromakey - * - * Description: - * Change layer chromakey. - * Note! This changes have no effect until the shadow register reload has - * been done. - * - * Input Parameters: - * layer - Reference to the layer control structure - * chroma - chromakey - * - ****************************************************************************/ - -static void stm32_ltdc_lchromakey(struct stm32_ltdc_s *layer, - uint32_t chroma) -{ - uint32_t rgb; - DEBUGASSERT(layer->layerno < LTDC_NLAYERS); - - reginfo("%08" PRIx32 "\n", getreg32(stm32_cr_layer_t[layer->layerno])); - - /* Set chromakey */ - -#ifdef CONFIG_STM32_FB_CMAP - uint8_t r = g_vtable.cmap.red[chroma]; - uint8_t g = g_vtable.cmap.green[chroma]; - uint8_t b = g_vtable.cmap.blue[chroma]; - rgb = ((r << 16) | (g << 8) | b); -#else - rgb = ARGB8888(chroma); -#endif - - reginfo("set LTDC_L%dCKCR=%08" PRIx32 "\n", layer->layerno + 1, rgb); - putreg32(rgb, stm32_ckcr_layer_t[layer->layerno]); - - /* Reload shadow register */ - - stm32_ltdc_reload(LTDC_SRCR_IMR, false); -} - -/**************************************************************************** - * Name: stm32_ltdc_lchromakeyenable - * - * Description: - * Enable or disable layer chromakey support. - * Note! This changes have no effect until the shadow register reload has - * been done. - * - * Input Parameters: - * layer - Reference to the layer control structure - * enable - Enable or disable chromakey - * - ****************************************************************************/ - -static void stm32_ltdc_lchromakeyenable(struct stm32_ltdc_s *layer, - bool enable) -{ - uint32_t regval; - DEBUGASSERT(layer->layerno < LTDC_NLAYERS); - - regval = getreg32(stm32_cr_layer_t[layer->layerno]); - - /* Enable/Disable colorkey */ - - if (enable == true) - { - regval |= LTDC_LXCR_COLKEN; - } - else - { - regval &= ~LTDC_LXCR_COLKEN; - } - - reginfo("set LTDC_L%dCR=%08" PRIx32 "\n", layer->layerno + 1, regval); - putreg32(regval, stm32_cr_layer_t[layer->layerno]); - - /* Reload shadow register */ - - stm32_ltdc_reload(LTDC_SRCR_IMR, false); -} - -/**************************************************************************** - * Name: stm32_ltdc_lclutenable - * - * Description: - * Disable or enable the layer clut support - * - * Input Parameters: - * layer - Reference to the layer control structure - * enable - Enable or disable - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_FB_CMAP -static void stm32_ltdc_lclutenable(struct stm32_ltdc_s *layer, - bool enable) -{ - uint32_t regval; - - regval = getreg32(stm32_cr_layer_t[layer->oinfo.overlay]); - reginfo("get LTDC_L%dCR=%08" PRIx32 "\n", - layer->oinfo.overlay + 1, regval); - - /* Disable the clut support during update the color table */ - - if (enable == true) - { - regval |= LTDC_LXCR_CLUTEN; - } - else - { - regval &= ~LTDC_LXCR_CLUTEN; - } - - reginfo("set LTDC_L%dCR=%08" PRIx32 "\n", layer->oinfo.overlay, regval); - putreg32(regval, stm32_cr_layer_t[layer->oinfo.overlay]); - - /* Reload shadow register */ - - stm32_ltdc_reload(LTDC_SRCR_IMR, false); -} - -/**************************************************************************** - * Name: stm32_ltdc_lputclut - * - * Description: - * Update the clut layer register during blank period. - * Note! The clut register is no shadow register. - * - * Input Parameters: - * layer - Reference to the layer control structure - * cmap - Color map - * - ****************************************************************************/ - -static void stm32_ltdc_lputclut(struct stm32_ltdc_s *layer, - const struct fb_cmap_s *cmap) -{ - int n; - irqstate_t flags; - - /* Disable clut during register update */ - - stm32_ltdc_lclutenable(layer, false); - - /* Update the clut registers. Ensure operation is atomic or in interrupt - * protected context. - */ - - flags = enter_critical_section(); - - for (n = cmap->first; n < cmap->len && n < STM32_LTDC_NCLUT; n++) - { - uint32_t regval; - - regval = (uint32_t)LTDC_CLUT_ADD(n) | - (uint32_t)LTDC_CLUT_RED(cmap->red[n]) | - (uint32_t)LTDC_CLUT_GREEN(cmap->green[n]) | - (uint32_t)LTDC_CLUT_BLUE(cmap->blue[n]); - - reginfo("set LTDC_L%dCLUTWR = %08" PRIx32 ", first = %d, len = %d\n", - layer->oinfo.overlay + 1, regval, cmap->first, cmap->len); - putreg32(regval, stm32_clutwr_layer_t[layer->oinfo.overlay]); - } - - leave_critical_section(flags); - - /* Enable clut after register update */ - - stm32_ltdc_lclutenable(layer, true); - - /* Reload shadow control register */ - - stm32_ltdc_reload(LTDC_SRCR_IMR, false); -} - -/**************************************************************************** - * Name: stm32_ltdc_lgetclut - * - * Description: - * Copy the layers color lookup table. - * - * Input Parameters: - * layer - Reference to the layer control structure - * cmap - Color map - * - ****************************************************************************/ - -static void stm32_ltdc_lgetclut(struct stm32_ltdc_s *layer, - struct fb_cmap_s *cmap) -{ - int n; - struct fb_cmap_s *priv_cmap = &g_vtable.cmap; - - /* Copy from internal cmap */ - - for (n = cmap->first; n < cmap->len && n < STM32_LTDC_NCLUT; n++) - { -# ifdef CONFIG_STM32_FB_TRANSPARENCY - cmap->transp[n] = priv_cmap->transp[n]; -# endif - cmap->red[n] = priv_cmap->red[n]; - cmap->green[n] = priv_cmap->green[n]; - cmap->blue[n] = priv_cmap->blue[n]; - - reginfo("color = %d, transp=%02x, red=%02x, green=%02x, blue=%02x\n", - n, -# ifdef CONFIG_STM32_FB_TRANSPARENCY - cmap->transp[n], -# endif - cmap->red[n], - cmap->green[n], - cmap->blue[n]); - } -} -#endif /* CONFIG_STM32_FB_CMAP */ - -/**************************************************************************** - * Name: stm32_ltdc_lclear - * - * Description: - * Clear the whole layer - * - * Input Parameters: - * overlayno - Number overlay - * - ****************************************************************************/ - -static void stm32_ltdc_lclear(uint8_t overlayno) -{ - memset((uint8_t *)stm32_fbmem_layer_t[overlayno], 0, - stm32_fblen_layer_t[overlayno]); -} - -/**************************************************************************** - * Name: stm32_ltdc_lvalidate - * - * Description: - * Validates if the given area is within the overlay framebuffer memory - * region - * - * Input Parameters: - * layer - Reference to the layer control structure - * area - Reference to the overlay area - * - ****************************************************************************/ - -#if defined(CONFIG_STM32_DMA2D) && defined(CONFIG_FB_OVERLAY_BLIT) -static bool stm32_ltdc_lvalidate(const struct stm32_ltdc_s *layer, - const struct fb_area_s *area) -{ - uint32_t offset; - - offset = (area->y + area->h - 1) * layer->oinfo.stride + - (area->x + area->w) * layer->oinfo.bpp / 8; - - return (offset <= layer->oinfo.fblen && area->w > 0 && area->h > 0); -} -#endif /* defined(CONFIG_STM32_DMA2D) && defined(CONFIG_FB_OVERLAY_BLIT) */ - -/**************************************************************************** - * Name: stm32_ltdc_linit - * - * Description: - * Initialize layer to their default states. - * - * Initialize: - * - layer framebuffer - * - layer pixelformat - * - layer defaultcolor - * - layer chromakey - * - layer transparency - * - layer clut - * - * Input Parameters: - * layer - Reference to the layer control structure - * - ****************************************************************************/ - -static void stm32_ltdc_linit(uint8_t overlay) -{ - DEBUGASSERT(overlay < LTDC_NLAYERS); - - struct stm32_ltdcdev_s *dev = &g_vtable; - struct stm32_ltdc_s *layer = &dev->layer[overlay]; - - /* Disable layer */ - - stm32_ltdc_lenable(layer, false); - - /* Clear the layer framebuffer */ - - stm32_ltdc_lclear(overlay); - - /* Set layers framebuffer */ - - stm32_ltdc_lframebuffer(layer); - - /* Set layers pixel input format */ - - stm32_ltdc_lpixelformat(layer); - - /* Configure layer default color */ - - stm32_ltdc_ldefaultcolor(layer, stm32_defaultcolor_layer_t[overlay]); - - /* Layers default transparency */ - - stm32_ltdc_ltransp(layer, 0xff, 0); - - /* Layers chromakey */ - - stm32_ltdc_lchromakey(layer, stm32_chromakey_layer_t[overlay]); - - /* Enable chromakey */ - - stm32_ltdc_lchromakeyenable(layer, stm32_chromakeyen_layer_t[overlay]); - -#ifdef CONFIG_STM32_FB_CMAP - /* Disable clut by default */ - - if (dev->vinfo.fmt == FB_FMT_RGB8) - { - /* Initialize LTDC clut register */ - - stm32_ltdc_lputclut(layer, &g_vtable.cmap); - - /* Configure the clut register */ - - stm32_ltdc_lclutenable(layer, true); - } -#endif - - /* Finally enable the layer */ - - stm32_ltdc_lenable(layer, true); -} - -/**************************************************************************** - * Name: stm32_ltdc_dma2dlinit - * - * Description: - * Initialize dma2d layer to their default states. - * - * Initialize: - * - layer framebuffer - * - layer pixelformat - * - layer size - * - layer color - * - layer chromakey - * - layer transparency - * - layer clut - * - * Input Parameters: - * layer - Reference to the layer control structure - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_DMA2D -static void stm32_ltdc_dma2dlinit(void) -{ - int n; - struct stm32_ltdcdev_s *dev = &g_vtable; - - for (n = 0; n < DMA2D_NLAYERS; n++) - { - uint32_t overlay = n + LTDC_NLAYERS; - struct stm32_ltdc_s *layer = &dev->layer[overlay]; - uint8_t * fbmem = (uint8_t *)STM32_DMA2D_BUFFER_START; - - layer->layerno = overlay; - layer->oinfo.fbmem = fbmem + STM32_DMA2D_LAYER_SIZE * n; - layer->oinfo.fblen = STM32_DMA2D_FBSIZE; - layer->oinfo.stride = STM32_DMA2D_STRIDE; - layer->oinfo.overlay = overlay; - layer->oinfo.bpp = STM32_DMA2D_BPP; - layer->oinfo.blank = 0; - layer->oinfo.chromakey = 0; - layer->oinfo.color = 0; - layer->oinfo.transp.transp = 0xff; - layer->oinfo.transp.transp_mode = 0; - layer->oinfo.sarea.x = 0; - layer->oinfo.sarea.y = 0; - layer->oinfo.sarea.w = STM32_DMA2D_WIDTH; - layer->oinfo.sarea.h = STM32_DMA2D_HEIGHT; - layer->oinfo.accl = DMA2D_ACCL; - layer->lock = &g_lock; - layer->dma2dinfo.fmt = STM32_DMA2D_COLOR_FMT; - layer->dma2dinfo.transp_mode = STM32_DMA2D_PFCCR_AM_NONE; - layer->dma2dinfo.xres = layer->oinfo.sarea.w; - layer->dma2dinfo.yres = layer->oinfo.sarea.h; - layer->dma2dinfo.oinfo = &layer->oinfo; - } -} -#endif /* CONFIG_STM32_DMA2D */ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_getvideoinfo - * - * Description: - * Entrypoint ioctl FBIOGET_VIDEOINFO - * Get the videoinfo for the framebuffer - * - * Input Parameters: - * vtable - The framebuffer driver object - * vinfo - the videoinfo object - * - * Returned Value: - * On success - OK - * On error - -EINVAL - * - ****************************************************************************/ - -static int stm32_getvideoinfo(struct fb_vtable_s *vtable, - struct fb_videoinfo_s *vinfo) -{ - struct stm32_ltdcdev_s *priv = (struct stm32_ltdcdev_s *)vtable; - - lcdinfo("vtable=%p vinfo=%p\n", vtable, vinfo); - DEBUGASSERT(vtable != NULL && priv == &g_vtable && vinfo != NULL); - - memcpy(vinfo, &priv->vinfo, sizeof(struct fb_videoinfo_s)); - return OK; -} - -/**************************************************************************** - * Name: stm32_getplaneinfo - * - * Description: - * Entrypoint ioctl FBIOGET_PLANEINFO - * Get the planeinfo for the framebuffer - * - * Input Parameters: - * vtable - The framebuffer driver object - * pinfo - the planeinfo object - * - * Returned Value: - * On success - OK - * On error - -EINVAL - * - ****************************************************************************/ - -static int stm32_getplaneinfo(struct fb_vtable_s *vtable, int planeno, - struct fb_planeinfo_s *pinfo) -{ - struct stm32_ltdcdev_s *priv = (struct stm32_ltdcdev_s *)vtable; - - DEBUGASSERT(vtable != NULL && priv == &g_vtable); - lcdinfo("vtable=%p planeno=%d pinfo=%p\n", vtable, planeno, pinfo); - - if (planeno == 0) - { - memcpy(pinfo, &priv->pinfo, sizeof(struct fb_planeinfo_s)); - return OK; - } - - lcderr("ERROR: Returning EINVAL\n"); - return -EINVAL; -} - -/**************************************************************************** - * Name: stm32_getcmap - * - * Description: - * Entrypoint ioctl FBIOGET_CMAP - * Get a range of CLUT values for the LCD - * - * Input Parameters: - * vtable - The framebuffer driver object - * cmap - the color table - * - * Returned Value: - * On success - OK - * On error - -EINVAL - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_FB_CMAP -static int stm32_getcmap(struct fb_vtable_s *vtable, - struct fb_cmap_s *cmap) -{ - int ret; - struct stm32_ltdcdev_s *priv = (struct stm32_ltdcdev_s *)vtable; - - DEBUGASSERT(vtable != NULL && priv == &g_vtable && cmap != NULL); - lcdinfo("vtable=%p cmap=%p\n", vtable, cmap); - - if (priv->vinfo.fmt != FB_FMT_RGB8) - { - lcderr("ERROR: CLUT is not supported for the pixel format: %d\n", - priv->vinfo.fmt); - ret = -EINVAL; - } - else if (cmap->first >= STM32_LTDC_NCLUT) - { - lcderr("ERROR: only %d color table entries supported\n", - STM32_LTDC_NCLUT); - ret = -EINVAL; - } - else - { - /* Currently, there is no api to set color map for each overlay - * separately. LTDC layers can have different color maps. Get the cmap - * from the main overlay. - */ - - struct stm32_ltdc_s *layer; -# ifdef CONFIG_STM32_LTDC_L2 - layer = &priv->layer[LTDC_LAYER_L2]; -# else - layer = &priv->layer[LTDC_LAYER_L1]; -# endif - nxmutex_lock(layer->lock); - stm32_ltdc_lgetclut(layer, cmap); - nxmutex_unlock(layer->lock); - - ret = OK; - } - - return ret; -} - -/**************************************************************************** - * Name: stm32_putcmap - * - * Description: - * Entrypoint ioctl FBIOPUT_CMAP - * Set a range of the CLUT values for the LCD - * - * Input Parameters: - * vtable - The framebuffer driver object - * cmap - the color table - * - * Returned Value: - * On success - OK - * On error - -EINVAL - * - ****************************************************************************/ - -static int stm32_putcmap(struct fb_vtable_s *vtable, - const struct fb_cmap_s *cmap) -{ - int ret; - struct stm32_ltdcdev_s *priv = (struct stm32_ltdcdev_s *)vtable; - - DEBUGASSERT(vtable != NULL && priv == &g_vtable && cmap != NULL); - lcdinfo("vtable=%p cmap=%p\n", vtable, cmap); - - if (priv->vinfo.fmt != FB_FMT_RGB8) - { - lcderr("ERROR: CLUT is not supported for the pixel format: %d\n", - priv->vinfo.fmt); - ret = -EINVAL; - } - else if (cmap->first >= STM32_LTDC_NCLUT) - { - lcderr("ERROR: only %d color table entries supported\n", - STM32_LTDC_NCLUT); - ret = -EINVAL; - } - else - { - /* Currently, there is no api to set color map for each overlay - * separately. LTDC layers can have different color maps, but is shared - * for now. - */ - - int n; - struct fb_cmap_s *priv_cmap = &g_vtable.cmap; - - /* First copy to internal cmap */ - - for (n = cmap->first; n < cmap->len && n < STM32_LTDC_NCLUT; n++) - { - priv_cmap->red[n] = cmap->red[n]; - priv_cmap->green[n] = cmap->green[n]; - priv_cmap->blue[n] = cmap->blue[n]; -# ifdef CONFIG_STM32_FB_TRANSPARENCY - /* Not supported by LTDC */ - - priv_cmap->transp[n] = cmap->transp[n]; -# endif - } - - priv_cmap->first = cmap->first; - priv_cmap->len = cmap->len; - - /* Update the layer clut register */ - - nxmutex_lock(&g_lock); - - for (n = 0; n < LTDC_NLAYERS; n++) - { - struct stm32_ltdc_s *layer = &priv->layer[n]; - stm32_ltdc_lputclut(layer, priv_cmap); - } - -# ifdef CONFIG_STM32_DMA2D - /* Update dma2d cmap */ - - priv->dma2d->setclut(cmap); -# endif - nxmutex_unlock(&g_lock); - - ret = OK; - } - - return ret; -} -#endif /* CONFIG_STM32_FB_CMAP */ - -/**************************************************************************** - * Name: stm32_ioctl_waitforvsync - * Description: - * Entrypoint ioctl FBIO_WAITFORSYNC - ****************************************************************************/ - -#ifdef CONFIG_FB_SYNC -static int stm32_waitforvsync(struct fb_vtable_s *vtable) -{ - int ret; - - DEBUGASSERT(vtable != NULL && vtable == &g_vtable.vtable); - - /* Wait upon vertical synchronization. */ - - ret = stm32_ltdc_reload(LTDC_SRCR_VBR, true); - - return ret; -} -#endif /* CONFIG_FB_SYNC */ - -/**************************************************************************** - * Name: stm32_getoverlayinfo - * Description: - * Entrypoint ioctl FBIOGET_OVERLAYINFO - ****************************************************************************/ - -#ifdef CONFIG_FB_OVERLAY -static int stm32_getoverlayinfo(struct fb_vtable_s *vtable, - int overlayno, - struct fb_overlayinfo_s *oinfo) -{ - struct stm32_ltdcdev_s *priv = (struct stm32_ltdcdev_s *)vtable; - - lcdinfo("vtable=%p overlay=%d oinfo=%p\n", vtable, overlayno, oinfo); - DEBUGASSERT(vtable != NULL && priv == &g_vtable); - - if (overlayno < LTDC_NOVERLAYS) - { - struct stm32_ltdc_s *layer = &priv->layer[overlayno]; - memcpy(oinfo, &layer->oinfo, sizeof(struct fb_overlayinfo_s)); - return OK; - } - - lcderr("ERROR: Returning EINVAL\n"); - return -EINVAL; -} - -/**************************************************************************** - * Name: stm32_settransp - * Description: - * Entrypoint ioctl FBIOSET_TRANSP - ****************************************************************************/ - -static int stm32_settransp(struct fb_vtable_s *vtable, - const struct fb_overlayinfo_s *oinfo) -{ - struct stm32_ltdcdev_s *priv = (struct stm32_ltdcdev_s *)vtable; - - DEBUGASSERT(vtable != NULL && priv == &g_vtable); - lcdinfo("vtable=%p, overlay=%d, transp=%02x, transp_mode=%02x\n", vtable, - oinfo->overlay, oinfo->transp.transp, oinfo->transp.transp_mode); - - if (oinfo->transp.transp_mode > 1) - { - lcderr("ERROR: Returning ENOSYS, transparency mode not supported\n"); - return -ENOSYS; - } - - if (oinfo->overlay < LTDC_NOVERLAYS) - { - struct stm32_ltdc_s *layer = &priv->layer[oinfo->overlay]; - - nxmutex_lock(layer->lock); - layer->oinfo.transp.transp = oinfo->transp.transp; - layer->oinfo.transp.transp_mode = oinfo->transp.transp_mode; - -# ifdef CONFIG_STM32_DMA2D - if (layer->oinfo.transp.transp_mode == 0) - { - layer->dma2dinfo.transp_mode = STM32_DMA2D_PFCCR_AM_CONST; - } - else if (layer->oinfo.transp.transp_mode == 1) - { - layer->dma2dinfo.transp_mode = STM32_DMA2D_PFCCR_AM_PIXEL; - } - - if (oinfo->overlay < LTDC_NLAYERS) -# endif - { - /* Set LTDC blendmode and alpha value */ - - stm32_ltdc_ltransp(layer, layer->oinfo.transp.transp, - layer->oinfo.transp.transp_mode); - } - - nxmutex_unlock(layer->lock); - return OK; - } - - lcderr("ERROR: Returning EINVAL\n"); - return -EINVAL; -} - -/**************************************************************************** - * Name: stm32_setchromakey - * Description: - * Entrypoint ioctl FBIOSET_CHROMAKEY - ****************************************************************************/ - -static int stm32_setchromakey(struct fb_vtable_s *vtable, - const struct fb_overlayinfo_s *oinfo) -{ - struct stm32_ltdcdev_s *priv = (struct stm32_ltdcdev_s *)vtable; - - DEBUGASSERT(vtable != NULL && priv == &g_vtable && oinfo != NULL); - lcdinfo("vtable=%p, overlay=%d, chromakey=%08" PRIx32 "\n", vtable, - oinfo->overlay, oinfo->chromakey); - - if (oinfo->overlay < LTDC_NLAYERS) - { - int ret; - struct stm32_ltdc_s *layer = &priv->layer[oinfo->overlay]; - -# ifndef CONFIG_STM32_LTDC_L1_CHROMAKEY - if (oinfo->overlay == LTDC_LAYER_L1) - { - return -ENOSYS; - } -# endif - -# ifndef CONFIG_STM32_LTDC_L2_CHROMAKEY - if (oinfo->overlay == LTDC_LAYER_L2) - { - return -ENOSYS; - } -# endif - - nxmutex_lock(layer->lock); -# ifdef CONFIG_STM32_FB_CMAP - if (oinfo->chromakey >= g_vtable.cmap.len) - { - lcderr("ERROR: Clut index %" PRId32 " is out of range\n", - oinfo->chromakey); - ret = -EINVAL; - } - else -# endif - { - layer->oinfo.chromakey = oinfo->chromakey; - - /* Set chromakey */ - - stm32_ltdc_lchromakey(layer, layer->oinfo.chromakey); - ret = OK; - } - - nxmutex_unlock(layer->lock); - return ret; - } -# ifdef CONFIG_STM32_DMA2D - else if (oinfo->overlay < LTDC_NOVERLAYS) - { - /* Chromakey not supported by DMA2D */ - - return -ENOSYS; - } -# endif - - lcderr("ERROR: Returning EINVAL\n"); - return -EINVAL; -} - -/**************************************************************************** - * Name: stm32_setcolor - * Description: - * Entrypoint ioctl FBIOSET_COLOR - ****************************************************************************/ - -static int stm32_setcolor(struct fb_vtable_s *vtable, - const struct fb_overlayinfo_s *oinfo) -{ - DEBUGASSERT(vtable != NULL && vtable == &g_vtable.vtable && oinfo != NULL); - lcdinfo("vtable=%p, overlay=%d, color=%08" PRIx32 "\n", - vtable, oinfo->overlay, oinfo->color); - - if (oinfo->overlay < LTDC_NOVERLAYS) - { -# ifdef CONFIG_STM32_DMA2D - - /* Set color within the active overlay is not supported by LTDC. So use - * DMA2D controller instead when configured. - */ - - int ret; - struct stm32_ltdcdev_s *priv = (struct stm32_ltdcdev_s *) - vtable; - struct stm32_ltdc_s *layer = &priv->layer[oinfo->overlay]; - struct fb_overlayinfo_s *poverlay = layer->dma2dinfo.oinfo; - - DEBUGASSERT(&layer->oinfo == poverlay); - - nxmutex_lock(layer->lock); - poverlay->color = oinfo->color; - ret = priv->dma2d->fillcolor(&layer->dma2dinfo, &poverlay->sarea, - poverlay->color); - nxmutex_unlock(layer->lock); - - return ret; -# else - /* Coloring not supported by LTDC */ - - return -ENOSYS; -# endif - } - - lcderr("ERROR: Returning EINVAL\n"); - return -EINVAL; -} - -/**************************************************************************** - * Name: stm32_setblank - * Description: - * Entrypoint ioctl FBIOSET_BLANK - ****************************************************************************/ - -static int stm32_setblank(struct fb_vtable_s *vtable, - const struct fb_overlayinfo_s *oinfo) -{ - struct stm32_ltdcdev_s *priv = (struct stm32_ltdcdev_s *)vtable; - - DEBUGASSERT(vtable != NULL && priv == &g_vtable && oinfo != NULL); - lcdinfo("vtable=%p, overlay=%d, blank=%02x\n", - vtable, oinfo->overlay, oinfo->blank); - - if (oinfo->overlay < LTDC_NLAYERS) - { - struct stm32_ltdc_s *layer = &priv->layer[oinfo->overlay]; - - nxmutex_lock(layer->lock); - layer->oinfo.blank = oinfo->blank; - - /* Enable or disable layer */ - - stm32_ltdc_lenable(layer, (layer->oinfo.blank == 0)); - nxmutex_unlock(layer->lock); - - return OK; - } -# ifdef CONFIG_STM32_DMA2D - else if (oinfo->overlay < LTDC_NOVERLAYS) - { - /* DMA2D overlays are non visible */ - - return OK; - } -# endif - - lcderr("ERROR: Returning EINVAL\n"); - return -EINVAL; -} - -/**************************************************************************** - * Name: stm32_setarea - * Description: - * Entrypoint ioctl FBIOSET_AREA - ****************************************************************************/ - -static int stm32_setarea(struct fb_vtable_s *vtable, - const struct fb_overlayinfo_s *oinfo) -{ - DEBUGASSERT(vtable != NULL && vtable == &g_vtable.vtable && oinfo != NULL); - lcdinfo("vtable=%p, overlay=%d, x=%d, y=%d, w=%d, h=%d\n", vtable, - oinfo->overlay, oinfo->sarea.x, oinfo->sarea.y, oinfo->sarea.w, - oinfo->sarea.h); - - if (oinfo->overlay < LTDC_NLAYERS) - { - /* LTDC area is defined by the overlay size (display resolution) only */ - - return -ENOSYS; - } - -# ifdef CONFIG_STM32_DMA2D - if (oinfo->overlay < LTDC_NOVERLAYS) - { - struct stm32_ltdcdev_s *priv = (struct stm32_ltdcdev_s *) - vtable; - struct stm32_ltdc_s *layer = &priv->layer[oinfo->overlay]; - - nxmutex_lock(layer->lock); - memcpy(&layer->oinfo.sarea, &oinfo->sarea, sizeof(struct fb_area_s)); - nxmutex_unlock(layer->lock); - - return OK; - } -# endif - - lcderr("ERROR: Returning EINVAL\n"); - return -EINVAL; -} - -/**************************************************************************** - * Name: stm32_blit - * Description: - * Entrypoint ioctl FBIOSET_BLIT - ****************************************************************************/ - -# ifdef CONFIG_FB_OVERLAY_BLIT -static int stm32_blit(struct fb_vtable_s *vtable, - const struct fb_overlayblit_s *blit) -{ - DEBUGASSERT(vtable != NULL && vtable == &g_vtable.vtable && blit != NULL); - lcdinfo("vtable = %p, blit = %p\n", vtable, blit); - - if (blit->dest.overlay < LTDC_NOVERLAYS && - blit->src.overlay < LTDC_NOVERLAYS) - { -# ifdef CONFIG_STM32_DMA2D - int ret; - struct fb_area_s sarea; - const struct fb_area_s *darea = &blit->dest.area; - struct stm32_ltdcdev_s *priv = (struct stm32_ltdcdev_s *) - vtable; - struct stm32_ltdc_s *dlayer = &priv->layer[blit->dest.overlay]; - struct stm32_ltdc_s *slayer = &priv->layer[blit->src.overlay]; - - DEBUGASSERT(&dlayer->oinfo == dlayer->dma2dinfo.oinfo && - &slayer->oinfo == slayer->dma2dinfo.oinfo); - - /* DMA2D doesn't support image scale, so set to the smallest area */ - - memcpy(&sarea, &blit->src.area, sizeof(struct fb_area_s)); - - /* Check if area is within the entire overlay */ - - if (!stm32_ltdc_lvalidate(dlayer, darea) || - !stm32_ltdc_lvalidate(slayer, &sarea)) - { - return -EINVAL; - } - - sarea.w = MIN(darea->w, sarea.w); - sarea.h = MIN(darea->h, sarea.h); - - nxmutex_lock(dlayer->lock); - ret = priv->dma2d->blit(&dlayer->dma2dinfo, darea->x, darea->y, - &slayer->dma2dinfo, &sarea); - nxmutex_unlock(dlayer->lock); - - return ret; -# else - /* LTDC doesn't support blit transfer */ - - return -ENOSYS; -# endif - } - - lcderr("ERROR: Returning EINVAL\n"); - return -EINVAL; -} - -/**************************************************************************** - * Name: stm32_blend - * Description: - * Entrypoint ioctl FBIOSET_BLEND - ****************************************************************************/ - -static int stm32_blend(struct fb_vtable_s *vtable, - const struct fb_overlayblend_s *blend) -{ - DEBUGASSERT(vtable != NULL && vtable == &g_vtable.vtable && blend != NULL); - lcdinfo("vtable = %p, blend = %p\n", vtable, blend); - - if (blend->dest.overlay < LTDC_NOVERLAYS && - blend->foreground.overlay < LTDC_NOVERLAYS && - blend->background.overlay < LTDC_NOVERLAYS) - { -# ifdef CONFIG_STM32_DMA2D - int ret; - struct fb_area_s barea; - const struct fb_area_s *darea = &blend->dest.area; - const struct fb_area_s *farea = &blend->foreground.area; - struct stm32_ltdcdev_s *priv = (struct stm32_ltdcdev_s *) - vtable; - struct stm32_ltdc_s *dlayer = &priv->layer[blend->dest.overlay]; - struct stm32_ltdc_s *flayer = - &priv->layer[blend->foreground.overlay]; - struct stm32_ltdc_s *blayer = - &priv->layer[blend->background.overlay]; - - DEBUGASSERT(&dlayer->oinfo == dlayer->dma2dinfo.oinfo && - &flayer->oinfo == flayer->dma2dinfo.oinfo && - &blayer->oinfo == blayer->dma2dinfo.oinfo); - - /* DMA2D doesn't support image scale, so set to the smallest area */ - - memcpy(&barea, &blend->background.area, sizeof(struct fb_area_s)); - - /* Check if area is within the entire overlay */ - - if (!stm32_ltdc_lvalidate(dlayer, darea) || - !stm32_ltdc_lvalidate(flayer, farea) || - !stm32_ltdc_lvalidate(blayer, &barea)) - { - lcderr("ERROR: Returning EINVAL\n"); - return -EINVAL; - } - - barea.w = MIN(darea->w, barea.w); - barea.h = MIN(darea->h, barea.h); - barea.w = MIN(farea->w, barea.w); - barea.h = MIN(farea->h, barea.h); - - nxmutex_lock(dlayer->lock); - ret = priv->dma2d->blend(&dlayer->dma2dinfo, darea->x, darea->y, - &flayer->dma2dinfo, farea->x, farea->y, - &blayer->dma2dinfo, &barea); - nxmutex_unlock(dlayer->lock); - - return ret; -# else - /* LTDC doesn't support blend transfer */ - - return -ENOSYS; -# endif - } - - lcderr("ERROR: Returning EINVAL\n"); - return -EINVAL; -} -# endif /* CONFIG_FB_OVERLAY_BLIT */ -#endif /* CONFIG_FB_OVERLAY */ - -/**************************************************************************** - * Name: stm32_ltdcreset - * - * Description: - * Reset LTDC via APB2RSTR - * - ****************************************************************************/ - -void stm32_ltdcreset(void) -{ - uint32_t regval = getreg32(STM32_RCC_APB2RSTR); - putreg32(regval | RCC_APB2RSTR_LTDCRST, STM32_RCC_APB2RSTR); - putreg32(regval & ~RCC_APB2RSTR_LTDCRST, STM32_RCC_APB2RSTR); -} - -/**************************************************************************** - * Name: stm32_ltdcinitialize - * - * Description: - * Initialize the ltdc controller - * - * Returned Value: - * OK - * - ****************************************************************************/ - -int stm32_ltdcinitialize(void) -{ - int ret = OK; - - lcdinfo("Initialize LTDC driver\n"); - - if (g_initialized == true) - { - return ret; - } - - /* Disable the LCD */ - - stm32_ltdc_enable(false); - - lcdinfo("Configuring the LCD controller\n"); - - /* Configure LCD periphery */ - - lcdinfo("Configure lcd periphery\n"); - stm32_ltdc_periphconfig(); - - /* Configure interrupts */ - - lcdinfo("Configure interrupts\n"); - stm32_ltdc_irqconfig(); - - /* Configure global ltdc register */ - - lcdinfo("Configure global register\n"); - stm32_ltdc_globalconfig(); - -#ifdef CONFIG_STM32_DMA2D - /* Initialize the dma2d controller */ - - ret = stm32_dma2dinitialize(); - - if (ret != OK) - { - return ret; - } - - /* Bind the dma2d interface */ - - g_vtable.dma2d = stm32_dma2ddev(); - DEBUGASSERT(g_vtable.dma2d != NULL); -#endif - -#ifdef CONFIG_STM32_FB_CMAP - /* Cleanup clut */ - - memset(&g_redclut, 0, STM32_LTDC_NCLUT); - memset(&g_blueclut, 0, STM32_LTDC_NCLUT); - memset(&g_greenclut, 0, STM32_LTDC_NCLUT); -# ifdef CONFIG_STM32_FB_TRANSPARENCY - memset(&g_transpclut, 0, STM32_LTDC_NCLUT); -# endif -#endif /* CONFIG_STM32_FB_CMAP */ - - /* Initialize ltdc layer */ - - lcdinfo("Initialize ltdc layer\n"); - stm32_ltdc_linit(LTDC_LAYER_L1); -#ifdef CONFIG_STM32_LTDC_L2 - stm32_ltdc_linit(LTDC_LAYER_L2); -#endif - -#ifdef CONFIG_STM32_DMA2D - stm32_ltdc_dma2dlinit(); -#endif - /* Enable the backlight */ - -#ifdef CONFIG_STM32_LCD_BACKLIGHT - stm32_backlight(true); -#endif - - /* Reload shadow register */ - - lcdinfo("Reload shadow register\n"); - stm32_ltdc_reload(LTDC_SRCR_IMR, false); - - /* Turn the LCD on */ - - lcdinfo("Enabling the display\n"); - stm32_ltdc_enable(true); - - /* Set initialized state */ - - g_initialized = true; - return ret; -} - -/**************************************************************************** - * Name: stm32_ltdcgetvplane - * - * Description: - * Return a a reference to the framebuffer object for the specified video - * plane. - * - * Input Parameters: - * None - * - * Returned Value: - * Reference to the framebuffer object (NULL on failure) - * - ****************************************************************************/ - -struct fb_vtable_s *stm32_ltdcgetvplane(int vplane) -{ - lcdinfo("vplane: %d\n", vplane); - - if (vplane == 0) - { - return &g_vtable.vtable; - } - - return NULL; -} - -/**************************************************************************** - * Name: stm32_ltdcuninitialize - * - * Description: - * Uninitialize the framebuffer driver. Bad things will happen if you - * call this without first calling fb_initialize()! - * - ****************************************************************************/ - -void stm32_ltdcuninitialize(void) -{ - /* Disable all ltdc interrupts */ - - stm32_ltdc_irqctrl(0, LTDC_IER_RRIE | LTDC_IER_TERRIE | - LTDC_IER_FUIE | LTDC_IER_LIE); - - up_disable_irq(g_interrupt.irq); - irq_detach(g_interrupt.irq); - - /* Disable the LCD controller */ - - stm32_ltdc_enable(false); - - /* Set initialized state */ - - g_initialized = false; -} - -/**************************************************************************** - * Name: stm32_lcd_backlight - * - * Description: - * Provide this interface to turn the backlight on and off. - * - * Input Parameters: - * blon - Enable or disable the lcd backlight - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_LCD_BACKLIGHT -void stm32_backlight(bool blon) -{ - /* Set default backlight level CONFIG_STM32_LTDC_DEFBACKLIGHT */ - - lcderr("ERROR: Not supported\n"); -} -#endif diff --git a/arch/arm/src/stm32/stm32_ltdc.h b/arch/arm/src/stm32/stm32_ltdc.h deleted file mode 100644 index 50e089869e09a..0000000000000 --- a/arch/arm/src/stm32/stm32_ltdc.h +++ /dev/null @@ -1,102 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_ltdc.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32_STM32_LTDC_H -#define __ARCH_ARM_SRC_STM32_STM32_LTDC_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include -#include - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_ltdcreset - * - * Description: - * Reset LTDC via APB2RSTR - * - ****************************************************************************/ - -void stm32_ltdcreset(void); - -/**************************************************************************** - * Name: stm32_ltdcinitialize - * - * Description: - * Initialize the ltdc controller - * - * Returned Value: - * OK - * - ****************************************************************************/ - -int stm32_ltdcinitialize(void); - -/**************************************************************************** - * Name: stm32_ltdcuninitialize - * - * Description: - * Uninitialize the ltdc controller - * - ****************************************************************************/ - -void stm32_ltdcuninitialize(void); - -/**************************************************************************** - * Name: stm32_ltdcgetvplane - * - * Description: - * Get video plane reference used by framebuffer interface - * - * Parameter: - * vplane - Video plane - * - * Returned Value: - * Video plane reference - * - ****************************************************************************/ - -struct fb_vtable_s *stm32_ltdcgetvplane(int vplane); - -/**************************************************************************** - * Name: stm32_lcd_backlight - * - * Description: - * If CONFIG_STM32_LCD_BACKLIGHT is defined, then the board-specific logic - * must provide this interface to turn the backlight on and off. - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_LCD_BACKLIGHT -void stm32_backlight(bool blon); -#endif -#endif /* __ARCH_ARM_SRC_STM32_STM32_LTDC_H */ diff --git a/arch/arm/src/stm32/stm32_mpuinit.c b/arch/arm/src/stm32/stm32_mpuinit.c deleted file mode 100644 index 6cc545c825ea4..0000000000000 --- a/arch/arm/src/stm32/stm32_mpuinit.c +++ /dev/null @@ -1,103 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_mpuinit.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include - -#include "mpu.h" -#include "stm32_mpuinit.h" - -#if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_ARM_MPU) - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_mpuinitialize - * - * Description: - * Configure the MPU to permit user-space access to only restricted SAM3U - * resources. - * - ****************************************************************************/ - -void stm32_mpuinitialize(void) -{ - uintptr_t datastart = MIN(USERSPACE->us_datastart, USERSPACE->us_bssstart); - uintptr_t dataend = MAX(USERSPACE->us_dataend, USERSPACE->us_bssend); - - DEBUGASSERT(USERSPACE->us_textend >= USERSPACE->us_textstart && - dataend >= datastart); - - /* Show MPU information */ - - mpu_showtype(); - - /* Reset MPU if enabled */ - - mpu_reset(); - - /* Configure user flash and SRAM space */ - - mpu_user_flash(USERSPACE->us_textstart, - USERSPACE->us_textend - USERSPACE->us_textstart); - - mpu_user_intsram(datastart, dataend - datastart); - - /* Then enable the MPU */ - - mpu_control(true, false, true); -} - -/**************************************************************************** - * Name: stm32_mpu_uheap - * - * Description: - * Map the user-heap region. - * - * This logic may need an extension to handle external SDRAM). - * - ****************************************************************************/ - -void stm32_mpu_uheap(uintptr_t start, size_t size) -{ - mpu_user_intsram(start, size); -} - -#endif /* CONFIG_BUILD_PROTECTED && CONFIG_ARM_MPU */ diff --git a/arch/arm/src/stm32/stm32_oneshot.c b/arch/arm/src/stm32/stm32_oneshot.c deleted file mode 100644 index b80df41e76265..0000000000000 --- a/arch/arm/src/stm32/stm32_oneshot.c +++ /dev/null @@ -1,458 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_oneshot.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -#include "stm32_oneshot.h" - -#ifdef CONFIG_STM32_ONESHOT - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -static int stm32_oneshot_handler(int irg_num, void * context, void *arg); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -static struct stm32_oneshot_s *g_oneshot[CONFIG_STM32_ONESHOT_MAXTIMERS]; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_oneshot_handler - * - * Description: - * Common timer interrupt callback. When any oneshot timer interrupt - * expires, this function will be called. It will forward the call to - * the next level up. - * - * Input Parameters: - * oneshot - The state associated with the expired timer - * - * Returned Value: - * Always returns OK - * - ****************************************************************************/ - -static int stm32_oneshot_handler(int irg_num, void * context, void *arg) -{ - struct stm32_oneshot_s * oneshot = (struct stm32_oneshot_s *) arg; - oneshot_handler_t oneshot_handler; - void *oneshot_arg; - - tmrinfo("Expired...\n"); - DEBUGASSERT(oneshot != NULL && oneshot->handler); - - /* The clock was stopped, but not disabled when the RC match occurred. - * Disable the TC now and disable any further interrupts. - */ - - STM32_TIM_SETISR(oneshot->tch, NULL, NULL, 0); - STM32_TIM_DISABLEINT(oneshot->tch, GTIM_DIER_UIE); - STM32_TIM_SETMODE(oneshot->tch, STM32_TIM_MODE_DISABLED); - STM32_TIM_ACKINT(oneshot->tch, GTIM_SR_UIF); - - /* The timer is no longer running */ - - oneshot->running = false; - - /* Forward the event, clearing out any vestiges */ - - oneshot_handler = (oneshot_handler_t)oneshot->handler; - oneshot->handler = NULL; - oneshot_arg = (void *)oneshot->arg; - oneshot->arg = NULL; - - oneshot_handler(oneshot_arg); - return OK; -} - -/**************************************************************************** - * Name: stm32_allocate_handler - * - * Description: - * Allocate a timer callback handler for the oneshot instance. - * - * Input Parameters: - * oneshot - The state instance the new oneshot timer - * - * Returned Value: - * Returns zero (OK) on success. This can only fail if the number of - * timers exceeds CONFIG_STM32_ONESHOT_MAXTIMERS. - * - ****************************************************************************/ - -static inline int stm32_allocate_handler(struct stm32_oneshot_s *oneshot) -{ -#if CONFIG_STM32_ONESHOT_MAXTIMERS > 1 - int ret = -EBUSY; - int i; - - /* Search for an unused handler */ - - for (i = 0; i < CONFIG_STM32_ONESHOT_MAXTIMERS; i++) - { - /* Is this handler available? */ - - if (g_oneshot[i] == NULL) - { - /* Yes... assign it to this oneshot */ - - g_oneshot[i] = oneshot; - oneshot->cbndx = i; - ret = OK; - break; - } - } - - return ret; - -#else - if (g_oneshot[0] == NULL) - { - g_oneshot[0] = oneshot; - return OK; - } - - return -EBUSY; -#endif -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_oneshot_initialize - * - * Description: - * Initialize the oneshot timer wrapper - * - * Input Parameters: - * oneshot Caller allocated instance of the oneshot state structure - * chan Timer counter channel to be used. - * resolution The required resolution of the timer in units of - * microseconds. NOTE that the range is restricted to the - * range of uint16_t (excluding zero). - * - * Returned Value: - * Zero (OK) is returned on success; a negated errno value is returned - * on failure. - * - ****************************************************************************/ - -int stm32_oneshot_initialize(struct stm32_oneshot_s *oneshot, int chan, - uint16_t resolution) -{ - uint32_t frequency; - - tmrinfo("chan=%d resolution=%d usec\n", chan, resolution); - DEBUGASSERT(oneshot && resolution > 0); - - /* Get the TC frequency the corresponds to the requested resolution */ - - frequency = USEC_PER_SEC / (uint32_t)resolution; - oneshot->frequency = frequency; - - oneshot->tch = stm32_tim_init(chan); - if (!oneshot->tch) - { - tmrerr("ERROR: Failed to allocate TIM%d\n", chan); - return -EBUSY; - } - - STM32_TIM_SETCLOCK(oneshot->tch, frequency); - - /* Initialize the remaining fields in the state structure. */ - - oneshot->chan = chan; - oneshot->running = false; - oneshot->handler = NULL; - oneshot->arg = NULL; - - /* Assign a callback handler to the oneshot */ - - return stm32_allocate_handler(oneshot); -} - -/**************************************************************************** - * Name: stm32_oneshot_max_delay - * - * Description: - * Determine the maximum delay of the one-shot timer (in microseconds) - * - ****************************************************************************/ - -int stm32_oneshot_max_delay(struct stm32_oneshot_s *oneshot, uint64_t *usec) -{ - DEBUGASSERT(oneshot != NULL && usec != NULL); - - *usec = (uint64_t)(UINT32_MAX / oneshot->frequency) * - (uint64_t)USEC_PER_SEC; - return OK; -} - -/**************************************************************************** - * Name: stm32_oneshot_start - * - * Description: - * Start the oneshot timer - * - * Input Parameters: - * oneshot Caller allocated instance of the oneshot state structure. This - * structure must have been previously initialized via a call to - * stm32_oneshot_initialize(); - * handler The function to call when when the oneshot timer expires. - * arg An opaque argument that will accompany the callback. - * ts Provides the duration of the one shot timer. - * - * Returned Value: - * Zero (OK) is returned on success; a negated errno value is returned - * on failure. - * - ****************************************************************************/ - -int stm32_oneshot_start(struct stm32_oneshot_s *oneshot, - oneshot_handler_t handler, void *arg, - const struct timespec *ts) -{ - uint64_t usec; - uint64_t period; - irqstate_t flags; - - tmrinfo("handler=%p arg=%p, ts=(%jd, %ld)\n", - handler, arg, (intmax_t)ts->tv_sec, ts->tv_nsec); - DEBUGASSERT(oneshot && handler && ts); - DEBUGASSERT(oneshot->tch); - - /* Was the oneshot already running? */ - - flags = enter_critical_section(); - if (oneshot->running) - { - /* Yes.. then cancel it */ - - tmrinfo("Already running... cancelling\n"); - stm32_oneshot_cancel(oneshot, NULL); - } - - /* Save the new handler and its argument */ - - oneshot->handler = handler; - oneshot->arg = arg; - - /* Express the delay in microseconds */ - - usec = ts->tv_sec * USEC_PER_SEC + - (ts->tv_nsec / NSEC_PER_USEC); - - /* Get the timer counter frequency and determine the number of counts need - * to achieve the requested delay. - * - * frequency = ticks / second - * ticks = seconds * frequency - * = (usecs * frequency) / USEC_PER_SEC; - */ - - period = (usec * (uint64_t)oneshot->frequency) / USEC_PER_SEC; - - tmrinfo("usec=%llu period=%08llx\n", usec, period); - DEBUGASSERT(period <= UINT32_MAX); - - /* Set up to receive the callback when the interrupt occurs */ - - STM32_TIM_SETISR(oneshot->tch, stm32_oneshot_handler, oneshot, 0); - - /* Set timer period */ - - oneshot->period = (uint32_t)period; - STM32_TIM_SETPERIOD(oneshot->tch, (uint32_t)period); - - /* Start the counter */ - - STM32_TIM_SETMODE(oneshot->tch, STM32_TIM_MODE_PULSE); - - STM32_TIM_ACKINT(oneshot->tch, GTIM_SR_UIF); - STM32_TIM_ENABLEINT(oneshot->tch, GTIM_DIER_UIE); - - /* Enable interrupts. We should get the callback when the interrupt - * occurs. - */ - - oneshot->running = true; - leave_critical_section(flags); - return OK; -} - -/**************************************************************************** - * Name: stm32_oneshot_cancel - * - * Description: - * Cancel the oneshot timer and return the time remaining on the timer. - * - * NOTE: This function may execute at a high rate with no timer running (as - * when pre-emption is enabled and disabled). - * - * Input Parameters: - * oneshot Caller allocated instance of the oneshot state structure. This - * structure must have been previously initialized via a call to - * stm32_oneshot_initialize(); - * ts The location in which to return the time remaining on the - * oneshot timer. A time of zero is returned if the timer is - * not running. ts may be zero in which case the time remaining - * is not returned. - * - * Returned Value: - * Zero (OK) is returned on success. A call to up_timer_cancel() when - * the timer is not active should also return success; a negated errno - * value is returned on any failure. - * - ****************************************************************************/ - -int stm32_oneshot_cancel(struct stm32_oneshot_s *oneshot, - struct timespec *ts) -{ - irqstate_t flags; - uint64_t usec; - uint64_t sec; - uint64_t nsec; - uint32_t count; - uint32_t period; - - /* Was the timer running? */ - - flags = enter_critical_section(); - if (!oneshot->running) - { - /* No.. Just return zero timer remaining and successful cancellation. - * This function may execute at a high rate with no timer running - * (as when pre-emption is enabled and disabled). - */ - - ts->tv_sec = 0; - ts->tv_nsec = 0; - leave_critical_section(flags); - return OK; - } - - /* Yes.. Get the timer counter and period registers and stop the counter. - * If the counter expires while we are doing this, the counter clock will - * be stopped, but the clock will not be disabled. - * - * The expected behavior is that the counter register will freezes at - * a value equal to the RC register when the timer expires. The counter - * should have values between 0 and RC in all other cased. - * - * REVISIT: This does not appear to be the case. - */ - - tmrinfo("Cancelling...\n"); - - count = STM32_TIM_GETCOUNTER(oneshot->tch); - period = oneshot->period; - - /* Now we can disable the interrupt and stop the timer. */ - - STM32_TIM_DISABLEINT(oneshot->tch, GTIM_DIER_UIE); - STM32_TIM_SETISR(oneshot->tch, NULL, NULL, 0); - STM32_TIM_SETMODE(oneshot->tch, STM32_TIM_MODE_DISABLED); - - oneshot->running = false; - oneshot->handler = NULL; - oneshot->arg = NULL; - leave_critical_section(flags); - - /* Did the caller provide us with a location to return the time - * remaining? - */ - - if (ts) - { - /* Yes.. then calculate and return the time remaining on the - * oneshot timer. - */ - - tmrinfo("period=%lu count=%lu\n", - (unsigned long)period, (unsigned long)count); - - /* REVISIT: I am not certain why the timer counter value sometimes - * exceeds RC. Might be a bug, or perhaps the counter does not stop - * in all cases. - */ - - if (count >= period) - { - /* No time remaining (?) */ - - ts->tv_sec = 0; - ts->tv_nsec = 0; - } - else - { - /* The total time remaining is the difference. Convert that - * to units of microseconds. - * - * frequency = ticks / second - * seconds = ticks * frequency - * usecs = (ticks * USEC_PER_SEC) / frequency; - */ - - usec = (((uint64_t)(period - count)) * USEC_PER_SEC) / - oneshot->frequency; - - /* Return the time remaining in the correct form */ - - sec = usec / USEC_PER_SEC; - nsec = ((usec) - (sec * USEC_PER_SEC)) * NSEC_PER_USEC; - - ts->tv_sec = sec; - ts->tv_nsec = nsec; - } - - tmrinfo("remaining (%jd, %ld)\n", - (intmax_t)ts->tv_sec, ts->tv_nsec); - } - - return OK; -} - -#endif /* CONFIG_STM32_ONESHOT */ diff --git a/arch/arm/src/stm32/stm32_oneshot.h b/arch/arm/src/stm32/stm32_oneshot.h deleted file mode 100644 index 913321fa60ea2..0000000000000 --- a/arch/arm/src/stm32/stm32_oneshot.h +++ /dev/null @@ -1,197 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_oneshot.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32_STM32_ONESHOT_H -#define __ARCH_ARM_SRC_STM32_STM32_ONESHOT_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include - -#include "stm32_tim.h" - -#ifdef CONFIG_STM32_ONESHOT - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#if !defined(CONFIG_STM32_ONESHOT_MAXTIMERS) || \ - CONFIG_STM32_ONESHOT_MAXTIMERS < 1 -# undef CONFIG_STM32_ONESHOT_MAXTIMERS -# define CONFIG_STM32_ONESHOT_MAXTIMERS 1 -#endif - -#if CONFIG_STM32_ONESHOT_MAXTIMERS > 8 -# warning Additional logic required to handle more than 8 timers -# undef CONFIG_STM32_ONESHOT_MAXTIMERS -# define CONFIG_STM32_ONESHOT_MAXTIMERS 8 -#endif - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -/* This describes the callback function that will be invoked when the oneshot - * timer expires. The oneshot fires, the client will receive: - * - * arg - The opaque argument provided when the interrupt was registered - */ - -typedef void (*oneshot_handler_t)(void *arg); - -/* The oneshot client must allocate an instance of this structure and called - * stm32_oneshot_initialize() before using the oneshot facilities. The - * client should not access the contents of this structure directly since - * the contents are subject to change. - */ - -struct stm32_oneshot_s -{ - uint8_t chan; /* The timer/counter in use */ -#if CONFIG_STM32_ONESHOT_MAXTIMERS > 1 - uint8_t cbndx; /* Timer callback handler index */ -#endif - volatile bool running; /* True: the timer is running */ - struct stm32_tim_dev_s *tch; /* Pointer returned by - * stm32_tim_init() */ - volatile oneshot_handler_t handler; /* Oneshot expiration callback */ - volatile void *arg; /* The argument that will accompany - * the callback */ - uint32_t frequency; - uint32_t period; -}; - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_oneshot_initialize - * - * Description: - * Initialize the oneshot timer wrapper - * - * Input Parameters: - * oneshot Caller allocated instance of the oneshot state structure - * chan Timer counter channel to be used. - * resolution The required resolution of the timer in units of - * microseconds. NOTE that the range is restricted to the - * range of uint16_t (excluding zero). - * - * Returned Value: - * Zero (OK) is returned on success; a negated errno value is returned - * on failure. - * - ****************************************************************************/ - -int stm32_oneshot_initialize(struct stm32_oneshot_s *oneshot, int chan, - uint16_t resolution); - -/**************************************************************************** - * Name: stm32_oneshot_max_delay - * - * Description: - * Determine the maximum delay of the one-shot timer (in microseconds) - * - ****************************************************************************/ - -int stm32_oneshot_max_delay(struct stm32_oneshot_s *oneshot, uint64_t *usec); - -/**************************************************************************** - * Name: stm32_oneshot_start - * - * Description: - * Start the oneshot timer - * - * Input Parameters: - * oneshot Caller allocated instance of the oneshot state structure. This - * structure must have been previously initialized via a call to - * stm32_oneshot_initialize(); - * handler The function to call when when the oneshot timer expires. - * arg An opaque argument that will accompany the callback. - * ts Provides the duration of the one shot timer. - * - * Returned Value: - * Zero (OK) is returned on success; a negated errno value is returned - * on failure. - * - ****************************************************************************/ - -int stm32_oneshot_start(struct stm32_oneshot_s *oneshot, - oneshot_handler_t handler, void *arg, - const struct timespec *ts); - -/**************************************************************************** - * Name: stm32_oneshot_cancel - * - * Description: - * Cancel the oneshot timer and return the time remaining on the timer. - * - * NOTE: This function may execute at a high rate with no timer running (as - * when pre-emption is enabled and disabled). - * - * Input Parameters: - * oneshot Caller allocated instance of the oneshot state structure. This - * structure must have been previously initialized via a call to - * stm32_oneshot_initialize(); - * ts The location in which to return the time remaining on the - * oneshot timer. A time of zero is returned if the timer is - * not running. - * - * Returned Value: - * Zero (OK) is returned on success. A call to up_timer_cancel() when - * the timer is not active should also return success; a negated errno - * value is returned on any failure. - * - ****************************************************************************/ - -int stm32_oneshot_cancel(struct stm32_oneshot_s *oneshot, - struct timespec *ts); - -#undef EXTERN -#ifdef __cplusplus -} -#endif - -#endif /* CONFIG_STM32_ONESHOT */ -#endif /* __ARCH_ARM_SRC_STM32_STM32_ONESHOT_H */ diff --git a/arch/arm/src/stm32/stm32_oneshot_lowerhalf.c b/arch/arm/src/stm32/stm32_oneshot_lowerhalf.c deleted file mode 100644 index 8d5c5c79a2861..0000000000000 --- a/arch/arm/src/stm32/stm32_oneshot_lowerhalf.c +++ /dev/null @@ -1,309 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_oneshot_lowerhalf.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include -#include -#include - -#include "stm32_oneshot.h" - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/* This structure describes the state of the oneshot timer lower-half driver - */ - -struct stm32_oneshot_lowerhalf_s -{ - /* This is the part of the lower half driver that is visible to the upper- - * half client of the driver. This must be the first thing in this - * structure so that pointers to struct oneshot_lowerhalf_s are cast - * compatible to struct stm32_oneshot_lowerhalf_s and vice versa. - */ - - struct oneshot_lowerhalf_s lh; /* Common lower-half driver fields */ - - /* Private lower half data follows */ - - struct stm32_oneshot_s oneshot; /* STM32-specific oneshot state */ -}; - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -static void stm32_oneshot_handler(void *arg); - -static int stm32_max_delay(struct oneshot_lowerhalf_s *lower, - struct timespec *ts); -static int stm32_start(struct oneshot_lowerhalf_s *lower, - const struct timespec *ts); -static int stm32_cancel(struct oneshot_lowerhalf_s *lower, - struct timespec *ts); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* Lower half operations */ - -static const struct oneshot_operations_s g_oneshot_ops = -{ - .max_delay = stm32_max_delay, - .start = stm32_start, - .cancel = stm32_cancel, -}; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_oneshot_handler - * - * Description: - * Timer expiration handler - * - * Input Parameters: - * arg - Should be the same argument provided when stm32_oneshot_start() - * was called. - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void stm32_oneshot_handler(void *arg) -{ - struct stm32_oneshot_lowerhalf_s *priv = - (struct stm32_oneshot_lowerhalf_s *)arg; - - DEBUGASSERT(priv != NULL); - - /* Perhaps the callback was nullified in a race condition with - * stm32_cancel? - */ - - oneshot_process_callback(&priv->lh); -} - -/**************************************************************************** - * Name: stm32_max_delay - * - * Description: - * Determine the maximum delay of the one-shot timer (in microseconds) - * - * Input Parameters: - * lower An instance of the lower-half oneshot state structure. This - * structure must have been previously initialized via a call to - * oneshot_initialize(); - * ts The location in which to return the maximum delay. - * - * Returned Value: - * Zero (OK) is returned on success; a negated errno value is returned - * on failure. - * - ****************************************************************************/ - -static int stm32_max_delay(struct oneshot_lowerhalf_s *lower, - struct timespec *ts) -{ - struct stm32_oneshot_lowerhalf_s *priv = - (struct stm32_oneshot_lowerhalf_s *)lower; - uint64_t usecs; - int ret; - - DEBUGASSERT(priv != NULL && ts != NULL); - ret = stm32_oneshot_max_delay(&priv->oneshot, &usecs); - if (ret >= 0) - { - uint64_t sec = usecs / 1000000; - usecs -= 1000000 * sec; - - ts->tv_sec = sec; - ts->tv_nsec = usecs * 1000; - } - - return ret; -} - -/**************************************************************************** - * Name: stm32_start - * - * Description: - * Start the oneshot timer - * - * Input Parameters: - * lower An instance of the lower-half oneshot state structure. This - * structure must have been previously initialized via a call to - * oneshot_initialize(); - * handler The function to call when when the oneshot timer expires. - * arg An opaque argument that will accompany the callback. - * ts Provides the duration of the one shot timer. - * - * Returned Value: - * Zero (OK) is returned on success; a negated errno value is returned - * on failure. - * - ****************************************************************************/ - -static int stm32_start(struct oneshot_lowerhalf_s *lower, - const struct timespec *ts) -{ - struct stm32_oneshot_lowerhalf_s *priv = - (struct stm32_oneshot_lowerhalf_s *)lower; - irqstate_t flags; - int ret; - - DEBUGASSERT(priv != NULL && ts != NULL); - - /* Save the callback information and start the timer */ - - flags = enter_critical_section(); - ret = stm32_oneshot_start(&priv->oneshot, - stm32_oneshot_handler, priv, ts); - leave_critical_section(flags); - - if (ret < 0) - { - tmrerr("ERROR: stm32_oneshot_start failed: %d\n", flags); - } - - return ret; -} - -/**************************************************************************** - * Name: stm32_cancel - * - * Description: - * Cancel the oneshot timer and return the time remaining on the timer. - * - * NOTE: This function may execute at a high rate with no timer running (as - * when pre-emption is enabled and disabled). - * - * Input Parameters: - * lower Caller allocated instance of the oneshot state structure. This - * structure must have been previously initialized via a call to - * oneshot_initialize(); - * ts The location in which to return the time remaining on the - * oneshot timer. A time of zero is returned if the timer is - * not running. - * - * Returned Value: - * Zero (OK) is returned on success. A call to up_timer_cancel() when - * the timer is not active should also return success; a negated errno - * value is returned on any failure. - * - ****************************************************************************/ - -static int stm32_cancel(struct oneshot_lowerhalf_s *lower, - struct timespec *ts) -{ - struct stm32_oneshot_lowerhalf_s *priv = - (struct stm32_oneshot_lowerhalf_s *)lower; - irqstate_t flags; - int ret; - - DEBUGASSERT(priv != NULL); - - /* Cancel the timer */ - - flags = enter_critical_section(); - ret = stm32_oneshot_cancel(&priv->oneshot, ts); - leave_critical_section(flags); - - if (ret < 0) - { - tmrerr("ERROR: stm32_oneshot_cancel failed: %d\n", flags); - } - - return ret; -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: oneshot_initialize - * - * Description: - * Initialize the oneshot timer and return a oneshot lower half driver - * instance. - * - * Input Parameters: - * chan Timer counter channel to be used. - * resolution The required resolution of the timer in units of - * microseconds. NOTE that the range is restricted to the - * range of uint16_t (excluding zero). - * - * Returned Value: - * On success, a non-NULL instance of the oneshot lower-half driver is - * returned. NULL is return on any failure. - * - ****************************************************************************/ - -struct oneshot_lowerhalf_s *oneshot_initialize(int chan, - uint16_t resolution) -{ - struct stm32_oneshot_lowerhalf_s *priv; - int ret; - - /* Allocate an instance of the lower half driver */ - - priv = (struct stm32_oneshot_lowerhalf_s *) - kmm_zalloc(sizeof(struct stm32_oneshot_lowerhalf_s)); - - if (priv == NULL) - { - tmrerr("ERROR: Failed to initialized state structure\n"); - return NULL; - } - - /* Initialize the lower-half driver structure */ - - priv->lh.ops = &g_oneshot_ops; - - /* Initialize the contained STM32 oneshot timer */ - - ret = stm32_oneshot_initialize(&priv->oneshot, chan, resolution); - if (ret < 0) - { - tmrerr("ERROR: stm32_oneshot_initialize failed: %d\n", ret); - kmm_free(priv); - return NULL; - } - - return &priv->lh; -} diff --git a/arch/arm/src/stm32/stm32_opamp.c b/arch/arm/src/stm32/stm32_opamp.c deleted file mode 100644 index 05f685eab55a4..0000000000000 --- a/arch/arm/src/stm32/stm32_opamp.c +++ /dev/null @@ -1,1409 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_opamp.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include - -#include -#include -#include - -#include "chip.h" -#include "stm32_gpio.h" -#include "stm32_opamp.h" - -/* OPAMP "upper half" support must be enabled */ - -#ifdef CONFIG_STM32_OPAMP - -/* Some OPAMP peripheral must be enabled */ - -/* Up to 4 OPAMPs in STM32F3 Series */ - -#if defined(CONFIG_STM32_OPAMP1) || defined(CONFIG_STM32_OPAMP2) || \ - defined(CONFIG_STM32_OPAMP3) || defined(CONFIG_STM32_OPAMP4) - -#ifndef CONFIG_STM32_SYSCFG -# error "SYSCFG clock enable must be set" -#endif - -/* @TODO: support for STM32F30XX opamps */ - -#if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) - -/* Currently only STM32F33XX supported */ - -#if defined(CONFIG_STM32_STM32F30XX) -# error "Not supported yet" -#endif - -#if defined(CONFIG_STM32_STM32F33XX) -# if defined(CONFIG_STM32_OPAMP1) || defined(CONFIG_STM32_OPAMP3) || \ - defined(CONFIG_STM32_OPAMP4) -# error "STM32F33 supports only OPAMP2" -# endif -#endif - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* OPAMPs default configuration *********************************************/ - -#ifdef CONFIG_STM32_OPAMP1 -# ifndef OPAMP1_MODE -# define OPAMP1_MODE OPAMP_MODE_DEFAULT -# endif -# ifndef OPAMP1_MUX -# define OPAMP1_MUX OPAMP_MUX_DEFAULT -# endif -# ifndef OPAMP1_USERCAL -# define OPAMP1_USERCAL OPAMP_USERCAL_DEFAULT -# endif -# ifndef OPAMP1_LOCK -# define OPAMP1_LOCK OPAMP_LOCK_DEFAULT -# endif -# ifndef OPAMP1_GAIN -# define OPAMP1_GAIN OPAMP_GAIN_DEFAULT -# endif -#endif -#ifdef CONFIG_STM32_OPAMP2 -# ifndef OPAMP2_MODE -# define OPAMP2_MODE OPAMP_MODE_DEFAULT -# endif -# ifndef OPAMP2_MUX -# define OPAMP2_MUX OPAMP_MUX_DEFAULT -# endif -# ifndef OPAMP2_USERCAL -# define OPAMP2_USERCAL OPAMP_USERCAL_DEFAULT -# endif -# ifndef OPAMP2_LOCK -# define OPAMP2_LOCK OPAMP_LOCK_DEFAULT -# endif -# ifndef OPAMP2_GAIN -# define OPAMP2_GAIN OPAMP_GAIN_DEFAULT -# endif -#endif -#ifdef CONFIG_STM32_OPAMP3 -# ifndef OPAMP3_MODE -# define OPAMP3_MODE OPAMP_MODE_DEFAULT -# endif -# ifndef OPAMP3_MUX -# define OPAMP3_MUX OPAMP_MUX_DEFAULT -# endif -# ifndef OPAMP3_USERCAL -# define OPAMP3_USERCAL OPAMP_USERCAL_DEFAULT -# endif -# ifndef OPAMP3_LOCK -# define OPAMP3_LOCK OPAMP_LOCK_DEFAULT -# endif -# ifndef OPAMP3_GAIN -# define OPAMP3_GAIN OPAMP_GAIN_DEFAULT -# endif -#endif -#ifdef CONFIG_STM32_OPAMP4 -# ifndef OPAMP4_MODE -# define OPAMP4_MODE OPAMP_MODE_DEFAULT -# endif -# ifndef OPAMP4_MUX -# define OPAMP4_MUX OPAMP_MUX_DEFAULT -# endif -# ifndef OPAMP4_USERCAL -# define OPAMP4_USERCAL OPAMP_USERCAL_DEFAULT -# endif -# ifndef OPAMP4_LOCK -# define OPAMP4_LOCK OPAMP_LOCK_DEFAULT -# endif -# ifndef OPAMP4_GAIN -# define OPAMP4_GAIN OPAMP_GAIN_DEFAULT -# endif -#endif - -/* Some assertions *********************************************************/ - -/* Check OPAMPs inputs selection */ - -#ifdef CONFIG_STM32_OPAMP1 -# if (OPAMP1_MODE == OPAMP_MODE_FOLLOWER) -# define OPAMP1_VMSEL OPAMP1_VMSEL_FOLLOWER -# endif -# if (OPAMP1_MODE == OPAMP_MODE_PGA) -# define OPAMP1_VMSEL OPAMP1_VMSEL_PGA -# endif -# if (OPAMP1_MODE == OPAMP_MODE_STANDALONE) -# ifndef OPAMP1_VMSEL -# error "OPAMP1_VMSEL must be selected in standalone mode!" -# endif -# endif -# ifndef OPAMP1_VPSEL -# error "OPAMP1_VPSEL must be selected in standalone mode!" -# endif -#endif -#ifdef CONFIG_STM32_OPAMP2 -# if (OPAMP2_MODE == OPAMP_MODE_FOLLOWER) -# define OPAMP2_VMSEL OPAMP2_VMSEL_FOLLOWER -# endif -# if (OPAMP2_MODE == OPAMP_MODE_PGA) -# define OPAMP2_VMSEL OPAMP2_VMSEL_PGA -# endif -# if (OPAMP2_MODE == OPAMP_MODE_STANDALONE) -# ifndef OPAMP2_VMSEL -# error "OPAMP2_VMSEL must be selected in standalone mode!" -# endif -# endif -# ifndef OPAMP2_VPSEL -# error "OPAMP2_VPSEL must be selected in standalone mode!" -# endif -#endif -#ifdef CONFIG_STM32_OPAMP3 -# if (OPAMP3_MODE == OPAMP_MODE_FOLLOWER) -# define OPAMP3_VMSEL OPAMP3_VMSEL_FOLLOWER -# endif -# if (OPAMP3_MODE == OPAMP_MODE_PGA) -# define OPAMP3_VMSEL OPAMP3_VMSEL_PGA -# endif -# if (OPAMP3_MODE == OPAMP_MODE_STANDALONE) -# ifndef OPAMP3_VMSEL -# error "OPAMP3_VMSEL must be selected in standalone mode!" -# endif -# endif -# ifndef OPAMP3_VPSEL -# error "OPAMP3_VPSEL must be selected in standalone mode!" -# endif -#endif -#ifdef CONFIG_STM32_OPAMP4 -# if (OPAMP4_MODE == OPAMP_MODE_FOLLOWER) -# define OPAMP4_VMSEL OPAMP4_VMSEL_FOLLOWER -# endif -# if (OPAMP4_MODE == OPAMP_MODE_PGA) -# define OPAMP4_VMSEL OPAMP4_VMSEL_PGA -# endif -# if (OPAMP4_MODE == OPAMP_MODE_STANDALONE) -# ifndef OPAMP4_VMSEL -# error "OPAMP4_VMSEL must be selected in standalone mode!" -# endif -# endif -# ifndef OPAMP4_VPSEL -# error "OPAMP4_VPSEL must be selected in standalone mode!" -# endif -#endif - -/* When OPAMP MUX enabled, make sure that secondary selection inputs are - * configured - */ - -#ifdef CONFIG_STM32_OPAMP1 -# if (OPAMP1_MUX == OPAMP_MUX_ENABLE) -# if !defined(OPAMP1_VMSSEL) || !defined(OPAMP1_VPSSEL) -# error "OPAMP1_VMSSEL and OPAMP1_VPSSEL must be selected when OPAMP1 MUX enabled!" -# endif -# endif -#endif -#ifdef CONFIG_STM32_OPAMP2 -# if (OPAMP2_MUX == OPAMP_MUX_ENABLE) -# if !defined(OPAMP2_VMSSEL) || !defined(OPAMP2_VPSSEL) -# error "OPAMP2_VMSSEL and OPAMP2_VPSSEL must be selected when OPAMP2 MUX enabled!" -# endif -# endif -#endif -#ifdef CONFIG_STM32_OPAMP3 -# if (OPAMP3_MUX == OPAMP_MUX_ENABLE) -# if !defined(OPAMP3_VMSSEL) || !defined(OPAMP3_VPSSEL) -# error "OPAMP3_VMSSEL and OPAMP3_VPSSEL must be selected when OPAMP3 MUX enabled!" -# endif -# endif -#endif -#ifdef CONFIG_STM32_OPAMP4 -# if (OPAMP4_MUX == OPAMP_MUX_ENABLE) -# if !defined(OPAMP4_VMSSEL) || !defined(OPAMP4_VPSSEL) -# error "OPAMP4_VMSSEL and OPAMP4_VPSSEL must be selected when OPAMP4 MUX enabled!" -# endif -# endif -#endif - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/* This structure describes the configuration of one OPAMP device */ - -struct stm32_opamp_s -{ - uint32_t csr; /* Control and status register */ - - uint8_t lock:1; /* OPAMP lock */ - uint8_t mux:1; /* Timer controlled MUX mode */ - uint8_t mode:2; /* OPAMP mode */ - uint8_t gain:4; /* OPAMP gain in PGA mode */ - - uint8_t vm_sel:2; /* Inverting input selection */ - uint8_t vp_sel:2; /* Non inverting input selection */ - uint8_t vms_sel:2; /* Inverting input secondary selection (MUX mode) */ - uint8_t vps_sel:2; /* Non inverting input secondary selection (Mux mode) */ - - uint16_t trim_n:5; /* Offset trimming value (NMOS) */ - uint16_t trim_p:5; /* Offset trimming value (PMOS) */ - uint16_t _reserved:6; /* reserved for calibration */ -}; - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -/* OPAMP Register access */ - -static inline void opamp_modify_csr(struct stm32_opamp_s *priv, - uint32_t clearbits, uint32_t setbits); -static inline uint32_t opamp_getreg_csr(struct stm32_opamp_s *priv); -static inline void opamp_putreg_csr(struct stm32_opamp_s *priv, - uint32_t value); -static bool stm32_opamplock_get(struct stm32_opamp_s *priv); -static int stm32_opamplock(struct stm32_opamp_s *priv, bool lock); - -/* Initialization */ - -static int stm32_opampconfig(struct stm32_opamp_s *priv); -static int stm32_opampenable(struct stm32_opamp_s *priv, bool enable); -static int stm32_opampgain_set(struct stm32_opamp_s *priv, uint8_t gain); -#if 0 -static int stm32_opampcalibrate(struct stm32_opamp_s *priv); -#endif - -/* OPAMP Driver Methods */ - -static void opamp_shutdown(struct opamp_dev_s *dev); -static int opamp_setup(struct opamp_dev_s *dev); -static int opamp_ioctl(struct opamp_dev_s *dev, int cmd, - unsigned long arg); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -static const struct opamp_ops_s g_opampops = -{ - .ao_shutdown = opamp_shutdown, - .ao_setup = opamp_setup, - .ao_ioctl = opamp_ioctl -}; - -#ifdef CONFIG_STM32_OPAMP1 -static struct stm32_opamp_s g_opamp1priv = -{ - .csr = STM32_OPAMP1_CSR, - .lock = OPAMP1_LOCK, - .mux = OPAMP1_MUX, - .mode = OPAMP1_MODE, - .vm_sel = OPAMP1_VMSEL, - .vp_sel = OPAMP1_VPSEL, -#if OPAMP1_MUX == OPAMP_MUX_ENABLE - .vms_sel = OPAMP1_VMSSEL, - .vps_sel = OPAMP1_VPSSEL, -#endif - .gain = OPAMP1_GAIN -}; - -static struct opamp_dev_s g_opamp1dev = -{ - .ad_ops = &g_opampops, - .ad_priv = &g_opamp1priv -}; -#endif - -#ifdef CONFIG_STM32_OPAMP2 -static struct stm32_opamp_s g_opamp2priv = -{ - .csr = STM32_OPAMP2_CSR, - .lock = OPAMP2_LOCK, - .mux = OPAMP2_MUX, - .mode = OPAMP2_MODE, - .vm_sel = OPAMP2_VMSEL, - .vp_sel = OPAMP2_VPSEL, -#if OPAMP2_MUX == OPAMP_MUX_ENABLE - .vms_sel = OPAMP2_VMSSEL, - .vps_sel = OPAMP2_VPSSEL, -#endif - .gain = OPAMP2_GAIN -}; - -static struct opamp_dev_s g_opamp2dev = - { - .ad_ops = &g_opampops, - .ad_priv = &g_opamp2priv - }; -#endif - -#ifdef CONFIG_STM32_OPAMP3 -static struct stm32_opamp_s g_opamp3priv = -{ - .csr = STM32_OPAMP3_CSR, - .lock = OPAMP3_LOCK, - .mux = OPAMP3_MUX, - .mode = OPAMP3_MODE, - .vm_sel = OPAMP3_VMSEL, - .vp_sel = OPAMP3_VPSEL, -#if OPAMP3_MUX == OPAMP_MUX_ENABLE - .vms_sel = OPAMP3_VMSSEL, - .vps_sel = OPAMP3_VPSSEL, -#endif - .gain = OPAMP3_GAIN -}; - -static struct opamp_dev_s g_opamp3dev = -{ - .ad_ops = &g_opampops, - .ad_priv = &g_opamp3priv -}; -#endif - -#ifdef CONFIG_STM32_OPAMP4 -static struct stm32_opamp_s g_opamp4priv = -{ - .csr = STM32_OPAMP4_CSR, - .lock = OPAMP4_LOCK, - .mux = OPAMP4_MUX, - .mode = OPAMP4_MODE, - .vm_sel = OPAMP4_VMSEL, - .vp_sel = OPAMP4_VPSEL, -#if OPAMP4_MUX == OPAMP_MUX_ENABLE - .vms_sel = OPAMP4_VMSSEL, - .vps_sel = OPAMP4_VPSSEL, -#endif - .gain = OPAMP4_GAIN -}; - -static struct opamp_dev_s g_opamp4dev = -{ - .ad_ops = &g_opampops, - .ad_priv = &g_opamp4priv -}; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: opamp_modify_csr - * - * Description: - * Modify the value of a 32-bit OPAMP CSR register (not atomic). - * - * Input Parameters: - * priv - A reference to the OPAMP structure - * clrbits - The bits to clear - * setbits - The bits to set - * - * Returned Value: - * None - * - ****************************************************************************/ - -static inline void opamp_modify_csr(struct stm32_opamp_s *priv, - uint32_t clearbits, uint32_t setbits) -{ - uint32_t csr = priv->csr; - - modifyreg32(csr, clearbits, setbits); -} - -/**************************************************************************** - * Name: opamp_getreg_csr - * - * Description: - * Read the value of an OPAMP CSR register - * - * Input Parameters: - * priv - A reference to the OPAMP structure - * - * Returned Value: - * The current contents of the OPAMP CSR register - * - ****************************************************************************/ - -static inline uint32_t opamp_getreg_csr(struct stm32_opamp_s *priv) -{ - uint32_t csr = priv->csr; - - return getreg32(csr); -} - -/**************************************************************************** - * Name: opamp_putreg_csr - * - * Description: - * Write a value to an OPAMP register. - * - * Input Parameters: - * priv - A reference to the OPAMP structure - * value - The value to write to the OPAMP CSR register - * - * Returned Value: - * None - * - ****************************************************************************/ - -static inline void opamp_putreg_csr(struct stm32_opamp_s *priv, - uint32_t value) -{ - uint32_t csr = priv->csr; - - putreg32(value, csr); -} - -/**************************************************************************** - * Name: stm32_opamp_opamplock_get - * - * Description: - * Get OPAMP lock bit state - * - * Input Parameters: - * priv - A reference to the OPAMP structure - * - * Returned Value: - * True if OPAMP locked, false if not locked - * - ****************************************************************************/ - -static bool stm32_opamplock_get(struct stm32_opamp_s *priv) -{ - uint32_t regval; - - regval = opamp_getreg_csr(priv); - - return (((regval & OPAMP_CSR_LOCK) == 0) ? false : true); -} - -/**************************************************************************** - * Name: stm32_opamplock - * - * Description: - * Lock OPAMP CSR register - * - * Input Parameters: - * priv - A reference to the OPAMP structure - * enable - lock flag - * - * Returned Value: - * 0 on success, a negated errno value on failure - * - ****************************************************************************/ - -static int stm32_opamplock(struct stm32_opamp_s *priv, bool lock) -{ - bool current; - - current = stm32_opamplock_get(priv); - - if (current) - { - if (lock == false) - { - aerr("ERROR: OPAMP LOCK can be cleared only by a system reset\n"); - - return -EPERM; - } - } - else - { - if (lock == true) - { - opamp_modify_csr(priv, 0, OPAMP_CSR_LOCK); - - priv->lock = OPAMP_LOCK_RO; - } - } - - return OK; -} - -/**************************************************************************** - * Name: stm32_opampconfig - * - * Description: - * Configure OPAMP and used I/Os - * - * Input Parameters: - * priv - A reference to the OPAMP structure - * - * Returned Value: - * 0 on success, a negated errno value on failure - * - ****************************************************************************/ - -static int stm32_opampconfig(struct stm32_opamp_s *priv) -{ - uint32_t regval = 0; - int index; - - /* Get OPAMP index */ - - switch (priv->csr) - { -#ifdef CONFIG_STM32_OPAMP1 - case STM32_OPAMP1_CSR: - index = 1; - break; -#endif - -#ifdef CONFIG_STM32_OPAMP2 - case STM32_OPAMP2_CSR: - index = 2; - break; -#endif - -#ifdef CONFIG_STM32_OPAMP3 - case STM32_OPAMP3_CSR: - index = 3; - break; -#endif - -#ifdef CONFIG_STM32_OPAMP4 - case STM32_OPAMP4_CSR: - index = 4; - break; -#endif - - default: - return -EINVAL; - } - - /* Configure non inverting input */ - - switch (index) - { -#ifdef CONFIG_STM32_OPAMP1 - case 1: - { - switch (priv->vp_sel) - { - case OPAMP1_VPSEL_PA7: - stm32_configgpio(GPIO_OPAMP1_VINP_1); - regval |= OPAMP_CSR_VPSEL_PA7; - break; - - case OPAMP1_VPSEL_PA5: - stm32_configgpio(GPIO_OPAMP1_VINP_2); - regval |= OPAMP_CSR_VPSEL_PA5; - break; - - case OPAMP1_VPSEL_PA3: - stm32_configgpio(GPIO_OPAMP1_VINP_3); - regval |= OPAMP_CSR_VPSEL_PA3; - break; - - case OPAMP1_VPSEL_PA1: - stm32_configgpio(GPIO_OPAMP1_VINP_4); - regval |= OPAMP_CSR_VPSEL_PA1; - break; - - default: - return -EINVAL; - } - break; - } -#endif - -#ifdef CONFIG_STM32_OPAMP2 - case 2: - { - switch (priv->vp_sel) - { -#ifndef CONFIG_STM32_STM32F33XX - case OPAMP2_VPSEL_PD14: - stm32_configgpio(GPIO_OPAMP2_VINP_1); - regval |= OPAMP_CSR_VPSEL_PD14; - break; -#endif - case OPAMP2_VPSEL_PB14: - stm32_configgpio(GPIO_OPAMP2_VINP_2); - regval |= OPAMP_CSR_VPSEL_PB14; - break; - - case OPAMP2_VPSEL_PB0: - stm32_configgpio(GPIO_OPAMP2_VINP_3); - regval |= OPAMP_CSR_VPSEL_PB0; - break; - - case OPAMP2_VPSEL_PA7: - stm32_configgpio(GPIO_OPAMP2_VINP_4); - regval |= OPAMP_CSR_VPSEL_PA7; - break; - - default: - return -EINVAL; - } - break; - } -#endif - -#ifdef CONFIG_STM32_OPAMP3 - case 3: - { - switch (priv->vp_sel) - { - case OPAMP3_VPSEL_PB13: - stm32_configgpio(GPIO_OPAMP3_VINP_1); - regval |= OPAMP_CSR_VPSEL_PB13; - break; - - case OPAMP3_VPSEL_PA5: - stm32_configgpio(GPIO_OPAMP3_VINP_2); - regval |= OPAMP_CSR_VPSEL_PA5; - break; - - case OPAMP3_VPSEL_PA1: - stm32_configgpio(GPIO_OPAMP3_VINP_3); - regval |= OPAMP_CSR_VPSEL_PA1; - break; - - case OPAMP3_VPSEL_PB0: - stm32_configgpio(GPIO_OPAMP3_VINP_4); - regval |= OPAMP_CSR_VPSEL_PB0; - break; - - default: - return -EINVAL; - } - break; - } -#endif - -#ifdef CONFIG_STM32_OPAMP4 - case 4: - { - switch (priv->vp_sel) - { - case OPAMP4_VPSEL_PD11: - stm32_configgpio(GPIO_OPAMP4_VINP_1); - regval |= OPAMP_CSR_VPSEL_PD11; - break; - - case OPAMP4_VPSEL_PB11: - stm32_configgpio(GPIO_OPAMP4_VINP_2); - regval |= OPAMP_CSR_VPSEL_PB11; - break; - - case OPAMP4_VPSEL_PA4: - stm32_configgpio(GPIO_OPAMP4_VINP_3); - regval |= OPAMP_CSR_VPSEL_PA4; - break; - - case OPAMP4_VPSEL_PB13: - stm32_configgpio(GPIO_OPAMP4_VINP_4; - regval |= OPAMP_CSR_VPSEL_PB13; - break; - - default: - return -EINVAL; - } - break; - } -#endif - - default: - return -EINVAL; - } - - /* Configure inverting input */ - - switch (index) - { -#ifdef CONFIG_STM32_OPAMP1 - case 1: - { - switch (priv->vm_sel) - { - case OPAMP1_VSEL_PC5: - stm32_configgpio(GPIO_OPAMP1_VINM_1); - regval |= OPAMP_CSR_VMSEL_PC5; - break; - - case OPAMP1_VMSEL_PA3: - stm32_configgpio(GPIO_OPAMP1_VINM_2); - regval |= OPAMP_CSR_VMSEL_PA3; - break; - - case OPAMP1_VMSEL_PGAMODE: - regval |= OPAMP_CSR_VMSEL_PGA; - break; - - case OPAMP1_VMSEL_FOLLOWER: - regval |= OPAMP_CSR_VMSEL_FOLLOWER; - break; - - default: - return -EINVAL; - } - break; - } -#endif - -#ifdef CONFIG_STM32_OPAMP2 - case 2: - { - switch (priv->vm_sel) - { - case OPAMP2_VMSEL_PC5: - stm32_configgpio(GPIO_OPAMP2_VINM_1); - regval |= OPAMP_CSR_VMSEL_PC5; - break; - - case OPAMP2_VMSEL_PA5: - stm32_configgpio(GPIO_OPAMP2_VINM_2); - regval |= OPAMP_CSR_VMSEL_PA5; - break; - - case OPAMP2_VMSEL_PGAMODE: - regval |= OPAMP_CSR_VMSEL_PGA; - break; - - case OPAMP2_VMSEL_FOLLOWER: - regval |= OPAMP_CSR_VMSEL_FOLLOWER; - break; - - default: - return -EINVAL; - } - break; - } -#endif - -#ifdef CONFIG_STM32_OPAMP3 - case 3: - { - switch (priv->vm_sel) - { - case OPAMP3_VMSEL_PB10: - stm32_configgpio(GPIO_OPAMP3_VINM_1); - regval |= OPAMP_CSR_VMSEL_PB10; - break; - - case OPAMP3_VMSEL_PB2: - stm32_configgpio(GPIO_OPAMP3_VINM_2); - regval |= OPAMP_CSR_VMSEL_PB2; - break; - - case OPAMP3_VMSEL_PGAMODE: - regval |= OPAMP_CSR_VMSEL_PGA; - break; - - case OPAMP3_VMSEL_FOLLOWER: - regval |= OPAMP_CSR_VMSEL_FOLLOWER; - break; - - default: - return -EINVAL; - } - break; - } -#endif - -#ifdef CONFIG_STM32_OPAMP4 - case 4: - { - switch (priv->vm_sel) - { - case OPAMP4_VMSEL_PB10: - stm32_configgpio(GPIO_OPAMP4_VINM_1); - regval |= OPAMP_CSR_VMSEL_PB10; - break; - - case OPAMP4_VMSEL_PD8: - stm32_configgpio(GPIO_OPAMP4_VINM_2); - regval |= OPAMP_CSR_VMSEL_PD8; - break; - - case OPAMP4_VMSEL_PGAMODE: - regval |= OPAMP_CSR_VMSEL_PGA; - break; - - case OPAMP4_VMSEL_FOLLOWER: - regval |= OPAMP_CSR_VMSEL_FOLLOWER; - break; - - default: - return -EINVAL; - } - break; - } -#endif - - default: - return -EINVAL; - } - - if (priv->mux == 1) - { - /* Enable Timer controlled Mux mode */ - - regval |= OPAMP_CSR_TCMEN; - - /* Configure non inverting secondary input */ - - switch (index) - { -#ifdef CONFIG_STM32_OPAMP1 - case 1: - { - switch (priv->vps_sel) - { - case OPAMP1_VPSEL_PA7: - stm32_configgpio(GPIO_OPAMP1_VINP_1); - regval |= OPAMP_CSR_VPSSEL_PA7; - break; - - case OPAMP1_VPSEL_PA5: - stm32_configgpio(GPIO_OPAMP1_VINP_2); - regval |= OPAMP_CSR_VPSSEL_PA5; - break; - - case OPAMP1_VPSEL_PA3: - stm32_configgpio(GPIO_OPAMP1_VINP_3); - regval |= OPAMP_CSR_VPSSEL_PA3; - break; - - case OPAMP1_VPSEL_PA1: - stm32_configgpio(GPIO_OPAMP1_VINP_4); - regval |= OPAMP_CSR_VPSSEL_PA1; - break; - - default: - return -EINVAL; - } - break; - } -#endif - -#ifdef CONFIG_STM32_OPAMP2 - case 2: - { - switch (priv->vps_sel) - { -#ifndef CONFIG_STM32_STM32F33XX - case OPAMP2_VPSEL_PD14: - stm32_configgpio(GPIO_OPAMP2_VINP_1); - regval |= OPAMP_CSR_VPSSEL_PD14; - break; -#endif - case OPAMP2_VPSEL_PB14: - stm32_configgpio(GPIO_OPAMP2_VINP_2); - regval |= OPAMP_CSR_VPSSEL_PB14; - break; - - case OPAMP2_VPSEL_PB0: - stm32_configgpio(GPIO_OPAMP2_VINP_3); - regval |= OPAMP_CSR_VPSSEL_PB0; - break; - - case OPAMP2_VPSEL_PA7: - stm32_configgpio(GPIO_OPAMP2_VINP_4); - regval |= OPAMP_CSR_VPSSEL_PA7; - break; - - default: - return -EINVAL; - } - break; - } -#endif - -#ifdef CONFIG_STM32_OPAMP3 - case 3: - { - switch (priv->vps_sel) - { - case OPAMP3_VPSEL_PB13: - stm32_configgpio(GPIO_OPAMP3_VINP_1); - regval |= OPAMP_CSR_VPSSEL_PB13; - break; - - case OPAMP3_VPSEL_PA5: - stm32_configgpio(GPIO_OPAMP3_VINP_2); - regval |= OPAMP_CSR_VPSSEL_PA5; - break; - - case OPAMP3_VPSEL_PA1: - stm32_configgpio(GPIO_OPAMP3_VINP_3); - regval |= OPAMP_CSR_VPSSEL_PA1; - break; - - case OPAMP3_VPSEL_PB0: - stm32_configgpio(GPIO_OPAMP3_VINP_4); - regval |= OPAMP_CSR_VPSSEL_PB0; - break; - - default: - return -EINVAL; - } - break; - } -#endif - -#ifdef CONFIG_STM32_OPAMP4 - case 4: - { - switch (priv->vps_sel) - { - case OPAMP4_VPSEL_PD11: - stm32_configgpio(GPIO_OPAMP4_VINP_1); - regval |= OPAMP_CSR_VPSSEL_PD11; - break; - - case OPAMP4_VPSEL_PB11: - stm32_configgpio(GPIO_OPAMP4_VINP_2); - regval |= OPAMP_CSR_VPSSEL_PB11; - break; - - case OPAMP4_VPSEL_PA4: - stm32_configgpio(GPIO_OPAMP4_VINP_3); - regval |= OPAMP_CSR_VPSSEL_PA4; - break; - - case OPAMP4_VPSEL_PB13: - stm32_configgpio(GPIO_OPAMP4_VINP_4); - regval |= OPAMP_CSR_VPSSEL_PB13; - break; - - default: - return -EINVAL; - } - break; - } -#endif - - default: - return -EINVAL; - } - - /* Configure inverting secondary input */ - - switch (index) - { -#ifdef CONFIG_STM32_OPAMP1 - case 1: - { - switch (priv->vms_sel) - { - case OPAMP1_VSEL_PC5: - stm32_configgpio(GPIO_OPAMP1_VINM_1); - regval &= ~OPAMP_CSR_VMSSEL; - break; - - case OPAMP1_VMSEL_PA3: - stm32_configgpio(GPIO_OPAMP1_VINM_2); - regval |= OPAMP_CSR_VMSSEL; - break; - - default: - return -EINVAL; - } - break; - } -#endif - -#ifdef CONFIG_STM32_OPAMP2 - case 2: - { - switch (priv->vms_sel) - { - case OPAMP2_VMSEL_PC5: - stm32_configgpio(GPIO_OPAMP2_VINM_1); - regval &= ~OPAMP_CSR_VMSSEL; - break; - - case OPAMP2_VMSEL_PA5: - stm32_configgpio(GPIO_OPAMP2_VINM_2); - regval |= OPAMP_CSR_VMSSEL; - break; - - default: - return -EINVAL; - } - break; - } -#endif - -#ifdef CONFIG_STM32_OPAMP3 - case 3: - { - switch (priv->vms_sel) - { - case OPAMP3_VMSEL_PB10: - stm32_configgpio(GPIO_OPAMP3_VINM_1); - regval &= ~OPAMP_CSR_VMSSEL; - break; - - case OPAMP3_VMSEL_PB2: - stm32_configgpio(GPIO_OPAMP3_VINM_2); - regval |= OPAMP_CSR_VMSSEL; - break; - - default: - return -EINVAL; - } - break; - } -#endif - -#ifdef CONFIG_STM32_OPAMP4 - case 4: - { - switch (priv->vms_sel) - { - case OPAMP4_VMSEL_PB10: - stm32_configgpio(GPIO_OPAMP4_VINM_1); - regval &= ~OPAMP_CSR_VMSSEL; - break; - - case OPAMP4_VMSEL_PD8: - stm32_configgpio(GPIO_OPAMP4_VINM_2); - regval |= OPAMP_CSR_VMSSEL; - break; - - default: - return -EINVAL; - } - break; - } -#endif - - default: - return -EINVAL; - } - } - - /* Save CSR register */ - - opamp_putreg_csr(priv, regval); - - /* Configure default gain in PGA mode */ - - stm32_opampgain_set(priv, priv->gain); - - /* Enable OPAMP */ - - stm32_opampenable(priv, true); - - /* TODO: OPAMP user calibration */ - - /* stm32_opampcalibrate(priv); */ - - /* Lock OPAMP if needed */ - - if (priv->lock == OPAMP_LOCK_RO) - { - stm32_opamplock(priv, true); - } - - return OK; -} - -/**************************************************************************** - * Name: stm32_opampenable - * - * Description: - * Enable/disable OPAMP - * - * Input Parameters: - * priv - A reference to the OPAMP structure - * enable - enable/disable flag - * - * Returned Value: - * 0 on success, a negated errno value on failure - * - ****************************************************************************/ - -static int stm32_opampenable(struct stm32_opamp_s *priv, bool enable) -{ - bool lock; - - ainfo("enable: %d\n", enable ? 1 : 0); - - lock = stm32_opamplock_get(priv); - - if (lock) - { - aerr("ERROR: OPAMP locked!\n"); - - return -EPERM; - } - else - { - if (enable) - { - /* Enable the OPAMP */ - - opamp_modify_csr(priv, 0, OPAMP_CSR_OPAMPEN); - } - else - { - /* Disable the OPAMP */ - - opamp_modify_csr(priv, OPAMP_CSR_OPAMPEN, 0); - } - } - - return OK; -} - -/**************************************************************************** - * Name: stm32_opampgain_set - * - * Description: - * Set OPAMP gain - * - * Input Parameters: - * priv - A reference to the OPAMP structure - * gain - OPAMP gain - * - * Returned Value: - * 0 on success, a negated errno value on failure - * - ****************************************************************************/ - -static int stm32_opampgain_set(struct stm32_opamp_s *priv, uint8_t gain) -{ - bool lock; - uint32_t regval = 0; - - lock = stm32_opamplock_get(priv); - - if (lock) - { - aerr("ERROR: OPAMP locked!\n"); - return -EPERM; - } - - regval = opamp_getreg_csr(priv); - - switch (gain) - { - case OPAMP_GAIN_2: - regval |= OPAMP_CSR_PGAGAIN_2; - break; - case OPAMP_GAIN_4: - regval |= OPAMP_CSR_PGAGAIN_4; - break; - case OPAMP_GAIN_8: - regval |= OPAMP_CSR_PGAGAIN_8; - break; - case OPAMP_GAIN_2_VM0: - regval |= OPAMP_CSR_PGAGAIN_2VM0; - break; - case OPAMP_GAIN_4_VM0: - regval |= OPAMP_CSR_PGAGAIN_4VM0; - break; - case OPAMP_GAIN_8_VM0: - regval |= OPAMP_CSR_PGAGAIN_8VM0; - break; - case OPAMP_GAIN_16_VM0: - regval |= OPAMP_CSR_PGAGAIN_16VM0; - break; - case OPAMP_GAIN_2_VM1: - regval |= OPAMP_CSR_PGAGAIN_2VM1; - break; - case OPAMP_GAIN_4_VM1: - regval |= OPAMP_CSR_PGAGAIN_4VM1; - break; - case OPAMP_GAIN_8_VM1: - regval |= OPAMP_CSR_PGAGAIN_8VM1; - break; - case OPAMP_GAIN_16_VM1: - regval |= OPAMP_CSR_PGAGAIN_16VM1; - break; - default: - aerr("ERROR: Unsupported OPAMP gain\n"); - return -EINVAL; - } - - /* Update gain in OPAMP device structure */ - - priv->gain = gain; - - return OK; -} - -#if 0 -static int stm32_opampcalibrate(struct stm32_opamp_s *priv) -{ -#warning "Missing logic" - - return OK; -} -#endif - -/**************************************************************************** - * Name: opamp_shutdown - * - * Description: - * Disable the OPAMP. This method is called when the OPAMP device is - * closed. This method reverses the operation the setup method. - * Works only if OPAMP device is not locked. - * - * Input Parameters: - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void opamp_shutdown(struct opamp_dev_s *dev) -{ -#warning "Missing logic" -} - -/**************************************************************************** - * Name: opamp_setup - * - * Description: - * Configure the OPAMP. This method is called the first time that the OPAMP - * device is opened. This will occur when the port is first opened. - * This setup includes configuring and attaching OPAMP interrupts. - * Interrupts are all disabled upon return. - * - * Input Parameters: - * - * Returned Value: - * - ****************************************************************************/ - -static int opamp_setup(struct opamp_dev_s *dev) -{ -#warning "Missing logic" - return OK; -} - -/**************************************************************************** - * Name: opamp_ioctl - * - * Description: - * All ioctl calls will be routed through this method. - * - * Input Parameters: - * dev - pointer to device structure used by the driver - * cmd - command - * arg - arguments passed with command - * - * Returned Value: - * - ****************************************************************************/ - -static int opamp_ioctl(struct opamp_dev_s *dev, int cmd, - unsigned long arg) -{ -#warning "Missing logic" - return -ENOTTY; -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_opampinitialize - * - * Description: - * Initialize the OPAMP. - * - * Input Parameters: - * intf - The OPAMP interface number. - * - * Returned Value: - * Valid OPAMP device structure reference on success; a NULL on failure. - * - * Assumptions: - * 1. Clock to the OPAMP block has enabled, - * 2. Board-specific logic has already configured - * - ****************************************************************************/ - -struct opamp_dev_s *stm32_opampinitialize(int intf) -{ - struct opamp_dev_s *dev; - struct stm32_opamp_s *opamp; - int ret; - - switch (intf) - { -#ifdef CONFIG_STM32_OPAMP1 - case 1: - ainfo("OPAMP1 selected\n"); - dev = &g_opamp1dev; - break; -#endif - -#ifdef CONFIG_STM32_OPAMP2 - case 2: - ainfo("OPAMP2 selected\n"); - dev = &g_opamp2dev; - break; -#endif - -#ifdef CONFIG_STM32_OPAMP3 - case 3: - ainfo("OPAMP3 selected\n"); - dev = &g_opamp3dev; - break; -#endif - -#ifdef CONFIG_STM32_OPAMP4 - case 4: - ainfo("OPAMP4 selected\n"); - dev = &g_opamp4dev; - break; -#endif - - default: - aerr("ERROR: No OPAMP interface defined\n"); - return NULL; - } - - /* Configure selected OPAMP */ - - opamp = dev->ad_priv; - - ret = stm32_opampconfig(opamp); - if (ret < 0) - { - aerr("ERROR: Failed to initialize OPAMP%d: %d\n", intf, ret); - return NULL; - } - - return dev; -} - -#endif /* CONFIG_STM32_STM32F30XX || CONFIG_STM32_STM32F33XX*/ - -#endif /* CONFIG_STM32_OPAMP1 || CONFIG_STM32_OPAMP2 || - * CONFIG_STM32_OPAMP3 || CONFIG_STM32_OPAMP4 - */ - -#endif /* CONFIG_STM32_OPAMP */ diff --git a/arch/arm/src/stm32/stm32_opamp.h b/arch/arm/src/stm32/stm32_opamp.h deleted file mode 100644 index b85acb37bff16..0000000000000 --- a/arch/arm/src/stm32/stm32_opamp.h +++ /dev/null @@ -1,219 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_opamp.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32_STM32_OPAMP_H -#define __ARCH_ARM_SRC_STM32_STM32_OPAMP_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "chip.h" - -#ifdef CONFIG_STM32_OPAMP - -#if defined(CONFIG_STM32_STM32F30XX) -# error "OPAMP support for STM32F30XX not implemented yet" -#elif defined(CONFIG_STM32_STM32F33XX) -# include "hardware/stm32f33xxx_opamp.h" -#endif - -#include - -/**************************************************************************** - * Pre-processor definitions - ****************************************************************************/ - -/* OPAMP operation mode */ - -#define OPAMP_MODE_STANDALONE 0 -#define OPAMP_MODE_FOLLOWER 1 -#define OPAMP_MODE_PGA 2 - -/* Timer controlled Mux mode */ - -#define OPAMP_MUX_DISABLE 0 -#define OPAMP_MUX_ENABLE 1 - -/* User calibration */ - -#define OPAMP_USERCAL_DISABLE 0 -#define OPAMP_USERCAL_ENABLE 1 - -/* Default configuration */ - -#define OPAMP_MODE_DEFAULT OPAMP_MODE_STANDALONE /* Standalone mode */ -#define OPAMP_MUX_DEFAULT OPAMP_MUX_DISABLE /* MUX disabled */ -#define OPAMP_USERCAL_DEFAULT OPAMP_USERCAL_DISABLE /* User calibration disabled */ -#define OPAMP_GAIN_DEFAULT OPAMP_GAIN_2 /* Gain in PGA mode = 2 */ -#define OPAMP_LOCK_DEFAULT OPAMP_LOCK_RW /* Do not lock CSR register */ - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -/* CSR register lock state */ - -enum stm32_opamp_lock_e -{ - OPAMP_LOCK_RW, - OPAMP_LOCK_RO -}; - -/* Gain in PGA mode */ - -enum stm32_opamp_gain_e -{ - OPAMP_GAIN_2, - OPAMP_GAIN_4, - OPAMP_GAIN_8, - OPAMP_GAIN_2_VM0, - OPAMP_GAIN_4_VM0, - OPAMP_GAIN_8_VM0, - OPAMP_GAIN_16_VM0, - OPAMP_GAIN_2_VM1, - OPAMP_GAIN_4_VM1, - OPAMP_GAIN_8_VM1, - OPAMP_GAIN_16_VM1 -}; - -/* Input selection and secondary input selection use the same GPIOs */ - -#ifdef CONFIG_STM32_OPAMP1 -enum stm32_opamp1_vpsel_e -{ - OPAMP1_VPSEL_PA7, - OPAMP1_VPSEL_PA5, - OPAMP1_VPSEL_PA3, - OPAMP1_VPSEL_PA1 -}; - -enum stm32_opamp1_vmsel_e -{ - OPAMP1_VMSEL_PC5, - OPAMP1_VMSEL_PA3, - OPAMP1_VMSEL_PGAMODE, - OPAMP1_VMSEL_FOLLOWER, -}; -#endif - -#ifdef CONFIG_STM32_OPAMP2 -enum stm32_opamp2_vpsel_e -{ -#ifndef CONFIG_STM32_STM32F33XX - /* TODO: STM32F303xB/C and STM32F358C devices only */ - - OPAMP2_VPSEL_PD14, -#endif - OPAMP2_VPSEL_PB14, - OPAMP2_VPSEL_PB0, - OPAMP2_VPSEL_PA7 -}; - -enum stm32_opamp2_vmsel_e -{ - OPAMP2_VMSEL_PC5, - OPAMP2_VMSEL_PA5, - OPAMP2_VMSEL_PGAMODE, - OPAMP2_VMSEL_FOLLOWER -}; -#endif - -#ifdef CONFIG_STM32_OPAMP3 -enum stm32_opamp3_vpsel_e -{ - OPAMP3_VPSEL_PB13, - OPAMP3_VPSEL_PA5, - OPAMP3_VPSEL_PA1, - OPAMP3_VPSEL_PB0 -}; - -enum stm32_opamp3_vmsel_e -{ - OPAMP3_VMSEL_PB10, - OPAMP3_VMSEL_PB2, - OPAMP3_VMSEL_PGAMODE, - OPAMP3_VMSEL_FOLLOWER -}; -#endif - -#ifdef CONFIG_STM32_OPAMP4 -enum stm32_opamp4_vpsel_e -{ - OPAMP4_VPSEL_PD11, - OPAMP4_VPSEL_PB11, - OPAMP4_VPSEL_PA4, - OPAMP4_VPSEL_PB13 -}; - -enum stm32_opamp4_vmsel_e -{ - OPAMP4_VMSEL_PB10, - OPAMP4_VMSEL_PD8, - OPAMP4_VMSEL_PGAMODE, - OPAMP4_VMSEL_FOLLOWER -}; -#endif - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -#ifndef __ASSEMBLY__ -#ifdef __cplusplus -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Name: stm32_opampinitialize - * - * Description: - * Initialize the OPAMP. - * - * Input Parameters: - * intf - The OPAMP interface number. - * - * Returned Value: - * Valid OPAMP device structure reference on success; a NULL on failure. - * - * Assumptions: - * 1. Clock to the OPAMP block has enabled, - * 2. Board-specific logic has already configured - * - ****************************************************************************/ - -struct opamp_dev_s *stm32_opampinitialize(int intf); - -#undef EXTERN -#ifdef __cplusplus -} -#endif -#endif /* __ASSEMBLY__ */ - -#endif /* CONFIG_STM32_OPAMP */ -#endif /* __ARCH_ARM_SRC_STM32_STM32_OPAMP_H */ diff --git a/arch/arm/src/stm32/stm32_otgfsdev.c b/arch/arm/src/stm32/stm32_otgfsdev.c deleted file mode 100644 index 2f3c1416e7ee6..0000000000000 --- a/arch/arm/src/stm32/stm32_otgfsdev.c +++ /dev/null @@ -1,5871 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_otgfsdev.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include - -#include -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32_otgfs.h" -#include "stm32_rcc.h" - -#if defined(CONFIG_USBDEV) && (defined(CONFIG_STM32_OTGFS)) -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -#ifndef CONFIG_USBDEV_EP0_MAXSIZE -# define CONFIG_USBDEV_EP0_MAXSIZE 64 -#endif - -#ifndef CONFIG_USBDEV_SETUP_MAXDATASIZE -# define CONFIG_USBDEV_SETUP_MAXDATASIZE CONFIG_USBDEV_EP0_MAXSIZE -#endif - -#ifndef CONFIG_USBDEV_MAXPOWER -# define CONFIG_USBDEV_MAXPOWER 100 /* mA */ -#endif - -#ifndef CONFIG_DEBUG_USB_INFO -# undef CONFIG_STM32_USBDEV_REGDEBUG -#endif - -/* There is 1.25Kb of FIFO memory. The default partitions this memory - * so that there is a TxFIFO allocated for each endpoint and with more - * memory provided for the common RxFIFO. A more knowledge-able - * configuration would not allocate any TxFIFO space to OUT endpoints. - */ - -#ifndef CONFIG_USBDEV_RXFIFO_SIZE -# define CONFIG_USBDEV_RXFIFO_SIZE 512 -#endif - -#ifndef CONFIG_USBDEV_EP0_TXFIFO_SIZE -# define CONFIG_USBDEV_EP0_TXFIFO_SIZE 192 -#endif - -#ifndef CONFIG_USBDEV_EP1_TXFIFO_SIZE -# define CONFIG_USBDEV_EP1_TXFIFO_SIZE 192 -#endif - -#ifndef CONFIG_USBDEV_EP2_TXFIFO_SIZE -# define CONFIG_USBDEV_EP2_TXFIFO_SIZE 192 -#endif - -#ifndef CONFIG_USBDEV_EP3_TXFIFO_SIZE -# define CONFIG_USBDEV_EP3_TXFIFO_SIZE 192 -#endif - -#if (CONFIG_USBDEV_RXFIFO_SIZE + \ - CONFIG_USBDEV_EP0_TXFIFO_SIZE + CONFIG_USBDEV_EP1_TXFIFO_SIZE + \ - CONFIG_USBDEV_EP2_TXFIFO_SIZE + CONFIG_USBDEV_EP3_TXFIFO_SIZE) > 1280 -# error "FIFO allocations exceed FIFO memory size" -#endif - -/* The actual FIFO addresses that we use must be aligned to 4-byte - * boundaries; - * FIFO sizes must be provided in units of 32-bit words. - */ - -#define STM32_RXFIFO_BYTES ((CONFIG_USBDEV_RXFIFO_SIZE + 3) & ~3) -#define STM32_RXFIFO_WORDS ((CONFIG_USBDEV_RXFIFO_SIZE + 3) >> 2) - -#define STM32_EP0_TXFIFO_BYTES ((CONFIG_USBDEV_EP0_TXFIFO_SIZE + 3) & ~3) -#define STM32_EP0_TXFIFO_WORDS ((CONFIG_USBDEV_EP0_TXFIFO_SIZE + 3) >> 2) - -#if STM32_EP0_TXFIFO_WORDS < 16 || STM32_EP0_TXFIFO_WORDS > 256 -# error "CONFIG_USBDEV_EP0_TXFIFO_SIZE is out of range" -#endif - -#define STM32_EP1_TXFIFO_BYTES ((CONFIG_USBDEV_EP1_TXFIFO_SIZE + 3) & ~3) -#define STM32_EP1_TXFIFO_WORDS ((CONFIG_USBDEV_EP1_TXFIFO_SIZE + 3) >> 2) - -#if STM32_EP1_TXFIFO_WORDS < 16 -# error "CONFIG_USBDEV_EP1_TXFIFO_SIZE is out of range" -#endif - -#define STM32_EP2_TXFIFO_BYTES ((CONFIG_USBDEV_EP2_TXFIFO_SIZE + 3) & ~3) -#define STM32_EP2_TXFIFO_WORDS ((CONFIG_USBDEV_EP2_TXFIFO_SIZE + 3) >> 2) - -#if STM32_EP2_TXFIFO_WORDS < 16 -# error "CONFIG_USBDEV_EP2_TXFIFO_SIZE is out of range" -#endif - -#define STM32_EP3_TXFIFO_BYTES ((CONFIG_USBDEV_EP3_TXFIFO_SIZE + 3) & ~3) -#define STM32_EP3_TXFIFO_WORDS ((CONFIG_USBDEV_EP3_TXFIFO_SIZE + 3) >> 2) - -#if STM32_EP3_TXFIFO_WORDS < 16 -# error "CONFIG_USBDEV_EP3_TXFIFO_SIZE is out of range" -#endif - -#if defined(CONFIG_STM32_STM32F446) || defined(CONFIG_STM32_STM32F469) -# define OTGFS_GINT_RESETS (OTGFS_GINT_USBRST | OTGFS_GINT_RSTDET) -# define OTGFS_GINT_RESERVED (OTGFS_GINT_RES89 | OTGFS_GINT_RES16 | \ - OTGFS_GINTMSK_EPMISM | OTGFS_GINT_RES22) - -# define OTGFS_GINT_RC_W1 (OTGFS_GINT_MMIS | \ - OTGFS_GINT_SOF | \ - OTGFS_GINT_ESUSP | \ - OTGFS_GINT_USBSUSP | \ - OTGFS_GINT_USBRST | \ - OTGFS_GINT_ENUMDNE | \ - OTGFS_GINT_ISOODRP | \ - OTGFS_GINT_EOPF | \ - OTGFS_GINT_IISOIXFR | \ - OTGFS_GINT_IISOOXFR | \ - OTGFS_GINT_RSTDET | \ - OTGFS_GINT_LPMINT | \ - OTGFS_GINT_CIDSCHG | \ - OTGFS_GINT_DISC | \ - OTGFS_GINT_SRQ | \ - OTGFS_GINT_WKUP) -#else -# define OTGFS_GINT_RESETS OTGFS_GINT_USBRST -# define OTGFS_GINT_RESERVED (OTGFS_GINT_RES89 | OTGFS_GINT_RES16 | \ - OTGFS_GINTMSK_EPMISM | OTGFS_GINT_RES2223 | \ - OTGFS_GINT_RES27) - -# define OTGFS_GINT_RC_W1 (OTGFS_GINT_MMIS | \ - OTGFS_GINT_SOF | \ - OTGFS_GINT_ESUSP | \ - OTGFS_GINT_USBSUSP | \ - OTGFS_GINT_USBRST | \ - OTGFS_GINT_ENUMDNE | \ - OTGFS_GINT_ISOODRP | \ - OTGFS_GINT_EOPF | \ - OTGFS_GINT_IISOIXFR | \ - OTGFS_GINT_IISOOXFR | \ - OTGFS_GINT_CIDSCHG | \ - OTGFS_GINT_DISC | \ - OTGFS_GINT_SRQ | \ - OTGFS_GINT_WKUP) -#endif - -/* Debug ********************************************************************/ - -/* Trace error codes */ - -#define STM32_TRACEERR_ALLOCFAIL 0x01 -#define STM32_TRACEERR_BADCLEARFEATURE 0x02 -#define STM32_TRACEERR_BADDEVGETSTATUS 0x03 -#define STM32_TRACEERR_BADEPNO 0x04 -#define STM32_TRACEERR_BADEPGETSTATUS 0x05 -#define STM32_TRACEERR_BADGETCONFIG 0x06 -#define STM32_TRACEERR_BADGETSETDESC 0x07 -#define STM32_TRACEERR_BADGETSTATUS 0x08 -#define STM32_TRACEERR_BADSETADDRESS 0x09 -#define STM32_TRACEERR_BADSETCONFIG 0x0a -#define STM32_TRACEERR_BADSETFEATURE 0x0b -#define STM32_TRACEERR_BADTESTMODE 0x0c -#define STM32_TRACEERR_BINDFAILED 0x0d -#define STM32_TRACEERR_DISPATCHSTALL 0x0e -#define STM32_TRACEERR_DRIVER 0x0f -#define STM32_TRACEERR_DRIVERREGISTERED 0x10 -#define STM32_TRACEERR_EP0NOSETUP 0x11 -#define STM32_TRACEERR_EP0SETUPSTALLED 0x12 -#define STM32_TRACEERR_EPINNULLPACKET 0x13 -#define STM32_TRACEERR_EPINUNEXPECTED 0x14 -#define STM32_TRACEERR_EPOUTNULLPACKET 0x15 -#define STM32_TRACEERR_EPOUTUNEXPECTED 0x16 -#define STM32_TRACEERR_INVALIDCTRLREQ 0x17 -#define STM32_TRACEERR_INVALIDPARMS 0x18 -#define STM32_TRACEERR_IRQREGISTRATION 0x19 -#define STM32_TRACEERR_NOEP 0x1a -#define STM32_TRACEERR_NOTCONFIGURED 0x1b -#define STM32_TRACEERR_EPOUTQEMPTY 0x1c -#define STM32_TRACEERR_EPINREQEMPTY 0x1d -#define STM32_TRACEERR_NOOUTSETUP 0x1e -#define STM32_TRACEERR_POLLTIMEOUT 0x1f - -/* Trace interrupt codes */ - -#define STM32_TRACEINTID_USB 1 /* USB Interrupt entry/exit */ -#define STM32_TRACEINTID_INTPENDING 2 /* On each pass through the loop */ - -#define STM32_TRACEINTID_EPOUT (10 + 0) /* First level interrupt decode */ -#define STM32_TRACEINTID_EPIN (10 + 1) -#define STM32_TRACEINTID_MISMATCH (10 + 2) -#define STM32_TRACEINTID_WAKEUP (10 + 3) -#define STM32_TRACEINTID_SUSPEND (10 + 4) -#define STM32_TRACEINTID_SOF (10 + 5) -#define STM32_TRACEINTID_RXFIFO (10 + 6) -#define STM32_TRACEINTID_DEVRESET (10 + 7) -#define STM32_TRACEINTID_ENUMDNE (10 + 8) -#define STM32_TRACEINTID_IISOIXFR (10 + 9) -#define STM32_TRACEINTID_IISOOXFR (10 + 10) -#define STM32_TRACEINTID_SRQ (10 + 11) -#define STM32_TRACEINTID_OTG (10 + 12) - -#define STM32_TRACEINTID_EPOUT_XFRC (40 + 0) /* EPOUT second level decode */ -#define STM32_TRACEINTID_EPOUT_EPDISD (40 + 1) -#define STM32_TRACEINTID_EPOUT_SETUP (40 + 2) -#define STM32_TRACEINTID_DISPATCH (40 + 3) - -#define STM32_TRACEINTID_GETSTATUS (50 + 0) /* EPOUT third level decode */ -#define STM32_TRACEINTID_EPGETSTATUS (50 + 1) -#define STM32_TRACEINTID_DEVGETSTATUS (50 + 2) -#define STM32_TRACEINTID_IFGETSTATUS (50 + 3) -#define STM32_TRACEINTID_CLEARFEATURE (50 + 4) -#define STM32_TRACEINTID_SETFEATURE (50 + 5) -#define STM32_TRACEINTID_SETADDRESS (50 + 6) -#define STM32_TRACEINTID_GETSETDESC (50 + 7) -#define STM32_TRACEINTID_GETCONFIG (50 + 8) -#define STM32_TRACEINTID_SETCONFIG (50 + 9) -#define STM32_TRACEINTID_GETSETIF (50 + 10) -#define STM32_TRACEINTID_SYNCHFRAME (50 + 11) - -#define STM32_TRACEINTID_EPIN_XFRC (70 + 0) /* EPIN second level decode */ -#define STM32_TRACEINTID_EPIN_TOC (70 + 1) -#define STM32_TRACEINTID_EPIN_ITTXFE (70 + 2) -#define STM32_TRACEINTID_EPIN_EPDISD (70 + 3) -#define STM32_TRACEINTID_EPIN_TXFE (70 + 4) - -#define STM32_TRACEINTID_EPIN_EMPWAIT (80 + 0) /* EPIN second level decode */ - -#define STM32_TRACEINTID_OUTNAK (90 + 0) /* RXFLVL second level decode */ -#define STM32_TRACEINTID_OUTRECVD (90 + 1) -#define STM32_TRACEINTID_OUTDONE (90 + 2) -#define STM32_TRACEINTID_SETUPDONE (90 + 3) -#define STM32_TRACEINTID_SETUPRECVD (90 + 4) - -/* Endpoints ****************************************************************/ - -/* Odd physical endpoint numbers are IN; even are OUT */ - -#define STM32_EPPHYIN2LOG(epphy) ((uint8_t)(epphy)|USB_DIR_IN) -#define STM32_EPPHYOUT2LOG(epphy) ((uint8_t)(epphy)|USB_DIR_OUT) - -/* Endpoint 0 */ - -#define EP0 (0) - -/* The set of all endpoints available to the class implementation (1-3) */ - -#define STM32_EP_AVAILABLE (0x0e) /* All available endpoints */ - -/* Maximum packet sizes for full speed endpoints */ - -#define STM32_MAXPACKET (64) /* Max packet size (1-64) */ - -/* Delays *******************************************************************/ - -#define STM32_READY_DELAY 200000 -#define STM32_FLUSH_DELAY 200000 - -/* Request queue operations *************************************************/ - -#define stm32_rqempty(ep) ((ep)->head == NULL) -#define stm32_rqpeek(ep) ((ep)->head) - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/* Overall device state */ - -enum stm32_devstate_e -{ - DEVSTATE_DEFAULT = 0, /* Power-up, unconfigured state. This state simply - * means that the device is not yet been given an - * address. - * SET: At initialization, uninitialization, - * reset, and whenever the device address - * is set to zero - * TESTED: Never - */ - DEVSTATE_ADDRESSED, /* Device address has been assigned, not no - * configuration has yet been selected. - * SET: When either a non-zero device address - * is first assigned or when the device - * is unconfigured (with configuration == 0) - * TESTED: never - */ - DEVSTATE_CONFIGURED, /* Address assigned and configured: - * SET: When the device has been addressed and - * an non-zero configuration has been selected. - * TESTED: In many places to assure that the USB device - * has been properly configured by the host. - */ -}; - -/* Endpoint 0 states */ - -enum stm32_ep0state_e -{ - EP0STATE_IDLE = 0, /* Idle State, leave on receiving a SETUP packet or - * epsubmit: - * SET: In stm32_epin() and stm32_epout() when - * we revert from request processing to - * SETUP processing. - * TESTED: Never - */ - EP0STATE_SETUP_OUT, /* OUT SETUP packet received. Waiting for the DATA - * OUT phase of SETUP Packet to complete before - * processing a SETUP command (without a USB request): - * SET: Set in stm32_rxinterrupt() when SETUP OUT - * packet is received. - * TESTED: In stm32_ep0out_receive() - */ - EP0STATE_SETUP_READY, /* IN SETUP packet received -OR- OUT SETUP packet and - * accompanying data have been received. Processing - * of SETUP command will happen soon. - * SET: (1) stm32_ep0out_receive() when the OUT - * SETUP data phase completes, or (2) - * stm32_rxinterrupt() when an IN SETUP is - * packet received. - * TESTED: Tested in stm32_epout_interrupt() when - * SETUP phase is done to see if the SETUP - * command is ready to be processed. Also - * tested in stm32_ep0out_setup() just to - * double-check that we have a SETUP request - * and any accompanying data. - */ - EP0STATE_SETUP_PROCESS, /* SETUP Packet is being processed by stm32_ep0out_setup(): - * SET: When SETUP packet received in EP0 OUT - * TESTED: Never - */ - EP0STATE_SETUPRESPONSE, /* Short SETUP response write (without a USB request): - * SET: When SETUP response is sent by - * stm32_ep0in_setupresponse() - * TESTED: Never - */ - EP0STATE_DATA_IN, /* Waiting for data out stage (with a USB request): - * SET: In stm32_epin_request() when a write - * request is processed on EP0. - * TESTED: In stm32_epin() to see if we should - * revert to SETUP processing. - */ - EP0STATE_DATA_OUT /* Waiting for data in phase to complete ( with a - * USB request) - * SET: In stm32_epout_request() when a read - * request is processed on EP0. - * TESTED: In stm32_epout() to see if we should - * revert to SETUP processing - */ -}; - -/* Parsed control request */ - -struct stm32_ctrlreq_s -{ - uint8_t type; - uint8_t req; - uint16_t value; - uint16_t index; - uint16_t len; -}; - -/* A container for a request so that the request may be retained in a list */ - -struct stm32_req_s -{ - struct usbdev_req_s req; /* Standard USB request */ - struct stm32_req_s *flink; /* Supports a singly linked list */ -}; - -/* This is the internal representation of an endpoint */ - -struct stm32_ep_s -{ - /* Common endpoint fields. This must be the first thing defined in the - * structure so that it is possible to simply cast from struct usbdev_ep_s - * to struct stm32_ep_s. - */ - - struct usbdev_ep_s ep; /* Standard endpoint structure */ - - /* STM32-specific fields */ - - struct stm32_usbdev_s *dev; /* Reference to private driver data */ - struct stm32_req_s *head; /* Request list for this endpoint */ - struct stm32_req_s *tail; - uint8_t epphy; /* Physical EP address */ - uint8_t eptype:2; /* Endpoint type */ - uint8_t active:1; /* 1: A request is being processed */ - uint8_t stalled:1; /* 1: Endpoint is stalled */ - uint8_t isin:1; /* 1: IN Endpoint */ - uint8_t odd:1; /* 1: Odd frame */ - uint8_t zlp:1; /* 1: Transmit a zero-length-packet (IN EPs only) */ -}; - -/* This structure retains the state of the USB device controller */ - -struct stm32_usbdev_s -{ - /* Common device fields. This must be the first thing defined in the - * structure so that it is possible to simply cast from struct usbdev_s - * to struct stm32_usbdev_s. - */ - - struct usbdev_s usbdev; - - /* The bound device class driver */ - - struct usbdevclass_driver_s *driver; - - /* STM32-specific fields */ - - uint8_t stalled:1; /* 1: Protocol stalled */ - uint8_t selfpowered:1; /* 1: Device is self powered */ - uint8_t addressed:1; /* 1: Peripheral address has been set */ - uint8_t configured:1; /* 1: Class driver has been configured */ - uint8_t wakeup:1; /* 1: Device remote wake-up */ - uint8_t dotest:1; /* 1: Test mode selected */ - - uint8_t devstate:4; /* See enum stm32_devstate_e */ - uint8_t ep0state:4; /* See enum stm32_ep0state_e */ - uint8_t testmode:4; /* Selected test mode */ - uint8_t epavail[2]; /* Bitset of available OUT/IN endpoints */ - - /* E0 SETUP data buffering. - * - * ctrlreq: - * The 8-byte SETUP request is received on the EP0 OUT endpoint and is - * saved. - * - * ep0data - * For OUT SETUP requests, the SETUP data phase must also complete before - * the SETUP command can be processed. The pack receipt logic will save - * the accompanying EP0 OUT data in ep0data[] before the SETUP command is - * processed. The data length is specified in the SETUP packet payload, - * and can consist of multiple DATA packets. - * - * For IN SETUP requests, the DATA phase will occur AFTER the SETUP - * control request is processed. In that case, ep0data[] may be used as - * the response buffer. - * - * ep0datlen - * Length of data received part of OUT SETUP request. During transfer - * it is the total number of bytes received, which can be more than - * CONFIG_USBDEV_SETUP_MAXDATASIZE. The value is clamped to valid length - * of data in ep0data[] before SETUP OUT handler is called. Bytes that - * exceed the maximum length are discarded, but must be read out of the - * USB peripheral FIFO. - */ - - struct usb_ctrlreq_s ctrlreq; - uint8_t ep0data[CONFIG_USBDEV_SETUP_MAXDATASIZE]; - uint16_t ep0datlen; - - /* The endpoint lists */ - - struct stm32_ep_s epin[STM32_NENDPOINTS]; - struct stm32_ep_s epout[STM32_NENDPOINTS]; -}; - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -/* Register operations ******************************************************/ - -#ifdef CONFIG_STM32_USBDEV_REGDEBUG -static uint32_t stm32_getreg(uint32_t addr); -static void stm32_putreg(uint32_t val, uint32_t addr); -#else -# define stm32_getreg(addr) getreg32(addr) -# define stm32_putreg(val,addr) putreg32(val,addr) -#endif - -/* Request queue operations *************************************************/ - -static struct stm32_req_s *stm32_req_remfirst( - struct stm32_ep_s *privep); -static bool stm32_req_addlast(struct stm32_ep_s *privep, - struct stm32_req_s *req); - -/* Low level data transfers and request operations **************************/ - -/* Special endpoint 0 data transfer logic */ - -static void stm32_ep0in_setupresponse(struct stm32_usbdev_s *priv, - uint8_t *data, uint32_t nbytes); -static inline void stm32_ep0in_transmitzlp(struct stm32_usbdev_s *priv); -static void stm32_ep0in_activate(void); - -static void stm32_ep0out_ctrlsetup(struct stm32_usbdev_s *priv); - -/* IN request and TxFIFO handling */ - -static void stm32_txfifo_write(struct stm32_ep_s *privep, - uint8_t *buf, int nbytes); -static void stm32_epin_transfer(struct stm32_ep_s *privep, - uint8_t *buf, int nbytes); -static void stm32_epin_request(struct stm32_usbdev_s *priv, - struct stm32_ep_s *privep); - -/* OUT request and RxFIFO handling */ - -static void stm32_rxfifo_read(struct stm32_ep_s *privep, - uint8_t *dest, uint16_t len); -static void stm32_rxfifo_discard(struct stm32_ep_s *privep, - int len); -static void stm32_epout_complete(struct stm32_usbdev_s *priv, - struct stm32_ep_s *privep); -static inline void stm32_ep0out_receive(struct stm32_ep_s *privep, - int bcnt); -static inline void stm32_epout_receive(struct stm32_ep_s *privep, - int bcnt); -static void stm32_epout_request(struct stm32_usbdev_s *priv, - struct stm32_ep_s *privep); - -/* General request handling */ - -static void stm32_ep_flush(struct stm32_ep_s *privep); -static void stm32_req_complete(struct stm32_ep_s *privep, - int16_t result); -static void stm32_req_cancel(struct stm32_ep_s *privep, - int16_t status); - -/* Interrupt handling *******************************************************/ - -static struct stm32_ep_s *stm32_ep_findbyaddr( - struct stm32_usbdev_s *priv, - uint16_t eplog); -static int stm32_req_dispatch(struct stm32_usbdev_s *priv, - const struct usb_ctrlreq_s *ctrl); -static void stm32_usbreset(struct stm32_usbdev_s *priv); - -/* Second level OUT endpoint interrupt processing */ - -static inline void stm32_ep0out_testmode(struct stm32_usbdev_s *priv, - uint16_t index); -static inline void stm32_ep0out_stdrequest(struct stm32_usbdev_s *priv, - struct stm32_ctrlreq_s *ctrlreq); -static inline void stm32_ep0out_setup(struct stm32_usbdev_s *priv); -static inline void stm32_epout(struct stm32_usbdev_s *priv, - uint8_t epno); -static inline void stm32_epout_interrupt(struct stm32_usbdev_s *priv); - -/* Second level IN endpoint interrupt processing */ - -static inline void stm32_epin_runtestmode(struct stm32_usbdev_s *priv); -static inline void stm32_epin(struct stm32_usbdev_s *priv, uint8_t epno); -static inline void stm32_epin_txfifoempty(struct stm32_usbdev_s *priv, - int epno); -static inline void stm32_epin_interrupt(struct stm32_usbdev_s *priv); - -/* Other second level interrupt processing */ - -static inline void stm32_resumeinterrupt(struct stm32_usbdev_s *priv); -static inline void stm32_suspendinterrupt(struct stm32_usbdev_s *priv); -static inline void stm32_rxinterrupt(struct stm32_usbdev_s *priv); -static inline void stm32_enuminterrupt(struct stm32_usbdev_s *priv); -#ifdef CONFIG_USBDEV_ISOCHRONOUS -static inline void stm32_isocininterrupt(struct stm32_usbdev_s *priv); -static inline void stm32_isocoutinterrupt(struct stm32_usbdev_s *priv); -#endif -#ifdef CONFIG_USBDEV_VBUSSENSING -static inline void stm32_sessioninterrupt(struct stm32_usbdev_s *priv); -static inline void stm32_otginterrupt(struct stm32_usbdev_s *priv); -#endif - -/* First level interrupt processing */ - -static int stm32_usbinterrupt(int irq, void *context, - void *arg); - -/* Endpoint operations ******************************************************/ - -/* Global OUT NAK controls */ - -static void stm32_enablegonak(struct stm32_ep_s *privep); -static void stm32_disablegonak(struct stm32_ep_s *privep); - -/* Endpoint configuration */ - -static int stm32_epout_configure(struct stm32_ep_s *privep, - uint8_t eptype, uint16_t maxpacket); -static int stm32_epin_configure(struct stm32_ep_s *privep, - uint8_t eptype, uint16_t maxpacket); -static int stm32_ep_configure(struct usbdev_ep_s *ep, - const struct usb_epdesc_s *desc, bool last); -static void stm32_ep0_configure(struct stm32_usbdev_s *priv); - -/* Endpoint disable */ - -static void stm32_epout_disable(struct stm32_ep_s *privep); -static void stm32_epin_disable(struct stm32_ep_s *privep); -static int stm32_ep_disable(struct usbdev_ep_s *ep); - -/* Endpoint request management */ - -static struct usbdev_req_s *stm32_ep_allocreq( - struct usbdev_ep_s *ep); -static void stm32_ep_freereq(struct usbdev_ep_s *ep, - struct usbdev_req_s *); - -/* Endpoint buffer management */ - -#ifdef CONFIG_USBDEV_DMA -static void *stm32_ep_allocbuffer(struct usbdev_ep_s *ep, - uint16_t bytes); -static void stm32_ep_freebuffer(struct usbdev_ep_s *ep, - void *buf); -#endif - -/* Endpoint request submission */ - -static int stm32_ep_submit(struct usbdev_ep_s *ep, - struct usbdev_req_s *req); - -/* Endpoint request cancellation */ - -static int stm32_ep_cancel(struct usbdev_ep_s *ep, - struct usbdev_req_s *req); - -/* Stall handling */ - -static int stm32_epout_setstall(struct stm32_ep_s *privep); -static int stm32_epin_setstall(struct stm32_ep_s *privep); -static int stm32_ep_setstall(struct stm32_ep_s *privep); -static int stm32_ep_clrstall(struct stm32_ep_s *privep); -static int stm32_ep_stall(struct usbdev_ep_s *ep, bool resume); -static void stm32_ep0_stall(struct stm32_usbdev_s *priv); - -/* Endpoint allocation */ - -static struct usbdev_ep_s *stm32_ep_alloc(struct usbdev_s *dev, - uint8_t epno, bool in, uint8_t eptype); -static void stm32_ep_free(struct usbdev_s *dev, - struct usbdev_ep_s *ep); - -/* USB device controller operations *****************************************/ - -static int stm32_getframe(struct usbdev_s *dev); -static int stm32_wakeup(struct usbdev_s *dev); -static int stm32_selfpowered(struct usbdev_s *dev, bool selfpowered); -static int stm32_pullup(struct usbdev_s *dev, bool enable); -static void stm32_setaddress(struct stm32_usbdev_s *priv, - uint16_t address); -static int stm32_txfifo_flush(uint32_t txfnum); -static int stm32_rxfifo_flush(void); - -/* Initialization ***********************************************************/ - -static void stm32_swinitialize(struct stm32_usbdev_s *priv); -static void stm32_hwinitialize(struct stm32_usbdev_s *priv); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* Since there is only a single USB interface, all status information can be - * be simply retained in a single global instance. - */ - -static struct stm32_usbdev_s g_otgfsdev; - -static const struct usbdev_epops_s g_epops = -{ - .configure = stm32_ep_configure, - .disable = stm32_ep_disable, - .allocreq = stm32_ep_allocreq, - .freereq = stm32_ep_freereq, -#ifdef CONFIG_USBDEV_DMA - .allocbuffer = stm32_ep_allocbuffer, - .freebuffer = stm32_ep_freebuffer, -#endif - .submit = stm32_ep_submit, - .cancel = stm32_ep_cancel, - .stall = stm32_ep_stall, -}; - -static const struct usbdev_ops_s g_devops = -{ - .allocep = stm32_ep_alloc, - .freeep = stm32_ep_free, - .getframe = stm32_getframe, - .wakeup = stm32_wakeup, - .selfpowered = stm32_selfpowered, - .pullup = stm32_pullup, -}; - -/* Device error strings that may be enabled for more descriptive USB trace - * output. - */ - -#ifdef CONFIG_USBDEV_TRACE_STRINGS -const struct trace_msg_t g_usb_trace_strings_deverror[] = -{ - TRACE_STR(STM32_TRACEERR_ALLOCFAIL), - TRACE_STR(STM32_TRACEERR_BADCLEARFEATURE), - TRACE_STR(STM32_TRACEERR_BADDEVGETSTATUS), - TRACE_STR(STM32_TRACEERR_BADEPNO), - TRACE_STR(STM32_TRACEERR_BADEPGETSTATUS), - TRACE_STR(STM32_TRACEERR_BADGETCONFIG), - TRACE_STR(STM32_TRACEERR_BADGETSETDESC), - TRACE_STR(STM32_TRACEERR_BADGETSTATUS), - TRACE_STR(STM32_TRACEERR_BADSETADDRESS), - TRACE_STR(STM32_TRACEERR_BADSETCONFIG), - TRACE_STR(STM32_TRACEERR_BADSETFEATURE), - TRACE_STR(STM32_TRACEERR_BADTESTMODE), - TRACE_STR(STM32_TRACEERR_BINDFAILED), - TRACE_STR(STM32_TRACEERR_DISPATCHSTALL), - TRACE_STR(STM32_TRACEERR_DRIVER), - TRACE_STR(STM32_TRACEERR_DRIVERREGISTERED), - TRACE_STR(STM32_TRACEERR_EP0NOSETUP), - TRACE_STR(STM32_TRACEERR_EP0SETUPSTALLED), - TRACE_STR(STM32_TRACEERR_EPINNULLPACKET), - TRACE_STR(STM32_TRACEERR_EPINUNEXPECTED), - TRACE_STR(STM32_TRACEERR_EPOUTNULLPACKET), - TRACE_STR(STM32_TRACEERR_EPOUTUNEXPECTED), - TRACE_STR(STM32_TRACEERR_INVALIDCTRLREQ), - TRACE_STR(STM32_TRACEERR_INVALIDPARMS), - TRACE_STR(STM32_TRACEERR_IRQREGISTRATION), - TRACE_STR(STM32_TRACEERR_NOEP), - TRACE_STR(STM32_TRACEERR_NOTCONFIGURED), - TRACE_STR(STM32_TRACEERR_EPOUTQEMPTY), - TRACE_STR(STM32_TRACEERR_EPINREQEMPTY), - TRACE_STR(STM32_TRACEERR_NOOUTSETUP), - TRACE_STR(STM32_TRACEERR_POLLTIMEOUT), - TRACE_STR_END -}; -#endif - -/* Interrupt event strings that may be enabled for more descriptive USB trace - * output. - */ - -#ifdef CONFIG_USBDEV_TRACE_STRINGS -const struct trace_msg_t g_usb_trace_strings_intdecode[] = -{ - TRACE_STR(STM32_TRACEINTID_USB), - TRACE_STR(STM32_TRACEINTID_INTPENDING), - TRACE_STR(STM32_TRACEINTID_EPOUT), - TRACE_STR(STM32_TRACEINTID_EPIN), - TRACE_STR(STM32_TRACEINTID_MISMATCH), - TRACE_STR(STM32_TRACEINTID_WAKEUP), - TRACE_STR(STM32_TRACEINTID_SUSPEND), - TRACE_STR(STM32_TRACEINTID_SOF), - TRACE_STR(STM32_TRACEINTID_RXFIFO), - TRACE_STR(STM32_TRACEINTID_DEVRESET), - TRACE_STR(STM32_TRACEINTID_ENUMDNE), - TRACE_STR(STM32_TRACEINTID_IISOIXFR), - TRACE_STR(STM32_TRACEINTID_IISOOXFR), - TRACE_STR(STM32_TRACEINTID_SRQ), - TRACE_STR(STM32_TRACEINTID_OTG), - TRACE_STR(STM32_TRACEINTID_EPOUT_XFRC), - TRACE_STR(STM32_TRACEINTID_EPOUT_EPDISD), - TRACE_STR(STM32_TRACEINTID_EPOUT_SETUP), - TRACE_STR(STM32_TRACEINTID_DISPATCH), - TRACE_STR(STM32_TRACEINTID_GETSTATUS), - TRACE_STR(STM32_TRACEINTID_EPGETSTATUS), - TRACE_STR(STM32_TRACEINTID_DEVGETSTATUS), - TRACE_STR(STM32_TRACEINTID_IFGETSTATUS), - TRACE_STR(STM32_TRACEINTID_CLEARFEATURE), - TRACE_STR(STM32_TRACEINTID_SETFEATURE), - TRACE_STR(STM32_TRACEINTID_SETADDRESS), - TRACE_STR(STM32_TRACEINTID_GETSETDESC), - TRACE_STR(STM32_TRACEINTID_GETCONFIG), - TRACE_STR(STM32_TRACEINTID_SETCONFIG), - TRACE_STR(STM32_TRACEINTID_GETSETIF), - TRACE_STR(STM32_TRACEINTID_SYNCHFRAME), - TRACE_STR(STM32_TRACEINTID_EPIN_XFRC), - TRACE_STR(STM32_TRACEINTID_EPIN_TOC), - TRACE_STR(STM32_TRACEINTID_EPIN_ITTXFE), - TRACE_STR(STM32_TRACEINTID_EPIN_EPDISD), - TRACE_STR(STM32_TRACEINTID_EPIN_TXFE), - TRACE_STR(STM32_TRACEINTID_EPIN_EMPWAIT), - TRACE_STR(STM32_TRACEINTID_OUTNAK), - TRACE_STR(STM32_TRACEINTID_OUTRECVD), - TRACE_STR(STM32_TRACEINTID_OUTDONE), - TRACE_STR(STM32_TRACEINTID_SETUPDONE), - TRACE_STR(STM32_TRACEINTID_SETUPRECVD), - TRACE_STR_END -}; -#endif - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_getreg - * - * Description: - * Get the contents of an STM32 register - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_USBDEV_REGDEBUG -static uint32_t stm32_getreg(uint32_t addr) -{ - static uint32_t prevaddr = 0; - static uint32_t preval = 0; - static uint32_t count = 0; - - /* Read the value from the register */ - - uint32_t val = getreg32(addr); - - /* Is this the same value that we read from the same register last time? - * Are we polling the register? If so, suppress some of the output. - */ - - if (addr == prevaddr && val == preval) - { - if (count == 0xffffffff || ++count > 3) - { - if (count == 4) - { - uinfo("...\n"); - } - - return val; - } - } - - /* No this is a new address or value */ - - else - { - /* Did we print "..." for the previous value? */ - - if (count > 3) - { - /* Yes.. then show how many times the value repeated */ - - uinfo("[repeats %d more times]\n", count - 3); - } - - /* Save the new address, value, and count */ - - prevaddr = addr; - preval = val; - count = 1; - } - - /* Show the register value read */ - - uinfo("%08" PRIx32 "->%08" PRIx32 "\n", addr, val); - return val; -} -#endif - -/**************************************************************************** - * Name: stm32_putreg - * - * Description: - * Set the contents of an STM32 register to a value - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_USBDEV_REGDEBUG -static void stm32_putreg(uint32_t val, uint32_t addr) -{ - /* Show the register value being written */ - - uinfo("%08" PRIx32 "<-%08" PRIx32 "\n", addr, val); - - /* Write the value */ - - putreg32(val, addr); -} -#endif - -/**************************************************************************** - * Name: stm32_req_remfirst - * - * Description: - * Remove a request from the head of an endpoint request queue - * - ****************************************************************************/ - -static struct stm32_req_s *stm32_req_remfirst( - struct stm32_ep_s *privep) -{ - struct stm32_req_s *ret = privep->head; - - if (ret) - { - privep->head = ret->flink; - if (!privep->head) - { - privep->tail = NULL; - } - - ret->flink = NULL; - } - - return ret; -} - -/**************************************************************************** - * Name: stm32_req_addlast - * - * Description: - * Add a request to the end of an endpoint request queue - * - ****************************************************************************/ - -static bool stm32_req_addlast(struct stm32_ep_s *privep, - struct stm32_req_s *req) -{ - bool is_empty = !privep->head; - - req->flink = NULL; - if (is_empty) - { - privep->head = req; - privep->tail = req; - } - else - { - privep->tail->flink = req; - privep->tail = req; - } - - return is_empty; -} - -/**************************************************************************** - * Name: stm32_ep0in_setupresponse - * - * Description: - * Schedule a short transfer on Endpoint 0 (IN or OUT) - * - ****************************************************************************/ - -static void stm32_ep0in_setupresponse(struct stm32_usbdev_s *priv, - uint8_t *buf, uint32_t nbytes) -{ - stm32_epin_transfer(&priv->epin[EP0], buf, nbytes); - priv->ep0state = EP0STATE_SETUPRESPONSE; - stm32_ep0out_ctrlsetup(priv); -} - -/**************************************************************************** - * Name: stm32_ep0in_transmitzlp - * - * Description: - * Send a zero length packet (ZLP) on endpoint 0 IN - * - ****************************************************************************/ - -static inline void stm32_ep0in_transmitzlp(struct stm32_usbdev_s *priv) -{ - stm32_ep0in_setupresponse(priv, NULL, 0); -} - -/**************************************************************************** - * Name: stm32_ep0in_activate - * - * Description: - * Activate the endpoint 0 IN endpoint. - * - ****************************************************************************/ - -static void stm32_ep0in_activate(void) -{ - uint32_t regval; - - /* Set the max packet size of the IN EP. */ - - regval = stm32_getreg(STM32_OTGFS_DIEPCTL0); - regval &= ~OTGFS_DIEPCTL0_MPSIZ_MASK; - -#if CONFIG_USBDEV_EP0_MAXSIZE == 8 - regval |= OTGFS_DIEPCTL0_MPSIZ_8; -#elif CONFIG_USBDEV_EP0_MAXSIZE == 16 - regval |= OTGFS_DIEPCTL0_MPSIZ_16; -#elif CONFIG_USBDEV_EP0_MAXSIZE == 32 - regval |= OTGFS_DIEPCTL0_MPSIZ_32; -#elif CONFIG_USBDEV_EP0_MAXSIZE == 64 - regval |= OTGFS_DIEPCTL0_MPSIZ_64; -#else -# error "Unsupported value of CONFIG_USBDEV_EP0_MAXSIZE" -#endif - - stm32_putreg(regval, STM32_OTGFS_DIEPCTL0); - - /* Clear global IN NAK */ - - regval = stm32_getreg(STM32_OTGFS_DCTL); - regval |= OTGFS_DCTL_CGINAK; - stm32_putreg(regval, STM32_OTGFS_DCTL); -} - -/**************************************************************************** - * Name: stm32_ep0out_ctrlsetup - * - * Description: - * Setup to receive a SETUP packet. - * - ****************************************************************************/ - -static void stm32_ep0out_ctrlsetup(struct stm32_usbdev_s *priv) -{ - uint32_t regval; - - /* Setup the hardware to perform the SETUP transfer */ - - regval = (USB_SIZEOF_CTRLREQ * 3 << OTGFS_DOEPTSIZ0_XFRSIZ_SHIFT) | - (OTGFS_DOEPTSIZ0_PKTCNT) | - (3 << OTGFS_DOEPTSIZ0_STUPCNT_SHIFT); - stm32_putreg(regval, STM32_OTGFS_DOEPTSIZ0); - - /* Then clear NAKing and enable the transfer */ - - regval = stm32_getreg(STM32_OTGFS_DOEPCTL0); - regval |= (OTGFS_DOEPCTL0_CNAK | OTGFS_DOEPCTL0_EPENA); - stm32_putreg(regval, STM32_OTGFS_DOEPCTL0); -} - -/**************************************************************************** - * Name: stm32_txfifo_write - * - * Description: - * Send data to the endpoint's TxFIFO. - * - ****************************************************************************/ - -static void stm32_txfifo_write(struct stm32_ep_s *privep, - uint8_t *buf, int nbytes) -{ - uint32_t regaddr; - uint32_t regval; - int nwords; - int i; - - /* Convert the number of bytes to words */ - - nwords = (nbytes + 3) >> 2; - - /* Get the TxFIFO for this endpoint (same as the endpoint number) */ - - regaddr = STM32_OTGFS_DFIFO_DEP(privep->epphy); - - /* Then transfer each word to the TxFIFO */ - - for (i = 0; i < nwords; i++) - { - /* Read four bytes from the source buffer (to avoid unaligned accesses) - * and pack these into one 32-bit word (little endian). - */ - - regval = (uint32_t)*buf++; - regval |= ((uint32_t)*buf++) << 8; - regval |= ((uint32_t)*buf++) << 16; - regval |= ((uint32_t)*buf++) << 24; - - /* Then write the packet data to the TxFIFO */ - - stm32_putreg(regval, regaddr); - } -} - -/**************************************************************************** - * Name: stm32_epin_transfer - * - * Description: - * Start the Tx data transfer - * - ****************************************************************************/ - -static void stm32_epin_transfer(struct stm32_ep_s *privep, - uint8_t *buf, int nbytes) -{ - uint32_t pktcnt; - uint32_t regval; - - /* Read the DIEPSIZx register */ - - regval = stm32_getreg(STM32_OTGFS_DIEPTSIZ(privep->epphy)); - - /* Clear the XFRSIZ, PKTCNT, and MCNT field of the DIEPSIZx register */ - - regval &= ~(OTGFS_DIEPTSIZ_XFRSIZ_MASK | OTGFS_DIEPTSIZ_PKTCNT_MASK | - OTGFS_DIEPTSIZ_MCNT_MASK); - - /* Are we sending a zero length packet (ZLP) */ - - if (nbytes == 0) - { - /* Yes.. leave the transfer size at zero and set the packet count to - * 1 - */ - - pktcnt = 1; - } - else - { - /* No.. Program the transfer size and packet count . First calculate: - * - * xfrsize = The total number of bytes to be sent. - * pktcnt = the number of packets (of maxpacket bytes) required to - * perform the transfer. - */ - - pktcnt = ((uint32_t)nbytes + (privep->ep.maxpacket - 1)) / - privep->ep.maxpacket; - } - - /* Set the XFRSIZ and PKTCNT */ - - regval |= (pktcnt << OTGFS_DIEPTSIZ_PKTCNT_SHIFT); - regval |= ((uint32_t)nbytes << OTGFS_DIEPTSIZ_XFRSIZ_SHIFT); - - /* If this is an isochronous endpoint, then set the multi-count field to - * the PKTCNT as well. - */ - - if (privep->eptype == USB_EP_ATTR_XFER_ISOC) - { - regval |= (pktcnt << OTGFS_DIEPTSIZ_MCNT_SHIFT); - } - - /* Save DIEPSIZx register value */ - - stm32_putreg(regval, STM32_OTGFS_DIEPTSIZ(privep->epphy)); - - /* Read the DIEPCTLx register */ - - regval = stm32_getreg(STM32_OTGFS_DIEPCTL(privep->epphy)); - - /* If this is an isochronous endpoint, then set the even/odd frame bit - * the DIEPCTLx register. - */ - - if (privep->eptype == USB_EP_ATTR_XFER_ISOC) - { - /* Check bit 0 of the frame number of the received SOF and set the - * even/odd frame to match. - */ - - uint32_t status = stm32_getreg(STM32_OTGFS_DSTS); - if ((status & OTGFS_DSTS_SOFFN0) == OTGFS_DSTS_SOFFN_EVEN) - { - regval |= OTGFS_DIEPCTL_SEVNFRM; - } - else - { - regval |= OTGFS_DIEPCTL_SODDFRM; - } - } - - /* EP enable, IN data in FIFO */ - - regval &= ~OTGFS_DIEPCTL_EPDIS; - regval |= (OTGFS_DIEPCTL_CNAK | OTGFS_DIEPCTL_EPENA); - stm32_putreg(regval, STM32_OTGFS_DIEPCTL(privep->epphy)); - - /* Transfer the data to the TxFIFO. At this point, the caller has already - * assured that there is sufficient space in the TxFIFO to hold the - * transfer we can just blindly continue. - */ - - stm32_txfifo_write(privep, buf, nbytes); -} - -/**************************************************************************** - * Name: stm32_epin_request - * - * Description: - * Begin or continue write request processing. - * - ****************************************************************************/ - -static void stm32_epin_request(struct stm32_usbdev_s *priv, - struct stm32_ep_s *privep) -{ - struct stm32_req_s *privreq; - uint32_t regaddr; - uint32_t regval; - uint8_t *buf; - int nbytes; - int nwords; - int bytesleft; - - /* We get here in one of four possible ways. From three interrupting - * events: - * - * 1. From stm32_epin as part of the transfer complete interrupt processing - * This interrupt indicates that the last transfer has completed. - * 2. As part of the ITTXFE interrupt processing. That interrupt indicates - * that an IN token was received when the associated TxFIFO was empty. - * 3. From stm32_epin_txfifoempty as part of the TXFE interrupt processing. - * The TXFE interrupt is only enabled when the TxFIFO is full and the - * software must wait for space to become available in the TxFIFO. - * - * And this function may be called immediately when the write request is - * queue to start up the next transaction. - * - * 4. From stm32_ep_submit when a new write request is received WHILE the - * endpoint is not active (privep->active == false). - */ - - /* Check the request from the head of the endpoint request queue */ - - privreq = stm32_rqpeek(privep); - if (!privreq) - { - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EPINREQEMPTY), privep->epphy); - - /* There is no TX transfer in progress and no new pending TX - * requests to send. To stop transmitting any data on a particular - * IN endpoint, the application must set the IN NAK bit. To set this - * bit, the following field must be programmed. - */ - - regaddr = STM32_OTGFS_DIEPCTL(privep->epphy); - regval = stm32_getreg(regaddr); - regval |= OTGFS_DIEPCTL_SNAK; - stm32_putreg(regval, regaddr); - - /* The endpoint is no longer active */ - - privep->active = false; - return; - } - - uinfo("EP%d req=%p: len=%zu xfrd=%zu zlp=%d\n", - privep->epphy, privreq, privreq->req.len, - privreq->req.xfrd, privep->zlp); - - /* Check for a special case: If we are just starting a request (xfrd==0) - * and the class driver is trying to send a zero-length packet (len==0). - * Then set the ZLP flag so that the packet will be sent. - */ - - if (privreq->req.len == 0) - { - /* The ZLP flag is set TRUE whenever we want to force the driver to - * send a zero-length-packet on the next pass through the loop (below). - * The flag is cleared whenever a packet is sent in the loop below. - */ - - privep->zlp = true; - } - - /* Add one more packet to the TxFIFO. We will wait for the transfer - * complete event before we add the next packet (or part of a packet - * to the TxFIFO). - * - * The documentation says that we can can multiple packets to the TxFIFO, - * but it seems that we need to get the transfer complete event before - * we can add the next (or maybe I have got something wrong?) - */ - -#if 0 - while (privreq->req.xfrd < privreq->req.len || privep->zlp) -#else - if (privreq->req.xfrd < privreq->req.len || privep->zlp) -#endif - { - /* Get the number of bytes left to be sent in the request */ - - bytesleft = privreq->req.len - privreq->req.xfrd; - nbytes = bytesleft; - - /* Assume no zero-length-packet on the next pass through this loop */ - - privep->zlp = false; - - /* Limit the size of the transfer to one full packet and handle - * zero-length packets (ZLPs). - */ - - if (nbytes > 0) - { - /* Either send the maxpacketsize or all of the remaining data in - * the request. - */ - - if (nbytes >= privep->ep.maxpacket) - { - nbytes = privep->ep.maxpacket; - - /* Handle the case where this packet is exactly the - * maxpacketsize. Do we need to send a zero-length packet - * in this case? - */ - - if (bytesleft == privep->ep.maxpacket && - (privreq->req.flags & USBDEV_REQFLAGS_NULLPKT) != 0) - { - /* The ZLP flag is set TRUE whenever we want to force - * the driver to send a zero-length-packet on the next - * pass through this loop. The flag is cleared (above) - * whenever we are committed to sending any packet and - * set here when we want to force one more pass through - * the loop. - */ - - privep->zlp = true; - } - } - } - - /* Get the transfer size in 32-bit words */ - - nwords = (nbytes + 3) >> 2; - - /* Get the number of 32-bit words available in the TxFIFO. The - * DXTFSTS indicates the amount of free space available in the - * endpoint TxFIFO. Values are in terms of 32-bit words: - * - * 0: Endpoint TxFIFO is full - * 1: 1 word available - * 2: 2 words available - * n: n words available - */ - - regaddr = STM32_OTGFS_DTXFSTS(privep->epphy); - - /* Check for space in the TxFIFO. If space in the TxFIFO is not - * available, then set up an interrupt to resume the transfer when - * the TxFIFO is empty. - */ - - regval = stm32_getreg(regaddr); - if ((int)(regval & OTGFS_DTXFSTS_MASK) < nwords) - { - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPIN_EMPWAIT), - (uint16_t)regval); - - /* There is insufficient space in the TxFIFO. Wait for a TxFIFO - * empty interrupt and try again. - */ - - uint32_t empmsk = stm32_getreg(STM32_OTGFS_DIEPEMPMSK); - empmsk |= OTGFS_DIEPEMPMSK(privep->epphy); - stm32_putreg(empmsk, STM32_OTGFS_DIEPEMPMSK); - -#ifdef CONFIG_DEBUG_FEATURES - /* Check if the configured TXFIFO size is sufficient for a given - * request. If not, raise an assertion here. - */ - - regval = stm32_getreg(STM32_OTGFS_DIEPTXF(privep->epphy)); - regval &= OTGFS_DIEPTXF_INEPTXFD_MASK; - regval >>= OTGFS_DIEPTXF_INEPTXFD_SHIFT; - uerr("EP%" PRId8 " TXLEN=%" PRId32 " nwords=%d\n", - privep->epphy, regval, nwords); - DEBUGASSERT(regval >= nwords); -#endif - - /* Terminate the transfer. We will try again when the TxFIFO empty - * interrupt is received. - */ - - return; - } - - /* Transfer data to the TxFIFO */ - - buf = privreq->req.buf + privreq->req.xfrd; - stm32_epin_transfer(privep, buf, nbytes); - - /* If it was not before, the OUT endpoint is now actively transferring - * data. - */ - - privep->active = true; - - /* EP0 is a special case */ - - if (privep->epphy == EP0) - { - priv->ep0state = EP0STATE_DATA_IN; - } - - /* Update for the next time through the loop */ - - privreq->req.xfrd += nbytes; - } - - /* Note that the ZLP, if any, must be sent as a separate transfer. The - * need for a ZLP is indicated by privep->zlp. If all of the bytes were - * sent (including any final null packet) then we are finished with the - * transfer - */ - - if (privreq->req.xfrd >= privreq->req.len && !privep->zlp) - { - usbtrace(TRACE_COMPLETE(privep->epphy), privreq->req.xfrd); - - /* We are finished with the request (although the transfer has not - * yet completed). - */ - - stm32_req_complete(privep, OK); - } -} - -/**************************************************************************** - * Name: stm32_rxfifo_read - * - * Description: - * Read packet from the RxFIFO into a read request. - * - ****************************************************************************/ - -static void stm32_rxfifo_read(struct stm32_ep_s *privep, - uint8_t *dest, uint16_t len) -{ - uint32_t regaddr; - int i; - - /* Get the address of the RxFIFO. Note: there is only one RxFIFO so - * we might as well use the address associated with EP0. - */ - - regaddr = STM32_OTGFS_DFIFO_DEP(EP0); - - /* Read 32-bits and write 4 x 8-bits at time (to avoid unaligned - * accesses) - */ - - for (i = 0; i < len; i += 4) - { - union - { - uint32_t w; - uint8_t b[4]; - } data; - - /* Read 1 x 32-bits of EP0 packet data */ - - data.w = stm32_getreg(regaddr); - - /* Write 4 x 8-bits of EP0 packet data */ - - *dest++ = data.b[0]; - *dest++ = data.b[1]; - *dest++ = data.b[2]; - *dest++ = data.b[3]; - } -} - -/**************************************************************************** - * Name: stm32_rxfifo_discard - * - * Description: - * Discard packet data from the RxFIFO. - * - ****************************************************************************/ - -static void stm32_rxfifo_discard(struct stm32_ep_s *privep, int len) -{ - if (len > 0) - { - uint32_t regaddr; - int i; - - /* Get the address of the RxFIFO Note: there is only one RxFIFO so - * we might as well use the address associated with EP0. - */ - - regaddr = STM32_OTGFS_DFIFO_DEP(EP0); - - /* Read 32-bits at time */ - - for (i = 0; i < len; i += 4) - { - volatile uint32_t data = stm32_getreg(regaddr); - UNUSED(data); - } - } -} - -/**************************************************************************** - * Name: stm32_epout_complete - * - * Description: - * This function is called when an OUT transfer complete interrupt is - * received. It completes the read request at the head of the endpoint's - * request queue. - * - ****************************************************************************/ - -static void stm32_epout_complete(struct stm32_usbdev_s *priv, - struct stm32_ep_s *privep) -{ - struct stm32_req_s *privreq; - - /* Since a transfer just completed, there must be a read request at the - * head of the endpoint request queue. - */ - - privreq = stm32_rqpeek(privep); - DEBUGASSERT(privreq); - - if (!privreq) - { - /* An OUT transfer completed, but no packet to receive the data. This - * should not happen. - */ - - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EPOUTQEMPTY), privep->epphy); - privep->active = false; - return; - } - - uinfo("EP%d: len=%zu xfrd=%zu\n", - privep->epphy, privreq->req.len, privreq->req.xfrd); - - /* Return the completed read request to the class driver and mark the state - * IDLE. - */ - - usbtrace(TRACE_COMPLETE(privep->epphy), privreq->req.xfrd); - stm32_req_complete(privep, OK); - privep->active = false; - - /* Now set up the next read request (if any) */ - - stm32_epout_request(priv, privep); -} - -/**************************************************************************** - * Name: stm32_ep0out_receive - * - * Description: - * This function is called from the RXFLVL interrupt handler when new - * incoming data is available in the endpoint's RxFIFO. This function - * will simply copy the incoming data into pending request's data buffer. - * - ****************************************************************************/ - -static inline void stm32_ep0out_receive(struct stm32_ep_s *privep, - int bcnt) -{ - struct stm32_usbdev_s *priv; - - /* Sanity Checking */ - - DEBUGASSERT(privep && privep->dev); - priv = (struct stm32_usbdev_s *)privep->dev; - - uinfo("EP0: bcnt=%d\n", bcnt); - usbtrace(TRACE_READ(EP0), bcnt); - - /* Verify that an OUT SETUP request as received before this data was - * received in the RxFIFO. - */ - - if (priv->ep0state == EP0STATE_SETUP_OUT) - { - if (priv->ep0datlen < CONFIG_USBDEV_SETUP_MAXDATASIZE) - { - /* Read the data into our special buffer for SETUP data */ - - int bufspace = CONFIG_USBDEV_SETUP_MAXDATASIZE - priv->ep0datlen; - int readlen = MIN(bufspace, bcnt); - stm32_rxfifo_read(privep, priv->ep0data, readlen); - priv->ep0datlen += readlen; - bcnt -= readlen; - } - - /* Do we have to discard any excess bytes? */ - - if (bcnt > 0) - { - stm32_rxfifo_discard(privep, bcnt); - priv->ep0datlen += bcnt; - } - - /* Is the transfer complete? */ - - if (priv->ep0datlen >= GETUINT16(priv->ctrlreq.len)) - { - /* Now we can process the setup command */ - - privep->active = false; - priv->ep0state = EP0STATE_SETUP_READY; - priv->ep0datlen = MIN(CONFIG_USBDEV_SETUP_MAXDATASIZE, - priv->ep0datlen); - - stm32_ep0out_setup(priv); - } - else - { - /* More data to come, clear NAKSTS */ - - uint32_t regval = stm32_getreg(STM32_OTGFS_DOEPCTL0); - regval |= OTGFS_DOEPCTL0_CNAK; - stm32_putreg(regval, STM32_OTGFS_DOEPCTL0); - } - } - else - { - /* This is an error. We don't have any idea what to do with the EP0 - * data in this case. Just read and discard it so that the RxFIFO - * does not become constipated. - */ - - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_NOOUTSETUP), priv->ep0state); - stm32_rxfifo_discard(privep, bcnt); - privep->active = false; - } -} - -/**************************************************************************** - * Name: stm32_epout_receive - * - * Description: - * This function is called from the RXFLVL interrupt handler when new - * incoming data is available in the endpoint's RxFIFO. This function - * will simply copy the incoming data into pending request's data buffer. - * - ****************************************************************************/ - -static inline void stm32_epout_receive(struct stm32_ep_s *privep, - int bcnt) -{ - struct stm32_req_s *privreq; - uint8_t *dest; - int buflen; - int readlen; - - /* Get a reference to the request at the head of the endpoint's request - * queue. - */ - - privreq = stm32_rqpeek(privep); - if (!privreq) - { - /* Incoming data is available in the RxFIFO, but there is no read setup - * to receive the receive the data. This should not happen for data - * endpoints; those endpoints should have been NAKing any OUT data - * tokens. - * - * We should get here normally on OUT data phase following an OUT - * SETUP command. EP0 data will still receive data in this case and it - * should not be NAKing. - */ - - if (privep->epphy == 0) - { - stm32_ep0out_receive(privep, bcnt); - } - else - { - /* Otherwise, the data is lost. This really should not happen if - * NAKing is working as expected. - */ - - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EPOUTQEMPTY), - privep->epphy); - - /* Discard the data in the RxFIFO */ - - stm32_rxfifo_discard(privep, bcnt); - } - - privep->active = false; - return; - } - - uinfo("EP%d: len=%zu xfrd=%zu\n", - privep->epphy, privreq->req.len, privreq->req.xfrd); - usbtrace(TRACE_READ(privep->epphy), bcnt); - - /* Get the number of bytes to transfer from the RxFIFO */ - - buflen = privreq->req.len - privreq->req.xfrd; - DEBUGASSERT(buflen > 0 && buflen >= bcnt); - readlen = MIN(buflen, bcnt); - - /* Get the destination of the data transfer */ - - dest = privreq->req.buf + privreq->req.xfrd; - - /* Transfer the data from the RxFIFO to the request's data buffer */ - - stm32_rxfifo_read(privep, dest, readlen); - - /* If there were more bytes in the RxFIFO than could be held in the read - * request, then we will have to discard those. - */ - - stm32_rxfifo_discard(privep, bcnt - readlen); - - /* Update the number of bytes transferred */ - - privreq->req.xfrd += readlen; -} - -/**************************************************************************** - * Name: stm32_epout_request - * - * Description: - * This function is called when either (1) new read request is received, or - * (2) a pending receive request completes. If there is no read in - * pending, then this function will initiate the next OUT (read) operation. - * - ****************************************************************************/ - -static void stm32_epout_request(struct stm32_usbdev_s *priv, - struct stm32_ep_s *privep) -{ - struct stm32_req_s *privreq; - uint32_t regaddr; - uint32_t regval; - uint32_t xfrsize; - uint32_t pktcnt; - - /* Make sure that there is not already a pending request request. If - * there is, just return, leaving the newly received request in the - * request queue. - */ - - if (!privep->active) - { - /* Loop until a valid request is found (or the request queue is empty). - * The loop is only need to look at the request queue again is an - * invalid read request is encountered. - */ - - for (; ; ) - { - /* Get a reference to the request at the head of the endpoint's - * request queue - */ - - privreq = stm32_rqpeek(privep); - if (!privreq) - { - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EPOUTQEMPTY), - privep->epphy); - - /* There are no read requests to be setup. Configure the - * hardware to NAK any incoming packets. (This should already - * be the case. I think that the hardware will automatically - * NAK after a transfer is completed until SNAK is cleared). - */ - - regaddr = STM32_OTGFS_DOEPCTL(privep->epphy); - regval = stm32_getreg(regaddr); - regval |= OTGFS_DOEPCTL_SNAK; - stm32_putreg(regval, regaddr); - - /* This endpoint is no longer actively transferring */ - - privep->active = false; - return; - } - - uinfo("EP%d: len=%d\n", privep->epphy, privreq->req.len); - - /* Ignore any attempt to receive a zero length packet (this really - * should not happen. - */ - - if (privreq->req.len <= 0) - { - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EPOUTNULLPACKET), 0); - stm32_req_complete(privep, OK); - } - - /* Otherwise, we have a usable read request... break out of the - * loop - */ - - else - { - break; - } - } - - /* Setup the pending read into the request buffer. First calculate: - * - * pktcnt = the number of packets (of maxpacket bytes) required to - * perform the transfer. - * xfrsize = The total number of bytes required (in units of - * maxpacket bytes). - */ - - pktcnt = (privreq->req.len + (privep->ep.maxpacket - 1)) / - privep->ep.maxpacket; - xfrsize = pktcnt * privep->ep.maxpacket; - - /* Then setup the hardware to perform this transfer */ - - regaddr = STM32_OTGFS_DOEPTSIZ(privep->epphy); - regval = stm32_getreg(regaddr); - regval &= ~(OTGFS_DOEPTSIZ_XFRSIZ_MASK | OTGFS_DOEPTSIZ_PKTCNT_MASK); - regval |= (xfrsize << OTGFS_DOEPTSIZ_XFRSIZ_SHIFT); - regval |= (pktcnt << OTGFS_DOEPTSIZ_PKTCNT_SHIFT); - stm32_putreg(regval, regaddr); - - /* Then enable the transfer */ - - regaddr = STM32_OTGFS_DOEPCTL(privep->epphy); - regval = stm32_getreg(regaddr); - - /* When an isochronous transfer is enabled the Even/Odd frame bit must - * also be set appropriately. - */ - -#ifdef CONFIG_USBDEV_ISOCHRONOUS - if (privep->eptype == USB_EP_ATTR_XFER_ISOC) - { - if (privep->odd) - { - regval |= OTGFS_DOEPCTL_SODDFRM; - } - else - { - regval |= OTGFS_DOEPCTL_SEVNFRM; - } - } -#endif - - /* Clearing NAKing and enable the transfer. */ - - regval |= (OTGFS_DOEPCTL_CNAK | OTGFS_DOEPCTL_EPENA); - stm32_putreg(regval, regaddr); - - /* A transfer is now active on this endpoint */ - - privep->active = true; - - /* EP0 is a special case. We need to know when to switch back to - * normal SETUP processing. - */ - - if (privep->epphy == EP0) - { - priv->ep0state = EP0STATE_DATA_OUT; - } - } -} - -/**************************************************************************** - * Name: stm32_ep_flush - * - * Description: - * Flush any primed descriptors from this ep - * - ****************************************************************************/ - -static void stm32_ep_flush(struct stm32_ep_s *privep) -{ - if (privep->isin) - { - stm32_txfifo_flush(OTGFS_GRSTCTL_TXFNUM_D(privep->epphy)); - } - else - { - stm32_rxfifo_flush(); - } -} - -/**************************************************************************** - * Name: stm32_req_complete - * - * Description: - * Handle termination of the request at the head of the endpoint request - * queue. - * - ****************************************************************************/ - -static void stm32_req_complete(struct stm32_ep_s *privep, int16_t result) -{ - struct stm32_req_s *privreq; - - /* Remove the request at the head of the request list */ - - privreq = stm32_req_remfirst(privep); - DEBUGASSERT(privreq != NULL); - - /* If endpoint 0, temporarily reflect the state of protocol stalled - * in the callback. - */ - - bool stalled = privep->stalled; - if (privep->epphy == EP0) - { - privep->stalled = privep->dev->stalled; - } - - /* Save the result in the request structure */ - - privreq->req.result = result; - - /* Callback to the request completion handler */ - - privreq->req.callback(&privep->ep, &privreq->req); - - /* Restore the stalled indication */ - - privep->stalled = stalled; -} - -/**************************************************************************** - * Name: stm32_req_cancel - * - * Description: - * Cancel all pending requests for an endpoint - * - ****************************************************************************/ - -static void stm32_req_cancel(struct stm32_ep_s *privep, int16_t status) -{ - if (!stm32_rqempty(privep)) - { - stm32_ep_flush(privep); - } - - while (!stm32_rqempty(privep)) - { - usbtrace(TRACE_COMPLETE(privep->epphy), - (stm32_rqpeek(privep))->req.xfrd); - stm32_req_complete(privep, status); - } -} - -/**************************************************************************** - * Name: stm32_ep_findbyaddr - * - * Description: - * Find the physical endpoint structure corresponding to a logic endpoint - * address - * - ****************************************************************************/ - -static struct stm32_ep_s *stm32_ep_findbyaddr(struct stm32_usbdev_s *priv, - uint16_t eplog) -{ - struct stm32_ep_s *privep; - uint8_t epphy = USB_EPNO(eplog); - - if (epphy >= STM32_NENDPOINTS) - { - return NULL; - } - - /* Is this an IN or an OUT endpoint? */ - - if (USB_ISEPIN(eplog)) - { - privep = &priv->epin[epphy]; - } - else - { - privep = &priv->epout[epphy]; - } - - /* Return endpoint reference */ - - DEBUGASSERT(privep->epphy == epphy); - return privep; -} - -/**************************************************************************** - * Name: stm32_req_dispatch - * - * Description: - * Provide unhandled setup actions to the class driver. This is logically - * part of the USB interrupt handler. - * - ****************************************************************************/ - -static int stm32_req_dispatch(struct stm32_usbdev_s *priv, - const struct usb_ctrlreq_s *ctrl) -{ - int ret = -EIO; - - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_DISPATCH), 0); - if (priv->driver) - { - /* Forward to the control request to the class driver implementation */ - - ret = CLASS_SETUP(priv->driver, &priv->usbdev, ctrl, - priv->ep0data, priv->ep0datlen); - } - - if (ret < 0) - { - /* Stall on failure */ - - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_DISPATCHSTALL), 0); - priv->stalled = true; - } - - return ret; -} - -/**************************************************************************** - * Name: stm32_usbreset - * - * Description: - * Reset Usb engine - * - ****************************************************************************/ - -static void stm32_usbreset(struct stm32_usbdev_s *priv) -{ - struct stm32_ep_s *privep; - uint32_t regval; - int i; - - /* Clear the Remote Wake-up Signaling */ - - regval = stm32_getreg(STM32_OTGFS_DCTL); - regval &= ~OTGFS_DCTL_RWUSIG; - stm32_putreg(regval, STM32_OTGFS_DCTL); - - /* Flush the EP0 Tx FIFO */ - - stm32_txfifo_flush(OTGFS_GRSTCTL_TXFNUM_D(EP0)); - - /* Tell the class driver that we are disconnected. The class - * driver should then accept any new configurations. - */ - - if (priv->driver) - { - CLASS_DISCONNECT(priv->driver, &priv->usbdev); - } - - /* Mark all endpoints as available */ - - priv->epavail[0] = STM32_EP_AVAILABLE; - priv->epavail[1] = STM32_EP_AVAILABLE; - - /* Disable all end point interrupts */ - - for (i = 0; i < STM32_NENDPOINTS ; i++) - { - /* Disable endpoint interrupts */ - - stm32_putreg(0xff, STM32_OTGFS_DIEPINT(i)); - stm32_putreg(0xff, STM32_OTGFS_DOEPINT(i)); - - /* Return write requests to the class implementation */ - - privep = &priv->epin[i]; - stm32_req_cancel(privep, -ESHUTDOWN); - - /* Reset IN endpoint status */ - - privep->stalled = false; - privep->active = false; - privep->zlp = false; - - /* Return read requests to the class implementation */ - - privep = &priv->epout[i]; - stm32_req_cancel(privep, -ESHUTDOWN); - - /* Reset endpoint status */ - - privep->stalled = false; - privep->active = false; - privep->zlp = false; - } - - stm32_putreg(0xffffffff, STM32_OTGFS_DAINT); - - /* Mask all device endpoint interrupts except EP0 */ - - regval = (OTGFS_DAINT_IEP(EP0) | OTGFS_DAINT_OEP(EP0)); - stm32_putreg(regval, STM32_OTGFS_DAINTMSK); - - /* Unmask OUT interrupts */ - - regval = (OTGFS_DOEPMSK_XFRCM | OTGFS_DOEPMSK_STUPM | OTGFS_DOEPMSK_EPDM); - stm32_putreg(regval, STM32_OTGFS_DOEPMSK); - - /* Unmask IN interrupts */ - - regval = (OTGFS_DIEPMSK_XFRCM | OTGFS_DIEPMSK_EPDM | OTGFS_DIEPMSK_TOM); - stm32_putreg(regval, STM32_OTGFS_DIEPMSK); - - /* Reset device address to 0 */ - - stm32_setaddress(priv, 0); - priv->devstate = DEVSTATE_DEFAULT; - priv->usbdev.speed = USB_SPEED_FULL; - - /* Re-configure EP0 */ - - stm32_ep0_configure(priv); - - /* Setup EP0 to receive SETUP packets */ - - stm32_ep0out_ctrlsetup(priv); -} - -/**************************************************************************** - * Name: stm32_ep0out_testmode - * - * Description: - * Select test mode - * - ****************************************************************************/ - -static inline void stm32_ep0out_testmode(struct stm32_usbdev_s *priv, - uint16_t index) -{ - uint8_t testmode; - - testmode = index >> 8; - switch (testmode) - { - case 1: - priv->testmode = OTGFS_TESTMODE_J; - break; - - case 2: - priv->testmode = OTGFS_TESTMODE_K; - break; - - case 3: - priv->testmode = OTGFS_TESTMODE_SE0_NAK; - break; - - case 4: - priv->testmode = OTGFS_TESTMODE_PACKET; - break; - - case 5: - priv->testmode = OTGFS_TESTMODE_FORCE; - break; - - default: - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADTESTMODE), testmode); - priv->dotest = false; - priv->testmode = OTGFS_TESTMODE_DISABLED; - priv->stalled = true; - } - - priv->dotest = true; - stm32_ep0in_transmitzlp(priv); -} - -/**************************************************************************** - * Name: stm32_ep0out_stdrequest - * - * Description: - * Handle a standard request on EP0. Pick off the things of interest to - * the USB device controller driver; pass what is left to the class driver. - * - ****************************************************************************/ - -static inline void stm32_ep0out_stdrequest(struct stm32_usbdev_s *priv, - struct stm32_ctrlreq_s * - ctrlreq) -{ - struct stm32_ep_s *privep; - - /* Handle standard request */ - - switch (ctrlreq->req) - { - case USB_REQ_GETSTATUS: - { - /* type: device-to-host; recipient = device, interface, endpoint - * value: 0 - * index: zero interface endpoint - * len: 2; data = status - */ - - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_GETSTATUS), 0); - if (!priv->addressed || - ctrlreq->len != 2 || - USB_REQ_ISOUT(ctrlreq->type) || - ctrlreq->value != 0) - { - priv->stalled = true; - } - else - { - switch (ctrlreq->type & USB_REQ_RECIPIENT_MASK) - { - case USB_REQ_RECIPIENT_ENDPOINT: - { - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPGETSTATUS), 0); - privep = stm32_ep_findbyaddr(priv, ctrlreq->index); - if (!privep) - { - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADEPGETSTATUS), - 0); - priv->stalled = true; - } - else - { - if (privep->stalled) - { - priv->ep0data[0] = (1 << USB_FEATURE_ENDPOINTHALT); - } - else - { - priv->ep0data[0] = 0; /* Not stalled */ - } - - priv->ep0data[1] = 0; - stm32_ep0in_setupresponse(priv, priv->ep0data, 2); - } - } - break; - - case USB_REQ_RECIPIENT_DEVICE: - { - if (ctrlreq->index == 0) - { - usbtrace(TRACE_INTDECODE( - STM32_TRACEINTID_DEVGETSTATUS), - 0); - - /* Features: Remote Wakeup and self-powered */ - - priv->ep0data[0] = (priv->selfpowered << - USB_FEATURE_SELFPOWERED); - priv->ep0data[0] |= (priv->wakeup << - USB_FEATURE_REMOTEWAKEUP); - priv->ep0data[1] = 0; - - stm32_ep0in_setupresponse(priv, priv->ep0data, 2); - } - else - { - usbtrace(TRACE_DEVERROR( - STM32_TRACEERR_BADDEVGETSTATUS), - 0); - priv->stalled = true; - } - } - break; - - case USB_REQ_RECIPIENT_INTERFACE: - { - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_IFGETSTATUS), 0); - priv->ep0data[0] = 0; - priv->ep0data[1] = 0; - - stm32_ep0in_setupresponse(priv, priv->ep0data, 2); - } - break; - - default: - { - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADGETSTATUS), 0); - priv->stalled = true; - } - break; - } - } - } - break; - - case USB_REQ_CLEARFEATURE: - { - /* type: host-to-device; recipient = device, interface or endpoint - * value: feature selector - * index: zero interface endpoint; - * len: zero, data = none - */ - - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_CLEARFEATURE), 0); - if (priv->addressed != 0 && ctrlreq->len == 0) - { - uint8_t recipient = ctrlreq->type & USB_REQ_RECIPIENT_MASK; - if (recipient == USB_REQ_RECIPIENT_ENDPOINT && - ctrlreq->value == USB_FEATURE_ENDPOINTHALT && - (privep = stm32_ep_findbyaddr(priv, ctrlreq->index)) != NULL) - { - stm32_ep_clrstall(privep); - stm32_ep0in_transmitzlp(priv); - } - else if (recipient == USB_REQ_RECIPIENT_DEVICE && - ctrlreq->value == USB_FEATURE_REMOTEWAKEUP) - { - priv->wakeup = 0; - stm32_ep0in_transmitzlp(priv); - } - else - { - /* Actually, I think we could just stall here. */ - - stm32_req_dispatch(priv, &priv->ctrlreq); - } - } - else - { - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADCLEARFEATURE), 0); - priv->stalled = true; - } - } - break; - - case USB_REQ_SETFEATURE: - { - /* type: host-to-device; recipient = device, interface, endpoint - * value: feature selector - * index: zero interface endpoint; - * len: 0; data = none - */ - - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SETFEATURE), 0); - if (priv->addressed != 0 && ctrlreq->len == 0) - { - uint8_t recipient = ctrlreq->type & USB_REQ_RECIPIENT_MASK; - if (recipient == USB_REQ_RECIPIENT_ENDPOINT && - ctrlreq->value == USB_FEATURE_ENDPOINTHALT && - (privep = stm32_ep_findbyaddr(priv, ctrlreq->index)) != NULL) - { - stm32_ep_setstall(privep); - stm32_ep0in_transmitzlp(priv); - } - else if (recipient == USB_REQ_RECIPIENT_DEVICE && - ctrlreq->value == USB_FEATURE_REMOTEWAKEUP) - { - priv->wakeup = 1; - stm32_ep0in_transmitzlp(priv); - } - else if (recipient == USB_REQ_RECIPIENT_DEVICE && - ctrlreq->value == USB_FEATURE_TESTMODE && - ((ctrlreq->index & 0xff) == 0)) - { - stm32_ep0out_testmode(priv, ctrlreq->index); - } - else if (priv->configured) - { - /* Actually, I think we could just stall here. */ - - stm32_req_dispatch(priv, &priv->ctrlreq); - } - else - { - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADSETFEATURE), 0); - priv->stalled = true; - } - } - else - { - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADSETFEATURE), 0); - priv->stalled = true; - } - } - break; - - case USB_REQ_SETADDRESS: - { - /* type: host-to-device; recipient = device - * value: device address - * index: 0 - * len: 0; data = none - */ - - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SETADDRESS), - ctrlreq->value); - if ((ctrlreq->type & USB_REQ_RECIPIENT_MASK) == - USB_REQ_RECIPIENT_DEVICE && - ctrlreq->index == 0 && - ctrlreq->len == 0 && - ctrlreq->value < 128 && - priv->devstate != DEVSTATE_CONFIGURED) - { - /* Save the address. We cannot actually change to the next - * address until the completion of the status phase. - */ - - stm32_setaddress(priv, (uint16_t)priv->ctrlreq.value[0]); - stm32_ep0in_transmitzlp(priv); - } - else - { - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADSETADDRESS), 0); - priv->stalled = true; - } - } - break; - - case USB_REQ_GETDESCRIPTOR: - /* type: device-to-host; recipient = device - * value: descriptor type and index - * index: 0 or language ID; - * len: descriptor len; data = descriptor - */ - - case USB_REQ_SETDESCRIPTOR: - /* type: host-to-device; recipient = device - * value: descriptor type and index - * index: 0 or language ID; - * len: descriptor len; data = descriptor - */ - - { - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_GETSETDESC), 0); - if ((ctrlreq->type & USB_REQ_RECIPIENT_MASK) == - USB_REQ_RECIPIENT_DEVICE) - { - stm32_req_dispatch(priv, &priv->ctrlreq); - } - else - { - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADGETSETDESC), 0); - priv->stalled = true; - } - } - break; - - case USB_REQ_GETCONFIGURATION: - /* type: device-to-host; recipient = device - * value: 0; - * index: 0; - * len: 1; data = configuration value - */ - - { - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_GETCONFIG), 0); - if (priv->addressed && - (ctrlreq->type & USB_REQ_RECIPIENT_MASK) == - USB_REQ_RECIPIENT_DEVICE && - ctrlreq->value == 0 && - ctrlreq->index == 0 && - ctrlreq->len == 1) - { - stm32_req_dispatch(priv, &priv->ctrlreq); - } - else - { - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADGETCONFIG), 0); - priv->stalled = true; - } - } - break; - - case USB_REQ_SETCONFIGURATION: - /* type: host-to-device; recipient = device - * value: configuration value - * index: 0; - * len: 0; data = none - */ - - { - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SETCONFIG), 0); - if (priv->addressed && - (ctrlreq->type & USB_REQ_RECIPIENT_MASK) == - USB_REQ_RECIPIENT_DEVICE && - ctrlreq->index == 0 && - ctrlreq->len == 0) - { - /* Give the configuration to the class driver */ - - int ret = stm32_req_dispatch(priv, &priv->ctrlreq); - - /* If the class driver accepted the configuration, then mark the - * device state as configured (or not, depending on the - * configuration). - */ - - if (ret == OK) - { - uint8_t cfg = (uint8_t)ctrlreq->value; - if (cfg != 0) - { - priv->devstate = DEVSTATE_CONFIGURED; - priv->configured = true; - } - else - { - priv->devstate = DEVSTATE_ADDRESSED; - priv->configured = false; - } - } - } - else - { - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADSETCONFIG), 0); - priv->stalled = true; - } - } - break; - - case USB_REQ_GETINTERFACE: - /* type: device-to-host; recipient = interface - * value: 0 - * index: interface; - * len: 1; data = alt interface - */ - - case USB_REQ_SETINTERFACE: - /* type: host-to-device; recipient = interface - * value: alternate setting - * index: interface; - * len: 0; data = none - */ - - { - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_GETSETIF), 0); - stm32_req_dispatch(priv, &priv->ctrlreq); - } - break; - - case USB_REQ_SYNCHFRAME: - /* type: device-to-host; recipient = endpoint - * value: 0 - * index: endpoint; - * len: 2; data = frame number - */ - - { - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SYNCHFRAME), 0); - } - break; - - default: - { - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDCTRLREQ), 0); - priv->stalled = true; - } - break; - } -} - -/**************************************************************************** - * Name: stm32_ep0out_setup - * - * Description: - * USB Ctrl EP Setup Event. This is logically part of the USB interrupt - * handler. This event occurs when a setup packet is receive on EP0 OUT. - * - ****************************************************************************/ - -static inline void stm32_ep0out_setup(struct stm32_usbdev_s *priv) -{ - struct stm32_ctrlreq_s ctrlreq; - - /* Verify that a SETUP was received */ - - if (priv->ep0state != EP0STATE_SETUP_READY) - { - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EP0NOSETUP), priv->ep0state); - return; - } - - /* Terminate any pending requests */ - - stm32_req_cancel(&priv->epout[EP0], -EPROTO); - stm32_req_cancel(&priv->epin[EP0], -EPROTO); - - /* Assume NOT stalled */ - - priv->epout[EP0].stalled = false; - priv->epin[EP0].stalled = false; - priv->stalled = false; - - /* Starting to process a control request - update state */ - - priv->ep0state = EP0STATE_SETUP_PROCESS; - - /* And extract the little-endian 16-bit values to host order */ - - ctrlreq.type = priv->ctrlreq.type; - ctrlreq.req = priv->ctrlreq.req; - ctrlreq.value = GETUINT16(priv->ctrlreq.value); - ctrlreq.index = GETUINT16(priv->ctrlreq.index); - ctrlreq.len = GETUINT16(priv->ctrlreq.len); - - uinfo("type=%02x req=%02x value=%04x index=%04x len=%04x\n", - ctrlreq.type, ctrlreq.req, ctrlreq.value, ctrlreq.index, - ctrlreq.len); - - /* Check for a standard request */ - - if ((ctrlreq.type & USB_REQ_TYPE_MASK) != USB_REQ_TYPE_STANDARD) - { - /* Dispatch any non-standard requests */ - - stm32_req_dispatch(priv, &priv->ctrlreq); - } - else - { - /* Handle standard requests. */ - - stm32_ep0out_stdrequest(priv, &ctrlreq); - } - - /* Check if the setup processing resulted in a STALL */ - - if (priv->stalled) - { - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EP0SETUPSTALLED), - priv->ep0state); - stm32_ep0_stall(priv); - } - - /* Reset state/data associated with the SETUP request */ - - priv->ep0datlen = 0; -} - -/**************************************************************************** - * Name: stm32_epout - * - * Description: - * This is part of the OUT endpoint interrupt processing. This function - * handles the OUT event for a single endpoint. - * - ****************************************************************************/ - -static inline void stm32_epout(struct stm32_usbdev_s *priv, uint8_t epno) -{ - struct stm32_ep_s *privep; - - /* Endpoint 0 is a special case. */ - - if (epno == 0) - { - privep = &priv->epout[EP0]; - - /* In the EP0STATE_DATA_OUT state, we are receiving data into the - * request buffer. In that case, we must continue the request - * processing. - */ - - if (priv->ep0state == EP0STATE_DATA_OUT) - { - /* Continue processing data from the EP0 OUT request queue */ - - stm32_epout_complete(priv, privep); - - /* If we are not actively processing an OUT request, then we - * need to setup to receive the next control request. - */ - - if (!privep->active) - { - stm32_ep0out_ctrlsetup(priv); - priv->ep0state = EP0STATE_IDLE; - } - } - } - - /* For other endpoints, the only possibility is that we are continuing - * or finishing an OUT request. - */ - - else if (priv->devstate == DEVSTATE_CONFIGURED) - { - stm32_epout_complete(priv, &priv->epout[epno]); - } -} - -/**************************************************************************** - * Name: stm32_epout_interrupt - * - * Description: - * USB OUT endpoint interrupt handler. The core generates this interrupt - * when there is an interrupt is pending on one of the OUT endpoints of - * the core. - * The driver must read the OTGFS DAINT register to determine the exact - * number of the OUT endpoint on which the interrupt occurred, and then - * read the corresponding OTGFS DOEPINTx register to determine the exact - * cause of the interrupt. - * - ****************************************************************************/ - -static inline void stm32_epout_interrupt(struct stm32_usbdev_s *priv) -{ - uint32_t daint; - uint32_t regval; - uint32_t doepint; - int epno; - - /* Get the pending, enabled interrupts for the OUT endpoint from the - * endpoint interrupt status register. - */ - - regval = stm32_getreg(STM32_OTGFS_DAINT); - regval &= stm32_getreg(STM32_OTGFS_DAINTMSK); - daint = (regval & OTGFS_DAINT_OEP_MASK) >> OTGFS_DAINT_OEP_SHIFT; - - if (daint == 0) - { - /* We got an interrupt, but there is no unmasked endpoint that caused - * it ?! When this happens, the interrupt flag never gets cleared and - * we are stuck in infinite interrupt loop. - * - * This shouldn't happen if we are diligent about handling timing - * issues when masking endpoint interrupts. However, this workaround - * avoids infinite loop and allows operation to continue normally. It - * works by clearing each endpoint flags, masked or not. - */ - - regval = stm32_getreg(STM32_OTGFS_DAINT); - daint = (regval & OTGFS_DAINT_OEP_MASK) >> OTGFS_DAINT_OEP_SHIFT; - - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EPOUTUNEXPECTED), - (uint16_t)regval); - - epno = 0; - while (daint) - { - if ((daint & 1) != 0) - { - regval = stm32_getreg(STM32_OTGFS_DOEPINT(epno)); - uinfo("DOEPINT(%d) = %08" PRIx32 "\n", epno, regval); - stm32_putreg(0xff, STM32_OTGFS_DOEPINT(epno)); - } - - epno++; - daint >>= 1; - } - - return; - } - - /* Process each pending IN endpoint interrupt */ - - epno = 0; - while (daint) - { - /* Is an OUT interrupt pending for this endpoint? */ - - if ((daint & 1) != 0) - { - /* Yes.. get the OUT endpoint interrupt status */ - - doepint = stm32_getreg(STM32_OTGFS_DOEPINT(epno)); - doepint &= stm32_getreg(STM32_OTGFS_DOEPMSK); - - /* Transfer completed interrupt. This interrupt is triggered when - * stm32_rxinterrupt() removes the last packet data from the - * RxFIFO. In this case, core internally sets the NAK bit for this - * endpoint to prevent it from receiving any more packets. - */ - - if ((doepint & OTGFS_DOEPINT_XFRC) != 0) - { - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPOUT_XFRC), - (uint16_t)doepint); - - /* Clear the bit in DOEPINTn for this interrupt */ - - stm32_putreg(OTGFS_DOEPINT_XFRC, STM32_OTGFS_DOEPINT(epno)); - - /* Handle the RX transfer data ready event */ - - stm32_epout(priv, epno); - } - - /* Endpoint disabled interrupt (ignored because this interrupt is - * used in polled mode by the endpoint disable logic). - */ -#if 1 - /* REVISIT: */ - - if ((doepint & OTGFS_DOEPINT_EPDISD) != 0) - { - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPOUT_EPDISD), - (uint16_t)doepint); - - /* Clear the bit in DOEPINTn for this interrupt */ - - stm32_putreg(OTGFS_DOEPINT_EPDISD, STM32_OTGFS_DOEPINT(epno)); - } -#endif - - /* Setup Phase Done (control EPs) */ - - if ((doepint & OTGFS_DOEPINT_SETUP) != 0) - { - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPOUT_SETUP), - priv->ep0state); - - /* Handle the receipt of the IN SETUP packets now (OUT setup - * packet processing may be delayed until the accompanying - * OUT DATA is received) - */ - - if (priv->ep0state == EP0STATE_SETUP_READY) - { - stm32_ep0out_setup(priv); - } - - stm32_putreg(OTGFS_DOEPINT_SETUP, STM32_OTGFS_DOEPINT(epno)); - } - } - - epno++; - daint >>= 1; - } -} - -/**************************************************************************** - * Name: stm32_epin_runtestmode - * - * Description: - * Execute the test mode setup by the SET FEATURE request - * - ****************************************************************************/ - -static inline void stm32_epin_runtestmode(struct stm32_usbdev_s *priv) -{ - uint32_t regval = stm32_getreg(STM32_OTGFS_DCTL); - regval &= OTGFS_DCTL_TCTL_MASK; - regval |= (uint32_t)priv->testmode << OTGFS_DCTL_TCTL_SHIFT; - stm32_putreg(regval , STM32_OTGFS_DCTL); - - priv->dotest = 0; - priv->testmode = OTGFS_TESTMODE_DISABLED; -} - -/**************************************************************************** - * Name: stm32_epin - * - * Description: - * This is part of the IN endpoint interrupt processing. This function - * handles the IN event for a single endpoint. - * - ****************************************************************************/ - -static inline void stm32_epin(struct stm32_usbdev_s *priv, uint8_t epno) -{ - struct stm32_ep_s *privep = &priv->epin[epno]; - - /* Endpoint 0 is a special case. */ - - if (epno == 0) - { - /* In the EP0STATE_DATA_IN state, we are sending data from request - * buffer. In that case, we must continue the request processing. - */ - - if (priv->ep0state == EP0STATE_DATA_IN) - { - /* Continue processing data from the EP0 OUT request queue */ - - stm32_epin_request(priv, privep); - - /* If we are not actively processing an OUT request, then we - * need to setup to receive the next control request. - */ - - if (!privep->active) - { - stm32_ep0out_ctrlsetup(priv); - priv->ep0state = EP0STATE_IDLE; - } - } - - /* Test mode is another special case */ - - if (priv->dotest) - { - stm32_epin_runtestmode(priv); - } - } - - /* For other endpoints, the only possibility is that we are continuing - * or finishing an IN request. - */ - - else if (priv->devstate == DEVSTATE_CONFIGURED) - { - /* Continue processing data from the endpoint write request queue */ - - stm32_epin_request(priv, privep); - } -} - -/**************************************************************************** - * Name: stm32_epin_txfifoempty - * - * Description: - * TxFIFO empty interrupt handling - * - ****************************************************************************/ - -static inline void stm32_epin_txfifoempty(struct stm32_usbdev_s *priv, - int epno) -{ - struct stm32_ep_s *privep = &priv->epin[epno]; - - /* Continue processing the write request queue. This may mean sending - * more data from the existing request or terminating the current requests - * and (perhaps) starting the IN transfer from the next write request. - */ - - stm32_epin_request(priv, privep); -} - -/**************************************************************************** - * Name: stm32_epin_interrupt - * - * Description: - * USB IN endpoint interrupt handler. The core generates this interrupt - * when an interrupt is pending on one of the IN endpoints of the core. - * The driver must read the OTGFS DAINT register to determine the exact - * number of the IN endpoint on which the interrupt occurred, and then - * read the corresponding OTGFS DIEPINTx register to determine the exact - * cause of the interrupt. - * - ****************************************************************************/ - -static inline void stm32_epin_interrupt(struct stm32_usbdev_s *priv) -{ - uint32_t diepint; - uint32_t daint; - uint32_t mask; - uint32_t empty; - int epno; - - /* Get the pending, enabled interrupts for the IN endpoint from the - * endpoint interrupt status register. - */ - - daint = stm32_getreg(STM32_OTGFS_DAINT); - daint &= stm32_getreg(STM32_OTGFS_DAINTMSK); - daint &= OTGFS_DAINT_IEP_MASK; - - if (daint == 0) - { - /* We got an interrupt, but there is no unmasked endpoint that caused - * it ?! When this happens, the interrupt flag never gets cleared and - * we are stuck in infinite interrupt loop. - * - * This shouldn't happen if we are diligent about handling timing - * issues when masking endpoint interrupts. However, this workaround - * avoids infinite loop and allows operation to continue normally. It - * works by clearing each endpoint flags, masked or not. - */ - - daint = stm32_getreg(STM32_OTGFS_DAINT); - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EPINUNEXPECTED), - (uint16_t)daint); - - daint &= OTGFS_DAINT_IEP_MASK; - epno = 0; - - while (daint) - { - if ((daint & 1) != 0) - { - uinfo("DIEPINT(%d) = %08" PRIx32 "\n", - epno, stm32_getreg(STM32_OTGFS_DIEPINT(epno))); - stm32_putreg(0xff, STM32_OTGFS_DIEPINT(epno)); - } - - epno++; - daint >>= 1; - } - - return; - } - - /* Process each pending IN endpoint interrupt */ - - epno = 0; - while (daint) - { - /* Is an IN interrupt pending for this endpoint? */ - - if ((daint & 1) != 0) - { - /* Get IN interrupt mask register. Bits 0-6 correspond to enabled - * interrupts as will be found in the DIEPINT interrupt status - * register. - */ - - mask = stm32_getreg(STM32_OTGFS_DIEPMSK); - - /* Check if the TxFIFO not empty interrupt is enabled for this - * endpoint in the DIEPMSK register. Bits n corresponds to - * endpoint n in the register. That condition corresponds to - * bit 7 of the DIEPINT interrupt status register. There is - * no TXFE bit in the mask register, so we fake one here. - */ - - empty = stm32_getreg(STM32_OTGFS_DIEPEMPMSK); - if ((empty & OTGFS_DIEPEMPMSK(epno)) != 0) - { - mask |= OTGFS_DIEPINT_TXFE; - } - - /* Now, read the interrupt status and mask out all disabled - * interrupts. - */ - - diepint = stm32_getreg(STM32_OTGFS_DIEPINT(epno)) & mask; - - /* Decode and process the enabled, pending interrupts */ - - /* Transfer completed interrupt */ - - if ((diepint & OTGFS_DIEPINT_XFRC) != 0) - { - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPIN_XFRC), - (uint16_t)diepint); - - /* It is possible that logic may be waiting for a the - * TxFIFO to become empty. We disable the TxFIFO empty - * interrupt here; it will be re-enabled if there is still - * insufficient space in the TxFIFO. - */ - - empty &= ~OTGFS_DIEPEMPMSK(epno); - stm32_putreg(empty, STM32_OTGFS_DIEPEMPMSK); - stm32_putreg(OTGFS_DIEPINT_XFRC, STM32_OTGFS_DIEPINT(epno)); - - /* IN transfer complete */ - - stm32_epin(priv, epno); - } - - /* Timeout condition */ - - if ((diepint & OTGFS_DIEPINT_TOC) != 0) - { - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPIN_TOC), - (uint16_t)diepint); - stm32_putreg(OTGFS_DIEPINT_TOC, STM32_OTGFS_DIEPINT(epno)); - } - - /* IN token received when TxFIFO is empty. Applies to - * non-periodic IN endpoints only. This interrupt indicates - * that an IN token was received when the associated TxFIFO - * (periodic/non-periodic) was empty. This interrupt is asserted - * on the endpoint for which the IN token was received. - */ - - if ((diepint & OTGFS_DIEPINT_ITTXFE) != 0) - { - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPIN_ITTXFE), - (uint16_t)diepint); - stm32_epin_request(priv, &priv->epin[epno]); - stm32_putreg(OTGFS_DIEPINT_ITTXFE, STM32_OTGFS_DIEPINT(epno)); - } - - /* IN endpoint NAK effective (ignored as this used only in polled - * mode) - */ -#if 0 - if ((diepint & OTGFS_DIEPINT_INEPNE) != 0) - { - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPIN_INEPNE), - (uint16_t)diepint); - stm32_putreg(OTGFS_DIEPINT_INEPNE, STM32_OTGFS_DIEPINT(epno)); - } -#endif - - /* Endpoint disabled interrupt (ignored as this used only in polled - * mode) - */ -#if 0 - if ((diepint & OTGFS_DIEPINT_EPDISD) != 0) - { - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPIN_EPDISD), - (uint16_t)diepint); - stm32_putreg(OTGFS_DIEPINT_EPDISD, STM32_OTGFS_DIEPINT(epno)); - } -#endif - - /* Transmit FIFO empty */ - - if ((diepint & OTGFS_DIEPINT_TXFE) != 0) - { - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPIN_TXFE), - (uint16_t)diepint); - - /* If we were waiting for TxFIFO to become empty, the we might - * have both XFRC and TXFE interrupts pending. Since we do - * the same thing for both cases, ignore the TXFE if we have - * already processed the XFRC. - */ - - if ((diepint & OTGFS_DIEPINT_XFRC) == 0) - { - /* Mask further FIFO empty interrupts. This will be - * re-enabled whenever we need to wait for a FIFO event. - */ - - empty &= ~OTGFS_DIEPEMPMSK(epno); - stm32_putreg(empty, STM32_OTGFS_DIEPEMPMSK); - - /* Handle TxFIFO empty */ - - stm32_epin_txfifoempty(priv, epno); - } - - /* Clear the pending TxFIFO empty interrupt */ - - stm32_putreg(OTGFS_DIEPINT_TXFE, STM32_OTGFS_DIEPINT(epno)); - } - } - - epno++; - daint >>= 1; - } -} - -/**************************************************************************** - * Name: stm32_resumeinterrupt - * - * Description: - * Resume/remote wakeup detected interrupt - * - ****************************************************************************/ - -static inline void stm32_resumeinterrupt(struct stm32_usbdev_s *priv) -{ - uint32_t regval; - - /* Restart the PHY clock and un-gate USB core clock (HCLK) */ - -#ifdef CONFIG_USBDEV_LOWPOWER - regval = stm32_getreg(STM32_OTGFS_PCGCCTL); - regval &= ~(OTGFS_PCGCCTL_STPPCLK | OTGFS_PCGCCTL_GATEHCLK); - stm32_putreg(regval, STM32_OTGFS_PCGCCTL); -#endif - - /* Clear remote wake-up signaling */ - - regval = stm32_getreg(STM32_OTGFS_DCTL); - regval &= ~OTGFS_DCTL_RWUSIG; - stm32_putreg(regval, STM32_OTGFS_DCTL); - - /* Restore full power -- whatever that means for this particular board */ - - stm32_usbsuspend((struct usbdev_s *)priv, true); - - /* Notify the class driver of the resume event */ - - if (priv->driver) - { - CLASS_RESUME(priv->driver, &priv->usbdev); - } -} - -/**************************************************************************** - * Name: stm32_suspendinterrupt - * - * Description: - * USB suspend interrupt - * - ****************************************************************************/ - -static inline void stm32_suspendinterrupt(struct stm32_usbdev_s *priv) -{ -#ifdef CONFIG_USBDEV_LOWPOWER - uint32_t regval; -#endif - - /* Notify the class driver of the suspend event */ - - if (priv->driver) - { - CLASS_SUSPEND(priv->driver, &priv->usbdev); - } - -#ifdef CONFIG_USBDEV_LOWPOWER - /* OTGFS_DSTS_SUSPSTS is set as long as the suspend condition is detected - * on USB. Check if we are still have the suspend condition, that we are - * connected to the host, and that we have been configured. - */ - - regval = stm32_getreg(STM32_OTGFS_DSTS); - - if ((regval & OTGFS_DSTS_SUSPSTS) != 0 && devstate == DEVSTATE_CONFIGURED) - { - /* Switch off OTG FS clocking. Setting OTGFS_PCGCCTL_STPPCLK stops the - * PHY clock. - */ - - regval = stm32_getreg(STM32_OTGFS_PCGCCTL); - regval |= OTGFS_PCGCCTL_STPPCLK; - stm32_putreg(regval, STM32_OTGFS_PCGCCTL); - - /* Setting OTGFS_PCGCCTL_GATEHCLK gate HCLK to modules other than - * the AHB Slave and Master and wakeup logic. - */ - - regval |= OTGFS_PCGCCTL_GATEHCLK; - stm32_putreg(regval, STM32_OTGFS_PCGCCTL); - } -#endif - - /* Let the board-specific logic know that we have entered the suspend - * state - */ - - stm32_usbsuspend((struct usbdev_s *)priv, false); -} - -/**************************************************************************** - * Name: stm32_rxinterrupt - * - * Description: - * RxFIFO non-empty interrupt. This interrupt indicates that there is at - * least one packet pending to be read from the RxFIFO. - * - ****************************************************************************/ - -static inline void stm32_rxinterrupt(struct stm32_usbdev_s *priv) -{ - struct stm32_ep_s *privep; - uint32_t regval; - int bcnt; - int epphy; - - /* Disable the Rx status queue level interrupt */ - - while (0 != (stm32_getreg(STM32_OTGFS_GINTSTS) & OTGFS_GINT_RXFLVL)) - { - /* Get the status from the top of the FIFO */ - - regval = stm32_getreg(STM32_OTGFS_GRXSTSP); - - /* Decode status fields */ - - epphy = (regval & OTGFS_GRXSTSD_EPNUM_MASK) >> - OTGFS_GRXSTSD_EPNUM_SHIFT; - - /* Workaround for bad values read from the STM32_OTGFS_GRXSTSP register - * happens regval is 0xb4e48168 or 0xa80c9367 or 267E781c - * All of which provide out of range indexes for epout[epphy] - */ - - if (epphy < STM32_NENDPOINTS) - { - privep = &priv->epout[epphy]; - - /* Handle the RX event according to the packet status field */ - - switch (regval & OTGFS_GRXSTSD_PKTSTS_MASK) - { - /* Global OUT NAK. This indicate that the global OUT NAK bit - * has taken effect. - * - * PKTSTS = Global OUT NAK, BCNT = 0, EPNUM = Don't Care, - * DPID = Don't Care. - */ - - case OTGFS_GRXSTSD_PKTSTS_OUTNAK: - { - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_OUTNAK), 0); - } - break; - - /* OUT data packet received. - * - * PKTSTS = DataOUT, BCNT = size of the received data OUT packet, - * EPNUM = EPNUM on which the packet was received, DPID = Actual - * Data PID. - */ - - case OTGFS_GRXSTSD_PKTSTS_OUTRECVD: - { - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_OUTRECVD), epphy); - bcnt = (regval & OTGFS_GRXSTSD_BCNT_MASK) >> - OTGFS_GRXSTSD_BCNT_SHIFT; - if (bcnt > 0) - { - stm32_epout_receive(privep, bcnt); - } - } - break; - - /* OUT transfer completed. This indicates that an OUT data - * transfer for the specified OUT endpoint has completed. - * After this entry is popped from the receive FIFO, the core - * asserts a Transfer Completed interrupt on the specified OUT - * endpoint. - * - * PKTSTS = Data OUT Transfer Done, BCNT = 0, EPNUM = OUT EP - * Num on which the data transfer is complete, DPID = Don't Care. - */ - - case OTGFS_GRXSTSD_PKTSTS_OUTDONE: - { - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_OUTDONE), epphy); - } - break; - - /* SETUP transaction completed. This indicates that the Setup - * stage for the specified endpoint has completed and the Data - * stage has started. - * After this entry is popped from the receive FIFO, the core - * asserts a Setup interrupt on the specified control OUT - * endpoint (triggers an interrupt). - * - * PKTSTS = Setup Stage Done, BCNT = 0, EPNUM = Control EP Num, - * DPID = Don't Care. - */ - - case OTGFS_GRXSTSD_PKTSTS_SETUPDONE: - { - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SETUPDONE), epphy); - - /* Now that the Setup Phase is complete if it was an OUT - * enable the endpoint - * (Doing this here prevents the loss of the first FIFO word) - */ - - if (priv->ep0state == EP0STATE_SETUP_OUT) - { - /* Clear NAKSTS so that we can receive the data */ - - regval = stm32_getreg(STM32_OTGFS_DOEPCTL0); - regval |= OTGFS_DOEPCTL0_CNAK; - stm32_putreg(regval, STM32_OTGFS_DOEPCTL0); - } - } - break; - - /* SETUP data packet received. This indicates that a SETUP - * packet for the specified endpoint is now available for - * reading from the receive FIFO. - * - * PKTSTS = SETUP, BCNT = 8, EPNUM = Control EP Num, DPID = D0. - */ - - case OTGFS_GRXSTSD_PKTSTS_SETUPRECVD: - { - uint16_t datlen; - - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SETUPRECVD), - epphy); - - /* Read EP0 setup data. NOTE: If multiple SETUP packets are - * received, the last one overwrites the previous setup - * packets and only that last SETUP packet will be processed. - */ - - stm32_rxfifo_read(&priv->epout[EP0], - (uint8_t *)&priv->ctrlreq, - USB_SIZEOF_CTRLREQ); - - /* Was this an IN or an OUT SETUP packet. If it is an OUT - * SETUP, then we need to wait for the completion of the - * data phase to process the setup command. If it is an - * IN SETUP packet, then we must processing the command - * BEFORE we enter the DATA phase. - * - * If the data associated with the OUT SETUP packet is zero - * length, then, of course, we don't need to wait. - */ - - datlen = GETUINT16(priv->ctrlreq.len); - if (USB_REQ_ISOUT(priv->ctrlreq.type) && datlen > 0) - { - /* Wait for the data phase. */ - - priv->ep0state = EP0STATE_SETUP_OUT; - priv->ep0datlen = 0; - } - else - { - /* We can process the setup data as soon as SETUP done - * word is popped of the RxFIFO. - */ - - priv->ep0state = EP0STATE_SETUP_READY; - } - } - break; - - default: - { - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), - (regval & OTGFS_GRXSTSD_PKTSTS_MASK) >> - OTGFS_GRXSTSD_PKTSTS_SHIFT); - } - break; - } - } - } -} - -/**************************************************************************** - * Name: stm32_enuminterrupt - * - * Description: - * Enumeration done interrupt - * - ****************************************************************************/ - -static inline void stm32_enuminterrupt(struct stm32_usbdev_s *priv) -{ - uint32_t regval; - - /* Activate EP0 */ - - stm32_ep0in_activate(); - - /* Set USB turn-around time for the full speed device with internal PHY - * interface. - */ - - regval = stm32_getreg(STM32_OTGFS_GUSBCFG); - regval &= ~OTGFS_GUSBCFG_TRDT_MASK; - regval |= OTGFS_GUSBCFG_TRDT(6); - stm32_putreg(regval, STM32_OTGFS_GUSBCFG); -} - -/**************************************************************************** - * Name: stm32_isocininterrupt - * - * Description: - * Incomplete isochronous IN transfer interrupt. Assertion of the - * incomplete isochronous IN transfer interrupt indicates an incomplete - * isochronous IN transfer on at least one of the isochronous IN endpoints. - * - ****************************************************************************/ - -#ifdef CONFIG_USBDEV_ISOCHRONOUS -static inline void stm32_isocininterrupt(struct stm32_usbdev_s *priv) -{ - int i; - - /* The application must read the endpoint control register for all - * isochronous IN endpoints to detect endpoints with incomplete IN data - * transfers. - */ - - for (i = 0; i < STM32_NENDPOINTS; i++) - { - /* Is this an isochronous IN endpoint? */ - - privep = &priv->epin[i]; - if (privep->eptype != USB_EP_ATTR_XFER_ISOC) - { - /* No... keep looking */ - - continue; - } - - /* Is there an active read request on the isochronous OUT endpoint? */ - - if (!privep->active) - { - /* No.. the endpoint is not actively transmitting data */ - - continue; - } - - /* Check if this is the endpoint that had the incomplete transfer */ - - regaddr = STM32_OTGFS_DIEPCTL(privep->epphy); - doepctl = stm32_getreg(regaddr); - dsts = stm32_getreg(STM32_OTGFS_DSTS); - - /* EONUM = 0:even frame, 1:odd frame - * SOFFN = Frame number of the received SOF - */ - - eonum = ((doepctl & OTGFS_DIEPCTL_EONUM) != 0); - soffn = ((dsts & OTGFS_DSTS_SOFFN0) != 0); - - if (eonum != soffn) - { - /* Not this endpoint */ - - continue; - } - - /* For isochronous IN endpoints with incomplete transfers, - * the application must discard the data in the memory and - * disable the endpoint. - */ - - stm32_req_complete(privep, -EIO); -#warning "Will clear OTGFS_DIEPCTL_USBAEP too" - stm32_epin_disable(privep); - break; - } -} -#endif - -/**************************************************************************** - * Name: stm32_isocoutinterrupt - * - * Description: - * Incomplete periodic transfer interrupt - * - ****************************************************************************/ - -#ifdef CONFIG_USBDEV_ISOCHRONOUS -static inline void stm32_isocoutinterrupt(struct stm32_usbdev_s *priv) -{ - struct stm32_ep_s *privep; - struct stm32_req_s *privreq; - uint32_t regaddr; - uint32_t doepctl; - uint32_t dsts; - bool eonum; - bool soffn; - - /* When it receives an IISOOXFR interrupt, the application must read the - * control registers of all isochronous OUT endpoints to determine which - * endpoints had an incomplete transfer in the current microframe. An - * endpoint transfer is incomplete if both the following conditions are - * true: - * - * DOEPCTLx:EONUM = DSTS:SOFFN[0], and - * DOEPCTLx:EPENA = 1 - */ - - for (i = 0; i < STM32_NENDPOINTS; i++) - { - /* Is this an isochronous OUT endpoint? */ - - privep = &priv->epout[i]; - if (privep->eptype != USB_EP_ATTR_XFER_ISOC) - { - /* No... keep looking */ - - continue; - } - - /* Is there an active read request on the isochronous OUT endpoint? */ - - if (!privep->active) - { - /* No.. the endpoint is not actively transmitting data */ - - continue; - } - - /* Check if this is the endpoint that had the incomplete transfer */ - - regaddr = STM32_OTGFS_DOEPCTL(privep->epphy); - doepctl = stm32_getreg(regaddr); - dsts = stm32_getreg(STM32_OTGFS_DSTS); - - /* EONUM = 0:even frame, 1:odd frame - * SOFFN = Frame number of the received SOF - */ - - eonum = ((doepctl & OTGFS_DOEPCTL_EONUM) != 0); - soffn = ((dsts & OTGFS_DSTS_SOFFN0) != 0); - - if (eonum != soffn) - { - /* Not this endpoint */ - - continue; - } - - /* For isochronous OUT endpoints with incomplete transfers, - * the application must discard the data in the memory and - * disable the endpoint. - */ - - stm32_req_complete(privep, -EIO); -#warning "Will clear OTGFS_DOEPCTL_USBAEP too" - stm32_epout_disable(privep); - break; - } -} -#endif - -/**************************************************************************** - * Name: stm32_sessioninterrupt - * - * Description: - * Session request/new session detected interrupt - * - ****************************************************************************/ - -#ifdef CONFIG_USBDEV_VBUSSENSING -static inline void stm32_sessioninterrupt(struct stm32_usbdev_s *priv) -{ -#warning "Missing logic" -} -#endif - -/**************************************************************************** - * Name: stm32_otginterrupt - * - * Description: - * OTG interrupt - * - ****************************************************************************/ - -#ifdef CONFIG_USBDEV_VBUSSENSING -static inline void stm32_otginterrupt(struct stm32_usbdev_s *priv) -{ - uint32_t regval; - - /* Check for session end detected */ - - regval = stm32_getreg(STM32_OTGFS_GOTGINT); - if ((regval & OTGFS_GOTGINT_SEDET) != 0) - { -#warning "Missing logic" - } - - /* Clear OTG interrupt */ - - stm32_putreg(regval, STM32_OTGFS_GOTGINT); -} -#endif - -/**************************************************************************** - * Name: stm32_usbinterrupt - * - * Description: - * USB interrupt handler - * - ****************************************************************************/ - -static int stm32_usbinterrupt(int irq, void *context, void *arg) -{ - /* At present, there is only a single OTG FS device support. Hence it is - * pre-allocated as g_otgfsdev. However, in most code, the private data - * structure will be referenced using the 'priv' pointer (rather than the - * global data) in order to simplify any future support for multiple - * devices. - */ - - struct stm32_usbdev_s *priv = &g_otgfsdev; - uint32_t regval; - uint32_t reserved; - - usbtrace(TRACE_INTENTRY(STM32_TRACEINTID_USB), 0); - - /* Assure that we are in device mode */ - - DEBUGASSERT((stm32_getreg(STM32_OTGFS_GINTSTS) & OTGFS_GINTSTS_CMOD) == - OTGFS_GINTSTS_DEVMODE); - - /* Get the state of all enabled interrupts. We will do this repeatedly - * some interrupts (like RXFLVL) will generate additional interrupting - * events. - */ - - for (; ; ) - { - /* Get the set of pending, un-masked interrupts */ - - regval = stm32_getreg(STM32_OTGFS_GINTSTS); - reserved = (regval & OTGFS_GINT_RESERVED); - regval &= stm32_getreg(STM32_OTGFS_GINTMSK); - - /* With out modifying the reserved bits, acknowledge all - * **Writable** pending irqs we will service below - */ - - stm32_putreg(((regval | reserved) & OTGFS_GINT_RC_W1), - STM32_OTGFS_GINTSTS); - - /* Break out of the loop when there are no further pending (and - * unmasked) interrupts to be processes. - */ - - if (regval == 0) - { - break; - } - - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_INTPENDING), - (uint16_t)regval); - - /* OUT endpoint interrupt. The core sets this bit to indicate that an - * interrupt is pending on one of the OUT endpoints of the core. - */ - - if ((regval & OTGFS_GINT_OEP) != 0) - { - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPOUT), - (uint16_t)regval); - stm32_epout_interrupt(priv); - } - - /* IN endpoint interrupt. The core sets this bit to indicate that - * an interrupt is pending on one of the IN endpoints of the core. - */ - - if ((regval & OTGFS_GINT_IEP) != 0) - { - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPIN), (uint16_t)regval); - stm32_epin_interrupt(priv); - } - - /* Host/device mode mismatch error interrupt */ - -#ifdef CONFIG_DEBUG_USB - if ((regval & OTGFS_GINT_MMIS) != 0) - { - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_MISMATCH), - (uint16_t)regval); - } -#endif - - /* Resume/remote wakeup detected interrupt */ - - if ((regval & OTGFS_GINT_WKUP) != 0) - { - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_WAKEUP), - (uint16_t)regval); - stm32_resumeinterrupt(priv); - } - - /* USB suspend interrupt */ - - if ((regval & OTGFS_GINT_USBSUSP) != 0) - { - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SUSPEND), - (uint16_t)regval); - stm32_suspendinterrupt(priv); - } - - /* Start of frame interrupt */ - -#ifdef CONFIG_USBDEV_SOFINTERRUPT - if ((regval & OTGFS_GINT_SOF) != 0) - { - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SOF), (uint16_t)regval); - usbdev_sof_irq(&priv->usbdev, stm32_getframe(&priv->usbdev)); - } -#endif - - /* RxFIFO non-empty interrupt. Indicates that there is at least one - * packet pending to be read from the RxFIFO. - */ - - if ((regval & OTGFS_GINT_RXFLVL) != 0) - { - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_RXFIFO), - (uint16_t)regval); - stm32_rxinterrupt(priv); - } - - /* USB reset interrupt */ - - if ((regval & OTGFS_GINT_RESETS) != 0) - { - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_DEVRESET), - (uint16_t)regval); - - /* Perform the device reset */ - - stm32_usbreset(priv); - usbtrace(TRACE_INTEXIT(STM32_TRACEINTID_USB), 0); - return OK; - } - - /* Enumeration done interrupt */ - - if ((regval & OTGFS_GINT_ENUMDNE) != 0) - { - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_ENUMDNE), - (uint16_t)regval); - stm32_enuminterrupt(priv); - } - - /* Incomplete isochronous IN transfer interrupt. When the core finds - * non-empty any of the isochronous IN endpoint FIFOs scheduled for - * the current frame non-empty, the core generates an IISOIXFR - * interrupt. - */ - -#ifdef CONFIG_USBDEV_ISOCHRONOUS - if ((regval & OTGFS_GINT_IISOIXFR) != 0) - { - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_IISOIXFR), - (uint16_t)regval); - stm32_isocininterrupt(priv); - } - - /* Incomplete isochronous OUT transfer. For isochronous OUT - * endpoints, the XFRC interrupt may not always be asserted. If the - * core drops isochronous OUT data packets, the application could fail - * to detect the XFRC interrupt. The incomplete Isochronous OUT data - * interrupt indicates that an XFRC interrupt was not asserted on at - * least one of the isochronous OUT endpoints. At this point, the - * endpoint with the incomplete transfer remains enabled, but no active - * transfers remain in progress on this endpoint on the USB. - */ - - if ((regval & OTGFS_GINT_IISOOXFR) != 0) - { - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_IISOOXFR), - (uint16_t)regval); - stm32_isocoutinterrupt(priv); - } -#endif - - /* Session request/new session detected interrupt */ - -#ifdef CONFIG_USBDEV_VBUSSENSING - if ((regval & OTGFS_GINT_SRQ) != 0) - { - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SRQ), (uint16_t)regval); - stm32_sessioninterrupt(priv); - } - - /* OTG interrupt */ - - if ((regval & OTGFS_GINT_OTG) != 0) - { - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_OTG), (uint16_t)regval); - stm32_otginterrupt(priv); - } -#endif - } - - usbtrace(TRACE_INTEXIT(STM32_TRACEINTID_USB), 0); - return OK; -} - -/**************************************************************************** - * Endpoint operations - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_enablegonak - * - * Description: - * Enable global OUT NAK mode - * - ****************************************************************************/ - -static void stm32_enablegonak(struct stm32_ep_s *privep) -{ - uint32_t regval; - - /* First, make sure that there is no GNOAKEFF interrupt pending. */ - -#if 0 - stm32_putreg(OTGFS_GINT_GONAKEFF, STM32_OTGFS_GINTSTS); -#endif - - /* Enable Global OUT NAK mode in the core. */ - - regval = stm32_getreg(STM32_OTGFS_DCTL); - regval |= OTGFS_DCTL_SGONAK; - stm32_putreg(regval, STM32_OTGFS_DCTL); - -#if 0 - /* Wait for the GONAKEFF interrupt that indicates that the OUT NAK - * mode is in effect. When the interrupt handler pops the OUTNAK word - * from the RxFIFO, the core sets the GONAKEFF interrupt. - */ - - while ((stm32_getreg(STM32_OTGFS_GINTSTS) & OTGFS_GINT_GONAKEFF) == 0); - stm32_putreg(OTGFS_GINT_GONAKEFF, STM32_OTGFS_GINTSTS); - -#else - /* Since we are in the interrupt handler, we cannot wait inline for the - * GONAKEFF because it cannot occur until service the RXFLVL global - * interrupt and pop the OUTNAK word from the RxFIFO. - * - * Perhaps it is sufficient to wait for Global OUT NAK status to be - * reported in OTGFS DCTL register? - */ - - while ((stm32_getreg(STM32_OTGFS_DCTL) & OTGFS_DCTL_GONSTS) == 0); -#endif -} - -/**************************************************************************** - * Name: stm32_disablegonak - * - * Description: - * Disable global OUT NAK mode - * - ****************************************************************************/ - -static void stm32_disablegonak(struct stm32_ep_s *privep) -{ - uint32_t regval; - - /* Set the "Clear the Global OUT NAK bit" to disable global OUT NAK mode */ - - regval = stm32_getreg(STM32_OTGFS_DCTL); - regval |= OTGFS_DCTL_CGONAK; - stm32_putreg(regval, STM32_OTGFS_DCTL); -} - -/**************************************************************************** - * Name: stm32_epout_configure - * - * Description: - * Configure an OUT endpoint, making it usable - * - * Input Parameters: - * privep - a pointer to an internal endpoint structure - * eptype - The type of the endpoint - * maxpacket - The max packet size of the endpoint - * - ****************************************************************************/ - -static int stm32_epout_configure(struct stm32_ep_s *privep, - uint8_t eptype, - uint16_t maxpacket) -{ - uint32_t mpsiz; - uint32_t regaddr; - uint32_t regval; - - usbtrace(TRACE_EPCONFIGURE, privep->epphy); - - /* For EP0, the packet size is encoded */ - - if (privep->epphy == EP0) - { - DEBUGASSERT(eptype == USB_EP_ATTR_XFER_CONTROL); - - /* Map the size in bytes to the encoded value in the register */ - - switch (maxpacket) - { - case 8: - mpsiz = OTGFS_DOEPCTL0_MPSIZ_8; - break; - - case 16: - mpsiz = OTGFS_DOEPCTL0_MPSIZ_16; - break; - - case 32: - mpsiz = OTGFS_DOEPCTL0_MPSIZ_32; - break; - - case 64: - mpsiz = OTGFS_DOEPCTL0_MPSIZ_64; - break; - - default: - uerr("ERROR: Unsupported maxpacket: %d\n", maxpacket); - return -EINVAL; - } - } - - /* For other endpoints, the packet size is in bytes */ - - else - { - mpsiz = (maxpacket << OTGFS_DOEPCTL_MPSIZ_SHIFT); - } - - /* If the endpoint is already active don't change the endpoint control - * register. - */ - - regaddr = STM32_OTGFS_DOEPCTL(privep->epphy); - regval = stm32_getreg(regaddr); - if ((regval & OTGFS_DOEPCTL_USBAEP) == 0) - { - if (regval & OTGFS_DOEPCTL_NAKSTS) - { - regval |= OTGFS_DOEPCTL_CNAK; - } - - regval &= ~(OTGFS_DOEPCTL_MPSIZ_MASK | OTGFS_DOEPCTL_EPTYP_MASK); - regval |= mpsiz; - regval |= (eptype << OTGFS_DOEPCTL_EPTYP_SHIFT); - regval |= (OTGFS_DOEPCTL_SD0PID | OTGFS_DOEPCTL_USBAEP); - stm32_putreg(regval, regaddr); - - /* Save the endpoint configuration */ - - privep->ep.maxpacket = maxpacket; - privep->eptype = eptype; - privep->stalled = false; - privep->active = false; - privep->zlp = false; - } - - /* Enable the interrupt for this endpoint */ - - regval = stm32_getreg(STM32_OTGFS_DAINTMSK); - regval |= OTGFS_DAINT_OEP(privep->epphy); - stm32_putreg(regval, STM32_OTGFS_DAINTMSK); - return OK; -} - -/**************************************************************************** - * Name: stm32_epin_configure - * - * Description: - * Configure an IN endpoint, making it usable - * - * Input Parameters: - * privep - a pointer to an internal endpoint structure - * eptype - The type of the endpoint - * maxpacket - The max packet size of the endpoint - * - ****************************************************************************/ - -static int stm32_epin_configure(struct stm32_ep_s *privep, - uint8_t eptype, - uint16_t maxpacket) -{ - uint32_t mpsiz; - uint32_t regaddr; - uint32_t regval; - - usbtrace(TRACE_EPCONFIGURE, privep->epphy); - - /* For EP0, the packet size is encoded */ - - if (privep->epphy == EP0) - { - DEBUGASSERT(eptype == USB_EP_ATTR_XFER_CONTROL); - - /* Map the size in bytes to the encoded value in the register */ - - switch (maxpacket) - { - case 8: - mpsiz = OTGFS_DIEPCTL0_MPSIZ_8; - break; - - case 16: - mpsiz = OTGFS_DIEPCTL0_MPSIZ_16; - break; - - case 32: - mpsiz = OTGFS_DIEPCTL0_MPSIZ_32; - break; - - case 64: - mpsiz = OTGFS_DIEPCTL0_MPSIZ_64; - break; - - default: - uerr("ERROR: Unsupported maxpacket: %d\n", maxpacket); - return -EINVAL; - } - } - - /* For other endpoints, the packet size is in bytes */ - - else - { - mpsiz = (maxpacket << OTGFS_DIEPCTL_MPSIZ_SHIFT); - } - - /* If the endpoint is already active don't change the endpoint control - * register. - */ - - regaddr = STM32_OTGFS_DIEPCTL(privep->epphy); - regval = stm32_getreg(regaddr); - if ((regval & OTGFS_DIEPCTL_USBAEP) == 0) - { - if (regval & OTGFS_DIEPCTL_NAKSTS) - { - regval |= OTGFS_DIEPCTL_CNAK; - } - - regval &= ~(OTGFS_DIEPCTL_MPSIZ_MASK | OTGFS_DIEPCTL_EPTYP_MASK | - OTGFS_DIEPCTL_TXFNUM_MASK); - regval |= mpsiz; - regval |= (eptype << OTGFS_DIEPCTL_EPTYP_SHIFT); - regval |= (privep->epphy << OTGFS_DIEPCTL_TXFNUM_SHIFT); - regval |= (OTGFS_DIEPCTL_SD0PID | OTGFS_DIEPCTL_USBAEP); - stm32_putreg(regval, regaddr); - - /* Save the endpoint configuration */ - - privep->ep.maxpacket = maxpacket; - privep->eptype = eptype; - privep->stalled = false; - privep->active = false; - privep->zlp = false; - } - - /* Enable the interrupt for this endpoint */ - - regval = stm32_getreg(STM32_OTGFS_DAINTMSK); - regval |= OTGFS_DAINT_IEP(privep->epphy); - stm32_putreg(regval, STM32_OTGFS_DAINTMSK); - - return OK; -} - -/**************************************************************************** - * Name: stm32_ep_configure - * - * Description: - * Configure endpoint, making it usable - * - * Input Parameters: - * ep - the struct usbdev_ep_s instance obtained from allocep() - * desc - A struct usb_epdesc_s instance describing the endpoint - * last - true if this this last endpoint to be configured. Some hardware - * needs to take special action when all of the endpoints have been - * configured. - * - ****************************************************************************/ - -static int stm32_ep_configure(struct usbdev_ep_s *ep, - const struct usb_epdesc_s *desc, - bool last) -{ - struct stm32_ep_s *privep = (struct stm32_ep_s *)ep; - uint16_t maxpacket; - uint8_t eptype; - int ret; - - usbtrace(TRACE_EPCONFIGURE, privep->epphy); - DEBUGASSERT(desc->addr == ep->eplog); - - /* Initialize EP capabilities */ - - maxpacket = GETUINT16(desc->mxpacketsize); - eptype = desc->attr & USB_EP_ATTR_XFERTYPE_MASK; - - /* Setup Endpoint Control Register */ - - if (privep->isin) - { - ret = stm32_epin_configure(privep, eptype, maxpacket); - } - else - { - ret = stm32_epout_configure(privep, eptype, maxpacket); - } - - return ret; -} - -/**************************************************************************** - * Name: stm32_ep0_configure - * - * Description: - * Reset Usb engine - * - ****************************************************************************/ - -static void stm32_ep0_configure(struct stm32_usbdev_s *priv) -{ - /* Enable EP0 IN and OUT */ - - stm32_epin_configure(&priv->epin[EP0], USB_EP_ATTR_XFER_CONTROL, - CONFIG_USBDEV_EP0_MAXSIZE); - stm32_epout_configure(&priv->epout[EP0], USB_EP_ATTR_XFER_CONTROL, - CONFIG_USBDEV_EP0_MAXSIZE); -} - -/**************************************************************************** - * Name: stm32_epout_disable - * - * Description: - * Disable an OUT endpoint will no longer be used - * - ****************************************************************************/ - -static void stm32_epout_disable(struct stm32_ep_s *privep) -{ - uint32_t regaddr; - uint32_t regval; - irqstate_t flags; - - usbtrace(TRACE_EPDISABLE, privep->epphy); - - /* Is this an IN or an OUT endpoint */ - - /* Before disabling any OUT endpoint, the application must enable - * Global OUT NAK mode in the core. - */ - - flags = enter_critical_section(); - stm32_enablegonak(privep); - - /* Disable the required OUT endpoint by setting the EPDIS and SNAK bits - * int DOECPTL register. - */ - - regaddr = STM32_OTGFS_DOEPCTL(privep->epphy); - regval = stm32_getreg(regaddr); - regval &= ~OTGFS_DOEPCTL_USBAEP; - regval |= (OTGFS_DOEPCTL_EPDIS | OTGFS_DOEPCTL_SNAK); - stm32_putreg(regval, regaddr); - - /* Wait for the EPDISD interrupt which indicates that the OUT - * endpoint is completely disabled. - */ - -#if 0 /* Doesn't happen */ - regaddr = STM32_OTGFS_DOEPINT(privep->epphy); - while ((stm32_getreg(regaddr) & OTGFS_DOEPINT_EPDISD) == 0); -#else - /* REVISIT: */ - - up_udelay(10); -#endif - - /* Clear the EPDISD interrupt indication */ - - stm32_putreg(OTGFS_DOEPINT_EPDISD, STM32_OTGFS_DOEPINT(privep->epphy)); - - /* Then disable the Global OUT NAK mode to continue receiving data - * from other non-disabled OUT endpoints. - */ - - stm32_disablegonak(privep); - - /* Disable endpoint interrupts */ - - regval = stm32_getreg(STM32_OTGFS_DAINTMSK); - regval &= ~OTGFS_DAINT_OEP(privep->epphy); - stm32_putreg(regval, STM32_OTGFS_DAINTMSK); - - /* Cancel any queued read requests */ - - stm32_req_cancel(privep, -ESHUTDOWN); - - leave_critical_section(flags); -} - -/**************************************************************************** - * Name: stm32_epin_disable - * - * Description: - * Disable an IN endpoint when it will no longer be used - * - ****************************************************************************/ - -static void stm32_epin_disable(struct stm32_ep_s *privep) -{ - uint32_t regaddr; - uint32_t regval; - irqstate_t flags; - - usbtrace(TRACE_EPDISABLE, privep->epphy); - - /* After USB reset, the endpoint will already be deactivated by the - * hardware. Trying to disable again will just hang in the wait. - */ - - regaddr = STM32_OTGFS_DIEPCTL(privep->epphy); - regval = stm32_getreg(regaddr); - if ((regval & OTGFS_DIEPCTL_USBAEP) == 0) - { - return; - } - - /* This INEPNE wait logic is suggested by reference manual, but seems - * to get stuck to infinite loop. - */ - -#if 0 - /* Make sure that there is no pending IPEPNE interrupt (because we are - * to poll this bit below). - */ - - stm32_putreg(OTGFS_DIEPINT_INEPNE, STM32_OTGFS_DIEPINT(privep->epphy)); - - /* Set the endpoint in NAK mode */ - - regaddr = STM32_OTGFS_DIEPCTL(privep->epphy); - regval = stm32_getreg(regaddr); - regval &= ~OTGFS_DIEPCTL_USBAEP; - regval |= (OTGFS_DIEPCTL_EPDIS | OTGFS_DIEPCTL_SNAK); - stm32_putreg(regval, regaddr); - - /* Wait for the INEPNE interrupt that indicates that we are now in NAK - * mode - */ - - regaddr = STM32_OTGFS_DIEPINT(privep->epphy); - while ((stm32_getreg(regaddr) & OTGFS_DIEPINT_INEPNE) == 0); - - /* Clear the INEPNE interrupt indication */ - - stm32_putreg(OTGFS_DIEPINT_INEPNE, regaddr); -#endif - - /* Deactivate and disable the endpoint by setting the EPDIS and SNAK bits - * the DIEPCTLx register. - */ - - flags = enter_critical_section(); - regaddr = STM32_OTGFS_DIEPCTL(privep->epphy); - regval = stm32_getreg(regaddr); - regval &= ~OTGFS_DIEPCTL_USBAEP; - regval |= (OTGFS_DIEPCTL_EPDIS | OTGFS_DIEPCTL_SNAK); - stm32_putreg(regval, regaddr); - - /* Wait for the EPDISD interrupt which indicates that the IN - * endpoint is completely disabled. - */ - - regaddr = STM32_OTGFS_DIEPINT(privep->epphy); - while ((stm32_getreg(regaddr) & OTGFS_DIEPINT_EPDISD) == 0); - - /* Clear the EPDISD interrupt indication */ - - stm32_putreg(OTGFS_DIEPINT_EPDISD, stm32_getreg(regaddr)); - - /* Flush any data remaining in the TxFIFO */ - - stm32_txfifo_flush(OTGFS_GRSTCTL_TXFNUM_D(privep->epphy)); - - /* Disable endpoint interrupts */ - - regval = stm32_getreg(STM32_OTGFS_DAINTMSK); - regval &= ~OTGFS_DAINT_IEP(privep->epphy); - stm32_putreg(regval, STM32_OTGFS_DAINTMSK); - - /* Cancel any queued write requests */ - - stm32_req_cancel(privep, -ESHUTDOWN); - leave_critical_section(flags); -} - -/**************************************************************************** - * Name: stm32_ep_disable - * - * Description: - * The endpoint will no longer be used - * - ****************************************************************************/ - -static int stm32_ep_disable(struct usbdev_ep_s *ep) -{ - struct stm32_ep_s *privep = (struct stm32_ep_s *)ep; - -#ifdef CONFIG_DEBUG_FEATURES - if (!ep) - { - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); - return -EINVAL; - } -#endif - - usbtrace(TRACE_EPDISABLE, privep->epphy); - - /* Is this an IN or an OUT endpoint */ - - if (privep->isin) - { - /* Disable the IN endpoint */ - - stm32_epin_disable(privep); - } - else - { - /* Disable the OUT endpoint */ - - stm32_epout_disable(privep); - } - - return OK; -} - -/**************************************************************************** - * Name: stm32_ep_allocreq - * - * Description: - * Allocate an I/O request - * - ****************************************************************************/ - -static struct usbdev_req_s *stm32_ep_allocreq(struct usbdev_ep_s *ep) -{ - struct stm32_req_s *privreq; - -#ifdef CONFIG_DEBUG_FEATURES - if (!ep) - { - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); - return NULL; - } -#endif - - usbtrace(TRACE_EPALLOCREQ, ((struct stm32_ep_s *)ep)->epphy); - - privreq = kmm_malloc(sizeof(struct stm32_req_s)); - if (!privreq) - { - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_ALLOCFAIL), 0); - return NULL; - } - - memset(privreq, 0, sizeof(struct stm32_req_s)); - return &privreq->req; -} - -/**************************************************************************** - * Name: stm32_ep_freereq - * - * Description: - * Free an I/O request - * - ****************************************************************************/ - -static void stm32_ep_freereq(struct usbdev_ep_s *ep, - struct usbdev_req_s *req) -{ - struct stm32_req_s *privreq = (struct stm32_req_s *)req; - -#ifdef CONFIG_DEBUG_FEATURES - if (!ep || !req) - { - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); - return; - } -#endif - - usbtrace(TRACE_EPFREEREQ, ((struct stm32_ep_s *)ep)->epphy); - kmm_free(privreq); -} - -/**************************************************************************** - * Name: stm32_ep_allocbuffer - * - * Description: - * Allocate an I/O buffer - * - ****************************************************************************/ - -#ifdef CONFIG_USBDEV_DMA -static void *stm32_ep_allocbuffer(struct usbdev_ep_s *ep, uint16_t bytes) -{ - usbtrace(TRACE_EPALLOCBUFFER, ((struct stm32_ep_s *)ep)->epphy); - -#ifdef CONFIG_USBDEV_DMAMEMORY - return usbdev_dma_alloc(bytes); -#else - return kmm_malloc(bytes); -#endif -} -#endif - -/**************************************************************************** - * Name: stm32_ep_freebuffer - * - * Description: - * Free an I/O buffer - * - ****************************************************************************/ - -#ifdef CONFIG_USBDEV_DMA -static void stm32_ep_freebuffer(struct usbdev_ep_s *ep, void *buf) -{ - usbtrace(TRACE_EPALLOCBUFFER, ((struct stm32_ep_s *)ep)->epphy); - -#ifdef CONFIG_USBDEV_DMAMEMORY - usbdev_dma_free(buf); -#else - kmm_free(buf); -#endif -} -#endif - -/**************************************************************************** - * Name: stm32_ep_submit - * - * Description: - * Submit an I/O request to the endpoint - * - ****************************************************************************/ - -static int stm32_ep_submit(struct usbdev_ep_s *ep, - struct usbdev_req_s *req) -{ - struct stm32_req_s *privreq = (struct stm32_req_s *)req; - struct stm32_ep_s *privep = (struct stm32_ep_s *)ep; - struct stm32_usbdev_s *priv; - irqstate_t flags; - int ret = OK; - - /* Some sanity checking */ - -#ifdef CONFIG_DEBUG_FEATURES - if (!req || !req->callback || !req->buf || !ep) - { - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); - uinfo("req=%p callback=%p buf=%p ep=%p\n", req, req->callback, - req->buf, ep); - return -EINVAL; - } -#endif - - usbtrace(TRACE_EPSUBMIT, privep->epphy); - priv = privep->dev; - -#ifdef CONFIG_DEBUG_FEATURES - if (!priv->driver) - { - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_NOTCONFIGURED), - priv->usbdev.speed); - return -ESHUTDOWN; - } -#endif - - /* Handle the request from the class driver */ - - req->result = -EINPROGRESS; - req->xfrd = 0; - - /* Disable Interrupts */ - - flags = enter_critical_section(); - - /* If we are stalled, then drop all requests on the floor */ - - if (privep->stalled) - { - ret = -EBUSY; - } - else - { - /* Add the new request to the request queue for the endpoint. */ - - if (stm32_req_addlast(privep, privreq) && !privep->active) - { - /* If a request was added to an IN endpoint, then attempt to send - * the request data buffer now. - */ - - if (privep->isin) - { - usbtrace(TRACE_INREQQUEUED(privep->epphy), privreq->req.len); - - /* If the endpoint is not busy with another write request, - * then process the newly received write request now. - */ - - if (!privep->active) - { - stm32_epin_request(priv, privep); - } - } - - /* If the request was added to an OUT endpoint, then attempt to - * setup a read into the request data buffer now (this will, of - * course, fail if there is already a read in place). - */ - - else - { - usbtrace(TRACE_OUTREQQUEUED(privep->epphy), privreq->req.len); - stm32_epout_request(priv, privep); - } - } - } - - leave_critical_section(flags); - return ret; -} - -/**************************************************************************** - * Name: stm32_ep_cancel - * - * Description: - * Cancel an I/O request previously sent to an endpoint - * - ****************************************************************************/ - -static int stm32_ep_cancel(struct usbdev_ep_s *ep, - struct usbdev_req_s *req) -{ - struct stm32_ep_s *privep = (struct stm32_ep_s *)ep; - irqstate_t flags; - -#ifdef CONFIG_DEBUG_FEATURES - if (!ep || !req) - { - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); - return -EINVAL; - } -#endif - - usbtrace(TRACE_EPCANCEL, privep->epphy); - - flags = enter_critical_section(); - - /* FIXME: if the request is the first, then we need to flush the EP - * otherwise just remove it from the list - * - * but ... all other implementations cancel all requests ... - */ - - stm32_req_cancel(privep, -ESHUTDOWN); - leave_critical_section(flags); - return OK; -} - -/**************************************************************************** - * Name: stm32_epout_setstall - * - * Description: - * Stall an OUT endpoint - * - ****************************************************************************/ - -static int stm32_epout_setstall(struct stm32_ep_s *privep) -{ -#if 1 - /* This implementation follows the requirements from the STM32 F4 reference - * manual. - */ - - uint32_t regaddr; - uint32_t regval; - - /* Put the core in the Global OUT NAK mode */ - - stm32_enablegonak(privep); - - /* Disable and STALL the OUT endpoint by setting the EPDIS and STALL bits - * in the DOECPTL register. - */ - - regaddr = STM32_OTGFS_DOEPCTL(privep->epphy); - regval = stm32_getreg(regaddr); - regval |= (OTGFS_DOEPCTL_EPDIS | OTGFS_DOEPCTL_STALL); - stm32_putreg(regval, regaddr); - - /* Wait for the EPDISD interrupt which indicates that the OUT - * endpoint is completely disabled. - */ - -#if 0 /* Doesn't happen */ - regaddr = STM32_OTGFS_DOEPINT(privep->epphy); - while ((stm32_getreg(regaddr) & OTGFS_DOEPINT_EPDISD) == 0); -#else - /* REVISIT: */ - - up_udelay(10); -#endif - - /* Disable Global OUT NAK mode */ - - stm32_disablegonak(privep); - - /* The endpoint is now stalled */ - - privep->stalled = true; - return OK; -#else - /* This implementation follows the STMicro code example. */ - - /* REVISIT: */ - - uint32_t regaddr; - uint32_t regval; - - /* Stall the OUT endpoint by setting the STALL bit in the DOECPTL - * register. - */ - - regaddr = STM32_OTGFS_DOEPCTL(privep->epphy); - regval = stm32_getreg(regaddr); - regval |= OTGFS_DOEPCTL_STALL; - stm32_putreg(regval, regaddr); - - /* The endpoint is now stalled */ - - privep->stalled = true; - return OK; -#endif -} - -/**************************************************************************** - * Name: stm32_epin_setstall - * - * Description: - * Stall an IN endpoint - * - ****************************************************************************/ - -static int stm32_epin_setstall(struct stm32_ep_s *privep) -{ - uint32_t regaddr; - uint32_t regval; - - /* Get the IN endpoint device control register */ - - regaddr = STM32_OTGFS_DIEPCTL(privep->epphy); - regval = stm32_getreg(regaddr); - - /* Then stall the endpoint */ - - regval |= OTGFS_DIEPCTL_STALL; - stm32_putreg(regval, regaddr); - - /* The endpoint is now stalled */ - - privep->stalled = true; - return OK; -} - -/**************************************************************************** - * Name: stm32_ep_setstall - * - * Description: - * Stall an endpoint - * - ****************************************************************************/ - -static int stm32_ep_setstall(struct stm32_ep_s *privep) -{ - usbtrace(TRACE_EPSTALL, privep->epphy); - - /* Is this an IN endpoint? */ - - if (privep->isin == 1) - { - return stm32_epin_setstall(privep); - } - else - { - return stm32_epout_setstall(privep); - } -} - -/**************************************************************************** - * Name: stm32_ep_clrstall - * - * Description: - * Resume a stalled endpoint - * - ****************************************************************************/ - -static int stm32_ep_clrstall(struct stm32_ep_s *privep) -{ - uint32_t regaddr; - uint32_t regval; - uint32_t stallbit; - uint32_t data0bit; - - usbtrace(TRACE_EPRESUME, privep->epphy); - - /* Is this an IN endpoint? */ - - if (privep->isin == 1) - { - /* Clear the stall bit in the IN endpoint device control register */ - - regaddr = STM32_OTGFS_DIEPCTL(privep->epphy); - stallbit = OTGFS_DIEPCTL_STALL; - data0bit = OTGFS_DIEPCTL_SD0PID; - } - else - { - /* Clear the stall bit in the IN endpoint device control register */ - - regaddr = STM32_OTGFS_DOEPCTL(privep->epphy); - stallbit = OTGFS_DOEPCTL_STALL; - data0bit = OTGFS_DOEPCTL_SD0PID; - } - - /* Clear the stall bit */ - - regval = stm32_getreg(regaddr); - regval &= ~stallbit; - - /* Set the DATA0 pid for interrupt and bulk endpoints */ - - if (privep->eptype == USB_EP_ATTR_XFER_INT || - privep->eptype == USB_EP_ATTR_XFER_BULK) - { - /* Writing this bit sets the DATA0 PID */ - - regval |= data0bit; - } - - stm32_putreg(regval, regaddr); - - /* The endpoint is no longer stalled */ - - privep->stalled = false; - return OK; -} - -/**************************************************************************** - * Name: stm32_ep_stall - * - * Description: - * Stall or resume an endpoint - * - ****************************************************************************/ - -static int stm32_ep_stall(struct usbdev_ep_s *ep, bool resume) -{ - struct stm32_ep_s *privep = (struct stm32_ep_s *)ep; - irqstate_t flags; - int ret; - - /* Set or clear the stall condition as requested */ - - flags = enter_critical_section(); - if (resume) - { - ret = stm32_ep_clrstall(privep); - } - else - { - ret = stm32_ep_setstall(privep); - } - - leave_critical_section(flags); - - return ret; -} - -/**************************************************************************** - * Name: stm32_ep0_stall - * - * Description: - * Stall endpoint 0 - * - ****************************************************************************/ - -static void stm32_ep0_stall(struct stm32_usbdev_s *priv) -{ - stm32_epin_setstall(&priv->epin[EP0]); - stm32_epout_setstall(&priv->epout[EP0]); - priv->stalled = true; - stm32_ep0out_ctrlsetup(priv); -} - -/**************************************************************************** - * Device operations - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_ep_alloc - * - * Description: - * Allocate an endpoint matching the parameters. - * - * Input Parameters: - * eplog - 7-bit logical endpoint number (direction bit ignored). - * Zero means that any endpoint matching the other requirements - * will suffice. The assigned endpoint can be found in the eplog - * field. - * in - true: IN (device-to-host) endpoint requested - * eptype - Endpoint type. One of {USB_EP_ATTR_XFER_ISOC, - * USB_EP_ATTR_XFER_BULK, USB_EP_ATTR_XFER_INT} - * - ****************************************************************************/ - -static struct usbdev_ep_s *stm32_ep_alloc(struct usbdev_s *dev, - uint8_t eplog, bool in, - uint8_t eptype) -{ - struct stm32_usbdev_s *priv = (struct stm32_usbdev_s *)dev; - uint8_t epavail; - irqstate_t flags; - int epphy; - int epno = 0; - - usbtrace(TRACE_DEVALLOCEP, (uint16_t)eplog); - - /* Ignore any direction bits in the logical address */ - - epphy = USB_EPNO(eplog); - - /* Get the set of available endpoints depending on the direction */ - - flags = enter_critical_section(); - epavail = priv->epavail[in]; - - /* A physical address of 0 means that any endpoint will do */ - - if (epphy > 0) - { - /* Otherwise, we will return the endpoint structure only for the - * requested 'logical' endpoint. All of the other checks will still - * be performed. - * - * First, verify that the logical endpoint is in the range supported by - * by the hardware. - */ - - if (epphy >= STM32_NENDPOINTS) - { - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADEPNO), (uint16_t)epphy); - return NULL; - } - - /* Remove all of the candidate endpoints from the bitset except for the - * this physical endpoint number. - */ - - epavail &= (1 << epphy); - } - - /* Is there an available endpoint? */ - - if (epavail) - { - /* Yes.. Select the lowest numbered endpoint in the set of available - * endpoints. - */ - - for (epno = 1; epno < STM32_NENDPOINTS; epno++) - { - uint8_t bit = 1 << epno; - if ((epavail & bit) != 0) - { - /* Mark the endpoint no longer available */ - - priv->epavail[in] &= ~(1 << epno); - - /* And return the pointer to the standard endpoint structure */ - - leave_critical_section(flags); - return in ? &priv->epin[epno].ep : &priv->epout[epno].ep; - } - } - - /* We should not get here */ - } - - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_NOEP), (uint16_t)eplog); - leave_critical_section(flags); - return NULL; -} - -/**************************************************************************** - * Name: stm32_ep_free - * - * Description: - * Free the previously allocated endpoint - * - ****************************************************************************/ - -static void stm32_ep_free(struct usbdev_s *dev, - struct usbdev_ep_s *ep) -{ - struct stm32_usbdev_s *priv = (struct stm32_usbdev_s *)dev; - struct stm32_ep_s *privep = (struct stm32_ep_s *)ep; - irqstate_t flags; - - usbtrace(TRACE_DEVFREEEP, (uint16_t)privep->epphy); - - if (priv && privep) - { - /* Mark the endpoint as available */ - - flags = enter_critical_section(); - priv->epavail[privep->isin] |= (1 << privep->epphy); - leave_critical_section(flags); - } -} - -/**************************************************************************** - * Name: stm32_getframe - * - * Description: - * Returns the current frame number - * - ****************************************************************************/ - -static int stm32_getframe(struct usbdev_s *dev) -{ - uint32_t regval; - - usbtrace(TRACE_DEVGETFRAME, 0); - - /* Return the last frame number of the last SOF detected by the hardware */ - - regval = stm32_getreg(STM32_OTGFS_DSTS); - return (int)((regval & OTGFS_DSTS_SOFFN_MASK) >> OTGFS_DSTS_SOFFN_SHIFT); -} - -/**************************************************************************** - * Name: stm32_wakeup - * - * Description: - * Exit suspend mode. - * - ****************************************************************************/ - -static int stm32_wakeup(struct usbdev_s *dev) -{ - struct stm32_usbdev_s *priv = (struct stm32_usbdev_s *)dev; - uint32_t regval; - irqstate_t flags; - - usbtrace(TRACE_DEVWAKEUP, 0); - - /* Is wakeup enabled? */ - - flags = enter_critical_section(); - if (priv->wakeup) - { - /* Yes... is the core suspended? */ - - regval = stm32_getreg(STM32_OTGFS_DSTS); - if ((regval & OTGFS_DSTS_SUSPSTS) != 0) - { - /* Re-start the PHY clock and un-gate USB core clock (HCLK) */ - -#ifdef CONFIG_USBDEV_LOWPOWER - regval = stm32_getreg(STM32_OTGFS_PCGCCTL); - regval &= ~(OTGFS_PCGCCTL_STPPCLK | OTGFS_PCGCCTL_GATEHCLK); - stm32_putreg(regval, STM32_OTGFS_PCGCCTL); -#endif - /* Activate Remote wakeup signaling */ - - regval = stm32_getreg(STM32_OTGFS_DCTL); - regval |= OTGFS_DCTL_RWUSIG; - stm32_putreg(regval, STM32_OTGFS_DCTL); - up_mdelay(5); - regval &= ~OTGFS_DCTL_RWUSIG; - stm32_putreg(regval, STM32_OTGFS_DCTL); - } - } - - leave_critical_section(flags); - return OK; -} - -/**************************************************************************** - * Name: stm32_selfpowered - * - * Description: - * Sets/clears the device self-powered feature - * - ****************************************************************************/ - -static int stm32_selfpowered(struct usbdev_s *dev, bool selfpowered) -{ - struct stm32_usbdev_s *priv = (struct stm32_usbdev_s *)dev; - - usbtrace(TRACE_DEVSELFPOWERED, (uint16_t)selfpowered); - -#ifdef CONFIG_DEBUG_FEATURES - if (!dev) - { - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); - return -ENODEV; - } -#endif - - priv->selfpowered = selfpowered; - return OK; -} - -/**************************************************************************** - * Name: stm32_pullup - * - * Description: - * Software-controlled connect to/disconnect from USB host - * - ****************************************************************************/ - -static int stm32_pullup(struct usbdev_s *dev, bool enable) -{ - uint32_t regval; - - usbtrace(TRACE_DEVPULLUP, (uint16_t)enable); - - irqstate_t flags = enter_critical_section(); - regval = stm32_getreg(STM32_OTGFS_DCTL); - if (enable) - { - /* Connect the device by clearing the soft disconnect bit in the DCTL - * register - */ - - regval &= ~OTGFS_DCTL_SDIS; - } - else - { - /* Connect the device by setting the soft disconnect bit in the DCTL - * register - */ - - regval |= OTGFS_DCTL_SDIS; - } - - stm32_putreg(regval, STM32_OTGFS_DCTL); - leave_critical_section(flags); - return OK; -} - -/**************************************************************************** - * Name: stm32_setaddress - * - * Description: - * Set the devices USB address - * - ****************************************************************************/ - -static void stm32_setaddress(struct stm32_usbdev_s *priv, uint16_t address) -{ - uint32_t regval; - - /* Set the device address in the DCFG register */ - - regval = stm32_getreg(STM32_OTGFS_DCFG); - regval &= ~OTGFS_DCFG_DAD_MASK; - regval |= ((uint32_t)address << OTGFS_DCFG_DAD_SHIFT); - stm32_putreg(regval, STM32_OTGFS_DCFG); - - /* Are we now addressed? (i.e., do we have a non-NULL device - * address?) - */ - - if (address != 0) - { - priv->devstate = DEVSTATE_ADDRESSED; - priv->addressed = true; - } - else - { - priv->devstate = DEVSTATE_DEFAULT; - priv->addressed = false; - } -} - -/**************************************************************************** - * Name: stm32_txfifo_flush - * - * Description: - * Flush the specific TX fifo. - * - ****************************************************************************/ - -static int stm32_txfifo_flush(uint32_t txfnum) -{ - uint32_t regval; - uint32_t timeout; - - /* Initiate the TX FIFO flush operation */ - - regval = OTGFS_GRSTCTL_TXFFLSH | txfnum; - stm32_putreg(regval, STM32_OTGFS_GRSTCTL); - - /* Wait for the FLUSH to complete */ - - for (timeout = 0; timeout < STM32_FLUSH_DELAY; timeout++) - { - regval = stm32_getreg(STM32_OTGFS_GRSTCTL); - if ((regval & OTGFS_GRSTCTL_TXFFLSH) == 0) - { - break; - } - } - - /* Wait for 3 PHY Clocks */ - - up_udelay(3); - return OK; -} - -/**************************************************************************** - * Name: stm32_rxfifo_flush - * - * Description: - * Flush the RX fifo. - * - ****************************************************************************/ - -static int stm32_rxfifo_flush(void) -{ - uint32_t regval; - uint32_t timeout; - - /* Initiate the RX FIFO flush operation */ - - stm32_putreg(OTGFS_GRSTCTL_RXFFLSH, STM32_OTGFS_GRSTCTL); - - /* Wait for the FLUSH to complete */ - - for (timeout = 0; timeout < STM32_FLUSH_DELAY; timeout++) - { - regval = stm32_getreg(STM32_OTGFS_GRSTCTL); - if ((regval & OTGFS_GRSTCTL_RXFFLSH) == 0) - { - break; - } - } - - /* Wait for 3 PHY Clocks */ - - up_udelay(3); - return OK; -} - -/**************************************************************************** - * Name: stm32_swinitialize - * - * Description: - * Initialize all driver data structures. - * - ****************************************************************************/ - -static void stm32_swinitialize(struct stm32_usbdev_s *priv) -{ - struct stm32_ep_s *privep; - int i; - - /* Initialize the device state structure */ - - memset(priv, 0, sizeof(struct stm32_usbdev_s)); - - priv->usbdev.ops = &g_devops; - priv->usbdev.ep0 = &priv->epin[EP0].ep; - - priv->epavail[0] = STM32_EP_AVAILABLE; - priv->epavail[1] = STM32_EP_AVAILABLE; - - /* Initialize the endpoint lists */ - - for (i = 0; i < STM32_NENDPOINTS; i++) - { - /* Set endpoint operations, reference to driver structure (not - * really necessary because there is only one controller), and - * the physical endpoint number (which is just the index to the - * endpoint). - */ - - privep = &priv->epin[i]; - privep->ep.ops = &g_epops; - privep->dev = priv; - privep->isin = 1; - - /* The index, i, is the physical endpoint address; Map this - * to a logical endpoint address usable by the class driver. - */ - - privep->epphy = i; - privep->ep.eplog = STM32_EPPHYIN2LOG(i); - - /* Control until endpoint is activated */ - - privep->eptype = USB_EP_ATTR_XFER_CONTROL; - privep->ep.maxpacket = CONFIG_USBDEV_EP0_MAXSIZE; - } - - /* Initialize the endpoint lists */ - - for (i = 0; i < STM32_NENDPOINTS; i++) - { - /* Set endpoint operations, reference to driver structure (not - * really necessary because there is only one controller), and - * the physical endpoint number (which is just the index to the - * endpoint). - */ - - privep = &priv->epout[i]; - privep->ep.ops = &g_epops; - privep->dev = priv; - - /* The index, i, is the physical endpoint address; Map this - * to a logical endpoint address usable by the class driver. - */ - - privep->epphy = i; - privep->ep.eplog = STM32_EPPHYOUT2LOG(i); - - /* Control until endpoint is activated */ - - privep->eptype = USB_EP_ATTR_XFER_CONTROL; - privep->ep.maxpacket = CONFIG_USBDEV_EP0_MAXSIZE; - } -} - -/**************************************************************************** - * Name: stm32_hwinitialize - * - * Description: - * Configure the OTG FS core for operation. - * - ****************************************************************************/ - -static void stm32_hwinitialize(struct stm32_usbdev_s *priv) -{ - uint32_t regval; - uint32_t timeout; - uint32_t address; - int i; - - /* At start-up the core is in FS mode. */ - - /* Disable global interrupts by clearing the GINTMASK bit in the GAHBCFG - * register; Set the TXFELVL bit in the GAHBCFG register so that TxFIFO - * interrupts will occur when the TxFIFO is truly empty (not just half - * full). - */ - - stm32_putreg(OTGFS_GAHBCFG_TXFELVL, STM32_OTGFS_GAHBCFG); - - /* Common USB OTG core initialization */ - - /* Reset after a PHY select and set Host mode. First, wait for AHB master - * IDLE state. - */ - - for (timeout = 0; timeout < STM32_READY_DELAY; timeout++) - { - up_udelay(3); - regval = stm32_getreg(STM32_OTGFS_GRSTCTL); - if ((regval & OTGFS_GRSTCTL_AHBIDL) != 0) - { - break; - } - } - - /* Then perform the core soft reset. */ - - stm32_putreg(OTGFS_GRSTCTL_CSRST, STM32_OTGFS_GRSTCTL); - for (timeout = 0; timeout < STM32_READY_DELAY; timeout++) - { - regval = stm32_getreg(STM32_OTGFS_GRSTCTL); - if ((regval & OTGFS_GRSTCTL_CSRST) == 0) - { - break; - } - } - - /* Wait for 3 PHY Clocks */ - - up_udelay(3); - - /* Deactivate the power down */ - -#if defined(CONFIG_STM32_STM32F446) || defined(CONFIG_STM32_STM32F469) - /* In the case of the STM32F446 or STM32F469 the meaning of the bit - * has changed to VBUS Detection Enable when set - */ - - regval = OTGFS_GCCFG_PWRDWN; - -# ifdef CONFIG_USBDEV_VBUSSENSING - regval |= OTGFS_GCCFG_VBDEN; -# endif - -#else - /* In the case of the all others the meaning of the bit is No VBUS - * Sense when Set - */ - - regval = (OTGFS_GCCFG_PWRDWN | OTGFS_GCCFG_VBUSASEN | - OTGFS_GCCFG_VBUSBSEN); -# ifndef CONFIG_USBDEV_VBUSSENSING - regval |= OTGFS_GCCFG_NOVBUSSENS; -# endif -# ifdef CONFIG_STM32_OTGFS_SOFOUTPUT - regval |= OTGFS_GCCFG_SOFOUTEN; -# endif -#endif - stm32_putreg(regval, STM32_OTGFS_GCCFG); - up_mdelay(20); - - /* For the new OTG controller in the F446, F469 when VBUS sensing is not - * used we need to force the B session valid - */ - -#if defined(CONFIG_STM32_STM32F446) || defined(CONFIG_STM32_STM32F469) -# ifndef CONFIG_USBDEV_VBUSSENSING - regval = stm32_getreg(STM32_OTGFS_GOTGCTL); - regval |= (OTGFS_GOTGCTL_BVALOEN | OTGFS_GOTGCTL_BVALOVAL); - stm32_putreg(regval, STM32_OTGFS_GOTGCTL); -# endif -#endif - - /* Force Device Mode */ - - regval = stm32_getreg(STM32_OTGFS_GUSBCFG); - regval &= ~OTGFS_GUSBCFG_FHMOD; - regval |= OTGFS_GUSBCFG_FDMOD; - stm32_putreg(regval, STM32_OTGFS_GUSBCFG); - up_mdelay(50); - - /* Initialize device mode */ - - /* Restart the PHY Clock */ - - stm32_putreg(0, STM32_OTGFS_PCGCCTL); - - /* Device configuration register */ - - regval = stm32_getreg(STM32_OTGFS_DCFG); - regval &= ~OTGFS_DCFG_PFIVL_MASK; - regval |= OTGFS_DCFG_PFIVL_80PCT; - stm32_putreg(regval, STM32_OTGFS_DCFG); - - /* Set full speed PHY */ - - regval = stm32_getreg(STM32_OTGFS_DCFG); - regval &= ~OTGFS_DCFG_DSPD_MASK; - regval |= OTGFS_DCFG_DSPD_FS; - stm32_putreg(regval, STM32_OTGFS_DCFG); - - /* Set Rx FIFO size */ - - stm32_putreg(STM32_RXFIFO_WORDS, STM32_OTGFS_GRXFSIZ); - - /* EP0 TX */ - - address = STM32_RXFIFO_WORDS; - regval = (address << OTGFS_DIEPTXF0_TX0FD_SHIFT) | - (STM32_EP0_TXFIFO_WORDS << OTGFS_DIEPTXF0_TX0FSA_SHIFT); - stm32_putreg(regval, STM32_OTGFS_DIEPTXF0); - - /* EP1 TX */ - - address += STM32_EP0_TXFIFO_WORDS; - regval = (address << OTGFS_DIEPTXF_INEPTXSA_SHIFT) | - (STM32_EP1_TXFIFO_WORDS << OTGFS_DIEPTXF_INEPTXFD_SHIFT); - stm32_putreg(regval, STM32_OTGFS_DIEPTXF1); - - /* EP2 TX */ - - address += STM32_EP1_TXFIFO_WORDS; - regval = (address << OTGFS_DIEPTXF_INEPTXSA_SHIFT) | - (STM32_EP2_TXFIFO_WORDS << OTGFS_DIEPTXF_INEPTXFD_SHIFT); - stm32_putreg(regval, STM32_OTGFS_DIEPTXF2); - - /* EP3 TX */ - - address += STM32_EP2_TXFIFO_WORDS; - regval = (address << OTGFS_DIEPTXF_INEPTXSA_SHIFT) | - (STM32_EP3_TXFIFO_WORDS << OTGFS_DIEPTXF_INEPTXFD_SHIFT); - stm32_putreg(regval, STM32_OTGFS_DIEPTXF3); - - /* Flush the FIFOs */ - - stm32_txfifo_flush(OTGFS_GRSTCTL_TXFNUM_DALL); - stm32_rxfifo_flush(); - - /* Clear all pending Device Interrupts */ - - stm32_putreg(0, STM32_OTGFS_DIEPMSK); - stm32_putreg(0, STM32_OTGFS_DOEPMSK); - stm32_putreg(0, STM32_OTGFS_DIEPEMPMSK); - stm32_putreg(0xffffffff, STM32_OTGFS_DAINT); - stm32_putreg(0, STM32_OTGFS_DAINTMSK); - - /* Configure all IN endpoints */ - - for (i = 0; i < STM32_NENDPOINTS; i++) - { - regval = stm32_getreg(STM32_OTGFS_DIEPCTL(i)); - if ((regval & OTGFS_DIEPCTL_EPENA) != 0) - { - /* The endpoint is already enabled */ - - regval = OTGFS_DIEPCTL_EPENA | OTGFS_DIEPCTL_SNAK; - } - else - { - regval = 0; - } - - stm32_putreg(regval, STM32_OTGFS_DIEPCTL(i)); - stm32_putreg(0, STM32_OTGFS_DIEPTSIZ(i)); - stm32_putreg(0xff, STM32_OTGFS_DIEPINT(i)); - } - - /* Configure all OUT endpoints */ - - for (i = 0; i < STM32_NENDPOINTS; i++) - { - regval = stm32_getreg(STM32_OTGFS_DOEPCTL(i)); - if ((regval & OTGFS_DOEPCTL_EPENA) != 0) - { - /* The endpoint is already enabled */ - - regval = OTGFS_DOEPCTL_EPENA | OTGFS_DOEPCTL_SNAK; - } - else - { - regval = 0; - } - - stm32_putreg(regval, STM32_OTGFS_DOEPCTL(i)); - stm32_putreg(0, STM32_OTGFS_DOEPTSIZ(i)); - stm32_putreg(0xff, STM32_OTGFS_DOEPINT(i)); - } - - /* Disable all interrupts. */ - - stm32_putreg(0, STM32_OTGFS_GINTMSK); - - /* Clear any pending USB_OTG Interrupts */ - - stm32_putreg(0xffffffff, STM32_OTGFS_GOTGINT); - - /* Clear any pending interrupts */ - - regval = stm32_getreg(STM32_OTGFS_GINTSTS); - regval &= OTGFS_GINT_RESERVED; - stm32_putreg(regval | OTGFS_GINT_RC_W1, STM32_OTGFS_GINTSTS); - - /* Enable the interrupts in the INTMSK */ - - regval = (OTGFS_GINT_RXFLVL | OTGFS_GINT_USBSUSP | OTGFS_GINT_ENUMDNE | - OTGFS_GINT_IEP | OTGFS_GINT_OEP | OTGFS_GINT_USBRST); - -#ifdef CONFIG_USBDEV_ISOCHRONOUS - regval |= (OTGFS_GINT_IISOIXFR | OTGFS_GINT_IISOOXFR); -#endif - -#ifdef CONFIG_USBDEV_SOFINTERRUPT - regval |= OTGFS_GINT_SOF; -#endif - -#ifdef CONFIG_USBDEV_VBUSSENSING - regval |= (OTGFS_GINT_OTG | OTGFS_GINT_SRQ); -#endif - -#ifdef CONFIG_DEBUG_USB - regval |= OTGFS_GINT_MMIS; -#endif - - stm32_putreg(regval, STM32_OTGFS_GINTMSK); - - /* Enable the USB global interrupt by setting GINTMSK in the global OTG - * FS AHB configuration register; Set the TXFELVL bit in the GAHBCFG - * register so that TxFIFO interrupts will occur when the TxFIFO is truly - * empty (not just half full). - */ - - stm32_putreg(OTGFS_GAHBCFG_GINTMSK | OTGFS_GAHBCFG_TXFELVL, - STM32_OTGFS_GAHBCFG); -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: arm_usbinitialize - * - * Description: - * Initialize USB hardware. - * - * Assumptions: - * - This function is called very early in the initialization sequence - * - PLL and GIO pin initialization is not performed here but should been in - * the low-level boot logic: PLL1 must be configured for operation at - * 48MHz and P0.23 and PO.31 in PINSEL1 must be configured for Vbus and - * USB connect LED. - * - ****************************************************************************/ - -void arm_usbinitialize(void) -{ - /* At present, there is only a single OTG FS device support. Hence it is - * pre-allocated as g_otgfsdev. However, in most code, the private data - * structure will be referenced using the 'priv' pointer (rather than the - * global data) in order to simplify any future support for multiple - * devices. - */ - - struct stm32_usbdev_s *priv = &g_otgfsdev; - int ret; - - usbtrace(TRACE_DEVINIT, 0); - - /* Here we assume that: - * - * 1. GPIOA and OTG FS peripheral clocking has already been enabled as part - * of the boot sequence. - * 2. Board-specific logic has already enabled other board specific GPIOs - * for things like soft pull-up, VBUS sensing, power controls, and over- - * current detection. - */ - - /* Configure OTG FS alternate function pins - * - * PIN* SIGNAL DIRECTION - * ---- ----------- ---------- - * PA8 OTG_FS_SOF SOF clock output - * PA9 OTG_FS_VBUS VBUS input for device, Driven by external regulator by - * host (not an alternate function) - * PA10 OTG_FS_ID OTG ID pin (only needed in Dual mode) - * PA11 OTG_FS_DM D- I/O - * PA12 OTG_FS_DP D+ I/O - * - * *Pins may vary from device-to-device. - */ - - stm32_configgpio(GPIO_OTGFS_DM); - stm32_configgpio(GPIO_OTGFS_DP); - - /* Only needed for OTG */ -#ifndef CONFIG_OTG_ID_GPIO_DISABLE - stm32_configgpio(GPIO_OTGFS_ID); -#endif - - /* SOF output pin configuration is configurable. */ - -#ifdef CONFIG_STM32_OTGFS_SOFOUTPUT - stm32_configgpio(GPIO_OTGFS_SOF); -#endif - - /* Uninitialize the hardware so that we know that we are starting from a - * known state. - */ - - arm_usbuninitialize(); - - /* Initialize the driver data structure */ - - stm32_swinitialize(priv); - - /* Attach the OTG FS interrupt handler */ - - ret = irq_attach(STM32_IRQ_OTGFS, stm32_usbinterrupt, NULL); - if (ret < 0) - { - uerr("ERROR: irq_attach failed: %d\n", ret); - goto errout; - } - - /* Initialize the USB OTG core */ - - stm32_hwinitialize(priv); - - /* Disconnect device */ - - stm32_pullup(&priv->usbdev, false); - - /* Reset/Re-initialize the USB hardware */ - - stm32_usbreset(priv); - - /* Enable USB controller interrupts at the NVIC */ - - up_enable_irq(STM32_IRQ_OTGFS); - return; - -errout: - arm_usbuninitialize(); -} - -/**************************************************************************** - * Name: arm_usbuninitialize - ****************************************************************************/ - -void arm_usbuninitialize(void) -{ - /* At present, there is only a single OTG FS device support. Hence it is - * pre-allocated as g_otgfsdev. However, in most code, the private data - * structure will be referenced using the 'priv' pointer (rather than the - * global data) in order to simplify any future support for multiple - * devices. - */ - - struct stm32_usbdev_s *priv = &g_otgfsdev; - irqstate_t flags; - int i; - - usbtrace(TRACE_DEVUNINIT, 0); - - if (priv->driver) - { - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_DRIVERREGISTERED), 0); - usbdev_unregister(priv->driver); - } - - /* Disconnect device */ - - flags = enter_critical_section(); - stm32_pullup(&priv->usbdev, false); - priv->usbdev.speed = USB_SPEED_UNKNOWN; - - /* Disable and detach IRQs */ - - up_disable_irq(STM32_IRQ_OTGFS); - irq_detach(STM32_IRQ_OTGFS); - - /* Disable all endpoint interrupts */ - - for (i = 0; i < STM32_NENDPOINTS; i++) - { - stm32_putreg(0xff, STM32_OTGFS_DIEPINT(i)); - stm32_putreg(0xff, STM32_OTGFS_DOEPINT(i)); - } - - stm32_putreg(0, STM32_OTGFS_DIEPMSK); - stm32_putreg(0, STM32_OTGFS_DOEPMSK); - stm32_putreg(0, STM32_OTGFS_DIEPEMPMSK); - stm32_putreg(0, STM32_OTGFS_DAINTMSK); - stm32_putreg(0xffffffff, STM32_OTGFS_DAINT); - - /* Flush the FIFOs */ - - stm32_txfifo_flush(OTGFS_GRSTCTL_TXFNUM_DALL); - stm32_rxfifo_flush(); - - /* TODO: Turn off USB power and clocking */ - - priv->devstate = DEVSTATE_DEFAULT; - leave_critical_section(flags); -} - -/**************************************************************************** - * Name: usbdev_register - * - * Description: - * Register a USB device class driver. The class driver's bind() method - * will be called to bind it to a USB device driver. - * - ****************************************************************************/ - -int usbdev_register(struct usbdevclass_driver_s *driver) -{ - /* At present, there is only a single OTG FS device support. Hence it is - * pre-allocated as g_otgfsdev. However, in most code, the private data - * structure will be referenced using the 'priv' pointer (rather than the - * global data) in order to simplify any future support for multiple - * devices. - */ - - struct stm32_usbdev_s *priv = &g_otgfsdev; - int ret; - - usbtrace(TRACE_DEVREGISTER, 0); - -#ifdef CONFIG_DEBUG_FEATURES - if (!driver || !driver->ops->bind || !driver->ops->unbind || - !driver->ops->disconnect || !driver->ops->setup) - { - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); - return -EINVAL; - } - - if (priv->driver) - { - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_DRIVER), 0); - return -EBUSY; - } -#endif - - /* First hook up the driver */ - - priv->driver = driver; - - /* Then bind the class driver */ - - ret = CLASS_BIND(driver, &priv->usbdev); - if (ret) - { - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BINDFAILED), (uint16_t)-ret); - priv->driver = NULL; - } - else - { - /* Enable USB controller interrupts */ - - up_enable_irq(STM32_IRQ_OTGFS); - - /* FIXME: nothing seems to call DEV_CONNECT(), but we need to set - * the RS bit to enable the controller. It kind of makes sense - * to do this after the class has bound to us... - * GEN: This bug is really in the class driver. It should make the - * soft connect when it is ready to be enumerated. I have added - * that logic to the class drivers but left this logic here. - */ - - stm32_pullup(&priv->usbdev, true); - priv->usbdev.speed = USB_SPEED_FULL; - } - - return ret; -} - -/**************************************************************************** - * Name: usbdev_unregister - * - * Description: - * Un-register usbdev class driver.If the USB device is connected to a USB - * host, it will first disconnect(). The driver is also requested to - * unbind() and clean up any device state, before this procedure finally - * returns. - * - ****************************************************************************/ - -int usbdev_unregister(struct usbdevclass_driver_s *driver) -{ - /* At present, there is only a single OTG FS device support. Hence it is - * pre-allocated as g_otgfsdev. However, in most code, the private data - * structure will be referenced using the 'priv' pointer (rather than the - * global data) in order to simplify any future support for multiple - * devices. - */ - - struct stm32_usbdev_s *priv = &g_otgfsdev; - irqstate_t flags; - - usbtrace(TRACE_DEVUNREGISTER, 0); - -#ifdef CONFIG_DEBUG_FEATURES - if (driver != priv->driver) - { - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); - return -EINVAL; - } -#endif - - /* Reset the hardware and cancel all requests. All requests must be - * canceled while the class driver is still bound. - */ - - flags = enter_critical_section(); - stm32_usbreset(priv); - leave_critical_section(flags); - - /* Unbind the class driver */ - - CLASS_UNBIND(driver, &priv->usbdev); - - /* Disable USB controller interrupts */ - - flags = enter_critical_section(); - up_disable_irq(STM32_IRQ_OTGFS); - - /* Disconnect device */ - - stm32_pullup(&priv->usbdev, false); - - /* Unhook the driver */ - - priv->driver = NULL; - leave_critical_section(flags); - - return OK; -} - -#endif /* CONFIG_USBDEV && CONFIG_STM32_OTGFSDEV */ diff --git a/arch/arm/src/stm32/stm32_otgfshost.c b/arch/arm/src/stm32/stm32_otgfshost.c deleted file mode 100644 index b8a44c901782f..0000000000000 --- a/arch/arm/src/stm32/stm32_otgfshost.c +++ /dev/null @@ -1,5471 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_otgfshost.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include - -#include "chip.h" /* Includes default GPIO settings */ -#include /* May redefine GPIO settings */ - -#include "arm_internal.h" -#include "stm32_gpio.h" -#include "stm32_usbhost.h" - -#if defined(CONFIG_STM32_USBHOST) && defined(CONFIG_STM32_OTGFS) - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -/* STM32 USB OTG FS Host Driver Support - * - * Pre-requisites - * - * CONFIG_STM32_USBHOST - Enable STM32 USB host support - * CONFIG_USBHOST - Enable general USB host support - * CONFIG_STM32_OTGFS - Enable the STM32 USB OTG FS block - * CONFIG_STM32_SYSCFG - Needed - * - * Options: - * - * CONFIG_STM32_OTGFS_RXFIFO_SIZE - Size of the RX FIFO in 32-bit words. - * Default 128 (512 bytes) - * CONFIG_STM32_OTGFS_NPTXFIFO_SIZE - Size of the non-periodic Tx FIFO - * in 32-bit words. Default 96 (384 bytes) - * CONFIG_STM32_OTGFS_PTXFIFO_SIZE - Size of the periodic Tx FIFO in 32-bit - * words. Default 96 (384 bytes) - * CONFIG_STM32_OTGFS_DESCSIZE - Maximum size of a descriptor. Default: 128 - * CONFIG_STM32_OTGFS_SOFINTR - Enable SOF interrupts. Why would you ever - * want to do that? - * CONFIG_STM32_USBHOST_REGDEBUG - Enable very low-level register access - * debug. Depends on CONFIG_DEBUG_FEATURES. - * CONFIG_STM32_USBHOST_PKTDUMP - Dump all incoming and outgoing USB - * packets. Depends on CONFIG_DEBUG_FEATURES. - */ - -/* Pre-requisites (partial) */ - -#ifndef CONFIG_STM32_SYSCFG -# error "CONFIG_STM32_SYSCFG is required" -#endif - -/* Default RxFIFO size */ - -#ifndef CONFIG_STM32_OTGFS_RXFIFO_SIZE -# define CONFIG_STM32_OTGFS_RXFIFO_SIZE 128 -#endif - -/* Default host non-periodic Tx FIFO size */ - -#ifndef CONFIG_STM32_OTGFS_NPTXFIFO_SIZE -# define CONFIG_STM32_OTGFS_NPTXFIFO_SIZE 96 -#endif - -/* Default host periodic Tx fifo size register */ - -#ifndef CONFIG_STM32_OTGFS_PTXFIFO_SIZE -# define CONFIG_STM32_OTGFS_PTXFIFO_SIZE 96 -#endif - -/* Maximum size of a descriptor */ - -#ifndef CONFIG_STM32_OTGFS_DESCSIZE -# define CONFIG_STM32_OTGFS_DESCSIZE 128 -#endif - -/* Register/packet debug depends on CONFIG_DEBUG_FEATURES */ - -#ifndef CONFIG_DEBUG_USB_INFO -# undef CONFIG_STM32_USBHOST_REGDEBUG -# undef CONFIG_STM32_USBHOST_PKTDUMP -#endif - -/* HCD Setup ****************************************************************/ - -/* Hardware capabilities */ - -#define STM32_NHOST_CHANNELS 8 /* Number of host channels */ -#define STM32_MAX_PACKET_SIZE 64 /* Full speed max packet size */ -#define STM32_EP0_DEF_PACKET_SIZE 8 /* EP0 default packet size */ -#define STM32_EP0_MAX_PACKET_SIZE 64 /* EP0 FS max packet size */ -#define STM32_MAX_TX_FIFOS 15 /* Max number of TX FIFOs */ -#define STM32_MAX_PKTCOUNT 256 /* Max packet count */ -#define STM32_RETRY_COUNT 3 /* Number of ctrl transfer retries */ - -/* Delays *******************************************************************/ - -#define STM32_READY_DELAY 200000 /* In loop counts */ -#define STM32_FLUSH_DELAY 200000 /* In loop counts */ -#define STM32_SETUP_DELAY SEC2TICK(5) /* 5 seconds in system ticks */ -#define STM32_DATANAK_DELAY SEC2TICK(5) /* 5 seconds in system ticks */ - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/* The following enumeration represents the various states of the USB host - * state machine (for debug purposes only) - */ - -enum stm32_smstate_e -{ - SMSTATE_DETACHED = 0, /* Not attached to a device */ - SMSTATE_ATTACHED, /* Attached to a device */ - SMSTATE_ENUM, /* Attached, enumerating */ - SMSTATE_CLASS_BOUND, /* Enumeration complete, class bound */ -}; - -/* This enumeration provides the reason for the channel halt. */ - -enum stm32_chreason_e -{ - CHREASON_IDLE = 0, /* Inactive (initial state) */ - CHREASON_FREED, /* Channel is no longer in use */ - CHREASON_XFRC, /* Transfer complete */ - CHREASON_NAK, /* NAK received */ - CHREASON_NYET, /* NotYet received */ - CHREASON_STALL, /* Endpoint stalled */ - CHREASON_TXERR, /* Transfer error received */ - CHREASON_DTERR, /* Data toggle error received */ - CHREASON_FRMOR, /* Frame overrun */ - CHREASON_CANCELLED /* Transfer cancelled */ -}; - -/* This structure retains the state of one host channel. NOTE: Since there - * is only one channel operation active at a time, some of the fields in - * in the structure could be moved in struct stm32_ubhost_s to achieve - * some memory savings. - */ - -struct stm32_chan_s -{ - sem_t waitsem; /* Channel wait semaphore */ - volatile uint8_t result; /* The result of the transfer */ - volatile uint8_t chreason; /* Channel halt reason. See enum stm32_chreason_e */ - uint8_t chidx; /* Channel index */ - uint8_t epno; /* Device endpoint number (0-127) */ - uint8_t eptype; /* See OTGFS_EPTYPE_* definitions */ - uint8_t funcaddr; /* Device function address */ - uint8_t speed; /* Device speed */ - uint8_t interval; /* Interrupt/isochronous EP polling interval */ - uint8_t pid; /* Data PID */ - uint8_t npackets; /* Number of packets (for data toggle) */ - bool inuse; /* True: This channel is "in use" */ - volatile bool indata1; /* IN data toggle. True: DATA01 (Bulk and INTR only) */ - volatile bool outdata1; /* OUT data toggle. True: DATA01 */ - bool in; /* True: IN endpoint */ - volatile bool waiter; /* True: Thread is waiting for a channel event */ - uint16_t maxpacket; /* Max packet size */ - uint16_t buflen; /* Buffer length (at start of transfer) */ - volatile uint16_t xfrd; /* Bytes transferred (at end of transfer) */ - volatile uint16_t inflight; /* Number of Tx bytes "in-flight" */ - uint8_t *buffer; /* Transfer buffer pointer */ -#ifdef CONFIG_USBHOST_ASYNCH - usbhost_asynch_t callback; /* Transfer complete callback */ - void *arg; /* Argument that accompanies the callback */ -#endif -}; - -/* A channel represents on uni-directional endpoint. So, in the case of the - * bi-directional, control endpoint, there must be two channels to represent - * the endpoint. - */ - -struct stm32_ctrlinfo_s -{ - uint8_t inndx; /* EP0 IN control channel index */ - uint8_t outndx; /* EP0 OUT control channel index */ -}; - -/* This structure retains the state of the USB host controller */ - -struct stm32_usbhost_s -{ - /* Common device fields. This must be the first thing defined in the - * structure so that it is possible to simply cast from struct usbhost_s - * to structstm32_usbhost_s. - */ - - struct usbhost_driver_s drvr; - - /* This is the hub port description understood by class drivers */ - - struct usbhost_roothubport_s rhport; - - /* Overall driver status */ - - volatile uint8_t smstate; /* The state of the USB host state machine */ - uint8_t chidx; /* ID of channel waiting for space in Tx FIFO */ - volatile bool connected; /* Connected to device */ - volatile bool change; /* Connection change */ - volatile bool pscwait; /* True: Thread is waiting for a port event */ - mutex_t lock; /* Support mutually exclusive access */ - sem_t pscsem; /* Semaphore to wait for a port event */ - struct stm32_ctrlinfo_s ep0; /* Root hub port EP0 description */ - -#ifdef CONFIG_USBHOST_HUB - /* Used to pass external hub port events */ - - volatile struct usbhost_hubport_s *hport; -#endif - - struct usbhost_devaddr_s devgen; /* Address generation data */ - - /* The state of each host channel */ - - struct stm32_chan_s chan[STM32_MAX_TX_FIFOS]; -}; - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -/* Register operations ******************************************************/ - -#ifdef CONFIG_STM32_USBHOST_REGDEBUG -static void stm32_printreg(uint32_t addr, uint32_t val, bool iswrite); -static void stm32_checkreg(uint32_t addr, uint32_t val, bool iswrite); -static uint32_t stm32_getreg(uint32_t addr); -static void stm32_putreg(uint32_t addr, uint32_t value); -#else -# define stm32_getreg(addr) getreg32(addr) -# define stm32_putreg(addr,val) putreg32(val,addr) -#endif - -static inline void stm32_modifyreg(uint32_t addr, uint32_t clrbits, - uint32_t setbits); - -#ifdef CONFIG_STM32_USBHOST_PKTDUMP -# define stm32_pktdump(m,b,n) lib_dumpbuffer(m,b,n) -#else -# define stm32_pktdump(m,b,n) -#endif - -/* Byte stream access helper functions **************************************/ - -static inline uint16_t stm32_getle16(const uint8_t *val); - -/* Channel management *******************************************************/ - -static int stm32_chan_alloc(struct stm32_usbhost_s *priv); -static inline void stm32_chan_free(struct stm32_usbhost_s *priv, - int chidx); -static inline void stm32_chan_freeall(struct stm32_usbhost_s *priv); -static void stm32_chan_configure(struct stm32_usbhost_s *priv, - int chidx); -static void stm32_chan_halt(struct stm32_usbhost_s *priv, int chidx, - enum stm32_chreason_e chreason); -static int stm32_chan_waitsetup(struct stm32_usbhost_s *priv, - struct stm32_chan_s *chan); -#ifdef CONFIG_USBHOST_ASYNCH -static int stm32_chan_asynchsetup(struct stm32_usbhost_s *priv, - struct stm32_chan_s *chan, - usbhost_asynch_t callback, void *arg); -#endif -static int stm32_chan_wait(struct stm32_usbhost_s *priv, - struct stm32_chan_s *chan); -static void stm32_chan_wakeup(struct stm32_usbhost_s *priv, - struct stm32_chan_s *chan); -static int stm32_ctrlchan_alloc(struct stm32_usbhost_s *priv, - uint8_t epno, uint8_t funcaddr, - uint8_t speed, - struct stm32_ctrlinfo_s *ctrlep); -static int stm32_ctrlep_alloc(struct stm32_usbhost_s *priv, - const struct usbhost_epdesc_s *epdesc, - usbhost_ep_t *ep); -static int stm32_xfrep_alloc(struct stm32_usbhost_s *priv, - const struct usbhost_epdesc_s *epdesc, - usbhost_ep_t *ep); - -/* Control/data transfer logic **********************************************/ - -static void stm32_transfer_start(struct stm32_usbhost_s *priv, - int chidx); -#if 0 /* Not used */ -static inline uint16_t stm32_getframe(void); -#endif -static int stm32_ctrl_sendsetup(struct stm32_usbhost_s *priv, - struct stm32_ctrlinfo_s *ep0, - const struct usb_ctrlreq_s *req); -static int stm32_ctrl_senddata(struct stm32_usbhost_s *priv, - struct stm32_ctrlinfo_s *ep0, - uint8_t *buffer, unsigned int buflen); -static int stm32_ctrl_recvdata(struct stm32_usbhost_s *priv, - struct stm32_ctrlinfo_s *ep0, - uint8_t *buffer, unsigned int buflen); -static int stm32_in_setup(struct stm32_usbhost_s *priv, int chidx); -static ssize_t stm32_in_transfer(struct stm32_usbhost_s *priv, int chidx, - uint8_t *buffer, size_t buflen); -#ifdef CONFIG_USBHOST_ASYNCH -static void stm32_in_next(struct stm32_usbhost_s *priv, - struct stm32_chan_s *chan); -static int stm32_in_asynch(struct stm32_usbhost_s *priv, int chidx, - uint8_t *buffer, size_t buflen, - usbhost_asynch_t callback, void *arg); -#endif -static int stm32_out_setup(struct stm32_usbhost_s *priv, int chidx); -static ssize_t stm32_out_transfer(struct stm32_usbhost_s *priv, - int chidx, uint8_t *buffer, - size_t buflen); -#ifdef CONFIG_USBHOST_ASYNCH -static void stm32_out_next(struct stm32_usbhost_s *priv, - struct stm32_chan_s *chan); -static int stm32_out_asynch(struct stm32_usbhost_s *priv, int chidx, - uint8_t *buffer, size_t buflen, - usbhost_asynch_t callback, void *arg); -#endif - -/* Interrupt handling *******************************************************/ - -/* Lower level interrupt handlers */ - -static void stm32_gint_wrpacket(struct stm32_usbhost_s *priv, - uint8_t *buffer, int chidx, int buflen); -static inline void stm32_gint_hcinisr(struct stm32_usbhost_s *priv, - int chidx); -static inline void stm32_gint_hcoutisr(struct stm32_usbhost_s *priv, - int chidx); -static void stm32_gint_connected(struct stm32_usbhost_s *priv); -static void stm32_gint_disconnected(struct stm32_usbhost_s *priv); - -/* Second level interrupt handlers */ - -#ifdef CONFIG_STM32_OTGFS_SOFINTR -static inline void stm32_gint_sofisr(struct stm32_usbhost_s *priv); -#endif -static inline void stm32_gint_rxflvlisr(struct stm32_usbhost_s *priv); -static inline void stm32_gint_nptxfeisr(struct stm32_usbhost_s *priv); -static inline void stm32_gint_ptxfeisr(struct stm32_usbhost_s *priv); -static inline void stm32_gint_hcisr(struct stm32_usbhost_s *priv); -static inline void stm32_gint_hprtisr(struct stm32_usbhost_s *priv); -static inline void stm32_gint_discisr(struct stm32_usbhost_s *priv); -static inline void stm32_gint_ipxfrisr(struct stm32_usbhost_s *priv); - -/* First level, global interrupt handler */ - -static int stm32_gint_isr(int irq, void *context, void *arg); - -/* Interrupt controls */ - -static void stm32_gint_enable(void); -static void stm32_gint_disable(void); -static inline void stm32_hostinit_enable(void); -static void stm32_txfe_enable(struct stm32_usbhost_s *priv, int chidx); - -/* USB host controller operations *******************************************/ - -static int stm32_wait(struct usbhost_connection_s *conn, - struct usbhost_hubport_s **hport); -static int stm32_rh_enumerate(struct stm32_usbhost_s *priv, - struct usbhost_connection_s *conn, - struct usbhost_hubport_s *hport); -static int stm32_enumerate(struct usbhost_connection_s *conn, - struct usbhost_hubport_s *hport); - -static int stm32_ep0configure(struct usbhost_driver_s *drvr, - usbhost_ep_t ep0, uint8_t funcaddr, - uint8_t speed, uint16_t maxpacketsize); -static int stm32_epalloc(struct usbhost_driver_s *drvr, - const struct usbhost_epdesc_s *epdesc, - usbhost_ep_t *ep); -static int stm32_epfree(struct usbhost_driver_s *drvr, usbhost_ep_t ep); -static int stm32_alloc(struct usbhost_driver_s *drvr, - uint8_t **buffer, size_t *maxlen); -static int stm32_free(struct usbhost_driver_s *drvr, - uint8_t *buffer); -static int stm32_ioalloc(struct usbhost_driver_s *drvr, - uint8_t **buffer, size_t buflen); -static int stm32_iofree(struct usbhost_driver_s *drvr, - uint8_t *buffer); -static int stm32_ctrlin(struct usbhost_driver_s *drvr, usbhost_ep_t ep0, - const struct usb_ctrlreq_s *req, - uint8_t *buffer); -static int stm32_ctrlout(struct usbhost_driver_s *drvr, usbhost_ep_t ep0, - const struct usb_ctrlreq_s *req, - const uint8_t *buffer); -static ssize_t stm32_transfer(struct usbhost_driver_s *drvr, - usbhost_ep_t ep, uint8_t *buffer, - size_t buflen); -#ifdef CONFIG_USBHOST_ASYNCH -static int stm32_asynch(struct usbhost_driver_s *drvr, usbhost_ep_t ep, - uint8_t *buffer, size_t buflen, - usbhost_asynch_t callback, void *arg); -#endif -static int stm32_cancel(struct usbhost_driver_s *drvr, usbhost_ep_t ep); -#ifdef CONFIG_USBHOST_HUB -static int stm32_connect(struct usbhost_driver_s *drvr, - struct usbhost_hubport_s *hport, - bool connected); -#endif -static void stm32_disconnect(struct usbhost_driver_s *drvr, - struct usbhost_hubport_s *hport); - -/* Initialization ***********************************************************/ - -static void stm32_portreset(struct stm32_usbhost_s *priv); -static void stm32_flush_txfifos(uint32_t txfnum); -static void stm32_flush_rxfifo(void); -static void stm32_vbusdrive(struct stm32_usbhost_s *priv, bool state); -static void stm32_host_initialize(struct stm32_usbhost_s *priv); - -static inline void stm32_sw_initialize(struct stm32_usbhost_s *priv); -static inline int stm32_hw_initialize(struct stm32_usbhost_s *priv); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* In this driver implementation, support is provided for only a single a - * single USB device. All status information can be simply retained in a - * single global instance. - */ - -static struct stm32_usbhost_s g_usbhost = -{ - .lock = NXMUTEX_INITIALIZER, - .pscsem = SEM_INITIALIZER(0), -}; - -/* This is the connection/enumeration interface */ - -static struct usbhost_connection_s g_usbconn = -{ - .wait = stm32_wait, - .enumerate = stm32_enumerate, -}; - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_printreg - * - * Description: - * Print the contents of an STM32xx register operation - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_USBHOST_REGDEBUG -static void stm32_printreg(uint32_t addr, uint32_t val, bool iswrite) -{ - uinfo("%08" PRIx32 "%s%08" PRIx32 "\n", addr, iswrite ? "<-" : "->", val); -} -#endif - -/**************************************************************************** - * Name: stm32_checkreg - * - * Description: - * Get the contents of an STM32 register - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_USBHOST_REGDEBUG -static void stm32_checkreg(uint32_t addr, uint32_t val, bool iswrite) -{ - static uint32_t prevaddr = 0; - static uint32_t preval = 0; - static uint32_t count = 0; - static bool prevwrite = false; - - /* Is this the same value that we read from/wrote to the same register - * last time? Are we polling the register? If so, suppress the output. - */ - - if (addr == prevaddr && val == preval && prevwrite == iswrite) - { - /* Yes.. Just increment the count */ - - count++; - } - else - { - /* No this is a new address or value or operation. Were there any - * duplicate accesses before this one? - */ - - if (count > 0) - { - /* Yes.. Just one? */ - - if (count == 1) - { - /* Yes.. Just one */ - - stm32_printreg(prevaddr, preval, prevwrite); - } - else - { - /* No.. More than one. */ - - uinfo("[repeats %d more times]\n", count); - } - } - - /* Save the new address, value, count, and operation for next time */ - - prevaddr = addr; - preval = val; - count = 0; - prevwrite = iswrite; - - /* Show the new regisgter access */ - - stm32_printreg(addr, val, iswrite); - } -} -#endif - -/**************************************************************************** - * Name: stm32_getreg - * - * Description: - * Get the contents of an STM32 register - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_USBHOST_REGDEBUG -static uint32_t stm32_getreg(uint32_t addr) -{ - /* Read the value from the register */ - - uint32_t val = getreg32(addr); - - /* Check if we need to print this value */ - - stm32_checkreg(addr, val, false); - return val; -} -#endif - -/**************************************************************************** - * Name: stm32_putreg - * - * Description: - * Set the contents of an STM32 register to a value - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_USBHOST_REGDEBUG -static void stm32_putreg(uint32_t addr, uint32_t val) -{ - /* Check if we need to print this value */ - - stm32_checkreg(addr, val, true); - - /* Write the value */ - - putreg32(val, addr); -} -#endif - -/**************************************************************************** - * Name: stm32_modifyreg - * - * Description: - * Modify selected bits of an STM32 register. - * - ****************************************************************************/ - -static inline void stm32_modifyreg(uint32_t addr, uint32_t clrbits, - uint32_t setbits) -{ - stm32_putreg(addr, (((stm32_getreg(addr)) & ~clrbits) | setbits)); -} - -/**************************************************************************** - * Name: stm32_getle16 - * - * Description: - * Get a (possibly unaligned) 16-bit little endian value. - * - ****************************************************************************/ - -static inline uint16_t stm32_getle16(const uint8_t *val) -{ - return (uint16_t)val[1] << 8 | (uint16_t)val[0]; -} - -/**************************************************************************** - * Name: stm32_chan_alloc - * - * Description: - * Allocate a channel. - * - ****************************************************************************/ - -static int stm32_chan_alloc(struct stm32_usbhost_s *priv) -{ - int chidx; - - /* Search the table of channels */ - - for (chidx = 0; chidx < STM32_NHOST_CHANNELS; chidx++) - { - /* Is this channel available? */ - - if (!priv->chan[chidx].inuse) - { - /* Yes... make it "in use" and return the index */ - - priv->chan[chidx].inuse = true; - return chidx; - } - } - - /* All of the channels are "in-use" */ - - return -EBUSY; -} - -/**************************************************************************** - * Name: stm32_chan_free - * - * Description: - * Free a previoiusly allocated channel. - * - ****************************************************************************/ - -static void stm32_chan_free(struct stm32_usbhost_s *priv, int chidx) -{ - DEBUGASSERT((unsigned)chidx < STM32_NHOST_CHANNELS); - - /* Halt the channel */ - - stm32_chan_halt(priv, chidx, CHREASON_FREED); - - /* Mark the channel available */ - - priv->chan[chidx].inuse = false; -} - -/**************************************************************************** - * Name: stm32_chan_freeall - * - * Description: - * Free all channels. - * - ****************************************************************************/ - -static inline void stm32_chan_freeall(struct stm32_usbhost_s *priv) -{ - uint8_t chidx; - - /* Free all host channels */ - - for (chidx = 2; chidx < STM32_NHOST_CHANNELS; chidx++) - { - stm32_chan_free(priv, chidx); - } -} - -/**************************************************************************** - * Name: stm32_chan_configure - * - * Description: - * Configure or re-configure a host channel. Host channels are configured - * when endpoint is allocated and EP0 (only) is re-configured with the - * max packet size or device address changes. - * - ****************************************************************************/ - -static void stm32_chan_configure(struct stm32_usbhost_s *priv, int chidx) -{ - struct stm32_chan_s *chan = &priv->chan[chidx]; - uint32_t regval; - - /* Clear any old pending interrupts for this host channel. */ - - stm32_putreg(STM32_OTGFS_HCINT(chidx), 0xffffffff); - - /* Enable channel interrupts required for transfers on this channel. */ - - regval = 0; - - switch (chan->eptype) - { - case OTGFS_EPTYPE_CTRL: - case OTGFS_EPTYPE_BULK: - { -#ifdef HAVE_USBHOST_TRACE_VERBOSE - uint16_t intrace; - uint16_t outtrace; - - /* Determine the definitive trace ID to use below */ - - if (chan->eptype == OTGFS_EPTYPE_CTRL) - { - intrace = OTGFS_VTRACE2_CHANCONF_CTRL_IN; - outtrace = OTGFS_VTRACE2_CHANCONF_CTRL_OUT; - } - else - { - intrace = OTGFS_VTRACE2_CHANCONF_BULK_IN; - outtrace = OTGFS_VTRACE2_CHANCONF_BULK_OUT; - } -#endif - - /* Interrupts required for CTRL and BULK endpoints */ - - regval |= (OTGFS_HCINT_XFRC | OTGFS_HCINT_STALL | OTGFS_HCINT_NAK | - OTGFS_HCINT_TXERR | OTGFS_HCINT_DTERR); - - /* Additional setting for IN/OUT endpoints */ - - if (chan->in) - { - usbhost_vtrace2(intrace, chidx, chan->epno); - regval |= OTGFS_HCINT_BBERR; - } - else - { - usbhost_vtrace2(outtrace, chidx, chan->epno); - regval |= OTGFS_HCINT_NYET; - } - } - break; - - case OTGFS_EPTYPE_INTR: - { - /* Interrupts required for INTR endpoints */ - - regval |= (OTGFS_HCINT_XFRC | OTGFS_HCINT_STALL | - OTGFS_HCINT_NAK | OTGFS_HCINT_TXERR | - OTGFS_HCINT_FRMOR | OTGFS_HCINT_DTERR); - - /* Additional setting for IN endpoints */ - - if (chan->in) - { - usbhost_vtrace2(OTGFS_VTRACE2_CHANCONF_INTR_IN, chidx, - chan->epno); - regval |= OTGFS_HCINT_BBERR; - } -#ifdef HAVE_USBHOST_TRACE_VERBOSE - else - { - usbhost_vtrace2(OTGFS_VTRACE2_CHANCONF_INTR_OUT, chidx, - chan->epno); - } -#endif - } - break; - - case OTGFS_EPTYPE_ISOC: - { - /* Interrupts required for ISOC endpoints */ - - regval |= OTGFS_HCINT_XFRC | OTGFS_HCINT_ACK | OTGFS_HCINT_FRMOR; - - /* Additional setting for IN endpoints */ - - if (chan->in) - { - usbhost_vtrace2(OTGFS_VTRACE2_CHANCONF_ISOC_IN, chidx, - chan->epno); - regval |= (OTGFS_HCINT_TXERR | OTGFS_HCINT_BBERR); - } -#ifdef HAVE_USBHOST_TRACE_VERBOSE - else - { - usbhost_vtrace2(OTGFS_VTRACE2_CHANCONF_ISOC_OUT, chidx, - chan->epno); - } -#endif - } - break; - } - - stm32_putreg(STM32_OTGFS_HCINTMSK(chidx), regval); - - /* Enable the top level host channel interrupt. */ - - stm32_modifyreg(STM32_OTGFS_HAINTMSK, 0, OTGFS_HAINT(chidx)); - - /* Make sure host channel interrupts are enabled. */ - - stm32_modifyreg(STM32_OTGFS_GINTMSK, 0, OTGFS_GINT_HC); - - /* Program the HCCHAR register */ - - regval = ((uint32_t)chan->maxpacket << OTGFS_HCCHAR_MPSIZ_SHIFT) | - ((uint32_t)chan->epno << OTGFS_HCCHAR_EPNUM_SHIFT) | - ((uint32_t)chan->eptype << OTGFS_HCCHAR_EPTYP_SHIFT) | - ((uint32_t)chan->funcaddr << OTGFS_HCCHAR_DAD_SHIFT); - - /* Special case settings for low speed devices */ - - if (chan->speed == USB_SPEED_LOW) - { - regval |= OTGFS_HCCHAR_LSDEV; - } - - /* Special case settings for IN endpoints */ - - if (chan->in) - { - regval |= OTGFS_HCCHAR_EPDIR_IN; - } - - /* Special case settings for INTR endpoints */ - - if (chan->eptype == OTGFS_EPTYPE_INTR) - { - regval |= OTGFS_HCCHAR_ODDFRM; - } - - /* Write the channel configuration */ - - stm32_putreg(STM32_OTGFS_HCCHAR(chidx), regval); -} - -/**************************************************************************** - * Name: stm32_chan_halt - * - * Description: - * Halt the channel associated with 'chidx' by setting the CHannel DISable - * (CHDIS) bit in in the HCCHAR register. - * - ****************************************************************************/ - -static void stm32_chan_halt(struct stm32_usbhost_s *priv, int chidx, - enum stm32_chreason_e chreason) -{ - uint32_t hcchar; - uint32_t intmsk; - uint32_t eptype; - unsigned int avail; - - /* Save the reason for the halt. We need this in the channel halt - * interrupt handling logic to know what to do next. - */ - - usbhost_vtrace2(OTGFS_VTRACE2_CHANHALT, chidx, chreason); - - priv->chan[chidx].chreason = (uint8_t)chreason; - - /* "The application can disable any channel by programming the - * OTG_FS_HCCHARx register with the CHDIS and CHENA bits set to 1. This - * enables the OTG_FS host to flush the posted requests (if any) and - * generates a channel halted interrupt. The application must wait for - * the CHH interrupt in OTG_FS_HCINTx before reallocating the channel for - * other transactions. The OTG_FS host does not interrupt the - * transaction that has already been started on the USB." - */ - - hcchar = stm32_getreg(STM32_OTGFS_HCCHAR(chidx)); - hcchar |= (OTGFS_HCCHAR_CHDIS | OTGFS_HCCHAR_CHENA); - - /* Get the endpoint type from the HCCHAR register */ - - eptype = hcchar & OTGFS_HCCHAR_EPTYP_MASK; - - /* Check for space in the Tx FIFO to issue the halt. - * - * "Before disabling a channel, the application must ensure that there is - * at least one free space available in the non-periodic request queue - * (when disabling a non-periodic channel) or the periodic request queue - * (when disabling a periodic channel). The application can simply flush - * the posted requests when the Request queue is full (before disabling - * the channel), by programming the OTG_FS_HCCHARx register with the - * CHDIS bit set to 1, and the CHENA bit cleared to 0." - */ - - if (eptype == OTGFS_HCCHAR_EPTYP_CTRL || - eptype == OTGFS_HCCHAR_EPTYP_BULK) - { - /* Get the number of words available in the non-periodic Tx FIFO. */ - - avail = stm32_getreg(STM32_OTGFS_HNPTXSTS) & - OTGFS_HNPTXSTS_NPTXFSAV_MASK; - } - else - { - /* Get the number of words available in the non-periodic Tx FIFO. */ - - avail = stm32_getreg(STM32_OTGFS_HPTXSTS) & - OTGFS_HPTXSTS_PTXFSAVL_MASK; - } - - /* Check if there is any space available in the Tx FIFO. */ - - if (avail == 0) - { - /* The Tx FIFO is full... disable the channel to flush the requests */ - - hcchar &= ~OTGFS_HCCHAR_CHENA; - } - - /* Unmask the CHannel Halted (CHH) interrupt */ - - intmsk = stm32_getreg(STM32_OTGFS_HCINTMSK(chidx)); - intmsk |= OTGFS_HCINT_CHH; - stm32_putreg(STM32_OTGFS_HCINTMSK(chidx), intmsk); - - /* Halt the channel by setting CHDIS (and maybe CHENA) in the HCCHAR */ - - stm32_putreg(STM32_OTGFS_HCCHAR(chidx), hcchar); -} - -/**************************************************************************** - * Name: stm32_chan_waitsetup - * - * Description: - * Set the request for the transfer complete event well BEFORE enabling - * the transfer (as soon as we are absolutely committed to the transfer). - * We do this to minimize race conditions. This logic would have to be - * expanded if we want to have more than one packet in flight at a time! - * - * Assumptions: - * Called from a normal thread context BEFORE the transfer has been - * started. - * - ****************************************************************************/ - -static int stm32_chan_waitsetup(struct stm32_usbhost_s *priv, - struct stm32_chan_s *chan) -{ - irqstate_t flags = enter_critical_section(); - int ret = -ENODEV; - - /* Is the device still connected? */ - - if (priv->connected) - { - /* Yes.. then set waiter to indicate that we expect to be informed - * when either (1) the device is disconnected, or (2) the transfer - * completed. - */ - - chan->waiter = true; -#ifdef CONFIG_USBHOST_ASYNCH - chan->callback = NULL; - chan->arg = NULL; -#endif - ret = OK; - } - - leave_critical_section(flags); - return ret; -} - -/**************************************************************************** - * Name: stm32_chan_asynchsetup - * - * Description: - * Set the request for the transfer complete event well BEFORE enabling - * the transfer (as soon as we are absolutely committed to the to avoid - * transfer). We do this to minimize race conditions. This logic would - * have to be expanded if we want to have more than one packet in flight - * at a time! - * - * Assumptions: - * Might be called from the level of an interrupt handler - * - ****************************************************************************/ - -#ifdef CONFIG_USBHOST_ASYNCH -static int stm32_chan_asynchsetup(struct stm32_usbhost_s *priv, - struct stm32_chan_s *chan, - usbhost_asynch_t callback, void *arg) -{ - irqstate_t flags = enter_critical_section(); - int ret = -ENODEV; - - /* Is the device still connected? */ - - if (priv->connected) - { - /* Yes.. then set waiter to indicate that we expect to be informed - * when either (1) the device is disconnected, or (2) the transfer - * completed. - */ - - chan->waiter = false; - chan->callback = callback; - chan->arg = arg; - ret = OK; - } - - leave_critical_section(flags); - return ret; -} -#endif - -/**************************************************************************** - * Name: stm32_chan_wait - * - * Description: - * Wait for a transfer on a channel to complete. - * - * Assumptions: - * Called from a normal thread context - * - ****************************************************************************/ - -static int stm32_chan_wait(struct stm32_usbhost_s *priv, - struct stm32_chan_s *chan) -{ - irqstate_t flags; - int ret; - - /* Disable interrupts so that the following operations will be atomic. On - * the OTG FS global interrupt needs to be disabled. However, here we - * disable all interrupts to exploit that fact that interrupts will be re- - * enabled while we wait. - */ - - flags = enter_critical_section(); - - /* Loop, testing for an end of transfer condition. The channel 'result' - * was set to EBUSY and 'waiter' was set to true before the transfer; - * 'waiter' will be set to false and 'result' will be set appropriately - * when the transfer is completed. - */ - - do - { - /* Wait for the transfer to complete. NOTE the transfer may already - * completed before we get here or the transfer may complete while we - * wait here. - */ - - ret = nxsem_wait_uninterruptible(&chan->waitsem); - } - while (chan->waiter && ret >= 0); - - /* The transfer is complete re-enable interrupts and return the result */ - - if (ret >= 0) - { - ret = -(int)chan->result; - } - - leave_critical_section(flags); - return ret; -} - -/**************************************************************************** - * Name: stm32_chan_wakeup - * - * Description: - * A channel transfer has completed... wakeup any threads waiting for the - * transfer to complete. - * - * Assumptions: - * This function is called from the transfer complete interrupt handler for - * the channel. Interrupts are disabled. - * - ****************************************************************************/ - -static void stm32_chan_wakeup(struct stm32_usbhost_s *priv, - struct stm32_chan_s *chan) -{ - /* Is the transfer complete? */ - - if (chan->result != EBUSY) - { - /* Is there a thread waiting for this transfer to complete? */ - - if (chan->waiter) - { -#ifdef CONFIG_USBHOST_ASYNCH - /* Yes.. there should not also be a callback scheduled */ - - DEBUGASSERT(chan->callback == NULL); -#endif - /* Wake'em up! */ - - usbhost_vtrace2(chan->in ? OTGFS_VTRACE2_CHANWAKEUP_IN : - OTGFS_VTRACE2_CHANWAKEUP_OUT, - chan->epno, chan->result); - - nxsem_post(&chan->waitsem); - chan->waiter = false; - } - -#ifdef CONFIG_USBHOST_ASYNCH - /* No.. is an asynchronous callback expected when the transfer - * completes? - */ - - else if (chan->callback) - { - /* Handle continuation of IN/OUT pipes */ - - if (chan->in) - { - stm32_in_next(priv, chan); - } - else - { - stm32_out_next(priv, chan); - } - } -#endif - } -} - -/**************************************************************************** - * Name: stm32_ctrlchan_alloc - * - * Description: - * Allocate and configured channels for a control pipe. - * - ****************************************************************************/ - -static int stm32_ctrlchan_alloc(struct stm32_usbhost_s *priv, - uint8_t epno, uint8_t funcaddr, - uint8_t speed, - struct stm32_ctrlinfo_s *ctrlep) -{ - struct stm32_chan_s *chan; - int inndx; - int outndx; - - outndx = stm32_chan_alloc(priv); - if (outndx < 0) - { - return -ENOMEM; - } - - ctrlep->outndx = outndx; - chan = &priv->chan[outndx]; - chan->epno = epno; - chan->in = false; - chan->eptype = OTGFS_EPTYPE_CTRL; - chan->funcaddr = funcaddr; - chan->speed = speed; - chan->interval = 0; - chan->maxpacket = STM32_EP0_DEF_PACKET_SIZE; - chan->indata1 = false; - chan->outdata1 = false; - - /* Configure control OUT channels */ - - stm32_chan_configure(priv, outndx); - - /* Allocate and initialize the control IN channel */ - - inndx = stm32_chan_alloc(priv); - if (inndx < 0) - { - stm32_chan_free(priv, outndx); - return -ENOMEM; - } - - ctrlep->inndx = inndx; - chan = &priv->chan[inndx]; - chan->epno = epno; - chan->in = true; - chan->eptype = OTGFS_EPTYPE_CTRL; - chan->funcaddr = funcaddr; - chan->speed = speed; - chan->interval = 0; - chan->maxpacket = STM32_EP0_DEF_PACKET_SIZE; - chan->indata1 = false; - chan->outdata1 = false; - - /* Configure control IN channels */ - - stm32_chan_configure(priv, inndx); - return OK; -} - -/**************************************************************************** - * Name: stm32_ctrlep_alloc - * - * Description: - * Allocate a container and channels for control pipe. - * - * Input Parameters: - * priv - The private USB host driver state. - * epdesc - Describes the endpoint to be allocated. - * ep - A memory location provided by the caller in which to receive the - * allocated endpoint descriptor. - * - * Returned Value: - * On success, zero (OK) is returned. On a failure, a negated errno value - * is returned indicating the nature of the failure - * - * Assumptions: - * This function will *not* be called from an interrupt handler. - * - ****************************************************************************/ - -static int stm32_ctrlep_alloc(struct stm32_usbhost_s *priv, - const struct usbhost_epdesc_s *epdesc, - usbhost_ep_t *ep) -{ - struct usbhost_hubport_s *hport; - struct stm32_ctrlinfo_s *ctrlep; - int ret; - - /* Sanity check. NOTE that this method should only be called if a device - * is connected (because we need a valid low speed indication). - */ - - DEBUGASSERT(epdesc->hport != NULL); - hport = epdesc->hport; - - /* Allocate a container for the control endpoint */ - - ctrlep = (struct stm32_ctrlinfo_s *) - kmm_malloc(sizeof(struct stm32_ctrlinfo_s)); - if (ctrlep == NULL) - { - uerr("ERROR: Failed to allocate control endpoint container\n"); - return -ENOMEM; - } - - /* Then allocate and configure the IN/OUT channels */ - - ret = stm32_ctrlchan_alloc(priv, epdesc->addr & USB_EPNO_MASK, - hport->funcaddr, hport->speed, ctrlep); - if (ret < 0) - { - uerr("ERROR: stm32_ctrlchan_alloc failed: %d\n", ret); - kmm_free(ctrlep); - return ret; - } - - /* Return a pointer to the control pipe container as the pipe "handle" */ - - *ep = (usbhost_ep_t)ctrlep; - return OK; -} - -/**************************************************************************** - * Name: stm32_xfrep_alloc - * - * Description: - * Allocate and configure one unidirectional endpoint. - * - * Input Parameters: - * priv - The private USB host driver state. - * epdesc - Describes the endpoint to be allocated. - * ep - A memory location provided by the caller in which to receive the - * allocated endpoint descriptor. - * - * Returned Value: - * On success, zero (OK) is returned. On a failure, a negated errno value - * is returned indicating the nature of the failure - * - * Assumptions: - * This function will *not* be called from an interrupt handler. - * - ****************************************************************************/ - -static int stm32_xfrep_alloc(struct stm32_usbhost_s *priv, - const struct usbhost_epdesc_s *epdesc, - usbhost_ep_t *ep) -{ - struct usbhost_hubport_s *hport; - struct stm32_chan_s *chan; - int chidx; - - /* Sanity check. NOTE that this method should only be called if a device - * is connected (because we need a valid low speed indication). - */ - - DEBUGASSERT(epdesc->hport != NULL); - hport = epdesc->hport; - - /* Allocate a host channel for the endpoint */ - - chidx = stm32_chan_alloc(priv); - if (chidx < 0) - { - uerr("ERROR: Failed to allocate a host channel\n"); - return -ENOMEM; - } - - /* Decode the endpoint descriptor to initialize the channel data - * structures. Note: Here we depend on the fact that the endpoint - * point type is encoded in the same way in the endpoint descriptor as it - * is in the OTG HS hardware. - */ - - chan = &priv->chan[chidx]; - chan->epno = epdesc->addr & USB_EPNO_MASK; - chan->in = epdesc->in; - chan->eptype = epdesc->xfrtype; - chan->funcaddr = hport->funcaddr; - chan->speed = hport->speed; - chan->interval = epdesc->interval; - chan->maxpacket = epdesc->mxpacketsize; - chan->indata1 = false; - chan->outdata1 = false; - - /* Then configure the endpoint */ - - stm32_chan_configure(priv, chidx); - - /* Return the index to the allocated channel as the endpoint "handle" */ - - *ep = (usbhost_ep_t)chidx; - return OK; -} - -/**************************************************************************** - * Name: stm32_transfer_start - * - * Description: - * Start at transfer on the select IN or OUT channel. - * - ****************************************************************************/ - -static void stm32_transfer_start(struct stm32_usbhost_s *priv, int chidx) -{ - struct stm32_chan_s *chan; - uint32_t regval; - unsigned int npackets; - unsigned int maxpacket; - unsigned int avail; - unsigned int wrsize; - unsigned int minsize; - - /* Set up the initial state of the transfer */ - - chan = &priv->chan[chidx]; - - usbhost_vtrace2(OTGFS_VTRACE2_STARTTRANSFER, chidx, chan->buflen); - - chan->result = EBUSY; - chan->inflight = 0; - chan->xfrd = 0; - priv->chidx = chidx; - - /* Compute the expected number of packets associated to the transfer. - * If the transfer length is zero (or less than the size of one maximum - * size packet), then one packet is expected. - */ - - /* If the transfer size is greater than one packet, then calculate the - * number of packets that will be received/sent, including any partial - * final packet. - */ - - maxpacket = chan->maxpacket; - - if (chan->buflen > maxpacket) - { - npackets = (chan->buflen + maxpacket - 1) / maxpacket; - - /* Clip if the buffer length if it exceeds the maximum number of - * packets that can be transferred (this should not happen). - */ - - if (npackets > STM32_MAX_PKTCOUNT) - { - npackets = STM32_MAX_PKTCOUNT; - chan->buflen = STM32_MAX_PKTCOUNT * maxpacket; - usbhost_trace2(OTGFS_TRACE2_CLIP, chidx, chan->buflen); - } - } - else - { - /* One packet will be sent/received (might be a zero length packet) */ - - npackets = 1; - } - - /* If it is an IN transfer, then adjust the size of the buffer UP to - * a full number of packets. Hmmm... couldn't this cause an overrun - * into unallocated memory? - */ - -#if 0 /* Think about this */ - if (chan->in) - { - /* Force the buffer length to an even multiple of maxpacket */ - - chan->buflen = npackets * maxpacket; - } -#endif - - /* Save the number of packets in the transfer. We will need this in - * order to set the next data toggle correctly when the transfer - * completes. - */ - - chan->npackets = (uint8_t)npackets; - - /* Setup the HCTSIZn register */ - - regval = ((uint32_t)chan->buflen << OTGFS_HCTSIZ_XFRSIZ_SHIFT) | - ((uint32_t)npackets << OTGFS_HCTSIZ_PKTCNT_SHIFT) | - ((uint32_t)chan->pid << OTGFS_HCTSIZ_DPID_SHIFT); - stm32_putreg(STM32_OTGFS_HCTSIZ(chidx), regval); - - /* Setup the HCCHAR register: Frame oddness and host channel enable */ - - regval = stm32_getreg(STM32_OTGFS_HCCHAR(chidx)); - - /* Set/clear the Odd Frame bit. Check for an even frame; if so set Odd - * Frame. This field is applicable for only periodic (isochronous and - * interrupt) channels. - */ - - if ((stm32_getreg(STM32_OTGFS_HFNUM) & 1) == 0) - { - regval |= OTGFS_HCCHAR_ODDFRM; - } - else - { - regval &= ~OTGFS_HCCHAR_ODDFRM; - } - - regval &= ~OTGFS_HCCHAR_CHDIS; - regval |= OTGFS_HCCHAR_CHENA; - stm32_putreg(STM32_OTGFS_HCCHAR(chidx), regval); - - /* If this is an out transfer, then we need to do more.. we need to copy - * the outgoing data into the correct TxFIFO. - */ - - if (!chan->in && chan->buflen > 0) - { - /* Handle non-periodic (CTRL and BULK) OUT transfers differently than - * periodic (INTR and ISOC) OUT transfers. - */ - - minsize = MIN(chan->buflen, chan->maxpacket); - - switch (chan->eptype) - { - case OTGFS_EPTYPE_CTRL: /* Non periodic transfer */ - case OTGFS_EPTYPE_BULK: - { - /* Read the Non-periodic Tx FIFO status register */ - - regval = stm32_getreg(STM32_OTGFS_HNPTXSTS); - avail = ((regval & OTGFS_HNPTXSTS_NPTXFSAV_MASK) >> - OTGFS_HNPTXSTS_NPTXFSAV_SHIFT) << 2; - } - break; - - /* Periodic transfer */ - - case OTGFS_EPTYPE_INTR: - case OTGFS_EPTYPE_ISOC: - { - /* Read the Non-periodic Tx FIFO status register */ - - regval = stm32_getreg(STM32_OTGFS_HPTXSTS); - avail = ((regval & OTGFS_HPTXSTS_PTXFSAVL_MASK) >> - OTGFS_HPTXSTS_PTXFSAVL_SHIFT) << 2; - } - break; - - default: - DEBUGPANIC(); - return; - } - - /* Is there space in the TxFIFO to hold the minimum size packet? */ - - if (minsize <= avail) - { - /* Yes.. Get the size of the biggest thing that we can put - * in the Tx FIFO now - */ - - wrsize = chan->buflen; - if (wrsize > avail) - { - /* Clip the write size to the number of full, max sized packets - * that will fit in the Tx FIFO. - */ - - unsigned int wrpackets = avail / chan->maxpacket; - wrsize = wrpackets * chan->maxpacket; - } - - /* Write packet into the Tx FIFO. */ - - stm32_gint_wrpacket(priv, chan->buffer, chidx, wrsize); - } - - /* Did we put the entire buffer into the Tx FIFO? */ - - if (chan->buflen > avail) - { - /* No, there was insufficient space to hold the entire transfer ... - * Enable the Tx FIFO interrupt to handle the transfer when the Tx - * FIFO becomes empty. - */ - - stm32_txfe_enable(priv, chidx); - } - } -} - -/**************************************************************************** - * Name: stm32_getframe - * - * Description: - * Get the current frame number. The frame number (FRNUM) field increments - * when a new SOF is transmitted on the USB, and is cleared to 0 when it - * reaches 0x3fff. - * - ****************************************************************************/ - -#if 0 /* Not used */ -static inline uint16_t stm32_getframe(void) -{ - return (uint16_t) - (stm32_getreg(STM32_OTGFS_HFNUM) & OTGFS_HFNUM_FRNUM_MASK); -} -#endif - -/**************************************************************************** - * Name: stm32_ctrl_sendsetup - * - * Description: - * Send an IN/OUT SETUP packet. - * - ****************************************************************************/ - -static int stm32_ctrl_sendsetup(struct stm32_usbhost_s *priv, - struct stm32_ctrlinfo_s *ep0, - const struct usb_ctrlreq_s *req) -{ - struct stm32_chan_s *chan; - clock_t start; - clock_t elapsed; - int ret; - - /* Loop while the device reports NAK (and a timeout is not exceeded */ - - chan = &priv->chan[ep0->outndx]; - start = clock_systime_ticks(); - - do - { - /* Send the SETUP packet */ - - chan->pid = OTGFS_PID_SETUP; - chan->buffer = (uint8_t *)req; - chan->buflen = USB_SIZEOF_CTRLREQ; - chan->xfrd = 0; - - /* Set up for the wait BEFORE starting the transfer */ - - ret = stm32_chan_waitsetup(priv, chan); - if (ret < 0) - { - usbhost_trace1(OTGFS_TRACE1_DEVDISCONN, 0); - return ret; - } - - /* Start the transfer */ - - stm32_transfer_start(priv, ep0->outndx); - - /* Wait for the transfer to complete */ - - ret = stm32_chan_wait(priv, chan); - - /* Return on success and for all failures other than EAGAIN. EAGAIN - * means that the device NAKed the SETUP command and that we should - * try a few more times. - */ - - if (ret != -EAGAIN) - { - /* Output some debug information if the transfer failed */ - - if (ret < 0) - { - usbhost_trace1(OTGFS_TRACE1_TRNSFRFAILED, ret); - } - - /* Return the result in any event */ - - return ret; - } - - /* Get the elapsed time (in frames) */ - - elapsed = clock_systime_ticks() - start; - } - while (elapsed < STM32_SETUP_DELAY); - - return -ETIMEDOUT; -} - -/**************************************************************************** - * Name: stm32_ctrl_senddata - * - * Description: - * Send data in the data phase of an OUT control transfer. Or send status - * in the status phase of an IN control transfer - * - ****************************************************************************/ - -static int stm32_ctrl_senddata(struct stm32_usbhost_s *priv, - struct stm32_ctrlinfo_s *ep0, - uint8_t *buffer, unsigned int buflen) -{ - struct stm32_chan_s *chan = &priv->chan[ep0->outndx]; - int ret; - - /* Save buffer information */ - - chan->buffer = buffer; - chan->buflen = buflen; - chan->xfrd = 0; - - /* Set the DATA PID */ - - if (buflen == 0) - { - /* For status OUT stage with buflen == 0, set PID DATA1 */ - - chan->outdata1 = true; - } - - /* Set the Data PID as per the outdata1 boolean */ - - chan->pid = chan->outdata1 ? OTGFS_PID_DATA1 : OTGFS_PID_DATA0; - - /* Set up for the wait BEFORE starting the transfer */ - - ret = stm32_chan_waitsetup(priv, chan); - if (ret < 0) - { - usbhost_trace1(OTGFS_TRACE1_DEVDISCONN, 0); - return ret; - } - - /* Start the transfer */ - - stm32_transfer_start(priv, ep0->outndx); - - /* Wait for the transfer to complete and return the result */ - - return stm32_chan_wait(priv, chan); -} - -/**************************************************************************** - * Name: stm32_ctrl_recvdata - * - * Description: - * Receive data in the data phase of an IN control transfer. Or receive - * status in the status phase of an OUT control transfer - * - ****************************************************************************/ - -static int stm32_ctrl_recvdata(struct stm32_usbhost_s *priv, - struct stm32_ctrlinfo_s *ep0, - uint8_t *buffer, unsigned int buflen) -{ - struct stm32_chan_s *chan = &priv->chan[ep0->inndx]; - int ret; - - /* Save buffer information */ - - chan->pid = OTGFS_PID_DATA1; - chan->buffer = buffer; - chan->buflen = buflen; - chan->xfrd = 0; - - /* Set up for the wait BEFORE starting the transfer */ - - ret = stm32_chan_waitsetup(priv, chan); - if (ret < 0) - { - usbhost_trace1(OTGFS_TRACE1_DEVDISCONN, 0); - return ret; - } - - /* Start the transfer */ - - stm32_transfer_start(priv, ep0->inndx); - - /* Wait for the transfer to complete and return the result */ - - return stm32_chan_wait(priv, chan); -} - -/**************************************************************************** - * Name: stm32_in_setup - * - * Description: - * Initiate an IN transfer on an bulk, interrupt, or isochronous pipe. - * - ****************************************************************************/ - -static int stm32_in_setup(struct stm32_usbhost_s *priv, int chidx) -{ - struct stm32_chan_s *chan; - - /* Set up for the transfer based on the direction and the endpoint type */ - - chan = &priv->chan[chidx]; - switch (chan->eptype) - { - default: - case OTGFS_EPTYPE_CTRL: /* Control */ - { - /* This kind of transfer on control endpoints other than EP0 are not - * currently supported - */ - - return -ENOSYS; - } - - case OTGFS_EPTYPE_ISOC: /* Isochronous */ - { - /* Set up the IN data PID */ - - usbhost_vtrace2(OTGFS_VTRACE2_ISOCIN, chidx, chan->buflen); - chan->pid = OTGFS_PID_DATA0; - } - break; - - case OTGFS_EPTYPE_BULK: /* Bulk */ - { - /* Setup the IN data PID */ - - usbhost_vtrace2(OTGFS_VTRACE2_BULKIN, chidx, chan->buflen); - chan->pid = chan->indata1 ? OTGFS_PID_DATA1 : OTGFS_PID_DATA0; - } - break; - - case OTGFS_EPTYPE_INTR: /* Interrupt */ - { - /* Setup the IN data PID */ - - usbhost_vtrace2(OTGFS_VTRACE2_INTRIN, chidx, chan->buflen); - chan->pid = chan->indata1 ? OTGFS_PID_DATA1 : OTGFS_PID_DATA0; - } - break; - } - - /* Start the transfer */ - - stm32_transfer_start(priv, chidx); - return OK; -} - -/**************************************************************************** - * Name: stm32_in_transfer - * - * Description: - * Transfer 'buflen' bytes into 'buffer' from an IN channel. - * - ****************************************************************************/ - -static ssize_t stm32_in_transfer(struct stm32_usbhost_s *priv, int chidx, - uint8_t *buffer, size_t buflen) -{ - struct stm32_chan_s *chan; - clock_t start; - ssize_t xfrd; - int ret; - - /* Loop until the transfer completes (i.e., buflen is decremented to zero) - * or a fatal error occurs any error other than a simple NAK. NAK would - * simply indicate the end of the transfer (short-transfer). - */ - - chan = &priv->chan[chidx]; - chan->buffer = buffer; - chan->buflen = buflen; - chan->xfrd = 0; - xfrd = 0; - - start = clock_systime_ticks(); - while (chan->xfrd < chan->buflen) - { - /* Set up for the wait BEFORE starting the transfer */ - - ret = stm32_chan_waitsetup(priv, chan); - if (ret < 0) - { - usbhost_trace1(OTGFS_TRACE1_DEVDISCONN, 0); - return (ssize_t)ret; - } - - /* Set up for the transfer based on the direction and the endpoint */ - - ret = stm32_in_setup(priv, chidx); - if (ret < 0) - { - uerr("ERROR: stm32_in_setup failed: %d\n", ret); - return (ssize_t)ret; - } - - /* Wait for the transfer to complete and get the result */ - - ret = stm32_chan_wait(priv, chan); - - /* EAGAIN indicates that the device NAKed the transfer. */ - - if (ret < 0) - { - /* The transfer failed. If we received a NAK, return all data - * buffered so far (if any). - */ - - if (ret == -EAGAIN) - { - /* Was data buffered prior to the NAK? */ - - if (xfrd > 0) - { - /* Yes, return the amount of data received. - * - * REVISIT: This behavior is clearly correct for CDC/ACM - * bulk transfers and HID interrupt transfers. But I am - * not so certain for MSC bulk transfers which, I think, - * could have NAKed packets in the middle of a transfer. - */ - - return xfrd; - } - else - { - useconds_t delay; - - /* Get the elapsed time. Has the timeout elapsed? - * if not then try again. - */ - - clock_t elapsed = clock_systime_ticks() - start; - if (elapsed >= STM32_DATANAK_DELAY) - { - /* Timeout out... break out returning the NAK as - * as a failure. - */ - - return (ssize_t)ret; - } - - /* Wait a bit before retrying after a NAK. */ - - if (chan->eptype == OTGFS_EPTYPE_INTR) - { - /* For interrupt (and isochronous) endpoints, the - * polling rate is determined by the bInterval field - * of the endpoint descriptor (in units of frames - * which we treat as milliseconds here). - */ - - if (chan->interval > 0) - { - /* Convert the delay to units of microseconds */ - - delay = (useconds_t)chan->interval * 1000; - } - else - { - /* Out of range! For interrupt endpoints, the valid - * range is 1-255 frames. Assume one frame. - */ - - delay = 1000; - } - } - else - { - /* For Isochronous endpoints, bInterval must be 1. - * Bulk endpoints do not have a polling interval. - * Rather, the should wait until data is received. - * - * REVISIT: For bulk endpoints this 1 msec delay is - * only intended to give the CPU a break from the bulk - * EP tight polling loop. But are there performance - * issues? - */ - - delay = 1000; - } - - /* Wait for the next polling interval. For interrupt and - * isochronous endpoints, this is necessary to assure the - * polling interval. It is used in other cases only to - * prevent the polling from consuming too much CPU - * bandwidth. - * - * Small delays could require more resolution than is - * provided by the system timer. For example, if the - * system timer resolution is 10MS, then - * nxsched_usleep(1000) will actually request a delay 20MS - * (due to both quantization and rounding). - * - * REVISIT: So which is better? To ignore tiny delays and - * hog the system bandwidth? Or to wait for an excessive - * amount and destroy system throughput? - */ - - if (delay > CONFIG_USEC_PER_TICK) - { - nxsched_usleep(delay - CONFIG_USEC_PER_TICK); - } - } - } - else - { - /* Some unexpected, fatal error occurred. */ - - usbhost_trace1(OTGFS_TRACE1_TRNSFRFAILED, ret); - - /* Break out and return the error */ - - uerr("ERROR: stm32_chan_wait failed: %d\n", ret); - return (ssize_t)ret; - } - } - else - { - /* Successfully received another chunk of data... add that to the - * running total. Then continue reading until we read 'buflen' - * bytes of data or until the devices NAKs (implying a short - * packet). - */ - - xfrd += chan->xfrd; - } - } - - return xfrd; -} - -/**************************************************************************** - * Name: stm32_in_next - * - * Description: - * Initiate the next of a sequence of asynchronous transfers. - * - * Assumptions: - * This function is always called from an interrupt handler - * - ****************************************************************************/ - -#ifdef CONFIG_USBHOST_ASYNCH -static void stm32_in_next(struct stm32_usbhost_s *priv, - struct stm32_chan_s *chan) -{ - usbhost_asynch_t callback; - void *arg; - ssize_t nbytes; - int result; - int ret; - - /* Is the full transfer complete? Did the last chunk transfer OK? */ - - result = -(int)chan->result; - if (chan->xfrd < chan->buflen && result == OK) - { - /* Yes.. Set up for the next transfer based on the direction and the - * endpoint type - */ - - ret = stm32_in_setup(priv, chan->chidx); - if (ret >= 0) - { - return; - } - - uerr("ERROR: stm32_in_setup failed: %d\n", ret); - result = ret; - } - - /* The transfer is complete, with or without an error */ - - uinfo("Transfer complete: %d\n", result); - - /* Extract the callback information */ - - callback = chan->callback; - arg = chan->arg; - nbytes = chan->xfrd; - - chan->callback = NULL; - chan->arg = NULL; - chan->xfrd = 0; - - /* Then perform the callback */ - - if (result < 0) - { - nbytes = (ssize_t)result; - } - - callback(arg, nbytes); -} -#endif - -/**************************************************************************** - * Name: stm32_in_asynch - * - * Description: - * Initiate the first of a sequence of asynchronous transfers. - * - * Assumptions: - * This function is never called from an interrupt handler - * - ****************************************************************************/ - -#ifdef CONFIG_USBHOST_ASYNCH -static int stm32_in_asynch(struct stm32_usbhost_s *priv, int chidx, - uint8_t *buffer, size_t buflen, - usbhost_asynch_t callback, void *arg) -{ - struct stm32_chan_s *chan; - int ret; - - /* Set up for the transfer BEFORE starting the first transfer */ - - chan = &priv->chan[chidx]; - chan->buffer = buffer; - chan->buflen = buflen; - chan->xfrd = 0; - - ret = stm32_chan_asynchsetup(priv, chan, callback, arg); - if (ret < 0) - { - uerr("ERROR: stm32_chan_asynchsetup failed: %d\n", ret); - return ret; - } - - /* Set up for the transfer based on the direction and the endpoint type */ - - ret = stm32_in_setup(priv, chidx); - if (ret < 0) - { - uerr("ERROR: stm32_in_setup failed: %d\n", ret); - } - - /* And return with the transfer pending */ - - return ret; -} -#endif - -/**************************************************************************** - * Name: stm32_out_setup - * - * Description: - * Initiate an OUT transfer on an bulk, interrupt, or isochronous pipe. - * - ****************************************************************************/ - -static int stm32_out_setup(struct stm32_usbhost_s *priv, int chidx) -{ - struct stm32_chan_s *chan; - - /* Set up for the transfer based on the direction and the endpoint type */ - - chan = &priv->chan[chidx]; - switch (chan->eptype) - { - default: - case OTGFS_EPTYPE_CTRL: /* Control */ - { - /* This kind of transfer on control endpoints other than EP0 are not - * currently supported - */ - - return -ENOSYS; - } - - case OTGFS_EPTYPE_ISOC: /* Isochronous */ - { - /* Set up the OUT data PID */ - - usbhost_vtrace2(OTGFS_VTRACE2_ISOCOUT, chidx, chan->buflen); - chan->pid = OTGFS_PID_DATA0; - } - break; - - case OTGFS_EPTYPE_BULK: /* Bulk */ - { - /* Setup the OUT data PID */ - - usbhost_vtrace2(OTGFS_VTRACE2_BULKOUT, chidx, chan->buflen); - chan->pid = chan->outdata1 ? OTGFS_PID_DATA1 : OTGFS_PID_DATA0; - } - break; - - case OTGFS_EPTYPE_INTR: /* Interrupt */ - { - /* Setup the OUT data PID */ - - usbhost_vtrace2(OTGFS_VTRACE2_INTROUT, chidx, chan->buflen); - chan->pid = chan->outdata1 ? OTGFS_PID_DATA1 : OTGFS_PID_DATA0; - - /* Toggle the OUT data PID for the next transfer */ - - chan->outdata1 ^= true; - } - break; - } - - /* Start the transfer */ - - stm32_transfer_start(priv, chidx); - return OK; -} - -/**************************************************************************** - * Name: stm32_out_transfer - * - * Description: - * Transfer the 'buflen' bytes in 'buffer' through an OUT channel. - * - ****************************************************************************/ - -static ssize_t stm32_out_transfer(struct stm32_usbhost_s *priv, - int chidx, uint8_t *buffer, - size_t buflen) -{ - struct stm32_chan_s *chan; - clock_t start; - clock_t elapsed; - size_t xfrlen; - ssize_t xfrd; - int ret; - bool zlp; - - /* Loop until the transfer completes (i.e., buflen is decremented to zero) - * or a fatal error occurs (any error other than a simple NAK) - */ - - chan = &priv->chan[chidx]; - start = clock_systime_ticks(); - xfrd = 0; - zlp = (buflen == 0); - - while (buflen > 0 || zlp) - { - /* Transfer one packet at a time. The hardware is capable of queueing - * multiple OUT packets, but I just haven't figured out how to handle - * the case where a single OUT packet in the group is NAKed. - */ - - xfrlen = MIN(chan->maxpacket, buflen); - chan->buffer = buffer; - chan->buflen = xfrlen; - chan->xfrd = 0; - - /* Set up for the wait BEFORE starting the transfer */ - - ret = stm32_chan_waitsetup(priv, chan); - if (ret < 0) - { - usbhost_trace1(OTGFS_TRACE1_DEVDISCONN, 0); - return (ssize_t)ret; - } - - /* Set up for the transfer based on the direction and the endpoint */ - - ret = stm32_out_setup(priv, chidx); - if (ret < 0) - { - uerr("ERROR: stm32_out_setup failed: %d\n", ret); - return (ssize_t)ret; - } - - /* Wait for the transfer to complete and get the result */ - - ret = stm32_chan_wait(priv, chan); - - /* Handle transfer failures */ - - if (ret < 0) - { - usbhost_trace1(OTGFS_TRACE1_TRNSFRFAILED, ret); - - /* Check for a special case: If (1) the transfer was NAKed and (2) - * no Tx FIFO empty or Rx FIFO not-empty event occurred, then we - * should be able to just flush the Rx and Tx FIFOs and try again. - * We can detect this latter case because then the transfer buffer - * pointer and buffer size will be unaltered. - */ - - elapsed = clock_systime_ticks() - start; - if (ret != -EAGAIN || /* Not a NAK condition OR */ - elapsed >= STM32_DATANAK_DELAY || /* Timeout has elapsed OR */ - chan->xfrd > 0) /* Data has been partially transferred */ - { - /* Break out and return the error */ - - uerr("ERROR: stm32_chan_wait failed: %d\n", ret); - return (ssize_t)ret; - } - - /* Is this flush really necessary? What does the hardware do with - * the data in the FIFO when the NAK occurs? Does it discard it? - */ - - stm32_flush_txfifos(OTGFS_GRSTCTL_TXFNUM_HALL); - - /* Get the device a little time to catch up. Then retry the - * transfer using the same buffer pointer and length. - */ - - nxsched_usleep(20 * 1000); - } - else - { - /* Successfully transferred. Update the buffer pointer/length */ - - buffer += xfrlen; - buflen -= xfrlen; - xfrd += chan->xfrd; - zlp = false; - } - } - - return xfrd; -} - -/**************************************************************************** - * Name: stm32_out_next - * - * Description: - * Initiate the next of a sequence of asynchronous transfers. - * - * Assumptions: - * This function is always called from an interrupt handler - * - ****************************************************************************/ - -#ifdef CONFIG_USBHOST_ASYNCH -static void stm32_out_next(struct stm32_usbhost_s *priv, - struct stm32_chan_s *chan) -{ - usbhost_asynch_t callback; - void *arg; - ssize_t nbytes; - int result; - int ret; - - /* Is the full transfer complete? Did the last chunk transfer OK? */ - - result = -(int)chan->result; - if (chan->xfrd < chan->buflen && result == OK) - { - /* Yes.. Set up for the next transfer based on the direction and the - * endpoint type - */ - - ret = stm32_out_setup(priv, chan->chidx); - if (ret >= 0) - { - return; - } - - uerr("ERROR: stm32_out_setup failed: %d\n", ret); - result = ret; - } - - /* The transfer is complete, with or without an error */ - - uinfo("Transfer complete: %d\n", result); - - /* Extract the callback information */ - - callback = chan->callback; - arg = chan->arg; - nbytes = chan->xfrd; - - chan->callback = NULL; - chan->arg = NULL; - chan->xfrd = 0; - - /* Then perform the callback */ - - if (result < 0) - { - nbytes = (ssize_t)result; - } - - callback(arg, nbytes); -} -#endif - -/**************************************************************************** - * Name: stm32_out_asynch - * - * Description: - * Initiate the first of a sequence of asynchronous transfers. - * - * Assumptions: - * This function is never called from an interrupt handler - * - ****************************************************************************/ - -#ifdef CONFIG_USBHOST_ASYNCH -static int stm32_out_asynch(struct stm32_usbhost_s *priv, int chidx, - uint8_t *buffer, size_t buflen, - usbhost_asynch_t callback, void *arg) -{ - struct stm32_chan_s *chan; - int ret; - - /* Set up for the transfer BEFORE starting the first transfer */ - - chan = &priv->chan[chidx]; - chan->buffer = buffer; - chan->buflen = buflen; - chan->xfrd = 0; - - ret = stm32_chan_asynchsetup(priv, chan, callback, arg); - if (ret < 0) - { - uerr("ERROR: stm32_chan_asynchsetup failed: %d\n", ret); - return ret; - } - - /* Set up for the transfer based on the direction and the endpoint type */ - - ret = stm32_out_setup(priv, chidx); - if (ret < 0) - { - uerr("ERROR: stm32_out_setup failed: %d\n", ret); - } - - /* And return with the transfer pending */ - - return ret; -} -#endif - -/**************************************************************************** - * Name: stm32_gint_wrpacket - * - * Description: - * Transfer the 'buflen' bytes in 'buffer' to the Tx FIFO associated with - * 'chidx' (non-DMA). - * - ****************************************************************************/ - -static void stm32_gint_wrpacket(struct stm32_usbhost_s *priv, - uint8_t *buffer, int chidx, int buflen) -{ - uint32_t *src; - uint32_t fifo; - int buflen32; - - stm32_pktdump("Sending", buffer, buflen); - - /* Get the number of 32-byte words associated with this byte size */ - - buflen32 = (buflen + 3) >> 2; - - /* Get the address of the Tx FIFO associated with this channel */ - - fifo = STM32_OTGFS_DFIFO_HCH(chidx); - - /* Transfer all of the data into the Tx FIFO */ - - src = (uint32_t *)buffer; - for (; buflen32 > 0; buflen32--) - { - uint32_t data = *src++; - stm32_putreg(fifo, data); - } - - /* Increment the count of bytes "in-flight" in the Tx FIFO */ - - priv->chan[chidx].inflight += buflen; -} - -/**************************************************************************** - * Name: stm32_gint_hcinisr - * - * Description: - * USB OTG FS host IN channels interrupt handler - * - * One the completion of the transfer, the channel result byte may be set - * as follows: - * - * OK - Transfer completed successfully - * EAGAIN - If devices NAKs the transfer or NYET occurs - * EPERM - If the endpoint stalls - * EIO - On a TX or data toggle error - * EPIPE - Frame overrun - * - * EBUSY in the result field indicates that the transfer has not completed. - * - ****************************************************************************/ - -static inline void stm32_gint_hcinisr(struct stm32_usbhost_s *priv, - int chidx) -{ - struct stm32_chan_s *chan = &priv->chan[chidx]; - uint32_t regval; - uint32_t pending; - - /* Read the HCINT register to get the pending HC interrupts. Read the - * HCINTMSK register to get the set of enabled HC interrupts. - */ - - pending = stm32_getreg(STM32_OTGFS_HCINT(chidx)); - regval = stm32_getreg(STM32_OTGFS_HCINTMSK(chidx)); - - /* AND the two to get the set of enabled, pending HC interrupts */ - - pending &= regval; - uinfo("HCINTMSK%d: %08" PRIx32 " pending: %08" PRIx32 "\n", - chidx, regval, pending); - - /* Check for a pending ACK response received/transmitted interrupt */ - - if ((pending & OTGFS_HCINT_ACK) != 0) - { - /* Clear the pending the ACK response received/transmitted interrupt */ - - stm32_putreg(STM32_OTGFS_HCINT(chidx), OTGFS_HCINT_ACK); - } - - /* Check for a pending STALL response receive (STALL) interrupt */ - - else if ((pending & OTGFS_HCINT_STALL) != 0) - { - /* Clear the NAK and STALL Conditions. */ - - stm32_putreg(STM32_OTGFS_HCINT(chidx), - OTGFS_HCINT_NAK | OTGFS_HCINT_STALL); - - /* Halt the channel when a STALL, TXERR, BBERR or DTERR interrupt is - * received on the channel. - */ - - stm32_chan_halt(priv, chidx, CHREASON_STALL); - - /* When there is a STALL, clear any pending NAK so that it is not - * processed below. - */ - - pending &= ~OTGFS_HCINT_NAK; - } - - /* Check for a pending Data Toggle ERRor (DTERR) interrupt */ - - else if ((pending & OTGFS_HCINT_DTERR) != 0) - { - /* Halt the channel when a STALL, TXERR, BBERR or DTERR interrupt is - * received on the channel. - */ - - stm32_chan_halt(priv, chidx, CHREASON_DTERR); - - /* Clear the NAK and data toggle error conditions */ - - stm32_putreg(STM32_OTGFS_HCINT(chidx), - OTGFS_HCINT_NAK | OTGFS_HCINT_DTERR); - } - - /* Check for a pending FRaMe OverRun (FRMOR) interrupt */ - - if ((pending & OTGFS_HCINT_FRMOR) != 0) - { - /* Halt the channel -- the CHH interrupt is expected next */ - - stm32_chan_halt(priv, chidx, CHREASON_FRMOR); - - /* Clear the FRaMe OverRun (FRMOR) condition */ - - stm32_putreg(STM32_OTGFS_HCINT(chidx), OTGFS_HCINT_FRMOR); - } - - /* Check for a pending TransFeR Completed (XFRC) interrupt */ - - else if ((pending & OTGFS_HCINT_XFRC) != 0) - { - /* Clear the TransFeR Completed (XFRC) condition */ - - stm32_putreg(STM32_OTGFS_HCINT(chidx), OTGFS_HCINT_XFRC); - - /* Then handle the transfer completion event based on the endpoint */ - - if (chan->eptype == OTGFS_EPTYPE_CTRL || - chan->eptype == OTGFS_EPTYPE_BULK) - { - /* Halt the channel -- the CHH interrupt is expected next */ - - stm32_chan_halt(priv, chidx, CHREASON_XFRC); - - /* Clear any pending NAK condition. The 'indata1' data toggle - * should have been appropriately updated by the RxFIFO - * logic as each packet was received. - */ - - stm32_putreg(STM32_OTGFS_HCINT(chidx), OTGFS_HCINT_NAK); - } - else if (chan->eptype == OTGFS_EPTYPE_INTR) - { - /* Force the next transfer on an ODD frame */ - - regval = stm32_getreg(STM32_OTGFS_HCCHAR(chidx)); - regval |= OTGFS_HCCHAR_ODDFRM; - stm32_putreg(STM32_OTGFS_HCCHAR(chidx), regval); - - /* Set the request done state */ - - chan->result = OK; - } - } - - /* Check for a pending CHannel Halted (CHH) interrupt */ - - else if ((pending & OTGFS_HCINT_CHH) != 0) - { - /* Mask the CHannel Halted (CHH) interrupt */ - - regval = stm32_getreg(STM32_OTGFS_HCINTMSK(chidx)); - regval &= ~OTGFS_HCINT_CHH; - stm32_putreg(STM32_OTGFS_HCINTMSK(chidx), regval); - - /* Update the request state based on the host state machine state */ - - if (chan->chreason == CHREASON_XFRC) - { - /* Set the request done result */ - - chan->result = OK; - } - else if (chan->chreason == CHREASON_STALL) - { - /* Set the request stall result */ - - chan->result = EPERM; - } - else if ((chan->chreason == CHREASON_TXERR) || - (chan->chreason == CHREASON_DTERR)) - { - /* Set the request I/O error result */ - - chan->result = EIO; - } - else if (chan->chreason == CHREASON_NAK) - { - /* Set the NAK error result */ - - chan->result = EAGAIN; - } - else /* if (chan->chreason == CHREASON_FRMOR) */ - { - /* Set the frame overrun error result */ - - chan->result = EPIPE; - } - - /* Clear the CHannel Halted (CHH) condition */ - - stm32_putreg(STM32_OTGFS_HCINT(chidx), OTGFS_HCINT_CHH); - } - - /* Check for a pending Transaction ERror (TXERR) interrupt */ - - else if ((pending & OTGFS_HCINT_TXERR) != 0) - { - /* Halt the channel when a STALL, TXERR, BBERR or DTERR interrupt is - * received on the channel. - */ - - stm32_chan_halt(priv, chidx, CHREASON_TXERR); - - /* Clear the Transaction ERror (TXERR) condition */ - - stm32_putreg(STM32_OTGFS_HCINT(chidx), OTGFS_HCINT_TXERR); - } - - /* Check for a pending NAK response received (NAK) interrupt */ - - else if ((pending & OTGFS_HCINT_NAK) != 0) - { - /* For a BULK transfer, the hardware is capable of retrying - * automatically on a NAK. However, this is not always - * what we need to do. So we always halt the transfer and - * return control to high level logic in the event of a NAK. - */ - -#if 1 - /* Halt the interrupt channel */ - - if (chan->eptype == OTGFS_EPTYPE_INTR || - chan->eptype == OTGFS_EPTYPE_BULK) - { - /* Halt the channel -- the CHH interrupt is expected next */ - - stm32_chan_halt(priv, chidx, CHREASON_NAK); - } - - /* Re-activate CTRL and BULK channels. - * - * REVISIT: This can cause a lot of interrupts! - * REVISIT: BULK endpoints are not re-activated. - */ - - else if (chan->eptype == OTGFS_EPTYPE_CTRL) - { - /* Re-activate the channel by clearing CHDIS and assuring that - * CHENA is set - * - * TODO: set channel reason to NACK? - */ - - regval = stm32_getreg(STM32_OTGFS_HCCHAR(chidx)); - regval |= OTGFS_HCCHAR_CHENA; - regval &= ~OTGFS_HCCHAR_CHDIS; - stm32_putreg(STM32_OTGFS_HCCHAR(chidx), regval); - } - -#else - /* Halt all transfers on the NAK -- CHH interrupt is expected next */ - - stm32_chan_halt(priv, chidx, CHREASON_NAK); -#endif - - /* Clear the NAK condition */ - - stm32_putreg(STM32_OTGFS_HCINT(chidx), OTGFS_HCINT_NAK); - } - - /* Check for a transfer complete event */ - - stm32_chan_wakeup(priv, chan); -} - -/**************************************************************************** - * Name: stm32_gint_hcoutisr - * - * Description: - * USB OTG FS host OUT channels interrupt handler - * - * One the completion of the transfer, the channel result byte may be set - * as follows: - * - * OK - Transfer completed successfully - * EAGAIN - If devices NAKs the transfer or NYET occurs - * EPERM - If the endpoint stalls - * EIO - On a TX or data toggle error - * EPIPE - Frame overrun - * - * EBUSY in the result field indicates that the transfer has not completed. - * - ****************************************************************************/ - -static inline void stm32_gint_hcoutisr(struct stm32_usbhost_s *priv, - int chidx) -{ - struct stm32_chan_s *chan = &priv->chan[chidx]; - uint32_t regval; - uint32_t pending; - - /* Read the HCINT register to get the pending HC interrupts. Read the - * HCINTMSK register to get the set of enabled HC interrupts. - */ - - pending = stm32_getreg(STM32_OTGFS_HCINT(chidx)); - regval = stm32_getreg(STM32_OTGFS_HCINTMSK(chidx)); - - /* AND the two to get the set of enabled, pending HC interrupts */ - - pending &= regval; - uinfo("HCINTMSK%d: %08" PRIx32 " pending: %08" PRIx32 "\n", - chidx, regval, pending); - - /* Check for a pending ACK response received/transmitted interrupt */ - - if ((pending & OTGFS_HCINT_ACK) != 0) - { - /* Clear the pending the ACK response received/transmitted interrupt */ - - stm32_putreg(STM32_OTGFS_HCINT(chidx), OTGFS_HCINT_ACK); - } - - /* Check for a pending FRaMe OverRun (FRMOR) interrupt */ - - else if ((pending & OTGFS_HCINT_FRMOR) != 0) - { - /* Halt the channel (probably not necessary for FRMOR) */ - - stm32_chan_halt(priv, chidx, CHREASON_FRMOR); - - /* Clear the pending the FRaMe OverRun (FRMOR) interrupt */ - - stm32_putreg(STM32_OTGFS_HCINT(chidx), OTGFS_HCINT_FRMOR); - } - - /* Check for a pending TransFeR Completed (XFRC) interrupt */ - - else if ((pending & OTGFS_HCINT_XFRC) != 0) - { - /* Decrement the number of bytes remaining by the number of - * bytes that were "in-flight". - */ - - priv->chan[chidx].buffer += priv->chan[chidx].inflight; - priv->chan[chidx].xfrd += priv->chan[chidx].inflight; - priv->chan[chidx].inflight = 0; - - /* Halt the channel -- the CHH interrupt is expected next */ - - stm32_chan_halt(priv, chidx, CHREASON_XFRC); - - /* Clear the pending the TransFeR Completed (XFRC) interrupt */ - - stm32_putreg(STM32_OTGFS_HCINT(chidx), OTGFS_HCINT_XFRC); - } - - /* Check for a pending STALL response receive (STALL) interrupt */ - - else if ((pending & OTGFS_HCINT_STALL) != 0) - { - /* Clear the pending the STALL response receive (STALL) interrupt */ - - stm32_putreg(STM32_OTGFS_HCINT(chidx), OTGFS_HCINT_STALL); - - /* Halt the channel when a STALL, TXERR, BBERR or DTERR interrupt is - * received on the channel. - */ - - stm32_chan_halt(priv, chidx, CHREASON_STALL); - } - - /* Check for a pending NAK response received (NAK) interrupt */ - - else if ((pending & OTGFS_HCINT_NAK) != 0) - { - /* Halt the channel -- the CHH interrupt is expected next */ - - stm32_chan_halt(priv, chidx, CHREASON_NAK); - - /* Clear the pending the NAK response received (NAK) interrupt */ - - stm32_putreg(STM32_OTGFS_HCINT(chidx), OTGFS_HCINT_NAK); - } - - /* Check for a pending Transaction ERror (TXERR) interrupt */ - - else if ((pending & OTGFS_HCINT_TXERR) != 0) - { - /* Halt the channel when a STALL, TXERR, BBERR or DTERR interrupt is - * received on the channel. - */ - - stm32_chan_halt(priv, chidx, CHREASON_TXERR); - - /* Clear the pending the Transaction ERror (TXERR) interrupt */ - - stm32_putreg(STM32_OTGFS_HCINT(chidx), OTGFS_HCINT_TXERR); - } - - /* Check for a NYET interrupt */ - -#if 0 /* NYET is a reserved bit in the HCINT register */ - else if ((pending & OTGFS_HCINT_NYET) != 0) - { - /* Halt the channel */ - - stm32_chan_halt(priv, chidx, CHREASON_NYET); - - /* Clear the pending the NYET interrupt */ - - stm32_putreg(STM32_OTGFS_HCINT(chidx), OTGFS_HCINT_NYET); - } -#endif - - /* Check for a pending Data Toggle ERRor (DTERR) interrupt */ - - else if (pending & OTGFS_HCINT_DTERR) - { - /* Halt the channel when a STALL, TXERR, BBERR or DTERR interrupt is - * received on the channel. - */ - - stm32_chan_halt(priv, chidx, CHREASON_DTERR); - - /* Clear the pending the Data Toggle ERRor (DTERR) and NAK interrupts */ - - stm32_putreg(STM32_OTGFS_HCINT(chidx), - OTGFS_HCINT_DTERR | OTGFS_HCINT_NAK); - } - - /* Check for a pending CHannel Halted (CHH) interrupt */ - - else if ((pending & OTGFS_HCINT_CHH) != 0) - { - /* Mask the CHannel Halted (CHH) interrupt */ - - regval = stm32_getreg(STM32_OTGFS_HCINTMSK(chidx)); - regval &= ~OTGFS_HCINT_CHH; - stm32_putreg(STM32_OTGFS_HCINTMSK(chidx), regval); - - if (chan->chreason == CHREASON_XFRC) - { - /* Set the request done result */ - - chan->result = OK; - - /* Read the HCCHAR register to get the HCCHAR register to get - * the endpoint type. - */ - - regval = stm32_getreg(STM32_OTGFS_HCCHAR(chidx)); - - /* Is it a bulk endpoint? Were an odd number of packets - * transferred? - */ - - if ((regval & OTGFS_HCCHAR_EPTYP_MASK) == - OTGFS_HCCHAR_EPTYP_BULK && - (chan->npackets & 1) != 0) - { - /* Yes to both... toggle the data out PID */ - - chan->outdata1 ^= true; - } - } - else if (chan->chreason == CHREASON_NAK || - chan->chreason == CHREASON_NYET) - { - /* Set the try again later result */ - - chan->result = EAGAIN; - } - else if (chan->chreason == CHREASON_STALL) - { - /* Set the request stall result */ - - chan->result = EPERM; - } - else if ((chan->chreason == CHREASON_TXERR) || - (chan->chreason == CHREASON_DTERR)) - { - /* Set the I/O failure result */ - - chan->result = EIO; - } - else /* if (chan->chreason == CHREASON_FRMOR) */ - { - /* Set the frame error result */ - - chan->result = EPIPE; - } - - /* Clear the pending the CHannel Halted (CHH) interrupt */ - - stm32_putreg(STM32_OTGFS_HCINT(chidx), OTGFS_HCINT_CHH); - } - - /* Check for a transfer complete event */ - - stm32_chan_wakeup(priv, chan); -} - -/**************************************************************************** - * Name: stm32_gint_connected - * - * Description: - * Handle a connection event. - * - ****************************************************************************/ - -static void stm32_gint_connected(struct stm32_usbhost_s *priv) -{ - /* We we previously disconnected? */ - - if (!priv->connected) - { - /* Yes.. then now we are connected */ - - usbhost_vtrace1(OTGFS_VTRACE1_CONNECTED, 0); - priv->connected = true; - priv->change = true; - DEBUGASSERT(priv->smstate == SMSTATE_DETACHED); - - /* Notify any waiters */ - - priv->smstate = SMSTATE_ATTACHED; - if (priv->pscwait) - { - nxsem_post(&priv->pscsem); - priv->pscwait = false; - } - } -} - -/**************************************************************************** - * Name: stm32_gint_disconnected - * - * Description: - * Handle a disconnection event. - * - ****************************************************************************/ - -static void stm32_gint_disconnected(struct stm32_usbhost_s *priv) -{ - /* Were we previously connected? */ - - if (priv->connected) - { - /* Yes.. then we no longer connected */ - - usbhost_vtrace1(OTGFS_VTRACE1_DISCONNECTED, 0); - - /* Are we bound to a class driver? */ - - if (priv->rhport.hport.devclass) - { - /* Yes.. Disconnect the class driver */ - - CLASS_DISCONNECTED(priv->rhport.hport.devclass); - priv->rhport.hport.devclass = NULL; - } - - /* Re-Initialize Host for new Enumeration */ - - priv->smstate = SMSTATE_DETACHED; - priv->connected = false; - priv->change = true; - stm32_chan_freeall(priv); - - priv->rhport.hport.speed = USB_SPEED_FULL; - priv->rhport.hport.funcaddr = 0; - - /* Notify any waiters that there is a change in the connection state */ - - if (priv->pscwait) - { - nxsem_post(&priv->pscsem); - priv->pscwait = false; - } - } -} - -/**************************************************************************** - * Name: stm32_gint_sofisr - * - * Description: - * USB OTG FS start-of-frame interrupt handler - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_OTGFS_SOFINTR -static inline void stm32_gint_sofisr(struct stm32_usbhost_s *priv) -{ - /* Handle SOF interrupt */ - -#warning "Do what?" - - /* Clear pending SOF interrupt */ - - stm32_putreg(STM32_OTGFS_GINTSTS, OTGFS_GINT_SOF); -} -#endif - -/**************************************************************************** - * Name: stm32_gint_rxflvlisr - * - * Description: - * USB OTG FS RxFIFO non-empty interrupt handler - * - ****************************************************************************/ - -static inline void stm32_gint_rxflvlisr(struct stm32_usbhost_s *priv) -{ - uint32_t *dest; - uint32_t grxsts; - uint32_t intmsk; - uint32_t hcchar; - uint32_t hctsiz; - uint32_t fifo; - int bcnt; - int bcnt32; - int chidx; - int i; - - /* Disable the RxFIFO non-empty interrupt */ - - intmsk = stm32_getreg(STM32_OTGFS_GINTMSK); - intmsk &= ~OTGFS_GINT_RXFLVL; - stm32_putreg(STM32_OTGFS_GINTMSK, intmsk); - - /* Read and pop the next status from the Rx FIFO */ - - grxsts = stm32_getreg(STM32_OTGFS_GRXSTSP); - uinfo("GRXSTS: %08" PRIx32 "\n", grxsts); - - /* Isolate the channel number/index in the status word */ - - chidx = (grxsts & OTGFS_GRXSTSH_CHNUM_MASK) >> OTGFS_GRXSTSH_CHNUM_SHIFT; - - /* Get the host channel characteristics register (HCCHAR) */ - - hcchar = stm32_getreg(STM32_OTGFS_HCCHAR(chidx)); - - /* Then process the interrupt according to the packet status */ - - switch (grxsts & OTGFS_GRXSTSH_PKTSTS_MASK) - { - case OTGFS_GRXSTSH_PKTSTS_INRECVD: /* IN data packet received */ - { - /* Read the data into the host buffer. */ - - bcnt = (grxsts & OTGFS_GRXSTSH_BCNT_MASK) >> - OTGFS_GRXSTSH_BCNT_SHIFT; - if (bcnt > 0 && priv->chan[chidx].buffer != NULL) - { - /* Transfer the packet from the Rx FIFO into the user buffer */ - - dest = (uint32_t *)priv->chan[chidx].buffer; - fifo = STM32_OTGFS_DFIFO_HCH(0); - bcnt32 = (bcnt + 3) >> 2; - - for (i = 0; i < bcnt32; i++) - { - *dest++ = stm32_getreg(fifo); - } - - stm32_pktdump("Received", priv->chan[chidx].buffer, bcnt); - - /* Toggle the IN data pid (Used by Bulk and INTR only) */ - - priv->chan[chidx].indata1 ^= true; - - /* Manage multiple packet transfers */ - - priv->chan[chidx].buffer += bcnt; - priv->chan[chidx].xfrd += bcnt; - - /* Check if more packets are expected */ - - hctsiz = stm32_getreg(STM32_OTGFS_HCTSIZ(chidx)); - if ((hctsiz & OTGFS_HCTSIZ_PKTCNT_MASK) != 0) - { - /* Re-activate the channel when more packets are expected */ - - hcchar |= OTGFS_HCCHAR_CHENA; - hcchar &= ~OTGFS_HCCHAR_CHDIS; - stm32_putreg(STM32_OTGFS_HCCHAR(chidx), hcchar); - } - } - } - break; - - case OTGFS_GRXSTSH_PKTSTS_INDONE: /* IN transfer completed */ - case OTGFS_GRXSTSH_PKTSTS_DTOGERR: /* Data toggle error */ - case OTGFS_GRXSTSH_PKTSTS_HALTED: /* Channel halted */ - default: - break; - } - - /* Re-enable the RxFIFO non-empty interrupt */ - - intmsk |= OTGFS_GINT_RXFLVL; - stm32_putreg(STM32_OTGFS_GINTMSK, intmsk); -} - -/**************************************************************************** - * Name: stm32_gint_nptxfeisr - * - * Description: - * USB OTG FS non-periodic TxFIFO empty interrupt handler - * - ****************************************************************************/ - -static inline void stm32_gint_nptxfeisr(struct stm32_usbhost_s *priv) -{ - struct stm32_chan_s *chan; - uint32_t regval; - unsigned int wrsize; - unsigned int avail; - unsigned int chidx; - - /* Recover the index of the channel that is waiting for space in the Tx - * FIFO. - */ - - chidx = priv->chidx; - chan = &priv->chan[chidx]; - - /* Reduce the buffer size by the number of bytes that were previously - * placed in the Tx FIFO. - */ - - chan->buffer += chan->inflight; - chan->xfrd += chan->inflight; - chan->inflight = 0; - - /* If we have now transferred the entire buffer, then this transfer is - * complete (this case really should never happen because we disable - * the NPTXFE interrupt on the final packet). - */ - - if (chan->xfrd >= chan->buflen) - { - /* Disable further Tx FIFO empty interrupts and bail. */ - - stm32_modifyreg(STM32_OTGFS_GINTMSK, OTGFS_GINT_NPTXFE, 0); - return; - } - - /* Read the status from the top of the non-periodic TxFIFO */ - - regval = stm32_getreg(STM32_OTGFS_HNPTXSTS); - - /* Extract the number of bytes available in the non-periodic Tx FIFO. */ - - avail = ((regval & OTGFS_HNPTXSTS_NPTXFSAV_MASK) >> - OTGFS_HNPTXSTS_NPTXFSAV_SHIFT) << 2; - - /* Get the size to put in the Tx FIFO now */ - - wrsize = chan->buflen - chan->xfrd; - - /* Get minimal size packet that can be sent. Something is seriously - * configured wrong if one packet will not fit into the empty Tx FIFO. - */ - - DEBUGASSERT(wrsize > 0 && avail >= MIN(wrsize, chan->maxpacket)); - if (wrsize > avail) - { - /* Clip the write size to the number of full, max sized packets - * that will fit in the Tx FIFO. - */ - - unsigned int wrpackets = avail / chan->maxpacket; - wrsize = wrpackets * chan->maxpacket; - } - - /* Otherwise, this will be the last packet to be sent in this transaction. - * We now need to disable further NPTXFE interrupts. - */ - - else - { - stm32_modifyreg(STM32_OTGFS_GINTMSK, OTGFS_GINT_NPTXFE, 0); - } - - /* Write the next group of packets into the Tx FIFO */ - - uinfo("HNPTXSTS: %08" PRIx32 " chidx: %d avail: %d buflen: %d xfrd: %d " - "wrsize: %d\n", - regval, chidx, avail, chan->buflen, chan->xfrd, wrsize); - - stm32_gint_wrpacket(priv, chan->buffer, chidx, wrsize); -} - -/**************************************************************************** - * Name: stm32_gint_ptxfeisr - * - * Description: - * USB OTG FS periodic TxFIFO empty interrupt handler - * - ****************************************************************************/ - -static inline void stm32_gint_ptxfeisr(struct stm32_usbhost_s *priv) -{ - struct stm32_chan_s *chan; - uint32_t regval; - unsigned int wrsize; - unsigned int avail; - unsigned int chidx; - - /* Recover the index of the channel that is waiting for space in the Tx - * FIFO. - */ - - chidx = priv->chidx; - chan = &priv->chan[chidx]; - - /* Reduce the buffer size by the number of bytes that were previously - * placed in the Tx FIFO. - */ - - chan->buffer += chan->inflight; - chan->xfrd += chan->inflight; - chan->inflight = 0; - - /* If we have now transferred the entire buffer, then this transfer is - * complete (this case really should never happen because we disable - * the PTXFE interrupt on the final packet). - */ - - if (chan->xfrd >= chan->buflen) - { - /* Disable further Tx FIFO empty interrupts and bail. */ - - stm32_modifyreg(STM32_OTGFS_GINTMSK, OTGFS_GINT_PTXFE, 0); - return; - } - - /* Read the status from the top of the periodic TxFIFO */ - - regval = stm32_getreg(STM32_OTGFS_HPTXSTS); - - /* Extract the number of bytes available in the periodic Tx FIFO. */ - - avail = ((regval & OTGFS_HPTXSTS_PTXFSAVL_MASK) >> - OTGFS_HPTXSTS_PTXFSAVL_SHIFT) << 2; - - /* Get the size to put in the Tx FIFO now */ - - wrsize = chan->buflen - chan->xfrd; - - /* Get minimal size packet that can be sent. Something is seriously - * configured wrong if one packet will not fit into the empty Tx FIFO. - */ - - DEBUGASSERT(wrsize && avail >= MIN(wrsize, chan->maxpacket)); - if (wrsize > avail) - { - /* Clip the write size to the number of full, max sized packets - * that will fit in the Tx FIFO. - */ - - unsigned int wrpackets = avail / chan->maxpacket; - wrsize = wrpackets * chan->maxpacket; - } - - /* Otherwise, this will be the last packet to be sent in this transaction. - * We now need to disable further PTXFE interrupts. - */ - - else - { - stm32_modifyreg(STM32_OTGFS_GINTMSK, OTGFS_GINT_PTXFE, 0); - } - - /* Write the next group of packets into the Tx FIFO */ - - uinfo("HPTXSTS: %08" PRIx32 - " chidx: %d avail: %d buflen: %d xfrd: %d wrsize: %d\n", - regval, chidx, avail, chan->buflen, chan->xfrd, wrsize); - - stm32_gint_wrpacket(priv, chan->buffer, chidx, wrsize); -} - -/**************************************************************************** - * Name: stm32_gint_hcisr - * - * Description: - * USB OTG FS host channels interrupt handler - * - ****************************************************************************/ - -static inline void stm32_gint_hcisr(struct stm32_usbhost_s *priv) -{ - uint32_t haint; - uint32_t hcchar; - int i = 0; - - /* Read the Host all channels interrupt register and test each bit in the - * register. Each bit i, i=0...(STM32_NHOST_CHANNELS-1), corresponds to - * a pending interrupt on channel i. - */ - - haint = stm32_getreg(STM32_OTGFS_HAINT); - for (i = 0; i < STM32_NHOST_CHANNELS; i++) - { - /* Is an interrupt pending on this channel? */ - - if ((haint & OTGFS_HAINT(i)) != 0) - { - /* Yes... read the HCCHAR register to get the direction bit */ - - hcchar = stm32_getreg(STM32_OTGFS_HCCHAR(i)); - - /* Was this an interrupt on an IN or an OUT channel? */ - - if ((hcchar & OTGFS_HCCHAR_EPDIR) != 0) - { - /* Handle the HC IN channel interrupt */ - - stm32_gint_hcinisr(priv, i); - } - else - { - /* Handle the HC OUT channel interrupt */ - - stm32_gint_hcoutisr(priv, i); - } - } - } -} - -/**************************************************************************** - * Name: stm32_gint_hprtisr - * - * Description: - * USB OTG FS host port interrupt handler - * - ****************************************************************************/ - -static inline void stm32_gint_hprtisr(struct stm32_usbhost_s *priv) -{ - uint32_t hprt; - uint32_t newhprt; - uint32_t hcfg; - - usbhost_vtrace1(OTGFS_VTRACE1_GINT_HPRT, 0); - - /* Read the port status and control register (HPRT) */ - - hprt = stm32_getreg(STM32_OTGFS_HPRT); - - /* Setup to clear the interrupt bits in GINTSTS by setting the - * corresponding bits in the HPRT. The HCINT interrupt bit is cleared - * when the appropriate status bits in the HPRT register are cleared. - */ - - newhprt = hprt & ~(OTGFS_HPRT_PENA | OTGFS_HPRT_PCDET | - OTGFS_HPRT_PENCHNG | OTGFS_HPRT_POCCHNG); - - /* Check for Port Over-urrent CHaNGe (POCCHNG) */ - - if ((hprt & OTGFS_HPRT_POCCHNG) != 0) - { - /* Set up to clear the POCCHNG status in the new HPRT contents. */ - - usbhost_vtrace1(OTGFS_VTRACE1_GINT_HPRT_POCCHNG, 0); - newhprt |= OTGFS_HPRT_POCCHNG; - } - - /* Check for Port Connect DETected (PCDET). The core sets this bit when a - * device connection is detected. - */ - - if ((hprt & OTGFS_HPRT_PCDET) != 0) - { - /* Set up to clear the PCDET status in the new HPRT contents. Then - * process the new connection event. - */ - - usbhost_vtrace1(OTGFS_VTRACE1_GINT_HPRT_PCDET, 0); - newhprt |= OTGFS_HPRT_PCDET; - stm32_portreset(priv); - stm32_gint_connected(priv); - } - - /* Check for Port Enable CHaNGed (PENCHNG) */ - - if ((hprt & OTGFS_HPRT_PENCHNG) != 0) - { - /* Set up to clear the PENCHNG status in the new HPRT contents. */ - - usbhost_vtrace1(OTGFS_VTRACE1_GINT_HPRT_PENCHNG, 0); - newhprt |= OTGFS_HPRT_PENCHNG; - - /* Was the port enabled? */ - - if ((hprt & OTGFS_HPRT_PENA) != 0) - { - /* Yes.. handle the new connection event */ - - stm32_gint_connected(priv); - - /* Check the Host ConFiGuration register (HCFG) */ - - hcfg = stm32_getreg(STM32_OTGFS_HCFG); - - /* Is this a low speed or full speed connection (OTG FS does not - * support high speed) - */ - - if ((hprt & OTGFS_HPRT_PSPD_MASK) == OTGFS_HPRT_PSPD_LS) - { - /* Set the Host Frame Interval Register for the 6KHz speed */ - - usbhost_vtrace1(OTGFS_VTRACE1_GINT_HPRT_LSDEV, 0); - stm32_putreg(STM32_OTGFS_HFIR, 6000); - - /* Are we switching from FS to LS? */ - - if ((hcfg & OTGFS_HCFG_FSLSPCS_MASK) != - OTGFS_HCFG_FSLSPCS_LS6MHz) - { - usbhost_vtrace1(OTGFS_VTRACE1_GINT_HPRT_FSLSSW, 0); - - /* Yes... configure for LS */ - - hcfg &= ~OTGFS_HCFG_FSLSPCS_MASK; - hcfg |= OTGFS_HCFG_FSLSPCS_LS6MHz; - stm32_putreg(STM32_OTGFS_HCFG, hcfg); - - /* And reset the port */ - - stm32_portreset(priv); - } - } - else /* if ((hprt & OTGFS_HPRT_PSPD_MASK) == OTGFS_HPRT_PSPD_FS) */ - { - usbhost_vtrace1(OTGFS_VTRACE1_GINT_HPRT_FSDEV, 0); - stm32_putreg(STM32_OTGFS_HFIR, 48000); - - /* Are we switching from LS to FS? */ - - if ((hcfg & OTGFS_HCFG_FSLSPCS_MASK) != - OTGFS_HCFG_FSLSPCS_FS48MHz) - { - usbhost_vtrace1(OTGFS_VTRACE1_GINT_HPRT_LSFSSW, 0); - - /* Yes... configure for FS */ - - hcfg &= ~OTGFS_HCFG_FSLSPCS_MASK; - hcfg |= OTGFS_HCFG_FSLSPCS_FS48MHz; - stm32_putreg(STM32_OTGFS_HCFG, hcfg); - - /* And reset the port */ - - stm32_portreset(priv); - } - } - } - } - - /* Clear port interrupts by setting bits in the HPRT */ - - stm32_putreg(STM32_OTGFS_HPRT, newhprt); -} - -/**************************************************************************** - * Name: stm32_gint_discisr - * - * Description: - * USB OTG FS disconnect detected interrupt handler - * - ****************************************************************************/ - -static inline void stm32_gint_discisr(struct stm32_usbhost_s *priv) -{ - /* Handle the disconnection event */ - - stm32_gint_disconnected(priv); - - /* Clear the dicsonnect interrupt */ - - stm32_putreg(STM32_OTGFS_GINTSTS, OTGFS_GINT_DISC); -} - -/**************************************************************************** - * Name: stm32_gint_ipxfrisr - * - * Description: - * USB OTG FS incomplete periodic interrupt handler - * - ****************************************************************************/ - -static inline void stm32_gint_ipxfrisr(struct stm32_usbhost_s *priv) -{ - uint32_t regval; - - /* CHENA : Set to enable the channel - * CHDIS : Set to stop transmitting/receiving data on a channel - */ - - regval = stm32_getreg(STM32_OTGFS_HCCHAR(0)); - regval |= (OTGFS_HCCHAR_CHDIS | OTGFS_HCCHAR_CHENA); - stm32_putreg(STM32_OTGFS_HCCHAR(0), regval); - - /* Clear the incomplete isochronous OUT interrupt */ - - stm32_putreg(STM32_OTGFS_GINTSTS, OTGFS_GINT_IPXFR); -} - -/**************************************************************************** - * Name: stm32_gint_isr - * - * Description: - * USB OTG FS global interrupt handler - * - ****************************************************************************/ - -static int stm32_gint_isr(int irq, void *context, void *arg) -{ - /* At present, there is only support for a single OTG FS host. Hence it is - * pre-allocated as g_usbhost. However, in most code, the private data - * structure will be referenced using the 'priv' pointer (rather than the - * global data) in order to simplify any future support for multiple - * devices. - */ - - struct stm32_usbhost_s *priv = &g_usbhost; - uint32_t pending; - - /* If OTG were supported, we would need to check if we are in host or - * device mode when the global interrupt occurs. Here we support only - * host mode - */ - - /* Loop while there are pending interrupts to process. This loop may save - * a little interrupt handling overhead. - */ - - for (; ; ) - { - /* Get the unmasked bits in the GINT status */ - - pending = stm32_getreg(STM32_OTGFS_GINTSTS); - pending &= stm32_getreg(STM32_OTGFS_GINTMSK); - - /* Return from the interrupt when there are no further pending - * interrupts. - */ - - if (pending == 0) - { - return OK; - } - - /* Otherwise, process each pending, unmasked GINT interrupts */ - - /* Handle the start of frame interrupt */ - -#ifdef CONFIG_STM32_OTGFS_SOFINTR - if ((pending & OTGFS_GINT_SOF) != 0) - { - usbhost_vtrace1(OTGFS_VTRACE1_GINT_SOF, 0); - stm32_gint_sofisr(priv); - } -#endif - - /* Handle the RxFIFO non-empty interrupt */ - - if ((pending & OTGFS_GINT_RXFLVL) != 0) - { - usbhost_vtrace1(OTGFS_VTRACE1_GINT_RXFLVL, 0); - stm32_gint_rxflvlisr(priv); - } - - /* Handle the non-periodic TxFIFO empty interrupt */ - - if ((pending & OTGFS_GINT_NPTXFE) != 0) - { - usbhost_vtrace1(OTGFS_VTRACE1_GINT_NPTXFE, 0); - stm32_gint_nptxfeisr(priv); - } - - /* Handle the periodic TxFIFO empty interrupt */ - - if ((pending & OTGFS_GINT_PTXFE) != 0) - { - usbhost_vtrace1(OTGFS_VTRACE1_GINT_PTXFE, 0); - stm32_gint_ptxfeisr(priv); - } - - /* Handle the host channels interrupt */ - - if ((pending & OTGFS_GINT_HC) != 0) - { - usbhost_vtrace1(OTGFS_VTRACE1_GINT_HC, 0); - stm32_gint_hcisr(priv); - } - - /* Handle the host port interrupt */ - - if ((pending & OTGFS_GINT_HPRT) != 0) - { - stm32_gint_hprtisr(priv); - } - - /* Handle the disconnect detected interrupt */ - - if ((pending & OTGFS_GINT_DISC) != 0) - { - usbhost_vtrace1(OTGFS_VTRACE1_GINT_DISC, 0); - stm32_gint_discisr(priv); - } - - /* Handle the incomplete periodic transfer */ - - if ((pending & OTGFS_GINT_IPXFR) != 0) - { - usbhost_vtrace1(OTGFS_VTRACE1_GINT_IPXFR, 0); - stm32_gint_ipxfrisr(priv); - } - } - - /* We won't get here */ - - return OK; -} - -/**************************************************************************** - * Name: stm32_gint_enable and stm32_gint_disable - * - * Description: - * Respectively enable or disable the global OTG FS interrupt. - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void stm32_gint_enable(void) -{ - uint32_t regval; - - /* Set the GINTMSK bit to unmask the interrupt */ - - regval = stm32_getreg(STM32_OTGFS_GAHBCFG); - regval |= OTGFS_GAHBCFG_GINTMSK; - stm32_putreg(STM32_OTGFS_GAHBCFG, regval); -} - -static void stm32_gint_disable(void) -{ - uint32_t regval; - - /* Clear the GINTMSK bit to mask the interrupt */ - - regval = stm32_getreg(STM32_OTGFS_GAHBCFG); - regval &= ~OTGFS_GAHBCFG_GINTMSK; - stm32_putreg(STM32_OTGFS_GAHBCFG, regval); -} - -/**************************************************************************** - * Name: stm32_hostinit_enable - * - * Description: - * Enable host interrupts. - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -static inline void stm32_hostinit_enable(void) -{ - uint32_t regval; - - /* Disable all interrupts. */ - - stm32_putreg(STM32_OTGFS_GINTMSK, 0); - - /* Clear any pending interrupts. */ - - stm32_putreg(STM32_OTGFS_GINTSTS, 0xffffffff); - - /* Clear any pending USB OTG Interrupts */ - - stm32_putreg(STM32_OTGFS_GOTGINT, 0xffffffff); - - /* Clear any pending USB OTG interrupts */ - - stm32_putreg(STM32_OTGFS_GINTSTS, 0xbfffffff); - - /* Enable the host interrupts */ - - /* Common interrupts: - * - * OTGFS_GINT_WKUP : Resume/remote wakeup detected interrupt - * OTGFS_GINT_USBSUSP : USB suspend - */ - - regval = (OTGFS_GINT_WKUP | OTGFS_GINT_USBSUSP); - - /* If OTG were supported, we would need to enable the following as well: - * - * OTGFS_GINT_OTG : OTG interrupt - * OTGFS_GINT_SRQ : Session request/new session detected interrupt - * OTGFS_GINT_CIDSCHG : Connector ID status change - */ - - /* Host-specific interrupts - * - * OTGFS_GINT_SOF : Start of frame - * OTGFS_GINT_RXFLVL : RxFIFO non-empty - * OTGFS_GINT_IISOOXFR : Incomplete isochronous OUT transfer - * OTGFS_GINT_HPRT : Host port interrupt - * OTGFS_GINT_HC : Host channels interrupt - * OTGFS_GINT_DISC : Disconnect detected interrupt - */ - -#ifdef CONFIG_STM32_OTGFS_SOFINTR - regval |= (OTGFS_GINT_SOF | OTGFS_GINT_RXFLVL | OTGFS_GINT_IISOOXFR | - OTGFS_GINT_HPRT | OTGFS_GINT_HC | OTGFS_GINT_DISC); -#else - regval |= (OTGFS_GINT_RXFLVL | OTGFS_GINT_IPXFR | OTGFS_GINT_HPRT | - OTGFS_GINT_HC | OTGFS_GINT_DISC); -#endif - stm32_putreg(STM32_OTGFS_GINTMSK, regval); -} - -/**************************************************************************** - * Name: stm32_txfe_enable - * - * Description: - * Enable Tx FIFO empty interrupts. This is necessary when the entire - * transfer will not fit into Tx FIFO. The transfer will then be completed - * when the Tx FIFO is empty. NOTE: The Tx FIFO interrupt is disabled - * the fifo empty interrupt handler when the transfer is complete. - * - * Input Parameters: - * priv - Driver state structure reference - * chidx - The channel that requires the Tx FIFO empty interrupt - * - * Returned Value: - * None - * - * Assumptions: - * Called from user task context. Interrupts must be disabled to assure - * exclusive access to the GINTMSK register. - * - ****************************************************************************/ - -static void stm32_txfe_enable(struct stm32_usbhost_s *priv, int chidx) -{ - struct stm32_chan_s *chan = &priv->chan[chidx]; - irqstate_t flags; - uint32_t regval; - - /* Disable all interrupts so that we have exclusive access to the GINTMSK - * (it would be sufficient just to disable the GINT interrupt). - */ - - flags = enter_critical_section(); - - /* Should we enable the periodic or non-peridic Tx FIFO empty interrupts */ - - regval = stm32_getreg(STM32_OTGFS_GINTMSK); - switch (chan->eptype) - { - default: - case OTGFS_EPTYPE_CTRL: /* Non periodic transfer */ - case OTGFS_EPTYPE_BULK: - regval |= OTGFS_GINT_NPTXFE; - break; - - case OTGFS_EPTYPE_INTR: /* Periodic transfer */ - case OTGFS_EPTYPE_ISOC: - regval |= OTGFS_GINT_PTXFE; - break; - } - - /* Enable interrupts */ - - stm32_putreg(STM32_OTGFS_GINTMSK, regval); - leave_critical_section(flags); -} - -/**************************************************************************** - * USB Host Controller Operations - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_wait - * - * Description: - * Wait for a device to be connected or disconnected to/from a hub port. - * - * Input Parameters: - * conn - The USB host connection instance obtained as a parameter from - * the call to the USB driver initialization logic. - * hport - The location to return the hub port descriptor that detected - * the connection related event. - * - * Returned Value: - * Zero (OK) is returned on success when a device is connected or - * disconnected. This function will not return until either (1) a device is - * connected or disconnect to/from any hub port or until (2) some failure - * occurs. On a failure, a negated errno value is returned indicating the - * nature of the failure - * - * Assumptions: - * - Called from a single thread so no mutual exclusion is required. - * - Never called from an interrupt handler. - * - ****************************************************************************/ - -static int stm32_wait(struct usbhost_connection_s *conn, - struct usbhost_hubport_s **hport) -{ - struct stm32_usbhost_s *priv = &g_usbhost; - struct usbhost_hubport_s *connport; - irqstate_t flags; - int ret; - - /* Loop until a change in connection state is detected */ - - flags = enter_critical_section(); - for (; ; ) - { - /* Is there a change in the connection state of the single root hub - * port? - */ - - if (priv->change) - { - connport = &priv->rhport.hport; - - /* Yes. Remember the new state */ - - connport->connected = priv->connected; - priv->change = false; - - /* And return the root hub port */ - - *hport = connport; - leave_critical_section(flags); - - uinfo("RHport Connected: %s\n", - connport->connected ? "YES" : "NO"); - return OK; - } - -#ifdef CONFIG_USBHOST_HUB - /* Is a device connected to an external hub? */ - - if (priv->hport) - { - /* Yes.. return the external hub port */ - - connport = (struct usbhost_hubport_s *)priv->hport; - priv->hport = NULL; - - *hport = connport; - leave_critical_section(flags); - - uinfo("Hub port Connected: %s\n", - connport->connected ? "YES" : "NO"); - return OK; - } -#endif - - /* Wait for the next connection event */ - - priv->pscwait = true; - ret = nxsem_wait_uninterruptible(&priv->pscsem); - if (ret < 0) - { - return ret; - } - } -} - -/**************************************************************************** - * Name: stm32_enumerate - * - * Description: - * Enumerate the connected device. As part of this enumeration process, - * the driver will (1) get the device's configuration descriptor, (2) - * extract the class ID info from the configuration descriptor, (3) call - * usbhost_findclass() to find the class that supports this device, (4) - * call the create() method on the struct usbhost_registry_s interface - * to get a class instance, and finally (5) call the connect() method - * of the struct usbhost_class_s interface. After that, the class is in - * charge of the sequence of operations. - * - * Input Parameters: - * conn - The USB host connection instance obtained as a parameter from - * the call to the USB driver initialization logic. - * hport - The descriptor of the hub port that has the newly connected - * device. - * - * Returned Value: - * On success, zero (OK) is returned. On a failure, a negated errno value - * is returned indicating the nature of the failure - * - * Assumptions: - * This function will *not* be called from an interrupt handler. - * - ****************************************************************************/ - -static int stm32_rh_enumerate(struct stm32_usbhost_s *priv, - struct usbhost_connection_s *conn, - struct usbhost_hubport_s *hport) -{ - uint32_t regval; - int ret; - - DEBUGASSERT(conn != NULL && hport != NULL && hport->port == 0); - - /* Are we connected to a device? The caller should have called the wait() - * method first to be assured that a device is connected. - */ - - while (!priv->connected) - { - /* No, return an error */ - - usbhost_trace1(OTGFS_TRACE1_DEVDISCONN, 0); - return -ENODEV; - } - - DEBUGASSERT(priv->smstate == SMSTATE_ATTACHED); - - /* USB 2.0 spec says at least 50ms delay before port reset. We wait - * 100ms. - */ - - nxsched_usleep(100 * 1000); - - /* Reset the host port */ - - stm32_portreset(priv); - - /* Get the current device speed */ - - regval = stm32_getreg(STM32_OTGFS_HPRT); - if ((regval & OTGFS_HPRT_PSPD_MASK) == OTGFS_HPRT_PSPD_LS) - { - priv->rhport.hport.speed = USB_SPEED_LOW; - } - else - { - priv->rhport.hport.speed = USB_SPEED_FULL; - } - - /* Allocate and initialize the root hub port EP0 channels */ - - ret = stm32_ctrlchan_alloc(priv, 0, 0, priv->rhport.hport.speed, - &priv->ep0); - if (ret < 0) - { - uerr("ERROR: Failed to allocate a control endpoint: %d\n", ret); - } - - return ret; -} - -static int stm32_enumerate(struct usbhost_connection_s *conn, - struct usbhost_hubport_s *hport) -{ - struct stm32_usbhost_s *priv = &g_usbhost; - int ret; - - DEBUGASSERT(hport); - - /* If this is a connection on the root hub, then we need to go to - * little more effort to get the device speed. If it is a connection - * on an external hub, then we already have that information. - */ - -#ifdef CONFIG_USBHOST_HUB - if (ROOTHUB(hport)) -#endif - { - ret = stm32_rh_enumerate(priv, conn, hport); - if (ret < 0) - { - return ret; - } - } - - /* Then let the common usbhost_enumerate do the real enumeration. */ - - uinfo("Enumerate the device\n"); - priv->smstate = SMSTATE_ENUM; - ret = usbhost_enumerate(hport, &hport->devclass); - - /* The enumeration may fail either because of some HCD interfaces failure - * or because the device class is not supported. In either case, we just - * need to perform the disconnection operation and make ready for a new - * enumeration. - */ - - if (ret < 0) - { - /* Return to the disconnected state */ - - uerr("ERROR: Enumeration failed: %d\n", ret); - stm32_gint_disconnected(priv); - } - - return ret; -} - -/**************************************************************************** - * Name: stm32_ep0configure - * - * Description: - * Configure endpoint 0. This method is normally used internally by the - * enumerate() method but is made available at the interface to support an - * external implementation of the enumeration logic. - * - * Input Parameters: - * drvr - The USB host driver instance obtained as a parameter from the - * call to the class create() method. - * ep0 - The (opaque) EP0 endpoint instance - * funcaddr - The USB address of the function containing the endpoint that - * EP0 controls - * speed - The speed of the port USB_SPEED_LOW, _FULL, or _HIGH - * maxpacketsize - The maximum number of bytes that can be sent to or - * received from the endpoint in a single data packet - * - * Returned Value: - * On success, zero (OK) is returned. On a failure, a negated errno value - * is returned indicating the nature of the failure - * - * Assumptions: - * This function will *not* be called from an interrupt handler. - * - ****************************************************************************/ - -static int stm32_ep0configure(struct usbhost_driver_s *drvr, - usbhost_ep_t ep0, uint8_t funcaddr, - uint8_t speed, uint16_t maxpacketsize) -{ - struct stm32_usbhost_s *priv = (struct stm32_usbhost_s *)drvr; - struct stm32_ctrlinfo_s *ep0info = (struct stm32_ctrlinfo_s *)ep0; - struct stm32_chan_s *chan; - int ret; - - DEBUGASSERT(drvr != NULL && ep0info != NULL && funcaddr < 128 && - maxpacketsize <= 64); - - /* We must have exclusive access to the USB host hardware and structures */ - - ret = nxmutex_lock(&priv->lock); - if (ret < 0) - { - return ret; - } - - /* Configure the EP0 OUT channel */ - - chan = &priv->chan[ep0info->outndx]; - chan->funcaddr = funcaddr; - chan->speed = speed; - chan->maxpacket = maxpacketsize; - - stm32_chan_configure(priv, ep0info->outndx); - - /* Configure the EP0 IN channel */ - - chan = &priv->chan[ep0info->inndx]; - chan->funcaddr = funcaddr; - chan->speed = speed; - chan->maxpacket = maxpacketsize; - - stm32_chan_configure(priv, ep0info->inndx); - - nxmutex_unlock(&priv->lock); - return OK; -} - -/**************************************************************************** - * Name: stm32_epalloc - * - * Description: - * Allocate and configure one endpoint. - * - * Input Parameters: - * drvr - The USB host driver instance obtained as a parameter from the - * call to the class create() method. - * epdesc - Describes the endpoint to be allocated. - * ep - A memory location provided by the caller in which to receive the - * allocated endpoint descriptor. - * - * Returned Value: - * On success, zero (OK) is returned. On a failure, a negated errno value - * is returned indicating the nature of the failure - * - * Assumptions: - * This function will *not* be called from an interrupt handler. - * - ****************************************************************************/ - -static int stm32_epalloc(struct usbhost_driver_s *drvr, - const struct usbhost_epdesc_s *epdesc, - usbhost_ep_t *ep) -{ - struct stm32_usbhost_s *priv = (struct stm32_usbhost_s *)drvr; - int ret; - - /* Sanity check. NOTE that this method should only be called if a device - * is connected (because we need a valid low speed indication). - */ - - DEBUGASSERT(drvr != 0 && epdesc != NULL && ep != NULL); - - /* We must have exclusive access to the USB host hardware and structures */ - - ret = nxmutex_lock(&priv->lock); - if (ret < 0) - { - return ret; - } - - /* Handler control pipes differently from other endpoint types. This is - * because the normal, "transfer" endpoints are unidirectional an require - * only a single channel. Control endpoints, however, are bi-diretional - * and require two channels, one for the IN and one for the OUT direction. - */ - - if (epdesc->xfrtype == OTGFS_EPTYPE_CTRL) - { - ret = stm32_ctrlep_alloc(priv, epdesc, ep); - } - else - { - ret = stm32_xfrep_alloc(priv, epdesc, ep); - } - - nxmutex_unlock(&priv->lock); - return ret; -} - -/**************************************************************************** - * Name: stm32_epfree - * - * Description: - * Free and endpoint previously allocated by DRVR_EPALLOC. - * - * Input Parameters: - * drvr - The USB host driver instance obtained as a parameter from the - * call to the class create() method. - * ep - The endpoint to be freed. - * - * Returned Value: - * On success, zero (OK) is returned. On a failure, a negated errno value - * is returned indicating the nature of the failure - * - * Assumptions: - * This function will *not* be called from an interrupt handler. - * - ****************************************************************************/ - -static int stm32_epfree(struct usbhost_driver_s *drvr, usbhost_ep_t ep) -{ - struct stm32_usbhost_s *priv = (struct stm32_usbhost_s *)drvr; - int ret; - - DEBUGASSERT(priv); - - /* We must have exclusive access to the USB host hardware and structures */ - - ret = nxmutex_lock(&priv->lock); - - /* A single channel is represent by an index in the range of 0 to - * STM32_MAX_TX_FIFOS. Otherwise, the ep must be a pointer to an allocated - * control endpoint structure. - */ - - if ((uintptr_t)ep < STM32_MAX_TX_FIFOS) - { - /* Halt the channel and mark the channel available */ - - stm32_chan_free(priv, (int)ep); - } - else - { - /* Halt both control channel and mark the channels available */ - - struct stm32_ctrlinfo_s *ctrlep = - (struct stm32_ctrlinfo_s *)ep; - - stm32_chan_free(priv, ctrlep->inndx); - stm32_chan_free(priv, ctrlep->outndx); - - /* And free the control endpoint container */ - - kmm_free(ctrlep); - } - - nxmutex_unlock(&priv->lock); - return ret; -} - -/**************************************************************************** - * Name: stm32_alloc - * - * Description: - * Some hardware supports special memory in which request and descriptor - * data can be accessed more efficiently. This method provides a - * mechanism to allocate the request/descriptor memory. If the underlying - * hardware does not support such "special" memory, this functions may - * simply map to kmm_malloc. - * - * This interface was optimized under a particular assumption. It was - * assumed that the driver maintains a pool of small, pre-allocated - * buffers for descriptor traffic. NOTE that size is not an input, but - * an output: The size of the pre-allocated buffer is returned. - * - * Input Parameters: - * drvr - The USB host driver instance obtained as a parameter from the - * call to the class create() method. - * buffer - The address of a memory location provided by the caller in - * which to return the allocated buffer memory address. - * maxlen - The address of a memory location provided by the caller in - * which to return the maximum size of the allocated buffer memory. - * - * Returned Value: - * On success, zero (OK) is returned. On a failure, a negated errno value - * is returned indicating the nature of the failure - * - * Assumptions: - * - Called from a single thread so no mutual exclusion is required. - * - Never called from an interrupt handler. - * - ****************************************************************************/ - -static int stm32_alloc(struct usbhost_driver_s *drvr, - uint8_t **buffer, size_t *maxlen) -{ - uint8_t *alloc; - - DEBUGASSERT(drvr && buffer && maxlen); - - /* There is no special memory requirement for the STM32. */ - - alloc = kmm_malloc(CONFIG_STM32_OTGFS_DESCSIZE); - if (!alloc) - { - return -ENOMEM; - } - - /* Return the allocated address and size of the descriptor buffer */ - - *buffer = alloc; - *maxlen = CONFIG_STM32_OTGFS_DESCSIZE; - return OK; -} - -/**************************************************************************** - * Name: stm32_free - * - * Description: - * Some hardware supports special memory in which request and descriptor - * data can be accessed more efficiently. This method provides a - * mechanism to free that request/descriptor memory. If the underlying - * hardware does not support such "special" memory, this functions may - * simply map to kmm_free(). - * - * Input Parameters: - * drvr - The USB host driver instance obtained as a parameter from the - * call to the class create() method. - * buffer - The address of the allocated buffer memory to be freed. - * - * Returned Value: - * On success, zero (OK) is returned. On a failure, a negated errno value - * is returned indicating the nature of the failure - * - * Assumptions: - * - Never called from an interrupt handler. - * - ****************************************************************************/ - -static int stm32_free(struct usbhost_driver_s *drvr, uint8_t *buffer) -{ - /* There is no special memory requirement */ - - DEBUGASSERT(drvr && buffer); - kmm_free(buffer); - return OK; -} - -/**************************************************************************** - * Name: stm32_ioalloc - * - * Description: - * Some hardware supports special memory in which larger IO buffers can - * be accessed more efficiently. This method provides a mechanism to - * allocate the request/descriptor memory. If the underlying hardware - * does not support such "special" memory, this functions may simply map - * to kmm_malloc. - * - * This interface differs from DRVR_ALLOC in that the buffers are - * variable-sized. - * - * Input Parameters: - * drvr - The USB host driver instance obtained as a parameter from the - * call to the class create() method. - * buffer - The address of a memory location provided by the caller in - * which to return the allocated buffer memory address. - * buflen - The size of the buffer required. - * - * Returned Value: - * On success, zero (OK) is returned. On a failure, a negated errno value - * is returned indicating the nature of the failure - * - * Assumptions: - * This function will *not* be called from an interrupt handler. - * - ****************************************************************************/ - -static int stm32_ioalloc(struct usbhost_driver_s *drvr, - uint8_t **buffer, size_t buflen) -{ - uint8_t *alloc; - - DEBUGASSERT(drvr && buffer && buflen > 0); - - /* There is no special memory requirement */ - - alloc = kmm_malloc(buflen); - if (!alloc) - { - return -ENOMEM; - } - - /* Return the allocated buffer */ - - *buffer = alloc; - return OK; -} - -/**************************************************************************** - * Name: stm32_iofree - * - * Description: - * Some hardware supports special memory in which IO data can be accessed - * more efficiently. This method provides a mechanism to free that IO - * buffer memory. If the underlying hardware does not support such - * "special" memory, this functions may simply map to kmm_free(). - * - * Input Parameters: - * drvr - The USB host driver instance obtained as a parameter from the - * call to the class create() method. - * buffer - The address of the allocated buffer memory to be freed. - * - * Returned Value: - * On success, zero (OK) is returned. On a failure, a negated errno value - * is returned indicating the nature of the failure - * - * Assumptions: - * This function will *not* be called from an interrupt handler. - * - ****************************************************************************/ - -static int stm32_iofree(struct usbhost_driver_s *drvr, - uint8_t *buffer) -{ - /* There is no special memory requirement */ - - DEBUGASSERT(drvr && buffer); - kmm_free(buffer); - return OK; -} - -/**************************************************************************** - * Name: stm32_ctrlin and stm32_ctrlout - * - * Description: - * Process a IN or OUT request on the control endpoint. These methods - * will enqueue the request and wait for it to complete. Only one - * transfer may be queued; Neither these methods nor the transfer() - * method can be called again until the control transfer functions - * returns. - * - * These are blocking methods; these functions will not return until the - * control transfer has completed. - * - * Input Parameters: - * drvr - The USB host driver instance obtained as a parameter from the - * call to the class create() method. - * ep0 - The control endpoint to send/receive the control request. - * req - Describes the request to be sent. This request must lie in memory - * created by DRVR_ALLOC. - * buffer - A buffer used for sending the request and for returning any - * responses. This buffer must be large enough to hold the length value - * in the request description. buffer must have been allocated using - * DRVR_ALLOC. - * - * NOTE: On an IN transaction, req and buffer may refer to the same - * allocated memory. - * - * Returned Value: - * On success, zero (OK) is returned. On a failure, a negated errno value - * is returned indicating the nature of the failure - * - * Assumptions: - * - Called from a single thread so no mutual exclusion is required. - * - Never called from an interrupt handler. - * - ****************************************************************************/ - -static int stm32_ctrlin(struct usbhost_driver_s *drvr, usbhost_ep_t ep0, - const struct usb_ctrlreq_s *req, - uint8_t *buffer) -{ - struct stm32_usbhost_s *priv = (struct stm32_usbhost_s *)drvr; - struct stm32_ctrlinfo_s *ep0info = (struct stm32_ctrlinfo_s *)ep0; - uint16_t buflen; - clock_t start; - clock_t elapsed; - int retries; - int ret; - - DEBUGASSERT(priv != NULL && ep0info != NULL && req != NULL); - usbhost_vtrace2(OTGFS_VTRACE2_CTRLIN, req->type, req->req); - uinfo("type:%02x req:%02x value:%02x%02x index:%02x%02x len:%02x%02x\n", - req->type, req->req, req->value[1], req->value[0], - req->index[1], req->index[0], req->len[1], req->len[0]); - - /* Extract values from the request */ - - buflen = stm32_getle16(req->len); - - /* We must have exclusive access to the USB host hardware and structures */ - - ret = nxmutex_lock(&priv->lock); - if (ret < 0) - { - return ret; - } - - /* Loop, retrying until the retry time expires */ - - for (retries = 0; retries < STM32_RETRY_COUNT; retries++) - { - /* Send the SETUP request */ - - ret = stm32_ctrl_sendsetup(priv, ep0info, req); - if (ret < 0) - { - usbhost_trace1(OTGFS_TRACE1_SENDSETUP, -ret); - continue; - } - - /* Handle the IN data phase (if any) */ - - if (buflen > 0) - { - ret = stm32_ctrl_recvdata(priv, ep0info, buffer, buflen); - if (ret < 0) - { - usbhost_trace1(OTGFS_TRACE1_RECVDATA, -ret); - continue; - } - } - - /* Get the start time. Loop again until the timeout expires */ - - start = clock_systime_ticks(); - do - { - /* Handle the status OUT phase */ - - priv->chan[ep0info->outndx].outdata1 ^= true; - ret = stm32_ctrl_senddata(priv, ep0info, NULL, 0); - if (ret == OK) - { - /* All success transactions exit here */ - - nxmutex_unlock(&priv->lock); - return OK; - } - - usbhost_trace1(OTGFS_TRACE1_SENDDATA, ret < 0 ? -ret : ret); - - /* Get the elapsed time (in frames) */ - - elapsed = clock_systime_ticks() - start; - } - while (elapsed < STM32_DATANAK_DELAY); - } - - /* All failures exit here after all retries and timeouts are exhausted */ - - nxmutex_unlock(&priv->lock); - return -ETIMEDOUT; -} - -static int stm32_ctrlout(struct usbhost_driver_s *drvr, usbhost_ep_t ep0, - const struct usb_ctrlreq_s *req, - const uint8_t *buffer) -{ - struct stm32_usbhost_s *priv = (struct stm32_usbhost_s *)drvr; - struct stm32_ctrlinfo_s *ep0info = (struct stm32_ctrlinfo_s *)ep0; - uint16_t buflen; - clock_t start; - clock_t elapsed; - int retries; - int ret; - - DEBUGASSERT(priv != NULL && ep0info != NULL && req != NULL); - usbhost_vtrace2(OTGFS_VTRACE2_CTRLOUT, req->type, req->req); - uinfo("type:%02x req:%02x value:%02x%02x index:%02x%02x len:%02x%02x\n", - req->type, req->req, req->value[1], req->value[0], - req->index[1], req->index[0], req->len[1], req->len[0]); - - /* Extract values from the request */ - - buflen = stm32_getle16(req->len); - - /* We must have exclusive access to the USB host hardware and structures */ - - ret = nxmutex_lock(&priv->lock); - if (ret < 0) - { - return ret; - } - - /* Loop, retrying until the retry time expires */ - - for (retries = 0; retries < STM32_RETRY_COUNT; retries++) - { - /* Send the SETUP request */ - - ret = stm32_ctrl_sendsetup(priv, ep0info, req); - if (ret < 0) - { - usbhost_trace1(OTGFS_TRACE1_SENDSETUP, -ret); - continue; - } - - /* Get the start time. Loop again until the timeout expires */ - - start = clock_systime_ticks(); - do - { - /* Handle the data OUT phase (if any) */ - - if (buflen > 0) - { - /* Start DATA out transfer (only one DATA packet) */ - - priv->chan[ep0info->outndx].outdata1 = true; - ret = stm32_ctrl_senddata(priv, ep0info, (uint8_t *)buffer, - buflen); - if (ret < 0) - { - usbhost_trace1(OTGFS_TRACE1_SENDDATA, -ret); - } - } - - /* Handle the status IN phase */ - - if (ret == OK) - { - ret = stm32_ctrl_recvdata(priv, ep0info, NULL, 0); - if (ret == OK) - { - /* All success transactins exit here */ - - nxmutex_unlock(&priv->lock); - return OK; - } - - usbhost_trace1(OTGFS_TRACE1_RECVDATA, ret < 0 ? -ret : ret); - } - - /* Get the elapsed time (in frames) */ - - elapsed = clock_systime_ticks() - start; - } - while (elapsed < STM32_DATANAK_DELAY); - } - - /* All failures exit here after all retries and timeouts are exhausted */ - - nxmutex_unlock(&priv->lock); - return -ETIMEDOUT; -} - -/**************************************************************************** - * Name: stm32_transfer - * - * Description: - * Process a request to handle a transfer descriptor. This method will - * enqueue the transfer request, blocking until the transfer completes. - * Only one transfer may be queued; Neither this method nor the ctrlin or - * ctrlout methods can be called again until this function returns. - * - * This is a blocking method; this functions will not return until the - * transfer has completed. - * - * Input Parameters: - * drvr - The USB host driver instance obtained as a parameter from the - * call to the class create() method. - * ep - The IN or OUT endpoint descriptor for the device endpoint on - * which to perform the transfer. - * buffer - A buffer containing the data to be sent (OUT endpoint) or - * received (IN endpoint). buffer must have been allocated using - * DRVR_ALLOC - * buflen - The length of the data to be sent or received. - * - * Returned Value: - * On success, a non-negative value is returned that indicates the number - * of bytes successfully transferred. On a failure, a negated errno value - * is returned that indicates the nature of the failure: - * - * EAGAIN - If devices NAKs the transfer (or NYET or other error where - * it may be appropriate to restart the entire transaction). - * EPERM - If the endpoint stalls - * EIO - On a TX or data toggle error - * EPIPE - Overrun errors - * - * Assumptions: - * - Called from a single thread so no mutual exclusion is required. - * - Never called from an interrupt handler. - * - ****************************************************************************/ - -static ssize_t stm32_transfer(struct usbhost_driver_s *drvr, - usbhost_ep_t ep, - uint8_t *buffer, size_t buflen) -{ - struct stm32_usbhost_s *priv = (struct stm32_usbhost_s *)drvr; - unsigned int chidx = (unsigned int)ep; - ssize_t nbytes; - int ret; - - uinfo("chidx: %d buflen: %d\n", (unsigned int)ep, buflen); - - DEBUGASSERT(priv && buffer && chidx < STM32_MAX_TX_FIFOS && buflen > 0); - - /* We must have exclusive access to the USB host hardware and structures */ - - ret = nxmutex_lock(&priv->lock); - if (ret < 0) - { - return (ssize_t)ret; - } - - /* Handle IN and OUT transfer slightly differently */ - - if (priv->chan[chidx].in) - { - nbytes = stm32_in_transfer(priv, chidx, buffer, buflen); - } - else - { - nbytes = stm32_out_transfer(priv, chidx, buffer, buflen); - } - - nxmutex_unlock(&priv->lock); - return nbytes; -} - -/**************************************************************************** - * Name: stm32_asynch - * - * Description: - * Process a request to handle a transfer descriptor. This method will - * enqueue the transfer request and return immediately. When the transfer - * completes, the callback will be invoked with the provided transfer. - * This method is useful for receiving interrupt transfers which may come - * infrequently. - * - * Only one transfer may be queued; Neither this method nor the ctrlin or - * ctrlout methods can be called again until the transfer completes. - * - * Input Parameters: - * drvr - The USB host driver instance obtained as a parameter from the - * call to the class create() method. - * ep - The IN or OUT endpoint descriptor for the device endpoint on - * which to perform the transfer. - * buffer - A buffer containing the data to be sent (OUT endpoint) or - * received (IN endpoint). buffer must have been allocated using - * DRVR_ALLOC - * buflen - The length of the data to be sent or received. - * callback - This function will be called when the transfer completes. - * arg - The arbitrary parameter that will be passed to the callback - * function when the transfer completes. - * - * Returned Value: - * On success, zero (OK) is returned. On a failure, a negated errno value - * is returned indicating the nature of the failure - * - * Assumptions: - * - Called from a single thread so no mutual exclusion is required. - * - Never called from an interrupt handler. - * - ****************************************************************************/ - -#ifdef CONFIG_USBHOST_ASYNCH -static int stm32_asynch(struct usbhost_driver_s *drvr, usbhost_ep_t ep, - uint8_t *buffer, size_t buflen, - usbhost_asynch_t callback, void *arg) -{ - struct stm32_usbhost_s *priv = (struct stm32_usbhost_s *)drvr; - unsigned int chidx = (unsigned int)ep; - int ret; - - uinfo("chidx: %d buflen: %d\n", (unsigned int)ep, buflen); - - DEBUGASSERT(priv && buffer && chidx < STM32_MAX_TX_FIFOS && buflen > 0); - - /* We must have exclusive access to the USB host hardware and structures */ - - ret = nxmutex_lock(&priv->lock); - if (ret < 0) - { - return ret; - } - - /* Handle IN and OUT transfer slightly differently */ - - if (priv->chan[chidx].in) - { - ret = stm32_in_asynch(priv, chidx, buffer, buflen, callback, arg); - } - else - { - ret = stm32_out_asynch(priv, chidx, buffer, buflen, callback, arg); - } - - nxmutex_unlock(&priv->lock); - return ret; -} -#endif /* CONFIG_USBHOST_ASYNCH */ - -/**************************************************************************** - * Name: stm32_cancel - * - * Description: - * Cancel a pending transfer on an endpoint. Cancelled synchronous or - * asynchronous transfer will complete normally with the error -ESHUTDOWN. - * - * Input Parameters: - * drvr - The USB host driver instance obtained as a parameter from the - * call to the class create() method. - * ep - The IN or OUT endpoint descriptor for the device endpoint on - * which an asynchronous transfer should be transferred. - * - * Returned Value: - * On success, zero (OK) is returned. On a failure, a negated errno value - * is returned indicating the nature of the failure - * - ****************************************************************************/ - -static int stm32_cancel(struct usbhost_driver_s *drvr, usbhost_ep_t ep) -{ - struct stm32_usbhost_s *priv = (struct stm32_usbhost_s *)drvr; - struct stm32_chan_s *chan; - unsigned int chidx = (unsigned int)ep; - irqstate_t flags; - - uinfo("chidx: %u\n", chidx); - - DEBUGASSERT(priv && chidx < STM32_MAX_TX_FIFOS); - chan = &priv->chan[chidx]; - - /* We need to disable interrupts to avoid race conditions with the - * asynchronous completion of the transfer being cancelled. - */ - - flags = enter_critical_section(); - - /* Halt the channel */ - - stm32_chan_halt(priv, chidx, CHREASON_CANCELLED); - chan->result = -ESHUTDOWN; - - /* Is there a thread waiting for this transfer to complete? */ - - if (chan->waiter) - { -#ifdef CONFIG_USBHOST_ASYNCH - /* Yes.. there should not also be a callback scheduled */ - - DEBUGASSERT(chan->callback == NULL); -#endif - - /* Wake'em up! */ - - nxsem_post(&chan->waitsem); - chan->waiter = false; - } - -#ifdef CONFIG_USBHOST_ASYNCH - /* No.. is an asynchronous callback expected when the transfer - * completes? - */ - - else if (chan->callback) - { - usbhost_asynch_t callback; - void *arg; - - /* Extract the callback information */ - - callback = chan->callback; - arg = chan->arg; - - chan->callback = NULL; - chan->arg = NULL; - chan->xfrd = 0; - - /* Then perform the callback */ - - callback(arg, -ESHUTDOWN); - } -#endif - - leave_critical_section(flags); - return OK; -} - -/**************************************************************************** - * Name: stm32_connect - * - * Description: - * New connections may be detected by an attached hub. This method is the - * mechanism that is used by the hub class to introduce a new connection - * and port description to the system. - * - * Input Parameters: - * drvr - The USB host driver instance obtained as a parameter from the - * call to the class create() method. - * hport - The descriptor of the hub port that detected the connection - * related event - * connected - True: device connected; false: device disconnected - * - * Returned Value: - * On success, zero (OK) is returned. On a failure, a negated errno value - * is returned indicating the nature of the failure - * - ****************************************************************************/ - -#ifdef CONFIG_USBHOST_HUB -static int stm32_connect(struct usbhost_driver_s *drvr, - struct usbhost_hubport_s *hport, - bool connected) -{ - struct stm32_usbhost_s *priv = (struct stm32_usbhost_s *)drvr; - irqstate_t flags; - - DEBUGASSERT(priv != NULL && hport != NULL); - - /* Set the connected/disconnected flag */ - - hport->connected = connected; - uinfo("Hub port %d connected: %s\n", - hport->port, connected ? "YES" : "NO"); - - /* Report the connection event */ - - flags = enter_critical_section(); - priv->hport = hport; - if (priv->pscwait) - { - priv->pscwait = false; - nxsem_post(&priv->pscsem); - } - - leave_critical_section(flags); - return OK; -} -#endif - -/**************************************************************************** - * Name: stm32_disconnect - * - * Description: - * Called by the class when an error occurs and driver has been - * disconnected. The USB host driver should discard the handle to the - * class instance (it is stale) and not attempt any further interaction - * with the class driver instance (until a new instance is received from - * the create() method). The driver should not call the class' - * disconnected() method. - * - * Input Parameters: - * drvr - The USB host driver instance obtained as a parameter from the - * call to the class create() method. - * hport - The port from which the device is being disconnected. Might be - * a port on a hub. - * - * Returned Value: - * None - * - * Assumptions: - * - Only a single class bound to a single device is supported. - * - Never called from an interrupt handler. - * - ****************************************************************************/ - -static void stm32_disconnect(struct usbhost_driver_s *drvr, - struct usbhost_hubport_s *hport) -{ - DEBUGASSERT(hport != NULL); - hport->devclass = NULL; -} - -/**************************************************************************** - * Name: stm32_portreset - * - * Description: - * Reset the USB host port. - * - * NOTE: "Before starting to drive a USB reset, the application waits for - * the OTG interrupt triggered by the debounce done bit (DBCDNE bit in - * OTG_FS_GOTGINT), which indicates that the bus is stable again after - * the electrical debounce caused by the attachment of a pull-up resistor - * on DP (FS) or DM (LS). - * - * Input Parameters: - * priv -- USB host driver private data structure. - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void stm32_portreset(struct stm32_usbhost_s *priv) -{ - uint32_t regval; - - regval = stm32_getreg(STM32_OTGFS_HPRT); - regval &= ~(OTGFS_HPRT_PENA | OTGFS_HPRT_PCDET | OTGFS_HPRT_PENCHNG | - OTGFS_HPRT_POCCHNG); - regval |= OTGFS_HPRT_PRST; - stm32_putreg(STM32_OTGFS_HPRT, regval); - - up_mdelay(20); - - regval &= ~OTGFS_HPRT_PRST; - stm32_putreg(STM32_OTGFS_HPRT, regval); - - up_mdelay(20); -} - -/**************************************************************************** - * Name: stm32_flush_txfifos - * - * Description: - * Flush the selected Tx FIFO. - * - * Input Parameters: - * txfnum -- USB host driver private data structure. - * - * Returned Value: - * None. - * - ****************************************************************************/ - -static void stm32_flush_txfifos(uint32_t txfnum) -{ - uint32_t regval; - uint32_t timeout; - - /* Initiate the TX FIFO flush operation */ - - regval = OTGFS_GRSTCTL_TXFFLSH | txfnum; - stm32_putreg(STM32_OTGFS_GRSTCTL, regval); - - /* Wait for the FLUSH to complete */ - - for (timeout = 0; timeout < STM32_FLUSH_DELAY; timeout++) - { - regval = stm32_getreg(STM32_OTGFS_GRSTCTL); - if ((regval & OTGFS_GRSTCTL_TXFFLSH) == 0) - { - break; - } - } - - /* Wait for 3 PHY Clocks */ - - up_udelay(3); -} - -/**************************************************************************** - * Name: stm32_flush_rxfifo - * - * Description: - * Flush the Rx FIFO. - * - * Input Parameters: - * priv -- USB host driver private data structure. - * - * Returned Value: - * None. - * - ****************************************************************************/ - -static void stm32_flush_rxfifo(void) -{ - uint32_t regval; - uint32_t timeout; - - /* Initiate the RX FIFO flush operation */ - - stm32_putreg(STM32_OTGFS_GRSTCTL, OTGFS_GRSTCTL_RXFFLSH); - - /* Wait for the FLUSH to complete */ - - for (timeout = 0; timeout < STM32_FLUSH_DELAY; timeout++) - { - regval = stm32_getreg(STM32_OTGFS_GRSTCTL); - if ((regval & OTGFS_GRSTCTL_RXFFLSH) == 0) - { - break; - } - } - - /* Wait for 3 PHY Clocks */ - - up_udelay(3); -} - -/**************************************************************************** - * Name: stm32_vbusdrive - * - * Description: - * Drive the Vbus +5V. - * - * Input Parameters: - * priv - USB host driver private data structure. - * state - True: Drive, False: Don't drive - * - * Returned Value: - * None. - * - ****************************************************************************/ - -static void stm32_vbusdrive(struct stm32_usbhost_s *priv, bool state) -{ - uint32_t regval; - -#ifdef CONFIG_STM32_OTGFS_VBUS_CONTROL - /* Enable/disable the external charge pump */ - - stm32_usbhost_vbusdrive(0, state); -#endif - - /* Turn on the Host port power. */ - - regval = stm32_getreg(STM32_OTGFS_HPRT); - regval &= ~(OTGFS_HPRT_PENA | OTGFS_HPRT_PCDET | OTGFS_HPRT_PENCHNG | - OTGFS_HPRT_POCCHNG); - - if (((regval & OTGFS_HPRT_PPWR) == 0) && state) - { - regval |= OTGFS_HPRT_PPWR; - stm32_putreg(STM32_OTGFS_HPRT, regval); - } - - if (((regval & OTGFS_HPRT_PPWR) != 0) && !state) - { - regval &= ~OTGFS_HPRT_PPWR; - stm32_putreg(STM32_OTGFS_HPRT, regval); - } - - up_mdelay(200); -} - -/**************************************************************************** - * Name: stm32_host_initialize - * - * Description: - * Initialize/re-initialize hardware for host mode operation. At present, - * this function is called only from stm32_hw_initialize(). But if OTG - * mode were supported, this function would also be called to switch - * between host and device modes on a connector ID change interrupt. - * - * Input Parameters: - * priv -- USB host driver private data structure. - * - * Returned Value: - * None. - * - ****************************************************************************/ - -static void stm32_host_initialize(struct stm32_usbhost_s *priv) -{ - uint32_t regval; - uint32_t offset; - int i; - - /* Restart the PHY Clock */ - - stm32_putreg(STM32_OTGFS_PCGCCTL, 0); - - /* Initialize Host Configuration (HCFG) register */ - - regval = stm32_getreg(STM32_OTGFS_HCFG); - regval &= ~OTGFS_HCFG_FSLSPCS_MASK; - regval |= OTGFS_HCFG_FSLSPCS_FS48MHz; - stm32_putreg(STM32_OTGFS_HCFG, regval); - - /* Reset the host port */ - - stm32_portreset(priv); - - /* Clear the FS-/LS-only support bit in the HCFG register */ - - regval = stm32_getreg(STM32_OTGFS_HCFG); - regval &= ~OTGFS_HCFG_FSLSS; - stm32_putreg(STM32_OTGFS_HCFG, regval); - - /* Carve up FIFO memory for the Rx FIFO and the periodic - * and non-periodic Tx FIFOs - */ - - /* Configure Rx FIFO size (GRXFSIZ) */ - - stm32_putreg(STM32_OTGFS_GRXFSIZ, CONFIG_STM32_OTGFS_RXFIFO_SIZE); - offset = CONFIG_STM32_OTGFS_RXFIFO_SIZE; - - /* Setup the host non-periodic Tx FIFO size (HNPTXFSIZ) */ - - regval = (offset | - (CONFIG_STM32_OTGFS_NPTXFIFO_SIZE << - OTGFS_HNPTXFSIZ_NPTXFD_SHIFT)); - stm32_putreg(STM32_OTGFS_HNPTXFSIZ, regval); - offset += CONFIG_STM32_OTGFS_NPTXFIFO_SIZE; - - /* Set up the host periodic Tx fifo size register (HPTXFSIZ) */ - - regval = (offset | - (CONFIG_STM32_OTGFS_PTXFIFO_SIZE << - OTGFS_HPTXFSIZ_PTXFD_SHIFT)); - stm32_putreg(STM32_OTGFS_HPTXFSIZ, regval); - - /* If OTG were supported, we should need to clear HNP enable bit in the - * USB_OTG control register about here. - */ - - /* Flush all FIFOs */ - - stm32_flush_txfifos(OTGFS_GRSTCTL_TXFNUM_HALL); - stm32_flush_rxfifo(); - - /* Clear all pending HC Interrupts */ - - for (i = 0; i < STM32_NHOST_CHANNELS; i++) - { - stm32_putreg(STM32_OTGFS_HCINT(i), 0xffffffff); - stm32_putreg(STM32_OTGFS_HCINTMSK(i), 0); - } - - /* Drive Vbus +5V (the smoke test). Should be done elsewhere in OTG - * mode. - */ - - stm32_vbusdrive(priv, true); - - /* Enable host interrupts */ - - stm32_hostinit_enable(); -} - -/**************************************************************************** - * Name: stm32_sw_initialize - * - * Description: - * One-time setup of the host driver state structure. - * - * Input Parameters: - * priv -- USB host driver private data structure. - * - * Returned Value: - * None. - * - ****************************************************************************/ - -static inline void stm32_sw_initialize(struct stm32_usbhost_s *priv) -{ - struct usbhost_driver_s *drvr; - struct usbhost_hubport_s *hport; - int i; - - /* Initialize the device operations */ - - drvr = &priv->drvr; - drvr->ep0configure = stm32_ep0configure; - drvr->epalloc = stm32_epalloc; - drvr->epfree = stm32_epfree; - drvr->alloc = stm32_alloc; - drvr->free = stm32_free; - drvr->ioalloc = stm32_ioalloc; - drvr->iofree = stm32_iofree; - drvr->ctrlin = stm32_ctrlin; - drvr->ctrlout = stm32_ctrlout; - drvr->transfer = stm32_transfer; -#ifdef CONFIG_USBHOST_ASYNCH - drvr->asynch = stm32_asynch; -#endif - drvr->cancel = stm32_cancel; -#ifdef CONFIG_USBHOST_HUB - drvr->connect = stm32_connect; -#endif - drvr->disconnect = stm32_disconnect; - - /* Initialize the public port representation */ - - hport = &priv->rhport.hport; - hport->drvr = drvr; -#ifdef CONFIG_USBHOST_HUB - hport->parent = NULL; -#endif - hport->ep0 = (usbhost_ep_t)&priv->ep0; - hport->speed = USB_SPEED_FULL; - - /* Initialize function address generation logic */ - - usbhost_devaddr_initialize(&priv->devgen); - priv->rhport.pdevgen = &priv->devgen; - - /* Initialize the driver state data */ - - priv->smstate = SMSTATE_DETACHED; - priv->connected = false; - priv->change = false; - - /* Put all of the channels back in their initial, allocated state */ - - memset(priv->chan, 0, STM32_MAX_TX_FIFOS * sizeof(struct stm32_chan_s)); - - /* Initialize each channel */ - - for (i = 0; i < STM32_MAX_TX_FIFOS; i++) - { - struct stm32_chan_s *chan = &priv->chan[i]; - - chan->chidx = i; - nxsem_init(&chan->waitsem, 0, 0); - } -} - -/**************************************************************************** - * Name: stm32_hw_initialize - * - * Description: - * One-time setup of the host controller hardware for normal operations. - * - * Input Parameters: - * priv -- USB host driver private data structure. - * - * Returned Value: - * Zero on success; a negated errno value on failure. - * - ****************************************************************************/ - -static inline int stm32_hw_initialize(struct stm32_usbhost_s *priv) -{ - uint32_t regval; - unsigned long timeout; - - /* Set the PHYSEL bit in the GUSBCFG register to select the OTG FS serial - * transceiver: "This bit is always 1 with write-only access" - */ - - regval = stm32_getreg(STM32_OTGFS_GUSBCFG); - regval |= OTGFS_GUSBCFG_PHYSEL; - stm32_putreg(STM32_OTGFS_GUSBCFG, regval); - - /* Reset after a PHY select and set Host mode. First, wait for AHB master - * IDLE state. - */ - - for (timeout = 0; timeout < STM32_READY_DELAY; timeout++) - { - up_udelay(3); - regval = stm32_getreg(STM32_OTGFS_GRSTCTL); - if ((regval & OTGFS_GRSTCTL_AHBIDL) != 0) - { - break; - } - } - - /* Then perform the core soft reset. */ - - stm32_putreg(STM32_OTGFS_GRSTCTL, OTGFS_GRSTCTL_CSRST); - for (timeout = 0; timeout < STM32_READY_DELAY; timeout++) - { - regval = stm32_getreg(STM32_OTGFS_GRSTCTL); - if ((regval & OTGFS_GRSTCTL_CSRST) == 0) - { - break; - } - } - - /* Wait for 3 PHY Clocks */ - - up_udelay(3); - - /* Deactivate the power down */ - - regval = OTGFS_GCCFG_PWRDWN | OTGFS_GCCFG_VBUSASEN | - OTGFS_GCCFG_VBUSBSEN; -#if !defined(CONFIG_USBDEV_VBUSSENSING) && !defined(CONFIG_STM32_OTGFS_VBUS_CONTROL) - regval |= OTGFS_GCCFG_NOVBUSSENS; -#endif -#ifdef CONFIG_STM32_OTGFS_SOFOUTPUT - regval |= OTGFS_GCCFG_SOFOUTEN; -#endif - stm32_putreg(STM32_OTGFS_GCCFG, regval); - up_mdelay(20); - - /* Initialize OTG features: In order to support OTP, the HNPCAP and SRPCAP - * bits would need to be set in the GUSBCFG register about here. - */ - - /* Force Host Mode */ - - regval = stm32_getreg(STM32_OTGFS_GUSBCFG); - regval &= ~OTGFS_GUSBCFG_FDMOD; - regval |= OTGFS_GUSBCFG_FHMOD; - stm32_putreg(STM32_OTGFS_GUSBCFG, regval); - up_mdelay(50); - - /* Initialize host mode and return success */ - - stm32_host_initialize(priv); - return OK; -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_otgfshost_initialize - * - * Description: - * Initialize USB host device controller hardware. - * - * Input Parameters: - * controller -- If the device supports more than USB host controller, then - * this identifies which controller is being initialized. Normally, this - * is just zero. - * - * Returned Value: - * And instance of the USB host interface. The controlling task should - * use this interface to (1) call the wait() method to wait for a device - * to be connected, and (2) call the enumerate() method to bind the device - * to a class driver. - * - * Assumptions: - * - This function should called in the initialization sequence in order - * to initialize the USB device functionality. - * - Class drivers should be initialized prior to calling this function. - * Otherwise, there is a race condition if the device is already connected. - * - ****************************************************************************/ - -struct usbhost_connection_s *stm32_otgfshost_initialize(int controller) -{ - /* At present, there is only support for a single OTG FS host. Hence it is - * pre-allocated as g_usbhost. However, in most code, the private data - * structure will be referenced using the 'priv' pointer (rather than the - * global data) in order to simplify any future support for multiple - * devices. - */ - - struct stm32_usbhost_s *priv = &g_usbhost; - - /* Sanity checks */ - - DEBUGASSERT(controller == 0); - - /* Make sure that interrupts from the OTG FS core are disabled */ - - stm32_gint_disable(); - - /* Reset the state of the host driver */ - - stm32_sw_initialize(priv); - - /* Alternate function pin configuration. Here we assume that: - * - * 1. GPIOA, SYSCFG, and OTG FS peripheral clocking have already been\ - * enabled as part of the boot sequence. - * 2. Board-specific logic has already enabled other board specific GPIOs - * for things like soft pull-up, VBUS sensing, power controls, and over- - * current detection. - */ - - /* Configure OTG FS alternate function pins for DM, DP, ID, and SOF. - * - * PIN* SIGNAL DIRECTION - * ---- ----------- ---------- - * PA8 OTG_FS_SOF SOF clock output - * PA9 OTG_FS_VBUS VBUS input for device, Driven by external regulator by - * host (not an alternate function) - * PA10 OTG_FS_ID OTG ID pin (only needed in Dual mode) - * PA11 OTG_FS_DM D- I/O - * PA12 OTG_FS_DP D+ I/O - * - * *Pins may vary from device-to-device. - */ - - stm32_configgpio(GPIO_OTGFS_DM); - stm32_configgpio(GPIO_OTGFS_DP); -#ifdef CONFIG_USBDEV - stm32_configgpio(GPIO_OTGFS_ID); /* Only needed for OTG */ -#endif - - /* SOF output pin configuration is configurable */ - -#ifdef CONFIG_STM32_OTGFS_SOFOUTPUT - stm32_configgpio(GPIO_OTGFS_SOF); -#endif - - /* Initialize the USB OTG FS core */ - - stm32_hw_initialize(priv); - - /* Attach USB host controller interrupt handler */ - - if (irq_attach(STM32_IRQ_OTGFS, stm32_gint_isr, NULL) != 0) - { - usbhost_trace1(OTGFS_TRACE1_IRQATTACH, 0); - return NULL; - } - - /* Enable USB OTG FS global interrupts */ - - stm32_gint_enable(); - - /* Enable interrupts at the interrupt controller */ - - up_enable_irq(STM32_IRQ_OTGFS); - return &g_usbconn; -} - -#endif /* CONFIG_STM32_USBHOST && CONFIG_STM32_OTGFS */ diff --git a/arch/arm/src/stm32/stm32_otghs.h b/arch/arm/src/stm32/stm32_otghs.h deleted file mode 100644 index 68016e3793fd8..0000000000000 --- a/arch/arm/src/stm32/stm32_otghs.h +++ /dev/null @@ -1,113 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_otghs.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32_STM32_OTGHS_H -#define __ARCH_ARM_SRC_STM32_STM32_OTGHS_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include - -#include - -#include "hardware/stm32_otghs.h" - -#if defined(CONFIG_STM32_OTGHS) - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Number of endpoints */ - -#define STM32_NENDPOINTS (4) /* ep0-3 x 2 for IN and OUT */ - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -#ifndef __ASSEMBLY__ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Name: stm32_otgfshost_initialize - * - * Description: - * Initialize USB host device controller hardware. - * - * Input Parameters: - * controller -- If the device supports more than USB host controller, - * then this identifies which controller is being initializeed. - * Normally, this is just zero. - * - * Returned Value: - * And instance of the USB host interface. The controlling task should - * use this interface to (1) call the wait() method to wait for a device - * to be connected, and (2) call the enumerate() method to bind the device - * to a class driver. - * - * Assumptions: - * - This function should called in the initialization sequence in order to - * initialize the USB device functionality. - * - Class drivers should be initialized prior to calling this function. - * Otherwise, there is a race condition if the device is already - * connected. - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_USBHOST -struct usbhost_connection_s; -struct usbhost_connection_s *stm32_otghshost_initialize(int controller); -#endif - -/**************************************************************************** - * Name: stm32_usbsuspend - * - * Description: - * Board logic must provide the stm32_usbsuspend logic if the OTG FS - * device driver is used. This function is called whenever the USB enters - * or leaves suspend mode. This is an opportunity for the board logic to - * shutdown clocks, power, etc. while the USB is suspended. - * - ****************************************************************************/ - -void stm32_usbsuspend(struct usbdev_s *dev, bool resume); - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ -#endif /* CONFIG_STM32_OTGFS */ -#endif /* __ARCH_ARM_SRC_STM32_STM32_OTGHS_H */ diff --git a/arch/arm/src/stm32/stm32_otghsdev.c b/arch/arm/src/stm32/stm32_otghsdev.c deleted file mode 100644 index a4fae9cad4fea..0000000000000 --- a/arch/arm/src/stm32/stm32_otghsdev.c +++ /dev/null @@ -1,5760 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_otghsdev.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include - -#include -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32_otghs.h" -#include "stm32_rcc.h" - -#if defined(CONFIG_USBDEV) && (defined(CONFIG_STM32_OTGHS)) - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -#ifndef CONFIG_USBDEV_EP0_MAXSIZE -# define CONFIG_USBDEV_EP0_MAXSIZE 64 -#endif - -#ifndef CONFIG_USBDEV_SETUP_MAXDATASIZE -# define CONFIG_USBDEV_SETUP_MAXDATASIZE CONFIG_USBDEV_EP0_MAXSIZE -#endif - -#ifndef CONFIG_USBDEV_MAXPOWER -# define CONFIG_USBDEV_MAXPOWER 100 /* mA */ -#endif - -#ifndef CONFIG_DEBUG_USB_INFO -# undef CONFIG_STM32_USBDEV_REGDEBUG -#endif - -/* There is 1.25Kb of FIFO memory. The default partitions this memory - * so that there is a TxFIFO allocated for each endpoint and with more - * memory provided for the common RxFIFO. A more knowledge-able - * configuration would not allocate any TxFIFO space to OUT endpoints. - */ - -#ifndef CONFIG_USBDEV_RXFIFO_SIZE -# define CONFIG_USBDEV_RXFIFO_SIZE 512 -#endif - -#ifndef CONFIG_USBDEV_EP0_TXFIFO_SIZE -# define CONFIG_USBDEV_EP0_TXFIFO_SIZE 192 -#endif - -#ifndef CONFIG_USBDEV_EP1_TXFIFO_SIZE -# define CONFIG_USBDEV_EP1_TXFIFO_SIZE 192 -#endif - -#ifndef CONFIG_USBDEV_EP2_TXFIFO_SIZE -# define CONFIG_USBDEV_EP2_TXFIFO_SIZE 192 -#endif - -#ifndef CONFIG_USBDEV_EP3_TXFIFO_SIZE -# define CONFIG_USBDEV_EP3_TXFIFO_SIZE 192 -#endif - -#if (CONFIG_USBDEV_RXFIFO_SIZE + CONFIG_USBDEV_EP0_TXFIFO_SIZE + \ - CONFIG_USBDEV_EP2_TXFIFO_SIZE + CONFIG_USBDEV_EP3_TXFIFO_SIZE) > 1280 -# error "FIFO allocations exceed FIFO memory size" -#endif - -/* The actual FIFO addresses that we use must be aligned to 4-byte - * boundaries; FIFO sizes must be provided in units of 32-bit words. - */ - -#define STM32_RXFIFO_BYTES ((CONFIG_USBDEV_RXFIFO_SIZE + 3) & ~3) -#define STM32_RXFIFO_WORDS ((CONFIG_USBDEV_RXFIFO_SIZE + 3) >> 2) - -#define STM32_EP0_TXFIFO_BYTES ((CONFIG_USBDEV_EP0_TXFIFO_SIZE + 3) & ~3) -#define STM32_EP0_TXFIFO_WORDS ((CONFIG_USBDEV_EP0_TXFIFO_SIZE + 3) >> 2) - -#if STM32_EP0_TXFIFO_WORDS < 16 || STM32_EP0_TXFIFO_WORDS > 256 -# error "CONFIG_USBDEV_EP0_TXFIFO_SIZE is out of range" -#endif - -#define STM32_EP1_TXFIFO_BYTES ((CONFIG_USBDEV_EP1_TXFIFO_SIZE + 3) & ~3) -#define STM32_EP1_TXFIFO_WORDS ((CONFIG_USBDEV_EP1_TXFIFO_SIZE + 3) >> 2) - -#if STM32_EP1_TXFIFO_WORDS < 16 -# error "CONFIG_USBDEV_EP1_TXFIFO_SIZE is out of range" -#endif - -#define STM32_EP2_TXFIFO_BYTES ((CONFIG_USBDEV_EP2_TXFIFO_SIZE + 3) & ~3) -#define STM32_EP2_TXFIFO_WORDS ((CONFIG_USBDEV_EP2_TXFIFO_SIZE + 3) >> 2) - -#if STM32_EP2_TXFIFO_WORDS < 16 -# error "CONFIG_USBDEV_EP2_TXFIFO_SIZE is out of range" -#endif - -#define STM32_EP3_TXFIFO_BYTES ((CONFIG_USBDEV_EP3_TXFIFO_SIZE + 3) & ~3) -#define STM32_EP3_TXFIFO_WORDS ((CONFIG_USBDEV_EP3_TXFIFO_SIZE + 3) >> 2) - -#if STM32_EP3_TXFIFO_WORDS < 16 -# error "CONFIG_USBDEV_EP3_TXFIFO_SIZE is out of range" -#endif - -/* Debug ********************************************************************/ - -/* Trace error codes */ - -#define STM32_TRACEERR_ALLOCFAIL 0x01 -#define STM32_TRACEERR_BADCLEARFEATURE 0x02 -#define STM32_TRACEERR_BADDEVGETSTATUS 0x03 -#define STM32_TRACEERR_BADEPNO 0x04 -#define STM32_TRACEERR_BADEPGETSTATUS 0x05 -#define STM32_TRACEERR_BADGETCONFIG 0x06 -#define STM32_TRACEERR_BADGETSETDESC 0x07 -#define STM32_TRACEERR_BADGETSTATUS 0x08 -#define STM32_TRACEERR_BADSETADDRESS 0x09 -#define STM32_TRACEERR_BADSETCONFIG 0x0a -#define STM32_TRACEERR_BADSETFEATURE 0x0b -#define STM32_TRACEERR_BADTESTMODE 0x0c -#define STM32_TRACEERR_BINDFAILED 0x0d -#define STM32_TRACEERR_DISPATCHSTALL 0x0e -#define STM32_TRACEERR_DRIVER 0x0f -#define STM32_TRACEERR_DRIVERREGISTERED 0x10 -#define STM32_TRACEERR_EP0NOSETUP 0x11 -#define STM32_TRACEERR_EP0SETUPSTALLED 0x12 -#define STM32_TRACEERR_EPINNULLPACKET 0x13 -#define STM32_TRACEERR_EPINUNEXPECTED 0x14 -#define STM32_TRACEERR_EPOUTNULLPACKET 0x15 -#define STM32_TRACEERR_EPOUTUNEXPECTED 0x16 -#define STM32_TRACEERR_INVALIDCTRLREQ 0x17 -#define STM32_TRACEERR_INVALIDPARMS 0x18 -#define STM32_TRACEERR_IRQREGISTRATION 0x19 -#define STM32_TRACEERR_NOEP 0x1a -#define STM32_TRACEERR_NOTCONFIGURED 0x1b -#define STM32_TRACEERR_EPOUTQEMPTY 0x1c -#define STM32_TRACEERR_EPINREQEMPTY 0x1d -#define STM32_TRACEERR_NOOUTSETUP 0x1e -#define STM32_TRACEERR_POLLTIMEOUT 0x1f - -/* Trace interrupt codes */ - -#define STM32_TRACEINTID_USB 1 /* USB Interrupt entry/exit */ -#define STM32_TRACEINTID_INTPENDING 2 /* On each pass through the loop */ - -#define STM32_TRACEINTID_EPOUT (10 + 0) /* First level interrupt decode */ -#define STM32_TRACEINTID_EPIN (10 + 1) -#define STM32_TRACEINTID_MISMATCH (10 + 2) -#define STM32_TRACEINTID_WAKEUP (10 + 3) -#define STM32_TRACEINTID_SUSPEND (10 + 4) -#define STM32_TRACEINTID_SOF (10 + 5) -#define STM32_TRACEINTID_RXFIFO (10 + 6) -#define STM32_TRACEINTID_DEVRESET (10 + 7) -#define STM32_TRACEINTID_ENUMDNE (10 + 8) -#define STM32_TRACEINTID_IISOIXFR (10 + 9) -#define STM32_TRACEINTID_IISOOXFR (10 + 10) -#define STM32_TRACEINTID_SRQ (10 + 11) -#define STM32_TRACEINTID_OTG (10 + 12) - -#define STM32_TRACEINTID_EPOUT_XFRC (40 + 0) /* EPOUT second level decode */ -#define STM32_TRACEINTID_EPOUT_EPDISD (40 + 1) -#define STM32_TRACEINTID_EPOUT_SETUP (40 + 2) -#define STM32_TRACEINTID_DISPATCH (40 + 3) - -#define STM32_TRACEINTID_GETSTATUS (50 + 0) /* EPOUT third level decode */ -#define STM32_TRACEINTID_EPGETSTATUS (50 + 1) -#define STM32_TRACEINTID_DEVGETSTATUS (50 + 2) -#define STM32_TRACEINTID_IFGETSTATUS (50 + 3) -#define STM32_TRACEINTID_CLEARFEATURE (50 + 4) -#define STM32_TRACEINTID_SETFEATURE (50 + 5) -#define STM32_TRACEINTID_SETADDRESS (50 + 6) -#define STM32_TRACEINTID_GETSETDESC (50 + 7) -#define STM32_TRACEINTID_GETCONFIG (50 + 8) -#define STM32_TRACEINTID_SETCONFIG (50 + 9) -#define STM32_TRACEINTID_GETSETIF (50 + 10) -#define STM32_TRACEINTID_SYNCHFRAME (50 + 11) - -#define STM32_TRACEINTID_EPIN_XFRC (70 + 0) /* EPIN second level decode */ -#define STM32_TRACEINTID_EPIN_TOC (70 + 1) -#define STM32_TRACEINTID_EPIN_ITTXFE (70 + 2) -#define STM32_TRACEINTID_EPIN_EPDISD (70 + 3) -#define STM32_TRACEINTID_EPIN_TXFE (70 + 4) - -#define STM32_TRACEINTID_EPIN_EMPWAIT (80 + 0) /* EPIN second level decode */ - -#define STM32_TRACEINTID_OUTNAK (90 + 0) /* RXFLVL second level decode */ -#define STM32_TRACEINTID_OUTRECVD (90 + 1) -#define STM32_TRACEINTID_OUTDONE (90 + 2) -#define STM32_TRACEINTID_SETUPDONE (90 + 3) -#define STM32_TRACEINTID_SETUPRECVD (90 + 4) - -/* Endpoints ****************************************************************/ - -/* Odd physical endpoint numbers are IN; even are OUT */ - -#define STM32_EPPHYIN2LOG(epphy) ((uint8_t)(epphy)|USB_DIR_IN) -#define STM32_EPPHYOUT2LOG(epphy) ((uint8_t)(epphy)|USB_DIR_OUT) - -/* Endpoint 0 */ - -#define EP0 (0) - -/* The set of all endpoints available to the class implementation (1-3) */ - -#define STM32_EP_AVAILABLE (0x0e) /* All available endpoints */ - -/* Maximum packet sizes for full speed endpoints */ - -#define STM32_MAXPACKET (64) /* Max packet size (1-64) */ - -/* Delays *******************************************************************/ - -#define STM32_READY_DELAY 200000 -#define STM32_FLUSH_DELAY 200000 - -/* Request queue operations *************************************************/ - -#define stm32_rqempty(ep) ((ep)->head == NULL) -#define stm32_rqpeek(ep) ((ep)->head) - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/* Overall device state */ - -enum stm32_devstate_e -{ - DEVSTATE_DEFAULT = 0, /* Power-up, unconfigured state. This state simply - * means that the device is not yet been given an - * address. - * SET: At initialization, uninitialization, - * reset, and whenever the device address - * is set to zero - * TESTED: Never - */ - DEVSTATE_ADDRESSED, /* Device address has been assigned, not no - * configuration has yet been selected. - * SET: When either a non-zero device address - * is first assigned or when the device - * is unconfigured (with configuration == 0) - * TESTED: never - */ - DEVSTATE_CONFIGURED, /* Address assigned and configured: - * SET: When the device has been addressed and - * an non-zero configuration has been selected. - * TESTED: In many places to assure that the USB device - * has been properly configured by the host. - */ -}; - -/* Endpoint 0 states */ - -enum stm32_ep0state_e -{ - EP0STATE_IDLE = 0, /* Idle State, leave on receiving a SETUP packet or - * epsubmit: - * SET: In stm32_epin() and stm32_epout() when - * we revert from request processing to - * SETUP processing. - * TESTED: Never - */ - EP0STATE_SETUP_OUT, /* OUT SETUP packet received. Waiting for the DATA - * OUT phase of SETUP Packet to complete before - * processing a SETUP command (without a USB request): - * SET: Set in stm32_rxinterrupt() when SETUP OUT - * packet is received. - * TESTED: In stm32_ep0out_receive() - */ - EP0STATE_SETUP_READY, /* IN SETUP packet received -OR- OUT SETUP packet and - * accompanying data have been received. Processing - * of SETUP command will happen soon. - * SET: (1) stm32_ep0out_receive() when the OUT - * SETUP data phase completes, or (2) - * stm32_rxinterrupt() when an IN SETUP is - * packet received. - * TESTED: Tested in stm32_epout_interrupt() when - * SETUP phase is done to see if the SETUP - * command is ready to be processed. Also - * tested in stm32_ep0out_setup() just to - * double-check that we have a SETUP request - * and any accompanying data. - */ - EP0STATE_SETUP_PROCESS, /* SETUP Packet is being processed by stm32_ep0out_setup(): - * SET: When SETUP packet received in EP0 OUT - * TESTED: Never - */ - EP0STATE_SETUPRESPONSE, /* Short SETUP response write (without a USB request): - * SET: When SETUP response is sent by - * stm32_ep0in_setupresponse() - * TESTED: Never - */ - EP0STATE_DATA_IN, /* Waiting for data out stage (with a USB request): - * SET: In stm32_epin_request() when a write - * request is processed on EP0. - * TESTED: In stm32_epin() to see if we should - * revert to SETUP processing. - */ - EP0STATE_DATA_OUT /* Waiting for data in phase to complete ( with a - * USB request) - * SET: In stm32_epout_request() when a read - * request is processed on EP0. - * TESTED: In stm32_epout() to see if we should - * revert to SETUP processing - */ -}; - -/* Parsed control request */ - -struct stm32_ctrlreq_s -{ - uint8_t type; - uint8_t req; - uint16_t value; - uint16_t index; - uint16_t len; -}; - -/* A container for a request so that the request may be retained in a list */ - -struct stm32_req_s -{ - struct usbdev_req_s req; /* Standard USB request */ - struct stm32_req_s *flink; /* Supports a singly linked list */ -}; - -/* This is the internal representation of an endpoint */ - -struct stm32_ep_s -{ - /* Common endpoint fields. This must be the first thing defined in the - * structure so that it is possible to simply cast from struct usbdev_ep_s - * to struct stm32_ep_s. - */ - - struct usbdev_ep_s ep; /* Standard endpoint structure */ - - /* STM32-specific fields */ - - struct stm32_usbdev_s *dev; /* Reference to private driver data */ - struct stm32_req_s *head; /* Request list for this endpoint */ - struct stm32_req_s *tail; - uint8_t epphy; /* Physical EP address */ - uint8_t eptype:2; /* Endpoint type */ - uint8_t active:1; /* 1: A request is being processed */ - uint8_t stalled:1; /* 1: Endpoint is stalled */ - uint8_t isin:1; /* 1: IN Endpoint */ - uint8_t odd:1; /* 1: Odd frame */ - uint8_t zlp:1; /* 1: Transmit a zero-length-packet (IN EPs only) */ -}; - -/* This structure retains the state of the USB device controller */ - -struct stm32_usbdev_s -{ - /* Common device fields. This must be the first thing defined in the - * structure so that it is possible to simply cast from struct usbdev_s - * to struct stm32_usbdev_s. - */ - - struct usbdev_s usbdev; - - /* The bound device class driver */ - - struct usbdevclass_driver_s *driver; - - /* STM32-specific fields */ - - uint8_t stalled:1; /* 1: Protocol stalled */ - uint8_t selfpowered:1; /* 1: Device is self powered */ - uint8_t addressed:1; /* 1: Peripheral address has been set */ - uint8_t configured:1; /* 1: Class driver has been configured */ - uint8_t wakeup:1; /* 1: Device remote wake-up */ - uint8_t dotest:1; /* 1: Test mode selected */ - - uint8_t devstate:4; /* See enum stm32_devstate_e */ - uint8_t ep0state:4; /* See enum stm32_ep0state_e */ - uint8_t testmode:4; /* Selected test mode */ - uint8_t epavail[2]; /* Bitset of available OUT/IN endpoints */ - - /* E0 SETUP data buffering. - * - * ctrlreq: - * The 8-byte SETUP request is received on the EP0 OUT endpoint and is - * saved. - * - * ep0data - * For OUT SETUP requests, the SETUP data phase must also complete before - * the SETUP command can be processed. The pack receipt logic will save - * the accompanying EP0 IN data in ep0data[] before the SETUP command is - * processed. - * - * For IN SETUP requests, the DATA phase will occur AFTER the SETUP - * control request is processed. In that case, ep0data[] may be used as - * the response buffer. - * - * ep0datlen - * Length of OUT DATA received in ep0data[] (Not used with OUT data) - */ - - struct usb_ctrlreq_s ctrlreq; - uint8_t ep0data[CONFIG_USBDEV_SETUP_MAXDATASIZE]; - uint16_t ep0datlen; - - /* The endpoint lists */ - - struct stm32_ep_s epin[STM32_NENDPOINTS]; - struct stm32_ep_s epout[STM32_NENDPOINTS]; -}; - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -/* Register operations ******************************************************/ - -#ifdef CONFIG_STM32_USBDEV_REGDEBUG -static uint32_t stm32_getreg(uint32_t addr); -static void stm32_putreg(uint32_t val, uint32_t addr); -#else -# define stm32_getreg(addr) getreg32(addr) -# define stm32_putreg(val,addr) putreg32(val,addr) -#endif - -/* Request queue operations *************************************************/ - -static struct stm32_req_s *stm32_req_remfirst( - struct stm32_ep_s *privep); -static bool stm32_req_addlast(struct stm32_ep_s *privep, - struct stm32_req_s *req); - -/* Low level data transfers and request operations **************************/ - -/* Special endpoint 0 data transfer logic */ - -static void stm32_ep0in_setupresponse(struct stm32_usbdev_s *priv, - uint8_t *data, uint32_t nbytes); -static inline void stm32_ep0in_transmitzlp(struct stm32_usbdev_s *priv); -static void stm32_ep0in_activate(void); - -static void stm32_ep0out_ctrlsetup(struct stm32_usbdev_s *priv); - -/* IN request and TxFIFO handling */ - -static void stm32_txfifo_write(struct stm32_ep_s *privep, - uint8_t *buf, int nbytes); -static void stm32_epin_transfer(struct stm32_ep_s *privep, - uint8_t *buf, int nbytes); -static void stm32_epin_request(struct stm32_usbdev_s *priv, - struct stm32_ep_s *privep); - -/* OUT request and RxFIFO handling */ - -static void stm32_rxfifo_read(struct stm32_ep_s *privep, - uint8_t *dest, uint16_t len); -static void stm32_rxfifo_discard(struct stm32_ep_s *privep, - int len); -static void stm32_epout_complete(struct stm32_usbdev_s *priv, - struct stm32_ep_s *privep); -static inline void stm32_ep0out_receive(struct stm32_ep_s *privep, - int bcnt); -static inline void stm32_epout_receive(struct stm32_ep_s *privep, - int bcnt); -static void stm32_epout_request(struct stm32_usbdev_s *priv, - struct stm32_ep_s *privep); - -/* General request handling */ - -static void stm32_ep_flush(struct stm32_ep_s *privep); -static void stm32_req_complete(struct stm32_ep_s *privep, - int16_t result); -static void stm32_req_cancel(struct stm32_ep_s *privep, - int16_t status); - -/* Interrupt handling *******************************************************/ - -static struct stm32_ep_s *stm32_ep_findbyaddr( - struct stm32_usbdev_s *priv, uint16_t eplog); -static int stm32_req_dispatch(struct stm32_usbdev_s *priv, - const struct usb_ctrlreq_s *ctrl); -static void stm32_usbreset(struct stm32_usbdev_s *priv); - -/* Second level OUT endpoint interrupt processing */ - -static inline void stm32_ep0out_testmode(struct stm32_usbdev_s *priv, - uint16_t index); -static inline void stm32_ep0out_stdrequest(struct stm32_usbdev_s *priv, - struct stm32_ctrlreq_s *ctrlreq); -static inline void stm32_ep0out_setup(struct stm32_usbdev_s *priv); -static inline void stm32_epout(struct stm32_usbdev_s *priv, - uint8_t epno); -static inline void stm32_epout_interrupt(struct stm32_usbdev_s *priv); - -/* Second level IN endpoint interrupt processing */ - -static inline void stm32_epin_runtestmode(struct stm32_usbdev_s *priv); -static inline void stm32_epin(struct stm32_usbdev_s *priv, uint8_t epno); -static inline void stm32_epin_txfifoempty(struct stm32_usbdev_s *priv, - int epno); -static inline void stm32_epin_interrupt(struct stm32_usbdev_s *priv); - -/* Other second level interrupt processing */ - -static inline void stm32_resumeinterrupt(struct stm32_usbdev_s *priv); -static inline void stm32_suspendinterrupt(struct stm32_usbdev_s *priv); -static inline void stm32_rxinterrupt(struct stm32_usbdev_s *priv); -static inline void stm32_enuminterrupt(struct stm32_usbdev_s *priv); -#ifdef CONFIG_USBDEV_ISOCHRONOUS -static inline void stm32_isocininterrupt(struct stm32_usbdev_s *priv); -static inline void stm32_isocoutinterrupt(struct stm32_usbdev_s *priv); -#endif -#ifdef CONFIG_USBDEV_VBUSSENSING -static inline void stm32_sessioninterrupt(struct stm32_usbdev_s *priv); -static inline void stm32_otginterrupt(struct stm32_usbdev_s *priv); -#endif - -/* First level interrupt processing */ - -static int stm32_usbinterrupt(int irq, void *context, - void *arg); - -/* Endpoint operations ******************************************************/ - -/* Global OUT NAK controls */ - -static void stm32_enablegonak(struct stm32_ep_s *privep); -static void stm32_disablegonak(struct stm32_ep_s *privep); - -/* Endpoint configuration */ - -static int stm32_epout_configure(struct stm32_ep_s *privep, - uint8_t eptype, uint16_t maxpacket); -static int stm32_epin_configure(struct stm32_ep_s *privep, - uint8_t eptype, uint16_t maxpacket); -static int stm32_ep_configure(struct usbdev_ep_s *ep, - const struct usb_epdesc_s *desc, bool last); -static void stm32_ep0_configure(struct stm32_usbdev_s *priv); - -/* Endpoint disable */ - -static void stm32_epout_disable(struct stm32_ep_s *privep); -static void stm32_epin_disable(struct stm32_ep_s *privep); -static int stm32_ep_disable(struct usbdev_ep_s *ep); - -/* Endpoint request management */ - -static struct usbdev_req_s *stm32_ep_allocreq( - struct usbdev_ep_s *ep); -static void stm32_ep_freereq(struct usbdev_ep_s *ep, - struct usbdev_req_s *); - -/* Endpoint buffer management */ - -#ifdef CONFIG_USBDEV_DMA -static void *stm32_ep_allocbuffer(struct usbdev_ep_s *ep, - uint16_t bytes); -static void stm32_ep_freebuffer(struct usbdev_ep_s *ep, - void *buf); -#endif - -/* Endpoint request submission */ - -static int stm32_ep_submit(struct usbdev_ep_s *ep, - struct usbdev_req_s *req); - -/* Endpoint request cancellation */ - -static int stm32_ep_cancel(struct usbdev_ep_s *ep, - struct usbdev_req_s *req); - -/* Stall handling */ - -static int stm32_epout_setstall(struct stm32_ep_s *privep); -static int stm32_epin_setstall(struct stm32_ep_s *privep); -static int stm32_ep_setstall(struct stm32_ep_s *privep); -static int stm32_ep_clrstall(struct stm32_ep_s *privep); -static int stm32_ep_stall(struct usbdev_ep_s *ep, bool resume); -static void stm32_ep0_stall(struct stm32_usbdev_s *priv); - -/* Endpoint allocation */ - -static struct usbdev_ep_s *stm32_ep_alloc(struct usbdev_s *dev, - uint8_t epno, bool in, uint8_t eptype); -static void stm32_ep_free(struct usbdev_s *dev, - struct usbdev_ep_s *ep); - -/* USB device controller operations *****************************************/ - -static int stm32_getframe(struct usbdev_s *dev); -static int stm32_wakeup(struct usbdev_s *dev); -static int stm32_selfpowered(struct usbdev_s *dev, bool selfpowered); -static int stm32_pullup(struct usbdev_s *dev, bool enable); -static void stm32_setaddress(struct stm32_usbdev_s *priv, - uint16_t address); -static int stm32_txfifo_flush(uint32_t txfnum); -static int stm32_rxfifo_flush(void); - -/* Initialization ***********************************************************/ - -static void stm32_swinitialize(struct stm32_usbdev_s *priv); -static void stm32_hwinitialize(struct stm32_usbdev_s *priv); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* Since there is only a single USB interface, all status information can be - * be simply retained in a single global instance. - */ - -static struct stm32_usbdev_s g_otghsdev; - -static const struct usbdev_epops_s g_epops = -{ - .configure = stm32_ep_configure, - .disable = stm32_ep_disable, - .allocreq = stm32_ep_allocreq, - .freereq = stm32_ep_freereq, -#ifdef CONFIG_USBDEV_DMA - .allocbuffer = stm32_ep_allocbuffer, - .freebuffer = stm32_ep_freebuffer, -#endif - .submit = stm32_ep_submit, - .cancel = stm32_ep_cancel, - .stall = stm32_ep_stall, -}; - -static const struct usbdev_ops_s g_devops = -{ - .allocep = stm32_ep_alloc, - .freeep = stm32_ep_free, - .getframe = stm32_getframe, - .wakeup = stm32_wakeup, - .selfpowered = stm32_selfpowered, - .pullup = stm32_pullup, -}; - -/* Device error strings that may be enabled for more descriptive USB trace - * output. - */ - -#ifdef CONFIG_USBDEV_TRACE_STRINGS -const struct trace_msg_t g_usb_trace_strings_deverror[] = -{ - TRACE_STR(STM32_TRACEERR_ALLOCFAIL), - TRACE_STR(STM32_TRACEERR_BADCLEARFEATURE), - TRACE_STR(STM32_TRACEERR_BADDEVGETSTATUS), - TRACE_STR(STM32_TRACEERR_BADEPNO), - TRACE_STR(STM32_TRACEERR_BADEPGETSTATUS), - TRACE_STR(STM32_TRACEERR_BADGETCONFIG), - TRACE_STR(STM32_TRACEERR_BADGETSETDESC), - TRACE_STR(STM32_TRACEERR_BADGETSTATUS), - TRACE_STR(STM32_TRACEERR_BADSETADDRESS), - TRACE_STR(STM32_TRACEERR_BADSETCONFIG), - TRACE_STR(STM32_TRACEERR_BADSETFEATURE), - TRACE_STR(STM32_TRACEERR_BADTESTMODE), - TRACE_STR(STM32_TRACEERR_BINDFAILED), - TRACE_STR(STM32_TRACEERR_DISPATCHSTALL), - TRACE_STR(STM32_TRACEERR_DRIVER), - TRACE_STR(STM32_TRACEERR_DRIVERREGISTERED), - TRACE_STR(STM32_TRACEERR_EP0NOSETUP), - TRACE_STR(STM32_TRACEERR_EP0SETUPSTALLED), - TRACE_STR(STM32_TRACEERR_EPINNULLPACKET), - TRACE_STR(STM32_TRACEERR_EPINUNEXPECTED), - TRACE_STR(STM32_TRACEERR_EPOUTNULLPACKET), - TRACE_STR(STM32_TRACEERR_EPOUTUNEXPECTED), - TRACE_STR(STM32_TRACEERR_INVALIDCTRLREQ), - TRACE_STR(STM32_TRACEERR_INVALIDPARMS), - TRACE_STR(STM32_TRACEERR_IRQREGISTRATION), - TRACE_STR(STM32_TRACEERR_NOEP), - TRACE_STR(STM32_TRACEERR_NOTCONFIGURED), - TRACE_STR(STM32_TRACEERR_EPOUTQEMPTY), - TRACE_STR(STM32_TRACEERR_EPINREQEMPTY), - TRACE_STR(STM32_TRACEERR_NOOUTSETUP), - TRACE_STR(STM32_TRACEERR_POLLTIMEOUT), - TRACE_STR_END -}; -#endif - -/* Interrupt event strings that may be enabled for more descriptive USB trace - * output. - */ - -#ifdef CONFIG_USBDEV_TRACE_STRINGS -const struct trace_msg_t g_usb_trace_strings_intdecode[] = -{ - TRACE_STR(STM32_TRACEINTID_USB), - TRACE_STR(STM32_TRACEINTID_INTPENDING), - TRACE_STR(STM32_TRACEINTID_EPOUT), - TRACE_STR(STM32_TRACEINTID_EPIN), - TRACE_STR(STM32_TRACEINTID_MISMATCH), - TRACE_STR(STM32_TRACEINTID_WAKEUP), - TRACE_STR(STM32_TRACEINTID_SUSPEND), - TRACE_STR(STM32_TRACEINTID_SOF), - TRACE_STR(STM32_TRACEINTID_RXFIFO), - TRACE_STR(STM32_TRACEINTID_DEVRESET), - TRACE_STR(STM32_TRACEINTID_ENUMDNE), - TRACE_STR(STM32_TRACEINTID_IISOIXFR), - TRACE_STR(STM32_TRACEINTID_IISOOXFR), - TRACE_STR(STM32_TRACEINTID_SRQ), - TRACE_STR(STM32_TRACEINTID_OTG), - TRACE_STR(STM32_TRACEINTID_EPOUT_XFRC), - TRACE_STR(STM32_TRACEINTID_EPOUT_EPDISD), - TRACE_STR(STM32_TRACEINTID_EPOUT_SETUP), - TRACE_STR(STM32_TRACEINTID_DISPATCH), - TRACE_STR(STM32_TRACEINTID_GETSTATUS), - TRACE_STR(STM32_TRACEINTID_EPGETSTATUS), - TRACE_STR(STM32_TRACEINTID_DEVGETSTATUS), - TRACE_STR(STM32_TRACEINTID_IFGETSTATUS), - TRACE_STR(STM32_TRACEINTID_CLEARFEATURE), - TRACE_STR(STM32_TRACEINTID_SETFEATURE), - TRACE_STR(STM32_TRACEINTID_SETADDRESS), - TRACE_STR(STM32_TRACEINTID_GETSETDESC), - TRACE_STR(STM32_TRACEINTID_GETCONFIG), - TRACE_STR(STM32_TRACEINTID_SETCONFIG), - TRACE_STR(STM32_TRACEINTID_GETSETIF), - TRACE_STR(STM32_TRACEINTID_SYNCHFRAME), - TRACE_STR(STM32_TRACEINTID_EPIN_XFRC), - TRACE_STR(STM32_TRACEINTID_EPIN_TOC), - TRACE_STR(STM32_TRACEINTID_EPIN_ITTXFE), - TRACE_STR(STM32_TRACEINTID_EPIN_EPDISD), - TRACE_STR(STM32_TRACEINTID_EPIN_TXFE), - TRACE_STR(STM32_TRACEINTID_EPIN_EMPWAIT), - TRACE_STR(STM32_TRACEINTID_OUTNAK), - TRACE_STR(STM32_TRACEINTID_OUTRECVD), - TRACE_STR(STM32_TRACEINTID_OUTDONE), - TRACE_STR(STM32_TRACEINTID_SETUPDONE), - TRACE_STR(STM32_TRACEINTID_SETUPRECVD), - TRACE_STR_END -}; -#endif - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_getreg - * - * Description: - * Get the contents of an STM32 register - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_USBDEV_REGDEBUG -static uint32_t stm32_getreg(uint32_t addr) -{ - static uint32_t prevaddr = 0; - static uint32_t preval = 0; - static uint32_t count = 0; - - /* Read the value from the register */ - - uint32_t val = getreg32(addr); - - /* Is this the same value that we read from the same register last time? - * Are we polling the register? If so, suppress some of the output. - */ - - if (addr == prevaddr && val == preval) - { - if (count == 0xffffffff || ++count > 3) - { - if (count == 4) - { - uinfo("...\n"); - } - - return val; - } - } - - /* No this is a new address or value */ - - else - { - /* Did we print "..." for the previous value? */ - - if (count > 3) - { - /* Yes.. then show how many times the value repeated */ - - uinfo("[repeats %d more times]\n", count - 3); - } - - /* Save the new address, value, and count */ - - prevaddr = addr; - preval = val; - count = 1; - } - - /* Show the register value read */ - - uinfo("%08" PRIx32 "->%08" PRIx32 "\n", addr, val); - return val; -} -#endif - -/**************************************************************************** - * Name: stm32_putreg - * - * Description: - * Set the contents of an STM32 register to a value - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_USBDEV_REGDEBUG -static void stm32_putreg(uint32_t val, uint32_t addr) -{ - /* Show the register value being written */ - - uinfo("%08" PRIx32 "<-%08" PRIx32 "\n", addr, val); - - /* Write the value */ - - putreg32(val, addr); -} -#endif - -/**************************************************************************** - * Name: stm32_req_remfirst - * - * Description: - * Remove a request from the head of an endpoint request queue - * - ****************************************************************************/ - -static struct stm32_req_s *stm32_req_remfirst( - struct stm32_ep_s *privep) -{ - struct stm32_req_s *ret = privep->head; - - if (ret) - { - privep->head = ret->flink; - if (!privep->head) - { - privep->tail = NULL; - } - - ret->flink = NULL; - } - - return ret; -} - -/**************************************************************************** - * Name: stm32_req_addlast - * - * Description: - * Add a request to the end of an endpoint request queue - * - ****************************************************************************/ - -static bool stm32_req_addlast(struct stm32_ep_s *privep, - struct stm32_req_s *req) -{ - bool is_empty = !privep->head; - - req->flink = NULL; - if (is_empty) - { - privep->head = req; - privep->tail = req; - } - else - { - privep->tail->flink = req; - privep->tail = req; - } - - return is_empty; -} - -/**************************************************************************** - * Name: stm32_ep0in_setupresponse - * - * Description: - * Schedule a short transfer on Endpoint 0 (IN or OUT) - * - ****************************************************************************/ - -static void stm32_ep0in_setupresponse(struct stm32_usbdev_s *priv, - uint8_t *buf, uint32_t nbytes) -{ - stm32_epin_transfer(&priv->epin[EP0], buf, nbytes); - priv->ep0state = EP0STATE_SETUPRESPONSE; - stm32_ep0out_ctrlsetup(priv); -} - -/**************************************************************************** - * Name: stm32_ep0in_transmitzlp - * - * Description: - * Send a zero length packet (ZLP) on endpoint 0 IN - * - ****************************************************************************/ - -static inline void stm32_ep0in_transmitzlp(struct stm32_usbdev_s *priv) -{ - stm32_ep0in_setupresponse(priv, NULL, 0); -} - -/**************************************************************************** - * Name: stm32_ep0in_activate - * - * Description: - * Activate the endpoint 0 IN endpoint. - * - ****************************************************************************/ - -static void stm32_ep0in_activate(void) -{ - uint32_t regval; - - /* Set the max packet size of the IN EP. */ - - regval = stm32_getreg(STM32_OTGHS_DIEPCTL0); - regval &= ~OTGHS_DIEPCTL0_MPSIZ_MASK; - -#if CONFIG_USBDEV_EP0_MAXSIZE == 8 - regval |= OTGHS_DIEPCTL0_MPSIZ_8; -#elif CONFIG_USBDEV_EP0_MAXSIZE == 16 - regval |= OTGHS_DIEPCTL0_MPSIZ_16; -#elif CONFIG_USBDEV_EP0_MAXSIZE == 32 - regval |= OTGHS_DIEPCTL0_MPSIZ_32; -#elif CONFIG_USBDEV_EP0_MAXSIZE == 64 - regval |= OTGHS_DIEPCTL0_MPSIZ_64; -#else -# error "Unsupported value of CONFIG_USBDEV_EP0_MAXSIZE" -#endif - - stm32_putreg(regval, STM32_OTGHS_DIEPCTL0); - - /* Clear global IN NAK */ - - regval = stm32_getreg(STM32_OTGHS_DCTL); - regval |= OTGHS_DCTL_CGINAK; - stm32_putreg(regval, STM32_OTGHS_DCTL); -} - -/**************************************************************************** - * Name: stm32_ep0out_ctrlsetup - * - * Description: - * Setup to receive a SETUP packet. - * - ****************************************************************************/ - -static void stm32_ep0out_ctrlsetup(struct stm32_usbdev_s *priv) -{ - uint32_t regval; - - /* Setup the hardware to perform the SETUP transfer */ - - regval = (USB_SIZEOF_CTRLREQ * 3 << OTGHS_DOEPTSIZ0_XFRSIZ_SHIFT) | - (OTGHS_DOEPTSIZ0_PKTCNT) | - (3 << OTGHS_DOEPTSIZ0_STUPCNT_SHIFT); - stm32_putreg(regval, STM32_OTGHS_DOEPTSIZ0); - - /* Then clear NAKing and enable the transfer */ - - regval = stm32_getreg(STM32_OTGHS_DOEPCTL0); - regval |= (OTGHS_DOEPCTL0_CNAK | OTGHS_DOEPCTL0_EPENA); - stm32_putreg(regval, STM32_OTGHS_DOEPCTL0); -} - -/**************************************************************************** - * Name: stm32_txfifo_write - * - * Description: - * Send data to the endpoint's TxFIFO. - * - ****************************************************************************/ - -static void stm32_txfifo_write(struct stm32_ep_s *privep, - uint8_t *buf, int nbytes) -{ - uint32_t regaddr; - uint32_t regval; - int nwords; - int i; - - /* Convert the number of bytes to words */ - - nwords = (nbytes + 3) >> 2; - - /* Get the TxFIFO for this endpoint (same as the endpoint number) */ - - regaddr = STM32_OTGHS_DFIFO_DEP(privep->epphy); - - /* Then transfer each word to the TxFIFO */ - - for (i = 0; i < nwords; i++) - { - /* Read four bytes from the source buffer (to avoid unaligned accesses) - * and pack these into one 32-bit word (little endian). - */ - - regval = (uint32_t)*buf++; - regval |= ((uint32_t)*buf++) << 8; - regval |= ((uint32_t)*buf++) << 16; - regval |= ((uint32_t)*buf++) << 24; - - /* Then write the packet data to the TxFIFO */ - - stm32_putreg(regval, regaddr); - } -} - -/**************************************************************************** - * Name: stm32_epin_transfer - * - * Description: - * Start the Tx data transfer - * - ****************************************************************************/ - -static void stm32_epin_transfer(struct stm32_ep_s *privep, - uint8_t *buf, int nbytes) -{ - uint32_t pktcnt; - uint32_t regval; - - /* Read the DIEPSIZx register */ - - regval = stm32_getreg(STM32_OTGHS_DIEPTSIZ(privep->epphy)); - - /* Clear the XFRSIZ, PKTCNT, and MCNT field of the DIEPSIZx register */ - - regval &= ~(OTGHS_DIEPTSIZ_XFRSIZ_MASK | OTGHS_DIEPTSIZ_PKTCNT_MASK | - OTGHS_DIEPTSIZ_MCNT_MASK); - - /* Are we sending a zero length packet (ZLP) */ - - if (nbytes == 0) - { - /* Yes.. - * leave the transfer size at zero and set the packet count to 1 - */ - - pktcnt = 1; - } - else - { - /* No.. Program the transfer size and packet count . First calculate: - * - * xfrsize = The total number of bytes to be sent. - * pktcnt = the number of packets (of maxpacket bytes) required to - * perform the transfer. - */ - - pktcnt = ((uint32_t)nbytes + (privep->ep.maxpacket - 1)) / - privep->ep.maxpacket; - } - - /* Set the XFRSIZ and PKTCNT */ - - regval |= (pktcnt << OTGHS_DIEPTSIZ_PKTCNT_SHIFT); - regval |= ((uint32_t)nbytes << OTGHS_DIEPTSIZ_XFRSIZ_SHIFT); - - /* If this is an isochronous endpoint, then set the multi-count field to - * the PKTCNT as well. - */ - - if (privep->eptype == USB_EP_ATTR_XFER_ISOC) - { - regval |= (pktcnt << OTGHS_DIEPTSIZ_MCNT_SHIFT); - } - - /* Save DIEPSIZx register value */ - - stm32_putreg(regval, STM32_OTGHS_DIEPTSIZ(privep->epphy)); - - /* Read the DIEPCTLx register */ - - regval = stm32_getreg(STM32_OTGHS_DIEPCTL(privep->epphy)); - - /* If this is an isochronous endpoint, then set the even/odd frame bit - * the DIEPCTLx register. - */ - - if (privep->eptype == USB_EP_ATTR_XFER_ISOC) - { - /* Check bit 0 of the frame number of the received SOF and set the - * even/odd frame to match. - */ - - uint32_t status = stm32_getreg(STM32_OTGHS_DSTS); - if ((status & OTGHS_DSTS_SOFFN0) == OTGHS_DSTS_SOFFN_EVEN) - { - regval |= OTGHS_DIEPCTL_SEVNFRM; - } - else - { - regval |= OTGHS_DIEPCTL_SODDFRM; - } - } - - /* EP enable, IN data in FIFO */ - - regval &= ~OTGHS_DIEPCTL_EPDIS; - regval |= (OTGHS_DIEPCTL_CNAK | OTGHS_DIEPCTL_EPENA); - stm32_putreg(regval, STM32_OTGHS_DIEPCTL(privep->epphy)); - - /* Transfer the data to the TxFIFO. At this point, the caller has already - * assured that there is sufficient space in the TxFIFO to hold the - * transfer we can just blindly continue. - */ - - stm32_txfifo_write(privep, buf, nbytes); -} - -/**************************************************************************** - * Name: stm32_epin_request - * - * Description: - * Begin or continue write request processing. - * - ****************************************************************************/ - -static void stm32_epin_request(struct stm32_usbdev_s *priv, - struct stm32_ep_s *privep) -{ - struct stm32_req_s *privreq; - uint32_t regaddr; - uint32_t regval; - uint8_t *buf; - int nbytes; - int nwords; - int bytesleft; - - /* We get here in one of four possible ways. From three interrupting - * events: - * - * 1. From stm32_epin as part of the transfer complete interrupt processing - * This interrupt indicates that the last transfer has completed. - * 2. As part of the ITTXFE interrupt processing. That interrupt indicates - * that an IN token was received when the associated TxFIFO was empty. - * 3. From stm32_epin_txfifoempty as part of the TXFE interrupt processing. - * The TXFE interrupt is only enabled when the TxFIFO is full and the - * software must wait for space to become available in the TxFIFO. - * - * And this function may be called immediately when the write request is - * queue to start up the next transaction. - * - * 4. From stm32_ep_submit when a new write request is received WHILE the - * endpoint is not active (privep->active == false). - */ - - /* Check the request from the head of the endpoint request queue */ - - privreq = stm32_rqpeek(privep); - if (!privreq) - { - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EPINREQEMPTY), privep->epphy); - - /* There is no TX transfer in progress and no new pending TX - * requests to send. To stop transmitting any data on a particular - * IN endpoint, the application must set the IN NAK bit. To set this - * bit, the following field must be programmed. - */ - - regaddr = STM32_OTGHS_DIEPCTL(privep->epphy); - regval = stm32_getreg(regaddr); - regval |= OTGHS_DIEPCTL_SNAK; - stm32_putreg(regval, regaddr); - - /* The endpoint is no longer active */ - - privep->active = false; - return; - } - - uinfo("EP%d req=%p: len=%zu xfrd=%zu zlp=%d\n", - privep->epphy, privreq, privreq->req.len, - privreq->req.xfrd, privep->zlp); - - /* Check for a special case: If we are just starting a request (xfrd==0) - * and the class driver is trying to send a zero-length packet (len==0). - * Then set the ZLP flag so that the packet will be sent. - */ - - if (privreq->req.len == 0) - { - /* The ZLP flag is set TRUE whenever we want to force the driver to - * send a zero-length-packet on the next pass through the loop (below). - * The flag is cleared whenever a packet is sent in the loop below. - */ - - privep->zlp = true; - } - - /* Add one more packet to the TxFIFO. We will wait for the transfer - * complete event before we add the next packet (or part of a packet - * to the TxFIFO). - * - * The documentation says that we can can multiple packets to the TxFIFO, - * but it seems that we need to get the transfer complete event before - * we can add the next (or maybe I have got something wrong?) - */ - -#if 0 - while (privreq->req.xfrd < privreq->req.len || privep->zlp) -#else - if (privreq->req.xfrd < privreq->req.len || privep->zlp) -#endif - { - /* Get the number of bytes left to be sent in the request */ - - bytesleft = privreq->req.len - privreq->req.xfrd; - nbytes = bytesleft; - - /* Assume no zero-length-packet on the next pass through this loop */ - - privep->zlp = false; - - /* Limit the size of the transfer to one full packet and handle - * zero-length packets (ZLPs). - */ - - if (nbytes > 0) - { - /* Either send the maxpacketsize or all of the remaining data in - * the request. - */ - - if (nbytes >= privep->ep.maxpacket) - { - nbytes = privep->ep.maxpacket; - - /* Handle the case where this packet is exactly the - * maxpacketsize. Do we need to send a zero-length packet - * in this case? - */ - - if (bytesleft == privep->ep.maxpacket && - (privreq->req.flags & USBDEV_REQFLAGS_NULLPKT) != 0) - { - /* The ZLP flag is set TRUE whenever we want to force - * the driver to send a zero-length-packet on the next - * pass through this loop. The flag is cleared (above) - * whenever we are committed to sending any packet and - * set here when we want to force one more pass through - * the loop. - */ - - privep->zlp = true; - } - } - } - - /* Get the transfer size in 32-bit words */ - - nwords = (nbytes + 3) >> 2; - - /* Get the number of 32-bit words available in the TxFIFO. The - * DXTHSTS indicates the amount of free space available in the - * endpoint TxFIFO. Values are in terms of 32-bit words: - * - * 0: Endpoint TxFIFO is full - * 1: 1 word available - * 2: 2 words available - * n: n words available - */ - - regaddr = STM32_OTGHS_DTXFSTS(privep->epphy); - - /* Check for space in the TxFIFO. If space in the TxFIFO is not - * available, then set up an interrupt to resume the transfer when - * the TxFIFO is empty. - */ - - regval = stm32_getreg(regaddr); - if ((int)(regval & OTGHS_DTXFSTS_MASK) < nwords) - { - usbtrace( - TRACE_INTDECODE(STM32_TRACEINTID_EPIN_EMPWAIT), - (uint16_t)regval); - - /* There is insufficient space in the TxFIFO. Wait for a TxFIFO - * empty interrupt and try again. - */ - - uint32_t empmsk = stm32_getreg(STM32_OTGHS_DIEPEMPMSK); - empmsk |= OTGHS_DIEPEMPMSK(privep->epphy); - stm32_putreg(empmsk, STM32_OTGHS_DIEPEMPMSK); - -#ifdef CONFIG_DEBUG_FEATURES - /* Check if the configured TXFIFO size is sufficient for a given - * request. If not, raise an assertion here. - */ - - regval = stm32_getreg(STM32_OTGHS_DIEPTXF(privep->epphy)); - regval &= OTGHS_DIEPTXF_INEPTXFD_MASK; - regval >>= OTGHS_DIEPTXF_INEPTXFD_SHIFT; - uerr("EP%" PRId8 " TXLEN=%" PRId32 " nwords=%d\n", - privep->epphy, regval, nwords); - DEBUGASSERT(regval >= nwords); -#endif - - /* Terminate the transfer. We will try again when the TxFIFO empty - * interrupt is received. - */ - - return; - } - - /* Transfer data to the TxFIFO */ - - buf = privreq->req.buf + privreq->req.xfrd; - stm32_epin_transfer(privep, buf, nbytes); - - /* If it was not before, the OUT endpoint is now actively transferring - * data. - */ - - privep->active = true; - - /* EP0 is a special case */ - - if (privep->epphy == EP0) - { - priv->ep0state = EP0STATE_DATA_IN; - } - - /* Update for the next time through the loop */ - - privreq->req.xfrd += nbytes; - } - - /* Note that the ZLP, if any, must be sent as a separate transfer. The need - * for a ZLP is indicated by privep->zlp. If all of the bytes were sent - * (including any final null packet) then we are finished with the transfer - */ - - if (privreq->req.xfrd >= privreq->req.len && !privep->zlp) - { - usbtrace(TRACE_COMPLETE(privep->epphy), privreq->req.xfrd); - - /* We are finished with the request (although the transfer has not - * yet completed). - */ - - stm32_req_complete(privep, OK); - } -} - -/**************************************************************************** - * Name: stm32_rxfifo_read - * - * Description: - * Read packet from the RxFIFO into a read request. - * - ****************************************************************************/ - -static void stm32_rxfifo_read(struct stm32_ep_s *privep, - uint8_t *dest, uint16_t len) -{ - uint32_t regaddr; - int i; - - /* Get the address of the RxFIFO. Note: there is only one RxFIFO so - * we might as well use the address associated with EP0. - */ - - regaddr = STM32_OTGHS_DFIFO_DEP(EP0); - - /* Read 32-bits and write 4 x 8-bits at time - * (to avoid unaligned accesses) - */ - - for (i = 0; i < len; i += 4) - { - union - { - uint32_t w; - uint8_t b[4]; - } data; - - /* Read 1 x 32-bits of EP0 packet data */ - - data.w = stm32_getreg(regaddr); - - /* Write 4 x 8-bits of EP0 packet data */ - - *dest++ = data.b[0]; - *dest++ = data.b[1]; - *dest++ = data.b[2]; - *dest++ = data.b[3]; - } -} - -/**************************************************************************** - * Name: stm32_rxfifo_discard - * - * Description: - * Discard packet data from the RxFIFO. - * - ****************************************************************************/ - -static void stm32_rxfifo_discard(struct stm32_ep_s *privep, int len) -{ - if (len > 0) - { - uint32_t regaddr; - int i; - - /* Get the address of the RxFIFO Note: there is only one RxFIFO so - * we might as well use the address associated with EP0. - */ - - regaddr = STM32_OTGHS_DFIFO_DEP(EP0); - - /* Read 32-bits at time */ - - for (i = 0; i < len; i += 4) - { - volatile uint32_t data = stm32_getreg(regaddr); - UNUSED(data); - } - } -} - -/**************************************************************************** - * Name: stm32_epout_complete - * - * Description: - * This function is called when an OUT transfer complete interrupt is - * received. It completes the read request at the head of the endpoint's - * request queue. - * - ****************************************************************************/ - -static void stm32_epout_complete(struct stm32_usbdev_s *priv, - struct stm32_ep_s *privep) -{ - struct stm32_req_s *privreq; - - /* Since a transfer just completed, there must be a read request at the - * head of the endpoint request queue. - */ - - privreq = stm32_rqpeek(privep); - DEBUGASSERT(privreq); - - if (!privreq) - { - /* An OUT transfer completed, but no packet to receive the data. This - * should not happen. - */ - - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EPOUTQEMPTY), privep->epphy); - privep->active = false; - return; - } - - uinfo("EP%d: len=%zu xfrd=%zu\n", - privep->epphy, privreq->req.len, privreq->req.xfrd); - - /* Return the completed read request to the class driver and mark the state - * IDLE. - */ - - usbtrace(TRACE_COMPLETE(privep->epphy), privreq->req.xfrd); - stm32_req_complete(privep, OK); - privep->active = false; - - /* Now set up the next read request (if any) */ - - stm32_epout_request(priv, privep); -} - -/**************************************************************************** - * Name: stm32_ep0out_receive - * - * Description: - * This function is called from the RXFLVL interrupt handler when new - * incoming data is available in the endpoint's RxFIFO. This function will - * simply copy the incoming data into pending request's data buffer. - * - ****************************************************************************/ - -static inline void stm32_ep0out_receive(struct stm32_ep_s *privep, - int bcnt) -{ - struct stm32_usbdev_s *priv; - - /* Sanity Checking */ - - DEBUGASSERT(privep && privep->dev); - priv = (struct stm32_usbdev_s *)privep->dev; - - uinfo("EP0: bcnt=%d\n", bcnt); - usbtrace(TRACE_READ(EP0), bcnt); - - /* Verify that an OUT SETUP request as received before this data was - * received in the RxFIFO. - */ - - if (priv->ep0state == EP0STATE_SETUP_OUT) - { - /* Read the data into our special buffer for SETUP data */ - - int readlen = MIN(CONFIG_USBDEV_SETUP_MAXDATASIZE, bcnt); - stm32_rxfifo_read(privep, priv->ep0data, readlen); - - /* Do we have to discard any excess bytes? */ - - stm32_rxfifo_discard(privep, bcnt - readlen); - - /* Now we can process the setup command */ - - privep->active = false; - priv->ep0state = EP0STATE_SETUP_READY; - priv->ep0datlen = readlen; - - stm32_ep0out_setup(priv); - } - else - { - /* This is an error. We don't have any idea what to do with the EP0 - * data in this case. Just read and discard it so that the RxFIFO - * does not become constipated. - */ - - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_NOOUTSETUP), priv->ep0state); - stm32_rxfifo_discard(privep, bcnt); - privep->active = false; - } -} - -/**************************************************************************** - * Name: stm32_epout_receive - * - * Description: - * This function is called from the RXFLVL interrupt handler when new - * incoming data is available in the endpoint's RxFIFO. This function will - * simply copy the incoming data into pending request's data buffer. - * - ****************************************************************************/ - -static inline void stm32_epout_receive(struct stm32_ep_s *privep, - int bcnt) -{ - struct stm32_req_s *privreq; - uint8_t *dest; - int buflen; - int readlen; - - /* Get a reference to the request at the head of the endpoint's request - * queue. - */ - - privreq = stm32_rqpeek(privep); - if (!privreq) - { - /* Incoming data is available in the RxFIFO, but there is no read setup - * to receive the receive the data. This should not happen for data - * endpoints; those endpoints should have been NAKing any OUT data - * tokens. - * - * We should get here normally on OUT data phase following an OUT - * SETUP command. EP0 data will still receive data in this case and it - * should not be NAKing. - */ - - if (privep->epphy == 0) - { - stm32_ep0out_receive(privep, bcnt); - } - else - { - /* Otherwise, the data is lost. This really should not happen if - * NAKing is working as expected. - */ - - usbtrace( - TRACE_DEVERROR(STM32_TRACEERR_EPOUTQEMPTY), privep->epphy); - - /* Discard the data in the RxFIFO */ - - stm32_rxfifo_discard(privep, bcnt); - } - - privep->active = false; - return; - } - - uinfo("EP%d: len=%zu xfrd=%zu\n", - privep->epphy, privreq->req.len, privreq->req.xfrd); - usbtrace(TRACE_READ(privep->epphy), bcnt); - - /* Get the number of bytes to transfer from the RxFIFO */ - - buflen = privreq->req.len - privreq->req.xfrd; - DEBUGASSERT(buflen > 0 && buflen >= bcnt); - readlen = MIN(buflen, bcnt); - - /* Get the destination of the data transfer */ - - dest = privreq->req.buf + privreq->req.xfrd; - - /* Transfer the data from the RxFIFO to the request's data buffer */ - - stm32_rxfifo_read(privep, dest, readlen); - - /* If there were more bytes in the RxFIFO than could be held in the read - * request, then we will have to discard those. - */ - - stm32_rxfifo_discard(privep, bcnt - readlen); - - /* Update the number of bytes transferred */ - - privreq->req.xfrd += readlen; -} - -/**************************************************************************** - * Name: stm32_epout_request - * - * Description: - * This function is called when either (1) new read request is received, or - * (2) a pending receive request completes. If there is no read in - * pending, then this function will initiate the next OUT (read) operation. - * - ****************************************************************************/ - -static void stm32_epout_request(struct stm32_usbdev_s *priv, - struct stm32_ep_s *privep) -{ - struct stm32_req_s *privreq; - uint32_t regaddr; - uint32_t regval; - uint32_t xfrsize; - uint32_t pktcnt; - - /* Make sure that there is not already a pending request request. If there - * is, just return, leaving the newly received request in the request - * queue. - */ - - if (!privep->active) - { - /* Loop until a valid request is found (or the request queue is empty). - * The loop is only need to look at the request queue again is an - * invalid read request is encountered. - */ - - for (; ; ) - { - /* Get a reference to the request at the head of the endpoint's - * request queue - */ - - privreq = stm32_rqpeek(privep); - if (!privreq) - { - usbtrace( - TRACE_DEVERROR(STM32_TRACEERR_EPOUTQEMPTY), privep->epphy); - - /* There are no read requests to be setup. Configure the - * hardware to NAK any incoming packets. (This should already - * be the case. I think that the hardware will automatically - * NAK after a transfer is completed until SNAK is cleared). - */ - - regaddr = STM32_OTGHS_DOEPCTL(privep->epphy); - regval = stm32_getreg(regaddr); - regval |= OTGHS_DOEPCTL_SNAK; - stm32_putreg(regval, regaddr); - - /* This endpoint is no longer actively transferring */ - - privep->active = false; - return; - } - - uinfo("EP%d: len=%d\n", privep->epphy, privreq->req.len); - - /* Ignore any attempt to receive a zero length packet (this really - * should not happen. - */ - - if (privreq->req.len <= 0) - { - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EPOUTNULLPACKET), 0); - stm32_req_complete(privep, OK); - } - - /* Otherwise, we have a usable read request... - * break out of the loop - */ - - else - { - break; - } - } - - /* Setup the pending read into the request buffer. First calculate: - * - * pktcnt = the number of packets (of maxpacket bytes) required to - * perform the transfer. - * xfrsize = The total number of bytes required (in units of - * maxpacket bytes). - */ - - pktcnt = (privreq->req.len + (privep->ep.maxpacket - 1)) / - privep->ep.maxpacket; - xfrsize = pktcnt * privep->ep.maxpacket; - - /* Then setup the hardware to perform this transfer */ - - regaddr = STM32_OTGHS_DOEPTSIZ(privep->epphy); - regval = stm32_getreg(regaddr); - regval &= ~(OTGHS_DOEPTSIZ_XFRSIZ_MASK | OTGHS_DOEPTSIZ_PKTCNT_MASK); - regval |= (xfrsize << OTGHS_DOEPTSIZ_XFRSIZ_SHIFT); - regval |= (pktcnt << OTGHS_DOEPTSIZ_PKTCNT_SHIFT); - stm32_putreg(regval, regaddr); - - /* Then enable the transfer */ - - regaddr = STM32_OTGHS_DOEPCTL(privep->epphy); - regval = stm32_getreg(regaddr); - - /* When an isochronous transfer is enabled the Even/Odd frame bit must - * also be set appropriately. - */ - -#ifdef CONFIG_USBDEV_ISOCHRONOUS - if (privep->eptype == USB_EP_ATTR_XFER_ISOC) - { - if (privep->odd) - { - regval |= OTGHS_DOEPCTL_SODDFRM; - } - else - { - regval |= OTGHS_DOEPCTL_SEVNFRM; - } - } -#endif - - /* Clearing NAKing and enable the transfer. */ - - regval |= (OTGHS_DOEPCTL_CNAK | OTGHS_DOEPCTL_EPENA); - stm32_putreg(regval, regaddr); - - /* A transfer is now active on this endpoint */ - - privep->active = true; - - /* EP0 is a special case. We need to know when to switch back to - * normal SETUP processing. - */ - - if (privep->epphy == EP0) - { - priv->ep0state = EP0STATE_DATA_OUT; - } - } -} - -/**************************************************************************** - * Name: stm32_ep_flush - * - * Description: - * Flush any primed descriptors from this ep - * - ****************************************************************************/ - -static void stm32_ep_flush(struct stm32_ep_s *privep) -{ - if (privep->isin) - { - stm32_txfifo_flush(OTGHS_GRSTCTL_TXFNUM_D(privep->epphy)); - } - else - { - stm32_rxfifo_flush(); - } -} - -/**************************************************************************** - * Name: stm32_req_complete - * - * Description: - * Handle termination of the request at the head of the endpoint request - * queue. - * - ****************************************************************************/ - -static void stm32_req_complete(struct stm32_ep_s *privep, int16_t result) -{ - struct stm32_req_s *privreq; - - /* Remove the request at the head of the request list */ - - privreq = stm32_req_remfirst(privep); - DEBUGASSERT(privreq != NULL); - - /* If endpoint 0, temporarily reflect the state of protocol stalled - * in the callback. - */ - - bool stalled = privep->stalled; - if (privep->epphy == EP0) - { - privep->stalled = privep->dev->stalled; - } - - /* Save the result in the request structure */ - - privreq->req.result = result; - - /* Callback to the request completion handler */ - - privreq->req.callback(&privep->ep, &privreq->req); - - /* Restore the stalled indication */ - - privep->stalled = stalled; -} - -/**************************************************************************** - * Name: stm32_req_cancel - * - * Description: - * Cancel all pending requests for an endpoint - * - ****************************************************************************/ - -static void stm32_req_cancel(struct stm32_ep_s *privep, int16_t status) -{ - if (!stm32_rqempty(privep)) - { - stm32_ep_flush(privep); - } - - while (!stm32_rqempty(privep)) - { - usbtrace(TRACE_COMPLETE(privep->epphy), - (stm32_rqpeek(privep))->req.xfrd); - stm32_req_complete(privep, status); - } -} - -/**************************************************************************** - * Name: stm32_ep_findbyaddr - * - * Description: - * Find the physical endpoint structure corresponding to a logic endpoint - * address - * - ****************************************************************************/ - -static struct stm32_ep_s *stm32_ep_findbyaddr(struct stm32_usbdev_s *priv, - uint16_t eplog) -{ - struct stm32_ep_s *privep; - uint8_t epphy = USB_EPNO(eplog); - - if (epphy >= STM32_NENDPOINTS) - { - return NULL; - } - - /* Is this an IN or an OUT endpoint? */ - - if (USB_ISEPIN(eplog)) - { - privep = &priv->epin[epphy]; - } - else - { - privep = &priv->epout[epphy]; - } - - /* Return endpoint reference */ - - DEBUGASSERT(privep->epphy == epphy); - return privep; -} - -/**************************************************************************** - * Name: stm32_req_dispatch - * - * Description: - * Provide unhandled setup actions to the class driver. This is logically - * part of the USB interrupt handler. - * - ****************************************************************************/ - -static int stm32_req_dispatch(struct stm32_usbdev_s *priv, - const struct usb_ctrlreq_s *ctrl) -{ - int ret = -EIO; - - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_DISPATCH), 0); - if (priv->driver) - { - /* Forward to the control request to the class driver implementation */ - - ret = CLASS_SETUP(priv->driver, &priv->usbdev, ctrl, - priv->ep0data, priv->ep0datlen); - } - - if (ret < 0) - { - /* Stall on failure */ - - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_DISPATCHSTALL), 0); - priv->stalled = true; - } - - return ret; -} - -/**************************************************************************** - * Name: stm32_usbreset - * - * Description: - * Reset Usb engine - * - ****************************************************************************/ - -static void stm32_usbreset(struct stm32_usbdev_s *priv) -{ - struct stm32_ep_s *privep; - uint32_t regval; - int i; - - /* Clear the Remote Wake-up Signaling */ - - regval = stm32_getreg(STM32_OTGHS_DCTL); - regval &= ~OTGHS_DCTL_RWUSIG; - stm32_putreg(regval, STM32_OTGHS_DCTL); - - /* Flush the EP0 Tx FIFO */ - - stm32_txfifo_flush(OTGHS_GRSTCTL_TXFNUM_D(EP0)); - - /* Tell the class driver that we are disconnected. The class - * driver should then accept any new configurations. - */ - - if (priv->driver) - { - CLASS_DISCONNECT(priv->driver, &priv->usbdev); - } - - /* Mark all endpoints as available */ - - priv->epavail[0] = STM32_EP_AVAILABLE; - priv->epavail[1] = STM32_EP_AVAILABLE; - - /* Disable all end point interrupts */ - - for (i = 0; i < STM32_NENDPOINTS ; i++) - { - /* Disable endpoint interrupts */ - - stm32_putreg(0xff, STM32_OTGHS_DIEPINT(i)); - stm32_putreg(0xff, STM32_OTGHS_DOEPINT(i)); - - /* Return write requests to the class implementation */ - - privep = &priv->epin[i]; - stm32_req_cancel(privep, -ESHUTDOWN); - - /* Reset IN endpoint status */ - - privep->stalled = false; - - /* Return read requests to the class implementation */ - - privep = &priv->epout[i]; - stm32_req_cancel(privep, -ESHUTDOWN); - - /* Reset endpoint status */ - - privep->stalled = false; - } - - stm32_putreg(0xffffffff, STM32_OTGHS_DAINT); - - /* Mask all device endpoint interrupts except EP0 */ - - regval = (OTGHS_DAINT_IEP(EP0) | OTGHS_DAINT_OEP(EP0)); - stm32_putreg(regval, STM32_OTGHS_DAINTMSK); - - /* Unmask OUT interrupts */ - - regval = (OTGHS_DOEPMSK_XFRCM | OTGHS_DOEPMSK_STUPM | OTGHS_DOEPMSK_EPDM); - stm32_putreg(regval, STM32_OTGHS_DOEPMSK); - - /* Unmask IN interrupts */ - - regval = (OTGHS_DIEPMSK_XFRCM | OTGHS_DIEPMSK_EPDM | OTGHS_DIEPMSK_TOM); - stm32_putreg(regval, STM32_OTGHS_DIEPMSK); - - /* Reset device address to 0 */ - - stm32_setaddress(priv, 0); - priv->devstate = DEVSTATE_DEFAULT; - priv->usbdev.speed = USB_SPEED_FULL; - - /* Re-configure EP0 */ - - stm32_ep0_configure(priv); - - /* Setup EP0 to receive SETUP packets */ - - stm32_ep0out_ctrlsetup(priv); -} - -/**************************************************************************** - * Name: stm32_ep0out_testmode - * - * Description: - * Select test mode - * - ****************************************************************************/ - -static inline void stm32_ep0out_testmode(struct stm32_usbdev_s *priv, - uint16_t index) -{ - uint8_t testmode; - - testmode = index >> 8; - switch (testmode) - { - case 1: - priv->testmode = OTGHS_TESTMODE_J; - break; - - case 2: - priv->testmode = OTGHS_TESTMODE_K; - break; - - case 3: - priv->testmode = OTGHS_TESTMODE_SE0_NAK; - break; - - case 4: - priv->testmode = OTGHS_TESTMODE_PACKET; - break; - - case 5: - priv->testmode = OTGHS_TESTMODE_FORCE; - break; - - default: - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADTESTMODE), testmode); - priv->dotest = false; - priv->testmode = OTGHS_TESTMODE_DISABLED; - priv->stalled = true; - } - - priv->dotest = true; - stm32_ep0in_transmitzlp(priv); -} - -/**************************************************************************** - * Name: stm32_ep0out_stdrequest - * - * Description: - * Handle a standard request on EP0. Pick off the things of interest to - * the USB device controller driver; pass what is left to the class driver. - * - ****************************************************************************/ - -static inline void stm32_ep0out_stdrequest(struct stm32_usbdev_s *priv, - struct stm32_ctrlreq_s *ctrlreq) -{ - struct stm32_ep_s *privep; - - /* Handle standard request */ - - switch (ctrlreq->req) - { - case USB_REQ_GETSTATUS: - { - /* type: device-to-host; recipient = device, interface, endpoint - * value: 0 - * index: zero interface endpoint - * len: 2; data = status - */ - - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_GETSTATUS), 0); - if (!priv->addressed || - ctrlreq->len != 2 || - USB_REQ_ISOUT(ctrlreq->type) || - ctrlreq->value != 0) - { - priv->stalled = true; - } - else - { - switch (ctrlreq->type & USB_REQ_RECIPIENT_MASK) - { - case USB_REQ_RECIPIENT_ENDPOINT: - { - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPGETSTATUS), 0); - privep = stm32_ep_findbyaddr(priv, ctrlreq->index); - if (!privep) - { - usbtrace( - TRACE_DEVERROR(STM32_TRACEERR_BADEPGETSTATUS), 0); - priv->stalled = true; - } - else - { - if (privep->stalled) - { - priv->ep0data[0] = (1 << USB_FEATURE_ENDPOINTHALT); - } - else - { - priv->ep0data[0] = 0; /* Not stalled */ - } - - priv->ep0data[1] = 0; - stm32_ep0in_setupresponse(priv, priv->ep0data, 2); - } - } - break; - - case USB_REQ_RECIPIENT_DEVICE: - { - if (ctrlreq->index == 0) - { - usbtrace( - TRACE_INTDECODE(STM32_TRACEINTID_DEVGETSTATUS), 0); - - /* Features: Remote Wakeup and self-powered */ - - priv->ep0data[0] = (priv->selfpowered << - USB_FEATURE_SELFPOWERED); - priv->ep0data[0] |= (priv->wakeup << - USB_FEATURE_REMOTEWAKEUP); - priv->ep0data[1] = 0; - - stm32_ep0in_setupresponse(priv, priv->ep0data, 2); - } - else - { - usbtrace( - TRACE_DEVERROR(STM32_TRACEERR_BADDEVGETSTATUS), 0); - priv->stalled = true; - } - } - break; - - case USB_REQ_RECIPIENT_INTERFACE: - { - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_IFGETSTATUS), 0); - priv->ep0data[0] = 0; - priv->ep0data[1] = 0; - - stm32_ep0in_setupresponse(priv, priv->ep0data, 2); - } - break; - - default: - { - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADGETSTATUS), 0); - priv->stalled = true; - } - break; - } - } - } - break; - - case USB_REQ_CLEARFEATURE: - { - /* type: host-to-device; recipient = device, interface or endpoint - * value: feature selector - * index: zero interface endpoint; - * len: zero, data = none - */ - - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_CLEARFEATURE), 0); - if (priv->addressed != 0 && ctrlreq->len == 0) - { - uint8_t recipient = ctrlreq->type & USB_REQ_RECIPIENT_MASK; - if (recipient == USB_REQ_RECIPIENT_ENDPOINT && - ctrlreq->value == USB_FEATURE_ENDPOINTHALT && - (privep = stm32_ep_findbyaddr(priv, ctrlreq->index)) != NULL) - { - stm32_ep_clrstall(privep); - stm32_ep0in_transmitzlp(priv); - } - else if (recipient == USB_REQ_RECIPIENT_DEVICE && - ctrlreq->value == USB_FEATURE_REMOTEWAKEUP) - { - priv->wakeup = 0; - stm32_ep0in_transmitzlp(priv); - } - else - { - /* Actually, I think we could just stall here. */ - - stm32_req_dispatch(priv, &priv->ctrlreq); - } - } - else - { - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADCLEARFEATURE), 0); - priv->stalled = true; - } - } - break; - - case USB_REQ_SETFEATURE: - { - /* type: host-to-device; recipient = device, interface, endpoint - * value: feature selector - * index: zero interface endpoint; - * len: 0; data = none - */ - - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SETFEATURE), 0); - if (priv->addressed != 0 && ctrlreq->len == 0) - { - uint8_t recipient = ctrlreq->type & USB_REQ_RECIPIENT_MASK; - if (recipient == USB_REQ_RECIPIENT_ENDPOINT && - ctrlreq->value == USB_FEATURE_ENDPOINTHALT && - (privep = stm32_ep_findbyaddr(priv, ctrlreq->index)) != NULL) - { - stm32_ep_setstall(privep); - stm32_ep0in_transmitzlp(priv); - } - else if (recipient == USB_REQ_RECIPIENT_DEVICE && - ctrlreq->value == USB_FEATURE_REMOTEWAKEUP) - { - priv->wakeup = 1; - stm32_ep0in_transmitzlp(priv); - } - else if (recipient == USB_REQ_RECIPIENT_DEVICE && - ctrlreq->value == USB_FEATURE_TESTMODE && - ((ctrlreq->index & 0xff) == 0)) - { - stm32_ep0out_testmode(priv, ctrlreq->index); - } - else if (priv->configured) - { - /* Actually, I think we could just stall here. */ - - stm32_req_dispatch(priv, &priv->ctrlreq); - } - else - { - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADSETFEATURE), 0); - priv->stalled = true; - } - } - else - { - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADSETFEATURE), 0); - priv->stalled = true; - } - } - break; - - case USB_REQ_SETADDRESS: - { - /* type: host-to-device; recipient = device - * value: device address - * index: 0 - * len: 0; data = none - */ - - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SETADDRESS), - ctrlreq->value); - if ((ctrlreq->type & USB_REQ_RECIPIENT_MASK) == - USB_REQ_RECIPIENT_DEVICE && - ctrlreq->index == 0 && - ctrlreq->len == 0 && - ctrlreq->value < 128 && - priv->devstate != DEVSTATE_CONFIGURED) - { - /* Save the address. We cannot actually change to the next - * address until the completion of the status phase. - */ - - stm32_setaddress(priv, (uint16_t)priv->ctrlreq.value[0]); - stm32_ep0in_transmitzlp(priv); - } - else - { - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADSETADDRESS), 0); - priv->stalled = true; - } - } - break; - - case USB_REQ_GETDESCRIPTOR: - /* type: device-to-host; recipient = device - * value: descriptor type and index - * index: 0 or language ID; - * len: descriptor len; data = descriptor - */ - - case USB_REQ_SETDESCRIPTOR: - /* type: host-to-device; recipient = device - * value: descriptor type and index - * index: 0 or language ID; - * len: descriptor len; data = descriptor - */ - - { - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_GETSETDESC), 0); - if ((ctrlreq->type & USB_REQ_RECIPIENT_MASK) == - USB_REQ_RECIPIENT_DEVICE || - (ctrlreq->type & USB_REQ_RECIPIENT_MASK) == - USB_REQ_RECIPIENT_INTERFACE) - { - stm32_req_dispatch(priv, &priv->ctrlreq); - } - else - { - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADGETSETDESC), 0); - priv->stalled = true; - } - } - break; - - case USB_REQ_GETCONFIGURATION: - /* type: device-to-host; recipient = device - * value: 0; - * index: 0; - * len: 1; data = configuration value - */ - - { - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_GETCONFIG), 0); - if (priv->addressed && - (ctrlreq->type & USB_REQ_RECIPIENT_MASK) == - USB_REQ_RECIPIENT_DEVICE && - ctrlreq->value == 0 && - ctrlreq->index == 0 && - ctrlreq->len == 1) - { - stm32_req_dispatch(priv, &priv->ctrlreq); - } - else - { - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADGETCONFIG), 0); - priv->stalled = true; - } - } - break; - - case USB_REQ_SETCONFIGURATION: - /* type: host-to-device; recipient = device - * value: configuration value - * index: 0; - * len: 0; data = none - */ - - { - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SETCONFIG), 0); - if (priv->addressed && - (ctrlreq->type & USB_REQ_RECIPIENT_MASK) == - USB_REQ_RECIPIENT_DEVICE && - ctrlreq->index == 0 && - ctrlreq->len == 0) - { - /* Give the configuration to the class driver */ - - int ret = stm32_req_dispatch(priv, &priv->ctrlreq); - - /* If the class driver accepted the configuration, then mark the - * device state as configured (or not, depending on the - * configuration). - */ - - if (ret == OK) - { - uint8_t cfg = (uint8_t)ctrlreq->value; - if (cfg != 0) - { - priv->devstate = DEVSTATE_CONFIGURED; - priv->configured = true; - } - else - { - priv->devstate = DEVSTATE_ADDRESSED; - priv->configured = false; - } - } - } - else - { - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADSETCONFIG), 0); - priv->stalled = true; - } - } - break; - - case USB_REQ_GETINTERFACE: - /* type: device-to-host; recipient = interface - * value: 0 - * index: interface; - * len: 1; data = alt interface - */ - - case USB_REQ_SETINTERFACE: - /* type: host-to-device; recipient = interface - * value: alternate setting - * index: interface; - * len: 0; data = none - */ - - { - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_GETSETIF), 0); - stm32_req_dispatch(priv, &priv->ctrlreq); - } - break; - - case USB_REQ_SYNCHFRAME: - /* type: device-to-host; recipient = endpoint - * value: 0 - * index: endpoint; - * len: 2; data = frame number - */ - - { - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SYNCHFRAME), 0); - } - break; - - default: - { - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDCTRLREQ), 0); - priv->stalled = true; - } - break; - } -} - -/**************************************************************************** - * Name: stm32_ep0out_setup - * - * Description: - * USB Ctrl EP Setup Event. This is logically part of the USB interrupt - * handler. This event occurs when a setup packet is receive on EP0 OUT. - * - ****************************************************************************/ - -static inline void stm32_ep0out_setup(struct stm32_usbdev_s *priv) -{ - struct stm32_ctrlreq_s ctrlreq; - - /* Verify that a SETUP was received */ - - if (priv->ep0state != EP0STATE_SETUP_READY) - { - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EP0NOSETUP), priv->ep0state); - return; - } - - /* Terminate any pending requests */ - - stm32_req_cancel(&priv->epout[EP0], -EPROTO); - stm32_req_cancel(&priv->epin[EP0], -EPROTO); - - /* Assume NOT stalled */ - - priv->epout[EP0].stalled = false; - priv->epin[EP0].stalled = false; - priv->stalled = false; - - /* Starting to process a control request - update state */ - - priv->ep0state = EP0STATE_SETUP_PROCESS; - - /* And extract the little-endian 16-bit values to host order */ - - ctrlreq.type = priv->ctrlreq.type; - ctrlreq.req = priv->ctrlreq.req; - ctrlreq.value = GETUINT16(priv->ctrlreq.value); - ctrlreq.index = GETUINT16(priv->ctrlreq.index); - ctrlreq.len = GETUINT16(priv->ctrlreq.len); - - uinfo("type=%02x req=%02x value=%04x index=%04x len=%04x\n", - ctrlreq.type, ctrlreq.req, ctrlreq.value, ctrlreq.index, - ctrlreq.len); - - /* Check for a standard request */ - - if ((ctrlreq.type & USB_REQ_TYPE_MASK) != USB_REQ_TYPE_STANDARD) - { - /* Dispatch any non-standard requests */ - - stm32_req_dispatch(priv, &priv->ctrlreq); - } - else - { - /* Handle standard requests. */ - - stm32_ep0out_stdrequest(priv, &ctrlreq); - } - - /* Check if the setup processing resulted in a STALL */ - - if (priv->stalled) - { - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EP0SETUPSTALLED), - priv->ep0state); - stm32_ep0_stall(priv); - } - - /* Reset state/data associated with the SETUP request */ - - priv->ep0datlen = 0; -} - -/**************************************************************************** - * Name: stm32_epout - * - * Description: - * This is part of the OUT endpoint interrupt processing. This function - * handles the OUT event for a single endpoint. - * - ****************************************************************************/ - -static inline void stm32_epout(struct stm32_usbdev_s *priv, uint8_t epno) -{ - struct stm32_ep_s *privep; - - /* Endpoint 0 is a special case. */ - - if (epno == 0) - { - privep = &priv->epout[EP0]; - - /* In the EP0STATE_DATA_OUT state, we are receiving data into the - * request buffer. In that case, we must continue the request - * processing. - */ - - if (priv->ep0state == EP0STATE_DATA_OUT) - { - /* Continue processing data from the EP0 OUT request queue */ - - stm32_epout_complete(priv, privep); - - /* If we are not actively processing an OUT request, then we - * need to setup to receive the next control request. - */ - - if (!privep->active) - { - stm32_ep0out_ctrlsetup(priv); - priv->ep0state = EP0STATE_IDLE; - } - } - } - - /* For other endpoints, the only possibility is that we are continuing - * or finishing an OUT request. - */ - - else if (priv->devstate == DEVSTATE_CONFIGURED) - { - stm32_epout_complete(priv, &priv->epout[epno]); - } -} - -/**************************************************************************** - * Name: stm32_epout_interrupt - * - * Description: - * USB OUT endpoint interrupt handler. The core generates this interrupt - * when there is an interrupt is pending on one of the OUT endpoints of the - * core. The driver must read the OTGHS DAINT register to determine the - * exact number of the OUT endpoint on which the interrupt occurred, and - * then read the corresponding OTGHS DOEPINTx register to determine the - * exact cause of the interrupt. - * - ****************************************************************************/ - -static inline void stm32_epout_interrupt(struct stm32_usbdev_s *priv) -{ - uint32_t daint; - uint32_t regval; - uint32_t doepint; - int epno; - - /* Get the pending, enabled interrupts for the OUT endpoint from the - * endpoint interrupt status register. - */ - - regval = stm32_getreg(STM32_OTGHS_DAINT); - regval &= stm32_getreg(STM32_OTGHS_DAINTMSK); - daint = (regval & OTGHS_DAINT_OEP_MASK) >> OTGHS_DAINT_OEP_SHIFT; - - if (daint == 0) - { - /* We got an interrupt, but there is no unmasked endpoint that caused - * it ?! When this happens, the interrupt flag never gets cleared and - * we are stuck in infinite interrupt loop. - * - * This shouldn't happen if we are diligent about handling timing - * issues when masking endpoint interrupts. However, this workaround - * avoids infinite loop and allows operation to continue normally. It - * works by clearing each endpoint flags, masked or not. - */ - - regval = stm32_getreg(STM32_OTGHS_DAINT); - daint = (regval & OTGHS_DAINT_OEP_MASK) >> OTGHS_DAINT_OEP_SHIFT; - - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EPOUTUNEXPECTED), - (uint16_t)regval); - - epno = 0; - while (daint) - { - if ((daint & 1) != 0) - { - regval = stm32_getreg(STM32_OTGHS_DOEPINT(epno)); - uinfo("DOEPINT(%d) = %08" PRIx32 "\n", epno, regval); - stm32_putreg(0xff, STM32_OTGHS_DOEPINT(epno)); - } - - epno++; - daint >>= 1; - } - - return; - } - - /* Process each pending IN endpoint interrupt */ - - epno = 0; - while (daint) - { - /* Is an OUT interrupt pending for this endpoint? */ - - if ((daint & 1) != 0) - { - /* Yes.. get the OUT endpoint interrupt status */ - - doepint = stm32_getreg(STM32_OTGHS_DOEPINT(epno)); - doepint &= stm32_getreg(STM32_OTGHS_DOEPMSK); - - /* Transfer completed interrupt. This interrupt is triggered when - * stm32_rxinterrupt() removes the last packet data from the - * RxFIFO. In this case, core internally sets the NAK bit for this - * endpoint to prevent it from receiving any more packets. - */ - - if ((doepint & OTGHS_DOEPINT_XFRC) != 0) - { - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPOUT_XFRC), - (uint16_t)doepint); - - /* Clear the bit in DOEPINTn for this interrupt */ - - stm32_putreg(OTGHS_DOEPINT_XFRC, STM32_OTGHS_DOEPINT(epno)); - - /* Handle the RX transfer data ready event */ - - stm32_epout(priv, epno); - } - - /* Endpoint disabled interrupt (ignored because this interrupt is - * used in polled mode by the endpoint disable logic). - */ -#if 1 - /* REVISIT: */ - - if ((doepint & OTGHS_DOEPINT_EPDISD) != 0) - { - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPOUT_EPDISD), - (uint16_t)doepint); - - /* Clear the bit in DOEPINTn for this interrupt */ - - stm32_putreg(OTGHS_DOEPINT_EPDISD, STM32_OTGHS_DOEPINT(epno)); - } -#endif - - /* Setup Phase Done (control EPs) */ - - if ((doepint & OTGHS_DOEPINT_SETUP) != 0) - { - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPOUT_SETUP), - priv->ep0state); - - /* Handle the receipt of the IN SETUP packets now (OUT setup - * packet processing may be delayed until the accompanying - * OUT DATA is received) - */ - - if (priv->ep0state == EP0STATE_SETUP_READY) - { - stm32_ep0out_setup(priv); - } - - stm32_putreg(OTGHS_DOEPINT_SETUP, STM32_OTGHS_DOEPINT(epno)); - } - } - - epno++; - daint >>= 1; - } -} - -/**************************************************************************** - * Name: stm32_epin_runtestmode - * - * Description: - * Execute the test mode setup by the SET FEATURE request - * - ****************************************************************************/ - -static inline void stm32_epin_runtestmode(struct stm32_usbdev_s *priv) -{ - uint32_t regval = stm32_getreg(STM32_OTGHS_DCTL); - regval &= OTGHS_DCTL_TCTL_MASK; - regval |= (uint32_t)priv->testmode << OTGHS_DCTL_TCTL_SHIFT; - stm32_putreg(regval , STM32_OTGHS_DCTL); - - priv->dotest = 0; - priv->testmode = OTGHS_TESTMODE_DISABLED; -} - -/**************************************************************************** - * Name: stm32_epin - * - * Description: - * This is part of the IN endpoint interrupt processing. This function - * handles the IN event for a single endpoint. - * - ****************************************************************************/ - -static inline void stm32_epin(struct stm32_usbdev_s *priv, uint8_t epno) -{ - struct stm32_ep_s *privep = &priv->epin[epno]; - - /* Endpoint 0 is a special case. */ - - if (epno == 0) - { - /* In the EP0STATE_DATA_IN state, we are sending data from request - * buffer. In that case, we must continue the request processing. - */ - - if (priv->ep0state == EP0STATE_DATA_IN) - { - /* Continue processing data from the EP0 OUT request queue */ - - stm32_epin_request(priv, privep); - - /* If we are not actively processing an OUT request, then we - * need to setup to receive the next control request. - */ - - if (!privep->active) - { - stm32_ep0out_ctrlsetup(priv); - priv->ep0state = EP0STATE_IDLE; - } - } - - /* Test mode is another special case */ - - if (priv->dotest) - { - stm32_epin_runtestmode(priv); - } - } - - /* For other endpoints, the only possibility is that we are continuing - * or finishing an IN request. - */ - - else if (priv->devstate == DEVSTATE_CONFIGURED) - { - /* Continue processing data from the endpoint write request queue */ - - stm32_epin_request(priv, privep); - } -} - -/**************************************************************************** - * Name: stm32_epin_txfifoempty - * - * Description: - * TxFIFO empty interrupt handling - * - ****************************************************************************/ - -static inline void stm32_epin_txfifoempty(struct stm32_usbdev_s *priv, - int epno) -{ - struct stm32_ep_s *privep = &priv->epin[epno]; - - /* Continue processing the write request queue. This may mean sending - * more data from the existing request or terminating the current requests - * and (perhaps) starting the IN transfer from the next write request. - */ - - stm32_epin_request(priv, privep); -} - -/**************************************************************************** - * Name: stm32_epin_interrupt - * - * Description: - * USB IN endpoint interrupt handler. The core generates this interrupt - * when an interrupt is pending on one of the IN endpoints of the core. - * The driver must read the OTGHS DAINT register to determine the exact - * number of the IN endpoint on which the interrupt occurred, and then read - * the corresponding OTGHS DIEPINTx register to determine the exact cause - * of the interrupt. - * - ****************************************************************************/ - -static inline void stm32_epin_interrupt(struct stm32_usbdev_s *priv) -{ - uint32_t diepint; - uint32_t daint; - uint32_t mask; - uint32_t empty; - int epno; - - /* Get the pending, enabled interrupts for the IN endpoint from the - * endpoint interrupt status register. - */ - - daint = stm32_getreg(STM32_OTGHS_DAINT); - daint &= stm32_getreg(STM32_OTGHS_DAINTMSK); - daint &= OTGHS_DAINT_IEP_MASK; - - if (daint == 0) - { - /* We got an interrupt, but there is no unmasked endpoint that caused - * it ?! When this happens, the interrupt flag never gets cleared and - * we are stuck in infinite interrupt loop. - * - * This shouldn't happen if we are diligent about handling timing - * issues when masking endpoint interrupts. However, this workaround - * avoids infinite loop and allows operation to continue normally. It - * works by clearing each endpoint flags, masked or not. - */ - - daint = stm32_getreg(STM32_OTGHS_DAINT); - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EPINUNEXPECTED), - (uint16_t)daint); - - daint &= OTGHS_DAINT_IEP_MASK; - epno = 0; - - while (daint) - { - if ((daint & 1) != 0) - { - uinfo("DIEPINT(%d) = %08" PRIx32 "\n", - epno, stm32_getreg(STM32_OTGHS_DIEPINT(epno))); - stm32_putreg(0xff, STM32_OTGHS_DIEPINT(epno)); - } - - epno++; - daint >>= 1; - } - - return; - } - - /* Process each pending IN endpoint interrupt */ - - epno = 0; - while (daint) - { - /* Is an IN interrupt pending for this endpoint? */ - - if ((daint & 1) != 0) - { - /* Get IN interrupt mask register. Bits 0-6 correspond to enabled - * interrupts as will be found in the DIEPINT interrupt status - * register. - */ - - mask = stm32_getreg(STM32_OTGHS_DIEPMSK); - - /* Check if the TxFIFO not empty interrupt is enabled for this - * endpoint in the DIEPMSK register. Bits n corresponds to - * endpoint n in the register. That condition corresponds to - * bit 7 of the DIEPINT interrupt status register. There is - * no TXFE bit in the mask register, so we fake one here. - */ - - empty = stm32_getreg(STM32_OTGHS_DIEPEMPMSK); - if ((empty & OTGHS_DIEPEMPMSK(epno)) != 0) - { - mask |= OTGHS_DIEPINT_TXFE; - } - - /* Now, read the interrupt status and mask out all disabled - * interrupts. - */ - - diepint = stm32_getreg(STM32_OTGHS_DIEPINT(epno)) & mask; - - /* Decode and process the enabled, pending interrupts */ - - /* Transfer completed interrupt */ - - if ((diepint & OTGHS_DIEPINT_XFRC) != 0) - { - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPIN_XFRC), - (uint16_t)diepint); - - /* It is possible that logic may be waiting for a the - * TxFIFO to become empty. We disable the TxFIFO empty - * interrupt here; it will be re-enabled if there is still - * insufficient space in the TxFIFO. - */ - - empty &= ~OTGHS_DIEPEMPMSK(epno); - stm32_putreg(empty, STM32_OTGHS_DIEPEMPMSK); - stm32_putreg(OTGHS_DIEPINT_XFRC, STM32_OTGHS_DIEPINT(epno)); - - /* IN transfer complete */ - - stm32_epin(priv, epno); - } - - /* Timeout condition */ - - if ((diepint & OTGHS_DIEPINT_TOC) != 0) - { - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPIN_TOC), - (uint16_t)diepint); - stm32_putreg(OTGHS_DIEPINT_TOC, STM32_OTGHS_DIEPINT(epno)); - } - - /* IN token received when TxFIFO is empty. Applies to non-periodic - * IN endpoints only. This interrupt indicates that an IN token - * was received when the associated TxFIFO (periodic/non-periodic) - * was empty. This interrupt is asserted on the endpoint for which - * the IN token was received. - */ - - if ((diepint & OTGHS_DIEPINT_ITTXFE) != 0) - { - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPIN_ITTXFE), - (uint16_t)diepint); - stm32_epin_request(priv, &priv->epin[epno]); - stm32_putreg(OTGHS_DIEPINT_ITTXFE, STM32_OTGHS_DIEPINT(epno)); - } - - /* IN endpoint NAK effective (ignored as this used only in polled - * mode) - */ -#if 0 - if ((diepint & OTGHS_DIEPINT_INEPNE) != 0) - { - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPIN_INEPNE), - (uint16_t)diepint); - stm32_putreg(OTGHS_DIEPINT_INEPNE, STM32_OTGHS_DIEPINT(epno)); - } -#endif - - /* Endpoint disabled interrupt (ignored as this used only in polled - * mode) - */ -#if 0 - if ((diepint & OTGHS_DIEPINT_EPDISD) != 0) - { - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPIN_EPDISD), - (uint16_t)diepint); - stm32_putreg(OTGHS_DIEPINT_EPDISD, STM32_OTGHS_DIEPINT(epno)); - } -#endif - - /* Transmit FIFO empty */ - - if ((diepint & OTGHS_DIEPINT_TXFE) != 0) - { - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPIN_TXFE), - (uint16_t)diepint); - - /* If we were waiting for TxFIFO to become empty, the we might - * have both XFRC and TXFE interrupts pending. Since we do the - * same thing for both cases, ignore the TXFE if we have - * already processed the XFRC. - */ - - if ((diepint & OTGHS_DIEPINT_XFRC) == 0) - { - /* Mask further FIFO empty interrupts. This will be - * re-enabled whenever we need to wait for a FIFO event. - */ - - empty &= ~OTGHS_DIEPEMPMSK(epno); - stm32_putreg(empty, STM32_OTGHS_DIEPEMPMSK); - - /* Handle TxFIFO empty */ - - stm32_epin_txfifoempty(priv, epno); - } - - /* Clear the pending TxFIFO empty interrupt */ - - stm32_putreg(OTGHS_DIEPINT_TXFE, STM32_OTGHS_DIEPINT(epno)); - } - } - - epno++; - daint >>= 1; - } -} - -/**************************************************************************** - * Name: stm32_resumeinterrupt - * - * Description: - * Resume/remote wakeup detected interrupt - * - ****************************************************************************/ - -static inline void stm32_resumeinterrupt(struct stm32_usbdev_s *priv) -{ - uint32_t regval; - - /* Restart the PHY clock and un-gate USB core clock (HCLK) */ - -#ifdef CONFIG_USBDEV_LOWPOWER - regval = stm32_getreg(STM32_OTGHS_PCGCCTL); - regval &= ~(OTGHS_PCGCCTL_STPPCLK | OTGHS_PCGCCTL_GATEHCLK); - stm32_putreg(regval, STM32_OTGHS_PCGCCTL); -#endif - - /* Clear remote wake-up signaling */ - - regval = stm32_getreg(STM32_OTGHS_DCTL); - regval &= ~OTGHS_DCTL_RWUSIG; - stm32_putreg(regval, STM32_OTGHS_DCTL); - - /* Restore full power -- whatever that means for this particular board */ - - stm32_usbsuspend((struct usbdev_s *)priv, true); - - /* Notify the class driver of the resume event */ - - if (priv->driver) - { - CLASS_RESUME(priv->driver, &priv->usbdev); - } -} - -/**************************************************************************** - * Name: stm32_suspendinterrupt - * - * Description: - * USB suspend interrupt - * - ****************************************************************************/ - -static inline void stm32_suspendinterrupt(struct stm32_usbdev_s *priv) -{ -#ifdef CONFIG_USBDEV_LOWPOWER - uint32_t regval; -#endif - - /* Notify the class driver of the suspend event */ - - if (priv->driver) - { - CLASS_SUSPEND(priv->driver, &priv->usbdev); - } - -#ifdef CONFIG_USBDEV_LOWPOWER - /* OTGHS_DSTS_SUSPSTS is set as long as the suspend condition is detected - * on USB. Check if we are still have the suspend condition, that we are - * connected to the host, and that we have been configured. - */ - - regval = stm32_getreg(STM32_OTGHS_DSTS); - - if ((regval & OTGHS_DSTS_SUSPSTS) != 0 && devstate == DEVSTATE_CONFIGURED) - { - /* Switch off OTG HS clocking. Setting OTGHS_PCGCCTL_STPPCLK stops the - * PHY clock. - */ - - regval = stm32_getreg(STM32_OTGHS_PCGCCTL); - regval |= OTGHS_PCGCCTL_STPPCLK; - stm32_putreg(regval, STM32_OTGHS_PCGCCTL); - - /* Setting OTGHS_PCGCCTL_GATEHCLK gate HCLK to modules other than - * the AHB Slave and Master and wakeup logic. - */ - - regval |= OTGHS_PCGCCTL_GATEHCLK; - stm32_putreg(regval, STM32_OTGHS_PCGCCTL); - } -#endif - - /* Let the board-specific logic know that we have entered the suspend - * state - */ - - stm32_usbsuspend((struct usbdev_s *)priv, false); -} - -/**************************************************************************** - * Name: stm32_rxinterrupt - * - * Description: - * RxFIFO non-empty interrupt. This interrupt indicates that there is at - * least one packet pending to be read from the RxFIFO. - * - ****************************************************************************/ - -static inline void stm32_rxinterrupt(struct stm32_usbdev_s *priv) -{ - struct stm32_ep_s *privep; - uint32_t regval; - int bcnt; - int epphy; - - /* Disable the Rx status queue level interrupt */ - - regval = stm32_getreg(STM32_OTGHS_GINTMSK); - regval &= ~OTGHS_GINT_RXFLVL; - stm32_putreg(regval, STM32_OTGHS_GINTMSK); - - /* Get the status from the top of the FIFO */ - - regval = stm32_getreg(STM32_OTGHS_GRXSTSP); - - /* Decode status fields */ - - epphy = (regval & OTGHS_GRXSTSD_EPNUM_MASK) >> OTGHS_GRXSTSD_EPNUM_SHIFT; - - if (epphy < STM32_NENDPOINTS) - { - privep = &priv->epout[epphy]; - - /* Handle the RX event according to the packet status field */ - - switch (regval & OTGHS_GRXSTSD_PKTSTS_MASK) - { - /* Global OUT NAK. This indicate that the global OUT NAK bit has - * taken effect. - * - * PKTSTS = Global OUT NAK, BCNT = 0, - * EPNUM = Don't Care, DPID = Don't Care. - */ - - case OTGHS_GRXSTSD_PKTSTS_OUTNAK: - { - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_OUTNAK), 0); - } - break; - - /* OUT data packet received. - * - * PKTSTS = DataOUT, BCNT = size of the received data OUT packet, - * EPNUM = EPNUM on which the packet was received, - * DPID = Actual Data PID. - */ - - case OTGHS_GRXSTSD_PKTSTS_OUTRECVD: - { - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_OUTRECVD), epphy); - bcnt = (regval & OTGHS_GRXSTSD_BCNT_MASK) >> - OTGHS_GRXSTSD_BCNT_SHIFT; - if (bcnt > 0) - { - stm32_epout_receive(privep, bcnt); - } - } - break; - - /* OUT transfer completed. This indicates that an OUT data transfer - * for the specified OUT endpoint has completed. After this entry is - * popped from the receive FIFO, the core asserts a Transfer - * Completed interrupt on the specified OUT endpoint. - * - * PKTSTS = Data OUT Transfer Done, BCNT = 0, EPNUM = OUT EP Num on - * which the data transfer is complete, DPID = Don't Care. - */ - - case OTGHS_GRXSTSD_PKTSTS_OUTDONE: - { - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_OUTDONE), epphy); - } - break; - - /* SETUP transaction completed. This indicates that the Setup stage - * for the specified endpoint has completed and the Data stage has - * started. After this entry is popped from the receive FIFO, the - * core asserts a Setup interrupt on the specified control OUT - * endpoint (triggers an interrupt). - * - * PKTSTS = Setup Stage Done, BCNT = 0, EPNUM = Control EP Num, - * DPID = Don't Care. - */ - - case OTGHS_GRXSTSD_PKTSTS_SETUPDONE: - { - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SETUPDONE), epphy); - } - break; - - /* SETUP data packet received. This indicates that a SETUP packet - * for the specified endpoint is now available for reading from the - * receive FIFO. - * - * PKTSTS = SETUP, BCNT = 8, EPNUM = Control EP Num, DPID = D0. - */ - - case OTGHS_GRXSTSD_PKTSTS_SETUPRECVD: - { - uint16_t datlen; - - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SETUPRECVD), epphy); - - /* Read EP0 setup data. NOTE: If multiple SETUP packets are - * received, the last one overwrites the previous setup packets - * and only that last SETUP packet will be processed. - */ - - stm32_rxfifo_read(&priv->epout[EP0], - (uint8_t *)&priv->ctrlreq, - USB_SIZEOF_CTRLREQ); - - /* Was this an IN or an OUT SETUP packet. If it is an OUT SETUP, - * then we need to wait for the completion of the data phase to - * process the setup command. If it is an IN SETUP packet, then - * we must processing the command BEFORE we enter the DATA phase. - * - * If the data associated with the OUT SETUP packet is zero - * length, then, of course, we don't need to wait. - */ - - datlen = GETUINT16(priv->ctrlreq.len); - if (USB_REQ_ISOUT(priv->ctrlreq.type) && datlen > 0) - { - /* Clear NAKSTS so that we can receive the data */ - - regval = stm32_getreg(STM32_OTGHS_DOEPCTL0); - regval |= OTGHS_DOEPCTL0_CNAK; - stm32_putreg(regval, STM32_OTGHS_DOEPCTL0); - - /* Wait for the data phase. */ - - priv->ep0state = EP0STATE_SETUP_OUT; - } - else - { - /* We can process the setup data as soon as SETUP done word - * is popped of the RxFIFO. - */ - - priv->ep0state = EP0STATE_SETUP_READY; - } - } - break; - - default: - { - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), - (regval & OTGHS_GRXSTSD_PKTSTS_MASK) - >> OTGHS_GRXSTSD_PKTSTS_SHIFT); - } - break; - } - } - - /* Enable the Rx Status Queue Level interrupt */ - - regval = stm32_getreg(STM32_OTGHS_GINTMSK); - regval |= OTGHS_GINT_RXFLVL; - stm32_putreg(regval, STM32_OTGHS_GINTMSK); -} - -/**************************************************************************** - * Name: stm32_enuminterrupt - * - * Description: - * Enumeration done interrupt - * - ****************************************************************************/ - -static inline void stm32_enuminterrupt(struct stm32_usbdev_s *priv) -{ - uint32_t regval; - - /* Activate EP0 */ - - stm32_ep0in_activate(); - - /* Set USB turn-around time for the full speed device with internal PHY - * interface. - */ - - regval = stm32_getreg(STM32_OTGHS_GUSBCFG); - regval &= ~OTGHS_GUSBCFG_TRDT_MASK; - regval |= OTGHS_GUSBCFG_TRDT(5); - stm32_putreg(regval, STM32_OTGHS_GUSBCFG); -} - -/**************************************************************************** - * Name: stm32_isocininterrupt - * - * Description: - * Incomplete isochronous IN transfer interrupt. Assertion of the - * incomplete isochronous IN transfer interrupt indicates an incomplete - * isochronous IN transfer on at least one of the isochronous IN endpoints. - * - ****************************************************************************/ - -#ifdef CONFIG_USBDEV_ISOCHRONOUS -static inline void stm32_isocininterrupt(struct stm32_usbdev_s *priv) -{ - int i; - - /* The application must read the endpoint control register for all - * isochronous IN endpoints to detect endpoints with incomplete IN data - * transfers. - */ - - for (i = 0; i < STM32_NENDPOINTS; i++) - { - /* Is this an isochronous IN endpoint? */ - - privep = &priv->epin[i]; - if (privep->eptype != USB_EP_ATTR_XFER_ISOC) - { - /* No... keep looking */ - - continue; - } - - /* Is there an active read request on the isochronous OUT endpoint? */ - - if (!privep->active) - { - /* No.. the endpoint is not actively transmitting data */ - - continue; - } - - /* Check if this is the endpoint that had the incomplete transfer */ - - regaddr = STM32_OTGHS_DIEPCTL(privep->epphy); - doepctl = stm32_getreg(regaddr); - dsts = stm32_getreg(STM32_OTGHS_DSTS); - - /* EONUM = 0:even frame, 1:odd frame - * SOFFN = Frame number of the received SOF - */ - - eonum = ((doepctl & OTGHS_DIEPCTL_EONUM) != 0); - soffn = ((dsts & OTGHS_DSTS_SOFFN0) != 0); - - if (eonum != soffn) - { - /* Not this endpoint */ - - continue; - } - - /* For isochronous IN endpoints with incomplete transfers, - * the application must discard the data in the memory and - * disable the endpoint. - */ - - stm32_req_complete(privep, -EIO); -#warning "Will clear OTGHS_DIEPCTL_USBAEP too" - stm32_epin_disable(privep); - break; - } -} -#endif - -/**************************************************************************** - * Name: stm32_isocoutinterrupt - * - * Description: - * Incomplete periodic transfer interrupt - * - ****************************************************************************/ - -#ifdef CONFIG_USBDEV_ISOCHRONOUS -static inline void stm32_isocoutinterrupt(struct stm32_usbdev_s *priv) -{ - struct stm32_ep_s *privep; - struct stm32_req_s *privreq; - uint32_t regaddr; - uint32_t doepctl; - uint32_t dsts; - bool eonum; - bool soffn; - - /* When it receives an IISOOXFR interrupt, the application must read the - * control registers of all isochronous OUT endpoints to determine which - * endpoints had an incomplete transfer in the current microframe. An - * endpoint transfer is incomplete if both the following conditions are - * true: - * - * DOEPCTLx:EONUM = DSTS:SOFFN[0], and - * DOEPCTLx:EPENA = 1 - */ - - for (i = 0; i < STM32_NENDPOINTS; i++) - { - /* Is this an isochronous OUT endpoint? */ - - privep = &priv->epout[i]; - if (privep->eptype != USB_EP_ATTR_XFER_ISOC) - { - /* No... keep looking */ - - continue; - } - - /* Is there an active read request on the isochronous OUT endpoint? */ - - if (!privep->active) - { - /* No.. the endpoint is not actively transmitting data */ - - continue; - } - - /* Check if this is the endpoint that had the incomplete transfer */ - - regaddr = STM32_OTGHS_DOEPCTL(privep->epphy); - doepctl = stm32_getreg(regaddr); - dsts = stm32_getreg(STM32_OTGHS_DSTS); - - /* EONUM = 0:even frame, 1:odd frame - * SOFFN = Frame number of the received SOF - */ - - eonum = ((doepctl & OTGHS_DOEPCTL_EONUM) != 0); - soffn = ((dsts & OTGHS_DSTS_SOFFN0) != 0); - - if (eonum != soffn) - { - /* Not this endpoint */ - - continue; - } - - /* For isochronous OUT endpoints with incomplete transfers, - * the application must discard the data in the memory and - * disable the endpoint. - */ - - stm32_req_complete(privep, -EIO); -#warning "Will clear OTGHS_DOEPCTL_USBAEP too" - stm32_epout_disable(privep); - break; - } -} -#endif - -/**************************************************************************** - * Name: stm32_sessioninterrupt - * - * Description: - * Session request/new session detected interrupt - * - ****************************************************************************/ - -#ifdef CONFIG_USBDEV_VBUSSENSING -static inline void stm32_sessioninterrupt(struct stm32_usbdev_s *priv) -{ -#warning "Missing logic" -} -#endif - -/**************************************************************************** - * Name: stm32_otginterrupt - * - * Description: - * OTG interrupt - * - ****************************************************************************/ - -#ifdef CONFIG_USBDEV_VBUSSENSING -static inline void stm32_otginterrupt(struct stm32_usbdev_s *priv) -{ - uint32_t regval; - - /* Check for session end detected */ - - regval = stm32_getreg(STM32_OTGHS_GOTGINT); - if ((regval & OTGHS_GOTGINT_SEDET) != 0) - { -#warning "Missing logic" - } - - /* Clear OTG interrupt */ - - stm32_putreg(retval, STM32_OTGHS_GOTGINT); -} -#endif - -/**************************************************************************** - * Name: stm32_usbinterrupt - * - * Description: - * USB interrupt handler - * - ****************************************************************************/ - -static int stm32_usbinterrupt(int irq, void *context, void *arg) -{ - /* At present, there is only a single OTG HS device support. Hence it is - * pre-allocated as g_otghsdev. However, in most code, the private data - * structure will be referenced using the 'priv' pointer (rather than the - * global data) in order to simplify any future support for multiple - * devices. - */ - - struct stm32_usbdev_s *priv = &g_otghsdev; - uint32_t regval; - - usbtrace(TRACE_INTENTRY(STM32_TRACEINTID_USB), 0); - - /* Assure that we are in device mode */ - - DEBUGASSERT((stm32_getreg(STM32_OTGHS_GINTSTS) & OTGHS_GINTSTS_CMOD) - == OTGHS_GINTSTS_DEVMODE); - - /* Get the state of all enabled interrupts. We will do this repeatedly - * some interrupts (like RXFLVL) will generate additional interrupting - * events. - */ - - for (; ; ) - { - /* Get the set of pending, un-masked interrupts */ - - regval = stm32_getreg(STM32_OTGHS_GINTSTS); - regval &= stm32_getreg(STM32_OTGHS_GINTMSK); - - /* Break out of the loop when there are no further pending (and - * unmasked) interrupts to be processes. - */ - - if (regval == 0) - { - break; - } - - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_INTPENDING), - (uint16_t)regval); - - /* OUT endpoint interrupt. The core sets this bit to indicate that an - * interrupt is pending on one of the OUT endpoints of the core. - */ - - if ((regval & OTGHS_GINT_OEP) != 0) - { - usbtrace( - TRACE_INTDECODE(STM32_TRACEINTID_EPOUT), (uint16_t)regval); - stm32_epout_interrupt(priv); - stm32_putreg(OTGHS_GINT_OEP, STM32_OTGHS_GINTSTS); - } - - /* IN endpoint interrupt. The core sets this bit to indicate that - * an interrupt is pending on one of the IN endpoints of the core. - */ - - if ((regval & OTGHS_GINT_IEP) != 0) - { - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPIN), (uint16_t)regval); - stm32_epin_interrupt(priv); - stm32_putreg(OTGHS_GINT_IEP, STM32_OTGHS_GINTSTS); - } - - /* Host/device mode mismatch error interrupt */ - -#ifdef CONFIG_DEBUG_USB - if ((regval & OTGHS_GINT_MMIS) != 0) - { - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_MISMATCH), - (uint16_t)regval); - stm32_putreg(OTGHS_GINT_MMIS, STM32_OTGHS_GINTSTS); - } -#endif - - /* Resume/remote wakeup detected interrupt */ - - if ((regval & OTGHS_GINT_WKUP) != 0) - { - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_WAKEUP), - (uint16_t)regval); - stm32_resumeinterrupt(priv); - stm32_putreg(OTGHS_GINT_WKUP, STM32_OTGHS_GINTSTS); - } - - /* USB suspend interrupt */ - - if ((regval & OTGHS_GINT_USBSUSP) != 0) - { - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SUSPEND), - (uint16_t)regval); - stm32_suspendinterrupt(priv); - stm32_putreg(OTGHS_GINT_USBSUSP, STM32_OTGHS_GINTSTS); - } - - /* Start of frame interrupt */ - -#ifdef CONFIG_USBDEV_SOFINTERRUPT - if ((regval & OTGHS_GINT_SOF) != 0) - { - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SOF), (uint16_t)regval); - stm32_putreg(OTGHS_GINT_SOF, STM32_OTGHS_GINTSTS); - } -#endif - - /* RxFIFO non-empty interrupt. Indicates that there is at least one - * packet pending to be read from the RxFIFO. - */ - - if ((regval & OTGHS_GINT_RXFLVL) != 0) - { - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_RXFIFO), - (uint16_t)regval); - stm32_rxinterrupt(priv); - stm32_putreg(OTGHS_GINT_RXFLVL, STM32_OTGHS_GINTSTS); - } - - /* USB reset interrupt */ - - if ((regval & OTGHS_GINT_USBRST) != 0) - { - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_DEVRESET), - (uint16_t)regval); - - /* Perform the device reset */ - - stm32_usbreset(priv); - usbtrace(TRACE_INTEXIT(STM32_TRACEINTID_USB), 0); - stm32_putreg(OTGHS_GINT_USBRST, STM32_OTGHS_GINTSTS); - return OK; - } - - /* Enumeration done interrupt */ - - if ((regval & OTGHS_GINT_ENUMDNE) != 0) - { - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_ENUMDNE), - (uint16_t)regval); - stm32_enuminterrupt(priv); - stm32_putreg(OTGHS_GINT_ENUMDNE, STM32_OTGHS_GINTSTS); - } - - /* Incomplete isochronous IN transfer interrupt. When the core finds - * non-empty any of the isochronous IN endpoint FIFOs scheduled for - * the current frame non-empty, the core generates an IISOIXFR - * interrupt. - */ - -#ifdef CONFIG_USBDEV_ISOCHRONOUS - if ((regval & OTGHS_GINT_IISOIXFR) != 0) - { - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_IISOIXFR), - (uint16_t)regval); - stm32_isocininterrupt(priv); - stm32_putreg(OTGHS_GINT_IISOIXFR, STM32_OTGHS_GINTSTS); - } - - /* Incomplete isochronous OUT transfer. For isochronous OUT - * endpoints, the XFRC interrupt may not always be asserted. If the - * core drops isochronous OUT data packets, the application could fail - * to detect the XFRC interrupt. The incomplete Isochronous OUT data - * interrupt indicates that an XFRC interrupt was not asserted on at - * least one of the isochronous OUT endpoints. At this point, the - * endpoint with the incomplete transfer remains enabled, but no active - * transfers remain in progress on this endpoint on the USB. - */ - - if ((regval & OTGHS_GINT_IISOOXFR) != 0) - { - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_IISOOXFR), - (uint16_t)regval); - stm32_isocoutinterrupt(priv); - stm32_putreg(OTGHS_GINT_IISOOXFR, STM32_OTGHS_GINTSTS); - } -#endif - - /* Session request/new session detected interrupt */ - -#ifdef CONFIG_USBDEV_VBUSSENSING - if ((regval & OTGHS_GINT_SRQ) != 0) - { - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SRQ), (uint16_t)regval); - stm32_sessioninterrupt(priv); - stm32_putreg(OTGHS_GINT_SRQ, STM32_OTGHS_GINTSTS); - } - - /* OTG interrupt */ - - if ((regval & OTGHS_GINT_OTG) != 0) - { - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_OTG), (uint16_t)regval); - stm32_otginterrupt(priv); - stm32_putreg(OTGHS_GINT_OTG, STM32_OTGHS_GINTSTS); - } -#endif - } - - usbtrace(TRACE_INTEXIT(STM32_TRACEINTID_USB), 0); - return OK; -} - -/**************************************************************************** - * Endpoint operations - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_enablegonak - * - * Description: - * Enable global OUT NAK mode - * - ****************************************************************************/ - -static void stm32_enablegonak(struct stm32_ep_s *privep) -{ - uint32_t regval; - - /* First, make sure that there is no GNOAKEFF interrupt pending. */ - -#if 0 - stm32_putreg(OTGHS_GINT_GONAKEFF, STM32_OTGHS_GINTSTS); -#endif - - /* Enable Global OUT NAK mode in the core. */ - - regval = stm32_getreg(STM32_OTGHS_DCTL); - regval |= OTGHS_DCTL_SGONAK; - stm32_putreg(regval, STM32_OTGHS_DCTL); - -#if 0 - /* Wait for the GONAKEFF interrupt that indicates that the OUT NAK - * mode is in effect. When the interrupt handler pops the OUTNAK word - * from the RxFIFO, the core sets the GONAKEFF interrupt. - */ - - while ((stm32_getreg(STM32_OTGHS_GINTSTS) & OTGHS_GINT_GONAKEFF) == 0); - stm32_putreg(OTGHS_GINT_GONAKEFF, STM32_OTGHS_GINTSTS); - -#else - /* Since we are in the interrupt handler, we cannot wait inline for the - * GONAKEFF because it cannot occur until service the RXFLVL global - * interrupt and pop the OUTNAK word from the RxFIFO. - * - * Perhaps it is sufficient to wait for Global OUT NAK status to be - * reported in OTGHS DCTL register? - */ - - while ((stm32_getreg(STM32_OTGHS_DCTL) & OTGHS_DCTL_GONSTS) == 0); -#endif -} - -/**************************************************************************** - * Name: stm32_disablegonak - * - * Description: - * Disable global OUT NAK mode - * - ****************************************************************************/ - -static void stm32_disablegonak(struct stm32_ep_s *privep) -{ - uint32_t regval; - - /* Set the "Clear the Global OUT NAK bit" to disable global OUT NAK mode */ - - regval = stm32_getreg(STM32_OTGHS_DCTL); - regval |= OTGHS_DCTL_CGONAK; - stm32_putreg(regval, STM32_OTGHS_DCTL); -} - -/**************************************************************************** - * Name: stm32_epout_configure - * - * Description: - * Configure an OUT endpoint, making it usable - * - * Input Parameters: - * privep - a pointer to an internal endpoint structure - * eptype - The type of the endpoint - * maxpacket - The max packet size of the endpoint - * - ****************************************************************************/ - -static int stm32_epout_configure(struct stm32_ep_s *privep, - uint8_t eptype, uint16_t maxpacket) -{ - uint32_t mpsiz; - uint32_t regaddr; - uint32_t regval; - - usbtrace(TRACE_EPCONFIGURE, privep->epphy); - - /* For EP0, the packet size is encoded */ - - if (privep->epphy == EP0) - { - DEBUGASSERT(eptype == USB_EP_ATTR_XFER_CONTROL); - - /* Map the size in bytes to the encoded value in the register */ - - switch (maxpacket) - { - case 8: - mpsiz = OTGHS_DOEPCTL0_MPSIZ_8; - break; - - case 16: - mpsiz = OTGHS_DOEPCTL0_MPSIZ_16; - break; - - case 32: - mpsiz = OTGHS_DOEPCTL0_MPSIZ_32; - break; - - case 64: - mpsiz = OTGHS_DOEPCTL0_MPSIZ_64; - break; - - default: - uerr("ERROR: Unsupported maxpacket: %d\n", maxpacket); - return -EINVAL; - } - } - - /* For other endpoints, the packet size is in bytes */ - - else - { - mpsiz = (maxpacket << OTGHS_DOEPCTL_MPSIZ_SHIFT); - } - - /* If the endpoint is already active don't change the endpoint control - * register. - */ - - regaddr = STM32_OTGHS_DOEPCTL(privep->epphy); - regval = stm32_getreg(regaddr); - if ((regval & OTGHS_DOEPCTL_USBAEP) == 0) - { - if (regval & OTGHS_DOEPCTL_NAKSTS) - { - regval |= OTGHS_DOEPCTL_CNAK; - } - - regval &= ~(OTGHS_DOEPCTL_MPSIZ_MASK | OTGHS_DOEPCTL_EPTYP_MASK); - regval |= mpsiz; - regval |= (eptype << OTGHS_DOEPCTL_EPTYP_SHIFT); - regval |= (OTGHS_DOEPCTL_SD0PID | OTGHS_DOEPCTL_USBAEP); - stm32_putreg(regval, regaddr); - - /* Save the endpoint configuration */ - - privep->ep.maxpacket = maxpacket; - privep->eptype = eptype; - privep->stalled = false; - } - - /* Enable the interrupt for this endpoint */ - - regval = stm32_getreg(STM32_OTGHS_DAINTMSK); - regval |= OTGHS_DAINT_OEP(privep->epphy); - stm32_putreg(regval, STM32_OTGHS_DAINTMSK); - return OK; -} - -/**************************************************************************** - * Name: stm32_epin_configure - * - * Description: - * Configure an IN endpoint, making it usable - * - * Input Parameters: - * privep - a pointer to an internal endpoint structure - * eptype - The type of the endpoint - * maxpacket - The max packet size of the endpoint - * - ****************************************************************************/ - -static int stm32_epin_configure(struct stm32_ep_s *privep, - uint8_t eptype, uint16_t maxpacket) -{ - uint32_t mpsiz; - uint32_t regaddr; - uint32_t regval; - - usbtrace(TRACE_EPCONFIGURE, privep->epphy); - - /* For EP0, the packet size is encoded */ - - if (privep->epphy == EP0) - { - DEBUGASSERT(eptype == USB_EP_ATTR_XFER_CONTROL); - - /* Map the size in bytes to the encoded value in the register */ - - switch (maxpacket) - { - case 8: - mpsiz = OTGHS_DIEPCTL0_MPSIZ_8; - break; - - case 16: - mpsiz = OTGHS_DIEPCTL0_MPSIZ_16; - break; - - case 32: - mpsiz = OTGHS_DIEPCTL0_MPSIZ_32; - break; - - case 64: - mpsiz = OTGHS_DIEPCTL0_MPSIZ_64; - break; - - default: - uerr("ERROR: Unsupported maxpacket: %d\n", maxpacket); - return -EINVAL; - } - } - - /* For other endpoints, the packet size is in bytes */ - - else - { - mpsiz = (maxpacket << OTGHS_DIEPCTL_MPSIZ_SHIFT); - } - - /* If the endpoint is already active don't change the endpoint control - * register. - */ - - regaddr = STM32_OTGHS_DIEPCTL(privep->epphy); - regval = stm32_getreg(regaddr); - if ((regval & OTGHS_DIEPCTL_USBAEP) == 0) - { - if (regval & OTGHS_DIEPCTL_NAKSTS) - { - regval |= OTGHS_DIEPCTL_CNAK; - } - - regval &= ~(OTGHS_DIEPCTL_MPSIZ_MASK | - OTGHS_DIEPCTL_EPTYP_MASK | - OTGHS_DIEPCTL_TXFNUM_MASK); - regval |= mpsiz; - regval |= (eptype << OTGHS_DIEPCTL_EPTYP_SHIFT); - regval |= (privep->epphy << OTGHS_DIEPCTL_TXFNUM_SHIFT); - regval |= (OTGHS_DIEPCTL_SD0PID | OTGHS_DIEPCTL_USBAEP); - stm32_putreg(regval, regaddr); - - /* Save the endpoint configuration */ - - privep->ep.maxpacket = maxpacket; - privep->eptype = eptype; - privep->stalled = false; - } - - /* Enable the interrupt for this endpoint */ - - regval = stm32_getreg(STM32_OTGHS_DAINTMSK); - regval |= OTGHS_DAINT_IEP(privep->epphy); - stm32_putreg(regval, STM32_OTGHS_DAINTMSK); - - return OK; -} - -/**************************************************************************** - * Name: stm32_ep_configure - * - * Description: - * Configure endpoint, making it usable - * - * Input Parameters: - * ep - the struct usbdev_ep_s instance obtained from allocep() - * desc - A struct usb_epdesc_s instance describing the endpoint - * last - true if this this last endpoint to be configured. Some hardware - * needs to take special action when all of the endpoints have been - * configured. - * - ****************************************************************************/ - -static int stm32_ep_configure(struct usbdev_ep_s *ep, - const struct usb_epdesc_s *desc, - bool last) -{ - struct stm32_ep_s *privep = (struct stm32_ep_s *)ep; - uint16_t maxpacket; - uint8_t eptype; - int ret; - - usbtrace(TRACE_EPCONFIGURE, privep->epphy); - DEBUGASSERT(desc->addr == ep->eplog); - - /* Initialize EP capabilities */ - - maxpacket = GETUINT16(desc->mxpacketsize); - eptype = desc->attr & USB_EP_ATTR_XFERTYPE_MASK; - - /* Setup Endpoint Control Register */ - - if (privep->isin) - { - ret = stm32_epin_configure(privep, eptype, maxpacket); - } - else - { - ret = stm32_epout_configure(privep, eptype, maxpacket); - } - - return ret; -} - -/**************************************************************************** - * Name: stm32_ep0_configure - * - * Description: - * Reset Usb engine - * - ****************************************************************************/ - -static void stm32_ep0_configure(struct stm32_usbdev_s *priv) -{ - /* Enable EP0 IN and OUT */ - - stm32_epin_configure(&priv->epin[EP0], USB_EP_ATTR_XFER_CONTROL, - CONFIG_USBDEV_EP0_MAXSIZE); - stm32_epout_configure(&priv->epout[EP0], USB_EP_ATTR_XFER_CONTROL, - CONFIG_USBDEV_EP0_MAXSIZE); -} - -/**************************************************************************** - * Name: stm32_epout_disable - * - * Description: - * Disable an OUT endpoint will no longer be used - * - ****************************************************************************/ - -static void stm32_epout_disable(struct stm32_ep_s *privep) -{ - uint32_t regaddr; - uint32_t regval; - irqstate_t flags; - - usbtrace(TRACE_EPDISABLE, privep->epphy); - - /* Is this an IN or an OUT endpoint */ - - /* Before disabling any OUT endpoint, the application must enable - * Global OUT NAK mode in the core. - */ - - flags = enter_critical_section(); - stm32_enablegonak(privep); - - /* Disable the required OUT endpoint by setting the EPDIS and SNAK bits - * int DOECPTL register. - */ - - regaddr = STM32_OTGHS_DOEPCTL(privep->epphy); - regval = stm32_getreg(regaddr); - regval &= ~OTGHS_DOEPCTL_USBAEP; - regval |= (OTGHS_DOEPCTL_EPDIS | OTGHS_DOEPCTL_SNAK); - stm32_putreg(regval, regaddr); - - /* Wait for the EPDISD interrupt which indicates that the OUT - * endpoint is completely disabled. - */ - -#if 0 /* Doesn't happen */ - regaddr = STM32_OTGHS_DOEPINT(privep->epphy); - while ((stm32_getreg(regaddr) & OTGHS_DOEPINT_EPDISD) == 0); -#else - /* REVISIT: */ - - up_udelay(10); -#endif - - /* Clear the EPDISD interrupt indication */ - - stm32_putreg(OTGHS_DOEPINT_EPDISD, STM32_OTGHS_DOEPINT(privep->epphy)); - - /* Then disable the Global OUT NAK mode to continue receiving data - * from other non-disabled OUT endpoints. - */ - - stm32_disablegonak(privep); - - /* Disable endpoint interrupts */ - - regval = stm32_getreg(STM32_OTGHS_DAINTMSK); - regval &= ~OTGHS_DAINT_OEP(privep->epphy); - stm32_putreg(regval, STM32_OTGHS_DAINTMSK); - - /* Cancel any queued read requests */ - - stm32_req_cancel(privep, -ESHUTDOWN); - - leave_critical_section(flags); -} - -/**************************************************************************** - * Name: stm32_epin_disable - * - * Description: - * Disable an IN endpoint when it will no longer be used - * - ****************************************************************************/ - -static void stm32_epin_disable(struct stm32_ep_s *privep) -{ - uint32_t regaddr; - uint32_t regval; - irqstate_t flags; - - usbtrace(TRACE_EPDISABLE, privep->epphy); - - /* After USB reset, the endpoint will already be deactivated by the - * hardware. Trying to disable again will just hang in the wait. - */ - - regaddr = STM32_OTGHS_DIEPCTL(privep->epphy); - regval = stm32_getreg(regaddr); - if ((regval & OTGHS_DIEPCTL_USBAEP) == 0) - { - return; - } - - /* This INEPNE wait logic is suggested by reference manual, but seems - * to get stuck to infinite loop. - */ - -#if 0 - /* Make sure that there is no pending IPEPNE interrupt (because we are - * to poll this bit below). - */ - - stm32_putreg(OTGHS_DIEPINT_INEPNE, STM32_OTGHS_DIEPINT(privep->epphy)); - - /* Set the endpoint in NAK mode */ - - regaddr = STM32_OTGHS_DIEPCTL(privep->epphy); - regval = stm32_getreg(regaddr); - regval &= ~OTGHS_DIEPCTL_USBAEP; - regval |= (OTGHS_DIEPCTL_EPDIS | OTGHS_DIEPCTL_SNAK); - stm32_putreg(regval, regaddr); - - /* Wait for the INEPNE interrupt that indicates that we are now in NAK mode - */ - - regaddr = STM32_OTGHS_DIEPINT(privep->epphy); - while ((stm32_getreg(regaddr) & OTGHS_DIEPINT_INEPNE) == 0); - - /* Clear the INEPNE interrupt indication */ - - stm32_putreg(OTGHS_DIEPINT_INEPNE, regaddr); -#endif - - /* Deactivate and disable the endpoint by setting the EPDIS and SNAK bits - * the DIEPCTLx register. - */ - - flags = enter_critical_section(); - regaddr = STM32_OTGHS_DIEPCTL(privep->epphy); - regval = stm32_getreg(regaddr); - regval &= ~OTGHS_DIEPCTL_USBAEP; - regval |= (OTGHS_DIEPCTL_EPDIS | OTGHS_DIEPCTL_SNAK); - stm32_putreg(regval, regaddr); - - /* Wait for the EPDISD interrupt which indicates that the IN - * endpoint is completely disabled. - */ - - regaddr = STM32_OTGHS_DIEPINT(privep->epphy); - while ((stm32_getreg(regaddr) & OTGHS_DIEPINT_EPDISD) == 0); - - /* Clear the EPDISD interrupt indication */ - - stm32_putreg(OTGHS_DIEPINT_EPDISD, stm32_getreg(regaddr)); - - /* Flush any data remaining in the TxFIFO */ - - stm32_txfifo_flush(OTGHS_GRSTCTL_TXFNUM_D(privep->epphy)); - - /* Disable endpoint interrupts */ - - regval = stm32_getreg(STM32_OTGHS_DAINTMSK); - regval &= ~OTGHS_DAINT_IEP(privep->epphy); - stm32_putreg(regval, STM32_OTGHS_DAINTMSK); - - /* Cancel any queued write requests */ - - stm32_req_cancel(privep, -ESHUTDOWN); - leave_critical_section(flags); -} - -/**************************************************************************** - * Name: stm32_ep_disable - * - * Description: - * The endpoint will no longer be used - * - ****************************************************************************/ - -static int stm32_ep_disable(struct usbdev_ep_s *ep) -{ - struct stm32_ep_s *privep = (struct stm32_ep_s *)ep; - -#ifdef CONFIG_DEBUG_FEATURES - if (!ep) - { - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); - return -EINVAL; - } -#endif - - usbtrace(TRACE_EPDISABLE, privep->epphy); - - /* Is this an IN or an OUT endpoint */ - - if (privep->isin) - { - /* Disable the IN endpoint */ - - stm32_epin_disable(privep); - } - else - { - /* Disable the OUT endpoint */ - - stm32_epout_disable(privep); - } - - return OK; -} - -/**************************************************************************** - * Name: stm32_ep_allocreq - * - * Description: - * Allocate an I/O request - * - ****************************************************************************/ - -static struct usbdev_req_s *stm32_ep_allocreq(struct usbdev_ep_s *ep) -{ - struct stm32_req_s *privreq; - -#ifdef CONFIG_DEBUG_FEATURES - if (!ep) - { - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); - return NULL; - } -#endif - - usbtrace(TRACE_EPALLOCREQ, ((struct stm32_ep_s *)ep)->epphy); - - privreq = kmm_malloc(sizeof(struct stm32_req_s)); - if (!privreq) - { - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_ALLOCFAIL), 0); - return NULL; - } - - memset(privreq, 0, sizeof(struct stm32_req_s)); - return &privreq->req; -} - -/**************************************************************************** - * Name: stm32_ep_freereq - * - * Description: - * Free an I/O request - * - ****************************************************************************/ - -static void stm32_ep_freereq(struct usbdev_ep_s *ep, - struct usbdev_req_s *req) -{ - struct stm32_req_s *privreq = (struct stm32_req_s *)req; - -#ifdef CONFIG_DEBUG_FEATURES - if (!ep || !req) - { - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); - return; - } -#endif - - usbtrace(TRACE_EPFREEREQ, ((struct stm32_ep_s *)ep)->epphy); - kmm_free(privreq); -} - -/**************************************************************************** - * Name: stm32_ep_allocbuffer - * - * Description: - * Allocate an I/O buffer - * - ****************************************************************************/ - -#ifdef CONFIG_USBDEV_DMA -static void *stm32_ep_allocbuffer(struct usbdev_ep_s *ep, uint16_t bytes) -{ - usbtrace(TRACE_EPALLOCBUFFER, ((struct stm32_ep_s *)ep)->epphy); - -#ifdef CONFIG_USBDEV_DMAMEMORY - return usbdev_dma_alloc(bytes); -#else - return kmm_malloc(bytes); -#endif -} -#endif - -/**************************************************************************** - * Name: stm32_ep_freebuffer - * - * Description: - * Free an I/O buffer - * - ****************************************************************************/ - -#ifdef CONFIG_USBDEV_DMA -static void stm32_ep_freebuffer(struct usbdev_ep_s *ep, void *buf) -{ - usbtrace(TRACE_EPFREEBUFFER, ((struct stm32_ep_s *)ep)->epphy); - -#ifdef CONFIG_USBDEV_DMAMEMORY - usbdev_dma_free(buf); -#else - kmm_free(buf); -#endif -} -#endif - -/**************************************************************************** - * Name: stm32_ep_submit - * - * Description: - * Submit an I/O request to the endpoint - * - ****************************************************************************/ - -static int stm32_ep_submit(struct usbdev_ep_s *ep, - struct usbdev_req_s *req) -{ - struct stm32_req_s *privreq = (struct stm32_req_s *)req; - struct stm32_ep_s *privep = (struct stm32_ep_s *)ep; - struct stm32_usbdev_s *priv; - irqstate_t flags; - int ret = OK; - - /* Some sanity checking */ - -#ifdef CONFIG_DEBUG_FEATURES - if (!req || !req->callback || !req->buf || !ep) - { - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); - uinfo("req=%p callback=%p buf=%p ep=%p\n", - req, req->callback, req->buf, ep); - return -EINVAL; - } -#endif - - usbtrace(TRACE_EPSUBMIT, privep->epphy); - priv = privep->dev; - -#ifdef CONFIG_DEBUG_FEATURES - if (!priv->driver) - { - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_NOTCONFIGURED), - priv->usbdev.speed); - return -ESHUTDOWN; - } -#endif - - /* Handle the request from the class driver */ - - req->result = -EINPROGRESS; - req->xfrd = 0; - - /* Disable Interrupts */ - - flags = enter_critical_section(); - - /* If we are stalled, then drop all requests on the floor */ - - if (privep->stalled) - { - ret = -EBUSY; - } - else - { - /* Add the new request to the request queue for the endpoint. */ - - if (stm32_req_addlast(privep, privreq) && !privep->active) - { - /* If a request was added to an IN endpoint, then attempt to send - * the request data buffer now. - */ - - if (privep->isin) - { - usbtrace(TRACE_INREQQUEUED(privep->epphy), privreq->req.len); - - /* If the endpoint is not busy with another write request, - * then process the newly received write request now. - */ - - if (!privep->active) - { - stm32_epin_request(priv, privep); - } - } - - /* If the request was added to an OUT endpoint, then attempt to - * setup a read into the request data buffer now (this will, of - * course, fail if there is already a read in place). - */ - - else - { - usbtrace(TRACE_OUTREQQUEUED(privep->epphy), privreq->req.len); - stm32_epout_request(priv, privep); - } - } - } - - leave_critical_section(flags); - return ret; -} - -/**************************************************************************** - * Name: stm32_ep_cancel - * - * Description: - * Cancel an I/O request previously sent to an endpoint - * - ****************************************************************************/ - -static int stm32_ep_cancel(struct usbdev_ep_s *ep, - struct usbdev_req_s *req) -{ - struct stm32_ep_s *privep = (struct stm32_ep_s *)ep; - irqstate_t flags; - -#ifdef CONFIG_DEBUG_FEATURES - if (!ep || !req) - { - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); - return -EINVAL; - } -#endif - - usbtrace(TRACE_EPCANCEL, privep->epphy); - - flags = enter_critical_section(); - - /* FIXME: if the request is the first, then we need to flush the EP - * otherwise just remove it from the list - * - * but ... all other implementations cancel all requests ... - */ - - stm32_req_cancel(privep, -ESHUTDOWN); - leave_critical_section(flags); - return OK; -} - -/**************************************************************************** - * Name: stm32_epout_setstall - * - * Description: - * Stall an OUT endpoint - * - ****************************************************************************/ - -static int stm32_epout_setstall(struct stm32_ep_s *privep) -{ -#if 1 - /* This implementation follows the requirements from the STM32 F4 reference - * manual. - */ - - uint32_t regaddr; - uint32_t regval; - - /* Put the core in the Global OUT NAK mode */ - - stm32_enablegonak(privep); - - /* Disable and STALL the OUT endpoint by setting the EPDIS and STALL bits - * in the DOECPTL register. - */ - - regaddr = STM32_OTGHS_DOEPCTL(privep->epphy); - regval = stm32_getreg(regaddr); - regval |= (OTGHS_DOEPCTL_EPDIS | OTGHS_DOEPCTL_STALL); - stm32_putreg(regval, regaddr); - - /* Wait for the EPDISD interrupt which indicates that the OUT - * endpoint is completely disabled. - */ - -#if 0 /* Doesn't happen */ - regaddr = STM32_OTGHS_DOEPINT(privep->epphy); - while ((stm32_getreg(regaddr) & OTGHS_DOEPINT_EPDISD) == 0); -#else - /* REVISIT: */ - - up_udelay(10); -#endif - - /* Disable Global OUT NAK mode */ - - stm32_disablegonak(privep); - - /* The endpoint is now stalled */ - - privep->stalled = true; - return OK; -#else - /* This implementation follows the STMicro code example. */ - - /* REVISIT: */ - - uint32_t regaddr; - uint32_t regval; - - /* Stall the OUT endpoint by setting the STALL bit in the DOECPTL register. - */ - - regaddr = STM32_OTGHS_DOEPCTL(privep->epphy); - regval = stm32_getreg(regaddr); - regval |= OTGHS_DOEPCTL_STALL; - stm32_putreg(regval, regaddr); - - /* The endpoint is now stalled */ - - privep->stalled = true; - return OK; -#endif -} - -/**************************************************************************** - * Name: stm32_epin_setstall - * - * Description: - * Stall an IN endpoint - * - ****************************************************************************/ - -static int stm32_epin_setstall(struct stm32_ep_s *privep) -{ - uint32_t regaddr; - uint32_t regval; - - /* Get the IN endpoint device control register */ - - regaddr = STM32_OTGHS_DIEPCTL(privep->epphy); - regval = stm32_getreg(regaddr); - - /* Then stall the endpoint */ - - regval |= OTGHS_DIEPCTL_STALL; - stm32_putreg(regval, regaddr); - - /* The endpoint is now stalled */ - - privep->stalled = true; - return OK; -} - -/**************************************************************************** - * Name: stm32_ep_setstall - * - * Description: - * Stall an endpoint - * - ****************************************************************************/ - -static int stm32_ep_setstall(struct stm32_ep_s *privep) -{ - usbtrace(TRACE_EPSTALL, privep->epphy); - - /* Is this an IN endpoint? */ - - if (privep->isin == 1) - { - return stm32_epin_setstall(privep); - } - else - { - return stm32_epout_setstall(privep); - } -} - -/**************************************************************************** - * Name: stm32_ep_clrstall - * - * Description: - * Resume a stalled endpoint - * - ****************************************************************************/ - -static int stm32_ep_clrstall(struct stm32_ep_s *privep) -{ - uint32_t regaddr; - uint32_t regval; - uint32_t stallbit; - uint32_t data0bit; - - usbtrace(TRACE_EPRESUME, privep->epphy); - - /* Is this an IN endpoint? */ - - if (privep->isin == 1) - { - /* Clear the stall bit in the IN endpoint device control register */ - - regaddr = STM32_OTGHS_DIEPCTL(privep->epphy); - stallbit = OTGHS_DIEPCTL_STALL; - data0bit = OTGHS_DIEPCTL_SD0PID; - } - else - { - /* Clear the stall bit in the IN endpoint device control register */ - - regaddr = STM32_OTGHS_DOEPCTL(privep->epphy); - stallbit = OTGHS_DOEPCTL_STALL; - data0bit = OTGHS_DOEPCTL_SD0PID; - } - - /* Clear the stall bit */ - - regval = stm32_getreg(regaddr); - regval &= ~stallbit; - - /* Set the DATA0 pid for interrupt and bulk endpoints */ - - if (privep->eptype == USB_EP_ATTR_XFER_INT || - privep->eptype == USB_EP_ATTR_XFER_BULK) - { - /* Writing this bit sets the DATA0 PID */ - - regval |= data0bit; - } - - stm32_putreg(regval, regaddr); - - /* The endpoint is no longer stalled */ - - privep->stalled = false; - return OK; -} - -/**************************************************************************** - * Name: stm32_ep_stall - * - * Description: - * Stall or resume an endpoint - * - ****************************************************************************/ - -static int stm32_ep_stall(struct usbdev_ep_s *ep, bool resume) -{ - struct stm32_ep_s *privep = (struct stm32_ep_s *)ep; - irqstate_t flags; - int ret; - - /* Set or clear the stall condition as requested */ - - flags = enter_critical_section(); - if (resume) - { - ret = stm32_ep_clrstall(privep); - } - else - { - ret = stm32_ep_setstall(privep); - } - - leave_critical_section(flags); - - return ret; -} - -/**************************************************************************** - * Name: stm32_ep0_stall - * - * Description: - * Stall endpoint 0 - * - ****************************************************************************/ - -static void stm32_ep0_stall(struct stm32_usbdev_s *priv) -{ - stm32_epin_setstall(&priv->epin[EP0]); - stm32_epout_setstall(&priv->epout[EP0]); - priv->stalled = true; - stm32_ep0out_ctrlsetup(priv); -} - -/**************************************************************************** - * Device operations - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_ep_alloc - * - * Description: - * Allocate an endpoint matching the parameters. - * - * Input Parameters: - * eplog - 7-bit logical endpoint number (direction bit ignored). Zero - * means that any endpoint matching the other requirements will - * suffice. The assigned endpoint can be found in the eplog - * field. - * in - true: IN (device-to-host) endpoint requested - * eptype - Endpoint type. One of {USB_EP_ATTR_XFER_ISOC, - * USB_EP_ATTR_XFER_BULK, USB_EP_ATTR_XFER_INT} - * - ****************************************************************************/ - -static struct usbdev_ep_s *stm32_ep_alloc(struct usbdev_s *dev, - uint8_t eplog, bool in, - uint8_t eptype) -{ - struct stm32_usbdev_s *priv = (struct stm32_usbdev_s *)dev; - uint8_t epavail; - irqstate_t flags; - int epphy; - int epno = 0; - - usbtrace(TRACE_DEVALLOCEP, (uint16_t)eplog); - - /* Ignore any direction bits in the logical address */ - - epphy = USB_EPNO(eplog); - - /* Get the set of available endpoints depending on the direction */ - - flags = enter_critical_section(); - epavail = priv->epavail[in]; - - /* A physical address of 0 means that any endpoint will do */ - - if (epphy > 0) - { - /* Otherwise, we will return the endpoint structure only for the - * requested 'logical' endpoint. All of the other checks will still - * be performed. - * - * First, verify that the logical endpoint is in the range supported by - * by the hardware. - */ - - if (epphy >= STM32_NENDPOINTS) - { - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADEPNO), (uint16_t)epphy); - return NULL; - } - - /* Remove all of the candidate endpoints from the bitset except for the - * this physical endpoint number. - */ - - epavail &= (1 << epphy); - } - - /* Is there an available endpoint? */ - - if (epavail) - { - /* Yes.. Select the lowest numbered endpoint in the set of available - * endpoints. - */ - - for (epno = 1; epno < STM32_NENDPOINTS; epno++) - { - uint8_t bit = 1 << epno; - if ((epavail & bit) != 0) - { - /* Mark the endpoint no longer available */ - - priv->epavail[in] &= ~(1 << epno); - - /* And return the pointer to the standard endpoint structure */ - - leave_critical_section(flags); - return in ? &priv->epin[epno].ep : &priv->epout[epno].ep; - } - } - - /* We should not get here */ - } - - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_NOEP), (uint16_t)eplog); - leave_critical_section(flags); - return NULL; -} - -/**************************************************************************** - * Name: stm32_ep_free - * - * Description: - * Free the previously allocated endpoint - * - ****************************************************************************/ - -static void stm32_ep_free(struct usbdev_s *dev, - struct usbdev_ep_s *ep) -{ - struct stm32_usbdev_s *priv = (struct stm32_usbdev_s *)dev; - struct stm32_ep_s *privep = (struct stm32_ep_s *)ep; - irqstate_t flags; - - usbtrace(TRACE_DEVFREEEP, (uint16_t)privep->epphy); - - if (priv && privep) - { - /* Mark the endpoint as available */ - - flags = enter_critical_section(); - priv->epavail[privep->isin] |= (1 << privep->epphy); - leave_critical_section(flags); - } -} - -/**************************************************************************** - * Name: stm32_getframe - * - * Description: - * Returns the current frame number - * - ****************************************************************************/ - -static int stm32_getframe(struct usbdev_s *dev) -{ - uint32_t regval; - - usbtrace(TRACE_DEVGETFRAME, 0); - - /* Return the last frame number of the last SOF detected by the hardware */ - - regval = stm32_getreg(STM32_OTGHS_DSTS); - return (int)((regval & OTGHS_DSTS_SOFFN_MASK) >> OTGHS_DSTS_SOFFN_SHIFT); -} - -/**************************************************************************** - * Name: stm32_wakeup - * - * Description: - * Exit suspend mode. - * - ****************************************************************************/ - -static int stm32_wakeup(struct usbdev_s *dev) -{ - struct stm32_usbdev_s *priv = (struct stm32_usbdev_s *)dev; - uint32_t regval; - irqstate_t flags; - - usbtrace(TRACE_DEVWAKEUP, 0); - - /* Is wakeup enabled? */ - - flags = enter_critical_section(); - if (priv->wakeup) - { - /* Yes... is the core suspended? */ - - regval = stm32_getreg(STM32_OTGHS_DSTS); - if ((regval & OTGHS_DSTS_SUSPSTS) != 0) - { - /* Re-start the PHY clock and un-gate USB core clock (HCLK) */ - -#ifdef CONFIG_USBDEV_LOWPOWER - regval = stm32_getreg(STM32_OTGHS_PCGCCTL); - regval &= ~(OTGHS_PCGCCTL_STPPCLK | OTGHS_PCGCCTL_GATEHCLK); - stm32_putreg(regval, STM32_OTGHS_PCGCCTL); -#endif - /* Activate Remote wakeup signaling */ - - regval = stm32_getreg(STM32_OTGHS_DCTL); - regval |= OTGHS_DCTL_RWUSIG; - stm32_putreg(regval, STM32_OTGHS_DCTL); - up_mdelay(5); - regval &= ~OTGHS_DCTL_RWUSIG; - stm32_putreg(regval, STM32_OTGHS_DCTL); - } - } - - leave_critical_section(flags); - return OK; -} - -/**************************************************************************** - * Name: stm32_selfpowered - * - * Description: - * Sets/clears the device self-powered feature - * - ****************************************************************************/ - -static int stm32_selfpowered(struct usbdev_s *dev, bool selfpowered) -{ - struct stm32_usbdev_s *priv = (struct stm32_usbdev_s *)dev; - - usbtrace(TRACE_DEVSELFPOWERED, (uint16_t)selfpowered); - -#ifdef CONFIG_DEBUG_FEATURES - if (!dev) - { - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); - return -ENODEV; - } -#endif - - priv->selfpowered = selfpowered; - return OK; -} - -/**************************************************************************** - * Name: stm32_pullup - * - * Description: - * Software-controlled connect to/disconnect from USB host - * - ****************************************************************************/ - -static int stm32_pullup(struct usbdev_s *dev, bool enable) -{ - uint32_t regval; - - usbtrace(TRACE_DEVPULLUP, (uint16_t)enable); - - irqstate_t flags = enter_critical_section(); - regval = stm32_getreg(STM32_OTGHS_DCTL); - if (enable) - { - /* Connect the device by clearing the soft disconnect bit in the DCTL - * register - */ - - regval &= ~OTGHS_DCTL_SDIS; - } - else - { - /* Connect the device by setting the soft disconnect bit in the DCTL - * register - */ - - regval |= OTGHS_DCTL_SDIS; - } - - stm32_putreg(regval, STM32_OTGHS_DCTL); - leave_critical_section(flags); - return OK; -} - -/**************************************************************************** - * Name: stm32_setaddress - * - * Description: - * Set the devices USB address - * - ****************************************************************************/ - -static void stm32_setaddress(struct stm32_usbdev_s *priv, uint16_t address) -{ - uint32_t regval; - - /* Set the device address in the DCFG register */ - - regval = stm32_getreg(STM32_OTGHS_DCFG); - regval &= ~OTGHS_DCFG_DAD_MASK; - regval |= ((uint32_t)address << OTGHS_DCFG_DAD_SHIFT); - stm32_putreg(regval, STM32_OTGHS_DCFG); - - /* Are we now addressed? (i.e., do we have a non-NULL device - * address?) - */ - - if (address != 0) - { - priv->devstate = DEVSTATE_ADDRESSED; - priv->addressed = true; - } - else - { - priv->devstate = DEVSTATE_DEFAULT; - priv->addressed = false; - } -} - -/**************************************************************************** - * Name: stm32_txfifo_flush - * - * Description: - * Flush the specific TX fifo. - * - ****************************************************************************/ - -static int stm32_txfifo_flush(uint32_t txfnum) -{ - uint32_t regval; - uint32_t timeout; - - /* Initiate the TX FIFO flush operation */ - - regval = OTGHS_GRSTCTL_TXFFLSH | txfnum; - stm32_putreg(regval, STM32_OTGHS_GRSTCTL); - - /* Wait for the FLUSH to complete */ - - for (timeout = 0; timeout < STM32_FLUSH_DELAY; timeout++) - { - regval = stm32_getreg(STM32_OTGHS_GRSTCTL); - if ((regval & OTGHS_GRSTCTL_TXFFLSH) == 0) - { - break; - } - } - - /* Wait for 3 PHY Clocks */ - - up_udelay(3); - return OK; -} - -/**************************************************************************** - * Name: stm32_rxfifo_flush - * - * Description: - * Flush the RX fifo. - * - ****************************************************************************/ - -static int stm32_rxfifo_flush(void) -{ - uint32_t regval; - uint32_t timeout; - - /* Initiate the RX FIFO flush operation */ - - stm32_putreg(OTGHS_GRSTCTL_RXFFLSH, STM32_OTGHS_GRSTCTL); - - /* Wait for the FLUSH to complete */ - - for (timeout = 0; timeout < STM32_FLUSH_DELAY; timeout++) - { - regval = stm32_getreg(STM32_OTGHS_GRSTCTL); - if ((regval & OTGHS_GRSTCTL_RXFFLSH) == 0) - { - break; - } - } - - /* Wait for 3 PHY Clocks */ - - up_udelay(3); - return OK; -} - -/**************************************************************************** - * Name: stm32_swinitialize - * - * Description: - * Initialize all driver data structures. - * - ****************************************************************************/ - -static void stm32_swinitialize(struct stm32_usbdev_s *priv) -{ - struct stm32_ep_s *privep; - int i; - - /* Initialize the device state structure */ - - memset(priv, 0, sizeof(struct stm32_usbdev_s)); - - priv->usbdev.ops = &g_devops; - priv->usbdev.ep0 = &priv->epin[EP0].ep; - - priv->epavail[0] = STM32_EP_AVAILABLE; - priv->epavail[1] = STM32_EP_AVAILABLE; - - /* Initialize the endpoint lists */ - - for (i = 0; i < STM32_NENDPOINTS; i++) - { - /* Set endpoint operations, reference to driver structure (not - * really necessary because there is only one controller), and - * the physical endpoint number (which is just the index to the - * endpoint). - */ - - privep = &priv->epin[i]; - privep->ep.ops = &g_epops; - privep->dev = priv; - privep->isin = 1; - - /* The index, i, is the physical endpoint address; Map this - * to a logical endpoint address usable by the class driver. - */ - - privep->epphy = i; - privep->ep.eplog = STM32_EPPHYIN2LOG(i); - - /* Control until endpoint is activated */ - - privep->eptype = USB_EP_ATTR_XFER_CONTROL; - privep->ep.maxpacket = CONFIG_USBDEV_EP0_MAXSIZE; - } - - /* Initialize the endpoint lists */ - - for (i = 0; i < STM32_NENDPOINTS; i++) - { - /* Set endpoint operations, reference to driver structure (not - * really necessary because there is only one controller), and - * the physical endpoint number (which is just the index to the - * endpoint). - */ - - privep = &priv->epout[i]; - privep->ep.ops = &g_epops; - privep->dev = priv; - - /* The index, i, is the physical endpoint address; Map this - * to a logical endpoint address usable by the class driver. - */ - - privep->epphy = i; - privep->ep.eplog = STM32_EPPHYOUT2LOG(i); - - /* Control until endpoint is activated */ - - privep->eptype = USB_EP_ATTR_XFER_CONTROL; - privep->ep.maxpacket = CONFIG_USBDEV_EP0_MAXSIZE; - } -} - -/**************************************************************************** - * Name: stm32_hwinitialize - * - * Description: - * Configure the OTG HS core for operation. - * - ****************************************************************************/ - -static void stm32_hwinitialize(struct stm32_usbdev_s *priv) -{ - uint32_t regval; - uint32_t timeout; - uint32_t address; - int i; - - /* At start-up the core is in HS mode. */ - - /* Disable global interrupts by clearing the GINTMASK bit in the GAHBCFG - * register; Set the TXFELVL bit in the GAHBCFG register so that TxFIFO - * interrupts will occur when the TxFIFO is truly empty (not just half - * full). - */ - - stm32_putreg(OTGHS_GAHBCFG_TXFELVL, STM32_OTGHS_GAHBCFG); - - /* Set the PHYSEL bit in the GUSBCFG register to select the OTG HS serial - * transceiver: "This bit is always 1 with write-only access" - */ - - regval = stm32_getreg(STM32_OTGHS_GUSBCFG); - regval |= OTGHS_GUSBCFG_PHYSEL; - stm32_putreg(regval, STM32_OTGHS_GUSBCFG); - - /* Common USB OTG core initialization */ - - /* Reset after a PHY select and set Host mode. First, wait for AHB master - * IDLE state. - */ - - for (timeout = 0; timeout < STM32_READY_DELAY; timeout++) - { - up_udelay(3); - regval = stm32_getreg(STM32_OTGHS_GRSTCTL); - if ((regval & OTGHS_GRSTCTL_AHBIDL) != 0) - { - break; - } - } - - /* Then perform the core soft reset. */ - - stm32_putreg(OTGHS_GRSTCTL_CSRST, STM32_OTGHS_GRSTCTL); - for (timeout = 0; timeout < STM32_READY_DELAY; timeout++) - { - regval = stm32_getreg(STM32_OTGHS_GRSTCTL); - if ((regval & OTGHS_GRSTCTL_CSRST) == 0) - { - break; - } - } - - /* Wait for 3 PHY Clocks */ - - up_udelay(3); - - /* Deactivate the power down */ - - regval = (OTGHS_GCCFG_PWRDWN | - OTGHS_GCCFG_VBUSASEN | - OTGHS_GCCFG_VBUSBSEN); -#ifndef CONFIG_USBDEV_VBUSSENSING - regval |= OTGHS_GCCFG_NOVBUSSENS; -#endif -#ifdef CONFIG_STM32_OTGHS_SOFOUTPUT - regval |= OTGHS_GCCFG_SOFOUTEN; -#endif - stm32_putreg(regval, STM32_OTGHS_GCCFG); - up_mdelay(20); - - /* Force Device Mode */ - - regval = stm32_getreg(STM32_OTGHS_GUSBCFG); - regval &= ~OTGHS_GUSBCFG_FHMOD; - regval |= OTGHS_GUSBCFG_FDMOD; - stm32_putreg(regval, STM32_OTGHS_GUSBCFG); - up_mdelay(50); - - /* Initialize device mode */ - - /* Restart the PHY Clock */ - - stm32_putreg(0, STM32_OTGHS_PCGCCTL); - - /* Device configuration register */ - - regval = stm32_getreg(STM32_OTGHS_DCFG); - regval &= ~OTGHS_DCFG_PFIVL_MASK; - regval |= OTGHS_DCFG_PFIVL_80PCT; - stm32_putreg(regval, STM32_OTGHS_DCFG); - - /* Set full speed PHY */ - - regval = stm32_getreg(STM32_OTGHS_DCFG); - regval &= ~OTGHS_DCFG_DSPD_MASK; - regval |= OTGHS_DCFG_DSPD_FS; - stm32_putreg(regval, STM32_OTGHS_DCFG); - - /* Set Rx FIFO size */ - - stm32_putreg(STM32_RXFIFO_WORDS, STM32_OTGHS_GRXFSIZ); - - /* EP0 TX */ - - address = STM32_RXFIFO_WORDS; - regval = (address << OTGHS_DIEPTXF0_TX0FD_SHIFT) | - (STM32_EP0_TXFIFO_WORDS << OTGHS_DIEPTXF0_TX0FSA_SHIFT); - stm32_putreg(regval, STM32_OTGHS_DIEPTXF0); - - /* EP1 TX */ - - address += STM32_EP0_TXFIFO_WORDS; - regval = (address << OTGHS_DIEPTXF_INEPTXSA_SHIFT) | - (STM32_EP1_TXFIFO_WORDS << OTGHS_DIEPTXF_INEPTXFD_SHIFT); - stm32_putreg(regval, STM32_OTGHS_DIEPTXF1); - - /* EP2 TX */ - - address += STM32_EP1_TXFIFO_WORDS; - regval = (address << OTGHS_DIEPTXF_INEPTXSA_SHIFT) | - (STM32_EP2_TXFIFO_WORDS << OTGHS_DIEPTXF_INEPTXFD_SHIFT); - stm32_putreg(regval, STM32_OTGHS_DIEPTXF2); - - /* EP3 TX */ - - address += STM32_EP2_TXFIFO_WORDS; - regval = (address << OTGHS_DIEPTXF_INEPTXSA_SHIFT) | - (STM32_EP3_TXFIFO_WORDS << OTGHS_DIEPTXF_INEPTXFD_SHIFT); - stm32_putreg(regval, STM32_OTGHS_DIEPTXF3); - - /* Flush the FIFOs */ - - stm32_txfifo_flush(OTGHS_GRSTCTL_TXFNUM_DALL); - stm32_rxfifo_flush(); - - /* Clear all pending Device Interrupts */ - - stm32_putreg(0, STM32_OTGHS_DIEPMSK); - stm32_putreg(0, STM32_OTGHS_DOEPMSK); - stm32_putreg(0, STM32_OTGHS_DIEPEMPMSK); - stm32_putreg(0xffffffff, STM32_OTGHS_DAINT); - stm32_putreg(0, STM32_OTGHS_DAINTMSK); - - /* Configure all IN endpoints */ - - for (i = 0; i < STM32_NENDPOINTS; i++) - { - regval = stm32_getreg(STM32_OTGHS_DIEPCTL(i)); - if ((regval & OTGHS_DIEPCTL_EPENA) != 0) - { - /* The endpoint is already enabled */ - - regval = OTGHS_DIEPCTL_EPENA | OTGHS_DIEPCTL_SNAK; - } - else - { - regval = 0; - } - - stm32_putreg(regval, STM32_OTGHS_DIEPCTL(i)); - stm32_putreg(0, STM32_OTGHS_DIEPTSIZ(i)); - stm32_putreg(0xff, STM32_OTGHS_DIEPINT(i)); - } - - /* Configure all OUT endpoints */ - - for (i = 0; i < STM32_NENDPOINTS; i++) - { - regval = stm32_getreg(STM32_OTGHS_DOEPCTL(i)); - if ((regval & OTGHS_DOEPCTL_EPENA) != 0) - { - /* The endpoint is already enabled */ - - regval = OTGHS_DOEPCTL_EPENA | OTGHS_DOEPCTL_SNAK; - } - else - { - regval = 0; - } - - stm32_putreg(regval, STM32_OTGHS_DOEPCTL(i)); - stm32_putreg(0, STM32_OTGHS_DOEPTSIZ(i)); - stm32_putreg(0xff, STM32_OTGHS_DOEPINT(i)); - } - - /* Disable all interrupts. */ - - stm32_putreg(0, STM32_OTGHS_GINTMSK); - - /* Clear any pending USB_OTG Interrupts */ - - stm32_putreg(0xffffffff, STM32_OTGHS_GOTGINT); - - /* Clear any pending interrupts */ - - stm32_putreg(0xbfffffff, STM32_OTGHS_GINTSTS); - -#ifndef BOARD_ENABLE_USBOTG_HSULPI - /* Disable the ULPI Clock enable in RCC AHB1 Register. This must - * be done because if both the ULPI and the FS PHY clock enable bits - * are set at the same time, the ARM never awakens from WFI due to - * some bug / errata in the chip. - */ - - regval = stm32_getreg(STM32_RCC_AHB1LPENR); - regval &= ~RCC_AHB1ENR_OTGHSULPIEN; - stm32_putreg(regval, STM32_RCC_AHB1LPENR); -#endif - - /* Enable the interrupts in the INTMSK */ - - regval = (OTGHS_GINT_RXFLVL | OTGHS_GINT_USBSUSP | OTGHS_GINT_ENUMDNE | - OTGHS_GINT_IEP | OTGHS_GINT_OEP | OTGHS_GINT_USBRST); - -#ifdef CONFIG_USBDEV_ISOCHRONOUS - regval |= (OTGHS_GINT_IISOIXFR | OTGHS_GINT_IISOOXFR); -#endif - -#ifdef CONFIG_USBDEV_SOFINTERRUPT - regval |= OTGHS_GINT_SOF; -#endif - -#ifdef CONFIG_USBDEV_VBUSSENSING - regval |= (OTGHS_GINT_OTG | OTGHS_GINT_SRQ); -#endif - -#ifdef CONFIG_DEBUG_USB - regval |= OTGHS_GINT_MMIS; -#endif - - stm32_putreg(regval, STM32_OTGHS_GINTMSK); - - /* Enable the USB global interrupt by setting GINTMSK in the global OTG - * HS AHB configuration register; Set the TXFELVL bit in the GAHBCFG - * register so that TxFIFO interrupts will occur when the TxFIFO is truly - * empty (not just half full). - */ - - stm32_putreg(OTGHS_GAHBCFG_GINTMSK | OTGHS_GAHBCFG_TXFELVL, - STM32_OTGHS_GAHBCFG); -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: arm_usbinitialize - * - * Description: - * Initialize USB hardware. - * - * Assumptions: - * - This function is called very early in the initialization sequence - * - PLL and GIO pin initialization is not performed here but should been in - * the low-level boot logic: PLL1 must be configured for operation at - * 48MHz and P0.23 and PO.31 in PINSEL1 must be configured for Vbus and USB - * connect LED. - * - ****************************************************************************/ - -void arm_usbinitialize(void) -{ - /* At present, there is only a single OTG HS device support. Hence it is - * pre-allocated as g_otghsdev. However, in most code, the private data - * structure will be referenced using the 'priv' pointer (rather than the - * global data) in order to simplify any future support for multiple - * devices. - */ - - struct stm32_usbdev_s *priv = &g_otghsdev; - int ret; - - usbtrace(TRACE_DEVINIT, 0); - - /* Here we assume that: - * - * 1. GPIOA and OTG HS peripheral clocking has already been enabled as part - * of the boot sequence. - * 2. Board-specific logic has already enabled other board specific GPIOs - * for things like soft pull-up, VBUS sensing, power controls, and over- - * current detection. - */ - - /* Configure OTG HS alternate function pins - * - * PIN* SIGNAL DIRECTION - * ---- ----------- ---------- - * PA8 OTG_HS_SOF SOF clock output - * PA9 OTG_HS_VBUS VBUS input for device, Driven by external regulator by - * host (not an alternate function) - * PA10 OTG_HS_ID OTG ID pin (only needed in Dual mode) - * PA11 OTG_HS_DM D- I/O - * PA12 OTG_HS_DP D+ I/O - * - * *Pins may vary from device-to-device. - */ - - stm32_configgpio(GPIO_OTGHS_DM); - stm32_configgpio(GPIO_OTGHS_DP); - stm32_configgpio(GPIO_OTGHS_ID); /* Only needed for OTG */ - - /* SOF output pin configuration is configurable. */ - -#ifdef CONFIG_STM32_OTGHS_SOFOUTPUT - stm32_configgpio(GPIO_OTGHS_SOF); -#endif - - /* Uninitialize the hardware so that we know that we are starting from a - * known state. - */ - - arm_usbuninitialize(); - - /* Initialize the driver data structure */ - - stm32_swinitialize(priv); - - /* Attach the OTG HS interrupt handler */ - - ret = irq_attach(STM32_IRQ_OTGHS, stm32_usbinterrupt, NULL); - if (ret < 0) - { - uerr("ERROR: irq_attach failed: %d\n", ret); - goto errout; - } - - /* Initialize the USB OTG core */ - - stm32_hwinitialize(priv); - - /* Disconnect device */ - - stm32_pullup(&priv->usbdev, false); - - /* Reset/Re-initialize the USB hardware */ - - stm32_usbreset(priv); - - /* Enable USB controller interrupts at the NVIC */ - - up_enable_irq(STM32_IRQ_OTGHS); - return; - -errout: - arm_usbuninitialize(); -} - -/**************************************************************************** - * Name: up_usbhsuninitialize - ****************************************************************************/ - -void arm_usbuninitialize(void) -{ - /* At present, there is only a single OTG HS device support. Hence it is - * pre-allocated as g_otghsdev. However, in most code, the private data - * structure will be referenced using the 'priv' pointer (rather than the - * global data) in order to simplify any future support for multiple - * devices. - */ - - struct stm32_usbdev_s *priv = &g_otghsdev; - irqstate_t flags; - int i; - - usbtrace(TRACE_DEVUNINIT, 0); - - if (priv->driver) - { - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_DRIVERREGISTERED), 0); - usbdev_unregister(priv->driver); - } - - /* Disconnect device */ - - flags = enter_critical_section(); - stm32_pullup(&priv->usbdev, false); - priv->usbdev.speed = USB_SPEED_UNKNOWN; - - /* Disable and detach IRQs */ - - up_disable_irq(STM32_IRQ_OTGHS); - irq_detach(STM32_IRQ_OTGHS); - - /* Disable all endpoint interrupts */ - - for (i = 0; i < STM32_NENDPOINTS; i++) - { - stm32_putreg(0xff, STM32_OTGHS_DIEPINT(i)); - stm32_putreg(0xff, STM32_OTGHS_DOEPINT(i)); - } - - stm32_putreg(0, STM32_OTGHS_DIEPMSK); - stm32_putreg(0, STM32_OTGHS_DOEPMSK); - stm32_putreg(0, STM32_OTGHS_DIEPEMPMSK); - stm32_putreg(0, STM32_OTGHS_DAINTMSK); - stm32_putreg(0xffffffff, STM32_OTGHS_DAINT); - - /* Flush the FIFOs */ - - stm32_txfifo_flush(OTGHS_GRSTCTL_TXFNUM_DALL); - stm32_rxfifo_flush(); - - /* TODO: Turn off USB power and clocking */ - - priv->devstate = DEVSTATE_DEFAULT; - leave_critical_section(flags); -} - -/**************************************************************************** - * Name: usbdev_register - * - * Description: - * Register a USB device class driver. The class driver's bind() method - * will be called to bind it to a USB device driver. - * - ****************************************************************************/ - -int usbdev_register(struct usbdevclass_driver_s *driver) -{ - /* At present, there is only a single OTG HS device support. Hence it is - * pre-allocated as g_otghsdev. However, in most code, the private data - * structure will be referenced using the 'priv' pointer (rather than the - * global data) in order to simplify any future support for multiple - * devices. - */ - - struct stm32_usbdev_s *priv = &g_otghsdev; - int ret; - - usbtrace(TRACE_DEVREGISTER, 0); - -#ifdef CONFIG_DEBUG_FEATURES - if (!driver || !driver->ops->bind || !driver->ops->unbind || - !driver->ops->disconnect || !driver->ops->setup) - { - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); - return -EINVAL; - } - - if (priv->driver) - { - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_DRIVER), 0); - return -EBUSY; - } -#endif - - /* First hook up the driver */ - - priv->driver = driver; - - /* Then bind the class driver */ - - ret = CLASS_BIND(driver, &priv->usbdev); - if (ret) - { - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BINDFAILED), (uint16_t)-ret); - priv->driver = NULL; - } - else - { - /* Enable USB controller interrupts */ - - up_enable_irq(STM32_IRQ_OTGHS); - - /* FIXME: nothing seems to call DEV_CONNECT(), but we need to set - * the RS bit to enable the controller. It kind of makes sense - * to do this after the class has bound to us... - * GEN: This bug is really in the class driver. It should make the - * soft connect when it is ready to be enumerated. I have added - * that logic to the class drivers but left this logic here. - */ - - stm32_pullup(&priv->usbdev, true); - priv->usbdev.speed = USB_SPEED_FULL; - } - - return ret; -} - -/**************************************************************************** - * Name: usbdev_unregister - * - * Description: - * Un-register usbdev class driver.If the USB device is connected to a - * USB host, it will first disconnect(). The driver is also requested - * to unbind() and clean up any device state, before this procedure - * finally returns. - * - ****************************************************************************/ - -int usbdev_unregister(struct usbdevclass_driver_s *driver) -{ - /* At present, there is only a single OTG HS device support. Hence it is - * pre-allocated as g_otghsdev. However, in most code, the private data - * structure will be referenced using the 'priv' pointer (rather than the - * global data) in order to simplify any future support for multiple - * devices. - */ - - struct stm32_usbdev_s *priv = &g_otghsdev; - irqstate_t flags; - - usbtrace(TRACE_DEVUNREGISTER, 0); - -#ifdef CONFIG_DEBUG_FEATURES - if (driver != priv->driver) - { - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); - return -EINVAL; - } -#endif - - /* Reset the hardware and cancel all requests. All requests must be - * canceled while the class driver is still bound. - */ - - flags = enter_critical_section(); - stm32_usbreset(priv); - leave_critical_section(flags); - - /* Unbind the class driver */ - - CLASS_UNBIND(driver, &priv->usbdev); - - /* Disable USB controller interrupts */ - - flags = enter_critical_section(); - up_disable_irq(STM32_IRQ_OTGHS); - - /* Disconnect device */ - - stm32_pullup(&priv->usbdev, false); - - /* Unhook the driver */ - - priv->driver = NULL; - leave_critical_section(flags); - - return OK; -} - -#endif /* CONFIG_USBDEV && CONFIG_STM32_OTGHSDEV */ diff --git a/arch/arm/src/stm32/stm32_otghshost.c b/arch/arm/src/stm32/stm32_otghshost.c deleted file mode 100644 index 4acc263c4209f..0000000000000 --- a/arch/arm/src/stm32/stm32_otghshost.c +++ /dev/null @@ -1,5470 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_otghshost.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include - -#include "chip.h" /* Includes default GPIO settings */ -#include /* May redefine GPIO settings */ - -#include "arm_internal.h" -#include "stm32_gpio.h" -#include "stm32_usbhost.h" - -#if defined(CONFIG_STM32_USBHOST) && defined(CONFIG_STM32_OTGHS) - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -/* STM32 USB OTG HS Host Driver Support - * - * Pre-requisites - * - * CONFIG_STM32_USBHOST - Enable STM32 USB host support - * CONFIG_USBHOST - Enable general USB host support - * CONFIG_STM32_OTGHS - Enable the STM32 USB OTG HS block - * CONFIG_STM32_SYSCFG - Needed - * - * Options: - * - * CONFIG_STM32_OTGHS_RXFIFO_SIZE - Size of the RX FIFO in 32-bit words. - * Default 128 (512 bytes) - * CONFIG_STM32_OTGHS_NPTXFIFO_SIZE - Size of the non-periodic Tx FIFO - * in 32-bit words. Default 96 (384 bytes) - * CONFIG_STM32_OTGHS_PTXFIFO_SIZE - Size of the periodic Tx FIFO in 32-bit - * words. Default 96 (384 bytes) - * CONFIG_STM32_OTGHS_DESCSIZE - Maximum size of a descriptor. Default: 128 - * CONFIG_STM32_OTGHS_SOFINTR - Enable SOF interrupts. Why would you ever - * want to do that? - * CONFIG_STM32_USBHOST_REGDEBUG - Enable very low-level register access - * debug. Depends on CONFIG_DEBUG_FEATURES. - * CONFIG_STM32_USBHOST_PKTDUMP - Dump all incoming and outgoing USB - * packets. Depends on CONFIG_DEBUG_FEATURES. - */ - -/* Pre-requisites (partial) */ - -#ifndef CONFIG_STM32_SYSCFG -# error "CONFIG_STM32_SYSCFG is required" -#endif - -/* Default RxFIFO size */ - -#ifndef CONFIG_STM32_OTGHS_RXFIFO_SIZE -# define CONFIG_STM32_OTGHS_RXFIFO_SIZE 128 -#endif - -/* Default host non-periodic Tx FIFO size */ - -#ifndef CONFIG_STM32_OTGHS_NPTXFIFO_SIZE -# define CONFIG_STM32_OTGHS_NPTXFIFO_SIZE 96 -#endif - -/* Default host periodic Tx fifo size register */ - -#ifndef CONFIG_STM32_OTGHS_PTXFIFO_SIZE -# define CONFIG_STM32_OTGHS_PTXFIFO_SIZE 96 -#endif - -/* Maximum size of a descriptor */ - -#ifndef CONFIG_STM32_OTGHS_DESCSIZE -# define CONFIG_STM32_OTGHS_DESCSIZE 128 -#endif - -/* Register/packet debug depends on CONFIG_DEBUG_FEATURES */ - -#ifndef CONFIG_DEBUG_USB_INFO -# undef CONFIG_STM32_USBHOST_REGDEBUG -# undef CONFIG_STM32_USBHOST_PKTDUMP -#endif - -/* HCD Setup ****************************************************************/ - -/* Hardware capabilities */ - -#if defined(CONFIG_STM32_STM32F446) -# define STM32_NHOST_CHANNELS 16 /* Number of host channels */ -# define STM32_MAX_TX_FIFOS 16 /* Max number of TX FIFOs */ -#else -# define STM32_NHOST_CHANNELS 12 /* Number of host channels */ -# define STM32_MAX_TX_FIFOS 12 /* Max number of TX FIFOs */ -#endif -#define STM32_MAX_PACKET_SIZE 64 /* Full speed max packet size */ -#define STM32_EP0_DEF_PACKET_SIZE 8 /* EP0 default packet size */ -#define STM32_EP0_MAX_PACKET_SIZE 64 /* EP0 HS max packet size */ -#define STM32_MAX_PKTCOUNT 256 /* Max packet count */ -#define STM32_RETRY_COUNT 3 /* Number of ctrl transfer retries */ - -/* Delays *******************************************************************/ - -#define STM32_READY_DELAY 200000 /* In loop counts */ -#define STM32_FLUSH_DELAY 200000 /* In loop counts */ -#define STM32_SETUP_DELAY SEC2TICK(5) /* 5 seconds in system ticks */ -#define STM32_DATANAK_DELAY SEC2TICK(5) /* 5 seconds in system ticks */ - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/* The following enumeration represents the various states of the USB host - * state machine (for debug purposes only) - */ - -enum stm32_smstate_e -{ - SMSTATE_DETACHED = 0, /* Not attached to a device */ - SMSTATE_ATTACHED, /* Attached to a device */ - SMSTATE_ENUM, /* Attached, enumerating */ - SMSTATE_CLASS_BOUND, /* Enumeration complete, class bound */ -}; - -/* This enumeration provides the reason for the channel halt. */ - -enum stm32_chreason_e -{ - CHREASON_IDLE = 0, /* Inactive (initial state) */ - CHREASON_FREED, /* Channel is no longer in use */ - CHREASON_XFRC, /* Transfer complete */ - CHREASON_NAK, /* NAK received */ - CHREASON_NYET, /* NotYet received */ - CHREASON_STALL, /* Endpoint stalled */ - CHREASON_TXERR, /* Transfer error received */ - CHREASON_DTERR, /* Data toggle error received */ - CHREASON_FRMOR, /* Frame overrun */ - CHREASON_CANCELLED /* Transfer cancelled */ -}; - -/* This structure retains the state of one host channel. NOTE: Since there - * is only one channel operation active at a time, some of the fields in - * in the structure could be moved in struct stm32_ubhost_s to achieve - * some memory savings. - */ - -struct stm32_chan_s -{ - sem_t waitsem; /* Channel wait semaphore */ - volatile uint8_t result; /* The result of the transfer */ - volatile uint8_t chreason; /* Channel halt reason. See enum stm32_chreason_e */ - uint8_t chidx; /* Channel index */ - uint8_t epno; /* Device endpoint number (0-127) */ - uint8_t eptype; /* See OTGHS_EPTYPE_* definitions */ - uint8_t funcaddr; /* Device function address */ - uint8_t speed; /* Device speed */ - uint8_t interval; /* Interrupt/isochronous EP polling interval */ - uint8_t pid; /* Data PID */ - uint8_t npackets; /* Number of packets (for data toggle) */ - bool inuse; /* True: This channel is "in use" */ - volatile bool indata1; /* IN data toggle. True: DATA01 (Bulk and INTR only) */ - volatile bool outdata1; /* OUT data toggle. True: DATA01 */ - bool in; /* True: IN endpoint */ - volatile bool waiter; /* True: Thread is waiting for a channel event */ - uint16_t maxpacket; /* Max packet size */ - uint16_t buflen; /* Buffer length (at start of transfer) */ - volatile uint16_t xfrd; /* Bytes transferred (at end of transfer) */ - volatile uint16_t inflight; /* Number of Tx bytes "in-flight" */ - uint8_t *buffer; /* Transfer buffer pointer */ -#ifdef CONFIG_USBHOST_ASYNCH - usbhost_asynch_t callback; /* Transfer complete callback */ - void *arg; /* Argument that accompanies the callback */ -#endif -}; - -/* A channel represents on uni-directional endpoint. So, in the case of the - * bi-directional, control endpoint, there must be two channels to represent - * the endpoint. - */ - -struct stm32_ctrlinfo_s -{ - uint8_t inndx; /* EP0 IN control channel index */ - uint8_t outndx; /* EP0 OUT control channel index */ -}; - -/* This structure retains the state of the USB host controller */ - -struct stm32_usbhost_s -{ - /* Common device fields. This must be the first thing defined in the - * structure so that it is possible to simply cast from struct usbhost_s - * to structstm32_usbhost_s. - */ - - struct usbhost_driver_s drvr; - - /* This is the hub port description understood by class drivers */ - - struct usbhost_roothubport_s rhport; - - /* Overall driver status */ - - volatile uint8_t smstate; /* The state of the USB host state machine */ - uint8_t chidx; /* ID of channel waiting for space in Tx FIFO */ - volatile bool connected; /* Connected to device */ - volatile bool change; /* Connection change */ - volatile bool pscwait; /* True: Thread is waiting for a port event */ - mutex_t lock; /* Support mutually exclusive access */ - sem_t pscsem; /* Semaphore to wait for a port event */ - struct stm32_ctrlinfo_s ep0; /* Root hub port EP0 description */ - -#ifdef CONFIG_USBHOST_HUB - /* Used to pass external hub port events */ - - volatile struct usbhost_hubport_s *hport; -#endif - - struct usbhost_devaddr_s devgen; /* Address generation data */ - - /* The state of each host channel */ - - struct stm32_chan_s chan[STM32_MAX_TX_FIFOS]; -}; - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -/* Register operations ******************************************************/ - -#ifdef CONFIG_STM32_USBHOST_REGDEBUG -static void stm32_printreg(uint32_t addr, uint32_t val, bool iswrite); -static void stm32_checkreg(uint32_t addr, uint32_t val, bool iswrite); -static uint32_t stm32_getreg(uint32_t addr); -static void stm32_putreg(uint32_t addr, uint32_t value); -#else -# define stm32_getreg(addr) getreg32(addr) -# define stm32_putreg(addr,val) putreg32(val,addr) -#endif - -static inline void stm32_modifyreg(uint32_t addr, uint32_t clrbits, - uint32_t setbits); - -#ifdef CONFIG_STM32_USBHOST_PKTDUMP -# define stm32_pktdump(m,b,n) lib_dumpbuffer(m,b,n) -#else -# define stm32_pktdump(m,b,n) -#endif - -/* Byte stream access helper functions **************************************/ - -static inline uint16_t stm32_getle16(const uint8_t *val); - -/* Channel management *******************************************************/ - -static int stm32_chan_alloc(struct stm32_usbhost_s *priv); -static inline void stm32_chan_free(struct stm32_usbhost_s *priv, - int chidx); -static inline void stm32_chan_freeall(struct stm32_usbhost_s *priv); -static void stm32_chan_configure(struct stm32_usbhost_s *priv, - int chidx); -static void stm32_chan_halt(struct stm32_usbhost_s *priv, int chidx, - enum stm32_chreason_e chreason); -static int stm32_chan_waitsetup(struct stm32_usbhost_s *priv, - struct stm32_chan_s *chan); -#ifdef CONFIG_USBHOST_ASYNCH -static int stm32_chan_asynchsetup(struct stm32_usbhost_s *priv, - struct stm32_chan_s *chan, - usbhost_asynch_t callback, void *arg); -#endif -static int stm32_chan_wait(struct stm32_usbhost_s *priv, - struct stm32_chan_s *chan); -static void stm32_chan_wakeup(struct stm32_usbhost_s *priv, - struct stm32_chan_s *chan); -static int stm32_ctrlchan_alloc(struct stm32_usbhost_s *priv, - uint8_t epno, uint8_t funcaddr, - uint8_t speed, - struct stm32_ctrlinfo_s *ctrlep); -static int stm32_ctrlep_alloc(struct stm32_usbhost_s *priv, - const struct usbhost_epdesc_s *epdesc, - usbhost_ep_t *ep); -static int stm32_xfrep_alloc(struct stm32_usbhost_s *priv, - const struct usbhost_epdesc_s *epdesc, - usbhost_ep_t *ep); - -/* Control/data transfer logic **********************************************/ - -static void stm32_transfer_start(struct stm32_usbhost_s *priv, - int chidx); -#if 0 /* Not used */ -static inline uint16_t stm32_getframe(void); -#endif -static int stm32_ctrl_sendsetup(struct stm32_usbhost_s *priv, - struct stm32_ctrlinfo_s *ep0, - const struct usb_ctrlreq_s *req); -static int stm32_ctrl_senddata(struct stm32_usbhost_s *priv, - struct stm32_ctrlinfo_s *ep0, - uint8_t *buffer, unsigned int buflen); -static int stm32_ctrl_recvdata(struct stm32_usbhost_s *priv, - struct stm32_ctrlinfo_s *ep0, - uint8_t *buffer, unsigned int buflen); -static int stm32_in_setup(struct stm32_usbhost_s *priv, int chidx); -static ssize_t stm32_in_transfer(struct stm32_usbhost_s *priv, int chidx, - uint8_t *buffer, size_t buflen); -#ifdef CONFIG_USBHOST_ASYNCH -static void stm32_in_next(struct stm32_usbhost_s *priv, - struct stm32_chan_s *chan); -static int stm32_in_asynch(struct stm32_usbhost_s *priv, int chidx, - uint8_t *buffer, size_t buflen, - usbhost_asynch_t callback, void *arg); -#endif -static int stm32_out_setup(struct stm32_usbhost_s *priv, int chidx); -static ssize_t stm32_out_transfer(struct stm32_usbhost_s *priv, - int chidx, uint8_t *buffer, - size_t buflen); -#ifdef CONFIG_USBHOST_ASYNCH -static void stm32_out_next(struct stm32_usbhost_s *priv, - struct stm32_chan_s *chan); -static int stm32_out_asynch(struct stm32_usbhost_s *priv, int chidx, - uint8_t *buffer, size_t buflen, - usbhost_asynch_t callback, void *arg); -#endif - -/* Interrupt handling *******************************************************/ - -/* Lower level interrupt handlers */ - -static void stm32_gint_wrpacket(struct stm32_usbhost_s *priv, - uint8_t *buffer, int chidx, int buflen); -static inline void stm32_gint_hcinisr(struct stm32_usbhost_s *priv, - int chidx); -static inline void stm32_gint_hcoutisr(struct stm32_usbhost_s *priv, - int chidx); -static void stm32_gint_connected(struct stm32_usbhost_s *priv); -static void stm32_gint_disconnected(struct stm32_usbhost_s *priv); - -/* Second level interrupt handlers */ - -#ifdef CONFIG_STM32_OTGHS_SOFINTR -static inline void stm32_gint_sofisr(struct stm32_usbhost_s *priv); -#endif -static inline void stm32_gint_rxflvlisr(struct stm32_usbhost_s *priv); -static inline void stm32_gint_nptxfeisr(struct stm32_usbhost_s *priv); -static inline void stm32_gint_ptxfeisr(struct stm32_usbhost_s *priv); -static inline void stm32_gint_hcisr(struct stm32_usbhost_s *priv); -static inline void stm32_gint_hprtisr(struct stm32_usbhost_s *priv); -static inline void stm32_gint_discisr(struct stm32_usbhost_s *priv); -static inline void stm32_gint_ipxfrisr(struct stm32_usbhost_s *priv); - -/* First level, global interrupt handler */ - -static int stm32_gint_isr(int irq, void *context, void *arg); - -/* Interrupt controls */ - -static void stm32_gint_enable(void); -static void stm32_gint_disable(void); -static inline void stm32_hostinit_enable(void); -static void stm32_txfe_enable(struct stm32_usbhost_s *priv, int chidx); - -/* USB host controller operations *******************************************/ - -static int stm32_wait(struct usbhost_connection_s *conn, - struct usbhost_hubport_s **hport); -static int stm32_rh_enumerate(struct stm32_usbhost_s *priv, - struct usbhost_connection_s *conn, - struct usbhost_hubport_s *hport); -static int stm32_enumerate(struct usbhost_connection_s *conn, - struct usbhost_hubport_s *hport); - -static int stm32_ep0configure(struct usbhost_driver_s *drvr, - usbhost_ep_t ep0, uint8_t funcaddr, - uint8_t speed, uint16_t maxpacketsize); -static int stm32_epalloc(struct usbhost_driver_s *drvr, - const struct usbhost_epdesc_s *epdesc, - usbhost_ep_t *ep); -static int stm32_epfree(struct usbhost_driver_s *drvr, usbhost_ep_t ep); -static int stm32_alloc(struct usbhost_driver_s *drvr, - uint8_t **buffer, size_t *maxlen); -static int stm32_free(struct usbhost_driver_s *drvr, - uint8_t *buffer); -static int stm32_ioalloc(struct usbhost_driver_s *drvr, - uint8_t **buffer, size_t buflen); -static int stm32_iofree(struct usbhost_driver_s *drvr, - uint8_t *buffer); -static int stm32_ctrlin(struct usbhost_driver_s *drvr, usbhost_ep_t ep0, - const struct usb_ctrlreq_s *req, - uint8_t *buffer); -static int stm32_ctrlout(struct usbhost_driver_s *drvr, usbhost_ep_t ep0, - const struct usb_ctrlreq_s *req, - const uint8_t *buffer); -static ssize_t stm32_transfer(struct usbhost_driver_s *drvr, - usbhost_ep_t ep, uint8_t *buffer, - size_t buflen); -#ifdef CONFIG_USBHOST_ASYNCH -static int stm32_asynch(struct usbhost_driver_s *drvr, usbhost_ep_t ep, - uint8_t *buffer, size_t buflen, - usbhost_asynch_t callback, void *arg); -#endif -static int stm32_cancel(struct usbhost_driver_s *drvr, usbhost_ep_t ep); -#ifdef CONFIG_USBHOST_HUB -static int stm32_connect(struct usbhost_driver_s *drvr, - struct usbhost_hubport_s *hport, - bool connected); -#endif -static void stm32_disconnect(struct usbhost_driver_s *drvr, - struct usbhost_hubport_s *hport); - -/* Initialization ***********************************************************/ - -static void stm32_portreset(struct stm32_usbhost_s *priv); -static void stm32_flush_txfifos(uint32_t txfnum); -static void stm32_flush_rxfifo(void); -static void stm32_vbusdrive(struct stm32_usbhost_s *priv, bool state); -static void stm32_host_initialize(struct stm32_usbhost_s *priv); - -static inline void stm32_sw_initialize(struct stm32_usbhost_s *priv); -static inline int stm32_hw_initialize(struct stm32_usbhost_s *priv); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* In this driver implementation, support is provided for only a single a - * single USB device. All status information can be simply retained in a - * single global instance. - */ - -static struct stm32_usbhost_s g_usbhost = -{ - .lock = NXMUTEX_INITIALIZER, - .pscsem = SEM_INITIALIZER(0), -}; - -/* This is the connection/enumeration interface */ - -static struct usbhost_connection_s g_usbconn = -{ - .wait = stm32_wait, - .enumerate = stm32_enumerate, -}; - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_printreg - * - * Description: - * Print the contents of an STM32xx register operation - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_USBHOST_REGDEBUG -static void stm32_printreg(uint32_t addr, uint32_t val, bool iswrite) -{ - uinfo("%08" PRIx32 "%s%08" PRIx32 "\n", addr, iswrite ? "<-" : "->", val); -} -#endif - -/**************************************************************************** - * Name: stm32_checkreg - * - * Description: - * Get the contents of an STM32 register - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_USBHOST_REGDEBUG -static void stm32_checkreg(uint32_t addr, uint32_t val, bool iswrite) -{ - static uint32_t prevaddr = 0; - static uint32_t preval = 0; - static uint32_t count = 0; - static bool prevwrite = false; - - /* Is this the same value that we read from/wrote to the same register - * last time? Are we polling the register? If so, suppress the output. - */ - - if (addr == prevaddr && val == preval && prevwrite == iswrite) - { - /* Yes.. Just increment the count */ - - count++; - } - else - { - /* No this is a new address or value or operation. Were there any - * duplicate accesses before this one? - */ - - if (count > 0) - { - /* Yes.. Just one? */ - - if (count == 1) - { - /* Yes.. Just one */ - - stm32_printreg(prevaddr, preval, prevwrite); - } - else - { - /* No.. More than one. */ - - uinfo("[repeats %d more times]\n", count); - } - } - - /* Save the new address, value, count, and operation for next time */ - - prevaddr = addr; - preval = val; - count = 0; - prevwrite = iswrite; - - /* Show the new regisgter access */ - - stm32_printreg(addr, val, iswrite); - } -} -#endif - -/**************************************************************************** - * Name: stm32_getreg - * - * Description: - * Get the contents of an STM32 register - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_USBHOST_REGDEBUG -static uint32_t stm32_getreg(uint32_t addr) -{ - /* Read the value from the register */ - - uint32_t val = getreg32(addr); - - /* Check if we need to print this value */ - - stm32_checkreg(addr, val, false); - return val; -} -#endif - -/**************************************************************************** - * Name: stm32_putreg - * - * Description: - * Set the contents of an STM32 register to a value - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_USBHOST_REGDEBUG -static void stm32_putreg(uint32_t addr, uint32_t val) -{ - /* Check if we need to print this value */ - - stm32_checkreg(addr, val, true); - - /* Write the value */ - - putreg32(val, addr); -} -#endif - -/**************************************************************************** - * Name: stm32_modifyreg - * - * Description: - * Modify selected bits of an STM32 register. - * - ****************************************************************************/ - -static inline void stm32_modifyreg(uint32_t addr, uint32_t clrbits, - uint32_t setbits) -{ - stm32_putreg(addr, (((stm32_getreg(addr)) & ~clrbits) | setbits)); -} - -/**************************************************************************** - * Name: stm32_getle16 - * - * Description: - * Get a (possibly unaligned) 16-bit little endian value. - * - ****************************************************************************/ - -static inline uint16_t stm32_getle16(const uint8_t *val) -{ - return (uint16_t)val[1] << 8 | (uint16_t)val[0]; -} - -/**************************************************************************** - * Name: stm32_chan_alloc - * - * Description: - * Allocate a channel. - * - ****************************************************************************/ - -static int stm32_chan_alloc(struct stm32_usbhost_s *priv) -{ - int chidx; - - /* Search the table of channels */ - - for (chidx = 0; chidx < STM32_NHOST_CHANNELS; chidx++) - { - /* Is this channel available? */ - - if (!priv->chan[chidx].inuse) - { - /* Yes... make it "in use" and return the index */ - - priv->chan[chidx].inuse = true; - return chidx; - } - } - - /* All of the channels are "in-use" */ - - return -EBUSY; -} - -/**************************************************************************** - * Name: stm32_chan_free - * - * Description: - * Free a previoiusly allocated channel. - * - ****************************************************************************/ - -static void stm32_chan_free(struct stm32_usbhost_s *priv, int chidx) -{ - DEBUGASSERT((unsigned)chidx < STM32_NHOST_CHANNELS); - - /* Halt the channel */ - - stm32_chan_halt(priv, chidx, CHREASON_FREED); - - /* Mark the channel available */ - - priv->chan[chidx].inuse = false; -} - -/**************************************************************************** - * Name: stm32_chan_freeall - * - * Description: - * Free all channels. - * - ****************************************************************************/ - -static inline void stm32_chan_freeall(struct stm32_usbhost_s *priv) -{ - uint8_t chidx; - - /* Free all host channels */ - - for (chidx = 2; chidx < STM32_NHOST_CHANNELS; chidx++) - { - stm32_chan_free(priv, chidx); - } -} - -/**************************************************************************** - * Name: stm32_chan_configure - * - * Description: - * Configure or re-configure a host channel. Host channels are configured - * when endpoint is allocated and EP0 (only) is re-configured with the - * max packet size or device address changes. - * - ****************************************************************************/ - -static void stm32_chan_configure(struct stm32_usbhost_s *priv, int chidx) -{ - struct stm32_chan_s *chan = &priv->chan[chidx]; - uint32_t regval; - - /* Clear any old pending interrupts for this host channel. */ - - stm32_putreg(STM32_OTGHS_HCINT(chidx), 0xffffffff); - - /* Enable channel interrupts required for transfers on this channel. */ - - regval = 0; - - switch (chan->eptype) - { - case OTGHS_EPTYPE_CTRL: - case OTGHS_EPTYPE_BULK: - { -#ifdef HAVE_USBHOST_TRACE_VERBOSE - uint16_t intrace; - uint16_t outtrace; - - /* Determine the definitive trace ID to use below */ - - if (chan->eptype == OTGHS_EPTYPE_CTRL) - { - intrace = OTGHS_VTRACE2_CHANCONF_CTRL_IN; - outtrace = OTGHS_VTRACE2_CHANCONF_CTRL_OUT; - } - else - { - intrace = OTGHS_VTRACE2_CHANCONF_BULK_IN; - outtrace = OTGHS_VTRACE2_CHANCONF_BULK_OUT; - } -#endif - - /* Interrupts required for CTRL and BULK endpoints */ - - regval |= (OTGHS_HCINT_XFRC | OTGHS_HCINT_STALL | OTGHS_HCINT_NAK | - OTGHS_HCINT_TXERR | OTGHS_HCINT_DTERR); - - /* Additional setting for IN/OUT endpoints */ - - if (chan->in) - { - usbhost_vtrace2(intrace, chidx, chan->epno); - regval |= OTGHS_HCINT_BBERR; - } - else - { - usbhost_vtrace2(outtrace, chidx, chan->epno); - regval |= OTGHS_HCINT_NYET; - } - } - break; - - case OTGHS_EPTYPE_INTR: - { - /* Interrupts required for INTR endpoints */ - - regval |= (OTGHS_HCINT_XFRC | OTGHS_HCINT_STALL | - OTGHS_HCINT_NAK | OTGHS_HCINT_TXERR | - OTGHS_HCINT_FRMOR | OTGHS_HCINT_DTERR); - - /* Additional setting for IN endpoints */ - - if (chan->in) - { - usbhost_vtrace2(OTGHS_VTRACE2_CHANCONF_INTR_IN, chidx, - chan->epno); - regval |= OTGHS_HCINT_BBERR; - } -#ifdef HAVE_USBHOST_TRACE_VERBOSE - else - { - usbhost_vtrace2(OTGHS_VTRACE2_CHANCONF_INTR_OUT, chidx, - chan->epno); - } -#endif - } - break; - - case OTGHS_EPTYPE_ISOC: - { - /* Interrupts required for ISOC endpoints */ - - regval |= OTGHS_HCINT_XFRC | OTGHS_HCINT_ACK | OTGHS_HCINT_FRMOR; - - /* Additional setting for IN endpoints */ - - if (chan->in) - { - usbhost_vtrace2(OTGHS_VTRACE2_CHANCONF_ISOC_IN, chidx, - chan->epno); - regval |= (OTGHS_HCINT_TXERR | OTGHS_HCINT_BBERR); - } -#ifdef HAVE_USBHOST_TRACE_VERBOSE - else - { - usbhost_vtrace2(OTGHS_VTRACE2_CHANCONF_ISOC_OUT, chidx, - chan->epno); - } -#endif - } - break; - } - - stm32_putreg(STM32_OTGHS_HCINTMSK(chidx), regval); - - /* Enable the top level host channel interrupt. */ - - stm32_modifyreg(STM32_OTGHS_HAINTMSK, 0, OTGHS_HAINT(chidx)); - - /* Make sure host channel interrupts are enabled. */ - - stm32_modifyreg(STM32_OTGHS_GINTMSK, 0, OTGHS_GINT_HC); - - /* Program the HCCHAR register */ - - regval = ((uint32_t)chan->maxpacket << OTGHS_HCCHAR_MPSIZ_SHIFT) | - ((uint32_t)chan->epno << OTGHS_HCCHAR_EPNUM_SHIFT) | - ((uint32_t)chan->eptype << OTGHS_HCCHAR_EPTYP_SHIFT) | - ((uint32_t)chan->funcaddr << OTGHS_HCCHAR_DAD_SHIFT); - - /* Special case settings for low speed devices */ - - if (chan->speed == USB_SPEED_LOW) - { - regval |= OTGHS_HCCHAR_LSDEV; - } - - /* Special case settings for IN endpoints */ - - if (chan->in) - { - regval |= OTGHS_HCCHAR_EPDIR_IN; - } - - /* Special case settings for INTR endpoints */ - - if (chan->eptype == OTGHS_EPTYPE_INTR) - { - regval |= OTGHS_HCCHAR_ODDFRM; - } - - /* Write the channel configuration */ - - stm32_putreg(STM32_OTGHS_HCCHAR(chidx), regval); -} - -/**************************************************************************** - * Name: stm32_chan_halt - * - * Description: - * Halt the channel associated with 'chidx' by setting the CHannel DISable - * (CHDIS) bit in in the HCCHAR register. - * - ****************************************************************************/ - -static void stm32_chan_halt(struct stm32_usbhost_s *priv, int chidx, - enum stm32_chreason_e chreason) -{ - uint32_t hcchar; - uint32_t intmsk; - uint32_t eptype; - unsigned int avail; - - /* Save the reason for the halt. We need this in the channel halt - * interrupt handling logic to know what to do next. - */ - - usbhost_vtrace2(OTGHS_VTRACE2_CHANHALT, chidx, chreason); - - priv->chan[chidx].chreason = (uint8_t)chreason; - - /* "The application can disable any channel by programming the - * OTG_HS_HCCHARx register with the CHDIS and CHENA bits set to 1. This - * enables the OTG_HS host to flush the posted requests (if any) and - * generates a channel halted interrupt. The application must wait for - * the CHH interrupt in OTG_HS_HCINTx before reallocating the channel for - * other transactions. The OTG_HS host does not interrupt the - * transaction that has already been started on the USB." - */ - - hcchar = stm32_getreg(STM32_OTGHS_HCCHAR(chidx)); - hcchar |= (OTGHS_HCCHAR_CHDIS | OTGHS_HCCHAR_CHENA); - - /* Get the endpoint type from the HCCHAR register */ - - eptype = hcchar & OTGHS_HCCHAR_EPTYP_MASK; - - /* Check for space in the Tx FIFO to issue the halt. - * - * "Before disabling a channel, the application must ensure that there is - * at least one free space available in the non-periodic request queue - * (when disabling a non-periodic channel) or the periodic request queue - * (when disabling a periodic channel). The application can simply flush - * the posted requests when the Request queue is full (before disabling - * the channel), by programming the OTG_HS_HCCHARx register with the - * CHDIS bit set to 1, and the CHENA bit cleared to 0." - */ - - if (eptype == OTGHS_HCCHAR_EPTYP_CTRL || - eptype == OTGHS_HCCHAR_EPTYP_BULK) - { - /* Get the number of words available in the non-periodic Tx FIFO. */ - - avail = stm32_getreg(STM32_OTGHS_HNPTXSTS) & - OTGHS_HNPTXSTS_NPTXFSAV_MASK; - } - else - { - /* Get the number of words available in the non-periodic Tx FIFO. */ - - avail = stm32_getreg(STM32_OTGHS_HPTXSTS) & - OTGHS_HPTXSTS_PTXFSAVL_MASK; - } - - /* Check if there is any space available in the Tx FIFO. */ - - if (avail == 0) - { - /* The Tx FIFO is full... disable the channel to flush the requests */ - - hcchar &= ~OTGHS_HCCHAR_CHENA; - } - - /* Unmask the CHannel Halted (CHH) interrupt */ - - intmsk = stm32_getreg(STM32_OTGHS_HCINTMSK(chidx)); - intmsk |= OTGHS_HCINT_CHH; - stm32_putreg(STM32_OTGHS_HCINTMSK(chidx), intmsk); - - /* Halt the channel by setting CHDIS (and maybe CHENA) in the HCCHAR */ - - stm32_putreg(STM32_OTGHS_HCCHAR(chidx), hcchar); -} - -/**************************************************************************** - * Name: stm32_chan_waitsetup - * - * Description: - * Set the request for the transfer complete event well BEFORE enabling - * the transfer (as soon as we are absolutely committed to the transfer). - * We do this to minimize race conditions. This logic would have to be - * expanded if we want to have more than one packet in flight at a time! - * - * Assumptions: - * Called from a normal thread context BEFORE the transfer has been - * started. - * - ****************************************************************************/ - -static int stm32_chan_waitsetup(struct stm32_usbhost_s *priv, - struct stm32_chan_s *chan) -{ - irqstate_t flags = enter_critical_section(); - int ret = -ENODEV; - - /* Is the device still connected? */ - - if (priv->connected) - { - /* Yes.. then set waiter to indicate that we expect to be informed - * when either (1) the device is disconnected, or (2) the transfer - * completed. - */ - - chan->waiter = true; -#ifdef CONFIG_USBHOST_ASYNCH - chan->callback = NULL; - chan->arg = NULL; -#endif - ret = OK; - } - - leave_critical_section(flags); - return ret; -} - -/**************************************************************************** - * Name: stm32_chan_asynchsetup - * - * Description: - * Set the request for the transfer complete event well BEFORE enabling - * the transfer (as soon as we are absolutely committed to the to avoid - * transfer). We do this to minimize race conditions. This logic would - * have to be expanded if we want to have more than one packet in flight - * at a time! - * - * Assumptions: - * Might be called from the level of an interrupt handler - * - ****************************************************************************/ - -#ifdef CONFIG_USBHOST_ASYNCH -static int stm32_chan_asynchsetup(struct stm32_usbhost_s *priv, - struct stm32_chan_s *chan, - usbhost_asynch_t callback, void *arg) -{ - irqstate_t flags = enter_critical_section(); - int ret = -ENODEV; - - /* Is the device still connected? */ - - if (priv->connected) - { - /* Yes.. then set waiter to indicate that we expect to be informed - * when either (1) the device is disconnected, or (2) the transfer - * completed. - */ - - chan->waiter = false; - chan->callback = callback; - chan->arg = arg; - ret = OK; - } - - leave_critical_section(flags); - return ret; -} -#endif - -/**************************************************************************** - * Name: stm32_chan_wait - * - * Description: - * Wait for a transfer on a channel to complete. - * - * Assumptions: - * Called from a normal thread context - * - ****************************************************************************/ - -static int stm32_chan_wait(struct stm32_usbhost_s *priv, - struct stm32_chan_s *chan) -{ - irqstate_t flags; - int ret; - - /* Disable interrupts so that the following operations will be atomic. On - * the OTG HS global interrupt needs to be disabled. However, here we - * disable all interrupts to exploit that fact that interrupts will be re- - * enabled while we wait. - */ - - flags = enter_critical_section(); - - /* Loop, testing for an end of transfer condition. The channel 'result' - * was set to EBUSY and 'waiter' was set to true before the transfer; - * 'waiter' will be set to false and 'result' will be set appropriately - * when the transfer is completed. - */ - - do - { - /* Wait for the transfer to complete. NOTE the transfer may already - * completed before we get here or the transfer may complete while we - * wait here. - */ - - nxsem_wait_uninterruptible(&chan->waitsem); - } - while (chan->waiter); - - /* The transfer is complete re-enable interrupts and return the result */ - - ret = -(int)chan->result; - leave_critical_section(flags); - return ret; -} - -/**************************************************************************** - * Name: stm32_chan_wakeup - * - * Description: - * A channel transfer has completed... wakeup any threads waiting for the - * transfer to complete. - * - * Assumptions: - * This function is called from the transfer complete interrupt handler for - * the channel. Interrupts are disabled. - * - ****************************************************************************/ - -static void stm32_chan_wakeup(struct stm32_usbhost_s *priv, - struct stm32_chan_s *chan) -{ - /* Is the transfer complete? */ - - if (chan->result != EBUSY) - { - /* Is there a thread waiting for this transfer to complete? */ - - if (chan->waiter) - { -#ifdef CONFIG_USBHOST_ASYNCH - /* Yes.. there should not also be a callback scheduled */ - - DEBUGASSERT(chan->callback == NULL); -#endif - /* Wake'em up! */ - - usbhost_vtrace2(chan->in ? OTGHS_VTRACE2_CHANWAKEUP_IN : - OTGHS_VTRACE2_CHANWAKEUP_OUT, - chan->epno, chan->result); - - nxsem_post(&chan->waitsem); - chan->waiter = false; - } - -#ifdef CONFIG_USBHOST_ASYNCH - /* No.. is an asynchronous callback expected when the transfer - * completes? - */ - - else if (chan->callback) - { - /* Handle continuation of IN/OUT pipes */ - - if (chan->in) - { - stm32_in_next(priv, chan); - } - else - { - stm32_out_next(priv, chan); - } - } -#endif - } -} - -/**************************************************************************** - * Name: stm32_ctrlchan_alloc - * - * Description: - * Allocate and configured channels for a control pipe. - * - ****************************************************************************/ - -static int stm32_ctrlchan_alloc(struct stm32_usbhost_s *priv, - uint8_t epno, uint8_t funcaddr, - uint8_t speed, - struct stm32_ctrlinfo_s *ctrlep) -{ - struct stm32_chan_s *chan; - int inndx; - int outndx; - - outndx = stm32_chan_alloc(priv); - if (outndx < 0) - { - return -ENOMEM; - } - - ctrlep->outndx = outndx; - chan = &priv->chan[outndx]; - chan->epno = epno; - chan->in = false; - chan->eptype = OTGHS_EPTYPE_CTRL; - chan->funcaddr = funcaddr; - chan->speed = speed; - chan->interval = 0; - chan->maxpacket = STM32_EP0_DEF_PACKET_SIZE; - chan->indata1 = false; - chan->outdata1 = false; - - /* Configure control OUT channels */ - - stm32_chan_configure(priv, outndx); - - /* Allocate and initialize the control IN channel */ - - inndx = stm32_chan_alloc(priv); - if (inndx < 0) - { - stm32_chan_free(priv, outndx); - return -ENOMEM; - } - - ctrlep->inndx = inndx; - chan = &priv->chan[inndx]; - chan->epno = epno; - chan->in = true; - chan->eptype = OTGHS_EPTYPE_CTRL; - chan->funcaddr = funcaddr; - chan->speed = speed; - chan->interval = 0; - chan->maxpacket = STM32_EP0_DEF_PACKET_SIZE; - chan->indata1 = false; - chan->outdata1 = false; - - /* Configure control IN channels */ - - stm32_chan_configure(priv, inndx); - return OK; -} - -/**************************************************************************** - * Name: stm32_ctrlep_alloc - * - * Description: - * Allocate a container and channels for control pipe. - * - * Input Parameters: - * priv - The private USB host driver state. - * epdesc - Describes the endpoint to be allocated. - * ep - A memory location provided by the caller in which to receive the - * allocated endpoint descriptor. - * - * Returned Value: - * On success, zero (OK) is returned. On a failure, a negated errno value - * is returned indicating the nature of the failure - * - * Assumptions: - * This function will *not* be called from an interrupt handler. - * - ****************************************************************************/ - -static int stm32_ctrlep_alloc(struct stm32_usbhost_s *priv, - const struct usbhost_epdesc_s *epdesc, - usbhost_ep_t *ep) -{ - struct usbhost_hubport_s *hport; - struct stm32_ctrlinfo_s *ctrlep; - int ret; - - /* Sanity check. NOTE that this method should only be called if a device - * is connected (because we need a valid low speed indication). - */ - - DEBUGASSERT(epdesc->hport != NULL); - hport = epdesc->hport; - - /* Allocate a container for the control endpoint */ - - ctrlep = (struct stm32_ctrlinfo_s *) - kmm_malloc(sizeof(struct stm32_ctrlinfo_s)); - if (ctrlep == NULL) - { - uerr("ERROR: Failed to allocate control endpoint container\n"); - return -ENOMEM; - } - - /* Then allocate and configure the IN/OUT channels */ - - ret = stm32_ctrlchan_alloc(priv, epdesc->addr & USB_EPNO_MASK, - hport->funcaddr, hport->speed, ctrlep); - if (ret < 0) - { - uerr("ERROR: stm32_ctrlchan_alloc failed: %d\n", ret); - kmm_free(ctrlep); - return ret; - } - - /* Return a pointer to the control pipe container as the pipe "handle" */ - - *ep = (usbhost_ep_t)ctrlep; - return OK; -} - -/**************************************************************************** - * Name: stm32_xfrep_alloc - * - * Description: - * Allocate and configure one unidirectional endpoint. - * - * Input Parameters: - * priv - The private USB host driver state. - * epdesc - Describes the endpoint to be allocated. - * ep - A memory location provided by the caller in which to receive the - * allocated endpoint descriptor. - * - * Returned Value: - * On success, zero (OK) is returned. On a failure, a negated errno value - * is returned indicating the nature of the failure - * - * Assumptions: - * This function will *not* be called from an interrupt handler. - * - ****************************************************************************/ - -static int stm32_xfrep_alloc(struct stm32_usbhost_s *priv, - const struct usbhost_epdesc_s *epdesc, - usbhost_ep_t *ep) -{ - struct usbhost_hubport_s *hport; - struct stm32_chan_s *chan; - int chidx; - - /* Sanity check. NOTE that this method should only be called if a device - * is connected (because we need a valid low speed indication). - */ - - DEBUGASSERT(epdesc->hport != NULL); - hport = epdesc->hport; - - /* Allocate a host channel for the endpoint */ - - chidx = stm32_chan_alloc(priv); - if (chidx < 0) - { - uerr("ERROR: Failed to allocate a host channel\n"); - return -ENOMEM; - } - - /* Decode the endpoint descriptor to initialize the channel data - * structures. Note: Here we depend on the fact that the endpoint - * point type is encoded in the same way in the endpoint descriptor as it - * is in the OTG HS hardware. - */ - - chan = &priv->chan[chidx]; - chan->epno = epdesc->addr & USB_EPNO_MASK; - chan->in = epdesc->in; - chan->eptype = epdesc->xfrtype; - chan->funcaddr = hport->funcaddr; - chan->speed = hport->speed; - chan->interval = epdesc->interval; - chan->maxpacket = epdesc->mxpacketsize; - chan->indata1 = false; - chan->outdata1 = false; - - /* Then configure the endpoint */ - - stm32_chan_configure(priv, chidx); - - /* Return the index to the allocated channel as the endpoint "handle" */ - - *ep = (usbhost_ep_t)chidx; - return OK; -} - -/**************************************************************************** - * Name: stm32_transfer_start - * - * Description: - * Start at transfer on the select IN or OUT channel. - * - ****************************************************************************/ - -static void stm32_transfer_start(struct stm32_usbhost_s *priv, int chidx) -{ - struct stm32_chan_s *chan; - uint32_t regval; - unsigned int npackets; - unsigned int maxpacket; - unsigned int avail; - unsigned int wrsize; - unsigned int minsize; - - /* Set up the initial state of the transfer */ - - chan = &priv->chan[chidx]; - - usbhost_vtrace2(OTGHS_VTRACE2_STARTTRANSFER, chidx, chan->buflen); - - chan->result = EBUSY; - chan->inflight = 0; - chan->xfrd = 0; - priv->chidx = chidx; - - /* Compute the expected number of packets associated to the transfer. - * If the transfer length is zero (or less than the size of one maximum - * size packet), then one packet is expected. - */ - - /* If the transfer size is greater than one packet, then calculate the - * number of packets that will be received/sent, including any partial - * final packet. - */ - - maxpacket = chan->maxpacket; - - if (chan->buflen > maxpacket) - { - npackets = (chan->buflen + maxpacket - 1) / maxpacket; - - /* Clip if the buffer length if it exceeds the maximum number of - * packets that can be transferred (this should not happen). - */ - - if (npackets > STM32_MAX_PKTCOUNT) - { - npackets = STM32_MAX_PKTCOUNT; - chan->buflen = STM32_MAX_PKTCOUNT * maxpacket; - usbhost_trace2(OTGHS_TRACE2_CLIP, chidx, chan->buflen); - } - } - else - { - /* One packet will be sent/received (might be a zero length packet) */ - - npackets = 1; - } - - /* If it is an IN transfer, then adjust the size of the buffer UP to - * a full number of packets. Hmmm... couldn't this cause an overrun - * into unallocated memory? - */ - -#if 0 /* Think about this */ - if (chan->in) - { - /* Force the buffer length to an even multiple of maxpacket */ - - chan->buflen = npackets * maxpacket; - } -#endif - - /* Save the number of packets in the transfer. We will need this in - * order to set the next data toggle correctly when the transfer - * completes. - */ - - chan->npackets = (uint8_t)npackets; - - /* Setup the HCTSIZn register */ - - regval = ((uint32_t)chan->buflen << OTGHS_HCTSIZ_XFRSIZ_SHIFT) | - ((uint32_t)npackets << OTGHS_HCTSIZ_PKTCNT_SHIFT) | - ((uint32_t)chan->pid << OTGHS_HCTSIZ_DPID_SHIFT); - stm32_putreg(STM32_OTGHS_HCTSIZ(chidx), regval); - - /* Setup the HCCHAR register: Frame oddness and host channel enable */ - - regval = stm32_getreg(STM32_OTGHS_HCCHAR(chidx)); - - /* Set/clear the Odd Frame bit. Check for an even frame; if so set Odd - * Frame. This field is applicable for only periodic (isochronous and - * interrupt) channels. - */ - - if ((stm32_getreg(STM32_OTGHS_HFNUM) & 1) == 0) - { - regval |= OTGHS_HCCHAR_ODDFRM; - } - else - { - regval &= ~OTGHS_HCCHAR_ODDFRM; - } - - regval &= ~OTGHS_HCCHAR_CHDIS; - regval |= OTGHS_HCCHAR_CHENA; - stm32_putreg(STM32_OTGHS_HCCHAR(chidx), regval); - - /* If this is an out transfer, then we need to do more.. we need to copy - * the outgoing data into the correct TxFIFO. - */ - - if (!chan->in && chan->buflen > 0) - { - /* Handle non-periodic (CTRL and BULK) OUT transfers differently than - * periodic (INTR and ISOC) OUT transfers. - */ - - minsize = MIN(chan->buflen, chan->maxpacket); - - switch (chan->eptype) - { - case OTGHS_EPTYPE_CTRL: /* Non periodic transfer */ - case OTGHS_EPTYPE_BULK: - { - /* Read the Non-periodic Tx FIFO status register */ - - regval = stm32_getreg(STM32_OTGHS_HNPTXSTS); - avail = ((regval & OTGHS_HNPTXSTS_NPTXFSAV_MASK) >> - OTGHS_HNPTXSTS_NPTXFSAV_SHIFT) << 2; - } - break; - - /* Periodic transfer */ - - case OTGHS_EPTYPE_INTR: - case OTGHS_EPTYPE_ISOC: - { - /* Read the Non-periodic Tx FIFO status register */ - - regval = stm32_getreg(STM32_OTGHS_HPTXSTS); - avail = ((regval & OTGHS_HPTXSTS_PTXFSAVL_MASK) >> - OTGHS_HPTXSTS_PTXFSAVL_SHIFT) << 2; - } - break; - - default: - DEBUGPANIC(); - return; - } - - /* Is there space in the TxFIFO to hold the minimum size packet? */ - - if (minsize <= avail) - { - /* Yes.. Get the size of the biggest thing that we can put - * in the Tx FIFO now - */ - - wrsize = chan->buflen; - if (wrsize > avail) - { - /* Clip the write size to the number of full, max sized packets - * that will fit in the Tx FIFO. - */ - - unsigned int wrpackets = avail / chan->maxpacket; - wrsize = wrpackets * chan->maxpacket; - } - - /* Write packet into the Tx FIFO. */ - - stm32_gint_wrpacket(priv, chan->buffer, chidx, wrsize); - } - - /* Did we put the entire buffer into the Tx FIFO? */ - - if (chan->buflen > avail) - { - /* No, there was insufficient space to hold the entire transfer ... - * Enable the Tx FIFO interrupt to handle the transfer when the Tx - * FIFO becomes empty. - */ - - stm32_txfe_enable(priv, chidx); - } - } -} - -/**************************************************************************** - * Name: stm32_getframe - * - * Description: - * Get the current frame number. The frame number (FRNUM) field increments - * when a new SOF is transmitted on the USB, and is cleared to 0 when it - * reaches 0x3fff. - * - ****************************************************************************/ - -#if 0 /* Not used */ -static inline uint16_t stm32_getframe(void) -{ - return (uint16_t) - (stm32_getreg(STM32_OTGHS_HFNUM) & OTGHS_HFNUM_FRNUM_MASK); -} -#endif - -/**************************************************************************** - * Name: stm32_ctrl_sendsetup - * - * Description: - * Send an IN/OUT SETUP packet. - * - ****************************************************************************/ - -static int stm32_ctrl_sendsetup(struct stm32_usbhost_s *priv, - struct stm32_ctrlinfo_s *ep0, - const struct usb_ctrlreq_s *req) -{ - struct stm32_chan_s *chan; - clock_t start; - clock_t elapsed; - int ret; - - /* Loop while the device reports NAK (and a timeout is not exceeded */ - - chan = &priv->chan[ep0->outndx]; - start = clock_systime_ticks(); - - do - { - /* Send the SETUP packet */ - - chan->pid = OTGHS_PID_SETUP; - chan->buffer = (uint8_t *)req; - chan->buflen = USB_SIZEOF_CTRLREQ; - chan->xfrd = 0; - - /* Set up for the wait BEFORE starting the transfer */ - - ret = stm32_chan_waitsetup(priv, chan); - if (ret < 0) - { - usbhost_trace1(OTGHS_TRACE1_DEVDISCONN, 0); - return ret; - } - - /* Start the transfer */ - - stm32_transfer_start(priv, ep0->outndx); - - /* Wait for the transfer to complete */ - - ret = stm32_chan_wait(priv, chan); - - /* Return on success and for all failures other than EAGAIN. EAGAIN - * means that the device NAKed the SETUP command and that we should - * try a few more times. - */ - - if (ret != -EAGAIN) - { - /* Output some debug information if the transfer failed */ - - if (ret < 0) - { - usbhost_trace1(OTGHS_TRACE1_TRNSFRFAILED, ret); - } - - /* Return the result in any event */ - - return ret; - } - - /* Get the elapsed time (in frames) */ - - elapsed = clock_systime_ticks() - start; - } - while (elapsed < STM32_SETUP_DELAY); - - return -ETIMEDOUT; -} - -/**************************************************************************** - * Name: stm32_ctrl_senddata - * - * Description: - * Send data in the data phase of an OUT control transfer. Or send status - * in the status phase of an IN control transfer - * - ****************************************************************************/ - -static int stm32_ctrl_senddata(struct stm32_usbhost_s *priv, - struct stm32_ctrlinfo_s *ep0, - uint8_t *buffer, unsigned int buflen) -{ - struct stm32_chan_s *chan = &priv->chan[ep0->outndx]; - int ret; - - /* Save buffer information */ - - chan->buffer = buffer; - chan->buflen = buflen; - chan->xfrd = 0; - - /* Set the DATA PID */ - - if (buflen == 0) - { - /* For status OUT stage with buflen == 0, set PID DATA1 */ - - chan->outdata1 = true; - } - - /* Set the Data PID as per the outdata1 boolean */ - - chan->pid = chan->outdata1 ? OTGHS_PID_DATA1 : OTGHS_PID_DATA0; - - /* Set up for the wait BEFORE starting the transfer */ - - ret = stm32_chan_waitsetup(priv, chan); - if (ret < 0) - { - usbhost_trace1(OTGHS_TRACE1_DEVDISCONN, 0); - return ret; - } - - /* Start the transfer */ - - stm32_transfer_start(priv, ep0->outndx); - - /* Wait for the transfer to complete and return the result */ - - return stm32_chan_wait(priv, chan); -} - -/**************************************************************************** - * Name: stm32_ctrl_recvdata - * - * Description: - * Receive data in the data phase of an IN control transfer. Or receive - * status in the status phase of an OUT control transfer - * - ****************************************************************************/ - -static int stm32_ctrl_recvdata(struct stm32_usbhost_s *priv, - struct stm32_ctrlinfo_s *ep0, - uint8_t *buffer, unsigned int buflen) -{ - struct stm32_chan_s *chan = &priv->chan[ep0->inndx]; - int ret; - - /* Save buffer information */ - - chan->pid = OTGHS_PID_DATA1; - chan->buffer = buffer; - chan->buflen = buflen; - chan->xfrd = 0; - - /* Set up for the wait BEFORE starting the transfer */ - - ret = stm32_chan_waitsetup(priv, chan); - if (ret < 0) - { - usbhost_trace1(OTGHS_TRACE1_DEVDISCONN, 0); - return ret; - } - - /* Start the transfer */ - - stm32_transfer_start(priv, ep0->inndx); - - /* Wait for the transfer to complete and return the result */ - - return stm32_chan_wait(priv, chan); -} - -/**************************************************************************** - * Name: stm32_in_setup - * - * Description: - * Initiate an IN transfer on an bulk, interrupt, or isochronous pipe. - * - ****************************************************************************/ - -static int stm32_in_setup(struct stm32_usbhost_s *priv, int chidx) -{ - struct stm32_chan_s *chan; - - /* Set up for the transfer based on the direction and the endpoint type */ - - chan = &priv->chan[chidx]; - switch (chan->eptype) - { - default: - case OTGHS_EPTYPE_CTRL: /* Control */ - { - /* This kind of transfer on control endpoints other than EP0 are not - * currently supported - */ - - return -ENOSYS; - } - - case OTGHS_EPTYPE_ISOC: /* Isochronous */ - { - /* Set up the IN data PID */ - - usbhost_vtrace2(OTGHS_VTRACE2_ISOCIN, chidx, chan->buflen); - chan->pid = OTGHS_PID_DATA0; - } - break; - - case OTGHS_EPTYPE_BULK: /* Bulk */ - { - /* Setup the IN data PID */ - - usbhost_vtrace2(OTGHS_VTRACE2_BULKIN, chidx, chan->buflen); - chan->pid = chan->indata1 ? OTGHS_PID_DATA1 : OTGHS_PID_DATA0; - } - break; - - case OTGHS_EPTYPE_INTR: /* Interrupt */ - { - /* Setup the IN data PID */ - - usbhost_vtrace2(OTGHS_VTRACE2_INTRIN, chidx, chan->buflen); - chan->pid = chan->indata1 ? OTGHS_PID_DATA1 : OTGHS_PID_DATA0; - } - break; - } - - /* Start the transfer */ - - stm32_transfer_start(priv, chidx); - return OK; -} - -/**************************************************************************** - * Name: stm32_in_transfer - * - * Description: - * Transfer 'buflen' bytes into 'buffer' from an IN channel. - * - ****************************************************************************/ - -static ssize_t stm32_in_transfer(struct stm32_usbhost_s *priv, int chidx, - uint8_t *buffer, size_t buflen) -{ - struct stm32_chan_s *chan; - clock_t start; - ssize_t xfrd; - int ret; - - /* Loop until the transfer completes (i.e., buflen is decremented to zero) - * or a fatal error occurs any error other than a simple NAK. NAK would - * simply indicate the end of the transfer (short-transfer). - */ - - chan = &priv->chan[chidx]; - chan->buffer = buffer; - chan->buflen = buflen; - chan->xfrd = 0; - xfrd = 0; - - start = clock_systime_ticks(); - while (chan->xfrd < chan->buflen) - { - /* Set up for the wait BEFORE starting the transfer */ - - ret = stm32_chan_waitsetup(priv, chan); - if (ret < 0) - { - usbhost_trace1(OTGHS_TRACE1_DEVDISCONN, 0); - return (ssize_t)ret; - } - - /* Set up for the transfer based on the direction and the endpoint */ - - ret = stm32_in_setup(priv, chidx); - if (ret < 0) - { - uerr("ERROR: stm32_in_setup failed: %d\n", ret); - return (ssize_t)ret; - } - - /* Wait for the transfer to complete and get the result */ - - ret = stm32_chan_wait(priv, chan); - - /* EAGAIN indicates that the device NAKed the transfer. */ - - if (ret < 0) - { - /* The transfer failed. If we received a NAK, return all data - * buffered so far (if any). - */ - - if (ret == -EAGAIN) - { - /* Was data buffered prior to the NAK? */ - - if (xfrd > 0) - { - /* Yes, return the amount of data received. - * - * REVISIT: This behavior is clearly correct for CDC/ACM - * bulk transfers and HID interrupt transfers. But I am - * not so certain for MSC bulk transfers which, I think, - * could have NAKed packets in the middle of a transfer. - */ - - return xfrd; - } - else - { - useconds_t delay; - - /* Get the elapsed time. Has the timeout elapsed? - * if not then try again. - */ - - clock_t elapsed = clock_systime_ticks() - start; - if (elapsed >= STM32_DATANAK_DELAY) - { - /* Timeout out... break out returning the NAK as - * as a failure. - */ - - return (ssize_t)ret; - } - - /* Wait a bit before retrying after a NAK. */ - - if (chan->eptype == OTGFS_EPTYPE_INTR) - { - /* For interrupt (and isochronous) endpoints, the - * polling rate is determined by the bInterval field - * of the endpoint descriptor (in units of frames - * which we treat as milliseconds here). - */ - - if (chan->interval > 0) - { - /* Convert the delay to units of microseconds */ - - delay = (useconds_t)chan->interval * 1000; - } - else - { - /* Out of range! For interrupt endpoints, the valid - * range is 1-255 frames. Assume one frame. - */ - - delay = 1000; - } - } - else - { - /* For Isochronous endpoints, bInterval must be 1. - * Bulk endpoints do not have a polling interval. - * Rather, the should wait until data is received. - * - * REVISIT: For bulk endpoints this 1 msec delay is - * only intended to give the CPU a break from the bulk - * EP tight polling loop. But are there performance - * issues? - */ - - delay = 1000; - } - - /* Wait for the next polling interval. For interrupt and - * isochronous endpoints, this is necessary to assure the - * polling interval. It is used in other cases only to - * prevent the polling from consuming too much CPU - * bandwidth. - * - * Small delays could require more resolution than is - * provided by the system timer. For example, if the - * system timer resolution is 10MS, then - * nxsched_usleep(1000) will actually request a delay 20MS - * (due to both quantization and rounding). - * - * REVISIT: So which is better? To ignore tiny delays and - * hog the system bandwidth? Or to wait for an excessive - * amount and destroy system throughput? - */ - - if (delay > CONFIG_USEC_PER_TICK) - { - nxsched_usleep(delay - CONFIG_USEC_PER_TICK); - } - } - } - else - { - /* Some unexpected, fatal error occurred. */ - - usbhost_trace1(OTGHS_TRACE1_TRNSFRFAILED, ret); - - /* Break out and return the error */ - - uerr("ERROR: stm32_chan_wait failed: %d\n", ret); - return (ssize_t)ret; - } - } - else - { - /* Successfully received another chunk of data... add that to the - * running total. Then continue reading until we read 'buflen' - * bytes of data or until the devices NAKs (implying a short - * packet). - */ - - xfrd += chan->xfrd; - } - } - - return xfrd; -} - -/**************************************************************************** - * Name: stm32_in_next - * - * Description: - * Initiate the next of a sequence of asynchronous transfers. - * - * Assumptions: - * This function is always called from an interrupt handler - * - ****************************************************************************/ - -#ifdef CONFIG_USBHOST_ASYNCH -static void stm32_in_next(struct stm32_usbhost_s *priv, - struct stm32_chan_s *chan) -{ - usbhost_asynch_t callback; - void *arg; - ssize_t nbytes; - int result; - int ret; - - /* Is the full transfer complete? Did the last chunk transfer OK? */ - - result = -(int)chan->result; - if (chan->xfrd < chan->buflen && result == OK) - { - /* Yes.. Set up for the next transfer based on the direction and the - * endpoint type - */ - - ret = stm32_in_setup(priv, chan->chidx); - if (ret >= 0) - { - return; - } - - uerr("ERROR: stm32_in_setup failed: %d\n", ret); - result = ret; - } - - /* The transfer is complete, with or without an error */ - - uinfo("Transfer complete: %d\n", result); - - /* Extract the callback information */ - - callback = chan->callback; - arg = chan->arg; - nbytes = chan->xfrd; - - chan->callback = NULL; - chan->arg = NULL; - chan->xfrd = 0; - - /* Then perform the callback */ - - if (result < 0) - { - nbytes = (ssize_t)result; - } - - callback(arg, nbytes); -} -#endif - -/**************************************************************************** - * Name: stm32_in_asynch - * - * Description: - * Initiate the first of a sequence of asynchronous transfers. - * - * Assumptions: - * This function is never called from an interrupt handler - * - ****************************************************************************/ - -#ifdef CONFIG_USBHOST_ASYNCH -static int stm32_in_asynch(struct stm32_usbhost_s *priv, int chidx, - uint8_t *buffer, size_t buflen, - usbhost_asynch_t callback, void *arg) -{ - struct stm32_chan_s *chan; - int ret; - - /* Set up for the transfer BEFORE starting the first transfer */ - - chan = &priv->chan[chidx]; - chan->buffer = buffer; - chan->buflen = buflen; - chan->xfrd = 0; - - ret = stm32_chan_asynchsetup(priv, chan, callback, arg); - if (ret < 0) - { - uerr("ERROR: stm32_chan_asynchsetup failed: %d\n", ret); - return ret; - } - - /* Set up for the transfer based on the direction and the endpoint type */ - - ret = stm32_in_setup(priv, chidx); - if (ret < 0) - { - uerr("ERROR: stm32_in_setup failed: %d\n", ret); - } - - /* And return with the transfer pending */ - - return ret; -} -#endif - -/**************************************************************************** - * Name: stm32_out_setup - * - * Description: - * Initiate an OUT transfer on an bulk, interrupt, or isochronous pipe. - * - ****************************************************************************/ - -static int stm32_out_setup(struct stm32_usbhost_s *priv, int chidx) -{ - struct stm32_chan_s *chan; - - /* Set up for the transfer based on the direction and the endpoint type */ - - chan = &priv->chan[chidx]; - switch (chan->eptype) - { - default: - case OTGHS_EPTYPE_CTRL: /* Control */ - { - /* This kind of transfer on control endpoints other than EP0 are not - * currently supported - */ - - return -ENOSYS; - } - - case OTGHS_EPTYPE_ISOC: /* Isochronous */ - { - /* Set up the OUT data PID */ - - usbhost_vtrace2(OTGHS_VTRACE2_ISOCOUT, chidx, chan->buflen); - chan->pid = OTGHS_PID_DATA0; - } - break; - - case OTGHS_EPTYPE_BULK: /* Bulk */ - { - /* Setup the OUT data PID */ - - usbhost_vtrace2(OTGHS_VTRACE2_BULKOUT, chidx, chan->buflen); - chan->pid = chan->outdata1 ? OTGHS_PID_DATA1 : OTGHS_PID_DATA0; - } - break; - - case OTGHS_EPTYPE_INTR: /* Interrupt */ - { - /* Setup the OUT data PID */ - - usbhost_vtrace2(OTGHS_VTRACE2_INTROUT, chidx, chan->buflen); - chan->pid = chan->outdata1 ? OTGHS_PID_DATA1 : OTGHS_PID_DATA0; - - /* Toggle the OUT data PID for the next transfer */ - - chan->outdata1 ^= true; - } - break; - } - - /* Start the transfer */ - - stm32_transfer_start(priv, chidx); - return OK; -} - -/**************************************************************************** - * Name: stm32_out_transfer - * - * Description: - * Transfer the 'buflen' bytes in 'buffer' through an OUT channel. - * - ****************************************************************************/ - -static ssize_t stm32_out_transfer(struct stm32_usbhost_s *priv, - int chidx, uint8_t *buffer, - size_t buflen) -{ - struct stm32_chan_s *chan; - clock_t start; - clock_t elapsed; - size_t xfrlen; - ssize_t xfrd; - int ret; - bool zlp; - - /* Loop until the transfer completes (i.e., buflen is decremented to zero) - * or a fatal error occurs (any error other than a simple NAK) - */ - - chan = &priv->chan[chidx]; - start = clock_systime_ticks(); - xfrd = 0; - zlp = (buflen == 0); - - while (buflen > 0 || zlp) - { - /* Transfer one packet at a time. The hardware is capable of queueing - * multiple OUT packets, but I just haven't figured out how to handle - * the case where a single OUT packet in the group is NAKed. - */ - - xfrlen = MIN(chan->maxpacket, buflen); - chan->buffer = buffer; - chan->buflen = xfrlen; - chan->xfrd = 0; - - /* Set up for the wait BEFORE starting the transfer */ - - ret = stm32_chan_waitsetup(priv, chan); - if (ret < 0) - { - usbhost_trace1(OTGHS_TRACE1_DEVDISCONN, 0); - return (ssize_t)ret; - } - - /* Set up for the transfer based on the direction and the endpoint */ - - ret = stm32_out_setup(priv, chidx); - if (ret < 0) - { - uerr("ERROR: stm32_out_setup failed: %d\n", ret); - return (ssize_t)ret; - } - - /* Wait for the transfer to complete and get the result */ - - ret = stm32_chan_wait(priv, chan); - - /* Handle transfer failures */ - - if (ret < 0) - { - usbhost_trace1(OTGHS_TRACE1_TRNSFRFAILED, ret); - - /* Check for a special case: If (1) the transfer was NAKed and (2) - * no Tx FIFO empty or Rx FIFO not-empty event occurred, then we - * should be able to just flush the Rx and Tx FIFOs and try again. - * We can detect this latter case because then the transfer buffer - * pointer and buffer size will be unaltered. - */ - - elapsed = clock_systime_ticks() - start; - if (ret != -EAGAIN || /* Not a NAK condition OR */ - elapsed >= STM32_DATANAK_DELAY || /* Timeout has elapsed OR */ - chan->xfrd > 0) /* Data has been partially transferred */ - { - /* Break out and return the error */ - - uerr("ERROR: stm32_chan_wait failed: %d\n", ret); - return (ssize_t)ret; - } - - /* Is this flush really necessary? What does the hardware do with - * the data in the FIFO when the NAK occurs? Does it discard it? - */ - - stm32_flush_txfifos(OTGHS_GRSTCTL_TXFNUM_HALL); - - /* Get the device a little time to catch up. Then retry the - * transfer using the same buffer pointer and length. - */ - - nxsched_usleep(20 * 1000); - } - else - { - /* Successfully transferred. Update the buffer pointer/length */ - - buffer += xfrlen; - buflen -= xfrlen; - xfrd += chan->xfrd; - zlp = false; - } - } - - return xfrd; -} - -/**************************************************************************** - * Name: stm32_out_next - * - * Description: - * Initiate the next of a sequence of asynchronous transfers. - * - * Assumptions: - * This function is always called from an interrupt handler - * - ****************************************************************************/ - -#ifdef CONFIG_USBHOST_ASYNCH -static void stm32_out_next(struct stm32_usbhost_s *priv, - struct stm32_chan_s *chan) -{ - usbhost_asynch_t callback; - void *arg; - ssize_t nbytes; - int result; - int ret; - - /* Is the full transfer complete? Did the last chunk transfer OK? */ - - result = -(int)chan->result; - if (chan->xfrd < chan->buflen && result == OK) - { - /* Yes.. Set up for the next transfer based on the direction and the - * endpoint type - */ - - ret = stm32_out_setup(priv, chan->chidx); - if (ret >= 0) - { - return; - } - - uerr("ERROR: stm32_out_setup failed: %d\n", ret); - result = ret; - } - - /* The transfer is complete, with or without an error */ - - uinfo("Transfer complete: %d\n", result); - - /* Extract the callback information */ - - callback = chan->callback; - arg = chan->arg; - nbytes = chan->xfrd; - - chan->callback = NULL; - chan->arg = NULL; - chan->xfrd = 0; - - /* Then perform the callback */ - - if (result < 0) - { - nbytes = (ssize_t)result; - } - - callback(arg, nbytes); -} -#endif - -/**************************************************************************** - * Name: stm32_out_asynch - * - * Description: - * Initiate the first of a sequence of asynchronous transfers. - * - * Assumptions: - * This function is never called from an interrupt handler - * - ****************************************************************************/ - -#ifdef CONFIG_USBHOST_ASYNCH -static int stm32_out_asynch(struct stm32_usbhost_s *priv, int chidx, - uint8_t *buffer, size_t buflen, - usbhost_asynch_t callback, void *arg) -{ - struct stm32_chan_s *chan; - int ret; - - /* Set up for the transfer BEFORE starting the first transfer */ - - chan = &priv->chan[chidx]; - chan->buffer = buffer; - chan->buflen = buflen; - chan->xfrd = 0; - - ret = stm32_chan_asynchsetup(priv, chan, callback, arg); - if (ret < 0) - { - uerr("ERROR: stm32_chan_asynchsetup failed: %d\n", ret); - return ret; - } - - /* Set up for the transfer based on the direction and the endpoint type */ - - ret = stm32_out_setup(priv, chidx); - if (ret < 0) - { - uerr("ERROR: stm32_out_setup failed: %d\n", ret); - } - - /* And return with the transfer pending */ - - return ret; -} -#endif - -/**************************************************************************** - * Name: stm32_gint_wrpacket - * - * Description: - * Transfer the 'buflen' bytes in 'buffer' to the Tx FIFO associated with - * 'chidx' (non-DMA). - * - ****************************************************************************/ - -static void stm32_gint_wrpacket(struct stm32_usbhost_s *priv, - uint8_t *buffer, int chidx, int buflen) -{ - uint32_t *src; - uint32_t fifo; - int buflen32; - - stm32_pktdump("Sending", buffer, buflen); - - /* Get the number of 32-byte words associated with this byte size */ - - buflen32 = (buflen + 3) >> 2; - - /* Get the address of the Tx FIFO associated with this channel */ - - fifo = STM32_OTGHS_DFIFO_HCH(chidx); - - /* Transfer all of the data into the Tx FIFO */ - - src = (uint32_t *)buffer; - for (; buflen32 > 0; buflen32--) - { - uint32_t data = *src++; - stm32_putreg(fifo, data); - } - - /* Increment the count of bytes "in-flight" in the Tx FIFO */ - - priv->chan[chidx].inflight += buflen; -} - -/**************************************************************************** - * Name: stm32_gint_hcinisr - * - * Description: - * USB OTG HS host IN channels interrupt handler - * - * One the completion of the transfer, the channel result byte may be set - * as follows: - * - * OK - Transfer completed successfully - * EAGAIN - If devices NAKs the transfer or NYET occurs - * EPERM - If the endpoint stalls - * EIO - On a TX or data toggle error - * EPIPE - Frame overrun - * - * EBUSY in the result field indicates that the transfer has not completed. - * - ****************************************************************************/ - -static inline void stm32_gint_hcinisr(struct stm32_usbhost_s *priv, - int chidx) -{ - struct stm32_chan_s *chan = &priv->chan[chidx]; - uint32_t regval; - uint32_t pending; - - /* Read the HCINT register to get the pending HC interrupts. Read the - * HCINTMSK register to get the set of enabled HC interrupts. - */ - - pending = stm32_getreg(STM32_OTGHS_HCINT(chidx)); - regval = stm32_getreg(STM32_OTGHS_HCINTMSK(chidx)); - - /* AND the two to get the set of enabled, pending HC interrupts */ - - pending &= regval; - uinfo("HCINTMSK%d: %08" PRIx32 " pending: %08" PRIx32 "\n", - chidx, regval, pending); - - /* Check for a pending ACK response received/transmitted interrupt */ - - if ((pending & OTGHS_HCINT_ACK) != 0) - { - /* Clear the pending the ACK response received/transmitted interrupt */ - - stm32_putreg(STM32_OTGHS_HCINT(chidx), OTGHS_HCINT_ACK); - } - - /* Check for a pending STALL response receive (STALL) interrupt */ - - else if ((pending & OTGHS_HCINT_STALL) != 0) - { - /* Clear the NAK and STALL Conditions. */ - - stm32_putreg(STM32_OTGHS_HCINT(chidx), - OTGHS_HCINT_NAK | OTGHS_HCINT_STALL); - - /* Halt the channel when a STALL, TXERR, BBERR or DTERR interrupt is - * received on the channel. - */ - - stm32_chan_halt(priv, chidx, CHREASON_STALL); - - /* When there is a STALL, clear any pending NAK so that it is not - * processed below. - */ - - pending &= ~OTGHS_HCINT_NAK; - } - - /* Check for a pending Data Toggle ERRor (DTERR) interrupt */ - - else if ((pending & OTGHS_HCINT_DTERR) != 0) - { - /* Halt the channel when a STALL, TXERR, BBERR or DTERR interrupt is - * received on the channel. - */ - - stm32_chan_halt(priv, chidx, CHREASON_DTERR); - - /* Clear the NAK and data toggle error conditions */ - - stm32_putreg(STM32_OTGHS_HCINT(chidx), - OTGHS_HCINT_NAK | OTGHS_HCINT_DTERR); - } - - /* Check for a pending FRaMe OverRun (FRMOR) interrupt */ - - if ((pending & OTGHS_HCINT_FRMOR) != 0) - { - /* Halt the channel -- the CHH interrupt is expected next */ - - stm32_chan_halt(priv, chidx, CHREASON_FRMOR); - - /* Clear the FRaMe OverRun (FRMOR) condition */ - - stm32_putreg(STM32_OTGHS_HCINT(chidx), OTGHS_HCINT_FRMOR); - } - - /* Check for a pending TransFeR Completed (XFRC) interrupt */ - - else if ((pending & OTGHS_HCINT_XFRC) != 0) - { - /* Clear the TransFeR Completed (XFRC) condition */ - - stm32_putreg(STM32_OTGHS_HCINT(chidx), OTGHS_HCINT_XFRC); - - /* Then handle the transfer completion event based on the endpoint */ - - if (chan->eptype == OTGHS_EPTYPE_CTRL || - chan->eptype == OTGHS_EPTYPE_BULK) - { - /* Halt the channel -- the CHH interrupt is expected next */ - - stm32_chan_halt(priv, chidx, CHREASON_XFRC); - - /* Clear any pending NAK condition. The 'indata1' data toggle - * should have been appropriately updated by the RxFIFO - * logic as each packet was received. - */ - - stm32_putreg(STM32_OTGHS_HCINT(chidx), OTGHS_HCINT_NAK); - } - else if (chan->eptype == OTGHS_EPTYPE_INTR) - { - /* Force the next transfer on an ODD frame */ - - regval = stm32_getreg(STM32_OTGHS_HCCHAR(chidx)); - regval |= OTGHS_HCCHAR_ODDFRM; - stm32_putreg(STM32_OTGHS_HCCHAR(chidx), regval); - - /* Set the request done state */ - - chan->result = OK; - } - } - - /* Check for a pending CHannel Halted (CHH) interrupt */ - - else if ((pending & OTGHS_HCINT_CHH) != 0) - { - /* Mask the CHannel Halted (CHH) interrupt */ - - regval = stm32_getreg(STM32_OTGHS_HCINTMSK(chidx)); - regval &= ~OTGHS_HCINT_CHH; - stm32_putreg(STM32_OTGHS_HCINTMSK(chidx), regval); - - /* Update the request state based on the host state machine state */ - - if (chan->chreason == CHREASON_XFRC) - { - /* Set the request done result */ - - chan->result = OK; - } - else if (chan->chreason == CHREASON_STALL) - { - /* Set the request stall result */ - - chan->result = EPERM; - } - else if ((chan->chreason == CHREASON_TXERR) || - (chan->chreason == CHREASON_DTERR)) - { - /* Set the request I/O error result */ - - chan->result = EIO; - } - else if (chan->chreason == CHREASON_NAK) - { - /* Set the NAK error result */ - - chan->result = EAGAIN; - } - else /* if (chan->chreason == CHREASON_FRMOR) */ - { - /* Set the frame overrun error result */ - - chan->result = EPIPE; - } - - /* Clear the CHannel Halted (CHH) condition */ - - stm32_putreg(STM32_OTGHS_HCINT(chidx), OTGHS_HCINT_CHH); - } - - /* Check for a pending Transaction ERror (TXERR) interrupt */ - - else if ((pending & OTGHS_HCINT_TXERR) != 0) - { - /* Halt the channel when a STALL, TXERR, BBERR or DTERR interrupt is - * received on the channel. - */ - - stm32_chan_halt(priv, chidx, CHREASON_TXERR); - - /* Clear the Transaction ERror (TXERR) condition */ - - stm32_putreg(STM32_OTGHS_HCINT(chidx), OTGHS_HCINT_TXERR); - } - - /* Check for a pending NAK response received (NAK) interrupt */ - - else if ((pending & OTGHS_HCINT_NAK) != 0) - { - /* For a BULK transfer, the hardware is capable of retrying - * automatically on a NAK. However, this is not always - * what we need to do. So we always halt the transfer and - * return control to high level logic in the event of a NAK. - */ - -#if 1 - /* Halt the interrupt channel */ - - if (chan->eptype == OTGHS_EPTYPE_INTR || - chan->eptype == OTGHS_EPTYPE_BULK) - { - /* Halt the channel -- the CHH interrupt is expected next */ - - stm32_chan_halt(priv, chidx, CHREASON_NAK); - } - - /* Re-activate CTRL and BULK channels. - * - * REVISIT: This can cdause a lot of intedrrupts! - * REVISIT: BULK endpoints are not re-activated. - */ - - else if (chan->eptype == OTGHS_EPTYPE_CTRL) - { - /* Re-activate the channel by clearing CHDIS and assuring that - * CHENA is set - * - * TODO: set channel reason to NACK? - */ - - regval = stm32_getreg(STM32_OTGHS_HCCHAR(chidx)); - regval |= OTGHS_HCCHAR_CHENA; - regval &= ~OTGHS_HCCHAR_CHDIS; - stm32_putreg(STM32_OTGHS_HCCHAR(chidx), regval); - } - -#else - /* Halt all transfers on the NAK -- CHH interrupt is expected next */ - - stm32_chan_halt(priv, chidx, CHREASON_NAK); -#endif - - /* Clear the NAK condition */ - - stm32_putreg(STM32_OTGHS_HCINT(chidx), OTGHS_HCINT_NAK); - } - - /* Check for a transfer complete event */ - - stm32_chan_wakeup(priv, chan); -} - -/**************************************************************************** - * Name: stm32_gint_hcoutisr - * - * Description: - * USB OTG HS host OUT channels interrupt handler - * - * One the completion of the transfer, the channel result byte may be set - * as follows: - * - * OK - Transfer completed successfully - * EAGAIN - If devices NAKs the transfer or NYET occurs - * EPERM - If the endpoint stalls - * EIO - On a TX or data toggle error - * EPIPE - Frame overrun - * - * EBUSY in the result field indicates that the transfer has not completed. - * - ****************************************************************************/ - -static inline void stm32_gint_hcoutisr(struct stm32_usbhost_s *priv, - int chidx) -{ - struct stm32_chan_s *chan = &priv->chan[chidx]; - uint32_t regval; - uint32_t pending; - - /* Read the HCINT register to get the pending HC interrupts. Read the - * HCINTMSK register to get the set of enabled HC interrupts. - */ - - pending = stm32_getreg(STM32_OTGHS_HCINT(chidx)); - regval = stm32_getreg(STM32_OTGHS_HCINTMSK(chidx)); - - /* AND the two to get the set of enabled, pending HC interrupts */ - - pending &= regval; - uinfo("HCINTMSK%d: %08" PRIx32 " pending: %08" PRIx32 "\n", - chidx, regval, pending); - - /* Check for a pending ACK response received/transmitted interrupt */ - - if ((pending & OTGHS_HCINT_ACK) != 0) - { - /* Clear the pending the ACK response received/transmitted interrupt */ - - stm32_putreg(STM32_OTGHS_HCINT(chidx), OTGHS_HCINT_ACK); - } - - /* Check for a pending FRaMe OverRun (FRMOR) interrupt */ - - else if ((pending & OTGHS_HCINT_FRMOR) != 0) - { - /* Halt the channel (probably not necessary for FRMOR) */ - - stm32_chan_halt(priv, chidx, CHREASON_FRMOR); - - /* Clear the pending the FRaMe OverRun (FRMOR) interrupt */ - - stm32_putreg(STM32_OTGHS_HCINT(chidx), OTGHS_HCINT_FRMOR); - } - - /* Check for a pending TransFeR Completed (XFRC) interrupt */ - - else if ((pending & OTGHS_HCINT_XFRC) != 0) - { - /* Decrement the number of bytes remaining by the number of - * bytes that were "in-flight". - */ - - priv->chan[chidx].buffer += priv->chan[chidx].inflight; - priv->chan[chidx].xfrd += priv->chan[chidx].inflight; - priv->chan[chidx].inflight = 0; - - /* Halt the channel -- the CHH interrupt is expected next */ - - stm32_chan_halt(priv, chidx, CHREASON_XFRC); - - /* Clear the pending the TransFeR Completed (XFRC) interrupt */ - - stm32_putreg(STM32_OTGHS_HCINT(chidx), OTGHS_HCINT_XFRC); - } - - /* Check for a pending STALL response receive (STALL) interrupt */ - - else if ((pending & OTGHS_HCINT_STALL) != 0) - { - /* Clear the pending the STALL response receive (STALL) interrupt */ - - stm32_putreg(STM32_OTGHS_HCINT(chidx), OTGHS_HCINT_STALL); - - /* Halt the channel when a STALL, TXERR, BBERR or DTERR interrupt is - * received on the channel. - */ - - stm32_chan_halt(priv, chidx, CHREASON_STALL); - } - - /* Check for a pending NAK response received (NAK) interrupt */ - - else if ((pending & OTGHS_HCINT_NAK) != 0) - { - /* Halt the channel -- the CHH interrupt is expected next */ - - stm32_chan_halt(priv, chidx, CHREASON_NAK); - - /* Clear the pending the NAK response received (NAK) interrupt */ - - stm32_putreg(STM32_OTGHS_HCINT(chidx), OTGHS_HCINT_NAK); - } - - /* Check for a pending Transaction ERror (TXERR) interrupt */ - - else if ((pending & OTGHS_HCINT_TXERR) != 0) - { - /* Halt the channel when a STALL, TXERR, BBERR or DTERR interrupt is - * received on the channel. - */ - - stm32_chan_halt(priv, chidx, CHREASON_TXERR); - - /* Clear the pending the Transaction ERror (TXERR) interrupt */ - - stm32_putreg(STM32_OTGHS_HCINT(chidx), OTGHS_HCINT_TXERR); - } - - /* Check for a NYET interrupt */ - -#if 0 /* NYET is a reserved bit in the HCINT register */ - else if ((pending & OTGHS_HCINT_NYET) != 0) - { - /* Halt the channel */ - - stm32_chan_halt(priv, chidx, CHREASON_NYET); - - /* Clear the pending the NYET interrupt */ - - stm32_putreg(STM32_OTGHS_HCINT(chidx), OTGHS_HCINT_NYET); - } -#endif - - /* Check for a pending Data Toggle ERRor (DTERR) interrupt */ - - else if (pending & OTGHS_HCINT_DTERR) - { - /* Halt the channel when a STALL, TXERR, BBERR or DTERR interrupt is - * received on the channel. - */ - - stm32_chan_halt(priv, chidx, CHREASON_DTERR); - - /* Clear the pending the Data Toggle ERRor (DTERR) and NAK interrupts */ - - stm32_putreg(STM32_OTGHS_HCINT(chidx), - OTGHS_HCINT_DTERR | OTGHS_HCINT_NAK); - } - - /* Check for a pending CHannel Halted (CHH) interrupt */ - - else if ((pending & OTGHS_HCINT_CHH) != 0) - { - /* Mask the CHannel Halted (CHH) interrupt */ - - regval = stm32_getreg(STM32_OTGHS_HCINTMSK(chidx)); - regval &= ~OTGHS_HCINT_CHH; - stm32_putreg(STM32_OTGHS_HCINTMSK(chidx), regval); - - if (chan->chreason == CHREASON_XFRC) - { - /* Set the request done result */ - - chan->result = OK; - - /* Read the HCCHAR register to get the HCCHAR register to get - * the endpoint type. - */ - - regval = stm32_getreg(STM32_OTGHS_HCCHAR(chidx)); - - /* Is it a bulk endpoint? Were an odd number of packets - * transferred? - */ - - if ((regval & OTGHS_HCCHAR_EPTYP_MASK) == - OTGHS_HCCHAR_EPTYP_BULK && - (chan->npackets & 1) != 0) - { - /* Yes to both... toggle the data out PID */ - - chan->outdata1 ^= true; - } - } - else if (chan->chreason == CHREASON_NAK || - chan->chreason == CHREASON_NYET) - { - /* Set the try again later result */ - - chan->result = EAGAIN; - } - else if (chan->chreason == CHREASON_STALL) - { - /* Set the request stall result */ - - chan->result = EPERM; - } - else if ((chan->chreason == CHREASON_TXERR) || - (chan->chreason == CHREASON_DTERR)) - { - /* Set the I/O failure result */ - - chan->result = EIO; - } - else /* if (chan->chreason == CHREASON_FRMOR) */ - { - /* Set the frame error result */ - - chan->result = EPIPE; - } - - /* Clear the pending the CHannel Halted (CHH) interrupt */ - - stm32_putreg(STM32_OTGHS_HCINT(chidx), OTGHS_HCINT_CHH); - } - - /* Check for a transfer complete event */ - - stm32_chan_wakeup(priv, chan); -} - -/**************************************************************************** - * Name: stm32_gint_connected - * - * Description: - * Handle a connection event. - * - ****************************************************************************/ - -static void stm32_gint_connected(struct stm32_usbhost_s *priv) -{ - /* We we previously disconnected? */ - - if (!priv->connected) - { - /* Yes.. then now we are connected */ - - usbhost_vtrace1(OTGHS_VTRACE1_CONNECTED, 0); - priv->connected = true; - priv->change = true; - DEBUGASSERT(priv->smstate == SMSTATE_DETACHED); - - /* Notify any waiters */ - - priv->smstate = SMSTATE_ATTACHED; - if (priv->pscwait) - { - nxsem_post(&priv->pscsem); - priv->pscwait = false; - } - } -} - -/**************************************************************************** - * Name: stm32_gint_disconnected - * - * Description: - * Handle a disconnection event. - * - ****************************************************************************/ - -static void stm32_gint_disconnected(struct stm32_usbhost_s *priv) -{ - /* Were we previously connected? */ - - if (priv->connected) - { - /* Yes.. then we no longer connected */ - - usbhost_vtrace1(OTGHS_VTRACE1_DISCONNECTED, 0); - - /* Are we bound to a class driver? */ - - if (priv->rhport.hport.devclass) - { - /* Yes.. Disconnect the class driver */ - - CLASS_DISCONNECTED(priv->rhport.hport.devclass); - priv->rhport.hport.devclass = NULL; - } - - /* Re-Initialize Host for new Enumeration */ - - priv->smstate = SMSTATE_DETACHED; - priv->connected = false; - priv->change = true; - stm32_chan_freeall(priv); - - priv->rhport.hport.speed = USB_SPEED_FULL; - priv->rhport.hport.funcaddr = 0; - - /* Notify any waiters that there is a change in the connection state */ - - if (priv->pscwait) - { - nxsem_post(&priv->pscsem); - priv->pscwait = false; - } - } -} - -/**************************************************************************** - * Name: stm32_gint_sofisr - * - * Description: - * USB OTG HS start-of-frame interrupt handler - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_OTGHS_SOFINTR -static inline void stm32_gint_sofisr(struct stm32_usbhost_s *priv) -{ - /* Handle SOF interrupt */ - -#warning "Do what?" - - /* Clear pending SOF interrupt */ - - stm32_putreg(STM32_OTGHS_GINTSTS, OTGHS_GINT_SOF); -} -#endif - -/**************************************************************************** - * Name: stm32_gint_rxflvlisr - * - * Description: - * USB OTG HS RxFIFO non-empty interrupt handler - * - ****************************************************************************/ - -static inline void stm32_gint_rxflvlisr(struct stm32_usbhost_s *priv) -{ - uint32_t *dest; - uint32_t grxsts; - uint32_t intmsk; - uint32_t hcchar; - uint32_t hctsiz; - uint32_t fifo; - int bcnt; - int bcnt32; - int chidx; - int i; - - /* Disable the RxFIFO non-empty interrupt */ - - intmsk = stm32_getreg(STM32_OTGHS_GINTMSK); - intmsk &= ~OTGHS_GINT_RXFLVL; - stm32_putreg(STM32_OTGHS_GINTMSK, intmsk); - - /* Read and pop the next status from the Rx FIFO */ - - grxsts = stm32_getreg(STM32_OTGHS_GRXSTSP); - uinfo("GRXSTS: %08" PRIx32 "\n", grxsts); - - /* Isolate the channel number/index in the status word */ - - chidx = (grxsts & OTGHS_GRXSTSH_CHNUM_MASK) >> OTGHS_GRXSTSH_CHNUM_SHIFT; - - /* Get the host channel characteristics register (HCCHAR) */ - - hcchar = stm32_getreg(STM32_OTGHS_HCCHAR(chidx)); - - /* Then process the interrupt according to the packet status */ - - switch (grxsts & OTGHS_GRXSTSH_PKTSTS_MASK) - { - case OTGHS_GRXSTSH_PKTSTS_INRECVD: /* IN data packet received */ - { - /* Read the data into the host buffer. */ - - bcnt = (grxsts & OTGHS_GRXSTSH_BCNT_MASK) >> - OTGHS_GRXSTSH_BCNT_SHIFT; - if (bcnt > 0 && priv->chan[chidx].buffer != NULL) - { - /* Transfer the packet from the Rx FIFO into the user buffer */ - - dest = (uint32_t *)priv->chan[chidx].buffer; - fifo = STM32_OTGHS_DFIFO_HCH(0); - bcnt32 = (bcnt + 3) >> 2; - - for (i = 0; i < bcnt32; i++) - { - *dest++ = stm32_getreg(fifo); - } - - stm32_pktdump("Received", priv->chan[chidx].buffer, bcnt); - - /* Toggle the IN data pid (Used by Bulk and INTR only) */ - - priv->chan[chidx].indata1 ^= true; - - /* Manage multiple packet transfers */ - - priv->chan[chidx].buffer += bcnt; - priv->chan[chidx].xfrd += bcnt; - - /* Check if more packets are expected */ - - hctsiz = stm32_getreg(STM32_OTGHS_HCTSIZ(chidx)); - if ((hctsiz & OTGHS_HCTSIZ_PKTCNT_MASK) != 0) - { - /* Re-activate the channel when more packets are expected */ - - hcchar |= OTGHS_HCCHAR_CHENA; - hcchar &= ~OTGHS_HCCHAR_CHDIS; - stm32_putreg(STM32_OTGHS_HCCHAR(chidx), hcchar); - } - } - } - break; - - case OTGHS_GRXSTSH_PKTSTS_INDONE: /* IN transfer completed */ - case OTGHS_GRXSTSH_PKTSTS_DTOGERR: /* Data toggle error */ - case OTGHS_GRXSTSH_PKTSTS_HALTED: /* Channel halted */ - default: - break; - } - - /* Re-enable the RxFIFO non-empty interrupt */ - - intmsk |= OTGHS_GINT_RXFLVL; - stm32_putreg(STM32_OTGHS_GINTMSK, intmsk); -} - -/**************************************************************************** - * Name: stm32_gint_nptxfeisr - * - * Description: - * USB OTG HS non-periodic TxFIFO empty interrupt handler - * - ****************************************************************************/ - -static inline void stm32_gint_nptxfeisr(struct stm32_usbhost_s *priv) -{ - struct stm32_chan_s *chan; - uint32_t regval; - unsigned int wrsize; - unsigned int avail; - unsigned int chidx; - - /* Recover the index of the channel that is waiting for space in the Tx - * FIFO. - */ - - chidx = priv->chidx; - chan = &priv->chan[chidx]; - - /* Reduce the buffer size by the number of bytes that were previously - * placed in the Tx FIFO. - */ - - chan->buffer += chan->inflight; - chan->xfrd += chan->inflight; - chan->inflight = 0; - - /* If we have now transferred the entire buffer, then this transfer is - * complete (this case really should never happen because we disable - * the NPTXFE interrupt on the final packet). - */ - - if (chan->xfrd >= chan->buflen) - { - /* Disable further Tx FIFO empty interrupts and bail. */ - - stm32_modifyreg(STM32_OTGHS_GINTMSK, OTGHS_GINT_NPTXFE, 0); - return; - } - - /* Read the status from the top of the non-periodic TxFIFO */ - - regval = stm32_getreg(STM32_OTGHS_HNPTXSTS); - - /* Extract the number of bytes available in the non-periodic Tx FIFO. */ - - avail = ((regval & OTGHS_HNPTXSTS_NPTXFSAV_MASK) >> - OTGHS_HNPTXSTS_NPTXFSAV_SHIFT) << 2; - - /* Get the size to put in the Tx FIFO now */ - - wrsize = chan->buflen - chan->xfrd; - - /* Get minimal size packet that can be sent. Something is seriously - * configured wrong if one packet will not fit into the empty Tx FIFO. - */ - - DEBUGASSERT(wrsize > 0 && avail >= MIN(wrsize, chan->maxpacket)); - if (wrsize > avail) - { - /* Clip the write size to the number of full, max sized packets - * that will fit in the Tx FIFO. - */ - - unsigned int wrpackets = avail / chan->maxpacket; - wrsize = wrpackets * chan->maxpacket; - } - - /* Otherwise, this will be the last packet to be sent in this transaction. - * We now need to disable further NPTXFE interrupts. - */ - - else - { - stm32_modifyreg(STM32_OTGHS_GINTMSK, OTGHS_GINT_NPTXFE, 0); - } - - /* Write the next group of packets into the Tx FIFO */ - - uinfo("HNPTXSTS: %08" PRIx32 - " chidx: %d avail: %d buflen: %d xfrd: %dwrsize: %d\n", - regval, chidx, avail, chan->buflen, chan->xfrd, wrsize); - - stm32_gint_wrpacket(priv, chan->buffer, chidx, wrsize); -} - -/**************************************************************************** - * Name: stm32_gint_ptxfeisr - * - * Description: - * USB OTG HS periodic TxFIFO empty interrupt handler - * - ****************************************************************************/ - -static inline void stm32_gint_ptxfeisr(struct stm32_usbhost_s *priv) -{ - struct stm32_chan_s *chan; - uint32_t regval; - unsigned int wrsize; - unsigned int avail; - unsigned int chidx; - - /* Recover the index of the channel that is waiting for space in the Tx - * FIFO. - */ - - chidx = priv->chidx; - chan = &priv->chan[chidx]; - - /* Reduce the buffer size by the number of bytes that were previously - * placed in the Tx FIFO. - */ - - chan->buffer += chan->inflight; - chan->xfrd += chan->inflight; - chan->inflight = 0; - - /* If we have now transferred the entire buffer, then this transfer is - * complete (this case really should never happen because we disable - * the PTXFE interrupt on the final packet). - */ - - if (chan->xfrd >= chan->buflen) - { - /* Disable further Tx FIFO empty interrupts and bail. */ - - stm32_modifyreg(STM32_OTGHS_GINTMSK, OTGHS_GINT_PTXFE, 0); - return; - } - - /* Read the status from the top of the periodic TxFIFO */ - - regval = stm32_getreg(STM32_OTGHS_HPTXSTS); - - /* Extract the number of bytes available in the periodic Tx FIFO. */ - - avail = ((regval & OTGHS_HPTXSTS_PTXFSAVL_MASK) >> - OTGHS_HPTXSTS_PTXFSAVL_SHIFT) << 2; - - /* Get the size to put in the Tx FIFO now */ - - wrsize = chan->buflen - chan->xfrd; - - /* Get minimal size packet that can be sent. Something is seriously - * configured wrong if one packet will not fit into the empty Tx FIFO. - */ - - DEBUGASSERT(wrsize > 0 && avail >= MIN(wrsize, chan->maxpacket)); - if (wrsize > avail) - { - /* Clip the write size to the number of full, max sized packets - * that will fit in the Tx FIFO. - */ - - unsigned int wrpackets = avail / chan->maxpacket; - wrsize = wrpackets * chan->maxpacket; - } - - /* Otherwise, this will be the last packet to be sent in this transaction. - * We now need to disable further PTXFE interrupts. - */ - - else - { - stm32_modifyreg(STM32_OTGHS_GINTMSK, OTGHS_GINT_PTXFE, 0); - } - - /* Write the next group of packets into the Tx FIFO */ - - uinfo("HPTXSTS: %08" PRIx32 - " chidx: %d avail: %d buflen: %d xfrd: %d wrsize: %d\n", - regval, chidx, avail, chan->buflen, chan->xfrd, wrsize); - - stm32_gint_wrpacket(priv, chan->buffer, chidx, wrsize); -} - -/**************************************************************************** - * Name: stm32_gint_hcisr - * - * Description: - * USB OTG HS host channels interrupt handler - * - ****************************************************************************/ - -static inline void stm32_gint_hcisr(struct stm32_usbhost_s *priv) -{ - uint32_t haint; - uint32_t hcchar; - int i = 0; - - /* Read the Host all channels interrupt register and test each bit in the - * register. Each bit i, i=0...(STM32_NHOST_CHANNELS-1), corresponds to - * a pending interrupt on channel i. - */ - - haint = stm32_getreg(STM32_OTGHS_HAINT); - for (i = 0; i < STM32_NHOST_CHANNELS; i++) - { - /* Is an interrupt pending on this channel? */ - - if ((haint & OTGHS_HAINT(i)) != 0) - { - /* Yes... read the HCCHAR register to get the direction bit */ - - hcchar = stm32_getreg(STM32_OTGHS_HCCHAR(i)); - - /* Was this an interrupt on an IN or an OUT channel? */ - - if ((hcchar & OTGHS_HCCHAR_EPDIR) != 0) - { - /* Handle the HC IN channel interrupt */ - - stm32_gint_hcinisr(priv, i); - } - else - { - /* Handle the HC OUT channel interrupt */ - - stm32_gint_hcoutisr(priv, i); - } - } - } -} - -/**************************************************************************** - * Name: stm32_gint_hprtisr - * - * Description: - * USB OTG HS host port interrupt handler - * - ****************************************************************************/ - -static inline void stm32_gint_hprtisr(struct stm32_usbhost_s *priv) -{ - uint32_t hprt; - uint32_t newhprt; - uint32_t hcfg; - - usbhost_vtrace1(OTGHS_VTRACE1_GINT_HPRT, 0); - - /* Read the port status and control register (HPRT) */ - - hprt = stm32_getreg(STM32_OTGHS_HPRT); - - /* Setup to clear the interrupt bits in GINTSTS by setting the - * corresponding bits in the HPRT. The HCINT interrupt bit is cleared - * when the appropriate status bits in the HPRT register are cleared. - */ - - newhprt = hprt & ~(OTGHS_HPRT_PENA | OTGHS_HPRT_PCDET | - OTGHS_HPRT_PENCHNG | OTGHS_HPRT_POCCHNG); - - /* Check for Port Over-urrent CHaNGe (POCCHNG) */ - - if ((hprt & OTGHS_HPRT_POCCHNG) != 0) - { - /* Set up to clear the POCCHNG status in the new HPRT contents. */ - - usbhost_vtrace1(OTGHS_VTRACE1_GINT_HPRT_POCCHNG, 0); - newhprt |= OTGHS_HPRT_POCCHNG; - } - - /* Check for Port Connect DETected (PCDET). The core sets this bit when a - * device connection is detected. - */ - - if ((hprt & OTGHS_HPRT_PCDET) != 0) - { - /* Set up to clear the PCDET status in the new HPRT contents. Then - * process the new connection event. - */ - - usbhost_vtrace1(OTGHS_VTRACE1_GINT_HPRT_PCDET, 0); - newhprt |= OTGHS_HPRT_PCDET; - stm32_portreset(priv); - stm32_gint_connected(priv); - } - - /* Check for Port Enable CHaNGed (PENCHNG) */ - - if ((hprt & OTGHS_HPRT_PENCHNG) != 0) - { - /* Set up to clear the PENCHNG status in the new HPRT contents. */ - - usbhost_vtrace1(OTGHS_VTRACE1_GINT_HPRT_PENCHNG, 0); - newhprt |= OTGHS_HPRT_PENCHNG; - - /* Was the port enabled? */ - - if ((hprt & OTGHS_HPRT_PENA) != 0) - { - /* Yes.. handle the new connection event */ - - stm32_gint_connected(priv); - - /* Check the Host ConFiGuration register (HCFG) */ - - hcfg = stm32_getreg(STM32_OTGHS_HCFG); - - /* Is this a low speed or full speed connection (OTG HS does not - * support high speed) - */ - - if ((hprt & OTGHS_HPRT_PSPD_MASK) == OTGHS_HPRT_PSPD_LS) - { - /* Set the Host Frame Interval Register for the 6KHz speed */ - - usbhost_vtrace1(OTGHS_VTRACE1_GINT_HPRT_LSDEV, 0); - stm32_putreg(STM32_OTGHS_HFIR, 6000); - - /* Are we switching from HS to LS? */ - - if ((hcfg & OTGHS_HCFG_FSLSPCS_MASK) != - OTGHS_HCFG_FSLSPCS_LS6MHz) - { - usbhost_vtrace1(OTGHS_VTRACE1_GINT_HPRT_FSLSSW, 0); - - /* Yes... configure for LS */ - - hcfg &= ~OTGHS_HCFG_FSLSPCS_MASK; - hcfg |= OTGHS_HCFG_FSLSPCS_LS6MHz; - stm32_putreg(STM32_OTGHS_HCFG, hcfg); - - /* And reset the port */ - - stm32_portreset(priv); - } - } - else /* if ((hprt & OTGHS_HPRT_PSPD_MASK) == OTGHS_HPRT_PSPD_HS) */ - { - usbhost_vtrace1(OTGHS_VTRACE1_GINT_HPRT_FSDEV, 0); - stm32_putreg(STM32_OTGHS_HFIR, 48000); - - /* Are we switching from LS to HS? */ - - if ((hcfg & OTGHS_HCFG_FSLSPCS_MASK) != - OTGHS_HCFG_FSLSPCS_FS48MHz) - { - usbhost_vtrace1(OTGHS_VTRACE1_GINT_HPRT_LSFSSW, 0); - - /* Yes... configure for HS */ - - hcfg &= ~OTGHS_HCFG_FSLSPCS_MASK; - hcfg |= OTGHS_HCFG_FSLSPCS_FS48MHz; - stm32_putreg(STM32_OTGHS_HCFG, hcfg); - - /* And reset the port */ - - stm32_portreset(priv); - } - } - } - } - - /* Clear port interrupts by setting bits in the HPRT */ - - stm32_putreg(STM32_OTGHS_HPRT, newhprt); -} - -/**************************************************************************** - * Name: stm32_gint_discisr - * - * Description: - * USB OTG HS disconnect detected interrupt handler - * - ****************************************************************************/ - -static inline void stm32_gint_discisr(struct stm32_usbhost_s *priv) -{ - /* Handle the disconnection event */ - - stm32_gint_disconnected(priv); - - /* Clear the dicsonnect interrupt */ - - stm32_putreg(STM32_OTGHS_GINTSTS, OTGHS_GINT_DISC); -} - -/**************************************************************************** - * Name: stm32_gint_ipxfrisr - * - * Description: - * USB OTG HS incomplete periodic interrupt handler - * - ****************************************************************************/ - -static inline void stm32_gint_ipxfrisr(struct stm32_usbhost_s *priv) -{ - uint32_t regval; - - /* CHENA : Set to enable the channel - * CHDIS : Set to stop transmitting/receiving data on a channel - */ - - regval = stm32_getreg(STM32_OTGHS_HCCHAR(0)); - regval |= (OTGHS_HCCHAR_CHDIS | OTGHS_HCCHAR_CHENA); - stm32_putreg(STM32_OTGHS_HCCHAR(0), regval); - - /* Clear the incomplete isochronous OUT interrupt */ - - stm32_putreg(STM32_OTGHS_GINTSTS, OTGHS_GINT_IPXFR); -} - -/**************************************************************************** - * Name: stm32_gint_isr - * - * Description: - * USB OTG HS global interrupt handler - * - ****************************************************************************/ - -static int stm32_gint_isr(int irq, void *context, void *arg) -{ - /* At present, there is only support for a single OTG HS host. Hence it is - * pre-allocated as g_usbhost. However, in most code, the private data - * structure will be referenced using the 'priv' pointer (rather than the - * global data) in order to simplify any future support for multiple - * devices. - */ - - struct stm32_usbhost_s *priv = &g_usbhost; - uint32_t pending; - - /* If OTG were supported, we would need to check if we are in host or - * device mode when the global interrupt occurs. Here we support only - * host mode - */ - - /* Loop while there are pending interrupts to process. This loop may save - * a little interrupt handling overhead. - */ - - for (; ; ) - { - /* Get the unmasked bits in the GINT status */ - - pending = stm32_getreg(STM32_OTGHS_GINTSTS); - pending &= stm32_getreg(STM32_OTGHS_GINTMSK); - - /* Return from the interrupt when there are no further pending - * interrupts. - */ - - if (pending == 0) - { - return OK; - } - - /* Otherwise, process each pending, unmasked GINT interrupts */ - - /* Handle the start of frame interrupt */ - -#ifdef CONFIG_STM32_OTGHS_SOFINTR - if ((pending & OTGHS_GINT_SOF) != 0) - { - usbhost_vtrace1(OTGHS_VTRACE1_GINT_SOF, 0); - stm32_gint_sofisr(priv); - } -#endif - - /* Handle the RxFIFO non-empty interrupt */ - - if ((pending & OTGHS_GINT_RXFLVL) != 0) - { - usbhost_vtrace1(OTGHS_VTRACE1_GINT_RXFLVL, 0); - stm32_gint_rxflvlisr(priv); - } - - /* Handle the non-periodic TxFIFO empty interrupt */ - - if ((pending & OTGHS_GINT_NPTXFE) != 0) - { - usbhost_vtrace1(OTGHS_VTRACE1_GINT_NPTXFE, 0); - stm32_gint_nptxfeisr(priv); - } - - /* Handle the periodic TxFIFO empty interrupt */ - - if ((pending & OTGHS_GINT_PTXFE) != 0) - { - usbhost_vtrace1(OTGHS_VTRACE1_GINT_PTXFE, 0); - stm32_gint_ptxfeisr(priv); - } - - /* Handle the host channels interrupt */ - - if ((pending & OTGHS_GINT_HC) != 0) - { - usbhost_vtrace1(OTGHS_VTRACE1_GINT_HC, 0); - stm32_gint_hcisr(priv); - } - - /* Handle the host port interrupt */ - - if ((pending & OTGHS_GINT_HPRT) != 0) - { - stm32_gint_hprtisr(priv); - } - - /* Handle the disconnect detected interrupt */ - - if ((pending & OTGHS_GINT_DISC) != 0) - { - usbhost_vtrace1(OTGHS_VTRACE1_GINT_DISC, 0); - stm32_gint_discisr(priv); - } - - /* Handle the incomplete periodic transfer */ - - if ((pending & OTGHS_GINT_IPXFR) != 0) - { - usbhost_vtrace1(OTGHS_VTRACE1_GINT_IPXFR, 0); - stm32_gint_ipxfrisr(priv); - } - } - - /* We won't get here */ - - return OK; -} - -/**************************************************************************** - * Name: stm32_gint_enable and stm32_gint_disable - * - * Description: - * Respectively enable or disable the global OTG HS interrupt. - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void stm32_gint_enable(void) -{ - uint32_t regval; - - /* Set the GINTMSK bit to unmask the interrupt */ - - regval = stm32_getreg(STM32_OTGHS_GAHBCFG); - regval |= OTGHS_GAHBCFG_GINTMSK; - stm32_putreg(STM32_OTGHS_GAHBCFG, regval); -} - -static void stm32_gint_disable(void) -{ - uint32_t regval; - - /* Clear the GINTMSK bit to mask the interrupt */ - - regval = stm32_getreg(STM32_OTGHS_GAHBCFG); - regval &= ~OTGHS_GAHBCFG_GINTMSK; - stm32_putreg(STM32_OTGHS_GAHBCFG, regval); -} - -/**************************************************************************** - * Name: stm32_hostinit_enable - * - * Description: - * Enable host interrupts. - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -static inline void stm32_hostinit_enable(void) -{ - uint32_t regval; - - /* Disable all interrupts. */ - - stm32_putreg(STM32_OTGHS_GINTMSK, 0); - - /* Clear any pending interrupts. */ - - stm32_putreg(STM32_OTGHS_GINTSTS, 0xffffffff); - - /* Clear any pending USB OTG Interrupts */ - - stm32_putreg(STM32_OTGHS_GOTGINT, 0xffffffff); - - /* Clear any pending USB OTG interrupts */ - - stm32_putreg(STM32_OTGHS_GINTSTS, 0xbfffffff); - - /* Enable the host interrupts */ - - /* Common interrupts: - * - * OTGHS_GINT_WKUP : Resume/remote wakeup detected interrupt - * OTGHS_GINT_USBSUSP : USB suspend - */ - - regval = (OTGHS_GINT_WKUP | OTGHS_GINT_USBSUSP); - - /* If OTG were supported, we would need to enable the following as well: - * - * OTGHS_GINT_OTG : OTG interrupt - * OTGHS_GINT_SRQ : Session request/new session detected interrupt - * OTGHS_GINT_CIDSCHG : Connector ID status change - */ - - /* Host-specific interrupts - * - * OTGHS_GINT_SOF : Start of frame - * OTGHS_GINT_RXFLVL : RxFIFO non-empty - * OTGHS_GINT_IISOOXFR : Incomplete isochronous OUT transfer - * OTGHS_GINT_HPRT : Host port interrupt - * OTGHS_GINT_HC : Host channels interrupt - * OTGHS_GINT_DISC : Disconnect detected interrupt - */ - -#ifdef CONFIG_STM32_OTGHS_SOFINTR - regval |= (OTGHS_GINT_SOF | OTGHS_GINT_RXFLVL | OTGHS_GINT_IISOOXFR | - OTGHS_GINT_HPRT | OTGHS_GINT_HC | OTGHS_GINT_DISC); -#else - regval |= (OTGHS_GINT_RXFLVL | OTGHS_GINT_IPXFR | OTGHS_GINT_HPRT | - OTGHS_GINT_HC | OTGHS_GINT_DISC); -#endif - stm32_putreg(STM32_OTGHS_GINTMSK, regval); -} - -/**************************************************************************** - * Name: stm32_txfe_enable - * - * Description: - * Enable Tx FIFO empty interrupts. This is necessary when the entire - * transfer will not fit into Tx FIFO. The transfer will then be completed - * when the Tx FIFO is empty. NOTE: The Tx FIFO interrupt is disabled - * the fifo empty interrupt handler when the transfer is complete. - * - * Input Parameters: - * priv - Driver state structure reference - * chidx - The channel that requires the Tx FIFO empty interrupt - * - * Returned Value: - * None - * - * Assumptions: - * Called from user task context. Interrupts must be disabled to assure - * exclusive access to the GINTMSK register. - * - ****************************************************************************/ - -static void stm32_txfe_enable(struct stm32_usbhost_s *priv, int chidx) -{ - struct stm32_chan_s *chan = &priv->chan[chidx]; - irqstate_t flags; - uint32_t regval; - - /* Disable all interrupts so that we have exclusive access to the GINTMSK - * (it would be sufficient just to disable the GINT interrupt). - */ - - flags = enter_critical_section(); - - /* Should we enable the periodic or non-peridic Tx FIFO empty interrupts */ - - regval = stm32_getreg(STM32_OTGHS_GINTMSK); - switch (chan->eptype) - { - default: - case OTGHS_EPTYPE_CTRL: /* Non periodic transfer */ - case OTGHS_EPTYPE_BULK: - regval |= OTGHS_GINT_NPTXFE; - break; - - case OTGHS_EPTYPE_INTR: /* Periodic transfer */ - case OTGHS_EPTYPE_ISOC: - regval |= OTGHS_GINT_PTXFE; - break; - } - - /* Enable interrupts */ - - stm32_putreg(STM32_OTGHS_GINTMSK, regval); - leave_critical_section(flags); -} - -/**************************************************************************** - * USB Host Controller Operations - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_wait - * - * Description: - * Wait for a device to be connected or disconnected to/from a hub port. - * - * Input Parameters: - * conn - The USB host connection instance obtained as a parameter from - * the call to the USB driver initialization logic. - * hport - The location to return the hub port descriptor that detected - * the connection related event. - * - * Returned Value: - * Zero (OK) is returned on success when a device is connected or - * disconnected. This function will not return until either (1) a device is - * connected or disconnect to/from any hub port or until (2) some failure - * occurs. On a failure, a negated errno value is returned indicating the - * nature of the failure - * - * Assumptions: - * - Called from a single thread so no mutual exclusion is required. - * - Never called from an interrupt handler. - * - ****************************************************************************/ - -static int stm32_wait(struct usbhost_connection_s *conn, - struct usbhost_hubport_s **hport) -{ - struct stm32_usbhost_s *priv = &g_usbhost; - struct usbhost_hubport_s *connport; - irqstate_t flags; - int ret; - - /* Loop until a change in connection state is detected */ - - flags = enter_critical_section(); - for (; ; ) - { - /* Is there a change in the connection state of the single root hub - * port? - */ - - if (priv->change) - { - connport = &priv->rhport.hport; - - /* Yes. Remember the new state */ - - connport->connected = priv->connected; - priv->change = false; - - /* And return the root hub port */ - - *hport = connport; - leave_critical_section(flags); - - uinfo("RHport Connected: %s\n", - connport->connected ? "YES" : "NO"); - return OK; - } - -#ifdef CONFIG_USBHOST_HUB - /* Is a device connected to an external hub? */ - - if (priv->hport) - { - /* Yes.. return the external hub port */ - - connport = (struct usbhost_hubport_s *)priv->hport; - priv->hport = NULL; - - *hport = connport; - leave_critical_section(flags); - - uinfo("Hub port Connected: %s\n", - connport->connected ? "YES" : "NO"); - return OK; - } -#endif - - /* Wait for the next connection event */ - - priv->pscwait = true; - ret = nxsem_wait_uninterruptible(&priv->pscsem); - if (ret < 0) - { - return ret; - } - } -} - -/**************************************************************************** - * Name: stm32_enumerate - * - * Description: - * Enumerate the connected device. As part of this enumeration process, - * the driver will (1) get the device's configuration descriptor, (2) - * extract the class ID info from the configuration descriptor, (3) call - * usbhost_findclass() to find the class that supports this device, (4) - * call the create() method on the struct usbhost_registry_s interface - * to get a class instance, and finally (5) call the connect() method - * of the struct usbhost_class_s interface. After that, the class is in - * charge of the sequence of operations. - * - * Input Parameters: - * conn - The USB host connection instance obtained as a parameter from - * the call to the USB driver initialization logic. - * hport - The descriptor of the hub port that has the newly connected - * device. - * - * Returned Value: - * On success, zero (OK) is returned. On a failure, a negated errno value - * is returned indicating the nature of the failure - * - * Assumptions: - * This function will *not* be called from an interrupt handler. - * - ****************************************************************************/ - -static int stm32_rh_enumerate(struct stm32_usbhost_s *priv, - struct usbhost_connection_s *conn, - struct usbhost_hubport_s *hport) -{ - uint32_t regval; - int ret; - - DEBUGASSERT(conn != NULL && hport != NULL && hport->port == 0); - - /* Are we connected to a device? The caller should have called the wait() - * method first to be assured that a device is connected. - */ - - while (!priv->connected) - { - /* No, return an error */ - - usbhost_trace1(OTGHS_TRACE1_DEVDISCONN, 0); - return -ENODEV; - } - - DEBUGASSERT(priv->smstate == SMSTATE_ATTACHED); - - /* USB 2.0 spec says at least 50ms delay before port reset. We wait - * 100ms. - */ - - nxsched_usleep(100 * 1000); - - /* Reset the host port */ - - stm32_portreset(priv); - - /* Get the current device speed */ - - regval = stm32_getreg(STM32_OTGHS_HPRT); - if ((regval & OTGHS_HPRT_PSPD_MASK) == OTGHS_HPRT_PSPD_LS) - { - priv->rhport.hport.speed = USB_SPEED_LOW; - } - else - { - priv->rhport.hport.speed = USB_SPEED_FULL; - } - - /* Allocate and initialize the root hub port EP0 channels */ - - ret = stm32_ctrlchan_alloc(priv, 0, 0, priv->rhport.hport.speed, - &priv->ep0); - if (ret < 0) - { - uerr("ERROR: Failed to allocate a control endpoint: %d\n", ret); - } - - return ret; -} - -static int stm32_enumerate(struct usbhost_connection_s *conn, - struct usbhost_hubport_s *hport) -{ - struct stm32_usbhost_s *priv = &g_usbhost; - int ret; - - DEBUGASSERT(hport); - - /* If this is a connection on the root hub, then we need to go to - * little more effort to get the device speed. If it is a connection - * on an external hub, then we already have that information. - */ - -#ifdef CONFIG_USBHOST_HUB - if (ROOTHUB(hport)) -#endif - { - ret = stm32_rh_enumerate(priv, conn, hport); - if (ret < 0) - { - return ret; - } - } - - /* Then let the common usbhost_enumerate do the real enumeration. */ - - uinfo("Enumerate the device\n"); - priv->smstate = SMSTATE_ENUM; - ret = usbhost_enumerate(hport, &hport->devclass); - - /* The enumeration may fail either because of some HCD interfaces failure - * or because the device class is not supported. In either case, we just - * need to perform the disconnection operation and make ready for a new - * enumeration. - */ - - if (ret < 0) - { - /* Return to the disconnected state */ - - uerr("ERROR: Enumeration failed: %d\n", ret); - stm32_gint_disconnected(priv); - } - - return ret; -} - -/**************************************************************************** - * Name: stm32_ep0configure - * - * Description: - * Configure endpoint 0. This method is normally used internally by the - * enumerate() method but is made available at the interface to support an - * external implementation of the enumeration logic. - * - * Input Parameters: - * drvr - The USB host driver instance obtained as a parameter from the - * call to the class create() method. - * ep0 - The (opaque) EP0 endpoint instance - * funcaddr - The USB address of the function containing the endpoint that - * EP0 controls - * speed - The speed of the port USB_SPEED_LOW, _FULL, or _HIGH - * maxpacketsize - The maximum number of bytes that can be sent to or - * received from the endpoint in a single data packet - * - * Returned Value: - * On success, zero (OK) is returned. On a failure, a negated errno value - * is returned indicating the nature of the failure - * - * Assumptions: - * This function will *not* be called from an interrupt handler. - * - ****************************************************************************/ - -static int stm32_ep0configure(struct usbhost_driver_s *drvr, - usbhost_ep_t ep0, uint8_t funcaddr, - uint8_t speed, uint16_t maxpacketsize) -{ - struct stm32_usbhost_s *priv = (struct stm32_usbhost_s *)drvr; - struct stm32_ctrlinfo_s *ep0info = (struct stm32_ctrlinfo_s *)ep0; - struct stm32_chan_s *chan; - int ret; - - DEBUGASSERT(drvr != NULL && ep0info != NULL && funcaddr < 128 && - maxpacketsize <= 64); - - /* We must have exclusive access to the USB host hardware and structures */ - - ret = nxmutex_lock(&priv->lock); - if (ret < 0) - { - return ret; - } - - /* Configure the EP0 OUT channel */ - - chan = &priv->chan[ep0info->outndx]; - chan->funcaddr = funcaddr; - chan->speed = speed; - chan->maxpacket = maxpacketsize; - - stm32_chan_configure(priv, ep0info->outndx); - - /* Configure the EP0 IN channel */ - - chan = &priv->chan[ep0info->inndx]; - chan->funcaddr = funcaddr; - chan->speed = speed; - chan->maxpacket = maxpacketsize; - - stm32_chan_configure(priv, ep0info->inndx); - - nxmutex_unlock(&priv->lock); - return OK; -} - -/**************************************************************************** - * Name: stm32_epalloc - * - * Description: - * Allocate and configure one endpoint. - * - * Input Parameters: - * drvr - The USB host driver instance obtained as a parameter from the - * call to the class create() method. - * epdesc - Describes the endpoint to be allocated. - * ep - A memory location provided by the caller in which to receive the - * allocated endpoint descriptor. - * - * Returned Value: - * On success, zero (OK) is returned. On a failure, a negated errno value - * is returned indicating the nature of the failure - * - * Assumptions: - * This function will *not* be called from an interrupt handler. - * - ****************************************************************************/ - -static int stm32_epalloc(struct usbhost_driver_s *drvr, - const struct usbhost_epdesc_s *epdesc, - usbhost_ep_t *ep) -{ - struct stm32_usbhost_s *priv = (struct stm32_usbhost_s *)drvr; - int ret; - - /* Sanity check. NOTE that this method should only be called if a device - * is connected (because we need a valid low speed indication). - */ - - DEBUGASSERT(drvr != 0 && epdesc != NULL && ep != NULL); - - /* We must have exclusive access to the USB host hardware and structures */ - - ret = nxmutex_lock(&priv->lock); - if (ret < 0) - { - return ret; - } - - /* Handler control pipes differently from other endpoint types. This is - * because the normal, "transfer" endpoints are unidirectional an require - * only a single channel. Control endpoints, however, are bi-diretional - * and require two channels, one for the IN and one for the OUT direction. - */ - - if (epdesc->xfrtype == OTGHS_EPTYPE_CTRL) - { - ret = stm32_ctrlep_alloc(priv, epdesc, ep); - } - else - { - ret = stm32_xfrep_alloc(priv, epdesc, ep); - } - - nxmutex_unlock(&priv->lock); - return ret; -} - -/**************************************************************************** - * Name: stm32_epfree - * - * Description: - * Free and endpoint previously allocated by DRVR_EPALLOC. - * - * Input Parameters: - * drvr - The USB host driver instance obtained as a parameter from the - * call to the class create() method. - * ep - The endpoint to be freed. - * - * Returned Value: - * On success, zero (OK) is returned. On a failure, a negated errno value - * is returned indicating the nature of the failure - * - * Assumptions: - * This function will *not* be called from an interrupt handler. - * - ****************************************************************************/ - -static int stm32_epfree(struct usbhost_driver_s *drvr, usbhost_ep_t ep) -{ - struct stm32_usbhost_s *priv = (struct stm32_usbhost_s *)drvr; - int ret; - - DEBUGASSERT(priv); - - /* We must have exclusive access to the USB host hardware and structures */ - - ret = nxmutex_lock(&priv->lock); - - /* A single channel is represent by an index in the range of 0 to - * STM32_MAX_TX_FIFOS. Otherwise, the ep must be a pointer to an allocated - * control endpoint structure. - */ - - if ((uintptr_t)ep < STM32_MAX_TX_FIFOS) - { - /* Halt the channel and mark the channel available */ - - stm32_chan_free(priv, (int)ep); - } - else - { - /* Halt both control channel and mark the channels available */ - - struct stm32_ctrlinfo_s *ctrlep = - (struct stm32_ctrlinfo_s *)ep; - - stm32_chan_free(priv, ctrlep->inndx); - stm32_chan_free(priv, ctrlep->outndx); - - /* And free the control endpoint container */ - - kmm_free(ctrlep); - } - - nxmutex_unlock(&priv->lock); - return ret; -} - -/**************************************************************************** - * Name: stm32_alloc - * - * Description: - * Some hardware supports special memory in which request and descriptor - * data can be accessed more efficiently. This method provides a - * mechanism to allocate the request/descriptor memory. If the underlying - * hardware does not support such "special" memory, this functions may - * simply map to kmm_malloc. - * - * This interface was optimized under a particular assumption. It was - * assumed that the driver maintains a pool of small, pre-allocated - * buffers for descriptor traffic. NOTE that size is not an input, but - * an output: The size of the pre-allocated buffer is returned. - * - * Input Parameters: - * drvr - The USB host driver instance obtained as a parameter from the - * call to the class create() method. - * buffer - The address of a memory location provided by the caller in - * which to return the allocated buffer memory address. - * maxlen - The address of a memory location provided by the caller in - * which to return the maximum size of the allocated buffer memory. - * - * Returned Value: - * On success, zero (OK) is returned. On a failure, a negated errno value - * is returned indicating the nature of the failure - * - * Assumptions: - * - Called from a single thread so no mutual exclusion is required. - * - Never called from an interrupt handler. - * - ****************************************************************************/ - -static int stm32_alloc(struct usbhost_driver_s *drvr, - uint8_t **buffer, size_t *maxlen) -{ - uint8_t *alloc; - - DEBUGASSERT(drvr && buffer && maxlen); - - /* There is no special memory requirement for the STM32. */ - - alloc = kmm_malloc(CONFIG_STM32_OTGHS_DESCSIZE); - if (!alloc) - { - return -ENOMEM; - } - - /* Return the allocated address and size of the descriptor buffer */ - - *buffer = alloc; - *maxlen = CONFIG_STM32_OTGHS_DESCSIZE; - return OK; -} - -/**************************************************************************** - * Name: stm32_free - * - * Description: - * Some hardware supports special memory in which request and descriptor - * data can be accessed more efficiently. This method provides a - * mechanism to free that request/descriptor memory. If the underlying - * hardware does not support such "special" memory, this functions may - * simply map to kmm_free(). - * - * Input Parameters: - * drvr - The USB host driver instance obtained as a parameter from the - * call to the class create() method. - * buffer - The address of the allocated buffer memory to be freed. - * - * Returned Value: - * On success, zero (OK) is returned. On a failure, a negated errno value - * is returned indicating the nature of the failure - * - * Assumptions: - * - Never called from an interrupt handler. - * - ****************************************************************************/ - -static int stm32_free(struct usbhost_driver_s *drvr, uint8_t *buffer) -{ - /* There is no special memory requirement */ - - DEBUGASSERT(drvr && buffer); - kmm_free(buffer); - return OK; -} - -/**************************************************************************** - * Name: stm32_ioalloc - * - * Description: - * Some hardware supports special memory in which larger IO buffers can - * be accessed more efficiently. This method provides a mechanism to - * allocate the request/descriptor memory. If the underlying hardware - * does not support such "special" memory, this functions may simply map - * to kmm_malloc. - * - * This interface differs from DRVR_ALLOC in that the buffers are - * variable-sized. - * - * Input Parameters: - * drvr - The USB host driver instance obtained as a parameter from the - * call to the class create() method. - * buffer - The address of a memory location provided by the caller in - * which to return the allocated buffer memory address. - * buflen - The size of the buffer required. - * - * Returned Value: - * On success, zero (OK) is returned. On a failure, a negated errno value - * is returned indicating the nature of the failure - * - * Assumptions: - * This function will *not* be called from an interrupt handler. - * - ****************************************************************************/ - -static int stm32_ioalloc(struct usbhost_driver_s *drvr, - uint8_t **buffer, size_t buflen) -{ - uint8_t *alloc; - - DEBUGASSERT(drvr && buffer && buflen > 0); - - /* There is no special memory requirement */ - - alloc = kmm_malloc(buflen); - if (!alloc) - { - return -ENOMEM; - } - - /* Return the allocated buffer */ - - *buffer = alloc; - return OK; -} - -/**************************************************************************** - * Name: stm32_iofree - * - * Description: - * Some hardware supports special memory in which IO data can be accessed - * more efficiently. This method provides a mechanism to free that IO - * buffer memory. If the underlying hardware does not support such - * "special" memory, this functions may simply map to kmm_free(). - * - * Input Parameters: - * drvr - The USB host driver instance obtained as a parameter from the - * call to the class create() method. - * buffer - The address of the allocated buffer memory to be freed. - * - * Returned Value: - * On success, zero (OK) is returned. On a failure, a negated errno value - * is returned indicating the nature of the failure - * - * Assumptions: - * This function will *not* be called from an interrupt handler. - * - ****************************************************************************/ - -static int stm32_iofree(struct usbhost_driver_s *drvr, - uint8_t *buffer) -{ - /* There is no special memory requirement */ - - DEBUGASSERT(drvr && buffer); - kmm_free(buffer); - return OK; -} - -/**************************************************************************** - * Name: stm32_ctrlin and stm32_ctrlout - * - * Description: - * Process a IN or OUT request on the control endpoint. These methods - * will enqueue the request and wait for it to complete. Only one - * transfer may be queued; Neither these methods nor the transfer() - * method can be called again until the control transfer functions - * returns. - * - * These are blocking methods; these functions will not return until the - * control transfer has completed. - * - * Input Parameters: - * drvr - The USB host driver instance obtained as a parameter from the - * call to the class create() method. - * ep0 - The control endpoint to send/receive the control request. - * req - Describes the request to be sent. This request must lie in memory - * created by DRVR_ALLOC. - * buffer - A buffer used for sending the request and for returning any - * responses. This buffer must be large enough to hold the length value - * in the request description. buffer must have been allocated using - * DRVR_ALLOC. - * - * NOTE: On an IN transaction, req and buffer may refer to the same - * allocated memory. - * - * Returned Value: - * On success, zero (OK) is returned. On a failure, a negated errno value - * is returned indicating the nature of the failure - * - * Assumptions: - * - Called from a single thread so no mutual exclusion is required. - * - Never called from an interrupt handler. - * - ****************************************************************************/ - -static int stm32_ctrlin(struct usbhost_driver_s *drvr, usbhost_ep_t ep0, - const struct usb_ctrlreq_s *req, - uint8_t *buffer) -{ - struct stm32_usbhost_s *priv = (struct stm32_usbhost_s *)drvr; - struct stm32_ctrlinfo_s *ep0info = (struct stm32_ctrlinfo_s *)ep0; - uint16_t buflen; - clock_t start; - clock_t elapsed; - int retries; - int ret; - - DEBUGASSERT(priv != NULL && ep0info != NULL && req != NULL); - usbhost_vtrace2(OTGHS_VTRACE2_CTRLIN, req->type, req->req); - uinfo("type:%02x req:%02x value:%02x%02x index:%02x%02x len:%02x%02x\n", - req->type, req->req, req->value[1], req->value[0], - req->index[1], req->index[0], req->len[1], req->len[0]); - - /* Extract values from the request */ - - buflen = stm32_getle16(req->len); - - /* We must have exclusive access to the USB host hardware and structures */ - - ret = nxmutex_lock(&priv->lock); - if (ret < 0) - { - return ret; - } - - /* Loop, retrying until the retry time expires */ - - for (retries = 0; retries < STM32_RETRY_COUNT; retries++) - { - /* Send the SETUP request */ - - ret = stm32_ctrl_sendsetup(priv, ep0info, req); - if (ret < 0) - { - usbhost_trace1(OTGHS_TRACE1_SENDSETUP, -ret); - continue; - } - - /* Handle the IN data phase (if any) */ - - if (buflen > 0) - { - ret = stm32_ctrl_recvdata(priv, ep0info, buffer, buflen); - if (ret < 0) - { - usbhost_trace1(OTGHS_TRACE1_RECVDATA, -ret); - continue; - } - } - - /* Get the start time. Loop again until the timeout expires */ - - start = clock_systime_ticks(); - do - { - /* Handle the status OUT phase */ - - priv->chan[ep0info->outndx].outdata1 ^= true; - ret = stm32_ctrl_senddata(priv, ep0info, NULL, 0); - if (ret == OK) - { - /* All success transactions exit here */ - - nxmutex_unlock(&priv->lock); - return OK; - } - - usbhost_trace1(OTGHS_TRACE1_SENDDATA, ret < 0 ? -ret : ret); - - /* Get the elapsed time (in frames) */ - - elapsed = clock_systime_ticks() - start; - } - while (elapsed < STM32_DATANAK_DELAY); - } - - /* All failures exit here after all retries and timeouts are exhausted */ - - nxmutex_unlock(&priv->lock); - return -ETIMEDOUT; -} - -static int stm32_ctrlout(struct usbhost_driver_s *drvr, usbhost_ep_t ep0, - const struct usb_ctrlreq_s *req, - const uint8_t *buffer) -{ - struct stm32_usbhost_s *priv = (struct stm32_usbhost_s *)drvr; - struct stm32_ctrlinfo_s *ep0info = (struct stm32_ctrlinfo_s *)ep0; - uint16_t buflen; - clock_t start; - clock_t elapsed; - int retries; - int ret; - - DEBUGASSERT(priv != NULL && ep0info != NULL && req != NULL); - usbhost_vtrace2(OTGHS_VTRACE2_CTRLOUT, req->type, req->req); - uinfo("type:%02x req:%02x value:%02x%02x index:%02x%02x len:%02x%02x\n", - req->type, req->req, req->value[1], req->value[0], - req->index[1], req->index[0], req->len[1], req->len[0]); - - /* Extract values from the request */ - - buflen = stm32_getle16(req->len); - - /* We must have exclusive access to the USB host hardware and structures */ - - ret = nxmutex_lock(&priv->lock); - if (ret < 0) - { - return ret; - } - - /* Loop, retrying until the retry time expires */ - - for (retries = 0; retries < STM32_RETRY_COUNT; retries++) - { - /* Send the SETUP request */ - - ret = stm32_ctrl_sendsetup(priv, ep0info, req); - if (ret < 0) - { - usbhost_trace1(OTGHS_TRACE1_SENDSETUP, -ret); - continue; - } - - /* Get the start time. Loop again until the timeout expires */ - - start = clock_systime_ticks(); - do - { - /* Handle the data OUT phase (if any) */ - - if (buflen > 0) - { - /* Start DATA out transfer (only one DATA packet) */ - - priv->chan[ep0info->outndx].outdata1 = true; - ret = stm32_ctrl_senddata(priv, ep0info, (uint8_t *)buffer, - buflen); - if (ret < 0) - { - usbhost_trace1(OTGHS_TRACE1_SENDDATA, -ret); - } - } - - /* Handle the status IN phase */ - - if (ret == OK) - { - ret = stm32_ctrl_recvdata(priv, ep0info, NULL, 0); - if (ret == OK) - { - /* All success transactins exit here */ - - nxmutex_unlock(&priv->lock); - return OK; - } - - usbhost_trace1(OTGHS_TRACE1_RECVDATA, ret < 0 ? -ret : ret); - } - - /* Get the elapsed time (in frames) */ - - elapsed = clock_systime_ticks() - start; - } - while (elapsed < STM32_DATANAK_DELAY); - } - - /* All failures exit here after all retries and timeouts are exhausted */ - - nxmutex_unlock(&priv->lock); - return -ETIMEDOUT; -} - -/**************************************************************************** - * Name: stm32_transfer - * - * Description: - * Process a request to handle a transfer descriptor. This method will - * enqueue the transfer request, blocking until the transfer completes. - * Only one transfer may be queued; Neither this method nor the ctrlin or - * ctrlout methods can be called again until this function returns. - * - * This is a blocking method; this functions will not return until the - * transfer has completed. - * - * Input Parameters: - * drvr - The USB host driver instance obtained as a parameter from the - * call to the class create() method. - * ep - The IN or OUT endpoint descriptor for the device endpoint on - * which to perform the transfer. - * buffer - A buffer containing the data to be sent (OUT endpoint) or - * received (IN endpoint). buffer must have been allocated using - * DRVR_ALLOC - * buflen - The length of the data to be sent or received. - * - * Returned Value: - * On success, a non-negative value is returned that indicates the number - * of bytes successfully transferred. On a failure, a negated errno value - * is returned that indicates the nature of the failure: - * - * EAGAIN - If devices NAKs the transfer (or NYET or other error where - * it may be appropriate to restart the entire transaction). - * EPERM - If the endpoint stalls - * EIO - On a TX or data toggle error - * EPIPE - Overrun errors - * - * Assumptions: - * - Called from a single thread so no mutual exclusion is required. - * - Never called from an interrupt handler. - * - ****************************************************************************/ - -static ssize_t stm32_transfer(struct usbhost_driver_s *drvr, - usbhost_ep_t ep, - uint8_t *buffer, size_t buflen) -{ - struct stm32_usbhost_s *priv = (struct stm32_usbhost_s *)drvr; - unsigned int chidx = (unsigned int)ep; - ssize_t nbytes; - int ret; - - uinfo("chidx: %d buflen: %d\n", (unsigned int)ep, buflen); - - DEBUGASSERT(priv && buffer && chidx < STM32_MAX_TX_FIFOS && buflen > 0); - - /* We must have exclusive access to the USB host hardware and structures */ - - ret = nxmutex_lock(&priv->lock); - if (ret < 0) - { - return (ssize_t)ret; - } - - /* Handle IN and OUT transfer slightly differently */ - - if (priv->chan[chidx].in) - { - nbytes = stm32_in_transfer(priv, chidx, buffer, buflen); - } - else - { - nbytes = stm32_out_transfer(priv, chidx, buffer, buflen); - } - - nxmutex_unlock(&priv->lock); - return nbytes; -} - -/**************************************************************************** - * Name: stm32_asynch - * - * Description: - * Process a request to handle a transfer descriptor. This method will - * enqueue the transfer request and return immediately. When the transfer - * completes, the callback will be invoked with the provided transfer. - * This method is useful for receiving interrupt transfers which may come - * infrequently. - * - * Only one transfer may be queued; Neither this method nor the ctrlin or - * ctrlout methods can be called again until the transfer completes. - * - * Input Parameters: - * drvr - The USB host driver instance obtained as a parameter from the - * call to the class create() method. - * ep - The IN or OUT endpoint descriptor for the device endpoint on - * which to perform the transfer. - * buffer - A buffer containing the data to be sent (OUT endpoint) or - * received (IN endpoint). buffer must have been allocated using - * DRVR_ALLOC - * buflen - The length of the data to be sent or received. - * callback - This function will be called when the transfer completes. - * arg - The arbitrary parameter that will be passed to the callback - * function when the transfer completes. - * - * Returned Value: - * On success, zero (OK) is returned. On a failure, a negated errno value - * is returned indicating the nature of the failure - * - * Assumptions: - * - Called from a single thread so no mutual exclusion is required. - * - Never called from an interrupt handler. - * - ****************************************************************************/ - -#ifdef CONFIG_USBHOST_ASYNCH -static int stm32_asynch(struct usbhost_driver_s *drvr, usbhost_ep_t ep, - uint8_t *buffer, size_t buflen, - usbhost_asynch_t callback, void *arg) -{ - struct stm32_usbhost_s *priv = (struct stm32_usbhost_s *)drvr; - unsigned int chidx = (unsigned int)ep; - int ret; - - uinfo("chidx: %d buflen: %d\n", (unsigned int)ep, buflen); - - DEBUGASSERT(priv && buffer && chidx < STM32_MAX_TX_FIFOS && buflen > 0); - - /* We must have exclusive access to the USB host hardware and structures */ - - ret = nxmutex_lock(&priv->lock); - if (ret < 0) - { - return ret; - } - - /* Handle IN and OUT transfer slightly differently */ - - if (priv->chan[chidx].in) - { - ret = stm32_in_asynch(priv, chidx, buffer, buflen, callback, arg); - } - else - { - ret = stm32_out_asynch(priv, chidx, buffer, buflen, callback, arg); - } - - nxmutex_unlock(&priv->lock); - return ret; -} -#endif /* CONFIG_USBHOST_ASYNCH */ - -/**************************************************************************** - * Name: stm32_cancel - * - * Description: - * Cancel a pending transfer on an endpoint. Cancelled synchronous or - * asynchronous transfer will complete normally with the error -ESHUTDOWN. - * - * Input Parameters: - * drvr - The USB host driver instance obtained as a parameter from the - * call to the class create() method. - * ep - The IN or OUT endpoint descriptor for the device endpoint on - * which an asynchronous transfer should be transferred. - * - * Returned Value: - * On success, zero (OK) is returned. On a failure, a negated errno value - * is returned indicating the nature of the failure - * - ****************************************************************************/ - -static int stm32_cancel(struct usbhost_driver_s *drvr, usbhost_ep_t ep) -{ - struct stm32_usbhost_s *priv = (struct stm32_usbhost_s *)drvr; - struct stm32_chan_s *chan; - unsigned int chidx = (unsigned int)ep; - irqstate_t flags; - - uinfo("chidx: %u\n", chidx); - - DEBUGASSERT(priv && chidx < STM32_MAX_TX_FIFOS); - chan = &priv->chan[chidx]; - - /* We need to disable interrupts to avoid race conditions with the - * asynchronous completion of the transfer being cancelled. - */ - - flags = enter_critical_section(); - - /* Halt the channel */ - - stm32_chan_halt(priv, chidx, CHREASON_CANCELLED); - chan->result = -ESHUTDOWN; - - /* Is there a thread waiting for this transfer to complete? */ - - if (chan->waiter) - { -#ifdef CONFIG_USBHOST_ASYNCH - /* Yes.. there should not also be a callback scheduled */ - - DEBUGASSERT(chan->callback == NULL); -#endif - - /* Wake'em up! */ - - nxsem_post(&chan->waitsem); - chan->waiter = false; - } - -#ifdef CONFIG_USBHOST_ASYNCH - /* No.. is an asynchronous callback expected when the transfer - * completes? - */ - - else if (chan->callback) - { - usbhost_asynch_t callback; - void *arg; - - /* Extract the callback information */ - - callback = chan->callback; - arg = chan->arg; - - chan->callback = NULL; - chan->arg = NULL; - chan->xfrd = 0; - - /* Then perform the callback */ - - callback(arg, -ESHUTDOWN); - } -#endif - - leave_critical_section(flags); - return OK; -} - -/**************************************************************************** - * Name: stm32_connect - * - * Description: - * New connections may be detected by an attached hub. This method is the - * mechanism that is used by the hub class to introduce a new connection - * and port description to the system. - * - * Input Parameters: - * drvr - The USB host driver instance obtained as a parameter from the - * call to the class create() method. - * hport - The descriptor of the hub port that detected the connection - * related event - * connected - True: device connected; false: device disconnected - * - * Returned Value: - * On success, zero (OK) is returned. On a failure, a negated errno value - * is returned indicating the nature of the failure - * - ****************************************************************************/ - -#ifdef CONFIG_USBHOST_HUB -static int stm32_connect(struct usbhost_driver_s *drvr, - struct usbhost_hubport_s *hport, - bool connected) -{ - struct stm32_usbhost_s *priv = (struct stm32_usbhost_s *)drvr; - irqstate_t flags; - - DEBUGASSERT(priv != NULL && hport != NULL); - - /* Set the connected/disconnected flag */ - - hport->connected = connected; - uinfo("Hub port %d connected: %s\n", - hport->port, connected ? "YES" : "NO"); - - /* Report the connection event */ - - flags = enter_critical_section(); - priv->hport = hport; - if (priv->pscwait) - { - priv->pscwait = false; - nxsem_post(&priv->pscsem); - } - - leave_critical_section(flags); - return OK; -} -#endif - -/**************************************************************************** - * Name: stm32_disconnect - * - * Description: - * Called by the class when an error occurs and driver has been - * disconnected. The USB host driver should discard the handle to the - * class instance (it is stale) and not attempt any further interaction - * with the class driver instance (until a new instance is received from - * the create() method). The driver should not called the class' - * disconnected() method. - * - * Input Parameters: - * drvr - The USB host driver instance obtained as a parameter from the - * call to the class create() method. - * hport - The port from which the device is being disconnected. Might be - * a port on a hub. - * - * Returned Value: - * None - * - * Assumptions: - * - Only a single class bound to a single device is supported. - * - Never called from an interrupt handler. - * - ****************************************************************************/ - -static void stm32_disconnect(struct usbhost_driver_s *drvr, - struct usbhost_hubport_s *hport) -{ - DEBUGASSERT(hport != NULL); - hport->devclass = NULL; -} - -/**************************************************************************** - * Name: stm32_portreset - * - * Description: - * Reset the USB host port. - * - * NOTE: "Before starting to drive a USB reset, the application waits for - * the OTG interrupt triggered by the debounce done bit (DBCDNE bit in - * OTG_HS_GOTGINT), which indicates that the bus is stable again after the - * electrical debounce caused by the attachment of a pull-up resistor on DP - * (HS) or DM (LS). - * - * Input Parameters: - * priv -- USB host driver private data structure. - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void stm32_portreset(struct stm32_usbhost_s *priv) -{ - uint32_t regval; - - regval = stm32_getreg(STM32_OTGHS_HPRT); - regval &= ~(OTGHS_HPRT_PENA | OTGHS_HPRT_PCDET | OTGHS_HPRT_PENCHNG | - OTGHS_HPRT_POCCHNG); - regval |= OTGHS_HPRT_PRST; - stm32_putreg(STM32_OTGHS_HPRT, regval); - - up_mdelay(20); - - regval &= ~OTGHS_HPRT_PRST; - stm32_putreg(STM32_OTGHS_HPRT, regval); - - up_mdelay(20); -} - -/**************************************************************************** - * Name: stm32_flush_txfifos - * - * Description: - * Flush the selected Tx FIFO. - * - * Input Parameters: - * txfnum -- USB host driver private data structure. - * - * Returned Value: - * None. - * - ****************************************************************************/ - -static void stm32_flush_txfifos(uint32_t txfnum) -{ - uint32_t regval; - uint32_t timeout; - - /* Initiate the TX FIFO flush operation */ - - regval = OTGHS_GRSTCTL_TXFFLSH | txfnum; - stm32_putreg(STM32_OTGHS_GRSTCTL, regval); - - /* Wait for the FLUSH to complete */ - - for (timeout = 0; timeout < STM32_FLUSH_DELAY; timeout++) - { - regval = stm32_getreg(STM32_OTGHS_GRSTCTL); - if ((regval & OTGHS_GRSTCTL_TXFFLSH) == 0) - { - break; - } - } - - /* Wait for 3 PHY Clocks */ - - up_udelay(3); -} - -/**************************************************************************** - * Name: stm32_flush_rxfifo - * - * Description: - * Flush the Rx FIFO. - * - * Input Parameters: - * priv -- USB host driver private data structure. - * - * Returned Value: - * None. - * - ****************************************************************************/ - -static void stm32_flush_rxfifo(void) -{ - uint32_t regval; - uint32_t timeout; - - /* Initiate the RX FIFO flush operation */ - - stm32_putreg(STM32_OTGHS_GRSTCTL, OTGHS_GRSTCTL_RXFFLSH); - - /* Wait for the FLUSH to complete */ - - for (timeout = 0; timeout < STM32_FLUSH_DELAY; timeout++) - { - regval = stm32_getreg(STM32_OTGHS_GRSTCTL); - if ((regval & OTGHS_GRSTCTL_RXFFLSH) == 0) - { - break; - } - } - - /* Wait for 3 PHY Clocks */ - - up_udelay(3); -} - -/**************************************************************************** - * Name: stm32_vbusdrive - * - * Description: - * Drive the Vbus +5V. - * - * Input Parameters: - * priv - USB host driver private data structure. - * state - True: Drive, False: Don't drive - * - * Returned Value: - * None. - * - ****************************************************************************/ - -static void stm32_vbusdrive(struct stm32_usbhost_s *priv, bool state) -{ - uint32_t regval; - - /* Enable/disable the external charge pump */ - - stm32_usbhost_vbusdrive(0, state); - - /* Turn on the Host port power. */ - - regval = stm32_getreg(STM32_OTGHS_HPRT); - regval &= ~(OTGHS_HPRT_PENA | OTGHS_HPRT_PCDET | OTGHS_HPRT_PENCHNG | - OTGHS_HPRT_POCCHNG); - - if (((regval & OTGHS_HPRT_PPWR) == 0) && state) - { - regval |= OTGHS_HPRT_PPWR; - stm32_putreg(STM32_OTGHS_HPRT, regval); - } - - if (((regval & OTGHS_HPRT_PPWR) != 0) && !state) - { - regval &= ~OTGHS_HPRT_PPWR; - stm32_putreg(STM32_OTGHS_HPRT, regval); - } - - up_mdelay(200); -} - -/**************************************************************************** - * Name: stm32_host_initialize - * - * Description: - * Initialize/re-initialize hardware for host mode operation. At present, - * this function is called only from stm32_hw_initialize(). But if OTG - * mode were supported, this function would also be called to switch - * between host and device modes on a connector ID change interrupt. - * - * Input Parameters: - * priv -- USB host driver private data structure. - * - * Returned Value: - * None. - * - ****************************************************************************/ - -static void stm32_host_initialize(struct stm32_usbhost_s *priv) -{ - uint32_t regval; - uint32_t offset; - int i; - - /* Restart the PHY Clock */ - - stm32_putreg(STM32_OTGHS_PCGCCTL, 0); - - /* Initialize Host Configuration (HCFG) register */ - - regval = stm32_getreg(STM32_OTGHS_HCFG); - regval &= ~OTGHS_HCFG_FSLSPCS_MASK; - regval |= OTGHS_HCFG_FSLSPCS_FS48MHz; - stm32_putreg(STM32_OTGHS_HCFG, regval); - - /* Reset the host port */ - - stm32_portreset(priv); - - /* Clear the HS-/LS-only support bit in the HCFG register */ - - regval = stm32_getreg(STM32_OTGHS_HCFG); - regval &= ~OTGHS_HCFG_FSLSS; - stm32_putreg(STM32_OTGHS_HCFG, regval); - - /* Carve up FIFO memory for the Rx FIFO and the periodic and non-periodic - * Tx FIFOs - */ - - /* Configure Rx FIFO size (GRXHSIZ) */ - - stm32_putreg(STM32_OTGHS_GRXFSIZ, CONFIG_STM32_OTGHS_RXFIFO_SIZE); - offset = CONFIG_STM32_OTGHS_RXFIFO_SIZE; - - /* Setup the host non-periodic Tx FIFO size (HNPTXHSIZ) */ - - regval = (offset | - (CONFIG_STM32_OTGHS_NPTXFIFO_SIZE << - OTGHS_HNPTXFSIZ_NPTXFD_SHIFT)); - stm32_putreg(STM32_OTGHS_HNPTXFSIZ, regval); - offset += CONFIG_STM32_OTGHS_NPTXFIFO_SIZE; - - /* Set up the host periodic Tx fifo size register (HPTXHSIZ) */ - - regval = (offset | - (CONFIG_STM32_OTGHS_PTXFIFO_SIZE << - OTGHS_HPTXFSIZ_PTXFD_SHIFT)); - stm32_putreg(STM32_OTGHS_HPTXFSIZ, regval); - - /* If OTG were supported, we should need to clear HNP enable bit in the - * USB_OTG control register about here. - */ - - /* Flush all FIFOs */ - - stm32_flush_txfifos(OTGHS_GRSTCTL_TXFNUM_HALL); - stm32_flush_rxfifo(); - - /* Clear all pending HC Interrupts */ - - for (i = 0; i < STM32_NHOST_CHANNELS; i++) - { - stm32_putreg(STM32_OTGHS_HCINT(i), 0xffffffff); - stm32_putreg(STM32_OTGHS_HCINTMSK(i), 0); - } - - /* Driver Vbus +5V (the smoke test). Should be done elsewhere in OTG - * mode. - */ - - stm32_vbusdrive(priv, true); - - /* Enable host interrupts */ - - stm32_hostinit_enable(); -} - -/**************************************************************************** - * Name: stm32_sw_initialize - * - * Description: - * One-time setup of the host driver state structure. - * - * Input Parameters: - * priv -- USB host driver private data structure. - * - * Returned Value: - * None. - * - ****************************************************************************/ - -static inline void stm32_sw_initialize(struct stm32_usbhost_s *priv) -{ - struct usbhost_driver_s *drvr; - struct usbhost_hubport_s *hport; - int i; - - /* Initialize the device operations */ - - drvr = &priv->drvr; - drvr->ep0configure = stm32_ep0configure; - drvr->epalloc = stm32_epalloc; - drvr->epfree = stm32_epfree; - drvr->alloc = stm32_alloc; - drvr->free = stm32_free; - drvr->ioalloc = stm32_ioalloc; - drvr->iofree = stm32_iofree; - drvr->ctrlin = stm32_ctrlin; - drvr->ctrlout = stm32_ctrlout; - drvr->transfer = stm32_transfer; -#ifdef CONFIG_USBHOST_ASYNCH - drvr->asynch = stm32_asynch; -#endif - drvr->cancel = stm32_cancel; -#ifdef CONFIG_USBHOST_HUB - drvr->connect = stm32_connect; -#endif - drvr->disconnect = stm32_disconnect; - - /* Initialize the public port representation */ - - hport = &priv->rhport.hport; - hport->drvr = drvr; -#ifdef CONFIG_USBHOST_HUB - hport->parent = NULL; -#endif - hport->ep0 = (usbhost_ep_t)&priv->ep0; - hport->speed = USB_SPEED_FULL; - - /* Initialize function address generation logic */ - - usbhost_devaddr_initialize(&priv->devgen); - priv->rhport.pdevgen = &priv->devgen; - - /* Initialize the driver state data */ - - priv->smstate = SMSTATE_DETACHED; - priv->connected = false; - priv->change = false; - - /* Put all of the channels back in their initial, allocated state */ - - memset(priv->chan, 0, STM32_MAX_TX_FIFOS * sizeof(struct stm32_chan_s)); - - /* Initialize each channel */ - - for (i = 0; i < STM32_MAX_TX_FIFOS; i++) - { - struct stm32_chan_s *chan = &priv->chan[i]; - - chan->chidx = i; - nxsem_init(&chan->waitsem, 0, 0); - } -} - -/**************************************************************************** - * Name: stm32_hw_initialize - * - * Description: - * One-time setup of the host controller hardware for normal operations. - * - * Input Parameters: - * priv -- USB host driver private data structure. - * - * Returned Value: - * Zero on success; a negated errno value on failure. - * - ****************************************************************************/ - -static inline int stm32_hw_initialize(struct stm32_usbhost_s *priv) -{ - uint32_t regval; - unsigned long timeout; - - /* Set the PHYSEL bit in the GUSBCFG register to select the OTG HS serial - * transceiver: "This bit is always 1 with write-only access" - */ - - regval = stm32_getreg(STM32_OTGHS_GUSBCFG); - regval |= OTGHS_GUSBCFG_PHYSEL; - stm32_putreg(STM32_OTGHS_GUSBCFG, regval); - - /* Reset after a PHY select and set Host mode. First, wait for AHB master - * IDLE state. - */ - - for (timeout = 0; timeout < STM32_READY_DELAY; timeout++) - { - up_udelay(3); - regval = stm32_getreg(STM32_OTGHS_GRSTCTL); - if ((regval & OTGHS_GRSTCTL_AHBIDL) != 0) - { - break; - } - } - - /* Then perform the core soft reset. */ - - stm32_putreg(STM32_OTGHS_GRSTCTL, OTGHS_GRSTCTL_CSRST); - for (timeout = 0; timeout < STM32_READY_DELAY; timeout++) - { - regval = stm32_getreg(STM32_OTGHS_GRSTCTL); - if ((regval & OTGHS_GRSTCTL_CSRST) == 0) - { - break; - } - } - - /* Wait for 3 PHY Clocks */ - - up_udelay(3); - - /* Deactivate the power down */ - - regval = OTGHS_GCCFG_PWRDWN | OTGHS_GCCFG_VBUSASEN | - OTGHS_GCCFG_VBUSBSEN; -#ifndef CONFIG_USBDEV_VBUSSENSING - regval |= OTGHS_GCCFG_NOVBUSSENS; -#endif -#ifdef CONFIG_STM32_OTGHS_SOFOUTPUT - regval |= OTGHS_GCCFG_SOFOUTEN; -#endif - stm32_putreg(STM32_OTGHS_GCCFG, regval); - up_mdelay(20); - - /* Initialize OTG features: In order to support OTP, the HNPCAP and SRPCAP - * bits would need to be set in the GUSBCFG register about here. - */ - - /* Force Host Mode */ - - regval = stm32_getreg(STM32_OTGHS_GUSBCFG); - regval &= ~OTGHS_GUSBCFG_FDMOD; - regval |= OTGHS_GUSBCFG_FHMOD; - stm32_putreg(STM32_OTGHS_GUSBCFG, regval); - up_mdelay(50); - - /* Initialize host mode and return success */ - - stm32_host_initialize(priv); - return OK; -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_otghshost_initialize - * - * Description: - * Initialize USB host device controller hardware. - * - * Input Parameters: - * controller -- If the device supports more than USB host controller, then - * this identifies which controller is being initialized. Normally, this - * is just zero. - * - * Returned Value: - * And instance of the USB host interface. The controlling task should - * use this interface to (1) call the wait() method to wait for a device - * to be connected, and (2) call the enumerate() method to bind the device - * to a class driver. - * - * Assumptions: - * - This function should called in the initialization sequence in order - * to initialize the USB device functionality. - * - Class drivers should be initialized prior to calling this function. - * Otherwise, there is a race condition if the device is already connected. - * - ****************************************************************************/ - -struct usbhost_connection_s *stm32_otghshost_initialize(int controller) -{ - /* At present, there is only support for a single OTG HS host. Hence it is - * pre-allocated as g_usbhost. However, in most code, the private data - * structure will be referenced using the 'priv' pointer (rather than the - * global data) in order to simplify any future support for multiple - * devices. - */ - - struct stm32_usbhost_s *priv = &g_usbhost; - - /* Sanity checks */ - - DEBUGASSERT(controller == 0); - - /* Make sure that interrupts from the OTG HS core are disabled */ - - stm32_gint_disable(); - - /* Reset the state of the host driver */ - - stm32_sw_initialize(priv); - - /* Alternate function pin configuration. Here we assume that: - * - * 1. GPIOA, SYSCFG, and OTG HS peripheral clocking have already been\ - * enabled as part of the boot sequence. - * 2. Board-specific logic has already enabled other board specific GPIOs - * for things like soft pull-up, VBUS sensing, power controls, and over- - * current detection. - */ - - /* Configure OTG HS alternate function pins for DM, DP, ID, and SOF. - * - * PIN* SIGNAL DIRECTION - * ---- ----------- ---------- - * PA8 OTG_HS_SOF SOF clock output - * PA9 OTG_HS_VBUS VBUS input for device, Driven by external regulator by - * host (not an alternate function) - * PA10 OTG_HS_ID OTG ID pin (only needed in Dual mode) - * PA11 OTG_HS_DM D- I/O - * PA12 OTG_HS_DP D+ I/O - * - * *Pins may vary from device-to-device. - */ - - stm32_configgpio(GPIO_OTGHSFS_DM); - stm32_configgpio(GPIO_OTGHSFS_DP); -#if 0 /* Only needed for OTG */ - stm32_configgpio(GPIO_OTGHSFS_ID); -#endif - - /* SOF output pin configuration is configurable */ - -#ifdef CONFIG_STM32_OTGHS_SOFOUTPUT - stm32_configgpio(GPIO_OTGHSFS_SOF); -#endif - - /* Initialize the USB OTG HS core */ - - stm32_hw_initialize(priv); - - /* Attach USB host controller interrupt handler */ - - if (irq_attach(STM32_IRQ_OTGHS, stm32_gint_isr, NULL) != 0) - { - usbhost_trace1(OTGHS_TRACE1_IRQATTACH, 0); - return NULL; - } - - /* Enable USB OTG HS global interrupts */ - - stm32_gint_enable(); - - /* Enable interrupts at the interrupt controller */ - - up_enable_irq(STM32_IRQ_OTGHS); - return &g_usbconn; -} - -#endif /* CONFIG_STM32_USBHOST && CONFIG_STM32_OTGHS */ diff --git a/arch/arm/src/stm32/stm32_pminitialize.c b/arch/arm/src/stm32/stm32_pminitialize.c deleted file mode 100644 index 2f9883b2123d0..0000000000000 --- a/arch/arm/src/stm32/stm32_pminitialize.c +++ /dev/null @@ -1,64 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_pminitialize.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include - -#include "arm_internal.h" -#include "stm32_pm.h" - -#ifdef CONFIG_PM - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: arm_pminitialize - * - * Description: - * This function is called by MCU-specific logic at power-on reset in - * order to provide one-time initialization the power management subsystem. - * This function must be called *very* early in the initialization sequence - * *before* any other device drivers are initialized (since they may - * attempt to register with the power management subsystem). - * - * Input Parameters: - * None. - * - * Returned Value: - * None. - * - ****************************************************************************/ - -void arm_pminitialize(void) -{ - /* Initialize the NuttX power management subsystem proper */ - - pm_initialize(); -} - -#endif /* CONFIG_PM */ diff --git a/arch/arm/src/stm32/stm32_pmsleep.c b/arch/arm/src/stm32/stm32_pmsleep.c deleted file mode 100644 index 5f78cc8626884..0000000000000 --- a/arch/arm/src/stm32/stm32_pmsleep.c +++ /dev/null @@ -1,99 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_pmsleep.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include "arm_internal.h" -#include "nvic.h" -#include "stm32_pwr.h" -#include "stm32_pm.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_pmsleep - * - * Description: - * Enter SLEEP mode. - * - * Input Parameters: - * sleeponexit - true: SLEEPONEXIT bit is set when the WFI instruction is - * executed, the MCU enters Sleep mode as soon as it - * exits the lowest priority ISR. - * - false: SLEEPONEXIT bit is cleared, the MCU enters Sleep - * mode as soon as WFI or WFE instruction is executed. - * Returned Value: - * None - * - ****************************************************************************/ - -void stm32_pmsleep(bool sleeponexit) -{ - uint32_t regval; - - /* Clear SLEEPDEEP bit of Cortex System Control Register */ - - regval = getreg32(NVIC_SYSCON); - regval &= ~NVIC_SYSCON_SLEEPDEEP; - if (sleeponexit) - { - regval |= NVIC_SYSCON_SLEEPONEXIT; - } - else - { - regval &= ~NVIC_SYSCON_SLEEPONEXIT; - } - - putreg32(regval, NVIC_SYSCON); - - /* Sleep until the wakeup interrupt or event occurs */ - -#ifdef CONFIG_PM_WFE - /* Mode: SLEEP + Entry with WFE */ - - asm("wfe"); -#else - /* Mode: SLEEP + Entry with WFI */ - - asm("wfi"); -#endif -} diff --git a/arch/arm/src/stm32/stm32_pmstandby.c b/arch/arm/src/stm32/stm32_pmstandby.c deleted file mode 100644 index d8b9825aed5e1..0000000000000 --- a/arch/arm/src/stm32/stm32_pmstandby.c +++ /dev/null @@ -1,98 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_pmstandby.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include "arm_internal.h" -#include "nvic.h" -#include "stm32_pwr.h" -#include "stm32_pm.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_pmstandby - * - * Description: - * Enter STANDBY mode. - * - * Input Parameters: - * None - * - * Returned Value: - * On success, this function will not return (STANDBY mode can only be - * terminated with a reset event). Otherwise, STANDBY mode did not occur - * and a negated errno value is returned to indicate the cause of the - * failure. - * - ****************************************************************************/ - -int stm32_pmstandby(void) -{ - uint32_t regval; - - /* Clear the Wake-Up Flag by setting the CWUF bit in the power control - * register. - */ - - regval = getreg32(STM32_PWR_CR); - regval |= PWR_CR_CWUF; - putreg32(regval, STM32_PWR_CR); - - /* Set the Power Down Deep Sleep (PDDS) bit in the power control - * register. - */ - - regval |= PWR_CR_PDDS; - putreg32(regval, STM32_PWR_CR); - - /* Set SLEEPDEEP bit of Cortex System Control Register */ - - regval = getreg32(NVIC_SYSCON); - regval |= NVIC_SYSCON_SLEEPDEEP; - putreg32(regval, NVIC_SYSCON); - - /* Sleep until the wakeup reset occurs */ - - asm("wfi"); - return OK; /* Won't get here */ -} diff --git a/arch/arm/src/stm32/stm32_pmstop.c b/arch/arm/src/stm32/stm32_pmstop.c deleted file mode 100644 index 9acf05990f9aa..0000000000000 --- a/arch/arm/src/stm32/stm32_pmstop.c +++ /dev/null @@ -1,109 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_pmstop.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include "arm_internal.h" -#include "nvic.h" -#include "stm32_pwr.h" -#include "stm32_pm.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_pmstop - * - * Description: - * Enter STOP mode. - * - * Input Parameters: - * lpds - true: To further reduce power consumption in Stop mode, put the - * internal voltage regulator in low-power mode using the LPDS bit - * of the Power control register (PWR_CR). - * - * Returned Value: - * Zero means that the STOP was successfully entered and the system has - * been re-awakened. The internal voltage regulator is back to its - * original state. Otherwise, STOP mode did not occur and a negated - * errno value is returned to indicate the cause of the failure. - * - ****************************************************************************/ - -int stm32_pmstop(bool lpds) -{ - uint32_t regval; - - /* Clear the Power Down Deep Sleep (PDDS) and the Low Power Deep Sleep - * (LPDS)) bits in the power control register. - */ - - regval = getreg32(STM32_PWR_CR); - regval &= ~(PWR_CR_LPDS | PWR_CR_PDDS); - - /* Set the Low Power Deep Sleep (LPDS) bit if so requested */ - - if (lpds) - { - regval |= PWR_CR_LPDS; - } - - putreg32(regval, STM32_PWR_CR); - - /* Set SLEEPDEEP bit of Cortex System Control Register */ - - regval = getreg32(NVIC_SYSCON); - regval |= NVIC_SYSCON_SLEEPDEEP; - putreg32(regval, NVIC_SYSCON); - - /* Sleep until the wakeup interrupt or event occurs */ - -#ifdef CONFIG_PM_WFE - /* Mode: SLEEP + Entry with WFE */ - - asm("wfe"); -#else - /* Mode: SLEEP + Entry with WFI */ - - asm("wfi"); -#endif - return OK; -} diff --git a/arch/arm/src/stm32/stm32_pulsecount.c b/arch/arm/src/stm32/stm32_pulsecount.c deleted file mode 100644 index c8aea22c4e19e..0000000000000 --- a/arch/arm/src/stm32/stm32_pulsecount.c +++ /dev/null @@ -1,1775 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_pulsecount.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include -#include - -#include -#include - -#include "arm_internal.h" -#include "chip.h" -#include "stm32_pulsecount.h" -#include "stm32_rcc.h" -#include "stm32_gpio.h" -#include "stm32_tim.h" - -/* This module then only compiles if there is at least one enabled timer - * intended for use with the pulsecount upper half driver. - * - * It implements support for both: - * 1. STM32 TIMER IP version 1 - F0, F1, F2, F37x, F4, L0, L1 - * 2. STM32 TIMER IP version 2 - F3 (no F37x), F7, H7, L4, L4+ - */ - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Timer Definitions ********************************************************/ - -/* Pulsecount is supported by advanced timers only. */ - -#define TIMTYPE_ADVANCED 5 -#define TIMTYPE_TIM1 TIMTYPE_ADVANCED -#define TIMTYPE_TIM8 TIMTYPE_ADVANCED - -/* Advanced timer clock source, RCC EN offset, enable bit, - * RCC RST offset, reset bit to use - */ - -# define TIMCLK_TIM1 STM32_APB2_TIM1_CLKIN -# define TIMRCCEN_TIM1 STM32_RCC_APB2ENR -# define TIMEN_TIM1 RCC_APB2ENR_TIM1EN -# define TIMRCCRST_TIM1 STM32_RCC_APB2RSTR -# define TIMRST_TIM1 RCC_APB2RSTR_TIM1RST -# define TIMCLK_TIM8 STM32_APB2_TIM8_CLKIN -# define TIMRCCEN_TIM8 STM32_RCC_APB2ENR -# define TIMEN_TIM8 RCC_APB2ENR_TIM8EN -# define TIMRCCRST_TIM8 STM32_RCC_APB2RSTR -# define TIMRST_TIM8 RCC_APB2RSTR_TIM8RST - -/* Default GPIO pins state */ - -#if defined(CONFIG_STM32_STM32F10XX) -# define PINCFG_DEFAULT (GPIO_INPUT | GPIO_CNF_INFLOAT | GPIO_MODE_INPUT) -#elif defined(CONFIG_STM32_STM32F20XX) || \ - defined(CONFIG_STM32_STM32F30XX) || \ - defined(CONFIG_STM32_STM32F33XX) || \ - defined(CONFIG_STM32_STM32F37XX) || \ - defined(CONFIG_STM32_STM32F4XXX) || \ - defined(CONFIG_STM32_STM32L15XX) || \ - defined(CONFIG_STM32_STM32G4XXX) -# define PINCFG_DEFAULT (GPIO_INPUT | GPIO_FLOAT) -#else -# error "Unrecognized STM32 chip" -#endif - -#define PULSECOUNT_POL_NEG 1 -#define PULSECOUNT_IDLE_ACTIVE 1 - -/* Debug ********************************************************************/ - -#ifdef CONFIG_DEBUG_TIMER_INFO -# define pulsecount_dumpgpio(p,m) stm32_dumpgpio(p,m) -#else -# define pulsecount_dumpgpio(p,m) -#endif - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/* Pulsecount output configuration */ - -struct stm32_out_s -{ - uint8_t in_use:1; - uint8_t pol:1; - uint8_t idle:1; - uint8_t _res:5; - uint32_t pincfg; -}; - -/* Pulsecount channel configuration */ - -struct stm32_chan_s -{ - uint8_t channel; - struct stm32_out_s out1; -}; - -/* This structure represents the state of one pulsecount timer */ - -struct stm32_tim_s -{ - struct stm32_chan_s channel; - uint8_t timid:5; - uint8_t timtype:3; - uint8_t t_dts:3; - uint8_t _res:5; - uint8_t irq; - uint8_t prev; - uint8_t curr; - uint32_t count; - uint32_t frequency; - uint32_t base; - uint32_t pclk; - void *handle; -}; - -struct stm32_pulsecount_s -{ - const struct pulsecount_ops_s *ops; - struct stm32_tim_s *timer; -}; - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -/* Register access */ - -static uint32_t pulsecount_getreg(struct stm32_tim_s *priv, int offset); -static void pulsecount_putreg(struct stm32_tim_s *priv, int offset, - uint32_t value); -static void pulsecount_modifyreg(struct stm32_tim_s *priv, uint32_t offset, - uint32_t clearbits, uint32_t setbits); - -#ifdef CONFIG_DEBUG_TIMER_INFO -static void pulsecount_dumpregs(struct pulsecount_lowerhalf_s *dev, - const char *msg); -#else -# define pulsecount_dumpregs(priv,msg) -#endif - -/* Timer management */ - -static int pulsecount_ccr_update(struct pulsecount_lowerhalf_s *dev, - uint8_t index, uint32_t ccr); -static int pulsecount_duty_update(struct pulsecount_lowerhalf_s *dev, - uint8_t channel, ub16_t duty); -static int pulsecount_frequency_update(struct pulsecount_lowerhalf_s *dev, - uint32_t frequency); -static int pulsecount_timer_configure(struct stm32_tim_s *priv); -static int pulsecount_channel_configure(struct pulsecount_lowerhalf_s *dev, - uint8_t channel); -static int pulsecount_output_configure(struct stm32_tim_s *priv, - struct stm32_chan_s *chan); -static int pulsecount_outputs_enable(struct pulsecount_lowerhalf_s *dev, - uint16_t outputs, bool state); -static void pulsecount_moe_enable(struct pulsecount_lowerhalf_s *dev, - bool enable); -static int pulsecount_configure(struct pulsecount_lowerhalf_s *dev); -static int pulsecount_timer(struct pulsecount_lowerhalf_s *dev, - const struct pulsecount_info_s *info); -static int pulsecount_interrupt(struct pulsecount_lowerhalf_s *dev); -# ifdef CONFIG_STM32_TIM1_PULSECOUNT -static int pulsecount_tim1interrupt(int irq, void *context, void *arg); -# endif -# ifdef CONFIG_STM32_TIM8_PULSECOUNT -static int pulsecount_tim8interrupt(int irq, void *context, void *arg); -# endif -static uint8_t pulsecount_count(uint32_t count); - -/* Pulsecount driver methods */ - -static int pulsecount_ll_setup(struct pulsecount_lowerhalf_s *dev); -static int pulsecount_ll_shutdown(struct pulsecount_lowerhalf_s *dev); - -static int pulsecount_ll_stop(struct pulsecount_lowerhalf_s *dev); -static int pulsecount_ll_ioctl(struct pulsecount_lowerhalf_s *dev, - int cmd, unsigned long arg); - -static int pulsecount_setup(struct pulsecount_lowerhalf_s *dev); -static int pulsecount_shutdown(struct pulsecount_lowerhalf_s *dev); -static int pulsecount_start(struct pulsecount_lowerhalf_s *dev, - const struct pulsecount_info_s *info, - void *handle); -static int pulsecount_stop(struct pulsecount_lowerhalf_s *dev); -static int pulsecount_ioctl(struct pulsecount_lowerhalf_s *dev, - int cmd, unsigned long arg); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -#ifdef CONFIG_STM32_TIM1_PULSECOUNT - -static struct stm32_tim_s g_pulsecount1dev = -{ - .channel = - { - .channel = CONFIG_STM32_TIM1_PULSECOUNT_CHANNEL, -#if CONFIG_STM32_TIM1_PULSECOUNT_CHANNEL == 1 - .out1 = - { - .in_use = 1, - .pol = CONFIG_STM32_TIM1_PULSECOUNT_POL, - .idle = CONFIG_STM32_TIM1_PULSECOUNT_IDLE, - .pincfg = GPIO_TIM1_CH1OUT, - }, -#elif CONFIG_STM32_TIM1_PULSECOUNT_CHANNEL == 2 - .out1 = - { - .in_use = 1, - .pol = CONFIG_STM32_TIM1_PULSECOUNT_POL, - .idle = CONFIG_STM32_TIM1_PULSECOUNT_IDLE, - .pincfg = GPIO_TIM1_CH2OUT, - }, -#elif CONFIG_STM32_TIM1_PULSECOUNT_CHANNEL == 3 - .out1 = - { - .in_use = 1, - .pol = CONFIG_STM32_TIM1_PULSECOUNT_POL, - .idle = CONFIG_STM32_TIM1_PULSECOUNT_IDLE, - .pincfg = GPIO_TIM1_CH3OUT, - }, -#elif CONFIG_STM32_TIM1_PULSECOUNT_CHANNEL == 4 - .out1 = - { - .in_use = 1, - .pol = CONFIG_STM32_TIM1_PULSECOUNT_POL, - .idle = CONFIG_STM32_TIM1_PULSECOUNT_IDLE, - .pincfg = GPIO_TIM1_CH4OUT, - }, -#endif - }, - .timid = 1, - .timtype = TIMTYPE_TIM1, - .t_dts = CONFIG_STM32_TIM1_PULSECOUNT_TDTS, - .irq = STM32_IRQ_TIM1UP, - .base = STM32_TIM1_BASE, - .pclk = TIMCLK_TIM1, -}; - -#endif /* CONFIG_STM32_TIM1_PULSECOUNT */ - -#ifdef CONFIG_STM32_TIM8_PULSECOUNT - -static struct stm32_tim_s g_pulsecount8dev = -{ - .channel = - { - .channel = CONFIG_STM32_TIM8_PULSECOUNT_CHANNEL, -#if CONFIG_STM32_TIM8_PULSECOUNT_CHANNEL == 1 - .out1 = - { - .in_use = 1, - .pol = CONFIG_STM32_TIM8_PULSECOUNT_POL, - .idle = CONFIG_STM32_TIM8_PULSECOUNT_IDLE, - .pincfg = GPIO_TIM8_CH1OUT, - }, -#elif CONFIG_STM32_TIM8_PULSECOUNT_CHANNEL == 2 - .out1 = - { - .in_use = 1, - .pol = CONFIG_STM32_TIM8_PULSECOUNT_POL, - .idle = CONFIG_STM32_TIM8_PULSECOUNT_IDLE, - .pincfg = GPIO_TIM8_CH2OUT, - }, -#elif CONFIG_STM32_TIM8_PULSECOUNT_CHANNEL == 3 - .out1 = - { - .in_use = 1, - .pol = CONFIG_STM32_TIM8_PULSECOUNT_POL, - .idle = CONFIG_STM32_TIM8_PULSECOUNT_IDLE, - .pincfg = GPIO_TIM8_CH3OUT, - }, -#elif CONFIG_STM32_TIM8_PULSECOUNT_CHANNEL == 4 - .out1 = - { - .in_use = 1, - .pol = CONFIG_STM32_TIM8_PULSECOUNT_POL, - .idle = CONFIG_STM32_TIM8_PULSECOUNT_IDLE, - .pincfg = GPIO_TIM8_CH4OUT, - }, -#endif - }, - .timid = 8, - .timtype = TIMTYPE_TIM8, - .t_dts = CONFIG_STM32_TIM8_PULSECOUNT_TDTS, - .irq = STM32_IRQ_TIM8UP, - .base = STM32_TIM8_BASE, - .pclk = TIMCLK_TIM8, -}; - -#endif /* CONFIG_STM32_TIM8_PULSECOUNT */ - -static const struct pulsecount_ops_s g_pulsecountops = -{ - .setup = pulsecount_setup, - .shutdown = pulsecount_shutdown, - .start = pulsecount_start, - .stop = pulsecount_stop, - .ioctl = pulsecount_ioctl, -}; - -#ifdef CONFIG_STM32_TIM1_PULSECOUNT -static struct stm32_pulsecount_s g_pulsecount1lower = -{ - .ops = &g_pulsecountops, - .timer = &g_pulsecount1dev, -}; -#endif - -#ifdef CONFIG_STM32_TIM8_PULSECOUNT -static struct stm32_pulsecount_s g_pulsecount8lower = -{ - .ops = &g_pulsecountops, - .timer = &g_pulsecount8dev, -}; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: pulsecount_reg_is_32bit - ****************************************************************************/ - -static bool pulsecount_reg_is_32bit(uint8_t timtype, uint32_t offset) -{ - bool ret = false; - - if (timtype == TIMTYPE_ADVANCED) - { - if (offset == STM32_ATIM_CR2_OFFSET || - offset == STM32_ATIM_CCMR1_OFFSET || - offset == STM32_ATIM_CCMR2_OFFSET || - offset == STM32_ATIM_CCER_OFFSET || - offset == STM32_ATIM_BDTR_OFFSET) - { - ret = true; - } - } - - return ret; -} - -/**************************************************************************** - * Name: pulsecount_getreg - * - * Description: - * Read the value of an pulsecount timer register - * - * Input Parameters: - * priv - A reference to the pulsecount block status - * offset - The offset to the register to read - * - * Returned Value: - * The current contents of the specified register - * - ****************************************************************************/ - -static uint32_t pulsecount_getreg(struct stm32_tim_s *priv, int offset) -{ - uint32_t retval = 0; - - if (pulsecount_reg_is_32bit(priv->timtype, offset) == true) - { - /* 32-bit register */ - - retval = getreg32(priv->base + offset); - } - else - { - /* 16-bit register */ - - retval = getreg16(priv->base + offset); - } - - /* Return 32-bit value */ - - return retval; -} - -/**************************************************************************** - * Name: pulsecount_putreg - * - * Description: - * Read the value of an pulsecount timer register - * - * Input Parameters: - * priv - A reference to the pulsecount block status - * offset - The offset to the register to read - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void pulsecount_putreg(struct stm32_tim_s *priv, int offset, - uint32_t value) -{ - if (pulsecount_reg_is_32bit(priv->timtype, offset) == true) - { - /* 32-bit register */ - - putreg32(value, priv->base + offset); - } - else - { - /* 16-bit register */ - - putreg16((uint16_t)value, priv->base + offset); - } -} - -/**************************************************************************** - * Name: pulsecount_modifyreg - * - * Description: - * Modify timer register (32-bit or 16-bit) - * - * Input Parameters: - * priv - A reference to the pulsecount block status - * offset - The offset to the register to read - * clrbits - The bits to clear - * setbits - The bits to set - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void pulsecount_modifyreg(struct stm32_tim_s *priv, uint32_t offset, - uint32_t clearbits, uint32_t setbits) -{ - if (pulsecount_reg_is_32bit(priv->timtype, offset) == true) - { - /* 32-bit register */ - - modifyreg32(priv->base + offset, clearbits, setbits); - } - else - { - /* 16-bit register */ - - modifyreg16(priv->base + offset, (uint16_t)clearbits, - (uint16_t)setbits); - } -} - -/**************************************************************************** - * Name: pulsecount_dumpregs - * - * Description: - * Dump all timer registers. - * - * Input Parameters: - * dev - A reference to the lower half pulsecount driver state structure - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef CONFIG_DEBUG_TIMER_INFO -static void pulsecount_dumpregs(struct pulsecount_lowerhalf_s *dev, - const char *msg) -{ - struct stm32_tim_s *priv = (struct stm32_tim_s *)dev; - - _info("%s:\n", msg); - _info(" CR1: %04x CR2: %04x SMCR: %04x DIER: %04x\n", - pulsecount_getreg(priv, STM32_GTIM_CR1_OFFSET), - pulsecount_getreg(priv, STM32_GTIM_CR2_OFFSET), - pulsecount_getreg(priv, STM32_GTIM_SMCR_OFFSET), - pulsecount_getreg(priv, STM32_GTIM_DIER_OFFSET)); - - _info(" SR: %04x EGR: %04x CCMR1: %04x CCMR2: %04x\n", - pulsecount_getreg(priv, STM32_GTIM_SR_OFFSET), - pulsecount_getreg(priv, STM32_GTIM_EGR_OFFSET), - pulsecount_getreg(priv, STM32_GTIM_CCMR1_OFFSET), - pulsecount_getreg(priv, STM32_GTIM_CCMR2_OFFSET)); - - _info(" CCER: %04x CNT: %04x PSC: %04x ARR: %04x\n", - pulsecount_getreg(priv, STM32_GTIM_CCER_OFFSET), - pulsecount_getreg(priv, STM32_GTIM_CNT_OFFSET), - pulsecount_getreg(priv, STM32_GTIM_PSC_OFFSET), - pulsecount_getreg(priv, STM32_GTIM_ARR_OFFSET)); - - if (priv->timid == 1 || priv->timid == 8) - { - _info(" RCR: %04x BDTR: %04x\n", - pulsecount_getreg(priv, STM32_ATIM_RCR_OFFSET), - pulsecount_getreg(priv, STM32_ATIM_BDTR_OFFSET)); - } - - _info(" CCR1: %04x CCR2: %04x CCR3: %04x CCR4: %04x\n", - pulsecount_getreg(priv, STM32_GTIM_CCR1_OFFSET), - pulsecount_getreg(priv, STM32_GTIM_CCR2_OFFSET), - pulsecount_getreg(priv, STM32_GTIM_CCR3_OFFSET), - pulsecount_getreg(priv, STM32_GTIM_CCR4_OFFSET)); - - _info(" DCR: %04x DMAR: %04x\n", - pulsecount_getreg(priv, STM32_GTIM_DCR_OFFSET), - pulsecount_getreg(priv, STM32_GTIM_DMAR_OFFSET)); -} -#endif - -/**************************************************************************** - * Name: pulsecount_ccr_update - ****************************************************************************/ - -static int pulsecount_ccr_update(struct pulsecount_lowerhalf_s *dev, - uint8_t index, uint32_t ccr) -{ - struct stm32_tim_s *priv = (struct stm32_tim_s *)dev; - uint32_t offset = 0; - - /* CCR channel indices are one-based to match timer channel numbers. */ - - switch (index) - { - case 1: - { - offset = STM32_GTIM_CCR1_OFFSET; - break; - } - - case 2: - { - offset = STM32_GTIM_CCR2_OFFSET; - break; - } - - case 3: - { - offset = STM32_GTIM_CCR3_OFFSET; - break; - } - - case 4: - { - offset = STM32_GTIM_CCR4_OFFSET; - break; - } - - default: - { - _err("ERROR: No such CCR: %u\n", index); - return -EINVAL; - } - } - - /* Update CCR register */ - - pulsecount_putreg(priv, offset, ccr); - - return OK; -} - -/**************************************************************************** - * Name: pulsecount_duty_update - * - * Description: - * Try to change only channel duty - * - * Input Parameters: - * dev - A reference to the lower half driver state structure - * channel - Channel to by updated - * duty - New duty - * - * Returned Value: - * Zero on success; a negated errno value on failure - * - ****************************************************************************/ - -static int pulsecount_duty_update(struct pulsecount_lowerhalf_s *dev, - uint8_t channel, ub16_t duty) -{ - struct stm32_tim_s *priv = (struct stm32_tim_s *)dev; - uint32_t reload = 0; - uint32_t ccr = 0; - - /* We don't want compilation warnings if no DEBUGASSERT */ - - UNUSED(priv); - - DEBUGASSERT(priv != NULL); - - _info("TIM%u channel: %u duty: %08" PRIx32 "\n", - priv->timid, channel, duty); - - /* Get the reload values */ - - reload = pulsecount_getreg(priv, STM32_GTIM_ARR_OFFSET); - - /* Duty cycle: - * - * duty cycle = ccr / reload (fractional value) - */ - - ccr = b16toi(duty * reload + b16HALF); - - _info("ccr: %" PRIu32 "\n", ccr); - - /* Write corresponding CCR register */ - - return pulsecount_ccr_update(dev, channel, ccr); -} - -/**************************************************************************** - * Name: pulsecount_frequency_update - * - * Description: - * Update a pulsecount timer frequency - * - ****************************************************************************/ - -static int pulsecount_frequency_update(struct pulsecount_lowerhalf_s *dev, - uint32_t frequency) -{ - struct stm32_tim_s *priv = (struct stm32_tim_s *)dev; - uint32_t reload = 0; - uint32_t timclk = 0; - uint32_t prescaler = 0; - - /* Calculate optimal values for the timer prescaler and for the timer - * reload register. If 'frequency' is the desired frequency, then - * - * reload = timclk / frequency - * timclk = pclk / presc - * - * Or, - * - * reload = pclk / presc / frequency - * - * There are many solutions to this, but the best solution will be the one - * that has the largest reload value and the smallest prescaler value. - * That is the solution that should give us the most accuracy in the timer - * control. Subject to: - * - * 0 <= presc <= 65536 - * 1 <= reload <= 65535 - * - * So presc = pclk / 65535 / frequency would be optimal. - * - * Example: - * - * pclk = 42 MHz - * frequency = 100 Hz - * - * prescaler = 42,000,000 / 65,535 / 100 - * = 6.4 (or 7 -- taking the ceiling always) - * timclk = 42,000,000 / 7 - * = 6,000,000 - * reload = 6,000,000 / 100 - * = 60,000 - */ - - prescaler = (priv->pclk / frequency + 65534) / 65535; - if (prescaler < 1) - { - prescaler = 1; - } - else if (prescaler > 65536) - { - prescaler = 65536; - } - - timclk = priv->pclk / prescaler; - - reload = timclk / frequency; - if (reload < 2) - { - reload = 1; - } - else if (reload > 65535) - { - reload = 65535; - } - else - { - reload--; - } - - _info("TIM%u PCLK: %" PRIu32" frequency: %" PRIu32 - " TIMCLK: %" PRIu32 " " - "prescaler: %" PRIu32 " reload: %" PRIu32 "\n", - priv->timid, priv->pclk, frequency, timclk, prescaler, reload); - - /* Set the reload and prescaler values */ - - pulsecount_putreg(priv, STM32_GTIM_ARR_OFFSET, reload); - pulsecount_putreg(priv, STM32_GTIM_PSC_OFFSET, (uint16_t)(prescaler - 1)); - - return OK; -} - -/**************************************************************************** - * Name: pulsecount_timer_configure - * - * Description: - * Initial configuration for pulsecount timer - * - ****************************************************************************/ - -static int pulsecount_timer_configure(struct stm32_tim_s *priv) -{ - uint16_t cr1 = 0; - - /* Set up the advanced timer CR1 register. */ - - cr1 = pulsecount_getreg(priv, STM32_GTIM_CR1_OFFSET); - - /* Pulsecount always uses edge-aligned up-counting mode. */ - - cr1 &= ~(GTIM_CR1_DIR | GTIM_CR1_CMS_MASK); - cr1 |= GTIM_CR1_EDGE; - cr1 &= ~GTIM_CR1_CKD_MASK; - cr1 |= priv->t_dts << GTIM_CR1_CKD_SHIFT; - - /* Enable ARR preload to preserve the previous pulsecount behavior. */ - - cr1 |= GTIM_CR1_ARPE; - - /* Write CR1 */ - - pulsecount_putreg(priv, STM32_GTIM_CR1_OFFSET, cr1); - - return OK; -} - -/**************************************************************************** - * Name: pulsecount_channel_configure - * - * Description: - * Configure pulsecount output compare for a channel - * - ****************************************************************************/ - -static int pulsecount_channel_configure(struct pulsecount_lowerhalf_s *dev, - uint8_t channel) -{ - struct stm32_tim_s *priv = (struct stm32_tim_s *)dev; - uint32_t chanmode = 0; - uint32_t ocmode = 0; - uint32_t ccmr = 0; - uint32_t offset = 0; - int ret = OK; - - /* Configure output compare mode */ - - chanmode = GTIM_CCMR_MODE_PWM1; - - /* Get CCMR offset */ - - switch (channel) - { - case 1: - case 2: - { - offset = STM32_GTIM_CCMR1_OFFSET; - break; - } - - case 3: - case 4: - { - offset = STM32_GTIM_CCMR2_OFFSET; - break; - } - - default: - { - _err("ERROR: No such channel: %u\n", channel); - ret = -EINVAL; - goto errout; - } - } - - /* Get current registers */ - - ccmr = pulsecount_getreg(priv, offset); - - /* output compare configuration. - * NOTE: The CCMRx registers are identical if the channels are outputs. - */ - - switch (channel) - { - /* Configure channel 1/3 */ - - case 1: - case 3: - { - ccmr &= ~(ATIM_CCMR1_CC1S_MASK | ATIM_CCMR1_OC1M_MASK | - ATIM_CCMR1_OC1PE); - ocmode |= (ATIM_CCMR_CCS_CCOUT << ATIM_CCMR1_CC1S_SHIFT); - ocmode |= (chanmode << ATIM_CCMR1_OC1M_SHIFT); - ocmode |= ATIM_CCMR1_OC1PE; -#ifdef HAVE_IP_TIMERS_V2 - ccmr &= ~(ATIM_CCMR1_OC1M); -#endif - break; - } - - /* Configure channel 2/4 */ - - case 2: - case 4: - { - ccmr &= ~(ATIM_CCMR1_CC2S_MASK | ATIM_CCMR1_OC2M_MASK | - ATIM_CCMR1_OC2PE); - ocmode |= (ATIM_CCMR_CCS_CCOUT << ATIM_CCMR1_CC2S_SHIFT); - ocmode |= (chanmode << ATIM_CCMR1_OC2M_SHIFT); - ocmode |= ATIM_CCMR1_OC2PE; -#ifdef HAVE_IP_TIMERS_V2 - ccmr &= ~(ATIM_CCMR1_OC2M); -#endif - break; - } - } - - /* Set the selected output compare configuration */ - - ccmr |= ocmode; - - /* Write CCMRx registers */ - - pulsecount_putreg(priv, offset, ccmr); - -errout: - return ret; -} - -/**************************************************************************** - * Name: pulsecount_output_configure - * - * Description: - * Configure pulsecount output for given channel - * - ****************************************************************************/ - -static int pulsecount_output_configure(struct stm32_tim_s *priv, - struct stm32_chan_s *chan) -{ - uint32_t cr2 = 0; - uint32_t ccer = 0; - uint8_t channel = 0; - - /* Get channel */ - - channel = chan->channel; - - /* Get current registers state */ - - cr2 = pulsecount_getreg(priv, STM32_GTIM_CR2_OFFSET); - ccer = pulsecount_getreg(priv, STM32_GTIM_CCER_OFFSET); - - /* | OISx | IDLE | advanced timers | CR2 register - * | CCxP | POL | all pulsecount timers | CCER register - */ - - /* Configure output polarity (all pulsecount timers) */ - - if (chan->out1.pol == PULSECOUNT_POL_NEG) - { - ccer |= (GTIM_CCER_CC1P << ((channel - 1) * 4)); - } - else - { - ccer &= ~(GTIM_CCER_CC1P << ((channel - 1) * 4)); - } - - if (priv->timtype == TIMTYPE_ADVANCED) - { - /* Configure output IDLE State */ - - if (chan->out1.idle == PULSECOUNT_IDLE_ACTIVE) - { - cr2 |= (ATIM_CR2_OIS1 << ((channel - 1) * 2)); - } - else - { - cr2 &= ~(ATIM_CR2_OIS1 << ((channel - 1) * 2)); - } - } - - /* Write registers */ - - pulsecount_modifyreg(priv, STM32_GTIM_CR2_OFFSET, 0, cr2); - pulsecount_modifyreg(priv, STM32_GTIM_CCER_OFFSET, 0, ccer); - - return OK; -} - -/**************************************************************************** - * Name: pulsecount_outputs_enable - * - * Description: - * Enable/disable given timer pulsecount outputs. - * - * NOTE: This is bulk operation - we can enable/disable many outputs - * at one time - * - * Input Parameters: - * dev - A reference to the lower half driver state structure - * outputs - outputs to set (look at enum stm32_pulsecount_chan_e) - * state - Enable/disable operation - * - ****************************************************************************/ - -static int pulsecount_outputs_enable(struct pulsecount_lowerhalf_s *dev, - uint16_t outputs, bool state) -{ - struct stm32_tim_s *priv = (struct stm32_tim_s *)dev; - uint32_t ccer = 0; - uint32_t regval = 0; - - /* Get current register state */ - - ccer = pulsecount_getreg(priv, STM32_GTIM_CCER_OFFSET); - - /* Get outputs configuration */ - - regval |= ((outputs & (1 << 0)) ? GTIM_CCER_CC1E : 0); - regval |= ((outputs & (1 << 2)) ? GTIM_CCER_CC2E : 0); - regval |= ((outputs & (1 << 4)) ? GTIM_CCER_CC3E : 0); - regval |= ((outputs & (1 << 6)) ? GTIM_CCER_CC4E : 0); - - if (state == true) - { - /* Enable outputs - set bits */ - - ccer |= regval; - } - else - { - /* Disable outputs - reset bits */ - - ccer &= ~regval; - } - - /* Write register */ - - pulsecount_putreg(priv, STM32_GTIM_CCER_OFFSET, ccer); - - return OK; -} - -/**************************************************************************** - * Name: pulsecount_moe_enable - ****************************************************************************/ - -static void pulsecount_moe_enable(struct pulsecount_lowerhalf_s *dev, - bool enable) -{ - struct stm32_tim_s *priv = (struct stm32_tim_s *)dev; - - if (enable) - { - pulsecount_modifyreg(priv, STM32_ATIM_BDTR_OFFSET, 0, ATIM_BDTR_MOE); - } - else - { - pulsecount_modifyreg(priv, STM32_ATIM_BDTR_OFFSET, ATIM_BDTR_MOE, 0); - } -} - -/**************************************************************************** - * Name: pulsecount_outputs_from_channels - * - * Description: - * Get enabled outputs configuration from the pulsecount timer state - * - ****************************************************************************/ - -static uint16_t -pulsecount_outputs_from_channels(struct stm32_tim_s *priv, uint8_t selected) -{ - uint16_t outputs = 0; - uint8_t channel; - - channel = priv->channel.channel; - - if (channel != 0 && (selected == 0 || channel == selected) && - priv->channel.out1.in_use == 1) - { - outputs = (1 << ((channel - 1) * 2)); - } - - return outputs; -} - -/**************************************************************************** - * Name: pulsecount_configure - * - * Description: - * Configure pulsecount timer in PULSECOUNT mode - * - ****************************************************************************/ - -static int pulsecount_configure(struct pulsecount_lowerhalf_s *dev) -{ - struct stm32_tim_s *priv = (struct stm32_tim_s *)dev; - uint16_t outputs = 0; - int ret = OK; - - /* NOTE: leave timer counter disabled and all outputs disabled! */ - - /* Disable the timer until we get it configured */ - - pulsecount_modifyreg(priv, STM32_GTIM_CR1_OFFSET, GTIM_CR1_CEN, 0); - - /* Get configured outputs */ - - outputs = pulsecount_outputs_from_channels(priv, 0); - - /* Disable configured outputs before the timer is reconfigured. */ - - ret = pulsecount_outputs_enable(dev, outputs, false); - if (ret < 0) - { - goto errout; - } - - /* Initial timer configuration */ - - ret = pulsecount_timer_configure(priv); - if (ret < 0) - { - goto errout; - } - - /* Disable software break (enable outputs) */ - - pulsecount_moe_enable(dev, true); - - /* Configure timer channels */ - - if (priv->channel.channel != 0) - { - pulsecount_channel_configure(dev, priv->channel.channel); - pulsecount_output_configure(priv, &priv->channel); - } - -errout: - return ret; -} - -/**************************************************************************** - * Name: pulsecount_timer - * - * Description: - * (Re-)initialize the timer resources and start the pulsed output - * - * Input Parameters: - * dev - A reference to the lower half pulsecount driver state structure - * info - A reference to the characteristics of the pulsed output - * - * Returned Value: - * Zero on success; a negated errno value on failure - * - * This split keeps pulsecount as the existing single-channel mode. - * - ****************************************************************************/ - -static int pulsecount_timer(struct pulsecount_lowerhalf_s *dev, - const struct pulsecount_info_s *info) -{ - struct stm32_tim_s *priv = (struct stm32_tim_s *)dev; - ub16_t duty = 0; - uint8_t channel = 0; - uint16_t outputs = 0; - int ret = OK; - - /* If we got here then the timer instance supports pulsecount output. */ - - DEBUGASSERT(priv != NULL && info != NULL); - - _info("TIM%u channel: %u high: %" PRIu32 " ns low: %" PRIu32 - " ns count: %" PRIu32 "\n", - priv->timid, priv->channel.channel, info->high_ns, - info->low_ns, info->count); - - DEBUGASSERT(pulsecount_frequency(info) > 0); - - /* Channel specific setup */ - - duty = pulsecount_duty(info); - channel = priv->channel.channel; - - /* Disable all interrupts and DMA requests, clear all pending status */ - - pulsecount_putreg(priv, STM32_GTIM_DIER_OFFSET, 0); - pulsecount_putreg(priv, STM32_GTIM_SR_OFFSET, 0); - - /* Set timer frequency */ - - ret = pulsecount_frequency_update(dev, pulsecount_frequency(info)); - if (ret < 0) - { - goto errout; - } - - /* Update duty cycle */ - - ret = pulsecount_duty_update(dev, channel, duty); - if (ret < 0) - { - goto errout; - } - - /* If a non-zero repetition count has been selected, then set the - * repetition counter to the count-1 (pulsecount_start() has already - * assured us that the count value is within range). - */ - - if (info->count > 0) - { - /* Save the remaining count and the number of counts that will have - * elapsed on the first interrupt. - */ - - /* If the first interrupt occurs at the end end of the first - * repetition count, then the count will be the same as the RCR - * value. - */ - - priv->prev = pulsecount_count(info->count); - pulsecount_putreg(priv, STM32_ATIM_RCR_OFFSET, priv->prev - 1); - - /* Generate an update event to reload the prescaler. This should - * preload the RCR into active repetition counter. - */ - - pulsecount_putreg(priv, STM32_GTIM_EGR_OFFSET, GTIM_EGR_UG); - - /* Now set the value of the RCR that will be loaded on the next - * update event. - */ - - priv->count = info->count; - priv->curr = pulsecount_count(info->count - priv->prev); - pulsecount_putreg(priv, STM32_ATIM_RCR_OFFSET, priv->curr - 1); - } - - /* Otherwise, just clear the repetition counter */ - - else - { - /* Set the repetition counter to zero */ - - pulsecount_putreg(priv, STM32_ATIM_RCR_OFFSET, 0); - - /* Generate an update event to reload the prescaler */ - - pulsecount_putreg(priv, STM32_GTIM_EGR_OFFSET, GTIM_EGR_UG); - } - - /* Get configured outputs */ - - outputs = pulsecount_outputs_from_channels(priv, channel); - - /* Enable output */ - - ret = pulsecount_outputs_enable(dev, outputs, true); - if (ret < 0) - { - goto errout; - } - - /* Setup update interrupt. If info->count is > 0, then we can - * be assured that pulsecount_start() has already verified: (1) that - * this is an advanced timer, and that (2) the repetition count is within - * range. - */ - - if (info->count > 0) - { - /* Clear all pending interrupts and enable the update interrupt. */ - - pulsecount_putreg(priv, STM32_GTIM_SR_OFFSET, 0); - pulsecount_putreg(priv, STM32_GTIM_DIER_OFFSET, GTIM_DIER_UIE); - - /* Enable the timer */ - - pulsecount_modifyreg(priv, STM32_GTIM_CR1_OFFSET, 0, GTIM_CR1_CEN); - - /* And enable timer interrupts at the NVIC */ - - up_enable_irq(priv->irq); - } - - pulsecount_dumpregs(dev, "After starting"); - -errout: - return ret; -} - -/**************************************************************************** - * Name: pulsecount_interrupt - * - * Description: - * Handle timer interrupts. - * - * Input Parameters: - * dev - A reference to the lower half pulsecount driver state structure - * - * Returned Value: - * Zero on success; a negated errno value on failure - * - ****************************************************************************/ - -static int pulsecount_interrupt(struct pulsecount_lowerhalf_s *dev) -{ - struct stm32_tim_s *priv = (struct stm32_tim_s *)dev; - uint16_t regval; - - /* Verify that this is an update interrupt. Nothing else is expected. */ - - regval = pulsecount_getreg(priv, STM32_ATIM_SR_OFFSET); - DEBUGASSERT((regval & ATIM_SR_UIF) != 0); - - /* Clear the UIF interrupt bit */ - - pulsecount_putreg(priv, STM32_ATIM_SR_OFFSET, (regval & ~ATIM_SR_UIF)); - - /* Calculate the new count by subtracting the number of pulses - * since the last interrupt. - */ - - if (priv->count <= priv->prev) - { - /* We are finished. Turn off the master output to stop the output as - * quickly as possible. - */ - - pulsecount_moe_enable(dev, false); - - /* Disable first interrupts, stop and reset the timer */ - - pulsecount_ll_stop(dev); - - /* Then perform the callback into the upper half driver */ - - pulsecount_expired(priv->handle); - - priv->handle = NULL; - priv->count = 0; - priv->prev = 0; - priv->curr = 0; - } - else - { - /* Decrement the count of pulses remaining using the number of - * pulses generated since the last interrupt. - */ - - priv->count -= priv->prev; - - /* Set up the next RCR. Set 'prev' to the value of the RCR that - * was loaded when the update occurred (just before this interrupt) - * and set 'curr' to the current value of the RCR register (which - * will bet loaded on the next update event). - */ - - priv->prev = priv->curr; - priv->curr = pulsecount_count(priv->count - priv->prev); - pulsecount_putreg(priv, STM32_ATIM_RCR_OFFSET, priv->curr - 1); - } - - /* Now all of the time critical stuff is done so we can do some debug - * output. - */ - - _info("Update interrupt SR: %04" PRIx16 " prev: %u curr: %u" - " count: %" PRIu32 "\n", - regval, (unsigned int)priv->prev, (unsigned int)priv->curr, - priv->count); - - return OK; -} - -/**************************************************************************** - * Name: pulsecount_tim1/8interrupt - * - * Description: - * Handle timer 1 and 8 interrupts. - * - * Input Parameters: - * Standard NuttX interrupt inputs - * - * Returned Value: - * Zero on success; a negated errno value on failure - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_TIM1_PULSECOUNT -static int pulsecount_tim1interrupt(int irq, void *context, void *arg) -{ - return pulsecount_interrupt((struct pulsecount_lowerhalf_s *) - &g_pulsecount1dev); -} -#endif /* CONFIG_STM32_TIM1_PULSECOUNT */ - -#ifdef CONFIG_STM32_TIM8_PULSECOUNT -static int pulsecount_tim8interrupt(int irq, void *context, void *arg) -{ - return pulsecount_interrupt((struct pulsecount_lowerhalf_s *) - &g_pulsecount8dev); -} -#endif /* CONFIG_STM32_TIM8_PULSECOUNT */ - -/**************************************************************************** - * Name: pulsecount_count - * - * Description: - * Pick an optimal pulse count to program the RCR. - * - * Input Parameters: - * count - The total count remaining - * - * Returned Value: - * The recommended pulse count - * - ****************************************************************************/ - -static uint8_t pulsecount_count(uint32_t count) -{ - /* Use the advanced-timer repetition counter limit. */ - - /* The the remaining pulse count is less than or equal to the maximum, the - * just return the count. - */ - - if (count <= ATIM_RCR_REP_MAX) - { - return (uint8_t)count; - } - - /* Otherwise, we have to be careful. We do not want a small number of - * counts at the end because we might have trouble responding fast enough. - * If the remaining count is less than 150% of the maximum, then return - * half of the maximum. In this case the final sequence will be between 64 - * and 128. - */ - - else if (count < (3 * ATIM_RCR_REP_MAX / 2)) - { - return (uint8_t)((ATIM_RCR_REP_MAX + 1) >> 1); - } - - /* Otherwise, return the maximum. The final count will be 64 or more */ - - else - { - return (uint8_t)ATIM_RCR_REP_MAX; - } -} - -/**************************************************************************** - * Name: pulsecount_set_apb_clock - * - * Description: - * Enable or disable APB clock for the timer peripheral - * - * Input Parameters: - * priv - A reference to the pulsecount block status - * on - Enable clock if 'on' is 'true' and disable if 'false' - * - ****************************************************************************/ - -static int pulsecount_set_apb_clock(struct stm32_tim_s *priv, bool on) -{ - uint32_t en_bit = 0; - uint32_t regaddr = 0; - int ret = OK; - - _info("timer %d clock enable: %d\n", priv->timid, on ? 1 : 0); - - /* Determine which timer to configure */ - - switch (priv->timid) - { -#ifdef CONFIG_STM32_TIM1_PULSECOUNT - case 1: - { - regaddr = TIMRCCEN_TIM1; - en_bit = TIMEN_TIM1; - break; - } -#endif - -#ifdef CONFIG_STM32_TIM8_PULSECOUNT - case 8: - { - regaddr = TIMRCCEN_TIM8; - en_bit = TIMEN_TIM8; - break; - } -#endif - - default: - { - _err("ERROR: No such timer configured %d\n", priv->timid); - ret = -EINVAL; - goto errout; - } - } - - /* Enable/disable APB 1/2 clock for timer */ - - _info("RCC_APBxENR base: %08" PRIx32 " bits: %04" PRIx32 "\n", - regaddr, en_bit); - - if (on) - { - modifyreg32(regaddr, 0, en_bit); - } - else - { - modifyreg32(regaddr, en_bit, 0); - } - -errout: - return ret; -} - -/**************************************************************************** - * Name: pulsecount_ll_setup - * - * Description: - * This method is called when the driver is opened. The lower half driver - * should configure and initialize the device so that it is ready for use. - * It should not, however, output pulses until the start method is called. - * - * Input Parameters: - * dev - A reference to the lower half pulsecount driver state structure - * - * Returned Value: - * Zero on success; a negated errno value on failure - * - * Assumptions: - * APB1 or 2 clocking for the GPIOs has already been configured by the RCC - * logic at power up. - * - ****************************************************************************/ - -static int pulsecount_ll_setup(struct pulsecount_lowerhalf_s *dev) -{ - struct stm32_tim_s *priv = (struct stm32_tim_s *)dev; - uint32_t pincfg = 0; - int ret = OK; - - _info("TIM%u\n", priv->timid); - - /* Enable APB1/2 clocking for timer. */ - - ret = pulsecount_set_apb_clock(priv, true); - if (ret < 0) - { - goto errout; - } - - pulsecount_dumpregs(dev, "Initially"); - - /* Configure the pulsecount output pins, but do not start the timer yet */ - - if (priv->channel.out1.in_use == 1) - { - /* Do not configure the pin if pincfg is not specified. - * This prevents overwriting the PA0 configuration if the - * channel is used internally. - */ - - pincfg = priv->channel.out1.pincfg; - if (pincfg != 0) - { - _info("pincfg: %08" PRIx32 "\n", pincfg); - - stm32_configgpio(pincfg); - pulsecount_dumpgpio(pincfg, "pulsecount setup"); - } - } - -errout: - return ret; -} - -/**************************************************************************** - * Name: pulsecount_ll_shutdown - * - * Description: - * This method is called when the driver is closed. The lower half driver - * stop pulsed output, free any resources, disable the timer hardware, and - * put the system into the lowest possible power usage state - * - * Input Parameters: - * dev - A reference to the lower half pulsecount driver state structure - * - * Returned Value: - * Zero on success; a negated errno value on failure - * - ****************************************************************************/ - -static int pulsecount_ll_shutdown(struct pulsecount_lowerhalf_s *dev) -{ - struct stm32_tim_s *priv = (struct stm32_tim_s *)dev; - uint32_t pincfg = 0; - int ret = OK; - - _info("TIM%u\n", priv->timid); - - /* Make sure that the output has been stopped */ - - pulsecount_ll_stop(dev); - - /* Disable APB1/2 clocking for timer. */ - - ret = pulsecount_set_apb_clock(priv, false); - if (ret < 0) - { - goto errout; - } - - /* Then put the GPIO pins back to the default state */ - - pincfg = priv->channel.out1.pincfg; - if (pincfg != 0) - { - _info("pincfg: %08" PRIx32 "\n", pincfg); - - pincfg &= (GPIO_PORT_MASK | GPIO_PIN_MASK); - pincfg |= PINCFG_DEFAULT; - - stm32_configgpio(pincfg); - } - -errout: - return ret; -} - -/**************************************************************************** - * Name: pulsecount_ll_stop - * - * Description: - * Stop the pulsed output and reset the timer resources - * - * Input Parameters: - * dev - A reference to the lower half pulsecount driver state structure - * - * Returned Value: - * Zero on success; a negated errno value on failure - * - * Assumptions: - * This function is called to stop the pulsed output at anytime. This - * method is also called from the timer interrupt handler when a repetition - * count expires... automatically stopping the timer. - * - ****************************************************************************/ - -static int pulsecount_ll_stop(struct pulsecount_lowerhalf_s *dev) -{ - struct stm32_tim_s *priv = (struct stm32_tim_s *)dev; - irqstate_t flags = 0; - uint16_t outputs = 0; - int ret = OK; - - _info("TIM%u\n", priv->timid); - - /* Disable interrupts momentary to stop any ongoing timer processing and - * to prevent any concurrent access to the reset register. - */ - - flags = enter_critical_section(); - - /* Stopped so frequency is zero */ - - priv->frequency = 0; - - /* Disable further interrupts and stop the timer */ - - pulsecount_putreg(priv, STM32_GTIM_DIER_OFFSET, 0); - pulsecount_putreg(priv, STM32_GTIM_SR_OFFSET, 0); - - /* Disable the timer and timer outputs */ - - pulsecount_modifyreg(priv, STM32_GTIM_CR1_OFFSET, GTIM_CR1_CEN, 0); - outputs = pulsecount_outputs_from_channels(priv, 0); - ret = pulsecount_outputs_enable(dev, outputs, false); - - /* Clear all channels */ - - pulsecount_putreg(priv, STM32_GTIM_CCR1_OFFSET, 0); - pulsecount_putreg(priv, STM32_GTIM_CCR2_OFFSET, 0); - pulsecount_putreg(priv, STM32_GTIM_CCR3_OFFSET, 0); - pulsecount_putreg(priv, STM32_GTIM_CCR4_OFFSET, 0); - - leave_critical_section(flags); - - pulsecount_dumpregs(dev, "After stop"); - - return ret; -} - -/**************************************************************************** - * Name: pulsecount_ll_ioctl - * - * Description: - * Lower-half logic may support platform-specific ioctl commands - * - * Input Parameters: - * dev - A reference to the lower half pulsecount driver state structure - * cmd - The ioctl command - * arg - The argument accompanying the ioctl command - * - * Returned Value: - * Zero on success; a negated errno value on failure - * - ****************************************************************************/ - -static int pulsecount_ll_ioctl(struct pulsecount_lowerhalf_s *dev, int cmd, - unsigned long arg) -{ -#ifdef CONFIG_DEBUG_TIMER_INFO - struct stm32_tim_s *priv = (struct stm32_tim_s *)dev; - - /* There are no platform-specific ioctl commands */ - - _info("TIM%u\n", priv->timid); -#endif - return -ENOTTY; -} - -static int pulsecount_setup(struct pulsecount_lowerhalf_s *dev) -{ - struct stm32_pulsecount_s *pulse = (struct stm32_pulsecount_s *)dev; - int ret; - - ret = pulsecount_ll_setup((struct pulsecount_lowerhalf_s *)pulse->timer); - if (ret < 0) - { - return ret; - } - - return pulsecount_configure((struct pulsecount_lowerhalf_s *)pulse->timer); -} - -static int pulsecount_shutdown(struct pulsecount_lowerhalf_s *dev) -{ - struct stm32_pulsecount_s *pulse = (struct stm32_pulsecount_s *)dev; - return pulsecount_ll_shutdown((struct pulsecount_lowerhalf_s *) - pulse->timer); -} - -static int pulsecount_start(struct pulsecount_lowerhalf_s *dev, - const struct pulsecount_info_s *info, - void *handle) -{ - struct stm32_pulsecount_s *pulse = (struct stm32_pulsecount_s *)dev; - struct stm32_tim_s *priv = pulse->timer; - - /* Check if a pulsecount has been selected */ - - if (info->count > 0) - { - /* Only the advanced timers (TIM1,8 can support the pulse counting) - */ - - if (priv->timtype != TIMTYPE_ADVANCED) - { - _err("ERROR: TIM%u cannot support pulse count: %" PRIu32 "\n", - priv->timid, info->count); - return -EPERM; - } - } - - /* Save the handle */ - - priv->handle = handle; - - /* Start the time */ - - return pulsecount_timer((struct pulsecount_lowerhalf_s *)priv, info); -} - -static int pulsecount_stop(struct pulsecount_lowerhalf_s *dev) -{ - struct stm32_pulsecount_s *pulse = (struct stm32_pulsecount_s *)dev; - return pulsecount_ll_stop((struct pulsecount_lowerhalf_s *)pulse->timer); -} - -static int pulsecount_ioctl(struct pulsecount_lowerhalf_s *dev, - int cmd, unsigned long arg) -{ - struct stm32_pulsecount_s *pulse = (struct stm32_pulsecount_s *)dev; - return pulsecount_ll_ioctl((struct pulsecount_lowerhalf_s *)pulse->timer, - cmd, arg); -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -struct pulsecount_lowerhalf_s *stm32_pulsecountinitialize(int timer) -{ - struct stm32_pulsecount_s *lower = NULL; - - _info("TIM%u\n", timer); - - switch (timer) - { -#ifdef CONFIG_STM32_TIM1_PULSECOUNT - case 1: - { - lower = &g_pulsecount1lower; - irq_attach(lower->timer->irq, pulsecount_tim1interrupt, NULL); - up_disable_irq(lower->timer->irq); - break; - } -#endif - -#ifdef CONFIG_STM32_TIM8_PULSECOUNT - case 8: - { - lower = &g_pulsecount8lower; - irq_attach(lower->timer->irq, pulsecount_tim8interrupt, NULL); - up_disable_irq(lower->timer->irq); - break; - } -#endif - - default: - { - _err("ERROR: TIM%d does not support pulse count\n", timer); - return NULL; - } - } - - return (struct pulsecount_lowerhalf_s *)lower; -} diff --git a/arch/arm/src/stm32/stm32_pulsecount.h b/arch/arm/src/stm32/stm32_pulsecount.h deleted file mode 100644 index 20ccf3608fed1..0000000000000 --- a/arch/arm/src/stm32/stm32_pulsecount.h +++ /dev/null @@ -1,39 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_pulsecount.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32_STM32_PULSECOUNT_H -#define __ARCH_ARM_SRC_STM32_STM32_PULSECOUNT_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -struct pulsecount_lowerhalf_s *stm32_pulsecountinitialize(int timer); - -#endif /* __ARCH_ARM_SRC_STM32_STM32_PULSECOUNT_H */ diff --git a/arch/arm/src/stm32/stm32_pwm.c b/arch/arm/src/stm32/stm32_pwm.c deleted file mode 100644 index 4b7d1378d8240..0000000000000 --- a/arch/arm/src/stm32/stm32_pwm.c +++ /dev/null @@ -1,4107 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_pwm.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include -#include - -#include -#include - -#include "arm_internal.h" -#include "chip.h" -#include "stm32_pwm.h" -#include "stm32_rcc.h" -#include "stm32_gpio.h" - -/* This module then only compiles if there is at least one enabled timer - * intended for use with the PWM upper half driver. - * - * It implements support for both: - * 1. STM32 TIMER IP version 1 - F0, F1, F2, F37x, F4, L0, L1 - * 2. STM32 TIMER IP version 2 - F3 (no F37x), F7, H7, L4, L4+ - */ - -#ifdef CONFIG_STM32_PWM - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* PWM/Timer Definitions ****************************************************/ - -/* The following definitions are used to identify the various time types. - * There are some differences in timer types across STM32 families: - * - TIM2 is 16-bit timer for F1, L1 and L0 - * - TIM5 is 16-bit timer for F1 - */ - -#define TIMTYPE_BASIC 0 /* Basic timers (no outputs) */ -#define TIMTYPE_GENERAL16 1 /* General 16-bit timers (up, down, up/down)*/ -#define TIMTYPE_COUNTUP16 2 /* General 16-bit count-up timers */ -#define TIMTYPE_COUNTUP16_N 3 /* General 16-bit count-up timers with - * complementary outputs - */ -#define TIMTYPE_GENERAL32 4 /* General 32-bit timers (up, down, up/down)*/ -#define TIMTYPE_ADVANCED 5 /* Advanced timers */ - -#define TIMTYPE_TIM1 TIMTYPE_ADVANCED -#if defined(CONFIG_STM32_STM32L15XX) || defined(CONFIG_STM32_STM32F10XX) -# define TIMTYPE_TIM2 TIMTYPE_GENERAL16 -#else -# define TIMTYPE_TIM2 TIMTYPE_GENERAL32 -#endif -#define TIMTYPE_TIM3 TIMTYPE_GENERAL16 -#define TIMTYPE_TIM4 TIMTYPE_GENERAL16 -#if defined(CONFIG_STM32_STM32F10XX) -# define TIMTYPE_TIM5 TIMTYPE_GENERAL16 -#else -# define TIMTYPE_TIM5 TIMTYPE_GENERAL32 -#endif -#define TIMTYPE_TIM6 TIMTYPE_BASIC -#define TIMTYPE_TIM7 TIMTYPE_BASIC -#define TIMTYPE_TIM8 TIMTYPE_ADVANCED -#define TIMTYPE_TIM9 TIMTYPE_COUNTUP16 -#define TIMTYPE_TIM10 TIMTYPE_COUNTUP16 -#define TIMTYPE_TIM11 TIMTYPE_COUNTUP16 -#define TIMTYPE_TIM12 TIMTYPE_COUNTUP16 -#define TIMTYPE_TIM13 TIMTYPE_COUNTUP16 -#define TIMTYPE_TIM14 TIMTYPE_COUNTUP16 -#define TIMTYPE_TIM15 TIMTYPE_COUNTUP16_N /* Treated as ADVTIM */ -#define TIMTYPE_TIM16 TIMTYPE_COUNTUP16_N /* Treated as ADVTIM */ -#define TIMTYPE_TIM17 TIMTYPE_COUNTUP16_N /* Treated as ADVTIM */ - -/* Timer clock source, RCC EN offset, enable bit, - * RCC RST offset, reset bit to use - * - * TODO: simplify this and move somewhere else. - */ - -#if defined(CONFIG_STM32_STM32F37XX) -# define TIMCLK_TIM2 STM32_APB1_TIM2_CLKIN -# define TIMRCCEN_TIM2 STM32_RCC_APB1ENR -# define TIMEN_TIM2 RCC_APB1ENR_TIM2EN -# define TIMRCCRST_TIM2 STM32_RCC_APB1RSTR -# define TIMRST_TIM2 RCC_APB1RSTR_TIM2RST -# define TIMCLK_TIM3 STM32_APB1_TIM3_CLKIN -# define TIMRCCEN_TIM3 STM32_RCC_APB1ENR -# define TIMEN_TIM3 RCC_APB1ENR_TIM3EN -# define TIMRCCRST_TIM3 STM32_RCC_APB1RSTR -# define TIMRST_TIM3 RCC_APB1RSTR_TIM3RST -# define TIMCLK_TIM4 STM32_APB1_TIM4_CLKIN -# define TIMRCCEN_TIM4 STM32_RCC_APB1ENR -# define TIMEN_TIM4 RCC_APB1ENR_TIM4EN -# define TIMRCCRST_TIM4 STM32_RCC_APB1RSTR -# define TIMRST_TIM4 RCC_APB1RSTR_TIM4RST -# define TIMCLK_TIM5 STM32_APB1_TIM5_CLKIN -# define TIMRCCEN_TIM5 STM32_RCC_APB1ENR -# define TIMEN_TIM5 RCC_APB1ENR_TIM5EN -# define TIMRCCRST_TIM5 STM32_RCC_APB1RSTR -# define TIMRST_TIM5 RCC_APB1RSTR_TIM5RST -# define TIMCLK_TIM6 STM32_APB1_TIM6_CLKIN -# define TIMRCCEN_TIM6 STM32_RCC_APB1ENR -# define TIMEN_TIM6 RCC_APB1ENR_TIM6EN -# define TIMRCCRST_TIM6 STM32_RCC_APB1RSTR -# define TIMRST_TIM6 RCC_APB1RSTR_TIM6RST -# define TIMCLK_TIM7 STM32_APB1_TIM7_CLKIN -# define TIMRCCEN_TIM7 STM32_RCC_APB1ENR -# define TIMEN_TIM7 RCC_APB1ENR_TIM7EN -# define TIMRCCRST_TIM7 STM32_RCC_APB1RSTR -# define TIMRST_TIM7 RCC_APB1RSTR_TIM7RST -# define TIMCLK_TIM12 STM32_APB1_TIM12_CLKIN -# define TIMRCCEN_TIM12 STM32_RCC_APB1ENR -# define TIMEN_TIM12 RCC_APB1ENR_TIM12EN -# define TIMRCCRST_TIM12 STM32_RCC_APB1RSTR -# define TIMRST_TIM12 RCC_APB1RSTR_TIM12RST -# define TIMCLK_TIM13 STM32_APB1_TIM13_CLKIN -# define TIMRCCEN_TIM13 STM32_RCC_APB1ENR -# define TIMEN_TIM13 RCC_APB1ENR_TIM13EN -# define TIMRCCRST_TIM13 STM32_RCC_APB1RSTR -# define TIMRST_TIM13 RCC_APB1RSTR_TIM13RST -# define TIMCLK_TIM14 STM32_APB1_TIM14_CLKIN -# define TIMRCCEN_TIM14 STM32_RCC_APB1ENR -# define TIMEN_TIM14 RCC_APB1ENR_TIM14EN -# define TIMRCCRST_TIM14 STM32_RCC_APB1RSTR -# define TIMRST_TIM14 RCC_APB1RSTR_TIM14RST -# define TIMCLK_TIM15 STM32_APB2_TIM15_CLKIN -# define TIMRCCEN_TIM15 STM32_RCC_APB2ENR -# define TIMEN_TIM15 RCC_APB2ENR_TIM15EN -# define TIMRCCRST_TIM15 STM32_RCC_APB2RSTR -# define TIMRST_TIM15 RCC_APB2RSTR_TIM15RST -# define TIMCLK_TIM16 STM32_APB2_TIM16_CLKIN -# define TIMRCCEN_TIM16 STM32_RCC_APB2ENR -# define TIMEN_TIM16 RCC_APB2ENR_TIM16EN -# define TIMRCCRST_TIM16 STM32_RCC_APB2RSTR -# define TIMRST_TIM16 RCC_APB2RSTR_TIM16RST -# define TIMCLK_TIM17 STM32_APB2_TIM17_CLKIN -# define TIMRCCEN_TIM17 STM32_RCC_APB2ENR -# define TIMEN_TIM17 RCC_APB2ENR_TIM17EN -# define TIMRCCRST_TIM17 STM32_RCC_APB2RSTR -# define TIMRST_TIM17 RCC_APB2RSTR_TIM17RST -# define TIMCLK_TIM18 STM32_APB1_TIM18_CLKIN -# define TIMRCCEN_TIM18 STM32_RCC_APB1ENR -# define TIMEN_TIM18 RCC_APB1ENR_TIM18EN -# define TIMRCCRST_TIM18 STM32_RCC_APB1RSTR -# define TIMRST_TIM18 RCC_APB1RSTR_TIM18RST -# define TIMCLK_TIM19 STM32_APB2_TIM19_CLKIN -# define TIMRCCEN_TIM19 STM32_RCC_APB2ENR -# define TIMEN_TIM19 RCC_APB2ENR_TIM19EN -# define TIMRCCRST_TIM19 STM32_RCC_APB2RSTR -# define TIMRST_TIM19 RCC_APB2RSTR_TIM19RST -#else -# define TIMCLK_TIM1 STM32_APB2_TIM1_CLKIN -# define TIMRCCEN_TIM1 STM32_RCC_APB2ENR -# define TIMEN_TIM1 RCC_APB2ENR_TIM1EN -# define TIMRCCRST_TIM1 STM32_RCC_APB2RSTR -# define TIMRST_TIM1 RCC_APB2RSTR_TIM1RST -# define TIMCLK_TIM2 STM32_APB1_TIM2_CLKIN -# define TIMRCCEN_TIM2 STM32_RCC_APB1ENR -# define TIMEN_TIM2 RCC_APB1ENR_TIM2EN -# define TIMRCCRST_TIM2 STM32_RCC_APB1RSTR -# define TIMRST_TIM2 RCC_APB1RSTR_TIM2RST -# define TIMCLK_TIM3 STM32_APB1_TIM3_CLKIN -# define TIMRCCEN_TIM3 STM32_RCC_APB1ENR -# define TIMEN_TIM3 RCC_APB1ENR_TIM3EN -# define TIMRCCRST_TIM3 STM32_RCC_APB1RSTR -# define TIMRST_TIM3 RCC_APB1RSTR_TIM3RST -# define TIMCLK_TIM4 STM32_APB1_TIM4_CLKIN -# define TIMRCCEN_TIM4 STM32_RCC_APB1ENR -# define TIMEN_TIM4 RCC_APB1ENR_TIM4EN -# define TIMRCCRST_TIM4 STM32_RCC_APB1RSTR -# define TIMRST_TIM4 RCC_APB1RSTR_TIM4RST -# define TIMCLK_TIM5 STM32_APB1_TIM5_CLKIN -# define TIMRCCEN_TIM5 STM32_RCC_APB1ENR -# define TIMEN_TIM5 RCC_APB1ENR_TIM5EN -# define TIMRCCRST_TIM5 STM32_RCC_APB1RSTR -# define TIMRST_TIM5 RCC_APB1RSTR_TIM5RST -# define TIMCLK_TIM8 STM32_APB2_TIM8_CLKIN -# define TIMRCCEN_TIM8 STM32_RCC_APB2ENR -# define TIMEN_TIM8 RCC_APB2ENR_TIM8EN -# define TIMRCCRST_TIM8 STM32_RCC_APB2RSTR -# define TIMRST_TIM8 RCC_APB2RSTR_TIM8RST -# define TIMCLK_TIM9 STM32_APB2_TIM9_CLKIN -# define TIMRCCEN_TIM9 STM32_RCC_APB2ENR -# define TIMEN_TIM9 RCC_APB2ENR_TIM9EN -# define TIMRCCRST_TIM9 STM32_RCC_APB2RSTR -# define TIMRST_TIM9 RCC_APB2RSTR_TIM9RST -# define TIMCLK_TIM10 STM32_APB2_TIM10_CLKIN -# define TIMRCCEN_TIM10 STM32_RCC_APB2ENR -# define TIMEN_TIM10 RCC_APB2ENR_TIM10EN -# define TIMRCCRST_TIM10 STM32_RCC_APB2RSTR -# define TIMRST_TIM10 RCC_APB2RSTR_TIM10RST -# define TIMCLK_TIM11 STM32_APB2_TIM11_CLKIN -# define TIMRCCEN_TIM11 STM32_RCC_APB2ENR -# define TIMEN_TIM11 RCC_APB2ENR_TIM11EN -# define TIMRCCRST_TIM11 STM32_RCC_APB2RSTR -# define TIMRST_TIM11 RCC_APB2RSTR_TIM11RST -# define TIMCLK_TIM12 STM32_APB1_TIM12_CLKIN -# define TIMRCCEN_TIM12 STM32_RCC_APB1ENR -# define TIMEN_TIM12 RCC_APB1ENR_TIM12EN -# define TIMRCCRST_TIM12 STM32_RCC_APB1RSTR -# define TIMRST_TIM12 RCC_APB1RSTR_TIM12RST -# define TIMCLK_TIM13 STM32_APB1_TIM13_CLKIN -# define TIMRCCEN_TIM13 STM32_RCC_APB1ENR -# define TIMEN_TIM13 RCC_APB1ENR_TIM13EN -# define TIMRCCRST_TIM13 STM32_RCC_APB1RSTR -# define TIMRST_TIM13 RCC_APB1RSTR_TIM13RST -# define TIMCLK_TIM14 STM32_APB1_TIM14_CLKIN -# define TIMRCCEN_TIM14 STM32_RCC_APB1ENR -# define TIMEN_TIM14 RCC_APB1ENR_TIM14EN -# define TIMRCCRST_TIM14 STM32_RCC_APB1RSTR -# define TIMRST_TIM14 RCC_APB1RSTR_TIM14RST -# define TIMCLK_TIM15 STM32_APB1_TIM15_CLKIN -# define TIMRCCEN_TIM15 STM32_RCC_APB1ENR -# define TIMEN_TIM15 RCC_APB1ENR_TIM15EN -# define TIMRCCRST_TIM15 STM32_RCC_APB1RSTR -# define TIMRST_TIM15 RCC_APB1RSTR_TIM15RST -# define TIMCLK_TIM16 STM32_APB1_TIM16_CLKIN -# define TIMRCCEN_TIM16 STM32_RCC_APB1ENR -# define TIMEN_TIM16 RCC_APB1ENR_TIM16EN -# define TIMRCCRST_TIM16 STM32_RCC_APB1RSTR -# define TIMRST_TIM16 RCC_APB1RSTR_TIM16RST -# define TIMCLK_TIM17 STM32_APB1_TIM17_CLKIN -# define TIMRCCEN_TIM17 STM32_RCC_APB1ENR -# define TIMEN_TIM17 RCC_APB1ENR_TIM17EN -# define TIMRCCRST_TIM17 STM32_RCC_APB1RSTR -# define TIMRST_TIM17 RCC_APB1RSTR_TIM17RST -#endif - -/* Default GPIO pins state */ - -#if defined(CONFIG_STM32_STM32F10XX) -# define PINCFG_DEFAULT (GPIO_INPUT | GPIO_CNF_INFLOAT | GPIO_MODE_INPUT) -#elif defined(CONFIG_STM32_STM32F20XX) || \ - defined(CONFIG_STM32_STM32F30XX) || \ - defined(CONFIG_STM32_STM32F33XX) || \ - defined(CONFIG_STM32_STM32F37XX) || \ - defined(CONFIG_STM32_STM32F4XXX) || \ - defined(CONFIG_STM32_STM32L15XX) || \ - defined(CONFIG_STM32_STM32G4XXX) -# define PINCFG_DEFAULT (GPIO_INPUT | GPIO_FLOAT) -#else -# error "Unrecognized STM32 chip" -#endif - -/* Advanced Timer support - * NOTE: TIM15-17 are not ADVTIM but they support most of the - * ADVTIM functionality. The main difference is the number of - * supported capture/compare. - */ - -#if defined(CONFIG_STM32_TIM1_PWM) || defined(CONFIG_STM32_TIM8_PWM) || \ - defined(CONFIG_STM32_TIM15_PWM) || defined(CONFIG_STM32_TIM16_PWM) || \ - defined(CONFIG_STM32_TIM17_PWM) -# define HAVE_ADVTIM -#else -# undef HAVE_ADVTIM -#endif - -/* TRGO/TRGO2 support */ - -#ifdef CONFIG_STM32_PWM_TRGO -# define HAVE_TRGO -#endif - -/* Break support */ - -#if defined(CONFIG_STM32_TIM1_BREAK1) || defined(CONFIG_STM32_TIM1_BREAK2) || \ - defined(CONFIG_STM32_TIM8_BREAK1) || defined(CONFIG_STM32_TIM8_BREAK2) || \ - defined(CONFIG_STM32_TIM15_BREAK1) || defined(CONFIG_STM32_TIM16_BREAK1) || \ - defined(CONFIG_STM32_TIM17_BREAK1) -# defined HAVE_BREAK -#endif - -/* Debug ********************************************************************/ - -#ifdef CONFIG_DEBUG_PWM_INFO -# define pwm_dumpgpio(p,m) stm32_dumpgpio(p,m) -#else -# define pwm_dumpgpio(p,m) -#endif - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/* PWM output configuration */ - -struct stm32_pwm_out_s -{ - uint8_t in_use:1; /* Output in use */ - uint8_t pol:1; /* Polarity. Default: positive */ - uint8_t idle:1; /* Idle state. Default: inactive */ - uint8_t _res:5; /* Reserved */ - uint32_t pincfg; /* Output pin configuration */ -}; - -/* PWM break configuration */ - -#ifdef HAVE_BREAK -struct stm32_pwm_break_s -{ - uint8_t en1:1; /* Break 1 enable */ - uint8_t pol1:1; /* Break 1 polarity */ - uint8_t _res:6; /* Reserved */ -#ifdef HAVE_IP_TIMERS_V2 - uint8_t en2:1; /* Break 2 enable */ - uint8_t pol2:1; /* Break 2 polarity */ - uint8_t flt2:6; /* Break 2 filter */ -#endif -}; -#endif - -/* PWM channel configuration */ - -struct stm32_pwmchan_s -{ - uint8_t channel:4; /* Timer output channel: {1,..4} */ - uint8_t mode:4; /* PWM channel mode (see stm32_pwm_chanmode_e) */ - struct stm32_pwm_out_s out1; /* PWM output configuration */ -#ifdef HAVE_BREAK - struct stm32_pwm_break_s brk; /* PWM break configuration */ -#endif -#ifdef HAVE_PWM_COMPLEMENTARY - struct stm32_pwm_out_s out2; /* PWM complementary output configuration */ -#endif -}; - -/* This structure represents the state of one PWM timer */ - -struct stm32_pwmtimer_s -{ - const struct pwm_ops_s *ops; /* PWM operations */ -#ifdef CONFIG_STM32_PWM_LL_OPS - const struct stm32_pwm_ops_s *llops; /* Low-level PWM ops */ -#endif - struct stm32_pwmchan_s *channels; /* Channels configuration */ - uint8_t timid:5; /* Timer ID {1,...,17} */ - uint8_t chan_num:3; /* Number of configured channels */ - uint8_t timtype:3; /* See the TIMTYPE_* definitions */ - uint8_t mode:3; /* Timer mode (see stm32_pwm_tim_mode_e) */ - uint8_t lock:2; /* Lock configuration */ - uint8_t t_dts:3; /* Clock division for t_DTS */ - uint8_t _res:5; /* Reserved */ -#ifdef HAVE_PWM_COMPLEMENTARY - uint8_t deadtime; /* Dead-time value */ -#endif -#ifdef HAVE_TRGO - uint8_t trgo; /* TRGO configuration: - * 4 LSB = TRGO, 4 MSB = TRGO2 - */ -#endif - uint32_t frequency; /* Current frequency setting */ - uint32_t base; /* The base address of the timer */ - uint32_t pclk; /* The frequency of the peripheral - * clock that drives the timer module - */ -}; - -/**************************************************************************** - * Static Function Prototypes - ****************************************************************************/ - -/* Register access */ - -static uint32_t pwm_getreg(struct stm32_pwmtimer_s *priv, int offset); -static void pwm_putreg(struct stm32_pwmtimer_s *priv, int offset, - uint32_t value); -static void pwm_modifyreg(struct stm32_pwmtimer_s *priv, uint32_t offset, - uint32_t clearbits, uint32_t setbits); - -#ifdef CONFIG_DEBUG_PWM_INFO -static void pwm_dumpregs(struct pwm_lowerhalf_s *dev, - const char *msg); -#else -# define pwm_dumpregs(priv,msg) -#endif - -/* Timer management */ - -static int pwm_frequency_update(struct pwm_lowerhalf_s *dev, - uint32_t frequency); -static int pwm_mode_configure(struct pwm_lowerhalf_s *dev, - uint8_t channel, uint32_t mode); -static int pwm_timer_configure(struct stm32_pwmtimer_s *priv); -static int pwm_output_configure(struct stm32_pwmtimer_s *priv, - struct stm32_pwmchan_s *chan); -static int pwm_outputs_enable(struct pwm_lowerhalf_s *dev, - uint16_t outputs, bool state); -static int pwm_soft_update(struct pwm_lowerhalf_s *dev); -static int pwm_soft_break(struct pwm_lowerhalf_s *dev, bool state); -static int pwm_ccr_update(struct pwm_lowerhalf_s *dev, uint8_t index, - uint32_t ccr); -static int pwm_arr_update(struct pwm_lowerhalf_s *dev, uint32_t arr); -static uint32_t pwm_arr_get(struct pwm_lowerhalf_s *dev); -static int pwm_duty_update(struct pwm_lowerhalf_s *dev, uint8_t channel, - ub16_t duty); -static int pwm_timer_enable(struct pwm_lowerhalf_s *dev, bool state); - -#ifdef HAVE_ADVTIM -static int pwm_break_dt_configure(struct stm32_pwmtimer_s *priv); -#endif -#ifdef HAVE_TRGO -static int pwm_trgo_configure(struct pwm_lowerhalf_s *dev, - uint8_t trgo); -#endif -#if defined(HAVE_PWM_COMPLEMENTARY) && defined(CONFIG_STM32_PWM_LL_OPS) -static int pwm_deadtime_update(struct pwm_lowerhalf_s *dev, uint8_t dt); -#endif -#ifdef CONFIG_STM32_PWM_LL_OPS -static uint32_t pwm_ccr_get(struct pwm_lowerhalf_s *dev, uint8_t index); -static uint16_t pwm_rcr_get(struct pwm_lowerhalf_s *dev); -#endif -#ifdef HAVE_ADVTIM -static int pwm_rcr_update(struct pwm_lowerhalf_s *dev, uint16_t rcr); -#endif - -static int pwm_configure(struct pwm_lowerhalf_s *dev); -static int pwm_timer(struct pwm_lowerhalf_s *dev, - const struct pwm_info_s *info); - -/* PWM driver methods */ - -static int pwm_setup(struct pwm_lowerhalf_s *dev); -static int pwm_shutdown(struct pwm_lowerhalf_s *dev); - -static int pwm_start(struct pwm_lowerhalf_s *dev, - const struct pwm_info_s *info); - -static int pwm_stop(struct pwm_lowerhalf_s *dev); -static int pwm_ioctl(struct pwm_lowerhalf_s *dev, - int cmd, unsigned long arg); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* This is the list of lower half PWM driver methods used by the upper half - * driver. - */ - -static const struct pwm_ops_s g_pwmops = -{ - .setup = pwm_setup, - .shutdown = pwm_shutdown, - .start = pwm_start, - .stop = pwm_stop, - .ioctl = pwm_ioctl, -}; - -#ifdef CONFIG_STM32_PWM_LL_OPS -static const struct stm32_pwm_ops_s g_llpwmops = -{ - .configure = pwm_configure, - .soft_break = pwm_soft_break, - .ccr_update = pwm_ccr_update, - .mode_update = pwm_mode_configure, - .ccr_get = pwm_ccr_get, - .arr_update = pwm_arr_update, - .arr_get = pwm_arr_get, -#ifdef HAVE_ADVTIM - .rcr_update = pwm_rcr_update, -#endif - .rcr_get = pwm_rcr_get, -#ifdef HAVE_TRGO - .trgo_set = pwm_trgo_configure, -#endif - .outputs_enable = pwm_outputs_enable, - .soft_update = pwm_soft_update, - .freq_update = pwm_frequency_update, - .tim_enable = pwm_timer_enable, -# ifdef CONFIG_DEBUG_PWM_INFO - .dump_regs = pwm_dumpregs, -# endif -# ifdef HAVE_PWM_COMPLEMENTARY - .dt_update = pwm_deadtime_update, -# endif -}; -#endif - -#ifdef CONFIG_STM32_TIM1_PWM - -static struct stm32_pwmchan_s g_pwm1channels[] = -{ - /* TIM1 has 4 channels, 4 complementary */ - -#ifdef CONFIG_STM32_TIM1_CHANNEL1 - { - .channel = 1, - .mode = CONFIG_STM32_TIM1_CH1MODE, -#ifdef HAVE_BREAK - .brk = - { -#ifdef CONFIG_STM32_TIM1_BREAK1 - .en1 = 1, - .pol1 = CONFIG_STM32_TIM1_BRK1POL, -#endif -#ifdef CONFIG_STM32_TIM1_BREAK2 - .en2 = 1, - .pol2 = CONFIG_STM32_TIM1_BRK2POL, - .flt2 = CONFIG_STM32_TIM1_BRK2FLT, -#endif - }, -#endif -#ifdef CONFIG_STM32_TIM1_CH1OUT - .out1 = - { - .in_use = 1, - .pol = CONFIG_STM32_TIM1_CH1POL, - .idle = CONFIG_STM32_TIM1_CH1IDLE, - .pincfg = PWM_TIM1_CH1CFG, - }, -#endif -#ifdef CONFIG_STM32_TIM1_CH1NOUT - .out2 = - { - .in_use = 1, - .pol = CONFIG_STM32_TIM1_CH1NPOL, - .idle = CONFIG_STM32_TIM1_CH1NIDLE, - .pincfg = PWM_TIM1_CH1NCFG, - } -#endif - }, -#endif -#ifdef CONFIG_STM32_TIM1_CHANNEL2 - { - .channel = 2, - .mode = CONFIG_STM32_TIM1_CH2MODE, -#ifdef CONFIG_STM32_TIM1_CH2OUT - .out1 = - { - .in_use = 1, - .pol = CONFIG_STM32_TIM1_CH2POL, - .idle = CONFIG_STM32_TIM1_CH2IDLE, - .pincfg = PWM_TIM1_CH2CFG, - }, -#endif -#ifdef CONFIG_STM32_TIM1_CH2NOUT - .out2 = - { - .in_use = 1, - .pol = CONFIG_STM32_TIM1_CH2NPOL, - .idle = CONFIG_STM32_TIM1_CH2NIDLE, - .pincfg = PWM_TIM1_CH2NCFG, - } -#endif - }, -#endif -#ifdef CONFIG_STM32_TIM1_CHANNEL3 - { - .channel = 3, - .mode = CONFIG_STM32_TIM1_CH3MODE, -#ifdef CONFIG_STM32_TIM1_CH3OUT - .out1 = - { - .in_use = 1, - .pol = CONFIG_STM32_TIM1_CH3POL, - .idle = CONFIG_STM32_TIM1_CH3IDLE, - .pincfg = PWM_TIM1_CH3CFG, - }, -#endif -#ifdef CONFIG_STM32_TIM1_CH3NOUT - .out2 = - { - .in_use = 1, - .pol = CONFIG_STM32_TIM1_CH3NPOL, - .idle = CONFIG_STM32_TIM1_CH3NIDLE, - .pincfg = PWM_TIM1_CH3NCFG, - } -#endif - }, -#endif -#ifdef CONFIG_STM32_TIM1_CHANNEL4 - { - .channel = 4, - .mode = CONFIG_STM32_TIM1_CH4MODE, -#ifdef CONFIG_STM32_TIM1_CH4OUT - .out1 = - { - .in_use = 1, - .pol = CONFIG_STM32_TIM1_CH4POL, - .idle = CONFIG_STM32_TIM1_CH4IDLE, - .pincfg = PWM_TIM1_CH4CFG, - } -#endif - }, -#endif -#ifdef CONFIG_STM32_TIM1_CHANNEL5 - { - .channel = 5, - .mode = CONFIG_STM32_TIM1_CH5MODE, -#ifdef CONFIG_STM32_TIM1_CH5OUT - .out1 = - { - .in_use = 1, - .pol = CONFIG_STM32_TIM1_CH5POL, - .idle = CONFIG_STM32_TIM1_CH5IDLE, - .pincfg = 0, /* Not available externally */ - } -#endif - }, -#endif -#ifdef CONFIG_STM32_TIM1_CHANNEL6 - { - .channel = 6, - .mode = CONFIG_STM32_TIM1_CH6MODE, -#ifdef CONFIG_STM32_TIM1_CH6OUT - .out1 = - { - .in_use = 1, - .pol = CONFIG_STM32_TIM1_CH6POL, - .idle = CONFIG_STM32_TIM1_CH6IDLE, - .pincfg = 0, /* Not available externally */ - } -#endif - } -#endif -}; - -static struct stm32_pwmtimer_s g_pwm1dev = -{ - .ops = &g_pwmops, -#ifdef CONFIG_STM32_PWM_LL_OPS - .llops = &g_llpwmops, -#endif - .timid = 1, - .chan_num = PWM_TIM1_NCHANNELS, - .channels = g_pwm1channels, - .timtype = TIMTYPE_TIM1, - .mode = CONFIG_STM32_TIM1_MODE, - .lock = CONFIG_STM32_TIM1_LOCK, - .t_dts = CONFIG_STM32_TIM1_TDTS, -#ifdef HAVE_PWM_COMPLEMENTARY - .deadtime = CONFIG_STM32_TIM1_DEADTIME, -#endif -#if defined(HAVE_TRGO) && defined(STM32_TIM1_TRGO) - .trgo = STM32_TIM1_TRGO, -#endif - .base = STM32_TIM1_BASE, - .pclk = TIMCLK_TIM1, -}; -#endif /* CONFIG_STM32_TIM1_PWM */ - -#ifdef CONFIG_STM32_TIM2_PWM - -static struct stm32_pwmchan_s g_pwm2channels[] = -{ - /* TIM2 has 4 channels */ - -#ifdef CONFIG_STM32_TIM2_CHANNEL1 - { - .channel = 1, - .mode = CONFIG_STM32_TIM2_CH1MODE, -#ifdef CONFIG_STM32_TIM2_CH1OUT - .out1 = - { - .in_use = 1, - .pol = CONFIG_STM32_TIM2_CH1POL, - .idle = CONFIG_STM32_TIM2_CH1IDLE, - .pincfg = PWM_TIM2_CH1CFG, - } -#endif - /* No complementary outputs */ - }, -#endif -#ifdef CONFIG_STM32_TIM2_CHANNEL2 - { - .channel = 2, - .mode = CONFIG_STM32_TIM2_CH2MODE, -#ifdef CONFIG_STM32_TIM2_CH2OUT - .out1 = - { - .in_use = 1, - .pol = CONFIG_STM32_TIM2_CH2POL, - .idle = CONFIG_STM32_TIM2_CH2IDLE, - .pincfg = PWM_TIM2_CH2CFG, - } -#endif - /* No complementary outputs */ - }, -#endif -#ifdef CONFIG_STM32_TIM2_CHANNEL3 - { - .channel = 3, - .mode = CONFIG_STM32_TIM2_CH3MODE, -#ifdef CONFIG_STM32_TIM2_CH3OUT - .out1 = - { - .in_use = 1, - .pol = CONFIG_STM32_TIM2_CH3POL, - .idle = CONFIG_STM32_TIM2_CH3IDLE, - .pincfg = PWM_TIM2_CH3CFG, - } -#endif - /* No complementary outputs */ - }, -#endif -#ifdef CONFIG_STM32_TIM2_CHANNEL4 - { - .channel = 4, - .mode = CONFIG_STM32_TIM2_CH4MODE, -#ifdef CONFIG_STM32_TIM2_CH4OUT - .out1 = - { - .in_use = 1, - .pol = CONFIG_STM32_TIM2_CH4POL, - .idle = CONFIG_STM32_TIM2_CH4IDLE, - .pincfg = PWM_TIM2_CH4CFG, - } -#endif - /* No complementary outputs */ - } -#endif -}; - -static struct stm32_pwmtimer_s g_pwm2dev = -{ - .ops = &g_pwmops, -#ifdef CONFIG_STM32_PWM_LL_OPS - .llops = &g_llpwmops, -#endif - .timid = 2, - .chan_num = PWM_TIM2_NCHANNELS, - .channels = g_pwm2channels, - .timtype = TIMTYPE_TIM2, - .mode = CONFIG_STM32_TIM2_MODE, - .lock = 0, /* No lock */ - .t_dts = 0, /* No t_dts */ -#ifdef HAVE_PWM_COMPLEMENTARY - .deadtime = 0, /* No deadtime */ -#endif -#if defined(HAVE_TRGO) && defined(STM32_TIM2_TRGO) - .trgo = STM32_TIM2_TRGO, -#endif - .base = STM32_TIM2_BASE, - .pclk = TIMCLK_TIM2, -}; -#endif /* CONFIG_STM32_TIM2_PWM */ - -#ifdef CONFIG_STM32_TIM3_PWM - -static struct stm32_pwmchan_s g_pwm3channels[] = -{ - /* TIM3 has 4 channels */ - -#ifdef CONFIG_STM32_TIM3_CHANNEL1 - { - .channel = 1, - .mode = CONFIG_STM32_TIM3_CH1MODE, -#ifdef CONFIG_STM32_TIM3_CH1OUT - .out1 = - { - .in_use = 1, - .pol = CONFIG_STM32_TIM3_CH1POL, - .idle = CONFIG_STM32_TIM3_CH1IDLE, - .pincfg = PWM_TIM3_CH1CFG, - } -#endif - /* No complementary outputs */ - }, -#endif -#ifdef CONFIG_STM32_TIM3_CHANNEL2 - { - .channel = 2, - .mode = CONFIG_STM32_TIM3_CH2MODE, -#ifdef CONFIG_STM32_TIM3_CH2OUT - .out1 = - { - .in_use = 1, - .pol = CONFIG_STM32_TIM3_CH2POL, - .idle = CONFIG_STM32_TIM3_CH2IDLE, - .pincfg = PWM_TIM3_CH2CFG, - } -#endif - /* No complementary outputs */ - }, -#endif -#ifdef CONFIG_STM32_TIM3_CHANNEL3 - { - .channel = 3, - .mode = CONFIG_STM32_TIM3_CH3MODE, -#ifdef CONFIG_STM32_TIM3_CH3OUT - .out1 = - { - .in_use = 1, - .pol = CONFIG_STM32_TIM3_CH3POL, - .idle = CONFIG_STM32_TIM3_CH3IDLE, - .pincfg = PWM_TIM3_CH3CFG, - } -#endif - /* No complementary outputs */ - }, -#endif -#ifdef CONFIG_STM32_TIM3_CHANNEL4 - { - .channel = 4, - .mode = CONFIG_STM32_TIM3_CH4MODE, -#ifdef CONFIG_STM32_TIM3_CH4OUT - .out1 = - { - .in_use = 1, - .pol = CONFIG_STM32_TIM3_CH4POL, - .idle = CONFIG_STM32_TIM3_CH4IDLE, - .pincfg = PWM_TIM3_CH4CFG, - } -#endif - /* No complementary outputs */ - } -#endif -}; - -static struct stm32_pwmtimer_s g_pwm3dev = -{ - .ops = &g_pwmops, -#ifdef CONFIG_STM32_PWM_LL_OPS - .llops = &g_llpwmops, -#endif - .timid = 3, - .chan_num = PWM_TIM3_NCHANNELS, - .channels = g_pwm3channels, - .timtype = TIMTYPE_TIM3, - .mode = CONFIG_STM32_TIM3_MODE, - .lock = 0, /* No lock */ - .t_dts = 0, /* No t_dts */ -#ifdef HAVE_PWM_COMPLEMENTARY - .deadtime = 0, /* No deadtime */ -#endif -#if defined(HAVE_TRGO) && defined(STM32_TIM3_TRGO) - .trgo = STM32_TIM3_TRGO, -#endif - .base = STM32_TIM3_BASE, - .pclk = TIMCLK_TIM3, -}; -#endif /* CONFIG_STM32_TIM3_PWM */ - -#ifdef CONFIG_STM32_TIM4_PWM - -static struct stm32_pwmchan_s g_pwm4channels[] = -{ - /* TIM4 has 4 channels */ - -#ifdef CONFIG_STM32_TIM4_CHANNEL1 - { - .channel = 1, - .mode = CONFIG_STM32_TIM4_CH1MODE, -#ifdef CONFIG_STM32_TIM4_CH1OUT - .out1 = - { - .in_use = 1, - .pol = CONFIG_STM32_TIM4_CH1POL, - .idle = CONFIG_STM32_TIM4_CH1IDLE, - .pincfg = PWM_TIM4_CH1CFG, - } -#endif - /* No complementary outputs */ - }, -#endif -#ifdef CONFIG_STM32_TIM4_CHANNEL2 - { - .channel = 2, - .mode = CONFIG_STM32_TIM4_CH2MODE, -#ifdef CONFIG_STM32_TIM4_CH2OUT - .out1 = - { - .in_use = 1, - .pol = CONFIG_STM32_TIM4_CH2POL, - .idle = CONFIG_STM32_TIM4_CH2IDLE, - .pincfg = PWM_TIM4_CH2CFG, - } -#endif - /* No complementary outputs */ - }, -#endif -#ifdef CONFIG_STM32_TIM4_CHANNEL3 - { - .channel = 3, - .mode = CONFIG_STM32_TIM4_CH3MODE, -#ifdef CONFIG_STM32_TIM4_CH3OUT - .out1 = - { - .in_use = 1, - .pol = CONFIG_STM32_TIM4_CH3POL, - .idle = CONFIG_STM32_TIM4_CH3IDLE, - .pincfg = PWM_TIM4_CH3CFG, - } -#endif - /* No complementary outputs */ - }, -#endif -#ifdef CONFIG_STM32_TIM4_CHANNEL4 - { - .channel = 4, - .mode = CONFIG_STM32_TIM4_CH4MODE, -#ifdef CONFIG_STM32_TIM4_CH4OUT - .out1 = - { - .in_use = 1, - .pol = CONFIG_STM32_TIM4_CH4POL, - .idle = CONFIG_STM32_TIM4_CH4IDLE, - .pincfg = PWM_TIM4_CH4CFG, - } -#endif - /* No complementary outputs */ - } -#endif -}; - -static struct stm32_pwmtimer_s g_pwm4dev = -{ - .ops = &g_pwmops, -#ifdef CONFIG_STM32_PWM_LL_OPS - .llops = &g_llpwmops, -#endif - .timid = 4, - .chan_num = PWM_TIM4_NCHANNELS, - .channels = g_pwm4channels, - .timtype = TIMTYPE_TIM4, - .mode = CONFIG_STM32_TIM4_MODE, - .lock = 0, /* No lock */ - .t_dts = 0, /* No t_dts */ -#ifdef HAVE_PWM_COMPLEMENTARY - .deadtime = 0, /* No deadtime */ -#endif -#if defined(HAVE_TRGO) && defined(STM32_TIM4_TRGO) - .trgo = STM32_TIM4_TRGO, -#endif - .base = STM32_TIM4_BASE, - .pclk = TIMCLK_TIM4, -}; -#endif /* CONFIG_STM32_TIM4_PWM */ - -#ifdef CONFIG_STM32_TIM5_PWM - -static struct stm32_pwmchan_s g_pwm5channels[] = -{ - /* TIM5 has 4 channels */ - -#ifdef CONFIG_STM32_TIM5_CHANNEL1 - { - .channel = 1, - .mode = CONFIG_STM32_TIM5_CH1MODE, -#ifdef CONFIG_STM32_TIM5_CH1OUT - .out1 = - { - .in_use = 1, - .pol = CONFIG_STM32_TIM5_CH1POL, - .idle = CONFIG_STM32_TIM5_CH1IDLE, - .pincfg = PWM_TIM5_CH1CFG, - } -#endif - /* No complementary outputs */ - }, -#endif -#ifdef CONFIG_STM32_TIM5_CHANNEL2 - { - .channel = 2, - .mode = CONFIG_STM32_TIM5_CH2MODE, -#ifdef CONFIG_STM32_TIM5_CH2OUT - .out1 = - { - .in_use = 1, - .pol = CONFIG_STM32_TIM5_CH2POL, - .idle = CONFIG_STM32_TIM5_CH2IDLE, - .pincfg = PWM_TIM5_CH2CFG, - } -#endif - /* No complementary outputs */ - }, -#endif -#ifdef CONFIG_STM32_TIM5_CHANNEL3 - { - .channel = 3, - .mode = CONFIG_STM32_TIM5_CH3MODE, -#ifdef CONFIG_STM32_TIM5_CH3OUT - .out1 = - { - .in_use = 1, - .pol = CONFIG_STM32_TIM5_CH3POL, - .idle = CONFIG_STM32_TIM5_CH3IDLE, - .pincfg = PWM_TIM5_CH3CFG, - } -#endif - }, -#endif -#ifdef CONFIG_STM32_TIM5_CHANNEL4 - { - .channel = 4, - .mode = CONFIG_STM32_TIM5_CH4MODE, -#ifdef CONFIG_STM32_TIM5_CH4OUT - .out1 = - { - .in_use = 1, - .pol = CONFIG_STM32_TIM5_CH4POL, - .idle = CONFIG_STM32_TIM5_CH4IDLE, - .pincfg = PWM_TIM5_CH4CFG, - } -#endif - }, -#endif -}; - -static struct stm32_pwmtimer_s g_pwm5dev = -{ - .ops = &g_pwmops, -#ifdef CONFIG_STM32_PWM_LL_OPS - .llops = &g_llpwmops, -#endif - .timid = 5, - .chan_num = PWM_TIM5_NCHANNELS, - .channels = g_pwm5channels, - .timtype = TIMTYPE_TIM5, - .mode = CONFIG_STM32_TIM5_MODE, - .lock = 0, /* No lock */ - .t_dts = 0, /* No t_dts */ -#ifdef HAVE_PWM_COMPLEMENTARY - .deadtime = 0, /* No deadtime */ -#endif -#if defined(HAVE_TRGO) && defined(STM32_TIM5_TRGO) - .trgo = STM32_TIM5_TRGO, -#endif - .base = STM32_TIM5_BASE, - .pclk = TIMCLK_TIM5, -}; -#endif /* CONFIG_STM32_TIM5_PWM */ - -#ifdef CONFIG_STM32_TIM8_PWM - -static struct stm32_pwmchan_s g_pwm8channels[] = -{ - /* TIM8 has 4 channels, 4 complementary */ - -#ifdef CONFIG_STM32_TIM8_CHANNEL1 - { - .channel = 1, - .mode = CONFIG_STM32_TIM8_CH1MODE, -#ifdef HAVE_BREAK - .brk = - { -#ifdef CONFIG_STM32_TIM8_BREAK1 - .en1 = 1, - .pol1 = CONFIG_STM32_TIM8_BRK1POL, -#endif -#ifdef CONFIG_STM32_TIM8_BREAK2 - .en2 = 1, - .pol2 = CONFIG_STM32_TIM8_BRK2POL, - .flt2 = CONFIG_STM32_TIM8_BRK2FLT, -#endif - }, -#endif -#ifdef CONFIG_STM32_TIM8_CH1OUT - .out1 = - { - .in_use = 1, - .pol = CONFIG_STM32_TIM8_CH1POL, - .idle = CONFIG_STM32_TIM8_CH1IDLE, - .pincfg = PWM_TIM8_CH1CFG, - }, -#endif -#ifdef CONFIG_STM32_TIM8_CH1NOUT - .out2 = - { - .in_use = 1, - .pol = CONFIG_STM32_TIM8_CH1NPOL, - .idle = CONFIG_STM32_TIM8_CH1NIDLE, - .pincfg = PWM_TIM8_CH1NCFG, - } -#endif - }, -#endif -#ifdef CONFIG_STM32_TIM8_CHANNEL2 - { - .channel = 2, - .mode = CONFIG_STM32_TIM8_CH2MODE, -#ifdef CONFIG_STM32_TIM8_CH2OUT - .out1 = - { - .in_use = 1, - .pol = CONFIG_STM32_TIM8_CH2POL, - .idle = CONFIG_STM32_TIM8_CH2IDLE, - .pincfg = PWM_TIM8_CH2CFG, - }, -#endif -#ifdef CONFIG_STM32_TIM8_CH2NOUT - .out2 = - { - .in_use = 1, - .pol = CONFIG_STM32_TIM8_CH2NPOL, - .idle = CONFIG_STM32_TIM8_CH2NIDLE, - .pincfg = PWM_TIM8_CH2NCFG, - } -#endif - }, -#endif -#ifdef CONFIG_STM32_TIM8_CHANNEL3 - { - .channel = 3, - .mode = CONFIG_STM32_TIM8_CH3MODE, -#ifdef CONFIG_STM32_TIM8_CH3OUT - .out1 = - { - .in_use = 1, - .pol = CONFIG_STM32_TIM8_CH3POL, - .idle = CONFIG_STM32_TIM8_CH3IDLE, - .pincfg = PWM_TIM8_CH3CFG, - }, -#endif -#ifdef CONFIG_STM32_TIM8_CH3NOUT - .out2 = - { - .in_use = 1, - .pol = CONFIG_STM32_TIM8_CH3NPOL, - .idle = CONFIG_STM32_TIM8_CH3NIDLE, - .pincfg = PWM_TIM8_CH3NCFG, - } -#endif - }, -#endif -#ifdef CONFIG_STM32_TIM8_CHANNEL4 - { - .channel = 4, - .mode = CONFIG_STM32_TIM8_CH4MODE, -#ifdef CONFIG_STM32_TIM8_CH4OUT - .out1 = - { - .in_use = 1, - .pol = CONFIG_STM32_TIM8_CH4POL, - .idle = CONFIG_STM32_TIM8_CH4IDLE, - .pincfg = PWM_TIM8_CH4CFG, - } -#endif - }, -#endif -#ifdef CONFIG_STM32_TIM8_CHANNEL5 - { - .channel = 5, - .mode = CONFIG_STM32_TIM8_CH5MODE, -#ifdef CONFIG_STM32_TIM8_CH5OUT - .out1 = - { - .in_use = 1, - .pol = CONFIG_STM32_TIM8_CH5POL, - .idle = CONFIG_STM32_TIM8_CH5IDLE, - .pincfg = 0, /* Not available externally */ - } -#endif - }, -#endif -#ifdef CONFIG_STM32_TIM8_CHANNEL6 - { - .channel = 6, - .mode = CONFIG_STM32_TIM8_CH6MODE, -#ifdef CONFIG_STM32_TIM8_CH6OUT - .out1 = - { - .in_use = 1, - .pol = CONFIG_STM32_TIM8_CH6POL, - .idle = CONFIG_STM32_TIM8_CH6IDLE, - .pincfg = 0, /* Not available externally */ - } -#endif - } -#endif -}; - -static struct stm32_pwmtimer_s g_pwm8dev = -{ - .ops = &g_pwmops, -#ifdef CONFIG_STM32_PWM_LL_OPS - .llops = &g_llpwmops, -#endif - .timid = 8, - .chan_num = PWM_TIM8_NCHANNELS, - .channels = g_pwm8channels, - .timtype = TIMTYPE_TIM8, - .mode = CONFIG_STM32_TIM8_MODE, - .lock = CONFIG_STM32_TIM8_LOCK, - .t_dts = CONFIG_STM32_TIM8_TDTS, -#ifdef HAVE_PWM_COMPLEMENTARY - .deadtime = CONFIG_STM32_TIM8_DEADTIME, -#endif -#if defined(HAVE_TRGO) && defined(STM32_TIM8_TRGO) - .trgo = STM32_TIM8_TRGO, -#endif - .base = STM32_TIM8_BASE, - .pclk = TIMCLK_TIM8, -}; -#endif /* CONFIG_STM32_TIM8_PWM */ - -#ifdef CONFIG_STM32_TIM9_PWM - -static struct stm32_pwmchan_s g_pwm9channels[] = -{ - /* TIM9 has 2 channels */ - -#ifdef CONFIG_STM32_TIM9_CHANNEL1 - { - .channel = 1, - .mode = CONFIG_STM32_TIM9_CH1MODE, -#ifdef CONFIG_STM32_TIM9_CH1OUT - .out1 = - { - .in_use = 1, - .pol = CONFIG_STM32_TIM9_CH1POL, - .idle = CONFIG_STM32_TIM9_CH1IDLE, - .pincfg = PWM_TIM9_CH1CFG, - } -#endif - /* No complementary outputs */ - }, -#endif -#ifdef CONFIG_STM32_TIM9_CHANNEL2 - { - .channel = 2, - .mode = CONFIG_STM32_TIM9_CH2MODE, -#ifdef CONFIG_STM32_TIM9_CH2OUT - .out1 = - { - .in_use = 1, - .pol = CONFIG_STM32_TIM9_CH2POL, - .idle = CONFIG_STM32_TIM9_CH2IDLE, - .pincfg = PWM_TIM9_CH2CFG, - } -#endif - /* No complementary outputs */ - } -#endif -}; - -static struct stm32_pwmtimer_s g_pwm9dev = -{ - .ops = &g_pwmops, -#ifdef CONFIG_STM32_PWM_LL_OPS - .llops = &g_llpwmops, -#endif - .timid = 9, - .chan_num = PWM_TIM9_NCHANNELS, - .channels = g_pwm9channels, - .timtype = TIMTYPE_TIM9, - .mode = STM32_TIMMODE_COUNTUP, - .lock = 0, /* No lock */ - .t_dts = 0, /* No t_dts */ -#ifdef HAVE_PWM_COMPLEMENTARY - .deadtime = 0, /* No deadtime */ -#endif -#if defined(HAVE_TRGO) - .trgo = 0, /* TRGO not supported for TIM9 */ -#endif - .base = STM32_TIM9_BASE, - .pclk = TIMCLK_TIM9, -}; -#endif /* CONFIG_STM32_TIM9_PWM */ - -#ifdef CONFIG_STM32_TIM10_PWM - -static struct stm32_pwmchan_s g_pwm10channels[] = -{ - /* TIM10 has 1 channel */ - -#ifdef CONFIG_STM32_TIM10_CHANNEL1 - { - .channel = 1, - .mode = CONFIG_STM32_TIM10_CH1MODE, -#ifdef CONFIG_STM32_TIM10_CH1OUT - .out1 = - { - .in_use = 1, - .pol = CONFIG_STM32_TIM10_CH1POL, - .idle = CONFIG_STM32_TIM10_CH1IDLE, - .pincfg = PWM_TIM10_CH1CFG, - } -#endif - /* No complementary outputs */ - } -#endif -}; - -static struct stm32_pwmtimer_s g_pwm10dev = -{ - .ops = &g_pwmops, -#ifdef CONFIG_STM32_PWM_LL_OPS - .llops = &g_llpwmops, -#endif - .timid = 10, - .chan_num = PWM_TIM10_NCHANNELS, - .channels = g_pwm10channels, - .timtype = TIMTYPE_TIM10, - .mode = STM32_TIMMODE_COUNTUP, - .lock = 0, /* No lock */ - .t_dts = 0, /* No t_dts */ -#ifdef HAVE_PWM_COMPLEMENTARY - .deadtime = 0, /* No deadtime */ -#endif -#if defined(HAVE_TRGO) - .trgo = 0, /* TRGO not supported for TIM10 */ -#endif - .base = STM32_TIM10_BASE, - .pclk = TIMCLK_TIM10, -}; -#endif /* CONFIG_STM32_TIM10_PWM */ - -#ifdef CONFIG_STM32_TIM11_PWM - -static struct stm32_pwmchan_s g_pwm11channels[] = -{ - /* TIM11 has 1 channel */ - -#ifdef CONFIG_STM32_TIM11_CHANNEL1 - { - .channel = 1, - .mode = CONFIG_STM32_TIM11_CH1MODE, -#ifdef CONFIG_STM32_TIM11_CH1OUT - .out1 = - { - .in_use = 1, - .pol = CONFIG_STM32_TIM11_CH1POL, - .idle = CONFIG_STM32_TIM11_CH1IDLE, - .pincfg = PWM_TIM11_CH1CFG, - } -#endif - /* No complementary outputs */ - } -#endif -}; - -static struct stm32_pwmtimer_s g_pwm11dev = -{ - .ops = &g_pwmops, -#ifdef CONFIG_STM32_PWM_LL_OPS - .llops = &g_llpwmops, -#endif - .timid = 11, - .chan_num = PWM_TIM11_NCHANNELS, - .channels = g_pwm11channels, - .timtype = TIMTYPE_TIM11, - .mode = STM32_TIMMODE_COUNTUP, - .lock = 0, /* No lock */ - .t_dts = 0, /* No t_dts */ -#ifdef HAVE_PWM_COMPLEMENTARY - .deadtime = 0, /* No deadtime */ -#endif -#if defined(HAVE_TRGO) - .trgo = 0, /* TRGO not supported for TIM11 */ -#endif - .base = STM32_TIM11_BASE, - .pclk = TIMCLK_TIM11, -}; -#endif /* CONFIG_STM32_TIM11_PWM */ - -#ifdef CONFIG_STM32_TIM12_PWM - -static struct stm32_pwmchan_s g_pwm12channels[] = -{ - /* TIM12 has 2 channels */ - -#ifdef CONFIG_STM32_TIM12_CHANNEL1 - { - .channel = 1, - .mode = CONFIG_STM32_TIM12_CH1MODE, -#ifdef CONFIG_STM32_TIM12_CH1OUT - .out1 = - { - .in_use = 1, - .pol = CONFIG_STM32_TIM12_CH1POL, - .idle = CONFIG_STM32_TIM12_CH1IDLE, - .pincfg = PWM_TIM12_CH1CFG, - } -#endif - /* No complementary outputs */ - }, -#endif -#ifdef CONFIG_STM32_TIM12_CHANNEL2 - { - .channel = 2, - .mode = CONFIG_STM32_TIM12_CH2MODE, -#ifdef CONFIG_STM32_TIM12_CH2OUT - .out1 = - { - .in_use = 1, - .pol = CONFIG_STM32_TIM12_CH2POL, - .idle = CONFIG_STM32_TIM12_CH2IDLE, - .pincfg = PWM_TIM12_CH2CFG, - } -#endif - /* No complementary outputs */ - } -#endif -}; - -static struct stm32_pwmtimer_s g_pwm12dev = -{ - .ops = &g_pwmops, -#ifdef CONFIG_STM32_PWM_LL_OPS - .llops = &g_llpwmops, -#endif - .timid = 12, - .chan_num = PWM_TIM12_NCHANNELS, - .channels = g_pwm12channels, - .timtype = TIMTYPE_TIM12, - .mode = STM32_TIMMODE_COUNTUP, - .lock = 0, /* No lock */ - .t_dts = 0, /* No t_dts */ -#ifdef HAVE_PWM_COMPLEMENTARY - .deadtime = 0, /* No deadtime */ -#endif -#if defined(HAVE_TRGO) - .trgo = 0, /* TRGO not supported for TIM12 */ -#endif - .base = STM32_TIM12_BASE, - .pclk = TIMCLK_TIM12, -}; -#endif /* CONFIG_STM32_TIM12_PWM */ - -#ifdef CONFIG_STM32_TIM13_PWM - -static struct stm32_pwmchan_s g_pwm13channels[] = -{ - /* TIM13 has 1 channel */ - -#ifdef CONFIG_STM32_TIM13_CHANNEL1 - { - .channel = 1, - .mode = CONFIG_STM32_TIM13_CH1MODE, -#ifdef CONFIG_STM32_TIM13_CH1OUT - .out1 = - { - .in_use = 1, - .pol = CONFIG_STM32_TIM13_CH1POL, - .idle = CONFIG_STM32_TIM13_CH1IDLE, - .pincfg = PWM_TIM13_CH1CFG, - } -#endif - /* No complementary outputs */ - } -#endif -}; - -static struct stm32_pwmtimer_s g_pwm13dev = -{ - .ops = &g_pwmops, -#ifdef CONFIG_STM32_PWM_LL_OPS - .llops = &g_llpwmops, -#endif - .timid = 13, - .chan_num = PWM_TIM13_NCHANNELS, - .channels = g_pwm13channels, - .timtype = TIMTYPE_TIM13, - .mode = STM32_TIMMODE_COUNTUP, - .lock = 0, /* No lock */ - .t_dts = 0, /* No t_dts */ -#ifdef HAVE_PWM_COMPLEMENTARY - .deadtime = 0, /* No deadtime */ -#endif -#if defined(HAVE_TRGO) - .trgo = 0, /* TRGO not supported for TIM13 */ -#endif - .base = STM32_TIM13_BASE, - .pclk = TIMCLK_TIM13, -}; -#endif /* CONFIG_STM32_TIM13_PWM */ - -#ifdef CONFIG_STM32_TIM14_PWM - -static struct stm32_pwmchan_s g_pwm14channels[] = -{ - /* TIM14 has 1 channel */ - -#ifdef CONFIG_STM32_TIM14_CHANNEL1 - { - .channel = 1, - .mode = CONFIG_STM32_TIM14_CH1MODE, -#ifdef CONFIG_STM32_TIM14_CH1OUT - .out1 = - { - .in_use = 1, - .pol = CONFIG_STM32_TIM14_CH1POL, - .idle = CONFIG_STM32_TIM14_CH1IDLE, - .pincfg = PWM_TIM14_CH1CFG, - } -#endif - /* No complementary outputs */ - } -#endif -}; - -static struct stm32_pwmtimer_s g_pwm14dev = -{ - .ops = &g_pwmops, -#ifdef CONFIG_STM32_PWM_LL_OPS - .llops = &g_llpwmops, -#endif - .timid = 14, - .chan_num = PWM_TIM14_NCHANNELS, - .channels = g_pwm14channels, - .timtype = TIMTYPE_TIM14, - .mode = STM32_TIMMODE_COUNTUP, - .lock = 0, /* No lock */ - .t_dts = 0, /* No t_dts */ -#ifdef HAVE_PWM_COMPLEMENTARY - .deadtime = 0, /* No deadtime */ -#endif -#if defined(HAVE_TRGO) - .trgo = 0, /* TRGO not supported for TIM14 */ -#endif - .base = STM32_TIM14_BASE, - .pclk = TIMCLK_TIM14, -}; -#endif /* CONFIG_STM32_TIM14_PWM */ - -#ifdef CONFIG_STM32_TIM15_PWM - -static struct stm32_pwmchan_s g_pwm15channels[] = -{ - /* TIM15 has 2 channels, 1 complementary */ - -#ifdef CONFIG_STM32_TIM15_CHANNEL1 - { - .channel = 1, - .mode = CONFIG_STM32_TIM15_CH1MODE, -#ifdef HAVE_BREAK - .brk = - { -#ifdef CONFIG_STM32_TIM15_BREAK1 - .en1 = 1, - .pol1 = CONFIG_STM32_TIM15_BRK1POL, -#endif - /* No BREAK2 */ - }, -#endif -#ifdef CONFIG_STM32_TIM15_CH1OUT - .out1 = - { - .in_use = 1, - .pol = CONFIG_STM32_TIM15_CH1POL, - .idle = CONFIG_STM32_TIM15_CH1IDLE, - .pincfg = PWM_TIM15_CH1CFG, - }, -#endif -#ifdef CONFIG_STM32_TIM15_CH1NOUT - .out2 = - { - .in_use = 1, - .pol = CONFIG_STM32_TIM15_CH1NPOL, - .idle = CONFIG_STM32_TIM15_CH1NIDLE, - .pincfg = PWM_TIM15_CH2CFG, - } -#endif - }, -#endif -#ifdef CONFIG_STM32_TIM15_CHANNEL2 - { - .channel = 2, - .mode = CONFIG_STM32_TIM15_CH2MODE, -#ifdef CONFIG_STM32_TIM12_CH2OUT - .out1 = - { - .in_use = 1, - .pol = CONFIG_STM32_TIM15_CH2POL, - .idle = CONFIG_STM32_TIM15_CH2IDLE, - .pincfg = PWM_TIM15_CH2CFG, - } -#endif - /* No complementary outputs */ - }, -#endif -}; - -static struct stm32_pwmtimer_s g_pwm15dev = -{ - .ops = &g_pwmops, -#ifdef CONFIG_STM32_PWM_LL_OPS - .llops = &g_llpwmops, -#endif - .timid = 15, - .chan_num = PWM_TIM15_NCHANNELS, - .channels = g_pwm15channels, - .timtype = TIMTYPE_TIM15, - .mode = STM32_TIMMODE_COUNTUP, - .lock = CONFIG_STM32_TIM15_LOCK, - .t_dts = CONFIG_STM32_TIM15_TDTS, -#ifdef HAVE_PWM_COMPLEMENTARY - .deadtime = CONFIG_STM32_TIM15_DEADTIME, -#endif -#if defined(HAVE_TRGO) && defined(STM32_TIM15_TRGO) - .trgo = STM32_TIM15_TRGO, -#endif - .base = STM32_TIM15_BASE, - .pclk = TIMCLK_TIM15, -}; -#endif /* CONFIG_STM32_TIM15_PWM */ - -#ifdef CONFIG_STM32_TIM16_PWM - -static struct stm32_pwmchan_s g_pwm16channels[] = -{ - /* TIM16 has 1 channel, 1 complementary */ - -#ifdef CONFIG_STM32_TIM16_CHANNEL1 - { - .channel = 1, - .mode = CONFIG_STM32_TIM16_CH1MODE, -#ifdef HAVE_BREAK - .brk = - { -#ifdef CONFIG_STM32_TIM16_BREAK1 - .en1 = 1, - .pol1 = CONFIG_STM32_TIM16_BRK1POL, -#endif - /* No BREAK2 */ - }, -#endif -#ifdef CONFIG_STM32_TIM16_CH1OUT - .out1 = - { - .in_use = 1, - .pol = CONFIG_STM32_TIM16_CH1POL, - .idle = CONFIG_STM32_TIM16_CH1IDLE, - .pincfg = PWM_TIM16_CH1CFG, - }, -#endif -#ifdef CONFIG_STM32_TIM16_CH1NOUT - .out2 = - { - .in_use = 1, - .pol = CONFIG_STM32_TIM16_CH1NPOL, - .idle = CONFIG_STM32_TIM16_CH1NIDLE, - .pincfg = PWM_TIM16_CH2CFG, - } -#endif - }, -#endif -}; - -static struct stm32_pwmtimer_s g_pwm16dev = -{ - .ops = &g_pwmops, -#ifdef CONFIG_STM32_PWM_LL_OPS - .llops = &g_llpwmops, -#endif - .timid = 16, - .chan_num = PWM_TIM16_NCHANNELS, - .channels = g_pwm16channels, - .timtype = TIMTYPE_TIM16, - .mode = STM32_TIMMODE_COUNTUP, - .lock = CONFIG_STM32_TIM16_LOCK, - .t_dts = CONFIG_STM32_TIM16_TDTS, -#ifdef HAVE_PWM_COMPLEMENTARY - .deadtime = CONFIG_STM32_TIM16_DEADTIME, -#endif -#if defined(HAVE_TRGO) - .trgo = 0, /* TRGO not supported for TIM16 */ -#endif - .base = STM32_TIM16_BASE, - .pclk = TIMCLK_TIM16, -}; -#endif /* CONFIG_STM32_TIM16_PWM */ - -#ifdef CONFIG_STM32_TIM17_PWM - -static struct stm32_pwmchan_s g_pwm17channels[] = -{ - /* TIM17 has 1 channel, 1 complementary */ - -#ifdef CONFIG_STM32_TIM17_CHANNEL1 - { - .channel = 1, - .mode = CONFIG_STM32_TIM17_CH1MODE, -#ifdef HAVE_BREAK - .brk = - { -#ifdef CONFIG_STM32_TIM17_BREAK1 - .en1 = 1, - .pol1 = CONFIG_STM32_TIM17_BRK1POL, -#endif - /* No BREAK2 */ - }, -#endif -#ifdef CONFIG_STM32_TIM17_CH1OUT - .out1 = - { - .in_use = 1, - .pol = CONFIG_STM32_TIM17_CH1POL, - .idle = CONFIG_STM32_TIM17_CH1IDLE, - .pincfg = PWM_TIM17_CH1CFG, - }, -#endif -#ifdef CONFIG_STM32_TIM17_CH1NOUT - .out2 = - { - .in_use = 1, - .pol = CONFIG_STM32_TIM17_CH1NPOL, - .idle = CONFIG_STM32_TIM17_CH1NIDLE, - .pincfg = PWM_TIM17_CH2CFG, - } -#endif - }, -#endif -}; - -static struct stm32_pwmtimer_s g_pwm17dev = -{ - .ops = &g_pwmops, -#ifdef CONFIG_STM32_PWM_LL_OPS - .llops = &g_llpwmops, -#endif - .timid = 17, - .chan_num = PWM_TIM17_NCHANNELS, - .channels = g_pwm17channels, - .timtype = TIMTYPE_TIM17, - .mode = STM32_TIMMODE_COUNTUP, - .lock = CONFIG_STM32_TIM17_LOCK, - .t_dts = CONFIG_STM32_TIM17_TDTS, -#ifdef HAVE_PWM_COMPLEMENTARY - .deadtime = CONFIG_STM32_TIM17_DEADTIME, -#endif -#if defined(HAVE_TRGO) - .trgo = 0, /* TRGO not supported for TIM17 */ -#endif - .base = STM32_TIM17_BASE, - .pclk = TIMCLK_TIM17, -}; -#endif /* CONFIG_STM32_TIM17_PWM */ - -/* TODO: support for TIM19,20,21,22 */ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: pwm_reg_is_32bit - ****************************************************************************/ - -static bool pwm_reg_is_32bit(uint8_t timtype, uint32_t offset) -{ - bool ret = false; - - if (timtype == TIMTYPE_GENERAL32) - { - if (offset == STM32_GTIM_CNT_OFFSET || - offset == STM32_GTIM_ARR_OFFSET || - offset == STM32_GTIM_CCR1_OFFSET || - offset == STM32_GTIM_CCR2_OFFSET || - offset == STM32_GTIM_CCR3_OFFSET || - offset == STM32_GTIM_CCR4_OFFSET) - { - ret = true; - } - } -#ifdef HAVE_IP_TIMERS_V2 - else if (timtype == TIMTYPE_ADVANCED) - { - if (offset == STM32_ATIM_CR2_OFFSET || - offset == STM32_ATIM_CCMR1_OFFSET || - offset == STM32_ATIM_CCMR2_OFFSET || - offset == STM32_ATIM_CCER_OFFSET || - offset == STM32_ATIM_BDTR_OFFSET || - offset == STM32_ATIM_CCMR3_OFFSET || - offset == STM32_ATIM_CCR5_OFFSET) - { - ret = true; - } - } -#endif - - return ret; -} - -/**************************************************************************** - * Name: pwm_getreg - * - * Description: - * Read the value of an PWM timer register - * - * Input Parameters: - * priv - A reference to the PWM block status - * offset - The offset to the register to read - * - * Returned Value: - * The current contents of the specified register - * - ****************************************************************************/ - -static uint32_t pwm_getreg(struct stm32_pwmtimer_s *priv, int offset) -{ - uint32_t retval = 0; - - if (pwm_reg_is_32bit(priv->timtype, offset) == true) - { - /* 32-bit register */ - - retval = getreg32(priv->base + offset); - } - else - { - /* 16-bit register */ - - retval = getreg16(priv->base + offset); - } - - /* Return 32-bit value */ - - return retval; -} - -/**************************************************************************** - * Name: pwm_putreg - * - * Description: - * Read the value of an PWM timer register - * - * Input Parameters: - * priv - A reference to the PWM block status - * offset - The offset to the register to read - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void pwm_putreg(struct stm32_pwmtimer_s *priv, int offset, - uint32_t value) -{ - if (pwm_reg_is_32bit(priv->timtype, offset) == true) - { - /* 32-bit register */ - - putreg32(value, priv->base + offset); - } - else - { - /* 16-bit register */ - - putreg16((uint16_t)value, priv->base + offset); - } -} - -/**************************************************************************** - * Name: pwm_modifyreg - * - * Description: - * Modify PWM register (32-bit or 16-bit) - * - * Input Parameters: - * priv - A reference to the PWM block status - * offset - The offset to the register to read - * clrbits - The bits to clear - * setbits - The bits to set - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void pwm_modifyreg(struct stm32_pwmtimer_s *priv, uint32_t offset, - uint32_t clearbits, uint32_t setbits) -{ - if (pwm_reg_is_32bit(priv->timtype, offset) == true) - { - /* 32-bit register */ - - modifyreg32(priv->base + offset, clearbits, setbits); - } - else - { - /* 16-bit register */ - - modifyreg16(priv->base + offset, (uint16_t)clearbits, - (uint16_t)setbits); - } -} - -/**************************************************************************** - * Name: pwm_dumpregs - * - * Description: - * Dump all timer registers. - * - * Input Parameters: - * dev - A reference to the lower half PWM driver state structure - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef CONFIG_DEBUG_PWM_INFO -static void pwm_dumpregs(struct pwm_lowerhalf_s *dev, const char *msg) -{ - struct stm32_pwmtimer_s *priv = (struct stm32_pwmtimer_s *)dev; - - pwminfo("%s:\n", msg); - if (priv->timid == 16 || priv->timid == 17) - { - pwminfo(" CR1: %04x CR2: %04x DIER: %04x\n", - pwm_getreg(priv, STM32_GTIM_CR1_OFFSET), - pwm_getreg(priv, STM32_GTIM_CR2_OFFSET), - pwm_getreg(priv, STM32_GTIM_DIER_OFFSET)); - } - else - { - pwminfo(" CR1: %04x CR2: %04x SMCR: %04x DIER: %04x\n", - pwm_getreg(priv, STM32_GTIM_CR1_OFFSET), - pwm_getreg(priv, STM32_GTIM_CR2_OFFSET), - pwm_getreg(priv, STM32_GTIM_SMCR_OFFSET), - pwm_getreg(priv, STM32_GTIM_DIER_OFFSET)); - } - - if (priv->timid >= 15 && priv->timid <= 17) - { - pwminfo(" SR: %04x EGR: %04x CCMR1: %04x\n", - pwm_getreg(priv, STM32_GTIM_SR_OFFSET), - pwm_getreg(priv, STM32_GTIM_EGR_OFFSET), - pwm_getreg(priv, STM32_GTIM_CCMR1_OFFSET)); - } - else - { - pwminfo(" SR: %04x EGR: %04x CCMR1: %04x CCMR2: %04x\n", - pwm_getreg(priv, STM32_GTIM_SR_OFFSET), - pwm_getreg(priv, STM32_GTIM_EGR_OFFSET), - pwm_getreg(priv, STM32_GTIM_CCMR1_OFFSET), - pwm_getreg(priv, STM32_GTIM_CCMR2_OFFSET)); - } - - /* REVISIT: CNT and ARR may be 32-bits wide */ - - pwminfo(" CCER: %04x CNT: %04x PSC: %04x ARR: %04x\n", - pwm_getreg(priv, STM32_GTIM_CCER_OFFSET), - pwm_getreg(priv, STM32_GTIM_CNT_OFFSET), - pwm_getreg(priv, STM32_GTIM_PSC_OFFSET), - pwm_getreg(priv, STM32_GTIM_ARR_OFFSET)); - - if (priv->timid == 1 || priv->timid == 8 || - (priv->timid >= 15 && priv->timid <= 17)) - { - pwminfo(" RCR: %04x BDTR: %04x\n", - pwm_getreg(priv, STM32_ATIM_RCR_OFFSET), - pwm_getreg(priv, STM32_ATIM_BDTR_OFFSET)); - } - - /* REVISIT: CCR1-CCR4 may be 32-bits wide */ - - if (priv->timid == 16 || priv->timid == 17) - { - pwminfo(" CCR1: %04x\n", - pwm_getreg(priv, STM32_GTIM_CCR1_OFFSET)); - } - else if (priv->timid == 15) - { - pwminfo(" CCR1: %04x CCR2: %04x\n", - pwm_getreg(priv, STM32_GTIM_CCR1_OFFSET), - pwm_getreg(priv, STM32_GTIM_CCR2_OFFSET)); - } - else - { - pwminfo(" CCR1: %04x CCR2: %04x CCR3: %04x CCR4: %04x\n", - pwm_getreg(priv, STM32_GTIM_CCR1_OFFSET), - pwm_getreg(priv, STM32_GTIM_CCR2_OFFSET), - pwm_getreg(priv, STM32_GTIM_CCR3_OFFSET), - pwm_getreg(priv, STM32_GTIM_CCR4_OFFSET)); - } - - pwminfo(" DCR: %04x DMAR: %04x\n", - pwm_getreg(priv, STM32_GTIM_DCR_OFFSET), - pwm_getreg(priv, STM32_GTIM_DMAR_OFFSET)); - -#ifdef HAVE_IP_TIMERS_V2 - if (priv->timtype == TIMTYPE_ADVANCED) - { - pwminfo(" CCMR3: %04x CCR5: %04x CCR6: %04x\n", - pwm_getreg(priv, STM32_ATIM_CCMR3_OFFSET), - pwm_getreg(priv, STM32_ATIM_CCR5_OFFSET), - pwm_getreg(priv, STM32_ATIM_CCR6_OFFSET)); - } -#endif -} -#endif - -/**************************************************************************** - * Name: pwm_ccr_update - ****************************************************************************/ - -static int pwm_ccr_update(struct pwm_lowerhalf_s *dev, uint8_t index, - uint32_t ccr) -{ - struct stm32_pwmtimer_s *priv = (struct stm32_pwmtimer_s *)dev; - uint32_t offset = 0; - - /* Only ADV timers have CC5 and CC6 */ - -#ifdef HAVE_IP_TIMERS_V2 - if (priv->timtype != TIMTYPE_ADVANCED && (index == 5 || index == 6)) - { - pwmerr("ERROR: No such CCR: %u\n", index); - return -EINVAL; - } -#endif - - /* REVISIT: start index from 0? */ - - switch (index) - { - case STM32_PWM_CHAN1: - { - offset = STM32_GTIM_CCR1_OFFSET; - break; - } - - case STM32_PWM_CHAN2: - { - offset = STM32_GTIM_CCR2_OFFSET; - break; - } - - case STM32_PWM_CHAN3: - { - offset = STM32_GTIM_CCR3_OFFSET; - break; - } - - case STM32_PWM_CHAN4: - { - offset = STM32_GTIM_CCR4_OFFSET; - break; - } - -#ifdef HAVE_IP_TIMERS_V2 - case STM32_PWM_CHAN5: - { - offset = STM32_ATIM_CCR5_OFFSET; - break; - } - - case STM32_PWM_CHAN6: - { - offset = STM32_ATIM_CCR6_OFFSET; - break; - } -#endif - - default: - { - pwmerr("ERROR: No such CCR: %u\n", index); - return -EINVAL; - } - } - - /* Update CCR register */ - - pwm_putreg(priv, offset, ccr); - - return OK; -} - -/**************************************************************************** - * Name: pwm_ccr_get - ****************************************************************************/ - -#ifdef CONFIG_STM32_PWM_LL_OPS -static uint32_t pwm_ccr_get(struct pwm_lowerhalf_s *dev, uint8_t index) -{ - struct stm32_pwmtimer_s *priv = (struct stm32_pwmtimer_s *)dev; - uint32_t offset = 0; - - switch (index) - { - case STM32_PWM_CHAN1: - { - offset = STM32_GTIM_CCR1_OFFSET; - break; - } - - case STM32_PWM_CHAN2: - { - offset = STM32_GTIM_CCR2_OFFSET; - break; - } - - case STM32_PWM_CHAN3: - { - offset = STM32_GTIM_CCR3_OFFSET; - break; - } - - case STM32_PWM_CHAN4: - { - offset = STM32_GTIM_CCR4_OFFSET; - break; - } - -#ifdef HAVE_IP_TIMERS_V2 - case STM32_PWM_CHAN5: - { - offset = STM32_ATIM_CCR5_OFFSET; - break; - } - - case STM32_PWM_CHAN6: - { - offset = STM32_ATIM_CCR6_OFFSET; - break; - } -#endif - - default: - { - pwmerr("ERROR: No such CCR: %u\n", index); - return -EINVAL; - } - } - - /* Return CCR register */ - - return pwm_getreg(priv, offset); -} -#endif /* CONFIG_STM32_PWM_LL_OPS */ - -/**************************************************************************** - * Name: pwm_arr_update - ****************************************************************************/ - -static int pwm_arr_update(struct pwm_lowerhalf_s *dev, uint32_t arr) -{ - struct stm32_pwmtimer_s *priv = (struct stm32_pwmtimer_s *)dev; - - /* Update ARR register */ - - pwm_putreg(priv, STM32_GTIM_ARR_OFFSET, arr); - - return OK; -} - -/**************************************************************************** - * Name: pwm_arr_get - ****************************************************************************/ - -static uint32_t pwm_arr_get(struct pwm_lowerhalf_s *dev) -{ - struct stm32_pwmtimer_s *priv = (struct stm32_pwmtimer_s *)dev; - - return pwm_getreg(priv, STM32_GTIM_ARR_OFFSET); -} - -#ifdef HAVE_ADVTIM -/**************************************************************************** - * Name: pwm_rcr_update - ****************************************************************************/ - -static int pwm_rcr_update(struct pwm_lowerhalf_s *dev, uint16_t rcr) -{ - struct stm32_pwmtimer_s *priv = (struct stm32_pwmtimer_s *)dev; - - /* Update RCR register */ - - pwm_putreg(priv, STM32_ATIM_RCR_OFFSET, rcr); - - return OK; -} -#endif - -#ifdef CONFIG_STM32_PWM_LL_OPS -/**************************************************************************** - * Name: pwm_rcr_get - ****************************************************************************/ - -static uint16_t pwm_rcr_get(struct pwm_lowerhalf_s *dev) -{ - struct stm32_pwmtimer_s *priv = (struct stm32_pwmtimer_s *)dev; - - return pwm_getreg(priv, STM32_ATIM_RCR_OFFSET); -} -#endif - -/**************************************************************************** - * Name: pwm_duty_update - * - * Description: - * Try to change only channel duty - * - * Input Parameters: - * dev - A reference to the lower half PWM driver state structure - * channel - Channel to by updated - * duty - New duty - * - * Returned Value: - * Zero on success; a negated errno value on failure - * - ****************************************************************************/ - -static int pwm_duty_update(struct pwm_lowerhalf_s *dev, uint8_t channel, - ub16_t duty) -{ - struct stm32_pwmtimer_s *priv = (struct stm32_pwmtimer_s *)dev; - uint32_t reload = 0; - uint32_t ccr = 0; - - /* We don't want compilation warnings if no DEBUGASSERT */ - - UNUSED(priv); - - DEBUGASSERT(priv != NULL); - - pwminfo("TIM%u channel: %u duty: %08" PRIx32 "\n", - priv->timid, channel, duty); - - /* Get the reload values */ - - reload = pwm_arr_get(dev); - - /* Duty cycle: - * - * duty cycle = ccr / reload (fractional value) - */ - - ccr = b16toi(duty * reload + b16HALF); - - pwminfo("ccr: %" PRIu32 "\n", ccr); - - /* Write corresponding CCR register */ - - pwm_ccr_update(dev, channel, ccr); - - return OK; -} - -/**************************************************************************** - * Name: pwm_timer_enable - ****************************************************************************/ - -static int pwm_timer_enable(struct pwm_lowerhalf_s *dev, bool state) -{ - struct stm32_pwmtimer_s *priv = (struct stm32_pwmtimer_s *)dev; - - if (state == true) - { - /* Enable timer counter */ - - pwm_modifyreg(priv, STM32_GTIM_CR1_OFFSET, 0, GTIM_CR1_CEN); - } - else - { - /* Disable timer counter */ - - pwm_modifyreg(priv, STM32_GTIM_CR1_OFFSET, GTIM_CR1_CEN, 0); - } - - return OK; -} - -/**************************************************************************** - * Name: pwm_frequency_update - * - * Description: - * Update a PWM timer frequency - * - ****************************************************************************/ - -static int pwm_frequency_update(struct pwm_lowerhalf_s *dev, - uint32_t frequency) -{ - struct stm32_pwmtimer_s *priv = (struct stm32_pwmtimer_s *)dev; - uint32_t reload = 0; - uint32_t timclk = 0; - uint32_t prescaler = 0; - - /* Calculate optimal values for the timer prescaler and for the timer - * reload register. If 'frequency' is the desired frequency, then - * - * reload = timclk / frequency - * timclk = pclk / presc - * - * Or, - * - * reload = pclk / presc / frequency - * - * There are many solutions to this, but the best solution will be the one - * that has the largest reload value and the smallest prescaler value. - * That is the solution that should give us the most accuracy in the timer - * control. Subject to: - * - * 0 <= presc <= 65536 - * 1 <= reload <= 65535 - * - * So presc = pclk / 65535 / frequency would be optimal. - * - * Example: - * - * pclk = 42 MHz - * frequency = 100 Hz - * - * prescaler = 42,000,000 / 65,535 / 100 - * = 6.4 (or 7 -- taking the ceiling always) - * timclk = 42,000,000 / 7 - * = 6,000,000 - * reload = 6,000,000 / 100 - * = 60,000 - */ - - prescaler = (priv->pclk / frequency + 65534) / 65535; - if (prescaler < 1) - { - prescaler = 1; - } - else if (prescaler > 65536) - { - prescaler = 65536; - } - - timclk = priv->pclk / prescaler; - - reload = timclk / frequency; - if (reload < 2) - { - reload = 1; - } - else if (reload > 65535) - { - reload = 65535; - } - else - { - reload--; - } - - pwminfo("TIM%u PCLK: %" PRIu32" frequency: %" PRIu32 - " TIMCLK: %" PRIu32 " " - "prescaler: %" PRIu32 " reload: %" PRIu32 "\n", - priv->timid, priv->pclk, frequency, timclk, prescaler, reload); - - /* Set the reload and prescaler values */ - - pwm_arr_update(dev, reload); - pwm_putreg(priv, STM32_GTIM_PSC_OFFSET, (uint16_t)(prescaler - 1)); - - return OK; -} - -/**************************************************************************** - * Name: pwm_timer_configure - * - * Description: - * Initial configuration for PWM timer - * - ****************************************************************************/ - -static int pwm_timer_configure(struct stm32_pwmtimer_s *priv) -{ - uint16_t cr1 = 0; - int ret = OK; - - /* Set up the timer CR1 register: - * - * 1,8 CKD[1:0] ARPE CMS[1:0] DIR OPM URS UDIS CEN - * 2-5 CKD[1:0] ARPE CMS DIR OPM URS UDIS CEN - * 6-7 ARPE OPM URS UDIS CEN - * 9-14 CKD[1:0] ARPE URS UDIS CEN - * 15-17 CKD[1:0] ARPE OPM URS UDIS CEN - */ - - cr1 = pwm_getreg(priv, STM32_GTIM_CR1_OFFSET); - - /* Set the counter mode for the advanced timers (1,8) and most general - * purpose timers (all 2-5, but not 9-17), i.e., all but TIMTYPE_COUNTUP16 - * and TIMTYPE_BASIC - */ - - if (priv->timtype != TIMTYPE_BASIC && priv->timtype != TIMTYPE_COUNTUP16) - { - /* Select the Counter Mode: - * - * GTIM_CR1_EDGE: The counter counts up or down depending on the - * direction bit (DIR). - * GTIM_CR1_CENTER1, GTIM_CR1_CENTER2, GTIM_CR1_CENTER3: The counter - * counts up then down. - * GTIM_CR1_DIR: 0: count up, 1: count down - */ - - cr1 &= ~(GTIM_CR1_DIR | GTIM_CR1_CMS_MASK); - - switch (priv->mode) - { - case STM32_TIMMODE_COUNTUP: - { - cr1 |= GTIM_CR1_EDGE; - break; - } - - case STM32_TIMMODE_COUNTDOWN: - { - cr1 |= GTIM_CR1_EDGE | GTIM_CR1_DIR; - break; - } - - case STM32_TIMMODE_CENTER1: - { - cr1 |= GTIM_CR1_CENTER1; - break; - } - - case STM32_TIMMODE_CENTER2: - { - cr1 |= GTIM_CR1_CENTER2; - break; - } - - case STM32_TIMMODE_CENTER3: - { - cr1 |= GTIM_CR1_CENTER3; - break; - } - - default: - { - pwmerr("ERROR: No such timer mode: %u\n", - (unsigned int)priv->mode); - ret = -EINVAL; - goto errout; - } - } - } - - /* Enable ARR Preload - * TODO: this should be configurable - */ - - cr1 |= GTIM_CR1_ARPE; - - /* Write CR1 */ - - pwm_putreg(priv, STM32_GTIM_CR1_OFFSET, cr1); - -errout: - return ret; -} - -/**************************************************************************** - * Name: pwm_mode_configure - * - * Description: - * Configure a PWM mode for given channel - * - ****************************************************************************/ - -static int pwm_mode_configure(struct pwm_lowerhalf_s *dev, - uint8_t channel, uint32_t mode) -{ - struct stm32_pwmtimer_s *priv = (struct stm32_pwmtimer_s *)dev; - uint32_t chanmode = 0; - uint32_t ocmode = 0; - uint32_t ccmr = 0; - uint32_t offset = 0; - int ret = OK; -#ifdef HAVE_IP_TIMERS_V2 - bool ocmbit = false; -#endif - -#ifdef HAVE_IP_TIMERS_V2 - /* Only advanced timers have channels 5-6 */ - - if (channel > 4 && priv->timtype != TIMTYPE_ADVANCED) - { - pwmerr("ERROR: No such channel: %u\n", channel); - ret = -EINVAL; - goto errout; - } -#endif - - /* Get channel mode - * TODO: configurable preload for CCxR - */ - - switch (mode) - { - case STM32_CHANMODE_FRZN: - { - chanmode = GTIM_CCMR_MODE_FRZN; - break; - } - - case STM32_CHANMODE_CHACT: - { - chanmode = GTIM_CCMR_MODE_CHACT; - break; - } - - case STM32_CHANMODE_CHINACT: - { - chanmode = GTIM_CCMR_MODE_CHINACT; - break; - } - - case STM32_CHANMODE_OCREFTOG: - { - chanmode = GTIM_CCMR_MODE_OCREFTOG; - break; - } - - case STM32_CHANMODE_OCREFLO: - { - chanmode = GTIM_CCMR_MODE_OCREFLO; - break; - } - - case STM32_CHANMODE_OCREFHI: - { - chanmode = GTIM_CCMR_MODE_OCREFHI; - break; - } - - case STM32_CHANMODE_PWM1: - { - chanmode = GTIM_CCMR_MODE_PWM1; - break; - } - - case STM32_CHANMODE_PWM2: - { - chanmode = GTIM_CCMR_MODE_PWM2; - break; - } - -#ifdef HAVE_IP_TIMERS_V2 - case STM32_CHANMODE_COMBINED1: - { - chanmode = ATIM_CCMR_MODE_COMBINED1; - ocmbit = true; - break; - } - - case STM32_CHANMODE_COMBINED2: - { - chanmode = ATIM_CCMR_MODE_COMBINED2; - ocmbit = true; - break; - } - - case STM32_CHANMODE_ASYMMETRIC1: - { - chanmode = ATIM_CCMR_MODE_ASYMMETRIC1; - ocmbit = true; - break; - } - - case STM32_CHANMODE_ASYMMETRIC2: - { - chanmode = ATIM_CCMR_MODE_ASYMMETRIC2; - ocmbit = true; - break; - } -#endif - - default: - { - pwmerr("ERROR: No such mode: %u\n", (unsigned int)mode); - ret = -EINVAL; - goto errout; - } - } - - /* Get CCMR offset */ - - switch (channel) - { - case STM32_PWM_CHAN1: - case STM32_PWM_CHAN2: - { - offset = STM32_GTIM_CCMR1_OFFSET; - break; - } - - case STM32_PWM_CHAN3: - case STM32_PWM_CHAN4: - { - offset = STM32_GTIM_CCMR2_OFFSET; - break; - } - -#ifdef HAVE_IP_TIMERS_V2 - case STM32_PWM_CHAN5: - case STM32_PWM_CHAN6: - { - offset = STM32_ATIM_CCMR3_OFFSET; - break; - } -#endif - - default: - { - pwmerr("ERROR: No such channel: %u\n", channel); - ret = -EINVAL; - goto errout; - } - } - - /* Get current registers */ - - ccmr = pwm_getreg(priv, offset); - - /* PWM mode configuration. - * NOTE: The CCMRx registers are identical if the channels are outputs. - */ - - switch (channel) - { - /* Configure channel 1/3/5 */ - - case STM32_PWM_CHAN1: - case STM32_PWM_CHAN3: -#ifdef HAVE_IP_TIMERS_V2 - case STM32_PWM_CHAN5: -#endif - { - /* Reset current channel 1/3/5 mode configuration */ - - ccmr &= ~(ATIM_CCMR1_CC1S_MASK | ATIM_CCMR1_OC1M_MASK | - ATIM_CCMR1_OC1PE); - - /* Configure CC1/3/5 as output */ - - ocmode |= (ATIM_CCMR_CCS_CCOUT << ATIM_CCMR1_CC1S_SHIFT); - - /* Configure Compare 1/3/5 mode */ - - ocmode |= (chanmode << ATIM_CCMR1_OC1M_SHIFT); - - /* Enable CCR1/3/5 preload */ - - ocmode |= ATIM_CCMR1_OC1PE; - -#ifdef HAVE_IP_TIMERS_V2 - /* Reset current OC bit */ - - ccmr &= ~(ATIM_CCMR1_OC1M); - - /* Set an additional OC1/3/5M bit */ - - if (ocmbit) - { - ocmode |= ATIM_CCMR1_OC1M; - } -#endif - break; - } - - /* Configure channel 2/4/6 */ - - case STM32_PWM_CHAN2: - case STM32_PWM_CHAN4: -#ifdef HAVE_IP_TIMERS_V2 - case STM32_PWM_CHAN6: -#endif - { - /* Reset current channel 2/4/6 mode configuration */ - - ccmr &= ~(ATIM_CCMR1_CC2S_MASK | ATIM_CCMR1_OC2M_MASK | - ATIM_CCMR1_OC2PE); - - /* Configure CC2/4/6 as output */ - - ocmode |= (ATIM_CCMR_CCS_CCOUT << ATIM_CCMR1_CC2S_SHIFT); - - /* Configure Compare 2/4/6 mode */ - - ocmode |= (chanmode << ATIM_CCMR1_OC2M_SHIFT); - - /* Enable CCR2/4/6 preload */ - - ocmode |= ATIM_CCMR1_OC2PE; - -#ifdef HAVE_IP_TIMERS_V2 - /* Reset current OC bit */ - - ccmr &= ~(ATIM_CCMR1_OC2M); - - /* Set an additioneal OC2/4/6M bit */ - - if (ocmbit) - { - ocmode |= ATIM_CCMR1_OC2M; - } -#endif - break; - } - } - - /* Set the selected output compare mode */ - - ccmr |= ocmode; - - /* Write CCMRx registers */ - - pwm_putreg(priv, offset, ccmr); - -errout: - return ret; -} - -/**************************************************************************** - * Name: pwm_output_configure - * - * Description: - * Configure PWM output for given channel - * - ****************************************************************************/ - -static int pwm_output_configure(struct stm32_pwmtimer_s *priv, - struct stm32_pwmchan_s *chan) -{ - uint32_t cr2 = 0; - uint32_t ccer = 0; - uint8_t channel = 0; - - /* Get channel */ - - channel = chan->channel; - - /* Get current registers state */ - - cr2 = pwm_getreg(priv, STM32_GTIM_CR2_OFFSET); - ccer = pwm_getreg(priv, STM32_GTIM_CCER_OFFSET); - - /* | OISx/OISxN | IDLE | for ADVANCED and COUNTUP16 | CR2 register - * | CCxP/CCxNP | POL | all PWM timers | CCER register - */ - - /* Configure output polarity (all PWM timers) */ - - if (chan->out1.pol == STM32_POL_NEG) - { - ccer |= (GTIM_CCER_CC1P << ((channel - 1) * 4)); - } - else - { - ccer &= ~(GTIM_CCER_CC1P << ((channel - 1) * 4)); - } - -#ifdef HAVE_ADVTIM - if (priv->timtype == TIMTYPE_ADVANCED || - priv->timtype == TIMTYPE_COUNTUP16_N) - { - /* Configure output IDLE State */ - - if (chan->out1.idle == STM32_IDLE_ACTIVE) - { - cr2 |= (ATIM_CR2_OIS1 << ((channel - 1) * 2)); - } - else - { - cr2 &= ~(ATIM_CR2_OIS1 << ((channel - 1) * 2)); - } - -#ifdef HAVE_PWM_COMPLEMENTARY - /* Configure complementary output IDLE state */ - - if (chan->out2.idle == STM32_IDLE_ACTIVE) - { - cr2 |= (ATIM_CR2_OIS1N << ((channel - 1) * 2)); - } - else - { - cr2 &= ~(ATIM_CR2_OIS1N << ((channel - 1) * 2)); - } - - /* Configure complementary output polarity */ - - if (chan->out2.pol == STM32_POL_NEG) - { - ccer |= (ATIM_CCER_CC1NP << ((channel - 1) * 4)); - } - else - { - ccer &= ~(ATIM_CCER_CC1NP << ((channel - 1) * 4)); - } -#endif /* HAVE_PWM_COMPLEMENTARY */ - -#ifdef HAVE_IP_TIMERS_V2 - /* TODO: OIS5 and OIS6 */ - - cr2 &= ~(ATIM_CR2_OIS5 | ATIM_CR2_OIS6); - - /* TODO: CC5P and CC6P */ - - ccer &= ~(ATIM_CCER_CC5P | ATIM_CCER_CC6P); -#endif /* HAVE_IP_TIMERS_V2 */ - } -#ifdef HAVE_GTIM_CCXNP - else -#endif /* HAVE_GTIM_CCXNP */ -#endif /* HAVE_ADVTIM */ -#ifdef HAVE_GTIM_CCXNP - { - /* CCxNP must be cleared if not ADVANCED timer. - * - * REVISIT: not all families have CCxNP bits for GTIM, - * which causes an ugly condition above - */ - - ccer &= ~(GTIM_CCER_CC1NP << ((channel - 1) * 4)); - } -#endif /* HAVE_GTIM_CCXNP */ - - /* Write registers */ - - pwm_modifyreg(priv, STM32_GTIM_CR2_OFFSET, 0, cr2); - pwm_modifyreg(priv, STM32_GTIM_CCER_OFFSET, 0, ccer); - - return OK; -} - -/**************************************************************************** - * Name: pwm_outputs_enable - * - * Description: - * Enable/disable given timer PWM outputs. - * - * NOTE: This is bulk operation - we can enable/disable many outputs - * at one time - * - * Input Parameters: - * dev - A reference to the lower half PWM driver state structure - * outputs - outputs to set (look at enum stm32_chan_e in stm32_pwm.h) - * state - Enable/disable operation - * - ****************************************************************************/ - -static int pwm_outputs_enable(struct pwm_lowerhalf_s *dev, - uint16_t outputs, bool state) -{ - struct stm32_pwmtimer_s *priv = (struct stm32_pwmtimer_s *)dev; - uint32_t ccer = 0; - uint32_t regval = 0; - - /* Get current register state */ - - ccer = pwm_getreg(priv, STM32_GTIM_CCER_OFFSET); - - /* Get outputs configuration */ - - regval |= ((outputs & STM32_PWM_OUT1) ? GTIM_CCER_CC1E : 0); - regval |= ((outputs & STM32_PWM_OUT1N) ? ATIM_CCER_CC1NE : 0); - regval |= ((outputs & STM32_PWM_OUT2) ? GTIM_CCER_CC2E : 0); - regval |= ((outputs & STM32_PWM_OUT2N) ? ATIM_CCER_CC2NE : 0); - regval |= ((outputs & STM32_PWM_OUT3) ? GTIM_CCER_CC3E : 0); - regval |= ((outputs & STM32_PWM_OUT3N) ? ATIM_CCER_CC3NE : 0); - regval |= ((outputs & STM32_PWM_OUT4) ? GTIM_CCER_CC4E : 0); - - /* NOTE: CC4N doesn't exist, but some docs show configuration bits for it */ - -#ifdef HAVE_IP_TIMERS_V2 - regval |= ((outputs & STM32_PWM_OUT5) ? ATIM_CCER_CC5E : 0); - regval |= ((outputs & STM32_PWM_OUT6) ? ATIM_CCER_CC6E : 0); -#endif - - if (state == true) - { - /* Enable outputs - set bits */ - - ccer |= regval; - } - else - { - /* Disable outputs - reset bits */ - - ccer &= ~regval; - } - - /* Write register */ - - pwm_putreg(priv, STM32_GTIM_CCER_OFFSET, ccer); - - return OK; -} - -#if defined(HAVE_PWM_COMPLEMENTARY) && defined(CONFIG_STM32_PWM_LL_OPS) - -/**************************************************************************** - * Name: pwm_deadtime_update - ****************************************************************************/ - -static int pwm_deadtime_update(struct pwm_lowerhalf_s *dev, uint8_t dt) -{ - struct stm32_pwmtimer_s *priv = (struct stm32_pwmtimer_s *)dev; - uint32_t bdtr = 0; - int ret = OK; - - /* Check if locked */ - - if (priv->lock > 0) - { - ret = -EACCES; - goto errout; - } - - /* Get current register state */ - - bdtr = pwm_getreg(priv, STM32_ATIM_BDTR_OFFSET); - - /* TODO: check if BDTR not locked */ - - /* Update deadtime */ - - bdtr &= ~(ATIM_BDTR_DTG_MASK); - bdtr |= (dt << ATIM_BDTR_DTG_SHIFT); - - /* Write BDTR register */ - - pwm_putreg(priv, STM32_ATIM_BDTR_OFFSET, bdtr); - -errout: - return ret; -} -#endif - -#ifdef HAVE_TRGO -/**************************************************************************** - * Name: pwm_trgo_configure - * - * Description: - * Configure an output synchronisation event for PWM timer (TRGO/TRGO2) - * - ****************************************************************************/ - -static int pwm_trgo_configure(struct pwm_lowerhalf_s *dev, - uint8_t trgo) -{ - struct stm32_pwmtimer_s *priv = (struct stm32_pwmtimer_s *)dev; - uint32_t cr2 = 0; - - /* Configure TRGO (4 LSB in trgo) */ - - cr2 |= (((trgo >> 0) & 0x0f) << ATIM_CR2_MMS_SHIFT) & ATIM_CR2_MMS_MASK; - -#ifdef HAVE_IP_TIMERS_V2 - /* Configure TRGO2 (4 MSB in trgo) */ - - cr2 |= (((trgo >> 4) & 0x0f) << ATIM_CR2_MMS2_SHIFT) & ATIM_CR2_MMS2_MASK; -#endif - - /* Write register */ - - pwm_modifyreg(priv, STM32_GTIM_CR2_OFFSET, 0, cr2); - - return OK; -} -#endif - -/**************************************************************************** - * Name: pwm_soft_update - * - * Description: - * Generate an software update event - * - ****************************************************************************/ - -static int pwm_soft_update(struct pwm_lowerhalf_s *dev) -{ - struct stm32_pwmtimer_s *priv = (struct stm32_pwmtimer_s *)dev; - - pwm_putreg(priv, STM32_GTIM_EGR_OFFSET, GTIM_EGR_UG); - - return OK; -} - -/**************************************************************************** - * Name: pwm_soft_break - * - * Description: - * Generate an software break event - * - * Outputs are enabled if state is false. - * Outputs are disabled if state is true. - * - * NOTE: only timers with complementary outputs have BDTR register and - * support software break. - * - ****************************************************************************/ - -static int pwm_soft_break(struct pwm_lowerhalf_s *dev, bool state) -{ - struct stm32_pwmtimer_s *priv = (struct stm32_pwmtimer_s *)dev; - - if (state == true) - { - /* Reset MOE bit */ - - pwm_modifyreg(priv, STM32_ATIM_BDTR_OFFSET, ATIM_BDTR_MOE, 0); - } - else - { - /* Set MOE bit */ - - pwm_modifyreg(priv, STM32_ATIM_BDTR_OFFSET, 0, ATIM_BDTR_MOE); - } - - return OK; -} - -/**************************************************************************** - * Name: pwm_outputs_from_channels - * - * Description: - * Get enabled outputs configuration from the PWM timer state - * - ****************************************************************************/ - -static uint16_t pwm_outputs_from_channels(struct stm32_pwmtimer_s *priv) -{ - uint16_t outputs = 0; - uint8_t channel = 0; - uint8_t i = 0; - - for (i = 0; i < priv->chan_num; i += 1) - { - /* Get channel */ - - channel = priv->channels[i].channel; - - /* Set outputs if channel configured */ - - if (channel != 0) - { - /* Enable output if configured */ - - if (priv->channels[i].out1.in_use == 1) - { - outputs |= (STM32_PWM_OUT1 << ((channel - 1) * 2)); - } - -#ifdef HAVE_PWM_COMPLEMENTARY - /* Enable complementary output if configured */ - - if (priv->channels[i].out2.in_use == 1) - { - outputs |= (STM32_PWM_OUT1N << ((channel - 1) * 2)); - } -#endif - } - } - - return outputs; -} - -#ifdef HAVE_ADVTIM - -/**************************************************************************** - * Name: pwm_break_dt_configure - * - * Description: - * Configure break and deadtime - * - * NOTE: we have to configure all BDTR registers at once due to possible - * lock configuration - * - ****************************************************************************/ - -static int pwm_break_dt_configure(struct stm32_pwmtimer_s *priv) -{ - uint32_t bdtr = 0; - - /* Set the clock division to zero for all (but the basic timers, but there - * should be no basic timers in this context - */ - - pwm_modifyreg(priv, STM32_GTIM_CR1_OFFSET, GTIM_CR1_CKD_MASK, - priv->t_dts << GTIM_CR1_CKD_SHIFT); - -#ifdef HAVE_PWM_COMPLEMENTARY - /* Initialize deadtime */ - - bdtr |= (priv->deadtime << ATIM_BDTR_DTG_SHIFT); -#endif - -#ifdef HAVE_BREAK - /* Configure Break 1 */ - - if (priv->brk.en1 == 1) - { - /* Enable Break 1 */ - - bdtr |= ATIM_BDTR_BKE; - - /* Set Break 1 polarity */ - - bdtr |= (priv->brk.pol1 == STM32_POL_NEG ? ATIM_BDTR_BKP : 0); - } - -#ifdef HAVE_IP_TIMERS_V2 - /* Configure Break 1 */ - - if (priv->brk.en2 == 1) - { - /* Enable Break 2 */ - - bdtr |= ATIM_BDTR_BK2E; - - /* Set Break 2 polarity */ - - bdtr |= (priv->brk.pol2 == STM32_POL_NEG ? ATIM_BDTR_BK2P : 0); - - /* Configure BRK2 filter */ - - bdtr |= (priv->brk.flt2 << ATIM_BDTR_BK2F_SHIFT); - } -#endif /* HAVE_IP_TIMERS_V2 */ -#endif /* HAVE_BREAK */ - - /* Clear the OSSI and OSSR bits in the BDTR register. - * - * REVISIT: this should be configurable - */ - - bdtr &= ~(ATIM_BDTR_OSSI | ATIM_BDTR_OSSR); - - /* Configure lock */ - - bdtr |= priv->lock << ATIM_BDTR_LOCK_SHIFT; - - /* Write BDTR register at once */ - - pwm_putreg(priv, STM32_ATIM_BDTR_OFFSET, bdtr); - - return OK; -} -#endif - -/**************************************************************************** - * Name: pwm_configure - * - * Description: - * Configure PWM timer in standard mode - * - ****************************************************************************/ - -static int pwm_configure(struct pwm_lowerhalf_s *dev) -{ - struct stm32_pwmtimer_s *priv = (struct stm32_pwmtimer_s *)dev; - uint16_t outputs = 0; - uint8_t j = 0; - int ret = OK; - - /* NOTE: leave timer counter disabled and all outputs disabled! */ - - /* Get configured outputs */ - - outputs = pwm_outputs_from_channels(priv); - - /* Disable outputs */ - - ret = pwm_outputs_enable(dev, outputs, false); - if (ret < 0) - { - goto errout; - } - - /* Disable the timer until we get it configured */ - - pwm_timer_enable(dev, false); - - /* Initial timer configuration */ - - ret = pwm_timer_configure(priv); - if (ret < 0) - { - goto errout; - } - - /* Some special setup for advanced timers */ - -#ifdef HAVE_ADVTIM - if (priv->timtype == TIMTYPE_ADVANCED || - priv->timtype == TIMTYPE_COUNTUP16_N) - { - /* Configure break and deadtime register */ - - ret = pwm_break_dt_configure(priv); - if (ret < 0) - { - goto errout; - } - -#ifdef HAVE_TRGO - /* Configure TRGO/TRGO2 */ - - ret = pwm_trgo_configure(dev, priv->trgo); - if (ret < 0) - { - goto errout; - } -#endif - } -#endif - - /* Configure timer channels */ - - for (j = 0; j < priv->chan_num; j++) - { - /* Skip channel if not in use */ - - if (priv->channels[j].channel != 0) - { - /* Update PWM mode */ - - ret = pwm_mode_configure(dev, priv->channels[j].channel, - priv->channels[j].mode); - if (ret < 0) - { - goto errout; - } - - /* PWM outputs configuration */ - - ret = pwm_output_configure(priv, &priv->channels[j]); - if (ret < 0) - { - goto errout; - } - } - } - - /* Disable software break at the end of the outputs configuration (enablei - * outputs). - * - * NOTE: Only timers with complementary outputs have BDTR register and - * support software break. - */ - - if (priv->timtype == TIMTYPE_ADVANCED || - priv->timtype == TIMTYPE_COUNTUP16_N) - { - ret = pwm_soft_break(dev, false); - if (ret < 0) - { - goto errout; - } - } - -errout: - return ret; -} - -/**************************************************************************** - * Name: pwm_duty_channels_update - * - * Description: - * Update duty cycle for given channels - * - ****************************************************************************/ - -static int pwm_duty_channels_update(struct pwm_lowerhalf_s *dev, - const struct pwm_info_s *info) -{ - struct stm32_pwmtimer_s *priv = (struct stm32_pwmtimer_s *)dev; - uint8_t channel = 0; - ub16_t duty = 0; - int ret = OK; - int i = 0; - int j = 0; - - for (i = 0; i < CONFIG_PWM_NCHANNELS; i++) - { - /* Break the loop if all following channels are not configured */ - - if (info->channels[i].channel == -1) - { - break; - } - - duty = info->channels[i].duty; - channel = info->channels[i].channel; - - /* A value of zero means to skip this channel */ - - if (channel != 0) - { - /* Find the channel */ - - for (j = 0; j < priv->chan_num; j++) - { - if (priv->channels[j].channel == channel) - { - break; - } - } - - /* Check range */ - - if (j >= priv->chan_num) - { - pwmerr("ERROR: No such channel: %u\n", channel); - ret = -EINVAL; - goto errout; - } - - /* Update duty cycle */ - - ret = pwm_duty_update(dev, channel, duty); - if (ret < 0) - { - goto errout; - } - } - } - -errout: - return OK; -} - -/**************************************************************************** - * Name: pwm_timer - * - * Description: - * (Re-)initialize the timer resources and start the pulsed output - * - * Input Parameters: - * dev - A reference to the lower half PWM driver state structure - * info - A reference to the characteristics of the pulsed output - * - * Returned Value: - * Zero on success; a negated errno value on failure - * - ****************************************************************************/ - -static int pwm_timer(struct pwm_lowerhalf_s *dev, - const struct pwm_info_s *info) -{ - struct stm32_pwmtimer_s *priv = (struct stm32_pwmtimer_s *)dev; - uint16_t outputs = 0; - int ret = OK; - - DEBUGASSERT(priv != NULL && info != NULL); - - pwminfo("TIM%u frequency: %" PRIu32 "\n", - priv->timid, info->frequency); - - DEBUGASSERT(info->frequency > 0); - - /* TODO: what if we have pwm running and we want disable some channels ? */ - - /* Set timer frequency */ - - ret = pwm_frequency_update(dev, info->frequency); - if (ret < 0) - { - goto errout; - } - - /* Channel specific configuration */ - - ret = pwm_duty_channels_update(dev, info); - if (ret < 0) - { - goto errout; - } - - /* Set the advanced timer's repetition counter */ - -#ifdef HAVE_ADVTIM - if (priv->timtype == TIMTYPE_ADVANCED || - priv->timtype == TIMTYPE_COUNTUP16_N) - { - /* If a non-zero repetition count has been selected, then set the - * repetition counter to the count-1 (pwm_start() has already - * assured us that the count value is within range). - */ - - /* Set the repetition counter to zero */ - - pwm_rcr_update(dev, 0); - - /* Generate an update event to reload the prescaler */ - - pwm_soft_update(dev); - } - else -#endif - { - /* Generate an update event to reload the prescaler (all timers) */ - - pwm_soft_update(dev); - } - - /* Get configured outputs */ - - outputs = pwm_outputs_from_channels(priv); - - /* Enable outputs */ - - ret = pwm_outputs_enable(dev, outputs, true); - if (ret < 0) - { - goto errout; - } - - /* Just enable the timer, leaving all interrupts disabled */ - - pwm_timer_enable(dev, true); - - pwm_dumpregs(dev, "After starting"); - -errout: - return ret; -} - -/**************************************************************************** - * Name: pwm_set_apb_clock - * - * Description: - * Enable or disable APB clock for the timer peripheral - * - * Input Parameters: - * priv - A reference to the PWM block status - * on - Enable clock if 'on' is 'true' and disable if 'false' - * - ****************************************************************************/ - -static int pwm_set_apb_clock(struct stm32_pwmtimer_s *priv, bool on) -{ - uint32_t en_bit = 0; - uint32_t regaddr = 0; - int ret = OK; - - pwminfo("timer %d clock enable: %d\n", priv->timid, on ? 1 : 0); - - /* Determine which timer to configure */ - - switch (priv->timid) - { -#ifdef CONFIG_STM32_TIM1_PWM - case 1: - { - regaddr = TIMRCCEN_TIM1; - en_bit = TIMEN_TIM1; - break; - } -#endif - -#ifdef CONFIG_STM32_TIM2_PWM - case 2: - { - regaddr = TIMRCCEN_TIM2; - en_bit = TIMEN_TIM2; - break; - } -#endif - -#ifdef CONFIG_STM32_TIM3_PWM - case 3: - { - regaddr = TIMRCCEN_TIM3; - en_bit = TIMEN_TIM3; - break; - } -#endif - -#ifdef CONFIG_STM32_TIM4_PWM - case 4: - { - regaddr = TIMRCCEN_TIM4; - en_bit = TIMEN_TIM4; - break; - } -#endif - -#ifdef CONFIG_STM32_TIM5_PWM - case 5: - { - regaddr = TIMRCCEN_TIM5; - en_bit = TIMEN_TIM5; - break; - } -#endif - -#ifdef CONFIG_STM32_TIM8_PWM - case 8: - { - regaddr = TIMRCCEN_TIM8; - en_bit = TIMEN_TIM8; - break; - } -#endif - -#ifdef CONFIG_STM32_TIM9_PWM - case 9: - { - regaddr = TIMRCCEN_TIM9; - en_bit = TIMEN_TIM9; - break; - } -#endif - -#ifdef CONFIG_STM32_TIM10_PWM - case 10: - { - regaddr = TIMRCCEN_TIM10; - en_bit = TIMEN_TIM10; - break; - } -#endif - -#ifdef CONFIG_STM32_TIM11_PWM - case 11: - { - regaddr = TIMRCCEN_TIM11; - en_bit = TIMEN_TIM11; - break; - } -#endif - -#ifdef CONFIG_STM32_TIM12_PWM - case 12: - { - regaddr = TIMRCCEN_TIM12; - en_bit = TIMEN_TIM12; - break; - } -#endif - -#ifdef CONFIG_STM32_TIM13_PWM - case 13: - { - regaddr = TIMRCCEN_TIM13; - en_bit = TIMEN_TIM13; - break; - } -#endif - -#ifdef CONFIG_STM32_TIM14_PWM - case 14: - { - regaddr = TIMRCCEN_TIM14; - en_bit = TIMEN_TIM14; - break; - } -#endif - -#ifdef CONFIG_STM32_TIM15_PWM - case 15: - { - regaddr = TIMRCCEN_TIM15; - en_bit = TIMEN_TIM15; - break; - } -#endif - -#ifdef CONFIG_STM32_TIM16_PWM - case 16: - { - regaddr = TIMRCCEN_TIM16; - en_bit = TIMEN_TIM16; - break; - } -#endif - -#ifdef CONFIG_STM32_TIM17_PWM - case 17: - { - regaddr = TIMRCCEN_TIM17; - en_bit = TIMEN_TIM17; - break; - } -#endif - - default: - { - pwmerr("ERROR: No such timer configured %d\n", priv->timid); - ret = -EINVAL; - goto errout; - } - } - - /* Enable/disable APB 1/2 clock for timer */ - - pwminfo("RCC_APBxENR base: %08" PRIx32 " bits: %04" PRIx32 "\n", - regaddr, en_bit); - - if (on) - { - modifyreg32(regaddr, 0, en_bit); - } - else - { - modifyreg32(regaddr, en_bit, 0); - } - -errout: - return ret; -} - -/**************************************************************************** - * Name: pwm_setup - * - * Description: - * This method is called when the driver is opened. The lower half driver - * should configure and initialize the device so that it is ready for use. - * It should not, however, output pulses until the start method is called. - * - * Input Parameters: - * dev - A reference to the lower half PWM driver state structure - * - * Returned Value: - * Zero on success; a negated errno value on failure - * - * Assumptions: - * APB1 or 2 clocking for the GPIOs has already been configured by the RCC - * logic at power up. - * - ****************************************************************************/ - -static int pwm_setup(struct pwm_lowerhalf_s *dev) -{ - struct stm32_pwmtimer_s *priv = (struct stm32_pwmtimer_s *)dev; - uint32_t pincfg = 0; - int ret = OK; - int i = 0; - - pwminfo("TIM%u\n", priv->timid); - - /* Enable APB1/2 clocking for timer. */ - - ret = pwm_set_apb_clock(priv, true); - if (ret < 0) - { - goto errout; - } - - pwm_dumpregs(dev, "Initially"); - - /* Configure the PWM output pins, but do not start the timer yet */ - - for (i = 0; i < priv->chan_num; i++) - { - if (priv->channels[i].out1.in_use == 1) - { - /* Do not configure the pin if pincfg is not specified. - * This prevents overwriting the PA0 configuration if the - * channel is used internally. - */ - - pincfg = priv->channels[i].out1.pincfg; - if (pincfg != 0) - { - pwminfo("pincfg: %08" PRIx32 "\n", pincfg); - - stm32_configgpio(pincfg); - pwm_dumpgpio(pincfg, "PWM setup"); - } - } - -#ifdef HAVE_PWM_COMPLEMENTARY - if (priv->channels[i].out2.in_use == 1) - { - pincfg = priv->channels[i].out2.pincfg; - - /* Do not configure the pin if pincfg is not specified. - * This prevents overwriting the PA0 configuration if the - * channel is used internally. - */ - - if (pincfg != 0) - { - pwminfo("pincfg: %08" PRIx32 "\n", pincfg); - - stm32_configgpio(pincfg); - pwm_dumpgpio(pincfg, "PWM setup"); - } - } -#endif - } - - /* Configure PWM timer with the selected configuration. - * - * NOTE: We configure PWM here during setup, but leave timer with disabled - * counter, disabled outputs, not configured frequency and duty cycle - */ - - { - ret = pwm_configure(dev); - } - - if (ret < 0) - { - pwmerr("failed to configure PWM %d\n", priv->timid); - ret = ERROR; - goto errout; - } - -errout: - return ret; -} - -/**************************************************************************** - * Name: pwm_shutdown - * - * Description: - * This method is called when the driver is closed. The lower half driver - * stop pulsed output, free any resources, disable the timer hardware, and - * put the system into the lowest possible power usage state - * - * Input Parameters: - * dev - A reference to the lower half PWM driver state structure - * - * Returned Value: - * Zero on success; a negated errno value on failure - * - ****************************************************************************/ - -static int pwm_shutdown(struct pwm_lowerhalf_s *dev) -{ - struct stm32_pwmtimer_s *priv = (struct stm32_pwmtimer_s *)dev; - uint32_t pincfg = 0; - int i = 0; - int ret = OK; - - pwminfo("TIM%u\n", priv->timid); - - /* Make sure that the output has been stopped */ - - pwm_stop(dev); - - /* Disable APB1/2 clocking for timer. */ - - ret = pwm_set_apb_clock(priv, false); - if (ret < 0) - { - goto errout; - } - - /* Then put the GPIO pins back to the default state */ - - for (i = 0; i < priv->chan_num; i++) - { - pincfg = priv->channels[i].out1.pincfg; - if (pincfg != 0) - { - pwminfo("pincfg: %08" PRIx32 "\n", pincfg); - - pincfg &= (GPIO_PORT_MASK | GPIO_PIN_MASK); - pincfg |= PINCFG_DEFAULT; - - stm32_configgpio(pincfg); - } - -#ifdef HAVE_PWM_COMPLEMENTARY - pincfg = priv->channels[i].out2.pincfg; - if (pincfg != 0) - { - pwminfo("pincfg: %08" PRIx32 "\n", pincfg); - - pincfg &= (GPIO_PORT_MASK | GPIO_PIN_MASK); - pincfg |= PINCFG_DEFAULT; - - stm32_configgpio(pincfg); - } -#endif - } - -errout: - return ret; -} - -/**************************************************************************** - * Name: pwm_start - * - * Description: - * (Re-)initialize the timer resources and start the pulsed output - * - * Input Parameters: - * dev - A reference to the lower half PWM driver state structure - * info - A reference to the characteristics of the pulsed output - * - * Returned Value: - * Zero on success; a negated errno value on failure - * - ****************************************************************************/ - -static int pwm_start(struct pwm_lowerhalf_s *dev, - const struct pwm_info_s *info) -{ - struct stm32_pwmtimer_s *priv = (struct stm32_pwmtimer_s *)dev; - int ret = OK; - - /* if frequency has not changed we just update duty */ - - if (info->frequency == priv->frequency) - { - int i; - - for (i = 0; ret == OK && i < CONFIG_PWM_NCHANNELS; i++) - { - /* Break the loop if all following channels are not configured */ - - if (info->channels[i].channel == -1) - { - break; - } - - /* Set output if channel configured */ - - if (info->channels[i].channel != 0) - { - ret = pwm_duty_update(dev, info->channels[i].channel, - info->channels[i].duty); - } - } - } - else - { - ret = pwm_timer(dev, info); - - /* Save current frequency */ - - if (ret == OK) - { - priv->frequency = info->frequency; - } - } - - return ret; -} - -/**************************************************************************** - * Name: pwm_stop - * - * Description: - * Stop the pulsed output and reset the timer resources - * - * Input Parameters: - * dev - A reference to the lower half PWM driver state structure - * - * Returned Value: - * Zero on success; a negated errno value on failure - * - * Assumptions: - * This function is called to stop the pulsed output at anytime. This - * method is also called from the timer interrupt handler when a repetition - * count expires... automatically stopping the timer. - * - ****************************************************************************/ - -static int pwm_stop(struct pwm_lowerhalf_s *dev) -{ - struct stm32_pwmtimer_s *priv = (struct stm32_pwmtimer_s *)dev; - irqstate_t flags = 0; - uint16_t outputs = 0; - int ret = OK; - - pwminfo("TIM%u\n", priv->timid); - - /* Disable interrupts momentary to stop any ongoing timer processing and - * to prevent any concurrent access to the reset register. - */ - - flags = enter_critical_section(); - - /* Stopped so frequency is zero */ - - priv->frequency = 0; - - /* Disable further interrupts and stop the timer */ - - pwm_putreg(priv, STM32_GTIM_DIER_OFFSET, 0); - pwm_putreg(priv, STM32_GTIM_SR_OFFSET, 0); - - /* Disable the timer and timer outputs */ - - pwm_timer_enable(dev, false); - outputs = pwm_outputs_from_channels(priv); - ret = pwm_outputs_enable(dev, outputs, false); - - /* Clear all channels */ - - pwm_putreg(priv, STM32_GTIM_CCR1_OFFSET, 0); - pwm_putreg(priv, STM32_GTIM_CCR2_OFFSET, 0); - pwm_putreg(priv, STM32_GTIM_CCR3_OFFSET, 0); - pwm_putreg(priv, STM32_GTIM_CCR4_OFFSET, 0); - - leave_critical_section(flags); - - pwm_dumpregs(dev, "After stop"); - - return ret; -} - -/**************************************************************************** - * Name: pwm_ioctl - * - * Description: - * Lower-half logic may support platform-specific ioctl commands - * - * Input Parameters: - * dev - A reference to the lower half PWM driver state structure - * cmd - The ioctl command - * arg - The argument accompanying the ioctl command - * - * Returned Value: - * Zero on success; a negated errno value on failure - * - ****************************************************************************/ - -static int pwm_ioctl(struct pwm_lowerhalf_s *dev, int cmd, - unsigned long arg) -{ -#ifdef CONFIG_DEBUG_PWM_INFO - struct stm32_pwmtimer_s *priv = (struct stm32_pwmtimer_s *)dev; - - /* There are no platform-specific ioctl commands */ - - pwminfo("TIM%u\n", priv->timid); -#endif - return -ENOTTY; -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_pwminitialize - * - * Description: - * Initialize one timer for use with the upper_level PWM driver. - * - * Input Parameters: - * timer - A number identifying the timer use. The number of valid timer - * IDs varies with the STM32 MCU and MCU family but is somewhere in - * the range of {1,..,17}. - * - * Returned Value: - * On success, a pointer to the STM32 lower half PWM driver is returned. - * NULL is returned on any failure. - * - ****************************************************************************/ - -struct pwm_lowerhalf_s *stm32_pwminitialize(int timer) -{ - struct stm32_pwmtimer_s *lower = NULL; - - pwminfo("TIM%u\n", timer); - - switch (timer) - { -#ifdef CONFIG_STM32_TIM1_PWM - case 1: - { - lower = &g_pwm1dev; - - /* Attach but disable the TIM1 update interrupt */ - - break; - } -#endif - -#ifdef CONFIG_STM32_TIM2_PWM - case 2: - { - lower = &g_pwm2dev; - break; - } -#endif - -#ifdef CONFIG_STM32_TIM3_PWM - case 3: - { - lower = &g_pwm3dev; - break; - } -#endif - -#ifdef CONFIG_STM32_TIM4_PWM - case 4: - { - lower = &g_pwm4dev; - break; - } -#endif - -#ifdef CONFIG_STM32_TIM5_PWM - case 5: - { - lower = &g_pwm5dev; - break; - } -#endif - -#ifdef CONFIG_STM32_TIM8_PWM - case 8: - { - lower = &g_pwm8dev; - - /* Attach but disable the TIM8 update interrupt */ - - break; - } -#endif - -#ifdef CONFIG_STM32_TIM9_PWM - case 9: - { - lower = &g_pwm9dev; - break; - } -#endif - -#ifdef CONFIG_STM32_TIM10_PWM - case 10: - { - lower = &g_pwm10dev; - break; - } - -#endif - -#ifdef CONFIG_STM32_TIM11_PWM - case 11: - { - lower = &g_pwm11dev; - break; - } -#endif - -#ifdef CONFIG_STM32_TIM12_PWM - case 12: - { - lower = &g_pwm12dev; - break; - } -#endif - -#ifdef CONFIG_STM32_TIM13_PWM - case 13: - { - lower = &g_pwm13dev; - break; - } -#endif - -#ifdef CONFIG_STM32_TIM14_PWM - case 14: - { - lower = &g_pwm14dev; - break; - } -#endif - -#ifdef CONFIG_STM32_TIM15_PWM - case 15: - { - lower = &g_pwm15dev; - break; - } -#endif - -#ifdef CONFIG_STM32_TIM16_PWM - case 16: - { - lower = &g_pwm16dev; - break; - } -#endif - -#ifdef CONFIG_STM32_TIM17_PWM - case 17: - { - lower = &g_pwm17dev; - break; - } -#endif - - default: - { - pwmerr("ERROR: No such timer configured %d\n", timer); - lower = NULL; - goto errout; - } - } - -errout: - return (struct pwm_lowerhalf_s *)lower; -} - -#endif /* CONFIG_STM32_PWM */ diff --git a/arch/arm/src/stm32/stm32_pwm.h b/arch/arm/src/stm32/stm32_pwm.h deleted file mode 100644 index f2f7191bcf077..0000000000000 --- a/arch/arm/src/stm32/stm32_pwm.h +++ /dev/null @@ -1,1178 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_pwm.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32_STM32_PWM_H -#define __ARCH_ARM_SRC_STM32_STM32_PWM_H - -/* The STM32 does not have dedicated PWM hardware. Rather, pulsed output - * control is a capability of the STM32 timers. The logic in this file - * implements the lower half of the standard, NuttX PWM interface using the - * STM32 timers. That interface is described in include/nuttx/timers/pwm.h. - */ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include "chip.h" - -#ifdef CONFIG_STM32_PWM -# include -# include "hardware/stm32_tim.h" -#endif - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -/* Timer devices may be used for different purposes. One special purpose is - * to generate modulated outputs for such things as motor control. - * If CONFIG_STM32_TIMn is defined then the CONFIG_STM32_TIMn_PWM must also - * be defined to indicate that timer "n" is intended to be used for pulsed - * output signal generation. - */ - -#ifndef CONFIG_STM32_TIM1 -# undef CONFIG_STM32_TIM1_PWM -#endif -#ifndef CONFIG_STM32_TIM2 -# undef CONFIG_STM32_TIM2_PWM -#endif -#ifndef CONFIG_STM32_TIM3 -# undef CONFIG_STM32_TIM3_PWM -#endif -#ifndef CONFIG_STM32_TIM4 -# undef CONFIG_STM32_TIM4_PWM -#endif -#ifndef CONFIG_STM32_TIM5 -# undef CONFIG_STM32_TIM5_PWM -#endif -#ifndef CONFIG_STM32_TIM8 -# undef CONFIG_STM32_TIM8_PWM -#endif -#ifndef CONFIG_STM32_TIM9 -# undef CONFIG_STM32_TIM9_PWM -#endif -#ifndef CONFIG_STM32_TIM10 -# undef CONFIG_STM32_TIM10_PWM -#endif -#ifndef CONFIG_STM32_TIM11 -# undef CONFIG_STM32_TIM11_PWM -#endif -#ifndef CONFIG_STM32_TIM12 -# undef CONFIG_STM32_TIM12_PWM -#endif -#ifndef CONFIG_STM32_TIM13 -# undef CONFIG_STM32_TIM13_PWM -#endif -#ifndef CONFIG_STM32_TIM14 -# undef CONFIG_STM32_TIM14_PWM -#endif -#ifndef CONFIG_STM32_TIM15 -# undef CONFIG_STM32_TIM15_PWM -#endif -#ifndef CONFIG_STM32_TIM16 -# undef CONFIG_STM32_TIM16_PWM -#endif -#ifndef CONFIG_STM32_TIM17 -# undef CONFIG_STM32_TIM17_PWM -#endif - -/* The basic timers (timer 6 and 7) are not capable of generating output - * pulses - */ - -#undef CONFIG_STM32_TIM6_PWM -#undef CONFIG_STM32_TIM7_PWM - -/* Check if PWM support for any channel is enabled. */ - -#ifdef CONFIG_STM32_PWM - -/* PWM driver channels configuration */ - -#ifdef CONFIG_STM32_PWM_MULTICHAN - -#ifdef CONFIG_STM32_TIM1_CHANNEL1 -# define PWM_TIM1_CHANNEL1 1 -#else -# define PWM_TIM1_CHANNEL1 0 -#endif -#ifdef CONFIG_STM32_TIM1_CHANNEL2 -# define PWM_TIM1_CHANNEL2 1 -#else -# define PWM_TIM1_CHANNEL2 0 -#endif -#ifdef CONFIG_STM32_TIM1_CHANNEL3 -# define PWM_TIM1_CHANNEL3 1 -#else -# define PWM_TIM1_CHANNEL3 0 -#endif -#ifdef CONFIG_STM32_TIM1_CHANNEL4 -# define PWM_TIM1_CHANNEL4 1 -#else -# define PWM_TIM1_CHANNEL4 0 -#endif -#ifdef CONFIG_STM32_TIM1_CHANNEL5 -# define PWM_TIM1_CHANNEL5 1 -#else -# define PWM_TIM1_CHANNEL5 0 -#endif -#ifdef CONFIG_STM32_TIM1_CHANNEL6 -# define PWM_TIM1_CHANNEL6 1 -#else -# define PWM_TIM1_CHANNEL6 0 -#endif -#define PWM_TIM1_NCHANNELS (PWM_TIM1_CHANNEL1 + PWM_TIM1_CHANNEL2 + \ - PWM_TIM1_CHANNEL3 + PWM_TIM1_CHANNEL4 + \ - PWM_TIM1_CHANNEL5 + PWM_TIM1_CHANNEL6) - -#ifdef CONFIG_STM32_TIM2_CHANNEL1 -# define PWM_TIM2_CHANNEL1 1 -#else -# define PWM_TIM2_CHANNEL1 0 -#endif -#ifdef CONFIG_STM32_TIM2_CHANNEL2 -# define PWM_TIM2_CHANNEL2 1 -#else -# define PWM_TIM2_CHANNEL2 0 -#endif -#ifdef CONFIG_STM32_TIM2_CHANNEL3 -# define PWM_TIM2_CHANNEL3 1 -#else -# define PWM_TIM2_CHANNEL3 0 -#endif -#ifdef CONFIG_STM32_TIM2_CHANNEL4 -# define PWM_TIM2_CHANNEL4 1 -#else -# define PWM_TIM2_CHANNEL4 0 -#endif -#define PWM_TIM2_NCHANNELS (PWM_TIM2_CHANNEL1 + PWM_TIM2_CHANNEL2 + \ - PWM_TIM2_CHANNEL3 + PWM_TIM2_CHANNEL4) - -#ifdef CONFIG_STM32_TIM3_CHANNEL1 -# define PWM_TIM3_CHANNEL1 1 -#else -# define PWM_TIM3_CHANNEL1 0 -#endif -#ifdef CONFIG_STM32_TIM3_CHANNEL2 -# define PWM_TIM3_CHANNEL2 1 -#else -# define PWM_TIM3_CHANNEL2 0 -#endif -#ifdef CONFIG_STM32_TIM3_CHANNEL3 -# define PWM_TIM3_CHANNEL3 1 -#else -# define PWM_TIM3_CHANNEL3 0 -#endif -#ifdef CONFIG_STM32_TIM3_CHANNEL4 -# define PWM_TIM3_CHANNEL4 1 -#else -# define PWM_TIM3_CHANNEL4 0 -#endif -#define PWM_TIM3_NCHANNELS (PWM_TIM3_CHANNEL1 + PWM_TIM3_CHANNEL2 + \ - PWM_TIM3_CHANNEL3 + PWM_TIM3_CHANNEL4) - -#ifdef CONFIG_STM32_TIM4_CHANNEL1 -# define PWM_TIM4_CHANNEL1 1 -#else -# define PWM_TIM4_CHANNEL1 0 -#endif -#ifdef CONFIG_STM32_TIM4_CHANNEL2 -# define PWM_TIM4_CHANNEL2 1 -#else -# define PWM_TIM4_CHANNEL2 0 -#endif -#ifdef CONFIG_STM32_TIM4_CHANNEL3 -# define PWM_TIM4_CHANNEL3 1 -#else -# define PWM_TIM4_CHANNEL3 0 -#endif -#ifdef CONFIG_STM32_TIM4_CHANNEL4 -# define PWM_TIM4_CHANNEL4 1 -#else -# define PWM_TIM4_CHANNEL4 0 -#endif -#define PWM_TIM4_NCHANNELS (PWM_TIM4_CHANNEL1 + PWM_TIM4_CHANNEL2 + \ - PWM_TIM4_CHANNEL3 + PWM_TIM4_CHANNEL4) - -#ifdef CONFIG_STM32_TIM5_CHANNEL1 -# define PWM_TIM5_CHANNEL1 1 -#else -# define PWM_TIM5_CHANNEL1 0 -#endif -#ifdef CONFIG_STM32_TIM5_CHANNEL2 -# define PWM_TIM5_CHANNEL2 1 -#else -# define PWM_TIM5_CHANNEL2 0 -#endif -#ifdef CONFIG_STM32_TIM5_CHANNEL3 -# define PWM_TIM5_CHANNEL3 1 -#else -# define PWM_TIM5_CHANNEL3 0 -#endif -#ifdef CONFIG_STM32_TIM5_CHANNEL4 -# define PWM_TIM5_CHANNEL4 1 -#else -# define PWM_TIM5_CHANNEL4 0 -#endif -#define PWM_TIM5_NCHANNELS (PWM_TIM5_CHANNEL1 + PWM_TIM5_CHANNEL2 + \ - PWM_TIM5_CHANNEL3 + PWM_TIM5_CHANNEL4) - -#ifdef CONFIG_STM32_TIM8_CHANNEL1 -# define PWM_TIM8_CHANNEL1 1 -#else -# define PWM_TIM8_CHANNEL1 0 -#endif -#ifdef CONFIG_STM32_TIM8_CHANNEL2 -# define PWM_TIM8_CHANNEL2 1 -#else -# define PWM_TIM8_CHANNEL2 0 -#endif -#ifdef CONFIG_STM32_TIM8_CHANNEL3 -# define PWM_TIM8_CHANNEL3 1 -#else -# define PWM_TIM8_CHANNEL3 0 -#endif -#ifdef CONFIG_STM32_TIM8_CHANNEL4 -# define PWM_TIM8_CHANNEL4 1 -#else -# define PWM_TIM8_CHANNEL4 0 -#endif -#ifdef CONFIG_STM32_TIM8_CHANNEL5 -# define PWM_TIM8_CHANNEL5 1 -#else -# define PWM_TIM8_CHANNEL5 0 -#endif -#ifdef CONFIG_STM32_TIM8_CHANNEL6 -# define PWM_TIM8_CHANNEL6 1 -#else -# define PWM_TIM8_CHANNEL6 0 -#endif -#define PWM_TIM8_NCHANNELS (PWM_TIM8_CHANNEL1 + PWM_TIM8_CHANNEL2 + \ - PWM_TIM8_CHANNEL3 + PWM_TIM8_CHANNEL4 + \ - PWM_TIM8_CHANNEL5 + PWM_TIM8_CHANNEL6) - -#ifdef CONFIG_STM32_TIM9_CHANNEL1 -# define PWM_TIM9_CHANNEL1 1 -#else -# define PWM_TIM9_CHANNEL1 0 -#endif -#ifdef CONFIG_STM32_TIM9_CHANNEL2 -# define PWM_TIM9_CHANNEL2 1 -#else -# define PWM_TIM9_CHANNEL2 0 -#endif -#define PWM_TIM9_NCHANNELS (PWM_TIM9_CHANNEL1 + PWM_TIM9_CHANNEL2) - -#ifdef CONFIG_STM32_TIM10_CHANNEL1 -# define PWM_TIM10_CHANNEL1 1 -#else -# define PWM_TIM10_CHANNEL1 0 -#endif -#define PWM_TIM10_NCHANNELS (PWM_TIM10_CHANNEL1) - -#ifdef CONFIG_STM32_TIM11_CHANNEL1 -# define PWM_TIM11_CHANNEL1 1 -#else -# define PWM_TIM11_CHANNEL1 0 -#endif -#define PWM_TIM11_NCHANNELS (PWM_TIM11_CHANNEL1) - -#ifdef CONFIG_STM32_TIM12_CHANNEL1 -# define PWM_TIM12_CHANNEL1 1 -#else -# define PWM_TIM12_CHANNEL1 0 -#endif -#ifdef CONFIG_STM32_TIM12_CHANNEL2 -# define PWM_TIM12_CHANNEL2 1 -#else -# define PWM_TIM12_CHANNEL2 0 -#endif -#define PWM_TIM12_NCHANNELS (PWM_TIM12_CHANNEL1 + PWM_TIM12_CHANNEL2) - -#ifdef CONFIG_STM32_TIM13_CHANNEL1 -# define PWM_TIM13_CHANNEL1 1 -#else -# define PWM_TIM13_CHANNEL1 0 -#endif -#define PWM_TIM13_NCHANNELS (PWM_TIM13_CHANNEL1) - -#ifdef CONFIG_STM32_TIM14_CHANNEL1 -# define PWM_TIM14_CHANNEL1 1 -#else -# define PWM_TIM14_CHANNEL1 0 -#endif -#define PWM_TIM14_NCHANNELS (PWM_TIM14_CHANNEL1) - -#ifdef CONFIG_STM32_TIM15_CHANNEL1 -# define PWM_TIM15_CHANNEL1 1 -#else -# define PWM_TIM15_CHANNEL1 0 -#endif -#ifdef CONFIG_STM32_TIM15_CHANNEL2 -# define PWM_TIM15_CHANNEL2 1 -#else -# define PWM_TIM15_CHANNEL2 0 -#endif -#define PWM_TIM15_NCHANNELS (PWM_TIM15_CHANNEL1 + PWM_TIM15_CHANNEL2) - -#ifdef CONFIG_STM32_TIM16_CHANNEL1 -# define PWM_TIM16_CHANNEL1 1 -#else -# define PWM_TIM16_CHANNEL1 0 -#endif -#define PWM_TIM16_NCHANNELS PWM_TIM16_CHANNEL1 - -#ifdef CONFIG_STM32_TIM17_CHANNEL1 -# define PWM_TIM17_CHANNEL1 1 -#else -# define PWM_TIM17_CHANNEL1 0 -#endif -#define PWM_TIM17_NCHANNELS PWM_TIM17_CHANNEL1 - -#else /* !CONFIG_STM32_PWM_MULTICHAN */ - -/* For each timer that is enabled for PWM usage, we need the following - * additional configuration settings: - * - * CONFIG_STM32_TIMx_CHANNEL - Specifies the timer output channel {1,..,4} - * PWM_TIMx_CHn - One of the values defined in chip/stm32*_pinmap.h. In the - * case where there are multiple pin selections, the correct setting must be - * provided in the arch/board/board.h file. - * - * NOTE: The STM32 timers are each capable of generating different signals on - * each of the four channels with different duty cycles. That capability is - * not supported by this driver: Only one output channel per timer. - */ - -#ifdef CONFIG_STM32_TIM1_PWM -# if !defined(CONFIG_STM32_TIM1_CHANNEL) -# error "CONFIG_STM32_TIM1_CHANNEL must be provided" -# elif CONFIG_STM32_TIM1_CHANNEL == 1 -# define CONFIG_STM32_TIM1_CHANNEL1 1 -# define CONFIG_STM32_TIM1_CH1MODE CONFIG_STM32_TIM1_CHMODE -# elif CONFIG_STM32_TIM1_CHANNEL == 2 -# define CONFIG_STM32_TIM1_CHANNEL2 1 -# define CONFIG_STM32_TIM1_CH2MODE CONFIG_STM32_TIM1_CHMODE -# elif CONFIG_STM32_TIM1_CHANNEL == 3 -# define CONFIG_STM32_TIM1_CHANNEL3 1 -# define CONFIG_STM32_TIM1_CH3MODE CONFIG_STM32_TIM1_CHMODE -# elif CONFIG_STM32_TIM1_CHANNEL == 4 -# define CONFIG_STM32_TIM1_CHANNEL4 1 -# define CONFIG_STM32_TIM1_CH4MODE CONFIG_STM32_TIM1_CHMODE -# else -# error "Unsupported value of CONFIG_STM32_TIM1_CHANNEL" -# endif -# define PWM_TIM1_NCHANNELS 1 -#endif - -#ifdef CONFIG_STM32_TIM2_PWM -# if !defined(CONFIG_STM32_TIM2_CHANNEL) -# error "CONFIG_STM32_TIM2_CHANNEL must be provided" -# elif CONFIG_STM32_TIM2_CHANNEL == 1 -# define CONFIG_STM32_TIM2_CHANNEL1 1 -# define CONFIG_STM32_TIM2_CH1MODE CONFIG_STM32_TIM2_CHMODE -# elif CONFIG_STM32_TIM2_CHANNEL == 2 -# define CONFIG_STM32_TIM2_CHANNEL2 1 -# define CONFIG_STM32_TIM2_CH2MODE CONFIG_STM32_TIM2_CHMODE -# elif CONFIG_STM32_TIM2_CHANNEL == 3 -# define CONFIG_STM32_TIM2_CHANNEL3 1 -# define CONFIG_STM32_TIM2_CH3MODE CONFIG_STM32_TIM2_CHMODE -# elif CONFIG_STM32_TIM2_CHANNEL == 4 -# define CONFIG_STM32_TIM2_CHANNEL4 1 -# define CONFIG_STM32_TIM2_CH4MODE CONFIG_STM32_TIM2_CHMODE -# else -# error "Unsupported value of CONFIG_STM32_TIM2_CHANNEL" -# endif -# define PWM_TIM2_NCHANNELS 1 -#endif - -#ifdef CONFIG_STM32_TIM3_PWM -# if !defined(CONFIG_STM32_TIM3_CHANNEL) -# error "CONFIG_STM32_TIM3_CHANNEL must be provided" -# elif CONFIG_STM32_TIM3_CHANNEL == 1 -# define CONFIG_STM32_TIM3_CHANNEL1 1 -# define CONFIG_STM32_TIM3_CH1MODE CONFIG_STM32_TIM3_CHMODE -# elif CONFIG_STM32_TIM3_CHANNEL == 2 -# define CONFIG_STM32_TIM3_CHANNEL2 1 -# define CONFIG_STM32_TIM3_CH2MODE CONFIG_STM32_TIM3_CHMODE -# elif CONFIG_STM32_TIM3_CHANNEL == 3 -# define CONFIG_STM32_TIM3_CHANNEL3 1 -# define CONFIG_STM32_TIM3_CH3MODE CONFIG_STM32_TIM3_CHMODE -# elif CONFIG_STM32_TIM3_CHANNEL == 4 -# define CONFIG_STM32_TIM3_CHANNEL4 1 -# define CONFIG_STM32_TIM3_CH4MODE CONFIG_STM32_TIM3_CHMODE -# else -# error "Unsupported value of CONFIG_STM32_TIM3_CHANNEL" -# endif -# define PWM_TIM3_NCHANNELS 1 -#endif - -#ifdef CONFIG_STM32_TIM4_PWM -# if !defined(CONFIG_STM32_TIM4_CHANNEL) -# error "CONFIG_STM32_TIM4_CHANNEL must be provided" -# elif CONFIG_STM32_TIM4_CHANNEL == 1 -# define CONFIG_STM32_TIM4_CHANNEL1 1 -# define CONFIG_STM32_TIM4_CH1MODE CONFIG_STM32_TIM4_CHMODE -# elif CONFIG_STM32_TIM4_CHANNEL == 2 -# define CONFIG_STM32_TIM4_CHANNEL2 1 -# define CONFIG_STM32_TIM4_CH2MODE CONFIG_STM32_TIM4_CHMODE -# elif CONFIG_STM32_TIM4_CHANNEL == 3 -# define CONFIG_STM32_TIM4_CHANNEL3 1 -# define CONFIG_STM32_TIM4_CH3MODE CONFIG_STM32_TIM4_CHMODE -# elif CONFIG_STM32_TIM4_CHANNEL == 4 -# define CONFIG_STM32_TIM4_CHANNEL4 1 -# define CONFIG_STM32_TIM4_CH4MODE CONFIG_STM32_TIM4_CHMODE -# else -# error "Unsupported value of CONFIG_STM32_TIM4_CHANNEL" -# endif -# define PWM_TIM4_NCHANNELS 1 -#endif - -#ifdef CONFIG_STM32_TIM5_PWM -# if !defined(CONFIG_STM32_TIM5_CHANNEL) -# error "CONFIG_STM32_TIM5_CHANNEL must be provided" -# elif CONFIG_STM32_TIM5_CHANNEL == 1 -# define CONFIG_STM32_TIM5_CHANNEL1 1 -# define CONFIG_STM32_TIM5_CH1MODE CONFIG_STM32_TIM5_CHMODE -# elif CONFIG_STM32_TIM5_CHANNEL == 2 -# define CONFIG_STM32_TIM5_CHANNEL2 1 -# define CONFIG_STM32_TIM5_CH2MODE CONFIG_STM32_TIM5_CHMODE -# elif CONFIG_STM32_TIM5_CHANNEL == 3 -# define CONFIG_STM32_TIM5_CHANNEL3 1 -# define CONFIG_STM32_TIM5_CH3MODE CONFIG_STM32_TIM5_CHMODE -# elif CONFIG_STM32_TIM5_CHANNEL == 4 -# define CONFIG_STM32_TIM5_CHANNEL4 1 -# define CONFIG_STM32_TIM5_CH4MODE CONFIG_STM32_TIM5_CHMODE -# else -# error "Unsupported value of CONFIG_STM32_TIM5_CHANNEL" -# endif -# define PWM_TIM5_NCHANNELS 1 -#endif - -#ifdef CONFIG_STM32_TIM8_PWM -# if !defined(CONFIG_STM32_TIM8_CHANNEL) -# error "CONFIG_STM32_TIM8_CHANNEL must be provided" -# elif CONFIG_STM32_TIM8_CHANNEL == 1 -# define CONFIG_STM32_TIM8_CHANNEL1 1 -# define CONFIG_STM32_TIM8_CH1MODE CONFIG_STM32_TIM8_CHMODE -# elif CONFIG_STM32_TIM8_CHANNEL == 2 -# define CONFIG_STM32_TIM8_CHANNEL2 1 -# define CONFIG_STM32_TIM8_CH2MODE CONFIG_STM32_TIM8_CHMODE -# elif CONFIG_STM32_TIM8_CHANNEL == 3 -# define CONFIG_STM32_TIM8_CHANNEL3 1 -# define CONFIG_STM32_TIM8_CH3MODE CONFIG_STM32_TIM8_CHMODE -# elif CONFIG_STM32_TIM8_CHANNEL == 4 -# define CONFIG_STM32_TIM8_CHANNEL4 1 -# define CONFIG_STM32_TIM8_CH4MODE CONFIG_STM32_TIM8_CHMODE -# else -# error "Unsupported value of CONFIG_STM32_TIM8_CHANNEL" -# endif -# define PWM_TIM8_NCHANNELS 1 -#endif - -#ifdef CONFIG_STM32_TIM9_PWM -# if !defined(CONFIG_STM32_TIM9_CHANNEL) -# error "CONFIG_STM32_TIM9_CHANNEL must be provided" -# elif CONFIG_STM32_TIM9_CHANNEL == 1 -# define CONFIG_STM32_TIM9_CHANNEL1 1 -# define CONFIG_STM32_TIM9_CH1MODE CONFIG_STM32_TIM9_CHMODE -# elif CONFIG_STM32_TIM9_CHANNEL == 2 -# define CONFIG_STM32_TIM9_CHANNEL2 1 -# define CONFIG_STM32_TIM9_CH2MODE CONFIG_STM32_TIM9_CHMODE -# else -# error "Unsupported value of CONFIG_STM32_TIM9_CHANNEL" -# endif -# define PWM_TIM9_NCHANNELS 1 -#endif - -#ifdef CONFIG_STM32_TIM10_PWM -# if !defined(CONFIG_STM32_TIM10_CHANNEL) -# error "CONFIG_STM32_TIM10_CHANNEL must be provided" -# elif CONFIG_STM32_TIM10_CHANNEL == 1 -# define CONFIG_STM32_TIM10_CHANNEL1 1 -# define CONFIG_STM32_TIM10_CH1MODE CONFIG_STM32_TIM10_CHMODE -# else -# error "Unsupported value of CONFIG_STM32_TIM10_CHANNEL" -# endif -# define PWM_TIM10_NCHANNELS 1 -#endif - -#ifdef CONFIG_STM32_TIM11_PWM -# if !defined(CONFIG_STM32_TIM11_CHANNEL) -# error "CONFIG_STM32_TIM11_CHANNEL must be provided" -# elif CONFIG_STM32_TIM11_CHANNEL == 1 -# define CONFIG_STM32_TIM11_CHANNEL1 1 -# define CONFIG_STM32_TIM11_CH1MODE CONFIG_STM32_TIM11_CHMODE -# else -# error "Unsupported value of CONFIG_STM32_TIM11_CHANNEL" -# endif -# define PWM_TIM11_NCHANNELS 1 -#endif - -#ifdef CONFIG_STM32_TIM12_PWM -# if !defined(CONFIG_STM32_TIM12_CHANNEL) -# error "CONFIG_STM32_TIM12_CHANNEL must be provided" -# elif CONFIG_STM32_TIM12_CHANNEL == 1 -# define CONFIG_STM32_TIM12_CHANNEL1 1 -# define CONFIG_STM32_TIM12_CH1MODE CONFIG_STM32_TIM12_CHMODE -# elif CONFIG_STM32_TIM12_CHANNEL == 2 -# define CONFIG_STM32_TIM12_CHANNEL2 1 -# define CONFIG_STM32_TIM12_CH2MODE CONFIG_STM32_TIM12_CHMODE -# else -# error "Unsupported value of CONFIG_STM32_TIM12_CHANNEL" -# endif -# define PWM_TIM12_NCHANNELS 1 -#endif - -#ifdef CONFIG_STM32_TIM13_PWM -# if !defined(CONFIG_STM32_TIM13_CHANNEL) -# error "CONFIG_STM32_TIM13_CHANNEL must be provided" -# elif CONFIG_STM32_TIM13_CHANNEL == 1 -# define CONFIG_STM32_TIM13_CHANNEL1 1 -# define CONFIG_STM32_TIM13_CH1MODE CONFIG_STM32_TIM13_CHMODE -# else -# error "Unsupported value of CONFIG_STM32_TIM13_CHANNEL" -# endif -# define PWM_TIM13_NCHANNELS 1 -#endif - -#ifdef CONFIG_STM32_TIM14_PWM -# if !defined(CONFIG_STM32_TIM14_CHANNEL) -# error "CONFIG_STM32_TIM14_CHANNEL must be provided" -# elif CONFIG_STM32_TIM14_CHANNEL == 1 -# define CONFIG_STM32_TIM14_CHANNEL1 1 -# define CONFIG_STM32_TIM14_CH1MODE CONFIG_STM32_TIM14_CHMODE -# else -# error "Unsupported value of CONFIG_STM32_TIM14_CHANNEL" -# endif -# define PWM_TIM14_NCHANNELS 1 -#endif - -#ifdef CONFIG_STM32_TIM15_PWM -# if !defined(CONFIG_STM32_TIM15_CHANNEL) -# error "CONFIG_STM32_TIM15_CHANNEL must be provided" -# elif CONFIG_STM32_TIM15_CHANNEL == 1 -# define CONFIG_STM32_TIM15_CHANNEL1 1 -# define CONFIG_STM32_TIM15_CH1MODE CONFIG_STM32_TIM15_CHMODE -# elif CONFIG_STM32_TIM15_CHANNEL == 2 -# define CONFIG_STM32_TIM15_CHANNEL2 1 -# define CONFIG_STM32_TIM15_CH2MODE CONFIG_STM32_TIM15_CHMODE -# else -# error "Unsupported value of CONFIG_STM32_TIM15_CHANNEL" -# endif -# define PWM_TIM15_NCHANNELS 1 -#endif - -#ifdef CONFIG_STM32_TIM16_PWM -# if !defined(CONFIG_STM32_TIM16_CHANNEL) -# error "CONFIG_STM32_TIM16_CHANNEL must be provided" -# elif CONFIG_STM32_TIM16_CHANNEL == 1 -# define CONFIG_STM32_TIM16_CHANNEL1 1 -# define CONFIG_STM32_TIM16_CH1MODE CONFIG_STM32_TIM16_CHMODE -# else -# error "Unsupported value of CONFIG_STM32_TIM16_CHANNEL" -# endif -# define PWM_TIM16_NCHANNELS 1 -#endif - -#ifdef CONFIG_STM32_TIM17_PWM -# if !defined(CONFIG_STM32_TIM17_CHANNEL) -# error "CONFIG_STM32_TIM17_CHANNEL must be provided" -# elif CONFIG_STM32_TIM17_CHANNEL == 1 -# define CONFIG_STM32_TIM17_CHANNEL1 1 -# define CONFIG_STM32_TIM17_CH1MODE CONFIG_STM32_TIM17_CHMODE -# else -# error "Unsupported value of CONFIG_STM32_TIM17_CHANNEL" -# endif -# define PWM_TIM17_NCHANNELS 1 -#endif - -#endif /* CONFIG_STM32_PWM_MULTICHAN */ - -#ifdef CONFIG_STM32_TIM1_CH1OUT -# define PWM_TIM1_CH1CFG GPIO_TIM1_CH1OUT -#else -# define PWM_TIM1_CH1CFG 0 -#endif -#ifdef CONFIG_STM32_TIM1_CH1NOUT -# define PWM_TIM1_CH1NCFG GPIO_TIM1_CH1NOUT -#else -# define PWM_TIM1_CH1NCFG 0 -#endif -#ifdef CONFIG_STM32_TIM1_CH2OUT -# define PWM_TIM1_CH2CFG GPIO_TIM1_CH2OUT -#else -# define PWM_TIM1_CH2CFG 0 -#endif -#ifdef CONFIG_STM32_TIM1_CH2NOUT -# define PWM_TIM1_CH2NCFG GPIO_TIM1_CH2NOUT -#else -# define PWM_TIM1_CH2NCFG 0 -#endif -#ifdef CONFIG_STM32_TIM1_CH3OUT -# define PWM_TIM1_CH3CFG GPIO_TIM1_CH3OUT -#else -# define PWM_TIM1_CH3CFG 0 -#endif -#ifdef CONFIG_STM32_TIM1_CH3NOUT -# define PWM_TIM1_CH3NCFG GPIO_TIM1_CH3NOUT -#else -# define PWM_TIM1_CH3NCFG 0 -#endif -#ifdef CONFIG_STM32_TIM1_CH4OUT -# define PWM_TIM1_CH4CFG GPIO_TIM1_CH4OUT -#else -# define PWM_TIM1_CH4CFG 0 -#endif - -#ifdef CONFIG_STM32_TIM2_CH1OUT -# define PWM_TIM2_CH1CFG GPIO_TIM2_CH1OUT -#else -# define PWM_TIM2_CH1CFG 0 -#endif -#ifdef CONFIG_STM32_TIM2_CH2OUT -# define PWM_TIM2_CH2CFG GPIO_TIM2_CH2OUT -#else -# define PWM_TIM2_CH2CFG 0 -#endif -#ifdef CONFIG_STM32_TIM2_CH3OUT -# define PWM_TIM2_CH3CFG GPIO_TIM2_CH3OUT -#else -# define PWM_TIM2_CH3CFG 0 -#endif -#ifdef CONFIG_STM32_TIM2_CH4OUT -# define PWM_TIM2_CH4CFG GPIO_TIM2_CH4OUT -#else -# define PWM_TIM2_CH4CFG 0 -#endif - -#ifdef CONFIG_STM32_TIM3_CH1OUT -# define PWM_TIM3_CH1CFG GPIO_TIM3_CH1OUT -#else -# define PWM_TIM3_CH1CFG 0 -#endif -#ifdef CONFIG_STM32_TIM3_CH2OUT -# define PWM_TIM3_CH2CFG GPIO_TIM3_CH2OUT -#else -# define PWM_TIM3_CH2CFG 0 -#endif -#ifdef CONFIG_STM32_TIM3_CH3OUT -# define PWM_TIM3_CH3CFG GPIO_TIM3_CH3OUT -#else -# define PWM_TIM3_CH3CFG 0 -#endif -#ifdef CONFIG_STM32_TIM3_CH4OUT -# define PWM_TIM3_CH4CFG GPIO_TIM3_CH4OUT -#else -# define PWM_TIM3_CH4CFG 0 -#endif - -#ifdef CONFIG_STM32_TIM4_CH1OUT -# define PWM_TIM4_CH1CFG GPIO_TIM4_CH1OUT -#else -# define PWM_TIM4_CH1CFG 0 -#endif -#ifdef CONFIG_STM32_TIM4_CH2OUT -# define PWM_TIM4_CH2CFG GPIO_TIM4_CH2OUT -#else -# define PWM_TIM4_CH2CFG 0 -#endif -#ifdef CONFIG_STM32_TIM4_CH3OUT -# define PWM_TIM4_CH3CFG GPIO_TIM4_CH3OUT -#else -# define PWM_TIM4_CH3CFG 0 -#endif -#ifdef CONFIG_STM32_TIM4_CH4OUT -# define PWM_TIM4_CH4CFG GPIO_TIM4_CH4OUT -#else -# define PWM_TIM4_CH4CFG 0 -#endif - -#ifdef CONFIG_STM32_TIM5_CH1OUT -# define PWM_TIM5_CH1CFG GPIO_TIM5_CH1OUT -#else -# define PWM_TIM5_CH1CFG 0 -#endif -#ifdef CONFIG_STM32_TIM5_CH2OUT -# define PWM_TIM5_CH2CFG GPIO_TIM5_CH2OUT -#else -# define PWM_TIM5_CH2CFG 0 -#endif -#ifdef CONFIG_STM32_TIM5_CH3OUT -# define PWM_TIM5_CH3CFG GPIO_TIM5_CH3OUT -#else -# define PWM_TIM5_CH3CFG 0 -#endif -#ifdef CONFIG_STM32_TIM5_CH4OUT -# define PWM_TIM5_CH4CFG GPIO_TIM5_CH4OUT -#else -# define PWM_TIM5_CH4CFG 0 -#endif - -#ifdef CONFIG_STM32_TIM8_CH1OUT -# define PWM_TIM8_CH1CFG GPIO_TIM8_CH1OUT -#else -# define PWM_TIM8_CH1CFG 0 -#endif -#ifdef CONFIG_STM32_TIM8_CH1NOUT -# define PWM_TIM8_CH1NCFG GPIO_TIM8_CH1NOUT -#else -# define PWM_TIM8_CH1NCFG 0 -#endif -#ifdef CONFIG_STM32_TIM8_CH2OUT -# define PWM_TIM8_CH2CFG GPIO_TIM8_CH2OUT -#else -# define PWM_TIM8_CH2CFG 0 -#endif -#ifdef CONFIG_STM32_TIM8_CH2NOUT -# define PWM_TIM8_CH2NCFG GPIO_TIM8_CH2NOUT -#else -# define PWM_TIM8_CH2NCFG 0 -#endif -#ifdef CONFIG_STM32_TIM8_CH3OUT -# define PWM_TIM8_CH3CFG GPIO_TIM8_CH3OUT -#else -# define PWM_TIM8_CH3CFG 0 -#endif -#ifdef CONFIG_STM32_TIM8_CH3NOUT -# define PWM_TIM8_CH3NCFG GPIO_TIM8_CH3NOUT -#else -# define PWM_TIM8_CH3NCFG 0 -#endif -#ifdef CONFIG_STM32_TIM8_CH4OUT -# define PWM_TIM8_CH4CFG GPIO_TIM8_CH4OUT -#else -# define PWM_TIM8_CH4CFG 0 -#endif - -#ifdef CONFIG_STM32_TIM9_CH1OUT -# define PWM_TIM9_CH1CFG GPIO_TIM9_CH1OUT -#else -# define PWM_TIM9_CH1CFG 0 -#endif - -#ifdef CONFIG_STM32_TIM9_CH2OUT -# define PWM_TIM9_CH2CFG GPIO_TIM9_CH2OUT -#else -# define PWM_TIM9_CH2CFG 0 -#endif - -#ifdef CONFIG_STM32_TIM10_CH1OUT -# define PWM_TIM10_CH1CFG GPIO_TIM10_CH1OUT -#else -# define PWM_TIM10_CH1CFG 0 -#endif - -#ifdef CONFIG_STM32_TIM11_CH1OUT -# define PWM_TIM11_CH1CFG GPIO_TIM11_CH1OUT -#else -# define PWM_TIM11_CH1CFG 0 -#endif - -#ifdef CONFIG_STM32_TIM12_CH1OUT -# define PWM_TIM12_CH1CFG GPIO_TIM12_CH1OUT -#else -# define PWM_TIM12_CH1CFG 0 -#endif -#ifdef CONFIG_STM32_TIM12_CH2OUT -# define PWM_TIM12_CH2CFG GPIO_TIM12_CH2OUT -#else -# define PWM_TIM12_CH2CFG 0 -#endif - -#ifdef CONFIG_STM32_TIM13_CH1OUT -# define PWM_TIM13_CH1CFG GPIO_TIM13_CH1OUT -#else -# define PWM_TIM13_CH1CFG 0 -#endif - -#ifdef CONFIG_STM32_TIM14_CH1OUT -# define PWM_TIM14_CH1CFG GPIO_TIM14_CH1OUT -#else -# define PWM_TIM14_CH1CFG 0 -#endif - -#ifdef CONFIG_STM32_TIM15_CH1OUT -# define PWM_TIM15_CH1CFG GPIO_TIM15_CH1OUT -#else -# define PWM_TIM15_CH1CFG 0 -#endif - -#ifdef CONFIG_STM32_TIM15_CH1NOUT -# define PWM_TIM15_CH1NCFG GPIO_TIM15_CH1NOUT -#else -# define PWM_TIM15_CH1NCFG 0 -#endif -#ifdef CONFIG_STM32_TIM15_CH2OUT -# define PWM_TIM15_CH2CFG GPIO_TIM15_CH2OUT -#else -# define PWM_TIM15_CH2CFG 0 -#endif - -#ifdef CONFIG_STM32_TIM16_CH1OUT -# define PWM_TIM16_CH1CFG GPIO_TIM16_CH1OUT -#else -# define PWM_TIM16_CH1CFG 0 -#endif -#ifdef CONFIG_STM32_TIM16_CH1NOUT -# define PWM_TIM16_CH1NCFG GPIO_TIM16_CH1NOUT -#else -# define PWM_TIM16_CH1NCFG 0 -#endif - -#ifdef CONFIG_STM32_TIM17_CH1OUT -# define PWM_TIM17_CH1CFG GPIO_TIM17_CH1OUT -#else -# define PWM_TIM17_CH1CFG 0 -#endif -#ifdef CONFIG_STM32_TIM17_CH1NOUT -# define PWM_TIM17_CH1NCFG GPIO_TIM17_CH1NOUT -#else -# define PWM_TIM17_CH1NCFG 0 -#endif - -/* Complementary outputs support */ - -#if defined(CONFIG_STM32_TIM1_CH1NOUT) || defined(CONFIG_STM32_TIM1_CH2NOUT) || \ - defined(CONFIG_STM32_TIM1_CH3NOUT) -# define HAVE_TIM1_COMPLEMENTARY -#endif -#if defined(CONFIG_STM32_TIM8_CH1NOUT) || defined(CONFIG_STM32_TIM8_CH2NOUT) || \ - defined(CONFIG_STM32_TIM8_CH3NOUT) -# define HAVE_TIM8_COMPLEMENTARY -#endif -#if defined(CONFIG_STM32_TIM15_CH1NOUT) -# define HAVE_TIM15_COMPLEMENTARY -#endif -#if defined(CONFIG_STM32_TIM16_CH1NOUT) -# define HAVE_TIM16_COMPLEMENTARY -#endif -#if defined(CONFIG_STM32_TIM17_CH1NOUT) -# define HAVE_TIM17_COMPLEMENTARY -#endif -#if defined(HAVE_TIM1_COMPLEMENTARY) || defined(HAVE_TIM8_COMPLEMENTARY) || \ - defined(HAVE_TIM15_COMPLEMENTARY) || defined(HAVE_TIM16_COMPLEMENTARY) || \ - defined(HAVE_TIM17_COMPLEMENTARY) -# define HAVE_PWM_COMPLEMENTARY -#endif - -/* Low-level ops helpers ****************************************************/ - -#ifdef CONFIG_STM32_PWM_LL_OPS - -/* NOTE: - * low-level ops accept pwm_lowerhalf_s as first argument, but llops access - * can be found in stm32_pwm_dev_s - */ - -#define PWM_SETUP(dev) \ - (dev)->ops->setup((struct pwm_lowerhalf_s *)dev) -#define PWM_SHUTDOWN(dev) \ - (dev)->ops->shutdown((struct pwm_lowerhalf_s *)dev) -#define PWM_CCR_UPDATE(dev, index, ccr) \ - (dev)->llops->ccr_update((struct pwm_lowerhalf_s *)dev, index, ccr) -#define PWM_MODE_UPDATE(dev, index, mode) \ - (dev)->llops->mode_update((struct pwm_lowerhalf_s *)dev, index, mode) -#define PWM_CCR_GET(dev, index) \ - (dev)->llops->ccr_get((struct pwm_lowerhalf_s *)dev, index) -#define PWM_ARR_UPDATE(dev, arr) \ - (dev)->llops->arr_update((struct pwm_lowerhalf_s *)dev, arr) -#define PWM_ARR_GET(dev) \ - (dev)->llops->arr_get((struct pwm_lowerhalf_s *)dev) -#define PWM_RCR_UPDATE(dev, rcr) \ - (dev)->llops->rcr_update((struct pwm_lowerhalf_s *)dev, rcr) -#define PWM_RCR_GET(dev) \ - (dev)->llops->rcr_get((struct pwm_lowerhalf_s *)dev) -#ifdef CONFIG_STM32_PWM_TRGO -# define PWM_TRGO_SET(dev, trgo) \ - (dev)->llops->trgo_set((struct pwm_lowerhalf_s *)dev, trgo) -#endif -#define PWM_OUTPUTS_ENABLE(dev, out, state) \ - (dev)->llops->outputs_enable((struct pwm_lowerhalf_s *)dev, out, state) -#define PWM_SOFT_UPDATE(dev) \ - (dev)->llops->soft_update((struct pwm_lowerhalf_s *)dev) -#define PWM_CONFIGURE(dev) \ - (dev)->llops->configure((struct pwm_lowerhalf_s *)dev) -#define PWM_SOFT_BREAK(dev, state) \ - (dev)->llops->soft_break((struct pwm_lowerhalf_s *)dev, state) -#define PWM_FREQ_UPDATE(dev, freq) \ - (dev)->llops->freq_update((struct pwm_lowerhalf_s *)dev, freq) -#define PWM_TIM_ENABLE(dev, state) \ - (dev)->llops->tim_enable((struct pwm_lowerhalf_s *)dev, state) -#ifdef CONFIG_DEBUG_PWM_INFO -# define PWM_DUMP_REGS(dev, msg) \ - (dev)->llops->dump_regs((struct pwm_lowerhalf_s *)dev, msg) -#else -# define PWM_DUMP_REGS(dev, msg) -#endif -#define PWM_DT_UPDATE(dev, dt) \ - (dev)->llops->dt_update((struct pwm_lowerhalf_s *)dev, dt) -#endif - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -/* Timer mode */ - -enum stm32_pwm_tim_mode_e -{ - STM32_TIMMODE_COUNTUP = 0, - STM32_TIMMODE_COUNTDOWN = 1, - STM32_TIMMODE_CENTER1 = 2, - STM32_TIMMODE_CENTER2 = 3, - STM32_TIMMODE_CENTER3 = 4, -}; - -/* Timer output polarity */ - -enum stm32_pwm_pol_e -{ - STM32_POL_POS = 0, - STM32_POL_NEG = 1, -}; - -/* Timer output IDLE state */ - -enum stm32_pwm_idle_e -{ - STM32_IDLE_INACTIVE = 0, - STM32_IDLE_ACTIVE = 1 -}; - -/* PWM channel mode */ - -enum stm32_pwm_chanmode_e -{ - STM32_CHANMODE_FRZN = 0, /* CCRx matches has no effects on outputs */ - STM32_CHANMODE_CHACT = 1, /* OCxREF active on match */ - STM32_CHANMODE_CHINACT = 2, /* OCxREF inactive on match */ - STM32_CHANMODE_OCREFTOG = 3, /* OCxREF toggles when TIMy_CNT=TIMyCCRx */ - STM32_CHANMODE_OCREFLO = 4, /* OCxREF is forced low */ - STM32_CHANMODE_OCREFHI = 5, /* OCxREF is forced high */ - STM32_CHANMODE_PWM1 = 6, /* PWM mode 1 */ - STM32_CHANMODE_PWM2 = 7, /* PWM mode 2 */ -#ifdef HAVE_IP_TIMERS_V2 - STM32_CHANMODE_COMBINED1 = 8, /* Combined PWM mode 1 */ - STM32_CHANMODE_COMBINED2 = 9, /* Combined PWM mode 2 */ - STM32_CHANMODE_ASYMMETRIC1 = 10, /* Asymmetric PWM mode 1 */ - STM32_CHANMODE_ASYMMETRIC2 = 11, /* Asymmetric PWM mode 2 */ -#endif -}; - -/* PWM timer channel */ - -enum stm32_pwm_chan_e -{ - STM32_PWM_CHAN1 = 1, - STM32_PWM_CHAN2 = 2, - STM32_PWM_CHAN3 = 3, - STM32_PWM_CHAN4 = 4, -#ifdef HAVE_IP_TIMERS_V2 - STM32_PWM_CHAN5 = 5, - STM32_PWM_CHAN6 = 6, -#endif -}; - -/* PWM timer channel output */ - -enum stm32_pwm_output_e -{ - STM32_PWM_OUT1 = (1 << 0), - STM32_PWM_OUT1N = (1 << 1), - STM32_PWM_OUT2 = (1 << 2), - STM32_PWM_OUT2N = (1 << 3), - STM32_PWM_OUT3 = (1 << 4), - STM32_PWM_OUT3N = (1 << 5), - STM32_PWM_OUT4 = (1 << 6), - - /* 1 << 7 reserved - no complementary output for CH4 */ - -#ifdef HAVE_IP_TIMERS_V2 - /* Only available inside micro */ - - STM32_PWM_OUT5 = (1 << 8), - - /* 1 << 9 reserved - no complementary output for CH5 */ - - STM32_PWM_OUT6 = (1 << 10), - - /* 1 << 11 reserved - no complementary output for CH6 */ -#endif -}; - -#ifdef CONFIG_STM32_PWM_LL_OPS - -/* This structure provides the publicly visible representation of the - * "lower-half" PWM driver structure. - */ - -struct stm32_pwm_dev_s -{ - /* The first field of this state structure must be a pointer to the PWM - * callback structure to be consistent with upper-half PWM driver. - */ - - const struct pwm_ops_s *ops; - - /* Publicly visible portion of the "lower-half" PWM driver structure */ - - const struct stm32_pwm_ops_s *llops; - - /* Require cast-compatibility with private "lower-half" PWM structure */ -}; - -/* Low-level operations for PWM */ - -struct pwm_lowerhalf_s; -struct stm32_pwm_ops_s -{ - /* Update CCR register */ - - int (*ccr_update)(struct pwm_lowerhalf_s *dev, - uint8_t index, uint32_t ccr); - - /* Update PWM mode */ - - int (*mode_update)(struct pwm_lowerhalf_s *dev, - uint8_t index, uint32_t mode); - - /* Get CCR register */ - - uint32_t (*ccr_get)(struct pwm_lowerhalf_s *dev, uint8_t index); - - /* Update ARR register */ - - int (*arr_update)(struct pwm_lowerhalf_s *dev, uint32_t arr); - - /* Get ARR register */ - - uint32_t (*arr_get)(struct pwm_lowerhalf_s *dev); - - /* Update RCR register */ - - int (*rcr_update)(struct pwm_lowerhalf_s *dev, uint16_t rcr); - - /* Get RCR register */ - - uint16_t (*rcr_get)(struct pwm_lowerhalf_s *dev); - -#ifdef CONFIG_STM32_PWM_TRGO - /* Set TRGO/TRGO2 register */ - - int (*trgo_set)(struct pwm_lowerhalf_s *dev, uint8_t trgo); -#endif - - /* Enable outputs */ - - int (*outputs_enable)(struct pwm_lowerhalf_s *dev, uint16_t outputs, - bool state); - - /* Software update */ - - int (*soft_update)(struct pwm_lowerhalf_s *dev); - - /* PWM configure */ - - int (*configure)(struct pwm_lowerhalf_s *dev); - - /* Software break */ - - int (*soft_break)(struct pwm_lowerhalf_s *dev, bool state); - - /* Update frequency */ - - int (*freq_update)(struct pwm_lowerhalf_s *dev, uint32_t frequency); - - /* Enable timer counter */ - - int (*tim_enable)(struct pwm_lowerhalf_s *dev, bool state); - -#ifdef CONFIG_DEBUG_PWM_INFO - /* Dump timer registers */ - - void (*dump_regs)(struct pwm_lowerhalf_s *dev, const char *msg); -#endif - -#ifdef HAVE_PWM_COMPLEMENTARY - /* Deadtime update */ - - int (*dt_update)(struct pwm_lowerhalf_s *dev, uint8_t dt); -#endif -}; - -#endif /* CONFIG_STM32_PWM_LL_OPS */ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -#ifndef __ASSEMBLY__ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_pwminitialize - * - * Description: - * Initialize one timer for use with the upper_level PWM driver. - * - * Input Parameters: - * timer - A number identifying the timer use. The number of valid timer - * IDs varies with the STM32 MCU and MCU family but is somewhere in - * the range of {1,..,17}. - * - * Returned Value: - * On success, a pointer to the STM32 lower half PWM driver is returned. - * NULL is returned on any failure. - * - ****************************************************************************/ - -struct pwm_lowerhalf_s *stm32_pwminitialize(int timer); - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ -#endif /* CONFIG_STM32_PWM */ -#endif /* __ARCH_ARM_SRC_STM32_STM32_PWM_H */ diff --git a/arch/arm/src/stm32/stm32_pwr.c b/arch/arm/src/stm32/stm32_pwr.c deleted file mode 100644 index b55c301cd3622..0000000000000 --- a/arch/arm/src/stm32/stm32_pwr.c +++ /dev/null @@ -1,481 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_pwr.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include - -#include -#include - -#include "arm_internal.h" -#include "stm32_pwr.h" - -#if defined(CONFIG_STM32_PWR) - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* Wakeup Pin Definitions: See chip/stm32_pwr.h */ - -#undef HAVE_PWR_WKUP2 -#undef HAVE_PWR_WKUP3 - -#if defined(CONFIG_STM32_STM32F30XX) -# define HAVE_PWR_WKUP2 1 -#elif defined(CONFIG_STM32_STM32L15XX) || defined(CONFIG_STM32_STM32F33XX) || \ - defined(CONFIG_STM32_STM32F37XX) -# define HAVE_PWR_WKUP2 1 -# define HAVE_PWR_WKUP3 1 -#endif - -/* Thr parts only support a single Wake-up pin do not include the numeric - * suffix in the naming. - */ - -#ifndef PWR_CSR_EWUP1 -# define PWR_CSR_EWUP1 PWR_CSR_EWUP -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -static uint16_t g_bkp_writable_counter = 0; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -static inline uint32_t stm32_pwr_getreg32(uint8_t offset) -{ - return getreg32(STM32_PWR_BASE + (uint32_t)offset); -} - -static inline void stm32_pwr_putreg32(uint8_t offset, uint32_t value) -{ - putreg32(value, STM32_PWR_BASE + (uint32_t)offset); -} - -static inline void stm32_pwr_modifyreg32(uint8_t offset, uint32_t clearbits, - uint32_t setbits) -{ - modifyreg32(STM32_PWR_BASE + (uint32_t)offset, clearbits, setbits); -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_pwr_enablesdadc - * - * Description: - * Enables SDADC power - * - * Input Parameters: - * sdadc - SDADC number 1-3 - * - * Returned Value: - * None - * - ****************************************************************************/ - -#if defined(CONFIG_STM32_STM32F37XX) -void stm32_pwr_enablesdadc(uint8_t sdadc) -{ - uint32_t setbits = 0; - - switch (sdadc) - { - case 1: - setbits = PWR_CR_ENSD1; - break; - - case 2: - setbits = PWR_CR_ENSD2; - break; - - case 3: - setbits = PWR_CR_ENSD3; - break; - } - - stm32_pwr_modifyreg32(STM32_PWR_CR_OFFSET, 0, setbits); -} -#endif - -/**************************************************************************** - * Name: stm32_pwr_initbkp - * - * Description: - * Insures the referenced count access to the backup domain (RTC registers, - * RTC backup data registers and backup SRAM is consistent with the HW - * state without relying on a variable. - * - * NOTE: This function should only be called by SoC Start up code. - * - * Input Parameters: - * writable - True: enable ability to write to backup domain registers - * - * Returned Value: - * None - * - ****************************************************************************/ - -void stm32_pwr_initbkp(bool writable) -{ - uint16_t regval; - - /* Make the HW not writable */ - - regval = stm32_pwr_getreg32(STM32_PWR_CR_OFFSET); - regval &= ~PWR_CR_DBP; - stm32_pwr_putreg32(STM32_PWR_CR_OFFSET, regval); - - /* Make the reference count agree */ - - g_bkp_writable_counter = 0; - stm32_pwr_enablebkp(writable); -} - -/**************************************************************************** - * Name: stm32_pwr_enablebkp - * - * Description: - * Enables access to the backup domain (RTC registers, RTC backup data - * registers and backup SRAM). - * - * NOTE: - * Reference counting is used in order to supported nested calls to this - * function. As a consequence, every call to stm32_pwr_enablebkp(true) - * must be followed by a matching call to stm32_pwr_enablebkp(false). - * - * Input Parameters: - * writable - True: enable ability to write to backup domain registers - * - * Returned Value: - * None - * - ****************************************************************************/ - -void stm32_pwr_enablebkp(bool writable) -{ - irqstate_t flags; - uint16_t regval; - bool waswritable; - bool wait = false; - - flags = enter_critical_section(); - - /* Get the current state of the STM32 PWR control register */ - - regval = stm32_pwr_getreg32(STM32_PWR_CR_OFFSET); - waswritable = ((regval & PWR_CR_DBP) != 0); - - if (writable) - { - DEBUGASSERT(g_bkp_writable_counter < UINT16_MAX); - g_bkp_writable_counter++; - } - else if (g_bkp_writable_counter > 0) - { - g_bkp_writable_counter--; - } - - /* Enable or disable the ability to write */ - - if (waswritable && g_bkp_writable_counter == 0) - { - /* Disable backup domain access */ - - regval &= ~PWR_CR_DBP; - stm32_pwr_putreg32(STM32_PWR_CR_OFFSET, regval); - } - else if (!waswritable && g_bkp_writable_counter > 0) - { - /* Enable backup domain access */ - - regval |= PWR_CR_DBP; - stm32_pwr_putreg32(STM32_PWR_CR_OFFSET, regval); - - wait = true; - } - - leave_critical_section(flags); - - if (wait) - { - /* Enable does not happen right away */ - - up_udelay(4); - } -} - -/**************************************************************************** - * Name: stm32_pwr_enablewkup - * - * Description: - * Enables the WKUP pin. - * - * Input Parameters: - * wupin - Selects the WKUP pin to enable/disable - * wupon - state to set it to - * - * Returned Value: - * Zero (OK) is returned on success; A negated errno value is returned on - * any failure. The only cause of failure is if the selected MCU does not - * support the requested wakeup pin. - * - ****************************************************************************/ - -int stm32_pwr_enablewkup(enum stm32_pwr_wupin_e wupin, bool wupon) -{ - uint16_t pinmask; - - /* Select the PWR_CSR bit associated with the requested wakeup pin */ - - switch (wupin) - { - case PWR_WUPIN_1: /* Wake-up pin 1 (all parts) */ - pinmask = PWR_CSR_EWUP1; - break; - -#ifdef HAVE_PWR_WKUP2 - case PWR_WUPIN_2: /* Wake-up pin 2 */ - pinmask = PWR_CSR_EWUP2; - break; -#endif - -#ifdef HAVE_PWR_WKUP3 - case PWR_WUPIN_3: /* Wake-up pin 3 */ - pinmask = PWR_CSR_EWUP3; - break; -#endif - - default: - return -EINVAL; - } - - /* Set/clear the wakeup pin enable bit in the CSR. This must be done - * within a critical section because the CSR is shared with other functions - * that may be running concurrently on another thread. - */ - - if (wupon) - { - /* Enable the wakeup pin by setting the bit in the CSR. */ - - stm32_pwr_modifyreg32(STM32_PWR_CSR_OFFSET, 0, pinmask); - } - else - { - /* Disable the wakeup pin by clearing the bit in the CSR. */ - - stm32_pwr_modifyreg32(STM32_PWR_CSR_OFFSET, pinmask, 0); - } - - return OK; -} - -/**************************************************************************** - * Name: stm32_pwr_getsbf - * - * Description: - * Return the standby flag. - * - ****************************************************************************/ - -bool stm32_pwr_getsbf(void) -{ - return (stm32_pwr_getreg32(STM32_PWR_CSR_OFFSET) & PWR_CSR_SBF) != 0; -} - -/**************************************************************************** - * Name: stm32_pwr_getwuf - * - * Description: - * Return the wakeup flag. - * - ****************************************************************************/ - -bool stm32_pwr_getwuf(void) -{ - return (stm32_pwr_getreg32(STM32_PWR_CSR_OFFSET) & PWR_CSR_WUF) != 0; -} - -/**************************************************************************** - * Name: stm32_pwr_enablebreg - * - * Description: - * Enables the Backup regulator, the Backup regulator (used to maintain - * backup SRAM content in Standby and VBAT modes) is enabled. If BRE is - * reset, the backup regulator is switched off. The backup SRAM can still - * be used but its content will be lost in the Standby and VBAT modes. - * Once set, the application must wait that the Backup Regulator Ready - * flag (BRR) is set to indicate that the data written into the RAM will - * be maintained in the Standby and VBAT modes. - * - * Input Parameters: - * region - state to set it to - * - * Returned Value: - * None - * - ****************************************************************************/ - -#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) -void stm32_pwr_enablebreg(bool region) -{ - uint16_t regval; - - regval = stm32_pwr_getreg32(STM32_PWR_CSR_OFFSET); - regval &= ~PWR_CSR_BRE; - regval |= region ? PWR_CSR_BRE : 0; - stm32_pwr_putreg32(STM32_PWR_CSR_OFFSET, regval); - - if (region) - { - while ((stm32_pwr_getreg32(STM32_PWR_CSR_OFFSET) & PWR_CSR_BRR) == 0); - } -} -#endif - -/**************************************************************************** - * Name: stm32_pwr_setvos - * - * Description: - * Set voltage scaling for EnergyLite devices. - * - * Input Parameters: - * vos - Properly aligned voltage scaling select bits for the PWR_CR - * register. - * - * Returned Value: - * None - * - * Assumptions: - * At present, this function is called only from initialization logic. - * If used for any other purpose that protection to assure that its - * operation is atomic will be required. - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_ENERGYLITE -void stm32_pwr_setvos(uint16_t vos) -{ - uint16_t regval; - - /* The following sequence is required to program the voltage regulator - * ranges: - * 1. Check VDD to identify which ranges are allowed... - * 2. Poll VOSF bit of in PWR_CSR. Wait until it is reset to 0. - * 3. Configure the voltage scaling range by setting the VOS bits in the - * PWR_CR register. - * 4. Poll VOSF bit of in PWR_CSR register. Wait until it is reset to 0. - */ - - while ((stm32_pwr_getreg32(STM32_PWR_CSR_OFFSET) & PWR_CSR_VOSF) != 0); - - regval = stm32_pwr_getreg32(STM32_PWR_CR_OFFSET); - regval &= ~PWR_CR_VOS_MASK; - regval |= (vos & PWR_CR_VOS_MASK); - stm32_pwr_putreg32(STM32_PWR_CR_OFFSET, regval); - - while ((stm32_pwr_getreg32(STM32_PWR_CSR_OFFSET) & PWR_CSR_VOSF) != 0); -} - -/**************************************************************************** - * Name: stm32_pwr_setpvd - * - * Description: - * Sets power voltage detector - * - * Input Parameters: - * pls - PVD level - * - * Returned Value: - * None - * - * Assumptions: - * At present, this function is called only from initialization logic. - * If used for any other purpose that protection to assure that its - * operation is atomic will be required. - * - ****************************************************************************/ - -void stm32_pwr_setpvd(uint16_t pls) -{ - uint16_t regval; - - /* Set PLS */ - - regval = stm32_pwr_getreg32(STM32_PWR_CR_OFFSET); - regval &= ~PWR_CR_PLS_MASK; - regval |= (pls & PWR_CR_PLS_MASK); - - /* Write value to register */ - - stm32_pwr_putreg32(STM32_PWR_CR_OFFSET, regval); -} - -/**************************************************************************** - * Name: stm32_pwr_enablepvd - * - * Description: - * Enable the Programmable Voltage Detector - * - ****************************************************************************/ - -void stm32_pwr_enablepvd(void) -{ - /* Enable PVD by setting the PVDE bit in PWR_CR register. */ - - stm32_pwr_modifyreg32(STM32_PWR_CR_OFFSET, 0, PWR_CR_PVDE); -} - -/**************************************************************************** - * Name: stm32_pwr_disablepvd - * - * Description: - * Disable the Programmable Voltage Detector - * - ****************************************************************************/ - -void stm32_pwr_disablepvd(void) -{ - /* Disable PVD by clearing the PVDE bit in PWR_CR register. */ - - stm32_pwr_modifyreg32(STM32_PWR_CR_OFFSET, PWR_CR_PVDE, 0); -} - -#endif /* CONFIG_STM32_ENERGYLITE */ - -#endif /* CONFIG_STM32_PWR */ diff --git a/arch/arm/src/stm32/stm32_pwr.h b/arch/arm/src/stm32/stm32_pwr.h deleted file mode 100644 index 141f81a360910..0000000000000 --- a/arch/arm/src/stm32/stm32_pwr.h +++ /dev/null @@ -1,267 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_pwr.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32_STM32_PWR_H -#define __ARCH_ARM_SRC_STM32_STM32_PWR_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include "chip.h" -#include "hardware/stm32_pwr.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#ifndef __ASSEMBLY__ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -/* Identify MCU-specific wakeup pin. - * Different STM32 parts support differing numbers of wakeup pins. - */ - -enum stm32_pwr_wupin_e -{ - PWR_WUPIN_1 = 0, /* Wake-up pin 1 (all parts) */ - PWR_WUPIN_2, /* Wake-up pin 2 */ - PWR_WUPIN_3 /* Wake-up pin 3 */ -}; - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_pwr_enablesdadc - * - * Description: - * Enables SDADC power - * - * Input Parameters: - * sdadc - SDADC number 1-3 - * - * Returned Value: - * None - * - ****************************************************************************/ - -#if defined(CONFIG_STM32_STM32F37XX) -void stm32_pwr_enablesdadc(uint8_t sdadc); -#endif - -/**************************************************************************** - * Name: stm32_pwr_initbkp - * - * Description: - * Insures the referenced count access to the backup domain - * (RTC registers, RTC backup data registers and backup SRAM is consistent - * with the HW state without relying on a variable. - * - * NOTE: This function should only be called by SoC Start up code. - * - * Input Parameters: - * writable - set the initial state of the enable and the - * bkp_writable_counter - * - * Returned Value: - * None - * - ****************************************************************************/ - -void stm32_pwr_initbkp(bool writable); - -/**************************************************************************** - * Name: stm32_pwr_enablebkp - * - * Description: - * Enables access to the backup domain - * (RTC registers, RTC backup data registers and backup SRAM). - * - * NOTE: - * Reference counting is used in order to supported nested calls to this - * function. As a consequence, every call to stm32_pwr_enablebkp(true) - * must be followed by a matching call to stm32_pwr_enablebkp(false). - * - * Input Parameters: - * writable - True: enable ability to write to backup domain registers - * - * Returned Value: - * None - * - ****************************************************************************/ - -void stm32_pwr_enablebkp(bool writable); - -/**************************************************************************** - * Name: stm32_pwr_enablewkup - * - * Description: - * Enables the WKUP pin. - * - * Input Parameters: - * wupin - Selects the WKUP pin to enable/disable - * wupon - state to set it to - * - * Returned Value: - * Zero (OK) is returned on success; A negated errno value is returned on - * any failure. The only cause of failure is if the selected MCU does not - * support the requested wakeup pin. - * - ****************************************************************************/ - -int stm32_pwr_enablewkup(enum stm32_pwr_wupin_e wupin, bool wupon); - -/**************************************************************************** - * Name: stm32_pwr_getsbf - * - * Description: - * Return the standby flag. - * - ****************************************************************************/ - -bool stm32_pwr_getsbf(void); - -/**************************************************************************** - * Name: stm32_pwr_getwuf - * - * Description: - * Return the wakeup flag. - * - ****************************************************************************/ - -bool stm32_pwr_getwuf(void); - -/**************************************************************************** - * Name: stm32_pwr_enablebreg - * - * Description: - * Enables the Backup regulator, the Backup regulator (used to maintain - * backup SRAM content in Standby and VBAT modes) is enabled. If BRE is - * reset, the backup regulator is switched off. The backup SRAM can still - * be used but its content will be lost in the Standby and VBAT modes. - * Once set, the application must wait that the Backup Regulator Ready flag - * (BRR) is set to indicate that the data written into the RAM will be - * maintained in the Standby and VBAT modes. - * - * Input Parameters: - * region - state to set it to - * - * Returned Value: - * None - * - ****************************************************************************/ - -#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) -void stm32_pwr_enablebreg(bool region); -#else -# define stm32_pwr_enablebreg(region) -#endif - -/**************************************************************************** - * Name: stm32_pwr_setvos - * - * Description: - * Set voltage scaling for EnergyLite devices. - * - * Input Parameters: - * vos - Properly aligned voltage scaling select bits for the PWR_CR - * register. - * - * Returned Value: - * None - * - * Assumptions: - * At present, this function is called only from initialization logic. - * If used for any other purpose that protection to assure that its - * operation is atomic will be required. - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_ENERGYLITE -void stm32_pwr_setvos(uint16_t vos); - -/**************************************************************************** - * Name: stm32_pwr_setpvd - * - * Description: - * Sets power voltage detector for EnergyLite devices. - * - * Input Parameters: - * pls - PVD level - * - * Returned Value: - * None - * - * Assumptions: - * At present, this function is called only from initialization logic. - * - ****************************************************************************/ - -void stm32_pwr_setpvd(uint16_t pls); - -/**************************************************************************** - * Name: stm32_pwr_enablepvd - * - * Description: - * Enable the Programmable Voltage Detector - * - ****************************************************************************/ - -void stm32_pwr_enablepvd(void); - -/**************************************************************************** - * Name: stm32_pwr_disablepvd - * - * Description: - * Disable the Programmable Voltage Detector - * - ****************************************************************************/ - -void stm32_pwr_disablepvd(void); - -#endif /* CONFIG_STM32_ENERGYLITE */ - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32_STM32_PWR_H */ diff --git a/arch/arm/src/stm32/stm32_qencoder.c b/arch/arm/src/stm32/stm32_qencoder.c deleted file mode 100644 index 1c0a9921b4ea5..0000000000000 --- a/arch/arm/src/stm32/stm32_qencoder.c +++ /dev/null @@ -1,1484 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_qencoder.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32.h" -#include "stm32_gpio.h" -#include "stm32_tim.h" -#include "stm32_qencoder.h" - -#ifdef CONFIG_SENSORS_QENCODER - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Timers *******************************************************************/ - -#undef HAVE_32BIT_TIMERS -#undef HAVE_16BIT_TIMERS - -/* On the F1 series, all timers are 16-bit. */ - -#if defined(CONFIG_STM32_STM32F10XX) - -# define HAVE_16BIT_TIMERS 1 - - /* The width in bits of each timer */ - -# define TIM1_BITWIDTH 16 -# define TIM2_BITWIDTH 16 -# define TIM3_BITWIDTH 16 -# define TIM4_BITWIDTH 16 -# define TIM5_BITWIDTH 16 -# define TIM8_BITWIDTH 16 - -/* On the F2, F3, F4 and G4 series, TIM2 and TIM5 are 32-bit. - * All of the rest are 16-bit - */ - -#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) || \ - defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32G4XXX) - - /* If TIM2 or TIM5 are enabled, then we have 32-bit timers */ - -# if defined(CONFIG_STM32_TIM2_QE) || defined(CONFIG_STM32_TIM5_QE) -# define HAVE_32BIT_TIMERS 1 -# endif - - /* If TIM1,3,4, or 8 are enabled, then we have 16-bit timers */ - -# if defined(CONFIG_STM32_TIM1_QE) || defined(CONFIG_STM32_TIM3_QE) || \ - defined(CONFIG_STM32_TIM4_QE) || defined(CONFIG_STM32_TIM8_QE) -# define HAVE_16BIT_TIMERS 1 -# endif - - /* The width in bits of each timer */ - -# define TIM1_BITWIDTH 16 -# define TIM2_BITWIDTH 32 -# define TIM3_BITWIDTH 16 -# define TIM4_BITWIDTH 16 -# define TIM5_BITWIDTH 32 -# define TIM8_BITWIDTH 16 -#endif - -/* Do we need to support mixed 16- and 32-bit timers */ - -#undef HAVE_MIXEDWIDTH_TIMERS -#if defined(HAVE_16BIT_TIMERS) && defined(HAVE_32BIT_TIMERS) -# define HAVE_MIXEDWIDTH_TIMERS 1 -#endif - -/* Input filter *************************************************************/ - -#ifdef CONFIG_STM32_QENCODER_FILTER -# if defined(CONFIG_STM32_QENCODER_SAMPLE_FDTS) -# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_1) -# define STM32_QENCODER_ICF GTIM_CCMR_ICF_NOFILT -# endif -# elif defined(CONFIG_STM32_QENCODER_SAMPLE_CKINT) -# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_2) -# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FCKINT2 -# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_4) -# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FCKINT4 -# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_8) -# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FCKINT8 -# endif -# elif defined(CONFIG_STM32_QENCODER_SAMPLE_FDTS_2) -# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_6) -# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd26 -# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_8) -# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd28 -# endif -# elif defined(CONFIG_STM32_QENCODER_SAMPLE_FDTS_4) -# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_6) -# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd46 -# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_8) -# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd48 -# endif -# elif defined(CONFIG_STM32_QENCODER_SAMPLE_FDTS_8) -# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_6) -# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd86 -# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_8) -# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd88 -# endif -# elif defined(CONFIG_STM32_QENCODER_SAMPLE_FDTS_16) -# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_5) -# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd165 -# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_6) -# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd166 -# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_8) -# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd168 -# endif -# elif defined(CONFIG_STM32_QENCODER_SAMPLE_FDTS_32) -# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_5) -# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd325 -# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_6) -# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd326 -# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_8) -# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd328 -# endif -# endif - -# ifndef STM32_QENCODER_ICF -# warning "Invalid encoder filter combination, filter disabled" -# endif -#endif - -#ifndef STM32_QENCODER_ICF -# define STM32_QENCODER_ICF GTIM_CCMR_ICF_NOFILT -#endif - -#if defined(CONFIG_STM32_STM32F10XX) -# define STM32_GPIO_INPUT_FLOAT (GPIO_INPUT | GPIO_CNF_INFLOAT | \ - GPIO_MODE_INPUT) -#elif defined(CONFIG_STM32_STM32F20XX) || \ - defined(CONFIG_STM32_STM32F30XX) || \ - defined(CONFIG_STM32_STM32F4XXX) || \ - defined(CONFIG_STM32_STM32G4XXX) -# define STM32_GPIO_INPUT_FLOAT (GPIO_INPUT | GPIO_FLOAT) -#else -# error "Unrecognized STM32 chip" -#endif - -/* RCC definitions */ - -#if defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F20XX) || \ - defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F4XXX) - -# define TIMRCCEN_TIM1 STM32_RCC_APB2ENR -# define TIMEN_TIM1 RCC_APB2ENR_TIM1EN -# define TIMRCCRST_TIM1 STM32_RCC_APB2RSTR -# define TIMRST_TIM1 RCC_APB2RSTR_TIM1RST - -# define TIMRCCEN_TIM2 STM32_RCC_APB1ENR -# define TIMEN_TIM2 RCC_APB1ENR_TIM2EN -# define TIMRCCRST_TIM2 STM32_RCC_APB1RSTR -# define TIMRST_TIM2 RCC_APB1RSTR_TIM2RST - -# define TIMRCCEN_TIM3 STM32_RCC_APB1ENR -# define TIMEN_TIM3 RCC_APB1ENR_TIM3EN -# define TIMRCCRST_TIM3 STM32_RCC_APB1RSTR -# define TIMRST_TIM3 RCC_APB1RSTR_TIM3RST - -# define TIMRCCEN_TIM4 STM32_RCC_APB1ENR -# define TIMEN_TIM4 RCC_APB1ENR_TIM4EN -# define TIMRCCRST_TIM4 STM32_RCC_APB1RSTR -# define TIMRST_TIM4 RCC_APB1RSTR_TIM4RST - -# define TIMRCCEN_TIM5 STM32_RCC_APB1ENR -# define TIMEN_TIM5 RCC_APB1ENR_TIM5EN -# define TIMRCCRST_TIM5 STM32_RCC_APB1RSTR -# define TIMRST_TIM5 RCC_APB1RSTR_TIM5RST - -# define TIMRCCEN_TIM8 STM32_RCC_APB2ENR -# define TIMEN_TIM8 RCC_APB2ENR_TIM8EN -# define TIMRCCRST_TIM8 STM32_RCC_APB2RSTR -# define TIMRST_TIM8 RCC_APB2RSTR_TIM8RST - -#elif defined(CONFIG_STM32_STM32G4XXX) - -# define TIMRCCEN_TIM1 STM32_RCC_APB2ENR -# define TIMEN_TIM1 RCC_APB2ENR_TIM1EN -# define TIMRCCRST_TIM1 STM32_RCC_APB2RSTR -# define TIMRST_TIM1 RCC_APB2RSTR_TIM1RST - -# define TIMRCCEN_TIM2 STM32_RCC_APB1ENR1 -# define TIMEN_TIM2 RCC_APB1ENR1_TIM2EN -# define TIMRCCRST_TIM2 STM32_RCC_APB1RSTR1 -# define TIMRST_TIM2 RCC_APB1RSTR1_TIM2RST - -# define TIMRCCEN_TIM3 STM32_RCC_APB1ENR1 -# define TIMEN_TIM3 RCC_APB1ENR1_TIM3EN -# define TIMRCCRST_TIM3 STM32_RCC_APB1RSTR1 -# define TIMRST_TIM3 RCC_APB1RSTR1_TIM3RST - -# define TIMRCCEN_TIM4 STM32_RCC_APB1ENR1 -# define TIMEN_TIM4 RCC_APB1ENR1_TIM4EN -# define TIMRCCRST_TIM4 STM32_RCC_APB1RSTR1 -# define TIMRST_TIM4 RCC_APB1RSTR1_TIM4RST - -# define TIMRCCEN_TIM5 STM32_RCC_APB1ENR1 -# define TIMEN_TIM5 RCC_APB1ENR1_TIM5EN -# define TIMRCCRST_TIM5 STM32_RCC_APB1RSTR1 -# define TIMRST_TIM5 RCC_APB1RSTR1_TIM5RST - -# define TIMRCCEN_TIM8 STM32_RCC_APB2ENR -# define TIMEN_TIM8 RCC_APB2ENR_TIM8EN -# define TIMRCCRST_TIM8 STM32_RCC_APB2RSTR -# define TIMRST_TIM8 RCC_APB2RSTR_TIM8RST - -#else -# error "Unrecognized STM32 chip" -#endif - -/* Debug ********************************************************************/ - -/* Non-standard debug that may be enabled just for testing the quadrature - * encoder - */ - -#ifndef CONFIG_DEBUG_FEATURES -# undef CONFIG_DEBUG_SENSORS -#endif - -#ifdef CONFIG_DEBUG_SENSORS -# ifdef CONFIG_DEBUG_INFO -# define qe_dumpgpio(p,m) stm32_dumpgpio(p,m) -# else -# define qe_dumpgpio(p,m) -# endif -#else -# define qe_dumpgpio(p,m) -#endif - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/* Constant configuration structure that is retained in FLASH */ - -struct stm32_qeconfig_s -{ - uint8_t timid; /* Timer ID {1,2,3,4,5,8} */ - uint8_t irq; /* Timer update IRQ */ -#ifdef HAVE_MIXEDWIDTH_TIMERS - uint8_t width; /* Timer width (16- or 32-bits) */ -#endif -#ifdef CONFIG_STM32_STM32F10XX - uint16_t ti1cfg; /* TI1 input pin configuration (16-bit encoding) */ - uint16_t ti2cfg; /* TI2 input pin configuration (16-bit encoding) */ -#else - uint32_t ti1cfg; /* TI1 input pin configuration (20-bit encoding) */ - uint32_t ti2cfg; /* TI2 input pin configuration (20-bit encoding) */ -#endif - uintptr_t regaddr; /* RCC clock enable register address */ - uint32_t enable; /* RCC clock enable bit */ - uint32_t base; /* Register base address */ - uint32_t psc; /* Timer input clock prescaler */ -}; - -/* Overall, RAM-based state structure */ - -struct stm32_lowerhalf_s -{ - /* The first field of this state structure must be a pointer to the lower- - * half callback structure: - */ - - const struct qe_ops_s *ops; /* Lower half callback structure */ - - /* STM32 driver-specific fields: */ - - const struct stm32_qeconfig_s *config; /* static configuration */ - - bool inuse; /* True: The lower-half driver is in-use */ -#ifdef CONFIG_STM32_QENCODER_INDEX_PIN - uint32_t index_pin; /* Index pin GPIO */ - bool index_use; /* True: Index pin is configured */ - int32_t index_offset; /* Index pin offset */ -#endif - -#ifndef CONFIG_STM32_QENCODER_DISABLE_EXTEND16BTIMERS - volatile int32_t position; /* The current position offset */ -#endif - spinlock_t lock; -}; - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -/* Helper functions */ - -static uint16_t stm32_getreg16(struct stm32_lowerhalf_s *priv, - int offset); -static void stm32_putreg16(struct stm32_lowerhalf_s *priv, int offset, - uint16_t value); -static uint32_t stm32_getreg32(struct stm32_lowerhalf_s *priv, - int offset); -static void stm32_putreg32(struct stm32_lowerhalf_s *priv, int offset, - uint32_t value); - -#if defined(CONFIG_DEBUG_SENSORS) && defined(CONFIG_DEBUG_INFO) -static void stm32_dumpregs(struct stm32_lowerhalf_s *priv, - const char *msg); -#else -# define stm32_dumpregs(priv,msg) -#endif - -static struct stm32_lowerhalf_s *stm32_tim2lower(int tim); - -/* Interrupt handling */ - -#ifndef CONFIG_STM32_QENCODER_DISABLE_EXTEND16BTIMERS -static int stm32_interrupt(int irq, void *context, void *arg); -#endif - -/* Lower-half Quadrature Encoder Driver Methods */ - -static int stm32_setup(struct qe_lowerhalf_s *lower); -static int stm32_shutdown(struct qe_lowerhalf_s *lower); -static int stm32_position(struct qe_lowerhalf_s *lower, - int32_t *pos); -static int stm32_setposmax(struct qe_lowerhalf_s *lower, uint32_t pos); -static int stm32_reset(struct qe_lowerhalf_s *lower); -static int stm32_setindex(struct qe_lowerhalf_s *lower, uint32_t pos); -static int stm32_ioctl(struct qe_lowerhalf_s *lower, int cmd, - unsigned long arg); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* The lower half callback structure */ - -static const struct qe_ops_s g_qecallbacks = -{ - .setup = stm32_setup, - .shutdown = stm32_shutdown, - .position = stm32_position, - .setposmax = stm32_setposmax, - .reset = stm32_reset, - .setindex = stm32_setindex, - .ioctl = stm32_ioctl, -}; - -/* Per-timer state structures */ - -#ifdef CONFIG_STM32_TIM1_QE -static const struct stm32_qeconfig_s g_tim1config = -{ - .timid = 1, - .irq = STM32_IRQ_TIM1UP, -#ifdef HAVE_MIXEDWIDTH_TIMERS - .width = TIM1_BITWIDTH, -#endif - .regaddr = TIMRCCEN_TIM1, - .enable = TIMEN_TIM1, - .base = STM32_TIM1_BASE, - .psc = CONFIG_STM32_TIM1_QEPSC, - .ti1cfg = GPIO_TIM1_CH1IN, - .ti2cfg = GPIO_TIM1_CH2IN, -}; - -static struct stm32_lowerhalf_s g_tim1lower = -{ - .ops = &g_qecallbacks, - .config = &g_tim1config, - .inuse = false, - .lock = SP_UNLOCKED, -}; - -#endif - -#ifdef CONFIG_STM32_TIM2_QE -static const struct stm32_qeconfig_s g_tim2config = -{ - .timid = 2, - .irq = STM32_IRQ_TIM2, -#ifdef HAVE_MIXEDWIDTH_TIMERS - .width = TIM2_BITWIDTH, -#endif - .regaddr = TIMRCCEN_TIM2, - .enable = TIMEN_TIM2, - .base = STM32_TIM2_BASE, - .psc = CONFIG_STM32_TIM2_QEPSC, - .ti1cfg = GPIO_TIM2_CH1IN, - .ti2cfg = GPIO_TIM2_CH2IN, -}; - -static struct stm32_lowerhalf_s g_tim2lower = -{ - .ops = &g_qecallbacks, - .config = &g_tim2config, - .inuse = false, - .lock = SP_UNLOCKED, -}; - -#endif - -#ifdef CONFIG_STM32_TIM3_QE -static const struct stm32_qeconfig_s g_tim3config = -{ - .timid = 3, - .irq = STM32_IRQ_TIM3, -#ifdef HAVE_MIXEDWIDTH_TIMERS - .width = TIM3_BITWIDTH, -#endif - .regaddr = TIMRCCEN_TIM3, - .enable = TIMEN_TIM3, - .base = STM32_TIM3_BASE, - .psc = CONFIG_STM32_TIM3_QEPSC, - .ti1cfg = GPIO_TIM3_CH1IN, - .ti2cfg = GPIO_TIM3_CH2IN, -}; - -static struct stm32_lowerhalf_s g_tim3lower = -{ - .ops = &g_qecallbacks, - .config = &g_tim3config, - .inuse = false, - .lock = SP_UNLOCKED, -}; - -#endif - -#ifdef CONFIG_STM32_TIM4_QE -static const struct stm32_qeconfig_s g_tim4config = -{ - .timid = 4, - .irq = STM32_IRQ_TIM4, -#ifdef HAVE_MIXEDWIDTH_TIMERS - .width = TIM4_BITWIDTH, -#endif - .regaddr = TIMRCCEN_TIM4, - .enable = TIMEN_TIM4, - .base = STM32_TIM4_BASE, - .psc = CONFIG_STM32_TIM4_QEPSC, - .ti1cfg = GPIO_TIM4_CH1IN, - .ti2cfg = GPIO_TIM4_CH2IN, -}; - -static struct stm32_lowerhalf_s g_tim4lower = -{ - .ops = &g_qecallbacks, - .config = &g_tim4config, - .inuse = false, - .lock = SP_UNLOCKED, -}; - -#endif - -#ifdef CONFIG_STM32_TIM5_QE -static const struct stm32_qeconfig_s g_tim5config = -{ - .timid = 5, - .irq = STM32_IRQ_TIM5, -#ifdef HAVE_MIXEDWIDTH_TIMERS - .width = TIM5_BITWIDTH, -#endif - .regaddr = TIMRCCEN_TIM5, - .enable = TIMEN_TIM5, - .base = STM32_TIM5_BASE, - .psc = CONFIG_STM32_TIM5_QEPSC, - .ti1cfg = GPIO_TIM5_CH1IN, - .ti2cfg = GPIO_TIM5_CH2IN, -}; - -static struct stm32_lowerhalf_s g_tim5lower = -{ - .ops = &g_qecallbacks, - .config = &g_tim5config, - .inuse = false, - .lock = SP_UNLOCKED, -}; - -#endif - -#ifdef CONFIG_STM32_TIM8_QE -static const struct stm32_qeconfig_s g_tim8config = -{ - .timid = 8, - .irq = STM32_IRQ_TIM8UP, -#ifdef HAVE_MIXEDWIDTH_TIMERS - .width = TIM8_BITWIDTH, -#endif - .regaddr = TIMRCCEN_TIM8, - .enable = TIMEN_TIM8, - .base = STM32_TIM8_BASE, - .psc = CONFIG_STM32_TIM8_QEPSC, - .ti1cfg = GPIO_TIM8_CH1IN, - .ti2cfg = GPIO_TIM8_CH2IN, -}; - -static struct stm32_lowerhalf_s g_tim8lower = -{ - .ops = &g_qecallbacks, - .config = &g_tim8config, - .inuse = false, - .lock = SP_UNLOCKED, -}; - -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_getreg16 - * - * Description: - * Read the value of a 16-bit timer register. - * - * Input Parameters: - * priv - A reference to the lower half status - * offset - The offset to the register to read - * - * Returned Value: - * The current contents of the specified register - * - ****************************************************************************/ - -static uint16_t stm32_getreg16(struct stm32_lowerhalf_s *priv, int offset) -{ - return getreg16(priv->config->base + offset); -} - -/**************************************************************************** - * Name: stm32_putreg16 - * - * Description: - * Write a value to a 16-bit timer register. - * - * Input Parameters: - * priv - A reference to the lower half status - * offset - The offset to the register to read - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void stm32_putreg16(struct stm32_lowerhalf_s *priv, int offset, - uint16_t value) -{ - putreg16(value, priv->config->base + offset); -} - -/**************************************************************************** - * Name: stm32_getreg32 - * - * Description: - * Read the value of a 32-bit timer register. This applies only for the - * STM32 F4 32-bit registers (CNT, ARR, CRR1-4) in the 32-bit timers TIM2-5 - * (but works OK with the 16-bit TIM1,8 and F1 registers as well). - * - * Input Parameters: - * priv - A reference to the lower half status - * offset - The offset to the register to read - * - * Returned Value: - * The current contents of the specified register - * - ****************************************************************************/ - -static uint32_t stm32_getreg32(struct stm32_lowerhalf_s *priv, - int offset) -{ - return getreg32(priv->config->base + offset); -} - -/**************************************************************************** - * Name: stm32_putreg32 - * - * Description: - * Write a value to a 32-bit timer register. This applies only for the - * STM32 F4 32-bit registers (CNT, ARR, CRR1-4) in the 32-bit timers TIM2-5 - * (but works OK with the 16-bit TIM1,8 and F1 registers). - * - * Input Parameters: - * priv - A reference to the lower half status - * offset - The offset to the register to read - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void stm32_putreg32(struct stm32_lowerhalf_s *priv, int offset, - uint32_t value) -{ - putreg32(value, priv->config->base + offset); -} - -/**************************************************************************** - * Name: stm32_dumpregs - * - * Description: - * Dump all timer registers. - * - * Input Parameters: - * priv - A reference to the QENCODER block status - * - * Returned Value: - * None - * - ****************************************************************************/ - -#if defined(CONFIG_DEBUG_SENSORS) && defined(CONFIG_DEBUG_INFO) -static void stm32_dumpregs(struct stm32_lowerhalf_s *priv, - const char *msg) -{ - sninfo("%s:\n", msg); - sninfo(" CR1: %04x CR2: %04x SMCR: %04x DIER: %04x\n", - stm32_getreg16(priv, STM32_GTIM_CR1_OFFSET), - stm32_getreg16(priv, STM32_GTIM_CR2_OFFSET), - stm32_getreg16(priv, STM32_GTIM_SMCR_OFFSET), - stm32_getreg16(priv, STM32_GTIM_DIER_OFFSET)); - sninfo(" SR: %04x EGR: %04x CCMR1: %04x CCMR2: %04x\n", - stm32_getreg16(priv, STM32_GTIM_SR_OFFSET), - stm32_getreg16(priv, STM32_GTIM_EGR_OFFSET), - stm32_getreg16(priv, STM32_GTIM_CCMR1_OFFSET), - stm32_getreg16(priv, STM32_GTIM_CCMR2_OFFSET)); - sninfo(" CCER: %04x CNT: %04x PSC: %04x ARR: %04x\n", - stm32_getreg16(priv, STM32_GTIM_CCER_OFFSET), - stm32_getreg16(priv, STM32_GTIM_CNT_OFFSET), - stm32_getreg16(priv, STM32_GTIM_PSC_OFFSET), - stm32_getreg16(priv, STM32_GTIM_ARR_OFFSET)); - sninfo(" CCR1: %04x CCR2: %04x CCR3: %04x CCR4: %04x\n", - stm32_getreg16(priv, STM32_GTIM_CCR1_OFFSET), - stm32_getreg16(priv, STM32_GTIM_CCR2_OFFSET), - stm32_getreg16(priv, STM32_GTIM_CCR3_OFFSET), - stm32_getreg16(priv, STM32_GTIM_CCR4_OFFSET)); -#if defined(CONFIG_STM32_TIM1_QE) || defined(CONFIG_STM32_TIM8_QE) - if (priv->config->timid == 1 || priv->config->timid == 8) - { - sninfo(" RCR: %04x BDTR: %04x DCR: %04x DMAR: %04x\n", - stm32_getreg16(priv, STM32_ATIM_RCR_OFFSET), - stm32_getreg16(priv, STM32_ATIM_BDTR_OFFSET), - stm32_getreg16(priv, STM32_ATIM_DCR_OFFSET), - stm32_getreg16(priv, STM32_ATIM_DMAR_OFFSET)); - } - else -#endif - { - sninfo(" DCR: %04x DMAR: %04x\n", - stm32_getreg16(priv, STM32_GTIM_DCR_OFFSET), - stm32_getreg16(priv, STM32_GTIM_DMAR_OFFSET)); - } -} -#endif - -/**************************************************************************** - * Name: stm32_tim2lower - * - * Description: - * Map a timer number to a device structure - * - ****************************************************************************/ - -static struct stm32_lowerhalf_s *stm32_tim2lower(int tim) -{ - switch (tim) - { -#ifdef CONFIG_STM32_TIM1_QE - case 1: - return &g_tim1lower; -#endif -#ifdef CONFIG_STM32_TIM2_QE - case 2: - return &g_tim2lower; -#endif -#ifdef CONFIG_STM32_TIM3_QE - case 3: - return &g_tim3lower; -#endif -#ifdef CONFIG_STM32_TIM4_QE - case 4: - return &g_tim4lower; -#endif -#ifdef CONFIG_STM32_TIM5_QE - case 5: - return &g_tim5lower; -#endif -#ifdef CONFIG_STM32_TIM8_QE - case 8: - return &g_tim8lower; -#endif - default: - return NULL; - } -} - -/**************************************************************************** - * Name: stm32_interrupt - * - * Description: - * Common timer interrupt handling. NOTE: Only 16-bit timers require timer - * interrupts. - * - ****************************************************************************/ - -#ifndef CONFIG_STM32_QENCODER_DISABLE_EXTEND16BTIMERS -static int stm32_interrupt(int irq, void *context, void *arg) -{ - struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)arg; - uint16_t regval; - - DEBUGASSERT(priv != NULL); - - /* Verify that this is an update interrupt. Nothing else is expected. */ - - regval = stm32_getreg16(priv, STM32_GTIM_SR_OFFSET); - DEBUGASSERT((regval & ATIM_SR_UIF) != 0); - - /* Clear the UIF interrupt bit */ - - stm32_putreg16(priv, STM32_GTIM_SR_OFFSET, regval & ~GTIM_SR_UIF); - - /* Check the direction bit in the CR1 register and add or subtract the - * maximum value + 1, as appropriate. - */ - - regval = stm32_getreg16(priv, STM32_GTIM_CR1_OFFSET); - if ((regval & ATIM_CR1_DIR) != 0) - { - priv->position -= (int32_t)0x00010000; - } - else - { - priv->position += (int32_t)0x00010000; - } - - return OK; -} -#endif - -#ifdef CONFIG_STM32_QENCODER_INDEX_PIN -/**************************************************************************** - * Name: stm32_qe_index_irq - * - * Description: - * Common encoder index pin interrupt. - * - ****************************************************************************/ - -static int stm32_qe_index_irq(int irq, void *context, void *arg) -{ - struct stm32_lowerhalf_s *priv; - bool valid = false; - - DEBUGASSERT(arg); - - /* Get QE data */ - - priv = (struct stm32_lowerhalf_s *)arg; - - /* Get pin state */ - - valid = stm32_gpioread(priv->index_pin); - - /* Only if pin still high to avoid noises */ - - if (valid == true) - { - /* Force position to index offset */ - - stm32_putreg32(priv, STM32_GTIM_CNT_OFFSET, priv->index_offset); - } - - return OK; -} -#endif - -/**************************************************************************** - * Name: stm32_setup - * - * Description: - * This method is called when the driver is opened. The lower half driver - * should configure and initialize the device so that it is ready for use. - * The initial position value should be zero. * - * - ****************************************************************************/ - -static int stm32_setup(struct qe_lowerhalf_s *lower) -{ - struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; - uint16_t dier; - uint32_t smcr; - uint32_t ccmr1; - uint16_t ccer; - uint16_t cr1; -#ifndef CONFIG_STM32_QENCODER_DISABLE_EXTEND16BTIMERS - uint16_t regval; - int ret; -#endif - - /* Enable clocking to the timer */ - - modifyreg32(priv->config->regaddr, 0, priv->config->enable); - - /* Timer base configuration */ - - cr1 = stm32_getreg16(priv, STM32_GTIM_CR1_OFFSET); - - /* Clear the direction bit (0=count up) and select the Counter Mode - * (0=Edge aligned) (Timers 2-5 and 1-8 only) - */ - - cr1 &= ~(GTIM_CR1_DIR | GTIM_CR1_CMS_MASK); - stm32_putreg16(priv, STM32_GTIM_CR1_OFFSET, cr1); - - /* Set the Autoreload value */ - -#if defined(HAVE_MIXEDWIDTH_TIMERS) - if (priv->config->width == 32) - { - stm32_putreg32(priv, STM32_GTIM_ARR_OFFSET, 0xffffffff); - } - else - { - stm32_putreg16(priv, STM32_GTIM_ARR_OFFSET, 0xffff); - } -#elif defined(HAVE_32BIT_TIMERS) - stm32_putreg32(priv, STM32_GTIM_ARR_OFFSET, 0xffffffff); -#else - stm32_putreg16(priv, STM32_GTIM_ARR_OFFSET, 0xffff); -#endif - - /* Set the timer prescaler value. - * - * If we are doing precise shaft positioning, each qe pulse is important. - * So the STM32 has direct config control on the pulse count prescaler. - * This input clock just limits the incoming pulse rate, which should be - * lower than the peripheral clock due to resynchronization, but it is the - * responsibility of the system designer to decide the correct prescaler - * value, because it has a direct influence on the encoder resolution. - */ - - stm32_putreg16(priv, STM32_GTIM_PSC_OFFSET, (uint16_t)priv->config->psc); - -#if defined(CONFIG_STM32_TIM1_QE) || defined(CONFIG_STM32_TIM8_QE) - if (priv->config->timid == 1 || priv->config->timid == 8) - { - /* Clear the Repetition Counter value */ - - stm32_putreg16(priv, STM32_ATIM_RCR_OFFSET, 0); - } -#endif - - /* Generate an update event to reload the Prescaler - * and the repetition counter (only for TIM1 and TIM8) value immediately - */ - - stm32_putreg16(priv, STM32_GTIM_EGR_OFFSET, GTIM_EGR_UG); - - /* GPIO pin configuration */ - - stm32_configgpio(priv->config->ti1cfg); - stm32_configgpio(priv->config->ti2cfg); - - /* Set the encoder Mode 3 */ - - smcr = stm32_getreg32(priv, STM32_GTIM_SMCR_OFFSET); - smcr &= ~GTIM_SMCR_SMS_MASK; - smcr |= GTIM_SMCR_ENCMD3; - stm32_putreg32(priv, STM32_GTIM_SMCR_OFFSET, smcr); - - /* TI1 Channel Configuration */ - - /* Disable the Channel 1: Reset the CC1E Bit */ - - ccer = stm32_getreg16(priv, STM32_GTIM_CCER_OFFSET); - ccer &= ~GTIM_CCER_CC1E; - stm32_putreg16(priv, STM32_GTIM_CCER_OFFSET, ccer); - - ccmr1 = stm32_getreg32(priv, STM32_GTIM_CCMR1_OFFSET); - ccer = stm32_getreg16(priv, STM32_GTIM_CCER_OFFSET); - - /* Select the Input IC1=TI1 and set the filter fSAMPLING=fDTS/4, N=6 */ - - ccmr1 &= ~(GTIM_CCMR1_CC1S_MASK | GTIM_CCMR1_IC1F_MASK); - ccmr1 |= GTIM_CCMR_CCS_CCIN1 << GTIM_CCMR1_CC1S_SHIFT; - ccmr1 |= STM32_QENCODER_ICF << GTIM_CCMR1_IC1F_SHIFT; - - /* Select the Polarity=rising and set the CC1E Bit */ - -#ifdef HAVE_GTIM_CCXNP - ccer &= ~(GTIM_CCER_CC1P | GTIM_CCER_CC1NP); -#else - ccer &= ~(GTIM_CCER_CC1P); -#endif - ccer |= GTIM_CCER_CC1E; - - /* Write to TIM CCMR1 and CCER registers */ - - stm32_putreg32(priv, STM32_GTIM_CCMR1_OFFSET, ccmr1); - stm32_putreg16(priv, STM32_GTIM_CCER_OFFSET, ccer); - - /* Set the Input Capture Prescaler value: Capture performed each time an - * edge is detected on the capture input. - */ - - ccmr1 = stm32_getreg32(priv, STM32_GTIM_CCMR1_OFFSET); - ccmr1 &= ~GTIM_CCMR1_IC1PSC_MASK; - ccmr1 |= (GTIM_CCMR_ICPSC_NOPSC << GTIM_CCMR1_IC1PSC_SHIFT); - stm32_putreg32(priv, STM32_GTIM_CCMR1_OFFSET, ccmr1); - - /* TI2 Channel Configuration */ - - /* Disable the Channel 2: Reset the CC2E Bit */ - - ccer = stm32_getreg16(priv, STM32_GTIM_CCER_OFFSET); - ccer &= ~GTIM_CCER_CC2E; - stm32_putreg16(priv, STM32_GTIM_CCER_OFFSET, ccer); - - ccmr1 = stm32_getreg32(priv, STM32_GTIM_CCMR1_OFFSET); - ccer = stm32_getreg16(priv, STM32_GTIM_CCER_OFFSET); - - /* Select the Input IC2=TI2 and set the filter fSAMPLING=fDTS/4, N=6 */ - - ccmr1 &= ~(GTIM_CCMR1_CC2S_MASK | GTIM_CCMR1_IC2F_MASK); - ccmr1 |= GTIM_CCMR_CCS_CCIN1 << GTIM_CCMR1_CC2S_SHIFT; - ccmr1 |= STM32_QENCODER_ICF << GTIM_CCMR1_IC2F_SHIFT; - - /* Select the Polarity=rising and set the CC2E Bit */ - -#ifdef HAVE_GTIM_CCXNP - ccer &= ~(GTIM_CCER_CC2P | GTIM_CCER_CC2NP); -#else - ccer &= ~(GTIM_CCER_CC2P); -#endif - ccer |= GTIM_CCER_CC2E; - - /* Write to TIM CCMR1 and CCER registers */ - - stm32_putreg32(priv, STM32_GTIM_CCMR1_OFFSET, ccmr1); - stm32_putreg16(priv, STM32_GTIM_CCER_OFFSET, ccer); - - /* Set the Input Capture Prescaler value: Capture performed each time an - * edge is detected on the capture input. - */ - - ccmr1 = stm32_getreg32(priv, STM32_GTIM_CCMR1_OFFSET); - ccmr1 &= ~GTIM_CCMR1_IC2PSC_MASK; - ccmr1 |= (GTIM_CCMR_ICPSC_NOPSC << GTIM_CCMR1_IC2PSC_SHIFT); - stm32_putreg32(priv, STM32_GTIM_CCMR1_OFFSET, ccmr1); - - /* Disable the update interrupt */ - - dier = stm32_getreg16(priv, STM32_GTIM_DIER_OFFSET); - dier &= ~GTIM_DIER_UIE; - stm32_putreg16(priv, STM32_GTIM_DIER_OFFSET, dier); - - /* There is no need for interrupts with 32-bit timers */ - -#ifndef CONFIG_STM32_QENCODER_DISABLE_EXTEND16BTIMERS -#ifdef HAVE_MIXEDWIDTH_TIMERS - if (priv->config->width != 32) -#endif - { - /* Attach the interrupt handler */ - - ret = irq_attach(priv->config->irq, stm32_interrupt, priv); - if (ret < 0) - { - stm32_shutdown(lower); - return ret; - } - - /* Enable the update/global interrupt at the NVIC */ - - up_enable_irq(priv->config->irq); - } -#endif - - /* Reset the Update Disable Bit */ - - cr1 = stm32_getreg16(priv, STM32_GTIM_CR1_OFFSET); - cr1 &= ~GTIM_CR1_UDIS; - stm32_putreg16(priv, STM32_GTIM_CR1_OFFSET, cr1); - - /* Reset the URS Bit */ - - cr1 &= ~GTIM_CR1_URS; - stm32_putreg16(priv, STM32_GTIM_CR1_OFFSET, cr1); - - /* There is no need for interrupts with 32-bit timers */ - -#ifndef CONFIG_STM32_QENCODER_DISABLE_EXTEND16BTIMERS -#ifdef HAVE_MIXEDWIDTH_TIMERS - if (priv->config->width != 32) -#endif - { - /* Clear any pending update interrupts */ - - regval = stm32_getreg16(priv, STM32_GTIM_SR_OFFSET); - stm32_putreg16(priv, STM32_GTIM_SR_OFFSET, regval & ~GTIM_SR_UIF); - - /* Then enable the update interrupt */ - - dier = stm32_getreg16(priv, STM32_GTIM_DIER_OFFSET); - dier |= GTIM_DIER_UIE; - stm32_putreg16(priv, STM32_GTIM_DIER_OFFSET, dier); - } -#endif - -#ifdef CONFIG_STM32_QENCODER_INDEX_PIN - /* At default index pin offset is 0 */ - - priv->index_offset = 0; -#endif - - /* Enable the TIM Counter */ - - cr1 = stm32_getreg16(priv, STM32_GTIM_CR1_OFFSET); - cr1 |= GTIM_CR1_CEN; - stm32_putreg16(priv, STM32_GTIM_CR1_OFFSET, cr1); - - stm32_dumpregs(priv, "After setup"); - - return OK; -} - -/**************************************************************************** - * Name: stm32_shutdown - * - * Description: - * This method is called when the driver is closed. The lower half driver - * should stop data collection, free any resources, disable timer hardware, - * and put the system into the lowest possible power usage state - * - ****************************************************************************/ - -static int stm32_shutdown(struct qe_lowerhalf_s *lower) -{ - struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; - irqstate_t flags; - uint32_t regaddr; - uint32_t regval; - uint32_t resetbit; - uint32_t pincfg; - - /* Disable the update/global interrupt at the NVIC */ - - flags = enter_critical_section(); - up_disable_irq(priv->config->irq); - - /* Detach the interrupt handler */ - - irq_detach(priv->config->irq); - - /* Disable interrupts momentary to stop any ongoing timer processing and - * to prevent any concurrent access to the reset register. - */ - - /* Disable further interrupts and stop the timer */ - - stm32_putreg16(priv, STM32_GTIM_DIER_OFFSET, 0); - stm32_putreg16(priv, STM32_GTIM_SR_OFFSET, 0); - - /* Determine which timer to reset */ - - switch (priv->config->timid) - { -#ifdef CONFIG_STM32_TIM1_QE - case 1: - regaddr = TIMRCCRST_TIM1; - resetbit = TIMRST_TIM1; - break; -#endif -#ifdef CONFIG_STM32_TIM2_QE - case 2: - regaddr = TIMRCCRST_TIM2; - resetbit = TIMRST_TIM2; - break; -#endif -#ifdef CONFIG_STM32_TIM3_QE - case 3: - regaddr = TIMRCCRST_TIM3; - resetbit = TIMRST_TIM3; - break; -#endif -#ifdef CONFIG_STM32_TIM4_QE - case 4: - regaddr = TIMRCCRST_TIM4; - resetbit = TIMRST_TIM4; - break; -#endif -#ifdef CONFIG_STM32_TIM5_QE - case 5: - regaddr = TIMRCCRST_TIM5; - resetbit = TIMRST_TIM5; - break; -#endif -#ifdef CONFIG_STM32_TIM8_QE - case 8: - regaddr = TIMRCCRST_TIM8; - resetbit = TIMRST_TIM8; - break; -#endif - default: - leave_critical_section(flags); - return -EINVAL; - } - - /* Reset the timer - stopping the output and putting the timer back - * into a state where stm32_start() can be called. - */ - - regval = getreg32(regaddr); - regval |= resetbit; - putreg32(regval, regaddr); - - regval &= ~resetbit; - putreg32(regval, regaddr); - leave_critical_section(flags); - - sninfo("regaddr: %08" PRIx32 " resetbit: %08" PRIx32 "\n", - regaddr, resetbit); - - stm32_dumpregs(priv, "After stop"); - - /* Disable clocking to the timer */ - - modifyreg32(priv->config->regaddr, priv->config->enable, 0); - - /* Put the TI1 GPIO pin back to its default state */ - - pincfg = priv->config->ti1cfg & (GPIO_PORT_MASK | GPIO_PIN_MASK); - pincfg |= STM32_GPIO_INPUT_FLOAT; - - stm32_configgpio(pincfg); - - /* Put the TI2 GPIO pin back to its default state */ - - pincfg = priv->config->ti2cfg & (GPIO_PORT_MASK | GPIO_PIN_MASK); - pincfg |= STM32_GPIO_INPUT_FLOAT; - - stm32_configgpio(pincfg); - return OK; -} - -/**************************************************************************** - * Name: stm32_position - * - * Description: - * Return the current position measurement. - * - ****************************************************************************/ - -static int stm32_position(struct qe_lowerhalf_s *lower, int32_t *pos) -{ - struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; -#ifndef CONFIG_STM32_QENCODER_DISABLE_EXTEND16BTIMERS - irqstate_t flags; - int32_t position; - int32_t verify; - uint32_t count; - - DEBUGASSERT(lower && priv->inuse); - - /* Loop until we are certain that no interrupt occurred between samples */ - - flags = spin_lock_irqsave(&priv->lock); - do - { - position = priv->position; - count = stm32_getreg32(priv, STM32_GTIM_CNT_OFFSET); - verify = priv->position; - } - while (position != verify); - spin_unlock_irqrestore(&priv->lock, flags); - - /* Return the position measurement */ - - *pos = position + (int32_t)count; -#else - /* Return the counter value */ - -# if defined(HAVE_32BIT_TIMERS) - *pos = (int32_t)stm32_getreg32(priv, STM32_GTIM_CNT_OFFSET); -# else - *pos = (int32_t)stm32_getreg16(priv, STM32_GTIM_CNT_OFFSET); -# endif -#endif - return OK; -} - -/**************************************************************************** - * Name: stm32_setposmax - * - * Description: - * Set the maximum encoder position. - * - ****************************************************************************/ - -static int stm32_setposmax(struct qe_lowerhalf_s *lower, uint32_t pos) -{ -#ifdef CONFIG_STM32_QENCODER_DISABLE_EXTEND16BTIMERS - struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; - -#if defined(HAVE_MIXEDWIDTH_TIMERS) - if (priv->config->width == 32) - { - stm32_putreg32(priv, STM32_GTIM_ARR_OFFSET, pos); - } - else - { - stm32_putreg16(priv, STM32_GTIM_ARR_OFFSET, pos); - } -#elif defined(HAVE_32BIT_TIMERS) - stm32_putreg32(priv, STM32_GTIM_ARR_OFFSET, pos); -#else - stm32_putreg16(priv, STM32_GTIM_ARR_OFFSET, pos); -#endif - - return OK; -#else - return -ENOTTY; -#endif -} - -/**************************************************************************** - * Name: stm32_reset - * - * Description: - * Reset the position measurement to zero. - * - ****************************************************************************/ - -static int stm32_reset(struct qe_lowerhalf_s *lower) -{ - struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; -#ifndef CONFIG_STM32_QENCODER_DISABLE_EXTEND16BTIMERS - irqstate_t flags; - - sninfo("Resetting position to zero\n"); - DEBUGASSERT(lower && priv->inuse); - - /* Reset the timer and the counter. Interrupts are disabled to make this - * atomic (if possible) - */ - - flags = enter_critical_section(); - stm32_putreg32(priv, STM32_GTIM_CNT_OFFSET, 0); - priv->position = 0; - leave_critical_section(flags); -#else - sninfo("Resetting position to zero\n"); - DEBUGASSERT(lower && priv->inuse); - - /* Reset the counter to zero */ - - stm32_putreg32(priv, STM32_GTIM_CNT_OFFSET, 0); -#endif - return OK; -} - -/**************************************************************************** - * Name: stm32_setindex - * - * Description: - * Set the index pin position - * - ****************************************************************************/ - -static int stm32_setindex(struct qe_lowerhalf_s *lower, uint32_t pos) -{ -#ifdef CONFIG_STM32_QENCODER_INDEX_PIN - struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; - int ret = OK; - - sninfo("Set QE TIM%d the index pin position %" PRIx32 "\n", - priv->config->timid, pos); - DEBUGASSERT(lower && priv->inuse); - - /* Only if index pin configured */ - - if (priv->index_use == false) - { - snerr("ERROR: QE TIM%d index not registered\n", - priv->config->timid); - ret = -EPERM; - goto errout; - } - - priv->index_offset = pos; - -errout: - return ret; -#else - return -ENOTTY; -#endif -} - -/**************************************************************************** - * Name: stm32_ioctl - * - * Description: - * Lower-half logic may support platform-specific ioctl commands - * - ****************************************************************************/ - -static int stm32_ioctl(struct qe_lowerhalf_s *lower, int cmd, - unsigned long arg) -{ - /* No ioctl commands supported */ - - /* TODO add an IOCTL to control the encoder pulse count prescaler */ - - return -ENOTTY; -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_qeinitialize - * - * Description: - * Initialize a quadrature encoder interface. This function must be - * called from board-specific logic. - * - * Input Parameters: - * devpath - The full path to the driver to register. E.g., "/dev/qe0" - * tim - The timer number to used. 'tim' must be an element of - * {1,2,3,4,5,8} - * - * Returned Value: - * Zero on success; A negated errno value is returned on failure. - * - ****************************************************************************/ - -int stm32_qeinitialize(const char *devpath, int tim) -{ - struct stm32_lowerhalf_s *priv; - int ret; - - /* Find the pre-allocated timer state structure corresponding to this - * timer - */ - - priv = stm32_tim2lower(tim); - if (!priv) - { - snerr("ERROR: TIM%d support not configured\n", tim); - return -ENXIO; - } - - /* Make sure that it is available */ - - if (priv->inuse) - { - snerr("ERROR: TIM%d is in-use\n", tim); - return -EBUSY; - } - - /* Register the upper-half driver */ - - ret = qe_register(devpath, (struct qe_lowerhalf_s *)priv); - if (ret < 0) - { - snerr("ERROR: qe_register failed: %d\n", ret); - return ret; - } - - /* Make sure that the timer is in the shutdown state */ - - stm32_shutdown((struct qe_lowerhalf_s *)priv); - - /* The driver is now in-use */ - - priv->inuse = true; - return OK; -} - -#ifdef CONFIG_STM32_QENCODER_INDEX_PIN -/**************************************************************************** - * Name: stm32_qe_index_init - * - * Description: - * Register the encoder index pin to a given Qencoder timer - * - * Input Parameters: - * tim - The qenco timer number - * gpio - gpio pin configuration - * - * Returned Value: - * Zero on success; A negated errno value is returned on failure. - * - ****************************************************************************/ - -int stm32_qe_index_init(int tim, uint32_t gpio) -{ - struct stm32_lowerhalf_s *priv; - int ret = OK; - - /* Find the pre-allocated timer state structure corresponding to this - * timer - */ - - priv = stm32_tim2lower(tim); - if (!priv) - { - snerr("ERROR: TIM%d support not configured\n", tim); - return -ENXIO; - } - - /* Make sure that it is available */ - - if (priv->inuse == false) - { - snerr("ERROR: TIM%d is not in-use\n", tim); - ret = -EINVAL; - } - - /* Configure QE index pin */ - - priv->index_pin = gpio; - stm32_configgpio(priv->index_pin); - - /* Register interrupt */ - - ret = stm32_gpiosetevent(gpio, true, false, true, - stm32_qe_index_irq, priv); - if (ret < 0) - { - snerr("ERROR: QE TIM%d failed register irq\n", tim); - goto errout; - } - - /* Set flag */ - - priv->index_use = true; - -errout: - return ret; -} -#endif - -#endif /* CONFIG_SENSORS_QENCODER */ diff --git a/arch/arm/src/stm32/stm32_qencoder.h b/arch/arm/src/stm32/stm32_qencoder.h deleted file mode 100644 index a8c9ff66e002c..0000000000000 --- a/arch/arm/src/stm32/stm32_qencoder.h +++ /dev/null @@ -1,121 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_qencoder.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32_STM32_QENCODER_H -#define __ARCH_ARM_SRC_STM32_STM32_QENCODER_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "chip.h" - -#ifdef CONFIG_SENSORS_QENCODER - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -/* Timer devices may be used for different purposes. One special purpose is - * as a quadrature encoder input device. If CONFIG_STM32_TIMn is defined - * then the CONFIG_STM32_TIMn_QE must also be defined to indicate that timer - * "n" is intended to be used for as a quadrature encoder. - */ - -#ifndef CONFIG_STM32_TIM1 -# undef CONFIG_STM32_TIM1_QE -#endif -#ifndef CONFIG_STM32_TIM2 -# undef CONFIG_STM32_TIM2_QE -#endif -#ifndef CONFIG_STM32_TIM3 -# undef CONFIG_STM32_TIM3_QE -#endif -#ifndef CONFIG_STM32_TIM4 -# undef CONFIG_STM32_TIM4_QE -#endif -#ifndef CONFIG_STM32_TIM5 -# undef CONFIG_STM32_TIM5_QE -#endif -#ifndef CONFIG_STM32_TIM8 -# undef CONFIG_STM32_TIM8_QE -#endif - -/* Only timers 2-5, and 1 & 8 can be used as a quadrature encoder (at least - * for the STM32 F4) - */ - -#undef CONFIG_STM32_TIM6_QE -#undef CONFIG_STM32_TIM7_QE -#undef CONFIG_STM32_TIM9_QE -#undef CONFIG_STM32_TIM10_QE -#undef CONFIG_STM32_TIM11_QE -#undef CONFIG_STM32_TIM12_QE -#undef CONFIG_STM32_TIM13_QE -#undef CONFIG_STM32_TIM14_QE - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_qeinitialize - * - * Description: - * Initialize a quadrature encoder interface. This function must be called - * from board-specific logic.. - * - * Input Parameters: - * devpath - The full path to the driver to register. E.g., "/dev/qe0" - * tim - The timer number to used. 'tim' must be an element of - * {1,2,3,4,5,8} - * - * Returned Value: - * Zero on success; A negated errno value is returned on failure. - * - ****************************************************************************/ - -int stm32_qeinitialize(const char *devpath, int tim); - -#ifdef CONFIG_STM32_QENCODER_INDEX_PIN -/**************************************************************************** - * Name: stm32_qe_index_init - * - * Description: - * Register the encoder index pin to a given Qencoder timer - * - * Input Parameters: - * tim - The qenco timer number - * gpio - gpio pin configuration - * - * Returned Value: - * Zero on success; A negated errno value is returned on failure. - * - ****************************************************************************/ - -int stm32_qe_index_init(int tim, uint32_t gpio); -#endif - -#endif /* CONFIG_SENSORS_QENCODER */ -#endif /* __ARCH_ARM_SRC_STM32_STM32_QENCODER_H */ diff --git a/arch/arm/src/stm32/stm32_rcc.c b/arch/arm/src/stm32/stm32_rcc.c deleted file mode 100644 index 5d1c3715b6aaf..0000000000000 --- a/arch/arm/src/stm32/stm32_rcc.c +++ /dev/null @@ -1,252 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_rcc.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include - -#include - -#include "arm_internal.h" -#include "chip.h" -#include "stm32_gpio.h" -#include "stm32_rcc.h" -#include "stm32_rtc.h" -#include "stm32_flash.h" -#include "stm32.h" -#include "stm32_waste.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1, - "Configure BOARD_LOOPSPERMSEC to non-default value."); - -/* Allow up to 100 milliseconds for the high speed clock to become ready. - * that is a very long delay, but if the clock does not become ready we are - * hosed anyway. - */ - -#define HSERDY_TIMEOUT (100 * CONFIG_BOARD_LOOPSPERMSEC) - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -/* Include chip-specific clocking initialization logic */ - -#if defined(CONFIG_STM32_STM32L15XX) -# include "stm32l15xxx_rcc.c" -#elif defined(CONFIG_STM32_STM32F10XX) -# include "stm32f10xxx_rcc.c" -#elif defined(CONFIG_STM32_STM32F20XX) -# include "stm32f20xxx_rcc.c" -#elif defined(CONFIG_STM32_STM32F30XX) -# include "stm32f30xxx_rcc.c" -#elif defined(CONFIG_STM32_STM32F33XX) -# include "stm32f33xxx_rcc.c" -#elif defined(CONFIG_STM32_STM32F37XX) -# include "stm32f37xxx_rcc.c" -#elif defined(CONFIG_STM32_STM32F4XXX) -# include "stm32f40xxx_rcc.c" -#elif defined(CONFIG_STM32_STM32G4XXX) -# include "stm32g4xxxx_rcc.c" -#else -# error "Unsupported STM32 chip" -#endif - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#if defined(CONFIG_STM32_STM32L15XX) -# define STM32_RCC_XXX STM32_RCC_CSR -# define RCC_XXX_YYYRST RCC_CSR_RTCRST -#else -# define STM32_RCC_XXX STM32_RCC_BDCR -# define RCC_XXX_YYYRST RCC_BDCR_BDRST -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: rcc_resetbkp - * - * Description: - * The RTC needs to reset the Backup Domain to change RTCSEL and resetting - * the Backup Domain renders to disabling the LSE as consequence. - * In order to avoid resetting the Backup Domain when we already - * configured LSE we will reset the Backup Domain early (here). - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -#if defined(CONFIG_STM32_RTC) && defined(CONFIG_STM32_PWR) && !defined(CONFIG_STM32_STM32F10XX) -static inline void rcc_resetbkp(void) -{ - uint32_t regval; - - /* Check if the RTC is already configured */ - - stm32_pwr_initbkp(false); - - regval = getreg32(RTC_MAGIC_REG); - if (regval != RTC_MAGIC && regval != RTC_MAGIC_TIME_SET) - { - stm32_pwr_enablebkp(true); - - /* We might be changing RTCSEL - to ensure such changes work, we must - * reset the backup domain (having backed up the RTC_MAGIC token) - */ - - modifyreg32(STM32_RCC_XXX, 0, RCC_XXX_YYYRST); - modifyreg32(STM32_RCC_XXX, RCC_XXX_YYYRST, 0); - - stm32_pwr_enablebkp(false); - } -} -#else -# define rcc_resetbkp() -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_clockconfig - * - * Description: - * Called to establish the clock settings based on the values in board.h. - * This function (by default) will reset most everything, enable the PLL, - * and enable peripheral clocking for all peripherals enabled in the NuttX - * configuration file. - * - * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then clocking - * will be enabled by an externally provided, board-specific function - * called stm32_board_clockconfig(). - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -void stm32_clockconfig(void) -{ - /* Make sure that we are starting in the reset state */ - - rcc_reset(); - - /* Reset backup domain if appropriate */ - - rcc_resetbkp(); - -#if defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) - - /* Invoke Board Custom Clock Configuration */ - - stm32_board_clockconfig(); - -#else - - /* Invoke standard, fixed clock configuration based on definitions - * in board.h - */ - - stm32_stdclockconfig(); - -#endif - - /* Enable peripheral clocking */ - - rcc_enableperipherals(); - -#ifdef CONFIG_STM32_SYSCFG_IOCOMPENSATION - /* Enable I/O Compensation */ - - stm32_iocompensation(); -#endif -} - -/**************************************************************************** - * Name: stm32_clockenable - * - * Description: - * Re-enable the clock and restore the clock settings based on settings - * in board.h. This function is only available to support low-power - * modes of operation: When re-awakening from deep-sleep modes, it is - * necessary to re-enable/re-start the PLL - * - * This functional performs a subset of the operations performed by - * stm32_clockconfig(): It does not reset any devices, and it does not - * reset the currently enabled peripheral clocks. - * - * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then clocking - * will be enabled by an externally provided, board-specific function - * called stm32_board_clockconfig(). - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef CONFIG_PM -void stm32_clockenable(void) -{ -#if defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) - - /* Invoke Board Custom Clock Configuration */ - - stm32_board_clockconfig(); - -#else - - /* Invoke standard, fixed clock configuration based on definitions - * in board.h - */ - - stm32_stdclockconfig(); - -#endif -} -#endif diff --git a/arch/arm/src/stm32/stm32_rcc.h b/arch/arm/src/stm32/stm32_rcc.h deleted file mode 100644 index cfead6ee3e43b..0000000000000 --- a/arch/arm/src/stm32/stm32_rcc.h +++ /dev/null @@ -1,321 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_rcc.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32_STM32_RCC_H -#define __ARCH_ARM_SRC_STM32_STM32_RCC_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "arm_internal.h" -#include "chip.h" - -#if defined(CONFIG_STM32_STM32L15XX) -# include "hardware/stm32l15xxx_rcc.h" -#elif defined(CONFIG_STM32_STM32F10XX) -# include "hardware/stm32f10xxx_rcc.h" -#elif defined(CONFIG_STM32_STM32F20XX) -# include "hardware/stm32f20xxx_rcc.h" -#elif defined(CONFIG_STM32_STM32F30XX) -# include "hardware/stm32f30xxx_rcc.h" -#elif defined(CONFIG_STM32_STM32F33XX) -# include "hardware/stm32f33xxx_rcc.h" -#elif defined(CONFIG_STM32_STM32F37XX) -# include "hardware/stm32f37xxx_rcc.h" -#elif defined(CONFIG_STM32_STM32F4XXX) -# include "hardware/stm32f40xxx_rcc.h" -#elif defined(CONFIG_STM32_STM32G4XXX) -# include "hardware/stm32g4xxxx_rcc.h" -#else -# error "Unsupported STM32 chip" -#endif - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#ifndef __ASSEMBLY__ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Inline Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_mco1config - * - * Description: - * Selects the clock source to output on MCO1 pin (PA8). PA8 should be - * configured in alternate function mode. - * - * Input Parameters: - * source - One of the definitions for the RCC_CFGR_MCO1 definitions from - * chip/stm32f4xxxx_rcc.h {RCC_CFGR_MCO1_HSI, RCC_CFGR_MCO1_LSE, - * RCC_CFGR_MCO1_HSE, RCC_CFGR_MCO1_PLL} - * div - One of the definitions for the RCC_CFGR_MCO1PRE definitions from - * chip/stm32f4xxxx_rcc.h {RCC_CFGR_MCO1PRE_NONE, RCC_CFGR_MCO1PRE_DIV2, - * RCC_CFGR_MCO1PRE_DIV3, RCC_CFGR_MCO1PRE_DIV4, RCC_CFGR_MCO1PRE_DIV5} - * - * Returned Value: - * None - * - ****************************************************************************/ - -#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) -static inline void stm32_mco1config(uint32_t source, uint32_t div) -{ - uint32_t regval; - - regval = getreg32(STM32_RCC_CFGR); - regval &= ~(RCC_CFGR_MCO1_MASK | RCC_CFGR_MCO1PRE_MASK); - regval |= (source | div); - putreg32(regval, STM32_RCC_CFGR); -} -#endif - -/**************************************************************************** - * Name: stm32_mcoconfig - * - * Description: - * Selects the clock source to output on MC pin (PA8) for stm32f10xxx. - * PA8 should be configured in alternate function mode. - * - * Input Parameters: - * source - One of the definitions for the RCC_CFGR_MCO definitions from - * chip/stm32f10xxx_rcc.h {RCC_CFGR_SYSCLK, RCC_CFGR_INTCLK, - * RCC_CFGR_EXTCLK, RCC_CFGR_PLLCLKd2, RCC_CFGR_PLL2CLK, - * RCC_CFGR_PLL3CLKd2, RCC_CFGR_XT1, RCC_CFGR_PLL3CLK} - * - * Returned Value: - * None - * - ****************************************************************************/ - -#if defined(CONFIG_STM32_CONNECTIVITYLINE) -static inline void stm32_mcoconfig(uint32_t source) -{ - uint32_t regval; - - /* Set MCO source */ - - regval = getreg32(STM32_RCC_CFGR); - regval &= ~(RCC_CFGR_MCO_MASK); - regval |= (source & RCC_CFGR_MCO_MASK); - putreg32(regval, STM32_RCC_CFGR); -} -#endif - -/**************************************************************************** - * Name: stm32_mcodivconfig - * - * Description: - * Selects the clock source to output and clock divider on MC pin (PA4) for - * stm32l1xxx. PA4 should be configured in alternate function mode. - * - * Input Parameters: - * source - One of the definitions for the RCC_CFGR_MCOSEL definitions - * from chip/stm32l15xxx_rcc.h - * {RCC_CFGR_MCOSEL_DISABLED, RCC_CFGR_MCOSEL_SYSCLK, - * RCC_CFGR_MCOSEL_HSICLK, RCC_CFGR_MCOSEL_MSICLK, - * RCC_CFGR_MCOSEL_HSECLK, RCC_CFGR_MCOSEL_PLLCLK, - * RCC_CFGR_MCOSEL_LSICLK, RCC_CFGR_MCOSEL_LSECLK} - * divider - One of the definitions for the RCC_CFGR_MCOPRE definitions - * from chip/stm32l15xxx_rcc.h - * {RCC_CFGR_MCOPRE_DIV1, RCC_CFGR_MCOPRE_DIV2, - * RCC_CFGR_MCOPRE_DIV4, RCC_CFGR_MCOPRE_DIV8, RCC_CFGR_MCOPRE_DIV16} - * - * Returned Value: - * None - * - ****************************************************************************/ - -#if defined(CONFIG_STM32_STM32L15XX) -static inline void stm32_mcodivconfig(uint32_t source, uint32_t divider) -{ - uint32_t regval; - - /* Set MCO source */ - - regval = getreg32(STM32_RCC_CFGR); - regval &= ~(RCC_CFGR_MCOSEL_MASK); - regval |= (source & RCC_CFGR_MCOSEL_MASK); - regval &= ~(RCC_CFGR_MCOPRE_MASK); - regval |= (divider & RCC_CFGR_MCOPRE_MASK); - putreg32(regval, STM32_RCC_CFGR); -} -#endif - -/**************************************************************************** - * Name: stm32_mco2config - * - * Description: - * Selects the clock source to output on MCO2 pin (PC9). PC9 should be - * configured in alternate function mode. - * - * Input Parameters: - * source - One of the definitions for the RCC_CFGR_MCO2 definitions from - * chip/stm32f4xxxx_rcc.h {RCC_CFGR_MCO2_SYSCLK, RCC_CFGR_MCO2_PLLI2S, - * RCC_CFGR_MCO2_HSE, RCC_CFGR_MCO2_PLL} - * div - One of the definitions for the RCC_CFGR_MCO2PRE definitions from - * chip/stm32f4xxxx_rcc.h {RCC_CFGR_MCO2PRE_NONE, RCC_CFGR_MCO2PRE_DIV2, - * RCC_CFGR_MCO2PRE_DIV3, RCC_CFGR_MCO2PRE_DIV4, RCC_CFGR_MCO2PRE_DIV5} - * - * Returned Value: - * None - * - ****************************************************************************/ - -#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) -static inline void stm32_mco2config(uint32_t source, uint32_t div) -{ - uint32_t regval; - - regval = getreg32(STM32_RCC_CFGR); - regval &= ~(RCC_CFGR_MCO2_MASK | RCC_CFGR_MCO2PRE_MASK); - regval |= (source | div); - putreg32(regval, STM32_RCC_CFGR); -} -#endif - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_clockconfig - * - * Description: - * Called to establish the clock settings based on the values in board.h. - * This function (by default) will reset most everything, enable the PLL, - * and enable peripheral clocking for all periperipherals enabled in the - * NuttX configuration file. - * - * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then clocking - * will be enabled by an externally provided, board-specific function - * called stm32_board_clockconfig(). - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -void stm32_clockconfig(void); - -/**************************************************************************** - * Name: stm32_board_clockconfig - * - * Description: - * Any STM32 board may replace the "standard" board clock configuration - * logic with its own, custom clock configuration logic. - * - ****************************************************************************/ - -#ifdef CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG -void stm32_board_clockconfig(void); -#endif - -/**************************************************************************** - * Name: stm32_clockenable - * - * Description: - * Re-enable the clock and restore the clock settings based on settings in - * board.h. - * This function is only available to support low-power modes of operation: - * When re-awakening from deep-sleep modes, it is necessary to re-enable/ - * re-start the PLL - * - * This functional performs a subset of the operations performed by - * stm32_clockconfig(): It does not reset any devices, and it does not - * reset the currently enabled peripheral clocks. - * - * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then clocking - * will be enabled by an externally provided, board-specific function - * called stm32_board_clockconfig(). - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef CONFIG_PM -void stm32_clockenable(void); -#endif - -/**************************************************************************** - * Name: stm32_rcc_enablelse - * - * Description: - * Enable the External Low-Speed (LSE) Oscillator. - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -void stm32_rcc_enablelse(void); - -/**************************************************************************** - * Name: stm32_rcc_enablelsi - * - * Description: - * Enable the Internal Low-Speed (LSI) RC Oscillator. - * - ****************************************************************************/ - -void stm32_rcc_enablelsi(void); - -/**************************************************************************** - * Name: stm32_rcc_disablelsi - * - * Description: - * Disable the Internal Low-Speed (LSI) RC Oscillator. - * - ****************************************************************************/ - -void stm32_rcc_disablelsi(void); - -#undef EXTERN -#if defined(__cplusplus) -} -#endif -#endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32_STM32_RCC_H */ diff --git a/arch/arm/src/stm32/stm32_rng.c b/arch/arm/src/stm32/stm32_rng.c deleted file mode 100644 index 9a4c46aaa0bef..0000000000000 --- a/arch/arm/src/stm32/stm32_rng.c +++ /dev/null @@ -1,314 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_rng.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include - -#include "hardware/stm32_rng.h" -#include "arm_internal.h" - -#if defined(CONFIG_STM32_RNG) -#if defined(CONFIG_DEV_RANDOM) || defined(CONFIG_DEV_URANDOM_ARCH) - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -static int stm32_rng_initialize(void); -static int stm32_rng_interrupt(int irq, void *context, void *arg); -static void stm32_rng_enable(void); -static void stm32_rng_disable(void); -static ssize_t stm32_rng_read(struct file *filep, char *buffer, size_t); - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -struct rng_dev_s -{ - mutex_t rd_devlock; /* Threads can only exclusively access the RNG */ - sem_t rd_readsem; /* To block until the buffer is filled */ - char *rd_buf; - size_t rd_buflen; - uint32_t rd_lastval; - bool rd_first; -}; - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -static struct rng_dev_s g_rngdev = -{ - .rd_devlock = NXMUTEX_INITIALIZER, - .rd_readsem = SEM_INITIALIZER(0), -}; - -static const struct file_operations g_rngops = -{ - NULL, /* open */ - NULL, /* close */ - stm32_rng_read, /* read */ -}; - -/**************************************************************************** - * Private functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_rng_initialize - ****************************************************************************/ - -static int stm32_rng_initialize(void) -{ - uint32_t regval; - - _info("Initializing RNG\n"); - - if (irq_attach(STM32_IRQ_RNG, stm32_rng_interrupt, NULL)) - { - /* We could not attach the ISR to the interrupt */ - - _info("Could not attach IRQ.\n"); - - return -EAGAIN; - } - - /* Enable interrupts */ - - regval = getreg32(STM32_RNG_CR); - regval |= RNG_CR_IE; - putreg32(regval, STM32_RNG_CR); - - up_enable_irq(STM32_IRQ_RNG); - - return OK; -} - -/**************************************************************************** - * Name: stm32_rng_enable - ****************************************************************************/ - -static void stm32_rng_enable(void) -{ - uint32_t regval; - - g_rngdev.rd_first = true; - - regval = getreg32(STM32_RNG_CR); - regval |= RNG_CR_RNGEN; - putreg32(regval, STM32_RNG_CR); -} - -/**************************************************************************** - * Name: stm32_rng_disable - ****************************************************************************/ - -static void stm32_rng_disable(void) -{ - uint32_t regval; - regval = getreg32(STM32_RNG_CR); - regval &= ~RNG_CR_RNGEN; - putreg32(regval, STM32_RNG_CR); -} - -/**************************************************************************** - * Name: stm32_rng_interrupt - ****************************************************************************/ - -static int stm32_rng_interrupt(int irq, void *context, void *arg) -{ - uint32_t rngsr; - uint32_t data; - - rngsr = getreg32(STM32_RNG_SR); - - if ((rngsr & (RNG_SR_SEIS | RNG_SR_CEIS)) /* Check for error bits */ - || !(rngsr & RNG_SR_DRDY)) /* Data ready must be set */ - { - /* This random value is not valid, we will try again. */ - - return OK; - } - - data = getreg32(STM32_RNG_DR); - - /* As required by the FIPS PUB (Federal Information Processing Standard - * Publication) 140-2, the first random number generated after setting the - * RNGEN bit should not be used, but saved for comparison with the next - * generated random number. Each subsequent generated random number has to - * be compared with the previously generated number. The test fails if any - * two compared numbers are equal (continuous random number generator - * test). - */ - - if (g_rngdev.rd_first) - { - g_rngdev.rd_first = false; - g_rngdev.rd_lastval = data; - return OK; - } - - if (g_rngdev.rd_lastval == data) - { - /* Two subsequent same numbers, we will try again. */ - - return OK; - } - - /* If we get here, the random number is valid. */ - - g_rngdev.rd_lastval = data; - - if (g_rngdev.rd_buflen >= 4) - { - g_rngdev.rd_buflen -= 4; - *(uint32_t *)&g_rngdev.rd_buf[g_rngdev.rd_buflen] = data; - } - else - { - while (g_rngdev.rd_buflen > 0) - { - g_rngdev.rd_buf[--g_rngdev.rd_buflen] = (char)data; - data >>= 8; - } - } - - if (g_rngdev.rd_buflen == 0) - { - /* Buffer filled, stop further interrupts. */ - - stm32_rng_disable(); - nxsem_post(&g_rngdev.rd_readsem); - } - - return OK; -} - -/**************************************************************************** - * Name: stm32_rng_read - ****************************************************************************/ - -static ssize_t stm32_rng_read(struct file *filep, char *buffer, - size_t buflen) -{ - int ret; - - ret = nxmutex_lock(&g_rngdev.rd_devlock); - if (ret < 0) - { - return ret; - } - - /* We've got the mutex. */ - - /* Reset the operation semaphore with 0 for blocking until the - * buffer is filled from interrupts. - */ - - nxsem_reset(&g_rngdev.rd_readsem, 0); - - g_rngdev.rd_buflen = buflen; - g_rngdev.rd_buf = buffer; - - /* Enable RNG with interrupts */ - - stm32_rng_enable(); - - /* Wait until the buffer is filled */ - - ret = nxsem_wait(&g_rngdev.rd_readsem); - - /* Free RNG for next use */ - - nxmutex_unlock(&g_rngdev.rd_devlock); - return ret < 0 ? ret : buflen; -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: devrandom_register - * - * Description: - * Initialize the RNG hardware and register the /dev/random driver. - * Must be called BEFORE devurandom_register. - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef CONFIG_DEV_RANDOM -void devrandom_register(void) -{ - stm32_rng_initialize(); - register_driver("/dev/random", &g_rngops, 0444, NULL); -} -#endif - -/**************************************************************************** - * Name: devurandom_register - * - * Description: - * Register /dev/urandom - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef CONFIG_DEV_URANDOM_ARCH -void devurandom_register(void) -{ -#ifndef CONFIG_DEV_RANDOM - stm32_rng_initialize(); -#endif - register_driver("/dev/urandom", &g_rngops, 0444, NULL); -} -#endif - -#endif /* CONFIG_DEV_RANDOM || CONFIG_DEV_URANDOM_ARCH */ -#endif /* CONFIG_STM32_RNG */ diff --git a/arch/arm/src/stm32/stm32_rtc.c b/arch/arm/src/stm32/stm32_rtc.c deleted file mode 100644 index 7d191c9882517..0000000000000 --- a/arch/arm/src/stm32/stm32_rtc.c +++ /dev/null @@ -1,61 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_rtc.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "chip.h" - -/* This file is only a thin shell that includes the correct RTC - * implementation for the selected STM32 family. The correct file cannot be - * selected by the make system because it needs the intelligence that only - * exists in chip.h that can associate an STM32 part number with an STM32 - * family. - */ - -/* The STM32 F1 has a simple battery-backed counter for its RTC and has a - * separate block for the BKP registers. - */ - -#if defined(CONFIG_STM32_STM32F10XX) -# include "stm32_rtcounter.c" - -/* The other families use a more traditional Realtime Clock/Calendar (RTCC) - * with broken-out data/time in BCD format. The backup registers are - * integrated into the RTCC in these families. - */ - -#elif defined(CONFIG_STM32_STM32F20XX) || \ - defined(CONFIG_STM32_STM32F30XX) -# include "stm32_rtcc.c" -#elif defined(CONFIG_STM32_STM32L15XX) -# include "stm32l15xxx_rtcc.c" -#elif defined(CONFIG_STM32_STM32F4XXX) -# include "stm32f40xxx_rtcc.c" -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ diff --git a/arch/arm/src/stm32/stm32_rtc.h b/arch/arm/src/stm32/stm32_rtc.h deleted file mode 100644 index 3df1ac02a7b3d..0000000000000 --- a/arch/arm/src/stm32/stm32_rtc.h +++ /dev/null @@ -1,225 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_rtc.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32_STM32_RTC_H -#define __ARCH_ARM_SRC_STM32_STM32_RTC_H - -#include - -#include "chip.h" - -/* The STM32 F1 has a simple battery-backed counter for its RTC and has a - * separate block for the BKP registers. - */ - -#if defined(CONFIG_STM32_STM32F10XX) -# include "hardware/stm32_rtc.h" -# include "hardware/stm32_bkp.h" - -/* The other families use a more traditional Realtime Clock/Calendar (RTCC) - * with broken-out data/time in BCD format. The backup registers are - * integrated into the RTCC in these families. - */ - -#elif defined(CONFIG_STM32_STM32L15XX) || defined(CONFIG_STM32_STM32F20XX) || \ - defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F4XXX) -# include "hardware/stm32_rtcc.h" -#endif - -/* Alarm function differs from part to part */ - -#if defined(CONFIG_STM32_STM32F4XXX) -# include "stm32f40xxx_alarm.h" -#elif defined(CONFIG_STM32_STM32L15XX) -# include "stm32l15xxx_alarm.h" -#else -# include "stm32_alarm.h" -#endif - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#define STM32_RTC_PRESCALER_SECOND 32767 /* Default prescaler to get a - * second base */ -#define STM32_RTC_PRESCALER_MIN 1 /* Maximum speed of 16384 Hz */ - -#if defined(CONFIG_STM32_STM32F10XX) -/* RTC is only a counter, store RTC data in backup domain register DR1 (if - * CONFIG_RTC_HIRES) and DR2 (state). - */ - -#if !defined(CONFIG_STM32_RTC_MAGIC) -# define CONFIG_STM32_RTC_MAGIC (0xface) /* only 16 bit */ -#endif - -#if !defined(CONFIG_STM32_RTC_MAGIC_TIME_SET) -# define CONFIG_STM32_RTC_MAGIC_TIME_SET (0xf00d) -#endif - -#define RTC_MAGIC_REG STM32_BKP_DR2 - -#else /* !CONFIG_STM32_STM32F10XX */ - -#if !defined(CONFIG_STM32_RTC_MAGIC) -# define CONFIG_STM32_RTC_MAGIC (0xfacefeed) -#endif - -#if !defined(CONFIG_STM32_RTC_MAGIC_TIME_SET) -# define CONFIG_STM32_RTC_MAGIC_TIME_SET (0xf00dface) -#endif - -#if !defined(CONFIG_STM32_RTC_MAGIC_REG) -# define CONFIG_STM32_RTC_MAGIC_REG (0) -#endif - -#define RTC_MAGIC_REG STM32_RTC_BKR(CONFIG_STM32_RTC_MAGIC_REG) - -#endif /* CONFIG_STM32_STM32F10XX */ - -#define RTC_MAGIC CONFIG_STM32_RTC_MAGIC -#define RTC_MAGIC_TIME_SET CONFIG_STM32_RTC_MAGIC_TIME_SET - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -#ifndef __ASSEMBLY__ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_rtc_irqinitialize - * - * Description: - * Initialize IRQs for RTC, not possible during up_rtc_initialize because - * up_irqinitialize is called later. - * - * Input Parameters: - * None - * - * Returned Value: - * Zero (OK) on success; a negated errno on failure - * - ****************************************************************************/ - -int stm32_rtc_irqinitialize(void); - -/**************************************************************************** - * Name: stm32_rtc_getdatetime_with_subseconds - * - * Description: - * Get the current date and time from the date/time RTC. This interface - * is only supported by the date/time RTC hardware implementation. - * It is used to replace the system timer. It is only used by the RTOS - * during initialization to set up the system time when CONFIG_RTC and - * CONFIG_RTC_DATETIME are selected (and CONFIG_RTC_HIRES is not). - * - * NOTE: Some date/time RTC hardware is capability of sub-second accuracy. - * Thatsub-second accuracy is returned through 'nsec'. - * - * Input Parameters: - * tp - The location to return the high resolution time value. - * nsec - The location to return the subsecond time value. - * - * Returned Value: - * Zero (OK) on success; a negated errno on failure - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_HAVE_RTC_SUBSECONDS -int stm32_rtc_getdatetime_with_subseconds(struct tm *tp, long *nsec); -#endif - -/**************************************************************************** - * Name: stm32_rtc_setdatetime - * - * Description: - * Set the RTC to the provided time. RTC implementations which provide - * up_rtc_getdatetime() (CONFIG_RTC_DATETIME is selected) should provide - * this function. - * - * Input Parameters: - * tp - the time to use - * - * Returned Value: - * Zero (OK) on success; a negated errno on failure - * - ****************************************************************************/ - -#ifdef CONFIG_RTC_DATETIME -struct tm; -int stm32_rtc_setdatetime(const struct tm *tp); -#endif - -/**************************************************************************** - * Name: stm32_rtc_lowerhalf - * - * Description: - * Instantiate the RTC lower half driver for the STM32. General usage: - * - * #include - * #include "stm32_rtc.h" - * - * struct rtc_lowerhalf_s *lower; - * lower = stm32_rtc_lowerhalf(); - * rtc_initialize(0, lower); - * - * Input Parameters: - * None - * - * Returned Value: - * On success, a non-NULL RTC lower interface is returned. NULL is - * returned on any failure. - * - ****************************************************************************/ - -#ifdef CONFIG_RTC_DRIVER -struct rtc_lowerhalf_s; -struct rtc_lowerhalf_s *stm32_rtc_lowerhalf(void); -#endif - -#undef EXTERN -#if defined(__cplusplus) -} -#endif -#endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32_STM32_RTC_H */ diff --git a/arch/arm/src/stm32/stm32_rtc_lowerhalf.c b/arch/arm/src/stm32/stm32_rtc_lowerhalf.c deleted file mode 100644 index 69c59d6f8879d..0000000000000 --- a/arch/arm/src/stm32/stm32_rtc_lowerhalf.c +++ /dev/null @@ -1,931 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_rtc_lowerhalf.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include - -#include -#include -#include - -#include "arm_internal.h" -#include "chip.h" -#include "stm32_rtc.h" - -#ifdef CONFIG_RTC_DRIVER - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#if defined(CONFIG_STM32_STM32F4XXX) || defined(CONFIG_STM32_STM32L15XX) -# define STM32_NALARMS 2 -#else -# define STM32_NALARMS 1 -#endif - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -#ifdef CONFIG_RTC_ALARM -struct stm32_cbinfo_s -{ - volatile rtc_alarm_callback_t cb; /* Callback when the alarm expires */ - volatile void *priv; /* Private argument to accompany callback */ -#if defined(CONFIG_STM32_STM32F4XXX) || defined(CONFIG_STM32_STM32L15XX) - uint8_t id; /* Identifies the alarm */ -#endif -}; -#endif - -/* This is the private type for the RTC state. It must be cast compatible - * with struct rtc_lowerhalf_s. - */ - -struct stm32_lowerhalf_s -{ - /* This is the contained reference to the read-only, lower-half - * operations vtable (which may lie in FLASH or ROM) - */ - - const struct rtc_ops_s *ops; - - /* Data following is private to this driver and not visible outside of - * this file. - */ - - mutex_t devlock; /* Threads can only exclusively access the RTC */ - -#ifdef CONFIG_RTC_ALARM - /* Alarm callback information */ - - struct stm32_cbinfo_s cbinfo[STM32_NALARMS]; -#endif - -#ifdef CONFIG_RTC_PERIODIC - /* Periodic wakeup information */ - - struct lower_setperiodic_s periodic; -#endif -}; - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -/* Prototypes for static methods in struct rtc_ops_s */ - -static int stm32_rdtime(struct rtc_lowerhalf_s *lower, - struct rtc_time *rtctime); -static int stm32_settime(struct rtc_lowerhalf_s *lower, - const struct rtc_time *rtctime); -static bool stm32_havesettime(struct rtc_lowerhalf_s *lower); - -#ifdef CONFIG_RTC_ALARM -static int stm32_setalarm(struct rtc_lowerhalf_s *lower, - const struct lower_setalarm_s *alarminfo); -static int stm32_setrelative(struct rtc_lowerhalf_s *lower, - const struct lower_setrelative_s *alarminfo); -static int stm32_cancelalarm(struct rtc_lowerhalf_s *lower, - int alarmid); -static int stm32_rdalarm(struct rtc_lowerhalf_s *lower, - struct lower_rdalarm_s *alarminfo); -#endif - -#ifdef CONFIG_RTC_PERIODIC -static int stm32_setperiodic(struct rtc_lowerhalf_s *lower, - const struct lower_setperiodic_s *alarminfo); -static int stm32_cancelperiodic(struct rtc_lowerhalf_s *lower, int id); -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* STM32 RTC driver operations */ - -static const struct rtc_ops_s g_rtc_ops = -{ - .rdtime = stm32_rdtime, - .settime = stm32_settime, - .havesettime = stm32_havesettime, -#ifdef CONFIG_RTC_ALARM - .setalarm = stm32_setalarm, - .setrelative = stm32_setrelative, - .cancelalarm = stm32_cancelalarm, - .rdalarm = stm32_rdalarm, -#endif -#ifdef CONFIG_RTC_PERIODIC - .setperiodic = stm32_setperiodic, - .cancelperiodic = stm32_cancelperiodic, -#endif -}; - -/* STM32 RTC device state */ - -static struct stm32_lowerhalf_s g_rtc_lowerhalf = -{ - .ops = &g_rtc_ops, - .devlock = NXMUTEX_INITIALIZER, -}; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_alarm_callback - * - * Description: - * This is the function that is called from the RTC driver when the alarm - * goes off. It just invokes the upper half drivers callback. - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef CONFIG_RTC_ALARM -#if defined(CONFIG_STM32_STM32F4XXX) || defined(CONFIG_STM32_STM32L15XX) -static void stm32_alarm_callback(void *arg, unsigned int alarmid) -{ - struct stm32_lowerhalf_s *lower; - struct stm32_cbinfo_s *cbinfo; - rtc_alarm_callback_t cb; - void *priv; - - DEBUGASSERT(alarmid == RTC_ALARMA || alarmid == RTC_ALARMB); - - lower = (struct stm32_lowerhalf_s *)arg; - cbinfo = &lower->cbinfo[alarmid]; - - /* Sample and clear the callback information to minimize the window in - * time in which race conditions can occur. - */ - - cb = (rtc_alarm_callback_t)cbinfo->cb; - priv = (void *)cbinfo->priv; - DEBUGASSERT(priv != NULL); - - cbinfo->cb = NULL; - cbinfo->priv = NULL; - - /* Perform the callback */ - - if (cb != NULL) - { - cb(priv, alarmid); - } -} - -#else -static void stm32_alarm_callback(void) -{ - struct stm32_cbinfo_s *cbinfo = &g_rtc_lowerhalf.cbinfo[0]; - - /* Sample and clear the callback information to minimize the window in - * time in which race conditions can occur. - */ - - rtc_alarm_callback_t cb = (rtc_alarm_callback_t)cbinfo->cb; - void *arg = (void *)cbinfo->priv; - - cbinfo->cb = NULL; - cbinfo->priv = NULL; - - /* Perform the callback */ - - if (cb != NULL) - { - cb(arg, 0); - } -} - -#endif /* CONFIG_STM32_STM32F4XXX || CONFIG_STM32_STM32L15XX */ -#endif /* CONFIG_RTC_ALARM */ - -/**************************************************************************** - * Name: stm32_rdtime - * - * Description: - * Implements the rdtime() method of the RTC driver interface - * - * Input Parameters: - * lower - A reference to RTC lower half driver state structure - * rcttime - The location in which to return the current RTC time. - * - * Returned Value: - * Zero (OK) is returned on success; a negated errno value is returned - * on any failure. - * - ****************************************************************************/ - -static int stm32_rdtime(struct rtc_lowerhalf_s *lower, - struct rtc_time *rtctime) -{ -#if defined(CONFIG_RTC_DATETIME) - /* This operation depends on the fact that struct rtc_time is cast - * compatible with struct tm. - */ - - return up_rtc_getdatetime((struct tm *)rtctime); - -#elif defined(CONFIG_RTC_HIRES) - struct timespec ts; - int ret; - - /* Get the higher resolution time */ - - ret = up_rtc_gettime(&ts); - if (ret < 0) - { - goto errout; - } - - /* Convert the one second epoch time to a struct tm. This operation - * depends on the fact that struct rtc_time and struct tm are cast - * compatible. - */ - - if (!gmtime_r(&ts.tv_sec, (struct tm *)rtctime)) - { - ret = -get_errno(); - goto errout; - } - - return OK; - -errout: - DEBUGASSERT(ret < 0); - return ret; - -#else - time_t timer; - - /* The resolution of time is only 1 second */ - - timer = up_rtc_time(); - - /* Convert the one second epoch time to a struct tm */ - - if (!gmtime_r(&timer, (struct tm *)rtctime)) - { - int errcode = get_errno(); - DEBUGASSERT(errcode > 0); - return -errcode; - } - - return OK; -#endif -} - -/**************************************************************************** - * Name: stm32_settime - * - * Description: - * Implements the settime() method of the RTC driver interface - * - * Input Parameters: - * lower - A reference to RTC lower half driver state structure - * rcttime - The new time to set - * - * Returned Value: - * Zero (OK) is returned on success; a negated errno value is returned - * on any failure. - * - ****************************************************************************/ - -static int stm32_settime(struct rtc_lowerhalf_s *lower, - const struct rtc_time *rtctime) -{ -#ifdef CONFIG_RTC_DATETIME - /* This operation depends on the fact that struct rtc_time is cast - * compatible with struct tm. - */ - - return stm32_rtc_setdatetime((const struct tm *)rtctime); - -#else - struct timespec ts; - - /* Convert the struct rtc_time to a time_t. Here we assume that struct - * rtc_time is cast compatible with struct tm. - */ - - ts.tv_sec = timegm((struct tm *)rtctime); - ts.tv_nsec = 0; - - /* Now set the time (to one second accuracy) */ - - return up_rtc_settime(&ts); -#endif -} - -/**************************************************************************** - * Name: stm32_havesettime - * - * Description: - * Implements the havesettime() method of the RTC driver interface - * - * Input Parameters: - * lower - A reference to RTC lower half driver state structure - * - * Returned Value: - * Returns true if RTC date-time have been previously set. - * - ****************************************************************************/ - -static bool stm32_havesettime(struct rtc_lowerhalf_s *lower) -{ -#if defined(CONFIG_STM32_STM32F10XX) - return getreg16(RTC_MAGIC_REG) == RTC_MAGIC_TIME_SET; -#else - return getreg32(RTC_MAGIC_REG) == RTC_MAGIC_TIME_SET; -#endif -} - -/**************************************************************************** - * Name: stm32_setalarm - * - * Description: - * Set a new alarm. This function implements the setalarm() method of the - * RTC driver interface - * - * Input Parameters: - * lower - A reference to RTC lower half driver state structure - * alarminfo - Provided information needed to set the alarm - * - * Returned Value: - * Zero (OK) is returned on success; a negated errno value is returned - * on any failure. - * - ****************************************************************************/ - -#ifdef CONFIG_RTC_ALARM -static int stm32_setalarm(struct rtc_lowerhalf_s *lower, - const struct lower_setalarm_s *alarminfo) -{ -#if defined(CONFIG_STM32_STM32F4XXX) || defined(CONFIG_STM32_STM32L15XX) - struct stm32_lowerhalf_s *priv; - struct stm32_cbinfo_s *cbinfo; - struct alm_setalarm_s lowerinfo; - int ret; - - /* ID0-> Alarm A; ID1 -> Alarm B */ - - DEBUGASSERT(lower != NULL && alarminfo != NULL); - DEBUGASSERT(alarminfo->id == RTC_ALARMA || alarminfo->id == RTC_ALARMB); - priv = (struct stm32_lowerhalf_s *)lower; - - ret = nxmutex_lock(&priv->devlock); - if (ret < 0) - { - return ret; - } - - ret = -EINVAL; - if (alarminfo->id == RTC_ALARMA || alarminfo->id == RTC_ALARMB) - { - /* Remember the callback information */ - - cbinfo = &priv->cbinfo[alarminfo->id]; - cbinfo->cb = alarminfo->cb; - cbinfo->priv = alarminfo->priv; - cbinfo->id = alarminfo->id; - - /* Set the alarm */ - - lowerinfo.as_id = alarminfo->id; - lowerinfo.as_cb = stm32_alarm_callback; - lowerinfo.as_arg = priv; - memcpy(&lowerinfo.as_time, &alarminfo->time, sizeof(struct tm)); - - /* And set the alarm */ - - ret = stm32_rtc_setalarm(&lowerinfo); - if (ret < 0) - { - cbinfo->cb = NULL; - cbinfo->priv = NULL; - } - } - - nxmutex_unlock(&priv->devlock); - return ret; - -#else - struct stm32_lowerhalf_s *priv; - struct stm32_cbinfo_s *cbinfo; - int ret; - - DEBUGASSERT(lower != NULL && alarminfo != NULL && alarminfo->id == 0); - priv = (struct stm32_lowerhalf_s *)lower; - - ret = nxmutex_lock(&priv->devlock); - if (ret < 0) - { - return ret; - } - - ret = -EINVAL; - if (alarminfo->id == 0) - { - struct timespec ts; - - /* Convert the RTC time to a timespec (1 second accuracy) */ - - ts.tv_sec = timegm((struct tm *)&alarminfo->time); - ts.tv_nsec = 0; - - /* Remember the callback information */ - - cbinfo = &priv->cbinfo[0]; - cbinfo->cb = alarminfo->cb; - cbinfo->priv = alarminfo->priv; - - /* And set the alarm */ - - ret = stm32_rtc_setalarm(&ts, stm32_alarm_callback); - if (ret < 0) - { - cbinfo->cb = NULL; - cbinfo->priv = NULL; - } - } - - nxmutex_unlock(&priv->devlock); - return ret; -#endif -} -#endif - -/**************************************************************************** - * Name: stm32_setrelative - * - * Description: - * Set a new alarm relative to the current time. This function implements - * the setrelative() method of the RTC driver interface - * - * Input Parameters: - * lower - A reference to RTC lower half driver state structure - * alarminfo - Provided information needed to set the alarm - * - * Returned Value: - * Zero (OK) is returned on success; a negated errno value is returned - * on any failure. - * - ****************************************************************************/ - -#ifdef CONFIG_RTC_ALARM -static int stm32_setrelative(struct rtc_lowerhalf_s *lower, - const struct lower_setrelative_s *alarminfo) -{ -#if defined(CONFIG_STM32_STM32F4XXX) || defined(CONFIG_STM32_STM32L15XX) - struct lower_setalarm_s setalarm; - struct tm time; - time_t seconds; - int ret = -EINVAL; - irqstate_t flags; - - DEBUGASSERT(lower != NULL && alarminfo != NULL); - DEBUGASSERT(alarminfo->id == RTC_ALARMA || alarminfo->id == RTC_ALARMB); - - if ((alarminfo->id == RTC_ALARMA || alarminfo->id == RTC_ALARMB) && - alarminfo->reltime > 0) - { - /* Disable pre-emption while we do this so that we don't have to worry - * about being suspended and working on an old time. - */ - - flags = enter_critical_section(); - - /* Get the current time in broken out format */ - - ret = up_rtc_getdatetime(&time); - if (ret >= 0) - { - /* Convert to seconds since the epoch */ - - seconds = timegm(&time); - - /* Add the seconds offset. Add one to the number of seconds - * because we are unsure of the phase of the timer. - */ - - seconds += (alarminfo->reltime + 1); - - /* And convert the time back to broken out format */ - - gmtime_r(&seconds, (struct tm *)&setalarm.time); - - /* The set the alarm using this absolute time */ - - setalarm.id = alarminfo->id; - setalarm.cb = alarminfo->cb; - setalarm.priv = alarminfo->priv; - - ret = stm32_setalarm(lower, &setalarm); - } - - leave_critical_section(flags); - } - - return ret; - -#else - struct stm32_lowerhalf_s *priv; - struct stm32_cbinfo_s *cbinfo; -#if defined(CONFIG_RTC_DATETIME) - struct tm time; -#endif - struct timespec ts; - int ret = -EINVAL; - irqstate_t flags; - - DEBUGASSERT(lower != NULL && alarminfo != NULL && alarminfo->id == 0); - priv = (struct stm32_lowerhalf_s *)lower; - - if (alarminfo->id == 0 && alarminfo->reltime > 0) - { - /* Disable pre-emption while we do this so that we don't have to worry - * about being suspended and working on an old time. - */ - - flags = enter_critical_section(); - - /* Get the current time in seconds */ - -#if defined(CONFIG_RTC_DATETIME) - /* Get the broken out time and convert to seconds */ - - ret = up_rtc_getdatetime(&time); - if (ret < 0) - { - leave_critical_section(flags); - return ret; - } - - ts.tv_sec = timegm(&time); - ts.tv_nsec = 0; - -#elif defined(CONFIG_RTC_HIRES) - /* Get the higher resolution time */ - - ret = up_rtc_gettime(&ts); - if (ret < 0) - { - leave_critical_section(flags); - return ret; - } -#else - /* The resolution of time is only 1 second */ - - ts.tv_sec = up_rtc_time(); - ts.tv_nsec = 0; -#endif - - /* Add the seconds offset. Add one to the number of seconds because - * we are unsure of the phase of the timer. - */ - - ts.tv_sec += (alarminfo->reltime + 1); - - /* Remember the callback information */ - - cbinfo = &priv->cbinfo[0]; - cbinfo->cb = alarminfo->cb; - cbinfo->priv = alarminfo->priv; - - /* And set the alarm */ - - ret = stm32_rtc_setalarm(&ts, stm32_alarm_callback); - if (ret < 0) - { - cbinfo->cb = NULL; - cbinfo->priv = NULL; - } - - leave_critical_section(flags); - } - - return ret; -#endif -} -#endif - -/**************************************************************************** - * Name: stm32_cancelalarm - * - * Description: - * Cancel the current alarm. This function implements the cancelalarm() - * method of the RTC driver interface - * - * Input Parameters: - * lower - A reference to RTC lower half driver state structure - * alarminfo - Provided information needed to set the alarm - * - * Returned Value: - * Zero (OK) is returned on success; a negated errno value is returned - * on any failure. - * - ****************************************************************************/ - -#ifdef CONFIG_RTC_ALARM -static int stm32_cancelalarm(struct rtc_lowerhalf_s *lower, int alarmid) -{ -#if defined(CONFIG_STM32_STM32F4XXX) || defined(CONFIG_STM32_STM32L15XX) - struct stm32_lowerhalf_s *priv; - struct stm32_cbinfo_s *cbinfo; - int ret; - - DEBUGASSERT(lower != NULL); - DEBUGASSERT(alarmid == RTC_ALARMA || alarmid == RTC_ALARMB); - priv = (struct stm32_lowerhalf_s *)lower; - - ret = nxmutex_lock(&priv->devlock); - if (ret < 0) - { - return ret; - } - - /* ID0-> Alarm A; ID1 -> Alarm B */ - - ret = -EINVAL; - if (alarmid == RTC_ALARMA || alarmid == RTC_ALARMB) - { - /* Nullify callback information to reduce window for race conditions */ - - cbinfo = &priv->cbinfo[alarmid]; - cbinfo->cb = NULL; - cbinfo->priv = NULL; - - /* Then cancel the alarm */ - - ret = stm32_rtc_cancelalarm((enum alm_id_e)alarmid); - } - - nxmutex_unlock(&priv->devlock); - return ret; - -#else - struct stm32_lowerhalf_s *priv; - struct stm32_cbinfo_s *cbinfo; - - DEBUGASSERT(lower != NULL); - DEBUGASSERT(alarmid == 0); - priv = (struct stm32_lowerhalf_s *)lower; - - /* Nullify callback information to reduce window for race conditions */ - - cbinfo = &priv->cbinfo[0]; - cbinfo->cb = NULL; - cbinfo->priv = NULL; - - /* Then cancel the alarm */ - - return stm32_rtc_cancelalarm(); -#endif -} -#endif - -/**************************************************************************** - * Name: stm32_rdalarm - * - * Description: - * Query the RTC alarm. - * - * Input Parameters: - * lower - A reference to RTC lower half driver state structure - * alarminfo - Provided information needed to query the alarm - * - * Returned Value: - * Zero (OK) is returned on success; a negated errno value is returned - * on any failure. - * - ****************************************************************************/ - -#ifdef CONFIG_RTC_ALARM -static int stm32_rdalarm(struct rtc_lowerhalf_s *lower, - struct lower_rdalarm_s *alarminfo) -{ - struct alm_rdalarm_s lowerinfo; - int ret = -EINVAL; - irqstate_t flags; - - DEBUGASSERT(lower != NULL && alarminfo != NULL && alarminfo->time != NULL); -#if defined(CONFIG_STM32_STM32F4XXX) || defined(CONFIG_STM32_STM32L15XX) - DEBUGASSERT(alarminfo->id == RTC_ALARMA || alarminfo->id == RTC_ALARMB); - - if (alarminfo->id == RTC_ALARMA || alarminfo->id == RTC_ALARMB) -#else - DEBUGASSERT(alarminfo->id >= 0 && alarminfo->id < CONFIG_RTC_NALARMS); - - if (alarminfo != NULL && alarminfo->id >= 0 && - alarminfo->id < CONFIG_RTC_NALARMS) -#endif - { - /* Disable pre-emption while we do this so that we don't have to worry - * about being suspended and working on an old time. - */ - - flags = enter_critical_section(); - - lowerinfo.ar_id = alarminfo->id; - lowerinfo.ar_time = alarminfo->time; - - ret = stm32_rtc_rdalarm(&lowerinfo); - - leave_critical_section(flags); - } - - return ret; -} -#endif - -/**************************************************************************** - * Name: stm32_periodic_callback - * - * Description: - * This is the function that is called from the RTC driver when the - * periodic wakeup goes off. It just invokes the upper half drivers - * callback. - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef CONFIG_RTC_PERIODIC -static int stm32_periodic_callback(void) -{ - struct stm32_lowerhalf_s *lower; - struct lower_setperiodic_s *cbinfo; - rtc_wakeup_callback_t cb; - void *priv; - - lower = (struct stm32_lowerhalf_s *)&g_rtc_lowerhalf; - - cbinfo = &lower->periodic; - cb = (rtc_wakeup_callback_t)cbinfo->cb; - priv = (void *)cbinfo->priv; - - /* Perform the callback */ - - if (cb != NULL) - { - cb(priv, 0); - } - - return OK; -} -#endif /* CONFIG_RTC_PERIODIC */ - -/**************************************************************************** - * Name: stm32_setperiodic - * - * Description: - * Set a new periodic wakeup relative to the current time, with a given - * period. This function implements the setperiodic() method of the RTC - * driver interface - * - * Input Parameters: - * lower - A reference to RTC lower half driver state structure - * alarminfo - Provided information needed to set the wakeup activity - * - * Returned Value: - * Zero (OK) is returned on success; a negated errno value is returned - * on any failure. - * - ****************************************************************************/ - -#ifdef CONFIG_RTC_PERIODIC -static int stm32_setperiodic(struct rtc_lowerhalf_s *lower, - const struct lower_setperiodic_s *alarminfo) -{ - struct stm32_lowerhalf_s *priv; - int ret; - - DEBUGASSERT(lower != NULL && alarminfo != NULL); - priv = (struct stm32_lowerhalf_s *)lower; - - ret = nxmutex_lock(&priv->devlock); - if (ret < 0) - { - return ret; - } - - memcpy(&priv->periodic, alarminfo, sizeof(struct lower_setperiodic_s)); - ret = stm32_rtc_setperiodic(&alarminfo->period, stm32_periodic_callback); - - nxmutex_unlock(&priv->devlock); - return ret; -} -#endif - -/**************************************************************************** - * Name: stm32_cancelperiodic - * - * Description: - * Cancel the current periodic wakeup activity. This function implements - * the cancelperiodic() method of the RTC driver interface - * - * Input Parameters: - * lower - A reference to RTC lower half driver state structure - * - * Returned Value: - * Zero (OK) is returned on success; a negated errno value is returned - * on any failure. - * - ****************************************************************************/ - -#ifdef CONFIG_RTC_PERIODIC -static int stm32_cancelperiodic(struct rtc_lowerhalf_s *lower, int id) -{ - struct stm32_lowerhalf_s *priv; - int ret; - - DEBUGASSERT(lower != NULL); - priv = (struct stm32_lowerhalf_s *)lower; - - DEBUGASSERT(id == 0); - - ret = nxmutex_lock(&priv->devlock); - if (ret < 0) - { - return ret; - } - - ret = stm32_rtc_cancelperiodic(); - - nxmutex_unlock(&priv->devlock); - return ret; -} -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_rtc_lowerhalf - * - * Description: - * Instantiate the RTC lower half driver for the STM32. General usage: - * - * #include - * #include "stm32_rtc.h> - * - * struct rtc_lowerhalf_s *lower; - * lower = stm32_rtc_lowerhalf(); - * rtc_initialize(0, lower); - * - * Input Parameters: - * None - * - * Returned Value: - * On success, a non-NULL RTC lower interface is returned. NULL is - * returned on any failure. - * - ****************************************************************************/ - -struct rtc_lowerhalf_s *stm32_rtc_lowerhalf(void) -{ - return (struct rtc_lowerhalf_s *)&g_rtc_lowerhalf; -} - -#endif /* CONFIG_RTC_DRIVER */ diff --git a/arch/arm/src/stm32/stm32_rtcc.c b/arch/arm/src/stm32/stm32_rtcc.c deleted file mode 100644 index cd0e55db467f6..0000000000000 --- a/arch/arm/src/stm32/stm32_rtcc.c +++ /dev/null @@ -1,1080 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_rtcc.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include - -#include -#include -#include - -#include - -#include "arm_internal.h" -#include "stm32_rcc.h" -#include "stm32_pwr.h" -#include "stm32_exti.h" -#include "stm32_rtc.h" - -#ifdef CONFIG_STM32_RTC - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -/* This RTC implementation supports only date/time RTC hardware */ - -#ifndef CONFIG_RTC_DATETIME -# error "CONFIG_RTC_DATETIME must be set to use this driver" -#endif - -#ifdef CONFIG_RTC_HIRES -# error "CONFIG_RTC_HIRES must NOT be set with this driver" -#endif - -#ifndef CONFIG_STM32_PWR -# error "CONFIG_STM32_PWR must selected to use this driver" -#endif - -/* Constants ****************************************************************/ - -#define SYNCHRO_TIMEOUT (0x00020000) -#define INITMODE_TIMEOUT (0x00010000) - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* Callback to use when the alarm expires */ - -#ifdef CONFIG_RTC_ALARM -static alarmcb_t g_alarmcb; -#endif - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/* g_rtc_enabled is set true after the RTC has successfully initialized */ - -volatile bool g_rtc_enabled = false; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: rtc_dumpregs - ****************************************************************************/ - -#ifdef CONFIG_DEBUG_RTC_INFO -static void rtc_dumpregs(const char *msg) -{ - rtcinfo("%s:\n", msg); - rtcinfo(" TR: %08" PRIx32 "\n", getreg32(STM32_RTC_TR)); - rtcinfo(" DR: %08" PRIx32 "\n", getreg32(STM32_RTC_DR)); - rtcinfo(" CR: %08" PRIx32 "\n", getreg32(STM32_RTC_CR)); - rtcinfo(" ISR: %08" PRIx32 "\n", getreg32(STM32_RTC_ISR)); - rtcinfo(" PRER: %08" PRIx32 "\n", getreg32(STM32_RTC_PRER)); - rtcinfo(" WUTR: %08" PRIx32 "\n", getreg32(STM32_RTC_WUTR)); -#ifndef CONFIG_STM32_STM32F30XX - rtcinfo(" CALIBR: %08" PRIx32 "\n", getreg32(STM32_RTC_CALIBR)); -#endif - rtcinfo(" ALRMAR: %08" PRIx32 "\n", getreg32(STM32_RTC_ALRMAR)); - rtcinfo(" ALRMBR: %08" PRIx32 "\n", getreg32(STM32_RTC_ALRMBR)); - rtcinfo(" SHIFTR: %08" PRIx32 "\n", getreg32(STM32_RTC_SHIFTR)); - rtcinfo(" TSTR: %08" PRIx32 "\n", getreg32(STM32_RTC_TSTR)); - rtcinfo(" TSDR: %08" PRIx32 "\n", getreg32(STM32_RTC_TSDR)); - rtcinfo(" TSSSR: %08" PRIx32 "\n", getreg32(STM32_RTC_TSSSR)); - rtcinfo(" CALR: %08" PRIx32 "\n", getreg32(STM32_RTC_CALR)); - rtcinfo(" TAFCR: %08" PRIx32 "\n", getreg32(STM32_RTC_TAFCR)); - rtcinfo("ALRMASSR: %08" PRIx32 "\n", getreg32(STM32_RTC_ALRMASSR)); - rtcinfo("ALRMBSSR: %08" PRIx32 "\n", getreg32(STM32_RTC_ALRMBSSR)); - rtcinfo("MAGICREG: %08" PRIx32 "\n", getreg32(RTC_MAGIC_REG)); -} -#else -# define rtc_dumpregs(msg) -#endif - -/**************************************************************************** - * Name: rtc_dumptime - ****************************************************************************/ - -#ifdef CONFIG_DEBUG_RTC_INFO -static void rtc_dumptime(struct tm *tp, const char *msg) -{ - rtcinfo("%s:\n", msg); - rtcinfo(" tm_sec: %08x\n", tp->tm_sec); - rtcinfo(" tm_min: %08x\n", tp->tm_min); - rtcinfo(" tm_hour: %08x\n", tp->tm_hour); - rtcinfo(" tm_mday: %08x\n", tp->tm_mday); - rtcinfo(" tm_mon: %08x\n", tp->tm_mon); - rtcinfo(" tm_year: %08x\n", tp->tm_year); -} -#else -# define rtc_dumptime(tp, msg) -#endif - -/**************************************************************************** - * Name: rtc_wprunlock - * - * Description: - * Disable RTC write protection - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void rtc_wprunlock(void) -{ - /* Enable write access to the backup domain (RTC registers, RTC backup data - * registers and backup SRAM). - */ - - stm32_pwr_enablebkp(true); - - /* The following steps are required to unlock the write protection on all - * the RTC registers (except for RTC_ISR[13:8], RTC_TAFCR, and RTC_BKPxR). - * - * 1. Write 0xCA into the RTC_WPR register. - * 2. Write 0x53 into the RTC_WPR register. - * - * Writing a wrong key re-activates the write protection. - */ - - putreg32(0xca, STM32_RTC_WPR); - putreg32(0x53, STM32_RTC_WPR); -} - -/**************************************************************************** - * Name: rtc_wprlock - * - * Description: - * Enable RTC write protection - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -static inline void rtc_wprlock(void) -{ - /* Writing any wrong key re-activates the write protection. */ - - putreg32(0xff, STM32_RTC_WPR); - - /* Disable write access to the backup domain (RTC registers, RTC backup - * data registers and backup SRAM). - */ - - stm32_pwr_enablebkp(false); -} - -/**************************************************************************** - * Name: rtc_synchwait - * - * Description: - * Waits until the RTC Time and Date registers (RTC_TR and RTC_DR) are - * synchronized with RTC APB clock. - * - * Input Parameters: - * None - * - * Returned Value: - * Zero (OK) on success; a negated errno on failure - * - ****************************************************************************/ - -static int rtc_synchwait(void) -{ - volatile uint32_t timeout; - uint32_t regval; - int ret; - - /* Disable the write protection for RTC registers */ - - rtc_wprunlock(); - - /* Clear Registers synchronization flag (RSF) */ - - regval = getreg32(STM32_RTC_ISR); - regval &= ~RTC_ISR_RSF; - putreg32(regval, STM32_RTC_ISR); - - /* Now wait the registers to become synchronised */ - - ret = -ETIMEDOUT; - for (timeout = 0; timeout < SYNCHRO_TIMEOUT; timeout++) - { - regval = getreg32(STM32_RTC_ISR); - if ((regval & RTC_ISR_RSF) != 0) - { - /* Synchronized */ - - ret = OK; - break; - } - } - - /* Re-enable the write protection for RTC registers */ - - rtc_wprlock(); - return ret; -} - -/**************************************************************************** - * Name: rtc_enterinit - * - * Description: - * Enter RTC initialization mode. - * - * Input Parameters: - * None - * - * Returned Value: - * Zero (OK) on success; a negated errno on failure - * - ****************************************************************************/ - -static int rtc_enterinit(void) -{ - volatile uint32_t timeout; - uint32_t regval; - int ret; - - /* Check if the Initialization mode is already set */ - - regval = getreg32(STM32_RTC_ISR); - - ret = OK; - if ((regval & RTC_ISR_INITF) == 0) - { - /* Set the Initialization mode */ - - putreg32(RTC_ISR_INIT, STM32_RTC_ISR); - - /* Wait until the RTC is in the INIT state (or a timeout occurs) */ - - ret = -ETIMEDOUT; - for (timeout = 0; timeout < INITMODE_TIMEOUT; timeout++) - { - regval = getreg32(STM32_RTC_ISR); - if ((regval & RTC_ISR_INITF) != 0) - { - ret = OK; - break; - } - } - } - - return ret; -} - -/**************************************************************************** - * Name: rtc_exitinit - * - * Description: - * Exit RTC initialization mode. - * - * Input Parameters: - * None - * - * Returned Value: - * Zero (OK) on success; a negated errno on failure - * - ****************************************************************************/ - -static void rtc_exitinit(void) -{ - uint32_t regval; - - regval = getreg32(STM32_RTC_ISR); - regval &= ~(RTC_ISR_INIT); - putreg32(regval, STM32_RTC_ISR); -} - -/**************************************************************************** - * Name: rtc_bin2bcd - * - * Description: - * Converts a 2 digit binary to BCD format - * - * Input Parameters: - * value - The byte to be converted. - * - * Returned Value: - * The value in BCD representation - * - ****************************************************************************/ - -static uint32_t rtc_bin2bcd(int value) -{ - uint32_t msbcd = 0; - - while (value >= 10) - { - msbcd++; - value -= 10; - } - - return (msbcd << 4) | value; -} - -/**************************************************************************** - * Name: rtc_bin2bcd - * - * Description: - * Convert from 2 digit BCD to binary. - * - * Input Parameters: - * value - The BCD value to be converted. - * - * Returned Value: - * The value in binary representation - * - ****************************************************************************/ - -static int rtc_bcd2bin(uint32_t value) -{ - uint32_t tens = (value >> 4) * 10; - return (int)(tens + (value & 0x0f)); -} - -/**************************************************************************** - * Name: rtc_setup - * - * Description: - * Performs first time configuration of the RTC. A special value written - * into back-up register 0 will prevent this function from being called on - * sub-sequent resets or power up. - * - * Input Parameters: - * None - * - * Returned Value: - * Zero (OK) on success; a negated errno on failure - * - ****************************************************************************/ - -static int rtc_setup(void) -{ - uint32_t regval; - int ret; - - /* Disable the write protection for RTC registers */ - - rtc_wprunlock(); - - /* Set Initialization mode */ - - ret = rtc_enterinit(); - if (ret == OK) - { - /* Set the 24 hour format by clearing the FMT bit in the RTC - * control register - */ - - regval = getreg32(STM32_RTC_CR); - regval &= ~RTC_CR_FMT; - putreg32(regval, STM32_RTC_CR); - - /* Configure RTC pre-scaler with the required values */ - -#ifdef CONFIG_STM32_RTC_HSECLOCK - /* STMicro app note AN4759 suggests using 7999 and 124 to - * get exactly 1MHz when using the RTC at 8MHz. - */ - - putreg32(((uint32_t)7999 << RTC_PRER_PREDIV_S_SHIFT) | - ((uint32_t)124 << RTC_PRER_PREDIV_A_SHIFT), - STM32_RTC_PRER); -#else - /* Correct values for 32.768 KHz LSE clock and inaccurate LSI clock */ - - putreg32(((uint32_t)0xff << RTC_PRER_PREDIV_S_SHIFT) | - ((uint32_t)0x7f << RTC_PRER_PREDIV_A_SHIFT), - STM32_RTC_PRER); -#endif - - /* Exit RTC initialization mode */ - - rtc_exitinit(); - } - - /* Re-enable the write protection for RTC registers */ - - rtc_wprlock(); - - return ret; -} - -/**************************************************************************** - * Name: rtc_resume - * - * Description: - * Called when the RTC was already initialized on a previous power cycle. - * This just brings the RTC back into full operation. - * - * Input Parameters: - * None - * - * Returned Value: - * Zero (OK) on success; a negated errno on failure - * - ****************************************************************************/ - -static void rtc_resume(void) -{ -#ifdef CONFIG_RTC_ALARM - uint32_t regval; - - /* Clear the RTC alarm flags */ - - regval = getreg32(STM32_RTC_ISR); - regval &= ~(RTC_ISR_ALRAF | RTC_ISR_ALRBF); - putreg32(regval, STM32_RTC_ISR); - - /* Clear the EXTI Line 17 Pending bit (Connected internally to RTC Alarm) */ - - putreg32((1 << 17), STM32_EXTI_PR); -#endif -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: up_rtc_initialize - * - * Description: - * Initialize the hardware RTC per the selected configuration. - * This function is called once during the OS initialization sequence - * - * Input Parameters: - * None - * - * Returned Value: - * Zero (OK) on success; a negated errno on failure - * - ****************************************************************************/ - -int up_rtc_initialize(void) -{ - uint32_t regval; - uint32_t tr_bkp; - uint32_t dr_bkp; - int ret; - int maxretry = 10; - int nretry = 0; - - /* Clocking for the PWR block must be provided. However, this is done - * unconditionally in stm32f40xxx_rcc.c on power up. This done - * unconditionally because the PWR block is also needed to set the internal - * voltage regulator for maximum performance. - */ - - rtc_dumpregs("On reset"); - - /* Select the clock source */ - - /* Save the token before losing it when resetting */ - - regval = getreg32(RTC_MAGIC_REG); - - stm32_pwr_enablebkp(true); - - if (regval != RTC_MAGIC && regval != RTC_MAGIC_TIME_SET) - { - /* Some boards do not have the external 32khz oscillator installed, - * for those boards we must fallback to the crummy internal RC clock - * or the external high rate clock - */ - -#ifdef CONFIG_STM32_RTC_HSECLOCK - /* Use the HSE clock as the input to the RTC block */ - - modifyreg32(STM32_RCC_BDCR, RCC_BDCR_RTCSEL_MASK, RCC_BDCR_RTCSEL_HSE); - -#elif defined(CONFIG_STM32_RTC_LSICLOCK) - /* Use the LSI clock as the input to the RTC block */ - - modifyreg32(STM32_RCC_BDCR, RCC_BDCR_RTCSEL_MASK, RCC_BDCR_RTCSEL_LSI); - -#elif defined(CONFIG_STM32_RTC_LSECLOCK) - /* Use the LSE clock as the input to the RTC block */ - - modifyreg32(STM32_RCC_BDCR, RCC_BDCR_RTCSEL_MASK, RCC_BDCR_RTCSEL_LSE); - -#endif - /* Enable the RTC Clock by setting the RTCEN bit in the RCC register */ - - modifyreg32(STM32_RCC_BDCR, 0, RCC_BDCR_RTCEN); - } - else /* The RTC is already in use: check if the clock source is changed */ - { -#if defined(CONFIG_STM32_RTC_HSECLOCK) || defined(CONFIG_STM32_RTC_LSICLOCK) || \ - defined(CONFIG_STM32_RTC_LSECLOCK) - - uint32_t clksrc = getreg32(STM32_RCC_BDCR); - -#if defined(CONFIG_STM32_RTC_HSECLOCK) - if ((clksrc & RCC_BDCR_RTCSEL_MASK) != RCC_BDCR_RTCSEL_HSE) -#elif defined(CONFIG_STM32_RTC_LSICLOCK) - if ((clksrc & RCC_BDCR_RTCSEL_MASK) != RCC_BDCR_RTCSEL_LSI) -#elif defined(CONFIG_STM32_RTC_LSECLOCK) - if ((clksrc & RCC_BDCR_RTCSEL_MASK) != RCC_BDCR_RTCSEL_LSE) -#endif -#endif - { - tr_bkp = getreg32(STM32_RTC_TR); - dr_bkp = getreg32(STM32_RTC_DR); - modifyreg32(STM32_RCC_BDCR, 0, RCC_BDCR_BDRST); - modifyreg32(STM32_RCC_BDCR, RCC_BDCR_BDRST, 0); - -#if defined(CONFIG_STM32_RTC_HSECLOCK) - /* Change to the new clock as the input to the RTC block */ - - modifyreg32(STM32_RCC_BDCR, - RCC_BDCR_RTCSEL_MASK, RCC_BDCR_RTCSEL_HSE); - -#elif defined(CONFIG_STM32_RTC_LSICLOCK) - modifyreg32(STM32_RCC_BDCR, - RCC_BDCR_RTCSEL_MASK, RCC_BDCR_RTCSEL_LSI); - -#elif defined(CONFIG_STM32_RTC_LSECLOCK) - modifyreg32(STM32_RCC_BDCR, - RCC_BDCR_RTCSEL_MASK, RCC_BDCR_RTCSEL_LSE); -#endif - - putreg32(tr_bkp, STM32_RTC_TR); - putreg32(dr_bkp, STM32_RTC_DR); - - /* Remember that the RTC is initialized */ - - putreg32(RTC_MAGIC, RTC_MAGIC_REG); - - /* Enable the RTC Clock by setting the RTCEN bit in the RCC - * register - */ - - modifyreg32(STM32_RCC_BDCR, 0, RCC_BDCR_RTCEN); - } - } - - stm32_pwr_enablebkp(false); - - /* Loop, attempting to initialize/resume the RTC. This loop is necessary - * because it seems that occasionally it takes longer to initialize the RTC - * (the actual failure is in rtc_synchwait()). - */ - - do - { - /* Wait for the RTC Time and Date registers to be synchronized with RTC - * APB clock. - */ - - ret = rtc_synchwait(); - - /* Check that rtc_syncwait() returned successfully */ - - switch (ret) - { - case OK: - { - rtcinfo("rtc_syncwait() okay\n"); - break; - } - - default: - { - rtcerr("ERROR: rtc_syncwait() failed (%d)\n", ret); - break; - } - } - } - while (ret != OK && ++nretry < maxretry); - - /* Check if the one-time initialization of the RTC has already been - * performed. We can determine this by checking if the magic number - * has been written to the back-up date register DR0. - */ - - if (regval != RTC_MAGIC && regval != RTC_MAGIC_TIME_SET) - { - rtcinfo("Do setup\n"); - - /* Perform the one-time setup of the LSE clocking to the RTC */ - - ret = rtc_setup(); - - /* Enable write access to the backup domain (RTC registers, RTC - * backup data registers and backup SRAM). - */ - - stm32_pwr_enablebkp(true); - - /* Remember that the RTC is initialized */ - - putreg32(RTC_MAGIC, RTC_MAGIC_REG); - - /* Disable write access to the backup domain (RTC registers, RTC - * backup data registers and backup SRAM). - */ - - stm32_pwr_enablebkp(false); - } - else - { - rtcinfo("Do resume\n"); - - /* RTC already set-up, just resume normal operation */ - - rtc_resume(); - rtc_dumpregs("Did resume"); - } - - if (ret != OK && nretry > 0) - { - rtcinfo("setup/resume ran %d times and failed with %d\n", - nretry, ret); - return -ETIMEDOUT; - } - - /* Configure RTC interrupt to catch alarm interrupts. All RTC interrupts - * are connected to the EXTI controller. To enable the RTC Alarm - * interrupt, the following sequence is required: - * - * 1. Configure and enable the EXTI Line 17 in interrupt mode and select - * the rising edge sensitivity. - * 2. Configure and enable the RTC_Alarm IRQ channel in the NVIC. - * 3. Configure the RTC to generate RTC alarms (Alarm A or Alarm B). - */ - - g_rtc_enabled = true; - rtc_dumpregs("After Initialization"); - return OK; -} - -/**************************************************************************** - * Name: stm32_rtc_irqinitialize - * - * Description: - * Initialize IRQs for RTC, not possible during up_rtc_initialize because - * up_irqinitialize is called later. - * - * Input Parameters: - * None - * - * Returned Value: - * Zero (OK) on success; a negated errno on failure - * - ****************************************************************************/ - -int stm32_rtc_irqinitialize(void) -{ -#ifdef CONFIG_RTC_ALARM -# warning "Missing logic" -#endif - - return OK; -} - -/**************************************************************************** - * Name: stm32_rtc_getdatetime_with_subseconds - * - * Description: - * Get the current date and time from the date/time RTC. This interface - * is only supported by the date/time RTC hardware implementation. - * It is used to replace the system timer. It is only used by the RTOS - * during initialization to set up the system time when CONFIG_RTC and - * CONFIG_RTC_DATETIME are selected (and CONFIG_RTC_HIRES is not). - * - * NOTE: Some date/time RTC hardware is capability of sub-second accuracy. - * That sub-second accuracy is returned through 'nsec'. - * - * Input Parameters: - * tp - The location to return the high resolution time value. - * nsec - The location to return the subsecond time value. - * - * Returned Value: - * Zero (OK) on success; a negated errno on failure - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_HAVE_RTC_SUBSECONDS -int stm32_rtc_getdatetime_with_subseconds(struct tm *tp, long *nsec) -#else -int up_rtc_getdatetime(struct tm *tp) -#endif -{ -#ifdef CONFIG_STM32_HAVE_RTC_SUBSECONDS - uint32_t ssr; -#endif - uint32_t dr; - uint32_t tr; - uint32_t tmp; - - /* Sample the data time registers. There is a race condition here... If - * we sample the time just before midnight on December 31, the date could - * be wrong because the day rolled over while were sampling. Thus loop for - * checking overflow here is needed. There is a race condition with - * subseconds too. If we sample TR register just before second rolling - * and subseconds are read at wrong second, we get wrong time. - */ - - do - { - dr = getreg32(STM32_RTC_DR); - tr = getreg32(STM32_RTC_TR); -#ifdef CONFIG_STM32_HAVE_RTC_SUBSECONDS - ssr = getreg32(STM32_RTC_SSR); - tmp = getreg32(STM32_RTC_TR); - if (tmp != tr) - { - continue; - } -#endif - - tmp = getreg32(STM32_RTC_DR); - if (tmp == dr) - { - break; - } - } - while (1); - - rtc_dumpregs("Reading Time"); - - /* Convert the RTC time to fields in struct tm format. All of the STM32 - * ranges of values correspond between struct tm and the time register. - */ - - tmp = (tr & (RTC_TR_SU_MASK | RTC_TR_ST_MASK)) >> RTC_TR_SU_SHIFT; - tp->tm_sec = rtc_bcd2bin(tmp); - - tmp = (tr & (RTC_TR_MNU_MASK | RTC_TR_MNT_MASK)) >> RTC_TR_MNU_SHIFT; - tp->tm_min = rtc_bcd2bin(tmp); - - tmp = (tr & (RTC_TR_HU_MASK | RTC_TR_HT_MASK)) >> RTC_TR_HU_SHIFT; - tp->tm_hour = rtc_bcd2bin(tmp); - - /* Now convert the RTC date to fields in struct tm format: - * Days: 1-31 match in both cases. - * Month: STM32 is 1-12, struct tm is 0-11. - * Years: STM32 is 00-99, struct tm is years since 1900. - * WeekDay: STM32 is 1 = Mon - 7 = Sun - * - * Issue: I am not sure what the STM32 years mean. Are these the - * years 2000-2099? I'll assume so. - */ - - tmp = (dr & (RTC_DR_DU_MASK | RTC_DR_DT_MASK)) >> RTC_DR_DU_SHIFT; - tp->tm_mday = rtc_bcd2bin(tmp); - - tmp = (dr & (RTC_DR_MU_MASK | RTC_DR_MT)) >> RTC_DR_MU_SHIFT; - tp->tm_mon = rtc_bcd2bin(tmp) - 1; - - tmp = (dr & (RTC_DR_YU_MASK | RTC_DR_YT_MASK)) >> RTC_DR_YU_SHIFT; - tp->tm_year = rtc_bcd2bin(tmp) + 100; - - tmp = (dr & RTC_DR_WDU_MASK) >> RTC_DR_WDU_SHIFT; - tp->tm_wday = tmp % 7; - tp->tm_yday = tp->tm_mday - 1 + - clock_daysbeforemonth(tp->tm_mon, - clock_isleapyear(tp->tm_year + 1900)); - tp->tm_isdst = 0; - -#ifdef CONFIG_STM32_HAVE_RTC_SUBSECONDS - /* Return RTC sub-seconds if no configured and if a non-NULL value - * of nsec has been provided to receive the sub-second value. - */ - - if (nsec) - { - uint32_t prediv_s; - uint32_t usecs; - - prediv_s = getreg32(STM32_RTC_PRER) & RTC_PRER_PREDIV_S_MASK; - prediv_s >>= RTC_PRER_PREDIV_S_SHIFT; - - ssr &= RTC_SSR_MASK; - - /* Maximum prediv_s is 0x7fff, thus we can multiply by 100000 and - * still fit 32-bit unsigned integer. - */ - - usecs = (((prediv_s - ssr) * 100000) / (prediv_s + 1)) * 10; - *nsec = usecs * 1000; - } -#endif /* CONFIG_STM32_HAVE_RTC_SUBSECONDS */ - - rtc_dumptime(tp, "Returning"); - return OK; -} - -/**************************************************************************** - * Name: up_rtc_getdatetime - * - * Description: - * Get the current date and time from the date/time RTC. This interface - * is only supported by the date/time RTC hardware implementation. - * It is used to replace the system timer. It is only used by the RTOS - * during initialization to set up the system time when CONFIG_RTC and - * CONFIG_RTC_DATETIME are selected (and CONFIG_RTC_HIRES is not). - * - * NOTE: Some date/time RTC hardware is capability of sub-second accuracy. - * That sub-second accuracy is lost in this interface. However, since the - * system time is reinitialized on each power-up/reset, there will be no - * timing inaccuracy in the long run. - * - * Input Parameters: - * tp - The location to return the high resolution time value. - * - * Returned Value: - * Zero (OK) on success; a negated errno on failure - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_HAVE_RTC_SUBSECONDS -int up_rtc_getdatetime(struct tm *tp) -{ - return stm32_rtc_getdatetime_with_subseconds(tp, NULL); -} -#endif - -/**************************************************************************** - * Name: up_rtc_getdatetime_with_subseconds - * - * Description: - * Get the current date and time from the date/time RTC. This interface - * is only supported by the date/time RTC hardware implementation. - * It is used to replace the system timer. It is only used by the RTOS - * during initialization to set up the system time when CONFIG_RTC and - * CONFIG_RTC_DATETIME are selected (and CONFIG_RTC_HIRES is not). - * - * NOTE: - * This interface exposes sub-second accuracy capability of RTC hardware. - * This interface allow maintaining timing accuracy when system time needs - * constant resynchronization with RTC, for example on MCU with low-power - * state that stop system timer. - * - * Input Parameters: - * tp - The location to return the high resolution time value. - * nsec - The location to return the subsecond time value. - * - * Returned Value: - * Zero (OK) on success; a negated errno on failure - * - ****************************************************************************/ - -#ifdef CONFIG_ARCH_HAVE_RTC_SUBSECONDS -# ifndef CONFIG_STM32_HAVE_RTC_SUBSECONDS -# error "Invalid config, enable CONFIG_STM32_HAVE_RTC_SUBSECONDS." -# endif -int up_rtc_getdatetime_with_subseconds(struct tm *tp, long *nsec) -{ - return stm32_rtc_getdatetime_with_subseconds(tp, nsec); -} -#endif - -/**************************************************************************** - * Name: stm32_rtc_setdatetime - * - * Description: - * Set the RTC to the provided time. RTC implementations which provide - * up_rtc_getdatetime() (CONFIG_RTC_DATETIME is selected) should provide - * this function. - * - * Input Parameters: - * tp - the time to use - * - * Returned Value: - * Zero (OK) on success; a negated errno on failure - * - ****************************************************************************/ - -int stm32_rtc_setdatetime(const struct tm *tp) -{ - uint32_t tr; - uint32_t dr; - int ret; - - rtc_dumptime(tp, "Setting time"); - - /* Then write the broken out values to the RTC */ - - /* Convert the struct tm format to RTC time register fields. All of the - * STM32 All of the ranges of values correspond between struct tm and the - * time register. - */ - - tr = (rtc_bin2bcd(tp->tm_sec) << RTC_TR_SU_SHIFT) | - (rtc_bin2bcd(tp->tm_min) << RTC_TR_MNU_SHIFT) | - (rtc_bin2bcd(tp->tm_hour) << RTC_TR_HU_SHIFT); - tr &= ~RTC_TR_RESERVED_BITS; - - /* Now convert the fields in struct tm format to the RTC date register - * fields: - * Days: 1-31 match in both cases. - * Month: STM32 is 1-12, struct tm is 0-11. - * Years: STM32 is 00-99, struct tm is years since 1900. - * WeekDay: STM32 is 1 = Mon - 7 = Sun - * Issue: I am not sure what the STM32 years mean. Are these the - * years 2000-2099? I'll assume so. - */ - - dr = (rtc_bin2bcd(tp->tm_mday) << RTC_DR_DU_SHIFT) | - ((rtc_bin2bcd(tp->tm_mon + 1)) << RTC_DR_MU_SHIFT) | - ((tp->tm_wday == 0 ? 7 : (tp->tm_wday & 7)) << RTC_DR_WDU_SHIFT) | - ((rtc_bin2bcd(tp->tm_year - 100)) << RTC_DR_YU_SHIFT); - - dr &= ~RTC_DR_RESERVED_BITS; - - /* Disable the write protection for RTC registers */ - - rtc_wprunlock(); - - /* Set Initialization mode */ - - ret = rtc_enterinit(); - if (ret == OK) - { - /* Set the RTC TR and DR registers */ - - putreg32(tr, STM32_RTC_TR); - putreg32(dr, STM32_RTC_DR); - - /* Exit Initialization mode and wait for the RTC Time and Date - * registers to be synchronized with RTC APB clock. - */ - - rtc_exitinit(); - ret = rtc_synchwait(); - } - - /* Remember that the RTC is initialized and had its time set. */ - - if (getreg32(RTC_MAGIC_REG) != RTC_MAGIC_TIME_SET) - { - stm32_pwr_enablebkp(true); - putreg32(RTC_MAGIC_TIME_SET, RTC_MAGIC_REG); - stm32_pwr_enablebkp(false); - } - - /* Re-enable the write protection for RTC registers */ - - rtc_wprlock(); - rtc_dumpregs("New time setting"); - return ret; -} - -/**************************************************************************** - * Name: up_rtc_settime - * - * Description: - * Set the RTC to the provided time. All RTC implementations must be able - * to set their time based on a standard timespec. - * - * Input Parameters: - * tp - the time to use - * - * Returned Value: - * Zero (OK) on success; a negated errno on failure - * - ****************************************************************************/ - -int up_rtc_settime(const struct timespec *tp) -{ - struct tm newtime; - - /* Break out the time values - * (not that the time is set only to units of seconds) - */ - - gmtime_r(&tp->tv_sec, &newtime); - return stm32_rtc_setdatetime(&newtime); -} - -/**************************************************************************** - * Name: stm32_rtc_setalarm - * - * Description: - * Set up an alarm. - * Up to two alarms can be supported (ALARM A and ALARM B). - * - * Input Parameters: - * tp - the time to set the alarm - * callback - the function to call when the alarm expires. - * - * Returned Value: - * Zero (OK) on success; a negated errno on failure - * - ****************************************************************************/ - -#ifdef CONFIG_RTC_ALARM -int stm32_rtc_setalarm(const struct timespec *tp, alarmcb_t callback) -{ - int ret = -EBUSY; - - /* Is there already something waiting on the ALARM? */ - - if (g_alarmcb == NULL) - { - /* No.. Save the callback function pointer */ - - g_alarmcb = callback; - - /* Break out the time values */ - -#warning "Missing logic" - - /* The set the alarm */ - -#warning "Missing logic" - - ret = OK; - } - - return ret; -} -#endif - -#endif /* CONFIG_STM32_RTC */ diff --git a/arch/arm/src/stm32/stm32_rtcounter.c b/arch/arm/src/stm32/stm32_rtcounter.c deleted file mode 100644 index a93fcb4f8904b..0000000000000 --- a/arch/arm/src/stm32/stm32_rtcounter.c +++ /dev/null @@ -1,848 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_rtcounter.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* The STM32 RTC Driver offers standard precision of 1 Hz or High Resolution - * operating at rate up to 16384 Hz. It provides UTC time and alarm interface - * with external output pin (for wake-up). - * - * RTC is based on hardware RTC module which is located in a separate power - * domain. The 32-bit counter is extended by 16-bit registers in BKP domain - * STM32_BKP_DR1 to provide system equiv. function to the: time_t time - * (time_t *). - * - * Notation: - * - clock refers to 32-bit hardware counter - * - time is a combination of clock and upper bits stored in backuped domain - * with unit of 1 [s] - * - * TODO: - * Error Handling in case LSE fails during start-up or during operation. - */ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include - -#include "arm_internal.h" -#include "stm32_pwr.h" -#include "stm32_rcc.h" -#include "stm32_rtc.h" -#include "stm32_waste.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -/* In hi-res mode, the RTC operates at 16384Hz. Overflow interrupts are - * handled when the 32-bit RTC counter overflows every 3 days and 43 minutes. - * A BKP register is incremented on each overflow interrupt creating, - * effectively, a 48-bit RTC counter. - * - * In the lo-res mode, the RTC operates at 1Hz. Overflow interrupts are not - * handled (because the next overflow is not expected until the year 2106). - * - * WARNING: - * Overflow interrupts are lost whenever the STM32 is powered down. The - * overflow interrupt may be lost even if the STM32 is powered down only - * momentarily. Therefore hi-res solution is only useful in systems where - * the power is always on. - */ - -#ifdef CONFIG_RTC_HIRES -# ifndef CONFIG_RTC_FREQUENCY -# error "CONFIG_RTC_FREQUENCY is required for CONFIG_RTC_HIRES" -# elif CONFIG_RTC_FREQUENCY != 16384 -# error "Only hi-res CONFIG_RTC_FREQUENCY of 16384Hz is supported" -# endif -#else -# ifndef CONFIG_RTC_FREQUENCY -# define CONFIG_RTC_FREQUENCY 1 -# endif -# if CONFIG_RTC_FREQUENCY != 1 -# error "Only lo-res CONFIG_RTC_FREQUENCY of 1Hz is supported" -# endif -#endif - -#ifndef CONFIG_STM32_BKP -# error "CONFIG_STM32_BKP is required for CONFIG_STM32_RTC" -#endif - -#ifndef CONFIG_STM32_PWR -# error "CONFIG_STM32_PWR is required for CONFIG_STM32_RTC" -#endif - -#ifdef CONFIG_STM32_STM32F10XX -# if defined(CONFIG_STM32_RTC_HSECLOCK) -# error "RTC with HSE clock not yet implemented for STM32F10XXX" -# elif defined(CONFIG_STM32_RTC_LSICLOCK) -# error "RTC with LSI clock not yet implemented for STM32F10XXX" -# endif -#endif - -/* RTC/BKP Definitions ******************************************************/ - -/* STM32_RTC_PRESCALAR_VALUE - * RTC pre-scalar value. The RTC is driven by a 32,768Hz input clock. - * This input value is divided by this value (plus one) to generate the - * RTC frequency. - * RTC_TIMEMSB_REG - * The BKP module register used to hold the RTC overflow value. - * Overflows are only handled in hi-res mode. - * RTC_CLOCKS_SHIFT - * The shift used to convert the hi-res timer LSB to one second. - * Not used with the lo-res timer. - */ - -#ifdef CONFIG_RTC_HIRES -# define STM32_RTC_PRESCALAR_VALUE STM32_RTC_PRESCALER_MIN -# define RTC_TIMEMSB_REG STM32_BKP_DR1 -# define RTC_CLOCKS_SHIFT 14 -#else -# define STM32_RTC_PRESCALAR_VALUE STM32_RTC_PRESCALER_SECOND -#endif - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -struct rtc_regvals_s -{ - uint16_t cntl; - uint16_t cnth; -#ifdef CONFIG_RTC_HIRES - uint16_t ovf; -#endif -}; - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -static spinlock_t g_rtc_lock = SP_UNLOCKED; - -/* Callback to use when the alarm expires */ - -#ifdef CONFIG_RTC_ALARM -static alarmcb_t g_alarmcb; -#endif - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/* Variable determines the state of the LSE oscillator. - * Possible errors: - * - on start-up - * - during operation, reported by LSE interrupt - */ - -volatile bool g_rtc_enabled = false; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_rtc_waitlasttask - * - * Description: - * wait task done - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -static inline void stm32_rtc_waitlasttask(void) -{ - /* Previous write is done? */ - - while ((getreg16(STM32_RTC_CRL) & RTC_CRL_RTOFF) == 0) - { - stm32_waste(); - } -} - -/**************************************************************************** - * Name: stm32_rtc_beginwr - * - * Description: - * Enter configuration mode - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -static inline void stm32_rtc_beginwr(void) -{ - stm32_rtc_waitlasttask(); - - /* Enter Config mode, Set Value and Exit */ - - modifyreg16(STM32_RTC_CRL, 0, RTC_CRL_CNF); -} - -/**************************************************************************** - * Name: stm32_rtc_endwr - * - * Description: - * Exit configuration mode - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -static inline void stm32_rtc_endwr(void) -{ - modifyreg16(STM32_RTC_CRL, RTC_CRL_CNF, 0); - stm32_rtc_waitlasttask(); -} - -/**************************************************************************** - * Name: stm32_rtc_wait4rsf - * - * Description: - * Wait for registers to synchronise with RTC module, call after power-up - * only - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -static inline void stm32_rtc_wait4rsf(void) -{ - modifyreg16(STM32_RTC_CRL, RTC_CRL_RSF, 0); - while ((getreg16(STM32_RTC_CRL) & RTC_CRL_RSF) == 0) - { - stm32_waste(); - } -} - -/**************************************************************************** - * Name: stm32_rtc_breakout - * - * Description: - * Set the RTC to the provided time. - * - * Input Parameters: - * tp - the time to use - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef CONFIG_RTC_HIRES -static void stm32_rtc_breakout(const struct timespec *tp, - struct rtc_regvals_s *regvals) -{ - uint64_t frac; - uint32_t cnt; - uint16_t ovf; - - /* Break up the time in seconds + milleconds into the correct values for - * our use - */ - - frac = (tp->tv_nsec * CONFIG_RTC_FREQUENCY) / 1000000000; - cnt = (tp->tv_sec << RTC_CLOCKS_SHIFT) | - ((uint32_t)frac & (CONFIG_RTC_FREQUENCY - 1)); - ovf = (tp->tv_sec >> (32 - RTC_CLOCKS_SHIFT)); - - /* Then return the broken out time */ - - regvals->cnth = cnt >> 16; - regvals->cntl = cnt & 0xffff; - regvals->ovf = ovf; -} -#else -static inline void stm32_rtc_breakout(const struct timespec *tp, - struct rtc_regvals_s *regvals) -{ - /* The low-res timer is easy... tv_sec holds exactly the value needed - * by the CNTH/CNTL registers. - */ - - regvals->cnth = (uint16_t)((uint32_t)tp->tv_sec >> 16); - regvals->cntl = (uint16_t)((uint32_t)tp->tv_sec & 0xffff); -} -#endif - -/**************************************************************************** - * Name: stm32_rtc_interrupt - * - * Description: - * RTC interrupt service routine - * - * Input Parameters: - * irq - The IRQ number that generated the interrupt - * context - Architecture specific register save information. - * - * Returned Value: - * Zero (OK) on success; A negated errno value on failure. - * - ****************************************************************************/ - -#if defined(CONFIG_RTC_HIRES) || defined(CONFIG_RTC_ALARM) -static int stm32_rtc_interrupt(int irq, void *context, void *arg) -{ - uint16_t source = getreg16(STM32_RTC_CRL); - -#ifdef CONFIG_RTC_HIRES - if ((source & RTC_CRL_OWF) != 0) - { - stm32_pwr_enablebkp(true); - putreg16(getreg16(RTC_TIMEMSB_REG) + 1, RTC_TIMEMSB_REG); - stm32_pwr_enablebkp(false); - } -#endif - -#ifdef CONFIG_RTC_ALARM - if ((source & RTC_CRL_ALRF) != 0 && g_alarmcb != NULL) - { - /* Alarm callback */ - - g_alarmcb(); - g_alarmcb = NULL; - } -#endif - - /* Clear pending flags, leave RSF high */ - - putreg16(RTC_CRL_RSF, STM32_RTC_CRL); - return 0; -} -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: up_rtc_initialize - * - * Description: - * Initialize the hardware RTC per the selected configuration. - * This function is called once during the OS initialization sequence - * - * Input Parameters: - * None - * - * Returned Value: - * Zero (OK) on success; a negated errno on failure - * - ****************************************************************************/ - -int up_rtc_initialize(void) -{ - uint32_t regval; - - /* Enable write access to the backup domain (RTC registers, RTC backup data - * registers and backup SRAM). - */ - - stm32_pwr_enablebkp(true); - - regval = getreg32(RTC_MAGIC_REG); - if (regval != RTC_MAGIC && regval != RTC_MAGIC_TIME_SET) - { - /* Reset backup domain if bad magic */ - - modifyreg32(STM32_RCC_BDCR, 0, RCC_BDCR_BDRST); - modifyreg32(STM32_RCC_BDCR, RCC_BDCR_BDRST, 0); - - modifyreg16(STM32_RCC_BDCR, 0, RCC_BDCR_LSEON); - - /* Wait for the LSE clock to be ready */ - - while ((getreg16(STM32_RCC_BDCR) & RCC_BDCR_LSERDY) == 0) - { - stm32_waste(); - } - - /* Select the lower power external 32,768Hz (Low-Speed External, LSE) - * oscillator as RTC Clock Source and enable the Clock. - */ - - modifyreg16(STM32_RCC_BDCR, RCC_BDCR_RTCSEL_MASK, RCC_BDCR_RTCSEL_LSE); - - /* Enable RTC and wait for RSF */ - - modifyreg16(STM32_RCC_BDCR, 0, RCC_BDCR_RTCEN); - stm32_rtc_waitlasttask(); - - stm32_rtc_wait4rsf(); - stm32_rtc_waitlasttask(); - - /* Configure prescaler, note that these are write-only registers */ - - stm32_rtc_beginwr(); - putreg16(STM32_RTC_PRESCALAR_VALUE >> 16, STM32_RTC_PRLH); - putreg16(STM32_RTC_PRESCALAR_VALUE & 0xffff, STM32_RTC_PRLL); - stm32_rtc_endwr(); - - stm32_rtc_wait4rsf(); - stm32_rtc_waitlasttask(); - - /* Write the magic register after RTC initialization. */ - - putreg16(RTC_MAGIC, RTC_MAGIC_REG); - } - -#ifdef CONFIG_RTC_HIRES - /* Enable overflow interrupt - alarm interrupt is enabled in - * stm32_rtc_setalarm. - */ - - modifyreg16(STM32_RTC_CRH, 0, RTC_CRH_OWIE); -#endif - - /* TODO: Get state from this function, if everything is - * okay and whether it is already enabled (if it was disabled - * reset upper time register) - */ - - g_rtc_enabled = true; - - /* Alarm Int via EXTI Line */ - - /* STM32_IRQ_RTCALRM 41: RTC alarm through EXTI line interrupt */ - - /* Disable write access to the backup domain - * (RTC registers, RTC backup data registers and backup SRAM). - */ - - stm32_pwr_enablebkp(false); - - return OK; -} - -/**************************************************************************** - * Name: stm32_rtc_irqinitialize - * - * Description: - * Initialize IRQs for RTC, not possible during up_rtc_initialize because - * up_irqinitialize is called later. - * - * Input Parameters: - * None - * - * Returned Value: - * Zero (OK) on success; a negated errno on failure - * - ****************************************************************************/ - -int stm32_rtc_irqinitialize(void) -{ -#if defined(CONFIG_RTC_HIRES) || defined(CONFIG_RTC_ALARM) - /* Configure RTC interrupt to catch overflow and alarm interrupts. */ - - irq_attach(STM32_IRQ_RTC, stm32_rtc_interrupt, NULL); - up_enable_irq(STM32_IRQ_RTC); -#endif - - return OK; -} - -/**************************************************************************** - * Name: up_rtc_time - * - * Description: - * Get the current time in seconds. - * This is similar to the standard time() function. - * This interface is only required if the low-resolution RTC/counter - * hardware implementation selected. It is only used by the RTOS during - * initialization to set up the system time when CONFIG_RTC is set but - * neither CONFIG_RTC_HIRES nor CONFIG_RTC_DATETIME are set. - * - * Input Parameters: - * None - * - * Returned Value: - * The current time in seconds - * - ****************************************************************************/ - -#ifndef CONFIG_RTC_HIRES -time_t up_rtc_time(void) -{ - irqstate_t flags; - uint16_t cnth; - uint16_t cntl; - uint16_t tmp; - - /* The RTC counter is read from two 16-bit registers to form one 32-bit - * value. Because these are non-atomic operations, many things can happen - * between the two reads: This thread could get suspended or interrupted - * or the lower 16-bit counter could rollover between reads. Disabling - * interrupts will prevent suspensions and interruptions: - */ - - flags = spin_lock_irqsave(&g_rtc_lock); - - /* And the following loop will handle any clock rollover events that may - * happen between samples. Most of the time (like 99.9%), the following - * loop will execute only once. In the rare rollover case, it should - * execute no more than 2 times. - */ - - do - { - tmp = getreg16(STM32_RTC_CNTL); - cnth = getreg16(STM32_RTC_CNTH); - cntl = getreg16(STM32_RTC_CNTL); - } - - /* The second sample of CNTL could be less than the first sample of CNTL - * only if rollover occurred. In that case, CNTH may or may not be out - * of sync. The best thing to do is try again until we know that no - * rollover occurred. - */ - - while (cntl < tmp); - spin_unlock_irqrestore(&g_rtc_lock, flags); - - /* Okay.. the samples should be as close together in time as possible and - * we can be assured that no clock rollover occurred between the samples. - * - * Return the time in seconds. - */ - - return (time_t)cnth << 16 | (time_t)cntl; -} -#endif - -/**************************************************************************** - * Name: up_rtc_gettime - * - * Description: - * Get the current time from the high resolution RTC clock/counter. This - * interface is only supported by the high-resolution RTC/counter hardware - * implementation. - * It is used to replace the system timer. - * - * Input Parameters: - * tp - The location to return the high resolution time value. - * - * Returned Value: - * Zero (OK) on success; a negated errno on failure - * - ****************************************************************************/ - -#ifdef CONFIG_RTC_HIRES -int up_rtc_gettime(struct timespec *tp) -{ - irqstate_t flags; - uint32_t ls; - uint32_t ms; - uint16_t ovf; - uint16_t cnth; - uint16_t cntl; - uint16_t tmp; - - /* The RTC counter is read from two 16-bit registers to form one 32-bit - * value. Because these are non-atomic operations, many things can happen - * between the two reads: This thread could get suspended or interrupted - * or the lower 16-bit counter could rollover between reads. Disabling - * interrupts will prevent suspensions and interruptions: - */ - - flags = spin_lock_irqsave(&g_rtc_lock); - - /* And the following loop will handle any clock rollover events that may - * happen between samples. Most of the time (like 99.9%), the following - * loop will execute only once. In the rare rollover case, it should - * execute no more than 2 times. - */ - - do - { - tmp = getreg16(STM32_RTC_CNTL); - cnth = getreg16(STM32_RTC_CNTH); - ovf = getreg16(RTC_TIMEMSB_REG); - cntl = getreg16(STM32_RTC_CNTL); - } - - /* The second sample of CNTL could be less than the first sample of CNTL - * only if rollover occurred. In that case, CNTH may or may not be out - * of sync. The best thing to do is try again until we know that no - * rollover occurred. - */ - - while (cntl < tmp); - spin_unlock_irqrestore(&g_rtc_lock, flags); - - /* Okay.. the samples should be as close together in time as possible and - * we can be assured that no clock rollover occurred between the samples. - * - * Create a 32-bit value from the LS and MS 16-bit RTC counter values and - * from the MS and overflow 16-bit counter values. - */ - - ls = (uint32_t)cnth << 16 | (uint32_t)cntl; - ms = (uint32_t)ovf << 16 | (uint32_t)cnth; - - /* Then we can save the time in seconds and fractional seconds. */ - - tp->tv_sec = (ms << (32 - RTC_CLOCKS_SHIFT - 16)) | - (ls >> (RTC_CLOCKS_SHIFT + 16)); - tp->tv_nsec = (ls & (CONFIG_RTC_FREQUENCY - 1)) * - (1000000000 / CONFIG_RTC_FREQUENCY); - return OK; -} -#endif - -/**************************************************************************** - * Name: up_rtc_settime - * - * Description: - * Set the RTC to the provided time. All RTC implementations must be able - * to set their time based on a standard timespec. - * - * Input Parameters: - * tp - the time to use - * - * Returned Value: - * Zero (OK) on success; a negated errno on failure - * - ****************************************************************************/ - -int up_rtc_settime(const struct timespec *tp) -{ - struct rtc_regvals_s regvals; - irqstate_t flags; - - /* Break out the time values */ - - stm32_rtc_breakout(tp, ®vals); - - /* Enable write access to the backup domain */ - - flags = spin_lock_irqsave(&g_rtc_lock); - stm32_pwr_enablebkp(true); - - /* Then write the broken out values to the RTC counter and BKP overflow - * register (hi-res mode only) - */ - - stm32_rtc_beginwr(); - putreg16(regvals.cnth, STM32_RTC_CNTH); - putreg16(regvals.cntl, STM32_RTC_CNTL); - stm32_rtc_endwr(); - putreg16(RTC_MAGIC_TIME_SET, RTC_MAGIC_REG); - -#ifdef CONFIG_RTC_HIRES - putreg16(regvals.ovf, RTC_TIMEMSB_REG); -#endif - - stm32_pwr_enablebkp(false); - spin_unlock_irqrestore(&g_rtc_lock, flags); - return OK; -} - -/**************************************************************************** - * Name: stm32_rtc_setalarm - * - * Description: - * Set up an alarm. - * - * Input Parameters: - * tp - the time to set the alarm - * callback - the function to call when the alarm expires. - * - * Returned Value: - * Zero (OK) on success; a negated errno on failure - * - ****************************************************************************/ - -#ifdef CONFIG_RTC_ALARM -int stm32_rtc_setalarm(const struct timespec *tp, alarmcb_t callback) -{ - struct rtc_regvals_s regvals; - irqstate_t flags; - uint16_t cr; - int ret = -EBUSY; - - flags = spin_lock_irqsave(&g_rtc_lock); - - /* Is there already something waiting on the ALARM? */ - - if (g_alarmcb == NULL) - { - /* No.. Save the callback function pointer */ - - g_alarmcb = callback; - - /* Break out the time values */ - - stm32_rtc_breakout(tp, ®vals); - - stm32_pwr_enablebkp(true); - - /* Enable RTC alarm */ - - cr = getreg16(STM32_RTC_CRH); - cr |= RTC_CRH_ALRIE; - putreg16(cr, STM32_RTC_CRH); - - /* The set the alarm */ - - stm32_rtc_beginwr(); - putreg16(regvals.cnth, STM32_RTC_ALRH); - putreg16(regvals.cntl, STM32_RTC_ALRL); - stm32_rtc_endwr(); - - stm32_pwr_enablebkp(false); - - ret = OK; - } - - spin_unlock_irqrestore(&g_rtc_lock, flags); - - return ret; -} -#endif - -/**************************************************************************** - * Name: stm32_rtc_cancelalarm - * - * Description: - * Cancel a pending alarm alarm - * - * Input Parameters: - * none - * - * Returned Value: - * Zero (OK) on success; a negated errno on failure - * - ****************************************************************************/ - -#ifdef CONFIG_RTC_ALARM -int stm32_rtc_cancelalarm(void) -{ - irqstate_t flags; - int ret = -ENODATA; - - flags = spin_lock_irqsave(&g_rtc_lock); - - if (g_alarmcb != NULL) - { - /* Cancel the global callback function */ - - g_alarmcb = NULL; - - /* Unset the alarm */ - - stm32_pwr_enablebkp(true); - stm32_rtc_beginwr(); - putreg16(0xffff, STM32_RTC_ALRH); - putreg16(0xffff, STM32_RTC_ALRL); - stm32_rtc_endwr(); - stm32_pwr_enablebkp(false); - - ret = OK; - } - - spin_unlock_irqrestore(&g_rtc_lock, flags); - - return ret; -} -#endif - -/**************************************************************************** - * Name: stm32_rtc_rdalarm - * - * Description: - * Query an alarm configured in hardware. - * - * Input Parameters: - * alminfo - Information about the alarm configuration. - * - * Returned Value: - * Zero (OK) on success; a negated errno on failure - * - ****************************************************************************/ - -#ifdef CONFIG_RTC_ALARM -int stm32_rtc_rdalarm(FAR struct alm_rdalarm_s *alminfo) -{ - struct rtc_regvals_s regvals; - FAR struct timespec tp; - int ret = -EINVAL; - - DEBUGASSERT(alminfo != NULL); - DEBUGASSERT(alminfo->ar_id == 0); - - switch (alminfo->ar_id) - { - case 0: - { - regvals.cnth = getreg16(STM32_RTC_ALRH); - regvals.cntl = getreg16(STM32_RTC_ALRL); - tp.tv_sec = regvals.cnth << 16 | regvals.cntl; - memcpy(alminfo->ar_time, gmtime(&tp.tv_sec), - sizeof(struct tm)); - ret = OK; - } - break; - - default: - rtcerr("ERROR: Invalid ALARM%d\n", alminfo->ar_id); - break; - } - - return ret; -} -#endif diff --git a/arch/arm/src/stm32/stm32_sdadc.c b/arch/arm/src/stm32/stm32_sdadc.c deleted file mode 100644 index 783dd03c6cc28..0000000000000 --- a/arch/arm/src/stm32/stm32_sdadc.c +++ /dev/null @@ -1,1408 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_sdadc.c - * - * SPDX-License-Identifier: BSD-3-Clause - * SPDX-FileCopyrightText: 2015-2017 Gregory Nutt. All rights reserved. - * SPDX-FileCopyrightText: 2009, 2011 Gregory Nutt. All rights reserved. - * SPDX-FileCopyrightText: 2016 Studelec. All rights reserved. - * SPDX-FileContributor: Gregory Nutt - * SPDX-FileContributor: Marc Rechté - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include - -#include "arm_internal.h" -#include "chip.h" -#include "stm32.h" -#include "stm32_dma.h" -#include "stm32_pwr.h" -#include "stm32_sdadc.h" - -#ifdef CONFIG_STM32_SDADC - -/* Some SDADC peripheral must be enabled */ - -#if defined(CONFIG_STM32_SDADC1) || defined(CONFIG_STM32_SDADC2) || \ - defined(CONFIG_STM32_SDADC3) - -/* This implementation is for the STM32F37XX only */ - -#ifndef CONFIG_STM32_STM32F37XX -# error "This chip is not yet supported" -#endif - -/* TODO: At the moment there is no implementation - * for timer and external triggers - */ - -#if defined(SDADC_HAVE_TIMER) -# error "There is no proper implementation for TIMER TRIGGERS at the moment" -#endif - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* RCC reset ****************************************************************/ - -#define STM32_RCC_RSTR STM32_RCC_APB2RSTR -#define RCC_RSTR_SDADC1RST RCC_APB2RSTR_SDADC1RST -#define RCC_RSTR_SDADC2RST RCC_APB2RSTR_SDADC2RST -#define RCC_RSTR_SDADC3RST RCC_APB2RSTR_SDADC3RST - -/* SDADC interrupts *********************************************************/ - -#define SDADC_ISR_ALLINTS (SDADC_ISR_JEOCF | SDADC_ISR_JOVRF) - -/* SDADC Channels/DMA *******************************************************/ - -#define SDADC_DMA_CONTROL_WORD (DMA_CCR_MSIZE_16BITS | \ - DMA_CCR_PSIZE_16BITS | \ - DMA_CCR_MINC | \ - DMA_CCR_CIRC) - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/* This structure describes the state of one SDADC block */ - -struct stm32_dev_s -{ - const struct adc_callback_s *cb; - uint8_t irq; /* Interrupt generated by this SDADC block */ - uint8_t nchannels; /* Number of channels */ - uint8_t cchannels; /* Number of configured channels */ - uint8_t intf; /* SDADC interface number */ - uint8_t current; /* Current SDADC channel being converted */ - uint8_t refv; /* Reference voltage selection */ -#ifdef SDADC_HAVE_DMA - uint8_t dmachan; /* DMA channel needed by this SDADC */ - bool hasdma; /* True: This channel supports DMA */ -#endif -#ifdef SDADC_HAVE_TIMER - uint8_t trigger; /* Timer trigger selection: see SDADCx_JEXTSEL_TIMxx */ -#endif - uint32_t base; /* Base address of registers unique to this SDADC - * block */ -#ifdef SDADC_HAVE_TIMER - uint32_t tbase; /* Base address of timer used by this SDADC block */ - uint32_t jextsel; /* JEXTSEL value used by this SDADC block */ - uint32_t pclck; /* The PCLK frequency that drives this timer */ - uint32_t freq; /* The desired frequency of conversions */ -#endif -#ifdef SDADC_HAVE_DMA - DMA_HANDLE dma; /* Allocated DMA channel */ - - /* DMA transfer buffer */ - - int16_t dmabuffer[SDADC_MAX_SAMPLES]; -#endif - - /* List of selected SDADC injected channels to sample */ - - uint8_t chanlist[SDADC_MAX_SAMPLES]; -}; - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -/* ADC Register access */ - -static uint32_t sdadc_getreg(struct stm32_dev_s *priv, int offset); -static void sdadc_putreg(struct stm32_dev_s *priv, int offset, - uint32_t value); -static void sdadc_modifyreg(struct stm32_dev_s *priv, int offset, - uint32_t clrbits, uint32_t setbits); -#ifdef ADC_HAVE_TIMER -static uint16_t tim_getreg(struct stm32_dev_s *priv, int offset); -static void tim_putreg(struct stm32_dev_s *priv, int offset, - uint16_t value); -static void tim_modifyreg(struct stm32_dev_s *priv, int offset, - uint16_t clrbits, uint16_t setbits); -static void tim_dumpregs(struct stm32_dev_s *priv, - const char *msg); -#endif - -static void sdadc_rccreset(struct stm32_dev_s *priv, bool reset); - -/* ADC Interrupt Handler */ - -static int sdadc_interrupt(int irq, void *context, void *arg); - -/* ADC Driver Methods */ - -static int sdadc_bind(struct adc_dev_s *dev, - const struct adc_callback_s *callback); -static void sdadc_reset(struct adc_dev_s *dev); -static int sdadc_setup(struct adc_dev_s *dev); -static void sdadc_shutdown(struct adc_dev_s *dev); -static void sdadc_rxint(struct adc_dev_s *dev, bool enable); -static int sdadc_ioctl(struct adc_dev_s *dev, int cmd, - unsigned long arg); -static void sdadc_enable(struct stm32_dev_s *priv, bool enable); - -static int sdadc_set_ch(struct adc_dev_s *dev, uint8_t ch); - -#ifdef ADC_HAVE_TIMER -static void sdadc_timstart(struct stm32_dev_s *priv, bool enable); -static int sdadc_timinit(struct stm32_dev_s *priv); -#endif - -#ifdef ADC_HAVE_DMA -static void sdadc_dmaconvcallback(DMA_HANDLE handle, uint8_t isr, - void *arg); -#endif - -static void sdadc_startconv(struct stm32_dev_s *priv, bool enable); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* SDADC interface operations */ - -static const struct adc_ops_s g_sdadcops = -{ - .ao_bind = sdadc_bind, - .ao_reset = sdadc_reset, - .ao_setup = sdadc_setup, - .ao_shutdown = sdadc_shutdown, - .ao_rxint = sdadc_rxint, - .ao_ioctl = sdadc_ioctl, -}; - -/* SDADC1 state */ - -#ifdef CONFIG_STM32_SDADC1 -static struct stm32_dev_s g_sdadcpriv1 = -{ - .irq = STM32_IRQ_SDADC1, - .intf = 1, - .base = STM32_SDADC1_BASE, - .refv = SDADC1_REFV, -#ifdef SDADC1_HAVE_TIMER - .trigger = CONFIG_STM32_SDADC1_TIMTRIG, - .tbase = SDADC1_TIMER_BASE, - .extsel = SDADC1_EXTSEL_VALUE, - .pclck = SDADC1_TIMER_PCLK_FREQUENCY, - .freq = CONFIG_STM32_SDADC1_SAMPLE_FREQUENCY, -#endif -#ifdef SDADC1_HAVE_DMA - .dmachan = DMACHAN_SDADC1, - .hasdma = true, -#endif -}; - -static struct adc_dev_s g_sdadcdev1 = -{ - .ad_ops = &g_sdadcops, - .ad_priv = &g_sdadcpriv1, -}; -#endif - -/* SDADC2 state */ - -#ifdef CONFIG_STM32_SDADC2 -static struct stm32_dev_s g_sdadcpriv2 = -{ - .irq = STM32_IRQ_SDADC2, - .base = STM32_SDADC2_BASE, - .refv = SDADC2_REFV, -#ifdef SDADC2_HAVE_TIMER - .trigger = CONFIG_STM32_SDADC2_TIMTRIG, - .tbase = SDADC2_TIMER_BASE, - .extsel = SDADC2_EXTSEL_VALUE, - .pclck = SDADC2_TIMER_PCLK_FREQUENCY, - .freq = CONFIG_STM32_SDADC2_SAMPLE_FREQUENCY, -#endif -#ifdef SDADC2_HAVE_DMA - .dmachan = DMACHAN_SDADC2, - .hasdma = true, -#endif -}; - -static struct adc_dev_s g_sdadcdev2 = -{ - .ad_ops = &g_sdadcops, - .ad_priv = &g_sdadcpriv2, -}; -#endif - -/* SDADC3 state */ - -#ifdef CONFIG_STM32_SDADC3 -static struct stm32_dev_s g_sdadcpriv3 = -{ - .irq = STM32_IRQ_SDADC3, - .base = STM32_SDADC3_BASE, - .refv = SDADC3_REFV, -#ifdef SDADC3_HAVE_TIMER - .trigger = CONFIG_STM32_SDADC3_TIMTRIG, - .tbase = SDADC3_TIMER_BASE, - .extsel = SDADC3_EXTSEL_VALUE, - .pclck = SDADC3_TIMER_PCLK_FREQUENCY, - .freq = CONFIG_STM32_SDADC3_SAMPLE_FREQUENCY, -#endif -#ifdef SDADC3_HAVE_DMA - .dmachan = DMACHAN_SDADC3, - .hasdma = true, -#endif -}; - -static struct adc_dev_s g_sdadcdev3 = -{ - .ad_ops = &g_sdadcops, - .ad_priv = &g_sdadcpriv3, -}; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: sdadc_getreg - * - * Description: - * Read the value of an SDADC register. - * - * Input Parameters: - * priv - A reference to the SDADC block state - * offset - The offset to the register to read - * - * Returned Value: - * The current contents of the specified register - * - ****************************************************************************/ - -static uint32_t sdadc_getreg(struct stm32_dev_s *priv, int offset) -{ - return getreg32(priv->base + offset); -} - -/**************************************************************************** - * Name: sdadc_putreg - * - * Description: - * Write a value to an SDADC register. - * - * Input Parameters: - * priv - A reference to the SDADC block state - * offset - The offset to the register to write to - * value - The value to write to the register - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void sdadc_putreg(struct stm32_dev_s *priv, int offset, - uint32_t value) -{ - putreg32(value, priv->base + offset); -} - -/**************************************************************************** - * Name: sdadc_modifyreg - * - * Description: - * Modify the value of an SDADC register (not atomic). - * - * Input Parameters: - * priv - A reference to the SDADC block state - * offset - The offset to the register to modify - * clrbits - The bits to clear - * setbits - The bits to set - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void sdadc_modifyreg(struct stm32_dev_s *priv, int offset, - uint32_t clrbits, uint32_t setbits) -{ - sdadc_putreg(priv, offset, - (sdadc_getreg(priv, offset) & ~clrbits) | setbits); -} - -/**************************************************************************** - * Name: tim_getreg - * - * Description: - * Read the value of an SDADC timer register. - * - * Input Parameters: - * priv - A reference to the SDADC block state - * offset - The offset to the register to read - * - * Returned Value: - * The current contents of the specified register - * - ****************************************************************************/ - -#ifdef SDADC_HAVE_TIMER -static uint16_t tim_getreg(struct stm32_dev_s *priv, int offset) -{ - return getreg16(priv->tbase + offset); -} -#endif - -/**************************************************************************** - * Name: tim_putreg - * - * Description: - * Write a value to an SDADC timer register. - * - * Input Parameters: - * priv - A reference to the SDADC block state - * offset - The offset to the register to write to - * value - The value to write to the register - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef SDADC_HAVE_TIMER -static void tim_putreg(struct stm32_dev_s *priv, int offset, - uint16_t value) -{ - putreg16(value, priv->tbase + offset); -} -#endif - -/**************************************************************************** - * Name: tim_modifyreg - * - * Description: - * Modify the value of an SDADC timer register (not atomic). - * - * Input Parameters: - * priv - A reference to the SDADC block state - * offset - The offset to the register to modify - * clrbits - The bits to clear - * setbits - The bits to set - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef SDADC_HAVE_TIMER -static void tim_modifyreg(struct stm32_dev_s *priv, int offset, - uint16_t clrbits, uint16_t setbits) -{ - tim_putreg(priv, offset, (tim_getreg(priv, offset) & ~clrbits) | setbits); -} -#endif - -/**************************************************************************** - * Name: tim_dumpregs - * - * Description: - * Dump all timer registers. - * - * Input Parameters: - * priv - A reference to the SDADC block state - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef SDADC_HAVE_TIMER -static void tim_dumpregs(struct stm32_dev_s *priv, const char *msg) -{ - ainfo("%s:\n", msg); - - /* TODO */ -} -#endif - -/**************************************************************************** - * Name: sdadc_timstart - * - * Description: - * Start (or stop) the timer counter - * - * Input Parameters: - * priv - A reference to the SDADC block state - * enable - True: Start conversion - * - * Returned Value: - * - ****************************************************************************/ - -#ifdef SDADC_HAVE_TIMER -static void sdadc_timstart(struct stm32_dev_s *priv, bool enable) -{ - ainfo("enable: %d\n", enable ? 1 : 0); - - if (enable) - { - /* Start the counter */ - - tim_modifyreg(priv, STM32_GTIM_CR1_OFFSET, 0, GTIM_CR1_CEN); - } - else - { - /* Disable the counter */ - - tim_modifyreg(priv, STM32_GTIM_CR1_OFFSET, GTIM_CR1_CEN, 0); - } -} -#endif - -/**************************************************************************** - * Name: sdadc_timinit - * - * Description: - * Initialize the timer that drivers the SDADC sampling for this channel - * using the pre-calculated timer divider definitions. - * - * Input Parameters: - * priv - A reference to the SDADC block state - * - * Returned Value: - * Zero on success; a negated errno value on failure. - * - ****************************************************************************/ - -#ifdef SDADC_HAVE_TIMER -static int sdadc_timinit(struct stm32_dev_s *priv) -{ - /* TODO */ - - aerr("ERROR: not implemented"); - return ERROR; -} -#endif - -/**************************************************************************** - * Name: sdadc_startconv - * - * Description: - * Start (or stop) the SDADC conversion process - * - * Input Parameters: - * priv - A reference to the SDADC block state - * enable - True: Start conversion - * - * Returned Value: - * - ****************************************************************************/ - -static void sdadc_startconv(struct stm32_dev_s *priv, bool enable) -{ - ainfo("enable: %d\n", enable ? 1 : 0); - - if (enable) - { - /* Start the conversion of injected channels */ - - sdadc_modifyreg(priv, STM32_SDADC_CR2_OFFSET, 0, SDADC_CR2_JSWSTART); - } - else - { - /* Wait for a possible conversion to stop */ - - while ((sdadc_getreg(priv, - STM32_SDADC_ISR_OFFSET) & SDADC_ISR_JCIP) != 0); - } -} - -/**************************************************************************** - * Name: sdadc_rccreset - * - * Description: - * (De)Initializes the SDADC block registers to their default - * reset values. - * - * Input Parameters: - * priv - A reference to the SDADC block state - * reset - true: to put in reset state, false: to revert to normal state - * - * Returned Value: - * - ****************************************************************************/ - -static void sdadc_rccreset(struct stm32_dev_s *priv, bool reset) -{ - uint32_t adcbit; - - /* Pick the appropriate bit in the APB2 reset register. - */ - - switch (priv->intf) - { -#ifdef CONFIG_STM32_SDADC1 - case 1: - adcbit = RCC_RSTR_SDADC1RST; - break; -#endif -#ifdef CONFIG_STM32_SDADC2 - case 2: - adcbit = RCC_RSTR_SDADC2RST; - break; -#endif -#ifdef CONFIG_STM32_SDADC3 - case 3: - adcbit = RCC_RSTR_SDADC3RST; - break; -#endif - default: - return; - } - - /* Set or clear the selected bit in the APB2 reset register. - * modifyreg32() disables interrupts. Disabling interrupts is necessary - * because the APB2RSTR register is used by several different drivers. - */ - - if (reset) - { - /* Enable SDADC reset state */ - - modifyreg32(STM32_RCC_RSTR, 0, adcbit); - } - else - { - /* Release SDADC from reset state */ - - modifyreg32(STM32_RCC_RSTR, adcbit, 0); - } -} - -/**************************************************************************** - * Name: sdadc_power_down_idle - * - * Description: - * Enables or disables power down during the idle phase. - * - * Input Parameters: - * priv - A reference to the SDADC block state - * pdi_high - true: The SDADC is powered down when waiting for a start - * event - * false: The SDADC is powered up when waiting for a start event - * - * Returned Value: - * None. - * - ****************************************************************************/ - -#if 0 -static void sdadc_power_down_idle(struct stm32_dev_s *priv, - bool pdi_high) -{ - uint32_t regval; - - ainfo("PDI: %d\n", pdi_high ? 1 : 0); - - regval = sdadc_getreg(priv, STM32_SDADC_CR2_OFFSET); - - if ((regval & SDADC_CR2_ADON) == 0) - { - regval = sdadc_getreg(priv, STM32_SDADC_CR1_OFFSET); - if (pdi_high) - { - regval |= SDADC_CR1_PDI; - } - else - { - regval &= ~SDADC_CR1_PDI; - } - - sdadc_putreg(priv, STM32_SDADC_CR1_OFFSET, regval); - } -} -#endif - -/**************************************************************************** - * Name: sdadc_enable - * - * Description: - * Enables or disables the specified SDADC peripheral. - * Does not start conversion unless the SDADC is - * triggered by timer - * - * Input Parameters: - * priv - A reference to the SDADC block state - * enable - true: enable SDADC conversion - * false: disable SDADC conversion - * - * Returned Value: - * - ****************************************************************************/ - -static void sdadc_enable(struct stm32_dev_s *priv, bool enable) -{ - uint32_t regval; - - ainfo("enable: %d\n", enable ? 1 : 0); - - regval = sdadc_getreg(priv, STM32_SDADC_CR2_OFFSET); - - if (enable) - { - /* Enable the SDADC */ - - sdadc_putreg(priv, STM32_SDADC_CR2_OFFSET, regval | SDADC_CR2_ADON); - - /* Wait for the SDADC to be stabilized */ - - while (sdadc_getreg(priv, STM32_SDADC_ISR_OFFSET) & SDADC_ISR_STABIP); - } - else if ((regval & SDADC_CR2_ADON) != 0) - { - /* Ongoing conversions will be stopped implicitly */ - - /* Disable the SDADC */ - - sdadc_putreg(priv, STM32_SDADC_CR2_OFFSET, regval & ~SDADC_CR2_ADON); - } -} - -/**************************************************************************** - * Name: sdadc_dmaconvcallback - * - * Description: - * Callback for DMA. Called from the DMA transfer complete interrupt after - * all channels have been converted and transferred with DMA. - * - * Input Parameters: - * handle - handle to DMA - * isr - - * arg - SDADC device - * - * Returned Value: - * - ****************************************************************************/ - -#ifdef SDADC_HAVE_DMA -static void sdadc_dmaconvcallback(DMA_HANDLE handle, - uint8_t isr, void *arg) -{ - struct adc_dev_s *dev = (struct adc_dev_s *)arg; - struct stm32_dev_s *priv = (struct stm32_dev_s *)dev->ad_priv; - int i; - - /* Verify that the upper-half driver has bound its callback functions */ - - if (priv->cb != NULL) - { - DEBUGASSERT(priv->cb->au_receive != NULL); - - for (i = 0; i < priv->nchannels; i++) - { - priv->cb->au_receive(dev, priv->chanlist[priv->current], - priv->dmabuffer[priv->current]); - priv->current++; - if (priv->current >= priv->nchannels) - { - /* Restart the conversion sequence from the beginning */ - - priv->current = 0; - } - } - } -} -#endif - -/**************************************************************************** - * Name: sdadc_bind - * - * Description: - * Bind the upper-half driver callbacks to the lower-half implementation. - * This must be called early in order to receive SDADC event notifications. - * - ****************************************************************************/ - -static int sdadc_bind(struct adc_dev_s *dev, - const struct adc_callback_s *callback) -{ - struct stm32_dev_s *priv = (struct stm32_dev_s *)dev->ad_priv; - - DEBUGASSERT(priv != NULL); - priv->cb = callback; - return OK; -} - -/**************************************************************************** - * Name: sdadc_reset - * - * Description: - * Reset the SDADC device. - * This is firstly called whenever the SDADC device is registered by - * sdadc_register() - * Does mostly the SDAC register setting. - * Leave the device in power down mode. - * Note that SDACx clock is already enable (for all SDADC) by the - * rcc_enableapb2() - * - * Input Parameters: - * dev - pointer to the sdadc device structure - * - * Returned Value: - * - ****************************************************************************/ - -static void sdadc_reset(struct adc_dev_s *dev) -{ - struct stm32_dev_s *priv = (struct stm32_dev_s *)dev->ad_priv; - irqstate_t flags; - uint32_t setbits = 0; - - ainfo("intf: %d\n", priv->intf); - - /* TODO: why critical ? */ - - flags = enter_critical_section(); - - /* Enable SDADC reset state */ - - sdadc_rccreset(priv, true); - - /* Enable power */ - - stm32_pwr_enablesdadc(priv->intf); - - /* Release SDADC from reset state */ - - sdadc_rccreset(priv, false); - - /* Enable the SDADC (and wait until it stabilizes) */ - - sdadc_enable(priv, true); - - /* Put SDADC in in initialization mode */ - - sdadc_putreg(priv, STM32_SDADC_CR1_OFFSET, SDADC_CR1_INIT); - - /* Wait for the SDADC to be ready */ - - while ((sdadc_getreg(priv, - STM32_SDADC_ISR_OFFSET) & - SDADC_ISR_INITRDY) == 0); - - /* Load configurations */ - - sdadc_putreg(priv, STM32_SDADC_CONF0R_OFFSET, SDADC_CONF0R_DEFAULT); - sdadc_putreg(priv, STM32_SDADC_CONF1R_OFFSET, SDADC_CONF1R_DEFAULT); - sdadc_putreg(priv, STM32_SDADC_CONF2R_OFFSET, SDADC_CONF2R_DEFAULT); - - sdadc_putreg(priv, STM32_SDADC_CONFCHR1_OFFSET, SDADC_CONFCHR1_DEFAULT); - sdadc_putreg(priv, STM32_SDADC_CONFCHR2_OFFSET, SDADC_CONFCHR2_DEFAULT); - - /* Configuration of the injected channels group */ - - sdadc_set_ch(dev, 0); - - /* CR1 ********************************************************************/ - - /* Enable interrupt / dma flags, is done later by upper half when opening - * device by calling sdadc_rxint() - */ - - setbits = SDADC_CR1_INIT; /* remains in init mode while configuring */ - - /* Reference voltage */ - - setbits |= priv->refv; - - /* Set CR1 configuration */ - - sdadc_putreg(priv, STM32_SDADC_CR1_OFFSET, setbits); - - /* CR2 ********************************************************************/ - - setbits = SDADC_CR2_ADON; /* leave it ON ! */ - - /* TODO: JEXTEN / JEXTSEL */ - - /* Number of calibrations is for 3 configurations */ - - setbits |= (2 << SDADC_CR2_CALIBCNT_SHIFT); - - /* Set CR2 configuration */ - - sdadc_putreg(priv, STM32_SDADC_CR2_OFFSET, setbits); - - /* Release INIT mode ******************************************************/ - - sdadc_modifyreg(priv, STM32_SDADC_CR1_OFFSET, SDADC_CR1_INIT, 0); - - /* Calibrate the SDADC */ - - sdadc_modifyreg(priv, STM32_SDADC_CR2_OFFSET, 0, SDADC_CR2_STARTCALIB); - - /* Wait for the calibration to complete (may take up to 5ms) */ - - while ((sdadc_getreg(priv, - STM32_SDADC_ISR_OFFSET) & SDADC_ISR_EOCALF) == 0); - - /* Clear this flag */ - - sdadc_modifyreg(priv, - STM32_SDADC_CLRISR_OFFSET, SDADC_CLRISR_CLREOCALF, 0); - -#ifdef SDADC_HAVE_TIMER - if (priv->tbase != 0) - { - ret = sdadc_timinit(priv); - if (ret < 0) - { - aerr("ERROR: sdadc_timinit failed: %d\n", ret); - } - } -#endif - - /* Put the device in low power mode until it is actually used by - * application code. - */ - - sdadc_enable(priv, false); - - leave_critical_section(flags); - - ainfo("CR1: 0x%08" PRIx32 " CR2: 0x%08" PRIx32 "\n", - sdadc_getreg(priv, STM32_SDADC_CR1_OFFSET), - sdadc_getreg(priv, STM32_SDADC_CR2_OFFSET)); - - ainfo("CONF0R: 0x%08" PRIx32 " CONF1R: 0x%08" PRIx32 - " CONF3R: 0x%08" PRIx32 "\n", - sdadc_getreg(priv, STM32_SDADC_CONF0R_OFFSET), - sdadc_getreg(priv, STM32_SDADC_CONF1R_OFFSET), - sdadc_getreg(priv, STM32_SDADC_CONF2R_OFFSET)); - - ainfo("CONFCHR1: 0x%08" PRIx32 " CONFCHR2: 0x%08" PRIx32 - " JCHGR: 0x%08" PRIx32 "\n", - sdadc_getreg(priv, STM32_SDADC_CONFCHR1_OFFSET), - sdadc_getreg(priv, STM32_SDADC_CONFCHR2_OFFSET), - sdadc_getreg(priv, STM32_SDADC_JCHGR_OFFSET)); -} - -/**************************************************************************** - * Name: sdadc_setup - * - * Description: - * Configure the ADC. This method is called the first time that the SDADC - * device is opened. - * This is called by the upper half driver sdadc_open(). - * This will occur when the port is first - * opened in the application code (/dev/sdadcN). - * It would be called again after closing all references to this file and - * reopening it. - * This function wakes up the device and setup the DMA / IRQ - * - * Input Parameters: - * dev - pointer to the sdadc device structure - * - * Returned Value: - * - ****************************************************************************/ - -static int sdadc_setup(struct adc_dev_s *dev) -{ - struct stm32_dev_s *priv = (struct stm32_dev_s *)dev->ad_priv; - int ret; - - /* Wakes up the device */ - - sdadc_enable(priv, true); - - /* Setup DMA or interrupt control. Note that either DMA or interrupt is - * setup not both. - */ - -#ifdef SDADC_HAVE_DMA - if (priv->hasdma) - { - /* Setup DMA */ - - /* Stop and free DMA if it was started before */ - - if (priv->dma != NULL) - { - stm32_dmastop(priv->dma); - stm32_dmafree(priv->dma); - } - - priv->dma = stm32_dmachannel(priv->dmachan); - - stm32_dmasetup(priv->dma, - priv->base + STM32_SDADC_JDATAR_OFFSET, - (uint32_t)priv->dmabuffer, - priv->nchannels, - SDADC_DMA_CONTROL_WORD); - - stm32_dmastart(priv->dma, sdadc_dmaconvcallback, dev, false); - } - else - { - /* Attach the SDADC interrupt */ - - ret = irq_attach(priv->irq, sdadc_interrupt, dev); - if (ret < 0) - { - ainfo("irq_attach failed: %d\n", ret); - return ret; - } - } -#else - /* Attach the SDADC interrupt */ - - ret = irq_attach(priv->irq, sdadc_interrupt, dev); - if (ret < 0) - { - ainfo("irq_attach failed: %d\n", ret); - return ret; - } -#endif - - return OK; -} - -/**************************************************************************** - * Name: sdadc_shutdown - * - * Description: - * Disable the ADC. This method is called when the last instance - * of the SDADC device is closed by the user application. - * This method reverses the operation the setup method. - * - * Input Parameters: - * dev - pointer to the sdadc device structure - * - * Returned Value: - * - ****************************************************************************/ - -static void sdadc_shutdown(struct adc_dev_s *dev) -{ - struct stm32_dev_s *priv = (struct stm32_dev_s *)dev->ad_priv; - - /* Put the device in low power mode */ - - sdadc_enable(priv, false); - - /* Disable interrupt / dma */ - - sdadc_rxint(dev, false); - -#ifdef SDADC_HAVE_DMA - if (priv->hasdma) - { - /* Stop and free DMA if it was started before */ - - if (priv->dma != NULL) - { - stm32_dmastop(priv->dma); - stm32_dmafree(priv->dma); - } - } - else - { - /* Disable ADC interrupts and detach the SDADC interrupt handler */ - - up_disable_irq(priv->irq); - irq_detach(priv->irq); - } -#else - /* Disable ADC interrupts and detach the SDADC interrupt handler */ - - up_disable_irq(priv->irq); - irq_detach(priv->irq); -#endif -} - -/**************************************************************************** - * Name: sdadc_rxint - * - * Description: - * Call to enable or disable RX interrupts. - * - * Input Parameters: - * - * Returned Value: - * - ****************************************************************************/ - -static void sdadc_rxint(struct adc_dev_s *dev, bool enable) -{ - struct stm32_dev_s *priv = (struct stm32_dev_s *)dev->ad_priv; - uint32_t setbits; - - ainfo("intf: %d enable: %d\n", priv->intf, enable ? 1 : 0); - - /* DMA mode */ - -#ifdef SDADC_HAVE_DMA - if (priv->hasdma) - { - setbits = SDADC_CR1_JDMAEN; /* DMA enabled for injected channels group */ - } - else - { - /* Interrupt enable for injected channel group overrun - * and end of conversion - */ - - setbits = SDADC_CR1_JOVRIE | SDADC_CR1_JEOCIE; - } -#else - setbits = SDADC_CR1_JOVRIE | SDADC_CR1_JEOCIE; -#endif - - if (enable) - { - /* Enable */ - - sdadc_modifyreg(priv, STM32_SDADC_CR1_OFFSET, 0, setbits); - } - else - { - /* Disable all ADC interrupts and DMA */ - - sdadc_modifyreg(priv, STM32_SDADC_CR1_OFFSET, - SDADC_CR1_JOVRIE | SDADC_CR1_JEOCIE | SDADC_CR1_JDMAEN, - 0); - } -} - -/**************************************************************************** - * Name: sdadc_set_ch - * - * Description: - * Sets the SDADC injected channel group. - * - * Input Parameters: - * dev - pointer to device structure used by the driver - * ch - ADC channel number + 1. 0 reserved for all configured channels - * - * Returned Value: - * int - errno - * - ****************************************************************************/ - -static int sdadc_set_ch(struct adc_dev_s *dev, uint8_t ch) -{ - struct stm32_dev_s *priv = (struct stm32_dev_s *)dev->ad_priv; - uint32_t bits = 0; - int i; - - if (ch == 0) - { - priv->current = 0; - priv->nchannels = priv->cchannels; - } - else - { - for (i = 0; i < priv->cchannels && priv->chanlist[i] != ch - 1; i++); - - if (i >= priv->cchannels) - { - return -ENODEV; - } - - priv->current = i; - priv->nchannels = 1; - } - - for (i = 0; i < priv->nchannels; i++) - { - bits |= (uint32_t)(1 << priv->chanlist[i]); - } - - sdadc_putreg(priv, STM32_SDADC_JCHGR_OFFSET, bits); - - return OK; -} - -/**************************************************************************** - * Name: sdadc_ioctl - * - * Description: - * All ioctl calls will be routed through this method. - * - * Input Parameters: - * dev - pointer to device structure used by the driver - * cmd - command - * arg - arguments passed with command - * - * Returned Value: - * - ****************************************************************************/ - -static int sdadc_ioctl(struct adc_dev_s *dev, int cmd, unsigned long arg) -{ - struct stm32_dev_s *priv = (struct stm32_dev_s *)dev->ad_priv; - int ret = OK; - - switch (cmd) - { - case ANIOC_TRIGGER: - { - sdadc_startconv(priv, true); - } - break; - - case ANIOC_GET_NCHANNELS: - { - /* Return the number of configured channels */ - - ret = priv->cchannels; - } - break; - - default: - { - aerr("ERROR: Unknown cmd: %d\n", cmd); - ret = -ENOTTY; - } - break; - } - - return ret; -} - -/**************************************************************************** - * Name: sdadc_interrupt - * - * Description: - * Common SDADC interrupt handler. - * - * Input Parameters: - * - * Returned Value: - * - ****************************************************************************/ - -static int sdadc_interrupt(int irq, void *context, void *arg) -{ - struct adc_dev_s *dev = (struct adc_dev_s *)arg; - struct stm32_dev_s *priv; - uint32_t regval; - uint32_t pending; - int32_t data; - uint8_t chan; - - DEBUGASSERT(dev != NULL && dev->ad_priv != NULL); - priv = (struct stm32_dev_s *)dev->ad_priv; - - regval = sdadc_getreg(priv, STM32_SDADC_ISR_OFFSET); - pending = regval & SDADC_ISR_ALLINTS; - if (pending == 0) - { - return OK; - } - - /* JOVRF: overrun flag */ - - if ((regval & SDADC_ISR_JOVRF) != 0) - { - awarn("WARNING: Overrun has occurred!\n"); - } - - /* JEOCF: End of conversion */ - - if ((regval & SDADC_ISR_JEOCF) != 0) - { - /* Read the converted value and clear JEOCF bit - * (It is cleared by reading the SDADC_JDATAR) - */ - - data = sdadc_getreg(priv, - STM32_SDADC_JDATAR_OFFSET) & - SDADC_JDATAR_JDATA_MASK; - chan = sdadc_getreg(priv, - STM32_SDADC_JDATAR_OFFSET) & - SDADC_JDATAR_JDATACH_MASK; - - DEBUGASSERT(priv->chanlist[priv->current] == chan); - - /* Verify that the upper-half driver has bound its callback functions */ - - if (priv->cb != NULL) - { - /* Give the SDADC data to the ADC driver. The ADC receive() method - * accepts 3 parameters: - * - * 1) The first is the ADC device instance for this SDADC block. - * 2) The second is the channel number for the data, and - * 3) The third is the converted data for the channel. - */ - - DEBUGASSERT(priv->cb->au_receive != NULL); - priv->cb->au_receive(dev, chan, data); - } - - /* Set the channel number of the next channel that will complete - * conversion. - */ - - priv->current++; - - if (priv->current >= priv->nchannels) - { - /* Restart the conversion sequence from the beginning */ - - priv->current = 0; - } - - /* do no clear this interrupt (cleared by reading data) */ - - pending &= ~SDADC_ISR_JEOCF; - } - - /* Clears interrupt flags, if any */ - - if (pending) - { - sdadc_putreg(priv, STM32_SDADC_CLRISR_OFFSET, pending); - } - - return OK; -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_sdadcinitialize - * - * Description: - * Initialize one SDADC block - * - * The logic is, save and initialize the channel list in the private driver - * structure and return the corresponding adc device structure. - * - * Each SDADC will convert the channels indicated each - * time a conversion is triggered either by software, timer or external - * event. Channels are numbered from 0 - 8 and must be given in order - * (contrarily to what says ST RM0313 doc !!!). - * - * Input Parameters: - * intf - Could be {1,2,3} for SDADC1, SDADC2, or SDADC3 - * chanlist - The list of channels eg. { 0, 3, 7, 8 } - * cchannels - Number of channels - * - * Returned Value: - * Valid ADC device structure reference on success; a NULL on failure - * - ****************************************************************************/ - -struct adc_dev_s *stm32_sdadcinitialize(int intf, - const uint8_t *chanlist, - int cchannels) -{ - struct adc_dev_s *dev; - struct stm32_dev_s *priv; - int i; - - ainfo("intf: %d cchannels: %d\n", intf, cchannels); - - switch (intf) - { -#ifdef CONFIG_STM32_SDADC1 - case 1: - ainfo("SDADC1 selected\n"); - dev = &g_sdadcdev1; - break; -#endif -#ifdef CONFIG_STM32_SDADC2 - case 2: - ainfo("SDADC2 selected\n"); - dev = &g_sdadcdev2; - break; -#endif -#ifdef CONFIG_STM32_SDADC3 - case 3: - ainfo("SDADC3 selected\n"); - dev = &g_sdadcdev3; - break; -#endif - default: - aerr("ERROR: No SDADC interface defined\n"); - return NULL; - } - - /* Check channel list in order */ - - DEBUGASSERT((cchannels <= SDADC_MAX_SAMPLES) && (cchannels > 0)); - for (i = 0; i < cchannels - 1; i++) - { - if (chanlist[i] >= chanlist[i + 1]) - { - aerr("ERROR: SDADC channel list must be given in order\n"); - return NULL; - } - } - - /* Configure the selected SDADC */ - - priv = (struct stm32_dev_s *)dev->ad_priv; - - priv->cb = NULL; - priv->cchannels = cchannels; - - memcpy(priv->chanlist, chanlist, cchannels); - - return dev; -} - -#endif /* CONFIG_STM32_SDADC1 || CONFIG_STM32_SDADC2 || - * CONFIG_STM32_SDADC3 */ -#endif /* CONFIG_STM32_SDADC */ diff --git a/arch/arm/src/stm32/stm32_sdadc.h b/arch/arm/src/stm32/stm32_sdadc.h deleted file mode 100644 index 75d474efa568d..0000000000000 --- a/arch/arm/src/stm32/stm32_sdadc.h +++ /dev/null @@ -1,431 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_sdadc.h - * - * SPDX-License-Identifier: BSD-3-Clause - * SPDX-FileCopyrightText: 2015 Gregory Nutt. All rights reserved. - * SPDX-FileCopyrightText: 2009, 2011 Gregory Nutt. All rights reserved. - * SPDX-FileCopyrightText: 2016 Studelec. All rights reserved. - * SPDX-FileContributor: Gregory Nutt - * SPDX-FileContributor: Marc Rechté - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32_STM32_SDADC_H -#define __ARCH_ARM_SRC_STM32_STM32_SDADC_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "chip.h" - -#if defined(CONFIG_STM32_STM32F37XX) -# include "hardware/stm32f37xxx_sdadc.h" -#else -/* No generic chip/stm32_sdadc.h yet */ - -# error "This chip is not yet supported" -#endif - -#include - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -/* Timer devices may be used for different purposes. One special purpose - * is to control periodic SDADC sampling. If CONFIG_STM32_TIMn is defined - * then CONFIG_STM32_TIMn_SDADC must also be defined to indicate that timer - * "n" is intended to be used for that purpose. - */ - -/* For the STM32 F37XX line, timers 2-4, 12-17 an 19 may be used. */ - -/* TODO cf. stm32_adc.h */ - -/* Up to 3 SDADC interfaces are supported */ - -#if STM32_NSDADC < 3 -# undef CONFIG_STM32_SDADC3 -#endif - -#if STM32_NSDADC < 2 -# undef CONFIG_STM32_SDADC2 -#endif - -#if STM32_NSDADC < 1 -# undef CONFIG_STM32_SDADC1 -#endif - -#if defined(CONFIG_STM32_SDADC1) || defined(CONFIG_STM32_SDADC2) || \ - defined(CONFIG_STM32_SDADC3) - -/* DMA support */ - -#if defined(CONFIG_STM32_SDADC1_DMA) || defined(CONFIG_STM32_SDADC2_DMA) || \ - defined(CONFIG_STM32_SDADC3_DMA) -# define SDADC_HAVE_DMA 1 -#endif - -#ifdef CONFIG_STM32_SDADC1_DMA -# define SDADC1_HAVE_DMA 1 -#else -# undef SDADC1_HAVE_DMA -#endif - -#ifdef CONFIG_STM32_SDADC2_DMA -# define SDADC2_HAVE_DMA 1 -#else -# undef SDADC2_HAVE_DMA -#endif - -#ifdef CONFIG_STM32_SDADC3_DMA -# define SDADC3_HAVE_DMA 1 -#else -# undef SDADC3_HAVE_DMA -#endif - -/* SDADC Channels/DMA ******************************************************* - * The maximum number of channels that can be sampled at each scan. - * If DMA support is not enabled, then only a single channel - * ought to be sampled. - * Otherwise, unless sampling frequency is reduced, - * data overruns would occur. - */ - -#define SDADC_MAX_CHANNELS_DMA 9 -#define SDADC_MAX_CHANNELS_NODMA 1 - -#ifndef SDADC_MAX_SAMPLES -#ifdef SDADC_HAVE_DMA -# define SDADC_MAX_SAMPLES SDADC_MAX_CHANNELS_DMA -#else -# define SDADC_MAX_SAMPLES SDADC_MAX_CHANNELS_NODMA -#endif -#endif - -/* Timer configuration: If a timer trigger is specified, then get - * information about the timer. - */ - -#if defined(CONFIG_STM32_TIM3_SDADC1) -# define SDADC1_HAVE_TIMER 1 -# define SDADC1_TIMER_BASE STM32_TIM3_BASE -# define SDADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM3_CLKIN -#elif defined(CONFIG_STM32_TIM4_SDADC1) -# define SDADC1_HAVE_TIMER 1 -# define SDADC1_TIMER_BASE STM32_TIM4_BASE -# define SDADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM4_CLKIN -#elif defined(CONFIG_STM32_TIM13_SDADC1) -# define SDADC1_HAVE_TIMER 1 -# define SDADC1_TIMER_BASE STM32_TIM13_BASE -# define SDADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM13_CLKIN -#elif defined(CONFIG_STM32_TIM14_SDADC1) -# define SDADC1_HAVE_TIMER 1 -# define SDADC1_TIMER_BASE STM32_TIM14_BASE -# define SDADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM14_CLKIN -#elif defined(CONFIG_STM32_TIM15_SDADC1) -# define SDADC1_HAVE_TIMER 1 -# define SDADC1_TIMER_BASE STM32_TIM15_BASE -# define SDADC1_TIMER_PCLK_FREQUENCY STM32_APB2_TIM15_CLKIN -#elif defined(CONFIG_STM32_TIM19_SDADC1) -# define SDADC1_HAVE_TIMER 1 -# define SDADC1_TIMER_BASE STM32_TIM19_BASE -# define SDADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM19_CLKIN -#else -# undef SDADC1_HAVE_TIMER -#endif - -#ifdef SDADC1_HAVE_TIMER -# ifndef CONFIG_STM32_SDADC1_SAMPLE_FREQUENCY -# error "CONFIG_STM32_SDADC1_SAMPLE_FREQUENCY not defined" -# endif -# ifndef CONFIG_STM32_SDADC1_TIMTRIG -# error "CONFIG_STM32_SDADC1_TIMTRIG not defined" -# warning "Values 0:TIM13_CH1 1:TIM14_CH1 2:TIM15_CH2 3:TIM3_CH1 4:TIM4_CH1 5:TIM19_CH2" -# endif -#endif - -#if defined(CONFIG_STM32_TIM2_SDADC2) -# define SDADC2_HAVE_TIMER 1 -# define SDADC2_TIMER_BASE STM32_TIM2_BASE -# define SDADC2_TIMER_PCLK_FREQUENCY STM32_APB1_TIM2_CLKIN -#elif defined(CONFIG_STM32_TIM3_SDADC2) -# define SDADC2_HAVE_TIMER 1 -# define SDADC2_TIMER_BASE STM32_TIM3_BASE -# define SDADC2_TIMER_PCLK_FREQUENCY STM32_APB1_TIM3_CLKIN -#elif defined(CONFIG_STM32_TIM4_SDADC2) -# define SDADC2_HAVE_TIMER 1 -# define SDADC2_TIMER_BASE STM32_TIM4_BASE -# define SDADC2_TIMER_PCLK_FREQUENCY STM32_APB1_TIM4_CLKIN -#elif defined(CONFIG_STM32_TIM12_SDADC2) -# define SDADC2_HAVE_TIMER 1 -# define SDADC2_TIMER_BASE STM32_TIM12_BASE -# define SDADC2_TIMER_PCLK_FREQUENCY STM32_APB1_TIM12_CLKIN -#elif defined(CONFIG_STM32_TIM17_SDADC2) -# define SDADC2_HAVE_TIMER 1 -# define SDADC2_TIMER_BASE STM32_TIM17_BASE -# define SDADC2_TIMER_PCLK_FREQUENCY STM32_APB2_TIM17_CLKIN -#elif defined(CONFIG_STM32_TIM19_SDADC2) -# define SDADC2_HAVE_TIMER 1 -# define SDADC2_TIMER_BASE STM32_TIM19_BASE -# define SDADC2_TIMER_PCLK_FREQUENCY STM32_APB1_TIM19_CLKIN -#else -# undef SDADC2_HAVE_TIMER -#endif - -#ifdef SDADC2_HAVE_TIMER -# ifndef CONFIG_STM32_SDADC2_SAMPLE_FREQUENCY -# error "CONFIG_STM32_SDADC2_SAMPLE_FREQUENCY not defined" -# endif -# ifndef CONFIG_STM32_SDADC2_TIMTRIG -# error "CONFIG_STM32_SDADC2_TIMTRIG not defined" -# warning "Values 0:TIM17_CH1 1:TIM12_CH1 2:TIM2_CH3 3:TIM3_CH2 4:TIM4_CH2 5:TIM19_CH3" -# endif -#endif - -#if defined(CONFIG_STM32_TIM2_SDADC3) -# define SDADC3_HAVE_TIMER 1 -# define SDADC3_TIMER_BASE STM32_TIM2_BASE -# define SDADC3_TIMER_PCLK_FREQUENCY STM32_APB1_TIM2_CLKIN -#elif defined(CONFIG_STM32_TIM3_SDADC3) -# define SDADC3_HAVE_TIMER 1 -# define SDADC3_TIMER_BASE STM32_TIM3_BASE -# define SDADC3_TIMER_PCLK_FREQUENCY STM32_APB1_TIM3_CLKIN -#elif defined(CONFIG_STM32_TIM4_SDADC3) -# define SDADC3_HAVE_TIMER 1 -# define SDADC3_TIMER_BASE STM32_TIM4_BASE -# define SDADC3_TIMER_PCLK_FREQUENCY STM32_APB1_TIM4_CLKIN -#elif defined(CONFIG_STM32_TIM12_SDADC3) -# define SDADC3_HAVE_TIMER 1 -# define SDADC3_TIMER_BASE STM32_TIM12_BASE -# define SDADC3_TIMER_PCLK_FREQUENCY STM32_APB1_TIM12_CLKIN -#elif defined(CONFIG_STM32_TIM16_SDADC3) -# define SDADC3_HAVE_TIMER 1 -# define SDADC3_TIMER_BASE STM32_TIM16_BASE -# define SDADC3_TIMER_PCLK_FREQUENCY STM32_APB2_TIM16_CLKIN -#elif defined(CONFIG_STM32_TIM19_SDADC3) -# define SDADC3_HAVE_TIMER 1 -# define SDADC3_TIMER_BASE STM32_TIM19_BASE -# define SDADC3_TIMER_PCLK_FREQUENCY STM32_APB1_TIM19_CLKIN -#else -# undef SDADC3_HAVE_TIMER -#endif - -#ifdef SDADC3_HAVE_TIMER -# ifndef CONFIG_STM32_SDADC3_SAMPLE_FREQUENCY -# error "CONFIG_STM32_SDADC3_SAMPLE_FREQUENCY not defined" -# endif -# ifndef CONFIG_STM32_SDADC3_TIMTRIG -# error "CONFIG_STM32_SDADC3_TIMTRIG not defined" -# warning "Values 0:TIM16_CH1 1:TIM12_CH2 2:TIM2_CH4 3:TIM3_CH3 4:TIM4_CH3 5:TIM19_CH4" -# endif -#endif - -#if defined(SDADC1_HAVE_TIMER) || defined(SDADC2_HAVE_TIMER) || \ - defined(SDADC3_HAVE_TIMER) -# define SDADC_HAVE_TIMER 1 -# if defined(CONFIG_STM32_STM32F37XX) && !defined(CONFIG_STM32_FORCEPOWER) -# warning "CONFIG_STM32_FORCEPOWER must be defined to enable the timer(s)" -# endif -#else -# undef SDADC_HAVE_TIMER -#endif - -/* NOTE: The following assumes that all possible combinations of timers and - * values are support JEXTSEL. That is not so and it varies from one STM32 - * to another. But this (wrong) assumptions keeps the logic as simple as - * possible. If unsupported combination is used, an error will show up - * later during compilation although it may be difficult to track it back - * to this simplification. - * - * STM32L37XX-family has 3 SDADC onboard - */ - -#ifdef CONFIG_STM32_STM32F37XX -# define SDADC1_JEXTSEL_TIM13_CH1 SDADC1_CR2_JEXTSEL_TIM13_CH1 -# define SDADC1_JEXTSEL_TIM14_CH1 SDADC1_CR2_JEXTSEL_TIM14_CH1 -# define SDADC1_JEXTSEL_TIM15_CH2 SDADC1_CR2_JEXTSEL_TIM15_CH2 -# define SDADC1_JEXTSEL_TIM3_CH1 SDADC1_CR2_JEXTSEL_TIM3_CH1 -# define SDADC1_JEXTSEL_TIM4_CH1 SDADC1_CR2_JEXTSEL_TIM4_CH1 -# define SDADC1_JEXTSEL_TIM19_CH2 SDADC1_CR2_JEXTSEL_TIM19_CH2 -# define SDADC1_JEXTSEL_EXTI15 SDADC1_CR2_JEXTSEL_EXTI15 -# define SDADC1_JEXTSEL_EXTI11 SDADC1_CR2_JEXTSEL_EXTI11 -# define SDADC2_JEXTSEL_TIM17_CH1 SDADC2_CR2_JEXTSEL_TIM17_CH1 -# define SDADC2_JEXTSEL_TIM12_CH1 SDADC2_CR2_JEXTSEL_TIM12_CH1 -# define SDADC2_JEXTSEL_TIM2_CH3 SDADC2_CR2_JEXTSEL_TIM2_CH3 -# define SDADC2_JEXTSEL_TIM3_CH2 SDADC2_CR2_JEXTSEL_TIM3_CH2 -# define SDADC2_JEXTSEL_TIM4_CH2 SDADC2_CR2_JEXTSEL_TIM4_CH2 -# define SDADC2_JEXTSEL_TIM19_CH3 SDADC2_CR2_JEXTSEL_TIM19_CH3 -# define SDADC2_JEXTSEL_EXTI15 SDADC2_CR2_JEXTSEL_EXTI15 -# define SDADC2_JEXTSEL_EXTI11 SDADC2_CR2_JEXTSEL_EXTI11 -# define SDADC3_JEXTSEL_TIM16_CH1 SDADC3_CR2_JEXTSEL_TIM16_CH1 -# define SDADC3_JEXTSEL_TIM12_CH1 SDADC3_CR2_JEXTSEL_TIM12_CH1 -# define SDADC3_JEXTSEL_TIM2_CH4 SDADC3_CR2_JEXTSEL_TIM2_CH4 -# define SDADC3_JEXTSEL_TIM3_CH3 SDADC3_CR2_JEXTSEL_TIM3_CH3 -# define SDADC3_JEXTSEL_TIM4_CH3 SDADC3_CR2_JEXTSEL_TIM4_CH3 -# define SDADC3_JEXTSEL_TIM19_CH4 SDADC3_CR2_JEXTSEL_TIM19_CH4 -# define SDADC3_JEXTSEL_EXTI15 SDADC3_CR2_JEXTSEL_EXTI15 -# define SDADC3_JEXTSEL_EXTI11 SDADC3_CR2_JEXTSEL_EXTI11 -#endif - -#if defined(CONFIG_STM32_TIM3_SDADC1) -# define SDADC1_JEXTSEL_VALUE 3 -#elif defined(CONFIG_STM32_TIM4_SDADC1) -# define SDADC1_JEXTSEL_VALUE 4 -#elif defined(CONFIG_STM32_TIM13_SDADC1) -# define SDADC1_JEXTSEL_VALUE 0 -#elif defined(CONFIG_STM32_TIM14_SDADC1) -# define SDADC1_JEXTSEL_VALUE 1 -#elif defined(CONFIG_STM32_TIM15_SDADC1) -# define SDADC1_JEXTSEL_VALUE 2 -#elif defined(CONFIG_STM32_TIM19_SDADC1) -# define SDADC1_JEXTSEL_VALUE 5 -#else -# undef SDADC1_JEXTSEL_VALUE -#endif - -#if defined(CONFIG_STM32_TIM2_SDADC2) -# define SDADC2_JEXTSEL_VALUE 2 -#elif defined(CONFIG_STM32_TIM3_SDADC2) -# define SDADC2_JEXTSEL_VALUE 3 -#elif defined(CONFIG_STM32_TIM4_SDADC2) -# define SDADC2_JEXTSEL_VALUE 4 -#elif defined(CONFIG_STM32_TIM12_SDADC2) -# define SDADC2_JEXTSEL_VALUE 1 -#elif defined(CONFIG_STM32_TIM17_SDADC2) -# define SDADC2_JEXTSEL_VALUE 0 -#elif defined(CONFIG_STM32_TIM19_SDADC2) -# define SDADC2_JEXTSEL_VALUE 5 -#else -# undef SDADC2_JEXTSEL_VALUE -#endif - -#if defined(CONFIG_STM32_TIM2_SDADC3) -# define SDADC3_JEXTSEL_VALUE 2 -#elif defined(CONFIG_STM32_TIM3_SDADC3) -# define SDADC3_JEXTSEL_VALUE 3 -#elif defined(CONFIG_STM32_TIM4_SDADC3) -# define SDADC3_JEXTSEL_VALUE 4 -#elif defined(CONFIG_STM32_TIM12_SDADC3) -# define SDADC3_JEXTSEL_VALUE 1 -#elif defined(CONFIG_STM32_TIM16_SDADC3) -# define SDADC3_JEXTSEL_VALUE 0 -#elif defined(CONFIG_STM32_TIM19_SDADC3) -# define SDADC3_JEXTSEL_VALUE 5 -#else -# undef SDADC3_JEXTSEL_VALUE -#endif - -/* SDADC Configurations ***************************************************** - * Up to 3 configuration profiles may be defined in order to define: - * - calibration method - * - SE/differential mode - * - input gain - * Each of the 9 SDADC channels is assigned to a configuration profile - */ -#ifndef SDADC_CONF0R_DEFAULT -# define SDADC_CONF0R_DEFAULT (SDADC_CONFR_GAIN_1X | SDADC_CONFR_SE_SE_OFFSET | SDADC_CONFR_COMMON_GND) -#endif -#ifndef SDADC_CONF1R_DEFAULT -# define SDADC_CONF1R_DEFAULT (SDADC_CONFR_GAIN_2X | SDADC_CONFR_SE_SE_OFFSET | SDADC_CONFR_COMMON_GND) -#endif -#ifndef SDADC_CONF2R_DEFAULT -# define SDADC_CONF2R_DEFAULT (SDADC_CONFR_GAIN_4X | SDADC_CONFR_SE_SE_OFFSET | SDADC_CONFR_COMMON_GND) -#endif -#ifndef SDADC_CONFCHR1_DEFAULT -# define SDADC_CONFCHR1_DEFAULT ((SDADC_CONF0R << SDADC_CONFCHR1_CH_SHIFT(0)) | \ - (SDADC_CONF0R << SDADC_CONFCHR1_CH_SHIFT(1)) | \ - (SDADC_CONF0R << SDADC_CONFCHR1_CH_SHIFT(2)) | \ - (SDADC_CONF0R << SDADC_CONFCHR1_CH_SHIFT(3)) | \ - (SDADC_CONF0R << SDADC_CONFCHR1_CH_SHIFT(4)) | \ - (SDADC_CONF0R << SDADC_CONFCHR1_CH_SHIFT(5)) | \ - (SDADC_CONF0R << SDADC_CONFCHR1_CH_SHIFT(6)) | \ - (SDADC_CONF0R << SDADC_CONFCHR1_CH_SHIFT(7))) -#endif -#ifndef SDADC_CONFCHR2_DEFAULT -# define SDADC_CONFCHR2_DEFAULT (SDADC_CONF0R << SDADC_CONFCHR2_CH8_SHIFT) -#endif - -/* SDADC Reference voltage selection ****************************************/ - -#ifndef SDADC_REFV_DEFAULT -# define SDADC_REFV_DEFAULT SDADC_CR1_REFV_EXT -#endif -#ifndef SDADC1_REFV -# define SDADC1_REFV SDADC_REFV_DEFAULT -#endif -#ifndef SDADC2_REFV -# define SDADC2_REFV SDADC_REFV_DEFAULT -#endif -#ifndef SDADC3_REFV -# define SDADC3_REFV SDADC_REFV_DEFAULT -#endif - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -#ifndef __ASSEMBLY__ -#ifdef __cplusplus -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Name: stm32_sdadcinitialize - * - ****************************************************************************/ - -struct adc_dev_s *stm32_sdadcinitialize(int intf, - const uint8_t *chanlist, - int nchannels); - -#undef EXTERN -#ifdef __cplusplus -} -#endif -#endif /* __ASSEMBLY__ */ - -#endif /* CONFIG_STM32_SDADC1 || CONFIG_STM32_SDADC2 || - * CONFIG_STM32_SDADC3 - */ -#endif /* __ARCH_ARM_SRC_STM32_STM32_SDADC_H */ diff --git a/arch/arm/src/stm32/stm32_sdio.c b/arch/arm/src/stm32/stm32_sdio.c deleted file mode 100644 index 5d6e5cfc44126..0000000000000 --- a/arch/arm/src/stm32/stm32_sdio.c +++ /dev/null @@ -1,3194 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_sdio.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include - -#include -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32.h" -#include "stm32_dma.h" -#include "stm32_sdio.h" - -#ifdef CONFIG_STM32_SDIO - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -/* Required system configuration options: - * - * CONFIG_ARCH_DMA - Enable architecture-specific DMA subsystem - * initialization. Required if CONFIG_STM32_SDIO_DMA is enabled. - * CONFIG_STM32_DMA2 - Enable STM32 DMA2 support. Required if - * CONFIG_STM32_SDIO_DMA is enabled - * CONFIG_SCHED_WORKQUEUE -- Callback support requires work queue support. - * - * Driver-specific configuration options: - * - * CONFIG_SDIO_MUXBUS - Setting this configuration enables some locking - * APIs to manage concurrent accesses on the SDIO bus. This is not - * needed for the simple case of a single SD card, for example. - * CONFIG_STM32_SDIO_DMA - Enable SDIO. This is a marginally optional. - * For most usages, SDIO will cause data overruns if used without DMA. - * NOTE the above system DMA configuration options. - * CONFIG_STM32_SDIO_WIDTH_D1_ONLY - This may be selected to force the - * driver operate with only a single data line (the default is to use - * all 4 SD data lines). - * CONFIG_SDM_DMAPRIO - SDIO DMA priority. This can be selected if - * CONFIG_STM32_SDIO_DMA is enabled. - * CONFIG_SDIO_XFRDEBUG - Enables some very low-level debug output - * This also requires CONFIG_DEBUG_FS and CONFIG_DEBUG_INFO - */ - -#if !defined(CONFIG_STM32_SDIO_DMA) -# warning "Large Non-DMA transfer may result in RX overrun failures" -#else -# ifndef CONFIG_STM32_DMA2 -# error "CONFIG_STM32_SDIO_DMA support requires CONFIG_STM32_DMA2" -# endif -# ifndef CONFIG_SDIO_DMA -# error CONFIG_SDIO_DMA must be defined with CONFIG_STM32_SDIO_DMA -# endif -#endif - -#ifndef CONFIG_STM32_SDIO_DMA -# warning "Large Non-DMA transfer may result in RX overrun failures" -#endif - -#ifndef CONFIG_SCHED_WORKQUEUE -# error "Callback support requires CONFIG_SCHED_WORKQUEUE" -#endif - -#ifdef CONFIG_STM32_SDIO_DMA -# ifndef CONFIG_STM32_SDIO_DMAPRIO -# if defined(CONFIG_STM32_STM32F10XX) -# define CONFIG_STM32_SDIO_DMAPRIO DMA_CCR_PRIMED -# elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) -# define CONFIG_STM32_SDIO_DMAPRIO DMA_SCR_PRIVERYHI -# else -# error "Unknown STM32 DMA" -# endif -# endif -# if defined(CONFIG_STM32_STM32F10XX) -# if (CONFIG_STM32_SDIO_DMAPRIO & ~DMA_CCR_PL_MASK) != 0 -# error "Illegal value for CONFIG_STM32_SDIO_DMAPRIO" -# endif -# elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) -# if (CONFIG_STM32_SDIO_DMAPRIO & ~DMA_SCR_PL_MASK) != 0 -# error "Illegal value for CONFIG_STM32_SDIO_DMAPRIO" -# endif -# else -# error "Unknown STM32 DMA" -# endif -#else -# undef CONFIG_STM32_SDIO_DMAPRIO -#endif - -#ifndef CONFIG_DEBUG_MEMCARD_INFO -# undef CONFIG_SDIO_XFRDEBUG -#endif - -/* Enable the SDIO pull-up resistors if needed */ - -#ifdef CONFIG_STM32_SDIO_PULLUP -# define SDIO_PULLUP_ENABLE GPIO_PULLUP -#else -# define SDIO_PULLUP_ENABLE 0 -#endif - -/* Friendly CLKCR bit re-definitions ****************************************/ - -#define SDIO_CLKCR_RISINGEDGE (0) -#define SDIO_CLKCR_FALLINGEDGE SDIO_CLKCR_NEGEDGE - -/* Use the default of the rising edge but allow a configuration, - * that does not have the errata, to override the edge the SDIO - * command and data is changed on. - */ - -#if !defined(SDIO_CLKCR_EDGE) -# define SDIO_CLKCR_EDGE SDIO_CLKCR_RISINGEDGE -#endif - -/* Mode dependent settings. These depend on clock divisor settings that must - * be defined in the board-specific board.h header file: SDIO_INIT_CLKDIV, - * SDIO_MMCXFR_CLKDIV, and SDIO_SDXFR_CLKDIV. - */ - -#define STM32_CLCKCR_INIT (SDIO_INIT_CLKDIV | SDIO_CLKCR_EDGE | \ - SDIO_CLKCR_WIDBUS_D1) -#define SDIO_CLKCR_MMCXFR (SDIO_MMCXFR_CLKDIV | SDIO_CLKCR_EDGE | \ - SDIO_CLKCR_WIDBUS_D1) -#define SDIO_CLCKR_SDXFR (SDIO_SDXFR_CLKDIV | SDIO_CLKCR_EDGE | \ - SDIO_CLKCR_WIDBUS_D1) -#define SDIO_CLCKR_SDWIDEXFR (SDIO_SDXFR_CLKDIV | SDIO_CLKCR_EDGE | \ - SDIO_CLKCR_WIDBUS_D4) - -/* Timing */ - -#define SDIO_CMDTIMEOUT (100000) -#define SDIO_LONGTIMEOUT (0x7fffffff) - -/* DTIMER setting */ - -/* Assuming Max timeout in bypass 48 Mhz */ - -#define IP_CLCK_FREQ UINT32_C(48000000) -#define SDIO_DTIMER_DATATIMEOUT_MS 250 - -/* DMA channel/stream configuration register settings. The following - * must be selected. The DMA driver will select the remaining fields. - * - * - 32-bit DMA - * - Memory increment - * - Direction (memory-to-peripheral, peripheral-to-memory) - * - Memory burst size (F4 only) - */ - -/* STM32 F1 channel configuration register (CCR) settings */ - -#if defined(CONFIG_STM32_STM32F10XX) -# define SDIO_RXDMA32_CONFIG (CONFIG_STM32_SDIO_DMAPRIO | DMA_CCR_MSIZE_32BITS | \ - DMA_CCR_PSIZE_32BITS | DMA_CCR_MINC) -# define SDIO_TXDMA32_CONFIG (CONFIG_STM32_SDIO_DMAPRIO | DMA_CCR_MSIZE_32BITS | \ - DMA_CCR_PSIZE_32BITS | DMA_CCR_MINC | DMA_CCR_DIR) - -/* STM32 F4 stream configuration register (SCR) settings. */ - -#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) -# define SDIO_RXDMA32_CONFIG (DMA_SCR_PFCTRL | DMA_SCR_DIR_P2M|DMA_SCR_MINC | \ - DMA_SCR_PSIZE_32BITS | DMA_SCR_MSIZE_32BITS | \ - CONFIG_STM32_SDIO_DMAPRIO | DMA_SCR_PBURST_INCR4 | \ - DMA_SCR_MBURST_INCR4) -# define SDIO_TXDMA32_CONFIG (DMA_SCR_PFCTRL | DMA_SCR_DIR_M2P | DMA_SCR_MINC | \ - DMA_SCR_PSIZE_32BITS | DMA_SCR_MSIZE_32BITS | \ - CONFIG_STM32_SDIO_DMAPRIO | DMA_SCR_PBURST_INCR4 | \ - DMA_SCR_MBURST_INCR4) -#else -# error "Unknown STM32 DMA" -#endif - -/* SDIO DMA Channel/Stream selection. For the case of the STM32 F4, there - * are multiple DMA stream options that must be dis-ambiguated in the board.h - * file. - */ - -#if defined(CONFIG_STM32_STM32F10XX) -# define SDIO_DMACHAN DMACHAN_SDIO -#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) -# define SDIO_DMACHAN DMAMAP_SDIO -#else -# error "Unknown STM32 DMA" -#endif - -/* FIFO sizes */ - -#define SDIO_HALFFIFO_WORDS (8) -#define SDIO_HALFFIFO_BYTES (8*4) - -/* Data transfer interrupt mask bits */ - -#define SDIO_RECV_MASK (SDIO_MASK_DCRCFAILIE | SDIO_MASK_DTIMEOUTIE | \ - SDIO_MASK_DATAENDIE | SDIO_MASK_RXOVERRIE | \ - SDIO_MASK_RXFIFOHFIE | SDIO_MASK_STBITERRIE) -#define SDIO_SEND_MASK (SDIO_MASK_DCRCFAILIE | SDIO_MASK_DTIMEOUTIE | \ - SDIO_MASK_DATAENDIE | SDIO_MASK_TXUNDERRIE | \ - SDIO_MASK_TXFIFOHEIE | SDIO_MASK_STBITERRIE) -#define SDIO_DMARECV_MASK (SDIO_MASK_DCRCFAILIE | SDIO_MASK_DTIMEOUTIE | \ - SDIO_MASK_DATAENDIE | SDIO_MASK_RXOVERRIE | \ - SDIO_MASK_STBITERRIE) -#define SDIO_DMASEND_MASK (SDIO_MASK_DCRCFAILIE | SDIO_MASK_DTIMEOUTIE | \ - SDIO_MASK_DATAENDIE | SDIO_MASK_TXUNDERRIE | \ - SDIO_MASK_STBITERRIE) - -/* Event waiting interrupt mask bits */ - -#define SDIO_CMDDONE_STA (SDIO_STA_CMDSENT) -#define SDIO_RESPDONE_STA (SDIO_STA_CTIMEOUT | SDIO_STA_CCRCFAIL | \ - SDIO_STA_CMDREND) -#define SDIO_XFRDONE_STA (0) - -#define SDIO_CMDDONE_MASK (SDIO_MASK_CMDSENTIE) -#define SDIO_RESPDONE_MASK (SDIO_MASK_CCRCFAILIE | SDIO_MASK_CTIMEOUTIE | \ - SDIO_MASK_CMDRENDIE) -#define SDIO_XFRDONE_MASK (0) - -#define SDIO_CMDDONE_ICR (SDIO_ICR_CMDSENTC | SDIO_ICR_DBCKENDC) -#define SDIO_RESPDONE_ICR (SDIO_ICR_CTIMEOUTC | SDIO_ICR_CCRCFAILC | \ - SDIO_ICR_CMDRENDC | SDIO_ICR_DBCKENDC) -#define SDIO_XFRDONE_ICR (SDIO_ICR_DATAENDC | SDIO_ICR_DCRCFAILC | \ - SDIO_ICR_DTIMEOUTC | SDIO_ICR_RXOVERRC | \ - SDIO_ICR_TXUNDERRC | SDIO_ICR_STBITERRC | \ - SDIO_ICR_DBCKENDC) - -#define SDIO_WAITALL_ICR (SDIO_CMDDONE_ICR | SDIO_RESPDONE_ICR | \ - SDIO_XFRDONE_ICR | SDIO_ICR_DBCKENDC) - -/* Let's wait until we have both SDIO transfer complete and DMA complete. */ - -#define SDIO_XFRDONE_FLAG (1) -#define SDIO_DMADONE_FLAG (2) -#define SDIO_ALLDONE (3) - -/* Register logging support */ - -#ifdef CONFIG_SDIO_XFRDEBUG -# ifdef CONFIG_STM32_SDIO_DMA -# define SAMPLENDX_BEFORE_SETUP 0 -# define SAMPLENDX_BEFORE_ENABLE 1 -# define SAMPLENDX_AFTER_SETUP 2 -# define SAMPLENDX_END_TRANSFER 3 -# define SAMPLENDX_DMA_CALLBACK 4 -# define DEBUG_NSAMPLES 5 -# else -# define SAMPLENDX_BEFORE_SETUP 0 -# define SAMPLENDX_AFTER_SETUP 1 -# define SAMPLENDX_END_TRANSFER 2 -# define DEBUG_NSAMPLES 3 -# endif -#endif - -#define STM32_SDIO_USE_DEFAULT_BLOCKSIZE ((uint8_t)-1) - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/* This structure defines the state of the STM32 SDIO interface */ - -struct stm32_dev_s -{ - struct sdio_dev_s dev; /* Standard, base SDIO interface */ - - /* STM32-specific extensions */ - - /* Event support */ - - sem_t waitsem; /* Implements event waiting */ - sdio_eventset_t waitevents; /* Set of events to be waited for */ - uint32_t waitmask; /* Interrupt enables for event waiting */ - volatile sdio_eventset_t wkupevent; /* The event that caused the wakeup */ - struct wdog_s waitwdog; /* Watchdog that handles event timeouts */ - - /* Callback support */ - - sdio_statset_t cdstatus; /* Card status */ - sdio_eventset_t cbevents; /* Set of events to be cause callbacks */ - worker_t callback; /* Registered callback function */ - void *cbarg; /* Registered callback argument */ - struct work_s cbwork; /* Callback work queue structure */ - - /* Interrupt mode data transfer support */ - - uint32_t *buffer; /* Address of current R/W buffer */ - size_t remaining; /* Number of bytes remaining in the transfer */ - uint32_t xfrmask; /* Interrupt enables for data transfer */ - -#ifdef CONFIG_STM32_SDIO_CARD - /* Interrupt at SDIO_D1 pin, only for SDIO cards */ - - uint32_t sdiointmask; /* STM32 SDIO register mask */ - int (*do_sdio_card)(void *); /* SDIO card ISR */ - void *do_sdio_arg; /* arg for SDIO card ISR */ -#endif - - /* Fixed transfer block size support */ - -#ifdef CONFIG_SDIO_BLOCKSETUP - uint8_t block_size; -#endif - - /* DMA data transfer support */ - - bool widebus; /* Required for DMA support */ -#ifdef CONFIG_STM32_SDIO_DMA - volatile uint8_t xfrflags; /* Used to synchronize SDIO and - * DMA completion events */ - bool dmamode; /* true: DMA mode transfer */ - DMA_HANDLE dma; /* Handle for DMA channel */ -#endif -}; - -/* Register logging support */ - -#ifdef CONFIG_SDIO_XFRDEBUG -struct stm32_sdioregs_s -{ - uint8_t power; - uint16_t clkcr; - uint16_t dctrl; - uint32_t dtimer; - uint32_t dlen; - uint32_t dcount; - uint32_t sta; - uint32_t mask; - uint32_t fifocnt; -}; - -struct stm32_sampleregs_s -{ - struct stm32_sdioregs_s sdio; -#if defined(CONFIG_DEBUG_DMA_INFO) && defined(CONFIG_STM32_SDIO_DMA) - struct stm32_dmaregs_s dma; -#endif -}; -#endif - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -/* Low-level helpers ********************************************************/ - -static inline void stm32_setclkcr(uint32_t clkcr); -static void stm32_configwaitints(struct stm32_dev_s *priv, uint32_t waitmask, - sdio_eventset_t waitevents, sdio_eventset_t wkupevents); -static void stm32_configxfrints(struct stm32_dev_s *priv, uint32_t xfrmask); -static void stm32_setpwrctrl(uint32_t pwrctrl); - -/* DMA Helpers **************************************************************/ - -#ifdef CONFIG_SDIO_XFRDEBUG -static void stm32_sampleinit(void); -static void stm32_sdiosample(struct stm32_sdioregs_s *regs); -static void stm32_sample(struct stm32_dev_s *priv, int index); -static void stm32_sdiodump(struct stm32_sdioregs_s *regs, const char *msg); -static void stm32_dumpsample(struct stm32_dev_s *priv, - struct stm32_sampleregs_s *regs, const char *msg); -static void stm32_dumpsamples(struct stm32_dev_s *priv); -#else -# define stm32_sampleinit() -# define stm32_sample(priv,index) -# define stm32_dumpsamples(priv) -#endif - -#ifdef CONFIG_STM32_SDIO_DMA -static void stm32_dmacallback(DMA_HANDLE handle, uint8_t status, void *arg); -#endif - -/* Data Transfer Helpers ****************************************************/ - -static uint8_t stm32_log2(uint16_t value); -static void stm32_dataconfig(uint32_t timeout, uint32_t dlen, - uint32_t dctrl); -static void stm32_datadisable(void); -static void stm32_sendfifo(struct stm32_dev_s *priv); -static void stm32_recvfifo(struct stm32_dev_s *priv); -static void stm32_eventtimeout(wdparm_t arg); -static void stm32_endwait(struct stm32_dev_s *priv, - sdio_eventset_t wkupevent); -static void stm32_endtransfer(struct stm32_dev_s *priv, - sdio_eventset_t wkupevent); - -/* Interrupt Handling *******************************************************/ - -static int stm32_interrupt(int irq, void *context, void *arg); -#ifdef CONFIG_MMCSD_SDIOWAIT_WRCOMPLETE -static int stm32_rdyinterrupt(int irq, void *context, void *arg); -#endif - -/* SDIO interface methods ***************************************************/ - -/* Mutual exclusion */ - -#ifdef CONFIG_SDIO_MUXBUS -static int stm32_lock(struct sdio_dev_s *dev, bool lock); -#endif - -/* Initialization/setup */ - -static void stm32_reset(struct sdio_dev_s *dev); -static sdio_capset_t stm32_capabilities(struct sdio_dev_s *dev); -static sdio_statset_t stm32_status(struct sdio_dev_s *dev); -static void stm32_widebus(struct sdio_dev_s *dev, bool enable); -static void stm32_clock(struct sdio_dev_s *dev, - enum sdio_clock_e rate); -static int stm32_attach(struct sdio_dev_s *dev); - -/* Command/Status/Data Transfer */ - -static int stm32_sendcmd(struct sdio_dev_s *dev, uint32_t cmd, - uint32_t arg); -#ifdef CONFIG_SDIO_BLOCKSETUP -static void stm32_blocksetup(struct sdio_dev_s *dev, - unsigned int blocklen, unsigned int nblocks); -#endif -static int stm32_recvsetup(struct sdio_dev_s *dev, uint8_t *buffer, - size_t nbytes); -static int stm32_sendsetup(struct sdio_dev_s *dev, - const uint8_t *buffer, size_t nbytes); -static int stm32_cancel(struct sdio_dev_s *dev); - -static int stm32_waitresponse(struct sdio_dev_s *dev, uint32_t cmd); -static int stm32_recvshortcrc(struct sdio_dev_s *dev, uint32_t cmd, - uint32_t *rshort); -static int stm32_recvlong(struct sdio_dev_s *dev, uint32_t cmd, - uint32_t rlong[4]); -static int stm32_recvshort(struct sdio_dev_s *dev, uint32_t cmd, - uint32_t *rshort); - -/* EVENT handler */ - -static void stm32_waitenable(struct sdio_dev_s *dev, - sdio_eventset_t eventset, uint32_t timeout); -static sdio_eventset_t stm32_eventwait(struct sdio_dev_s *dev); -static void stm32_callbackenable(struct sdio_dev_s *dev, - sdio_eventset_t eventset); -static int stm32_registercallback(struct sdio_dev_s *dev, - worker_t callback, void *arg); - -/* DMA */ - -#ifdef CONFIG_STM32_SDIO_DMA -#ifdef CONFIG_ARCH_HAVE_SDIO_PREFLIGHT -static int stm32_dmapreflight(struct sdio_dev_s *dev, - const uint8_t *buffer, size_t buflen); -#endif -static int stm32_dmarecvsetup(struct sdio_dev_s *dev, - uint8_t *buffer, size_t buflen); -static int stm32_dmasendsetup(struct sdio_dev_s *dev, - const uint8_t *buffer, size_t buflen); -#endif - -/* Initialization/uninitialization/reset ************************************/ - -static void stm32_callback(void *arg); -static void stm32_default(void); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -struct stm32_dev_s g_sdiodev = -{ - .dev = - { -#ifdef CONFIG_SDIO_MUXBUS - .lock = stm32_lock, -#endif - .reset = stm32_reset, - .capabilities = stm32_capabilities, - .status = stm32_status, - .widebus = stm32_widebus, - .clock = stm32_clock, - .attach = stm32_attach, - .sendcmd = stm32_sendcmd, -#ifdef CONFIG_SDIO_BLOCKSETUP - .blocksetup = stm32_blocksetup, -#endif - .recvsetup = stm32_recvsetup, - .sendsetup = stm32_sendsetup, - .cancel = stm32_cancel, - .waitresponse = stm32_waitresponse, - .recv_r1 = stm32_recvshortcrc, - .recv_r2 = stm32_recvlong, - .recv_r3 = stm32_recvshort, - .recv_r4 = stm32_recvshort, - .recv_r5 = stm32_recvshortcrc, - .recv_r6 = stm32_recvshortcrc, - .recv_r7 = stm32_recvshort, - .waitenable = stm32_waitenable, - .eventwait = stm32_eventwait, - .callbackenable = stm32_callbackenable, - .registercallback = stm32_registercallback, -#ifdef CONFIG_SDIO_DMA -#ifdef CONFIG_STM32_SDIO_DMA -#ifdef CONFIG_ARCH_HAVE_SDIO_PREFLIGHT - .dmapreflight = stm32_dmapreflight, -#endif - .dmarecvsetup = stm32_dmarecvsetup, - .dmasendsetup = stm32_dmasendsetup, -#else -#ifdef CONFIG_ARCH_HAVE_SDIO_PREFLIGHT - .dmapreflight = NULL, -#endif - .dmarecvsetup = stm32_recvsetup, - .dmasendsetup = stm32_sendsetup, -#endif -#endif - }, - .waitsem = SEM_INITIALIZER(0), -}; - -/* Register logging support */ - -#ifdef CONFIG_SDIO_XFRDEBUG -static struct stm32_sampleregs_s g_sampleregs[DEBUG_NSAMPLES]; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_setclkcr - * - * Description: - * Modify oft-changed bits in the CLKCR register. Only the following bit- - * fields are changed: - * - * CLKDIV, PWRSAV, BYPASS, WIDBUS, NEGEDGE, and HWFC_EN - * - * Input Parameters: - * clkcr - A new CLKCR setting for the above mentions bits (other bits - * are ignored. - * - * Returned Value: - * None - * - ****************************************************************************/ - -static inline void stm32_setclkcr(uint32_t clkcr) -{ - uint32_t regval = getreg32(STM32_SDIO_CLKCR); - - /* Clear CLKDIV, PWRSAV, BYPASS, WIDBUS, NEGEDGE, HWFC_EN bits */ - - regval &= ~(SDIO_CLKCR_CLKDIV_MASK | SDIO_CLKCR_PWRSAV | - SDIO_CLKCR_BYPASS | SDIO_CLKCR_WIDBUS_MASK | - SDIO_CLKCR_NEGEDGE | SDIO_CLKCR_HWFC_EN | - SDIO_CLKCR_CLKEN); - - /* Replace with user provided settings */ - - clkcr &= (SDIO_CLKCR_CLKDIV_MASK | SDIO_CLKCR_PWRSAV | - SDIO_CLKCR_BYPASS | SDIO_CLKCR_WIDBUS_MASK | - SDIO_CLKCR_NEGEDGE | SDIO_CLKCR_HWFC_EN | - SDIO_CLKCR_CLKEN); - - regval |= clkcr; - putreg32(regval, STM32_SDIO_CLKCR); - - mcinfo("CLKCR: %08" PRIx32 " PWR: %08" PRIx32 "\n", - getreg32(STM32_SDIO_CLKCR), getreg32(STM32_SDIO_POWER)); -} - -/**************************************************************************** - * Name: stm32_configwaitints - * - * Description: - * Enable/disable SDIO interrupts needed to support the wait function - * - * Input Parameters: - * priv - A reference to the SDIO device state structure - * waitmask - The set of bits in the SDIO MASK register to set - * waitevents - Waited for events - * wkupevent - Wake-up events - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void stm32_configwaitints(struct stm32_dev_s *priv, uint32_t waitmask, - sdio_eventset_t waitevents, - sdio_eventset_t wkupevent) -{ - irqstate_t flags; -#ifdef CONFIG_MMCSD_SDIOWAIT_WRCOMPLETE - int pinset; -#endif - - /* Save all of the data and set the new interrupt mask in one, atomic - * operation. - */ - - flags = enter_critical_section(); - -#ifdef CONFIG_MMCSD_SDIOWAIT_WRCOMPLETE - if ((waitevents & SDIOWAIT_WRCOMPLETE) != 0) - { - pinset = GPIO_SDIO_D0 & (GPIO_PORT_MASK | GPIO_PIN_MASK); - pinset |= (GPIO_INPUT | GPIO_FLOAT | GPIO_EXTI); - - /* Arm the SDIO_D0 Ready and install Isr */ - - stm32_gpiosetevent(pinset, true, false, false, - stm32_rdyinterrupt, priv); - } - - /* Disarm SDIO_D0 ready and return it to SDIO D0 */ - - if ((wkupevent & SDIOWAIT_WRCOMPLETE) != 0) - { - stm32_gpiosetevent(GPIO_SDIO_D0, false, false, false, - NULL, NULL); - } -#endif - - priv->waitevents = waitevents; - priv->wkupevent = wkupevent; - priv->waitmask = waitmask; -#ifdef CONFIG_STM32_SDIO_DMA - priv->xfrflags = 0; -#endif - -#ifdef CONFIG_STM32_SDIO_CARD - putreg32(priv->xfrmask | priv->waitmask | priv->sdiointmask, - STM32_SDIO_MASK); -#else - putreg32(priv->xfrmask | priv->waitmask, STM32_SDIO_MASK); -#endif - - leave_critical_section(flags); -} - -/**************************************************************************** - * Name: stm32_configxfrints - * - * Description: - * Enable SDIO interrupts needed to support the data transfer event - * - * Input Parameters: - * priv - A reference to the SDIO device state structure - * xfrmask - The set of bits in the SDIO MASK register to set - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void stm32_configxfrints(struct stm32_dev_s *priv, uint32_t xfrmask) -{ - irqstate_t flags; - - flags = enter_critical_section(); - priv->xfrmask = xfrmask; -#ifdef CONFIG_STM32_SDIO_CARD - putreg32(priv->xfrmask | priv->waitmask | priv->sdiointmask, - STM32_SDIO_MASK); -#else - putreg32(priv->xfrmask | priv->waitmask, STM32_SDIO_MASK); -#endif - leave_critical_section(flags); -} - -/**************************************************************************** - * Name: stm32_setpwrctrl - * - * Description: - * Change the PWRCTRL field of the SDIO POWER register to turn the SDIO - * ON or OFF - * - * Input Parameters: - * clkcr - A new PWRCTRL setting - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void stm32_setpwrctrl(uint32_t pwrctrl) -{ - uint32_t regval; - - regval = getreg32(STM32_SDIO_POWER); - regval &= ~SDIO_POWER_PWRCTRL_MASK; - regval |= pwrctrl; - putreg32(regval, STM32_SDIO_POWER); -} - -/**************************************************************************** - * Name: stm32_sampleinit - * - * Description: - * Setup prior to collecting DMA samples - * - ****************************************************************************/ - -#ifdef CONFIG_SDIO_XFRDEBUG -static void stm32_sampleinit(void) -{ - memset(g_sampleregs, 0xff, - DEBUG_NSAMPLES * sizeof(struct stm32_sampleregs_s)); -} -#endif - -/**************************************************************************** - * Name: stm32_sdiosample - * - * Description: - * Sample SDIO registers - * - ****************************************************************************/ - -#ifdef CONFIG_SDIO_XFRDEBUG -static void stm32_sdiosample(struct stm32_sdioregs_s *regs) -{ - regs->power = (uint8_t)getreg32(STM32_SDIO_POWER); - regs->clkcr = (uint16_t)getreg32(STM32_SDIO_CLKCR); - regs->dctrl = (uint16_t)getreg32(STM32_SDIO_DCTRL); - regs->dtimer = getreg32(STM32_SDIO_DTIMER); - regs->dlen = getreg32(STM32_SDIO_DLEN); - regs->dcount = getreg32(STM32_SDIO_DCOUNT); - regs->sta = getreg32(STM32_SDIO_STA); - regs->mask = getreg32(STM32_SDIO_MASK); - regs->fifocnt = getreg32(STM32_SDIO_FIFOCNT); -} -#endif - -/**************************************************************************** - * Name: stm32_sample - * - * Description: - * Sample SDIO/DMA registers - * - ****************************************************************************/ - -#ifdef CONFIG_SDIO_XFRDEBUG -static void stm32_sample(struct stm32_dev_s *priv, int index) -{ - struct stm32_sampleregs_s *regs = &g_sampleregs[index]; - -#if defined(CONFIG_DEBUG_DMA_INFO) && defined(CONFIG_STM32_SDIO_DMA) - if (priv->dmamode) - { - stm32_dmasample(priv->dma, ®s->dma); - } -#endif - - stm32_sdiosample(®s->sdio); -} -#endif - -/**************************************************************************** - * Name: stm32_sdiodump - * - * Description: - * Dump one register sample - * - ****************************************************************************/ - -#ifdef CONFIG_SDIO_XFRDEBUG -static void stm32_sdiodump(struct stm32_sdioregs_s *regs, const char *msg) -{ - mcinfo("SDIO Registers: %s\n", msg); - mcinfo(" POWER[%08x]: %08x\n", STM32_SDIO_POWER, regs->power); - mcinfo(" CLKCR[%08x]: %08x\n", STM32_SDIO_CLKCR, regs->clkcr); - mcinfo(" DCTRL[%08x]: %08x\n", STM32_SDIO_DCTRL, regs->dctrl); - mcinfo(" DTIMER[%08x]: %08" PRIx32 "\n", - STM32_SDIO_DTIMER, regs->dtimer); - mcinfo(" DLEN[%08x]: %08" PRIx32 "\n", - STM32_SDIO_DLEN, regs->dlen); - mcinfo(" DCOUNT[%08x]: %08" PRIx32 "\n", - STM32_SDIO_DCOUNT, regs->dcount); - mcinfo(" STA[%08x]: %08" PRIx32 "\n", - STM32_SDIO_STA, regs->sta); - mcinfo(" MASK[%08x]: %08" PRIx32 "\n", - STM32_SDIO_MASK, regs->mask); - mcinfo("FIFOCNT[%08x]: %08" PRIx32 "\n", - STM32_SDIO_FIFOCNT, regs->fifocnt); -} -#endif - -/**************************************************************************** - * Name: stm32_dumpsample - * - * Description: - * Dump one register sample - * - ****************************************************************************/ - -#ifdef CONFIG_SDIO_XFRDEBUG -static void stm32_dumpsample(struct stm32_dev_s *priv, - struct stm32_sampleregs_s *regs, - const char *msg) -{ -#if defined(CONFIG_DEBUG_DMA_INFO) && defined(CONFIG_STM32_SDIO_DMA) - if (priv->dmamode) - { - stm32_dmadump(priv->dma, ®s->dma, msg); - } -#endif - - stm32_sdiodump(®s->sdio, msg); -} -#endif - -/**************************************************************************** - * Name: stm32_dumpsamples - * - * Description: - * Dump all sampled register data - * - ****************************************************************************/ - -#ifdef CONFIG_SDIO_XFRDEBUG -static void stm32_dumpsamples(struct stm32_dev_s *priv) -{ - stm32_dumpsample(priv, &g_sampleregs[SAMPLENDX_BEFORE_SETUP], - "Before setup"); - -#if defined(CONFIG_DEBUG_DMA_INFO) && defined(CONFIG_STM32_SDIO_DMA) - if (priv->dmamode) - { - stm32_dumpsample(priv, &g_sampleregs[SAMPLENDX_BEFORE_ENABLE], - "Before DMA enable"); - } -#endif - - stm32_dumpsample(priv, &g_sampleregs[SAMPLENDX_AFTER_SETUP], - "After setup"); - stm32_dumpsample(priv, &g_sampleregs[SAMPLENDX_END_TRANSFER], - "End of transfer"); - -#if defined(CONFIG_DEBUG_DMA_INFO) && defined(CONFIG_STM32_SDIO_DMA) - if (priv->dmamode) - { - stm32_dumpsample(priv, &g_sampleregs[SAMPLENDX_DMA_CALLBACK], - "DMA Callback"); - } -#endif -} -#endif - -/**************************************************************************** - * Name: stm32_dmacallback - * - * Description: - * Called when SDIO DMA completes - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_SDIO_DMA -static void stm32_dmacallback(DMA_HANDLE handle, uint8_t status, void *arg) -{ - struct stm32_dev_s *priv = (struct stm32_dev_s *)arg; - DEBUGASSERT(priv->dmamode); - sdio_eventset_t result; - - /* In the normal case, SDIO appears to handle the End-Of-Transfer interrupt - * first with the End-Of-DMA event occurring significantly later. On - * transfer errors, however, the DMA error will occur before the End-of- - * Transfer. - */ - - stm32_sample((struct stm32_dev_s *)arg, SAMPLENDX_DMA_CALLBACK); - - /* Get the result of the DMA transfer */ - - if ((status & DMA_STATUS_ERROR) != 0) - { - mcerr("ERROR: DMA error %02x, remaining: %d\n", - status, priv->remaining); - result = SDIOWAIT_ERROR; - } - else - { - result = SDIOWAIT_TRANSFERDONE; - } - - /* Then terminate the transfer if this completes all of the steps in the - * transfer OR if a DMA error occurred. In the non-error case, we should - * already have the SDIO transfer done interrupt. If not, the transfer - * will appropriately time out. - */ - - priv->xfrflags |= SDIO_DMADONE_FLAG; - if (priv->xfrflags == SDIO_ALLDONE || result == SDIOWAIT_ERROR) - { - stm32_endtransfer(priv, result); - } -} -#endif - -/**************************************************************************** - * Name: stm32_log2 - * - * Description: - * Take (approximate) log base 2 of the provided number (Only works if the - * provided number is a power of 2). - * - ****************************************************************************/ - -static uint8_t stm32_log2(uint16_t value) -{ - uint8_t log2 = 0; - - /* 0000 0000 0000 0001 -> return 0, - * 0000 0000 0000 001x -> return 1, - * 0000 0000 0000 01xx -> return 2, - * 0000 0000 0000 1xxx -> return 3, - * ... - * 1xxx xxxx xxxx xxxx -> return 15, - */ - - DEBUGASSERT(value > 0); - while (value != 1) - { - value >>= 1; - log2++; - } - - return log2; -} - -/**************************************************************************** - * Name: stm32_dataconfig - * - * Description: - * Configure the SDIO data path for the next data transfer - * - ****************************************************************************/ - -static void stm32_dataconfig(uint32_t timeout, uint32_t dlen, uint32_t dctrl) -{ - uint32_t clkdiv; - uint32_t regval; - uint32_t sdio_clk = IP_CLCK_FREQ; - - /* Enable data path using a timeout scaled to the SD_CLOCK (the card - * clock). - */ - - regval = getreg32(STM32_SDIO_CLKCR); - clkdiv = (regval & SDIO_CLKCR_CLKDIV_MASK) >> SDIO_CLKCR_CLKDIV_SHIFT; - if ((regval & SDIO_CLKCR_BYPASS) == 0) - { - sdio_clk = sdio_clk / (2 + clkdiv); - } - - /* Convert Timeout in Ms to SD_CLK counts */ - - timeout = timeout * (sdio_clk / 1000); - - putreg32(timeout, STM32_SDIO_DTIMER); /* Set DTIMER */ - putreg32(dlen, STM32_SDIO_DLEN); /* Set DLEN */ - - /* Configure DCTRL DTDIR, DTMODE, and DBLOCKSIZE fields and set the DTEN - * field - */ - - regval = getreg32(STM32_SDIO_DCTRL); - regval &= ~(SDIO_DCTRL_DTDIR | SDIO_DCTRL_DTMODE | - SDIO_DCTRL_DBLOCKSIZE_MASK); - dctrl &= (SDIO_DCTRL_DTDIR | SDIO_DCTRL_DTMODE | - SDIO_DCTRL_DBLOCKSIZE_MASK); - regval |= (dctrl | SDIO_DCTRL_DTEN | SDIO_DCTRL_SDIOEN); - putreg32(regval, STM32_SDIO_DCTRL); -} - -/**************************************************************************** - * Name: stm32_datadisable - * - * Description: - * Disable the SDIO data path setup by stm32_dataconfig() and - * disable DMA. - * - ****************************************************************************/ - -static void stm32_datadisable(void) -{ - uint32_t regval; - - /* Disable the data path */ - - /* Reset DTIMER */ - - putreg32(UINT32_MAX, STM32_SDIO_DTIMER); - - /* Reset DLEN */ - - putreg32(0, STM32_SDIO_DLEN); - - /* Reset DCTRL DTEN, DTDIR, DTMODE, DMAEN, and DBLOCKSIZE fields */ - - regval = getreg32(STM32_SDIO_DCTRL); - regval &= ~(SDIO_DCTRL_DTEN | SDIO_DCTRL_DTDIR | SDIO_DCTRL_DTMODE | - SDIO_DCTRL_DMAEN | SDIO_DCTRL_DBLOCKSIZE_MASK); - putreg32(regval, STM32_SDIO_DCTRL); -} - -/**************************************************************************** - * Name: stm32_sendfifo - * - * Description: - * Send SDIO data in interrupt mode - * - * Input Parameters: - * priv - An instance of the SDIO device interface - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void stm32_sendfifo(struct stm32_dev_s *priv) -{ - union - { - uint32_t w; - uint8_t b[4]; - } data; - - /* Loop while there is more data to be sent and the RX FIFO is not full */ - - while (priv->remaining > 0 && - (getreg32(STM32_SDIO_STA) & SDIO_STA_TXFIFOF) == 0) - { - /* Is there a full word remaining in the user buffer? */ - - if (priv->remaining >= sizeof(uint32_t)) - { - /* Yes, transfer the word to the TX FIFO */ - - data.w = *priv->buffer++; - priv->remaining -= sizeof(uint32_t); - } - else - { - /* No.. transfer just the bytes remaining in the user buffer, - * padding with zero as necessary to extend to a full word. - */ - - uint8_t *ptr = (uint8_t *)priv->remaining; - int i; - - data.w = 0; - for (i = 0; i < (int)priv->remaining; i++) - { - data.b[i] = *ptr++; - } - - /* Now the transfer is finished */ - - priv->remaining = 0; - } - - /* Put the word in the FIFO */ - - putreg32(data.w, STM32_SDIO_FIFO); - } -} - -/**************************************************************************** - * Name: stm32_recvfifo - * - * Description: - * Receive SDIO data in interrupt mode - * - * Input Parameters: - * priv - An instance of the SDIO device interface - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void stm32_recvfifo(struct stm32_dev_s *priv) -{ - union - { - uint32_t w; - uint8_t b[4]; - } data; - - /* Loop while there is space to store the data and there is more - * data available in the RX FIFO. - */ - - while (priv->remaining > 0 && - (getreg32(STM32_SDIO_STA) & SDIO_STA_RXDAVL) != 0) - { - /* Read the next word from the RX FIFO */ - - data.w = getreg32(STM32_SDIO_FIFO); - if (priv->remaining >= sizeof(uint32_t)) - { - /* Transfer the whole word to the user buffer */ - - *priv->buffer++ = data.w; - priv->remaining -= sizeof(uint32_t); - } - else - { - /* Transfer any trailing fractional word */ - - uint8_t *ptr = (uint8_t *)priv->buffer; - int i; - - for (i = 0; i < (int)priv->remaining; i++) - { - *ptr++ = data.b[i]; - } - - /* Now the transfer is finished */ - - priv->remaining = 0; - } - } -} - -/**************************************************************************** - * Name: stm32_eventtimeout - * - * Description: - * The watchdog timeout setup when the event wait start has expired without - * any other waited-for event occurring. - * - * Input Parameters: - * arg - The argument - * - * Returned Value: - * None - * - * Assumptions: - * Always called from the interrupt level with interrupts disabled. - * - ****************************************************************************/ - -static void stm32_eventtimeout(wdparm_t arg) -{ - struct stm32_dev_s *priv = (struct stm32_dev_s *)arg; - - /* There is always race conditions with timer expirations. */ - - DEBUGASSERT((priv->waitevents & SDIOWAIT_TIMEOUT) != 0 || - priv->wkupevent != 0); - - mcinfo("sta: %08" PRIx32 " enabled irq: %08" PRIx32 "\n", - getreg32(STM32_SDIO_STA), - getreg32(STM32_SDIO_MASK)); - - /* Is a data transfer complete event expected? */ - - if ((priv->waitevents & SDIOWAIT_TIMEOUT) != 0) - { - /* Yes.. wake up any waiting threads */ - -#ifdef CONFIG_MMCSD_SDIOWAIT_WRCOMPLETE - stm32_endwait(priv, SDIOWAIT_TIMEOUT | - (priv->waitevents & SDIOWAIT_WRCOMPLETE)); -#else - stm32_endwait(priv, SDIOWAIT_TIMEOUT); -#endif - mcerr("Timeout: remaining: %d\n", priv->remaining); - } -} - -/**************************************************************************** - * Name: stm32_endwait - * - * Description: - * Wake up a waiting thread if the waited-for event has occurred. - * - * Input Parameters: - * priv - An instance of the SDIO device interface - * wkupevent - The event that caused the wait to end - * - * Returned Value: - * None - * - * Assumptions: - * Always called from the interrupt level with interrupts disabled. - * - ****************************************************************************/ - -static void stm32_endwait(struct stm32_dev_s *priv, - sdio_eventset_t wkupevent) -{ - /* Cancel the watchdog timeout */ - - wd_cancel(&priv->waitwdog); - - /* Disable event-related interrupts */ - - stm32_configwaitints(priv, 0, 0, wkupevent); - - /* Wake up the waiting thread */ - - nxsem_post(&priv->waitsem); -} - -/**************************************************************************** - * Name: stm32_endtransfer - * - * Description: - * Terminate a transfer with the provided status. This function is called - * only from the SDIO interrupt handler when end-of-transfer conditions - * are detected. - * - * Input Parameters: - * priv - An instance of the SDIO device interface - * wkupevent - The event that caused the transfer to end - * - * Returned Value: - * None - * - * Assumptions: - * Always called from the interrupt level with interrupts disabled. - * - ****************************************************************************/ - -static void stm32_endtransfer(struct stm32_dev_s *priv, - sdio_eventset_t wkupevent) -{ - /* Disable all transfer related interrupts */ - - stm32_configxfrints(priv, 0); - - /* Clearing pending interrupt status on all transfer related interrupts */ - - putreg32(SDIO_XFRDONE_ICR, STM32_SDIO_ICR); - - /* If this was a DMA transfer, make sure that DMA is stopped */ - -#ifdef CONFIG_STM32_SDIO_DMA - if (priv->dmamode) - { - /* DMA debug instrumentation */ - - stm32_sample(priv, SAMPLENDX_END_TRANSFER); - - /* Make sure that the DMA is stopped (it will be stopped automatically - * on normal transfers, but not necessarily when the transfer - * terminates on an error condition). - */ - - stm32_dmastop(priv->dma); - } -#endif - - /* Mark the transfer finished */ - - priv->remaining = 0; - - /* Is a thread wait for these data transfer complete events? */ - - if ((priv->waitevents & wkupevent) != 0) - { - /* Yes.. wake up any waiting threads */ - - stm32_endwait(priv, wkupevent); - } -} - -/**************************************************************************** - * Name: stm32_rdyinterrupt - * - * Description: - * SDIO ready interrupt handler - * - * Input Parameters: - * dev - An instance of the SDIO device interface - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef CONFIG_MMCSD_SDIOWAIT_WRCOMPLETE -static int stm32_rdyinterrupt(int irq, void *context, void *arg) -{ - struct stm32_dev_s *priv = (struct stm32_dev_s *)arg; - - /* Avoid noise, check the state */ - - if (stm32_gpioread(GPIO_SDIO_D0)) - { - stm32_endwait(priv, SDIOWAIT_WRCOMPLETE); - } - - return OK; -} -#endif - -/**************************************************************************** - * Name: stm32_interrupt - * - * Description: - * SDIO interrupt handler - * - * Input Parameters: - * dev - An instance of the SDIO device interface - * - * Returned Value: - * None - * - ****************************************************************************/ - -static int stm32_interrupt(int irq, void *context, void *arg) -{ - struct stm32_dev_s *priv = &g_sdiodev; - uint32_t enabled; - uint32_t pending; - - /* Loop while there are pending interrupts. Check the SDIO status - * register. Mask out all bits that don't correspond to enabled - * interrupts. (This depends on the fact that bits are ordered - * the same in both the STA and MASK register). If there are non-zero - * bits remaining, then we have work to do here. - */ - - while ((enabled = getreg32(STM32_SDIO_STA) & - getreg32(STM32_SDIO_MASK)) != 0) - { - /* Handle in progress, interrupt driven data transfers ****************/ - - pending = enabled & priv->xfrmask; - if (pending != 0) - { -#ifdef CONFIG_STM32_SDIO_DMA - if (!priv->dmamode) -#endif - { - /* Is the RX FIFO half full or more? Is so then we must be - * processing a receive transaction. - */ - - if ((pending & SDIO_STA_RXFIFOHF) != 0) - { - /* Receive data from the RX FIFO */ - - stm32_recvfifo(priv); - } - - /* Otherwise, Is the transmit FIFO half empty or less? If so - * we must be processing a send transaction. NOTE: We can't - * be processing both! - */ - - else if ((pending & SDIO_STA_TXFIFOHE) != 0) - { - /* Send data via the TX FIFO */ - - stm32_sendfifo(priv); - } - } - - /* Handle data end events */ - - if ((pending & SDIO_STA_DATAEND) != 0) - { - /* Handle any data remaining the RX FIFO. If the RX FIFO is - * less than half full at the end of the transfer, then no - * half-full interrupt will be received. - */ - - /* Was this transfer performed in DMA mode? */ - -#ifdef CONFIG_STM32_SDIO_DMA - if (priv->dmamode) - { - /* Yes.. Terminate the transfers only if the DMA has also - * finished. - */ - - priv->xfrflags |= SDIO_XFRDONE_FLAG; - if (priv->xfrflags == SDIO_ALLDONE) - { - stm32_endtransfer(priv, SDIOWAIT_TRANSFERDONE); - } - - /* Otherwise, just disable further transfer interrupts and - * wait for the DMA complete event. - */ - - else - { - stm32_configxfrints(priv, 0); - } - } - else -#endif - { - /* Receive data from the RX FIFO */ - - stm32_recvfifo(priv); - - /* Then terminate the transfer */ - - stm32_endtransfer(priv, SDIOWAIT_TRANSFERDONE); - } - } - - /* Handle data block send/receive CRC failure */ - - else if ((pending & SDIO_STA_DCRCFAIL) != 0) - { - /* Terminate the transfer with an error */ - - mcerr("ERROR: Data block CRC failure, remaining: %d\n", - priv->remaining); - stm32_endtransfer(priv, - SDIOWAIT_TRANSFERDONE | SDIOWAIT_ERROR); - } - - /* Handle data timeout error */ - - else if ((pending & SDIO_STA_DTIMEOUT) != 0) - { - /* Terminate the transfer with an error */ - - mcerr("ERROR: Data timeout, remaining: %d\n", - priv->remaining); - stm32_endtransfer(priv, - SDIOWAIT_TRANSFERDONE | SDIOWAIT_TIMEOUT); - } - - /* Handle RX FIFO overrun error */ - - else if ((pending & SDIO_STA_RXOVERR) != 0) - { - /* Terminate the transfer with an error */ - - mcerr("ERROR: RX FIFO overrun, remaining: %d\n", - priv->remaining); - stm32_endtransfer(priv, - SDIOWAIT_TRANSFERDONE | SDIOWAIT_ERROR); - } - - /* Handle TX FIFO underrun error */ - - else if ((pending & SDIO_STA_TXUNDERR) != 0) - { - /* Terminate the transfer with an error */ - - mcerr("ERROR: TX FIFO underrun, remaining: %d\n", - priv->remaining); - stm32_endtransfer(priv, - SDIOWAIT_TRANSFERDONE | SDIOWAIT_ERROR); - } - - /* Handle start bit error */ - - else if ((pending & SDIO_STA_STBITERR) != 0) - { - /* Terminate the transfer with an error */ - - mcerr("ERROR: Start bit, remaining: %d\n", - priv->remaining); - stm32_endtransfer(priv, - SDIOWAIT_TRANSFERDONE | SDIOWAIT_ERROR); - } - } - - /* Handle wait events *************************************************/ - - pending = enabled & priv->waitmask; - if (pending != 0) - { - /* Is this a response completion event? */ - - if ((pending & SDIO_RESPDONE_STA) != 0) - { - /* Yes.. Is their a thread waiting for response done? */ - - if ((priv->waitevents & SDIOWAIT_RESPONSEDONE) != 0) - { - /* Yes.. wake the thread up */ - - putreg32(SDIO_RESPDONE_ICR | SDIO_CMDDONE_ICR, - STM32_SDIO_ICR); - stm32_endwait(priv, SDIOWAIT_RESPONSEDONE); - } - } - - /* Is this a command completion event? */ - - if ((pending & SDIO_CMDDONE_STA) != 0) - { - /* Yes.. Is their a thread waiting for command done? */ - - if ((priv->waitevents & SDIOWAIT_RESPONSEDONE) != 0) - { - /* Yes.. wake the thread up */ - - putreg32(SDIO_CMDDONE_ICR, STM32_SDIO_ICR); - stm32_endwait(priv, SDIOWAIT_CMDDONE); - } - } - } - -#ifdef CONFIG_STM32_SDIO_CARD - /* Handle SDIO card interrupt */ - - pending = enabled & priv->sdiointmask; - if (pending != 0) - { - putreg32(SDIO_STA_SDIOIT, STM32_SDIO_ICR); - - /* Perform callback */ - - if (priv->do_sdio_card) - { - priv->do_sdio_card(priv->do_sdio_arg); - } - } -#endif - } - - return OK; -} - -/**************************************************************************** - * Name: stm32_lock - * - * Description: - * Locks the bus. Function calls low-level multiplexed bus routines to - * resolve bus requests and acknowledgment issues. - * - * Input Parameters: - * dev - An instance of the SDIO device interface - * lock - TRUE to lock, FALSE to unlock. - * - * Returned Value: - * OK on success; a negated errno on failure - * - ****************************************************************************/ - -#ifdef CONFIG_SDIO_MUXBUS -static int stm32_lock(struct sdio_dev_s *dev, bool lock) -{ - /* Single SDIO instance so there is only one possibility. The multiplex - * bus is part of board support package. - */ - - /* FIXME: Implement the below function to support bus share: - * - * stm32_muxbus_sdio_lock(lock); - */ - - return OK; -} -#endif - -/**************************************************************************** - * Name: stm32_reset - * - * Description: - * Reset the SDIO controller. Undo all setup and initialization. - * - * Input Parameters: - * dev - An instance of the SDIO device interface - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void stm32_reset(struct sdio_dev_s *dev) -{ - struct stm32_dev_s *priv = (struct stm32_dev_s *)dev; - irqstate_t flags; - - /* Disable clocking */ - - flags = enter_critical_section(); - putreg32(0, SDIO_CLKCR_CLKEN_BB); - stm32_setpwrctrl(SDIO_POWER_PWRCTRL_OFF); - - /* Put SDIO registers in their default, reset state */ - - stm32_default(); - - /* Reset data */ - - priv->waitevents = 0; /* Set of events to be waited for */ - priv->waitmask = 0; /* Interrupt enables for event waiting */ - priv->wkupevent = 0; /* The event that caused the wakeup */ -#ifdef CONFIG_STM32_SDIO_DMA - priv->xfrflags = 0; /* Used to synchronize SDIO and DMA completion events */ -#endif - - wd_cancel(&priv->waitwdog); /* Cancel any timeouts */ - - /* Interrupt mode data transfer support */ - - priv->buffer = 0; /* Address of current R/W buffer */ - priv->remaining = 0; /* Number of bytes remaining in the transfer */ - priv->xfrmask = 0; /* Interrupt enables for data transfer */ - -#ifdef CONFIG_STM32_SDIO_CARD - priv->sdiointmask = 0; /* SDIO card in-band interrupt mask */ -#endif - - /* DMA data transfer support */ - - priv->widebus = false; /* Required for DMA support */ -#ifdef CONFIG_STM32_SDIO_DMA - priv->dmamode = false; /* true: DMA mode transfer */ -#endif - - /* Configure the SDIO peripheral */ - - stm32_setclkcr(STM32_CLCKCR_INIT | SDIO_CLKCR_CLKEN); - stm32_setpwrctrl(SDIO_POWER_PWRCTRL_ON); - leave_critical_section(flags); - - mcinfo("CLCKR: %08" PRIx32 " POWER: %08" PRIx32 "\n", - getreg32(STM32_SDIO_CLKCR), getreg32(STM32_SDIO_POWER)); -} - -/**************************************************************************** - * Name: stm32_capabilities - * - * Description: - * Get capabilities (and limitations) of the SDIO driver (optional) - * - * Input Parameters: - * dev - Device-specific state data - * - * Returned Value: - * Returns a bitset of status values (see SDIO_CAPS_* defines) - * - ****************************************************************************/ - -static sdio_capset_t stm32_capabilities(struct sdio_dev_s *dev) -{ - sdio_capset_t caps = 0; - -#ifdef CONFIG_STM32_SDIO_WIDTH_D1_ONLY - caps |= SDIO_CAPS_1BIT_ONLY; -#endif -#ifdef CONFIG_STM32_SDIO_DMA - caps |= SDIO_CAPS_DMASUPPORTED; -#endif - - return caps; -} - -/**************************************************************************** - * Name: stm32_status - * - * Description: - * Get SDIO status. - * - * Input Parameters: - * dev - Device-specific state data - * - * Returned Value: - * Returns a bitset of status values (see stm32_status_* defines) - * - ****************************************************************************/ - -static sdio_statset_t stm32_status(struct sdio_dev_s *dev) -{ - struct stm32_dev_s *priv = (struct stm32_dev_s *)dev; - return priv->cdstatus; -} - -/**************************************************************************** - * Name: stm32_widebus - * - * Description: - * Called after change in Bus width has been selected (via ACMD6). Most - * controllers will need to perform some special operations to work - * correctly in the new bus mode. - * - * Input Parameters: - * dev - An instance of the SDIO device interface - * wide - true: wide bus (4-bit) bus mode enabled - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void stm32_widebus(struct sdio_dev_s *dev, bool wide) -{ - struct stm32_dev_s *priv = (struct stm32_dev_s *)dev; - priv->widebus = wide; -} - -/**************************************************************************** - * Name: stm32_clock - * - * Description: - * Enable/disable SDIO clocking - * - * Input Parameters: - * dev - An instance of the SDIO device interface - * rate - Specifies the clocking to use (see enum sdio_clock_e) - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void stm32_clock(struct sdio_dev_s *dev, enum sdio_clock_e rate) -{ - uint32_t clckr; - - switch (rate) - { - /* Disable clocking (with default ID mode divisor) */ - - default: - case CLOCK_SDIO_DISABLED: - clckr = STM32_CLCKCR_INIT; - break; - - /* Enable in initial ID mode clocking (<400KHz) */ - - case CLOCK_IDMODE: - clckr = (STM32_CLCKCR_INIT | SDIO_CLKCR_CLKEN); - break; - - /* Enable in MMC normal operation clocking */ - - case CLOCK_MMC_TRANSFER: - clckr = (SDIO_CLKCR_MMCXFR | SDIO_CLKCR_CLKEN); - break; - - /* SD normal operation clocking (wide 4-bit mode) */ - - case CLOCK_SD_TRANSFER_4BIT: -#ifndef CONFIG_STM32_SDIO_WIDTH_D1_ONLY - clckr = (SDIO_CLCKR_SDWIDEXFR | SDIO_CLKCR_CLKEN); - break; -#endif - - /* SD normal operation clocking (narrow 1-bit mode) */ - - case CLOCK_SD_TRANSFER_1BIT: - clckr = (SDIO_CLCKR_SDXFR | SDIO_CLKCR_CLKEN); - break; - } - - /* Set the new clock frequency along with the clock enable/disable bit */ - - stm32_setclkcr(clckr); -} - -/**************************************************************************** - * Name: stm32_attach - * - * Description: - * Attach and prepare interrupts - * - * Input Parameters: - * dev - An instance of the SDIO device interface - * - * Returned Value: - * OK on success; A negated errno on failure. - * - ****************************************************************************/ - -static int stm32_attach(struct sdio_dev_s *dev) -{ - int ret; - - /* Attach the SDIO interrupt handler */ - - ret = irq_attach(STM32_IRQ_SDIO, stm32_interrupt, NULL); - if (ret == OK) - { - /* Disable all interrupts at the SDIO controller and clear static - * interrupt flags - */ - - putreg32(SDIO_MASK_RESET, STM32_SDIO_MASK); - putreg32(SDIO_ICR_STATICFLAGS, STM32_SDIO_ICR); - - /* Enable SDIO interrupts at the NVIC. They can now be enabled at - * the SDIO controller as needed. - */ - - up_enable_irq(STM32_IRQ_SDIO); - } - - return ret; -} - -/**************************************************************************** - * Name: stm32_sendcmd - * - * Description: - * Send the SDIO command - * - * Input Parameters: - * dev - An instance of the SDIO device interface - * cmd - The command to send (32-bits, encoded) - * arg - 32-bit argument required with some commands - * - * Returned Value: - * None - * - ****************************************************************************/ - -static int stm32_sendcmd(struct sdio_dev_s *dev, uint32_t cmd, - uint32_t arg) -{ - uint32_t regval; - uint32_t cmdidx; - - /* Set the SDIO Argument value */ - - putreg32(arg, STM32_SDIO_ARG); - - /* Clear CMDINDEX, WAITRESP, WAITINT, WAITPEND, and CPSMEN bits */ - - regval = getreg32(STM32_SDIO_CMD); - regval &= ~(SDIO_CMD_CMDINDEX_MASK | SDIO_CMD_WAITRESP_MASK | - SDIO_CMD_WAITINT | SDIO_CMD_WAITPEND | SDIO_CMD_CPSMEN); - - /* Set WAITRESP bits */ - - switch (cmd & MMCSD_RESPONSE_MASK) - { - case MMCSD_NO_RESPONSE: - regval |= SDIO_CMD_NORESPONSE; - break; - - case MMCSD_R1_RESPONSE: - case MMCSD_R1B_RESPONSE: - case MMCSD_R3_RESPONSE: - case MMCSD_R4_RESPONSE: - case MMCSD_R5_RESPONSE: - case MMCSD_R6_RESPONSE: - case MMCSD_R7_RESPONSE: - regval |= SDIO_CMD_SHORTRESPONSE; - break; - - case MMCSD_R2_RESPONSE: - regval |= SDIO_CMD_LONGRESPONSE; - break; - } - - /* Set CPSMEN and the command index */ - - cmdidx = (cmd & MMCSD_CMDIDX_MASK) >> MMCSD_CMDIDX_SHIFT; - regval |= cmdidx | SDIO_CMD_CPSMEN; - - mcinfo("cmd: %08" PRIx32 " arg: %08" PRIx32 " regval: %08" PRIx32 - " enabled irq: %08" PRIx32 "\n", - cmd, arg, regval, getreg32(STM32_SDIO_MASK)); - - /* Write the SDIO CMD */ - - putreg32(SDIO_RESPDONE_ICR | SDIO_CMDDONE_ICR, STM32_SDIO_ICR); - putreg32(regval, STM32_SDIO_CMD); - return OK; -} - -/**************************************************************************** - * Name: stm32_blocksetup - * - * Description: - * Configure block size and the number of blocks for next transfer - * - * Input Parameters: - * dev - An instance of the SDIO device interface - * blocklen - The selected block size. - * nblocklen - The number of blocks to transfer - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef CONFIG_SDIO_BLOCKSETUP -static void stm32_blocksetup(struct sdio_dev_s *dev, - unsigned int blocklen, unsigned int nblocks) -{ - struct stm32_dev_s *priv = (struct stm32_dev_s *)dev; - - /* Configure block size for next transfer */ - - priv->block_size = stm32_log2(blocklen); -} -#endif - -/**************************************************************************** - * Name: stm32_recvsetup - * - * Description: - * Setup hardware in preparation for data transfer from the card in non-DMA - * (interrupt driven mode). This method will do whatever controller setup - * is necessary. This would be called for SD memory just BEFORE sending - * CMD13 (SEND_STATUS), CMD17 (READ_SINGLE_BLOCK), CMD18 - * (READ_MULTIPLE_BLOCKS), ACMD51 (SEND_SCR), etc. Normally, - * SDIO_WAITEVENT will be called to receive the indication that the - * transfer is complete. - * - * Input Parameters: - * dev - An instance of the SDIO device interface - * buffer - Address of the buffer in which to receive the data - * nbytes - The number of bytes in the transfer - * - * Returned Value: - * Number of bytes sent on success; a negated errno on failure - * - ****************************************************************************/ - -static int stm32_recvsetup(struct sdio_dev_s *dev, uint8_t *buffer, - size_t nbytes) -{ - struct stm32_dev_s *priv = (struct stm32_dev_s *)dev; - uint32_t dblocksize; - - DEBUGASSERT(priv != NULL && buffer != NULL && nbytes > 0); - DEBUGASSERT(((uint32_t)buffer & 3) == 0); - - /* Reset the DPSM configuration */ - - stm32_datadisable(); - stm32_sampleinit(); - stm32_sample(priv, SAMPLENDX_BEFORE_SETUP); - - /* Save the destination buffer information for use by the interrupt - * handler. - */ - - priv->buffer = (uint32_t *)buffer; - priv->remaining = nbytes; -#ifdef CONFIG_STM32_SDIO_DMA - priv->dmamode = false; -#endif - - /* Then set up the SDIO data path */ - -#ifdef CONFIG_SDIO_BLOCKSETUP - if (priv->block_size != STM32_SDIO_USE_DEFAULT_BLOCKSIZE) - { - dblocksize = priv->block_size << SDIO_DCTRL_DBLOCKSIZE_SHIFT; - } - else -#endif - { - dblocksize = stm32_log2(nbytes) << SDIO_DCTRL_DBLOCKSIZE_SHIFT; - } - - stm32_dataconfig(SDIO_DTIMER_DATATIMEOUT_MS, nbytes, - dblocksize | SDIO_DCTRL_DTDIR); - - /* And enable interrupts */ - - stm32_configxfrints(priv, SDIO_RECV_MASK); - stm32_sample(priv, SAMPLENDX_AFTER_SETUP); - return OK; -} - -/**************************************************************************** - * Name: stm32_sendsetup - * - * Description: - * Setup hardware in preparation for data transfer from the card. This - * method will do whatever controller setup is necessary. This would be - * called for SD memory just AFTER sending CMD24 (WRITE_BLOCK), CMD25 - * (WRITE_MULTIPLE_BLOCK), ... and before SDIO_SENDDATA is called. - * - * Input Parameters: - * dev - An instance of the SDIO device interface - * buffer - Address of the buffer containing the data to send - * nbytes - The number of bytes in the transfer - * - * Returned Value: - * Number of bytes sent on success; a negated errno on failure - * - ****************************************************************************/ - -static int stm32_sendsetup(struct sdio_dev_s *dev, - const uint8_t *buffer, size_t nbytes) -{ - struct stm32_dev_s *priv = (struct stm32_dev_s *)dev; - uint32_t dblocksize; - - DEBUGASSERT(priv != NULL && buffer != NULL && nbytes > 0); - DEBUGASSERT(((uint32_t)buffer & 3) == 0); - - /* Reset the DPSM configuration */ - - stm32_datadisable(); - stm32_sampleinit(); - stm32_sample(priv, SAMPLENDX_BEFORE_SETUP); - - /* Save the source buffer information for use by the interrupt handler */ - - priv->buffer = (uint32_t *)buffer; - priv->remaining = nbytes; -#ifdef CONFIG_STM32_SDIO_DMA - priv->dmamode = false; -#endif - - /* Then set up the SDIO data path */ - -#ifdef CONFIG_SDIO_BLOCKSETUP - if (priv->block_size != STM32_SDIO_USE_DEFAULT_BLOCKSIZE) - { - dblocksize = priv->block_size << SDIO_DCTRL_DBLOCKSIZE_SHIFT; - } - else -#endif - { - dblocksize = stm32_log2(nbytes) << SDIO_DCTRL_DBLOCKSIZE_SHIFT; - } - - stm32_dataconfig(SDIO_DTIMER_DATATIMEOUT_MS, nbytes, dblocksize); - - /* Enable TX interrupts */ - - stm32_configxfrints(priv, SDIO_SEND_MASK); - stm32_sample(priv, SAMPLENDX_AFTER_SETUP); - return OK; -} - -/**************************************************************************** - * Name: stm32_cancel - * - * Description: - * Cancel the data transfer setup of SDIO_RECVSETUP, SDIO_SENDSETUP, - * SDIO_DMARECVSETUP or SDIO_DMASENDSETUP. This must be called to cancel - * the data transfer setup if, for some reason, you cannot perform the - * transfer. - * - * Input Parameters: - * dev - An instance of the SDIO device interface - * - * Returned Value: - * OK is success; a negated errno on failure - * - ****************************************************************************/ - -static int stm32_cancel(struct sdio_dev_s *dev) -{ - struct stm32_dev_s *priv = (struct stm32_dev_s *)dev; - - /* Disable all transfer- and event- related interrupts */ - - stm32_configxfrints(priv, 0); - stm32_configwaitints(priv, 0, 0, 0); - - /* Clearing pending interrupt status on all transfer- and event- related - * interrupts - */ - - putreg32(SDIO_WAITALL_ICR, STM32_SDIO_ICR); - - /* Cancel any watchdog timeout */ - - wd_cancel(&priv->waitwdog); - - /* If this was a DMA transfer, make sure that DMA is stopped */ - -#ifdef CONFIG_STM32_SDIO_DMA - if (priv->dmamode) - { - /* Make sure that the DMA is stopped (it will be stopped automatically - * on normal transfers, but not necessarily when the transfer - * terminates on an error condition. - */ - - stm32_dmastop(priv->dma); - } -#endif - - /* Mark no transfer in progress */ - - priv->remaining = 0; - return OK; -} - -/**************************************************************************** - * Name: stm32_waitresponse - * - * Description: - * Poll-wait for the response to the last command to be ready. - * - * Input Parameters: - * dev - An instance of the SDIO device interface - * cmd - The command that was sent. See 32-bit command definitions above. - * - * Returned Value: - * OK is success; a negated errno on failure - * - ****************************************************************************/ - -static int stm32_waitresponse(struct sdio_dev_s *dev, uint32_t cmd) -{ - int32_t timeout; - uint32_t events; - - switch (cmd & MMCSD_RESPONSE_MASK) - { - case MMCSD_NO_RESPONSE: - events = SDIO_CMDDONE_STA; - timeout = SDIO_CMDTIMEOUT; - break; - - case MMCSD_R1_RESPONSE: - case MMCSD_R1B_RESPONSE: - case MMCSD_R2_RESPONSE: - case MMCSD_R4_RESPONSE: - case MMCSD_R5_RESPONSE: - case MMCSD_R6_RESPONSE: - events = SDIO_RESPDONE_STA; - timeout = SDIO_LONGTIMEOUT; - break; - - case MMCSD_R3_RESPONSE: - case MMCSD_R7_RESPONSE: - events = SDIO_RESPDONE_STA; - timeout = SDIO_CMDTIMEOUT; - break; - - default: - return -EINVAL; - } - - /* Then wait for the response (or timeout) */ - - while ((getreg32(STM32_SDIO_STA) & events) == 0) - { - if (--timeout <= 0) - { - mcerr("ERROR: Timeout cmd: %08" PRIx32 " events: %08" PRIx32 - " STA: %08" PRIx32 "\n", - cmd, events, getreg32(STM32_SDIO_STA)); - - return -ETIMEDOUT; - } - } - - putreg32(SDIO_CMDDONE_ICR, STM32_SDIO_ICR); - return OK; -} - -/**************************************************************************** - * Name: stm32_recv* - * - * Description: - * Receive response to SDIO command. Only the critical payload is - * returned -- that is 32 bits for 48 bit status and 128 bits for 136 bit - * status. The driver implementation should verify the correctness of - * the remaining, non-returned bits (CRCs, CMD index, etc.). - * - * Input Parameters: - * dev - An instance of the SDIO device interface - * Rx - Buffer in which to receive the response - * - * Returned Value: - * Number of bytes sent on success; a negated errno on failure. Here a - * failure means only a failure to obtain the requested response (due to - * transport problem -- timeout, CRC, etc.). The implementation only - * assures that the response is returned intacta and does not check errors - * within the response itself. - * - ****************************************************************************/ - -static int stm32_recvshortcrc(struct sdio_dev_s *dev, uint32_t cmd, - uint32_t *rshort) -{ -#ifdef CONFIG_DEBUG_MEMCARD_INFO - uint32_t respcmd; -#endif - uint32_t regval; - int ret = OK; - - /* R1 Command response (48-bit) - * 47 0 Start bit - * 46 0 Transmission bit (0=from card) - * 45:40 bit5 - bit0 Command index (0-63) - * 39:8 bit31 - bit0 32-bit card status - * 7:1 bit6 - bit0 CRC7 - * 0 1 End bit - * - * R1b Identical to R1 with the additional busy signaling via the data - * line. - * - * R6 Published RCA Response (48-bit, SD card only) - * 47 0 Start bit - * 46 0 Transmission bit (0=from card) - * 45:40 bit5 - bit0 Command index (0-63) - * 39:8 bit31 - bit0 32-bit Argument Field, consisting of: - * [31:16] New published RCA of card - * [15:0] Card status bits {23,22,19,12:0} - * 7:1 bit6 - bit0 CRC7 - * 0 1 End bit - */ - -#ifdef CONFIG_DEBUG_MEMCARD_INFO - if (!rshort) - { - mcerr("ERROR: rshort=NULL\n"); - ret = -EINVAL; - } - - /* Check that this is the correct response to this command */ - - else if ((cmd & MMCSD_RESPONSE_MASK) != MMCSD_R1_RESPONSE && - (cmd & MMCSD_RESPONSE_MASK) != MMCSD_R1B_RESPONSE && - (cmd & MMCSD_RESPONSE_MASK) != MMCSD_R5_RESPONSE && - (cmd & MMCSD_RESPONSE_MASK) != MMCSD_R6_RESPONSE) - { - mcerr("ERROR: Wrong response CMD=%08" PRIx32 "\n", cmd); - ret = -EINVAL; - } - else -#endif - { - /* Check if a timeout or CRC error occurred */ - - regval = getreg32(STM32_SDIO_STA); - if ((regval & SDIO_STA_CTIMEOUT) != 0) - { - mcerr("ERROR: Command timeout: %08" PRIx32 "\n", regval); - ret = -ETIMEDOUT; - } - else if ((regval & SDIO_STA_CCRCFAIL) != 0) - { - mcerr("ERROR: CRC failure: %08" PRIx32 "\n", regval); - ret = -EIO; - } -#ifdef CONFIG_DEBUG_MEMCARD_INFO - else - { - /* Check response received is of desired command */ - - respcmd = getreg32(STM32_SDIO_RESPCMD); - if ((uint8_t)(respcmd & SDIO_RESPCMD_MASK) != - (cmd & MMCSD_CMDIDX_MASK)) - { - mcerr("ERROR: RESCMD=%02" PRIx32 " CMD=%08" PRIx32 "\n", - respcmd, cmd); - ret = -EINVAL; - } - } -#endif - } - - /* Clear all pending message completion events and return the R1/R6 - * response. - */ - - putreg32(SDIO_RESPDONE_ICR | SDIO_CMDDONE_ICR, STM32_SDIO_ICR); - *rshort = getreg32(STM32_SDIO_RESP1); - return ret; -} - -static int stm32_recvlong(struct sdio_dev_s *dev, uint32_t cmd, - uint32_t rlong[4]) -{ - uint32_t regval; - int ret = OK; - - /* R2 CID, CSD register (136-bit) - * 135 0 Start bit - * 134 0 Transmission bit (0=from card) - * 133:128 bit5 - bit0 Reserved - * 127:1 bit127 - bit1 127-bit CID or CSD register - * (including internal CRC) - * 0 1 End bit - */ - -#ifdef CONFIG_DEBUG_MEMCARD_INFO - /* Check that R1 is the correct response to this command */ - - if ((cmd & MMCSD_RESPONSE_MASK) != MMCSD_R2_RESPONSE) - { - mcerr("ERROR: Wrong response CMD=%08" PRIx32 "\n", cmd); - ret = -EINVAL; - } - else -#endif - { - /* Check if a timeout or CRC error occurred */ - - regval = getreg32(STM32_SDIO_STA); - if (regval & SDIO_STA_CTIMEOUT) - { - mcerr("ERROR: Timeout STA: %08" PRIx32 "\n", regval); - ret = -ETIMEDOUT; - } - else if (regval & SDIO_STA_CCRCFAIL) - { - mcerr("ERROR: CRC fail STA: %08" PRIx32 "\n", regval); - ret = -EIO; - } - } - - /* Return the long response */ - - putreg32(SDIO_RESPDONE_ICR | SDIO_CMDDONE_ICR, STM32_SDIO_ICR); - if (rlong) - { - rlong[0] = getreg32(STM32_SDIO_RESP1); - rlong[1] = getreg32(STM32_SDIO_RESP2); - rlong[2] = getreg32(STM32_SDIO_RESP3); - rlong[3] = getreg32(STM32_SDIO_RESP4); - } - - return ret; -} - -static int stm32_recvshort(struct sdio_dev_s *dev, uint32_t cmd, - uint32_t *rshort) -{ - uint32_t regval; - int ret = OK; - - /* R3 OCR (48-bit) - * 47 0 Start bit - * 46 0 Transmission bit (0=from card) - * 45:40 bit5 - bit0 Reserved - * 39:8 bit31 - bit0 32-bit OCR register - * 7:1 bit6 - bit0 Reserved - * 0 1 End bit - */ - - /* Check that this is the correct response to this command */ - -#ifdef CONFIG_DEBUG_MEMCARD_INFO - if ((cmd & MMCSD_RESPONSE_MASK) != MMCSD_R3_RESPONSE && - (cmd & MMCSD_RESPONSE_MASK) != MMCSD_R4_RESPONSE && - (cmd & MMCSD_RESPONSE_MASK) != MMCSD_R7_RESPONSE) - { - mcerr("ERROR: Wrong response CMD=%08" PRIx32 "\n", cmd); - ret = -EINVAL; - } - else -#endif - { - /* Check if a timeout occurred (Apparently a CRC error can terminate - * a good response) - */ - - regval = getreg32(STM32_SDIO_STA); - if (regval & SDIO_STA_CTIMEOUT) - { - mcerr("ERROR: Timeout STA: %08" PRIx32 "\n", regval); - ret = -ETIMEDOUT; - } - } - - putreg32(SDIO_RESPDONE_ICR | SDIO_CMDDONE_ICR, STM32_SDIO_ICR); - if (rshort) - { - *rshort = getreg32(STM32_SDIO_RESP1); - } - - return ret; -} - -/**************************************************************************** - * Name: stm32_waitenable - * - * Description: - * Enable/disable of a set of SDIO wait events. This is part of the - * the SDIO_WAITEVENT sequence. The set of to-be-waited-for events is - * configured before calling stm32_eventwait. This is done in this way - * to help the driver to eliminate race conditions between the command - * setup and the subsequent events. - * - * The enabled events persist until either (1) SDIO_WAITENABLE is called - * again specifying a different set of wait events, or (2) SDIO_EVENTWAIT - * returns. - * - * Input Parameters: - * dev - An instance of the SDIO device interface - * eventset - A bitset of events to enable or disable (see SDIOWAIT_* - * definitions). 0=disable; 1=enable. - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void stm32_waitenable(struct sdio_dev_s *dev, - sdio_eventset_t eventset, uint32_t timeout) -{ - struct stm32_dev_s *priv = (struct stm32_dev_s *)dev; - uint32_t waitmask; - - DEBUGASSERT(priv != NULL); - - /* Disable event-related interrupts */ - - stm32_configwaitints(priv, 0, 0, 0); - - /* Select the interrupt mask that will give us the appropriate wakeup - * interrupts. - */ - -#if defined(CONFIG_MMCSD_SDIOWAIT_WRCOMPLETE) - if ((eventset & SDIOWAIT_WRCOMPLETE) != 0) - { - /* eventset carries this */ - - waitmask = 0; - } - else -#endif - { - waitmask = 0; - if ((eventset & SDIOWAIT_CMDDONE) != 0) - { - waitmask |= SDIO_CMDDONE_MASK; - } - - if ((eventset & SDIOWAIT_RESPONSEDONE) != 0) - { - waitmask |= SDIO_RESPDONE_MASK; - } - - if ((eventset & SDIOWAIT_TRANSFERDONE) != 0) - { - waitmask |= SDIO_XFRDONE_MASK; - } - - /* Enable event-related interrupts */ - - putreg32(SDIO_WAITALL_ICR, STM32_SDIO_ICR); - } - - stm32_configwaitints(priv, waitmask, eventset, 0); - - /* Check if the timeout event is specified in the event set */ - - if ((priv->waitevents & SDIOWAIT_TIMEOUT) != 0) - { - int delay; - int ret; - - /* Yes.. Handle a cornercase: The user request a timeout event but - * with timeout == 0? - */ - - if (!timeout) - { - priv->wkupevent = SDIOWAIT_TIMEOUT; - return; - } - - /* Start the watchdog timer */ - - delay = MSEC2TICK(timeout); - ret = wd_start(&priv->waitwdog, delay, - stm32_eventtimeout, (wdparm_t)priv); - if (ret < 0) - { - mcerr("ERROR: wd_start failed: %d\n", ret); - } - } -} - -/**************************************************************************** - * Name: stm32_eventwait - * - * Description: - * Wait for one of the enabled events to occur (or a timeout). Note that - * all events enabled by SDIO_WAITEVENTS are disabled when stm32_eventwait - * returns. SDIO_WAITEVENTS must be called again before stm32_eventwait - * can be used again. - * - * Input Parameters: - * dev - An instance of the SDIO device interface - * timeout - Maximum time in milliseconds to wait. Zero means immediate - * timeout with no wait. The timeout value is ignored if - * SDIOWAIT_TIMEOUT is not included in the waited-for eventset. - * - * Returned Value: - * Event set containing the event(s) that ended the wait. Should always - * be non-zero. All events are disabled after the wait concludes. - * - ****************************************************************************/ - -static sdio_eventset_t stm32_eventwait(struct sdio_dev_s *dev) -{ - struct stm32_dev_s *priv = (struct stm32_dev_s *)dev; - sdio_eventset_t wkupevent = 0; - irqstate_t flags; - int ret; - - /* There is a race condition here... the event may have completed before - * we get here. In this case waitevents will be zero, but wkupevents will - * be non-zero (and, hopefully, the semaphore count will also be non-zero. - */ - - flags = enter_critical_section(); - -#if defined(CONFIG_MMCSD_SDIOWAIT_WRCOMPLETE) - /* A card ejected while in SDIOWAIT_WRCOMPLETE can lead to a - * condition where there is no waitevents set and no wkupevent - */ - - if (priv->waitevents == 0 && priv->wkupevent == 0) - { - wkupevent = SDIOWAIT_ERROR; - goto errout_with_waitints; - } - -#else - DEBUGASSERT(priv->waitevents != 0 || priv->wkupevent != 0); -#endif - -#if defined(CONFIG_MMCSD_SDIOWAIT_WRCOMPLETE) - if ((priv->waitevents & SDIOWAIT_WRCOMPLETE) != 0) - { - /* Atomically read pin to see if ready (true) and determine if ISR - * fired. If Pin is ready and if ISR did NOT fire end the wait here. - */ - - if (stm32_gpioread(GPIO_SDIO_D0) && - (priv->wkupevent & SDIOWAIT_WRCOMPLETE) == 0) - { - stm32_endwait(priv, SDIOWAIT_WRCOMPLETE); - } - } -#endif - - /* Loop until the event (or the timeout occurs). Race conditions are - * avoided by calling stm32_waitenable prior to triggering the logic that - * will cause the wait to terminate. Under certain race conditions, the - * waited-for may have already occurred before this function was called! - */ - - for (; ; ) - { - /* Wait for an event in event set to occur. If this the event has - * already occurred, then the semaphore will already have been - * incremented and there will be no wait. - */ - - ret = nxsem_wait_uninterruptible(&priv->waitsem); - if (ret < 0) - { - /* Task canceled. Cancel the wdog (assuming it was started) and - * return an SDIO error. - */ - - wd_cancel(&priv->waitwdog); - wkupevent = SDIOWAIT_ERROR; - goto errout_with_waitints; - } - - wkupevent = priv->wkupevent; - - /* Check if the event has occurred. When the event has occurred, then - * evenset will be set to 0 and wkupevent will be set to a nonzero - * value. - */ - - if (wkupevent != 0) - { - /* Yes... break out of the loop with wkupevent non-zero */ - - break; - } - } - - /* Disable event-related interrupts */ - -errout_with_waitints: - stm32_configwaitints(priv, 0, 0, 0); -#ifdef CONFIG_STM32_SDIO_DMA - priv->xfrflags = 0; -#endif - - leave_critical_section(flags); - stm32_dumpsamples(priv); - return wkupevent; -} - -/**************************************************************************** - * Name: stm32_callbackenable - * - * Description: - * Enable/disable of a set of SDIO callback events. This is part of the - * the SDIO callback sequence. The set of events is configured to enabled - * callbacks to the function provided in stm32_registercallback. - * - * Events are automatically disabled once the callback is performed and no - * further callback events will occur until they are again enabled by - * calling this method. - * - * Input Parameters: - * dev - An instance of the SDIO device interface - * eventset - A bitset of events to enable or disable (see SDIOMEDIA_* - * definitions). 0=disable; 1=enable. - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void stm32_callbackenable(struct sdio_dev_s *dev, - sdio_eventset_t eventset) -{ - struct stm32_dev_s *priv = (struct stm32_dev_s *)dev; - - mcinfo("eventset: %02x\n", eventset); - DEBUGASSERT(priv != NULL); - - priv->cbevents = eventset; - stm32_callback(priv); -} - -/**************************************************************************** - * Name: stm32_registercallback - * - * Description: - * Register a callback that that will be invoked on any media status - * change. Callbacks should not be made from interrupt handlers, rather - * interrupt level events should be handled by calling back on the work - * thread. - * - * When this method is called, all callbacks should be disabled until they - * are enabled via a call to SDIO_CALLBACKENABLE - * - * Input Parameters: - * dev - Device-specific state data - * callback - The function to call on the media change - * arg - A caller provided value to return with the callback - * - * Returned Value: - * 0 on success; negated errno on failure. - * - ****************************************************************************/ - -static int stm32_registercallback(struct sdio_dev_s *dev, - worker_t callback, void *arg) -{ - struct stm32_dev_s *priv = (struct stm32_dev_s *)dev; - - /* Disable callbacks and register this callback and is argument */ - - mcinfo("Register %p(%p)\n", callback, arg); - DEBUGASSERT(priv != NULL); - - priv->cbevents = 0; - priv->cbarg = arg; - priv->callback = callback; - return OK; -} - -/**************************************************************************** - * Name: stm32_dmapreflight - * - * Description: - * Preflight an SDIO DMA operation. If the buffer is not well-formed for - * SDIO DMA transfer (alignment, size, etc.) returns an error. - * - * Input Parameters: - * dev - An instance of the SDIO device interface - * buffer - The memory to DMA to/from - * buflen - The size of the DMA transfer in bytes - * - * Returned Value: - * OK on success; a negated errno on failure - ****************************************************************************/ - -#if defined(CONFIG_STM32_SDIO_DMA) && defined(CONFIG_ARCH_HAVE_SDIO_PREFLIGHT) -static int stm32_dmapreflight(struct sdio_dev_s *dev, - const uint8_t *buffer, size_t buflen) -{ -#if !defined(CONFIG_STM32_STM32F4XXX) - struct stm32_dev_s *priv = (struct stm32_dev_s *)dev; - - DEBUGASSERT(priv != NULL && buffer != NULL && buflen > 0); - - /* Wide bus operation is required for DMA */ - - if (!priv->widebus) - { - return -EINVAL; - } -#endif - - /* DMA must be possible to the buffer */ - - if (!stm32_dmacapable((uintptr_t)buffer, (buflen + 3) >> 2, - SDIO_RXDMA32_CONFIG)) - { - return -EFAULT; - } - - return 0; -} -#endif - -/**************************************************************************** - * Name: stm32_dmarecvsetup - * - * Description: - * Setup to perform a read DMA. If the processor supports a data cache, - * then this method will also make sure that the contents of the DMA memory - * and the data cache are coherent. For read transfers this may mean - * invalidating the data cache. - * - * Input Parameters: - * dev - An instance of the SDIO device interface - * buffer - The memory to DMA from - * buflen - The size of the DMA transfer in bytes - * - * Returned Value: - * OK on success; a negated errno on failure - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_SDIO_DMA -static int stm32_dmarecvsetup(struct sdio_dev_s *dev, - uint8_t *buffer, size_t buflen) -{ - struct stm32_dev_s *priv = (struct stm32_dev_s *)dev; - uint32_t dblocksize; - - DEBUGASSERT(priv != NULL && buffer != NULL && buflen > 0); -#ifdef CONFIG_ARCH_HAVE_SDIO_PREFLIGHT - DEBUGASSERT(stm32_dmapreflight(dev, buffer, buflen) == 0); -#endif - - /* Reset the DPSM configuration */ - - stm32_datadisable(); - - /* Initialize register sampling */ - - stm32_sampleinit(); - stm32_sample(priv, SAMPLENDX_BEFORE_SETUP); - - /* Save the destination buffer information for use by the interrupt - * handler. - */ - - priv->buffer = (uint32_t *)buffer; - priv->remaining = buflen; - priv->dmamode = true; - - /* Then set up the SDIO data path */ - -#ifdef CONFIG_SDIO_BLOCKSETUP - if (priv->block_size != STM32_SDIO_USE_DEFAULT_BLOCKSIZE) - { - dblocksize = priv->block_size << SDIO_DCTRL_DBLOCKSIZE_SHIFT; - } - else -#endif - { - dblocksize = stm32_log2(buflen) << SDIO_DCTRL_DBLOCKSIZE_SHIFT; - } - - stm32_dataconfig(SDIO_DTIMER_DATATIMEOUT_MS, buflen, - dblocksize | SDIO_DCTRL_DTDIR); - - /* Configure the RX DMA */ - - stm32_configxfrints(priv, SDIO_DMARECV_MASK); - - putreg32(1, SDIO_DCTRL_DMAEN_BB); - stm32_dmasetup(priv->dma, STM32_SDIO_FIFO, (uint32_t)buffer, - (buflen + 3) >> 2, SDIO_RXDMA32_CONFIG); - - /* Start the DMA */ - - stm32_sample(priv, SAMPLENDX_BEFORE_ENABLE); - stm32_dmastart(priv->dma, stm32_dmacallback, priv, false); - stm32_sample(priv, SAMPLENDX_AFTER_SETUP); - - return OK; -} -#endif - -/**************************************************************************** - * Name: stm32_dmasendsetup - * - * Description: - * Setup to perform a write DMA. If the processor supports a data cache, - * then this method will also make sure that the contents of the DMA memory - * and the data cache are coherent. For write transfers, this may mean - * flushing the data cache. - * - * Input Parameters: - * dev - An instance of the SDIO device interface - * buffer - The memory to DMA into - * buflen - The size of the DMA transfer in bytes - * - * Returned Value: - * OK on success; a negated errno on failure - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_SDIO_DMA -static int stm32_dmasendsetup(struct sdio_dev_s *dev, - const uint8_t *buffer, size_t buflen) -{ - struct stm32_dev_s *priv = (struct stm32_dev_s *)dev; - uint32_t dblocksize; - - DEBUGASSERT(priv != NULL && buffer != NULL && buflen > 0); -#ifdef CONFIG_ARCH_HAVE_SDIO_PREFLIGHT - DEBUGASSERT(stm32_dmapreflight(dev, buffer, buflen) == 0); -#endif - - /* Reset the DPSM configuration */ - - stm32_datadisable(); - - /* Initialize register sampling */ - - stm32_sampleinit(); - stm32_sample(priv, SAMPLENDX_BEFORE_SETUP); - - /* Save the source buffer information for use by the interrupt handler */ - - priv->buffer = (uint32_t *)buffer; - priv->remaining = buflen; - priv->dmamode = true; - - /* Then set up the SDIO data path */ - -#ifdef CONFIG_SDIO_BLOCKSETUP - if (priv->block_size != STM32_SDIO_USE_DEFAULT_BLOCKSIZE) - { - dblocksize = priv->block_size << SDIO_DCTRL_DBLOCKSIZE_SHIFT; - } - else -#endif - { - dblocksize = stm32_log2(buflen) << SDIO_DCTRL_DBLOCKSIZE_SHIFT; - } - - stm32_dataconfig(SDIO_DTIMER_DATATIMEOUT_MS, buflen, dblocksize); - - /* Configure the TX DMA */ - - stm32_dmasetup(priv->dma, STM32_SDIO_FIFO, (uint32_t)buffer, - (buflen + 3) >> 2, SDIO_TXDMA32_CONFIG); - - stm32_sample(priv, SAMPLENDX_BEFORE_ENABLE); - putreg32(1, SDIO_DCTRL_DMAEN_BB); - - /* Start the DMA */ - - stm32_dmastart(priv->dma, stm32_dmacallback, priv, false); - stm32_sample(priv, SAMPLENDX_AFTER_SETUP); - - /* Enable TX interrupts */ - - stm32_configxfrints(priv, SDIO_DMASEND_MASK); - - return OK; -} -#endif - -/**************************************************************************** - * Name: stm32_callback - * - * Description: - * Perform callback. - * - * Assumptions: - * This function does not execute in the context of an interrupt handler. - * It may be invoked on any user thread or scheduled on the work thread - * from an interrupt handler. - * - ****************************************************************************/ - -static void stm32_callback(void *arg) -{ - struct stm32_dev_s *priv = (struct stm32_dev_s *)arg; - - /* Is a callback registered? */ - - DEBUGASSERT(priv != NULL); - mcinfo("Callback %p(%p) cbevents: %02x cdstatus: %02x\n", - priv->callback, priv->cbarg, priv->cbevents, priv->cdstatus); - - if (priv->callback) - { - /* Yes.. Check for enabled callback events */ - - if ((priv->cdstatus & SDIO_STATUS_PRESENT) != 0) - { - /* Media is present. Is the media inserted event enabled? */ - - if ((priv->cbevents & SDIOMEDIA_INSERTED) == 0) - { - /* No... return without performing the callback */ - - return; - } - } - else - { - /* Media is not present. Is the media eject event enabled? */ - - if ((priv->cbevents & SDIOMEDIA_EJECTED) == 0) - { - /* No... return without performing the callback */ - - return; - } - } - - /* Perform the callback, disabling further callbacks. Of course, the - * the callback can (and probably should) re-enable callbacks. - */ - - priv->cbevents = 0; - - /* Callbacks cannot be performed in the context of an interrupt - * handler. If we are in an interrupt handler, then queue the - * callback to be performed later on the work thread. - */ - - if (up_interrupt_context()) - { - /* Yes.. queue it */ - - mcinfo("Queuing callback to %p(%p)\n", - priv->callback, priv->cbarg); - work_queue(HPWORK, &priv->cbwork, priv->callback, - priv->cbarg, 0); - } - else - { - /* No.. then just call the callback here */ - - mcinfo("Callback to %p(%p)\n", priv->callback, priv->cbarg); - priv->callback(priv->cbarg); - } - } -} - -/**************************************************************************** - * Name: stm32_default - * - * Description: - * Restore SDIO registers to their default, reset values - * - ****************************************************************************/ - -static void stm32_default(void) -{ - putreg32(SDIO_POWER_RESET, STM32_SDIO_POWER); - putreg32(SDIO_CLKCR_RESET, STM32_SDIO_CLKCR); - putreg32(SDIO_ARG_RESET, STM32_SDIO_ARG); - putreg32(SDIO_CMD_RESET, STM32_SDIO_CMD); - putreg32(SDIO_DTIMER_RESET, STM32_SDIO_DTIMER); - putreg32(SDIO_DLEN_RESET, STM32_SDIO_DLEN); - putreg32(SDIO_DCTRL_RESET, STM32_SDIO_DCTRL); - putreg32(SDIO_ICR_RESET, STM32_SDIO_ICR); - putreg32(SDIO_MASK_RESET, STM32_SDIO_MASK); -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: sdio_initialize - * - * Description: - * Initialize SDIO for operation. - * - * Input Parameters: - * slotno - Not used. - * - * Returned Value: - * A reference to an SDIO interface structure. NULL is returned on - * failures. - * - ****************************************************************************/ - -struct sdio_dev_s *sdio_initialize(int slotno) -{ - /* There is only one slot */ - - struct stm32_dev_s *priv = &g_sdiodev; - - /* Allocate a DMA channel */ - -#ifdef CONFIG_STM32_SDIO_DMA - priv->dma = stm32_dmachannel(SDIO_DMACHAN); - DEBUGASSERT(priv->dma); -#endif - - /* Configure GPIOs for 4-bit, wide-bus operation (the chip is capable of - * 8-bit wide bus operation but D4-D7 are not configured). - * - * If bus is multiplexed then there is a custom bus configuration utility - * in the scope of the board support package. - */ - -#ifndef CONFIG_SDIO_MUXBUS - stm32_configgpio(GPIO_SDIO_D0 | SDIO_PULLUP_ENABLE); -#ifndef CONFIG_STM32_SDIO_WIDTH_D1_ONLY - stm32_configgpio(GPIO_SDIO_D1 | SDIO_PULLUP_ENABLE); - stm32_configgpio(GPIO_SDIO_D2 | SDIO_PULLUP_ENABLE); - stm32_configgpio(GPIO_SDIO_D3 | SDIO_PULLUP_ENABLE); -#endif - stm32_configgpio(GPIO_SDIO_CK | SDIO_PULLUP_ENABLE); - stm32_configgpio(GPIO_SDIO_CMD | SDIO_PULLUP_ENABLE); -#endif - - /* Reset the card and assure that it is in the initial, unconfigured - * state. - */ - - stm32_reset(&priv->dev); - return &g_sdiodev.dev; -} - -/**************************************************************************** - * Name: sdio_mediachange - * - * Description: - * Called by board-specific logic -- possibly from an interrupt handler -- - * in order to signal to the driver that a card has been inserted or - * removed from the slot - * - * Input Parameters: - * dev - An instance of the SDIO driver device state structure. - * cardinslot - true is a card has been detected in the slot; false if a - * card has been removed from the slot. Only transitions - * (inserted->removed or removed->inserted should be reported) - * - * Returned Value: - * None - * - ****************************************************************************/ - -void sdio_mediachange(struct sdio_dev_s *dev, bool cardinslot) -{ - struct stm32_dev_s *priv = (struct stm32_dev_s *)dev; - sdio_statset_t cdstatus; - irqstate_t flags; - - /* Update card status */ - - flags = enter_critical_section(); - cdstatus = priv->cdstatus; - if (cardinslot) - { - priv->cdstatus |= SDIO_STATUS_PRESENT; - } - else - { - priv->cdstatus &= ~SDIO_STATUS_PRESENT; - } - - leave_critical_section(flags); - - mcinfo("cdstatus OLD: %02x NEW: %02x\n", cdstatus, priv->cdstatus); - - /* Perform any requested callback if the status has changed */ - - if (cdstatus != priv->cdstatus) - { - stm32_callback(priv); - } -} - -/**************************************************************************** - * Name: sdio_wrprotect - * - * Description: - * Called by board-specific logic to report if the card in the slot is - * mechanically write protected. - * - * Input Parameters: - * dev - An instance of the SDIO driver device state structure. - * wrprotect - true is a card is writeprotected. - * - * Returned Value: - * None - * - ****************************************************************************/ - -void sdio_wrprotect(struct sdio_dev_s *dev, bool wrprotect) -{ - struct stm32_dev_s *priv = (struct stm32_dev_s *)dev; - irqstate_t flags; - - /* Update card status */ - - flags = enter_critical_section(); - if (wrprotect) - { - priv->cdstatus |= SDIO_STATUS_WRPROTECTED; - } - else - { - priv->cdstatus &= ~SDIO_STATUS_WRPROTECTED; - } - - mcinfo("cdstatus: %02x\n", priv->cdstatus); - leave_critical_section(flags); -} - -/**************************************************************************** - * Name: sdio_set_sdio_card_isr - * - * Description: - * SDIO card generates interrupt via SDIO_DATA_1 pin. - * Called by board-specific logic to register an ISR for SDIO card. - * - * Input Parameters: - * func - callback function. - * arg - arg to be passed to the function. - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_SDIO_CARD -void sdio_set_sdio_card_isr(struct sdio_dev_s *dev, - int (*func)(void *), void *arg) -{ - struct stm32_dev_s *priv = (struct stm32_dev_s *)dev; - - priv->do_sdio_card = func; - - if (func != NULL) - { - priv->sdiointmask = SDIO_STA_SDIOIT; - priv->do_sdio_arg = arg; - } - else - { - priv->sdiointmask = 0; - } - - putreg32(priv->xfrmask | priv->waitmask | priv->sdiointmask, - STM32_SDIO_MASK); -} -#endif - -#endif /* CONFIG_STM32_SDIO */ diff --git a/arch/arm/src/stm32/stm32_sdio.h b/arch/arm/src/stm32/stm32_sdio.h deleted file mode 100644 index d74b3fe398949..0000000000000 --- a/arch/arm/src/stm32/stm32_sdio.h +++ /dev/null @@ -1,136 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_sdio.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32_STM32_SDIO_H -#define __ARCH_ARM_SRC_STM32_STM32_SDIO_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include -#include - -#include "chip.h" -#include "hardware/stm32_sdio.h" - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -#ifndef __ASSEMBLY__ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Name: sdio_initialize - * - * Description: - * Initialize SDIO for operation. - * - * Input Parameters: - * slotno - Not used. - * - * Returned Value: - * A reference to an SDIO interface structure. NULL is returned on - * failures. - * - ****************************************************************************/ - -struct sdio_dev_s; /* See include/nuttx/sdio.h */ -struct sdio_dev_s *sdio_initialize(int slotno); - -/**************************************************************************** - * Name: sdio_mediachange - * - * Description: - * Called by board-specific logic -- possibly from an interrupt handler -- - * in order to signal to the driver that a card has been inserted or - * removed from the slot - * - * Input Parameters: - * dev - An instance of the SDIO driver device state structure. - * cardinslot - true is a card has been detected in the slot; false if a - * card has been removed from the slot. Only transitions - * (inserted->removed or removed->inserted should be reported) - * - * Returned Value: - * None - * - ****************************************************************************/ - -void sdio_mediachange(struct sdio_dev_s *dev, bool cardinslot); - -/**************************************************************************** - * Name: sdio_wrprotect - * - * Description: - * Called by board-specific logic to report if the card in the slot is - * mechanically write protected. - * - * Input Parameters: - * dev - An instance of the SDIO driver device state structure. - * wrprotect - true is a card is writeprotected. - * - * Returned Value: - * None - * - ****************************************************************************/ - -void sdio_wrprotect(struct sdio_dev_s *dev, bool wrprotect); - -/**************************************************************************** - * Name: sdio_set_sdio_card_isr - * - * Description: - * SDIO card generates interrupt via SDIO_DATA_1 pin. - * Called by board-specific logic to register an ISR for SDIO card. - * - * Input Parameters: - * func - callback function. - * arg - arg to be passed to the function. - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_SDIO_CARD -void sdio_set_sdio_card_isr(struct sdio_dev_s *dev, - int (*func)(void *), void *arg); -#endif - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32_STM32_SDIO_H */ diff --git a/arch/arm/src/stm32/stm32_serial.c b/arch/arm/src/stm32/stm32_serial.c deleted file mode 100644 index 09cbe58c2fc50..0000000000000 --- a/arch/arm/src/stm32/stm32_serial.c +++ /dev/null @@ -1,3765 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_serial.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include - -#ifdef CONFIG_SERIAL_TERMIOS -# include -#endif - -#include - -#include "chip.h" -#include "stm32_uart.h" -#include "stm32_dma.h" -#include "stm32_rcc.h" -#include "arm_internal.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Some sanity checks *******************************************************/ - -/* DMA configuration */ - -/* If DMA is enabled on any USART, then very that other pre-requisites - * have also been selected. - */ - -#ifdef SERIAL_HAVE_RXDMA - -# if defined(CONFIG_STM32_HAVE_IP_DMA_V2) -/* Verify that DMA has been enabled and the DMA channel has been defined. - */ - -# if defined(CONFIG_USART1_RXDMA) || defined(CONFIG_USART6_RXDMA) -# ifndef CONFIG_STM32_DMA2 -# error STM32 USART1/6 receive DMA requires CONFIG_STM32_DMA2 -# endif -# endif - -# if defined(CONFIG_USART2_RXDMA) || defined(CONFIG_USART3_RXDMA) || \ - defined(CONFIG_UART4_RXDMA) || defined(CONFIG_UART5_RXDMA) || \ - defined(CONFIG_UART7_RXDMA) || defined(CONFIG_UART8_RXDMA) -# ifndef CONFIG_STM32_DMA1 -# error STM32 USART2/3/4/5/7/8 receive DMA requires CONFIG_STM32_DMA1 -# endif -# endif - -/* Currently RS-485 support cannot be enabled when RXDMA is in use due to - * lack of testing - RS-485 support was developed on STM32F1x - */ - -# if (defined(CONFIG_USART1_RXDMA) && defined(CONFIG_USART1_RS485)) || \ - (defined(CONFIG_USART2_RXDMA) && defined(CONFIG_USART2_RS485)) || \ - (defined(CONFIG_USART3_RXDMA) && defined(CONFIG_USART3_RS485)) || \ - (defined(CONFIG_UART4_RXDMA) && defined(CONFIG_UART4_RS485)) || \ - (defined(CONFIG_UART5_RXDMA) && defined(CONFIG_UART5_RS485)) || \ - (defined(CONFIG_USART6_RXDMA) && defined(CONFIG_USART6_RS485)) || \ - (defined(CONFIG_UART7_RXDMA) && defined(CONFIG_UART7_RS485)) || \ - (defined(CONFIG_UART8_RXDMA) && defined(CONFIG_UART8_RS485)) -# error "RXDMA and RS-485 cannot be enabled at the same time for the same U[S]ART" -# endif - -/* For the F4, there are alternate DMA channels for USART1 and 6. - * Logic in the board.h file make the DMA channel selection by defining - * the following in the board.h file. - */ - -# if defined(CONFIG_USART1_RXDMA) && !defined(DMAMAP_USART1_RX) -# error "USART1 DMA channel not defined (DMAMAP_USART1_RX)" -# endif - -# if defined(CONFIG_USART2_RXDMA) && !defined(DMAMAP_USART2_RX) -# error "USART2 DMA channel not defined (DMAMAP_USART2_RX)" -# endif - -# if defined(CONFIG_USART3_RXDMA) && !defined(DMAMAP_USART3_RX) -# error "USART3 DMA channel not defined (DMAMAP_USART3_RX)" -# endif - -# if defined(CONFIG_UART4_RXDMA) && !defined(DMAMAP_UART4_RX) -# error "UART4 DMA channel not defined (DMAMAP_UART4_RX)" -# endif - -# if defined(CONFIG_UART5_RXDMA) && !defined(DMAMAP_UART5_RX) -# error "UART5 DMA channel not defined (DMAMAP_UART5_RX)" -# endif - -# if defined(CONFIG_USART6_RXDMA) && !defined(DMAMAP_USART6_RX) -# error "USART6 DMA channel not defined (DMAMAP_USART6_RX)" -# endif - -# if defined(CONFIG_UART7_RXDMA) && !defined(DMAMAP_UART7_RX) -# error "UART7 DMA channel not defined (DMAMAP_UART7_RX)" -# endif - -# if defined(CONFIG_UART8_RXDMA) && !defined(DMAMAP_UART8_RX) -# error "UART8 DMA channel not defined (DMAMAP_UART8_RX)" -# endif - -# elif defined(CONFIG_STM32_HAVE_IP_DMA_V1) - -# if defined(CONFIG_USART1_RXDMA) || defined(CONFIG_USART2_RXDMA) || \ - defined(CONFIG_USART3_RXDMA) || defined(CONFIG_LPUART1_RXDMA) -# ifndef CONFIG_STM32_DMA1 -# error STM32 LPUART1 / USART1/2/3 receive DMA requires CONFIG_STM32_DMA1 -# endif -# endif - -# if defined(CONFIG_UART4_RXDMA) || defined(CONFIG_UART5_RXDMA) -# ifndef CONFIG_STM32_DMA2 -# error STM32 UART4/5 receive DMA requires CONFIG_STM32_DMA2 -# endif -# endif - -/* There are no optional DMA channel assignments for the F1 */ - -# define DMAMAP_USART1_RX DMACHAN_USART1_RX -# define DMAMAP_USART2_RX DMACHAN_USART2_RX -# define DMAMAP_USART3_RX DMACHAN_USART3_RX -# define DMAMAP_UART4_RX DMACHAN_UART4_RX -# define DMAMAP_UART5_RX DMACHAN_UART5_RX -# if defined(CONFIG_LPUART1_RXDMA) && defined(CONFIG_STM32_STM32G4XXX) -# define DMAMAP_LPUART1_RX DMAMAP_DMA12_LPUART1RX_0 -# endif - -# endif - -/* The DMA buffer size when using RX DMA to emulate a FIFO. - * - * When streaming data, the generic serial layer will be called - * every time the FIFO receives half this number of bytes. - */ -# if !defined(CONFIG_STM32_SERIAL_RXDMA_BUFFER_SIZE) -# define CONFIG_STM32_SERIAL_RXDMA_BUFFER_SIZE 32 -# endif -# define RXDMA_MUTIPLE 4 -# define RXDMA_MUTIPLE_MASK (RXDMA_MUTIPLE -1) -# define RXDMA_BUFFER_SIZE ((CONFIG_STM32_SERIAL_RXDMA_BUFFER_SIZE \ - + RXDMA_MUTIPLE_MASK) \ - & ~RXDMA_MUTIPLE_MASK) - -/* DMA priority */ - -# ifndef CONFIG_USART_RXDMAPRIO -# if defined(CONFIG_STM32_HAVE_IP_DMA_V1) -# define CONFIG_USART_RXDMAPRIO DMA_CCR_PRIMED -# elif defined(CONFIG_STM32_HAVE_IP_DMA_V2) -# define CONFIG_USART_RXDMAPRIO DMA_SCR_PRIMED -# else -# error "Unknown STM32 DMA" -# endif -# endif -# if defined(CONFIG_STM32_HAVE_IP_DMA_V1) -# if (CONFIG_USART_RXDMAPRIO & ~DMA_CCR_PL_MASK) != 0 -# error "Illegal value for CONFIG_USART_RXDMAPRIO" -# endif -# elif defined(CONFIG_STM32_HAVE_IP_DMA_V2) -# if (CONFIG_USART_RXDMAPRIO & ~DMA_SCR_PL_MASK) != 0 -# error "Illegal value for CONFIG_USART_RXDMAPRIO" -# endif -# else -# error "Unknown STM32 DMA" -# endif - -/* DMA control word */ - -# if defined(CONFIG_STM32_HAVE_IP_DMA_V2) -# define SERIAL_RXDMA_CONTROL_WORD \ - (DMA_SCR_DIR_P2M | \ - DMA_SCR_CIRC | \ - DMA_SCR_MINC | \ - DMA_SCR_PSIZE_8BITS | \ - DMA_SCR_MSIZE_8BITS | \ - CONFIG_USART_RXDMAPRIO | \ - DMA_SCR_PBURST_SINGLE | \ - DMA_SCR_MBURST_SINGLE) -# else -# define SERIAL_RXDMA_CONTROL_WORD \ - (DMA_CCR_CIRC | \ - DMA_CCR_MINC | \ - DMA_CCR_PSIZE_8BITS | \ - DMA_CCR_MSIZE_8BITS | \ - CONFIG_USART_RXDMAPRIO) -# endif - -#endif /* SERIAL_HAVE_RXDMA */ - -#ifdef SERIAL_HAVE_TXDMA - -# if defined(CONFIG_STM32_HAVE_IP_DMA_V2) - -/* Verify that DMA has been enabled and the DMA channel has been defined. - */ - -# if defined(CONFIG_USART1_TXDMA) || defined(CONFIG_USART6_TXDMA) -# ifndef CONFIG_STM32_DMA2 -# error STM32 USART1/6 receive DMA requires CONFIG_STM32_DMA2 -# endif -# endif - -# if defined(CONFIG_USART2_TXDMA) || defined(CONFIG_USART3_TXDMA) || \ - defined(CONFIG_UART4_TXDMA) || defined(CONFIG_UART5_TXDMA) || \ - defined(CONFIG_UART7_TXDMA) || defined(CONFIG_UART8_TXDMA) -# ifndef CONFIG_STM32_DMA1 -# error STM32 USART2/3/4/5/7/8 receive DMA requires CONFIG_STM32_DMA1 -# endif -# endif - -/* Currently RS-485 support cannot be enabled when TXDMA is in use due to - * lack of testing - RS-485 support was developed on STM32F1x - */ - -# if (defined(CONFIG_USART1_TXDMA) && defined(CONFIG_USART1_RS485)) || \ - (defined(CONFIG_USART2_TXDMA) && defined(CONFIG_USART2_RS485)) || \ - (defined(CONFIG_USART3_TXDMA) && defined(CONFIG_USART3_RS485)) || \ - (defined(CONFIG_UART4_TXDMA) && defined(CONFIG_UART4_RS485)) || \ - (defined(CONFIG_UART5_TXDMA) && defined(CONFIG_UART5_RS485)) || \ - (defined(CONFIG_USART6_TXDMA) && defined(CONFIG_USART6_RS485)) || \ - (defined(CONFIG_UART7_TXDMA) && defined(CONFIG_UART7_RS485)) || \ - (defined(CONFIG_UART8_TXDMA) && defined(CONFIG_UART8_RS485)) -# error "TXDMA and RS-485 cannot be enabled at the same time for the same U[S]ART" -# endif - -# if defined(CONFIG_USART1_TXDMA) && !defined(DMAMAP_USART1_TX) -# error "USART1 DMA channel not defined (DMAMAP_USART1_TX)" -# endif - -# if defined(CONFIG_USART2_TXDMA) && !defined(DMAMAP_USART2_TX) -# error "USART2 DMA channel not defined (DMAMAP_USART2_TX)" -# endif - -# if defined(CONFIG_USART3_TXDMA) && !defined(DMAMAP_USART3_TX) -# error "USART3 DMA channel not defined (DMAMAP_USART3_TX)" -# endif - -# if defined(CONFIG_UART4_TXDMA) && !defined(DMAMAP_UART4_TX) -# error "UART4 DMA channel not defined (DMAMAP_UART4_TX)" -# endif - -# if defined(CONFIG_UART5_TXDMA) && !defined(DMAMAP_UART5_TX) -# error "UART5 DMA channel not defined (DMAMAP_UART5_TX)" -# endif - -# if defined(CONFIG_USART6_TXDMA) && !defined(DMAMAP_USART6_TX) -# error "USART6 DMA channel not defined (DMAMAP_USART6_TX)" -# endif - -# if defined(CONFIG_UART7_TXDMA) && !defined(DMAMAP_UART7_TX) -# error "UART7 DMA channel not defined (DMAMAP_UART7_TX)" -# endif - -# if defined(CONFIG_UART8_TXDMA) && !defined(DMAMAP_UART8_TX) -# error "UART8 DMA channel not defined (DMAMAP_UART8_TX)" -# endif - -# elif defined(CONFIG_STM32_HAVE_IP_DMA_V1) - -# if defined(CONFIG_USART1_TXDMA) || defined(CONFIG_USART2_TXDMA) || \ - defined(CONFIG_USART3_TXDMA) || defined(CONFIG_LPUART1_TXDMA) -# ifndef CONFIG_STM32_DMA1 -# error STM32 USART1/2/3 receive DMA requires CONFIG_STM32_DMA1 -# endif -# endif - -# if defined(CONFIG_UART4_TXDMA) || defined(CONFIG_UART5_TXDMA) -# ifndef CONFIG_STM32_DMA2 -# error STM32 UART4/5 receive DMA requires CONFIG_STM32_DMA2 -# endif -# endif - -# define DMAMAP_USART1_TX DMACHAN_USART1_TX -# define DMAMAP_USART2_TX DMACHAN_USART2_TX -# define DMAMAP_USART3_TX DMACHAN_USART3_TX -# define DMAMAP_UART4_TX DMACHAN_UART4_TX -# define DMAMAP_UART5_TX DMACHAN_UART5_TX -# if defined(CONFIG_LPUART1_TXDMA) && defined(CONFIG_STM32_STM32G4XXX) -# define DMAMAP_LPUART1_TX DMAMAP_DMA12_LPUART1TX_0 -# endif - -# endif - -/* DMA priority */ - -# ifndef CONFIG_USART_TXDMAPRIO -# if defined(CONFIG_STM32_HAVE_IP_DMA_V1) -# define CONFIG_USART_TXDMAPRIO DMA_CCR_PRIMED -# elif defined(CONFIG_STM32_HAVE_IP_DMA_V2) -# define CONFIG_USART_TXDMAPRIO DMA_SCR_PRIMED -# else -# error "Unknown STM32 DMA" -# endif -# endif -# if defined(CONFIG_STM32_HAVE_IP_DMA_V1) -# if (CONFIG_USART_TXDMAPRIO & ~DMA_CCR_PL_MASK) != 0 -# error "Illegal value for CONFIG_USART_TXDMAPRIO" -# endif -# elif defined(CONFIG_STM32_HAVE_IP_DMA_V2) -# if (CONFIG_USART_TXDMAPRIO & ~DMA_SCR_PL_MASK) != 0 -# error "Illegal value for CONFIG_USART_TXDMAPRIO" -# endif -# else -# error "Unknown STM32 DMA" -# endif - -/* DMA control word */ - -# if defined(CONFIG_STM32_HAVE_IP_DMA_V2) -# define SERIAL_TXDMA_CONTROL_WORD \ - (DMA_SCR_DIR_M2P | \ - DMA_SCR_MINC | \ - DMA_SCR_PSIZE_8BITS | \ - DMA_SCR_MSIZE_8BITS | \ - CONFIG_USART_TXDMAPRIO | \ - DMA_SCR_PBURST_SINGLE | \ - DMA_SCR_MBURST_SINGLE) -# elif defined(CONFIG_STM32_HAVE_IP_DMA_V1) -# define SERIAL_TXDMA_CONTROL_WORD \ - (DMA_CCR_DIR | \ - DMA_CCR_MINC | \ - DMA_CCR_PSIZE_8BITS | \ - DMA_CCR_MSIZE_8BITS | \ - CONFIG_USART_TXDMAPRIO) -# else -# error "Unknown STM32 DMA" -# endif - -/* DMA ISR status */ - -# if defined(CONFIG_STM32_HAVE_IP_DMA_V1) -# define DMA_ISR_HTIF_BIT DMA_CHAN_HTIF_BIT -# define DMA_ISR_TCIF_BIT DMA_CHAN_TCIF_BIT -# elif defined(CONFIG_STM32_HAVE_IP_DMA_V2) -# define DMA_ISR_HTIF_BIT DMA_STREAM_HTIF_BIT -# define DMA_ISR_TCIF_BIT DMA_STREAM_TCIF_BIT -# else -# error "Unknown STM32 DMA" -# endif - -#endif /* SERIAL_HAVE_TXDMA */ - -/* Power management definitions */ - -#if defined(CONFIG_PM) && !defined(CONFIG_STM32_PM_SERIAL_ACTIVITY) -# define CONFIG_STM32_PM_SERIAL_ACTIVITY 10 -#endif - -/* Since RX DMA or TX DMA or both may be enabled for a given U[S]ART. - * We need runtime detection in up_dma_setup and up_dma_shutdown - * We use the default struct default init value of 0 which maps to - * STM32_DMA_MAP(DMA1,DMA_STREAM0,DMA_CHAN0) which is not a U[S]ART. - */ - -#define INVALID_SERIAL_DMA_CHANNEL 0 - -/* Keep track if a Break was set - * - * Note: - * - * 1) This value is set in the priv->ie but never written to the control - * register. It must not collide with USART_CR1_USED_INTS or USART_CR3_EIE - * 2) USART_CR3_EIE is also carried in the up_dev_s ie member. - * - * See up_restoreusartint where the masking is done. - */ - -#ifdef CONFIG_STM32_SERIALBRK_BSDCOMPAT -# define USART_CR1_IE_BREAK_INPROGRESS_SHFTS 15 -# define USART_CR1_IE_BREAK_INPROGRESS (1 << USART_CR1_IE_BREAK_INPROGRESS_SHFTS) -#endif - -#ifdef USE_SERIALDRIVER -#ifdef HAVE_SERIALDRIVER - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -struct up_dev_s -{ - struct uart_dev_s dev; /* Generic UART device */ - uint16_t ie; /* Saved interrupt mask bits value */ - uint16_t sr; /* Saved status bits */ - - /* Has been initialized and HW is setup. */ - - bool initialized; - - /* If termios are supported, then the following fields may vary at - * runtime. - */ - -#ifdef CONFIG_SERIAL_TERMIOS - uint8_t parity; /* 0=none, 1=odd, 2=even */ - uint8_t bits; /* Number of bits (7 or 8) */ - bool stopbits2; /* True: Configure with 2 stop bits instead of 1 */ -#ifdef CONFIG_SERIAL_IFLOWCONTROL - bool iflow; /* input flow control (RTS) enabled */ -#endif -#ifdef CONFIG_SERIAL_OFLOWCONTROL - bool oflow; /* output flow control (CTS) enabled */ -#endif - uint32_t baud; /* Configured baud */ -#else - const uint8_t parity; /* 0=none, 1=odd, 2=even */ - const uint8_t bits; /* Number of bits (7 or 8) */ - const bool stopbits2; /* True: Configure with 2 stop bits instead of 1 */ -#ifdef CONFIG_SERIAL_IFLOWCONTROL - const bool iflow; /* input flow control (RTS) enabled */ -#endif -#ifdef CONFIG_SERIAL_OFLOWCONTROL - const bool oflow; /* output flow control (CTS) enabled */ -#endif - const uint32_t baud; /* Configured baud */ -#endif - - const uint8_t irq; /* IRQ associated with this USART */ - const uint32_t apbclock; /* PCLK 1 or 2 frequency */ - const uint32_t usartbase; /* Base address of USART registers */ - const uint32_t tx_gpio; /* U[S]ART TX GPIO pin configuration */ - const uint32_t rx_gpio; /* U[S]ART RX GPIO pin configuration */ -#ifdef CONFIG_SERIAL_IFLOWCONTROL - const uint32_t rts_gpio; /* U[S]ART RTS GPIO pin configuration */ -#endif -#ifdef CONFIG_SERIAL_OFLOWCONTROL - const uint32_t cts_gpio; /* U[S]ART CTS GPIO pin configuration */ -#endif -#ifdef CONFIG_SERIAL_TIOCGICOUNT - struct serial_icounter_s icount; /* U[S]ART error report */ -#endif - - /* TX DMA state */ - -#ifdef SERIAL_HAVE_TXDMA - const unsigned int txdma_channel; /* DMA channel assigned */ - DMA_HANDLE txdma; /* currently-open transmit DMA stream */ -#endif - -#ifdef SERIAL_HAVE_RXDMA - const unsigned int rxdma_channel; /* DMA channel assigned */ -#endif - - /* RX DMA state */ - -#ifdef SERIAL_HAVE_RXDMA - DMA_HANDLE rxdma; /* currently-open receive DMA stream */ - bool rxenable; /* DMA-based reception en/disable */ - uint32_t rxdmanext; /* Next byte in the DMA buffer to be read */ - char *const rxfifo; /* Receive DMA buffer */ -#endif - -#ifdef HAVE_RS485 - const uint32_t rs485_dir_gpio; /* U[S]ART RS-485 DIR GPIO pin cfg */ - const bool rs485_dir_polarity; /* U[S]ART RS-485 DIR TXEN polarity */ -#endif - const bool islpuart; /* Is this device a Low Power UART? */ - spinlock_t lock; /* Spinlock */ -}; - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -static void up_set_format(struct uart_dev_s *dev); -static int up_setup(struct uart_dev_s *dev); -static void up_shutdown(struct uart_dev_s *dev); -static int up_attach(struct uart_dev_s *dev); -static void up_detach(struct uart_dev_s *dev); -static int up_interrupt(int irq, void *context, void *arg); -static int up_ioctl(struct file *filep, int cmd, unsigned long arg); -#if defined(SERIAL_HAVE_TXDMA_OPS) || defined(SERIAL_HAVE_NODMA_OPS) -static int up_receive(struct uart_dev_s *dev, unsigned int *status); -static void up_rxint(struct uart_dev_s *dev, bool enable); -static bool up_rxavailable(struct uart_dev_s *dev); -#endif -#ifdef CONFIG_SERIAL_IFLOWCONTROL -static bool up_rxflowcontrol(struct uart_dev_s *dev, unsigned int nbuffered, - bool upper); -#endif -static void up_send(struct uart_dev_s *dev, int ch); -#if defined(SERIAL_HAVE_RXDMA_OPS) || defined(SERIAL_HAVE_NODMA_OPS) || \ - defined(CONFIG_STM32_SERIALBRK_BSDCOMPAT) -static void up_txint(struct uart_dev_s *dev, bool enable); -#endif -static bool up_txready(struct uart_dev_s *dev); - -#ifdef SERIAL_HAVE_TXDMA -static void up_dma_send(struct uart_dev_s *dev); -static void up_dma_txint(struct uart_dev_s *dev, bool enable); -static void up_dma_txavailable(struct uart_dev_s *dev); -static void up_dma_txcallback(DMA_HANDLE handle, uint8_t status, void *arg); -#endif - -#if defined(SERIAL_HAVE_RXDMA) || defined(SERIAL_HAVE_TXDMA) -static int up_dma_setup(struct uart_dev_s *dev); -static void up_dma_shutdown(struct uart_dev_s *dev); -#endif - -#ifdef SERIAL_HAVE_RXDMA -static int up_dma_receive(struct uart_dev_s *dev, unsigned int *status); -static void up_dma_rxint(struct uart_dev_s *dev, bool enable); -static bool up_dma_rxavailable(struct uart_dev_s *dev); - -static void up_dma_rxcallback(DMA_HANDLE handle, uint8_t status, void *arg); -#endif - -#ifdef CONFIG_PM -static void up_pm_notify(struct pm_callback_s *cb, int dowmin, - enum pm_state_e pmstate); -static int up_pm_prepare(struct pm_callback_s *cb, int domain, - enum pm_state_e pmstate); -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -#ifdef SERIAL_HAVE_NODMA_OPS -static const struct uart_ops_s g_uart_ops = -{ - .setup = up_setup, - .shutdown = up_shutdown, - .attach = up_attach, - .detach = up_detach, - .ioctl = up_ioctl, - .receive = up_receive, - .rxint = up_rxint, - .rxavailable = up_rxavailable, -#ifdef CONFIG_SERIAL_IFLOWCONTROL - .rxflowcontrol = up_rxflowcontrol, -#endif - .send = up_send, - .txint = up_txint, - .txready = up_txready, - .txempty = up_txready, -}; -#endif - -#ifdef SERIAL_HAVE_RXTXDMA_OPS -static const struct uart_ops_s g_uart_rxtxdma_ops = -{ - .setup = up_dma_setup, - .shutdown = up_dma_shutdown, - .attach = up_attach, - .detach = up_detach, - .ioctl = up_ioctl, - .receive = up_dma_receive, - .rxint = up_dma_rxint, - .rxavailable = up_dma_rxavailable, -#ifdef CONFIG_SERIAL_IFLOWCONTROL - .rxflowcontrol = up_rxflowcontrol, -#endif - .send = up_send, - .txint = up_dma_txint, - .txready = up_txready, - .txempty = up_txready, - .dmatxavail = up_dma_txavailable, - .dmasend = up_dma_send, -}; -#endif - -#ifdef SERIAL_HAVE_RXDMA_OPS -static const struct uart_ops_s g_uart_rxdma_ops = -{ - .setup = up_dma_setup, - .shutdown = up_dma_shutdown, - .attach = up_attach, - .detach = up_detach, - .ioctl = up_ioctl, - .receive = up_dma_receive, - .rxint = up_dma_rxint, - .rxavailable = up_dma_rxavailable, -#ifdef CONFIG_SERIAL_IFLOWCONTROL - .rxflowcontrol = up_rxflowcontrol, -#endif - .send = up_send, - .txint = up_txint, - .txready = up_txready, - .txempty = up_txready, -}; -#endif - -#ifdef SERIAL_HAVE_TXDMA_OPS -static const struct uart_ops_s g_uart_txdma_ops = -{ - .setup = up_dma_setup, - .shutdown = up_dma_shutdown, - .attach = up_attach, - .detach = up_detach, - .ioctl = up_ioctl, - .receive = up_receive, - .rxint = up_rxint, - .rxavailable = up_rxavailable, -#ifdef CONFIG_SERIAL_IFLOWCONTROL - .rxflowcontrol = up_rxflowcontrol, -#endif - .send = up_send, - .txint = up_dma_txint, - .txready = up_txready, - .txempty = up_txready, - .dmatxavail = up_dma_txavailable, - .dmasend = up_dma_send, -}; -#endif - -/* I/O buffers */ - -#ifdef CONFIG_STM32_USART1_SERIALDRIVER -static char g_usart1rxbuffer[CONFIG_USART1_RXBUFSIZE]; -static char g_usart1txbuffer[CONFIG_USART1_TXBUFSIZE]; -# ifdef CONFIG_USART1_RXDMA -static char g_usart1rxfifo[RXDMA_BUFFER_SIZE]; -# endif -#endif - -#ifdef CONFIG_STM32_USART2_SERIALDRIVER -static char g_usart2rxbuffer[CONFIG_USART2_RXBUFSIZE]; -static char g_usart2txbuffer[CONFIG_USART2_TXBUFSIZE]; -# ifdef CONFIG_USART2_RXDMA -static char g_usart2rxfifo[RXDMA_BUFFER_SIZE]; -# endif -#endif - -#ifdef CONFIG_STM32_USART3_SERIALDRIVER -static char g_usart3rxbuffer[CONFIG_USART3_RXBUFSIZE]; -static char g_usart3txbuffer[CONFIG_USART3_TXBUFSIZE]; -# ifdef CONFIG_USART3_RXDMA -static char g_usart3rxfifo[RXDMA_BUFFER_SIZE]; -# endif -#endif - -#ifdef CONFIG_STM32_UART4_SERIALDRIVER -static char g_uart4rxbuffer[CONFIG_UART4_RXBUFSIZE]; -static char g_uart4txbuffer[CONFIG_UART4_TXBUFSIZE]; -# ifdef CONFIG_UART4_RXDMA -static char g_uart4rxfifo[RXDMA_BUFFER_SIZE]; -# endif -#endif - -#ifdef CONFIG_STM32_UART5_SERIALDRIVER -static char g_uart5rxbuffer[CONFIG_UART5_RXBUFSIZE]; -static char g_uart5txbuffer[CONFIG_UART5_TXBUFSIZE]; -# ifdef CONFIG_UART5_RXDMA -static char g_uart5rxfifo[RXDMA_BUFFER_SIZE]; -# endif -#endif - -#ifdef CONFIG_STM32_USART6_SERIALDRIVER -static char g_usart6rxbuffer[CONFIG_USART6_RXBUFSIZE]; -static char g_usart6txbuffer[CONFIG_USART6_TXBUFSIZE]; -# ifdef CONFIG_USART6_RXDMA -static char g_usart6rxfifo[RXDMA_BUFFER_SIZE]; -# endif -#endif - -#ifdef CONFIG_STM32_UART7_SERIALDRIVER -static char g_uart7rxbuffer[CONFIG_UART7_RXBUFSIZE]; -static char g_uart7txbuffer[CONFIG_UART7_TXBUFSIZE]; -# ifdef CONFIG_UART7_RXDMA -static char g_uart7rxfifo[RXDMA_BUFFER_SIZE]; -# endif -#endif - -#ifdef CONFIG_STM32_UART8_SERIALDRIVER -static char g_uart8rxbuffer[CONFIG_UART8_RXBUFSIZE]; -static char g_uart8txbuffer[CONFIG_UART8_TXBUFSIZE]; -# ifdef CONFIG_UART8_RXDMA -static char g_uart8rxfifo[RXDMA_BUFFER_SIZE]; -# endif -#endif - -#ifdef CONFIG_STM32_LPUART1_SERIALDRIVER -static char g_lpuart1rxbuffer[CONFIG_LPUART1_RXBUFSIZE]; -static char g_lpuart1txbuffer[CONFIG_LPUART1_TXBUFSIZE]; -# ifdef CONFIG_LPUART1_RXDMA -static char g_lpuart1rxfifo[RXDMA_BUFFER_SIZE]; -# endif -#endif - -/* This describes the state of the STM32 USART1 ports. */ - -#ifdef CONFIG_STM32_USART1_SERIALDRIVER -static struct up_dev_s g_usart1priv = -{ - .dev = - { -# if CONSOLE_UART == 1 - .isconsole = true, -# endif - .recv = - { - .size = CONFIG_USART1_RXBUFSIZE, - .buffer = g_usart1rxbuffer, - }, - .xmit = - { - .size = CONFIG_USART1_TXBUFSIZE, - .buffer = g_usart1txbuffer, - }, -# if defined(CONFIG_USART1_RXDMA) && defined(CONFIG_USART1_TXDMA) - .ops = &g_uart_rxtxdma_ops, -# elif defined(CONFIG_USART1_RXDMA) && !defined(CONFIG_USART1_TXDMA) - .ops = &g_uart_rxdma_ops, -# elif !defined(CONFIG_USART1_RXDMA) && defined(CONFIG_USART1_TXDMA) - .ops = &g_uart_txdma_ops, -# else - .ops = &g_uart_ops, -# endif - .priv = &g_usart1priv, - }, - - .islpuart = false, - .irq = STM32_IRQ_USART1, - .parity = CONFIG_USART1_PARITY, - .bits = CONFIG_USART1_BITS, - .stopbits2 = CONFIG_USART1_2STOP, - .baud = CONFIG_USART1_BAUD, -# if defined(CONFIG_STM32_STM32F33XX) || defined(CONFIG_STM32_STM32F302) - .apbclock = STM32_PCLK1_FREQUENCY, /* Errata 2.5.1 */ -# else - .apbclock = STM32_PCLK2_FREQUENCY, -# endif - .usartbase = STM32_USART1_BASE, - .tx_gpio = GPIO_USART1_TX, - .rx_gpio = GPIO_USART1_RX, -# if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_USART1_OFLOWCONTROL) - .oflow = true, - .cts_gpio = GPIO_USART1_CTS, -# endif -# if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_USART1_IFLOWCONTROL) - .iflow = true, - .rts_gpio = GPIO_USART1_RTS, -# endif -# ifdef CONFIG_USART1_TXDMA - .txdma_channel = DMAMAP_USART1_TX, -# endif -# ifdef CONFIG_USART1_RXDMA - .rxdma_channel = DMAMAP_USART1_RX, - .rxfifo = g_usart1rxfifo, -# endif - -# ifdef CONFIG_USART1_RS485 - .rs485_dir_gpio = GPIO_USART1_RS485_DIR, -# if (CONFIG_USART1_RS485_DIR_POLARITY == 0) - .rs485_dir_polarity = false, -# else - .rs485_dir_polarity = true, -# endif -# endif - .lock = SP_UNLOCKED, -}; -#endif - -/* This describes the state of the STM32 USART2 port. */ - -#ifdef CONFIG_STM32_USART2_SERIALDRIVER -static struct up_dev_s g_usart2priv = -{ - .dev = - { -# if CONSOLE_UART == 2 - .isconsole = true, -# endif - .recv = - { - .size = CONFIG_USART2_RXBUFSIZE, - .buffer = g_usart2rxbuffer, - }, - .xmit = - { - .size = CONFIG_USART2_TXBUFSIZE, - .buffer = g_usart2txbuffer, - }, -# if defined(CONFIG_USART2_RXDMA) && defined(CONFIG_USART2_TXDMA) - .ops = &g_uart_rxtxdma_ops, -# elif defined(CONFIG_USART2_RXDMA) && !defined(CONFIG_USART2_TXDMA) - .ops = &g_uart_rxdma_ops, -# elif !defined(CONFIG_USART2_RXDMA) && defined(CONFIG_USART2_TXDMA) - .ops = &g_uart_txdma_ops, -# else - .ops = &g_uart_ops, -# endif - .priv = &g_usart2priv, - }, - - .islpuart = false, - .irq = STM32_IRQ_USART2, - .parity = CONFIG_USART2_PARITY, - .bits = CONFIG_USART2_BITS, - .stopbits2 = CONFIG_USART2_2STOP, - .baud = CONFIG_USART2_BAUD, - .apbclock = STM32_PCLK1_FREQUENCY, - .usartbase = STM32_USART2_BASE, - .tx_gpio = GPIO_USART2_TX, - .rx_gpio = GPIO_USART2_RX, -# if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_USART2_OFLOWCONTROL) - .oflow = true, - .cts_gpio = GPIO_USART2_CTS, -# endif -# if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_USART2_IFLOWCONTROL) - .iflow = true, - .rts_gpio = GPIO_USART2_RTS, -# endif -# ifdef CONFIG_USART2_TXDMA - .txdma_channel = DMAMAP_USART2_TX, -# endif -# ifdef CONFIG_USART2_RXDMA - .rxdma_channel = DMAMAP_USART2_RX, - .rxfifo = g_usart2rxfifo, -# endif - -# ifdef CONFIG_USART2_RS485 - .rs485_dir_gpio = GPIO_USART2_RS485_DIR, -# if (CONFIG_USART2_RS485_DIR_POLARITY == 0) - .rs485_dir_polarity = false, -# else - .rs485_dir_polarity = true, -# endif -# endif - .lock = SP_UNLOCKED, -}; -#endif - -/* This describes the state of the STM32 USART3 port. */ - -#ifdef CONFIG_STM32_USART3_SERIALDRIVER -static struct up_dev_s g_usart3priv = -{ - .dev = - { -# if CONSOLE_UART == 3 - .isconsole = true, -# endif - .recv = - { - .size = CONFIG_USART3_RXBUFSIZE, - .buffer = g_usart3rxbuffer, - }, - .xmit = - { - .size = CONFIG_USART3_TXBUFSIZE, - .buffer = g_usart3txbuffer, - }, -# if defined(CONFIG_USART3_RXDMA) && defined(CONFIG_USART3_TXDMA) - .ops = &g_uart_rxtxdma_ops, -# elif defined(CONFIG_USART3_RXDMA) && !defined(CONFIG_USART3_TXDMA) - .ops = &g_uart_rxdma_ops, -# elif !defined(CONFIG_USART3_RXDMA) && defined(CONFIG_USART3_TXDMA) - .ops = &g_uart_txdma_ops, -# else - .ops = &g_uart_ops, -# endif - .priv = &g_usart3priv, - }, - - .islpuart = false, - .irq = STM32_IRQ_USART3, - .parity = CONFIG_USART3_PARITY, - .bits = CONFIG_USART3_BITS, - .stopbits2 = CONFIG_USART3_2STOP, - .baud = CONFIG_USART3_BAUD, - .apbclock = STM32_PCLK1_FREQUENCY, - .usartbase = STM32_USART3_BASE, - .tx_gpio = GPIO_USART3_TX, - .rx_gpio = GPIO_USART3_RX, -# if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_USART3_OFLOWCONTROL) - .oflow = true, - .cts_gpio = GPIO_USART3_CTS, -# endif -# if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_USART3_IFLOWCONTROL) - .iflow = true, - .rts_gpio = GPIO_USART3_RTS, -# endif -# ifdef CONFIG_USART3_TXDMA - .txdma_channel = DMAMAP_USART3_TX, -# endif -# ifdef CONFIG_USART3_RXDMA - .rxdma_channel = DMAMAP_USART3_RX, - .rxfifo = g_usart3rxfifo, -# endif - -# ifdef CONFIG_USART3_RS485 - .rs485_dir_gpio = GPIO_USART3_RS485_DIR, -# if (CONFIG_USART3_RS485_DIR_POLARITY == 0) - .rs485_dir_polarity = false, -# else - .rs485_dir_polarity = true, -# endif -# endif - .lock = SP_UNLOCKED, -}; -#endif - -/* This describes the state of the STM32 UART4 port. */ - -#ifdef CONFIG_STM32_UART4_SERIALDRIVER -static struct up_dev_s g_uart4priv = -{ - .dev = - { -# if CONSOLE_UART == 4 - .isconsole = true, -# endif - .recv = - { - .size = CONFIG_UART4_RXBUFSIZE, - .buffer = g_uart4rxbuffer, - }, - .xmit = - { - .size = CONFIG_UART4_TXBUFSIZE, - .buffer = g_uart4txbuffer, - }, -# if defined(CONFIG_UART4_RXDMA) && defined(CONFIG_UART4_TXDMA) - .ops = &g_uart_rxtxdma_ops, -# elif defined(CONFIG_UART4_RXDMA) && !defined(CONFIG_UART4_TXDMA) - .ops = &g_uart_rxdma_ops, -# elif !defined(CONFIG_UART4_RXDMA) && defined(CONFIG_UART4_TXDMA) - .ops = &g_uart_txdma_ops, -# else - .ops = &g_uart_ops, -# endif - .priv = &g_uart4priv, - }, - - .islpuart = false, - .irq = STM32_IRQ_UART4, - .parity = CONFIG_UART4_PARITY, - .bits = CONFIG_UART4_BITS, - .stopbits2 = CONFIG_UART4_2STOP, -# if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_UART4_OFLOWCONTROL) - .oflow = true, - .cts_gpio = GPIO_UART4_CTS, -# endif -# if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_UART4_IFLOWCONTROL) - .iflow = true, - .rts_gpio = GPIO_UART4_RTS, -# endif - .baud = CONFIG_UART4_BAUD, - .apbclock = STM32_PCLK1_FREQUENCY, - .usartbase = STM32_UART4_BASE, - .tx_gpio = GPIO_UART4_TX, - .rx_gpio = GPIO_UART4_RX, -# ifdef CONFIG_UART4_TXDMA - .txdma_channel = DMAMAP_UART4_TX, -# endif -# ifdef CONFIG_UART4_RXDMA - .rxdma_channel = DMAMAP_UART4_RX, - .rxfifo = g_uart4rxfifo, -# endif - -# ifdef CONFIG_UART4_RS485 - .rs485_dir_gpio = GPIO_UART4_RS485_DIR, -# if (CONFIG_UART4_RS485_DIR_POLARITY == 0) - .rs485_dir_polarity = false, -# else - .rs485_dir_polarity = true, -# endif -# endif - .lock = SP_UNLOCKED, -}; -#endif - -/* This describes the state of the STM32 UART5 port. */ - -#ifdef CONFIG_STM32_UART5_SERIALDRIVER -static struct up_dev_s g_uart5priv = -{ - .dev = - { -# if CONSOLE_UART == 5 - .isconsole = true, -# endif - .recv = - { - .size = CONFIG_UART5_RXBUFSIZE, - .buffer = g_uart5rxbuffer, - }, - .xmit = - { - .size = CONFIG_UART5_TXBUFSIZE, - .buffer = g_uart5txbuffer, - }, -# if defined(CONFIG_UART5_RXDMA) && defined(CONFIG_UART5_TXDMA) - .ops = &g_uart_rxtxdma_ops, -# elif defined(CONFIG_UART5_RXDMA) && !defined(CONFIG_UART5_TXDMA) - .ops = &g_uart_rxdma_ops, -# elif !defined(CONFIG_UART5_RXDMA) && defined(CONFIG_UART5_TXDMA) - .ops = &g_uart_txdma_ops, -# else - .ops = &g_uart_ops, -# endif - .priv = &g_uart5priv, - }, - - .islpuart = false, - .irq = STM32_IRQ_UART5, - .parity = CONFIG_UART5_PARITY, - .bits = CONFIG_UART5_BITS, - .stopbits2 = CONFIG_UART5_2STOP, -# if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_UART5_OFLOWCONTROL) - .oflow = true, - .cts_gpio = GPIO_UART5_CTS, -# endif -# if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_UART5_IFLOWCONTROL) - .iflow = true, - .rts_gpio = GPIO_UART5_RTS, -# endif - .baud = CONFIG_UART5_BAUD, - .apbclock = STM32_PCLK1_FREQUENCY, - .usartbase = STM32_UART5_BASE, - .tx_gpio = GPIO_UART5_TX, - .rx_gpio = GPIO_UART5_RX, -# ifdef CONFIG_UART5_TXDMA - .txdma_channel = DMAMAP_UART5_TX, -# endif -# ifdef CONFIG_UART5_RXDMA - .rxdma_channel = DMAMAP_UART5_RX, - .rxfifo = g_uart5rxfifo, -# endif - -# ifdef CONFIG_UART5_RS485 - .rs485_dir_gpio = GPIO_UART5_RS485_DIR, -# if (CONFIG_UART5_RS485_DIR_POLARITY == 0) - .rs485_dir_polarity = false, -# else - .rs485_dir_polarity = true, -# endif -# endif - .lock = SP_UNLOCKED, -}; -#endif - -/* This describes the state of the STM32 USART6 port. */ - -#ifdef CONFIG_STM32_USART6_SERIALDRIVER -static struct up_dev_s g_usart6priv = -{ - .dev = - { -# if CONSOLE_UART == 6 - .isconsole = true, -# endif - .recv = - { - .size = CONFIG_USART6_RXBUFSIZE, - .buffer = g_usart6rxbuffer, - }, - .xmit = - { - .size = CONFIG_USART6_TXBUFSIZE, - .buffer = g_usart6txbuffer, - }, -# if defined(CONFIG_USART6_RXDMA) && defined(CONFIG_USART6_TXDMA) - .ops = &g_uart_rxtxdma_ops, -# elif defined(CONFIG_USART6_RXDMA) && !defined(CONFIG_USART6_TXDMA) - .ops = &g_uart_rxdma_ops, -# elif !defined(CONFIG_USART6_RXDMA) && defined(CONFIG_USART6_TXDMA) - .ops = &g_uart_txdma_ops, -# else - .ops = &g_uart_ops, -# endif - .priv = &g_usart6priv, - }, - - .islpuart = false, - .irq = STM32_IRQ_USART6, - .parity = CONFIG_USART6_PARITY, - .bits = CONFIG_USART6_BITS, - .stopbits2 = CONFIG_USART6_2STOP, - .baud = CONFIG_USART6_BAUD, - .apbclock = STM32_PCLK2_FREQUENCY, - .usartbase = STM32_USART6_BASE, - .tx_gpio = GPIO_USART6_TX, - .rx_gpio = GPIO_USART6_RX, -# if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_USART6_OFLOWCONTROL) - .oflow = true, - .cts_gpio = GPIO_USART6_CTS, -# endif -# if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_USART6_IFLOWCONTROL) - .iflow = true, - .rts_gpio = GPIO_USART6_RTS, -# endif -# ifdef CONFIG_USART6_TXDMA - .txdma_channel = DMAMAP_USART6_TX, -# endif -# ifdef CONFIG_USART6_RXDMA - .rxdma_channel = DMAMAP_USART6_RX, - .rxfifo = g_usart6rxfifo, -# endif - -# ifdef CONFIG_USART6_RS485 - .rs485_dir_gpio = GPIO_USART6_RS485_DIR, -# if (CONFIG_USART6_RS485_DIR_POLARITY == 0) - .rs485_dir_polarity = false, -# else - .rs485_dir_polarity = true, -# endif -# endif - .lock = SP_UNLOCKED, -}; -#endif - -/* This describes the state of the STM32 UART7 port. */ - -#ifdef CONFIG_STM32_UART7_SERIALDRIVER -static struct up_dev_s g_uart7priv = -{ - .dev = - { -# if CONSOLE_UART == 7 - .isconsole = true, -# endif - .recv = - { - .size = CONFIG_UART7_RXBUFSIZE, - .buffer = g_uart7rxbuffer, - }, - .xmit = - { - .size = CONFIG_UART7_TXBUFSIZE, - .buffer = g_uart7txbuffer, - }, -# if defined(CONFIG_UART7_RXDMA) && defined(CONFIG_UART7_TXDMA) - .ops = &g_uart_rxtxdma_ops, -# elif defined(CONFIG_UART7_RXDMA) && !defined(CONFIG_UART7_TXDMA) - .ops = &g_uart_rxdma_ops, -# elif !defined(CONFIG_UART7_RXDMA) && defined(CONFIG_UART7_TXDMA) - .ops = &g_uart_txdma_ops, -# else - .ops = &g_uart_ops, -# endif - .priv = &g_uart7priv, - }, - - .islpuart = false, - .irq = STM32_IRQ_UART7, - .parity = CONFIG_UART7_PARITY, - .bits = CONFIG_UART7_BITS, - .stopbits2 = CONFIG_UART7_2STOP, - .baud = CONFIG_UART7_BAUD, - .apbclock = STM32_PCLK1_FREQUENCY, - .usartbase = STM32_UART7_BASE, - .tx_gpio = GPIO_UART7_TX, - .rx_gpio = GPIO_UART7_RX, -# if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_UART7_OFLOWCONTROL) - .oflow = true, - .cts_gpio = GPIO_UART7_CTS, -# endif -# if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_UART7_IFLOWCONTROL) - .iflow = true, - .rts_gpio = GPIO_UART7_RTS, -# endif -# ifdef CONFIG_UART7_TXDMA - .txdma_channel = DMAMAP_UART7_TX, -# endif -# ifdef CONFIG_UART7_RXDMA - .rxdma_channel = DMAMAP_UART7_RX, - .rxfifo = g_uart7rxfifo, -# endif - -# ifdef CONFIG_UART7_RS485 - .rs485_dir_gpio = GPIO_UART7_RS485_DIR, -# if (CONFIG_UART7_RS485_DIR_POLARITY == 0) - .rs485_dir_polarity = false, -# else - .rs485_dir_polarity = true, -# endif -# endif - .lock = SP_UNLOCKED, -}; -#endif - -/* This describes the state of the STM32 UART8 port. */ - -#ifdef CONFIG_STM32_UART8_SERIALDRIVER -static struct up_dev_s g_uart8priv = -{ - .dev = - { -# if CONSOLE_UART == 8 - .isconsole = true, -# endif - .recv = - { - .size = CONFIG_UART8_RXBUFSIZE, - .buffer = g_uart8rxbuffer, - }, - .xmit = - { - .size = CONFIG_UART8_TXBUFSIZE, - .buffer = g_uart8txbuffer, - }, -# if defined(CONFIG_UART8_RXDMA) && defined(CONFIG_UART8_TXDMA) - .ops = &g_uart_rxtxdma_ops, -# elif defined(CONFIG_UART8_RXDMA) && !defined(CONFIG_UART8_TXDMA) - .ops = &g_uart_rxdma_ops, -# elif !defined(CONFIG_UART8_RXDMA) && defined(CONFIG_UART8_TXDMA) - .ops = &g_uart_txdma_ops, -# else - .ops = &g_uart_ops, -# endif - .priv = &g_uart8priv, - }, - - .islpuart = false, - .irq = STM32_IRQ_UART8, - .parity = CONFIG_UART8_PARITY, - .bits = CONFIG_UART8_BITS, - .stopbits2 = CONFIG_UART8_2STOP, - .baud = CONFIG_UART8_BAUD, - .apbclock = STM32_PCLK1_FREQUENCY, - .usartbase = STM32_UART8_BASE, - .tx_gpio = GPIO_UART8_TX, - .rx_gpio = GPIO_UART8_RX, -# if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_UART8_OFLOWCONTROL) - .oflow = true, - .cts_gpio = GPIO_UART8_CTS, -# endif -# if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_UART8_IFLOWCONTROL) - .iflow = true, - .rts_gpio = GPIO_UART8_RTS, -# endif -# ifdef CONFIG_UART8_TXDMA - .txdma_channel = DMAMAP_UART8_TX, -# endif -# ifdef CONFIG_UART8_RXDMA - .rxdma_channel = DMAMAP_UART8_RX, - .rxfifo = g_uart8rxfifo, -# endif - -# ifdef CONFIG_UART8_RS485 - .rs485_dir_gpio = GPIO_UART8_RS485_DIR, -# if (CONFIG_UART8_RS485_DIR_POLARITY == 0) - .rs485_dir_polarity = false, -# else - .rs485_dir_polarity = true, -# endif -# endif - .lock = SP_UNLOCKED, -}; -#endif - -/* This describes the state of the STM32 LPUART1 ports. */ -#ifdef CONFIG_STM32_LPUART1_SERIALDRIVER -static struct up_dev_s g_lpuart1priv = -{ - .dev = - { -# if CONSOLE_LPUART == 1 - .isconsole = true, -# endif - .recv = - { - .size = CONFIG_LPUART1_RXBUFSIZE, - .buffer = g_lpuart1rxbuffer, - }, - .xmit = - { - .size = CONFIG_LPUART1_TXBUFSIZE, - .buffer = g_lpuart1txbuffer, - }, -# if defined(CONFIG_LPUART1_RXDMA) && defined(CONFIG_LPUART1_TXDMA) - .ops = &g_uart_rxtxdma_ops, -# elif defined(CONFIG_LPUART1_RXDMA) && !defined(CONFIG_LPUART1_TXDMA) - .ops = &g_uart_rxdma_ops, -# elif !defined(CONFIG_LPUART1_RXDMA) && defined(CONFIG_LPUART1_TXDMA) - .ops = &g_uart_txdma_ops, -# else - .ops = &g_uart_ops, -# endif - .priv = &g_lpuart1priv, - }, - - .islpuart = true, - .irq = STM32_IRQ_LPUART, - .parity = CONFIG_LPUART1_PARITY, - .bits = CONFIG_LPUART1_BITS, - .stopbits2 = CONFIG_LPUART1_2STOP, - .baud = CONFIG_LPUART1_BAUD, - .apbclock = STM32_PCLK2_FREQUENCY, - .usartbase = STM32_LPUART1_BASE, - .tx_gpio = GPIO_LPUART1_TX, - .rx_gpio = GPIO_LPUART1_RX, -# if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_LPUART1_OFLOWCONTROL) - .oflow = true, - .cts_gpio = GPIO_LPUART1_CTS, -# endif -# if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART1_IFLOWCONTROL) - .iflow = true, - .rts_gpio = GPIO_LPUART1_RTS, -# endif -# ifdef CONFIG_LPUART1_TXDMA - .txdma_channel = DMAMAP_LPUART1_TX, -# endif -# ifdef CONFIG_LPUART1_RXDMA - .rxdma_channel = DMAMAP_LPUART1_RX, - .rxfifo = g_lpuart1rxfifo, -# endif - -# ifdef CONFIG_LPUART1_RS485 - .rs485_dir_gpio = GPIO_LPUART1_RS485_DIR, -# if (CONFIG_USART1_RS485_DIR_POLARITY == 0) - .rs485_dir_polarity = false, -# else - .rs485_dir_polarity = true, -# endif -# endif - .lock = SP_UNLOCKED, -}; -#endif - -/* This table lets us iterate over the configured USARTs */ - -static struct up_dev_s * const g_uart_devs[STM32_NUSART] = -{ -#ifdef CONFIG_STM32_USART1_SERIALDRIVER - [0] = &g_usart1priv, -#endif -#ifdef CONFIG_STM32_USART2_SERIALDRIVER - [1] = &g_usart2priv, -#endif -#ifdef CONFIG_STM32_USART3_SERIALDRIVER - [2] = &g_usart3priv, -#endif -#ifdef CONFIG_STM32_UART4_SERIALDRIVER - [3] = &g_uart4priv, -#endif -#ifdef CONFIG_STM32_UART5_SERIALDRIVER - [4] = &g_uart5priv, -#endif -#ifdef CONFIG_STM32_USART6_SERIALDRIVER - [5] = &g_usart6priv, -#endif -#ifdef CONFIG_STM32_UART7_SERIALDRIVER - [6] = &g_uart7priv, -#endif -#ifdef CONFIG_STM32_UART8_SERIALDRIVER - [7] = &g_uart8priv, -#endif -}; - -/* This table lets us iterate over the configured LPUARTs */ - -static struct up_dev_s * const g_lpuart_devs[STM32_NLPUART] = -{ -#ifdef CONFIG_STM32_LPUART1_SERIALDRIVER - [0] = &g_lpuart1priv, -#endif -}; - -#ifdef CONFIG_PM -static struct pm_callback_s g_serialcb = -{ - .notify = up_pm_notify, - .prepare = up_pm_prepare, -}; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: up_serialin - ****************************************************************************/ - -static inline uint32_t up_serialin(struct up_dev_s *priv, int offset) -{ - return getreg32(priv->usartbase + offset); -} - -/**************************************************************************** - * Name: up_serialout - ****************************************************************************/ - -static inline void up_serialout(struct up_dev_s *priv, int offset, - uint32_t value) -{ - putreg32(value, priv->usartbase + offset); -} - -/**************************************************************************** - * Name: up_setusartint - ****************************************************************************/ - -static inline void up_setusartint(struct up_dev_s *priv, uint16_t ie) -{ - uint32_t cr; - - /* Save the interrupt mask */ - - priv->ie = ie; - - /* And restore the interrupt state (see the interrupt enable/usage - * table above) - */ - - cr = up_serialin(priv, STM32_USART_CR1_OFFSET); - cr &= ~(USART_CR1_USED_INTS); - cr |= (ie & (USART_CR1_USED_INTS)); - up_serialout(priv, STM32_USART_CR1_OFFSET, cr); - - cr = up_serialin(priv, STM32_USART_CR3_OFFSET); - cr &= ~USART_CR3_EIE; - cr |= (ie & USART_CR3_EIE); - up_serialout(priv, STM32_USART_CR3_OFFSET, cr); -} - -/**************************************************************************** - * Name: up_restoreusartint - ****************************************************************************/ - -static void up_restoreusartint(struct up_dev_s *priv, uint16_t ie) -{ - irqstate_t flags; - - flags = spin_lock_irqsave(&priv->lock); - - up_setusartint(priv, ie); - - spin_unlock_irqrestore(&priv->lock, flags); -} - -/**************************************************************************** - * Name: up_disableusartint - ****************************************************************************/ - -static void up_disableusartint(struct up_dev_s *priv, uint16_t *ie) -{ - irqstate_t flags; - - flags = spin_lock_irqsave(&priv->lock); - - if (ie) - { - uint32_t cr1; - uint32_t cr3; - - /* USART interrupts: - * - * Enable Status Meaning Usage - * ------------------ --------------- ---------------------- ---------- - * USART_CR1_IDLEIE USART_SR_IDLE Idle Line Detected (not used) - * USART_CR1_RXNEIE USART_SR_RXNE Rx Data Ready - * " " USART_SR_ORE Overrun Error Detected - * USART_CR1_TCIE USART_SR_TC Transmission Complete (RS-485) - * USART_CR1_TXEIE USART_SR_TXE Tx Data Register Empty - * USART_CR1_PEIE USART_SR_PE Parity Error - * - * USART_CR2_LBDIE USART_SR_LBD Break Flag - * USART_CR3_EIE USART_SR_FE Framing Error - * " " USART_SR_NE Noise Error - * " " USART_SR_ORE Overrun Error Detected - * USART_CR3_CTSIE USART_SR_CTS CTS flag (not used) - */ - - cr1 = up_serialin(priv, STM32_USART_CR1_OFFSET); - cr3 = up_serialin(priv, STM32_USART_CR3_OFFSET); - - /* Return the current interrupt mask value for the used interrupts. - * Notice that this depends on the fact that none of the used interrupt - * enable bits overlap. This logic would fail if we needed the break - * interrupt! - */ - - *ie = (cr1 & (USART_CR1_USED_INTS)) | (cr3 & USART_CR3_EIE); - } - - /* Disable all interrupts */ - - up_setusartint(priv, 0); - - spin_unlock_irqrestore(&priv->lock, flags); -} - -/**************************************************************************** - * Name: up_dma_nextrx - * - * Description: - * Returns the index into the RX FIFO where the DMA will place the next - * byte that it receives. - * - ****************************************************************************/ - -#ifdef SERIAL_HAVE_RXDMA -static int up_dma_nextrx(struct up_dev_s *priv) -{ - size_t dmaresidual; - - dmaresidual = stm32_dmaresidual(priv->rxdma); - - return (RXDMA_BUFFER_SIZE - (int)dmaresidual); -} -#endif - -/**************************************************************************** - * Name: up_set_format - * - * Description: - * Set the serial line format and speed. - * - ****************************************************************************/ - -#ifndef CONFIG_SUPPRESS_UART_CONFIG -static void up_set_format(struct uart_dev_s *dev) -{ - struct up_dev_s *priv = (struct up_dev_s *)dev->priv; -#if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) || \ - defined(CONFIG_STM32_STM32F37XX) || defined(CONFIG_STM32_STM32G4XXX) - uint32_t usartdiv8; -#else - uint32_t usartdiv32; - uint32_t mantissa; - uint32_t fraction; -#endif - uint32_t regval; - uint32_t brr; - - /* Load CR1 */ - - regval = up_serialin(priv, STM32_USART_CR1_OFFSET); - -#if defined(CONFIG_STM32_STM32G4XXX) - regval &= ~(USART_CR1_UE | USART_CR1_TE | USART_CR1_RE); - up_serialout(priv, STM32_USART_CR1_OFFSET, regval); -#endif -#if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX)|| \ - defined(CONFIG_STM32_STM32F37XX) || defined(CONFIG_STM32_STM32G4XXX) - -#ifdef CONFIG_STM32_LPUART1 - if (priv->islpuart == true) - { - /* LPUART BRR (19:00) = (256*apbclock_hz/baud_rate) */ - - uint32_t apbclock_whole = priv->apbclock; - uint32_t clock_baud_ratio = apbclock_whole / priv->baud; - uint32_t presc_reg = 0x0; - - /* LPUART PRESC (3:0) - * Divide the apbclock if necessary for low baud rates - * 3 * baud_rate <= apbclock_whole <= 4096 * baud_rate - */ - - if (clock_baud_ratio <= 4096) - { - presc_reg = 0x0; - } - else if (clock_baud_ratio > 4096 && clock_baud_ratio <= 8192) - { - presc_reg = 0x1; - apbclock_whole >>= 1; - } - else if (clock_baud_ratio > 8192 && clock_baud_ratio <= 16384) - { - presc_reg = 0x2; - apbclock_whole >>= 2; - } - else if (clock_baud_ratio > 16384 && clock_baud_ratio <= 24576) - { - presc_reg = 0x3; - apbclock_whole /= 6; - } - else if (clock_baud_ratio > 24576 && clock_baud_ratio <= 32768) - { - presc_reg = 0x4; - apbclock_whole >>= 3; - } - else if (clock_baud_ratio > 32768 && clock_baud_ratio <= 40960) - { - presc_reg = 0x5; - apbclock_whole /= 10; - } - else if (clock_baud_ratio > 40960 && clock_baud_ratio <= 49152) - { - presc_reg = 0x6; - apbclock_whole /= 12; - } - else if (clock_baud_ratio > 32768 && clock_baud_ratio <= 65536) - { - presc_reg = 0x7; - apbclock_whole >>= 4; - } - else if (clock_baud_ratio > 65536 && clock_baud_ratio <= 131072) - { - presc_reg = 0x8; - apbclock_whole >>= 5; - } - else if (clock_baud_ratio > 131072 && clock_baud_ratio <= 262144) - { - presc_reg = 0x9; - apbclock_whole >>= 6; - } - else if (clock_baud_ratio > 262144 && clock_baud_ratio <= 524288) - { - presc_reg = 0xa; - apbclock_whole >>= 7; - } - else - { - presc_reg = 0xb; - apbclock_whole >>= 8; - } - - /* Write the PRESC register */ - - up_serialout(priv, STM32_USART_PRESC_OFFSET, presc_reg); - - /* Set the LPUART BRR value after setting Prescaler - * BRR = ( (256 * apbclock_whole) + baud_rate / 2 ) / baud_rate - */ - - brr = (((uint64_t)apbclock_whole << 8) + (priv->baud >> 1)) / \ - priv->baud; - } - else -#endif /* CONFIG_STM32_LPUART1 */ - { - /* This first implementation is for U[S]ARTs that support oversampling - * by 8 in additional to the standard oversampling by 16. - * With baud rate of fCK / Divider for oversampling by 16. - * and baud rate of 2 * fCK / Divider for oversampling by 8 - * - * In case of oversampling by 8, the equation is: - * - * baud = 2 * fCK / usartdiv8 - * usartdiv8 = 2 * fCK / baud - */ - - usartdiv8 = ((priv->apbclock << 1) + (priv->baud >> 1)) / priv->baud; - - /* Baud rate for standard USART (SPI mode included): - * - * In case of oversampling by 16, the equation is: - * baud = fCK / usartdiv16 - * usartdiv16 = fCK / baud - * = 2 * usartdiv8 - * - * Use oversamply by 8 only if the divisor is small. But what is small? - */ - - if (usartdiv8 > 100) - { - /* Use usartdiv16 */ - - brr = (usartdiv8 + 1) >> 1; - - /* Clear oversampling by 8 to enable oversampling by 16 */ - - regval &= ~USART_CR1_OVER8; - } - else - { - DEBUGASSERT(usartdiv8 >= 8); - - /* Perform mysterious operations on bits 0-3 */ - - brr = ((usartdiv8 & 0xfff0) | ((usartdiv8 & 0x000f) >> 1)); - - /* Set oversampling by 8 */ - - regval |= USART_CR1_OVER8; - } - } -#else - /* This second implementation is for U[S]ARTs that support fractional - * dividers. - * - * Configure the USART Baud Rate. The baud rate for the receiver and - * transmitter (Rx and Tx) are both set to the same value as programmed - * in the Mantissa and Fraction values of USARTDIV. - * - * baud = fCK / (16 * usartdiv) - * usartdiv = fCK / (16 * baud) - * - * Where fCK is the input clock to the peripheral (PCLK1 for USART2, 3, - * 4, 5 or PCLK2 for USART1) - * - * First calculate (NOTE: all standard baud values are even so dividing by - * two does not lose precision): - * - * usartdiv32 = 32 * usartdiv = fCK / (baud/2) - */ - - usartdiv32 = priv->apbclock / (priv->baud >> 1); - - /* The mantissa part is then */ - - mantissa = usartdiv32 >> 5; - - /* The fractional remainder (with rounding) */ - - fraction = (usartdiv32 - (mantissa << 5) + 1) >> 1; - -#if defined(CONFIG_STM32_STM32F4XXX) - /* The F4 supports 8 X in oversampling additional to the - * standard oversampling by 16. - * - * With baud rate of fCK / (16 * Divider) for oversampling by 16. - * and baud rate of fCK / (8 * Divider) for oversampling by 8 - */ - - /* Check if 8x oversampling is necessary */ - - if (mantissa == 0) - { - regval |= USART_CR1_OVER8; - - /* Rescale the mantissa */ - - mantissa = usartdiv32 >> 4; - - /* The fractional remainder (with rounding) */ - - fraction = (usartdiv32 - (mantissa << 4) + 1) >> 1; - } - else - { - /* Use 16x Oversampling */ - - regval &= ~USART_CR1_OVER8; - } -#endif - - brr = mantissa << USART_BRR_MANT_SHIFT; - brr |= fraction << USART_BRR_FRAC_SHIFT; -#endif - - up_serialout(priv, STM32_USART_CR1_OFFSET, regval); - up_serialout(priv, STM32_USART_BRR_OFFSET, brr); - - /* Configure parity mode */ - - regval &= ~(USART_CR1_PCE | USART_CR1_PS | USART_CR1_M); - - if (priv->parity == 1) /* Odd parity */ - { - regval |= (USART_CR1_PCE | USART_CR1_PS); - } - else if (priv->parity == 2) /* Even parity */ - { - regval |= USART_CR1_PCE; - } - - /* Configure word length (parity uses one of configured bits) - * - * Default: 1 start, 8 data (no parity), n stop, OR - * 1 start, 7 data + parity, n stop - */ - - if (priv->bits == 9 || (priv->bits == 8 && priv->parity != 0)) - { - /* Select: 1 start, 8 data + parity, n stop, OR - * 1 start, 9 data (no parity), n stop. - */ - - regval |= USART_CR1_M; - } - - up_serialout(priv, STM32_USART_CR1_OFFSET, regval); - - /* Configure STOP bits */ - - regval = up_serialin(priv, STM32_USART_CR2_OFFSET); - regval &= ~(USART_CR2_STOP_MASK); - - if (priv->stopbits2) - { - regval |= USART_CR2_STOP2; - } - - up_serialout(priv, STM32_USART_CR2_OFFSET, regval); - - /* Configure hardware flow control */ - - regval = up_serialin(priv, STM32_USART_CR3_OFFSET); - regval &= ~(USART_CR3_CTSE | USART_CR3_RTSE); - -#if defined(CONFIG_SERIAL_IFLOWCONTROL) && \ - !defined(CONFIG_STM32_FLOWCONTROL_BROKEN) - if (priv->iflow && (priv->rts_gpio != 0)) - { - regval |= USART_CR3_RTSE; - } -#endif - -#ifdef CONFIG_SERIAL_OFLOWCONTROL - if (priv->oflow && (priv->cts_gpio != 0)) - { - regval |= USART_CR3_CTSE; - } -#endif - - up_serialout(priv, STM32_USART_CR3_OFFSET, regval); -#if defined(CONFIG_STM32_STM32G4XXX) - regval = up_serialin(priv, STM32_USART_CR1_OFFSET); - regval |= (USART_CR1_UE | USART_CR1_TE | USART_CR1_RE); - up_serialout(priv, STM32_USART_CR1_OFFSET, regval); -#endif -} -#endif /* CONFIG_SUPPRESS_UART_CONFIG */ - -/**************************************************************************** - * Name: up_set_apb_clock - * - * Description: - * Enable or disable APB clock for the USART peripheral - * - * Input Parameters: - * dev - A reference to the UART driver state structure - * on - Enable clock if 'on' is 'true' and disable if 'false' - * - ****************************************************************************/ - -static void up_set_apb_clock(struct uart_dev_s *dev, bool on) -{ - struct up_dev_s *priv = (struct up_dev_s *)dev->priv; - uint32_t rcc_en; - uint32_t regaddr; - - /* Determine which USART to configure */ - - switch (priv->usartbase) - { - default: - return; -#ifdef CONFIG_STM32_USART1_SERIALDRIVER - case STM32_USART1_BASE: - rcc_en = RCC_APB2ENR_USART1EN; - regaddr = STM32_RCC_APB2ENR; - break; -#endif -#ifdef CONFIG_STM32_USART2_SERIALDRIVER - case STM32_USART2_BASE: - rcc_en = RCC_APB1ENR_USART2EN; - regaddr = STM32_RCC_APB1ENR; - break; -#endif -#ifdef CONFIG_STM32_USART3_SERIALDRIVER - case STM32_USART3_BASE: - rcc_en = RCC_APB1ENR_USART3EN; - regaddr = STM32_RCC_APB1ENR; - break; -#endif -#ifdef CONFIG_STM32_UART4_SERIALDRIVER - case STM32_UART4_BASE: - rcc_en = RCC_APB1ENR_UART4EN; - regaddr = STM32_RCC_APB1ENR; - break; -#endif -#ifdef CONFIG_STM32_UART5_SERIALDRIVER - case STM32_UART5_BASE: - rcc_en = RCC_APB1ENR_UART5EN; - regaddr = STM32_RCC_APB1ENR; - break; -#endif -#ifdef CONFIG_STM32_USART6_SERIALDRIVER - case STM32_USART6_BASE: - rcc_en = RCC_APB2ENR_USART6EN; - regaddr = STM32_RCC_APB2ENR; - break; -#endif -#ifdef CONFIG_STM32_UART7_SERIALDRIVER - case STM32_UART7_BASE: - rcc_en = RCC_APB1ENR_UART7EN; - regaddr = STM32_RCC_APB1ENR; - break; -#endif -#ifdef CONFIG_STM32_UART8_SERIALDRIVER - case STM32_UART8_BASE: - rcc_en = RCC_APB1ENR_UART8EN; - regaddr = STM32_RCC_APB1ENR; - break; -#endif -#ifdef CONFIG_STM32_LPUART1_SERIALDRIVER - case STM32_LPUART1_BASE: - rcc_en = RCC_APB1ENR2_LPUART1EN; - regaddr = STM32_RCC_APB1ENR2; - break; -#endif - } - - /* Enable/disable APB 1/2 clock for USART */ - - if (on) - { - modifyreg32(regaddr, 0, rcc_en); - } - else - { - modifyreg32(regaddr, rcc_en, 0); - } -} - -/**************************************************************************** - * Name: up_setup - * - * Description: - * Configure the USART baud, bits, parity, etc. This method is called the - * first time that the serial port is opened. - * - ****************************************************************************/ - -static int up_setup(struct uart_dev_s *dev) -{ - struct up_dev_s *priv = (struct up_dev_s *)dev->priv; - -#ifndef CONFIG_SUPPRESS_UART_CONFIG - uint32_t regval; - - /* Note: The logic here depends on the fact that that the USART module - * was enabled in stm32_lowsetup(). - */ - - /* Enable USART APB1/2 clock */ - - up_set_apb_clock(dev, true); - - /* Configure pins for USART use */ - - if (priv->tx_gpio != 0) - { - stm32_configgpio(priv->tx_gpio); - } - - if (priv->rx_gpio != 0) - { - stm32_configgpio(priv->rx_gpio); - } - -#ifdef CONFIG_SERIAL_OFLOWCONTROL - if (priv->cts_gpio != 0) - { - stm32_configgpio(priv->cts_gpio); - } -#endif - -#ifdef CONFIG_SERIAL_IFLOWCONTROL - if (priv->rts_gpio != 0) - { - uint32_t config = priv->rts_gpio; - -#ifdef CONFIG_STM32_FLOWCONTROL_BROKEN - /* Instead of letting hw manage this pin, we will bitbang */ - - config = (config & ~GPIO_MODE_MASK) | GPIO_OUTPUT; -#endif - stm32_configgpio(config); - } -#endif - -#ifdef HAVE_RS485 - if (priv->rs485_dir_gpio != 0) - { - stm32_configgpio(priv->rs485_dir_gpio); - stm32_gpiowrite(priv->rs485_dir_gpio, !priv->rs485_dir_polarity); - } -#endif - - /* Configure CR2 - * Clear STOP, CLKEN, CPOL, CPHA, LBCL, and interrupt enable bits - */ - - regval = up_serialin(priv, STM32_USART_CR2_OFFSET); - if (priv->islpuart == true) - { - regval &= ~(USART_CR2_STOP_MASK | USART_CR2_CLKEN); - } - else - { - regval &= ~(USART_CR2_STOP_MASK | USART_CR2_CLKEN | USART_CR2_CPOL | - USART_CR2_CPHA | USART_CR2_LBCL | USART_CR2_LBDIE); - } - - /* Configure STOP bits */ - - if (priv->stopbits2) - { - regval |= USART_CR2_STOP2; - } - - up_serialout(priv, STM32_USART_CR2_OFFSET, regval); - - /* Configure CR1 - * Clear TE, REm and all interrupt enable bits - */ - - regval = up_serialin(priv, STM32_USART_CR1_OFFSET); - -#ifdef CONFIG_STM32_LPUART1 - if (priv->islpuart == true) - { - regval &= ~(USART_CR1_TE | USART_CR1_RE | LPUART_CR1_ALLINTS); - } - else -#endif - { - regval &= ~(USART_CR1_TE | USART_CR1_RE | USART_CR1_ALLINTS); - } - - up_serialout(priv, STM32_USART_CR1_OFFSET, regval); - - /* Configure CR3 - * Clear CTSE, RTSE, and all interrupt enable bits - */ - - regval = up_serialin(priv, STM32_USART_CR3_OFFSET); - regval &= ~(USART_CR3_CTSIE | USART_CR3_CTSE | USART_CR3_RTSE | - USART_CR3_EIE); - - up_serialout(priv, STM32_USART_CR3_OFFSET, regval); - - /* Configure the USART line format and speed. */ - - up_set_format(dev); - - /* Enable Rx, Tx, and the USART */ - - regval = up_serialin(priv, STM32_USART_CR1_OFFSET); - regval |= (USART_CR1_UE | USART_CR1_TE | USART_CR1_RE); - up_serialout(priv, STM32_USART_CR1_OFFSET, regval); - -#endif /* CONFIG_SUPPRESS_UART_CONFIG */ - - /* Set up the cached interrupt enables value */ - - priv->ie = 0; - - /* Mark device as initialized. */ - - priv->initialized = true; - - return OK; -} - -/**************************************************************************** - * Name: up_dma_setup - * - * Description: - * Configure the USART baud, bits, parity, etc. This method is called the - * first time that the serial port is opened. - * - ****************************************************************************/ - -#if defined(SERIAL_HAVE_RXDMA) || defined(SERIAL_HAVE_TXDMA) -static int up_dma_setup(struct uart_dev_s *dev) -{ - struct up_dev_s *priv = (struct up_dev_s *)dev->priv; - int result; - - /* Do the basic UART setup first, unless we are the console */ - - if (!dev->isconsole) - { - result = up_setup(dev); - if (result != OK) - { - return result; - } - } - -#if defined(SERIAL_HAVE_TXDMA) - /* Acquire the Tx DMA channel. This should always succeed. */ - - if (priv->txdma_channel != INVALID_SERIAL_DMA_CHANNEL) - { - priv->txdma = stm32_dmachannel(priv->txdma_channel); - - /* Enable receive Tx DMA for the UART */ - - modifyreg32(priv->usartbase + STM32_USART_CR3_OFFSET, - 0, USART_CR3_DMAT); - } -#endif - -#if defined(SERIAL_HAVE_RXDMA) - /* Acquire the DMA channel. This should always succeed. */ - - if (priv->rxdma_channel != INVALID_SERIAL_DMA_CHANNEL) - { - priv->rxdma = stm32_dmachannel(priv->rxdma_channel); - - /* Configure for circular DMA reception into the RX fifo */ - - stm32_dmasetup(priv->rxdma, - priv->usartbase + STM32_USART_RDR_OFFSET, - (uint32_t)priv->rxfifo, - RXDMA_BUFFER_SIZE, - SERIAL_RXDMA_CONTROL_WORD); - - /* Reset our DMA shadow pointer to match the address just - * programmed above. - */ - - priv->rxdmanext = 0; - - /* Enable receive Rx DMA for the UART */ - - modifyreg32(priv->usartbase + STM32_USART_CR3_OFFSET, - 0, USART_CR3_DMAR); - - /* Start the DMA channel, and arrange for callbacks at the half and - * full points in the FIFO. This ensures that we have half a FIFO - * worth of time to claim bytes before they are overwritten. - */ - - stm32_dmastart(priv->rxdma, up_dma_rxcallback, (void *)priv, true); - } -#endif - - return OK; -} -#endif - -/**************************************************************************** - * Name: up_shutdown - * - * Description: - * Disable the USART. This method is called when the serial - * port is closed - * - ****************************************************************************/ - -static void up_shutdown(struct uart_dev_s *dev) -{ - struct up_dev_s *priv = (struct up_dev_s *)dev->priv; - uint32_t regval; - - /* Mark device as uninitialized. */ - - priv->initialized = false; - - /* Disable all interrupts */ - - up_disableusartint(priv, NULL); - - /* Disable USART APB1/2 clock */ - - up_set_apb_clock(dev, false); - - /* Disable Rx, Tx, and the UART */ - - regval = up_serialin(priv, STM32_USART_CR1_OFFSET); - regval &= ~(USART_CR1_UE | USART_CR1_TE | USART_CR1_RE); - up_serialout(priv, STM32_USART_CR1_OFFSET, regval); - - /* Release pins. "If the serial-attached device is powered down, the TX - * pin causes back-powering, potentially confusing the device to the point - * of complete lock-up." - * - * REVISIT: Is unconfiguring the pins appropriate for all device? If not, - * then this may need to be a configuration option. - */ - - if (priv->tx_gpio != 0) - { - stm32_unconfiggpio(priv->tx_gpio); - } - - if (priv->rx_gpio != 0) - { - stm32_unconfiggpio(priv->rx_gpio); - } - -#ifdef CONFIG_SERIAL_OFLOWCONTROL - if (priv->cts_gpio != 0) - { - stm32_unconfiggpio(priv->cts_gpio); - } -#endif - -#ifdef CONFIG_SERIAL_IFLOWCONTROL - if (priv->rts_gpio != 0) - { - stm32_unconfiggpio(priv->rts_gpio); - } -#endif - -#ifdef HAVE_RS485 - if (priv->rs485_dir_gpio != 0) - { - stm32_unconfiggpio(priv->rs485_dir_gpio); - } -#endif -} - -/**************************************************************************** - * Name: up_dma_shutdown - * - * Description: - * Disable the USART. This method is called when the serial - * port is closed - * - ****************************************************************************/ - -#if defined(SERIAL_HAVE_RXDMA) || defined(SERIAL_HAVE_TXDMA) -static void up_dma_shutdown(struct uart_dev_s *dev) -{ - struct up_dev_s *priv = (struct up_dev_s *)dev->priv; - - /* Perform the normal UART shutdown */ - - up_shutdown(dev); - -#if defined(SERIAL_HAVE_RXDMA) - /* Stop the RX DMA channel */ - - if (priv->rxdma_channel != INVALID_SERIAL_DMA_CHANNEL) - { - stm32_dmastop(priv->rxdma); - - /* Release the RX DMA channel */ - - stm32_dmafree(priv->rxdma); - priv->rxdma = NULL; - } -#endif - -#if defined(SERIAL_HAVE_TXDMA) - /* Stop the TX DMA channel */ - - if (priv->txdma_channel != INVALID_SERIAL_DMA_CHANNEL) - { - stm32_dmastop(priv->txdma); - - /* Release the TX DMA channel */ - - stm32_dmafree(priv->txdma); - priv->txdma = NULL; - } -#endif -} -#endif - -/**************************************************************************** - * Name: up_attach - * - * Description: - * Configure the USART to operation in interrupt driven mode. This method - * is called when the serial port is opened. Normally, this is just after - * the setup() method is called, however, the serial console may operate - * in a non-interrupt driven mode during the boot phase. - * - * RX and TX interrupts are not enabled when by the attach method (unless - * the hardware supports multiple levels of interrupt enabling). The RX - * and TX interrupts are not enabled until the txint() and rxint() methods - * are called. - * - ****************************************************************************/ - -static int up_attach(struct uart_dev_s *dev) -{ - struct up_dev_s *priv = (struct up_dev_s *)dev->priv; - int ret; - - /* Attach and enable the IRQ */ - - ret = irq_attach(priv->irq, up_interrupt, priv); - if (ret == OK) - { - /* Enable the interrupt (RX and TX interrupts are still disabled - * in the USART - */ - - up_enable_irq(priv->irq); - } - - return ret; -} - -/**************************************************************************** - * Name: up_detach - * - * Description: - * Detach USART interrupts. This method is called when the serial port is - * closed normally just before the shutdown method is called. The - * exception is the serial console which is never shutdown. - * - ****************************************************************************/ - -static void up_detach(struct uart_dev_s *dev) -{ - struct up_dev_s *priv = (struct up_dev_s *)dev->priv; - up_disable_irq(priv->irq); - irq_detach(priv->irq); -} - -/**************************************************************************** - * Name: up_interrupt - * - * Description: - * This is the UART interrupt handler. It will be invoked when an - * interrupt is received on the 'irq'. It should call uart_xmitchars or - * uart_recvchars to perform the appropriate data transfers. The - * interrupt handling logic must be able to map the 'arg' to the - * appropriate uart_dev_s structure in order to call these functions. - * - ****************************************************************************/ - -static int up_interrupt(int irq, void *context, void *arg) -{ - struct up_dev_s *priv = (struct up_dev_s *)arg; - int passes; - bool handled; - - DEBUGASSERT(priv != NULL); - - /* Report serial activity to the power management logic */ - -#if defined(CONFIG_PM) && CONFIG_STM32_PM_SERIAL_ACTIVITY > 0 - pm_activity(PM_IDLE_DOMAIN, CONFIG_STM32_PM_SERIAL_ACTIVITY); -#endif - - /* Loop until there are no characters to be transferred or, - * until we have been looping for a long time. - */ - - handled = true; - for (passes = 0; passes < 256 && handled; passes++) - { - handled = false; - - /* Get the masked USART status word. */ - - priv->sr = up_serialin(priv, STM32_USART_SR_OFFSET); - - /* USART interrupts: - * - * Enable Status Meaning Usage - * ------------------ --------------- ---------------------- ---------- - * USART_CR1_IDLEIE USART_SR_IDLE Idle Line Detected (not used) - * USART_CR1_RXNEIE USART_SR_RXNE Rx Data Ready - * " " USART_SR_ORE Overrun Error Detected - * USART_CR1_TCIE USART_SR_TC Tx Complete (RS-485) - * USART_CR1_TXEIE USART_SR_TXE Tx Data Register Empty - * USART_CR1_PEIE USART_SR_PE Parity Error - * - * USART_CR2_LBDIE USART_SR_LBD Break Flag - * USART_CR3_EIE USART_SR_FE Framing Error - * " " USART_SR_NE Noise Error - * " " USART_SR_ORE Overrun Error Detected - * USART_CR3_CTSIE USART_SR_CTS CTS flag (not used) - * - * NOTE: Some of these status bits must be cleared by explicitly - * writing zero to the SR register: USART_SR_CTS, USART_SR_LBD. Note of - * those are currently being used. - */ - - /* Error report */ - -#ifdef CONFIG_SERIAL_TIOCGICOUNT - if (priv->sr & USART_SR_FE) - { - priv->icount.frame++; - } - - if (priv->sr & USART_SR_ORE) - { - priv->icount.overrun++; - } - - if (priv->sr & USART_SR_PE) - { - priv->icount.parity++; - } - - if (priv->sr & USART_SR_LBD) - { - priv->icount.brk++; - } -#endif - -#ifdef HAVE_RS485 - /* Transmission of whole buffer is over - TC is set, TXEIE is cleared. - * Note - this should be first, to have the most recent TC bit value - * from SR register - sending data affects TC, but without refresh we - * will not know that... - */ - - if (((priv->sr & USART_SR_TC) != 0) && - ((priv->ie & USART_CR1_TCIE) != 0) && - ((priv->ie & USART_CR1_TXEIE) == 0)) - { - stm32_gpiowrite(priv->rs485_dir_gpio, !priv->rs485_dir_polarity); - up_restoreusartint(priv, priv->ie & ~USART_CR1_TCIE); - } -#endif - - /* Handle incoming, receive bytes. */ - - if (((priv->sr & USART_SR_RXNE) != 0) && - ((priv->ie & USART_CR1_RXNEIE) != 0)) - { - /* Received data ready... process incoming bytes. NOTE the check - * for RXNEIE: We cannot call uart_recvchards of RX interrupts are - * disabled. - */ - - uart_recvchars(&priv->dev); - handled = true; - } - - /* We may still have to read from the DR register to clear any pending - * error conditions. - */ - - else if ((priv->sr & (USART_SR_ORE | USART_SR_NE | USART_SR_FE | - USART_SR_LBD)) != 0) - { -#if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) || \ - defined(CONFIG_STM32_STM32F37XX) || defined(CONFIG_STM32_STM32G4XXX) - /* These errors are cleared by writing the corresponding bit to the - * interrupt clear register (ICR). - */ - - up_serialout(priv, STM32_USART_ICR_OFFSET, - (USART_ICR_NCF | USART_ICR_ORECF | USART_ICR_FECF | - USART_ICR_LBDCF)); -#else - /* If an error occurs, read from DR to clear the error (data has - * been lost). If ORE is set along with RXNE then it tells you - * that the byte *after* the one in the data register has been - * lost, but the data register value is correct. That case will - * be handled above if interrupts are enabled. Otherwise, that - * good byte will be lost. - */ - - up_serialin(priv, STM32_USART_RDR_OFFSET); -#endif - } - - /* Handle outgoing, transmit bytes */ - - if (((priv->sr & USART_SR_TXE) != 0) && - ((priv->ie & USART_CR1_TXEIE) != 0)) - { - /* Transmit data register empty ... process outgoing bytes */ - - uart_xmitchars(&priv->dev); - handled = true; - } - } - - return OK; -} - -/**************************************************************************** - * Name: up_ioctl - * - * Description: - * All ioctl calls will be routed through this method - * - ****************************************************************************/ - -static int up_ioctl(struct file *filep, int cmd, unsigned long arg) -{ -#if defined(CONFIG_SERIAL_TERMIOS) || defined(CONFIG_SERIAL_TIOCSERGSTRUCT) \ - || defined(CONFIG_SERIAL_TIOCGICOUNT) \ - || defined(CONFIG_STM32_SERIALBRK_BSDCOMPAT) \ - || defined(CONFIG_STM32_USART_SINGLEWIRE) - struct inode *inode = filep->f_inode; - struct uart_dev_s *dev = inode->i_private; -#endif -#if defined(CONFIG_SERIAL_TERMIOS) \ - || defined(CONFIG_SERIAL_TIOCGICOUNT) \ - || defined(CONFIG_STM32_SERIALBRK_BSDCOMPAT) \ - || defined(CONFIG_STM32_USART_SINGLEWIRE) - struct up_dev_s *priv = (struct up_dev_s *)dev->priv; -#endif - int ret = OK; - - switch (cmd) - { -#ifdef CONFIG_SERIAL_TIOCSERGSTRUCT - case TIOCSERGSTRUCT: - { - struct up_dev_s *user = (struct up_dev_s *)arg; - if (!user) - { - ret = -EINVAL; - } - else - { - memcpy(user, dev, sizeof(struct up_dev_s)); - } - } - break; -#endif - -#ifdef CONFIG_SERIAL_TIOCGICOUNT - /* Get U(S)ART error counters */ - - case TIOCGICOUNT: - { - struct serial_icounter_s *icount = (struct serial_icounter_s *)arg; - if (icount == NULL) - { - ret = -EINVAL; - } - else - { - memcpy(icount, &priv->icount, sizeof(struct serial_icounter_s)); - } - } - break; -#endif - -#ifdef CONFIG_STM32_USART_SINGLEWIRE - case TIOCSSINGLEWIRE: - { - /* Change the TX port to be open-drain/push-pull and enable/disable - * half-duplex mode. - */ - - uint32_t cr = up_serialin(priv, STM32_USART_CR3_OFFSET); - -#if defined(CONFIG_STM32_STM32F10XX) - if ((arg & SER_SINGLEWIRE_ENABLED) != 0) - { - if (priv->tx_gpio != 0) - { - stm32_configgpio((priv->tx_gpio & ~(GPIO_CNF_MASK)) | - GPIO_CNF_AFOD); - } - - cr |= USART_CR3_HDSEL; - } - else - { - if (priv->tx_gpio != 0) - { - stm32_configgpio((priv->tx_gpio & ~(GPIO_CNF_MASK)) | - GPIO_CNF_AFPP); - } - - cr &= ~USART_CR3_HDSEL; - } -#else - if ((arg & SER_SINGLEWIRE_ENABLED) != 0) - { - uint32_t gpio_val = (arg & SER_SINGLEWIRE_PUSHPULL) == - SER_SINGLEWIRE_PUSHPULL ? - GPIO_PUSHPULL : GPIO_OPENDRAIN; - gpio_val |= ((arg & SER_SINGLEWIRE_PULL_MASK) == - SER_SINGLEWIRE_PULLUP) ? GPIO_PULLUP - : GPIO_FLOAT; - gpio_val |= ((arg & SER_SINGLEWIRE_PULL_MASK) == - SER_SINGLEWIRE_PULLDOWN) ? GPIO_PULLDOWN - : GPIO_FLOAT; - if (priv->tx_gpio != 0) - { - stm32_configgpio((priv->tx_gpio & ~(GPIO_PUPD_MASK | - GPIO_OPENDRAIN)) | - gpio_val); - } - - cr |= USART_CR3_HDSEL; - } - else - { - if (priv->tx_gpio != 0) - { - stm32_configgpio((priv->tx_gpio & ~(GPIO_PUPD_MASK | - GPIO_OPENDRAIN)) | - GPIO_PUSHPULL); - } - - cr &= ~USART_CR3_HDSEL; - } -#endif - - up_serialout(priv, STM32_USART_CR3_OFFSET, cr); - } - break; -#endif - -#ifdef CONFIG_SERIAL_TERMIOS - case TCGETS: - { - struct termios *termiosp = (struct termios *)arg; - - if (!termiosp) - { - ret = -EINVAL; - break; - } - - /* Note that since we only support 8/9 bit modes and - * there is no way to report 9-bit mode, we always claim 8. - */ - - termiosp->c_cflag = - ((priv->parity != 0) ? PARENB : 0) | - ((priv->parity == 1) ? PARODD : 0) | - ((priv->stopbits2) ? CSTOPB : 0) | -#ifdef CONFIG_SERIAL_OFLOWCONTROL - ((priv->oflow) ? CCTS_OFLOW : 0) | -#endif -#ifdef CONFIG_SERIAL_IFLOWCONTROL - ((priv->iflow) ? CRTS_IFLOW : 0) | -#endif - CS8; - - cfsetispeed(termiosp, priv->baud); - - /* TODO: CRTS_IFLOW, CCTS_OFLOW */ - } - break; - - case TCSETS: - { - struct termios *termiosp = (struct termios *)arg; - - if (!termiosp) - { - ret = -EINVAL; - break; - } - - /* Perform some sanity checks before accepting any changes */ - - if (((termiosp->c_cflag & CSIZE) != CS8) -#ifdef CONFIG_SERIAL_OFLOWCONTROL - || ((termiosp->c_cflag & CCTS_OFLOW) && (priv->cts_gpio == 0)) -#endif -#ifdef CONFIG_SERIAL_IFLOWCONTROL - || ((termiosp->c_cflag & CRTS_IFLOW) && (priv->rts_gpio == 0)) -#endif - ) - { - ret = -EINVAL; - break; - } - - if (termiosp->c_cflag & PARENB) - { - priv->parity = (termiosp->c_cflag & PARODD) ? 1 : 2; - } - else - { - priv->parity = 0; - } - - priv->stopbits2 = (termiosp->c_cflag & CSTOPB) != 0; -#ifdef CONFIG_SERIAL_OFLOWCONTROL - priv->oflow = (termiosp->c_cflag & CCTS_OFLOW) != 0; -#endif -#ifdef CONFIG_SERIAL_IFLOWCONTROL - priv->iflow = (termiosp->c_cflag & CRTS_IFLOW) != 0; -#endif - - /* Note that since there is no way to request 9-bit mode - * and no way to support 5/6/7-bit modes, we ignore them - * all here. - */ - - /* Note that only cfgetispeed is used because we have knowledge - * that only one speed is supported. - */ - - priv->baud = cfgetispeed(termiosp); - - /* Effect the changes immediately - note that we do not implement - * TCSADRAIN / TCSAFLUSH - */ - - up_set_format(dev); - } - break; -#endif /* CONFIG_SERIAL_TERMIOS */ - -#ifdef CONFIG_STM32_USART_BREAKS -# ifdef CONFIG_STM32_SERIALBRK_BSDCOMPAT - case TIOCSBRK: /* BSD compatibility: Turn break on, unconditionally */ - { - irqstate_t flags; - - flags = enter_critical_section(); - - /* Disable any further tx activity */ - - priv->ie |= USART_CR1_IE_BREAK_INPROGRESS; - - up_txint(dev, false); - - /* Configure TX as a GPIO output pin and Send a break signal */ - - if (priv->tx_gpio != 0) - { - uint32_t tx_break = GPIO_OUTPUT | - (~(GPIO_MODE_MASK | GPIO_OUTPUT_SET) & - priv->tx_gpio); - stm32_configgpio(tx_break); - } - - leave_critical_section(flags); - } - break; - - case TIOCCBRK: /* BSD compatibility: Turn break off, unconditionally */ - { - irqstate_t flags; - - flags = enter_critical_section(); - - /* Configure TX back to U(S)ART */ - - if (priv->tx_gpio != 0) - { - stm32_configgpio(priv->tx_gpio); - } - - priv->ie &= ~USART_CR1_IE_BREAK_INPROGRESS; - - /* Enable further tx activity */ - - up_txint(dev, true); - - leave_critical_section(flags); - } - break; -# else - case TIOCSBRK: /* No BSD compatibility: Turn break on for M bit times */ - { - uint32_t cr1; - irqstate_t flags; - - flags = enter_critical_section(); - cr1 = up_serialin(priv, STM32_USART_CR1_OFFSET); - up_serialout(priv, STM32_USART_CR1_OFFSET, cr1 | USART_CR1_SBK); - leave_critical_section(flags); - } - break; - - case TIOCCBRK: /* No BSD compatibility: May turn off break too soon */ - { - uint32_t cr1; - irqstate_t flags; - - flags = enter_critical_section(); - cr1 = up_serialin(priv, STM32_USART_CR1_OFFSET); - up_serialout(priv, STM32_USART_CR1_OFFSET, cr1 & ~USART_CR1_SBK); - leave_critical_section(flags); - } - break; -# endif -#endif - - default: - ret = -ENOTTY; - break; - } - - return ret; -} - -/**************************************************************************** - * Name: up_receive - * - * Description: - * Called (usually) from the interrupt level to receive one - * character from the USART. Error bits associated with the - * receipt are provided in the return 'status'. - * - ****************************************************************************/ - -#if defined(SERIAL_HAVE_TXDMA_OPS) || defined(SERIAL_HAVE_NODMA_OPS) -static int up_receive(struct uart_dev_s *dev, unsigned int *status) -{ - struct up_dev_s *priv = (struct up_dev_s *)dev->priv; - uint32_t rdr; - - /* Get the Rx byte */ - - rdr = up_serialin(priv, STM32_USART_RDR_OFFSET); - - /* Get the Rx byte plux error information. Return those in status */ - - *status = priv->sr << 16 | rdr; - priv->sr = 0; - - /* Then return the actual received byte */ - - return rdr & 0xff; -} -#endif - -/**************************************************************************** - * Name: up_rxint - * - * Description: - * Call to enable or disable RX interrupts - * - ****************************************************************************/ - -#if defined(SERIAL_HAVE_TXDMA_OPS) || defined(SERIAL_HAVE_NODMA_OPS) -static void up_rxint(struct uart_dev_s *dev, bool enable) -{ - struct up_dev_s *priv = (struct up_dev_s *)dev->priv; - irqstate_t flags; - uint16_t ie; - - /* USART receive interrupts: - * - * Enable Status Meaning Usage - * ------------------ --------------- ------------------------- ---------- - * USART_CR1_IDLEIE USART_SR_IDLE Idle Line Detected (not used) - * USART_CR1_RXNEIE USART_SR_RXNE Rx Data Ready to be Read - * " " USART_SR_ORE Overrun Error Detected - * USART_CR1_PEIE USART_SR_PE Parity Error - * - * USART_CR2_LBDIE USART_SR_LBD Break Flag - * USART_CR3_EIE USART_SR_FE Framing Error - * " " USART_SR_NE Noise Error - * " " USART_SR_ORE Overrun Error Detected - */ - - flags = enter_critical_section(); - ie = priv->ie; - if (enable) - { - /* Receive an interrupt when their is anything in the Rx data register - * (or an Rx timeout occurs). - */ - -#ifndef CONFIG_SUPPRESS_SERIAL_INTS -#ifdef CONFIG_USART_ERRINTS - ie |= (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR3_EIE); -#else - ie |= USART_CR1_RXNEIE; -#endif -#endif - } - else - { - ie &= ~(USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR3_EIE); - } - - /* Then set the new interrupt state */ - - up_restoreusartint(priv, ie); - leave_critical_section(flags); -} -#endif - -/**************************************************************************** - * Name: up_rxavailable - * - * Description: - * Return true if the receive register is not empty - * - ****************************************************************************/ - -#if defined(SERIAL_HAVE_TXDMA_OPS) || defined(SERIAL_HAVE_NODMA_OPS) -static bool up_rxavailable(struct uart_dev_s *dev) -{ - struct up_dev_s *priv = (struct up_dev_s *)dev->priv; - return ((up_serialin(priv, STM32_USART_SR_OFFSET) & USART_SR_RXNE) != 0); -} -#endif - -/**************************************************************************** - * Name: up_rxflowcontrol - * - * Description: - * Called when Rx buffer is full (or exceeds configured watermark levels - * if CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS is defined). - * Return true if UART activated RX flow control to block more incoming - * data - * - * Input Parameters: - * dev - UART device instance - * nbuffered - the number of characters currently buffered - * (if CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS is - * not defined the value will be 0 for an empty buffer or the - * defined buffer size for a full buffer) - * upper - true indicates the upper watermark was crossed where - * false indicates the lower watermark has been crossed - * - * Returned Value: - * true if RX flow control activated. - * - ****************************************************************************/ - -#ifdef CONFIG_SERIAL_IFLOWCONTROL -static bool up_rxflowcontrol(struct uart_dev_s *dev, - unsigned int nbuffered, bool upper) -{ - struct up_dev_s *priv = (struct up_dev_s *)dev->priv; - -#if defined(CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS) && \ - defined(CONFIG_STM32_FLOWCONTROL_BROKEN) - if (priv->iflow && (priv->rts_gpio != 0)) - { - /* Assert/de-assert nRTS set it high resume/stop sending */ - - stm32_gpiowrite(priv->rts_gpio, upper); - - if (upper) - { - /* With heavy Rx traffic, RXNE might be set and data pending. - * Returning 'true' in such case would cause RXNE left unhandled - * and causing interrupt storm. Sending end might be also be slow - * to react on nRTS, and returning 'true' here would prevent - * processing that data. - * - * Therefore, return 'false' so input data is still being processed - * until sending end reacts on nRTS signal and stops sending more. - */ - - return false; - } - - return upper; - } - -#else - if (priv->iflow) - { - /* Is the RX buffer full? */ - - if (upper) - { - /* Disable Rx interrupt to prevent more data being from - * peripheral. When hardware RTS is enabled, this will - * prevent more data from coming in. - * - * This function is only called when UART recv buffer is full, - * that is: "dev->recv.head + 1 == dev->recv.tail". - * - * Logic in "uart_read" will automatically toggle Rx interrupts - * when buffer is read empty and thus we do not have to re- - * enable Rx interrupts. - */ - - uart_disablerxint(dev); - return true; - } - - /* No.. The RX buffer is empty */ - - else - { - /* We might leave Rx interrupt disabled if full recv buffer was - * read empty. Enable Rx interrupt to make sure that more input is - * received. - */ - - uart_enablerxint(dev); - } - } -#endif - - return false; -} -#endif - -/**************************************************************************** - * Name: up_dma_receive - * - * Description: - * Called (usually) from the interrupt level to receive one - * character from the USART. Error bits associated with the - * receipt are provided in the return 'status'. - * - ****************************************************************************/ - -#ifdef SERIAL_HAVE_RXDMA -static int up_dma_receive(struct uart_dev_s *dev, unsigned int *status) -{ - struct up_dev_s *priv = (struct up_dev_s *)dev->priv; - int c = 0; - - if (up_dma_nextrx(priv) != priv->rxdmanext) - { - c = priv->rxfifo[priv->rxdmanext]; - - priv->rxdmanext++; - if (priv->rxdmanext == RXDMA_BUFFER_SIZE) - { - priv->rxdmanext = 0; - } - } - - return c; -} -#endif - -/**************************************************************************** - * Name: up_dma_rxint - * - * Description: - * Call to enable or disable RX interrupts - * - ****************************************************************************/ - -#ifdef SERIAL_HAVE_RXDMA -static void up_dma_rxint(struct uart_dev_s *dev, bool enable) -{ - struct up_dev_s *priv = (struct up_dev_s *)dev->priv; - - /* En/disable DMA reception. - * - * Note that it is not safe to check for available bytes and immediately - * pass them to uart_recvchars as that could potentially recurse back - * to us again. Instead, bytes must wait until the next up_dma_poll or - * DMA event. - */ - - priv->rxenable = enable; -} -#endif - -/**************************************************************************** - * Name: up_dma_rxavailable - * - * Description: - * Return true if the receive register is not empty - * - ****************************************************************************/ - -#ifdef SERIAL_HAVE_RXDMA -static bool up_dma_rxavailable(struct uart_dev_s *dev) -{ - struct up_dev_s *priv = (struct up_dev_s *)dev->priv; - - /* Compare our receive pointer to the current DMA pointer, if they - * do not match, then there are bytes to be received. - */ - - return (up_dma_nextrx(priv) != priv->rxdmanext); -} -#endif - -/**************************************************************************** - * Name: up_dma_txcallback - * - * Description: - * This function clears dma buffer at complete of DMA transfer and wakes up - * threads waiting for space in buffer. - * - ****************************************************************************/ - -#ifdef SERIAL_HAVE_TXDMA -static void up_dma_txcallback(DMA_HANDLE handle, uint8_t status, void *arg) -{ - struct up_dev_s *priv = (struct up_dev_s *)arg; - - /* Update 'nbytes' indicating number of bytes actually transferred by DMA. - * This is important to free TX buffer space by 'uart_xmitchars_done'. - */ - - if (status & DMA_ISR_TCIF_BIT) - { - priv->dev.dmatx.nbytes += priv->dev.dmatx.length; - if (priv->dev.dmatx.nlength) - { - /* Set up DMA on next buffer */ - - stm32_dmasetup(priv->txdma, - priv->usartbase + STM32_USART_TDR_OFFSET, - (uint32_t) priv->dev.dmatx.nbuffer, - (size_t) priv->dev.dmatx.nlength, - SERIAL_TXDMA_CONTROL_WORD); - - /* Set length for the next completion */ - - priv->dev.dmatx.length = priv->dev.dmatx.nlength; - priv->dev.dmatx.nlength = 0; - - /* Start transmission with the callback on DMA completion */ - - stm32_dmastart(priv->txdma, up_dma_txcallback, - (void *)priv, false); - - return; - } - } - else if (status & DMA_ISR_HTIF_BIT) - { - priv->dev.dmatx.nbytes += priv->dev.dmatx.length / 2; - } - - /* Adjust the pointers */ - - uart_xmitchars_done(&priv->dev); -} -#endif - -/**************************************************************************** - * Name: up_dma_txavailable - * - * Description: - * Informs DMA that Tx data is available and is ready for transfer. - * - ****************************************************************************/ - -#ifdef SERIAL_HAVE_TXDMA -static void up_dma_txavailable(struct uart_dev_s *dev) -{ - struct up_dev_s *priv = (struct up_dev_s *)dev->priv; - - /* Only send when the DMA is idle */ - - if (stm32_dmaresidual(priv->txdma) == 0) - { - uart_xmitchars_dma(dev); - } -} -#endif - -/**************************************************************************** - * Name: up_dma_send - * - * Description: - * Called (usually) from the interrupt level to start DMA transfer. - * (Re-)Configures DMA Stream updating buffer and buffer length. - * - ****************************************************************************/ - -#ifdef SERIAL_HAVE_TXDMA -static void up_dma_send(struct uart_dev_s *dev) -{ - struct up_dev_s *priv = (struct up_dev_s *)dev->priv; - - /* We need to stop DMA before reconfiguration */ - - stm32_dmastop(priv->txdma); - - /* Reset the number sent */ - - dev->dmatx.nbytes = 0; - - /* Make use of setup function to update buffer and its length for - * next transfer - */ - - stm32_dmasetup(priv->txdma, - priv->usartbase + STM32_USART_TDR_OFFSET, - (uint32_t) dev->dmatx.buffer, - (size_t) dev->dmatx.length, - SERIAL_TXDMA_CONTROL_WORD); - - /* Start transmission with the callback on DMA completion */ - - stm32_dmastart(priv->txdma, up_dma_txcallback, (void *)priv, false); -} -#endif - -/**************************************************************************** - * Name: up_send - * - * Description: - * This method will send one byte on the USART - * - ****************************************************************************/ - -static void up_send(struct uart_dev_s *dev, int ch) -{ - struct up_dev_s *priv = (struct up_dev_s *)dev->priv; -#ifdef HAVE_RS485 - if (priv->rs485_dir_gpio != 0) - { - stm32_gpiowrite(priv->rs485_dir_gpio, priv->rs485_dir_polarity); - } -#endif - - up_serialout(priv, STM32_USART_TDR_OFFSET, (uint32_t)ch); -} - -/**************************************************************************** - * Name: up_dma_txint - * - * Description: - * Call to enable or disable TX interrupts from the UART. - * - ****************************************************************************/ - -#ifdef SERIAL_HAVE_TXDMA -static void up_dma_txint(struct uart_dev_s *dev, bool enable) -{ - /* Nothing to do. */ - - /* In case of DMA transfer we do not want to make use of UART interrupts. - * Instead, we use DMA interrupts that are activated once during boot - * sequence. Furthermore we can use up_dma_txcallback() to handle staff at - * half DMA transfer or after transfer completion (depending configuration, - * see stm32_dmastart(...) ). - */ -} -#endif - -/**************************************************************************** - * Name: up_txint - * - * Description: - * Call to enable or disable TX interrupts - * - ****************************************************************************/ - -#if defined(SERIAL_HAVE_RXDMA_OPS) || defined(SERIAL_HAVE_NODMA_OPS) || \ - defined(CONFIG_STM32_SERIALBRK_BSDCOMPAT) -static void up_txint(struct uart_dev_s *dev, bool enable) -{ - struct up_dev_s *priv = (struct up_dev_s *)dev->priv; - irqstate_t flags; - - /* USART transmit interrupts: - * - * Enable Status Meaning Usage - * ------------------ --------------- ----------------------- ---------- - * USART_CR1_TCIE USART_SR_TC Tx Complete (RS-485) - * USART_CR1_TXEIE USART_SR_TXE Tx Data Register Empty - * USART_CR3_CTSIE USART_SR_CTS CTS flag (not used) - */ - - flags = enter_critical_section(); - if (enable) - { - /* Set to receive an interrupt when the TX data register is empty */ - -#ifndef CONFIG_SUPPRESS_SERIAL_INTS - uint16_t ie = priv->ie | USART_CR1_TXEIE; - - /* If RS-485 is supported on this U[S]ART, then also enable the - * transmission complete interrupt. - */ - -# ifdef HAVE_RS485 - if (priv->rs485_dir_gpio != 0) - { - ie |= USART_CR1_TCIE; - } -# endif - -# ifdef CONFIG_STM32_SERIALBRK_BSDCOMPAT - if (priv->ie & USART_CR1_IE_BREAK_INPROGRESS) - { - leave_critical_section(flags); - return; - } -# endif - - up_restoreusartint(priv, ie); - -#else - /* Fake a TX interrupt here by just calling uart_xmitchars() with - * interrupts disabled (note this may recurse). - */ - - uart_xmitchars(dev); -#endif - } - else - { - /* Disable the TX interrupt */ - - up_restoreusartint(priv, priv->ie & ~USART_CR1_TXEIE); - } - - leave_critical_section(flags); -} -#endif - -/**************************************************************************** - * Name: up_txready - * - * Description: - * Return true if the transmit data register is empty - * - ****************************************************************************/ - -static bool up_txready(struct uart_dev_s *dev) -{ - struct up_dev_s *priv = (struct up_dev_s *)dev->priv; - return ((up_serialin(priv, STM32_USART_SR_OFFSET) & USART_SR_TXE) != 0); -} - -/**************************************************************************** - * Name: up_dma_rxcallback - * - * Description: - * This function checks the current DMA state and calls the generic - * serial stack when bytes appear to be available. - * - ****************************************************************************/ - -#ifdef SERIAL_HAVE_RXDMA -static void up_dma_rxcallback(DMA_HANDLE handle, uint8_t status, void *arg) -{ - struct up_dev_s *priv = (struct up_dev_s *)arg; - - if (priv->rxenable && up_dma_rxavailable(&priv->dev)) - { - uart_recvchars(&priv->dev); - } -} -#endif - -/**************************************************************************** - * Name: up_pm_notify - * - * Description: - * Notify the driver of new power state. This callback is called after - * all drivers have had the opportunity to prepare for the new power state. - * - * Input Parameters: - * - * cb - Returned to the driver. The driver version of the callback - * structure may include additional, driver-specific state data at - * the end of the structure. - * - * pmstate - Identifies the new PM state - * - * Returned Value: - * None - The driver already agreed to transition to the low power - * consumption state when when it returned OK to the prepare() call. - * - * - ****************************************************************************/ - -#ifdef CONFIG_PM -static void up_pm_notify(struct pm_callback_s *cb, int domain, - enum pm_state_e pmstate) -{ - switch (pmstate) - { - case (PM_NORMAL): - { - /* Logic for PM_NORMAL goes here */ - } - break; - - case (PM_IDLE): - { - /* Logic for PM_IDLE goes here */ - } - break; - - case (PM_STANDBY): - { - /* Logic for PM_STANDBY goes here */ - } - break; - - case (PM_SLEEP): - { - /* Logic for PM_SLEEP goes here */ - } - break; - - default: - { - /* Should not get here */ - } - break; - } -} -#endif - -/**************************************************************************** - * Name: up_pm_prepare - * - * Description: - * Request the driver to prepare for a new power state. This is a warning - * that the system is about to enter into a new power state. The driver - * should begin whatever operations that may be required to enter power - * state. The driver may abort the state change mode by returning a - * non-zero value from the callback function. - * - * Input Parameters: - * - * cb - Returned to the driver. The driver version of the callback - * structure may include additional, driver-specific state data at - * the end of the structure. - * - * pmstate - Identifies the new PM state - * - * Returned Value: - * Zero - (OK) means the event was successfully processed and that the - * driver is prepared for the PM state change. - * - * Non-zero - means that the driver is not prepared to perform the tasks - * needed achieve this power setting and will cause the state - * change to be aborted. NOTE: The prepare() method will also - * be called when reverting from lower back to higher power - * consumption modes (say because another driver refused a - * lower power state change). Drivers are not permitted to - * return non-zero values when reverting back to higher power - * consumption modes! - * - * - ****************************************************************************/ - -#ifdef CONFIG_PM -static int up_pm_prepare(struct pm_callback_s *cb, int domain, - enum pm_state_e pmstate) -{ - /* Logic to prepare for a reduced power state goes here. */ - - return OK; -} -#endif -#endif /* HAVE_SERIALDRIVER */ -#endif /* USE_SERIALDRIVER */ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -#ifdef USE_SERIALDRIVER - -/**************************************************************************** - * Name: stm32_serial_get_uart - * - * Description: - * Get serial driver structure for STM32 USART - * - ****************************************************************************/ - -#ifdef HAVE_SERIALDRIVER -uart_dev_t *stm32_serial_get_uart(int uart_num) -{ - int uart_idx = uart_num - 1; - - if (uart_idx < 0 || uart_idx >= STM32_NUSART || !g_uart_devs[uart_idx]) - { - return NULL; - } - - if (!g_uart_devs[uart_idx]->initialized) - { - return NULL; - } - - return &g_uart_devs[uart_idx]->dev; -} -#endif /* HAVE_SERIALDRIVER */ - -/**************************************************************************** - * Name: arm_earlyserialinit - * - * Description: - * Performs the low level USART initialization early in debug so that the - * serial console will be available during boot up. This must be called - * before arm_serialinit. - * - ****************************************************************************/ - -#ifdef USE_EARLYSERIALINIT -void arm_earlyserialinit(void) -{ -#ifdef HAVE_SERIALDRIVER - unsigned i; - - /* Disable all USART interrupts */ - - for (i = 0; i < STM32_NUSART; i++) - { - if (g_uart_devs[i]) - { - up_disableusartint(g_uart_devs[i], NULL); - } - } - - for (i = 0; i < STM32_NLPUART; i++) - { - if (g_lpuart_devs[i]) - { - up_disableusartint(g_lpuart_devs[i], NULL); - } - } - - /* Configure whichever one is the console */ - -#if CONSOLE_UART > 0 - up_setup(&g_uart_devs[CONSOLE_UART - 1]->dev); -#elif CONSOLE_LPUART > 0 - up_setup(&g_lpuart_devs[CONSOLE_LPUART - 1]->dev); -#endif -#endif /* HAVE_UART */ -} -#endif - -/**************************************************************************** - * Name: arm_serialinit - * - * Description: - * Register serial console and serial ports. This assumes - * that arm_earlyserialinit was called previously. - * - ****************************************************************************/ - -void arm_serialinit(void) -{ -#ifdef HAVE_SERIALDRIVER - char devname[16]; - unsigned i; - unsigned minor = 0; -#ifdef CONFIG_PM - int ret; -#endif - - /* Register to receive power management callbacks */ - -#ifdef CONFIG_PM - ret = pm_register(&g_serialcb); - DEBUGASSERT(ret == OK); - UNUSED(ret); -#endif - - /* Register the console */ - -#if CONSOLE_UART > 0 - struct uart_dev_s *dev = &g_uart_devs[CONSOLE_UART - 1]->dev; -#elif CONSOLE_LPUART > 0 - struct uart_dev_s *dev = &g_lpuart_devs[CONSOLE_LPUART - 1]->dev; -#endif - -#if CONSOLE_UART > 0 || CONSOLE_LPUART > 0 - uart_register("/dev/console", dev); - -#ifndef CONFIG_STM32_SERIAL_DISABLE_REORDERING - /* If not disabled, register the console UART to ttyS0 and exclude - * it from initializing it further down - */ - - uart_register("/dev/ttyS0", dev); - minor = 1; -#endif - -#if defined(SERIAL_HAVE_CONSOLE_RXDMA) || defined(SERIAL_HAVE_CONSOLE_TXDMA) - /* If we need to re-initialise the console to enable DMA do that here. */ - - up_dma_setup(dev); -#endif -#endif /* CONSOLE_UART > 0 || CONSOLE_LPUART > 0 */ - - /* Register all remaining USARTs */ - - strlcpy(devname, "/dev/ttySx", sizeof(devname)); - - for (i = 0; i < STM32_NUSART; i++) - { - /* Don't create a device for non-configured ports. */ - - if (g_uart_devs[i] == 0) - { - continue; - } - -#ifndef CONFIG_STM32_SERIAL_DISABLE_REORDERING - /* Don't create a device for the console - we did that above */ - - if (g_uart_devs[i]->dev.isconsole) - { - continue; - } -#endif - - /* Register USARTs as devices in increasing order */ - - devname[9] = '0' + minor++; - uart_register(devname, &g_uart_devs[i]->dev); - } - - for (i = 0; i < STM32_NLPUART; i++) - { - /* Don't create a device for non-configured ports. */ - - if (g_lpuart_devs[i] == 0) - { - continue; - } - -#ifndef CONFIG_STM32_SERIAL_DISABLE_REORDERING - /* Don't create a device for the console - we did that above */ - - if (g_lpuart_devs[i]->dev.isconsole) - { - continue; - } -#endif - - /* Register USARTs as devices in increasing order */ - - devname[9] = '0' + minor++; - uart_register(devname, &g_lpuart_devs[i]->dev); - } - -#endif /* HAVE UART */ -} - -/**************************************************************************** - * Name: stm32_serial_dma_poll - * - * Description: - * Checks receive DMA buffers for received bytes that have not accumulated - * to the point where the DMA half/full interrupt has triggered. - * - * This function should be called from a timer or other periodic context. - * - ****************************************************************************/ - -#ifdef SERIAL_HAVE_RXDMA -void stm32_serial_dma_poll(void) -{ - irqstate_t flags; - - flags = enter_critical_section(); - -#ifdef CONFIG_USART1_RXDMA - if (g_usart1priv.rxdma != NULL) - { - up_dma_rxcallback(g_usart1priv.rxdma, 0, &g_usart1priv); - } -#endif - -#ifdef CONFIG_USART2_RXDMA - if (g_usart2priv.rxdma != NULL) - { - up_dma_rxcallback(g_usart2priv.rxdma, 0, &g_usart2priv); - } -#endif - -#ifdef CONFIG_USART3_RXDMA - if (g_usart3priv.rxdma != NULL) - { - up_dma_rxcallback(g_usart3priv.rxdma, 0, &g_usart3priv); - } -#endif - -#ifdef CONFIG_UART4_RXDMA - if (g_uart4priv.rxdma != NULL) - { - up_dma_rxcallback(g_uart4priv.rxdma, 0, &g_uart4priv); - } -#endif - -#ifdef CONFIG_UART5_RXDMA - if (g_uart5priv.rxdma != NULL) - { - up_dma_rxcallback(g_uart5priv.rxdma, 0, &g_uart5priv); - } -#endif - -#ifdef CONFIG_USART6_RXDMA - if (g_usart6priv.rxdma != NULL) - { - up_dma_rxcallback(g_usart6priv.rxdma, 0, &g_usart6priv); - } -#endif - -#ifdef CONFIG_UART7_RXDMA - if (g_uart7priv.rxdma != NULL) - { - up_dma_rxcallback(g_uart7priv.rxdma, 0, &g_uart7priv); - } -#endif - -#ifdef CONFIG_UART8_RXDMA - if (g_uart8priv.rxdma != NULL) - { - up_dma_rxcallback(g_uart8priv.rxdma, 0, &g_uart8priv); - } -#endif - -#ifdef CONFIG_LPUART1_RXDMA - if (g_lpuart1priv.rxdma != NULL) - { - up_dma_rxcallback(g_lpuart1priv.rxdma, 0, &g_lpuart1priv); - } -#endif - - leave_critical_section(flags); -} -#endif - -/**************************************************************************** - * Name: up_putc - * - * Description: - * Provide priority, low-level access to support OS debug writes - * - ****************************************************************************/ - -#ifndef CONFIG_ARM_SEMIHOSTING_SYSLOG -void up_putc(int ch) -{ -#if CONSOLE_UART > 0 - struct up_dev_s *priv = g_uart_devs[CONSOLE_UART - 1]; -#elif CONSOLE_LPUART > 0 - struct up_dev_s *priv = g_lpuart_devs[CONSOLE_LPUART - 1]; -#endif - -#if CONSOLE_UART > 0 || CONSOLE_LPUART > 0 - uint16_t ie; - - up_disableusartint(priv, &ie); - arm_lowputc(ch); - up_restoreusartint(priv, ie); -#endif -} -#endif - -#else /* USE_SERIALDRIVER */ - -/**************************************************************************** - * Name: up_putc - * - * Description: - * Provide priority, low-level access to support OS debug writes - * - ****************************************************************************/ - -#ifndef CONFIG_ARM_SEMIHOSTING_SYSLOG -void up_putc(int ch) -{ -#if CONSOLE_UART > 0 || CONSOLE_LPUART > 0 - arm_lowputc(ch); -#endif -} -#endif - -#endif /* USE_SERIALDRIVER */ diff --git a/arch/arm/src/stm32/stm32_spi.c b/arch/arm/src/stm32/stm32_spi.c deleted file mode 100644 index 62b019ce07ed8..0000000000000 --- a/arch/arm/src/stm32/stm32_spi.c +++ /dev/null @@ -1,2395 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_spi.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status must - * be provided by board-specific logic. They are implementations of the - * select and status methods of the SPI interface defined by struct spi_ops_s - * (see include/nuttx/spi/spi.h). - * All other methods (including stm32_spibus_initialize()) are provided by - * common STM32 logic. To use this common SPI logic on your board: - * - * 1. Provide logic in stm32_boardinitialize() to configure SPI chip select - * pins. - * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() functions - * in your board-specific logic. These functions will perform chip - * selection and status operations using GPIOs in the way your board is - * configured. - * 3. Add a calls to stm32_spibus_initialize() in your low level - * application initialization logic - * 4. The handle returned by stm32_spibus_initialize() may then be used to - * bind the SPI driver to higher level logic (e.g., calling - * mmcsd_spislotinitialize(), for example, will bind the SPI driver to - * the SPI MMC/SD driver). - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include - -#include - -#include "arm_internal.h" -#include "chip.h" -#include "stm32.h" -#include "stm32_gpio.h" -#include "stm32_dma.h" -#include "stm32_spi.h" - -#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || \ - defined(CONFIG_STM32_SPI3) || defined(CONFIG_STM32_SPI4) || \ - defined(CONFIG_STM32_SPI5) || defined(CONFIG_STM32_SPI6) - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -/* SPI interrupts */ - -#ifdef CONFIG_STM32_SPI_INTERRUPTS -# error "Interrupt driven SPI not yet supported" -#endif - -/* Can't have both interrupt driven SPI and SPI DMA */ - -#if defined(CONFIG_STM32_SPI_INTERRUPTS) && defined(CONFIG_STM32_SPI_DMA) -# error "Cannot enable both interrupt mode and DMA mode for SPI" -#endif - -/* SPI DMA priority */ - -#ifdef CONFIG_STM32_SPI_DMA - -# if defined(CONFIG_SPI_DMAPRIO) -# define SPI_DMA_PRIO CONFIG_SPI_DMAPRIO -# elif defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32L15XX) || \ - defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32G4XXX) -# define SPI_DMA_PRIO DMA_CCR_PRIMED -# elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) -# define SPI_DMA_PRIO DMA_SCR_PRIMED -# else -# error "Unknown STM32 DMA" -# endif - -# if defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32L15XX) || \ - defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32G4XXX) -# if (SPI_DMA_PRIO & ~DMA_CCR_PL_MASK) != 0 -# error "Illegal value for CONFIG_SPI_DMAPRIO" -# endif -# elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) -# if (SPI_DMA_PRIO & ~DMA_SCR_PL_MASK) != 0 -# error "Illegal value for CONFIG_SPI_DMAPRIO" -# endif -# else -# error "Unknown STM32 DMA" -# endif - -/* DMA channel configuration */ - -#if defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32L15XX) || \ - defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX) || \ - defined(CONFIG_STM32_STM32G4XXX) -# define SPI_RXDMA16_CONFIG (SPI_DMA_PRIO|DMA_CCR_MSIZE_16BITS|DMA_CCR_PSIZE_16BITS|DMA_CCR_MINC ) -# define SPI_RXDMA8_CONFIG (SPI_DMA_PRIO|DMA_CCR_MSIZE_8BITS |DMA_CCR_PSIZE_8BITS |DMA_CCR_MINC ) -# define SPI_RXDMA16NULL_CONFIG (SPI_DMA_PRIO|DMA_CCR_MSIZE_8BITS |DMA_CCR_PSIZE_16BITS ) -# define SPI_RXDMA8NULL_CONFIG (SPI_DMA_PRIO|DMA_CCR_MSIZE_8BITS |DMA_CCR_PSIZE_8BITS ) -# define SPI_TXDMA16_CONFIG (SPI_DMA_PRIO|DMA_CCR_MSIZE_16BITS|DMA_CCR_PSIZE_16BITS|DMA_CCR_MINC|DMA_CCR_DIR) -# define SPI_TXDMA8_CONFIG (SPI_DMA_PRIO|DMA_CCR_MSIZE_8BITS |DMA_CCR_PSIZE_8BITS |DMA_CCR_MINC|DMA_CCR_DIR) -# define SPI_TXDMA16NULL_CONFIG (SPI_DMA_PRIO|DMA_CCR_MSIZE_8BITS |DMA_CCR_PSIZE_16BITS |DMA_CCR_DIR) -# define SPI_TXDMA8NULL_CONFIG (SPI_DMA_PRIO|DMA_CCR_MSIZE_8BITS |DMA_CCR_PSIZE_8BITS |DMA_CCR_DIR) -#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) -# define SPI_RXDMA16_CONFIG (SPI_DMA_PRIO|DMA_SCR_MSIZE_16BITS|DMA_SCR_PSIZE_16BITS|DMA_SCR_MINC|DMA_SCR_DIR_P2M) -# define SPI_RXDMA8_CONFIG (SPI_DMA_PRIO|DMA_SCR_MSIZE_8BITS |DMA_SCR_PSIZE_8BITS |DMA_SCR_MINC|DMA_SCR_DIR_P2M) -# define SPI_RXDMA16NULL_CONFIG (SPI_DMA_PRIO|DMA_SCR_MSIZE_8BITS |DMA_SCR_PSIZE_16BITS |DMA_SCR_DIR_P2M) -# define SPI_RXDMA8NULL_CONFIG (SPI_DMA_PRIO|DMA_SCR_MSIZE_8BITS |DMA_SCR_PSIZE_8BITS |DMA_SCR_DIR_P2M) -# define SPI_TXDMA16_CONFIG (SPI_DMA_PRIO|DMA_SCR_MSIZE_16BITS|DMA_SCR_PSIZE_16BITS|DMA_SCR_MINC|DMA_SCR_DIR_M2P) -# define SPI_TXDMA8_CONFIG (SPI_DMA_PRIO|DMA_SCR_MSIZE_8BITS |DMA_SCR_PSIZE_8BITS |DMA_SCR_MINC|DMA_SCR_DIR_M2P) -# define SPI_TXDMA16NULL_CONFIG (SPI_DMA_PRIO|DMA_SCR_MSIZE_8BITS |DMA_SCR_PSIZE_16BITS |DMA_SCR_DIR_M2P) -# define SPI_TXDMA8NULL_CONFIG (SPI_DMA_PRIO|DMA_SCR_MSIZE_8BITS |DMA_SCR_PSIZE_8BITS |DMA_SCR_DIR_M2P) -#else -# error "Unknown STM32 DMA" -#endif - -/* Maximum number of data items per single DMA descriptor. - * - * Both the STM32 DMA IPv1 (CNDTR on F0/F1/F3/G4/L0/L1/L4) and IPv2 (SxNDTR - * on F2/F4/F7/H7) transfer-count registers are 16 bits wide, so each call - * to stm32_dmasetup() can program at most 65535 transfers. spi_exchange() - * below chunks larger requests to stay within this limit; without it a - * single SPI_EXCHANGE() of >= 64 KiB silently programs NDTR to 0 (low 16 - * bits of nwords) and the driver blocks forever waiting on a DMA-complete - * IRQ that never fires. - */ - -# define STM32_SPI_DMA_MAX_XFER 65535u - -# define SPIDMA_BUFFER_MASK (4 - 1) -# define SPIDMA_SIZE(b) (((b) + SPIDMA_BUFFER_MASK) & ~SPIDMA_BUFFER_MASK) -# define SPIDMA_BUF_ALIGN aligned_data(4) - -# if defined(CONFIG_STM32_SPI1_DMA_BUFFER) && \ - CONFIG_STM32_SPI1_DMA_BUFFER > 0 -# define SPI1_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32_SPI1_DMA_BUFFER) -# define SPI1_DMABUFSIZE_ALGN SPIDMA_BUF_ALIGN -# endif - -# if defined(CONFIG_STM32_SPI2_DMA_BUFFER) && \ - CONFIG_STM32_SPI2_DMA_BUFFER > 0 -# define SPI2_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32_SPI2_DMA_BUFFER) -# define SPI2_DMABUFSIZE_ALGN SPIDMA_BUF_ALIGN -# endif - -# if defined(CONFIG_STM32_SPI3_DMA_BUFFER) && \ - CONFIG_STM32_SPI3_DMA_BUFFER > 0 -# define SPI3_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32_SPI3_DMA_BUFFER) -# define SPI3_DMABUFSIZE_ALGN SPIDMA_BUF_ALIGN -# endif - -# if defined(CONFIG_STM32_SPI4_DMA_BUFFER) && \ - CONFIG_STM32_SPI4_DMA_BUFFER > 0 -# define SPI4_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32_SPI4_DMA_BUFFER) -# define SPI4_DMABUFSIZE_ALGN SPIDMA_BUF_ALIGN -# endif - -# if defined(CONFIG_STM32_SPI5_DMA_BUFFER) && \ - CONFIG_STM32_SPI5_DMA_BUFFER > 0 -# define SPI5_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32_SPI5_DMA_BUFFER) -# define SPI5_DMABUFSIZE_ALGN SPIDMA_BUF_ALIGN -# endif - -# if defined(CONFIG_STM32_SPI6_DMA_BUFFER) && \ - CONFIG_STM32_SPI6_DMA_BUFFER > 0 -# define SPI6_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32_SPI6_DMA_BUFFER) -# define SPI6_DMABUFSIZE_ALGN SPIDMA_BUF_ALIGN -# endif - -#endif - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -struct stm32_spidev_s -{ - struct spi_dev_s spidev; /* Externally visible part of the SPI interface */ - uint32_t spibase; /* SPIn base address */ - uint32_t spiclock; /* Clocking for the SPI module */ -#ifdef CONFIG_STM32_SPI_INTERRUPTS - uint8_t spiirq; /* SPI IRQ number */ -#endif -#ifdef CONFIG_STM32_SPI_DMA - volatile uint8_t rxresult; /* Result of the RX DMA */ - volatile uint8_t txresult; /* Result of the RX DMA */ -#ifdef CONFIG_SPI_TRIGGER - bool defertrig; /* Flag indicating that trigger should be deferred */ - bool trigarmed; /* Flag indicating that the trigger is armed */ -#endif - uint8_t rxch; /* The RX DMA channel number */ - uint8_t txch; /* The TX DMA channel number */ - uint8_t *rxbuf; /* The RX DMA buffer */ - uint8_t *txbuf; /* The TX DMA buffer */ - size_t buflen; /* The DMA buffer length */ - DMA_HANDLE rxdma; /* DMA channel handle for RX transfers */ - DMA_HANDLE txdma; /* DMA channel handle for TX transfers */ - sem_t rxsem; /* Wait for RX DMA to complete */ - sem_t txsem; /* Wait for TX DMA to complete */ - uint32_t txccr; /* DMA control register for TX transfers */ - uint32_t rxccr; /* DMA control register for RX transfers */ -#endif - bool initialized; /* Has SPI interface been initialized */ - mutex_t lock; /* Held while chip is selected for mutual exclusion */ - uint32_t frequency; /* Requested clock frequency */ - uint32_t actual; /* Actual clock frequency */ - uint8_t nbits; /* Width of word in bits (4 through 16) */ - uint8_t mode; /* Mode 0,1,2,3 */ -}; - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -/* Helpers */ - -static inline uint16_t spi_getreg(struct stm32_spidev_s *priv, - uint8_t offset); -#if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX) -static inline uint8_t spi_getreg8(struct stm32_spidev_s *priv, - uint8_t offset); -#endif -static inline void spi_putreg(struct stm32_spidev_s *priv, - uint8_t offset, - uint16_t value); -#if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX) -static inline void spi_putreg8(struct stm32_spidev_s *priv, - uint8_t offset, - uint8_t value); -#endif -static inline uint16_t spi_readword(struct stm32_spidev_s *priv); -static inline void spi_writeword(struct stm32_spidev_s *priv, - uint16_t byte); - -/* DMA support */ - -#ifdef CONFIG_STM32_SPI_DMA -static int spi_dmarxwait(struct stm32_spidev_s *priv); -static int spi_dmatxwait(struct stm32_spidev_s *priv); -static inline void spi_dmarxwakeup(struct stm32_spidev_s *priv); -static inline void spi_dmatxwakeup(struct stm32_spidev_s *priv); -static void spi_dmarxcallback(DMA_HANDLE handle, uint8_t isr, - void *arg); -static void spi_dmatxcallback(DMA_HANDLE handle, uint8_t isr, - void *arg); -static void spi_dmarxsetup(struct stm32_spidev_s *priv, - void *rxbuffer, - void *rxdummy, - size_t nwords); -static void spi_dmatxsetup(struct stm32_spidev_s *priv, - const void *txbuffer, - const void *txdummy, - size_t nwords); -static inline void spi_dmarxstart(struct stm32_spidev_s *priv); -static inline void spi_dmatxstart(struct stm32_spidev_s *priv); -#endif - -/* SPI methods */ - -static int spi_lock(struct spi_dev_s *dev, bool lock); -static uint32_t spi_setfrequency(struct spi_dev_s *dev, - uint32_t frequency); -static void spi_setmode(struct spi_dev_s *dev, - enum spi_mode_e mode); -static void spi_setbits(struct spi_dev_s *dev, int nbits); -#ifdef CONFIG_SPI_HWFEATURES -static int spi_hwfeatures(struct spi_dev_s *dev, - spi_hwfeatures_t features); -#endif -static uint32_t spi_send(struct spi_dev_s *dev, uint32_t wd); -static void spi_exchange(struct spi_dev_s *dev, - const void *txbuffer, - void *rxbuffer, size_t nwords); -#ifdef CONFIG_SPI_TRIGGER -static int spi_trigger(struct spi_dev_s *dev); -#endif -#ifndef CONFIG_SPI_EXCHANGE -static void spi_sndblock(struct spi_dev_s *dev, - const void *txbuffer, - size_t nwords); -static void spi_recvblock(struct spi_dev_s *dev, - void *rxbuffer, - size_t nwords); -#endif - -/* Initialization */ - -static void spi_bus_initialize(struct stm32_spidev_s *priv); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -#ifdef CONFIG_STM32_SPI1 -static const struct spi_ops_s g_sp1iops = -{ - .lock = spi_lock, - .select = stm32_spi1select, - .setfrequency = spi_setfrequency, - .setmode = spi_setmode, - .setbits = spi_setbits, -#ifdef CONFIG_SPI_HWFEATURES - .hwfeatures = spi_hwfeatures, -#endif - .status = stm32_spi1status, -#ifdef CONFIG_SPI_CMDDATA - .cmddata = stm32_spi1cmddata, -#endif - .send = spi_send, -#ifdef CONFIG_SPI_EXCHANGE - .exchange = spi_exchange, -#else - .sndblock = spi_sndblock, - .recvblock = spi_recvblock, -#endif -#ifdef CONFIG_SPI_TRIGGER - .trigger = spi_trigger, -#endif -#ifdef CONFIG_SPI_CALLBACK - .registercallback = stm32_spi1register, /* Provided externally */ -#else - .registercallback = 0, /* Not implemented */ -#endif -}; - -#if defined(SPI1_DMABUFSIZE_ADJUSTED) -static uint8_t g_spi1_txbuf[SPI1_DMABUFSIZE_ADJUSTED] SPI1_DMABUFSIZE_ALGN; -static uint8_t g_spi1_rxbuf[SPI1_DMABUFSIZE_ADJUSTED] SPI1_DMABUFSIZE_ALGN; -#endif - -static struct stm32_spidev_s g_spi1dev = -{ - .spidev = - { - .ops = &g_sp1iops - }, - .spibase = STM32_SPI1_BASE, - .spiclock = STM32_PCLK2_FREQUENCY, -#ifdef CONFIG_STM32_SPI_INTERRUPTS - .spiirq = STM32_IRQ_SPI1, -#endif -#ifdef CONFIG_STM32_SPI_DMA -# ifdef CONFIG_STM32_SPI1_DMA - .rxch = DMACHAN_SPI1_RX, - .txch = DMACHAN_SPI1_TX, -# ifdef SPI1_DMABUFSIZE_ADJUSTED - .rxbuf = g_spi1_rxbuf, - .txbuf = g_spi1_txbuf, - .buflen = SPI1_DMABUFSIZE_ADJUSTED, -# endif -# else - .rxch = 0, - .txch = 0, -# endif - .rxsem = SEM_INITIALIZER(0), - .txsem = SEM_INITIALIZER(0), -#endif - .lock = NXMUTEX_INITIALIZER, -}; -#endif - -#ifdef CONFIG_STM32_SPI2 -static const struct spi_ops_s g_sp2iops = -{ - .lock = spi_lock, - .select = stm32_spi2select, - .setfrequency = spi_setfrequency, - .setmode = spi_setmode, - .setbits = spi_setbits, -#ifdef CONFIG_SPI_HWFEATURES - .hwfeatures = spi_hwfeatures, -#endif - .status = stm32_spi2status, -#ifdef CONFIG_SPI_CMDDATA - .cmddata = stm32_spi2cmddata, -#endif - .send = spi_send, -#ifdef CONFIG_SPI_EXCHANGE - .exchange = spi_exchange, -#else - .sndblock = spi_sndblock, - .recvblock = spi_recvblock, -#endif -#ifdef CONFIG_SPI_TRIGGER - .trigger = spi_trigger, -#endif -#ifdef CONFIG_SPI_CALLBACK - .registercallback = stm32_spi2register, /* provided externally */ -#else - .registercallback = 0, /* not implemented */ -#endif -}; - -#if defined(SPI2_DMABUFSIZE_ADJUSTED) -static uint8_t g_spi2_txbuf[SPI2_DMABUFSIZE_ADJUSTED] SPI2_DMABUFSIZE_ALGN; -static uint8_t g_spi2_rxbuf[SPI2_DMABUFSIZE_ADJUSTED] SPI2_DMABUFSIZE_ALGN; -#endif - -static struct stm32_spidev_s g_spi2dev = -{ - .spidev = - { - .ops = &g_sp2iops - }, - .spibase = STM32_SPI2_BASE, - .spiclock = STM32_PCLK1_FREQUENCY, -#ifdef CONFIG_STM32_SPI_INTERRUPTS - .spiirq = STM32_IRQ_SPI2, -#endif -#ifdef CONFIG_STM32_SPI_DMA -# ifdef CONFIG_STM32_SPI2_DMA - .rxch = DMACHAN_SPI2_RX, - .txch = DMACHAN_SPI2_TX, -# ifdef SPI2_DMABUFSIZE_ADJUSTED - .rxbuf = g_spi2_rxbuf, - .txbuf = g_spi2_txbuf, - .buflen = SPI2_DMABUFSIZE_ADJUSTED, -# endif -# else - .rxch = 0, - .txch = 0, -# endif - .rxsem = SEM_INITIALIZER(0), - .txsem = SEM_INITIALIZER(0), -#endif - .lock = NXMUTEX_INITIALIZER, -}; -#endif - -#ifdef CONFIG_STM32_SPI3 -static const struct spi_ops_s g_sp3iops = -{ - .lock = spi_lock, - .select = stm32_spi3select, - .setfrequency = spi_setfrequency, - .setmode = spi_setmode, - .setbits = spi_setbits, -#ifdef CONFIG_SPI_HWFEATURES - .hwfeatures = spi_hwfeatures, -#endif - .status = stm32_spi3status, -#ifdef CONFIG_SPI_CMDDATA - .cmddata = stm32_spi3cmddata, -#endif - .send = spi_send, -#ifdef CONFIG_SPI_EXCHANGE - .exchange = spi_exchange, -#else - .sndblock = spi_sndblock, - .recvblock = spi_recvblock, -#endif -#ifdef CONFIG_SPI_TRIGGER - .trigger = spi_trigger, -#endif -#ifdef CONFIG_SPI_CALLBACK - .registercallback = stm32_spi3register, /* provided externally */ -#else - .registercallback = 0, /* not implemented */ -#endif -}; - -#if defined(SPI3_DMABUFSIZE_ADJUSTED) -static uint8_t g_spi3_txbuf[SPI3_DMABUFSIZE_ADJUSTED] SPI3_DMABUFSIZE_ALGN; -static uint8_t g_spi3_rxbuf[SPI3_DMABUFSIZE_ADJUSTED] SPI3_DMABUFSIZE_ALGN; -#endif - -static struct stm32_spidev_s g_spi3dev = -{ - .spidev = - { - .ops = &g_sp3iops - }, - .spibase = STM32_SPI3_BASE, - .spiclock = STM32_PCLK1_FREQUENCY, -#ifdef CONFIG_STM32_SPI_INTERRUPTS - .spiirq = STM32_IRQ_SPI3, -#endif -#ifdef CONFIG_STM32_SPI_DMA -# ifdef CONFIG_STM32_SPI3_DMA - .rxch = DMACHAN_SPI3_RX, - .txch = DMACHAN_SPI3_TX, -# ifdef SPI3_DMABUFSIZE_ADJUSTED - .rxbuf = g_spi3_rxbuf, - .txbuf = g_spi3_txbuf, - .buflen = SPI3_DMABUFSIZE_ADJUSTED, -# endif -# else - .rxch = 0, - .txch = 0, -# endif - .rxsem = SEM_INITIALIZER(0), - .txsem = SEM_INITIALIZER(0), -#endif - .lock = NXMUTEX_INITIALIZER, -}; -#endif - -#ifdef CONFIG_STM32_SPI4 -static const struct spi_ops_s g_sp4iops = -{ - .lock = spi_lock, - .select = stm32_spi4select, - .setfrequency = spi_setfrequency, - .setmode = spi_setmode, - .setbits = spi_setbits, -#ifdef CONFIG_SPI_HWFEATURES - .hwfeatures = spi_hwfeatures, -#endif - .status = stm32_spi4status, -#ifdef CONFIG_SPI_CMDDATA - .cmddata = stm32_spi4cmddata, -#endif - .send = spi_send, -#ifdef CONFIG_SPI_EXCHANGE - .exchange = spi_exchange, -#else - .sndblock = spi_sndblock, - .recvblock = spi_recvblock, -#endif -#ifdef CONFIG_SPI_TRIGGER - .trigger = spi_trigger, -#endif -#ifdef CONFIG_SPI_CALLBACK - .registercallback = stm32_spi4register, /* provided externally */ -#else - .registercallback = 0, /* not implemented */ -#endif -}; - -#if defined(SPI4_DMABUFSIZE_ADJUSTED) -static uint8_t g_spi4_txbuf[SPI4_DMABUFSIZE_ADJUSTED] SPI4_DMABUFSIZE_ALGN; -static uint8_t g_spi4_rxbuf[SPI4_DMABUFSIZE_ADJUSTED] SPI4_DMABUFSIZE_ALGN; -#endif - -static struct stm32_spidev_s g_spi4dev = -{ - .spidev = - { - .ops = &g_sp4iops - }, - .spibase = STM32_SPI4_BASE, - .spiclock = STM32_PCLK2_FREQUENCY, -#ifdef CONFIG_STM32_SPI_INTERRUPTS - .spiirq = STM32_IRQ_SPI4, -#endif -#ifdef CONFIG_STM32_SPI_DMA -# ifdef CONFIG_STM32_SPI4_DMA - .rxch = DMACHAN_SPI4_RX, - .txch = DMACHAN_SPI4_TX, -# ifdef SPI4_DMABUFSIZE_ADJUSTED - .rxbuf = g_spi4_rxbuf, - .txbuf = g_spi4_txbuf, - .buflen = SPI4_DMABUFSIZE_ADJUSTED, -# endif -# else - .rxch = 0, - .txch = 0, -# endif - .rxsem = SEM_INITIALIZER(0), - .txsem = SEM_INITIALIZER(0), -#endif - .lock = NXMUTEX_INITIALIZER, -}; -#endif - -#ifdef CONFIG_STM32_SPI5 -static const struct spi_ops_s g_sp5iops = -{ - .lock = spi_lock, - .select = stm32_spi5select, - .setfrequency = spi_setfrequency, - .setmode = spi_setmode, - .setbits = spi_setbits, -#ifdef CONFIG_SPI_HWFEATURES - .hwfeatures = spi_hwfeatures, -#endif - .status = stm32_spi5status, -#ifdef CONFIG_SPI_CMDDATA - .cmddata = stm32_spi5cmddata, -#endif - .send = spi_send, -#ifdef CONFIG_SPI_EXCHANGE - .exchange = spi_exchange, -#else - .sndblock = spi_sndblock, - .recvblock = spi_recvblock, -#endif -#ifdef CONFIG_SPI_TRIGGER - .trigger = spi_trigger, -#endif -#ifdef CONFIG_SPI_CALLBACK - .registercallback = stm32_spi5register, /* provided externally */ -#else - .registercallback = 0, /* not implemented */ -#endif -}; - -#if defined(SPI5_DMABUFSIZE_ADJUSTED) -static uint8_t g_spi5_txbuf[SPI5_DMABUFSIZE_ADJUSTED] SPI5_DMABUFSIZE_ALGN; -static uint8_t g_spi5_rxbuf[SPI5_DMABUFSIZE_ADJUSTED] SPI5_DMABUFSIZE_ALGN; -#endif - -static struct stm32_spidev_s g_spi5dev = -{ - .spidev = - { - .ops = &g_sp5iops - }, - .spibase = STM32_SPI5_BASE, - .spiclock = STM32_PCLK2_FREQUENCY, -#ifdef CONFIG_STM32_SPI_INTERRUPTS - .spiirq = STM32_IRQ_SPI5, -#endif -#ifdef CONFIG_STM32_SPI_DMA -# ifdef CONFIG_STM32_SPI5_DMA - .rxch = DMACHAN_SPI5_RX, - .txch = DMACHAN_SPI5_TX, -# ifdef SPI5_DMABUFSIZE_ADJUSTED - .rxbuf = g_spi5_rxbuf, - .txbuf = g_spi5_txbuf, - .buflen = SPI5_DMABUFSIZE_ADJUSTED, -# endif -# else - .rxch = 0, - .txch = 0, -# endif - .rxsem = SEM_INITIALIZER(0), - .txsem = SEM_INITIALIZER(0), -#endif - .lock = NXMUTEX_INITIALIZER, -}; -#endif - -#ifdef CONFIG_STM32_SPI6 -static const struct spi_ops_s g_sp6iops = -{ - .lock = spi_lock, - .select = stm32_spi6select, - .setfrequency = spi_setfrequency, - .setmode = spi_setmode, - .setbits = spi_setbits, -#ifdef CONFIG_SPI_HWFEATURES - .hwfeatures = spi_hwfeatures, -#endif - .status = stm32_spi6status, -#ifdef CONFIG_SPI_CMDDATA - .cmddata = stm32_spi6cmddata, -#endif - .send = spi_send, -#ifdef CONFIG_SPI_EXCHANGE - .exchange = spi_exchange, -#else - .sndblock = spi_sndblock, - .recvblock = spi_recvblock, -#endif -#ifdef CONFIG_SPI_TRIGGER - .trigger = spi_trigger, -#endif -#ifdef CONFIG_SPI_CALLBACK - .registercallback = stm32_spi6register, /* provided externally */ -#else - .registercallback = 0, /* not implemented */ -#endif -}; - -#if defined(SPI6_DMABUFSIZE_ADJUSTED) -static uint8_t g_spi6_txbuf[SPI6_DMABUFSIZE_ADJUSTED] SPI6_DMABUFSIZE_ALGN; -static uint8_t g_spi6_rxbuf[SPI6_DMABUFSIZE_ADJUSTED] SPI6_DMABUFSIZE_ALGN; -#endif - -static struct stm32_spidev_s g_spi6dev = -{ - .spidev = - { - .ops = &g_sp6iops - }, - .spibase = STM32_SPI6_BASE, - .spiclock = STM32_PCLK2_FREQUENCY, -#ifdef CONFIG_STM32_SPI_INTERRUPTS - .spiirq = STM32_IRQ_SPI6, -#endif -#ifdef CONFIG_STM32_SPI_DMA -# ifdef CONFIG_STM32_SPI6_DMA - .rxch = DMACHAN_SPI6_RX, - .txch = DMACHAN_SPI6_TX, -# ifdef SPI6_DMABUFSIZE_ADJUSTED - .rxbuf = g_spi6_rxbuf, - .txbuf = g_spi6_txbuf, - .buflen = SPI6_DMABUFSIZE_ADJUSTED, -# endif -# else - .rxch = 0, - .txch = 0, -# endif - .rxsem = SEM_INITIALIZER(0), - .txsem = SEM_INITIALIZER(0), -#endif - .lock = NXMUTEX_INITIALIZER, -}; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: spi_getreg - * - * Description: - * Get the contents of the SPI register at offset - * - * Input Parameters: - * priv - private SPI device structure - * offset - offset to the register of interest - * - * Returned Value: - * The contents of the 16-bit register - * - ****************************************************************************/ - -static inline uint16_t spi_getreg(struct stm32_spidev_s *priv, - uint8_t offset) -{ - return getreg16(priv->spibase + offset); -} - -/**************************************************************************** - * Name: spi_getreg8 - * - * Description: - * Get the contents of the SPI register at offset - * - * Input Parameters: - * priv - private SPI device structure - * offset - offset to the register of interest - * - * Returned Value: - * The contents of the 16-bit register - * - ****************************************************************************/ - -#if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX) || \ - defined(CONFIG_STM32_STM32G4XXX) -static inline uint8_t spi_getreg8(struct stm32_spidev_s *priv, - uint8_t offset) -{ - return getreg8(priv->spibase + offset); -} -#endif - -/**************************************************************************** - * Name: spi_putreg - * - * Description: - * Write a 16-bit value to the SPI register at offset - * - * Input Parameters: - * priv - private SPI device structure - * offset - offset to the register of interest - * value - the 16-bit value to be written - * - * Returned Value: - * The contents of the 16-bit register - * - ****************************************************************************/ - -static inline void spi_putreg(struct stm32_spidev_s *priv, - uint8_t offset, - uint16_t value) -{ - putreg16(value, priv->spibase + offset); -} - -/**************************************************************************** - * Name: spi_putreg8 - * - * Description: - * Write an 8-bit value to the SPI register at offset - * - * Input Parameters: - * priv - private SPI device structure - * offset - offset to the register of interest - * value - the 16-bit value to be written - * - * Returned Value: - * The contents of the 16-bit register - * - ****************************************************************************/ - -#if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX) || \ - defined(CONFIG_STM32_STM32G4XXX) -static inline void spi_putreg8(struct stm32_spidev_s *priv, - uint8_t offset, - uint8_t value) -{ - putreg8(value, priv->spibase + offset); -} -#endif - -/**************************************************************************** - * Name: spi_readword - * - * Description: - * Read one byte from SPI - * - * Input Parameters: - * priv - Device-specific state data - * - * Returned Value: - * Byte as read - * - ****************************************************************************/ - -static inline uint16_t spi_readword(struct stm32_spidev_s *priv) -{ - /* Wait until the receive buffer is not empty */ - - while ((spi_getreg(priv, STM32_SPI_SR_OFFSET) & SPI_SR_RXNE) == 0) - { - } - - /* Then return the received byte */ - -#if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX)|| \ - defined(CONFIG_STM32_STM32G4XXX) - /* "When the data frame size fits into one byte - * (less than or equal to 8 bits), - * data packing is used automatically when any read or write 16-bit access - * is performed on the SPIx_DR register. The double data frame pattern is - * handled in parallel in this case. At first, the SPI operates using the - * pattern stored in the LSB of the accessed word, then with the other - * half stored in the MSB.... The receiver then has to access both data - * frames by a single 16-bit read of SPIx_DR as a response to this single - * RXNE event. The RxFIFO threshold setting and the following read access - * must be always kept aligned at the receiver side, as data can be lost - * if it is not in line." - */ - - if (priv->nbits < 9) - { - return (uint16_t)spi_getreg8(priv, STM32_SPI_DR_OFFSET); - } - else -#endif - { - return spi_getreg(priv, STM32_SPI_DR_OFFSET); - } -} - -/**************************************************************************** - * Name: spi_writeword - * - * Description: - * Write one byte to SPI - * - * Input Parameters: - * priv - Device-specific state data - * byte - Byte to send - * - * Returned Value: - * None - * - ****************************************************************************/ - -static inline void spi_writeword(struct stm32_spidev_s *priv, - uint16_t word) -{ - /* Wait until the transmit buffer is empty */ - - while ((spi_getreg(priv, STM32_SPI_SR_OFFSET) & SPI_SR_TXE) == 0) - { - } - - /* Then send the word */ - -#if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX) || \ - defined(CONFIG_STM32_STM32G4XXX) - /* "When the data frame size fits into one byte (less than or equal to 8 - * bits), data packing is used automatically when any read or write 16-bit - * access is performed on the SPIx_DR register. The double data frame - * pattern is handled in parallel in this case. At first, the SPI operates - * using the pattern stored in the LSB of the accessed word, then with the - * other half stored in the MSB... - * - * "A specific problem appears if an odd number of such "fit into one - * byte" data frames must be handled. On the transmitter side, writing - * the last data frame of any odd sequence with an 8-bit access to - * SPIx_DR is enough. ..." - * - * REVISIT: "...The receiver has to change the Rx_FIFO threshold level for - * the last data frame received in the odd sequence of frames in order to - * generate the RXNE event." - */ - - if (priv->nbits < 9) - { - spi_putreg8(priv, STM32_SPI_DR_OFFSET, (uint8_t)word); - } - else -#endif - { - spi_putreg(priv, STM32_SPI_DR_OFFSET, word); - } -} - -/**************************************************************************** - * Name: spi_dmarxwait - * - * Description: - * Wait for DMA to complete. - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_SPI_DMA -static int spi_dmarxwait(struct stm32_spidev_s *priv) -{ - int ret; - - /* Take the semaphore (perhaps waiting). If the result is zero, then the - * DMA must not really have completed??? - */ - - do - { - ret = nxsem_wait_uninterruptible(&priv->rxsem); - - /* The only expected error is ECANCELED which would occur if the - * calling thread were canceled. - */ - - DEBUGASSERT(ret == OK || ret == -ECANCELED); - } - while (priv->rxresult == 0 && ret == OK); - - return ret; -} -#endif - -/**************************************************************************** - * Name: spi_dmatxwait - * - * Description: - * Wait for DMA to complete. - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_SPI_DMA -static int spi_dmatxwait(struct stm32_spidev_s *priv) -{ - int ret; - - /* Take the semaphore (perhaps waiting). If the result is zero, then the - * DMA must not really have completed??? - */ - - do - { - ret = nxsem_wait_uninterruptible(&priv->txsem); - - /* The only expected error is ECANCELED which would occur if the - * calling thread were canceled. - */ - - DEBUGASSERT(ret == OK || ret == -ECANCELED); - } - while (priv->txresult == 0 && ret == OK); - - return ret; -} -#endif - -/**************************************************************************** - * Name: spi_dmarxwakeup - * - * Description: - * Signal that DMA is complete - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_SPI_DMA -static inline void spi_dmarxwakeup(struct stm32_spidev_s *priv) -{ - nxsem_post(&priv->rxsem); -} -#endif - -/**************************************************************************** - * Name: spi_dmatxwakeup - * - * Description: - * Signal that DMA is complete - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_SPI_DMA -static inline void spi_dmatxwakeup(struct stm32_spidev_s *priv) -{ - nxsem_post(&priv->txsem); -} -#endif - -/**************************************************************************** - * Name: spi_dmarxcallback - * - * Description: - * Called when the RX DMA completes - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_SPI_DMA -static void spi_dmarxcallback(DMA_HANDLE handle, uint8_t isr, void *arg) -{ - struct stm32_spidev_s *priv = (struct stm32_spidev_s *)arg; - - /* Wake-up the SPI driver */ - - priv->rxresult = isr | 0x080; /* OR'ed with 0x80 to assure non-zero */ - spi_dmarxwakeup(priv); -} -#endif - -/**************************************************************************** - * Name: spi_dmatxcallback - * - * Description: - * Called when the RX DMA completes - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_SPI_DMA -static void spi_dmatxcallback(DMA_HANDLE handle, uint8_t isr, void *arg) -{ - struct stm32_spidev_s *priv = (struct stm32_spidev_s *)arg; - - /* Wake-up the SPI driver */ - - priv->txresult = isr | 0x080; /* OR'ed with 0x80 to assure non-zero */ - spi_dmatxwakeup(priv); -} -#endif - -/**************************************************************************** - * Name: spi_dmarxsetup - * - * Description: - * Setup to perform RX DMA - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_SPI_DMA -static void spi_dmarxsetup(struct stm32_spidev_s *priv, - void *rxbuffer, - void *rxdummy, size_t nwords) -{ - /* 8- or 16-bit mode? */ - - if (priv->nbits > 8) - { - /* 16-bit mode -- is there a buffer to receive data in? */ - - if (rxbuffer) - { - priv->rxccr = SPI_RXDMA16_CONFIG; - } - else - { - rxbuffer = rxdummy; - priv->rxccr = SPI_RXDMA16NULL_CONFIG; - } - } - else - { - /* 8-bit mode -- is there a buffer to receive data in? */ - - if (rxbuffer) - { - priv->rxccr = SPI_RXDMA8_CONFIG; - } - else - { - rxbuffer = rxdummy; - priv->rxccr = SPI_RXDMA8NULL_CONFIG; - } - } - - /* Configure the RX DMA */ - - stm32_dmasetup(priv->rxdma, priv->spibase + STM32_SPI_DR_OFFSET, - (uint32_t)rxbuffer, nwords, priv->rxccr); -} -#endif - -/**************************************************************************** - * Name: spi_dmatxsetup - * - * Description: - * Setup to perform TX DMA - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_SPI_DMA -static void spi_dmatxsetup(struct stm32_spidev_s *priv, - const void *txbuffer, - const void *txdummy, size_t nwords) -{ - /* 8- or 16-bit mode? */ - - if (priv->nbits > 8) - { - /* 16-bit mode -- is there a buffer to transfer data from? */ - - if (txbuffer) - { - priv->txccr = SPI_TXDMA16_CONFIG; - } - else - { - txbuffer = txdummy; - priv->txccr = SPI_TXDMA16NULL_CONFIG; - } - } - else - { - /* 8-bit mode -- is there a buffer to transfer data from? */ - - if (txbuffer) - { - priv->txccr = SPI_TXDMA8_CONFIG; - } - else - { - txbuffer = txdummy; - priv->txccr = SPI_TXDMA8NULL_CONFIG; - } - } - - /* Setup the TX DMA */ - - stm32_dmasetup(priv->txdma, priv->spibase + STM32_SPI_DR_OFFSET, - (uint32_t)txbuffer, nwords, priv->txccr); -} -#endif - -/**************************************************************************** - * Name: spi_dmarxstart - * - * Description: - * Start RX DMA - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_SPI_DMA -static inline void spi_dmarxstart(struct stm32_spidev_s *priv) -{ - priv->rxresult = 0; - stm32_dmastart(priv->rxdma, spi_dmarxcallback, priv, false); -} -#endif - -/**************************************************************************** - * Name: spi_dmatxstart - * - * Description: - * Start TX DMA - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_SPI_DMA -static inline void spi_dmatxstart(struct stm32_spidev_s *priv) -{ - priv->txresult = 0; - stm32_dmastart(priv->txdma, spi_dmatxcallback, priv, false); -} -#endif - -/**************************************************************************** - * Name: spi_modifycr1 - * - * Description: - * Clear and set bits in the CR1 register - * - * Input Parameters: - * priv - Device-specific state data - * clrbits - The bits to clear - * setbits - The bits to set - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void spi_modifycr1(struct stm32_spidev_s *priv, - uint16_t setbits, - uint16_t clrbits) -{ - uint16_t cr1; - cr1 = spi_getreg(priv, STM32_SPI_CR1_OFFSET); - cr1 &= ~clrbits; - cr1 |= setbits; - spi_putreg(priv, STM32_SPI_CR1_OFFSET, cr1); -} - -/**************************************************************************** - * Name: spi_modifycr2 - * - * Description: - * Clear and set bits in the CR2 register - * - * Input Parameters: - * priv - Device-specific state data - * clrbits - The bits to clear - * setbits - The bits to set - * - * Returned Value: - * None - * - ****************************************************************************/ - -#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F30XX) || \ - defined(CONFIG_STM32_STM32F37XX) || defined(CONFIG_STM32_STM32F4XXX) || \ - defined(CONFIG_STM32_STM32G4XXX) || defined(CONFIG_STM32_SPI_DMA) -static void spi_modifycr2(struct stm32_spidev_s *priv, uint16_t setbits, - uint16_t clrbits) -{ - uint16_t cr2; - cr2 = spi_getreg(priv, STM32_SPI_CR2_OFFSET); - cr2 &= ~clrbits; - cr2 |= setbits; - spi_putreg(priv, STM32_SPI_CR2_OFFSET, cr2); -} -#endif - -/**************************************************************************** - * Name: spi_lock - * - * Description: - * On SPI buses where there are multiple devices, it will be necessary to - * lock SPI to have exclusive access to the buses for a sequence of - * transfers. The bus should be locked before the chip is selected. After - * locking the SPI bus, the caller should then also call the setfrequency, - * setbits, and setmode methods to make sure that the SPI is properly - * configured for the device. If the SPI bus is being shared, then it - * may have been left in an incompatible state. - * - * Input Parameters: - * dev - Device-specific state data - * lock - true: Lock spi bus, false: unlock SPI bus - * - * Returned Value: - * None - * - ****************************************************************************/ - -static int spi_lock(struct spi_dev_s *dev, bool lock) -{ - struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev; - int ret; - - if (lock) - { - ret = nxmutex_lock(&priv->lock); - } - else - { - ret = nxmutex_unlock(&priv->lock); - } - - return ret; -} - -/**************************************************************************** - * Name: spi_setfrequency - * - * Description: - * Set the SPI frequency. - * - * Input Parameters: - * dev - Device-specific state data - * frequency - The SPI frequency requested - * - * Returned Value: - * Returns the actual frequency selected - * - ****************************************************************************/ - -static uint32_t spi_setfrequency(struct spi_dev_s *dev, - uint32_t frequency) -{ - struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev; - uint16_t setbits; - uint32_t actual; - - /* Has the frequency changed? */ - - if (frequency != priv->frequency) - { - /* Choices are limited by PCLK frequency with a set of divisors */ - - if (frequency >= priv->spiclock >> 1) - { - /* More than fPCLK/2. This is as fast as we can go */ - - setbits = SPI_CR1_FPCLCKd2; /* 000: fPCLK/2 */ - actual = priv->spiclock >> 1; - } - else if (frequency >= priv->spiclock >> 2) - { - /* Between fPCLCK/2 and fPCLCK/4, pick the slower */ - - setbits = SPI_CR1_FPCLCKd4; /* 001: fPCLK/4 */ - actual = priv->spiclock >> 2; - } - else if (frequency >= priv->spiclock >> 3) - { - /* Between fPCLCK/4 and fPCLCK/8, pick the slower */ - - setbits = SPI_CR1_FPCLCKd8; /* 010: fPCLK/8 */ - actual = priv->spiclock >> 3; - } - else if (frequency >= priv->spiclock >> 4) - { - /* Between fPCLCK/8 and fPCLCK/16, pick the slower */ - - setbits = SPI_CR1_FPCLCKd16; /* 011: fPCLK/16 */ - actual = priv->spiclock >> 4; - } - else if (frequency >= priv->spiclock >> 5) - { - /* Between fPCLCK/16 and fPCLCK/32, pick the slower */ - - setbits = SPI_CR1_FPCLCKd32; /* 100: fPCLK/32 */ - actual = priv->spiclock >> 5; - } - else if (frequency >= priv->spiclock >> 6) - { - /* Between fPCLCK/32 and fPCLCK/64, pick the slower */ - - setbits = SPI_CR1_FPCLCKd64; /* 101: fPCLK/64 */ - actual = priv->spiclock >> 6; - } - else if (frequency >= priv->spiclock >> 7) - { - /* Between fPCLCK/64 and fPCLCK/128, pick the slower */ - - setbits = SPI_CR1_FPCLCKd128; /* 110: fPCLK/128 */ - actual = priv->spiclock >> 7; - } - else - { - /* Less than fPCLK/128. This is as slow as we can go */ - - setbits = SPI_CR1_FPCLCKd256; /* 111: fPCLK/256 */ - actual = priv->spiclock >> 8; - } - - spi_modifycr1(priv, 0, SPI_CR1_SPE); - spi_modifycr1(priv, setbits, SPI_CR1_BR_MASK); - spi_modifycr1(priv, SPI_CR1_SPE, 0); - - /* Save the frequency selection so that subsequent reconfigurations - * will be faster. - */ - - spiinfo("Frequency %" PRIu32 "->%" PRIu32 "\n", frequency, actual); - - priv->frequency = frequency; - priv->actual = actual; - } - - return priv->actual; -} - -/**************************************************************************** - * Name: spi_setmode - * - * Description: - * Set the SPI mode. see enum spi_mode_e for mode definitions - * - * Input Parameters: - * dev - Device-specific state data - * mode - The SPI mode requested - * - * Returned Value: - * Returns the actual frequency selected - * - ****************************************************************************/ - -static void spi_setmode(struct spi_dev_s *dev, enum spi_mode_e mode) -{ - struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev; - uint16_t setbits; - uint16_t clrbits; - - spiinfo("mode=%d\n", mode); - - /* Has the mode changed? */ - - if (mode != priv->mode) - { - /* Yes... Set CR1 appropriately */ - - switch (mode) - { - case SPIDEV_MODE0: /* CPOL=0; CPHA=0 */ - setbits = 0; - clrbits = SPI_CR1_CPOL | SPI_CR1_CPHA; - break; - - case SPIDEV_MODE1: /* CPOL=0; CPHA=1 */ - setbits = SPI_CR1_CPHA; - clrbits = SPI_CR1_CPOL; - break; - - case SPIDEV_MODE2: /* CPOL=1; CPHA=0 */ - setbits = SPI_CR1_CPOL; - clrbits = SPI_CR1_CPHA; - break; - - case SPIDEV_MODE3: /* CPOL=1; CPHA=1 */ - setbits = SPI_CR1_CPOL | SPI_CR1_CPHA; - clrbits = 0; - break; - -#ifdef SPI_CR2_FRF /* If MCU supports TI Synchronous Serial Frame Format */ - case SPIDEV_MODETI: - setbits = 0; - clrbits = SPI_CR1_CPOL | SPI_CR1_CPHA; - break; -#endif - - default: - return; - } - - spi_modifycr1(priv, 0, SPI_CR1_SPE); - spi_modifycr1(priv, setbits, clrbits); - spi_modifycr1(priv, SPI_CR1_SPE, 0); - -#ifdef SPI_CR2_FRF /* If MCU supports TI Synchronous Serial Frame Format */ - switch (mode) - { - case SPIDEV_MODE0: - case SPIDEV_MODE1: - case SPIDEV_MODE2: - case SPIDEV_MODE3: - setbits = 0; - clrbits = SPI_CR2_FRF; - break; - - case SPIDEV_MODETI: - setbits = SPI_CR2_FRF; - clrbits = 0; - break; - - default: - return; - } - - spi_modifycr1(priv, 0, SPI_CR1_SPE); - spi_modifycr2(priv, setbits, clrbits); - spi_modifycr1(priv, SPI_CR1_SPE, 0); -#endif - - /* Save the mode so that subsequent re-configurations will be - * faster - */ - - priv->mode = mode; - } -} - -/**************************************************************************** - * Name: spi_setbits - * - * Description: - * Set the number of bits per word. - * - * Input Parameters: - * dev - Device-specific state data - * nbits - The number of bits requested - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void spi_setbits(struct spi_dev_s *dev, int nbits) -{ - struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev; - uint16_t setbits; - uint16_t clrbits; - - spiinfo("nbits=%d\n", nbits); - - /* Has the number of bits changed? */ - - if (nbits != priv->nbits) - { -#if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX) || \ - defined(CONFIG_STM32_STM32G4XXX) - /* Yes... Set CR2 appropriately */ - - /* Set the number of bits (valid range 4-16) */ - - if (nbits < 4 || nbits > 16) - { - spierr("ERROR: nbits out of range: %d\n", nbits); - return; - } - - clrbits = SPI_CR2_DS_MASK; - setbits = SPI_CR2_DS(nbits); - - /* If nbits is <=8, then we are in byte mode and FRXTH must be set - * (else, transaction will not complete). - */ - - if (nbits < 9) - { - setbits |= SPI_CR2_FRXTH; /* RX FIFO Threshold = 1 byte */ - } - else - { - clrbits |= SPI_CR2_FRXTH; /* RX FIFO Threshold = 2 bytes */ - } - - spi_modifycr1(priv, 0, SPI_CR1_SPE); - spi_modifycr2(priv, setbits, clrbits); - spi_modifycr1(priv, SPI_CR1_SPE, 0); -#else - /* Yes... Set CR1 appropriately */ - - switch (nbits) - { - case 8: - setbits = 0; - clrbits = SPI_CR1_DFF; - break; - - case 16: - setbits = SPI_CR1_DFF; - clrbits = 0; - break; - - default: - return; - } - - spi_modifycr1(priv, 0, SPI_CR1_SPE); - spi_modifycr1(priv, setbits, clrbits); - spi_modifycr1(priv, SPI_CR1_SPE, 0); -#endif - /* Save the selection so that subsequent re-configurations will be - * faster. - */ - - priv->nbits = nbits; - } -} - -/**************************************************************************** - * Name: spi_hwfeatures - * - * Description: - * Set hardware-specific feature flags. - * - * Input Parameters: - * dev - Device-specific state data - * features - H/W feature flags - * - * Returned Value: - * Zero (OK) if the selected H/W features are enabled; A negated errno - * value if any H/W feature is not supportable. - * - ****************************************************************************/ - -#ifdef CONFIG_SPI_HWFEATURES -static int spi_hwfeatures(struct spi_dev_s *dev, - spi_hwfeatures_t features) -{ -#if defined(CONFIG_SPI_BITORDER) || defined(CONFIG_SPI_TRIGGER) - struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev; -#endif - -#ifdef CONFIG_SPI_BITORDER - uint16_t setbits; - uint16_t clrbits; - - spiinfo("features=%08x\n", features); - - /* Transfer data LSB first? */ - - if ((features & HWFEAT_LSBFIRST) != 0) - { - setbits = SPI_CR1_LSBFIRST; - clrbits = 0; - } - else - { - setbits = 0; - clrbits = SPI_CR1_LSBFIRST; - } - - spi_modifycr1(priv, 0, SPI_CR1_SPE); - spi_modifycr1(priv, setbits, clrbits); - spi_modifycr1(priv, SPI_CR1_SPE, 0); - - features &= ~HWFEAT_LSBFIRST; -#endif - -#ifdef CONFIG_SPI_TRIGGER -/* Turn deferred trigger mode on or off. Only applicable for DMA mode. If a - * transfer is deferred then the DMA will not actually be triggered until a - * subsequent call to SPI_TRIGGER to set it off. The thread will be waiting - * on the transfer completing as normal. - */ - - priv->defertrig = ((features & HWFEAT_TRIGGER) != 0); - features &= ~HWFEAT_TRIGGER; -#endif - - /* Other H/W features are not supported */ - - return (features == 0) ? OK : -ENOSYS; -} -#endif - -/**************************************************************************** - * Name: spi_send - * - * Description: - * Exchange one word on SPI - * - * Input Parameters: - * dev - Device-specific state data - * wd - The word to send. the size of the data is determined by the - * number of bits selected for the SPI interface. - * - * Returned Value: - * response - * - ****************************************************************************/ - -static uint32_t spi_send(struct spi_dev_s *dev, uint32_t wd) -{ - struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev; - uint32_t regval; - uint32_t ret; - - DEBUGASSERT(priv && priv->spibase); - - spi_writeword(priv, (uint32_t)(wd & 0xffff)); - ret = (uint32_t)spi_readword(priv); - - /* Check and clear any error flags - * (Reading from the SR clears the error flags) - */ - - regval = spi_getreg(priv, STM32_SPI_SR_OFFSET); - - spiinfo("Sent: %04" PRIx32 " Return: %04" PRIx32 - " Status: %02" PRIx32 "\n", wd, ret, regval); - UNUSED(regval); - - return ret; -} - -/**************************************************************************** - * Name: spi_exchange (no DMA). aka spi_exchange_nodma - * - * Description: - * Exchange a block of data on SPI without using DMA - * - * REVISIT: - * This function could be much more efficient by exploiting (1) RX and TX - * FIFOs and (2) the STM32 F3 data packing. - * - * Input Parameters: - * dev - Device-specific state data - * txbuffer - A pointer to the buffer of data to be sent - * rxbuffer - A pointer to a buffer in which to receive data - * nwords - the length of data to be exchanged in units of words. - * The wordsize is determined by the number of bits-per-word - * selected for the SPI interface. If nbits <= 8, the data is - * packed into uint8_t's; if nbits >8, the data is packed into - * uint16_t's - * - * Returned Value: - * None - * - ****************************************************************************/ - -#if !defined(CONFIG_STM32_SPI_DMA) || defined(CONFIG_STM32_DMACAPABLE) || \ - defined(CONFIG_STM32_SPI_DMATHRESHOLD) -#if !defined(CONFIG_STM32_SPI_DMA) -static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, - void *rxbuffer, size_t nwords) -#else -static void spi_exchange_nodma(struct spi_dev_s *dev, - const void *txbuffer, - void *rxbuffer, size_t nwords) -#endif -{ - struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev; - DEBUGASSERT(priv && priv->spibase); - - spiinfo("txbuffer=%p rxbuffer=%p nwords=%d\n", txbuffer, rxbuffer, nwords); - - /* 8- or 16-bit mode? */ - - if (priv->nbits > 8) - { - /* 16-bit mode */ - - const uint16_t *src = (const uint16_t *)txbuffer; - uint16_t *dest = (uint16_t *)rxbuffer; - uint16_t word; - - while (nwords-- > 0) - { - /* Get the next word to write. Is there a source buffer? */ - - if (src) - { - word = *src++; - } - else - { - word = 0xffff; - } - - /* Exchange one word */ - - word = (uint16_t)spi_send(dev, (uint32_t)word); - - /* Is there a buffer to receive the return value? */ - - if (dest) - { - *dest++ = word; - } - } - } - else - { - /* 8-bit mode */ - - const uint8_t *src = (const uint8_t *)txbuffer; - uint8_t *dest = (uint8_t *)rxbuffer; - uint8_t word; - - while (nwords-- > 0) - { - /* Get the next word to write. Is there a source buffer? */ - - if (src) - { - word = *src++; - } - else - { - word = 0xff; - } - - /* Exchange one word */ - - word = (uint8_t)spi_send(dev, (uint32_t)word); - - /* Is there a buffer to receive the return value? */ - - if (dest) - { - *dest++ = word; - } - } - } -} -#endif /* !CONFIG_STM32_SPI_DMA || CONFIG_STM32_DMACAPABLE || CONFIG_STM32_SPI_DMATHRESHOLD */ - -/**************************************************************************** - * Name: spi_exchange (with DMA capability) - * - * Description: - * Exchange a block of data on SPI using DMA - * - * Input Parameters: - * dev - Device-specific state data - * txbuffer - A pointer to the buffer of data to be sent - * rxbuffer - A pointer to a buffer in which to receive data - * nwords - the length of data to be exchanged in units of words. - * The wordsize is determined by the number of bits-per-word - * selected for the SPI interface. If nbits <= 8, the data is - * packed into uint8_t's; if nbits >8, the data is packed into - * uint16_t's - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_SPI_DMA -static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, - void *rxbuffer, size_t nwords) -{ - struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev; - void *xbuffer = rxbuffer; - int ret; - - DEBUGASSERT(priv != NULL); - - /* Convert the number of word to a number of bytes */ - - size_t nbytes = (priv->nbits > 8) ? nwords << 1 : nwords; - -#ifdef CONFIG_STM32_SPI_DMATHRESHOLD - /* If this is a small SPI transfer, then let spi_exchange_nodma() do the - * work. - */ - - if (nbytes <= CONFIG_STM32_SPI_DMATHRESHOLD) - { - spi_exchange_nodma(dev, txbuffer, rxbuffer, nwords); - return; - } -#endif - - if ((priv->rxdma == NULL) || (priv->txdma == NULL) || - up_interrupt_context()) - { - /* Invalid DMA channels, or interrupt context, fall - * back to non-DMA method. - */ - - spi_exchange_nodma(dev, txbuffer, rxbuffer, nwords); - return; - } - -#ifdef CONFIG_STM32_DMACAPABLE - if ((txbuffer && priv->txbuf == 0 && - !stm32_dmacapable((uintptr_t)txbuffer, nwords, priv->txccr)) || - (rxbuffer && priv->rxbuf == 0 && - !stm32_dmacapable((uintptr_t)rxbuffer, nwords, priv->rxccr))) - { - /* Unsupported memory region fall back to non-DMA method. */ - - spi_exchange_nodma(dev, txbuffer, rxbuffer, nwords); - } - else -#endif - { - static uint16_t rxdummy = 0xffff; - static const uint16_t txdummy = 0xffff; - const size_t word_size = (priv->nbits > 8) ? 2u : 1u; - const uint8_t *txp; - uint8_t *rxp; - - spiinfo("txbuffer=%p rxbuffer=%p nwords=%zu\n", - txbuffer, rxbuffer, nwords); - DEBUGASSERT(priv && priv->spibase); - - /* Setup DMAs */ - - /* If this bus uses an in-driver buffer we will incur 2 copies, - * The copy cost is << less the non DMA transfer time and having - * the buffer in the driver ensures DMA can be used. This is because - * the API does not support passing the buffer extent so the only - * extent is buffer + the transfer size. These can sizes be less than - * the cache line size, and not aligned and typically greater then 4 - * bytes, which is about the break even point for the DMA IO overhead. - */ - - if (txbuffer && priv->txbuf) - { - if (nbytes > priv->buflen) - { - nbytes = priv->buflen; - } - - memcpy(priv->txbuf, txbuffer, nbytes); - txbuffer = priv->txbuf; - rxbuffer = rxbuffer ? priv->rxbuf : rxbuffer; - - /* Rescale nwords to match the (possibly clamped) nbytes. */ - - nwords = (priv->nbits > 8) ? nbytes >> 1 : nbytes; - } - - txp = (const uint8_t *)txbuffer; - rxp = (uint8_t *)rxbuffer; - ret = OK; - - /* Walk the request in chunks of at most STM32_SPI_DMA_MAX_XFER words. - * The STM32 DMA NDTR/CNDTR transfer-count register is only 16 bits - * wide; submitting more than 65535 transfers in a single descriptor - * silently programs NDTR to (nwords & 0xffff) and on most paths - * results in a stream that never raises transfer-complete, causing - * the SPI driver to block forever in spi_dmarxwait(). Splitting the - * request keeps each descriptor within the hardware limit and lets - * the W25/SD/etc. driver remain agnostic of this constraint. - */ - - while (nwords > 0) - { - size_t chunk = (nwords > STM32_SPI_DMA_MAX_XFER) - ? STM32_SPI_DMA_MAX_XFER - : nwords; - - spi_dmarxsetup(priv, rxp, &rxdummy, chunk); - spi_dmatxsetup(priv, txp, &txdummy, chunk); - -#ifdef CONFIG_SPI_TRIGGER - /* Is deferred triggering in effect? */ - - if (!priv->defertrig) - { - /* No.. Start the DMAs */ - - spi_dmarxstart(priv); - spi_dmatxstart(priv); - } - else - { - /* Yes.. indicate that we are ready to be started. Deferred - * triggering is only meaningful for the first (often only) - * chunk; subsequent chunks must run unconditionally or the - * caller would have to re-arm between chunks. - */ - - priv->trigarmed = true; - } -#else - /* Start the DMAs */ - - spi_dmarxstart(priv); - spi_dmatxstart(priv); -#endif - - /* Then wait for each to complete */ - - ret = spi_dmarxwait(priv); - if (ret < 0) - { - ret = spi_dmatxwait(priv); - } - - if (ret < 0) - { - break; - } - - if (txp != NULL) - { - txp += chunk * word_size; - } - - if (rxp != NULL) - { - rxp += chunk * word_size; - } - - nwords -= chunk; - } - - if (rxbuffer != NULL && priv->rxbuf != NULL && ret >= 0) - { - memcpy(xbuffer, priv->rxbuf, nbytes); - } - -#ifdef CONFIG_SPI_TRIGGER - priv->trigarmed = false; -#endif - } -} -#endif /* CONFIG_STM32_SPI_DMA */ - -/**************************************************************************** - * Name: spi_trigger - * - * Description: - * Trigger a previously configured DMA transfer. - * - * Input Parameters: - * dev - Device-specific state data - * - * Returned Value: - * OK - Trigger was fired - * ENOTSUP - Trigger not fired due to lack of DMA support - * EIO - Trigger not fired because not previously primed - * - ****************************************************************************/ - -#ifdef CONFIG_SPI_TRIGGER -static int spi_trigger(struct spi_dev_s *dev) -{ -#ifdef CONFIG_STM32_SPI_DMA - struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev; - - if (!priv->trigarmed) - { - return -EIO; - } - - spi_dmarxstart(priv); - spi_dmatxstart(priv); - - return OK; -#else - return -ENOSYS; -#endif -} -#endif - -/**************************************************************************** - * Name: spi_sndblock - * - * Description: - * Send a block of data on SPI - * - * Input Parameters: - * dev - Device-specific state data - * txbuffer - A pointer to the buffer of data to be sent - * nwords - the length of data to send from the buffer in number of - * words. - * The wordsize is determined by the number of bits-per-word - * selected for the SPI interface. If nbits <= 8, the data is - * packed into uint8_t's; if nbits >8, the data is packed into - * uint16_t's - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifndef CONFIG_SPI_EXCHANGE -static void spi_sndblock(struct spi_dev_s *dev, - const void *txbuffer, - size_t nwords) -{ - spiinfo("txbuffer=%p nwords=%d\n", txbuffer, nwords); - return spi_exchange(dev, txbuffer, NULL, nwords); -} -#endif - -/**************************************************************************** - * Name: spi_recvblock - * - * Description: - * Receive a block of data from SPI - * - * Input Parameters: - * dev - Device-specific state data - * rxbuffer - A pointer to the buffer in which to receive data - * nwords - the length of data that can be received in the buffer in - * number of words. The wordsize is determined by the number - * of bits-per-word selected for the SPI interface. If - * nbits <= 8, the data is packed into uint8_t's; if nbits >8, - * the data is packed into uint16_t's - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifndef CONFIG_SPI_EXCHANGE -static void spi_recvblock(struct spi_dev_s *dev, - void *rxbuffer, - size_t nwords) -{ - spiinfo("rxbuffer=%p nwords=%d\n", rxbuffer, nwords); - return spi_exchange(dev, NULL, rxbuffer, nwords); -} -#endif - -/**************************************************************************** - * Name: spi_bus_initialize - * - * Description: - * Initialize the selected SPI bus in its default state (Master, 8-bit, - * mode 0, etc.) - * - * Input Parameters: - * priv - private SPI device structure - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void spi_bus_initialize(struct stm32_spidev_s *priv) -{ - uint16_t setbits; - uint16_t clrbits; - -#if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX) || \ - defined(CONFIG_STM32_STM32G4XXX) - /* Configure CR1 and CR2. Default configuration: - * Mode 0: CR1.CPHA=0 and CR1.CPOL=0 - * Master: CR1.MSTR=1 - * 8-bit: CR2.DS=7 - * MSB transmitted first: CR1.LSBFIRST=0 - * Replace NSS with SSI & SSI=1: CR1.SSI=1 CR1.SSM=1 - * (prevents MODF error) - * Two lines full duplex: CR1.BIDIMODE=0 CR1.BIDIOIE=(Don't care) - * and CR1.RXONLY=0 - */ - - clrbits = SPI_CR1_CPHA | SPI_CR1_CPOL | SPI_CR1_BR_MASK | - SPI_CR1_LSBFIRST | SPI_CR1_RXONLY | SPI_CR1_CRCL | - SPI_CR1_BIDIOE | SPI_CR1_BIDIMODE; - setbits = SPI_CR1_MSTR | SPI_CR1_SSI | SPI_CR1_SSM; - spi_modifycr1(priv, setbits, clrbits); - - clrbits = SPI_CR2_DS_MASK; - setbits = SPI_CR2_DS_8BIT | SPI_CR2_FRXTH; /* FRXTH must be high in 8-bit mode */ - spi_modifycr2(priv, setbits, clrbits); -#else - /* Configure CR1. Default configuration: - * Mode 0: CPHA=0 and CPOL=0 - * Master: MSTR=1 - * 8-bit: DFF=0 - * MSB transmitted first: LSBFIRST=0 - * Replace NSS with SSI & SSI=1: SSI=1 SSM=1 (prevents MODF error) - * Two lines full duplex: BIDIMODE=0 BIDIOIE=(Don't care) - * and RXONLY=0 - */ - - clrbits = SPI_CR1_CPHA | SPI_CR1_CPOL | SPI_CR1_BR_MASK | - SPI_CR1_LSBFIRST | SPI_CR1_RXONLY | SPI_CR1_DFF | - SPI_CR1_BIDIOE | SPI_CR1_BIDIMODE; - setbits = SPI_CR1_MSTR | SPI_CR1_SSI | SPI_CR1_SSM; - spi_modifycr1(priv, setbits, clrbits); -#endif - - priv->frequency = 0; - priv->nbits = 8; - priv->mode = SPIDEV_MODE0; - - /* Select a default frequency of approx. 400KHz */ - - spi_setfrequency((struct spi_dev_s *)priv, 400000); - - /* CRCPOLY configuration */ - - spi_putreg(priv, STM32_SPI_CRCPR_OFFSET, 7); - -#ifdef CONFIG_STM32_SPI_DMA - if (priv->rxch && priv->txch) - { - /* Get DMA channels. NOTE: stm32_dmachannel() will always assign the - * DMA channel. If the channel is not available, then - * stm32_dmachannel() will block and wait until the channel becomes - * available. - * WARNING: If you have another device sharing a DMA channel with - * SPI and the code never releases that channel, then the call to - * stm32_dmachannel() will hang forever in this function! - * Don't let your design do that! - */ - - priv->rxdma = stm32_dmachannel(priv->rxch); - priv->txdma = stm32_dmachannel(priv->txch); - DEBUGASSERT(priv->rxdma && priv->txdma); - - spi_modifycr2(priv, SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN, 0); - } - else - { - priv->rxdma = NULL; - priv->txdma = NULL; - } -#endif - - /* Enable SPI */ - - spi_modifycr1(priv, SPI_CR1_SPE, 0); -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_spibus_initialize - * - * Description: - * Initialize the selected SPI bus - * - * Input Parameters: - * Port number (for hardware that has multiple SPI interfaces) - * - * Returned Value: - * Valid SPI device structure reference on success; a NULL on failure - * - ****************************************************************************/ - -struct spi_dev_s *stm32_spibus_initialize(int bus) -{ - struct stm32_spidev_s *priv = NULL; - - irqstate_t flags = enter_critical_section(); - -#ifdef CONFIG_STM32_SPI1 - if (bus == 1) - { - /* Select SPI1 */ - - priv = &g_spi1dev; - - /* Only configure if the bus is not already configured */ - - if (!priv->initialized) - { - /* Configure SPI1 pins: SCK, MISO, and MOSI */ - - stm32_configgpio(GPIO_SPI1_SCK); - stm32_configgpio(GPIO_SPI1_MISO); - stm32_configgpio(GPIO_SPI1_MOSI); - - /* Set up default configuration: Master, 8-bit, etc. */ - - spi_bus_initialize(priv); - priv->initialized = true; - } - } - else -#endif -#ifdef CONFIG_STM32_SPI2 - if (bus == 2) - { - /* Select SPI2 */ - - priv = &g_spi2dev; - - /* Only configure if the bus is not already configured */ - - if (!priv->initialized) - { - /* Configure SPI2 pins: SCK, MISO, and MOSI */ - - stm32_configgpio(GPIO_SPI2_SCK); - stm32_configgpio(GPIO_SPI2_MISO); - stm32_configgpio(GPIO_SPI2_MOSI); - - /* Set up default configuration: Master, 8-bit, etc. */ - - spi_bus_initialize(priv); - priv->initialized = true; - } - } - else -#endif -#ifdef CONFIG_STM32_SPI3 - if (bus == 3) - { - /* Select SPI3 */ - - priv = &g_spi3dev; - - /* Only configure if the bus is not already configured */ - - if (!priv->initialized) - { - /* Configure SPI3 pins: SCK, MISO, and MOSI */ - - stm32_configgpio(GPIO_SPI3_SCK); - stm32_configgpio(GPIO_SPI3_MISO); - stm32_configgpio(GPIO_SPI3_MOSI); - - /* Set up default configuration: Master, 8-bit, etc. */ - - spi_bus_initialize(priv); - priv->initialized = true; - } - } - else -#endif -#ifdef CONFIG_STM32_SPI4 - if (bus == 4) - { - /* Select SPI4 */ - - priv = &g_spi4dev; - - /* Only configure if the bus is not already configured */ - - if (!priv->initialized) - { - /* Configure SPI4 pins: SCK, MISO, and MOSI */ - - stm32_configgpio(GPIO_SPI4_SCK); - stm32_configgpio(GPIO_SPI4_MISO); - stm32_configgpio(GPIO_SPI4_MOSI); - - /* Set up default configuration: Master, 8-bit, etc. */ - - spi_bus_initialize(priv); - priv->initialized = true; - } - } - else -#endif -#ifdef CONFIG_STM32_SPI5 - if (bus == 5) - { - /* Select SPI5 */ - - priv = &g_spi5dev; - - /* Only configure if the bus is not already configured */ - - if (!priv->initialized) - { - /* Configure SPI5 pins: SCK, MISO, and MOSI */ - - stm32_configgpio(GPIO_SPI5_SCK); - stm32_configgpio(GPIO_SPI5_MISO); - stm32_configgpio(GPIO_SPI5_MOSI); - - /* Set up default configuration: Master, 8-bit, etc. */ - - spi_bus_initialize(priv); - priv->initialized = true; - } - } - else -#endif -#ifdef CONFIG_STM32_SPI6 - if (bus == 6) - { - /* Select SPI6 */ - - priv = &g_spi6dev; - - /* Only configure if the bus is not already configured */ - - if (!priv->initialized) - { - /* Configure SPI6 pins: SCK, MISO, and MOSI */ - - stm32_configgpio(GPIO_SPI6_SCK); - stm32_configgpio(GPIO_SPI6_MISO); - stm32_configgpio(GPIO_SPI6_MOSI); - - /* Set up default configuration: Master, 8-bit, etc. */ - - spi_bus_initialize(priv); - priv->initialized = true; - } - } - else -#endif - { - spierr("ERROR: Unsupported SPI bus: %d\n", bus); - } - - leave_critical_section(flags); - return (struct spi_dev_s *)priv; -} - -#endif /* CONFIG_STM32_SPI1 || CONFIG_STM32_SPI2 || CONFIG_STM32_SPI3 || - * CONFIG_STM32_SPI4 || CONFIG_STM32_SPI5 || CONFIG_STM32_SPI6 - */ diff --git a/arch/arm/src/stm32/stm32_spi.h b/arch/arm/src/stm32/stm32_spi.h deleted file mode 100644 index 13a48fb92cea0..0000000000000 --- a/arch/arm/src/stm32/stm32_spi.h +++ /dev/null @@ -1,209 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_spi.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32_STM32_SPI_H -#define __ARCH_ARM_SRC_STM32_STM32_SPI_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include "chip.h" -#include "hardware/stm32_spi.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#ifndef __ASSEMBLY__ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -struct spi_dev_s; - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_spibus_initialize - * - * Description: - * Initialize the selected SPI bus - * - * Input Parameters: - * bus number (for hardware that has multiple SPI interfaces) - * - * Returned Value: - * Valid SPI device structure reference on success; a NULL on failure - * - ****************************************************************************/ - -struct spi_dev_s *stm32_spibus_initialize(int bus); - -/**************************************************************************** - * Name: stm32_spi1/2/...select and stm32_spi1/2/...status - * - * Description: - * The external functions, stm32_spi1/2/...select, stm32_spi1/2/...status, - * and stm32_spi1/2/...cmddata must be provided by board-specific logic. - * These are implementations of the select, status, and cmddata methods of - * the SPI interface defined by struct spi_ops_s (see - * include/nuttx/spi/spi.h). All other methods (including - * stm32_spibus_initialize()) are provided by common STM32 logic. To use - * this common SPI logic on your board: - * - * 1. Provide logic in stm32_boardinitialize() to configure SPI chip - * select pins. - * 2. Provide stm32_spi1/2/...select() and stm32_spi1/2/...status() - * functions in your board-specific logic. These functions will - * perform chip selection and status operations using GPIOs in the way - * your board is configured. - * 3. If CONFIG_SPI_CMDDATA is defined in your NuttX configuration file, - * then provide stm32_spi1/2/...cmddata() functions in your board- - * specific logic. These functions will perform cmd/data selection - * operations using GPIOs in the way your board is configured. - * 4. Add a calls to stm32_spibus_initialize() in your low level - * application initialization logic - * 5. The handle returned by stm32_spibus_initialize() may then be used to - * bind the SPI driver to higher level logic (e.g., calling - * mmcsd_spislotinitialize(), for example, will bind the SPI driver to - * the SPI MMC/SD driver). - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_SPI1 -void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, - bool selected); -uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid); -int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); -#endif - -#ifdef CONFIG_STM32_SPI2 -void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid, - bool selected); -uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid); -int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); -#endif - -#ifdef CONFIG_STM32_SPI3 -void stm32_spi3select(struct spi_dev_s *dev, uint32_t devid, - bool selected); -uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid); -int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); -#endif - -#ifdef CONFIG_STM32_SPI4 -void stm32_spi4select(struct spi_dev_s *dev, uint32_t devid, - bool selected); -uint8_t stm32_spi4status(struct spi_dev_s *dev, uint32_t devid); -int stm32_spi4cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); -#endif - -#ifdef CONFIG_STM32_SPI5 -void stm32_spi5select(struct spi_dev_s *dev, uint32_t devid, - bool selected); -uint8_t stm32_spi5status(struct spi_dev_s *dev, uint32_t devid); -int stm32_spi5cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); -#endif - -#ifdef CONFIG_STM32_SPI6 -void stm32_spi6select(struct spi_dev_s *dev, uint32_t devid, - bool selected); -uint8_t stm32_spi6status(struct spi_dev_s *dev, uint32_t devid); -int stm32_spi6cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); -#endif - -/**************************************************************************** - * Name: stm32_spi1/2/...register - * - * Description: - * If the board supports a card detect callback to inform the SPI-based - * MMC/SD driver when an SD card is inserted or removed, then - * CONFIG_SPI_CALLBACK should be defined and the following function(s) - * must be implemented. These functions implements the registercallback - * method of the SPI interface (see include/nuttx/spi/spi.h for details) - * - * Input Parameters: - * dev - Device-specific state data - * callback - The function to call on the media change - * arg - A caller provided value to return with the callback - * - * Returned Value: - * 0 on success; negated errno on failure. - * - ****************************************************************************/ - -#ifdef CONFIG_SPI_CALLBACK -#ifdef CONFIG_STM32_SPI1 -int stm32_spi1register(struct spi_dev_s *dev, spi_mediachange_t callback, - void *arg); -#endif - -#ifdef CONFIG_STM32_SPI2 -int stm32_spi2register(struct spi_dev_s *dev, spi_mediachange_t callback, - void *arg); -#endif - -#ifdef CONFIG_STM32_SPI3 -int stm32_spi3register(struct spi_dev_s *dev, spi_mediachange_t callback, - void *arg); -#endif - -#ifdef CONFIG_STM32_SPI4 -int stm32_spi4register(struct spi_dev_s *dev, spi_mediachange_t callback, - void *arg); -#endif - -#ifdef CONFIG_STM32_SPI5 -int stm32_spi5register(struct spi_dev_s *dev, spi_mediachange_t callback, - void *arg); -#endif - -#ifdef CONFIG_STM32_SPI6 -int stm32_spi6register(struct spi_dev_s *dev, spi_mediachange_t callback, - void *arg); -#endif -#endif - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32_STM32_SPI_H */ diff --git a/arch/arm/src/stm32/stm32_start.c b/arch/arm/src/stm32/stm32_start.c deleted file mode 100644 index e4abdb7d3e980..0000000000000 --- a/arch/arm/src/stm32/stm32_start.c +++ /dev/null @@ -1,213 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_start.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include - -#include "arch/board/board.h" -#include "arm_internal.h" -#include "itm_syslog.h" -#include "nvic.h" -#include "mpu.h" - -#include "stm32.h" -#include "stm32_gpio.h" -#include "stm32_userspace.h" -#include "stm32_start.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* .data is positioned first in the primary RAM followed immediately by .bss. - * The IDLE thread stack lies just after .bss and has size give by - * CONFIG_IDLETHREAD_STACKSIZE; The heap then begins just after the IDLE. - * ARM EABI requires 64 bit stack alignment. - */ - -#define HEAP_BASE ((uintptr_t)_ebss + CONFIG_IDLETHREAD_STACKSIZE) - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/* g_idle_topstack: _sbss is the start of the BSS region as defined by the - * linker script. _ebss lies at the end of the BSS region. The idle task - * stack starts at the end of BSS and is of size CONFIG_IDLETHREAD_STACKSIZE. - * The IDLE thread is the thread that the system boots on and, eventually, - * becomes the IDLE, do nothing task that runs only when there is nothing - * else to run. The heap continues from there until the end of memory. - * g_idle_topstack is a read-only variable the provides this computed - * address. - */ - -const uintptr_t g_idle_topstack = HEAP_BASE; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: showprogress - * - * Description: - * Print a character on the UART to show boot status. - * - ****************************************************************************/ - -#ifdef CONFIG_DEBUG_FEATURES -# define showprogress(c) arm_lowputc(c) -#else -# define showprogress(c) -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -#ifdef CONFIG_ARMV7M_STACKCHECK -/* we need to get r10 set before we can allow instrumentation calls */ - -void __start(void) noinstrument_function; -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: __start - * - * Description: - * This is the reset entry point. - * - ****************************************************************************/ - -void __start(void) -{ - const uint32_t *src; - uint32_t *dest; - -#ifdef CONFIG_ARMV7M_STACKCHECK - /* Set the stack limit before we attempt to call any functions */ - - __asm__ volatile("sub r10, sp, %0" : : - "r"(CONFIG_IDLETHREAD_STACKSIZE - 64) :); -#endif - - /* If enabled reset the MPU */ - - mpu_early_reset(); - - /* Configure the UART so that we can get debug output as soon as possible */ - - stm32_clockconfig(); - arm_fpuconfig(); - stm32_lowsetup(); - stm32_gpioinit(); - showprogress('A'); - - /* Clear .bss. We'll do this inline (vs. calling memset) just to be - * certain that there are no issues with the state of global variables. - */ - - for (dest = (uint32_t *)_START_BSS; dest < (uint32_t *)_END_BSS; ) - { - *dest++ = 0; - } - - showprogress('B'); - - /* Move the initialized data section from his temporary holding spot in - * FLASH into the correct place in SRAM. The correct place in SRAM is - * give by _sdata and _edata. The temporary location is in FLASH at the - * end of all of the other read-only data (.text, .rodata) at _eronly. - */ - - for (src = (const uint32_t *)_DATA_INIT, - dest = (uint32_t *)_START_DATA; dest < (uint32_t *)_END_DATA; - ) - { - *dest++ = *src++; - } - - showprogress('C'); - -#ifdef CONFIG_ARMV7M_STACKCHECK - arm_stack_check_init(); -#endif - -#ifdef CONFIG_ARCH_PERF_EVENTS - up_perf_init((void *)STM32_SYSCLK_FREQUENCY); -#endif - -#ifdef CONFIG_ARMV7M_ITMSYSLOG - /* Perform ARMv7-M ITM SYSLOG initialization */ - - itm_syslog_initialize(); -#endif - - /* Perform early serial initialization */ - -#ifdef USE_EARLYSERIALINIT - arm_earlyserialinit(); -#endif - showprogress('D'); - - /* For the case of the separate user-/kernel-space build, perform whatever - * platform specific initialization of the user memory is required. - * Normally this just means initializing the user space .data and .bss - * segments. - */ - -#ifdef CONFIG_BUILD_PROTECTED - stm32_userspace(); - showprogress('E'); -#endif - - /* Initialize onboard resources */ - - stm32_boardinitialize(); - showprogress('F'); - - /* Then start NuttX */ - - showprogress('\r'); - showprogress('\n'); - - nx_start(); - - /* Shouldn't get here */ - -#ifndef CONFIG_DISABLE_IDLE_LOOP - for (; ; ); -#endif -} diff --git a/arch/arm/src/stm32/stm32_start.h b/arch/arm/src/stm32/stm32_start.h deleted file mode 100644 index 4d0e326dc491e..0000000000000 --- a/arch/arm/src/stm32/stm32_start.h +++ /dev/null @@ -1,49 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_start.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32_STM32_START_H -#define __ARCH_ARM_SRC_STM32_STM32_START_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_boardinitialize - * - * Description: - * All STM32 architectures must provide the following entry point. - * This entry point is called early in the initialization -- after - * clocking and memory have been configured but before caches have been - * enabled and before any devices have been initialized. - * - ****************************************************************************/ - -void stm32_boardinitialize(void); - -#endif /* __ARCH_ARM_SRC_STM32_STM32_START_H */ diff --git a/arch/arm/src/stm32/stm32_syscfg.h b/arch/arm/src/stm32/stm32_syscfg.h deleted file mode 100644 index 74d049711a61f..0000000000000 --- a/arch/arm/src/stm32/stm32_syscfg.h +++ /dev/null @@ -1,53 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_syscfg.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32_STM32_SYSCFG_H -#define __ARCH_ARM_SRC_STM32_STM32_SYSCFG_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include "chip.h" - -#if defined(CONFIG_STM32_STM32L15XX) -# include "hardware/stm32l15xxx_syscfg.h" -#elif defined(CONFIG_STM32_STM32F20XX) -# include "hardware/stm32f20xxx_syscfg.h" -#elif defined(CONFIG_STM32_STM32F30XX) -# include "hardware/stm32f30xxx_syscfg.h" -#elif defined(CONFIG_STM32_STM32F33XX) -# include "hardware/stm32f33xxx_syscfg.h" -#elif defined(CONFIG_STM32_STM32F37XX) -# include "hardware/stm32f37xxx_syscfg.h" -#elif defined(CONFIG_STM32_STM32F4XXX) -# include "hardware/stm32f40xxx_syscfg.h" -#elif defined(CONFIG_STM32_STM32G4XXX) -# include "hardware/stm32g4xxxx_syscfg.h" -#endif - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#endif /* __ARCH_ARM_SRC_STM32_STM32_SYSCFG_H */ diff --git a/arch/arm/src/stm32/stm32_tickless.c b/arch/arm/src/stm32/stm32_tickless.c deleted file mode 100644 index 3cd076bf1d742..0000000000000 --- a/arch/arm/src/stm32/stm32_tickless.c +++ /dev/null @@ -1,974 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_tickless.c - * - * SPDX-License-Identifier: BSD-3-Clause - * SPDX-FileCopyrightText: 2016-2017 Gregory Nutt. All rights reserved. - * SPDX-FileCopyrightText: 2017 Ansync Labs. All rights reserved. - * SPDX-FileContributor: Gregory Nutt - * SPDX-FileContributor: Konstantin Berezenko - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -/**************************************************************************** - * Tickless OS Support. - * - * When CONFIG_SCHED_TICKLESS is enabled, all support for timer interrupts - * is suppressed and the platform specific code is expected to provide the - * following custom functions. - * - * void up_timer_initialize(void): Initializes the timer facilities. - * Called early in the initialization sequence (by up_initialize()). - * int up_timer_gettime(struct timespec *ts): Returns the current - * time from the platform specific time source. - * int up_timer_cancel(void): Cancels the interval timer. - * int up_timer_start(const struct timespec *ts): Start (or re-starts) - * the interval timer. - * - * The RTOS will provide the following interfaces for use by the platform- - * specific interval timer implementation: - * - * void nxsched_process_timer(void): Called by the platform-specific - * logic when the interval timer expires. - * - ****************************************************************************/ - -/**************************************************************************** - * STM32 Timer Usage - * - * This implementation uses one timer: A free running timer to provide - * the current time and a capture/compare channel for timed-events. - * - * BASIC timers that are found on some STM32 chips (timers 6 and 7) are - * incompatible with this implementation because they don't have capture/ - * compare channels. There are two interrupts generated from our timer, - * the overflow interrupt which drives the timing handler and the capture/ - * compare interrupt which drives the interval handler. There are some low - * level timer control functions implemented here because the API of - * stm32_tim.c does not provide adequate control over capture/compare - * interrupts. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include - -#include -#include - -#include "arm_internal.h" -#include "stm32_tim.h" - -#ifdef CONFIG_SCHED_TICKLESS - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Only TIM2 and TIM5 timers may be 32-bits in width - * - * Reference Table 2 of en.DM00042534.pdf - */ - -#undef HAVE_32BIT_TICKLESS - -#if (CONFIG_STM32_TICKLESS_TIMER == 2 && \ - !defined(STM32_STM32F10XX) && \ - !defined(STM32_STM32L15XX)) \ - || (CONFIG_STM32_TICKLESS_TIMER == 5 && \ - !defined(STM32_STM32F10XX)) - #define HAVE_32BIT_TICKLESS 1 -#endif - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -struct stm32_tickless_s -{ - uint8_t timer; /* The timer/counter in use */ - uint8_t channel; /* The timer channel to use for intervals */ - struct stm32_tim_dev_s *tch; /* Handle returned by stm32_tim_init() */ - uint32_t frequency; - uint32_t overflow; /* Timer counter overflow */ - volatile bool pending; /* True: pending task */ - uint32_t period; /* Interval period */ - uint32_t base; -}; - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -static struct stm32_tickless_s g_tickless; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_getreg16 - * - * Description: - * Get a 16-bit register value by offset - * - ****************************************************************************/ - -static inline uint16_t stm32_getreg16(uint8_t offset) -{ - return getreg16(g_tickless.base + offset); -} - -/**************************************************************************** - * Name: stm32_putreg16 - * - * Description: - * Put a 16-bit register value by offset - * - ****************************************************************************/ - -static inline void stm32_putreg16(uint8_t offset, uint16_t value) -{ - putreg16(value, g_tickless.base + offset); -} - -/**************************************************************************** - * Name: stm32_modifyreg16 - * - * Description: - * Modify a 16-bit register value by offset - * - ****************************************************************************/ - -static inline void stm32_modifyreg16(uint8_t offset, uint16_t clearbits, - uint16_t setbits) -{ - modifyreg16(g_tickless.base + offset, clearbits, setbits); -} - -/**************************************************************************** - * Name: stm32_tickless_enableint - ****************************************************************************/ - -static inline void stm32_tickless_enableint(int channel) -{ - stm32_modifyreg16(STM32_BTIM_DIER_OFFSET, 0, 1 << channel); -} - -/**************************************************************************** - * Name: stm32_tickless_disableint - ****************************************************************************/ - -static inline void stm32_tickless_disableint(int channel) -{ - stm32_modifyreg16(STM32_BTIM_DIER_OFFSET, 1 << channel, 0); -} - -/**************************************************************************** - * Name: stm32_tickless_ackint - ****************************************************************************/ - -static inline void stm32_tickless_ackint(int channel) -{ - stm32_putreg16(STM32_BTIM_SR_OFFSET, ~(1 << channel)); -} - -/**************************************************************************** - * Name: stm32_tickless_getint - ****************************************************************************/ - -static inline uint16_t stm32_tickless_getint(void) -{ - return stm32_getreg16(STM32_BTIM_SR_OFFSET); -} - -/**************************************************************************** - * Name: stm32_tickless_setchannel - ****************************************************************************/ - -static int stm32_tickless_setchannel(uint8_t channel) -{ - uint16_t ccmr_orig = 0; - uint16_t ccmr_val = 0; - uint16_t ccmr_mask = 0xff; - uint16_t ccer_val = stm32_getreg16(STM32_GTIM_CCER_OFFSET); - uint8_t ccmr_offset = STM32_GTIM_CCMR1_OFFSET; - - /* Further we use range as 0..3; if channel=0 it will also overflow here */ - - if (--channel > 4) - { - return -EINVAL; - } - - /* Assume that channel is disabled and polarity is active high */ - - ccer_val &= ~((GTIM_CCER_CC1P | GTIM_CCER_CC1E) << - GTIM_CCER_CCXBASE(channel)); - - /* This function is not supported on basic timers. To enable or - * disable it, simply set its clock to valid frequency or zero. - */ - -#if STM32_NBTIM > 0 - if (g_tickless.base == STM32_TIM6_BASE -#endif -#if STM32_NBTIM > 1 - || g_tickless.base == STM32_TIM7_BASE -#endif -#if STM32_NBTIM > 0 - ) - { - return -EINVAL; - } -#endif - - /* Frozen mode because we don't want to change the GPIO, preload register - * disabled. - */ - - ccmr_val = (ATIM_CCMR_MODE_FRZN << ATIM_CCMR1_OC1M_SHIFT); - - /* Set polarity */ - - ccer_val |= ATIM_CCER_CC1P << GTIM_CCER_CCXBASE(channel); - - /* Define its position (shift) and get register offset */ - - if ((channel & 1) != 0) - { - ccmr_val <<= 8; - ccmr_mask <<= 8; - } - - if (channel > 1) - { - ccmr_offset = STM32_GTIM_CCMR2_OFFSET; - } - - ccmr_orig = stm32_getreg16(ccmr_offset); - ccmr_orig &= ~ccmr_mask; - ccmr_orig |= ccmr_val; - stm32_putreg16(ccmr_offset, ccmr_orig); - stm32_putreg16(STM32_GTIM_CCER_OFFSET, ccer_val); - - return OK; -} - -/**************************************************************************** - * Name: stm32_interval_handler - * - * Description: - * Called when the timer counter matches the compare register - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - * Assumptions: - * Called early in the initialization sequence before any special - * concurrency protections are required. - * - ****************************************************************************/ - -static void stm32_interval_handler(void) -{ - tmrinfo("Expired...\n"); - - /* Disable the compare interrupt now. */ - - stm32_tickless_disableint(g_tickless.channel); - stm32_tickless_ackint(g_tickless.channel); - - g_tickless.pending = false; - - nxsched_process_timer(); -} - -/**************************************************************************** - * Name: stm32_timing_handler - * - * Description: - * Timer interrupt callback. When the freerun timer counter overflows, - * this interrupt will occur. We will just increment an overflow count. - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void stm32_timing_handler(void) -{ - g_tickless.overflow++; - - STM32_TIM_ACKINT(g_tickless.tch, GTIM_SR_UIF); -} - -/**************************************************************************** - * Name: stm32_tickless_handler - * - * Description: - * Generic interrupt handler for this timer. It checks the source of the - * interrupt and fires the appropriate handler. - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -static int stm32_tickless_handler(int irq, void *context, void *arg) -{ - int interrupt_flags = stm32_tickless_getint(); - - if (interrupt_flags & ATIM_SR_UIF) - { - stm32_timing_handler(); - } - - if (interrupt_flags & (1 << g_tickless.channel)) - { - stm32_interval_handler(); - } - - return OK; -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: up_timer_initialize - * - * Description: - * Initializes all platform-specific timer facilities. This function is - * called early in the initialization sequence by up_initialize(). - * On return, the current up-time should be available from - * up_timer_gettime() and the interval timer is ready for use (but not - * actively timing. - * - * Provided by platform-specific code and called from the architecture- - * specific logic. - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - * Assumptions: - * Called early in the initialization sequence before any special - * concurrency protections are required. - * - ****************************************************************************/ - -void up_timer_initialize(void) -{ - switch (CONFIG_STM32_TICKLESS_TIMER) - { -#ifdef CONFIG_STM32_TIM1 - case 1: - g_tickless.base = STM32_TIM1_BASE; - break; -#endif - -#ifdef CONFIG_STM32_TIM2 - case 2: - g_tickless.base = STM32_TIM2_BASE; - break; -#endif - -#ifdef CONFIG_STM32_TIM3 - case 3: - g_tickless.base = STM32_TIM3_BASE; - break; -#endif - -#ifdef CONFIG_STM32_TIM4 - case 4: - g_tickless.base = STM32_TIM4_BASE; - break; -#endif -#ifdef CONFIG_STM32_TIM5 - case 5: - g_tickless.base = STM32_TIM5_BASE; - break; -#endif - -#ifdef CONFIG_STM32_TIM6 - case 6: - - /* Basic timers not supported by this implementation */ - - DEBUGPANIC(); - break; -#endif - -#ifdef CONFIG_STM32_TIM7 - case 7: - - /* Basic timers not supported by this implementation */ - - DEBUGPANIC(); - break; -#endif - -#ifdef CONFIG_STM32_TIM8 - case 8: - g_tickless.base = STM32_TIM8_BASE; - break; -#endif - -#ifdef CONFIG_STM32_TIM9 - case 9: - g_tickless.base = STM32_TIM9_BASE; - break; -#endif -#ifdef CONFIG_STM32_TIM10 - case 10: - g_tickless.base = STM32_TIM10_BASE; - break; -#endif - -#ifdef CONFIG_STM32_TIM11 - case 11: - g_tickless.base = STM32_TIM11_BASE; - break; -#endif -#ifdef CONFIG_STM32_TIM12 - case 12: - g_tickless.base = STM32_TIM12_BASE; - break; -#endif -#ifdef CONFIG_STM32_TIM13 - case 13: - g_tickless.base = STM32_TIM13_BASE; - break; -#endif - -#ifdef CONFIG_STM32_TIM14 - case 14: - g_tickless.base = STM32_TIM14_BASE; - break; -#endif -#ifdef CONFIG_STM32_TIM15 - case 15: - g_tickless.base = STM32_TIM15_BASE; - break; -#endif - -#ifdef CONFIG_STM32_TIM16 - case 16: - g_tickless.base = STM32_TIM16_BASE; - break; -#endif - -#ifdef CONFIG_STM32_TIM17 - case 17: - g_tickless.base = STM32_TIM17_BASE; - break; -#endif - - default: - DEBUGPANIC(); - } - - /* Get the TC frequency that corresponds to the requested resolution */ - - g_tickless.frequency = USEC_PER_SEC / (uint32_t)CONFIG_USEC_PER_TICK; - g_tickless.timer = CONFIG_STM32_TICKLESS_TIMER; - g_tickless.channel = CONFIG_STM32_TICKLESS_CHANNEL; - g_tickless.pending = false; - g_tickless.period = 0; - g_tickless.overflow = 0; - - tmrinfo("timer=%d channel=%d frequency=%lu Hz\n", - g_tickless.timer, g_tickless.channel, g_tickless.frequency); - - g_tickless.tch = stm32_tim_init(g_tickless.timer); - if (!g_tickless.tch) - { - tmrerr("ERROR: Failed to allocate TIM%d\n", g_tickless.timer); - DEBUGPANIC(); - } - - STM32_TIM_SETCLOCK(g_tickless.tch, g_tickless.frequency); - - /* Set up to receive the callback when the counter overflow occurs */ - - STM32_TIM_SETISR(g_tickless.tch, stm32_tickless_handler, NULL, 0); - - /* Initialize interval to zero */ - - STM32_TIM_SETCOMPARE(g_tickless.tch, g_tickless.channel, 0); - - /* Setup compare channel for the interval timing */ - - stm32_tickless_setchannel(g_tickless.channel); - - /* Set timer period */ - -#ifdef HAVE_32BIT_TICKLESS - STM32_TIM_SETPERIOD(g_tickless.tch, UINT32_MAX); -#ifdef CONFIG_SCHED_TICKLESS_LIMIT_MAX_SLEEP - g_oneshot_maxticks = UINT32_MAX; -#endif -#else - STM32_TIM_SETPERIOD(g_tickless.tch, UINT16_MAX); -#ifdef CONFIG_SCHED_TICKLESS_LIMIT_MAX_SLEEP - g_oneshot_maxticks = UINT16_MAX; -#endif -#endif - - /* Initialize the counter */ - - STM32_TIM_SETMODE(g_tickless.tch, STM32_TIM_MODE_UP); - - /* Start the timer */ - - STM32_TIM_ACKINT(g_tickless.tch, ~0); - STM32_TIM_ENABLEINT(g_tickless.tch, GTIM_DIER_UIE); -} - -/**************************************************************************** - * Name: up_timer_gettime - * - * Description: - * Return the elapsed time since power-up (or, more correctly, since - * up_timer_initialize() was called). This function is functionally - * equivalent to: - * - * int clock_gettime(clockid_t clockid, struct timespec *ts); - * - * when clockid is CLOCK_MONOTONIC. - * - * This function provides the basis for reporting the current time and - * also is used to eliminate error build-up from small errors in interval - * time calculations. - * - * Provided by platform-specific code and called from the RTOS base code. - * - * Input Parameters: - * ts - Provides the location in which to return the up-time. - * - * Returned Value: - * Zero (OK) is returned on success; a negated errno value is returned on - * any failure. - * - * Assumptions: - * Called from the normal tasking context. The implementation must - * provide whatever mutual exclusion is necessary for correct operation. - * This can include disabling interrupts in order to assure atomic register - * operations. - * - ****************************************************************************/ - -int up_timer_gettime(struct timespec *ts) -{ - uint64_t usec; - uint32_t counter; - uint32_t verify; - uint32_t overflow; - uint32_t sec; - int pending; - irqstate_t flags; - - DEBUGASSERT(ts); - - /* Timer not initialized yet, return zero */ - - if (g_tickless.tch == 0) - { - ts->tv_nsec = 0; - ts->tv_sec = 0; - return OK; - } - - /* Temporarily disable the overflow counter. NOTE that we have to be - * careful here because stm32_tc_getpending() will reset the pending - * interrupt status. If we do not handle the overflow here then, it will - * be lost. - */ - - flags = enter_critical_section(); - - overflow = g_tickless.overflow; - counter = STM32_TIM_GETCOUNTER(g_tickless.tch); - pending = STM32_TIM_CHECKINT(g_tickless.tch, GTIM_SR_UIF); - verify = STM32_TIM_GETCOUNTER(g_tickless.tch); - - /* If an interrupt was pending before we re-enabled interrupts, - * then the overflow needs to be incremented. - */ - - if (pending) - { - STM32_TIM_ACKINT(g_tickless.tch, GTIM_SR_UIF); - - /* Increment the overflow count and use the value of the - * guaranteed to be AFTER the overflow occurred. - */ - - overflow++; - counter = verify; - - /* Update tickless overflow counter. */ - - g_tickless.overflow = overflow; - } - - leave_critical_section(flags); - - tmrinfo("counter=%lu (%lu) overflow=%lu, pending=%i\n", - (unsigned long)counter, (unsigned long)verify, - (unsigned long)overflow, pending); - tmrinfo("frequency=%lu\n", g_tickless.frequency); - - /* Convert the whole thing to units of microseconds. - * - * frequency = ticks / second - * seconds = ticks * frequency - * usecs = (ticks * USEC_PER_SEC) / frequency; - */ -#ifdef HAVE_32BIT_TICKLESS - usec = ((((uint64_t)overflow << 32) + (uint64_t)counter) * USEC_PER_SEC) / - g_tickless.frequency; -#else - usec = ((((uint64_t)overflow << 16) + (uint64_t)counter) * USEC_PER_SEC) / - g_tickless.frequency; -#endif - - /* And return the value of the timer */ - - sec = (uint32_t)(usec / USEC_PER_SEC); - ts->tv_sec = sec; - ts->tv_nsec = (usec - (sec * USEC_PER_SEC)) * NSEC_PER_USEC; - - tmrinfo("usec=%llu ts=(%jd, %ld)\n", - usec, (intmax_t)ts->tv_sec, ts->tv_nsec); - - return OK; -} - -#ifdef CONFIG_CLOCK_TIMEKEEPING - -/**************************************************************************** - * Name: up_timer_gettick - * - * Description: - * To be provided - * - * Input Parameters: - * cycles - 64-bit return value - * - * Returned Value: - * None - * - ****************************************************************************/ - -int up_timer_gettick(clock_t *ticks) -{ - *ticks = STM32_TIM_GETCOUNTER(g_tickless.tch); - return OK; -} - -/**************************************************************************** - * Name: up_timer_getmask - * - * Description: - * To be provided - * - * Input Parameters: - * mask - Location to return the 64-bit mask - * - * Returned Value: - * None - * - ****************************************************************************/ - -void up_timer_getmask(clock_t *mask) -{ - DEBUGASSERT(mask != NULL); -#ifdef HAVE_32BIT_TICKLESS - *mask = UINT32_MAX; -#else - *mask = UINT16_MAX; -#endif -} - -#endif /* CONFIG_CLOCK_TIMEKEEPING */ - -/**************************************************************************** - * Name: up_timer_cancel - * - * Description: - * Cancel the interval timer and return the time remaining on the timer. - * These two steps need to be as nearly atomic as possible. - * nxsched_process_timer() will not be called unless the timer is - * restarted with up_timer_start(). - * - * If, as a race condition, the timer has already expired when this - * function is called, then that pending interrupt must be cleared so - * that up_timer_start() and the remaining time of zero should be - * returned. - * - * NOTE: This function may execute at a high rate with no timer running (as - * when pre-emption is enabled and disabled). - * - * Provided by platform-specific code and called from the RTOS base code. - * - * Input Parameters: - * ts - Location to return the remaining time. Zero should be returned - * if the timer is not active. ts may be zero in which case the - * time remaining is not returned. - * - * Returned Value: - * Zero (OK) is returned on success. A call to up_timer_cancel() when - * the timer is not active should also return success; a negated errno - * value is returned on any failure. - * - * Assumptions: - * May be called from interrupt level handling or from the normal tasking - * level. Interrupts may need to be disabled internally to assure - * non-reentrancy. - * - ****************************************************************************/ - -int up_timer_cancel(struct timespec *ts) -{ - irqstate_t flags; - uint64_t usec; - uint64_t sec; - uint64_t nsec; - uint32_t count; - uint32_t period; - - /* Was the timer running? */ - - flags = enter_critical_section(); - if (!g_tickless.pending) - { - /* No.. Just return zero timer remaining and successful cancellation. - * This function may execute at a high rate with no timer running - * (as when pre-emption is enabled and disabled). - */ - - if (ts) - { - ts->tv_sec = 0; - ts->tv_nsec = 0; - } - - leave_critical_section(flags); - return OK; - } - - /* Yes.. Get the timer counter and period registers and disable the compare - * interrupt. - */ - - tmrinfo("Cancelling...\n"); - - /* Disable the interrupt. */ - - stm32_tickless_disableint(g_tickless.channel); - - count = STM32_TIM_GETCOUNTER(g_tickless.tch); - period = g_tickless.period; - - g_tickless.pending = false; - leave_critical_section(flags); - - /* Did the caller provide us with a location to return the time - * remaining? - */ - - if (ts != NULL) - { - /* Yes.. then calculate and return the time remaining on the - * oneshot timer. - */ - - tmrinfo("period=%lu count=%lu\n", - (unsigned long)period, (unsigned long)count); - -#ifndef HAVE_32BIT_TICKLESS - if (count > period) - { - /* Handle rollover */ - - period += UINT16_MAX; - } - else if (count == period) -#else - if (count >= period) -#endif - { - /* No time remaining */ - - ts->tv_sec = 0; - ts->tv_nsec = 0; - return OK; - } - - /* The total time remaining is the difference. Convert that - * to units of microseconds. - * - * frequency = ticks / second - * seconds = ticks * frequency - * usecs = (ticks * USEC_PER_SEC) / frequency; - */ - - usec = (((uint64_t)(period - count)) * USEC_PER_SEC) / - g_tickless.frequency; - - /* Return the time remaining in the correct form */ - - sec = usec / USEC_PER_SEC; - nsec = ((usec) - (sec * USEC_PER_SEC)) * NSEC_PER_USEC; - - ts->tv_sec = sec; - ts->tv_nsec = nsec; - - tmrinfo("remaining (%jd, %ld)\n", - (intmax_t)ts->tv_sec, ts->tv_nsec); - } - - return OK; -} - -/**************************************************************************** - * Name: up_timer_start - * - * Description: - * Start the interval timer. nxsched_process_timer() will be - * called at the completion of the timeout (unless up_timer_cancel - * is called to stop the timing. - * - * Provided by platform-specific code and called from the RTOS base code. - * - * Input Parameters: - * ts - Provides the time interval until nxsched_process_timer() is - * called. - * - * Returned Value: - * Zero (OK) is returned on success; a negated errno value is returned on - * any failure. - * - * Assumptions: - * May be called from interrupt level handling or from the normal tasking - * level. Interrupts may need to be disabled internally to assure - * non-reentrancy. - * - ****************************************************************************/ - -int up_timer_start(const struct timespec *ts) -{ - uint64_t usec; - uint64_t period; - uint32_t count; - irqstate_t flags; - - tmrinfo("ts=(%jd, %ld)\n", - (intmax_t)ts->tv_sec, ts->tv_nsec); - DEBUGASSERT(ts); - DEBUGASSERT(g_tickless.tch); - - /* Was an interval already running? */ - - flags = enter_critical_section(); - if (g_tickless.pending) - { - /* Yes.. then cancel it */ - - tmrinfo("Already running... cancelling\n"); - up_timer_cancel(NULL); - } - - /* Express the delay in microseconds */ - - usec = ts->tv_sec * USEC_PER_SEC + - (ts->tv_nsec / NSEC_PER_USEC); - - /* Get the timer counter frequency and determine the number of counts need - * to achieve the requested delay. - * - * frequency = ticks / second - * ticks = seconds * frequency - * = (usecs * frequency) / USEC_PER_SEC; - */ - - period = (usec * (uint64_t)g_tickless.frequency) / USEC_PER_SEC; - count = STM32_TIM_GETCOUNTER(g_tickless.tch); - - tmrinfo("usec=%llu period=%08llx\n", usec, period); - - /* Set interval compare value. Rollover is fine, - * channel will trigger on the next period. - */ - -#ifdef HAVE_32BIT_TICKLESS - DEBUGASSERT(period <= UINT32_MAX); - g_tickless.period = (uint32_t)(period + count); -#else - DEBUGASSERT(period <= UINT16_MAX); - g_tickless.period = (uint16_t)(period + count); -#endif - - STM32_TIM_SETCOMPARE(g_tickless.tch, g_tickless.channel, - g_tickless.period); - - /* Enable interrupts. We should get the callback when the interrupt - * occurs. - */ - - stm32_tickless_ackint(g_tickless.channel); - stm32_tickless_enableint(g_tickless.channel); - - g_tickless.pending = true; - leave_critical_section(flags); - return OK; -} -#endif /* CONFIG_SCHED_TICKLESS */ diff --git a/arch/arm/src/stm32/stm32_tim.c b/arch/arm/src/stm32/stm32_tim.c deleted file mode 100644 index 71774e2898b47..0000000000000 --- a/arch/arm/src/stm32/stm32_tim.c +++ /dev/null @@ -1,1967 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_tim.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include -#include - -#include -#include -#include -#include -#include -#include - -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32.h" -#include "stm32_gpio.h" -#include "stm32_tim.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -/* Timer devices may be used for different purposes. Such special purposes - * include: - * - * - To generate modulated outputs for such things as motor control. If - * CONFIG_STM32_TIMn is defined then the CONFIG_STM32_TIMn_PWM may also be - * defined to indicate that the timer is intended to be used for pulsed - * output modulation. - * - * - To control periodic ADC input sampling. If CONFIG_STM32_TIMn is - * defined then CONFIG_STM32_TIMn_ADC may also be defined to indicate that - * timer "n" is intended to be used for that purpose. - * - * - To control periodic DAC outputs. If CONFIG_STM32_TIMn is defined then - * CONFIG_STM32_TIMn_DAC may also be defined to indicate that timer "n" is - * intended to be used for that purpose. - * - * - To use a Quadrature Encoder. If CONFIG_STM32_TIMn is defined then - * CONFIG_STM32_TIMn_QE may also be defined to indicate that timer "n" is - * intended to be used for that purpose. - * - * In any of these cases, the timer will not be used by this timer module. - */ - -#if defined(CONFIG_STM32_TIM1_PWM) || defined (CONFIG_STM32_TIM1_ADC) || \ - defined(CONFIG_STM32_TIM1_DAC) || defined(CONFIG_STM32_TIM1_QE) || \ - defined(CONFIG_STM32_TIM1_CAP) -# undef CONFIG_STM32_TIM1 -#endif -#if defined(CONFIG_STM32_TIM2_PWM) || defined (CONFIG_STM32_TIM2_ADC) || \ - defined(CONFIG_STM32_TIM2_DAC) || defined(CONFIG_STM32_TIM2_QE) || \ - defined(CONFIG_STM32_TIM2_CAP) -# undef CONFIG_STM32_TIM2 -#endif -#if defined(CONFIG_STM32_TIM3_PWM) || defined (CONFIG_STM32_TIM3_ADC) || \ - defined(CONFIG_STM32_TIM3_DAC) || defined(CONFIG_STM32_TIM3_QE) || \ - defined(CONFIG_STM32_TIM3_CAP) -# undef CONFIG_STM32_TIM3 -#endif -#if defined(CONFIG_STM32_TIM4_PWM) || defined (CONFIG_STM32_TIM4_ADC) || \ - defined(CONFIG_STM32_TIM4_DAC) || defined(CONFIG_STM32_TIM4_QE) || \ - defined(CONFIG_STM32_TIM4_CAP) -# undef CONFIG_STM32_TIM4 -#endif -#if defined(CONFIG_STM32_TIM5_PWM) || defined (CONFIG_STM32_TIM5_ADC) || \ - defined(CONFIG_STM32_TIM5_DAC) || defined(CONFIG_STM32_TIM5_QE) || \ - defined(CONFIG_STM32_TIM5_CAP) -# undef CONFIG_STM32_TIM5 -#endif -#if defined(CONFIG_STM32_TIM6_PWM) || defined (CONFIG_STM32_TIM6_ADC) || \ - defined(CONFIG_STM32_TIM6_DAC) || defined(CONFIG_STM32_TIM6_QE) -# undef CONFIG_STM32_TIM6 -#endif -#if defined(CONFIG_STM32_TIM7_PWM) || defined (CONFIG_STM32_TIM7_ADC) || \ - defined(CONFIG_STM32_TIM7_DAC) || defined(CONFIG_STM32_TIM7_QE) -# undef CONFIG_STM32_TIM7 -#endif -#if defined(CONFIG_STM32_TIM8_PWM) || defined (CONFIG_STM32_TIM8_ADC) || \ - defined(CONFIG_STM32_TIM8_DAC) || defined(CONFIG_STM32_TIM8_QE) || \ - defined(CONFIG_STM32_TIM8_CAP) -# undef CONFIG_STM32_TIM8 -#endif -#if defined(CONFIG_STM32_TIM9_PWM) || defined (CONFIG_STM32_TIM9_ADC) || \ - defined(CONFIG_STM32_TIM9_DAC) || defined(CONFIG_STM32_TIM9_QE) || \ - defined(CONFIG_STM32_TIM9_CAP) -# undef CONFIG_STM32_TIM9 -#endif -#if defined(CONFIG_STM32_TIM10_PWM) || defined (CONFIG_STM32_TIM10_ADC) || \ - defined(CONFIG_STM32_TIM10_DAC) || defined(CONFIG_STM32_TIM10_QE) || \ - defined(CONFIG_STM32_TIM10_CAP) -# undef CONFIG_STM32_TIM10 -#endif -#if defined(CONFIG_STM32_TIM11_PWM) || defined (CONFIG_STM32_TIM11_ADC) || \ - defined(CONFIG_STM32_TIM11_DAC) || defined(CONFIG_STM32_TIM11_QE) || \ - defined(CONFIG_STM32_TIM11_CAP) -# undef CONFIG_STM32_TIM11 -#endif -#if defined(CONFIG_STM32_TIM12_PWM) || defined (CONFIG_STM32_TIM12_ADC) || \ - defined(CONFIG_STM32_TIM12_DAC) || defined(CONFIG_STM32_TIM12_QE) || \ - defined(CONFIG_STM32_TIM12_CAP) -# undef CONFIG_STM32_TIM12 -#endif -#if defined(CONFIG_STM32_TIM13_PWM) || defined (CONFIG_STM32_TIM13_ADC) || \ - defined(CONFIG_STM32_TIM13_DAC) || defined(CONFIG_STM32_TIM13_QE) || \ - defined(CONFIG_STM32_TIM13_CAP) -# undef CONFIG_STM32_TIM13 -#endif -#if defined(CONFIG_STM32_TIM14_PWM) || defined (CONFIG_STM32_TIM14_ADC) || \ - defined(CONFIG_STM32_TIM14_DAC) || defined(CONFIG_STM32_TIM14_QE) || \ - defined(CONFIG_STM32_TIM14_CAP) -# undef CONFIG_STM32_TIM14 -#endif -#if defined(CONFIG_STM32_TIM15_PWM) || defined (CONFIG_STM32_TIM15_ADC) || \ - defined(CONFIG_STM32_TIM15_DAC) || defined(CONFIG_STM32_TIM15_QE) -# undef CONFIG_STM32_TIM15 -#endif -#if defined(CONFIG_STM32_TIM16_PWM) || defined (CONFIG_STM32_TIM16_ADC) || \ - defined(CONFIG_STM32_TIM16_DAC) || defined(CONFIG_STM32_TIM16_QE) -# undef CONFIG_STM32_TIM16 -#endif -#if defined(CONFIG_STM32_TIM17_PWM) || defined (CONFIG_STM32_TIM17_ADC) || \ - defined(CONFIG_STM32_TIM17_DAC) || defined(CONFIG_STM32_TIM17_QE) -# undef CONFIG_STM32_TIM17 -#endif - -#undef HAVE_TIM_GPIOCONFIG -#if defined(CONFIG_STM32_TIM1) -# if defined(GPIO_TIM1_CH1OUT) ||defined(GPIO_TIM1_CH2OUT)||\ - defined(GPIO_TIM1_CH3OUT) ||defined(GPIO_TIM1_CH4OUT) -# undef HAVE_TIM_GPIOCONFIG -# define HAVE_TIM_GPIOCONFIG 1 -# define HAVE_TIM1_GPIOCONFIG 1 -#endif -#endif - -#if defined(CONFIG_STM32_TIM2) -# if defined(GPIO_TIM2_CH1OUT) ||defined(GPIO_TIM2_CH2OUT)||\ - defined(GPIO_TIM2_CH3OUT) ||defined(GPIO_TIM2_CH4OUT) -# undef HAVE_TIM_GPIOCONFIG -# define HAVE_TIM_GPIOCONFIG 1 -# define HAVE_TIM2_GPIOCONFIG 1 -#endif -#endif - -#if defined(CONFIG_STM32_TIM3) -# if defined(GPIO_TIM3_CH1OUT) ||defined(GPIO_TIM3_CH2OUT)||\ - defined(GPIO_TIM3_CH3OUT) ||defined(GPIO_TIM3_CH4OUT) -# undef HAVE_TIM_GPIOCONFIG -# define HAVE_TIM_GPIOCONFIG 1 -# define HAVE_TIM3_GPIOCONFIG 1 -#endif -#endif - -#if defined(CONFIG_STM32_TIM4) -# if defined(GPIO_TIM4_CH1OUT) ||defined(GPIO_TIM4_CH2OUT)||\ - defined(GPIO_TIM4_CH3OUT) ||defined(GPIO_TIM4_CH4OUT) -# undef HAVE_TIM_GPIOCONFIG -# define HAVE_TIM_GPIOCONFIG 1 -# define HAVE_TIM4_GPIOCONFIG 1 -#endif -#endif - -#if defined(CONFIG_STM32_TIM5) -# if defined(GPIO_TIM5_CH1OUT) ||defined(GPIO_TIM5_CH2OUT)||\ - defined(GPIO_TIM5_CH3OUT) ||defined(GPIO_TIM5_CH4OUT) -# undef HAVE_TIM_GPIOCONFIG -# define HAVE_TIM_GPIOCONFIG 1 -# define HAVE_TIM5_GPIOCONFIG 1 -#endif -#endif - -#if defined(CONFIG_STM32_TIM8) -# if defined(GPIO_TIM8_CH1OUT) ||defined(GPIO_TIM8_CH2OUT)||\ - defined(GPIO_TIM8_CH3OUT) ||defined(GPIO_TIM8_CH4OUT) -# undef HAVE_TIM_GPIOCONFIG -# define HAVE_TIM_GPIOCONFIG 1 -# define HAVE_TIM8_GPIOCONFIG 1 -#endif -#endif - -#if defined(CONFIG_STM32_TIM9) -# if defined(GPIO_TIM9_CH1OUT) ||defined(GPIO_TIM9_CH2OUT)||\ - defined(GPIO_TIM9_CH3OUT) ||defined(GPIO_TIM9_CH4OUT) -# define HAVE_TIM9_GPIOCONFIG 1 -#endif -#endif - -#if defined(CONFIG_STM32_TIM10) -# if defined(GPIO_TIM10_CH1OUT) ||defined(GPIO_TIM10_CH2OUT)||\ - defined(GPIO_TIM10_CH3OUT) ||defined(GPIO_TIM10_CH4OUT) -# define HAVE_TIM10_GPIOCONFIG 1 -#endif -#endif - -#if defined(CONFIG_STM32_TIM11) -# if defined(GPIO_TIM11_CH1OUT) ||defined(GPIO_TIM11_CH2OUT)||\ - defined(GPIO_TIM11_CH3OUT) ||defined(GPIO_TIM11_CH4OUT) -# define HAVE_TIM11_GPIOCONFIG 1 -#endif -#endif - -#if defined(CONFIG_STM32_TIM12) -# if defined(GPIO_TIM12_CH1OUT) ||defined(GPIO_TIM12_CH2OUT)||\ - defined(GPIO_TIM12_CH3OUT) ||defined(GPIO_TIM12_CH4OUT) -# define HAVE_TIM12_GPIOCONFIG 1 -#endif -#endif - -#if defined(CONFIG_STM32_TIM13) -# if defined(GPIO_TIM13_CH1OUT) ||defined(GPIO_TIM13_CH2OUT)||\ - defined(GPIO_TIM13_CH3OUT) ||defined(GPIO_TIM13_CH4OUT) -# define HAVE_TIM13_GPIOCONFIG 1 -#endif -#endif - -#if defined(CONFIG_STM32_TIM14) -# if defined(GPIO_TIM14_CH1OUT) ||defined(GPIO_TIM14_CH2OUT)||\ - defined(GPIO_TIM14_CH3OUT) ||defined(GPIO_TIM14_CH4OUT) -# define HAVE_TIM14_GPIOCONFIG 1 -#endif -#endif - -#if defined(CONFIG_STM32_TIM15) -# if defined(GPIO_TIM15_CH1OUT) ||defined(GPIO_TIM15_CH2OUT)||\ - defined(GPIO_TIM15_CH3OUT) ||defined(GPIO_TIM15_CH4OUT) -# define HAVE_TIM15_GPIOCONFIG 1 -#endif -#endif - -#if defined(CONFIG_STM32_TIM16) -# if defined(GPIO_TIM16_CH1OUT) ||defined(GPIO_TIM16_CH2OUT)||\ - defined(GPIO_TIM16_CH3OUT) ||defined(GPIO_TIM16_CH4OUT) -# define HAVE_TIM16_GPIOCONFIG 1 -#endif -#endif - -#if defined(CONFIG_STM32_TIM17) -# if defined(GPIO_TIM17_CH1OUT) ||defined(GPIO_TIM17_CH2OUT)||\ - defined(GPIO_TIM17_CH3OUT) ||defined(GPIO_TIM17_CH4OUT) -# define HAVE_TIM17_GPIOCONFIG 1 -#endif -#endif - -/* This module then only compiles if there are enabled timers that are not - * intended for some other purpose. - */ - -#if defined(CONFIG_STM32_TIM1) || defined(CONFIG_STM32_TIM2) || \ - defined(CONFIG_STM32_TIM3) || defined(CONFIG_STM32_TIM4) || \ - defined(CONFIG_STM32_TIM5) || defined(CONFIG_STM32_TIM6) || \ - defined(CONFIG_STM32_TIM7) || defined(CONFIG_STM32_TIM8) || \ - defined(CONFIG_STM32_TIM9) || defined(CONFIG_STM32_TIM10) || \ - defined(CONFIG_STM32_TIM11) || defined(CONFIG_STM32_TIM12) || \ - defined(CONFIG_STM32_TIM13) || defined(CONFIG_STM32_TIM14) || \ - defined(CONFIG_STM32_TIM15) || defined(CONFIG_STM32_TIM16) || \ - defined(CONFIG_STM32_TIM17) - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/* TIM Device Structure */ - -struct stm32_tim_priv_s -{ - const struct stm32_tim_ops_s *ops; - stm32_tim_mode_t mode; - uint32_t base; /* TIMn base address */ -}; - -/**************************************************************************** - * Private Function prototypes - ****************************************************************************/ - -/* Register helpers */ - -static inline uint16_t stm32_getreg16(struct stm32_tim_dev_s *dev, - uint8_t offset); -static inline void stm32_putreg16(struct stm32_tim_dev_s *dev, - uint8_t offset, uint16_t value); -static inline void stm32_modifyreg16(struct stm32_tim_dev_s *dev, - uint8_t offset, uint16_t clearbits, - uint16_t setbits); -static inline uint32_t stm32_getreg32(struct stm32_tim_dev_s *dev, - uint8_t offset); -static inline void stm32_putreg32(struct stm32_tim_dev_s *dev, - uint8_t offset, uint32_t value); - -/* Timer helpers */ - -static void stm32_tim_reload_counter(struct stm32_tim_dev_s *dev); -static void stm32_tim_enable(struct stm32_tim_dev_s *dev); -static void stm32_tim_disable(struct stm32_tim_dev_s *dev); -static void stm32_tim_reset(struct stm32_tim_dev_s *dev); - -#ifdef HAVE_TIM_GPIOCONFIG -static void stm32_tim_gpioconfig(uint32_t cfg, stm32_tim_channel_t mode); -#endif - -/* Timer methods */ - -static int stm32_tim_setmode(struct stm32_tim_dev_s *dev, - stm32_tim_mode_t mode); -static int stm32_tim_setclock(struct stm32_tim_dev_s *dev, - uint32_t freq); -static void stm32_tim_setperiod(struct stm32_tim_dev_s *dev, - uint32_t period); -static uint32_t stm32_tim_getcounter(struct stm32_tim_dev_s *dev); -static void stm32_tim_setcounter(struct stm32_tim_dev_s *dev, - uint32_t count); -static int stm32_tim_getwidth(struct stm32_tim_dev_s *dev); -static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, - uint8_t channel, stm32_tim_channel_t mode); -static int stm32_tim_setcompare(struct stm32_tim_dev_s *dev, - uint8_t channel, uint32_t compare); -static int stm32_tim_getcapture(struct stm32_tim_dev_s *dev, - uint8_t channel); -static int stm32_tim_setisr(struct stm32_tim_dev_s *dev, - xcpt_t handler, void *arg, int source); -static void stm32_tim_enableint(struct stm32_tim_dev_s *dev, - int source); -static void stm32_tim_disableint(struct stm32_tim_dev_s *dev, - int source); -static void stm32_tim_ackint(struct stm32_tim_dev_s *dev, int source); -static int stm32_tim_checkint(struct stm32_tim_dev_s *dev, int source); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -static const struct stm32_tim_ops_s stm32_tim_ops = -{ - .enable = stm32_tim_enable, - .disable = stm32_tim_disable, - .setmode = stm32_tim_setmode, - .setclock = stm32_tim_setclock, - .setperiod = stm32_tim_setperiod, - .getcounter = stm32_tim_getcounter, - .setcounter = stm32_tim_setcounter, - .getwidth = stm32_tim_getwidth, - .setchannel = stm32_tim_setchannel, - .setcompare = stm32_tim_setcompare, - .getcapture = stm32_tim_getcapture, - .setisr = stm32_tim_setisr, - .enableint = stm32_tim_enableint, - .disableint = stm32_tim_disableint, - .ackint = stm32_tim_ackint, - .checkint = stm32_tim_checkint, -}; - -#ifdef CONFIG_STM32_TIM1 -struct stm32_tim_priv_s stm32_tim1_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM1_BASE, -}; -#endif -#ifdef CONFIG_STM32_TIM2 -struct stm32_tim_priv_s stm32_tim2_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM2_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM3 -struct stm32_tim_priv_s stm32_tim3_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM3_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM4 -struct stm32_tim_priv_s stm32_tim4_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM4_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM5 -struct stm32_tim_priv_s stm32_tim5_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM5_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM6 -struct stm32_tim_priv_s stm32_tim6_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM6_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM7 -struct stm32_tim_priv_s stm32_tim7_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM7_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM8 -struct stm32_tim_priv_s stm32_tim8_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM8_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM9 -struct stm32_tim_priv_s stm32_tim9_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM9_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM10 -struct stm32_tim_priv_s stm32_tim10_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM10_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM11 -struct stm32_tim_priv_s stm32_tim11_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM11_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM12 -struct stm32_tim_priv_s stm32_tim12_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM12_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM13 -struct stm32_tim_priv_s stm32_tim13_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM13_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM14 -struct stm32_tim_priv_s stm32_tim14_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM14_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM15 -struct stm32_tim_priv_s stm32_tim15_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM15_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM16 -struct stm32_tim_priv_s stm32_tim16_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM16_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM17 -struct stm32_tim_priv_s stm32_tim17_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM17_BASE, -}; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_getreg16 - * - * Description: - * Get a 16-bit register value by offset - * - ****************************************************************************/ - -static inline uint16_t stm32_getreg16(struct stm32_tim_dev_s *dev, - uint8_t offset) -{ - return getreg16(((struct stm32_tim_priv_s *)dev)->base + offset); -} - -/**************************************************************************** - * Name: stm32_putreg16 - * - * Description: - * Put a 16-bit register value by offset - * - ****************************************************************************/ - -static inline void stm32_putreg16(struct stm32_tim_dev_s *dev, - uint8_t offset, uint16_t value) -{ - putreg16(value, ((struct stm32_tim_priv_s *)dev)->base + offset); -} - -/**************************************************************************** - * Name: stm32_modifyreg16 - * - * Description: - * Modify a 16-bit register value by offset - * - ****************************************************************************/ - -static inline void stm32_modifyreg16(struct stm32_tim_dev_s *dev, - uint8_t offset, uint16_t clearbits, - uint16_t setbits) -{ - modifyreg16(((struct stm32_tim_priv_s *)dev)->base + offset, - clearbits, setbits); -} - -/**************************************************************************** - * Name: stm32_getreg32 - * - * Description: - * Get a 32-bit register value by offset. This applies only for the STM32 - * F4 32-bit registers (CNT, ARR, CRR1-4) in the 32-bit timers TIM2-5. - * - ****************************************************************************/ - -static inline uint32_t stm32_getreg32(struct stm32_tim_dev_s *dev, - uint8_t offset) -{ - return getreg32(((struct stm32_tim_priv_s *)dev)->base + offset); -} - -/**************************************************************************** - * Name: stm32_putreg32 - * - * Description: - * Put a 32-bit register value by offset. This applies only for the STM32 - * F4 32-bit registers (CNT, ARR, CRR1-4) in the 32-bit timers TIM2-5. - * - ****************************************************************************/ - -static inline void stm32_putreg32(struct stm32_tim_dev_s *dev, - uint8_t offset, uint32_t value) -{ - putreg32(value, ((struct stm32_tim_priv_s *)dev)->base + offset); -} - -/**************************************************************************** - * Name: stm32_tim_reload_counter - ****************************************************************************/ - -static void stm32_tim_reload_counter(struct stm32_tim_dev_s *dev) -{ - uint16_t val = stm32_getreg16(dev, STM32_GTIM_EGR_OFFSET); - val |= GTIM_EGR_UG; - stm32_putreg16(dev, STM32_GTIM_EGR_OFFSET, val); -} - -/**************************************************************************** - * Name: stm32_tim_enable - ****************************************************************************/ - -static void stm32_tim_enable(struct stm32_tim_dev_s *dev) -{ - uint16_t val = stm32_getreg16(dev, STM32_GTIM_CR1_OFFSET); - val |= GTIM_CR1_CEN; - stm32_tim_reload_counter(dev); - stm32_putreg16(dev, STM32_GTIM_CR1_OFFSET, val); -} - -/**************************************************************************** - * Name: stm32_tim_disable - ****************************************************************************/ - -static void stm32_tim_disable(struct stm32_tim_dev_s *dev) -{ - uint16_t val = stm32_getreg16(dev, STM32_GTIM_CR1_OFFSET); - val &= ~GTIM_CR1_CEN; - stm32_putreg16(dev, STM32_GTIM_CR1_OFFSET, val); -} - -/**************************************************************************** - * Name: stm32_tim_reset - * - * Description: - * Reset timer into system default state, but do not affect output/input - * pins - * - ****************************************************************************/ - -static void stm32_tim_reset(struct stm32_tim_dev_s *dev) -{ - ((struct stm32_tim_priv_s *)dev)->mode = STM32_TIM_MODE_DISABLED; - stm32_tim_disable(dev); -} - -/**************************************************************************** - * Name: stm32_tim_gpioconfig - ****************************************************************************/ - -#ifdef HAVE_TIM_GPIOCONFIG -static void stm32_tim_gpioconfig(uint32_t cfg, stm32_tim_channel_t mode) -{ - /* TODO: Add support for input capture and bipolar dual outputs for TIM8 */ - - if (mode & STM32_TIM_CH_MODE_MASK) - { - stm32_configgpio(cfg); - } - else - { - stm32_unconfiggpio(cfg); - } -} -#endif - -/**************************************************************************** - * Name: stm32_tim_setmode - ****************************************************************************/ - -static int stm32_tim_setmode(struct stm32_tim_dev_s *dev, - stm32_tim_mode_t mode) -{ - uint16_t val = GTIM_CR1_CEN | GTIM_CR1_ARPE; - - DEBUGASSERT(dev != NULL); - - /* This function is not supported on basic timers. To enable or - * disable it, simply set its clock to valid frequency or zero. - */ - -#if STM32_NBTIM > 0 - if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM6_BASE -#endif -#if STM32_NBTIM > 1 - || ((struct stm32_tim_priv_s *)dev)->base == STM32_TIM7_BASE -#endif -#if STM32_NBTIM > 0 - ) - { - return -EINVAL; - } -#endif - - /* Decode operational modes */ - - switch (mode & STM32_TIM_MODE_MASK) - { - case STM32_TIM_MODE_DISABLED: - val = 0; - break; - - case STM32_TIM_MODE_DOWN: - val |= GTIM_CR1_DIR; - - case STM32_TIM_MODE_UP: - break; - - case STM32_TIM_MODE_UPDOWN: - /* Our default: - * Interrupts are generated on compare, when counting down - */ - - val |= GTIM_CR1_CENTER1; - break; - - case STM32_TIM_MODE_PULSE: - val |= GTIM_CR1_OPM; - break; - - default: - return -EINVAL; - } - - stm32_tim_reload_counter(dev); - stm32_putreg16(dev, STM32_GTIM_CR1_OFFSET, val); - -#if STM32_NATIM > 0 - /* Advanced registers require Main Output Enable */ - - if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM1_BASE -#ifdef STM32_TIM8_BASE - || ((struct stm32_tim_priv_s *)dev)->base == STM32_TIM8_BASE -#endif - ) - { - stm32_modifyreg16(dev, STM32_ATIM_BDTR_OFFSET, 0, ATIM_BDTR_MOE); - } -#endif - - return OK; -} - -/**************************************************************************** - * Name: stm32_tim_setclock - ****************************************************************************/ - -static int stm32_tim_setclock(struct stm32_tim_dev_s *dev, uint32_t freq) -{ - uint32_t freqin; - int prescaler; - - DEBUGASSERT(dev != NULL); - - /* Disable Timer? */ - - if (freq == 0) - { - stm32_tim_disable(dev); - return 0; - } - - /* Get the input clock frequency for this timer. These vary with - * different timer clock sources, MCU-specific timer configuration, and - * board-specific clock configuration. The correct input clock frequency - * must be defined in the board.h header file. - */ - - switch (((struct stm32_tim_priv_s *)dev)->base) - { -#ifdef CONFIG_STM32_TIM1 - case STM32_TIM1_BASE: - freqin = STM32_APB2_TIM1_CLKIN; - break; -#endif -#ifdef CONFIG_STM32_TIM2 - case STM32_TIM2_BASE: - freqin = STM32_APB1_TIM2_CLKIN; - break; -#endif -#ifdef CONFIG_STM32_TIM3 - case STM32_TIM3_BASE: - freqin = STM32_APB1_TIM3_CLKIN; - break; -#endif -#ifdef CONFIG_STM32_TIM4 - case STM32_TIM4_BASE: - freqin = STM32_APB1_TIM4_CLKIN; - break; -#endif -#ifdef CONFIG_STM32_TIM5 - case STM32_TIM5_BASE: - freqin = STM32_APB1_TIM5_CLKIN; - break; -#endif -#ifdef CONFIG_STM32_TIM6 - case STM32_TIM6_BASE: - freqin = STM32_APB1_TIM6_CLKIN; - break; -#endif -#ifdef CONFIG_STM32_TIM7 - case STM32_TIM7_BASE: - freqin = STM32_APB1_TIM7_CLKIN; - break; -#endif -#ifdef CONFIG_STM32_TIM8 - case STM32_TIM8_BASE: - freqin = STM32_APB2_TIM8_CLKIN; - break; -#endif -#ifdef CONFIG_STM32_TIM9 - case STM32_TIM9_BASE: - freqin = STM32_APB2_TIM9_CLKIN; - break; -#endif -#ifdef CONFIG_STM32_TIM10 - case STM32_TIM10_BASE: - freqin = STM32_APB2_TIM10_CLKIN; - break; -#endif -#ifdef CONFIG_STM32_TIM11 - case STM32_TIM11_BASE: - freqin = STM32_APB2_TIM11_CLKIN; - break; -#endif -#ifdef CONFIG_STM32_TIM12 - case STM32_TIM12_BASE: - freqin = STM32_APB1_TIM12_CLKIN; - break; -#endif -#ifdef CONFIG_STM32_TIM13 - case STM32_TIM13_BASE: - freqin = STM32_APB1_TIM13_CLKIN; - break; -#endif -#ifdef CONFIG_STM32_TIM14 - case STM32_TIM14_BASE: - freqin = STM32_APB1_TIM14_CLKIN; - break; -#endif -#ifdef CONFIG_STM32_TIM15 - case STM32_TIM15_BASE: - freqin = STM32_APB2_TIM15_CLKIN; - break; -#endif -#ifdef CONFIG_STM32_TIM16 - case STM32_TIM16_BASE: - freqin = STM32_APB2_TIM16_CLKIN; - break; -#endif -#ifdef CONFIG_STM32_TIM17 - case STM32_TIM17_BASE: - freqin = STM32_APB2_TIM17_CLKIN; - break; -#endif - - default: - return -EINVAL; - } - - /* Select a pre-scaler value for this timer using the input clock - * frequency. - */ - - prescaler = freqin / freq; - - /* We need to decrement value for '1', but only, if that will not to - * cause underflow. - */ - - if (prescaler > 0) - { - prescaler--; - } - - /* Check for overflow as well. */ - - if (prescaler > 0xffff) - { - prescaler = 0xffff; - } - - stm32_putreg16(dev, STM32_GTIM_PSC_OFFSET, prescaler); - stm32_tim_enable(dev); - - return prescaler; -} - -/**************************************************************************** - * Name: stm32_tim_setperiod - ****************************************************************************/ - -static void stm32_tim_setperiod(struct stm32_tim_dev_s *dev, - uint32_t period) -{ - DEBUGASSERT(dev != NULL); - stm32_putreg32(dev, STM32_GTIM_ARR_OFFSET, period); -} - -/**************************************************************************** - * Name: stm32_tim_getcounter - ****************************************************************************/ - -static uint32_t stm32_tim_getcounter(struct stm32_tim_dev_s *dev) -{ - DEBUGASSERT(dev != NULL); - return stm32_tim_getwidth(dev) > 16 ? - stm32_getreg32(dev, STM32_GTIM_CNT_OFFSET) : - (uint32_t)stm32_getreg16(dev, STM32_GTIM_CNT_OFFSET); -} - -/**************************************************************************** - * Name: stm32_tim_setcounter - ****************************************************************************/ - -static void stm32_tim_setcounter(struct stm32_tim_dev_s *dev, - uint32_t count) -{ - DEBUGASSERT(dev != NULL); - - if (stm32_tim_getwidth(dev) > 16) - { - stm32_putreg32(dev, STM32_GTIM_CNT_OFFSET, count); - } - else - { - stm32_putreg16(dev, STM32_GTIM_CNT_OFFSET, (uint16_t)count); - } -} - -/**************************************************************************** - * Name: stm32_tim_getwidth - ****************************************************************************/ - -static int stm32_tim_getwidth(struct stm32_tim_dev_s *dev) -{ - /* Only TIM2 and TIM5 timers may be 32-bits in width - * - * Reference Table 2 of en.DM00042534.pdf - */ - - switch (((struct stm32_tim_priv_s *)dev)->base) - { - /* TIM2 is 32-bits on all except F10x, L0x, and L1x lines */ - -#if defined(CONFIG_STM32_TIM2) && !defined(STM32_STM32F10XX) && \ - !defined(STM32_STM32L15XX) - case STM32_TIM2_BASE: - return 32; -#endif - - /* TIM5 is 32-bits on all except F10x lines */ - -#if defined(CONFIG_STM32_TIM5) && !defined(STM32_STM32F10XX) - case STM32_TIM5_BASE: - return 32; -#endif - - /* All others are 16-bit times */ - - default: - return 16; - } -} - -/**************************************************************************** - * Name: stm32_tim_setchannel - ****************************************************************************/ - -static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, - uint8_t channel, stm32_tim_channel_t mode) -{ - uint16_t ccmr_orig = 0; - uint16_t ccmr_val = 0; - uint16_t ccmr_mask = 0xff; - uint16_t ccer_val = stm32_getreg16(dev, STM32_GTIM_CCER_OFFSET); - uint8_t ccmr_offset = STM32_GTIM_CCMR1_OFFSET; - - DEBUGASSERT(dev != NULL); - - /* Further we use range as 0..3; if channel=0 it will also overflow here */ - - if (--channel > 4) - { - return -EINVAL; - } - - /* Assume that channel is disabled and polarity is active high */ - - ccer_val &= ~((GTIM_CCER_CC1P | GTIM_CCER_CC1E) << - GTIM_CCER_CCXBASE(channel)); - - /* This function is not supported on basic timers. To enable or - * disable it, simply set its clock to valid frequency or zero. - */ - -#if STM32_NBTIM > 0 - if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM6_BASE -#endif -#if STM32_NBTIM > 1 - || ((struct stm32_tim_priv_s *)dev)->base == STM32_TIM7_BASE -#endif -#if STM32_NBTIM > 0 - ) - { - return -EINVAL; - } -#endif - - /* Decode configuration */ - - switch (mode & STM32_TIM_CH_MODE_MASK) - { - case STM32_TIM_CH_DISABLED: - break; - - case STM32_TIM_CH_OUTPWM: - ccmr_val = (GTIM_CCMR_MODE_PWM1 << GTIM_CCMR1_OC1M_SHIFT) + - GTIM_CCMR1_OC1PE; - ccer_val |= GTIM_CCER_CC1E << GTIM_CCER_CCXBASE(channel); - break; - - default: - return -EINVAL; - } - - /* Set polarity */ - - if (mode & STM32_TIM_CH_POLARITY_NEG) - { - ccer_val |= GTIM_CCER_CC1P << GTIM_CCER_CCXBASE(channel); - } - - /* Define its position (shift) and get register offset */ - - if (channel & 1) - { - ccmr_val <<= 8; - ccmr_mask <<= 8; - } - - if (channel > 1) - { - ccmr_offset = STM32_GTIM_CCMR2_OFFSET; - } - - ccmr_orig = stm32_getreg16(dev, ccmr_offset); - ccmr_orig &= ~ccmr_mask; - ccmr_orig |= ccmr_val; - stm32_putreg16(dev, ccmr_offset, ccmr_orig); - stm32_putreg16(dev, STM32_GTIM_CCER_OFFSET, ccer_val); - - /* set GPIO */ - - switch (((struct stm32_tim_priv_s *)dev)->base) - { -#ifdef CONFIG_STM32_TIM1 - case STM32_TIM1_BASE: - switch (channel) - { -#if defined(GPIO_TIM1_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM1_CH1OUT, mode); break; -#endif -#if defined(GPIO_TIM1_CH2OUT) - case 1: - stm32_tim_gpioconfig(GPIO_TIM1_CH2OUT, mode); break; -#endif -#if defined(GPIO_TIM1_CH3OUT) - case 2: - stm32_tim_gpioconfig(GPIO_TIM1_CH3OUT, mode); break; -#endif -#if defined(GPIO_TIM1_CH4OUT) - case 3: - stm32_tim_gpioconfig(GPIO_TIM1_CH4OUT, mode); break; -#endif - default: - return -EINVAL; - } - break; -#endif -#ifdef CONFIG_STM32_TIM2 - case STM32_TIM2_BASE: - switch (channel) - { -#if defined(GPIO_TIM2_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM2_CH1OUT, mode); - break; -#endif -#if defined(GPIO_TIM2_CH2OUT) - case 1: - stm32_tim_gpioconfig(GPIO_TIM2_CH2OUT, mode); - break; -#endif -#if defined(GPIO_TIM2_CH3OUT) - case 2: - stm32_tim_gpioconfig(GPIO_TIM2_CH3OUT, mode); - break; -#endif -#if defined(GPIO_TIM2_CH4OUT) - case 3: - stm32_tim_gpioconfig(GPIO_TIM2_CH4OUT, mode); - break; -#endif - default: - return -EINVAL; - } - break; -#endif -#ifdef CONFIG_STM32_TIM3 - case STM32_TIM3_BASE: - switch (channel) - { -#if defined(GPIO_TIM3_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM3_CH1OUT, mode); - break; -#endif -#if defined(GPIO_TIM3_CH2OUT) - case 1: - stm32_tim_gpioconfig(GPIO_TIM3_CH2OUT, mode); - break; -#endif -#if defined(GPIO_TIM3_CH3OUT) - case 2: - stm32_tim_gpioconfig(GPIO_TIM3_CH3OUT, mode); - break; -#endif -#if defined(GPIO_TIM3_CH4OUT) - case 3: - stm32_tim_gpioconfig(GPIO_TIM3_CH4OUT, mode); - break; -#endif - default: - return -EINVAL; - } - break; -#endif -#ifdef CONFIG_STM32_TIM4 - case STM32_TIM4_BASE: - switch (channel) - { -#if defined(GPIO_TIM4_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM4_CH1OUT, mode); - break; -#endif -#if defined(GPIO_TIM4_CH2OUT) - case 1: - stm32_tim_gpioconfig(GPIO_TIM4_CH2OUT, mode); - break; -#endif -#if defined(GPIO_TIM4_CH3OUT) - case 2: - stm32_tim_gpioconfig(GPIO_TIM4_CH3OUT, mode); - break; -#endif -#if defined(GPIO_TIM4_CH4OUT) - case 3: - stm32_tim_gpioconfig(GPIO_TIM4_CH4OUT, mode); - break; -#endif - default: - return -EINVAL; - } - break; -#endif -#ifdef CONFIG_STM32_TIM5 - case STM32_TIM5_BASE: - switch (channel) - { -#if defined(GPIO_TIM5_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM5_CH1OUT, mode); - break; -#endif -#if defined(GPIO_TIM5_CH2OUT) - case 1: - stm32_tim_gpioconfig(GPIO_TIM5_CH2OUT, mode); - break; -#endif -#if defined(GPIO_TIM5_CH3OUT) - case 2: - stm32_tim_gpioconfig(GPIO_TIM5_CH3OUT, mode); - break; -#endif -#if defined(GPIO_TIM5_CH4OUT) - case 3: - stm32_tim_gpioconfig(GPIO_TIM5_CH4OUT, mode); - break; -#endif - default: - return -EINVAL; - } - break; -#endif -#ifdef CONFIG_STM32_TIM8 - case STM32_TIM8_BASE: - switch (channel) - { -#if defined(GPIO_TIM8_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM8_CH1OUT, mode); break; -#endif -#if defined(GPIO_TIM8_CH2OUT) - case 1: - stm32_tim_gpioconfig(GPIO_TIM8_CH2OUT, mode); break; -#endif -#if defined(GPIO_TIM8_CH3OUT) - case 2: - stm32_tim_gpioconfig(GPIO_TIM8_CH3OUT, mode); break; -#endif -#if defined(GPIO_TIM8_CH4OUT) - case 3: - stm32_tim_gpioconfig(GPIO_TIM8_CH4OUT, mode); break; -#endif - default: - return -EINVAL; - } - break; -#endif -#ifdef CONFIG_STM32_TIM9 - case STM32_TIM9_BASE: - switch (channel) - { -#if defined(GPIO_TIM9_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM9_CH1OUT, mode); - break; -#endif -#if defined(GPIO_TIM9_CH2OUT) - case 1: - stm32_tim_gpioconfig(GPIO_TIM9_CH2OUT, mode); - break; -#endif -#if defined(GPIO_TIM9_CH3OUT) - case 2: - stm32_tim_gpioconfig(GPIO_TIM9_CH3OUT, mode); - break; -#endif -#if defined(GPIO_TIM9_CH4OUT) - case 3: - stm32_tim_gpioconfig(GPIO_TIM9_CH4OUT, mode); - break; -#endif - default: - return -EINVAL; - } - break; -#endif -#ifdef CONFIG_STM32_TIM10 - case STM32_TIM10_BASE: - switch (channel) - { -#if defined(GPIO_TIM10_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM10_CH1OUT, mode); - break; -#endif -#if defined(GPIO_TIM10_CH2OUT) - case 1: - stm32_tim_gpioconfig(GPIO_TIM10_CH2OUT, mode); - break; -#endif -#if defined(GPIO_TIM10_CH3OUT) - case 2: - stm32_tim_gpioconfig(GPIO_TIM10_CH3OUT, mode); - break; -#endif -#if defined(GPIO_TIM10_CH4OUT) - case 3: - stm32_tim_gpioconfig(GPIO_TIM10_CH4OUT, mode); - break; -#endif - default: - return -EINVAL; - } - break; -#endif -#ifdef CONFIG_STM32_TIM11 - case STM32_TIM11_BASE: - switch (channel) - { -#if defined(GPIO_TIM11_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM11_CH1OUT, mode); - break; -#endif -#if defined(GPIO_TIM11_CH2OUT) - case 1: - stm32_tim_gpioconfig(GPIO_TIM11_CH2OUT, mode); - break; -#endif -#if defined(GPIO_TIM11_CH3OUT) - case 2: - stm32_tim_gpioconfig(GPIO_TIM11_CH3OUT, mode); - break; -#endif -#if defined(GPIO_TIM11_CH4OUT) - case 3: - stm32_tim_gpioconfig(GPIO_TIM11_CH4OUT, mode); - break; -#endif - default: - return -EINVAL; - } - break; -#endif -#ifdef CONFIG_STM32_TIM12 - case STM32_TIM12_BASE: - switch (channel) - { -#if defined(GPIO_TIM12_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM12_CH1OUT, mode); - break; -#endif -#if defined(GPIO_TIM12_CH2OUT) - case 1: - stm32_tim_gpioconfig(GPIO_TIM12_CH2OUT, mode); - break; -#endif -#if defined(GPIO_TIM12_CH3OUT) - case 2: - stm32_tim_gpioconfig(GPIO_TIM12_CH3OUT, mode); - break; -#endif -#if defined(GPIO_TIM12_CH4OUT) - case 3: - stm32_tim_gpioconfig(GPIO_TIM12_CH4OUT, mode); - break; -#endif - default: - return -EINVAL; - } - break; -#endif -#ifdef CONFIG_STM32_TIM13 - case STM32_TIM13_BASE: - switch (channel) - { -#if defined(GPIO_TIM13_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM13_CH1OUT, mode); - break; -#endif -#if defined(GPIO_TIM13_CH2OUT) - case 1: - stm32_tim_gpioconfig(GPIO_TIM13_CH2OUT, mode); - break; -#endif -#if defined(GPIO_TIM13_CH3OUT) - case 2: - stm32_tim_gpioconfig(GPIO_TIM13_CH3OUT, mode); - break; -#endif -#if defined(GPIO_TIM13_CH4OUT) - case 3: - stm32_tim_gpioconfig(GPIO_TIM13_CH4OUT, mode); - break; -#endif - default: - return -EINVAL; - } - break; -#endif -#ifdef CONFIG_STM32_TIM14 - case STM32_TIM14_BASE: - switch (channel) - { -#if defined(GPIO_TIM14_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM14_CH1OUT, mode); - break; -#endif -#if defined(GPIO_TIM14_CH2OUT) - case 1: - stm32_tim_gpioconfig(GPIO_TIM14_CH2OUT, mode); - break; -#endif -#if defined(GPIO_TIM14_CH3OUT) - case 2: - stm32_tim_gpioconfig(GPIO_TIM14_CH3OUT, mode); - break; -#endif -#if defined(GPIO_TIM14_CH4OUT) - case 3: - stm32_tim_gpioconfig(GPIO_TIM14_CH4OUT, mode); - break; -#endif - default: - return -EINVAL; - } - break; -#endif -#ifdef CONFIG_STM32_TIM15 - case STM32_TIM15_BASE: - switch (channel) - { -#if defined(GPIO_TIM15_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM15_CH1OUT, mode); - break; -#endif -#if defined(GPIO_TIM15_CH2OUT) - case 1: - stm32_tim_gpioconfig(GPIO_TIM15_CH2OUT, mode); - break; -#endif -#if defined(GPIO_TIM15_CH3OUT) - case 2: - stm32_tim_gpioconfig(GPIO_TIM15_CH3OUT, mode); - break; -#endif -#if defined(GPIO_TIM15_CH4OUT) - case 3: - stm32_tim_gpioconfig(GPIO_TIM15_CH4OUT, mode); - break; -#endif - default: - return -EINVAL; - } - break; -#endif -#ifdef CONFIG_STM32_TIM16 - case STM32_TIM16_BASE: - switch (channel) - { -#if defined(GPIO_TIM16_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM16_CH1OUT, mode); - break; -#endif -#if defined(GPIO_TIM16_CH2OUT) - case 1: - stm32_tim_gpioconfig(GPIO_TIM16_CH2OUT, mode); - break; -#endif -#if defined(GPIO_TIM16_CH3OUT) - case 2: - stm32_tim_gpioconfig(GPIO_TIM16_CH3OUT, mode); - break; -#endif -#if defined(GPIO_TIM16_CH4OUT) - case 3: - stm32_tim_gpioconfig(GPIO_TIM16_CH4OUT, mode); - break; -#endif - default: - return -EINVAL; - } - break; -#endif -#ifdef CONFIG_STM32_TIM17 - case STM32_TIM17_BASE: - switch (channel) - { -#if defined(GPIO_TIM17_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM17_CH1OUT, mode); - break; -#endif -#if defined(GPIO_TIM17_CH2OUT) - case 1: - stm32_tim_gpioconfig(GPIO_TIM17_CH2OUT, mode); - break; -#endif -#if defined(GPIO_TIM17_CH3OUT) - case 2: - stm32_tim_gpioconfig(GPIO_TIM17_CH3OUT, mode); - break; -#endif -#if defined(GPIO_TIM17_CH4OUT) - case 3: - stm32_tim_gpioconfig(GPIO_TIM17_CH4OUT, mode); - break; -#endif - default: - return -EINVAL; - } - break; -#endif - default: - return -EINVAL; - } - - return OK; -} - -/**************************************************************************** - * Name: stm32_tim_setcompare - ****************************************************************************/ - -static int stm32_tim_setcompare(struct stm32_tim_dev_s *dev, - uint8_t channel, uint32_t compare) -{ - DEBUGASSERT(dev != NULL); - - switch (channel) - { - case 1: - stm32_putreg32(dev, STM32_GTIM_CCR1_OFFSET, compare); - break; - - case 2: - stm32_putreg32(dev, STM32_GTIM_CCR2_OFFSET, compare); - break; - - case 3: - stm32_putreg32(dev, STM32_GTIM_CCR3_OFFSET, compare); - break; - - case 4: - stm32_putreg32(dev, STM32_GTIM_CCR4_OFFSET, compare); - break; - - default: - return -EINVAL; - } - - return OK; -} - -/**************************************************************************** - * Name: stm32_tim_getcapture - ****************************************************************************/ - -static int stm32_tim_getcapture(struct stm32_tim_dev_s *dev, - uint8_t channel) -{ - DEBUGASSERT(dev != NULL); - - switch (channel) - { - case 1: - return stm32_getreg32(dev, STM32_GTIM_CCR1_OFFSET); - case 2: - return stm32_getreg32(dev, STM32_GTIM_CCR2_OFFSET); - case 3: - return stm32_getreg32(dev, STM32_GTIM_CCR3_OFFSET); - case 4: - return stm32_getreg32(dev, STM32_GTIM_CCR4_OFFSET); - } - - return -EINVAL; -} - -/**************************************************************************** - * Name: stm32_tim_setisr - ****************************************************************************/ - -static int stm32_tim_setisr(struct stm32_tim_dev_s *dev, xcpt_t handler, - void * arg, int source) -{ - int vectorno; - - DEBUGASSERT(dev != NULL); - DEBUGASSERT(source == 0); - - switch (((struct stm32_tim_priv_s *)dev)->base) - { -#ifdef CONFIG_STM32_TIM1 - case STM32_TIM1_BASE: - vectorno = STM32_IRQ_TIM1UP; - break; -#endif -#ifdef CONFIG_STM32_TIM2 - case STM32_TIM2_BASE: - vectorno = STM32_IRQ_TIM2; - break; -#endif -#ifdef CONFIG_STM32_TIM3 - case STM32_TIM3_BASE: - vectorno = STM32_IRQ_TIM3; - break; -#endif -#ifdef CONFIG_STM32_TIM4 - case STM32_TIM4_BASE: - vectorno = STM32_IRQ_TIM4; - break; -#endif -#ifdef CONFIG_STM32_TIM5 - case STM32_TIM5_BASE: - vectorno = STM32_IRQ_TIM5; - break; -#endif -#ifdef CONFIG_STM32_TIM6 - case STM32_TIM6_BASE: - vectorno = STM32_IRQ_TIM6; - break; -#endif -#ifdef CONFIG_STM32_TIM7 - case STM32_TIM7_BASE: - vectorno = STM32_IRQ_TIM7; - break; -#endif -#ifdef CONFIG_STM32_TIM8 - case STM32_TIM8_BASE: - vectorno = STM32_IRQ_TIM8UP; - break; -#endif -#ifdef CONFIG_STM32_TIM9 - case STM32_TIM9_BASE: - vectorno = STM32_IRQ_TIM9; - break; -#endif -#ifdef CONFIG_STM32_TIM10 - case STM32_TIM10_BASE: - vectorno = STM32_IRQ_TIM10; - break; -#endif -#ifdef CONFIG_STM32_TIM11 - case STM32_TIM11_BASE: - vectorno = STM32_IRQ_TIM11; - break; -#endif -#ifdef CONFIG_STM32_TIM12 - case STM32_TIM12_BASE: - vectorno = STM32_IRQ_TIM12; - break; -#endif -#ifdef CONFIG_STM32_TIM13 - case STM32_TIM13_BASE: - vectorno = STM32_IRQ_TIM13; - break; -#endif -#ifdef CONFIG_STM32_TIM14 - case STM32_TIM14_BASE: - vectorno = STM32_IRQ_TIM14; - break; -#endif -#ifdef CONFIG_STM32_TIM15 - case STM32_TIM15_BASE: - vectorno = STM32_IRQ_TIM15; - break; -#endif -#ifdef CONFIG_STM32_TIM16 - case STM32_TIM16_BASE: - vectorno = STM32_IRQ_TIM16; - break; -#endif -#ifdef CONFIG_STM32_TIM17 - case STM32_TIM17_BASE: - vectorno = STM32_IRQ_TIM17; - break; -#endif - - default: - return -EINVAL; - } - - /* Disable interrupt when callback is removed */ - - if (!handler) - { - up_disable_irq(vectorno); - irq_detach(vectorno); - return OK; - } - - /* Otherwise set callback and enable interrupt */ - - irq_attach(vectorno, handler, arg); - up_enable_irq(vectorno); - - return OK; -} - -/**************************************************************************** - * Name: stm32_tim_enableint - ****************************************************************************/ - -static void stm32_tim_enableint(struct stm32_tim_dev_s *dev, int source) -{ - DEBUGASSERT(dev != NULL); - stm32_modifyreg16(dev, STM32_GTIM_DIER_OFFSET, 0, source); -} - -/**************************************************************************** - * Name: stm32_tim_disableint - ****************************************************************************/ - -static void stm32_tim_disableint(struct stm32_tim_dev_s *dev, int source) -{ - DEBUGASSERT(dev != NULL); - stm32_modifyreg16(dev, STM32_GTIM_DIER_OFFSET, source, 0); -} - -/**************************************************************************** - * Name: stm32_tim_ackint - ****************************************************************************/ - -static void stm32_tim_ackint(struct stm32_tim_dev_s *dev, int source) -{ - stm32_putreg16(dev, STM32_GTIM_SR_OFFSET, ~source); -} - -/**************************************************************************** - * Name: stm32_tim_checkint - ****************************************************************************/ - -static int stm32_tim_checkint(struct stm32_tim_dev_s *dev, int source) -{ - uint16_t regval = stm32_getreg16(dev, STM32_GTIM_SR_OFFSET); - return (regval & source) ? 1 : 0; -} - -/**************************************************************************** - * Pubic Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_tim_init - ****************************************************************************/ - -struct stm32_tim_dev_s *stm32_tim_init(int timer) -{ - struct stm32_tim_dev_s *dev = NULL; - - /* Get structure and enable power */ - - switch (timer) - { -#ifdef CONFIG_STM32_TIM1 - case 1: - dev = (struct stm32_tim_dev_s *)&stm32_tim1_priv; - modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM1EN); - break; -#endif -#ifdef CONFIG_STM32_TIM2 - case 2: - dev = (struct stm32_tim_dev_s *)&stm32_tim2_priv; - modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM2EN); - break; -#endif -#ifdef CONFIG_STM32_TIM3 - case 3: - dev = (struct stm32_tim_dev_s *)&stm32_tim3_priv; - modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM3EN); - break; -#endif -#ifdef CONFIG_STM32_TIM4 - case 4: - dev = (struct stm32_tim_dev_s *)&stm32_tim4_priv; - modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM4EN); - break; -#endif -#ifdef CONFIG_STM32_TIM5 - case 5: - dev = (struct stm32_tim_dev_s *)&stm32_tim5_priv; - modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM5EN); - break; -#endif -#ifdef CONFIG_STM32_TIM6 - case 6: - dev = (struct stm32_tim_dev_s *)&stm32_tim6_priv; - modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM6EN); - break; -#endif -#ifdef CONFIG_STM32_TIM7 - case 7: - dev = (struct stm32_tim_dev_s *)&stm32_tim7_priv; - modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM7EN); - break; -#endif -#ifdef CONFIG_STM32_TIM8 - case 8: - dev = (struct stm32_tim_dev_s *)&stm32_tim8_priv; - modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM8EN); - break; -#endif -#ifdef CONFIG_STM32_TIM9 - case 9: - dev = (struct stm32_tim_dev_s *)&stm32_tim9_priv; - modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM9EN); - break; -#endif -#ifdef CONFIG_STM32_TIM10 - case 10: - dev = (struct stm32_tim_dev_s *)&stm32_tim10_priv; - modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM10EN); - break; -#endif -#ifdef CONFIG_STM32_TIM11 - case 11: - dev = (struct stm32_tim_dev_s *)&stm32_tim11_priv; - modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM11EN); - break; -#endif -#ifdef CONFIG_STM32_TIM12 - case 12: - dev = (struct stm32_tim_dev_s *)&stm32_tim12_priv; - modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM12EN); - break; -#endif -#ifdef CONFIG_STM32_TIM13 - case 13: - dev = (struct stm32_tim_dev_s *)&stm32_tim13_priv; - modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM13EN); - break; -#endif -#ifdef CONFIG_STM32_TIM14 - case 14: - dev = (struct stm32_tim_dev_s *)&stm32_tim14_priv; - modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM14EN); - break; -#endif -#ifdef CONFIG_STM32_TIM15 - case 15: - dev = (struct stm32_tim_dev_s *)&stm32_tim15_priv; - modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM15EN); - break; -#endif -#ifdef CONFIG_STM32_TIM16 - case 16: - dev = (struct stm32_tim_dev_s *)&stm32_tim16_priv; - modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM16EN); - break; -#endif -#ifdef CONFIG_STM32_TIM17 - case 17: - dev = (struct stm32_tim_dev_s *)&stm32_tim17_priv; - modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM17EN); - break; -#endif - default: - return NULL; - } - - /* Is device already allocated */ - - if (((struct stm32_tim_priv_s *)dev)->mode != STM32_TIM_MODE_UNUSED) - { - return NULL; - } - - stm32_tim_reset(dev); - - return dev; -} - -/**************************************************************************** - * Name: stm32_tim_deinit - * - * TODO: Detach interrupts, and close down all TIM Channels - * - ****************************************************************************/ - -int stm32_tim_deinit(struct stm32_tim_dev_s * dev) -{ - DEBUGASSERT(dev != NULL); - - /* Disable power */ - - switch (((struct stm32_tim_priv_s *)dev)->base) - { -#ifdef CONFIG_STM32_TIM1 - case STM32_TIM1_BASE: - modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM1EN, 0); - break; -#endif -#ifdef CONFIG_STM32_TIM2 - case STM32_TIM2_BASE: - modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM2EN, 0); - break; -#endif -#ifdef CONFIG_STM32_TIM3 - case STM32_TIM3_BASE: - modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM3EN, 0); - break; -#endif -#ifdef CONFIG_STM32_TIM4 - case STM32_TIM4_BASE: - modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM4EN, 0); - break; -#endif -#ifdef CONFIG_STM32_TIM5 - case STM32_TIM5_BASE: - modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM5EN, 0); - break; -#endif -#ifdef CONFIG_STM32_TIM6 - case STM32_TIM6_BASE: - modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM6EN, 0); - break; -#endif -#ifdef CONFIG_STM32_TIM7 - case STM32_TIM7_BASE: - modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM7EN, 0); - break; -#endif -#ifdef CONFIG_STM32_TIM8 - case STM32_TIM8_BASE: - modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM8EN, 0); - break; -#endif -#ifdef CONFIG_STM32_TIM9 - case STM32_TIM9_BASE: - modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM9EN, 0); - break; -#endif -#ifdef CONFIG_STM32_TIM10 - case STM32_TIM10_BASE: - modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM10EN, 0); - break; -#endif -#ifdef CONFIG_STM32_TIM11 - case STM32_TIM11_BASE: - modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM11EN, 0); - break; -#endif -#ifdef CONFIG_STM32_TIM12 - case STM32_TIM12_BASE: - modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM12EN, 0); - break; -#endif -#ifdef CONFIG_STM32_TIM13 - case STM32_TIM13_BASE: - modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM13EN, 0); - break; -#endif -#ifdef CONFIG_STM32_TIM14 - case STM32_TIM14_BASE: - modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM14EN, 0); - break; -#endif -#ifdef CONFIG_STM32_TIM15 - case STM32_TIM15_BASE: - modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM15EN, 0); - break; -#endif -#ifdef CONFIG_STM32_TIM16 - case STM32_TIM16_BASE: - modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM16EN, 0); - break; -#endif -#ifdef CONFIG_STM32_TIM17 - case STM32_TIM17_BASE: - modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM17EN, 0); - break; -#endif - default: - return -EINVAL; - } - - /* Mark it as free */ - - ((struct stm32_tim_priv_s *)dev)->mode = STM32_TIM_MODE_UNUSED; - - return OK; -} - -#endif /* defined(CONFIG_STM32_TIM1 || ... || TIM17) */ diff --git a/arch/arm/src/stm32/stm32_tim.h b/arch/arm/src/stm32/stm32_tim.h deleted file mode 100644 index 6e01e6693d7ae..0000000000000 --- a/arch/arm/src/stm32/stm32_tim.h +++ /dev/null @@ -1,225 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_tim.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32_STM32_TIM_H -#define __ARCH_ARM_SRC_STM32_STM32_TIM_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "chip.h" -#include "hardware/stm32_tim.h" - -#include - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Helpers ******************************************************************/ - -#define STM32_TIM_SETMODE(d,mode) ((d)->ops->setmode(d,mode)) -#define STM32_TIM_SETCLOCK(d,freq) ((d)->ops->setclock(d,freq)) -#define STM32_TIM_SETPERIOD(d,period) ((d)->ops->setperiod(d,period)) -#define STM32_TIM_GETCOUNTER(d) ((d)->ops->getcounter(d)) -#define STM32_TIM_SETCOUNTER(d,c) ((d)->ops->setcounter(d,c)) -#define STM32_TIM_GETWIDTH(d) ((d)->ops->getwidth(d)) -#define STM32_TIM_SETCHANNEL(d,ch,mode) ((d)->ops->setchannel(d,ch,mode)) -#define STM32_TIM_SETCOMPARE(d,ch,comp) ((d)->ops->setcompare(d,ch,comp)) -#define STM32_TIM_GETCAPTURE(d,ch) ((d)->ops->getcapture(d,ch)) -#define STM32_TIM_SETISR(d,hnd,arg,s) ((d)->ops->setisr(d,hnd,arg,s)) -#define STM32_TIM_ENABLEINT(d,s) ((d)->ops->enableint(d,s)) -#define STM32_TIM_DISABLEINT(d,s) ((d)->ops->disableint(d,s)) -#define STM32_TIM_ACKINT(d,s) ((d)->ops->ackint(d,s)) -#define STM32_TIM_CHECKINT(d,s) ((d)->ops->checkint(d,s)) -#define STM32_TIM_ENABLE(d) ((d)->ops->enable(d)) -#define STM32_TIM_DISABLE(d) ((d)->ops->disable(d)) - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -#ifndef __ASSEMBLY__ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/* TIM Device Structure */ - -struct stm32_tim_dev_s -{ - struct stm32_tim_ops_s *ops; -}; - -/* TIM Modes of Operation */ - -typedef enum -{ - STM32_TIM_MODE_UNUSED = -1, - - /* One of the following */ - - STM32_TIM_MODE_MASK = 0x0310, - STM32_TIM_MODE_DISABLED = 0x0000, - STM32_TIM_MODE_UP = 0x0100, - STM32_TIM_MODE_DOWN = 0x0110, - STM32_TIM_MODE_UPDOWN = 0x0200, - STM32_TIM_MODE_PULSE = 0x0300, - - /* One of the following */ - - STM32_TIM_MODE_CK_INT = 0x0000, - - /* STM32_TIM_MODE_CK_INT_TRIG = 0x0400, */ - - /* STM32_TIM_MODE_CK_EXT = 0x0800, */ - - /* STM32_TIM_MODE_CK_EXT_TRIG = 0x0C00, */ - - /* Clock sources, OR'ed with CK_EXT */ - - /* STM32_TIM_MODE_CK_CHINVALID = 0x0000, */ - - /* STM32_TIM_MODE_CK_CH1 = 0x0001, */ - - /* STM32_TIM_MODE_CK_CH2 = 0x0002, */ - - /* STM32_TIM_MODE_CK_CH3 = 0x0003, */ - - /* STM32_TIM_MODE_CK_CH4 = 0x0004 */ - - /* Todo: external trigger block */ -} stm32_tim_mode_t; - -/* TIM Channel Modes */ - -typedef enum -{ - STM32_TIM_CH_DISABLED = 0x00, - - /* Common configuration */ - - STM32_TIM_CH_POLARITY_POS = 0x00, - STM32_TIM_CH_POLARITY_NEG = 0x01, - - /* MODES: */ - - STM32_TIM_CH_MODE_MASK = 0x06, - - /* Output Compare Modes */ - - STM32_TIM_CH_OUTPWM = 0x04, /* Enable standard PWM mode, active high when counter < compare */ - - /* STM32_TIM_CH_OUTCOMPARE = 0x06, */ - - /* TODO other modes ... as PWM capture, ENCODER and Hall Sensor */ - - /* STM32_TIM_CH_INCAPTURE = 0x10, */ - - /* STM32_TIM_CH_INPWM = 0x20 */ - - /* STM32_TIM_CH_DRIVE_OC -- open collector mode */ -} stm32_tim_channel_t; - -/* TIM Operations */ - -struct stm32_tim_ops_s -{ - /* Basic Timers */ - - void (*enable)(struct stm32_tim_dev_s *dev); - void (*disable)(struct stm32_tim_dev_s *dev); - int (*setmode)(struct stm32_tim_dev_s *dev, stm32_tim_mode_t mode); - int (*setclock)(struct stm32_tim_dev_s *dev, uint32_t freq); - void (*setperiod)(struct stm32_tim_dev_s *dev, uint32_t period); - uint32_t (*getcounter)(struct stm32_tim_dev_s *dev); - void (*setcounter)(struct stm32_tim_dev_s *dev, uint32_t count); - - /* General and Advanced Timers Adds */ - - int (*getwidth)(struct stm32_tim_dev_s *dev); - int (*setchannel)(struct stm32_tim_dev_s *dev, uint8_t channel, - stm32_tim_channel_t mode); - int (*setcompare)(struct stm32_tim_dev_s *dev, uint8_t channel, - uint32_t compare); - int (*getcapture)(struct stm32_tim_dev_s *dev, uint8_t channel); - - /* Timer interrupts */ - - int (*setisr)(struct stm32_tim_dev_s *dev, - xcpt_t handler, void * arg, int source); - void (*enableint)(struct stm32_tim_dev_s *dev, int source); - void (*disableint)(struct stm32_tim_dev_s *dev, int source); - void (*ackint)(struct stm32_tim_dev_s *dev, int source); - int (*checkint)(struct stm32_tim_dev_s *dev, int source); -}; - -/**************************************************************************** - * Public Functions Prototypes - ****************************************************************************/ - -/* Power-up timer and get its structure */ - -struct stm32_tim_dev_s *stm32_tim_init(int timer); - -/* Power-down timer, mark it as unused */ - -int stm32_tim_deinit(struct stm32_tim_dev_s *dev); - -/**************************************************************************** - * Name: stm32_timer_initialize - * - * Description: - * Bind the configuration timer to a timer lower half instance and - * register the timer drivers at 'devpath' - * - * Input Parameters: - * devpath - The full path to the timer device. - * This should be of the form /dev/timer0 - * timer - the timer number. - * - * Returned Value: - * Zero (OK) is returned on success; A negated errno value is returned - * to indicate the nature of any failure. - * - ****************************************************************************/ - -#ifdef CONFIG_TIMER -int stm32_timer_initialize(const char *devpath, int timer); -#endif - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32_STM32_TIM_H */ diff --git a/arch/arm/src/stm32/stm32_tim_lowerhalf.c b/arch/arm/src/stm32/stm32_tim_lowerhalf.c deleted file mode 100644 index 14407bdc4f76f..0000000000000 --- a/arch/arm/src/stm32/stm32_tim_lowerhalf.c +++ /dev/null @@ -1,588 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_tim_lowerhalf.c - * - * SPDX-License-Identifier: BSD-3-Clause - * SPDX-FileCopyrightText: 2015 Wail Khemir. All rights reserved. - * SPDX-FileCopyrightText: 2015 Omni Hoverboards Inc. All rights reserved. - * SPDX-FileContributor: Wail Khemir - * SPDX-FileContributor: Paul Alexander Patience - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include -#include -#include - -#include -#include - -#include - -#include "stm32_tim.h" - -#if defined(CONFIG_TIMER) && \ - (defined(CONFIG_STM32_TIM1) || defined(CONFIG_STM32_TIM2) || \ - defined(CONFIG_STM32_TIM3) || defined(CONFIG_STM32_TIM4) || \ - defined(CONFIG_STM32_TIM5) || defined(CONFIG_STM32_TIM6) || \ - defined(CONFIG_STM32_TIM7) || defined(CONFIG_STM32_TIM8) || \ - defined(CONFIG_STM32_TIM9) || defined(CONFIG_STM32_TIM10) || \ - defined(CONFIG_STM32_TIM11) || defined(CONFIG_STM32_TIM12) || \ - defined(CONFIG_STM32_TIM13) || defined(CONFIG_STM32_TIM14)) - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#define STM32_TIM1_RES 16 -#if defined(CONFIG_STM32_STM32L15XX) || defined(CONFIG_STM32_STM32F10XX) -# define STM32_TIM2_RES 16 -#else -# define STM32_TIM2_RES 32 -#endif -#define STM32_TIM3_RES 16 -#define STM32_TIM4_RES 16 -#if defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F30XX) -# define STM32_TIM5_RES 16 -#else -# define STM32_TIM5_RES 32 -#endif -#define STM32_TIM6_RES 16 -#define STM32_TIM7_RES 16 -#define STM32_TIM8_RES 16 -#define STM32_TIM9_RES 16 -#define STM32_TIM10_RES 16 -#define STM32_TIM11_RES 16 -#define STM32_TIM12_RES 16 -#define STM32_TIM13_RES 16 -#define STM32_TIM14_RES 16 - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/* This structure provides the private representation of the "lower-half" - * driver state structure. This structure must be cast-compatible with the - * timer_lowerhalf_s structure. - */ - -struct stm32_lowerhalf_s -{ - const struct timer_ops_s *ops; /* Lower half operations */ - struct stm32_tim_dev_s *tim; /* stm32 timer driver */ - tccb_t callback; /* Current user interrupt callback */ - void *arg; /* Argument passed to upper half callback */ - bool started; /* True: Timer has been started */ - const uint8_t resolution; /* Number of bits in the timer (16 or 32 bits) */ -}; - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -static int stm32_timer_handler(int irq, void * context, void * arg); - -/* "Lower half" driver methods **********************************************/ - -static int stm32_start(struct timer_lowerhalf_s *lower); -static int stm32_stop(struct timer_lowerhalf_s *lower); -static int stm32_settimeout(struct timer_lowerhalf_s *lower, - uint32_t timeout); -static void stm32_setcallback(struct timer_lowerhalf_s *lower, - tccb_t callback, void *arg); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* "Lower half" driver methods */ - -static const struct timer_ops_s g_timer_ops = -{ - .start = stm32_start, - .stop = stm32_stop, - .getstatus = NULL, - .settimeout = stm32_settimeout, - .setcallback = stm32_setcallback, - .ioctl = NULL, -}; - -#ifdef CONFIG_STM32_TIM1 -static struct stm32_lowerhalf_s g_tim1_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM1_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM2 -static struct stm32_lowerhalf_s g_tim2_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM2_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM3 -static struct stm32_lowerhalf_s g_tim3_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM3_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM4 -static struct stm32_lowerhalf_s g_tim4_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM4_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM5 -static struct stm32_lowerhalf_s g_tim5_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM5_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM6 -static struct stm32_lowerhalf_s g_tim6_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM6_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM7 -static struct stm32_lowerhalf_s g_tim7_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM7_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM8 -static struct stm32_lowerhalf_s g_tim8_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM8_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM9 -static struct stm32_lowerhalf_s g_tim9_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM9_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM10 -static struct stm32_lowerhalf_s g_tim10_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM10_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM11 -static struct stm32_lowerhalf_s g_tim11_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM11_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM12 -static struct stm32_lowerhalf_s g_tim12_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM12_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM13 -static struct stm32_lowerhalf_s g_tim13_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM13_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM14 -static struct stm32_lowerhalf_s g_tim14_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM14_RES, -}; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_timer_handler - * - * Description: - * timer interrupt handler - * - * Input Parameters: - * - * Returned Value: - * - ****************************************************************************/ - -static int stm32_timer_handler(int irq, void * context, void * arg) -{ - struct stm32_lowerhalf_s *lower = (struct stm32_lowerhalf_s *) arg; - uint32_t next_interval_us = 0; - - STM32_TIM_ACKINT(lower->tim, ATIM_DIER_UIE); - - if (lower->callback(&next_interval_us, lower->arg)) - { - if (next_interval_us > 0) - { - STM32_TIM_SETPERIOD(lower->tim, next_interval_us); - } - } - else - { - stm32_stop((struct timer_lowerhalf_s *)lower); - } - - return OK; -} - -/**************************************************************************** - * Name: stm32_start - * - * Description: - * Start the timer, resetting the time to the current timeout, - * - * Input Parameters: - * lower - A pointer the publicly visible representation of the - * "lower-half" driver state structure. - * - * Returned Value: - * Zero on success; a negated errno value on failure. - * - ****************************************************************************/ - -static int stm32_start(struct timer_lowerhalf_s *lower) -{ - struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; - - if (!priv->started) - { - STM32_TIM_SETMODE(priv->tim, STM32_TIM_MODE_UP); - - if (priv->callback != NULL) - { - STM32_TIM_SETISR(priv->tim, stm32_timer_handler, priv, 0); - STM32_TIM_ENABLEINT(priv->tim, ATIM_DIER_UIE); - } - - priv->started = true; - return OK; - } - - /* Return EBUSY to indicate that the timer was already running */ - - return -EBUSY; -} - -/**************************************************************************** - * Name: stm32_stop - * - * Description: - * Stop the timer - * - * Input Parameters: - * lower - A pointer the publicly visible representation of the - * "lower-half" driver state structure. - * - * Returned Value: - * Zero on success; a negated errno value on failure. - * - ****************************************************************************/ - -static int stm32_stop(struct timer_lowerhalf_s *lower) -{ - struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; - - if (priv->started) - { - STM32_TIM_SETMODE(priv->tim, STM32_TIM_MODE_DISABLED); - STM32_TIM_DISABLEINT(priv->tim, ATIM_DIER_UIE); - STM32_TIM_SETISR(priv->tim, NULL, NULL, 0); - priv->started = false; - return OK; - } - - /* Return ENODEV to indicate that the timer was not running */ - - return -ENODEV; -} - -/**************************************************************************** - * Name: stm32_settimeout - * - * Description: - * Set a new timeout value (and reset the timer) - * - * Input Parameters: - * lower - A pointer the publicly visible representation of the - * "lower-half" driver state structure. - * timeout - The new timeout value in microseconds. - * - * Returned Value: - * Zero on success; a negated errno value on failure. - * - ****************************************************************************/ - -static int stm32_settimeout(struct timer_lowerhalf_s *lower, - uint32_t timeout) -{ - struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; - uint64_t maxtimeout; - - if (priv->started) - { - return -EPERM; - } - - maxtimeout = (1 << priv->resolution) - 1; - if (timeout > maxtimeout) - { - uint64_t freq = (maxtimeout * 1000000) / timeout; - STM32_TIM_SETCLOCK(priv->tim, freq); - STM32_TIM_SETPERIOD(priv->tim, maxtimeout); - } - else - { - STM32_TIM_SETCLOCK(priv->tim, 1000000); - STM32_TIM_SETPERIOD(priv->tim, timeout); - } - - return OK; -} - -/**************************************************************************** - * Name: stm32_setcallback - * - * Description: - * Call this user provided timeout callback. - * - * Input Parameters: - * lower - A pointer the publicly visible representation of the - * "lower-half" driver state structure. - * callback - The new timer expiration function pointer. If this - * function pointer is NULL, then the reset-on-expiration - * behavior is restored, - * arg - Argument that will be provided in the callback - * - * Returned Value: - * The previous timer expiration function pointer or NULL is there was - * no previous function pointer. - * - ****************************************************************************/ - -static void stm32_setcallback(struct timer_lowerhalf_s *lower, - tccb_t callback, void *arg) -{ - struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; - - irqstate_t flags = enter_critical_section(); - - /* Save the new callback */ - - priv->callback = callback; - priv->arg = arg; - - if (callback != NULL && priv->started) - { - STM32_TIM_SETISR(priv->tim, stm32_timer_handler, priv, 0); - STM32_TIM_ENABLEINT(priv->tim, ATIM_DIER_UIE); - } - else - { - STM32_TIM_DISABLEINT(priv->tim, ATIM_DIER_UIE); - STM32_TIM_SETISR(priv->tim, NULL, NULL, 0); - } - - leave_critical_section(flags); -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_timer_initialize - * - * Description: - * Bind the configuration timer to a timer lower half instance and - * register the timer drivers at 'devpath' - * - * Input Parameters: - * devpath - The full path to the timer device. This should be of the - * form /dev/timer0 - * timer - the timer's number. - * - * Returned Value: - * Zero (OK) is returned on success; A negated errno value is returned - * to indicate the nature of any failure. - * - ****************************************************************************/ - -int stm32_timer_initialize(const char *devpath, int timer) -{ - struct stm32_lowerhalf_s *lower; - - switch (timer) - { -#ifdef CONFIG_STM32_TIM1 - case 1: - lower = &g_tim1_lowerhalf; - break; -#endif -#ifdef CONFIG_STM32_TIM2 - case 2: - lower = &g_tim2_lowerhalf; - break; -#endif -#ifdef CONFIG_STM32_TIM3 - case 3: - lower = &g_tim3_lowerhalf; - break; -#endif -#ifdef CONFIG_STM32_TIM4 - case 4: - lower = &g_tim4_lowerhalf; - break; -#endif -#ifdef CONFIG_STM32_TIM5 - case 5: - lower = &g_tim5_lowerhalf; - break; -#endif -#ifdef CONFIG_STM32_TIM6 - case 6: - lower = &g_tim6_lowerhalf; - break; -#endif -#ifdef CONFIG_STM32_TIM7 - case 7: - lower = &g_tim7_lowerhalf; - break; -#endif -#ifdef CONFIG_STM32_TIM8 - case 8: - lower = &g_tim8_lowerhalf; - break; -#endif -#ifdef CONFIG_STM32_TIM9 - case 9: - lower = &g_tim9_lowerhalf; - break; -#endif -#ifdef CONFIG_STM32_TIM10 - case 10: - lower = &g_tim10_lowerhalf; - break; -#endif -#ifdef CONFIG_STM32_TIM11 - case 11: - lower = &g_tim11_lowerhalf; - break; -#endif -#ifdef CONFIG_STM32_TIM12 - case 12: - lower = &g_tim12_lowerhalf; - break; -#endif -#ifdef CONFIG_STM32_TIM13 - case 13: - lower = &g_tim13_lowerhalf; - break; -#endif -#ifdef CONFIG_STM32_TIM14 - case 14: - lower = &g_tim14_lowerhalf; - break; -#endif - default: - return -ENODEV; - } - - /* Initialize the elements of lower half state structure */ - - lower->started = false; - lower->callback = NULL; - lower->tim = stm32_tim_init(timer); - - if (lower->tim == NULL) - { - return -EINVAL; - } - - /* Register the timer driver as /dev/timerX. The returned value from - * timer_register is a handle that could be used with timer_unregister(). - * REVISIT: The returned handle is discard here. - */ - - void *drvr = timer_register(devpath, - (struct timer_lowerhalf_s *)lower); - if (drvr == NULL) - { - /* The actual cause of the failure may have been a failure to allocate - * perhaps a failure to register the timer driver (such as if the - * 'depath' were not unique). We know here but we return EEXIST to - * indicate the failure (implying the non-unique devpath). - */ - - return -EEXIST; - } - - return OK; -} - -#endif /* CONFIG_TIMER */ diff --git a/arch/arm/src/stm32/stm32_timerisr.c b/arch/arm/src/stm32/stm32_timerisr.c deleted file mode 100644 index c4fa9c76fb601..0000000000000 --- a/arch/arm/src/stm32/stm32_timerisr.c +++ /dev/null @@ -1,196 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_timerisr.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include -#include -#include - -#include "nvic.h" -#include "clock/clock.h" -#include "arm_internal.h" -#include "systick.h" - -#include "chip.h" -#include "stm32.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* The desired timer interrupt frequency is provided by the definition - * CLK_TCK (see include/time.h). CLK_TCK defines the desired number of - * system clock ticks per second. That value is a user configurable setting - * that defaults to 100 (100 ticks per second = 10 MS interval). - * - * The RCC feeds the Cortex System Timer (SysTick) with the AHB clock (HCLK) - * divided by 8. The SysTick can work either with this clock or with the - * Cortex clock (HCLK), configurable in the SysTick Control and Status - * register. - */ - -#undef CONFIG_STM32_SYSTICK_HCLKd8 /* Power up default is HCLK, not HCLK/8 */ - /* And I don't know now to re-configure it yet */ - -#ifdef CONFIG_STM32_SYSTICK_HCLKd8 -# define SYSTICK_CLOCK (STM32_HCLK_FREQUENCY / 8) -#else -# define SYSTICK_CLOCK (STM32_HCLK_FREQUENCY) -#endif - -#define SYSTICK_RELOAD ((SYSTICK_CLOCK / CLK_TCK) - 1) - -/* The size of the reload field is 24 bits. Verify that the reload value - * will fit in the reload register. - */ - -#define SYSTICK_MAX 0x00ffffff -#if SYSTICK_RELOAD > SYSTICK_MAX -# error SYSTICK_RELOAD exceeds the range of the RELOAD register -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Function: stm32_timerisr - * - * Description: - * The timer ISR will perform a variety of services for various portions - * of the systems. - * - ****************************************************************************/ - -#if !defined(CONFIG_ARMV7M_SYSTICK) && !defined(CONFIG_TIMER_ARCH) -static int stm32_timerisr(int irq, uint32_t *regs, void *arg) -{ - /* Process timer interrupt */ - - nxsched_process_timer(); - return 0; -} -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Function: up_adjtime - * - * Description: - * Adjusts timer period. This call is used when adjusting timer period as - * defined in adjtime() function. - * - * Input Parameters: - * ppb - Adjustment in parts per billion (nanoseconds per second). - * Zero is default rate, positive value makes clock run faster - * and negative value slower. - * - * Assumptions: - * Called from within critical section or interrupt context. - ****************************************************************************/ - -#ifdef CONFIG_CLOCK_ADJTIME -void up_adjtime(long ppb) -{ - uint32_t period = SYSTICK_RELOAD; - - if (ppb != 0) - { - period -= (long long)ppb * SYSTICK_RELOAD / 1000000000; - } - - /* Check whether period is at maximum value. */ - - if (period > SYSTICK_MAX) - { - period = SYSTICK_MAX; - } - - putreg32(period, NVIC_SYSTICK_RELOAD); -} -#endif - -/**************************************************************************** - * Function: up_timer_initialize - * - * Description: - * This function is called during start-up to initialize - * the timer interrupt. - * - ****************************************************************************/ - -void up_timer_initialize(void) -{ - uint32_t regval; - - /* Set the SysTick interrupt to the default priority */ - - regval = getreg32(NVIC_SYSH12_15_PRIORITY); - regval &= ~NVIC_SYSH_PRIORITY_PR15_MASK; - regval |= (NVIC_SYSH_PRIORITY_DEFAULT << NVIC_SYSH_PRIORITY_PR15_SHIFT); - putreg32(regval, NVIC_SYSH12_15_PRIORITY); - - /* Make sure that the SYSTICK clock source is set correctly */ - -#if 0 /* Does not work. Comes up with HCLK source and I can't change it */ - regval = getreg32(NVIC_SYSTICK_CTRL); -#ifdef CONFIG_STM32_SYSTICK_HCLKd8 - regval &= ~NVIC_SYSTICK_CTRL_CLKSOURCE; -#else - regval |= NVIC_SYSTICK_CTRL_CLKSOURCE; -#endif - putreg32(regval, NVIC_SYSTICK_CTRL); -#endif - -#if defined(CONFIG_ARMV7M_SYSTICK) && defined(CONFIG_TIMER_ARCH) - up_timer_set_lowerhalf(systick_initialize(true, STM32_HCLK_FREQUENCY, -1)); -#else - /* Configure SysTick to interrupt at the requested rate */ - - putreg32(SYSTICK_RELOAD, NVIC_SYSTICK_RELOAD); - - /* Attach the timer interrupt vector */ - - irq_attach(STM32_IRQ_SYSTICK, (xcpt_t)stm32_timerisr, NULL); - - /* Enable SysTick interrupts */ - - putreg32((NVIC_SYSTICK_CTRL_CLKSOURCE | NVIC_SYSTICK_CTRL_TICKINT | - NVIC_SYSTICK_CTRL_ENABLE), NVIC_SYSTICK_CTRL); - - /* And enable the timer interrupt */ - - up_enable_irq(STM32_IRQ_SYSTICK); -#endif -} diff --git a/arch/arm/src/stm32/stm32_uart.h b/arch/arm/src/stm32/stm32_uart.h deleted file mode 100644 index 3723edd4c1e22..0000000000000 --- a/arch/arm/src/stm32/stm32_uart.h +++ /dev/null @@ -1,668 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_uart.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_STC_STM32_STM32_UART_H -#define __ARCH_ARM_STC_STM32_STM32_UART_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include - -#include "chip.h" - -#if defined(CONFIG_STM32_STM32L15XX) -# include "hardware/stm32l15xxx_uart.h" -#elif defined(CONFIG_STM32_STM32F10XX) -# include "hardware/stm32f10xxx_uart.h" -#elif defined(CONFIG_STM32_STM32F20XX) -# include "hardware/stm32f20xxx_uart.h" -#elif defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) || \ - defined(CONFIG_STM32_STM32F37XX) -# include "hardware/stm32f30xxx_uart.h" -#elif defined(CONFIG_STM32_STM32F4XXX) -# include "hardware/stm32f40xxx_uart.h" -#elif defined(CONFIG_STM32_STM32G4XXX) -# include "hardware/stm32g4xxxx_uart.h" -#else -# error "Unsupported STM32 UART" -#endif - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Make sure that we have not enabled more U[S]ARTs than are supported by the - * device. - */ - -#if STM32_NUSART < 8 || !defined(CONFIG_STM32_HAVE_UART8) -# undef CONFIG_STM32_UART8 -#endif -#if STM32_NUSART < 7 || !defined(CONFIG_STM32_HAVE_UART7) -# undef CONFIG_STM32_UART7 -#endif -#if STM32_NUSART < 6 || !defined(CONFIG_STM32_HAVE_USART6) -# undef CONFIG_STM32_USART6 -#endif -#if STM32_NUSART < 5 || !defined(CONFIG_STM32_HAVE_UART5) -# undef CONFIG_STM32_UART5 -#endif -#if STM32_NUSART < 4 || !defined(CONFIG_STM32_HAVE_UART4) -# undef CONFIG_STM32_UART4 -#endif -#if STM32_NUSART < 3 || !defined(CONFIG_STM32_HAVE_USART3) -# undef CONFIG_STM32_USART3 -#endif -#if STM32_NUSART < 2 -# undef CONFIG_STM32_USART2 -#endif -#if STM32_NUSART < 1 -# undef CONFIG_STM32_USART1 -#endif - -#if !defined(CONFIG_STM32_HAVE_LPUART1) -# undef CONFIG_STM32_LPUART1 -#endif - -/* Sanity checks */ -#if !defined(CONFIG_STM32_LPUART1) -# undef CONFIG_STM32_LPUART1_SERIALDRIVER -# undef CONFIG_STM32_LPUART1_1WIREDRIVER -#endif -#if !defined(CONFIG_STM32_USART1) -# undef CONFIG_STM32_USART1_SERIALDRIVER -# undef CONFIG_STM32_USART1_1WIREDRIVER -#endif -#if !defined(CONFIG_STM32_USART2) -# undef CONFIG_STM32_USART2_SERIALDRIVER -# undef CONFIG_STM32_USART2_1WIREDRIVER -#endif -#if !defined(CONFIG_STM32_USART3) -# undef CONFIG_STM32_USART3_SERIALDRIVER -# undef CONFIG_STM32_USART3_1WIREDRIVER -#endif -#if !defined(CONFIG_STM32_UART4) -# undef CONFIG_STM32_UART4_SERIALDRIVER -# undef CONFIG_STM32_UART4_1WIREDRIVER -#endif -#if !defined(CONFIG_STM32_UART5) -# undef CONFIG_STM32_UART5_SERIALDRIVER -# undef CONFIG_STM32_UART5_1WIREDRIVER -#endif -#if !defined(CONFIG_STM32_USART6) -# undef CONFIG_STM32_USART6_SERIALDRIVER -# undef CONFIG_STM32_USART6_1WIREDRIVER -#endif -#if !defined(CONFIG_STM32_UART7) -# undef CONFIG_STM32_UART7_SERIALDRIVER -# undef CONFIG_STM32_UART7_1WIREDRIVER -#endif -#if !defined(CONFIG_STM32_UART8) -# undef CONFIG_STM32_UART8_SERIALDRIVER -# undef CONFIG_STM32_UART8_1WIREDRIVER -#endif - -/* Check 1-Wire and U(S)ART conflicts */ - -#if defined(CONFIG_STM32_USART1_1WIREDRIVER) && defined(CONFIG_STM32_USART1_SERIALDRIVER) -# error Both CONFIG_STM32_USART1_1WIREDRIVER and CONFIG_STM32_USART1_SERIALDRIVER defined -# undef CONFIG_STM32_USART1_1WIREDRIVER -#endif -#if defined(CONFIG_STM32_USART2_1WIREDRIVER) && defined(CONFIG_STM32_USART2_SERIALDRIVER) -# error Both CONFIG_STM32_USART2_1WIREDRIVER and CONFIG_STM32_USART2_SERIALDRIVER defined -# undef CONFIG_STM32_USART2_1WIREDRIVER -#endif -#if defined(CONFIG_STM32_USART3_1WIREDRIVER) && defined(CONFIG_STM32_USART3_SERIALDRIVER) -# error Both CONFIG_STM32_USART3_1WIREDRIVER and CONFIG_STM32_USART3_SERIALDRIVER defined -# undef CONFIG_STM32_USART3_1WIREDRIVER -#endif -#if defined(CONFIG_STM32_UART4_1WIREDRIVER) && defined(CONFIG_STM32_UART4_SERIALDRIVER) -# error Both CONFIG_STM32_UART4_1WIREDRIVER and CONFIG_STM32_UART4_SERIALDRIVER defined -# undef CONFIG_STM32_UART4_1WIREDRIVER -#endif -#if defined(CONFIG_STM32_UART5_1WIREDRIVER) && defined(CONFIG_STM32_UART5_SERIALDRIVER) -# error Both CONFIG_STM32_UART5_1WIREDRIVER and CONFIG_STM32_UART5_SERIALDRIVER defined -# undef CONFIG_STM32_UART5_1WIREDRIVER -#endif -#if defined(CONFIG_STM32_USART6_1WIREDRIVER) && defined(CONFIG_STM32_USART6_SERIALDRIVER) -# error Both CONFIG_STM32_USART6_1WIREDRIVER and CONFIG_STM32_USART6_SERIALDRIVER defined -# undef CONFIG_STM32_USART6_1WIREDRIVER -#endif -#if defined(CONFIG_STM32_UART7_1WIREDRIVER) && defined(CONFIG_STM32_UART7_SERIALDRIVER) -# error Both CONFIG_STM32_UART7_1WIREDRIVER and CONFIG_STM32_UART7_SERIALDRIVER defined -# undef CONFIG_STM32_UART7_1WIREDRIVER -#endif -#if defined(CONFIG_STM32_UART8_1WIREDRIVER) && defined(CONFIG_STM32_UART8_SERIALDRIVER) -# error Both CONFIG_STM32_UART8_1WIREDRIVER and CONFIG_STM32_UART8_SERIALDRIVER defined -# undef CONFIG_STM32_UART8_1WIREDRIVER -#endif - -/* Is the serial driver enabled? */ - -#if defined(CONFIG_STM32_USART1_SERIALDRIVER) || defined(CONFIG_STM32_USART2_SERIALDRIVER) || \ - defined(CONFIG_STM32_USART3_SERIALDRIVER) || defined(CONFIG_STM32_UART4_SERIALDRIVER) || \ - defined(CONFIG_STM32_UART5_SERIALDRIVER) || defined(CONFIG_STM32_USART6_SERIALDRIVER) || \ - defined(CONFIG_STM32_UART7_SERIALDRIVER) || defined(CONFIG_STM32_UART8_SERIALDRIVER) || \ - defined(CONFIG_STM32_LPUART1_SERIALDRIVER) -# define HAVE_SERIALDRIVER 1 -#endif - -/* Is the 1-Wire driver? */ - -#if defined(CONFIG_STM32_USART1_1WIREDRIVER) || defined(CONFIG_STM32_USART2_1WIREDRIVER) || \ - defined(CONFIG_STM32_USART3_1WIREDRIVER) || defined(CONFIG_STM32_UART4_1WIREDRIVER) || \ - defined(CONFIG_STM32_UART5_1WIREDRIVER) || defined(CONFIG_STM32_USART6_1WIREDRIVER) || \ - defined(CONFIG_STM32_UART7_1WIREDRIVER) || defined(CONFIG_STM32_UART8_1WIREDRIVER) -# define HAVE_1WIREDRIVER 1 -#endif - -/* Is there a serial console? */ - -#if defined(CONFIG_USART1_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART1_SERIALDRIVER) -# undef CONFIG_USART2_SERIAL_CONSOLE -# undef CONFIG_USART3_SERIAL_CONSOLE -# undef CONFIG_UART4_SERIAL_CONSOLE -# undef CONFIG_UART5_SERIAL_CONSOLE -# undef CONFIG_USART6_SERIAL_CONSOLE -# undef CONFIG_UART7_SERIAL_CONSOLE -# undef CONFIG_UART8_SERIAL_CONSOLE -# undef CONFIG_LPUART1_SERIAL_CONSOLE -# define CONSOLE_UART 1 -# define CONSOLE_LPUART 0 -# define HAVE_CONSOLE 1 -#elif defined(CONFIG_USART2_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART2_SERIALDRIVER) -# undef CONFIG_USART1_SERIAL_CONSOLE -# undef CONFIG_USART3_SERIAL_CONSOLE -# undef CONFIG_UART4_SERIAL_CONSOLE -# undef CONFIG_UART5_SERIAL_CONSOLE -# undef CONFIG_USART6_SERIAL_CONSOLE -# undef CONFIG_UART7_SERIAL_CONSOLE -# undef CONFIG_UART8_SERIAL_CONSOLE -# undef CONFIG_LPUART1_SERIAL_CONSOLE -# define CONSOLE_UART 2 -# define CONSOLE_LPUART 0 -# define HAVE_CONSOLE 1 -#elif defined(CONFIG_USART3_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART3_SERIALDRIVER) -# undef CONFIG_USART1_SERIAL_CONSOLE -# undef CONFIG_USART2_SERIAL_CONSOLE -# undef CONFIG_UART4_SERIAL_CONSOLE -# undef CONFIG_UART5_SERIAL_CONSOLE -# undef CONFIG_USART6_SERIAL_CONSOLE -# undef CONFIG_UART7_SERIAL_CONSOLE -# undef CONFIG_UART8_SERIAL_CONSOLE -# undef CONFIG_LPUART1_SERIAL_CONSOLE -# define CONSOLE_UART 3 -# define CONSOLE_LPUART 0 -# define HAVE_CONSOLE 1 -#elif defined(CONFIG_UART4_SERIAL_CONSOLE) && defined(CONFIG_STM32_UART4_SERIALDRIVER) -# undef CONFIG_USART1_SERIAL_CONSOLE -# undef CONFIG_USART2_SERIAL_CONSOLE -# undef CONFIG_USART3_SERIAL_CONSOLE -# undef CONFIG_UART5_SERIAL_CONSOLE -# undef CONFIG_USART6_SERIAL_CONSOLE -# undef CONFIG_UART7_SERIAL_CONSOLE -# undef CONFIG_UART8_SERIAL_CONSOLE -# undef CONFIG_LPUART1_SERIAL_CONSOLE -# define CONSOLE_UART 4 -# define CONSOLE_LPUART 0 -# define HAVE_CONSOLE 1 -#elif defined(CONFIG_UART5_SERIAL_CONSOLE) && defined(CONFIG_STM32_UART5_SERIALDRIVER) -# undef CONFIG_USART1_SERIAL_CONSOLE -# undef CONFIG_USART2_SERIAL_CONSOLE -# undef CONFIG_USART3_SERIAL_CONSOLE -# undef CONFIG_UART4_SERIAL_CONSOLE -# undef CONFIG_USART6_SERIAL_CONSOLE -# undef CONFIG_UART7_SERIAL_CONSOLE -# undef CONFIG_UART8_SERIAL_CONSOLE -# undef CONFIG_LPUART1_SERIAL_CONSOLE -# define CONSOLE_UART 5 -# define CONSOLE_LPUART 0 -# define HAVE_CONSOLE 1 -#elif defined(CONFIG_USART6_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART6_SERIALDRIVER) -# undef CONFIG_USART1_SERIAL_CONSOLE -# undef CONFIG_USART2_SERIAL_CONSOLE -# undef CONFIG_USART3_SERIAL_CONSOLE -# undef CONFIG_UART4_SERIAL_CONSOLE -# undef CONFIG_UART5_SERIAL_CONSOLE -# undef CONFIG_UART7_SERIAL_CONSOLE -# undef CONFIG_UART8_SERIAL_CONSOLE -# undef CONFIG_LPUART1_SERIAL_CONSOLE -# define CONSOLE_UART 6 -# define CONSOLE_LPUART 0 -# define HAVE_CONSOLE 1 -#elif defined(CONFIG_UART7_SERIAL_CONSOLE) && defined(CONFIG_STM32_UART7_SERIALDRIVER) -# undef CONFIG_USART1_SERIAL_CONSOLE -# undef CONFIG_USART2_SERIAL_CONSOLE -# undef CONFIG_USART3_SERIAL_CONSOLE -# undef CONFIG_UART4_SERIAL_CONSOLE -# undef CONFIG_UART5_SERIAL_CONSOLE -# undef CONFIG_USART6_SERIAL_CONSOLE -# undef CONFIG_UART8_SERIAL_CONSOLE -# undef CONFIG_LPUART1_SERIAL_CONSOLE -# define CONSOLE_UART 7 -# define CONSOLE_LPUART 0 -# define HAVE_CONSOLE 1 -#elif defined(CONFIG_UART8_SERIAL_CONSOLE) && defined(CONFIG_STM32_UART8_SERIALDRIVER) -# undef CONFIG_USART1_SERIAL_CONSOLE -# undef CONFIG_USART2_SERIAL_CONSOLE -# undef CONFIG_USART3_SERIAL_CONSOLE -# undef CONFIG_UART4_SERIAL_CONSOLE -# undef CONFIG_UART5_SERIAL_CONSOLE -# undef CONFIG_USART6_SERIAL_CONSOLE -# undef CONFIG_UART7_SERIAL_CONSOLE -# undef CONFIG_LPUART1_SERIAL_CONSOLE -# define CONSOLE_UART 8 -# define CONSOLE_LPUART 0 -# define HAVE_CONSOLE 1 -#elif defined(CONFIG_LPUART1_SERIAL_CONSOLE) && defined(CONFIG_STM32_LPUART1_SERIALDRIVER) -# undef CONFIG_USART1_SERIAL_CONSOLE -# undef CONFIG_USART2_SERIAL_CONSOLE -# undef CONFIG_USART3_SERIAL_CONSOLE -# undef CONFIG_UART4_SERIAL_CONSOLE -# undef CONFIG_UART5_SERIAL_CONSOLE -# undef CONFIG_USART6_SERIAL_CONSOLE -# undef CONFIG_UART7_SERIAL_CONSOLE -# undef CONFIG_UART8_SERIAL_CONSOLE -# define CONSOLE_LPUART 1 -# define CONSOLE_UART 0 -# define HAVE_CONSOLE 1 -#else -# undef CONFIG_USART1_SERIAL_CONSOLE -# undef CONFIG_USART2_SERIAL_CONSOLE -# undef CONFIG_USART3_SERIAL_CONSOLE -# undef CONFIG_UART4_SERIAL_CONSOLE -# undef CONFIG_UART5_SERIAL_CONSOLE -# undef CONFIG_USART6_SERIAL_CONSOLE -# undef CONFIG_UART7_SERIAL_CONSOLE -# undef CONFIG_UART8_SERIAL_CONSOLE -# undef CONFIG_LPUART1_SERIAL_CONSOLE -# define CONSOLE_UART 0 -# define CONSOLE_LPUART 0 -# undef HAVE_CONSOLE -#endif - -/* DMA support is only provided if CONFIG_ARCH_DMA is in the - * NuttX configuration - */ - -#if !defined(HAVE_SERIALDRIVER) || !defined(CONFIG_ARCH_DMA) -# undef CONFIG_USART1_RXDMA -# undef CONFIG_USART1_TXDMA -# undef CONFIG_USART2_RXDMA -# undef CONFIG_USART2_TXDMA -# undef CONFIG_USART3_RXDMA -# undef CONFIG_USART3_TXDMA -# undef CONFIG_UART4_RXDMA -# undef CONFIG_UART4_TXDMA -# undef CONFIG_UART5_RXDMA -# undef CONFIG_UART5_TXDMA -# undef CONFIG_USART6_RXDMA -# undef CONFIG_USART6_TXDMA -# undef CONFIG_UART7_RXDMA -# undef CONFIG_UART7_TXDMA -# undef CONFIG_UART8_RXDMA -# undef CONFIG_UART8_TXDMA -#endif - -/* Disable the DMA configuration on all unused USARTs */ - -#ifndef CONFIG_STM32_LPUART1_SERIALDRIVER -# undef CONFIG_LPUART1_RXDMA -# undef CONFIG_LPUART1_TXDMA -#endif - -#ifndef CONFIG_STM32_USART1_SERIALDRIVER -# undef CONFIG_USART1_RXDMA -# undef CONFIG_USART1_TXDMA -#endif - -#ifndef CONFIG_STM32_USART2_SERIALDRIVER -# undef CONFIG_USART2_RXDMA -# undef CONFIG_USART2_TXDMA -#endif - -#ifndef CONFIG_STM32_USART3_SERIALDRIVER -# undef CONFIG_USART3_RXDMA -# undef CONFIG_USART3_TXDMA -#endif - -#ifndef CONFIG_STM32_UART4_SERIALDRIVER -# undef CONFIG_UART4_RXDMA -# undef CONFIG_UART4_TXDMA -#endif - -#ifndef CONFIG_STM32_UART5_SERIALDRIVER -# undef CONFIG_UART5_RXDMA -# undef CONFIG_UART5_TXDMA -#endif - -#ifndef CONFIG_STM32_USART6_SERIALDRIVER -# undef CONFIG_USART6_RXDMA -# undef CONFIG_USART6_TXDMA -#endif - -#ifndef CONFIG_STM32_UART7_SERIALDRIVER -# undef CONFIG_UART7_RXDMA -# undef CONFIG_UART7_TXDMA -#endif - -#ifndef CONFIG_STM32_UART8_SERIALDRIVER -# undef CONFIG_UART8_RXDMA -# undef CONFIG_UART8_TXDMA -#endif - -/* Is DMA available on any (enabled) USART? */ - -#undef SERIAL_HAVE_RXDMA -#if defined(CONFIG_USART1_RXDMA) || defined(CONFIG_USART2_RXDMA) || \ - defined(CONFIG_USART3_RXDMA) || defined(CONFIG_UART4_RXDMA) || \ - defined(CONFIG_UART5_RXDMA) || defined(CONFIG_USART6_RXDMA) || \ - defined(CONFIG_UART7_RXDMA) || defined(CONFIG_UART8_RXDMA) || \ - defined(CONFIG_LPUART1_RXDMA) -# define SERIAL_HAVE_RXDMA 1 -#endif - -/* Is TX DMA available on any (enabled) USART? */ - -#undef SERIAL_HAVE_TXDMA -#if defined(CONFIG_USART1_TXDMA) || defined(CONFIG_USART2_TXDMA) || \ - defined(CONFIG_USART3_TXDMA) || defined(CONFIG_UART4_TXDMA) || \ - defined(CONFIG_UART5_TXDMA) || defined(CONFIG_USART6_TXDMA) || \ - defined(CONFIG_UART7_TXDMA) || defined(CONFIG_UART8_TXDMA) || \ - defined(CONFIG_LPUART1_TXDMA) -# define SERIAL_HAVE_TXDMA 1 -#endif - -/* Is RX DMA used on the console UART? */ - -#undef SERIAL_HAVE_CONSOLE_RXDMA -#if defined(CONFIG_USART1_SERIAL_CONSOLE) && defined(CONFIG_USART1_RXDMA) -# define SERIAL_HAVE_CONSOLE_RXDMA 1 -#elif defined(CONFIG_USART2_SERIAL_CONSOLE) && defined(CONFIG_USART2_RXDMA) -# define SERIAL_HAVE_CONSOLE_RXDMA 1 -#elif defined(CONFIG_USART3_SERIAL_CONSOLE) && defined(CONFIG_USART3_RXDMA) -# define SERIAL_HAVE_CONSOLE_RXDMA 1 -#elif defined(CONFIG_UART4_SERIAL_CONSOLE) && defined(CONFIG_UART4_RXDMA) -# define SERIAL_HAVE_CONSOLE_RXDMA 1 -#elif defined(CONFIG_UART5_SERIAL_CONSOLE) && defined(CONFIG_UART5_RXDMA) -# define SERIAL_HAVE_CONSOLE_RXDMA 1 -#elif defined(CONFIG_USART6_SERIAL_CONSOLE) && defined(CONFIG_USART6_RXDMA) -# define SERIAL_HAVE_CONSOLE_RXDMA 1 -#elif defined(CONFIG_UART7_SERIAL_CONSOLE) && defined(CONFIG_UART7_RXDMA) -# define SERIAL_HAVE_CONSOLE_RXDMA 1 -#elif defined(CONFIG_UART8_SERIAL_CONSOLE) && defined(CONFIG_UART8_RXDMA) -# define SERIAL_HAVE_CONSOLE_RXDMA 1 -#elif defined(CONFIG_LPUART1_SERIAL_CONSOLE) && defined(CONFIG_LPUART1_RXDMA) -# define SERIAL_HAVE_CONSOLE_RXDMA 1 -#endif - -/* Is TX DMA used on the console UART? */ - -#undef SERIAL_HAVE_CONSOLE_TXDMA -#if defined(CONFIG_USART1_SERIAL_CONSOLE) && defined(CONFIG_USART1_TXDMA) -# define SERIAL_HAVE_CONSOLE_TXDMA 1 -#elif defined(CONFIG_USART2_SERIAL_CONSOLE) && defined(CONFIG_USART2_TXDMA) -# define SERIAL_HAVE_CONSOLE_TXDMA 1 -#elif defined(CONFIG_USART3_SERIAL_CONSOLE) && defined(CONFIG_USART3_TXDMA) -# define SERIAL_HAVE_CONSOLE_TXDMA 1 -#elif defined(CONFIG_UART4_SERIAL_CONSOLE) && defined(CONFIG_UART4_TXDMA) -# define SERIAL_HAVE_CONSOLE_TXDMA 1 -#elif defined(CONFIG_UART5_SERIAL_CONSOLE) && defined(CONFIG_UART5_TXDMA) -# define SERIAL_HAVE_CONSOLE_TXDMA 1 -#elif defined(CONFIG_USART6_SERIAL_CONSOLE) && defined(CONFIG_USART6_TXDMA) -# define SERIAL_HAVE_CONSOLE_TXDMA 1 -#elif defined(CONFIG_UART7_SERIAL_CONSOLE) && defined(CONFIG_UART7_TXDMA) -# define SERIAL_HAVE_CONSOLE_TXDMA 1 -#elif defined(CONFIG_UART8_SERIAL_CONSOLE) && defined(CONFIG_UART8_TXDMA) -# define SERIAL_HAVE_CONSOLE_TXDMA 1 -#elif defined(CONFIG_LPUART1_SERIAL_CONSOLE) && defined(CONFIG_LPUART1_TXDMA) -# define SERIAL_HAVE_CONSOLE_TXDMA 1 -#endif - -/* Is RX DMA used on all (enabled) USARTs */ - -#define SERIAL_HAVE_ONLY_RXDMA 1 -#if defined(CONFIG_STM32_USART1) && !defined(CONFIG_USART1_RXDMA) -# undef SERIAL_HAVE_ONLY_RXDMA -#elif defined(CONFIG_STM32_USART2) && !defined(CONFIG_USART2_RXDMA) -# undef SERIAL_HAVE_ONLY_RXDMA -#elif defined(CONFIG_STM32_USART3) && !defined(CONFIG_USART3_RXDMA) -# undef SERIAL_HAVE_ONLY_RXDMA -#elif defined(CONFIG_STM32_UART4) && !defined(CONFIG_UART4_RXDMA) -# undef SERIAL_HAVE_ONLY_RXDMA -#elif defined(CONFIG_STM32_UART5) && !defined(CONFIG_UART5_RXDMA) -# undef SERIAL_HAVE_ONLY_RXDMA -#elif defined(CONFIG_STM32_USART6) && !defined(CONFIG_USART6_RXDMA) -# undef SERIAL_HAVE_ONLY_RXDMA -#elif defined(CONFIG_STM32_UART7) && !defined(CONFIG_UART7_RXDMA) -# undef SERIAL_HAVE_ONLY_RXDMA -#elif defined(CONFIG_STM32_UART8) && !defined(CONFIG_UART8_RXDMA) -# undef SERIAL_HAVE_ONLY_RXDMA -#elif defined(CONFIG_STM32_LPUART1) && !defined(CONFIG_LPUART1_RXDMA) -# undef SERIAL_HAVE_ONLY_RXDMA -#endif - -/* Is TX DMA used on all (enabled) USARTs */ - -#define SERIAL_HAVE_ONLY_TXDMA 1 -#if defined(CONFIG_STM32_USART1) && !defined(CONFIG_USART1_TXDMA) -# undef SERIAL_HAVE_ONLY_TXDMA -#elif defined(CONFIG_STM32_USART2) && !defined(CONFIG_USART2_TXDMA) -# undef SERIAL_HAVE_ONLY_TXDMA -#elif defined(CONFIG_STM32_USART3) && !defined(CONFIG_USART3_TXDMA) -# undef SERIAL_HAVE_ONLY_TXDMA -#elif defined(CONFIG_STM32_UART4) && !defined(CONFIG_UART4_TXDMA) -# undef SERIAL_HAVE_ONLY_TXDMA -#elif defined(CONFIG_STM32_UART5) && !defined(CONFIG_UART5_TXDMA) -# undef SERIAL_HAVE_ONLY_TXDMA -#elif defined(CONFIG_STM32_USART6) && !defined(CONFIG_USART6_TXDMA) -# undef SERIAL_HAVE_ONLY_TXDMA -#elif defined(CONFIG_STM32_UART7) && !defined(CONFIG_UART7_TXDMA) -# undef SERIAL_HAVE_ONLY_TXDMA -#elif defined(CONFIG_STM32_UART8) && !defined(CONFIG_UART8_TXDMA) -# undef SERIAL_HAVE_ONLY_TXDMA -#elif defined(CONFIG_STM32_LPUART1) && !defined(CONFIG_LPUART1_TXDMA) -# undef SERIAL_HAVE_ONLY_TXDMA -#endif - -#undef SERIAL_HAVE_ONLY_DMA -#if defined(SERIAL_HAVE_ONLY_RXDMA) && defined(SERIAL_HAVE_ONLY_TXDMA) -# define SERIAL_HAVE_ONLY_DMA 1 -#endif - -/* No DMA ops */ - -#undef SERIAL_HAVE_NODMA_OPS -#if defined(CONFIG_STM32_USART1) && !defined(CONFIG_USART1_RXDMA) && \ - !defined(CONFIG_USART1_TXDMA) -# define SERIAL_HAVE_NODMA_OPS -#elif defined(CONFIG_STM32_USART2) && !defined(CONFIG_USART2_RXDMA) && \ - !defined(CONFIG_USART2_TXDMA) -# define SERIAL_HAVE_NODMA_OPS -#elif defined(CONFIG_STM32_USART3) && !defined(CONFIG_USART3_RXDMA) && \ - !defined(CONFIG_USART3_TXDMA) -# define SERIAL_HAVE_NODMA_OPS -#elif defined(CONFIG_STM32_UART4) && !defined(CONFIG_UART4_RXDMA) && \ - !defined(CONFIG_UART4_TXDMA) -# define SERIAL_HAVE_NODMA_OPS -#elif defined(CONFIG_STM32_UART5) && !defined(CONFIG_UART5_RXDMA) && \ - !defined(CONFIG_UART5_TXDMA) -# define SERIAL_HAVE_NODMA_OPS -#elif defined(CONFIG_STM32_USART6) && !defined(CONFIG_USART6_RXDMA) && \ - !defined(CONFIG_USART6_TXDMA) -# define SERIAL_HAVE_NODMA_OPS -#elif defined(CONFIG_STM32_UART7) && !defined(CONFIG_UART7_RXDMA) && \ - !defined(CONFIG_UART7_TXDMA) -# define SERIAL_HAVE_NODMA_OPS -#elif defined(CONFIG_STM32_UART8) && !defined(CONFIG_UART8_RXDMA) && \ - !defined(CONFIG_UART8_TXDMA) -# define SERIAL_HAVE_NODMA_OPS -#elif defined(CONFIG_STM32_LPUART1) && !defined(CONFIG_LPUART1_RXDMA) && \ - !defined(CONFIG_LPUART1_TXDMA) -# define SERIAL_HAVE_NODMA_OPS -#endif - -/* RX+TX DMA ops */ - -#undef SERIAL_HAVE_RXTXDMA_OPS -#if defined(CONFIG_USART1_RXDMA) && defined(CONFIG_USART1_TXDMA) -# define SERIAL_HAVE_RXTXDMA_OPS -#elif defined(CONFIG_USART2_RXDMA) && defined(CONFIG_USART2_TXDMA) -# define SERIAL_HAVE_RXTXDMA_OPS -#elif defined(CONFIG_USART3_RXDMA) && defined(CONFIG_USART3_TXDMA) -# define SERIAL_HAVE_RXTXDMA_OPS -#elif defined(CONFIG_UART4_RXDMA) && defined(CONFIG_UART4_TXDMA) -# define SERIAL_HAVE_RXTXDMA_OPS -#elif defined(CONFIG_UART5_RXDMA) && defined(CONFIG_UART5_TXDMA) -# define SERIAL_HAVE_RXTXDMA_OPS -#elif defined(CONFIG_USART6_RXDMA) && defined(CONFIG_USART6_TXDMA) -# define SERIAL_HAVE_RXTXDMA_OPS -#elif defined(CONFIG_UART7_RXDMA) && defined(CONFIG_UART7_TXDMA) -# define SERIAL_HAVE_RXTXDMA_OPS -#elif defined(CONFIG_UART8_RXDMA) && defined(CONFIG_UART8_TXDMA) -# define SERIAL_HAVE_RXTXDMA_OPS -#elif defined(CONFIG_LPUART1_RXDMA) && defined(CONFIG_LPUART1_TXDMA) -# define SERIAL_HAVE_RXTXDMA_OPS -#endif - -/* TX DMA ops */ - -#undef SERIAL_HAVE_TXDMA_OPS -#if !defined(CONFIG_USART1_RXDMA) && defined(CONFIG_USART1_TXDMA) -# define SERIAL_HAVE_TXDMA_OPS -#elif !defined(CONFIG_USART2_RXDMA) && defined(CONFIG_USART2_TXDMA) -# define SERIAL_HAVE_TXDMA_OPS -#elif !defined(CONFIG_USART3_RXDMA) && defined(CONFIG_USART3_TXDMA) -# define SERIAL_HAVE_TXDMA_OPS -#elif !defined(CONFIG_UART4_RXDMA) && defined(CONFIG_UART4_TXDMA) -# define SERIAL_HAVE_TXDMA_OPS -#elif !defined(CONFIG_UART5_RXDMA) && defined(CONFIG_UART5_TXDMA) -# define SERIAL_HAVE_TXDMA_OPS -#elif !defined(CONFIG_USART6_RXDMA) && defined(CONFIG_USART6_TXDMA) -# define SERIAL_HAVE_TXDMA_OPS -#elif !defined(CONFIG_UART7_RXDMA) && defined(CONFIG_UART7_TXDMA) -# define SERIAL_HAVE_TXDMA_OPS -#elif !defined(CONFIG_UART8_RXDMA) && defined(CONFIG_UART8_TXDMA) -# define SERIAL_HAVE_TXDMA_OPS -#elif !defined(CONFIG_LPUART1_RXDMA) && defined(CONFIG_LPUART1_TXDMA) -# define SERIAL_HAVE_TXDMA_OPS -#endif - -/* RX DMA ops */ - -#undef SERIAL_HAVE_RXDMA_OPS -#if defined(CONFIG_USART1_RXDMA) && !defined(CONFIG_USART1_TXDMA) -# define SERIAL_HAVE_RXDMA_OPS -#elif defined(CONFIG_USART2_RXDMA) && !defined(CONFIG_USART2_TXDMA) -# define SERIAL_HAVE_RXDMA_OPS -#elif defined(CONFIG_USART3_RXDMA) && !defined(CONFIG_USART3_TXDMA) -# define SERIAL_HAVE_RXDMA_OPS -#elif defined(CONFIG_UART4_RXDMA) && !defined(CONFIG_UART4_TXDMA) -# define SERIAL_HAVE_RXDMA_OPS -#elif defined(CONFIG_UART5_RXDMA) && !defined(CONFIG_UART5_TXDMA) -# define SERIAL_HAVE_RXDMA_OPS -#elif defined(CONFIG_USART6_RXDMA) && !defined(CONFIG_USART6_TXDMA) -# define SERIAL_HAVE_RXDMA_OPS -#elif defined(CONFIG_UART7_RXDMA) && !defined(CONFIG_UART7_TXDMA) -# define SERIAL_HAVE_RXDMA_OPS -#elif defined(CONFIG_UART8_RXDMA) && !defined(CONFIG_UART8_TXDMA) -# define SERIAL_HAVE_RXDMA_OPS -#elif defined(CONFIG_LPUART1_RXDMA) && !defined(CONFIG_LPUART1_TXDMA) -# define SERIAL_HAVE_RXDMA_OPS -#endif - -/* Is RS-485 used? */ - -#if defined(CONFIG_USART1_RS485) || defined(CONFIG_USART2_RS485) || \ - defined(CONFIG_USART3_RS485) || defined(CONFIG_UART4_RS485) || \ - defined(CONFIG_UART5_RS485) || defined(CONFIG_USART6_RS485) || \ - defined(CONFIG_UART7_RS485) || defined(CONFIG_UART8_RS485) || \ - defined(CONFIG_LPUART1_RS485) -# define HAVE_RS485 1 -#endif - -#ifdef HAVE_RS485 -# define USART_CR1_USED_INTS (USART_CR1_RXNEIE | USART_CR1_TXEIE | USART_CR1_PEIE | USART_CR1_TCIE) -#else -# define USART_CR1_USED_INTS (USART_CR1_RXNEIE | USART_CR1_TXEIE | USART_CR1_PEIE) -#endif - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -#ifndef __ASSEMBLY__ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Public Functions Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_serial_get_uart - * - * Description: - * Get serial driver structure for STM32 USART - * - ****************************************************************************/ - -uart_dev_t *stm32_serial_get_uart(int uart_num); - -/**************************************************************************** - * Name: stm32_serial_dma_poll - * - * Description: - * Must be called periodically if any STM32 UART is configured for DMA. - * The DMA callback is triggered for each fifo size/2 bytes, but this can - * result in some bytes being transferred but not collected if the incoming - * data is not a whole multiple of half the FIFO size. - * - * May be safely called from either interrupt or thread context. - * - ****************************************************************************/ - -#ifdef SERIAL_HAVE_RXDMA -void stm32_serial_dma_poll(void); -#endif - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_STC_STM32_STM32_UART_H */ diff --git a/arch/arm/src/stm32/stm32_uid.c b/arch/arm/src/stm32/stm32_uid.c deleted file mode 100644 index fa274e1d62ae3..0000000000000 --- a/arch/arm/src/stm32/stm32_uid.c +++ /dev/null @@ -1,62 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_uid.c - * - * SPDX-License-Identifier: BSD-3-Clause - * SPDX-FileCopyrightText: 2015 Marawan Ragab. All rights reserved. - * SPDX-FileContributor: Marawan Ragab - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "hardware/stm32_memorymap.h" -#include "stm32_uid.h" - -#ifdef STM32_SYSMEM_UID /* Not defined for the STM32L */ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -void stm32_get_uniqueid(uint8_t uniqueid[12]) -{ - int i; - - for (i = 0; i < 12; i++) - { - uniqueid[i] = *((uint8_t *)(STM32_SYSMEM_UID) + i); - } -} - -#endif /* STM32_SYSMEM_UID */ diff --git a/arch/arm/src/stm32/stm32_uid.h b/arch/arm/src/stm32/stm32_uid.h deleted file mode 100644 index d820fcee8c6e1..0000000000000 --- a/arch/arm/src/stm32/stm32_uid.h +++ /dev/null @@ -1,52 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_uid.h - * - * SPDX-License-Identifier: BSD-3-Clause - * SPDX-FileCopyrightText: 2015 Marawan Ragab. All rights reserved. - * SPDX-FileContributor: Marawan Ragab - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32_STM32_UID_H -#define __ARCH_ARM_SRC_STM32_STM32_UID_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -void stm32_get_uniqueid(uint8_t uniqueid[12]); - -#endif /* __ARCH_ARM_SRC_STM32_STM32_UID_H */ diff --git a/arch/arm/src/stm32/stm32_usbdev.c b/arch/arm/src/stm32/stm32_usbdev.c deleted file mode 100644 index 09e7393131211..0000000000000 --- a/arch/arm/src/stm32/stm32_usbdev.c +++ /dev/null @@ -1,3983 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_usbdev.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* References: - * - RM0008 Reference manual, STMicro document ID 13902 - * - STM32F10xxx USB development kit, UM0424, STMicro - */ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include - -#include -#include - -#include "arm_internal.h" -#include "stm32.h" -#include "stm32_syscfg.h" -#include "stm32_gpio.h" -#include "stm32_usbdev.h" - -#if defined(CONFIG_USBDEV) && defined(CONFIG_STM32_USB) - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -#ifndef CONFIG_USBDEV_EP0_MAXSIZE -# define CONFIG_USBDEV_EP0_MAXSIZE 64 -#endif - -#ifndef CONFIG_USBDEV_SETUP_MAXDATASIZE -# define CONFIG_USBDEV_SETUP_MAXDATASIZE CONFIG_USBDEV_EP0_MAXSIZE -#endif - -/* USB Interrupts. Should be re-mapped if CAN is used. */ - -#ifdef CONFIG_STM32_STM32F30XX -# ifdef CONFIG_STM32_USB_ITRMP -# define STM32_IRQ_USBHP STM32_IRQ_USBHP_2 -# define STM32_IRQ_USBLP STM32_IRQ_USBLP_2 -# define STM32_IRQ_USBWKUP STM32_IRQ_USBWKUP_2 -# else -# define STM32_IRQ_USBHP STM32_IRQ_USBHP_1 -# define STM32_IRQ_USBLP STM32_IRQ_USBLP_1 -# define STM32_IRQ_USBWKUP STM32_IRQ_USBWKUP_1 -# endif -#endif - -/* Extremely detailed register debug that you would normally never want - * enabled. - */ - -#ifndef CONFIG_DEBUG_USB_INFO -# undef CONFIG_STM32_USBDEV_REGDEBUG -#endif - -/* Initial interrupt mask: Reset + Suspend + Correct Transfer */ - -#define STM32_CNTR_SETUP (USB_CNTR_RESETM|USB_CNTR_SUSPM|USB_CNTR_CTRM) - -/* Endpoint identifiers. The STM32 supports up to 16 mono-directional or 8 - * bidirectional endpoints. However, when you take into account PMA buffer - * usage (see below) and the fact that EP0 is bidirectional, then there is - * a functional limitation of EP0 + 5 mono-directional endpoints = 6. We'll - * define STM32_NENDPOINTS to be 8, however, because that is how many - * endpoint register sets there are. - */ - -#define EP0 (0) -#define EP1 (1) -#define EP2 (2) -#define EP3 (3) -#define EP4 (4) -#define EP5 (5) -#define EP6 (6) -#define EP7 (7) - -#define STM32_ENDP_BIT(ep) (1 << (ep)) -#define STM32_ENDP_ALLSET 0xff - -/* Packet sizes. We us a fixed 64 max packet size for all endpoint types */ - -#define STM32_MAXPACKET_SHIFT (6) -#define STM32_MAXPACKET_SIZE (1 << (STM32_MAXPACKET_SHIFT)) -#define STM32_MAXPACKET_MASK (STM32_MAXPACKET_SIZE-1) - -#define STM32_EP0MAXPACKET STM32_MAXPACKET_SIZE - -/* Buffer descriptor table. We assume that USB has exclusive use of CAN/USB - * memory. The buffer table is positioned at the beginning of the 512-byte - * CAN/USB memory. We will use the first STM32_NENDPOINTS*4 words for the - * buffer table. - * That is exactly 64 bytes, leaving 7*64 bytes for endpoint buffers. - */ - -#define STM32_BTABLE_ADDRESS (0x00) /* Start at the beginning of USB/CAN RAM */ -#define STM32_DESC_SIZE (8) /* Each descriptor is 4*2=8 bytes in size */ -#define STM32_BTABLE_SIZE (STM32_NENDPOINTS*STM32_DESC_SIZE) - -/* Buffer layout. Assume that all buffers are 64-bytes (maxpacketsize), then - * we have space for only 7 buffers; endpoint 0 will require two buffers, - * leaving 5 for other endpoints. - */ - -#define STM32_BUFFER_START STM32_BTABLE_SIZE -#define STM32_EP0_RXADDR STM32_BUFFER_START -#define STM32_EP0_TXADDR (STM32_EP0_RXADDR+STM32_EP0MAXPACKET) - -#define STM32_BUFFER_EP0 0x03 -#define STM32_NBUFFERS 7 -#define STM32_BUFFER_BIT(bn) (1 << (bn)) -#define STM32_BUFFER_ALLSET 0x7f -#define STM32_BUFNO2BUF(bn) (STM32_BUFFER_START+((bn)<head == NULL) -#define stm32_rqpeek(ep) ((ep)->head) - -/* USB trace ****************************************************************/ - -/* Trace error codes */ - -#define STM32_TRACEERR_ALLOCFAIL 0x0001 -#define STM32_TRACEERR_BADCLEARFEATURE 0x0002 -#define STM32_TRACEERR_BADDEVGETSTATUS 0x0003 -#define STM32_TRACEERR_BADEPGETSTATUS 0x0004 -#define STM32_TRACEERR_BADEPNO 0x0005 -#define STM32_TRACEERR_BADEPTYPE 0x0006 -#define STM32_TRACEERR_BADGETCONFIG 0x0007 -#define STM32_TRACEERR_BADGETSETDESC 0x0008 -#define STM32_TRACEERR_BADGETSTATUS 0x0009 -#define STM32_TRACEERR_BADSETADDRESS 0x000a -#define STM32_TRACEERR_BADSETCONFIG 0x000b -#define STM32_TRACEERR_BADSETFEATURE 0x000c -#define STM32_TRACEERR_BINDFAILED 0x000d -#define STM32_TRACEERR_DISPATCHSTALL 0x000e -#define STM32_TRACEERR_DRIVER 0x000f -#define STM32_TRACEERR_DRIVERREGISTERED 0x0010 -#define STM32_TRACEERR_EP0BADCTR 0x0011 -#define STM32_TRACEERR_EP0SETUPSTALLED 0x0012 -#define STM32_TRACEERR_EPBUFFER 0x0013 -#define STM32_TRACEERR_EPDISABLED 0x0014 -#define STM32_TRACEERR_EPOUTNULLPACKET 0x0015 -#define STM32_TRACEERR_EPRESERVE 0x0016 -#define STM32_TRACEERR_INVALIDCTRLREQ 0x0017 -#define STM32_TRACEERR_INVALIDPARMS 0x0018 -#define STM32_TRACEERR_IRQREGISTRATION 0x0019 -#define STM32_TRACEERR_NOTCONFIGURED 0x001a -#define STM32_TRACEERR_REQABORTED 0x001b - -/* Trace interrupt codes */ - -#define STM32_TRACEINTID_CLEARFEATURE 0x0001 -#define STM32_TRACEINTID_DEVGETSTATUS 0x0002 -#define STM32_TRACEINTID_DISPATCH 0x0003 -#define STM32_TRACEINTID_EP0IN 0x0004 -#define STM32_TRACEINTID_EP0INDONE 0x0005 -#define STM32_TRACEINTID_EP0OUTDONE 0x0006 -#define STM32_TRACEINTID_EP0SETUPDONE 0x0007 -#define STM32_TRACEINTID_EP0SETUPSETADDRESS 0x0008 -#define STM32_TRACEINTID_EPGETSTATUS 0x0009 -#define STM32_TRACEINTID_EPINDONE 0x000a -#define STM32_TRACEINTID_EPINQEMPTY 0x000b -#define STM32_TRACEINTID_EPOUTDONE 0x000c -#define STM32_TRACEINTID_EPOUTPENDING 0x000d -#define STM32_TRACEINTID_EPOUTQEMPTY 0x000e -#define STM32_TRACEINTID_ESOF 0x000f -#define STM32_TRACEINTID_GETCONFIG 0x0010 -#define STM32_TRACEINTID_GETSETDESC 0x0011 -#define STM32_TRACEINTID_GETSETIF 0x0012 -#define STM32_TRACEINTID_GETSTATUS 0x0013 -#define STM32_TRACEINTID_HPINTERRUPT 0x0014 -#define STM32_TRACEINTID_IFGETSTATUS 0x0015 -#define STM32_TRACEINTID_LPCTR 0x0016 -#define STM32_TRACEINTID_LPINTERRUPT 0x0017 -#define STM32_TRACEINTID_NOSTDREQ 0x0018 -#define STM32_TRACEINTID_RESET 0x0019 -#define STM32_TRACEINTID_SETCONFIG 0x001a -#define STM32_TRACEINTID_SETFEATURE 0x001b -#define STM32_TRACEINTID_SUSP 0x001c -#define STM32_TRACEINTID_SYNCHFRAME 0x001d -#define STM32_TRACEINTID_WKUP 0x001e -#define STM32_TRACEINTID_EP0SETUPOUT 0x001f -#define STM32_TRACEINTID_EP0SETUPOUTDATA 0x0020 - -/* Byte ordering in host-based values */ - -#ifdef CONFIG_ENDIAN_BIG -# define LSB 1 -# define MSB 0 -#else -# define LSB 0 -# define MSB 1 -#endif - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/* The various states of a control pipe */ - -enum stm32_ep0state_e -{ - EP0STATE_IDLE = 0, /* No request in progress */ - EP0STATE_SETUP_OUT, /* Set up received with data for device OUT in progress */ - EP0STATE_SETUP_READY, /* Set up was received prior and is in ctrl, - * now the data has arrived */ - EP0STATE_WRREQUEST, /* Write request in progress */ - EP0STATE_RDREQUEST, /* Read request in progress */ - EP0STATE_STALLED /* We are stalled */ -}; - -/* Resume states */ - -enum stm32_rsmstate_e -{ - RSMSTATE_IDLE = 0, /* Device is either fully suspended or running */ - RSMSTATE_STARTED, /* Resume sequence has been started */ - RSMSTATE_WAITING /* Waiting (on ESOFs) for end of sequence */ -}; - -union wb_u -{ - uint16_t w; - uint8_t b[2]; -}; - -/* A container for a request so that the request make be retained in a list */ - -struct stm32_req_s -{ - struct usbdev_req_s req; /* Standard USB request */ - struct stm32_req_s *flink; /* Supports a singly linked list */ -}; - -/* This is the internal representation of an endpoint */ - -struct stm32_ep_s -{ - /* Common endpoint fields. This must be the first thing defined in the - * structure so that it is possible to simply cast from struct usbdev_ep_s - * to struct stm32_ep_s. - */ - - struct usbdev_ep_s ep; /* Standard endpoint structure */ - - /* STR71X-specific fields */ - - struct stm32_usbdev_s *dev; /* Reference to private driver data */ - struct stm32_req_s *head; /* Request list for this endpoint */ - struct stm32_req_s *tail; - uint8_t bufno; /* Allocated buffer number */ - uint8_t stalled:1; /* true: Endpoint is stalled */ - uint8_t halted:1; /* true: Endpoint feature halted */ - uint8_t txbusy:1; /* true: TX endpoint FIFO full */ - uint8_t txnullpkt:1; /* Null packet needed at end of transfer */ -}; - -struct stm32_usbdev_s -{ - /* Common device fields. This must be the first thing defined in the - * structure so that it is possible to simply cast from struct usbdev_s - * to structstm32_usbdev_s. - */ - - struct usbdev_s usbdev; - - /* The bound device class driver */ - - struct usbdevclass_driver_s *driver; - - /* STM32-specific fields */ - - uint8_t ep0state; /* State of EP0 (see enum stm32_ep0state_e) */ - uint8_t rsmstate; /* Resume state (see enum stm32_rsmstate_e) */ - uint8_t nesofs; /* ESOF counter (for resume support) */ - uint8_t rxpending:1; /* 1: OUT data in PMA, but no read requests */ - uint8_t selfpowered:1; /* 1: Device is self powered */ - uint8_t epavail; /* Bitset of available endpoints */ - uint8_t bufavail; /* Bitset of available buffers */ - uint16_t rxstatus; /* Saved during interrupt processing */ - uint16_t txstatus; /* " " " " " " " " */ - uint16_t imask; /* Current interrupt mask */ - - /* E0 SETUP data buffering. - * - * ctrl - * The 8-byte SETUP request is received on the EP0 OUT endpoint and is - * saved. - * - * ep0data - * For OUT SETUP requests, the SETUP data phase must also complete - * before the SETUP command can be processed. The ep0 packet receipt - * logic stm32_ep0_rdrequest will save the accompanying EP0 OUT data - * in ep0data[] before the SETUP command is re-processed. - * - * ep0datlen - * Length of OUT DATA received in ep0data[] - */ - - struct usb_ctrlreq_s ctrl; /* Last EP0 request */ - - uint8_t ep0data[CONFIG_USBDEV_SETUP_MAXDATASIZE]; - uint16_t ep0datlen; - - /* The endpoint list */ - - struct stm32_ep_s eplist[STM32_NENDPOINTS]; -}; - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -/* Register operations ******************************************************/ - -#ifdef CONFIG_STM32_USBDEV_REGDEBUG -static uint16_t stm32_getreg(uint32_t addr); -static void stm32_putreg(uint16_t val, uint32_t addr); -static void stm32_checksetup(void); -static void stm32_dumpep(int epno); -#else -# define stm32_getreg(addr) getreg16(addr) -# define stm32_putreg(val,addr) putreg16(val,addr) -# define stm32_checksetup() -# define stm32_dumpep(epno) -#endif - -/* Low-Level Helpers ********************************************************/ - -static inline void - stm32_seteptxcount(uint8_t epno, uint16_t count); -static inline void - stm32_seteptxaddr(uint8_t epno, uint16_t addr); -static inline uint16_t - stm32_geteptxaddr(uint8_t epno); -static void stm32_seteprxcount(uint8_t epno, uint16_t count); -static inline uint16_t - stm32_geteprxcount(uint8_t epno); -static inline void - stm32_seteprxaddr(uint8_t epno, uint16_t addr); -static inline uint16_t - stm32_geteprxaddr(uint8_t epno); -static inline void - stm32_setepaddress(uint8_t epno, uint16_t addr); -static inline void - stm32_seteptype(uint8_t epno, uint16_t type); -static inline void - stm32_seteptxaddr(uint8_t epno, uint16_t addr); -static inline void - stm32_clrstatusout(uint8_t epno); -static void stm32_clrrxdtog(uint8_t epno); -static void stm32_clrtxdtog(uint8_t epno); -static void stm32_clrepctrrx(uint8_t epno); -static void stm32_clrepctrtx(uint8_t epno); -static void stm32_seteptxstatus(uint8_t epno, uint16_t state); -static void stm32_seteprxstatus(uint8_t epno, uint16_t state); -static inline uint16_t - stm32_geteptxstatus(uint8_t epno); -static inline uint16_t - stm32_geteprxstatus(uint8_t epno); -static bool stm32_eptxstalled(uint8_t epno); -static bool stm32_eprxstalled(uint8_t epno); -static void stm32_setimask(struct stm32_usbdev_s *priv, - uint16_t setbits, - uint16_t clrbits); - -/* Suspend/Resume Helpers ***************************************************/ - -static void stm32_suspend(struct stm32_usbdev_s *priv); -static void stm32_initresume(struct stm32_usbdev_s *priv); -static void stm32_esofpoll(struct stm32_usbdev_s *priv) ; - -/* Request Helpers **********************************************************/ - -static void stm32_copytopma(const uint8_t *buffer, uint16_t pma, - uint16_t nbytes); -static inline void stm32_copyfrompma(uint8_t *buffer, - uint16_t pma, uint16_t nbytes); -static struct stm32_req_s * - stm32_rqdequeue(struct stm32_ep_s *privep); -static void stm32_rqenqueue(struct stm32_ep_s *privep, - struct stm32_req_s *req); -static inline void - stm32_abortrequest(struct stm32_ep_s *privep, - struct stm32_req_s *privreq, int16_t result); -static void stm32_reqcomplete(struct stm32_ep_s *privep, int16_t result); -static void stm32_epwrite(struct stm32_usbdev_s *buf, - struct stm32_ep_s *privep, - const uint8_t *data, uint32_t nbytes); -static int stm32_wrrequest(struct stm32_usbdev_s *priv, - struct stm32_ep_s *privep); -inline static int - stm32_wrrequest_ep0(struct stm32_usbdev_s *priv, - struct stm32_ep_s *privep); -static inline int - stm32_ep0_rdrequest(struct stm32_usbdev_s *priv); -static int stm32_rdrequest(struct stm32_usbdev_s *priv, - struct stm32_ep_s *privep); -static void stm32_cancelrequests(struct stm32_ep_s *privep); - -/* Interrupt level processing ***********************************************/ - -static void stm32_dispatchrequest(struct stm32_usbdev_s *priv); -static void stm32_epdone(struct stm32_usbdev_s *priv, uint8_t epno); -static void stm32_setdevaddr(struct stm32_usbdev_s *priv, uint8_t value); -static void stm32_ep0setup(struct stm32_usbdev_s *priv); -static void stm32_ep0out(struct stm32_usbdev_s *priv); -static void stm32_ep0in(struct stm32_usbdev_s *priv); -static inline void - stm32_ep0done(struct stm32_usbdev_s *priv, uint16_t istr); -static void stm32_lptransfer(struct stm32_usbdev_s *priv); -static int stm32_hpinterrupt(int irq, void *context, void *arg); -static int stm32_lpinterrupt(int irq, void *context, void *arg); - -/* Endpoint helpers *********************************************************/ - -static inline struct stm32_ep_s * - stm32_epreserve(struct stm32_usbdev_s *priv, uint8_t epset); -static inline void - stm32_epunreserve(struct stm32_usbdev_s *priv, - struct stm32_ep_s *privep); -static inline bool - stm32_epreserved(struct stm32_usbdev_s *priv, int epno); -static int stm32_epallocpma(struct stm32_usbdev_s *priv); -static inline void - stm32_epfreepma(struct stm32_usbdev_s *priv, - struct stm32_ep_s *privep); - -/* Endpoint operations ******************************************************/ - -static int stm32_epconfigure(struct usbdev_ep_s *ep, - const struct usb_epdesc_s *desc, bool last); -static int stm32_epdisable(struct usbdev_ep_s *ep); -static struct usbdev_req_s * - stm32_epallocreq(struct usbdev_ep_s *ep); -static void stm32_epfreereq(struct usbdev_ep_s *ep, - struct usbdev_req_s *); -static int stm32_epsubmit(struct usbdev_ep_s *ep, - struct usbdev_req_s *req); -static int stm32_epcancel(struct usbdev_ep_s *ep, - struct usbdev_req_s *req); -static int stm32_epstall(struct usbdev_ep_s *ep, bool resume); - -/* USB device controller operations *****************************************/ - -static struct usbdev_ep_s * - stm32_allocep(struct usbdev_s *dev, uint8_t epno, bool in, - uint8_t eptype); -static void stm32_freeep(struct usbdev_s *dev, struct usbdev_ep_s *ep); -static int stm32_getframe(struct usbdev_s *dev); -static int stm32_wakeup(struct usbdev_s *dev); -static int stm32_selfpowered(struct usbdev_s *dev, bool selfpowered); - -/* Initialization/Reset *****************************************************/ - -static void stm32_reset(struct stm32_usbdev_s *priv); -static void stm32_hwreset(struct stm32_usbdev_s *priv); -static void stm32_hwsetup(struct stm32_usbdev_s *priv); -static void stm32_hwshutdown(struct stm32_usbdev_s *priv); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* Since there is only a single USB interface, all status information can be - * be simply retained in a single global instance. - */ - -static struct stm32_usbdev_s g_usbdev; - -static const struct usbdev_epops_s g_epops = -{ - .configure = stm32_epconfigure, - .disable = stm32_epdisable, - .allocreq = stm32_epallocreq, - .freereq = stm32_epfreereq, - .submit = stm32_epsubmit, - .cancel = stm32_epcancel, - .stall = stm32_epstall, -}; - -static const struct usbdev_ops_s g_devops = -{ - .allocep = stm32_allocep, - .freeep = stm32_freeep, - .getframe = stm32_getframe, - .wakeup = stm32_wakeup, - .selfpowered = stm32_selfpowered, - .pullup = stm32_usbpullup, -}; - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -#ifdef CONFIG_USBDEV_TRACE_STRINGS -const struct trace_msg_t g_usb_trace_strings_intdecode[] = -{ - TRACE_STR(STM32_TRACEINTID_CLEARFEATURE), - TRACE_STR(STM32_TRACEINTID_DEVGETSTATUS), - TRACE_STR(STM32_TRACEINTID_DISPATCH), - TRACE_STR(STM32_TRACEINTID_EP0IN), - TRACE_STR(STM32_TRACEINTID_EP0INDONE), - TRACE_STR(STM32_TRACEINTID_EP0OUTDONE), - TRACE_STR(STM32_TRACEINTID_EP0SETUPDONE), - TRACE_STR(STM32_TRACEINTID_EP0SETUPSETADDRESS), - TRACE_STR(STM32_TRACEINTID_EPGETSTATUS), - TRACE_STR(STM32_TRACEINTID_EPINDONE), - TRACE_STR(STM32_TRACEINTID_EPINQEMPTY), - TRACE_STR(STM32_TRACEINTID_EPOUTDONE), - TRACE_STR(STM32_TRACEINTID_EPOUTPENDING), - TRACE_STR(STM32_TRACEINTID_EPOUTQEMPTY), - TRACE_STR(STM32_TRACEINTID_ESOF), - TRACE_STR(STM32_TRACEINTID_GETCONFIG), - TRACE_STR(STM32_TRACEINTID_GETSETDESC), - TRACE_STR(STM32_TRACEINTID_GETSETIF), - TRACE_STR(STM32_TRACEINTID_GETSTATUS), - TRACE_STR(STM32_TRACEINTID_HPINTERRUPT), - TRACE_STR(STM32_TRACEINTID_IFGETSTATUS), - TRACE_STR(STM32_TRACEINTID_LPCTR), - TRACE_STR(STM32_TRACEINTID_LPINTERRUPT), - TRACE_STR(STM32_TRACEINTID_NOSTDREQ), - TRACE_STR(STM32_TRACEINTID_RESET), - TRACE_STR(STM32_TRACEINTID_SETCONFIG), - TRACE_STR(STM32_TRACEINTID_SETFEATURE), - TRACE_STR(STM32_TRACEINTID_SUSP), - TRACE_STR(STM32_TRACEINTID_SYNCHFRAME), - TRACE_STR(STM32_TRACEINTID_WKUP), - TRACE_STR(STM32_TRACEINTID_EP0SETUPOUT), - TRACE_STR(STM32_TRACEINTID_EP0SETUPOUTDATA), - TRACE_STR_END -}; -#endif - -#ifdef CONFIG_USBDEV_TRACE_STRINGS -const struct trace_msg_t g_usb_trace_strings_deverror[] = -{ - TRACE_STR(STM32_TRACEERR_ALLOCFAIL), - TRACE_STR(STM32_TRACEERR_BADCLEARFEATURE), - TRACE_STR(STM32_TRACEERR_BADDEVGETSTATUS), - TRACE_STR(STM32_TRACEERR_BADEPGETSTATUS), - TRACE_STR(STM32_TRACEERR_BADEPNO), - TRACE_STR(STM32_TRACEERR_BADEPTYPE), - TRACE_STR(STM32_TRACEERR_BADGETCONFIG), - TRACE_STR(STM32_TRACEERR_BADGETSETDESC), - TRACE_STR(STM32_TRACEERR_BADGETSTATUS), - TRACE_STR(STM32_TRACEERR_BADSETADDRESS), - TRACE_STR(STM32_TRACEERR_BADSETCONFIG), - TRACE_STR(STM32_TRACEERR_BADSETFEATURE), - TRACE_STR(STM32_TRACEERR_BINDFAILED), - TRACE_STR(STM32_TRACEERR_DISPATCHSTALL), - TRACE_STR(STM32_TRACEERR_DRIVER), - TRACE_STR(STM32_TRACEERR_DRIVERREGISTERED), - TRACE_STR(STM32_TRACEERR_EP0BADCTR), - TRACE_STR(STM32_TRACEERR_EP0SETUPSTALLED), - TRACE_STR(STM32_TRACEERR_EPBUFFER), - TRACE_STR(STM32_TRACEERR_EPDISABLED), - TRACE_STR(STM32_TRACEERR_EPOUTNULLPACKET), - TRACE_STR(STM32_TRACEERR_EPRESERVE), - TRACE_STR(STM32_TRACEERR_INVALIDCTRLREQ), - TRACE_STR(STM32_TRACEERR_INVALIDPARMS), - TRACE_STR(STM32_TRACEERR_IRQREGISTRATION), - TRACE_STR(STM32_TRACEERR_NOTCONFIGURED), - TRACE_STR(STM32_TRACEERR_REQABORTED), - TRACE_STR_END -}; -#endif - -/**************************************************************************** - * Private Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Register Operations - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_getreg - ****************************************************************************/ - -#ifdef CONFIG_STM32_USBDEV_REGDEBUG -static uint16_t stm32_getreg(uint32_t addr) -{ - static uint32_t prevaddr = 0; - static uint16_t preval = 0; - static uint32_t count = 0; - - /* Read the value from the register */ - - uint16_t val = getreg16(addr); - - /* Is this the same value that we read from the same register last time? - * Are we polling the register? If so, suppress some of the output. - */ - - if (addr == prevaddr && val == preval) - { - if (count == 0xffffffff || ++count > 3) - { - if (count == 4) - { - uinfo("...\n"); - } - - return val; - } - } - - /* No this is a new address or value */ - - else - { - /* Did we print "..." for the previous value? */ - - if (count > 3) - { - /* Yes.. then show how many times the value repeated */ - - uinfo("[repeats %d more times]\n", count - 3); - } - - /* Save the new address, value, and count */ - - prevaddr = addr; - preval = val; - count = 1; - } - - /* Show the register value read */ - - uinfo("%08" PRIx32 "->%04x\n", addr, val); - return val; -} -#endif - -/**************************************************************************** - * Name: stm32_putreg - ****************************************************************************/ - -#ifdef CONFIG_STM32_USBDEV_REGDEBUG -static void stm32_putreg(uint16_t val, uint32_t addr) -{ - /* Show the register value being written */ - - uinfo("%08" PRIx32 "<-%04x\n", addr, val); - - /* Write the value */ - - putreg16(val, addr); -} -#endif - -/**************************************************************************** - * Name: stm32_dumpep - ****************************************************************************/ - -#ifdef CONFIG_STM32_USBDEV_REGDEBUG -static void stm32_dumpep(int epno) -{ - uint32_t addr; - - /* Common registers */ - - uinfo("CNTR: %04x\n", getreg16(STM32_USB_CNTR)); - uinfo("ISTR: %04x\n", getreg16(STM32_USB_ISTR)); - uinfo("FNR: %04x\n", getreg16(STM32_USB_FNR)); - uinfo("DADDR: %04x\n", getreg16(STM32_USB_DADDR)); - uinfo("BTABLE: %04x\n", getreg16(STM32_USB_BTABLE)); - - /* Endpoint register */ - - addr = STM32_USB_EPR(epno); - uinfo("EPR%d: [%08" PRIx32 "] %04x\n", epno, addr, getreg16(addr)); - - /* Endpoint descriptor */ - - addr = STM32_USB_BTABLE_ADDR(epno, 0); - uinfo("DESC: %08" PRIx32 "\n", addr); - - /* Endpoint buffer descriptor */ - - addr = STM32_USB_ADDR_TX(epno); - uinfo(" TX ADDR: [%08" PRIx32 "] %04x\n", addr, getreg16(addr)); - - addr = STM32_USB_COUNT_TX(epno); - uinfo(" COUNT: [%08" PRIx32 "] %04x\n", addr, getreg16(addr)); - - addr = STM32_USB_ADDR_RX(epno); - uinfo(" RX ADDR: [%08" PRIx32 "] %04x\n", addr, getreg16(addr)); - - addr = STM32_USB_COUNT_RX(epno); - uinfo(" COUNT: [%08" PRIx32 "] %04x\n", addr, getreg16(addr)); -} -#endif - -/**************************************************************************** - * Name: stm32_checksetup - ****************************************************************************/ - -#ifdef CONFIG_STM32_USBDEV_REGDEBUG -static void stm32_checksetup(void) -{ - uint32_t cfgr = getreg32(STM32_RCC_CFGR); - uint32_t apb1rstr = getreg32(STM32_RCC_APB1RSTR); - uint32_t apb1enr = getreg32(STM32_RCC_APB1ENR); - - uinfo("CFGR: %08" PRIx32 " APB1RSTR: %08" PRIx32 - " APB1ENR: %08" PRIx32 "\n", - cfgr, apb1rstr, apb1enr); - - if ((apb1rstr & RCC_APB1RSTR_USBRST) != 0 || - (apb1enr & RCC_APB1ENR_USBEN) == 0) - { - uerr("ERROR: USB is NOT setup correctly\n"); - } -} -#endif - -/**************************************************************************** - * Low-Level Helpers - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_seteptxcount - ****************************************************************************/ - -static inline void stm32_seteptxcount(uint8_t epno, uint16_t count) -{ - volatile uint32_t *epaddr = (uint32_t *)STM32_USB_COUNT_TX(epno); - *epaddr = count; -} - -/**************************************************************************** - * Name: stm32_seteptxaddr - ****************************************************************************/ - -static inline void stm32_seteptxaddr(uint8_t epno, uint16_t addr) -{ - volatile uint32_t *txaddr = (uint32_t *)STM32_USB_ADDR_TX(epno); - *txaddr = addr; -} - -/**************************************************************************** - * Name: stm32_geteptxaddr - ****************************************************************************/ - -static inline uint16_t stm32_geteptxaddr(uint8_t epno) -{ - volatile uint32_t *txaddr = (uint32_t *)STM32_USB_ADDR_TX(epno); - return (uint16_t)*txaddr; -} - -/**************************************************************************** - * Name: stm32_seteprxcount - ****************************************************************************/ - -static void stm32_seteprxcount(uint8_t epno, uint16_t count) -{ - volatile uint32_t *epaddr = (uint32_t *)STM32_USB_COUNT_RX(epno); - uint32_t rxcount = 0; - uint16_t nblocks; - - /* The upper bits of the RX COUNT value contain the size of allocated - * RX buffer. This is based on a block size of 2 or 32: - * - * USB_COUNT_RX_BL_SIZE not set: - * nblocks is in units of 2 bytes. - * 00000 - not allowed - * 00001 - 2 bytes - * .... - * 11111 - 62 bytes - * - * USB_COUNT_RX_BL_SIZE set: - * 00000 - 32 bytes - * 00001 - 64 bytes - * ... - * 01111 - 512 bytes - * 1xxxx - Not allowed - */ - - if (count > 62) - { - /* Blocks of 32 (with 0 meaning one block of 32) */ - - nblocks = (count >> 5) - 1 ; - DEBUGASSERT(nblocks <= 0x0f); - rxcount = (uint32_t)((nblocks << - USB_COUNT_RX_NUM_BLOCK_SHIFT) | USB_COUNT_RX_BL_SIZE); - } - else if (count > 0) - { - /* Blocks of 2 (with 1 meaning one block of 2) */ - - nblocks = (count + 1) >> 1; - DEBUGASSERT(nblocks > 0 && nblocks < 0x1f); - rxcount = (uint32_t)(nblocks << USB_COUNT_RX_NUM_BLOCK_SHIFT); - } - - *epaddr = rxcount; -} - -/**************************************************************************** - * Name: stm32_geteprxcount - ****************************************************************************/ - -static inline uint16_t stm32_geteprxcount(uint8_t epno) -{ - volatile uint32_t *epaddr = (uint32_t *)STM32_USB_COUNT_RX(epno); - return (*epaddr) & USB_COUNT_RX_MASK; -} - -/**************************************************************************** - * Name: stm32_seteprxaddr - ****************************************************************************/ - -static inline void stm32_seteprxaddr(uint8_t epno, uint16_t addr) -{ - volatile uint32_t *rxaddr = (uint32_t *)STM32_USB_ADDR_RX(epno); - *rxaddr = addr; -} - -/**************************************************************************** - * Name: stm32_seteprxaddr - ****************************************************************************/ - -static inline uint16_t stm32_geteprxaddr(uint8_t epno) -{ - volatile uint32_t *rxaddr = (uint32_t *)STM32_USB_ADDR_RX(epno); - return (uint16_t)*rxaddr; -} - -/**************************************************************************** - * Name: stm32_setepaddress - ****************************************************************************/ - -static inline void stm32_setepaddress(uint8_t epno, uint16_t addr) -{ - uint32_t epaddr = STM32_USB_EPR(epno); - uint16_t regval; - - regval = stm32_getreg(epaddr); - regval &= EPR_NOTOG_MASK; - regval &= ~USB_EPR_EA_MASK; - regval |= (addr << USB_EPR_EA_SHIFT); - stm32_putreg(regval, epaddr); -} - -/**************************************************************************** - * Name: stm32_seteptype - ****************************************************************************/ - -static inline void stm32_seteptype(uint8_t epno, uint16_t type) -{ - uint32_t epaddr = STM32_USB_EPR(epno); - uint16_t regval; - - regval = stm32_getreg(epaddr); - regval &= EPR_NOTOG_MASK; - regval &= ~USB_EPR_EPTYPE_MASK; - regval |= type; - stm32_putreg(regval, epaddr); -} - -/**************************************************************************** - * Name: stm32_clrstatusout - ****************************************************************************/ - -static inline void stm32_clrstatusout(uint8_t epno) -{ - uint32_t epaddr = STM32_USB_EPR(epno); - uint16_t regval; - - /* For a BULK endpoint the EP_KIND bit is used to enabled double buffering; - * for a CONTROL endpoint, it is set to indicate that a status OUT - * transaction is expected. The bit is not used with out endpoint types. - */ - - regval = stm32_getreg(epaddr); - regval &= EPR_NOTOG_MASK; - regval &= ~USB_EPR_EP_KIND; - stm32_putreg(regval, epaddr); -} - -/**************************************************************************** - * Name: stm32_clrrxdtog - ****************************************************************************/ - -static void stm32_clrrxdtog(uint8_t epno) -{ - uint32_t epaddr = STM32_USB_EPR(epno); - uint16_t regval; - - regval = stm32_getreg(epaddr); - if ((regval & USB_EPR_DTOG_RX) != 0) - { - regval &= EPR_NOTOG_MASK; - regval |= USB_EPR_DTOG_RX; - stm32_putreg(regval, epaddr); - } -} - -/**************************************************************************** - * Name: stm32_clrtxdtog - ****************************************************************************/ - -static void stm32_clrtxdtog(uint8_t epno) -{ - uint32_t epaddr = STM32_USB_EPR(epno); - uint16_t regval; - - regval = stm32_getreg(epaddr); - if ((regval & USB_EPR_DTOG_TX) != 0) - { - regval &= EPR_NOTOG_MASK; - regval |= USB_EPR_DTOG_TX; - stm32_putreg(regval, epaddr); - } -} - -/**************************************************************************** - * Name: stm32_clrepctrrx - ****************************************************************************/ - -static void stm32_clrepctrrx(uint8_t epno) -{ - uint32_t epaddr = STM32_USB_EPR(epno); - uint16_t regval; - - regval = stm32_getreg(epaddr); - regval &= EPR_NOTOG_MASK; - regval &= ~USB_EPR_CTR_RX; - stm32_putreg(regval, epaddr); -} - -/**************************************************************************** - * Name: stm32_clrepctrtx - ****************************************************************************/ - -static void stm32_clrepctrtx(uint8_t epno) -{ - uint32_t epaddr = STM32_USB_EPR(epno); - uint16_t regval; - - regval = stm32_getreg(epaddr); - regval &= EPR_NOTOG_MASK; - regval &= ~USB_EPR_CTR_TX; - stm32_putreg(regval, epaddr); -} - -/**************************************************************************** - * Name: stm32_geteptxstatus - ****************************************************************************/ - -static inline uint16_t stm32_geteptxstatus(uint8_t epno) -{ - return (uint16_t)(stm32_getreg(STM32_USB_EPR(epno)) & - USB_EPR_STATTX_MASK); -} - -/**************************************************************************** - * Name: stm32_geteprxstatus - ****************************************************************************/ - -static inline uint16_t stm32_geteprxstatus(uint8_t epno) -{ - return (stm32_getreg(STM32_USB_EPR(epno)) & USB_EPR_STATRX_MASK); -} - -/**************************************************************************** - * Name: stm32_seteptxstatus - ****************************************************************************/ - -static void stm32_seteptxstatus(uint8_t epno, uint16_t state) -{ - uint32_t epaddr = STM32_USB_EPR(epno); - uint16_t regval; - - /* The bits in the STAT_TX field can be toggled by software to set their - * value. When set to 0, the value remains unchanged; when set to one, - * value toggles. - */ - - regval = stm32_getreg(epaddr); - - /* The exclusive OR will set STAT_TX bits to 1 if there value is different - * from the bits requested in 'state' - */ - - regval ^= state; - regval &= EPR_TXDTOG_MASK; - stm32_putreg(regval, epaddr); -} - -/**************************************************************************** - * Name: stm32_seteprxstatus - ****************************************************************************/ - -static void stm32_seteprxstatus(uint8_t epno, uint16_t state) -{ - uint32_t epaddr = STM32_USB_EPR(epno); - uint16_t regval; - - /* The bits in the STAT_RX field can be toggled by software to set their - * value. When set to 0, the value remains unchanged; when set to one, - * value toggles. - */ - - regval = stm32_getreg(epaddr); - - /* The exclusive OR will set STAT_RX bits to 1 if there value is different - * from the bits requested in 'state' - */ - - regval ^= state; - regval &= EPR_RXDTOG_MASK; - stm32_putreg(regval, epaddr); -} - -/**************************************************************************** - * Name: stm32_eptxstalled - ****************************************************************************/ - -static inline bool stm32_eptxstalled(uint8_t epno) -{ - return (stm32_geteptxstatus(epno) == USB_EPR_STATTX_STALL); -} - -/**************************************************************************** - * Name: stm32_eprxstalled - ****************************************************************************/ - -static inline bool stm32_eprxstalled(uint8_t epno) -{ - return (stm32_geteprxstatus(epno) == USB_EPR_STATRX_STALL); -} - -/**************************************************************************** - * Request Helpers - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_copytopma - ****************************************************************************/ - -static void stm32_copytopma(const uint8_t *buffer, - uint16_t pma, uint16_t nbytes) -{ - uint16_t *dest; - uint16_t ms; - uint16_t ls; - int nwords = (nbytes + 1) >> 1; - int i; - - /* Copy loop. Source=user buffer, Dest=packet memory */ - - dest = (uint16_t *)(STM32_USBRAM_BASE + ((uint32_t)pma << 1)); - for (i = nwords; i != 0; i--) - { - /* Read two bytes and pack into on 16-bit word */ - - ls = (uint16_t)(*buffer++); - ms = (uint16_t)(*buffer++); - *dest = ms << 8 | ls; - - /* Source address increments by 2*sizeof(uint8_t) = 2; Dest address - * increments by 2*sizeof(uint16_t) = 4. - */ - - dest += 2; - } -} - -/**************************************************************************** - * Name: stm32_copyfrompma - ****************************************************************************/ - -static inline void -stm32_copyfrompma(uint8_t *buffer, uint16_t pma, uint16_t nbytes) -{ - uint32_t *src; - int nwords = (nbytes + 1) >> 1; - int i; - - /* Copy loop. Source=packet memory, Dest=user buffer */ - - src = (uint32_t *)(STM32_USBRAM_BASE + ((uint32_t)pma << 1)); - for (i = nwords; i != 0; i--) - { - /* Copy 16-bits from packet memory to user buffer. */ - - *(uint16_t *)buffer = *src++; - - /* Source address increments by 1*sizeof(uint32_t) = 4; Dest address - * increments by 2*sizeof(uint8_t) = 2. - */ - - buffer += 2; - } -} - -/**************************************************************************** - * Name: stm32_rqdequeue - ****************************************************************************/ - -static struct stm32_req_s *stm32_rqdequeue(struct stm32_ep_s *privep) -{ - struct stm32_req_s *ret = privep->head; - - if (ret) - { - privep->head = ret->flink; - if (!privep->head) - { - privep->tail = NULL; - } - - ret->flink = NULL; - } - - return ret; -} - -/**************************************************************************** - * Name: stm32_rqenqueue - ****************************************************************************/ - -static void stm32_rqenqueue(struct stm32_ep_s *privep, - struct stm32_req_s *req) -{ - req->flink = NULL; - if (!privep->head) - { - privep->head = req; - privep->tail = req; - } - else - { - privep->tail->flink = req; - privep->tail = req; - } -} - -/**************************************************************************** - * Name: stm32_abortrequest - ****************************************************************************/ - -static inline void -stm32_abortrequest(struct stm32_ep_s *privep, - struct stm32_req_s *privreq, int16_t result) -{ - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_REQABORTED), - (uint16_t)USB_EPNO(privep->ep.eplog)); - - /* Save the result in the request structure */ - - privreq->req.result = result; - - /* Callback to the request completion handler */ - - privreq->req.callback(&privep->ep, &privreq->req); -} - -/**************************************************************************** - * Name: stm32_reqcomplete - ****************************************************************************/ - -static void stm32_reqcomplete(struct stm32_ep_s *privep, int16_t result) -{ - struct stm32_req_s *privreq; - irqstate_t flags; - - /* Remove the completed request at the head of the endpoint request list */ - - flags = enter_critical_section(); - privreq = stm32_rqdequeue(privep); - leave_critical_section(flags); - - if (privreq) - { - /* If endpoint 0, temporarily reflect the state of protocol stalled - * in the callback. - */ - - bool stalled = privep->stalled; - if (USB_EPNO(privep->ep.eplog) == EP0) - { - privep->stalled = (privep->dev->ep0state == EP0STATE_STALLED); - } - - /* Save the result in the request structure */ - - privreq->req.result = result; - - /* Callback to the request completion handler */ - - privreq->flink = NULL; - privreq->req.callback(&privep->ep, &privreq->req); - - /* Restore the stalled indication */ - - privep->stalled = stalled; - } -} - -/**************************************************************************** - * Name: tm32_epwrite - ****************************************************************************/ - -static void stm32_epwrite(struct stm32_usbdev_s *priv, - struct stm32_ep_s *privep, - const uint8_t *buf, uint32_t nbytes) -{ - uint8_t epno = USB_EPNO(privep->ep.eplog); - usbtrace(TRACE_WRITE(epno), nbytes); - - /* Check for a zero-length packet */ - - if (nbytes > 0) - { - /* Copy the data from the user buffer into packet memory for this - * endpoint - */ - - stm32_copytopma(buf, stm32_geteptxaddr(epno), nbytes); - } - - /* Send the packet (might be a null packet nbytes == 0) */ - - stm32_seteptxcount(epno, nbytes); - priv->txstatus = USB_EPR_STATTX_VALID; - - /* Indicate that there is data in the TX packet memory. This will be - * cleared when the next data out interrupt is received. - */ - - privep->txbusy = true; -} - -/**************************************************************************** - * Name: stm32_wrrequest_ep0 - * - * Description: - * Handle the ep0 state on writes. - * - ****************************************************************************/ - -inline static int stm32_wrrequest_ep0(struct stm32_usbdev_s *priv, - struct stm32_ep_s *privep) -{ - int ret; - ret = stm32_wrrequest(priv, privep); - priv->ep0state = ((ret == OK) ? EP0STATE_WRREQUEST : EP0STATE_IDLE); - return ret; -} - -/**************************************************************************** - * Name: stm32_wrrequest - ****************************************************************************/ - -static int stm32_wrrequest(struct stm32_usbdev_s *priv, - struct stm32_ep_s *privep) -{ - struct stm32_req_s *privreq; - uint8_t *buf; - uint8_t epno; - int nbytes; - int bytesleft; - - /* We get here when an IN endpoint interrupt occurs. So now we know that - * there is no TX transfer in progress. - */ - - privep->txbusy = false; - - /* Check the request from the head of the endpoint request queue */ - - privreq = stm32_rqpeek(privep); - if (!privreq) - { - /* There is no TX transfer in progress and no new pending TX - * requests to send. - */ - - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPINQEMPTY), 0); - return -ENOENT; - } - - epno = USB_EPNO(privep->ep.eplog); - uinfo("epno=%d req=%p: len=%zu xfrd=%zu nullpkt=%d\n", - epno, privreq, privreq->req.len, - privreq->req.xfrd, privep->txnullpkt); - UNUSED(epno); - - /* Get the number of bytes left to be sent in the packet */ - - bytesleft = privreq->req.len - privreq->req.xfrd; - nbytes = bytesleft; - -#warning "REVISIT: If the EP supports double buffering, then we can do better" - - /* Either (1) we are committed to sending the null packet - * (because txnullpkt == 1 && nbytes == 0), or (2) we have not yet send - * the last packet (nbytes > 0). - * In either case, it is appropriate to clearn txnullpkt now. - */ - - privep->txnullpkt = 0; - - /* If we are not sending a NULL packet, then clip the size to maxpacket - * and check if we need to send a following NULL packet. - */ - - if (nbytes > 0) - { - /* Either send the maxpacketsize or all of the remaining data in - * the request. - */ - - if (nbytes >= privep->ep.maxpacket) - { - nbytes = privep->ep.maxpacket; - - /* Handle the case where this packet is exactly the - * maxpacketsize. Do we need to send a zero-length packet - * in this case? - */ - - if (bytesleft == privep->ep.maxpacket && - (privreq->req.flags & USBDEV_REQFLAGS_NULLPKT) != 0) - { - privep->txnullpkt = 1; - } - } - } - - /* Send the packet (might be a null packet nbytes == 0) */ - - buf = privreq->req.buf + privreq->req.xfrd; - stm32_epwrite(priv, privep, buf, nbytes); - - /* Update for the next data IN interrupt */ - - privreq->req.xfrd += nbytes; - bytesleft = privreq->req.len - privreq->req.xfrd; - - /* If all of the bytes were sent (including any final null packet) - * then we are finished with the request buffer). - */ - - if (bytesleft == 0 && !privep->txnullpkt) - { - /* Return the write request to the class driver */ - - usbtrace(TRACE_COMPLETE(USB_EPNO(privep->ep.eplog)), - privreq->req.xfrd); - privep->txnullpkt = 0; - stm32_reqcomplete(privep, OK); - } - - return OK; -} - -/**************************************************************************** - * Name: stm32_ep0_rdrequest - * - * Description: - * This function is called from the stm32_ep0out handler when the ep0state - * is EP0STATE_SETUP_OUT and upon new incoming data is available in the - * endpoint 0's buffer. - * This function will simply copy the OUT data into ep0data. - * - ****************************************************************************/ - -static inline int stm32_ep0_rdrequest(struct stm32_usbdev_s *priv) -{ - uint32_t src; - int pmalen; - int readlen; - - /* Get the number of bytes to read from packet memory */ - - pmalen = stm32_geteprxcount(EP0); - - uinfo("EP0: pmalen=%d\n", pmalen); - usbtrace(TRACE_READ(EP0), pmalen); - - /* Read the data into our special buffer for SETUP data */ - - readlen = MIN(CONFIG_USBDEV_SETUP_MAXDATASIZE, pmalen); - src = stm32_geteprxaddr(EP0); - - /* Receive the next packet */ - - stm32_copyfrompma(&priv->ep0data[0], src, readlen); - - /* Now we can process the setup command */ - - priv->ep0state = EP0STATE_SETUP_READY; - priv->ep0datlen = readlen; - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EP0SETUPOUTDATA), - readlen); - - stm32_ep0setup(priv); - priv->ep0datlen = 0; /* mark the date consumed */ - - return OK; -} - -/**************************************************************************** - * Name: stm32_rdrequest - ****************************************************************************/ - -static int stm32_rdrequest(struct stm32_usbdev_s *priv, - struct stm32_ep_s *privep) -{ - struct stm32_req_s *privreq; - uint32_t src; - uint8_t *dest; - uint8_t epno; - int pmalen; - int readlen; - - /* Check the request from the head of the endpoint request queue */ - - epno = USB_EPNO(privep->ep.eplog); - privreq = stm32_rqpeek(privep); - if (!privreq) - { - /* Incoming data available in PMA, but no packet to receive the data. - * Mark that the RX data is pending and hope that a packet is returned - * soon. - */ - - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPOUTQEMPTY), epno); - return -ENOENT; - } - - uinfo("EP%d: len=%zu xfrd=%zu\n", - epno, privreq->req.len, privreq->req.xfrd); - - /* Ignore any attempt to receive a zero length packet */ - - if (privreq->req.len == 0) - { - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EPOUTNULLPACKET), 0); - stm32_reqcomplete(privep, OK); - return OK; - } - - usbtrace(TRACE_READ(USB_EPNO(privep->ep.eplog)), privreq->req.xfrd); - - /* Get the source and destination transfer addresses */ - - dest = privreq->req.buf + privreq->req.xfrd; - src = stm32_geteprxaddr(epno); - - /* Get the number of bytes to read from packet memory */ - - pmalen = stm32_geteprxcount(epno); - readlen = MIN(privreq->req.len, pmalen); - - /* Receive the next packet */ - - stm32_copyfrompma(dest, src, readlen); - - /* If the receive buffer is full or this is a partial packet, - * then we are finished with the request buffer). - */ - - privreq->req.xfrd += readlen; - if (pmalen < privep->ep.maxpacket || privreq->req.xfrd >= privreq->req.len) - { - /* Return the read request to the class driver. */ - - usbtrace(TRACE_COMPLETE(epno), privreq->req.xfrd); - stm32_reqcomplete(privep, OK); - } - - return OK; -} - -/**************************************************************************** - * Name: stm32_cancelrequests - ****************************************************************************/ - -static void stm32_cancelrequests(struct stm32_ep_s *privep) -{ - while (!stm32_rqempty(privep)) - { - usbtrace(TRACE_COMPLETE(USB_EPNO(privep->ep.eplog)), - (stm32_rqpeek(privep))->req.xfrd); - stm32_reqcomplete(privep, -ESHUTDOWN); - } -} - -/**************************************************************************** - * Interrupt Level Processing - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_dispatchrequest - ****************************************************************************/ - -static void stm32_dispatchrequest(struct stm32_usbdev_s *priv) -{ - int ret; - - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_DISPATCH), 0); - if (priv && priv->driver) - { - /* Forward to the control request to the class driver implementation */ - - ret = CLASS_SETUP(priv->driver, &priv->usbdev, &priv->ctrl, - priv->ep0data, priv->ep0datlen); - if (ret < 0) - { - /* Stall on failure */ - - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_DISPATCHSTALL), 0); - priv->ep0state = EP0STATE_STALLED; - } - } -} - -/**************************************************************************** - * Name: stm32_epdone - ****************************************************************************/ - -static void stm32_epdone(struct stm32_usbdev_s *priv, uint8_t epno) -{ - struct stm32_ep_s *privep; - uint16_t epr; - - /* Decode and service non control endpoints interrupt */ - - epr = stm32_getreg(STM32_USB_EPR(epno)); - privep = &priv->eplist[epno]; - - /* OUT: host-to-device - * CTR_RX is set by the hardware when an OUT/SETUP transaction - * successfully completed on this endpoint. - */ - - if ((epr & USB_EPR_CTR_RX) != 0) - { - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPOUTDONE), epr); - - /* Handle read requests. First check if a read request is available to - * accept the host data. - */ - - if (!stm32_rqempty(privep)) - { - /* Read host data into the current read request */ - - stm32_rdrequest(priv, privep); - - /* "After the received data is processed, the application software - * should set the STAT_RX bits to '11' (Valid) in the USB_EPnR, - * enabling further transactions. " - */ - - priv->rxstatus = USB_EPR_STATRX_VALID; - } - - /* NAK further OUT packets if there there no more read requests */ - - if (stm32_rqempty(privep)) - { - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPOUTPENDING), - (uint16_t)epno); - - /* Mark the RX processing as pending and NAK any OUT actions - * on this endpoint. "While the STAT_RX bits are equal to '10' - * (NAK), any OUT request addressed to that endpoint is NAKed, - * indicating a flow control condition: the USB host will retry - * the transaction until it succeeds." - */ - - priv->rxstatus = USB_EPR_STATRX_NAK; - priv->rxpending = true; - } - - /* Clear the interrupt status and set the new RX status */ - - stm32_clrepctrrx(epno); - stm32_seteprxstatus(epno, priv->rxstatus); - } - - /* IN: device-to-host - * CTR_TX is set when an IN transaction successfully completes on - * an endpoint - */ - - else if ((epr & USB_EPR_CTR_TX) != 0) - { - /* Clear interrupt status */ - - stm32_clrepctrtx(epno); - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPINDONE), epr); - - /* Handle write requests */ - - priv->txstatus = USB_EPR_STATTX_NAK; - if (epno == EP0) - { - stm32_wrrequest_ep0(priv, privep); - } - else - { - stm32_wrrequest(priv, privep); - } - - /* Set the new TX status */ - - stm32_seteptxstatus(epno, priv->txstatus); - } -} - -/**************************************************************************** - * Name: stm32_setdevaddr - ****************************************************************************/ - -static void stm32_setdevaddr(struct stm32_usbdev_s *priv, uint8_t value) -{ - int epno; - - /* Set address in every allocated endpoint */ - - for (epno = 0; epno < STM32_NENDPOINTS; epno++) - { - if (stm32_epreserved(priv, epno)) - { - stm32_setepaddress((uint8_t)epno, (uint8_t)epno); - } - } - - /* Set the device address and enable function */ - - stm32_putreg(value | USB_DADDR_EF, STM32_USB_DADDR); -} - -/**************************************************************************** - * Name: stm32_ep0setup - ****************************************************************************/ - -static void stm32_ep0setup(struct stm32_usbdev_s *priv) -{ - struct stm32_ep_s *ep0 = &priv->eplist[EP0]; - struct stm32_req_s *privreq = stm32_rqpeek(ep0); - struct stm32_ep_s *privep; - union wb_u value; - union wb_u index; - union wb_u len; - union wb_u response; - bool handled = false; - uint8_t epno; - int nbytes = 0; /* Assume zero-length packet */ - - /* Terminate any pending requests (doesn't work if the pending request - * was a zero-length transfer!) - */ - - while (!stm32_rqempty(ep0)) - { - int16_t result = OK; - if (privreq->req.xfrd != privreq->req.len) - { - result = -EPROTO; - } - - usbtrace(TRACE_COMPLETE(ep0->ep.eplog), privreq->req.xfrd); - stm32_reqcomplete(ep0, result); - } - - /* Assume NOT stalled; no TX in progress */ - - ep0->stalled = 0; - ep0->txbusy = 0; - - value.w = 0; - index.w = 0; - len.w = 0; - response.w = 0; - - /* Check to see if called from the DATA phase of a SETUP Transfer */ - - if (priv->ep0state != EP0STATE_SETUP_READY) - { - /* Not the data phase */ - - /* Get a 32-bit PMA address and use that to get the 8-byte setup - * request - */ - - stm32_copyfrompma((uint8_t *)&priv->ctrl, stm32_geteprxaddr(EP0), - USB_SIZEOF_CTRLREQ); - - /* And extract the little-endian 16-bit values to host order */ - - value.w = GETUINT16(priv->ctrl.value); - index.w = GETUINT16(priv->ctrl.index); - len.w = GETUINT16(priv->ctrl.len); - - uinfo("SETUP: type=%02x req=%02x value=%04x index=%04x len=%04x\n", - priv->ctrl.type, priv->ctrl.req, value.w, index.w, len.w); - - /* Is this an setup with OUT and data of length > 0 */ - - if (USB_REQ_ISOUT(priv->ctrl.type) && len.w > 0) - { - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EP0SETUPOUT), len.w); - - /* At this point priv->ctrl is the setup packet. */ - - priv->ep0state = EP0STATE_SETUP_OUT; - return; - } - else - { - priv->ep0state = EP0STATE_SETUP_READY; - } - } - - /* Dispatch any non-standard requests */ - - if ((priv->ctrl.type & USB_REQ_TYPE_MASK) != USB_REQ_TYPE_STANDARD) - { - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_NOSTDREQ), priv->ctrl.type); - - /* Let the class implementation handle all non-standar requests */ - - stm32_dispatchrequest(priv); - return; - } - - /* Handle standard request. Pick off the things of interest to the - * USB device controller driver; pass what is left to the class driver - */ - - switch (priv->ctrl.req) - { - case USB_REQ_GETSTATUS: - { - /* type: device-to-host; recipient = device, interface, endpoint - * value: 0 - * index: zero interface endpoint - * len: 2; data = status - */ - - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_GETSTATUS), - priv->ctrl.type); - if (len.w != 2 || (priv->ctrl.type & - USB_REQ_DIR_IN) == 0 || - index.b[MSB] != 0 || value.w != 0) - { - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADEPGETSTATUS), 0); - priv->ep0state = EP0STATE_STALLED; - } - else - { - switch (priv->ctrl.type & USB_REQ_RECIPIENT_MASK) - { - case USB_REQ_RECIPIENT_ENDPOINT: - { - epno = USB_EPNO(index.b[LSB]); - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPGETSTATUS), - epno); - if (epno >= STM32_NENDPOINTS) - { - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADEPGETSTATUS), - epno); - priv->ep0state = EP0STATE_STALLED; - } - else - { - response.w = 0; /* Not stalled */ - nbytes = 2; /* Response size: 2 bytes */ - - if (USB_ISEPIN(index.b[LSB])) - { - /* IN endpoint */ - - if (stm32_eptxstalled(epno)) - { - /* IN Endpoint stalled */ - - response.b[LSB] = 1; /* Stalled */ - } - } - else - { - /* OUT endpoint */ - - if (stm32_eprxstalled(epno)) - { - /* OUT Endpoint stalled */ - - response.b[LSB] = 1; /* Stalled */ - } - } - } - } - break; - - case USB_REQ_RECIPIENT_DEVICE: - { - if (index.w == 0) - { - usbtrace(TRACE_INTDECODE( - STM32_TRACEINTID_DEVGETSTATUS), 0); - - /* Features: Remote Wakeup=YES; selfpowered=? */ - - response.w = 0; - response.b[LSB] = (priv->selfpowered << - USB_FEATURE_SELFPOWERED) | - (1 << USB_FEATURE_REMOTEWAKEUP); - nbytes = 2; /* Response size: 2 bytes */ - } - else - { - usbtrace(TRACE_DEVERROR( - STM32_TRACEERR_BADDEVGETSTATUS), 0); - priv->ep0state = EP0STATE_STALLED; - } - } - break; - - case USB_REQ_RECIPIENT_INTERFACE: - { - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_IFGETSTATUS), 0); - response.w = 0; - nbytes = 2; /* Response size: 2 bytes */ - } - break; - - default: - { - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADGETSTATUS), 0); - priv->ep0state = EP0STATE_STALLED; - } - break; - } - } - } - break; - - case USB_REQ_CLEARFEATURE: - { - /* type: host-to-device; recipient = device, interface or endpoint - * value: feature selector - * index: zero interface endpoint; - * len: zero, data = none - */ - - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_CLEARFEATURE), - priv->ctrl.type); - if ((priv->ctrl.type & USB_REQ_RECIPIENT_MASK) != - USB_REQ_RECIPIENT_ENDPOINT) - { - /* Let the class implementation handle all recipients - * (except for the endpoint recipient) - */ - - stm32_dispatchrequest(priv); - handled = true; - } - else - { - /* Endpoint recipient */ - - epno = USB_EPNO(index.b[LSB]); - if (epno < STM32_NENDPOINTS && index.b[MSB] == 0 && - value.w == USB_FEATURE_ENDPOINTHALT && len.w == 0) - { - privep = &priv->eplist[epno]; - privep->halted = 0; - stm32_epstall(&privep->ep, true); - } - else - { - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADCLEARFEATURE), 0); - priv->ep0state = EP0STATE_STALLED; - } - } - } - break; - - case USB_REQ_SETFEATURE: - { - /* type: host-to-device; recipient = device, interface, endpoint - * value: feature selector - * index: zero interface endpoint; - * len: 0; data = none - */ - - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SETFEATURE), - priv->ctrl.type); - if (((priv->ctrl.type & USB_REQ_RECIPIENT_MASK) == - USB_REQ_RECIPIENT_DEVICE) && - value.w == USB_FEATURE_TESTMODE) - { - /* Special case recipient=device test mode */ - - uinfo("test mode: %d\n", index.w); - } - else if ((priv->ctrl.type & USB_REQ_RECIPIENT_MASK) != - USB_REQ_RECIPIENT_ENDPOINT) - { - /* The class driver handles all recipients except - * recipient=endpoint - */ - - stm32_dispatchrequest(priv); - handled = true; - } - else - { - /* Handler recipient=endpoint */ - - epno = USB_EPNO(index.b[LSB]); - if (epno < STM32_NENDPOINTS && index.b[MSB] == 0 && - value.w == USB_FEATURE_ENDPOINTHALT && len.w == 0) - { - privep = &priv->eplist[epno]; - privep->halted = 1; - stm32_epstall(&privep->ep, false); - } - else - { - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADSETFEATURE), 0); - priv->ep0state = EP0STATE_STALLED; - } - } - } - break; - - case USB_REQ_SETADDRESS: - { - /* type: host-to-device; recipient = device - * value: device address - * index: 0 - * len: 0; data = none - */ - - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EP0SETUPSETADDRESS), - value.w); - if ((priv->ctrl.type & USB_REQ_RECIPIENT_MASK) != - USB_REQ_RECIPIENT_DEVICE || - index.w != 0 || len.w != 0 || value.w > 127) - { - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADSETADDRESS), 0); - priv->ep0state = EP0STATE_STALLED; - } - /* Note that setting of the device address will be deferred. - * A zero-length packet will be sent and the device address - * will be set when the zero- length packet transfer completes. - */ - } - break; - - case USB_REQ_GETDESCRIPTOR: - /* type: device-to-host; recipient = device - * value: descriptor type and index - * index: 0 or language ID; - * len: descriptor len; data = descriptor - */ - - case USB_REQ_SETDESCRIPTOR: - /* type: host-to-device; recipient = device - * value: descriptor type and index - * index: 0 or language ID; - * len: descriptor len; data = descriptor - */ - - { - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_GETSETDESC), - priv->ctrl.type); - - /* The request seems valid... - * let the class implementation handle it - */ - - stm32_dispatchrequest(priv); - handled = true; - } - break; - - case USB_REQ_GETCONFIGURATION: - /* type: device-to-host; recipient = device - * value: 0; - * index: 0; - * len: 1; data = configuration value - */ - - { - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_GETCONFIG), - priv->ctrl.type); - if ((priv->ctrl.type & USB_REQ_RECIPIENT_MASK) == - USB_REQ_RECIPIENT_DEVICE && - value.w == 0 && index.w == 0 && len.w == 1) - { - /* The request seems valid... - * let the class implementation handle it - */ - - stm32_dispatchrequest(priv); - handled = true; - } - else - { - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADGETCONFIG), 0); - priv->ep0state = EP0STATE_STALLED; - } - } - break; - - case USB_REQ_SETCONFIGURATION: - /* type: host-to-device; recipient = device - * value: configuration value - * index: 0; - * len: 0; data = none - */ - - { - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SETCONFIG), - priv->ctrl.type); - if ((priv->ctrl.type & USB_REQ_RECIPIENT_MASK) == - USB_REQ_RECIPIENT_DEVICE && - index.w == 0 && len.w == 0) - { - /* The request seems valid... - * let the class implementation handle it - */ - - stm32_dispatchrequest(priv); - handled = true; - } - else - { - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADSETCONFIG), 0); - priv->ep0state = EP0STATE_STALLED; - } - } - break; - - case USB_REQ_GETINTERFACE: - /* type: device-to-host; recipient = interface - * value: 0 - * index: interface; - * len: 1; data = alt interface - */ - - case USB_REQ_SETINTERFACE: - /* type: host-to-device; recipient = interface - * value: alternate setting - * index: interface; - * len: 0; data = none - */ - - { - /* Let the class implementation handle the request */ - - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_GETSETIF), - priv->ctrl.type); - stm32_dispatchrequest(priv); - handled = true; - } - break; - - case USB_REQ_SYNCHFRAME: - /* type: device-to-host; recipient = endpoint - * value: 0 - * index: endpoint; - * len: 2; data = frame number - */ - - { - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SYNCHFRAME), 0); - } - break; - - default: - { - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDCTRLREQ), - priv->ctrl.req); - priv->ep0state = EP0STATE_STALLED; - } - break; - } - - /* At this point, the request has been handled and there are three possible - * outcomes: - * - * 1. The setup request was successfully handled above and a response - * packet must be sent (may be a zero length packet). - * 2. The request was successfully handled by the class implementation. - * In case, the EP0 IN response has already been queued and the local - * variable 'handled' will be set to true and - * ep0state != EP0STATE_STALLED; - * 3. An error was detected in either the above logic or by the class - * implementation logic. In either case, priv->state will be set - * EP0STATE_STALLED to indicate this case. - * - * NOTE: - * Non-standard requests are a special case. They are handled by the - * class implementation and this function returned early above, skipping - * this logic altogether. - */ - - if (priv->ep0state != EP0STATE_STALLED && !handled) - { - /* We will response. First, restrict the data length to the length - * requested in the setup packet - */ - - if (nbytes > len.w) - { - nbytes = len.w; - } - - /* Send the response (might be a zero-length packet) */ - - stm32_epwrite(priv, ep0, response.b, nbytes); - priv->ep0state = EP0STATE_IDLE; - } -} - -/**************************************************************************** - * Name: stm32_ep0in - ****************************************************************************/ - -static void stm32_ep0in(struct stm32_usbdev_s *priv) -{ - /* There is no longer anything in the EP0 TX packet memory */ - - priv->eplist[EP0].txbusy = false; - - /* Are we processing the completion of one packet of an outgoing request - * from the class driver? - */ - - if (priv->ep0state == EP0STATE_WRREQUEST) - { - stm32_wrrequest_ep0(priv, &priv->eplist[EP0]); - } - - /* No.. Are we processing the completion of a status response? */ - - else if (priv->ep0state == EP0STATE_IDLE) - { - /* Look at the saved SETUP command. Was it a SET ADDRESS request? - * If so, then now is the time to set the address. - */ - - if (priv->ctrl.req == USB_REQ_SETADDRESS && - (priv->ctrl.type & REQRECIPIENT_MASK) == - (USB_REQ_TYPE_STANDARD | USB_REQ_RECIPIENT_DEVICE)) - { - union wb_u value; - value.w = GETUINT16(priv->ctrl.value); - stm32_setdevaddr(priv, value.b[LSB]); - } - } - else - { - priv->ep0state = EP0STATE_STALLED; - } -} - -/**************************************************************************** - * Name: stm32_ep0out - ****************************************************************************/ - -static void stm32_ep0out(struct stm32_usbdev_s *priv) -{ - int ret; - - struct stm32_ep_s *privep = &priv->eplist[EP0]; - switch (priv->ep0state) - { - case EP0STATE_RDREQUEST: /* Read request in progress */ - case EP0STATE_IDLE: /* No transfer in progress */ - ret = stm32_rdrequest(priv, privep); - priv->ep0state = ((ret == OK) ? EP0STATE_RDREQUEST : EP0STATE_IDLE); - break; - - case EP0STATE_SETUP_OUT: /* SETUP was waiting for data */ - ret = stm32_ep0_rdrequest(priv); /* Off load the data and run the - * last set up command with the OUT - * data - */ - priv->ep0state = EP0STATE_IDLE; /* There is no notion of receiving OUT - * data greater then the length of - * CONFIG_USBDEV_SETUP_MAXDATASIZE - * so we are done - */ - break; - - default: - /* Unexpected state OR host aborted the OUT transfer before it - * completed, STALL the endpoint in either case - */ - - priv->ep0state = EP0STATE_STALLED; - break; - } -} - -/**************************************************************************** - * Name: stm32_ep0done - ****************************************************************************/ - -static inline void stm32_ep0done(struct stm32_usbdev_s *priv, uint16_t istr) -{ - uint16_t epr; - - /* Initialize RX and TX status. We shouldn't have to actually look at the - * status because the hardware is supposed to set the both RX and TX status - * to NAK when an EP0 SETUP occurs (of course, this might not be a setup) - */ - - priv->rxstatus = USB_EPR_STATRX_NAK; - priv->txstatus = USB_EPR_STATTX_NAK; - - /* Set both RX and TX status to NAK */ - - stm32_seteprxstatus(EP0, USB_EPR_STATRX_NAK); - stm32_seteptxstatus(EP0, USB_EPR_STATTX_NAK); - - /* Check the direction bit to determine if this the completion of an EP0 - * packet sent to or received from the host PC. - */ - - if ((istr & USB_ISTR_DIR) == 0) - { - /* EP0 IN: device-to-host (DIR=0) */ - - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EP0IN), istr); - stm32_clrepctrtx(EP0); - stm32_ep0in(priv); - } - else - { - /* EP0 OUT: host-to-device (DIR=1) */ - - epr = stm32_getreg(STM32_USB_EPR(EP0)); - - /* CTR_TX is set when an IN transaction successfully - * completes on an endpoint - */ - - if ((epr & USB_EPR_CTR_TX) != 0) - { - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EP0INDONE), epr); - stm32_clrepctrtx(EP0); - stm32_ep0in(priv); - } - - /* SETUP is set by the hardware when the last completed - * transaction was a control endpoint SETUP - */ - - else if ((epr & USB_EPR_SETUP) != 0) - { - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EP0SETUPDONE), epr); - stm32_clrepctrrx(EP0); - stm32_ep0setup(priv); - } - - /* Set by the hardware when an OUT/SETUP transaction successfully - * completed on this endpoint. - */ - - else if ((epr & USB_EPR_CTR_RX) != 0) - { - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EP0OUTDONE), epr); - stm32_clrepctrrx(EP0); - stm32_ep0out(priv); - } - - /* None of the above */ - - else - { - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EP0BADCTR), epr); - return; /* Does this ever happen? */ - } - } - - /* Make sure that the EP0 packet size is still OK (superstitious?) */ - - stm32_seteprxcount(EP0, STM32_EP0MAXPACKET); - - /* Now figure out the new RX/TX status. Here are all possible - * consequences of the above EP0 operations: - * - * rxstatus txstatus ep0state MEANING - * -------- -------- --------- --------------------------------- - * NAK NAK IDLE Nothing happened - * NAK VALID IDLE EP0 response sent from USBDEV driver - * NAK VALID WRREQUEST EP0 response sent from class driver - * NAK --- STALL Some protocol error occurred - * - * First handle the STALL condition: - */ - - if (priv->ep0state == EP0STATE_STALLED) - { - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EP0SETUPSTALLED), - priv->ep0state); - priv->rxstatus = USB_EPR_STATRX_STALL; - priv->txstatus = USB_EPR_STATTX_STALL; - } - - /* Was a transmission started? If so, txstatus will be VALID. The - * only special case to handle is when both are set to NAK. In that - * case, we need to set RX status to VALID in order to accept the next - * SETUP request. - */ - - else if (priv->rxstatus == USB_EPR_STATRX_NAK && - priv->txstatus == USB_EPR_STATTX_NAK) - { - priv->rxstatus = USB_EPR_STATRX_VALID; - } - - /* Now set the new TX and RX status */ - - stm32_seteprxstatus(EP0, priv->rxstatus); - stm32_seteptxstatus(EP0, priv->txstatus); -} - -/**************************************************************************** - * Name: stm32_lptransfer - ****************************************************************************/ - -static void stm32_lptransfer(struct stm32_usbdev_s *priv) -{ - uint8_t epno; - uint16_t istr; - - /* Stay in loop while LP interrupts are pending */ - - while (((istr = stm32_getreg(STM32_USB_ISTR)) & USB_ISTR_CTR) != 0) - { - stm32_putreg((uint16_t)~USB_ISTR_CTR, STM32_USB_ISTR); - - /* Extract highest priority endpoint number */ - - epno = (uint8_t)(istr & USB_ISTR_EPID_MASK); - - /* Handle EP0 completion events */ - - if (epno == 0) - { - stm32_ep0done(priv, istr); - } - - /* Handle other endpoint completion events */ - - else - { - stm32_epdone(priv, epno); - } - } -} - -/**************************************************************************** - * Name: stm32_hpinterrupt - ****************************************************************************/ - -static int stm32_hpinterrupt(int irq, void *context, void *arg) -{ - /* For now there is only one USB controller, but we will always refer to - * it using a pointer to make any future ports to multiple USB controllers - * easier. - */ - - struct stm32_usbdev_s *priv = &g_usbdev; - uint16_t istr; - uint8_t epno; - - /* High priority interrupts are only triggered by a correct transfer event - * for isochronous and double-buffer bulk transfers. - */ - - istr = stm32_getreg(STM32_USB_ISTR); - usbtrace(TRACE_INTENTRY(STM32_TRACEINTID_HPINTERRUPT), istr); - while ((istr & USB_ISTR_CTR) != 0) - { - stm32_putreg((uint16_t)~USB_ISTR_CTR, STM32_USB_ISTR); - - /* Extract highest priority endpoint number */ - - epno = (uint8_t)(istr & USB_ISTR_EPID_MASK); - - /* And handle the completion event */ - - stm32_epdone(priv, epno); - - /* Fetch the status again for the next time through the loop */ - - istr = stm32_getreg(STM32_USB_ISTR); - } - - usbtrace(TRACE_INTEXIT(STM32_TRACEINTID_HPINTERRUPT), 0); - return OK; -} - -/**************************************************************************** - * Name: stm32_lpinterrupt - ****************************************************************************/ - -static int stm32_lpinterrupt(int irq, void *context, void *arg) -{ - /* For now there is only one USB controller, but we will always refer to - * it using a pointer to make any future ports to multiple USB controllers - * easier. - */ - - struct stm32_usbdev_s *priv = &g_usbdev; - uint16_t istr = stm32_getreg(STM32_USB_ISTR); - - usbtrace(TRACE_INTENTRY(STM32_TRACEINTID_LPINTERRUPT), istr); - - /* Handle Reset interrupts. When this event occurs, the peripheral is left - * in the same conditions it is left by the system reset (but with the - * USB controller enabled). - */ - - if ((istr & USB_ISTR_RESET) != 0) - { - /* Reset interrupt received. Clear the RESET interrupt status. */ - - stm32_putreg(~USB_ISTR_RESET, STM32_USB_ISTR); - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_RESET), istr); - - /* Restore our power-up state and exit now because istr is no longer - * valid. - */ - - stm32_reset(priv); - goto exit_lpinterrupt; - } - - /* Handle Wakeup interrupts. - * This interrupt is only enable while the USB is suspended. - */ - - if ((istr & USB_ISTR_WKUP & priv->imask) != 0) - { - /* Wakeup interrupt received. Clear the WKUP interrupt status. The - * cause of the resume is indicated in the FNR register - */ - - stm32_putreg(~USB_ISTR_WKUP, STM32_USB_ISTR); - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_WKUP), - stm32_getreg(STM32_USB_FNR)); - - /* Perform the wakeup action */ - - stm32_initresume(priv); - priv->rsmstate = RSMSTATE_IDLE; - - /* Disable ESOF polling, disable the wakeup interrupt, and - * re-enable the suspend interrupt. Clear any pending SUSP - * interrupts. - */ - - stm32_setimask(priv, USB_CNTR_SUSPM, USB_CNTR_ESOFM | USB_CNTR_WKUPM); - stm32_putreg(~USB_CNTR_SUSPM, STM32_USB_ISTR); - } - - if ((istr & USB_ISTR_SUSP & priv->imask) != 0) - { - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SUSP), 0); - stm32_suspend(priv); - - /* Clear of the ISTR bit must be done after setting - * of USB_CNTR_FSUSP - */ - - stm32_putreg(~USB_ISTR_SUSP, STM32_USB_ISTR); - } - - if ((istr & USB_ISTR_ESOF & priv->imask) != 0) - { - stm32_putreg(~USB_ISTR_ESOF, STM32_USB_ISTR); - - /* Resume handling timing is made with ESOFs */ - - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_ESOF), 0); - stm32_esofpoll(priv); - } - - if ((istr & USB_ISTR_CTR & priv->imask) != 0) - { - /* Low priority endpoint correct transfer interrupt */ - - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_LPCTR), istr); - stm32_lptransfer(priv); - } - -exit_lpinterrupt: - usbtrace(TRACE_INTEXIT(STM32_TRACEINTID_LPINTERRUPT), - stm32_getreg(STM32_USB_EP0R)); - return OK; -} - -/**************************************************************************** - * Name: stm32_setimask - ****************************************************************************/ - -static void -stm32_setimask(struct stm32_usbdev_s *priv, - uint16_t setbits, uint16_t clrbits) -{ - uint16_t regval; - - /* Adjust the interrupt mask bits in the shadow copy first */ - - priv->imask &= ~clrbits; - priv->imask |= setbits; - - /* Then make the interrupt mask bits in the CNTR register match the shadow - * register (Hmmm... who is shadowing whom?) - */ - - regval = stm32_getreg(STM32_USB_CNTR); - regval &= ~USB_CNTR_ALLINTS; - regval |= priv->imask; - stm32_putreg(regval, STM32_USB_CNTR); -} - -/**************************************************************************** - * Suspend/Resume Helpers - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_suspend - ****************************************************************************/ - -static void stm32_suspend(struct stm32_usbdev_s *priv) -{ - uint16_t regval; - - /* Notify the class driver of the suspend event */ - - if (priv->driver) - { - CLASS_SUSPEND(priv->driver, &priv->usbdev); - } - - /* Disable ESOF polling, disable the SUSP interrupt, and enable the WKUP - * interrupt. Clear any pending WKUP interrupt. - */ - - stm32_setimask(priv, USB_CNTR_WKUPM, USB_CNTR_ESOFM | USB_CNTR_SUSPM); - stm32_putreg(~USB_ISTR_WKUP, STM32_USB_ISTR); - - /* Set the FSUSP bit in the CNTR register. This activates suspend mode - * within the USB peripheral and disables further SUSP interrupts. - */ - - regval = stm32_getreg(STM32_USB_CNTR); - regval |= USB_CNTR_FSUSP; - stm32_putreg(regval, STM32_USB_CNTR); - - /* If we are not a self-powered device, the got to low-power mode */ - - if (!priv->selfpowered) - { - /* Setting LPMODE in the CNTR register removes static power - * consumption in the USB analog transceivers but keeps them - * able to detect resume activity - */ - - regval = stm32_getreg(STM32_USB_CNTR); - regval |= USB_CNTR_LPMODE; - stm32_putreg(regval, STM32_USB_CNTR); - } - - /* Let the board-specific logic know that we have entered the suspend - * state - */ - - stm32_usbsuspend((struct usbdev_s *)priv, false); -} - -/**************************************************************************** - * Name: stm32_initresume - ****************************************************************************/ - -static void stm32_initresume(struct stm32_usbdev_s *priv) -{ - uint16_t regval; - - /* This function is called when either (1) a WKUP interrupt is received - * from the host PC, or (2) the class device implementation calls the - * wakeup() method. - */ - - /* Clear the USB low power mode (lower power mode was not set if this is - * a self-powered device. Also, low power mode is automatically cleared by - * hardware when a WKUP interrupt event occurs). - */ - - regval = stm32_getreg(STM32_USB_CNTR); - regval &= (~USB_CNTR_LPMODE); - stm32_putreg(regval, STM32_USB_CNTR); - - /* Restore full power -- whatever that means for this particular board */ - - stm32_usbsuspend((struct usbdev_s *)priv, true); - - /* Reset FSUSP bit and enable normal interrupt handling */ - - stm32_putreg(STM32_CNTR_SETUP, STM32_USB_CNTR); - - /* Notify the class driver of the resume event */ - - if (priv->driver) - { - CLASS_RESUME(priv->driver, &priv->usbdev); - } -} - -/**************************************************************************** - * Name: stm32_esofpoll - ****************************************************************************/ - -static void stm32_esofpoll(struct stm32_usbdev_s *priv) -{ - uint16_t regval; - - /* Called periodically from ESOF interrupt after RSMSTATE_STARTED */ - - switch (priv->rsmstate) - { - /* One ESOF after internal resume requested */ - - case RSMSTATE_STARTED: - regval = stm32_getreg(STM32_USB_CNTR); - regval |= USB_CNTR_RESUME; - stm32_putreg(regval, STM32_USB_CNTR); - priv->rsmstate = RSMSTATE_WAITING; - priv->nesofs = 10; - break; - - /* Countdown before completing the operation */ - - case RSMSTATE_WAITING: - priv->nesofs--; - if (priv->nesofs == 0) - { - /* Okay.. we are ready to resume normal operation */ - - regval = stm32_getreg(STM32_USB_CNTR); - regval &= (~USB_CNTR_RESUME); - stm32_putreg(regval, STM32_USB_CNTR); - priv->rsmstate = RSMSTATE_IDLE; - - /* Disable ESOF polling, disable the SUSP interrupt, and enable - * the WKUP interrupt. Clear any pending WKUP interrupt. - */ - - stm32_setimask(priv, - USB_CNTR_WKUPM, USB_CNTR_ESOFM | USB_CNTR_SUSPM); - stm32_putreg(~USB_ISTR_WKUP, STM32_USB_ISTR); - } - break; - - case RSMSTATE_IDLE: - default: - priv->rsmstate = RSMSTATE_IDLE; - break; - } -} - -/**************************************************************************** - * Endpoint Helpers - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_epreserve - ****************************************************************************/ - -static inline struct stm32_ep_s * -stm32_epreserve(struct stm32_usbdev_s *priv, uint8_t epset) -{ - struct stm32_ep_s *privep = NULL; - irqstate_t flags; - int epndx = 0; - - flags = enter_critical_section(); - epset &= priv->epavail; - if (epset) - { - /* Select the lowest bit in the set of matching, available endpoints - * (skipping EP0) - */ - - for (epndx = 1; epndx < STM32_NENDPOINTS; epndx++) - { - uint8_t bit = STM32_ENDP_BIT(epndx); - if ((epset & bit) != 0) - { - /* Mark the endpoint no longer available */ - - priv->epavail &= ~bit; - - /* And return the pointer to the standard endpoint structure */ - - privep = &priv->eplist[epndx]; - break; - } - } - } - - leave_critical_section(flags); - return privep; -} - -/**************************************************************************** - * Name: stm32_epunreserve - ****************************************************************************/ - -static inline void -stm32_epunreserve(struct stm32_usbdev_s *priv, struct stm32_ep_s *privep) -{ - irqstate_t flags = enter_critical_section(); - priv->epavail |= STM32_ENDP_BIT(USB_EPNO(privep->ep.eplog)); - leave_critical_section(flags); -} - -/**************************************************************************** - * Name: stm32_epreserved - ****************************************************************************/ - -static inline bool -stm32_epreserved(struct stm32_usbdev_s *priv, int epno) -{ - return ((priv->epavail & STM32_ENDP_BIT(epno)) == 0); -} - -/**************************************************************************** - * Name: stm32_epallocpma - ****************************************************************************/ - -static int stm32_epallocpma(struct stm32_usbdev_s *priv) -{ - irqstate_t flags; - int bufno = ERROR; - int bufndx; - - flags = enter_critical_section(); - for (bufndx = 2; bufndx < STM32_NBUFFERS; bufndx++) - { - /* Check if this buffer is available */ - - uint8_t bit = STM32_BUFFER_BIT(bufndx); - if ((priv->bufavail & bit) != 0) - { - /* Yes.. Mark the endpoint no longer available */ - - priv->bufavail &= ~bit; - - /* And return the index of the allocated buffer */ - - bufno = bufndx; - break; - } - } - - leave_critical_section(flags); - return bufno; -} - -/**************************************************************************** - * Name: stm32_epfreepma - ****************************************************************************/ - -static inline void -stm32_epfreepma(struct stm32_usbdev_s *priv, struct stm32_ep_s *privep) -{ - irqstate_t flags = enter_critical_section(); - priv->epavail |= STM32_ENDP_BIT(privep->bufno); - leave_critical_section(flags); -} - -/**************************************************************************** - * Endpoint operations - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_epconfigure - ****************************************************************************/ - -static int stm32_epconfigure(struct usbdev_ep_s *ep, - const struct usb_epdesc_s *desc, - bool last) -{ - struct stm32_ep_s *privep = (struct stm32_ep_s *)ep; - uint16_t pma; - uint16_t setting; - uint16_t maxpacket; - uint8_t epno; - -#ifdef CONFIG_DEBUG_FEATURES - if (!ep || !desc) - { - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); - uerr("ERROR: ep=%p desc=%p\n", ep, desc); - return -EINVAL; - } -#endif - - /* Get the unadorned endpoint address */ - - epno = USB_EPNO(desc->addr); - usbtrace(TRACE_EPCONFIGURE, (uint16_t)epno); - DEBUGASSERT(epno == USB_EPNO(ep->eplog)); - - /* Set the requested type */ - - switch (desc->attr & USB_EP_ATTR_XFERTYPE_MASK) - { - case USB_EP_ATTR_XFER_INT: /* Interrupt endpoint */ - setting = USB_EPR_EPTYPE_INTERRUPT; - break; - - case USB_EP_ATTR_XFER_BULK: /* Bulk endpoint */ - setting = USB_EPR_EPTYPE_BULK; - break; - - case USB_EP_ATTR_XFER_ISOC: /* Isochronous endpoint */ -#warning "REVISIT: Need to review isochronous EP setup" - setting = USB_EPR_EPTYPE_ISOC; - break; - - case USB_EP_ATTR_XFER_CONTROL: /* Control endpoint */ - setting = USB_EPR_EPTYPE_CONTROL; - break; - - default: - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADEPTYPE), - (uint16_t)desc->type); - return -EINVAL; - } - - stm32_seteptype(epno, setting); - - /* Get the address of the PMA buffer allocated for this endpoint */ - -#warning "REVISIT: Should configure BULK EPs using double buffer feature" - pma = STM32_BUFNO2BUF(privep->bufno); - - /* Get the maxpacket size of the endpoint. */ - - maxpacket = GETUINT16(desc->mxpacketsize); - DEBUGASSERT(maxpacket <= STM32_MAXPACKET_SIZE); - ep->maxpacket = maxpacket; - - /* Get the subset matching the requested direction */ - - if (USB_ISEPIN(desc->addr)) - { - /* The full, logical EP number includes direction */ - - ep->eplog = USB_EPIN(epno); - - /* Set up TX; disable RX */ - - stm32_seteptxaddr(epno, pma); - stm32_seteptxstatus(epno, USB_EPR_STATTX_NAK); - stm32_seteprxstatus(epno, USB_EPR_STATRX_DIS); - } - else - { - /* The full, logical EP number includes direction */ - - ep->eplog = USB_EPOUT(epno); - - /* Set up RX; disable TX */ - - stm32_seteprxaddr(epno, pma); - stm32_seteprxcount(epno, maxpacket); - stm32_seteprxstatus(epno, USB_EPR_STATRX_VALID); - stm32_seteptxstatus(epno, USB_EPR_STATTX_DIS); - } - - stm32_dumpep(epno); - return OK; -} - -/**************************************************************************** - * Name: stm32_epdisable - ****************************************************************************/ - -static int stm32_epdisable(struct usbdev_ep_s *ep) -{ - struct stm32_ep_s *privep = (struct stm32_ep_s *)ep; - irqstate_t flags; - uint8_t epno; - -#ifdef CONFIG_DEBUG_FEATURES - if (!ep) - { - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); - uerr("ERROR: ep=%p\n", ep); - return -EINVAL; - } -#endif - - epno = USB_EPNO(ep->eplog); - usbtrace(TRACE_EPDISABLE, epno); - - /* Cancel any ongoing activity */ - - flags = enter_critical_section(); - stm32_cancelrequests(privep); - - /* Disable TX; disable RX */ - - stm32_seteprxcount(epno, 0); - stm32_seteprxstatus(epno, USB_EPR_STATRX_DIS); - stm32_seteptxstatus(epno, USB_EPR_STATTX_DIS); - - leave_critical_section(flags); - return OK; -} - -/**************************************************************************** - * Name: stm32_epallocreq - ****************************************************************************/ - -static struct usbdev_req_s *stm32_epallocreq(struct usbdev_ep_s *ep) -{ - struct stm32_req_s *privreq; - -#ifdef CONFIG_DEBUG_FEATURES - if (!ep) - { - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); - return NULL; - } -#endif - usbtrace(TRACE_EPALLOCREQ, USB_EPNO(ep->eplog)); - - privreq = kmm_malloc(sizeof(struct stm32_req_s)); - if (!privreq) - { - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_ALLOCFAIL), 0); - return NULL; - } - - memset(privreq, 0, sizeof(struct stm32_req_s)); - return &privreq->req; -} - -/**************************************************************************** - * Name: stm32_epfreereq - ****************************************************************************/ - -static void stm32_epfreereq(struct usbdev_ep_s *ep, struct usbdev_req_s *req) -{ - struct stm32_req_s *privreq = (struct stm32_req_s *)req; - -#ifdef CONFIG_DEBUG_FEATURES - if (!ep || !req) - { - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); - return; - } -#endif - usbtrace(TRACE_EPFREEREQ, USB_EPNO(ep->eplog)); - - kmm_free(privreq); -} - -/**************************************************************************** - * Name: stm32_epsubmit - ****************************************************************************/ - -static int stm32_epsubmit(struct usbdev_ep_s *ep, struct usbdev_req_s *req) -{ - struct stm32_req_s *privreq = (struct stm32_req_s *)req; - struct stm32_ep_s *privep = (struct stm32_ep_s *)ep; - struct stm32_usbdev_s *priv; - irqstate_t flags; - uint8_t epno; - int ret = OK; - -#ifdef CONFIG_DEBUG_FEATURES - if (!req || !req->callback || !req->buf || !ep) - { - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); - uerr("ERROR: req=%p callback=%p buf=%p ep=%p\n", - req, req->callback, req->buf, ep); - return -EINVAL; - } -#endif - - usbtrace(TRACE_EPSUBMIT, USB_EPNO(ep->eplog)); - priv = privep->dev; - -#ifdef CONFIG_DEBUG_FEATURES - if (!priv->driver) - { - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_NOTCONFIGURED), - priv->usbdev.speed); - uerr("ERROR: driver=%p\n", priv->driver); - return -ESHUTDOWN; - } -#endif - - /* Handle the request from the class driver */ - - epno = USB_EPNO(ep->eplog); - req->result = -EINPROGRESS; - req->xfrd = 0; - flags = enter_critical_section(); - - /* If we are stalled, then drop all requests on the floor */ - - if (privep->stalled) - { - stm32_abortrequest(privep, privreq, -EBUSY); - uerr("ERROR: stalled\n"); - ret = -EBUSY; - } - - /* Handle IN (device-to-host) requests. NOTE: If the class device is - * using the bi-directional EP0, then we assume that they intend the EP0 - * IN functionality. - */ - - else if (USB_ISEPIN(ep->eplog) || epno == EP0) - { - /* Add the new request to the request queue for the IN endpoint */ - - stm32_rqenqueue(privep, privreq); - usbtrace(TRACE_INREQQUEUED(epno), req->len); - - /* If the IN endpoint FIFO is available, then transfer the data now */ - - if (!privep->txbusy) - { - priv->txstatus = USB_EPR_STATTX_NAK; - if (epno == EP0) - { - ret = stm32_wrrequest_ep0(priv, privep); - } - else - { - ret = stm32_wrrequest(priv, privep); - } - - /* Set the new TX status */ - - stm32_seteptxstatus(epno, priv->txstatus); - } - } - - /* Handle OUT (host-to-device) requests */ - - else - { - /* Add the new request to the request queue for the OUT endpoint */ - - privep->txnullpkt = 0; - stm32_rqenqueue(privep, privreq); - usbtrace(TRACE_OUTREQQUEUED(epno), req->len); - - /* This there a incoming data pending the availability of a request? */ - - if (priv->rxpending) - { - /* Set STAT_RX bits to '11' in the USB_EPnR, enabling further - * transactions. "While the STAT_RX bits are equal to '10' - * (NAK), any OUT request addressed to that endpoint is NAKed, - * indicating a flow control condition: the USB host will retry - * the transaction until it succeeds." - */ - - priv->rxstatus = USB_EPR_STATRX_VALID; - stm32_seteprxstatus(epno, priv->rxstatus); - - /* Data is no longer pending */ - - priv->rxpending = false; - } - } - - leave_critical_section(flags); - return ret; -} - -/**************************************************************************** - * Name: stm32_epcancel - ****************************************************************************/ - -static int stm32_epcancel(struct usbdev_ep_s *ep, struct usbdev_req_s *req) -{ - struct stm32_ep_s *privep = (struct stm32_ep_s *)ep; - irqstate_t flags; - -#ifdef CONFIG_DEBUG_USB - if (!ep || !req) - { - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); - return -EINVAL; - } -#endif - usbtrace(TRACE_EPCANCEL, USB_EPNO(ep->eplog)); - - flags = enter_critical_section(); - stm32_cancelrequests(privep); - leave_critical_section(flags); - return OK; -} - -/**************************************************************************** - * Name: stm32_epstall - ****************************************************************************/ - -static int stm32_epstall(struct usbdev_ep_s *ep, bool resume) -{ - struct stm32_ep_s *privep; - struct stm32_usbdev_s *priv; - uint8_t epno; - uint16_t status; - irqstate_t flags; - -#ifdef CONFIG_DEBUG_USB - if (!ep) - { - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); - return -EINVAL; - } -#endif - - privep = (struct stm32_ep_s *)ep; - priv = (struct stm32_usbdev_s *)privep->dev; - epno = USB_EPNO(ep->eplog); - - /* STALL or RESUME the endpoint */ - - flags = enter_critical_section(); - usbtrace(resume ? TRACE_EPRESUME : TRACE_EPSTALL, USB_EPNO(ep->eplog)); - - /* Get status of the endpoint; stall the request if the endpoint is - * disabled - */ - - if (USB_ISEPIN(ep->eplog)) - { - status = stm32_geteptxstatus(epno); - } - else - { - status = stm32_geteprxstatus(epno); - } - - if (status == 0) - { - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EPDISABLED), 0); - - if (epno == 0) - { - priv->ep0state = EP0STATE_STALLED; - } - - leave_critical_section(flags); - return -ENODEV; - } - - /* Handle the resume condition */ - - if (resume) - { - /* Resuming a stalled endpoint */ - - usbtrace(TRACE_EPRESUME, epno); - privep->stalled = false; - - if (USB_ISEPIN(ep->eplog)) - { - /* IN endpoint */ - - if (stm32_eptxstalled(epno)) - { - stm32_clrtxdtog(epno); - - /* Restart any queued write requests */ - - priv->txstatus = USB_EPR_STATTX_NAK; - if (epno == EP0) - { - stm32_wrrequest_ep0(priv, privep); - } - else - { - stm32_wrrequest(priv, privep); - } - - /* Set the new TX status */ - - stm32_seteptxstatus(epno, priv->txstatus); - } - } - else - { - /* OUT endpoint */ - - if (stm32_eprxstalled(epno)) - { - if (epno == EP0) - { - /* After clear the STALL, enable the default endpoint - * receiver - */ - - stm32_seteprxcount(epno, ep->maxpacket); - } - else - { - stm32_clrrxdtog(epno); - } - - priv->rxstatus = USB_EPR_STATRX_VALID; - stm32_seteprxstatus(epno, USB_EPR_STATRX_VALID); - } - } - } - - /* Handle the stall condition */ - - else - { - usbtrace(TRACE_EPSTALL, epno); - privep->stalled = true; - - if (USB_ISEPIN(ep->eplog)) - { - /* IN endpoint */ - - priv->txstatus = USB_EPR_STATTX_STALL; - stm32_seteptxstatus(epno, USB_EPR_STATTX_STALL); - } - else - { - /* OUT endpoint */ - - priv->rxstatus = USB_EPR_STATRX_STALL; - stm32_seteprxstatus(epno, USB_EPR_STATRX_STALL); - } - } - - leave_critical_section(flags); - return OK; -} - -/**************************************************************************** - * Device Controller Operations - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_allocep - ****************************************************************************/ - -static struct usbdev_ep_s *stm32_allocep(struct usbdev_s *dev, uint8_t epno, - bool in, uint8_t eptype) -{ - struct stm32_usbdev_s *priv = (struct stm32_usbdev_s *)dev; - struct stm32_ep_s *privep = NULL; - uint8_t epset = STM32_ENDP_ALLSET; - int bufno; - - usbtrace(TRACE_DEVALLOCEP, (uint16_t)epno); -#ifdef CONFIG_DEBUG_USB - if (!dev) - { - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); - return NULL; - } -#endif - - /* Ignore any direction bits in the logical address */ - - epno = USB_EPNO(epno); - - /* A logical address of 0 means that any endpoint will do */ - - if (epno > 0) - { - /* Otherwise, we will return the endpoint structure only for the - * requested 'logical' endpoint. - * All of the other checks will still be performed. - * - * First, verify that the logical endpoint is in the range supported by - * by the hardware. - */ - - if (epno >= STM32_NENDPOINTS) - { - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADEPNO), (uint16_t)epno); - return NULL; - } - - /* Convert the logical address to a physical OUT endpoint address and - * remove all of the candidate endpoints from the bitset except for the - * the IN/OUT pair for this logical address. - */ - - epset = STM32_ENDP_BIT(epno); - } - - /* Check if the selected endpoint number is available */ - - privep = stm32_epreserve(priv, epset); - if (!privep) - { - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EPRESERVE), (uint16_t)epset); - goto errout; - } - - /* Allocate a PMA buffer for this endpoint */ - -#warning "REVISIT: Should configure BULK EPs using double buffer feature" - bufno = stm32_epallocpma(priv); - if (bufno < 0) - { - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EPBUFFER), 0); - goto errout_with_ep; - } - - privep->bufno = (uint8_t)bufno; - return &privep->ep; - -errout_with_ep: - stm32_epunreserve(priv, privep); -errout: - return NULL; -} - -/**************************************************************************** - * Name: stm32_freeep - ****************************************************************************/ - -static void stm32_freeep(struct usbdev_s *dev, struct usbdev_ep_s *ep) -{ - struct stm32_usbdev_s *priv; - struct stm32_ep_s *privep; - -#ifdef CONFIG_DEBUG_USB - if (!dev || !ep) - { - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); - return; - } -#endif - priv = (struct stm32_usbdev_s *)dev; - privep = (struct stm32_ep_s *)ep; - usbtrace(TRACE_DEVFREEEP, (uint16_t)USB_EPNO(ep->eplog)); - - if (priv && privep) - { - /* Free the PMA buffer assigned to this endpoint */ - - stm32_epfreepma(priv, privep); - - /* Mark the endpoint as available */ - - stm32_epunreserve(priv, privep); - } -} - -/**************************************************************************** - * Name: stm32_getframe - ****************************************************************************/ - -static int stm32_getframe(struct usbdev_s *dev) -{ - uint16_t fnr; - -#ifdef CONFIG_DEBUG_USB - if (!dev) - { - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); - return -EINVAL; - } -#endif - - /* Return the last frame number detected by the hardware */ - - fnr = stm32_getreg(STM32_USB_FNR); - usbtrace(TRACE_DEVGETFRAME, fnr); - return (fnr & USB_FNR_FN_MASK); -} - -/**************************************************************************** - * Name: stm32_wakeup - ****************************************************************************/ - -static int stm32_wakeup(struct usbdev_s *dev) -{ - struct stm32_usbdev_s *priv = (struct stm32_usbdev_s *)dev; - irqstate_t flags; - - usbtrace(TRACE_DEVWAKEUP, 0); -#ifdef CONFIG_DEBUG_USB - if (!dev) - { - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); - return -EINVAL; - } -#endif - - /* Start the resume sequence. The actual resume steps will be driven - * by the ESOF interrupt. - */ - - flags = enter_critical_section(); - stm32_initresume(priv); - priv->rsmstate = RSMSTATE_STARTED; - - /* Disable the SUSP interrupt (until we are fully resumed), disable - * the WKUP interrupt (we are already waking up), and enable the - * ESOF interrupt that will drive the resume operations. Clear any - * pending ESOF interrupt. - */ - - stm32_setimask(priv, USB_CNTR_ESOFM, USB_CNTR_WKUPM | USB_CNTR_SUSPM); - stm32_putreg(~USB_ISTR_ESOF, STM32_USB_ISTR); - leave_critical_section(flags); - return OK; -} - -/**************************************************************************** - * Name: stm32_selfpowered - ****************************************************************************/ - -static int stm32_selfpowered(struct usbdev_s *dev, bool selfpowered) -{ - struct stm32_usbdev_s *priv = (struct stm32_usbdev_s *)dev; - - usbtrace(TRACE_DEVSELFPOWERED, (uint16_t)selfpowered); - -#ifdef CONFIG_DEBUG_USB - if (!dev) - { - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); - return -ENODEV; - } -#endif - - priv->selfpowered = selfpowered; - return OK; -} - -/**************************************************************************** - * Initialization/Reset - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_reset - ****************************************************************************/ - -static void stm32_reset(struct stm32_usbdev_s *priv) -{ - int epno; - - /* Put the USB controller in reset, disable all interrupts */ - - stm32_putreg(USB_CNTR_FRES, STM32_USB_CNTR); - - /* Tell the class driver that we are disconnected. The class driver - * should then accept any new configurations. - */ - - CLASS_DISCONNECT(priv->driver, &priv->usbdev); - - /* Reset the device state structure */ - - priv->ep0state = EP0STATE_IDLE; - priv->rsmstate = RSMSTATE_IDLE; - priv->rxpending = false; - - /* Reset endpoints */ - - for (epno = 0; epno < STM32_NENDPOINTS; epno++) - { - struct stm32_ep_s *privep = &priv->eplist[epno]; - - /* Cancel any queued requests. Since they are canceled - * with status -ESHUTDOWN, then will not be requeued - * until the configuration is reset. NOTE: This should - * not be necessary... the CLASS_DISCONNECT above should - * result in the class implementation calling stm32_epdisable - * for each of its configured endpoints. - */ - - stm32_cancelrequests(privep); - - /* Reset endpoint status */ - - privep->stalled = false; - privep->halted = false; - privep->txbusy = false; - privep->txnullpkt = false; - } - - /* Re-configure the USB controller in its initial, unconnected state */ - - stm32_hwreset(priv); - priv->usbdev.speed = USB_SPEED_FULL; -} - -/**************************************************************************** - * Name: stm32_hwreset - ****************************************************************************/ - -static void stm32_hwreset(struct stm32_usbdev_s *priv) -{ - /* Put the USB controller into reset, clear all interrupt enables */ - - stm32_putreg(USB_CNTR_FRES, STM32_USB_CNTR); - - /* Disable interrupts (and perhaps take the USB controller out of reset) */ - - priv->imask = 0; - stm32_putreg(priv->imask, STM32_USB_CNTR); - - /* Set the STM32 BTABLE address */ - - stm32_putreg(STM32_BTABLE_ADDRESS & 0xfff8, STM32_USB_BTABLE); - - /* Initialize EP0 */ - - stm32_seteptype(EP0, USB_EPR_EPTYPE_CONTROL); - stm32_seteptxstatus(EP0, USB_EPR_STATTX_NAK); - stm32_seteprxaddr(EP0, STM32_EP0_RXADDR); - stm32_seteprxcount(EP0, STM32_EP0MAXPACKET); - stm32_seteptxaddr(EP0, STM32_EP0_TXADDR); - stm32_clrstatusout(EP0); - stm32_seteprxstatus(EP0, USB_EPR_STATRX_VALID); - - /* Set the device to respond on default address */ - - stm32_setdevaddr(priv, 0); - - /* Clear any pending interrupts */ - - stm32_putreg(0, STM32_USB_ISTR); - - /* Enable interrupts at the USB controller */ - - stm32_setimask(priv, STM32_CNTR_SETUP, - (USB_CNTR_ALLINTS & ~STM32_CNTR_SETUP)); - stm32_dumpep(EP0); -} - -/**************************************************************************** - * Name: stm32_hwsetup - ****************************************************************************/ - -static void stm32_hwsetup(struct stm32_usbdev_s *priv) -{ - int epno; - - /* Power the USB controller, put the USB controller into reset, disable - * all USB interrupts - */ - - stm32_putreg(USB_CNTR_FRES | USB_CNTR_PDWN, STM32_USB_CNTR); - - /* Disconnect the device / disable the pull-up. We don't want the - * host to enumerate us until the class driver is registered. - */ - - stm32_usbpullup(&priv->usbdev, false); - - /* Initialize the device state structure. NOTE: many fields - * have the initial value of zero and, hence, are not explicitly - * initialized here. - */ - - memset(priv, 0, sizeof(struct stm32_usbdev_s)); - priv->usbdev.ops = &g_devops; - priv->usbdev.ep0 = &priv->eplist[EP0].ep; - priv->epavail = STM32_ENDP_ALLSET & ~STM32_ENDP_BIT(EP0); - priv->bufavail = STM32_BUFFER_ALLSET & ~STM32_BUFFER_EP0; - - /* Initialize the endpoint list */ - - for (epno = 0; epno < STM32_NENDPOINTS; epno++) - { - /* Set endpoint operations, reference to driver structure (not - * really necessary because there is only one controller), and - * the (physical) endpoint number which is just the index to the - * endpoint. - */ - - priv->eplist[epno].ep.ops = &g_epops; - priv->eplist[epno].dev = priv; - priv->eplist[epno].ep.eplog = epno; - - /* We will use a fixed maxpacket size for all endpoints (perhaps - * ISOC endpoints could have larger maxpacket???). A smaller - * packet size can be selected when the endpoint is configured. - */ - - priv->eplist[epno].ep.maxpacket = STM32_MAXPACKET_SIZE; - } - - /* Select a smaller endpoint size for EP0 */ - -#if STM32_EP0MAXPACKET < STM32_MAXPACKET_SIZE - priv->eplist[EP0].ep.maxpacket = STM32_EP0MAXPACKET; -#endif - - /* Configure the USB controller. USB uses the following GPIO pins: - * - * PA9 - VBUS - * PA10 - ID - * PA11 - DM - * PA12 - DP - * - * "As soon as the USB is enabled, these pins [DM and DP] are connected to - * the USB internal transceiver automatically." - */ - - /* Power up the USB controller, holding it in reset. There is a delay of - * about 1uS after applying power before the USB will behave predictably. - * A 5MS delay is more than enough. NOTE that we leave the USB controller - * in the reset state; the hardware will not be initialized until the - * class driver has been bound. - */ - - stm32_putreg(USB_CNTR_FRES, STM32_USB_CNTR); - up_mdelay(5); -} - -/**************************************************************************** - * Name: stm32_hwshutdown - ****************************************************************************/ - -static void stm32_hwshutdown(struct stm32_usbdev_s *priv) -{ - priv->usbdev.speed = USB_SPEED_UNKNOWN; - - /* Disable all interrupts and force the USB controller into reset */ - - stm32_putreg(USB_CNTR_FRES, STM32_USB_CNTR); - - /* Clear any pending interrupts */ - - stm32_putreg(0, STM32_USB_ISTR); - - /* Disconnect the device / disable the pull-up */ - - stm32_usbpullup(&priv->usbdev, false); - - /* Power down the USB controller */ - - stm32_putreg(USB_CNTR_FRES | USB_CNTR_PDWN, STM32_USB_CNTR); -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: arm_usbinitialize - * Description: - * Initialize the USB driver - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -void arm_usbinitialize(void) -{ - /* For now there is only one USB controller, but we will always refer to - * it using a pointer to make any future ports to multiple USB controllers - * easier. - */ - - struct stm32_usbdev_s *priv = &g_usbdev; - - usbtrace(TRACE_DEVINIT, 0); - stm32_checksetup(); - - /* Configure USB GPIO alternate function pins */ - -#ifdef CONFIG_STM32_STM32F30XX - stm32_configgpio(GPIO_USB_DM); - stm32_configgpio(GPIO_USB_DP); -#endif - - /* Power up the USB controller, but leave it in the reset state */ - - stm32_hwsetup(priv); - - /* Remap the USB interrupt as needed - * (Only supported by the STM32 F3 family) - */ - -#ifdef CONFIG_STM32_STM32F30XX -# ifdef CONFIG_STM32_USB_ITRMP - /* Clear the ITRMP bit to use the legacy, shared USB/CAN interrupts */ - - modifyreg32(STM32_RCC_APB1ENR, SYSCFG_CFGR1_USB_ITRMP, 0); -# else - /* Set the ITRMP bit to use the STM32 F3's dedicated USB interrupts */ - - modifyreg32(STM32_RCC_APB1ENR, 0, SYSCFG_CFGR1_USB_ITRMP); -# endif -#endif - - /* Attach USB controller interrupt handlers. The hardware will not be - * initialized and interrupts will not be enabled until the class device - * driver is bound. Getting the IRQs here only makes sure that we have - * them when we need them later. - */ - - if (irq_attach(STM32_IRQ_USBHP, stm32_hpinterrupt, NULL) != 0) - { - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_IRQREGISTRATION), - (uint16_t)STM32_IRQ_USBHP); - goto errout; - } - - if (irq_attach(STM32_IRQ_USBLP, stm32_lpinterrupt, NULL) != 0) - { - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_IRQREGISTRATION), - (uint16_t)STM32_IRQ_USBLP); - goto errout; - } - - return; - -errout: - arm_usbuninitialize(); -} - -/**************************************************************************** - * Name: arm_usbuninitialize - * Description: - * Initialize the USB driver - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -void arm_usbuninitialize(void) -{ - /* For now there is only one USB controller, but we will always refer to - * it using a pointer to make any future ports to multiple USB controllers - * easier. - */ - - struct stm32_usbdev_s *priv = &g_usbdev; - irqstate_t flags; - - flags = enter_critical_section(); - usbtrace(TRACE_DEVUNINIT, 0); - - /* Disable and detach the USB IRQs */ - - up_disable_irq(STM32_IRQ_USBHP); - up_disable_irq(STM32_IRQ_USBLP); - irq_detach(STM32_IRQ_USBHP); - irq_detach(STM32_IRQ_USBLP); - - if (priv->driver) - { - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_DRIVERREGISTERED), 0); - usbdev_unregister(priv->driver); - } - - /* Put the hardware in an inactive state */ - - stm32_hwshutdown(priv); - leave_critical_section(flags); -} - -/**************************************************************************** - * Name: usbdev_register - * - * Description: - * Register a USB device class driver. The class driver's bind() method - * will be called to bind it to a USB device driver. - * - ****************************************************************************/ - -int usbdev_register(struct usbdevclass_driver_s *driver) -{ - /* For now there is only one USB controller, but we will always refer to - * it using a pointer to make any future ports to multiple USB controllers - * easier. - */ - - struct stm32_usbdev_s *priv = &g_usbdev; - int ret; - - usbtrace(TRACE_DEVREGISTER, 0); - -#ifdef CONFIG_DEBUG_USB - if (!driver || !driver->ops->bind || !driver->ops->unbind || - !driver->ops->disconnect || !driver->ops->setup) - { - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); - return -EINVAL; - } - - if (priv->driver) - { - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_DRIVER), 0); - return -EBUSY; - } -#endif - - /* First hook up the driver */ - - priv->driver = driver; - - /* Then bind the class driver */ - - ret = CLASS_BIND(driver, &priv->usbdev); - if (ret) - { - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BINDFAILED), (uint16_t) - ret); - } - else - { - /* Setup the USB controller -- enabling interrupts at the USB - * controller - */ - - stm32_hwreset(priv); - - /* Enable USB controller interrupts at the NVIC */ - - up_enable_irq(STM32_IRQ_USBHP); - up_enable_irq(STM32_IRQ_USBLP); - - /* Enable pull-up to connect the device. The host should enumerate us - * some time after this - */ - - stm32_usbpullup(&priv->usbdev, true); - priv->usbdev.speed = USB_SPEED_FULL; - } - - return ret; -} - -/**************************************************************************** - * Name: usbdev_unregister - * - * Description: - * Un-register usbdev class driver. If the USB device is connected to a - * USB host, it will first disconnect(). The driver is also requested to - * unbind() and clean up any device state, before this procedure finally - * returns. - * - ****************************************************************************/ - -int usbdev_unregister(struct usbdevclass_driver_s *driver) -{ - /* For now there is only one USB controller, but we will always refer to - * it using a pointer to make any future ports to multiple USB controllers - * easier. - */ - - struct stm32_usbdev_s *priv = &g_usbdev; - irqstate_t flags; - - usbtrace(TRACE_DEVUNREGISTER, 0); - -#ifdef CONFIG_DEBUG_USB - if (driver != priv->driver) - { - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); - return -EINVAL; - } -#endif - - /* Reset the hardware and cancel all requests. All requests must be - * canceled while the class driver is still bound. - */ - - flags = enter_critical_section(); - stm32_reset(priv); - - /* Unbind the class driver */ - - CLASS_UNBIND(driver, &priv->usbdev); - - /* Disable USB controller interrupts (but keep them attached) */ - - up_disable_irq(STM32_IRQ_USBHP); - up_disable_irq(STM32_IRQ_USBLP); - - /* Put the hardware in an inactive state. Then bring the hardware back up - * in the reset state (this is probably not necessary, the stm32_reset() - * call above was probably sufficient). - */ - - stm32_hwshutdown(priv); - stm32_hwsetup(priv); - - /* Unhook the driver */ - - priv->driver = NULL; - leave_critical_section(flags); - return OK; -} - -#endif /* CONFIG_USBDEV && CONFIG_STM32_USB */ diff --git a/arch/arm/src/stm32/stm32_usbdev.h b/arch/arm/src/stm32/stm32_usbdev.h deleted file mode 100644 index 350bbb234d30b..0000000000000 --- a/arch/arm/src/stm32/stm32_usbdev.h +++ /dev/null @@ -1,92 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_usbdev.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32_STM32_USBDEV_H -#define __ARCH_ARM_SRC_STM32_STM32_USBDEV_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include -#include - -#include "chip.h" -#include "hardware/stm32_usbdev.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Number of endpoints */ - -#define STM32_NENDPOINTS (8) - -/**************************************************************************** - * Public Functions Prototypes - ****************************************************************************/ - -#ifndef __ASSEMBLY__ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Name: stm32_usbpullup - * - * Description: - * If USB is supported and the board supports a pullup via GPIO (for USB - * software connect and disconnect), then the board software must provide - * stm32_pullup. See include/nuttx/usb/usbdev.h for additional description - * of this method. - * - ****************************************************************************/ - -int stm32_usbpullup(struct usbdev_s *dev, bool enable); - -/**************************************************************************** - * Name: stm32_usbsuspend - * - * Description: - * Board logic must provide the stm32_usbsuspend logic if the USBDEV driver - * is used. This function is called whenever the USB enters or leaves - * suspend mode. This is an opportunity for the board logic to shutdown - * clocks, power, etc. while the USB is suspended. - * - ****************************************************************************/ - -void stm32_usbsuspend(struct usbdev_s *dev, bool resume); - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32_STM32_USBDEV_H */ diff --git a/arch/arm/src/stm32/stm32_usbfs.c b/arch/arm/src/stm32/stm32_usbfs.c deleted file mode 100644 index cb6cf7f47459a..0000000000000 --- a/arch/arm/src/stm32/stm32_usbfs.c +++ /dev/null @@ -1,3987 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_usbfs.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include - -#include - -#include "arm_internal.h" -#include "stm32.h" -#include "stm32_syscfg.h" -#include "stm32_gpio.h" -#include "stm32_usbfs.h" - -#if defined(CONFIG_STM32_USBFS) - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -#ifndef CONFIG_USBDEV_EP0_MAXSIZE -# define CONFIG_USBDEV_EP0_MAXSIZE 64 -#endif - -#ifndef CONFIG_USBDEV_SETUP_MAXDATASIZE -# define CONFIG_USBDEV_SETUP_MAXDATASIZE CONFIG_USBDEV_EP0_MAXSIZE -#endif - -/* Extremely detailed register debug that you would normally never want - * enabled. - */ - -#ifndef CONFIG_DEBUG_USB_INFO -# undef CONFIG_STM32_USBFS_REGDEBUG -#endif - -/* Initial interrupt mask: Reset + Suspend + Correct Transfer */ - -#define STM32_CNTR_SETUP (USB_CNTR_RESETM|USB_CNTR_SUSPM|USB_CNTR_CTRM) - -/* Endpoint identifiers. The STM32 supports up to 16 mono-directional or 8 - * bidirectional endpoints. However, when you take into account PMA buffer - * usage (see below) and the fact that EP0 is bidirectional, then there is - * a functional limitation of EP0 + 5 mono-directional endpoints = 6. We'll - * define STM32_NENDPOINTS to be 8, however, because that is how many - * endpoint register sets there are. - */ - -#define EP0 (0) -#define EP1 (1) -#define EP2 (2) -#define EP3 (3) -#define EP4 (4) -#define EP5 (5) -#define EP6 (6) -#define EP7 (7) - -#define STM32_ENDP_BIT(ep) (1 << (ep)) -#define STM32_ENDP_ALLSET 0xff - -/* Packet sizes. We us a fixed 64 max packet size for all endpoint types */ - -#define STM32_MAXPACKET_SHIFT (6) -#define STM32_MAXPACKET_SIZE (1 << (STM32_MAXPACKET_SHIFT)) -#define STM32_MAXPACKET_MASK (STM32_MAXPACKET_SIZE-1) - -#define STM32_EP0MAXPACKET STM32_MAXPACKET_SIZE - -/* Buffer descriptor table. We assume that USB has exclusive use of CAN/USB - * memory. The buffer table is positioned at the beginning of the 512-byte - * CAN/USB memory. We will use the first STM32_NENDPOINTS*4 words for the - * buffer table. - * That is exactly 64 bytes, leaving 7*64 bytes for endpoint buffers. - */ - -#define STM32_BTABLE_ADDRESS (0x00) /* Start at the beginning of USB/CAN RAM */ -#define STM32_DESC_SIZE (8) /* Each descriptor is 4*2=8 bytes in size */ -#define STM32_BTABLE_SIZE (STM32_NENDPOINTS*STM32_DESC_SIZE) - -/* Buffer layout. Assume that all buffers are 64-bytes (maxpacketsize), then - * we have space for only 7 buffers; endpoint 0 will require two buffers, - * leaving 5 for other endpoints. - */ - -#define STM32_BUFFER_START STM32_BTABLE_SIZE -#define STM32_EP0_RXADDR STM32_BUFFER_START -#define STM32_EP0_TXADDR (STM32_EP0_RXADDR+STM32_EP0MAXPACKET) - -#define STM32_BUFFER_EP0 0x03 -#define STM32_NBUFFERS 7 -#define STM32_BUFFER_BIT(bn) (1 << (bn)) -#define STM32_BUFFER_ALLSET 0x7f -#define STM32_BUFNO2BUF(bn) (STM32_BUFFER_START+((bn)<head == NULL) -#define stm32_rqpeek(ep) ((ep)->head) - -/* USB trace ****************************************************************/ - -/* Trace error codes */ - -#define STM32_TRACEERR_ALLOCFAIL 0x0001 -#define STM32_TRACEERR_BADCLEARFEATURE 0x0002 -#define STM32_TRACEERR_BADDEVGETSTATUS 0x0003 -#define STM32_TRACEERR_BADEPGETSTATUS 0x0004 -#define STM32_TRACEERR_BADEPNO 0x0005 -#define STM32_TRACEERR_BADEPTYPE 0x0006 -#define STM32_TRACEERR_BADGETCONFIG 0x0007 -#define STM32_TRACEERR_BADGETSETDESC 0x0008 -#define STM32_TRACEERR_BADGETSTATUS 0x0009 -#define STM32_TRACEERR_BADSETADDRESS 0x000a -#define STM32_TRACEERR_BADSETCONFIG 0x000b -#define STM32_TRACEERR_BADSETFEATURE 0x000c -#define STM32_TRACEERR_BINDFAILED 0x000d -#define STM32_TRACEERR_DISPATCHSTALL 0x000e -#define STM32_TRACEERR_DRIVER 0x000f -#define STM32_TRACEERR_DRIVERREGISTERED 0x0010 -#define STM32_TRACEERR_EP0BADCTR 0x0011 -#define STM32_TRACEERR_EP0SETUPSTALLED 0x0012 -#define STM32_TRACEERR_EPBUFFER 0x0013 -#define STM32_TRACEERR_EPDISABLED 0x0014 -#define STM32_TRACEERR_EPOUTNULLPACKET 0x0015 -#define STM32_TRACEERR_EPRESERVE 0x0016 -#define STM32_TRACEERR_INVALIDCTRLREQ 0x0017 -#define STM32_TRACEERR_INVALIDPARMS 0x0018 -#define STM32_TRACEERR_IRQREGISTRATION 0x0019 -#define STM32_TRACEERR_NOTCONFIGURED 0x001a -#define STM32_TRACEERR_REQABORTED 0x001b - -/* Trace interrupt codes */ - -#define STM32_TRACEINTID_CLEARFEATURE 0x0001 -#define STM32_TRACEINTID_DEVGETSTATUS 0x0002 -#define STM32_TRACEINTID_DISPATCH 0x0003 -#define STM32_TRACEINTID_EP0IN 0x0004 -#define STM32_TRACEINTID_EP0INDONE 0x0005 -#define STM32_TRACEINTID_EP0OUTDONE 0x0006 -#define STM32_TRACEINTID_EP0SETUPDONE 0x0007 -#define STM32_TRACEINTID_EP0SETUPSETADDRESS 0x0008 -#define STM32_TRACEINTID_EPGETSTATUS 0x0009 -#define STM32_TRACEINTID_EPINDONE 0x000a -#define STM32_TRACEINTID_EPINQEMPTY 0x000b -#define STM32_TRACEINTID_EPOUTDONE 0x000c -#define STM32_TRACEINTID_EPOUTPENDING 0x000d -#define STM32_TRACEINTID_EPOUTQEMPTY 0x000e -#define STM32_TRACEINTID_ESOF 0x000f -#define STM32_TRACEINTID_GETCONFIG 0x0010 -#define STM32_TRACEINTID_GETSETDESC 0x0011 -#define STM32_TRACEINTID_GETSETIF 0x0012 -#define STM32_TRACEINTID_GETSTATUS 0x0013 -#define STM32_TRACEINTID_HPINTERRUPT 0x0014 -#define STM32_TRACEINTID_IFGETSTATUS 0x0015 -#define STM32_TRACEINTID_LPCTR 0x0016 -#define STM32_TRACEINTID_LPINTERRUPT 0x0017 -#define STM32_TRACEINTID_NOSTDREQ 0x0018 -#define STM32_TRACEINTID_RESET 0x0019 -#define STM32_TRACEINTID_SETCONFIG 0x001a -#define STM32_TRACEINTID_SETFEATURE 0x001b -#define STM32_TRACEINTID_SUSP 0x001c -#define STM32_TRACEINTID_SYNCHFRAME 0x001d -#define STM32_TRACEINTID_WKUP 0x001e -#define STM32_TRACEINTID_EP0SETUPOUT 0x001f -#define STM32_TRACEINTID_EP0SETUPOUTDATA 0x0020 - -/* Byte ordering in host-based values */ - -#ifdef CONFIG_ENDIAN_BIG -# define LSB 1 -# define MSB 0 -#else -# define LSB 0 -# define MSB 1 -#endif - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/* The various states of a control pipe */ - -enum stm32_ep0state_e -{ - EP0STATE_IDLE = 0, /* No request in progress */ - EP0STATE_SETUP_OUT, /* Set up received with data for device OUT in progress */ - EP0STATE_SETUP_READY, /* Set up was received prior and is in ctrl, - * now the data has arrived */ - EP0STATE_WRREQUEST, /* Write request in progress */ - EP0STATE_RDREQUEST, /* Read request in progress */ - EP0STATE_STALLED /* We are stalled */ -}; - -/* Resume states */ - -enum stm32_rsmstate_e -{ - RSMSTATE_IDLE = 0, /* Device is either fully suspended or running */ - RSMSTATE_STARTED, /* Resume sequence has been started */ - RSMSTATE_WAITING /* Waiting (on ESOFs) for end of sequence */ -}; - -union wb_u -{ - uint16_t w; - uint8_t b[2]; -}; - -/* A container for a request so that the request make be retained in a list */ - -struct stm32_req_s -{ - struct usbdev_req_s req; /* Standard USB request */ - struct stm32_req_s *flink; /* Supports a singly linked list */ -}; - -/* This is the internal representation of an endpoint */ - -struct stm32_ep_s -{ - /* Common endpoint fields. This must be the first thing defined in the - * structure so that it is possible to simply cast from struct usbdev_ep_s - * to struct stm32_ep_s. - */ - - struct usbdev_ep_s ep; /* Standard endpoint structure */ - - /* STR71X-specific fields */ - - struct stm32_usbdev_s *dev; /* Reference to private driver data */ - struct stm32_req_s *head; /* Request list for this endpoint */ - struct stm32_req_s *tail; - uint8_t bufno; /* Allocated buffer number */ - uint8_t stalled:1; /* true: Endpoint is stalled */ - uint8_t halted:1; /* true: Endpoint feature halted */ - uint8_t txbusy:1; /* true: TX endpoint FIFO full */ - uint8_t txnullpkt:1; /* Null packet needed at end of transfer */ -}; - -struct stm32_usbdev_s -{ - /* Common device fields. This must be the first thing defined in the - * structure so that it is possible to simply cast from struct usbdev_s - * to structstm32_usbdev_s. - */ - - struct usbdev_s usbdev; - - /* The bound device class driver */ - - struct usbdevclass_driver_s *driver; - - /* STM32-specific fields */ - - uint8_t ep0state; /* State of EP0 (see enum stm32_ep0state_e) */ - uint8_t rsmstate; /* Resume state (see enum stm32_rsmstate_e) */ - uint8_t nesofs; /* ESOF counter (for resume support) */ - uint8_t rxpending:1; /* 1: OUT data in PMA, but no read requests */ - uint8_t selfpowered:1; /* 1: Device is self powered */ - uint8_t epavail; /* Bitset of available endpoints */ - uint8_t bufavail; /* Bitset of available buffers */ - uint16_t rxstatus; /* Saved during interrupt processing */ - uint16_t txstatus; /* " " " " " " " " */ - uint16_t imask; /* Current interrupt mask */ - - /* E0 SETUP data buffering. - * - * ctrl - * The 8-byte SETUP request is received on the EP0 OUT endpoint and is - * saved. - * - * ep0data - * For OUT SETUP requests, the SETUP data phase must also complete - * before the SETUP command can be processed. The ep0 packet receipt - * logic stm32_ep0_rdrequest will save the accompanying EP0 OUT data - * in ep0data[] before the SETUP command is re-processed. - * - * ep0datlen - * Length of OUT DATA received in ep0data[] - */ - - struct usb_ctrlreq_s ctrl; /* Last EP0 request */ - - uint8_t ep0data[CONFIG_USBDEV_SETUP_MAXDATASIZE]; - uint16_t ep0datlen; - - /* The endpoint list */ - - struct stm32_ep_s eplist[STM32_NENDPOINTS]; -}; - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -/* Register operations ******************************************************/ - -#ifdef CONFIG_STM32_USBFS_REGDEBUG -static uint16_t stm32_getreg(uint32_t addr); -static void stm32_putreg(uint16_t val, uint32_t addr); -static void stm32_checksetup(void); -static void stm32_dumpep(int epno); -#else -# define stm32_getreg(addr) getreg16(addr) -# define stm32_putreg(val,addr) putreg16(val,addr) -# define stm32_checksetup() -# define stm32_dumpep(epno) -#endif - -/* Low-Level Helpers ********************************************************/ - -static inline void - stm32_seteptxcount(uint8_t epno, uint16_t count); -static inline void - stm32_seteptxaddr(uint8_t epno, uint16_t addr); -static inline uint16_t - stm32_geteptxaddr(uint8_t epno); -static void stm32_seteprxcount(uint8_t epno, uint16_t count); -static inline uint16_t - stm32_geteprxcount(uint8_t epno); -static inline void - stm32_seteprxaddr(uint8_t epno, uint16_t addr); -static inline uint16_t - stm32_geteprxaddr(uint8_t epno); -static inline void - stm32_setepaddress(uint8_t epno, uint16_t addr); -static inline void - stm32_seteptype(uint8_t epno, uint16_t type); -static inline void - stm32_seteptxaddr(uint8_t epno, uint16_t addr); -static inline void - stm32_clrstatusout(uint8_t epno); -static void stm32_clrrxdtog(uint8_t epno); -static void stm32_clrtxdtog(uint8_t epno); -static void stm32_clrepctrrx(uint8_t epno); -static void stm32_clrepctrtx(uint8_t epno); -static void stm32_seteptxstatus(uint8_t epno, uint16_t state); -static void stm32_seteprxstatus(uint8_t epno, uint16_t state); -static inline uint16_t - stm32_geteptxstatus(uint8_t epno); -static inline uint16_t - stm32_geteprxstatus(uint8_t epno); -static bool stm32_eptxstalled(uint8_t epno); -static bool stm32_eprxstalled(uint8_t epno); -static void stm32_setimask(struct stm32_usbdev_s *priv, - uint16_t setbits, - uint16_t clrbits); - -/* Suspend/Resume Helpers ***************************************************/ - -static void stm32_suspend(struct stm32_usbdev_s *priv); -static void stm32_initresume(struct stm32_usbdev_s *priv); -static void stm32_esofpoll(struct stm32_usbdev_s *priv) ; - -/* Request Helpers **********************************************************/ - -static void stm32_copytopma(const uint8_t *buffer, uint16_t pma, - uint16_t nbytes); -static inline void stm32_copyfrompma(uint8_t *buffer, - uint16_t pma, uint16_t nbytes); -static struct stm32_req_s * - stm32_rqdequeue(struct stm32_ep_s *privep); -static void stm32_rqenqueue(struct stm32_ep_s *privep, - struct stm32_req_s *req); -static inline void - stm32_abortrequest(struct stm32_ep_s *privep, - struct stm32_req_s *privreq, int16_t result); -static void stm32_reqcomplete(struct stm32_ep_s *privep, int16_t result); -static void stm32_epwrite(struct stm32_usbdev_s *buf, - struct stm32_ep_s *privep, - const uint8_t *data, uint32_t nbytes); -static int stm32_wrrequest(struct stm32_usbdev_s *priv, - struct stm32_ep_s *privep); -inline static int - stm32_wrrequest_ep0(struct stm32_usbdev_s *priv, - struct stm32_ep_s *privep); -static inline int - stm32_ep0_rdrequest(struct stm32_usbdev_s *priv); -static int stm32_rdrequest(struct stm32_usbdev_s *priv, - struct stm32_ep_s *privep); -static void stm32_cancelrequests(struct stm32_ep_s *privep); - -/* Interrupt level processing ***********************************************/ - -static void stm32_dispatchrequest(struct stm32_usbdev_s *priv); -static void stm32_epdone(struct stm32_usbdev_s *priv, uint8_t epno); -static void stm32_setdevaddr(struct stm32_usbdev_s *priv, uint8_t value); -static void stm32_ep0setup(struct stm32_usbdev_s *priv); -static void stm32_ep0out(struct stm32_usbdev_s *priv); -static void stm32_ep0in(struct stm32_usbdev_s *priv); -static inline void - stm32_ep0done(struct stm32_usbdev_s *priv, uint16_t istr); -static void stm32_lptransfer(struct stm32_usbdev_s *priv); -static int stm32_hpinterrupt(int irq, void *context, void *arg); -static int stm32_lpinterrupt(int irq, void *context, void *arg); - -/* Endpoint helpers *********************************************************/ - -static inline struct stm32_ep_s * - stm32_epreserve(struct stm32_usbdev_s *priv, uint8_t epset); -static inline void - stm32_epunreserve(struct stm32_usbdev_s *priv, - struct stm32_ep_s *privep); -static inline bool - stm32_epreserved(struct stm32_usbdev_s *priv, int epno); -static int stm32_epallocpma(struct stm32_usbdev_s *priv); -static inline void - stm32_epfreepma(struct stm32_usbdev_s *priv, - struct stm32_ep_s *privep); - -/* Endpoint operations ******************************************************/ - -static int stm32_epconfigure(struct usbdev_ep_s *ep, - const struct usb_epdesc_s *desc, bool last); -static int stm32_epdisable(struct usbdev_ep_s *ep); -static struct usbdev_req_s * - stm32_epallocreq(struct usbdev_ep_s *ep); -static void stm32_epfreereq(struct usbdev_ep_s *ep, - struct usbdev_req_s *); -static int stm32_epsubmit(struct usbdev_ep_s *ep, - struct usbdev_req_s *req); -static int stm32_epcancel(struct usbdev_ep_s *ep, - struct usbdev_req_s *req); -static int stm32_epstall(struct usbdev_ep_s *ep, bool resume); - -/* USB device controller operations *****************************************/ - -static struct usbdev_ep_s * - stm32_allocep(struct usbdev_s *dev, uint8_t epno, bool in, - uint8_t eptype); -static void stm32_freeep(struct usbdev_s *dev, struct usbdev_ep_s *ep); -static int stm32_getframe(struct usbdev_s *dev); -static int stm32_wakeup(struct usbdev_s *dev); -static int stm32_selfpowered(struct usbdev_s *dev, bool selfpowered); -static int stm32_pullup(struct usbdev_s *dev, bool enable); - -/* Initialization/Reset *****************************************************/ - -static void stm32_reset(struct stm32_usbdev_s *priv); -static void stm32_hwreset(struct stm32_usbdev_s *priv); -static void stm32_hwsetup(struct stm32_usbdev_s *priv); -static void stm32_hwshutdown(struct stm32_usbdev_s *priv); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* Since there is only a single USB interface, all status information can be - * be simply retained in a single global instance. - */ - -static struct stm32_usbdev_s g_usbdev; - -static const struct usbdev_epops_s g_epops = -{ - .configure = stm32_epconfigure, - .disable = stm32_epdisable, - .allocreq = stm32_epallocreq, - .freereq = stm32_epfreereq, - .submit = stm32_epsubmit, - .cancel = stm32_epcancel, - .stall = stm32_epstall, -}; - -static const struct usbdev_ops_s g_devops = -{ - .allocep = stm32_allocep, - .freeep = stm32_freeep, - .getframe = stm32_getframe, - .wakeup = stm32_wakeup, - .selfpowered = stm32_selfpowered, - .pullup = stm32_pullup, -}; - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -#ifdef CONFIG_USBDEV_TRACE_STRINGS -const struct trace_msg_t g_usb_trace_strings_intdecode[] = -{ - TRACE_STR(STM32_TRACEINTID_CLEARFEATURE), - TRACE_STR(STM32_TRACEINTID_DEVGETSTATUS), - TRACE_STR(STM32_TRACEINTID_DISPATCH), - TRACE_STR(STM32_TRACEINTID_EP0IN), - TRACE_STR(STM32_TRACEINTID_EP0INDONE), - TRACE_STR(STM32_TRACEINTID_EP0OUTDONE), - TRACE_STR(STM32_TRACEINTID_EP0SETUPDONE), - TRACE_STR(STM32_TRACEINTID_EP0SETUPSETADDRESS), - TRACE_STR(STM32_TRACEINTID_EPGETSTATUS), - TRACE_STR(STM32_TRACEINTID_EPINDONE), - TRACE_STR(STM32_TRACEINTID_EPINQEMPTY), - TRACE_STR(STM32_TRACEINTID_EPOUTDONE), - TRACE_STR(STM32_TRACEINTID_EPOUTPENDING), - TRACE_STR(STM32_TRACEINTID_EPOUTQEMPTY), - TRACE_STR(STM32_TRACEINTID_ESOF), - TRACE_STR(STM32_TRACEINTID_GETCONFIG), - TRACE_STR(STM32_TRACEINTID_GETSETDESC), - TRACE_STR(STM32_TRACEINTID_GETSETIF), - TRACE_STR(STM32_TRACEINTID_GETSTATUS), - TRACE_STR(STM32_TRACEINTID_HPINTERRUPT), - TRACE_STR(STM32_TRACEINTID_IFGETSTATUS), - TRACE_STR(STM32_TRACEINTID_LPCTR), - TRACE_STR(STM32_TRACEINTID_LPINTERRUPT), - TRACE_STR(STM32_TRACEINTID_NOSTDREQ), - TRACE_STR(STM32_TRACEINTID_RESET), - TRACE_STR(STM32_TRACEINTID_SETCONFIG), - TRACE_STR(STM32_TRACEINTID_SETFEATURE), - TRACE_STR(STM32_TRACEINTID_SUSP), - TRACE_STR(STM32_TRACEINTID_SYNCHFRAME), - TRACE_STR(STM32_TRACEINTID_WKUP), - TRACE_STR(STM32_TRACEINTID_EP0SETUPOUT), - TRACE_STR(STM32_TRACEINTID_EP0SETUPOUTDATA), - TRACE_STR_END -}; -#endif - -#ifdef CONFIG_USBDEV_TRACE_STRINGS -const struct trace_msg_t g_usb_trace_strings_deverror[] = -{ - TRACE_STR(STM32_TRACEERR_ALLOCFAIL), - TRACE_STR(STM32_TRACEERR_BADCLEARFEATURE), - TRACE_STR(STM32_TRACEERR_BADDEVGETSTATUS), - TRACE_STR(STM32_TRACEERR_BADEPGETSTATUS), - TRACE_STR(STM32_TRACEERR_BADEPNO), - TRACE_STR(STM32_TRACEERR_BADEPTYPE), - TRACE_STR(STM32_TRACEERR_BADGETCONFIG), - TRACE_STR(STM32_TRACEERR_BADGETSETDESC), - TRACE_STR(STM32_TRACEERR_BADGETSTATUS), - TRACE_STR(STM32_TRACEERR_BADSETADDRESS), - TRACE_STR(STM32_TRACEERR_BADSETCONFIG), - TRACE_STR(STM32_TRACEERR_BADSETFEATURE), - TRACE_STR(STM32_TRACEERR_BINDFAILED), - TRACE_STR(STM32_TRACEERR_DISPATCHSTALL), - TRACE_STR(STM32_TRACEERR_DRIVER), - TRACE_STR(STM32_TRACEERR_DRIVERREGISTERED), - TRACE_STR(STM32_TRACEERR_EP0BADCTR), - TRACE_STR(STM32_TRACEERR_EP0SETUPSTALLED), - TRACE_STR(STM32_TRACEERR_EPBUFFER), - TRACE_STR(STM32_TRACEERR_EPDISABLED), - TRACE_STR(STM32_TRACEERR_EPOUTNULLPACKET), - TRACE_STR(STM32_TRACEERR_EPRESERVE), - TRACE_STR(STM32_TRACEERR_INVALIDCTRLREQ), - TRACE_STR(STM32_TRACEERR_INVALIDPARMS), - TRACE_STR(STM32_TRACEERR_IRQREGISTRATION), - TRACE_STR(STM32_TRACEERR_NOTCONFIGURED), - TRACE_STR(STM32_TRACEERR_REQABORTED), - TRACE_STR_END -}; -#endif - -/**************************************************************************** - * Private Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Register Operations - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_getreg - ****************************************************************************/ - -#ifdef CONFIG_STM32_USBFS_REGDEBUG -static uint16_t stm32_getreg(uint32_t addr) -{ - static uint32_t prevaddr = 0; - static uint16_t preval = 0; - static uint32_t count = 0; - - /* Read the value from the register */ - - uint16_t val = getreg16(addr); - - /* Is this the same value that we read from the same register last time? - * Are we polling the register? If so, suppress some of the output. - */ - - if (addr == prevaddr && val == preval) - { - if (count == 0xffffffff || ++count > 3) - { - if (count == 4) - { - uinfo("...\n"); - } - - return val; - } - } - - /* No this is a new address or value */ - - else - { - /* Did we print "..." for the previous value? */ - - if (count > 3) - { - /* Yes.. then show how many times the value repeated */ - - uinfo("[repeats %d more times]\n", count - 3); - } - - /* Save the new address, value, and count */ - - prevaddr = addr; - preval = val; - count = 1; - } - - /* Show the register value read */ - - uinfo("%08" PRIx32 "->%04" PRIx32 "\n", addr, val); - return val; -} -#endif - -/**************************************************************************** - * Name: stm32_putreg - ****************************************************************************/ - -#ifdef CONFIG_STM32_USBFS_REGDEBUG -static void stm32_putreg(uint16_t val, uint32_t addr) -{ - /* Show the register value being written */ - - uinfo("%08" PRIx32 "<-%04" PRIx32 "\n", addr, val); - - /* Write the value */ - - putreg16(val, addr); -} -#endif - -/**************************************************************************** - * Name: stm32_dumpep - ****************************************************************************/ - -#ifdef CONFIG_STM32_USBFS_REGDEBUG -static void stm32_dumpep(int epno) -{ - uint32_t addr; - - /* Common registers */ - - uinfo("CNTR: %04x\n", getreg16(STM32_USB_CNTR)); - uinfo("ISTR: %04x\n", getreg16(STM32_USB_ISTR)); - uinfo("FNR: %04x\n", getreg16(STM32_USB_FNR)); - uinfo("DADDR: %04x\n", getreg16(STM32_USB_DADDR)); - uinfo("BTABLE: %04x\n", getreg16(STM32_USB_BTABLE)); - - /* Endpoint register */ - - addr = STM32_USB_EPR(epno); - uinfo("EPR%d: [%08" PRIx32 "] %04x\n", epno, addr, getreg16(addr)); - - /* Endpoint descriptor */ - - addr = STM32_USB_BTABLE_ADDR(epno, 0); - uinfo("DESC: %08" PRIx32 "\n", addr); - - /* Endpoint buffer descriptor */ - - addr = STM32_USB_ADDR_TX(epno); - uinfo(" TX ADDR: [%08" PRIx32 "] %04x\n", addr, getreg16(addr)); - - addr = STM32_USB_COUNT_TX(epno); - uinfo(" COUNT: [%08" PRIx32 "] %04x\n", addr, getreg16(addr)); - - addr = STM32_USB_ADDR_RX(epno); - uinfo(" RX ADDR: [%08" PRIx32 "] %04x\n", addr, getreg16(addr)); - - addr = STM32_USB_COUNT_RX(epno); - uinfo(" COUNT: [%08" PRIx32 "] %04x\n", addr, getreg16(addr)); -} -#endif - -/**************************************************************************** - * Name: stm32_checksetup - ****************************************************************************/ - -#ifdef CONFIG_STM32_USBFS_REGDEBUG -static void stm32_checksetup(void) -{ - uint32_t cfgr = getreg32(STM32_RCC_CFGR); - uint32_t apb1rstr = getreg32(STM32_RCC_APB1RSTR1); - uint32_t apb1enr = getreg32(STM32_RCC_APB1ENR1); - - uinfo("CFGR: %08" PRIx32 " APB1RSTR: %08" PRIx32 - " APB1ENR: %08" PRIx32 "\n", - cfgr, apb1rstr, apb1enr); - - if ((apb1rstr & RCC_APB1RSTR1_USBRST) != 0 || - (apb1enr & RCC_APB1ENR1_USBEN) == 0) - { - uerr("ERROR: USB is NOT setup correctly\n"); - } -} -#endif - -/**************************************************************************** - * Low-Level Helpers - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_seteptxcount - ****************************************************************************/ - -static inline void stm32_seteptxcount(uint8_t epno, uint16_t count) -{ - volatile uint16_t *epaddr = (uint16_t *)STM32_USB_COUNT_TX(epno); - *epaddr = count; -} - -/**************************************************************************** - * Name: stm32_seteptxaddr - ****************************************************************************/ - -static inline void stm32_seteptxaddr(uint8_t epno, uint16_t addr) -{ - volatile uint16_t *txaddr = (uint16_t *)STM32_USB_ADDR_TX(epno); - *txaddr = addr; -} - -/**************************************************************************** - * Name: stm32_geteptxaddr - ****************************************************************************/ - -static inline uint16_t stm32_geteptxaddr(uint8_t epno) -{ - volatile uint16_t *txaddr = (uint16_t *)STM32_USB_ADDR_TX(epno); - return (uint16_t)*txaddr; -} - -/**************************************************************************** - * Name: stm32_seteprxcount - ****************************************************************************/ - -static void stm32_seteprxcount(uint8_t epno, uint16_t count) -{ - volatile uint16_t *epaddr = (uint16_t *)STM32_USB_COUNT_RX(epno); - uint32_t rxcount = 0; - uint16_t nblocks; - - /* The upper bits of the RX COUNT value contain the size of allocated - * RX buffer. This is based on a block size of 2 or 32: - * - * USB_COUNT_RX_BL_SIZE not set: - * nblocks is in units of 2 bytes. - * 00000 - not allowed - * 00001 - 2 bytes - * .... - * 11111 - 62 bytes - * - * USB_COUNT_RX_BL_SIZE set: - * 00000 - 32 bytes - * 00001 - 64 bytes - * ... - * 01111 - 512 bytes - * 1xxxx - Not allowed - */ - - if (count > 62) - { - /* Blocks of 32 (with 0 meaning one block of 32) */ - - nblocks = (count >> 5) - 1 ; - DEBUGASSERT(nblocks <= 0x0f); - rxcount = (uint32_t)((nblocks << - USB_COUNT_RX_NUM_BLOCK_SHIFT) | USB_COUNT_RX_BL_SIZE); - } - else if (count > 0) - { - /* Blocks of 2 (with 1 meaning one block of 2) */ - - nblocks = (count + 1) >> 1; - DEBUGASSERT(nblocks > 0 && nblocks < 0x1f); - rxcount = (uint32_t)(nblocks << USB_COUNT_RX_NUM_BLOCK_SHIFT); - } - - *epaddr = rxcount; -} - -/**************************************************************************** - * Name: stm32_geteprxcount - ****************************************************************************/ - -static inline uint16_t stm32_geteprxcount(uint8_t epno) -{ - volatile uint16_t *epaddr = (uint16_t *)STM32_USB_COUNT_RX(epno); - return (*epaddr) & USB_COUNT_RX_MASK; -} - -/**************************************************************************** - * Name: stm32_seteprxaddr - ****************************************************************************/ - -static inline void stm32_seteprxaddr(uint8_t epno, uint16_t addr) -{ - volatile uint16_t *rxaddr = (uint16_t *)STM32_USB_ADDR_RX(epno); - *rxaddr = addr; -} - -/**************************************************************************** - * Name: stm32_seteprxaddr - ****************************************************************************/ - -static inline uint16_t stm32_geteprxaddr(uint8_t epno) -{ - volatile uint16_t *rxaddr = (uint16_t *)STM32_USB_ADDR_RX(epno); - return (uint16_t)*rxaddr; -} - -/**************************************************************************** - * Name: stm32_setepaddress - ****************************************************************************/ - -static inline void stm32_setepaddress(uint8_t epno, uint16_t addr) -{ - uint32_t epaddr = STM32_USB_EPR(epno); - uint16_t regval; - - regval = stm32_getreg(epaddr); - regval &= EPR_NOTOG_MASK; - regval &= ~USB_EPR_EA_MASK; - regval |= (addr << USB_EPR_EA_SHIFT); - stm32_putreg(regval, epaddr); -} - -/**************************************************************************** - * Name: stm32_seteptype - ****************************************************************************/ - -static inline void stm32_seteptype(uint8_t epno, uint16_t type) -{ - uint32_t epaddr = STM32_USB_EPR(epno); - uint16_t regval; - - regval = stm32_getreg(epaddr); - regval &= EPR_NOTOG_MASK; - regval &= ~USB_EPR_EPTYPE_MASK; - regval |= type; - stm32_putreg(regval, epaddr); -} - -/**************************************************************************** - * Name: stm32_clrstatusout - ****************************************************************************/ - -static inline void stm32_clrstatusout(uint8_t epno) -{ - uint32_t epaddr = STM32_USB_EPR(epno); - uint16_t regval; - - /* For a BULK endpoint the EP_KIND bit is used to enabled double buffering; - * for a CONTROL endpoint, it is set to indicate that a status OUT - * transaction is expected. The bit is not used with out endpoint types. - */ - - regval = stm32_getreg(epaddr); - regval &= EPR_NOTOG_MASK; - regval &= ~USB_EPR_EP_KIND; - stm32_putreg(regval, epaddr); -} - -/**************************************************************************** - * Name: stm32_clrrxdtog - ****************************************************************************/ - -static void stm32_clrrxdtog(uint8_t epno) -{ - uint32_t epaddr = STM32_USB_EPR(epno); - uint16_t regval; - - regval = stm32_getreg(epaddr); - if ((regval & USB_EPR_DTOG_RX) != 0) - { - regval &= EPR_NOTOG_MASK; - regval |= USB_EPR_DTOG_RX; - stm32_putreg(regval, epaddr); - } -} - -/**************************************************************************** - * Name: stm32_clrtxdtog - ****************************************************************************/ - -static void stm32_clrtxdtog(uint8_t epno) -{ - uint32_t epaddr = STM32_USB_EPR(epno); - uint16_t regval; - - regval = stm32_getreg(epaddr); - if ((regval & USB_EPR_DTOG_TX) != 0) - { - regval &= EPR_NOTOG_MASK; - regval |= USB_EPR_DTOG_TX; - stm32_putreg(regval, epaddr); - } -} - -/**************************************************************************** - * Name: stm32_clrepctrrx - ****************************************************************************/ - -static void stm32_clrepctrrx(uint8_t epno) -{ - uint32_t epaddr = STM32_USB_EPR(epno); - uint16_t regval; - - regval = stm32_getreg(epaddr); - regval &= EPR_NOTOG_MASK; - regval &= ~USB_EPR_CTR_RX; - stm32_putreg(regval, epaddr); -} - -/**************************************************************************** - * Name: stm32_clrepctrtx - ****************************************************************************/ - -static void stm32_clrepctrtx(uint8_t epno) -{ - uint32_t epaddr = STM32_USB_EPR(epno); - uint16_t regval; - - regval = stm32_getreg(epaddr); - regval &= EPR_NOTOG_MASK; - regval &= ~USB_EPR_CTR_TX; - stm32_putreg(regval, epaddr); -} - -/**************************************************************************** - * Name: stm32_geteptxstatus - ****************************************************************************/ - -static inline uint16_t stm32_geteptxstatus(uint8_t epno) -{ - return (uint16_t)(stm32_getreg(STM32_USB_EPR(epno)) & - USB_EPR_STATTX_MASK); -} - -/**************************************************************************** - * Name: stm32_geteprxstatus - ****************************************************************************/ - -static inline uint16_t stm32_geteprxstatus(uint8_t epno) -{ - return (stm32_getreg(STM32_USB_EPR(epno)) & USB_EPR_STATRX_MASK); -} - -/**************************************************************************** - * Name: stm32_seteptxstatus - ****************************************************************************/ - -static void stm32_seteptxstatus(uint8_t epno, uint16_t state) -{ - uint32_t epaddr = STM32_USB_EPR(epno); - uint16_t regval; - - /* The bits in the STAT_TX field can be toggled by software to set their - * value. When set to 0, the value remains unchanged; when set to one, - * value toggles. - */ - - regval = stm32_getreg(epaddr); - - /* The exclusive OR will set STAT_TX bits to 1 if there value is different - * from the bits requested in 'state' - */ - - regval ^= state; - regval &= EPR_TXDTOG_MASK; - stm32_putreg(regval, epaddr); -} - -/**************************************************************************** - * Name: stm32_seteprxstatus - ****************************************************************************/ - -static void stm32_seteprxstatus(uint8_t epno, uint16_t state) -{ - uint32_t epaddr = STM32_USB_EPR(epno); - uint16_t regval; - - /* The bits in the STAT_RX field can be toggled by software to set their - * value. When set to 0, the value remains unchanged; when set to one, - * value toggles. - */ - - regval = stm32_getreg(epaddr); - - /* The exclusive OR will set STAT_RX bits to 1 if there value is different - * from the bits requested in 'state' - */ - - regval ^= state; - regval &= EPR_RXDTOG_MASK; - stm32_putreg(regval, epaddr); -} - -/**************************************************************************** - * Name: stm32_eptxstalled - ****************************************************************************/ - -static inline bool stm32_eptxstalled(uint8_t epno) -{ - return (stm32_geteptxstatus(epno) == USB_EPR_STATTX_STALL); -} - -/**************************************************************************** - * Name: stm32_eprxstalled - ****************************************************************************/ - -static inline bool stm32_eprxstalled(uint8_t epno) -{ - return (stm32_geteprxstatus(epno) == USB_EPR_STATRX_STALL); -} - -/**************************************************************************** - * Request Helpers - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_copytopma - ****************************************************************************/ - -static void stm32_copytopma(const uint8_t *buffer, - uint16_t pma, uint16_t nbytes) -{ - uint16_t *dest; - uint16_t ms; - uint16_t ls; - int nwords = (nbytes + 1) >> 1; - int i; - - /* Copy loop. Source=user buffer, Dest=packet memory */ - - dest = (uint16_t *)(STM32_USBRAM_BASE + (uint32_t)pma); - for (i = nwords; i != 0; i--) - { - /* Read two bytes and pack into on 16-bit word */ - - ls = (uint16_t)(*buffer++); - ms = (uint16_t)(*buffer++); - *dest++ = ms << 8 | ls; - } -} - -/**************************************************************************** - * Name: stm32_copyfrompma - ****************************************************************************/ - -static inline void -stm32_copyfrompma(uint8_t *buffer, uint16_t pma, uint16_t nbytes) -{ - uint16_t *src; - int nwords = (nbytes + 1) >> 1; - int i; - - /* Copy loop. Source=packet memory, Dest=user buffer */ - - src = (uint16_t *)(STM32_USBRAM_BASE + (uint32_t)pma); - for (i = nwords; i != 0; i--) - { - /* Copy 16-bits from packet memory to user buffer. */ - - *(uint16_t *)buffer = *src++; - - /* Source address increments by 1*sizeof(uint16_t) = 2; Dest address - * increments by 2*sizeof(uint8_t) = 2. - */ - - buffer += 2; - } -} - -/**************************************************************************** - * Name: stm32_rqdequeue - ****************************************************************************/ - -static struct stm32_req_s *stm32_rqdequeue(struct stm32_ep_s *privep) -{ - struct stm32_req_s *ret = privep->head; - - if (ret) - { - privep->head = ret->flink; - if (!privep->head) - { - privep->tail = NULL; - } - - ret->flink = NULL; - } - - return ret; -} - -/**************************************************************************** - * Name: stm32_rqenqueue - ****************************************************************************/ - -static void stm32_rqenqueue(struct stm32_ep_s *privep, - struct stm32_req_s *req) -{ - req->flink = NULL; - if (!privep->head) - { - privep->head = req; - privep->tail = req; - } - else - { - privep->tail->flink = req; - privep->tail = req; - } -} - -/**************************************************************************** - * Name: stm32_abortrequest - ****************************************************************************/ - -static inline void -stm32_abortrequest(struct stm32_ep_s *privep, - struct stm32_req_s *privreq, int16_t result) -{ - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_REQABORTED), - (uint16_t)USB_EPNO(privep->ep.eplog)); - - /* Save the result in the request structure */ - - privreq->req.result = result; - - /* Callback to the request completion handler */ - - privreq->req.callback(&privep->ep, &privreq->req); -} - -/**************************************************************************** - * Name: stm32_reqcomplete - ****************************************************************************/ - -static void stm32_reqcomplete(struct stm32_ep_s *privep, int16_t result) -{ - struct stm32_req_s *privreq; - irqstate_t flags; - - /* Remove the completed request at the head of the endpoint request list */ - - flags = enter_critical_section(); - privreq = stm32_rqdequeue(privep); - leave_critical_section(flags); - - if (privreq) - { - /* If endpoint 0, temporarily reflect the state of protocol stalled - * in the callback. - */ - - bool stalled = privep->stalled; - if (USB_EPNO(privep->ep.eplog) == EP0) - { - privep->stalled = (privep->dev->ep0state == EP0STATE_STALLED); - } - - /* Save the result in the request structure */ - - privreq->req.result = result; - - /* Callback to the request completion handler */ - - privreq->flink = NULL; - privreq->req.callback(&privep->ep, &privreq->req); - - /* Restore the stalled indication */ - - privep->stalled = stalled; - } -} - -/**************************************************************************** - * Name: tm32_epwrite - ****************************************************************************/ - -static void stm32_epwrite(struct stm32_usbdev_s *priv, - struct stm32_ep_s *privep, - const uint8_t *buf, uint32_t nbytes) -{ - uint8_t epno = USB_EPNO(privep->ep.eplog); - usbtrace(TRACE_WRITE(epno), nbytes); - - /* Check for a zero-length packet */ - - if (nbytes > 0) - { - /* Copy the data from the user buffer into packet memory for this - * endpoint - */ - - stm32_copytopma(buf, stm32_geteptxaddr(epno), nbytes); - } - - /* Send the packet (might be a null packet nbytes == 0) */ - - stm32_seteptxcount(epno, nbytes); - priv->txstatus = USB_EPR_STATTX_VALID; - - /* Indicate that there is data in the TX packet memory. This will be - * cleared when the next data out interrupt is received. - */ - - privep->txbusy = true; -} - -/**************************************************************************** - * Name: stm32_wrrequest_ep0 - * - * Description: - * Handle the ep0 state on writes. - * - ****************************************************************************/ - -inline static int stm32_wrrequest_ep0(struct stm32_usbdev_s *priv, - struct stm32_ep_s *privep) -{ - int ret; - ret = stm32_wrrequest(priv, privep); - priv->ep0state = ((ret == OK) ? EP0STATE_WRREQUEST : EP0STATE_IDLE); - return ret; -} - -/**************************************************************************** - * Name: stm32_wrrequest - ****************************************************************************/ - -static int stm32_wrrequest(struct stm32_usbdev_s *priv, - struct stm32_ep_s *privep) -{ - struct stm32_req_s *privreq; - uint8_t *buf; - uint8_t epno; - int nbytes; - int bytesleft; - - /* We get here when an IN endpoint interrupt occurs. So now we know that - * there is no TX transfer in progress. - */ - - privep->txbusy = false; - - /* Check the request from the head of the endpoint request queue */ - - privreq = stm32_rqpeek(privep); - if (!privreq) - { - /* There is no TX transfer in progress and no new pending TX - * requests to send. - */ - - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPINQEMPTY), 0); - return -ENOENT; - } - - epno = USB_EPNO(privep->ep.eplog); - uinfo("epno=%d req=%p: len=%zu xfrd=%zu nullpkt=%d\n", - epno, privreq, privreq->req.len, - privreq->req.xfrd, privep->txnullpkt); - UNUSED(epno); - - /* Get the number of bytes left to be sent in the packet */ - - bytesleft = privreq->req.len - privreq->req.xfrd; - nbytes = bytesleft; - -#warning "REVISIT: If the EP supports double buffering, then we can do better" - - /* Either (1) we are committed to sending the null packet - * (because txnullpkt == 1 && nbytes == 0), or (2) we have not yet send - * the last packet (nbytes > 0). - * In either case, it is appropriate to clearn txnullpkt now. - */ - - privep->txnullpkt = 0; - - /* If we are not sending a NULL packet, then clip the size to maxpacket - * and check if we need to send a following NULL packet. - */ - - if (nbytes > 0) - { - /* Either send the maxpacketsize or all of the remaining data in - * the request. - */ - - if (nbytes >= privep->ep.maxpacket) - { - nbytes = privep->ep.maxpacket; - - /* Handle the case where this packet is exactly the - * maxpacketsize. Do we need to send a zero-length packet - * in this case? - */ - - if (bytesleft == privep->ep.maxpacket && - (privreq->req.flags & USBDEV_REQFLAGS_NULLPKT) != 0) - { - privep->txnullpkt = 1; - } - } - } - - /* Send the packet (might be a null packet nbytes == 0) */ - - buf = privreq->req.buf + privreq->req.xfrd; - stm32_epwrite(priv, privep, buf, nbytes); - - /* Update for the next data IN interrupt */ - - privreq->req.xfrd += nbytes; - bytesleft = privreq->req.len - privreq->req.xfrd; - - /* If all of the bytes were sent (including any final null packet) - * then we are finished with the request buffer). - */ - - if (bytesleft == 0 && !privep->txnullpkt) - { - /* Return the write request to the class driver */ - - usbtrace(TRACE_COMPLETE(USB_EPNO(privep->ep.eplog)), - privreq->req.xfrd); - privep->txnullpkt = 0; - stm32_reqcomplete(privep, OK); - } - - return OK; -} - -/**************************************************************************** - * Name: stm32_ep0_rdrequest - * - * Description: - * This function is called from the stm32_ep0out handler when the ep0state - * is EP0STATE_SETUP_OUT and upon new incoming data is available in the - * endpoint 0's buffer. - * This function will simply copy the OUT data into ep0data. - * - ****************************************************************************/ - -static inline int stm32_ep0_rdrequest(struct stm32_usbdev_s *priv) -{ - uint32_t src; - int pmalen; - int readlen; - - /* Get the number of bytes to read from packet memory */ - - pmalen = stm32_geteprxcount(EP0); - - uinfo("EP0: pmalen=%d\n", pmalen); - usbtrace(TRACE_READ(EP0), pmalen); - - /* Read the data into our special buffer for SETUP data */ - - readlen = MIN(CONFIG_USBDEV_SETUP_MAXDATASIZE, pmalen); - src = stm32_geteprxaddr(EP0); - - /* Receive the next packet */ - - stm32_copyfrompma(&priv->ep0data[0], src, readlen); - - /* Now we can process the setup command */ - - priv->ep0state = EP0STATE_SETUP_READY; - priv->ep0datlen = readlen; - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EP0SETUPOUTDATA), - readlen); - - stm32_ep0setup(priv); - priv->ep0datlen = 0; /* mark the date consumed */ - - return OK; -} - -/**************************************************************************** - * Name: stm32_rdrequest - ****************************************************************************/ - -static int stm32_rdrequest(struct stm32_usbdev_s *priv, - struct stm32_ep_s *privep) -{ - struct stm32_req_s *privreq; - uint32_t src; - uint8_t *dest; - uint8_t epno; - int pmalen; - int readlen; - - /* Check the request from the head of the endpoint request queue */ - - epno = USB_EPNO(privep->ep.eplog); - privreq = stm32_rqpeek(privep); - if (!privreq) - { - /* Incoming data available in PMA, but no packet to receive the data. - * Mark that the RX data is pending and hope that a packet is returned - * soon. - */ - - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPOUTQEMPTY), epno); - return -ENOENT; - } - - uinfo("EP%d: len=%zu xfrd=%zu\n", - epno, privreq->req.len, privreq->req.xfrd); - - /* Ignore any attempt to receive a zero length packet */ - - if (privreq->req.len == 0) - { - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EPOUTNULLPACKET), 0); - stm32_reqcomplete(privep, OK); - return OK; - } - - usbtrace(TRACE_READ(USB_EPNO(privep->ep.eplog)), privreq->req.xfrd); - - /* Get the source and destination transfer addresses */ - - dest = privreq->req.buf + privreq->req.xfrd; - src = stm32_geteprxaddr(epno); - - /* Get the number of bytes to read from packet memory */ - - pmalen = stm32_geteprxcount(epno); - readlen = MIN(privreq->req.len, pmalen); - - /* Receive the next packet */ - - stm32_copyfrompma(dest, src, readlen); - - /* If the receive buffer is full or this is a partial packet, - * then we are finished with the request buffer). - */ - - privreq->req.xfrd += readlen; - if (pmalen < privep->ep.maxpacket || privreq->req.xfrd >= privreq->req.len) - { - /* Return the read request to the class driver. */ - - usbtrace(TRACE_COMPLETE(epno), privreq->req.xfrd); - stm32_reqcomplete(privep, OK); - } - - return OK; -} - -/**************************************************************************** - * Name: stm32_cancelrequests - ****************************************************************************/ - -static void stm32_cancelrequests(struct stm32_ep_s *privep) -{ - while (!stm32_rqempty(privep)) - { - usbtrace(TRACE_COMPLETE(USB_EPNO(privep->ep.eplog)), - (stm32_rqpeek(privep))->req.xfrd); - stm32_reqcomplete(privep, -ESHUTDOWN); - } -} - -/**************************************************************************** - * Interrupt Level Processing - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_dispatchrequest - ****************************************************************************/ - -static void stm32_dispatchrequest(struct stm32_usbdev_s *priv) -{ - int ret; - - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_DISPATCH), 0); - if (priv && priv->driver) - { - /* Forward to the control request to the class driver implementation */ - - ret = CLASS_SETUP(priv->driver, &priv->usbdev, &priv->ctrl, - priv->ep0data, priv->ep0datlen); - if (ret < 0) - { - /* Stall on failure */ - - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_DISPATCHSTALL), 0); - priv->ep0state = EP0STATE_STALLED; - } - } -} - -/**************************************************************************** - * Name: stm32_epdone - ****************************************************************************/ - -static void stm32_epdone(struct stm32_usbdev_s *priv, uint8_t epno) -{ - struct stm32_ep_s *privep; - uint16_t epr; - - /* Decode and service non control endpoints interrupt */ - - epr = stm32_getreg(STM32_USB_EPR(epno)); - privep = &priv->eplist[epno]; - - /* OUT: host-to-device - * CTR_RX is set by the hardware when an OUT/SETUP transaction - * successfully completed on this endpoint. - */ - - if ((epr & USB_EPR_CTR_RX) != 0) - { - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPOUTDONE), epr); - - /* Handle read requests. First check if a read request is available to - * accept the host data. - */ - - if (!stm32_rqempty(privep)) - { - /* Read host data into the current read request */ - - stm32_rdrequest(priv, privep); - - /* "After the received data is processed, the application software - * should set the STAT_RX bits to '11' (Valid) in the USB_EPnR, - * enabling further transactions. " - */ - - priv->rxstatus = USB_EPR_STATRX_VALID; - } - - /* NAK further OUT packets if there there no more read requests */ - - if (stm32_rqempty(privep)) - { - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPOUTPENDING), - (uint16_t)epno); - - /* Mark the RX processing as pending and NAK any OUT actions - * on this endpoint. "While the STAT_RX bits are equal to '10' - * (NAK), any OUT request addressed to that endpoint is NAKed, - * indicating a flow control condition: the USB host will retry - * the transaction until it succeeds." - */ - - priv->rxstatus = USB_EPR_STATRX_NAK; - priv->rxpending = true; - } - - /* Clear the interrupt status and set the new RX status */ - - stm32_clrepctrrx(epno); - stm32_seteprxstatus(epno, priv->rxstatus); - } - - /* IN: device-to-host - * CTR_TX is set when an IN transaction successfully completes on - * an endpoint - */ - - else if ((epr & USB_EPR_CTR_TX) != 0) - { - /* Clear interrupt status */ - - stm32_clrepctrtx(epno); - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPINDONE), epr); - - /* Handle write requests */ - - priv->txstatus = USB_EPR_STATTX_NAK; - if (epno == EP0) - { - stm32_wrrequest_ep0(priv, privep); - } - else - { - stm32_wrrequest(priv, privep); - } - - /* Set the new TX status */ - - stm32_seteptxstatus(epno, priv->txstatus); - } -} - -/**************************************************************************** - * Name: stm32_setdevaddr - ****************************************************************************/ - -static void stm32_setdevaddr(struct stm32_usbdev_s *priv, uint8_t value) -{ - int epno; - - /* Set address in every allocated endpoint */ - - for (epno = 0; epno < STM32_NENDPOINTS; epno++) - { - if (stm32_epreserved(priv, epno)) - { - stm32_setepaddress((uint8_t)epno, (uint8_t)epno); - } - } - - /* Set the device address and enable function */ - - stm32_putreg(value | USB_DADDR_EF, STM32_USB_DADDR); -} - -/**************************************************************************** - * Name: stm32_ep0setup - ****************************************************************************/ - -static void stm32_ep0setup(struct stm32_usbdev_s *priv) -{ - struct stm32_ep_s *ep0 = &priv->eplist[EP0]; - struct stm32_req_s *privreq = stm32_rqpeek(ep0); - struct stm32_ep_s *privep; - union wb_u value; - union wb_u index; - union wb_u len; - union wb_u response; - bool handled = false; - uint8_t epno; - int nbytes = 0; /* Assume zero-length packet */ - - /* Terminate any pending requests (doesn't work if the pending request - * was a zero-length transfer!) - */ - - while (!stm32_rqempty(ep0)) - { - int16_t result = OK; - if (privreq->req.xfrd != privreq->req.len) - { - result = -EPROTO; - } - - usbtrace(TRACE_COMPLETE(ep0->ep.eplog), privreq->req.xfrd); - stm32_reqcomplete(ep0, result); - } - - /* Assume NOT stalled; no TX in progress */ - - ep0->stalled = 0; - ep0->txbusy = 0; - - value.w = 0; - index.w = 0; - len.w = 0; - response.w = 0; - - /* Check to see if called from the DATA phase of a SETUP Transfer */ - - if (priv->ep0state != EP0STATE_SETUP_READY) - { - /* Not the data phase */ - - /* Get a 32-bit PMA address and use that to get the 8-byte setup - * request - */ - - stm32_copyfrompma((uint8_t *)&priv->ctrl, stm32_geteprxaddr(EP0), - USB_SIZEOF_CTRLREQ); - - /* And extract the little-endian 16-bit values to host order */ - - value.w = GETUINT16(priv->ctrl.value); - index.w = GETUINT16(priv->ctrl.index); - len.w = GETUINT16(priv->ctrl.len); - - uinfo("SETUP: type=%02x req=%02x value=%04x index=%04x len=%04x\n", - priv->ctrl.type, priv->ctrl.req, value.w, index.w, len.w); - - /* Is this an setup with OUT and data of length > 0 */ - - if (USB_REQ_ISOUT(priv->ctrl.type) && len.w > 0) - { - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EP0SETUPOUT), len.w); - - /* At this point priv->ctrl is the setup packet. */ - - priv->ep0state = EP0STATE_SETUP_OUT; - return; - } - else - { - priv->ep0state = EP0STATE_SETUP_READY; - } - } - - /* Dispatch any non-standard requests */ - - if ((priv->ctrl.type & USB_REQ_TYPE_MASK) != USB_REQ_TYPE_STANDARD) - { - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_NOSTDREQ), priv->ctrl.type); - - /* Let the class implementation handle all non-standar requests */ - - stm32_dispatchrequest(priv); - return; - } - - /* Handle standard request. Pick off the things of interest to the - * USB device controller driver; pass what is left to the class driver - */ - - switch (priv->ctrl.req) - { - case USB_REQ_GETSTATUS: - { - /* type: device-to-host; recipient = device, interface, endpoint - * value: 0 - * index: zero interface endpoint - * len: 2; data = status - */ - - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_GETSTATUS), - priv->ctrl.type); - if (len.w != 2 || (priv->ctrl.type & - USB_REQ_DIR_IN) == 0 || - index.b[MSB] != 0 || value.w != 0) - { - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADEPGETSTATUS), 0); - priv->ep0state = EP0STATE_STALLED; - } - else - { - switch (priv->ctrl.type & USB_REQ_RECIPIENT_MASK) - { - case USB_REQ_RECIPIENT_ENDPOINT: - { - epno = USB_EPNO(index.b[LSB]); - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPGETSTATUS), - epno); - if (epno >= STM32_NENDPOINTS) - { - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADEPGETSTATUS), - epno); - priv->ep0state = EP0STATE_STALLED; - } - else - { - response.w = 0; /* Not stalled */ - nbytes = 2; /* Response size: 2 bytes */ - - if (USB_ISEPIN(index.b[LSB])) - { - /* IN endpoint */ - - if (stm32_eptxstalled(epno)) - { - /* IN Endpoint stalled */ - - response.b[LSB] = 1; /* Stalled */ - } - } - else - { - /* OUT endpoint */ - - if (stm32_eprxstalled(epno)) - { - /* OUT Endpoint stalled */ - - response.b[LSB] = 1; /* Stalled */ - } - } - } - } - break; - - case USB_REQ_RECIPIENT_DEVICE: - { - if (index.w == 0) - { - usbtrace(TRACE_INTDECODE( - STM32_TRACEINTID_DEVGETSTATUS), 0); - - /* Features: Remote Wakeup=YES; selfpowered=? */ - - response.w = 0; - response.b[LSB] = (priv->selfpowered << - USB_FEATURE_SELFPOWERED) | - (1 << USB_FEATURE_REMOTEWAKEUP); - nbytes = 2; /* Response size: 2 bytes */ - } - else - { - usbtrace(TRACE_DEVERROR( - STM32_TRACEERR_BADDEVGETSTATUS), 0); - priv->ep0state = EP0STATE_STALLED; - } - } - break; - - case USB_REQ_RECIPIENT_INTERFACE: - { - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_IFGETSTATUS), 0); - response.w = 0; - nbytes = 2; /* Response size: 2 bytes */ - } - break; - - default: - { - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADGETSTATUS), 0); - priv->ep0state = EP0STATE_STALLED; - } - break; - } - } - } - break; - - case USB_REQ_CLEARFEATURE: - { - /* type: host-to-device; recipient = device, interface or endpoint - * value: feature selector - * index: zero interface endpoint; - * len: zero, data = none - */ - - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_CLEARFEATURE), - priv->ctrl.type); - if ((priv->ctrl.type & USB_REQ_RECIPIENT_MASK) != - USB_REQ_RECIPIENT_ENDPOINT) - { - /* Let the class implementation handle all recipients - * (except for the endpoint recipient) - */ - - stm32_dispatchrequest(priv); - handled = true; - } - else - { - /* Endpoint recipient */ - - epno = USB_EPNO(index.b[LSB]); - if (epno < STM32_NENDPOINTS && index.b[MSB] == 0 && - value.w == USB_FEATURE_ENDPOINTHALT && len.w == 0) - { - privep = &priv->eplist[epno]; - privep->halted = 0; - stm32_epstall(&privep->ep, true); - } - else - { - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADCLEARFEATURE), 0); - priv->ep0state = EP0STATE_STALLED; - } - } - } - break; - - case USB_REQ_SETFEATURE: - { - /* type: host-to-device; recipient = device, interface, endpoint - * value: feature selector - * index: zero interface endpoint; - * len: 0; data = none - */ - - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SETFEATURE), - priv->ctrl.type); - if (((priv->ctrl.type & USB_REQ_RECIPIENT_MASK) == - USB_REQ_RECIPIENT_DEVICE) && - value.w == USB_FEATURE_TESTMODE) - { - /* Special case recipient=device test mode */ - - uinfo("test mode: %d\n", index.w); - } - else if ((priv->ctrl.type & USB_REQ_RECIPIENT_MASK) != - USB_REQ_RECIPIENT_ENDPOINT) - { - /* The class driver handles all recipients except - * recipient=endpoint - */ - - stm32_dispatchrequest(priv); - handled = true; - } - else - { - /* Handler recipient=endpoint */ - - epno = USB_EPNO(index.b[LSB]); - if (epno < STM32_NENDPOINTS && index.b[MSB] == 0 && - value.w == USB_FEATURE_ENDPOINTHALT && len.w == 0) - { - privep = &priv->eplist[epno]; - privep->halted = 1; - stm32_epstall(&privep->ep, false); - } - else - { - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADSETFEATURE), 0); - priv->ep0state = EP0STATE_STALLED; - } - } - } - break; - - case USB_REQ_SETADDRESS: - { - /* type: host-to-device; recipient = device - * value: device address - * index: 0 - * len: 0; data = none - */ - - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EP0SETUPSETADDRESS), - value.w); - if ((priv->ctrl.type & USB_REQ_RECIPIENT_MASK) != - USB_REQ_RECIPIENT_DEVICE || - index.w != 0 || len.w != 0 || value.w > 127) - { - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADSETADDRESS), 0); - priv->ep0state = EP0STATE_STALLED; - } - /* Note that setting of the device address will be deferred. - * A zero-length packet will be sent and the device address - * will be set when the zero- length packet transfer completes. - */ - } - break; - - case USB_REQ_GETDESCRIPTOR: - /* type: device-to-host; recipient = device - * value: descriptor type and index - * index: 0 or language ID; - * len: descriptor len; data = descriptor - */ - - case USB_REQ_SETDESCRIPTOR: - /* type: host-to-device; recipient = device - * value: descriptor type and index - * index: 0 or language ID; - * len: descriptor len; data = descriptor - */ - - { - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_GETSETDESC), - priv->ctrl.type); - - /* The request seems valid... - * let the class implementation handle it - */ - - stm32_dispatchrequest(priv); - handled = true; - } - break; - - case USB_REQ_GETCONFIGURATION: - /* type: device-to-host; recipient = device - * value: 0; - * index: 0; - * len: 1; data = configuration value - */ - - { - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_GETCONFIG), - priv->ctrl.type); - if ((priv->ctrl.type & USB_REQ_RECIPIENT_MASK) == - USB_REQ_RECIPIENT_DEVICE && - value.w == 0 && index.w == 0 && len.w == 1) - { - /* The request seems valid... - * let the class implementation handle it - */ - - stm32_dispatchrequest(priv); - handled = true; - } - else - { - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADGETCONFIG), 0); - priv->ep0state = EP0STATE_STALLED; - } - } - break; - - case USB_REQ_SETCONFIGURATION: - /* type: host-to-device; recipient = device - * value: configuration value - * index: 0; - * len: 0; data = none - */ - - { - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SETCONFIG), - priv->ctrl.type); - if ((priv->ctrl.type & USB_REQ_RECIPIENT_MASK) == - USB_REQ_RECIPIENT_DEVICE && - index.w == 0 && len.w == 0) - { - /* The request seems valid... - * let the class implementation handle it - */ - - stm32_dispatchrequest(priv); - handled = true; - } - else - { - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADSETCONFIG), 0); - priv->ep0state = EP0STATE_STALLED; - } - } - break; - - case USB_REQ_GETINTERFACE: - /* type: device-to-host; recipient = interface - * value: 0 - * index: interface; - * len: 1; data = alt interface - */ - - case USB_REQ_SETINTERFACE: - /* type: host-to-device; recipient = interface - * value: alternate setting - * index: interface; - * len: 0; data = none - */ - - { - /* Let the class implementation handle the request */ - - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_GETSETIF), - priv->ctrl.type); - stm32_dispatchrequest(priv); - handled = true; - } - break; - - case USB_REQ_SYNCHFRAME: - /* type: device-to-host; recipient = endpoint - * value: 0 - * index: endpoint; - * len: 2; data = frame number - */ - - { - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SYNCHFRAME), 0); - } - break; - - default: - { - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDCTRLREQ), - priv->ctrl.req); - priv->ep0state = EP0STATE_STALLED; - } - break; - } - - /* At this point, the request has been handled and there are three possible - * outcomes: - * - * 1. The setup request was successfully handled above and a response - * packet must be sent (may be a zero length packet). - * 2. The request was successfully handled by the class implementation. - * In case, the EP0 IN response has already been queued and the local - * variable 'handled' will be set to true and - * ep0state != EP0STATE_STALLED; - * 3. An error was detected in either the above logic or by the class - * implementation logic. In either case, priv->state will be set - * EP0STATE_STALLED to indicate this case. - * - * NOTE: - * Non-standard requests are a special case. They are handled by the - * class implementation and this function returned early above, skipping - * this logic altogether. - */ - - if (priv->ep0state != EP0STATE_STALLED && !handled) - { - /* We will response. First, restrict the data length to the length - * requested in the setup packet - */ - - if (nbytes > len.w) - { - nbytes = len.w; - } - - /* Send the response (might be a zero-length packet) */ - - stm32_epwrite(priv, ep0, response.b, nbytes); - priv->ep0state = EP0STATE_IDLE; - } -} - -/**************************************************************************** - * Name: stm32_ep0in - ****************************************************************************/ - -static void stm32_ep0in(struct stm32_usbdev_s *priv) -{ - /* There is no longer anything in the EP0 TX packet memory */ - - priv->eplist[EP0].txbusy = false; - - /* Are we processing the completion of one packet of an outgoing request - * from the class driver? - */ - - if (priv->ep0state == EP0STATE_WRREQUEST) - { - stm32_wrrequest_ep0(priv, &priv->eplist[EP0]); - } - - /* No.. Are we processing the completion of a status response? */ - - else if (priv->ep0state == EP0STATE_IDLE) - { - /* Look at the saved SETUP command. Was it a SET ADDRESS request? - * If so, then now is the time to set the address. - */ - - if (priv->ctrl.req == USB_REQ_SETADDRESS && - (priv->ctrl.type & REQRECIPIENT_MASK) == - (USB_REQ_TYPE_STANDARD | USB_REQ_RECIPIENT_DEVICE)) - { - union wb_u value; - value.w = GETUINT16(priv->ctrl.value); - stm32_setdevaddr(priv, value.b[LSB]); - } - } - else - { - priv->ep0state = EP0STATE_STALLED; - } -} - -/**************************************************************************** - * Name: stm32_ep0out - ****************************************************************************/ - -static void stm32_ep0out(struct stm32_usbdev_s *priv) -{ - int ret; - - struct stm32_ep_s *privep = &priv->eplist[EP0]; - switch (priv->ep0state) - { - case EP0STATE_RDREQUEST: /* Read request in progress */ - case EP0STATE_IDLE: /* No transfer in progress */ - ret = stm32_rdrequest(priv, privep); - priv->ep0state = ((ret == OK) ? EP0STATE_RDREQUEST : EP0STATE_IDLE); - break; - - case EP0STATE_SETUP_OUT: /* SETUP was waiting for data */ - ret = stm32_ep0_rdrequest(priv); /* Off load the data and run the - * last set up command with the OUT - * data - */ - priv->ep0state = EP0STATE_IDLE; /* There is no notion of receiving OUT - * data greater then the length of - * CONFIG_USBDEV_SETUP_MAXDATASIZE - * so we are done - */ - break; - - default: - /* Unexpected state OR host aborted the OUT transfer before it - * completed, STALL the endpoint in either case - */ - - priv->ep0state = EP0STATE_STALLED; - break; - } -} - -/**************************************************************************** - * Name: stm32_ep0done - ****************************************************************************/ - -static inline void stm32_ep0done(struct stm32_usbdev_s *priv, uint16_t istr) -{ - uint16_t epr; - - /* Initialize RX and TX status. We shouldn't have to actually look at the - * status because the hardware is supposed to set the both RX and TX status - * to NAK when an EP0 SETUP occurs (of course, this might not be a setup) - */ - - priv->rxstatus = USB_EPR_STATRX_NAK; - priv->txstatus = USB_EPR_STATTX_NAK; - - /* Set both RX and TX status to NAK */ - - stm32_seteprxstatus(EP0, USB_EPR_STATRX_NAK); - stm32_seteptxstatus(EP0, USB_EPR_STATTX_NAK); - - /* Check the direction bit to determine if this the completion of an EP0 - * packet sent to or received from the host PC. - */ - - if ((istr & USB_ISTR_DIR) == 0) - { - /* EP0 IN: device-to-host (DIR=0) */ - - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EP0IN), istr); - stm32_clrepctrtx(EP0); - stm32_ep0in(priv); - } - else - { - /* EP0 OUT: host-to-device (DIR=1) */ - - epr = stm32_getreg(STM32_USB_EPR(EP0)); - - /* CTR_TX is set when an IN transaction successfully - * completes on an endpoint - */ - - if ((epr & USB_EPR_CTR_TX) != 0) - { - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EP0INDONE), epr); - stm32_clrepctrtx(EP0); - stm32_ep0in(priv); - } - - /* SETUP is set by the hardware when the last completed - * transaction was a control endpoint SETUP - */ - - else if ((epr & USB_EPR_SETUP) != 0) - { - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EP0SETUPDONE), epr); - stm32_clrepctrrx(EP0); - stm32_ep0setup(priv); - } - - /* Set by the hardware when an OUT/SETUP transaction successfully - * completed on this endpoint. - */ - - else if ((epr & USB_EPR_CTR_RX) != 0) - { - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EP0OUTDONE), epr); - stm32_clrepctrrx(EP0); - stm32_ep0out(priv); - } - - /* None of the above */ - - else - { - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EP0BADCTR), epr); - return; /* Does this ever happen? */ - } - } - - /* Make sure that the EP0 packet size is still OK (superstitious?) */ - - stm32_seteprxcount(EP0, STM32_EP0MAXPACKET); - - /* Now figure out the new RX/TX status. Here are all possible - * consequences of the above EP0 operations: - * - * rxstatus txstatus ep0state MEANING - * -------- -------- --------- --------------------------------- - * NAK NAK IDLE Nothing happened - * NAK VALID IDLE EP0 response sent from USBDEV driver - * NAK VALID WRREQUEST EP0 response sent from class driver - * NAK --- STALL Some protocol error occurred - * - * First handle the STALL condition: - */ - - if (priv->ep0state == EP0STATE_STALLED) - { - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EP0SETUPSTALLED), - priv->ep0state); - priv->rxstatus = USB_EPR_STATRX_STALL; - priv->txstatus = USB_EPR_STATTX_STALL; - } - - /* Was a transmission started? If so, txstatus will be VALID. The - * only special case to handle is when both are set to NAK. In that - * case, we need to set RX status to VALID in order to accept the next - * SETUP request. - */ - - else if (priv->rxstatus == USB_EPR_STATRX_NAK && - priv->txstatus == USB_EPR_STATTX_NAK) - { - priv->rxstatus = USB_EPR_STATRX_VALID; - } - - /* Now set the new TX and RX status */ - - stm32_seteprxstatus(EP0, priv->rxstatus); - stm32_seteptxstatus(EP0, priv->txstatus); -} - -/**************************************************************************** - * Name: stm32_lptransfer - ****************************************************************************/ - -static void stm32_lptransfer(struct stm32_usbdev_s *priv) -{ - uint8_t epno; - uint16_t istr; - - /* Stay in loop while LP interrupts are pending */ - - while (((istr = stm32_getreg(STM32_USB_ISTR)) & USB_ISTR_CTR) != 0) - { - stm32_putreg((uint16_t)~USB_ISTR_CTR, STM32_USB_ISTR); - - /* Extract highest priority endpoint number */ - - epno = (uint8_t)(istr & USB_ISTR_EPID_MASK); - - /* Handle EP0 completion events */ - - if (epno == 0) - { - stm32_ep0done(priv, istr); - } - - /* Handle other endpoint completion events */ - - else - { - stm32_epdone(priv, epno); - } - } -} - -/**************************************************************************** - * Name: stm32_hpinterrupt - ****************************************************************************/ - -static int stm32_hpinterrupt(int irq, void *context, void *arg) -{ - /* For now there is only one USB controller, but we will always refer to - * it using a pointer to make any future ports to multiple USB controllers - * easier. - */ - - struct stm32_usbdev_s *priv = &g_usbdev; - uint16_t istr; - uint8_t epno; - - /* High priority interrupts are only triggered by a correct transfer event - * for isochronous and double-buffer bulk transfers. - */ - - istr = stm32_getreg(STM32_USB_ISTR); - usbtrace(TRACE_INTENTRY(STM32_TRACEINTID_HPINTERRUPT), istr); - while ((istr & USB_ISTR_CTR) != 0) - { - stm32_putreg((uint16_t)~USB_ISTR_CTR, STM32_USB_ISTR); - - /* Extract highest priority endpoint number */ - - epno = (uint8_t)(istr & USB_ISTR_EPID_MASK); - - /* And handle the completion event */ - - stm32_epdone(priv, epno); - - /* Fetch the status again for the next time through the loop */ - - istr = stm32_getreg(STM32_USB_ISTR); - } - - usbtrace(TRACE_INTEXIT(STM32_TRACEINTID_HPINTERRUPT), 0); - return OK; -} - -/**************************************************************************** - * Name: stm32_lpinterrupt - ****************************************************************************/ - -static int stm32_lpinterrupt(int irq, void *context, void *arg) -{ - /* For now there is only one USB controller, but we will always refer to - * it using a pointer to make any future ports to multiple USB controllers - * easier. - */ - - struct stm32_usbdev_s *priv = &g_usbdev; - uint16_t istr = stm32_getreg(STM32_USB_ISTR); - - usbtrace(TRACE_INTENTRY(STM32_TRACEINTID_LPINTERRUPT), istr); - - /* Handle Reset interrupts. When this event occurs, the peripheral is left - * in the same conditions it is left by the system reset (but with the - * USB controller enabled). - */ - - if ((istr & USB_ISTR_RESET) != 0) - { - /* Reset interrupt received. Clear the RESET interrupt status. */ - - stm32_putreg(~USB_ISTR_RESET, STM32_USB_ISTR); - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_RESET), istr); - - /* Restore our power-up state and exit now because istr is no longer - * valid. - */ - - stm32_reset(priv); - goto exit_lpinterrupt; - } - - /* Handle Wakeup interrupts. - * This interrupt is only enable while the USB is suspended. - */ - - if ((istr & USB_ISTR_WKUP & priv->imask) != 0) - { - /* Wakeup interrupt received. Clear the WKUP interrupt status. The - * cause of the resume is indicated in the FNR register - */ - - stm32_putreg(~USB_ISTR_WKUP, STM32_USB_ISTR); - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_WKUP), - stm32_getreg(STM32_USB_FNR)); - - /* Perform the wakeup action */ - - stm32_initresume(priv); - priv->rsmstate = RSMSTATE_IDLE; - - /* Disable ESOF polling, disable the wakeup interrupt, and - * re-enable the suspend interrupt. Clear any pending SUSP - * interrupts. - */ - - stm32_setimask(priv, USB_CNTR_SUSPM, USB_CNTR_ESOFM | USB_CNTR_WKUPM); - stm32_putreg(~USB_CNTR_SUSPM, STM32_USB_ISTR); - } - - if ((istr & USB_ISTR_SUSP & priv->imask) != 0) - { - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SUSP), 0); - stm32_suspend(priv); - - /* Clear of the ISTR bit must be done after setting - * of USB_CNTR_FSUSP - */ - - stm32_putreg(~USB_ISTR_SUSP, STM32_USB_ISTR); - } - - if ((istr & USB_ISTR_ESOF & priv->imask) != 0) - { - stm32_putreg(~USB_ISTR_ESOF, STM32_USB_ISTR); - - /* Resume handling timing is made with ESOFs */ - - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_ESOF), 0); - stm32_esofpoll(priv); - } - - if ((istr & USB_ISTR_CTR & priv->imask) != 0) - { - /* Low priority endpoint correct transfer interrupt */ - - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_LPCTR), istr); - stm32_lptransfer(priv); - } - -exit_lpinterrupt: - usbtrace(TRACE_INTEXIT(STM32_TRACEINTID_LPINTERRUPT), - stm32_getreg(STM32_USB_EP0R)); - return OK; -} - -/**************************************************************************** - * Name: stm32_setimask - ****************************************************************************/ - -static void -stm32_setimask(struct stm32_usbdev_s *priv, - uint16_t setbits, uint16_t clrbits) -{ - uint16_t regval; - - /* Adjust the interrupt mask bits in the shadow copy first */ - - priv->imask &= ~clrbits; - priv->imask |= setbits; - - /* Then make the interrupt mask bits in the CNTR register match the shadow - * register (Hmmm... who is shadowing whom?) - */ - - regval = stm32_getreg(STM32_USB_CNTR); - regval &= ~USB_CNTR_ALLINTS; - regval |= priv->imask; - stm32_putreg(regval, STM32_USB_CNTR); -} - -/**************************************************************************** - * Suspend/Resume Helpers - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_suspend - ****************************************************************************/ - -static void stm32_suspend(struct stm32_usbdev_s *priv) -{ - uint16_t regval; - - /* Notify the class driver of the suspend event */ - - if (priv->driver) - { - CLASS_SUSPEND(priv->driver, &priv->usbdev); - } - - /* Disable ESOF polling, disable the SUSP interrupt, and enable the WKUP - * interrupt. Clear any pending WKUP interrupt. - */ - - stm32_setimask(priv, USB_CNTR_WKUPM, USB_CNTR_ESOFM | USB_CNTR_SUSPM); - stm32_putreg(~USB_ISTR_WKUP, STM32_USB_ISTR); - - /* Set the FSUSP bit in the CNTR register. This activates suspend mode - * within the USB peripheral and disables further SUSP interrupts. - */ - - regval = stm32_getreg(STM32_USB_CNTR); - regval |= USB_CNTR_FSUSP; - stm32_putreg(regval, STM32_USB_CNTR); - - /* If we are not a self-powered device, the got to low-power mode */ - - if (!priv->selfpowered) - { - /* Setting LPMODE in the CNTR register removes static power - * consumption in the USB analog transceivers but keeps them - * able to detect resume activity - */ - - regval = stm32_getreg(STM32_USB_CNTR); - regval |= USB_CNTR_LPMODE; - stm32_putreg(regval, STM32_USB_CNTR); - } - - /* Let the board-specific logic know that we have entered the suspend - * state - */ - - stm32_usbsuspend((struct usbdev_s *)priv, false); -} - -/**************************************************************************** - * Name: stm32_initresume - ****************************************************************************/ - -static void stm32_initresume(struct stm32_usbdev_s *priv) -{ - uint16_t regval; - - /* This function is called when either (1) a WKUP interrupt is received - * from the host PC, or (2) the class device implementation calls the - * wakeup() method. - */ - - /* Clear the USB low power mode (lower power mode was not set if this is - * a self-powered device. Also, low power mode is automatically cleared by - * hardware when a WKUP interrupt event occurs). - */ - - regval = stm32_getreg(STM32_USB_CNTR); - regval &= (~USB_CNTR_LPMODE); - stm32_putreg(regval, STM32_USB_CNTR); - - /* Restore full power -- whatever that means for this particular board */ - - stm32_usbsuspend((struct usbdev_s *)priv, true); - - /* Reset FSUSP bit and enable normal interrupt handling */ - - stm32_putreg(STM32_CNTR_SETUP, STM32_USB_CNTR); - - /* Notify the class driver of the resume event */ - - if (priv->driver) - { - CLASS_RESUME(priv->driver, &priv->usbdev); - } -} - -/**************************************************************************** - * Name: stm32_esofpoll - ****************************************************************************/ - -static void stm32_esofpoll(struct stm32_usbdev_s *priv) -{ - uint16_t regval; - - /* Called periodically from ESOF interrupt after RSMSTATE_STARTED */ - - switch (priv->rsmstate) - { - /* One ESOF after internal resume requested */ - - case RSMSTATE_STARTED: - regval = stm32_getreg(STM32_USB_CNTR); - regval |= USB_CNTR_RESUME; - stm32_putreg(regval, STM32_USB_CNTR); - priv->rsmstate = RSMSTATE_WAITING; - priv->nesofs = 10; - break; - - /* Countdown before completing the operation */ - - case RSMSTATE_WAITING: - priv->nesofs--; - if (priv->nesofs == 0) - { - /* Okay.. we are ready to resume normal operation */ - - regval = stm32_getreg(STM32_USB_CNTR); - regval &= (~USB_CNTR_RESUME); - stm32_putreg(regval, STM32_USB_CNTR); - priv->rsmstate = RSMSTATE_IDLE; - - /* Disable ESOF polling, disable the SUSP interrupt, and enable - * the WKUP interrupt. Clear any pending WKUP interrupt. - */ - - stm32_setimask(priv, - USB_CNTR_WKUPM, USB_CNTR_ESOFM | USB_CNTR_SUSPM); - stm32_putreg(~USB_ISTR_WKUP, STM32_USB_ISTR); - } - break; - - case RSMSTATE_IDLE: - default: - priv->rsmstate = RSMSTATE_IDLE; - break; - } -} - -/**************************************************************************** - * Endpoint Helpers - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_epreserve - ****************************************************************************/ - -static inline struct stm32_ep_s * -stm32_epreserve(struct stm32_usbdev_s *priv, uint8_t epset) -{ - struct stm32_ep_s *privep = NULL; - irqstate_t flags; - int epndx = 0; - - flags = enter_critical_section(); - epset &= priv->epavail; - if (epset) - { - /* Select the lowest bit in the set of matching, available endpoints - * (skipping EP0) - */ - - for (epndx = 1; epndx < STM32_NENDPOINTS; epndx++) - { - uint8_t bit = STM32_ENDP_BIT(epndx); - if ((epset & bit) != 0) - { - /* Mark the endpoint no longer available */ - - priv->epavail &= ~bit; - - /* And return the pointer to the standard endpoint structure */ - - privep = &priv->eplist[epndx]; - break; - } - } - } - - leave_critical_section(flags); - return privep; -} - -/**************************************************************************** - * Name: stm32_epunreserve - ****************************************************************************/ - -static inline void -stm32_epunreserve(struct stm32_usbdev_s *priv, struct stm32_ep_s *privep) -{ - irqstate_t flags = enter_critical_section(); - priv->epavail |= STM32_ENDP_BIT(USB_EPNO(privep->ep.eplog)); - leave_critical_section(flags); -} - -/**************************************************************************** - * Name: stm32_epreserved - ****************************************************************************/ - -static inline bool -stm32_epreserved(struct stm32_usbdev_s *priv, int epno) -{ - return ((priv->epavail & STM32_ENDP_BIT(epno)) == 0); -} - -/**************************************************************************** - * Name: stm32_epallocpma - ****************************************************************************/ - -static int stm32_epallocpma(struct stm32_usbdev_s *priv) -{ - irqstate_t flags; - int bufno = ERROR; - int bufndx; - - flags = enter_critical_section(); - for (bufndx = 2; bufndx < STM32_NBUFFERS; bufndx++) - { - /* Check if this buffer is available */ - - uint8_t bit = STM32_BUFFER_BIT(bufndx); - if ((priv->bufavail & bit) != 0) - { - /* Yes.. Mark the endpoint no longer available */ - - priv->bufavail &= ~bit; - - /* And return the index of the allocated buffer */ - - bufno = bufndx; - break; - } - } - - leave_critical_section(flags); - return bufno; -} - -/**************************************************************************** - * Name: stm32_epfreepma - ****************************************************************************/ - -static inline void -stm32_epfreepma(struct stm32_usbdev_s *priv, struct stm32_ep_s *privep) -{ - irqstate_t flags = enter_critical_section(); - priv->epavail |= STM32_ENDP_BIT(privep->bufno); - leave_critical_section(flags); -} - -/**************************************************************************** - * Endpoint operations - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_epconfigure - ****************************************************************************/ - -static int stm32_epconfigure(struct usbdev_ep_s *ep, - const struct usb_epdesc_s *desc, - bool last) -{ - struct stm32_ep_s *privep = (struct stm32_ep_s *)ep; - uint16_t pma; - uint16_t setting; - uint16_t maxpacket; - uint8_t epno; - -#ifdef CONFIG_DEBUG_FEATURES - if (!ep || !desc) - { - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); - uerr("ERROR: ep=%p desc=%p\n", ep, desc); - return -EINVAL; - } -#endif - - /* Get the unadorned endpoint address */ - - epno = USB_EPNO(desc->addr); - usbtrace(TRACE_EPCONFIGURE, (uint16_t)epno); - DEBUGASSERT(epno == USB_EPNO(ep->eplog)); - - /* Set the requested type */ - - switch (desc->attr & USB_EP_ATTR_XFERTYPE_MASK) - { - case USB_EP_ATTR_XFER_INT: /* Interrupt endpoint */ - setting = USB_EPR_EPTYPE_INTERRUPT; - break; - - case USB_EP_ATTR_XFER_BULK: /* Bulk endpoint */ - setting = USB_EPR_EPTYPE_BULK; - break; - - case USB_EP_ATTR_XFER_ISOC: /* Isochronous endpoint */ -#warning "REVISIT: Need to review isochronous EP setup" - setting = USB_EPR_EPTYPE_ISOC; - break; - - case USB_EP_ATTR_XFER_CONTROL: /* Control endpoint */ - setting = USB_EPR_EPTYPE_CONTROL; - break; - - default: - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADEPTYPE), - (uint16_t)desc->type); - return -EINVAL; - } - - stm32_seteptype(epno, setting); - - /* Get the address of the PMA buffer allocated for this endpoint */ - -#warning "REVISIT: Should configure BULK EPs using double buffer feature" - pma = STM32_BUFNO2BUF(privep->bufno); - - /* Get the maxpacket size of the endpoint. */ - - maxpacket = GETUINT16(desc->mxpacketsize); - DEBUGASSERT(maxpacket <= STM32_MAXPACKET_SIZE); - ep->maxpacket = maxpacket; - - /* Get the subset matching the requested direction */ - - if (USB_ISEPIN(desc->addr)) - { - /* The full, logical EP number includes direction */ - - ep->eplog = USB_EPIN(epno); - - /* Set up TX; disable RX */ - - stm32_seteptxaddr(epno, pma); - stm32_seteptxstatus(epno, USB_EPR_STATTX_NAK); - stm32_seteprxstatus(epno, USB_EPR_STATRX_DIS); - } - else - { - /* The full, logical EP number includes direction */ - - ep->eplog = USB_EPOUT(epno); - - /* Set up RX; disable TX */ - - stm32_seteprxaddr(epno, pma); - stm32_seteprxcount(epno, maxpacket); - stm32_seteprxstatus(epno, USB_EPR_STATRX_VALID); - stm32_seteptxstatus(epno, USB_EPR_STATTX_DIS); - } - - stm32_dumpep(epno); - return OK; -} - -/**************************************************************************** - * Name: stm32_epdisable - ****************************************************************************/ - -static int stm32_epdisable(struct usbdev_ep_s *ep) -{ - struct stm32_ep_s *privep = (struct stm32_ep_s *)ep; - irqstate_t flags; - uint8_t epno; - -#ifdef CONFIG_DEBUG_FEATURES - if (!ep) - { - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); - uerr("ERROR: ep=%p\n", ep); - return -EINVAL; - } -#endif - - epno = USB_EPNO(ep->eplog); - usbtrace(TRACE_EPDISABLE, epno); - - /* Cancel any ongoing activity */ - - flags = enter_critical_section(); - stm32_cancelrequests(privep); - - /* Disable TX; disable RX */ - - stm32_seteprxcount(epno, 0); - stm32_seteprxstatus(epno, USB_EPR_STATRX_DIS); - stm32_seteptxstatus(epno, USB_EPR_STATTX_DIS); - - leave_critical_section(flags); - return OK; -} - -/**************************************************************************** - * Name: stm32_epallocreq - ****************************************************************************/ - -static struct usbdev_req_s *stm32_epallocreq(struct usbdev_ep_s *ep) -{ - struct stm32_req_s *privreq; - -#ifdef CONFIG_DEBUG_FEATURES - if (!ep) - { - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); - return NULL; - } -#endif - usbtrace(TRACE_EPALLOCREQ, USB_EPNO(ep->eplog)); - - privreq = kmm_malloc(sizeof(struct stm32_req_s)); - if (!privreq) - { - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_ALLOCFAIL), 0); - return NULL; - } - - memset(privreq, 0, sizeof(struct stm32_req_s)); - return &privreq->req; -} - -/**************************************************************************** - * Name: stm32_epfreereq - ****************************************************************************/ - -static void stm32_epfreereq(struct usbdev_ep_s *ep, struct usbdev_req_s *req) -{ - struct stm32_req_s *privreq = (struct stm32_req_s *)req; - -#ifdef CONFIG_DEBUG_FEATURES - if (!ep || !req) - { - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); - return; - } -#endif - usbtrace(TRACE_EPFREEREQ, USB_EPNO(ep->eplog)); - - kmm_free(privreq); -} - -/**************************************************************************** - * Name: stm32_epsubmit - ****************************************************************************/ - -static int stm32_epsubmit(struct usbdev_ep_s *ep, struct usbdev_req_s *req) -{ - struct stm32_req_s *privreq = (struct stm32_req_s *)req; - struct stm32_ep_s *privep = (struct stm32_ep_s *)ep; - struct stm32_usbdev_s *priv; - irqstate_t flags; - uint8_t epno; - int ret = OK; - -#ifdef CONFIG_DEBUG_FEATURES - if (!req || !req->callback || !req->buf || !ep) - { - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); - uerr("ERROR: req=%p callback=%p buf=%p ep=%p\n", - req, req->callback, req->buf, ep); - return -EINVAL; - } -#endif - - usbtrace(TRACE_EPSUBMIT, USB_EPNO(ep->eplog)); - priv = privep->dev; - -#ifdef CONFIG_DEBUG_FEATURES - if (!priv->driver) - { - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_NOTCONFIGURED), - priv->usbdev.speed); - uerr("ERROR: driver=%p\n", priv->driver); - return -ESHUTDOWN; - } -#endif - - /* Handle the request from the class driver */ - - epno = USB_EPNO(ep->eplog); - req->result = -EINPROGRESS; - req->xfrd = 0; - flags = enter_critical_section(); - - /* If we are stalled, then drop all requests on the floor */ - - if (privep->stalled) - { - stm32_abortrequest(privep, privreq, -EBUSY); - uerr("ERROR: stalled\n"); - ret = -EBUSY; - } - - /* Handle IN (device-to-host) requests. NOTE: If the class device is - * using the bi-directional EP0, then we assume that they intend the EP0 - * IN functionality. - */ - - else if (USB_ISEPIN(ep->eplog) || epno == EP0) - { - /* Add the new request to the request queue for the IN endpoint */ - - stm32_rqenqueue(privep, privreq); - usbtrace(TRACE_INREQQUEUED(epno), req->len); - - /* If the IN endpoint FIFO is available, then transfer the data now */ - - if (!privep->txbusy) - { - priv->txstatus = USB_EPR_STATTX_NAK; - if (epno == EP0) - { - ret = stm32_wrrequest_ep0(priv, privep); - } - else - { - ret = stm32_wrrequest(priv, privep); - } - - /* Set the new TX status */ - - stm32_seteptxstatus(epno, priv->txstatus); - } - } - - /* Handle OUT (host-to-device) requests */ - - else - { - /* Add the new request to the request queue for the OUT endpoint */ - - privep->txnullpkt = 0; - stm32_rqenqueue(privep, privreq); - usbtrace(TRACE_OUTREQQUEUED(epno), req->len); - - /* This there a incoming data pending the availability of a request? */ - - if (priv->rxpending) - { - /* Set STAT_RX bits to '11' in the USB_EPnR, enabling further - * transactions. "While the STAT_RX bits are equal to '10' - * (NAK), any OUT request addressed to that endpoint is NAKed, - * indicating a flow control condition: the USB host will retry - * the transaction until it succeeds." - */ - - priv->rxstatus = USB_EPR_STATRX_VALID; - stm32_seteprxstatus(epno, priv->rxstatus); - - /* Data is no longer pending */ - - priv->rxpending = false; - } - } - - leave_critical_section(flags); - return ret; -} - -/**************************************************************************** - * Name: stm32_epcancel - ****************************************************************************/ - -static int stm32_epcancel(struct usbdev_ep_s *ep, struct usbdev_req_s *req) -{ - struct stm32_ep_s *privep = (struct stm32_ep_s *)ep; - irqstate_t flags; - -#ifdef CONFIG_DEBUG_USB - if (!ep || !req) - { - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); - return -EINVAL; - } -#endif - usbtrace(TRACE_EPCANCEL, USB_EPNO(ep->eplog)); - - flags = enter_critical_section(); - stm32_cancelrequests(privep); - leave_critical_section(flags); - return OK; -} - -/**************************************************************************** - * Name: stm32_epstall - ****************************************************************************/ - -static int stm32_epstall(struct usbdev_ep_s *ep, bool resume) -{ - struct stm32_ep_s *privep; - struct stm32_usbdev_s *priv; - uint8_t epno; - uint16_t status; - irqstate_t flags; - -#ifdef CONFIG_DEBUG_USB - if (!ep) - { - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); - return -EINVAL; - } -#endif - - privep = (struct stm32_ep_s *)ep; - priv = (struct stm32_usbdev_s *)privep->dev; - epno = USB_EPNO(ep->eplog); - - /* STALL or RESUME the endpoint */ - - flags = enter_critical_section(); - usbtrace(resume ? TRACE_EPRESUME : TRACE_EPSTALL, USB_EPNO(ep->eplog)); - - /* Get status of the endpoint; stall the request if the endpoint is - * disabled - */ - - if (USB_ISEPIN(ep->eplog)) - { - status = stm32_geteptxstatus(epno); - } - else - { - status = stm32_geteprxstatus(epno); - } - - if (status == 0) - { - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EPDISABLED), 0); - - if (epno == 0) - { - priv->ep0state = EP0STATE_STALLED; - } - - leave_critical_section(flags); - return -ENODEV; - } - - /* Handle the resume condition */ - - if (resume) - { - /* Resuming a stalled endpoint */ - - usbtrace(TRACE_EPRESUME, epno); - privep->stalled = false; - - if (USB_ISEPIN(ep->eplog)) - { - /* IN endpoint */ - - if (stm32_eptxstalled(epno)) - { - stm32_clrtxdtog(epno); - - /* Restart any queued write requests */ - - priv->txstatus = USB_EPR_STATTX_NAK; - if (epno == EP0) - { - stm32_wrrequest_ep0(priv, privep); - } - else - { - stm32_wrrequest(priv, privep); - } - - /* Set the new TX status */ - - stm32_seteptxstatus(epno, priv->txstatus); - } - } - else - { - /* OUT endpoint */ - - if (stm32_eprxstalled(epno)) - { - if (epno == EP0) - { - /* After clear the STALL, enable the default endpoint - * receiver - */ - - stm32_seteprxcount(epno, ep->maxpacket); - } - else - { - stm32_clrrxdtog(epno); - } - - priv->rxstatus = USB_EPR_STATRX_VALID; - stm32_seteprxstatus(epno, USB_EPR_STATRX_VALID); - } - } - } - - /* Handle the stall condition */ - - else - { - usbtrace(TRACE_EPSTALL, epno); - privep->stalled = true; - - if (USB_ISEPIN(ep->eplog)) - { - /* IN endpoint */ - - priv->txstatus = USB_EPR_STATTX_STALL; - stm32_seteptxstatus(epno, USB_EPR_STATTX_STALL); - } - else - { - /* OUT endpoint */ - - priv->rxstatus = USB_EPR_STATRX_STALL; - stm32_seteprxstatus(epno, USB_EPR_STATRX_STALL); - } - } - - leave_critical_section(flags); - return OK; -} - -/**************************************************************************** - * Device Controller Operations - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_allocep - ****************************************************************************/ - -static struct usbdev_ep_s *stm32_allocep(struct usbdev_s *dev, uint8_t epno, - bool in, uint8_t eptype) -{ - struct stm32_usbdev_s *priv = (struct stm32_usbdev_s *)dev; - struct stm32_ep_s *privep = NULL; - uint8_t epset = STM32_ENDP_ALLSET; - int bufno; - - usbtrace(TRACE_DEVALLOCEP, (uint16_t)epno); -#ifdef CONFIG_DEBUG_USB - if (!dev) - { - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); - return NULL; - } -#endif - - /* Ignore any direction bits in the logical address */ - - epno = USB_EPNO(epno); - - /* A logical address of 0 means that any endpoint will do */ - - if (epno > 0) - { - /* Otherwise, we will return the endpoint structure only for the - * requested 'logical' endpoint. - * All of the other checks will still be performed. - * - * First, verify that the logical endpoint is in the range supported by - * by the hardware. - */ - - if (epno >= STM32_NENDPOINTS) - { - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADEPNO), (uint16_t)epno); - return NULL; - } - - /* Convert the logical address to a physical OUT endpoint address and - * remove all of the candidate endpoints from the bitset except for the - * the IN/OUT pair for this logical address. - */ - - epset = STM32_ENDP_BIT(epno); - } - - /* Check if the selected endpoint number is available */ - - privep = stm32_epreserve(priv, epset); - if (!privep) - { - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EPRESERVE), (uint16_t)epset); - goto errout; - } - - /* Allocate a PMA buffer for this endpoint */ - -#warning "REVISIT: Should configure BULK EPs using double buffer feature" - bufno = stm32_epallocpma(priv); - if (bufno < 0) - { - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EPBUFFER), 0); - goto errout_with_ep; - } - - privep->bufno = (uint8_t)bufno; - return &privep->ep; - -errout_with_ep: - stm32_epunreserve(priv, privep); -errout: - return NULL; -} - -/**************************************************************************** - * Name: stm32_freeep - ****************************************************************************/ - -static void stm32_freeep(struct usbdev_s *dev, struct usbdev_ep_s *ep) -{ - struct stm32_usbdev_s *priv; - struct stm32_ep_s *privep; - -#ifdef CONFIG_DEBUG_USB - if (!dev || !ep) - { - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); - return; - } -#endif - priv = (struct stm32_usbdev_s *)dev; - privep = (struct stm32_ep_s *)ep; - usbtrace(TRACE_DEVFREEEP, (uint16_t)USB_EPNO(ep->eplog)); - - if (priv && privep) - { - /* Free the PMA buffer assigned to this endpoint */ - - stm32_epfreepma(priv, privep); - - /* Mark the endpoint as available */ - - stm32_epunreserve(priv, privep); - } -} - -/**************************************************************************** - * Name: stm32_getframe - ****************************************************************************/ - -static int stm32_getframe(struct usbdev_s *dev) -{ - uint16_t fnr; - -#ifdef CONFIG_DEBUG_USB - if (!dev) - { - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); - return -EINVAL; - } -#endif - - /* Return the last frame number detected by the hardware */ - - fnr = stm32_getreg(STM32_USB_FNR); - usbtrace(TRACE_DEVGETFRAME, fnr); - return (fnr & USB_FNR_FN_MASK); -} - -/**************************************************************************** - * Name: stm32_wakeup - ****************************************************************************/ - -static int stm32_wakeup(struct usbdev_s *dev) -{ - struct stm32_usbdev_s *priv = (struct stm32_usbdev_s *)dev; - irqstate_t flags; - - usbtrace(TRACE_DEVWAKEUP, 0); -#ifdef CONFIG_DEBUG_USB - if (!dev) - { - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); - return -EINVAL; - } -#endif - - /* Start the resume sequence. The actual resume steps will be driven - * by the ESOF interrupt. - */ - - flags = enter_critical_section(); - stm32_initresume(priv); - priv->rsmstate = RSMSTATE_STARTED; - - /* Disable the SUSP interrupt (until we are fully resumed), disable - * the WKUP interrupt (we are already waking up), and enable the - * ESOF interrupt that will drive the resume operations. Clear any - * pending ESOF interrupt. - */ - - stm32_setimask(priv, USB_CNTR_ESOFM, USB_CNTR_WKUPM | USB_CNTR_SUSPM); - stm32_putreg(~USB_ISTR_ESOF, STM32_USB_ISTR); - leave_critical_section(flags); - return OK; -} - -/**************************************************************************** - * Name: stm32_selfpowered - ****************************************************************************/ - -static int stm32_selfpowered(struct usbdev_s *dev, bool selfpowered) -{ - struct stm32_usbdev_s *priv = (struct stm32_usbdev_s *)dev; - - usbtrace(TRACE_DEVSELFPOWERED, (uint16_t)selfpowered); - -#ifdef CONFIG_DEBUG_USB - if (!dev) - { - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); - return -ENODEV; - } -#endif - - priv->selfpowered = selfpowered; - return OK; -} - -/**************************************************************************** - * Name: stm32_pullup - ****************************************************************************/ - -static int stm32_pullup(struct usbdev_s *dev, bool enable) -{ - uint32_t regval; - irqstate_t flags; - - usbtrace(TRACE_DEVPULLUP, (uint16_t)enable); - - flags = enter_critical_section(); - regval = stm32_getreg(STM32_USB_BCDR); - if (enable) - { - /* Connect the device by setting the DP pull-up bit in the BCDR - * register. - */ - - regval |= USB_BCDR_DPPU; - } - else - { - /* Disconnect the device by clearing the DP pull-up bit in the BCDR - * register. - */ - - regval &= ~USB_BCDR_DPPU; - } - - stm32_putreg(regval, STM32_USB_BCDR); - leave_critical_section(flags); - return OK; -} - -/**************************************************************************** - * Initialization/Reset - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_reset - ****************************************************************************/ - -static void stm32_reset(struct stm32_usbdev_s *priv) -{ - int epno; - - /* Put the USB controller in reset, disable all interrupts */ - - stm32_putreg(USB_CNTR_FRES, STM32_USB_CNTR); - - /* Tell the class driver that we are disconnected. The class driver - * should then accept any new configurations. - */ - - CLASS_DISCONNECT(priv->driver, &priv->usbdev); - - /* Reset the device state structure */ - - priv->ep0state = EP0STATE_IDLE; - priv->rsmstate = RSMSTATE_IDLE; - priv->rxpending = false; - - /* Reset endpoints */ - - for (epno = 0; epno < STM32_NENDPOINTS; epno++) - { - struct stm32_ep_s *privep = &priv->eplist[epno]; - - /* Cancel any queued requests. Since they are canceled - * with status -ESHUTDOWN, then will not be requeued - * until the configuration is reset. NOTE: This should - * not be necessary... the CLASS_DISCONNECT above should - * result in the class implementation calling stm32_epdisable - * for each of its configured endpoints. - */ - - stm32_cancelrequests(privep); - - /* Reset endpoint status */ - - privep->stalled = false; - privep->halted = false; - privep->txbusy = false; - privep->txnullpkt = false; - } - - /* Re-configure the USB controller in its initial, unconnected state */ - - stm32_hwreset(priv); - priv->usbdev.speed = USB_SPEED_FULL; -} - -/**************************************************************************** - * Name: stm32_hwreset - ****************************************************************************/ - -static void stm32_hwreset(struct stm32_usbdev_s *priv) -{ - /* Put the USB controller into reset, clear all interrupt enables */ - - stm32_putreg(USB_CNTR_FRES, STM32_USB_CNTR); - - /* Disable interrupts (and perhaps take the USB controller out of reset) */ - - priv->imask = 0; - stm32_putreg(priv->imask, STM32_USB_CNTR); - - /* Set the STM32 BTABLE address */ - - stm32_putreg(STM32_BTABLE_ADDRESS & 0xfff8, STM32_USB_BTABLE); - - /* Initialize EP0 */ - - stm32_seteptype(EP0, USB_EPR_EPTYPE_CONTROL); - stm32_seteptxstatus(EP0, USB_EPR_STATTX_NAK); - stm32_seteprxaddr(EP0, STM32_EP0_RXADDR); - stm32_seteprxcount(EP0, STM32_EP0MAXPACKET); - stm32_seteptxaddr(EP0, STM32_EP0_TXADDR); - stm32_clrstatusout(EP0); - stm32_seteprxstatus(EP0, USB_EPR_STATRX_VALID); - - /* Set the device to respond on default address */ - - stm32_setdevaddr(priv, 0); - - /* Clear any pending interrupts */ - - stm32_putreg(0, STM32_USB_ISTR); - - /* Enable interrupts at the USB controller */ - - stm32_setimask(priv, STM32_CNTR_SETUP, - (USB_CNTR_ALLINTS & ~STM32_CNTR_SETUP)); - stm32_dumpep(EP0); -} - -/**************************************************************************** - * Name: stm32_hwsetup - ****************************************************************************/ - -static void stm32_hwsetup(struct stm32_usbdev_s *priv) -{ - int epno; - -#ifdef CONFIG_STM32_STM32G47XX - /* FIXME - * Because stm32g4xxxx_rcc.c does not handle HSI48 for now, - * enable HSI48 clock for USB block here and wait till HSI48 is ready. - */ - - modifyreg32(STM32_RCC_CRRCR, RCC_CRRCR_HSI48ON, RCC_CRRCR_HSI48ON); - while (!(getreg32(STM32_RCC_CRRCR) & RCC_CRRCR_HSI48RDY)) - { - /* nothing to do here */ - } -#endif - - /* Power the USB controller, put the USB controller into reset, disable - * all USB interrupts - */ - - stm32_putreg(USB_CNTR_FRES | USB_CNTR_PDWN, STM32_USB_CNTR); - - /* Disconnect the device / disable the pull-up. We don't want the - * host to enumerate us until the class driver is registered. - */ - - stm32_pullup(&priv->usbdev, false); - - /* Initialize the device state structure. NOTE: many fields - * have the initial value of zero and, hence, are not explicitly - * initialized here. - */ - - memset(priv, 0, sizeof(struct stm32_usbdev_s)); - priv->usbdev.ops = &g_devops; - priv->usbdev.ep0 = &priv->eplist[EP0].ep; - priv->epavail = STM32_ENDP_ALLSET & ~STM32_ENDP_BIT(EP0); - priv->bufavail = STM32_BUFFER_ALLSET & ~STM32_BUFFER_EP0; - - /* Initialize the endpoint list */ - - for (epno = 0; epno < STM32_NENDPOINTS; epno++) - { - /* Set endpoint operations, reference to driver structure (not - * really necessary because there is only one controller), and - * the (physical) endpoint number which is just the index to the - * endpoint. - */ - - priv->eplist[epno].ep.ops = &g_epops; - priv->eplist[epno].dev = priv; - priv->eplist[epno].ep.eplog = epno; - - /* We will use a fixed maxpacket size for all endpoints (perhaps - * ISOC endpoints could have larger maxpacket???). A smaller - * packet size can be selected when the endpoint is configured. - */ - - priv->eplist[epno].ep.maxpacket = STM32_MAXPACKET_SIZE; - } - - /* Select a smaller endpoint size for EP0 */ - -#if STM32_EP0MAXPACKET < STM32_MAXPACKET_SIZE - priv->eplist[EP0].ep.maxpacket = STM32_EP0MAXPACKET; -#endif - - /* Configure the USB controller. USB uses the following GPIO pins: - * - * PA9 - VBUS - * PA10 - ID - * PA11 - DM - * PA12 - DP - * - * "As soon as the USB is enabled, these pins [DM and DP] are connected to - * the USB internal transceiver automatically." - */ - - /* Power up the USB controller, holding it in reset. There is a delay of - * about 1uS after applying power before the USB will behave predictably. - * A 5MS delay is more than enough. NOTE that we leave the USB controller - * in the reset state; the hardware will not be initialized until the - * class driver has been bound. - */ - - stm32_putreg(USB_CNTR_FRES, STM32_USB_CNTR); - up_mdelay(5); -} - -/**************************************************************************** - * Name: stm32_hwshutdown - ****************************************************************************/ - -static void stm32_hwshutdown(struct stm32_usbdev_s *priv) -{ - priv->usbdev.speed = USB_SPEED_UNKNOWN; - - /* Disable all interrupts and force the USB controller into reset */ - - stm32_putreg(USB_CNTR_FRES, STM32_USB_CNTR); - - /* Clear any pending interrupts */ - - stm32_putreg(0, STM32_USB_ISTR); - - /* Disconnect the device / disable the pull-up */ - - stm32_pullup(&priv->usbdev, false); - - /* Power down the USB controller */ - - stm32_putreg(USB_CNTR_FRES | USB_CNTR_PDWN, STM32_USB_CNTR); -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: arm_usbinitialize - * Description: - * Initialize the USB driver - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -void arm_usbinitialize(void) -{ - /* For now there is only one USB controller, but we will always refer to - * it using a pointer to make any future ports to multiple USB controllers - * easier. - */ - - struct stm32_usbdev_s *priv = &g_usbdev; - - usbtrace(TRACE_DEVINIT, 0); - stm32_checksetup(); - - /* Power up the USB controller, but leave it in the reset state */ - - stm32_hwsetup(priv); - - /* Remap the USB interrupt as needed - * (Only supported by the STM32 F3 family) - */ - - /* Attach USB controller interrupt handlers. The hardware will not be - * initialized and interrupts will not be enabled until the class device - * driver is bound. Getting the IRQs here only makes sure that we have - * them when we need them later. - */ - - if (irq_attach(STM32_IRQ_USBHP, stm32_hpinterrupt, NULL) != 0) - { - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_IRQREGISTRATION), - (uint16_t)STM32_IRQ_USBHP); - goto errout; - } - - if (irq_attach(STM32_IRQ_USBLP, stm32_lpinterrupt, NULL) != 0) - { - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_IRQREGISTRATION), - (uint16_t)STM32_IRQ_USBLP); - goto errout; - } - - return; - -errout: - arm_usbuninitialize(); -} - -/**************************************************************************** - * Name: arm_usbuninitialize - * Description: - * Initialize the USB driver - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -void arm_usbuninitialize(void) -{ - /* For now there is only one USB controller, but we will always refer to - * it using a pointer to make any future ports to multiple USB controllers - * easier. - */ - - struct stm32_usbdev_s *priv = &g_usbdev; - irqstate_t flags; - - flags = enter_critical_section(); - usbtrace(TRACE_DEVUNINIT, 0); - - /* Disable and detach the USB IRQs */ - - up_disable_irq(STM32_IRQ_USBHP); - up_disable_irq(STM32_IRQ_USBLP); - irq_detach(STM32_IRQ_USBHP); - irq_detach(STM32_IRQ_USBLP); - - if (priv->driver) - { - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_DRIVERREGISTERED), 0); - usbdev_unregister(priv->driver); - } - - /* Put the hardware in an inactive state */ - - stm32_hwshutdown(priv); - leave_critical_section(flags); -} - -/**************************************************************************** - * Name: usbdev_register - * - * Description: - * Register a USB device class driver. The class driver's bind() method - * will be called to bind it to a USB device driver. - * - ****************************************************************************/ - -int usbdev_register(struct usbdevclass_driver_s *driver) -{ - /* For now there is only one USB controller, but we will always refer to - * it using a pointer to make any future ports to multiple USB controllers - * easier. - */ - - struct stm32_usbdev_s *priv = &g_usbdev; - int ret; - - usbtrace(TRACE_DEVREGISTER, 0); - -#ifdef CONFIG_DEBUG_USB - if (!driver || !driver->ops->bind || !driver->ops->unbind || - !driver->ops->disconnect || !driver->ops->setup) - { - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); - return -EINVAL; - } - - if (priv->driver) - { - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_DRIVER), 0); - return -EBUSY; - } -#endif - - /* First hook up the driver */ - - priv->driver = driver; - - /* Then bind the class driver */ - - ret = CLASS_BIND(driver, &priv->usbdev); - if (ret) - { - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BINDFAILED), (uint16_t) - ret); - } - else - { - /* Setup the USB controller -- enabling interrupts at the USB - * controller - */ - - stm32_hwreset(priv); - - /* Enable USB controller interrupts at the NVIC */ - - up_enable_irq(STM32_IRQ_USBHP); - up_enable_irq(STM32_IRQ_USBLP); - - /* Enable pull-up to connect the device. The host should enumerate us - * some time after this - */ - - stm32_pullup(&priv->usbdev, true); - priv->usbdev.speed = USB_SPEED_FULL; - } - - return ret; -} - -/**************************************************************************** - * Name: usbdev_unregister - * - * Description: - * Un-register usbdev class driver. If the USB device is connected to a - * USB host, it will first disconnect(). The driver is also requested to - * unbind() and clean up any device state, before this procedure finally - * returns. - * - ****************************************************************************/ - -int usbdev_unregister(struct usbdevclass_driver_s *driver) -{ - /* For now there is only one USB controller, but we will always refer to - * it using a pointer to make any future ports to multiple USB controllers - * easier. - */ - - struct stm32_usbdev_s *priv = &g_usbdev; - irqstate_t flags; - - usbtrace(TRACE_DEVUNREGISTER, 0); - -#ifdef CONFIG_DEBUG_USB - if (driver != priv->driver) - { - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); - return -EINVAL; - } -#endif - - /* Reset the hardware and cancel all requests. All requests must be - * canceled while the class driver is still bound. - */ - - flags = enter_critical_section(); - stm32_reset(priv); - - /* Unbind the class driver */ - - CLASS_UNBIND(driver, &priv->usbdev); - - /* Disable USB controller interrupts (but keep them attached) */ - - up_disable_irq(STM32_IRQ_USBHP); - up_disable_irq(STM32_IRQ_USBLP); - - /* Put the hardware in an inactive state. Then bring the hardware back up - * in the reset state (this is probably not necessary, the stm32_reset() - * call above was probably sufficient). - */ - - stm32_hwshutdown(priv); - stm32_hwsetup(priv); - - /* Unhook the driver */ - - priv->driver = NULL; - leave_critical_section(flags); - return OK; -} - -#endif /* CONFIG_STM32_USBFS */ diff --git a/arch/arm/src/stm32/stm32_usbfs.h b/arch/arm/src/stm32/stm32_usbfs.h deleted file mode 100644 index b9c7ed0405b62..0000000000000 --- a/arch/arm/src/stm32/stm32_usbfs.h +++ /dev/null @@ -1,79 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_usbfs.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32_STM32_USBFS_H -#define __ARCH_ARM_SRC_STM32_STM32_USBFS_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include -#include - -#include "chip.h" -#include "hardware/stm32_usbfs.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Number of endpoints */ - -#define STM32_NENDPOINTS (8) - -/**************************************************************************** - * Public Functions Prototypes - ****************************************************************************/ - -#ifndef __ASSEMBLY__ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Name: stm32_usbsuspend - * - * Description: - * Board logic must provide the stm32_usbsuspend logic if the USBDEV driver - * is used. This function is called whenever the USB enters or leaves - * suspend mode. This is an opportunity for the board logic to shutdown - * clocks, power, etc. while the USB is suspended. - * - ****************************************************************************/ - -void stm32_usbsuspend(struct usbdev_s *dev, bool resume); - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32_STM32_USBFS_H */ diff --git a/arch/arm/src/stm32/stm32_usbhost.c b/arch/arm/src/stm32/stm32_usbhost.c deleted file mode 100644 index 1314be9c5e481..0000000000000 --- a/arch/arm/src/stm32/stm32_usbhost.c +++ /dev/null @@ -1,417 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_usbhost.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include "stm32_usbhost.h" - -#ifdef HAVE_USBHOST_TRACE - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#define TR_FMT1 false -#define TR_FMT2 true - -#define TRENTRY(id,fmt1,string) {string} - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -struct stm32_usbhost_trace_s -{ -#if 0 - uint16_t id; - bool fmt2; -#endif - const char *string; -}; - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -static const struct stm32_usbhost_trace_s g_trace1[TRACE1_NSTRINGS] = -{ -#ifdef CONFIG_STM32_OTGFS - - TRENTRY(OTGFS_TRACE1_DEVDISCONN, - TR_FMT1, - "OTGFS ERROR: Host Port %d. Device disconnected\n"), - TRENTRY(OTGFS_TRACE1_IRQATTACH, - TR_FMT1, - "OTGFS ERROR: Failed to attach IRQ\n"), - TRENTRY(OTGFS_TRACE1_TRNSFRFAILED, - TR_FMT1, - "OTGFS ERROR: Transfer Failed. ret=%d\n"), - TRENTRY(OTGFS_TRACE1_SENDSETUP, - TR_FMT1, - "OTGFS ERROR: ctrl_sendsetup() failed with: %d\n"), - TRENTRY(OTGFS_TRACE1_SENDDATA, - TR_FMT1, - "OTGFS ERROR: ctrl_senddata() failed with: %d\n"), - TRENTRY(OTGFS_TRACE1_RECVDATA, - TR_FMT1, - "OTGFS ERROR: ctrl_recvdata() failed with: %d\n"), - -# ifdef HAVE_USBHOST_TRACE_VERBOSE - - TRENTRY(OTGFS_VTRACE1_CONNECTED, - TR_FMT1, - "OTGFS Host Port %d connected.\n"), - TRENTRY(OTGFS_VTRACE1_DISCONNECTED, - TR_FMT1, - "OTGFS Host Port %d disconnected.\n"), - TRENTRY(OTGFS_VTRACE1_GINT, - TR_FMT1, - "OTGFS Handling Interrupt. Entry Point.\n"), - TRENTRY(OTGFS_VTRACE1_GINT_SOF, - TR_FMT1, - "OTGFS Handle the start of frame interrupt.\n"), - TRENTRY(OTGFS_VTRACE1_GINT_RXFLVL, - TR_FMT1, - "OTGFS Handle the RxFIFO non-empty interrupt.\n"), - TRENTRY(OTGFS_VTRACE1_GINT_NPTXFE, - TR_FMT1, - "OTGFS Handle the non-periodic TxFIFO empty interrupt.\n"), - TRENTRY(OTGFS_VTRACE1_GINT_PTXFE, - TR_FMT1, - "OTGFS Handle the periodic TxFIFO empty interrupt.\n"), - TRENTRY(OTGFS_VTRACE1_GINT_HC, - TR_FMT1, - "OTGFS Handle the host channels interrupt.\n"), - TRENTRY(OTGFS_VTRACE1_GINT_HPRT, - TR_FMT1, - "OTGFS Handle the host port interrupt.\n"), - TRENTRY(OTGFS_VTRACE1_GINT_HPRT_POCCHNG, - TR_FMT1, - "OTGFS HPRT: Port Over-Current Change.\n"), - TRENTRY(OTGFS_VTRACE1_GINT_HPRT_PCDET, - TR_FMT1, - "OTGFS HPRT: Port Connect Detect.\n"), - TRENTRY(OTGFS_VTRACE1_GINT_HPRT_PENCHNG, - TR_FMT1, - "OTGFS HPRT: Port Enable Changed.\n"), - TRENTRY(OTGFS_VTRACE1_GINT_HPRT_LSDEV, - TR_FMT1, - "OTGFS HPRT: Low Speed Device Connected.\n"), - TRENTRY(OTGFS_VTRACE1_GINT_HPRT_FSDEV, - TR_FMT1, - "OTGFS HPRT: Full Speed Device Connected.\n"), - TRENTRY(OTGFS_VTRACE1_GINT_HPRT_LSFSSW, - TR_FMT1, - "OTGFS HPRT: Host Switch: LS -> FS.\n"), - TRENTRY(OTGFS_VTRACE1_GINT_HPRT_FSLSSW, - TR_FMT1, - "OTGFS HPRT: Host Switch: FS -> LS.\n"), - TRENTRY(OTGFS_VTRACE1_GINT_DISC, - TR_FMT1, - "OTGFS Handle the disconnect detected interrupt.\n"), - TRENTRY(OTGFS_VTRACE1_GINT_IPXFR, - TR_FMT1, - "OTGFS Handle the incomplete periodic transfer.\n"), - -# endif -#endif - -#ifdef CONFIG_STM32_OTGHS - - TRENTRY(OTGHS_TRACE1_DEVDISCONN, - TR_FMT1, - "OTGHS ERROR: Host Port %d. Device disconnected\n"), - TRENTRY(OTGHS_TRACE1_IRQATTACH, - TR_FMT1, - "OTGHS ERROR: Failed to attach IRQ\n"), - TRENTRY(OTGHS_TRACE1_TRNSFRFAILED, - TR_FMT1, - "OTGHS ERROR: Transfer Failed. ret=%d\n"), - TRENTRY(OTGHS_TRACE1_SENDSETUP, - TR_FMT1, - "OTGHS ERROR: ctrl_sendsetup() failed with: %d\n"), - TRENTRY(OTGHS_TRACE1_SENDDATA, - TR_FMT1, - "OTGHS ERROR: ctrl_senddata() failed with: %d\n"), - TRENTRY(OTGHS_TRACE1_RECVDATA, - TR_FMT1, - "OTGHS ERROR: ctrl_recvdata() failed with: %d\n"), - -# ifdef HAVE_USBHOST_TRACE_VERBOSE - - TRENTRY(OTGHS_VTRACE1_CONNECTED, - TR_FMT1, - "OTGHS Host Port %d connected.\n"), - TRENTRY(OTGHS_VTRACE1_DISCONNECTED, - TR_FMT1, - "OTGHS Host Port %d disconnected.\n"), - TRENTRY(OTGHS_VTRACE1_GINT, - TR_FMT1, - "OTGHS Handling Interrupt. Entry Point.\n"), - TRENTRY(OTGHS_VTRACE1_GINT_SOF, - TR_FMT1, - "OTGHS Handle the start of frame interrupt.\n"), - TRENTRY(OTGHS_VTRACE1_GINT_RXFLVL, - TR_FMT1, - "OTGHS Handle the RxFIFO non-empty interrupt.\n"), - TRENTRY(OTGHS_VTRACE1_GINT_NPTXFE, - TR_FMT1, - "OTGHS Handle the non-periodic TxFIFO empty interrupt.\n"), - TRENTRY(OTGHS_VTRACE1_GINT_PTXFE, - TR_FMT1, - "OTGHS Handle the periodic TxFIFO empty interrupt.\n"), - TRENTRY(OTGHS_VTRACE1_GINT_HC, - TR_FMT1, - "OTGHS Handle the host channels interrupt.\n"), - TRENTRY(OTGHS_VTRACE1_GINT_HPRT, - TR_FMT1, - "OTGHS Handle the host port interrupt.\n"), - TRENTRY(OTGHS_VTRACE1_GINT_HPRT_POCCHNG, - TR_FMT1, - "OTGHS HPRT: Port Over-Current Change.\n"), - TRENTRY(OTGHS_VTRACE1_GINT_HPRT_PCDET, - TR_FMT1, - "OTGHS HPRT: Port Connect Detect.\n"), - TRENTRY(OTGHS_VTRACE1_GINT_HPRT_PENCHNG, - TR_FMT1, - "OTGHS HPRT: Port Enable Changed.\n"), - TRENTRY(OTGHS_VTRACE1_GINT_HPRT_LSDEV, - TR_FMT1, - "OTGHS HPRT: Low Speed Device Connected.\n"), - TRENTRY(OTGHS_VTRACE1_GINT_HPRT_HSDEV, - TR_FMT1, - "OTGHS HPRT: Full Speed Device Connected.\n"), - TRENTRY(OTGHS_VTRACE1_GINT_HPRT_LSHSSW, - TR_FMT1, - "OTGHS HPRT: Host Switch: LS -> HS.\n"), - TRENTRY(OTGHS_VTRACE1_GINT_HPRT_HSLSSW, - TR_FMT1, - "OTGHS HPRT: Host Switch: HS -> LS.\n"), - TRENTRY(OTGHS_VTRACE1_GINT_DISC, - TR_FMT1, - "OTGHS Handle the disconnect detected interrupt.\n"), - TRENTRY(OTGHS_VTRACE1_GINT_IPXFR, - TR_FMT1, - "OTGHS Handle the incomplete periodic transfer.\n"), -# endif -#endif -}; - -static const struct stm32_usbhost_trace_s g_trace2[TRACE2_NSTRINGS] = -{ -#ifdef CONFIG_STM32_OTGFS - - TRENTRY(OTGFS_TRACE2_CLIP, - TR_FMT2, - "OTGFS CLIP: chidx: %d buflen: %d\n"), - -# ifdef HAVE_USBHOST_TRACE_VERBOSE - TRENTRY(OTGFS_VTRACE2_CHANWAKEUP_IN, - TR_FMT2, - "OTGFS EP%d(IN) wake up with result: %d\n"), - TRENTRY(OTGFS_VTRACE2_CHANWAKEUP_OUT, - TR_FMT2, - "OTGFS EP%d(OUT) wake up with result: %d\n"), - TRENTRY(OTGFS_VTRACE2_CTRLIN, - TR_FMT2, - "OTGFS CTRL_IN type: %02x req: %02x\n"), - TRENTRY(OTGFS_VTRACE2_CTRLOUT, - TR_FMT2, - "OTGFS CTRL_OUT type: %02x req: %02x\n"), - TRENTRY(OTGFS_VTRACE2_INTRIN, - TR_FMT2, - "OTGFS INTR_IN chidx: %02x len: %02x\n"), - TRENTRY(OTGFS_VTRACE2_INTROUT, - TR_FMT2, - "OTGFS INTR_OUT chidx: %02x len: %02x\n"), - TRENTRY(OTGFS_VTRACE2_BULKIN, - TR_FMT2, - "OTGFS BULK_IN chidx: %02x len: %02x\n"), - TRENTRY(OTGFS_VTRACE2_BULKOUT, - TR_FMT2, - "OTGFS BULK_OUT chidx: %02x len: %02x\n"), - TRENTRY(OTGFS_VTRACE2_ISOCIN, - TR_FMT2, - "OTGFS ISOC_IN chidx: %02x len: %04d\n"), - TRENTRY(OTGFS_VTRACE2_ISOCOUT, - TR_FMT2, - "OTGFS ISOC_OUT chidx: %02x req: %02x\n"), - TRENTRY(OTGFS_VTRACE2_STARTTRANSFER, - TR_FMT2, - "OTGFS Transfer chidx: %d buflen: %d\n"), - TRENTRY(OTGFS_VTRACE2_CHANCONF_CTRL_IN, - TR_FMT2, - "OTGFS Channel configured. chidx: %d: (EP%d,IN ,CTRL)\n"), - TRENTRY(OTGFS_VTRACE2_CHANCONF_CTRL_OUT, - TR_FMT2, - "OTGFS Channel configured. chidx: %d: (EP%d,OUT,CTRL)\n"), - TRENTRY(OTGFS_VTRACE2_CHANCONF_INTR_IN, - TR_FMT2, - "OTGFS Channel configured. chidx: %d: (EP%d,IN ,INTR)\n"), - TRENTRY(OTGFS_VTRACE2_CHANCONF_INTR_OUT, - TR_FMT2, - "OTGFS Channel configured. chidx: %d: (EP%d,OUT,INTR)\n"), - TRENTRY(OTGFS_VTRACE2_CHANCONF_BULK_IN, - TR_FMT2, - "OTGFS Channel configured. chidx: %d: (EP%d,IN ,BULK)\n"), - TRENTRY(OTGFS_VTRACE2_CHANCONF_BULK_OUT, - TR_FMT2, - "OTGFS Channel configured. chidx: %d: (EP%d,OUT,BULK)\n"), - TRENTRY(OTGFS_VTRACE2_CHANCONF_ISOC_IN, - TR_FMT2, - "OTGFS Channel configured. chidx: %d: (EP%d,IN ,ISOC)\n"), - TRENTRY(OTGFS_VTRACE2_CHANCONF_ISOC_OUT, - TR_FMT2, - "OTGFS Channel configured. chidx: %d: (EP%d,OUT,ISOC)\n"), - TRENTRY(OTGFS_VTRACE2_CHANHALT, - TR_FMT2, - "OTGFS Channel halted. chidx: %d, reason: %d\n"), - -# endif -#endif -#ifdef CONFIG_STM32_OTGHS - - TRENTRY(OTGHS_TRACE2_CLIP, - TR_FMT2, - "OTGHS CLIP: chidx: %d buflen: %d\n"), - -# ifdef HAVE_USBHOST_TRACE_VERBOSE - - TRENTRY(OTGHS_VTRACE2_CHANWAKEUP_IN, - TR_FMT2, - "OTGHS EP%d(IN) wake up with result: %d\n"), - TRENTRY(OTGHS_VTRACE2_CHANWAKEUP_OUT, - TR_FMT2, - "OTGHS EP%d(OUT) wake up with result: %d\n"), - TRENTRY(OTGHS_VTRACE2_CTRLIN, - TR_FMT2, - "OTGHS CTRL_IN type: %02x req: %02x\n"), - TRENTRY(OTGHS_VTRACE2_CTRLOUT, - TR_FMT2, - "OTGHS CTRL_OUT type: %02x req: %02x\n"), - TRENTRY(OTGHS_VTRACE2_INTRIN, - TR_FMT2, - "OTGHS INTR_IN chidx: %02x len: %02x\n"), - TRENTRY(OTGHS_VTRACE2_INTROUT, - TR_FMT2, - "OTGHS INTR_OUT chidx: %02x len: %02x\n"), - TRENTRY(OTGHS_VTRACE2_BULKIN, - TR_FMT2, - "OTGHS BULK_IN chidx: %02x len: %02x\n"), - TRENTRY(OTGHS_VTRACE2_BULKOUT, - TR_FMT2, - "OTGHS BULK_OUT chidx: %02x len: %02x\n"), - TRENTRY(OTGHS_VTRACE2_ISOCIN, - TR_FMT2, - "OTGHS ISOC_IN chidx: %02x len: %04d\n"), - TRENTRY(OTGHS_VTRACE2_ISOCOUT, - TR_FMT2, - "OTGHS ISOC_OUT chidx: %02x req: %02x\n"), - TRENTRY(OTGHS_VTRACE2_STARTTRANSFER, - TR_FMT2, - "OTGHS Transfer chidx: %d buflen: %d\n"), - TRENTRY(OTGHS_VTRACE2_CHANCONF_CTRL_IN, - TR_FMT2, - "OTGHS Channel configured. chidx: %d: (EP%d,IN ,CTRL)\n"), - TRENTRY(OTGHS_VTRACE2_CHANCONF_CTRL_OUT, - TR_FMT2, - "OTGHS Channel configured. chidx: %d: (EP%d,OUT,CTRL)\n"), - TRENTRY(OTGHS_VTRACE2_CHANCONF_INTR_IN, - TR_FMT2, - "OTGHS Channel configured. chidx: %d: (EP%d,IN ,INTR)\n"), - TRENTRY(OTGHS_VTRACE2_CHANCONF_INTR_OUT, - TR_FMT2, - "OTGHS Channel configured. chidx: %d: (EP%d,OUT,INTR)\n"), - TRENTRY(OTGHS_VTRACE2_CHANCONF_BULK_IN, - TR_FMT2, - "OTGHS Channel configured. chidx: %d: (EP%d,IN ,BULK)\n"), - TRENTRY(OTGHS_VTRACE2_CHANCONF_BULK_OUT, - TR_FMT2, - "OTGHS Channel configured. chidx: %d: (EP%d,OUT,BULK)\n"), - TRENTRY(OTGHS_VTRACE2_CHANCONF_ISOC_IN, - TR_FMT2, - "OTGHS Channel configured. chidx: %d: (EP%d,IN ,ISOC)\n"), - TRENTRY(OTGHS_VTRACE2_CHANCONF_ISOC_OUT, - TR_FMT2, - "OTGHS Channel configured. chidx: %d: (EP%d,OUT,ISOC)\n"), - TRENTRY(OTGHS_VTRACE2_CHANHALT, - TR_FMT2, - "OTGHS Channel halted. chidx: %d, reason: %d\n"), - -# endif -#endif -}; - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: usbhost_trformat1 and usbhost_trformat2 - * - * Description: - * This interface must be provided by platform specific logic that knows - * the HCDs encoding of USB trace data. - * - * Given an 9-bit index, return a format string suitable for use with, say, - * printf. The returned format is expected to handle two unsigned integer - * values. - * - ****************************************************************************/ - -const char *usbhost_trformat1(uint16_t id) -{ - int ndx = TRACE1_INDEX(id); - - if (ndx < TRACE1_NSTRINGS) - { - return g_trace1[ndx].string; - } - - return NULL; -} - -const char *usbhost_trformat2(uint16_t id) -{ - int ndx = TRACE2_INDEX(id); - - if (ndx < TRACE2_NSTRINGS) - { - return g_trace2[ndx].string; - } - - return NULL; -} - -#endif /* HAVE_USBHOST_TRACE */ diff --git a/arch/arm/src/stm32/stm32_usbhost.h b/arch/arm/src/stm32/stm32_usbhost.h deleted file mode 100644 index b71a9e46a7c09..0000000000000 --- a/arch/arm/src/stm32/stm32_usbhost.h +++ /dev/null @@ -1,283 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_usbhost.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32_STM32_USBHOST_H -#define __ARCH_ARM_SRC_STM32_STM32_USBHOST_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include -#include -#include - -#include "chip.h" -#include "hardware/stm32fxxxxx_otgfs.h" -#include "hardware/stm32_otghs.h" - -#if (defined(CONFIG_STM32_OTGFS) || defined(CONFIG_STM32_OTGHS)) && \ - defined(CONFIG_STM32_USBHOST) - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -#ifdef HAVE_USBHOST_TRACE -enum usbhost_trace1codes_e -{ - __TRACE1_BASEVALUE = 0, /* This will force the first value to be 1 */ - -#ifdef CONFIG_STM32_OTGFS - - OTGFS_TRACE1_DEVDISCONN, /* OTGFS ERROR: Host Port Device disconnected */ - OTGFS_TRACE1_IRQATTACH, /* OTGFS ERROR: Failed to attach IRQ */ - OTGFS_TRACE1_TRNSFRFAILED, /* OTGFS ERROR: Host Port Transfer Failed */ - OTGFS_TRACE1_SENDSETUP, /* OTGFS ERROR: sendsetup() failed with: */ - OTGFS_TRACE1_SENDDATA, /* OTGFS ERROR: senddata() failed with: */ - OTGFS_TRACE1_RECVDATA, /* OTGFS ERROR: recvdata() failed with: */ - -# ifdef HAVE_USBHOST_TRACE_VERBOSE - - OTGFS_VTRACE1_CONNECTED, /* OTGFS Host Port connected */ - OTGFS_VTRACE1_DISCONNECTED, /* OTGFS Host Port disconnected */ - OTGFS_VTRACE1_GINT, /* OTGFS Handling Interrupt. Entry Point */ - OTGFS_VTRACE1_GINT_SOF, /* OTGFS Handle the start of frame interrupt */ - OTGFS_VTRACE1_GINT_RXFLVL, /* OTGFS Handle the RxFIFO non-empty interrupt */ - OTGFS_VTRACE1_GINT_NPTXFE, /* OTGFS Handle the non-periodic TxFIFO empty interrupt */ - OTGFS_VTRACE1_GINT_PTXFE, /* OTGFS Handle the periodic TxFIFO empty interrupt */ - OTGFS_VTRACE1_GINT_HC, /* OTGFS Handle the host channels interrupt */ - OTGFS_VTRACE1_GINT_HPRT, /* OTGFS Handle the host port interrupt */ - OTGFS_VTRACE1_GINT_HPRT_POCCHNG, /* OTGFS HPRT: Port Over-Current Change */ - OTGFS_VTRACE1_GINT_HPRT_PCDET, /* OTGFS HPRT: Port Connect Detect */ - OTGFS_VTRACE1_GINT_HPRT_PENCHNG, /* OTGFS HPRT: Port Enable Changed */ - OTGFS_VTRACE1_GINT_HPRT_LSDEV, /* OTGFS HPRT: Low Speed Device Connected */ - OTGFS_VTRACE1_GINT_HPRT_FSDEV, /* OTGFS HPRT: Full Speed Device Connected */ - OTGFS_VTRACE1_GINT_HPRT_LSFSSW, /* OTGFS HPRT: Host Switch: LS -> FS */ - OTGFS_VTRACE1_GINT_HPRT_FSLSSW, /* OTGFS HPRT: Host Switch: FS -> LS */ - OTGFS_VTRACE1_GINT_DISC, /* OTGFS Handle the disconnect detected interrupt */ - OTGFS_VTRACE1_GINT_IPXFR, /* OTGFS Handle the incomplete periodic transfer */ - -# endif -#endif - -#ifdef CONFIG_STM32_OTGHS - - OTGHS_TRACE1_DEVDISCONN, /* OTGHS ERROR: Host Port Device disconnected */ - OTGHS_TRACE1_IRQATTACH, /* OTGHS ERROR: Failed to attach IRQ */ - OTGHS_TRACE1_TRNSFRFAILED, /* OTGHS ERROR: Host Port Transfer Failed */ - OTGHS_TRACE1_SENDSETUP, /* OTGHS ERROR: sendsetup() failed with: */ - OTGHS_TRACE1_SENDDATA, /* OTGHS ERROR: senddata() failed with: */ - OTGHS_TRACE1_RECVDATA, /* OTGHS ERROR: recvdata() failed with: */ - -# ifdef HAVE_USBHOST_TRACE_VERBOSE - - OTGHS_VTRACE1_CONNECTED, /* OTGHS Host Port connected */ - OTGHS_VTRACE1_DISCONNECTED, /* OTGHS Host Port disconnected */ - OTGHS_VTRACE1_GINT, /* OTGHS Handling Interrupt. Entry Point */ - OTGHS_VTRACE1_GINT_SOF, /* OTGHS Handle the start of frame interrupt */ - OTGHS_VTRACE1_GINT_RXFLVL, /* OTGHS Handle the RxFIFO non-empty interrupt */ - OTGHS_VTRACE1_GINT_NPTXFE, /* OTGHS Handle the non-periodic TxFIFO empty interrupt */ - OTGHS_VTRACE1_GINT_PTXFE, /* OTGHS Handle the periodic TxFIFO empty interrupt */ - OTGHS_VTRACE1_GINT_HC, /* OTGHS Handle the host channels interrupt */ - OTGHS_VTRACE1_GINT_HPRT, /* OTGHS Handle the host port interrupt */ - OTGHS_VTRACE1_GINT_HPRT_POCCHNG, /* OTGHS HPRT: Port Over-Current Change */ - OTGHS_VTRACE1_GINT_HPRT_PCDET, /* OTGHS HPRT: Port Connect Detect */ - OTGHS_VTRACE1_GINT_HPRT_PENCHNG, /* OTGHS HPRT: Port Enable Changed */ - OTGHS_VTRACE1_GINT_HPRT_LSDEV, /* OTGHS HPRT: Low Speed Device Connected */ - OTGHS_VTRACE1_GINT_HPRT_FSDEV, /* OTGHS HPRT: Full Speed Device Connected */ - OTGHS_VTRACE1_GINT_HPRT_LSFSSW, /* OTGHS HPRT: Host Switch: LS -> FS */ - OTGHS_VTRACE1_GINT_HPRT_FSLSSW, /* OTGHS HPRT: Host Switch: FS -> LS */ - OTGHS_VTRACE1_GINT_DISC, /* OTGHS Handle the disconnect detected interrupt */ - OTGHS_VTRACE1_GINT_IPXFR, /* OTGHS Handle the incomplete periodic transfer */ - -# endif -#endif - - __TRACE1_NSTRINGS, /* Separates the format 1 from the format 2 strings */ - -#ifdef CONFIG_STM32_OTGFS - - OTGFS_TRACE2_CLIP, /* OTGFS CLIP: chidx: buflen: */ - -# ifdef HAVE_USBHOST_TRACE_VERBOSE - - OTGFS_VTRACE2_CHANWAKEUP_IN, /* OTGFS IN Channel wake up with result */ - OTGFS_VTRACE2_CHANWAKEUP_OUT, /* OTGFS OUT Channel wake up with result */ - OTGFS_VTRACE2_CTRLIN, /* OTGFS CTRLIN */ - OTGFS_VTRACE2_CTRLOUT, /* OTGFS CTRLOUT */ - OTGFS_VTRACE2_INTRIN, /* OTGFS INTRIN */ - OTGFS_VTRACE2_INTROUT, /* OTGFS INTROUT */ - OTGFS_VTRACE2_BULKIN, /* OTGFS BULKIN */ - OTGFS_VTRACE2_BULKOUT, /* OTGFS BULKOUT */ - OTGFS_VTRACE2_ISOCIN, /* OTGFS ISOCIN */ - OTGFS_VTRACE2_ISOCOUT, /* OTGFS ISOCOUT */ - OTGFS_VTRACE2_STARTTRANSFER, /* OTGFS EP buflen */ - OTGFS_VTRACE2_CHANCONF_CTRL_IN, - OTGFS_VTRACE2_CHANCONF_CTRL_OUT, - OTGFS_VTRACE2_CHANCONF_INTR_IN, - OTGFS_VTRACE2_CHANCONF_INTR_OUT, - OTGFS_VTRACE2_CHANCONF_BULK_IN, - OTGFS_VTRACE2_CHANCONF_BULK_OUT, - OTGFS_VTRACE2_CHANCONF_ISOC_IN, - OTGFS_VTRACE2_CHANCONF_ISOC_OUT, - OTGFS_VTRACE2_CHANHALT, /* Channel halted. chidx: , reason: */ - -# endif -#endif - -#ifdef CONFIG_STM32_OTGHS - - OTGHS_TRACE2_CLIP, /* OTGHS CLIP: chidx: buflen: */ - -# ifdef HAVE_USBHOST_TRACE_VERBOSE - - OTGHS_VTRACE2_CHANWAKEUP_IN, /* OTGHS IN Channel wake up with result */ - OTGHS_VTRACE2_CHANWAKEUP_OUT, /* OTGHS OUT Channel wake up with result */ - OTGHS_VTRACE2_CTRLIN, /* OTGHS CTRLIN */ - OTGHS_VTRACE2_CTRLOUT, /* OTGHS CTRLOUT */ - OTGHS_VTRACE2_INTRIN, /* OTGHS INTRIN */ - OTGHS_VTRACE2_INTROUT, /* OTGHS INTROUT */ - OTGHS_VTRACE2_BULKIN, /* OTGHS BULKIN */ - OTGHS_VTRACE2_BULKOUT, /* OTGHS BULKOUT */ - OTGHS_VTRACE2_ISOCIN, /* OTGHS ISOCIN */ - OTGHS_VTRACE2_ISOCOUT, /* OTGHS ISOCOUT */ - OTGHS_VTRACE2_STARTTRANSFER, /* OTGHS EP buflen */ - OTGHS_VTRACE2_CHANCONF_CTRL_IN, - OTGHS_VTRACE2_CHANCONF_CTRL_OUT, - OTGHS_VTRACE2_CHANCONF_INTR_IN, - OTGHS_VTRACE2_CHANCONF_INTR_OUT, - OTGHS_VTRACE2_CHANCONF_BULK_IN, - OTGHS_VTRACE2_CHANCONF_BULK_OUT, - OTGHS_VTRACE2_CHANCONF_ISOC_IN, - OTGHS_VTRACE2_CHANCONF_ISOC_OUT, - OTGHS_VTRACE2_CHANHALT, /* Channel halted. chidx: , reason: */ - -# endif -#endif - - __TRACE2_NSTRINGS /* Total number of enumeration values */ -}; - -# define TRACE1_FIRST ((int)__TRACE1_BASEVALUE + 1) -# define TRACE1_INDEX(id) ((int)(id) - TRACE1_FIRST) -# define TRACE1_NSTRINGS TRACE1_INDEX(__TRACE1_NSTRINGS) - -# define TRACE2_FIRST ((int)__TRACE1_NSTRINGS + 1) -# define TRACE2_INDEX(id) ((int)(id) - TRACE2_FIRST) -# define TRACE2_NSTRINGS TRACE2_INDEX(__TRACE2_NSTRINGS) - -#endif - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/* STM32 USB OTG FS Host Driver Support - * - * Pre-requisites - * - * CONFIG_STM32_USBHOST - Enable general USB host support - * CONFIG_USBHOST - Enable general USB host support - * CONFIG_STM32_OTGFS - Enable the STM32 USB OTG FS block - * or - * CONFIG_STM32_OTGHS - Enable the STM32 USB OTG HS block - * CONFIG_STM32_SYSCFG - Needed - * - * Options: - * - * CONFIG_STM32_OTGFS_RXFIFO_SIZE - Size of the RX FIFO in 32-bit words. - * Default 128 (512 bytes) - * CONFIG_STM32_OTGFS_NPTXFIFO_SIZE - Size of the non-periodic Tx FIFO - * in 32-bit words. Default 96 (384 bytes) - * CONFIG_STM32_OTGFS_PTXFIFO_SIZE - Size of the periodic Tx FIFO in 32-bit - * words. Default 96 (384 bytes) - * CONFIG_STM32_OTGFS_SOFINTR - Enable SOF interrupts. Why would you ever - * want to do that? - * - * CONFIG_STM32_OTGHS_RXFIFO_SIZE - Size of the RX FIFO in 32-bit words. - * Default 128 (512 bytes) - * CONFIG_STM32_OTGHS_NPTXFIFO_SIZE - Size of the non-periodic Tx FIFO - * in 32-bit words. Default 96 (384 bytes) - * CONFIG_STM32_OTGHS_PTXFIFO_SIZE - Size of the periodic Tx FIFO in 32-bit - * words. Default 96 (384 bytes) - * CONFIG_STM32_OTGHS_SOFINTR - Enable SOF interrupts. Why would you ever - * want to do that? - * - * CONFIG_STM32_USBHOST_REGDEBUG - Enable very low-level register access - * debug. Depends on CONFIG_DEBUG_FEATURES. - */ - -#ifndef __ASSEMBLY__ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Name: stm32_usbhost_vbusdrive - * - * Description: - * Enable/disable driving of VBUS 5V output. This function must be - * provided be each platform that implements the STM32 OTG FS host - * interface. - * - * "On-chip 5 V VBUS generation is not supported. For this reason, a - * charge pump or, if 5 V are available on the application board, a basic - * power switch, must be added externally to drive the 5 V VBUS line. The - * external charge pump can be driven by any GPIO output. When the - * application decides to power on VBUS using the chosen GPIO, it must - * also set the port power bit in the host port control and status - * register (PPWR bit in OTG_FS_HPRT). - * - * "The application uses this field to control power to this port, and the - * core clears this bit on an overcurrent condition." - * - * Input Parameters: - * iface - For future growth to handle multiple USB host interface. - * Should be zero. - * enable - true: enable VBUS power; false: disable VBUS power - * - * Returned Value: - * None - * - ****************************************************************************/ - -#if defined(CONFIG_STM32_OTGFS_VBUS_CONTROL) || \ - defined(CONFIG_STM32_OTGHS_VBUS_CONTROL) -void stm32_usbhost_vbusdrive(int iface, bool enable); -#endif - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ -#endif /* CONFIG_STM32_OTGFS && CONFIG_STM32_USBHOST */ -#endif /* __ARCH_ARM_SRC_STM32_STM32_USBHOST_H */ diff --git a/arch/arm/src/stm32/stm32_userspace.c b/arch/arm/src/stm32/stm32_userspace.c deleted file mode 100644 index 92897821b352e..0000000000000 --- a/arch/arm/src/stm32/stm32_userspace.c +++ /dev/null @@ -1,105 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_userspace.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include - -#include "stm32_mpuinit.h" -#include "stm32_userspace.h" - -#ifdef CONFIG_BUILD_PROTECTED - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_userspace - * - * Description: - * For the case of the separate user-/kernel-space build, perform whatever - * platform specific initialization of the user memory is required. - * Normally this just means initializing the user space .data and .bss - * segments. - * - ****************************************************************************/ - -void stm32_userspace(void) -{ - uint8_t *src; - uint8_t *dest; - uint8_t *end; - - /* Clear all of user-space .bss */ - - DEBUGASSERT(USERSPACE->us_bssstart != 0 && USERSPACE->us_bssend != 0 && - USERSPACE->us_bssstart <= USERSPACE->us_bssend); - - dest = (uint8_t *)USERSPACE->us_bssstart; - end = (uint8_t *)USERSPACE->us_bssend; - - while (dest != end) - { - *dest++ = 0; - } - - /* Initialize all of user-space .data */ - - DEBUGASSERT(USERSPACE->us_datasource != 0 && - USERSPACE->us_datastart != 0 && USERSPACE->us_dataend != 0 && - USERSPACE->us_datastart <= USERSPACE->us_dataend); - - src = (uint8_t *)USERSPACE->us_datasource; - dest = (uint8_t *)USERSPACE->us_datastart; - end = (uint8_t *)USERSPACE->us_dataend; - - while (dest != end) - { - *dest++ = *src++; - } - - /* Configure the MPU to permit user-space access to its FLASH and RAM */ - - stm32_mpuinitialize(); -} - -#endif /* CONFIG_BUILD_PROTECTED */ diff --git a/arch/arm/src/stm32/stm32_waste.c b/arch/arm/src/stm32/stm32_waste.c deleted file mode 100644 index ce40916f4f9c8..0000000000000 --- a/arch/arm/src/stm32/stm32_waste.c +++ /dev/null @@ -1,44 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_waste.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include -#include "stm32_waste.h" - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -uint32_t g_waste_counter = 0; - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -void stm32_waste(void) -{ - g_waste_counter++; -} diff --git a/arch/arm/src/stm32/stm32_waste.h b/arch/arm/src/stm32/stm32_waste.h deleted file mode 100644 index 39a9b88893e6f..0000000000000 --- a/arch/arm/src/stm32/stm32_waste.h +++ /dev/null @@ -1,66 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_waste.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32_STM32_WASTE_H -#define __ARCH_ARM_SRC_STM32_STM32_WASTE_H - -/* Waste CPU Time */ - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#ifndef __ASSEMBLY__ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/* Waste CPU Time - * - * stm32_waste() is the logic that will be executed when portions of kernel - * or user-app is polling some register or similar, waiting for desired - * status. This time is wasted away. This function offers a measure of - * badly written piece of software or some undesired behavior. - * - * At the same time this function adds to some IDLE time which portion - * cannot be used for other purposes (yet). - */ - -void stm32_waste(void); - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32_STM32_WASTE_H */ diff --git a/arch/arm/src/stm32/stm32_wdg.h b/arch/arm/src/stm32/stm32_wdg.h deleted file mode 100644 index 0ad2d4eb362c7..0000000000000 --- a/arch/arm/src/stm32/stm32_wdg.h +++ /dev/null @@ -1,106 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_wdg.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32_STM32_WDG_H -#define __ARCH_ARM_SRC_STM32_STM32_WDG_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "chip.h" -#include "hardware/stm32_wdg.h" - -#ifdef CONFIG_WATCHDOG - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#ifndef __ASSEMBLY__ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_iwdginitialize - * - * Description: - * Initialize the IWDG watchdog time. The watchdog timer is initialized - * and registers as 'devpath. The initial state of the watchdog time is - * disabled. - * - * Input Parameters: - * devpath - The full path to the watchdog. This should be of the form - * /dev/watchdog0 - * lsifreq - The calibrated LSI clock frequency - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_IWDG -void stm32_iwdginitialize(const char *devpath, uint32_t lsifreq); -#endif - -/**************************************************************************** - * Name: stm32_wwdginitialize - * - * Description: - * Initialize the WWDG watchdog time. The watchdog timer is initializeed - * and registers as 'devpath. The initial state of the watchdog time is - * disabled. - * - * Input Parameters: - * devpath - The full path to the watchdog. This should be of the form - * /dev/watchdog0 - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_WWDG -void stm32_wwdginitialize(const char *devpath); -#endif - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ -#endif /* CONFIG_WATCHDOG */ -#endif /* __ARCH_ARM_SRC_STM32_STM32_WDG_H */ diff --git a/arch/arm/src/stm32/stm32_wwdg.c b/arch/arm/src/stm32/stm32_wwdg.c deleted file mode 100644 index 26decaa9e5f33..0000000000000 --- a/arch/arm/src/stm32/stm32_wwdg.c +++ /dev/null @@ -1,801 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_wwdg.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include - -#include -#include -#include - -#include -#include -#include -#include - -#include "arm_internal.h" -#include "hardware/stm32_dbgmcu.h" -#include "stm32_wdg.h" - -#if defined(CONFIG_WATCHDOG) && defined(CONFIG_STM32_WWDG) - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Clocking *****************************************************************/ - -/* The minimum frequency of the WWDG clock is: - * - * Fmin = PCLK1 / 4096 / 8 - * - * So the maximum delay (in milliseconds) is then: - * - * 1000 * (WWDG_CR_T_MAX+1) / Fmin - * - * For example, if PCLK1 = 42MHz, then the maximum delay is: - * - * Fmin = 1281.74 - * 1000 * 64 / Fmin = 49.93 msec - */ - -#define WWDG_FMIN (STM32_PCLK1_FREQUENCY / 4096 / 8) -#define WWDG_MAXTIMEOUT (1000 * (WWDG_CR_T_MAX+1) / WWDG_FMIN) - -/* Configuration ************************************************************/ - -#ifndef CONFIG_STM32_WWDG_DEFTIMOUT -# define CONFIG_STM32_WWDG_DEFTIMOUT WWDG_MAXTIMEOUT -#endif - -#ifndef CONFIG_DEBUG_WATCHDOG_INFO -# undef CONFIG_STM32_WWDG_REGDEBUG -#endif - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/* This structure provides the private representation of the "lower-half" - * driver state structure. This structure must be cast-compatible with the - * well-known watchdog_lowerhalf_s structure. - */ - -struct stm32_lowerhalf_s -{ - const struct watchdog_ops_s *ops; /* Lower half operations */ - xcpt_t handler; /* Current EWI interrupt handler */ - uint32_t timeout; /* The actual timeout value */ - uint32_t fwwdg; /* WWDG clock frequency */ - bool started; /* The timer has been started */ - uint8_t reload; /* The 7-bit reload field reset value */ - uint8_t window; /* The 7-bit window (W) field value */ -}; - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -/* Register operations ******************************************************/ - -#ifdef CONFIG_STM32_WWDG_REGDEBUG -static uint16_t stm32_getreg(uint32_t addr); -static void stm32_putreg(uint16_t val, uint32_t addr); -#else -# define stm32_getreg(addr) getreg32(addr) -# define stm32_putreg(val,addr) putreg32(val,addr) -#endif -static void stm32_setwindow(struct stm32_lowerhalf_s *priv, - uint8_t window); - -/* Interrupt handling *******************************************************/ - -static int stm32_interrupt(int irq, void *context, void *arg); - -/* "Lower half" driver methods **********************************************/ - -static int stm32_start(struct watchdog_lowerhalf_s *lower); -static int stm32_stop(struct watchdog_lowerhalf_s *lower); -static int stm32_keepalive(struct watchdog_lowerhalf_s *lower); -static int stm32_getstatus(struct watchdog_lowerhalf_s *lower, - struct watchdog_status_s *status); -static int stm32_settimeout(struct watchdog_lowerhalf_s *lower, - uint32_t timeout); -static xcpt_t stm32_capture(struct watchdog_lowerhalf_s *lower, - xcpt_t handler); -static int stm32_ioctl(struct watchdog_lowerhalf_s *lower, int cmd, - unsigned long arg); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* "Lower half" driver methods */ - -static const struct watchdog_ops_s g_wdgops = -{ - .start = stm32_start, - .stop = stm32_stop, - .keepalive = stm32_keepalive, - .getstatus = stm32_getstatus, - .settimeout = stm32_settimeout, - .capture = stm32_capture, - .ioctl = stm32_ioctl, -}; - -/* "Lower half" driver state */ - -static struct stm32_lowerhalf_s g_wdgdev; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_getreg - * - * Description: - * Get the contents of an STM32 register - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_WWDG_REGDEBUG -static uint16_t stm32_getreg(uint32_t addr) -{ - static uint32_t prevaddr = 0; - static uint32_t count = 0; - static uint16_t preval = 0; - - /* Read the value from the register */ - - uint16_t val = getreg16(addr); - - /* Is this the same value that we read from the same register last time? - * Are we polling the register? If so, suppress some of the output. - */ - - if (addr == prevaddr && val == preval) - { - if (count == 0xffffffff || ++count > 3) - { - if (count == 4) - { - wdinfo("...\n"); - } - - return val; - } - } - - /* No this is a new address or value */ - - else - { - /* Did we print "..." for the previous value? */ - - if (count > 3) - { - /* Yes.. then show how many times the value repeated */ - - wdinfo("[repeats %d more times]\n", count - 3); - } - - /* Save the new address, value, and count */ - - prevaddr = addr; - preval = val; - count = 1; - } - - /* Show the register value read */ - - wdinfo("%08" PRIx32 "->%04x\n", addr, val); - return val; -} -#endif - -/**************************************************************************** - * Name: stm32_putreg - * - * Description: - * Set the contents of an STM32 register to a value - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_WWDG_REGDEBUG -static void stm32_putreg(uint16_t val, uint32_t addr) -{ - /* Show the register value being written */ - - wdinfo("%08" PRIx32 "<-%04x\n", addr, val); - - /* Write the value */ - - putreg16(val, addr); -} -#endif - -/**************************************************************************** - * Name: stm32_setwindow - * - * Description: - * Set the CFR window value. The window value is compared to the down- - * counter when the counter is updated. The WWDG counter should be updated - * only when the counter is below this window value (and greater than 64) - * otherwise a reset will be generated - * - ****************************************************************************/ - -static void stm32_setwindow(struct stm32_lowerhalf_s *priv, - uint8_t window) -{ - uint16_t regval; - - /* Set W[6:0] bits according to selected window value */ - - regval = stm32_getreg(STM32_WWDG_CFR); - regval &= ~WWDG_CFR_W_MASK; - regval |= window << WWDG_CFR_W_SHIFT; - stm32_putreg(regval, STM32_WWDG_CFR); - - /* Remember the window setting */ - - priv->window = window; -} - -/**************************************************************************** - * Name: stm32_interrupt - * - * Description: - * WWDG early warning interrupt - * - * Input Parameters: - * Usual interrupt handler arguments. - * - * Returned Value: - * Always returns OK. - * - ****************************************************************************/ - -static int stm32_interrupt(int irq, void *context, void *arg) -{ - struct stm32_lowerhalf_s *priv = &g_wdgdev; - uint16_t regval; - - /* Check if the EWI interrupt is really pending */ - - regval = stm32_getreg(STM32_WWDG_SR); - if ((regval & WWDG_SR_EWIF) != 0) - { - /* Is there a registered handler? */ - - if (priv->handler) - { - /* Yes... NOTE: This interrupt service routine (ISR) must reload - * the WWDG counter to prevent the reset. Otherwise, we will reset - * upon return. - */ - - priv->handler(irq, context, arg); - } - - /* The EWI interrupt is cleared by writing '0' to the EWIF bit in the - * WWDG_SR register. - */ - - regval &= ~WWDG_SR_EWIF; - stm32_putreg(regval, STM32_WWDG_SR); - } - - return OK; -} - -/**************************************************************************** - * Name: stm32_start - * - * Description: - * Start the watchdog timer, resetting the time to the current timeout, - * - * Input Parameters: - * lower - A pointer the publicly visible representation of the "lower- - * half" driver state structure. - * - * Returned Value: - * Zero on success; a negated errno value on failure. - * - ****************************************************************************/ - -static int stm32_start(struct watchdog_lowerhalf_s *lower) -{ - struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; - - wdinfo("Entry\n"); - DEBUGASSERT(priv); - - /* The watchdog is always disabled after a reset. It is enabled by setting - * the WDGA bit in the WWDG_CR register, then it cannot be disabled again - * except by a reset. - */ - - stm32_putreg(WWDG_CR_WDGA | WWDG_CR_T_RESET | priv->reload, STM32_WWDG_CR); - priv->started = true; - return OK; -} - -/**************************************************************************** - * Name: stm32_stop - * - * Description: - * Stop the watchdog timer - * - * Input Parameters: - * lower - A pointer the publicly visible representation of the "lower- - * half" driver state structure. - * - * Returned Value: - * Zero on success; a negated errno value on failure. - * - ****************************************************************************/ - -static int stm32_stop(struct watchdog_lowerhalf_s *lower) -{ - /* The watchdog is always disabled after a reset. It is enabled by setting - * the WDGA bit in the WWDG_CR register, then it cannot be disabled again - * except by a reset. - */ - - wdinfo("Entry\n"); - return -ENOSYS; -} - -/**************************************************************************** - * Name: stm32_keepalive - * - * Description: - * Reset the watchdog timer to the current timeout value, prevent any - * imminent watchdog timeouts. This is sometimes referred as "pinging" - * the watchdog timer or "petting the dog". - * - * The application program must write in the WWDG_CR register at regular - * intervals during normal operation to prevent an MCU reset. This - * operation must occur only when the counter value is lower than the - * window register value. The value to be stored in the WWDG_CR register - * must be between 0xff and 0xC0: - * - * Input Parameters: - * lower - A pointer the publicly visible representation of the "lower- - * half" driver state structure. - * - * Returned Value: - * Zero on success; a negated errno value on failure. - * - ****************************************************************************/ - -static int stm32_keepalive(struct watchdog_lowerhalf_s *lower) -{ - struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; - - wdinfo("Entry\n"); - DEBUGASSERT(priv); - - /* Write to T[6:0] bits to configure the counter value, no need to do - * a read-modify-write; writing a 0 to WDGA bit does nothing. - */ - - stm32_putreg((WWDG_CR_T_RESET | priv->reload), STM32_WWDG_CR); - return OK; -} - -/**************************************************************************** - * Name: stm32_getstatus - * - * Description: - * Get the current watchdog timer status - * - * Input Parameters: - * lower - A pointer the publicly visible representation of the "lower- - * half" driver state structure. - * status - The location to return the watchdog status information. - * - * Returned Value: - * Zero on success; a negated errno value on failure. - * - ****************************************************************************/ - -static int stm32_getstatus(struct watchdog_lowerhalf_s *lower, - struct watchdog_status_s *status) -{ - struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; - uint32_t elapsed; - uint16_t reload; - - wdinfo("Entry\n"); - DEBUGASSERT(priv); - - /* Return the status bit */ - - status->flags = WDFLAGS_RESET; - if (priv->started) - { - status->flags |= WDFLAGS_ACTIVE; - } - - if (priv->handler) - { - status->flags |= WDFLAGS_CAPTURE; - } - - /* Return the actual timeout is milliseconds */ - - status->timeout = priv->timeout; - - /* Get the time remaining until the watchdog expires (in milliseconds) */ - - reload = (stm32_getreg(STM32_WWDG_CR) >> WWDG_CR_T_SHIFT) & 0x7f; - elapsed = priv->reload - reload; - status->timeleft = (priv->timeout * elapsed) / (priv->reload + 1); - - wdinfo("Status :\n"); - wdinfo(" flags : %08x\n", (unsigned)status->flags); - wdinfo(" timeout : %u\n", (unsigned)status->timeout); - wdinfo(" timeleft : %u\n", (unsigned)status->flags); - return OK; -} - -/**************************************************************************** - * Name: stm32_settimeout - * - * Description: - * Set a new timeout value (and reset the watchdog timer) - * - * Input Parameters: - * lower - A pointer the publicly visible representation of the - * "lower-half" driver state structure. - * timeout - The new timeout value in milliseconds. - * - * Returned Value: - * Zero on success; a negated errno value on failure. - * - ****************************************************************************/ - -static int stm32_settimeout(struct watchdog_lowerhalf_s *lower, - uint32_t timeout) -{ - struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; - uint32_t fwwdg; - uint32_t reload; - uint16_t regval; - int wdgtb; - - DEBUGASSERT(priv); - wdinfo("Entry: timeout=%u\n", (unsigned)timeout); - - /* Can this timeout be represented? */ - - if (timeout < 1 || timeout > WWDG_MAXTIMEOUT) - { - wderr("ERROR: Cannot represent timeout=%u > %lu\n", - (unsigned)timeout, WWDG_MAXTIMEOUT); - return -ERANGE; - } - - /* Determine prescaler value. - * - * Fwwdg = PCLK1/4096/prescaler. - * - * Where - * Fwwwdg is the frequency of the WWDG clock - * wdgtb is one of {1, 2, 4, or 8} - */ - - /* Select the smallest prescaler that will result in a reload field value - * that is less than the maximum. - */ - - for (wdgtb = 0; ; wdgtb++) - { - /* WDGTB = 0 -> Divider = 1 = 1 << 0 - * WDGTB = 1 -> Divider = 2 = 1 << 1 - * WDGTB = 2 -> Divider = 4 = 1 << 2 - * WDGTB = 3 -> Divider = 8 = 1 << 3 - */ - - /* Get the WWDG counter frequency in Hz. */ - - fwwdg = (STM32_PCLK1_FREQUENCY / 4096) >> wdgtb; - - /* The formula to calculate the timeout value is given by: - * - * timeout = 1000 * (reload + 1) / Fwwdg, OR - * reload = timeout * Fwwdg / 1000 - 1 - * - * Where - * timeout is the desired timeout in milliseconds - * reload is the contents of T{5:0] - * Fwwdg is the frequency of the WWDG clock - */ - - reload = timeout * fwwdg / 1000 - 1; - - /* If this reload valid is less than the maximum or we are not ready - * at the prescaler value, then break out of the loop to use these - * settings. - */ - -#if 0 - wdinfo("wdgtb=%d fwwdg=%d reload=%d timeout=%d\n", - wdgtb, fwwdg, reload, 1000 * (reload + 1) / fwwdg); -#endif - if (reload <= WWDG_CR_T_MAX || wdgtb == 3) - { - /* Note that we explicitly break out of the loop rather than using - * the 'for' loop termination logic because we do not want the - * value of wdgtb to be incremented. - */ - - break; - } - } - - /* Make sure that the final reload value is within range */ - - if (reload > WWDG_CR_T_MAX) - { - reload = WWDG_CR_T_MAX; - } - - /* Calculate and save the actual timeout value in milliseconds: - * - * timeout = 1000 * (reload + 1) / Fwwdg - */ - - priv->timeout = 1000 * (reload + 1) / fwwdg; - - /* Remember the selected values */ - - priv->fwwdg = fwwdg; - priv->reload = reload; - - wdinfo("wdgtb=%d fwwdg=%u reload=%u timeout=%u\n", - wdgtb, (unsigned)fwwdg, (unsigned)reload, (unsigned)priv->timeout); - - /* Set WDGTB[1:0] bits according to calculated value */ - - regval = stm32_getreg(STM32_WWDG_CFR); - regval &= ~WWDG_CFR_WDGTB_MASK; - regval |= (uint16_t)wdgtb << WWDG_CFR_WDGTB_SHIFT; - stm32_putreg(regval, STM32_WWDG_CFR); - - /* Reset the 7-bit window value to the maximum value.. essentially - * disabling the lower limit of the watchdog reset time. - */ - - stm32_setwindow(priv, 0x7f); - return OK; -} - -/**************************************************************************** - * Name: stm32_capture - * - * Description: - * Don't reset on watchdog timer timeout; instead, call this user provider - * timeout handler. NOTE: Providing handler==NULL will restore the reset - * behavior. - * - * Input Parameters: - * lower - A pointer the publicly visible representation of the - * "lower-half" driver state structure. - * newhandler - The new watchdog expiration function pointer. If this - * function pointer is NULL, then the reset-on-expiration - * behavior is restored, - * - * Returned Value: - * The previous watchdog expiration function pointer or NULL is there was - * no previous function pointer, i.e., if the previous behavior was - * reset-on-expiration (NULL is also returned if an error occurs). - * - ****************************************************************************/ - -static xcpt_t stm32_capture(struct watchdog_lowerhalf_s *lower, - xcpt_t handler) -{ - struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; - irqstate_t flags; - xcpt_t oldhandler; - uint16_t regval; - - DEBUGASSERT(priv); - wdinfo("Entry: handler=%p\n", handler); - - /* Get the old handler return value */ - - flags = enter_critical_section(); - oldhandler = priv->handler; - - /* Save the new handler */ - - priv->handler = handler; - - /* Are we attaching or detaching the handler? */ - - regval = stm32_getreg(STM32_WWDG_CFR); - if (handler) - { - /* Attaching... Enable the EWI interrupt */ - - regval |= WWDG_CFR_EWI; - stm32_putreg(regval, STM32_WWDG_CFR); - - up_enable_irq(STM32_IRQ_WWDG); - } - else - { - /* Detaching... Disable the EWI interrupt */ - - regval &= ~WWDG_CFR_EWI; - stm32_putreg(regval, STM32_WWDG_CFR); - - up_disable_irq(STM32_IRQ_WWDG); - } - - leave_critical_section(flags); - return oldhandler; -} - -/**************************************************************************** - * Name: stm32_ioctl - * - * Description: - * Any ioctl commands that are not recognized by the "upper-half" driver - * are forwarded to the lower half driver through this method. - * - * Input Parameters: - * lower - A pointer the publicly visible representation of the "lower- - * half" driver state structure. - * cmd - The ioctl command value - * arg - The optional argument that accompanies the 'cmd'. The - * interpretation of this argument depends on the particular - * command. - * - * Returned Value: - * Zero on success; a negated errno value on failure. - * - ****************************************************************************/ - -static int stm32_ioctl(struct watchdog_lowerhalf_s *lower, int cmd, - unsigned long arg) -{ - struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; - int ret = -ENOTTY; - - DEBUGASSERT(priv); - wdinfo("Entry: cmd=%d arg=%ld\n", cmd, arg); - - /* WDIOC_MINTIME: Set the minimum ping time. If two keepalive ioctls - * are received within this time, a reset event will be generated. - * Argument: A 32-bit time value in milliseconds. - */ - - if (cmd == WDIOC_MINTIME) - { - uint32_t mintime = (uint32_t)arg; - - /* The minimum time should be strictly less than the total delay - * which, in turn, will be less than or equal to WWDG_CR_T_MAX - */ - - ret = -EINVAL; - if (mintime < priv->timeout) - { - uint32_t window = (priv->timeout - mintime) * priv->fwwdg / - 1000 - 1; - DEBUGASSERT(window < priv->reload); - stm32_setwindow(priv, window | WWDG_CR_T_RESET); - ret = OK; - } - } - - return ret; -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_wwdginitialize - * - * Description: - * Initialize the WWDG watchdog timer. The watchdog timer is initialized - * and registers as 'devpath'. The initial state of the watchdog timer is - * disabled. - * - * Input Parameters: - * devpath - The full path to the watchdog. This should be of the form - * /dev/watchdog0 - * - * Returned Value: - * None - * - ****************************************************************************/ - -void stm32_wwdginitialize(const char *devpath) -{ - struct stm32_lowerhalf_s *priv = &g_wdgdev; - - wdinfo("Entry: devpath=%s\n", devpath); - - /* NOTE we assume that clocking to the WWDG has already been provided by - * the RCC initialization logic. - */ - - /* Initialize the driver state structure. Here we assume: (1) the state - * structure lies in .bss and was zeroed at reset time. (2) This function - * is only called once so it is never necessary to re-zero the structure. - */ - - priv->ops = &g_wdgops; - - /* Attach our EWI interrupt handler (But don't enable it yet) */ - - irq_attach(STM32_IRQ_WWDG, stm32_interrupt, NULL); - - /* Select an arbitrary initial timeout value. But don't start the watchdog - * yet. NOTE: If the "Hardware watchdog" feature is enabled through the - * device option bits, the watchdog is automatically enabled at power-on. - */ - - stm32_settimeout((struct watchdog_lowerhalf_s *)priv, - CONFIG_STM32_WWDG_DEFTIMOUT); - - /* Register the watchdog driver as /dev/watchdog0 */ - - watchdog_register(devpath, (struct watchdog_lowerhalf_s *)priv); - - /* When the microcontroller enters debug mode (Cortex-M core halted), - * the WWDG counter either continues to work normally or stops, depending - * on DBG_WWDG_STOP configuration bit in DBG module. - */ - -#if defined(CONFIG_STM32_JTAG_FULL_ENABLE) || \ - defined(CONFIG_STM32_JTAG_NOJNTRST_ENABLE) || \ - defined(CONFIG_STM32_JTAG_SW_ENABLE) - { -#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F30XX) || \ - defined(CONFIG_STM32_STM32F4XXX) || defined(CONFIG_STM32_STM32L15XX) - uint32_t cr = getreg32(STM32_DBGMCU_APB1_FZ); - cr |= DBGMCU_APB1_WWDGSTOP; - putreg32(cr, STM32_DBGMCU_APB1_FZ); -#else /* if defined(CONFIG_STM32_STM32F10XX) */ - uint32_t cr = getreg32(STM32_DBGMCU_CR); - cr |= DBGMCU_CR_WWDGSTOP; - putreg32(cr, STM32_DBGMCU_CR); -#endif - } -#endif -} - -#endif /* CONFIG_WATCHDOG && CONFIG_STM32_WWDG */ diff --git a/arch/arm/src/stm32/stm32f10xxf30xx_flash.c b/arch/arm/src/stm32/stm32f10xxf30xx_flash.c deleted file mode 100644 index a35d47482ba5e..0000000000000 --- a/arch/arm/src/stm32/stm32f10xxf30xx_flash.c +++ /dev/null @@ -1,387 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32f10xxf30xx_flash.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* Provides standard flash access functions, to be used by the flash mtd - * driver. The interface is defined in the include/nuttx/progmem.h - * - * Requirements during write/erase operations on FLASH: - * - HSI must be ON. - * - Low Power Modes are not permitted during write/erase - */ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include -#include - -#include -#include -#include - -#include "stm32_flash.h" -#include "stm32_rcc.h" -#include "stm32_waste.h" -#include "arm_internal.h" - -/* Only for the STM32F[1|3]0xx family. */ - -#if defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F30XX) - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#define FLASH_KEY1 0x45670123 -#define FLASH_KEY2 0xcdef89ab -#define FLASH_OPTKEY1 0x08192a3b -#define FLASH_OPTKEY2 0x4c5d6e7f -#define FLASH_ERASEDVALUE 0xffu - -#if defined(STM32_FLASH_DUAL_BANK) -/* Bank 0 is 512Kb; Bank 1 is up to 512Kb */ - -# define STM32_FLASH_BANK0_NPAGES (512 * 1024 / STM32_FLASH_PAGESIZE) -# define STM32_FLASH_BANK1_NPAGES (STM32_FLASH_NPAGES - STM32_FLASH_BANK0_NPAGES) -#else -/* Bank 0 is up to 512Kb; Bank 1 is not present */ - -# define STM32_FLASH_BANK0_NPAGES STM32_FLASH_NPAGES -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -static mutex_t g_lock = NXMUTEX_INITIALIZER; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -static void flash_unlock(uintptr_t base) -{ - while ((getreg32(base + STM32_FLASH_SR_OFFSET) & FLASH_SR_BSY) != 0) - { - stm32_waste(); - } - - if ((getreg32(base + STM32_FLASH_CR_OFFSET) & FLASH_CR_LOCK) != 0) - { - /* Unlock sequence */ - - putreg32(FLASH_KEY1, base + STM32_FLASH_KEYR_OFFSET); - putreg32(FLASH_KEY2, base + STM32_FLASH_KEYR_OFFSET); - } -} - -static void flash_lock(uintptr_t base) -{ - modifyreg32(base + STM32_FLASH_CR_OFFSET, 0, FLASH_CR_LOCK); -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -int stm32_flash_unlock(void) -{ - int ret; - - ret = nxmutex_lock(&g_lock); - if (ret < 0) - { - return ret; - } - - flash_unlock(STM32_FLASHIF_BASE); -#if defined(STM32_FLASH_DUAL_BANK) - flash_unlock(STM32_FLASHIF1_BASE); -#endif - nxmutex_unlock(&g_lock); - - return ret; -} - -int stm32_flash_lock(void) -{ - int ret; - - ret = nxmutex_lock(&g_lock); - if (ret < 0) - { - return ret; - } - - flash_lock(STM32_FLASHIF_BASE); -#if defined(STM32_FLASH_DUAL_BANK) - flash_lock(STM32_FLASHIF1_BASE); -#endif - nxmutex_unlock(&g_lock); - - return ret; -} - -size_t up_progmem_pagesize(size_t page) -{ - return STM32_FLASH_PAGESIZE; -} - -size_t up_progmem_erasesize(size_t block) -{ - return STM32_FLASH_PAGESIZE; -} - -ssize_t up_progmem_getpage(size_t addr) -{ - if (addr >= STM32_FLASH_BASE) - { - addr -= STM32_FLASH_BASE; - } - - if (addr >= STM32_FLASH_SIZE) - { - return -EFAULT; - } - - return addr / STM32_FLASH_PAGESIZE; -} - -size_t up_progmem_getaddress(size_t page) -{ - if (page >= STM32_FLASH_NPAGES) - { - return SIZE_MAX; - } - - return page * STM32_FLASH_PAGESIZE + STM32_FLASH_BASE; -} - -size_t up_progmem_neraseblocks(void) -{ - return STM32_FLASH_NPAGES; -} - -bool up_progmem_isuniform(void) -{ -#ifdef STM32_FLASH_PAGESIZE - return true; -#else - return false; -#endif -} - -ssize_t up_progmem_ispageerased(size_t page) -{ - size_t addr; - size_t count; - size_t bwritten = 0; - - if (page >= STM32_FLASH_NPAGES) - { - return -EFAULT; - } - - /* Verify */ - - for (addr = up_progmem_getaddress(page), count = up_progmem_pagesize(page); - count; count--, addr++) - { - if (getreg8(addr) != FLASH_ERASEDVALUE) - { - bwritten++; - } - } - - return bwritten; -} - -ssize_t up_progmem_eraseblock(size_t block) -{ - uintptr_t base; - size_t page_address; - int ret; - - if (block >= STM32_FLASH_NPAGES) - { - return -EFAULT; - } - -#if defined(STM32_FLASH_DUAL_BANK) - /* Handle paged FLASH */ - - if (block >= STM32_FLASH_BANK0_NPAGES) - { - base = STM32_FLASHIF1_BASE; - } - else -#endif - { - base = STM32_FLASHIF_BASE; - } - - ret = nxmutex_lock(&g_lock); - if (ret < 0) - { - return (ssize_t)ret; - } - - if ((getreg32(STM32_RCC_CR) & RCC_CR_HSION) == 0) - { - nxmutex_unlock(&g_lock); - return -EPERM; - } - - /* Get flash ready and begin erasing single page */ - - flash_unlock(base); - - modifyreg32(base + STM32_FLASH_CR_OFFSET, 0, FLASH_CR_PER); - - /* Must be valid - page index checked above */ - - page_address = up_progmem_getaddress(block); - putreg32(page_address, base + STM32_FLASH_AR_OFFSET); - - modifyreg32(base + STM32_FLASH_CR_OFFSET, 0, FLASH_CR_STRT); - - while ((getreg32(base + STM32_FLASH_SR_OFFSET) & FLASH_SR_BSY) != 0) - { - stm32_waste(); - } - - modifyreg32(base + STM32_FLASH_CR_OFFSET, FLASH_CR_PER, 0); - nxmutex_unlock(&g_lock); - - /* Verify */ - - if (up_progmem_ispageerased(block) == 0) - { - return up_progmem_erasesize(block); /* success */ - } - else - { - return -EIO; /* failure */ - } -} - -ssize_t up_progmem_write(size_t addr, const void *buf, size_t count) -{ - uintptr_t base; - uint16_t *hword = (uint16_t *)buf; - size_t written = count; - int ret; - - /* STM32 requires half-word access */ - - if (count & 1) - { - return -EINVAL; - } - - /* Check for valid address range */ - - if (addr >= STM32_FLASH_BASE) - { - addr -= STM32_FLASH_BASE; - } - - if ((addr + count) > STM32_FLASH_SIZE) - { - return -EFAULT; - } - -#if defined(STM32_FLASH_DUAL_BANK) - /* Handle paged FLASH */ - - size_t page = addr / STM32_FLASH_PAGESIZE; - - if (page >= STM32_FLASH_BANK0_NPAGES) - { - base = STM32_FLASHIF1_BASE; - } - else -#endif - { - base = STM32_FLASHIF_BASE; - } - - ret = nxmutex_lock(&g_lock); - if (ret < 0) - { - return (ssize_t)ret; - } - - if ((getreg32(STM32_RCC_CR) & RCC_CR_HSION) == 0) - { - nxmutex_unlock(&g_lock); - return -EPERM; - } - - /* Get flash ready and begin flashing */ - - flash_unlock(base); - - modifyreg32(base + STM32_FLASH_CR_OFFSET, 0, FLASH_CR_PG); - - for (addr += STM32_FLASH_BASE; count; count -= 2, hword++, addr += 2) - { - /* Write half-word and wait to complete */ - - putreg16(*hword, addr); - - while ((getreg32(base + STM32_FLASH_SR_OFFSET) & FLASH_SR_BSY) != 0) - { - stm32_waste(); - } - - /* Verify */ - - if ((getreg32(base + STM32_FLASH_SR_OFFSET) & FLASH_SR_WRPRT_ERR) != 0) - { - modifyreg32(base + STM32_FLASH_CR_OFFSET, FLASH_CR_PG, 0); - nxmutex_unlock(&g_lock); - return -EROFS; - } - - if (getreg16(addr) != *hword) - { - modifyreg32(base + STM32_FLASH_CR_OFFSET, FLASH_CR_PG, 0); - nxmutex_unlock(&g_lock); - return -EIO; - } - } - - modifyreg32(base + STM32_FLASH_CR_OFFSET, FLASH_CR_PG, 0); - - nxmutex_unlock(&g_lock); - return written; -} - -uint8_t up_progmem_erasestate(void) -{ - return FLASH_ERASEDVALUE; -} - -#endif /* defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F30XX) */ diff --git a/arch/arm/src/stm32/stm32f20xxf40xx_flash.c b/arch/arm/src/stm32/stm32f20xxf40xx_flash.c deleted file mode 100644 index f8125b7ceb9f8..0000000000000 --- a/arch/arm/src/stm32/stm32f20xxf40xx_flash.c +++ /dev/null @@ -1,452 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32f20xxf40xx_flash.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* Provides standard flash access functions, to be used by the flash mtd - * driver. The interface is defined in the include/nuttx/progmem.h - * - * Requirements during write/erase operations on FLASH: - * - HSI must be ON. - * - Low Power Modes are not permitted during write/erase - */ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include -#include - -#include -#include -#include - -#include "stm32_flash.h" -#include "stm32_rcc.h" -#include "stm32_waste.h" -#include "arm_internal.h" - -/* Only for the STM32F[2|4]0xx family. */ - -#if defined(CONFIG_STM32_STM32F20XX) || defined (CONFIG_STM32_STM32F4XXX) - -#if defined(CONFIG_STM32_FLASH_CONFIG_DEFAULT) -# warning "Default Flash Configuration Used - See Override Flash Size Designator" -#endif - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#define FLASH_KEY1 0x45670123 -#define FLASH_KEY2 0xcdef89ab -#define FLASH_OPTKEY1 0x08192a3b -#define FLASH_OPTKEY2 0x4c5d6e7f -#define FLASH_ERASEDVALUE 0xff - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -static mutex_t g_lock = NXMUTEX_INITIALIZER; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -static void flash_unlock(void) -{ - while (getreg32(STM32_FLASH_SR) & FLASH_SR_BSY) - { - stm32_waste(); - } - - if (getreg32(STM32_FLASH_CR) & FLASH_CR_LOCK) - { - /* Unlock sequence */ - - putreg32(FLASH_KEY1, STM32_FLASH_KEYR); - putreg32(FLASH_KEY2, STM32_FLASH_KEYR); - } -} - -static void flash_lock(void) -{ - modifyreg32(STM32_FLASH_CR, 0, FLASH_CR_LOCK); -} - -#if defined(CONFIG_STM32_FLASH_WORKAROUND_DATA_CACHE_CORRUPTION_ON_RWW) -static void data_cache_disable(void) -{ - modifyreg32(STM32_FLASH_ACR, FLASH_ACR_DCEN, 0); -} - -static void data_cache_enable(void) -{ - /* Reset data cache */ - - modifyreg32(STM32_FLASH_ACR, 0, FLASH_ACR_DCRST); - - /* Enable data cache */ - - modifyreg32(STM32_FLASH_ACR, 0, FLASH_ACR_DCEN); -} -#endif /* defined(CONFIG_STM32_FLASH_WORKAROUND_DATA_CACHE_CORRUPTION_ON_RWW) */ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -int stm32_flash_unlock(void) -{ - int ret; - - ret = nxmutex_lock(&g_lock); - if (ret < 0) - { - return ret; - } - - flash_unlock(); - nxmutex_unlock(&g_lock); - - return ret; -} - -int stm32_flash_lock(void) -{ - int ret; - - ret = nxmutex_lock(&g_lock); - if (ret < 0) - { - return ret; - } - - flash_lock(); - nxmutex_unlock(&g_lock); - - return ret; -} - -/**************************************************************************** - * Name: stm32_flash_writeprotect - * - * Description: - * Enable or disable the write protection of a flash sector. - * - ****************************************************************************/ - -int stm32_flash_writeprotect(size_t page, bool enabled) -{ - uint32_t reg; - uint32_t val; - - if (page >= STM32_FLASH_NPAGES) - { - return -EFAULT; - } - - /* Select the register that contains the bit to be changed */ - - if (page < 12) - { - reg = STM32_FLASH_OPTCR; - } -#if defined(CONFIG_STM32_FLASH_CONFIG_I) - else - { - reg = STM32_FLASH_OPTCR1; - page -= 12; - } -#else - else - { - return -EFAULT; - } -#endif - - /* Read the option status */ - - val = getreg32(reg); - - /* Set or clear the protection */ - - if (enabled) - { - val &= ~(1 << (16 + page)); - } - else - { - val |= (1 << (16 + page)); - } - - /* Unlock options */ - - putreg32(FLASH_OPTKEY1, STM32_FLASH_OPTKEYR); - putreg32(FLASH_OPTKEY2, STM32_FLASH_OPTKEYR); - - /* Write options */ - - putreg32(val, reg); - - /* Trigger programming */ - - modifyreg32(STM32_FLASH_OPTCR, 0, FLASH_OPTCR_OPTSTRT); - - /* Wait for completion */ - - while (getreg32(STM32_FLASH_SR) & FLASH_SR_BSY) - { - stm32_waste(); - } - - /* Relock options */ - - modifyreg32(STM32_FLASH_OPTCR, 0, FLASH_OPTCR_OPTLOCK); - return 0; -} - -size_t up_progmem_pagesize(size_t page) -{ - static const size_t page_sizes[STM32_FLASH_NPAGES] = STM32_FLASH_SIZES; - - if (page >= sizeof(page_sizes) / sizeof(*page_sizes)) - { - return 0; - } - else - { - return page_sizes[page]; - } -} - -size_t up_progmem_erasesize(size_t block) -{ - return up_progmem_pagesize(block); -} - -ssize_t up_progmem_getpage(size_t addr) -{ - size_t page_end = 0; - size_t i; - - if (addr >= STM32_FLASH_BASE) - { - addr -= STM32_FLASH_BASE; - } - - if (addr >= STM32_FLASH_SIZE) - { - return -EFAULT; - } - - for (i = 0; i < STM32_FLASH_NPAGES; ++i) - { - page_end += up_progmem_pagesize(i); - if (page_end > addr) - { - return i; - } - } - - return -EFAULT; -} - -size_t up_progmem_getaddress(size_t page) -{ - size_t base_address = STM32_FLASH_BASE; - size_t i; - - if (page >= STM32_FLASH_NPAGES) - { - return SIZE_MAX; - } - - for (i = 0; i < page; ++i) - { - base_address += up_progmem_pagesize(i); - } - - return base_address; -} - -size_t up_progmem_neraseblocks(void) -{ - return STM32_FLASH_NPAGES; -} - -bool up_progmem_isuniform(void) -{ -#ifdef STM32_FLASH_PAGESIZE - return true; -#else - return false; -#endif -} - -ssize_t up_progmem_ispageerased(size_t page) -{ - size_t addr; - size_t count; - size_t bwritten = 0; - - if (page >= STM32_FLASH_NPAGES) - { - return -EFAULT; - } - - /* Verify */ - - for (addr = up_progmem_getaddress(page), count = up_progmem_pagesize(page); - count; count--, addr++) - { - if (getreg8(addr) != FLASH_ERASEDVALUE) - { - bwritten++; - } - } - - return bwritten; -} - -ssize_t up_progmem_eraseblock(size_t block) -{ - if (block >= STM32_FLASH_NPAGES) - { - return -EFAULT; - } - - nxmutex_lock(&g_lock); - - /* Get flash ready and begin erasing single block */ - - flash_unlock(); - - modifyreg32(STM32_FLASH_CR, 0, FLASH_CR_SER); - modifyreg32(STM32_FLASH_CR, FLASH_CR_SNB_MASK, FLASH_CR_SNB(block)); - modifyreg32(STM32_FLASH_CR, 0, FLASH_CR_STRT); - - while (getreg32(STM32_FLASH_SR) & FLASH_SR_BSY) - { - stm32_waste(); - } - - modifyreg32(STM32_FLASH_CR, FLASH_CR_SER, 0); - nxmutex_unlock(&g_lock); - - /* Verify */ - - if (up_progmem_ispageerased(block) == 0) - { - return up_progmem_pagesize(block); /* success */ - } - else - { - return -EIO; /* failure */ - } -} - -ssize_t up_progmem_write(size_t addr, const void *buf, size_t count) -{ - uint16_t *hword = (uint16_t *)buf; - size_t written = count; - - /* STM32 requires half-word access */ - - if (count & 1) - { - return -EINVAL; - } - - /* Check for valid address range */ - - if (addr >= STM32_FLASH_BASE) - { - addr -= STM32_FLASH_BASE; - } - - if ((addr + count) > STM32_FLASH_SIZE) - { - return -EFAULT; - } - - nxmutex_lock(&g_lock); - - /* Get flash ready and begin flashing */ - - flash_unlock(); - -#if defined(CONFIG_STM32_FLASH_WORKAROUND_DATA_CACHE_CORRUPTION_ON_RWW) - data_cache_disable(); -#endif - - modifyreg32(STM32_FLASH_CR, 0, FLASH_CR_PG); - - /* TODO: implement up_progmem_write() to support other sizes than 16-bits */ - - modifyreg32(STM32_FLASH_CR, FLASH_CR_PSIZE_MASK, FLASH_CR_PSIZE_X16); - - for (addr += STM32_FLASH_BASE; count; count -= 2, hword++, addr += 2) - { - /* Write half-word and wait to complete */ - - putreg16(*hword, addr); - - while (getreg32(STM32_FLASH_SR) & FLASH_SR_BSY) - { - stm32_waste(); - } - - /* Verify */ - - if (getreg32(STM32_FLASH_SR) & FLASH_CR_SER) - { - modifyreg32(STM32_FLASH_CR, FLASH_CR_PG, 0); - nxmutex_unlock(&g_lock); - return -EROFS; - } - - if (getreg16(addr) != *hword) - { - modifyreg32(STM32_FLASH_CR, FLASH_CR_PG, 0); - nxmutex_unlock(&g_lock); - return -EIO; - } - } - - modifyreg32(STM32_FLASH_CR, FLASH_CR_PG, 0); - -#if defined(CONFIG_STM32_FLASH_WORKAROUND_DATA_CACHE_CORRUPTION_ON_RWW) - data_cache_enable(); -#endif - - nxmutex_unlock(&g_lock); - return written; -} - -uint8_t up_progmem_erasestate(void) -{ - return FLASH_ERASEDVALUE; -} - -#endif /* defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) */ diff --git a/arch/arm/src/stm32/stm32f40xxx_i2c.c b/arch/arm/src/stm32/stm32f40xxx_i2c.c deleted file mode 100644 index 58b769fc5d96a..0000000000000 --- a/arch/arm/src/stm32/stm32f40xxx_i2c.c +++ /dev/null @@ -1,2694 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32f40xxx_i2c.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* Supports: - * - Master operation, 100 kHz (standard) and 400 kHz (full speed) - * - Multiple instances (shared bus) - * - Interrupt based operation - * - * Structure naming: - * - Device: structure as defined by the nuttx/i2c/i2c.h - * - Instance: represents each individual access to the I2C driver, obtained - * by the i2c_init(); it extends the Device structure from the - * nuttx/i2c/i2c.h; - * Instance points to OPS, to common I2C Hardware private data and - * contains its own private data, as frequency, address, mode of - * operation (in the future) - * - Private: Private data of an I2C Hardware - * - * TODO - * - Check for all possible deadlocks (as BUSY='1' I2C needs to be reset in - * HW using the I2C_CR1_SWRST) - * - SMBus support (hardware layer timings are already supported) and add - * SMBA gpio pin - * - Slave support with multiple addresses (on multiple instances): - * - 2 x 7-bit address or - * - 1 x 10 bit addresses + 1 x 7 bit address (?) - * - plus the broadcast address (general call) - * - Multi-master support - * - Be ready for IPMI - */ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include - -#include - -#include "arm_internal.h" -#include "stm32_rcc.h" -#include "stm32_i2c.h" -#include "stm32_waste.h" -#include "stm32_dma.h" - -/* At least one I2C peripheral must be enabled */ - -#if defined(CONFIG_STM32_I2C1) || defined(CONFIG_STM32_I2C2) || \ - defined(CONFIG_STM32_I2C3) - -/* This implementation is for the STM32 F1, F2, and F4 only. - * Experimentally enabled for STM32L15XX. - */ - -#if defined(CONFIG_STM32_STM32L15XX) || defined(CONFIG_STM32_STM32F10XX) || \ - defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#if STM32_PCLK1_FREQUENCY < 4000000 -# warning STM32_I2C: Peripheral clock must be at least 4 MHz to support 400 kHz operation. -#endif - -#if STM32_PCLK1_FREQUENCY < 2000000 -# error STM32_I2C: Peripheral clock must be at least 2 MHz to support 100 kHz operation. -#endif - -/* Configuration ************************************************************/ - -/* CONFIG_I2C_POLLED may be set so that I2C interrupts will not be used. - * Instead, CPU-intensive polling will be used. - */ - -/* Interrupt wait timeout in seconds and milliseconds */ - -#if !defined(CONFIG_STM32_I2CTIMEOSEC) && !defined(CONFIG_STM32_I2CTIMEOMS) -# define CONFIG_STM32_I2CTIMEOSEC 0 -# define CONFIG_STM32_I2CTIMEOMS 500 /* Default is 500 milliseconds */ -#elif !defined(CONFIG_STM32_I2CTIMEOSEC) -# define CONFIG_STM32_I2CTIMEOSEC 0 /* User provided milliseconds */ -#elif !defined(CONFIG_STM32_I2CTIMEOMS) -# define CONFIG_STM32_I2CTIMEOMS 0 /* User provided seconds */ -#endif - -/* Interrupt wait time timeout in system timer ticks */ - -#ifndef CONFIG_STM32_I2CTIMEOTICKS -# define CONFIG_STM32_I2CTIMEOTICKS \ - (SEC2TICK(CONFIG_STM32_I2CTIMEOSEC) + MSEC2TICK(CONFIG_STM32_I2CTIMEOMS)) -#endif - -#ifndef CONFIG_STM32_I2C_DYNTIMEO_STARTSTOP -# define CONFIG_STM32_I2C_DYNTIMEO_STARTSTOP TICK2USEC(CONFIG_STM32_I2CTIMEOTICKS) -#endif - -/* On the STM32F103ZE, there is an internal conflict between I2C1 and FSMC. - * In that case, it is necessary to disable FSMC before each I2C1 access and - * re-enable FSMC when the I2C access completes. - */ - -#undef I2C1_FSMC_CONFLICT -#if defined(CONFIG_STM32_STM32F10XX) && defined(CONFIG_STM32_FSMC) && defined(CONFIG_STM32_I2C1) -# define I2C1_FSMC_CONFLICT -#endif - -/* Macros to convert a I2C pin to a GPIO output */ - -#if defined(CONFIG_STM32_STM32L15XX) -# define I2C_OUTPUT (GPIO_OUTPUT | GPIO_OUTPUT_SET | GPIO_OPENDRAIN | \ - GPIO_SPEED_40MHz) -#elif defined(CONFIG_STM32_STM32F10XX) -# define I2C_OUTPUT (GPIO_OUTPUT | GPIO_OUTPUT_SET | GPIO_CNF_OUTOD | \ - GPIO_MODE_50MHz) -#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) -# define I2C_OUTPUT (GPIO_OUTPUT | GPIO_FLOAT | GPIO_OPENDRAIN |\ - GPIO_SPEED_50MHz | GPIO_OUTPUT_SET) -#endif - -#define MKI2C_OUTPUT(p) (((p) & (GPIO_PORT_MASK | GPIO_PIN_MASK)) | I2C_OUTPUT) - -/* I2C DMA priority */ - -#ifdef CONFIG_STM32_I2C_DMA - -# if defined(CONFIG_I2C_DMAPRIO) -# if (CONFIG_I2C_DMAPRIO & ~DMA_SCR_PL_MASK) != 0 -# error "Illegal value for CONFIG_I2C_DMAPRIO" -# endif -# define I2C_DMA_PRIO CONFIG_I2C_DMAPRIO -# else -# define I2C_DMA_PRIO DMA_SCR_PRIMED -# endif - -#endif - -/* Debug ********************************************************************/ - -/* I2C event trace logic. NOTE: trace uses the internal, non-standard, - * low-level debug interface syslog() but does not require that any other - * debug is enabled. - */ - -#ifndef CONFIG_I2C_TRACE -# define stm32_i2c_tracereset(p) -# define stm32_i2c_tracenew(p,s) -# define stm32_i2c_traceevent(p,e,a) -# define stm32_i2c_tracedump(p) -#endif - -#ifndef CONFIG_I2C_NTRACE -# define CONFIG_I2C_NTRACE 32 -#endif - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/* Interrupt state */ - -enum stm32_intstate_e -{ - INTSTATE_IDLE = 0, /* No I2C activity */ - INTSTATE_WAITING, /* Waiting for completion of interrupt activity */ - INTSTATE_DONE, /* Interrupt activity complete */ -}; - -/* Trace events */ - -enum stm32_trace_e -{ - I2CEVENT_NONE = 0, - I2CEVENT_STATE_ERROR, - I2CEVENT_ISR_SHUTDOWN, - I2CEVENT_ISR_CALL, - I2CEVENT_ISR_EMPTY_CALL, - I2CEVENT_MSG_HANDLING, - I2CEVENT_POLL_NOT_READY, - I2CEVENT_EMPTY_MSG, - I2CEVENT_START, - I2CEVENT_SENDADDR, - I2CEVENT_ADDRESS_ACKED, - I2CEVENT_ADDRESS_NACKED, - I2CEVENT_NACK, - I2CEVENT_READ, - I2CEVENT_READ_ERROR, - I2CEVENT_ADDRESS_ACKED_READ_1, - I2CEVENT_ADDRESS_ACKED_READ_2, - I2CEVENT_WRITE_TO_DR, - I2CEVENT_WRITE_STOP, - I2CEVENT_WRITE_RESTART, - I2CEVENT_WRITE_NO_RESTART, - I2CEVENT_WRITE_ERROR, - I2CEVENT_WRITE_FLAG_ERROR, - I2CEVENT_TC_RESTART, - I2CEVENT_TC_NO_RESTART, - I2CEVENT_ERROR -}; - -/* Trace data */ - -struct stm32_trace_s -{ - uint32_t status; /* I2C 32-bit SR2|SR1 status */ - uint32_t count; /* Interrupt count when status change */ - enum stm32_intstate_e event; /* Last event that occurred with this status */ - uint32_t parm; /* Parameter associated with the event */ - clock_t time; /* First of event or first status */ -}; - -/* I2C Device hardware configuration */ - -struct stm32_i2c_config_s -{ - uint32_t base; /* I2C base address */ - uint32_t clk_bit; /* Clock enable bit */ - uint32_t reset_bit; /* Reset bit */ - uint32_t scl_pin; /* GPIO configuration for SCL as SCL */ - uint32_t sda_pin; /* GPIO configuration for SDA as SDA */ -#ifndef CONFIG_I2C_POLLED - uint32_t ev_irq; /* Event IRQ */ - uint32_t er_irq; /* Error IRQ */ -#endif -}; - -/* I2C Device Private Data */ - -struct stm32_i2c_priv_s -{ - /* Standard I2C operations */ - - const struct i2c_ops_s *ops; - - /* Port configuration */ - - const struct stm32_i2c_config_s *config; - - int refs; /* Reference count */ - mutex_t lock; /* Mutual exclusion mutex */ -#ifndef CONFIG_I2C_POLLED - sem_t sem_isr; /* Interrupt wait semaphore */ -#endif - volatile uint8_t intstate; /* Interrupt handshake (see enum stm32_intstate_e) */ - - uint8_t msgc; /* Message count */ - struct i2c_msg_s *msgv; /* Message list */ - uint8_t *ptr; /* Current message buffer */ - uint32_t frequency; /* Current I2C frequency */ - volatile int dcnt; /* Current message length */ - uint16_t flags; /* Current message flags */ - bool check_addr_ack; /* Flag to signal if on next interrupt address has ACKed */ - - /* I2C trace support */ - -#ifdef CONFIG_I2C_TRACE - int tndx; /* Trace array index */ - clock_t start_time; /* Time when the trace was started */ - - /* The actual trace data */ - - struct stm32_trace_s trace[CONFIG_I2C_NTRACE]; -#endif - - uint32_t status; /* End of transfer SR2|SR1 status */ - - /* I2C DMA support */ - -#ifdef CONFIG_STM32_I2C_DMA - DMA_HANDLE txdma; /* TX DMA handle */ - DMA_HANDLE rxdma; /* RX DMA handle */ - uint8_t txch; /* TX DMA channel */ - uint8_t rxch; /* RX DMA channel */ -#endif -}; - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -static inline uint16_t stm32_i2c_getreg(struct stm32_i2c_priv_s *priv, - uint8_t offset); -static inline void stm32_i2c_putreg(struct stm32_i2c_priv_s *priv, - uint8_t offset, uint16_t value); -static inline void stm32_i2c_modifyreg(struct stm32_i2c_priv_s *priv, - uint8_t offset, uint16_t clearbits, - uint16_t setbits); - -#ifdef CONFIG_STM32_I2C_DYNTIMEO -static uint32_t stm32_i2c_toticks(int msgc, struct i2c_msg_s *msgs); -#endif /* CONFIG_STM32_I2C_DYNTIMEO */ - -static inline int stm32_i2c_sem_waitdone(struct stm32_i2c_priv_s *priv); -static inline void stm32_i2c_sem_waitstop(struct stm32_i2c_priv_s *priv); - -#ifdef CONFIG_I2C_TRACE -static void stm32_i2c_tracereset(struct stm32_i2c_priv_s *priv); -static void stm32_i2c_tracenew(struct stm32_i2c_priv_s *priv, - uint32_t status); -static void stm32_i2c_traceevent(struct stm32_i2c_priv_s *priv, - enum stm32_trace_e event, uint32_t parm); -static void stm32_i2c_tracedump(struct stm32_i2c_priv_s *priv); -#endif /* CONFIG_I2C_TRACE */ - -static void stm32_i2c_setclock(struct stm32_i2c_priv_s *priv, - uint32_t frequency); -static inline void stm32_i2c_sendstart(struct stm32_i2c_priv_s *priv); -static inline void stm32_i2c_clrstart(struct stm32_i2c_priv_s *priv); -static inline void stm32_i2c_sendstop(struct stm32_i2c_priv_s *priv); -static inline -uint32_t stm32_i2c_getstatus(struct stm32_i2c_priv_s *priv); - -#ifdef I2C1_FSMC_CONFLICT -static inline -uint32_t stm32_i2c_disablefsmc(struct stm32_i2c_priv_s *priv); -static inline void stm32_i2c_enablefsmc(uint32_t ahbenr); -#endif /* I2C1_FSMC_CONFLICT */ - -static int stm32_i2c_isr_process(struct stm32_i2c_priv_s *priv); - -#ifndef CONFIG_I2C_POLLED -static int stm32_i2c_isr(int irq, void *context, void *arg); -#endif /* !CONFIG_I2C_POLLED */ - -static int stm32_i2c_init(struct stm32_i2c_priv_s *priv); -static int stm32_i2c_deinit(struct stm32_i2c_priv_s *priv); -static int stm32_i2c_transfer(struct i2c_master_s *dev, - struct i2c_msg_s *msgs, int count); -#ifdef CONFIG_I2C_RESET -static int stm32_i2c_reset(struct i2c_master_s *dev); -#endif - -/* DMA support */ - -#ifdef CONFIG_STM32_I2C_DMA -static void stm32_i2c_dmarxcallback(DMA_HANDLE handle, - uint8_t status, void *arg); -static void stm32_i2c_dmatxcallback(DMA_HANDLE handle, - uint8_t status, void *arg); -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* I2C interface */ - -static const struct i2c_ops_s stm32_i2c_ops = -{ - .transfer = stm32_i2c_transfer -#ifdef CONFIG_I2C_RESET - , .reset = stm32_i2c_reset -#endif -}; - -/* I2C device structures */ - -#ifdef CONFIG_STM32_I2C1 -static const struct stm32_i2c_config_s stm32_i2c1_config = -{ - .base = STM32_I2C1_BASE, - .clk_bit = RCC_APB1ENR_I2C1EN, - .reset_bit = RCC_APB1RSTR_I2C1RST, - .scl_pin = GPIO_I2C1_SCL, - .sda_pin = GPIO_I2C1_SDA, -#ifndef CONFIG_I2C_POLLED - .ev_irq = STM32_IRQ_I2C1EV, - .er_irq = STM32_IRQ_I2C1ER -#endif -}; - -static struct stm32_i2c_priv_s stm32_i2c1_priv = -{ - .ops = &stm32_i2c_ops, - .config = &stm32_i2c1_config, - .refs = 0, - .lock = NXMUTEX_INITIALIZER, -#ifndef CONFIG_I2C_POLLED - .sem_isr = SEM_INITIALIZER(0), -#endif - .intstate = INTSTATE_IDLE, - .msgc = 0, - .msgv = NULL, - .ptr = NULL, - .dcnt = 0, - .flags = 0, - .status = 0, -#ifdef CONFIG_STM32_I2C_DMA -# ifndef CONFIG_STM32_DMA1 -# error "I2C1 enabled with DMA but corresponding DMA controller 1 is not enabled!" -# endif - /* TODO: ch for i2c 1 and 2 could be *X_2 based on stream priority */ - - .rxch = DMAMAP_I2C1_RX, - .txch = DMAMAP_I2C1_TX, -#endif -}; -#endif - -#ifdef CONFIG_STM32_I2C2 -static const struct stm32_i2c_config_s stm32_i2c2_config = -{ - .base = STM32_I2C2_BASE, - .clk_bit = RCC_APB1ENR_I2C2EN, - .reset_bit = RCC_APB1RSTR_I2C2RST, - .scl_pin = GPIO_I2C2_SCL, - .sda_pin = GPIO_I2C2_SDA, -# ifndef CONFIG_I2C_POLLED - .ev_irq = STM32_IRQ_I2C2EV, - .er_irq = STM32_IRQ_I2C2ER -# endif -}; - -static struct stm32_i2c_priv_s stm32_i2c2_priv = -{ - .ops = &stm32_i2c_ops, - .config = &stm32_i2c2_config, - .refs = 0, - .lock = NXMUTEX_INITIALIZER, -# ifndef CONFIG_I2C_POLLED - .sem_isr = SEM_INITIALIZER(0), -# endif - .intstate = INTSTATE_IDLE, - .msgc = 0, - .msgv = NULL, - .ptr = NULL, - .dcnt = 0, - .flags = 0, - .status = 0, -# ifdef CONFIG_STM32_I2C_DMA -# ifndef CONFIG_STM32_DMA1 -# error "I2C2 enabled with DMA but corresponding DMA controller 1 is not enabled!" -# endif - .rxch = DMAMAP_I2C2_RX, - .txch = DMAMAP_I2C2_TX, -# endif -}; -#endif - -#ifdef CONFIG_STM32_I2C3 -static const struct stm32_i2c_config_s stm32_i2c3_config = -{ - .base = STM32_I2C3_BASE, - .clk_bit = RCC_APB1ENR_I2C3EN, - .reset_bit = RCC_APB1RSTR_I2C3RST, - .scl_pin = GPIO_I2C3_SCL, - .sda_pin = GPIO_I2C3_SDA, -# ifndef CONFIG_I2C_POLLED - .ev_irq = STM32_IRQ_I2C3EV, - .er_irq = STM32_IRQ_I2C3ER -# endif -}; - -static struct stm32_i2c_priv_s stm32_i2c3_priv = -{ - .ops = &stm32_i2c_ops, - .config = &stm32_i2c3_config, - .refs = 0, - .lock = NXMUTEX_INITIALIZER, -# ifndef CONFIG_I2C_POLLED - .sem_isr = SEM_INITIALIZER(0), -# endif - .intstate = INTSTATE_IDLE, - .msgc = 0, - .msgv = NULL, - .ptr = NULL, - .dcnt = 0, - .flags = 0, - .status = 0, -# ifdef CONFIG_STM32_I2C_DMA -# ifndef CONFIG_STM32_DMA1 -# error "I2C3 enabled with DMA but corresponding DMA controller 1 is not enabled!" -# endif - .rxch = DMAMAP_I2C3_RX, - .txch = DMAMAP_I2C3_TX, -# endif -}; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_i2c_getreg - * - * Description: - * Get a 16-bit register value by offset - * - ****************************************************************************/ - -static inline uint16_t stm32_i2c_getreg(struct stm32_i2c_priv_s *priv, - uint8_t offset) -{ - return getreg16(priv->config->base + offset); -} - -/**************************************************************************** - * Name: stm32_i2c_putreg - * - * Description: - * Put a 16-bit register value by offset - * - ****************************************************************************/ - -static inline void stm32_i2c_putreg(struct stm32_i2c_priv_s *priv, - uint8_t offset, uint16_t value) -{ - putreg16(value, priv->config->base + offset); -} - -/**************************************************************************** - * Name: stm32_i2c_modifyreg - * - * Description: - * Modify a 16-bit register value by offset - * - ****************************************************************************/ - -static inline void stm32_i2c_modifyreg(struct stm32_i2c_priv_s *priv, - uint8_t offset, uint16_t clearbits, - uint16_t setbits) -{ - modifyreg16(priv->config->base + offset, clearbits, setbits); -} - -/**************************************************************************** - * Name: stm32_i2c_toticks - * - * Description: - * Return a micro-second delay based on the number of bytes left to be - * processed. - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_I2C_DYNTIMEO -static uint32_t stm32_i2c_toticks(int msgc, struct i2c_msg_s *msgs) -{ - size_t bytecount = 0; - int i; - - /* Count the number of bytes left to process */ - - for (i = 0; i < msgc; i++) - { - bytecount += msgs[i].length; - } - - /* Then return a number of microseconds based on a user provided scaling - * factor. - */ - - return USEC2TICK(CONFIG_STM32_I2C_DYNTIMEO_USECPERBYTE * bytecount); -} -#endif - -/**************************************************************************** - * Name: stm32_i2c_sem_waitdone - * - * Description: - * Wait for a transfer to complete - * - ****************************************************************************/ - -#ifndef CONFIG_I2C_POLLED -static inline int stm32_i2c_sem_waitdone(struct stm32_i2c_priv_s *priv) -{ - irqstate_t flags; - uint32_t regval; - int ret; - - flags = enter_critical_section(); - - /* Enable I2C interrupts */ - - regval = stm32_i2c_getreg(priv, STM32_I2C_CR2_OFFSET); - regval |= (I2C_CR2_ITERREN | I2C_CR2_ITEVFEN); - stm32_i2c_putreg(priv, STM32_I2C_CR2_OFFSET, regval); - - /* Signal the interrupt handler that we are waiting. NOTE: Interrupts - * are currently disabled but will be temporarily re-enabled below when - * nxsem_tickwait_uninterruptible() sleeps. - */ - - priv->intstate = INTSTATE_WAITING; - do - { - /* Wait until either the transfer is complete or the timeout expires */ - -#ifdef CONFIG_STM32_I2C_DYNTIMEO - ret = nxsem_tickwait_uninterruptible(&priv->sem_isr, - stm32_i2c_toticks(priv->msgc, priv->msgv)); -#else - ret = nxsem_tickwait_uninterruptible(&priv->sem_isr, - CONFIG_STM32_I2CTIMEOTICKS); -#endif - if (ret < 0) - { - /* Break out of the loop on irrecoverable errors. This would - * include timeouts and mystery errors reported by - * nxsem_tickwait_uninterruptible. - */ - - break; - } - } - - /* Loop until the interrupt level transfer is complete. */ - - while (priv->intstate != INTSTATE_DONE); - - /* Set the interrupt state back to IDLE */ - - priv->intstate = INTSTATE_IDLE; - - /* Disable I2C interrupts */ - - regval = stm32_i2c_getreg(priv, STM32_I2C_CR2_OFFSET); - regval &= ~I2C_CR2_ALLINTS; - stm32_i2c_putreg(priv, STM32_I2C_CR2_OFFSET, regval); - - leave_critical_section(flags); - return ret; -} -#else -static inline int stm32_i2c_sem_waitdone(struct stm32_i2c_priv_s *priv) -{ - clock_t timeout; - clock_t start; - clock_t elapsed; - int ret; - - /* Get the timeout value */ - -#ifdef CONFIG_STM32_I2C_DYNTIMEO - timeout = stm32_i2c_toticks(priv->msgc, priv->msgv); -#else - timeout = CONFIG_STM32_I2CTIMEOTICKS; -#endif - - /* Signal the interrupt handler that we are waiting. NOTE: Interrupts - * are currently disabled but will be temporarily re-enabled below when - * nxsem_tickwait_uninterruptible() sleeps. - */ - - priv->intstate = INTSTATE_WAITING; - start = clock_systime_ticks(); - - do - { - /* Calculate the elapsed time */ - - elapsed = clock_systime_ticks() - start; - - /* Poll by simply calling the timer interrupt handler until it - * reports that it is done. - */ - - stm32_i2c_isr_process(priv); - } - - /* Loop until the transfer is complete. */ - - while (priv->intstate != INTSTATE_DONE && elapsed < timeout); - - i2cinfo("intstate: %d elapsed: %ld threshold: %ld status: %08" PRIx32 "\n", - priv->intstate, (long)elapsed, (long)timeout, priv->status); - - /* Set the interrupt state back to IDLE */ - - ret = priv->intstate == INTSTATE_DONE ? OK : -ETIMEDOUT; - priv->intstate = INTSTATE_IDLE; - return ret; -} -#endif - -/**************************************************************************** - * Name: stm32_i2c_sem_waitstop - * - * Description: - * Wait for a STOP to complete - * - ****************************************************************************/ - -static inline void stm32_i2c_sem_waitstop(struct stm32_i2c_priv_s *priv) -{ - clock_t start; - clock_t elapsed; - clock_t timeout; - uint32_t cr1; - uint32_t sr1; - - /* Select a timeout */ - -#ifdef CONFIG_STM32_I2C_DYNTIMEO - timeout = USEC2TICK(CONFIG_STM32_I2C_DYNTIMEO_STARTSTOP); -#else - timeout = CONFIG_STM32_I2CTIMEOTICKS; -#endif - - /* Wait as stop might still be in progress; but stop might also - * be set because of a timeout error: "The [STOP] bit is set and - * cleared by software, cleared by hardware when a Stop condition is - * detected, set by hardware when a timeout error is detected." - */ - - start = clock_systime_ticks(); - do - { - /* Calculate the elapsed time */ - - elapsed = clock_systime_ticks() - start; - - /* Check for STOP condition */ - - cr1 = stm32_i2c_getreg(priv, STM32_I2C_CR1_OFFSET); - if ((cr1 & I2C_CR1_STOP) == 0) - { - return; - } - - /* Check for timeout error */ - - sr1 = stm32_i2c_getreg(priv, STM32_I2C_SR1_OFFSET); - if ((sr1 & I2C_SR1_TIMEOUT) != 0) - { - return; - } - } - - /* Loop until the stop is complete or a timeout occurs. */ - - while (elapsed < timeout); - - /* If we get here then a timeout occurred with the STOP condition - * still pending. - */ - - i2cinfo("Timeout with CR1: %04" PRIx32 " SR1: %04" PRIx32 "\n", cr1, sr1); -} - -/**************************************************************************** - * Name: stm32_i2c_trace* - * - * Description: - * I2C trace instrumentation - * - ****************************************************************************/ - -#ifdef CONFIG_I2C_TRACE -static void stm32_i2c_traceclear(struct stm32_i2c_priv_s *priv) -{ - struct stm32_trace_s *trace = &priv->trace[priv->tndx]; - - trace->status = 0; /* I2C 32-bit SR2|SR1 status */ - trace->count = 0; /* Interrupt count when status change */ - trace->event = I2CEVENT_NONE; /* Last event that occurred with this status */ - trace->parm = 0; /* Parameter associated with the event */ - trace->time = 0; /* Time of first status or event */ -} - -static void stm32_i2c_tracereset(struct stm32_i2c_priv_s *priv) -{ - /* Reset the trace info for a new data collection */ - - priv->tndx = 0; - priv->start_time = clock_systime_ticks(); - stm32_i2c_traceclear(priv); -} - -static void stm32_i2c_tracenew(struct stm32_i2c_priv_s *priv, - uint32_t status) -{ - struct stm32_trace_s *trace = &priv->trace[priv->tndx]; - - /* Is the current entry uninitialized? Has the status changed? */ - - if (trace->count == 0 || status != trace->status) - { - /* Yes.. Was it the status changed? */ - - if (trace->count != 0) - { - /* Yes.. bump up the trace index - * (unless we are out of trace entries) - */ - - if (priv->tndx >= (CONFIG_I2C_NTRACE - 1)) - { - i2cerr("ERROR: Trace table overflow\n"); - return; - } - - priv->tndx++; - trace = &priv->trace[priv->tndx]; - } - - /* Initialize the new trace entry */ - - stm32_i2c_traceclear(priv); - trace->status = status; - trace->count = 1; - trace->time = clock_systime_ticks(); - } - else - { - /* Just increment the count of times that we have seen this status */ - - trace->count++; - } -} - -static void stm32_i2c_traceevent(struct stm32_i2c_priv_s *priv, - enum stm32_trace_e event, uint32_t parm) -{ - struct stm32_trace_s *trace; - - if (event != I2CEVENT_NONE) - { - trace = &priv->trace[priv->tndx]; - - /* Initialize the new trace entry */ - - trace->event = event; - trace->parm = parm; - - /* Bump up the trace index (unless we are out of trace entries) */ - - if (priv->tndx >= (CONFIG_I2C_NTRACE - 1)) - { - i2cerr("ERROR: Trace table overflow\n"); - return; - } - - priv->tndx++; - stm32_i2c_traceclear(priv); - } -} - -static void stm32_i2c_tracedump(struct stm32_i2c_priv_s *priv) -{ - struct stm32_trace_s *trace; - int i; - - syslog(LOG_DEBUG, "Elapsed time: %ld\n", - (long)(clock_systime_ticks() - priv->start_time)); - - for (i = 0; i < priv->tndx; i++) - { - trace = &priv->trace[i]; - syslog(LOG_DEBUG, - "%2d. STATUS: %08" PRIx32 " COUNT: %3d EVENT: %2d" - " PARM: %08" PRIx32 " TIME: %d\n", - i + 1, trace->status, trace->count, trace->event, trace->parm, - (int)(trace->time - priv->start_time)); - } -} -#endif /* CONFIG_I2C_TRACE */ - -/**************************************************************************** - * Name: stm32_i2c_setclock - * - * Description: - * Set the I2C clock - * - ****************************************************************************/ - -static void stm32_i2c_setclock(struct stm32_i2c_priv_s *priv, - uint32_t frequency) -{ - uint16_t cr1; - uint16_t ccr; - uint16_t trise; - uint16_t freqmhz; - uint16_t speed; - - /* Has the I2C bus frequency changed? */ - - if (frequency != priv->frequency) - { - /* Disable the selected I2C peripheral to configure TRISE */ - - cr1 = stm32_i2c_getreg(priv, STM32_I2C_CR1_OFFSET); - stm32_i2c_putreg(priv, STM32_I2C_CR1_OFFSET, cr1 & ~I2C_CR1_PE); - - /* Update timing and control registers */ - - freqmhz = (uint16_t)(STM32_PCLK1_FREQUENCY / 1000000); - ccr = 0; - - /* Configure speed in standard mode */ - - if (frequency <= 100000) - { - /* Standard mode speed calculation */ - - speed = (uint16_t)(STM32_PCLK1_FREQUENCY / (frequency << 1)); - - /* The CCR fault must be >= 4 */ - - if (speed < 4) - { - /* Set the minimum allowed value */ - - speed = 4; - } - - ccr |= speed; - - /* Set Maximum Rise Time for standard mode */ - - trise = freqmhz + 1; - } - - /* Configure speed in fast mode */ - - else /* (frequency <= 400000) */ - { - /* Fast mode speed calculation with Tlow/Thigh = 16/9 */ - -#ifdef CONFIG_STM32_I2C_DUTY16_9 - speed = (uint16_t)(STM32_PCLK1_FREQUENCY / (frequency * 25)); - - /* Set DUTY and fast speed bits */ - - ccr |= (I2C_CCR_DUTY | I2C_CCR_FS); -#else - /* Fast mode speed calculation with Tlow/Thigh = 2 */ - - speed = (uint16_t)(STM32_PCLK1_FREQUENCY / (frequency * 3)); - - /* Set fast speed bit */ - - ccr |= I2C_CCR_FS; -#endif - - /* Verify that the CCR speed value is nonzero */ - - if (speed < 1) - { - /* Set the minimum allowed value */ - - speed = 1; - } - - ccr |= speed; - - /* Set Maximum Rise Time for fast mode */ - - trise = (uint16_t)(((freqmhz * 300) / 1000) + 1); - } - - /* Write the new values of the CCR and TRISE registers */ - - stm32_i2c_putreg(priv, STM32_I2C_CCR_OFFSET, ccr); - stm32_i2c_putreg(priv, STM32_I2C_TRISE_OFFSET, trise); - - /* Bit 14 of OAR1 must be configured and kept at 1 */ - - stm32_i2c_putreg(priv, STM32_I2C_OAR1_OFFSET, I2C_OAR1_ONE); - - /* Re-enable the peripheral (or not) */ - - stm32_i2c_putreg(priv, STM32_I2C_CR1_OFFSET, cr1); - - /* Save the new I2C frequency */ - - priv->frequency = frequency; - } -} - -/**************************************************************************** - * Name: stm32_i2c_sendstart - * - * Description: - * Send the START conditions/force Master mode - * - ****************************************************************************/ - -static inline void stm32_i2c_sendstart(struct stm32_i2c_priv_s *priv) -{ - /* Disable ACK on receive by default and generate START */ - - stm32_i2c_modifyreg(priv, - STM32_I2C_CR1_OFFSET, I2C_CR1_ACK, I2C_CR1_START); -} - -/**************************************************************************** - * Name: stm32_i2c_clrstart - * - * Description: - * Clear the STOP, START or PEC condition on certain error recovery steps. - * - ****************************************************************************/ - -static inline void stm32_i2c_clrstart(struct stm32_i2c_priv_s *priv) -{ - /* "Note: When the STOP, START or PEC bit is set, the software must - * not perform any write access to I2C_CR1 before this bit is - * cleared by hardware. Otherwise there is a risk of setting a - * second STOP, START or PEC request." - * - * "The [STOP] bit is set and cleared by software, cleared by hardware - * when a Stop condition is detected, set by hardware when a timeout - * error is detected. - * - * "This [START] bit is set and cleared by software and cleared by hardware - * when start is sent or PE=0." The bit must be cleared by software if - * the START is never sent. - * - * "This [PEC] bit is set and cleared by software, and cleared by hardware - * when PEC is transferred or by a START or Stop condition or when PE=0." - */ - - stm32_i2c_modifyreg(priv, STM32_I2C_CR1_OFFSET, - I2C_CR1_START | I2C_CR1_STOP | I2C_CR1_PEC, 0); -} - -/**************************************************************************** - * Name: stm32_i2c_sendstop - * - * Description: - * Send the STOP conditions - * - ****************************************************************************/ - -static inline void stm32_i2c_sendstop(struct stm32_i2c_priv_s *priv) -{ - stm32_i2c_modifyreg(priv, STM32_I2C_CR1_OFFSET, I2C_CR1_ACK, I2C_CR1_STOP); -} - -/**************************************************************************** - * Name: stm32_i2c_getstatus - * - * Description: - * Get 32-bit status (SR1 and SR2 combined) - * - ****************************************************************************/ - -static inline uint32_t stm32_i2c_getstatus(struct stm32_i2c_priv_s *priv) -{ - uint32_t status = stm32_i2c_getreg(priv, STM32_I2C_SR1_OFFSET); - status |= (stm32_i2c_getreg(priv, STM32_I2C_SR2_OFFSET) << 16); - return status; -} - -/**************************************************************************** - * Name: stm32_i2c_disablefsmc - * - * Description: - * FSMC must be disable while accessing I2C1 because it uses a common - * resource (LBAR) - * - * NOTE: - * This is an issue with the STM32F103ZE, but may not be an issue with other - * STM32s. You may need to experiment - * - ****************************************************************************/ - -#ifdef I2C1_FSMC_CONFLICT -static inline -uint32_t stm32_i2c_disablefsmc(struct stm32_i2c_priv_s *priv) -{ - uint32_t ret = 0; - uint32_t regval; - - /* Is this I2C1 */ - -#if defined(CONFIG_STM32_I2C2) || defined(CONFIG_STM32_I2C3) - if (priv->config->base == STM32_I2C1_BASE) -#endif - { - /* Disable FSMC unconditionally */ - - ret = getreg32(STM32_RCC_AHBENR); - regval = ret & ~RCC_AHBENR_FSMCEN; - putreg32(regval, STM32_RCC_AHBENR); - } - - return ret; -} - -/**************************************************************************** - * Name: stm32_i2c_enablefsmc - * - * Description: - * Re-enable the FSMC - * - ****************************************************************************/ - -static inline void stm32_i2c_enablefsmc(uint32_t ahbenr) -{ - uint32_t regval; - - /* Enable AHB clocking to the FSMC only if it was previously enabled. */ - - if ((ahbenr & RCC_AHBENR_FSMCEN) != 0) - { - regval = getreg32(STM32_RCC_AHBENR); - regval |= RCC_AHBENR_FSMCEN; - putreg32(regval, STM32_RCC_AHBENR); - } -} -#else -# define stm32_i2c_disablefsmc(priv) (0) -# define stm32_i2c_enablefsmc(ahbenr) -#endif /* I2C1_FSMC_CONFLICT */ - -/**************************************************************************** - * Name: stm32_i2c_isr_process - * - * Description: - * Common Interrupt Service Routine - * - ****************************************************************************/ - -static int stm32_i2c_isr_process(struct stm32_i2c_priv_s *priv) -{ - uint32_t status; -#ifndef CONFIG_I2C_POLLED - uint32_t regval; -#endif -#ifdef CONFIG_STM32_I2C_DMA - uint16_t cr2; -#endif - - i2cinfo("I2C ISR called\n"); - - /* Get state of the I2C controller (register SR1 only) - * - * Get control register SR1 only as reading both SR1 and SR2 clears the - * ADDR flag(possibly others) causing the hardware to advance to the next - * state without the proper action being taken. - */ - - status = stm32_i2c_getreg(priv, STM32_I2C_SR1_OFFSET); - - /* Update private version of the state */ - - priv->status = status; - - /* Check if this is a new transmission so to set up the - * trace table accordingly. - */ - - stm32_i2c_tracenew(priv, status); - stm32_i2c_traceevent(priv, I2CEVENT_ISR_CALL, 0); - - /* Messages handling (1/2) - * - * Message handling should only operate when a message has been completely - * sent and after the ISR had the chance to run to set bits after the last - * written/read byte, i.e. priv->dcnt == -1. This is also the case in when - * the ISR is called for the first time. This can seen in - * stm32_i2c_process() before entering the stm32_i2c_sem_waitdone() waiting - * process. - * - * Message handling should only operate when: - * - A message has been completely sent and there are still messages - * to send(i.e. msgc > 0). - * - After the ISR had the chance to run to set start bit or - * termination flags after the last written/read byte(after last byte - * dcnt=0, msg handling dcnt = -1). - * - * When the ISR is called for the first time the same conditions hold. - * This can seen in stm32_i2c_process() before entering the - * stm32_i2c_sem_waitdone() waiting process. - */ - -#ifdef CONFIG_STM32_I2C_DMA - /* If ISR gets called (ex. polling mode) while DMA is still in - * progress, we should just return and let the DMA finish. - */ - - cr2 = stm32_i2c_getreg(priv, STM32_I2C_CR2_OFFSET); - if ((cr2 & I2C_CR2_DMAEN) != 0) - { -#ifdef CONFIG_DEBUG_I2C_INFO - size_t left = stm32_dmaresidual(priv->rxdma); - - i2cinfo("DMA in progress: %ld [bytes] remainining. Returning.\n", - left); -#endif - return OK; - } -#endif - - if (priv->dcnt == -1 && priv->msgc > 0) - { - /* Any new message should begin with "Start" condition - * However there were 2 situations where that was not true - * Situation 1: - * Next message continue transmission sequence of previous message - * - * Situation 2: If an error is injected that looks like a STOP the - * interrupt will be reentered with some status that will be incorrect. - * This will ensure that the error handler will clear the interrupt - * enables and return the error to the waiting task. - */ - - if (((priv->msgv[0].flags & I2C_M_NOSTART) != 0 && - (status & I2C_SR1_TXE) == 0) || - ((priv->msgv[0].flags & I2C_M_NOSTART) == 0 && - (status & I2C_SR1_SB) == 0)) - { -#if defined(CONFIG_STM32_I2C_DMA) || defined(CONFIG_I2C_POLLED) - return OK; -#else - priv->status |= I2C_SR1_TIMEOUT; - goto state_error; -#endif - } - - i2cinfo("Switch to new message\n"); - - /* Get current message to process data and copy to private structure */ - - priv->ptr = priv->msgv->buffer; /* Copy buffer to private struct */ - priv->dcnt = priv->msgv->length; /* Set counter of current msg length */ - priv->flags = priv->msgv->flags; /* Copy flags to private struct */ - - i2cinfo("Current flags %i\n", priv->flags); - - /* Decrease counter to indicate the number of messages left to - * process - */ - - priv->msgc--; - - /* Decrease message pointer. - * If last message set next message vector to null - */ - - if (priv->msgc == 0) - { - /* No more messages, don't need to increment msgv. This pointer - * will be set to zero when reaching the termination of the ISR - * calls, i.e. Messages handling(2/2). - */ - } - else - { - /* If not last message increment to next message to process */ - - priv->msgv++; - } - - /* Trace event */ - - stm32_i2c_traceevent(priv, I2CEVENT_MSG_HANDLING, priv->msgc); - } - - /* Note the event where we are on the last message and after the last - * byte is handled at the bottom of this function, as it terminates - * the repeated calls to the ISR. - */ - - /* I2C protocol logic - * - * I2C protocol logic follows. It's organized in an if else chain such that - * only one mode of operation is executed every time the ISR is called. - */ - - /* Address Handling - * - * Check if a start bit was set and transmit address with proper format. - * - * Note: - * On first call the start bit has been set by stm32_i2c_waitdone() - * Otherwise it will be set from this ISR. - * - * Remember that after a start bit an address has always to be sent. - */ - - if ((status & I2C_SR1_SB) != 0) - { - /* Start bit is set */ - - i2cinfo("Entering address handling, status = %" PRIi32 "\n", status); - - /* Check for empty message (for robustness) */ - - if (priv->dcnt > 0) - { - /* Set POS bit to zero (can be up from a previous 2 byte receive) */ - - stm32_i2c_modifyreg(priv, STM32_I2C_CR1_OFFSET, I2C_CR1_POS, 0); - - /* ACK is the expected answer for N>=3 reads and writes */ - - stm32_i2c_modifyreg(priv, STM32_I2C_CR1_OFFSET, 0, I2C_CR1_ACK); - - /* Send address byte with correct 8th bit set - * (for writing or reading) - * Transmission happens after having written to the data register - * STM32_I2C_DR - */ - - stm32_i2c_putreg(priv, STM32_I2C_DR_OFFSET, - (priv->flags & I2C_M_TEN) ? - 0 : ((priv->msgv->addr << 1) | - (priv->flags & I2C_M_READ))); - - i2cinfo("Address sent. Addr=%#02x Write/Read bit=%i\n", - priv->msgv->addr, (priv->flags & I2C_M_READ)); - - /* Flag that address has just been sent */ - - priv->check_addr_ack = true; - - stm32_i2c_traceevent(priv, I2CEVENT_SENDADDR, priv->msgv->addr); - } - else - { - /* TODO: untested!! */ - - i2cwarn(" An empty message has been detected, " - "ignoring and passing to next message.\n"); - - /* Trace event */ - - stm32_i2c_traceevent(priv, I2CEVENT_EMPTY_MSG, 0); - - /* Set condition to activate msg handling */ - - priv->dcnt = -1; - -#ifndef CONFIG_I2C_POLLED - /* Restart ISR by setting an interrupt buffer bit */ - - stm32_i2c_modifyreg(priv, - STM32_I2C_CR2_OFFSET, 0, I2C_CR2_ITBUFEN); -#endif - } - } - - /* Address cleared event - * - * Check if the address cleared, i.e. the driver found a valid address. - * If a NACK was received the address is invalid, if an ACK was - * received the address is valid and transmission can continue. - */ - - /* Check for NACK after an address */ - -#ifndef CONFIG_I2C_POLLED - /* When polling the i2c ISR it's not possible to determine when - * an address has been ACKed(i.e. the address is valid). - * - * The mechanism to deal a NACKed address is to wait for the I2C - * call to timeout (value defined in defconfig by one of the - * following: CONFIG_STM32_I2C_DYNTIMEO, CONFIG_STM32_I2CTIMEOSEC, - * CONFIG_STM32_I2CTIMEOMS, CONFIG_STM32_I2CTIMEOTICKS). - * - * To be safe in the case of a timeout/NACKed address a stop bit - * is set on the bus to clear it. In POLLED operation it's done - * stm32_i2c_process() after the call to stm32_i2c_sem_waitdone(). - * - * In ISR driven operation the stop bit in case of a NACKed address - * is set in the ISR itself. - * - * Note: this commentary is found in both places. - */ - - else if ((status & I2C_SR1_ADDR) == 0 && priv->check_addr_ack) - { - i2cinfo("Invalid Address. Setting stop bit and clearing message\n"); - i2cinfo("status %" PRIi32 "\n", status); - - /* Set condition to terminate msg chain transmission as address is - * invalid. - */ - - priv->dcnt = -1; - priv->msgc = 0; - - i2cinfo("dcnt %i , msgc %i\n", priv->dcnt, priv->msgc); - - /* Reset flag to check for valid address */ - - priv->check_addr_ack = false; - - /* Send stop bit to clear bus */ - - stm32_i2c_sendstop(priv); - - /* Trace event */ - - stm32_i2c_traceevent(priv, I2CEVENT_ADDRESS_NACKED, priv->msgv->addr); - } -#endif - - /* ACK in read mode, ACK in write mode is handled separately */ - - else if ((priv->flags & I2C_M_READ) != 0 && (status & I2C_SR1_ADDR) != 0 && - priv->check_addr_ack) - { - /* Reset check addr flag as we are handling this event */ - - priv->check_addr_ack = false; - - /* Note: - * - * When reading a single byte the stop condition has to be set - * immediately after clearing the state flags, which happens - * when reading SR2(as SR1 has already been read). - * - * Similarly when reading 2 bytes the NACK bit has to be set as just - * after the clearing of the address. - */ - - if (priv->dcnt == 1) - { - /* this should only happen when receiving a message of length 1 */ - - i2cinfo("short read N=1: setting NACK\n"); - - /* Set POS bit to zero (can be up from a previous 2 byte receive) */ - - stm32_i2c_modifyreg(priv, STM32_I2C_CR1_OFFSET, I2C_CR1_POS, 0); - - /* Immediately set NACK */ - - stm32_i2c_modifyreg(priv, STM32_I2C_CR1_OFFSET, I2C_CR1_ACK, 0); - -#ifndef CONFIG_I2C_POLLED - /* Enable RxNE and TxE buffers in order to receive one or multiple - * bytes - */ - - stm32_i2c_modifyreg(priv, - STM32_I2C_CR2_OFFSET, 0, I2C_CR2_ITBUFEN); -#endif - - /* Clear ADDR flag by reading SR2 and adding it to status */ - - status |= (stm32_i2c_getreg(priv, STM32_I2C_SR2_OFFSET) << 16); - - /* Send Stop/Restart */ - - if (priv->msgc > 0) - { - stm32_i2c_sendstart(priv); - } - else - { - stm32_i2c_sendstop(priv); - } - - i2cinfo("Address ACKed beginning data reception\n"); - i2cinfo("short read N=1: programming stop bit\n"); - - /* Trace */ - - stm32_i2c_traceevent(priv, I2CEVENT_ADDRESS_ACKED_READ_1, 0); - } - else if (priv->dcnt == 2) - { - /* This should only happen when receiving a message of length 2 */ - - /* Set POS bit to zero (can be up from a previous 2 byte receive) */ - - stm32_i2c_modifyreg(priv, STM32_I2C_CR1_OFFSET, 0, I2C_CR1_POS); - - /* Immediately set NACK */ - - stm32_i2c_modifyreg(priv, STM32_I2C_CR1_OFFSET, I2C_CR1_ACK, 0); - - /* Clear ADDR flag by reading SR2 and adding it to status */ - - status |= (stm32_i2c_getreg(priv, STM32_I2C_SR2_OFFSET) << 16); - - i2cinfo("Address ACKed beginning data reception\n"); - i2cinfo("short read N=2: programming NACK\n"); - - /* Trace */ - - stm32_i2c_traceevent(priv, I2CEVENT_ADDRESS_ACKED_READ_2, 0); - } - else - { - i2cinfo("Address ACKed beginning data reception\n"); - - /* Clear ADDR flag by reading SR2 and adding it to status */ - - status |= (stm32_i2c_getreg(priv, STM32_I2C_SR2_OFFSET) << 16); - - /* Trace */ - - stm32_i2c_traceevent(priv, I2CEVENT_ADDRESS_ACKED, 0); - -#ifdef CONFIG_STM32_I2C_DMA - /* DMA only when not doing a short read */ - - i2cinfo("Starting dma transfer and disabling interrupts\n"); - - /* The DMA must be initialized and enabled before the I2C data - * transfer. - * The DMAEN bit must be set in the I2C_CR2 register before the - * ADDR event. - */ - - stm32_dmasetup(priv->rxdma, - priv->config->base + STM32_I2C_DR_OFFSET, - (uint32_t)priv->ptr, priv->dcnt, - DMA_SCR_DIR_P2M | - DMA_SCR_MSIZE_8BITS | - DMA_SCR_PSIZE_8BITS | - DMA_SCR_MINC | - I2C_DMA_PRIO); - - /* Do not enable the ITBUFEN bit in the I2C_CR2 register if DMA is - * used. - */ - - stm32_i2c_modifyreg(priv, - STM32_I2C_CR2_OFFSET, I2C_CR2_ITBUFEN, 0); - -#ifndef CONFIG_I2C_POLLED - /* Now let DMA do all the work, disable i2c interrupts */ - - regval = stm32_i2c_getreg(priv, STM32_I2C_CR2_OFFSET); - regval &= ~I2C_CR2_ALLINTS; - stm32_i2c_putreg(priv, STM32_I2C_CR2_OFFSET, regval); -#endif - - /* The user can generate a Stop condition in the DMA Transfer - * Complete interrupt routine if enabled. This will be done in - * the dma rx callback Start DMA. - */ - - stm32_dmastart(priv->rxdma, stm32_i2c_dmarxcallback, priv, false); - stm32_i2c_modifyreg(priv, STM32_I2C_CR2_OFFSET, 0, I2C_CR2_DMAEN); -#else -#ifndef CONFIG_I2C_POLLED - if (priv->dcnt > 3) - { - /* Don't enable I2C_CR2_ITBUFEN for messages longer than 3 - * bytes - */ - - stm32_i2c_modifyreg(priv, - STM32_I2C_CR2_OFFSET, 0, I2C_CR2_ITBUFEN); - } -#endif -#endif - } - } - - /* Write mode - * - * Handles all write related I2C protocol logic. Also handles the - * ACK event after clearing the ADDR flag as the write has to - * begin immediately after. - */ - - else if ((priv->flags & I2C_M_READ) == 0 && - (status & I2C_SR1_BTF) != 0 && - priv->dcnt == 0) - { - /* After last byte, check what to do based on next message flags */ - - if (priv->msgc == 0) - { - /* If last message send stop bit */ - - stm32_i2c_sendstop(priv); - i2cinfo("Stop sent dcnt = %i msgc = %i\n", priv->dcnt, priv->msgc); - - /* Decrease counter to get to next message */ - - priv->dcnt--; - i2cinfo("dcnt %i\n", priv->dcnt); - stm32_i2c_traceevent(priv, I2CEVENT_WRITE_STOP, priv->dcnt); - } - - /* If there is a next message with no flags or the read flag - * a restart sequence has to be sent. - * Note msgv already points to the next message. - */ - - else if (priv->msgc > 0 && - (priv->msgv->flags == 0 || - (priv->msgv[0].flags & I2C_M_READ) != 0)) - { - /* Send start */ - - stm32_i2c_sendstart(priv); - - stm32_i2c_getreg(priv, STM32_I2C_DR_OFFSET); - - i2cinfo("Restart detected!\n"); - i2cinfo("Nextflag %i\n", priv->msgv[0].flags); - - /* Decrease counter to get to next message */ - - priv->dcnt--; - i2cinfo("dcnt %i\n", priv->dcnt); - stm32_i2c_traceevent(priv, I2CEVENT_WRITE_RESTART, priv->dcnt); - } - else - { - i2cinfo("Write mode: next message has an unrecognized flag.\n"); - stm32_i2c_traceevent(priv, - I2CEVENT_WRITE_FLAG_ERROR, priv->msgv->flags); - } - - status |= (stm32_i2c_getreg(priv, STM32_I2C_SR2_OFFSET) << 16); - } - else if ((priv->flags & I2C_M_READ) == 0 && - (status & (I2C_SR1_ADDR | I2C_SR1_TXE)) != 0 && - priv->dcnt != 0) - { - /* The has cleared(ADDR is set, ACK was received after the address) - * or the transmit buffer is empty flag has been set(TxE) then we can - * transmit the next byte. - */ - - i2cinfo("Entering write mode dcnt = %i msgc = %i\n", - priv->dcnt, priv->msgc); - - /* Clear ADDR flag by reading SR2 and adding it to status */ - - status |= (stm32_i2c_getreg(priv, STM32_I2C_SR2_OFFSET) << 16); - - /* Address has cleared so don't check on next call */ - - priv->check_addr_ack = false; - - /* Check if we have transmitted the whole message or we are after - * the last byte where the stop condition or else(according to the - * msg flags) has to be set. - */ - -#ifdef CONFIG_STM32_I2C_DMA - /* if DMA is enabled, only makes sense to make use of it for longer - * than 1 B transfers. - */ - - if (priv->dcnt > 1) - { - i2cinfo("Starting DMA transfer and disabling interrupts\n"); - - /* The DMA must be initialized and enabled before the I2C data - * transfer. The DMAEN bit must be set in the I2C_CR2 register - * before the ADDR event. - */ - - stm32_dmasetup(priv->txdma, - priv->config->base + STM32_I2C_DR_OFFSET, - (uint32_t) priv->ptr, priv->dcnt, - DMA_SCR_DIR_M2P | - DMA_SCR_MSIZE_8BITS | - DMA_SCR_PSIZE_8BITS | - DMA_SCR_MINC | - I2C_DMA_PRIO); - - /* Do not enable the ITBUFEN bit in the I2C_CR2 register if DMA is - * used. - */ - - stm32_i2c_modifyreg(priv, - STM32_I2C_CR2_OFFSET, I2C_CR2_ITBUFEN, 0); - -#ifndef CONFIG_I2C_POLLED - /* Now let DMA do all the work, disable i2c interrupts */ - - regval = stm32_i2c_getreg(priv, STM32_I2C_CR2_OFFSET); - regval &= ~I2C_CR2_ALLINTS; - stm32_i2c_putreg(priv, STM32_I2C_CR2_OFFSET, regval); -#endif - - /* In the interrupt routine after the EOT interrupt, disable DMA - * requests then wait for a BTF event before programming the Stop - * condition. To do this, we'll just call the ISR again in - * DMA tx callback, in which point we fall into the msgc==0 case - * which ultimately sends the stop..TODO: but we don't explicitly - * wait for BTF bit being set... - * Start DMA. - */ - - stm32_i2c_modifyreg(priv, STM32_I2C_CR2_OFFSET, 0, I2C_CR2_DMAEN); - stm32_dmastart(priv->txdma, stm32_i2c_dmatxcallback, priv, false); - } - else -#endif /* CONFIG_STM32_I2C_DMA */ - { -#ifndef CONFIG_I2C_POLLED - if (priv->dcnt == 1 && - (priv->msgc == 0 || (priv->msgv->flags & I2C_M_NOSTART) == 0)) - { - stm32_i2c_modifyreg(priv, - STM32_I2C_CR2_OFFSET, I2C_CR2_ITBUFEN, 0); - } -#endif - - /* Transmitting message. - * Send byte == write data into write register - */ - - stm32_i2c_putreg(priv, STM32_I2C_DR_OFFSET, *priv->ptr++); - - /* Decrease current message length */ - - stm32_i2c_traceevent(priv, I2CEVENT_WRITE_TO_DR, priv->dcnt); - priv->dcnt--; - - if ((status & I2C_SR1_ADDR) != 0 && priv->dcnt > 0) - { - /* Transmitting message. - * ADDR -> BTF & TXE - Send one more byte - */ - - stm32_i2c_putreg(priv, STM32_I2C_DR_OFFSET, *priv->ptr++); - - /* Decrease current message length */ - - stm32_i2c_traceevent(priv, I2CEVENT_WRITE_TO_DR, priv->dcnt); - priv->dcnt--; - } - -#ifndef CONFIG_I2C_POLLED - if (((status & I2C_SR1_ADDR) != 0 && priv->dcnt > 0) || - (priv->msgc > 0 && (priv->msgv->flags & I2C_M_NOSTART) != 0)) - { - stm32_i2c_modifyreg(priv, - STM32_I2C_CR2_OFFSET, 0, I2C_CR2_ITBUFEN); - } -#endif - - if (priv->dcnt == 0 && - priv->msgc > 0 && (priv->msgv->flags & I2C_M_NOSTART) != 0) - { - /* Set condition to get to next message */ - - priv->dcnt = -1; - stm32_i2c_traceevent(priv, - I2CEVENT_WRITE_NO_RESTART, priv->dcnt); - } - } - } - - /* Read mode - * - * Handles all read related I2C protocol logic. - * - * * * * * * * WARNING STM32F1xx HARDWARE ERRATA * * * * * * * - * - * source: https://github.com/hikob/openlab/blob/master/drivers/stm32/i2c.c - * - * RXNE-only events should not be handled since it sometimes - * fails. Only BTF & RXNE events should be handled (with the - * consequence of slowing down the transfer). - * - * It seems that when a RXNE interrupt is handled 'around' - * the end of the next byte reception, the DR register read - * is ignored by the i2c controller: it does not flush the - * DR with next byte - * - * Thus we read twice the same byte and we read effectively - * read one byte less than expected from the i2c slave point - * of view. - * - * Example: - * + we want to receive 6 bytes (B1 to B6) - * + the problem appear when reading B3 - * -> we read B1 B2 B3 B3 B4 B5(B3 twice) - * -> the i2c transfer was B1 B2 B3 B4 B5(B6 is not sent) - */ - - else if ((priv->flags & (I2C_M_READ)) != 0 && - (status & (I2C_SR1_RXNE | I2C_SR1_BTF)) != 0) - { - /* When read flag is set and the receive buffer is not empty - * (RXNE is set) then the driver can read from the data register. - */ - - status |= (stm32_i2c_getreg(priv, STM32_I2C_SR2_OFFSET) << 16); - - i2cinfo("Entering read mode dcnt = %i msgc = %i, " - "status 0x%04" PRIx32 "\n", - priv->dcnt, priv->msgc, status); - - /* Byte #N-3W, we don't want to manage RxNE interrupt anymore, bytes - * N, N-1, N-2 will be read with BTF: - */ - -#ifndef CONFIG_I2C_POLLED - if (priv->dcnt < 5) - { - stm32_i2c_modifyreg(priv, - STM32_I2C_CR2_OFFSET, I2C_CR2_ITBUFEN, 0); - } -#else - if (priv->dcnt == 1 || - priv->dcnt > 3 || (status & I2C_SR1_BTF) != 0) -#endif - { - /* BTF: N-2/N-1, set NACK, read N-2 */ - - if (priv->dcnt == 3) - { - stm32_i2c_modifyreg(priv, - STM32_I2C_CR1_OFFSET, I2C_CR1_ACK, 0); - } - - /* BTF: N-1/N, STOP/START, read N-1, N */ - - else if (priv->dcnt == 2) - { - if (priv->msgc > 0) - { - stm32_i2c_sendstart(priv); - } - else - { - stm32_i2c_sendstop(priv); - } - - /* Read byte #N-1 */ - - *priv->ptr++ = stm32_i2c_getreg(priv, STM32_I2C_DR_OFFSET); - priv->dcnt--; - } - - /* Read last or current byte */ - - *priv->ptr++ = stm32_i2c_getreg(priv, STM32_I2C_DR_OFFSET); - priv->dcnt--; - - if (priv->dcnt == 0) - { - priv->dcnt = -1; - } - } - } - - /* Empty call handler - * - * Case to handle an empty call to the ISR where it only has to - * Shutdown - */ - - else if (priv->dcnt == -1 && priv->msgc == 0) - { - /* Read rest of the state */ - - status |= (stm32_i2c_getreg(priv, STM32_I2C_SR2_OFFSET) << 16); - i2cinfo("Empty call to ISR: Stopping ISR\n"); - stm32_i2c_traceevent(priv, I2CEVENT_ISR_EMPTY_CALL, 0); - } - - /* Error handler - * - * Gets triggered if the driver does not recognize a situation(state) - * it can deal with. - * This should not happen in interrupt based operation(i.e. when - * CONFIG_I2C_POLLED is not set in the defconfig file). - * During polled operation(i.e. CONFIG_I2C_POLLED=y in defconfig) - * this case should do nothing but tracing the event that the - * device wasn't ready yet. - */ - - else - { -#ifdef CONFIG_I2C_POLLED - stm32_i2c_traceevent(priv, I2CEVENT_POLL_DEV_NOT_RDY, 0); -#else - /* Read rest of the state */ - - status |= (stm32_i2c_getreg(priv, STM32_I2C_SR2_OFFSET) << 16); - - /* No any error bit is set, but driver is in incorrect state, signal - * it with "Bus error" bit. - */ - - if ((status & I2C_SR1_ERRORMASK) != 0) - { - priv->status |= I2C_SR1_BERR; - } - - i2cinfo(" No correct state detected(start bit, read or write)\n"); - i2cinfo(" state %" PRIi32 "\n", status); - - /* Set condition to terminate ISR and wake waiting thread */ - - priv->dcnt = -1; - priv->msgc = 0; - stm32_i2c_traceevent(priv, I2CEVENT_STATE_ERROR, 0); -#endif - } - - /* Messages handling(2/2) - * - * Transmission of the whole message chain has been completed. We have to - * terminate the ISR and wake up stm32_i2c_process() that is waiting for - * the ISR cycle to handle the sending/receiving of the messages. - */ - - /* First check for errors */ - - if ((status & I2C_SR1_ERRORMASK) != 0) - { - stm32_i2c_traceevent(priv, I2CEVENT_ERROR, status & I2C_SR1_ERRORMASK); - - /* Clear interrupt flags */ - -#if !defined(CONFIG_STM32_I2C_DMA) && !defined(CONFIG_I2C_POLLED) -state_error: -#endif - stm32_i2c_putreg(priv, STM32_I2C_SR1_OFFSET, 0); - - priv->dcnt = -1; - priv->msgc = 0; - } - - if (priv->dcnt == -1 && priv->msgc == 0) - { - i2cinfo("Shutting down I2C ISR\n"); - - stm32_i2c_traceevent(priv, I2CEVENT_ISR_SHUTDOWN, 0); - - /* Clear internal pointer to the message content. - * Good practice + done by last implementation when messages are - * finished (compatibility concerns) - */ - - priv->msgv = NULL; - -#ifdef CONFIG_I2C_POLLED - priv->intstate = INTSTATE_DONE; -#else - /* Clear all interrupts */ - - regval = stm32_i2c_getreg(priv, STM32_I2C_CR2_OFFSET); - regval &= ~I2C_CR2_ALLINTS; - stm32_i2c_putreg(priv, STM32_I2C_CR2_OFFSET, regval); - - /* Is there a thread waiting for this event(there should be) */ - - if (priv->intstate == INTSTATE_WAITING) - { - /* Yes.. inform the thread that the transfer is complete - * and wake it up. - */ - - nxsem_post(&priv->sem_isr); - priv->intstate = INTSTATE_DONE; - } -#endif - } - - return OK; -} - -/**************************************************************************** - * Name: stm32_i2c_isr - * - * Description: - * Common I2C interrupt service routine - * - ****************************************************************************/ - -#ifndef CONFIG_I2C_POLLED -static int stm32_i2c_isr(int irq, void *context, void *arg) -{ - struct stm32_i2c_priv_s *priv = (struct stm32_i2c_priv_s *)arg; - - DEBUGASSERT(priv != NULL); - return stm32_i2c_isr_process(priv); -} -#endif - -/**************************************************************************** - * Name: stm32_i2c_dmarxcallback - * - * Description: - * Called when the RX DMA completes - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_I2C_DMA -static void stm32_i2c_dmarxcallback(DMA_HANDLE handle, - uint8_t status, void *arg) -{ -#ifndef CONFIG_I2C_POLLED - uint32_t regval; -#endif - - i2cinfo("DMA rx callback, status = %d\n", status); - - struct stm32_i2c_priv_s *priv = (struct stm32_i2c_priv_s *)arg; - - priv->dcnt = -1; - - /* The user can generate a Stop condition in the DMA Transfer Complete - * interrupt routine if enabled. - */ - - if (priv->msgc > 0) - { - stm32_i2c_sendstart(priv); - } - else - { - stm32_i2c_sendstop(priv); - } - - /* Let the I2C periph know to stop DMA transfers, also is used by ISR - * to check if DMA is done. - */ - - stm32_i2c_modifyreg(priv, STM32_I2C_CR2_OFFSET, I2C_CR2_DMAEN, 0); - -#ifndef CONFIG_I2C_POLLED - /* Re-enable interrupts */ - - regval = stm32_i2c_getreg(priv, STM32_I2C_CR2_OFFSET); - regval |= (I2C_CR2_ITERREN | I2C_CR2_ITEVFEN); - stm32_i2c_putreg(priv, STM32_I2C_CR2_OFFSET, regval); -#endif - - /* let the ISR routine take care of shutting down or switching to - * next msg - */ - - stm32_i2c_isr_process(priv); -} -#endif /* ifdef CONFIG_STM32_I2C_DMA */ - -/**************************************************************************** - * Name: stm32_i2c_dmarxcallback - * - * Description: - * Called when the RX DMA completes - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_I2C_DMA -static void stm32_i2c_dmatxcallback(DMA_HANDLE handle, - uint8_t status, void *arg) -{ -#ifndef CONFIG_I2C_POLLED - uint32_t regval; -#endif - - i2cinfo("DMA tx callback, status = %d\n", status); - - struct stm32_i2c_priv_s *priv = (struct stm32_i2c_priv_s *)arg; - - priv->dcnt = 0; - - /* In the interrupt routine after the EOT interrupt, - * disable DMA requests - */ - - stm32_i2c_modifyreg(priv, STM32_I2C_CR2_OFFSET, I2C_CR2_DMAEN, 0); - -#ifndef CONFIG_I2C_POLLED - /* re-enable interrupts */ - - regval = stm32_i2c_getreg(priv, STM32_I2C_CR2_OFFSET); - regval |= (I2C_CR2_ITERREN | I2C_CR2_ITEVFEN); - stm32_i2c_putreg(priv, STM32_I2C_CR2_OFFSET, regval); -#endif -} -#endif /* ifdef CONFIG_STM32_I2C_DMA */ - -/**************************************************************************** - * Name: stm32_i2c_init - * - * Description: - * Setup the I2C hardware, ready for operation with defaults - * - ****************************************************************************/ - -static int stm32_i2c_init(struct stm32_i2c_priv_s *priv) -{ - /* Power-up and configure GPIOs */ - - /* Enable power and reset the peripheral */ - - modifyreg32(STM32_RCC_APB1ENR, 0, priv->config->clk_bit); - modifyreg32(STM32_RCC_APB1RSTR, 0, priv->config->reset_bit); - modifyreg32(STM32_RCC_APB1RSTR, priv->config->reset_bit, 0); - - /* Configure pins */ - - if (stm32_configgpio(priv->config->scl_pin) < 0) - { - return ERROR; - } - - if (stm32_configgpio(priv->config->sda_pin) < 0) - { - stm32_unconfiggpio(priv->config->scl_pin); - return ERROR; - } - - /* Attach ISRs */ - -#ifndef CONFIG_I2C_POLLED - irq_attach(priv->config->ev_irq, stm32_i2c_isr, priv); - irq_attach(priv->config->er_irq, stm32_i2c_isr, priv); - up_enable_irq(priv->config->ev_irq); - up_enable_irq(priv->config->er_irq); -#endif - - /* Set peripheral frequency, where it must be at least 2 MHz for 100 kHz - * or 4 MHz for 400 kHz. This also disables all I2C interrupts. - */ - - stm32_i2c_putreg(priv, - STM32_I2C_CR2_OFFSET, (STM32_PCLK1_FREQUENCY / 1000000)); - - /* Force a frequency update */ - - priv->frequency = 0; - - stm32_i2c_setclock(priv, 100000); - -#ifdef CONFIG_STM32_I2C_DMA - /* If, in the I2C_CR2 register, the LAST bit is set, I2C automatically - * sends a NACK after the next byte following EOT_1. - * Clear DMA en just in case. - */ - - stm32_i2c_modifyreg(priv, - STM32_I2C_CR2_OFFSET, I2C_CR2_DMAEN, I2C_CR2_LAST); -#endif - - /* Enable I2C */ - - stm32_i2c_putreg(priv, STM32_I2C_CR1_OFFSET, I2C_CR1_PE); - return OK; -} - -/**************************************************************************** - * Name: stm32_i2c_deinit - * - * Description: - * Shutdown the I2C hardware - * - ****************************************************************************/ - -static int stm32_i2c_deinit(struct stm32_i2c_priv_s *priv) -{ - /* Disable I2C */ - - stm32_i2c_putreg(priv, STM32_I2C_CR1_OFFSET, 0); - stm32_i2c_putreg(priv, STM32_I2C_CR2_OFFSET, 0); - - /* Unconfigure GPIO pins */ - - stm32_unconfiggpio(priv->config->scl_pin); - stm32_unconfiggpio(priv->config->sda_pin); - - /* Disable and detach interrupts */ - -#ifndef CONFIG_I2C_POLLED - up_disable_irq(priv->config->ev_irq); - up_disable_irq(priv->config->er_irq); - irq_detach(priv->config->ev_irq); - irq_detach(priv->config->er_irq); -#endif - -#ifdef CONFIG_STM32_I2C_DMA - /* Disable DMA */ - - stm32_dmastop(priv->txdma); - stm32_dmastop(priv->rxdma); -#endif - - /* Disable clocking */ - - modifyreg32(STM32_RCC_APB1ENR, priv->config->clk_bit, 0); - return OK; -} - -/**************************************************************************** - * Device Driver Operations - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_i2c_transfer - * - * Description: - * Generic I2C transfer function - * - ****************************************************************************/ - -static int stm32_i2c_transfer(struct i2c_master_s *dev, - struct i2c_msg_s *msgs, int count) -{ - struct stm32_i2c_priv_s *priv = (struct stm32_i2c_priv_s *)dev; - uint32_t status = 0; -#ifdef I2C1_FSMC_CONFLICT - uint32_t ahbenr; -#endif - int ret; - - DEBUGASSERT(count); - - /* Ensure that address or flags don't change meanwhile */ - - ret = nxmutex_lock(&priv->lock); - if (ret < 0) - { - return ret; - } - -#ifdef CONFIG_STM32_I2C_DMA - /* Stop DMA just in case */ - - stm32_i2c_modifyreg(priv, STM32_I2C_CR2_OFFSET, I2C_CR2_DMAEN, 0); - stm32_dmastop(priv->rxdma); - stm32_dmastop(priv->txdma); -#endif - -#ifdef I2C1_FSMC_CONFLICT - /* Disable FSMC that shares a pin with I2C1 (LBAR) */ - - ahbenr = stm32_i2c_disablefsmc(priv); - -#else - /* Wait for any STOP in progress. NOTE: If we have to disable the FSMC - * then we cannot do this at the top of the loop, unfortunately. The STOP - * will not complete normally if the FSMC is enabled. - */ - - stm32_i2c_sem_waitstop(priv); -#endif - - /* Clear any pending error interrupts */ - - stm32_i2c_putreg(priv, STM32_I2C_SR1_OFFSET, 0); - - /* "Note: When the STOP, START or PEC bit is set, the software must - * not perform any write access to I2C_CR1 before this bit is - * cleared by hardware. Otherwise there is a risk of setting a - * second STOP, START or PEC request." However, if the bits are - * not cleared by hardware, then we will have to do that from hardware. - */ - - stm32_i2c_clrstart(priv); - - /* Old transfers are done */ - - /* Reset ptr and dcnt to ensure an unexpected data interrupt doesn't - * overwrite stale data. - */ - - priv->dcnt = 0; - priv->ptr = NULL; - - priv->msgv = msgs; - priv->msgc = count; - - /* Reset I2C trace logic */ - - stm32_i2c_tracereset(priv); - - /* Set I2C clock frequency (on change it toggles I2C_CR1_PE !) - * REVISIT: Note that the frequency is set only on the first message. - * This could be extended to support different transfer frequencies for - * each message segment. - */ - - stm32_i2c_setclock(priv, msgs->frequency); - - /* Trigger start condition, then the process moves into the ISR. I2C - * interrupts will be enabled within stm32_i2c_waitdone(). - */ - - priv->dcnt = -1; - priv->status = 0; - stm32_i2c_sendstart(priv); - - /* Wait for an ISR, if there was a timeout, fetch latest status to get - * the BUSY flag. - */ - - if (stm32_i2c_sem_waitdone(priv) < 0) - { - status = stm32_i2c_getstatus(priv); - ret = -ETIMEDOUT; - - i2cerr("ERROR: Timed out: CR1: 0x%04x status: 0x%08" PRIx32 "\n", - stm32_i2c_getreg(priv, STM32_I2C_CR1_OFFSET), status); - - /* "Note: When the STOP, START or PEC bit is set, the software must - * not perform any write access to I2C_CR1 before this bit is - * cleared by hardware. Otherwise there is a risk of setting a - * second STOP, START or PEC request." - */ - - stm32_i2c_clrstart(priv); - - /* Clear busy flag in case of timeout */ - - status = priv->status & 0xffff; - } - else - { - /* clear SR2 (BUSY flag) as we've done successfully */ - - status = priv->status & 0xffff; - } - - /* Check for error status conditions */ - - if ((status & I2C_SR1_ERRORMASK) != 0) - { - /* I2C_SR1_ERRORMASK is the 'OR' of the following individual bits: */ - - if (status & I2C_SR1_BERR) - { - /* Bus Error */ - - ret = -EIO; - } - else if (status & I2C_SR1_ARLO) - { - /* Arbitration Lost (master mode) */ - - ret = -EAGAIN; - } - else if (status & I2C_SR1_AF) - { - /* Acknowledge Failure */ - - ret = -ENXIO; - } - else if (status & I2C_SR1_OVR) - { - /* Overrun/Underrun */ - - ret = -EIO; - } - else if (status & I2C_SR1_PECERR) - { - /* PEC Error in reception */ - - ret = -EPROTO; - } - else if (status & I2C_SR1_TIMEOUT) - { - /* Timeout or Tlow Error */ - - ret = -ETIME; - } - - /* This is not an error and should never happen since SMBus is not - * enabled - */ - - else /* if (status & I2C_SR1_SMBALERT) */ - { - /* SMBus alert is an optional signal with an interrupt line for - * devices that want to trade their ability to master for a pin. - */ - - ret = -EINTR; - } - } - - /* This is not an error, but should not happen. The BUSY signal can hang, - * however, if there are unhealthy devices on the bus that need to be - * reset. - * NOTE: We will only see this busy indication if stm32_i2c_sem_waitdone() - * fails above; Otherwise it is cleared. - */ - - else if ((status & (I2C_SR2_BUSY << 16)) != 0) - { - /* I2C Bus is for some reason busy */ - - ret = -EBUSY; - } - - /* Dump the trace result */ - - stm32_i2c_tracedump(priv); - -#ifdef I2C1_FSMC_CONFLICT - /* Wait for any STOP in progress. NOTE: If we have to disable the FSMC - * then we cannot do this at the top of the loop, unfortunately. The STOP - * will not complete normally if the FSMC is enabled. - */ - - stm32_i2c_sem_waitstop(priv); - - /* Re-enable the FSMC */ - - stm32_i2c_enablefsmc(ahbenr); -#endif - - /* Ensure that any ISR happening after we finish can't overwrite any user - * data - */ - - priv->dcnt = 0; - priv->ptr = NULL; - - nxmutex_unlock(&priv->lock); - return ret; -} - -/**************************************************************************** - * Name: stm32_i2c_reset - * - * Description: - * Perform an I2C bus reset in an attempt to break loose stuck I2C devices. - * - * Input Parameters: - * dev - Device-specific state data - * - * Returned Value: - * Zero (OK) on success; a negated errno value on failure. - * - ****************************************************************************/ - -#ifdef CONFIG_I2C_RESET -static int stm32_i2c_reset(struct i2c_master_s *dev) -{ - struct stm32_i2c_priv_s *priv = (struct stm32_i2c_priv_s *)dev; - unsigned int clock_count; - unsigned int stretch_count; - uint32_t scl_gpio; - uint32_t sda_gpio; - uint32_t frequency; - int ret; - - DEBUGASSERT(dev); - - /* Our caller must own a ref */ - - DEBUGASSERT(priv->refs > 0); - - /* Lock out other clients */ - - ret = nxmutex_lock(&priv->lock); - if (ret < 0) - { - return ret; - } - - ret = -EIO; - - /* Save the current frequency */ - - frequency = priv->frequency; - - /* De-init the port */ - - stm32_i2c_deinit(priv); - - /* Use GPIO configuration to un-wedge the bus */ - - scl_gpio = MKI2C_OUTPUT(priv->config->scl_pin); - sda_gpio = MKI2C_OUTPUT(priv->config->sda_pin); - - stm32_configgpio(scl_gpio); - stm32_configgpio(sda_gpio); - - /* Let SDA go high */ - - stm32_gpiowrite(sda_gpio, 1); - - /* Clock the bus until any slaves currently driving it let it go. */ - - clock_count = 0; - while (!stm32_gpioread(sda_gpio)) - { - /* Give up if we have tried too hard */ - - if (clock_count++ > 10) - { - goto out; - } - - /* Sniff to make sure that clock stretching has finished. - * - * If the bus never relaxes, the reset has failed. - */ - - stretch_count = 0; - while (!stm32_gpioread(scl_gpio)) - { - /* Give up if we have tried too hard */ - - if (stretch_count++ > 10) - { - goto out; - } - - up_udelay(10); - } - - /* Drive SCL low */ - - stm32_gpiowrite(scl_gpio, 0); - up_udelay(10); - - /* Drive SCL high again */ - - stm32_gpiowrite(scl_gpio, 1); - up_udelay(10); - } - - /* Generate a start followed by a stop to reset slave - * state machines. - */ - - stm32_gpiowrite(sda_gpio, 0); - up_udelay(10); - stm32_gpiowrite(scl_gpio, 0); - up_udelay(10); - stm32_gpiowrite(scl_gpio, 1); - up_udelay(10); - stm32_gpiowrite(sda_gpio, 1); - up_udelay(10); - - /* Revert the GPIO configuration. */ - - stm32_unconfiggpio(sda_gpio); - stm32_unconfiggpio(scl_gpio); - - /* Re-init the port */ - - stm32_i2c_init(priv); - - /* Restore the frequency */ - - stm32_i2c_setclock(priv, frequency); - ret = OK; - -out: - - /* Release the port for reuse by other clients */ - - nxmutex_unlock(&priv->lock); - return ret; -} -#endif /* CONFIG_I2C_RESET */ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_i2cbus_initialize - * - * Description: - * Initialize one I2C bus - * - ****************************************************************************/ - -struct i2c_master_s *stm32_i2cbus_initialize(int port) -{ - struct stm32_i2c_priv_s *priv = NULL; - - /* Get I2C private structure */ - - switch (port) - { -#ifdef CONFIG_STM32_I2C1 - case 1: - priv = (struct stm32_i2c_priv_s *)&stm32_i2c1_priv; - break; -#endif -#ifdef CONFIG_STM32_I2C2 - case 2: - priv = (struct stm32_i2c_priv_s *)&stm32_i2c2_priv; - break; -#endif -#ifdef CONFIG_STM32_I2C3 - case 3: - priv = (struct stm32_i2c_priv_s *)&stm32_i2c3_priv; - break; -#endif - default: - return NULL; - } - - /* Initialize private data for the first time, increment reference count, - * power-up hardware and configure GPIOs. - */ - - nxmutex_lock(&priv->lock); - if (priv->refs++ == 0) - { - stm32_i2c_init(priv); - -#ifdef CONFIG_STM32_I2C_DMA - /* Get DMA channels. NOTE: stm32_dmachannel() will always assign the - * DMA channel. If the channel is not available, then - * stm32_dmachannel() will block and wait until the channel becomes - * available. - * WARNING: If you have another device sharing a DMA channel with SPI - * and the code never releases that channel, then the call to - * stm32_dmachannel() will hang forever in this function! - * Don't let your design do that! - */ - - priv->rxdma = stm32_dmachannel(priv->rxch); - priv->txdma = stm32_dmachannel(priv->txch); - DEBUGASSERT(priv->rxdma && priv->txdma); -#endif /* CONFIG_STM32_I2C_DMA */ - } - - nxmutex_unlock(&priv->lock); - return (struct i2c_master_s *)priv; -} - -/**************************************************************************** - * Name: stm32_i2cbus_uninitialize - * - * Description: - * Uninitialize an I2C bus - * - ****************************************************************************/ - -int stm32_i2cbus_uninitialize(struct i2c_master_s *dev) -{ - struct stm32_i2c_priv_s *priv = (struct stm32_i2c_priv_s *)dev; - - DEBUGASSERT(dev); - - /* Decrement reference count and check for underflow */ - - if (priv->refs == 0) - { - return ERROR; - } - - nxmutex_lock(&priv->lock); - if (--priv->refs) - { - nxmutex_unlock(&priv->lock); - return OK; - } - - /* Disable power and other HW resource (GPIO's) */ - - stm32_i2c_deinit(priv); - -#ifdef CONFIG_STM32_I2C_DMA - stm32_dmafree(priv->rxdma); - stm32_dmafree(priv->txdma); -#endif - - nxmutex_unlock(&priv->lock); - return OK; -} - -#endif /* CONFIG_STM32_STM32F10XX || CONFIG_STM32_STM32F20XX || CONFIG_STM32_STM32F4XXX */ -#endif /* CONFIG_STM32_I2C1 || CONFIG_STM32_I2C2 || CONFIG_STM32_I2C3 */ diff --git a/arch/arm/src/stm32/stm32f40xxx_rtcc.c b/arch/arm/src/stm32/stm32f40xxx_rtcc.c deleted file mode 100644 index 6917d43fd3472..0000000000000 --- a/arch/arm/src/stm32/stm32f40xxx_rtcc.c +++ /dev/null @@ -1,1633 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32f40xxx_rtcc.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -#include "arm_internal.h" -#include "stm32_rcc.h" -#include "stm32_pwr.h" -#include "stm32_exti.h" -#include "stm32_rtc.h" - -#include - -#ifdef CONFIG_STM32_RTC - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -/* This RTC implementation supports - * - date/time RTC hardware - * - extended functions Alarm A and B for STM32F4xx and onwards - * */ - -#ifndef CONFIG_RTC_DATETIME -# error "CONFIG_RTC_DATETIME must be set to use this driver" -#endif - -#ifdef CONFIG_RTC_HIRES -# error "CONFIG_RTC_HIRES must NOT be set with this driver" -#endif - -#ifndef CONFIG_STM32_PWR -# error "CONFIG_STM32_PWR must selected to use this driver" -#endif - -/* Constants ****************************************************************/ - -#define SYNCHRO_TIMEOUT (0x00020000) -#define INITMODE_TIMEOUT (0x00010000) - -/* Proxy definitions to make the same code work for all the STM32 series ****/ - -# define STM32_RCC_XXX STM32_RCC_BDCR -# define RCC_XXX_YYYRST RCC_BDCR_BDRST -# define RCC_XXX_RTCEN RCC_BDCR_RTCEN -# define RCC_XXX_RTCSEL_MASK RCC_BDCR_RTCSEL_MASK -# define RCC_XXX_RTCSEL_LSE RCC_BDCR_RTCSEL_LSE -# define RCC_XXX_RTCSEL_LSI RCC_BDCR_RTCSEL_LSI -# define RCC_XXX_RTCSEL_HSE RCC_BDCR_RTCSEL_HSE - -/* Time conversions */ - -#define MINUTES_IN_HOUR 60 -#define HOURS_IN_DAY 24 - -#define hours_add(parm_hrs) \ - time->tm_hour += parm_hrs;\ - if ((HOURS_IN_DAY-1) < (time->tm_hour))\ - {\ - time->tm_hour = (parm_hrs - HOURS_IN_DAY);\ - } - -#define RTC_ALRMR_DIS_MASK (RTC_ALRMR_MSK4 | RTC_ALRMR_MSK3 | \ - RTC_ALRMR_MSK2 | RTC_ALRMR_MSK1) -#define RTC_ALRMR_DIS_DATE_MASK (RTC_ALRMR_MSK4) -#define RTC_ALRMR_ENABLE (0) - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -#ifdef CONFIG_RTC_ALARM -typedef unsigned int rtc_alarmreg_t; - -struct alm_cbinfo_s -{ - volatile alm_callback_t ac_cb; /* Client callback function */ - volatile void *ac_arg; /* Argument to pass with the callback function */ -}; -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -#ifdef CONFIG_RTC_ALARM -/* Callback to use when an EXTI is activated */ - -static struct alm_cbinfo_s g_alarmcb[RTC_ALARM_LAST]; -static bool g_alarm_enabled; /* True: Alarm interrupts are enabled */ -#endif - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/* g_rtc_enabled is set true after the RTC has successfully initialized */ - -volatile bool g_rtc_enabled = false; - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -#ifdef CONFIG_RTC_ALARM -static int rtchw_check_alrawf(void); -static int rtchw_set_alrmar(rtc_alarmreg_t alarmreg); -#if CONFIG_RTC_NALARMS > 1 -static int rtchw_check_alrbwf(void); -static int rtchw_set_alrmbr(rtc_alarmreg_t alarmreg); -#endif -static inline void rtc_enable_alarm(void); -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: rtc_dumpregs - ****************************************************************************/ - -#ifdef CONFIG_DEBUG_RTC_INFO -static void rtc_dumpregs(const char *msg) -{ - int rtc_state; - - rtcinfo("%s:\n", msg); - rtcinfo(" TR: %08" PRIx32 "\n", getreg32(STM32_RTC_TR)); - rtcinfo(" DR: %08" PRIx32 "\n", getreg32(STM32_RTC_DR)); - rtcinfo(" CR: %08" PRIx32 "\n", getreg32(STM32_RTC_CR)); - rtcinfo(" ISR: %08" PRIx32 "\n", getreg32(STM32_RTC_ISR)); - rtcinfo(" PRER: %08" PRIx32 "\n", getreg32(STM32_RTC_PRER)); - rtcinfo(" WUTR: %08" PRIx32 "\n", getreg32(STM32_RTC_WUTR)); - rtcinfo(" ALRMAR: %08" PRIx32 "\n", getreg32(STM32_RTC_ALRMAR)); - rtcinfo(" ALRMBR: %08" PRIx32 "\n", getreg32(STM32_RTC_ALRMBR)); - rtcinfo(" SHIFTR: %08" PRIx32 "\n", getreg32(STM32_RTC_SHIFTR)); - rtcinfo(" TSTR: %08" PRIx32 "\n", getreg32(STM32_RTC_TSTR)); - rtcinfo(" TSDR: %08" PRIx32 "\n", getreg32(STM32_RTC_TSDR)); - rtcinfo(" TSSSR: %08" PRIx32 "\n", getreg32(STM32_RTC_TSSSR)); - rtcinfo(" CALR: %08" PRIx32 "\n", getreg32(STM32_RTC_CALR)); - rtcinfo(" TAFCR: %08" PRIx32 "\n", getreg32(STM32_RTC_TAFCR)); - rtcinfo("ALRMASSR: %08" PRIx32 "\n", getreg32(STM32_RTC_ALRMASSR)); - rtcinfo("ALRMBSSR: %08" PRIx32 "\n", getreg32(STM32_RTC_ALRMBSSR)); - rtcinfo("MAGICREG: %08" PRIx32 "\n", getreg32(RTC_MAGIC_REG)); - - rtc_state = - ((getreg32(STM32_EXTI_RTSR) & EXTI_RTC_ALARM) ? 0x1000 : 0) | - ((getreg32(STM32_EXTI_FTSR) & EXTI_RTC_ALARM) ? 0x0100 : 0) | - ((getreg32(STM32_EXTI_IMR) & EXTI_RTC_ALARM) ? 0x0010 : 0) | - ((getreg32(STM32_EXTI_EMR) & EXTI_RTC_ALARM) ? 0x0001 : 0); - rtcinfo("EXTI (RTSR FTSR ISR EVT): %01x\n", rtc_state); -} -#else -# define rtc_dumpregs(msg) -#endif - -/**************************************************************************** - * Name: rtc_dumptime - ****************************************************************************/ - -#ifdef CONFIG_DEBUG_RTC_INFO -static void rtc_dumptime(const struct tm *tp, const char *msg) -{ - rtcinfo("%s:\n", msg); - rtcinfo(" tm_sec: %08x\n", tp->tm_sec); - rtcinfo(" tm_min: %08x\n", tp->tm_min); - rtcinfo(" tm_hour: %08x\n", tp->tm_hour); - rtcinfo(" tm_mday: %08x\n", tp->tm_mday); - rtcinfo(" tm_mon: %08x\n", tp->tm_mon); - rtcinfo(" tm_year: %08x\n", tp->tm_year); -} -#else -# define rtc_dumptime(tp, msg) -#endif - -/**************************************************************************** - * Name: rtc_wprunlock - * - * Description: - * Disable RTC write protection - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void rtc_wprunlock(void) -{ - /* Enable write access to the backup domain (RTC registers, RTC backup data - * registers and backup SRAM). - */ - - stm32_pwr_enablebkp(true); - - /* The following steps are required to unlock the write protection on all - * the RTC registers (except for RTC_ISR[13:8], RTC_TAFCR, and RTC_BKPxR): - * - * 1. Write 0xCA into the RTC_WPR register. - * 2. Write 0x53 into the RTC_WPR register. - * - * Writing a wrong key re-activates the write protection. - */ - - putreg32(0xca, STM32_RTC_WPR); - putreg32(0x53, STM32_RTC_WPR); -} - -/**************************************************************************** - * Name: rtc_wprlock - * - * Description: - * Enable RTC write protection - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -static inline void rtc_wprlock(void) -{ - /* Writing any wrong key re-activates the write protection. */ - - putreg32(0xff, STM32_RTC_WPR); - - /* Disable write access to the backup domain (RTC registers, RTC backup - * data registers and backup SRAM). - */ - - stm32_pwr_enablebkp(false); -} - -/**************************************************************************** - * Name: rtc_synchwait - * - * Description: - * Waits until the RTC Time and Date registers (RTC_TR and RTC_DR) are - * synchronized with RTC APB clock. - * - * Input Parameters: - * None - * - * Returned Value: - * Zero (OK) on success; a negated errno on failure - * - ****************************************************************************/ - -static int rtc_synchwait(void) -{ - volatile uint32_t timeout; - uint32_t regval; - int ret; - - /* Disable the write protection for RTC registers */ - - rtc_wprunlock(); - - /* Clear Registers synchronization flag (RSF) */ - - regval = getreg32(STM32_RTC_ISR); - regval &= ~RTC_ISR_RSF; - putreg32(regval, STM32_RTC_ISR); - - /* Now wait the registers to become synchronised */ - - ret = -ETIMEDOUT; - for (timeout = 0; timeout < SYNCHRO_TIMEOUT; timeout++) - { - regval = getreg32(STM32_RTC_ISR); - if ((regval & RTC_ISR_RSF) != 0) - { - /* Synchronized */ - - ret = OK; - break; - } - } - - /* Re-enable the write protection for RTC registers */ - - rtc_wprlock(); - return ret; -} - -/**************************************************************************** - * Name: rtc_enterinit - * - * Description: - * Enter RTC initialization mode. - * - * Input Parameters: - * None - * - * Returned Value: - * Zero (OK) on success; a negated errno on failure - * - ****************************************************************************/ - -static int rtc_enterinit(void) -{ - volatile uint32_t timeout; - uint32_t regval; - int ret; - - /* Check if the Initialization mode is already set */ - - regval = getreg32(STM32_RTC_ISR); - - ret = OK; - if ((regval & RTC_ISR_INITF) == 0) - { - /* Set the Initialization mode */ - - putreg32(RTC_ISR_INIT, STM32_RTC_ISR); - - /* Wait until the RTC is in the INIT state (or a timeout occurs) */ - - ret = -ETIMEDOUT; - for (timeout = 0; timeout < INITMODE_TIMEOUT; timeout++) - { - regval = getreg32(STM32_RTC_ISR); - if ((regval & RTC_ISR_INITF) != 0) - { - ret = OK; - break; - } - } - } - - return ret; -} - -/**************************************************************************** - * Name: rtc_exitinit - * - * Description: - * Exit RTC initialization mode. - * - * Input Parameters: - * None - * - * Returned Value: - * Zero (OK) on success; a negated errno on failure - * - ****************************************************************************/ - -static void rtc_exitinit(void) -{ - uint32_t regval; - - regval = getreg32(STM32_RTC_ISR); - regval &= ~(RTC_ISR_INIT); - putreg32(regval, STM32_RTC_ISR); -} - -/**************************************************************************** - * Name: rtc_bin2bcd - * - * Description: - * Converts a 2 digit binary to BCD format - * - * Input Parameters: - * value - The byte to be converted. - * - * Returned Value: - * The value in BCD representation - * - ****************************************************************************/ - -static uint32_t rtc_bin2bcd(int value) -{ - uint32_t msbcd = 0; - - while (value >= 10) - { - msbcd++; - value -= 10; - } - - return (msbcd << 4) | value; -} - -/**************************************************************************** - * Name: rtc_bin2bcd - * - * Description: - * Convert from 2 digit BCD to binary. - * - * Input Parameters: - * value - The BCD value to be converted. - * - * Returned Value: - * The value in binary representation - * - ****************************************************************************/ - -static int rtc_bcd2bin(uint32_t value) -{ - uint32_t tens = (value >> 4) * 10; - return (int)(tens + (value & 0x0f)); -} - -/**************************************************************************** - * Name: rtc_setup - * - * Description: - * Performs first time configuration of the RTC. A special value written - * into back-up register 0 will prevent this function from being called on - * sub-sequent resets or power up. - * - * Input Parameters: - * None - * - * Returned Value: - * Zero (OK) on success; a negated errno on failure - * - ****************************************************************************/ - -static int rtc_setup(void) -{ - uint32_t regval; - int ret; - - /* Disable the write protection for RTC registers */ - - rtc_wprunlock(); - - /* Set Initialization mode */ - - ret = rtc_enterinit(); - if (ret == OK) - { - /* Set the 24 hour format by clearing the FMT bit in the RTC - * control register - */ - - regval = getreg32(STM32_RTC_CR); - regval &= ~RTC_CR_FMT; - putreg32(regval, STM32_RTC_CR); - - /* Configure RTC pre-scaler with the required values */ - -#ifdef CONFIG_STM32_RTC_HSECLOCK - /* STMicro app note AN4759 suggests using 7999 and 124 to - * get exactly 1MHz when using the RTC at 8MHz. - */ - - putreg32(((uint32_t)7999 << RTC_PRER_PREDIV_S_SHIFT) | - ((uint32_t)124 << RTC_PRER_PREDIV_A_SHIFT), - STM32_RTC_PRER); -#else - /* Correct values for 32.768 KHz LSE clock and inaccurate LSI clock */ - - putreg32(((uint32_t)0xff << RTC_PRER_PREDIV_S_SHIFT) | - ((uint32_t)0x7f << RTC_PRER_PREDIV_A_SHIFT), - STM32_RTC_PRER); -#endif - - /* Exit RTC initialization mode */ - - rtc_exitinit(); - } - - /* Re-enable the write protection for RTC registers */ - - rtc_wprlock(); - - return ret; -} - -/**************************************************************************** - * Name: rtc_resume - * - * Description: - * Called when the RTC was already initialized on a previous power cycle. - * This just brings the RTC back into full operation. - * - * Input Parameters: - * None - * - * Returned Value: - * Zero (OK) on success; a negated errno on failure - * - ****************************************************************************/ - -static void rtc_resume(void) -{ -#ifdef CONFIG_RTC_ALARM - uint32_t regval; - - /* Clear the RTC alarm flags */ - - regval = getreg32(STM32_RTC_ISR); - regval &= ~(RTC_ISR_ALRAF | RTC_ISR_ALRBF); - putreg32(regval, STM32_RTC_ISR); - - /* Clear the RTC Alarm Pending bit */ - - putreg32(EXTI_RTC_ALARM, STM32_EXTI_PR); -#endif -} - -/**************************************************************************** - * Name: stm32_rtc_alarm_handler - * - * Description: - * RTC ALARM interrupt service routine through the EXTI line - * - * Input Parameters: - * irq - The IRQ number that generated the interrupt - * context - Architecture specific register save information. - * - * Returned Value: - * Zero (OK) on success; A negated errno value on failure. - * - ****************************************************************************/ - -#ifdef CONFIG_RTC_ALARM -static int stm32_rtc_alarm_handler(int irq, void *context, void *arg) -{ - struct alm_cbinfo_s *cbinfo; - alm_callback_t cb; - void *cb_arg; - uint32_t isr; - uint32_t cr; - int ret = OK; - - /* Disable the write protection for RTC registers */ - - rtc_wprunlock(); - - isr = getreg32(STM32_RTC_ISR); - - /* Check for EXTI from Alarm A or B and handle according */ - - if ((isr & RTC_ISR_ALRAF) != 0) - { - cr = getreg32(STM32_RTC_CR); - if ((cr & RTC_CR_ALRAIE) != 0) - { - cbinfo = &g_alarmcb[RTC_ALARMA]; - if (cbinfo->ac_cb != NULL) - { - /* Alarm A callback */ - - cb = cbinfo->ac_cb; - cb_arg = (void *)cbinfo->ac_arg; - - cbinfo->ac_cb = NULL; - cbinfo->ac_arg = NULL; - - cb(cb_arg, RTC_ALARMA); - } - - isr = getreg32(STM32_RTC_ISR) & ~RTC_ISR_ALRAF; - putreg32(isr, STM32_RTC_ISR); - } - } - -#if CONFIG_RTC_NALARMS > 1 - if ((isr & RTC_ISR_ALRBF) != 0) - { - cr = getreg32(STM32_RTC_CR); - if ((cr & RTC_CR_ALRBIE) != 0) - { - cbinfo = &g_alarmcb[RTC_ALARMB]; - if (cbinfo->ac_cb != NULL) - { - /* Alarm B callback */ - - cb = cbinfo->ac_cb; - cb_arg = (void *)cbinfo->ac_arg; - - cbinfo->ac_cb = NULL; - cbinfo->ac_arg = NULL; - - cb(cb_arg, RTC_ALARMB); - } - - isr = getreg32(STM32_RTC_ISR) & ~RTC_ISR_ALRBF; - putreg32(isr, STM32_RTC_ISR); - } - } -#endif - - /* Re-enable the write protection for RTC registers */ - - rtc_wprlock(); - return ret; -} -#endif - -/**************************************************************************** - * Name: rtchw_check_alrXwf X= a or B - * - * Description: - * Check registers - * - * Input Parameters: - * None - * - * Returned Value: - * Zero (OK) on success; a negated errno on failure - * - ****************************************************************************/ - -#ifdef CONFIG_RTC_ALARM -static int rtchw_check_alrawf(void) -{ - volatile uint32_t timeout; - uint32_t regval; - int ret = -ETIMEDOUT; - - /* Check RTC_ISR ALRAWF for access to alarm register, - * Can take 2 RTCCLK cycles or timeout - * CubeMX use GetTick. - */ - - for (timeout = 0; timeout < INITMODE_TIMEOUT; timeout++) - { - regval = getreg32(STM32_RTC_ISR); - if ((regval & RTC_ISR_ALRAWF) != 0) - { - ret = OK; - break; - } - } - - return ret; -} -#endif - -#if defined(CONFIG_RTC_ALARM) && CONFIG_RTC_NALARMS > 1 -static int rtchw_check_alrbwf(void) -{ - volatile uint32_t timeout; - uint32_t regval; - int ret = -ETIMEDOUT; - - /* Check RTC_ISR ALRBWF for access to alarm register, - * can take 2 RTCCLK cycles or timeout - * CubeMX use GetTick. - */ - - for (timeout = 0; timeout < INITMODE_TIMEOUT; timeout++) - { - regval = getreg32(STM32_RTC_ISR); - if ((regval & RTC_ISR_ALRBWF) != 0) - { - ret = OK; - break; - } - } - - return ret; -} -#endif - -/**************************************************************************** - * Name: stm32_rtchw_set_alrmXr X is a or b - * - * Description: - * Set the alarm (A or B) hardware registers, using the required hardware - * access protocol - * - * Input Parameters: - * alarmreg - the register - * - * Returned Value: - * Zero (OK) on success; a negated errno on failure - * - ****************************************************************************/ - -#ifdef CONFIG_RTC_ALARM -static int rtchw_set_alrmar(rtc_alarmreg_t alarmreg) -{ - int ret = -EBUSY; - - /* Disable the write protection for RTC registers */ - - rtc_wprunlock(); - - /* Disable RTC alarm & Interrupt */ - - modifyreg32(STM32_RTC_CR, (RTC_CR_ALRAE | RTC_CR_ALRAIE), 0); - - ret = rtchw_check_alrawf(); - if (ret != OK) - { - goto errout_with_wprunlock; - } - - /* Set the RTC Alarm register */ - - putreg32(alarmreg, STM32_RTC_ALRMAR); - rtcinfo(" ALRMAR: %08" PRIx32 "\n", getreg32(STM32_RTC_ALRMAR)); - - /* Enable RTC alarm */ - - modifyreg32(STM32_RTC_CR, 0, (RTC_CR_ALRAE | RTC_CR_ALRAIE)); - -errout_with_wprunlock: - rtc_wprlock(); - return ret; -} -#endif - -#if defined(CONFIG_RTC_ALARM) && CONFIG_RTC_NALARMS > 1 -static int rtchw_set_alrmbr(rtc_alarmreg_t alarmreg) -{ - int ret = -EBUSY; - - /* Disable the write protection for RTC registers */ - - rtc_wprunlock(); - - /* Disable RTC alarm B & Interrupt B */ - - modifyreg32(STM32_RTC_CR, (RTC_CR_ALRBE | RTC_CR_ALRBIE), 0); - - ret = rtchw_check_alrbwf(); - if (ret != OK) - { - goto rtchw_set_alrmbr_exit; - } - - /* Set the RTC Alarm register */ - - putreg32(alarmreg, STM32_RTC_ALRMBR); - rtcinfo(" ALRMBR: %08" PRIx32 "\n", getreg32(STM32_RTC_ALRMBR)); - - /* Enable RTC alarm B */ - - modifyreg32(STM32_RTC_CR, 0, (RTC_CR_ALRBE | RTC_CR_ALRBIE)); - -rtchw_set_alrmbr_exit: - rtc_wprlock(); - return ret; -} -#endif - -/**************************************************************************** - * Name: rtc_enable_alarm - * - * Description: - * Enable ALARM interrupts - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef CONFIG_RTC_ALARM -static inline void rtc_enable_alarm(void) -{ - /* Is the alarm already enabled? */ - - if (!g_alarm_enabled) - { - /* Configure RTC interrupt to catch alarm interrupts. All RTC - * interrupts are connected to the EXTI controller. To enable the - * RTC Alarm interrupt, the following sequence is required: - * - * 1. Configure and enable the EXTI Line 17 RTC ALARM in interrupt - * mode and select the rising edge sensitivity. - * For STM32F4xx - * EXTI line 21 RTC Tamper & Timestamp - * EXTI line 22 RTC Wakeup - * 2. Configure and enable the RTC_Alarm IRQ channel in the NVIC. - * 3. Configure the RTC to generate RTC alarms (Alarm A or Alarm B). - */ - - stm32_exti_alarm(true, false, true, stm32_rtc_alarm_handler, NULL); - g_alarm_enabled = true; - } -} -#endif - -/**************************************************************************** - * Name: stm32_rtc_getalarmdatetime - * - * Description: - * Get the current date and time for a RTC alarm. - * - * Input Parameters: - * reg - RTC alarm register - * tp - The location to return the high resolution time value. - * - * Returned Value: - * Zero (OK) on success; a negated errno on failure - * - ****************************************************************************/ - -#ifdef CONFIG_RTC_ALARM -static int stm32_rtc_getalarmdatetime(rtc_alarmreg_t reg, struct tm *tp) -{ - uint32_t data; - uint32_t tmp; - - DEBUGASSERT(tp != NULL); - - /* Sample the data time register. */ - - data = getreg32(reg); - - /* Convert the RTC time to fields in struct tm format. All of the STM32 - * ranges of values correspond between struct tm and the time register. - */ - - tmp = (data & (RTC_ALRMR_SU_MASK | RTC_ALRMR_ST_MASK)) >> - RTC_ALRMR_SU_SHIFT; - tp->tm_sec = rtc_bcd2bin(tmp); - - tmp = (data & (RTC_ALRMR_MNU_MASK | RTC_ALRMR_MNT_MASK)) >> - RTC_ALRMR_MNU_SHIFT; - tp->tm_min = rtc_bcd2bin(tmp); - - tmp = (data & (RTC_ALRMR_HU_MASK | RTC_ALRMR_HT_MASK)) >> - RTC_ALRMR_HU_SHIFT; - tp->tm_hour = rtc_bcd2bin(tmp); - - tmp = (data & (RTC_ALRMR_DU_MASK | RTC_ALRMR_DT_MASK)) >> - RTC_ALRMR_DU_SHIFT; - tp->tm_mday = rtc_bcd2bin(tmp); - - return OK; -} -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: up_rtc_initialize - * - * Description: - * Initialize the hardware RTC per the selected configuration. This - * function is called once during the OS initialization sequence - * - * Input Parameters: - * None - * - * Returned Value: - * Zero (OK) on success; a negated errno on failure - * - ****************************************************************************/ - -int up_rtc_initialize(void) -{ - uint32_t regval; - uint32_t tr_bkp; - uint32_t dr_bkp; - int ret; - int maxretry = 10; - int nretry = 0; - - /* Clocking for the PWR block must be provided. However, this is done - * unconditionally in stm32f40xxx_rcc.c on power up. This done - * unconditionally because the PWR block is also needed to set the - * internal voltage regulator for maximum performance. - */ - - /* Select the clock source */ - - /* Save the token before losing it when resetting */ - - regval = getreg32(RTC_MAGIC_REG); - - stm32_pwr_enablebkp(true); - - if (regval != RTC_MAGIC && regval != RTC_MAGIC_TIME_SET) - { - /* Some boards do not have the external 32khz oscillator installed, - * for those boards we must fallback to the crummy internal RC clock - * or the external high rate clock - */ - -#ifdef CONFIG_STM32_RTC_HSECLOCK - /* Use the HSE clock as the input to the RTC block */ - - rtc_dumpregs("On reset HSE"); - modifyreg32(STM32_RCC_XXX, RCC_XXX_RTCSEL_MASK, RCC_XXX_RTCSEL_HSE); - -#elif defined(CONFIG_STM32_RTC_LSICLOCK) - /* Use the LSI clock as the input to the RTC block */ - - rtc_dumpregs("On reset LSI"); - modifyreg32(STM32_RCC_XXX, RCC_XXX_RTCSEL_MASK, RCC_XXX_RTCSEL_LSI); - -#elif defined(CONFIG_STM32_RTC_LSECLOCK) - /* Use the LSE clock as the input to the RTC block */ - - rtc_dumpregs("On reset LSE"); - modifyreg32(STM32_RCC_XXX, RCC_XXX_RTCSEL_MASK, RCC_XXX_RTCSEL_LSE); - -#endif - /* Enable the RTC Clock by setting the RTCEN bit in the RCC register */ - - modifyreg32(STM32_RCC_XXX, 0, RCC_XXX_RTCEN); - } - else /* The RTC is already in use: check if the clock source is changed */ - { -#if defined(CONFIG_STM32_RTC_HSECLOCK) || defined(CONFIG_STM32_RTC_LSICLOCK) || \ - defined(CONFIG_STM32_RTC_LSECLOCK) - - uint32_t clksrc = getreg32(STM32_RCC_XXX); - - rtc_dumpregs("On reset warm"); - -#if defined(CONFIG_STM32_RTC_HSECLOCK) - if ((clksrc & RCC_XXX_RTCSEL_MASK) != RCC_XXX_RTCSEL_HSE) -#elif defined(CONFIG_STM32_RTC_LSICLOCK) - if ((clksrc & RCC_XXX_RTCSEL_MASK) != RCC_XXX_RTCSEL_LSI) -#elif defined(CONFIG_STM32_RTC_LSECLOCK) - if ((clksrc & RCC_XXX_RTCSEL_MASK) != RCC_XXX_RTCSEL_LSE) -#endif -#endif - { - tr_bkp = getreg32(STM32_RTC_TR); - dr_bkp = getreg32(STM32_RTC_DR); - modifyreg32(STM32_RCC_XXX, 0, RCC_XXX_YYYRST); - modifyreg32(STM32_RCC_XXX, RCC_XXX_YYYRST, 0); - -#if defined(CONFIG_STM32_RTC_HSECLOCK) - /* Change to the new clock as the input to the RTC block */ - - modifyreg32(STM32_RCC_XXX, RCC_XXX_RTCSEL_MASK, - RCC_XXX_RTCSEL_HSE); - -#elif defined(CONFIG_STM32_RTC_LSICLOCK) - modifyreg32(STM32_RCC_XXX, RCC_XXX_RTCSEL_MASK, - RCC_XXX_RTCSEL_LSI); - -#elif defined(CONFIG_STM32_RTC_LSECLOCK) - modifyreg32(STM32_RCC_XXX, RCC_XXX_RTCSEL_MASK, - RCC_XXX_RTCSEL_LSE); -#endif - - putreg32(tr_bkp, STM32_RTC_TR); - putreg32(dr_bkp, STM32_RTC_DR); - - /* Remember that the RTC is initialized */ - - putreg32(RTC_MAGIC, RTC_MAGIC_REG); - - /* Enable the RTC Clock by setting the RTCEN bit in the RCC - * register - */ - - modifyreg32(STM32_RCC_XXX, 0, RCC_XXX_RTCEN); - } - } - - stm32_pwr_enablebkp(false); - - /* Loop, attempting to initialize/resume the RTC. This loop is necessary - * because it seems that occasionally it takes longer to initialize the RTC - * (the actual failure is in rtc_synchwait()). - */ - - do - { - /* Wait for the RTC Time and Date registers to be synchronized with RTC - * APB clock. - */ - - ret = rtc_synchwait(); - - /* Check that rtc_syncwait() returned successfully */ - - switch (ret) - { - case OK: - { - rtcinfo("rtc_syncwait() okay\n"); - break; - } - - default: - { - rtcerr("ERROR: rtc_syncwait() failed (%d)\n", ret); - break; - } - } - } - while (ret != OK && ++nretry < maxretry); - - /* Check if the one-time initialization of the RTC has already been - * performed. We can determine this by checking if the magic number - * has been written to the back-up date register DR0. - */ - - if (regval != RTC_MAGIC && regval != RTC_MAGIC_TIME_SET) - { - rtcinfo("Do setup\n"); - - /* Perform the one-time setup of the LSE clocking to the RTC */ - - ret = rtc_setup(); - - /* Enable write access to the backup domain (RTC registers, RTC - * backup data registers and backup SRAM). - */ - - stm32_pwr_enablebkp(true); - - /* Remember that the RTC is initialized */ - - putreg32(RTC_MAGIC, RTC_MAGIC_REG); - - /* Disable write access to the backup domain (RTC registers, RTC - * backup data registers and backup SRAM). - */ - - stm32_pwr_enablebkp(false); - } - else - { - rtcinfo("Do resume\n"); - - /* RTC already set-up, just resume normal operation */ - - rtc_resume(); - rtc_dumpregs("Did resume"); - } - - if (ret != OK && nretry > 0) - { - rtcinfo("setup/resume ran %d times and failed with %d\n", - nretry, ret); - return -ETIMEDOUT; - } - - rtc_dumpregs("After Initialization"); - - g_rtc_enabled = true; - return OK; -} - -/**************************************************************************** - * Name: stm32_rtc_irqinitialize - * - * Description: - * Initialize IRQs for RTC, not possible during up_rtc_initialize because - * up_irqinitialize is called later. - * - * Input Parameters: - * None - * - * Returned Value: - * Zero (OK) on success; a negated errno on failure - * - ****************************************************************************/ - -int stm32_rtc_irqinitialize(void) -{ - /* Nothing to do */ - - return OK; -} - -/**************************************************************************** - * Name: stm32_rtc_getdatetime_with_subseconds - * - * Description: - * Get the current date and time from the date/time RTC. This interface - * is only supported by the date/time RTC hardware implementation. - * It is used to replace the system timer. It is only used by the RTOS - * during initialization to set up the system time when CONFIG_RTC and - * CONFIG_RTC_DATETIME are selected (and CONFIG_RTC_HIRES is not). - * - * NOTE: Some date/time RTC hardware is capability of sub-second accuracy. - * That sub-second accuracy is returned through 'nsec'. - * - * Input Parameters: - * tp - The location to return the high resolution time value. - * nsec - The location to return the subsecond time value. - * - * Returned Value: - * Zero (OK) on success; a negated errno on failure - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_HAVE_RTC_SUBSECONDS -int stm32_rtc_getdatetime_with_subseconds(struct tm *tp, long *nsec) -#else -int up_rtc_getdatetime(struct tm *tp) -#endif -{ -#ifdef CONFIG_STM32_HAVE_RTC_SUBSECONDS - uint32_t ssr; -#endif - uint32_t dr; - uint32_t tr; - uint32_t tmp; - - /* Sample the data time registers. There is a race condition here... If - * we sample the time just before midnight on December 31, the date could - * be wrong because the day rolled over while were sampling. Thus loop for - * checking overflow here is needed. There is a race condition with - * subseconds too. If we sample TR register just before second rolling - * and subseconds are read at wrong second, we get wrong time. - */ - - do - { - dr = getreg32(STM32_RTC_DR); - tr = getreg32(STM32_RTC_TR); -#ifdef CONFIG_STM32_HAVE_RTC_SUBSECONDS - ssr = getreg32(STM32_RTC_SSR); - tmp = getreg32(STM32_RTC_TR); - if (tmp != tr) - { - continue; - } -#endif - - tmp = getreg32(STM32_RTC_DR); - if (tmp == dr) - { - break; - } - } - while (1); - - rtc_dumpregs("Reading Time"); - - /* Convert the RTC time to fields in struct tm format. All of the STM32 - * ranges of values correspond between struct tm and the time register. - */ - - tmp = (tr & (RTC_TR_SU_MASK | RTC_TR_ST_MASK)) >> RTC_TR_SU_SHIFT; - tp->tm_sec = rtc_bcd2bin(tmp); - - tmp = (tr & (RTC_TR_MNU_MASK | RTC_TR_MNT_MASK)) >> RTC_TR_MNU_SHIFT; - tp->tm_min = rtc_bcd2bin(tmp); - - tmp = (tr & (RTC_TR_HU_MASK | RTC_TR_HT_MASK)) >> RTC_TR_HU_SHIFT; - tp->tm_hour = rtc_bcd2bin(tmp); - - /* Now convert the RTC date to fields in struct tm format: - * Days: 1-31 match in both cases. - * Month: STM32 is 1-12, struct tm is 0-11. - * Years: STM32 is 00-99, struct tm is years since 1900. - * WeekDay: STM32 is 1 = Mon - 7 = Sun - * - * Issue: I am not sure what the STM32 years mean. Are these the - * years 2000-2099? I'll assume so. - */ - - tmp = (dr & (RTC_DR_DU_MASK | RTC_DR_DT_MASK)) >> RTC_DR_DU_SHIFT; - tp->tm_mday = rtc_bcd2bin(tmp); - - tmp = (dr & (RTC_DR_MU_MASK | RTC_DR_MT)) >> RTC_DR_MU_SHIFT; - tp->tm_mon = rtc_bcd2bin(tmp) - 1; - - tmp = (dr & (RTC_DR_YU_MASK | RTC_DR_YT_MASK)) >> RTC_DR_YU_SHIFT; - tp->tm_year = rtc_bcd2bin(tmp) + 100; - - tmp = (dr & RTC_DR_WDU_MASK) >> RTC_DR_WDU_SHIFT; - tp->tm_wday = tmp % 7; - tp->tm_yday = tp->tm_mday - 1 + - clock_daysbeforemonth(tp->tm_mon, - clock_isleapyear(tp->tm_year + 1900)); - tp->tm_isdst = 0; - -#ifdef CONFIG_STM32_HAVE_RTC_SUBSECONDS - /* Return RTC sub-seconds if no configured and if a non-NULL value - * of nsec has been provided to receive the sub-second value. - */ - - if (nsec) - { - uint32_t prediv_s; - uint32_t usecs; - - prediv_s = getreg32(STM32_RTC_PRER) & RTC_PRER_PREDIV_S_MASK; - prediv_s >>= RTC_PRER_PREDIV_S_SHIFT; - - ssr &= RTC_SSR_MASK; - - /* Maximum prediv_s is 0x7fff, thus we can multiply by 100000 and - * still fit 32-bit unsigned integer. - */ - - usecs = (((prediv_s - ssr) * 100000) / (prediv_s + 1)) * 10; - *nsec = usecs * 1000; - } -#endif /* CONFIG_STM32_HAVE_RTC_SUBSECONDS */ - - rtc_dumptime((const struct tm *)tp, "Returning"); - return OK; -} - -/**************************************************************************** - * Name: up_rtc_getdatetime - * - * Description: - * Get the current date and time from the date/time RTC. This interface - * is only supported by the date/time RTC hardware implementation. - * It is used to replace the system timer. It is only used by the RTOS - * during initialization to set up the system time when CONFIG_RTC and - * CONFIG_RTC_DATETIME are selected (and CONFIG_RTC_HIRES is not). - * - * NOTE: Some date/time RTC hardware is capability of sub-second accuracy. - * That sub-second accuracy is lost in this interface. However, since the - * system time is reinitialized on each power-up/reset, there will be no - * timing inaccuracy in the long run. - * - * Input Parameters: - * tp - The location to return the high resolution time value. - * - * Returned Value: - * Zero (OK) on success; a negated errno on failure - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_HAVE_RTC_SUBSECONDS -int up_rtc_getdatetime(struct tm *tp) -{ - return stm32_rtc_getdatetime_with_subseconds(tp, NULL); -} -#endif - -/**************************************************************************** - * Name: stm32_rtc_setdatetime - * - * Description: - * Set the RTC to the provided time. RTC implementations which provide - * up_rtc_getdatetime() (CONFIG_RTC_DATETIME is selected) should provide - * this function. - * - * Input Parameters: - * tp - the time to use - * - * Returned Value: - * Zero (OK) on success; a negated errno on failure - * - ****************************************************************************/ - -int stm32_rtc_setdatetime(const struct tm *tp) -{ - uint32_t tr; - uint32_t dr; - int ret; - - rtc_dumptime(tp, "Setting time"); - - /* Then write the broken out values to the RTC */ - - /* Convert the struct tm format to RTC time register fields. - * All of the ranges of values correspond between struct tm and the time - * register. - */ - - tr = (rtc_bin2bcd(tp->tm_sec) << RTC_TR_SU_SHIFT) | - (rtc_bin2bcd(tp->tm_min) << RTC_TR_MNU_SHIFT) | - (rtc_bin2bcd(tp->tm_hour) << RTC_TR_HU_SHIFT); - - /* Now convert the fields in struct tm format to the RTC date register - * fields: - * - * Days: 1-31 match in both cases. - * Month: STM32 is 1-12, struct tm is 0-11. - * Years: STM32 is 00-99, struct tm is years since 1900. - * WeekDay: STM32 is 1 = Mon - 7 = Sun - * - * Issue: I am not sure what the STM32 years mean. Are these the - * years 2000-2099? I'll assume so. - */ - - dr = (rtc_bin2bcd(tp->tm_mday) << RTC_DR_DU_SHIFT) | - ((rtc_bin2bcd(tp->tm_mon + 1)) << RTC_DR_MU_SHIFT) | - ((tp->tm_wday == 0 ? 7 : (tp->tm_wday & 7)) << RTC_DR_WDU_SHIFT) | - ((rtc_bin2bcd(tp->tm_year - 100)) << RTC_DR_YU_SHIFT); - - dr &= ~RTC_DR_RESERVED_BITS; - - /* Disable the write protection for RTC registers */ - - rtc_wprunlock(); - - /* Set Initialization mode */ - - ret = rtc_enterinit(); - if (ret == OK) - { - /* Set the RTC TR and DR registers */ - - putreg32(tr, STM32_RTC_TR); - putreg32(dr, STM32_RTC_DR); - - /* Exit Initialization mode and wait for the RTC Time and Date - * registers to be synchronized with RTC APB clock. - */ - - rtc_exitinit(); - ret = rtc_synchwait(); - } - - /* Remember that the RTC is initialized and had its time set. */ - - if (getreg32(RTC_MAGIC_REG) != RTC_MAGIC_TIME_SET) - { - stm32_pwr_enablebkp(true); - putreg32(RTC_MAGIC_TIME_SET, RTC_MAGIC_REG); - stm32_pwr_enablebkp(false); - } - - /* Re-enable the write protection for RTC registers */ - - rtc_wprlock(); - rtc_dumpregs("New time setting"); - return ret; -} - -/**************************************************************************** - * Name: up_rtc_settime - * - * Description: - * Set the RTC to the provided time. All RTC implementations must be able - * to set their time based on a standard timespec. - * - * Input Parameters: - * tp - the time to use - * - * Returned Value: - * Zero (OK) on success; a negated errno on failure - * - ****************************************************************************/ - -int up_rtc_settime(const struct timespec *tp) -{ - struct tm newtime; - - /* Break out the time values (not that the time is set only to units of - * seconds) - */ - - gmtime_r(&tp->tv_sec, &newtime); - return stm32_rtc_setdatetime(&newtime); -} - -/**************************************************************************** - * Name: stm32_rtc_setalarm - * - * Description: - * Set an alarm to an absolute time using associated hardware. - * - * Input Parameters: - * alminfo - Information about the alarm configuration. - * - * Returned Value: - * Zero (OK) on success; a negated errno on failure - * - ****************************************************************************/ - -#ifdef CONFIG_RTC_ALARM -int stm32_rtc_setalarm(struct alm_setalarm_s *alminfo) -{ - struct alm_cbinfo_s *cbinfo; - rtc_alarmreg_t alarmreg; - int ret = -EINVAL; - - DEBUGASSERT(alminfo != NULL); - DEBUGASSERT(RTC_ALARM_LAST > alminfo->as_id); - - /* Make sure the alarm interrupt is enabled at the NVIC */ - - rtc_enable_alarm(); - - /* REVISIT: Should test that the time is in the future */ - - rtc_dumptime(&alminfo->as_time, "New alarm time"); - - /* Break out the values to the HW alarm register format. The values in - * all STM32 fields match the fields of struct tm in this case. Notice - * that the alarm is limited to one month. - */ - - alarmreg = (rtc_bin2bcd(alminfo->as_time.tm_sec) << RTC_ALRMR_SU_SHIFT) | - (rtc_bin2bcd(alminfo->as_time.tm_min) << RTC_ALRMR_MNU_SHIFT) | - (rtc_bin2bcd(alminfo->as_time.tm_hour) << RTC_ALRMR_HU_SHIFT) | - (rtc_bin2bcd(alminfo->as_time.tm_mday) << RTC_ALRMR_DU_SHIFT); - - /* Set the alarm in hardware and enable interrupts from the RTC */ - - switch (alminfo->as_id) - { - case RTC_ALARMA: - { - cbinfo = &g_alarmcb[RTC_ALARMA]; - cbinfo->ac_cb = alminfo->as_cb; - cbinfo->ac_arg = alminfo->as_arg; - - ret = rtchw_set_alrmar(alarmreg | RTC_ALRMR_ENABLE); - if (ret < 0) - { - cbinfo->ac_cb = NULL; - cbinfo->ac_arg = NULL; - } - - rtc_dumpregs("Set AlarmA"); - } - break; - -#if CONFIG_RTC_NALARMS > 1 - case RTC_ALARMB: - { - cbinfo = &g_alarmcb[RTC_ALARMB]; - cbinfo->ac_cb = alminfo->as_cb; - cbinfo->ac_arg = alminfo->as_arg; - - ret = rtchw_set_alrmbr(alarmreg | RTC_ALRMR_ENABLE); - if (ret < 0) - { - cbinfo->ac_cb = NULL; - cbinfo->ac_arg = NULL; - } - - rtc_dumpregs("Set AlarmB"); - } - break; -#endif - - default: - rtcerr("ERROR: Invalid ALARM%d\n", alminfo->as_id); - break; - } - - return ret; -} -#endif - -/**************************************************************************** - * Name: stm32_rtc_cancelalarm - * - * Description: - * Cancel an alarm. - * - * Input Parameters: - * alarmid - Identifies the alarm to be cancelled - * - * Returned Value: - * Zero (OK) on success; a negated errno on failure - * - ****************************************************************************/ - -#ifdef CONFIG_RTC_ALARM -int stm32_rtc_cancelalarm(enum alm_id_e alarmid) -{ - int ret = -EINVAL; - - DEBUGASSERT(RTC_ALARM_LAST > alarmid); - - /* Cancel the alarm in hardware and disable interrupts */ - - switch (alarmid) - { - case RTC_ALARMA: - { - /* Cancel the global callback function */ - - g_alarmcb[alarmid].ac_cb = NULL; - g_alarmcb[alarmid].ac_arg = NULL; - - /* Disable the write protection for RTC registers */ - - rtc_wprunlock(); - - /* Disable RTC alarm and interrupt */ - - modifyreg32(STM32_RTC_CR, (RTC_CR_ALRAE | RTC_CR_ALRAIE), 0); - - ret = rtchw_check_alrawf(); - if (ret < 0) - { - goto errout_with_wprunlock; - } - - /* Unset the alarm */ - - putreg32(-1, STM32_RTC_ALRMAR); - rtc_wprlock(); - ret = OK; - } - break; - -#if CONFIG_RTC_NALARMS > 1 - case RTC_ALARMB: - { - /* Cancel the global callback function */ - - g_alarmcb[alarmid].ac_cb = NULL; - g_alarmcb[alarmid].ac_arg = NULL; - - /* Disable the write protection for RTC registers */ - - rtc_wprunlock(); - - /* Disable RTC alarm and interrupt */ - - modifyreg32(STM32_RTC_CR, (RTC_CR_ALRBE | RTC_CR_ALRBIE), 0); - - ret = rtchw_check_alrbwf(); - if (ret < 0) - { - goto errout_with_wprunlock; - } - - /* Unset the alarm */ - - putreg32(-1, STM32_RTC_ALRMBR); - rtc_wprlock(); - ret = OK; - } - break; -#endif - - default: - rtcerr("ERROR: Invalid ALARM%d\n", alarmid); - break; - } - - return ret; - -errout_with_wprunlock: - rtc_wprlock(); - return ret; -} -#endif - -/**************************************************************************** - * Name: stm32_rtc_rdalarm - * - * Description: - * Query an alarm configured in hardware. - * - * Input Parameters: - * alminfo - Information about the alarm configuration. - * - * Returned Value: - * Zero (OK) on success; a negated errno on failure - * - ****************************************************************************/ - -#ifdef CONFIG_RTC_ALARM -int stm32_rtc_rdalarm(struct alm_rdalarm_s *alminfo) -{ - rtc_alarmreg_t alarmreg; - int ret = -EINVAL; - - DEBUGASSERT(alminfo != NULL); - DEBUGASSERT(RTC_ALARM_LAST > alminfo->ar_id); - - switch (alminfo->ar_id) - { - case RTC_ALARMA: - { - alarmreg = STM32_RTC_ALRMAR; - ret = stm32_rtc_getalarmdatetime(alarmreg, - (struct tm *)alminfo->ar_time); - } - break; - -#if CONFIG_RTC_NALARMS > 1 - case RTC_ALARMB: - { - alarmreg = STM32_RTC_ALRMBR; - ret = stm32_rtc_getalarmdatetime(alarmreg, - (struct tm *)alminfo->ar_time); - } - break; -#endif - - default: - rtcerr("ERROR: Invalid ALARM%d\n", alminfo->ar_id); - break; - } - - return ret; -} -#endif - -#endif /* CONFIG_STM32_RTC */ diff --git a/arch/arm/src/stm32/stm32g4xxx_flash.c b/arch/arm/src/stm32/stm32g4xxx_flash.c deleted file mode 100644 index c14dd875a9ab5..0000000000000 --- a/arch/arm/src/stm32/stm32g4xxx_flash.c +++ /dev/null @@ -1,618 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32g4xxx_flash.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* Provides standard flash access functions, to be used by the flash mtd - * driver. The interface is defined in the include/nuttx/progmem.h - * - * Notes about this implementation: - * - HSI16 is automatically turned ON by MCU, if not enabled beforehand - * - Only Standard Programming is supported, no Fast Programming. - * - Low Power Modes are not permitted during write/erase - */ - -/* Differences vs STM32L4 (used as template): - * 1. FLASH_CR - Bits (29:28) (SEC_PROT2, SEC_PROT1) added. - * 2. FLASH_ECCR - Bits (29:28) (ECCD2, ECCC2) added. - * Note: Bits are set by hardware. Nothing to do - * 3. FLASH_OPTR - - * a. DUALBANK moved from bit 21 to 22. - * b. NRST_MODE added - Bits 29:28 - * c. IRHEN added - Bit 30 - * 4. FLASH_SEC1R - (New) Secure Area Bank 1 Register - * a. BOOT_LOCK - Forces boot from user flash area - * b. SEC_SIZE1[7:0] - Starts at 0x80000000, size = SEC_SIZE1 * page_size - * 5. FLASH_SEC2R - (New) Secure Area Bank 2 Register - * a. BOOT_LOCK - Forces boot from user flash area - * b. SEC_SIZE1[7:0] - Starts at 0x80000000, size = SEC_SIZE1 * page_size - * 6. FLASH_PAGE_SIZE - The page size of the STM32G47XX and STM32G48XX - * is dependent on the DBANK bit. If Dual Banks are used, the page size - * is 2K. If a single bank is used, the page size is 4K. - */ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include - -#include "stm32_rcc.h" -#include "stm32_waste.h" -#include "stm32_flash.h" -#include "arm_internal.h" - -#if !(defined(CONFIG_STM32_STM32G43XX) || defined(CONFIG_STM32_STM32G47XX) || \ - defined(CONFIG_STM32_STM32G48XX) || defined(CONFIG_STM32_STM32G49XX)) -# error "Unrecognized STM32 chip" -#endif - -#if !defined(CONFIG_STM32_FLASH_CONFIG_DEFAULT) -# warning "Flash Configuration has been overridden - make sure it is correct" -#endif - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#define FLASH_KEY1 0x45670123 -#define FLASH_KEY2 0xCDEF89AB -#define FLASH_ERASEDVALUE 0xffu - -#define OPTBYTES_KEY1 0x08192A3B -#define OPTBYTES_KEY2 0x4C5D6E7F - -#define FLASH_CR_PAGE_ERASE FLASH_CR_PER -#define FLASH_SR_WRITE_PROTECTION_ERROR FLASH_SR_WRPERR - -/* All errors for Standard Programming, not for other operations. */ - -#define FLASH_SR_ALLERRS (FLASH_SR_PGSERR | FLASH_SR_SIZERR | \ - FLASH_SR_PGAERR | FLASH_SR_WRPERR | \ - FLASH_SR_PROGERR) - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -static mutex_t g_lock = NXMUTEX_INITIALIZER; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -static uint32_t get_flash_page_size(void) -{ -#if defined(CONFIG_STM32_STM32G47XX) || defined(CONFIG_STM32_STM32G48XX) - if (getreg32(STM32_FLASH_OPTR) & FLASH_OPTR_DBANK) - { - return 2048; - } - else - { - return 4096; - } -#else - return STM32_FLASH_PAGESIZE; -#endif -} - -static uint32_t get_flash_npages(void) -{ -#if defined(CONFIG_STM32_STM32G47XX) || defined(CONFIG_STM32_STM32G48XX) - if (getreg32(STM32_FLASH_OPTR) & FLASH_OPTR_DBANK) - { - return STM32_FLASH_SIZE / 2048; - } - else - { - return STM32_FLASH_SIZE / 4096; - } -#else - return STM32_FLASH_NPAGES; -#endif -} - -static void flash_unlock(void) -{ - while (getreg32(STM32_FLASH_SR) & FLASH_SR_BSY) - { - stm32_waste(); - } - - if (getreg32(STM32_FLASH_CR) & FLASH_CR_LOCK) - { - /* Unlock sequence */ - - putreg32(FLASH_KEY1, STM32_FLASH_KEYR); - putreg32(FLASH_KEY2, STM32_FLASH_KEYR); - } -} - -static void flash_lock(void) -{ - modifyreg32(STM32_FLASH_CR, 0, FLASH_CR_LOCK); -} - -static void flash_optbytes_unlock(void) -{ - flash_unlock(); - - if (getreg32(STM32_FLASH_CR) & FLASH_CR_OPTLOCK) - { - /* Unlock Option Bytes sequence */ - - putreg32(OPTBYTES_KEY1, STM32_FLASH_OPTKEYR); - putreg32(OPTBYTES_KEY2, STM32_FLASH_OPTKEYR); - } -} - -static inline void flash_optbytes_lock(void) -{ - /* We don't need to set OPTLOCK here as it is automatically - * set by MCU when flash_lock() sets LOCK. - */ - - flash_lock(); -} - -static inline void flash_erase(size_t page) -{ - finfo("erase page %u\n", page); - - modifyreg32(STM32_FLASH_CR, 0, FLASH_CR_PAGE_ERASE); - - modifyreg32(STM32_FLASH_CR, FLASH_CR_PNB_MASK, - FLASH_CR_PNB(page)); - -#if (defined(CONFIG_STM32_STM32G47XX) || \ - defined(CONFIG_STM32_STM32G48XX)) - uint32_t half_npages = get_flash_npages() / 2; - - if (getreg32(STM32_FLASH_OPTR) & FLASH_OPTR_DBANK) - { - if (page < half_npages) - { - /* Select bank 1 */ - - modifyreg32(STM32_FLASH_CR, FLASH_CR_BKER, 0); - } - else - { - /* Select bank 2 */ - - modifyreg32(STM32_FLASH_CR, 0, FLASH_CR_BKER); - } - } -#endif - - modifyreg32(STM32_FLASH_CR, 0, FLASH_CR_START); - - while (getreg32(STM32_FLASH_SR) & FLASH_SR_BSY) - { - stm32_waste(); - } - - modifyreg32(STM32_FLASH_CR, FLASH_CR_PAGE_ERASE, 0); -} - -#if defined(CONFIG_STM32_FLASH_WORKAROUND_DATA_CACHE_CORRUPTION_ON_RWW) -static void data_cache_disable(void) -{ - modifyreg32(STM32_FLASH_ACR, FLASH_ACR_DCEN, 0); -} - -static void data_cache_enable(void) -{ - /* Reset data cache */ - - modifyreg32(STM32_FLASH_ACR, 0, FLASH_ACR_DCRST); - - /* Enable data cache */ - - modifyreg32(STM32_FLASH_ACR, 0, FLASH_ACR_DCEN); -} -#endif /* defined(CONFIG_STM32_FLASH_WORKAROUND_DATA_CACHE_CORRUPTION_ON_RWW) */ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -int stm32_flash_unlock(void) -{ - int ret; - - ret = nxmutex_lock(&g_lock); - if (ret < 0) - { - return ret; - } - - flash_unlock(); - nxmutex_unlock(&g_lock); - - return ret; -} - -int stm32_flash_lock(void) -{ - int ret; - - ret = nxmutex_lock(&g_lock); - if (ret < 0) - { - return ret; - } - - flash_lock(); - nxmutex_unlock(&g_lock); - - return ret; -} - -uint32_t stm32_flash_user_optbytes(uint32_t clrbits, uint32_t setbits) -{ - uint32_t regval; - int ret; - - /* To avoid accidents, do not allow setting RDP via this function. - * Remove these asserts if want to enable changing the protection level. - * WARNING: level 2 protection is permanent! - */ - - DEBUGASSERT((clrbits & FLASH_OPTR_RDP_MASK) == 0); - DEBUGASSERT((setbits & FLASH_OPTR_RDP_MASK) == 0); - - ret = nxmutex_lock(&g_lock); - if (ret < 0) - { - return 0; - } - - flash_optbytes_unlock(); - - /* Modify Option Bytes in register. */ - - regval = getreg32(STM32_FLASH_OPTR); - - finfo("Flash option bytes before: 0x%" PRIx32 "\n", regval); - - regval = (regval & ~clrbits) | setbits; - - putreg32(regval, STM32_FLASH_OPTR); - - finfo("Flash option bytes after: 0x%" PRIx32 "\n", regval); - - /* Start Option Bytes programming and wait for completion. */ - - modifyreg32(STM32_FLASH_CR, 0, FLASH_CR_OPTSTRT); - - while (getreg32(STM32_FLASH_SR) & FLASH_SR_BSY) - { - stm32_waste(); - } - - flash_optbytes_lock(); - nxmutex_unlock(&g_lock); - - return regval; -} - -size_t up_progmem_pagesize(size_t page) -{ - return get_flash_page_size(); -} - -size_t up_progmem_erasesize(size_t block) -{ - return get_flash_page_size(); -} - -ssize_t up_progmem_getpage(size_t addr) -{ - if (addr >= STM32_FLASH_BASE) - { - addr -= STM32_FLASH_BASE; - } - - if (addr >= STM32_FLASH_SIZE) - { - return -EFAULT; - } - - return addr / get_flash_page_size(); -} - -size_t up_progmem_getaddress(size_t page) -{ - if (page >= get_flash_npages()) - { - return SIZE_MAX; - } - - return page * get_flash_page_size() + STM32_FLASH_BASE; -} - -size_t up_progmem_neraseblocks(void) -{ - return get_flash_npages(); -} - -bool up_progmem_isuniform(void) -{ - return true; -} - -ssize_t up_progmem_eraseblock(size_t block) -{ - int ret; - - if (block >= get_flash_npages()) - { - return -EFAULT; - } - - /* Erase single block */ - - ret = nxmutex_lock(&g_lock); - if (ret < 0) - { - return (ssize_t)ret; - } - - flash_unlock(); - - flash_erase(block); - - flash_lock(); - nxmutex_unlock(&g_lock); - - /* Verify */ - - if (up_progmem_ispageerased(block) == 0) - { - return up_progmem_erasesize(block); - } - else - { - return -EIO; - } -} - -ssize_t up_progmem_ispageerased(size_t page) -{ - size_t addr; - size_t count; - size_t bwritten = 0; - - if (page >= get_flash_npages()) - { - return -EFAULT; - } - - /* Verify */ - - for (addr = up_progmem_getaddress(page), count = up_progmem_pagesize(page); - count; count--, addr++) - { - if (getreg8(addr) != FLASH_ERASEDVALUE) - { - bwritten++; - } - } - - return bwritten; -} - -ssize_t up_progmem_write(size_t addr, const void *buf, size_t buflen) -{ - uint32_t *dest; - const uint32_t *src; - size_t written; - size_t xfrsize; - size_t offset; - size_t page; - bool set_pg_bit = false; - int i; - int ret = OK; - const uint32_t flash_page_size = get_flash_page_size(); - const uint32_t flash_page_words = flash_page_size / 4; - const uint32_t flash_page_mask = flash_page_size - 1; - uint32_t *page_buffer = NULL; - - /* Check for valid address range. */ - - offset = addr; - if (addr >= STM32_FLASH_BASE) - { - offset -= STM32_FLASH_BASE; - } - - if (offset + buflen > STM32_FLASH_SIZE) - { - return -EFAULT; - } - - /* Get the page number corresponding to the flash offset and the byte - * offset into the page. Align write destination to page boundary. - */ - - if (flash_page_size == 4096) - { - page = ((uint32_t)offset >> 12); - } - else - { - page = ((uint32_t)offset >> 11); - } - - offset &= flash_page_mask; - - dest = (uint32_t *)((uint8_t *)addr - offset); - written = 0; - - ret = nxmutex_lock(&g_lock); - if (ret < 0) - { - return (ssize_t)ret; - } - - /* Get flash ready and begin flashing. */ - - flash_unlock(); - - /* Loop until all of the data has been written */ - - while (buflen > 0) - { - /* How much can we write into this page? */ - - xfrsize = MIN((size_t) flash_page_size - offset, buflen); - - /* Do we need to use the intermediate buffer? */ - - if (offset == 0 && xfrsize == flash_page_size) - { - /* No, we can take the data directly from the user buffer */ - - src = (const uint32_t *)buf; - } - else - { - /* Yes, copy data into the page buffer */ - - page_buffer = malloc(flash_page_size); - - if (offset > 0) - { - memcpy(page_buffer, dest, offset); - } - - memcpy((uint8_t *)page_buffer + offset, buf, xfrsize); - - if (offset + xfrsize < flash_page_size) - { - memcpy((uint8_t *)page_buffer + offset + xfrsize, - (const uint8_t *)dest + offset + xfrsize, - flash_page_size - offset - xfrsize); - } - - src = page_buffer; - } - - /* Erase the page. Unlike most flash chips, STM32 is unable to - * write back existing data read from page without erase. - */ - - flash_erase(page); - - /* Write the page. Must be with double-words. */ - -#if defined(CONFIG_STM32_FLASH_WORKAROUND_DATA_CACHE_CORRUPTION_ON_RWW) - data_cache_disable(); -#endif - - modifyreg32(STM32_FLASH_CR, 0, FLASH_CR_PG); - set_pg_bit = true; - - for (i = 0; i < flash_page_words; i += 2) - { - *dest++ = *src++; - *dest++ = *src++; - - while (getreg32(STM32_FLASH_SR) & FLASH_SR_BSY) - { - stm32_waste(); - } - - /* Verify */ - - if (getreg32(STM32_FLASH_SR) & FLASH_SR_WRITE_PROTECTION_ERROR) - { - ret = -EROFS; - goto out; - } - - if (getreg32(dest -1) != *(src - 1) || - getreg32(dest - 2) != *(src - 2)) - { - ret = -EIO; - goto out; - } - } - - modifyreg32(STM32_FLASH_CR, FLASH_CR_PG, 0); - set_pg_bit = false; - -#if defined(CONFIG_STM32_FLASH_WORKAROUND_DATA_CACHE_CORRUPTION_ON_RWW) - data_cache_enable(); -#endif - - /* Adjust pointers and counts for the next time through the loop */ - - written += xfrsize; - addr += xfrsize; - dest = (uint32_t *)addr; - buf = (void *)((uintptr_t)buf + xfrsize); - buflen -= xfrsize; - page++; - } - -out: - if (set_pg_bit) - { - modifyreg32(STM32_FLASH_CR, FLASH_CR_PG, 0); -#if defined(CONFIG_STM32_FLASH_WORKAROUND_DATA_CACHE_CORRUPTION_ON_RWW) - data_cache_enable(); -#endif - } - - /* If there was an error, clear all error flags in status register (rc_w1 - * register so do this by writing the error bits). - */ - - if (ret != OK) - { - ferr("flash write error: %d, status: 0x%" PRIx32 "\n", - ret, getreg32(STM32_FLASH_SR)); - - modifyreg32(STM32_FLASH_SR, 0, FLASH_SR_ALLERRS); - } - - free(page_buffer); - flash_lock(); - nxmutex_unlock(&g_lock); - return (ret == OK) ? written : ret; -} - -uint8_t up_progmem_erasestate(void) -{ - return FLASH_ERASEDVALUE; -} diff --git a/arch/arm/src/stm32/stm32l15xx_flash.c b/arch/arm/src/stm32/stm32l15xx_flash.c deleted file mode 100644 index 4051a7eafda5d..0000000000000 --- a/arch/arm/src/stm32/stm32l15xx_flash.c +++ /dev/null @@ -1,558 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32l15xx_flash.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* Provides standard flash access functions, to be used by the - * flash mtd driver. - * The interface is defined in the include/nuttx/progmem.h - * - * Requirements during write/erase operations on FLASH: - * - HSI must be ON. - * - Low Power Modes are not permitted during write/erase - */ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include -#include - -#include -#include -#include -#include -#include - -#include "stm32_flash.h" -#include "stm32_rcc.h" -#include "stm32_waste.h" -#include "arm_internal.h" - -/* Only for the STM32L15xx family. */ - -#if defined(CONFIG_STM32_STM32L15XX) - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#define FLASH_KEY1 0x8c9daebf -#define FLASH_KEY2 0x13141516 -#define FLASH_OPTKEY1 0xfbead9c8 -#define FLASH_OPTKEY2 0x24252627 -#define EEPROM_KEY1 0x89abcdef -#define EEPROM_KEY2 0x02030405 - -#define FLASH_SR_WRITE_PROTECTION_ERROR FLASH_SR_WRPERR -#define FLASH_SR_ALLERRS (FLASH_SR_RDERR | FLASH_SR_SIZERR | \ - FLASH_SR_PGAERR | FLASH_SR_WRPERR) - -/* STM32L1 internal flash is based on EEPROM-technology while most others - * are NOR-flash, thus many things are different including the erase value. - */ - -#define FLASH_ERASEDVALUE 0x00 - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -static mutex_t g_lock = NXMUTEX_INITIALIZER; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -static void stm32_eeprom_unlock(void) -{ - while (getreg32(STM32_FLASH_SR) & FLASH_SR_BSY) - { - stm32_waste(); - } - - if (getreg32(STM32_FLASH_PECR) & FLASH_PECR_PELOCK) - { - /* Unlock sequence */ - - putreg32(EEPROM_KEY1, STM32_FLASH_PEKEYR); - putreg32(EEPROM_KEY2, STM32_FLASH_PEKEYR); - } -} - -static void stm32_eeprom_lock(void) -{ - modifyreg32(STM32_FLASH_PECR, 0, FLASH_PECR_PELOCK); -} - -static void flash_unlock(void) -{ - if (getreg32(STM32_FLASH_PECR) & FLASH_PECR_PRGLOCK) - { - stm32_eeprom_unlock(); - - /* Unlock sequence */ - - putreg32(FLASH_KEY1, STM32_FLASH_PRGKEYR); - putreg32(FLASH_KEY2, STM32_FLASH_PRGKEYR); - } -} - -static void flash_lock(void) -{ - modifyreg32(STM32_FLASH_PECR, 0, FLASH_PECR_PRGLOCK); - stm32_eeprom_lock(); -} - -static ssize_t stm32_eeprom_erase_write(size_t addr, const void *buf, - size_t buflen) -{ - const char *cbuf = buf; - size_t i; - - if (buflen == 0) - { - return 0; - } - - /* Check for valid address range */ - - if (addr >= STM32_EEPROM_BASE) - { - addr -= STM32_EEPROM_BASE; - } - - if (addr >= STM32_EEPROM_SIZE) - { - return -EINVAL; - } - - /* TODO: Voltage range must be range 1 or 2. Erase/program not allowed in - * range 3. - */ - - stm32_eeprom_unlock(); - - /* Clear pending status flags. */ - - putreg32(FLASH_SR_WRPERR | FLASH_SR_PGAERR | - FLASH_SR_SIZERR | FLASH_SR_OPTVERR | - FLASH_SR_OPTVERRUSR | FLASH_SR_RDERR, STM32_FLASH_SR); - - /* Enable automatic erasing (by disabling 'fixed time' programming). */ - - modifyreg32(STM32_FLASH_PECR, FLASH_PECR_FTDW, 0); - - /* Write buffer to EEPROM data memory. */ - - addr += STM32_EEPROM_BASE; - i = 0; - while (i < buflen) - { - uint32_t writeval; - size_t left = buflen - i; - - if ((addr & 0x03) == 0x00 && left >= 4) - { - /* Read/erase/write word */ - - writeval = cbuf ? *(uint32_t *)cbuf : 0; - putreg32(writeval, addr); - } - else if ((addr & 0x01) == 0x00 && left >= 2) - { - /* Read/erase/write half-word */ - - writeval = cbuf ? *(uint16_t *)cbuf : 0; - putreg16(writeval, addr); - } - else - { - /* Read/erase/write byte */ - - writeval = cbuf ? *(uint8_t *)cbuf : 0; - putreg8(writeval, addr); - } - - /* ... and wait to complete. */ - - while (getreg32(STM32_FLASH_SR) & FLASH_SR_BSY) - { - stm32_waste(); - } - - /* Verify */ - - /* We do not check Options Byte invalid flags FLASH_SR_OPTVERR - * and FLASH_SR_OPTVERRUSR for EEPROM erase/write. They are unrelated - * and STM32L standard library does not check for these either. - */ - - if (getreg32(STM32_FLASH_SR) & (FLASH_SR_WRPERR | FLASH_SR_PGAERR | - FLASH_SR_SIZERR | FLASH_SR_RDERR)) - { - stm32_eeprom_lock(); - return -EROFS; - } - - if ((addr & 0x03) == 0x00 && left >= 4) - { - if (getreg32(addr) != writeval) - { - stm32_eeprom_lock(); - return -EIO; - } - - addr += 4; - i += 4; - cbuf += !!(cbuf) * 4; - } - else if ((addr & 0x01) == 0x00 && left >= 2) - { - if (getreg16(addr) != writeval) - { - stm32_eeprom_lock(); - return -EIO; - } - - addr += 2; - i += 2; - cbuf += !!(cbuf) * 2; - } - else - { - if (getreg8(addr) != writeval) - { - stm32_eeprom_lock(); - return -EIO; - } - - addr += 1; - i += 1; - cbuf += !!(cbuf) * 1; - } - } - - stm32_eeprom_lock(); - return buflen; -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -int stm32_flash_unlock(void) -{ - int ret; - - ret = nxmutex_lock(&g_lock); - if (ret < 0) - { - return ret; - } - - flash_unlock(); - nxmutex_unlock(&g_lock); - - return ret; -} - -int stm32_flash_lock(void) -{ - int ret; - - ret = nxmutex_lock(&g_lock); - if (ret < 0) - { - return ret; - } - - flash_lock(); - nxmutex_unlock(&g_lock); - - return ret; -} - -size_t stm32_eeprom_size(void) -{ - return STM32_EEPROM_SIZE; -} - -size_t stm32_eeprom_getaddress(void) -{ - return STM32_EEPROM_BASE; -} - -ssize_t stm32_eeprom_write(size_t addr, const void *buf, size_t buflen) -{ - ssize_t outlen; - int ret; - - if (!buf) - { - return -EINVAL; - } - - ret = nxmutex_lock(&g_lock); - if (ret < 0) - { - return (ssize_t)ret; - } - - outlen = stm32_eeprom_erase_write(addr, buf, buflen); - nxmutex_unlock(&g_lock); - - return outlen; -} - -ssize_t stm32_eeprom_erase(size_t addr, size_t eraselen) -{ - ssize_t outlen; - int ret; - - ret = nxmutex_lock(&g_lock); - if (ret < 0) - { - return (ssize_t)ret; - } - - outlen = stm32_eeprom_erase_write(addr, NULL, eraselen); - nxmutex_unlock(&g_lock); - - return outlen; -} - -size_t up_progmem_pagesize(size_t page) -{ - return STM32_FLASH_PAGESIZE; -} - -size_t up_progmem_erasesize(size_t block) -{ - return STM32_FLASH_PAGESIZE; -} - -ssize_t up_progmem_getpage(size_t addr) -{ - if (addr >= STM32_FLASH_BASE) - { - addr -= STM32_FLASH_BASE; - } - - if (addr >= STM32_FLASH_SIZE) - { - return -EFAULT; - } - - return addr / STM32_FLASH_PAGESIZE; -} - -size_t up_progmem_getaddress(size_t page) -{ - if (page >= STM32_FLASH_NPAGES) - { - return SIZE_MAX; - } - - return page * STM32_FLASH_PAGESIZE + STM32_FLASH_BASE; -} - -size_t up_progmem_neraseblocks(void) -{ - return STM32_FLASH_NPAGES; -} - -bool up_progmem_isuniform(void) -{ -#ifdef STM32_FLASH_PAGESIZE - return true; -#else - return false; -#endif -} - -ssize_t up_progmem_ispageerased(size_t page) -{ - size_t addr; - size_t count; - size_t bwritten = 0; - - if (page >= STM32_FLASH_NPAGES) - { - return -EFAULT; - } - - /* Verify */ - - for (addr = up_progmem_getaddress(page), count = up_progmem_pagesize(page); - count; count--, addr++) - { - if (getreg8(addr) != FLASH_ERASEDVALUE) - { - bwritten++; - } - } - - return bwritten; -} - -ssize_t up_progmem_eraseblock(size_t block) -{ - size_t page_address; - int ret; - - if (block >= STM32_FLASH_NPAGES) - { - return -EFAULT; - } - - page_address = up_progmem_getaddress(block); - - /* Get flash ready and begin erasing single page */ - - ret = nxmutex_lock(&g_lock); - if (ret < 0) - { - return (ssize_t)ret; - } - - flash_unlock(); - - modifyreg32(STM32_FLASH_PECR, 0, FLASH_PECR_ERASE); - modifyreg32(STM32_FLASH_PECR, 0, FLASH_PECR_PROG); - - /* Erase is started by writing 0x00000000 to the first word - * of the program page. - */ - - putreg32(0x00, page_address); - - while (getreg32(STM32_FLASH_SR) & FLASH_SR_BSY) - { - stm32_waste(); - } - - flash_lock(); - nxmutex_unlock(&g_lock); - - /* Verify */ - - if (up_progmem_ispageerased(block) == 0) - { - return up_progmem_erasesize(block); - } - else - { - return -EIO; - } -} - -ssize_t up_progmem_write(size_t addr, const void *buf, size_t count) -{ - uint32_t *word = (uint32_t *)buf; - size_t written = count; - int ret = OK; - - /* STM32L1 requires word access and alignment. */ - - if (addr & 3) - { - return -EINVAL; - } - - if (count & 3) - { - return -EINVAL; - } - - /* Check for valid address range */ - - if (addr >= STM32_FLASH_BASE) - { - addr -= STM32_FLASH_BASE; - } - - if ((addr + count) > STM32_FLASH_SIZE) - { - return -EFAULT; - } - - /* Get flash ready and begin flashing */ - - ret = nxmutex_lock(&g_lock); - if (ret < 0) - { - return (ssize_t)ret; - } - - flash_unlock(); - - for (addr += STM32_FLASH_BASE; count; count -= 4, word++, addr += 4) - { - /* Write word and wait to complete */ - - putreg32(*word, addr); - - while (getreg32(STM32_FLASH_SR) & FLASH_SR_BSY) - { - stm32_waste(); - } - - /* Verify */ - - if (getreg32(STM32_FLASH_SR) & FLASH_SR_WRITE_PROTECTION_ERROR) - { - ret = -EROFS; - goto out; - } - - if (getreg32(addr) != *word) - { - ret = -EIO; - goto out; - } - } - -out: - /* If there was an error, clear all error flags in status - * register (rc_w1 register so do this by writing the - * error bits). - */ - - if (ret != OK) - { - ferr("flash write error: %d, status: 0x%" PRIx32 "\n", - ret, getreg32(STM32_FLASH_SR)); - modifyreg32(STM32_FLASH_SR, 0, FLASH_SR_ALLERRS); - } - - flash_lock(); - nxmutex_unlock(&g_lock); - return (ret == OK) ? written : ret; -} - -uint8_t up_progmem_erasestate(void) -{ - return FLASH_ERASEDVALUE; -} - -#endif /* defined(CONFIG_STM32_STM32L15XX) */ diff --git a/arch/arm/src/stm32/stm32l15xxx_rtcc.c b/arch/arm/src/stm32/stm32l15xxx_rtcc.c deleted file mode 100644 index 3a37110089d26..0000000000000 --- a/arch/arm/src/stm32/stm32l15xxx_rtcc.c +++ /dev/null @@ -1,1883 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32l15xxx_rtcc.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include "chip.h" - -#include -#include -#include -#include -#include - -#include -#include -#include - -#include - -#include "arm_internal.h" -#include "stm32_rcc.h" -#include "stm32_pwr.h" -#include "stm32_exti.h" -#include "stm32_rtc.h" - -#ifdef CONFIG_STM32_RTC - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -/* This RTC implementation supports - * - date/time RTC hardware - * - extended functions Alarm A and B - * */ - -#ifndef CONFIG_RTC_DATETIME -# error "CONFIG_RTC_DATETIME must be set to use this driver" -#endif - -#ifdef CONFIG_RTC_HIRES -# error "CONFIG_RTC_HIRES must NOT be set with this driver" -#endif - -#ifndef CONFIG_STM32_PWR -# error "CONFIG_STM32_PWR must selected to use this driver" -#endif - -#if defined(CONFIG_STM32_RTC_HSECLOCK) -# warning "RTC with HSE clock not yet tested on STM32L15XXX" -#elif defined(CONFIG_STM32_RTC_LSICLOCK) -# warning "RTC with LSI clock not yet tested on STM32L15XXX" -#endif - -#if !defined(CONFIG_STM32_RTC_MAGIC) -# define CONFIG_STM32_RTC_MAGIC (0xfacefeed) -#endif - -#if !defined(CONFIG_STM32_RTC_MAGIC_TIME_SET) -# define CONFIG_STM32_RTC_MAGIC_TIME_SET (0xf00dface) -#endif - -#if !defined(CONFIG_STM32_RTC_MAGIC_REG) -# define CONFIG_STM32_RTC_MAGIC_REG (0) -#endif - -#define RTC_MAGIC CONFIG_STM32_RTC_MAGIC -#define RTC_MAGIC_TIME_SET CONFIG_STM32_RTC_MAGIC_TIME_SET -#define RTC_MAGIC_REG STM32_RTC_BKR(CONFIG_STM32_RTC_MAGIC_REG) - -/* Constants ****************************************************************/ - -#define SYNCHRO_TIMEOUT (0x00020000) -#define INITMODE_TIMEOUT (0x00010000) - -#define RTC_ALRMR_ENABLE 0 - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -#ifdef CONFIG_RTC_ALARM -typedef unsigned int rtc_alarmreg_t; - -struct alm_cbinfo_s -{ - volatile alm_callback_t ac_cb; /* Client callback function */ - volatile void *ac_arg; /* Argument to pass with the callback function */ -}; -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -#ifdef CONFIG_RTC_ALARM -/* Callback to use when an EXTI is activated */ - -static struct alm_cbinfo_s g_alarmcb[RTC_ALARM_LAST]; -static bool g_alarm_enabled; /* True: Alarm interrupts are enabled */ -#endif - -#ifdef CONFIG_RTC_PERIODIC -static wakeupcb_t g_wakeupcb; -static bool g_wakeup_enabled; /* True: Wakeup interrupts are enabled */ -#endif - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/* g_rtc_enabled is set true after the RTC has successfully initialized */ - -volatile bool g_rtc_enabled = false; - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -#ifdef CONFIG_RTC_ALARM -static int rtchw_check_alrawf(void); -static int rtchw_set_alrmar(rtc_alarmreg_t alarmreg); -#if CONFIG_RTC_NALARMS > 1 -static int rtchw_check_alrbwf(void); -static int rtchw_set_alrmbr(rtc_alarmreg_t alarmreg); -#endif -static inline void rtc_enable_alarm(void); -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: rtc_dumpregs - ****************************************************************************/ - -#ifdef CONFIG_DEBUG_RTC_INFO -static void rtc_dumpregs(const char *msg) -{ - rtcinfo("%s:\n", msg); - rtcinfo(" TR: %08" PRIx32 "\n", getreg32(STM32_RTC_TR)); - rtcinfo(" DR: %08" PRIx32 "\n", getreg32(STM32_RTC_DR)); - rtcinfo(" CR: %08" PRIx32 "\n", getreg32(STM32_RTC_CR)); - rtcinfo(" ISR: %08" PRIx32 "\n", getreg32(STM32_RTC_ISR)); - rtcinfo(" PRER: %08" PRIx32 "\n", getreg32(STM32_RTC_PRER)); - rtcinfo(" WUTR: %08" PRIx32 "\n", getreg32(STM32_RTC_WUTR)); - rtcinfo(" CALIBR: %08" PRIx32 "\n", getreg32(STM32_RTC_CALIBR)); - rtcinfo(" ALRMAR: %08" PRIx32 "\n", getreg32(STM32_RTC_ALRMAR)); - rtcinfo(" ALRMBR: %08" PRIx32 "\n", getreg32(STM32_RTC_ALRMBR)); - rtcinfo(" SHIFTR: %08" PRIx32 "\n", getreg32(STM32_RTC_SHIFTR)); - rtcinfo(" TSTR: %08" PRIx32 "\n", getreg32(STM32_RTC_TSTR)); - rtcinfo(" TSDR: %08" PRIx32 "\n", getreg32(STM32_RTC_TSDR)); - rtcinfo(" TSSSR: %08" PRIx32 "\n", getreg32(STM32_RTC_TSSSR)); - rtcinfo(" CALR: %08" PRIx32 "\n", getreg32(STM32_RTC_CALR)); - rtcinfo(" TAFCR: %08" PRIx32 "\n", getreg32(STM32_RTC_TAFCR)); - rtcinfo("ALRMASSR: %08" PRIx32 "\n", getreg32(STM32_RTC_ALRMASSR)); - rtcinfo("ALRMBSSR: %08" PRIx32 "\n", getreg32(STM32_RTC_ALRMBSSR)); - rtcinfo("MAGICREG: %08" PRIx32 "\n", getreg32(RTC_MAGIC_REG)); -} -#else -# define rtc_dumpregs(msg) -#endif - -/**************************************************************************** - * Name: rtc_dumptime - ****************************************************************************/ - -#ifdef CONFIG_DEBUG_RTC_INFO -static void rtc_dumptime(const struct tm *tp, const char *msg) -{ - rtcinfo("%s:\n", msg); -#if 0 - rtcinfo(" tm_sec: %08x\n", tp->tm_sec); - rtcinfo(" tm_min: %08x\n", tp->tm_min); - rtcinfo(" tm_hour: %08x\n", tp->tm_hour); - rtcinfo(" tm_mday: %08x\n", tp->tm_mday); - rtcinfo(" tm_mon: %08x\n", tp->tm_mon); - rtcinfo(" tm_year: %08x\n", tp->tm_year); -#else - rtcinfo(" tm: %04d-%02d-%02d %02d:%02d:%02d\n", - tp->tm_year + 1900, tp->tm_mon + 1, tp->tm_mday, - tp->tm_hour, tp->tm_min, tp->tm_sec); -#endif -} -#else -# define rtc_dumptime(tp, msg) -#endif - -/**************************************************************************** - * Name: rtc_wprunlock - * - * Description: - * Disable RTC write protection - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void rtc_wprunlock(void) -{ - /* Enable write access to the backup domain. */ - - stm32_pwr_enablebkp(true); - - /* The following steps are required to unlock the write protection on all - * the RTC registers (except for RTC_ISR[13:8], RTC_TAFCR, and RTC_BKPxR). - * - * 1. Write 0xCA into the RTC_WPR register. - * 2. Write 0x53 into the RTC_WPR register. - * - * Writing a wrong key re-activates the write protection. - */ - - putreg32(0xca, STM32_RTC_WPR); - putreg32(0x53, STM32_RTC_WPR); -} - -/**************************************************************************** - * Name: rtc_wprlock - * - * Description: - * Enable RTC write protection - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -static inline void rtc_wprlock(void) -{ - /* Writing any wrong key re-activates the write protection. */ - - putreg32(0xff, STM32_RTC_WPR); - - /* Disable write access to the backup domain. */ - - stm32_pwr_enablebkp(false); -} - -/**************************************************************************** - * Name: rtc_synchwait - * - * Description: - * Waits until the RTC Time and Date registers (RTC_TR and RTC_DR) are - * synchronized with RTC APB clock. - * - * Input Parameters: - * None - * - * Returned Value: - * Zero (OK) on success; a negated errno on failure - * - ****************************************************************************/ - -static int rtc_synchwait(void) -{ - volatile uint32_t timeout; - uint32_t regval; - int ret; - - /* Clear Registers synchronization flag (RSF) */ - - regval = getreg32(STM32_RTC_ISR); - regval &= ~RTC_ISR_RSF; - putreg32(regval, STM32_RTC_ISR); - - /* Now wait the registers to become synchronised */ - - ret = -ETIMEDOUT; - for (timeout = 0; timeout < SYNCHRO_TIMEOUT; timeout++) - { - regval = getreg32(STM32_RTC_ISR); - if ((regval & RTC_ISR_RSF) != 0) - { - /* Synchronized */ - - ret = OK; - break; - } - } - - return ret; -} - -/**************************************************************************** - * Name: rtc_enterinit - * - * Description: - * Enter RTC initialization mode. - * - * Input Parameters: - * None - * - * Returned Value: - * Zero (OK) on success; a negated errno on failure - * - ****************************************************************************/ - -static int rtc_enterinit(void) -{ - volatile uint32_t timeout; - uint32_t regval; - int ret; - - /* Check if the Initialization mode is already set */ - - regval = getreg32(STM32_RTC_ISR); - - ret = OK; - if ((regval & RTC_ISR_INITF) == 0) - { - /* Set the Initialization mode */ - - putreg32(RTC_ISR_INIT, STM32_RTC_ISR); - - /* Wait until the RTC is in the INIT state (or a timeout occurs) */ - - ret = -ETIMEDOUT; - for (timeout = 0; timeout < INITMODE_TIMEOUT; timeout++) - { - regval = getreg32(STM32_RTC_ISR); - if ((regval & RTC_ISR_INITF) != 0) - { - ret = OK; - break; - } - } - } - - return ret; -} - -/**************************************************************************** - * Name: rtc_exitinit - * - * Description: - * Exit RTC initialization mode. - * - * Input Parameters: - * None - * - * Returned Value: - * Zero (OK) on success; a negated errno on failure - * - ****************************************************************************/ - -static void rtc_exitinit(void) -{ - uint32_t regval; - - regval = getreg32(STM32_RTC_ISR); - regval &= ~(RTC_ISR_INIT); - putreg32(regval, STM32_RTC_ISR); -} - -/**************************************************************************** - * Name: rtc_bin2bcd - * - * Description: - * Converts a 2 digit binary to BCD format - * - * Input Parameters: - * value - The byte to be converted. - * - * Returned Value: - * The value in BCD representation - * - ****************************************************************************/ - -static uint32_t rtc_bin2bcd(int value) -{ - uint32_t msbcd = 0; - - while (value >= 10) - { - msbcd++; - value -= 10; - } - - return (msbcd << 4) | value; -} - -/**************************************************************************** - * Name: rtc_bin2bcd - * - * Description: - * Convert from 2 digit BCD to binary. - * - * Input Parameters: - * value - The BCD value to be converted. - * - * Returned Value: - * The value in binary representation - * - ****************************************************************************/ - -static int rtc_bcd2bin(uint32_t value) -{ - uint32_t tens = (value >> 4) * 10; - return (int)(tens + (value & 0x0f)); -} - -/**************************************************************************** - * Name: rtc_resume - * - * Description: - * Called when the RTC was already initialized on a previous power cycle. - * This just brings the RTC back into full operation. - * - * Input Parameters: - * None - * - * Returned Value: - * Zero (OK) on success; a negated errno on failure - * - ****************************************************************************/ - -static void rtc_resume(void) -{ -#ifdef CONFIG_RTC_ALARM - uint32_t regval; - - /* Clear the RTC alarm flags */ - - regval = getreg32(STM32_RTC_ISR); - regval &= ~(RTC_ISR_ALRAF | RTC_ISR_ALRBF); - putreg32(regval, STM32_RTC_ISR); - - /* Clear the EXTI Line 18 Pending bit (Connected internally to RTC Alarm) */ - - putreg32(EXTI_RTC_ALARM, STM32_EXTI_PR); -#endif -} - -/**************************************************************************** - * Name: stm32_rtc_alarm_handler - * - * Description: - * RTC ALARM interrupt service routine through the EXTI line - * - * Input Parameters: - * irq - The IRQ number that generated the interrupt - * context - Architecture specific register save information. - * - * Returned Value: - * Zero (OK) on success; A negated errno value on failure. - * - ****************************************************************************/ - -#ifdef CONFIG_RTC_ALARM -static int stm32_rtc_alarm_handler(int irq, void *context, - void *rtc_handler_arg) -{ - struct alm_cbinfo_s *cbinfo; - alm_callback_t cb; - void *arg; - uint32_t isr; - uint32_t cr; - int ret = OK; - - /* Enable write access to the backup domain (RTC registers, RTC - * backup data registers and backup SRAM). - */ - - stm32_pwr_enablebkp(true); - - /* Check for EXTI from Alarm A or B and handle according */ - - cr = getreg32(STM32_RTC_CR); - if ((cr & RTC_CR_ALRAIE) != 0) - { - isr = getreg32(STM32_RTC_ISR); - if ((isr & RTC_ISR_ALRAF) != 0) - { - cbinfo = &g_alarmcb[RTC_ALARMA]; - if (cbinfo->ac_cb != NULL) - { - /* Alarm A callback */ - - cb = cbinfo->ac_cb; - arg = (void *)cbinfo->ac_arg; - - cbinfo->ac_cb = NULL; - cbinfo->ac_arg = NULL; - - cb(arg, RTC_ALARMA); - } - - /* note, bits 8-13 do /not/ require the write enable procedure */ - - isr = getreg32(STM32_RTC_ISR); - isr &= ~RTC_ISR_ALRAF; - putreg32(isr, STM32_RTC_ISR); - } - } - -#if CONFIG_RTC_NALARMS > 1 - cr = getreg32(STM32_RTC_CR); - if ((cr & RTC_CR_ALRBIE) != 0) - { - isr = getreg32(STM32_RTC_ISR); - if ((isr & RTC_ISR_ALRBF) != 0) - { - cbinfo = &g_alarmcb[RTC_ALARMB]; - if (cbinfo->ac_cb != NULL) - { - /* Alarm B callback */ - - cb = cbinfo->ac_cb; - arg = (void *)cbinfo->ac_arg; - - cbinfo->ac_cb = NULL; - cbinfo->ac_arg = NULL; - - cb(arg, RTC_ALARMB); - } - - /* note, bits 8-13 do /not/ require the write enable procedure */ - - isr = getreg32(STM32_RTC_ISR); - isr &= ~RTC_ISR_ALRBF; - putreg32(isr, STM32_RTC_ISR); - } - } -#endif - - /* Disable write access to the backup domain (RTC registers, RTC backup - * data registers and backup SRAM). - */ - - stm32_pwr_enablebkp(false); - - return ret; -} -#endif - -/**************************************************************************** - * Name: rtchw_check_alrXwf X= a or B - * - * Description: - * Check registers - * - * Input Parameters: - * None - * - * Returned Value: - * Zero (OK) on success; a negated errno on failure - * - ****************************************************************************/ - -#ifdef CONFIG_RTC_ALARM -static int rtchw_check_alrawf(void) -{ - volatile uint32_t timeout; - uint32_t regval; - int ret = -ETIMEDOUT; - - /* Check RTC_ISR ALRAWF for access to alarm register, - * Can take 2 RTCCLK cycles or timeout - * CubeMX use GetTick. - */ - - for (timeout = 0; timeout < INITMODE_TIMEOUT; timeout++) - { - regval = getreg32(STM32_RTC_ISR); - if ((regval & RTC_ISR_ALRAWF) != 0) - { - ret = OK; - break; - } - } - - return ret; -} -#endif - -#if defined(CONFIG_RTC_ALARM) && CONFIG_RTC_NALARMS > 1 -static int rtchw_check_alrbwf(void) -{ - volatile uint32_t timeout; - uint32_t regval; - int ret = -ETIMEDOUT; - - /* Check RTC_ISR ALRBWF for access to alarm register, - * can take 2 RTCCLK cycles or timeout - * CubeMX use GetTick. - */ - - for (timeout = 0; timeout < INITMODE_TIMEOUT; timeout++) - { - regval = getreg32(STM32_RTC_ISR); - if ((regval & RTC_ISR_ALRBWF) != 0) - { - ret = OK; - break; - } - } - - return ret; -} -#endif - -/**************************************************************************** - * Name: stm32_rtchw_set_alrmXr X is a or b - * - * Description: - * Set the alarm (A or B) hardware registers, using the required hardware - * access protocol - * - * Input Parameters: - * alarmreg - the register - * - * Returned Value: - * Zero (OK) on success; a negated errno on failure - * - ****************************************************************************/ - -#ifdef CONFIG_RTC_ALARM -static int rtchw_set_alrmar(rtc_alarmreg_t alarmreg) -{ - int isr; - int ret = -EBUSY; - - /* Disable the write protection for RTC registers */ - - rtc_wprunlock(); - - /* Disable RTC alarm A & Interrupt A */ - - modifyreg32(STM32_RTC_CR, (RTC_CR_ALRAE | RTC_CR_ALRAIE), 0); - - /* Ensure Alarm A flag reset; this is edge triggered */ - - isr = getreg32(STM32_RTC_ISR) & ~RTC_ISR_ALRAF; - putreg32(isr, STM32_RTC_ISR); - - /* Wait for Alarm A to be writable */ - - ret = rtchw_check_alrawf(); - if (ret != OK) - { - goto errout_with_wprunlock; - } - - /* Set the RTC Alarm A register */ - - putreg32(alarmreg, STM32_RTC_ALRMAR); - putreg32(0, STM32_RTC_ALRMASSR); - rtcinfo(" ALRMAR: %08" PRIx32 "\n", getreg32(STM32_RTC_ALRMAR)); - - /* Enable RTC alarm A */ - - modifyreg32(STM32_RTC_CR, 0, (RTC_CR_ALRAE | RTC_CR_ALRAIE)); - -errout_with_wprunlock: - rtc_wprlock(); - return ret; -} -#endif - -#if defined(CONFIG_RTC_ALARM) && CONFIG_RTC_NALARMS > 1 -static int rtchw_set_alrmbr(rtc_alarmreg_t alarmreg) -{ - int isr; - int ret = -EBUSY; - - /* Disable the write protection for RTC registers */ - - rtc_wprunlock(); - - /* Disable RTC alarm B & Interrupt B */ - - modifyreg32(STM32_RTC_CR, (RTC_CR_ALRBE | RTC_CR_ALRBIE), 0); - - /* Ensure Alarm B flag reset; this is edge triggered */ - - isr = getreg32(STM32_RTC_ISR) & ~RTC_ISR_ALRBF; - putreg32(isr, STM32_RTC_ISR); - - /* Wait for Alarm B to be writable */ - - ret = rtchw_check_alrbwf(); - if (ret != OK) - { - goto rtchw_set_alrmbr_exit; - } - - /* Set the RTC Alarm B register */ - - putreg32(alarmreg, STM32_RTC_ALRMBR); - putreg32(0, STM32_RTC_ALRMBSSR); - rtcinfo(" ALRMBR: %08" PRIx32 "\n", getreg32(STM32_RTC_ALRMBR)); - - /* Enable RTC alarm B */ - - modifyreg32(STM32_RTC_CR, 0, (RTC_CR_ALRBE | RTC_CR_ALRBIE)); - -rtchw_set_alrmbr_exit: - rtc_wprlock(); - return ret; -} -#endif - -/**************************************************************************** - * Name: rtc_enable_alarm - * - * Description: - * Enable ALARM interrupts - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef CONFIG_RTC_ALARM -static inline void rtc_enable_alarm(void) -{ - /* Is the alarm already enabled? */ - - if (!g_alarm_enabled) - { - /* Configure RTC interrupt to catch alarm interrupts. All RTC - * interrupts are connected to the EXTI controller. To enable the - * RTC Alarm interrupt, the following sequence is required: - * - * 1. Configure and enable the EXTI Line 18 in interrupt mode and - * select the rising edge sensitivity. - * EXTI line 19 RTC Tamper or Timestamp or CSS_LSE - * EXTI line 20 RTC Wakeup - * 2. Configure and enable the RTC_Alarm IRQ channel in the NVIC. - * 3. Configure the RTC to generate RTC alarms (Alarm A or Alarm B). - */ - - stm32_exti_alarm(true, false, true, stm32_rtc_alarm_handler, NULL); - g_alarm_enabled = true; - } -} -#endif - -/**************************************************************************** - * Name: stm32_rtc_getalarmdatetime - * - * Description: - * Get the current date and time for a RTC alarm. - * - * Input Parameters: - * reg - RTC alarm register - * tp - The location to return the high resolution time value. - * - * Returned Value: - * Zero (OK) on success; a negated errno on failure - * - ****************************************************************************/ - -#ifdef CONFIG_RTC_ALARM -static int stm32_rtc_getalarmdatetime(rtc_alarmreg_t reg, struct tm *tp) -{ - uint32_t data; - uint32_t tmp; - - DEBUGASSERT(tp != NULL); - - /* Sample the data time register. */ - - data = getreg32(reg); - - /* Convert the RTC time to fields in struct tm format. All of the STM32 - * ranges of values correspond between struct tm and the time register. - */ - - tmp = (data & (RTC_ALRMR_SU_MASK | RTC_ALRMR_ST_MASK)) >> - RTC_ALRMR_SU_SHIFT; - tp->tm_sec = rtc_bcd2bin(tmp); - - tmp = (data & (RTC_ALRMR_MNU_MASK | RTC_ALRMR_MNT_MASK)) >> - RTC_ALRMR_MNU_SHIFT; - tp->tm_min = rtc_bcd2bin(tmp); - - tmp = (data & (RTC_ALRMR_HU_MASK | RTC_ALRMR_HT_MASK)) >> - RTC_ALRMR_HU_SHIFT; - tp->tm_hour = rtc_bcd2bin(tmp); - - tmp = (data & (RTC_ALRMR_DU_MASK | RTC_ALRMR_DT_MASK)) >> - RTC_ALRMR_DU_SHIFT; - tp->tm_mday = rtc_bcd2bin(tmp); - - return OK; -} -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_rtc_is_initialized - * - * Description: - * Returns 'true' if the RTC has been initialized - * Returns 'false' if the RTC has never been initialized since first time - * power up, and the counters are stopped until it is first initialized. - * - * Input Parameters: - * None - * - * Returned Value: - * Returns true if RTC has been initialized. - * - ****************************************************************************/ - -bool stm32_rtc_is_initialized(void) -{ - uint32_t regval; - - regval = getreg32(RTC_MAGIC_REG); - - return regval == RTC_MAGIC || regval == RTC_MAGIC_TIME_SET; -} - -/**************************************************************************** - * Name: up_rtc_initialize - * - * Description: - * Initialize the hardware RTC per the selected configuration. This - * function is called once during the OS initialization sequence - * - * Input Parameters: - * None - * - * Returned Value: - * Zero (OK) on success; a negated errno on failure - * - ****************************************************************************/ - -int up_rtc_initialize(void) -{ - bool init_stat; - uint32_t regval; - - rtc_dumpregs("Before Initialization"); - - /* See if the clock has already been initialized; since it is battery - * backed, we don't need or want to re-initialize on each reset. - */ - - init_stat = stm32_rtc_is_initialized(); - if (!init_stat) - { - /* Enable write access to the backup domain (RTC registers, RTC - * backup data registers and backup SRAM). - */ - - stm32_pwr_enablebkp(true); - -#if defined(CONFIG_STM32_RTC_HSECLOCK) - modifyreg32(STM32_RCC_CSR, RCC_CSR_RTCSEL_MASK, RCC_CSR_RTCSEL_HSE); -#elif defined(CONFIG_STM32_RTC_LSICLOCK) - modifyreg32(STM32_RCC_CSR, RCC_CSR_RTCSEL_MASK, RCC_CSR_RTCSEL_LSI); -#elif defined(CONFIG_STM32_RTC_LSECLOCK) - modifyreg32(STM32_RCC_CSR, RCC_CSR_RTCSEL_MASK, RCC_CSR_RTCSEL_LSE); -#else -# error "No clock for RTC!" -#endif - - /* Enable the RTC Clock by setting the RTCEN bit in the CSR register */ - - modifyreg32(STM32_RCC_CSR, 0, RCC_CSR_RTCEN); - - /* Disable the write protection for RTC registers */ - - rtc_wprunlock(); - - /* Set Initialization mode */ - - if (OK != rtc_enterinit()) - { - /* Enable the write protection for RTC registers */ - - rtc_wprlock(); - - /* Disable write access to the backup domain (RTC registers, RTC - * backup data registers and backup SRAM). - */ - - stm32_pwr_enablebkp(false); - - rtc_dumpregs("After Failed Initialization"); - - return ERROR; - } - else - { - /* Clear RTC_CR FMT, OSEL and POL Bits */ - - regval = getreg32(STM32_RTC_CR); - regval &= ~(RTC_CR_FMT | RTC_CR_OSEL_MASK | RTC_CR_POL); - putreg32(regval, STM32_RTC_CR); - - /* Configure RTC pre-scaler with the required values */ - -#ifdef CONFIG_STM32_RTC_HSECLOCK - /* The HSE is divided by 32 prior to the prescaler we set here. - * - * NOTE: max HSE/32 is 4 MHz if it is to be used with RTC - */ - - /* For a 1 MHz clock this yields 0.9999360041 Hz on the second - * timer - which is pretty close. - */ - - putreg32(((uint32_t)7812 << RTC_PRER_PREDIV_S_SHIFT) | - ((uint32_t)0x7f << RTC_PRER_PREDIV_A_SHIFT), - STM32_RTC_PRER); -#elif defined(CONFIG_STM32_RTC_LSICLOCK) - /* Suitable values for 32.000 KHz LSI clock - * (29.5 - 34 KHz, though) - */ - - putreg32(((uint32_t)0xf9 << RTC_PRER_PREDIV_S_SHIFT) | - ((uint32_t)0x7f << RTC_PRER_PREDIV_A_SHIFT), - STM32_RTC_PRER); -#else /* defined(CONFIG_STM32_RTC_LSECLOCK) */ - /* Correct values for 32.768 KHz LSE clock */ - - putreg32(((uint32_t)0xff << RTC_PRER_PREDIV_S_SHIFT) | - ((uint32_t)0x7f << RTC_PRER_PREDIV_A_SHIFT), - STM32_RTC_PRER); -#endif - - /* Exit Initialization mode */ - - rtc_exitinit(); - - /* Wait for the RTC Time and Date registers to be synchronized - * with RTC APB clock. - */ - - rtc_synchwait(); - - /* Keep the fact that the RTC is initialized */ - - putreg32(RTC_MAGIC, RTC_MAGIC_REG); - - /* Enable the write protection for RTC registers */ - - rtc_wprlock(); - - /* Disable write access to the backup domain (RTC registers, RTC - * backup data registers and backup SRAM). - */ - - stm32_pwr_enablebkp(false); - } - } - else - { - /* Enable write access to the backup domain (RTC registers, RTC - * backup data registers and backup SRAM). - */ - - stm32_pwr_enablebkp(true); - - /* Write protection for RTC registers does not need to be disabled. */ - - rtc_resume(); - - /* Disable write access to the backup domain (RTC registers, RTC backup - * data registers and backup SRAM). - */ - - stm32_pwr_enablebkp(false); - } - - g_rtc_enabled = true; - rtc_dumpregs("After Initialization"); - - return OK; -} - -/**************************************************************************** - * Name: stm32_rtc_irqinitialize - * - * Description: - * Initialize IRQs for RTC, not possible during up_rtc_initialize because - * up_irqinitialize is called later. - * - * Input Parameters: - * None - * - * Returned Value: - * Zero (OK) on success; a negated errno on failure - * - ****************************************************************************/ - -int stm32_rtc_irqinitialize(void) -{ - /* Nothing to do */ - - return OK; -} - -/**************************************************************************** - * Name: stm32_rtc_getdatetime_with_subseconds - * - * Description: - * Get the current date and time from the date/time RTC. This interface - * is only supported by the date/time RTC hardware implementation. It is - * used to replace the system timer. It is only used by the RTOS during - * initialization to set up the system time when CONFIG_RTC and - * CONFIG_RTC_DATETIME are selected. - * - * Sub-second accuracy is returned through 'nsec'. - * - * Input Parameters: - * tp - The location to return the high resolution time value. - * nsec - The location to return the subsecond time value. - * - * Returned Value: - * Zero (OK) on success; a negated errno on failure - * - ****************************************************************************/ - -int stm32_rtc_getdatetime_with_subseconds(struct tm *tp, long *nsec) -{ -#ifdef CONFIG_STM32_HAVE_RTC_SUBSECONDS - uint32_t ssr; -#endif - uint32_t dr; - uint32_t tr; - uint32_t tmp; - - /* Sample the data time registers. There is a race condition here... If - * we sample the time just before midnight on December 31, the date could - * be wrong because the day rolled over while were sampling. Thus loop for - * checking overflow here is needed. There is a race condition with - * subseconds too. If we sample TR register just before second rolling - * and subseconds are read at wrong second, we get wrong time. - */ - - do - { - dr = getreg32(STM32_RTC_DR); - tr = getreg32(STM32_RTC_TR); -#ifdef CONFIG_STM32_HAVE_RTC_SUBSECONDS - ssr = getreg32(STM32_RTC_SSR); - tmp = getreg32(STM32_RTC_TR); - if (tmp != tr) - { - continue; - } -#endif - - tmp = getreg32(STM32_RTC_DR); - if (tmp == dr) - { - break; - } - } - while (1); - - rtc_dumpregs("Reading Time"); - - /* Convert the RTC time to fields in struct tm format. All of the STM32 - * ranges of values correspond between struct tm and the time register. - */ - - tmp = (tr & (RTC_TR_SU_MASK | RTC_TR_ST_MASK)) >> RTC_TR_SU_SHIFT; - tp->tm_sec = rtc_bcd2bin(tmp); - - tmp = (tr & (RTC_TR_MNU_MASK | RTC_TR_MNT_MASK)) >> RTC_TR_MNU_SHIFT; - tp->tm_min = rtc_bcd2bin(tmp); - - tmp = (tr & (RTC_TR_HU_MASK | RTC_TR_HT_MASK)) >> RTC_TR_HU_SHIFT; - tp->tm_hour = rtc_bcd2bin(tmp); - - /* Now convert the RTC date to fields in struct tm format: - * Days: 1-31 match in both cases. - * Month: STM32 is 1-12, struct tm is 0-11. - * Years: STM32 is 00-99, struct tm is years since 1900. - * WeekDay: STM32 is 1 = Mon - 7 = Sun - * - * Issue: I am not sure what the STM32 years mean. Are these the - * years 2000-2099? I'll assume so. - */ - - tmp = (dr & (RTC_DR_DU_MASK | RTC_DR_DT_MASK)) >> RTC_DR_DU_SHIFT; - tp->tm_mday = rtc_bcd2bin(tmp); - - tmp = (dr & (RTC_DR_MU_MASK | RTC_DR_MT)) >> RTC_DR_MU_SHIFT; - tp->tm_mon = rtc_bcd2bin(tmp) - 1; - - tmp = (dr & (RTC_DR_YU_MASK | RTC_DR_YT_MASK)) >> RTC_DR_YU_SHIFT; - tp->tm_year = rtc_bcd2bin(tmp) + 100; - - tmp = (dr & RTC_DR_WDU_MASK) >> RTC_DR_WDU_SHIFT; - tp->tm_wday = tmp % 7; - tp->tm_yday = tp->tm_mday - 1 + - clock_daysbeforemonth(tp->tm_mon, - clock_isleapyear(tp->tm_year + 1900)); - tp->tm_isdst = 0; - - /* Return RTC sub-seconds if a non-NULL value - * of nsec has been provided to receive the sub-second value. - */ - -#ifdef CONFIG_STM32_HAVE_RTC_SUBSECONDS - if (nsec) - { - uint32_t prediv_s; - uint32_t usecs; - - prediv_s = getreg32(STM32_RTC_PRER) & RTC_PRER_PREDIV_S_MASK; - prediv_s >>= RTC_PRER_PREDIV_S_SHIFT; - - ssr &= RTC_SSR_MASK; - - /* Maximum prediv_s is 0x7fff, thus we can multiply by 100000 and - * still fit 32-bit unsigned integer. - */ - - usecs = (((prediv_s - ssr) * 100000) / (prediv_s + 1)) * 10; - *nsec = usecs * 1000; - } -#else - DEBUGASSERT(nsec == NULL); -#endif - - rtc_dumptime(tp, "Returning"); - return OK; -} - -/**************************************************************************** - * Name: up_rtc_getdatetime - * - * Description: - * Get the current date and time from the date/time RTC. This interface - * is only supported by the date/time RTC hardware implementation. It is - * used to replace the system timer. It is only used by the RTOS during - * initialization to set up the system time when CONFIG_RTC and - * CONFIG_RTC_DATETIME are selected. - * - * NOTE: Some date/time RTC hardware is capability of sub-second accuracy. - * That sub-second accuracy is lost in this interface. However, since the - * system time is reinitialized on each power-up/reset, there will be no - * timing inaccuracy in the long run. - * - * Input Parameters: - * tp - The location to return the high resolution time value. - * - * Returned Value: - * Zero (OK) on success; a negated errno on failure - * - ****************************************************************************/ - -int up_rtc_getdatetime(struct tm *tp) -{ - return stm32_rtc_getdatetime_with_subseconds(tp, NULL); -} - -/**************************************************************************** - * Name: up_rtc_getdatetime_with_subseconds - * - * Description: - * Get the current date and time from the date/time RTC. This interface - * is only supported by the date/time RTC hardware implementation. - * It is used to replace the system timer. It is only used by the RTOS - * during initialization to set up the system time when CONFIG_RTC and - * CONFIG_RTC_DATETIME are selected (and CONFIG_RTC_HIRES is not). - * - * NOTE: This interface exposes sub-second accuracy capability of RTC - * hardware. This interface allow maintaining timing accuracy when - * system time needs constant resynchronization with RTC, for example - * with board level power-save mode utilizing deep-sleep modes such as - * STOP on STM32 MCUs. - * - * Input Parameters: - * tp - The location to return the high resolution time value. - * nsec - The location to return the subsecond time value. - * - * Returned Value: - * Zero (OK) on success; a negated errno on failure - * - ****************************************************************************/ - -#ifdef CONFIG_ARCH_HAVE_RTC_SUBSECONDS -# ifndef CONFIG_STM32_HAVE_RTC_SUBSECONDS -# error "Invalid config, enable CONFIG_STM32_HAVE_RTC_SUBSECONDS." -# endif -int up_rtc_getdatetime_with_subseconds(struct tm *tp, long *nsec) -{ - return stm32_rtc_getdatetime_with_subseconds(tp, nsec); -} -#endif - -/**************************************************************************** - * Name: stm32_rtc_setdatetime - * - * Description: - * Set the RTC to the provided time. RTC implementations which provide - * up_rtc_getdatetime() (CONFIG_RTC_DATETIME is selected) should provide - * this function. - * - * Input Parameters: - * tp - the time to use - * - * Returned Value: - * Zero (OK) on success; a negated errno on failure - * - ****************************************************************************/ - -int stm32_rtc_setdatetime(const struct tm *tp) -{ - uint32_t tr; - uint32_t dr; - int ret; - - rtc_dumptime(tp, "Setting time"); - - /* Then write the broken out values to the RTC */ - - /* Convert the struct tm format to RTC time register fields. - * All of the ranges of values correspond between struct tm and the time - * register. - */ - - tr = (rtc_bin2bcd(tp->tm_sec) << RTC_TR_SU_SHIFT) | - (rtc_bin2bcd(tp->tm_min) << RTC_TR_MNU_SHIFT) | - (rtc_bin2bcd(tp->tm_hour) << RTC_TR_HU_SHIFT); - tr &= ~RTC_TR_RESERVED_BITS; - - /* Now convert the fields in struct tm format to the RTC date register - * fields: - * - * Days: 1-31 match in both cases. - * Month: STM32 is 1-12, struct tm is 0-11. - * Years: STM32 is 00-99, struct tm is years since 1900. - * WeekDay: STM32 is 1 = Mon - 7 = Sun - * Issue: I am not sure what the STM32 years mean. Are these the - * years 2000-2099? I'll assume so. - */ - - dr = (rtc_bin2bcd(tp->tm_mday) << RTC_DR_DU_SHIFT) | - ((rtc_bin2bcd(tp->tm_mon + 1)) << RTC_DR_MU_SHIFT) | - ((tp->tm_wday == 0 ? 7 : (tp->tm_wday & 7)) << RTC_DR_WDU_SHIFT) | - ((rtc_bin2bcd(tp->tm_year - 100)) << RTC_DR_YU_SHIFT); - - dr &= ~RTC_DR_RESERVED_BITS; - - /* Disable the write protection for RTC registers */ - - rtc_wprunlock(); - - /* Set Initialization mode */ - - ret = rtc_enterinit(); - if (ret == OK) - { - /* Set the RTC TR and DR registers */ - - putreg32(tr, STM32_RTC_TR); - putreg32(dr, STM32_RTC_DR); - - /* Exit Initialization mode and wait for the RTC Time and Date - * registers to be synchronized with RTC APB clock. - */ - - rtc_exitinit(); - ret = rtc_synchwait(); - } - - /* Remember that the RTC is initialized and had its time set. */ - - if (getreg32(RTC_MAGIC_REG) != RTC_MAGIC_TIME_SET) - { - stm32_pwr_enablebkp(true); - putreg32(RTC_MAGIC_TIME_SET, RTC_MAGIC_REG); - stm32_pwr_enablebkp(false); - } - - /* Re-enable the write protection for RTC registers */ - - rtc_wprlock(); - rtc_dumpregs("New time setting"); - return ret; -} - -/**************************************************************************** - * Name: stm32_rtc_havesettime - * - * Description: - * Check if RTC time has been set. - * - * Returned Value: - * Returns true if RTC date-time have been previously set. - * - ****************************************************************************/ - -bool stm32_rtc_havesettime(void) -{ - return getreg32(RTC_MAGIC_REG) == RTC_MAGIC_TIME_SET; -} - -/**************************************************************************** - * Name: up_rtc_settime - * - * Description: - * Set the RTC to the provided time. All RTC implementations must be able - * to set their time based on a standard timespec. - * - * Input Parameters: - * tp - the time to use - * - * Returned Value: - * Zero (OK) on success; a negated errno on failure - * - ****************************************************************************/ - -int up_rtc_settime(const struct timespec *tp) -{ - struct tm newtime; - - /* Break out the time values (not that the time is set only to units of - * seconds) - */ - - gmtime_r(&tp->tv_sec, &newtime); - return stm32_rtc_setdatetime(&newtime); -} - -/**************************************************************************** - * Name: stm32_rtc_setalarm - * - * Description: - * Set an alarm to an absolute time using associated hardware. - * - * Input Parameters: - * alminfo - Information about the alarm configuration. - * - * Returned Value: - * Zero (OK) on success; a negated errno on failure - * - ****************************************************************************/ - -#ifdef CONFIG_RTC_ALARM -int stm32_rtc_setalarm(struct alm_setalarm_s *alminfo) -{ - struct alm_cbinfo_s *cbinfo; - rtc_alarmreg_t alarmreg; - int ret = -EINVAL; - - DEBUGASSERT(alminfo != NULL); - DEBUGASSERT(RTC_ALARM_LAST > alminfo->as_id); - - /* Make sure the alarm interrupt is enabled at the NVIC */ - - rtc_enable_alarm(); - - /* REVISIT: Should test that the time is in the future */ - - rtc_dumptime(&alminfo->as_time, "New alarm time"); - - /* Break out the values to the HW alarm register format. The values in - * all STM32 fields match the fields of struct tm in this case. Notice - * that the alarm is limited to one month. - */ - - alarmreg = (rtc_bin2bcd(alminfo->as_time.tm_sec) << RTC_ALRMR_SU_SHIFT) | - (rtc_bin2bcd(alminfo->as_time.tm_min) << RTC_ALRMR_MNU_SHIFT) | - (rtc_bin2bcd(alminfo->as_time.tm_hour) << RTC_ALRMR_HU_SHIFT) | - (rtc_bin2bcd(alminfo->as_time.tm_mday) << RTC_ALRMR_DU_SHIFT); - - /* Set the alarm in hardware and enable interrupts from the RTC */ - - switch (alminfo->as_id) - { - case RTC_ALARMA: - { - cbinfo = &g_alarmcb[RTC_ALARMA]; - cbinfo->ac_cb = alminfo->as_cb; - cbinfo->ac_arg = alminfo->as_arg; - - ret = rtchw_set_alrmar(alarmreg | RTC_ALRMR_ENABLE); - if (ret < 0) - { - cbinfo->ac_cb = NULL; - cbinfo->ac_arg = NULL; - } - } - break; - -#if CONFIG_RTC_NALARMS > 1 - case RTC_ALARMB: - { - cbinfo = &g_alarmcb[RTC_ALARMB]; - cbinfo->ac_cb = alminfo->as_cb; - cbinfo->ac_arg = alminfo->as_arg; - - ret = rtchw_set_alrmbr(alarmreg | RTC_ALRMR_ENABLE); - if (ret < 0) - { - cbinfo->ac_cb = NULL; - cbinfo->ac_arg = NULL; - } - } - break; -#endif - - default: - rtcerr("ERROR: Invalid ALARM%d\n", alminfo->as_id); - break; - } - - rtc_dumpregs("After alarm setting"); - - return ret; -} -#endif - -/**************************************************************************** - * Name: stm32_rtc_cancelalarm - * - * Description: - * Cancel an alarm. - * - * Input Parameters: - * alarmid - Identifies the alarm to be cancelled - * - * Returned Value: - * Zero (OK) on success; a negated errno on failure - * - ****************************************************************************/ - -#ifdef CONFIG_RTC_ALARM -int stm32_rtc_cancelalarm(enum alm_id_e alarmid) -{ - int ret = -EINVAL; - - DEBUGASSERT(RTC_ALARM_LAST > alarmid); - - /* Cancel the alarm in hardware and disable interrupts */ - - switch (alarmid) - { - case RTC_ALARMA: - { - /* Cancel the global callback function */ - - g_alarmcb[alarmid].ac_cb = NULL; - g_alarmcb[alarmid].ac_arg = NULL; - - /* Disable the write protection for RTC registers */ - - rtc_wprunlock(); - - /* Disable RTC alarm and interrupt */ - - modifyreg32(STM32_RTC_CR, (RTC_CR_ALRAE | RTC_CR_ALRAIE), 0); - - ret = rtchw_check_alrawf(); - if (ret < 0) - { - goto errout_with_wprunlock; - } - - /* Unset the alarm */ - - putreg32(-1, STM32_RTC_ALRMAR); - modifyreg32(STM32_RTC_ISR, RTC_ISR_ALRAF, 0); - rtc_wprlock(); - ret = OK; - } - break; - -#if CONFIG_RTC_NALARMS > 1 - case RTC_ALARMB: - { - /* Cancel the global callback function */ - - g_alarmcb[alarmid].ac_cb = NULL; - g_alarmcb[alarmid].ac_arg = NULL; - - /* Disable the write protection for RTC registers */ - - rtc_wprunlock(); - - /* Disable RTC alarm and interrupt */ - - modifyreg32(STM32_RTC_CR, (RTC_CR_ALRBE | RTC_CR_ALRBIE), 0); - - ret = rtchw_check_alrbwf(); - if (ret < 0) - { - goto errout_with_wprunlock; - } - - /* Unset the alarm */ - - putreg32(-1, STM32_RTC_ALRMBR); - modifyreg32(STM32_RTC_ISR, RTC_ISR_ALRBF, 0); - rtc_wprlock(); - ret = OK; - } - break; -#endif - - default: - rtcerr("ERROR: Invalid ALARM%d\n", alarmid); - break; - } - - return ret; - -errout_with_wprunlock: - rtc_wprlock(); - return ret; -} -#endif - -/**************************************************************************** - * Name: stm32_rtc_rdalarm - * - * Description: - * Query an alarm configured in hardware. - * - * Input Parameters: - * alminfo - Information about the alarm configuration. - * - * Returned Value: - * Zero (OK) on success; a negated errno on failure - * - ****************************************************************************/ - -#ifdef CONFIG_RTC_ALARM -int stm32_rtc_rdalarm(struct alm_rdalarm_s *alminfo) -{ - rtc_alarmreg_t alarmreg; - int ret = -EINVAL; - - DEBUGASSERT(alminfo != NULL); - DEBUGASSERT(RTC_ALARM_LAST > alminfo->ar_id); - - switch (alminfo->ar_id) - { - case RTC_ALARMA: - { - alarmreg = STM32_RTC_ALRMAR; - ret = stm32_rtc_getalarmdatetime(alarmreg, - (struct tm *)alminfo->ar_time); - } - break; - -#if CONFIG_RTC_NALARMS > 1 - case RTC_ALARMB: - { - alarmreg = STM32_RTC_ALRMBR; - ret = stm32_rtc_getalarmdatetime(alarmreg, - (struct tm *)alminfo->ar_time); - } - break; -#endif - - default: - rtcerr("ERROR: Invalid ALARM%d\n", alminfo->ar_id); - break; - } - - return ret; -} -#endif - -/**************************************************************************** - * Name: stm32_rtc_wakeup_handler - * - * Description: - * RTC WAKEUP interrupt service routine through the EXTI line - * - * Input Parameters: - * irq - The IRQ number that generated the interrupt - * - * Returned Value: - * Zero (OK) on success; A negated errno value on failure. - * - ****************************************************************************/ - -#ifdef CONFIG_RTC_PERIODIC -static int stm32_rtc_wakeup_handler(int irq, void *context, - void *arg) -{ - uint32_t regval = 0; - - stm32_pwr_enablebkp(true); - - regval = getreg32(STM32_RTC_ISR); - regval &= ~RTC_ISR_WUTF; - putreg32(regval, STM32_RTC_ISR); - - stm32_pwr_enablebkp(false); - - if (g_wakeupcb != NULL) - { - g_wakeupcb(); - } - - return OK; -} -#endif - -/**************************************************************************** - * Name: rtc_enable_wakeup - * - * Description: - * Enable periodic wakeup interrupts - * - ****************************************************************************/ - -#ifdef CONFIG_RTC_PERIODIC -static inline void rtc_enable_wakeup(void) -{ - if (!g_wakeup_enabled) - { - stm32_exti_wakeup(true, false, true, stm32_rtc_wakeup_handler, NULL); - g_wakeup_enabled = true; - } -} -#endif - -/**************************************************************************** - * Name: rtc_set_wcksel - * - * Description: - * Sets RTC wakeup clock selection value - * - ****************************************************************************/ - -#ifdef CONFIG_RTC_PERIODIC -static inline void rtc_set_wcksel(unsigned int wucksel) -{ - uint32_t regval = 0; - - regval = getreg32(STM32_RTC_CR); - regval &= ~RTC_CR_WUCKSEL_MASK; - regval |= wucksel; - putreg32(regval, STM32_RTC_CR); -} -#endif - -/**************************************************************************** - * Name: stm32_rtc_setperiodic - * - * Description: - * Set a periodic RTC wakeup - * - * Input Parameters: - * period - Time to sleep between wakeups - * callback - Function to call when the period expires. - * - * Returned Value: - * Zero (OK) on success; a negated errno on failure - * - ****************************************************************************/ - -#ifdef CONFIG_RTC_PERIODIC -int stm32_rtc_setperiodic(const struct timespec *period, - wakeupcb_t callback) -{ - unsigned int wutr_val; - int ret; - int timeout; - uint32_t regval; - uint32_t secs; - uint32_t millisecs; - -#if defined(CONFIG_STM32_RTC_HSECLOCK) -# error "Periodic wakeup not available for HSE" -#elif defined(CONFIG_STM32_RTC_LSICLOCK) -# error "Periodic wakeup not available for LSI (and it is too inaccurate!)" -#elif defined(CONFIG_STM32_RTC_LSECLOCK) - const uint32_t rtc_div16_max_msecs = 16 * 1000 * 0xffffu / - STM32_LSE_FREQUENCY; -#else -# error "No clock for RTC!" -#endif - - /* Lets use RTC wake-up with 0.001 sec to ~18 hour range. - * - * TODO: scale to higher periods, with necessary losing some precision. - * We currently go for subseconds accuracy instead of maximum period. - */ - - if (period->tv_sec > 0xffffu || - (period->tv_sec == 0xffffu && period->tv_nsec > 0)) - { - /* More than max. */ - - secs = 0xffffu; - millisecs = secs * 1000; - } - else - { - secs = period->tv_sec; - millisecs = secs * 1000 + period->tv_nsec / NSEC_PER_MSEC; - } - - if (millisecs == 0) - { - return -EINVAL; - } - - /* Make sure the alarm interrupt is enabled at the NVIC */ - - rtc_enable_wakeup(); - - rtc_wprunlock(); - - /* Clear WUTE in RTC_CR to disable the wakeup timer */ - - regval = getreg32(STM32_RTC_CR); - regval &= ~RTC_CR_WUTE; - putreg32(regval, STM32_RTC_CR); - - /* Poll WUTWF until it is set in RTC_ISR (takes around 2 RTCCLK clock - * cycles) - */ - - ret = -ETIMEDOUT; - for (timeout = 0; timeout < SYNCHRO_TIMEOUT; timeout++) - { - regval = getreg32(STM32_RTC_ISR); - if ((regval & RTC_ISR_WUTWF) != 0) - { - /* Synchronized */ - - ret = OK; - break; - } - } - - /* Set callback function pointer. */ - - g_wakeupcb = callback; - - if (millisecs <= rtc_div16_max_msecs) - { - unsigned int ticks; - - /* Select wake-up with 32768/16 hz counter. */ - - rtc_set_wcksel(RTC_CR_WUCKSEL_RTCDIV16); - - /* Get number of ticks. */ - - ticks = millisecs * STM32_LSE_FREQUENCY / (16 * 1000); - - /* Wake-up is after WUT+1 ticks. */ - - wutr_val = ticks - 1; - } - else - { - /* Select wake-up with 1hz counter. */ - - rtc_set_wcksel(RTC_CR_WUCKSEL_CKSPRE); - - /* Wake-up is after WUT+1 ticks. */ - - wutr_val = secs - 1; - } - - /* Program the wakeup auto-reload value WUT[15:0], and the wakeup clock - * selection. - */ - - putreg32(wutr_val, STM32_RTC_WUTR); - - regval = getreg32(STM32_RTC_CR); - regval |= RTC_CR_WUTIE | RTC_CR_WUTE; - putreg32(regval, STM32_RTC_CR); - - /* Just in case resets the WUTF flag in RTC_ISR */ - - regval = getreg32(STM32_RTC_ISR); - regval &= ~RTC_ISR_WUTF; - putreg32(regval, STM32_RTC_ISR); - - rtc_wprlock(); - - return ret; -} -#endif - -/**************************************************************************** - * Name: stm32_rtc_cancelperiodic - * - * Description: - * Cancel a periodic wakeup - * - * Input Parameters: - * - * Returned Value: - * Zero (OK) on success; a negated errno on failure - * - ****************************************************************************/ - -#ifdef CONFIG_RTC_PERIODIC -int stm32_rtc_cancelperiodic(void) -{ - int ret = OK; - int timeout = 0; - uint32_t regval = 0; - - rtc_wprunlock(); - - /* Clear WUTE and WUTIE in RTC_CR to disable the wakeup timer */ - - regval = getreg32(STM32_RTC_CR); - regval &= ~(RTC_CR_WUTE | RTC_CR_WUTIE); - putreg32(regval, STM32_RTC_CR); - - /* Poll WUTWF until it is set in RTC_ISR (takes around 2 RTCCLK clock - * cycles) - */ - - ret = -ETIMEDOUT; - for (timeout = 0; timeout < SYNCHRO_TIMEOUT; timeout++) - { - regval = getreg32(STM32_RTC_ISR); - if ((regval & RTC_ISR_WUTWF) != 0) - { - /* Synchronized */ - - ret = OK; - break; - } - } - - /* Clears RTC_WUTR register */ - - regval = getreg32(STM32_RTC_WUTR); - regval &= ~RTC_WUTR_MASK; - putreg32(regval, STM32_RTC_WUTR); - - rtc_wprlock(); - - return ret; -} -#endif - -#endif /* CONFIG_STM32_RTC */ diff --git a/arch/arm/src/stm32c0/CMakeLists.txt b/arch/arm/src/stm32c0/CMakeLists.txt new file mode 100644 index 0000000000000..c795baf9c0418 --- /dev/null +++ b/arch/arm/src/stm32c0/CMakeLists.txt @@ -0,0 +1,32 @@ +# ############################################################################## +# arch/arm/src/stm32c0/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(SRCS) + +list(APPEND SRCS stm32_rcc.c) + +if(CONFIG_BUILD_PROTECTED) + list(APPEND SRCS stm32_userspace.c) +endif() + +target_sources(arch PRIVATE ${SRCS}) +add_subdirectory(${NUTTX_DIR}/arch/arm/src/common/stm32 stm32_common) diff --git a/arch/arm/src/stm32c0/Kconfig b/arch/arm/src/stm32c0/Kconfig new file mode 100644 index 0000000000000..c8f8b5164c77f --- /dev/null +++ b/arch/arm/src/stm32c0/Kconfig @@ -0,0 +1,282 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# +comment "STM32 C0 configuration" + +if ARCH_CHIP_STM32C0 + +choice + prompt "ST STM32C0 Chip Selection" + default ARCH_CHIP_STM32C071RB + depends on ARCH_CHIP_STM32C0 + +config ARCH_CHIP_STM32C051D8 + bool "STM32C051D8" + select ARCH_CHIP_STM32C051XX + select STM32_FLASH_CONFIG_8 + +config ARCH_CHIP_STM32C051F6 + bool "STM32C051F6" + select ARCH_CHIP_STM32C051XX + select STM32_FLASH_CONFIG_6 + +config ARCH_CHIP_STM32C051F8 + bool "STM32C051F8" + select ARCH_CHIP_STM32C051XX + select STM32_FLASH_CONFIG_8 + +config ARCH_CHIP_STM32C051G6 + bool "STM32C051G6" + select ARCH_CHIP_STM32C051XX + select STM32_FLASH_CONFIG_6 + +config ARCH_CHIP_STM32C051G8 + bool "STM32C051G8" + select ARCH_CHIP_STM32C051XX + select STM32_FLASH_CONFIG_8 + +config ARCH_CHIP_STM32C051K6 + bool "STM32C051K6" + select ARCH_CHIP_STM32C051XX + select STM32_FLASH_CONFIG_6 + +config ARCH_CHIP_STM32C051K8 + bool "STM32C051K8" + select ARCH_CHIP_STM32C051XX + select STM32_FLASH_CONFIG_8 + +config ARCH_CHIP_STM32C051C6 + bool "STM32C051C6" + select ARCH_CHIP_STM32C051XX + select STM32_FLASH_CONFIG_6 + +config ARCH_CHIP_STM32C051C8 + bool "STM32C051C8" + select ARCH_CHIP_STM32C051XX + select STM32_FLASH_CONFIG_8 + +config ARCH_CHIP_STM32C071F8 + bool "STM32C071F8" + select ARCH_CHIP_STM32C071XX + select STM32_FLASH_CONFIG_8 + +config ARCH_CHIP_STM32C071FB + bool "STM32C071FB" + select ARCH_CHIP_STM32C071XX + select STM32_FLASH_CONFIG_B + +config ARCH_CHIP_STM32C071G8 + bool "STM32C071G8" + select ARCH_CHIP_STM32C071XX + select STM32_FLASH_CONFIG_8 + +config ARCH_CHIP_STM32C071GB + bool "STM32C071GB" + select ARCH_CHIP_STM32C071XX + select STM32_FLASH_CONFIG_B + +config ARCH_CHIP_STM32C071K8 + bool "STM32C071K8" + select ARCH_CHIP_STM32C071XX + select STM32_FLASH_CONFIG_8 + +config ARCH_CHIP_STM32C071KB + bool "STM32C071KB" + select ARCH_CHIP_STM32C071XX + select STM32_FLASH_CONFIG_B + +config ARCH_CHIP_STM32C071C8 + bool "STM32C071C8" + select ARCH_CHIP_STM32C071XX + select STM32_FLASH_CONFIG_8 + +config ARCH_CHIP_STM32C071CB + bool "STM32C071CB" + select ARCH_CHIP_STM32C071XX + select STM32_FLASH_CONFIG_B + +config ARCH_CHIP_STM32C071R8 + bool "STM32C071R8" + select ARCH_CHIP_STM32C071XX + select STM32_FLASH_CONFIG_8 + +config ARCH_CHIP_STM32C071RB + bool "STM32C071RB" + select ARCH_CHIP_STM32C071XX + select STM32_FLASH_CONFIG_B + +config ARCH_CHIP_STM32C091FB + bool "STM32C091FB" + select ARCH_CHIP_STM32C091XX + select STM32_FLASH_CONFIG_B + +config ARCH_CHIP_STM32C091FC + bool "STM32C091FC" + select ARCH_CHIP_STM32C091XX + select STM32_FLASH_CONFIG_C + +config ARCH_CHIP_STM32C091EC + bool "STM32C091EC" + select ARCH_CHIP_STM32C091XX + select STM32_FLASH_CONFIG_C + +config ARCH_CHIP_STM32C091GB + bool "STM32C091GB" + select ARCH_CHIP_STM32C091XX + select STM32_FLASH_CONFIG_B + +config ARCH_CHIP_STM32C091GC + bool "STM32C091GC" + select ARCH_CHIP_STM32C091XX + select STM32_FLASH_CONFIG_C + +config ARCH_CHIP_STM32C091KB + bool "STM32C091KB" + select ARCH_CHIP_STM32C091XX + select STM32_FLASH_CONFIG_B + +config ARCH_CHIP_STM32C091KC + bool "STM32C091KC" + select ARCH_CHIP_STM32C091XX + select STM32_FLASH_CONFIG_C + +config ARCH_CHIP_STM32C091CB + bool "STM32C091CB" + select ARCH_CHIP_STM32C091XX + select STM32_FLASH_CONFIG_B + +config ARCH_CHIP_STM32C091CC + bool "STM32C091CC" + select ARCH_CHIP_STM32C091XX + select STM32_FLASH_CONFIG_C + +config ARCH_CHIP_STM32C091RB + bool "STM32C091RB" + select ARCH_CHIP_STM32C091XX + select STM32_FLASH_CONFIG_B + +config ARCH_CHIP_STM32C091RC + bool "STM32C091RC" + select ARCH_CHIP_STM32C091XX + select STM32_FLASH_CONFIG_C + +config ARCH_CHIP_STM32C092FB + bool "STM32C092FB" + select ARCH_CHIP_STM32C092XX + select STM32_FLASH_CONFIG_B + +config ARCH_CHIP_STM32C092FC + bool "STM32C092FC" + select ARCH_CHIP_STM32C092XX + select STM32_FLASH_CONFIG_C + +config ARCH_CHIP_STM32C092EC + bool "STM32C092EC" + select ARCH_CHIP_STM32C092XX + select STM32_FLASH_CONFIG_C + +config ARCH_CHIP_STM32C092GB + bool "STM32C092GB" + select ARCH_CHIP_STM32C092XX + select STM32_FLASH_CONFIG_B + +config ARCH_CHIP_STM32C092GC + bool "STM32C092GC" + select ARCH_CHIP_STM32C092XX + select STM32_FLASH_CONFIG_C + +config ARCH_CHIP_STM32C092KB + bool "STM32C092KB" + select ARCH_CHIP_STM32C092XX + select STM32_FLASH_CONFIG_B + +config ARCH_CHIP_STM32C092KC + bool "STM32C092KC" + select ARCH_CHIP_STM32C092XX + select STM32_FLASH_CONFIG_C + +config ARCH_CHIP_STM32C092CB + bool "STM32C092CB" + select ARCH_CHIP_STM32C092XX + select STM32_FLASH_CONFIG_B + +config ARCH_CHIP_STM32C092CC + bool "STM32C092CC" + select ARCH_CHIP_STM32C092XX + select STM32_FLASH_CONFIG_C + +config ARCH_CHIP_STM32C092RB + bool "STM32C092RB" + select ARCH_CHIP_STM32C092XX + select STM32_FLASH_CONFIG_B + +config ARCH_CHIP_STM32C092RC + bool "STM32C092RC" + select ARCH_CHIP_STM32C092XX + select STM32_FLASH_CONFIG_C + +endchoice + +endif + +config STM32_STM32C0 + bool + default n + select STM32_HAVE_DMA1 + select STM32_HAVE_USART1 + select STM32_HAVE_USART2 + select STM32_HAVE_SPI2 + select STM32_HAVE_I2C2 + select STM32_HAVE_DMAMUX + select STM32_HAVE_IP_ADC_M0_V1 + select STM32_HAVE_IP_AES_M0_V1 if STM32_HAVE_AES + select STM32_HAVE_IP_COMP_M0_V1 if STM32_HAVE_COMP + select STM32_HAVE_IP_DAC_M0_V1 if STM32_HAVE_DAC1 + select STM32_HAVE_IP_DBGMCU_M0_V1 + select STM32_HAVE_IP_DMA_V1 + select STM32_HAVE_IP_FDCAN_MCAN_M0_V1 + select STM32_HAVE_IP_DMA_V1_7CH_DMAMUX + select STM32_HAVE_IP_EXTI_V2 + select STM32_HAVE_IP_FLASH_M0_V1 + select STM32_HAVE_IP_FLASH_M0_G0C0 + select STM32_HAVE_IP_GPIO_M0_V1 + select STM32_HAVE_IP_I2C_M0_V1 + select STM32_HAVE_IP_PWR_G0 + select STM32_HAVE_IP_RNG_M0_V1 if STM32_HAVE_RNG + select STM32_HAVE_IP_RTCC_M0_V1 + select STM32_HAVE_IP_SPI_V2 + select STM32_HAVE_IP_TIMERS_M0_V1 + select STM32_HAVE_IP_USART_V4 + select STM32_HAVE_IP_WDG_M0_V1 + select STM32_HAVE_IP_USBDEV_M0_V1 if STM32_HAVE_USBDEV + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM3 + select STM32_HAVE_TIM14 + select STM32_HAVE_TIM16 + select STM32_HAVE_TIM17 + select ARCH_HAVE_PROGMEM + +config ARCH_CHIP_STM32C051XX + bool + select STM32_STM32C0 + +config ARCH_CHIP_STM32C071XX + bool + select STM32_STM32C0 + select STM32_HAVE_USBDEV + +config ARCH_CHIP_STM32C091XX + bool + select STM32_STM32C0 + select STM32_HAVE_USART3 + select STM32_HAVE_USART4 + select STM32_HAVE_TIM15 + +config ARCH_CHIP_STM32C092XX + bool + select STM32_STM32C0 + select STM32_HAVE_USART3 + select STM32_HAVE_USART4 + select STM32_HAVE_FDCAN1 diff --git a/arch/arm/src/stm32c0/Make.defs b/arch/arm/src/stm32c0/Make.defs new file mode 100644 index 0000000000000..f7f9d727e6765 --- /dev/null +++ b/arch/arm/src/stm32c0/Make.defs @@ -0,0 +1,31 @@ +############################################################################ +# arch/arm/src/stm32c0/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include armv6-m/Make.defs + +CHIP_CSRCS = stm32_rcc.c + +ifeq ($(CONFIG_BUILD_PROTECTED),y) +CHIP_CSRCS += stm32_userspace.c +endif + +include common/stm32/Make.defs diff --git a/arch/arm/src/stm32c0/chip.h b/arch/arm/src/stm32c0/chip.h new file mode 100644 index 0000000000000..e65e4fc23f633 --- /dev/null +++ b/arch/arm/src/stm32c0/chip.h @@ -0,0 +1,44 @@ +/**************************************************************************** + * arch/arm/src/stm32c0/chip.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32C0_CHIP_H +#define __ARCH_ARM_SRC_STM32C0_CHIP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include "nvic.h" + +/* Include the chip capabilities file */ + +#include + +/* Include the memory map file. + * Other chip hardware files should then include this file for the proper + * setup. + */ + +#include "hardware/stm32_memorymap.h" + +#endif /* __ARCH_ARM_SRC_STM32C0_CHIP_H */ diff --git a/arch/arm/src/stm32c0/hardware/stm32_memorymap.h b/arch/arm/src/stm32c0/hardware/stm32_memorymap.h new file mode 100644 index 0000000000000..455026d894141 --- /dev/null +++ b/arch/arm/src/stm32c0/hardware/stm32_memorymap.h @@ -0,0 +1,17 @@ +/**************************************************************************** + * arch/arm/src/stm32c0/hardware/stm32_memorymap.h + * + * SPDX-License-Identifier: Apache-2.0 + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32C0_HARDWARE_STM32_MEMORYMAP_H +#define __ARCH_ARM_SRC_STM32C0_HARDWARE_STM32_MEMORYMAP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "hardware/stm32c0_memorymap.h" + +#endif /* __ARCH_ARM_SRC_STM32C0_HARDWARE_STM32_MEMORYMAP_H */ diff --git a/arch/arm/src/stm32c0/hardware/stm32_pinmap.h b/arch/arm/src/stm32c0/hardware/stm32_pinmap.h new file mode 100644 index 0000000000000..4d31e5c8a3ed0 --- /dev/null +++ b/arch/arm/src/stm32c0/hardware/stm32_pinmap.h @@ -0,0 +1,17 @@ +/**************************************************************************** + * arch/arm/src/stm32c0/hardware/stm32_pinmap.h + * + * SPDX-License-Identifier: Apache-2.0 + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32C0_HARDWARE_STM32_PINMAP_H +#define __ARCH_ARM_SRC_STM32C0_HARDWARE_STM32_PINMAP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "hardware/stm32c0_pinmap.h" + +#endif /* __ARCH_ARM_SRC_STM32C0_HARDWARE_STM32_PINMAP_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32c0_dmamux.h b/arch/arm/src/stm32c0/hardware/stm32c0_dmamux.h similarity index 89% rename from arch/arm/src/stm32f0l0g0/hardware/stm32c0_dmamux.h rename to arch/arm/src/stm32c0/hardware/stm32c0_dmamux.h index 1d91dc308bca1..1e03567fdd5f7 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32c0_dmamux.h +++ b/arch/arm/src/stm32c0/hardware/stm32c0_dmamux.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32c0_dmamux.h + * arch/arm/src/stm32c0/hardware/stm32c0_dmamux.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32C0_DMAMUX_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32C0_DMAMUX_H +#ifndef __ARCH_ARM_SRC_STM32C0_HARDWARE_STM32C0_DMAMUX_H +#define __ARCH_ARM_SRC_STM32C0_HARDWARE_STM32C0_DMAMUX_H /**************************************************************************** * Included Files @@ -54,4 +54,4 @@ #define DMAMAP_DMA1_REQGEN3 DMAMAP_MAP(DMA1, DMAMUX1_REQ_GEN3) #define DMAMAP_DMA1_ADC1 DMAMAP_MAP(DMA1, DMAMUX1_ADC1) -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32C0_DMAMUX_H */ +#endif /* __ARCH_ARM_SRC_STM32C0_HARDWARE_STM32C0_DMAMUX_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32c0_exti.h b/arch/arm/src/stm32c0/hardware/stm32c0_exti.h similarity index 95% rename from arch/arm/src/stm32f0l0g0/hardware/stm32c0_exti.h rename to arch/arm/src/stm32c0/hardware/stm32c0_exti.h index 800a7a4faff96..666034a22cd35 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32c0_exti.h +++ b/arch/arm/src/stm32c0/hardware/stm32c0_exti.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32c0_exti.h + * arch/arm/src/stm32c0/hardware/stm32c0_exti.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32C0_EXTI_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32C0_EXTI_H +#ifndef __ARCH_ARM_SRC_STM32C0_HARDWARE_STM32C0_EXTI_H +#define __ARCH_ARM_SRC_STM32C0_HARDWARE_STM32C0_EXTI_H /**************************************************************************** * Included Files @@ -87,4 +87,4 @@ /* TODO */ -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32C0_EXTI_H */ +#endif /* __ARCH_ARM_SRC_STM32C0_HARDWARE_STM32C0_EXTI_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32c0_flash.h b/arch/arm/src/stm32c0/hardware/stm32c0_flash.h similarity index 97% rename from arch/arm/src/stm32f0l0g0/hardware/stm32c0_flash.h rename to arch/arm/src/stm32c0/hardware/stm32c0_flash.h index dfcdb1e5e133f..0fb3d2d084424 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32c0_flash.h +++ b/arch/arm/src/stm32c0/hardware/stm32c0_flash.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32c0_flash.h + * arch/arm/src/stm32c0/hardware/stm32c0_flash.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32C0_FLASH_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32C0_FLASH_H +#ifndef __ARCH_ARM_SRC_STM32C0_HARDWARE_STM32C0_FLASH_H +#define __ARCH_ARM_SRC_STM32C0_HARDWARE_STM32C0_FLASH_H /**************************************************************************** * Included Files @@ -202,4 +202,4 @@ #define FLASH_SECR_BOOT_LOCK (1 << 16) /* Bit 16: Used to force boot from user area */ /* Bits 20-31: Reserved */ -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32C0_FLASH_H */ +#endif /* __ARCH_ARM_SRC_STM32C0_HARDWARE_STM32C0_FLASH_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32c0_memorymap.h b/arch/arm/src/stm32c0/hardware/stm32c0_memorymap.h similarity index 96% rename from arch/arm/src/stm32f0l0g0/hardware/stm32c0_memorymap.h rename to arch/arm/src/stm32c0/hardware/stm32c0_memorymap.h index c847f7ca05088..212d3f4a95cc8 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32c0_memorymap.h +++ b/arch/arm/src/stm32c0/hardware/stm32c0_memorymap.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32c0_memorymap.h + * arch/arm/src/stm32c0/hardware/stm32c0_memorymap.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32C0_MEMORYMAP_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32C0_MEMORYMAP_H +#ifndef __ARCH_ARM_SRC_STM32C0_HARDWARE_STM32C0_MEMORYMAP_H +#define __ARCH_ARM_SRC_STM32C0_HARDWARE_STM32C0_MEMORYMAP_H /**************************************************************************** * Pre-processor Definitions @@ -115,4 +115,4 @@ #define STM32_SYSMEM_UID 0x1fff7550 /* The 96-bit unique device identifier */ -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32C0_MEMORYMAP_H */ +#endif /* __ARCH_ARM_SRC_STM32C0_HARDWARE_STM32C0_MEMORYMAP_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32c0_pinmap.h b/arch/arm/src/stm32c0/hardware/stm32c0_pinmap.h similarity index 98% rename from arch/arm/src/stm32f0l0g0/hardware/stm32c0_pinmap.h rename to arch/arm/src/stm32c0/hardware/stm32c0_pinmap.h index 4e10209f8a623..5d8805236ed52 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32c0_pinmap.h +++ b/arch/arm/src/stm32c0/hardware/stm32c0_pinmap.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32c0_pinmap.h + * arch/arm/src/stm32c0/hardware/stm32c0_pinmap.h * * SPDX-License-Identifier: Apache-2.0 * @@ -32,8 +32,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32C0_PINMAP_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32C0_PINMAP_H +#ifndef __ARCH_ARM_SRC_STM32C0_HARDWARE_STM32C0_PINMAP_H +#define __ARCH_ARM_SRC_STM32C0_HARDWARE_STM32C0_PINMAP_H /**************************************************************************** * Included Files @@ -351,4 +351,4 @@ #define GPIO_TIM17_CH1NOUT_1 (GPIO_ALT | GPIO_AF5 | GPIO_PORTA | GPIO_PIN4) #define GPIO_TIM17_CH1NOUT_2 (GPIO_ALT | GPIO_AF2 | GPIO_PORTB | GPIO_PIN7) -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32C0_PINMAP_H */ +#endif /* __ARCH_ARM_SRC_STM32C0_HARDWARE_STM32C0_PINMAP_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32c0_pwr.h b/arch/arm/src/stm32c0/hardware/stm32c0_pwr.h similarity index 97% rename from arch/arm/src/stm32f0l0g0/hardware/stm32c0_pwr.h rename to arch/arm/src/stm32c0/hardware/stm32c0_pwr.h index 7c16d410baf47..0b6db18987c6c 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32c0_pwr.h +++ b/arch/arm/src/stm32c0/hardware/stm32c0_pwr.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32c0_pwr.h + * arch/arm/src/stm32c0/hardware/stm32c0_pwr.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32C0_PWR_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32C0_PWR_H +#ifndef __ARCH_ARM_SRC_STM32C0_HARDWARE_STM32C0_PWR_H +#define __ARCH_ARM_SRC_STM32C0_HARDWARE_STM32C0_PWR_H /**************************************************************************** * Included Files @@ -150,4 +150,4 @@ #define PWR_BKPR_MASK (0xffff) /* Bits 0-16: Backup bitfield */ -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32C0_PWR_H */ +#endif /* __ARCH_ARM_SRC_STM32C0_HARDWARE_STM32C0_PWR_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32c0_rcc.h b/arch/arm/src/stm32c0/hardware/stm32c0_rcc.h similarity index 99% rename from arch/arm/src/stm32f0l0g0/hardware/stm32c0_rcc.h rename to arch/arm/src/stm32c0/hardware/stm32c0_rcc.h index 10119b6e62dad..9784111a9b184 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32c0_rcc.h +++ b/arch/arm/src/stm32c0/hardware/stm32c0_rcc.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32c0_rcc.h + * arch/arm/src/stm32c0/hardware/stm32c0_rcc.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32C0_RCC_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32C0_RCC_H +#ifndef __ARCH_ARM_SRC_STM32C0_HARDWARE_STM32C0_RCC_H +#define __ARCH_ARM_SRC_STM32C0_HARDWARE_STM32C0_RCC_H /**************************************************************************** * Pre-processor Definitions @@ -394,4 +394,4 @@ #define RCC_CSR2_WWDGRSTF (1 << 30) /* Bit 30: WWDG reset flag */ #define RCC_CSR2_LPWRRSTF (1 << 31) /* Bit 31: Low-power reset flag */ -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32C0_RCC_H */ +#endif /* __ARCH_ARM_SRC_STM32C0_HARDWARE_STM32C0_RCC_H */ diff --git a/arch/arm/src/stm32c0/stm32.h b/arch/arm/src/stm32c0/stm32.h new file mode 100644 index 0000000000000..7d1c5ae34764f --- /dev/null +++ b/arch/arm/src/stm32c0/stm32.h @@ -0,0 +1,54 @@ +/**************************************************************************** + * arch/arm/src/stm32c0/stm32.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32C0_STM32_H +#define __ARCH_ARM_SRC_STM32C0_STM32_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include +#include + +#include "arm_internal.h" + +/* Peripherals **************************************************************/ + +#include "chip.h" +#include "stm32_dma.h" +#include "stm32_gpio.h" +#include "stm32_i2c.h" +#include "stm32_pwr.h" +#include "stm32_rcc.h" +#include "stm32_spi.h" +#include "stm32_uart.h" +#include "stm32_lowputc.h" +#include "stm32_adc.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#endif /* __ARCH_ARM_SRC_STM32C0_STM32_H */ diff --git a/arch/arm/src/stm32c0/stm32_rcc.c b/arch/arm/src/stm32c0/stm32_rcc.c new file mode 100644 index 0000000000000..4c847902807db --- /dev/null +++ b/arch/arm/src/stm32c0/stm32_rcc.c @@ -0,0 +1,220 @@ +/**************************************************************************** + * arch/arm/src/stm32c0/stm32_rcc.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include + +#include "arm_internal.h" +#include "hardware/stm32_flash.h" +#include "stm32_rcc.h" +#include "stm32_hsi48_m0_v1.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifdef CONFIG_STM32_RNG +# ifndef STM32_USE_CLK48 +# error RNG requires CLK48 enabled +# endif +#endif + +#ifdef CONFIG_STM32_USB +# ifndef STM32_USE_CLK48 +# error USB requires CLK48 enabled +# endif +#endif + +static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1, + "Configure BOARD_LOOPSPERMSEC to non-default value."); + +/* Allow up to 100 milliseconds for the high speed clock to become ready. + * that is a very long delay, but if the clock does not become ready we are + * hosed anyway. + */ + +#define HSERDY_TIMEOUT (100 * CONFIG_BOARD_LOOPSPERMSEC) + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/* Include chip-specific clocking initialization logic */ + +#include "stm32c0_rcc.c" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: rcc_resetbkp + * + * Description: + * The RTC needs to reset the Backup Domain to change RTCSEL and resetting + * the Backup Domain renders to disabling the LSE as consequence. + * In order to avoid resetting the Backup Domain when we already configured + * LSE we will reset the Backup Domain early (here). + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +#if defined(CONFIG_STM32_RTC) && defined(CONFIG_STM32_PWR) +static inline void rcc_resetbkp(void) +{ + uint32_t regval; + + /* Check if the RTC is already configured */ + + stm32_pwr_initbkp(false); + + regval = getreg32(RTC_MAGIC_REG); + if (regval != RTC_MAGIC && regval != RTC_MAGIC_TIME_SET) + { + stm32_pwr_enablebkp(true); + + /* We might be changing RTCSEL - to ensure such changes work, we must + * reset the backup domain (having backed up the RTC_MAGIC token) + */ + + modifyreg32(STM32_RCC_BDCR, 0, RCC_BDCR_BDRST); + modifyreg32(STM32_RCC_BDCR, RCC_BDCR_BDRST, 0); + + stm32_pwr_enablebkp(false); + } +} +#else +# define rcc_resetbkp() +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_clockconfig + * + * Description: + * Called to establish the clock settings based on the values in board.h. + * This function (by default) will reset most everything, enable the PLL, + * and enable peripheral clocking for all peripherals enabled in the NuttX + * configuration file. + * + * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then + * clocking will be enabled by an externally provided, board-specific + * function called stm32_board_clockconfig(). + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void stm32_clockconfig(void) +{ + /* Make sure that we are starting in the reset state */ + + rcc_reset(); + + /* Reset backup domain if appropriate */ + + rcc_resetbkp(); + +#if defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) + /* Invoke Board Custom Clock Configuration */ + + stm32_board_clockconfig(); + +#else + /* Invoke standard, fixed clock configuration based on definitions + * in board.h + */ + + stm32_stdclockconfig(); + +#endif + + /* Enable peripheral clocking */ + + rcc_enableperipherals(); +} + +/**************************************************************************** + * Name: stm32_clockenable + * + * Description: + * Re-enable the clock and restore the clock settings based on settings in + * board.h. This function is only available to support low-power modes of + * operation: When re-awakening from deep-sleep modes, it is necessary to + * re-enable/re-start the PLL + * + * This functional performs a subset of the operations performed by + * stm32_clockconfig(): It does not reset any devices, and it does not + * reset the currently enabled peripheral clocks. + * + * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then + * clocking will be enabled by an externally provided, board-specific + * function called stm32_board_clockconfig(). + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_PM +void stm32_clockenable(void) +{ +#if defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) + /* Invoke Board Custom Clock Configuration */ + + stm32_board_clockconfig(); + +#else + /* Invoke standard, fixed clock configuration based on definitions + * in board.h + */ + + stm32_stdclockconfig(); + +#endif +} +#endif diff --git a/arch/arm/src/stm32f0l0g0/stm32c0_rcc.c b/arch/arm/src/stm32c0/stm32c0_rcc.c similarity index 92% rename from arch/arm/src/stm32f0l0g0/stm32c0_rcc.c rename to arch/arm/src/stm32c0/stm32c0_rcc.c index b483d8637d305..ffa41fc0c6dea 100644 --- a/arch/arm/src/stm32f0l0g0/stm32c0_rcc.c +++ b/arch/arm/src/stm32c0/stm32c0_rcc.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32c0_rcc.c + * arch/arm/src/stm32c0/stm32c0_rcc.c * * SPDX-License-Identifier: Apache-2.0 * @@ -114,31 +114,31 @@ static inline void rcc_enableahb(void) regval = getreg32(STM32_RCC_AHBENR); -#ifdef CONFIG_STM32F0L0G0_DMA1 +#ifdef CONFIG_STM32_DMA1 /* DMA 1 clock enable */ regval |= RCC_AHBENR_DMA1EN; #endif -#ifdef CONFIG_STM32F0L0G0_MIF +#ifdef CONFIG_STM32_MIF /* Memory interface clock enable */ regval |= RCC_AHBENR_MIFEN; #endif -#ifdef CONFIG_STM32F0L0G0_CRC +#ifdef CONFIG_STM32_CRC /* CRC clock enable */ regval |= RCC_AHBENR_CRCEN; #endif -#ifdef CONFIG_STM32F0L0G0_RNG +#ifdef CONFIG_STM32_RNG /* Random number generator clock enable */ regval |= RCC_AHBENR_RNGEN; #endif -#ifdef CONFIG_STM32F0L0G0_AES +#ifdef CONFIG_STM32_AES /* AES modules clock enable */ regval |= RCC_AHBENR_AESEN; @@ -165,67 +165,67 @@ static inline void rcc_enableapb1(void) regval = getreg32(STM32_RCC_APB1ENR); -#ifdef CONFIG_STM32F0L0G0_TIM2 +#ifdef CONFIG_STM32_TIM2 /* Timer 2 clock enable */ regval |= RCC_APB1ENR_TIM2EN; #endif -#ifdef CONFIG_STM32F0L0G0_TIM3 +#ifdef CONFIG_STM32_TIM3 /* Timer 3 clock enable */ regval |= RCC_APB1ENR_TIM3EN; #endif -#ifdef CONFIG_STM32F0L0G0_FDCAN1 +#ifdef CONFIG_STM32_FDCAN1 /* FDCAN1 clock enable */ regval |= RCC_APB1ENR_FDCANEN; #endif -#ifdef CONFIG_STM32F0L0G0_SPI2 +#ifdef CONFIG_STM32_SPI2 /* SPI 2 clock enable */ regval |= RCC_APB1ENR_SPI2EN; #endif -#ifdef CONFIG_STM32F0L0G0_USB +#ifdef CONFIG_STM32_USB /* USB clock enable */ regval |= RCC_APB1ENR_USBEN; #endif -#ifdef CONFIG_STM32F0L0G0_CRC +#ifdef CONFIG_STM32_CRC /* CRC clock enable */ regval |= RCC_APB1ENR_CRCEN; #endif -#ifdef CONFIG_STM32F0L0G0_USART2 +#ifdef CONFIG_STM32_USART2 /* USART 2 clock enable */ regval |= RCC_APB1ENR_USART2EN; #endif -#ifdef CONFIG_STM32F0L0G0_USART3 +#ifdef CONFIG_STM32_USART3 /* USART 3 clock enable */ regval |= RCC_APB1ENR_USART3EN; #endif -#ifdef CONFIG_STM32F0L0G0_USART4 +#ifdef CONFIG_STM32_USART4 /* USART 4 clock enable */ regval |= RCC_APB1ENR_USART4EN; #endif -#ifdef CONFIG_STM32F0L0G0_I2C1 +#ifdef CONFIG_STM32_I2C1 /* I2C 1 clock enable */ regval |= RCC_APB1ENR_I2C1EN; #endif -#ifdef CONFIG_STM32F0L0G0_PWR +#ifdef CONFIG_STM32_PWR /* Power interface clock enable */ regval |= RCC_APB1ENR_PWREN; @@ -252,55 +252,55 @@ static inline void rcc_enableapb2(void) regval = getreg32(STM32_RCC_APB2ENR); -#ifdef CONFIG_STM32F0L0G0_SYSCFG +#ifdef CONFIG_STM32_SYSCFG /* SYSCFG clock */ regval |= RCC_APB2ENR_SYSCFGEN; #endif -#ifdef CONFIG_STM32F0L0G0_TIM1 +#ifdef CONFIG_STM32_TIM1 /* TIM1 Timer clock enable */ regval |= RCC_APB2ENR_TIM1EN; #endif -#ifdef CONFIG_STM32F0L0G0_SPI1 +#ifdef CONFIG_STM32_SPI1 /* SPI 1 clock enable */ regval |= RCC_APB2ENR_SPI1EN; #endif -#ifdef CONFIG_STM32F0L0G0_USART1 +#ifdef CONFIG_STM32_USART1 /* USART1 clock enable */ regval |= RCC_APB2ENR_USART1EN; #endif -#ifdef CONFIG_STM32F0L0G0_TIM14 +#ifdef CONFIG_STM32_TIM14 /* TIM14 Timer clock enable */ regval |= RCC_APB2ENR_TIM14EN; #endif -#ifdef CONFIG_STM32F0L0G0_TIM15 +#ifdef CONFIG_STM32_TIM15 /* TIM5 Timer clock enable */ regval |= RCC_APB2ENR_TIM15EN; #endif -#ifdef CONFIG_STM32F0L0G0_TIM16 +#ifdef CONFIG_STM32_TIM16 /* TIM16 Timer clock enable */ regval |= RCC_APB2ENR_TIM16EN; #endif -#ifdef CONFIG_STM32F0L0G0_TIM17 +#ifdef CONFIG_STM32_TIM17 /* TIM17 Timer clock enable */ regval |= RCC_APB2ENR_TIM17EN; #endif -#ifdef CONFIG_STM32F0L0G0_ADC1 +#ifdef CONFIG_STM32_ADC1 /* ADC 1 clock enable */ regval |= RCC_APB2ENR_ADC1EN; @@ -364,7 +364,7 @@ static inline bool stm32_rcc_enablehse(void) * ****************************************************************************/ -#ifndef CONFIG_ARCH_BOARD_STM32F0G0L0_CUSTOM_CLOCKCONFIG +#ifndef CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG static void stm32_stdclockconfig(void) { uint32_t regval; @@ -457,7 +457,7 @@ static void stm32_stdclockconfig(void) while ((getreg32(STM32_RCC_CFGR) & RCC_CFGR_SWS_MASK) != STM32_SYSCLK_SWS); -#ifdef CONFIG_STM32F0L0G0_FDCAN1 +#ifdef CONFIG_STM32_FDCAN1 /* Configure FDCAN1 clock source */ regval = getreg32(STM32_RCC_CCIPR1); diff --git a/arch/arm/src/stm32f0/CMakeLists.txt b/arch/arm/src/stm32f0/CMakeLists.txt new file mode 100644 index 0000000000000..1d1fbc82d053d --- /dev/null +++ b/arch/arm/src/stm32f0/CMakeLists.txt @@ -0,0 +1,32 @@ +# ############################################################################## +# arch/arm/src/stm32f0/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(SRCS) + +list(APPEND SRCS stm32_rcc.c) + +if(CONFIG_BUILD_PROTECTED) + list(APPEND SRCS stm32_userspace.c) +endif() + +target_sources(arch PRIVATE ${SRCS}) +add_subdirectory(${NUTTX_DIR}/arch/arm/src/common/stm32 stm32_common) diff --git a/arch/arm/src/stm32f0/Kconfig b/arch/arm/src/stm32f0/Kconfig new file mode 100644 index 0000000000000..d3c7b58ba6341 --- /dev/null +++ b/arch/arm/src/stm32f0/Kconfig @@ -0,0 +1,554 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# +comment "STM32 F0 configuration" + +if ARCH_CHIP_STM32F0 + +choice + prompt "ST STM32F0 Chip Selection" + default ARCH_CHIP_STM32F051R8 + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F030C6 + bool "STM32F030C6" + select STM32_STM32F03X + select STM32F0_VALUELINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F030C8 + bool "STM32F030C8" + select STM32_STM32F03X + select STM32F0_VALUELINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F030CC + bool "STM32F030CC" + select STM32_STM32F03X + select STM32F0_VALUELINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F030F4 + bool "STM32F030F4" + select STM32_STM32F03X + select STM32F0_VALUELINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F030K6 + bool "STM32F030K6" + select STM32_STM32F03X + select STM32F0_VALUELINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F030R8 + bool "STM32F030R8" + select STM32_STM32F03X + select STM32F0_VALUELINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F030RC + bool "STM32F030RC" + select STM32_STM32F03X + select STM32F0_VALUELINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F031C4 + bool "STM32F031C4" + select STM32_STM32F03X + select STM32F0_ACCESSLINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F031C6 + bool "STM32F031C6" + select STM32_STM32F03X + select STM32F0_ACCESSLINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F031E6 + bool "STM32F031E6" + select STM32_STM32F03X + select STM32F0_ACCESSLINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F031F4 + bool "STM32F031F4" + select STM32_STM32F03X + select STM32F0_ACCESSLINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F031F6 + bool "STM32F031F6" + select STM32_STM32F03X + select STM32F0_ACCESSLINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F031G4 + bool "STM32F031G4" + select STM32_STM32F03X + select STM32F0_ACCESSLINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F031G6 + bool "STM32F031G6" + select STM32_STM32F03X + select STM32F0_ACCESSLINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F031K4 + bool "STM32F031K4" + select STM32_STM32F03X + select STM32F0_ACCESSLINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F031K6 + bool "STM32F031K6" + select STM32_STM32F03X + select STM32F0_ACCESSLINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F038C6 + bool "STM32F038C6" + select STM32_STM32F03X + select STM32F0_LOWVOLTLINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F038E6 + bool "STM32F038E6" + select STM32_STM32F03X + select STM32F0_LOWVOLTLINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F038F6 + bool "STM32F038F6" + select STM32_STM32F03X + select STM32F0_LOWVOLTLINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F038G6 + bool "STM32F038G6" + select STM32_STM32F03X + select STM32F0_LOWVOLTLINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F038K6 + bool "STM32F038K6" + select STM32_STM32F03X + select STM32F0_LOWVOLTLINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F042C4 + bool "STM32F042C4" + select STM32_STM32F04X + select STM32F0_USBLINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F042C6 + bool "STM32F042C6" + select STM32_STM32F04X + select STM32F0_USBLINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F042F4 + bool "STM32F042F4" + select STM32_STM32F04X + select STM32F0_USBLINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F042F6 + bool "STM32F042F6" + select STM32_STM32F04X + select STM32F0_USBLINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F042G4 + bool "STM32F042G4" + select STM32_STM32F04X + select STM32F0_USBLINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F042G6 + bool "STM32F042G6" + select STM32_STM32F04X + select STM32F0_USBLINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F042K4 + bool "STM32F042K4" + select STM32_STM32F04X + select STM32F0_USBLINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F042K6 + bool "STM32F042K6" + select STM32_STM32F04X + select STM32F0_USBLINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F042T6 + bool "STM32F042T6" + select STM32_STM32F04X + select STM32F0_USBLINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F048C6 + bool "STM32F048C6" + select STM32_STM32F04X + select STM32F0_LOWVOLTLINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F048G6 + bool "STM32F048G6" + select STM32_STM32F04X + select STM32F0_LOWVOLTLINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F048T6 + bool "STM32F048T6" + select STM32_STM32F04X + select STM32F0_LOWVOLTLINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F051C4 + bool "STM32F051C4" + select STM32_STM32F05X + select STM32F0_ACCESSLINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F051C6 + bool "STM32F051C6" + select STM32_STM32F05X + select STM32F0_ACCESSLINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F051C8 + bool "STM32F051C8" + select STM32_STM32F05X + select STM32F0_ACCESSLINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F051K4 + bool "STM32F051K4" + select STM32_STM32F05X + select STM32F0_ACCESSLINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F051K6 + bool "STM32F051K6" + select STM32_STM32F05X + select STM32F0_ACCESSLINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F051K8 + bool "STM32F051K8" + select STM32_STM32F05X + select STM32F0_ACCESSLINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F051R4 + bool "STM32F051R4" + select STM32_STM32F05X + select STM32F0_ACCESSLINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F051R6 + bool "STM32F051R6" + select STM32_STM32F05X + select STM32F0_ACCESSLINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F051R8 + bool "STM32F051R8" + select STM32_STM32F05X + select STM32F0_ACCESSLINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F051T8 + bool "STM32F051T8" + select STM32_STM32F05X + select STM32F0_ACCESSLINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F058C8 + bool "STM32F058C8" + select STM32_STM32F05X + select STM32F0_LOWVOLTLINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F058R8 + bool "STM32F058R8" + select STM32_STM32F05X + select STM32F0_LOWVOLTLINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F058T8 + bool "STM32F058T8" + select STM32_STM32F05X + select STM32F0_LOWVOLTLINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F070C6 + bool "STM32F070C6" + select STM32_STM32F07X + select STM32F0_VALUELINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F070CB + bool "STM32F070CB" + select STM32_STM32F07X + select STM32F0_VALUELINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F070F6 + bool "STM32F070F6" + select STM32_STM32F07X + select STM32F0_VALUELINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F070RB + bool "STM32F070RB" + select STM32_STM32F07X + select STM32F0_VALUELINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F071C8 + bool "STM32F071C8" + select STM32_STM32F07X + select STM32F0_ACCESSLINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F071CB + bool "STM32F071CB" + select STM32_STM32F07X + select STM32F0_ACCESSLINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F071RB + bool "STM32F071RB" + select STM32_STM32F07X + select STM32F0_ACCESSLINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F071V8 + bool "STM32F071V8" + select STM32_STM32F07X + select STM32F0_ACCESSLINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F071VB + bool "STM32F071VB" + select STM32_STM32F07X + select STM32F0_ACCESSLINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F072C8 + bool "STM32F072C8" + select STM32_STM32F07X + select STM32F0_USBLINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F072CB + bool "STM32F072CB" + select STM32_STM32F07X + select STM32F0_USBLINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F072R8 + bool "STM32F072R8" + select STM32_STM32F07X + select STM32F0_USBLINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F072RB + bool "STM32F072RB" + select STM32_STM32F07X + select STM32F0_USBLINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F072V8 + bool "STM32F072V8" + select STM32_STM32F07X + select STM32F0_USBLINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F072VB + bool "STM32F072VB" + select STM32_STM32F07X + select STM32F0_USBLINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F078CB + bool "STM32F078CB" + select STM32_STM32F07X + select STM32F0_LOWVOLTLINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F078RB + bool "STM32F078RB" + select STM32_STM32F07X + select STM32F0_LOWVOLTLINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F078VB + bool "STM32F078VB" + select STM32_STM32F07X + select STM32F0_LOWVOLTLINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F091CB + bool "STM32F091CB" + select STM32_STM32F09X + select STM32F0_ACCESSLINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F091CC + bool "STM32F091CC" + select STM32_STM32F09X + select STM32F0_ACCESSLINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F091RB + bool "STM32F091RB" + select STM32_STM32F09X + select STM32F0_ACCESSLINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F091RC + bool "STM32F091RC" + select STM32_STM32F09X + select STM32F0_ACCESSLINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F091VB + bool "STM32F091VB" + select STM32_STM32F09X + select STM32F0_ACCESSLINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F091VC + bool "STM32F091VC" + select STM32_STM32F09X + select STM32F0_ACCESSLINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F098CC + bool "STM32F098CC" + select STM32_STM32F09X + select STM32F0_LOWVOLTLINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F098RC + bool "STM32F098RC" + select STM32_STM32F09X + select STM32F0_LOWVOLTLINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F098VC + bool "STM32F098VC" + select STM32_STM32F09X + select STM32F0_LOWVOLTLINE + depends on ARCH_CHIP_STM32F0 + +endchoice + +endif + +config STM32_STM32F0 + bool + default n + select STM32_HAVE_DMA1 + select STM32_HAVE_I2C1 + select STM32_HAVE_SPI1 + select STM32_HAVE_USART1 + select STM32_HAVE_USART2 + select STM32_HAVE_USART3 + select STM32_HAVE_USART4 + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM3 + select STM32_HAVE_TIM6 + select STM32_HAVE_TIM7 + select STM32_HAVE_TIM14 + select STM32_HAVE_TIM15 + select STM32_HAVE_TIM16 + select STM32_HAVE_TIM17 + select STM32_HAVE_IP_ADC_M0_V1 + select STM32_HAVE_IP_AES_M0_V1 if STM32_HAVE_AES + select STM32_HAVE_IP_CAN_BXCAN_M0_V1 + select STM32_HAVE_IP_COMP_M0_V1 if STM32_HAVE_COMP + select STM32_HAVE_IP_DAC_M0_V1 if STM32_HAVE_DAC1 + select STM32_HAVE_IP_DBGMCU_M0_V1 + select STM32_HAVE_IP_DMA_V1 + select STM32_HAVE_IP_DMA_V1_7CH + select STM32_HAVE_IP_EXTI_V1 + select STM32_HAVE_IP_FLASH_M0_V1 + select STM32_HAVE_IP_GPIO_M0_V1 + select STM32_HAVE_IP_I2C_M0_V1 + select STM32_HAVE_IP_PWR_M0_V1 + select STM32_HAVE_IP_RNG_M0_V1 if STM32_HAVE_RNG + select STM32_HAVE_IP_RTCC_M0_V1 + select STM32_HAVE_IP_SPI_V2 + select STM32_HAVE_IP_TIMERS_M0_V1 + select STM32_HAVE_IP_USART_V3 + select STM32_HAVE_IP_WDG_M0_V1 + select STM32_HAVE_IP_USBDEV_M0_V1 if STM32_HAVE_USBDEV + select STM32_HAVE_IP_HSI48_M0_V1 if STM32_HAVE_HSI48 + +config STM32_STM32F03X + bool + default n + select STM32_STM32F0 + +config STM32_STM32F04X + bool + default n + select STM32_STM32F0 + select STM32_HAVE_HSI48 + +config STM32_STM32F05X + bool + default n + select STM32_STM32F0 + select STM32_HAVE_DMA2 + +config STM32_STM32F07X + bool + default n + select STM32_STM32F0 + select STM32_HAVE_HSI48 + select STM32_HAVE_DMA2 + +config STM32_STM32F09X + bool + default n + select STM32_STM32F0 + select STM32_HAVE_HSI48 + select STM32_HAVE_DMA2 + +config STM32F0_VALUELINE + bool + default n + select STM32_HAVE_USART5 + select STM32_HAVE_SPI2 + +config STM32F0_ACCESSLINE + bool + default n + select STM32_HAVE_USART5 + select STM32_HAVE_CAN1 + select STM32_HAVE_SPI2 + +config STM32F0_LOWVOLTLINE + bool + default n + select STM32_HAVE_USART5 + select STM32_HAVE_CAN1 + select STM32_HAVE_SPI2 + +config STM32F0_USBLINE + bool + default n + select STM32_HAVE_HSI48 + select STM32_HAVE_CAN1 + select STM32_HAVE_SPI2 + select STM32_HAVE_USBDEV diff --git a/arch/arm/src/stm32f0/Make.defs b/arch/arm/src/stm32f0/Make.defs new file mode 100644 index 0000000000000..54436033fa267 --- /dev/null +++ b/arch/arm/src/stm32f0/Make.defs @@ -0,0 +1,31 @@ +############################################################################ +# arch/arm/src/stm32f0/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include armv6-m/Make.defs + +CHIP_CSRCS = stm32_rcc.c + +ifeq ($(CONFIG_BUILD_PROTECTED),y) +CHIP_CSRCS += stm32_userspace.c +endif + +include common/stm32/Make.defs diff --git a/arch/arm/src/stm32f0/chip.h b/arch/arm/src/stm32f0/chip.h new file mode 100644 index 0000000000000..3e5f5a1103c59 --- /dev/null +++ b/arch/arm/src/stm32f0/chip.h @@ -0,0 +1,44 @@ +/**************************************************************************** + * arch/arm/src/stm32f0/chip.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32F0_CHIP_H +#define __ARCH_ARM_SRC_STM32F0_CHIP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include "nvic.h" + +/* Include the chip capabilities file */ + +#include + +/* Include the memory map file. + * Other chip hardware files should then include this file for the proper + * setup. + */ + +#include "hardware/stm32_memorymap.h" + +#endif /* __ARCH_ARM_SRC_STM32F0_CHIP_H */ diff --git a/arch/arm/src/stm32f0/hardware/stm32_memorymap.h b/arch/arm/src/stm32f0/hardware/stm32_memorymap.h new file mode 100644 index 0000000000000..b11687cda1f94 --- /dev/null +++ b/arch/arm/src/stm32f0/hardware/stm32_memorymap.h @@ -0,0 +1,26 @@ +/**************************************************************************** + * arch/arm/src/stm32f0/hardware/stm32_memorymap.h + * + * SPDX-License-Identifier: Apache-2.0 + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32F0_HARDWARE_STM32_MEMORYMAP_H +#define __ARCH_ARM_SRC_STM32F0_HARDWARE_STM32_MEMORYMAP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#if defined(CONFIG_STM32_STM32F03X) +# include "hardware/stm32f03x_memorymap.h" +#elif defined(CONFIG_STM32_STM32F05X) || defined(CONFIG_STM32_STM32F07X) || \ + defined(CONFIG_STM32_STM32F09X) +# include "hardware/stm32f05xf07xf09x_memorymap.h" +#else +# error "Unsupported STM32F0 memory map" +#endif + +#endif /* __ARCH_ARM_SRC_STM32F0_HARDWARE_STM32_MEMORYMAP_H */ diff --git a/arch/arm/src/stm32f0/hardware/stm32_pinmap.h b/arch/arm/src/stm32f0/hardware/stm32_pinmap.h new file mode 100644 index 0000000000000..847044b52b358 --- /dev/null +++ b/arch/arm/src/stm32f0/hardware/stm32_pinmap.h @@ -0,0 +1,29 @@ +/**************************************************************************** + * arch/arm/src/stm32f0/hardware/stm32_pinmap.h + * + * SPDX-License-Identifier: Apache-2.0 + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32F0_HARDWARE_STM32_PINMAP_H +#define __ARCH_ARM_SRC_STM32F0_HARDWARE_STM32_PINMAP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#if defined(CONFIG_STM32_STM32F03X) +# include "hardware/stm32f03x_pinmap.h" +#elif defined(CONFIG_STM32_STM32F05X) +# include "hardware/stm32f05x_pinmap.h" +#elif defined(CONFIG_STM32_STM32F07X) +# include "hardware/stm32f07x_pinmap.h" +#elif defined(CONFIG_STM32_STM32F09X) +# include "hardware/stm32f09x_pinmap.h" +#else +# error "Unsupported STM32F0 pin map" +#endif + +#endif /* __ARCH_ARM_SRC_STM32F0_HARDWARE_STM32_PINMAP_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32f03x_memorymap.h b/arch/arm/src/stm32f0/hardware/stm32f03x_memorymap.h similarity index 96% rename from arch/arm/src/stm32f0l0g0/hardware/stm32f03x_memorymap.h rename to arch/arm/src/stm32f0/hardware/stm32f03x_memorymap.h index b88eb339fe7ca..c993ab035914f 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32f03x_memorymap.h +++ b/arch/arm/src/stm32f0/hardware/stm32f03x_memorymap.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32f03x_memorymap.h + * arch/arm/src/stm32f0/hardware/stm32f03x_memorymap.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F03X_MEMORYMAP_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F03X_MEMORYMAP_H +#ifndef __ARCH_ARM_SRC_STM32F0_HARDWARE_STM32F03X_MEMORYMAP_H +#define __ARCH_ARM_SRC_STM32F0_HARDWARE_STM32F03X_MEMORYMAP_H /**************************************************************************** * Pre-processor Definitions @@ -141,4 +141,4 @@ #define STM32_SYSMEM_UID 0x1ffff7ac /* The 96-bit unique device identifier */ -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F03X_MEMORYMAP_H */ +#endif /* __ARCH_ARM_SRC_STM32F0_HARDWARE_STM32F03X_MEMORYMAP_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32f03x_pinmap.h b/arch/arm/src/stm32f0/hardware/stm32f03x_pinmap.h similarity index 98% rename from arch/arm/src/stm32f0l0g0/hardware/stm32f03x_pinmap.h rename to arch/arm/src/stm32f0/hardware/stm32f03x_pinmap.h index 1c9bbb9622c17..6a8d81bf82d35 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32f03x_pinmap.h +++ b/arch/arm/src/stm32f0/hardware/stm32f03x_pinmap.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32f03x_pinmap.h + * arch/arm/src/stm32f0/hardware/stm32f03x_pinmap.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F03X_PINMAP_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F03X_PINMAP_H +#ifndef __ARCH_ARM_SRC_STM32F0_HARDWARE_STM32F03X_PINMAP_H +#define __ARCH_ARM_SRC_STM32F0_HARDWARE_STM32F03X_PINMAP_H /**************************************************************************** * Included Files @@ -241,4 +241,4 @@ #define GPIO_USART4_TX_1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTC | GPIO_PIN10) #define GPIO_USART4_TX_2 (GPIO_ALT | GPIO_AF4 | GPIO_PORTA | GPIO_PIN0) -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F03X_PINMAP_H */ +#endif /* __ARCH_ARM_SRC_STM32F0_HARDWARE_STM32F03X_PINMAP_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32f05x_pinmap.h b/arch/arm/src/stm32f0/hardware/stm32f05x_pinmap.h similarity index 95% rename from arch/arm/src/stm32f0l0g0/hardware/stm32f05x_pinmap.h rename to arch/arm/src/stm32f0/hardware/stm32f05x_pinmap.h index 81964a46b93cc..436a483058a33 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32f05x_pinmap.h +++ b/arch/arm/src/stm32f0/hardware/stm32f05x_pinmap.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32f05x_pinmap.h + * arch/arm/src/stm32f0/hardware/stm32f05x_pinmap.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F05X_PINMAP_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F05X_PINMAP_H +#ifndef __ARCH_ARM_SRC_STM32F0_HARDWARE_STM32F05X_PINMAP_H +#define __ARCH_ARM_SRC_STM32F0_HARDWARE_STM32F05X_PINMAP_H /**************************************************************************** * Included Files @@ -119,4 +119,4 @@ #define GPIO_I2C2_SCL_0 (GPIO_ALT | GPIO_AF1 | GPIO_OPENDRAIN | GPIO_PORTB | GPIO_PIN10) #define GPIO_I2C2_SDA_0 (GPIO_ALT | GPIO_AF1 | GPIO_OPENDRAIN | GPIO_PORTB | GPIO_PIN11) -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F05X_PINMAP_H */ +#endif /* __ARCH_ARM_SRC_STM32F0_HARDWARE_STM32F05X_PINMAP_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32f05xf07xf09x_memorymap.h b/arch/arm/src/stm32f0/hardware/stm32f05xf07xf09x_memorymap.h similarity index 96% rename from arch/arm/src/stm32f0l0g0/hardware/stm32f05xf07xf09x_memorymap.h rename to arch/arm/src/stm32f0/hardware/stm32f05xf07xf09x_memorymap.h index 384e67bdeeaba..b8fa02c00a129 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32f05xf07xf09x_memorymap.h +++ b/arch/arm/src/stm32f0/hardware/stm32f05xf07xf09x_memorymap.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32f05xf07xf09x_memorymap.h + * arch/arm/src/stm32f0/hardware/stm32f05xf07xf09x_memorymap.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F05XF07XF09X_MEMORYMAP_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F05XF07XF09X_MEMORYMAP_H +#ifndef __ARCH_ARM_SRC_STM32F0_HARDWARE_STM32F05XF07XF09X_MEMORYMAP_H +#define __ARCH_ARM_SRC_STM32F0_HARDWARE_STM32F05XF07XF09X_MEMORYMAP_H /**************************************************************************** * Pre-processor Definitions @@ -145,4 +145,4 @@ #define STM32_SYSMEM_UID 0x1ffff7ac /* The 96-bit unique device identifier */ -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F05XF07XF09X_MEMORYMAP_H */ +#endif /* __ARCH_ARM_SRC_STM32F0_HARDWARE_STM32F05XF07XF09X_MEMORYMAP_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32f07x_pinmap.h b/arch/arm/src/stm32f0/hardware/stm32f07x_pinmap.h similarity index 98% rename from arch/arm/src/stm32f0l0g0/hardware/stm32f07x_pinmap.h rename to arch/arm/src/stm32f0/hardware/stm32f07x_pinmap.h index 2210e67af117a..24255d24048c4 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32f07x_pinmap.h +++ b/arch/arm/src/stm32f0/hardware/stm32f07x_pinmap.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32f07x_pinmap.h + * arch/arm/src/stm32f0/hardware/stm32f07x_pinmap.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F07X_PINMAP_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F07X_PINMAP_H +#ifndef __ARCH_ARM_SRC_STM32F0_HARDWARE_STM32F07X_PINMAP_H +#define __ARCH_ARM_SRC_STM32F0_HARDWARE_STM32F07X_PINMAP_H /**************************************************************************** * Included Files @@ -385,4 +385,4 @@ #define GPIO_USB_NOE_0 (GPIO_ALT | GPIO_AF2 | GPIO_PORTA | GPIO_PIN13) -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F07X_PINMAP_H */ +#endif /* __ARCH_ARM_SRC_STM32F0_HARDWARE_STM32F07X_PINMAP_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32f09x_pinmap.h b/arch/arm/src/stm32f0/hardware/stm32f09x_pinmap.h similarity index 99% rename from arch/arm/src/stm32f0l0g0/hardware/stm32f09x_pinmap.h rename to arch/arm/src/stm32f0/hardware/stm32f09x_pinmap.h index b2b2b44cd9b17..bfeb238a732a5 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32f09x_pinmap.h +++ b/arch/arm/src/stm32f0/hardware/stm32f09x_pinmap.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32f09x_pinmap.h + * arch/arm/src/stm32f0/hardware/stm32f09x_pinmap.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F09X_PINMAP_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F09X_PINMAP_H +#ifndef __ARCH_ARM_SRC_STM32F0_HARDWARE_STM32F09X_PINMAP_H +#define __ARCH_ARM_SRC_STM32F0_HARDWARE_STM32F09X_PINMAP_H /**************************************************************************** * Included Files @@ -414,4 +414,4 @@ #define GPIO_USART8_RX_3 (GPIO_ALT | GPIO_AF0 | GPIO_PORTD | GPIO_PIN13) #define GPIO_USART8_CK_RST_0 (GPIO_ALT | GPIO_AF2 | GPIO_PORTD | GPIO_PIN14) -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F09X_PINMAP_H */ +#endif /* __ARCH_ARM_SRC_STM32F0_HARDWARE_STM32F09X_PINMAP_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32f0_exti.h b/arch/arm/src/stm32f0/hardware/stm32f0_exti.h similarity index 96% rename from arch/arm/src/stm32f0l0g0/hardware/stm32f0_exti.h rename to arch/arm/src/stm32f0/hardware/stm32f0_exti.h index ec2f58f8a186c..d006ddb3ff11f 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32f0_exti.h +++ b/arch/arm/src/stm32f0/hardware/stm32f0_exti.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32f0_exti.h + * arch/arm/src/stm32f0/hardware/stm32f0_exti.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F0_EXTI_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F0_EXTI_H +#ifndef __ARCH_ARM_SRC_STM32F0_HARDWARE_STM32F0_EXTI_H +#define __ARCH_ARM_SRC_STM32F0_HARDWARE_STM32F0_EXTI_H /**************************************************************************** * Included Files @@ -114,4 +114,4 @@ #define EXTI_PR_SHIFT (0) /* Bits 0-X: Pending bit for all lines */ #define EXTI_PR_MASK STM32_EXTI_MASK -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F0_EXTI_H */ +#endif /* __ARCH_ARM_SRC_STM32F0_HARDWARE_STM32F0_EXTI_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32f0_flash.h b/arch/arm/src/stm32f0/hardware/stm32f0_flash.h similarity index 95% rename from arch/arm/src/stm32f0l0g0/hardware/stm32f0_flash.h rename to arch/arm/src/stm32f0/hardware/stm32f0_flash.h index fde24890c4f05..46c87416a0afa 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32f0_flash.h +++ b/arch/arm/src/stm32f0/hardware/stm32f0_flash.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32f0_flash.h + * arch/arm/src/stm32f0/hardware/stm32f0_flash.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F0_FLASH_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F0_FLASH_H +#ifndef __ARCH_ARM_SRC_STM32F0_HARDWARE_STM32F0_FLASH_H +#define __ARCH_ARM_SRC_STM32F0_HARDWARE_STM32F0_FLASH_H /**************************************************************************** * Included Files @@ -94,4 +94,4 @@ #define FLASH_OBR_ /* To be provided */ -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F0_FLASH_H */ +#endif /* __ARCH_ARM_SRC_STM32F0_HARDWARE_STM32F0_FLASH_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32f0_pwr.h b/arch/arm/src/stm32f0/hardware/stm32f0_pwr.h similarity index 94% rename from arch/arm/src/stm32f0l0g0/hardware/stm32f0_pwr.h rename to arch/arm/src/stm32f0/hardware/stm32f0_pwr.h index 64a693f752288..9b981257bc55f 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32f0_pwr.h +++ b/arch/arm/src/stm32f0/hardware/stm32f0_pwr.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32f0_pwr.h + * arch/arm/src/stm32f0/hardware/stm32f0_pwr.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F0_PWR_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F0_PWR_H +#ifndef __ARCH_ARM_SRC_STM32F0_HARDWARE_STM32F0_PWR_H +#define __ARCH_ARM_SRC_STM32F0_HARDWARE_STM32F0_PWR_H /**************************************************************************** * Included Files @@ -85,4 +85,4 @@ #define PWR_CSR_EWUP7 (1 << 14) /* Bit 14: Enable WKUP7 pin */ #define PWR_CSR_EWUP8 (1 << 15) /* Bit 15: Enable WKUP8 pin */ -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F0_PWR_H */ +#endif /* __ARCH_ARM_SRC_STM32F0_HARDWARE_STM32F0_PWR_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32f0_rcc.h b/arch/arm/src/stm32f0/hardware/stm32f0_rcc.h similarity index 99% rename from arch/arm/src/stm32f0l0g0/hardware/stm32f0_rcc.h rename to arch/arm/src/stm32f0/hardware/stm32f0_rcc.h index 63c213b1531e5..3bd0a3dab1763 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32f0_rcc.h +++ b/arch/arm/src/stm32f0/hardware/stm32f0_rcc.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32f0_rcc.h + * arch/arm/src/stm32f0/hardware/stm32f0_rcc.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F0_RCC_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F0_RCC_H +#ifndef __ARCH_ARM_SRC_STM32F0_HARDWARE_STM32F0_RCC_H +#define __ARCH_ARM_SRC_STM32F0_HARDWARE_STM32F0_RCC_H /**************************************************************************** * Pre-processor Definitions @@ -391,4 +391,4 @@ #define RCC_CR2_HSI48CAL_SHIFT (24) /* Bits 24-31: HSI48 factory clock calibration */ #define RCC_CR2_HSI48CAL_MASK (0xff << RCC_CR2_HSI48CAL_SHIFT) -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F0_RCC_H */ +#endif /* __ARCH_ARM_SRC_STM32F0_HARDWARE_STM32F0_RCC_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32f0_syscfg.h b/arch/arm/src/stm32f0/hardware/stm32f0_syscfg.h similarity index 99% rename from arch/arm/src/stm32f0l0g0/hardware/stm32f0_syscfg.h rename to arch/arm/src/stm32f0/hardware/stm32f0_syscfg.h index 63f38bf07caed..f7822582a674a 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32f0_syscfg.h +++ b/arch/arm/src/stm32f0/hardware/stm32f0_syscfg.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32f0_syscfg.h + * arch/arm/src/stm32f0/hardware/stm32f0_syscfg.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F0_SYSCFG_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F0_SYSCFG_H +#ifndef __ARCH_ARM_SRC_STM32F0_HARDWARE_STM32F0_SYSCFG_H +#define __ARCH_ARM_SRC_STM32F0_HARDWARE_STM32F0_SYSCFG_H /**************************************************************************** * Included Files @@ -378,4 +378,4 @@ #define SYSCFG_ITLINE30_CEC (1 << 0) /* Bit 0: CEC interrupt request pending, combined with EXTI line 27 */ #define SYSCFG_ITLINE30_CAN (1 << 1) /* Bit 1: CAN interrupt request pending */ -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F0_SYSCFG_H */ +#endif /* __ARCH_ARM_SRC_STM32F0_HARDWARE_STM32F0_SYSCFG_H */ diff --git a/arch/arm/src/stm32f0/stm32.h b/arch/arm/src/stm32f0/stm32.h new file mode 100644 index 0000000000000..fabdd48a6255b --- /dev/null +++ b/arch/arm/src/stm32f0/stm32.h @@ -0,0 +1,54 @@ +/**************************************************************************** + * arch/arm/src/stm32f0/stm32.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32F0_STM32_H +#define __ARCH_ARM_SRC_STM32F0_STM32_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include +#include + +#include "arm_internal.h" + +/* Peripherals **************************************************************/ + +#include "chip.h" +#include "stm32_dma.h" +#include "stm32_gpio.h" +#include "stm32_i2c.h" +#include "stm32_pwr.h" +#include "stm32_rcc.h" +#include "stm32_spi.h" +#include "stm32_uart.h" +#include "stm32_lowputc.h" +#include "stm32_adc.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#endif /* __ARCH_ARM_SRC_STM32F0_STM32_H */ diff --git a/arch/arm/src/stm32f0/stm32_rcc.c b/arch/arm/src/stm32f0/stm32_rcc.c new file mode 100644 index 0000000000000..d343b49ad173e --- /dev/null +++ b/arch/arm/src/stm32f0/stm32_rcc.c @@ -0,0 +1,220 @@ +/**************************************************************************** + * arch/arm/src/stm32f0/stm32_rcc.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include + +#include "arm_internal.h" +#include "hardware/stm32_flash.h" +#include "stm32_rcc.h" +#include "stm32_hsi48_m0_v1.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifdef CONFIG_STM32_RNG +# ifndef STM32_USE_CLK48 +# error RNG requires CLK48 enabled +# endif +#endif + +#ifdef CONFIG_STM32_USB +# ifndef STM32_USE_CLK48 +# error USB requires CLK48 enabled +# endif +#endif + +static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1, + "Configure BOARD_LOOPSPERMSEC to non-default value."); + +/* Allow up to 100 milliseconds for the high speed clock to become ready. + * that is a very long delay, but if the clock does not become ready we are + * hosed anyway. + */ + +#define HSERDY_TIMEOUT (100 * CONFIG_BOARD_LOOPSPERMSEC) + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/* Include chip-specific clocking initialization logic */ + +#include "stm32f0_rcc.c" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: rcc_resetbkp + * + * Description: + * The RTC needs to reset the Backup Domain to change RTCSEL and resetting + * the Backup Domain renders to disabling the LSE as consequence. + * In order to avoid resetting the Backup Domain when we already configured + * LSE we will reset the Backup Domain early (here). + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +#if defined(CONFIG_STM32_RTC) && defined(CONFIG_STM32_PWR) +static inline void rcc_resetbkp(void) +{ + uint32_t regval; + + /* Check if the RTC is already configured */ + + stm32_pwr_initbkp(false); + + regval = getreg32(RTC_MAGIC_REG); + if (regval != RTC_MAGIC && regval != RTC_MAGIC_TIME_SET) + { + stm32_pwr_enablebkp(true); + + /* We might be changing RTCSEL - to ensure such changes work, we must + * reset the backup domain (having backed up the RTC_MAGIC token) + */ + + modifyreg32(STM32_RCC_BDCR, 0, RCC_BDCR_BDRST); + modifyreg32(STM32_RCC_BDCR, RCC_BDCR_BDRST, 0); + + stm32_pwr_enablebkp(false); + } +} +#else +# define rcc_resetbkp() +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_clockconfig + * + * Description: + * Called to establish the clock settings based on the values in board.h. + * This function (by default) will reset most everything, enable the PLL, + * and enable peripheral clocking for all peripherals enabled in the NuttX + * configuration file. + * + * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then + * clocking will be enabled by an externally provided, board-specific + * function called stm32_board_clockconfig(). + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void stm32_clockconfig(void) +{ + /* Make sure that we are starting in the reset state */ + + rcc_reset(); + + /* Reset backup domain if appropriate */ + + rcc_resetbkp(); + +#if defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) + /* Invoke Board Custom Clock Configuration */ + + stm32_board_clockconfig(); + +#else + /* Invoke standard, fixed clock configuration based on definitions + * in board.h + */ + + stm32_stdclockconfig(); + +#endif + + /* Enable peripheral clocking */ + + rcc_enableperipherals(); +} + +/**************************************************************************** + * Name: stm32_clockenable + * + * Description: + * Re-enable the clock and restore the clock settings based on settings in + * board.h. This function is only available to support low-power modes of + * operation: When re-awakening from deep-sleep modes, it is necessary to + * re-enable/re-start the PLL + * + * This functional performs a subset of the operations performed by + * stm32_clockconfig(): It does not reset any devices, and it does not + * reset the currently enabled peripheral clocks. + * + * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then + * clocking will be enabled by an externally provided, board-specific + * function called stm32_board_clockconfig(). + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_PM +void stm32_clockenable(void) +{ +#if defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) + /* Invoke Board Custom Clock Configuration */ + + stm32_board_clockconfig(); + +#else + /* Invoke standard, fixed clock configuration based on definitions + * in board.h + */ + + stm32_stdclockconfig(); + +#endif +} +#endif diff --git a/arch/arm/src/stm32f0l0g0/stm32f0_rcc.c b/arch/arm/src/stm32f0/stm32f0_rcc.c similarity index 88% rename from arch/arm/src/stm32f0l0g0/stm32f0_rcc.c rename to arch/arm/src/stm32f0/stm32f0_rcc.c index ff387fbe10a4a..b5106208ca9e2 100644 --- a/arch/arm/src/stm32f0l0g0/stm32f0_rcc.c +++ b/arch/arm/src/stm32f0/stm32f0_rcc.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32f0_rcc.c + * arch/arm/src/stm32f0/stm32f0_rcc.c * * SPDX-License-Identifier: Apache-2.0 * @@ -44,7 +44,7 @@ /* Determine if board wants to use HSI48 as 48 MHz oscillator. */ -#if defined(CONFIG_STM32F0L0G0_HAVE_HSI48) && defined(STM32_USE_CLK48) +#if defined(CONFIG_STM32_HAVE_HSI48) && defined(STM32_USE_CLK48) # if STM32_CLK48_SEL == RCC_CFGR3_CLK48_HSI48 # define STM32_USE_HSI48 # endif @@ -107,25 +107,25 @@ static inline void rcc_enableahb(void) regval = getreg32(STM32_RCC_AHBENR); -#ifdef CONFIG_STM32F0L0G0_DMA1 +#ifdef CONFIG_STM32_DMA1 /* DMA 1 clock enable */ regval |= RCC_AHBENR_DMA1EN; #endif -#ifdef CONFIG_STM32F0L0G0_DMA2 +#ifdef CONFIG_STM32_DMA2 /* DMA 2 clock enable */ regval |= RCC_AHBENR_DMA2EN; #endif -#ifdef CONFIG_STM32F0L0G0_CRC +#ifdef CONFIG_STM32_CRC /* CRC clock enable */ regval |= RCC_AHBENR_CRCEN; #endif -#ifdef CONFIG_STM32F0L0G0_TSC +#ifdef CONFIG_STM32_TSC /* TSC clock enable */ regval |= RCC_AHBENR_TSCEN; @@ -152,121 +152,121 @@ static inline void rcc_enableapb1(void) regval = getreg32(STM32_RCC_APB1ENR); -#ifdef CONFIG_STM32F0L0G0_TIM2 +#ifdef CONFIG_STM32_TIM2 /* Timer 2 clock enable */ regval |= RCC_APB1ENR_TIM2EN; #endif -#ifdef CONFIG_STM32F0L0G0_TIM3 +#ifdef CONFIG_STM32_TIM3 /* Timer 3 clock enable */ regval |= RCC_APB1ENR_TIM3EN; #endif -#ifdef CONFIG_STM32F0L0G0_TIM4 +#ifdef CONFIG_STM32_TIM4 /* Timer 4 clock enable */ regval |= RCC_APB1ENR_TIM4EN; #endif -#ifdef CONFIG_STM32F0L0G0_TIM6 +#ifdef CONFIG_STM32_TIM6 /* Timer 6 clock enable */ regval |= RCC_APB1ENR_TIM6EN; #endif -#ifdef CONFIG_STM32F0L0G0_TIM7 +#ifdef CONFIG_STM32_TIM7 /* Timer 7 clock enable */ regval |= RCC_APB1ENR_TIM7EN; #endif -#ifdef CONFIG_STM32F0L0G0_TIM14 +#ifdef CONFIG_STM32_TIM14 /* Timer 14 clock enable */ regval |= RCC_APB1ENR_TIM14EN; #endif -#ifdef CONFIG_STM32F0L0G0_WWDG +#ifdef CONFIG_STM32_WWDG /* Window Watchdog clock enable */ regval |= RCC_APB1ENR_WWDGEN; #endif -#ifdef CONFIG_STM32F0L0G0_SPI2 +#ifdef CONFIG_STM32_SPI2 /* SPI 2 clock enable */ regval |= RCC_APB1ENR_SPI2EN; #endif -#ifdef CONFIG_STM32F0L0G0_USART2 +#ifdef CONFIG_STM32_USART2 /* USART 2 clock enable */ regval |= RCC_APB1ENR_USART2EN; #endif -#ifdef CONFIG_STM32F0L0G0_USART3 +#ifdef CONFIG_STM32_USART3 /* USART 3 clock enable */ regval |= RCC_APB1ENR_USART3EN; #endif -#ifdef CONFIG_STM32F0L0G0_USART4 +#ifdef CONFIG_STM32_USART4 /* USART 4 clock enable */ regval |= RCC_APB1ENR_USART4EN; #endif -#ifdef CONFIG_STM32F0L0G0_USART5 +#ifdef CONFIG_STM32_USART5 /* USART 5 clock enable */ regval |= RCC_APB1ENR_USART5EN; #endif -#ifdef CONFIG_STM32F0L0G0_I2C1 +#ifdef CONFIG_STM32_I2C1 /* I2C 1 clock enable */ regval |= RCC_APB1ENR_I2C1EN; #endif -#ifdef CONFIG_STM32F0L0G0_I2C2 +#ifdef CONFIG_STM32_I2C2 /* I2C 2 clock enable */ regval |= RCC_APB1ENR_I2C2EN; #endif -#ifdef CONFIG_STM32F0L0G0_USB +#ifdef CONFIG_STM32_USB /* USB clock enable */ regval |= RCC_APB1ENR_USBEN; #endif -#ifdef CONFIG_STM32F0L0G0_CAN1 +#ifdef CONFIG_STM32_CAN1 /* CAN1 clock enable */ regval |= RCC_APB1ENR_CAN1EN; #endif -#ifdef CONFIG_STM32F0L0G0_CRS +#ifdef CONFIG_STM32_CRS /* Clock recovery system clock enable */ regval |= RCC_APB1ENR_CRSEN; #endif -#ifdef CONFIG_STM32F0L0G0_PWR +#ifdef CONFIG_STM32_PWR /* Power interface clock enable */ regval |= RCC_APB1ENR_PWREN; #endif -#ifdef CONFIG_STM32F0L0G0_DAC1 +#ifdef CONFIG_STM32_DAC1 /* DAC 1 interface clock enable */ regval |= RCC_APB1ENR_DAC1EN; #endif -#ifdef CONFIG_STM32F0L0G0_CEC +#ifdef CONFIG_STM32_CEC /* CEC interface clock enable */ regval |= RCC_APB1ENR_CECEN; @@ -293,67 +293,67 @@ static inline void rcc_enableapb2(void) regval = getreg32(STM32_RCC_APB2ENR); -#ifdef CONFIG_STM32F0L0G0_SYSCFG +#ifdef CONFIG_STM32_SYSCFG /* SYSCFG clock */ regval |= RCC_APB2ENR_SYSCFGCOMPEN; #endif -#ifdef CONFIG_STM32F0L0G0_USART6 +#ifdef CONFIG_STM32_USART6 /* USART 6 clock enable */ regval |= RCC_APB2ENR_USART6EN; #endif -#ifdef CONFIG_STM32F0L0G0_USART7 +#ifdef CONFIG_STM32_USART7 /* USART 7 clock enable */ regval |= RCC_APB2ENR_USART7EN; #endif -#ifdef CONFIG_STM32F0L0G0_USART8 +#ifdef CONFIG_STM32_USART8 /* USART 8 clock enable */ regval |= RCC_APB2ENR_USART8EN; #endif -#ifdef CONFIG_STM32F0L0G0_ADC1 +#ifdef CONFIG_STM32_ADC1 /* ADC 1 clock enable */ regval |= RCC_APB2ENR_ADC1EN; #endif -#ifdef CONFIG_STM32F0L0G0_TIM1 +#ifdef CONFIG_STM32_TIM1 /* Timer 1 clock enable */ regval |= RCC_APB2ENR_TIM1EN; #endif -#ifdef CONFIG_STM32F0L0G0_SPI1 +#ifdef CONFIG_STM32_SPI1 /* SPI 1 clock enable */ regval |= RCC_APB2ENR_SPI1EN; #endif -#ifdef CONFIG_STM32F0L0G0_USART1 +#ifdef CONFIG_STM32_USART1 /* USART1 clock enable */ regval |= RCC_APB2ENR_USART1EN; #endif -#ifdef CONFIG_STM32F0L0G0_TIM15 +#ifdef CONFIG_STM32_TIM15 /* Timer 15 clock enable */ regval |= RCC_APB2ENR_TIM15EN; #endif -#ifdef CONFIG_STM32F0L0G0_TIM16 +#ifdef CONFIG_STM32_TIM16 /* Timer 16 clock enable */ regval |= RCC_APB2ENR_TIM16EN; #endif -#ifdef CONFIG_STM32F0L0G0_TIM17 +#ifdef CONFIG_STM32_TIM17 /* Timer 17 clock enable */ regval |= RCC_APB2ENR_TIM17EN; @@ -379,7 +379,7 @@ static inline void rcc_enableapb2(void) * ****************************************************************************/ -#ifndef CONFIG_ARCH_BOARD_STM32F0G0L0_CUSTOM_CLOCKCONFIG +#ifndef CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG static void stm32_stdclockconfig(void) { uint32_t regval; diff --git a/arch/arm/src/stm32f0l0g0/CMakeLists.txt b/arch/arm/src/stm32f0l0g0/CMakeLists.txt deleted file mode 100644 index a60ec1966a7ec..0000000000000 --- a/arch/arm/src/stm32f0l0g0/CMakeLists.txt +++ /dev/null @@ -1,135 +0,0 @@ -# ############################################################################## -# arch/arm/src/stm32f0l0g0/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -set(SRCS) - -list( - APPEND - SRCS - stm32_start.c - stm32_gpio.c - stm32_exti_gpio.c - stm32_irq.c - stm32_lowputc.c - stm32_serial.c - stm32_lsi.c - stm32_rcc.c - stm32_uid.c) - -if(CONFIG_STM32F0L0G0_RTC_LSECLOCK OR CONFIG_LCD_LSECLOCK) - list(APPEND SRCS stm32_lse.c) -endif() - -if(CONFIG_STM32F0L0G0_DMA) - list(APPEND SRCS stm32_dma.c) -endif() - -if(CONFIG_STM32F0L0G0_PWR) - list(APPEND SRCS stm32_pwr.c) -endif() - -if(NOT CONFIG_ARCH_IDLE_CUSTOM) - list(APPEND SRCS stm32_idle.c) -endif() - -if(NOT CONFIG_SCHED_TICKLESS) - list(APPEND SRCS stm32_timerisr.c) -endif() - -if(CONFIG_BUILD_PROTECTED) - list(APPEND SRCS stm32_userspace.c) -endif() - -if(CONFIG_STM32F0L0G0_PROGMEM) - list(APPEND SRCS stm32_flash.c) -endif() - -if(CONFIG_STM32F0L0G0_GPIOIRQ) - list(APPEND SRCS stm32_gpioint.c) -endif() - -if(CONFIG_ARCH_IRQPRIO) - list(APPEND SRCS stm32_irqprio.c) -endif() - -if(CONFIG_STM32F0L0G0_HAVE_HSI48) - list(APPEND SRCS stm32_hsi48.c) -endif() - -if(CONFIG_STM32F0L0G0_USB) - list(APPEND SRCS stm32_usbdev.c) -endif() - -if(CONFIG_STM32F0L0G0_I2C) - list(APPEND SRCS stm32_i2c.c) -endif() - -if(CONFIG_STM32F0L0G0_SPI) - list(APPEND SRCS stm32_spi.c) -endif() - -if(CONFIG_STM32F0L0G0_PWM) - list(APPEND SRCS stm32_pwm.c) -endif() - -if(CONFIG_PULSECOUNT AND CONFIG_STM32F0L0G0_TIM1_PULSECOUNT) - list(APPEND SRCS stm32_pulsecount.c) -endif() - -if(CONFIG_STM32F0L0G0_ADC) - list(APPEND SRCS stm32_adc.c) -endif() - -if(CONFIG_STM32F0L0G0_AES) - list(APPEND SRCS stm32_aes.c) -endif() - -if(CONFIG_STM32F0L0G0_RNG) - list(APPEND SRCS stm32_rng.c) -endif() - -if(CONFIG_STM32F0L0G0_TIM) - list(APPEND SRCS stm32_tim.c stm32_tim_lowerhalf.c) -endif() - -if(CONFIG_STM32F0L0G0_IWDG) - list(APPEND SRCS stm32_iwdg.c) -endif() - -if(CONFIG_STM32F0L0G0_WWDG) - list(APPEND SRCS stm32_wwdg.c) -endif() - -if(CONFIG_STM32F0L0G0_FDCAN) - if(CONFIG_STM32F0L0G0_FDCAN_CHARDRIVER) - list(APPEND SRCS stm32_fdcan.c) - endif() - if(CONFIG_STM32F0L0G0_FDCAN_SOCKET) - list(APPEND SRCS stm32_fdcan_sock.c) - endif() -endif() - -if(CONFIG_SENSORS_QENCODER) - list(APPEND SRCS stm32_qencoder.c) -endif() - -target_sources(arch PRIVATE ${SRCS}) diff --git a/arch/arm/src/stm32f0l0g0/Kconfig b/arch/arm/src/stm32f0l0g0/Kconfig deleted file mode 100644 index 31cddad994e15..0000000000000 --- a/arch/arm/src/stm32f0l0g0/Kconfig +++ /dev/null @@ -1,4012 +0,0 @@ -# -# For a description of the syntax of this configuration file, -# see the file kconfig-language.txt in the NuttX tools repository. -# - -comment "STM32F0/L0/G0 Configuration Options" - -choice - prompt "ST STM32F0/L0/G0 Chip Selection" - default ARCH_CHIP_STM32F051R8 if ARCH_CHIP_STM32F0 - default ARCH_CHIP_STM32L073RZ if ARCH_CHIP_STM32L0 - default ARCH_CHIP_STM32G071RB if ARCH_CHIP_STM32G0 - default ARCH_CHIP_STM32C071RB if ARCH_CHIP_STM32C0 - depends on ARCH_CHIP_STM32F0 || ARCH_CHIP_STM32L0 || ARCH_CHIP_STM32G0 || ARCH_CHIP_STM32C0 - -config ARCH_CHIP_STM32F030C6 - bool "STM32F030C6" - select STM32F0L0G0_STM32F03X - select STM32F0L0G0_VALUELINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F030C8 - bool "STM32F030C8" - select STM32F0L0G0_STM32F03X - select STM32F0L0G0_VALUELINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F030CC - bool "STM32F030CC" - select STM32F0L0G0_STM32F03X - select STM32F0L0G0_VALUELINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F030F4 - bool "STM32F030F4" - select STM32F0L0G0_STM32F03X - select STM32F0L0G0_VALUELINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F030K6 - bool "STM32F030K6" - select STM32F0L0G0_STM32F03X - select STM32F0L0G0_VALUELINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F030R8 - bool "STM32F030R8" - select STM32F0L0G0_STM32F03X - select STM32F0L0G0_VALUELINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F030RC - bool "STM32F030RC" - select STM32F0L0G0_STM32F03X - select STM32F0L0G0_VALUELINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F031C4 - bool "STM32F031C4" - select STM32F0L0G0_STM32F03X - select STM32F0L0G0_ACCESSLINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F031C6 - bool "STM32F031C6" - select STM32F0L0G0_STM32F03X - select STM32F0L0G0_ACCESSLINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F031E6 - bool "STM32F031E6" - select STM32F0L0G0_STM32F03X - select STM32F0L0G0_ACCESSLINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F031F4 - bool "STM32F031F4" - select STM32F0L0G0_STM32F03X - select STM32F0L0G0_ACCESSLINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F031F6 - bool "STM32F031F6" - select STM32F0L0G0_STM32F03X - select STM32F0L0G0_ACCESSLINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F031G4 - bool "STM32F031G4" - select STM32F0L0G0_STM32F03X - select STM32F0L0G0_ACCESSLINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F031G6 - bool "STM32F031G6" - select STM32F0L0G0_STM32F03X - select STM32F0L0G0_ACCESSLINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F031K4 - bool "STM32F031K4" - select STM32F0L0G0_STM32F03X - select STM32F0L0G0_ACCESSLINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F031K6 - bool "STM32F031K6" - select STM32F0L0G0_STM32F03X - select STM32F0L0G0_ACCESSLINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F038C6 - bool "STM32F038C6" - select STM32F0L0G0_STM32F03X - select STM32F0L0G0_LOWVOLTLINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F038E6 - bool "STM32F038E6" - select STM32F0L0G0_STM32F03X - select STM32F0L0G0_LOWVOLTLINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F038F6 - bool "STM32F038F6" - select STM32F0L0G0_STM32F03X - select STM32F0L0G0_LOWVOLTLINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F038G6 - bool "STM32F038G6" - select STM32F0L0G0_STM32F03X - select STM32F0L0G0_LOWVOLTLINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F038K6 - bool "STM32F038K6" - select STM32F0L0G0_STM32F03X - select STM32F0L0G0_LOWVOLTLINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F042C4 - bool "STM32F042C4" - select STM32F0L0G0_STM32F04X - select STM32F0L0G0_USBLINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F042C6 - bool "STM32F042C6" - select STM32F0L0G0_STM32F04X - select STM32F0L0G0_USBLINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F042F4 - bool "STM32F042F4" - select STM32F0L0G0_STM32F04X - select STM32F0L0G0_USBLINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F042F6 - bool "STM32F042F6" - select STM32F0L0G0_STM32F04X - select STM32F0L0G0_USBLINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F042G4 - bool "STM32F042G4" - select STM32F0L0G0_STM32F04X - select STM32F0L0G0_USBLINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F042G6 - bool "STM32F042G6" - select STM32F0L0G0_STM32F04X - select STM32F0L0G0_USBLINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F042K4 - bool "STM32F042K4" - select STM32F0L0G0_STM32F04X - select STM32F0L0G0_USBLINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F042K6 - bool "STM32F042K6" - select STM32F0L0G0_STM32F04X - select STM32F0L0G0_USBLINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F042T6 - bool "STM32F042T6" - select STM32F0L0G0_STM32F04X - select STM32F0L0G0_USBLINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F048C6 - bool "STM32F048C6" - select STM32F0L0G0_STM32F04X - select STM32F0L0G0_LOWVOLTLINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F048G6 - bool "STM32F048G6" - select STM32F0L0G0_STM32F04X - select STM32F0L0G0_LOWVOLTLINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F048T6 - bool "STM32F048T6" - select STM32F0L0G0_STM32F04X - select STM32F0L0G0_LOWVOLTLINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F051C4 - bool "STM32F051C4" - select STM32F0L0G0_STM32F05X - select STM32F0L0G0_ACCESSLINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F051C6 - bool "STM32F051C6" - select STM32F0L0G0_STM32F05X - select STM32F0L0G0_ACCESSLINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F051C8 - bool "STM32F051C8" - select STM32F0L0G0_STM32F05X - select STM32F0L0G0_ACCESSLINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F051K4 - bool "STM32F051K4" - select STM32F0L0G0_STM32F05X - select STM32F0L0G0_ACCESSLINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F051K6 - bool "STM32F051K6" - select STM32F0L0G0_STM32F05X - select STM32F0L0G0_ACCESSLINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F051K8 - bool "STM32F051K8" - select STM32F0L0G0_STM32F05X - select STM32F0L0G0_ACCESSLINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F051R4 - bool "STM32F051R4" - select STM32F0L0G0_STM32F05X - select STM32F0L0G0_ACCESSLINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F051R6 - bool "STM32F051R6" - select STM32F0L0G0_STM32F05X - select STM32F0L0G0_ACCESSLINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F051R8 - bool "STM32F051R8" - select STM32F0L0G0_STM32F05X - select STM32F0L0G0_ACCESSLINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F051T8 - bool "STM32F051T8" - select STM32F0L0G0_STM32F05X - select STM32F0L0G0_ACCESSLINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F058C8 - bool "STM32F058C8" - select STM32F0L0G0_STM32F05X - select STM32F0L0G0_LOWVOLTLINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F058R8 - bool "STM32F058R8" - select STM32F0L0G0_STM32F05X - select STM32F0L0G0_LOWVOLTLINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F058T8 - bool "STM32F058T8" - select STM32F0L0G0_STM32F05X - select STM32F0L0G0_LOWVOLTLINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F070C6 - bool "STM32F070C6" - select STM32F0L0G0_STM32F07X - select STM32F0L0G0_VALUELINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F070CB - bool "STM32F070CB" - select STM32F0L0G0_STM32F07X - select STM32F0L0G0_VALUELINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F070F6 - bool "STM32F070F6" - select STM32F0L0G0_STM32F07X - select STM32F0L0G0_VALUELINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F070RB - bool "STM32F070RB" - select STM32F0L0G0_STM32F07X - select STM32F0L0G0_VALUELINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F071C8 - bool "STM32F071C8" - select STM32F0L0G0_STM32F07X - select STM32F0L0G0_ACCESSLINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F071CB - bool "STM32F071CB" - select STM32F0L0G0_STM32F07X - select STM32F0L0G0_ACCESSLINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F071RB - bool "STM32F071RB" - select STM32F0L0G0_STM32F07X - select STM32F0L0G0_ACCESSLINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F071V8 - bool "STM32F071V8" - select STM32F0L0G0_STM32F07X - select STM32F0L0G0_ACCESSLINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F071VB - bool "STM32F071VB" - select STM32F0L0G0_STM32F07X - select STM32F0L0G0_ACCESSLINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F072C8 - bool "STM32F072C8" - select STM32F0L0G0_STM32F07X - select STM32F0L0G0_USBLINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F072CB - bool "STM32F072CB" - select STM32F0L0G0_STM32F07X - select STM32F0L0G0_USBLINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F072R8 - bool "STM32F072R8" - select STM32F0L0G0_STM32F07X - select STM32F0L0G0_USBLINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F072RB - bool "STM32F072RB" - select STM32F0L0G0_STM32F07X - select STM32F0L0G0_USBLINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F072V8 - bool "STM32F072V8" - select STM32F0L0G0_STM32F07X - select STM32F0L0G0_USBLINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F072VB - bool "STM32F072VB" - select STM32F0L0G0_STM32F07X - select STM32F0L0G0_USBLINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F078CB - bool "STM32F078CB" - select STM32F0L0G0_STM32F07X - select STM32F0L0G0_LOWVOLTLINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F078RB - bool "STM32F078RB" - select STM32F0L0G0_STM32F07X - select STM32F0L0G0_LOWVOLTLINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F078VB - bool "STM32F078VB" - select STM32F0L0G0_STM32F07X - select STM32F0L0G0_LOWVOLTLINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F091CB - bool "STM32F091CB" - select STM32F0L0G0_STM32F09X - select STM32F0L0G0_ACCESSLINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F091CC - bool "STM32F091CC" - select STM32F0L0G0_STM32F09X - select STM32F0L0G0_ACCESSLINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F091RB - bool "STM32F091RB" - select STM32F0L0G0_STM32F09X - select STM32F0L0G0_ACCESSLINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F091RC - bool "STM32F091RC" - select STM32F0L0G0_STM32F09X - select STM32F0L0G0_ACCESSLINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F091VB - bool "STM32F091VB" - select STM32F0L0G0_STM32F09X - select STM32F0L0G0_ACCESSLINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F091VC - bool "STM32F091VC" - select STM32F0L0G0_STM32F09X - select STM32F0L0G0_ACCESSLINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F098CC - bool "STM32F098CC" - select STM32F0L0G0_STM32F09X - select STM32F0L0G0_LOWVOLTLINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F098RC - bool "STM32F098RC" - select STM32F0L0G0_STM32F09X - select STM32F0L0G0_LOWVOLTLINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F098VC - bool "STM32F098VC" - select STM32F0L0G0_STM32F09X - select STM32F0L0G0_LOWVOLTLINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32G070CB - bool "STM32G070CB" - select STM32F0L0G0_STM32G070 - select STM32F0L0G0_FLASH_CONFIG_B - depends on ARCH_CHIP_STM32G0 - -config ARCH_CHIP_STM32G070KB - bool "STM32G070KB" - select STM32F0L0G0_STM32G070 - select STM32F0L0G0_FLASH_CONFIG_B - depends on ARCH_CHIP_STM32G0 - -config ARCH_CHIP_STM32G070RB - bool "STM32G070RB" - select STM32F0L0G0_STM32G070 - select STM32F0L0G0_FLASH_CONFIG_B - depends on ARCH_CHIP_STM32G0 - -config ARCH_CHIP_STM32G071EB - bool "STM32G071EB" - select STM32F0L0G0_STM32G071 - select STM32F0L0G0_FLASH_CONFIG_B - depends on ARCH_CHIP_STM32G0 - -config ARCH_CHIP_STM32G071G8 - bool "STM32G071G8" - select STM32F0L0G0_STM32G071 - select STM32F0L0G0_FLASH_CONFIG_8 - depends on ARCH_CHIP_STM32G0 - -config ARCH_CHIP_STM32G071GB - bool "STM32G071GB" - select STM32F0L0G0_STM32G071 - select STM32F0L0G0_FLASH_CONFIG_B - depends on ARCH_CHIP_STM32G0 - -config ARCH_CHIP_STM32G071G8XN - bool "STM32G071G8XN" - select STM32F0L0G0_STM32G071 - select STM32F0L0G0_FLASH_CONFIG_8 - depends on ARCH_CHIP_STM32G0 - -config ARCH_CHIP_STM32G071GBXN - bool "STM32G071GBXN" - select STM32F0L0G0_STM32G071 - select STM32F0L0G0_FLASH_CONFIG_B - depends on ARCH_CHIP_STM32G0 - -config ARCH_CHIP_STM32G071K8 - bool "STM32G071K8" - select STM32F0L0G0_STM32G071 - select STM32F0L0G0_FLASH_CONFIG_8 - depends on ARCH_CHIP_STM32G0 - -config ARCH_CHIP_STM32G071KB - bool "STM32G071KB" - select STM32F0L0G0_STM32G071 - select STM32F0L0G0_FLASH_CONFIG_B - depends on ARCH_CHIP_STM32G0 - -config ARCH_CHIP_STM32G071K8XN - bool "STM32G071K8XN" - select STM32F0L0G0_STM32G071 - select STM32F0L0G0_FLASH_CONFIG_8 - depends on ARCH_CHIP_STM32G0 - -config ARCH_CHIP_STM32G071KBXN - bool "STM32G071KBXN" - select STM32F0L0G0_STM32G071 - select STM32F0L0G0_FLASH_CONFIG_B - depends on ARCH_CHIP_STM32G0 - -config ARCH_CHIP_STM32G071C8 - bool "STM32G071C8" - select STM32F0L0G0_STM32G071 - select STM32F0L0G0_FLASH_CONFIG_8 - depends on ARCH_CHIP_STM32G0 - -config ARCH_CHIP_STM32G071CB - bool "STM32G071CB" - select STM32F0L0G0_STM32G071 - select STM32F0L0G0_FLASH_CONFIG_B - depends on ARCH_CHIP_STM32G0 - -config ARCH_CHIP_STM32G071R8 - bool "STM32G071R8" - select STM32F0L0G0_STM32G071 - select STM32F0L0G0_FLASH_CONFIG_8 - depends on ARCH_CHIP_STM32G0 - -config ARCH_CHIP_STM32G071RB - bool "STM32G071RB" - select STM32F0L0G0_STM32G071 - select STM32F0L0G0_FLASH_CONFIG_B - depends on ARCH_CHIP_STM32G0 - -config ARCH_CHIP_STM32G0B1KB - bool "STM32G0B1KB" - select STM32F0L0G0_STM32G0B1 - select STM32F0L0G0_FLASH_CONFIG_B - depends on ARCH_CHIP_STM32G0 - -config ARCH_CHIP_STM32G0B1CB - bool "STM32G0B1CB" - select STM32F0L0G0_STM32G0B1 - select STM32F0L0G0_FLASH_CONFIG_B - depends on ARCH_CHIP_STM32G0 - -config ARCH_CHIP_STM32G0B1RB - bool "STM32G0B1RB" - select STM32F0L0G0_STM32G0B1 - select STM32F0L0G0_FLASH_CONFIG_B - depends on ARCH_CHIP_STM32G0 - -config ARCH_CHIP_STM32G0B1MB - bool "STM32G0B1MB" - select STM32F0L0G0_STM32G0B1 - select STM32F0L0G0_FLASH_CONFIG_B - depends on ARCH_CHIP_STM32G0 - -config ARCH_CHIP_STM32G0B1VB - bool "STM32G0B1VB" - select STM32F0L0G0_STM32G0B1 - select STM32F0L0G0_FLASH_CONFIG_B - depends on ARCH_CHIP_STM32G0 - -config ARCH_CHIP_STM32G0B1KC - bool "STM32G0B1KC" - select STM32F0L0G0_STM32G0B1 - select STM32F0L0G0_FLASH_CONFIG_C - depends on ARCH_CHIP_STM32G0 - -config ARCH_CHIP_STM32G0B1CC - bool "STM32G0B1CC" - select STM32F0L0G0_STM32G0B1 - select STM32F0L0G0_FLASH_CONFIG_C - depends on ARCH_CHIP_STM32G0 - -config ARCH_CHIP_STM32G0B1RC - bool "STM32G0B1RC" - select STM32F0L0G0_STM32G0B1 - select STM32F0L0G0_FLASH_CONFIG_C - depends on ARCH_CHIP_STM32G0 - -config ARCH_CHIP_STM32G0B1MC - bool "STM32G0B1MC" - select STM32F0L0G0_STM32G0B1 - select STM32F0L0G0_FLASH_CONFIG_C - depends on ARCH_CHIP_STM32G0 - -config ARCH_CHIP_STM32G0B1VC - bool "STM32G0B1VC" - select STM32F0L0G0_STM32G0B1 - select STM32F0L0G0_FLASH_CONFIG_C - depends on ARCH_CHIP_STM32G0 - -config ARCH_CHIP_STM32G0B1KE - bool "STM32G0B1KE" - select STM32F0L0G0_STM32G0B1 - select STM32F0L0G0_FLASH_CONFIG_E - depends on ARCH_CHIP_STM32G0 - -config ARCH_CHIP_STM32G0B1CE - bool "STM32G0B1CE" - select STM32F0L0G0_STM32G0B1 - select STM32F0L0G0_FLASH_CONFIG_E - depends on ARCH_CHIP_STM32G0 - -config ARCH_CHIP_STM32G0B1RE - bool "STM32G0B1RE" - select STM32F0L0G0_STM32G0B1 - select STM32F0L0G0_FLASH_CONFIG_E - depends on ARCH_CHIP_STM32G0 - -config ARCH_CHIP_STM32G0B1NE - bool "STM32G0B1NE" - select STM32F0L0G0_STM32G0B1 - select STM32F0L0G0_FLASH_CONFIG_E - depends on ARCH_CHIP_STM32G0 - -config ARCH_CHIP_STM32G0B1ME - bool "STM32G0B1ME" - select STM32F0L0G0_STM32G0B1 - select STM32F0L0G0_FLASH_CONFIG_E - depends on ARCH_CHIP_STM32G0 - -config ARCH_CHIP_STM32G0B1VE - bool "STM32G0B1VE" - select STM32F0L0G0_STM32G0B1 - select STM32F0L0G0_FLASH_CONFIG_E - depends on ARCH_CHIP_STM32G0 - -config ARCH_CHIP_STM32G0B1KB - bool "STM32G0B1KB" - select STM32F0L0G0_STM32G0B1 - depends on ARCH_CHIP_STM32G0 - -config ARCH_CHIP_STM32G0B1CB - bool "STM32G0B1CB" - select STM32F0L0G0_STM32G0B1 - depends on ARCH_CHIP_STM32G0 - -config ARCH_CHIP_STM32G0B1RB - bool "STM32G0B1RB" - select STM32F0L0G0_STM32G0B1 - depends on ARCH_CHIP_STM32G0 - -config ARCH_CHIP_STM32G0B1MB - bool "STM32G0B1MB" - select STM32F0L0G0_STM32G0B1 - depends on ARCH_CHIP_STM32G0 - -config ARCH_CHIP_STM32G0B1VB - bool "STM32G0B1VB" - select STM32F0L0G0_STM32G0B1 - depends on ARCH_CHIP_STM32G0 - -config ARCH_CHIP_STM32G0B1KC - bool "STM32G0B1KC" - select STM32F0L0G0_STM32G0B1 - depends on ARCH_CHIP_STM32G0 - -config ARCH_CHIP_STM32G0B1CC - bool "STM32G0B1CC" - select STM32F0L0G0_STM32G0B1 - depends on ARCH_CHIP_STM32G0 - -config ARCH_CHIP_STM32G0B1RC - bool "STM32G0B1RC" - select STM32F0L0G0_STM32G0B1 - depends on ARCH_CHIP_STM32G0 - -config ARCH_CHIP_STM32G0B1MC - bool "STM32G0B1MC" - select STM32F0L0G0_STM32G0B1 - depends on ARCH_CHIP_STM32G0 - -config ARCH_CHIP_STM32G0B1VC - bool "STM32G0B1VC" - select STM32F0L0G0_STM32G0B1 - depends on ARCH_CHIP_STM32G0 - -config ARCH_CHIP_STM32G0B1KE - bool "STM32G0B1KE" - select STM32F0L0G0_STM32G0B1 - depends on ARCH_CHIP_STM32G0 - -config ARCH_CHIP_STM32G0B1CE - bool "STM32G0B1CE" - select STM32F0L0G0_STM32G0B1 - depends on ARCH_CHIP_STM32G0 - -config ARCH_CHIP_STM32G0B1RE - bool "STM32G0B1RE" - select STM32F0L0G0_STM32G0B1 - depends on ARCH_CHIP_STM32G0 - -config ARCH_CHIP_STM32G0B1NE - bool "STM32G0B1NE" - select STM32F0L0G0_STM32G0B1 - depends on ARCH_CHIP_STM32G0 - -config ARCH_CHIP_STM32G0B1ME - bool "STM32G0B1ME" - select STM32F0L0G0_STM32G0B1 - depends on ARCH_CHIP_STM32G0 - -config ARCH_CHIP_STM32G0B1VE - bool "STM32G0B1VE" - select STM32F0L0G0_STM32G0B1 - depends on ARCH_CHIP_STM32G0 - -config ARCH_CHIP_STM32L053C8 - bool "STM32L053C8" - select ARCH_CHIP_STM32L053XX - depends on ARCH_CHIP_STM32L0 - -config ARCH_CHIP_STM32L053R8 - bool "STM32L053R8" - select ARCH_CHIP_STM32L053XX - depends on ARCH_CHIP_STM32L0 - -config ARCH_CHIP_STM32L071K8 - bool "STM32L071K8" - select ARCH_CHIP_STM32L071XX - depends on ARCH_CHIP_STM32L0 - -config ARCH_CHIP_STM32L071KB - bool "STM32L071KB" - select ARCH_CHIP_STM32L071XX - depends on ARCH_CHIP_STM32L0 - -config ARCH_CHIP_STM32L071KZ - bool "STM32L071KZ" - select ARCH_CHIP_STM32L071XX - depends on ARCH_CHIP_STM32L0 - -config ARCH_CHIP_STM32L071C8 - bool "STM32L071C8" - select ARCH_CHIP_STM32L071XX - select STM32F0L0G0_HAVE_USART5 - select STM32F0L0G0_HAVE_SPI2 - select STM32F0L0G0_HAVE_I2C3 - depends on ARCH_CHIP_STM32L0 - -config ARCH_CHIP_STM32L071CB - bool "STM32L071CB" - select ARCH_CHIP_STM32L071XX - select STM32F0L0G0_HAVE_USART5 - select STM32F0L0G0_HAVE_SPI2 - select STM32F0L0G0_HAVE_I2C3 - depends on ARCH_CHIP_STM32L0 - -config ARCH_CHIP_STM32L071CZ - bool "STM32L071CZ" - select ARCH_CHIP_STM32L071XX - select STM32F0L0G0_HAVE_USART5 - select STM32F0L0G0_HAVE_SPI2 - select STM32F0L0G0_HAVE_I2C3 - depends on ARCH_CHIP_STM32L0 - -config ARCH_CHIP_STM32L071V8 - bool "STM32L071V8" - select ARCH_CHIP_STM32L071XX - select STM32F0L0G0_HAVE_USART5 - select STM32F0L0G0_HAVE_SPI2 - select STM32F0L0G0_HAVE_I2C3 - depends on ARCH_CHIP_STM32L0 - -config ARCH_CHIP_STM32L071VB - bool "STM32L071VB" - select ARCH_CHIP_STM32L071XX - select STM32F0L0G0_HAVE_USART5 - select STM32F0L0G0_HAVE_SPI2 - select STM32F0L0G0_HAVE_I2C3 - depends on ARCH_CHIP_STM32L0 - -config ARCH_CHIP_STM32L071VZ - bool "STM32L071VZ" - select ARCH_CHIP_STM32L071XX - select STM32F0L0G0_HAVE_USART5 - select STM32F0L0G0_HAVE_SPI2 - select STM32F0L0G0_HAVE_I2C3 - depends on ARCH_CHIP_STM32L0 - -config ARCH_CHIP_STM32L071RB - bool "STM32L071RB" - select ARCH_CHIP_STM32L071XX - select STM32F0L0G0_HAVE_USART5 - select STM32F0L0G0_HAVE_SPI2 - select STM32F0L0G0_HAVE_I2C3 - depends on ARCH_CHIP_STM32L0 - -config ARCH_CHIP_STM32L071RZ - bool "STM32L071RZ" - select ARCH_CHIP_STM32L071XX - select STM32F0L0G0_HAVE_USART5 - select STM32F0L0G0_HAVE_SPI2 - select STM32F0L0G0_HAVE_I2C3 - depends on ARCH_CHIP_STM32L0 - -config ARCH_CHIP_STM32L072V8 - bool "STM32L072V8" - select ARCH_CHIP_STM32L072XX - select STM32F0L0G0_HAVE_SPI2 - select STM32F0L0G0_HAVE_I2C3 - depends on ARCH_CHIP_STM32L0 - -config ARCH_CHIP_STM32L072VB - bool "STM32L072VB" - select ARCH_CHIP_STM32L072XX - select STM32F0L0G0_HAVE_SPI2 - select STM32F0L0G0_HAVE_I2C3 - depends on ARCH_CHIP_STM32L0 - -config ARCH_CHIP_STM32L072VZ - bool "STM32L072VZ" - select ARCH_CHIP_STM32L072XX - select STM32F0L0G0_HAVE_SPI2 - select STM32F0L0G0_HAVE_I2C3 - depends on ARCH_CHIP_STM32L0 - -config ARCH_CHIP_STM32L072KB - bool "STM32L072KB" - select ARCH_CHIP_STM32L072XX - depends on ARCH_CHIP_STM32L0 - -config ARCH_CHIP_STM32L072KZ - bool "STM32L072KZ" - select ARCH_CHIP_STM32L072XX - depends on ARCH_CHIP_STM32L0 - -config ARCH_CHIP_STM32L072CB - bool "STM32L072CB" - select ARCH_CHIP_STM32L072XX - select STM32F0L0G0_HAVE_SPI2 - select STM32F0L0G0_HAVE_I2C3 - depends on ARCH_CHIP_STM32L0 - -config ARCH_CHIP_STM32L072CZ - bool "STM32L072CZ" - select ARCH_CHIP_STM32L072XX - select STM32F0L0G0_HAVE_SPI2 - select STM32F0L0G0_HAVE_I2C3 - depends on ARCH_CHIP_STM32L0 - -config ARCH_CHIP_STM32L072RB - bool "STM32L072RB" - select ARCH_CHIP_STM32L072XX - select STM32F0L0G0_HAVE_SPI2 - select STM32F0L0G0_HAVE_I2C3 - depends on ARCH_CHIP_STM32L0 - -config ARCH_CHIP_STM32L072RZ - bool "STM32L072RZ" - select ARCH_CHIP_STM32L072XX - select STM32F0L0G0_HAVE_SPI2 - select STM32F0L0G0_HAVE_I2C3 - depends on ARCH_CHIP_STM32L0 - -config ARCH_CHIP_STM32L073V8 - bool "STM32L073V8" - select ARCH_CHIP_STM32L073XX - depends on ARCH_CHIP_STM32L0 - -config ARCH_CHIP_STM32L073VB - bool "STM32L073VB" - select ARCH_CHIP_STM32L073XX - depends on ARCH_CHIP_STM32L0 - -config ARCH_CHIP_STM32L073VZ - bool "STM32L073VZ" - select ARCH_CHIP_STM32L073XX - depends on ARCH_CHIP_STM32L0 - -config ARCH_CHIP_STM32L073CB - bool "STM32L073CB" - select ARCH_CHIP_STM32L073XX - depends on ARCH_CHIP_STM32L0 - -config ARCH_CHIP_STM32L073CZ - bool "STM32L073CZ" - select ARCH_CHIP_STM32L073XX - depends on ARCH_CHIP_STM32L0 - -config ARCH_CHIP_STM32L073RB - bool "STM32L073RB" - select ARCH_CHIP_STM32L073XX - depends on ARCH_CHIP_STM32L0 - -config ARCH_CHIP_STM32L073RZ - bool "STM32L073RZ" - select ARCH_CHIP_STM32L073XX - depends on ARCH_CHIP_STM32L0 - -config ARCH_CHIP_STM32C051D8 - bool "STM32C051D8" - select ARCH_CHIP_STM32C051XX - select STM32F0L0G0_FLASH_CONFIG_8 - -config ARCH_CHIP_STM32C051F6 - bool "STM32C051F6" - select ARCH_CHIP_STM32C051XX - select STM32F0L0G0_FLASH_CONFIG_6 - -config ARCH_CHIP_STM32C051F8 - bool "STM32C051F8" - select ARCH_CHIP_STM32C051XX - select STM32F0L0G0_FLASH_CONFIG_8 - -config ARCH_CHIP_STM32C051G6 - bool "STM32C051G6" - select ARCH_CHIP_STM32C051XX - select STM32F0L0G0_FLASH_CONFIG_6 - -config ARCH_CHIP_STM32C051G8 - bool "STM32C051G8" - select ARCH_CHIP_STM32C051XX - select STM32F0L0G0_FLASH_CONFIG_8 - -config ARCH_CHIP_STM32C051K6 - bool "STM32C051K6" - select ARCH_CHIP_STM32C051XX - select STM32F0L0G0_FLASH_CONFIG_6 - -config ARCH_CHIP_STM32C051K8 - bool "STM32C051K8" - select ARCH_CHIP_STM32C051XX - select STM32F0L0G0_FLASH_CONFIG_8 - -config ARCH_CHIP_STM32C051C6 - bool "STM32C051C6" - select ARCH_CHIP_STM32C051XX - select STM32F0L0G0_FLASH_CONFIG_6 - -config ARCH_CHIP_STM32C051C8 - bool "STM32C051C8" - select ARCH_CHIP_STM32C051XX - select STM32F0L0G0_FLASH_CONFIG_8 - -config ARCH_CHIP_STM32C071F8 - bool "STM32C071F8" - select ARCH_CHIP_STM32C071XX - select STM32F0L0G0_FLASH_CONFIG_8 - -config ARCH_CHIP_STM32C071FB - bool "STM32C071FB" - select ARCH_CHIP_STM32C071XX - select STM32F0L0G0_FLASH_CONFIG_B - -config ARCH_CHIP_STM32C071G8 - bool "STM32C071G8" - select ARCH_CHIP_STM32C071XX - select STM32F0L0G0_FLASH_CONFIG_8 - -config ARCH_CHIP_STM32C071GB - bool "STM32C071GB" - select ARCH_CHIP_STM32C071XX - select STM32F0L0G0_FLASH_CONFIG_B - -config ARCH_CHIP_STM32C071K8 - bool "STM32C071K8" - select ARCH_CHIP_STM32C071XX - select STM32F0L0G0_FLASH_CONFIG_8 - -config ARCH_CHIP_STM32C071KB - bool "STM32C071KB" - select ARCH_CHIP_STM32C071XX - select STM32F0L0G0_FLASH_CONFIG_B - -config ARCH_CHIP_STM32C071C8 - bool "STM32C071C8" - select ARCH_CHIP_STM32C071XX - select STM32F0L0G0_FLASH_CONFIG_8 - -config ARCH_CHIP_STM32C071CB - bool "STM32C071CB" - select ARCH_CHIP_STM32C071XX - select STM32F0L0G0_FLASH_CONFIG_B - -config ARCH_CHIP_STM32C071R8 - bool "STM32C071R8" - select ARCH_CHIP_STM32C071XX - select STM32F0L0G0_FLASH_CONFIG_8 - -config ARCH_CHIP_STM32C071RB - bool "STM32C071RB" - select ARCH_CHIP_STM32C071XX - select STM32F0L0G0_FLASH_CONFIG_B - -config ARCH_CHIP_STM32C091FB - bool "STM32C091FB" - select ARCH_CHIP_STM32C091XX - select STM32F0L0G0_FLASH_CONFIG_B - -config ARCH_CHIP_STM32C091FC - bool "STM32C091FC" - select ARCH_CHIP_STM32C091XX - select STM32F0L0G0_FLASH_CONFIG_C - -config ARCH_CHIP_STM32C091EC - bool "STM32C091EC" - select ARCH_CHIP_STM32C091XX - select STM32F0L0G0_FLASH_CONFIG_C - -config ARCH_CHIP_STM32C091GB - bool "STM32C091GB" - select ARCH_CHIP_STM32C091XX - select STM32F0L0G0_FLASH_CONFIG_B - -config ARCH_CHIP_STM32C091GC - bool "STM32C091GC" - select ARCH_CHIP_STM32C091XX - select STM32F0L0G0_FLASH_CONFIG_C - -config ARCH_CHIP_STM32C091KB - bool "STM32C091KB" - select ARCH_CHIP_STM32C091XX - select STM32F0L0G0_FLASH_CONFIG_B - -config ARCH_CHIP_STM32C091KC - bool "STM32C091KC" - select ARCH_CHIP_STM32C091XX - select STM32F0L0G0_FLASH_CONFIG_C - -config ARCH_CHIP_STM32C091CB - bool "STM32C091CB" - select ARCH_CHIP_STM32C091XX - select STM32F0L0G0_FLASH_CONFIG_B - -config ARCH_CHIP_STM32C091CC - bool "STM32C091CC" - select ARCH_CHIP_STM32C091XX - select STM32F0L0G0_FLASH_CONFIG_C - -config ARCH_CHIP_STM32C091RB - bool "STM32C091RB" - select ARCH_CHIP_STM32C091XX - select STM32F0L0G0_FLASH_CONFIG_B - -config ARCH_CHIP_STM32C091RC - bool "STM32C091RC" - select ARCH_CHIP_STM32C091XX - select STM32F0L0G0_FLASH_CONFIG_C - -config ARCH_CHIP_STM32C092FB - bool "STM32C092FB" - select ARCH_CHIP_STM32C092XX - select STM32F0L0G0_FLASH_CONFIG_B - -config ARCH_CHIP_STM32C092FC - bool "STM32C092FC" - select ARCH_CHIP_STM32C092XX - select STM32F0L0G0_FLASH_CONFIG_C - -config ARCH_CHIP_STM32C092EC - bool "STM32C092EC" - select ARCH_CHIP_STM32C092XX - select STM32F0L0G0_FLASH_CONFIG_C - -config ARCH_CHIP_STM32C092GB - bool "STM32C092GB" - select ARCH_CHIP_STM32C092XX - select STM32F0L0G0_FLASH_CONFIG_B - -config ARCH_CHIP_STM32C092GC - bool "STM32C092GC" - select ARCH_CHIP_STM32C092XX - select STM32F0L0G0_FLASH_CONFIG_C - -config ARCH_CHIP_STM32C092KB - bool "STM32C092KB" - select ARCH_CHIP_STM32C092XX - select STM32F0L0G0_FLASH_CONFIG_B - -config ARCH_CHIP_STM32C092KC - bool "STM32C092KC" - select ARCH_CHIP_STM32C092XX - select STM32F0L0G0_FLASH_CONFIG_C - -config ARCH_CHIP_STM32C092CB - bool "STM32C092CB" - select ARCH_CHIP_STM32C092XX - select STM32F0L0G0_FLASH_CONFIG_B - -config ARCH_CHIP_STM32C092CC - bool "STM32C092CC" - select ARCH_CHIP_STM32C092XX - select STM32F0L0G0_FLASH_CONFIG_C - -config ARCH_CHIP_STM32C092RB - bool "STM32C092RB" - select ARCH_CHIP_STM32C092XX - select STM32F0L0G0_FLASH_CONFIG_B - -config ARCH_CHIP_STM32C092RC - bool "STM32C092RC" - select ARCH_CHIP_STM32C092XX - select STM32F0L0G0_FLASH_CONFIG_C - -endchoice # ST STM32F0/L0/G0/C0 Chip Selection - -# Flash configurations - -config STM32F0L0G0_FLASH_CONFIG_4 - bool - default n - -config STM32F0L0G0_FLASH_CONFIG_6 - bool - default n - -config STM32F0L0G0_FLASH_CONFIG_8 - bool - default n - -config STM32F0L0G0_FLASH_CONFIG_B - bool - default n - -config STM32F0L0G0_FLASH_CONFIG_C - bool - default n - -config STM32F0L0G0_FLASH_CONFIG_D - bool - default n - -config STM32F0L0G0_FLASH_CONFIG_E - bool - default n - -config STM32F0L0G0_FLASH_CONFIG_F - bool - default n - -config STM32F0L0G0_FLASH_CONFIG_G - bool - default n - -config STM32F0L0G0_FLASH_CONFIG_I - bool - default n - -config STM32F0L0G0_FLASH_OVERRIDE - bool "Override Flash Designator" - default n - -choice - prompt "Override Flash Size Designator" - depends on STM32F0L0G0_FLASH_OVERRIDE - default STM32F0L0G0_FLASH_OVERRIDE_B - ---help--- - STM32F series parts numbering (sans the package type) ends with a number or letter - that designates the FLASH size. - - Designator Size in KiB - 4 16 - 6 32 - 8 64 - B 128 - C 256 - D 384 - E 512 - F 768 - G 1024 - I 2048 - - This configuration option defaults to using the configuration based on that designator - or the default smaller size if there is no last character designator is present in the - STM32 Chip Selection. - - Examples: - If the STM32G071RB is chosen, the Flash configuration would be 'B', if a variant of - the part with a 2048 KiB Flash is released in the future one could simply select - the 'I' designator here. - -config STM32F0L0G0_FLASH_OVERRIDE_4 - bool "4 16KiB" - -config STM32F0L0G0_FLASH_OVERRIDE_6 - bool "6 32KiB" - -config STM32F0L0G0_FLASH_OVERRIDE_8 - bool "8 64KiB" - -config STM32F0L0G0_FLASH_OVERRIDE_B - bool "B 128KiB" - -config STM32F0L0G0_FLASH_OVERRIDE_C - bool "C 256KiB" - -config STM32F0L0G0_FLASH_OVERRIDE_D - bool "D 384KiB" - -config STM32F0L0G0_FLASH_OVERRIDE_E - bool "E 512KiB" - -config STM32F0L0G0_FLASH_OVERRIDE_F - bool "F 768KiB" - -config STM32F0L0G0_FLASH_OVERRIDE_G - bool "G 1024KiB" - -config STM32F0L0G0_FLASH_OVERRIDE_I - bool "I 2048KiB" - -endchoice # Override Flash Size Designator - -config STM32F0L0G0_STM32F0 - bool - default n - select STM32F0L0G0_HAVE_USART3 - select STM32F0L0G0_HAVE_USART4 - select STM32F0L0G0_HAVE_TIM1 - select STM32F0L0G0_HAVE_TIM2 - select STM32F0L0G0_HAVE_TIM3 - select STM32F0L0G0_HAVE_TIM6 - select STM32F0L0G0_HAVE_TIM7 - select STM32F0L0G0_HAVE_TIM14 - select STM32F0L0G0_HAVE_TIM15 - select STM32F0L0G0_HAVE_TIM16 - select STM32F0L0G0_HAVE_TIM17 - select STM32F0L0G0_HAVE_ADC1_DMA - select STM32F0L0G0_HAVE_IP_USART_V1 - select STM32F0L0G0_HAVE_IP_EXTI_V1 - -config STM32F0L0G0_STM32G0 - bool - default n - select STM32F0L0G0_HAVE_ADC1_DMA - select STM32F0L0G0_HAVE_DMAMUX - select STM32F0L0G0_HAVE_IP_USART_V2 - select STM32F0L0G0_HAVE_IP_EXTI_V2 - select STM32F0L0G0_HAVE_TIM1 - select STM32F0L0G0_HAVE_TIM3 - select STM32F0L0G0_HAVE_TIM14 - select STM32F0L0G0_HAVE_TIM16 - select STM32F0L0G0_HAVE_TIM17 - select STM32F0L0G0_HAVE_I2C2 - select ARCH_HAVE_PROGMEM - -config STM32F0L0G0_STM32L0 - bool - default n - select STM32F0L0G0_ENERGYLITE - select STM32F0L0G0_HAVE_VREFINT - select STM32F0L0G0_HAVE_ADC1_DMA - select STM32F0L0G0_HAVE_IP_USART_V1 - select STM32F0L0G0_HAVE_IP_EXTI_V1 - -config STM32F0L0G0_STM32C0 - bool - default n - select STM32F0L0G0_HAVE_SPI2 - select STM32F0L0G0_HAVE_I2C2 - select STM32F0L0G0_HAVE_DMAMUX - select STM32F0L0G0_HAVE_ADC1_DMA - select STM32F0L0G0_HAVE_IP_USART_V2 - select STM32F0L0G0_HAVE_IP_EXTI_V2 - select STM32F0L0G0_HAVE_TIM1 - select STM32F0L0G0_HAVE_TIM2 - select STM32F0L0G0_HAVE_TIM3 - select STM32F0L0G0_HAVE_TIM14 - select STM32F0L0G0_HAVE_TIM16 - select STM32F0L0G0_HAVE_TIM17 - select ARCH_HAVE_PROGMEM - -config STM32F0L0G0_STM32F03X - bool - default n - select STM32F0L0G0_STM32F0 - -config STM32F0L0G0_STM32F04X - bool - default n - select STM32F0L0G0_STM32F0 - -config STM32F0L0G0_STM32F05X - bool - default n - select STM32F0L0G0_STM32F0 - -config STM32F0L0G0_STM32F07X - bool - default n - select STM32F0L0G0_STM32F0 - -config STM32F0L0G0_STM32F09X - bool - default n - select STM32F0L0G0_STM32F0 - select STM32F0L0G0_HAVE_HSI48 - select STM32F0L0G0_HAVE_DMA2 - -config STM32F0L0G0_STM32G030 - bool - default n - select STM32F0L0G0_STM32G0 - select STM32F0L0G0_STM32G03X - -config STM32F0L0G0_STM32G031 - bool - default n - select STM32F0L0G0_STM32G0 - select STM32F0L0G0_STM32G03X - select STM32F0L0G0_HAVE_LPUART1 - -config STM32F0L0G0_STM32G03X - bool - default n - -config STM32F0L0G0_STM32G041 - bool - default n - select STM32F0L0G0_STM32G0 - select STM32F0L0G0_HAVE_RNG - select STM32F0L0G0_HAVE_AES - select STM32F0L0G0_HAVE_LPUART1 - -config STM32F0L0G0_STM32G050 - bool - default n - select STM32F0L0G0_STM32G0 - select STM32F0L0G0_STM32G05X - -config STM32F0L0G0_STM32G051 - bool - default n - select STM32F0L0G0_STM32G0 - select STM32F0L0G0_STM32G05X - select STM32F0L0G0_HAVE_DAC1 - select STM32F0L0G0_HAVE_COMP1 - select STM32F0L0G0_HAVE_COMP2 - select STM32F0L0G0_HAVE_TIM15 - select STM32F0L0G0_HAVE_LPUART1 - -config STM32F0L0G0_STM32G05X - bool - default n - select STM32F0L0G0_HAVE_TIM6 - select STM32F0L0G0_HAVE_TIM7 - -config STM32F0L0G0_STM32G061 - bool - default n - select STM32F0L0G0_STM32G0 - select STM32F0L0G0_HAVE_RNG - select STM32F0L0G0_HAVE_AES - select STM32F0L0G0_HAVE_DAC1 - select STM32F0L0G0_HAVE_COMP1 - select STM32F0L0G0_HAVE_COMP2 - select STM32F0L0G0_HAVE_TIM6 - select STM32F0L0G0_HAVE_TIM7 - select STM32F0L0G0_HAVE_TIM15 - select STM32F0L0G0_HAVE_LPUART1 - -config STM32F0L0G0_STM32G070 - bool - default n - select STM32F0L0G0_STM32G0 - select STM32F0L0G0_STM32G07X - -config STM32F0L0G0_STM32G071 - bool - default n - select STM32F0L0G0_STM32G0 - select STM32F0L0G0_STM32G07X - select STM32F0L0G0_HAVE_DAC1 - select STM32F0L0G0_HAVE_COMP1 - select STM32F0L0G0_HAVE_COMP2 - select STM32F0L0G0_HAVE_CEC - select STM32F0L0G0_HAVE_LPUART1 - -config STM32F0L0G0_STM32G07X - bool - default n - select STM32F0L0G0_HAVE_USART3 - select STM32F0L0G0_HAVE_USART4 - select STM32F0L0G0_HAVE_TIM6 - select STM32F0L0G0_HAVE_TIM7 - select STM32F0L0G0_HAVE_TIM15 - select STM32F0L0G0_HAVE_UCPD1 - select STM32F0L0G0_HAVE_UCPD2 - -config STM32F0L0G0_STM32G081 - bool - default n - select STM32F0L0G0_STM32G0 - select STM32F0L0G0_HAVE_USART3 - select STM32F0L0G0_HAVE_USART4 - select STM32F0L0G0_HAVE_RNG - select STM32F0L0G0_HAVE_AES - select STM32F0L0G0_HAVE_DAC1 - select STM32F0L0G0_HAVE_COMP1 - select STM32F0L0G0_HAVE_COMP2 - select STM32F0L0G0_HAVE_TIM6 - select STM32F0L0G0_HAVE_TIM7 - select STM32F0L0G0_HAVE_TIM15 - select STM32F0L0G0_HAVE_UCPD1 - select STM32F0L0G0_HAVE_UCPD2 - select STM32F0L0G0_HAVE_CEC - select STM32F0L0G0_HAVE_LPUART1 - -config STM32F0L0G0_STM32G0B0 - bool - default n - select STM32F0L0G0_STM32G0 - select STM32F0L0G0_STM32G0BX - -config STM32F0L0G0_STM32G0B1 - bool - default n - select STM32F0L0G0_STM32G0 - select STM32F0L0G0_STM32G0BX - select STM32F0L0G0_HAVE_DAC1 - select STM32F0L0G0_HAVE_COMP1 - select STM32F0L0G0_HAVE_COMP2 - select STM32F0L0G0_HAVE_COMP3 - select STM32F0L0G0_HAVE_FDCAN1 - select STM32F0L0G0_HAVE_FDCAN2 - select STM32F0L0G0_HAVE_CEC - -config STM32F0L0G0_STM32G0BX - bool - default n - select STM32F0L0G0_HAVE_DMA2 - select STM32F0L0G0_HAVE_USART3 - select STM32F0L0G0_HAVE_USART4 - select STM32F0L0G0_HAVE_USART5 - select STM32F0L0G0_HAVE_USART6 - select STM32F0L0G0_HAVE_LPUART1 - select STM32F0L0G0_HAVE_LPUART2 - select STM32F0L0G0_HAVE_CRS - select STM32F0L0G0_HAVE_TIM4 - select STM32F0L0G0_HAVE_TIM6 - select STM32F0L0G0_HAVE_TIM7 - select STM32F0L0G0_HAVE_TIM15 - select STM32F0L0G0_HAVE_I2C3 - select STM32F0L0G0_HAVE_SPI3 - select STM32F0L0G0_HAVE_I2S2 - select STM32F0L0G0_HAVE_USBDEV - select STM32F0L0G0_HAVE_UCPD1 - select STM32F0L0G0_HAVE_UCPD2 - select STM32F0L0G0_HAVE_HSI48 - -config STM32F0L0G0_STM32G0C1 - bool - default n - select STM32F0L0G0_STM32G0 - select STM32F0L0G0_HAVE_DMA2 - select STM32F0L0G0_HAVE_USART3 - select STM32F0L0G0_HAVE_USART4 - select STM32F0L0G0_HAVE_USART5 - select STM32F0L0G0_HAVE_USART6 - select STM32F0L0G0_HAVE_CRS - select STM32F0L0G0_HAVE_RNG - select STM32F0L0G0_HAVE_AES - select STM32F0L0G0_HAVE_DAC1 - select STM32F0L0G0_HAVE_COMP1 - select STM32F0L0G0_HAVE_COMP2 - select STM32F0L0G0_HAVE_COMP3 - select STM32F0L0G0_HAVE_TIM4 - select STM32F0L0G0_HAVE_TIM6 - select STM32F0L0G0_HAVE_TIM7 - select STM32F0L0G0_HAVE_TIM15 - select STM32F0L0G0_HAVE_I2C3 - select STM32F0L0G0_HAVE_SPI3 - select STM32F0L0G0_HAVE_I2S2 - select STM32F0L0G0_HAVE_LPUART2 - select STM32F0L0G0_HAVE_USBDEV - select STM32F0L0G0_HAVE_UCPD1 - select STM32F0L0G0_HAVE_UCPD2 - select STM32F0L0G0_HAVE_FDCAN1 - select STM32F0L0G0_HAVE_FDCAN2 - select STM32F0L0G0_HAVE_CEC - select STM32F0L0G0_HAVE_HSI48 - -config STM32F0L0G0_VALUELINE - bool - default n - select STM32F0L0G0_HAVE_USART5 - select STM32F0L0G0_HAVE_SPI2 - -config STM32F0L0G0_ACCESSLINE - bool - default n - select STM32F0L0G0_HAVE_USART5 - select STM32F0L0G0_HAVE_CAN1 - select STM32F0L0G0_HAVE_SPI2 - -config STM32F0L0G0_LOWVOLTLINE - bool - default n - select STM32F0L0G0_HAVE_USART5 - select STM32F0L0G0_HAVE_CAN1 - select STM32F0L0G0_HAVE_SPI2 - -config STM32F0L0G0_USBLINE - bool - default n - select STM32F0L0G0_HAVE_HSI48 - select STM32F0L0G0_HAVE_CAN1 - select STM32F0L0G0_HAVE_SPI2 - select STM32F0L0G0_HAVE_USBDEV - -config STM32F0L0G0_ENERGYLITE - bool - default n - -config ARCH_CHIP_STM32L053XX - bool - select STM32F0L0G0_STM32L0 - -config ARCH_CHIP_STM32L071XX - bool - select STM32F0L0G0_STM32L0 - select STM32F0L0G0_HAVE_RNG - select STM32F0L0G0_HAVE_HSI48 - select STM32F0L0G0_HAVE_USART4 - -config ARCH_CHIP_STM32L072XX - bool - select STM32F0L0G0_STM32L0 - select STM32F0L0G0_HAVE_RNG - select STM32F0L0G0_HAVE_HSI48 - select STM32F0L0G0_HAVE_USART4 - select STM32F0L0G0_HAVE_USART5 - select STM32F0L0G0_HAVE_I2C2 - select STM32F0L0G0_HAVE_USBDEV - -config ARCH_CHIP_STM32L073XX - bool - select STM32F0L0G0_STM32L0 - select STM32F0L0G0_HAVE_RNG - select STM32F0L0G0_HAVE_HSI48 - select STM32F0L0G0_HAVE_USART4 - select STM32F0L0G0_HAVE_USART5 - select STM32F0L0G0_HAVE_SPI2 - select STM32F0L0G0_HAVE_I2C2 - select STM32F0L0G0_HAVE_I2C3 - select STM32F0L0G0_HAVE_USBDEV - -config ARCH_CHIP_STM32C051XX - bool - select STM32F0L0G0_STM32C0 - -config ARCH_CHIP_STM32C071XX - bool - select STM32F0L0G0_STM32C0 - select STM32F0L0G0_HAVE_USBDEV - -config ARCH_CHIP_STM32C091XX - bool - select STM32F0L0G0_STM32C0 - select STM32F0L0G0_HAVE_USART3 - select STM32F0L0G0_HAVE_USART4 - select STM32F0L0G0_HAVE_TIM15 - -config ARCH_CHIP_STM32C092XX - bool - select STM32F0L0G0_STM32C0 - select STM32F0L0G0_HAVE_USART3 - select STM32F0L0G0_HAVE_USART4 - select STM32F0L0G0_HAVE_FDCAN1 - -config STM32F0L0G0_DFU - bool "DFU bootloader" - default n - depends on !STM32F0L0G0_VALUELINE - ---help--- - Configure and position code for use with the STMicro DFU bootloader. Do - not select this option if you will load code using JTAG/SWM. - -config STM32F0L0G0_PROGMEM - bool "Flash PROGMEM support" - default n - depends on ARCH_HAVE_PROGMEM - select MTD - select MTD_PROGMEM - ---help--- - Add progmem support, start block and end block options are provided to - obtain a uniform flash memory mapping. - -choice - prompt "SysTick clock source" - default STM32F0L0G0_SYSTICK_CORECLK - -config STM32F0L0G0_SYSTICK_CORECLK - bool "Cortex-M0 core clock" - -config STM32F0L0G0_SYSTICK_CORECLK_DIV16 - bool "Cortex-M0 core clock divided by 16" - -endchoice # SysTick clock source - -config ARCH_BOARD_STM32F0G0L0_CUSTOM_CLOCKCONFIG - bool "Custom clock configuration" - default n - ---help--- - Enables special, board-specific STM32 clock configuration. - -menu "STM32 Peripheral Support" - -# These "hidden" settings determine whether a peripheral option is available -# for the selected MCU - -config STM32F0L0G0_HAVE_AES - bool - default n - -config STM32F0L0G0_HAVE_VREFINT - bool - default n - -config STM32F0L0G0_HAVE_CCM - bool - default n - -config STM32F0L0G0_HAVE_HSI48 - bool - default n - -config STM32F0L0G0_HAVE_LCD - bool - default n - -config STM32F0L0G0_HAVE_USBDEV - bool - default n - -config STM32F0L0G0_HAVE_FSMC - bool - default n - -config STM32F0L0G0_HAVE_USART3 - bool - default n - -config STM32F0L0G0_HAVE_USART4 - bool - default n - -config STM32F0L0G0_HAVE_USART5 - bool - default n - -config STM32F0L0G0_HAVE_USART6 - bool - default n - -config STM32F0L0G0_HAVE_USART7 - bool - default n - -config STM32F0L0G0_HAVE_USART8 - bool - default n - -config STM32F0L0G0_HAVE_LPUART1 - bool - default n - -config STM32F0L0G0_HAVE_LPUART2 - bool - default n - -config STM32F0L0G0_HAVE_TIM1 - bool - default n - -config STM32F0L0G0_HAVE_TIM2 - bool - default n - -config STM32F0L0G0_HAVE_TIM3 - bool - default n - -config STM32F0L0G0_HAVE_TIM4 - bool - default n - -config STM32F0L0G0_HAVE_TIM6 - bool - default n - -config STM32F0L0G0_HAVE_TIM7 - bool - default n - -config STM32F0L0G0_HAVE_TIM14 - bool - default n - -config STM32F0L0G0_HAVE_TIM15 - bool - default n - -config STM32F0L0G0_HAVE_TIM16 - bool - default n - -config STM32F0L0G0_HAVE_TIM17 - bool - default n - -config STM32F0L0G0_HAVE_TSC - bool - default n - -config STM32F0L0G0_HAVE_ADC1_DMA - bool - default n - -config STM32F0L0G0_HAVE_ADC_OVERSAMPLE - bool - default STM32F0L0G0_STM32L0 || STM32F0L0G0_STM32G0 || STM32F0L0G0_STM32C0 - -config STM32F0L0G0_HAVE_CEC - bool - default n - -config STM32F0L0G0_HAVE_CAN1 - bool - default n - -config STM32F0L0G0_HAVE_COMP1 - bool - default n - -config STM32F0L0G0_HAVE_COMP2 - bool - default n - -config STM32F0L0G0_HAVE_COMP3 - bool - default n - -config STM32F0L0G0_HAVE_DAC1 - bool - default n - -config STM32F0L0G0_HAVE_DMAMUX - bool - default n - -config STM32F0L0G0_HAVE_DMA2 - bool - default n - -config STM32F0L0G0_HAVE_RNG - bool - default n - -config STM32F0L0G0_HAVE_CRS - bool - default n - -config STM32F0L0G0_HAVE_I2C2 - bool - default n - -config STM32F0L0G0_HAVE_I2C3 - bool - default n - -config STM32F0L0G0_HAVE_SPI2 - bool - default n - -config STM32F0L0G0_HAVE_SPI3 - bool - default n - -config STM32F0L0G0_HAVE_SAIPLL - bool - default n - -config STM32F0L0G0_HAVE_SDIO - bool - default n - -config STM32F0L0G0_HAVE_I2SPLL - bool - default n - -config STM32F0L0G0_HAVE_OPAMP1 - bool - default n - -config STM32F0L0G0_HAVE_OPAMP2 - bool - default n - -config STM32F0L0G0_HAVE_OPAMP3 - bool - default n - -config STM32F0L0G0_HAVE_OPAMP4 - bool - default n - -config STM32F0L0G0_HAVE_FDCAN1 - bool - default n - -config STM32F0L0G0_HAVE_FDCAN2 - bool - default n - -config STM32F0L0G0_HAVE_I2S2 - bool - default n - -config STM32F0L0G0_HAVE_UCPD1 - bool - default n - -config STM32F0L0G0_HAVE_UCPD2 - bool - default n - -# These are STM32 peripherals IP blocks - -config STM32F0L0G0_HAVE_IP_USART_V1 - bool - default n - -config STM32F0L0G0_HAVE_IP_USART_V2 - bool - default n - -config STM32F0L0G0_HAVE_IP_EXTI_V1 - bool - default n - -config STM32F0L0G0_HAVE_IP_EXTI_V2 - bool - default n - -# These are the peripheral selections proper - -config STM32F0L0G0_ADC1 - bool "ADC1" - default n - select STM32F0L0G0_ADC - -config STM32F0L0G0_COMP1 - bool "COMP1" - default n - depends on STM32F0L0G0_HAVE_COMP1 - -config STM32F0L0G0_COMP2 - bool "COMP2" - default n - depends on STM32F0L0G0_HAVE_COMP2 - -config STM32F0L0G0_BKP - bool "BKP" - default n - -config STM32F0L0G0_BKPSRAM - bool "Enable BKP RAM Domain" - default n - -config STM32F0L0G0_CAN1 - bool "CAN1" - default n - select CAN - select STM32F0L0G0_CAN - depends on STM32F0L0G0_HAVE_CAN1 - -config STM32F0L0G0_AES - bool "128-bit AES" - default n - depends on STM32F0L0G0_HAVE_AES - select CRYPTO_AES192_DISABLE if CRYPTO_ALGTEST - select CRYPTO_AES256_DISABLE if CRYPTO_ALGTEST - -config STM32F0L0G0_VREFINT - bool "Enable VREFINT" - default n - depends on STM32F0L0G0_HAVE_VREFINT - -config STM32F0L0G0_CEC - bool "CEC" - default n - depends on STM32F0L0G0_HAVE_CEC - -config STM32F0L0G0_CRC - bool "CRC" - default n - -config STM32F0L0G0_CRYP - bool "CRYP" - default n - depends on STM32F0L0G0_HAVE_HASH - -config STM32F0L0G0_DMA1 - bool "DMA1" - default n - select ARCH_DMA - select STM32F0L0G0_DMA - -config STM32F0L0G0_DMA2 - bool "DMA2" - default n - depends on STM32F0L0G0_HAVE_DMA2 - select ARCH_DMA - select STM32F0L0G0_DMA - -config STM32F0L0G0_DAC1 - bool "DAC1" - default n - depends on STM32F0L0G0_HAVE_DAC1 - select STM32F0L0G0_DAC - -config STM32F0L0G0_FDCAN1 - bool "FDCAN1" - default n - depends on STM32F0L0G0_HAVE_FDCAN1 - select STM32F0L0G0_FDCAN - -config STM32F0L0G0_FSMC - bool "FSMC" - default n - depends on STM32F0L0G0_HAVE_FSMC - -config STM32F0L0G0_HASH - bool "HASH" - default n - depends on STM32F0L0G0_HAVE_HASH - -config STM32F0L0G0_I2C1 - bool "I2C1" - default n - select STM32F0L0G0_I2C - -config STM32F0L0G0_I2C2 - bool "I2C2" - default n - depends on STM32F0L0G0_HAVE_I2C2 - select STM32F0L0G0_I2C - -config STM32F0L0G0_I2C3 - bool "I2C3" - default n - depends on STM32F0L0G0_HAVE_I2C3 - select STM32F0L0G0_I2C - -config STM32F0L0G0_PWR - bool "PWR" - default n - -config STM32F0L0G0_RNG - bool "RNG" - default n - depends on STM32F0L0G0_HAVE_RNG - select ARCH_HAVE_RNG - -config STM32F0L0G0_SDIO - bool "SDIO" - default n - depends on STM32F0L0G0_HAVE_SDIO - select ARCH_HAVE_SDIO - select ARCH_HAVE_SDIOWAIT_WRCOMPLETE - select ARCH_HAVE_SDIO_PREFLIGHT - -config STM32F0L0G0_SPI1 - bool "SPI1" - default n - select SPI - select STM32F0L0G0_SPI - -config STM32F0L0G0_SPI2 - bool "SPI2" - default n - depends on STM32F0L0G0_HAVE_SPI2 - select SPI - select STM32F0L0G0_SPI - -config STM32F0L0G0_SPI3 - bool "SPI3" - default n - depends on STM32F0L0G0_HAVE_SPI3 - select SPI - select STM32F0L0G0_SPI - -config STM32F0L0G0_SYSCFG - bool "SYSCFG" - default y - -config STM32F0L0G0_TIM1 - bool "TIM1" - default n - depends on STM32F0L0G0_HAVE_TIM1 - select STM32F0L0G0_TIM - -config STM32F0L0G0_TIM2 - bool "TIM2" - default n - depends on STM32F0L0G0_HAVE_TIM2 - select STM32F0L0G0_TIM - -config STM32F0L0G0_TIM3 - bool "TIM3" - default n - depends on STM32F0L0G0_HAVE_TIM3 - select STM32F0L0G0_TIM - -config STM32F0L0G0_TIM6 - bool "TIM6" - default n - depends on STM32F0L0G0_HAVE_TIM6 - select STM32F0L0G0_TIM - -config STM32F0L0G0_TIM7 - bool "TIM7" - default n - depends on STM32F0L0G0_HAVE_TIM7 - select STM32F0L0G0_TIM - -config STM32F0L0G0_TIM14 - bool "TIM14" - default n - depends on STM32F0L0G0_HAVE_TIM14 - select STM32F0L0G0_TIM - -config STM32F0L0G0_TIM15 - bool "TIM15" - default n - depends on STM32F0L0G0_HAVE_TIM15 - select STM32F0L0G0_TIM - -config STM32F0L0G0_TIM16 - bool "TIM16" - default n - depends on STM32F0L0G0_HAVE_TIM16 - select STM32F0L0G0_TIM - -config STM32F0L0G0_TIM17 - bool "TIM17" - default n - depends on STM32F0L0G0_HAVE_TIM17 - select STM32F0L0G0_TIM - -config STM32F0L0G0_TSC - bool "TSC" - default n - depends on STM32F0L0G0_HAVE_TSC - -config STM32F0L0G0_USART1 - bool "USART1" - default n - select STM32F0L0G0_USART - -config STM32F0L0G0_USART2 - bool "USART2" - default n - select STM32F0L0G0_USART - -config STM32F0L0G0_USART3 - bool "USART3" - default n - depends on STM32F0L0G0_HAVE_USART3 - select STM32F0L0G0_USART - -config STM32F0L0G0_USART4 - bool "USART4" - default n - depends on STM32F0L0G0_HAVE_USART4 - select STM32F0L0G0_USART - -config STM32F0L0G0_USART5 - bool "USART5" - default n - depends on STM32F0L0G0_HAVE_USART5 - select STM32F0L0G0_USART - -config STM32F0L0G0_USART6 - bool "USART6" - default n - depends on STM32F0L0G0_HAVE_USART6 - select STM32F0L0G0_USART - -config STM32F0L0G0_USART7 - bool "USART7" - default n - depends on STM32F0L0G0_HAVE_USART7 - select STM32F0L0G0_USART - -config STM32F0L0G0_USART8 - bool "USART8" - default n - depends on STM32F0L0G0_HAVE_USART8 - select STM32F0L0G0_USART - -config STM32F0L0G0_USB - bool "USB Device" - default n - depends on STM32F0L0G0_HAVE_USBDEV - select USBDEV - -config STM32F0L0G0_LCD - bool "Segment LCD" - default n - depends on STM32F0L0G0_HAVE_LCD - select USBDEV - -config STM32F0L0G0_IWDG - bool "IWDG" - default n - select WATCHDOG - -config STM32F0L0G0_WWDG - bool "WWDG" - default n - select WATCHDOG - -endmenu # STM32 Peripheral Support - -config STM32F0L0G0_COMP - bool - default n - -config STM32F0L0G0_ADC - bool - default n - -config STM32F0L0G0_DAC - bool - default n - -config STM32F0L0G0_DMA - bool - default n - -config STM32F0L0G0_SPI - bool - -config STM32F0L0G0_SPI_DMA - bool - default n - -config STM32F0L0G0_I2C - bool - default n - -config STM32F0L0G0_CAN - bool - default n - -config STM32F0L0G0_PWM - bool - default n - -config STM32F0L0G0_USART - bool - default n - -config STM32F0L0G0_TIM - bool - default n - -config STM32F0L0G0_FDCAN - bool - default n - -config STM32F0L0G0_SERIALDRIVER - bool - default n - -config STM32F0L0G0_1WIREDRIVER - bool - default n - -menu "Timer Configuration" - -config STM32F0L0G0_TIM1_PULSECOUNT - bool "TIM1 pulse count" - default n - depends on STM32F0L0G0_TIM1 - select ARCH_HAVE_PULSECOUNT - select PULSECOUNT - ---help--- - Reserve timer 1 for use by the pulse count driver. - - Timer devices may be used for different purposes. If STM32F0L0G0_TIM1 - is defined then this option may also be defined to indicate that TIM1 is - intended to generate a fixed number of output pulses. - -config STM32F0L0G0_TIM1_PWM - bool "TIM1 PWM" - default n - depends on STM32F0L0G0_TIM1 && !STM32F0L0G0_TIM1_PULSECOUNT - select STM32F0L0G0_PWM - ---help--- - Reserve timer 1 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If - STM32F0L0G0_TIM1 is defined then this option may also be defined to - indicate that the timer is intended to be used for pulsed output modulation. - - Valid channel modes: - - 0 -> PWM Mode 1 - 1 -> PWM Mode 2 - 2 -> Combined PWM mode 1 - 3 -> Combined PWM mode 2 - 4 -> Asymmetric PWM mode 1 - 5 -> Asymmetric PWM mode 2 - -if STM32F0L0G0_TIM1_PWM - -config STM32F0L0G0_TIM1_MODE - int "TIM1 Mode" - default 0 - range 0 4 - ---help--- - Specifies the timer mode: - - 0 -> Upcounting mode - 1 -> Downcounting mode - 2 -> Center-aligned mode 1 - 3 -> Center-aligned mode 2 - 4 -> Center-aligned mode 3 - -if STM32F0L0G0_PWM_MULTICHAN - -config STM32F0L0G0_TIM1_CHANNEL1 - bool "TIM1 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32F0L0G0_TIM1_CHANNEL1 - -config STM32F0L0G0_TIM1_CH1MODE - int "TIM1 Channel 1 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -config STM32F0L0G0_TIM1_CH1OUT - bool "TIM1 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -config STM32F0L0G0_TIM1_CH1NOUT - bool "TIM1 Channel 1 Complementary Output" - default n - depends on STM32F0L0G0_TIM1_CH1OUT - ---help--- - Enables channel 1 complementary output. - -endif # STM32F0L0G0_TIM1_CHANNEL1 - -config STM32F0L0G0_TIM1_CHANNEL2 - bool "TIM1 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32F0L0G0_TIM1_CHANNEL2 - -config STM32F0L0G0_TIM1_CH2MODE - int "TIM1 Channel 2 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -config STM32F0L0G0_TIM1_CH2OUT - bool "TIM1 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -config STM32F0L0G0_TIM1_CH2NOUT - bool "TIM1 Channel 2 Complementary Output" - default n - depends on STM32F0L0G0_TIM1_CH2OUT - ---help--- - Enables channel 2 complementary output. - -endif # STM32F0L0G0_TIM1_CHANNEL2 - -config STM32F0L0G0_TIM1_CHANNEL3 - bool "TIM1 Channel 3" - default n - ---help--- - Enables channel 3. - -if STM32F0L0G0_TIM1_CHANNEL3 - -config STM32F0L0G0_TIM1_CH3MODE - int "TIM1 Channel 3 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -config STM32F0L0G0_TIM1_CH3OUT - bool "TIM1 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -config STM32F0L0G0_TIM1_CH3NOUT - bool "TIM1 Channel 3 Complementary Output" - default n - depends on STM32F0L0G0_TIM1_CH3OUT - ---help--- - Enables channel 3 complementary output. - -endif # STM32F0L0G0_TIM1_CHANNEL3 - -config STM32F0L0G0_TIM1_CHANNEL4 - bool "TIM1 Channel 4" - default n - ---help--- - Enables channel 4. - -if STM32F0L0G0_TIM1_CHANNEL4 - -config STM32F0L0G0_TIM1_CH4MODE - int "TIM1 Channel 4 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -config STM32F0L0G0_TIM1_CH4OUT - bool "TIM1 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32F0L0G0_TIM1_CHANNEL4 - -endif # STM32F0L0G0_PWM_MULTICHAN - -if !STM32F0L0G0_PWM_MULTICHAN - -config STM32F0L0G0_TIM1_CHANNEL - int "TIM1 PWM Output Channel" - default 1 - range 1 4 - ---help--- - If TIM1 is enabled for output usage, you also need specifies the timer output - channel {1,..,4} - -config STM32F0L0G0_TIM1_CHMODE - int "TIM1 Channel Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -endif # !STM32F0L0G0_PWM_MULTICHAN - -endif # STM32F0L0G0_TIM1_PWM - -if STM32F0L0G0_TIM1_PULSECOUNT - -config STM32F0L0G0_TIM1_PULSECOUNT_CHANNEL - int "TIM1 pulse count channel" - default 1 - range 1 4 - ---help--- - Specifies the timer channel {1,..,4}. - -endif # STM32F0L0G0_TIM1_PULSECOUNT - -config STM32F0L0G0_TIM1_QE - bool "TIM1 Quadrature Encoder" - default n - depends on STM32F0L0G0_TIM1 - ---help--- - Reserve TIM1 for use by Quadrature Encoder. - -config STM32F0L0G0_TIM2_PWM - bool "TIM2 PWM" - default n - depends on STM32F0L0G0_TIM2 - select STM32F0L0G0_PWM - ---help--- - Reserve timer 2 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If - STM32F0L0G0_TIM2 is defined then THIS option may also be defined to - indicate that the timer is intended to be used for pulsed output modulation. - - Valid channel modes: - - 0 -> PWM Mode 1 - 1 -> PWM Mode 2 - 2 -> Combined PWM mode 1 - 3 -> Combined PWM mode 2 - 4 -> Asymmetric PWM mode 1 - 5 -> Asymmetric PWM mode 2 - -if STM32F0L0G0_TIM2_PWM - -config STM32F0L0G0_TIM2_MODE - int "TIM2 Mode" - default 0 - range 0 4 - ---help--- - Specifies the timer mode: - - 0 -> Upcounting mode - 1 -> Downcounting mode - 2 -> Center-aligned mode 1 - 3 -> Center-aligned mode 2 - 4 -> Center-aligned mode 3 - -if STM32F0L0G0_PWM_MULTICHAN - -config STM32F0L0G0_TIM2_CHANNEL1 - bool "TIM2 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32F0L0G0_TIM2_CHANNEL1 - -config STM32F0L0G0_TIM2_CH1MODE - int "TIM2 Channel 1 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. See STM32F0L0G0_TIM2_PWM description for available modes. - -config STM32F0L0G0_TIM2_CH1OUT - bool "TIM2 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32F0L0G0_TIM2_CHANNEL1 - -config STM32F0L0G0_TIM2_CHANNEL2 - bool "TIM2 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32F0L0G0_TIM2_CHANNEL2 - -config STM32F0L0G0_TIM2_CH2MODE - int "TIM2 Channel 2 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. See STM32F0L0G0_TIM2_PWM description for available modes. - -config STM32F0L0G0_TIM2_CH2OUT - bool "TIM2 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32F0L0G0_TIM2_CHANNEL2 - -config STM32F0L0G0_TIM2_CHANNEL3 - bool "TIM2 Channel 3" - default n - ---help--- - Enables channel 3. - -if STM32F0L0G0_TIM2_CHANNEL3 - -config STM32F0L0G0_TIM2_CH3MODE - int "TIM2 Channel 3 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. See STM32F0L0G0_TIM2_PWM description for available modes. - -config STM32F0L0G0_TIM2_CH3OUT - bool "TIM2 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -endif # STM32F0L0G0_TIM2_CHANNEL3 - -config STM32F0L0G0_TIM2_CHANNEL4 - bool "TIM2 Channel 4" - default n - ---help--- - Enables channel 4. - -if STM32F0L0G0_TIM2_CHANNEL4 - -config STM32F0L0G0_TIM2_CH4MODE - int "TIM2 Channel 4 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. See STM32F0L0G0_TIM2_PWM description for available modes. - -config STM32F0L0G0_TIM2_CH4OUT - bool "TIM2 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32F0L0G0_TIM2_CHANNEL4 - -endif # STM32F0L0G0_PWM_MULTICHAN - -if !STM32F0L0G0_PWM_MULTICHAN - -config STM32F0L0G0_TIM2_CHANNEL - int "TIM2 PWM Output Channel" - default 1 - range 1 4 - ---help--- - If TIM2 is enabled for PWM usage, you also need specifies the timer output - channel {1,..,4} - -config STM32F0L0G0_TIM2_CHMODE - int "TIM2 Channel Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. See STM32F0L0G0_TIM2_PWM description for available modes. - -endif # !STM32F0L0G0_PWM_MULTICHAN - -endif # STM32F0L0G0_TIM2_PWM - -config STM32F0L0G0_TIM2_QE - bool "TIM2 Quadrature Encoder" - default n - depends on STM32F0L0G0_TIM2 - ---help--- - Reserve TIM2 for use by Quadrature Encoder. - -config STM32F0L0G0_TIM3_PWM - bool "TIM3 PWM" - default n - depends on STM32F0L0G0_TIM3 - select STM32F0L0G0_PWM - ---help--- - Reserve timer 3 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If - STM32F0L0G0_TIM3 is defined then THIS option may also be defined to - indicate that the timer is intended to be used for pulsed output modulation. - - Valid channel modes: - - 0 -> PWM Mode 1 - 1 -> PWM Mode 2 - 2 -> Combined PWM mode 1 - 3 -> Combined PWM mode 2 - 4 -> Asymmetric PWM mode 1 - 5 -> Asymmetric PWM mode 2 - -if STM32F0L0G0_TIM3_PWM - -config STM32F0L0G0_TIM3_MODE - int "TIM3 Mode" - default 0 - range 0 4 - ---help--- - Specifies the timer mode: - - 0 -> Upcounting mode - 1 -> Downcounting mode - 2 -> Center-aligned mode 1 - 3 -> Center-aligned mode 2 - 4 -> Center-aligned mode 3 - -if STM32F0L0G0_PWM_MULTICHAN - -config STM32F0L0G0_TIM3_CHANNEL1 - bool "TIM3 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32F0L0G0_TIM3_CHANNEL1 - -config STM32F0L0G0_TIM3_CH1MODE - int "TIM3 Channel 1 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. See STM32F0L0G0_TIM3_PWM description for available modes. - -config STM32F0L0G0_TIM3_CH1OUT - bool "TIM3 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32F0L0G0_TIM3_CHANNEL1 - -config STM32F0L0G0_TIM3_CHANNEL2 - bool "TIM3 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32F0L0G0_TIM3_CHANNEL2 - -config STM32F0L0G0_TIM3_CH2MODE - int "TIM3 Channel 2 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. See STM32F0L0G0_TIM3_PWM description for available modes. - -config STM32F0L0G0_TIM3_CH2OUT - bool "TIM3 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32F0L0G0_TIM3_CHANNEL2 - -config STM32F0L0G0_TIM3_CHANNEL3 - bool "TIM3 Channel 3" - default n - ---help--- - Enables channel 3. - -if STM32F0L0G0_TIM3_CHANNEL3 - -config STM32F0L0G0_TIM3_CH3MODE - int "TIM3 Channel 3 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. See STM32F0L0G0_TIM3_PWM description for available modes. - -config STM32F0L0G0_TIM3_CH3OUT - bool "TIM3 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -endif # STM32F0L0G0_TIM3_CHANNEL3 - -config STM32F0L0G0_TIM3_CHANNEL4 - bool "TIM3 Channel 4" - default n - ---help--- - Enables channel 4. - -if STM32F0L0G0_TIM3_CHANNEL4 - -config STM32F0L0G0_TIM3_CH4MODE - int "TIM3 Channel 4 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. See STM32F0L0G0_TIM3_PWM description for available modes. - -config STM32F0L0G0_TIM3_CH4OUT - bool "TIM3 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32F0L0G0_TIM3_CHANNEL4 - -endif # STM32F0L0G0_PWM_MULTICHAN - -if !STM32F0L0G0_PWM_MULTICHAN - -config STM32F0L0G0_TIM3_CHANNEL - int "TIM3 PWM Output Channel" - default 1 - range 1 4 - ---help--- - If TIM3 is enabled for PWM usage, you also need specifies the timer output - channel {1,..,4} - -config STM32F0L0G0_TIM3_CHMODE - int "TIM3 Channel Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. See STM32F0L0G0_TIM3_PWM description for available modes. - -endif # !STM32F0L0G0_PWM_MULTICHAN - -endif # STM32F0L0G0_TIM3_PWM - -config STM32F0L0G0_TIM3_QE - bool "TIM3 Quadrature Encoder" - default n - depends on STM32F0L0G0_TIM3 - ---help--- - Reserve TIM3 for use by Quadrature Encoder. - -config STM32F0L0G0_TIM4_QE - bool "TIM3 Quadrature Encoder" - default n - depends on STM32F0L0G0_TIM4 - ---help--- - Reserve TIM4 for use by Quadrature Encoder. - -menu "STM32F0L0G0 QEncoder Driver" - depends on SENSORS_QENCODER - depends on STM32F0L0G0_TIM1 || STM32F0L0G0_TIM2 || STM32F0L0G0_TIM3 || STM32F0L0G0_TIM4 - -config STM32F0L0G0_TIM1_QEPSC - int "TIM1 QE pulse prescaler" - default 1 - depends on STM32F0L0G0_TIM1_QE - ---help--- - This prescaler divides the number of recorded encoder pulses, - limiting the count rate at the expense of resolution. - -config STM32F0L0G0_TIM2_QEPSC - int "TIM2 QE pulse prescaler" - default 1 - depends on STM32F0L0G0_TIM2_QE - ---help--- - This prescaler divides the number of recorded encoder pulses, - limiting the count rate at the expense of resolution. - -config STM32F0L0G0_TIM3_QEPSC - int "TIM3 QE pulse prescaler" - default 1 - depends on STM32F0L0G0_TIM3_QE - ---help--- - This prescaler divides the number of recorded encoder pulses, - limiting the count rate at the expense of resolution. - -config STM32F0L0G0_TIM4_QEPSC - int "TIM3 QE pulse prescaler" - default 1 - depends on STM32F0L0G0_TIM4_QE - ---help--- - This prescaler divides the number of recorded encoder pulses, - limiting the count rate at the expense of resolution. - -config STM32F0L0G0_QENCODER_DISABLE_EXTEND16BTIMERS - bool "Disable QEncoder timers extension from 16-bit to 32-bit" - default n - ---help--- - Disable the extension of 16-bit timers to 32-bit via interrupt-based - overflow tracking. When enabled, timers will use their native hardware - counter width (16-bit or 32-bit). This reduces interrupt overhead but - limits the position range for 16-bit timers. - -config STM32F0L0G0_QENCODER_INDEX_PIN - bool "Enable QEncoder timers support for index pin" - default n - ---help--- - Enable support for quadrature encoder index pin. The index pin can be - used to reset the encoder position to a known value when the index - pulse is detected. - -config STM32F0L0G0_QENCODER_FILTER - bool "Enable filtering on STM32F0L0G0 QEncoder input" - default y - ---help--- - Enable input filtering on quadrature encoder channels to reduce noise. - -choice - depends on STM32F0L0G0_QENCODER_FILTER - prompt "Input channel sampling frequency" - default STM32F0L0G0_QENCODER_SAMPLE_FDTS_4 - ---help--- - Select the sampling frequency for the input filter. - -config STM32F0L0G0_QENCODER_SAMPLE_FDTS - bool "fDTS" - -config STM32F0L0G0_QENCODER_SAMPLE_CKINT - bool "fCK_INT" - -config STM32F0L0G0_QENCODER_SAMPLE_FDTS_2 - bool "fDTS/2" - -config STM32F0L0G0_QENCODER_SAMPLE_FDTS_4 - bool "fDTS/4" - -config STM32F0L0G0_QENCODER_SAMPLE_FDTS_8 - bool "fDTS/8" - -config STM32F0L0G0_QENCODER_SAMPLE_FDTS_16 - bool "fDTS/16" - -config STM32F0L0G0_QENCODER_SAMPLE_FDTS_32 - bool "fDTS/32" - -endchoice - -choice - depends on STM32F0L0G0_QENCODER_FILTER - prompt "Input channel event count" - default STM32F0L0G0_QENCODER_SAMPLE_EVENT_6 - ---help--- - Select the number of consecutive events required to validate a transition. - -config STM32F0L0G0_QENCODER_SAMPLE_EVENT_1 - depends on STM32F0L0G0_QENCODER_SAMPLE_FDTS - bool "1" - -config STM32F0L0G0_QENCODER_SAMPLE_EVENT_2 - depends on STM32F0L0G0_QENCODER_SAMPLE_CKINT - bool "2" - -config STM32F0L0G0_QENCODER_SAMPLE_EVENT_4 - depends on STM32F0L0G0_QENCODER_SAMPLE_CKINT - bool "4" - -config STM32F0L0G0_QENCODER_SAMPLE_EVENT_5 - depends on STM32F0L0G0_QENCODER_SAMPLE_FDTS_16 || STM32F0L0G0_QENCODER_SAMPLE_FDTS_32 - bool "5" - -config STM32F0L0G0_QENCODER_SAMPLE_EVENT_6 - depends on !STM32F0L0G0_QENCODER_SAMPLE_FDTS && !STM32F0L0G0_QENCODER_SAMPLE_CKINT - bool "6" - -config STM32F0L0G0_QENCODER_SAMPLE_EVENT_8 - depends on !STM32F0L0G0_QENCODER_SAMPLE_FDTS - bool "8" - -endchoice - -endmenu # STM32F0L0G0 QEncoder Driver - -config STM32F0L0G0_TIM14_PWM - bool "TIM14 PWM" - default n - depends on STM32F0L0G0_TIM14 - select STM32F0L0G0_PWM - ---help--- - Reserve timer 14 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32F0L0G0_TIM14 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32F0L0G0_TIM14_PWM - -if STM32F0L0G0_PWM_MULTICHAN - -config STM32F0L0G0_TIM14_CHANNEL1 - bool "TIM14 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32F0L0G0_TIM14_CHANNEL1 - -config STM32F0L0G0_TIM14_CH1MODE - int "TIM14 Channel 1 Mode" - default 0 - range 0 1 - ---help--- - Specifies the channel mode. - -config STM32F0L0G0_TIM14_CH1OUT - bool "TIM14 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32F0L0G0_TIM14_CHANNEL1 - -endif # STM32F0L0G0_PWM_MULTICHAN - -if !STM32F0L0G0_PWM_MULTICHAN - -config STM32F0L0G0_TIM14_CHANNEL - int "TIM14 PWM Output Channel" - default 1 - range 1 1 - ---help--- - If TIM14 is enabled for PWM usage, you also need specifies the timer output - channel {1} - -config STM32F0L0G0_TIM14_CHMODE - int "TIM14 Channel Mode" - default 0 - range 0 1 - ---help--- - Specifies the channel mode. - -endif # !STM32F0L0G0_PWM_MULTICHAN - -endif # STM32F0L0G0_TIM14_PWM - -config STM32F0L0G0_TIM15_PWM - bool "TIM15 PWM" - default n - depends on STM32F0L0G0_TIM15 - select STM32F0L0G0_PWM - ---help--- - Reserve timer 15 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32F0L0G0_TIM15 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32F0L0G0_TIM15_PWM - -if STM32F0L0G0_PWM_MULTICHAN - -config STM32F0L0G0_TIM15_CHANNEL1 - bool "TIM15 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32F0L0G0_TIM15_CHANNEL1 - -config STM32F0L0G0_TIM15_CH1MODE - int "TIM15 Channel 1 Mode" - default 0 - range 0 3 - ---help--- - Specifies the channel mode. - -config STM32F0L0G0_TIM15_CH1OUT - bool "TIM15 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -config STM32F0L0G0_TIM15_CH1NOUT - bool "TIM15 Channel 1 Complementary Output" - default n - depends on STM32F0L0G0_TIM15_CH1OUT - ---help--- - Enables channel 1 complementary output. - -endif # STM32F0L0G0_TIM15_CHANNEL1 - -config STM32F0L0G0_TIM15_CHANNEL2 - bool "TIM15 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32F0L0G0_TIM15_CHANNEL2 - -config STM32F0L0G0_TIM15_CH2MODE - int "TIM15 Channel 2 Mode" - default 0 - range 0 3 - ---help--- - Specifies the channel mode. - -config STM32F0L0G0_TIM15_CH2OUT - bool "TIM15 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32F0L0G0_TIM15_CHANNEL2 - -endif # STM32F0L0G0_PWM_MULTICHAN - -if !STM32F0L0G0_PWM_MULTICHAN - -config STM32F0L0G0_TIM15_CHANNEL - int "TIM15 PWM Output Channel" - default 1 - range 1 2 - ---help--- - If TIM15 is enabled for PWM usage, you also need specifies the timer output - channel {1,2} - -config STM32F0L0G0_TIM15_CHMODE - int "TIM15 Channel Mode" - default 0 - range 0 3 - ---help--- - Specifies the channel mode. - -endif # !STM32F0L0G0_PWM_MULTICHAN - -endif # STM32F0L0G0_TIM15_PWM - -config STM32F0L0G0_TIM16_PWM - bool "TIM16 PWM" - default n - depends on STM32F0L0G0_TIM16 - select STM32F0L0G0_PWM - ---help--- - Reserve timer 16 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32F0L0G0_TIM16 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32F0L0G0_TIM16_PWM - -if STM32F0L0G0_PWM_MULTICHAN - -config STM32F0L0G0_TIM16_CHANNEL1 - bool "TIM16 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32F0L0G0_TIM16_CHANNEL1 - -config STM32F0L0G0_TIM16_CH1MODE - int "TIM16 Channel 1 Mode" - default 0 - range 0 1 - ---help--- - Specifies the channel mode. - -config STM32F0L0G0_TIM16_CH1OUT - bool "TIM16 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -config STM32F0L0G0_TIM16_CH1NOUT - bool "TIM16 Channel 1 Complementary Output" - default n - depends on STM32F0L0G0_TIM16_CH1OUT - ---help--- - Enables channel 1 complementary output. - -endif # STM32F0L0G0_TIM16_CHANNEL1 - -endif # STM32F0L0G0_PWM_MULTICHAN - -if !STM32F0L0G0_PWM_MULTICHAN - -config STM32F0L0G0_TIM16_CHANNEL - int "TIM16 PWM Output Channel" - default 1 - range 1 1 - ---help--- - If TIM16 is enabled for PWM usage, you also need specifies the timer output - channel {1} - -config STM32F0L0G0_TIM16_CHMODE - int "TIM16 Channel Mode" - default 0 - range 0 1 - ---help--- - Specifies the channel mode. - -endif # !STM32F0L0G0_PWM_MULTICHAN - -endif # STM32F0L0G0_TIM16_PWM - -config STM32F0L0G0_TIM17_PWM - bool "TIM17 PWM" - default n - depends on STM32F0L0G0_TIM17 - select STM32F0L0G0_PWM - ---help--- - Reserve timer 17 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32F0L0G0_TIM17 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32F0L0G0_TIM17_PWM - -if STM32F0L0G0_PWM_MULTICHAN - -config STM32F0L0G0_TIM17_CHANNEL1 - bool "TIM17 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32F0L0G0_TIM17_CHANNEL1 - -config STM32F0L0G0_TIM17_CH1MODE - int "TIM17 Channel 1 Mode" - default 0 - range 0 1 - ---help--- - Specifies the channel mode. - -config STM32F0L0G0_TIM17_CH1OUT - bool "TIM17 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -config STM32F0L0G0_TIM17_CH1NOUT - bool "TIM17 Channel 1 Complementary Output" - default n - depends on STM32F0L0G0_TIM17_CH1OUT - ---help--- - Enables channel 1 complementary output. - -endif # STM32F0L0G0_TIM17_CHANNEL1 - -endif # STM32F0L0G0_PWM_MULTICHAN - -if !STM32F0L0G0_PWM_MULTICHAN - -config STM32F0L0G0_TIM17_CHANNEL - int "TIM17 PWM Output Channel" - default 1 - range 1 1 - ---help--- - If TIM17 is enabled for PWM usage, you also need specifies the timer output - channel {1} - -config STM32F0L0G0_TIM17_CHMODE - int "TIM17 Channel Mode" - default 0 - range 0 1 - ---help--- - Specifies the channel mode. - -endif # !STM32F0L0G0_PWM_MULTICHAN - -endif # STM32F0L0G0_TIM17_PWM - -config STM32F0L0G0_PWM_MULTICHAN - bool "PWM Multiple Output Channels" - default n - depends on STM32F0L0G0_PWM - ---help--- - Specifies that the PWM driver supports multiple output channels per timer. - -config STM32F0L0G0_TIM1_ADC - bool "TIM1 ADC" - default n - depends on STM32F0L0G0_TIM1 && STM32F0L0G0_ADC - ---help--- - Reserve timer 1 for use by ADC - -choice - prompt "Select TIM1 ADC channel" - default STM32F0L0G0_TIM1_ADC1 - depends on STM32F0L0G0_TIM1_ADC - -config STM32F0L0G0_TIM1_ADC1 - bool "TIM1 ADC channel 1" - depends on STM32F0L0G0_ADC1 - select STM32F0L0G0_HAVE_ADC1_TIMER - ---help--- - Reserve TIM1 to trigger ADC1 - -endchoice - -config STM32F0L0G0_TIM2_ADC - bool "TIM2 ADC" - default n - depends on STM32F0L0G0_TIM2 && STM32F0L0G0_ADC - ---help--- - Reserve timer 1 for use by ADC - -choice - prompt "Select TIM2 ADC channel" - default STM32F0L0G0_TIM2_ADC1 - depends on STM32F0L0G0_TIM2_ADC - -config STM32F0L0G0_TIM2_ADC1 - bool "TIM2 ADC channel 1" - depends on STM32F0L0G0_ADC1 - select STM32F0L0G0_HAVE_ADC1_TIMER - ---help--- - Reserve TIM2 to trigger ADC1 - -endchoice - -config STM32F0L0G0_TIM3_ADC - bool "TIM3 ADC" - default n - depends on STM32F0L0G0_TIM3 && STM32F0L0G0_ADC - ---help--- - Reserve timer 1 for use by ADC - -choice - prompt "Select TIM3 ADC channel" - default STM32F0L0G0_TIM3_ADC1 - depends on STM32F0L0G0_TIM3_ADC - -config STM32F0L0G0_TIM3_ADC1 - bool "TIM3 ADC channel 1" - depends on STM32F0L0G0_ADC1 - select STM32F0L0G0_HAVE_ADC1_TIMER - ---help--- - Reserve TIM3 to trigger ADC1 - -endchoice - -config STM32F0L0G0_TIM15_ADC - bool "TIM15 ADC" - default n - depends on STM32F0L0G0_TIM15 && STM32F0L0G0_ADC - ---help--- - Reserve timer 1 for use by ADC - -choice - prompt "Select TIM15 ADC channel" - default STM32F0L0G0_TIM15_ADC1 - depends on STM32F0L0G0_TIM15_ADC - -config STM32F0L0G0_TIM15_ADC1 - bool "TIM15 ADC channel 1" - depends on STM32F0L0G0_ADC1 - select STM32F0L0G0_HAVE_ADC1_TIMER - ---help--- - Reserve TIM15 to trigger ADC1 - -endchoice - -config STM32F0L0G0_HAVE_ADC1_TIMER - bool - -config STM32F0L0G0_ADC1_SAMPLE_FREQUENCY - int "ADC1 Sampling Frequency" - default 100 - depends on STM32F0L0G0_HAVE_ADC1_TIMER - ---help--- - ADC1 sampling frequency. Default: 100Hz - -config STM32F0L0G0_ADC1_TIMTRIG - int "ADC1 Timer Trigger" - default 0 - range 0 5 - depends on STM32F0L0G0_HAVE_ADC1_TIMER - ---help--- - Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO 5:TRGO2. - This option must match with the MCU's supported EXTSEL. - -endmenu # Timer Configuration - -menu "FDCAN driver configuration" - depends on STM32F0L0G0_FDCAN - -choice - prompt "FDCAN character driver or SocketCAN support" - default STM32F0L0G0_FDCAN_CHARDRIVER - -config STM32F0L0G0_FDCAN_CHARDRIVER - bool "STM32 FDCAN character driver support" - select ARCH_HAVE_CAN_ERRORS - select CAN - -config STM32F0L0G0_FDCAN_SOCKET - bool "STM32 FDCAN SocketCAN support" - select NET_CAN_HAVE_ERRORS - select NET_CAN_HAVE_CANFD - -endchoice # FDCAN character driver or SocketCAN support - -config STM32F0L0G0_FDCAN_REGDEBUG - bool "CAN Register level debug" - depends on DEBUG_CAN_INFO - default n - ---help--- - Output detailed register-level CAN device debug information. - Requires also CONFIG_DEBUG_CAN_INFO. - -config STM32F0L0G0_FDCAN_QUEUE_MODE - bool "FDCAN QUEUE mode (vs FIFO mode)" - default n - -menu "FDCAN1 device driver options" - depends on STM32F0L0G0_FDCAN1 - -choice - prompt "FDCAN1 frame format" - default STM32F0L0G0_FDCAN1_ISO11898_1 - -config STM32F0L0G0_FDCAN1_ISO11898_1 - bool "ISO11898-1" - ---help--- - Enable ISO11898-1 frame format - -config STM32F0L0G0_FDCAN1_NONISO_FORMAT - bool "Non ISO" - ---help--- - Enable Non ISO, Bosch CAN FD Specification V1.0 - -endchoice # FDCAN1 frame format - -choice - prompt "FDCAN1 mode" - default STM32F0L0G0_FDCAN1_CLASSIC - -config STM32F0L0G0_FDCAN1_CLASSIC - bool "Classic CAN" - ---help--- - Enable Classic CAN mode - -config STM32F0L0G0_FDCAN1_FD - bool "CAN FD" - depends on CAN_FD || NET_CAN_CANFD - ---help--- - Enable CAN FD mode - -config STM32F0L0G0_FDCAN1_FD_BRS - bool "CAN FD with fast bit rate switching" - depends on CAN_FD || NET_CAN_CANFD - ---help--- - Enable CAN FD mode with fast bit rate switching mode. - -endchoice # FDCAN1 mode - -config STM32F0L0G0_FDCAN1_LOOPBACK - bool "Enable FDCAN1 loopback mode" - default n - ---help--- - Enable the FDCAN1 local loopback mode for testing purposes. - -comment "Nominal Bit Timing" - -config STM32F0L0G0_FDCAN1_BITRATE - int "FDCAN bitrate" - default 500000 - range 0 1000000 - ---help--- - FDCAN1 bitrate in bits per second. Required if STM32F0L0G0_FDCAN1 is defined. - -config STM32F0L0G0_FDCAN1_NTSEG1 - int "FDCAN1 NTSEG1 (PropSeg + PhaseSeg1)" - default 6 - range 1 256 - ---help--- - The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). - -config STM32F0L0G0_FDCAN1_NTSEG2 - int "FDCAN1 NTSEG2 (PhaseSeg2)" - default 7 - range 1 128 - ---help--- - The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). - -config STM32F0L0G0_FDCAN1_NSJW - int "FDCAN1 synchronization jump width" - default 1 - range 1 128 - ---help--- - The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). - -comment "Data Bit Timing" - depends on CAN_FD && STM32F0L0G0_FDCAN1_FD_BRS - -config STM32F0L0G0_FDCAN1_DBITRATE - int "FDCAN1 data bitrate" - default 2000000 - depends on CAN_FD && STM32F0L0G0_FDCAN1_FD_BRS - ---help--- - FDCAN1 bitrate in bits per second. Required if operating in FD mode with bit rate switching (BRS). - -config STM32F0L0G0_FDCAN1_DTSEG1 - int "FDCAN1 DTSEG1 (PropSeg + PhaseSeg1 of data phase)" - default 4 - range 1 31 - depends on CAN_FD && STM32F0L0G0_FDCAN1_FD_BRS - ---help--- - The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). - -config STM32F0L0G0_FDCAN1_DTSEG2 - int "FDCAN1 DTSEG2 (PhaseSeg2 of data phase)" - default 4 - range 1 15 - depends on CAN_FD && STM32F0L0G0_FDCAN1_FD_BRS - ---help--- - The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). - -config STM32F0L0G0_FDCAN1_DSJW - int "FDCAN1 fast synchronization jump width" - default 2 - range 1 15 - depends on CAN_FD && STM32F0L0G0_FDCAN1_FD_BRS - ---help--- - The duration of a synchronization jump is Tcan_clk x DSJW. - -endmenu # FDCAN1 device driver options - -endmenu # "FDCAN driver configuration" - -menu "U[S]ART Configuration" - depends on STM32F0L0G0_USART - -comment "U[S]ART Device Configuration" - -choice - prompt "USART1 Driver Configuration" - default STM32F0L0G0_USART1_SERIALDRIVER - depends on STM32F0L0G0_USART1 - -config STM32F0L0G0_USART1_SERIALDRIVER - bool "Standard serial driver" - select USART1_SERIALDRIVER - select ARCH_HAVE_SERIAL_TERMIOS - select STM32F0L0G0_SERIALDRIVER - -config STM32F0L0G0_USART1_1WIREDRIVER - bool "1-Wire driver" - select STM32F0L0G0_1WIREDRIVER - -endchoice # USART1 Driver Configuration - -if STM32F0L0G0_USART1_SERIALDRIVER - -config USART1_RXFIFO_THRES - int "USART1 Rx FIFO Threshold" - default 3 - range 0 5 - depends on STM32F0L0G0_HAVE_IP_USART_V2 - ---help--- - Select the Rx FIFO threshold: - - 0 -> 1/8 full - 1 -> 1/4 full - 2 -> 1/2 full - 3 -> 3/4 full - 4 -> 7/8 full - 5 -> Full - - Higher values mean lower interrupt rates and better CPU performance. - Lower values may be needed at high BAUD rates to prevent Rx data - overrun errors. - -config USART1_RS485 - bool "RS-485 on USART1" - default n - ---help--- - Enable RS-485 interface on USART1. Your board config will have to - provide GPIO_USART1_RS485_DIR pin definition. - -config USART1_RS485_DIR_POLARITY - int "USART1 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on USART1_RS485 - ---help--- - Polarity of DIR pin for RS-485 on USART1. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -endif # STM32F0L0G0_USART1_SERIALDRIVER - -choice - prompt "USART2 Driver Configuration" - default STM32F0L0G0_USART2_SERIALDRIVER - depends on STM32F0L0G0_USART2 - -config STM32F0L0G0_USART2_SERIALDRIVER - bool "Standard serial driver" - select USART2_SERIALDRIVER - select ARCH_HAVE_SERIAL_TERMIOS - select STM32F0L0G0_SERIALDRIVER - -config STM32F0L0G0_USART2_1WIREDRIVER - bool "1-Wire driver" - select STM32F0L0G0_1WIREDRIVER - -endchoice # USART2 Driver Configuration - -if STM32F0L0G0_USART2_SERIALDRIVER - -config USART2_RXFIFO_THRES - int "USART2 Rx FIFO Threshold" - default 3 - range 0 5 - depends on STM32F0L0G0_HAVE_IP_USART_V2 - ---help--- - Select the Rx FIFO threshold: - - 0 -> 1/8 full - 1 -> 1/4 full - 2 -> 1/2 full - 3 -> 3/4 full - 4 -> 7/8 full - 5 -> Full - - Higher values mean lower interrupt rates and better CPU performance. - Lower values may be needed at high BAUD rates to prevent Rx data - overrun errors. - -config USART2_RS485 - bool "RS-485 on USART2" - default n - ---help--- - Enable RS-485 interface on USART2. Your board config will have to - provide GPIO_USART2_RS485_DIR pin definition. - -config USART2_RS485_DIR_POLARITY - int "USART2 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on USART2_RS485 - ---help--- - Polarity of DIR pin for RS-485 on USART2. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -endif # STM32F0L0G0_USART2_SERIALDRIVER - -choice - prompt "USART3 Driver Configuration" - default STM32F0L0G0_USART3_SERIALDRIVER - depends on STM32F0L0G0_USART3 - -config STM32F0L0G0_USART3_SERIALDRIVER - bool "Standard serial driver" - select USART3_SERIALDRIVER - select ARCH_HAVE_SERIAL_TERMIOS - select STM32F0L0G0_SERIALDRIVER - -config STM32F0L0G0_USART3_1WIREDRIVER - bool "1-Wire driver" - select STM32F0L0G0_1WIREDRIVER - -endchoice # USART3 Driver Configuration - -if STM32F0L0G0_USART3_SERIALDRIVER - -config USART3_RS485 - bool "RS-485 on USART3" - default n - ---help--- - Enable RS-485 interface on USART3. Your board config will have to - provide GPIO_USART3_RS485_DIR pin definition. - -config USART3_RS485_DIR_POLARITY - int "USART3 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on USART3_RS485 - ---help--- - Polarity of DIR pin for RS-485 on USART3. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -endif # STM32F0L0G0_USART3_SERIALDRIVER - -choice - prompt "USART4 Driver Configuration" - default STM32F0L0G0_USART4_SERIALDRIVER - depends on STM32F0L0G0_USART4 - -config STM32F0L0G0_USART4_SERIALDRIVER - bool "Standard serial driver" - select USART4_SERIALDRIVER - select ARCH_HAVE_SERIAL_TERMIOS - select STM32F0L0G0_SERIALDRIVER - -config STM32F0L0G0_USART4_1WIREDRIVER - bool "1-Wire driver" - select STM32F0L0G0_1WIREDRIVER - -endchoice # USART4 Driver Configuration - -if STM32F0L0G0_USART4_SERIALDRIVER - -config USART4_RS485 - bool "RS-485 on USART4" - default n - ---help--- - Enable RS-485 interface on USART4. Your board config will have to - provide GPIO_USART4_RS485_DIR pin definition. - -config USART4_RS485_DIR_POLARITY - int "USART4 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on USART4_RS485 - ---help--- - Polarity of DIR pin for RS-485 on USART4. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -endif # STM32F0L0G0_USART4_SERIALDRIVER - -choice - prompt "USART5 Driver Configuration" - default STM32F0L0G0_USART5_SERIALDRIVER - depends on STM32F0L0G0_USART5 - -config STM32F0L0G0_USART5_SERIALDRIVER - bool "Standard serial driver" - select USART5_SERIALDRIVER - select ARCH_HAVE_SERIAL_TERMIOS - select STM32F0L0G0_SERIALDRIVER - -config STM32F0L0G0_USART5_1WIREDRIVER - bool "1-Wire driver" - select STM32F0L0G0_1WIREDRIVER - -endchoice # USART5 Driver Configuration - -if STM32F0L0G0_USART5_SERIALDRIVER - -config USART5_RS485 - bool "RS-485 on USART5" - default n - ---help--- - Enable RS-485 interface on USART5. Your board config will have to - provide GPIO_USART5_RS485_DIR pin definition. - -config USART5_RS485_DIR_POLARITY - int "USART5 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on USART5_RS485 - ---help--- - Polarity of DIR pin for RS-485 on USART5. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -endif # STM32F0L0G0_USART5_SERIALDRIVER - -choice - prompt "USART6 Driver Configuration" - default STM32F0L0G0_USART6_SERIALDRIVER - depends on STM32F0L0G0_USART6 - -config STM32F0L0G0_USART6_SERIALDRIVER - bool "Standard serial driver" - select USART6_SERIALDRIVER - select ARCH_HAVE_SERIAL_TERMIOS - select STM32F0L0G0_SERIALDRIVER - -config STM32F0L0G0_USART6_1WIREDRIVER - bool "1-Wire driver" - select STM32F0L0G0_1WIREDRIVER - -endchoice # USART6 Driver Configuration - -if STM32F0L0G0_USART6_SERIALDRIVER - -config USART6_RS485 - bool "RS-485 on USART6" - default n - ---help--- - Enable RS-485 interface on USART6. Your board config will have to - provide GPIO_USART6_RS485_DIR pin definition. - -config USART6_RS485_DIR_POLARITY - int "USART6 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on USART6_RS485 - ---help--- - Polarity of DIR pin for RS-485 on USART6. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -endif # STM32F0L0G0_USART6_SERIALDRIVER - -choice - prompt "USART7 Driver Configuration" - default STM32F0L0G0_USART7_SERIALDRIVER - depends on STM32F0L0G0_USART7 - -config STM32F0L0G0_USART7_SERIALDRIVER - bool "Standard serial driver" - select USART7_SERIALDRIVER - select ARCH_HAVE_SERIAL_TERMIOS - select STM32F0L0G0_SERIALDRIVER - -config STM32F0L0G0_USART7_1WIREDRIVER - bool "1-Wire driver" - select STM32F0L0G0_1WIREDRIVER - -endchoice # USART7 Driver Configuration - -if STM32F0L0G0_USART7_SERIALDRIVER - -config USART7_RS485 - bool "RS-485 on USART7" - default n - ---help--- - Enable RS-485 interface on USART7. Your board config will have to - provide GPIO_USART7_RS485_DIR pin definition. - -config USART7_RS485_DIR_POLARITY - int "USART7 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on USART7_RS485 - ---help--- - Polarity of DIR pin for RS-485 on USART7. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -endif # STM32F0L0G0_USART7_SERIALDRIVER - -choice - prompt "USART8 Driver Configuration" - default STM32F0L0G0_USART8_SERIALDRIVER - depends on STM32F0L0G0_USART8 - -config STM32F0L0G0_USART8_SERIALDRIVER - bool "Standard serial driver" - select USART8_SERIALDRIVER - select ARCH_HAVE_SERIAL_TERMIOS - select STM32F0L0G0_SERIALDRIVER - -config STM32F0L0G0_USART8_1WIREDRIVER - bool "1-Wire driver" - select STM32F0L0G0_1WIREDRIVER - -endchoice # USART8 Driver Configuration - -if STM32F0L0G0_USART8_SERIALDRIVER - -config USART8_RS485 - bool "RS-485 on USART8" - default n - ---help--- - Enable RS-485 interface on USART8. Your board config will have to - provide GPIO_USART8_RS485_DIR pin definition. - -config USART8_RS485_DIR_POLARITY - int "USART8 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on USART8_RS485 - ---help--- - Polarity of DIR pin for RS-485 on USART8. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -endif # STM32F0L0G0_USART8_SERIALDRIVER - -menu "Serial Driver Configuration" - depends on STM32F0L0G0_SERIALDRIVER - -config STM32F0L0G0_SERIAL_DISABLE_REORDERING - bool "Disable reordering of ttySx devices." - default n - ---help--- - NuttX per default reorders the serial ports (/dev/ttySx) so that the - console is always on /dev/ttyS0. If more than one UART is in use this - can, however, have the side-effect that all port mappings - (hardware USART1 -> /dev/ttyS0) change if the console is moved to another - UART. This is in particular relevant if a project uses the USB console - in some boards and a serial console in other boards, but does not - want the side effect of having all serial port names change when just - the console is moved from serial to USB. - -config STM32F0L0G0_USART_SINGLEWIRE - bool "Single Wire Support" - default n - depends on STM32F0L0G0_USART - ---help--- - Enable single wire UART support. The option enables support for the - TIOCSSINGLEWIRE ioctl in the STM32F0 serial driver. - -endmenu # Serial Driver Configuration - -if PM - -config STM32F0L0G0_PM_SERIAL_ACTIVITY - int "PM serial activity" - default 10 - ---help--- - PM activity reported to power management logic on every serial - interrupt. - -endif # PM - -endmenu # U[S]ART Configuration - -menu "ADC Configuration" - depends on STM32F0L0G0_ADC - -config STM32F0L0G0_ADC1_RESOLUTION - int "ADC1 resolution" - depends on STM32F0L0G0_ADC1 - default 0 - range 0 3 - ---help--- - ADC1 resolution. 0 - 12 bit, 1 - 10 bit, 2 - 8 bit, 3 - 6 bit - -config STM32F0L0G0_ADC_MAX_SAMPLES - int "The maximum number of channels that can be sampled" - default 16 if STM32F0L0G0_ADC1_DMA - default 1 if !STM32F0L0G0_ADC1_DMA - ---help--- - The maximum number of samples which can be handled without - overrun depends on various factors. This is the user's - responsibility to correctly select this value. - Since the interface to update the sampling time is available - for all supported devices, the user can change the default - values in the board initialization logic and avoid ADC overrun. - -config STM32F0L0G0_ADC_NO_STARTUP_CONV - bool "Do not start conversion when opening ADC device" - default n - ---help--- - Do not start conversion when opening ADC device. - -config STM32F0L0G0_ADC_NOIRQ - bool "Do not use default ADC interrupts" - default n - ---help--- - Do not use default ADC interrupts handlers. - -config STM32F0L0G0_ADC_LL_OPS - bool "ADC low-level operations" - default n - ---help--- - Enable low-level ADC ops. - -config STM32F0L0G0_ADC_CHANGE_SAMPLETIME - bool "ADC sample time configuration" - default n - depends on STM32F0L0G0_ADC_LL_OPS - ---help--- - Enable ADC sample time configuration (SMPRx registers). - -config STM32F0L0G0_ADC1_DMA - bool "ADC1 DMA" - depends on STM32F0L0G0_ADC1 && STM32F0L0G0_HAVE_ADC1_DMA - default n - ---help--- - If DMA is selected, then the ADC may be configured to support - DMA transfer, which is necessary if multiple channels are read - or if very high trigger frequencies are used. - -config STM32F0L0G0_ADC1_DMA_CFG - int "ADC1 DMA configuration" - depends on STM32F0L0G0_ADC1_DMA && !STM32F0L0G0_HAVE_IP_ADC_V1_BASIC - range 0 1 - default 0 - ---help--- - 0 - ADC1 DMA in One Shot Mode, 1 - ADC1 DMA in Circular Mode - -config STM32F0L0G0_ADC_OVERSAMPLE - bool "Enable ADC hardware oversampling support" - depends on STM32F0L0G0_ADC1 && STM32F0L0G0_HAVE_ADC_OVERSAMPLE - default n - ---help--- - Enable the on-chip ADC oversampling/accumulation block (CFGR2.OVSE). - Only STM32G0 and STM32L0 series include this hardware block. - -if STM32F0L0G0_ADC_OVERSAMPLE - -config STM32F0L0G0_ADC_TOVS - bool "Enable triggered oversampling (CFGR2.TOVS)" - default n - ---help--- - If set, oversampling will only occur when a trigger event occurs. - If not set, oversampling occurs continuously (TOVS=0). - -config STM32F0L0G0_ADC_OVSR - int "Oversampling ratio (CFGR2.OVSR)" - default 0 - range 0 7 - ---help--- - Sets the oversampling ratio as 2^(OVSR+1). For example: - 0 -> 2× - 1 -> 4× - 2 -> 8× - ... - 7 -> 256× - -config STM32F0L0G0_ADC_OVSS - int "Oversampling right-shift bits (CFGR2.OVSS)" - default 0 - range 0 8 - ---help--- - Sets how many bits the accumulated result is right-shifted. - Max of 8-bits. - -endif # STM32F0L0G0_ADC_OVERSAMPLE - -config STM32F0L0G0_ADC1_DMA_BATCH - int "ADC1 DMA number of conversions" - depends on STM32F0L0G0_ADC1 && STM32F0L0G0_ADC1_DMA - default 1 - ---help--- - This option allows you to select the number of regular group conversions - that will trigger a DMA callback transerring data to the upper-half driver. - By default, this value is 1, which means that data is transferred after - each group conversion. - -config STM32F0L0G0_ADC1_EXTSEL - bool "ADC1 external trigger for regular group" - depends on STM32F0L0G0_ADC1 && !STM32F0L0G0_HAVE_ADC1_TIMER - default n - ---help--- - Enable EXTSEL for ADC1. - -config STM32F0L0G0_ADC1_CONTINUOUS - bool "Enable ADC1 Continuous Conversion Mode" - default n - depends on STM32F0L0G0_ADC1 - ---help--- - If enabled, the ADC will operate in continuous conversion mode. - Otherwise, it will perform single conversions. - Note: Continuous and discontinuous mode cannot be defined at - the same time - -endmenu # ADC Configuration - -menu "SPI Configuration" - depends on STM32F0L0G0_SPI - -config STM32F0L0G0_SPI_INTERRUPTS - bool "Interrupt driver SPI" - default n - ---help--- - Select to enable interrupt driven SPI support. Non-interrupt-driven, - poll-waiting is recommended if the interrupt rate would be to high in - the interrupt driven case. - -config STM32F0L0G0_SPI1_DMA - bool "SPI1 DMA" - default n - depends on STM32F0L0G0_SPI1 && !STM32F0L0G0_SPI_INTERRUPTS - select STM32F0L0G0_SPI_DMA - ---help--- - Use DMA to improve SPI1 transfer performance. Cannot be used with STM32F0L0G0_SPI_INTERRUPT. - -config STM32F0L0G0_SPI2_DMA - bool "SPI2 DMA" - default n - depends on STM32F0L0G0_SPI2 && !STM32F0L0G0_SPI_INTERRUPTS - select STM32F0L0G0_SPI_DMA - ---help--- - Use DMA to improve SPI2 transfer performance. Cannot be used with STM32F0L0G0_SPI_INTERRUPT. - -config STM32F0L0G0_SPI3_DMA - bool "SPI3 DMA" - default n - depends on STM32F0L0G0_SPI3 && !STM32F0L0G0_SPI_INTERRUPTS - select STM32F0L0G0_SPI_DMA - ---help--- - Use DMA to improve SPI3 transfer performance. Cannot be used with STM32F0L0G0_SPI_INTERRUPT. - -config STM32F0L0G0_SPI1_COMMTYPE - int "SPI1 Operation mode" - default 0 - range 0 3 - depends on STM32F0L0G0_SPI1 - ---help--- - Select full-duplex (0), simplex tx (1), simplex rx (2) or half-duplex (3) - -config STM32F0L0G0_SPI2_COMMTYPE - int "SPI2 Operation mode" - default 0 - range 0 3 - depends on STM32F0L0G0_SPI2 - ---help--- - Select full-duplex (0), simplex tx (1), simplex rx (2) or half-duplex (3) - -config STM32F0L0G0_SPI3_COMMTYPE - int "SPI3 Operation mode" - default 0 - range 0 3 - depends on STM32F0L0G0_SPI3 - ---help--- - Select full-duplex (0), simplex tx (1), simplex rx (2) or half-duplex (3) - -endmenu # SPI Configuration - -menu "I2C Configuration" - depends on STM32F0L0G0_I2C - -config STM32F0L0G0_I2C_DYNTIMEO - bool "Use dynamic timeouts" - default n - depends on STM32F0L0G0_I2C - -config STM32F0L0G0_I2C_DYNTIMEO_USECPERBYTE - int "Timeout Microseconds per Byte" - default 500 - depends on STM32F0L0G0_I2C_DYNTIMEO - -config STM32F0L0G0_I2C_DYNTIMEO_STARTSTOP - int "Timeout for Start/Stop (Milliseconds)" - default 1000 - depends on STM32F0L0G0_I2C_DYNTIMEO - -config STM32F0L0G0_I2CTIMEOSEC - int "Timeout seconds" - default 0 - depends on STM32F0L0G0_I2C - -config STM32F0L0G0_I2CTIMEOMS - int "Timeout Milliseconds" - default 500 - depends on STM32F0L0G0_I2C && !STM32F0L0G0_I2C_DYNTIMEO - -config STM32F0L0G0_I2CTIMEOTICKS - int "Timeout for Done and Stop (ticks)" - default 500 - depends on STM32F0L0G0_I2C && !STM32F0L0G0_I2C_DYNTIMEO - -endmenu #I2C Configuration diff --git a/arch/arm/src/stm32f0l0g0/Make.defs b/arch/arm/src/stm32f0l0g0/Make.defs deleted file mode 100644 index e4ab1438876cc..0000000000000 --- a/arch/arm/src/stm32f0l0g0/Make.defs +++ /dev/null @@ -1,121 +0,0 @@ -############################################################################ -# arch/arm/src/stm32f0l0g0/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include armv6-m/Make.defs - -CHIP_CSRCS = stm32_start.c stm32_gpio.c stm32_exti_gpio.c stm32_irq.c -CHIP_CSRCS += stm32_lowputc.c stm32_serial.c stm32_rcc.c stm32_lsi.c stm32_uid.c - -ifneq ($(CONFIG_STM32F0L0G0_RTC_LSECLOCK)$(CONFIG_STM32F0L0G0_LCD_LSECLOCK),) -CHIP_CSRCS += stm32_lse.c -endif - -ifeq ($(CONFIG_STM32F0L0G0_DMA),y) -CHIP_CSRCS += stm32_dma.c -endif - -ifeq ($(CONFIG_STM32F0L0G0_PWR),y) -CHIP_CSRCS += stm32_pwr.c -endif - -ifneq ($(CONFIG_ARCH_IDLE_CUSTOM),y) -CHIP_CSRCS += stm32_idle.c -endif - -ifneq ($(CONFIG_SCHED_TICKLESS),y) -CHIP_CSRCS += stm32_timerisr.c -endif - -ifeq ($(CONFIG_BUILD_PROTECTED),y) -CHIP_CSRCS += stm32_userspace.c -endif - -ifeq ($(CONFIG_STM32F0L0G0_PROGMEM),y) -CHIP_CSRCS += stm32_flash.c -endif - -ifeq ($(CONFIG_STM32F0L0G0_GPIOIRQ),y) -CHIP_CSRCS += stm32_gpioint.c -endif - -ifeq ($(CONFIG_STM32F0L0G0_HAVE_HSI48),y) -CHIP_CSRCS += stm32_hsi48.c -endif - -ifeq ($(CONFIG_STM32F0L0G0_USB),y) -CHIP_CSRCS += stm32_usbdev.c -endif - -ifeq ($(CONFIG_STM32F0L0G0_I2C),y) -CHIP_CSRCS += stm32_i2c.c -endif - -ifeq ($(CONFIG_STM32F0L0G0_SPI),y) -CHIP_CSRCS += stm32_spi.c -endif - -ifeq ($(CONFIG_STM32F0L0G0_PWM),y) -CHIP_CSRCS += stm32_pwm.c -endif - -ifeq ($(CONFIG_PULSECOUNT),y) -ifeq ($(CONFIG_STM32F0L0G0_TIM1_PULSECOUNT),y) -CHIP_CSRCS += stm32_pulsecount.c -endif -endif - -ifeq ($(CONFIG_STM32F0L0G0_ADC),y) -CHIP_CSRCS += stm32_adc.c -endif - -ifeq ($(CONFIG_STM32F0L0G0_AES),y) -CHIP_CSRCS += stm32_aes.c -endif - -ifeq ($(CONFIG_STM32F0L0G0_RNG),y) -CHIP_CSRCS += stm32_rng.c -endif - -ifeq ($(CONFIG_STM32F0L0G0_TIM),y) -CHIP_CSRCS += stm32_tim.c stm32_tim_lowerhalf.c -endif - -ifeq ($(CONFIG_STM32F0L0G0_IWDG),y) -CHIP_CSRCS += stm32_iwdg.c -endif - -ifeq ($(CONFIG_STM32F0L0G0_WWDG),y) -CHIP_CSRCS += stm32_wwdg.c -endif - -ifeq ($(CONFIG_STM32F0L0G0_FDCAN),y) -ifeq ($(CONFIG_STM32F0L0G0_FDCAN_CHARDRIVER),y) -CHIP_CSRCS += stm32_fdcan.c -endif -ifeq ($(CONFIG_STM32F0L0G0_FDCAN_SOCKET),y) -CHIP_CSRCS += stm32_fdcan_sock.c -endif -endif - -ifeq ($(CONFIG_SENSORS_QENCODER),y) -CHIP_CSRCS += stm32_qencoder.c -endif diff --git a/arch/arm/src/stm32f0l0g0/chip.h b/arch/arm/src/stm32f0l0g0/chip.h deleted file mode 100644 index b496c6b202067..0000000000000 --- a/arch/arm/src/stm32f0l0g0/chip.h +++ /dev/null @@ -1,46 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32f0l0g0/chip.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_CHIP_H -#define __ARCH_ARM_SRC_STM32F0L0G0_CHIP_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include "nvic.h" - -/* Include the chip capabilities file */ - -#include - -#define ARMV6M_PERIPHERAL_INTERRUPTS 32 - -/* Include the memory map file. - * Other chip hardware files should then include this file for the proper - * setup. - */ - -#include "hardware/stm32_memorymap.h" - -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_CHIP_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32_adc.h b/arch/arm/src/stm32f0l0g0/hardware/stm32_adc.h deleted file mode 100644 index b855b530df532..0000000000000 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32_adc.h +++ /dev/null @@ -1,326 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32_adc.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_ADC_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_ADC_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "chip.h" - -/* STM32 M0 ADC driver: - * - no injected channels - * - no offset registers - * - the F0/L0 family support one sampling time configuration for all - * channels - * - the G0 family support two sampling time configurations - */ - -/* Support for battery voltage */ - -#if 0 -# define HAVE_ADC_VBAT -#else -# undef HAVE_ADC_VBAT -#endif - -/* Support for ADC clock prescaler */ - -#if defined(CONFIG_STM32F0L0G0_STM32L0) || defined(CONFIG_STM32F0L0G0_STM32G0) -# define HAVE_ADC_PRE -#else -# undef HAVE_ADC_PRE -#endif - -/* Support for LCD voltage */ - -#ifdef CONFIG_STM32F0L0G0_HAVE_LCD -# define HAVE_ADC_VLCD -#else -# undef HAVE_ADC_VLCD -#endif - -/* Support for Low frequency mode */ - -#ifdef CONFIG_STM32F0L0G0_ENERGYLITE -# define HAVE_ADC_LFM -#else -# undef HAVE_ADC_LFM -#endif - -#undef ADC_HAVE_INJECTED - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#define STM32_ADCCMN_OFFSET 0x0300 - -/* ADC1, ADC2 common - ADC2 not present on STM32 M0/M0+ devices */ - -#define STM32_ADC12CMN_BASE (STM32_ADCCMN_OFFSET+STM32_ADC1_BASE) - -/* Register Offsets *********************************************************/ - -#define STM32_ADC_ISR_OFFSET 0x0000 /* ADC interrupt and status register */ -#define STM32_ADC_IER_OFFSET 0x0004 /* ADC interrupt enable register */ -#define STM32_ADC_CR_OFFSET 0x0008 /* ADC control register */ -#define STM32_ADC_CFGR1_OFFSET 0x000c /* ADC configuration register 1 */ -#define STM32_ADC_CFGR2_OFFSET 0x0010 /* ADC configuration register 2 */ -#define STM32_ADC_SMPR_OFFSET 0x0014 /* ADC sample time register */ -#define STM32_ADC_TR_OFFSET 0x0020 /* ADC watchdog threshold register */ -#define STM32_ADC_AWD2TR_OFFSET 0x0024 /* ADC watchdog 2 threshold register */ -#define STM32_ADC_CHSELR_OFFSET 0x0028 /* ADC channel selection register */ -#define STM32_ADC_AWD3TR_OFFSET 0x002c /* ADC watchdog 3 threshold register */ -#define STM32_ADC_DR_OFFSET 0x0040 /* ADC regular data register */ -#define STM32_ADC_AWD2CR_OFFSET 0x00a0 /* ADC watchdog 2 control register */ -#define STM32_ADC_AWD3CR_OFFSET 0x00a4 /* ADC watchdog 2 control register */ -#define STM32_ADC_CALFACT_OFFSET 0x00b4 /* ADC Calibration factor register */ - -/* Master and Slave ADC Common Registers */ - -#define STM32_ADC_CCR_OFFSET 0x0008 /* Common control register */ - -/* Register Addresses *******************************************************/ - -#define STM32_ADC1_ISR (STM32_ADC1_BASE + STM32_ADC_ISR_OFFSET) -#define STM32_ADC1_IER (STM32_ADC1_BASE + STM32_ADC_IER_OFFSET) -#define STM32_ADC1_CR (STM32_ADC1_BASE + STM32_ADC_CR_OFFSET) -#define STM32_ADC1_CFGR1 (STM32_ADC1_BASE + STM32_ADC_CFGR1_OFFSET) -#define STM32_ADC1_CFGR2 (STM32_ADC1_BASE + STM32_ADC_CFGR2_OFFSET) -#define STM32_ADC1_SMPR (STM32_ADC1_BASE + STM32_ADC_SMPR_OFFSET) -#define STM32_ADC1_TR (STM32_ADC1_BASE + STM32_ADC_TR_OFFSET) -#define STM32_ADC1_AWD2TR (STM32_ADC1_BASE + STM32_ADC_AWD2TR_OFFSET) -#define STM32_ADC1_CHSELR (STM32_ADC1_BASE + STM32_ADC_CHSELR_OFFSET) -#define STM32_ADC1_AWD3TR (STM32_ADC1_BASE + STM32_ADC_AWD3TR_OFFSET) -#define STM32_ADC1_DR (STM32_ADC1_BASE + STM32_ADC_DR_OFFSET) -#define STM32_ADC1_AWD2CR (STM32_ADC1_BASE + STM32_ADC_AWD2CR_OFFSET) -#define STM32_ADC1_AWD3CR (STM32_ADC1_BASE + STM32_ADC_AWD3CR_OFFSET) -#define STM32_ADC1_CALFACT (STM32_ADC1_BASE + STM32_ADC_CALFACT_OFFSET) -#if defined(CONFIG_ARCH_CHIP_STM32G0) -# define STM32_ADC1_CCR (STM32_ADC1_BASE + STM32_ADC_CCR_OFFSET) -#endif - -/* Register Bitfield Definitions ********************************************/ - -/* ADC interrupt and status register (ISR) and - * ADC interrupt enable register (IER) - */ - -#define ADC_INT_ARDY (1 << 0) /* Bit 0: ADC ready */ -#define ADC_INT_EOSMP (1 << 1) /* Bit 1: End of sampling flag */ -#define ADC_INT_EOC (1 << 2) /* Bit 2: End of conversion */ -#define ADC_INT_EOS (1 << 3) /* Bit 3: End of regular sequence flag */ -#define ADC_INT_OVR (1 << 4) /* Bit 4: Overrun */ -#define ADC_INT_AWD (1 << 7) /* Bit 7: Analog watchdog flag */ -#define ADC_INT_EOCAL (1 << 11) /* Bit 11: End of calibration flag */ -#define ADC_INT_CCRDY (1 << 13) /* Bit 13: Channel configuration ready flag*/ - -/* ADC control register */ - -#define ADC_CR_ADEN (1 << 0) /* Bit 0: ADC enable control */ -#define ADC_CR_ADDIS (1 << 1) /* Bit 1: ADC disable command */ -#define ADC_CR_ADSTART (1 << 2) /* Bit 2: ADC start of regular conversion */ -#define ADC_CR_ADSTP (1 << 4) /* Bit 4: ADC stop of regular conversion command */ -#define ADC_CR_ADVREGEN (1 << 28) /* Bit 28: ADC Voltage Regulator Enable */ -#define ADC_CR_ADCAL (1 << 31) /* Bit 31: ADC calibration */ - -/* ADC configuration register 1 */ - -#define ADC_CFGR1_DMAEN (1 << 0) /* Bit 0: Direct memory access enable */ -#define ADC_CFGR1_DMACFG (1 << 1) /* Bit 1: Direct memory access configuration */ -#define ADC_CFGR1_SCANDIR (1 << 2) /* Bit 2: Scan sequence direction */ -#define ADC_CFGR1_RES_SHIFT (3) /* Bits 3-4: Data resolution */ -#define ADC_CFGR1_RES_MASK (3 << ADC_CFGR1_RES_SHIFT) -# define ADC_CFGR1_RES_12BIT (0 << ADC_CFGR1_RES_SHIFT) /* 15 ADCCLK clyes */ -# define ADC_CFGR1_RES_10BIT (1 << ADC_CFGR1_RES_SHIFT) /* 13 ADCCLK clyes */ -# define ADC_CFGR1_RES_8BIT (2 << ADC_CFGR1_RES_SHIFT) /* 11 ADCCLK clyes */ -# define ADC_CFGR1_RES_6BIT (3 << ADC_CFGR1_RES_SHIFT) /* 9 ADCCLK clyes */ - -#define ADC_CFGR1_ALIGN (1 << 5) /* Bit 5: Data Alignment */ -#define ADC_CFGR1_EXTSEL_SHIFT (6) /* Bits 6-8: External trigger selection */ -#define ADC_CFGR1_EXTSEL_MASK (7 << ADC_CFGR1_EXTSEL_SHIFT) -# define ADC12_CFGR1_EXTSEL_TRG0 (0 << ADC_CFGR1_EXTSEL_SHIFT) -# define ADC12_CFGR1_EXTSEL_TRG1 (1 << ADC_CFGR1_EXTSEL_SHIFT) -# define ADC12_CFGR1_EXTSEL_TRG2 (2 << ADC_CFGR1_EXTSEL_SHIFT) -# define ADC12_CFGR1_EXTSEL_TRG3 (3 << ADC_CFGR1_EXTSEL_SHIFT) -# define ADC12_CFGR1_EXTSEL_TRG4 (4 << ADC_CFGR1_EXTSEL_SHIFT) -# define ADC12_CFGR1_EXTSEL_TRG5 (5 << ADC_CFGR1_EXTSEL_SHIFT) -# define ADC12_CFGR1_EXTSEL_TRG6 (6 << ADC_CFGR1_EXTSEL_SHIFT) -# define ADC12_CFGR1_EXTSEL_TRG7 (7 << ADC_CFGR1_EXTSEL_SHIFT) -#define ADC_CFGR1_EXTEN_SHIFT (10) /* Bits 10-11: External trigger/polarity selection regular channels */ -#define ADC_CFGR1_EXTEN_MASK (3 << ADC_CFGR1_EXTEN_SHIFT) -# define ADC_CFGR1_EXTEN_NONE (0 << ADC_CFGR1_EXTEN_SHIFT) /* Trigger detection disabled */ -# define ADC_CFGR1_EXTEN_RISING (1 << ADC_CFGR1_EXTEN_SHIFT) /* Trigger detection on the rising edge */ -# define ADC_CFGR1_EXTEN_FALLING (2 << ADC_CFGR1_EXTEN_SHIFT) /* Trigger detection on the falling edge */ -# define ADC_CFGR1_EXTEN_BOTH (3 << ADC_CFGR1_EXTEN_SHIFT) /* Trigger detection on both edges */ - -#define ADC_CFGR1_OVRMOD (1 << 12) /* Bit 12: Overrun Mode */ -#define ADC_CFGR1_CONT (1 << 13) /* Bit 13: Continuous mode for regular conversions */ -#define ADC_CFGR1_WAIT (1 << 14) /* Bit 14: Wait conversion mode */ -#define ADC_CFGR1_AUTOFF (1 << 15) /* Bit 15: Auto-off mode */ -#define ADC_CFGR1_DISCEN (1 << 16) /* Bit 16: Discontinuous mode on regular channels */ -#define ADC_CFGR1_CHSELRMOD (1 << 21) /* Bit 21: Mode selection of ADC_CHSELR register */ -#define ADC_CFGR1_AWDSGL (1 << 22) /* Bit 22: Enable watchdog on single/all channels */ -#define ADC_CFGR1_AWDEN (1 << 23) /* Bit 23: Analog watchdog enable */ -#define ADC_CFGR1_AWDCH_SHIFT (26) /* Bits 26-30: Analog watchdog 1 channel select bits */ -#define ADC_CFGR1_AWDCH_MASK (31 << ADC_CFGR1_AWDCH_SHIFT) -# define ADC_CFGR1_AWDCH_DISABLED (0 << ADC_CFGR1_AWDCH_SHIFT) - -/* ADC configuration register 2 */ - -#define ADC_CFGR2_OVSE (1 << 0) /* Bit 1: Oversampler enable */ -#define ADC_CFGR2_OVSR_SHIFT (2) /* Bits 2-4: Oversampling ratio */ -#define ADC_CFGR2_OVSR_MASK (7 << ADC_CFGR2_OVSR_SHIFT) -# define ADC_CFGR2_OVSR_2X (0 << ADC_CFGR2_OVSR_SHIFT) -# define ADC_CFGR2_OVSR_4X (1 << ADC_CFGR2_OVSR_SHIFT) -# define ADC_CFGR2_OVSR_8X (2 << ADC_CFGR2_OVSR_SHIFT) -# define ADC_CFGR2_OVSR_16X (3 << ADC_CFGR2_OVSR_SHIFT) -# define ADC_CFGR2_OVSR_32X (4 << ADC_CFGR2_OVSR_SHIFT) -# define ADC_CFGR2_OVSR_64X (5 << ADC_CFGR2_OVSR_SHIFT) -# define ADC_CFGR2_OVSR_128X (6 << ADC_CFGR2_OVSR_SHIFT) -# define ADC_CFGR2_OVSR_256X (7 << ADC_CFGR2_OVSR_SHIFT) -#define ADC_CFGR2_OVSS_SHIFT (5) /* Bits 5-8: Oversampling shift */ -#define ADC_CFGR2_OVSS_MASK (0xf << ADC_CFGR2_OVSS_SHIFT) -#define ADC_CFGR2_OVSS(sb) ((sb) << ADC_CFGR2_OVSS_SHIFT) /* Shift sb bits */ -# define ADC_CFGR2_OVSS_NONE (0 << ADC_CFGR2_OVSS_SHIFT) -#define ADC_CFGR2_TOVS (1 << 9) /* Bit 9: Triggered oversampling */ - /* Bits 10-28: Reserved */ -#define ADC_CFGR2_LFTRIG (1 << 29) /* Bit 29: Low frequency trigger mode enable */ -#define ADC_CFGR2_CKMODE_SHIFT (30) /* Bits 30-31: ADC clock mode */ -#define ADC_CFGR2_CKMODE_MASK (3 << ADC_CFGR2_CKMODE_SHIFT) -# define ADC_CFGR2_CKMODE_ADCCLK (0 << ADC_CFGR2_CKMODE_SHIFT) /* 00: ADCCLK (Asynchronous) generated at product level */ -# define ADC_CFGR2_CKMODE_PCLKd2 (1 << ADC_CFGR2_CKMODE_SHIFT) /* 01: PCLK/2 (Synchronous clock mode) */ -# define ADC_CFGR2_CKMODE_PCLKd4 (2 << ADC_CFGR2_CKMODE_SHIFT) /* 10: PCLK/4 (Synchronous clock mode) */ - -/* ADC sample time register */ - -#if defined(CONFIG_ARCH_CHIP_STM32C0) || defined(CONFIG_ARCH_CHIP_STM32G0) -# define ADC_SMPR_1p5 (0) /* 000: 1.5 cycles */ -# define ADC_SMPR_3p5 (1) /* 001: 3.5 cycles */ -# define ADC_SMPR_7p5 (2) /* 010: 7.5 cycles */ -# define ADC_SMPR_12p5 (3) /* 011: 12.5 cycles */ -# define ADC_SMPR_19p5 (4) /* 100: 19.5 cycles */ -# define ADC_SMPR_39p5 (5) /* 101: 39.5 cycles */ -# define ADC_SMPR_79p5 (6) /* 110: 79.5 cycles */ -# define ADC_SMPR_160p5 (7) /* 111: 160.5 cycles */ -#else -# define ADC_SMPR_1p5 (0) /* 000: 1.5 cycles */ -# define ADC_SMPR_7p5 (1) /* 001: 7.5 cycles */ -# define ADC_SMPR_13p5 (2) /* 010: 13.5 cycles */ -# define ADC_SMPR_28p5 (3) /* 011: 28.5 cycles */ -# define ADC_SMPR_41p5 (4) /* 100: 41.5 cycles */ -# define ADC_SMPR_55p5 (5) /* 101: 55.5 cycles */ -# define ADC_SMPR_71p5 (6) /* 110: 71.5 cycles */ -# define ADC_SMPR_239p5 (7) /* 111: 239.5 cycles */ -#endif - -#define ADC_SMPR_SMP1_SHIFT (0) /* Bits 0-2: Sampling time selection 1 */ -#define ADC_SMPR_SMP1_MASK (7 << ADC_SMPR_SMP_SHIFT) -#define ADC_SMPR_SMP2_SHIFT (4) /* Bits 4-6: Sampling time selection 2 */ -#define ADC_SMPR_SMP2_MASK (7 << ADC_SMPR_SMP_SHIFT) -#define ADC_SMPR_SMPSEL_SHIFT (8) /* Bits 8-26: channel-x sampling time selection */ -#if defined(CONFIG_ARCH_CHIP_STM32G0) || defined(CONFIG_ARCH_CHIP_STM32C0) -# define ADC_SMPR_SMPSEL(ch, smp) ((smp) << (ADC_SMPR_SMPSEL_SHIFT + ch)) /* ch = [0..22] and smp = 0 or 1 */ -# define ADC_SMPSEL(ch, smp) ((smp) << (ch)) /* For use in adc_sampletime_set */ -#else -# define ADC_SMPR_SMPSEL(ch, smp) (smp << ADC_SMPR_SMPSEL_SHIFT) -#endif - -/* ADC watchdog threshold register */ - -#define ADC_TR_LT_SHIFT (0) /* Bits 0-11: Analog watchdog lower threshold */ -#define ADC_TR_LT_MASK (0x0fff << ADC_TR_LT_SHIFT) -#define ADC_TR_HT_SHIFT (16) /* Bits 16-27: Analog watchdog higher threshold */ -#define ADC_TR_HT_MASK (0x0fff << ADC_TR_HT_SHIFT) - -/* ADC channel selection register */ - -#define ADC_CHSELR_CHSEL0 (1 << 0) /* Select channel 0 */ -#define ADC_CHSELR_CHSEL1 (1 << 1) /* Select channel 1 */ -#define ADC_CHSELR_CHSEL2 (1 << 2) /* Select channel 2 */ -#define ADC_CHSELR_CHSEL3 (1 << 3) /* Select channel 3 */ -#define ADC_CHSELR_CHSEL4 (1 << 4) /* Select channel 4 */ -#define ADC_CHSELR_CHSEL5 (1 << 5) /* Select channel 5 */ -#define ADC_CHSELR_CHSEL6 (1 << 6) /* Select channel 6 */ -#define ADC_CHSELR_CHSEL7 (1 << 7) /* Select channel 7 */ -#define ADC_CHSELR_CHSEL8 (1 << 8) /* Select channel 8 */ -#define ADC_CHSELR_CHSEL9 (1 << 9) /* Select channel 9 */ -#define ADC_CHSELR_CHSEL10 (1 << 10) /* Select channel 10 */ -#define ADC_CHSELR_CHSEL11 (1 << 11) /* Select channel 11 */ -#define ADC_CHSELR_CHSEL12 (1 << 12) /* Select channel 12 */ -#define ADC_CHSELR_CHSEL13 (1 << 13) /* Select channel 13 */ -#define ADC_CHSELR_CHSEL14 (1 << 14) /* Select channel 14 */ -#define ADC_CHSELR_CHSEL15 (1 << 15) /* Select channel 15 */ -#define ADC_CHSELR_CHSEL16 (1 << 16) /* Select channel 16 */ -#define ADC_CHSELR_CHSEL17 (1 << 17) /* Select channel 17 */ -#define ADC_CHSELR_CHSEL18 (1 << 18) /* Select channel 18 */ -#define ADC_CHSELR_CHSEL(ch) (1 << (ch)) - -/* ADC channel selection alternate register - * Enabled when CHSELRMOD = 1 in ADC_CFGR1 - */ - -#if defined(CONFIG_ARCH_CHIP_STM32G0) -# define ADC_CHSELR_ALT_SQN(sqn, ch) ((ch) << (((sqn) - 1) * 4)) /* sqn = [0..8], ch = [0..14] */ -#endif - -#define ADC_DR_RDATA_SHIFT (0) -#define ADC_DR_RDATA_MASK (0xffff << ADC_DR_RDATA_SHIFT) - -/* Analog watchdog 2/3 configuration register */ - -#define ADC_AWDXCR_AWDXCHN(ch) (1 << (ch)) /* ch = [0..18] */ - -/* Calibration factor register */ - -#define ADC_CALFACT_CALFACT_SHIFT (0) -#define ADC_CALFACT_CALFACT_MASK (0x7f << ADC_CALFACT_CALFACT_SHIFT) - -/* Common configuration register */ - -#define ADC_CCR_PRESC_SHIFT (18) /* ADC Prescaler */ -#define ADC_CCR_PRESC_MASK (0xf << ADC_CCR_PRESC_SHIFT) -# define ADC_CCR_PRESC_NOT_DIV (0) -# define ADC_CCR_PRESC_DIV2 (1 << ADC_CCR_PRESC_SHIFT) -# define ADC_CCR_PRESC_DIV4 (2 << ADC_CCR_PRESC_SHIFT) -# define ADC_CCR_PRESC_DIV6 (3 << ADC_CCR_PRESC_SHIFT) -# define ADC_CCR_PRESC_DIV8 (4 << ADC_CCR_PRESC_SHIFT) -# define ADC_CCR_PRESC_DIV10 (5 << ADC_CCR_PRESC_SHIFT) -# define ADC_CCR_PRESC_DIV12 (6 << ADC_CCR_PRESC_SHIFT) -# define ADC_CCR_PRESC_DIV16 (7 << ADC_CCR_PRESC_SHIFT) -# define ADC_CCR_PRESC_DIV32 (8 << ADC_CCR_PRESC_SHIFT) -# define ADC_CCR_PRESC_DIV64 (9 << ADC_CCR_PRESC_SHIFT) -# define ADC_CCR_PRESC_DIV128 (10 << ADC_CCR_PRESC_SHIFT) -# define ADC_CCR_PRESC_DIV256 (11 << ADC_CCR_PRESC_SHIFT) - -#define ADC_CCR_VREFEN (1 << 22) /* Bit 22: VREFINT enable */ -#define ADC_CCR_TSEN (1 << 23) /* Bit 23: Temperature sensor enable */ -#define ADC_CCR_VBATEN (1 << 24) /* Bit 24: VBAT enable */ -#define ADC_CCR_VLCDEN (1 << 24) /* Bit 24: VLCD enable */ -#define ADC_CCR_LFMEN (1 << 25) /* Bit 25: Low Frequency Mode enable */ - -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_ADC_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32_aes.h b/arch/arm/src/stm32f0l0g0/hardware/stm32_aes.h deleted file mode 100644 index d49e402abbac0..0000000000000 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32_aes.h +++ /dev/null @@ -1,101 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32_aes.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_AES_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_AES_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "chip.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* AES register offsets *****************************************************/ - -#define STM32_AES_CR_OFFSET 0x0000 /* Control Register */ -#define STM32_AES_SR_OFFSET 0x0004 /* Status Register */ -#define STM32_AES_DINR_OFFSET 0x0008 /* Data Input Register */ -#define STM32_AES_DOUTR_OFFSET 0x000C /* Data Output Register */ -#define STM32_AES_KEYR0_OFFSET 0x0010 /* AES Key Register 0 */ -#define STM32_AES_KEYR1_OFFSET 0x0014 /* AES Key Register 1 */ -#define STM32_AES_KEYR2_OFFSET 0x0018 /* AES Key Register 2 */ -#define STM32_AES_KEYR3_OFFSET 0x001C /* AES Key Register 3 */ -#define STM32_AES_IVR0_OFFSET 0x0020 /* AES Initialization Vector Register 0 */ -#define STM32_AES_IVR1_OFFSET 0x0024 /* AES Initialization Vector Register 1 */ -#define STM32_AES_IVR2_OFFSET 0x0028 /* AES Initialization Vector Register 2 */ -#define STM32_AES_IVR3_OFFSET 0x002C /* AES Initialization Vector Register 3 */ - -/* AES register addresses ***************************************************/ - -#define STM32_AES_CR (STM32_AES_BASE + STM32_AES_CR_OFFSET) -#define STM32_AES_SR (STM32_AES_BASE + STM32_AES_SR_OFFSET) -#define STM32_AES_DINR (STM32_AES_BASE + STM32_AES_DINR_OFFSET) -#define STM32_AES_DOUTR (STM32_AES_BASE + STM32_AES_DOUTR_OFFSET) -#define STM32_AES_KEYR0 (STM32_AES_BASE + STM32_AES_KEYR0_OFFSET) -#define STM32_AES_KEYR1 (STM32_AES_BASE + STM32_AES_KEYR1_OFFSET) -#define STM32_AES_KEYR2 (STM32_AES_BASE + STM32_AES_KEYR2_OFFSET) -#define STM32_AES_KEYR3 (STM32_AES_BASE + STM32_AES_KEYR3_OFFSET) -#define STM32_AES_IVR0 (STM32_AES_BASE + STM32_AES_IVR0_OFFSET) -#define STM32_AES_IVR1 (STM32_AES_BASE + STM32_AES_IVR1_OFFSET) -#define STM32_AES_IVR2 (STM32_AES_BASE + STM32_AES_IVR2_OFFSET) -#define STM32_AES_IVR3 (STM32_AES_BASE + STM32_AES_IVR3_OFFSET) - -/* AES register bit definitions *********************************************/ - -/* AES_CR register */ - -#define AES_CR_EN (1 << 0) /* AES Enable */ -#define AES_CR_DATATYPE (1 << 1) /* Data type selection */ -# define AES_CR_DATATYPE_LE (0x0 << 1) -# define AES_CR_DATATYPE_BE (0x2 << 1) - -#define AES_CR_MODE (1 << 3) /* AES Mode of operation */ -# define AES_CR_MODE_ENCRYPT (0x0 << 3) -# define AES_CR_MODE_KEYDERIV (0x1 << 3) -# define AES_CR_MODE_DECRYPT (0x2 << 3) -# define AES_CR_MODE_DECRYPT_KEYDERIV (0x3 << 3) - -#define AES_CR_CHMOD (1 << 5) /* AES Chaining Mode */ -# define AES_CR_CHMOD_ECB (0x0 << 5) -# define AES_CR_CHMOD_CBC (0x1 << 5) -# define AES_CR_CHMOD_CTR (0x2 << 5) - -#define AES_CR_CCFC (1 << 7) /* Computation Complete Flag Clear */ -#define AES_CR_ERRC (1 << 8) /* Error Clear */ -#define AES_CR_CCIE (1 << 9) /* Computation Complete Interrupt Enable */ -#define AES_CR_ERRIE (1 << 10) /* Error Interrupt Enable */ -#define AES_CR_DMAINEN (1 << 11) /* DMA Enable Input */ -#define AES_CR_DMAOUTEN (1 << 12) /* DMA Enable Output */ - -/* AES_SR register */ - -#define AES_SR_CCF (1 << 0) /* Computation Complete Flag */ -#define AES_SR_RDERR (1 << 1) /* Read Error Flag */ -#define AES_SR_WRERR (1 << 2) /* Write Error Flag */ - -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_AES_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32_can.h b/arch/arm/src/stm32f0l0g0/hardware/stm32_can.h deleted file mode 100644 index 774855c7f8fbe..0000000000000 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32_can.h +++ /dev/null @@ -1,456 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32_can.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_CAN_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_CAN_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "chip.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* 3 TX mailboxes */ - -#define CAN_TXMBOX1 0 -#define CAN_TXMBOX2 1 -#define CAN_TXMBOX3 2 - -/* 2 RX mailboxes */ - -#define CAN_RXMBOX1 0 -#define CAN_RXMBOX2 1 - -/* Number of filters depends on silicon */ - -#define CAN_NFILTERS 14 - -/* Register Offsets *********************************************************/ - -/* CAN control and status registers */ - -#define STM32_CAN_MCR_OFFSET 0x0000 /* CAN master control register */ -#define STM32_CAN_MSR_OFFSET 0x0004 /* CAN master status register */ -#define STM32_CAN_TSR_OFFSET 0x0008 /* CAN transmit status register */ - -#define STM32_CAN_RFR_OFFSET(m) (0x000c + ((m) << 2)) -#define STM32_CAN_RF0R_OFFSET 0x000c /* CAN receive FIFO 0 register */ -#define STM32_CAN_RF1R_OFFSET 0x0010 /* CAN receive FIFO 1 register */ - -#define STM32_CAN_IER_OFFSET 0x0014 /* CAN interrupt enable register */ -#define STM32_CAN_ESR_OFFSET 0x0018 /* CAN error status register */ -#define STM32_CAN_BTR_OFFSET 0x001c /* CAN bit timing register */ - -/* CAN mailbox registers (3 TX and 2 RX) */ - -#define STM32_CAN_TIR_OFFSET(m) (0x0180 + ((m) << 4)) -#define STM32_CAN_TI0R_OFFSET 0x0180 /* TX mailbox identifier register 0 */ -#define STM32_CAN_TI1R_OFFSET 0x0190 /* TX mailbox identifier register 1 */ -#define STM32_CAN_TI2R_OFFSET 0x01a0 /* TX mailbox identifier register 2 */ - -#define STM32_CAN_TDTR_OFFSET(m) (0x0184 + ((m) << 4)) -#define STM32_CAN_TDT0R_OFFSET 0x0184 /* Mailbox data length control and time stamp register 0 */ -#define STM32_CAN_TDT1R_OFFSET 0x0194 /* Mailbox data length control and time stamp register 1 */ -#define STM32_CAN_TDT2R_OFFSET 0x01a4 /* Mailbox data length control and time stamp register 2 */ - -#define STM32_CAN_TDLR_OFFSET(m) (0x0188 + ((m) << 4)) -#define STM32_CAN_TDL0R_OFFSET 0x0188 /* Mailbox data low register 0 */ -#define STM32_CAN_TDL1R_OFFSET 0x0198 /* Mailbox data low register 1 */ -#define STM32_CAN_TDL2R_OFFSET 0x01a8 /* Mailbox data low register 2 */ - -#define STM32_CAN_TDHR_OFFSET(m) (0x018c + ((m) << 4)) -#define STM32_CAN_TDH0R_OFFSET 0x018c /* Mailbox data high register 0 */ -#define STM32_CAN_TDH1R_OFFSET 0x019c /* Mailbox data high register 1 */ -#define STM32_CAN_TDH2R_OFFSET 0x01ac /* Mailbox data high register 2 */ - -#define STM32_CAN_RIR_OFFSET(m) (0x01b0 + ((m) << 4)) -#define STM32_CAN_RI0R_OFFSET 0x01b0 /* Rx FIFO mailbox identifier register 0 */ -#define STM32_CAN_RI1R_OFFSET 0x01c0 /* Rx FIFO mailbox identifier register 1 */ - -#define STM32_CAN_RDTR_OFFSET(m) (0x01b4 + ((m) << 4)) -#define STM32_CAN_RDT0R_OFFSET 0x01b4 /* Rx FIFO mailbox data length control and time stamp register 0 */ -#define STM32_CAN_RDT1R_OFFSET 0x01c4 /* Rx FIFO mailbox data length control and time stamp register 1 */ - -#define STM32_CAN_RDLR_OFFSET(m) (0x01b8 + ((m) << 4)) -#define STM32_CAN_RDL0R_OFFSET 0x01b8 /* Receive FIFO mailbox data low register 0 */ -#define STM32_CAN_RDL1R_OFFSET 0x01c8 /* Receive FIFO mailbox data low register 1 */ - -#define STM32_CAN_RDHR_OFFSET(m) (0x01bc + ((m) << 4)) -#define STM32_CAN_RDH0R_OFFSET 0x01bc /* Receive FIFO mailbox data high register 0 */ -#define STM32_CAN_RDH1R_OFFSET 0x01cc /* Receive FIFO mailbox data high register 1 */ - -/* CAN filter registers */ - -#define STM32_CAN_FMR_OFFSET 0x0200 /* CAN filter master register */ -#define STM32_CAN_FM1R_OFFSET 0x0204 /* CAN filter mode register */ -#define STM32_CAN_FS1R_OFFSET 0x020c /* CAN filter scale register */ -#define STM32_CAN_FFA1R_OFFSET 0x0214 /* CAN filter FIFO assignment register */ -#define STM32_CAN_FA1R_OFFSET 0x021c /* CAN filter activation register */ - -/* There are 14 or 28 filter banks (depending) on the device. - * Each filter bank is composed of two 32-bit registers, CAN_FiR: - * F0R1 Offset 0x240 - * F0R2 Offset 0x244 - * F1R1 Offset 0x248 - * F1R2 Offset 0x24c - * ... - */ - -#define STM32_CAN_FIR_OFFSET(f,i) (0x240 + ((f) << 3)+(((i) - 1) << 2)) - -/* Register Addresses *******************************************************/ - -#if STM32_NCAN > 0 -# define STM32_CAN1_MCR (STM32_CAN1_BASE + STM32_CAN_MCR_OFFSET) -# define STM32_CAN1_MSR (STM32_CAN1_BASE + STM32_CAN_MSR_OFFSET) -# define STM32_CAN1_TSR (STM32_CAN1_BASE + STM32_CAN_TSR_OFFSET) -# define STM32_CAN1_RF0R (STM32_CAN1_BASE + STM32_CAN_RF0R_OFFSET) -# define STM32_CAN1_RF1R (STM32_CAN1_BASE + STM32_CAN_RF1R_OFFSET) -# define STM32_CAN1_IER (STM32_CAN1_BASE + STM32_CAN_IER_OFFSET) -# define STM32_CAN1_ESR (STM32_CAN1_BASE + STM32_CAN_ESR_OFFSET) -# define STM32_CAN1_BTR (STM32_CAN1_BASE + STM32_CAN_BTR_OFFSET) - -# define STM32_CAN1_TIR(m) (STM32_CAN1_BASE + STM32_CAN_TIR_OFFSET(m)) -# define STM32_CAN1_TI0R (STM32_CAN1_BASE + STM32_CAN_TI0R_OFFSET) -# define STM32_CAN1_TI1R (STM32_CAN1_BASE + STM32_CAN_TI1R_OFFSET) -# define STM32_CAN1_TI2R (STM32_CAN1_BASE + STM32_CAN_TI2R_OFFSET) - -# define STM32_CAN1_TDTR(m) (STM32_CAN1_BASE + STM32_CAN_TDTR_OFFSET(m)) -# define STM32_CAN1_TDT0R (STM32_CAN1_BASE + STM32_CAN_TDT0R_OFFSET) -# define STM32_CAN1_TDT1R (STM32_CAN1_BASE + STM32_CAN_TDT1R_OFFSET) -# define STM32_CAN1_TDT2R (STM32_CAN1_BASE + STM32_CAN_TDT2R_OFFSET) - -# define STM32_CAN1_TDLR(m) (STM32_CAN1_BASE + STM32_CAN_TDLR_OFFSET(m)) -# define STM32_CAN1_TDL0R (STM32_CAN1_BASE + STM32_CAN_TDL0R_OFFSET) -# define STM32_CAN1_TDL1R (STM32_CAN1_BASE + STM32_CAN_TDL1R_OFFSET) -# define STM32_CAN1_TDL2R (STM32_CAN1_BASE + STM32_CAN_TDL2R_OFFSET) - -# define STM32_CAN1_TDHR(m) (STM32_CAN1_BASE + STM32_CAN_TDHR_OFFSET(m)) -# define STM32_CAN1_TDH0R (STM32_CAN1_BASE + STM32_CAN_TDH0R_OFFSET) -# define STM32_CAN1_TDH1R (STM32_CAN1_BASE + STM32_CAN_TDH1R_OFFSET) -# define STM32_CAN1_TDH2R (STM32_CAN1_BASE + STM32_CAN_TDH2R_OFFSET) - -# define STM32_CAN1_RIR(m) (STM32_CAN1_BASE + STM32_CAN_RIR_OFFSET(m)) -# define STM32_CAN1_RI0R (STM32_CAN1_BASE + STM32_CAN_RI0R_OFFSET) -# define STM32_CAN1_RI1R (STM32_CAN1_BASE + STM32_CAN_RI1R_OFFSET) - -# define STM32_CAN1_RDTR(m) (STM32_CAN1_BASE + STM32_CAN_RDTR_OFFSET(m)) -# define STM32_CAN1_RDT0R (STM32_CAN1_BASE + STM32_CAN_RDT0R_OFFSET) -# define STM32_CAN1_RDT1R (STM32_CAN1_BASE + STM32_CAN_RDT1R_OFFSET) - -# define STM32_CAN1_RDLR(m) (STM32_CAN1_BASE + STM32_CAN_RDLR_OFFSET(m)) -# define STM32_CAN1_RDL0R (STM32_CAN1_BASE + STM32_CAN_RDL0R_OFFSET) -# define STM32_CAN1_RDL1R (STM32_CAN1_BASE + STM32_CAN_RDL1R_OFFSET) - -# define STM32_CAN1_RDHR(m) (STM32_CAN1_BASE + STM32_CAN_RDHR_OFFSET(m)) -# define STM32_CAN1_RDH0R (STM32_CAN1_BASE + STM32_CAN_RDH0R_OFFSET) -# define STM32_CAN1_RDH1R (STM32_CAN1_BASE + STM32_CAN_RDH1R_OFFSET) - -# define STM32_CAN1_FMR (STM32_CAN1_BASE + STM32_CAN_FMR_OFFSET) -# define STM32_CAN1_FM1R (STM32_CAN1_BASE + STM32_CAN_FM1R_OFFSET) -# define STM32_CAN1_FS1R (STM32_CAN1_BASE + STM32_CAN_FS1R_OFFSET) -# define STM32_CAN1_FFA1R (STM32_CAN1_BASE + STM32_CAN_FFA1R_OFFSET) -# define STM32_CAN1_FA1R (STM32_CAN1_BASE + STM32_CAN_FA1R_OFFSET) -# define STM32_CAN1_FIR(b,i) (STM32_CAN1_BASE + STM32_CAN_FIR_OFFSET(b,i)) -#endif - -#if STM32_NCAN > 1 -# define STM32_CAN2_MCR (STM32_CAN2_BASE + STM32_CAN_MCR_OFFSET) -# define STM32_CAN2_MSR (STM32_CAN2_BASE + STM32_CAN_MSR_OFFSET) -# define STM32_CAN2_TSR (STM32_CAN2_BASE + STM32_CAN_TSR_OFFSET) -# define STM32_CAN2_RF0R (STM32_CAN2_BASE + STM32_CAN_RF0R_OFFSET) -# define STM32_CAN2_RF1R (STM32_CAN2_BASE + STM32_CAN_RF1R_OFFSET) -# define STM32_CAN2_IER (STM32_CAN2_BASE + STM32_CAN_IER_OFFSET) -# define STM32_CAN2_ESR (STM32_CAN2_BASE + STM32_CAN_ESR_OFFSET) -# define STM32_CAN2_BTR (STM32_CAN2_BASE + STM32_CAN_BTR_OFFSET) - -# define STM32_CAN2_TIR(m) (STM32_CAN2_BASE + STM32_CAN_TIR_OFFSET(m)) -# define STM32_CAN2_TI0R (STM32_CAN2_BASE + STM32_CAN_TI0R_OFFSET) -# define STM32_CAN2_TI1R (STM32_CAN2_BASE + STM32_CAN_TI1R_OFFSET) -# define STM32_CAN2_TI2R (STM32_CAN2_BASE + STM32_CAN_TI2R_OFFSET) - -# define STM32_CAN2_TDTR(m) (STM32_CAN2_BASE + STM32_CAN_TDTR_OFFSET(m)) -# define STM32_CAN2_TDT0R (STM32_CAN2_BASE + STM32_CAN_TDT0R_OFFSET) -# define STM32_CAN2_TDT1R (STM32_CAN2_BASE + STM32_CAN_TDT1R_OFFSET) -# define STM32_CAN2_TDT2R (STM32_CAN2_BASE + STM32_CAN_TDT2R_OFFSET) - -# define STM32_CAN2_TDLR(m) (STM32_CAN2_BASE + STM32_CAN_TDLR_OFFSET(m)) -# define STM32_CAN2_TDL0R (STM32_CAN2_BASE + STM32_CAN_TDL0R_OFFSET) -# define STM32_CAN2_TDL1R (STM32_CAN2_BASE + STM32_CAN_TDL1R_OFFSET) -# define STM32_CAN2_TDL2R (STM32_CAN2_BASE + STM32_CAN_TDL2R_OFFSET) - -# define STM32_CAN2_TDHR(m) (STM32_CAN2_BASE + STM32_CAN_TDHR_OFFSET(m)) -# define STM32_CAN2_TDH0R (STM32_CAN2_BASE + STM32_CAN_TDH0R_OFFSET) -# define STM32_CAN2_TDH1R (STM32_CAN2_BASE + STM32_CAN_TDH1R_OFFSET) -# define STM32_CAN2_TDH2R (STM32_CAN2_BASE + STM32_CAN_TDH2R_OFFSET) - -# define STM32_CAN2_RIR(m) (STM32_CAN2_BASE + STM32_CAN_RIR_OFFSET(m)) -# define STM32_CAN2_RI0R (STM32_CAN2_BASE + STM32_CAN_RI0R_OFFSET) -# define STM32_CAN2_RI1R (STM32_CAN2_BASE + STM32_CAN_RI1R_OFFSET) - -# define STM32_CAN2_RDTR(m) (STM32_CAN2_BASE + STM32_CAN_RDTR_OFFSET(m)) -# define STM32_CAN2_RDT0R (STM32_CAN2_BASE + STM32_CAN_RDT0R_OFFSET) -# define STM32_CAN2_RDT1R (STM32_CAN2_BASE + STM32_CAN_RDT1R_OFFSET) - -# define STM32_CAN2_RDLR(m) (STM32_CAN2_BASE + STM32_CAN_RDLR_OFFSET(m)) -# define STM32_CAN2_RDL0R (STM32_CAN2_BASE + STM32_CAN_RDL0R_OFFSET) -# define STM32_CAN2_RDL1R (STM32_CAN2_BASE + STM32_CAN_RDL1R_OFFSET) - -# define STM32_CAN2_RDHR(m) (STM32_CAN2_BASE + STM32_CAN_RDHR_OFFSET(m)) -# define STM32_CAN2_RDH0R (STM32_CAN2_BASE + STM32_CAN_RDH0R_OFFSET) -# define STM32_CAN2_RDH1R (STM32_CAN2_BASE + STM32_CAN_RDH1R_OFFSET) - -# define STM32_CAN2_FMR (STM32_CAN2_BASE + STM32_CAN_FMR_OFFSET) -# define STM32_CAN2_FM1R (STM32_CAN2_BASE + STM32_CAN_FM1R_OFFSET) -# define STM32_CAN2_FS1R (STM32_CAN2_BASE + STM32_CAN_FS1R_OFFSET) -# define STM32_CAN2_FFA1R (STM32_CAN2_BASE + STM32_CAN_FFA1R_OFFSET) -# define STM32_CAN2_FA1R (STM32_CAN2_BASE + STM32_CAN_FA1R_OFFSET) -# define STM32_CAN2_FIR(b,i) (STM32_CAN2_BASE + STM32_CAN_FIR_OFFSET(b,i)) -#endif - -/* Register Bitfield Definitions ********************************************/ - -/* CAN master control register */ - -#define CAN_MCR_INRQ (1 << 0) /* Bit 0: Initialization Request */ -#define CAN_MCR_SLEEP (1 << 1) /* Bit 1: Sleep Mode Request */ -#define CAN_MCR_TXFP (1 << 2) /* Bit 2: Transmit FIFO Priority */ -#define CAN_MCR_RFLM (1 << 3) /* Bit 3: Receive FIFO Locked Mode */ -#define CAN_MCR_NART (1 << 4) /* Bit 4: No Automatic Retransmission */ -#define CAN_MCR_AWUM (1 << 5) /* Bit 5: Automatic Wakeup Mode */ -#define CAN_MCR_ABOM (1 << 6) /* Bit 6: Automatic Bus-Off Management */ -#define CAN_MCR_TTCM (1 << 7) /* Bit 7: Time Triggered Communication Mode Enable */ -#define CAN_MCR_RESET (1 << 15) /* Bit 15: bxCAN software master reset */ -#define CAN_MCR_DBF (1 << 16) /* Bit 16: Debug freeze */ - -/* CAN master status register */ - -#define CAN_MSR_INAK (1 << 0) /* Bit 0: Initialization Acknowledge */ -#define CAN_MSR_SLAK (1 << 1) /* Bit 1: Sleep Acknowledge */ -#define CAN_MSR_ERRI (1 << 2) /* Bit 2: Error Interrupt */ -#define CAN_MSR_WKUI (1 << 3) /* Bit 3: Wakeup Interrupt */ -#define CAN_MSR_SLAKI (1 << 4) /* Bit 4: Sleep acknowledge interrupt */ -#define CAN_MSR_TXM (1 << 8) /* Bit 8: Transmit Mode */ -#define CAN_MSR_RXM (1 << 9) /* Bit 9: Receive Mode */ -#define CAN_MSR_SAMP (1 << 10) /* Bit 10: Last Sample Point */ -#define CAN_MSR_RX (1 << 11) /* Bit 11: CAN Rx Signal */ - -/* CAN transmit status register */ - -#define CAN_TSR_RQCP0 (1 << 0) /* Bit 0: Request Completed Mailbox 0 */ -#define CAN_TSR_TXOK0 (1 << 1) /* Bit 1 : Transmission OK of Mailbox 0 */ -#define CAN_TSR_ALST0 (1 << 2) /* Bit 2 : Arbitration Lost for Mailbox 0 */ -#define CAN_TSR_TERR0 (1 << 3) /* Bit 3 : Transmission Error of Mailbox 0 */ -#define CAN_TSR_ABRQ0 (1 << 7) /* Bit 7 : Abort Request for Mailbox 0 */ -#define CAN_TSR_RQCP1 (1 << 8) /* Bit 8 : Request Completed Mailbox 1 */ -#define CAN_TSR_TXOK1 (1 << 9) /* Bit 9 : Transmission OK of Mailbox 1 */ -#define CAN_TSR_ALST1 (1 << 10) /* Bit 10 : Arbitration Lost for Mailbox 1 */ -#define CAN_TSR_TERR1 (1 << 11) /* Bit 11 : Transmission Error of Mailbox 1 */ -#define CAN_TSR_ABRQ1 (1 << 15) /* Bit 15 : Abort Request for Mailbox 1 */ -#define CAN_TSR_RQCP2 (1 << 16) /* Bit 16 : Request Completed Mailbox 2 */ -#define CAN_TSR_TXOK2 (1 << 17) /* Bit 17 : Transmission OK of Mailbox 2 */ -#define CAN_TSR_ALST2 (1 << 18) /* Bit 18: Arbitration Lost for Mailbox 2 */ -#define CAN_TSR_TERR2 (1 << 19) /* Bit 19: Transmission Error of Mailbox 2 */ -#define CAN_TSR_ABRQ2 (1 << 23) /* Bit 23: Abort Request for Mailbox 2 */ -#define CAN_TSR_CODE_SHIFT (24) /* Bits 25-24: Mailbox Code */ -#define CAN_TSR_CODE_MASK (3 << CAN_TSR_CODE_SHIFT) -#define CAN_TSR_TME0 (1 << 26) /* Bit 26: Transmit Mailbox 0 Empty */ -#define CAN_TSR_TME1 (1 << 27) /* Bit 27: Transmit Mailbox 1 Empty */ -#define CAN_TSR_TME2 (1 << 28) /* Bit 28: Transmit Mailbox 2 Empty */ -#define CAN_TSR_LOW0 (1 << 29) /* Bit 29: Lowest Priority Flag for Mailbox 0 */ -#define CAN_TSR_LOW1 (1 << 30) /* Bit 30: Lowest Priority Flag for Mailbox 1 */ -#define CAN_TSR_LOW2 (1 << 31) /* Bit 31: Lowest Priority Flag for Mailbox 2 */ - -/* CAN receive FIFO 0/1 registers */ - -#define CAN_RFR_FMP_SHIFT (0) /* Bits 1-0: FIFO Message Pending */ -#define CAN_RFR_FMP_MASK (3 << CAN_RFR_FMP_SHIFT) -#define CAN_RFR_FULL (1 << 3) /* Bit 3: FIFO 0 Full */ -#define CAN_RFR_FOVR (1 << 4) /* Bit 4: FIFO 0 Overrun */ -#define CAN_RFR_RFOM (1 << 5) /* Bit 5: Release FIFO 0 Output Mailbox */ - -/* CAN interrupt enable register */ - -#define CAN_IER_TMEIE (1 << 0) /* Bit 0: Transmit Mailbox Empty Interrupt Enable */ -#define CAN_IER_FMPIE0 (1 << 1) /* Bit 1: FIFO Message Pending Interrupt Enable */ -#define CAN_IER_FFIE0 (1 << 2) /* Bit 2: FIFO Full Interrupt Enable */ -#define CAN_IER_FOVIE0 (1 << 3) /* Bit 3: FIFO Overrun Interrupt Enable */ -#define CAN_IER_FMPIE1 (1 << 4) /* Bit 4: FIFO Message Pending Interrupt Enable */ -#define CAN_IER_FFIE1 (1 << 5) /* Bit 5: FIFO Full Interrupt Enable */ -#define CAN_IER_FOVIE1 (1 << 6) /* Bit 6: FIFO Overrun Interrupt Enable */ -#define CAN_IER_EWGIE (1 << 8) /* Bit 8: Error Warning Interrupt Enable */ -#define CAN_IER_EPVIE (1 << 9) /* Bit 9: Error Passive Interrupt Enable */ -#define CAN_IER_BOFIE (1 << 10) /* Bit 10: Bus-Off Interrupt Enable */ -#define CAN_IER_LECIE (1 << 11) /* Bit 11: Last Error Code Interrupt Enable */ -#define CAN_IER_ERRIE (1 << 15) /* Bit 15: Error Interrupt Enable */ -#define CAN_IER_WKUIE (1 << 16) /* Bit 16: Wakeup Interrupt Enable */ -#define CAN_IER_SLKIE (1 << 17) /* Bit 17: Sleep Interrupt Enable */ - -/* CAN error status register */ - -#define CAN_ESR_EWGF (1 << 0) /* Bit 0: Error Warning Flag */ -#define CAN_ESR_EPVF (1 << 1) /* Bit 1: Error Passive Flag */ -#define CAN_ESR_BOFF (1 << 2) /* Bit 2: Bus-Off Flag */ -#define CAN_ESR_LEC_SHIFT (4) /* Bits 6-4: Last Error Code */ -#define CAN_ESR_LEC_MASK (7 << CAN_ESR_LEC_SHIFT) -# define CAN_ESR_NOERROR (0 << CAN_ESR_LEC_SHIFT) /* 000: No Error */ -# define CAN_ESR_STUFFERROR (1 << CAN_ESR_LEC_SHIFT) /* 001: Stuff Error */ -# define CAN_ESR_FORMERROR (2 << CAN_ESR_LEC_SHIFT) /* 010: Form Error */ -# define CAN_ESR_ACKERROR (3 << CAN_ESR_LEC_SHIFT) /* 011: Acknowledgment Error */ -# define CAN_ESR_BRECERROR (4 << CAN_ESR_LEC_SHIFT) /* 100: Bit recessive Error */ -# define CAN_ESR_BDOMERROR (5 << CAN_ESR_LEC_SHIFT) /* 101: Bit dominant Error */ -# define CAN_ESR_CRCERRPR (6 << CAN_ESR_LEC_SHIFT) /* 110: CRC Error */ -# define CAN_ESR_SWERROR (7 << CAN_ESR_LEC_SHIFT) /* 111: Set by software */ - -#define CAN_ESR_TEC_SHIFT (16) /* Bits 23-16: LS byte of the 9-bit Transmit Error Counter */ -#define CAN_ESR_TEC_MASK (0xff << CAN_ESR_TEC_SHIF) -#define CAN_ESR_REC_SHIFT (24) /* Bits 31-24: Receive Error Counter */ -#define CAN_ESR_REC_MASK (0xff << CAN_ESR_REC_SHIFT) - -/* CAN bit timing register */ - -#define CAN_BTR_BRP_SHIFT (0) /* Bits 9-0: Baud Rate Prescaler */ -#define CAN_BTR_BRP_MASK (0x03ff << CAN_BTR_BRP_SHIFT) -#define CAN_BTR_TS1_SHIFT (16) /* Bits 19-16: Time Segment 1 */ -#define CAN_BTR_TS1_MASK (0x0f << CAN_BTR_TS1_SHIFT) -#define CAN_BTR_TS2_SHIFT (20) /* Bits 22-20: Time Segment 2 */ -#define CAN_BTR_TS2_MASK (7 << CAN_BTR_TS2_SHIFT) -#define CAN_BTR_SJW_SHIFT (24) /* Bits 25-24: Resynchronization Jump Width */ -#define CAN_BTR_SJW_MASK (3 << CAN_BTR_SJW_SHIFT) -#define CAN_BTR_LBKM (1 << 30) /* Bit 30: Loop Back Mode (Debug) */ -#define CAN_BTR_SILM (1 << 31) /* Bit 31: Silent Mode (Debug) */ - -#define CAN_BTR_BRP_MAX (1024) /* Maximum BTR value (without decrement) */ -#define CAN_BTR_TSEG1_MAX (16) /* Maximum TSEG1 value (without decrement) */ -#define CAN_BTR_TSEG2_MAX (8) /* Maximum TSEG2 value (without decrement) */ - -/* TX mailbox identifier register */ - -#define CAN_TIR_TXRQ (1 << 0) /* Bit 0: Transmit Mailbox Request */ -#define CAN_TIR_RTR (1 << 1) /* Bit 1: Remote Transmission Request */ -#define CAN_TIR_IDE (1 << 2) /* Bit 2: Identifier Extension */ -#define CAN_TIR_EXID_SHIFT (3) /* Bit 3-31: Extended Identifier */ -#define CAN_TIR_EXID_MASK (0x1fffffff << CAN_TIR_EXID_SHIFT) -#define CAN_TIR_STID_SHIFT (21) /* Bits 21-31: Standard Identifier */ -#define CAN_TIR_STID_MASK (0x07ff << CAN_TIR_STID_SHIFT) - -/* Mailbox data length control and time stamp register */ - -#define CAN_TDTR_DLC_SHIFT (0) /* Bits 3:0: Data Length Code */ -#define CAN_TDTR_DLC_MASK (0x0f << CAN_TDTR_DLC_SHIFT) -#define CAN_TDTR_TGT (1 << 8) /* Bit 8: Transmit Global Time */ -#define CAN_TDTR_TIME_SHIFT (16) /* Bits 31:16: Message Time Stamp */ -#define CAN_TDTR_TIME_MASK (0xffff << CAN_TDTR_TIME_SHIFT) - -/* Mailbox data low register */ - -#define CAN_TDLR_DATA0_SHIFT (0) /* Bits 7-0: Data Byte 0 */ -#define CAN_TDLR_DATA0_MASK (0xff << CAN_TDLR_DATA0_SHIFT) -#define CAN_TDLR_DATA1_SHIFT (8) /* Bits 15-8: Data Byte 1 */ -#define CAN_TDLR_DATA1_MASK (0xff << CAN_TDLR_DATA1_SHIFT) -#define CAN_TDLR_DATA2_SHIFT (16) /* Bits 23-16: Data Byte 2 */ -#define CAN_TDLR_DATA2_MASK (0xff << CAN_TDLR_DATA2_SHIFT) -#define CAN_TDLR_DATA3_SHIFT (24) /* Bits 31-24: Data Byte 3 */ -#define CAN_TDLR_DATA3_MASK (0xff << CAN_TDLR_DATA3_SHIFT) - -/* Mailbox data high register */ - -#define CAN_TDHR_DATA4_SHIFT (0) /* Bits 7-0: Data Byte 4 */ -#define CAN_TDHR_DATA4_MASK (0xff << CAN_TDHR_DATA4_SHIFT) -#define CAN_TDHR_DATA5_SHIFT (8) /* Bits 15-8: Data Byte 5 */ -#define CAN_TDHR_DATA5_MASK (0xff << CAN_TDHR_DATA5_SHIFT) -#define CAN_TDHR_DATA6_SHIFT (16) /* Bits 23-16: Data Byte 6 */ -#define CAN_TDHR_DATA6_MASK (0xff << CAN_TDHR_DATA6_SHIFT) -#define CAN_TDHR_DATA7_SHIFT (24) /* Bits 31-24: Data Byte 7 */ -#define CAN_TDHR_DATA7_MASK (0xff << CAN_TDHR_DATA7_SHIFT) - -/* Rx FIFO mailbox identifier register */ - -#define CAN_RIR_RTR (1 << 1) /* Bit 1: Remote Transmission Request */ -#define CAN_RIR_IDE (1 << 2) /* Bit 2: Identifier Extension */ -#define CAN_RIR_EXID_SHIFT (3) /* Bit 3-31: Extended Identifier */ -#define CAN_RIR_EXID_MASK (0x1fffffff << CAN_RIR_EXID_SHIFT) -#define CAN_RIR_STID_SHIFT (21) /* Bits 21-31: Standard Identifier */ -#define CAN_RIR_STID_MASK (0x07ff << CAN_RIR_STID_SHIFT) - -/* Receive FIFO mailbox data length control and time stamp register */ - -#define CAN_RDTR_DLC_SHIFT (0) /* Bits 3:0: Data Length Code */ -#define CAN_RDTR_DLC_MASK (0x0f << CAN_RDTR_DLC_SHIFT) -#define CAN_RDTR_FMI_SHIFT (8) /* Bits 15-8: Filter Match Index */ -#define CAN_RDTR_FMI_MASK (0xff << CAN_RDTR_FM_SHIFT) -#define CAN_RDTR_TIME_SHIFT (16) /* Bits 31:16: Message Time Stamp */ -#define CAN_RDTR_TIME_MASK (0xffff << CAN_RDTR_TIME_SHIFT) - -/* Receive FIFO mailbox data low register */ - -#define CAN_RDLR_DATA0_SHIFT (0) /* Bits 7-0: Data Byte 0 */ -#define CAN_RDLR_DATA0_MASK (0xff << CAN_RDLR_DATA0_SHIFT) -#define CAN_RDLR_DATA1_SHIFT (8) /* Bits 15-8: Data Byte 1 */ -#define CAN_RDLR_DATA1_MASK (0xff << CAN_RDLR_DATA1_SHIFT) -#define CAN_RDLR_DATA2_SHIFT (16) /* Bits 23-16: Data Byte 2 */ -#define CAN_RDLR_DATA2_MASK (0xff << CAN_RDLR_DATA2_SHIFT) -#define CAN_RDLR_DATA3_SHIFT (24) /* Bits 31-24: Data Byte 3 */ -#define CAN_RDLR_DATA3_MASK (0xff << CAN_RDLR_DATA3_SHIFT) - -/* Receive FIFO mailbox data high register */ - -#define CAN_RDHR_DATA4_SHIFT (0) /* Bits 7-0: Data Byte 4 */ -#define CAN_RDHR_DATA4_MASK (0xff << CAN_RDHR_DATA4_SHIFT) -#define CAN_RDHR_DATA5_SHIFT (8) /* Bits 15-8: Data Byte 5 */ -#define CAN_RDHR_DATA5_MASK (0xff << CAN_RDHR_DATA5_SHIFT) -#define CAN_RDHR_DATA6_SHIFT (16) /* Bits 23-16: Data Byte 6 */ -#define CAN_RDHR_DATA6_MASK (0xff << CAN_RDHR_DATA6_SHIFT) -#define CAN_RDHR_DATA7_SHIFT (24) /* Bits 31-24: Data Byte 7 */ -#define CAN_RDHR_DATA7_MASK (0xff << CAN_RDHR_DATA7_SHIFT) - -/* CAN filter master register */ - -#define CAN_FMR_FINIT (1 << 0) /* Bit 0: Filter Init Mode */ - -/* CAN filter mode register */ - -#define CAN_FM1R_FBM_SHIFT (0) /* Bits 13:0: Filter Mode */ -#define CAN_FM1R_FBM_MASK (0x3fff << CAN_FM1R_FBM_SHIFT) - -/* CAN filter scale register */ - -#define CAN_FS1R_FSC_SHIFT (0) /* Bits 13:0: Filter Scale Configuration */ -#define CAN_FS1R_FSC_MASK (0x3fff << CAN_FS1R_FSC_SHIFT) - -/* CAN filter FIFO assignment register */ - -#define CAN_FFA1R_FFA_SHIFT (0) /* Bits 13:0: Filter FIFO Assignment */ -#define CAN_FFA1R_FFA_MASK (0x3fff << CAN_FFA1R_FFA_SHIFT) - -/* CAN filter activation register */ - -#define CAN_FA1R_FACT_SHIFT (0) /* Bits 13:0: Filter Active */ -#define CAN_FA1R_FACT_MASK (0x3fff << CAN_FA1R_FACT_SHIFT) - -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_CAN_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32_comp.h b/arch/arm/src/stm32f0l0g0/hardware/stm32_comp.h deleted file mode 100644 index 5d96fe86f47b4..0000000000000 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32_comp.h +++ /dev/null @@ -1,124 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32_comp.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_COMP_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_COMP_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "chip.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Register Offsets *********************************************************/ - -#define STM32_COMP_CSR_OFFSET 0x001c /* COMP1/COMP2 Control register */ - -/* Register Addresses *******************************************************/ - -#define STM32_COMP_CSR (STM32_COMP_BASE + STM32_COMP_CSR_OFFSET) - -/* Register Bitfield Definitions ********************************************/ - -/* COMP control and status register */ - -#define COMP_CSR_COMP1EN (1 << 0) /* Bit 0: Comparator 1 enable */ -#define COMP_CSR_COMP1SW1 (1 << 1) /* Bit 1: Comparator 1 non inverting input DAC switch */ -#define COMP_CSR_COMP1MODE_SHIFT (2) /* Bits 2-3: Compator 1 mode */ -#define COMP_CSR_COMP1MODE_MASK (3 << COMP_CSR_COMP1MODE_SHIFT) -# define COMP_CSR_COMP1MODE_HIGH (0 << COMP_CSR_COMP1MODE_SHIFT) /* 00: High Speed / full power */ -# define COMP_CSR_COMP1MODE_MEDIUM (1 << COMP_CSR_COMP1MODE_SHIFT) /* 01: Medium Speed / medium power */ -# define COMP_CSR_COMP1MODE_LOW (2 << COMP_CSR_COMP1MODE_SHIFT) /* 10: Low Speed / low-power */ -# define COMP_CSR_COMP1MODE_VLOW (3 << COMP_CSR_COMP1MODE_SHIFT) /* 11: Very-low Speed / ultra-low power */ -#define COMP_CSR_COMP1INSEL_SHIFT (4) /* Bits 4-6: Comparator 1 inverting input selection */ -#define COMP_CSR_COMP1INSEL_MASK (7 << COMP_CSR_COMP1INSEL_SHIFT) -# define COMP_CSR_COMP1INSEL_1P4VREF (0 << COMP_CSR_COMP1INSEL_SHIFT) /* 000: 1/4 of Vrefint */ -# define COMP_CSR_COMP1INSEL_1P2VREF (1 << COMP_CSR_COMP1INSEL_SHIFT) /* 001: 1/2 of Vrefint */ -# define COMP_CSR_COMP1INSEL_3P4VREF (2 << COMP_CSR_COMP1INSEL_SHIFT) /* 010: 3/4 of Vrefint */ -# define COMP_CSR_COMP1INSEL_VREF (3 << COMP_CSR_COMP1INSEL_SHIFT) /* 011: Vrefint */ -# define COMP_CSR_COMP1INSEL_INM4 (4 << COMP_CSR_COMP1INSEL_SHIFT) /* 100: COMP1_INM4 (PA4 DAC_OUT1 if enabled) */ -# define COMP_CSR_COMP1INSEL_INM5 (5 << COMP_CSR_COMP1INSEL_SHIFT) /* 101: COMP1_INM5 (PA5 DAC_OUT2 if present and enabled) */ -# define COMP_CSR_COMP1INSEL_INM6 (6 << COMP_CSR_COMP1INSEL_SHIFT) /* 110: COMP1_INM6 (PA0) */ -#define COMP_CSR_COMP1OUTSEL_SHIFT (8) /* Bits 8-10: Comparator 1 output selection*/ -#define COMP_CSR_COMP1OUTSEL_MASK (7 << COMP_CSR_COMP1OUTSEL_MASK) -# define COMP_CSR_COMP1OUTSEL_NOSEL (0 << COMP_CSR_COMP1OUTSEL_MASK) /* 000: no selection */ -# define COMP_CSR_COMP1OUTSEL_T1BRK (1 << COMP_CSR_COMP1OUTSEL_MASK) /* 001: Timer 1 break input */ -# define COMP_CSR_COMP1OUTSEL_T1ICAP (2 << COMP_CSR_COMP1OUTSEL_MASK) /* 010: Timer 1 Input capture 1 */ -# define COMP_CSR_COMP1OUTSEL_T1OCRC (3 << COMP_CSR_COMP1OUTSEL_MASK) /* 011: Timer 1 OCrefclear input */ -# define COMP_CSR_COMP1OUTSEL_T2ICAP (4 << COMP_CSR_COMP1OUTSEL_MASK) /* 100: Timer 2 input capture 4 */ -# define COMP_CSR_COMP1OUTSEL_T2OCRC (5 << COMP_CSR_COMP1OUTSEL_MASK) /* 101: Timer 2 OCrefclear input */ -# define COMP_CSR_COMP1OUTSEL_T3ICAP (6 << COMP_CSR_COMP1OUTSEL_MASK) /* 110: Timer 3 input capture 1 */ -# define COMP_CSR_COMP1OUTSEL_T3OCRC (7 << COMP_CSR_COMP1OUTSEL_MASK) /* 111: Timer 3 OCrefclear input */ -#define COMP_CSR_COMP1POL (1 << 11) /* Bit 11: Comparator 1 output polarity */ -#define COMP_CSR_COMP1HYST_SHIFT (12) /* Bits 12-13: Comparator 1 hysteresis */ -#define COMP_CSR_COMP1HYST_MASK (3 << COMP_CSR_COMP1HYST_SHIFT) -# define COMP_CSR_COMP1HYST_NOHYST (0 << COMP_CSR_COMP1HYST_MASK) /* 00: No hysteresis */ -# define COMP_CSR_COMP1HYST_LOWHYST (1 << COMP_CSR_COMP1HYST_MASK) /* 01: Low hysteresis */ -# define COMP_CSR_COMP1HYST_MDHYST (2 << COMP_CSR_COMP1HYST_MASK) /* 10: Medium hysteresis */ -# define COMP_CSR_COMP1HYST_HIHYST (3 << COMP_CSR_COMP1HYST_MASK) /* 11: Low hysteresis */ -#define COMP_CSR_COMP1OUT (1 << 14) /* Bit 14: Comparator 1 output */ -#define COMP_CSR_COMP1LOCK (1 << 15) /* Bit 15: Comparator 1 lock */ - -#define COMP_CSR_COMP2EN (1 << 16) /* Bit 16: Comparator 2 enable */ -#define COMP_CSR_COMP2MODE_SHIFT (18) /* Bits 18-19: Compator 2 mode */ -#define COMP_CSR_COMP2MODE_MASK (3 << COMP_CSR_COMP2MODE_SHIFT) -# define COMP_CSR_COMP2MODE_HIGH (0 << COMP_CSR_COMP2MODE_SHIFT) /* 00: High Speed / full power */ -# define COMP_CSR_COMP2MODE_MEDIUM (1 << COMP_CSR_COMP2MODE_SHIFT) /* 01: Medium Speed / medium power */ -# define COMP_CSR_COMP2MODE_LOW (2 << COMP_CSR_COMP2MODE_SHIFT) /* 10: Low Speed / low-power */ -# define COMP_CSR_COMP2MODE_VLOW (3 << COMP_CSR_COMP2MODE_SHIFT) /* 11: Very-low Speed / ultra-low power */ -#define COMP_CSR_COMP2INSEL_SHIFT (20) /* Bits 20-22: Comparator 2 inverting input selection */ -#define COMP_CSR_COMP2INSEL_MASK (7 << COMP_CSR_COMP2INSEL_SHIFT) -# define COMP_CSR_COMP2INSEL_1P4VREF (0 << COMP_CSR_COMP2INSEL_SHIFT) /* 000: 1/4 of Vrefint */ -# define COMP_CSR_COMP2INSEL_1P2VREF (1 << COMP_CSR_COMP2INSEL_SHIFT) /* 001: 1/2 of Vrefint */ -# define COMP_CSR_COMP2INSEL_3P4VREF (2 << COMP_CSR_COMP2INSEL_SHIFT) /* 010: 3/4 of Vrefint */ -# define COMP_CSR_COMP2INSEL_VREF (3 << COMP_CSR_COMP2INSEL_SHIFT) /* 011: Vrefint */ -# define COMP_CSR_COMP2INSEL_INM4 (4 << COMP_CSR_COMP2INSEL_SHIFT) /* 100: COMP1_INM4 (PA4 DAC_OUT1 if enabled) */ -# define COMP_CSR_COMP2INSEL_INM5 (5 << COMP_CSR_COMP2INSEL_SHIFT) /* 101: COMP1_INM5 (PA5 DAC_OUT2 if present and enabled) */ -# define COMP_CSR_COMP2INSEL_INM6 (6 << COMP_CSR_COMP2INSEL_SHIFT) /* 110: COMP1_INM6 (PA2) */ -#define COMP_CSR_WNDWEN (1 << 23) /* Bit 23: Window mode enable */ -#define COMP_CSR_COMP2OUTSEL_SHIFT (24) /* Bits 24-26: Comparator 1 output selection*/ -#define COMP_CSR_COMP2OUTSEL_MASK (7 << COMP_CSR_COMP2OUTSEL_MASK) -# define COMP_CSR_COMP2OUTSEL_NOSEL (0 << COMP_CSR_COMP2OUTSEL_MASK) /* 000: no selection */ -# define COMP_CSR_COMP2OUTSEL_T1BRK (1 << COMP_CSR_COMP2OUTSEL_MASK) /* 001: Timer 1 break input */ -# define COMP_CSR_COMP2OUTSEL_T1ICAP (2 << COMP_CSR_COMP2OUTSEL_MASK) /* 010: Timer 1 Input capture 1 */ -# define COMP_CSR_COMP2OUTSEL_T1OCRC (3 << COMP_CSR_COMP2OUTSEL_MASK) /* 011: Timer 1 OCrefclear input */ -# define COMP_CSR_COMP2OUTSEL_T2ICAP (4 << COMP_CSR_COMP2OUTSEL_MASK) /* 100: Timer 2 input capture 4 */ -# define COMP_CSR_COMP2OUTSEL_T2OCRC (5 << COMP_CSR_COMP2OUTSEL_MASK) /* 101: Timer 2 OCrefclear input */ -# define COMP_CSR_COMP2OUTSEL_T3ICAP (6 << COMP_CSR_COMP2OUTSEL_MASK) /* 110: Timer 3 input capture 1 */ -# define COMP_CSR_COMP2OUTSEL_T3OCRC (7 << COMP_CSR_COMP2OUTSEL_MASK) /* 111: Timer 3 OCrefclear input */ -#define COMP_CSR_COMP2POL (1 << 27) /* Bit 27: Comparator 2 output polarity */ -#define COMP_CSR_COMP2HYST_SHIFT (12) /* Bits 12-13: Comparator 1 hysteresis */ -#define COMP_CSR_COMP2HYST_MASK (3 << COMP_CSR_COMP2HYST_SHIFT) -# define COMP_CSR_COMP2HYST_NOHYST (0 << COMP_CSR_COMP2HYST_MASK) /* 00: No hysteresis */ -# define COMP_CSR_COMP2HYST_LOWHYST (1 << COMP_CSR_COMP2HYST_MASK) /* 01: Low hysteresis */ -# define COMP_CSR_COMP2HYST_MDHYST (2 << COMP_CSR_COMP2HYST_MASK) /* 10: Medium hysteresis */ -# define COMP_CSR_COMP2HYST_HIHYST (3 << COMP_CSR_COMP2HYST_MASK) /* 11: Low hysteresis */ -#define COMP_CSR_COMP2OUT (1 << 14) /* Bit 14: Comparator 1 output */ -#define COMP_CSR_COMP2LOCK (1 << 15) /* Bit 15: Comparator 1 lock */ - -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_COMP_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32_dac.h b/arch/arm/src/stm32f0l0g0/hardware/stm32_dac.h deleted file mode 100644 index 7b5262432c060..0000000000000 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32_dac.h +++ /dev/null @@ -1,211 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32_dac.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_DAC_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_DAC_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include "chip.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Register Offsets *********************************************************/ - -#define STM32_DAC_CR_OFFSET 0x0000 /* DAC control register */ -#define STM32_DAC_SWTRIGR_OFFSET 0x0004 /* DAC software trigger register */ -#define STM32_DAC_DHR12R1_OFFSET 0x0008 /* DAC channel 1 12-bit right-aligned data holding register */ -#define STM32_DAC_DHR12L1_OFFSET 0x000c /* DAC channel 1 12-bit left aligned data holding register */ -#define STM32_DAC_DHR8R1_OFFSET 0x0010 /* DAC channel 1 8-bit right aligned data holding register */ -#define STM32_DAC_DHR12R2_OFFSET 0x0014 /* DAC channel 2 12-bit right aligned data holding register */ -#define STM32_DAC_DHR12L2_OFFSET 0x0018 /* DAC channel 2 12-bit left aligned data holding register */ -#define STM32_DAC_DHR8R2_OFFSET 0x001c /* DAC channel 2 8-bit right-aligned data holding register */ -#define STM32_DAC_DHR12RD_OFFSET 0x0020 /* Dual DAC 12-bit right-aligned data holding register */ -#define STM32_DAC_DHR12LD_OFFSET 0x0024 /* DUAL DAC 12-bit left aligned data holding register */ -#define STM32_DAC_DHR8RD_OFFSET 0x0028 /* DUAL DAC 8-bit right aligned data holding register */ -#define STM32_DAC_DOR1_OFFSET 0x002c /* DAC channel 1 data output register */ -#define STM32_DAC_DOR2_OFFSET 0x0030 /* DAC channel 2 data output register */ -#define STM32_DAC_SR_OFFSET 0x0034 /* DAC status register */ - -/* Register Addresses *******************************************************/ - -/* DAC */ - -#define STM32_DAC1_CR (STM32_DAC1_BASE + STM32_DAC_CR_OFFSET) -#define STM32_DAC1_SWTRIGR (STM32_DAC1_BASE + STM32_DAC_SWTRIGR_OFFSET) -#define STM32_DAC1_DHR12R1 (STM32_DAC1_BASE + STM32_DAC_DHR12R1_OFFSET) -#define STM32_DAC1_DHR12L1 (STM32_DAC1_BASE + STM32_DAC_DHR12L1_OFFSET) -#define STM32_DAC1_DHR8R1 (STM32_DAC1_BASE + STM32_DAC_DHR8R1_OFFSET) -#define STM32_DAC1_DHR12R2 (STM32_DAC1_BASE + STM32_DAC_DHR12R2_OFFSET) -#define STM32_DAC1_DHR12L2 (STM32_DAC1_BASE + STM32_DAC_DHR12L2_OFFSET) -#define STM32_DAC1_DHR8R2 (STM32_DAC1_BASE + STM32_DAC_DHR8R2_OFFSET) -#define STM32_DAC1_DHR12RD (STM32_DAC1_BASE + STM32_DAC_DHR12RD_OFFSET) -#define STM32_DAC1_DHR12LD (STM32_DAC1_BASE + STM32_DAC_DHR12LD_OFFSET) -#define STM32_DAC1_DHR8RD (STM32_DAC1_BASE + STM32_DAC_DHR8RD_OFFSET) -#define STM32_DAC1_DOR1 (STM32_DAC1_BASE + STM32_DAC_DOR1_OFFSET) -#define STM32_DAC1_DOR2 (STM32_DAC1_BASE + STM32_DAC_DOR2_OFFSET) -#define STM32_DAC1_SR (STM32_DAC1_BASE + STM32_DAC_SR_OFFSET) - -/* Register Bitfield Definitions ********************************************/ - -/* DAC control register */ - -/* These definitions may be used with the full, 32-bit register */ - -#define DAC_CR_EN1 (1 << 0) /* Bit 0: DAC channel 1 enable */ -#define DAC_CR_BOFF1 (1 << 1) /* Bit 1: DAC channel 1 output buffer disable */ -#define DAC_CR_TEN1 (1 << 2) /* Bit 2: DAC channel 1 trigger enable */ -#define DAC_CR_TSEL1_SHIFT (3) /* Bits 3-5: DAC channel 1 trigger selection */ -#define DAC_CR_TSEL1_MASK (7 << DAC_CR_TSEL1_SHIFT) -# define DAC_CR_TSEL1_TIM6 (0 << DAC_CR_TSEL1_SHIFT) /* Timer 6 TRGO event */ -# define DAC_CR_TSEL1_TIM3 (1 << DAC_CR_TSEL1_SHIFT) /* Timer 3 TRGO event */ -# define DAC_CR_TSEL1_TIM7 (2 << DAC_CR_TSEL1_SHIFT) /* Timer 7 TRGO event */ -# define DAC_CR_TSEL1_TIM15 (3 << DAC_CR_TSEL1_SHIFT) /* Timer 15 TRGO event, or */ -# define DAC_CR_TSEL1_TIM2 (4 << DAC_CR_TSEL1_SHIFT) /* Timer 2 TRGO event */ -# define DAC_CR_TSEL1_EXT9 (6 << DAC_CR_TSEL1_SHIFT) /* External line9 */ -# define DAC_CR_TSEL1_SW (7 << DAC_CR_TSEL1_SHIFT) /* Software trigger */ - -#define DAC_CR_WAVE1_SHIFT (6) /* Bits 6-7: DAC channel 1 noise/triangle wave generation */ -#define DAC_CR_WAVE1_MASK (3 << DAC_CR_WAVE1_SHIFT) -# define DAC_CR_WAVE1_DISABLED (0 << DAC_CR_WAVE1_SHIFT) /* Wave generation disabled */ -# define DAC_CR_WAVE1_NOISE (1 << DAC_CR_WAVE1_SHIFT) /* Noise wave generation enabled */ -# define DAC_CR_WAVE1_TRIANGLE (2 << DAC_CR_WAVE1_SHIFT) /* Triangle wave generation enabled */ - -#define DAC_CR_MAMP1_SHIFT (8) /* Bits 8-11: DAC channel 1 mask/amplitude selector */ -#define DAC_CR_MAMP1_MASK (15 << DAC_CR_MAMP1_SHIFT) -# define DAC_CR_MAMP1_AMP1 (0 << DAC_CR_MAMP1_SHIFT) /* Unmask bit0 of LFSR/triangle amplitude=1 */ -# define DAC_CR_MAMP1_AMP3 (1 << DAC_CR_MAMP1_SHIFT) /* Unmask bits[1:0] of LFSR/triangle amplitude=3 */ -# define DAC_CR_MAMP1_AMP7 (2 << DAC_CR_MAMP1_SHIFT) /* Unmask bits[2:0] of LFSR/triangle amplitude=7 */ -# define DAC_CR_MAMP1_AMP15 (3 << DAC_CR_MAMP1_SHIFT) /* Unmask bits[3:0] of LFSR/triangle amplitude=15 */ -# define DAC_CR_MAMP1_AMP31 (4 << DAC_CR_MAMP1_SHIFT) /* Unmask bits[4:0] of LFSR/triangle amplitude=31 */ -# define DAC_CR_MAMP1_AMP63 (5 << DAC_CR_MAMP1_SHIFT) /* Unmask bits[5:0] of LFSR/triangle amplitude=63 */ -# define DAC_CR_MAMP1_AMP127 (6 << DAC_CR_MAMP1_SHIFT) /* Unmask bits[6:0] of LFSR/triangle amplitude=127 */ -# define DAC_CR_MAMP1_AMP255 (7 << DAC_CR_MAMP1_SHIFT) /* Unmask bits[7:0] of LFSR/triangle amplitude=255 */ -# define DAC_CR_MAMP1_AMP511 (8 << DAC_CR_MAMP1_SHIFT) /* Unmask bits[8:0] of LFSR/triangle amplitude=511 */ -# define DAC_CR_MAMP1_AMP1023 (9 << DAC_CR_MAMP1_SHIFT) /* Unmask bits[9:0] of LFSR/triangle amplitude=1023 */ -# define DAC_CR_MAMP1_AMP2047 (10 << DAC_CR_MAMP1_SHIFT) /* Unmask bits[10:0] of LFSR/triangle amplitude=2047 */ -# define DAC_CR_MAMP1_AMP4095 (11 << DAC_CR_MAMP1_SHIFT) /* Unmask bits[11:0] of LFSR/triangle amplitude=4095 */ - -#define DAC_CR_DMAEN1 (1 << 12) /* Bit 12: DAC channel 1 DMA enable */ -#define DAC_CR_DMAUDRIE1 (1 << 13) /* Bit 13: DAC channel 1 DMA Underrun Interrupt enable */ - -#define DAC_CR_EN2 (1 << 16) /* Bit 16: DAC channel 2 enable */ -#define DAC_CR_BOFF2 (1 << 17) /* Bit 17: DAC channel 2 output buffer disable */ -#define DAC_CR_TEN2 (1 << 18) /* Bit 18: DAC channel 2 trigger enable */ -#define DAC_CR_TSEL2_SHIFT (19) /* Bits 19-21: DAC channel 2 trigger selection */ -#define DAC_CR_TSEL2_MASK (7 << DAC_CR_TSEL2_SHIFT) -# define DAC_CR_TSEL2_TIM6 (0 << DAC_CR_TSEL2_SHIFT) /* Timer 6 TRGO event */ -# define DAC_CR_TSEL2_TIM3 (1 << DAC_CR_TSEL2_SHIFT) /* Timer 3 TRGO event */ -# define DAC_CR_TSEL2_TIM7 (2 << DAC_CR_TSEL2_SHIFT) /* Timer 7 TRGO event */ -# define DAC_CR_TSEL2_TIM15 (3 << DAC_CR_TSEL2_SHIFT) /* Timer 15 TRGO event */ -# define DAC_CR_TSEL2_TIM2 (4 << DAC_CR_TSEL2_SHIFT) /* Timer 2 TRGO event */ -# define DAC_CR_TSEL2_EXT9 (6 << DAC_CR_TSEL2_SHIFT) /* External line9 */ -# define DAC_CR_TSEL2_SW (7 << DAC_CR_TSEL2_SHIFT) /* Software trigger */ - -#define DAC_CR_WAVE2_SHIFT (22) /* Bit 22-23: DAC channel 2 noise/triangle wave generation enable */ -#define DAC_CR_WAVE2_MASK (3 << DAC_CR_WAVE2_SHIFT) -# define DAC_CR_WAVE2_DISABLED (0 << DAC_CR_WAVE2_SHIFT) /* Wave generation disabled */ -# define DAC_CR_WAVE2_NOISE (1 << DAC_CR_WAVE2_SHIFT) /* Noise wave generation enabled */ -# define DAC_CR_WAVE2_TRIANGLE (2 << DAC_CR_WAVE2_SHIFT) /* Triangle wave generation enabled */ - -#define DAC_CR_MAMP2_SHIFT (24) /* Bit 24-27: DAC channel 2 mask/amplitude selector */ -#define DAC_CR_MAMP2_MASK (15 << DAC_CR_MAMP2_SHIFT) -# define DAC_CR_MAMP2_AMP1 (0 << DAC_CR_MAMP2_SHIFT) /* Unmask bit0 of LFSR/triangle amplitude=1 */ -# define DAC_CR_MAMP2_AMP3 (1 << DAC_CR_MAMP2_SHIFT) /* Unmask bits[1:0] of LFSR/triangle amplitude=3 */ -# define DAC_CR_MAMP2_AMP7 (2 << DAC_CR_MAMP2_SHIFT) /* Unmask bits[2:0] of LFSR/triangle amplitude=7 */ -# define DAC_CR_MAMP2_AMP15 (3 << DAC_CR_MAMP2_SHIFT) /* Unmask bits[3:0] of LFSR/triangle amplitude=15 */ -# define DAC_CR_MAMP2_AMP31 (4 << DAC_CR_MAMP2_SHIFT) /* Unmask bits[4:0] of LFSR/triangle amplitude=31 */ -# define DAC_CR_MAMP2_AMP63 (5 << DAC_CR_MAMP2_SHIFT) /* Unmask bits[5:0] of LFSR/triangle amplitude=63 */ -# define DAC_CR_MAMP2_AMP127 (6 << DAC_CR_MAMP2_SHIFT) /* Unmask bits[6:0] of LFSR/triangle amplitude=127 */ -# define DAC_CR_MAMP2_AMP255 (7 << DAC_CR_MAMP2_SHIFT) /* Unmask bits[7:0] of LFSR/triangle amplitude=255 */ -# define DAC_CR_MAMP2_AMP511 (8 << DAC_CR_MAMP2_SHIFT) /* Unmask bits[8:0] of LFSR/triangle amplitude=511 */ -# define DAC_CR_MAMP2_AMP1023 (9 << DAC_CR_MAMP2_SHIFT) /* Unmask bits[9:0] of LFSR/triangle amplitude=1023 */ -# define DAC_CR_MAMP2_AMP2047 (10 << DAC_CR_MAMP2_SHIFT) /* Unmask bits[10:0] of LFSR/triangle amplitude=2047 */ -# define DAC_CR_MAMP2_AMP4095 (11 << DAC_CR_MAMP2_SHIFT) /* Unmask bits[11:0] of LFSR/triangle amplitude=4095 */ - -#define DAC_CR_DMAEN2 (1 << 28) /* Bit 28: DAC channel 2 DMA enable */ -#define DAC_CR_DMAUDRIE2 (1 << 29) /* Bit 29: DAC channel 2 DMA underrun interrupt enable */ - -/* DAC software trigger register */ - -#define DAC_SWTRIGR_SWTRIG(n) (1 << ((n)-1)) -#define DAC_SWTRIGR_SWTRIG1 (1 << 0) /* Bit 0: DAC channel 1 software trigger */ -#define DAC_SWTRIGR_SWTRIG2 (1 << 1) /* Bit 1: DAC channel 2 software trigger */ - -/* DAC channel 1/2 12-bit right-aligned data holding register */ - -#define DAC_DHR12R_MASK (0x0fff) - -/* DAC channel 1/2 12-bit left aligned data holding register */ - -#define DAC_DHR12L_MASK (0xfff0) - -/* DAC channel 1/2 8-bit right aligned data holding register */ - -#define DAC_DHR8R_MASK (0x00ff) - -/* Dual DAC 12-bit right-aligned data holding register */ - -#define DAC_DHR12RD_DACC_SHIFT(n) (((n)-1) << 4) -#define DAC_DHR12RD_DACC_MASK(n) (0xfff << DAC_DHR12RD_DACC_SHIFT(n)) - -#define DAC_DHR12RD_DACC1_SHIFT (0) /* Bits 0-11: DAC channel 1 12-bit right-aligned data */ -#define DAC_DHR12RD_DACC1_MASK (0xfff << DAC_DHR12RD_DACC1_SHIFT) -#define DAC_DHR12RD_DACC2_SHIFT (16) /* Bits 16-27: DAC channel 2 12-bit right-aligned data */ -#define DAC_DHR12RD_DACC2_MASK (0xfff << DAC_DHR12RD_DACC2_SHIFT) - -/* Dual DAC 12-bit left-aligned data holding register */ - -#define DAC_DHR12LD_DACC_SHIFT(n) ((((n)-1) << 4) + 4) -#define DAC_DHR12LD_DACC_MASK(n) (0xfff << DAC_DHR12LD_DACC_SHIFT(n)) - -#define DAC_DHR12LD_DACC1_SHIFT (4) /* Bits 4-15: DAC channel 1 12-bit left-aligned data */ -#define DAC_DHR12LD_DACC1_MASK (0xfff << DAC_DHR12LD_DACC1_SHIFT) -#define DAC_DHR12LD_DACC2_SHIFT (20) /* Bits 20-31: DAC channel 2 12-bit left-aligned data */ -#define DAC_DHR12LD_DACC2_MASK (0xfff << DAC_DHR12LD_DACC2_SHIFT) - -/* DUAL DAC 8-bit right aligned data holding register */ - -#define DAC_DHR8RD_DACC_SHIFT(n) (((n)-1) << 3) -#define DAC_DHR8RD_DACC_MASK(n) (0xff << DAC_DHR8RD_DACC_SHIFT(n)) - -#define DAC_DHR8RD_DACC1_SHIFT (0) /* Bits 0-7: DAC channel 1 8-bit right-aligned data */ -#define DAC_DHR8RD_DACC1_MASK (0xff << DAC_DHR8RD_DACC1_SHIFT) -#define DAC_DHR8RD_DACC2_SHIFT (8) /* Bits 8-15: DAC channel 2 8-bit right-aligned data */ -#define DAC_DHR8RD_DACC2_MASK (0xff << DAC_DHR8RD_DACC2_SHIFT) - -/* DAC channel 1/2 data output register */ - -#define DAC_DOR_MASK (0x0fff) - -/* DAC status register */ - -#define DAC_SR_DMAUDR(n) (1 << ((((n)-1) << 4) + 13)) -#define DAC_SR_DMAUDR1 (1 << 13) /* Bit 13: DAC channel 1 DMA underrun flag */ -#define DAC_SR_DMAUDR2 (1 << 29) /* Bit 29: DAC channel 2 DMA underrun flag */ - -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_DAC_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32_dbgmcu.h b/arch/arm/src/stm32f0l0g0/hardware/stm32_dbgmcu.h deleted file mode 100644 index 0e5efadeaf7b3..0000000000000 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32_dbgmcu.h +++ /dev/null @@ -1,80 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32_dbgmcu.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_DBGMCU_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_DBGMCU_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include "chip.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Register Offsets *********************************************************/ - -#define STM32_DBGMCU_IDCODE 0x40015800 /* MCU identifier */ -#define STM32_DBGMCU_CR 0x40015804 /* MCU debug */ -#define STM32_DBGMCU_APB1_FZ 0x40015808 /* Debug MCU APB1 freeze register */ -#define STM32_DBGMCU_APB2_FZ 0x4001580c /* Debug MCU APB2 freeze register */ - -/* Register Bitfield Definitions ********************************************/ - -/* MCU identifier */ - -#define DBGMCU_IDCODE_DEVID_SHIFT (0) /* Bits 11-0: Device Identifier */ -#define DBGMCU_IDCODE_DEVID_MASK (0x0fff << DBGMCU_IDCODE_DEVID_SHIFT) -#define DBGMCU_IDCODE_REVID_SHIFT (16) /* Bits 31-16: Revision Identifier */ -#define DBGMCU_IDCODE_REVID_MASK (0xffff << DBGMCU_IDCODE_REVID_SHIFT) - -/* MCU debug */ - -#define DBGMCU_CR_SLEEP (1 << 0) /* Bit 0: Debug Sleep Mode */ -#define DBGMCU_CR_STOP (1 << 1) /* Bit 1: Debug Stop Mode */ -#define DBGMCU_CR_STANDBY (1 << 2) /* Bit 2: Debug Standby mode */ - -/* Debug MCU APB freeze register 1 */ - -#ifdef CONFIG_ARCH_CHIP_STM32C0 -# define DBGMCU_APB1_TIM2STOP (1 << 0) /* Bit 0: TIM2 stopped when core is halted */ -# define DBGMCU_APB1_TIM3STOP (1 << 1) /* Bit 1: TIM3 stopped when core is halted */ -# define DBGMCU_APB1_RTCSTOP (1 << 10) /* Bit 10: RTC stopped when core is halted */ -# define DBGMCU_APB1_WWDGSTOP (1 << 11) /* Bit 11: WWDG stopped when core is halted */ -# define DBGMCU_APB1_IWDGSTOP (1 << 12) /* Bit 12: IWDG stopped when core is halted */ -# define DBGMCU_APB1_I2C1STOP (1 << 21) /* Bit 21: SMBUS timeout mode stopped when Core is halted */ -#endif - -/* Debug MCU APB freeze register 2 */ - -#ifdef CONFIG_ARCH_CHIP_STM32C0 -# define DBGMCU_APB1_TIM1STOP (1 << 11) /* Bit 1: TIM1 stopped when core is halted */ -# define DBGMCU_APB1_TIM14STOP (1 << 15) /* Bit 15: TIM14 stopped when core is halted */ -# define DBGMCU_APB1_TIM15STOP (1 << 16) /* Bit 16: TIM15 stopped when core is halted */ -# define DBGMCU_APB1_TIM16STOP (1 << 17) /* Bit 16: TIM16 stopped when core is halted */ -# define DBGMCU_APB1_TIM17STOP (1 << 18) /* Bit 16: TIM17 stopped when core is halted */ -#endif - -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_DBGMCU_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32_dma_v1.h b/arch/arm/src/stm32f0l0g0/hardware/stm32_dma_v1.h deleted file mode 100644 index cdae49a53ee25..0000000000000 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32_dma_v1.h +++ /dev/null @@ -1,548 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32_dma_v1.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_DMA_V1_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_DMA_V1_H - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* This is implementation for - * STM32 DMA IP version 1 - F0, F1, F3, L0, L1, L4 - */ - -#define HAVE_IP_DMA_V1 1 -#undef HAVE_IP_DMA_V2 - -/* F0, L0, L4 have additional CSELR register */ - -#if defined(CONFIG_ARCH_CHIP_STM32L0) -# define DMA_HAVE_CSELR 1 -#endif - -/* 2 DMA controllers */ - -#define DMA1 (0) -#define DMA2 (1) - -/* 12 Channels Total: 7 DMA1 Channels(1-7) and 5 DMA2 channels (1-5) */ - -#define DMA_CHAN1 (0) -#define DMA_CHAN2 (1) -#define DMA_CHAN3 (2) -#define DMA_CHAN4 (3) -#define DMA_CHAN5 (4) -#define DMA_CHAN6 (5) -#define DMA_CHAN7 (6) - -/* Register Offsets *********************************************************/ - -#define STM32_DMA_ISR_OFFSET 0x0000 /* DMA interrupt status register */ -#define STM32_DMA_IFCR_OFFSET 0x0004 /* DMA interrupt flag clear register */ - -#define STM32_DMACHAN_OFFSET(n) (0x0014 * (n)) -#define STM32_DMACHAN1_OFFSET 0x0000 -#define STM32_DMACHAN2_OFFSET 0x0014 -#define STM32_DMACHAN3_OFFSET 0x0028 -#define STM32_DMACHAN4_OFFSET 0x003c -#define STM32_DMACHAN5_OFFSET 0x0050 -#define STM32_DMACHAN6_OFFSET 0x0064 -#define STM32_DMACHAN7_OFFSET 0x0078 - -#define STM32_DMACHAN_CCR_OFFSET 0x0008 /* DMA channel configuration register */ -#define STM32_DMACHAN_CNDTR_OFFSET 0x000c /* DMA channel number of data register */ -#define STM32_DMACHAN_CPAR_OFFSET 0x0010 /* DMA channel peripheral address register */ -#define STM32_DMACHAN_CMAR_OFFSET 0x0014 /* DMA channel 1 memory address register */ - -#define STM32_DMA_CCR_OFFSET(n) (STM32_DMACHAN_CCR_OFFSET + STM32_DMACHAN_OFFSET(n)) -#define STM32_DMA_CNDTR_OFFSET(n) (STM32_DMACHAN_CNDTR_OFFSET + STM32_DMACHAN_OFFSET(n)) -#define STM32_DMA_CPAR_OFFSET(n) (STM32_DMACHAN_CPAR_OFFSET + STM32_DMACHAN_OFFSET(n)) -#define STM32_DMA_CMAR_OFFSET(n) (STM32_DMACHAN_CMAR_OFFSET + STM32_DMACHAN_OFFSET(n)) - -#define STM32_DMA_CCR1_OFFSET 0x0008 /* DMA channel 1 configuration register */ -#define STM32_DMA_CCR2_OFFSET 0x001c /* DMA channel 2 configuration register */ -#define STM32_DMA_CCR3_OFFSET 0x0030 /* DMA channel 3 configuration register */ -#define STM32_DMA_CCR4_OFFSET 0x0044 /* DMA channel 4 configuration register */ -#define STM32_DMA_CCR5_OFFSET 0x0058 /* DMA channel 5 configuration register */ -#define STM32_DMA_CCR6_OFFSET 0x006c /* DMA channel 6 configuration register */ -#define STM32_DMA_CCR7_OFFSET 0x0080 /* DMA channel 7 configuration register */ - -#define STM32_DMA_CNDTR1_OFFSET 0x000c /* DMA channel 1 number of data register */ -#define STM32_DMA_CNDTR2_OFFSET 0x0020 /* DMA channel 2 number of data register */ -#define STM32_DMA_CNDTR3_OFFSET 0x0034 /* DMA channel 3 number of data register */ -#define STM32_DMA_CNDTR4_OFFSET 0x0048 /* DMA channel 4 number of data register */ -#define STM32_DMA_CNDTR5_OFFSET 0x005c /* DMA channel 5 number of data register */ -#define STM32_DMA_CNDTR6_OFFSET 0x0070 /* DMA channel 6 number of data register */ -#define STM32_DMA_CNDTR7_OFFSET 0x0084 /* DMA channel 7 number of data register */ - -#define STM32_DMA_CPAR1_OFFSET 0x0010 /* DMA channel 1 peripheral address register */ -#define STM32_DMA_CPAR2_OFFSET 0x0024 /* DMA channel 2 peripheral address register */ -#define STM32_DMA_CPAR3_OFFSET 0x0038 /* DMA channel 3 peripheral address register */ -#define STM32_DMA_CPAR4_OFFSET 0x004c /* DMA channel 4 peripheral address register */ -#define STM32_DMA_CPAR5_OFFSET 0x0060 /* DMA channel 5 peripheral address register */ -#define STM32_DMA_CPAR6_OFFSET 0x0074 /* DMA channel 6 peripheral address register */ -#define STM32_DMA_CPAR7_OFFSET 0x0088 /* DMA channel 7 peripheral address register */ - -#define STM32_DMA_CMAR1_OFFSET 0x0014 /* DMA channel 1 memory address register */ -#define STM32_DMA_CMAR2_OFFSET 0x0028 /* DMA channel 2 memory address register */ -#define STM32_DMA_CMAR3_OFFSET 0x003c /* DMA channel 3 memory address register */ -#define STM32_DMA_CMAR4_OFFSET 0x0050 /* DMA channel 4 memory address register */ -#define STM32_DMA_CMAR5_OFFSET 0x0064 /* DMA channel 5 memory address register */ -#define STM32_DMA_CMAR6_OFFSET 0x0078 /* DMA channel 6 memory address register */ -#define STM32_DMA_CMAR7_OFFSET 0x008c /* DMA channel 7 memory address register */ - -#ifdef DMA_HAVE_CSELR -# define STM32_DMA_CSELR_OFFSET 0x00a8 /* DMA channel selection register */ -#endif - -/* Register Addresses *******************************************************/ - -#define STM32_DMA1_ISRC (STM32_DMA1_BASE + STM32_DMA_ISR_OFFSET) -#define STM32_DMA1_IFCR (STM32_DMA1_BASE + STM32_DMA_IFCR_OFFSET) - -#define STM32_DMA1_CCR(n) (STM32_DMA1_BASE + STM32_DMA_CCR_OFFSET(n)) -#define STM32_DMA1_CCR1 (STM32_DMA1_BASE + STM32_DMA_CCR1_OFFSET) -#define STM32_DMA1_CCR2 (STM32_DMA1_BASE + STM32_DMA_CCR2_OFFSET) -#define STM32_DMA1_CCR3 (STM32_DMA1_BASE + STM32_DMA_CCR3_OFFSET) -#define STM32_DMA1_CCR4 (STM32_DMA1_BASE + STM32_DMA_CCR4_OFFSET) -#define STM32_DMA1_CCR5 (STM32_DMA1_BASE + STM32_DMA_CCR5_OFFSET) -#define STM32_DMA1_CCR6 (STM32_DMA1_BASE + STM32_DMA_CCR6_OFFSET) -#define STM32_DMA1_CCR7 (STM32_DMA1_BASE + STM32_DMA_CCR7_OFFSET) - -#define STM32_DMA1_CNDTR(n) (STM32_DMA1_BASE + STM32_DMA_CNDTR_OFFSET(n)) -#define STM32_DMA1_CNDTR1 (STM32_DMA1_BASE + STM32_DMA_CNDTR1_OFFSET) -#define STM32_DMA1_CNDTR2 (STM32_DMA1_BASE + STM32_DMA_CNDTR2_OFFSET) -#define STM32_DMA1_CNDTR3 (STM32_DMA1_BASE + STM32_DMA_CNDTR3_OFFSET) -#define STM32_DMA1_CNDTR4 (STM32_DMA1_BASE + STM32_DMA_CNDTR4_OFFSET) -#define STM32_DMA1_CNDTR5 (STM32_DMA1_BASE + STM32_DMA_CNDTR5_OFFSET) -#define STM32_DMA1_CNDTR6 (STM32_DMA1_BASE + STM32_DMA_CNDTR6_OFFSET) -#define STM32_DMA1_CNDTR7 (STM32_DMA1_BASE + STM32_DMA_CNDTR7_OFFSET) - -#define STM32_DMA1_CPAR(n) (STM32_DMA1_BASE + STM32_DMA_CPAR_OFFSET(n)) -#define STM32_DMA1_CPAR1 (STM32_DMA1_BASE + STM32_DMA_CPAR1_OFFSET) -#define STM32_DMA1_CPAR2 (STM32_DMA1_BASE + STM32_DMA_CPAR2_OFFSET) -#define STM32_DMA1_CPAR3 (STM32_DMA1_BASE + STM32_DMA_CPAR3_OFFSET) -#define STM32_DMA1_CPAR4 (STM32_DMA1_BASE + STM32_DMA_CPAR4_OFFSET) -#define STM32_DMA1_CPAR5 (STM32_DMA1_BASE + STM32_DMA_CPAR5_OFFSET) -#define STM32_DMA1_CPAR6 (STM32_DMA1_BASE + STM32_DMA_CPAR6_OFFSET) -#define STM32_DMA1_CPAR7 (STM32_DMA1_BASE + STM32_DMA_CPAR7_OFFSET) - -#define STM32_DMA1_CMAR(n) (STM32_DMA1_BASE + STM32_DMA_CMAR_OFFSET(n)) -#define STM32_DMA1_CMAR1 (STM32_DMA1_BASE + STM32_DMA_CMAR1_OFFSET) -#define STM32_DMA1_CMAR2 (STM32_DMA1_BASE + STM32_DMA_CMAR2_OFFSET) -#define STM32_DMA1_CMAR3 (STM32_DMA1_BASE + STM32_DMA_CMAR3_OFFSET) -#define STM32_DMA1_CMAR4 (STM32_DMA1_BASE + STM32_DMA_CMAR4_OFFSET) -#define STM32_DMA1_CMAR5 (STM32_DMA1_BASE + STM32_DMA_CMAR5_OFFSET) -#define STM32_DMA1_CMAR6 (STM32_DMA1_BASE + STM32_DMA_CMAR6_OFFSET) -#define STM32_DMA1_CMAR7 (STM32_DMA1_BASE + STM32_DMA_CMAR7_OFFSET) - -#define STM32_DMA2_ISRC (STM32_DMA2_BASE + STM32_DMA_ISR_OFFSET) -#define STM32_DMA2_IFCR (STM32_DMA2_BASE + STM32_DMA_IFCR_OFFSET) - -#define STM32_DMA2_CCR(n) (STM32_DMA2_BASE + STM32_DMA_CCR_OFFSET(n)) -#define STM32_DMA2_CCR1 (STM32_DMA2_BASE + STM32_DMA_CCR1_OFFSET) -#define STM32_DMA2_CCR2 (STM32_DMA2_BASE + STM32_DMA_CCR2_OFFSET) -#define STM32_DMA2_CCR3 (STM32_DMA2_BASE + STM32_DMA_CCR3_OFFSET) -#define STM32_DMA2_CCR4 (STM32_DMA2_BASE + STM32_DMA_CCR4_OFFSET) -#define STM32_DMA2_CCR5 (STM32_DMA2_BASE + STM32_DMA_CCR5_OFFSET) - -#define STM32_DMA2_CNDTR(n) (STM32_DMA2_BASE + STM32_DMA_CNDTR_OFFSET(n)) -#define STM32_DMA2_CNDTR1 (STM32_DMA2_BASE + STM32_DMA_CNDTR1_OFFSET) -#define STM32_DMA2_CNDTR2 (STM32_DMA2_BASE + STM32_DMA_CNDTR2_OFFSET) -#define STM32_DMA2_CNDTR3 (STM32_DMA2_BASE + STM32_DMA_CNDTR3_OFFSET) -#define STM32_DMA2_CNDTR4 (STM32_DMA2_BASE + STM32_DMA_CNDTR4_OFFSET) -#define STM32_DMA2_CNDTR5 (STM32_DMA2_BASE + STM32_DMA_CNDTR5_OFFSET) - -#define STM32_DMA2_CPAR(n) (STM32_DMA2_BASE + STM32_DMA_CPAR_OFFSET(n)) -#define STM32_DMA2_CPAR1 (STM32_DMA2_BASE + STM32_DMA_CPAR1_OFFSET) -#define STM32_DMA2_CPAR2 (STM32_DMA2_BASE + STM32_DMA_CPAR2_OFFSET) -#define STM32_DMA2_CPAR3 (STM32_DMA2_BASE + STM32_DMA_CPAR3_OFFSET) -#define STM32_DMA2_CPAR4 (STM32_DMA2_BASE + STM32_DMA_CPAR4_OFFSET) -#define STM32_DMA2_CPAR5 (STM32_DMA2_BASE + STM32_DMA_CPAR5_OFFSET) - -#define STM32_DMA2_CMAR(n) (STM32_DMA2_BASE + STM32_DMA_CMAR_OFFSET(n)) -#define STM32_DMA2_CMAR1 (STM32_DMA2_BASE + STM32_DMA_CMAR1_OFFSET) -#define STM32_DMA2_CMAR2 (STM32_DMA2_BASE + STM32_DMA_CMAR2_OFFSET) -#define STM32_DMA2_CMAR3 (STM32_DMA2_BASE + STM32_DMA_CMAR3_OFFSET) -#define STM32_DMA2_CMAR4 (STM32_DMA2_BASE + STM32_DMA_CMAR4_OFFSET) -#define STM32_DMA2_CMAR5 (STM32_DMA2_BASE + STM32_DMA_CMAR5_OFFSET) - -#ifdef DMA_HAVE_CSELR -# define STM32_DMA_CSELR (STM32_DMA2_BASE + STM32_DMA_CSELR_OFFSET) -#endif - -/* Register Bitfield Definitions ********************************************/ - -#define DMA_CHAN_SHIFT(n) ((n) << 2) -#define DMA_CHAN_MASK 0x0f -#define DMA_CHAN_GIF_BIT (1 << 0) /* Bit 0: Channel Global interrupt flag */ -#define DMA_CHAN_TCIF_BIT (1 << 1) /* Bit 1: Channel Transfer Complete flag */ -#define DMA_CHAN_HTIF_BIT (1 << 2) /* Bit 2: Channel Half Transfer flag */ -#define DMA_CHAN_TEIF_BIT (1 << 3) /* Bit 3: Channel Transfer Error flag */ - -/* DMA interrupt status register */ - -#define DMA_ISR_CHAN_SHIFT(n) DMA_CHAN_SHIFT(n) -#define DMA_ISR_CHAN_MASK(n) (DMA_CHAN_MASK << DMA_ISR_CHAN_SHIFT(n)) -#define DMA_ISR_CHAN1_SHIFT (0) /* Bits 3-0: DMA Channel 1 interrupt status */ -#define DMA_ISR_CHAN1_MASK (DMA_CHAN_MASK << DMA_ISR_CHAN1_SHIFT) -#define DMA_ISR_CHAN2_SHIFT (4) /* Bits 7-4: DMA Channel 2 interrupt status */ -#define DMA_ISR_CHAN2_MASK (DMA_CHAN_MASK << DMA_ISR_CHAN2_SHIFT) -#define DMA_ISR_CHAN3_SHIFT (8) /* Bits 11-8: DMA Channel 3 interrupt status */ -#define DMA_ISR_CHAN3_MASK (DMA_CHAN_MASK << DMA_ISR_CHAN3_SHIFT) -#define DMA_ISR_CHAN4_SHIFT (12) /* Bits 15-12: DMA Channel 4 interrupt status */ -#define DMA_ISR_CHAN4_MASK (DMA_CHAN_MASK << DMA_ISR_CHAN4_SHIFT) -#define DMA_ISR_CHAN5_SHIFT (16) /* Bits 19-16: DMA Channel 5 interrupt status */ -#define DMA_ISR_CHAN5_MASK (DMA_CHAN_MASK << DMA_ISR_CHAN5_SHIFT) -#define DMA_ISR_CHAN6_SHIFT (20) /* Bits 23-20: DMA Channel 6 interrupt status */ -#define DMA_ISR_CHAN6_MASK (DMA_CHAN_MASK << DMA_ISR_CHAN6_SHIFT) -#define DMA_ISR_CHAN7_SHIFT (24) /* Bits 27-24: DMA Channel 7 interrupt status */ -#define DMA_ISR_CHAN7_MASK (DMA_CHAN_MASK << DMA_ISR_CHAN7_SHIFT) - -#define DMA_ISR_GIF(n) (DMA_CHAN_GIF_BIT << DMA_ISR_CHAN_SHIFT(n)) -#define DMA_ISR_TCIF(n) (DMA_CHAN_TCIF_BIT << DMA_ISR_CHAN_SHIFT(n)) -#define DMA_ISR_HTIF(n) (DMA_CHAN_HTIF_BIT << DMA_ISR_CHAN_SHIFT(n)) -#define DMA_ISR_TEIF(n) (DMA_CHAN_TEIF_BIT << DMA_ISR_CHAN_SHIFT(n)) - -/* DMA interrupt flag clear register */ - -#define DMA_IFCR_CHAN_SHIFT(n) DMA_CHAN_SHIFT(n) -#define DMA_IFCR_CHAN_MASK(n) (DMA_CHAN_MASK << DMA_IFCR_CHAN_SHIFT(n)) -#define DMA_IFCR_CHAN1_SHIFT (0) /* Bits 3-0: DMA Channel 1 interrupt flag clear */ -#define DMA_IFCR_CHAN1_MASK (DMA_CHAN_MASK << DMA_IFCR_CHAN1_SHIFT) -#define DMA_IFCR_CHAN2_SHIFT (4) /* Bits 7-4: DMA Channel 2 interrupt flag clear */ -#define DMA_IFCR_CHAN2_MASK (DMA_CHAN_MASK << DMA_IFCR_CHAN2_SHIFT) -#define DMA_IFCR_CHAN3_SHIFT (8) /* Bits 11-8: DMA Channel 3 interrupt flag clear */ -#define DMA_IFCR_CHAN3_MASK (DMA_CHAN_MASK << DMA_IFCR_CHAN3_SHIFT) -#define DMA_IFCR_CHAN4_SHIFT (12) /* Bits 15-12: DMA Channel 4 interrupt flag clear */ -#define DMA_IFCR_CHAN4_MASK (DMA_CHAN_MASK << DMA_IFCR_CHAN4_SHIFT) -#define DMA_IFCR_CHAN5_SHIFT (16) /* Bits 19-16: DMA Channel 5 interrupt flag clear */ -#define DMA_IFCR_CHAN5_MASK (DMA_CHAN_MASK << DMA_IFCR_CHAN5_SHIFT) -#define DMA_IFCR_CHAN6_SHIFT (20) /* Bits 23-20: DMA Channel 6 interrupt flag clear */ -#define DMA_IFCR_CHAN6_MASK (DMA_CHAN_MASK << DMA_IFCR_CHAN6_SHIFT) -#define DMA_IFCR_CHAN7_SHIFT (24) /* Bits 27-24: DMA Channel 7 interrupt flag clear */ -#define DMA_IFCR_CHAN7_MASK (DMA_CHAN_MASK << DMA_IFCR_CHAN7_SHIFT) -#define DMA_IFCR_ALLCHANNELS (0x0fffffff) - -#define DMA_IFCR_CGIF(n) (DMA_CHAN_GIF_BIT << DMA_IFCR_CHAN_SHIFT(n)) -#define DMA_IFCR_CTCIF(n) (DMA_CHAN_TCIF_BIT << DMA_IFCR_CHAN_SHIFT(n)) -#define DMA_IFCR_CHTIF(n) (DMA_CHAN_HTIF_BIT << DMA_IFCR_CHAN_SHIFT(n)) -#define DMA_IFCR_CTEIF(n) (DMA_CHAN_TEIF_BIT << DMA_IFCR_CHAN_SHIFT(n)) - -/* DMA channel configuration register */ - -#define DMA_CCR_EN (1 << 0) /* Bit 0: Channel enable */ -#define DMA_CCR_TCIE (1 << 1) /* Bit 1: Transfer complete interrupt enable */ -#define DMA_CCR_HTIE (1 << 2) /* Bit 2: Half Transfer interrupt enable */ -#define DMA_CCR_TEIE (1 << 3) /* Bit 3: Transfer error interrupt enable */ -#define DMA_CCR_DIR (1 << 4) /* Bit 4: Data transfer direction */ -#define DMA_CCR_CIRC (1 << 5) /* Bit 5: Circular mode */ -#define DMA_CCR_PINC (1 << 6) /* Bit 6: Peripheral increment mode */ -#define DMA_CCR_MINC (1 << 7) /* Bit 7: Memory increment mode */ -#define DMA_CCR_PSIZE_SHIFT (8) /* Bits 8-9: Peripheral size */ -#define DMA_CCR_PSIZE_MASK (3 << DMA_CCR_PSIZE_SHIFT) -# define DMA_CCR_PSIZE_8BITS (0 << DMA_CCR_PSIZE_SHIFT) /* 00: 8-bits */ -# define DMA_CCR_PSIZE_16BITS (1 << DMA_CCR_PSIZE_SHIFT) /* 01: 16-bits */ -# define DMA_CCR_PSIZE_32BITS (2 << DMA_CCR_PSIZE_SHIFT) /* 10: 32-bits */ - -#define DMA_CCR_MSIZE_SHIFT (10) /* Bits 10-11: Memory size */ -#define DMA_CCR_MSIZE_MASK (3 << DMA_CCR_MSIZE_SHIFT) -# define DMA_CCR_MSIZE_8BITS (0 << DMA_CCR_MSIZE_SHIFT) /* 00: 8-bits */ -# define DMA_CCR_MSIZE_16BITS (1 << DMA_CCR_MSIZE_SHIFT) /* 01: 16-bits */ -# define DMA_CCR_MSIZE_32BITS (2 << DMA_CCR_MSIZE_SHIFT) /* 10: 32-bits */ - -#define DMA_CCR_PL_SHIFT (12) /* Bits 12-13: Channel Priority level */ -#define DMA_CCR_PL_MASK (3 << DMA_CCR_PL_SHIFT) -# define DMA_CCR_PRILO (0 << DMA_CCR_PL_SHIFT) /* 00: Low */ -# define DMA_CCR_PRIMED (1 << DMA_CCR_PL_SHIFT) /* 01: Medium */ -# define DMA_CCR_PRIHI (2 << DMA_CCR_PL_SHIFT) /* 10: High */ -# define DMA_CCR_PRIVERYHI (3 << DMA_CCR_PL_SHIFT) /* 11: Very high */ - -#define DMA_CCR_MEM2MEM (1 << 14) /* Bit 14: Memory to memory mode */ - -#define DMA_CCR_ALLINTS (DMA_CCR_TEIE|DMA_CCR_HTIE|DMA_CCR_TCIE) - -/* DMA channel number of data register */ - -#define DMA_CNDTR_NDT_SHIFT (0) /* Bits 15-0: Number of data to Transfer */ -#define DMA_CNDTR_NDT_MASK (0xffff << DMA_CNDTR_NDT_SHIFT) - -/* DMA Channel mapping. Each DMA channel has a mapping to several possible - * sources/sinks of data. The requests from peripherals assigned to a - * channel are simply OR'ed together before entering the DMA block. This - * means that only one request on a given channel can be enabled at once. - * - * Alternative DMA channel selections are provided with a numeric suffix like - * _1, _2, etc. Drivers, however, will use the pin selection without the - * numeric suffix. Additional definitions are required in the board.h file. - */ - -#define STM32_DMA1_CHAN1 (0) -#define STM32_DMA1_CHAN2 (1) -#define STM32_DMA1_CHAN3 (2) -#define STM32_DMA1_CHAN4 (3) -#define STM32_DMA1_CHAN5 (4) -#define STM32_DMA1_CHAN6 (5) -#define STM32_DMA1_CHAN7 (6) - -#define STM32_DMA2_CHAN1 (7) -#define STM32_DMA2_CHAN2 (8) -#define STM32_DMA2_CHAN3 (9) -#define STM32_DMA2_CHAN4 (10) -#define STM32_DMA2_CHAN5 (11) - -#ifdef DMA_HAVE_CSELR -# define DMACHAN_SETTING(chan, sel) ((((sel) & 0xff) << 8) | ((chan) & 0xff)) -# define DMACHAN_SETTING_CHANNEL_MASK 0x00ff -# define DMACHAN_SETTING_CHANNEL_SHIFT (0) -# define DMACHAN_SETTING_FUNCTION_MASK 0xff00 -# define DMACHAN_SETTING_FUNCTION_SHIFT (8) -#endif - -#if defined(CONFIG_ARCH_CHIP_STM32F0) -/* REVISIT: based on STM32L4 DMA Header */ - -/* ADC */ - -# define DMACHAN_ADC1_1 DMACHAN_SETTING(STM32_DMA1_CHAN1, 0) -# define DMACHAN_ADC1_2 DMACHAN_SETTING(STM32_DMA2_CHAN3, 0) - -# define DMACHAN_ADC2_1 DMACHAN_SETTING(STM32_DMA1_CHAN1, 0) -# define DMACHAN_ADC2_2 DMACHAN_SETTING(STM32_DMA2_CHAN4, 0) - -# define DMACHAN_ADC3_1 DMACHAN_SETTING(STM32_DMA1_CHAN1, 0) -# define DMACHAN_ADC3_2 DMACHAN_SETTING(STM32_DMA2_CHAN5, 0) - -/* AES */ - -# define DMACHAN_AES_IN_1 DMACHAN_SETTING(STM32_DMA2_CHAN1, 6) -# define DMACHAN_AES_IN_2 DMACHAN_SETTING(STM32_DMA2_CHAN5, 6) -# define DMACHAN_AES_OUT_1 DMACHAN_SETTING(STM32_DMA2_CHAN2, 6) -# define DMACHAN_AES_OUT_2 DMACHAN_SETTING(STM32_DMA2_CHAN3, 6) - -/* DAC */ - -# define DMACHAN_DAC1_1 DMACHAN_SETTING(STM32_DMA1_CHAN3, 6) -# define DMACHAN_DAC1_2 DMACHAN_SETTING(STM32_DMA1_CHAN4, 5) -# define DMACHAN_DAC1_3 DMACHAN_SETTING(STM32_DMA2_CHAN4, 3) - -# define DMACHAN_DAC2 DMACHAN_SETTING(STM32_DMA2_CHAN5, 3) - -/* I2C */ - -# define DMACHAN_I2C1_RX_1 DMACHAN_SETTING(STM32_DMA1_CHAN7, 3) -# define DMACHAN_I2C1_RX_2 DMACHAN_SETTING(STM32_DMA2_CHAN6, 5) -# define DMACHAN_I2C1_TX_1 DMACHAN_SETTING(STM32_DMA1_CHAN6, 3) -# define DMACHAN_I2C1_TX_2 DMACHAN_SETTING(STM32_DMA2_CHAN7, 5) - -# define DMACHAN_I2C2_RX DMACHAN_SETTING(STM32_DMA1_CHAN5, 3) -# define DMACHAN_I2C2_TX DMACHAN_SETTING(STM32_DMA1_CHAN4, 3) - -# define DMACHAN_I2C3_RX DMACHAN_SETTING(STM32_DMA1_CHAN3, 2) -# define DMACHAN_I2C3_TX DMACHAN_SETTING(STM32_DMA1_CHAN2, 3) - -/* QUADSPI */ - -# define DMACHAN_QUADSPI_1 DMACHAN_SETTING(STM32_DMA1_CHAN5, 5) -# define DMACHAN_QUADSPI_2 DMACHAN_SETTING(STM32_DMA2_CHAN7, 3) - -/* SPI */ - -# define DMACHAN_SPI1_RX_1 DMACHAN_SETTING(STM32_DMA1_CHAN2, 1) -# define DMACHAN_SPI1_RX_2 DMACHAN_SETTING(STM32_DMA2_CHAN3, 4) -# define DMACHAN_SPI1_TX_1 DMACHAN_SETTING(STM32_DMA1_CHAN3, 0) -# define DMACHAN_SPI1_TX_2 DMACHAN_SETTING(STM32_DMA2_CHAN4, 4) - -# define DMACHAN_SPI2_RX DMACHAN_SETTING(STM32_DMA1_CHAN4, 1) -# define DMACHAN_SPI2_TX DMACHAN_SETTING(STM32_DMA1_CHAN5, 1) - -# define DMACHAN_SPI3_RX DMACHAN_SETTING(STM32_DMA2_CHAN1, 3) -# define DMACHAN_SPI3_TX DMACHAN_SETTING(STM32_DMA2_CHAN2, 3) - -/* TIM */ - -# define DMACHAN_TIM1_CH1 DMACHAN_SETTING(STM32_DMA1_CHAN2, 7) -# define DMACHAN_TIM1_CH2 DMACHAN_SETTING(STM32_DMA1_CHAN3, 7) -# define DMACHAN_TIM1_CH3 DMACHAN_SETTING(STM32_DMA1_CHAN7, 7) -# define DMACHAN_TIM1_CH4 DMACHAN_SETTING(STM32_DMA1_CHAN4, 7) -# define DMACHAN_TIM1_COM DMACHAN_SETTING(STM32_DMA1_CHAN4, 7) -# define DMACHAN_TIM1_TRIG DMACHAN_SETTING(STM32_DMA1_CHAN4, 7) -# define DMACHAN_TIM1_UP DMACHAN_SETTING(STM32_DMA1_CHAN6, 7) - -# define DMACHAN_TIM2_CH1 DMACHAN_SETTING(STM32_DMA1_CHAN5, 4) -# define DMACHAN_TIM2_CH2 DMACHAN_SETTING(STM32_DMA1_CHAN7, 4) -# define DMACHAN_TIM2_CH3 DMACHAN_SETTING(STM32_DMA1_CHAN1, 4) -# define DMACHAN_TIM2_CH4 DMACHAN_SETTING(STM32_DMA1_CHAN7, 4) -# define DMACHAN_TIM2_UP DMACHAN_SETTING(STM32_DMA1_CHAN2, 4) - -# define DMACHAN_TIM3_CH1 DMACHAN_SETTING(STM32_DMA1_CHAN6, 5) -# define DMACHAN_TIM3_CH3 DMACHAN_SETTING(STM32_DMA1_CHAN2, 5) -# define DMACHAN_TIM3_CH4 DMACHAN_SETTING(STM32_DMA1_CHAN3, 5) -# define DMACHAN_TIM3_TRIG DMACHAN_SETTING(STM32_DMA1_CHAN6, 5) -# define DMACHAN_TIM3_UP DMACHAN_SETTING(STM32_DMA1_CHAN3, 5) - -# define DMACHAN_TIM4_CH1 DMACHAN_SETTING(STM32_DMA1_CHAN1, 6) -# define DMACHAN_TIM4_CH2 DMACHAN_SETTING(STM32_DMA1_CHAN4, 6) -# define DMACHAN_TIM4_CH3 DMACHAN_SETTING(STM32_DMA1_CHAN5, 6) -# define DMACHAN_TIM4_UP DMACHAN_SETTING(STM32_DMA1_CHAN7, 6) - -# define DMACHAN_TIM5_CH1 DMACHAN_SETTING(STM32_DMA2_CHAN5, 5) -# define DMACHAN_TIM5_CH2 DMACHAN_SETTING(STM32_DMA2_CHAN4, 5) -# define DMACHAN_TIM5_CH3 DMACHAN_SETTING(STM32_DMA2_CHAN2, 5) -# define DMACHAN_TIM5_CH4 DMACHAN_SETTING(STM32_DMA2_CHAN1, 5) -# define DMACHAN_TIM5_COM DMACHAN_SETTING(STM32_DMA2_CHAN1, 5) -# define DMACHAN_TIM5_TRIG DMACHAN_SETTING(STM32_DMA2_CHAN1, 5) -# define DMACHAN_TIM5_UP DMACHAN_SETTING(STM32_DMA2_CHAN2, 5) - -# define DMACHAN_TIM6_UP_1 DMACHAN_SETTING(STM32_DMA1_CHAN3, 6) -# define DMACHAN_TIM6_UP_2 DMACHAN_SETTING(STM32_DMA2_CHAN4, 3) - -# define DMACHAN_TIM7_UP_1 DMACHAN_SETTING(STM32_DMA1_CHAN4, 5) -# define DMACHAN_TIM7_UP_2 DMACHAN_SETTING(STM32_DMA2_CHAN5, 3) - -# define DMACHAN_TIM8_CH1 DMACHAN_SETTING(STM32_DMA2_CHAN6, 7) -# define DMACHAN_TIM8_CH2 DMACHAN_SETTING(STM32_DMA2_CHAN7, 7) -# define DMACHAN_TIM8_CH3 DMACHAN_SETTING(STM32_DMA2_CHAN1, 7) -# define DMACHAN_TIM8_CH4 DMACHAN_SETTING(STM32_DMA2_CHAN2, 7) -# define DMACHAN_TIM8_COM DMACHAN_SETTING(STM32_DMA2_CHAN2, 7) -# define DMACHAN_TIM8_TRIG DMACHAN_SETTING(STM32_DMA2_CHAN2, 7) -# define DMACHAN_TIM8_UP DMACHAN_SETTING(STM32_DMA2_CHAN1, 7) - -# define DMACHAN_TIM15_CH1 DMACHAN_SETTING(STM32_DMA1_CHAN5, 7) -# define DMACHAN_TIM15_COM DMACHAN_SETTING(STM32_DMA1_CHAN5, 7) -# define DMACHAN_TIM15_TRIG DMACHAN_SETTING(STM32_DMA1_CHAN5, 7) -# define DMACHAN_TIM15_UP DMACHAN_SETTING(STM32_DMA1_CHAN5, 7) - -# define DMACHAN_TIM16_CH1_1 DMACHAN_SETTING(STM32_DMA1_CHAN3, 4) -# define DMACHAN_TIM16_CH1_2 DMACHAN_SETTING(STM32_DMA1_CHAN6, 4) -# define DMACHAN_TIM16_UP_1 DMACHAN_SETTING(STM32_DMA1_CHAN3, 4) -# define DMACHAN_TIM16_UP_2 DMACHAN_SETTING(STM32_DMA1_CHAN6, 4) - -# define DMACHAN_TIM17_CH1_1 DMACHAN_SETTING(STM32_DMA1_CHAN1, 5) -# define DMACHAN_TIM17_CH1_2 DMACHAN_SETTING(STM32_DMA1_CHAN7, 5) -# define DMACHAN_TIM17_UP_1 DMACHAN_SETTING(STM32_DMA1_CHAN1, 5) -# define DMACHAN_TIM17_UP_2 DMACHAN_SETTING(STM32_DMA1_CHAN7, 5) - -/* USARTs */ - -# define DMACHAN_USART1_RX_1 DMACHAN_SETTING(STM32_DMA1_CHAN5, 2) -# define DMACHAN_USART1_RX_2 DMACHAN_SETTING(STM32_DMA2_CHAN7, 2) -# define DMACHAN_USART1_TX_1 DMACHAN_SETTING(STM32_DMA1_CHAN4, 2) -# define DMACHAN_USART1_TX_2 DMACHAN_SETTING(STM32_DMA2_CHAN6, 2) - -# define DMACHAN_USART2_RX DMACHAN_SETTING(STM32_DMA1_CHAN6, 2) -# define DMACHAN_USART2_TX DMACHAN_SETTING(STM32_DMA1_CHAN7, 2) - -# define DMACHAN_USART3_RX DMACHAN_SETTING(STM32_DMA1_CHAN3, 1) -# define DMACHAN_USART3_TX DMACHAN_SETTING(STM32_DMA1_CHAN2, 2) - -# define DMACHAN_USART4_RX DMACHAN_SETTING(STM32_DMA2_CHAN5, 2) -# define DMACHAN_USART4_TX DMACHAN_SETTING(STM32_DMA2_CHAN3, 2) - -# define DMACHAN_USART5_RX DMACHAN_SETTING(STM32_DMA2_CHAN2, 2) -# define DMACHAN_USART5_TX DMACHAN_SETTING(STM32_DMA2_CHAN1, 2) - -#elif defined(CONFIG_ARCH_CHIP_STM32L0) - -/* ADC */ - -# define DMACHAN_ADC1_1 DMACHAN_SETTING(STM32_DMA1_CHAN1, 0) -# define DMACHAN_ADC1_2 DMACHAN_SETTING(STM32_DMA1_CHAN2, 0) - -/* AES */ - -# define DMACHAN_AES_IN_1 DMACHAN_SETTING(STM32_DMA1_CHAN1, 11) -# define DMACHAN_AES_IN_2 DMACHAN_SETTING(STM32_DMA1_CHAN5, 11) -# define DMACHAN_AES_OUT_1 DMACHAN_SETTING(STM32_DMA1_CHAN2, 11) -# define DMACHAN_AES_OUT_2 DMACHAN_SETTING(STM32_DMA1_CHAN3, 11) - -/* DAC */ - -# define DMACHAN_DAC1CH1 DMACHAN_SETTING(STM32_DMA1_CHAN2, 9) -# define DMACHAN_DAC1CH2 DMACHAN_SETTING(STM32_DMA1_CHAN4, 15) - -/* I2C */ - -# define DMACHAN_I2C1_TX_1 DMACHAN_SETTING(STM32_DMA1_CHAN2, 6) -# define DMACHAN_I2C1_TX_2 DMACHAN_SETTING(STM32_DMA1_CHAN6, 6) -# define DMACHAN_I2C1_RX_1 DMACHAN_SETTING(STM32_DMA1_CHAN3, 6) -# define DMACHAN_I2C1_RX_2 DMACHAN_SETTING(STM32_DMA1_CHAN7, 6) -# define DMACHAN_I2C2_TX DMACHAN_SETTING(STM32_DMA1_CHAN4, 7) -# define DMACHAN_I2C2_RX DMACHAN_SETTING(STM32_DMA1_CHAN7, 7) -# define DMACHAN_I2C3_TX_1 DMACHAN_SETTING(STM32_DMA1_CHAN2, 14) -# define DMACHAN_I2C3_TX_2 DMACHAN_SETTING(STM32_DMA1_CHAN4, 14) -# define DMACHAN_I2C3_RX_1 DMACHAN_SETTING(STM32_DMA1_CHAN3, 14) -# define DMACHAN_I2C3_RX_2 DMACHAN_SETTING(STM32_DMA1_CHAN5, 14) - -/* SPI */ - -# define DMACHAN_SPI1_RX DMACHAN_SETTING(STM32_DMA1_CHAN2, 1) -# define DMACHAN_SPI1_TX DMACHAN_SETTING(STM32_DMA1_CHAN3, 1) -# define DMACHAN_SPI2_RX_1 DMACHAN_SETTING(STM32_DMA1_CHAN4, 2) -# define DMACHAN_SPI2_RX_2 DMACHAN_SETTING(STM32_DMA1_CHAN6, 2) -# define DMACHAN_SPI2_TX_1 DMACHAN_SETTING(STM32_DMA1_CHAN5, 2) -# define DMACHAN_SPI2_TX_2 DMACHAN_SETTING(STM32_DMA1_CHAN7, 2) - -/* TIM */ - -# define DMACHAN_TIM2_CH1 DMACHAN_SETTING(STM32_DMA1_CHAN5, 8) -# define DMACHAN_TIM2_CH2_1 DMACHAN_SETTING(STM32_DMA1_CHAN3, 8) -# define DMACHAN_TIM2_CH2_2 DMACHAN_SETTING(STM32_DMA1_CHAN7, 8) -# define DMACHAN_TIM2_CH3 DMACHAN_SETTING(STM32_DMA1_CHAN1, 8) -# define DMACHAN_TIM2_CH4_1 DMACHAN_SETTING(STM32_DMA1_CHAN4, 8) -# define DMACHAN_TIM2_CH4_2 DMACHAN_SETTING(STM32_DMA1_CHAN7, 8) -# define DMACHAN_TIM2_UP DMACHAN_SETTING(STM32_DMA1_CHAN2, 8) -# define DMACHAN_TIM6_UP DMACHAN_SETTING(STM32_DMA1_CHAN2, 9) -# define DMACHAN_TIM7_UP DMACHAN_SETTING(STM32_DMA1_CHAN4, 15) - -/* USART */ - -# define DMACHAN_USART1_TX_1 DMACHAN_SETTING(STM32_DMA1_CHAN2, 3) -# define DMACHAN_USART1_TX_2 DMACHAN_SETTING(STM32_DMA1_CHAN4, 3) -# define DMACHAN_USART1_RX_1 DMACHAN_SETTING(STM32_DMA1_CHAN3, 3) -# define DMACHAN_USART1_RX_2 DMACHAN_SETTING(STM32_DMA1_CHAN5, 3) -# define DMACHAN_USART2_TX_1 DMACHAN_SETTING(STM32_DMA1_CHAN4, 4) -# define DMACHAN_USART2_TX_2 DMACHAN_SETTING(STM32_DMA1_CHAN7, 4) -# define DMACHAN_USART2_RX_1 DMACHAN_SETTING(STM32_DMA1_CHAN5, 4) -# define DMACHAN_USART2_RX_2 DMACHAN_SETTING(STM32_DMA1_CHAN6, 4) -# define DMACHAN_LPUART1_TX_1 DMACHAN_SETTING(STM32_DMA1_CHAN2, 5) -# define DMACHAN_LPUART1_TX_2 DMACHAN_SETTING(STM32_DMA1_CHAN7, 5) -# define DMACHAN_LPUART1_RX_1 DMACHAN_SETTING(STM32_DMA1_CHAN3, 5) -# define DMACHAN_LPUART1_RX_2 DMACHAN_SETTING(STM32_DMA1_CHAN6, 5) -# define DMACHAN_USART4_RX_1 DMACHAN_SETTING(STM32_DMA1_CHAN2, 12) -# define DMACHAN_USART4_RX_2 DMACHAN_SETTING(STM32_DMA1_CHAN6, 12) -# define DMACHAN_USART4_TX_1 DMACHAN_SETTING(STM32_DMA1_CHAN7, 12) -# define DMACHAN_USART4_TX_2 DMACHAN_SETTING(STM32_DMA1_CHAN3, 12) -# define DMACHAN_USART5_RX_1 DMACHAN_SETTING(STM32_DMA1_CHAN2, 13) -# define DMACHAN_USART5_RX_2 DMACHAN_SETTING(STM32_DMA1_CHAN6, 13) -# define DMACHAN_USART5_TX_1 DMACHAN_SETTING(STM32_DMA1_CHAN7, 13) -# define DMACHAN_USART5_TX_2 DMACHAN_SETTING(STM32_DMA1_CHAN3, 13) - -#elif defined(CONFIG_ARCH_CHIP_STM32G0) || defined(CONFIG_ARCH_CHIP_STM32C0) -/* This family uses a DMAMUX */ - -#else -# error "Unknown DMA channel assignments" -#endif - -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_DMA_V1_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32_dmamux.h b/arch/arm/src/stm32f0l0g0/hardware/stm32_dmamux.h deleted file mode 100644 index 31402fafbc02e..0000000000000 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32_dmamux.h +++ /dev/null @@ -1,162 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32_dmamux.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_DMAMUX_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_DMAMUX_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include "chip.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#define DMAMUX1 0 - -/* Register Offsets *********************************************************/ - -#define STM32_DMAMUX_CXCR_OFFSET(x) (0x0000+0x0004*(x)) /* DMAMUX1 request line multiplexer channel x configuration register */ -#define STM32_DMAMUX_C0CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(0) -#define STM32_DMAMUX_C1CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(1) -#define STM32_DMAMUX_C2CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(2) -#define STM32_DMAMUX_C3CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(3) -#define STM32_DMAMUX_C4CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(4) -#define STM32_DMAMUX_C5CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(5) -#define STM32_DMAMUX_C6CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(6) - /* 0x01C-0x07C: Reserved */ -#define STM32_DMAMUX_CSR_OFFSET 0x0080 /* DMAMUX1 request line multiplexer interrupt channel status register */ -#define STM32_DMAMUX_CFR_OFFSET 0x0084 /* DMAMUX1 request line multiplexer interrupt clear flag register */ - /* 0x088-0x0FC: Reserved */ -#define STM32_DMAMUX_RGXCR_OFFSET(x) (0x0100+0x004*(x)) /* DMAMUX1 request generator channel x configuration register */ -#define STM32_DMAMUX_RG0CR_OFFSET STM32_DMAMUX_RGXCR_OFFSET(0) -#define STM32_DMAMUX_RG1CR_OFFSET STM32_DMAMUX_RGXCR_OFFSET(1) -#define STM32_DMAMUX_RG2CR_OFFSET STM32_DMAMUX_RGXCR_OFFSET(2) -#define STM32_DMAMUX_RG3CR_OFFSET STM32_DMAMUX_RGXCR_OFFSET(3) -#define STM32_DMAMUX_RGSR_OFFSET 0x0140 /* DMAMUX1 request generator interrupt status register */ -#define STM32_DMAMUX_RGCFR_OFFSET 0x0144 /* DMAMUX1 request generator interrupt clear flag register */ - /* 0x148-0x3FC: Reserved */ - -/* Register Addresses *******************************************************/ - -#define STM32_DMAMUX1_CXCR(x) (STM32_DMAMUX1_BASE+STM32_DMAMUX_CXCR_OFFSET(x)) -#define STM32_DMAMUX1_C0CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_C0CR_OFFSET) -#define STM32_DMAMUX1_C1CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_C1CR_OFFSET) -#define STM32_DMAMUX1_C2CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_C2CR_OFFSET) -#define STM32_DMAMUX1_C3CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_C3CR_OFFSET) -#define STM32_DMAMUX1_C4CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_C4CR_OFFSET) -#define STM32_DMAMUX1_C5CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_C5CR_OFFSET) -#define STM32_DMAMUX1_C6CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_C6CR_OFFSET) - -#define STM32_DMAMUX1_CSR (STM32_DMAMUX1_BASE+STM32_DMAMUX_CSR_OFFSET) -#define STM32_DMAMUX1_CFR (STM32_DMAMUX1_BASE+STM32_DMAMUX_CFR_OFFSET) - -#define STM32_DMAMUX1_RGXCR(x) (STM32_DMAMUX1_BASE+STM32_DMAMUX_RGXCR_OFFSET(x)) -#define STM32_DMAMUX1_RG0CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_RG0CR_OFFSET) -#define STM32_DMAMUX1_RG1CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_RG1CR_OFFSET) -#define STM32_DMAMUX1_RG2CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_RG2CR_OFFSET) -#define STM32_DMAMUX1_RG3CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_RG3CR_OFFSET) - -#define STM32_DMAMUX1_RGSR (STM32_DMAMUX1_BASE+STM32_DMAMUX_RGSR_OFFSET) -#define STM32_DMAMUX1_RGCFR (STM32_DMAMUX1_BASE+STM32_DMAMUX_RGCFR_OFFSET) - -/* Register Bitfield Definitions ********************************************/ - -/* DMAMUX1 request line multiplexer channel x configuration register */ - -#define DMAMUX_CCR_DMAREQID_SHIFT (0) /* Bits 0-6: DMA request identification */ -#define DMAMUX_CCR_DMAREQID_MASK (0x7f << DMAMUX_CCR_DMAREQID_SHIFT) -#define DMAMUX_CCR_SOIE (8) /* Bit 8: Synchronization overrun interrupt enable */ -#define DMAMUX_CCR_EGE (9) /* Bit 9: Event generation enable */ -#define DMAMUX_CCR_SE (16) /* Bit 16: Synchronization enable */ -#define DMAMUX_CCR_SPOL_SHIFT (17) /* Bits 17-18: Synchronization polarity */ -#define DMAMUX_CCR_SPOL_MASK (0x3 << DMAMUX_CCR_SPOL_SHIFT) -# define DMAMUX_CCR_SPOL_NONE (0x0 << DMAMUX_CCR_SPOL_SHIFT) /* No event: No trigger detection or generation */ -# define DMAMUX_CCR_SPOL_RISING (0x1 << DMAMUX_CCR_SPOL_SHIFT) /* Rising edge */ -# define DMAMUX_CCR_SPOL_FALLING (0x2 << DMAMUX_CCR_SPOL_SHIFT) /* Falling edge */ -# define DMAMUX_CCR_SPOL_BOTH (0x3 << DMAMUX_CCR_SPOL_SHIFT) /* Both rising and falling edges */ -#define DMAMUX_CCR_NBREQ_SHIFT (19) /* Bits 19-23: Number of DMA request - 1 to forward */ -#define DMAMUX_CCR_NBREQ_MASK (0x1f << DMAMUX_CCR_NBREQ_SHIFT) -#define DMAMUX_CCR_SYNCID_SHIFT (24) /* Bits 24-28: Synchronization identification */ -#define DMAMUX_CCR_SYNCID_MASK (0x1f << DMAMUX_CCR_SYNCID_SHIFT) - -/* DMAMUX1 request line multiplexer interrupt channel status register */ - -#define DMAMUX1_CSR_SOF(x) (1 << (x)) /* Synchronization overrun event flag */ - -/* DMAMUX1 request line multiplexer interrupt clear flag register */ - -#define DMAMUX1_CFR_CSOF(x) (1 << (x)) /* Clear synchronization overrun event flag */ - -/* DMAMUX1 request generator channel x configuration register */ - -#define DMAMUX_RGCR_SIGID_SHIFT (0) /* Bits 0-4: Signal identification */ -#define DMAMUX_RGCR_SIGID_MASK (0x1f << DMAMUX_RGCR_SIGID_SHIFT) -#define DMAMUX_RGCR_OIE (8) /* Bit 8: Trigger overrun interrupt enable */ -#define DMAMUX_RGCR_GE (16) /* Bit 16: DMA request generator channel X enable*/ -#define DMAMUX_RGCR_GPOL_SHIFT (17) /* Bits 17-18: DMA request generator trigger polarity */ -#define DMAMUX_RGCR_GPOL_MASK (0x3 << DMAMUX_RGCR_GPOL_SHIFT) -# define DMAMUX_RGCR_GPOL_NONE (0x0 << DMAMUX_RGCR_GPOL_SHIFT) /* No event: No trigger detection or generation */ -# define DMAMUX_RGCR_GPOL_RISING (0x1 << DMAMUX_RGCR_GPOL_SHIFT) /* Rising edge */ -# define DMAMUX_RGCR_GPOL_FALLING (0x2 << DMAMUX_RGCR_GPOL_SHIFT) /* Falling edge */ -# define DMAMUX_RGCR_GPOL_BOTH (0x3 << DMAMUX_RGCR_GPOL_SHIFT) /* Both rising and falling edges */ -#define DMAMUX_RGCR_GNBREQ_SHIFT (19) /* Bits 19-23: Number of DMA requests to be generated -1 */ -#define DMAMUX_RGCR_GNBREQL_MASK (0x1f << DMAMUX_RGCR_GNBREQ_SHIFT) - -/* DMAMUX1 request generator interrupt status register */ - -#define DMAMUX1_RGSR_OF(x) (1 << (x)) /* Trigger overrun event flag */ - -/* DMAMUX1 request generator interrupt clear flag register */ - -#define DMAMUX1_RGCFR_COF(x) (1 << (x)) /* Clear trigger overrun event flag */ - -/* DMA channel mapping - * - * XXXXX.DDD.CCCCCCCC - * C - DMAMUX request - * D - DMA controller - * X - free bits - */ - -#define DMAMAP_MAP(d,c) ((d) << 8 | (c)) -#define DMAMAP_CONTROLLER(m) ((m) >> 8 & 0x07) -#define DMAMAP_REQUEST(m) ((m) >> 0 & 0xff) - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -/* Import DMAMUX map */ - -#if defined(CONFIG_STM32F0L0G0_STM32G0) -# include "hardware/stm32g0_dmamux.h" -#elif defined(CONFIG_STM32F0L0G0_STM32C0) -# include "hardware/stm32c0_dmamux.h" -#else -# error "Unsupported STM32 M0 sub family" -#endif - -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_DMAMUX_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32_exti.h b/arch/arm/src/stm32f0l0g0/hardware/stm32_exti.h deleted file mode 100644 index 82e7cff363d4b..0000000000000 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32_exti.h +++ /dev/null @@ -1,45 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32_exti.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_EXTI_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_EXTI_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include "chip.h" - -#if defined(CONFIG_ARCH_CHIP_STM32F0) -# include "hardware/stm32f0_exti.h" -#elif defined(CONFIG_ARCH_CHIP_STM32L0) -# include "hardware/stm32l0_exti.h" -#elif defined(CONFIG_ARCH_CHIP_STM32G0) -# include "hardware/stm32g0_exti.h" -#elif defined(CONFIG_ARCH_CHIP_STM32C0) -# include "hardware/stm32c0_exti.h" -#else -# error "Unrecognized STM32 M0 EXTI" -#endif - -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_EXTI_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32_fdcan.h b/arch/arm/src/stm32f0l0g0/hardware/stm32_fdcan.h deleted file mode 100644 index fa93956fc691c..0000000000000 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32_fdcan.h +++ /dev/null @@ -1,582 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32_fdcan.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_FDCAN_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_FDCAN_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "chip.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Register Offsets *********************************************************/ - -#define STM32_FDCAN_CREL_OFFSET 0x0000 /* FDCAN core release register */ -#define STM32_FDCAN_ENDN_OFFSET 0x0004 /* FDCAN endian register */ - /* 0x0008 Reserved */ -#define STM32_FDCAN_DBTP_OFFSET 0x000c /* FDCAN data bit timing and prescaler register */ -#define STM32_FDCAN_TEST_OFFSET 0x0010 /* FDCAN test register */ -#define STM32_FDCAN_RWD_OFFSET 0x0014 /* FDCAN RAM watchdog register */ -#define STM32_FDCAN_CCCR_OFFSET 0x0018 /* FDCAN CC control register */ -#define STM32_FDCAN_NBTP_OFFSET 0x001c /* FDCAN nominal bit timing and prescaler register */ -#define STM32_FDCAN_TSCC_OFFSET 0x0020 /* FDCAN timestamp counter configuration register */ -#define STM32_FDCAN_TSCV_OFFSET 0x0024 /* FDCAN timestamp counter value register */ -#define STM32_FDCAN_TOCC_OFFSET 0x0028 /* FDCAN timeout counter configuration register */ -#define STM32_FDCAN_TOCV_OFFSET 0x002c /* FDCAN timeout counter value register */ - /* 0x0030 to 0x003c Reserved */ -#define STM32_FDCAN_ECR_OFFSET 0x0040 /* FDCAN error counter register */ -#define STM32_FDCAN_PSR_OFFSET 0x0044 /* FDCAN protocol status register */ -#define STM32_FDCAN_TDCR_OFFSET 0x0048 /* FDCAN transmitter delay compensation register */ - /* 0x004c Reserved */ -#define STM32_FDCAN_IR_OFFSET 0x0050 /* FDCAN interrupt register */ -#define STM32_FDCAN_IE_OFFSET 0x0054 /* FDCAN interrupt enable register */ -#define STM32_FDCAN_ILS_OFFSET 0x0058 /* FDCAN interrupt line select register */ -#define STM32_FDCAN_ILE_OFFSET 0x005c /* FDCAN interrupt line enable register */ - /* 0x0060 to 0x007c Reserved */ -#define STM32_FDCAN_RXGFC_OFFSET 0x0080 /* FDCAN global filter configuration register */ -#define STM32_FDCAN_XIDAM_OFFSET 0x0084 /* FDCAN extended ID and mask register */ -#define STM32_FDCAN_HPMS_OFFSET 0x0088 /* FDCAN high-priority message status register */ -#define STM32_FDCAN_RXFS_OFFSET(f) (0x0090 + ((f) << 3) -#define STM32_FDCAN_RXFA_OFFSET(f) (0x0094 + ((f) << 3) -#define STM32_FDCAN_RXF0S_OFFSET 0x0090 /* FDCAN Rx FIFO 0 status register */ -#define STM32_FDCAN_RXF0A_OFFSET 0x0094 /* CAN Rx FIFO 0 acknowledge register */ -#define STM32_FDCAN_RXF1S_OFFSET 0x0098 /* FDCAN Rx FIFO 1 status register */ -#define STM32_FDCAN_RXF1A_OFFSET 0x009c /* FDCAN Rx FIFO 1 acknowledge register */ - /* 0x00a0 to 0x00bc Reserved */ -#define STM32_FDCAN_TXBC_OFFSET 0x00c0 /* FDCAN Tx buffer configuration register */ -#define STM32_FDCAN_TXFQS_OFFSET 0x00c4 /* FDCAN Tx FIFO/queue status register */ -#define STM32_FDCAN_TXBRP_OFFSET 0x00c8 /* FDCAN Tx buffer request pending register */ -#define STM32_FDCAN_TXBAR_OFFSET 0x00cc /* FDCAN Tx buffer add request register */ -#define STM32_FDCAN_TXBCR_OFFSET 0x00d0 /* FDCAN Tx buffer cancellation request register */ -#define STM32_FDCAN_TXBTO_OFFSET 0x00d4 /* FDCAN Tx buffer transmission occurred register */ -#define STM32_FDCAN_TXBCNF_OFFSET 0x00d8 /* FDCAN Tx buffer cancellation finished register */ -#define STM32_FDCAN_TXBTIE_OFFSET 0x00dc /* FDCAN Tx buffer transmission interrupt enable register */ -#define STM32_FDCAN_TXBCIE_OFFSET 0x00e0 /* FDCAN Tx buffer cancellation finished interrupt enable register */ -#define STM32_FDCAN_TXEFS_OFFSET 0x00e4 /* FDCAN Tx event FIFO status register */ -#define STM32_FDCAN_TXEFA_OFFSET 0x00e8 /* FDCAN Tx event FIFO acknowledge register */ -#define STM32_FDCAN_CKDIV_OFFSET 0x0100 /* FDCAN CFG clock divider register */ - -/* Register Bitfield Definitions ********************************************/ - -/* FDCAN core release register */ - -#define FDCAN_CREL_DAY_SHIFT (0) /* Bits 0-7: DAY */ -#define FDCAN_CREL_DAY_MASK (0xff << FDCAN_CREL_DAY_SHIFT) -#define FDCAN_CREL_MON_SHIFT (8) /* Bits 8-15: MON */ -#define FDCAN_CREL_MON_MASK (0xff << FDCAN_CREL_MON_SHIFT) -#define FDCAN_CREL_YEAR_SHIFT (16) /* Bits 8-15: YEAR */ -#define FDCAN_CREL_YEAR_MASK (0x0f << FDCAN_CREL_YEAR_SHIFT) -#define FDCAN_CREL_SUBSTEP_SHIFT (20) /* Bits 20-23: SUBSTEP */ -#define FDCAN_CREL_SUBSTEP_MASK (0x0f << FDCAN_CREL_SUBSTEP_SHIFT) -#define FDCAN_CREL_STEP_SHIFT (24) /* Bits 24-27: STEP */ -#define FDCAN_CREL_STEP_MASK (0x0f << FDCAN_CREL_STEP_SHIFT) -#define FDCAN_CREL_REL_SHIFT (28) /* Bits 28-31: REL */ -#define FDCAN_CREL_REL_MASK (0x0f << FDCAN_CREL_REL_SHIFT) - -/* FDCAN data bit timing and prescaler register */ - -#define FDCAN_DBTP_DSJW_SHIFT (0) /* Bits 0-3: Synchronization jump width */ -#define FDCAN_DBTP_DSJW_MASK (0x0f << FDCAN_DBTP_DSJW_SHIFT) -# define FDCAN_DBTP_DSJW(value) ((value) << FDCAN_DBTP_DSJW_SHIFT) -# define FDCAN_DBTP_DSJW_MAX (15) -#define FDCAN_DBTP_DTSEG2_SHIFT (4) /* Bits 4-7: Data time segment after sample point*/ -#define FDCAN_DBTP_DTSEG2_MASK (0x0f << FDCAN_DBTP_DTSEG2_SHIFT) -# define FDCAN_DBTP_DTSEG2(value) ((value) << FDCAN_DBTP_DTSEG2_SHIFT) -# define FDCAN_DBTP_DTSEG2_MAX (15) -#define FDCAN_DBTP_DTSEG1_SHIFT (8) /* Bits 8-12: Data time segment before sample point*/ -#define FDCAN_DBTP_DTSEG1_MASK (0x1f << FDCAN_DBTP_DTSEG1_SHIFT) -# define FDCAN_DBTP_DTSEG1(value) ((value) << FDCAN_DBTP_DTSEG1_SHIFT) -# define FDCAN_DBTP_DTSEG1_MAX (31) -#define FDCAN_DBTP_DBRP_SHIFT (16) /* Bits 16-20: Data bitrate prescaler */ -#define FDCAN_DBTP_DBRP_MASK (0x1f << FDCAN_DBTP_DBRP_SHIFT) -# define FDCAN_DBTP_DBRP(value) ((value) << FDCAN_DBTP_DBRP_SHIFT) -# define FDCAN_DBTP_DBRP_MAX (31) -#define FDCAN_DBTP_TDC_EN (1 << 23) /* Bit 23: Transceiver delay compensation enable */ - -/* FDCAN test register */ - -#define FDCAN_TEST_LBCK (1 << 4) /* Bit 4: Loop back mode */ -#define FDCAN_TEST_TX_SHIFT (5) /* Bits 5-6: Control of transmit pin */ -#define FDCAN_TEST_TX_MASK (0x3 << FDCAN_TEST_TX_SHIFT) -# define FDCAN_TEST_TX_RESET (0 << FDCAN_TEST_TX_SHIFT) /* 00: TX is controlled by CAN core */ -# define FDCAN_TEST_TX_SP (1 << FDCAN_TEST_TX_SHIFT) /* 01: Sample point can be monitored at TX pin */ -# define FDCAN_TEST_TX_DLVL (2 << FDCAN_TEST_TX_SHIFT) /* 10: Dominant (0) level at TX pin */ -# define FDCAN_TEST_TX_RLVL (3 << FDCAN_TEST_TX_SHIFT) /* 11: Recesive (1) level at TX pin */ -#define FDCAN_TEST_RX (1 << 7) /* Bit 7: Receive pin */ - -/* FDCAN RAM watchdog register */ - -#define FDCAN_RWD_WDC_SHIFT (0) /* Bits 0-7: RAM watchdog counter start value */ -#define FDCAN_RWD_WDC_MASK (0xff << FDCAN_RWD_WDC_SHIFT) -# define FDCAN_RWD_WDC_DIS (0 << FDCAN_RWD_WDC_SHIFT) /* Counter disabled */ -# define FDCAN_RWD_WDC(value) ((value) << FDCAN_RWD_WDC_SHIFT) -#define FDCAN_RWD_WDV_SHIFT (8) /* Bits 8-15: RAM watchdog counter value */ -#define FDCAN_RWD_WDV_MASK (0xff << FDCAN_RWD_WDV_SHIFT) - -/* FDCAN CC control register */ - -#define FDCAN_CCCR_INIT (1 << 0) /* Bit 0: Initialization */ -#define FDCAN_CCCR_CCE (1 << 1) /* Bit 1: Configuration change enable */ -#define FDCAN_CCCR_ASM (1 << 2) /* Bit 2: ASM restricted operation mode */ -#define FDCAN_CCCR_CSA (1 << 3) /* Bit 3: Clock stop acknowledge */ -#define FDCAN_CCCR_CSR (1 << 4) /* Bit 4: Clock stop request */ -#define FDCAN_CCCR_MON (1 << 5) /* Bit 5: Bus monitoring mode */ -#define FDCAN_CCCR_DAR (1 << 6) /* Bit 6: Disable automatic retransmission */ -#define FDCAN_CCCR_TEST (1 << 7) /* Bit 7: Test mode enable */ -#define FDCAN_CCCR_FDOE (1 << 8) /* Bit 8: FD operation enable */ -#define FDCAN_CCCR_BRSE (1 << 9) /* Bit 9: FDCAN Bitrate switching */ - /* Bits 10-11: Reserved */ -#define FDCAN_CCCR_PXHD (1 << 12) /* Bit 12: Protocol exception handling disable */ -#define FDCAN_CCCR_EFBI (1 << 13) /* Bit 13: Edge filtering during bus integration */ -#define FDCAN_CCCR_TXP (1 << 14) /* Bit 14: Tx pause */ -#define FDCAN_CCCR_NISO (1 << 15) /* Bit 15: Non ISO operation */ - -/* FDCAN nominal bit timing and prescaler register */ - -#define FDCAN_NBTP_NTSEG2_SHIFT (0) /* Bits 0-6: Nominal time segment after sample point */ -#define FDCAN_NBTP_NTSEG2_MASK (0x7f << FDCAN_NBTP_NTSEG2_SHIFT) -# define FDCAN_NBTP_NTSEG2(value) ((value) << FDCAN_NBTP_NTSEG2_SHIFT) -# define FDCAN_NBTP_NTSEG2_MAX (127) -#define FDCAN_NBTP_NTSEG1_SHIFT (8) /* Bits 8-15: Nominal time segment before sample point */ -#define FDCAN_NBTP_NTSEG1_MASK (0xff << FDCAN_NBTP_NTSEG1_SHIFT) -# define FDCAN_NBTP_NTSEG1(value) ((value) << FDCAN_NBTP_NTSEG1_SHIFT) -# define FDCAN_NBTP_NTSEG1_MAX (255) -#define FDCAN_NBTP_NBRP_SHIFT (16) /* Bits 16-24: Bitrate prescaler */ -#define FDCAN_NBTP_NBRP_MASK (0x1ff << FDCAN_NBTP_NBRP_SHIFT) -# define FDCAN_NBTP_NBRP(value) ((value) << FDCAN_NBTP_NBRP_SHIFT) -# define FDCAN_NBTP_NBRP_MAX (511) -#define FDCAN_NBTP_NSJW_SHIFT (25) /* Bits 25-31: Nominal (re)synchronization jump width */ -#define FDCAN_NBTP_NSJW_MASK (0x7f << FDCAN_NBTP_NSJW_SHIFT) -# define FDCAN_NBTP_NSJW(value) ((value) << FDCAN_NBTP_NSJW_SHIFT) -# define FDCAN_NBTP_NSJW_MAX (127) - -/* FDCAN timestamp counter configuration register */ - -#define FDCAN_TSCC_TSS_SHIFT (0) /* Bits 0-1: Timestamp counter select */ -#define FDCAN_TSCC_TSS_MASK (0x3 << FDCAN_TSCC_TSS_SHIFT) -# define FDCAN_TSCC_TSS_ZERO (0 << FDCAN_TSCC_TSS_SHIFT) /* 00: Always 0 */ -# define FDCAN_TSCC_TSS_TCP (1 << FDCAN_TSCC_TSS_SHIFT) /* 01: Incremented based on TCP */ -# define FDCAN_TSCC_TSS_TIM3 (2 << FDCAN_TSCC_TSS_SHIFT) /* 10: Value from TIM3 used */ -#define FDCAN_TSCC_TCP_SHIFT (16) /* Bits 16-19: Timestamp counter prescaler */ -#define FDCAN_TSCC_TCP_MASK (0x0f << FDCAN_TSCC_TCP_SHIFT) -# define FDCAN_TSCC_TCP(value) ((value) << FDCAN_TSCC_TCP_SHIFT) - -/* FDCAN timestamp counter value register */ - -#define FDCAN_TSCV_TSC_SHIFT (0) /* Bits 0-15: Timestamp counter */ -#define FDCAN_TSCV_TSC_MASK (0xffff << FDCAN_TSCV_TSC_SHIFT) - -/* FDCAN timeout counter configuration register */ - -#define FDCAN_TOCC_ETOC (1 << 0) /* Bit 0: Enable timeout counter */ -#define FDCAN_TOCC_TOS_SHIFT (1) /* Bits 1-2: Timeout select */ -#define FDCAN_TOCC_TOS_MASK (0x03 << FDCAN_TOCC_TOS_SHIFT) -# define FDCAN_TOCC_TOS_CONT (0 << FDCAN_TOCC_TOS_SHIFT) /* 00: Continuous operation */ -# define FDCAN_TOCC_TOS_TXFIFO (1 << FDCAN_TOCC_TOS_SHIFT) /* 01: Tx event FIFO */ -# define FDCAN_TOCC_TOS_RX_FIFO0 (2 << FDCAN_TOCC_TOS_SHIFT) /* 10: Rx FIFO 0 */ -# define FDCAN_TOCC_TOS_RX_FIFO1 (3 << FDCAN_TOCC_TOS_SHIFT) /* 11: Rx FIFO 1 */ -#define FDCAN_TOCC_TOP_SHIFT (16) /* Bits 16-31: Timeout period counter start value */ -#define FDCAN_TOCC_TOP_MASK (0xffff << FDCAN_TOCC_TOP_SHIFT) -# define FDCAN_TOCC_TOP(value) ((value) << FDCAN_TOCC_TOP_SHIFT) - -/* FDCAN timeout counter value register */ - -#define FDCAN_TOCV_TOC_SHIFT (0) /* Bits 0-15: Timestamp counter */ -#define FDCAN_TOCV_TOC_MASK (0xffff << FDCAN_TOCV_TOC_SHIFT) - -/* FDCAN error counter register */ - -#define FDCAN_ECR_TEC_SHIFT (0) /* Bits 0-7: Transmit error counter */ -#define FDCAN_CR_TEC_MASK (0xff << FDCAN_ECR_TEC_SHIFT) -#define FDCAN_ECR_REC_SHIFT (8) /* Bits 8-14: Receive error counter */ -#define FDCAN_ECR_REC_MASK (0x7f << FDCAN_ECR_REC_SHIFT) -#define FDCAN_ECR_RP (1 << 15) /* Bit 15: Receive error passive */ -#define FDCAN_ECR_CEL_SHIFT (16) /* Bits 16-23: CAN error logging */ -#define FDCAN_ECR_CEL_MASK (0xff << FDCAN_ECR_CEL_SHIFT) - -/* FDCAN protocol status register */ - -/* Error codes */ - -#define FDCAN_PSR_EC_NO_ERROR (0) /* No error occurred since LEC has been reset */ -#define FDCAN_PSR_EC_STUFF_ERROR (1) /* More than 5 equal bits in a sequence */ -#define FDCAN_PSR_EC_FORM_ERROR (2) /* Part of a received frame has wrong format */ -#define FDCAN_PSR_EC_ACK_ERROR (3) /* Message not acknowledged by another node */ -#define FDCAN_PSR_EC_BIT1_ERROR (4) /* Send with recessive level, but bus value was dominant */ -#define FDCAN_PSR_EC_BIT0_ERROR (5) /* Send with dominant level, but bus value was recessive */ -#define FDCAN_PSR_EC_CRC_ERROR (6) /* CRC received message incorrect */ -#define FDCAN_PSR_EC_NO_CHANGE (7) /* No CAN bus event was detected since last read */ - -#define FDCAN_PSR_LEC_SHIFT (0) /* Bits 0-2: Last error code */ -#define FDCAN_PSR_LEC_MASK (0x7 << FDCAN_PSR_LEC_SHIFT) -# define FDCAN_PSR_LEC(n) ((uint32_t)(n) << FDCAN_PSR_LEC_SHIFT) /* See error codes above */ -#define FDCAN_PSR_ACT_SHIFT (3) /* Bits 3-4: Activity */ -#define FDCAN_PSR_ACT_MASK (3 << FDCAN_PSR_ACT_SHIFT) -# define FDCAN_PSR_ACT_SYNC (0 << FDCAN_PSR_ACT_SHIFT) /* 00: Synchronizing */ -# define FDCAN_PSR_ACT_IDLE (1 << FDCAN_PSR_ACT_SHIFT) /* 01: Idle */ -# define FDCAN_PSR_ACT_RECV (2 << FDCAN_PSR_ACT_SHIFT) /* 10: Receiver */ -# define FDCAN_PSR_ACT_TRANS (3 << FDCAN_PSR_ACT_SHIFT) /* 11: Transmitter */ -#define FDCAN_PSR_EP (1 << 5) /* Bit 5: Error passive */ -#define FDCAN_PSR_EW (1 << 6) /* Bit 6: Warning status */ -#define FDCAN_PSR_BO (1 << 7) /* Bit 7: Bus_off status */ -#define FDCAN_PSR_DLEC_SHIFT (8) /* Bits 8-10: Data last error code */ -#define FDCAN_PSR_DLEC_MASK (0x7 << FDCAN_PSR_DLEC_SHIFT) -# define FDCAN_PSR_DLEC(n) ((uint32_t)(n) << FDCAN_PSR_DLEC_SHIFT) /* See error codes above */ -#define FDCAN_PSR_RESI (1 << 11) /* Bit 11: ESI flag of last message */ -#define FDCAN_PSR_RBRS (1 << 12) /* Bit 12: BRS flag of last message */ -#define FDCAN_PSR_REDL (1 << 13) /* Bit 13: Received message */ -#define FDCAN_PSR_PXE (1 << 14) /* Bit 14: Protocol exception event */ -#define FDCAN_PSR_TDCV_SHIFT (16) /* Bits 16-22: Transmitter delay compensation */ -#define FDCAN_PSR_TDCV_MASK (0x7f << FDCAN_PSR_TDCV_SHIFT) - -/* FDCAN transmitter delay compensation register */ - -#define FDCAN_TDCR_TDCF_SHIFT (0) /* Bits 0-6: Transmitter delay compensation filter window length */ -#define FDCAN_TDCR_TDCF_MASK (0x7f << FDCAN_TDCR_TDCF_SHIFT) -# define FDCAN_TDCR_TDCF(value) ((value) << FDCAN_TDCR_TDCF_SHIFT) -#define FDCAN_TDCR_TDCO_SHIFT (8) /* Bits 8-14: Transmiiter delay compensation offset */ -#define FDCAN_TDCR_TDCO_MASK (0x7f << FDCAN_TDCR_TDCO_SHIFT) -# define FDCAN_TDCR_TDCO(value) ((value) << FDCAN_TDCR_TDCO_SHIFT) - -/* FDCAN interrupt register and interrupt enable register */ - -#define FDCAN_INT_RF0N (1 << 0) /* Bit 0: Rx FIFO 0 new message */ -#define FDCAN_INT_RF0F (1 << 1) /* Bit 1: Rx FIFO 0 full */ -#define FDCAN_INT_RF0L (1 << 2) /* Bit 2: Rx FIFO 0 message lost */ -#define FDCAN_INT_RF1N (1 << 3) /* Bit 3: Rx FIFO 1 new message */ -#define FDCAN_INT_RF1F (1 << 4) /* Bit 4: Rx FIFO 1 full */ -#define FDCAN_INT_RF1L (1 << 5) /* Bit 5: Rx FIFO 1 message lost */ -#define FDCAN_INT_HPM (1 << 6) /* Bit 6: High priority message */ -#define FDCAN_INT_TC (1 << 7) /* Bit 7: Transmission completed */ -#define FDCAN_INT_TCF (1 << 8) /* Bit 8: Transmission cancellation finished */ -#define FDCAN_INT_TFE (1 << 9) /* Bit 9: Tx FIFO empty */ -#define FDCAN_INT_TEFN (1 << 10) /* Bit 10: Tx event FIFO new entry */ -#define FDCAN_INT_TEFF (1 << 11) /* Bit 11: Tx event FIFO full */ -#define FDCAN_INT_TEFL (1 << 12) /* Bit 12: Tx event FIFO element lost */ -#define FDCAN_INT_TSW (1 << 13) /* Bit 13: Timestamp wraparound */ -#define FDCAN_INT_MRAF (1 << 14) /* Bit 14: Message RAM access failure */ -#define FDCAN_INT_TOO (1 << 15) /* Bit 15: Timeout occurred */ -#define FDCAN_INT_ELO (1 << 16) /* Bit 16: Error logging overflow */ -#define FDCAN_INT_EP (1 << 17) /* Bit 17: Error_passive status */ -#define FDCAN_INT_EW (1 << 18) /* Bit 18: Error_warning status */ -#define FDCAN_INT_BO (1 << 19) /* Bit 19: Buss_off status */ -#define FDCAN_INT_WDI (1 << 20) /* Bit 20: Watchdog interrupt */ -#define FDCAN_INT_PEA (1 << 21) /* Bit 21: Protocol error arbitration phase */ -#define FDCAN_INT_PED (1 << 22) /* Bit 22: Protocol error data phase */ -#define FDCAN_INT_ARA (1 << 23) /* Bit 23: Access to reserved address */ - -/* FDCAN interrupt line select register */ - -#define FDCAN_ILS_RXFIFO0 (1 << 0) /* Bit 0: RXFIFO 0 */ -#define FDCAN_ILS_RXFIFO1 (1 << 1) /* Bit 1: RXFIFO 1 */ -#define FDCAN_ILS_SMG (1 << 2) /* Bit 2: SMSG */ -#define FDCAN_ILS_TFERR (1 << 3) /* Bit 3: TFERR */ -#define FDCAN_ILS_MISC (1 << 4) /* Bit 4: MISC */ -#define FDCAN_ILS_BERR (1 << 5) /* Bit 5: BERR */ -#define FDCAN_ILS_PERR (1 << 6) /* Bit 6: PERR */ - -/* FDCAN interrupt line enable register */ - -#define FDCAN_ILE_EINT0 (1 << 0) /* Bit 0: Enable interrupt line 0 */ -#define FDCAN_ILE_EINT1 (1 << 1) /* Bit 1: Enable interrupt line 1 */ - -/* FDCAN global filter configuration register */ - -#define FDCAN_RXGFC_RRFE (1 << 0) /* Bit 0: Reject remote frames ext */ -#define FDCAN_RXGFC_RRFS (1 << 1) /* Bit 1: Reject remote frames std */ -#define FDCAN_RXGFC_ANFE_SHIFT (2) /* Bits 2-3: Accept non-matching frames ext */ -#define FDCAN_RXGFC_ANFE_MASK (0x3 << FDCAN_RXGFC_ANFE_SHIFT) -# define FDCAN_RXGFC_ANFE_RX_FIFO0 (0 << FDCAN_RXGFC_ANFE_SHIFT) /* 00: Accept in Rx FIFO 0 */ -# define FDCAN_RXGFC_ANFE_RX_FIFO1 (1 << FDCAN_RXGFC_ANFE_SHIFT) /* 01: Accept in Rx FIFO 1 */ -# define FDCAN_RXGFC_ANFE_REJECTED (2 << FDCAN_RXGFC_ANFE_SHIFT) /* 10: Reject */ -#define FDCAN_RXGFC_ANFS_SHIFT (4) /* Bits 5-4: Accept non-matching frames std */ -#define FDCAN_RXGFC_ANFS_MASK (0x3 << FDCAN_RXGFC_ANFS_SHIFT) -# define FDCAN_RXGFC_ANFS_RX_FIFO0 (0 << FDCAN_RXGFC_ANFS_SHIFT) /* 00: Accept in Rx FIFO 0 */ -# define FDCAN_RXGFC_ANFS_RX_FIFO1 (1 << FDCAN_RXGFC_ANFS_SHIFT) /* 01: Accept in Rx FIFO 1 */ -# define FDCAN_RXGFC_ANFS_REJECTED (2 << FDCAN_RXGFC_ANFS_SHIFT) /* 10: Reject */ -#define FDCAN_RXGFC_F1OM (1 << 8) /* Bit 8: FIFO 1 operation mode */ -#define FDCAN_RXGFC_F0OM (1 << 9) /* Bit 9: FIFO 0 operation mode */ -#define FDCAN_RXGFC_LSS_SHIFT (16) /* Bits 16-20: List size std */ -#define FDCAN_RXGFC_LSS_MASK (0x1f << FDCAN_RXGFC_LSS_SHIFT) -# define FDCAN_RXGFC_LSS(value) ((value) << FDCAN_RXGFC_LSS_SHIFT) -# define FDCAN_RXGFC_LSS_MAX (28) -#define FDCAN_RXGFC_LSE_SHIFT (24) /* Bits 24-27: List size ext */ -#define FDCAN_RXGFC_LSE_MASK (0x1f << FDCAN_RXGFC_LSE_SHIFT) -# define FDCAN_RXGFC_LSE(value) ((value) << FDCAN_RXGFC_LSE_SHIFT) -# define FDCAN_RXGFC_LSE_MAX (8) - -/* FDCAN extended ID and mask register */ - -#define FDCAN_XIDAM_EIDM_SHIFT (0) /* Bits 0-28: Extended ID mask */ -#define FDCAN_XIDAM_EIDM_MASK (0x1fffffff << FDCAN_XIDAM_EIDM_SHIFT) - -/* FDCAN high-priority message status register */ - -#define FDCAN_HPMS_BIDX_SHIFT (0) /* Bits 0-2: Buffer index */ -#define FDCAN_HPMS_BIDX_MASK (0x7 << FDCAN_HPMS_BIDX_SHIFT) -# define FDCAN_HPMS_BIDX(value) ((value) << FDCAN_HPMS_BIDX_SHIFT) -#define FDCAN_HPMS_MSI_SHIFT (6) /* Bits 6-7: Message storage indicator */ -#define FDCAN_HPMS_MSI_MASK (0x3 << FDCAN_HPMS_MSI_SHIFT) -# define FDCAN_HPMS_MSI(value) ((value) << FDCAN_HPMS_MSI_SHIFT) -#define FDCAN_HPMS_FIDX_SHIFT (8) /* Bits 8-12: Filter index */ -#define FDCAN_HPMS_FIDX_MASK (0x1f << FDCAN_HPMS_FIDX_SHIFT) -# define FDCAN_HPMS_FIDX(value) ((value) << FDCAN_HPMS_FIDX_SHIFT) -#define FDCAN_HPMS_FLST (1 << 15) /* Bit 15: Filter list */ - -/* FDCAN Rx FIFO x status register */ - -#define FDCAN_RXFS_FFL_SHIFT (0) /* Bits 0-3: FIFO fill level */ -#define FDCAN_RXFS_FFL_MASK (0xf << FDCAN_RXFS_FFL_SHIFT) -# define FDCAN_RXFS_FFL(value) ((value) << FDCAN_RXFS_FFL_SHIFT) -#define FDCAN_RXFS_FGI_SHIFT (8) /* Bits 8-9: FIFO get index */ -#define FDCAN_RXFS_FGI_MASK (0x3 << FDCAN_RXFS_FGI_SHIFT) -# define FDCAN_RXFS_FGI(value) ((value) << FDCAN_RXFS_FGI_SHIFT) -#define FDCAN_RXFS_FPI_SHIFT (16) /* Bits 16-17: FIFO put index */ -#define FDCAN_RXFS_FPI_MASK (0x3 << FDCAN_RXFS_FPI_SHIFT) -# define FDCAN_RXFS_FPI(value) ((value) << FDCAN_RXFS_FPI_SHIFT) -#define FDCAN_RXFS_FF (1 << 24) /* Bit 24: FIFO full */ -#define FDCAN_RXFS_RFL (1 << 25) /* Bit 25: FIFO message lost */ - -/* FDCAN Rx FIFO x acknowledge register */ - -#define FDCAN_RXFA_FAI_SHIFT (0) /* Bits 0-2: FIFO 0 acknowledge index */ -#define FDCAN_RXFA_FAI_MASK (0x7 << FDCAN_RXFA_FAI_SHIFT) - -/* FDCAN Tx buffer configuration register */ - -#define FDCAN_TXBC_TFQM (1 << 24) /* Bit 24: FIFO/queue mode */ - -/* FDCAN Tx FIFO/queue status register */ - -#define FDCAN_TXFQS_TFFL_SHIFT (0) /* Bits 0-2: FIFO free level */ -#define FDCAN_TXFQS_TFFL_MASK (0x7 << FDCAN_TXFQS_TFFL_SHIFT) -#define FDCAN_TXFQS_TFGI_SHIFT (8) /* Bits 8-9: FIFO get index */ -#define FDCAN_TXFQS_TFGI_MASK (0x3 << FDCAN_TXFQS_TFGI_SHIFT) -#define FDCAN_TXFQS_TFQPI_SHIFT (16) /* Bits 20-16: FIFO/queue put index */ -#define FDCAN_TXFQS_TFQPI_MASK (0x3 << FDCAN_TXFQS_TFQPI_SHIFT) -#define FDCAN_TXFQS_TFQF (1 << 21) /* Bit 21: FIFO/queue full */ - -/* FDCAN Tx buffer request pending register */ - -#define FDCAN_TXBRP_TRP_SHIFT (0) /* Bits 0-2: Transmission request pending */ -#define FDCAN_TXBRP_TRP_MASK (0x7 << FDCAN_TXBRP_TRP_SHIFT) -# define FDCAN_TXBRP_TRP(value) ((value) << FDCAN_TXBRP_TRP_SHIFT) - -/* FDCAN Tx buffer add request register */ - -#define FDCAN_TXBAR_AR_SHIFT (0) /* Bits 0-2: Add request */ -#define FDCAN_TXBAR_AR_MASK (0x7 << FDCAN_TXBAR_AR_SHIFT) -# define FDCAN_TXBAR_AR(value) ((value) << FDCAN_TXBAR_AR_SHIFT) - -/* FDCAN Tx buffer cancellation request register */ - -#define FDCAN_TXBCR_CR_SHIFT (0) /* Bits 0-2: Cancellation request */ -#define FDCAN_TXBCR_CR_MASK (0x7 << FDCAN_TXBCR_CR_SHIFT) -# define FDCAN_TXBCR_CR(value) ((value) << FDCAN_TXBCR_CR_SHIFT) - -/* FDCAN Tx buffer transmission occurred register */ - -#define FDCAN_TXBTO_TO_SHIFT (0) /* Bits 0-2: Transmission occurred */ -#define FDCAN_TXBTO_TO_MASK (0x7 << FDCAN_TXBTO_TO_SHIFT) - -/* FDCAN Tx buffer cancellation finished register */ - -#define FDCAN_TXBCF_CF_SHIFT (0) /* Bits 0-2: Cancellation finished */ -#define FDCAN_TXBCF_CF_MASK (0x7 << FDCAN_TXBCF_CF_SHIFT) - -/* FDCAN Tx buffer transmission interrupt enable register */ - -#define FDCAN_TXBTIE_TIE_SHIFT (0) /* Bits 0-2: Transmission interrupt enable */ -#define FDCAN_TXBTIE_TIE_MASK (0x7 << FDCAN_TXBTIE_TIE_SHIFT) -# define FDCAN_TXBTIE_TIE(value) ((value) << FDCAN_TXBTIE_TIE_SHIFT) - -/* FDCAN Tx buffer cancellation finished interrupt enable register */ - -#define FDCAN_TXBCIE_CFIE_SHIFT (0) /* Bits 0-2: Cancellation finished interrupt enable */ -#define FDCAN_TXBCIE_CFIE_MASK (0x7 << FDCAN_TXBCIE_CFIE_SHIFT) -# define FDCAN_TXBCIE_CFIE(value) ((value) << FDCAN_TXBCIE_CFIE_SHIFT) - -/* FDCAN Tx event FIFO status register */ - -#define FDCAN_TXEFS_EFFL_SHIFT (2) /* Bits 0-2: Event FIFO fill level */ -#define FDCAN_TXEFS_EFFL_MASK (0x7 << FDCAN_TXEFC_EFFL_SHIFT) -# define FDCAN_TXEFC_EFFL(value) ((value) << FDCAN_TXEFC_EFFL_SHIFT) -#define FDCAN_TXEFS_EFGI_SHIFT (8) /* Bits 8-9: Event FIFO get index */ -#define FDCAN_TXEFS_EFGI_MASK (0x3 << FDCAN_TXEFS_EFGI_SHIFT) -# define FDCAN_TXEFS_EFGI(value) ((value) << FDCAN_TXEFS_EFGI_SHIFT) -#define FDCAN_TXEFS_EFPI_SHIFT (16) /* Bits 16-17: Event FIFO put index */ -#define FDCAN_TXEFS_EFPI_MASK (0x3 << FDCAN_TXEFS_EFPI_SHIFT) -# define FDCAN_TXEFS_EFPI(value) ((value) << FDCAN_TXEFS_EFPI_SHIFT) -#define FDCAN_TXEFS_EFF (1 << 24) /* Bit 24: Event FIFO full */ -#define FDCAN_TXEFS_TEFL (1 << 25) /* Bit 25: Tx Event FIFO element lost */ - /* Bits 26-31: Reserved */ - -/* FDCAN Tx event FIFO acknowledge register */ - -#define FDCAN_TXEFA_EFAI_SHIFT (0) /* Bits 0-3: Event FIFO acknowledge index */ -#define FDCAN_TXEFA_EFAI_MASK (0x3 << FDCAN_TXEFA_EFAI_SHIFT) - -/* FDCAN CFG clock divider register */ - -#define FDCAN_CKDIV_PDIV_SHIFT (0) /* Bits 0-3: Input clock divider */ -#define FDCAN_CKDIV_PDIV_MASK (0xf << FDCAN_CKDIV_PDIV_SHIFT) - -/* Message RAM Definitions **************************************************/ - -/* Common Buffer and FIFO element bit definitions: - * - * --------------- ------------------- -------------------------------- - * RESOURCE R0 R1 - * --------------- ------------------- -------------------------------- - * RX FIFO: ESI, XTD, RTR, ID, ANMF, FIDX, EDL, BRS, DLC, RXTS - * TX buffer: XTD, RTR, ID, MM, EFC, DLC - * TX Event FIFO: ESI, XTD, RTR, ID, MM, ET, EDL, BRS, DLC, TXTS - * --------------- ------------------- -------------------------------- - */ - -/* Common */ - -#define BUFFER_R0_EXTID_SHIFT (0) /* Bits 0-28: Extended identifier */ -#define BUFFER_R0_EXTID_MASK (0x1fffffff << BUFFER_R0_EXTID_SHIFT) -# define BUFFER_R0_EXTID(n) ((uint32_t)(n) << BUFFER_R0_EXTID_SHIFT) -#define BUFFER_R0_STDID_SHIFT (18) /* Bits 18-28: Standard identifier */ -#define BUFFER_R0_STDID_MASK (0x7ff << BUFFER_R0_STDID_SHIFT) -# define BUFFER_R0_STDID(n) ((uint32_t)(n) << BUFFER_R0_STDID_SHIFT) -#define BUFFER_R0_RTR (1 << 29) /* Bit 29: Remote Transmission Request */ -#define BUFFER_R0_XTD (1 << 30) /* Bit 30: Extended Identifier */ -#define BUFFER_R0_ESI (1 << 31) /* Bit 31: Error State Indicator */ - -/* Common */ - -#define BUFFER_R1_DLC_SHIFT (16) /* Bits 16-19: Date length code */ -#define BUFFER_R1_DLC_MASK (15 << BUFFER_R1_DLC_SHIFT) -# define BUFFER_R1_DLC(n) ((uint32_t)(n) << BUFFER_R1_DLC_SHIFT) -#define BUFFER_R1_BRS (1 << 20) /* Bit 20: Bit Rate Switch */ -#define BUFFER_R1_FDF (1 << 21) /* Bit 21: FD Format */ - -/* RX buffer/RX FIFOs */ - -#define BUFFER_R1_RXTS_SHIFT (0) /* Bits 0-15: RX Timestamp */ -#define BUFFER_R1_RXTS_MASK (0xffff << BUFFER_R1_RXTS_SHIFT) -# define BUFFER_R1_RXTS(n) ((uint32_t)(n) << BUFFER_R1_RXTS_SHIFT) -#define BUFFER_R1_FIDX_SHIFT (24) /* Bits 24-30: Filter index */ -#define BUFFER_R1_FIDX_MASK (0x7f << BUFFER_R1_FIDX_SHIFT) -# define BUFFER_R1_FIDX(n) ((uint32_t)(n) << BUFFER_R1_FIDX_SHIFT) -#define BUFFER_R1_ANMF (1 << 31) /* Bit 31: Accepted Non-matching Frame */ - -/* TX buffer/TX Event FIFO */ - -#define BUFFER_R1_MM_SHIFT (24) /* Bits 24-31: Message Marker */ -#define BUFFER_R1_MM_MASK (0xff << BUFFER_R1_MM_SHIFT) -# define BUFFER_R1_MM(n) ((uint32_t)(n) << BUFFER_R1_MM_SHIFT) - -/* TX buffer */ - -#define BUFFER_R1_EFC (1 << 23) /* Bit 23: Event FIFO Control */ - -/* TX Event FIFO */ - -#define BUFFER_R1_TXTS_SHIFT (0) /* Bits 0-15: TX Timestamp */ -#define BUFFER_R1_TXTS_MASK (0xffff << BUFFER_R1_TXTS_SHIFT) -# define BUFFER_R1_TXTS(n) ((uint32_t)(n) << BUFFER_R1_TXTS_SHIFT) -#define BUFFER_R1_EDL (1 << 21) /* Bit 21: Extended Data Length */ -#define BUFFER_R1_ET_SHIFT (22) /* Bits 22-23: Event Type */ -#define BUFFER_R1_ET_MASK (3 << BUFFER_R1_ET_SHIFT) -# define BUFFER_R1_ET_TXEVENT (1 << BUFFER_R1_ET_SHIFT) /* Tx event */ -# define BUFFER_R1_ET_TXCANCEL (2 << BUFFER_R1_ET_SHIFT) /* Transmission despite cancellation */ - -/* Standard Message ID Filter Element */ - -#define STDFILTER_S0_SFID2_SHIFT (0) /* Bits 0-10: Standard Filter ID 2 */ -#define STDFILTER_S0_SFID2_MASK (0x7ff << STDFILTER_S0_SFID2_SHIFT) -# define STDFILTER_S0_SFID2(n ) ((uint32_t)(n) << STDFILTER_S0_SFID2_SHIFT) -#define STDFILTER_S0_BUFFER_SHIFT (0) /* Bits 0-5: RX buffer start address */ -#define STDFILTER_S0_BUFFER_MASK (63 << STDFILTER_S0_BUFFER_SHIFT) -# define STDFILTER_S0_BUFFER(n) ((uint32_t)(n) << STDFILTER_S0_BUFFER_SHIFT) -#define STDFILTER_S0_ACTION_SHIFT (9) /* Bits 9-10: Action taken */ -#define STDFILTER_S0_ACTION_MASK (3 << STDFILTER_S0_ACTION_SHIFT) -# define STDFILTER_S0_RXBUFFER (0 << STDFILTER_S0_ACTION_SHIFT) /* Store message in a Rx buffer */ -# define STDFILTER_S0_DEBUGA (1 << STDFILTER_S0_ACTION_SHIFT) /* Debug Message A */ -# define STDFILTER_S0_DEBUGB (2 << STDFILTER_S0_ACTION_SHIFT) /* Debug Message B */ -# define STDFILTER_S0_DEBUGC (3 << STDFILTER_S0_ACTION_SHIFT) /* Debug Message C */ -#define STDFILTER_S0_SFID1_SHIFT (16) /* Bits 16-26: Standard Filter ID 2 */ -#define STDFILTER_S0_SFID1_MASK (0x7ff << STDFILTER_S0_SFID1_SHIFT) -# define STDFILTER_S0_SFID1(n) ((uint32_t)(n) << STDFILTER_S0_SFID1_SHIFT) -#define STDFILTER_S0_SFEC_SHIFT (27) /* Bits 27-29: Standard Filter Element Configuration */ -#define STDFILTER_S0_SFEC_MASK (7 << STDFILTER_S0_SFEC_SHIFT) -# define STDFILTER_S0_SFEC_DISABLE (0 << STDFILTER_S0_SFEC_SHIFT) /* Disable filter element */ -# define STDFILTER_S0_SFEC_FIFO0 (1 << STDFILTER_S0_SFEC_SHIFT) /* Store in Rx FIFO 0 on match */ -# define STDFILTER_S0_SFEC_FIFO1 (2 << STDFILTER_S0_SFEC_SHIFT) /* Store in Rx FIFO 1 on match */ -# define STDFILTER_S0_SFEC_REJECT (3 << STDFILTER_S0_SFEC_SHIFT) /* Reject ID on match */ -# define STDFILTER_S0_SFEC_PRIORITY (4 << STDFILTER_S0_SFEC_SHIFT) /* Set priority ion match */ -# define STDFILTER_S0_SFEC_PRIOFIFO0 (5 << STDFILTER_S0_SFEC_SHIFT) /* Set priority and store in FIFO 0 on match */ -# define STDFILTER_S0_SFEC_PRIOFIFO1 (6 << STDFILTER_S0_SFEC_SHIFT) /* Set priority and store in FIFO 1 on match */ -# define STDFILTER_S0_SFEC_BUFFER (7 << STDFILTER_S0_SFEC_SHIFT) /* Store into Rx Buffer or as debug message */ -#define STDFILTER_S0_SFT_SHIFT (30) /* Bits 30-31: Standard Filter Type */ -#define STDFILTER_S0_SFT_MASK (3 << STDFILTER_S0_SFT_SHIFT) -# define STDFILTER_S0_SFT_RANGE (0 << STDFILTER_S0_SFT_SHIFT) /* Range filter from SF1ID to SF2ID */ -# define STDFILTER_S0_SFT_DUAL (1 << STDFILTER_S0_SFT_SHIFT) /* Dual ID filter for SF1ID or SF2ID */ -# define STDFILTER_S0_SFT_CLASSIC (2 << STDFILTER_S0_SFT_SHIFT) /* Classic filter: SF1ID=filter SF2ID=mask */ - -/* Extended Message ID Filter Element */ - -#define EXTFILTER_F0_EFID1_SHIFT (0) /* Bits 0-28: Extended Filter ID 1 */ -#define EXTFILTER_F0_EFID1_MASK (0x1fffffff << EXTFILTER_F0_EFID1_SHIFT) -# define EXTFILTER_F0_EFID1(n) ((uint32_t)(n) << EXTFILTER_F0_EFID1_SHIFT) -#define EXTFILTER_F0_EFEC_SHIFT (29) /* Bits 29-31: Extended Filter Element Configuration */ -#define EXTFILTER_F0_EFEC_MASK (7 << EXTFILTER_F0_EFEC_SHIFT) -# define EXTFILTER_F0_EFEC_DISABLE (0 << EXTFILTER_F0_EFEC_SHIFT) /* Disable filter element */ -# define EXTFILTER_F0_EFEC_FIFO0 (1 << EXTFILTER_F0_EFEC_SHIFT) /* Store in Rx FIFO 0 on match */ -# define EXTFILTER_F0_EFEC_FIFO1 (2 << EXTFILTER_F0_EFEC_SHIFT) /* Store in Rx FIFO 1 on match */ -# define EXTFILTER_F0_EFEC_REJECT (3 << EXTFILTER_F0_EFEC_SHIFT) /* Reject ID on match */ -# define EXTFILTER_F0_EFEC_PRIORITY (4 << EXTFILTER_F0_EFEC_SHIFT) /* Set priority on match */ -# define EXTFILTER_F0_EFEC_PRIOFIFO0 (5 << EXTFILTER_F0_EFEC_SHIFT) /* Set priority and store in FIFO 0 on match */ -# define EXTFILTER_F0_EFEC_PRIOFIFO1 (6 << EXTFILTER_F0_EFEC_SHIFT) /* Set priority and store in FIFO 1 on match */ -# define EXTFILTER_F0_EFEC_BUFFER (7 << EXTFILTER_F0_EFEC_SHIFT) /* Store into Rx Buffer or as debug message */ - -#define EXTFILTER_F1_EFID2_SHIFT (0) /* Bits 0-28: Extended Filter ID 2 */ -#define EXTFILTER_F1_EFID2_MASK (0x1fffffff << EXTFILTER_F1_EFID2_SHIFT) -# define EXTFILTER_F1_EFID2(n) ((uint32_t)(n) << EXTFILTER_F1_EFID2_SHIFT) -#define EXTFILTER_F1_BUFFER_SHIFT (0) /* Bits 0-5: RX buffer start address */ -#define EXTFILTER_F1_BUFFER_MASK (63 << EXTFILTER_F1_BUFFER_SHIFT) -# define EXTFILTER_F1_BUFFER(n) ((uint32_t)(n) << EXTFILTER_F1_BUFFER_SHIFT) -#define EXTFILTER_F1_ACTION_SHIFT (9) /* Bits 9-10: Action taken */ -#define EXTFILTER_F1_ACTION_MASK (3 << EXTFILTER_F1_ACTION_SHIFT) -# define EXTFILTER_F1_RXBUFFER (0 << EXTFILTER_F1_ACTION_SHIFT) /* Store message in a Rx buffer */ -# define EXTFILTER_F1_DEBUGA (1 << EXTFILTER_F1_ACTION_SHIFT) /* Debug Message A */ -# define EXTFILTER_F1_DEBUGB (2 << EXTFILTER_F1_ACTION_SHIFT) /* Debug Message B */ -# define EXTFILTER_F1_DEBUGC (3 << EXTFILTER_F1_ACTION_SHIFT) /* Debug Message C */ -#define EXTFILTER_F1_EFT_SHIFT (30) /* Bits 30-31: Extended Filter Type */ -#define EXTFILTER_F1_EFT_MASK (3 << EXTFILTER_F1_EFT_SHIFT) -# define EXTFILTER_F1_EFT_RANGE (0 << EXTFILTER_F1_EFT_SHIFT) /* Range filter from SF1ID to SF2ID */ -# define EXTFILTER_F1_EFT_DUAL (1 << EXTFILTER_F1_EFT_SHIFT) /* Dual ID filter for SF1ID or SF2ID */ -# define EXTFILTER_F1_EFT_CLASSIC (2 << EXTFILTER_F1_EFT_SHIFT) /* Classic filter: SF1ID=filter SF2ID=mask */ -# define EXTFILTER_F1_EFT_NOXIDAM (3 << EXTFILTER_F1_EFT_SHIFT) /* Range filter from EF1ID to EF2ID, no XIDAM */ - -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_FDCAN_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32_flash.h b/arch/arm/src/stm32f0l0g0/hardware/stm32_flash.h deleted file mode 100644 index 57193fbe896e6..0000000000000 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32_flash.h +++ /dev/null @@ -1,45 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32_flash.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_FLASH_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_FLASH_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include "chip.h" - -#if defined(CONFIG_ARCH_CHIP_STM32F0) -# include "hardware/stm32f0_flash.h" -#elif defined(CONFIG_ARCH_CHIP_STM32L0) -# include "hardware/stm32l0_flash.h" -#elif defined(CONFIG_ARCH_CHIP_STM32G0) -# include "hardware/stm32g0_flash.h" -#elif defined(CONFIG_ARCH_CHIP_STM32C0) -# include "hardware/stm32c0_flash.h" -#else -# error "Unsupported STM32 M0 FLASH" -#endif - -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_FLASH_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32_gpio.h b/arch/arm/src/stm32f0l0g0/hardware/stm32_gpio.h deleted file mode 100644 index 11ecd42a32daf..0000000000000 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32_gpio.h +++ /dev/null @@ -1,347 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32_gpio.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_GPIO_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_GPIO_H - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#if defined(CONFIG_ARCH_CHIP_STM32F0) -# undef STM32_GPIO_VERY_LOW_SPEED /* No very low speed operation */ -#elif defined(CONFIG_ARCH_CHIP_STM32L0) -# define STM32_GPIO_VERY_LOW_SPEED 1 /* Have very low speed operation (400KHz) */ -#elif defined(CONFIG_ARCH_CHIP_STM32G0) -# define STM32_GPIO_VERY_LOW_SPEED 1 /* Have very low speed operation */ -#elif defined(CONFIG_ARCH_CHIP_STM32C0) -# define STM32_GPIO_VERY_LOW_SPEED 1 /* Have very low speed operation */ -#else -# error "Unsupported STM32 M0 family" -#endif - -/* Register Offsets *********************************************************/ - -#define STM32_GPIO_MODER_OFFSET 0x0000 /* GPIO port mode register */ -#define STM32_GPIO_OTYPER_OFFSET 0x0004 /* GPIO port output type register */ -#define STM32_GPIO_OSPEED_OFFSET 0x0008 /* GPIO port output speed register */ -#define STM32_GPIO_PUPDR_OFFSET 0x000c /* GPIO port pull-up/pull-down register */ -#define STM32_GPIO_IDR_OFFSET 0x0010 /* GPIO port input data register */ -#define STM32_GPIO_ODR_OFFSET 0x0014 /* GPIO port output data register */ -#define STM32_GPIO_BSRR_OFFSET 0x0018 /* GPIO port bit set/reset register */ -#define STM32_GPIO_LCKR_OFFSET 0x001c /* GPIO port configuration lock register */ -#define STM32_GPIO_AFRL_OFFSET 0x0020 /* GPIO alternate function low register */ -#define STM32_GPIO_AFRH_OFFSET 0x0024 /* GPIO alternate function high register */ -#define STM32_GPIO_BRR_OFFSET 0x0028 /* GPIO port bit reset register */ - -/* Register Addresses *******************************************************/ - -#if STM32_NPORTS > 0 -# define STM32_GPIOA_MODER (STM32_GPIOA_BASE+STM32_GPIO_MODER_OFFSET) -# define STM32_GPIOA_OTYPER (STM32_GPIOA_BASE+STM32_GPIO_OTYPER_OFFSET) -# define STM32_GPIOA_OSPEED (STM32_GPIOA_BASE+STM32_GPIO_OSPEED_OFFSET) -# define STM32_GPIOA_PUPDR (STM32_GPIOA_BASE+STM32_GPIO_PUPDR_OFFSET) -# define STM32_GPIOA_IDR (STM32_GPIOA_BASE+STM32_GPIO_IDR_OFFSET) -# define STM32_GPIOA_ODR (STM32_GPIOA_BASE+STM32_GPIO_ODR_OFFSET) -# define STM32_GPIOA_BSRR (STM32_GPIOA_BASE+STM32_GPIO_BSRR_OFFSET) -# define STM32_GPIOA_LCKR (STM32_GPIOA_BASE+STM32_GPIO_LCKR_OFFSET) -# define STM32_GPIOA_AFRL (STM32_GPIOA_BASE+STM32_GPIO_AFRL_OFFSET) -# define STM32_GPIOA_AFRH (STM32_GPIOA_BASE+STM32_GPIO_AFRH_OFFSET) -#endif - -#if STM32_NPORTS > 1 -# define STM32_GPIOB_MODER (STM32_GPIOB_BASE+STM32_GPIO_MODER_OFFSET) -# define STM32_GPIOB_OTYPER (STM32_GPIOB_BASE+STM32_GPIO_OTYPER_OFFSET) -# define STM32_GPIOB_OSPEED (STM32_GPIOB_BASE+STM32_GPIO_OSPEED_OFFSET) -# define STM32_GPIOB_PUPDR (STM32_GPIOB_BASE+STM32_GPIO_PUPDR_OFFSET) -# define STM32_GPIOB_IDR (STM32_GPIOB_BASE+STM32_GPIO_IDR_OFFSET) -# define STM32_GPIOB_ODR (STM32_GPIOB_BASE+STM32_GPIO_ODR_OFFSET) -# define STM32_GPIOB_BSRR (STM32_GPIOB_BASE+STM32_GPIO_BSRR_OFFSET) -# define STM32_GPIOB_LCKR (STM32_GPIOB_BASE+STM32_GPIO_LCKR_OFFSET) -# define STM32_GPIOB_AFRL (STM32_GPIOB_BASE+STM32_GPIO_AFRL_OFFSET) -# define STM32_GPIOB_AFRH (STM32_GPIOB_BASE+STM32_GPIO_AFRH_OFFSET) -#endif - -#if STM32_NPORTS > 2 -# define STM32_GPIOC_MODER (STM32_GPIOC_BASE+STM32_GPIO_MODER_OFFSET) -# define STM32_GPIOC_OTYPER (STM32_GPIOC_BASE+STM32_GPIO_OTYPER_OFFSET) -# define STM32_GPIOC_OSPEED (STM32_GPIOC_BASE+STM32_GPIO_OSPEED_OFFSET) -# define STM32_GPIOC_PUPDR (STM32_GPIOC_BASE+STM32_GPIO_PUPDR_OFFSET) -# define STM32_GPIOC_IDR (STM32_GPIOC_BASE+STM32_GPIO_IDR_OFFSET) -# define STM32_GPIOC_ODR (STM32_GPIOC_BASE+STM32_GPIO_ODR_OFFSET) -# define STM32_GPIOC_BSRR (STM32_GPIOC_BASE+STM32_GPIO_BSRR_OFFSET) -# define STM32_GPIOC_LCKR (STM32_GPIOC_BASE+STM32_GPIO_LCKR_OFFSET) -# define STM32_GPIOC_AFRL (STM32_GPIOC_BASE+STM32_GPIO_AFRL_OFFSET) -# define STM32_GPIOC_AFRH (STM32_GPIOC_BASE+STM32_GPIO_AFRH_OFFSET) -#endif - -#if STM32_NPORTS > 3 -# define STM32_GPIOD_MODER (STM32_GPIOD_BASE+STM32_GPIO_MODER_OFFSET) -# define STM32_GPIOD_OTYPER (STM32_GPIOD_BASE+STM32_GPIO_OTYPER_OFFSET) -# define STM32_GPIOD_OSPEED (STM32_GPIOD_BASE+STM32_GPIO_OSPEED_OFFSET) -# define STM32_GPIOD_PUPDR (STM32_GPIOD_BASE+STM32_GPIO_PUPDR_OFFSET) -# define STM32_GPIOD_IDR (STM32_GPIOD_BASE+STM32_GPIO_IDR_OFFSET) -# define STM32_GPIOD_ODR (STM32_GPIOD_BASE+STM32_GPIO_ODR_OFFSET) -# define STM32_GPIOD_BSRR (STM32_GPIOD_BASE+STM32_GPIO_BSRR_OFFSET) -# define STM32_GPIOD_LCKR (STM32_GPIOD_BASE+STM32_GPIO_LCKR_OFFSET) -# define STM32_GPIOD_AFRL (STM32_GPIOD_BASE+STM32_GPIO_AFRL_OFFSET) -# define STM32_GPIOD_AFRH (STM32_GPIOD_BASE+STM32_GPIO_AFRH_OFFSET) -#endif - -#if STM32_NPORTS > 4 -# define STM32_GPIOE_MODER (STM32_GPIOE_BASE+STM32_GPIO_MODER_OFFSET) -# define STM32_GPIOE_OTYPER (STM32_GPIOE_BASE+STM32_GPIO_OTYPER_OFFSET) -# define STM32_GPIOE_OSPEED (STM32_GPIOE_BASE+STM32_GPIO_OSPEED_OFFSET) -# define STM32_GPIOE_PUPDR (STM32_GPIOE_BASE+STM32_GPIO_PUPDR_OFFSET) -# define STM32_GPIOE_IDR (STM32_GPIOE_BASE+STM32_GPIO_IDR_OFFSET) -# define STM32_GPIOE_ODR (STM32_GPIOE_BASE+STM32_GPIO_ODR_OFFSET) -# define STM32_GPIOE_BSRR (STM32_GPIOE_BASE+STM32_GPIO_BSRR_OFFSET) -# define STM32_GPIOE_LCKR (STM32_GPIOE_BASE+STM32_GPIO_LCKR_OFFSET) -# define STM32_GPIOE_AFRL (STM32_GPIOE_BASE+STM32_GPIO_AFRL_OFFSET) -# define STM32_GPIOE_AFRH (STM32_GPIOE_BASE+STM32_GPIO_AFRH_OFFSET) -#endif - -#if STM32_NPORTS > 5 -# define STM32_GPIOH_MODER (STM32_GPIOH_BASE+STM32_GPIO_MODER_OFFSET) -# define STM32_GPIOH_OTYPER (STM32_GPIOH_BASE+STM32_GPIO_OTYPER_OFFSET) -# define STM32_GPIOH_OSPEED (STM32_GPIOH_BASE+STM32_GPIO_OSPEED_OFFSET) -# define STM32_GPIOH_PUPDR (STM32_GPIOH_BASE+STM32_GPIO_PUPDR_OFFSET) -# define STM32_GPIOH_IDR (STM32_GPIOH_BASE+STM32_GPIO_IDR_OFFSET) -# define STM32_GPIOH_ODR (STM32_GPIOH_BASE+STM32_GPIO_ODR_OFFSET) -# define STM32_GPIOH_BSRR (STM32_GPIOH_BASE+STM32_GPIO_BSRR_OFFSET) -# define STM32_GPIOH_LCKR (STM32_GPIOH_BASE+STM32_GPIO_LCKR_OFFSET) -# define STM32_GPIOH_AFRL (STM32_GPIOH_BASE+STM32_GPIO_AFRL_OFFSET) -# define STM32_GPIOH_AFRH (STM32_GPIOH_BASE+STM32_GPIO_AFRH_OFFSET) -#endif - -#if STM32_NPORTS > 6 -# define STM32_GPIOF_MODER (STM32_GPIOF_BASE+STM32_GPIO_MODER_OFFSET) -# define STM32_GPIOF_OTYPER (STM32_GPIOF_BASE+STM32_GPIO_OTYPER_OFFSET) -# define STM32_GPIOF_OSPEED (STM32_GPIOF_BASE+STM32_GPIO_OSPEED_OFFSET) -# define STM32_GPIOF_PUPDR (STM32_GPIOF_BASE+STM32_GPIO_PUPDR_OFFSET) -# define STM32_GPIOF_IDR (STM32_GPIOF_BASE+STM32_GPIO_IDR_OFFSET) -# define STM32_GPIOF_ODR (STM32_GPIOF_BASE+STM32_GPIO_ODR_OFFSET) -# define STM32_GPIOF_BSRR (STM32_GPIOF_BASE+STM32_GPIO_BSRR_OFFSET) -# define STM32_GPIOF_LCKR (STM32_GPIOF_BASE+STM32_GPIO_LCKR_OFFSET) -# define STM32_GPIOF_AFRL (STM32_GPIOF_BASE+STM32_GPIO_AFRL_OFFSET) -# define STM32_GPIOF_AFRH (STM32_GPIOF_BASE+STM32_GPIO_AFRH_OFFSET) -#endif - -#if STM32_NPORTS > 7 -# define STM32_GPIOG_MODER (STM32_GPIOG_BASE+STM32_GPIO_MODER_OFFSET) -# define STM32_GPIOG_OTYPER (STM32_GPIOG_BASE+STM32_GPIO_OTYPER_OFFSET) -# define STM32_GPIOG_OSPEED (STM32_GPIOG_BASE+STM32_GPIO_OSPEED_OFFSET) -# define STM32_GPIOG_PUPDR (STM32_GPIOG_BASE+STM32_GPIO_PUPDR_OFFSET) -# define STM32_GPIOG_IDR (STM32_GPIOG_BASE+STM32_GPIO_IDR_OFFSET) -# define STM32_GPIOG_ODR (STM32_GPIOG_BASE+STM32_GPIO_ODR_OFFSET) -# define STM32_GPIOG_BSRR (STM32_GPIOG_BASE+STM32_GPIO_BSRR_OFFSET) -# define STM32_GPIOG_LCKR (STM32_GPIOG_BASE+STM32_GPIO_LCKR_OFFSET) -# define STM32_GPIOG_AFRL (STM32_GPIOG_BASE+STM32_GPIO_AFRL_OFFSET) -# define STM32_GPIOG_AFRH (STM32_GPIOG_BASE+STM32_GPIO_AFRH_OFFSET) -#endif - -/* Register Bitfield Definitions ********************************************/ - -/* GPIO port mode register */ - -#define GPIO_MODER_INPUT (0) /* Input */ -#define GPIO_MODER_OUTPUT (1) /* General purpose output mode */ -#define GPIO_MODER_ALT (2) /* Alternate mode */ -#define GPIO_MODER_ANALOG (3) /* Analog mode */ - -#define GPIO_MODER_SHIFT(n) ((n) << 1) -#define GPIO_MODER_MASK(n) (3 << GPIO_MODER_SHIFT(n)) - -#define GPIO_MODER0_SHIFT (0) -#define GPIO_MODER0_MASK (3 << GPIO_MODER0_SHIFT) -#define GPIO_MODER1_SHIFT (2) -#define GPIO_MODER1_MASK (3 << GPIO_MODER1_SHIFT) -#define GPIO_MODER2_SHIFT (4) -#define GPIO_MODER2_MASK (3 << GPIO_MODER2_SHIFT) -#define GPIO_MODER3_SHIFT (6) -#define GPIO_MODER3_MASK (3 << GPIO_MODER3_SHIFT) -#define GPIO_MODER4_SHIFT (8) -#define GPIO_MODER4_MASK (3 << GPIO_MODER4_SHIFT) -#define GPIO_MODER5_SHIFT (10) -#define GPIO_MODER5_MASK (3 << GPIO_MODER5_SHIFT) -#define GPIO_MODER6_SHIFT (12) -#define GPIO_MODER6_MASK (3 << GPIO_MODER6_SHIFT) -#define GPIO_MODER7_SHIFT (14) -#define GPIO_MODER7_MASK (3 << GPIO_MODER7_SHIFT) -#define GPIO_MODER8_SHIFT (16) -#define GPIO_MODER8_MASK (3 << GPIO_MODER8_SHIFT) -#define GPIO_MODER9_SHIFT (18) -#define GPIO_MODER9_MASK (3 << GPIO_MODER9_SHIFT) -#define GPIO_MODER10_SHIFT (20) -#define GPIO_MODER10_MASK (3 << GPIO_MODER10_SHIFT) -#define GPIO_MODER11_SHIFT (22) -#define GPIO_MODER11_MASK (3 << GPIO_MODER11_SHIFT) -#define GPIO_MODER12_SHIFT (24) -#define GPIO_MODER12_MASK (3 << GPIO_MODER12_SHIFT) -#define GPIO_MODER13_SHIFT (26) -#define GPIO_MODER13_MASK (3 << GPIO_MODER13_SHIFT) -#define GPIO_MODER14_SHIFT (28) -#define GPIO_MODER14_MASK (3 << GPIO_MODER14_SHIFT) -#define GPIO_MODER15_SHIFT (30) -#define GPIO_MODER15_MASK (3 << GPIO_MODER15_SHIFT) - -/* GPIO port output type register */ - -#define GPIO_OTYPER_OD(n) (1 << (n)) /* 1=Output open-drain */ -#define GPIO_OTYPER_PP(n) (0) /* 0=Output push-pull */ - -/* GPIO port output speed register */ - -#if defined(STM32_GPIO_VERY_LOW_SPEED) -# define GPIO_OSPEED_VERYLOW (0) /* Very low speed */ -# define GPIO_OSPEED_LOW (1) /* Low speed */ -# define GPIO_OSPEED_MEDIUM (2) /* Medium speed */ -# define GPIO_OSPEED_HIGH (3) /* High speed */ -#else -# define GPIO_OSPEED_LOW (0) /* Low speed */ -# define GPIO_OSPEED_MEDIUM (1) /* Medium speed */ -# define GPIO_OSPEED_HIGH (3) /* High speed */ -#endif - -#define GPIO_OSPEED_SHIFT(n) ((n) << 1) -#define GPIO_OSPEED_MASK(n) (3 << GPIO_OSPEED_SHIFT(n)) - -#define GPIO_OSPEED0_SHIFT (0) -#define GPIO_OSPEED0_MASK (3 << GPIO_OSPEED0_SHIFT) -#define GPIO_OSPEED1_SHIFT (2) -#define GPIO_OSPEED1_MASK (3 << GPIO_OSPEED1_SHIFT) -#define GPIO_OSPEED2_SHIFT (4) -#define GPIO_OSPEED2_MASK (3 << GPIO_OSPEED2_SHIFT) -#define GPIO_OSPEED3_SHIFT (6) -#define GPIO_OSPEED3_MASK (3 << GPIO_OSPEED3_SHIFT) -#define GPIO_OSPEED4_SHIFT (8) -#define GPIO_OSPEED4_MASK (3 << GPIO_OSPEED4_SHIFT) -#define GPIO_OSPEED5_SHIFT (10) -#define GPIO_OSPEED5_MASK (3 << GPIO_OSPEED5_SHIFT) -#define GPIO_OSPEED6_SHIFT (12) -#define GPIO_OSPEED6_MASK (3 << GPIO_OSPEED6_SHIFT) -#define GPIO_OSPEED7_SHIFT (14) -#define GPIO_OSPEED7_MASK (3 << GPIO_OSPEED7_SHIFT) -#define GPIO_OSPEED8_SHIFT (16) -#define GPIO_OSPEED8_MASK (3 << GPIO_OSPEED8_SHIFT) -#define GPIO_OSPEED9_SHIFT (18) -#define GPIO_OSPEED9_MASK (3 << GPIO_OSPEED9_SHIFT) -#define GPIO_OSPEED10_SHIFT (20) -#define GPIO_OSPEED10_MASK (3 << GPIO_OSPEED10_SHIFT) -#define GPIO_OSPEED11_SHIFT (22) -#define GPIO_OSPEED11_MASK (3 << GPIO_OSPEED11_SHIFT) -#define GPIO_OSPEED12_SHIFT (24) -#define GPIO_OSPEED12_MASK (3 << GPIO_OSPEED12_SHIFT) -#define GPIO_OSPEED13_SHIFT (26) -#define GPIO_OSPEED13_MASK (3 << GPIO_OSPEED13_SHIFT) -#define GPIO_OSPEED14_SHIFT (28) -#define GPIO_OSPEED14_MASK (3 << GPIO_OSPEED14_SHIFT) -#define GPIO_OSPEED15_SHIFT (30) -#define GPIO_OSPEED15_MASK (3 << GPIO_OSPEED15_SHIFT) - -/* GPIO port pull-up/pull-down register */ - -#define GPIO_PUPDR_NONE (0) /* No pull-up, pull-down */ -#define GPIO_PUPDR_PULLUP (1) /* Pull-up */ -#define GPIO_PUPDR_PULLDOWN (2) /* Pull-down */ - -#define GPIO_PUPDR_SHIFT(n) ((n) << 1) -#define GPIO_PUPDR_MASK(n) (3 << GPIO_PUPDR_SHIFT(n)) - -#define GPIO_PUPDR0_SHIFT (0) -#define GPIO_PUPDR0_MASK (3 << GPIO_PUPDR0_SHIFT) -#define GPIO_PUPDR1_SHIFT (2) -#define GPIO_PUPDR1_MASK (3 << GPIO_PUPDR1_SHIFT) -#define GPIO_PUPDR2_SHIFT (4) -#define GPIO_PUPDR2_MASK (3 << GPIO_PUPDR2_SHIFT) -#define GPIO_PUPDR3_SHIFT (6) -#define GPIO_PUPDR3_MASK (3 << GPIO_PUPDR3_SHIFT) -#define GPIO_PUPDR4_SHIFT (8) -#define GPIO_PUPDR4_MASK (3 << GPIO_PUPDR4_SHIFT) -#define GPIO_PUPDR5_SHIFT (10) -#define GPIO_PUPDR5_MASK (3 << GPIO_PUPDR5_SHIFT) -#define GPIO_PUPDR6_SHIFT (12) -#define GPIO_PUPDR6_MASK (3 << GPIO_PUPDR6_SHIFT) -#define GPIO_PUPDR7_SHIFT (14) -#define GPIO_PUPDR7_MASK (3 << GPIO_PUPDR7_SHIFT) -#define GPIO_PUPDR8_SHIFT (16) -#define GPIO_PUPDR8_MASK (3 << GPIO_PUPDR8_SHIFT) -#define GPIO_PUPDR9_SHIFT (18) -#define GPIO_PUPDR9_MASK (3 << GPIO_PUPDR9_SHIFT) -#define GPIO_PUPDR10_SHIFT (20) -#define GPIO_PUPDR10_MASK (3 << GPIO_PUPDR10_SHIFT) -#define GPIO_PUPDR11_SHIFT (22) -#define GPIO_PUPDR11_MASK (3 << GPIO_PUPDR11_SHIFT) -#define GPIO_PUPDR12_SHIFT (24) -#define GPIO_PUPDR12_MASK (3 << GPIO_PUPDR12_SHIFT) -#define GPIO_PUPDR13_SHIFT (26) -#define GPIO_PUPDR13_MASK (3 << GPIO_PUPDR13_SHIFT) -#define GPIO_PUPDR14_SHIFT (28) -#define GPIO_PUPDR14_MASK (3 << GPIO_PUPDR14_SHIFT) -#define GPIO_PUPDR15_SHIFT (30) -#define GPIO_PUPDR15_MASK (3 << GPIO_PUPDR15_SHIFT) - -/* GPIO port input data register */ - -#define GPIO_IDR(n) (1 << (n)) - -/* GPIO port output data register */ - -#define GPIO_ODR(n) (1 << (n)) - -/* GPIO port bit set/reset register */ - -#define GPIO_BSRR_SET(n) (1 << (n)) -#define GPIO_BSRR_RESET(n) (1 << ((n) + 16)) - -/* GPIO port configuration lock register */ - -#define GPIO_LCKR(n) (1 << (n)) -#define GPIO_LCKK (1 << 16) /* Lock key */ - -/* GPIO alternate function low/high register */ - -#define GPIO_AFR_SHIFT(n) ((n) << 2) -#define GPIO_AFR_MASK(n) (15 << GPIO_AFR_SHIFT(n)) - -#define GPIO_AFRL0_SHIFT (0) -#define GPIO_AFRL0_MASK (15 << GPIO_AFRL0_SHIFT) -#define GPIO_AFRL1_SHIFT (4) -#define GPIO_AFRL1_MASK (15 << GPIO_AFRL1_SHIFT) -#define GPIO_AFRL2_SHIFT (8) -#define GPIO_AFRL2_MASK (15 << GPIO_AFRL2_SHIFT) -#define GPIO_AFRL3_SHIFT (12) -#define GPIO_AFRL3_MASK (15 << GPIO_AFRL3_SHIFT) -#define GPIO_AFRL4_SHIFT (16) -#define GPIO_AFRL4_MASK (15 << GPIO_AFRL4_SHIFT) -#define GPIO_AFRL5_SHIFT (20) -#define GPIO_AFRL5_MASK (15 << GPIO_AFRL5_SHIFT) -#define GPIO_AFRL6_SHIFT (24) -#define GPIO_AFRL6_MASK (15 << GPIO_AFRL6_SHIFT) -#define GPIO_AFRL7_SHIFT (28) -#define GPIO_AFRL7_MASK (15 << GPIO_AFRL7_SHIFT) - -/* GPIO port bit reset register */ - -#define GPIO_BRR(n) (1 << (n)) - -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_GPIO_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32_i2c.h b/arch/arm/src/stm32f0l0g0/hardware/stm32_i2c.h deleted file mode 100644 index aa10265f4a93b..0000000000000 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32_i2c.h +++ /dev/null @@ -1,227 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32_i2c.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_I2C_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_I2C_H - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Register Offsets *********************************************************/ - -#define STM32_I2C_CR1_OFFSET 0x0000 /* Control register 1 (32-bit) */ -#define STM32_I2C_CR2_OFFSET 0x0004 /* Control register 2 (32-bit) */ -#define STM32_I2C_OAR1_OFFSET 0x0008 /* Own address register 1 (16-bit) */ -#define STM32_I2C_OAR2_OFFSET 0x000c /* Own address register 2 (16-bit) */ -#define STM32_I2C_TIMINGR_OFFSET 0x0010 /* Timing register */ -#define STM32_I2C_TIMEOUTR_OFFSET 0x0014 /* Timeout register */ -#define STM32_I2C_ISR_OFFSET 0x0018 /* Interrupt and Status register */ -#define STM32_I2C_ICR_OFFSET 0x001c /* Interrupt clear register */ -#define STM32_I2C_PECR_OFFSET 0x0020 /* Packet error checking register */ -#define STM32_I2C_RXDR_OFFSET 0x0024 /* Receive data register */ -#define STM32_I2C_TXDR_OFFSET 0x0028 /* Transmit data register */ - -/* Register Addresses *******************************************************/ - -#if STM32_NI2C > 0 -# define STM32_I2C1_CR1 (STM32_I2C1_BASE + STM32_I2C_CR1_OFFSET) -# define STM32_I2C1_CR2 (STM32_I2C1_BASE + STM32_I2C_CR2_OFFSET) -# define STM32_I2C1_OAR1 (STM32_I2C1_BASE + STM32_I2C_OAR1_OFFSET) -# define STM32_I2C1_OAR2 (STM32_I2C1_BASE + STM32_I2C_OAR2_OFFSET) -# define STM32_I2C1_TIMINGR (STM32_I2C1_BASE + STM32_I2C_TIMINGR_OFFSET) -# define STM32_I2C1_TIMEOUTR (STM32_I2C1_BASE + STM32_I2C_TIMEOUTR_OFFSET) -# define STM32_I2C1_ISR (STM32_I2C1_BASE + STM32_I2C_ISR_OFFSET) -# define STM32_I2C1_ICR (STM32_I2C1_BASE + STM32_I2C_ICR_OFFSET) -# define STM32_I2C1_PECR (STM32_I2C1_BASE + STM32_I2C_PECR_OFFSET) -# define STM32_I2C1_RXDR (STM32_I2C1_BASE + STM32_I2C_RXDR_OFFSET) -# define STM32_I2C1_TXDR (STM32_I2C1_BASE + STM32_I2C_TXDR_OFFSET) -#endif - -#if STM32_NI2C > 1 -# define STM32_I2C2_CR1 (STM32_I2C2_BASE + STM32_I2C_CR1_OFFSET) -# define STM32_I2C2_CR2 (STM32_I2C2_BASE + STM32_I2C_CR2_OFFSET) -# define STM32_I2C2_OAR1 (STM32_I2C2_BASE + STM32_I2C_OAR1_OFFSET) -# define STM32_I2C2_OAR2 (STM32_I2C2_BASE + STM32_I2C_OAR2_OFFSET) -# define STM32_I2C2_TIMINGR (STM32_I2C2_BASE + STM32_I2C_TIMINGR_OFFSET) -# define STM32_I2C2_TIMEOUTR (STM32_I2C2_BASE + STM32_I2C_TIMEOUTR_OFFSET) -# define STM32_I2C2_ISR (STM32_I2C2_BASE + STM32_I2C_ISR_OFFSET) -# define STM32_I2C2_ICR (STM32_I2C2_BASE + STM32_I2C_ICR_OFFSET) -# define STM32_I2C2_PECR (STM32_I2C2_BASE + STM32_I2C_PECR_OFFSET) -# define STM32_I2C2_RXDR (STM32_I2C2_BASE + STM32_I2C_RXDR_OFFSET) -# define STM32_I2C2_TXDR (STM32_I2C2_BASE + STM32_I2C_TXDR_OFFSET) -#endif - -/* Register Bitfield Definitions ********************************************/ - -/* Control register 1 */ - -#define I2C_CR1_PE (1 << 0) /* Bit 0: Peripheral Enable */ -#define I2C_CR1_TXIE (1 << 1) /* Bit 1: TX Interrupt enable */ -#define I2C_CR1_RXIE (1 << 2) /* Bit 2: RX Interrupt enable */ -#define I2C_CR1_ADDRIE (1 << 3) /* Bit 3: Address match interrupt enable (slave) */ -#define I2C_CR1_NACKIE (1 << 4) /* Bit 4: Not acknowledge received interrupt enable */ -#define I2C_CR1_STOPIE (1 << 5) /* Bit 5: STOP detection interrupt enable */ -#define I2C_CR1_TCIE (1 << 6) /* Bit 6: Transfer Complete interrupt enable */ -#define I2C_CR1_ERRIE (1 << 7) /* Bit 7: Error interrupts enable */ -#define I2C_CR1_DNF_SHIFT (8) /* Bits 8-11: Digital noise filter */ -#define I2C_CR1_DNF_MASK (15 << I2C_CR1_DNF_SHIFT) -# define I2C_CR1_DNF_DISABLE (0 << I2C_CR1_DNF_SHIFT) -# define I2C_CR1_DNF(n) ((n) << I2C_CR1_DNF_SHIFT) /* Up to n * Ti2cclk, n=1..15 */ - -#define I2C_CR1_ANFOFF (1 << 12) /* Bit 12: Analog noise filter OFF */ -#define I2C_CR1_TXDMAEN (1 << 14) /* Bit 14: DMA transmission requests enable */ -#define I2C_CR1_RXDMAEN (1 << 15) /* Bit 15: DMA reception requests enable */ -#define I2C_CR1_SBC (1 << 16) /* Bit 16: Slave byte control */ -#define I2C_CR1_NOSTRETCH (1 << 17) /* Bit 17: Clock stretching disable */ -#define I2C_CR1_WUPEN (1 << 18) /* Bit 18: Wakeup from STOP enable */ -#define I2C_CR1_GCEN (1 << 19) /* Bit 19: General call enable */ -#define I2C_CR1_SMBHEN (1 << 20) /* Bit 20: SMBus Host address enable */ -#define I2C_CR1_SMBDEN (1 << 21) /* Bit 21: SMBus Device Default address enable */ -#define I2C_CR1_ALERTEN (1 << 22) /* Bit 22: SMBus alert enable */ -#define I2C_CR1_PECEN (1 << 23) /* Bit 23: PEC enable */ - -/* Control register 2 */ - -#define I2C_CR2_SADD10_SHIFT (0) /* Bits 0-9: Slave 10-bit address (master) */ -#define I2C_CR2_SADD10_MASK (0x3ff << I2C_CR2_SADD10_SHIFT) -#define I2C_CR2_SADD7_SHIFT (1) /* Bits 1-7: Slave 7-bit address (master) */ -#define I2C_CR2_SADD7_MASK (0x7f << I2C_CR2_SADD7_SHIFT) -#define I2C_CR2_RD_WRN (1 << 10) /* Bit 10: Transfer direction (master) */ -#define I2C_CR2_ADD10 (1 << 11) /* Bit 11: 10-bit addressing mode (master) */ -#define I2C_CR2_HEAD10R (1 << 12) /* Bit 12: 10-bit address header only read direction (master) */ -#define I2C_CR2_START (1 << 13) /* Bit 13: Start generation */ -#define I2C_CR2_STOP (1 << 14) /* Bit 14: Stop generation (master) */ -#define I2C_CR2_NACK (1 << 15) /* Bit 15: NACK generation (slave) */ -#define I2C_CR2_NBYTES_SHIFT (16) /* Bits 16-23: Number of bytes */ -#define I2C_CR2_NBYTES_MASK (0xff << I2C_CR2_NBYTES_SHIFT) -#define I2C_CR2_RELOAD (1 << 24) /* Bit 24: NBYTES reload mode */ -#define I2C_CR2_AUTOEND (1 << 25) /* Bit 25: Automatic end mode (master) */ -#define I2C_CR2_PECBYTE (1 << 26) /* Bit 26: Packet error checking byte */ - -/* Own address register 1 */ - -#define I2C_OAR1_OA1_10_SHIFT (0) /* Bits 0-9: 10-bit interface address */ -#define I2C_OAR1_OA1_10_MASK (0x3ff << I2C_OAR1_OA1_10_SHIFT) -#define I2C_OAR1_OA1_7_SHIFT (1) /* Bits 1-7: 7-bit interface address */ -#define I2C_OAR1_OA1_7_MASK (0x7f << I2C_OAR1_OA1_7_SHIFT) -#define I2C_OAR1_OA1MODE (1 << 10) /* Bit 10: Own Address 1 10-bit mode */ -#define I2C_OAR1_OA1EN (1 << 15) /* Bit 15: Own Address 1 enable */ - -/* Own address register 2 */ - -#define I2C_OAR2_OA2_SHIFT (1) /* Bits 1-7: 7-bit interface address */ -#define I2C_OAR2_OA2_MASK (0x7f << I2C_OAR2_OA2_SHIFT) -#define I2C_OAR2_OA2MSK_SHIFT (8) /* Bits 8-10: Own Address 2 masks */ -#define I2C_OAR2_OA2MSK_MASK (7 << I2C_OAR2_OA2MSK_SHIFT) -# define I2C_OAR2_OA2MSK_NONE (0 << I2C_OAR2_OA2MSK_SHIFT) /* No mask */ -# define I2C_OAR2_OA2MSK_2_7 (1 << I2C_OAR2_OA2MSK_SHIFT) /* Only OA2[7:2] are compared */ -# define I2C_OAR2_OA2MSK_3_7 (2 << I2C_OAR2_OA2MSK_SHIFT) /* Only OA2[7:3] are compared */ -# define I2C_OAR2_OA2MSK_4_7 (3 << I2C_OAR2_OA2MSK_SHIFT) /* Only OA2[7:4] are compared */ -# define I2C_OAR2_OA2MSK_5_7 (4 << I2C_OAR2_OA2MSK_SHIFT) /* Only OA2[7:5] are compared */ -# define I2C_OAR2_OA2MSK_6_7 (5 << I2C_OAR2_OA2MSK_SHIFT) /* Only OA2[7:6] are compared */ -# define I2C_OAR2_OA2MSK_7 (6 << I2C_OAR2_OA2MSK_SHIFT) /* Only OA2[7] is compared */ -# define I2C_OAR2_OA2MSK_ALL (7 << I2C_OAR2_OA2MSK_SHIFT) /* All 7-bit addresses acknowledged */ - -#define I2C_OAR2_OA2EN (1 << 15) /* Bit 15: Own Address 2 enable */ - -/* Timing register */ - -#define I2C_TIMINGR_SCLL_SHIFT (0) /* Bits 0-7: SCL low period (master) */ -#define I2C_TIMINGR_SCLL_MASK (0xff << I2C_TIMINGR_SCLL_SHIFT) -# define I2C_TIMINGR_SCLL(n) (((n)-1) << I2C_TIMINGR_SCLL_SHIFT) /* tSCLL = n x tPRESC */ - -#define I2C_TIMINGR_SCLH_SHIFT (8) /* Bits 8-15: SCL high period (master) */ -#define I2C_TIMINGR_SCLH_MASK (0xff << I2C_TIMINGR_SCLH_SHIFT) -# define I2C_TIMINGR_SCLH(n) (((n)-1) << I2C_TIMINGR_SCLH_SHIFT) /* tSCLH = n x tPRESC */ - -#define I2C_TIMINGR_SDADEL_SHIFT (16) /* Bits 16-19: Data hold time */ -#define I2C_TIMINGR_SDADEL_MASK (15 << I2C_TIMINGR_SDADEL_SHIFT) -# define I2C_TIMINGR_SDADEL(n) ((n) << I2C_TIMINGR_SDADEL_SHIFT) /* tSDADEL= n x tPRESC */ - -#define I2C_TIMINGR_SCLDEL_SHIFT (20) /* Bits 20-23: Data setup time */ -#define I2C_TIMINGR_SCLDEL_MASK (15 << I2C_TIMINGR_SCLDEL_SHIFT) -# define I2C_TIMINGR_SCLDEL(n) (((n)-1) << I2C_TIMINGR_SCLDEL_SHIFT) /* tSCLDEL = n x tPRESC */ - -#define I2C_TIMINGR_PRESC_SHIFT (28) /* Bits 28-31: Timing prescaler */ -#define I2C_TIMINGR_PRESC_MASK (15 << I2C_TIMINGR_PRESC_SHIFT) -# define I2C_TIMINGR_PRESC(n) (((n)-1) << I2C_TIMINGR_PRESC_SHIFT) /* tPRESC = n x tI2CCLK */ - -/* Timeout register */ - -#define I2C_TIMEOUTR_A_SHIFT (0) /* Bits 0-11: Bus Timeout A */ -#define I2C_TIMEOUTR_A_MASK (0x0fff << I2C_TIMEOUTR_A_SHIFT) -# define I2C_TIMEOUTR_A(n) ((n) << I2C_TIMEOUTR_A_SHIFT) -#define I2C_TIMEOUTR_TIDLE (1 << 12) /* Bit 12: Idle clock timeout detection */ -#define I2C_TIMEOUTR_TIMOUTEN (1 << 15) /* Bit 15: Clock timeout enable */ -#define I2C_TIMEOUTR_B_SHIFT (16) /* Bits 16-27: Bus Timeout B */ -#define I2C_TIMEOUTR_B_MASK (0x0fff << I2C_TIMEOUTR_B_SHIFT) -# define I2C_TIMEOUTR_B(n) ((n) << I2C_TIMEOUTR_B_SHIFT) -#define I2C_TIMEOUTR_TEXTEN (1 << 31) /* Bits 31: Extended clock timeout enable */ - -/* Interrupt and Status register and interrupt clear register */ - -/* Common interrupt bits */ - -#define I2C_INT_ADDR (1 << 3) /* Bit 3: Address matched (slave) */ -#define I2C_INT_NACK (1 << 4) /* Bit 4: Not Acknowledge received flag */ -#define I2C_INT_STOP (1 << 5) /* Bit 5: Stop detection flag */ -#define I2C_INT_BERR (1 << 8) /* Bit 8: Bus error */ -#define I2C_INT_ARLO (1 << 9) /* Bit 9: Arbitration lost */ -#define I2C_INT_OVR (1 << 10) /* Bit 10: Overrun/Underrun (slave) */ -#define I2C_INT_PECERR (1 << 11) /* Bit 11: PEC Error in reception */ -#define I2C_INT_TIMEOUT (1 << 12) /* Bit 12: Timeout or tLOW detection flag */ -#define I2C_INT_ALERT (1 << 13) /* Bit 13: SMBus alert */ - -/* Fields unique to the Interrupt and Status register */ - -#define I2C_ISR_TXE (1 << 0) /* Bit 0: Transmit data register empty (transmitters) */ -#define I2C_ISR_TXIS (1 << 1) /* Bit 1: Transmit interrupt status (transmitters) */ -#define I2C_ISR_RXNE (1 << 2) /* Bit 2: Receive data register not empty (receivers) */ -#define I2C_ISR_ADDR (1 << 3) /* Bit 3: Address Match (slave mode) */ -#define I2C_ISR_NACKF (1 << 4) /* Bit 4: Not Acknowledge received flag */ -#define I2C_ISR_STOPF (1 << 5) /* Bit 5: Stop detection flag */ -#define I2C_ISR_TC (1 << 6) /* Bit 6: Transfer Complete (master) */ -#define I2C_ISR_TCR (1 << 7) /* Bit 7: Transfer Complete Reload */ -#define I2C_ISR_BUSY (1 << 15) /* Bit 15: Bus busy */ -#define I2C_ISR_DIR (1 << 16) /* Bit 16: Transfer direction (slave) */ -#define I2C_ISR_ADDCODE_SHIFT (17) /* Bits 17-23: Address match code (slave) */ -#define I2C_ISR_ADDCODE_MASK (0x7f << I2C_ISR_ADDCODE_SHIFT) - -#define I2C_ISR_ERRORMASK (I2C_INT_BERR | I2C_INT_ARLO | I2C_INT_OVR | I2C_INT_PECERR | I2C_INT_TIMEOUT) - -#define I2C_ICR_CLEARMASK (I2C_INT_ADDR | I2C_INT_NACK | I2C_INT_STOP | I2C_INT_BERR | I2C_INT_ARLO \ - | I2C_INT_OVR | I2C_INT_PECERR | I2C_INT_TIMEOUT | I2C_INT_ALERT) - -/* Packet error checking register */ - -#define I2C_PECR_MASK (0xff) - -/* Receive data register */ - -#define I2C_RXDR_MASK (0xff) - -/* Transmit data register */ - -#define I2C_TXDR_MASK (0xff) - -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_I2C_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32_memorymap.h b/arch/arm/src/stm32f0l0g0/hardware/stm32_memorymap.h deleted file mode 100644 index dba663e2a366d..0000000000000 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32_memorymap.h +++ /dev/null @@ -1,49 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32_memorymap.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_MEMORYMAP_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_MEMORYMAP_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include "chip.h" - -#if defined(CONFIG_STM32F0L0G0_STM32F03X) -# include "hardware/stm32f03x_memorymap.h" -#elif defined(CONFIG_STM32F0L0G0_STM32F05X) || \ - defined(CONFIG_STM32F0L0G0_STM32F07X) || \ - defined(CONFIG_STM32F0L0G0_STM32F09X) -# include "hardware/stm32f05xf07xf09x_memorymap.h" -#elif defined(CONFIG_ARCH_CHIP_STM32L0) -# include "hardware/stm32l0_memorymap.h" -#elif defined(CONFIG_ARCH_CHIP_STM32G0) -# include "hardware/stm32g0_memorymap.h" -#elif defined(CONFIG_ARCH_CHIP_STM32C0) -# include "hardware/stm32c0_memorymap.h" -#else -# error "Unsupported STM32 M0 memory map" -#endif - -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_MEMORYMAP_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32_pinmap.h b/arch/arm/src/stm32f0l0g0/hardware/stm32_pinmap.h deleted file mode 100644 index 54cea66eed1ea..0000000000000 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32_pinmap.h +++ /dev/null @@ -1,51 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32_pinmap.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_PINMAP_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_PINMAP_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include "chip.h" - -#if defined(CONFIG_STM32F0L0G0_STM32F03X) -# include "hardware/stm32f03x_pinmap.h" -#elif defined(CONFIG_STM32F0L0G0_STM32F05X) -# include "hardware/stm32f05x_pinmap.h" -#elif defined(CONFIG_STM32F0L0G0_STM32F07X) -# include "hardware/stm32f07x_pinmap.h" -#elif defined(CONFIG_STM32F0L0G0_STM32F09X) -# include "hardware/stm32f09x_pinmap.h" -#elif defined(CONFIG_ARCH_CHIP_STM32L0) -# include "hardware/stm32l0_pinmap.h" -#elif defined(CONFIG_ARCH_CHIP_STM32G0) -# include "hardware/stm32g0_pinmap.h" -#elif defined(CONFIG_ARCH_CHIP_STM32C0) -# include "hardware/stm32c0_pinmap.h" -#else -# error "Unsupported STM32 M0 pin map" -#endif - -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_PINMAP_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32_pwr.h b/arch/arm/src/stm32f0l0g0/hardware/stm32_pwr.h deleted file mode 100644 index bdb173a17cbf1..0000000000000 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32_pwr.h +++ /dev/null @@ -1,45 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32_pwr.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_PWR_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_PWR_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include "chip.h" - -#if defined(CONFIG_ARCH_CHIP_STM32F0) -# include "hardware/stm32f0_pwr.h" -#elif defined(CONFIG_ARCH_CHIP_STM32L0) -# include "hardware/stm32l0_pwr.h" -#elif defined(CONFIG_ARCH_CHIP_STM32G0) -# include "hardware/stm32g0_pwr.h" -#elif defined(CONFIG_ARCH_CHIP_STM32C0) -# include "hardware/stm32c0_pwr.h" -#else -# error "Unsupported STM32 M0 PWR" -#endif - -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_PWR_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32_rcc.h b/arch/arm/src/stm32f0l0g0/hardware/stm32_rcc.h deleted file mode 100644 index 9242ac00ff6bd..0000000000000 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32_rcc.h +++ /dev/null @@ -1,45 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32_rcc.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_RCC_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_RCC_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include "chip.h" - -#if defined(CONFIG_ARCH_CHIP_STM32F0) -# include "hardware/stm32f0_rcc.h" -#elif defined(CONFIG_ARCH_CHIP_STM32L0) -# include "hardware/stm32l0_rcc.h" -#elif defined(CONFIG_ARCH_CHIP_STM32G0) -# include "hardware/stm32g0_rcc.h" -#elif defined(CONFIG_ARCH_CHIP_STM32C0) -# include "hardware/stm32c0_rcc.h" -#else -# error "Unsupported STM32 M0 RCC" -#endif - -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_RCC_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32_rng.h b/arch/arm/src/stm32f0l0g0/hardware/stm32_rng.h deleted file mode 100644 index 7155e94758101..0000000000000 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32_rng.h +++ /dev/null @@ -1,65 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32_rng.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_RNG_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_RNG_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include "chip.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Register Offsets *********************************************************/ - -#define STM32_RNG_CR_OFFSET 0x0000 /* RNG Control Register */ -#define STM32_RNG_SR_OFFSET 0x0004 /* RNG Status Register */ -#define STM32_RNG_DR_OFFSET 0x0008 /* RNG Data Register */ - -/* Register Addresses *******************************************************/ - -#define STM32_RNG_CR (STM32_RNG_BASE+STM32_RNG_CR_OFFSET) -#define STM32_RNG_SR (STM32_RNG_BASE+STM32_RNG_SR_OFFSET) -#define STM32_RNG_DR (STM32_RNG_BASE+STM32_RNG_DR_OFFSET) - -/* Register Bitfield Definitions ********************************************/ - -/* RNG Control Register */ - -#define RNG_CR_RNGEN (1 << 2) /* Bit 2: RNG enable */ -#define RNG_CR_IE (1 << 3) /* Bit 3: Interrupt enable */ -#define RNG_CR_CE (1 << 5) /* Bit 5: Clock error detection */ - -/* RNG Status Register */ - -#define RNG_SR_DRDY (1 << 0) /* Bit 0: Data ready */ -#define RNG_SR_CECS (1 << 1) /* Bit 1: Clock error current status */ -#define RNG_SR_SECS (1 << 2) /* Bit 2: Seed error current status */ -#define RNG_SR_CEIS (1 << 5) /* Bit 5: Clock error interrupt status */ -#define RNG_SR_SEIS (1 << 6) /* Bit 6: Seed error interrupt status */ - -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_RNG_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32_rtcc.h b/arch/arm/src/stm32f0l0g0/hardware/stm32_rtcc.h deleted file mode 100644 index 78145ffc5ca28..0000000000000 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32_rtcc.h +++ /dev/null @@ -1,314 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32_rtcc.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_RTCC_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_RTCC_H - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Register Offsets *********************************************************/ - -#define STM32_RTC_TR_OFFSET 0x0000 /* RTC time register */ -#define STM32_RTC_DR_OFFSET 0x0004 /* RTC date register */ -#define STM32_RTC_CR_OFFSET 0x0008 /* RTC control register */ -#define STM32_RTC_ISR_OFFSET 0x000c /* RTC initialization and status register */ -#define STM32_RTC_PRER_OFFSET 0x0010 /* RTC prescaler register */ -#define STM32_RTC_WUTR_OFFSET 0x0014 /* RTC wakeup timer register */ -#define STM32_RTC_ALRMAR_OFFSET 0x001c /* RTC alarm A register */ -#define STM32_RTC_WPR_OFFSET 0x0024 /* RTC write protection register */ -#define STM32_RTC_SSR_OFFSET 0x0028 /* RTC sub second register */ -#define STM32_RTC_SHIFTR_OFFSET 0x002c /* RTC shift control register */ -#define STM32_RTC_TSTR_OFFSET 0x0030 /* RTC time stamp time register */ -#define STM32_RTC_TSDR_OFFSET 0x0034 /* RTC time stamp date register */ -#define STM32_RTC_TSSSR_OFFSET 0x0038 /* RTC timestamp sub second register */ -#define STM32_RTC_CALR_OFFSET 0x003c /* RTC calibration register */ -#define STM32_RTC_TAFCR_OFFSET 0x0040 /* RTC tamper and alternate function configuration register */ -#define STM32_RTC_ALRMASSR_OFFSET 0x0044 /* RTC alarm A sub second register */ - -#define STM32_RTC_BKR_OFFSET(n) (0x0050 + ((n) << 2)) -#define STM32_RTC_BK0R_OFFSET 0x0050 /* RTC backup register 0 */ -#define STM32_RTC_BK1R_OFFSET 0x0054 /* RTC backup register 1 */ -#define STM32_RTC_BK2R_OFFSET 0x0058 /* RTC backup register 2 */ -#define STM32_RTC_BK3R_OFFSET 0x005c /* RTC backup register 3 */ -#define STM32_RTC_BK4R_OFFSET 0x0060 /* RTC backup register 4 */ - -/* Register Addresses *******************************************************/ - -#define STM32_RTC_TR (STM32_RTC_BASE + STM32_RTC_TR_OFFSET) -#define STM32_RTC_DR (STM32_RTC_BASE + STM32_RTC_DR_OFFSET) -#define STM32_RTC_CR (STM32_RTC_BASE + STM32_RTC_CR_OFFSET) -#define STM32_RTC_ISR (STM32_RTC_BASE + STM32_RTC_ISR_OFFSET) -#define STM32_RTC_PRER (STM32_RTC_BASE + STM32_RTC_PRER_OFFSET) -#define STM32_RTC_WUTR (STM32_RTC_BASE + STM32_RTC_WUTR_OFFSET) -#define STM32_RTC_ALRMAR (STM32_RTC_BASE + STM32_RTC_ALRMAR_OFFSET) -#define STM32_RTC_WPR (STM32_RTC_BASE + STM32_RTC_WPR_OFFSET) -#define STM32_RTC_SSR (STM32_RTC_BASE + STM32_RTC_SSR_OFFSET) -#define STM32_RTC_SHIFTR (STM32_RTC_BASE + STM32_RTC_SHIFTR_OFFSET) -#define STM32_RTC_TSTR (STM32_RTC_BASE + STM32_RTC_TSTR_OFFSET) -#define STM32_RTC_TSDR (STM32_RTC_BASE + STM32_RTC_TSDR_OFFSET) -#define STM32_RTC_TSSSR (STM32_RTC_BASE + STM32_RTC_TSSSR_OFFSET) -#define STM32_RTC_CALR (STM32_RTC_BASE + STM32_RTC_CALR_OFFSET) -#define STM32_RTC_TAFCR (STM32_RTC_BASE + STM32_RTC_TAFCR_OFFSET) -#define STM32_RTC_ALRMASSR (STM32_RTC_BASE + STM32_RTC_ALRMASSR_OFFSET) - -#define STM32_RTC_BKR(n) (STM32_RTC_BASE + STM32_RTC_BKR_OFFSET(n)) -#define STM32_RTC_BK0R (STM32_RTC_BASE + STM32_RTC_BK0R_OFFSET) -#define STM32_RTC_BK1R (STM32_RTC_BASE + STM32_RTC_BK1R_OFFSET) -#define STM32_RTC_BK2R (STM32_RTC_BASE + STM32_RTC_BK2R_OFFSET) -#define STM32_RTC_BK3R (STM32_RTC_BASE + STM32_RTC_BK3R_OFFSET) -#define STM32_RTC_BK4R (STM32_RTC_BASE + STM32_RTC_BK4R_OFFSET) - -#define STM32_RTC_BKCOUNT 5 - -/* Register Bitfield Definitions ********************************************/ - -/* RTC time register */ - -#define RTC_TR_SU_SHIFT (0) /* Bits 0-3: Second units in BCD format */ -#define RTC_TR_SU_MASK (15 << RTC_TR_SU_SHIFT) -#define RTC_TR_ST_SHIFT (4) /* Bits 4-6: Second tens in BCD format */ -#define RTC_TR_ST_MASK (7 << RTC_TR_ST_SHIFT) -#define RTC_TR_MNU_SHIFT (8) /* Bit 8-11: Minute units in BCD format */ -#define RTC_TR_MNU_MASK (15 << RTC_TR_MNU_SHIFT) -#define RTC_TR_MNT_SHIFT (12) /* Bits 12-14: Minute tens in BCD format */ -#define RTC_TR_MNT_MASK (7 << RTC_TR_MNT_SHIFT) -#define RTC_TR_HU_SHIFT (16) /* Bit 16-19: Hour units in BCD format */ -#define RTC_TR_HU_MASK (15 << RTC_TR_HU_SHIFT) -#define RTC_TR_HT_SHIFT (20) /* Bits 20-21: Hour tens in BCD format */ -#define RTC_TR_HT_MASK (3 << RTC_TR_HT_SHIFT) -#define RTC_TR_PM (1 << 22) /* Bit 22: AM/PM notation */ -#define RTC_TR_RESERVED_BITS (0xff808080) - -/* RTC date register */ - -#define RTC_DR_DU_SHIFT (0) /* Bits 0-3: Date units in BCD format */ -#define RTC_DR_DU_MASK (15 << RTC_DR_DU_SHIFT) -#define RTC_DR_DT_SHIFT (4) /* Bits 4-5: Date tens in BCD format */ -#define RTC_DR_DT_MASK (3 << RTC_DR_DT_SHIFT) -#define RTC_DR_MU_SHIFT (8) /* Bits 8-11: Month units in BCD format */ -#define RTC_DR_MU_MASK (15 << RTC_DR_MU_SHIFT) -#define RTC_DR_MT (1 << 12) /* Bit 12: Month tens in BCD format */ -#define RTC_DR_WDU_SHIFT (13) /* Bits 13-15: Week day units */ -#define RTC_DR_WDU_MASK (7 << RTC_DR_WDU_SHIFT) -# define RTC_DR_WDU_MONDAY (1 << RTC_DR_WDU_SHIFT) -# define RTC_DR_WDU_TUESDAY (2 << RTC_DR_WDU_SHIFT) -# define RTC_DR_WDU_WEDNESDAY (3 << RTC_DR_WDU_SHIFT) -# define RTC_DR_WDU_THURSDAY (4 << RTC_DR_WDU_SHIFT) -# define RTC_DR_WDU_FRIDAY (5 << RTC_DR_WDU_SHIFT) -# define RTC_DR_WDU_SATURDAY (6 << RTC_DR_WDU_SHIFT) -# define RTC_DR_WDU_SUNDAY (7 << RTC_DR_WDU_SHIFT) -#define RTC_DR_YU_SHIFT (16) /* Bits 16-19: Year units in BCD format */ -#define RTC_DR_YU_MASK (15 << RTC_DR_YU_SHIFT) -#define RTC_DR_YT_SHIFT (20) /* Bits 20-23: Year tens in BCD format */ -#define RTC_DR_YT_MASK (15 << RTC_DR_YT_SHIFT) -#define RTC_DR_RESERVED_BITS (0xff0000c0) - -/* RTC control register */ - -#define RTC_CR_WUCKSEL_SHIFT (0) /* Bits 0-2: Wakeup clock selection */ -#define RTC_CR_WUCKSEL_MASK (7 << RTC_CR_WUCKSEL_SHIFT) -# define RTC_CR_WUCKSEL_RTCDIV16 (0 << RTC_CR_WUCKSEL_SHIFT) /* 000: RTC/16 clock is selected */ -# define RTC_CR_WUCKSEL_RTCDIV8 (1 << RTC_CR_WUCKSEL_SHIFT) /* 001: RTC/8 clock is selected */ -# define RTC_CR_WUCKSEL_RTCDIV4 (2 << RTC_CR_WUCKSEL_SHIFT) /* 010: RTC/4 clock is selected */ -# define RTC_CR_WUCKSEL_RTCDIV2 (3 << RTC_CR_WUCKSEL_SHIFT) /* 011: RTC/2 clock is selected */ -# define RTC_CR_WUCKSEL_CKSPRE (4 << RTC_CR_WUCKSEL_SHIFT) /* 10x: ck_spre clock is selected */ -# define RTC_CR_WUCKSEL_CKSPREADD (6 << RTC_CR_WUCKSEL_SHIFT) /* 11x: ck_spr clock and 216 added WUT counter */ - -#define RTC_CR_TSEDGE (1 << 3) /* Bit 3: Timestamp event active edge */ -#define RTC_CR_REFCKON (1 << 4) /* Bit 4: Reference clock detection enable (50 or 60 Hz) */ -#define RTC_CR_BYPSHAD (1 << 5) /* Bit 5: Bypass the shadow registers */ -#define RTC_CR_FMT (1 << 6) /* Bit 6: Hour format */ -#define RTC_CR_ALRAE (1 << 8) /* Bit 8: Alarm A enable */ -#define RTC_CR_WUTE (1 << 10) /* Bit 10: Wakeup timer enable */ -#define RTC_CR_TSE (1 << 11) /* Bit 11: Time stamp enable */ -#define RTC_CR_ALRAIE (1 << 12) /* Bit 12: Alarm A interrupt enable */ -#define RTC_CR_WUTIE (1 << 14) /* Bit 14: Wakeup timer interrupt enable */ -#define RTC_CR_TSIE (1 << 15) /* Bit 15: Timestamp interrupt enable */ -#define RTC_CR_ADD1H (1 << 16) /* Bit 16: Add 1 hour (summer time change) */ -#define RTC_CR_SUB1H (1 << 17) /* Bit 17: Subtract 1 hour (winter time change) */ -#define RTC_CR_BKP (1 << 18) /* Bit 18: Backup */ -#define RTC_CR_COSEL (1 << 19) /* Bit 19: Calibration output selection */ -#define RTC_CR_POL (1 << 20) /* Bit 20: Output polarity */ -#define RTC_CR_OSEL_SHIFT (21) /* Bits 21-22: Output selection */ -#define RTC_CR_OSEL_MASK (3 << RTC_CR_OSEL_SHIFT) -# define RTC_CR_OSEL_DISABLED (0 << RTC_CR_OSEL_SHIFT) /* 00: Output disabled */ -# define RTC_CR_OSEL_ALRMA (1 << RTC_CR_OSEL_SHIFT) /* 01: Alarm A output enabled */ -# define RTC_CR_OSEL_ALRMB (2 << RTC_CR_OSEL_SHIFT) /* 10: Alarm B output enabled */ -# define RTC_CR_OSEL_WUT (3 << RTC_CR_OSEL_SHIFT) /* 11: Wakeup output enabled */ - -#define RTC_CR_COE (1 << 23) /* Bit 23: Calibration output enable */ - -/* RTC initialization and status register */ - -#define RTC_ISR_ALRAWF (1 << 0) /* Bit 0: Alarm A write flag */ -#define RTC_ISR_WUTWF (1 << 2) /* Bit 2: Wakeup timer write flag */ -#define RTC_ISR_SHPF (1 << 3) /* Bit 3: Shift operation pending */ -#define RTC_ISR_INITS (1 << 4) /* Bit 4: Initialization status flag */ -#define RTC_ISR_RSF (1 << 5) /* Bit 5: Registers synchronization flag */ -#define RTC_ISR_INITF (1 << 6) /* Bit 6: Initialization flag */ -#define RTC_ISR_INIT (1 << 7) /* Bit 7: Initialization mode */ -#define RTC_ISR_ALRAF (1 << 8) /* Bit 8: Alarm A flag */ -#define RTC_ISR_WUTF (1 << 10) /* Bit 10: Wakeup timer flag */ -#define RTC_ISR_TSF (1 << 11) /* Bit 11: Timestamp flag */ -#define RTC_ISR_TSOVF (1 << 12) /* Bit 12: Timestamp overflow flag */ -#define RTC_ISR_TAMP1F (1 << 13) /* Bit 13: Tamper detection flag */ -#define RTC_ISR_TAMP2F (1 << 14) /* Bit 14: TAMPER2 detection flag */ -#define RTC_ISR_TAMP3F (1 << 15) /* Bit 15: TAMPER3 detection flag */ -#define RTC_ISR_RECALPF (1 << 16) /* Bit 16: Recalibration pending flag */ -#define RTC_ISR_ALLFLAGS (0x00017fff) - -/* RTC prescaler register */ - -#define RTC_PRER_PREDIV_S_SHIFT (0) /* Bits 0-14: Synchronous prescaler factor */ -#define RTC_PRER_PREDIV_S_MASK (0x7fff << RTC_PRER_PREDIV_S_SHIFT) -#define RTC_PRER_PREDIV_A_SHIFT (16) /* Bits 16-22: Asynchronous prescaler factor */ -#define RTC_PRER_PREDIV_A_MASK (0x7f << RTC_PRER_PREDIV_A_SHIFT) - -/* RTC wakeup timer register */ - -#define RTC_WUTR_MASK (0xffff) /* Bits 15:0 Wakeup auto-reload value bits */ - -/* RTC alarm A register */ - -#define RTC_ALRMR_SU_SHIFT (0) /* Bits 0-3: Second units in BCD format. */ -#define RTC_ALRMR_SU_MASK (15 << RTC_ALRMR_SU_SHIFT) -#define RTC_ALRMR_ST_SHIFT (4) /* Bits 4-6: Second tens in BCD format. */ -#define RTC_ALRMR_ST_MASK (7 << RTC_ALRMR_ST_SHIFT) -#define RTC_ALRMR_MSK1 (1 << 7) /* Bit 7 : Alarm A seconds mask */ -#define RTC_ALRMR_MNU_SHIFT (8) /* Bits 8-11: Minute units in BCD format. */ -#define RTC_ALRMR_MNU_MASK (15 << RTC_ALRMR_MNU_SHIFT) -#define RTC_ALRMR_MNT_SHIFT (12) /* Bits 12-14: Minute tens in BCD format. */ -#define RTC_ALRMR_MNT_MASK (7 << RTC_ALRMR_MNT_SHIFT) -#define RTC_ALRMR_MSK2 (1 << 15) /* Bit 15 : Alarm A minutes mask */ -#define RTC_ALRMR_HU_SHIFT (16) /* Bits 16-19: Hour units in BCD format. */ -#define RTC_ALRMR_HU_MASK (15 << RTC_ALRMR_HU_SHIFT) -#define RTC_ALRMR_HT_SHIFT (20) /* Bits 20-21: Hour tens in BCD format. */ -#define RTC_ALRMR_HT_MASK (3 << RTC_ALRMR_HT_SHIFT) -#define RTC_ALRMR_PM (1 << 22) /* Bit 22 : AM/PM notation */ -#define RTC_ALRMR_MSK3 (1 << 23) /* Bit 23 : Alarm A hours mask */ -#define RTC_ALRMR_DU_SHIFT (24) /* Bits 24-27: Date units or day in BCD format. */ -#define RTC_ALRMR_DU_MASK (15 << RTC_ALRMR_DU_SHIFT) -#define RTC_ALRMR_DT_SHIFT (28) /* Bits 28-29: Date tens in BCD format. */ -#define RTC_ALRMR_DT_MASK (3 << RTC_ALRMR_DT_SHIFT) -#define RTC_ALRMR_WDSEL (1 << 30) /* Bit 30: Week day selection */ -#define RTC_ALRMR_MSK4 (1 << 31) /* Bit 31: Alarm A date mask */ - -/* RTC write protection register */ - -#define RTC_WPR_MASK (0xff) /* Bits 0-7: Write protection key */ - -/* RTC sub second register */ - -#define RTC_SSR_MASK (0xffff) /* Bits 0-15: Sub second value */ - -/* RTC shift control register */ - -#define RTC_SHIFTR_SUBFS_SHIFT (0) /* Bits 0-14: Subtract a fraction of a second */ -#define RTC_SHIFTR_SUBFS_MASK (0x7fff << RTC_SHIFTR_SUBFS_SHIFT) -#define RTC_SHIFTR_ADD1S (1 << 31) /* Bit 31: Add one second */ - -/* RTC time stamp time register */ - -#define RTC_TSTR_SU_SHIFT (0) /* Bits 0-3: Second units in BCD format. */ -#define RTC_TSTR_SU_MASK (15 << RTC_TSTR_SU_SHIFT) -#define RTC_TSTR_ST_SHIFT (4) /* Bits 4-6: Second tens in BCD format. */ -#define RTC_TSTR_ST_MASK (7 << RTC_TSTR_ST_SHIFT) -#define RTC_TSTR_MNU_SHIFT (8) /* Bits 8-11: Minute units in BCD format. */ -#define RTC_TSTR_MNU_MASK (15 << RTC_TSTR_MNU_SHIFT) -#define RTC_TSTR_MNT_SHIFT (12) /* Bits 12-14: Minute tens in BCD format. */ -#define RTC_TSTR_MNT_MASK (7 << RTC_TSTR_MNT_SHIFT) -#define RTC_TSTR_HU_SHIFT (16) /* Bits 16-19: Hour units in BCD format. */ -#define RTC_TSTR_HU_MASK (15 << RTC_TSTR_HU_SHIFT) -#define RTC_TSTR_HT_SHIFT (20) /* Bits 20-21: Hour tens in BCD format. */ -#define RTC_TSTR_HT_MASK (3 << RTC_TSTR_HT_SHIFT) -#define RTC_TSTR_PM (1 << 22) /* Bit 22: AM/PM notation */ - -/* RTC time stamp date register */ - -#define RTC_TSDR_DU_SHIFT (0) /* Bit 0-3: Date units in BCD format */ -#define RTC_TSDR_DU_MASK (15 << RTC_TSDR_DU_SHIFT) -#define RTC_TSDR_DT_SHIFT (4) /* Bits 4-5: Date tens in BCD format */ -#define RTC_TSDR_DT_MASK (3 << RTC_TSDR_DT_SHIFT) -#define RTC_TSDR_MU_SHIFT (8) /* Bits 8-11: Month units in BCD format */ -#define RTC_TSDR_MU_MASK (15 << RTC_TSDR_MU_SHIFT) -#define RTC_TSDR_MT (1 << 12) /* Bit 12: Month tens in BCD format */ -#define RTC_TSDR_WDU_SHIFT (13) /* Bits 13-15: Week day units */ -#define RTC_TSDR_WDU_MASK (7 << RTC_TSDR_WDU_SHIFT) - -/* RTC timestamp sub second register */ - -#define RTC_TSSSR_MASK (0xffff) /* Bits 0-15: Sub second value */ - -/* RTC calibration register */ - -#define RTC_CALR_CALM_SHIFT (0) /* Bits 0-8: Calibration minus */ -#define RTC_CALR_CALM_MASK (0x1ff << RTC_CALR_CALM_SHIFT) -#define RTC_CALR_CALW16 (1 << 13) /* Bit 13: Use a 16-second calibration cycle period */ -#define RTC_CALR_CALW8 (1 << 14) /* Bit 14: Use an 8-second calibration cycle period */ -#define RTC_CALR_CALP (1 << 15) /* Bit 15: Increase frequency of RTC by 488.5 ppm */ - -/* RTC tamper and alternate function configuration register */ - -#define RTC_TAFCR_TAMP1E (1 << 0) /* Bit 0: RTC_TAMP1 input detection enable */ -#define RTC_TAFCR_TAMP1TRG (1 << 1) /* Bit 1: Active level for RTC_TAMP1 input */ -#define RTC_TAFCR_TAMPIE (1 << 2) /* Bit 2: Tamper interrupt enable */ -#define RTC_TAFCR_TAMP3E (1 << 5) /* Bit 5: RTC_TAMP3 detection enable */ -#define RTC_TAFCR_TAMP3TRG (1 << 6) /* Bit 6: Active level for RTC_TAMP3 input */ -#define RTC_TAFCR_TAMPTS (1 << 7) /* Bit 7: Activate timestamp on tamper detection event */ -#define RTC_TAFCR_TAMPFREQ_SHIFT (8) /* Bits 8-10: Tamper sampling frequency */ -#define RTC_TAFCR_TAMPFREQ_MASK (7 << RTC_TAFCR_TAMPFREQ_SHIFT) -# define RTC_TAFCR_TAMPFREQ_DIV32768 (0 << RTC_TAFCR_TAMPFREQ_SHIFT) /* RTCCLK / 32768 (1 Hz) */ -# define RTC_TAFCR_TAMPFREQ_DIV16384 (1 << RTC_TAFCR_TAMPFREQ_SHIFT) /* RTCCLK / 16384 (2 Hz) */ -# define RTC_TAFCR_TAMPFREQ_DIV8192 (2 << RTC_TAFCR_TAMPFREQ_SHIFT) /* RTCCLK / 8192 (4 Hz) */ -# define RTC_TAFCR_TAMPFREQ_DIV4096 (3 << RTC_TAFCR_TAMPFREQ_SHIFT) /* RTCCLK / 4096 (8 Hz) */ -# define RTC_TAFCR_TAMPFREQ_DIV2048 (4 << RTC_TAFCR_TAMPFREQ_SHIFT) /* RTCCLK / 2048 (16 Hz) */ -# define RTC_TAFCR_TAMPFREQ_DIV1024 (5 << RTC_TAFCR_TAMPFREQ_SHIFT) /* RTCCLK / 1024 (32 Hz) */ -# define RTC_TAFCR_TAMPFREQ_DIV512 (6 << RTC_TAFCR_TAMPFREQ_SHIFT) /* RTCCLK / 512 (64 Hz) */ -# define RTC_TAFCR_TAMPFREQ_DIV256 (7 << RTC_TAFCR_TAMPFREQ_SHIFT) /* RTCCLK / 256 (128 Hz) */ - -#define RTC_TAFCR_TAMPFLT_SHIFT (11) /* Bits 11-12: RTC_TAMPx filter count */ -#define RTC_TAFCR_TAMPFLT_MASK (3 << RTC_TAFCR_TAMPFLT_SHIFT) -#define RTC_TAFCR_TAMPPRCH_SHIFT (13) /* Bits 13-14: RTC_TAMPx precharge duration */ -#define RTC_TAFCR_TAMPPRCH_MASK (3 << RTC_TAFCR_TAMPPRCH_SHIFT) -# define RTC_TAFCR_TAMPPRCH_1CYCLE (0 << RTC_TAFCR_TAMPPRCH_SHIFT) /* 1 RTCCLK cycle */ -# define RTC_TAFCR_TAMPPRCH_2CYCLES (1 << RTC_TAFCR_TAMPPRCH_SHIFT) /* 2 RTCCLK cycles */ -# define RTC_TAFCR_TAMPPRCH_4CYCLES (2 << RTC_TAFCR_TAMPPRCH_SHIFT) /* 4 RTCCLK cycles */ -# define RTC_TAFCR_TAMPPRCH_5CYCLES (3 << RTC_TAFCR_TAMPPRCH_SHIFT) /* 8 RTCCLK cycles */ - -#define RTC_TAFCR_TAMPPUDIS (1 << 15) /* Bit 15: RTC_TAMPx pull-up disable */ -#define RTC_TAFCR_PC13VALUE (1 << 18) /* Bit 18: RTC_ALARM output type/PC13 value */ -#define RTC_TAFCR_PC13MODE (1 << 19) /* Bit 19: PC13 mode */ -#define RTC_TAFCR_PC14VALUE (1 << 20) /* Bit 20: PC14 value */ -#define RTC_TAFCR_PC14MODE (1 << 21) /* Bit 21: PC14 mode */ -#define RTC_TAFCR_PC15VALUE (1 << 22) /* Bit 22: PC15 value */ -#define RTC_TAFCR_PC15MODE (1 << 23) /* Bit 23: PC15 mode */ - -/* RTC alarm A sub second register */ - -#define RTC_ALRMSSR_SS_SHIFT (0) /* Bits 0-14: Sub second value */ -#define RTC_ALRMSSR_SS_MASK (0x7fff << RTC_ALRMSSR_SS_SHIFT) -#define RTC_ALRMSSR_MASKSS_SHIFT (24) /* Bits 24-27: Mask the most-significant bits starting at this bit */ -#define RTC_ALRMSSR_MASKSS_MASK (0xf << RTC_ALRMSSR_MASKSS_SHIFT) - -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_RTCC_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32_spi.h b/arch/arm/src/stm32f0l0g0/hardware/stm32_spi.h deleted file mode 100644 index 0a058ebf09468..0000000000000 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32_spi.h +++ /dev/null @@ -1,232 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32_spi.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_SPI_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_SPI_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include "chip.h" - -/* Select STM32 SPI IP core */ - -#if defined(CONFIG_STM32F0L0G0_STM32F0) || \ - defined(CONFIG_STM32F0L0G0_STM32G0) || \ - defined(CONFIG_STM32F0L0G0_STM32C0) -# define HAVE_IP_SPI_V2 -#elif defined(CONFIG_STM32F0L0G0_STM32L0) -# define HAVE_IP_SPI_V1 -#else -# error Unsupported family -#endif - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Maximum allowed speed as per data sheet for all SPIs - * (both pclk1 and pclk2) - */ - -#define STM32_SPI_CLK_MAX 50000000UL - -/* Register Offsets *********************************************************/ - -#define STM32_SPI_CR1_OFFSET 0x0000 /* SPI Control Register 1 (16-bit) */ -#define STM32_SPI_CR2_OFFSET 0x0004 /* SPI control register 2 (16-bit) */ -#define STM32_SPI_SR_OFFSET 0x0008 /* SPI status register (16-bit) */ -#define STM32_SPI_DR_OFFSET 0x000c /* SPI data register (16-bit) */ -#define STM32_SPI_CRCPR_OFFSET 0x0010 /* SPI CRC polynomial register (16-bit) */ -#define STM32_SPI_RXCRCR_OFFSET 0x0014 /* SPI Rx CRC register (16-bit) */ -#define STM32_SPI_TXCRCR_OFFSET 0x0018 /* SPI Tx CRC register (16-bit) */ -#define STM32_SPI_I2SCFGR_OFFSET 0x001c /* I2S configuration register */ -#define STM32_SPI_I2SPR_OFFSET 0x0020 /* I2S prescaler register */ - -/* Register Addresses *******************************************************/ - -#if STM32_NSPI > 0 -# define STM32_SPI1_CR1 (STM32_SPI1_BASE + STM32_SPI_CR1_OFFSET) -# define STM32_SPI1_CR2 (STM32_SPI1_BASE + STM32_SPI_CR2_OFFSET) -# define STM32_SPI1_SR (STM32_SPI1_BASE + STM32_SPI_SR_OFFSET) -# define STM32_SPI1_DR (STM32_SPI1_BASE + STM32_SPI_DR_OFFSET) -# define STM32_SPI1_CRCPR (STM32_SPI1_BASE + STM32_SPI_CRCPR_OFFSET) -# define STM32_SPI1_RXCRCR (STM32_SPI1_BASE + STM32_SPI_RXCRCR_OFFSET) -# define STM32_SPI1_TXCRCR (STM32_SPI1_BASE + STM32_SPI_TXCRCR_OFFSET) -#endif - -#if STM32_NSPI > 1 -# define STM32_SPI2_CR1 (STM32_SPI2_BASE + STM32_SPI_CR1_OFFSET) -# define STM32_SPI2_CR2 (STM32_SPI2_BASE + STM32_SPI_CR2_OFFSET) -# define STM32_SPI2_SR (STM32_SPI2_BASE + STM32_SPI_SR_OFFSET) -# define STM32_SPI2_DR (STM32_SPI2_BASE + STM32_SPI_DR_OFFSET) -# define STM32_SPI2_CRCPR (STM32_SPI2_BASE + STM32_SPI_CRCPR_OFFSET) -# define STM32_SPI2_RXCRCR (STM32_SPI2_BASE + STM32_SPI_RXCRCR_OFFSET) -# define STM32_SPI2_TXCRCR (STM32_SPI2_BASE + STM32_SPI_TXCRCR_OFFSET) -# define STM32_SPI2_I2SCFGR (STM32_SPI2_BASE + STM32_SPI_I2SCFGR_OFFSET) -# define STM32_SPI2_I2SPR (STM32_SPI2_BASE + STM32_SPI_I2SPR_OFFSET) -#endif - -#if STM32_NSPI > 2 -# define STM32_SPI3_CR1 (STM32_SPI3_BASE + STM32_SPI_CR1_OFFSET) -# define STM32_SPI3_CR2 (STM32_SPI3_BASE + STM32_SPI_CR2_OFFSET) -# define STM32_SPI3_SR (STM32_SPI3_BASE + STM32_SPI_SR_OFFSET) -# define STM32_SPI3_DR (STM32_SPI3_BASE + STM32_SPI_DR_OFFSET) -# define STM32_SPI3_CRCPR (STM32_SPI3_BASE + STM32_SPI_CRCPR_OFFSET) -# define STM32_SPI3_RXCRCR (STM32_SPI3_BASE + STM32_SPI_RXCRCR_OFFSET) -# define STM32_SPI3_TXCRCR (STM32_SPI3_BASE + STM32_SPI_TXCRCR_OFFSET) -# define STM32_SPI3_I2SCFGR (STM32_SPI3_BASE + STM32_SPI_I2SCFGR_OFFSET) -# define STM32_SPI3_I2SPR (STM32_SPI3_BASE + STM32_SPI_I2SPR_OFFSET) -#endif - -/* Register Bitfield Definitions ********************************************/ - -/* SPI Control Register 1 */ - -#define SPI_CR1_CPHA (1 << 0) /* Bit 0: Clock Phase */ -#define SPI_CR1_CPOL (1 << 1) /* Bit 1: Clock Polarity */ -#define SPI_CR1_MSTR (1 << 2) /* Bit 2: Master Selection */ -#define SPI_CR1_BR_SHIFT (3) /* Bits 5:3 Baud Rate Control */ -#define SPI_CR1_BR_MASK (7 << SPI_CR1_BR_SHIFT) -# define SPI_CR1_FPCLCKd2 (0 << SPI_CR1_BR_SHIFT) /* 000: fPCLK/2 */ -# define SPI_CR1_FPCLCKd4 (1 << SPI_CR1_BR_SHIFT) /* 001: fPCLK/4 */ -# define SPI_CR1_FPCLCKd8 (2 << SPI_CR1_BR_SHIFT) /* 010: fPCLK/8 */ -# define SPI_CR1_FPCLCKd16 (3 << SPI_CR1_BR_SHIFT) /* 011: fPCLK/16 */ -# define SPI_CR1_FPCLCKd32 (4 << SPI_CR1_BR_SHIFT) /* 100: fPCLK/32 */ -# define SPI_CR1_FPCLCKd64 (5 << SPI_CR1_BR_SHIFT) /* 101: fPCLK/64 */ -# define SPI_CR1_FPCLCKd128 (6 << SPI_CR1_BR_SHIFT) /* 110: fPCLK/128 */ -# define SPI_CR1_FPCLCKd256 (7 << SPI_CR1_BR_SHIFT) /* 111: fPCLK/256 */ - -#define SPI_CR1_SPE (1 << 6) /* Bit 6: SPI Enable */ -#define SPI_CR1_LSBFIRST (1 << 7) /* Bit 7: Frame Format */ -#define SPI_CR1_SSI (1 << 8) /* Bit 8: Internal slave select */ -#define SPI_CR1_SSM (1 << 9) /* Bit 9: Software slave management */ -#define SPI_CR1_RXONLY (1 << 10) /* Bit 10: Receive only */ -# ifdef HAVE_IP_SPI_V2 -# define SPI_CR1_CRCL (1 << 11) /* Bit 11: CRC length */ -#else -# define SPI_CR1_DFF (1 << 11) /* Bit 11: Data frame format */ -#endif -#define SPI_CR1_CRCNEXT (1 << 12) /* Bit 12: Transmit CRC next */ -#define SPI_CR1_CRCEN (1 << 13) /* Bit 13: Hardware CRC calculation enable */ -#define SPI_CR1_BIDIOE (1 << 14) /* Bit 14: Output enable in bidirectional mode */ -#define SPI_CR1_BIDIMODE (1 << 15) /* Bit 15: Bidirectional data mode enable */ - -/* SPI Control Register 2 */ - -#define SPI_CR2_RXDMAEN (1 << 0) /* Bit 0: Rx Buffer DMA Enable */ -#define SPI_CR2_TXDMAEN (1 << 1) /* Bit 1: Tx Buffer DMA Enable */ -#define SPI_CR2_SSOE (1 << 2) /* Bit 2: SS Output Enable */ -#ifdef HAVE_IP_SPI_V2 -# define SPI_CR2_NSSP (1 << 3) /* Bit 3 NSSP: NSS pulse management */ -#endif -#define SPI_CR2_FRF (1 << 4) /* Bit 4: Frame format */ -#define SPI_CR2_ERRIE (1 << 5) /* Bit 5: Error interrupt enable */ -#define SPI_CR2_RXNEIE (1 << 6) /* Bit 6: RX buffer not empty interrupt enable */ -#define SPI_CR2_TXEIE (1 << 7) /* Bit 7: Tx buffer empty interrupt enable */ -#ifdef HAVE_IP_SPI_V2 -# define SPI_CR2_DS_SHIFT (8) /* Bits 8-11: Data size */ -# define SPI_CR2_DS_MASK (0xf << SPI_CR2_DS_SHIFT) -# define SPI_CR2_DS_VAL(bits) (((bits)-1) << SPI_CR2_DS_SHIFT) -# define SPI_CR2_DS_4BIT SPI_CR2_DS_VAL(4) -# define SPI_CR2_DS_5BIT SPI_CR2_DS_VAL(5) -# define SPI_CR2_DS_6BIT SPI_CR2_DS_VAL(6) -# define SPI_CR2_DS_7BIT SPI_CR2_DS_VAL(7) -# define SPI_CR2_DS_8BIT SPI_CR2_DS_VAL(8) -# define SPI_CR2_DS_9BIT SPI_CR2_DS_VAL(9) -# define SPI_CR2_DS_10BIT SPI_CR2_DS_VAL(10) -# define SPI_CR2_DS_11BIT SPI_CR2_DS_VAL(11) -# define SPI_CR2_DS_12BIT SPI_CR2_DS_VAL(12) -# define SPI_CR2_DS_13BIT SPI_CR2_DS_VAL(13) -# define SPI_CR2_DS_14BIT SPI_CR2_DS_VAL(14) -# define SPI_CR2_DS_15BIT SPI_CR2_DS_VAL(15) -# define SPI_CR2_DS_16BIT SPI_CR2_DS_VAL(16) -# define SPI_CR2_FRXTH (1 << 12) /* Bit 12: FIFO reception threshold */ -# define SPI_CR2_LDMARX (1 << 13) /* Bit 13: Last DMA transfer for receptione */ -# define SPI_CR2_LDMATX (1 << 14) /* Bit 14: Last DMA transfer for transmission */ -#endif - -/* SPI status register */ - -#define SPI_SR_RXNE (1 << 0) /* Bit 0: Receive buffer not empty */ -#define SPI_SR_TXE (1 << 1) /* Bit 1: Transmit buffer empty */ -#define SPI_SR_CHSIDE (1 << 2) /* Bit 2: Channel side (i2s) */ -#define SPI_SR_UDR (1 << 3) /* Bit 3: Underrun flag (i2s) */ -#define SPI_SR_CRCERR (1 << 4) /* Bit 4: CRC error flag */ -#define SPI_SR_MODF (1 << 5) /* Bit 5: Mode fault */ -#define SPI_SR_OVR (1 << 6) /* Bit 6: Overrun flag */ -#define SPI_SR_BSY (1 << 7) /* Bit 7: Busy flag */ -#define SPI_SR_FRE (1 << 8) /* Bit 8: Frame format error */ -#ifdef HAVE_IP_SPI_V2 -# define SPI_SR_FRLVL_SHIFT (9) /* Bits 9-10: FIFO reception level */ -# define SPI_SR_FRLVL_MASK (3 << SPI_SR_FRLVL_SHIFT) -# define SPI_SR_FRLVL_EMPTY (0 << SPI_SR_FRLVL_SHIFT) /* FIFO empty */ -# define SPI_SR_FRLVL_QUARTER (1 << SPI_SR_FRLVL_SHIFT) /* 1/4 FIFO */ -# define SPI_SR_FRLVL_HALF (2 << SPI_SR_FRLVL_SHIFT) /* 1/2 FIFO */ -# define SPI_SR_FRLVL_FULL (3 << SPI_SR_FRLVL_SHIFT) /* FIFO full */ - -# define SPI_SR_FTLVL_SHIFT (11) /* Bits 11-12: FIFO transmission level */ -# define SPI_SR_FTLVL_MASK (3 << SPI_SR_FTLVL_SHIFT) -# define SPI_SR_FTLVL_EMPTY (0 << SPI_SR_FTLVL_SHIFT) /* FIFO empty */ -# define SPI_SR_FTLVL_QUARTER (1 << SPI_SR_FTLVL_SHIFT) /* 1/4 FIFO */ -# define SPI_SR_FTLVL_HALF (2 << SPI_SR_FTLVL_SHIFT) /* 1/2 FIFO */ -# define SPI_SR_FTLVL_FULL (3 << SPI_SR_FTLVL_SHIFT) /* FIFO full */ -#endif - -/* I2S configuration register */ - -#define SPI_I2SCFGR_CHLEN (1 << 0) /* Bit 0: Channel length (number of bits per audio channel) */ -#define SPI_I2SCFGR_DATLEN_SHIFT (1) /* Bit 1-2: Data length to be transferred */ -#define SPI_I2SCFGR_DATLEN_MASK (3 << SPI_I2SCFGR_DATLEN_SHIFT) -# define SPI_I2SCFGR_DATLEN_16BIT (0 << SPI_I2SCFGR_DATLEN_SHIFT) /* 00: 16-bit data length */ -# define SPI_I2SCFGR_DATLEN_24BIT (1 << SPI_I2SCFGR_DATLEN_SHIFT) /* 01: 24-bit data length */ -# define SPI_I2SCFGR_DATLEN_32BIT (2 << SPI_I2SCFGR_DATLEN_SHIFT) /* 10: 32-bit data length */ - -#define SPI_I2SCFGR_CKPOL (1 << 3) /* Bit 3: Steady state clock polarity */ -#define SPI_I2SCFGR_I2SSTD_SHIFT (4) /* Bit 4-5: I2S standard selection */ -#define SPI_I2SCFGR_I2SSTD_MASK (3 << SPI_I2SCFGR_I2SSTD_SHIFT) -# define SPI_I2SCFGR_I2SSTD_PHILLIPS (0 << SPI_I2SCFGR_I2SSTD_SHIFT) /* 00: I2S Phillips standard. */ -# define SPI_I2SCFGR_I2SSTD_MSB (1 << SPI_I2SCFGR_I2SSTD_SHIFT) /* 01: MSB justified standard (left justified) */ -# define SPI_I2SCFGR_I2SSTD_LSB (2 << SPI_I2SCFGR_I2SSTD_SHIFT) /* 10: LSB justified standard (right justified) */ -# define SPI_I2SCFGR_I2SSTD_PCM (3 << SPI_I2SCFGR_I2SSTD_SHIFT) /* 11: PCM standard */ - -#define SPI_I2SCFGR_PCMSYNC (1 << 7) /* Bit 7: PCM frame synchronization */ -#define SPI_I2SCFGR_I2SCFG_SHIFT (8) /* Bit 8-9: I2S configuration mode */ -#define SPI_I2SCFGR_I2SCFG_MASK (3 << SPI_I2SCFGR_I2SCFG_SHIFT) -# define SPI_I2SCFGR_I2SCFG_STX (0 << SPI_I2SCFGR_I2SCFG_SHIFT) /* 00: Slave - transmit */ -# define SPI_I2SCFGR_I2SCFG_SRX (1 << SPI_I2SCFGR_I2SCFG_SHIFT) /* 01: Slave - receive */ -# define SPI_I2SCFGR_I2SCFG_MTX (2 << SPI_I2SCFGR_I2SCFG_SHIFT) /* 10: Master - transmit */ -# define SPI_I2SCFGR_I2SCFG_MRX (3 << SPI_I2SCFGR_I2SCFG_SHIFT) /* 11: Master - receive */ - -#define SPI_I2SCFGR_I2SE (1 << 10) /* Bit 10: I2S Enable */ -#define SPI_I2SCFGR_I2SMOD (1 << 11) /* Bit 11: I2S mode selection */ - -/* I2S prescaler register */ - -#define SPI_I2SPR_I2SDIV_SHIFT (0) /* Bit 0-7: I2S Linear prescaler */ -#define SPI_I2SPR_I2SDIV_MASK (0xff << SPI_I2SPR_I2SDIV_SHIFT) -#define SPI_I2SPR_ODD (1 << 8) /* Bit 8: Odd factor for the prescaler */ -#define SPI_I2SPR_MCKOE (1 << 9) /* Bit 9: Master clock output enable */ - -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_SPI_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32_syscfg.h b/arch/arm/src/stm32f0l0g0/hardware/stm32_syscfg.h deleted file mode 100644 index f8966bbbcb362..0000000000000 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32_syscfg.h +++ /dev/null @@ -1,43 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32_syscfg.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_SYSCFG_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_SYSCFG_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include "chip.h" - -#if defined(CONFIG_ARCH_CHIP_STM32F0) -# include "hardware/stm32f0_syscfg.h" -#elif defined(CONFIG_ARCH_CHIP_STM32L0) -# include "hardware/stm32l0_syscfg.h" -#elif defined(CONFIG_ARCH_CHIP_STM32G0) -# include "hardware/stm32g0_syscfg.h" -#else -# error "Unsupported STM32 M0 SYSCFG" -#endif - -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_SYSCFG_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32_tim.h b/arch/arm/src/stm32f0l0g0/hardware/stm32_tim.h deleted file mode 100644 index 91fea96af14cf..0000000000000 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32_tim.h +++ /dev/null @@ -1,1151 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32_tim.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_TIM_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_TIM_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include "chip.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Timer Capabilities *******************************************************/ - -/* TIM2 is 16-bit on STM32L0, but 32-bit on STM32F0, STM32G0 and STM32C0 */ - -#if defined(CONFIG_ARCH_CHIP_STM32L0) -# define HAVE_TIM2_16BIT 1 -# undef HAVE_TIM2_32BIT -#elif defined(CONFIG_ARCH_CHIP_STM32G0) || defined(CONFIG_STM32F0L0G0_STM32F09X) -# define HAVE_TIM2_32BIT 1 -# undef HAVE_TIM2_16BIT -#else -# define HAVE_TIM2_32BIT 1 -# undef HAVE_TIM2_16BIT -#endif - -/* TODO Missing TIM2 definitions available on STM32G0x1 */ - -/* Register Offsets *********************************************************/ - -/* Basic Timers - TIM6 and TIM7 */ - -#define STM32_BTIM_CR1_OFFSET 0x0000 /* Control register 1 (16-bit) */ -#define STM32_BTIM_CR2_OFFSET 0x0004 /* Control register 2 (16-bit) */ -#define STM32_BTIM_DIER_OFFSET 0x000c /* DMA/Interrupt enable register (16-bit) */ -#define STM32_BTIM_SR_OFFSET 0x0010 /* Status register (16-bit) */ -#define STM32_BTIM_EGR_OFFSET 0x0014 /* Event generation register (16-bit) */ -#define STM32_BTIM_CNT_OFFSET 0x0024 /* Counter (16-bit) */ -#define STM32_BTIM_PSC_OFFSET 0x0028 /* Prescaler (16-bit) */ -#define STM32_BTIM_ARR_OFFSET 0x002c /* Auto-reload register (16-bit) */ - -/* 16-bit General-purpose Timers - TIM3 and TIM14-17 */ - -#define STM32_GTIM_CR1_OFFSET 0x0000 /* Control register 1 (16-bit) */ -#define STM32_GTIM_CR2_OFFSET 0x0004 /* Control register 2 (16-bit TIM3 and TIM15-17) */ -#define STM32_GTIM_SMCR_OFFSET 0x0008 /* Slave mode control register (32-bit TIM3 and TIM15 only) */ -#define STM32_GTIM_DIER_OFFSET 0x000c /* DMA/Interrupt enable register (16-bit) */ -#define STM32_GTIM_SR_OFFSET 0x0010 /* Status register (16-bit) */ -#define STM32_GTIM_EGR_OFFSET 0x0014 /* Event generation register (16-bit) */ -#define STM32_GTIM_CCMR1_OFFSET 0x0018 /* Capture/compare mode register 1 (32-bit) */ -#define STM32_GTIM_CCMR2_OFFSET 0x001c /* Capture/compare mode register 2 (32-bit TIM3 only) */ -#define STM32_GTIM_CCER_OFFSET 0x0020 /* Capture/compare enable register (16-bit) */ -#define STM32_GTIM_CNT_OFFSET 0x0024 /* Counter (16-bit) */ -#define STM32_GTIM_PSC_OFFSET 0x0028 /* Prescaler (16-bit) */ -#define STM32_GTIM_ARR_OFFSET 0x002c /* Auto-reload register (16-bit) */ -#define STM32_GTIM_RCR_OFFSET 0x0030 /* Repetition counter register (16-bit, TIM15-17) */ -#define STM32_GTIM_CCR1_OFFSET 0x0034 /* Capture/compare register 1 (16-bit) */ -#define STM32_GTIM_CCR2_OFFSET 0x0038 /* Capture/compare register 2 (16-bit TIM3 and TIM15 only) */ -#define STM32_GTIM_CCR3_OFFSET 0x003c /* Capture/compare register 3 (16-bit TIM3 only) */ -#define STM32_GTIM_CCR4_OFFSET 0x0040 /* Capture/compare register 4 (16-bit TIM3 only) */ -#define STM32_GTIM_BDTR_OFFSET 0x0044 /* Break and dead-time register (32-bit TIM15-17) */ -#define STM32_GTIM_DCR_OFFSET 0x0048 /* DMA control register (16-bit TIM3 and TIM15-17) */ -#define STM32_GTIM_DMAR_OFFSET 0x004c /* DMA address for burst mode (16-bit TIM3 and TIM15-17) */ -#define STM32_GTIM_AF1_OFFSET 0x0060 /* Alternate function option register 1 (16-bit TIM15-17 or 32-bit TIM3) */ -#define STM32_GTIM_TISEL_OFFSET 0x0068 /* Timer input selection register (16-bit TIM14-17 or 32-bit TIM3) */ - -/* Advanced Timers - TIM1 */ - -#define STM32_ATIM_CR1_OFFSET 0x0000 /* Control register 1 (16-bit) */ -#define STM32_ATIM_CR2_OFFSET 0x0004 /* Control register 2 (16-bit*) */ -#define STM32_ATIM_SMCR_OFFSET 0x0008 /* Slave mode control register (16-bit) */ -#define STM32_ATIM_DIER_OFFSET 0x000c /* DMA/Interrupt enable register (16-bit) */ -#define STM32_ATIM_SR_OFFSET 0x0010 /* Status register (16-bit*) */ -#define STM32_ATIM_EGR_OFFSET 0x0014 /* Event generation register (16-bit) */ -#define STM32_ATIM_CCMR1_OFFSET 0x0018 /* Capture/compare mode register 1 (16-bit*) */ -#define STM32_ATIM_CCMR2_OFFSET 0x001c /* Capture/compare mode register 2 (16-bit*) */ -#define STM32_ATIM_CCER_OFFSET 0x0020 /* Capture/compare enable register (16-bit*) */ -#define STM32_ATIM_CNT_OFFSET 0x0024 /* Counter (16-bit) */ -#define STM32_ATIM_PSC_OFFSET 0x0028 /* Prescaler (16-bit) */ -#define STM32_ATIM_ARR_OFFSET 0x002c /* Auto-reload register (16-bit) */ -#define STM32_ATIM_RCR_OFFSET 0x0030 /* Repetition counter register (16-bit) */ -#define STM32_ATIM_CCR1_OFFSET 0x0034 /* Capture/compare register 1 (16-bit) */ -#define STM32_ATIM_CCR2_OFFSET 0x0038 /* Capture/compare register 2 (16-bit) */ -#define STM32_ATIM_CCR3_OFFSET 0x003c /* Capture/compare register 3 (16-bit) */ -#define STM32_ATIM_CCR4_OFFSET 0x0040 /* Capture/compare register 4 (16-bit) */ -#define STM32_ATIM_BDTR_OFFSET 0x0044 /* Break and dead-time register (16-bit*) */ -#define STM32_ATIM_DCR_OFFSET 0x0048 /* DMA control register (16-bit) */ -#define STM32_ATIM_DMAR_OFFSET 0x004c /* DMA address for burst mode (16-bit) */ -#define STM32_ATIM_OR1_OFFSET 0x0050 /* Timer option register 1 (16-bit) */ -#define STM32_ATIM_CCMR3_OFFSET 0x0054 /* Capture/compare mode register 3 (32-bit) */ -#define STM32_ATIM_CCR5_OFFSET 0x0058 /* Capture/compare register 4 (16-bit) */ -#define STM32_ATIM_CCR6_OFFSET 0x005c /* Capture/compare register 4 (32-bit) */ -#define STM32_ATIM_AF1_OFFSET 0x0060 /* Alternate function option register 1 (32-bit) */ -#define STM32_ATIM_AF2_OFFSET 0x0064 /* Alternate function option register 2 (32-bit) */ -#define STM32_ATIM_TISEL_OFFSET 0x0068 /* Timer input selection register (32-bit) */ - -/* Register Addresses *******************************************************/ - -/* Advanced Timers - TIM1 */ - -#define STM32_TIM1_CR1 (STM32_TIM1_BASE+STM32_ATIM_CR1_OFFSET) -#define STM32_TIM1_CR2 (STM32_TIM1_BASE+STM32_ATIM_CR2_OFFSET) -#define STM32_TIM1_SMCR (STM32_TIM1_BASE+STM32_ATIM_SMCR_OFFSET) -#define STM32_TIM1_DIER (STM32_TIM1_BASE+STM32_ATIM_DIER_OFFSET) -#define STM32_TIM1_SR (STM32_TIM1_BASE+STM32_ATIM_SR_OFFSET) -#define STM32_TIM1_EGR (STM32_TIM1_BASE+STM32_ATIM_EGR_OFFSET) -#define STM32_TIM1_CCMR1 (STM32_TIM1_BASE+STM32_ATIM_CCMR1_OFFSET) -#define STM32_TIM1_CCMR2 (STM32_TIM1_BASE+STM32_ATIM_CCMR2_OFFSET) -#define STM32_TIM1_CCER (STM32_TIM1_BASE+STM32_ATIM_CCER_OFFSET) -#define STM32_TIM1_CNT (STM32_TIM1_BASE+STM32_ATIM_CNT_OFFSET) -#define STM32_TIM1_PSC (STM32_TIM1_BASE+STM32_ATIM_PSC_OFFSET) -#define STM32_TIM1_ARR (STM32_TIM1_BASE+STM32_ATIM_ARR_OFFSET) -#define STM32_TIM1_RCR (STM32_TIM1_BASE+STM32_ATIM_RCR_OFFSET) -#define STM32_TIM1_CCR1 (STM32_TIM1_BASE+STM32_ATIM_CCR1_OFFSET) -#define STM32_TIM1_CCR2 (STM32_TIM1_BASE+STM32_ATIM_CCR2_OFFSET) -#define STM32_TIM1_CCR3 (STM32_TIM1_BASE+STM32_ATIM_CCR3_OFFSET) -#define STM32_TIM1_CCR4 (STM32_TIM1_BASE+STM32_ATIM_CCR4_OFFSET) -#define STM32_TIM1_BDTR (STM32_TIM1_BASE+STM32_ATIM_BDTR_OFFSET) -#define STM32_TIM1_DCR (STM32_TIM1_BASE+STM32_ATIM_DCR_OFFSET) -#define STM32_TIM1_DMAR (STM32_TIM1_BASE+STM32_ATIM_DMAR_OFFSET) -#define STM32_TIM1_OR1 (STM32_TIM1_BASE+STM32_ATIM_OR1_OFFSET) -#define STM32_TIM1_CCMR3 (STM32_TIM1_BASE+STM32_ATIM_CCMR3_OFFSET) -#define STM32_TIM1_CCR5 (STM32_TIM1_BASE+STM32_ATIM_CCR5_OFFSET) -#define STM32_TIM1_CCR6 (STM32_TIM1_BASE+STM32_ATIM_CCR6_OFFSET) -#define STM32_TIM1_AF1 (STM32_TIM1_BASE+STM32_ATIM_AF1_OFFSET) -#define STM32_TIM1_AF2 (STM32_TIM1_BASE+STM32_ATIM_AF2_OFFSET) -#define STM32_TIM1_TISEL (STM32_TIM1_BASE+STM32_ATIM_TISEL_OFFSET) - -/* 16-bit General Timers TIM3 and TIM14-17 */ - -#define STM32_TIM3_CR1 (STM32_TIM3_BASE+STM32_GTIM_CR1_OFFSET) -#define STM32_TIM3_CR2 (STM32_TIM3_BASE+STM32_GTIM_CR2_OFFSET) -#define STM32_TIM3_SMCR (STM32_TIM3_BASE+STM32_GTIM_SMCR_OFFSET) -#define STM32_TIM3_DIER (STM32_TIM3_BASE+STM32_GTIM_DIER_OFFSET) -#define STM32_TIM3_SR (STM32_TIM3_BASE+STM32_GTIM_SR_OFFSET) -#define STM32_TIM3_EGR (STM32_TIM3_BASE+STM32_GTIM_EGR_OFFSET) -#define STM32_TIM3_CCMR1 (STM32_TIM3_BASE+STM32_GTIM_CCMR1_OFFSET) -#define STM32_TIM3_CCMR2 (STM32_TIM3_BASE+STM32_GTIM_CCMR2_OFFSET) -#define STM32_TIM3_CCER (STM32_TIM3_BASE+STM32_GTIM_CCER_OFFSET) -#define STM32_TIM3_CNT (STM32_TIM3_BASE+STM32_GTIM_CNT_OFFSET) -#define STM32_TIM3_PSC (STM32_TIM3_BASE+STM32_GTIM_PSC_OFFSET) -#define STM32_TIM3_ARR (STM32_TIM3_BASE+STM32_GTIM_ARR_OFFSET) -#define STM32_TIM3_CCR1 (STM32_TIM3_BASE+STM32_GTIM_CCR1_OFFSET) -#define STM32_TIM3_CCR2 (STM32_TIM3_BASE+STM32_GTIM_CCR2_OFFSET) -#define STM32_TIM3_CCR3 (STM32_TIM3_BASE+STM32_GTIM_CCR3_OFFSET) -#define STM32_TIM3_CCR4 (STM32_TIM3_BASE+STM32_GTIM_CCR4_OFFSET) -#define STM32_TIM3_DCR (STM32_TIM3_BASE+STM32_GTIM_DCR_OFFSET) -#define STM32_TIM3_DMAR (STM32_TIM3_BASE+STM32_GTIM_DMAR_OFFSET) -#define STM32_TIM3_AF1 (STM32_TIM3_BASE+STM32_GTIM_AF1_OFFSET) -#define STM32_TIM3_TISEL (STM32_TIM3_BASE+STM32_GTIM_TISEL_OFFSET) - -#define STM32_TIM14_CR1 (STM32_TIM14_BASE+STM32_GTIM_CR1_OFFSET) -#define STM32_TIM14_DIER (STM32_TIM14_BASE+STM32_GTIM_DIER_OFFSET) -#define STM32_TIM14_SR (STM32_TIM14_BASE+STM32_GTIM_SR_OFFSET) -#define STM32_TIM14_EGR (STM32_TIM14_BASE+STM32_GTIM_EGR_OFFSET) -#define STM32_TIM14_CCMR1 (STM32_TIM14_BASE+STM32_GTIM_CCMR1_OFFSET) -#define STM32_TIM14_CCER (STM32_TIM14_BASE+STM32_GTIM_CCER_OFFSET) -#define STM32_TIM14_CNT (STM32_TIM14_BASE+STM32_GTIM_CNT_OFFSET) -#define STM32_TIM14_PSC (STM32_TIM14_BASE+STM32_GTIM_PSC_OFFSET) -#define STM32_TIM14_ARR (STM32_TIM14_BASE+STM32_GTIM_ARR_OFFSET) -#define STM32_TIM14_CCR1 (STM32_TIM14_BASE+STM32_GTIM_CCR1_OFFSET) -#define STM32_TIM14_TISEL (STM32_TIM14_BASE+STM32_GTIM_TISEL_OFFSET) - -#define STM32_TIM15_CR1 (STM32_TIM15_BASE+STM32_GTIM_CR1_OFFSET) -#define STM32_TIM15_CR2 (STM32_TIM15_BASE+STM32_GTIM_CR2_OFFSET) -#define STM32_TIM15_SMCR (STM32_TIM15_BASE+STM32_GTIM_SMCR_OFFSET) -#define STM32_TIM15_DIER (STM32_TIM15_BASE+STM32_GTIM_DIER_OFFSET) -#define STM32_TIM15_SR (STM32_TIM15_BASE+STM32_GTIM_SR_OFFSET) -#define STM32_TIM15_EGR (STM32_TIM15_BASE+STM32_GTIM_EGR_OFFSET) -#define STM32_TIM15_CCMR1 (STM32_TIM15_BASE+STM32_GTIM_CCMR1_OFFSET) -#define STM32_TIM15_CCER (STM32_TIM15_BASE+STM32_GTIM_CCER_OFFSET) -#define STM32_TIM15_CNT (STM32_TIM15_BASE+STM32_GTIM_CNT_OFFSET) -#define STM32_TIM15_PSC (STM32_TIM15_BASE+STM32_GTIM_PSC_OFFSET) -#define STM32_TIM15_ARR (STM32_TIM15_BASE+STM32_GTIM_ARR_OFFSET) -#define STM32_TIM15_RCR (STM32_TIM15_BASE+STM32_GTIM_RCR_OFFSET) -#define STM32_TIM15_CCR1 (STM32_TIM15_BASE+STM32_GTIM_CCR1_OFFSET) -#define STM32_TIM15_CCR2 (STM32_TIM15_BASE+STM32_GTIM_CCR2_OFFSET) -#define STM32_TIM15_BDTR (STM32_TIM15_BASE+STM32_GTIM_BDTR_OFFSET) -#define STM32_TIM15_DCR (STM32_TIM15_BASE+STM32_GTIM_DCR_OFFSET) -#define STM32_TIM15_DMAR (STM32_TIM15_BASE+STM32_GTIM_DMAR_OFFSET) -#define STM32_TIM15_AF1 (STM32_TIM15_BASE+STM32_GTIM_AF1_OFFSET) -#define STM32_TIM15_TISEL (STM32_TIM15_BASE+STM32_GTIM_TISEL_OFFSET) - -#define STM32_TIM16_CR1 (STM32_TIM16_BASE+STM32_GTIM_CR1_OFFSET) -#define STM32_TIM16_CR2 (STM32_TIM16_BASE+STM32_GTIM_CR2_OFFSET) -#define STM32_TIM16_DIER (STM32_TIM16_BASE+STM32_GTIM_DIER_OFFSET) -#define STM32_TIM16_SR (STM32_TIM16_BASE+STM32_GTIM_SR_OFFSET) -#define STM32_TIM16_EGR (STM32_TIM16_BASE+STM32_GTIM_EGR_OFFSET) -#define STM32_TIM16_CCMR1 (STM32_TIM16_BASE+STM32_GTIM_CCMR1_OFFSET) -#define STM32_TIM16_CCER (STM32_TIM16_BASE+STM32_GTIM_CCER_OFFSET) -#define STM32_TIM16_CNT (STM32_TIM16_BASE+STM32_GTIM_CNT_OFFSET) -#define STM32_TIM16_PSC (STM32_TIM16_BASE+STM32_GTIM_PSC_OFFSET) -#define STM32_TIM16_ARR (STM32_TIM16_BASE+STM32_GTIM_ARR_OFFSET) -#define STM32_TIM16_RCR (STM32_TIM16_BASE+STM32_GTIM_RCR_OFFSET) -#define STM32_TIM16_CCR1 (STM32_TIM16_BASE+STM32_GTIM_CCR1_OFFSET) -#define STM32_TIM16_BDTR (STM32_TIM16_BASE+STM32_GTIM_BDTR_OFFSET) -#define STM32_TIM16_DCR (STM32_TIM16_BASE+STM32_GTIM_DCR_OFFSET) -#define STM32_TIM16_DMAR (STM32_TIM16_BASE+STM32_GTIM_DMAR_OFFSET) -#define STM32_TIM16_AF1 (STM32_TIM16_BASE+STM32_GTIM_AF1_OFFSET) -#define STM32_TIM16_TISEL (STM32_TIM16_BASE+STM32_GTIM_TISEL_OFFSET) - -#define STM32_TIM17_CR1 (STM32_TIM17_BASE+STM32_GTIM_CR1_OFFSET) -#define STM32_TIM17_CR2 (STM32_TIM17_BASE+STM32_GTIM_CR2_OFFSET) -#define STM32_TIM17_DIER (STM32_TIM17_BASE+STM32_GTIM_DIER_OFFSET) -#define STM32_TIM17_SR (STM32_TIM17_BASE+STM32_GTIM_SR_OFFSET) -#define STM32_TIM17_EGR (STM32_TIM17_BASE+STM32_GTIM_EGR_OFFSET) -#define STM32_TIM17_CCMR1 (STM32_TIM17_BASE+STM32_GTIM_CCMR1_OFFSET) -#define STM32_TIM17_CCER (STM32_TIM17_BASE+STM32_GTIM_CCER_OFFSET) -#define STM32_TIM17_CNT (STM32_TIM17_BASE+STM32_GTIM_CNT_OFFSET) -#define STM32_TIM17_PSC (STM32_TIM17_BASE+STM32_GTIM_PSC_OFFSET) -#define STM32_TIM17_ARR (STM32_TIM17_BASE+STM32_GTIM_ARR_OFFSET) -#define STM32_TIM17_RCR (STM32_TIM17_BASE+STM32_GTIM_RCR_OFFSET) -#define STM32_TIM17_CCR1 (STM32_TIM17_BASE+STM32_GTIM_CCR1_OFFSET) -#define STM32_TIM17_BDTR (STM32_TIM17_BASE+STM32_GTIM_BDTR_OFFSET) -#define STM32_TIM17_DCR (STM32_TIM17_BASE+STM32_GTIM_DCR_OFFSET) -#define STM32_TIM17_DMAR (STM32_TIM17_BASE+STM32_GTIM_DMAR_OFFSET) -#define STM32_TIM17_AF1 (STM32_TIM17_BASE+STM32_GTIM_AF1_OFFSET) -#define STM32_TIM17_TISEL (STM32_TIM17_BASE+STM32_GTIM_TISEL_OFFSET) - -/* Basic Timers - TIM6 and TIM7 */ - -#define STM32_TIM6_CR1 (STM32_TIM6_BASE+STM32_BTIM_CR1_OFFSET) -#define STM32_TIM6_CR2 (STM32_TIM6_BASE+STM32_BTIM_CR2_OFFSET) -#define STM32_TIM6_DIER (STM32_TIM6_BASE+STM32_BTIM_DIER_OFFSET) -#define STM32_TIM6_SR (STM32_TIM6_BASE+STM32_BTIM_SR_OFFSET) -#define STM32_TIM6_EGR (STM32_TIM6_BASE+STM32_BTIM_EGR_OFFSET) -#define STM32_TIM6_CNT (STM32_TIM6_BASE+STM32_BTIM_CNT_OFFSET) -#define STM32_TIM6_PSC (STM32_TIM6_BASE+STM32_BTIM_PSC_OFFSET) -#define STM32_TIM6_ARR (STM32_TIM6_BASE+STM32_BTIM_ARR_OFFSET) - -#define STM32_TIM7_CR1 (STM32_TIM7_BASE+STM32_BTIM_CR1_OFFSET) -#define STM32_TIM7_CR2 (STM32_TIM7_BASE+STM32_BTIM_CR2_OFFSET) -#define STM32_TIM7_DIER (STM32_TIM7_BASE+STM32_BTIM_DIER_OFFSET) -#define STM32_TIM7_SR (STM32_TIM7_BASE+STM32_BTIM_SR_OFFSET) -#define STM32_TIM7_EGR (STM32_TIM7_BASE+STM32_BTIM_EGR_OFFSET) -#define STM32_TIM7_CNT (STM32_TIM7_BASE+STM32_BTIM_CNT_OFFSET) -#define STM32_TIM7_PSC (STM32_TIM7_BASE+STM32_BTIM_PSC_OFFSET) -#define STM32_TIM7_ARR (STM32_TIM7_BASE+STM32_BTIM_ARR_OFFSET) - -/* Register Bitfield Definitions ********************************************/ - -/* Control register 1 */ - -#define ATIM_CR1_CEN (1 << 0) /* Bit 0: Counter enable */ -#define ATIM_CR1_UDIS (1 << 1) /* Bit 1: Update disable */ -#define ATIM_CR1_URS (1 << 2) /* Bit 2: Update request source */ -#define ATIM_CR1_OPM (1 << 3) /* Bit 3: One pulse mode */ -#define ATIM_CR1_DIR (1 << 4) /* Bit 4: Direction */ -#define ATIM_CR1_CMS_SHIFT (5) /* Bits 6-5: Center-aligned mode selection */ -#define ATIM_CR1_CMS_MASK (3 << ATIM_CR1_CMS_SHIFT) -# define ATIM_CR1_EDGE (0 << ATIM_CR1_CMS_SHIFT) /* 00: Edge-aligned mode */ -# define ATIM_CR1_CENTER1 (1 << ATIM_CR1_CMS_SHIFT) /* 01: Center-aligned mode 1 */ -# define ATIM_CR1_CENTER2 (2 << ATIM_CR1_CMS_SHIFT) /* 10: Center-aligned mode 2 */ -# define ATIM_CR1_CENTER3 (3 << ATIM_CR1_CMS_SHIFT) /* 11: Center-aligned mode 3 */ - -#define ATIM_CR1_ARPE (1 << 7) /* Bit 7: Auto-reload preload enable */ -#define ATIM_CR1_CKD_SHIFT (8) /* Bits 9-8: Clock division */ -#define ATIM_CR1_CKD_MASK (3 << ATIM_CR1_CKD_SHIFT) -# define ATIM_CR1_TCKINT (0 << ATIM_CR1_CKD_SHIFT) /* 00: tDTS=tCK_INT */ -# define ATIM_CR1_2TCKINT (1 << ATIM_CR1_CKD_SHIFT) /* 01: tDTS=2*tCK_INT */ -# define ATIM_CR1_4TCKINT (2 << ATIM_CR1_CKD_SHIFT) /* 10: tDTS=4*tCK_INT */ - -#define ATIM_CR1_UIFREMAP (1 << 11) /* Bit 11: UIF status bit remapping */ - -/* Control register 2 */ - -#define ATIM_CR2_CCPC (1 << 0) /* Bit 0: Capture/Compare Preloaded Control */ -#define ATIM_CR2_CCUS (1 << 2) /* Bit 2: Capture/Compare Control Update Selection */ -#define ATIM_CR2_CCDS (1 << 3) /* Bit 3: Capture/Compare DMA Selection */ -#define ATIM_CR2_MMS_SHIFT (4) /* Bits 6-4: Master Mode Selection */ -#define ATIM_CR2_MMS_MASK (7 << ATIM_CR2_MMS_SHIFT) -# define ATIM_CR2_MMS_RESET (0 << ATIM_CR2_MMS_SHIFT) /* 000: Reset - TIMx_EGR UG bit is TRGO */ -# define ATIM_CR2_MMS_ENABLE (1 << ATIM_CR2_MMS_SHIFT) /* 001: Enable - CNT_EN is TRGO */ -# define ATIM_CR2_MMS_UPDATE (2 << ATIM_CR2_MMS_SHIFT) /* 010: Update event is TRGO */ -# define ATIM_CR2_MMS_COMPP (3 << ATIM_CR2_MMS_SHIFT) /* 010: Compare Pulse - CC1IF flag */ -# define ATIM_CR2_MMS_OC1REF (4 << ATIM_CR2_MMS_SHIFT) /* 100: Compare OC1REF is TRGO */ -# define ATIM_CR2_MMS_OC2REF (5 << ATIM_CR2_MMS_SHIFT) /* 101: Compare OC2REF is TRGO */ -# define ATIM_CR2_MMS_OC3REF (6 << ATIM_CR2_MMS_SHIFT) /* 110: Compare OC3REF is TRGO */ -# define ATIM_CR2_MMS_OC4REF (7 << ATIM_CR2_MMS_SHIFT) /* 111: Compare OC4REF is TRGO */ - -#define ATIM_CR2_TI1S (1 << 7) /* Bit 7: TI1 Selection */ -#define ATIM_CR2_OIS1 (1 << 8) /* Bit 8: Output Idle state 1 (OC1 output) */ -#define ATIM_CR2_OIS1N (1 << 9) /* Bit 9: Output Idle state 1 (OC1N output) */ -#define ATIM_CR2_OIS2 (1 << 10) /* Bit 10: Output Idle state 2 (OC2 output) */ -#define ATIM_CR2_OIS2N (1 << 11) /* Bit 11: Output Idle state 2 (OC2N output) */ -#define ATIM_CR2_OIS3 (1 << 12) /* Bit 12: Output Idle state 3 (OC3 output) */ -#define ATIM_CR2_OIS3N (1 << 13) /* Bit 13: Output Idle state 3 (OC3N output) */ -#define ATIM_CR2_OIS4 (1 << 14) /* Bit 14: Output Idle state 4 (OC4 output) */ -#define ATIM_CR2_OIS5 (1 << 16) /* Bit 16: Output Idle state 5 (OC5 output) */ -#define ATIM_CR2_OIS6 (1 << 18) /* Bit 18: Output Idle state 6 (OC6 output) */ -#define ATIM_CR2_MMS2_SHIFT (20) /* Bits 20-23: Master Mode Selection 2 */ -#define ATIM_CR2_MMS2_MASK (15 << ATIM_CR2_MMS2_SHIFT) -# define ATIM_CR2_MMS2_RESET (0 << ATIM_CR2_MMS2_SHIFT) /* 0000: Reset - TIMx_EGR UG bit is TRG9 */ -# define ATIM_CR2_MMS2_ENABLE (1 << ATIM_CR2_MMS2_SHIFT) /* 0001: Enable - CNT_EN is TRGO2 */ -# define ATIM_CR2_MMS2_UPDATE (2 << ATIM_CR2_MMS2_SHIFT) /* 0010: Update event is TRGH0*/ -# define ATIM_CR2_MMS2_COMPP (3 << ATIM_CR2_MMS2_SHIFT) /* 0010: Compare Pulse - CC1IF flag */ -# define ATIM_CR2_MMS2_OC1REF (4 << ATIM_CR2_MMS2_SHIFT) /* 0100: Compare OC1REF is TRGO2 */ -# define ATIM_CR2_MMS2_OC2REF (5 << ATIM_CR2_MMS2_SHIFT) /* 0101: Compare OC2REF is TRGO2 */ -# define ATIM_CR2_MMS2_OC3REF (6 << ATIM_CR2_MMS2_SHIFT) /* 0110: Compare OC3REF is TRGO2 */ -# define ATIM_CR2_MMS2_OC4REF (7 << ATIM_CR2_MMS2_SHIFT) /* 0111: Compare OC4REF is TRGO2 */ -# define ATIM_CR2_MMS2_OC5REF (8 << ATIM_CR2_MMS2_SHIFT) /* 1000: Compare OC5REF is TRGO2 */ -# define ATIM_CR2_MMS2_OC6REF (9 << ATIM_CR2_MMS2_SHIFT) /* 1001: Compare OC6REF is TRGO2 */ -# define ATIM_CR2_MMS2_CMPOC4 (10 << ATIM_CR2_MMS2_SHIFT) /* 1010: Compare pulse - OC4REF edge is TRGO2 */ -# define ATIM_CR2_MMS2_CMPOC6 (11 << ATIM_CR2_MMS2_SHIFT) /* 1011: Compare pulse - OC6REF edge is TRGO2 */ -# define ATIM_CR2_MMS2_CMPOC4R6R (12 << ATIM_CR2_MMS2_SHIFT) /* 1100: Compare pulse - OC4REF/OC6REF rising */ -# define ATIM_CR2_MMS2_CMPOC4R6F (13 << ATIM_CR2_MMS2_SHIFT) /* 1101: Compare pulse - OC4REF rising/OC6REF falling */ -# define ATIM_CR2_MMS2_CMPOC5R6R (14 << ATIM_CR2_MMS2_SHIFT) /* 1110: Compare pulse - OC5REF/OC6REF rising */ -# define ATIM_CR2_MMS2_CMPOC5R6F (15 << ATIM_CR2_MMS2_SHIFT) /* 1111: Compare pulse - OC5REF rising/OC6REF falling */ - -/* Slave mode control register */ - -#define ATIM_SMCR_SMS_SHIFT (0) /* Bits 0-2: Slave mode selection */ -#define ATIM_SMCR_SMS_MASK (7 << ATIM_SMCR_SMS_SHIFT) -# define ATIM_SMCR_DISAB (0 << ATIM_SMCR_SMS_SHIFT) /* 000: Slave mode disabled */ -# define ATIM_SMCR_ENCMD1 (1 << ATIM_SMCR_SMS_SHIFT) /* 001: Encoder mode 1 */ -# define ATIM_SMCR_ENCMD2 (2 << ATIM_SMCR_SMS_SHIFT) /* 010: Encoder mode 2 */ -# define ATIM_SMCR_ENCMD3 (3 << ATIM_SMCR_SMS_SHIFT) /* 011: Encoder mode 3 */ -# define ATIM_SMCR_RESET (4 << ATIM_SMCR_SMS_SHIFT) /* 100: Reset Mode */ -# define ATIM_SMCR_GATED (5 << ATIM_SMCR_SMS_SHIFT) /* 101: Gated Mode */ -# define ATIM_SMCR_TRIGGER (6 << ATIM_SMCR_SMS_SHIFT) /* 110: Trigger Mode */ -# define ATIM_SMCR_EXTCLK1 (7 << ATIM_SMCR_SMS_SHIFT) /* 111: External Clock Mode 1 */ - -#define ATIM_SMCR_OCCS (1 << 3) /* Bit 3: OCREF clear selection */ -#define ATIM_SMCR_TS_SHIFT (4) /* Bits 4-6: Trigger selection */ -#define ATIM_SMCR_TS_MASK (7 << ATIM_SMCR_TS_SHIFT) -# define ATIM_SMCR_ITR0 (0 << ATIM_SMCR_TS_SHIFT) /* 000: Internal trigger 0 (ITR0) */ -# define ATIM_SMCR_ITR1 (1 << ATIM_SMCR_TS_SHIFT) /* 001: Internal trigger 1 (ITR1) */ -# define ATIM_SMCR_ITR2 (2 << ATIM_SMCR_TS_SHIFT) /* 010: Internal trigger 2 (ITR2) */ -# define ATIM_SMCR_ITR3 (3 << ATIM_SMCR_TS_SHIFT) /* 011: Internal trigger 3 (ITR3) */ -# define ATIM_SMCR_T1FED (4 << ATIM_SMCR_TS_SHIFT) /* 100: TI1 Edge Detector (TI1F_ED) */ -# define ATIM_SMCR_TI1FP1 (5 << ATIM_SMCR_TS_SHIFT) /* 101: Filtered Timer Input 1 (TI1FP1) */ -# define ATIM_SMCR_T12FP2 (6 << ATIM_SMCR_TS_SHIFT) /* 110: Filtered Timer Input 2 (TI2FP2) */ -# define ATIM_SMCR_ETRF (7 << ATIM_SMCR_TS_SHIFT) /* 111: External Trigger input (ETRF) */ - -#define ATIM_SMCR_MSM (1 << 7) /* Bit 7: Master/slave mode */ -#define ATIM_SMCR_ETF_SHIFT (8) /* Bits 8-11: External trigger filter */ -#define ATIM_SMCR_ETF_MASK (0x0f << ATIM_SMCR_ETF_SHIFT) -# define ATIM_SMCR_NOFILT (0 << ATIM_SMCR_ETF_SHIFT) /* 0000: No filter, sampling is done at fDTS */ -# define ATIM_SMCR_FCKINT2 (1 << ATIM_SMCR_ETF_SHIFT) /* 0001: fSAMPLING=fCK_INT, N=2 */ -# define ATIM_SMCR_FCKINT4 (2 << ATIM_SMCR_ETF_SHIFT) /* 0010: fSAMPLING=fCK_INT, N=4 */ -# define ATIM_SMCR_FCKINT8 (3 << ATIM_SMCR_ETF_SHIFT) /* 0011: fSAMPLING=fCK_INT, N=8 */ -# define ATIM_SMCR_FDTSd26 (4 << ATIM_SMCR_ETF_SHIFT) /* 0100: fSAMPLING=fDTS/2, N=6 */ -# define ATIM_SMCR_FDTSd28 (5 << ATIM_SMCR_ETF_SHIFT) /* 0101: fSAMPLING=fDTS/2, N=8 */ -# define ATIM_SMCR_FDTSd46 (6 << ATIM_SMCR_ETF_SHIFT) /* 0110: fSAMPLING=fDTS/4, N=6 */ -# define ATIM_SMCR_FDTSd48 (7 << ATIM_SMCR_ETF_SHIFT) /* 0111: fSAMPLING=fDTS/4, N=8 */ -# define ATIM_SMCR_FDTSd86 (8 << ATIM_SMCR_ETF_SHIFT) /* 1000: fSAMPLING=fDTS/8, N=6 */ -# define ATIM_SMCR_FDTSd88 (9 << ATIM_SMCR_ETF_SHIFT) /* 1001: fSAMPLING=fDTS/8, N=8 */ -# define ATIM_SMCR_FDTSd165 (10 << ATIM_SMCR_ETF_SHIFT) /* 1010: fSAMPLING=fDTS/16, N=5 */ -# define ATIM_SMCR_FDTSd166 (11 << ATIM_SMCR_ETF_SHIFT) /* 1011: fSAMPLING=fDTS/16, N=6 */ -# define ATIM_SMCR_FDTSd168 (12 << ATIM_SMCR_ETF_SHIFT) /* 1100: fSAMPLING=fDTS/16, N=8 */ -# define ATIM_SMCR_FDTSd325 (13 << ATIM_SMCR_ETF_SHIFT) /* 1101: fSAMPLING=fDTS/32, N=5 */ -# define ATIM_SMCR_FDTSd326 (14 << ATIM_SMCR_ETF_SHIFT) /* 1110: fSAMPLING=fDTS/32, N=6 */ -# define ATIM_SMCR_FDTSd328 (15 << ATIM_SMCR_ETF_SHIFT) /* 1111: fSAMPLING=fDTS/32, N=8 */ - -#define ATIM_SMCR_ETPS_SHIFT (12) /* Bits 12-13: External trigger prescaler */ -#define ATIM_SMCR_ETPS_MASK (3 << ATIM_SMCR_ETPS_SHIFT) -# define ATIM_SMCR_PSCOFF (0 << ATIM_SMCR_ETPS_SHIFT) /* 00: Prescaler OFF */ -# define ATIM_SMCR_ETRPd2 (1 << ATIM_SMCR_ETPS_SHIFT) /* 01: ETRP frequency divided by 2 */ -# define ATIM_SMCR_ETRPd4 (2 << ATIM_SMCR_ETPS_SHIFT) /* 10: ETRP frequency divided by 4 */ -# define ATIM_SMCR_ETRPd8 (3 << ATIM_SMCR_ETPS_SHIFT) /* 11: ETRP frequency divided by 8 */ - -#define ATIM_SMCR_ECE (1 << 14) /* Bit 14: External clock enable */ -#define ATIM_SMCR_ETP (1 << 15) /* Bit 15: External trigger polarity */ -#define ATIM_SMCR_SMS (1 << 16) /* Bit 16: Slave mode selection - bit 3 */ - -/* TS[3:4] (bits 20-21) are set to 00 for each valid option */ - -/* DMA/Interrupt enable register */ - -#define ATIM_DIER_UIE (1 << 0) /* Bit 0: Update interrupt enable */ -#define ATIM_DIER_CC1IE (1 << 1) /* Bit 1: Capture/Compare 1 interrupt enable */ -#define ATIM_DIER_CC2IE (1 << 2) /* Bit 2: Capture/Compare 2 interrupt enable */ -#define ATIM_DIER_CC3IE (1 << 3) /* Bit 3: Capture/Compare 3 interrupt enable */ -#define ATIM_DIER_CC4IE (1 << 4) /* Bit 4: Capture/Compare 4 interrupt enable */ -#define ATIM_DIER_COMIE (1 << 5) /* Bit 5: COM interrupt enable */ -#define ATIM_DIER_TIE (1 << 6) /* Bit 6: Trigger interrupt enable */ -#define ATIM_DIER_BIE (1 << 7) /* Bit 7: Break interrupt enable */ -#define ATIM_DIER_UDE (1 << 8) /* Bit 8: Update DMA request enable */ -#define ATIM_DIER_CC1DE (1 << 9) /* Bit 9: Capture/Compare 1 DMA request enable */ -#define ATIM_DIER_CC2DE (1 << 10) /* Bit 10: Capture/Compare 2 DMA request enable */ -#define ATIM_DIER_CC3DE (1 << 11) /* Bit 11: Capture/Compare 3 DMA request enable */ -#define ATIM_DIER_CC4DE (1 << 12) /* Bit 12: Capture/Compare 4 DMA request enable */ -#define ATIM_DIER_COMDE (1 << 13) /* Bit 13: COM DMA request enable */ -#define ATIM_DIER_TDE (1 << 14) /* Bit 14: Trigger DMA request enable */ - -/* Status register */ - -#define ATIM_SR_UIF (1 << 0) /* Bit 0: Update interrupt Flag */ -#define ATIM_SR_CC1IF (1 << 1) /* Bit 1: Capture/Compare 1 interrupt Flag */ -#define ATIM_SR_CC2IF (1 << 2) /* Bit 2: Capture/Compare 2 interrupt Flag */ -#define ATIM_SR_CC3IF (1 << 3) /* Bit 3: Capture/Compare 3 interrupt Flag */ -#define ATIM_SR_CC4IF (1 << 4) /* Bit 4: Capture/Compare 4 interrupt Flag */ -#define ATIM_SR_COMIF (1 << 5) /* Bit 5: COM interrupt Flag */ -#define ATIM_SR_TIF (1 << 6) /* Bit 6: Trigger interrupt Flag */ -#define ATIM_SR_BIF (1 << 7) /* Bit 7: Break interrupt Flag */ -#define ATIM_SR_B2IF (1 << 8) /* Bit 8: Break 2 interrupt Flag */ -#define ATIM_SR_CC1OF (1 << 9) /* Bit 9: Capture/Compare 1 Overcapture Flag */ -#define ATIM_SR_CC2OF (1 << 10) /* Bit 10: Capture/Compare 2 Overcapture Flag */ -#define ATIM_SR_CC3OF (1 << 11) /* Bit 11: Capture/Compare 3 Overcapture Flag */ -#define ATIM_SR_CC4OF (1 << 12) /* Bit 12: Capture/Compare 4 Overcapture Flag */ -#define ATIM_SR_SBIF (1 << 13) /* Bit 13: System break interrupt Flag */ -#define ATIM_SR_CC5IF (1 << 16) /* Bit 16: Compare 5 interrupt flag */ -#define ATIM_SR_CC6IF (1 << 17) /* Bit 17: Compare 6 interrupt flag */ - -/* Event generation register */ - -#define ATIM_EGR_UG (1 << 0) /* Bit 0: Update Generation */ -#define ATIM_EGR_CC1G (1 << 1) /* Bit 1: Capture/Compare 1 Generation */ -#define ATIM_EGR_CC2G (1 << 2) /* Bit 2: Capture/Compare 2 Generation */ -#define ATIM_EGR_CC3G (1 << 3) /* Bit 3: Capture/Compare 3 Generation */ -#define ATIM_EGR_CC4G (1 << 4) /* Bit 4: Capture/Compare 4 Generation */ -#define ATIM_EGR_COMG (1 << 5) /* Bit 5: Capture/Compare Control Update Generation */ -#define ATIM_EGR_TG (1 << 6) /* Bit 6: Trigger Generation */ -#define ATIM_EGR_BG (1 << 7) /* Bit 7: Break Generation */ -#define ATIM_EGR_B2G (1 << 8) /* Bit 8: Break 2 Generation */ - -/* Capture/compare mode register 1 -- Output compare mode */ - -#define ATIM_CCMR1_CC1S_SHIFT (0) /* Bits 1-0: Capture/Compare 1 Selection */ -#define ATIM_CCMR1_CC1S_MASK (3 << ATIM_CCMR1_CC1S_SHIFT) - /* (See common (unshifted) bit field definitions below) */ -#define ATIM_CCMR1_OC1FE (1 << 2) /* Bit 2: Output Compare 1 Fast enable */ -#define ATIM_CCMR1_OC1PE (1 << 3) /* Bit 3: Output Compare 1 Preload enable */ -#define ATIM_CCMR1_OC1M_SHIFT (4) /* Bits 6-4: Output Compare 1 Mode */ -#define ATIM_CCMR1_OC1M_MASK (7 << ATIM_CCMR1_OC1M_SHIFT) - /* (See common (unshifted) bit field definitions below) */ -#define ATIM_CCMR1_OC1CE (1 << 7) /* Bit 7: Output Compare 1Clear Enable */ -#define ATIM_CCMR1_CC2S_SHIFT (8) /* Bits 8-9: Capture/Compare 2 Selection */ -#define ATIM_CCMR1_CC2S_MASK (3 << ATIM_CCMR1_CC2S_SHIFT) - /* (See common (unshifted) bit field definitions below) */ -#define ATIM_CCMR1_OC2FE (1 << 10) /* Bit 10: Output Compare 2 Fast enable */ -#define ATIM_CCMR1_OC2PE (1 << 11) /* Bit 11: Output Compare 2 Preload enable */ -#define ATIM_CCMR1_OC2M_SHIFT (12) /* Bits 14-12: Output Compare 2 Mode */ -#define ATIM_CCMR1_OC2M_MASK (7 << ATIM_CCMR1_OC2M_SHIFT) - /* (See common (unshifted) bit field definitions below) */ -#define ATIM_CCMR1_OC2CE (1 << 15) /* Bit 15: Output Compare 2 Clear Enable */ -#define ATIM_CCMR1_OC1M (1 << 16) /* Bit 16: Output Compare 1 mode - bit 3 */ -#define ATIM_CCMR1_OC2M (1 << 24) /* Bit 24: Output Compare 2 mode - bit 3 */ - -/* Common CCMR (unshifted) Capture/Compare Selection bit-field definitions */ - -#define ATIM_CCMR_CCS_CCOUT (0) /* 00: CCx channel output */ -#define ATIM_CCMR_CCS_CCIN1 (1) /* 01: CCx channel input, ICx is TIx */ -#define ATIM_CCMR_CCS_CCIN2 (2) /* 10: CCx channel input, ICx is TIy */ -#define ATIM_CCMR_CCS_CCINTRC (3) /* 11: CCx channel input, ICx is TRC */ - -/* Common CCMR (unshifted) Compare Mode bit field definitions */ - -#define ATIM_CCMR_MODE_FRZN (0) /* 000: Frozen */ -#define ATIM_CCMR_MODE_CHACT (1) /* 001: Channel x active on match */ -#define ATIM_CCMR_MODE_CHINACT (2) /* 010: Channel x inactive on match */ -#define ATIM_CCMR_MODE_OCREFTOG (3) /* 011: OCxREF toggle ATIM_CNT=ATIM_CCRx */ -#define ATIM_CCMR_MODE_OCREFLO (4) /* 100: OCxREF forced low */ -#define ATIM_CCMR_MODE_OCREFHI (5) /* 101: OCxREF forced high */ -#define ATIM_CCMR_MODE_PWM1 (6) /* 110: PWM mode 1 */ -#define ATIM_CCMR_MODE_PWM2 (7) /* 111: PWM mode 2 */ -#define ATIM_CCMR_MODE_RETRIG1 (8) /* 1000: Retrigerrable OPM mode 1 */ -#define ATIM_CCMR_MODE_RETRIG2 (9) /* 1001: Retrigerrable OPM mode 2 */ -#define ATIM_CCMR_MODE_COMBINED1 (12) /* 1100: Combined PWM mode 1 */ -#define ATIM_CCMR_MODE_COMBINED2 (13) /* 1101: Combined PWM mode 2 */ -#define ATIM_CCMR_MODE_ASYMMETRIC1 (14) /* 1110: Asymmetric PWM mode 1 */ -#define ATIM_CCMR_MODE_ASYMMETRIC2 (15) /* 1111: Asymmetric PWM mode 2 */ - -/* Capture/compare mode register 1 -- Input capture mode */ - -/* Bits 1-0: - * same as output compare mode) - */ -#define ATIM_CCMR1_IC1PSC_SHIFT (2) /* Bits 3-2: Input Capture 1 Prescaler */ -#define ATIM_CCMR1_IC1PSC_MASK (3 << ATIM_CCMR1_IC1PSC_SHIFT) - /* (See common (unshifted) bit field definitions below) */ -#define ATIM_CCMR1_IC1F_SHIFT (4) /* Bits 7-4: Input Capture 1 Filter */ -#define ATIM_CCMR1_IC1F_MASK (0x0f << ATIM_CCMR1_IC1F_SHIFT) - /* (See common (unshifted) bit field definitions below) */ - /* Bits 9:8 (same as output compare mode) */ -#define ATIM_CCMR1_IC2PSC_SHIFT (10) /* Bits 11:10: Input Capture 2 Prescaler */ -#define ATIM_CCMR1_IC2PSC_MASK (3 << ATIM_CCMR1_IC2PSC_SHIFT) - /* (See common (unshifted) bit field definitions below) */ -#define ATIM_CCMR1_IC2F_SHIFT (12) /* Bits 15-12: Input Capture 2 Filter */ -#define ATIM_CCMR1_IC2F_MASK (0x0f << ATIM_CCMR1_IC2F_SHIFT) - /* (See common (unshifted) bit field definitions below) */ - -/* Common CCMR (unshifted) Input Capture Prescaler bit-field definitions */ - -#define ATIM_CCMR_ICPSC_NOPSC (0) /* 00: no prescaler, capture each edge */ -#define ATIM_CCMR_ICPSC_EVENTS2 (1) /* 01: capture once every 2 events */ -#define ATIM_CCMR_ICPSC_EVENTS4 (2) /* 10: capture once every 4 events */ -#define ATIM_CCMR_ICPSC_EVENTS8 (3) /* 11: capture once every 8 events */ - -/* Common CCMR (unshifted) Input Capture Filter bit-field definitions */ - -#define ATIM_CCMR_ICF_NOFILT (0) /* 0000: No filter, sampling at fDTS */ -#define ATIM_CCMR_ICF_FCKINT2 (1) /* 0001: fSAMPLING=fCK_INT, N=2 */ -#define ATIM_CCMR_ICF_FCKINT4 (2) /* 0010: fSAMPLING=fCK_INT, N=4 */ -#define ATIM_CCMR_ICF_FCKINT8 (3) /* 0011: fSAMPLING=fCK_INT, N=8 */ -#define ATIM_CCMR_ICF_FDTSd26 (4) /* 0100: fSAMPLING=fDTS/2, N=6 */ -#define ATIM_CCMR_ICF_FDTSd28 (5) /* 0101: fSAMPLING=fDTS/2, N=8 */ -#define ATIM_CCMR_ICF_FDTSd46 (6) /* 0110: fSAMPLING=fDTS/4, N=6 */ -#define ATIM_CCMR_ICF_FDTSd48 (7) /* 0111: fSAMPLING=fDTS/4, N=8 */ -#define ATIM_CCMR_ICF_FDTSd86 (8) /* 1000: fSAMPLING=fDTS/8, N=6 */ -#define ATIM_CCMR_ICF_FDTSd88 (9) /* 1001: fSAMPLING=fDTS/8, N=8 */ -#define ATIM_CCMR_ICF_FDTSd165 (10) /* 1010: fSAMPLING=fDTS/16, N=5 */ -#define ATIM_CCMR_ICF_FDTSd166 (11) /* 1011: fSAMPLING=fDTS/16, N=6 */ -#define ATIM_CCMR_ICF_FDTSd168 (12) /* 1100: fSAMPLING=fDTS/16, N=8 */ -#define ATIM_CCMR_ICF_FDTSd325 (13) /* 1101: fSAMPLING=fDTS/32, N=5 */ -#define ATIM_CCMR_ICF_FDTSd326 (14) /* 1110: fSAMPLING=fDTS/32, N=6 */ -#define ATIM_CCMR_ICF_FDTSd328 (15) /* 1111: fSAMPLING=fDTS/32, N=8 */ - -/* Capture/compare mode register 2 - Output Compare mode */ - -#define ATIM_CCMR2_CC3S_SHIFT (0) /* Bits 1-0: Capture/Compare 3 Selection */ -#define ATIM_CCMR2_CC3S_MASK (3 << ATIM_CCMR2_CC3S_SHIFT) - /* (See common (unshifted) bit field definitions above) */ -#define ATIM_CCMR2_OC3FE (1 << 2) /* Bit 2: Output Compare 3 Fast enable */ -#define ATIM_CCMR2_OC3PE (1 << 3) /* Bit 3: Output Compare 3 Preload enable */ -#define ATIM_CCMR2_OC3M_SHIFT (4) /* Bits 6-4: Output Compare 3 Mode */ -#define ATIM_CCMR2_OC3M_MASK (7 << ATIM_CCMR2_OC3M_SHIFT) - /* (See common (unshifted) bit field definitions above) */ -#define ATIM_CCMR2_OC3CE (1 << 7) /* Bit 7: Output Compare 3 Clear Enable */ -#define ATIM_CCMR2_CC4S_SHIFT (8) /* Bits 9-8: Capture/Compare 4 Selection */ -#define ATIM_CCMR2_CC4S_MASK (3 << ATIM_CCMR2_CC4S_SHIFT) - /* (See common (unshifted) bit field definitions above) */ -#define ATIM_CCMR2_OC4FE (1 << 10) /* Bit 10: Output Compare 4 Fast enable */ -#define ATIM_CCMR2_OC4PE (1 << 11) /* Bit 11: Output Compare 4 Preload enable */ -#define ATIM_CCMR2_OC4M_SHIFT (12) /* Bits 14-12: Output Compare 4 Mode */ -#define ATIM_CCMR2_OC4M_MASK (7 << ATIM_CCMR2_OC4M_SHIFT) - /* (See common (unshifted) bit field definitions above) */ -#define ATIM_CCMR2_OC4CE (1 << 15) /* Bit 15: Output Compare 4 Clear Enable */ -#define ATIM_CCMR2_OC3M (1 << 16) /* Bit 16: Output Compare 3 mode - bit 3 */ -#define ATIM_CCMR2_OC4M (1 << 24) /* Bit 24: Output Compare 4 mode - bit 3 */ - -/* Capture/compare mode register 2 - Input Capture Mode */ - -/* Bits 1-0: - * (same as output compare mode) - */ -#define ATIM_CCMR2_IC3PSC_SHIFT (2) /* Bits 3-2: Input Capture 3 Prescaler */ -#define ATIM_CCMR1_IC3PSC_MASK (3 << ATIM_CCMR2_IC3PSC_SHIFT) - /* (See common (unshifted) bit field definitions above) */ -#define ATIM_CCMR2_IC3F_SHIFT (4) /* Bits 7-4: Input Capture 3 Filter */ -#define ATIM_CCMR2_IC3F_MASK (0x0f << ATIM_CCMR2_IC3F_SHIFT) - /* (See common (unshifted) bit field definitions above) */ - /* Bits 9:8 (same as output compare mode) */ -#define ATIM_CCMR2_IC4PSC_SHIFT (10) /* Bits 11:10: Input Capture 4 Prescaler */ -#define ATIM_CCMR2_IC4PSC_MASK (3 << ATIM_CCMR2_IC4PSC_SHIFT) - /* (See common (unshifted) bit field definitions above) */ -#define ATIM_CCMR2_IC4F_SHIFT (12) /* Bits 15-12: Input Capture 4 Filter */ -#define ATIM_CCMR2_IC4F_MASK (0x0f << ATIM_CCMR2_IC4F_SHIFT) - /* (See common (unshifted) bit field definitions above) */ - -/* Capture/compare mode register 3 -- Output compare mode */ - -#define ATIM_CCMR3_OC5FE (1 << 2) /* Bit 2: Output Compare 5 Fast enable */ -#define ATIM_CCMR3_OC5PE (1 << 3) /* Bit 3: Output Compare 5 Preload enable */ -#define ATIM_CCMR3_OC5M_SHIFT (4) /* Bits 6-4: Output Compare 5 Mode */ -#define ATIM_CCMR3_OC5M_MASK (7 << ATIM_CCMR3_OC5M_SHIFT) - - /* (See common (unshifted) bit field definitions below) */ -#define ATIM_CCMR3_OC5CE (1 << 7) /* Bit 7: Output Compare 5 Clear Enable */ -#define ATIM_CCMR3_OC6FE (1 << 10) /* Bit 10: Output Compare 6 Fast enable */ -#define ATIM_CCMR3_OC6PE (1 << 11) /* Bit 11: Output Compare 6 Preload enable */ -#define ATIM_CCMR3_OC6M_SHIFT (12) /* Bits 14-12: Output Compare 7 Mode */ -#define ATIM_CCMR3_OC6M_MASK (7 << ATIM_CCMR3_OC6M_SHIFT) - - /* (See common (unshifted) bit field definitions below) */ -#define ATIM_CCMR3_OC6CE (1 << 15) /* Bit 15: Output Compare 7 Clear Enable */ - -#define ATIM_CCMR3_OC5M (1 << 16) /* Bit 16: Output Compare 5 mode - bit 3 */ -#define ATIM_CCMR3_OC6M (1 << 24) /* Bit 24: Output Compare 6 mode - bit 3 */ - -/* Capture/compare enable register */ - -#define ATIM_CCER_CC1E (1 << 0) /* Bit 0: Capture/Compare 1 output enable */ -#define ATIM_CCER_CC1P (1 << 1) /* Bit 1: Capture/Compare 1 output Polarity */ -#define ATIM_CCER_CC1NE (1 << 2) /* Bit 2: Capture/Compare 1 Complementary output enable */ -#define ATIM_CCER_CC1NP (1 << 3) /* Bit 3: Capture/Compare 1 Complementary output polarity */ -#define ATIM_CCER_CC2E (1 << 4) /* Bit 4: Capture/Compare 2 output enable */ -#define ATIM_CCER_CC2P (1 << 5) /* Bit 5: Capture/Compare 2 output Polarity */ -#define ATIM_CCER_CC2NE (1 << 6) /* Bit 6: Capture/Compare 2 Complementary output enable */ -#define ATIM_CCER_CC2NP (1 << 7) /* Bit 7: Capture/Compare 2 Complementary output polarity */ -#define ATIM_CCER_CC3E (1 << 8) /* Bit 8: Capture/Compare 3 output enable */ -#define ATIM_CCER_CC3P (1 << 9) /* Bit 9: Capture/Compare 3 output Polarity */ -#define ATIM_CCER_CC3NE (1 << 10) /* Bit 10: Capture/Compare 3 Complementary output enable */ -#define ATIM_CCER_CC3NP (1 << 11) /* Bit 11: Capture/Compare 3 Complementary output polarity */ -#define ATIM_CCER_CC4E (1 << 12) /* Bit 12: Capture/Compare 4 output enable */ -#define ATIM_CCER_CC4P (1 << 13) /* Bit 13: Capture/Compare 4 output Polarity */ -#define ATIM_CCER_CC4NP (1 << 15) /* Bit 15: Capture/Compare 4 Complementary output polarity */ -#define ATIM_CCER_CC5E (1 << 16) /* Bit 16: Capture/Compare 5 output enable */ -#define ATIM_CCER_CC5P (1 << 17) /* Bit 17: Capture/Compare 5 output Polarity */ -#define ATIM_CCER_CC6E (1 << 20) /* Bit 20: Capture/Compare 6 output enable */ -#define ATIM_CCER_CC6P (1 << 21) /* Bit 21: Capture/Compare 6 output Polarity */ -#define ATIM_CCER_CCXBASE(ch) (ch << 2) /* Each channel uses 4-bits */ - -/* 16-bit counter register */ - -#define ATIM_CNT_SHIFT (0) /* Bits 0-15: Timer counter value */ -#define ATIM_CNT_MASK (0xffff << ATIM_CNT_SHIFT) -#define ATIM_CCER_UIFCPY (1 << 31) /* Bit 31: UIF copy */ - -/* Repetition counter register */ - -#define ATIM_RCR_REP_SHIFT (0) /* Bits 0-15: Repetition Counter Value */ -#define ATIM_RCR_REP_MASK (0xffff << ATIM_RCR_REP_SHIFT) -#define ATIM_RCR_REP_MAX 65536 - -/* Capture/compare registers (CCR) */ - -#define ATIM_CCR5_GC5C1 (1 << 29) /* Bit 29: Group Channel 5 and Channel 1 */ -#define ATIM_CCR5_GC5C2 (1 << 30) /* Bit 30: Group Channel 5 and Channel 2 */ -#define ATIM_CCR5_GC5C3 (1 << 31) /* Bit 31: Group Channel 5 and Channel 3 */ - -#define ATIM_CCR_MASK (0xffff) - -/* Alternate function option register 1 (TIMx_AF1) */ - -#define ATIM_AF1_BKINE (1 << 0) /* Bit 0: BRK BKIN input enable */ -#define ATIM_AF1_BKINP (1 << 9) /* Bit 9: BRK BKIN input polarity */ - -#define ATIM_AF1_ETRSEL_SHIFT (14) /* Bits 14-17: ETR source selection */ -#define ATIM_AF1_ETRSEL_MASK (0xf << ATIM_AF1_ETRSEL_SHIFT) -# define ATIM_AF1_ETRLEGACY (0 << ATIM_AF1_ETRSEL_SHIFT) /* 0000: ETR legacy mode */ -# define ATIM_AF1_ADC1AWD1 (3 << ATIM_AF1_ETRSEL_SHIFT) /* 0011: ADC1 AWD1 */ -# define ATIM_AF1_ADC1AWD2 (4 << ATIM_AF1_ETRSEL_SHIFT) /* 0100: ADC1 AWD2 */ -# define ATIM_AF1_ADC1AWD3 (5 << ATIM_AF1_ETRSEL_SHIFT) /* 0101: ADC1 AWD3 */ - -/* Alternate function option register 2 (TIMx_AF2) */ - -#define ATIM_AF2_BK2INE (1 << 0) /* Bit 0: BRK2 BKIN input enable */ -#define ATIM_AF2_BK2INP (1 << 9) /* Bit 9: BRK2 BKIN2 input polarity */ - -/* Break and dead-time register */ - -#define ATIM_BDTR_DTG_SHIFT (0) /* Bits 7:0 [7:0]: Dead-Time Generator set-up */ -#define ATIM_BDTR_DTG_MASK (0xff << ATIM_BDTR_DTG_SHIFT) -#define ATIM_BDTR_LOCK_SHIFT (8) /* Bits 9:8 [1:0]: Lock Configuration */ -#define ATIM_BDTR_LOCK_MASK (3 << ATIM_BDTR_LOCK_SHIFT) -# define ATIM_BDTR_LOCKOFF (0 << ATIM_BDTR_LOCK_SHIFT) /* 00: LOCK OFF - No bit is write protected */ -# define ATIM_BDTR_LOCK1 (1 << ATIM_BDTR_LOCK_SHIFT) /* 01: LOCK Level 1 protection */ -# define ATIM_BDTR_LOCK2 (2 << ATIM_BDTR_LOCK_SHIFT) /* 10: LOCK Level 2 protection */ -# define ATIM_BDTR_LOCK3 (3 << ATIM_BDTR_LOCK_SHIFT) /* 11: LOCK Level 3 protection */ - -#define ATIM_BDTR_OSSI (1 << 10) /* Bit 10: Off-State Selection for Idle mode */ -#define ATIM_BDTR_OSSR (1 << 11) /* Bit 11: Off-State Selection for Run mode */ -#define ATIM_BDTR_BKE (1 << 12) /* Bit 12: Break enable */ -#define ATIM_BDTR_BKP (1 << 13) /* Bit 13: Break Polarity */ -#define ATIM_BDTR_AOE (1 << 14) /* Bit 14: Automatic Output enable */ -#define ATIM_BDTR_MOE (1 << 15) /* Bit 15: Main Output enable */ -#define ATIM_BDTR_BKF_SHIFT (16) /* Bits 16-19: Break filter */ -#define ATIM_BDTR_BKF_MASK (0xf << ATIM_BDTR_BKF_SHIFT) -# define ATIM_BDTR_BKF_NOFILT (0 << ATIM_BDTR_BKF_SHIFT) /* 0000: No filter, BRK acts asynchronously */ -# define ATIM_BDTR_BKF_FCKINT2 (1 << ATIM_BDTR_BKF_SHIFT) /* 0001: fSAMPLING=fCK_INT, N=2 */ -# define ATIM_BDTR_BKF_FCKINT4 (2 << ATIM_BDTR_BKF_SHIFT) /* 0010: fSAMPLING=fCK_INT, N=4 */ -# define ATIM_BDTR_BKF_FCKINT8 (3 << ATIM_BDTR_BKF_SHIFT) /* 0011: fSAMPLING=fCK_INT, N=8 */ -# define ATIM_BDTR_BKF_FDTSd26 (4 << ATIM_BDTR_BKF_SHIFT) /* 0100: fSAMPLING=fDTS/2, N=6 */ -# define ATIM_BDTR_BKF_FDTSd28 (5 << ATIM_BDTR_BKF_SHIFT) /* 0101: fSAMPLING=fDTS/2, N=8 */ -# define ATIM_BDTR_BKF_FDTSd36 (6 << ATIM_BDTR_BKF_SHIFT) /* 0110: fSAMPLING=fDTS/4, N=6 */ -# define ATIM_BDTR_BKF_FDTSd38 (7 << ATIM_BDTR_BKF_SHIFT) /* 0111: fSAMPLING=fDTS/4, N=8 */ -# define ATIM_BDTR_BKF_FDTSd86 (8 << ATIM_BDTR_BKF_SHIFT) /* 1000: fSAMPLING=fDTS/8, N=6 */ -# define ATIM_BDTR_BKF_FDTSd88 (9 << ATIM_BDTR_BKF_SHIFT) /* 1001: fSAMPLING=fDTS/8, N=8 */ -# define ATIM_BDTR_BKF_FDTSd165 (10 << ATIM_BDTR_BKF_SHIFT) /* 1010: fSAMPLING=fDTS/16, N=5 */ -# define ATIM_BDTR_BKF_FDTSd166 (11 << ATIM_BDTR_BKF_SHIFT) /* 1011: fSAMPLING=fDTS/16, N=6 */ -# define ATIM_BDTR_BKF_FDTSd168 (12 << ATIM_BDTR_BKF_SHIFT) /* 1100: fSAMPLING=fDTS/16, N=8 */ -# define ATIM_BDTR_BKF_FDTSd325 (13 << ATIM_BDTR_BKF_SHIFT) /* 1101: fSAMPLING=fDTS/32, N=5 */ -# define ATIM_BDTR_BKF_FDTSd326 (14 << ATIM_BDTR_BKF_SHIFT) /* 1110: fSAMPLING=fDTS/32, N=6 */ -# define ATIM_BDTR_BKF_FDTSd328 (15 << ATIM_BDTR_BKF_SHIFT) /* 1111: fSAMPLING=fDTS/32, N=8 */ - -#define ATIM_BDTR_BK2F_SHIFT (20) /* Bits 20-23: Break 2 filter */ -#define ATIM_BDTR_BK2F_MASK (0xf << ATIM_BDTR_BK2F_SHIFT) -# define ATIM_BDTR_BK2F_NOFILT (0 << ATIM_BDTR_BK2F_SHIFT) /* 0000: No filter, BRK 2 acts asynchronously */ -# define ATIM_BDTR_BK2F_FCKINT2 (1 << ATIM_BDTR_BK2F_SHIFT) /* 0001: fSAMPLING=fCK_INT, N=2 */ -# define ATIM_BDTR_BK2F_FCKINT4 (2 << ATIM_BDTR_BK2F_SHIFT) /* 0010: fSAMPLING=fCK_INT, N=4 */ -# define ATIM_BDTR_BK2F_FCKINT8 (3 << ATIM_BDTR_BK2F_SHIFT) /* 0011: fSAMPLING=fCK_INT, N=8 */ -# define ATIM_BDTR_BK2F_FDTSd26 (4 << ATIM_BDTR_BK2F_SHIFT) /* 0100: fSAMPLING=fDTS/2, N=6 */ -# define ATIM_BDTR_BK2F_FDTSd28 (5 << ATIM_BDTR_BK2F_SHIFT) /* 0101: fSAMPLING=fDTS/2, N=8 */ -# define ATIM_BDTR_BK2F_FDTSd36 (6 << ATIM_BDTR_BK2F_SHIFT) /* 0110: fSAMPLING=fDTS/4, N=6 */ -# define ATIM_BDTR_BK2F_FDTSd38 (7 << ATIM_BDTR_BK2F_SHIFT) /* 0111: fSAMPLING=fDTS/4, N=8 */ -# define ATIM_BDTR_BK2F_FDTSd86 (8 << ATIM_BDTR_BK2F_SHIFT) /* 1000: fSAMPLING=fDTS/8, N=6 */ -# define ATIM_BDTR_BK2F_FDTSd88 (9 << ATIM_BDTR_BK2F_SHIFT) /* 1001: fSAMPLING=fDTS/8, N=8 */ -# define ATIM_BDTR_BK2F_FDTSd165 (10 << ATIM_BDTR_BK2F_SHIFT) /* 1010: fSAMPLING=fDTS/16, N=5 */ -# define ATIM_BDTR_BK2F_FDTSd166 (11 << ATIM_BDTR_BK2F_SHIFT) /* 1011: fSAMPLING=fDTS/16, N=6 */ -# define ATIM_BDTR_BK2F_FDTSd168 (12 << ATIM_BDTR_BK2F_SHIFT) /* 1100: fSAMPLING=fDTS/16, N=8 */ -# define ATIM_BDTR_BK2F_FDTSd325 (13 << ATIM_BDTR_BK2F_SHIFT) /* 1101: fSAMPLING=fDTS/32, N=5 */ -# define ATIM_BDTR_BK2F_FDTSd326 (14 << ATIM_BDTR_BK2F_SHIFT) /* 1110: fSAMPLING=fDTS/32, N=6 */ -# define ATIM_BDTR_BK2F_FDTSd328 (15 << ATIM_BDTR_BK2F_SHIFT) /* 1111: fSAMPLING=fDTS/32, N=8 */ - -#define ATIM_BDTR_BK2E (1 << 24) /* Bit 24: Break2 enable */ -#define ATIM_BDTR_BK2P (1 << 25) /* Bit 25: Break2 polarity */ -#define ATIM_BDTR_BKDSRM (1 << 26) /* Bit 26: Break disarm */ -#define ATIM_BDTR_BK2DSRM (1 << 27) /* Bit 27: Break2 disarm */ -#define ATIM_BDTR_BKBID (1 << 28) /* Bit 28: Break bidirectional */ -#define ATIM_BDTR_BK2BID (1 << 29) /* Bit 29: Break 2 bidirectional */ - -/* DMA control register */ - -#define ATIM_DCR_DBA_SHIFT (0) /* Bits 4-0: DMA Base Address */ -#define ATIM_DCR_DBA_MASK (0x1f << ATIM_DCR_DBA_SHIFT) -#define ATIM_DCR_DBL_SHIFT (8) /* Bits 12-8: DMA Burst Length */ -#define ATIM_DCR_DBL_MASK (0x1f << ATIM_DCR_DBL_SHIFT) -# define ATIM_DCR_DBL(n) (((n)-1) << ATIM_DCR_DBL_SHIFT) /* n transfers, n = 1..18 */ - -/* Timer input selection register */ - -#define ATIM_TISEL_TI1SEL_SHIFT (0) /* Bits 3-0: Selects TI1[0] to TI1[15] input */ -#define ATIM_TISEL_TI1SEL_MASK (0xf << ATIM_TISEL_TI1SEL_SHIFT) -#define ATIM_TISEL_TI2SEL_SHIFT (8) /* Bits 11-8: Selects TI2[0] to TI2[15] input */ -#define ATIM_TISEL_TI2SEL_MASK (0xf << ATIM_TISEL_TI2SEL_SHIFT) -#define ATIM_TISEL_TI3SEL_SHIFT (16) /* Bits 19-16: Selects TI3[0] to TI3[15] input */ -#define ATIM_TISEL_TI3SEL_MASK (0xf << ATIM_TISEL_TI3SEL_SHIFT) -#define ATIM_TISEL_TI4SEL_SHIFT (24) /* Bits 27-24: Selects TI4[0] to TI4[15] input */ -#define ATIM_TISEL_TI4SEL_MASK (0xf << ATIM_TISEL_TI4SEL_SHIFT) - -/* Control register 1 */ - -#define GTIM_CR1_CEN (1 << 0) /* Bit 0: Counter enable */ -#define GTIM_CR1_UDIS (1 << 1) /* Bit 1: Update Disable */ -#define GTIM_CR1_URS (1 << 2) /* Bit 2: Update Request Source */ -#define GTIM_CR1_OPM (1 << 3) /* Bit 3: One Pulse Mode */ -#define GTIM_CR1_DIR (1 << 4) /* Bit 4: Direction (TIM3 only) */ -#define GTIM_CR1_CMS_SHIFT (5) /* Bits 6-5: Center-aligned Mode Selection (TIM3 only) */ -#define GTIM_CR1_CMS_MASK (3 << GTIM_CR1_CMS_SHIFT) -# define GTIM_CR1_EDGE (0 << GTIM_CR1_CMS_SHIFT) /* 00: Edge-aligned mode. */ -# define GTIM_CR1_CENTER1 (1 << GTIM_CR1_CMS_SHIFT) /* 01: Center-aligned mode 1 */ -# define GTIM_CR1_CENTER2 (2 << GTIM_CR1_CMS_SHIFT) /* 10: Center-aligned mode 2 */ -# define GTIM_CR1_CENTER3 (3 << GTIM_CR1_CMS_SHIFT) /* 11: Center-aligned mode 3 */ - -#define GTIM_CR1_ARPE (1 << 7) /* Bit 7: Auto-Reload Preload enable */ -#define GTIM_CR1_CKD_SHIFT (8) /* Bits 9-8: Clock Division */ -#define GTIM_CR1_CKD_MASK (3 << GTIM_CR1_CKD_SHIFT) -# define GTIM_CR1_TCKINT (0 << GTIM_CR1_CKD_SHIFT) /* 00: tDTS = tCK_INT */ -# define GTIM_CR1_2TCKINT (1 << GTIM_CR1_CKD_SHIFT) /* 01: tDTS = 2 x tCK_INT */ -# define GTIM_CR1_4TCKINT (2 << GTIM_CR1_CKD_SHIFT) /* 10: tDTS = 4 x tCK_INT */ - -#define GTIM_CR1_UIFREMAP (1 << 11) /* Bit 11: UIF status bit remapping */ - -/* Control register 2 (16-bit TIM3 and TIM15-17) */ - -#define GTIM_CR2_CCPC (1 << 0) /* Bit 0: Capture/compare preloaded control (TIM15-17 only) */ -#define GTIM_CR2_CCUS (1 << 2) /* Bit 2: Capture/compare control update selection (TIM15 only) */ -#define GTIM_CR2_CCDS (1 << 3) /* Bit 3: Capture/Compare DMA Selection */ -#define GTIM_CR2_MMS_SHIFT (4) /* Bits 6-4: Master Mode Selection (TIM3 and TIM15 only) */ -#define GTIM_CR2_MMS_MASK (7 << GTIM_CR2_MMS_SHIFT) -# define GTIM_CR2_MMS_RESET (0 << GTIM_CR2_MMS_SHIFT) /* 000: Reset */ -# define GTIM_CR2_MMS_ENABLE (1 << GTIM_CR2_MMS_SHIFT) /* 001: Enable */ -# define GTIM_CR2_MMS_UPDATE (2 << GTIM_CR2_MMS_SHIFT) /* 010: Update */ -# define GTIM_CR2_MMS_COMPP (3 << GTIM_CR2_MMS_SHIFT) /* 011: Compare Pulse */ -# define GTIM_CR2_MMS_OC1REF (4 << GTIM_CR2_MMS_SHIFT) /* 100: Compare - OC1REF signal is used as trigger output (TRGO) */ -# define GTIM_CR2_MMS_OC2REF (5 << GTIM_CR2_MMS_SHIFT) /* 101: Compare - OC2REF signal is used as trigger output (TRGO) */ -# define GTIM_CR2_MMS_OC3REF (6 << GTIM_CR2_MMS_SHIFT) /* 110: Compare - OC3REF signal is used as trigger output (TRGO, TIM3 only) */ -# define GTIM_CR2_MMS_OC4REF (7 << GTIM_CR2_MMS_SHIFT) /* 111: Compare - OC4REF signal is used as trigger output (TRGO, TIM3 only) */ - -#define GTIM_CR2_TI1S (1 << 7) /* Bit 7: TI1 Selection (TIM3 and TIM15 only) */ -#define GTIM_CR2_OIS1 (1 << 8) /* Bit 8: COutput Idle state 1 (OC1 output) (TIM15-17 only) */ -#define GTIM_CR2_OIS1N (1 << 9) /* Bit 9: Output Idle state 1 (OC1N output) (TIM15-17 only) */ -#define GTIM_CR2_OIS2 (1 << 10) /* Bit 10: Output idle state 2 (OC2 output) (TIM15 only) */ - -/* Slave mode control register (TIM3 and TIM15 only) */ - -#define GTIM_SMCR_SMS_SHIFT (0) /* Bits 2-0: Slave Mode Selection */ -#define GTIM_SMCR_SMS_MASK (7 << GTIM_SMCR_SMS_SHIFT) -# define GTIM_SMCR_DISAB (0 << GTIM_SMCR_SMS_SHIFT) /* 000: Slave mode disabled */ -# define GTIM_SMCR_ENCMD1 (1 << GTIM_SMCR_SMS_SHIFT) /* 001: Encoder mode 1 */ -# define GTIM_SMCR_ENCMD2 (2 << GTIM_SMCR_SMS_SHIFT) /* 010: Encoder mode 2 */ -# define GTIM_SMCR_ENCMD3 (3 << GTIM_SMCR_SMS_SHIFT) /* 011: Encoder mode 3 */ -# define GTIM_SMCR_RESET (4 << GTIM_SMCR_SMS_SHIFT) /* 100: Reset Mode */ -# define GTIM_SMCR_GATED (5 << GTIM_SMCR_SMS_SHIFT) /* 101: Gated Mode */ -# define GTIM_SMCR_TRIGGER (6 << GTIM_SMCR_SMS_SHIFT) /* 110: Trigger Mode */ -# define GTIM_SMCR_EXTCLK1 (7 << GTIM_SMCR_SMS_SHIFT) /* 111: External Clock Mode 1 */ - -#define GTIM_SMCR_OCCS (1 << 3) /* Bit 3: OCREF Clear Selection (TIM3 only) */ -#define GTIM_SMCR_TS_SHIFT (4) /* Bits 6-4: Trigger Selection. See TS2 below for more options. */ -#define GTIM_SMCR_TS_MASK (7 << GTIM_SMCR_TS_SHIFT) -# define GTIM_SMCR_ITR0 (0 << GTIM_SMCR_TS_SHIFT) /* 000: Internal Trigger 0 (ITR0). For TIM3: TIM1. */ -# define GTIM_SMCR_ITR1 (1 << GTIM_SMCR_TS_SHIFT) /* 001: Internal Trigger 1 (ITR1). For TIM15: TIM3*/ -# define GTIM_SMCR_ITR2 (2 << GTIM_SMCR_TS_SHIFT) /* 010: Internal Trigger 2 (ITR2). For TIM3: TIM15. For TIM15: TIM16_OC1 */ -# define GTIM_SMCR_ITR3 (3 << GTIM_SMCR_TS_SHIFT) /* 011: Internal Trigger 3 (ITR3). For TIM3: TIM14_OC1. For TIM15: TIM17_OC1 */ -# define GTIM_SMCR_TI1FED (4 << GTIM_SMCR_TS_SHIFT) /* 100: TI1 Edge Detector (TI1F_ED) */ -# define GTIM_SMCR_TI1FP1 (5 << GTIM_SMCR_TS_SHIFT) /* 101: Filtered Timer Input 1 (TI1FP1) */ -# define GTIM_SMCR_TI2FP2 (6 << GTIM_SMCR_TS_SHIFT) /* 110: Filtered Timer Input 2 (TI2FP2) */ -# define GTIM_SMCR_ETRF (7 << GTIM_SMCR_TS_SHIFT) /* 111: External Trigger input (ETRF) */ - -#define GTIM_SMCR_MSM (1 << 7) /* Bit 7: Master/Slave mode */ -#define GTIM_SMCR_ETF_SHIFT (8) /* Bits 11-8: External Trigger Filter (TIM3 only) */ -#define GTIM_SMCR_ETF_MASK (0x0f << GTIM_SMCR_ETF_SHIFT) -# define GTIM_SMCR_NOFILT (0 << GTIM_SMCR_ETF_SHIFT) /* 0000: No filter, sampling is done at fDTS */ -# define GTIM_SMCR_FCKINT2 (1 << GTIM_SMCR_ETF_SHIFT) /* 0001: fSAMPLING=fCK_INT, N=2 */ -# define GTIM_SMCR_FCKINT4 (2 << GTIM_SMCR_ETF_SHIFT) /* 0010: fSAMPLING=fCK_INT, N=4 */ -# define GTIM_SMCR_FCKINT8 (3 << GTIM_SMCR_ETF_SHIFT) /* 0011: fSAMPLING=fCK_INT, N=8 */ -# define GTIM_SMCR_FDTSd26 (4 << GTIM_SMCR_ETF_SHIFT) /* 0100: fSAMPLING=fDTS/2, N=6 */ -# define GTIM_SMCR_FDTSd28 (5 << GTIM_SMCR_ETF_SHIFT) /* 0101: fSAMPLING=fDTS/2, N=8 */ -# define GTIM_SMCR_FDTSd36 (6 << GTIM_SMCR_ETF_SHIFT) /* 0110: fSAMPLING=fDTS/4, N=6 */ -# define GTIM_SMCR_FDTSd38 (7 << GTIM_SMCR_ETF_SHIFT) /* 0111: fSAMPLING=fDTS/4, N=8 */ -# define GTIM_SMCR_FDTSd86 (8 << GTIM_SMCR_ETF_SHIFT) /* 1000: fSAMPLING=fDTS/8, N=6 */ -# define GTIM_SMCR_FDTSd88 (9 << GTIM_SMCR_ETF_SHIFT) /* 1001: fSAMPLING=fDTS/8, N=8 */ -# define GTIM_SMCR_FDTSd165 (10 << GTIM_SMCR_ETF_SHIFT) /* 1010: fSAMPLING=fDTS/16, N=5 */ -# define GTIM_SMCR_FDTSd166 (11 << GTIM_SMCR_ETF_SHIFT) /* 1011: fSAMPLING=fDTS/16, N=6 */ -# define GTIM_SMCR_FDTSd168 (12 << GTIM_SMCR_ETF_SHIFT) /* 1100: fSAMPLING=fDTS/16, N=8 */ -# define GTIM_SMCR_FDTSd325 (13 << GTIM_SMCR_ETF_SHIFT) /* 1101: fSAMPLING=fDTS/32, N=5 */ -# define GTIM_SMCR_FDTSd326 (14 << GTIM_SMCR_ETF_SHIFT) /* 1110: fSAMPLING=fDTS/32, N=6 */ -# define GTIM_SMCR_FDTSd328 (15 << GTIM_SMCR_ETF_SHIFT) /* 1111: fSAMPLING=fDTS/32, N=8 */ - -#define GTIM_SMCR_ETPS_SHIFT (12) /* Bits 13-12: External Trigger Prescaler (TIM3 only) */ -#define GTIM_SMCR_ETPS_MASK (3 << GTIM_SMCR_ETPS_SHIFT) -# define GTIM_SMCR_PSCOFF (0 << GTIM_SMCR_ETPS_SHIFT) /* 00: Prescaler OFF */ -# define GTIM_SMCR_ETRPd2 (1 << GTIM_SMCR_ETPS_SHIFT) /* 01: ETRP frequency divided by 2 */ -# define GTIM_SMCR_ETRPd4 (2 << GTIM_SMCR_ETPS_SHIFT) /* 10: ETRP frequency divided by 4 */ -# define GTIM_SMCR_ETRPd8 (3 << GTIM_SMCR_ETPS_SHIFT) /* 11: ETRP frequency divided by 8 */ - -#define GTIM_SMCR_ECE (1 << 14) /* Bit 14: External Clock enable (TIM3 only) */ -#define GTIM_SMCR_ETP (1 << 15) /* Bit 15: External Trigger Polarity (TIM3 only) */ -#define GTIM_SMCR_SMS (1 << 16) /* Bit 16: Slave mode selection - bit 3 */ -#define GTIM_SMCR_TS2_SHIFT (4) /* Bits 21-20: Trigger Selection - bits 3-4 - * Other values for TS (including bits 3-4): - * 01000: Internal Trigger 4 (ITR4) - * 01001: Internal Trigger 5 (ITR5) - * 01010: Internal Trigger 6 (ITR6) - * 01011: Internal Trigger 7 (ITR7) - * 01100: Internal Trigger 8 (ITR8) - */ -#define GTIM_SMCR_TS2_MASK (3 << GTIM_SMCR_TS_SHIFT) - -/* DMA/Interrupt enable register */ - -#define GTIM_DIER_UIE (1 << 0) /* Bit 0: Update interrupt enable */ -#define GTIM_DIER_CC1IE (1 << 1) /* Bit 1: Capture/Compare 1 interrupt enable */ -#define GTIM_DIER_CC2IE (1 << 2) /* Bit 2: Capture/Compare 2 interrupt enable (TIM3, TIM15 only) */ -#define GTIM_DIER_CC3IE (1 << 3) /* Bit 3: Capture/Compare 3 interrupt enable (TIM3 only) */ -#define GTIM_DIER_CC4IE (1 << 4) /* Bit 4: Capture/Compare 4 interrupt enable (TIM3 only) */ -#define GTIM_DIER_COMIE (1 << 5) /* Bit 5: COM interrupt enable (TIM15-17 only) */ -#define GTIM_DIER_TIE (1 << 6) /* Bit 6: Trigger interrupt enable (TIM3, TIM15 only) */ -#define GTIM_DIER_BIE (1 << 7) /* Bit 7: Break interrupt enable (TIM15-17 only) */ -#define GTIM_DIER_UDE (1 << 8) /* Bit 8: Update DMA request enable (TIM3, TIM15-17 only) */ -#define GTIM_DIER_CC1DE (1 << 9) /* Bit 9: Capture/Compare 1 DMA request enable (TIM3, TIM15-17 only) */ -#define GTIM_DIER_CC2DE (1 << 10) /* Bit 10: Capture/Compare 2 DMA request enable (TIM3, TIM15 only) */ -#define GTIM_DIER_CC3DE (1 << 11) /* Bit 11: Capture/Compare 3 DMA request enable (TIM3 only) */ -#define GTIM_DIER_CC4DE (1 << 12) /* Bit 12: Capture/Compare 4 DMA request enable (TIM3 only) */ -#define GTIM_DIER_COMDE (1 << 13) /* Bit 13: COM DMA request enable (TIM15 only) */ -#define GTIM_DIER_TDE (1 << 14) /* Bit 14: Trigger DMA request enable (TIM3, TIM15 only) */ - -/* Status register */ - -#define GTIM_SR_UIF (1 << 0) /* Bit 0: Update interrupt flag */ -#define GTIM_SR_CC1IF (1 << 1) /* Bit 1: Capture/compare 1 interrupt flag */ -#define GTIM_SR_CC2IF (1 << 2) /* Bit 2: Capture/Compare 2 interrupt flag (TIM3,15 only) */ -#define GTIM_SR_CC3IF (1 << 3) /* Bit 3: Capture/Compare 3 interrupt flag (TIM3,15 only) */ -#define GTIM_SR_CC4IF (1 << 4) /* Bit 4: Capture/Compare 4 interrupt flag (TIM3,15 only) */ -#define GTIM_SR_COMIF (1 << 5) /* Bit 5: COM interrupt flag (TIM15-17 only) */ -#define GTIM_SR_TIF (1 << 6) /* Bit 6: Trigger interrupt Flag (TIM3,15 only) */ -#define GTIM_SR_BIF (1 << 7) /* Bit 7: Break interrupt flag (TIM15-17 only) */ -#define GTIM_SR_CC1OF (1 << 9) /* Bit 9: Capture/Compare 1 Overcapture flag */ -#define GTIM_SR_CC2OF (1 << 10) /* Bit 10: Capture/Compare 2 Overcapture flag (TIM3,15 only) */ -#define GTIM_SR_CC3OF (1 << 11) /* Bit 11: Capture/Compare 3 Overcapture flag (TIM3 only) */ -#define GTIM_SR_CC4OF (1 << 12) /* Bit 12: Capture/Compare 4 Overcapture flag (TIM3 only) */ - -/* Event generation register */ - -#define GTIM_EGR_UG (1 << 0) /* Bit 0: Update generation */ -#define GTIM_EGR_CC1G (1 << 1) /* Bit 1: Capture/compare 1 generation */ -#define GTIM_EGR_CC2G (1 << 2) /* Bit 2: Capture/compare 2 generation (TIM3,15 only) */ -#define GTIM_EGR_CC3G (1 << 3) /* Bit 3: Capture/compare 3 generation (TIM3 only) */ -#define GTIM_EGR_CC4G (1 << 4) /* Bit 4: Capture/compare 4 generation (TIM3 only) */ -#define GTIM_EGR_COMIG (1 << 5) /* Bit 5: Capture/Compare control update generation (TIM15-17 only) */ -#define GTIM_EGR_TG (1 << 6) /* Bit 6: Trigger generation (TIM3,15 only) */ -#define GTIM_EGR_BG (1 << 7) /* Bit 7: Break generation (TIM15-17 only) */ - -/* Capture/compare mode register 1 - Output compare mode */ - -#define GTIM_CCMR1_CC1S_SHIFT (0) /* Bits 1-0: Capture/Compare 1 Selection */ -#define GTIM_CCMR1_CC1S_MASK (3 << GTIM_CCMR1_CC1S_SHIFT) - /* (See common CCMR Capture/Compare Selection definitions below) */ -#define GTIM_CCMR1_OC1FE (1 << 2) /* Bit 2: Output Compare 1 Fast enable */ -#define GTIM_CCMR1_OC1PE (1 << 3) /* Bit 3: Output Compare 1 Preload enable */ -#define GTIM_CCMR1_OC1M_SHIFT (4) /* Bits 6-4: Output Compare 1 Mode */ -#define GTIM_CCMR1_OC1M_MASK (7 << GTIM_CCMR1_OC1M_SHIFT) - /* (See common CCMR Output Compare Mode definitions below) */ -#define GTIM_CCMR1_OC1CE (1 << 7) /* Bit 7: Output Compare 1Clear Enable (TIM3 only) */ -#define GTIM_CCMR1_CC2S_SHIFT (8) /* Bits 9-8: Capture/Compare 2 Selection (TIM3,15 only) */ -#define GTIM_CCMR1_CC2S_MASK (3 << GTIM_CCMR1_CC2S_SHIFT) - /* (See common CCMR Capture/Compare Selection definitions below) */ -#define GTIM_CCMR1_OC2FE (1 << 10) /* Bit 10: Output Compare 2 Fast enable (TIM3,15 only) */ -#define GTIM_CCMR1_OC2PE (1 << 11) /* Bit 11: Output Compare 2 Preload enable (TIM3,15 only) */ -#define GTIM_CCMR1_OC2M_SHIFT (12) /* Bits 14-12: Output Compare 2 Mode (TIM3,15 only) */ -#define GTIM_CCMR1_OC2M_MASK (7 << GTIM_CCMR1_OC2M_SHIFT) - /* (See common CCMR Output Compare Mode definitions below) */ -#define GTIM_CCMR1_OC2CE (1 << 15) /* Bit 15: Output Compare 2 Clear Enable (TIM3 only) */ -#define GTIM_CCMR1_OC1M (1 << 16) /* Bit 16: Output Compare 1 mode - bit 3 */ -#define GTIM_CCMR1_OC2M (1 << 24) /* Bit 24: Output Compare 2 mode - bit 3 (TIM3,15 only) */ - -/* Common CCMR (unshifted) Capture/Compare Selection bit-field definitions */ - -#define GTIM_CCMR_CCS_CCOUT (0) /* 00: CCx channel output */ -#define GTIM_CCMR_CCS_CCIN1 (1) /* 01: CCx channel input, ICx is TIx */ -#define GTIM_CCMR_CCS_CCIN2 (2) /* 10: CCx channel input, ICx is TIy */ -#define GTIM_CCMR_CCS_CCINTRC (3) /* 11: CCx channel input, ICx is TRC */ - -/* Common CCMR (unshifted) Compare Mode bit field definitions */ - -#define GTIM_CCMR_MODE_FRZN (0) /* 000: Frozen */ -#define GTIM_CCMR_MODE_CHACT (1) /* 001: Channel x active on match */ -#define GTIM_CCMR_MODE_CHINACT (2) /* 010: Channel x inactive on match */ -#define GTIM_CCMR_MODE_OCREFTOG (3) /* 011: OCxREF toggle ATIM_CNT=ATIM_CCRx */ -#define GTIM_CCMR_MODE_OCREFLO (4) /* 100: OCxREF forced low */ -#define GTIM_CCMR_MODE_OCREFHI (5) /* 101: OCxREF forced high */ -#define GTIM_CCMR_MODE_PWM1 (6) /* 110: PWM mode 1 */ -#define GTIM_CCMR_MODE_PWM2 (7) /* 111: PWM mode 2 */ -#define GTIM_CCMR_MODE_RETRIG1 (8) /* 1000: Retrigerrable OPM mode 1 (TIM3,15 only) */ -#define GTIM_CCMR_MODE_RETRIG2 (9) /* 1001: Retrigerrable OPM mode 2 (TIM3,15 only) */ -#define GTIM_CCMR_MODE_COMBINED1 (12) /* 1100: Combined PWM mode 1 (TIM3,15 only) */ -#define GTIM_CCMR_MODE_COMBINED2 (13) /* 1101: Combined PWM mode 2 (TIM3,15 only) */ -#define GTIM_CCMR_MODE_ASYMMETRIC1 (14) /* 1110: Asymmetric PWM mode 1 (TIM3 only) */ -#define GTIM_CCMR_MODE_ASYMMETRIC2 (15) /* 1111: Asymmetric PWM mode 2 (TIM3 only) */ - -/* Capture/compare mode register 1 - Input capture mode */ - -/* Bits 1-0 - * (Same as Output Compare Mode) - */ -#define GTIM_CCMR1_IC1PSC_SHIFT (2) /* Bits 3-2: Input Capture 1 Prescaler */ -#define GTIM_CCMR1_IC1PSC_MASK (3 << GTIM_CCMR1_IC1PSC_SHIFT) - /* (See common CCMR Input Capture Prescaler definitions below) */ -#define GTIM_CCMR1_IC1F_SHIFT (4) /* Bits 7-4: Input Capture 1 Filter */ -#define GTIM_CCMR1_IC1F_MASK (0x0f << GTIM_CCMR1_IC1F_SHIFT) - /* (See common CCMR Input Capture Filter definitions below) */ - /* Bits 9-8: (Same as Output Compare Mode) (TIM3,15 only) */ -#define GTIM_CCMR1_IC2PSC_SHIFT (10) /* Bits 11-10: Input Capture 2 Prescaler (TIM3,15 only) */ -#define GTIM_CCMR1_IC2PSC_MASK (3 << GTIM_CCMR1_IC2PSC_SHIFT) - /* (See common CCMR Input Capture Prescaler definitions below) */ -#define GTIM_CCMR1_IC2F_SHIFT (12) /* Bits 15-12: Input Capture 2 Filter (TIM3,15 only) */ -#define GTIM_CCMR1_IC2F_MASK (0x0f << GTIM_CCMR1_IC2F_SHIFT) - /* (See common CCMR Input Capture Filter definitions below) */ - -/* Common CCMR (unshifted) Input Capture Prescaler bit-field definitions */ - -#define GTIM_CCMR_ICPSC_NOPSC (0) /* 00: no prescaler, capture each edge */ -#define GTIM_CCMR_ICPSC_EVENTS2 (1) /* 01: capture once every 2 events */ -#define GTIM_CCMR_ICPSC_EVENTS4 (2) /* 10: capture once every 4 events */ -#define GTIM_CCMR_ICPSC_EVENTS8 (3) /* 11: capture once every 8 events */ - -/* Common CCMR (unshifted) Input Capture Filter bit-field definitions */ - -#define GTIM_CCMR_ICF_NOFILT (0) /* 0000: No filter, sampling at fDTS */ -#define GTIM_CCMR_ICF_FCKINT2 (1) /* 0001: fSAMPLING=fCK_INT, N=2 */ -#define GTIM_CCMR_ICF_FCKINT4 (2) /* 0010: fSAMPLING=fCK_INT, N=4 */ -#define GTIM_CCMR_ICF_FCKINT8 (3) /* 0011: fSAMPLING=fCK_INT, N=8 */ -#define GTIM_CCMR_ICF_FDTSd26 (4) /* 0100: fSAMPLING=fDTS/2, N=6 */ -#define GTIM_CCMR_ICF_FDTSd28 (5) /* 0101: fSAMPLING=fDTS/2, N=8 */ -#define GTIM_CCMR_ICF_FDTSd46 (6) /* 0110: fSAMPLING=fDTS/4, N=6 */ -#define GTIM_CCMR_ICF_FDTSd48 (7) /* 0111: fSAMPLING=fDTS/4, N=8 */ -#define GTIM_CCMR_ICF_FDTSd86 (8) /* 1000: fSAMPLING=fDTS/8, N=6 */ -#define GTIM_CCMR_ICF_FDTSd88 (9) /* 1001: fSAMPLING=fDTS/8, N=8 */ -#define GTIM_CCMR_ICF_FDTSd165 (10) /* 1010: fSAMPLING=fDTS/16, N=5 */ -#define GTIM_CCMR_ICF_FDTSd166 (11) /* 1011: fSAMPLING=fDTS/16, N=6 */ -#define GTIM_CCMR_ICF_FDTSd168 (12) /* 1100: fSAMPLING=fDTS/16, N=8 */ -#define GTIM_CCMR_ICF_FDTSd325 (13) /* 1101: fSAMPLING=fDTS/32, N=5 */ -#define GTIM_CCMR_ICF_FDTSd326 (14) /* 1110: fSAMPLING=fDTS/32, N=6 */ -#define GTIM_CCMR_ICF_FDTSd328 (15) /* 1111: fSAMPLING=fDTS/32, N=8 */ - -/* Capture/compare mode register 2 - Output Compare mode (TIM3 only) */ - -#define GTIM_CCMR2_CC3S_SHIFT (0) /* Bits 1-0: Capture/Compare 3 Selection */ -#define GTIM_CCMR2_CC3S_MASK (3 << GTIM_CCMR2_CC3S_SHIFT) - /* (See common CCMR Capture/Compare Selection definitions above) */ -#define GTIM_CCMR2_OC3FE (1 << 2) /* Bit 2: Output Compare 3 Fast enable */ -#define GTIM_CCMR2_OC3PE (1 << 3) /* Bit 3: Output Compare 3 Preload enable */ -#define GTIM_CCMR2_OC3M_SHIFT (4) /* Bits 6-4: Output Compare 3 Mode */ -#define GTIM_CCMR2_OC3M_MASK (7 << GTIM_CCMR2_OC3M_SHIFT) - /* (See common CCMR Output Compare Mode definitions above) */ -#define GTIM_CCMR2_OC3CE (1 << 7) /* Bit 7: Output Compare 3 Clear Enable */ -#define GTIM_CCMR2_CC4S_SHIFT (8) /* Bits 9-8: Capture/Compare 4 Selection */ -#define GTIM_CCMR2_CC4S_MASK (3 << GTIM_CCMR2_CC4S_SHIFT) - /* (See common CCMR Capture/Compare Selection definitions above) */ -#define GTIM_CCMR2_OC4FE (1 << 10) /* Bit 10: Output Compare 4 Fast enable */ -#define GTIM_CCMR2_OC4PE (1 << 11) /* Bit 11: Output Compare 4 Preload enable */ -#define GTIM_CCMR2_OC4M_SHIFT (12) /* Bits 14-12: Output Compare 4 Mode */ -#define GTIM_CCMR2_OC4M_MASK (7 << GTIM_CCMR2_OC4M_SHIFT) - /* (See common CCMR Output Compare Mode definitions above) */ -#define GTIM_CCMR2_OC4CE (1 << 15) /* Bit 15: Output Compare 4 Clear Enable */ - -/* Capture/compare mode register 2 - Input capture mode (TIM3 only) */ - -/* Bits 1-0 - * (Same as Output Compare Mode) - */ -#define GTIM_CCMR2_IC3PSC_SHIFT (2) /* Bits 3-2: Input Capture 3 Prescaler */ -#define GTIM_CCMR2_IC3PSC_MASK (3 << GTIM_CCMR2_IC3PSC_SHIFT) - /* (See common CCMR Input Capture Prescaler definitions below) */ -#define GTIM_CCMR2_IC3F_SHIFT (4) /* Bits 7-4: Input Capture 3 Filter */ -#define GTIM_CCMR2_IC3F_MASK (0x0f << GTIM_CCMR2_IC3F_SHIFT) - /* (See common CCMR Input Capture Filter definitions below) */ - /* Bits 9-8: (Same as Output Compare Mode) */ -#define GTIM_CCMR2_IC4PSC_SHIFT (10) /* Bits 11-10: Input Capture 4 Prescaler */ -#define GTIM_CCMR2_IC4PSC_MASK (3 << GTIM_CCMR2_IC4PSC_SHIFT) - /* (See common CCMR Input Capture Prescaler definitions below) */ -#define GTIM_CCMR2_IC4F_SHIFT (12) /* Bits 15-12: Input Capture 4 Filter */ -#define GTIM_CCMR2_IC4F_MASK (0x0f << GTIM_CCMR2_IC4F_SHIFT) - /* (See common CCMR Input Capture Filter definitions below) */ - -/* Capture/compare enable register */ - -#define GTIM_CCER_CC1E (1 << 0) /* Bit 0: Capture/Compare 1 output enable */ -#define GTIM_CCER_CC1P (1 << 1) /* Bit 1: Capture/Compare 1 output polarity */ -#define GTIM_CCER_CC1NE (1 << 2) /* Bit 2: Capture/Compare 1 complementary output enable (TIM15-17 only) */ -#define GTIM_CCER_CC1NP (1 << 3) /* Bit 3: Capture/Compare 1 output Polarity (TIM3,14-17 only) */ -#define GTIM_CCER_CC2E (1 << 4) /* Bit 4: Capture/Compare 2 output enable (TIM3,15 only) */ -#define GTIM_CCER_CC2P (1 << 5) /* Bit 5: Capture/Compare 2 output polarity (TIM3,15 only) */ -#define GTIM_CCER_CC2NP (1 << 7) /* Bit 7: Capture/Compare 2 output Polarity (TIM3,15 only) */ -#define GTIM_CCER_CC3E (1 << 8) /* Bit 8: Capture/Compare 3 output enable (TIM3 only) */ -#define GTIM_CCER_CC3P (1 << 9) /* Bit 9: Capture/Compare 3 output Polarity (TIM3 only) */ -#define GTIM_CCER_CC3NP (1 << 11) /* Bit 11: Capture/Compare 3 output Polarity (TIM3 only) */ -#define GTIM_CCER_CC4E (1 << 12) /* Bit 12: Capture/Compare 4 output enable (TIM3 only) */ -#define GTIM_CCER_CC4P (1 << 13) /* Bit 13: Capture/Compare 4 output Polarity (TIM3 only) */ -#define GTIM_CCER_CC4NP (1 << 15) /* Bit 15: Capture/Compare 4 output Polarity (TIM3 only) */ -#define GTIM_CCER_CCXBASE(ch) (ch << 2) /* Each channel uses 4-bits */ - -/* 16-bit counter register */ - -#define GTIM_CNT_SHIFT (0) /* Bits 0-15: Timer counter value */ -#define GTIM_CNT_MASK (0xffff << ATIM_CNT_SHIFT) - -/* Repetition counter (TIM15-17 only) */ - -#define GTIM_RCR_REP_SHIFT (0) /* Bits 0-7: Repetition Counter Value */ -#define GTIM_RCR_REP_MASK (0xff << GTIM_RCR_REP_SHIFT) - -#define GTIM_RCR_REP_MAX 255 - -/* Break and dead-time register (TIM15-17 only) */ - -#define GTIM_BDTR_DTG_SHIFT (0) /* Bits 7:0 [7:0]: Dead-Time Generator set-up */ -#define GTIM_BDTR_DTG_MASK (0xff << GTIM_BDTR_DTG_SHIFT) -#define GTIM_BDTR_LOCK_SHIFT (8) /* Bits 9:8 [1:0]: Lock Configuration */ -#define GTIM_BDTR_LOCK_MASK (3 << GTIM_BDTR_LOCK_SHIFT) -# define GTIM_BDTR_LOCKOFF (0 << GTIM_BDTR_LOCK_SHIFT) /* 00: LOCK OFF - No bit is write protected */ -# define GTIM_BDTR_LOCK1 (1 << GTIM_BDTR_LOCK_SHIFT) /* 01: LOCK Level 1 protection */ -# define GTIM_BDTR_LOCK2 (2 << GTIM_BDTR_LOCK_SHIFT) /* 10: LOCK Level 2 protection */ -# define GTIM_BDTR_LOCK3 (3 << GTIM_BDTR_LOCK_SHIFT) /* 11: LOCK Level 3 protection */ - -#define GTIM_BDTR_OSSI (1 << 10) /* Bit 10: Off-State Selection for Idle mode */ -#define GTIM_BDTR_OSSR (1 << 11) /* Bit 11: Off-State Selection for Run mode */ -#define GTIM_BDTR_BKE (1 << 12) /* Bit 12: Break enable */ -#define GTIM_BDTR_BKP (1 << 13) /* Bit 13: Break Polarity */ -#define GTIM_BDTR_AOE (1 << 14) /* Bit 14: Automatic Output enable */ -#define GTIM_BDTR_MOE (1 << 15) /* Bit 15: Main Output enable */ -#define GTIM_BDTR_BKF_SHIFT (16) /* Bits 16-19: Break filter */ -#define GTIM_BDTR_BKF_MASK (0xf << GTIM_BDTR_BKF_SHIFT) -# define GTIM_BDTR_BKF_NOFILT (0 << GTIM_BDTR_BKF_SHIFT) /* 0000: No filter, BRK acts asynchronously */ -# define GTIM_BDTR_BKF_FCKINT2 (1 << GTIM_BDTR_BKF_SHIFT) /* 0001: fSAMPLING=fCK_INT, N=2 */ -# define GTIM_BDTR_BKF_FCKINT4 (2 << GTIM_BDTR_BKF_SHIFT) /* 0010: fSAMPLING=fCK_INT, N=4 */ -# define GTIM_BDTR_BKF_FCKINT8 (3 << GTIM_BDTR_BKF_SHIFT) /* 0011: fSAMPLING=fCK_INT, N=8 */ -# define GTIM_BDTR_BKF_FDTSd26 (4 << GTIM_BDTR_BKF_SHIFT) /* 0100: fSAMPLING=fDTS/2, N=6 */ -# define GTIM_BDTR_BKF_FDTSd28 (5 << GTIM_BDTR_BKF_SHIFT) /* 0101: fSAMPLING=fDTS/2, N=8 */ -# define GTIM_BDTR_BKF_FDTSd36 (6 << GTIM_BDTR_BKF_SHIFT) /* 0110: fSAMPLING=fDTS/4, N=6 */ -# define GTIM_BDTR_BKF_FDTSd38 (7 << GTIM_BDTR_BKF_SHIFT) /* 0111: fSAMPLING=fDTS/4, N=8 */ -# define GTIM_BDTR_BKF_FDTSd86 (8 << GTIM_BDTR_BKF_SHIFT) /* 1000: fSAMPLING=fDTS/8, N=6 */ -# define GTIM_BDTR_BKF_FDTSd88 (9 << GTIM_BDTR_BKF_SHIFT) /* 1001: fSAMPLING=fDTS/8, N=8 */ -# define GTIM_BDTR_BKF_FDTSd165 (10 << GTIM_BDTR_BKF_SHIFT) /* 1010: fSAMPLING=fDTS/16, N=5 */ -# define GTIM_BDTR_BKF_FDTSd166 (11 << GTIM_BDTR_BKF_SHIFT) /* 1011: fSAMPLING=fDTS/16, N=6 */ -# define GTIM_BDTR_BKF_FDTSd168 (12 << GTIM_BDTR_BKF_SHIFT) /* 1100: fSAMPLING=fDTS/16, N=8 */ -# define GTIM_BDTR_BKF_FDTSd325 (13 << GTIM_BDTR_BKF_SHIFT) /* 1101: fSAMPLING=fDTS/32, N=5 */ -# define GTIM_BDTR_BKF_FDTSd326 (14 << GTIM_BDTR_BKF_SHIFT) /* 1110: fSAMPLING=fDTS/32, N=6 */ -# define GTIM_BDTR_BKF_FDTSd328 (15 << GTIM_BDTR_BKF_SHIFT) /* 1111: fSAMPLING=fDTS/32, N=8 */ - -#define GTIM_BDTR_BKDSRM (1 << 26) /* Bit 26: Break disarm */ -#define GTIM_BDTR_BKBID (1 << 28) /* Bit 28: Break bidirectional */ - -/* DMA control register (16-bit TIM3 and TIM15-17) */ - -#define GTIM_DCR_DBA_SHIFT (0) /* Bits 4-0: DMA Base Address */ -#define GTIM_DCR_DBA_MASK (0x1f << GTIM_DCR_DBA_SHIFT) -#define GTIM_DCR_DBL_SHIFT (8) /* Bits 12-8: DMA Burst Length */ -#define GTIM_DCR_DBL_MASK (0x1f << GTIM_DCR_DBL_SHIFT) - -/* Alternate function option register 1 (16-bit TIM15-17 or 32-bit TIM3) */ - -#define GTIM_AF1_BKINE (1 << 0) /* Bit 0: BRK BKIN input enable (TIM15-17 only) */ -#define GTIM_AF1_BKINP (1 << 9) /* Bit 9: BRK BKIN input polarity (TIM15-17 only) */ - -#define GTIM_AF1_ETRSEL_SHIFT (14) /* Bits 14-17: ETR source selection (TIM3 only) */ -#define GTIM_AF1_ETRSEL_MASK (0xf << GTIM_AF1_ETRSEL_SHIFT) -# define GTIM_AF1_ETRLEGACY (0 << GTIM_AF1_ETRSEL_SHIFT) /* 0000: ETR legacy mode */ - -/* Timer input selection register (16-bit TIM14-17 or 32-bit TIM3) */ - -#define GTIM_TISEL_TI1SEL_SHIFT (0) /* Bits 3-0: Selects TI1[0] to TI1[15] input */ -#define GTIM_TISEL_TI1SEL_MASK (0xf << GTIM_TISEL_TI1SEL_SHIFT) -#define GTIM_TISEL_TI2SEL_SHIFT (8) /* Bits 11-8: Selects TI2[0] to TI2[15] input (TIM3,15 only) */ -#define GTIM_TISEL_TI2SEL_MASK (0xf << GTIM_TISEL_TI2SEL_SHIFT) -#define GTIM_TISEL_TI3SEL_SHIFT (16) /* Bits 19-16: Selects TI3[0] to TI3[15] input (TIM3 only) */ -#define GTIM_TISEL_TI3SEL_MASK (0xf << GTIM_TISEL_TI3SEL_SHIFT) -#define GTIM_TISEL_TI4SEL_SHIFT (24) /* Bits 27-24: Selects TI4[0] to TI4[15] input (TIM3 only) */ -#define GTIM_TISEL_TI4SEL_MASK (0xf << GTIM_TISEL_TI4SEL_SHIFT) - -/* Control register 1 */ - -#define BTIM_CR1_CEN (1 << 0) /* Bit 0: Counter enable */ -#define BTIM_CR1_UDIS (1 << 1) /* Bit 1: Update Disable */ -#define BTIM_CR1_URS (1 << 2) /* Bit 2: Update Request Source */ -#define BTIM_CR1_OPM (1 << 3) /* Bit 3: One Pulse Mode */ -#define BTIM_CR1_ARPE (1 << 7) /* Bit 7: Auto-Reload Preload enable */ -#define BTIM_CR1_UIFREMAP (1 << 11) /* Bit 11: UIF status bit remapping */ - -/* Control register 2 */ - -#define BTIM_CR2_MMS_SHIFT (4) /* Bits 6-4: Master Mode Selection */ -#define BTIM_CR2_MMS_MASK (7 << BTIM_CR2_MMS_SHIFT) -# define BTIM_CR2_RESET (0 << BTIM_CR2_MMS_SHIFT) /* 000: Reset */ -# define BTIM_CR2_ENAB (1 << BTIM_CR2_MMS_SHIFT) /* 001: Enable */ -# define BTIM_CR2_UPDT (2 << BTIM_CR2_MMS_SHIFT) /* 010: Update */ - -/* DMA/Interrupt enable register */ - -#define BTIM_DIER_UIE (1 << 0) /* Bit 0: Update interrupt enable */ -#define BTIM_DIER_UDE (1 << 8) /* Bit 8: Update DMA request enable */ - -/* Status register */ - -#define BTIM_SR_UIF (1 << 0) /* Bit 0: Update interrupt flag */ - -/* Event generation register */ - -#define BTIM_EGR_UG (1 << 0) /* Bit 0: Update generation */ - -/* Counter register */ - -#define BTIM_CNT_UIFCPY (1 << 31) /* Bit 31: UIF copy */ - -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_TIM_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32_uart.h b/arch/arm/src/stm32f0l0g0/hardware/stm32_uart.h deleted file mode 100644 index 576fcddc3e3fb..0000000000000 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32_uart.h +++ /dev/null @@ -1,41 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32_uart.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_UART_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_UART_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include "chip.h" - -#if defined(CONFIG_STM32F0L0G0_HAVE_IP_USART_V1) -# include "hardware/stm32_uart_v1.h" -#elif defined(CONFIG_STM32F0L0G0_HAVE_IP_USART_V2) -# include "hardware/stm32_uart_v2.h" -#else -# error "Unsupported STM32 M0 USART" -#endif - -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_UART_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32_uart_v1.h b/arch/arm/src/stm32f0l0g0/hardware/stm32_uart_v1.h deleted file mode 100644 index 41bc90b3ae54f..0000000000000 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32_uart_v1.h +++ /dev/null @@ -1,303 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32_uart_v1.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_UART_V1_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_UART_V1_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include "chip.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Register Offsets *********************************************************/ - -#define STM32_USART_CR1_OFFSET 0x0000 /* Control register 1 */ -#define STM32_USART_CR2_OFFSET 0x0004 /* Control register 2 */ -#define STM32_USART_CR3_OFFSET 0x0008 /* Control register 3 */ -#define STM32_USART_BRR_OFFSET 0x000c /* Baud Rate register */ -#define STM32_USART_GTPR_OFFSET 0x0010 /* Guard time and prescaler register */ -#define STM32_USART_RTOR_OFFSET 0x0014 /* Receiver timeout register */ -#define STM32_USART_RQR_OFFSET 0x0018 /* Request register */ -#define STM32_USART_ISR_OFFSET 0x001c /* Interrupot and status register */ -#define STM32_USART_ICR_OFFSET 0x0020 /* Interrupt flag clear register */ -#define STM32_USART_RDR_OFFSET 0x0024 /* Receive Data register */ -#define STM32_USART_TDR_OFFSET 0x0028 /* Transmit Data register */ - -/* Register Addresses *******************************************************/ - -#if STM32_NUSART > 0 -# define STM32_USART1_CR1 (STM32_USART1_BASE + STM32_USART_CR1_OFFSET) -# define STM32_USART1_CR2 (STM32_USART1_BASE + STM32_USART_CR2_OFFSET) -# define STM32_USART1_CR3 (STM32_USART1_BASE + STM32_USART_CR3_OFFSET) -# define STM32_USART1_BRR (STM32_USART1_BASE + STM32_USART_BRR_OFFSET) -# define STM32_USART1_GTPR (STM32_USART1_BASE + STM32_USART_GTPR_OFFSET) -# define STM32_USART1_RTOR (STM32_USART1_BASE + STM32_USART_RTOR_OFFSET) -# define STM32_USART1_RQR (STM32_USART1_BASE + STM32_USART_RQR_OFFSET) -# define STM32_USART1_ISR (STM32_USART1_BASE + STM32_USART_ISR_OFFSET) -# define STM32_USART1_ICR (STM32_USART1_BASE + STM32_USART_ICR_OFFSET) -# define STM32_USART1_RDR (STM32_USART1_BASE + STM32_USART_RDR_OFFSET) -# define STM32_USART1_TDR (STM32_USART1_BASE + STM32_USART_TDR_OFFSET) -#endif - -#if STM32_NUSART > 1 -# define STM32_USART2_CR1 (STM32_USART2_BASE + STM32_USART_CR1_OFFSET) -# define STM32_USART2_CR2 (STM32_USART2_BASE + STM32_USART_CR2_OFFSET) -# define STM32_USART2_CR3 (STM32_USART2_BASE + STM32_USART_CR3_OFFSET) -# define STM32_USART2_BRR (STM32_USART2_BASE + STM32_USART_BRR_OFFSET) -# define STM32_USART2_GTPR (STM32_USART2_BASE + STM32_USART_GTPR_OFFSET) -# define STM32_USART2_RTOR (STM32_USART2_BASE + STM32_USART_RTOR_OFFSET) -# define STM32_USART2_RQR (STM32_USART2_BASE + STM32_USART_RQR_OFFSET) -# define STM32_USART2_ISR (STM32_USART2_BASE + STM32_USART_ISR_OFFSET) -# define STM32_USART2_ICR (STM32_USART2_BASE + STM32_USART_ICR_OFFSET) -# define STM32_USART2_RDR (STM32_USART2_BASE + STM32_USART_RDR_OFFSET) -# define STM32_USART2_TDR (STM32_USART2_BASE + STM32_USART_TDR_OFFSET) -#endif - -#if STM32_NUSART > 2 -# define STM32_USART3_CR1 (STM32_USART3_BASE + STM32_USART_CR1_OFFSET) -# define STM32_USART3_CR2 (STM32_USART3_BASE + STM32_USART_CR2_OFFSET) -# define STM32_USART3_CR3 (STM32_USART3_BASE + STM32_USART_CR3_OFFSET) -# define STM32_USART3_BRR (STM32_USART3_BASE + STM32_USART_BRR_OFFSET) -# define STM32_USART3_GTPR (STM32_USART3_BASE + STM32_USART_GTPR_OFFSET) -# define STM32_USART3_RTOR (STM32_USART3_BASE + STM32_USART_RTOR_OFFSET) -# define STM32_USART3_RQR (STM32_USART3_BASE + STM32_USART_RQR_OFFSET) -# define STM32_USART3_ISR (STM32_USART3_BASE + STM32_USART_ISR_OFFSET) -# define STM32_USART3_ICR (STM32_USART3_BASE + STM32_USART_ICR_OFFSET) -# define STM32_USART3_RDR (STM32_USART3_BASE + STM32_USART_RDR_OFFSET) -# define STM32_USART3_TDR (STM32_USART3_BASE + STM32_USART_TDR_OFFSET) -#endif - -#if STM32_NUSART > 3 -# define STM32_USART4_CR1 (STM32_USART4_BASE + STM32_USART_CR1_OFFSET) -# define STM32_USART4_CR2 (STM32_USART4_BASE + STM32_USART_CR2_OFFSET) -# define STM32_USART4_CR3 (STM32_USART4_BASE + STM32_USART_CR3_OFFSET) -# define STM32_USART4_BRR (STM32_USART4_BASE + STM32_USART_BRR_OFFSET) -# define STM32_USART4_GTPR (STM32_USART4_BASE + STM32_USART_GTPR_OFFSET) -# define STM32_USART4_RTOR (STM32_USART4_BASE + STM32_USART_RTOR_OFFSET) -# define STM32_USART4_RQR (STM32_USART4_BASE + STM32_USART_RQR_OFFSET) -# define STM32_USART4_ISR (STM32_USART4_BASE + STM32_USART_ISR_OFFSET) -# define STM32_USART4_ICR (STM32_USART4_BASE + STM32_USART_ICR_OFFSET) -# define STM32_USART4_RDR (STM32_USART4_BASE + STM32_USART_RDR_OFFSET) -# define STM32_USART4_TDR (STM32_USART4_BASE + STM32_USART_TDR_OFFSET) -#endif - -#if STM32_NUSART > 4 -# define STM32_USART5_CR1 (STM32_USART5_BASE + STM32_USART_CR1_OFFSET) -# define STM32_USART5_CR2 (STM32_USART5_BASE + STM32_USART_CR2_OFFSET) -# define STM32_USART5_CR3 (STM32_USART5_BASE + STM32_USART_CR3_OFFSET) -# define STM32_USART5_BRR (STM32_USART5_BASE + STM32_USART_BRR_OFFSET) -# define STM32_USART5_GTPR (STM32_USART5_BASE + STM32_USART_GTPR_OFFSET) -# define STM32_USART5_RTOR (STM32_USART5_BASE + STM32_USART_RTOR_OFFSET) -# define STM32_USART5_RQR (STM32_USART5_BASE + STM32_USART_RQR_OFFSET) -# define STM32_USART5_ISR (STM32_USART5_BASE + STM32_USART_ISR_OFFSET) -# define STM32_USART5_ICR (STM32_USART5_BASE + STM32_USART_ICR_OFFSET) -# define STM32_USART5_RDR (STM32_USART5_BASE + STM32_USART_RDR_OFFSET) -# define STM32_USART5_TDR (STM32_USART5_BASE + STM32_USART_TDR_OFFSET) -#endif - -/* Register Bitfield Definitions ********************************************/ - -/* Control register 1 */ - -#define USART_CR1_UE (1 << 0) /* Bit 0: USART Enable */ -#define USART_CR1_UESM (1 << 1) /* Bit 1: USART Enable in Stop mode*/ -#define USART_CR1_RE (1 << 2) /* Bit 2: Receiver Enable */ -#define USART_CR1_TE (1 << 3) /* Bit 3: Transmitter Enable */ -#define USART_CR1_IDLEIE (1 << 4) /* Bit 4: IDLE Interrupt Enable */ -#define USART_CR1_RXNEIE (1 << 5) /* Bit 5: RXNE Interrupt Enable */ -#define USART_CR1_TCIE (1 << 6) /* Bit 6: Transmission Complete Interrupt Enable */ -#define USART_CR1_TXEIE (1 << 7) /* Bit 7: TXE Interrupt Enable */ -#define USART_CR1_PEIE (1 << 8) /* Bit 8: PE Interrupt Enable */ -#define USART_CR1_PS (1 << 9) /* Bit 9: Parity Selection */ -#define USART_CR1_PCE (1 << 10) /* Bit 10: Parity Control Enable */ -#define USART_CR1_WAKE (1 << 11) /* Bit 11: Wakeup method */ -#define USART_CR1_M0 (1 << 12) /* Bit 12: Word length */ -#define USART_CR1_MME (1 << 13) /* Bit 13: Mute mode enable */ -#define USART_CR1_CMIE (1 << 14) /* Bit 14: Character match interrupt enable */ -#define USART_CR1_OVER8 (1 << 15) /* Bit 15: Oversampling mode */ - -#define USART_CR1_DEDT_SHIFT (16) /* Bits 16..20 DE deactivation delay */ -#define USART_CR1_DEDT_MASK (0x1f << USART_CR1_DEDT_SHIFT) - -#define USART_CR1_DEAT_SHIFT (21) /* Bits 21..25 DE activation delay */ -#define USART_CR1_DEAT_MASK (0x1f << USART_CR1_DEAT_SHIFT) - -#define USART_CR1_RTOIE (1 << 26) /* Bit 26: Receiver timeout interrupt enable */ -#define USART_CR1_EOBIE (1 << 27) /* Bit 27: End of block interrupt enable */ -#define USART_CR1_M1 (1 << 28) /* Bit 12: word length */ - -#define USART_CR1_ALLINTS (USART_CR1_IDLEIE | USART_CR1_RXNEIE | \ - USART_CR1_TCIE | USART_CR1_TXEIE | \ - USART_CR1_PEIE | USART_CR1_CMIE| \ - USART_CR1_RTOIE | USART_CR1_EOBIE) - -/* Control register 2 */ - -#define USART_CR2_ADDM7 (1 << 4) /* Bit 4: */ -#define USART_CR2_LBDL (1 << 5) /* Bit 5: LIN Break Detection Length */ -#define USART_CR2_LBDIE (1 << 6) /* Bit 6: LIN Break Detection Interrupt Enable */ -#define USART_CR2_LBCL (1 << 8) /* Bit 8: Last Bit Clock pulse */ -#define USART_CR2_CPHA (1 << 9) /* Bit 9: Clock Phase */ -#define USART_CR2_CPOL (1 << 10) /* Bit 10: Clock Polarity */ -#define USART_CR2_CLKEN (1 << 11) /* Bit 11: Clock Enable */ - -#define USART_CR2_STOP_SHIFT (12) /* Bits 13-12: STOP bits */ -#define USART_CR2_STOP_MASK (3 << USART_CR2_STOP_SHIFT) -# define USART_CR2_STOP1 (0 << USART_CR2_STOP_SHIFT) /* 00: 1 Stop bit */ -# define USART_CR2_STOP0p5 (1 << USART_CR2_STOP_SHIFT) /* 01: 0.5 Stop bit */ -# define USART_CR2_STOP2 (2 << USART_CR2_STOP_SHIFT) /* 10: 2 Stop bits */ -# define USART_CR2_STOP1p5 (3 << USART_CR2_STOP_SHIFT) /* 11: 1.5 Stop bit */ - -#define USART_CR2_LINEN (1 << 14) /* Bit 14: LIN mode enable */ -#define USART_CR2_SWAP (1 << 15) /* Bit 15: Swap TX/RX pins */ -#define USART_CR2_RXINV (1 << 16) /* Bit 16: RX pin active level inversion */ -#define USART_CR2_TXINV (1 << 17) /* Bit 17: TX pin active level inversion */ -#define USART_CR2_DATAINV (1 << 18) /* Bit 18: Binary data inversion */ -#define USART_CR2_MSBFIRST (1 << 19) /* Bit 19: Most significant bit first */ -#define USART_CR2_ABREN (1 << 20) /* Bit 20: Auto Baud rate enable */ - -#define USART_CR2_ABRMOD_SHIFT (21) /* Bits 21-22: Autobaud rate mode*/ -#define USART_CR2_ABRMOD_MASK (3 << USART_CR2_ABRMOD_SHIFT) -#define USART_CR2_ABRMOD_START (0 << USART_CR2_ABRMOD_SHIFT) /* 00: Start bit */ -#define USART_CR2_ABRMOD_EDGES (1 << USART_CR2_ABRMOD_SHIFT) /* 01: Falling-to-falling edge -> frame must start with 10xxxxxx */ -#define USART_CR2_ABRMOD_7F (2 << USART_CR2_ABRMOD_SHIFT) /* 10: 0x7F */ -#define USART_CR2_ABRMOD_55 (3 << USART_CR2_ABRMOD_SHIFT) /* 11: 0x55 */ - -#define USART_CR2_RTOEN (1 << 23) /* Bit 23: Receiver timeout enable */ - -#define USART_CR2_ADD_SHIFT (24) /* Bits 24-31: Address of the USART node */ -#define USART_CR2_ADD_MASK (0xff << USART_CR2_ADD_SHIFT) - -/* Control register 3 */ - -#define USART_CR3_EIE (1 << 0) /* Bit 0: Error Interrupt Enable */ -#define USART_CR3_IREN (1 << 1) /* Bit 1: IrDA mode Enable */ -#define USART_CR3_IRLP (1 << 2) /* Bit 2: IrDA Low-Power */ -#define USART_CR3_HDSEL (1 << 3) /* Bit 3: Half-Duplex Selection */ -#define USART_CR3_NACK (1 << 4) /* Bit 4: Smartcard NACK enable */ -#define USART_CR3_SCEN (1 << 5) /* Bit 5: Smartcard mode enable */ -#define USART_CR3_DMAR (1 << 6) /* Bit 6: DMA Enable Receiver */ -#define USART_CR3_DMAT (1 << 7) /* Bit 7: DMA Enable Transmitter */ -#define USART_CR3_RTSE (1 << 8) /* Bit 8: RTS Enable */ -#define USART_CR3_CTSE (1 << 9) /* Bit 9: CTS Enable */ -#define USART_CR3_CTSIE (1 << 10) /* Bit 10: CTS Interrupt Enable */ -#define USART_CR3_ONEBIT (1 << 11) /* Bit 11: One sample bit method Enable */ -#define USART_CR3_OVRDIS (1 << 12) /* Bit 12: Overrun Disable */ -#define USART_CR3_DDRE (1 << 13) /* Bit 13: DMA disable on Reception error */ -#define USART_CR3_DEM (1 << 14) /* Bit 14: Driver Enable mode */ -#define USART_CR3_DEP (1 << 15) /* Bit 15: Driver Enable polarity selection */ -#define USART_CR3_SCARCNT_SHIFT (17) /* Bits 17-19: Smart card auto retry count */ -#define USART_CR3_SCARCNT_MASK (7 << USART_CR3_SCARCNT_SHIFT) -#define USART_CR3_WUS_SHIFT (20) /* Bits 20-21: Wakeup from Stop mode interrupt flag selection */ -#define USART_CR3_WUS_MASK (3 << USART_CR3_WUS_SHIFT) -#define USART_CR3_WUS_ADDRESS (0 << USART_CR3_WUS_SHIFT) /* 00: WUF active on address match */ -#define USART_CR3_WUS_START (2 << USART_CR3_WUS_SHIFT) /* 10: WUF active on Start bit detection */ -#define USART_CR3_WUS_RXNE (3 << USART_CR3_WUS_SHIFT) /* 11: WUF active on RXNE */ - -#define USART_CR3_WUFIE (1 << 22) /* Bit 22: Wakeup from Stop mode interrupt enable */ - -/* Baud Rate Register */ - -#define USART_BRR_FRAC_SHIFT (0) /* Bits 3-0: fraction of USARTDIV */ -#define USART_BRR_FRAC_MASK (0x0f << USART_BRR_FRAC_SHIFT) -#define USART_BRR_MANT_SHIFT (4) /* Bits 15-4: mantissa of USARTDIV */ -#define USART_BRR_MANT_MASK (0x0fff << USART_BRR_MANT_SHIFT) - -/* Guard time and prescaler register */ - -#define USART_GTPR_PSC_SHIFT (0) /* Bits 0-7: Prescaler value */ -#define USART_GTPR_PSC_MASK (0xff << USART_GTPR_PSC_SHIFT) -#define USART_GTPR_GT_SHIFT (8) /* Bits 8-15: Guard time value */ -#define USART_GTPR_GT_MASK (0xff << USART_GTPR_GT_SHIFT) - -/* Receiver timeout register */ - -#define USART_RTOR_RTO_SHIFT (0) /* Bits 0-23: Receiver timeout value */ -#define USART_RTOR_RTO_MASK (0xffffff << USART_RTOR_RTO_SHIFT) -#define USART_RTOR_BLEN_SHIFT (24) /* Bits 24-31: Block length */ -#define USART_RTOR_BLEN_MASK (0xff << USART_RTOR_BLEN_SHIFT) - -/* Request Register */ - -#define USART_RQR_ABRRQ (1 << 0) /* Bit 0: Auto baud rate request */ -#define USART_RQR_SBKRQ (1 << 1) /* Bit 1: Send Break */ -#define USART_RQR_MMRQ (1 << 2) /* Bit 2: Mute mode request */ -#define USART_RQR_RXFRQ (1 << 3) /* Bit 3: Receive data flush request */ -#define USART_RQR_TXFRQ (1 << 4) /* Bit 4: Transmit data flush request */ - -/* Interrupt and Status register */ - -#define USART_ISR_PE (1 << 0) /* Bit 0: Parity Error */ -#define USART_ISR_FE (1 << 1) /* Bit 1: Framing Error */ -#define USART_ISR_NF (1 << 2) /* Bit 2: Noise Error Flag */ -#define USART_ISR_ORE (1 << 3) /* Bit 3: OverRun Error */ -#define USART_ISR_IDLE (1 << 4) /* Bit 4: IDLE line detected */ -#define USART_ISR_RXNE (1 << 5) /* Bit 5: Read Data Register Not Empty */ -#define USART_ISR_TC (1 << 6) /* Bit 6: Transmission Complete */ -#define USART_ISR_TXE (1 << 7) /* Bit 7: Transmit Data Register Empty */ -#define USART_ISR_LBDF (1 << 8) /* Bit 8: LIN Break Detection Flag */ -#define USART_ISR_CTSIF (1 << 9) /* Bit 9: CTS Interrupt flag */ -#define USART_ISR_CTS (1 << 10) /* Bit 9: CTS Flag */ -#define USART_ISR_RTOF (1 << 11) /* Bit 10: Receiver timeout Flag */ -#define USART_ISR_EOBF (1 << 12) /* Bit 11: End of block Flag */ -#define USART_ISR_ABRE (1 << 13) /* Bit 12: Auto baud rate Error */ -#define USART_ISR_ABRF (1 << 15) /* Bit 14: Auto baud rate Flag */ -#define USART_ISR_BUSY (1 << 16) /* Bit 15: Busy Flag */ -#define USART_ISR_CMF (1 << 17) /* Bit 16: Character match Flag */ -#define USART_ISR_SBKF (1 << 18) /* Bit 17: Send break Flag */ -#define USART_ISR_RWU (1 << 19) /* Bit 18: Receiver wakeup from Mute mode */ -#define USART_ISR_WUF (1 << 20) /* Bit 19: Wakeup from Stop mode Flag */ -#define USART_ISR_TEACK (1 << 21) /* Bit 20: Transmit enable acknowledge Flag */ -#define USART_ISR_REACK (1 << 22) /* Bit 21: Receive enable acknowledge Flag */ - -/* ICR */ - -#define USART_ICR_PECF (1 << 0) /* Bit 0: Parity error clear flag */ -#define USART_ICR_FECF (1 << 1) /* Bit 1: Framing error clear flag */ -#define USART_ICR_NCF (1 << 2) /* Bit 2: Noise detected clear flag */ -#define USART_ICR_ORECF (1 << 3) /* Bit 3: Overrun error clear flag */ -#define USART_ICR_IDLECF (1 << 4) /* Bit 4: Idle line detected clear flag */ -#define USART_ICR_TCCF (1 << 6) /* Bit 6: Transmission complete clear flag */ -#define USART_ICR_LBDCF (1 << 8) /* Bit 8: LIN break detection clear flag */ -#define USART_ICR_CTSCF (1 << 9) /* Bit 9: CTS clear flag */ -#define USART_ICR_RTOCF (1 << 11) /* Bit 11: Receiver timeout clear flag */ -#define USART_ICR_EOBCF (1 << 12) /* Bit 12: End of block clear flag */ -#define USART_ICR_CMCF (1 << 17) /* Bit 17: Character match clear flag */ -#define USART_ICR_WUCF (1 << 20) /* Bit 20: Wakeup from Stop mode clear flag */ - -/* Receive Data register */ - -#define USART_RDR_SHIFT (0) /* Bits 8:0: Data value */ -#define USART_RDR_MASK (0xff << USART_RDR_SHIFT) - -/* Transmit Data register */ - -#define USART_TDR_SHIFT (0) /* Bits 8:0: Data value */ -#define USART_TDR_MASK (0xff << USART_TDR_SHIFT) - -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_UART_V1_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32_uart_v2.h b/arch/arm/src/stm32f0l0g0/hardware/stm32_uart_v2.h deleted file mode 100644 index 82dbcfdcc2f70..0000000000000 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32_uart_v2.h +++ /dev/null @@ -1,352 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32_uart_v2.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_UART_V2_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_UART_V2_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include "chip.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Register Offsets *********************************************************/ - -#define STM32_USART_CR1_OFFSET 0x0000 /* Control register 1 */ -#define STM32_USART_CR2_OFFSET 0x0004 /* Control register 2 */ -#define STM32_USART_CR3_OFFSET 0x0008 /* Control register 3 */ -#define STM32_USART_BRR_OFFSET 0x000c /* Baud Rate Register (32-bits) */ -#define STM32_USART_GTPR_OFFSET 0x0010 /* Guard time and prescaler register */ -#define STM32_USART_RTOR_OFFSET 0x0014 /* Receiver timeout register */ -#define STM32_USART_RQR_OFFSET 0x0018 /* Request register */ -#define STM32_USART_ISR_OFFSET 0x001c /* Interrupt & status register */ -#define STM32_USART_ICR_OFFSET 0x0020 /* Interrupt flag clear register */ -#define STM32_USART_RDR_OFFSET 0x0024 /* Receive data register */ -#define STM32_USART_TDR_OFFSET 0x0028 /* Transmit data register */ -#define STM32_USART_PRESC_OFFSET 0x002c /* Prescaler register */ - -/* Register Addresses *******************************************************/ - -#if STM32_NUSART > 0 -# define STM32_USART1_CR1 (STM32_USART1_BASE + STM32_USART_CR1_OFFSET) -# define STM32_USART1_CR2 (STM32_USART1_BASE + STM32_USART_CR2_OFFSET) -# define STM32_USART1_CR3 (STM32_USART1_BASE + STM32_USART_CR3_OFFSET) -# define STM32_USART1_BRR (STM32_USART1_BASE + STM32_USART_BRR_OFFSET) -# define STM32_USART1_GTPR (STM32_USART1_BASE + STM32_USART_GTPR_OFFSET) -# define STM32_USART1_RTOR (STM32_USART1_BASE + STM32_USART_RTOR_OFFSET) -# define STM32_USART1_RQR (STM32_USART1_BASE + STM32_USART_RQR_OFFSET) -# define STM32_USART1_GTPR (STM32_USART1_BASE + STM32_USART_GTPR_OFFSET) -# define STM32_USART1_ISR (STM32_USART1_BASE + STM32_USART_ISR_OFFSET) -# define STM32_USART1_ICR (STM32_USART1_BASE + STM32_USART_ICR_OFFSET) -# define STM32_USART1_RDR (STM32_USART1_BASE + STM32_USART_RDR_OFFSET) -# define STM32_USART1_TDR (STM32_USART1_BASE + STM32_USART_TDR_OFFSET) -# define STM32_USART1_PRESC (STM32_USART1_BASE + STM32_USART_PRESC_OFFSET) -#endif - -#if STM32_NUSART > 1 -# define STM32_USART2_CR1 (STM32_USART2_BASE + STM32_USART_CR1_OFFSET) -# define STM32_USART2_CR2 (STM32_USART2_BASE + STM32_USART_CR2_OFFSET) -# define STM32_USART2_CR3 (STM32_USART2_BASE + STM32_USART_CR3_OFFSET) -# define STM32_USART2_BRR (STM32_USART2_BASE + STM32_USART_BRR_OFFSET) -# define STM32_USART2_GTPR (STM32_USART2_BASE + STM32_USART_GTPR_OFFSET) -# define STM32_USART2_RTOR (STM32_USART2_BASE + STM32_USART_RTOR_OFFSET) -# define STM32_USART2_RQR (STM32_USART2_BASE + STM32_USART_RQR_OFFSET) -# define STM32_USART2_GTPR (STM32_USART2_BASE + STM32_USART_GTPR_OFFSET) -# define STM32_USART2_ISR (STM32_USART2_BASE + STM32_USART_ISR_OFFSET) -# define STM32_USART2_ICR (STM32_USART2_BASE + STM32_USART_ICR_OFFSET) -# define STM32_USART2_RDR (STM32_USART2_BASE + STM32_USART_RDR_OFFSET) -# define STM32_USART2_TDR (STM32_USART2_BASE + STM32_USART_TDR_OFFSET) -# define STM32_USART2_PRESC (STM32_USART2_BASE + STM32_USART_PRESC_OFFSET) -#endif - -#if STM32_NUSART > 2 -# define STM32_USART3_CR1 (STM32_USART3_BASE + STM32_USART_CR1_OFFSET) -# define STM32_USART3_CR2 (STM32_USART3_BASE + STM32_USART_CR2_OFFSET) -# define STM32_USART3_CR3 (STM32_USART3_BASE + STM32_USART_CR3_OFFSET) -# define STM32_USART3_BRR (STM32_USART3_BASE + STM32_USART_BRR_OFFSET) -# define STM32_USART3_GTPR (STM32_USART3_BASE + STM32_USART_GTPR_OFFSET) -# define STM32_USART3_RTOR (STM32_USART3_BASE + STM32_USART_RTOR_OFFSET) -# define STM32_USART3_RQR (STM32_USART3_BASE + STM32_USART_RQR_OFFSET) -# define STM32_USART3_GTPR (STM32_USART3_BASE + STM32_USART_GTPR_OFFSET) -# define STM32_USART3_ISR (STM32_USART3_BASE + STM32_USART_ISR_OFFSET) -# define STM32_USART3_ICR (STM32_USART3_BASE + STM32_USART_ICR_OFFSET) -# define STM32_USART3_RDR (STM32_USART3_BASE + STM32_USART_RDR_OFFSET) -# define STM32_USART3_TDR (STM32_USART3_BASE + STM32_USART_TDR_OFFSET) -# define STM32_USART3_PRESC (STM32_USART3_BASE + STM32_USART_PRESC_OFFSET) -#endif - -#if STM32_NUSART > 3 -# define STM32_USART4_CR1 (STM32_USART4_BASE + STM32_USART_CR1_OFFSET) -# define STM32_USART4_CR2 (STM32_USART4_BASE + STM32_USART_CR2_OFFSET) -# define STM32_USART4_CR3 (STM32_USART4_BASE + STM32_USART_CR3_OFFSET) -# define STM32_USART4_BRR (STM32_USART4_BASE + STM32_USART_BRR_OFFSET) -# define STM32_USART4_GTPR (STM32_USART4_BASE + STM32_USART_GTPR_OFFSET) -# define STM32_USART4_RTOR (STM32_USART4_BASE + STM32_USART_RTOR_OFFSET) -# define STM32_USART4_RQR (STM32_USART4_BASE + STM32_USART_RQR_OFFSET) -# define STM32_USART4_GTPR (STM32_USART4_BASE + STM32_USART_GTPR_OFFSET) -# define STM32_USART4_ISR (STM32_USART4_BASE + STM32_USART_ISR_OFFSET) -# define STM32_USART4_ICR (STM32_USART4_BASE + STM32_USART_ICR_OFFSET) -# define STM32_USART4_RDR (STM32_USART4_BASE + STM32_USART_RDR_OFFSET) -# define STM32_USART4_TDR (STM32_USART4_BASE + STM32_USART_TDR_OFFSET) -# define STM32_USART4_PRESC (STM32_USART4_BASE + STM32_USART_PRESC_OFFSET) -#endif - -/* Register Bitfield Definitions ********************************************/ - -/* Control register 1 */ - -#define USART_CR1_UE (1 << 0) /* Bit 0: USART enable */ -#define USART_CR1_UESM (1 << 1) /* Bit 1: USART enable in low-power mode */ -#define USART_CR1_RE (1 << 2) /* Bit 2: Receiver Enable */ -#define USART_CR1_TE (1 << 3) /* Bit 3: Transmitter Enable */ -#define USART_CR1_IDLEIE (1 << 4) /* Bit 4: IDLE Interrupt Enable */ -#define USART_CR1_RXNEIE (1 << 5) /* Bit 5: RXNE Interrupt Enable */ -#define USART_CR1_TCIE (1 << 6) /* Bit 6: Transmission Complete Interrupt Enable */ -#define USART_CR1_TXEIE (1 << 7) /* Bit 7: TXE Interrupt Enable */ -#define USART_CR1_PEIE (1 << 8) /* Bit 8: PE Interrupt Enable */ -#define USART_CR1_PS (1 << 9) /* Bit 9: Parity Selection */ -#define USART_CR1_PCE (1 << 10) /* Bit 10: Parity Control Enable */ -#define USART_CR1_WAKE (1 << 11) /* Bit 11: Receiver wakeup method */ -#define USART_CR1_M0 (1 << 12) /* Bit 12: Word length, bit 0 */ -#define USART_CR1_MME (1 << 13) /* Bit 13: Mute mode enable */ -#define USART_CR1_CMIE (1 << 14) /* Bit 14: Character match interrupt enable */ -#define USART_CR1_OVER8 (1 << 15) /* Bit 15: Oversampling mode */ -#define USART_CR1_DEDT_SHIFT (16) /* Bits 16-20: Driver Enable deassertion time */ -#define USART_CR1_DEDT_MASK (31 << USART_CR1_DEDT_SHIFT) -# define USART_CR1_DEDT(n) ((uint32_t)(n) << USART_CR1_DEDT_SHIFT) -#define USART_CR1_DEAT_SHIFT (21) /* Bits 21-25: Driver Enable assertion time */ -#define USART_CR1_DEAT_MASK (31 << USART_CR1_DEAT_SHIFT) -# define USART_CR1_DEAT(n) ((uint32_t)(n) << USART_CR1_DEAT_SHIFT) -#define USART_CR1_RTOIE (1 << 26) /* Bit 26: Receiver timeout interrupt enable */ -#define USART_CR1_EOBIE (1 << 27) /* Bit 27: End of Block interrupt enable */ -#define USART_CR1_M1 (1 << 28) /* Bit 28: Word length, bit 1 */ -#define USART_CR1_FIFOEN (1 << 29) /* Bit 29: FIFO mode enable */ -#define USART_CR1_TXFEIE (1 << 30) /* Bit 30: TXFIFO empty interrupt enable */ -#define USART_CR1_RXFFIE (1 << 31) /* Bit 31: RXFIFO Full interrupt enable */ - -#define USART_CR1_ALLINTS \ - (USART_CR1_IDLEIE | USART_CR1_RXNEIE | USART_CR1_TCIE | USART_CR1_TXEIE |\ - USART_CR1_PEIE | USART_CR1_CMIE |USART_CR1_RTOIE | USART_CR1_EOBIE |\ - USART_CR1_TXFEIE | USART_CR1_RXFFIE) - -/* Control register 2 */ - -#define USART_CR2_SLVEN (1 << 0) /* Bit 0: Synchronous Slave mode enable */ -#define USART_CR2_DISNSS (1 << 3) /* Bit 3: Ignore NSS pin input */ -#define USART_CR2_ADDM7 (1 << 4) /* Bit 4: 7-/4-bit Address Detection */ -#define USART_CR2_LBDL (1 << 5) /* Bit 5: LIN Break Detection Length */ -#define USART_CR2_LBDIE (1 << 6) /* Bit 6: LIN Break Detection Interrupt Enable */ -#define USART_CR2_LBCL (1 << 8) /* Bit 8: Last Bit Clock pulse */ -#define USART_CR2_CPHA (1 << 9) /* Bit 9: Clock Phase */ -#define USART_CR2_CPOL (1 << 10) /* Bit 10: Clock Polarity */ -#define USART_CR2_CLKEN (1 << 11) /* Bit 11: Clock Enable */ -#define USART_CR2_STOP_SHIFT (12) /* Bits 13-12: STOP bits */ -#define USART_CR2_STOP_MASK (3 << USART_CR2_STOP_SHIFT) -# define USART_CR2_STOP1 (0 << USART_CR2_STOP_SHIFT) /* 00: 1 Stop bit */ -# define USART_CR2_STOP2 (2 << USART_CR2_STOP_SHIFT) /* 10: 2 Stop bits */ -# define USART_CR2_STOP1p5 (3 << USART_CR2_STOP_SHIFT) /* 11: 1.5 Stop bit */ - -#define USART_CR2_LINEN (1 << 14) /* Bit 14: LIN mode enable */ -#define USART_CR2_SWAP (1 << 15) /* Bit 15: Swap TX/RX pins */ -#define USART_CR2_RXINV (1 << 16) /* Bit 16: RX pin active level inversion */ -#define USART_CR2_TXINV (1 << 17) /* Bit 17: TX pin active level inversion */ -#define USART_CR2_DATAINV (1 << 18) /* Bit 18: Binary data inversion */ -#define USART_CR2_MSBFIRST (1 << 19) /* Bit 19: Most significant bit first */ -#define USART_CR2_ABREN (1 << 20) /* Bit 20: Auto baud rate enable */ -#define USART_CR2_ABRMOD_SHIFT (21) /* Bits 21-22: Auto baud rate mode */ -#define USART_CR2_ABRMOD_MASK (3 << USART_CR2_ABRMOD_SHIFT) -# define USART_CR2_ABRMOD_START (0 << USART_CR2_ABRMOD_SHIFT) /* Start bit */ -# define USART_CR2_ABRMOD_FALL (1 << USART_CR2_ABRMOD_SHIFT) /* Falling edge measurement */ -# define USART_CR2_ABRMOD_7F (2 << USART_CR2_ABRMOD_SHIFT) /* 0x7F frame detection */ -# define USART_CR2_ABRMOD_55 (3 << USART_CR2_ABRMOD_SHIFT) /* 0x55 frame detection */ - -#define USART_CR2_RTOEN (1 << 23) /* Bit 23: Receiver timeout enable */ -#define USART_CR2_ADD4L_SHIFT (24) /* Bits 24-27: Address[3:0]:of the USART node */ -#define USART_CR2_ADD4L_MASK (15 << USART_CR2_ADD4L_SHIFT) -# define USART_CR2_ADD4L(n) ((uint32_t)(n) << USART_CR2_ADD4L_SHIFT) -#define USART_CR2_ADD4H_SHIFT (28) /* Bits 28-31: Address[4:0] of the USART node */ -#define USART_CR2_ADD4H_MASK (15 << USART_CR2_ADD4H_SHIFT) -# define USART_CR2_ADD4H(n) ((uint32_t)(n) << USART_CR2_ADD4H_SHIFT) -#define USART_CR2_ADD8_SHIFT (24) /* Bits 24-31: Address[7:0] of the USART node */ -#define USART_CR2_ADD8_MASK (255 << USART_CR2_ADD8_SHIFT) -# define USART_CR2_ADD8(n) ((uint32_t)(n) << USART_CR2_ADD8_SHIFT) - -/* Control register 3 */ - -#define USART_CR3_EIE (1 << 0) /* Bit 0: Error Interrupt Enable */ -#define USART_CR3_IREN (1 << 1) /* Bit 1: IrDA mode Enable */ -#define USART_CR3_IRLP (1 << 2) /* Bit 2: IrDA Low-Power */ -#define USART_CR3_HDSEL (1 << 3) /* Bit 3: Half-Duplex Selection */ -#define USART_CR3_NACK (1 << 4) /* Bit 4: Smartcard NACK enable */ -#define USART_CR3_SCEN (1 << 5) /* Bit 5: Smartcard mode enable */ -#define USART_CR3_DMAR (1 << 6) /* Bit 6: DMA Enable Receiver */ -#define USART_CR3_DMAT (1 << 7) /* Bit 7: DMA Enable Transmitter */ -#define USART_CR3_RTSE (1 << 8) /* Bit 8: RTS Enable */ -#define USART_CR3_CTSE (1 << 9) /* Bit 9: CTS Enable */ -#define USART_CR3_CTSIE (1 << 10) /* Bit 10: CTS Interrupt Enable */ -#define USART_CR3_ONEBIT (1 << 11) /* Bit 11: One sample bit method enable */ -#define USART_CR3_OVRDIS (1 << 12) /* Bit 12: Overrun Disable */ -#define USART_CR3_DDRE (1 << 13) /* Bit 13: DMA Disable on Reception Error */ -#define USART_CR3_DEM (1 << 14) /* Bit 14: Driver enable mode */ -#define USART_CR3_DEP (1 << 15) /* Bit 15: Driver enable polarity selection */ -#define USART_CR3_SCARCNT_SHIFT (17) /* Bit 17-19: Smartcard auto-retry count */ -#define USART_CR3_SCARCNT_MASK (7 << USART_CR3_SCARCNT_SHIFT) -# define USART_CR3_SCARCNT(n) ((uint32_t)(n) << USART_CR3_SCARCNT_SHIFT) -#define USART_CR3_RXFTCFG_SHIFT (25) /* Bit 25-27: Receive FIFO threshold configuration */ -#define USART_CR3_RXFTCFG_MASK (7 << USART_CR3_RXFTCFG_SHIFT) -# define USART_CR3_RXFTCFG(n) ((uint32_t)(n) << USART_CR3_RXFTCFG_SHIFT) -# define USART_CR3_RXFTCFG_12PCT (0 << USART_CR3_RXFTCFG_SHIFT) /* RXFIFO 1/8 full */ -# define USART_CR3_RXFTCFG_25PCT (1 << USART_CR3_RXFTCFG_SHIFT) /* RXFIFO 1/4 full */ -# define USART_CR3_RXFTCFG_50PCT (2 << USART_CR3_RXFTCFG_SHIFT) /* RXFIFO 1/2 full */ -# define USART_CR3_RXFTCFG_75PCT (3 << USART_CR3_RXFTCFG_SHIFT) /* RXFIFO 3/4 full */ -# define USART_CR3_RXFTCFG_88PCT (4 << USART_CR3_RXFTCFG_SHIFT) /* RXFIFO 7/8 full */ -# define USART_CR3_RXFTCFG_FULL (5 << USART_CR3_RXFTCFG_SHIFT) /* RXIFO full */ - -#define USART_CR3_RXFTIE (1 << 28) /* Bit 28: RXFIFO threshold interrupt enable */ -#define USART_CR3_TXFTCFG_SHIFT (29) /* Bits 29-31: TXFIFO threshold configuration */ -#define USART_CR3_TXFTCFG_MASK (7 << USART_CR3_TXFTCFG_SHIFT) -# define USART_CR3_TXFTCFG(n) ((uint32_t)(n) << USART_CR3_TXFTCFG_SHIFT) -# define USART_CR3_TXFTCFG_12PCT (0 << USART_CR3_TXFTCFG_SHIFT) /* TXFIFO 1/8 full */ -# define USART_CR3_TXFTCFG_24PCT (1 << USART_CR3_TXFTCFG_SHIFT) /* TXFIFO 1/4 full */ -# define USART_CR3_TXFTCFG_50PCT (2 << USART_CR3_TXFTCFG_SHIFT) /* TXFIFO 1/2 full */ -# define USART_CR3_TXFTCFG_75PCT (3 << USART_CR3_TXFTCFG_SHIFT) /* TXFIFO 3/4 full */ -# define USART_CR3_TXFTCFG_88PCT (4 << USART_CR3_TXFTCFG_SHIFT) /* TXFIFO 7/8 full */ -# define USART_CR3_TXFTCFG_EMPY (5 << USART_CR3_TXFTCFG_SHIFT) /* TXFIFO empty */ - -/* Baud Rate Register */ - -#define USART_BRR_SHIFT (0) /* Bits 0-15: USARTDIV[15:0] OVER8=0*/ -#define USART_BRR_MASK (0xffff << USART_BRR_SHIFT) -# define USART_BRR(n) ((uint32_t)(n) << USART_BRR_SHIFT) - -/* Guard time and prescaler register */ - -#define USART_GTPR_PSC_SHIFT (0) /* Bits 0-7: Prescaler value */ -#define USART_GTPR_PSC_MASK (0xff << USART_GTPR_PSC_SHIFT) -# define USART_GTPR_PSC(n) ((uint32_t)(n) << USART_GTPR_PSC_SHIFT) -#define USART_GTPR_GT_SHIFT (8) /* Bits 8-15: Guard time value */ -#define USART_GTPR_GT_MASK (0xff << USART_GTPR_GT_SHIFT) -# define USART_GTPR_GT(n) ((uint32_t)(n) << USART_GTPR_GT_SHIFT) - -/* Receiver timeout register */ - -#define USART_RTOR_RTO_SHIFT (0) /* Bits 0-23: Receiver timeout value */ -#define USART_RTOR_RTO_MASK (0xffffff << USART_RTOR_RTO_SHIFT) -# define USART_RTOR_RTO(n) ((uint32_t)(n) << USART_RTOR_RTO_SHIFT) -#define USART_RTOR_BLEN_SHIFT (24) /* Bits 24-31: Block Length */ -#define USART_RTOR_BLEN_MASK (0xff << USART_RTOR_BLEN_SHIFT) -# define USART_RTOR_BLEN(n) ((uint32_t)(n) << USART_RTOR_BLEN_SHIFT) - -/* Request register */ - -#define USART_RQR_ABRRQ (1 << 0) /* Bit 0: Auto baud rate request */ -#define USART_RQR_SBKRQ (1 << 1) /* Bit 1: Send break request */ -#define USART_RQR_MMRQ (1 << 2) /* Bit 2: Mute mode request */ -#define USART_RQR_RXFRQ (1 << 3) /* Bit 3: Receive data flush request */ -#define USART_RQR_TXFRQ (1 << 4) /* Bit 4: Transmit data flush request */ - -/* Interrupt & status register */ - -#define USART_ISR_PE (1 << 0) /* Bit 0: Parity error */ -#define USART_ISR_FE (1 << 1) /* Bit 1: Framing error */ -#define USART_ISR_NE (1 << 2) /* Bit 2: Noise detected flag */ -#define USART_ISR_ORE (1 << 3) /* Bit 3: Overrun error */ -#define USART_ISR_IDLE (1 << 4) /* Bit 4: Idle line detected */ -#define USART_ISR_RXNE (1 << 5) /* Bit 5: Read data register not empty */ -#define USART_ISR_TC (1 << 6) /* Bit 6: Transmission complete */ -#define USART_ISR_TXE (1 << 7) /* Bit 7: Transmit data register empty */ -#define USART_ISR_LBDF (1 << 8) /* Bit 8: LIN break detection flag */ -#define USART_ISR_CTSIF (1 << 9) /* Bit 9: CTS interrupt flag */ -#define USART_ISR_CTS (1 << 10) /* Bit 10: CTS flag */ -#define USART_ISR_RTOF (1 << 11) /* Bit 11: Receiver timeout */ -#define USART_ISR_EOBF (1 << 12) /* Bit 12: End of block flag */ -#define USART_ISR_UDR (1 << 13) /* Bit 13: SPI slave underrun error flag */ -#define USART_ISR_ABRE (1 << 14) /* Bit 14: Auto baud rate error */ -#define USART_ISR_ABRF (1 << 15) /* Bit 15: Auto baud rate flag */ -#define USART_ISR_BUSY (1 << 16) /* Bit 16: Busy flag */ -#define USART_ISR_CMF (1 << 17) /* Bit 17: Character match flag */ -#define USART_ISR_SBKF (1 << 18) /* Bit 18: Send break flag */ -#define USART_ISR_RWU (1 << 19) /* Bit 19: Receiver wakeup from Mute mode */ -#define USART_ISR_WUF (1 << 20) /* Bit 20: Wakeup from low-power mode flag */ -#define USART_ISR_TEACK (1 << 21) /* Bit 21: Transmit enable acknowledge flag */ -#define USART_ISR_REACK (1 << 22) /* Bit 22: Receive enable acknowledge flag */ -#define USART_ISR_TXFE (1 << 23) /* Bit 23: TXFIFO Empty */ -#define USART_ISR_RXFF (1 << 24) /* Bit 24: RXFIFO Full */ -#define USART_ISR_TCBGT (1 << 25) /* Bit 25: Transmission complete before guard time flag */ -#define USART_ISR_RXFT (1 << 26) /* Bit 26: RXFIFO threshold flag */ -#define USART_ISR_TXFT (1 << 27) /* Bit 27: TXFIFO threshold flag */ - -#define USART_ISR_ALLBITS (0x0fffffff) - -/* Interrupt flag clear register */ - -#define USART_ICR_PECF (1 << 0) /* Bit 0: Parity error clear flag */ -#define USART_ICR_FECF (1 << 1) /* Bit 1: Framing error clear flag */ -#define USART_ICR_NCF (1 << 2) /* Bit 2: Noise detected flag *clear flag */ -#define USART_ICR_ORECF (1 << 3) /* Bit 3: Overrun error clear flag */ -#define USART_ICR_IDLECF (1 << 4) /* Bit 4: Idle line detected clear flag */ -#define USART_ICR_TXFECF (1 << 5) /* Bit 5: TXFIFO empty clear flag */ -#define USART_ICR_TCCF (1 << 6) /* Bit 6: Transmission complete */ -#define USART_ICR_TCBGTCF (1 << 7) /* Bit 7: Transmission complete before Guard time clear flag */ -#define USART_ICR_LBDCF (1 << 8) /* Bit 8: LIN break detection clear flag */ -#define USART_ICR_CTSCF (1 << 9) /* Bit 9: CTS interrupt clear flag */ -#define USART_ICR_RTOCF (1 << 11) /* Bit 11: Receiver timeout clear flag */ -#define USART_ICR_EOBCF (1 << 12) /* Bit 12: End of block clear flag */ -#define USART_ICR_UDRCF (1 << 13) /* Bit 13:SPI slave underrun clear flag */ -#define USART_ICR_CMCF (1 << 17) /* Bit 17: Character match clear flag */ -#define USART_ICR_WUCF (1 << 20) /* Bit 20: Wakeup from low-power mode clear flag */ - -#define USART_ICR_ALLBITS (0x00123b7f) - -/* Receive data register */ - -#define USART_RDR_SHIFT (0) /* Bits 0-8: Receive data value */ -#define USART_RDR_MASK (0x1ff << USART_RDR_SHIFT) - -/* Transmit data register */ - -#define USART_TDR_SHIFT (0) /* Bits 0-8: Transmit data value */ -#define USART_TDR_MASK (0x1ff << USART_TDR_SHIFT) - -/* Prescaler register */ - -#define USART_PRESC_SHIFT (0) /* Bits 0-3: Clock prescaler */ -#define USART_PRESC_MASK (15 << USART_PRESC_SHIFT) -# define USART_PRESC_NODIV (0 << USART_PRESC_SHIFT) /* Input clock not divided */ -# define USART_PRESC_DIV1 (1 << USART_PRESC_SHIFT) /* Input clock divided by 2 */ -# define USART_PRESC_DIV4 (2 << USART_PRESC_SHIFT) /* Input clock divided by 4 */ -# define USART_PRESC_DIV6 (3 << USART_PRESC_SHIFT) /* Input clock divided by 6 */ -# define USART_PRESC_DIV8 (4 << USART_PRESC_SHIFT) /* Input clock divided by 8 */ -# define USART_PRESC_DIV10 (5 << USART_PRESC_SHIFT) /* Input clock divided by 10 */ -# define USART_PRESC_DIV12 (6 << USART_PRESC_SHIFT) /* Input clock divided by 12 */ -# define USART_PRESC_DIV16 (7 << USART_PRESC_SHIFT) /* Input clock divided by 16 */ -# define USART_PRESC_DIV32 (8 << USART_PRESC_SHIFT) /* Input clock divided by 32 */ -# define USART_PRESC_DIV64 (9 << USART_PRESC_SHIFT) /* Input clock divided by 64 */ -# define USART_PRESC_DIV128 (10 << USART_PRESC_SHIFT) /* Input clock divided by 128 */ -# define USART_PRESC_DIV256 (11 << USART_PRESC_SHIFT) /* Input clock divided by 256 */ - -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_UART_V2_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32_usbdev.h b/arch/arm/src/stm32f0l0g0/hardware/stm32_usbdev.h deleted file mode 100644 index 9b1c6c78ce1e1..0000000000000 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32_usbdev.h +++ /dev/null @@ -1,255 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32_usbdev.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_USBDEV_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_USBDEV_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include - -#ifdef CONFIG_STM32F0L0G0_HAVE_USBDEV - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Register Offsets *********************************************************/ - -/* Endpoint Registers */ - -#define STM32_USB_EPR_OFFSET(n) ((n) << 2) /* USB endpoint n register (16-bits) */ - -#define STM32_USB_EP0R_OFFSET 0x0000 /* USB endpoint 0 register (16-bits) */ -#define STM32_USB_EP1R_OFFSET 0x0004 /* USB endpoint 1 register (16-bits) */ -#define STM32_USB_EP2R_OFFSET 0x0008 /* USB endpoint 2 register (16-bits) */ -#define STM32_USB_EP3R_OFFSET 0x000c /* USB endpoint 3 register (16-bits) */ -#define STM32_USB_EP4R_OFFSET 0x0010 /* USB endpoint 4 register (16-bits) */ -#define STM32_USB_EP5R_OFFSET 0x0014 /* USB endpoint 5 register (16-bits) */ -#define STM32_USB_EP6R_OFFSET 0x0018 /* USB endpoint 6 register (16-bits) */ -#define STM32_USB_EP7R_OFFSET 0x001c /* USB endpoint 7 register (16-bits) */ - -/* Common Registers */ - -#define STM32_USB_CNTR_OFFSET 0x0040 /* USB control register (16-bits) */ -#define STM32_USB_ISTR_OFFSET 0x0044 /* USB interrupt status register (16-bits) */ -#define STM32_USB_FNR_OFFSET 0x0048 /* USB frame number register (16-bits) */ -#define STM32_USB_DADDR_OFFSET 0x004c /* USB device address (16-bits) */ -#define STM32_USB_BTABLE_OFFSET 0x0050 /* Buffer table address (16-bits) */ -#define STM32_USB_LPMCSR_OFFSET 0x0054 /* LPM control and status register (16-bits) */ -#define STM32_USB_BCDR_OFFSET 0x0058 /* Battery charging detector (16-bits) */ - -/* Buffer Descriptor Table (Relatative to BTABLE address) */ - -#define STM32_USB_ADDR_TX_WOFFSET (0) /* Transmission buffer address n (16-bits) */ -#define STM32_USB_COUNT_TX_WOFFSET (2) /* Transmission byte count n (16-bits) */ -#define STM32_USB_ADDR_RX_WOFFSET (4) /* Reception buffer address n (16-bits) */ -#define STM32_USB_COUNT_RX_WOFFSET (6) /* Reception byte count n (16-bits) */ - -#define STM32_USB_BTABLE_RADDR(ep,o) ((((uint32_t)getreg16(STM32_USB_BTABLE) + ((ep) << 3)) + (o)) << 1) -#define STM32_USB_ADDR_TX_OFFSET(ep) STM32_USB_BTABLE_RADDR(ep,STM32_USB_ADDR_TX_WOFFSET) -#define STM32_USB_COUNT_TX_OFFSET(ep) STM32_USB_BTABLE_RADDR(ep,STM32_USB_COUNT_TX_WOFFSET) -#define STM32_USB_ADDR_RX_OFFSET(ep) STM32_USB_BTABLE_RADDR(ep,STM32_USB_ADDR_RX_WOFFSET) -#define STM32_USB_COUNT_RX_OFFSET(ep) STM32_USB_BTABLE_RADDR(ep,STM32_USB_COUNT_RX_WOFFSET) - -/* Register Addresses *******************************************************/ - -/* Endpoint Registers */ - -#define STM32_USB_EPR(n) (STM32_USB_BASE + STM32_USB_EPR_OFFSET(n)) -#define STM32_USB_EP0R (STM32_USB_BASE + STM32_USB_EP0R_OFFSET) -#define STM32_USB_EP1R (STM32_USB_BASE + STM32_USB_EP1R_OFFSET) -#define STM32_USB_EP2R (STM32_USB_BASE + STM32_USB_EP2R_OFFSET) -#define STM32_USB_EP3R (STM32_USB_BASE + STM32_USB_EP3R_OFFSET) -#define STM32_USB_EP4R (STM32_USB_BASE + STM32_USB_EP4R_OFFSET) -#define STM32_USB_EP5R (STM32_USB_BASE + STM32_USB_EP5R_OFFSET) -#define STM32_USB_EP6R (STM32_USB_BASE + STM32_USB_EP6R_OFFSET) -#define STM32_USB_EP7R (STM32_USB_BASE + STM32_USB_EP7R_OFFSET) - -/* Common Registers */ - -#define STM32_USB_CNTR (STM32_USB_BASE + STM32_USB_CNTR_OFFSET) -#define STM32_USB_ISTR (STM32_USB_BASE + STM32_USB_ISTR_OFFSET) -#define STM32_USB_FNR (STM32_USB_BASE + STM32_USB_FNR_OFFSET) -#define STM32_USB_DADDR (STM32_USB_BASE + STM32_USB_DADDR_OFFSET) -#define STM32_USB_BTABLE (STM32_USB_BASE + STM32_USB_BTABLE_OFFSET) -#define STM32_USB_LPMCSR (STM32_USB_BASE + STM32_USB_LPMCSR_OFFSET) -#define STM32_USB_BCDR (STM32_USB_BASE + STM32_USB_BCDR_OFFSET) - -/* Buffer Descriptor Table (Relative to BTABLE address) */ - -#define STM32_USB_BTABLE_ADDR(ep,o) (STM32_USBRAM_BASE + STM32_USB_BTABLE_RADDR(ep,o)) -#define STM32_USB_ADDR_TX(ep) STM32_USB_BTABLE_ADDR(ep,STM32_USB_ADDR_TX_WOFFSET) -#define STM32_USB_COUNT_TX(ep) STM32_USB_BTABLE_ADDR(ep,STM32_USB_COUNT_TX_WOFFSET) -#define STM32_USB_ADDR_RX(ep) STM32_USB_BTABLE_ADDR(ep,STM32_USB_ADDR_RX_WOFFSET) -#define STM32_USB_COUNT_RX(ep) STM32_USB_BTABLE_ADDR(ep,STM32_USB_COUNT_RX_WOFFSET) - -/* Register Bitfield Definitions ********************************************/ - -/* USB endpoint register */ - -#define USB_EPR_EA_SHIFT (0) /* Bits 3:0 [3:0]: Endpoint Address */ -#define USB_EPR_EA_MASK (0X0f << USB_EPR_EA_SHIFT) -#define USB_EPR_STATTX_SHIFT (4) /* Bits 5-4: Status bits, for transmission transfers */ -#define USB_EPR_STATTX_MASK (3 << USB_EPR_STATTX_SHIFT) -# define USB_EPR_STATTX_DIS (0 << USB_EPR_STATTX_SHIFT) /* EndPoint TX DISabled */ -# define USB_EPR_STATTX_STALL (1 << USB_EPR_STATTX_SHIFT) /* EndPoint TX STALLed */ -# define USB_EPR_STATTX_NAK (2 << USB_EPR_STATTX_SHIFT) /* EndPoint TX NAKed */ -# define USB_EPR_STATTX_VALID (3 << USB_EPR_STATTX_SHIFT) /* EndPoint TX VALID */ -# define USB_EPR_STATTX_DTOG1 (1 << USB_EPR_STATTX_SHIFT) /* EndPoint TX Data Toggle bit1 */ -# define USB_EPR_STATTX_DTOG2 (2 << USB_EPR_STATTX_SHIFT) /* EndPoint TX Data Toggle bit2 */ - -#define USB_EPR_DTOG_TX (1 << 6) /* Bit 6: Data Toggle, for transmission transfers */ -#define USB_EPR_CTR_TX (1 << 7) /* Bit 7: Correct Transfer for transmission */ -#define USB_EPR_EP_KIND (1 << 8) /* Bit 8: Endpoint Kind */ -#define USB_EPR_EPTYPE_SHIFT (9) /* Bits 10-9: Endpoint type */ -#define USB_EPR_EPTYPE_MASK (3 << USB_EPR_EPTYPE_SHIFT) -# define USB_EPR_EPTYPE_BULK (0 << USB_EPR_EPTYPE_SHIFT) /* EndPoint BULK */ -# define USB_EPR_EPTYPE_CONTROL (1 << USB_EPR_EPTYPE_SHIFT) /* EndPoint CONTROL */ -# define USB_EPR_EPTYPE_ISOC (2 << USB_EPR_EPTYPE_SHIFT) /* EndPoint ISOCHRONOUS */ -# define USB_EPR_EPTYPE_INTERRUPT (3 << USB_EPR_EPTYPE_SHIFT) /* EndPoint INTERRUPT */ - -#define USB_EPR_SETUP (1 << 11) /* Bit 11: Setup transaction completed */ -#define USB_EPR_STATRX_SHIFT (12) /* Bits 13-12: Status bits, for reception transfers */ -#define USB_EPR_STATRX_MASK (3 << USB_EPR_STATRX_SHIFT) -# define USB_EPR_STATRX_DIS (0 << USB_EPR_STATRX_SHIFT) /* EndPoint RX DISabled */ -# define USB_EPR_STATRX_STALL (1 << USB_EPR_STATRX_SHIFT) /* EndPoint RX STALLed */ -# define USB_EPR_STATRX_NAK (2 << USB_EPR_STATRX_SHIFT) /* EndPoint RX NAKed */ -# define USB_EPR_STATRX_VALID (3 << USB_EPR_STATRX_SHIFT) /* EndPoint RX VALID */ -# define USB_EPR_STATRX_DTOG1 (1 << USB_EPR_STATRX_SHIFT) /* EndPoint RX Data TOGgle bit1 */ -# define USB_EPR_STATRX_DTOG2 (2 << USB_EPR_STATRX_SHIFT) /* EndPoint RX Data TOGgle bit1 */ - -#define USB_EPR_DTOG_RX (1 << 14) /* Bit 14: Data Toggle, for reception transfers */ -#define USB_EPR_CTR_RX (1 << 15) /* Bit 15: Correct Transfer for reception */ - -/* USB control register */ - -#define USB_CNTR_FRES (1 << 0) /* Bit 0: Force USB Reset */ -#define USB_CNTR_PDWN (1 << 1) /* Bit 1: Power down */ -#define USB_CNTR_LPMODE (1 << 2) /* Bit 2: Low-power mode */ -#define USB_CNTR_FSUSP (1 << 3) /* Bit 3: Force suspend */ -#define USB_CNTR_RESUME (1 << 4) /* Bit 4: Resume request */ -#define USB_CNTR_L1RESUME (1 << 5) /* Bit 5: LPM L1 Resume request */ -#define USB_CNTR_L1REQ (1 << 7) /* Bit 7: LPM L1 state request interrupt mask */ -#define USB_CNTR_ESOFM (1 << 8) /* Bit 8: Expected Start Of Frame Interrupt Mask */ -#define USB_CNTR_SOFM (1 << 9) /* Bit 9: Start Of Frame Interrupt Mask */ -#define USB_CNTR_RESETM (1 << 10) /* Bit 10: USB Reset Interrupt Mask */ -#define USB_CNTR_SUSPM (1 << 11) /* Bit 11: Suspend mode Interrupt Mask */ -#define USB_CNTR_WKUPM (1 << 12) /* Bit 12: Wakeup Interrupt Mask */ -#define USB_CNTR_ERRM (1 << 13) /* Bit 13: Error Interrupt Mask */ -#define USB_CNTR_PMAOVRN (1 << 14) /* Bit 14: Packet Memory Area Over / Underrun Interrupt Mask */ -#define USB_CNTR_CTRM (1 << 15) /* Bit 15: Correct Transfer Interrupt Mask */ - -#define USB_CNTR_ALLINTS (USB_CNTR_L1REQ|USB_CNTR_ESOFM|USB_CNTR_SOFM|USB_CNTR_RESETM|\ - USB_CNTR_SUSPM|USB_CNTR_WKUPM|USB_CNTR_ERRM|USB_CNTR_PMAOVRN|\ - USB_CNTR_CTRM) - -/* USB interrupt status register */ - -#define USB_ISTR_EPID_SHIFT (0) /* Bits 3-0: Endpoint Identifier */ -#define USB_ISTR_EPID_MASK (0x0f << USB_ISTR_EPID_SHIFT) -#define USB_ISTR_DIR (1 << 4) /* Bit 4: Direction of transaction */ -#define USB_ISTR_L1REQ (1 << 7) /* Bit 7: LPM L1 state request */ -#define USB_ISTR_ESOF (1 << 8) /* Bit 8: Expected Start Of Frame */ -#define USB_ISTR_SOF (1 << 9) /* Bit 9: Start Of Frame */ -#define USB_ISTR_RESET (1 << 10) /* Bit 10: USB RESET request */ -#define USB_ISTR_SUSP (1 << 11) /* Bit 11: Suspend mode request */ -#define USB_ISTR_WKUP (1 << 12) /* Bit 12: Wake up */ -#define USB_ISTR_ERR (1 << 13) /* Bit 13: Error */ -#define USB_ISTR_PMAOVRN (1 << 14) /* Bit 14: Packet Memory Area Over / Underrun */ -#define USB_ISTR_CTR (1 << 15) /* Bit 15: Correct Transfer */ - -#define USB_ISTR_ALLINTS (USB_ISTR_L1REQ|USB_ISTR_ESOF|USB_ISTR_SOF|USB_ISTR_RESET|\ - USB_ISTR_SUSP|USB_ISTR_WKUP|USB_ISTR_ERR|USB_ISTR_PMAOVRN|\ - USB_ISTR_CTR) - -/* USB frame number register */ - -#define USB_FNR_FN_SHIFT (0) /* Bits 10-0: Frame Number */ -#define USB_FNR_FN_MASK (0x07ff << USB_FNR_FN_SHIFT) -#define USB_FNR_LSOF_SHIFT (11) /* Bits 12-11: Lost SOF */ -#define USB_FNR_LSOF_MASK (3 << USB_FNR_LSOF_SHIFT) -#define USB_FNR_LCK (1 << 13) /* Bit 13: Locked */ -#define USB_FNR_RXDM (1 << 14) /* Bit 14: Receive Data - Line Status */ -#define USB_FNR_RXDP (1 << 15) /* Bit 15: Receive Data + Line Status */ - -/* USB device address */ - -#define USB_DADDR_ADD_SHIFT (0) /* Bits 6-0: Device Address */ -#define USB_DADDR_ADD_MASK (0x7f << USB_DADDR_ADD_SHIFT) -#define USB_DADDR_EF (1 << 7) /* Bit 7: Enable Function */ - -/* Buffer table address */ - -#define USB_BTABLE_SHIFT (3) /* Bits 15:3: Buffer Table */ -#define USB_BTABLE_MASK (0x1fff << USB_BTABLE_SHIFT) - -/* LPM control and status register (16-bits) */ - -#define USB_LPMCSR_LPMEN (1 << 0) /* Bit 0: LPM support enable */ -#define USB_LPMCSR_LPMACK (1 << 1) /* Bit 1: LPM Token acknowledge enable */ -#define USB_LPMCSR_REMWAKE (1 << 3) /* Bit 3: bRemoteWake value */ -#define USB_LPMCSR_BESL_SHIFT (4) /* Bits 4-7: BESL value */ -#define USB_LPMCSR_BESL_MASK (15 << USB_LPMCSR_BESL_SHIFT) - -/* Battery charging detector (16-bits) */ - -#define USB_BCDR_BCDEN (1 << 0) /* Bit 0: Battery charging detector (BCD) enable */ -#define USB_BCDR_DCDEN (1 << 1) /* Bit 1: Data contact detection (DCD) mode enable */ -#define USB_BCDR_PDEN (1 << 2) /* Bit 2: Primary detection (PD) mode enable */ -#define USB_BCDR_SDEN (1 << 3) /* Bit 3: Secondary detection (SD) mode enable */ -#define USB_BCDR_DCDET (1 << 4) /* Bit 4: Data contact detection (DCD) status */ -#define USB_BCDR_PDET (1 << 5) /* Bit 5: Primary detection (PD) status */ -#define USB_BCDR_SDET (1 << 6) /* Bit 6: Secondary detection (SD) status */ -#define USB_BCDR_PS2DET (1 << 7) /* Bit 7: DM pull-up detection status */ -#define USB_BCDR_DPPU (1 << 15) /* Bit 15: DP pull-up control */ - -/* Transmission buffer address */ - -#define USB_ADDR_TX_ZERO (1 << 0) /* Bit 0 Must always be written as ‘0’ */ -#define USB_ADDR_TX_SHIFT (1) /* Bits 15-1: Transmission Buffer Address */ -#define USB_ADDR_TX_MASK (0x7fff << USB_ADDR_ADDR_TX_SHIFT) - -/* Transmission byte count */ - -#define USB_COUNT_TX_SHIFT (0) /* Bits 9-0: Transmission Byte Count */ -#define USB_COUNT_TX_MASK (0x03ff << USB_COUNT_COUNT_TX_SHIFT) - -/* Reception buffer address */ - -#define USB_ADDR_RX_ZERO (1 << 0) /* Bit 0 This bit must always be written as ‘0’ */ -#define USB_ADDR_RX_SHIFT (1) /* Bits 15:1 ADDRn_RX[15:1]: Reception Buffer Address */ -#define USB_ADDR_RX_MASK (0x7fff << USB_ADDR_RX_SHIFT) - -/* Reception byte count */ - -#define USB_COUNT_RX_BL_SIZE (1 << 15) /* Bit 15: BLock SIZE. */ -#define USB_COUNT_RX_NUM_BLOCK_SHIFT (10) /* Bits 14-10: Number of blocks */ -#define USB_COUNT_RX_NUM_BLOCK_MASK (0x1f << USB_COUNT_RX_NUM_BLOCK_SHIFT) -#define USB_COUNT_RX_SHIFT (0) /* Bits 9-0: Reception Byte Count */ -#define USB_COUNT_RX_MASK (0x03ff << USB_COUNT_RX_SHIFT) - -#endif /* CONFIG_STM32F0L0G0_HAVE_USBDEV */ -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_USBDEV_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32_wdg.h b/arch/arm/src/stm32f0l0g0/hardware/stm32_wdg.h deleted file mode 100644 index 824bf9c6a7dca..0000000000000 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32_wdg.h +++ /dev/null @@ -1,141 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32_wdg.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_WDG_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_WDG_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "chip.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Register Offsets *********************************************************/ - -#define STM32_IWDG_KR_OFFSET 0x0000 /* Key register (32-bit) */ -#define STM32_IWDG_PR_OFFSET 0x0004 /* Prescaler register (32-bit) */ -#define STM32_IWDG_RLR_OFFSET 0x0008 /* Reload register (32-bit) */ -#define STM32_IWDG_SR_OFFSET 0x000c /* Status register (32-bit) */ -#define STM32_IWDG_WINR_OFFSET 0x000c /* Window register (32-bit) */ - -#define STM32_WWDG_CR_OFFSET 0x0000 /* Control Register (32-bit) */ -#define STM32_WWDG_CFR_OFFSET 0x0004 /* Configuration register (32-bit) */ -#define STM32_WWDG_SR_OFFSET 0x0008 /* Status register (32-bit) */ - -/* Register Addresses *******************************************************/ - -#define STM32_IWDG_KR (STM32_IWDG_BASE+STM32_IWDG_KR_OFFSET) -#define STM32_IWDG_PR (STM32_IWDG_BASE+STM32_IWDG_PR_OFFSET) -#define STM32_IWDG_RLR (STM32_IWDG_BASE+STM32_IWDG_RLR_OFFSET) -#define STM32_IWDG_SR (STM32_IWDG_BASE+STM32_IWDG_SR_OFFSET) -#define STM32_IWDG_WINR (STM32_IWDG_BASE+STM32_IWDG_WINR_OFFSET) - -#define STM32_WWDG_CR (STM32_WWDG_BASE+STM32_WWDG_CR_OFFSET) -#define STM32_WWDG_CFR (STM32_WWDG_BASE+STM32_WWDG_CFR_OFFSET) -#define STM32_WWDG_SR (STM32_WWDG_BASE+STM32_WWDG_SR_OFFSET) - -/* Register Bitfield Definitions ********************************************/ - -/* Key register (32-bit) */ - -#define IWDG_KR_KEY_SHIFT (0) /* Bits 15-0: Key value (write only, read 0000h) */ -#define IWDG_KR_KEY_MASK (0xffff << IWDG_KR_KEY_SHIFT) - -#define IWDG_KR_KEY_ENABLE (0x5555) /* Enable register access */ -#define IWDG_KR_KEY_DISABLE (0x0000) /* Disable register access */ -#define IWDG_KR_KEY_RELOAD (0xaaaa) /* Reload the counter */ -#define IWDG_KR_KEY_START (0xcccc) /* Start the watchdog */ - -/* Prescaler register (32-bit) */ - -#define IWDG_PR_SHIFT (0) /* Bits 2-0: Prescaler divider */ -#define IWDG_PR_MASK (7 << IWDG_PR_SHIFT) -# define IWDG_PR_DIV4 (0 << IWDG_PR_SHIFT) /* 000: divider /4 */ -# define IWDG_PR_DIV8 (1 << IWDG_PR_SHIFT) /* 001: divider /8 */ -# define IWDG_PR_DIV16 (2 << IWDG_PR_SHIFT) /* 010: divider /16 */ -# define IWDG_PR_DIV32 (3 << IWDG_PR_SHIFT) /* 011: divider /32 */ -# define IWDG_PR_DIV64 (4 << IWDG_PR_SHIFT) /* 100: divider /64 */ -# define IWDG_PR_DIV128 (5 << IWDG_PR_SHIFT) /* 101: divider /128 */ -# define IWDG_PR_DIV256 (6 << IWDG_PR_SHIFT) /* 11x: divider /256 */ - -/* Reload register (32-bit) */ - -#define IWDG_RLR_RL_SHIFT (0) /* Bits11:0 RL[11:0]: Watchdog counter reload value */ -#define IWDG_RLR_RL_MASK (0x0fff << IWDG_RLR_RL_SHIFT) - -#define IWDG_RLR_MAX (0xfff) - -/* Status register (32-bit) */ - -#define IWDG_SR_PVU (1 << 0) /* Bit 0: Watchdog prescaler value update */ -#define IWDG_SR_RVU (1 << 1) /* Bit 1: Watchdog counter reload value update */ -#define IWDG_SR_WVU (1 << 2) /* Bit 2: */ - -/* Window register (32-bit) */ - -#define IWDG_WINR_SHIFT (0) -#define IWDG_WINR_MASK (0x0fff << IWDG_WINR_SHIFT) - -/* Control Register (32-bit) */ - -#define WWDG_CR_T_SHIFT (0) /* Bits 6:0 T[6:0]: 7-bit counter (MSB to LSB) */ -#define WWDG_CR_T_MASK (0x7f << WWDG_CR_T_SHIFT) -# define WWDG_CR_T_MAX (0x3f << WWDG_CR_T_SHIFT) -# define WWDG_CR_T_RESET (0x40 << WWDG_CR_T_SHIFT) -#define WWDG_CR_WDGA (1 << 7) /* Bit 7: Activation bit */ - -/* Configuration register (32-bit) */ - -#define WWDG_CFR_W_SHIFT (0) /* Bits 6:0 W[6:0] 7-bit window value */ -#define WWDG_CFR_W_MASK (0x7f << WWDG_CFR_W_SHIFT) -#define WWDG_CFR_WDGTB_SHIFT (7) /* Bits 8:7 [1:0]: Timer Base */ -#define WWDG_CFR_WDGTB_MASK (3 << WWDG_CFR_WDGTB_SHIFT) -# define WWDG_CFR_PCLK1 (0 << WWDG_CFR_WDGTB_SHIFT) /* 00: CK Counter Clock (PCLK1 div 4096) div 1 */ -# define WWDG_CFR_PCLK1d2 (1 << WWDG_CFR_WDGTB_SHIFT) /* 01: CK Counter Clock (PCLK1 div 4096) div 2 */ -# define WWDG_CFR_PCLK1d4 (2 << WWDG_CFR_WDGTB_SHIFT) /* 10: CK Counter Clock (PCLK1 div 4096) div 4 */ -# define WWDG_CFR_PCLK1d8 (3 << WWDG_CFR_WDGTB_SHIFT) /* 11: CK Counter Clock (PCLK1 div 4096) div 8 */ - -#define WWDG_CFR_EWI (1 << 9) /* Bit 9: Early Wakeup Interrupt */ - -/* Status register (32-bit) */ - -#define WWDG_SR_EWIF (1 << 0) /* Bit 0: Early Wakeup Interrupt Flag */ - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/**************************************************************************** - * Public Functions Prototypes - ****************************************************************************/ - -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_WDG_H */ diff --git a/arch/arm/src/stm32f0l0g0/stm32.h b/arch/arm/src/stm32f0l0g0/stm32.h deleted file mode 100644 index c43d655c8b9bf..0000000000000 --- a/arch/arm/src/stm32f0l0g0/stm32.h +++ /dev/null @@ -1,54 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_STM32_H -#define __ARCH_ARM_SRC_STM32F0L0G0_STM32_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include -#include -#include - -#include "arm_internal.h" - -/* Peripherals **************************************************************/ - -#include "chip.h" -#include "stm32_dma.h" -#include "stm32_gpio.h" -#include "stm32_i2c.h" -#include "stm32_pwr.h" -#include "stm32_rcc.h" -#include "stm32_spi.h" -#include "stm32_uart.h" -#include "stm32_lowputc.h" -#include "stm32_adc.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_STM32_H */ diff --git a/arch/arm/src/stm32f0l0g0/stm32_adc.c b/arch/arm/src/stm32f0l0g0/stm32_adc.c deleted file mode 100644 index 8435f1f8b6f45..0000000000000 --- a/arch/arm/src/stm32f0l0g0/stm32_adc.c +++ /dev/null @@ -1,2882 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_adc.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include - -#include "arm_internal.h" -#include "chip.h" -#include "stm32.h" -#include "stm32_tim.h" -#include "stm32_dma.h" -#include "stm32_adc.h" - -/* STM32 ADC "lower-half" support must be enabled */ - -#ifdef CONFIG_STM32F0L0G0_ADC - -/* Some ADC peripheral must be enabled */ - -#if defined(CONFIG_STM32F0L0G0_ADC1) - -#if defined(CONFIG_STM32F0L0G0_STM32F0) -# error Not tested -#endif - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* RCC reset ****************************************************************/ - -#define STM32_RCC_RSTR STM32_RCC_APB2RSTR -#define RCC_RSTR_ADC1RST RCC_APB2RSTR_ADC1RST - -/* ADC Channels/DMA *********************************************************/ - -/* DMA values differs according to STM32 DMA IP core version */ - -#if defined(HAVE_IP_DMA_V1) -# define ADC_DMA_CONTROL_WORD (DMA_CCR_MSIZE_16BITS | \ - DMA_CCR_PSIZE_16BITS | \ - DMA_CCR_MINC | \ - DMA_CCR_CIRC) -#else -# error Not supported -#endif - -/* Sample time default configuration */ - -/* C0 and G0 support additional sample time selection 2 */ - -#if defined(CONFIG_STM32F0L0G0_STM32G0) || defined(CONFIG_STM32F0L0G0_STM32C0) -# define ADC_HAVE_SMPR_SMP2 -#endif - -#if defined(ADC_HAVE_DMA) || (CONFIG_STM32F0L0G0_ADC_MAX_SAMPLES == 1) -# if defined(CONFIG_ARCH_CHIP_STM32C0) || defined(CONFIG_ARCH_CHIP_STM32G0) -# define ADC_SMP1_DEFAULT ADC_SMPR_12p5 -# define ADC_SMP2_DEFAULT ADC_SMPR_12p5 -# else -# define ADC_SMP1_DEFAULT ADC_SMPR_13p5 -# endif -#else /* Slow down sampling frequency */ -# if defined(CONFIG_ARCH_CHIP_STM32C0) || defined(CONFIG_ARCH_CHIP_STM32G0) -# define ADC_SMP1_DEFAULT ADC_SMPR_160p5 -# define ADC_SMP2_DEFAULT ADC_SMPR_160p5 -# else -# define ADC_SMP1_DEFAULT ADC_SMPR_239p5 -# endif -#endif - -#ifdef ADC_HAVE_SMPR_SMP2 -# define ADC_SMPSEL_DEFAULT 0 /* For now we use only SMP1 */ -#endif - -/* Number of channels per ADC: - * - F0, L0, G0 - 19, but single SMP for all channels - * - * NOTE: this value can be obtained from SMPRx register description - * (ST manual) - */ - -#if defined(CONFIG_STM32F0L0G0_STM32F0) || \ - defined(CONFIG_STM32F0L0G0_STM32L0) || \ - defined(CONFIG_STM32F0L0G0_STM32C0) || \ - defined(CONFIG_STM32F0L0G0_STM32G0) -# define ADC_CHANNELS_NUMBER 19 -#else -# error "Not supported" -#endif - -/* ADC resolution */ - -#define HAVE_ADC_RESOLUTION - -/* ADC have common registers but only single ADC */ - -#define HAVE_ADC_CMN_REGS 1 - -/* ADCx_EXTSEL_VALUE */ - -#ifdef ADC1_EXTSEL_VALUE -# define ADC1_HAVE_EXTCFG 1 -# define ADC1_EXTCFG_VALUE (ADC1_EXTSEL_VALUE | ADC_EXTREG_EXTEN_DEFAULT) -#else -# undef ADC1_HAVE_EXTCFG -#endif - -#if defined(ADC1_HAVE_EXTCFG) -# define ADC_HAVE_EXTCFG -#endif - -/* ADC DMA configuration bit support */ - -#define ADC_HAVE_DMACFG 1 - -#if defined(CONFIG_STM32F0L0G0_STM32G0) || defined(CONFIG_STM32F0L0G0_STM32L0) -# ifndef ANIOC_SET_OVERSAMPLE -# define ANIOC_SET_OVERSAMPLE _ANIOC(0x0f) -# endif -#endif - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/* Data common to all ADC instances */ - -#ifdef HAVE_ADC_CMN_DATA -struct adccmn_data_s -{ - uint8_t initialized; /* How many ADC instances are currently in use */ - mutex_t lock; /* Exclusive access to common ADC data */ -}; -#endif - -/* This structure describes the state of one ADC block - * REVISIT: save some space with bit fields. - */ - -struct stm32_dev_s -{ -#ifdef CONFIG_STM32F0L0G0_ADC_LL_OPS - const struct stm32_adc_ops_s *llops; /* Low-level ADC ops */ -#endif -#if !defined(CONFIG_STM32F0L0G0_ADC_NOIRQ) | defined(ADC_HAVE_DMA) - const struct adc_callback_s *cb; - uint8_t irq; /* Interrupt generated by this ADC block */ -#endif -#ifdef HAVE_ADC_CMN_DATA - struct adccmn_data_s *cmn; /* Common ADC data */ -#endif - uint8_t rnchannels; /* Number of regular channels */ - uint8_t cr_channels; /* Number of configured regular channels */ - uint8_t intf; /* ADC interface number */ - uint8_t current; /* Current ADC channel being converted */ -#ifdef HAVE_ADC_RESOLUTION - uint8_t resolution; /* ADC resolution (0-3) */ -#endif -#ifdef ADC_HAVE_DMA - uint8_t dmachan; /* DMA channel needed by this ADC */ -# ifdef ADC_HAVE_DMACFG - uint8_t dmacfg; /* DMA channel configuration, only for ADC IPv2 */ -# endif - bool hasdma; /* True: This channel supports DMA */ - uint16_t dmabatch; /* Number of conversions for DMA batch */ -#endif -#ifdef CONFIG_STM32F0L0G0_ADC_CHANGE_SAMPLETIME - /* Sample time selection. These bits must be written only when ADON=0. */ - -# ifdef ADC_HAVE_SMPR_SMP2 - uint8_t sample_rate[2]; /* [0] for SMP1, [1] for SMP2 */ - uint32_t smpsel; /* ADC Sample Rate Selection Bits */ -# else - uint8_t sample_rate[1]; /* Only SMP1 is used */ -# endif -#endif -#ifdef ADC_HAVE_TIMER - uint8_t trigger; /* Timer trigger channel: 0=CC1, 1=CC2, 2=CC3, - * 3=CC4, 4=TRGO, 5=TRGO2 - */ -#endif - xcpt_t isr; /* Interrupt handler for this ADC block */ - uint32_t base; /* Base address of registers unique to this ADC - * block */ -#ifdef ADC_HAVE_EXTCFG - uint32_t extcfg; /* External event configuration for regular group */ -#endif -#ifdef ADC_HAVE_TIMER - uint32_t tbase; /* Base address of timer used by this ADC block */ - uint32_t pclck; /* The PCLK frequency that drives this timer */ - uint32_t freq; /* The desired frequency of conversions */ -#endif -#ifdef ADC_HAVE_DMA - DMA_HANDLE dma; /* Allocated DMA channel */ - - /* DMA transfer buffer */ - - uint16_t *r_dmabuffer; -#endif - - /* List of selected ADC channels to sample */ - - uint8_t r_chanlist[CONFIG_STM32F0L0G0_ADC_MAX_SAMPLES]; -}; - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -/* ADC Register access */ - -static void stm32_modifyreg32(unsigned int addr, uint32_t clrbits, - uint32_t setbits); -static uint32_t adc_getreg(struct stm32_dev_s *priv, int offset); -static void adc_putreg(struct stm32_dev_s *priv, int offset, - uint32_t value); -static void adc_modifyreg(struct stm32_dev_s *priv, int offset, - uint32_t clrbits, uint32_t setbits); -#ifdef HAVE_ADC_CMN_REGS -static uint32_t adccmn_base_get(struct stm32_dev_s *priv); -static void adccmn_modifyreg(struct stm32_dev_s *priv, uint32_t offset, - uint32_t clrbits, uint32_t setbits); -static uint32_t adccmn_getreg(struct stm32_dev_s *priv, uint32_t offset); -#endif -#ifdef ADC_HAVE_TIMER -static uint16_t tim_getreg(struct stm32_dev_s *priv, int offset); -static void tim_putreg(struct stm32_dev_s *priv, int offset, - uint16_t value); -static void tim_modifyreg(struct stm32_dev_s *priv, int offset, - uint16_t clrbits, uint16_t setbits); -static void tim_modifyreg32(struct stm32_dev_s *priv, int offset, - uint32_t clrbits, uint32_t setbits); -static void tim_dumpregs(struct stm32_dev_s *priv, - const char *msg); -#endif - -static void adc_rccreset(struct stm32_dev_s *priv, bool reset); - -/* ADC Interrupt Handler */ - -#ifndef CONFIG_STM32F0L0G0_ADC_NOIRQ -static int adc_interrupt(struct adc_dev_s *dev); -static int adc1_interrupt(int irq, void *context, void *arg); -#endif /* CONFIG_STM32F0L0G0_ADC_NOIRQ */ - -/* ADC Driver Methods */ - -static int adc_bind(struct adc_dev_s *dev, - const struct adc_callback_s *callback); -static void adc_reset(struct adc_dev_s *dev); -static int adc_setup(struct adc_dev_s *dev); -static void adc_shutdown(struct adc_dev_s *dev); -static void adc_rxint(struct adc_dev_s *dev, bool enable); -static int adc_ioctl(struct adc_dev_s *dev, int cmd, unsigned long arg); -static void adc_enable(struct stm32_dev_s *priv, bool enable); - -static int adc_set_ch(struct adc_dev_s *dev, uint8_t ch); - -static int adc_ioc_change_ints(struct adc_dev_s *dev, int cmd, - bool arg); - -#ifdef HAVE_ADC_RESOLUTION -static int adc_resolution_set(struct adc_dev_s *dev, uint8_t res); -#endif -#ifdef HAVE_ADC_VBAT -static void adc_enable_vbat_channel(struct adc_dev_s *dev, bool enable); -#endif -#ifdef HAVE_ADC_POWERDOWN -static int adc_ioc_change_sleep_between_opers(struct adc_dev_s *dev, - int cmd, bool arg); -static void adc_power_down_idle(struct stm32_dev_s *priv, - bool pdi_high); -static void adc_power_down_delay(struct stm32_dev_s *priv, - bool pdd_high); -#endif - -#ifdef ADC_HAVE_TIMER -static void adc_timstart(struct stm32_dev_s *priv, bool enable); -static int adc_timinit(struct stm32_dev_s *priv); -#endif - -#if defined(ADC_HAVE_DMA) -static void adc_dmaconvcallback(DMA_HANDLE handle, uint8_t isr, - void *arg); -#endif - -static void adc_reg_startconv(struct stm32_dev_s *priv, bool enable); - -#ifdef ADC_HAVE_EXTCFG -static int adc_extcfg_set(struct adc_dev_s *dev, uint32_t extcfg); -#endif - -static void adc_dumpregs(struct stm32_dev_s *priv); - -#ifdef CONFIG_STM32F0L0G0_ADC_LL_OPS -static void adc_llops_intack(struct stm32_adc_dev_s *dev, - uint32_t source); -static void adc_llops_inten(struct stm32_adc_dev_s *dev, - uint32_t source); -static void adc_llops_intdis(struct stm32_adc_dev_s *dev, - uint32_t source); -static uint32_t adc_llops_intget(struct stm32_adc_dev_s *dev); -static uint32_t adc_llops_regget(struct stm32_adc_dev_s *dev); -static void adc_llops_reg_startconv(struct stm32_adc_dev_s *dev, - bool enable); -# ifdef ADC_HAVE_DMA -static int adc_llops_regbufregister(struct stm32_adc_dev_s *dev, - uint16_t *buffer, uint8_t len); -# endif -# ifdef CONFIG_STM32F0L0G0_ADC_CHANGE_SAMPLETIME -static void adc_sampletime_set(struct stm32_adc_dev_s *dev, - struct adc_sample_time_s *time_samples); -static void adc_sampletime_write(struct stm32_adc_dev_s *dev); -# endif -static void adc_llops_dumpregs(struct stm32_adc_dev_s *dev); -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* ADC interface operations */ - -static const struct adc_ops_s g_adcops = -{ - .ao_bind = adc_bind, - .ao_reset = adc_reset, - .ao_setup = adc_setup, - .ao_shutdown = adc_shutdown, - .ao_rxint = adc_rxint, - .ao_ioctl = adc_ioctl, -}; - -/* Publicly visible ADC lower-half operations */ - -#ifdef CONFIG_STM32F0L0G0_ADC_LL_OPS -static const struct stm32_adc_ops_s g_adc_llops = -{ - .int_ack = adc_llops_intack, - .int_get = adc_llops_intget, - .int_en = adc_llops_inten, - .int_dis = adc_llops_intdis, - .val_get = adc_llops_regget, - .reg_startconv = adc_llops_reg_startconv, -# ifdef ADC_HAVE_DMA - .regbuf_reg = adc_llops_regbufregister, -# endif -# ifdef CONFIG_STM32F0L0G0_ADC_CHANGE_SAMPLETIME - .stime_set = adc_sampletime_set, - .stime_write = adc_sampletime_write, -# endif - .dump_regs = adc_llops_dumpregs -}; -#endif - -/* ADC1 state */ - -#ifdef CONFIG_STM32F0L0G0_ADC1 - -#ifdef ADC1_HAVE_DMA -static uint16_t g_adc1_dmabuffer[CONFIG_STM32F0L0G0_ADC_MAX_SAMPLES * - CONFIG_STM32F0L0G0_ADC1_DMA_BATCH]; -#endif - -static struct stm32_dev_s g_adcpriv1 = -{ -#ifdef CONFIG_STM32F0L0G0_ADC_LL_OPS - .llops = &g_adc_llops, -#endif -#ifndef CONFIG_STM32F0L0G0_ADC_NOIRQ - .irq = STM32_IRQ_ADC, - .isr = adc1_interrupt, -#endif /* CONFIG_STM32F0L0G0_ADC_NOIRQ */ -#ifdef HAVE_ADC_CMN_DATA - .cmn = &ADC1CMN_DATA, -#endif - .intf = 1, -#ifdef HAVE_ADC_RESOLUTION - .resolution = CONFIG_STM32F0L0G0_ADC1_RESOLUTION, -#endif - .base = STM32_ADC1_BASE, -#ifdef ADC1_HAVE_EXTCFG - .extcfg = ADC1_EXTCFG_VALUE, -#endif -#ifdef ADC1_HAVE_TIMER - .trigger = CONFIG_STM32F0L0G0_ADC1_TIMTRIG, - .tbase = ADC1_TIMER_BASE, - .pclck = ADC1_TIMER_PCLK_FREQUENCY, - .freq = CONFIG_STM32F0L0G0_ADC1_SAMPLE_FREQUENCY, -#endif -#ifdef ADC1_HAVE_DMA - .dmachan = ADC1_DMA_CHAN, -# ifdef ADC_HAVE_DMACFG - .dmacfg = CONFIG_STM32F0L0G0_ADC1_DMA_CFG, -# endif - .hasdma = true, - .r_dmabuffer = g_adc1_dmabuffer, - .dmabatch = CONFIG_STM32F0L0G0_ADC1_DMA_BATCH -#endif -}; - -static struct adc_dev_s g_adcdev1 = -{ - .ad_ops = &g_adcops, - .ad_priv = &g_adcpriv1, -}; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_modifyreg32 - * - * Description: - * Modify the value of a 32-bit register (not atomic). - * - * Input Parameters: - * addr - The address of the register - * clrbits - The bits to clear - * setbits - The bits to set - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void stm32_modifyreg32(unsigned int addr, uint32_t clrbits, - uint32_t setbits) -{ - putreg32((getreg32(addr) & ~clrbits) | setbits, addr); -} - -/**************************************************************************** - * Name: adc_getreg - * - * Description: - * Read the value of an ADC register. - * - * Input Parameters: - * priv - A reference to the ADC block status - * offset - The offset to the register to read - * - * Returned Value: - * The current contents of the specified register - * - ****************************************************************************/ - -static uint32_t adc_getreg(struct stm32_dev_s *priv, int offset) -{ - return getreg32(priv->base + offset); -} - -/**************************************************************************** - * Name: adc_putreg - * - * Description: - * Write a value to an ADC register. - * - * Input Parameters: - * priv - A reference to the ADC block status - * offset - The offset to the register to write to - * value - The value to write to the register - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void adc_putreg(struct stm32_dev_s *priv, int offset, - uint32_t value) -{ - putreg32(value, priv->base + offset); -} - -/**************************************************************************** - * Name: adc_modifyreg - * - * Description: - * Modify the value of an ADC register (not atomic). - * - * Input Parameters: - * priv - A reference to the ADC block status - * offset - The offset to the register to modify - * clrbits - The bits to clear - * setbits - The bits to set - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void adc_modifyreg(struct stm32_dev_s *priv, int offset, - uint32_t clrbits, uint32_t setbits) -{ - adc_putreg(priv, offset, (adc_getreg(priv, offset) & ~clrbits) | setbits); -} - -#ifdef HAVE_ADC_CMN_REGS - -/**************************************************************************** - * Name: adccmn_base_get - ****************************************************************************/ - -static uint32_t adccmn_base_get(struct stm32_dev_s *priv) -{ - uint32_t base = 0; - - if (priv->base == STM32_ADC1_BASE) - { - base = STM32_ADC12CMN_BASE; - } - - return base; -} - -/**************************************************************************** - * Name: adccmn_modifyreg - ****************************************************************************/ - -static void adccmn_modifyreg(struct stm32_dev_s *priv, uint32_t offset, - uint32_t clrbits, uint32_t setbits) -{ - uint32_t base = 0; - - /* Get base address for ADC common register */ - - base = adccmn_base_get(priv); - - /* Modify register */ - - stm32_modifyreg32(offset + base, clrbits, setbits); -} - -/**************************************************************************** - * Name: adccmn_getreg - ****************************************************************************/ - -static uint32_t adccmn_getreg(struct stm32_dev_s *priv, uint32_t offset) -{ - uint32_t base = 0; - - /* Get base address for ADC common register */ - - base = adccmn_base_get(priv); - - /* Return register value */ - - return getreg32(base + offset); -} -#endif /* HAVE_ADC_CMN_REGS */ - -#ifdef ADC_HAVE_TIMER -/**************************************************************************** - * Name: tim_getreg - * - * Description: - * Read the value of an ADC timer register. - * - * Input Parameters: - * priv - A reference to the ADC block status - * offset - The offset to the register to read - * - * Returned Value: - * The current contents of the specified register - * - ****************************************************************************/ - -static uint16_t tim_getreg(struct stm32_dev_s *priv, int offset) -{ - return getreg16(priv->tbase + offset); -} - -/**************************************************************************** - * Name: tim_putreg - * - * Description: - * Write a value to an ADC timer register. - * - * Input Parameters: - * priv - A reference to the ADC block status - * offset - The offset to the register to write to - * value - The value to write to the register - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void tim_putreg(struct stm32_dev_s *priv, int offset, - uint16_t value) -{ - putreg16(value, priv->tbase + offset); -} - -/**************************************************************************** - * Name: tim_modifyreg - * - * Description: - * Modify the value of an ADC timer register (not atomic). - * - * Input Parameters: - * priv - A reference to the ADC block status - * offset - The offset to the register to modify - * clrbits - The bits to clear - * setbits - The bits to set - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void tim_modifyreg(struct stm32_dev_s *priv, int offset, - uint16_t clrbits, uint16_t setbits) -{ - tim_putreg(priv, offset, (tim_getreg(priv, offset) & ~clrbits) | setbits); -} - -/**************************************************************************** - * Name: tim_modifyreg32 - * - * Description: - * Modify the value of an ADC timer register (not atomic). - * - * Input Parameters: - * priv - A reference to the ADC block status - * offset - The offset to the register to modify - * clrbits - The bits to clear - * setbits - The bits to set - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void tim_modifyreg32(struct stm32_dev_s *priv, int offset, - uint32_t clrbits, uint32_t setbits) -{ - uint32_t addr = priv->tbase + offset; - putreg32((getreg32(addr) & ~clrbits) | setbits, addr); -} - -/**************************************************************************** - * Name: tim_dumpregs - * - * Description: - * Dump all timer registers. - * - * Input Parameters: - * priv - A reference to the ADC block status - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void tim_dumpregs(struct stm32_dev_s *priv, const char *msg) -{ - ainfo("%s:\n", msg); - ainfo(" CR1: %04x CR2: %04x SMCR: %04x DIER: %04x\n", - tim_getreg(priv, STM32_GTIM_CR1_OFFSET), - tim_getreg(priv, STM32_GTIM_CR2_OFFSET), - tim_getreg(priv, STM32_GTIM_SMCR_OFFSET), - tim_getreg(priv, STM32_GTIM_DIER_OFFSET)); - ainfo(" SR: %04x EGR: 0000 CCMR1: %04x CCMR2: %04x\n", - tim_getreg(priv, STM32_GTIM_SR_OFFSET), - tim_getreg(priv, STM32_GTIM_CCMR1_OFFSET), - tim_getreg(priv, STM32_GTIM_CCMR2_OFFSET)); - ainfo(" CCER: %04x CNT: %04x PSC: %04x ARR: %04x\n", - tim_getreg(priv, STM32_GTIM_CCER_OFFSET), - tim_getreg(priv, STM32_GTIM_CNT_OFFSET), - tim_getreg(priv, STM32_GTIM_PSC_OFFSET), - tim_getreg(priv, STM32_GTIM_ARR_OFFSET)); - ainfo(" CCR1: %04x CCR2: %04x CCR3: %04x CCR4: %04x\n", - tim_getreg(priv, STM32_GTIM_CCR1_OFFSET), - tim_getreg(priv, STM32_GTIM_CCR2_OFFSET), - tim_getreg(priv, STM32_GTIM_CCR3_OFFSET), - tim_getreg(priv, STM32_GTIM_CCR4_OFFSET)); -#if STM32_NATIM > 0 - if (priv->tbase == STM32_TIM1_BASE) - { - ainfo(" RCR: %04x BDTR: %04x DCR: %04x DMAR: %04x\n", - tim_getreg(priv, STM32_ATIM_RCR_OFFSET), - tim_getreg(priv, STM32_ATIM_BDTR_OFFSET), - tim_getreg(priv, STM32_ATIM_DCR_OFFSET), - tim_getreg(priv, STM32_ATIM_DMAR_OFFSET)); - } - else -#endif - { - ainfo(" DCR: %04x DMAR: %04x\n", - tim_getreg(priv, STM32_GTIM_DCR_OFFSET), - tim_getreg(priv, STM32_GTIM_DMAR_OFFSET)); - } -} - -/**************************************************************************** - * Name: adc_timstart - * - * Description: - * Start (or stop) the timer counter - * - * Input Parameters: - * priv - A reference to the ADC block status - * enable - True: Start conversion - * - * Returned Value: - * - ****************************************************************************/ - -static void adc_timstart(struct stm32_dev_s *priv, bool enable) -{ - ainfo("enable: %d\n", enable ? 1 : 0); - - if (enable) - { - /* Start the counter */ - - tim_modifyreg(priv, STM32_GTIM_CR1_OFFSET, 0, GTIM_CR1_CEN); - } - else - { - /* Disable the counter */ - - tim_modifyreg(priv, STM32_GTIM_CR1_OFFSET, GTIM_CR1_CEN, 0); - } -} - -/**************************************************************************** - * Name: adc_timinit - * - * Description: - * Initialize the timer that drivers the ADC sampling for this channel - * using the pre-calculated timer divider definitions. - * - * Input Parameters: - * priv - A reference to the ADC block status - * - * Returned Value: - * Zero on success; a negated errno value on failure. - * - ****************************************************************************/ - -static int adc_timinit(struct stm32_dev_s *priv) -{ - uint32_t prescaler; - uint32_t reload; - uint32_t timclk; - uint16_t clrbits = 0; - uint16_t setbits = 0; - uint16_t cr2; - uint16_t ccmr1; - uint16_t ccmr2; - uint16_t ocmode1; - uint16_t ocmode2; - uint16_t ccenable; - uint16_t ccer; - uint16_t egr; - - /* If the timer base address is zero, then this ADC was not configured to - * use a timer. - */ - - if (priv->tbase == 0) - { - return ERROR; - } - - /* NOTE: EXTSEL configuration is done in adc_reset function */ - - /* Configure the timer channel to drive the ADC */ - - /* Calculate optimal values for the timer prescaler and for the timer - * reload register. If freq is the desired frequency, then - * - * reload = timclk / freq - * reload = (pclck / prescaler) / freq - * - * There are many solutions to do this, but the best solution will be the - * one that has the largest reload value and the smallest prescaler value. - * That is the solution that should give us the most accuracy in the timer - * control. Subject to: - * - * 0 <= prescaler <= 65536 - * 1 <= reload <= 65535 - * - * So (prescaler = pclck / 65535 / freq) would be optimal. - */ - - prescaler = (priv->pclck / priv->freq + 65534) / 65535; - - /* We need to decrement the prescaler value by one, but only, the value - * does not underflow. - */ - - if (prescaler < 1) - { - awarn("WARNING: Prescaler underflowed.\n"); - prescaler = 1; - } - - /* Check for overflow */ - - else if (prescaler > 65536) - { - awarn("WARNING: Prescaler overflowed.\n"); - prescaler = 65536; - } - - timclk = priv->pclck / prescaler; - - reload = timclk / priv->freq; - if (reload < 1) - { - awarn("WARNING: Reload value underflowed.\n"); - reload = 1; - } - else if (reload > 65535) - { - awarn("WARNING: Reload value overflowed.\n"); - reload = 65535; - } - - /* Disable the timer until we get it configured */ - - adc_timstart(priv, false); - - /* Set up the timer CR1 register. - * - * Select the Counter Mode == count up: - * - * ATIM_CR1_EDGE: The counter counts up or down depending on the - * direction bit(DIR). - * ATIM_CR1_DIR: 0: count up, 1: count down - * - * Set the clock division to zero for all - */ - - clrbits = GTIM_CR1_DIR | GTIM_CR1_CMS_MASK | GTIM_CR1_CKD_MASK; - setbits = GTIM_CR1_EDGE; - tim_modifyreg(priv, STM32_GTIM_CR1_OFFSET, clrbits, setbits); - - /* Set the reload and prescaler values */ - - tim_putreg(priv, STM32_GTIM_PSC_OFFSET, prescaler - 1); - tim_putreg(priv, STM32_GTIM_ARR_OFFSET, reload); - - /* Clear the advanced timers repetition counter in TIM1 */ - - if (priv->tbase == STM32_TIM1_BASE) - { - tim_putreg(priv, STM32_ATIM_RCR_OFFSET, 0); - tim_putreg(priv, STM32_ATIM_BDTR_OFFSET, ATIM_BDTR_MOE); /* Check me */ - } - - /* TIMx event generation: Bit 0 UG: Update generation */ - - tim_putreg(priv, STM32_GTIM_EGR_OFFSET, GTIM_EGR_UG); - - /* Handle channel specific setup */ - - ocmode1 = 0; - ocmode2 = 0; - - switch (priv->trigger) - { - case 0: /* TimerX CC1 event */ - { - ccenable = ATIM_CCER_CC1E; - ocmode1 = (ATIM_CCMR_CCS_CCOUT << ATIM_CCMR1_CC1S_SHIFT) | - (ATIM_CCMR_MODE_PWM1 << ATIM_CCMR1_OC1M_SHIFT) | - ATIM_CCMR1_OC1PE; - - /* Set the event CC1 */ - - egr = ATIM_EGR_CC1G; - - /* Set the duty cycle by writing to the CCR register for this - * channel - */ - - tim_putreg(priv, STM32_GTIM_CCR1_OFFSET, (uint16_t)(reload >> 1)); - } - break; - - case 1: /* TimerX CC2 event */ - { - ccenable = ATIM_CCER_CC2E; - ocmode1 = (ATIM_CCMR_CCS_CCOUT << ATIM_CCMR1_CC2S_SHIFT) | - (ATIM_CCMR_MODE_PWM1 << ATIM_CCMR1_OC2M_SHIFT) | - ATIM_CCMR1_OC2PE; - - /* Set the event CC2 */ - - egr = ATIM_EGR_CC2G; - - /* Set the duty cycle by writing to the CCR register for this - * channel - */ - - tim_putreg(priv, STM32_GTIM_CCR2_OFFSET, (uint16_t)(reload >> 1)); - } - break; - - case 2: /* TimerX CC3 event */ - { - ccenable = ATIM_CCER_CC3E; - ocmode2 = (ATIM_CCMR_CCS_CCOUT << ATIM_CCMR2_CC3S_SHIFT) | - (ATIM_CCMR_MODE_PWM1 << ATIM_CCMR2_OC3M_SHIFT) | - ATIM_CCMR2_OC3PE; - - /* Set the event CC3 */ - - egr = ATIM_EGR_CC3G; - - /* Set the duty cycle by writing to the CCR register for this - * channel - */ - - tim_putreg(priv, STM32_GTIM_CCR3_OFFSET, (uint16_t)(reload >> 1)); - } - break; - - case 3: /* TimerX CC4 event */ - { - ccenable = ATIM_CCER_CC4E; - ocmode2 = (ATIM_CCMR_CCS_CCOUT << ATIM_CCMR2_CC4S_SHIFT) | - (ATIM_CCMR_MODE_PWM1 << ATIM_CCMR2_OC4M_SHIFT) | - ATIM_CCMR2_OC4PE; - - /* Set the event CC4 */ - - egr = ATIM_EGR_CC4G; - - /* Set the duty cycle by writing to the CCR register for this - * channel - */ - - tim_putreg(priv, STM32_GTIM_CCR4_OFFSET, (uint16_t)(reload >> 1)); - } - break; - - case 4: /* TimerX TRGO event */ - { - /* Set the event TRGO */ - - ccenable = 0; - egr = GTIM_EGR_TG; - - tim_modifyreg(priv, STM32_GTIM_CR2_OFFSET, clrbits, - GTIM_CR2_MMS_UPDATE); - } - break; - - case 5: /* TimerX TRGO2 event */ - { - /* Set the event TRGO2 */ - - ccenable = 0; - egr = GTIM_EGR_TG; - - tim_modifyreg32(priv, STM32_GTIM_CR2_OFFSET, clrbits, - ATIM_CR2_MMS2_UPDATE); - } - break; - - default: - aerr("ERROR: No such trigger: %d\n", priv->trigger); - return -EINVAL; - } - - /* Disable the Channel by resetting the CCxE Bit in the CCER register */ - - ccer = tim_getreg(priv, STM32_GTIM_CCER_OFFSET); - ccer &= ~ccenable; - tim_putreg(priv, STM32_GTIM_CCER_OFFSET, ccer); - - /* Fetch the CR2, CCMR1, and CCMR2 register (already have ccer) */ - - cr2 = tim_getreg(priv, STM32_GTIM_CR2_OFFSET); - ccmr1 = tim_getreg(priv, STM32_GTIM_CCMR1_OFFSET); - ccmr2 = tim_getreg(priv, STM32_GTIM_CCMR2_OFFSET); - - /* Reset the Output Compare Mode Bits and set the select output compare - * mode - */ - - ccmr1 &= ~(ATIM_CCMR1_CC1S_MASK | ATIM_CCMR1_OC1M_MASK | ATIM_CCMR1_OC1PE | - ATIM_CCMR1_CC2S_MASK | ATIM_CCMR1_OC2M_MASK | ATIM_CCMR1_OC2PE); - ccmr2 &= ~(ATIM_CCMR2_CC3S_MASK | ATIM_CCMR2_OC3M_MASK | ATIM_CCMR2_OC3PE | - ATIM_CCMR2_CC4S_MASK | ATIM_CCMR2_OC4M_MASK | ATIM_CCMR2_OC4PE); - ccmr1 |= ocmode1; - ccmr2 |= ocmode2; - - /* Reset the output polarity level of all channels (selects high - * polarity) - */ - - ccer &= ~(ATIM_CCER_CC1P | ATIM_CCER_CC2P | - ATIM_CCER_CC3P | ATIM_CCER_CC4P); - - /* Enable the output state of the selected channel (only) */ - - ccer &= ~(ATIM_CCER_CC1E | ATIM_CCER_CC2E | - ATIM_CCER_CC3E | ATIM_CCER_CC4E); - ccer |= ccenable; - - if (priv->tbase == STM32_TIM1_BASE) - { - /* Reset output N polarity level, output N state, output compare state, - * output compare N idle state. - */ - - ccer &= ~(ATIM_CCER_CC1NE | ATIM_CCER_CC1NP | - ATIM_CCER_CC2NE | ATIM_CCER_CC2NP | - ATIM_CCER_CC3NE | ATIM_CCER_CC3NP | - ATIM_CCER_CC4NP); - - /* Reset the output compare and output compare N IDLE State */ - - cr2 &= ~(ATIM_CR2_OIS1 | ATIM_CR2_OIS1N | - ATIM_CR2_OIS2 | ATIM_CR2_OIS2N | - ATIM_CR2_OIS3 | ATIM_CR2_OIS3N | - ATIM_CR2_OIS4); - } - else - { - ccer &= ~(GTIM_CCER_CC1NP | GTIM_CCER_CC2NP | GTIM_CCER_CC3NP); - } - - /* Reset the output compare and output compare N IDLE State */ - - if (priv->tbase >= STM32_TIM2_BASE && priv->tbase <= STM32_TIM3_BASE) - { - /* Reset output N polarity level, output N state, output compare state, - * output compare N idle state. - */ - - ccer &= ~(GTIM_CCER_CC1NE | GTIM_CCER_CC1NP | - GTIM_CCER_CC2NP | GTIM_CCER_CC3NP | - GTIM_CCER_CC4NP); - } - - /* Save the modified register values */ - - tim_putreg(priv, STM32_GTIM_CR2_OFFSET, cr2); - tim_putreg(priv, STM32_GTIM_CCMR1_OFFSET, ccmr1); - tim_putreg(priv, STM32_GTIM_CCMR2_OFFSET, ccmr2); - tim_putreg(priv, STM32_GTIM_CCER_OFFSET, ccer); - tim_putreg(priv, STM32_GTIM_EGR_OFFSET, egr); - - /* Set the ARR Preload Bit */ - - tim_modifyreg(priv, STM32_GTIM_CR1_OFFSET, 0, GTIM_CR1_ARPE); - - /* Enable the timer counter */ - - adc_timstart(priv, true); - - tim_dumpregs(priv, "After starting timers"); - - return OK; -} -#endif - -/**************************************************************************** - * Name: adc_reg_startconv - * - * Description: - * Start (or stop) the ADC regular conversion process - * - * Input Parameters: - * priv - A reference to the ADC block status - * enable - True: Start conversion - * - * Returned Value: - * - ****************************************************************************/ - -static void adc_reg_startconv(struct stm32_dev_s *priv, bool enable) -{ - uint32_t regval; - - ainfo("reg enable: %d\n", enable ? 1 : 0); - - if (enable) - { - /* Start the conversion of regular channels */ - - adc_modifyreg(priv, STM32_ADC_CR_OFFSET, 0, ADC_CR_ADSTART); - } - else - { - regval = adc_getreg(priv, STM32_ADC_CR_OFFSET); - - /* Is a conversion ongoing? */ - - if ((regval & ADC_CR_ADSTART) != 0) - { - /* Stop the conversion */ - - adc_putreg(priv, STM32_ADC_CR_OFFSET, regval | ADC_CR_ADSTP); - - /* Wait for the conversion to stop */ - - while ((adc_getreg(priv, STM32_ADC_CR_OFFSET) & - ADC_CR_ADSTP) != 0); - } - } -} - -/**************************************************************************** - * Name: adc_rccreset - * - * Description: - * Deinitializes the ADCx peripheral registers to their default - * reset values. It could set all the ADCs configured. - * - * Input Parameters: - * regaddr - The register to read - * reset - Condition, set or reset - * - * Returned Value: - * - ****************************************************************************/ - -static void adc_rccreset(struct stm32_dev_s *priv, bool reset) -{ - uint32_t adcbit; - - /* Pick the appropriate bit in the RCC reset register. - * For the STM32 ADC IPv2, there is an individual bit to reset each ADC - * block. - */ - - switch (priv->intf) - { -#if defined(CONFIG_STM32F0L0G0_ADC1) - case 1: - { - adcbit = RCC_RSTR_ADC1RST; - break; - } - -#endif - default: - { - return; - } - } - - /* Set or clear the selected bit in the RCC reset register */ - - if (reset) - { - /* Enable ADC reset state */ - - modifyreg32(STM32_RCC_RSTR, 0, adcbit); - } - else - { - /* Release ADC from reset state */ - - modifyreg32(STM32_RCC_RSTR, adcbit, 0); - } -} - -/**************************************************************************** - * Name: adc_enable - * - * Description: - * Enables or disables the specified ADC peripheral. Also, starts a - * conversion when the ADC is not triggered by timers - * - * Input Parameters: - * - * enable - true: enable ADC conversion - * false: disable ADC conversion - * - * Returned Value: - * - ****************************************************************************/ - -static void adc_enable(struct stm32_dev_s *priv, bool enable) -{ - uint32_t regval; - - ainfo("enable: %d\n", enable ? 1 : 0); - - regval = adc_getreg(priv, STM32_ADC_CR_OFFSET); - - if (enable) - { - /* Enable the ADC */ - - adc_putreg(priv, STM32_ADC_CR_OFFSET, regval | ADC_CR_ADEN); - - /* Wait for the ADC to be ready */ - - while ((adc_getreg(priv, STM32_ADC_ISR_OFFSET) & ADC_INT_ARDY) == 0); - } - else if ((regval & ADC_CR_ADEN) != 0 && (regval & ADC_CR_ADDIS) == 0) - { - /* Stop ongoing regular conversions */ - - adc_reg_startconv(priv, false); - - /* Disable the ADC */ - - adc_putreg(priv, STM32_ADC_CR_OFFSET, regval | ADC_CR_ADDIS); - - /* Wait for the ADC to be disabled */ - - while ((adc_getreg(priv, STM32_ADC_CR_OFFSET) & ADC_CR_ADEN) != 0); - } -} - -/**************************************************************************** - * Name: adc_dmaconvcallback - * - * Description: - * Callback for DMA. Called from the DMA transfer complete interrupt after - * all channels have been converted and transferred with DMA. - * - * Input Parameters: - * - * handle - handle to DMA - * isr - - * arg - adc device - * - * Returned Value: - * - ****************************************************************************/ - -#if defined(ADC_HAVE_DMA) -static void adc_dmaconvcallback(DMA_HANDLE handle, uint8_t isr, - void *arg) -{ - struct adc_dev_s *dev = (struct adc_dev_s *)arg; - struct stm32_dev_s *priv = (struct stm32_dev_s *)dev->ad_priv; - int i; - - /* Verify that the upper-half driver has bound its callback functions */ - - if (priv->cb != NULL) - { - DEBUGASSERT(priv->cb->au_receive != NULL); - - for (i = 0; i < priv->rnchannels * priv->dmabatch; i++) - { - priv->cb->au_receive(dev, priv->r_chanlist[priv->current], - priv->r_dmabuffer[i]); - priv->current++; - if (priv->current >= priv->rnchannels) - { - /* Restart the conversion sequence from the beginning */ - - priv->current = 0; - } - } - } - - /* Restart DMA for the next conversion series */ - - adc_modifyreg(priv, STM32_ADC_DMAREG_OFFSET, ADC_DMAREG_DMA, 0); - adc_modifyreg(priv, STM32_ADC_DMAREG_OFFSET, 0, ADC_DMAREG_DMA); -} -#endif - -/**************************************************************************** - * Name: adc_bind - * - * Description: - * Bind the upper-half driver callbacks to the lower-half implementation. - * This must be called early in order to receive ADC event notifications. - * - ****************************************************************************/ - -static int adc_bind(struct adc_dev_s *dev, - const struct adc_callback_s *callback) -{ -#ifndef CONFIG_STM32F0L0G0_ADC_NOIRQ - struct stm32_dev_s *priv = (struct stm32_dev_s *)dev->ad_priv; - - DEBUGASSERT(priv != NULL); - priv->cb = callback; -#endif - - return OK; -} - -/**************************************************************************** - * Name: adc_watchdog_cfg - ****************************************************************************/ - -static void adc_watchdog_cfg(struct stm32_dev_s *priv) -{ - uint32_t clrbits = 0; - uint32_t setbits = 0; - - uint32_t th = 0; - - /* Initialize the watchdog high threshold register */ - - th |= 0x0fff << ADC_TR_HT_SHIFT; - - /* Initialize the watchdog low threshold register */ - - th |= 0x0000 << ADC_TR_LT_SHIFT; - - /* Write threshold register */ - - adc_putreg(priv, STM32_ADC_TR_OFFSET, th); - - clrbits = ADC_CFGR1_AWDCH_MASK; - setbits = ADC_CFGR1_AWDEN | (priv->r_chanlist[0] << ADC_CFGR1_AWDCH_SHIFT); - - /* Modify CFGR1 configuration */ - - adc_modifyreg(priv, STM32_ADC_CFGR1_OFFSET, clrbits, setbits); -} - -/**************************************************************************** - * Name: adc_calibrate - ****************************************************************************/ - -static void adc_calibrate(struct stm32_dev_s *priv) -{ - /* Calibrate the ADC. - * 1. ADC must be disabled - * 2. the voltage regulator must be enabled - */ - - adc_modifyreg(priv, STM32_ADC_CR_OFFSET, 0, ADC_CR_ADCAL); - - /* Wait for the calibration to complete */ - - while ((adc_getreg(priv, STM32_ADC_CR_OFFSET) & ADC_CR_ADCAL) != 0); -} - -/**************************************************************************** - * Name: adc_mode_cfg - ****************************************************************************/ - -static void adc_mode_cfg(struct stm32_dev_s *priv) -{ - uint32_t clrbits = 0; - uint32_t setbits = 0; - - /* Disable continuous mode and set align to right */ - - clrbits = ADC_CFGR1_CONT | ADC_CFGR1_ALIGN; - - /* Disable external trigger for regular channels */ - - clrbits |= ADC_CFGR1_EXTEN_MASK; - setbits |= ADC_CFGR1_EXTEN_NONE; - -#ifdef CONFIG_STM32F0L0G0_ADC1_CONTINUOUS - setbits |= ADC_CFGR1_CONT; -#endif - - /* Set CFGR configuration */ - - adc_modifyreg(priv, STM32_ADC_CFGR1_OFFSET, clrbits, setbits); -} - -/**************************************************************************** - * Name: adc_voltreg_cfg - ****************************************************************************/ - -static void adc_voltreg_cfg(struct stm32_dev_s *priv) -{ - /* Enable voltage regulator - required by ADC calibration */ - - adc_putreg(priv, STM32_ADC_CR_OFFSET, ADC_CR_ADVREGEN); - - /* Wait for ADC voltage regulator start-up */ - - up_udelay(50); -} - -/**************************************************************************** - * Name: adc_sampletime_cfg - ****************************************************************************/ - -static void adc_sampletime_cfg(struct adc_dev_s *dev) -{ - /* Initialize the same sample time for each ADC. - * During sample cycles channel selection bits must remain unchanged. - */ -#ifdef CONFIG_STM32F0L0G0_ADC_CHANGE_SAMPLETIME - struct adc_sample_time_s time_samples = { -# ifdef STM32_ADC1_SMPR_SMP1 - .smp1 = STM32_ADC1_SMPR_SMP1, -# else - .smp1 = ADC_SMP1_DEFAULT, -# endif - -# ifdef ADC_HAVE_SMPR_SMP2 -# ifdef STM32_ADC1_SMPR_SMP2 - .smp2 = STM32_ADC1_SMPR_SMP2, -# else - .smp2 = ADC_SMP2_DEFAULT, -# endif - -# ifdef STM32_ADC1_SMPR_SMPSEL - .smpsel = STM32_ADC1_SMPR_SMPSEL -# else - .smpsel = ADC_SMPSEL_DEFAULT -# endif -# else - .smp2 = 0, - .smpsel = 0 -# endif - }; - - adc_sampletime_set((struct stm32_adc_dev_s *)dev, &time_samples); - adc_sampletime_write((struct stm32_adc_dev_s *)dev); -#else - struct stm32_dev_s *priv = (struct stm32_dev_s *)dev->ad_priv; - uint32_t setbits = 0; - - /* Configure sample time 1 */ - - setbits |= ADC_SMP1_DEFAULT << ADC_SMPR_SMP1_SHIFT; - -#ifdef ADC_HAVE_SMPR_SMP2 - /* Configure sample time 2 */ - - setbits |= ADC_SMP2_DEFAULT << ADC_SMPR_SMP2_SHIFT; - - /* Configure sample time selection */ - - setbits |= ADC_SMPSEL_DEFAULT << ADC_SMPR_SMPSEL_SHIFT; -#endif - - /* Write SMPR register */ - - adc_putreg(priv, STM32_ADC_SMPR_OFFSET, setbits); -#endif -} - -/**************************************************************************** - * Name: adc_ckmode_cfg - ****************************************************************************/ - -static void adc_ckmode_cfg(struct stm32_dev_s *priv) -{ - uint32_t setbits = 0; - uint32_t clearbits = ADC_CFGR2_CKMODE_MASK; - -#ifdef STM32_ADC_CFGR2_CKMODE - setbits |= STM32_ADC_CFGR2_CKMODE; -#endif - - adc_modifyreg(priv, STM32_ADC_CFGR2_OFFSET, clearbits, setbits); -} - -/**************************************************************************** - * Name: adc_common_cfg - ****************************************************************************/ - -static void adc_common_cfg(struct stm32_dev_s *priv) -{ - uint32_t clrbits = 0; - uint32_t setbits = 0; - -#ifdef STM32_ADC_CCR_PRESC - setbits |= STM32_ADC_CCR_PRESC; -#endif - - /* REVISIT: for now we reset all CCR bits */ - - clrbits |= ADC_CCR_PRESC_MASK | ADC_CCR_VREFEN | - ADC_CCR_TSEN; - -#ifdef HAVE_ADC_VBAT - clrbits |= ADC_CCR_VBATEN; -#endif - -#ifdef HAVE_ADC_VLCD - clrbits |= ADC_CCR_PRESC_MASK; -#endif - -#ifdef HAVE_ADC_VLCD - clrbits |= ADC_CCR_VLCDEN; -#endif - -#ifdef HAVE_ADC_LFM - clrbits |= ADC_CCR_LFMEN; -#endif - - adccmn_modifyreg(priv, STM32_ADC_CCR_OFFSET, clrbits, setbits); -} - -#ifdef ADC_HAVE_DMA -/**************************************************************************** - * Name: adc_dma_cfg - ****************************************************************************/ - -static void adc_dma_cfg(struct stm32_dev_s *priv) -{ - uint32_t clrbits = 0; - uint32_t setbits = 0; - - /* Set DMA mode */ - - if (priv->dmacfg == 0) - { - /* One Shot Mode */ - - clrbits |= ADC_CFGR1_DMACFG; - } - else - { - /* Circular Mode */ - - setbits |= ADC_CFGR1_DMACFG; - } - - /* Enable DMA */ - - setbits |= ADC_CFGR1_DMAEN; - - /* Modify CFGR configuration */ - - adc_modifyreg(priv, STM32_ADC_CFGR1_OFFSET, clrbits, setbits); -} - -/**************************************************************************** - * Name: adc_dma_start - ****************************************************************************/ - -static void adc_dma_start(struct adc_dev_s *dev) -{ - struct stm32_dev_s *priv = (struct stm32_dev_s *)dev->ad_priv; - - /* Stop and free DMA if it was started before */ - - if (priv->dma != NULL) - { - stm32_dmastop(priv->dma); - stm32_dmafree(priv->dma); - } - - priv->dma = stm32_dmachannel(priv->dmachan); - - stm32_dmasetup(priv->dma, - priv->base + STM32_ADC_DR_OFFSET, - (uint32_t)priv->r_dmabuffer, - priv->rnchannels * priv->dmabatch, - ADC_DMA_CONTROL_WORD); - - stm32_dmastart(priv->dma, adc_dmaconvcallback, dev, false); -} -#endif /* ADC_HAVE_DMA */ - -/**************************************************************************** - * Name: adc_configure - ****************************************************************************/ - -static void adc_configure(struct adc_dev_s *dev) -{ - struct stm32_dev_s *priv = (struct stm32_dev_s *)dev->ad_priv; - - /* Turn off the ADC before configuration */ - - adc_enable(priv, false); - - /* Configure voltage regulator if present */ - - adc_voltreg_cfg(priv); - - /* Calibrate ADC */ - - adc_calibrate(priv); - - /* Initialize the ADC watchdog */ - - adc_watchdog_cfg(priv); - - /* Initialize the ADC sample time */ - - adc_sampletime_cfg(dev); - - /* Set ADC working mode */ - - adc_mode_cfg(priv); - - /* Configuration of the channel conversions */ - - if (priv->cr_channels > 0) - { - adc_set_ch(dev, 0); - } - - /* ADC clock mode configuration */ - - adc_ckmode_cfg(priv); - - /* ADC common register configuration */ - - adc_common_cfg(priv); - -#ifdef ADC_HAVE_DMA - /* Configure ADC DMA if enabled */ - - if (priv->hasdma) - { - /* Configure ADC DMA */ - - adc_dma_cfg(priv); - - /* Start ADC DMA */ - - adc_dma_start(dev); - } -#endif - -#ifdef HAVE_ADC_RESOLUTION - /* Configure ADC resolution */ - - adc_resolution_set(dev, priv->resolution); -#endif - -#ifdef ADC_HAVE_EXTCFG - /* Configure external event for regular group */ - - adc_extcfg_set(dev, priv->extcfg); -#endif - - /* Enable ADC */ - - adc_enable(priv, true); - - /* Dump regs */ - - adc_dumpregs(priv); -} - - #ifdef CONFIG_STM32F0L0G0_ADC_OVERSAMPLE - -/**************************************************************************** - * Name: adc_oversample - ****************************************************************************/ - -static void adc_oversample(struct adc_dev_s *dev) -{ - struct stm32_dev_s *priv = (struct stm32_dev_s *)dev->ad_priv; - - uint32_t clrbits = ADC_CFGR2_OVSE | ADC_CFGR2_TOVS | - ADC_CFGR2_OVSR_MASK | ADC_CFGR2_OVSS_MASK; - - uint32_t setbits = ADC_CFGR2_OVSE | - (CONFIG_STM32F0L0G0_ADC_OVSR << ADC_CFGR2_OVSR_SHIFT) | - (CONFIG_STM32F0L0G0_ADC_OVSS << ADC_CFGR2_OVSS_SHIFT); - -# ifdef CONFIG_STM32F0L0G0_ADC_TOVS - setbits |= ADC_CFGR2_TOVS; -# endif - - adc_modifyreg(priv, STM32_ADC_CFGR2_OFFSET, clrbits, setbits); -} -#endif - -/**************************************************************************** - * Name: adc_reset - * - * Description: - * Reset the ADC device. Called early to initialize the hardware. - * This is called, before adc_setup() and on error conditions. - * - * Input Parameters: - * - * Returned Value: - * - ****************************************************************************/ - -static void adc_reset(struct adc_dev_s *dev) -{ - struct stm32_dev_s *priv = (struct stm32_dev_s *)dev->ad_priv; - irqstate_t flags; - - ainfo("intf: %d\n", priv->intf); - flags = enter_critical_section(); - -#if defined(HAVE_IP_ADC_V2) - /* Turn off the ADC so we can write the RCC bits */ - - adc_enable(priv, false); -#endif - - /* Only if this is the first initialzied ADC instance in the ADC block */ - -#ifdef HAVE_ADC_CMN_DATA - if (nxmutex_lock(&priv->cmn->lock) < 0) - { - leave_critical_section(flags); - return; - } - - if (priv->cmn->initialized == 0) -#endif - { - /* Enable ADC reset state */ - - adc_rccreset(priv, true); - - /* Release ADC from reset state */ - - adc_rccreset(priv, false); - } - -#ifdef HAVE_ADC_CMN_DATA - nxmutex_unlock(&priv->cmn->lock); -#endif - - leave_critical_section(flags); -} - -/**************************************************************************** - * Name: adc_setup - * - * Description: - * Configure the ADC. This method is called the first time that the ADC - * device is opened. This will occur when the port is first opened. - * This setup includes configuring and attaching ADC interrupts. - * Interrupts are all disabled upon return. - * - * Input Parameters: - * - * Returned Value: - * - ****************************************************************************/ - -static int adc_setup(struct adc_dev_s *dev) -{ -#if !defined(CONFIG_STM32F0L0G0_ADC_NOIRQ) || defined(HAVE_ADC_CMN_DATA) || \ - defined(ADC_HAVE_TIMER) || !defined(CONFIG_STM32F0L0G0_ADC_NO_STARTUP_CONV) - struct stm32_dev_s *priv = (struct stm32_dev_s *)dev->ad_priv; -#endif - int ret = OK; - - /* Attach the ADC interrupt */ - -#ifndef CONFIG_STM32F0L0G0_ADC_NOIRQ - ret = irq_attach(priv->irq, priv->isr, NULL); - if (ret < 0) - { - ainfo("irq_attach failed: %d\n", ret); - return ret; - } -#endif - - /* Make sure that the ADC device is in the powered up, reset state */ - - adc_reset(dev); - - /* Configure ADC device */ - - adc_configure(dev); - -#ifdef CONFIG_STM32F0L0G0_ADC_OVERSAMPLE - adc_oversample(dev); -#endif - -#ifdef ADC_HAVE_TIMER - /* Configure timer */ - - if (priv->tbase != 0) - { - ret = adc_timinit(priv); - if (ret < 0) - { - aerr("ERROR: adc_timinit failed: %d\n", ret); - } - } -#endif - - /* As default conversion is started here. - * - * NOTE: for ADC IPv2 (J)ADSTART bit must be set to start ADC conversion - * even if hardware trigger is selected. - * This can be done here during the opening of the ADC device - * or later with ANIOC_TRIGGER ioctl call. - */ - -#ifndef CONFIG_STM32F0L0G0_ADC_NO_STARTUP_CONV - /* Start regular conversion */ - - adc_reg_startconv(priv, true); - -#endif - - /* Enable the ADC interrupt */ - -#ifndef CONFIG_STM32F0L0G0_ADC_NOIRQ - ainfo("Enable the ADC interrupt: irq=%d\n", priv->irq); - up_enable_irq(priv->irq); -#endif - -#ifdef HAVE_ADC_CMN_DATA - /* Increase instances counter */ - - ret = nxmutex_lock(&priv->cmn->lock); - if (ret < 0) - { - return; - } - - priv->cmn->initialized += 1; - nxmutex_unlock(&priv->cmn->lock); -#endif - - return ret; -} - -/**************************************************************************** - * Name: adc_shutdown - * - * Description: - * Disable the ADC. This method is called when the ADC device is closed. - * This method reverses the operation the setup method. - * - * Input Parameters: - * - * Returned Value: - * - ****************************************************************************/ - -static void adc_shutdown(struct adc_dev_s *dev) -{ - struct stm32_dev_s *priv = (struct stm32_dev_s *)dev->ad_priv; - - /* Disable ADC */ - - adc_enable(priv, false); - -#ifndef CONFIG_STM32F0L0G0_ADC_NOIRQ - /* Disable ADC interrupts and detach the ADC interrupt handler */ - - up_disable_irq(priv->irq); - irq_detach(priv->irq); -#endif - -#ifdef HAVE_ADC_CMN_DATA - if (nxmutex_lock(&priv->cmn->lock) < 0) - { - return; - } - - if (priv->cmn->initialized <= 1) -#endif - { - /* Disable and reset the ADC module. - * - * NOTE: The ADC block will be reset to its reset state only if all - * ADC block instances are closed. This means that the closed ADC - * may not be reset which in turn may affect low-power - * applications. (But ADC is turned off here, is not that - * enough?) - */ - - adc_rccreset(priv, true); - } - -#ifdef ADC_HAVE_TIMER - /* Disable timer */ - - if (priv->tbase != 0) - { - adc_timstart(priv, false); - } -#endif - -#ifdef HAVE_ADC_CMN_DATA - /* Decrease instances counter */ - - priv->cmn->initialized -= 1; - nxmutex_unlock(&priv->cmn->lock); -#endif -} - -/**************************************************************************** - * Name: adc_rxint - * - * Description: - * Call to enable or disable RX interrupts. - * - * Input Parameters: - * - * Returned Value: - * - ****************************************************************************/ - -static void adc_rxint(struct adc_dev_s *dev, bool enable) -{ - struct stm32_dev_s *priv = (struct stm32_dev_s *)dev->ad_priv; - uint32_t regval; - - ainfo("intf: %d enable: %d\n", priv->intf, enable ? 1 : 0); - - if (enable) - { - /* Enable the analog watchdog / overrun interrupts, and if no DMA, - * end-of-conversion ADC. - */ - - regval = ADC_IER_ALLINTS; -#ifdef ADC_HAVE_DMA - if (priv->hasdma) - { - regval &= ~(ADC_IER_EOC); - } -#endif - - adc_modifyreg(priv, STM32_ADC_IER_OFFSET, 0, regval); - } - else - { - /* Disable all ADC interrupts */ - - adc_modifyreg(priv, STM32_ADC_IER_OFFSET, ADC_IER_ALLINTS, 0); - } -} - -/**************************************************************************** - * Name: adc_resolution_set - ****************************************************************************/ - -#ifdef HAVE_ADC_RESOLUTION -static int adc_resolution_set(struct adc_dev_s *dev, uint8_t res) -{ - struct stm32_dev_s *priv = (struct stm32_dev_s *)dev->ad_priv; - int ret = OK; - - /* Check input */ - - if (res > 3) - { - ret = -EINVAL; - goto errout; - } - - /* Modify appropriate register */ - - adc_modifyreg(priv, STM32_ADC_CFGR1_OFFSET, ADC_CFGR1_RES_MASK, - res << ADC_CFGR1_RES_SHIFT); - -errout: - return ret; -} -#endif - -/**************************************************************************** - * Name: adc_extsel_set - ****************************************************************************/ - -#ifdef ADC_HAVE_EXTCFG -static int adc_extcfg_set(struct adc_dev_s *dev, uint32_t extcfg) -{ - struct stm32_dev_s *priv = (struct stm32_dev_s *)dev->ad_priv; - uint32_t exten = 0; - uint32_t extsel = 0; - uint32_t setbits = 0; - uint32_t clrbits = 0; - - /* Get EXTEN and EXTSEL from input */ - - exten = (extcfg & ADC_EXTREG_EXTEN_MASK); - extsel = (extcfg & ADC_EXTREG_EXTSEL_MASK); - - /* EXTSEL selection: These bits select the external event used - * to trigger the start of conversion of a regular group. NOTE: - * - * - The position with of the EXTSEL field varies from one STM32 MCU - * to another. - * - The width of the EXTSEL field varies from one STM32 MCU to another. - */ - - if (exten > 0) - { - setbits = (extsel | exten); - clrbits = (ADC_EXTREG_EXTEN_MASK | ADC_EXTREG_EXTSEL_MASK); - - ainfo("Initializing extsel = 0x%" PRIx32 "\n", extsel); - - /* Write register */ - - adc_modifyreg(priv, STM32_ADC_EXTREG_OFFSET, clrbits, setbits); - } - - return OK; -} -#endif - -/**************************************************************************** - * Name: adc_dumpregs - ****************************************************************************/ - -static void adc_dumpregs(struct stm32_dev_s *priv) -{ - UNUSED(priv); - - ainfo("ISR: 0x%08" PRIx32 " IER: 0x%08" PRIx32 - " CR: 0x%08" PRIx32 " CFGR1: 0x%08" PRIx32 "\n", - adc_getreg(priv, STM32_ADC_ISR_OFFSET), - adc_getreg(priv, STM32_ADC_IER_OFFSET), - adc_getreg(priv, STM32_ADC_CR_OFFSET), - adc_getreg(priv, STM32_ADC_CFGR1_OFFSET)); - - ainfo("SMPR: 0x%08" PRIx32 " CHSELR: 0x%08" PRIx32 "\n", - adc_getreg(priv, STM32_ADC_SMPR_OFFSET), - adc_getreg(priv, STM32_ADC_CHSELR_OFFSET)); - - ainfo("CCR: 0x%08" PRIx32 "\n", - adccmn_getreg(priv, STM32_ADC_CCR_OFFSET)); -} - -/**************************************************************************** - * Name: adc_enable_vbat_channel - * - * Description: - * Enable/disable the Vbat voltage measurement channel. - * - * Input Parameters: - * dev - pointer to device structure used by the driver - * enable - true: Vbat input channel enabled (ch 18) - * false: Vbat input channel disabled (ch 18) - * - * Returned Value: - * None. - * - ****************************************************************************/ - -#ifdef HAVE_ADC_VBAT -static void adc_enable_vbat_channel(struct adc_dev_s *dev, bool enable) -{ - struct stm32_dev_s *priv = (struct stm32_dev_s *)dev->ad_priv; - - if (enable) - { - adccmn_modifyreg(priv, STM32_ADC_CCR_OFFSET, 0, ADC_CCR_VBATEN); - } - else - { - adccmn_modifyreg(priv, STM32_ADC_CCR_OFFSET, ADC_CCR_VBATEN, 0); - } - - ainfo("STM32_ADC_CCR value: 0x%08" PRIx32 "\n", - adccmn_getreg(priv, STM32_ADC_CCR_OFFSET)); -} -#endif - -/**************************************************************************** - * Name: adc_ioc_change_sleep_between_opers - * - * Description: - * Changes PDI and PDD bits to save battery. - * - * Input Parameters: - * dev - pointer to device structure used by the driver - * cmd - command - * arg - arguments passed with command - * - * Returned Value: - * - ****************************************************************************/ - -#ifdef HAVE_ADC_POWERDOWN -static int adc_ioc_change_sleep_between_opers(struct adc_dev_s *dev, - int cmd, bool arg) -{ - int ret = OK; - struct stm32_dev_s *priv = (struct stm32_dev_s *)dev->ad_priv; - - adc_enable(priv, false); - - switch (cmd) - { - case IO_ENABLE_DISABLE_PDI: - adc_power_down_idle(priv, arg); - break; - - case IO_ENABLE_DISABLE_PDD: - adc_power_down_delay(priv, arg); - break; - - case IO_ENABLE_DISABLE_PDD_PDI: - adc_power_down_idle(priv, arg); - adc_power_down_delay(priv, arg); - break; - - default: - ainfo("unknown cmd: %d\n", cmd); - break; - } - - adc_enable(priv, true); - - return ret; -} -#endif - -/**************************************************************************** - * Name: adc_ioc_enable_awd_int - * - * Description: - * Turns ON/OFF ADC analog watchdog interrupt. - * - * Input Parameters: - * dev - pointer to device structure used by the driver - * arg - true: Turn ON interrupt - * false: Turn OFF interrupt - * - * Returned Value: - * - ****************************************************************************/ - -static void adc_ioc_enable_awd_int(struct stm32_dev_s *priv, bool enable) -{ - if (enable) - { - adc_modifyreg(priv, STM32_ADC_IER_OFFSET, 0, ADC_IER_AWD); - } - else - { - adc_modifyreg(priv, STM32_ADC_IER_OFFSET, ADC_IER_AWD, 0); - } -} - -/**************************************************************************** - * Name: adc_ioc_enable_eoc_int - * - * Description: - * Turns ON/OFF ADC EOC interrupt. - * - * Input Parameters: - * dev - pointer to device structure used by the driver - * arg - true: Turn ON interrupt - * false: Turn OFF interrupt - * - * Returned Value: - * - ****************************************************************************/ - -static void adc_ioc_enable_eoc_int(struct stm32_dev_s *priv, bool enable) -{ - if (enable) - { - adc_modifyreg(priv, STM32_ADC_IER_OFFSET, 0, ADC_IER_EOC); - } - else - { - adc_modifyreg(priv, STM32_ADC_IER_OFFSET, ADC_IER_EOC, 0); - } -} - -/**************************************************************************** - * Name: adc_ioc_enable_ovr_int - * - * Description: - * Turns ON/OFF ADC overrun interrupt. - * - * Input Parameters: - * dev - pointer to device structure used by the driver - * arg - true: Turn ON interrupt - * false: Turn OFF interrupt - * - * Returned Value: - * - ****************************************************************************/ - -static void adc_ioc_enable_ovr_int(struct stm32_dev_s *priv, bool enable) -{ - if (enable) - { - adc_modifyreg(priv, STM32_ADC_IER_OFFSET, 0, ADC_IER_OVR); - } - else - { - adc_modifyreg(priv, STM32_ADC_IER_OFFSET, ADC_IER_OVR, 0); - } -} - -/**************************************************************************** - * Name: adc_ioc_change_ints - * - * Description: - * Turns ON/OFF ADC interrupts. - * - * Input Parameters: - * dev - pointer to device structure used by the driver - * cmd - command - * arg - arguments passed with command - * - * Returned Value: - * - ****************************************************************************/ - -static int adc_ioc_change_ints(struct adc_dev_s *dev, int cmd, bool arg) -{ - int ret = OK; - struct stm32_dev_s *priv = (struct stm32_dev_s *)dev->ad_priv; - - switch (cmd) - { - case IO_ENABLE_DISABLE_AWDIE: - adc_ioc_enable_awd_int(priv, arg); - break; - - case IO_ENABLE_DISABLE_EOCIE: - adc_ioc_enable_eoc_int(priv, arg); - break; - - case IO_ENABLE_DISABLE_OVRIE: - adc_ioc_enable_ovr_int(priv, arg); - break; - - case IO_ENABLE_DISABLE_ALL_INTS: - adc_ioc_enable_awd_int(priv, arg); - adc_ioc_enable_eoc_int(priv, arg); - adc_ioc_enable_ovr_int(priv, arg); - break; - - default: - ainfo("unknown cmd: %d\n", cmd); - break; - } - - return ret; -} -#ifdef CONFIG_STM32F0L0G0_ADC_OVERSAMPLE - -/**************************************************************************** - * Name: adc_ioc_set_oversample - * - * Description: - * For STM32G0 and STM32L0: Configure hardware oversampling via CFGR2. - * - * Input: - * dev - pointer to the ADC device - * arg - Packed 32-bit value that matches CFGR2 layout for OVSE, TOVS, - * OVSR[2:0] and OVSS[3:0]. - * - * Bit fields (match ADC_CFGR2 register layout): - * [0] = OVSE (enable oversampling) - * [1] = TOVS (triggered oversampling) - * [4:2] = OVSR (ratio: 000=2x, ..., 111=256x) - * [9:5] = OVSS (right shift: 00000=no shift, ..., 11111=31-bit) - * - * Returned Value: - * OK (0) on success - * - ****************************************************************************/ - -static int adc_ioc_set_oversample(struct adc_dev_s *dev, uint32_t arg) -{ - struct stm32_dev_s *priv = (struct stm32_dev_s *)dev->ad_priv; - uint32_t clrbits; - uint32_t setbits; - - /* Mask out the oversampling-related fields from CFGR2: - * OVSE | TOVS | OVSR[2:0] | OVSS[3:0] - */ - - clrbits = ADC_CFGR2_OVSE | - ADC_CFGR2_TOVS | - ADC_CFGR2_OVSR_MASK | - ADC_CFGR2_OVSS_MASK; - - setbits = arg & (ADC_CFGR2_OVSE | - ADC_CFGR2_TOVS | - ADC_CFGR2_OVSR_MASK | - ADC_CFGR2_OVSS_MASK); - - adc_modifyreg(priv, STM32_ADC_CFGR2_OFFSET, clrbits, setbits); - return OK; -} - -#endif /* G0 or L0 */ - -/**************************************************************************** - * Name: adc_set_ch - * - * Description: - * Sets the ADC channel. - * - * Input Parameters: - * dev - pointer to device structure used by the driver - * ch - ADC channel number + 1. 0 reserved for all configured channels - * - * Returned Value: - * int - errno - * - ****************************************************************************/ - -static int adc_set_ch(struct adc_dev_s *dev, uint8_t ch) -{ - struct stm32_dev_s *priv = (struct stm32_dev_s *)dev->ad_priv; - uint32_t bits = 0; - int i = 0; - - if (ch == 0) - { - priv->current = 0; - priv->rnchannels = priv->cr_channels; - } - else - { - for (i = 0; i < priv->cr_channels && priv->r_chanlist[i] != ch - 1; - i++); - - if (i >= priv->cr_channels) - { - return -ENODEV; - } - - priv->current = i; - priv->rnchannels = 1; - } - - for (i = 0; i < priv->rnchannels; i += 1) - { - bits |= ADC_CHSELR_CHSEL(priv->r_chanlist[i]); - } - - /* Write register */ - - adc_modifyreg(priv, STM32_ADC_CHSELR_OFFSET, 0, bits); - - return OK; -} - -/**************************************************************************** - * Name: adc_ioctl - * - * Description: - * All ioctl calls will be routed through this method. - * - * Input Parameters: - * dev - pointer to device structure used by the driver - * cmd - command - * arg - arguments passed with command - * - * Returned Value: - * - ****************************************************************************/ - -static int adc_ioctl(struct adc_dev_s *dev, int cmd, unsigned long arg) -{ - struct stm32_dev_s *priv = (struct stm32_dev_s *)dev->ad_priv; - int ret = OK; - - switch (cmd) - { - case ANIOC_TRIGGER: - { - /* Start regular conversion if regular channels configured */ - - if (priv->cr_channels > 0) - { - adc_reg_startconv(priv, true); - } - - break; - } - - case ANIOC_GET_NCHANNELS: - { - /* Return the number of configured channels */ - - ret = priv->cr_channels; - } - - break; - - case IO_TRIGGER_REG: - { - /* Start regular conversion if regular channels configured */ - - if (priv->cr_channels > 0) - { - adc_reg_startconv(priv, true); - } - - break; - } - - case IO_ENABLE_DISABLE_AWDIE: - case IO_ENABLE_DISABLE_EOCIE: - case IO_ENABLE_DISABLE_OVRIE: - case IO_ENABLE_DISABLE_ALL_INTS: - { - adc_ioc_change_ints(dev, cmd, *(bool *)arg); - break; - } - -#ifdef HAVE_ADC_VBAT - case IO_ENABLE_DISABLE_VBAT_CH: - { - adc_enable_vbat_channel(dev, *(bool *)arg); - break; - } -#endif - -#ifdef HAVE_ADC_POWERDOWN - case IO_ENABLE_DISABLE_PDI: - case IO_ENABLE_DISABLE_PDD: - case IO_ENABLE_DISABLE_PDD_PDI: - { - adc_ioc_change_sleep_between_opers(dev, cmd, *(bool *)arg); - break; - } -#endif - - case IO_STOP_ADC: - { - adc_enable(priv, false); - break; - } - - case IO_START_ADC: - { - adc_enable(priv, true); - break; - } - - case IO_START_CONV: - { - uint8_t ch = ((uint8_t)arg); - - ret = adc_set_ch(dev, ch); - if (ret < 0) - { - return ret; - } - -#ifdef CONFIG_ADC - if (ch) - { - /* Clear fifo if upper-half driver enabled */ - - dev->ad_recv.af_head = 0; - dev->ad_recv.af_tail = 0; - } -#endif - - adc_reg_startconv(priv, true); - break; - } - -#if defined(CONFIG_STM32F0L0G0_ADC_OVERSAMPLE) - case ANIOC_SET_OVERSAMPLE: - { - ret = adc_ioc_set_oversample(dev, arg); - break; - } -#endif - - default: - { - aerr("ERROR: Unknown cmd: %d\n", cmd); - ret = -ENOTTY; - break; - } - } - - return ret; -} - -#ifndef CONFIG_STM32F0L0G0_ADC_NOIRQ - -/**************************************************************************** - * Name: adc_interrupt - * - * Description: - * Common ADC interrupt handler. - * - * Input Parameters: - * - * Returned Value: - * - ****************************************************************************/ - -static int adc_interrupt(struct adc_dev_s *dev) -{ - struct stm32_dev_s *priv = (struct stm32_dev_s *)dev->ad_priv; - uint32_t regval; - uint32_t pending; - int32_t data; - - regval = adc_getreg(priv, STM32_ADC_ISR_OFFSET); - pending = regval & ADC_ISR_ALLINTS; - if (pending == 0) - { - return OK; - } - - /* Identifies the interruption AWD, OVR or EOC */ - - if ((regval & ADC_ISR_AWD) != 0) - { - awarn("WARNING: Analog Watchdog, Value converted out of range!\n"); - } - - if ((regval & ADC_ISR_OVR) != 0) - { - awarn("WARNING: Overrun has occurred!\n"); - } - - /* EOC: End of conversion */ - - if ((regval & ADC_ISR_EOC) != 0) - { - /* Read the converted value and clear EOC bit - * (It is cleared by reading the ADC_DR) - */ - - data = adc_getreg(priv, STM32_ADC_DR_OFFSET) & ADC_DR_RDATA_MASK; - - /* Verify that the upper-half driver has bound its callback functions */ - - if (priv->cb != NULL) - { - /* Give the ADC data to the ADC driver. The ADC receive() method - * accepts 3 parameters: - * - * 1) The first is the ADC device instance for this ADC block. - * 2) The second is the channel number for the data, and - * 3) The third is the converted data for the channel. - */ - - DEBUGASSERT(priv->cb->au_receive != NULL); - priv->cb->au_receive(dev, priv->r_chanlist[priv->current], data); - } - - /* Set the channel number of the next channel that will complete - * conversion. - */ - - priv->current++; - - if (priv->current >= priv->rnchannels) - { - /* Restart the conversion sequence from the beginning */ - - priv->current = 0; - } - } - - /* Clear pending interrupts */ - - adc_putreg(priv, STM32_ADC_ISR_OFFSET, pending); - - return OK; -} - -/**************************************************************************** - * Name: adc1_interrupt - * - * Description: - * ADC interrupt handler for the STM32 L15XX family. - * - * Input Parameters: - * irq - The IRQ number that generated the interrupt. - * context - Architecture specific register save information. - * - * Returned Value: - * - ****************************************************************************/ - -static int adc1_interrupt(int irq, void *context, void *arg) -{ - adc_interrupt(&g_adcdev1); - - return OK; -} -#endif /* CONFIG_STM32F0L0G0_ADC_NOIRQ */ - -#ifdef CONFIG_STM32F0L0G0_ADC_LL_OPS - -/**************************************************************************** - * Name: adc_llops_intack - ****************************************************************************/ - -static void adc_llops_intack(struct stm32_adc_dev_s *dev, - uint32_t source) -{ - struct stm32_dev_s *priv = (struct stm32_dev_s *)dev; - - /* Clear pending interrupts */ - -#ifdef HAVE_IP_ADC_V2 - /* Cleared by writing 1 to it */ - - adc_putreg(priv, STM32_ADC_ISR_OFFSET, (source & ADC_ISR_ALLINTS)); -#else - /* Cleared by writing 0 to it */ - - adc_modifyreg(priv, STM32_ADC_ISR_OFFSET, (source & ADC_ISR_ALLINTS), 0); -#endif -} - -/**************************************************************************** - * Name: adc_llops_inten - ****************************************************************************/ - -static void adc_llops_inten(struct stm32_adc_dev_s *dev, uint32_t source) -{ - struct stm32_dev_s *priv = (struct stm32_dev_s *)dev; - - /* Enable interrupts */ - - adc_modifyreg(priv, STM32_ADC_IER_OFFSET, 0, (source & ADC_IER_ALLINTS)); -} - -/**************************************************************************** - * Name: adc_llops_intdis - ****************************************************************************/ - -static void adc_llops_intdis(struct stm32_adc_dev_s *dev, - uint32_t source) -{ - struct stm32_dev_s *priv = (struct stm32_dev_s *)dev; - - /* Disable interrupts */ - - adc_modifyreg(priv, STM32_ADC_IER_OFFSET, (source & ADC_IER_ALLINTS), 0); -} - -/**************************************************************************** - * Name: adc_ackget - ****************************************************************************/ - -static uint32_t adc_llops_intget(struct stm32_adc_dev_s *dev) -{ - struct stm32_dev_s *priv = (struct stm32_dev_s *)dev; - uint32_t regval; - uint32_t pending; - - regval = adc_getreg(priv, STM32_ADC_ISR_OFFSET); - pending = regval & ADC_ISR_ALLINTS; - - return pending; -} - -/**************************************************************************** - * Name: adc_llops_regget - ****************************************************************************/ - -static uint32_t adc_llops_regget(struct stm32_adc_dev_s *dev) -{ - struct stm32_dev_s *priv = (struct stm32_dev_s *)dev; - - return adc_getreg(priv, STM32_ADC_DR_OFFSET) & ADC_DR_RDATA_MASK; -} - -/**************************************************************************** - * Name: adc_llops_reg_startconv - ****************************************************************************/ - -static void adc_llops_reg_startconv(struct stm32_adc_dev_s *dev, - bool enable) -{ - struct stm32_dev_s *priv = (struct stm32_dev_s *)dev; - - adc_reg_startconv(priv, enable); -} - -/**************************************************************************** - * Name: adc_llops_regbufregister - ****************************************************************************/ - -#ifdef ADC_HAVE_DMA -static int adc_llops_regbufregister(struct stm32_adc_dev_s *dev, - uint16_t *buffer, uint8_t len) -{ - struct stm32_dev_s *priv = (struct stm32_dev_s *)dev; - - stm32_dmasetup(priv->dma, - priv->base + STM32_ADC_DR_OFFSET, - (uint32_t)buffer, - len, - ADC_DMA_CONTROL_WORD); - - /* No DMA callback */ - - stm32_dmastart(priv->dma, NULL, dev, false); - - return OK; -} -#endif /* ADC_HAVE_DMA */ - -#ifdef CONFIG_STM32F0L0G0_ADC_CHANGE_SAMPLETIME -/**************************************************************************** - * Name: adc_sampletime_write - * - * Description: - * Writes previously defined values into ADC_SMPRx registers. - * - * Input Parameters: - * - * Returned Value: - * - ****************************************************************************/ - -static void adc_sampletime_write(struct stm32_adc_dev_s *dev) -{ - struct stm32_dev_s *priv = (struct stm32_dev_s *)dev; - uint32_t smpr = 0; - - smpr |= ((uint32_t)priv->sample_rate[0] << ADC_SMPR_SMP1_SHIFT); - -#ifdef ADC_HAVE_SMPR_SMP2 - smpr |= ((uint32_t)priv->sample_rate[1] << ADC_SMPR_SMP2_SHIFT); - smpr |= ((uint32_t)priv->smpsel << ADC_SMPR_SMPSEL_SHIFT); -#endif - - adc_putreg(priv, STM32_ADC_SMPR_OFFSET, smpr); -} - -/**************************************************************************** - * Name: adc_change_sample_time - * - * Description: - * Changes sample times for specified channels. This method - * doesn't make any register writing. So, it's only stores the information. - * Values provided by user will be written in registers only on the next - * ADC peripheral start, as it was told to do in manual. However, before - * very first start, user can call this method and override default values - * either for every channels or for only some predefined by user channel(s) - * - * Input Parameters: - * priv - pointer to the adc device structure - * pdi_high - true: The ADC is powered down when waiting for a start event - * false: The ADC is powered up when waiting for a start event - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void adc_sampletime_set(struct stm32_adc_dev_s *dev, - struct adc_sample_time_s *time_samples) -{ - struct stm32_dev_s *priv = (struct stm32_dev_s *)dev; - - priv->sample_rate[0] = time_samples->smp1; -#ifdef ADC_HAVE_SMPR_SMP2 - priv->sample_rate[1] = time_samples->smp2; - priv->smpsel = time_samples->smpsel; -#endif -} -#endif /* CONFIG_STM32F0L0G0_ADC_CHANGE_SAMPLETIME */ - -/**************************************************************************** - * Name: adc_llops_dumpregs - ****************************************************************************/ - -static void adc_llops_dumpregs(struct stm32_adc_dev_s *dev) -{ - struct stm32_dev_s *priv = (struct stm32_dev_s *)dev; - - adc_dumpregs(priv); -} - -#endif /* CONFIG_STM32F0L0G0_ADC_LL_OPS */ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_adc_initialize - * - * Description: - * Initialize the ADC. - * - * Input Parameters: - * intf - Could be {1} for ADC1 - * chanlist - The list of channels - * channels - Number of channels - * - * Returned Value: - * Valid ADC device structure reference on success; a NULL on failure - * - ****************************************************************************/ - -struct adc_dev_s *stm32_adcinitialize(int intf, const uint8_t *chanlist, - int channels) -{ - struct adc_dev_s *dev; - struct stm32_dev_s *priv; - - ainfo("intf: %d cchannels: %d\n", intf, channels); - - switch (intf) - { -#ifdef CONFIG_STM32F0L0G0_ADC1 - case 1: - { - ainfo("ADC1 selected\n"); - dev = &g_adcdev1; - break; - } - -#endif - default: - { - aerr("ERROR: No ADC interface defined\n"); - return NULL; - } - } - - /* Configure the selected ADC */ - - priv = (struct stm32_dev_s *)dev->ad_priv; - priv->cb = NULL; - - DEBUGASSERT(channels <= CONFIG_STM32F0L0G0_ADC_MAX_SAMPLES); - - priv->cr_channels = channels; - memcpy(priv->r_chanlist, chanlist, channels); - -#ifdef CONFIG_PM - if (pm_register(&priv->pm_callback) != OK) - { - aerr("Power management registration failed\n"); - return NULL; - } -#endif - - return dev; -} - -#endif /* CONFIG_STM32F0L0G0_ADC1 */ -#endif /* CONFIG_STM32F0L0G0_ADC */ diff --git a/arch/arm/src/stm32f0l0g0/stm32_adc.h b/arch/arm/src/stm32f0l0g0/stm32_adc.h deleted file mode 100644 index 89ac9b8da5d21..0000000000000 --- a/arch/arm/src/stm32f0l0g0/stm32_adc.h +++ /dev/null @@ -1,448 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_adc.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_STM32_ADC_H -#define __ARCH_ARM_SRC_STM32F0L0G0_STM32_ADC_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "chip.h" - -#include -#include - -#include "hardware/stm32_adc.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -/* Timer devices may be used for different purposes. One special purpose is - * to control periodic ADC sampling. If CONFIG_STM32F0L0G0_TIMn is defined - * then CONFIG_STM32F0L0G0_TIMn_ADC must also be defined to indicate that - * timer "n" is intended to be used for that purpose. Timers 1-6 and 8 may - * be used. - */ - -#ifndef CONFIG_STM32F0L0G0_TIM1 -# undef CONFIG_STM32F0L0G0_TIM1_ADC -# undef CONFIG_STM32F0L0G0_TIM1_ADC1 -#endif -#ifndef CONFIG_STM32F0L0G0_TIM2 -# undef CONFIG_STM32F0L0G0_TIM2_ADC -# undef CONFIG_STM32F0L0G0_TIM2_ADC1 -#endif -#ifndef CONFIG_STM32F0L0G0_TIM3 -# undef CONFIG_STM32F0L0G0_TIM3_ADC -# undef CONFIG_STM32F0L0G0_TIM3_ADC1 -#endif -#ifndef CONFIG_STM32F0L0G0_TIM15 -# undef CONFIG_STM32F0L0G0_TIM15_ADC -# undef CONFIG_STM32F0L0G0_TIM15_ADC1 -#endif - -/* Up to 1 ADC interfaces are supported */ - -#if STM32_NADC < 1 -# undef CONFIG_STM32F0L0G0_ADC1 -#endif - -#if defined(CONFIG_STM32F0L0G0_ADC1) - -/* DMA support */ - -#undef ADC_HAVE_DMA -#if defined(CONFIG_STM32F0L0G0_ADC1_DMA) -# define ADC_HAVE_DMA 1 -#endif - -#ifdef CONFIG_STM32F0L0G0_ADC1_DMA -# define ADC1_HAVE_DMA 1 -#else -# undef ADC1_HAVE_DMA -#endif - -/* Timer configuration: If a timer trigger is specified, then get - * information about the timer. - */ - -#if defined(CONFIG_STM32F0L0G0_TIM1_ADC1) -# define ADC1_HAVE_TIMER 1 -# define ADC1_TIMER_BASE STM32_TIM1_BASE -# define ADC1_TIMER_PCLK_FREQUENCY STM32_APB2_TIM1_CLKIN -#elif defined(CONFIG_STM32F0L0G0_TIM2_ADC1) -# define ADC1_HAVE_TIMER 1 -# define ADC1_TIMER_BASE STM32_TIM2_BASE -# define ADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM2_CLKIN -#elif defined(CONFIG_STM32F0L0G0_TIM3_ADC1) -# define ADC1_HAVE_TIMER 1 -# define ADC1_TIMER_BASE STM32_TIM3_BASE -# define ADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM3_CLKIN -#elif defined(CONFIG_STM32F0L0G0_TIM15_ADC1) -# define ADC1_HAVE_TIMER 1 -# define ADC1_TIMER_BASE STM32_TIM15_BASE -# define ADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM15_CLKIN -#else -# undef ADC1_HAVE_TIMER -#endif - -#ifdef ADC1_HAVE_TIMER -# ifndef CONFIG_STM32F0L0G0_ADC1_SAMPLE_FREQUENCY -# error "CONFIG_STM32F0L0G0_ADC1_SAMPLE_FREQUENCY not defined" -# endif -# ifndef CONFIG_STM32F0L0G0_ADC1_TIMTRIG -# error "CONFIG_STM32F0L0G0_ADC1_TIMTRIG not defined" -# warning "Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO 5:TRGO2" -# endif -#endif - -#if defined(ADC1_HAVE_TIMER) -# define ADC_HAVE_TIMER 1 -#else -# undef ADC_HAVE_TIMER -#endif - -/* EXTSEL */ - -#if defined(CONFIG_STM32F0L0G0_STM32F0) -# define ADC1_EXTSEL_T1TRGO ADC12_CFGR1_EXTSEL_TRG0 -# define ADC1_EXTSEL_T1CC4 ADC12_CFGR1_EXTSEL_TRG1 -# define ADC1_EXTSEL_T2TRGO ADC12_CFGR1_EXTSEL_TRG2 -# define ADC1_EXTSEL_T3TRGO ADC12_CFGR1_EXTSEL_TRG3 -# define ADC1_EXTSEL_T15TRGO ADC12_CFGR1_EXTSEL_TRG4 - /* TRG5 reserved - * TRG6 reserved - * TRG7 reserved - */ -#elif defined(CONFIG_STM32F0L0G0_STM32L0) - /* TRG0 reserved */ -# define ADC1_EXTSEL_T21CC2 ADC12_CFGR1_EXTSEL_TRG1 -# define ADC1_EXTSEL_T2TRGO ADC12_CFGR1_EXTSEL_TRG2 -# define ADC1_EXTSEL_T2CC4 ADC12_CFGR1_EXTSEL_TRG3 -# define ADC1_EXTSEL_T21TRGO ADC12_CFGR1_EXTSEL_TRG4 -# define ADC1_EXTSEL_T2CC3 ADC12_CFGR1_EXTSEL_TRG5 - /* TRG6 reserved */ -# define ADC1_EXTSEL_EXTI11 ADC12_CFGR1_EXTSEL_TRG7 -#elif defined(CONFIG_STM32F0L0G0_STM32G0) -# define ADC1_EXTSEL_T1TRGO2 ADC12_CFGR1_EXTSEL_TRG0 -# define ADC1_EXTSEL_T1CC4 ADC12_CFGR1_EXTSEL_TRG1 -# define ADC1_EXTSEL_T2TRGO ADC12_CFGR1_EXTSEL_TRG2 -# define ADC1_EXTSEL_T3TRGO ADC12_CFGR1_EXTSEL_TRG3 -# define ADC1_EXTSEL_T15TRGO ADC12_CFGR1_EXTSEL_TRG4 - /* TRG5 and TRG6 reserved */ -# define ADC1_EXTSEL_EXTI11 ADC12_CFGR1_EXTSEL_TRG7 -#elif defined(CONFIG_STM32F0L0G0_STM32C0) -# define ADC1_EXTSEL_T1TRGO2 ADC12_CFGR1_EXTSEL_TRG0 -# define ADC1_EXTSEL_T1CC4 ADC12_CFGR1_EXTSEL_TRG1 -# define ADC1_EXTSEL_T2TRGO ADC12_CFGR1_EXTSEL_TRG2 -# define ADC1_EXTSEL_T3TRGO ADC12_CFGR1_EXTSEL_TRG3 -# define ADC1_EXTSEL_T15TRGO ADC12_CFGR1_EXTSEL_TRG4 - /* TRG5 and TRG6 reserved */ -# define ADC1_EXTSEL_EXTI11 ADC12_CFGR1_EXTSEL_TRG7 -#else -# error -#endif - -/* EXTSEL configuration *****************************************************/ - -/* NOTE: - * this configuration if used only if CONFIG_STM32F0L0G0_TIMx_ADCy is - * selected. - * You can still connect the ADC with a timer trigger using the - * CONFIG_STM32F0L0G0_ADCx_EXTSEL option. - */ - -#if defined(CONFIG_STM32F0L0G0_TIM1_ADC1) -# if CONFIG_STM32F0L0G0_ADC1_TIMTRIG == 3 -# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T1CC4 -# elif CONFIG_STM32F0L0G0_ADC1_TIMTRIG == 4 -# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T1TRGO -# elif CONFIG_STM32F0L0G0_ADC1_TIMTRIG == 5 -# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T1TRGO2 -# else -# error "CONFIG_STM32F0L0G0_ADC1_TIMTRIG is out of range" -# endif -#elif defined(CONFIG_STM32F0L0G0_TIM2_ADC1) -# if CONFIG_STM32F0L0G0_ADC1_TIMTRIG == 3 -# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T2CC4 -# elif CONFIG_STM32F0L0G0_ADC1_TIMTRIG == 4 -# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T2TRGO -# else -# error "CONFIG_STM32F0L0G0_ADC1_TIMTRIG is out of range" -# endif -#elif defined(CONFIG_STM32F0L0G0_TIM3_ADC1) -# if CONFIG_STM32F0L0G0_ADC1_TIMTRIG == 4 -# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T3TRGO -# else -# error "CONFIG_STM32F0L0G0_ADC1_TIMTRIG is out of range" -# endif -#elif defined(CONFIG_STM32F0L0G0_TIM15_ADC1) -# if CONFIG_STM32F0L0G0_ADC1_TIMTRIG == 4 -# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T15TRGO -# else -# error "CONFIG_STM32F0L0G0_ADC1_TIMTRIG is out of range" -# endif -#elif defined(CONFIG_STM32F0L0G0_TIM21_ADC1) -# if CONFIG_STM32F0L0G0_ADC1_TIMTRIG == 1 -# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T21CC2 -# elif CONFIG_STM32F0L0G0_ADC1_TIMTRIG == 4 -# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T21TRGO -# else -# error "CONFIG_STM32F0L0G0_ADC1_TIMTRIG is out of range" -# endif -#endif - -/* Regular channels external trigger support */ - -#ifdef ADC1_EXTSEL_VALUE -# define ADC1_HAVE_EXTCFG 1 -# define ADC1_EXTCFG_VALUE (ADC1_EXTSEL_VALUE | ADC_EXTREG_EXTEN_DEFAULT) -#elif defined(CONFIG_STM32F0L0G0_ADC1_EXTSEL) -# define ADC1_HAVE_EXTCFG 1 -# define ADC1_EXTCFG_VALUE 0 -#else -# undef ADC1_HAVE_EXTCFG -#endif - -#if defined(ADC1_HAVE_EXTCFG) -# define ADC_HAVE_EXTCFG -#endif - -/* ADC interrupts ***********************************************************/ - -#define ADC_ISR_EOC ADC_INT_EOC -#define ADC_IER_EOC ADC_INT_EOC -#define ADC_ISR_AWD ADC_INT_AWD -#define ADC_IER_AWD ADC_INT_AWD -#define ADC_ISR_OVR ADC_INT_OVR -#define ADC_IER_OVR ADC_INT_OVR - -#define ADC_ISR_ALLINTS (ADC_ISR_EOC | ADC_ISR_AWD | ADC_ISR_OVR) -#define ADC_IER_ALLINTS (ADC_IER_EOC | ADC_IER_AWD | ADC_IER_OVR) - -/* ADC registers ************************************************************/ - -#define STM32_ADC_DMAREG_OFFSET STM32_ADC_CFGR1_OFFSET -#define ADC_DMAREG_DMA ADC_CFGR1_DMAEN -#define STM32_ADC_EXTREG_OFFSET STM32_ADC_CFGR1_OFFSET -#define ADC_EXTREG_EXTSEL_MASK ADC_CFGR1_EXTSEL_MASK -#define ADC_EXTREG_EXTEN_MASK ADC_CFGR1_EXTEN_MASK -#define ADC_EXTREG_EXTEN_DEFAULT ADC_CFGR1_EXTEN_RISING - -/* Low-level ops helpers ****************************************************/ - -#define ADC_INT_ACK(adc, source) \ - (adc)->llops->int_ack(adc, source) -#define ADC_INT_GET(adc) \ - (adc)->llops->int_get(adc) -#define ADC_INT_ENABLE(adc, source) \ - (adc)->llops->int_en(adc, source) -#define ADC_INT_DISABLE(adc, source) \ - (adc)->llops->int_dis(adc, source) -#define ADC_REGDATA_GET(adc) \ - (adc)->llops->val_get(adc) -#define ADC_REGBUF_REGISTER(adc, buffer, len) \ - (adc)->llops->regbuf_reg(adc, buffer, len) -#define ADC_REG_STARTCONV(adc, state) \ - (adc)->llops->reg_startconv(adc, state) -#define ADC_SAMPLETIME_SET(adc, time_samples) \ - (adc)->llops->stime_set(adc, time_samples) -#define ADC_SAMPLETIME_WRITE(adc) \ - (adc)->llops->stime_write(adc) -#define ADC_DUMP_REGS(adc) \ - (adc)->llops->dump_regs(adc) - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -/* On STM32F42xx and STM32F43xx devices,VBAT and temperature sensor are - * connected to the same ADC internal channel (ADC1_IN18). Only one - * conversion, either temperature sensor or VBAT, must be selected at a time. - * When both conversion are enabled simultaneously, only the VBAT conversion - * is performed. - */ - -enum adc_io_cmds_e -{ -#ifdef HAVE_ADC_VBAT - IO_ENABLE_DISABLE_VBAT_CH, -#endif - IO_ENABLE_DISABLE_AWDIE, - IO_ENABLE_DISABLE_EOCIE, - IO_ENABLE_DISABLE_JEOCIE, - IO_ENABLE_DISABLE_OVRIE, - IO_ENABLE_DISABLE_ALL_INTS, - IO_STOP_ADC, - IO_START_ADC, - IO_START_CONV, - IO_TRIGGER_REG, -#ifdef ADC_HAVE_INJECTED - IO_TRIGGER_INJ, -#endif -#ifdef HAVE_ADC_POWERDOWN - IO_ENABLE_DISABLE_PDI, - IO_ENABLE_DISABLE_PDD, - IO_ENABLE_DISABLE_PDD_PDI -#endif -}; - -/* ADC resolution can be reduced in order to perform faster conversion */ - -enum stm32_adc_resoluton_e -{ - ADC_RESOLUTION_12BIT = 0, /* 12 bit */ - ADC_RESOLUTION_10BIT = 1, /* 10 bit */ - ADC_RESOLUTION_8BIT = 2, /* 8 bit */ - ADC_RESOLUTION_6BIT = 3 /* 6 bit */ -}; - -#ifdef CONFIG_STM32F0L0G0_ADC_LL_OPS - -#ifdef CONFIG_STM32F0L0G0_ADC_CHANGE_SAMPLETIME - -struct adc_sample_time_s -{ - uint8_t smp1; /* Sample time for channels with SMPSEL bit = 0 */ - uint8_t smp2; /* Sample time for channels with SMPSEL bit = 1 */ - uint32_t smpsel; /* Bitmask for selecting which channels use SMP2 */ -}; -#endif /* CONFIG_STM32F0L0G0_ADC_CHANGE_SAMPLETIME */ - -/* This structure provides the publicly visible representation of the - * "lower-half" ADC driver structure. - */ - -struct stm32_adc_dev_s -{ - /* Publicly visible portion of the "lower-half" ADC driver structure */ - - const struct stm32_adc_ops_s *llops; - - /* Require cast-compatibility with private "lower-half" ADC structure */ -}; - -/* Low-level operations for ADC */ - -struct stm32_adc_ops_s -{ - /* Acknowledge interrupts */ - - void (*int_ack)(struct stm32_adc_dev_s *dev, uint32_t source); - - /* Get pending interrupts */ - - uint32_t (*int_get)(struct stm32_adc_dev_s *dev); - - /* Enable interrupts */ - - void (*int_en)(struct stm32_adc_dev_s *dev, uint32_t source); - - /* Disable interrupts */ - - void (*int_dis)(struct stm32_adc_dev_s *dev, uint32_t source); - - /* Get current ADC data register */ - - uint32_t (*val_get)(struct stm32_adc_dev_s *dev); - - /* Register buffer for ADC DMA transfer */ - - int (*regbuf_reg)(struct stm32_adc_dev_s *dev, uint16_t *buffer, - uint8_t len); - - /* Start/stop regular conversion */ - - void (*reg_startconv)(struct stm32_adc_dev_s *dev, bool state); - -#ifdef CONFIG_STM32F0L0G0_ADC_CHANGE_SAMPLETIME - /* Set ADC sample time */ - - void (*stime_set)(struct stm32_adc_dev_s *dev, - struct adc_sample_time_s *time_samples); - - /* Write ADC sample time */ - - void (*stime_write)(struct stm32_adc_dev_s *dev); -#endif - - void (*dump_regs)(struct stm32_adc_dev_s *dev); -}; - -#endif /* CONFIG_STM32F0L0G0_ADC_LL_OPS */ - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -#ifndef __ASSEMBLY__ -#ifdef __cplusplus -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Name: stm32_adcinitialize - * - * Description: - * Initialize the ADC. See stm32_adc.c for more details. - * - * Input Parameters: - * intf - Could be {1,2,3,4} for ADC1, ADC2, ADC3 or ADC4 - * chanlist - The list of channels (regular + injected) - * nchannels - Number of channels (regular + injected) - * - * Returned Value: - * Valid ADC device structure reference on success; a NULL on failure - * - ****************************************************************************/ - -struct adc_dev_s; -struct adc_dev_s *stm32_adcinitialize(int intf, const uint8_t *chanlist, - int channels); - -/**************************************************************************** - * Name: stm32_adc_llops_get - ****************************************************************************/ - -#ifdef CONFIG_STM32F0L0G0_ADC_LL_OPS -const struct stm32_adc_ops_s -*stm32_adc_llops_get(struct adc_dev_s *dev); -#endif - -#undef EXTERN -#ifdef __cplusplus -} -#endif -#endif /* __ASSEMBLY__ */ - -#endif /* CONFIG_STM32F0L0G0_ADC1 */ -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_STM32_ADC_H */ diff --git a/arch/arm/src/stm32f0l0g0/stm32_aes.c b/arch/arm/src/stm32f0l0g0/stm32_aes.c deleted file mode 100644 index 746047df3d7be..0000000000000 --- a/arch/arm/src/stm32f0l0g0/stm32_aes.c +++ /dev/null @@ -1,322 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_aes.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include - -#include "arm_internal.h" -#include "chip.h" -#include "stm32_rcc.h" -#include "stm32_aes.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#define AES_BLOCK_SIZE 16 - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -static void stm32aes_enable(bool on); -static void stm32aes_ccfc(void); -static void stm32aes_setkey(const void *key, size_t key_len); -static void stm32aes_setiv(const void *iv); -static void stm32aes_encryptblock(void *block_out, - const void *block_in); -static int stm32aes_setup_cr(int mode, int encrypt); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -static mutex_t g_stm32aes_lock = NXMUTEX_INITIALIZER; -static bool g_stm32aes_initdone; - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -static void stm32aes_enable(bool on) -{ - uint32_t regval; - - regval = getreg32(STM32_AES_CR); - if (on) - { - regval |= AES_CR_EN; - } - else - { - regval &= ~AES_CR_EN; - } - - putreg32(regval, STM32_AES_CR); -} - -/* Clear AES_SR_CCF status register bit */ - -static void stm32aes_ccfc(void) -{ - uint32_t regval; - - regval = getreg32(STM32_AES_CR); - regval |= AES_CR_CCFC; - putreg32(regval, STM32_AES_CR); -} - -/* TODO: Handle other AES key lengths or fail if length is not valid */ - -static void stm32aes_setkey(const void *key, size_t key_len) -{ - uint32_t *in = (uint32_t *)key; - - putreg32(__builtin_bswap32(*in), STM32_AES_KEYR3); - in++; - putreg32(__builtin_bswap32(*in), STM32_AES_KEYR2); - in++; - putreg32(__builtin_bswap32(*in), STM32_AES_KEYR1); - in++; - putreg32(__builtin_bswap32(*in), STM32_AES_KEYR0); -} - -static void stm32aes_setiv(const void *iv) -{ - uint32_t *in = (uint32_t *)iv; - - putreg32(__builtin_bswap32(*in), STM32_AES_IVR3); - in++; - putreg32(__builtin_bswap32(*in), STM32_AES_IVR2); - in++; - putreg32(__builtin_bswap32(*in), STM32_AES_IVR1); - in++; - putreg32(__builtin_bswap32(*in), STM32_AES_IVR0); -} - -static void stm32aes_encryptblock(void *block_out, - const void *block_in) -{ - uint32_t *in = (uint32_t *)block_in; - uint32_t *out = (uint32_t *)block_out; - - putreg32(*in, STM32_AES_DINR); - in++; - putreg32(*in, STM32_AES_DINR); - in++; - putreg32(*in, STM32_AES_DINR); - in++; - putreg32(*in, STM32_AES_DINR); - - while (!(getreg32(STM32_AES_SR) & AES_SR_CCF)); - stm32aes_ccfc(); - - *out = getreg32(STM32_AES_DOUTR); - out++; - *out = getreg32(STM32_AES_DOUTR); - out++; - *out = getreg32(STM32_AES_DOUTR); - out++; - *out = getreg32(STM32_AES_DOUTR); -} - -static int stm32aes_setup_cr(int mode, int encrypt) -{ - uint32_t regval = 0; - - regval |= AES_CR_DATATYPE_BE; - - switch (mode) - { - case AES_MODE_ECB: - regval |= AES_CR_CHMOD_ECB; - break; - - case AES_MODE_CBC: - regval |= AES_CR_CHMOD_CBC; - break; - - case AES_MODE_CTR: - regval |= AES_CR_CHMOD_CTR; - break; - - default: - return -EINVAL; - } - - if (encrypt) - { - regval |= AES_CR_MODE_ENCRYPT; - } - else - { - if (mode == AES_MODE_CTR) - { - regval |= AES_CR_MODE_DECRYPT; - } - else - { - regval |= AES_CR_MODE_DECRYPT_KEYDERIV; - } - } - - putreg32(regval, STM32_AES_CR); - return OK; -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -int stm32_aesreset(void) -{ - irqstate_t flags; - uint32_t regval; - - flags = enter_critical_section(); - - regval = getreg32(STM32_RCC_AHBRSTR); - regval |= RCC_AHBRSTR_AESRST; - putreg32(regval, STM32_RCC_AHBRSTR); - regval &= ~RCC_AHBRSTR_AESRST; - putreg32(regval, STM32_RCC_AHBRSTR); - - leave_critical_section(flags); - - return OK; -} - -int stm32_aesinitialize(void) -{ - uint32_t regval; - - regval = getreg32(STM32_RCC_AHBENR); - regval |= RCC_AHBENR_AESEN; - putreg32(regval, STM32_RCC_AHBENR); - - stm32aes_enable(false); - - return OK; -} - -int stm32_aesuninitialize(void) -{ - uint32_t regval; - - stm32aes_enable(false); - - regval = getreg32(STM32_RCC_AHBENR); - regval &= ~RCC_AHBENR_AESEN; - putreg32(regval, STM32_RCC_AHBENR); - - return OK; -} - -int aes_cypher(void *out, const void *in, size_t size, - const void *iv, const void *key, size_t keysize, - int mode, int encrypt) -{ - int ret = OK; - - /* Ensure initialization was done */ - - if (!g_stm32aes_initdone) - { - ret = stm32_aesinitialize(); - if (ret < 0) - { - return ret; /* AES init failed */ - } - - g_stm32aes_initdone = true; - } - - if ((size & (AES_BLOCK_SIZE - 1)) != 0) - { - return -EINVAL; - } - - if (keysize != 16) - { - return -EINVAL; - } - - ret = nxmutex_lock(&g_stm32aes_lock); - if (ret < 0) - { - return ret; - } - - /* AES must be disabled before changing mode, key or IV. */ - - stm32aes_enable(false); - ret = stm32aes_setup_cr(mode, encrypt); - if (ret < 0) - { - goto out; - } - - stm32aes_setkey(key, keysize); - if (iv != NULL) - { - stm32aes_setiv(iv); - } - - stm32aes_enable(true); - while (size) - { - stm32aes_encryptblock(out, in); - out = (uint8_t *)out + AES_BLOCK_SIZE; - in = (uint8_t *)in + AES_BLOCK_SIZE; - size -= AES_BLOCK_SIZE; - } - - stm32aes_enable(false); - -out: - nxmutex_unlock(&g_stm32aes_lock); - return ret; -} diff --git a/arch/arm/src/stm32f0l0g0/stm32_aes.h b/arch/arm/src/stm32f0l0g0/stm32_aes.h deleted file mode 100644 index f499aa8b95d41..0000000000000 --- a/arch/arm/src/stm32f0l0g0/stm32_aes.h +++ /dev/null @@ -1,50 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_aes.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_STM32_AES_H -#define __ARCH_ARM_SRC_STM32F0L0G0_STM32_AES_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include "chip.h" - -#include "hardware/stm32_aes.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -/**************************************************************************** - * Inline Functions - ****************************************************************************/ - -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_STM32_AES_H */ diff --git a/arch/arm/src/stm32f0l0g0/stm32_crypto.c b/arch/arm/src/stm32f0l0g0/stm32_crypto.c deleted file mode 100644 index 64b4b99c4f813..0000000000000 --- a/arch/arm/src/stm32f0l0g0/stm32_crypto.c +++ /dev/null @@ -1,162 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_crypto.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include - -#include -#include -#include - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -static uint32_t g_stm32_sesnum = 0; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: authcompute - * - * Description: - * Calculate the hash. - * - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_newsession - * - * Description: - * create new session for crypto. - * - ****************************************************************************/ - -static int stm32_newsession(uint32_t *sid, struct cryptoini *cri) -{ - if (sid == NULL || cri == NULL) - { - return -EINVAL; - } - - switch (cri->cri_alg) - { - case CRYPTO_AES_CBC: - *sid = g_stm32_sesnum++; - break; - case CRYPTO_AES_CTR: - if ((cri->cri_klen / 8 - 4) != 16) - { - /* stm32 aes-ctr key bits just support 128 */ - - return -EINVAL; - } - - *sid = g_stm32_sesnum++; - break; - default: - return -EINVAL; - } - - return OK; -} - -/**************************************************************************** - * Name: stm32_freesession - * - * Description: - * free session. - * - ****************************************************************************/ - -static int stm32_freesession(uint64_t tid) -{ - return 0; -} - -/**************************************************************************** - * Name: stm32_process - * - * Description: - * process session to use hardware algorithm. - * - ****************************************************************************/ - -static int stm32_process(struct cryptop *crp) -{ - struct cryptodesc *crd; - uint8_t iv[AESCTR_BLOCKSIZE]; - - for (crd = crp->crp_desc; crd; crd = crd->crd_next) - { - switch (crd->crd_alg) - { - case CRYPTO_AES_CBC: - return aes_cypher(crp->crp_dst, crp->crp_buf, crd->crd_len, - crd->crd_iv, crd->crd_key, 16, - AES_MODE_CBC, crd->crd_flags & CRD_F_ENCRYPT); - case CRYPTO_AES_CTR: - - memcpy(iv, crd->crd_key + crd->crd_klen / 8 - AESCTR_NONCESIZE, - AESCTR_NONCESIZE); - memcpy(iv + AESCTR_NONCESIZE, crd->crd_iv, AESCTR_IVSIZE); - memset(iv + AESCTR_NONCESIZE + AESCTR_IVSIZE , 0, 4); - - return aes_cypher(crp->crp_dst, crp->crp_buf, crd->crd_len, - iv, crd->crd_key, crd->crd_klen / 8 - 4, - AES_MODE_CTR, crd->crd_flags & CRD_F_ENCRYPT); - default: - return -EINVAL; - } - } -} - -/**************************************************************************** - * Name: hwcr_init - * - * Description: - * register the hardware crypto driver. - * - ****************************************************************************/ - -void hwcr_init(void) -{ - int hwcr_id; - int algs[CRYPTO_ALGORITHM_MAX + 1]; - - hwcr_id = crypto_get_driverid(0); - DEBUGASSERT(hwcr_id >= 0); - - memset(algs, 0, sizeof(algs)); - - algs[CRYPTO_AES_CBC] = CRYPTO_ALG_FLAG_SUPPORTED; - algs[CRYPTO_AES_CTR] = CRYPTO_ALG_FLAG_SUPPORTED; - - crypto_register(hwcr_id, algs, stm32_newsession, - stm32_freesession, stm32_process); -} diff --git a/arch/arm/src/stm32f0l0g0/stm32_dma.c b/arch/arm/src/stm32f0l0g0/stm32_dma.c deleted file mode 100644 index 4d60de3763b6d..0000000000000 --- a/arch/arm/src/stm32f0l0g0/stm32_dma.c +++ /dev/null @@ -1,39 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_dma.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "chip.h" - -#if defined(CONFIG_STM32F0L0G0_HAVE_DMAMUX) -# include "stm32_dma_v1mux.c" -#else -# include "stm32_dma_v1.c" -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ diff --git a/arch/arm/src/stm32f0l0g0/stm32_dma.h b/arch/arm/src/stm32f0l0g0/stm32_dma.h deleted file mode 100644 index 0d6d729a0cc5c..0000000000000 --- a/arch/arm/src/stm32f0l0g0/stm32_dma.h +++ /dev/null @@ -1,327 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_dma.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_STM32_DMA_H -#define __ARCH_ARM_SRC_STM32F0L0G0_STM32_DMA_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include - -#include "hardware/stm32_dma_v1.h" - -#ifdef CONFIG_STM32F0L0G0_HAVE_DMAMUX -# include "hardware/stm32_dmamux.h" -#endif - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* These definitions provide the bit encoding of the 'status' parameter - * passed to the DMA callback function (see dma_callback_t). - */ - -#define DMA_STATUS_TEIF DMA_CHAN_TEIF_BIT /* Channel Transfer Error */ -#define DMA_STATUS_HTIF DMA_CHAN_HTIF_BIT /* Channel Half Transfer */ -#define DMA_STATUS_TCIF DMA_CHAN_TCIF_BIT /* Channel Transfer Complete */ - -#define DMA_STATUS_ERROR (DMA_STATUS_TEIF) -#define DMA_STATUS_SUCCESS (DMA_STATUS_TCIF | DMA_STATUS_HTIF) - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -/* DMA_HANDLE provides an opaque reference that can be used to represent a - * DMA channel (F1) or a DMA stream (F4). - */ - -typedef void *DMA_HANDLE; - -/* Description: - * This is the type of the callback that is used to inform the user of the - * completion of the DMA. - * - * Input Parameters: - * handle - Refers to the DMA channel or stream - * status - A bit encoded value that provides the completion status. See - * the DMASTATUS_* definitions above. - * arg - A user-provided value that was provided when stm32_dmastart() - * was called. - */ - -typedef void (*dma_callback_t)(DMA_HANDLE handle, uint8_t status, void *arg); - -#ifdef CONFIG_DEBUG_DMA_INFO -struct stm32_dmaregs_s -{ - uint32_t isr; - uint32_t ccr; - uint32_t cndtr; - uint32_t cpar; - uint32_t cmar; -}; -#endif - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -#ifndef __ASSEMBLY__ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_dmachannel - * - * Description: - * Allocate a DMA channel. This function gives the caller mutually - * exclusive access to the DMA channel specified by the 'chan' argument. - * DMA channels are shared on the STM32: Devices sharing the same DMA - * channel cannot do DMA concurrently! See the DMACHAN_* definitions in - * stm32_dma.h. - * - * If the DMA channel is not available, then stm32_dmachannel() will wait - * until the holder of the channel relinquishes the channel by calling - * stm32_dmafree(). WARNING: If you have two devices sharing a DMA - * channel and the code never releases the channel, the stm32_dmachannel - * call for the other will hang forever in this function! Don't let your - * design do that! - * - * Hmm.. I suppose this interface could be extended to make a non-blocking - * version. Feel free to do that if that is what you need. - * - * Input Parameters: - * chan - Identifies the stream/channel resource - * For the STM32 F1, this is simply the channel number as provided by - * the DMACHAN_* definitions in chip/stm32f10xxx_dma.h. - * For the STM32 F4, this is a bit encoded value as provided by the - * the DMAMAP_* definitions in chip/stm32f40xxx_dma.h - * - * Returned Value: - * Provided that 'chan' is valid, this function ALWAYS returns a non-NULL, - * void* DMA channel handle. (If 'chan' is invalid, the function will - * assert if debug is enabled or do something ignorant otherwise). - * - * Assumptions: - * - The caller does not hold he DMA channel. - * - The caller can wait for the DMA channel to be freed if it is no - * available. - * - ****************************************************************************/ - -DMA_HANDLE stm32_dmachannel(unsigned int chan); - -/**************************************************************************** - * Name: stm32_dmafree - * - * Description: - * Release a DMA channel. If another thread is waiting for this DMA - * channel in a call to stm32_dmachannel, then this function will - * re-assign the DMA channel to that thread and wake it up. - * - * NOTE: The 'handle' used in this argument must NEVER be used again - * until stm32_dmachannel() is called again to re-gain access to - * the channel. - * - * Returned Value: - * None - * - * Assumptions: - * - The caller holds the DMA channel. - * - There is no DMA in progress - * - ****************************************************************************/ - -void stm32_dmafree(DMA_HANDLE handle); - -/**************************************************************************** - * Name: stm32_dmasetup - * - * Description: - * Configure DMA before using - * - ****************************************************************************/ - -void stm32_dmasetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr, - size_t ntransfers, uint32_t ccr); - -/**************************************************************************** - * Name: stm32_dmastart - * - * Description: - * Start the DMA transfer - * - * Assumptions: - * - DMA handle allocated by stm32_dmachannel() - * - No DMA in progress - * - ****************************************************************************/ - -void stm32_dmastart(DMA_HANDLE handle, dma_callback_t callback, void *arg, - bool half); - -/**************************************************************************** - * Name: stm32_dmastop - * - * Description: - * Cancel the DMA. After stm32_dmastop() is called, the DMA channel is - * reset and stm32_dmasetup() must be called before stm32_dmastart() can - * be called again - * - * Assumptions: - * - DMA handle allocated by stm32_dmachannel() - * - ****************************************************************************/ - -void stm32_dmastop(DMA_HANDLE handle); - -/**************************************************************************** - * Name: stm32_dmaresidual - * - * Description: - * Returns the number of bytes remaining to be transferred - * - * Assumptions: - * - DMA handle allocated by stm32_dmachannel() - * - ****************************************************************************/ - -size_t stm32_dmaresidual(DMA_HANDLE handle); - -/**************************************************************************** - * Name: stm32_dmacapable - * - * Description: - * Check if the DMA controller can transfer data to/from given memory - * address with the given configuration. This depends on the internal - * connections in the ARM bus matrix of the processor. Note that this - * only applies to memory addresses, it will return false for any - * peripheral address. - * - * Returned Value: - * True, if transfer is possible. - * - ****************************************************************************/ - -#ifdef CONFIG_STM32F0L0G0_DMACAPABLE -bool stm32_dmacapable(uintptr_t maddr, uint32_t count, uint32_t ccr); -#else -# define stm32_dmacapable(maddr, count, ccr) (true) -#endif - -/**************************************************************************** - * Name: stm32_dmasample - * - * Description: - * Sample DMA register contents - * - * Assumptions: - * - DMA handle allocated by stm32_dmachannel() - * - ****************************************************************************/ - -#ifdef CONFIG_DEBUG_DMA_INFO -void stm32_dmasample(DMA_HANDLE handle, struct stm32_dmaregs_s *regs); -#else -# define stm32_dmasample(handle,regs) -#endif - -/**************************************************************************** - * Name: stm32_dmadump - * - * Description: - * Dump previously sampled DMA register contents - * - * Assumptions: - * - DMA handle allocated by stm32_dmachannel() - * - ****************************************************************************/ - -#ifdef CONFIG_DEBUG_DMA_INFO -void stm32_dmadump(DMA_HANDLE handle, const struct stm32_dmaregs_s *regs, - const char *msg); -#else -# define stm32_dmadump(handle,regs,msg) -#endif - -/* High performance, zero latency DMA interrupts need some additional - * interfaces. - * - * TODO: For now the interface is different for STM32 DMAv1 and STM32 DMAv2. - * It should be unified somehow. - */ - -#ifdef CONFIG_ARCH_HIPRI_INTERRUPT - -/**************************************************************************** - * Name: stm32_dma_intack - * - * Description: - * Public visible interface to acknowledge interrupts on DMA channel - * - ****************************************************************************/ - -#if defined(HAVE_IP_DMA_V1) -void stm32_dma_intack(unsigned int chndx, uint32_t isr); -#elif defined(HAVE_IP_DMA_V2) -void stm32_dma_intack(unsigned int controller, uint8_t stream, uint32_t isr); -#endif - -/**************************************************************************** - * Name: stm32_dma_intget - * - * Description: - * Public visible interface to get pending interrupts from DMA channel - * - ****************************************************************************/ - -#if defined(HAVE_IP_DMA_V1) -uint32_t stm32_dma_intget(unsigned int chndx); -#elif defined(HAVE_IP_DMA_V2) -uint8_t stm32_dma_intget(unsigned int controller, uint8_t stream); -#endif - -#endif /* CONFIG_ARCH_HIPRI_INTERRUPT */ - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_STM32_DMA_H */ diff --git a/arch/arm/src/stm32f0l0g0/stm32_dma_v1.c b/arch/arm/src/stm32f0l0g0/stm32_dma_v1.c deleted file mode 100644 index 28ffac90950cc..0000000000000 --- a/arch/arm/src/stm32f0l0g0/stm32_dma_v1.c +++ /dev/null @@ -1,796 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_dma_v1.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include - -#include -#include -#include - -#include - -#include "arm_internal.h" -#include "sched/sched.h" -#include "chip.h" -#include "stm32_dma.h" -#include "stm32.h" - -/* This file supports the STM32 DMA IP core version 1 - F0, F1, F3, L0, L1, - * L4 - * - * F0, L0 and L4 have the additional CSELR register which is used to remap - * the DMA requests for each channel. - */ - -#ifdef CONFIG_STM32F0L0G0_HAVE_DMAMUX -# error DMAMUX not supported here. Look at stm32_dma_v1mux.c -#endif - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#define DMA1_NCHANNELS 7 - -#if STM32_NDMA > 1 -# define DMA2_NCHANNELS 5 -# define DMA_NCHANNELS (DMA1_NCHANNELS+DMA2_NCHANNELS) -#else -# define DMA_NCHANNELS DMA1_NCHANNELS -#endif - -/* Convert the DMA channel base address to the DMA register block address */ - -#define DMA_BASE(ch) (ch & 0xfffffc00) - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/* This structure describes one DMA channel */ - -struct stm32_dma_s -{ - uint8_t chan; /* DMA channel number (0-6) */ -#ifdef DMA_HAVE_CSELR - uint8_t function; /* DMA peripheral connected to this channel (0-7) */ -#endif - uint8_t irq; /* DMA channel IRQ number */ - sem_t sem; /* Used to wait for DMA channel to become available */ - uint32_t base; /* DMA register channel base address */ - dma_callback_t callback; /* Callback invoked when the DMA completes */ - void *arg; /* Argument passed to callback function */ -}; - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* This array describes the state of each DMA */ - -static struct stm32_dma_s g_dma[DMA_NCHANNELS] = -{ - { - .chan = 0, - .irq = STM32_IRQ_DMA1CH1, - .sem = SEM_INITIALIZER(1), - .base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(0), - }, - { - .chan = 1, - .irq = STM32_IRQ_DMA1CH2, - .sem = SEM_INITIALIZER(1), - .base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(1), - }, - { - .chan = 2, - .irq = STM32_IRQ_DMA1CH3, - .sem = SEM_INITIALIZER(1), - .base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(2), - }, - { - .chan = 3, - .irq = STM32_IRQ_DMA1CH4, - .sem = SEM_INITIALIZER(1), - .base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(3), - }, - { - .chan = 4, - .irq = STM32_IRQ_DMA1CH5, - .sem = SEM_INITIALIZER(1), - .base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(4), - }, - { - .chan = 5, - .irq = STM32_IRQ_DMA1CH6, - .sem = SEM_INITIALIZER(1), - .base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(5), - }, - { - .chan = 6, - .irq = STM32_IRQ_DMA1CH7, - .sem = SEM_INITIALIZER(1), - .base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(6), - }, -#if STM32_NDMA > 1 - { - .chan = 0, - .irq = STM32_IRQ_DMA2CH1, - .sem = SEM_INITIALIZER(1), - .base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(0), - }, - { - .chan = 1, - .irq = STM32_IRQ_DMA2CH2, - .sem = SEM_INITIALIZER(1), - .base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(1), - }, - { - .chan = 2, - .irq = STM32_IRQ_DMA2CH3, - .sem = SEM_INITIALIZER(1), - .base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(2), - }, - { - .chan = 3, - .irq = STM32_IRQ_DMA2CH4, - .sem = SEM_INITIALIZER(1), - .base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(3), - }, - { - .chan = 4, - .irq = STM32_IRQ_DMA2CH5, - .sem = SEM_INITIALIZER(1), - .base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(4), - }, -#endif -}; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * DMA register access functions - ****************************************************************************/ - -/* Get non-channel register from DMA1 or DMA2 */ - -static inline uint32_t dmabase_getreg(struct stm32_dma_s *dmach, - uint32_t offset) -{ - return getreg32(DMA_BASE(dmach->base) + offset); -} - -/* Write to non-channel register in DMA1 or DMA2 */ - -static inline void dmabase_putreg(struct stm32_dma_s *dmach, uint32_t offset, - uint32_t value) -{ - putreg32(value, DMA_BASE(dmach->base) + offset); -} - -/* Get channel register from DMA1 or DMA2 */ - -static inline uint32_t dmachan_getreg(struct stm32_dma_s *dmach, - uint32_t offset) -{ - return getreg32(dmach->base + offset); -} - -/* Write to channel register in DMA1 or DMA2 */ - -static inline void dmachan_putreg(struct stm32_dma_s *dmach, - uint32_t offset, uint32_t value) -{ - putreg32(value, dmach->base + offset); -} - -/**************************************************************************** - * Name: stm32_dmachandisable - * - * Description: - * Disable the DMA channel - * - ****************************************************************************/ - -static void stm32_dmachandisable(struct stm32_dma_s *dmach) -{ - uint32_t regval; - - /* Disable all interrupts at the DMA controller */ - - regval = dmachan_getreg(dmach, STM32_DMACHAN_CCR_OFFSET); - regval &= ~DMA_CCR_ALLINTS; - - /* Disable the DMA channel */ - - regval &= ~DMA_CCR_EN; - dmachan_putreg(dmach, STM32_DMACHAN_CCR_OFFSET, regval); - - /* Clear pending channel interrupts */ - - dmabase_putreg(dmach, STM32_DMA_IFCR_OFFSET, - DMA_ISR_CHAN_MASK(dmach->chan)); -} - -/**************************************************************************** - * Name: stm32_dmainterrupt - * - * Description: - * DMA interrupt handler - * - ****************************************************************************/ - -static int stm32_dmainterrupt(int irq, void *context, void *arg) -{ - struct stm32_dma_s *dmach; - uint32_t isr; - int chndx = 0; - - /* Get the channel structure from the interrupt number */ - - if (irq >= STM32_IRQ_DMA1CH1 && irq <= STM32_IRQ_DMA1CH7) - { - chndx = irq - STM32_IRQ_DMA1CH1; - } - else -#if STM32_NDMA > 1 - if (irq >= STM32_IRQ_DMA2CH1 && irq <= STM32_IRQ_DMA2CH5) - { - chndx = irq - STM32_IRQ_DMA2CH1 + DMA1_NCHANNELS; - } - else -#endif - { - DEBUGPANIC(); - } - - dmach = &g_dma[chndx]; - - /* Get the interrupt status (for this channel only) */ - - isr = dmabase_getreg(dmach, STM32_DMA_ISR_OFFSET) & - DMA_ISR_CHAN_MASK(dmach->chan); - - /* Clear the interrupts we are handling */ - - dmabase_putreg(dmach, STM32_DMA_IFCR_OFFSET, isr); - - /* Invoke the callback */ - - if (dmach->callback) - { - dmach->callback(dmach, isr >> DMA_ISR_CHAN_SHIFT(dmach->chan), - dmach->arg); - } - - return OK; -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_dmainitialize - * - * Description: - * Initialize the DMA subsystem - * - * Returned Value: - * None - * - ****************************************************************************/ - -void weak_function arm_dma_initialize(void) -{ - struct stm32_dma_s *dmach; - int chndx; - - /* Initialize each DMA channel */ - - for (chndx = 0; chndx < DMA_NCHANNELS; chndx++) - { - dmach = &g_dma[chndx]; - - /* Attach DMA interrupt vectors */ - - irq_attach(dmach->irq, stm32_dmainterrupt, NULL); - - /* Disable the DMA channel */ - - stm32_dmachandisable(dmach); - - /* Enable the IRQ at the NVIC (still disabled at the DMA controller) */ - - up_enable_irq(dmach->irq); - } -} - -/**************************************************************************** - * Name: stm32_dmachannel - * - * Description: - * Allocate a DMA channel. This function gives the caller mutually - * exclusive access to the DMA channel specified by the 'chndx' argument. - * DMA channels are shared on the STM32: Devices sharing the same DMA - * channel cannot do DMA concurrently! See the DMACHAN_* definitions in - * stm32_dma.h. - * - * If the DMA channel is not available, then stm32_dmachannel() will wait - * until the holder of the channel relinquishes the channel by calling - * stm32_dmafree(). WARNING: If you have two devices sharing a DMA - * channel and the code never releases the channel, the stm32_dmachannel - * call for the other will hang forever in this function! Don't let your - * design do that! - * - * Hmm.. I suppose this interface could be extended to make a non-blocking - * version. Feel free to do that if that is what you need. - * - * Input Parameters: - * chndx - Identifies the stream/channel resource. For the STM32 F1, this - * is simply the channel number as provided by the DMACHAN_* definitions - * in chip/stm32f10xxx_dma.h. - * - * Returned Value: - * Provided that 'chndx' is valid, this function ALWAYS returns a non-NULL, - * void* DMA channel handle. (If 'chndx' is invalid, the function will - * assert if debug is enabled or do something ignorant otherwise). - * - * Assumptions: - * - The caller does not hold he DMA channel. - * - The caller can wait for the DMA channel to be freed if it is no - * available. - * - ****************************************************************************/ - -DMA_HANDLE stm32_dmachannel(unsigned int chndef) -{ - int chndx = 0; - struct stm32_dma_s *dmach = NULL; - int ret; - -#ifdef DMA_HAVE_CSELR - chndx = (chndef & DMACHAN_SETTING_CHANNEL_MASK) >> - DMACHAN_SETTING_CHANNEL_SHIFT; -#else - chndx = chndef; -#endif - - dmach = &g_dma[chndx]; - - DEBUGASSERT(chndx < DMA_NCHANNELS); - - /* Get exclusive access to the DMA channel -- OR wait until the channel - * is available if it is currently being used by another driver - */ - - ret = nxsem_wait_uninterruptible(&dmach->sem); - if (ret < 0) - { - return NULL; - } - - /* The caller now has exclusive use of the DMA channel */ - -#ifdef DMA_HAVE_CSELR - /* Define the peripheral that will use the channel. This is stored until - * dmasetup is called. - */ - - dmach->function = (chndef & DMACHAN_SETTING_FUNCTION_MASK) >> - DMACHAN_SETTING_FUNCTION_SHIFT; -#endif - - return (DMA_HANDLE)dmach; -} - -/**************************************************************************** - * Name: stm32_dmafree - * - * Description: - * Release a DMA channel. If another thread is waiting for this DMA - * channel in a call to stm32_dmachannel, then this function will re-assign - * the DMA channel to that thread and wake it up. NOTE: The 'handle' used - * in this argument must NEVER be used again until stm32_dmachannel() is - * called again to re-gain access to the channel. - * - * Returned Value: - * None - * - * Assumptions: - * - The caller holds the DMA channel. - * - There is no DMA in progress - * - ****************************************************************************/ - -void stm32_dmafree(DMA_HANDLE handle) -{ - struct stm32_dma_s *dmach = (struct stm32_dma_s *)handle; - - DEBUGASSERT(handle != NULL); - - /* Release the channel */ - - nxsem_post(&dmach->sem); -} - -/**************************************************************************** - * Name: stm32_dmasetup - * - * Description: - * Configure DMA before using - * - ****************************************************************************/ - -void stm32_dmasetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr, - size_t ntransfers, uint32_t ccr) -{ - struct stm32_dma_s *dmach = (struct stm32_dma_s *)handle; - uint32_t regval; - - /* Then DMA_CNDTRx register can only be modified if the DMA channel is - * disabled. - */ - - regval = dmachan_getreg(dmach, STM32_DMACHAN_CCR_OFFSET); - regval &= ~(DMA_CCR_EN); - dmachan_putreg(dmach, STM32_DMACHAN_CCR_OFFSET, regval); - - /* Set the peripheral register address in the DMA_CPARx register. The data - * will be moved from/to this address to/from the memory after the - * peripheral event. - */ - - dmachan_putreg(dmach, STM32_DMACHAN_CPAR_OFFSET, paddr); - - /* Set the memory address in the DMA_CMARx register. The data will be - * written to or read from this memory after the peripheral event. - */ - - dmachan_putreg(dmach, STM32_DMACHAN_CMAR_OFFSET, maddr); - - /* Configure the total number of data to be transferred in the DMA_CNDTRx - * register. After each peripheral event, this value will be decremented. - */ - - dmachan_putreg(dmach, STM32_DMACHAN_CNDTR_OFFSET, ntransfers); - - /* Configure the channel priority using the PL[1:0] bits in the DMA_CCRx - * register. Configure data transfer direction, circular mode, peripheral - * and memory incremented mode, peripheral & memory data size, and - * interrupt after half and/or full transfer in the DMA_CCRx register. - */ - - regval = dmachan_getreg(dmach, STM32_DMACHAN_CCR_OFFSET); - regval &= ~(DMA_CCR_MEM2MEM | DMA_CCR_PL_MASK | DMA_CCR_MSIZE_MASK | - DMA_CCR_PSIZE_MASK | DMA_CCR_MINC | DMA_CCR_PINC | - DMA_CCR_CIRC | DMA_CCR_DIR); - ccr &= (DMA_CCR_MEM2MEM | DMA_CCR_PL_MASK | DMA_CCR_MSIZE_MASK | - DMA_CCR_PSIZE_MASK | DMA_CCR_MINC | DMA_CCR_PINC | - DMA_CCR_CIRC | DMA_CCR_DIR); - regval |= ccr; - dmachan_putreg(dmach, STM32_DMACHAN_CCR_OFFSET, regval); - -#ifdef DMA_HAVE_CSELR - /* Define peripheral indicated in dmach->function */ - - regval = dmabase_getreg(dmach, STM32_DMA_CSELR_OFFSET); - regval &= ~(0x0f << (dmach->chan << 2)); - regval |= (dmach->function << (dmach->chan << 2)); - dmabase_putreg(dmach, STM32_DMA_CSELR_OFFSET, regval); -#endif -} - -/**************************************************************************** - * Name: stm32_dmastart - * - * Description: - * Start the DMA transfer - * - * Assumptions: - * - DMA handle allocated by stm32_dmachannel() - * - No DMA in progress - * - ****************************************************************************/ - -void stm32_dmastart(DMA_HANDLE handle, dma_callback_t callback, - void *arg, bool half) -{ - struct stm32_dma_s *dmach = (struct stm32_dma_s *)handle; - uint32_t ccr; - - DEBUGASSERT(handle != NULL); - - /* Save the callback info. This will be invoked when the DMA completes. */ - - dmach->callback = callback; - dmach->arg = arg; - - /* Activate the channel by setting the ENABLE bit in the DMA_CCRx register. - * As soon as the channel is enabled, it can serve any DMA request from the - * peripheral connected on the channel. - */ - - ccr = dmachan_getreg(dmach, STM32_DMACHAN_CCR_OFFSET); - ccr |= DMA_CCR_EN; - - /* In normal mode, interrupt at either half or full completion. In circular - * mode, always interrupt on buffer wrap, and optionally interrupt at the - * halfway point. - */ - - if ((ccr & DMA_CCR_CIRC) == 0) - { - /* Once half of the bytes are transferred, the half-transfer flag - * (HTIF) is set and an interrupt is generated if the Half-Transfer - * Interrupt Enable bit (HTIE) is set. At the end of the transfer, the - * Transfer Complete Flag (TCIF) is set and an interrupt is generated - * if the Transfer Complete Interrupt Enable bit (TCIE) is set. - */ - - ccr |= (half ? (DMA_CCR_HTIE | DMA_CCR_TEIE) : - (DMA_CCR_TCIE | DMA_CCR_TEIE)); - } - else - { - /* In nonstop mode, when the transfer completes it immediately resets - * and starts again. The transfer-complete interrupt is thus always - * enabled, and the half-complete interrupt can be used in circular - * mode to determine when the buffer is half-full or in double-buffered - * mode to determine when one of the two buffers is full. - */ - - ccr |= (half ? DMA_CCR_HTIE : 0) | DMA_CCR_TCIE | DMA_CCR_TEIE; - } - - dmachan_putreg(dmach, STM32_DMACHAN_CCR_OFFSET, ccr); -} - -/**************************************************************************** - * Name: stm32_dmastop - * - * Description: - * Cancel the DMA. After stm32_dmastop() is called, the DMA channel is - * reset and stm32_dmasetup() must be called before stm32_dmastart() can be - * called again - * - * Assumptions: - * - DMA handle allocated by stm32_dmachannel() - * - ****************************************************************************/ - -void stm32_dmastop(DMA_HANDLE handle) -{ - struct stm32_dma_s *dmach = (struct stm32_dma_s *)handle; - stm32_dmachandisable(dmach); -} - -/**************************************************************************** - * Name: stm32_dmaresidual - * - * Description: - * Returns the number of bytes remaining to be transferred - * - * Assumptions: - * - DMA handle allocated by stm32_dmachannel() - * - ****************************************************************************/ - -size_t stm32_dmaresidual(DMA_HANDLE handle) -{ - struct stm32_dma_s *dmach = (struct stm32_dma_s *)handle; - - return dmachan_getreg(dmach, STM32_DMACHAN_CNDTR_OFFSET); -} - -/**************************************************************************** - * Name: stm32_dmacapable - * - * Description: - * Check if the DMA controller can transfer data to/from given memory - * address. This depends on the internal connections in the ARM bus matrix - * of the processor. Note that this only applies to memory addresses, it - * will return false for any peripheral address. - * - * Returned Value: - * True, if transfer is possible. - * - ****************************************************************************/ - -#ifdef CONFIG_STM32F0L0G0_DMACAPABLE -bool stm32_dmacapable(uintptr_t maddr, uint32_t count, uint32_t ccr) -{ - uint32_t transfer_size; - uint32_t mend; - - /* Verify that the address conforms to the memory transfer size. - * Transfers to/from memory performed by the DMA controller are - * required to be aligned to their size. - * - * See ST RM0090 rev4, section 9.3.11 - * - * Compute mend inline to avoid a possible non-constant integer - * multiply. - */ - - switch (ccr & DMA_CCR_MSIZE_MASK) - { - case DMA_CCR_MSIZE_8BITS: - transfer_size = 1; - mend = maddr + count - 1; - break; - - case DMA_CCR_MSIZE_16BITS: - transfer_size = 2; - mend = maddr + (count << 1) - 1; - break; - - case DMA_CCR_MSIZE_32BITS: - transfer_size = 4; - mend = maddr + (count << 2) - 1; - break; - - default: - return false; - } - - if ((maddr & (transfer_size - 1)) != 0) - { - return false; - } - - /* Verify that the transfer is to a memory region that supports DMA. */ - - if ((maddr & STM32_REGION_MASK) != (mend & STM32_REGION_MASK)) - { - return false; - } - - switch (maddr & STM32_REGION_MASK) - { - case STM32_SRAM_BASE: - case STM32_CODE_BASE: - - /* All RAM and flash is supported */ - - return true; - - default: - - /* Everything else is unsupported by DMA */ - - return false; - } -} -#endif - -/**************************************************************************** - * Name: stm32_dmasample - * - * Description: - * Sample DMA register contents - * - * Assumptions: - * - DMA handle allocated by stm32_dmachannel() - * - ****************************************************************************/ - -#ifdef CONFIG_DEBUG_DMA_INFO -void stm32_dmasample(DMA_HANDLE handle, struct stm32_dmaregs_s *regs) -{ - struct stm32_dma_s *dmach = (struct stm32_dma_s *)handle; - irqstate_t flags; - - flags = enter_critical_section(); - regs->isr = dmabase_getreg(dmach, STM32_DMA_ISR_OFFSET); -#ifdef DMA_HAVE_CSELR - regs->cselr = dmabase_getreg(dmach, STM32_DMA_CSELR_OFFSET); -#endif - regs->ccr = dmachan_getreg(dmach, STM32_DMACHAN_CCR_OFFSET); - regs->cndtr = dmachan_getreg(dmach, STM32_DMACHAN_CNDTR_OFFSET); - regs->cpar = dmachan_getreg(dmach, STM32_DMACHAN_CPAR_OFFSET); - regs->cmar = dmachan_getreg(dmach, STM32_DMACHAN_CMAR_OFFSET); - leave_critical_section(flags); -} -#endif - -/**************************************************************************** - * Name: stm32_dmadump - * - * Description: - * Dump previously sampled DMA register contents - * - * Assumptions: - * - DMA handle allocated by stm32_dmachannel() - * - ****************************************************************************/ - -#ifdef CONFIG_DEBUG_DMA_INFO -void stm32_dmadump(DMA_HANDLE handle, const struct stm32_dmaregs_s *regs, - const char *msg) -{ - struct stm32_dma_s *dmach = (struct stm32_dma_s *)handle; - uint32_t dmabase = DMA_BASE(dmach->base); - - dmainfo("DMA Registers: %s\n", msg); - dmainfo(" ISRC[%08" PRIx32 "]: %08" PRIx32 "\n", - dmabase + STM32_DMA_ISR_OFFSET, regs->isr); -#ifdef DMA_HAVE_CSELR - dmainfo(" CSELR[%08" PRIx32 "]: %08" PRIx32 "\n", - dmabase + STM32_DMA_CSELR_OFFSET, regs->cselr); -#endif - dmainfo(" CCR[%08" PRIx32 "]: %08" PRIx32 "\n", - dmach->base + STM32_DMACHAN_CCR_OFFSET, regs->ccr); - dmainfo(" CNDTR[%08" PRIx32 "]: %08" PRIx32 "\n", - dmach->base + STM32_DMACHAN_CNDTR_OFFSET, regs->cndtr); - dmainfo(" CPAR[%08" PRIx32 "]: %08" PRIx32 "\n", - dmach->base + STM32_DMACHAN_CPAR_OFFSET, regs->cpar); - dmainfo(" CMAR[%08" PRIx32 "]: %08" PRIx32 "\n", - dmach->base + STM32_DMACHAN_CMAR_OFFSET, regs->cmar); -} -#endif - -#ifdef CONFIG_ARCH_HIPRI_INTERRUPT - -/**************************************************************************** - * Name: stm32_dma_intack - * - * Description: - * Public visible interface to acknowledge interrupts on DMA channel - * - ****************************************************************************/ - -void stm32_dma_intack(unsigned int chndx, uint32_t isr) -{ - struct stm32_dma_s *dmach = &g_dma[chndx]; - - dmabase_putreg(dmach, STM32_DMA_IFCR_OFFSET, isr); -} - -/**************************************************************************** - * Name: stm32_dma_intget - * - * Description: - * Public visible interface to get pending interrupts from DMA channel - * - ****************************************************************************/ - -uint32_t stm32_dma_intget(unsigned int chndx) -{ - struct stm32_dma_s *dmach = &g_dma[chndx]; - - return dmabase_getreg(dmach, STM32_DMA_ISR_OFFSET) & - DMA_ISR_CHAN_MASK(dmach->chan); -} -#endif /* CONFIG_ARCH_HIPRI_INTERRUPT */ diff --git a/arch/arm/src/stm32f0l0g0/stm32_dma_v1mux.c b/arch/arm/src/stm32f0l0g0/stm32_dma_v1mux.c deleted file mode 100644 index a179bc8b9de49..0000000000000 --- a/arch/arm/src/stm32f0l0g0/stm32_dma_v1mux.c +++ /dev/null @@ -1,1463 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_dma_v1mux.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* Ported from arch/arm/src/stm32/stm32_dma_v1mux.c */ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -#include "arm_internal.h" -#include "sched/sched.h" -#include "stm32_dma.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#define DMAMUX_NUM 1 -#define DMA_CONTROLLERS 2 - -#ifdef CONFIG_STM32F0L0G0_DMA1 -# if defined(CONFIG_ARCH_CHIP_STM32C0) || \ - defined(CONFIG_STM32F0L0G0_STM32G03X) || \ - defined(CONFIG_STM32F0L0G0_STM32G041) -# define DMA1_NCHAN 5 -# define DMA2_NCHAN 0 -# elif defined(CONFIG_STM32F0L0G0_STM32G05X) || \ - defined(CONFIG_STM32F0L0G0_STM32G061) || \ - defined(CONFIG_STM32F0L0G0_STM32G07X) || \ - defined(CONFIG_STM32F0L0G0_STM32G081) -# define DMA1_NCHAN 7 -# define DMA2_NCHAN 0 -# elif defined(CONFIG_STM32F0L0G0_STM32G0BX) || \ - defined(CONFIG_STM32F0L0G0_STM32G0C1) -# define DMA1_NCHAN 7 -# define DMA2_NCHAN 5 -# else -# error "Unsupported STM32F0L0G0 subfamily" -# endif -#else -# define DMA1_NCHAN 0 -# define DMA2_NCHAN 0 -#endif - -#define DMA1_FIRST (0) -#define DMA1_LAST (DMA1_FIRST+DMA1_NCHAN) -#define DMA2_FIRST (DMA1_LAST) -#define DMA2_LAST (DMA2_FIRST+DMA2_NCHAN) - -/* All available DMA channels */ - -#define DMA_NCHANNELS (DMA1_NCHAN + DMA2_NCHAN) - -/* DMAMUX channels */ - -#if defined(CONFIG_ARCH_CHIP_STM32C0) || \ - defined(CONFIG_STM32F0L0G0_STM32G03X) || \ - defined(CONFIG_STM32F0L0G0_STM32G041) -# define DMAMUX_NCHANNELS 5 -#elif defined(CONFIG_STM32F0L0G0_STM32G05X) || \ - defined(CONFIG_STM32F0L0G0_STM32G061) || \ - defined(CONFIG_STM32F0L0G0_STM32G07X) || \ - defined(CONFIG_STM32F0L0G0_STM32G081) -# define DMAMUX_NCHANNELS 7 -#elif defined(CONFIG_STM32F0L0G0_STM32G0BX) || \ - defined(CONFIG_STM32F0L0G0_STM32G0C1) -# define DMAMUX_NCHANNELS 12 -#else -# error "Unknown chip for DMAMUX channel count" -#endif - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/* This structure described one DMAMUX device */ - -struct stm32_dmamux_s -{ - uint8_t id; /* DMAMUX id */ - uint8_t nchan; /* DMAMUX channels */ - uint32_t base; /* DMAMUX base address */ -}; - -typedef const struct stm32_dmamux_s *DMA_MUX; - -/* This structure describes one DMA controller */ - -struct stm32_dma_s -{ - uint8_t first; /* Offset in stm32_dmach_s array */ - uint8_t nchan; /* Number of channels */ - uint8_t dmamux_offset; /* DMAMUX channel offset */ - uint32_t base; /* Base address */ - DMA_MUX dmamux; /* DMAMUX associated with controller */ -}; - -/* This structure describes one DMA channel (DMA1, DMA2) */ - -struct stm32_dmach_s -{ - bool used; /* Channel in use */ - uint8_t dmamux_req; /* Configured DMAMUX input request */ - uint8_t ctrl; /* DMA controller */ - uint8_t chan; /* DMA channel channel id */ - uint8_t irq; /* DMA channel IRQ number */ - uint8_t shift; /* IFCR bit shift value */ - uint32_t base; /* DMA register channel base address */ - dma_callback_t callback; /* Callback invoked when the DMA completes */ - void *arg; /* Argument passed to callback function */ -}; - -typedef struct stm32_dmach_s *DMA_CHANNEL; - -/* DMA operations */ - -struct stm32_dma_ops_s -{ - /* Disable the DMA transfer */ - - void (*dma_disable)(DMA_CHANNEL dmachan); - - /* DMA interrupt */ - - int (*dma_interrupt)(int irq, void *context, void *arg); - - /* Setup the DMA */ - - void (*dma_setup)(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr, - size_t ntransfers, uint32_t ccr); - - /* Start the DMA */ - - void (*dma_start)(DMA_HANDLE handle, dma_callback_t callback, - void *arg, bool half); - - /* Read remaining DMA bytes */ - - size_t (*dma_residual)(DMA_HANDLE handle); - - /* Check the DMA configuration */ - - bool (*dma_capable)(uint32_t maddr, uint32_t count, uint32_t ccr); - -#ifdef CONFIG_DEBUG_DMA_INFO - /* Sample the DMA registers */ - - void (*dma_sample)(DMA_HANDLE handle, struct stm32_dmaregs_s *regs); - - /* Dump the DMA registers */ - - void (*dma_dump)(DMA_HANDLE handle, - const struct stm32_dmaregs_s *regs, - const char *msg); -#endif -}; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -#if defined(CONFIG_STM32F0L0G0_DMA1) || defined(CONFIG_STM32F0L0G0_DMA2) -static void stm32_dma12_disable(DMA_CHANNEL dmachan); -static int stm32_dma12_interrupt(int irq, void *context, void *arg); -static void stm32_dma12_setup(DMA_HANDLE handle, uint32_t paddr, - uint32_t maddr, size_t ntransfers, - uint32_t ccr); -static void stm32_dma12_start(DMA_HANDLE handle, dma_callback_t callback, - void *arg, bool half); -static size_t stm32_dma12_residual(DMA_HANDLE handle); -#ifdef CONFIG_DEBUG_DMA_INFO -static void stm32_dma12_sample(DMA_HANDLE handle, - struct stm32_dmaregs_s *regs); -static void stm32_dma12_dump(DMA_HANDLE handle, - const struct stm32_dmaregs_s *regs, - const char *msg); -#endif -#endif - -static uint32_t dmachan_getbase(DMA_CHANNEL dmachan); -static uint32_t dmabase_getreg(DMA_CHANNEL dmachan, uint32_t offset); -static void dmabase_putreg(DMA_CHANNEL dmachan, uint32_t offset, - uint32_t value); -static uint32_t dmachan_getreg(DMA_CHANNEL dmachan, uint32_t offset); -static void dmachan_putreg(DMA_CHANNEL dmachan, uint32_t offset, - uint32_t value); -static void dmamux_putreg(DMA_MUX dmamux, uint32_t offset, uint32_t value); -#ifdef CONFIG_DEBUG_DMA_INFO -static uint32_t dmamux_getreg(DMA_MUX dmamux, uint32_t offset); -static void stm32_dmamux_sample(DMA_MUX dmamux, uint8_t chan, - struct stm32_dmaregs_s *regs); -static void stm32_dmamux_dump(DMA_MUX dmamux, uint8_t channel, - const struct stm32_dmaregs_s *regs); -#endif -static DMA_CHANNEL stm32_dma_channel_get(uint8_t channel, - uint8_t controller); -static void stm32_gdma_limits_get(uint8_t controller, uint8_t *first, - uint8_t *last); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* Operations specific to DMA controller */ - -static const struct stm32_dma_ops_s g_dma_ops[DMA_CONTROLLERS] = -{ -#ifdef CONFIG_STM32F0L0G0_DMA1 - /* 0 - DMA1 */ - - { - .dma_disable = stm32_dma12_disable, - .dma_interrupt = stm32_dma12_interrupt, - .dma_setup = stm32_dma12_setup, - .dma_start = stm32_dma12_start, - .dma_residual = stm32_dma12_residual, -#ifdef CONFIG_DEBUG_DMA_INFO - .dma_sample = stm32_dma12_sample, - .dma_dump = stm32_dma12_dump, -#endif - }, -#else - { - NULL - }, -#endif - -#ifdef CONFIG_STM32F0L0G0_DMA2 - /* 1 - DMA2 */ - - { - .dma_disable = stm32_dma12_disable, - .dma_interrupt = stm32_dma12_interrupt, - .dma_setup = stm32_dma12_setup, - .dma_start = stm32_dma12_start, - .dma_residual = stm32_dma12_residual, -#ifdef CONFIG_DEBUG_DMA_INFO - .dma_sample = stm32_dma12_sample, - .dma_dump = stm32_dma12_dump, -#endif - } -#else - { - NULL - } -#endif -}; - -/* This array describes the state of DMAMUX controller */ - -static const struct stm32_dmamux_s g_dmamux[DMAMUX_NUM] = -{ - { - .id = 1, - .nchan = DMAMUX_NCHANNELS, - .base = STM32_DMAMUX1_BASE - } -}; - -/* This array describes the state of each controller */ - -static const struct stm32_dma_s g_dma[DMA_NCHANNELS] = -{ -#ifdef CONFIG_STM32F0L0G0_DMA1 - /* 0 - DMA1 */ - - { - .base = STM32_DMA1_BASE, - .first = DMA1_FIRST, - .nchan = DMA1_NCHAN, - .dmamux = &g_dmamux[DMAMUX1], /* DMAMUX1 channels 0-6 */ - .dmamux_offset = 0 - }, -#endif - -#ifdef CONFIG_STM32F0L0G0_DMA2 - /* 1 - DMA2 */ - - { - .base = STM32_DMA2_BASE, - .first = DMA2_FIRST, - .nchan = DMA2_NCHAN, - .dmamux = &g_dmamux[DMAMUX1], /* DMAMUX1 channels 7-13 */ - .dmamux_offset = 7 - } -#endif -}; - -/* This array describes the state of each DMA channel. */ - -static struct stm32_dmach_s g_dmach[DMA_NCHANNELS] = -{ -#ifdef CONFIG_STM32F0L0G0_DMA1 - /* DMA1 */ - - { - .ctrl = DMA1, - .chan = 0, - .irq = STM32_IRQ_DMA1CH1, - .shift = DMA_CHAN_SHIFT(0), - .base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(0), - }, - - { - .ctrl = DMA1, - .chan = 1, - .irq = STM32_IRQ_DMA1CH2, - .shift = DMA_CHAN_SHIFT(1), - .base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(1), - }, - - { - .ctrl = DMA1, - .chan = 2, - .irq = STM32_IRQ_DMA1CH3, - .shift = DMA_CHAN_SHIFT(2), - .base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(2), - }, - - { - .ctrl = DMA1, - .chan = 3, - .irq = STM32_IRQ_DMA1CH4, - .shift = DMA_CHAN_SHIFT(3), - .base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(3), - }, - - { - .ctrl = DMA1, - .chan = 4, - .irq = STM32_IRQ_DMA1CH5, - .shift = DMA_CHAN_SHIFT(4), - .base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(4), - }, - -# if DMA1_NCHAN > 5 - { - .ctrl = DMA1, - .chan = 5, - .irq = STM32_IRQ_DMA1CH6, - .shift = DMA_CHAN_SHIFT(5), - .base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(5), - }, -# endif - -# if DMA1_NCHAN > 6 - { - .ctrl = DMA1, - .chan = 6, - .irq = STM32_IRQ_DMA1CH7, - .shift = DMA_CHAN_SHIFT(6), - .base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(6), - }, -# endif - -# if DMA1_NCHAN > 7 - { - .ctrl = DMA1, - .chan = 7, - .irq = STM32_IRQ_DMA1CH8, - .shift = DMA_CHAN_SHIFT(7), - .base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(7), - }, -# endif -#endif - -#ifdef CONFIG_STM32F0L0G0_DMA2 - /* DMA2 */ - - { - .ctrl = DMA2, - .chan = 0, - .irq = STM32_IRQ_DMA2CH1, - .shift = DMA_CHAN_SHIFT(0), - .base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(0), - }, - - { - .ctrl = DMA2, - .chan = 1, - .irq = STM32_IRQ_DMA2CH2, - .shift = DMA_CHAN_SHIFT(1), - .base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(1), - }, - - { - .ctrl = DMA2, - .chan = 2, - .irq = STM32_IRQ_DMA2CH3, - .shift = DMA_CHAN_SHIFT(2), - .base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(2), - }, - - { - .ctrl = DMA2, - .chan = 3, - .irq = STM32_IRQ_DMA2CH4, - .shift = DMA_CHAN_SHIFT(3), - .base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(3), - }, - - { - .ctrl = DMA2, - .chan = 4, - .irq = STM32_IRQ_DMA2CH5, - .shift = DMA_CHAN_SHIFT(4), - .base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(4), - }, - -# if DMA2_NCHAN > 5 - { - .ctrl = DMA2, - .chan = 5, - .irq = STM32_IRQ_DMA2CH6, - .shift = DMA_CHAN_SHIFT(5), - .base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(5), - }, -# endif - -# if DMA2_NCHAN > 6 - { - .ctrl = DMA2, - .chan = 6, - .irq = STM32_IRQ_DMA2CH7, - .shift = DMA_CHAN_SHIFT(6), - .base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(6), - }, -# endif - -# if DMA2_NCHAN > 7 - { - .ctrl = DMA2, - .chan = 7, - .irq = STM32_IRQ_DMA2CH8, - .shift = DMA_CHAN_SHIFT(7), - .base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(7), - }, -# endif -#endif -}; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * DMA register access functions - ****************************************************************************/ - -/**************************************************************************** - * Name: dmachan_getbase - * - * Description: - * Get base DMA address for dmachan - * - ****************************************************************************/ - -static uint32_t dmachan_getbase(DMA_CHANNEL dmachan) -{ - uint8_t controller = dmachan->ctrl; - - return g_dma[controller].base; -} - -/**************************************************************************** - * Name: dmabase_getreg - * - * Description: - * Get non-channel register from DMA controller - * - ****************************************************************************/ - -static uint32_t dmabase_getreg(DMA_CHANNEL dmachan, uint32_t offset) -{ - uint32_t dmabase = dmachan_getbase(dmachan); - - return getreg32(dmabase + offset); -} - -/**************************************************************************** - * Name: dmabase_putreg - * - * Description: - * Write to non-channel register in DMA controller - * - ****************************************************************************/ - -static void dmabase_putreg(DMA_CHANNEL dmachan, uint32_t offset, - uint32_t value) -{ - uint32_t dmabase = dmachan_getbase(dmachan); - - putreg32(value, dmabase + offset); -} - -/**************************************************************************** - * Name: dmachan_getreg - * - * Description: - * Get channel register. - * - ****************************************************************************/ - -static uint32_t dmachan_getreg(DMA_CHANNEL dmachan, uint32_t offset) -{ - return getreg32(dmachan->base + offset); -} - -/**************************************************************************** - * Name: dmachan_putreg - * - * Description: - * Write to channel register. - * - ****************************************************************************/ - -static void dmachan_putreg(DMA_CHANNEL dmachan, uint32_t offset, - uint32_t value) -{ - putreg32(value, dmachan->base + offset); -} - -/**************************************************************************** - * Name: dmamux_getreg - * - * Description: - * Write to DMAMUX - * - ****************************************************************************/ - -static void dmamux_putreg(DMA_MUX dmamux, uint32_t offset, uint32_t value) -{ - putreg32(value, dmamux->base + offset); -} - -/**************************************************************************** - * Name: dmamux_getreg - * - * Description: - * Get DMAMUX register. - * - ****************************************************************************/ - -#ifdef CONFIG_DEBUG_DMA_INFO -static uint32_t dmamux_getreg(DMA_MUX dmamux, uint32_t offset) -{ - return getreg32(dmamux->base + offset); -} -#endif - -/**************************************************************************** - * Name: stm32_dma_channel_get - * - * Description: - * Get the g_dmach table entry associated with a given DMA controller - * and channel number. - * - ****************************************************************************/ - -static DMA_CHANNEL stm32_dma_channel_get(uint8_t channel, - uint8_t controller) -{ - uint8_t first = 0; - uint8_t nchan = 0; - - /* Get limits for g_dma array */ - - stm32_gdma_limits_get(controller, &first, &nchan); - - DEBUGASSERT(channel <= nchan); - - return &g_dmach[first + channel]; -} - -/**************************************************************************** - * Name: stm32_gdma_limits_get - * - * Description: - * Get g_dma array limits for a given DMA controller. - * - ****************************************************************************/ - -static void stm32_gdma_limits_get(uint8_t controller, uint8_t *first, - uint8_t *nchan) -{ - DEBUGASSERT(first != NULL); - DEBUGASSERT(nchan != NULL); - - DEBUGASSERT(controller >= DMA1 && controller <= DMA2); - - *first = g_dma[controller].first; - *nchan = g_dma[controller].nchan; -} - -/**************************************************************************** - * DMA controller functions - ****************************************************************************/ - -#if defined(CONFIG_STM32F0L0G0_DMA1) || defined(CONFIG_STM32F0L0G0_DMA2) - -/**************************************************************************** - * Name: stm32_dma12_disable - * - * Description: - * Disable DMA channel (DMA1/DMA2) - * - ****************************************************************************/ - -static void stm32_dma12_disable(DMA_CHANNEL dmachan) -{ - uint32_t regval; - - DEBUGASSERT(dmachan->ctrl == DMA1 || dmachan->ctrl == DMA2); - - /* Disable all interrupts at the DMA controller */ - - regval = dmachan_getreg(dmachan, STM32_DMACHAN_CCR_OFFSET); - regval &= ~DMA_CCR_ALLINTS; - - /* Disable the DMA channel */ - - regval &= ~DMA_CCR_EN; - dmachan_putreg(dmachan, STM32_DMACHAN_CCR_OFFSET, regval); - - /* Clear pending channel interrupts */ - - dmabase_putreg(dmachan, STM32_DMA_IFCR_OFFSET, - DMA_ISR_CHAN_MASK(dmachan->chan)); -} - -/**************************************************************************** - * Name: stm32_dma12_interrupt - * - * Description: - * DMA channel interrupt handler - * - ****************************************************************************/ - -static int stm32_dma12_interrupt(int irq, void *context, void *arg) -{ - DMA_CHANNEL dmachan; - uint32_t isr; - uint8_t channel; - uint8_t controller; - - /* Get the channel and the controller that generated the interrupt */ - - if (0) - { - } -#ifdef CONFIG_STM32F0L0G0_DMA1 - else if (irq >= STM32_IRQ_DMA1CH1 && irq <= STM32_IRQ_DMA1CH7) - { - channel = irq - STM32_IRQ_DMA1CH1; - controller = DMA1; - } -#endif -#ifdef CONFIG_STM32F0L0G0_DMA2 - else if (irq >= STM32_IRQ_DMA2CH1 && irq <= STM32_IRQ_DMA2CH5) - { - channel = irq - STM32_IRQ_DMA2CH1; - controller = DMA2; - } - else if (irq >= STM32_IRQ_DMA2CH6 && irq <= STM32_IRQ_DMA2CH7) - { - channel = irq - STM32_IRQ_DMA2CH6 + (6 - 1); - controller = DMA2; - } -#endif - else - { - DEBUGPANIC(); - return OK; - } - - /* Get the channel structure from the stream and controller numbers */ - - dmachan = stm32_dma_channel_get(channel, controller); - - /* Get the interrupt status (for this channel only) */ - - isr = dmabase_getreg(dmachan, STM32_DMA_ISR_OFFSET) & - DMA_ISR_CHAN_MASK(dmachan->chan); - - /* Invoke the callback */ - - if (dmachan->callback) - { - dmachan->callback(dmachan, isr >> DMA_ISR_CHAN_SHIFT(dmachan->chan), - dmachan->arg); - } - - /* Clear the interrupts we are handling */ - - dmabase_putreg(dmachan, STM32_DMA_IFCR_OFFSET, isr); - - return OK; -} - -/**************************************************************************** - * Name: stm32_dma12_setup - * - * Description: - * Configure DMA before using - * - ****************************************************************************/ - -static void stm32_dma12_setup(DMA_HANDLE handle, uint32_t paddr, - uint32_t maddr, size_t ntransfers, - uint32_t ccr) -{ - DMA_CHANNEL dmachan = (DMA_CHANNEL)handle; - uint32_t regval; - - DEBUGASSERT(handle != NULL); - DEBUGASSERT(ntransfers < 65536); - - DEBUGASSERT(dmachan->ctrl == DMA1 || dmachan->ctrl == DMA2); - - dmainfo("paddr: %08" PRIx32 " maddr: %08" PRIx32 - " ntransfers: %zd ccr: %08" PRIx32 "\n", - paddr, maddr, ntransfers, ccr); - -#ifdef CONFIG_STM32F0L0G0_DMACAPABLE - DEBUGASSERT(g_dma_ops[dmachan->ctrl].dma_capable(maddr, ntransfers, ccr)); -#endif - - /* Then DMA_CNDTRx register can only be modified if the DMA channel is - * disabled. - */ - - regval = dmachan_getreg(dmachan, STM32_DMACHAN_CCR_OFFSET); - regval &= ~(DMA_CCR_EN); - dmachan_putreg(dmachan, STM32_DMACHAN_CCR_OFFSET, regval); - - /* Set the peripheral register address in the DMA_CPARx register. The data - * will be moved from/to this address to/from the memory after the - * peripheral event. - */ - - dmachan_putreg(dmachan, STM32_DMACHAN_CPAR_OFFSET, paddr); - - /* Set the memory address in the DMA_CMARx register. The data will be - * written to or read from this memory after the peripheral event. - */ - - dmachan_putreg(dmachan, STM32_DMACHAN_CMAR_OFFSET, maddr); - - /* Configure the total number of data to be transferred in the DMA_CNDTRx - * register. After each peripheral event, this value will be decremented. - */ - - dmachan_putreg(dmachan, STM32_DMACHAN_CNDTR_OFFSET, ntransfers); - - /* Configure the channel priority using the PL[1:0] bits in the DMA_CCRx - * register. Configure data transfer direction, circular mode, peripheral - * & memory incremented mode, peripheral & memory data size, and interrupt - * after half and/or full transfer in the DMA_CCRx register. - */ - - regval = dmachan_getreg(dmachan, STM32_DMACHAN_CCR_OFFSET); - regval &= ~(DMA_CCR_MEM2MEM | DMA_CCR_PL_MASK | DMA_CCR_MSIZE_MASK | - DMA_CCR_PSIZE_MASK | DMA_CCR_MINC | DMA_CCR_PINC | - DMA_CCR_CIRC | DMA_CCR_DIR); - ccr &= (DMA_CCR_MEM2MEM | DMA_CCR_PL_MASK | DMA_CCR_MSIZE_MASK | - DMA_CCR_PSIZE_MASK | DMA_CCR_MINC | DMA_CCR_PINC | - DMA_CCR_CIRC | DMA_CCR_DIR); - regval |= ccr; - dmachan_putreg(dmachan, STM32_DMACHAN_CCR_OFFSET, regval); -} - -/**************************************************************************** - * Name: stm32_dma12_start - * - * Description: - * Start the standard DMA transfer - ****************************************************************************/ - -static void stm32_dma12_start(DMA_HANDLE handle, dma_callback_t callback, - void *arg, bool half) -{ - DMA_CHANNEL dmachan = (DMA_CHANNEL)handle; - uint32_t ccr; - - DEBUGASSERT(dmachan->ctrl == DMA1 || dmachan->ctrl == DMA2); - - /* Save the callback info. This will be invoked when the DMA completes */ - - dmachan->callback = callback; - dmachan->arg = arg; - - /* Activate the channel by setting the ENABLE bit in the DMA_CCRx register. - * As soon as the channel is enabled, it can serve any DMA request from the - * peripheral connected on the channel. - */ - - ccr = dmachan_getreg(dmachan, STM32_DMACHAN_CCR_OFFSET); - ccr |= DMA_CCR_EN; - - /* In normal mode, interrupt at either half or full completion. In circular - * mode, always interrupt on buffer wrap, and optionally interrupt at the - * halfway point. - */ - - if ((ccr & DMA_CCR_CIRC) == 0) - { - /* Once half of the bytes are transferred, the half-transfer flag - * (HTIF) is set and an interrupt is generated if the Half-Transfer - * Interrupt Enable bit (HTIE) is set. At the end of the transfer, - * the Transfer Complete Flag (TCIF) is set and an interrupt is - * generated if the Transfer Complete Interrupt Enable bit (TCIE) - * is set. - */ - - ccr |= (half ? (DMA_CCR_HTIE | DMA_CCR_TEIE) : - (DMA_CCR_TCIE | DMA_CCR_TEIE)); - } - else - { - /* In nonstop mode, when the transfer completes it immediately resets - * and starts again. The transfer-complete interrupt is thus always - * enabled, and the half-complete interrupt can be used in circular - * mode to determine when the buffer is half-full, or in - * double-buffered mode to determine when one of the two buffers - * is full. - */ - - ccr |= (half ? DMA_CCR_HTIE : 0) | DMA_CCR_TCIE | DMA_CCR_TEIE; - } - - dmachan_putreg(dmachan, STM32_DMACHAN_CCR_OFFSET, ccr); -} - -/**************************************************************************** - * Name: stm32_dma12_residual - ****************************************************************************/ - -static size_t stm32_dma12_residual(DMA_HANDLE handle) -{ - DMA_CHANNEL dmachan = (DMA_CHANNEL)handle; - - DEBUGASSERT(dmachan->ctrl == DMA1 || dmachan->ctrl == DMA2); - - return dmachan_getreg(dmachan, STM32_DMACHAN_CNDTR_OFFSET); -} - -/**************************************************************************** - * Name: stm32_dma12_sample - ****************************************************************************/ - -#ifdef CONFIG_DEBUG_DMA_INFO -void stm32_dma12_sample(DMA_HANDLE handle, struct stm32_dmaregs_s *regs) -{ - DMA_CHANNEL dmachan = (DMA_CHANNEL)handle; - irqstate_t flags; - - flags = enter_critical_section(); - - regs->isr = dmabase_getreg(dmachan, STM32_DMA_ISR_OFFSET); - regs->ccr = dmachan_getreg(dmachan, STM32_DMACHAN_CCR_OFFSET); - regs->cndtr = dmachan_getreg(dmachan, STM32_DMACHAN_CNDTR_OFFSET); - regs->cpar = dmachan_getreg(dmachan, STM32_DMACHAN_CPAR_OFFSET); - regs->cmar = dmachan_getreg(dmachan, STM32_DMACHAN_CMAR_OFFSET); - - stm32_dmamux_sample(g_dma[dmachan->ctrl].dmamux, - dmachan->chan + g_dma[dmachan->ctrl].dmamux_offset, - regs); - - leave_critical_section(flags); -} -#endif - -/**************************************************************************** - * Name: stm32_dma12_dump - ****************************************************************************/ - -#ifdef CONFIG_DEBUG_DMA_INFO -static void stm32_dma12_dump(DMA_HANDLE handle, - const struct stm32_dmaregs_s *regs, - const char *msg) -{ - DMA_CHANNEL dmachan = (DMA_CHANNEL)handle; - - DEBUGASSERT(dmachan->ctrl == DMA1 || dmachan->ctrl == DMA2); - - uint32_t dmabase = dmachan_getbase(dmachan); - - dmainfo("DMA%d Registers: %s\n", - dmachan->ctrl + 1, - msg); - dmainfo(" ISR[%08x]: %08x\n", - dmabase + STM32_DMA_ISR_OFFSET, - regs->isr); - dmainfo(" CCR[%08x]: %08x\n", - dmachan->base + STM32_DMACHAN_CCR_OFFSET, - regs->ccr); - dmainfo(" CNDTR[%08x]: %08x\n", - dmachan->base + STM32_DMACHAN_CNDTR_OFFSET, - regs->cndtr); - dmainfo(" CPAR[%08x]: %08x\n", - dmachan->base + STM32_DMACHAN_CPAR_OFFSET, - regs->cpar); - dmainfo(" CMAR[%08x]: %08x\n", - dmachan->base + STM32_DMACHAN_CMAR_OFFSET, - regs->cmar); - - stm32_dmamux_dump(g_dma[dmachan->ctrl].dmamux, - dmachan->chan + g_dma[dmachan->ctrl].dmamux_offset, - regs); -} -#endif - -#endif /* CONFIG_STM32F0L0G0_DMA1 || CONFIG_STM32F0L0G0_DMA2 */ - -/**************************************************************************** - * Name: stm32_dmamux_sample - ****************************************************************************/ - -#ifdef CONFIG_DEBUG_DMA_INFO -static void stm32_dmamux_sample(DMA_MUX dmamux, uint8_t chan, - struct stm32_dmaregs_s *regs) -{ - regs->dmamux.ccr = dmamux_getreg(dmamux, STM32_DMAMUX_CXCR_OFFSET(chan)); - regs->dmamux.csr = dmamux_getreg(dmamux, STM32_DMAMUX_CSR_OFFSET); - regs->dmamux.rg0cr = dmamux_getreg(dmamux, STM32_DMAMUX_RG0CR_OFFSET); - regs->dmamux.rg1cr = dmamux_getreg(dmamux, STM32_DMAMUX_RG1CR_OFFSET); - regs->dmamux.rg2cr = dmamux_getreg(dmamux, STM32_DMAMUX_RG2CR_OFFSET); - regs->dmamux.rg3cr = dmamux_getreg(dmamux, STM32_DMAMUX_RG3CR_OFFSET); - regs->dmamux.rgsr = dmamux_getreg(dmamux, STM32_DMAMUX_RGSR_OFFSET); -} -#endif - -/**************************************************************************** - * Name: stm32_dmamux_dump - ****************************************************************************/ - -#ifdef CONFIG_DEBUG_DMA_INFO -static void stm32_dmamux_dump(DMA_MUX dmamux, uint8_t channel, - const struct stm32_dmaregs_s *regs) -{ - dmainfo("DMAMUX%d CH=%d\n", dmamux->id, channel); - dmainfo(" CCR[%08" PRIx32 "]: %08" PRIx32 "\n", - dmamux->base + STM32_DMAMUX_CXCR_OFFSET(channel), - regs->dmamux.ccr); - dmainfo(" CSR[%08" PRIx32 "]: %08" PRIx32 "\n", - dmamux->base + STM32_DMAMUX_CSR_OFFSET, regs->dmamux.csr); - dmainfo(" RG0CR[%08" PRIx32 "]: %08" PRIx32 "\n", - dmamux->base + STM32_DMAMUX_RG0CR_OFFSET, regs->dmamux.rg0cr); - dmainfo(" RG1CR[%08" PRIx32 "]: %08" PRIx32 "\n", - dmamux->base + STM32_DMAMUX_RG1CR_OFFSET, regs->dmamux.rg1cr); - dmainfo(" RG2CR[%08" PRIx32 "]: %08" PRIx32 "\n", - dmamux->base + STM32_DMAMUX_RG2CR_OFFSET, regs->dmamux.rg2cr); - dmainfo(" RG3CR[%08" PRIx32 "]: %08" PRIx32 "\n", - dmamux->base + STM32_DMAMUX_RG3CR_OFFSET, regs->dmamux.rg3cr); - dmainfo(" RGSR[%08" PRIx32 "]: %08" PRIx32 "\n", - dmamux->base + STM32_DMAMUX_RGSR_OFFSET, regs->dmamux.rgsr); -}; -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: arm_dma_initialize - * - * Description: - * Initialize the DMA subsystem (DMA1, DMA2) - * - * Returned Value: - * None - * - ****************************************************************************/ - -void weak_function arm_dma_initialize(void) -{ - DMA_CHANNEL dmachan; - uint8_t controller; - int channel; - - dmainfo("Initialize DMA\n"); - - /* Initialize DMA channels */ - - for (channel = 0; channel < DMA_NCHANNELS; channel++) - { - dmachan = &g_dmach[channel]; - - /* Initialize flag */ - - dmachan->used = false; - - /* Get DMA controller associated with channel */ - - controller = dmachan->ctrl; - - DEBUGASSERT(controller >= DMA1 && controller <= DMA2); - - /* Attach standard DMA interrupt vectors */ - - irq_attach(dmachan->irq, g_dma_ops[controller].dma_interrupt, - dmachan); - - /* Disable the DMA channel */ - - g_dma_ops[controller].dma_disable(dmachan); - - /* Enable the IRQ at the NVIC (still disabled at the DMA controller) */ - - up_enable_irq(dmachan->irq); - } -} - -/**************************************************************************** - * Name: stm32_dmachannel - * - * Description: - * Allocate a DMA channel. This function gives the caller mutually - * exclusive access to the DMA channel specified by the 'dmamap' argument. - * It is common for both DMA controllers (DMA1 and DMA2). - * - * Input Parameters: - * dmamap - Identifies the stream/channel resource. For the STM32+, this - * is a bit-encoded value as provided by the DMAMAP_* definitions - * in hardware/stm32g4xxxx_dmamux.h - * - * Returned Value: - * On success, this function returns a non-NULL, void* DMA channel handle. - * NULL is returned on any failure. This function can fail only if no DMA - * channel is available. - * - * Assumptions: - * - The caller does not hold he DMA channel. - * - The caller can wait for the DMA channel to be freed if it is not - * available. - * - ****************************************************************************/ - -DMA_HANDLE stm32_dmachannel(unsigned int dmamap) -{ - DMA_CHANNEL dmachan; - uint8_t dmamux_req; - irqstate_t flags; - uint8_t controller; - uint8_t first = 0; - uint8_t nchan = 0; - int item = -1; - int i; - - /* Get DMA controller from encoded DMAMAP value */ - - controller = DMAMAP_CONTROLLER(dmamap); - DEBUGASSERT(controller >= DMA1 && controller <= DMA2); - - /* Get DMAMUX channel from encoded DMAMAP value */ - - dmamux_req = DMAMAP_REQUEST(dmamap); - - /* Get g_dma array limits for given controller */ - - stm32_gdma_limits_get(controller, &first, &nchan); - - /* Find available channel for given controller */ - - flags = enter_critical_section(); - for (i = first; i < first + nchan; i += 1) - { - if (g_dmach[i].used == false) - { - item = i; - g_dmach[i].used = true; - g_dmach[i].dmamux_req = dmamux_req; - break; - } - } - - leave_critical_section(flags); - - dmainfo("ctrl=%d item=%d\n", controller, item); - - if (item == -1) - { - dmainfo("No available DMA chan for CTRL=%d\n", - controller); - - /* No available channel */ - - return NULL; - } - - /* Assign DMA item */ - - dmachan = &g_dmach[item]; - - dmainfo("Get g_dmach[%d] CTRL=%d CH=%d\n", i, controller, dmachan->chan); - - /* Be sure that we have proper DMA controller */ - - DEBUGASSERT(dmachan->ctrl == controller); - - return (DMA_HANDLE)dmachan; -} - -/**************************************************************************** - * Name: stm32_dmafree - * - * Description: - * Release a DMA channel and unmap DMAMUX if required. - * - * NOTE: The 'handle' used in this argument must NEVER be used again - * until stm32_dmachannel() is called again to re-gain access to the - * channel. - * - * Returned Value: - * None - * - * Assumptions: - * - The caller holds the DMA channel. - * - There is no DMA in progress - * - ****************************************************************************/ - -void stm32_dmafree(DMA_HANDLE handle) -{ - DMA_CHANNEL dmachan = (DMA_CHANNEL)handle; - uint8_t controller; - irqstate_t flags; - - DEBUGASSERT(handle != NULL); - - /* Get DMA controller */ - - controller = dmachan->ctrl; - DEBUGASSERT(controller >= DMA1 && controller <= DMA2); - - dmainfo("Free g_dmach[%d] CTRL=%d CH=%d\n", dmachan - g_dmach, controller, - dmachan->chan); - UNUSED(controller); - - /* Release the channel */ - - flags = enter_critical_section(); - dmachan->used = false; - dmachan->dmamux_req = 0; - leave_critical_section(flags); -} - -/**************************************************************************** - * Name: stm32_dmasetup - * - * Description: - * Configure DMA before using - * - ****************************************************************************/ - -void stm32_dmasetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr, - size_t ntransfers, uint32_t ccr) -{ - DMA_CHANNEL dmachan = (DMA_CHANNEL)handle; - uint8_t controller; - - DEBUGASSERT(handle != NULL); - - /* Get DMA controller */ - - controller = dmachan->ctrl; - DEBUGASSERT(controller >= DMA1 && controller <= DMA2); - - g_dma_ops[controller].dma_setup(handle, paddr, maddr, ntransfers, ccr); -} - -/**************************************************************************** - * Name: stm32_dmastart - * - * Description: - * Start the DMA transfer - * - * Assumptions: - * - DMA handle allocated by stm32_dmachannel() - * - No DMA in progress - * - ****************************************************************************/ - -void stm32_dmastart(DMA_HANDLE handle, dma_callback_t callback, void *arg, - bool half) -{ - DMA_CHANNEL dmachan = (DMA_CHANNEL)handle; - DMA_MUX dmamux; - uint32_t regval; - uint8_t dmamux_chan; - uint8_t controller; - - DEBUGASSERT(handle != NULL); - - /* Get DMA controller */ - - controller = dmachan->ctrl; - DEBUGASSERT(controller >= DMA1 && controller <= DMA2); - - /* Recommended channel configure procedure in reference manual: - * 1. Set and configure the DMA channel y, except enabling the channel y. - * 2. Set and configure the related DMAMUX y channel. - * 3. Last, activate the DMA channel y. - */ - - /* Get DMAMUX associated with DMA controller */ - - dmamux = g_dma[controller].dmamux; - dmamux_chan = dmachan->chan + g_dma[controller].dmamux_offset; - - /* DMAMUX Set DMA channel source */ - - regval = dmachan->dmamux_req << DMAMUX_CCR_DMAREQID_SHIFT; - dmamux_putreg(dmamux, STM32_DMAMUX_CXCR_OFFSET(dmamux_chan), regval); - - /* Enable DMA channel */ - - g_dma_ops[controller].dma_start(handle, callback, arg, half); -} - -/**************************************************************************** - * Name: stm32_dmastop - * - * Description: - * Cancel the DMA. After stm32_dmastop() is called, the DMA channel is - * reset and stm32_dmasetup() must be called before stm32_dmastart() - * can be called again - * - * Assumptions: - * - DMA handle allocated by stm32_dmachannel() - * - ****************************************************************************/ - -void stm32_dmastop(DMA_HANDLE handle) -{ - DMA_CHANNEL dmachan = (DMA_CHANNEL)handle; - DMA_MUX dmamux; - uint8_t dmamux_chan; - uint8_t controller; - - DEBUGASSERT(handle != NULL); - - /* Get DMA controller */ - - controller = dmachan->ctrl; - DEBUGASSERT(controller >= DMA1 && controller <= DMA2); - - /* Get DMAMUX associated with DMA controller */ - - dmamux = g_dma[controller].dmamux; - dmamux_chan = dmachan->chan + g_dma[controller].dmamux_offset; - - /* Disable DMA channel */ - - g_dma_ops[controller].dma_disable(dmachan); - - /* DMAMUX Clear DMA channel source */ - - dmamux_putreg(dmamux, STM32_DMAMUX_CXCR_OFFSET(dmamux_chan), 0); -} - -/**************************************************************************** - * Name: stm32_dmaresidual - * - * Description: - * Read the DMA bytes-remaining register. - * - * Assumptions: - * - DMA handle allocated by stm32_dmachannel() - * - ****************************************************************************/ - -size_t stm32_dmaresidual(DMA_HANDLE handle) -{ - DMA_CHANNEL dmachan = (DMA_CHANNEL)handle; - uint8_t controller; - - DEBUGASSERT(handle != NULL); - - /* Get DMA controller */ - - controller = dmachan->ctrl; - DEBUGASSERT(controller >= DMA1 && controller <= DMA2); - - return g_dma_ops[controller].dma_residual(handle); -} - -/**************************************************************************** - * Name: stm32_dmacapable - * - * Description: - * Check if the DMA controller can transfer data to/from given memory - * address. This depends on the internal connections in the ARM bus matrix - * of the processor. Note that this only applies to memory addresses, it - * will return false for any peripheral address. - * - * Input Parameters: - * cfg - DMA transfer configuration - * - * Returned Value: - * True, if transfer is possible. - * - ****************************************************************************/ - -#ifdef CONFIG_STM32F0L0G0_DMACAPABLE -bool stm32_dmacapable(uint32_t maddr, uint32_t count, uint32_t ccr) -{ - unsigned int msize_shift; - uint32_t transfer_size; - uint32_t mend; - - /* Verify that the address conforms to the memory transfer size. - * Transfers to/from memory performed by the DMA controller are - * required to be aligned to their size. - * - * Datasheet 3.13 claims - * "Access to Flash, SRAM, APB and AHB peripherals as source - * and destination" - */ - - switch (ccr & DMA_CCR_MSIZE_MASK) - { - case DMA_CCR_MSIZE_8BITS: - msize_shift = 0; - break; - - case DMA_CCR_MSIZE_16BITS: - msize_shift = 1; - break; - - case DMA_CCR_MSIZE_32BITS: - msize_shift = 2; - break; - - default: - return false; - } - - transfer_size = 1 << msize_shift; - - if ((maddr & (transfer_size - 1)) != 0) - { - return false; - } - - /* Verify that the transfer is to a memory region that supports DMA. */ - - mend = maddr + (count << msize_shift) - 1; - - if ((maddr & STM32_REGION_MASK) != (mend & STM32_REGION_MASK)) - { - return false; - } - - switch (maddr & STM32_REGION_MASK) - { - case STM32_PERIPH_BASE: - case STM32_SRAM_BASE: - case STM32_CODE_BASE: - - /* All RAM and flash is supported */ - - return true; - - default: - - /* Everything else is unsupported by DMA */ - - return false; - } -} -#endif - -/**************************************************************************** - * Name: stm32_dmasample - * - * Description: - * Sample DMA register contents - * - * Assumptions: - * - DMA handle allocated by stm32_dmachannel() - * - ****************************************************************************/ - -#ifdef CONFIG_DEBUG_DMA_INFO -void stm32_dmasample(DMA_HANDLE handle, struct stm32_dmaregs_s *regs) -{ - DMA_CHANNEL dmachan = (DMA_CHANNEL)handle; - uint8_t controller; - - DEBUGASSERT(handle != NULL); - - /* Get DMA controller */ - - controller = dmachan->ctrl; - DEBUGASSERT(controller >= DMA1 && controller <= DMA2); - - g_dma_ops[controller].dma_sample(handle, regs); -} -#endif - -/**************************************************************************** - * Name: stm32_dmadump - * - * Description: - * Dump previously sampled DMA register contents - * - * Assumptions: - * - DMA handle allocated by stm32_dmachannel() - * - ****************************************************************************/ - -#ifdef CONFIG_DEBUG_DMA_INFO -void stm32_dmadump(DMA_HANDLE handle, const struct stm32_dmaregs_s *regs, - const char *msg) -{ - DMA_CHANNEL dmachan = (DMA_CHANNEL)handle; - uint8_t controller; - - DEBUGASSERT(handle != NULL); - - /* Get DMA controller */ - - controller = dmachan->ctrl; - DEBUGASSERT(controller >= DMA1 && controller <= DMA2); - - dmainfo("DMA %d CH%d Registers: %s\n", dmachan->ctrl, dmachan->ctrl, msg); - - g_dma_ops[controller].dma_dump(handle, regs, msg); -} -#endif diff --git a/arch/arm/src/stm32f0l0g0/stm32_exti.h b/arch/arm/src/stm32f0l0g0/stm32_exti.h deleted file mode 100644 index 33156f0dece9e..0000000000000 --- a/arch/arm/src/stm32f0l0g0/stm32_exti.h +++ /dev/null @@ -1,131 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_exti.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_STM32_EXTI_H -#define __ARCH_ARM_SRC_STM32F0L0G0_STM32_EXTI_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include "chip.h" -#include "hardware/stm32_exti.h" - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -#ifndef __ASSEMBLY__ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_gpiosetevent - * - * Description: - * Sets/clears GPIO based event and interrupt triggers. - * - * Input Parameters: - * - pinset: gpio pin configuration - * - rising/falling edge: enables - * - event: generate event when set - * - func: when non-NULL, generate interrupt - * - arg: Argument passed to the interrupt callback - * - * Returned Value: - * Zero (OK) on success; a negated errno value on failure indicating the - * nature of the failure. - * - ****************************************************************************/ - -int stm32_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, - bool event, xcpt_t func, void *arg); - -/**************************************************************************** - * Name: stm32_exti_alarm - * - * Description: - * Sets/clears EXTI alarm interrupt. - * - * Input Parameters: - * - rising/falling edge: enables interrupt on rising/falling edges - * - event: generate event when set - * - func: when non-NULL, generate interrupt - * - arg: Argument passed to the interrupt callback - * - * Returned Value: - * Zero (OK) on success; a negated errno value on failure indicating the - * nature of the failure. - * - ****************************************************************************/ - -#ifdef CONFIG_RTC_ALARM -int stm32_exti_alarm(bool risingedge, bool fallingedge, - bool event, xcpt_t func, - void *arg); -#endif - -/**************************************************************************** - * Name: stm32_exti_wakeup - * - * Description: - * Sets/clears EXTI wakeup interrupt. - * - * Input Parameters: - * - rising/falling edge: enables interrupt on rising/falling edges - * - event: generate event when set - * - func: when non-NULL, generate interrupt - * - arg: Argument passed to the interrupt callback - * - * Returned Value: - * Zero (OK) on success; a negated errno value on failure indicating the - * nature of the failure. - * - ****************************************************************************/ - -#ifdef CONFIG_RTC_PERIODIC -int stm32_exti_wakeup(bool risingedge, bool fallingedge, bool event, - xcpt_t func, void *arg); -#endif - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_STM32_EXTI_H */ diff --git a/arch/arm/src/stm32f0l0g0/stm32_exti_gpio.c b/arch/arm/src/stm32f0l0g0/stm32_exti_gpio.c deleted file mode 100644 index 433b0b6e39954..0000000000000 --- a/arch/arm/src/stm32f0l0g0/stm32_exti_gpio.c +++ /dev/null @@ -1,311 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_exti_gpio.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include -#include - -#include -#include -#include -#include - -#include - -#include "arm_internal.h" -#include "chip.h" -#include "stm32_gpio.h" -#include "stm32_exti.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#if defined(CONFIG_STM32F0L0G0_HAVE_IP_EXTI_V2) -# define STM32_EXTI_FTSR STM32_EXTI_FTSR1 -# define STM32_EXTI_RTSR STM32_EXTI_RTSR1 -# define STM32_EXTI_IMR STM32_EXTI_IMR1 -# define STM32_EXTI_EMR STM32_EXTI_EMR1 -#endif - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -struct gpio_callback_s -{ - xcpt_t callback; - void *arg; -}; - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* Interrupt handlers attached to each EXTI */ - -static struct gpio_callback_s g_gpio_callbacks[16]; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Interrupt Service Routines - Dispatchers - ****************************************************************************/ - -#if defined(CONFIG_STM32F0L0G0_HAVE_IP_EXTI_V1) -static int stm32_exti_multiisr(int irq, void *context, void *arg, - int first, int last) -{ - uint32_t pr; - int pin; - int ret = OK; - - /* Examine the state of each pin in the group */ - - pr = getreg32(STM32_EXTI_PR); - - /* And dispatch the interrupt to the handler */ - - for (pin = first; pin <= last; pin++) - { - /* Is an interrupt pending on this pin? */ - - uint32_t mask = (1 << pin); - if ((pr & mask) != 0) - { - /* Clear the pending interrupt */ - - putreg32(mask, STM32_EXTI_PR); - - /* And dispatch the interrupt to the handler */ - - if (g_gpio_callbacks[pin].callback != NULL) - { - xcpt_t callback = g_gpio_callbacks[pin].callback; - void *cbarg = g_gpio_callbacks[pin].arg; - int tmp; - - tmp = callback(irq, context, cbarg); - if (tmp < 0) - { - ret = tmp; - } - } - } - } - - return ret; -} -#elif defined(CONFIG_STM32F0L0G0_HAVE_IP_EXTI_V2) -static int stm32_exti_multiisr(int irq, void *context, void *arg, - int first, int last) -{ - uint32_t rpr; - uint32_t fpr; - int pin; - int ret = OK; - - /* Examine the state of each pin in the group. - * NOTE: We don't distinguish rising/falling edge! - */ - - rpr = getreg32(STM32_EXTI_RPR1); - fpr = getreg32(STM32_EXTI_FPR1); - - /* And dispatch the interrupt to the handler */ - - for (pin = first; pin <= last; pin++) - { - /* Is an interrupt pending on this pin? */ - - uint32_t mask = (1 << pin); - if (((rpr & mask) != 0) || ((fpr & mask) != 0)) - { - /* Clear the pending interrupt */ - - putreg32(mask, STM32_EXTI_RPR1); - putreg32(mask, STM32_EXTI_FPR1); - - /* And dispatch the interrupt to the handler */ - - if (g_gpio_callbacks[pin].callback != NULL) - { - xcpt_t callback = g_gpio_callbacks[pin].callback; - void *cbarg = g_gpio_callbacks[pin].arg; - int tmp; - - tmp = callback(irq, context, cbarg); - if (tmp < 0) - { - ret = tmp; - } - } - } - } - - return ret; -} -#endif - -static int stm32_exti01_isr(int irq, void *context, void *arg) -{ - return stm32_exti_multiisr(irq, context, arg, 0, 1); -} - -static int stm32_exti23_isr(int irq, void *context, void *arg) -{ - return stm32_exti_multiisr(irq, context, arg, 2, 3); -} - -static int stm32_exti415_isr(int irq, void *context, void *arg) -{ - return stm32_exti_multiisr(irq, context, arg, 4, 15); -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_gpiosetevent - * - * Description: - * Sets/clears GPIO based event and interrupt triggers. - * - * Input Parameters: - * - pinset: GPIO pin configuration - * - risingedge: Enables interrupt on rising edges - * - fallingedge: Enables interrupt on falling edges - * - event: Generate event when set - * - func: When non-NULL, generate interrupt - * - arg: Argument passed to the interrupt callback - * - * Returned Value: - * Zero (OK) on success; a negated errno value on failure indicating the - * nature of the failure. - * - ****************************************************************************/ - -int stm32_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, - bool event, xcpt_t func, void *arg) -{ - struct gpio_callback_s *shared_cbs; - uint32_t pin = pinset & GPIO_PIN_MASK; - uint32_t exti = STM32_EXTI_BIT(pin); - int irq; - xcpt_t handler; - int nshared; - int i; - - /* Select the interrupt handler for this EXTI pin */ - - if (pin < 2) - { - irq = STM32_IRQ_EXTI0_1; - handler = stm32_exti01_isr; - shared_cbs = &g_gpio_callbacks[0]; - nshared = 2; - } - else if (pin < 4) - { - irq = STM32_IRQ_EXTI2_3; - handler = stm32_exti23_isr; - shared_cbs = &g_gpio_callbacks[2]; - nshared = 2; - } - else - { - irq = STM32_IRQ_EXTI4_15; - handler = stm32_exti415_isr; - shared_cbs = &g_gpio_callbacks[4]; - nshared = 12; - } - - /* Get the previous GPIO IRQ handler; Save the new IRQ handler. */ - - g_gpio_callbacks[pin].callback = func; - g_gpio_callbacks[pin].arg = arg; - - /* Install external interrupt handlers */ - - if (func) - { - irq_attach(irq, handler, NULL); - up_enable_irq(irq); - } - else - { - /* Only disable IRQ if shared handler does not have any active - * callbacks. - */ - - for (i = 0; i < nshared; i++) - { - if (shared_cbs[i].callback != NULL) - { - break; - } - } - - if (i == nshared) - { - up_disable_irq(irq); - } - } - - /* Configure GPIO, enable EXTI line enabled if event or interrupt is - * enabled. - */ - - if (event || func) - { - pinset |= GPIO_EXTI; - } - - stm32_configgpio(pinset); - - /* Configure rising/falling edges */ - - modifyreg32(STM32_EXTI_RTSR, - risingedge ? 0 : exti, - risingedge ? exti : 0); - modifyreg32(STM32_EXTI_FTSR, - fallingedge ? 0 : exti, - fallingedge ? exti : 0); - - /* Enable Events and Interrupts */ - - modifyreg32(STM32_EXTI_EMR, - event ? 0 : exti, - event ? exti : 0); - modifyreg32(STM32_EXTI_IMR, - func ? 0 : exti, - func ? exti : 0); - - return OK; -} diff --git a/arch/arm/src/stm32f0l0g0/stm32_fdcan.c b/arch/arm/src/stm32f0l0g0/stm32_fdcan.c deleted file mode 100644 index 8f35cb89f26f6..0000000000000 --- a/arch/arm/src/stm32f0l0g0/stm32_fdcan.c +++ /dev/null @@ -1,3224 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_fdcan.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - *s - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include - -#include "arm_internal.h" -#include "stm32_fdcan.h" -#include "hardware/stm32_pinmap.h" -#include "stm32_gpio.h" -#include "stm32_rcc.h" - -/* Ported from arch/arm/src/stm32/stm32_fdcan.c */ - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Clock source *************************************************************/ - -#define FDCANCLK_PDIV (0) - -#if FDCANCLK_PDIV == 0 -# define STM32_FDCANCLK_FREQUENCY (STM32_FDCAN_FREQUENCY / (1)) -#else -# define STM32_FDCANCLK_FREQUENCY (STM32_FDCAN_FREQUENCY / (2 * FDCANCLK_PDIV)) -#endif - -/* General Configuration ****************************************************/ - -#if defined(CONFIG_ARCH_CHIP_STM32C0) - -/* FDCAN Message RAM */ - -# define FDCAN_MSGRAM_WORDS (212) -# define STM32_CANRAM1_BASE (STM32_CANRAM_BASE + 0x0000) - -# ifdef CONFIG_STM32F0L0G0_FDCAN1 -# define FDCAN1_STDFILTER_SIZE (28) -# define FDCAN1_EXTFILTER_SIZE (8) -# define FDCAN1_RXFIFO0_SIZE (3) -# define FDCAN1_RXFIFO1_SIZE (3) -# define FDCAN1_TXEVENTFIFO_SIZE (3) -# define FDCAN1_TXFIFIOQ_SIZE (3) - -# define FDCAN1_STDFILTER_WORDS (28) -# define FDCAN1_EXTFILTER_WORDS (16) -# define FDCAN1_RXFIFO0_WORDS (54) -# define FDCAN1_RXFIFO1_WORDS (54) -# define FDCAN1_TXEVENTFIFO_WORDS (6) -# define FDCAN1_TXFIFIOQ_WORDS (54) -# endif -#else -# error -#endif - -/* FDCAN1 Configuration *****************************************************/ - -#ifdef CONFIG_STM32F0L0G0_FDCAN1 - -/* Bit timing */ - -# define FDCAN1_NTSEG1 (CONFIG_STM32F0L0G0_FDCAN1_NTSEG1 - 1) -# define FDCAN1_NTSEG2 (CONFIG_STM32F0L0G0_FDCAN1_NTSEG2 - 1) -# define FDCAN1_NBRP ((STM32_FDCANCLK_FREQUENCY / \ - ((FDCAN1_NTSEG1 + FDCAN1_NTSEG2 + 3) * \ - CONFIG_STM32F0L0G0_FDCAN1_BITRATE)) - 1) -# define FDCAN1_NSJW (CONFIG_STM32F0L0G0_FDCAN1_NSJW - 1) - -# if FDCAN1_NTSEG1 > FDCAN_NBTP_NTSEG1_MAX -# error Invalid FDCAN1 NTSEG1 -# endif -# if FDCAN1_NTSEG2 > FDCAN_NBTP_NTSEG2_MAX -# error Invalid FDCAN1 NTSEG2 -# endif -# if FDCAN1_NSJW > FDCAN_NBTP_NSJW_MAX -# error Invalid FDCAN1 NSJW -# endif -# if FDCAN1_NBRP > FDCAN_NBTP_NBRP_MAX -# error Invalid FDCAN1 NBRP -# endif - -# ifdef CONFIG_STM32F0L0G0_FDCAN1_FD_BRS -# define FDCAN1_DTSEG1 (CONFIG_STM32F0L0G0_FDCAN1_DTSEG1 - 1) -# define FDCAN1_DTSEG2 (CONFIG_STM32F0L0G0_FDCAN1_DTSEG2 - 1) -# define FDCAN1_DBRP ((STM32_FDCANCLK_FREQUENCY / \ - ((FDCAN1_DTSEG1 + FDCAN1_DTSEG2 + 3) * \ - CONFIG_STM32F0L0G0_FDCAN1_DBITRATE)) - 1) -# define FDCAN1_DSJW (CONFIG_STM32F0L0G0_FDCAN1_DSJW - 1) -# else -# define FDCAN1_DTSEG1 1 -# define FDCAN1_DTSEG2 1 -# define FDCAN1_DBRP 1 -# define FDCAN1_DSJW 1 -# endif /* CONFIG_STM32F0L0G0_FDCAN1_FD_BRS */ - -# if FDCAN1_DTSEG1 > FDCAN_DBTP_DTSEG1_MAX -# error Invalid FDCAN1 DTSEG1 -# endif -# if FDCAN1_DTSEG2 > FDCAN_DBTP_DTSEG2_MAX -# error Invalid FDCAN1 DTSEG2 -# endif -# if FDCAN1_DBRP > FDCAN_DBTP_DBRP_MAX -# error Invalid FDCAN1 DBRP -# endif -# if FDCAN1_DSJW > FDCAN_DBTP_DSJW_MAX -# error Invalid FDCAN1 DSJW -# endif - -/* FDCAN1 Message RAM Configuration *****************************************/ - -/* FDCAN1 Message RAM Layout */ - -# define FDCAN1_STDFILTER_INDEX 0 -# define FDCAN1_EXTFILTERS_INDEX (FDCAN1_STDFILTER_INDEX + FDCAN1_STDFILTER_WORDS) -# define FDCAN1_RXFIFO0_INDEX (FDCAN1_EXTFILTERS_INDEX + FDCAN1_EXTFILTER_WORDS) -# define FDCAN1_RXFIFO1_INDEX (FDCAN1_RXFIFO0_INDEX + FDCAN1_RXFIFO0_WORDS) -# define FDCAN1_TXEVENTFIFO_INDEX (FDCAN1_RXFIFO1_INDEX + FDCAN1_RXFIFO1_WORDS) -# define FDCAN1_TXFIFOQ_INDEX (FDCAN1_TXEVENTFIFO_INDEX + FDCAN1_TXEVENTFIFO_WORDS) -# define FDCAN1_MSGRAM_WORDS (FDCAN1_TXFIFOQ_INDEX + FDCAN1_TXFIFIOQ_WORDS) - -#endif /* CONFIG_STM32F0L0G0_FDCAN1 */ - -/* Loopback mode */ - -#undef STM32_FDCAN_LOOPBACK -#if defined(CONFIG_STM32F0L0G0_FDCAN1_LOOPBACK) -# define STM32_FDCAN_LOOPBACK 1 -#endif - -/* Interrupts ***************************************************************/ - -/* Common interrupts - * - * FDCAN_INT_TSW - Timestamp Wraparound - * FDCAN_INT_MRAF - Message RAM Access Failure - * FDCAN_INT_TOO - Timeout Occurred - * FDCAN_INT_ELO - Error Logging Overflow - * FDCAN_INT_EP - Error Passive - * FDCAN_INT_EW - Warning Status - * FDCAN_INT_BO - Bus_Off Status - * FDCAN_INT_WDI - Watchdog Interrupt - * FDCAN_INT_PEA - Protocol Error in Arbritration Phase - * FDCAN_INT_PED - Protocol Error in Data Phase - */ - -#define FDCAN_CMNERR_INTS (FDCAN_INT_MRAF | FDCAN_INT_TOO | FDCAN_INT_EP | \ - FDCAN_INT_BO | FDCAN_INT_WDI | FDCAN_INT_PEA | \ - FDCAN_INT_PED) -#define FDCAN_COMMON_INTS FDCAN_CMNERR_INTS - -/* RXFIFO mode interrupts - * - * FDCAN_INT_RF0N - Receive FIFO 0 New Message - * FDCAN_INT_RF0F - Receive FIFO 0 Full - * FDCAN_INT_RF0L - Receive FIFO 0 Message Lost - * FDCAN_INT_RF1N - Receive FIFO 1 New Message - * FDCAN_INT_RF1F - Receive FIFO 1 Full - * FDCAN_INT_RF1L - Receive FIFO 1 Message Lost - * FDCAN_INT_HPM - High Priority Message Received - * - */ - -#define FDCAN_RXCOMMON_INTS 0 -#define FDCAN_RXFIFO0_INTS (FDCAN_INT_RF0N | FDCAN_INT_RF0L) -#define FDCAN_RXFIFO1_INTS (FDCAN_INT_RF1N | FDCAN_INT_RF1L) -#define FDCAN_RXFIFO_INTS (FDCAN_RXFIFO0_INTS | FDCAN_RXFIFO1_INTS | \ - FDCAN_INT_HPM | FDCAN_RXCOMMON_INTS) - -#define FDCAN_RXERR_INTS (FDCAN_INT_RF0L | FDCAN_INT_RF1L) - -/* TX FIFOQ mode interrupts - * - * FDCAN_INT_TFE - Tx FIFO Empty - * - * TX Event FIFO interrupts - * - * FDCAN_INT_TEFN - Tx Event FIFO New Entry - * FDCAN_INT_TEFF - Tx Event FIFO Full - * FDCAN_INT_TEFL - Tx Event FIFO Element Lost - * - * Mode-independent TX-related interrupts - * - * FDCAN_INT_TC - Transmission Completed - * FDCAN_INT_TCF - Transmission Cancellation Finished - */ - -#define FDCAN_TXCOMMON_INTS (FDCAN_INT_TC | FDCAN_INT_TCF) -#define FDCAN_TXFIFOQ_INTS (FDCAN_INT_TFE | FDCAN_TXCOMMON_INTS) -#define FDCAN_TXEVFIFO_INTS (FDCAN_INT_TEFN | FDCAN_INT_TEFF | \ - FDCAN_INT_TEFL) -#define FDCAN_TXDEDBUF_INTS FDCAN_TXCOMMON_INTS - -#define FDCAN_TXERR_INTS (FDCAN_INT_TEFL | FDCAN_INT_PEA | FDCAN_INT_PED) - -/* Common-, TX- and RX-Error-Mask */ - -#define FDCAN_ANYERR_INTS (FDCAN_CMNERR_INTS | FDCAN_RXERR_INTS | FDCAN_TXERR_INTS) - -/* Convenience macro for clearing all interrupts */ - -#define FDCAN_INT_ALL 0x3fcfffff - -/* Debug ********************************************************************/ - -/* Debug configurations that may be enabled just for testing FDCAN */ - -#ifndef CONFIG_DEBUG_CAN_INFO -# undef CONFIG_STM32F0L0G0_FDCAN_REGDEBUG -#endif - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/* CAN frame format */ - -enum stm32_frameformat_e -{ - FDCAN_ISO11898_1_FORMAT = 0, /* Frame format according to ISO11898-1 */ - FDCAN_NONISO_BOSCH_V1_FORMAT = 1 /* Frame format according to Bosch CAN FD V1.0 */ -}; - -/* CAN mode of operation */ - -enum stm32_canmode_e -{ - FDCAN_CLASSIC_MODE = 0, /* Classic CAN operation */ -#ifdef CONFIG_CAN_FD - FDCAN_FD_MODE = 1, /* CAN FD operation */ - FDCAN_FD_BRS_MODE = 2 /* CAN FD operation with bit rate switching */ -#endif -}; - -/* CAN driver state */ - -enum can_state_s -{ - FDCAN_STATE_UNINIT = 0, /* Not yet initialized */ - FDCAN_STATE_RESET, /* Initialized, reset state */ - FDCAN_STATE_SETUP, /* fdcan_setup() has been called */ - FDCAN_STATE_DISABLED /* Disabled by a fdcan_shutdown() */ -}; - -/* This structure describes the FDCAN message RAM layout */ - -struct stm32_msgram_s -{ - volatile uint32_t *stdfilters; /* Standard filters */ - volatile uint32_t *extfilters; /* Extended filters */ - volatile uint32_t *rxfifo0; /* RX FIFO0 */ - volatile uint32_t *rxfifo1; /* RX FIFO1 */ - volatile uint32_t *txeventfifo; /* TX event FIFO */ - volatile uint32_t *txfifoq; /* TX FIFO queue */ -}; - -/* This structure provides the constant configuration of a FDCAN peripheral */ - -struct stm32_config_s -{ - uint32_t rxpinset; /* RX pin configuration */ - uint32_t txpinset; /* TX pin configuration */ - uintptr_t base; /* Base address of the FDCAN registers */ - uint32_t baud; /* Configured baud */ - uint32_t nbtp; /* Nominal bit timing/prescaler register setting */ - uint32_t dbtp; /* Data bit timing/prescaler register setting */ - uint8_t port; /* FDCAN port number (1 or 2) */ - uint8_t irq0; /* FDCAN peripheral IRQ number for interrupt line 0 */ - uint8_t irq1; /* FDCAN peripheral IRQ number for interrupt line 1 */ - uint8_t mode; /* See enum stm32_canmode_e */ - uint8_t format; /* See enum stm32_frameformat_e */ - uint8_t nstdfilters; /* Number of standard filters */ - uint8_t nextfilters; /* Number of extended filters */ - uint8_t nrxfifo0; /* Number of RX FIFO0 elements */ - uint8_t nrxfifo1; /* Number of RX FIFO1 elements */ - uint8_t ntxeventfifo; /* Number of TXevent FIFO elements */ - uint8_t ntxfifoq; /* Number of TX FIFO queue elements */ - uint8_t rxfifo0esize; /* RX FIFO0 element size (words) */ - uint8_t rxfifo1esize; /* RX FIFO1 element size (words) */ - uint8_t txeventesize; /* TXevent element size (words) */ - uint8_t txbufferesize; /* TX buffer element size (words) */ -#ifdef STM32_FDCAN_LOOPBACK - bool loopback; /* True: Loopback mode */ -#endif - - /* FDCAN message RAM layout */ - - struct stm32_msgram_s msgram; -}; - -/* This structure provides the current state of a FDCAN peripheral */ - -struct stm32_fdcan_s -{ - /* The constant configuration */ - - const struct stm32_config_s *config; - - uint8_t state; /* See enum can_state_s */ -#ifdef CONFIG_CAN_EXTID - uint8_t nextalloc; /* Number of allocated extended filters */ -#endif - uint8_t nstdalloc; /* Number of allocated standard filters */ - uint32_t nbtp; /* Current nominal bit timing */ - uint32_t dbtp; /* Current data bit timing */ - uint32_t rxints; /* Configured RX interrupts */ - uint32_t txints; /* Configured TX interrupts */ - -#ifdef CONFIG_CAN_EXTID - uint32_t extfilters[2]; /* Extended filter bit allocator. 2*32=64 */ -#endif - uint32_t stdfilters[4]; /* Standard filter bit allocator. 4*32=128 */ - -#ifdef CONFIG_STM32F0L0G0_FDCAN_REGDEBUG - uintptr_t regaddr; /* Last register address read */ - uint32_t regval; /* Last value read from the register */ - unsigned int count; /* Number of times that the value was read */ -#endif -}; - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -/* FDCAN Register access */ - -static uint32_t fdcan_getreg(struct stm32_fdcan_s *priv, int offset); -static void fdcan_putreg(struct stm32_fdcan_s *priv, int offset, - uint32_t regval); -#ifdef CONFIG_STM32F0L0G0_FDCAN_REGDEBUG -static void fdcan_dumpregs(struct stm32_fdcan_s *priv, - const char *msg); -static void fdcan_dumprxregs(struct stm32_fdcan_s *priv, - const char *msg); -static void fdcan_dumptxregs(struct stm32_fdcan_s *priv, - const char *msg); -static void fdcan_dumpramlayout(struct stm32_fdcan_s *priv); -#else -# define fdcan_dumpregs(priv,msg) -# define fdcan_dumprxregs(priv,msg) -# define fdcan_dumptxregs(priv,msg) -# define fdcan_dumpramlayout(priv) -#endif - -/* FDCAN helpers */ - -static uint8_t fdcan_dlc2bytes(struct stm32_fdcan_s *priv, uint8_t dlc); - -#ifdef CONFIG_CAN_EXTID -static int fdcan_add_extfilter(struct stm32_fdcan_s *priv, - struct canioc_extfilter_s *extconfig); -static int fdcan_del_extfilter(struct stm32_fdcan_s *priv, int ndx); -#endif -static int fdcan_add_stdfilter(struct stm32_fdcan_s *priv, - struct canioc_stdfilter_s *stdconfig); -static int fdcan_del_stdfilter(struct stm32_fdcan_s *priv, int ndx); - -static int -fdcan_start_busoff_recovery_sequence(struct stm32_fdcan_s *priv); - -/* CAN driver methods */ - -static void fdcan_reset(struct can_dev_s *dev); -static int fdcan_setup(struct can_dev_s *dev); -static void fdcan_shutdown(struct can_dev_s *dev); -static void fdcan_rxint(struct can_dev_s *dev, bool enable); -static void fdcan_txint(struct can_dev_s *dev, bool enable); -static int fdcan_ioctl(struct can_dev_s *dev, int cmd, - unsigned long arg); -static int fdcan_remoterequest(struct can_dev_s *dev, uint16_t id); -static int fdcan_send(struct can_dev_s *dev, struct can_msg_s *msg); -static bool fdcan_txready(struct can_dev_s *dev); -static bool fdcan_txempty(struct can_dev_s *dev); - -/* FDCAN interrupt handling */ - -#ifdef CONFIG_CAN_ERRORS -static void fdcan_error(struct can_dev_s *dev, uint32_t status); -#endif -static void fdcan_receive(struct can_dev_s *dev, - volatile uint32_t *rxbuffer, - unsigned long nwords); -static int fdcan_interrupt(int irq, void *context, void *arg); - -/* Hardware initialization */ - -static int fdcan_hw_initialize(struct stm32_fdcan_s *priv); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -static const struct can_ops_s g_fdcanops = -{ - .co_reset = fdcan_reset, - .co_setup = fdcan_setup, - .co_shutdown = fdcan_shutdown, - .co_rxint = fdcan_rxint, - .co_txint = fdcan_txint, - .co_ioctl = fdcan_ioctl, - .co_remoterequest = fdcan_remoterequest, - .co_send = fdcan_send, - .co_txready = fdcan_txready, - .co_txempty = fdcan_txempty, -}; - -#ifdef CONFIG_STM32F0L0G0_FDCAN1 -/* Message RAM allocation */ - -/* Constant configuration */ - -static const struct stm32_config_s g_fdcan1const = -{ - .rxpinset = GPIO_FDCAN1_RX, - .txpinset = GPIO_FDCAN1_TX, - .base = STM32_FDCAN1_BASE, - .baud = CONFIG_STM32F0L0G0_FDCAN1_BITRATE, - .nbtp = FDCAN_NBTP_NBRP(FDCAN1_NBRP) | - FDCAN_NBTP_NTSEG1(FDCAN1_NTSEG1) | - FDCAN_NBTP_NTSEG2(FDCAN1_NTSEG2) | - FDCAN_NBTP_NSJW(FDCAN1_NSJW), - .dbtp = FDCAN_DBTP_DBRP(FDCAN1_DBRP) | - FDCAN_DBTP_DTSEG1(FDCAN1_DTSEG1) | - FDCAN_DBTP_DTSEG2(FDCAN1_DTSEG2) | - FDCAN_DBTP_DSJW(FDCAN1_DSJW), - .port = 1, - .irq0 = STM32_IRQ_FDCAN1_0, - .irq1 = STM32_IRQ_FDCAN1_1, -#if defined(CONFIG_STM32F0L0G0_FDCAN1_CLASSIC) - .mode = FDCAN_CLASSIC_MODE, -#elif defined(CONFIG_STM32F0L0G0_FDCAN1_FD) - .mode = FDCAN_FD_MODE, -#else - .mode = FDCAN_FD_BRS_MODE, -#endif -#if defined(CONFIG_STM32F0L0G0_FDCAN1_NONISO_FORMAT) - .format = FDCAN_NONISO_BOSCH_V1_FORMAT, -#else - .format = FDCAN_ISO11898_1_FORMAT, -#endif - .nstdfilters = FDCAN1_STDFILTER_SIZE, - .nextfilters = FDCAN1_EXTFILTER_SIZE, - .nrxfifo0 = FDCAN1_RXFIFO0_SIZE, - .nrxfifo1 = FDCAN1_RXFIFO1_SIZE, - .ntxeventfifo = FDCAN1_TXEVENTFIFO_SIZE, - .ntxfifoq = FDCAN1_TXFIFIOQ_SIZE, - .rxfifo0esize = (FDCAN1_RXFIFO0_WORDS / FDCAN1_RXFIFO0_SIZE), - .rxfifo1esize = (FDCAN1_RXFIFO1_WORDS / FDCAN1_RXFIFO1_SIZE), - .txeventesize = (FDCAN1_TXEVENTFIFO_WORDS / FDCAN1_TXEVENTFIFO_SIZE), - .txbufferesize = (FDCAN1_TXFIFIOQ_WORDS / FDCAN1_TXFIFIOQ_SIZE), - -#ifdef CONFIG_STM32F0L0G0_FDCAN1_LOOPBACK - .loopback = true, -#endif - - /* FDCAN1 Message RAM */ - - .msgram = - { - (uint32_t *)(STM32_CANRAM1_BASE + (FDCAN1_STDFILTER_INDEX << 2)), - (uint32_t *)(STM32_CANRAM1_BASE + (FDCAN1_EXTFILTERS_INDEX << 2)), - (uint32_t *)(STM32_CANRAM1_BASE + (FDCAN1_RXFIFO0_INDEX << 2)), - (uint32_t *)(STM32_CANRAM1_BASE + (FDCAN1_RXFIFO1_INDEX << 2)), - (uint32_t *)(STM32_CANRAM1_BASE + (FDCAN1_TXEVENTFIFO_INDEX << 2)), - (uint32_t *)(STM32_CANRAM1_BASE + (FDCAN1_TXFIFOQ_INDEX << 2)) - } -}; - -/* FDCAN1 variable driver state */ - -static struct stm32_fdcan_s g_fdcan1priv; -static struct can_dev_s g_fdcan1dev; - -#endif /* CONFIG_STM32F0L0G0_FDCAN1 */ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: fdcan_getreg - * - * Description: - * Read the value of a FDCAN register. - * - * Input Parameters: - * priv - A reference to the FDCAN peripheral state - * offset - The offset to the register to read - * - * Returned Value: - * - ****************************************************************************/ - -#ifdef CONFIG_STM32F0L0G0_FDCAN_REGDEBUG -static uint32_t fdcan_getreg(struct stm32_fdcan_s *priv, int offset) -{ - const struct stm32_config_s *config = priv->config; - uintptr_t regaddr = 0; - uint32_t regval = 0; - - /* Read the value from the register */ - - regaddr = config->base + offset; - regval = getreg32(regaddr); - - /* Is this the same value that we read from the same register last time? - * Are we polling the register? If so, suppress some of the output. - */ - - if (regaddr == priv->regaddr && regval == priv->regval) - { - if (priv->count == 0xffffffff || ++priv->count > 3) - { - if (priv->count == 4) - { - caninfo("...\n"); - } - - return regval; - } - } - - /* No this is a new address or value */ - - else - { - /* Did we print "..." for the previous value? */ - - if (priv->count > 3) - { - /* Yes.. then show how many times the value repeated */ - - caninfo("[repeats %d more times]\n", priv->count - 3); - } - - /* Save the new address, value, and count */ - - priv->regaddr = regaddr; - priv->regval = regval; - priv->count = 1; - } - - /* Show the register value read */ - - caninfo("%08" PRIx32 "->%08" PRIx32 "\n", regaddr, regval); - return regval; -} - -#else -static uint32_t fdcan_getreg(struct stm32_fdcan_s *priv, int offset) -{ - const struct stm32_config_s *config = priv->config; - return getreg32(config->base + offset); -} - -#endif - -/**************************************************************************** - * Name: fdcan_putreg - * - * Description: - * Set the value of a FDCAN register. - * - * Input Parameters: - * priv - A reference to the FDCAN peripheral state - * offset - The offset to the register to write - * regval - The value to write to the register - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef CONFIG_STM32F0L0G0_FDCAN_REGDEBUG -static void fdcan_putreg(struct stm32_fdcan_s *priv, int offset, - uint32_t regval) -{ - const struct stm32_config_s *config = priv->config; - uintptr_t regaddr = config->base + offset; - - /* Show the register value being written */ - - caninfo("%08" PRIx32 "->%08" PRIx32 "\n", regaddr, regval); - - /* Write the value */ - - putreg32(regval, regaddr); -} - -#else -static void fdcan_putreg(struct stm32_fdcan_s *priv, int offset, - uint32_t regval) -{ - const struct stm32_config_s *config = priv->config; - putreg32(regval, config->base + offset); -} - -#endif - -/**************************************************************************** - * Name: fdcan_dumpctrlregs - * - * Description: - * Dump the contents of all CAN control registers - * - * Input Parameters: - * priv - A reference to the CAN block status - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef CONFIG_STM32F0L0G0_FDCAN_REGDEBUG -static void fdcan_dumpregs(struct stm32_fdcan_s *priv, - const char *msg) -{ - const struct stm32_config_s *config = priv->config; - - caninfo("CAN%d Control and Status Registers: %s\n", config->port, msg); - caninfo(" Base: %08" PRIx32 "\n", config->base); - - /* CAN control and status registers */ - - caninfo(" CCCR: %08" PRIx32 " TEST: %08" PRIx32 "\n", - getreg32(config->base + STM32_FDCAN_CCCR_OFFSET), - getreg32(config->base + STM32_FDCAN_TEST_OFFSET)); - - caninfo(" NBTP: %08" PRIx32 " DBTP: %08" PRIx32 "\n", - getreg32(config->base + STM32_FDCAN_NBTP_OFFSET), - getreg32(config->base + STM32_FDCAN_DBTP_OFFSET)); - - caninfo(" IE: %08" PRIx32 " TIE: %08" PRIx32 "\n", - getreg32(config->base + STM32_FDCAN_IE_OFFSET), - getreg32(config->base + STM32_FDCAN_TXBTIE_OFFSET)); - - caninfo(" ILE: %08" PRIx32 " ILS: %08" PRIx32 "\n", - getreg32(config->base + STM32_FDCAN_ILE_OFFSET), - getreg32(config->base + STM32_FDCAN_ILS_OFFSET)); - - caninfo(" TXBC: %08" PRIx32 "\n", - getreg32(config->base + STM32_FDCAN_TXBC_OFFSET)); -} -#endif - -/**************************************************************************** - * Name: stm32can_dumprxregs - * - * Description: - * Dump the contents of all Rx status registers - * - * Input Parameters: - * priv - A reference to the CAN block status - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef CONFIG_STM32F0L0G0_FDCAN_REGDEBUG -static void fdcan_dumprxregs(struct stm32_fdcan_s *priv, - const char *msg) -{ - const struct stm32_config_s *config = priv->config; - - caninfo("CAN%d Rx Registers: %s\n", config->port, msg); - caninfo(" Base: %08" PRIx32 "\n", config->base); - - caninfo(" PSR: %08" PRIx32 " ECR: %08" PRIx32 - " HPMS: %08" PRIx32 "\n", - getreg32(config->base + STM32_FDCAN_PSR_OFFSET), - getreg32(config->base + STM32_FDCAN_ECR_OFFSET), - getreg32(config->base + STM32_FDCAN_HPMS_OFFSET)); - - caninfo(" RXF0S: %08" PRIx32 " RXF0A: %08" PRIx32 "\n", - getreg32(config->base + STM32_FDCAN_RXF0S_OFFSET), - getreg32(config->base + STM32_FDCAN_RXF0A_OFFSET)); - - caninfo(" RXF1S: %08" PRIx32 " RXF1A: %08" PRIx32 "\n", - getreg32(config->base + STM32_FDCAN_RXF1S_OFFSET), - getreg32(config->base + STM32_FDCAN_RXF1A_OFFSET)); - - caninfo(" IR: %08" PRIx32 " IE: %08" PRIx32 "\n", - getreg32(config->base + STM32_FDCAN_IR_OFFSET), - getreg32(config->base + STM32_FDCAN_IE_OFFSET)); -} -#endif - -/**************************************************************************** - * Name: stm32can_dumptxregs - * - * Description: - * Dump the contents of all Tx buffer registers - * - * Input Parameters: - * priv - A reference to the CAN block status - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef CONFIG_STM32F0L0G0_FDCAN_REGDEBUG -static void fdcan_dumptxregs(struct stm32_fdcan_s *priv, - const char *msg) -{ - const struct stm32_config_s *config = priv->config; - - caninfo("CAN%d Tx Registers: %s\n", config->port, msg); - caninfo(" Base: %08" PRIx32 "\n", config->base); - - caninfo(" PSR: %08" PRIx32 " ECR: %08" PRIx32 "\n", - getreg32(config->base + STM32_FDCAN_PSR_OFFSET), - getreg32(config->base + STM32_FDCAN_ECR_OFFSET)); - - caninfo(" TXQFS: %08" PRIx32 " TXBAR: %08" PRIx32 - " TXBRP: %08" PRIx32 "\n", - getreg32(config->base + STM32_FDCAN_TXFQS_OFFSET), - getreg32(config->base + STM32_FDCAN_TXBAR_OFFSET), - getreg32(config->base + STM32_FDCAN_TXBRP_OFFSET)); - - caninfo(" TXBTO: %08" PRIx32 " TXBCR: %08" PRIx32 "\n", - getreg32(config->base + STM32_FDCAN_TXBTO_OFFSET), - getreg32(config->base + STM32_FDCAN_TXBCR_OFFSET)); - - caninfo(" TXEFS: %08" PRIx32 " TXEFA: %08" PRIx32 "\n", - getreg32(config->base + STM32_FDCAN_TXEFS_OFFSET), - getreg32(config->base + STM32_FDCAN_TXEFA_OFFSET)); - - caninfo(" IR: %08" PRIx32 " IE: %08" PRIx32 - " TIE: %08" PRIx32 "\n", - getreg32(config->base + STM32_FDCAN_IR_OFFSET), - getreg32(config->base + STM32_FDCAN_IE_OFFSET), - getreg32(config->base + STM32_FDCAN_TXBTIE_OFFSET)); -} -#endif - -/**************************************************************************** - * Name: stm32can_dumpramlayout - * - * Description: - * Print the layout of the message RAM - * - * Input Parameters: - * priv - A reference to the CAN block status - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef CONFIG_STM32F0L0G0_FDCAN_REGDEBUG -static void fdcan_dumpramlayout(struct stm32_fdcan_s *priv) -{ - const struct stm32_config_s *config = priv->config; - - caninfo(" ******* FDCAN%d Message RAM layout *******\n", config->port); - caninfo(" Start # Elmnt Elmnt size (words)\n"); - - if (config->nstdfilters > 0) - { - caninfo("STD filters %p %4d %2d\n", - config->msgram.stdfilters, - config->nstdfilters, - 1); - } - - if (config->nextfilters > 0) - { - caninfo("EXT filters %p %4d %2d\n", - config->msgram.extfilters, - config->nextfilters, - 2); - } - - if (config->nrxfifo0 > 0) - { - caninfo("RX FIFO 0 %p %4d %2d\n", - config->msgram.rxfifo0, - config->nrxfifo0, - config->rxfifo0esize); - } - - if (config->nrxfifo1 > 0) - { - caninfo("RX FIFO 1 %p %4d %2d\n", - config->msgram.rxfifo1, - config->nrxfifo1, - config->rxfifo1esize); - } - - if (config->ntxeventfifo > 0) - { - caninfo("TX EVENT %p %4d %2d\n", - config->msgram.txeventfifo, - config->ntxeventfifo, - config->txeventesize); - } - - if (config->ntxfifoq > 0) - { - caninfo("TX FIFO %p %4d %2d\n", - config->msgram.txfifoq, - config->ntxfifoq, - config->txbufferesize); - } -} -#endif - -/**************************************************************************** - * Name: fdcan_dlc2bytes - * - * Description: - * In the CAN FD format, the coding of the DLC differs from the standard - * CAN format. The DLC codes 0 to 8 have the same coding as in standard - * CAN. But the codes 9 to 15 all imply a data field of 8 bytes with - * standard CAN. In CAN FD mode, the values 9 to 15 are encoded to values - * in the range 12 to 64. - * - * Input Parameters: - * dlc - the DLC value to convert to a byte count - * - * Returned Value: - * The number of bytes corresponding to the DLC value. - * - ****************************************************************************/ - -static uint8_t fdcan_dlc2bytes(struct stm32_fdcan_s *priv, uint8_t dlc) -{ - if (dlc > 8) - { -#ifdef CONFIG_CAN_FD - if (priv->config->mode == FDCAN_CLASSIC_MODE) - { - return 8; - } - else - { - switch (dlc) - { - case 9: - return 12; - case 10: - return 16; - case 11: - return 20; - case 12: - return 24; - case 13: - return 32; - case 14: - return 48; - default: - case 15: - return 64; - } - } -#else - return 8; -#endif - } - - return dlc; -} - -/**************************************************************************** - * Name: fdcan_add_extfilter - * - * Description: - * Add an address filter for a extended 29 bit address. - * - * Input Parameters: - * priv - An instance of the FDCAN driver state structure. - * extconfig - The configuration of the extended filter - * - * Returned Value: - * A non-negative filter ID is returned on success. Otherwise a negated - * errno value is returned to indicate the nature of the error. - * - ****************************************************************************/ - -#ifdef CONFIG_CAN_EXTID -static int fdcan_add_extfilter(struct stm32_fdcan_s *priv, - struct canioc_extfilter_s *extconfig) -{ - const struct stm32_config_s *config = NULL; - volatile uint32_t *extfilter = NULL; - uint32_t regval = 0; - int word = 0; - int bit = 0; - int ndx = 0; - - DEBUGASSERT(priv != NULL && priv->config != NULL && extconfig != NULL); - config = priv->config; - - /* Find an unused standard filter */ - - for (ndx = 0; ndx < config->nextfilters; ndx++) - { - /* Is this filter assigned? */ - - word = ndx >> 5; - bit = ndx & 0x1f; - - if ((priv->extfilters[word] & (1 << bit)) == 0) - { - /* No, assign the filter */ - - DEBUGASSERT(priv->nextalloc < priv->config->nstdfilters); - priv->extfilters[word] |= (1 << bit); - priv->nextalloc++; - - extfilter = config->msgram.extfilters + (ndx << 1); - - /* Format and write filter word F0 */ - - DEBUGASSERT(extconfig->xf_id1 <= CAN_MAX_EXTMSGID); - regval = EXTFILTER_F0_EFID1(extconfig->xf_id1); - - if (extconfig->xf_prio == 0) - { - regval |= EXTFILTER_F0_EFEC_FIFO0; - } - else - { - regval |= EXTFILTER_F0_EFEC_FIFO1; - } - - extfilter[0] = regval; - - /* Format and write filter word F1 */ - - DEBUGASSERT(extconfig->xf_id2 <= CAN_MAX_EXTMSGID); - regval = EXTFILTER_F1_EFID2(extconfig->xf_id2); - - switch (extconfig->xf_type) - { - case CAN_FILTER_DUAL: - { - regval |= EXTFILTER_F1_EFT_DUAL; - break; - } - - case CAN_FILTER_MASK: - { - regval |= EXTFILTER_F1_EFT_CLASSIC; - break; - } - - case CAN_FILTER_RANGE: - { - regval |= EXTFILTER_F1_EFT_RANGE; - break; - } - - default: - { - return -EINVAL; - } - } - - extfilter[1] = regval; - - /* Is this the first extended filter? */ - - if (priv->nextalloc == 1) - { - /* Enable the Initialization state */ - - regval = fdcan_getreg(priv, STM32_FDCAN_CCCR_OFFSET); - regval |= FDCAN_CCCR_INIT; - fdcan_putreg(priv, STM32_FDCAN_CCCR_OFFSET, regval); - - /* Wait for initialization mode to take effect */ - - while ((fdcan_getreg(priv, STM32_FDCAN_CCCR_OFFSET) & - FDCAN_CCCR_INIT) == 0); - - /* Enable writing to configuration registers */ - - regval = fdcan_getreg(priv, STM32_FDCAN_CCCR_OFFSET); - regval |= (FDCAN_CCCR_INIT | FDCAN_CCCR_CCE); - fdcan_putreg(priv, STM32_FDCAN_CCCR_OFFSET, regval); - - /* Update the Global Filter Configuration so that received - * messages are rejected if they do not match the acceptance - * filter. - * - * ANFE=2: Discard all rejected frames - */ - - regval = fdcan_getreg(priv, STM32_FDCAN_RXGFC_OFFSET); - regval &= ~FDCAN_RXGFC_ANFE_MASK; - regval |= FDCAN_RXGFC_ANFE_REJECTED; - fdcan_putreg(priv, STM32_FDCAN_RXGFC_OFFSET, regval); - - /* Disable writing to configuration registers */ - - regval = fdcan_getreg(priv, STM32_FDCAN_CCCR_OFFSET); - regval &= ~(FDCAN_CCCR_INIT | FDCAN_CCCR_CCE); - fdcan_putreg(priv, STM32_FDCAN_CCCR_OFFSET, regval); - } - - return ndx; - } - } - - DEBUGASSERT(priv->nextalloc == priv->config->nextfilters); - - return -EAGAIN; -} -#endif - -/**************************************************************************** - * Name: fdcan_del_extfilter - * - * Description: - * Remove an address filter for a standard 29 bit address. - * - * Input Parameters: - * priv - An instance of the FDCAN driver state structure. - * ndx - The filter index previously returned by the - * fdcan_add_extfilter(). - * - * Returned Value: - * Zero (OK) is returned on success. Otherwise a negated errno value is - * returned to indicate the nature of the error. - * - ****************************************************************************/ - -#ifdef CONFIG_CAN_EXTID -static int fdcan_del_extfilter(struct stm32_fdcan_s *priv, int ndx) -{ - const struct stm32_config_s *config = NULL; - volatile uint32_t *extfilter = NULL; - uint32_t regval = 0; - int word = 0; - int bit = 0; - - DEBUGASSERT(priv != NULL && priv->config != NULL); - config = priv->config; - - /* Check user Parameters */ - - DEBUGASSERT(ndx >= 0 || ndx < config->nextfilters); - - if (ndx < 0 || ndx >= config->nextfilters) - { - return -EINVAL; - } - - word = ndx >> 5; - bit = ndx & 0x1f; - - /* Check if this filter is really assigned */ - - if ((priv->extfilters[word] & (1 << bit)) == 0) - { - /* No, error out */ - - return -ENOENT; - } - - /* Release the filter */ - - priv->extfilters[word] &= ~(1 << bit); - - DEBUGASSERT(priv->nextalloc > 0); - priv->nextalloc--; - - /* Was that the last extended filter? */ - - if (priv->nextalloc == 0) - { - /* Enable the Initialization state */ - - regval = fdcan_getreg(priv, STM32_FDCAN_CCCR_OFFSET); - regval |= FDCAN_CCCR_INIT; - fdcan_putreg(priv, STM32_FDCAN_CCCR_OFFSET, regval); - - /* Wait for initialization mode to take effect */ - - while ((fdcan_getreg(priv, STM32_FDCAN_CCCR_OFFSET) & - FDCAN_CCCR_INIT) == 0); - - /* Enable writing to configuration registers */ - - regval = fdcan_getreg(priv, STM32_FDCAN_CCCR_OFFSET); - regval |= (FDCAN_CCCR_INIT | FDCAN_CCCR_CCE); - fdcan_putreg(priv, STM32_FDCAN_CCCR_OFFSET, regval); - - /* If there are no extended filters, then modify Global Filter - * Configuration so that all rejected messages are places in RX - * FIFO0. - * - * ANFE=0: Store all rejected extended frame in RX FIFO0 - */ - - regval = fdcan_getreg(priv, STM32_FDCAN_RXGFC_OFFSET); - regval &= ~FDCAN_RXGFC_ANFE_MASK; - regval |= FDCAN_RXGFC_ANFE_RX_FIFO0; - fdcan_putreg(priv, STM32_FDCAN_RXGFC_OFFSET, regval); - - /* Disable writing to configuration registers */ - - regval = fdcan_getreg(priv, STM32_FDCAN_CCCR_OFFSET); - regval &= ~(FDCAN_CCCR_INIT | FDCAN_CCCR_CCE); - fdcan_putreg(priv, STM32_FDCAN_CCCR_OFFSET, regval); - } - - /* Deactivate the filter last so that no messages are lost. */ - - extfilter = config->msgram.extfilters + (ndx << 1); - *extfilter++ = 0; - *extfilter = 0; - - return OK; -} -#endif - -/**************************************************************************** - * Name: fdcan_add_stdfilter - * - * Description: - * Add an address filter for a standard 11 bit address. - * - * Input Parameters: - * priv - An instance of the FDCAN driver state structure. - * stdconfig - The configuration of the standard filter - * - * Returned Value: - * A non-negative filter ID is returned on success. Otherwise a negated - * errno value is returned to indicate the nature of the error. - * - ****************************************************************************/ - -static int fdcan_add_stdfilter(struct stm32_fdcan_s *priv, - struct canioc_stdfilter_s *stdconfig) -{ - const struct stm32_config_s *config = NULL; - volatile uint32_t *stdfilter = NULL; - uint32_t regval = 0; - int word = 0; - int bit = 0; - int ndx = 0; - - DEBUGASSERT(priv != NULL && priv->config != NULL); - config = priv->config; - - /* Find an unused standard filter */ - - for (ndx = 0; ndx < config->nstdfilters; ndx++) - { - /* Is this filter assigned? */ - - word = ndx >> 5; - bit = ndx & 0x1f; - - if ((priv->stdfilters[word] & (1 << bit)) == 0) - { - /* No, assign the filter */ - - DEBUGASSERT(priv->nstdalloc < priv->config->nstdfilters); - priv->stdfilters[word] |= (1 << bit); - priv->nstdalloc++; - - /* Format and write filter word S0 */ - - stdfilter = config->msgram.stdfilters + ndx; - - DEBUGASSERT(stdconfig->sf_id1 <= CAN_MAX_STDMSGID); - regval = STDFILTER_S0_SFID1(stdconfig->sf_id1); - - DEBUGASSERT(stdconfig->sf_id2 <= CAN_MAX_STDMSGID); - regval |= STDFILTER_S0_SFID2(stdconfig->sf_id2); - - if (stdconfig->sf_prio == 0) - { - regval |= STDFILTER_S0_SFEC_FIFO0; - } - else - { - regval |= STDFILTER_S0_SFEC_FIFO1; - } - - switch (stdconfig->sf_type) - { - case CAN_FILTER_DUAL: - { - regval |= STDFILTER_S0_SFT_DUAL; - break; - } - - case CAN_FILTER_MASK: - { - regval |= STDFILTER_S0_SFT_CLASSIC; - break; - } - - case CAN_FILTER_RANGE: - { - regval |= STDFILTER_S0_SFT_RANGE; - break; - } - - default: - { - return -EINVAL; - } - } - - *stdfilter = regval; - - /* Is this the first standard filter? */ - - if (priv->nstdalloc == 1) - { - /* Enable the Initialization state */ - - regval = fdcan_getreg(priv, STM32_FDCAN_CCCR_OFFSET); - regval |= FDCAN_CCCR_INIT; - fdcan_putreg(priv, STM32_FDCAN_CCCR_OFFSET, regval); - - /* Wait for initialization mode to take effect */ - - while ((fdcan_getreg(priv, STM32_FDCAN_CCCR_OFFSET) & - FDCAN_CCCR_INIT) == 0); - - /* Enable writing to configuration registers */ - - regval = fdcan_getreg(priv, STM32_FDCAN_CCCR_OFFSET); - regval |= (FDCAN_CCCR_INIT | FDCAN_CCCR_CCE); - fdcan_putreg(priv, STM32_FDCAN_CCCR_OFFSET, regval); - - /* Update the Global Filter Configuration so that received - * messages are rejected if they do not match the acceptance - * filter. - * - * ANFS=2: Discard all rejected frames - */ - - regval = fdcan_getreg(priv, STM32_FDCAN_RXGFC_OFFSET); - regval &= ~FDCAN_RXGFC_ANFS_MASK; - regval |= FDCAN_RXGFC_ANFS_REJECTED; - fdcan_putreg(priv, STM32_FDCAN_RXGFC_OFFSET, regval); - - /* Disable writing to configuration registers */ - - regval = fdcan_getreg(priv, STM32_FDCAN_CCCR_OFFSET); - regval &= ~(FDCAN_CCCR_INIT | FDCAN_CCCR_CCE); - fdcan_putreg(priv, STM32_FDCAN_CCCR_OFFSET, regval); - } - - return ndx; - } - } - - DEBUGASSERT(priv->nstdalloc == priv->config->nstdfilters); - return -EAGAIN; -} - -/**************************************************************************** - * Name: fdcan_del_stdfilter - * - * Description: - * Remove an address filter for a standard 29 bit address. - * - * Input Parameters: - * priv - An instance of the FDCAN driver state structure. - * ndx - The filter index previously returned by the - * fdcan_add_stdfilter(). - * - * Returned Value: - * Zero (OK) is returned on success. Otherwise a negated errno value is - * returned to indicate the nature of the error. - * - ****************************************************************************/ - -static int fdcan_del_stdfilter(struct stm32_fdcan_s *priv, int ndx) -{ - const struct stm32_config_s *config = NULL; - volatile uint32_t *stdfilter = NULL; - uint32_t regval = 0; - int word = 0; - int bit = 0; - - DEBUGASSERT(priv != NULL && priv->config != NULL); - config = priv->config; - - /* Check Userspace Parameters */ - - DEBUGASSERT(ndx >= 0 || ndx < config->nstdfilters); - - if (ndx < 0 || ndx >= config->nstdfilters) - { - return -EINVAL; - } - - word = ndx >> 5; - bit = ndx & 0x1f; - - /* Check if this filter is really assigned */ - - if ((priv->stdfilters[word] & (1 << bit)) == 0) - { - /* No, error out */ - - return -ENOENT; - } - - /* Release the filter */ - - priv->stdfilters[word] &= ~(1 << bit); - - DEBUGASSERT(priv->nstdalloc > 0); - priv->nstdalloc--; - - /* Was that the last standard filter? */ - - if (priv->nstdalloc == 0) - { - /* Enable the Initialization state */ - - regval = fdcan_getreg(priv, STM32_FDCAN_CCCR_OFFSET); - regval |= FDCAN_CCCR_INIT; - fdcan_putreg(priv, STM32_FDCAN_CCCR_OFFSET, regval); - - /* Wait for initialization mode to take effect */ - - while ((fdcan_getreg(priv, STM32_FDCAN_CCCR_OFFSET) & - FDCAN_CCCR_INIT) == 0); - - /* Enable writing to configuration registers */ - - regval = fdcan_getreg(priv, STM32_FDCAN_CCCR_OFFSET); - regval |= (FDCAN_CCCR_INIT | FDCAN_CCCR_CCE); - fdcan_putreg(priv, STM32_FDCAN_CCCR_OFFSET, regval); - - /* If there are no standard filters, then modify Global Filter - * Configuration so that all rejected messages are places in RX - * FIFO0. - * - * ANFS=0: Store all rejected extended frame in RX FIFO0 - */ - - regval = fdcan_getreg(priv, STM32_FDCAN_RXGFC_OFFSET); - regval &= ~FDCAN_RXGFC_ANFS_MASK; - regval |= FDCAN_RXGFC_ANFS_RX_FIFO0; - fdcan_putreg(priv, STM32_FDCAN_RXGFC_OFFSET, regval); - - /* Disable writing to configuration registers */ - - regval = fdcan_getreg(priv, STM32_FDCAN_CCCR_OFFSET); - regval &= ~(FDCAN_CCCR_INIT | FDCAN_CCCR_CCE); - fdcan_putreg(priv, STM32_FDCAN_CCCR_OFFSET, regval); - } - - /* Deactivate the filter last so that no messages are lost. */ - - stdfilter = config->msgram.stdfilters + ndx; - *stdfilter = 0; - - return OK; -} - -/**************************************************************************** - * Name: fdcan_start_busoff_recovery_sequence - * - * Description: - * This function initiates the BUS-OFF recovery sequence. - * CAN Specification Rev. 2.0 or ISO11898-1:2015. - * According the STM32G4 datasheet section 44.3.2 Software initialziation. - * - * Input Parameters: - * priv - An instance of the FDCAN driver state structure. - * - * Returned Value: - * Zero (OK) is returned on success. Otherwise a negated errno value is - * returned to indicate the nature of the error. - * - ****************************************************************************/ - -static int -fdcan_start_busoff_recovery_sequence(struct stm32_fdcan_s *priv) -{ - uint32_t regval = 0; - - DEBUGASSERT(priv); - - /* Only start BUS-OFF recovery if we are in BUS-OFF state */ - - regval = fdcan_getreg(priv, STM32_FDCAN_PSR_OFFSET); - if ((regval & FDCAN_PSR_BO) == 0) - { - return -EPERM; - } - - /* Disable initialization mode to issue the recovery sequence */ - - regval = fdcan_getreg(priv, STM32_FDCAN_CCCR_OFFSET); - regval &= ~FDCAN_CCCR_INIT; - fdcan_putreg(priv, STM32_FDCAN_CCCR_OFFSET, regval); - - return OK; -} - -/**************************************************************************** - * Name: fdcan_reset - * - * Description: - * Reset the FDCAN device. Called early to initialize the hardware. This - * function is called, before fdcan_setup() and on error conditions. - * - * Input Parameters: - * dev - An instance of the "upper half" can driver state structure. - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void fdcan_reset(struct can_dev_s *dev) -{ - struct stm32_fdcan_s *priv = NULL; - const struct stm32_config_s *config = NULL; - uint32_t regval = 0; - irqstate_t flags; - - DEBUGASSERT(dev); - priv = dev->cd_priv; - DEBUGASSERT(priv); - config = priv->config; - DEBUGASSERT(config); - - caninfo("FDCAN%d\n", config->port); - UNUSED(config); - - /* Disable all interrupts */ - - fdcan_putreg(priv, STM32_FDCAN_IE_OFFSET, 0); - fdcan_putreg(priv, STM32_FDCAN_TXBTIE_OFFSET, 0); - - /* Make sure that all buffers are released. - * - * REVISIT: What if a thread is waiting for a buffer? The following - * will not wake up any waiting threads. - */ - - /* Disable the FDCAN controller. - * REVISIT: Should fdcan_shutdown() be called here? - */ - - /* Reset the FD CAN. - * REVISIT: Since there is only a single reset for both FDCAN - * controllers, do we really want to use the RCC reset here? - * This will nuke operation of the second controller if another - * device is registered. - */ - - flags = enter_critical_section(); - regval = getreg32(STM32_RCC_APB1RSTR); - regval |= RCC_APB1RSTR_FDCANRST; - putreg32(regval, STM32_RCC_APB1RSTR); - - regval &= ~RCC_APB1RSTR_FDCANRST; - putreg32(regval, STM32_RCC_APB1RSTR); - leave_critical_section(flags); - - priv->state = FDCAN_STATE_RESET; -} - -/**************************************************************************** - * Name: fdcan_setup - * - * Description: - * Configure the FDCAN. This method is called the first time that the FDCAN - * device is opened. This will occur when the port is first opened. - * This setup includes configuring and attaching FDCAN interrupts. - * All FDCAN interrupts are disabled upon return. - * - * Input Parameters: - * dev - An instance of the "upper half" can driver state structure. - * - * Returned Value: - * Zero on success; a negated errno on failure - * - ****************************************************************************/ - -static int fdcan_setup(struct can_dev_s *dev) -{ - struct stm32_fdcan_s *priv = NULL; - const struct stm32_config_s *config = NULL; - int ret = 0; - - DEBUGASSERT(dev); - priv = dev->cd_priv; - DEBUGASSERT(priv); - config = priv->config; - DEBUGASSERT(config); - - caninfo("FDCAN%d\n", config->port); - - /* FDCAN hardware initialization */ - - ret = fdcan_hw_initialize(priv); - if (ret < 0) - { - canerr("ERROR: FDCAN%d H/W initialization failed: %d\n", - config->port, ret); - return ret; - } - - fdcan_dumpregs(priv, "After hardware initialization"); - - /* Attach the FDCAN interrupt handlers */ - - ret = irq_attach(config->irq0, fdcan_interrupt, dev); - if (ret < 0) - { - canerr("ERROR: Failed to attach FDCAN%d line 0 IRQ (%d)", - config->port, config->irq0); - return ret; - } - - ret = irq_attach(config->irq1, fdcan_interrupt, dev); - if (ret < 0) - { - canerr("ERROR: Failed to attach FDCAN%d line 1 IRQ (%d)", - config->port, config->irq1); - return ret; - } - - priv->state = FDCAN_STATE_SETUP; - - /* Enable the interrupts at the NVIC (they are still disabled at the FDCAN - * peripheral). - */ - - up_enable_irq(config->irq0); - up_enable_irq(config->irq1); - - return OK; -} - -/**************************************************************************** - * Name: fdcan_shutdown - * - * Description: - * Disable the FDCAN. This method is called when the FDCAN device - * is closed. This method reverses the operation the setup method. - * - * Input Parameters: - * dev - An instance of the "upper half" can driver state structure. - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void fdcan_shutdown(struct can_dev_s *dev) -{ - struct stm32_fdcan_s *priv = NULL; - const struct stm32_config_s *config = NULL; - uint32_t regval = 0; - - DEBUGASSERT(dev); - priv = dev->cd_priv; - DEBUGASSERT(priv); - config = priv->config; - DEBUGASSERT(config); - - caninfo("FDCAN%d\n", config->port); - - /* Disable FDCAN interrupts at the NVIC */ - - up_disable_irq(config->irq0); - up_disable_irq(config->irq1); - - /* Disable all interrupts from the FDCAN peripheral */ - - fdcan_putreg(priv, STM32_FDCAN_IE_OFFSET, 0); - fdcan_putreg(priv, STM32_FDCAN_TXBTIE_OFFSET, 0); - - /* Detach the FDCAN interrupt handler */ - - irq_detach(config->irq0); - irq_detach(config->irq1); - - /* Disable device by setting the Clock Stop Request bit */ - - regval = fdcan_getreg(priv, STM32_FDCAN_CCCR_OFFSET); - regval |= FDCAN_CCCR_CSR; - fdcan_putreg(priv, STM32_FDCAN_CCCR_OFFSET, regval); - - /* Wait for Init and Clock Stop Acknowledge bits to verify - * device is in the powered down state - */ - - while ((fdcan_getreg(priv, STM32_FDCAN_CCCR_OFFSET) & FDCAN_CCCR_INIT) - == 0); - while ((fdcan_getreg(priv, STM32_FDCAN_CCCR_OFFSET) & FDCAN_CCCR_CSA) - == 0); - priv->state = FDCAN_STATE_DISABLED; -} - -/**************************************************************************** - * Name: fdcan_rxint - * - * Description: - * Call to enable or disable RX interrupts. - * - * Input Parameters: - * dev - An instance of the "upper half" can driver state structure. - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void fdcan_rxint(struct can_dev_s *dev, bool enable) -{ - struct stm32_fdcan_s *priv = dev->cd_priv; - uint32_t regval = 0; - - DEBUGASSERT(priv && priv->config); - - caninfo("FDCAN%d enable: %d\n", priv->config->port, enable); - - /* Enable/disable the receive interrupts */ - - regval = fdcan_getreg(priv, STM32_FDCAN_IE_OFFSET); - - if (enable) - { - regval |= priv->rxints | FDCAN_COMMON_INTS; - } - else - { - regval &= ~priv->rxints; - } - - fdcan_putreg(priv, STM32_FDCAN_IE_OFFSET, regval); -} - -/**************************************************************************** - * Name: fdcan_txint - * - * Description: - * Call to enable or disable TX interrupts. - * - * Input Parameters: - * dev - An instance of the "upper half" can driver state structure. - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void fdcan_txint(struct can_dev_s *dev, bool enable) -{ - struct stm32_fdcan_s *priv = dev->cd_priv; - uint32_t regval = 0; - - DEBUGASSERT(priv && priv->config); - - caninfo("FDCAN%d enable: %d\n", priv->config->port, enable); - - /* Enable/disable the receive interrupts */ - - regval = fdcan_getreg(priv, STM32_FDCAN_IE_OFFSET); - - if (enable) - { - regval |= priv->txints | FDCAN_COMMON_INTS; - } - else - { - regval &= ~priv->txints; - } - - fdcan_putreg(priv, STM32_FDCAN_IE_OFFSET, regval); -} - -/**************************************************************************** - * Name: fdcan_ioctl - * - * Description: - * All ioctl calls will be routed through this method - * - * Input Parameters: - * dev - An instance of the "upper half" can driver state structure. - * - * Returned Value: - * Zero on success; a negated errno on failure - * - ****************************************************************************/ - -static int fdcan_ioctl(struct can_dev_s *dev, int cmd, unsigned long arg) -{ - struct stm32_fdcan_s *priv = NULL; - int ret = -ENOTTY; - - caninfo("cmd=%04x arg=%lu\n", cmd, arg); - - DEBUGASSERT(dev && dev->cd_priv); - priv = dev->cd_priv; - - /* Handle the command */ - - switch (cmd) - { - /* CANIOC_GET_BITTIMING: - * Description: Return the current bit timing settings - * Argument: A pointer to a write-able instance of struct - * canioc_bittiming_s in which current bit timing - * values will be returned. - * Returned Value: Zero (OK) is returned on success. Otherwise -1 - * (ERROR) is returned with the errno variable set - * to indicate the nature of the error. - * Dependencies: None - */ - - case CANIOC_GET_BITTIMING: - { - struct canioc_bittiming_s *bt = - (struct canioc_bittiming_s *)arg; - uint32_t regval; - uint32_t nbrp; - - DEBUGASSERT(bt != NULL); - -#ifdef CONFIG_CAN_FD - if (bt->type == CAN_BITTIMING_DATA) - { - regval = fdcan_getreg(priv, STM32_FDCAN_DBTP_OFFSET); - bt->bt_sjw = ((regval & FDCAN_DBTP_DSJW_MASK) >> - FDCAN_DBTP_DSJW_SHIFT) + 1; - bt->bt_tseg1 = ((regval & FDCAN_DBTP_DTSEG1_MASK) >> - FDCAN_DBTP_DTSEG1_SHIFT) + 1; - bt->bt_tseg2 = ((regval & FDCAN_DBTP_DTSEG2_MASK) >> - FDCAN_DBTP_DTSEG2_SHIFT) + 1; - - nbrp = ((regval & FDCAN_DBTP_DBRP_MASK) >> - FDCAN_DBTP_DBRP_SHIFT) + 1; - bt->bt_baud = STM32_FDCANCLK_FREQUENCY / nbrp / - (bt->bt_tseg1 + bt->bt_tseg2 + 1); - } - else -#endif - { - regval = fdcan_getreg(priv, STM32_FDCAN_NBTP_OFFSET); - bt->bt_sjw = ((regval & FDCAN_NBTP_NSJW_MASK) >> - FDCAN_NBTP_NSJW_SHIFT) + 1; - bt->bt_tseg1 = ((regval & FDCAN_NBTP_NTSEG1_MASK) >> - FDCAN_NBTP_NTSEG1_SHIFT) + 1; - bt->bt_tseg2 = ((regval & FDCAN_NBTP_NTSEG2_MASK) >> - FDCAN_NBTP_NTSEG2_SHIFT) + 1; - - nbrp = ((regval & FDCAN_NBTP_NBRP_MASK) >> - FDCAN_NBTP_NBRP_SHIFT) + 1; - bt->bt_baud = STM32_FDCANCLK_FREQUENCY / nbrp / - (bt->bt_tseg1 + bt->bt_tseg2 + 1); - } - - ret = OK; - } - break; - - /* CANIOC_SET_BITTIMING: - * Description: Set new current bit timing values - * Argument: A pointer to a read-able instance of struct - * canioc_bittiming_s in which the new bit timing - * values are provided. - * Returned Value: Zero (OK) is returned on success. Otherwise -1 - * (ERROR) is returned with the errno variable set - * to indicate the nature of the error. - * Dependencies: None - * - * REVISIT: There is probably a limitation here: If there are - * multiple threads trying to send CAN packets, when one of these - * threads reconfigures the bitrate, the FDCAN hardware will be reset - * and the context of operation will be lost. Hence, this IOCTL can - * only safely be executed in quiescent time periods. - */ - - case CANIOC_SET_BITTIMING: - { - const struct canioc_bittiming_s *bt = - (const struct canioc_bittiming_s *)arg; - uint32_t nbrp; - uint32_t ntseg1; - uint32_t ntseg2; - uint32_t nsjw; - uint32_t ie; - uint8_t state; - - DEBUGASSERT(bt != NULL); - DEBUGASSERT(bt->bt_baud < STM32_FDCANCLK_FREQUENCY); - DEBUGASSERT(bt->bt_sjw > 0 && bt->bt_sjw <= 16); - DEBUGASSERT(bt->bt_tseg1 > 1 && bt->bt_tseg1 <= 64); - DEBUGASSERT(bt->bt_tseg2 > 0 && bt->bt_tseg2 <= 16); - - /* Extract bit timing data */ - - ntseg1 = bt->bt_tseg1 - 1; - ntseg2 = bt->bt_tseg2 - 1; - nsjw = bt->bt_sjw - 1; - - nbrp = (uint32_t) - (((float) STM32_FDCANCLK_FREQUENCY / - ((float)(ntseg1 + ntseg2 + 3) * (float)bt->bt_baud)) - 1); - - /* Save the value of the new bit timing register */ - -#ifdef CONFIG_CAN_FD - if (bt->type == CAN_BITTIMING_DATA) - { - priv->dbtp = FDCAN_NBTP_DBRP(nbrp) | - FDCAN_NBTP_DTSEG1(ntseg1) | - FDCAN_DBTP_DTSEG2(ntseg2) | - FDCAN_DBTP_DSJW(nsjw); - } - else -#endif - { - priv->nbtp = FDCAN_NBTP_NBRP(nbrp) | - FDCAN_NBTP_NTSEG1(ntseg1) | - FDCAN_NBTP_NTSEG2(ntseg2) | - FDCAN_NBTP_NSJW(nsjw); - } - - /* We need to reset to instantiate the new timing. Save - * current state information so that recover to this - * state. - */ - - ie = fdcan_getreg(priv, STM32_FDCAN_IE_OFFSET); - state = priv->state; - - /* Reset the FDCAN */ - - fdcan_reset(dev); - ret = OK; - - /* If we have previously been setup, then setup again */ - - if (state == FDCAN_STATE_SETUP) - { - ret = fdcan_setup(dev); - } - - /* We we have successfully re-initialized, then restore the - * interrupt state. - * - * REVISIT: Since the hardware was reset, any pending TX - * activity was lost. Should we disable TX interrupts? - */ - - if (ret == OK) - { - fdcan_putreg(priv, STM32_FDCAN_IE_OFFSET, ie & ~priv->txints); - } - } - break; - -#ifdef CONFIG_CAN_EXTID - /* CANIOC_ADD_EXTFILTER: - * Description: Add an address filter for a extended 29 bit - * address. - * Argument: A reference to struct canioc_extfilter_s - * Returned Value: A non-negative filter ID is returned on success. - * Otherwise -1 (ERROR) is returned with the errno - * variable set to indicate the nature of the error. - */ - - case CANIOC_ADD_EXTFILTER: - { - DEBUGASSERT(arg != 0); - - ret = fdcan_add_extfilter(priv, - (struct canioc_extfilter_s *)arg); - } - break; - - /* CANIOC_DEL_EXTFILTER: - * Description: Remove an address filter for a standard 29 bit - * address. - * Argument: The filter index previously returned by the - * CANIOC_ADD_EXTFILTER command - * Returned Value: Zero (OK) is returned on success. Otherwise -1 - * (ERROR) is returned with the errno variable set - * to indicate the nature of the error. - */ - - case CANIOC_DEL_EXTFILTER: - { - DEBUGASSERT(arg <= priv->config->nextfilters); - ret = fdcan_del_extfilter(priv, (int)arg); - } - break; -#endif - - /* CANIOC_ADD_STDFILTER: - * Description: Add an address filter for a standard 11 bit - * address. - * Argument: A reference to struct canioc_stdfilter_s - * Returned Value: A non-negative filter ID is returned on success. - * Otherwise -1 (ERROR) is returned with the errno - * variable set to indicate the nature of the error. - */ - - case CANIOC_ADD_STDFILTER: - { - DEBUGASSERT(arg != 0); - - ret = fdcan_add_stdfilter(priv, - (struct canioc_stdfilter_s *)arg); - } - break; - - /* CANIOC_DEL_STDFILTER: - * Description: Remove an address filter for a standard 11 bit - * address. - * Argument: The filter index previously returned by the - * CANIOC_ADD_STDFILTER command - * Returned Value: Zero (OK) is returned on success. Otherwise -1 - * (ERROR) is returned with the errno variable set - * to indicate the nature of the error. - */ - - case CANIOC_DEL_STDFILTER: - { - DEBUGASSERT(arg <= priv->config->nstdfilters); - ret = fdcan_del_stdfilter(priv, (int)arg); - } - break; - - /* CANIOC_BUSOFF_RECOVERY: - * Description : Initiates the BUS - OFF recovery sequence - * Argument : None - * Returned Value : Zero (OK) is returned on success. Otherwise -1 - * (ERROR) is returned with the errno variable set - * to indicate the nature of the error. - * Dependencies : None - */ - - case CANIOC_BUSOFF_RECOVERY: - { - ret = fdcan_start_busoff_recovery_sequence(priv); - } - break; - - /* Unsupported/unrecognized command */ - - default: - canerr("ERROR: Unrecognized command: %04x\n", cmd); - break; - } - - return ret; -} - -/**************************************************************************** - * Name: fdcan_remoterequest - * - * Description: - * Send a remote request - * - * Input Parameters: - * dev - An instance of the "upper half" can driver state structure. - * - * Returned Value: - * Zero on success; a negated errno on failure - * - ****************************************************************************/ - -static int fdcan_remoterequest(struct can_dev_s *dev, uint16_t id) -{ - /* REVISIT: Remote request not implemented */ - - return -ENOSYS; -} - -/**************************************************************************** - * Name: fdcan_send - * - * Description: - * Send one can message. - * - * One CAN-message consists of a maximum of 10 bytes. A message is - * composed of at least the first 2 bytes (when there are no data bytes). - * - * Byte 0: Bits 0-7: Bits 3-10 of the 11-bit CAN identifier - * Byte 1: Bits 5-7: Bits 0-2 of the 11-bit CAN identifier - * Bit 4: Remote Transmission Request (RTR) - * Bits 0-3: Data Length Code (DLC) - * Bytes 2-10: CAN data - * - * Input Parameters: - * dev - An instance of the "upper half" can driver state structure. - * - * Returned Value: - * Zero on success; a negated errno on failure - * - ****************************************************************************/ - -static int fdcan_send(struct can_dev_s *dev, struct can_msg_s *msg) -{ - struct stm32_fdcan_s *priv = NULL; - const struct stm32_config_s *config = NULL; - volatile uint32_t *txbuffer = NULL; - const uint8_t *src = NULL; - uint32_t *dest = NULL; - uint32_t regval = 0; - unsigned int ndx = 0; - unsigned int nbytes = 0; - uint32_t wordbuffer = 0; - unsigned int i = 0; - - DEBUGASSERT(dev); - priv = dev->cd_priv; - DEBUGASSERT(priv && priv->config); - config = priv->config; - - caninfo("CAN%" PRIu8 " ID: %" PRIu32 " DLC: %" PRIu8 "\n", - config->port, (uint32_t)msg->cm_hdr.ch_id, msg->cm_hdr.ch_dlc); - - fdcan_dumptxregs(priv, "Before send"); - - /* That that FIFO elements were configured */ - - DEBUGASSERT(config->ntxfifoq > 0); - - /* Get our reserved Tx FIFO/queue put index */ - - regval = fdcan_getreg(priv, STM32_FDCAN_TXFQS_OFFSET); - DEBUGASSERT((regval & FDCAN_TXFQS_TFQF) == 0); - - ndx = (regval & FDCAN_TXFQS_TFQPI_MASK) >> FDCAN_TXFQS_TFQPI_SHIFT; - - /* And the TX buffer corresponding to this index */ - - txbuffer = (config->msgram.txfifoq + ndx * config->txbufferesize); - - /* Format the TX FIFOQ entry - * - * Format word T0: - * Transfer message ID (ID) - Value from message structure - * Remote Transmission Request (RTR) - Value from message structure - * Extended Identifier (XTD) - Depends on configuration. - * Error state indicator (ESI) - ESI bit in CAN FD - * - * Format word T1: - * Data Length Code (DLC) - Value from message structure - * Bit Rate Switch (BRS) - Bit rate switching for CAN FD - * FD format (FDF) - Frame transmitted in CAN FD format - * Event FIFO Control (EFC) - Do not store events. - * Message Marker (MM) - Always zero - */ - - txbuffer[0] = 0; - txbuffer[1] = 0; - -#ifdef CONFIG_CAN_EXTID - if (msg->cm_hdr.ch_extid == 1) - { - DEBUGASSERT(msg->cm_hdr.ch_id <= CAN_MAX_EXTMSGID); - - txbuffer[0] |= BUFFER_R0_EXTID(msg->cm_hdr.ch_id) | BUFFER_R0_XTD; - } - else -#endif - { - DEBUGASSERT(msg->cm_hdr.ch_id <= CAN_MAX_STDMSGID); - - txbuffer[0] |= BUFFER_R0_STDID(msg->cm_hdr.ch_id); - } - - if (msg->cm_hdr.ch_rtr == 1) - { - txbuffer[0] |= BUFFER_R0_RTR; - } - - txbuffer[1] |= BUFFER_R1_DLC(msg->cm_hdr.ch_dlc); - -#ifdef CONFIG_CAN_FD - /* CAN FD Format */ - - if (msg->cm_hdr.ch_edl == 1) - { - txbuffer[1] |= BUFFER_R1_FDF; - - if (msg->cm_hdr.ch_brs == 1) - { - txbuffer[1] |= BUFFER_R1_BRS; - } - - if (msg->cm_hdr.ch_esi == 1) - { - txbuffer[0] |= BUFFER_R0_ESI; - } - } - else -#else - { - txbuffer[0] &= ~BUFFER_R0_ESI; - txbuffer[1] &= ~BUFFER_R1_FDF; - txbuffer[1] &= ~BUFFER_R1_BRS; - } -#endif - - /* Followed by the amount of data corresponding to the DLC (T2..) */ - - dest = (uint32_t *)&txbuffer[2]; - src = msg->cm_data; - nbytes = fdcan_dlc2bytes(priv, msg->cm_hdr.ch_dlc); - - /* Writes must be word length */ - - for (i = 0; i < nbytes; i += 4) - { - /* Little endian is assumed */ - - wordbuffer = src[0] | - (src[1] << 8) | - (src[2] << 16) | - (src[3] << 24); - src += 4; - - *dest++ = wordbuffer; - } - - /* Enable transmit interrupts from the TX FIFOQ buffer by setting TC - * interrupt bit in IR (also requires that the TC interrupt is enabled) - */ - - fdcan_putreg(priv, STM32_FDCAN_TXBTIE_OFFSET, (1 << ndx)); - - /* And request to send the packet */ - - fdcan_putreg(priv, STM32_FDCAN_TXBAR_OFFSET, (1 << ndx)); - - return OK; -} - -/**************************************************************************** - * Name: fdcan_txready - * - * Description: - * Return true if the FDCAN hardware can accept another TX message. - * - * Input Parameters: - * dev - An instance of the "upper half" can driver state structure. - * - * Returned Value: - * True if the FDCAN hardware is ready to accept another TX message. - * - ****************************************************************************/ - -static bool fdcan_txready(struct can_dev_s *dev) -{ - struct stm32_fdcan_s *priv = dev->cd_priv; - uint32_t regval = 0; - bool notfull = false; - - /* Return the state of the TX FIFOQ. Return TRUE if the TX FIFO/Queue is - * not full. - */ - - regval = fdcan_getreg(priv, STM32_FDCAN_TXFQS_OFFSET); - notfull = ((regval & FDCAN_TXFQS_TFQF) == 0); - - return notfull; -} - -/**************************************************************************** - * Name: fdcan_txempty - * - * Description: - * Return true if all message have been sent. If for example, the FDCAN - * hardware implements FIFOs, then this would mean the transmit FIFO is - * empty. This method is called when the driver needs to make sure that - * all characters are "drained" from the TX hardware before calling - * co_shutdown(). - * - * Input Parameters: - * dev - An instance of the "upper half" can driver state structure. - * - * Returned Value: - * True if there are no pending TX transfers in the FDCAN hardware. - * - ****************************************************************************/ - -static bool fdcan_txempty(struct can_dev_s *dev) -{ - struct stm32_fdcan_s *priv = dev->cd_priv; - uint32_t regval = 0; - int tffl = 0; - bool empty = false; - - DEBUGASSERT(priv != NULL && priv->config != NULL); - - /* Return the state of the TX FIFOQ. Return TRUE if the TX FIFO/Queue is - * empty. We don't have a reliable indication that the FIFO is empty, so - * we have to use some heuristics. - */ - - regval = fdcan_getreg(priv, STM32_FDCAN_TXFQS_OFFSET); - if ((regval & FDCAN_TXFQS_TFQF) != 0) - { - return false; - } - - /* Tx FIFO Free Level */ - - tffl = (regval & FDCAN_TXFQS_TFFL_MASK) >> FDCAN_TXFQS_TFFL_SHIFT; - empty = (tffl >= priv->config->ntxfifoq); - - return empty; -} - -/**************************************************************************** - * Name: fdcan_error - * - * Description: - * Report a CAN error - * - * Input Parameters: - * dev - CAN-common state data - * status - Interrupt status with error bits set - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef CONFIG_CAN_ERRORS -static void fdcan_error(struct can_dev_s *dev, uint32_t status) -{ - struct stm32_fdcan_s *priv = dev->cd_priv; - struct can_hdr_s hdr; - uint32_t psr = 0; - uint16_t errbits = 0; - uint8_t data[CAN_ERROR_DLC]; - int ret = 0; - - /* Encode error bits */ - - errbits = 0; - memset(data, 0, sizeof(data)); - - /* Always fill in "static" error conditions, but set the signaling bit - * only if the condition has changed (see IRQ-Flags below) - * They have to be filled in every time CAN_ERROR_CONTROLLER is set. - */ - - psr = fdcan_getreg(priv, STM32_FDCAN_PSR_OFFSET); - if ((psr & FDCAN_PSR_EP) != 0) - { - data[1] |= (CAN_ERROR1_RXPASSIVE | CAN_ERROR1_TXPASSIVE); - } - - if ((psr & FDCAN_PSR_EW) != 0) - { - data[1] |= (CAN_ERROR1_RXWARNING | CAN_ERROR1_TXWARNING); - } - - if ((status & (FDCAN_INT_EP | FDCAN_INT_EW)) != 0) - { - /* "Error Passive" or "Error Warning" status changed */ - - errbits |= CAN_ERROR_CONTROLLER; - } - - if ((status & FDCAN_INT_PEA) != 0) - { - /* Protocol Error in Arbitration Phase */ - - if ((psr & FDCAN_PSR_LEC_MASK) != 0) - { - /* Error code present */ - - if ((psr & FDCAN_PSR_LEC(FDCAN_PSR_EC_STUFF_ERROR)) != 0) - { - /* Stuff Error */ - - errbits |= CAN_ERROR_PROTOCOL; - data[2] |= CAN_ERROR2_STUFF; - } - - if ((psr & FDCAN_PSR_LEC(FDCAN_PSR_EC_FORM_ERROR)) != 0) - { - /* Format Error */ - - errbits |= CAN_ERROR_PROTOCOL; - data[2] |= CAN_ERROR2_FORM; - } - - if ((psr & FDCAN_PSR_LEC(FDCAN_PSR_EC_ACK_ERROR)) != 0) - { - /* Acknowledge Error */ - - errbits |= CAN_ERROR_NOACK; - } - - if ((psr & FDCAN_PSR_LEC(FDCAN_PSR_EC_BIT0_ERROR)) != 0) - { - /* Bit0 Error */ - - errbits |= CAN_ERROR_PROTOCOL; - data[2] |= CAN_ERROR2_BIT0; - } - - if ((psr & FDCAN_PSR_LEC(FDCAN_PSR_EC_BIT1_ERROR)) != 0) - { - /* Bit1 Error */ - - errbits |= CAN_ERROR_PROTOCOL; - data[2] |= CAN_ERROR2_BIT1; - } - - if ((psr & FDCAN_PSR_LEC(FDCAN_PSR_EC_CRC_ERROR)) != 0) - { - /* Receive CRC Error */ - - errbits |= CAN_ERROR_PROTOCOL; - data[3] |= (CAN_ERROR3_CRCSEQ | CAN_ERROR3_CRCDEL); - } - - if ((psr & FDCAN_PSR_LEC(FDCAN_PSR_EC_NO_CHANGE)) != 0) - { - /* No Change in Error */ - - errbits |= CAN_ERROR_PROTOCOL; - data[2] |= CAN_ERROR2_UNSPEC; - } - } - } - - if ((status & FDCAN_INT_PED) != 0) - { - /* Protocol Error in Data Phase */ - - if ((psr & FDCAN_PSR_DLEC_MASK) != 0) - { - /* Error code present */ - - if ((psr & FDCAN_PSR_DLEC(FDCAN_PSR_EC_STUFF_ERROR)) != 0) - { - /* Stuff Error */ - - errbits |= CAN_ERROR_PROTOCOL; - data[2] |= CAN_ERROR2_STUFF; - } - - if ((psr & FDCAN_PSR_DLEC(FDCAN_PSR_EC_FORM_ERROR)) != 0) - { - /* Format Error */ - - errbits |= CAN_ERROR_PROTOCOL; - data[2] |= CAN_ERROR2_FORM; - } - - if ((psr & FDCAN_PSR_DLEC(FDCAN_PSR_EC_ACK_ERROR)) != 0) - { - /* Acknowledge Error */ - - errbits |= CAN_ERROR_NOACK; - } - - if ((psr & FDCAN_PSR_DLEC(FDCAN_PSR_EC_BIT0_ERROR)) != 0) - { - /* Bit0 Error */ - - errbits |= CAN_ERROR_PROTOCOL; - data[2] |= CAN_ERROR2_BIT0; - } - - if ((psr & FDCAN_PSR_DLEC(FDCAN_PSR_EC_BIT1_ERROR)) != 0) - { - /* Bit1 Error */ - - errbits |= CAN_ERROR_PROTOCOL; - data[2] |= CAN_ERROR2_BIT1; - } - - if ((psr & FDCAN_PSR_DLEC(FDCAN_PSR_EC_CRC_ERROR)) != 0) - { - /* Receive CRC Error */ - - errbits |= CAN_ERROR_PROTOCOL; - data[3] |= (CAN_ERROR3_CRCSEQ | CAN_ERROR3_CRCDEL); - } - - if ((psr & FDCAN_PSR_DLEC(FDCAN_PSR_EC_NO_CHANGE)) != 0) - { - /* No Change in Error */ - - errbits |= CAN_ERROR_PROTOCOL; - data[2] |= CAN_ERROR2_UNSPEC; - } - } - } - - if ((status & FDCAN_INT_BO) != 0) - { - /* Bus_Off Status changed */ - - if ((psr & FDCAN_PSR_BO) != 0) - { - errbits |= CAN_ERROR_BUSOFF; - } - else - { - errbits |= CAN_ERROR_RESTARTED; - } - } - - if ((status & (FDCAN_INT_RF0L | FDCAN_INT_RF1L)) != 0) - { - /* Receive FIFO 0/1 Message Lost - * Receive FIFO 1 Message Lost - */ - - errbits |= CAN_ERROR_CONTROLLER; - data[1] |= CAN_ERROR1_RXOVERFLOW; - } - - if ((status & FDCAN_INT_TEFL) != 0) - { - /* Tx Event FIFO Element Lost */ - - errbits |= CAN_ERROR_CONTROLLER; - data[1] |= CAN_ERROR1_TXOVERFLOW; - } - - if ((status & FDCAN_INT_TOO) != 0) - { - /* Timeout Occurred */ - - errbits |= CAN_ERROR_TXTIMEOUT; - } - - if ((status & (FDCAN_INT_MRAF | FDCAN_INT_ELO)) != 0) - { - /* Message RAM Access Failure - * Error Logging Overflow - */ - - errbits |= CAN_ERROR_CONTROLLER; - data[1] |= CAN_ERROR1_UNSPEC; - } - - if (errbits != 0) - { - /* Format the CAN header for the error report. */ - - hdr.ch_id = errbits; - hdr.ch_dlc = CAN_ERROR_DLC; - hdr.ch_rtr = 0; - hdr.ch_error = 1; -#ifdef CONFIG_CAN_EXTID - hdr.ch_extid = 0; -#endif - hdr.ch_tcf = 0; - - /* And provide the error report to the upper half logic */ - - ret = can_receive(dev, &hdr, data); - if (ret < 0) - { - canerr("ERROR: can_receive failed: %d\n", ret); - } - } -} -#endif /* CONFIG_CAN_ERRORS */ - -/**************************************************************************** - * Name: fdcan_receive - * - * Description: - * Receive an FDCAN messages - * - * Input Parameters: - * dev - CAN-common state data - * rxbuffer - The RX buffer containing the received messages - * nwords - The length of the RX buffer (element size in words). - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void fdcan_receive(struct can_dev_s *dev, - volatile uint32_t *rxbuffer, - unsigned long nwords) -{ - struct can_hdr_s hdr; - int ret = 0; - - fdcan_dumprxregs(dev->cd_priv, "Before receive"); - - /* Format the CAN header */ - - /* Word R0 contains the CAN ID */ - -#ifdef CONFIG_CAN_ERRORS - hdr.ch_error = 0; -#endif - hdr.ch_tcf = 0; - - /* Extract the RTR bit */ - - hdr.ch_rtr = ((rxbuffer[0] & BUFFER_R0_RTR) != 0); - -#ifdef CONFIG_CAN_EXTID - if ((rxbuffer[0] & BUFFER_R0_XTD) != 0) - { - /* Save the extended ID of the newly received message */ - - hdr.ch_id = (rxbuffer[0] & BUFFER_R0_EXTID_MASK) >> - BUFFER_R0_EXTID_SHIFT; - hdr.ch_extid = 1; - } - else - { - hdr.ch_id = (rxbuffer[0] & BUFFER_R0_STDID_MASK) >> - BUFFER_R0_STDID_SHIFT; - hdr.ch_extid = 0; - } - -#else - if ((rxbuffer[0] & BUFFER_R0_XTD) != 0) - { - /* Drop any messages with extended IDs */ - - canerr("ERROR: Received message with extended identifier. Dropped\n"); - - return; - } - - /* Save the standard ID of the newly received message */ - - hdr.ch_id = (rxbuffer[0] & BUFFER_R0_STDID_MASK) >> BUFFER_R0_STDID_SHIFT; -#endif - - /* Word R1 contains the DLC and timestamp */ - - hdr.ch_dlc = (rxbuffer[1] & BUFFER_R1_DLC_MASK) >> BUFFER_R1_DLC_SHIFT; - -#ifdef CONFIG_CAN_FD - /* CAN FD format */ - - hdr.ch_esi = ((rxbuffer[0] & BUFFER_R0_ESI) != 0); - hdr.ch_edl = ((rxbuffer[1] & BUFFER_R1_FDF) != 0); - hdr.ch_brs = ((rxbuffer[1] & BUFFER_R1_BRS) != 0); -#else - if ((rxbuffer[1] & BUFFER_R1_FDF) != 0) - { - /* Drop any FD CAN messages if not supported */ - - canerr("ERROR: Received CAN FD message. Dropped\n"); - - return; - } -#endif - - /* And provide the CAN message to the upper half logic */ - - ret = can_receive(dev, &hdr, (uint8_t *)&rxbuffer[2]); - if (ret < 0) - { - canerr("ERROR: can_receive failed: %d\n", ret); - } -} - -/**************************************************************************** - * Name: fdcan_interrupt - * - * Description: - * Common FDCAN interrupt handler - * - * Input Parameters: - * dev - CAN-common state data - * - * Returned Value: - * None - * - ****************************************************************************/ - -static int fdcan_interrupt(int irq, void *context, void *arg) -{ - struct can_dev_s *dev = (struct can_dev_s *)arg; - struct stm32_fdcan_s *priv = NULL; - const struct stm32_config_s *config = NULL; - uint32_t ir = 0; - uint32_t ie = 0; - uint32_t pending = 0; - uint32_t regval = 0; - uint32_t psr = 0; - unsigned int nelem = 0; - unsigned int ndx = 0; - - DEBUGASSERT(dev != NULL); - priv = dev->cd_priv; - DEBUGASSERT(priv && priv->config); - config = priv->config; - - /* Get the set of pending interrupts. */ - - ir = fdcan_getreg(priv, STM32_FDCAN_IR_OFFSET); - ie = fdcan_getreg(priv, STM32_FDCAN_IE_OFFSET); - - pending = (ir & ie); - - /* Check for any errors */ - - if ((pending & FDCAN_ANYERR_INTS) != 0) - { - /* Check for common errors */ - - if ((pending & FDCAN_CMNERR_INTS) != 0) - { - canerr("ERROR: Common %08" PRIx32 "\n", - pending & FDCAN_CMNERR_INTS); - - /* When a protocol error occurs, the problem is recorded in - * the LEC/DLEC fields of the PSR register. In lieu of - * separate interrupt flags for each error, the hardware - * groups protocol errors under a single interrupt each for - * arbitration and data phases. - * - * These errors have a tendency to flood the system with - * interrupts, so they are disabled here until we get a - * successful transfer/receive on the hardware - */ - - psr = fdcan_getreg(priv, STM32_FDCAN_PSR_OFFSET); - - if ((psr & FDCAN_PSR_LEC_MASK) != 0) - { - canerr("ERROR: PSR %08" PRIx32 "\n", psr); - ie &= ~(FDCAN_INT_PEA | FDCAN_INT_PED); - fdcan_putreg(priv, STM32_FDCAN_IE_OFFSET, ie); - caninfo("disabled protocol error interrupts\n"); - } - - /* Clear the error indications */ - - fdcan_putreg(priv, STM32_FDCAN_IR_OFFSET, FDCAN_CMNERR_INTS); - } - - /* Check for transmission errors */ - - if ((pending & FDCAN_TXERR_INTS) != 0) - { - canerr("ERROR: TX %08" PRIx32 "\n", - pending & FDCAN_TXERR_INTS); - - /* An Acknowledge-Error will occur if for example the device - * is not connected to the bus. - * - * The CAN-Standard states that the Chip has to retry the - * message forever, which will produce an ACKE every time. - * To prevent this Interrupt-Flooding and the high CPU-Load - * we disable the ACKE here as long we didn't transfer at - * least one message successfully (see FDCAN_INT_TC below). - */ - - /* Clear the error indications */ - - fdcan_putreg(priv, STM32_FDCAN_IR_OFFSET, FDCAN_TXERR_INTS); - } - - /* Check for reception errors */ - - if ((pending & FDCAN_RXERR_INTS) != 0) - { - canerr("ERROR: RX %08" PRIx32 "\n", - pending & FDCAN_RXERR_INTS); - - /* To prevent Interrupt-Flooding the current active - * RX error interrupts are disabled. After successfully - * receiving at least one CAN packet all RX error interrupts - * are turned back on. - * - * The Interrupt-Flooding can for example occur if the - * configured CAN speed does not match the speed of the other - * CAN nodes in the network. - */ - - ie &= ~(pending & FDCAN_RXERR_INTS); - fdcan_putreg(priv, STM32_FDCAN_IE_OFFSET, ie); - - /* Clear the error indications */ - - fdcan_putreg(priv, STM32_FDCAN_IR_OFFSET, FDCAN_RXERR_INTS); - } - -#ifdef CONFIG_CAN_ERRORS - /* Report errors */ - - fdcan_error(dev, pending & FDCAN_ANYERR_INTS); -#endif - } - - /* Check for successful completion of a transmission */ - - if ((pending & FDCAN_INT_TC) != 0) - { - /* Check if we have disabled the ACKE in the error-handling above - * (see FDCAN_TXERR_INTS) to prevent Interrupt-Flooding and - * re-enable the error interrupt here again. - */ - - if ((ie & (FDCAN_INT_PEA | FDCAN_INT_PED)) == 0) - { - ie |= (FDCAN_INT_PEA | FDCAN_INT_PED); - fdcan_putreg(priv, STM32_FDCAN_IE_OFFSET, ie); - caninfo("Re-enabled protocol error interrupts\n"); - } - - /* Clear the pending TX completion interrupt (and all - * other TX-related interrupts) - */ - - fdcan_putreg(priv, STM32_FDCAN_IR_OFFSET, priv->txints); - - /* Check all TX buffers */ - - regval = fdcan_getreg(priv, STM32_FDCAN_TXBTO_OFFSET); - for (ndx = 0; ndx < config->ntxfifoq; ndx++) - { - if ((regval & (1 << ndx)) != 0) - { - /* Tell the upper half that the transfer is finished. */ - - can_txdone(dev); - } - } - } - else if ((pending & priv->txints) != 0) - { - /* Clear unhandled TX events */ - - fdcan_putreg(priv, STM32_FDCAN_IR_OFFSET, priv->txints); - } - - /* Clear the RX FIFO1 new message interrupt */ - - fdcan_putreg(priv, STM32_FDCAN_IR_OFFSET, FDCAN_INT_RF1N); - pending &= ~FDCAN_INT_RF1N; - - /* We treat RX FIFO1 as the "high priority" queue: We will process - * all messages in RX FIFO1 before processing any message from RX - * FIFO0. - */ - - for (; ; ) - { - /* Check if there is anything in RX FIFO1 */ - - regval = fdcan_getreg(priv, STM32_FDCAN_RXF1S_OFFSET); - nelem = (regval & FDCAN_RXFS_FFL_MASK) >> FDCAN_RXFS_FFL_SHIFT; - if (nelem == 0) - { - /* Break out of the loop if RX FIFO1 is empty */ - - break; - } - - /* Clear the RX FIFO1 interrupt (and all other FIFO1-related - * interrupts) - */ - - /* Handle the newly received message in FIFO1 */ - - ndx = (regval & FDCAN_RXFS_FGI_MASK) >> FDCAN_RXFS_FGI_SHIFT; - - if ((regval & FDCAN_RXFS_RFL) != 0) - { - canerr("ERROR: Message lost: %08" PRIx32 "\n", regval); - } - else - { - fdcan_receive(dev, - config->msgram.rxfifo1 + - (ndx * priv->config->rxfifo1esize), - priv->config->rxfifo1esize); - - /* Turning back on all configured RX error interrupts */ - - ie |= (priv->rxints & FDCAN_RXERR_INTS); - fdcan_putreg(priv, STM32_FDCAN_IE_OFFSET, ie); - } - - /* Acknowledge reading the FIFO entry */ - - fdcan_putreg(priv, STM32_FDCAN_RXF1A_OFFSET, ndx); - } - - /* Check for successful reception of a new message in RX FIFO0 */ - - /* Clear the RX FIFO0 new message interrupt */ - - fdcan_putreg(priv, STM32_FDCAN_IR_OFFSET, FDCAN_INT_RF0N); - pending &= ~FDCAN_INT_RF0N; - - /* Check if there is anything in RX FIFO0 */ - - regval = fdcan_getreg(priv, STM32_FDCAN_RXF0S_OFFSET); - nelem = (regval & FDCAN_RXFS_FFL_MASK) >> FDCAN_RXFS_FFL_SHIFT; - if (nelem > 0) - { - /* Handle the newly received message in FIFO0 */ - - ndx = (regval & FDCAN_RXFS_FGI_MASK) >> FDCAN_RXFS_FGI_SHIFT; - - if ((regval & FDCAN_RXFS_RFL) != 0) - { - canerr("ERROR: Message lost: %08" PRIx32 "\n", regval); - } - else - { - fdcan_receive(dev, - config->msgram.rxfifo0 + - (ndx * priv->config->rxfifo0esize), - priv->config->rxfifo0esize); - - /* Turning back on all configured RX error interrupts */ - - ie |= (priv->rxints & FDCAN_RXERR_INTS); - fdcan_putreg(priv, STM32_FDCAN_IE_OFFSET, ie); - } - - /* Acknowledge reading the FIFO entry */ - - fdcan_putreg(priv, STM32_FDCAN_RXF0A_OFFSET, ndx); - } - - /* Clear unhandled RX interrupts */ - - if ((pending & priv->rxints) != 0) - { - fdcan_putreg(priv, STM32_FDCAN_IR_OFFSET, priv->rxints); - } - - return OK; -} - -/**************************************************************************** - * Name: fdcan_hw_initialize - * - * Description: - * FDCAN hardware initialization - * - * Input Parameters: - * priv - A pointer to the private data structure for this FDCAN peripheral - * - * Returned Value: - * Zero on success; a negated errno value on failure. - * - ****************************************************************************/ - -static int fdcan_hw_initialize(struct stm32_fdcan_s *priv) -{ - const struct stm32_config_s *config = priv->config; - volatile uint32_t *msgram = NULL; - uint32_t regval = 0; - uint32_t cntr = 0; - - caninfo("FDCAN%d\n", config->port); - - /* Clean message RAM */ - - msgram = config->msgram.stdfilters; - cntr = (FDCAN_MSGRAM_WORDS + 1); - while (cntr > 0) - { - *msgram++ = 0; - cntr--; - } - - /* Configure FDCAN pins */ - - stm32_configgpio(config->rxpinset); - stm32_configgpio(config->txpinset); - - /* Re-enabled device if previously disabled in fdcan_shutdown() */ - - if (priv->state == FDCAN_STATE_DISABLED) - { - /* Reset Clock Stop Request bit */ - - regval = fdcan_getreg(priv, STM32_FDCAN_CCCR_OFFSET); - regval &= ~FDCAN_CCCR_CSR; - fdcan_putreg(priv, STM32_FDCAN_CCCR_OFFSET, regval); - - /* Wait for Clock Stop Acknowledge bit reset to indicate - * device is operational - */ - - while ((fdcan_getreg(priv, STM32_FDCAN_CCCR_OFFSET) & FDCAN_CCCR_CSA) - != 0); - } - - /* Enable the Initialization state */ - - regval = fdcan_getreg(priv, STM32_FDCAN_CCCR_OFFSET); - regval |= FDCAN_CCCR_INIT; - fdcan_putreg(priv, STM32_FDCAN_CCCR_OFFSET, regval); - - /* Wait for initialization mode to take effect */ - - while ((fdcan_getreg(priv, STM32_FDCAN_CCCR_OFFSET) & FDCAN_CCCR_INIT) - == 0); - - /* Enable writing to configuration registers */ - - regval = fdcan_getreg(priv, STM32_FDCAN_CCCR_OFFSET); - regval |= FDCAN_CCCR_CCE; - fdcan_putreg(priv, STM32_FDCAN_CCCR_OFFSET, regval); - - /* Global Filter Configuration: - * - * ANFS=0: Store all non matching standard frame in RX FIFO0 - * ANFE=0: Store all non matching extended frame in RX FIFO0 - */ - - regval = FDCAN_RXGFC_ANFE_RX_FIFO0 | FDCAN_RXGFC_ANFS_RX_FIFO0; - fdcan_putreg(priv, STM32_FDCAN_RXGFC_OFFSET, regval); - - /* Extended ID Filter AND mask */ - - fdcan_putreg(priv, STM32_FDCAN_XIDAM_OFFSET, 0x1fffffff); - - /* Disable all interrupts */ - - fdcan_putreg(priv, STM32_FDCAN_IE_OFFSET, 0); - fdcan_putreg(priv, STM32_FDCAN_TXBTIE_OFFSET, 0); - - /* All interrupts directed to Line 0. But disable both interrupt lines 0 - * and 1 for now. - * - * REVISIT: Only interrupt line 0 is used by this driver. - */ - - fdcan_putreg(priv, STM32_FDCAN_ILS_OFFSET, 0); - fdcan_putreg(priv, STM32_FDCAN_ILE_OFFSET, 0); - - /* Clear all pending interrupts. */ - - fdcan_putreg(priv, STM32_FDCAN_IR_OFFSET, FDCAN_INT_ALL); - - /* Configure FDCAN bit timing */ - - fdcan_putreg(priv, STM32_FDCAN_NBTP_OFFSET, priv->nbtp); - fdcan_putreg(priv, STM32_FDCAN_DBTP_OFFSET, priv->dbtp); - - /* Configure message RAM starting addresses and sizes. */ - - regval = FDCAN_RXGFC_LSS(config->nstdfilters); - regval |= FDCAN_RXGFC_LSE(config->nextfilters); - fdcan_putreg(priv, STM32_FDCAN_RXGFC_OFFSET, regval); - - /* Dump RAM layout */ - - fdcan_dumpramlayout(priv); - - /* Configure Message Filters */ - - /* Disable all standard filters */ - - msgram = config->msgram.stdfilters; - cntr = config->nstdfilters; - while (cntr > 0) - { - *msgram++ = STDFILTER_S0_SFEC_DISABLE; - cntr--; - } - - /* Disable all extended filters */ - - msgram = config->msgram.extfilters; - cntr = config->nextfilters; - while (cntr > 0) - { - *msgram = EXTFILTER_F0_EFEC_DISABLE; - msgram = msgram + 2; - cntr--; - } - - /* Input clock divider configuration */ - - regval = FDCANCLK_PDIV; - fdcan_putreg(priv, STM32_FDCAN_CKDIV_OFFSET, regval); - - /* CC control register */ - - regval = fdcan_getreg(priv, STM32_FDCAN_CCCR_OFFSET); - regval &= ~(FDCAN_CCCR_NISO | FDCAN_CCCR_FDOE | FDCAN_CCCR_BRSE); - - /* Select ISO11898-1 or Non ISO Bosch CAN FD Specification V1.0 */ - - switch (config->format) - { - case FDCAN_ISO11898_1_FORMAT: - { - break; - } - - case FDCAN_NONISO_BOSCH_V1_FORMAT: - { - regval |= FDCAN_CCCR_NISO; - break; - } - - default: - { - return -EINVAL; - } - } - - /* Select Classic CAN mode or FD mode with or without fast bit rate - * switching - */ - - switch (config->mode) - { - case FDCAN_CLASSIC_MODE: - { - break; - } - -#ifdef CONFIG_CAN_FD - case FDCAN_FD_MODE: - { - regval |= FDCAN_CCCR_FDOE; - break; - } - - case FDCAN_FD_BRS_MODE: - { - regval |= (FDCAN_CCCR_FDOE | FDCAN_CCCR_BRSE); - break; - } -#endif - - default: - { - return -EINVAL; - } - } - - /* Set the initial CAN mode */ - - fdcan_putreg(priv, STM32_FDCAN_CCCR_OFFSET, regval); - - /* Enable FIFO/Queue mode */ - - regval = fdcan_getreg(priv, STM32_FDCAN_TXBC_OFFSET); -#ifdef CONFIG_STM32F0L0G0_FDCAN_QUEUE_MODE - regval |= FDCAN_TXBC_TFQM; -#else - regval &= ~FDCAN_TXBC_TFQM; -#endif - fdcan_putreg(priv, STM32_FDCAN_TXBC_OFFSET, regval); - -#ifdef STM32_FDCAN_LOOPBACK - /* Is loopback mode selected for this peripheral? */ - - if (config->loopback) - { - /* FDCAN_CCCR_TEST - Test mode enable - * FDCAN_CCCR_MON - Bus monitoring mode (for internal loopback) - * FDCAN_TEST_LBCK - Loopback mode - */ - - regval = fdcan_getreg(priv, STM32_FDCAN_CCCR_OFFSET); - regval |= (FDCAN_CCCR_TEST | FDCAN_CCCR_MON); - fdcan_putreg(priv, STM32_FDCAN_CCCR_OFFSET, regval); - - regval = fdcan_getreg(priv, STM32_FDCAN_TEST_OFFSET); - regval |= FDCAN_TEST_LBCK; - fdcan_putreg(priv, STM32_FDCAN_TEST_OFFSET, regval); - } -#endif - - /* Configure interrupt lines */ - - /* Select RX-related interrupts */ - - priv->rxints = FDCAN_RXFIFO_INTS; - - /* Select TX-related interrupts */ - - priv->txints = FDCAN_TXFIFOQ_INTS; - - /* Direct all interrupts to Line 0. - * - * Bits in the ILS register correspond to each FDCAN interrupt; A bit - * set to '1' is directed to interrupt line 1; a bit cleared to '0' - * is directed interrupt line 0. - * - * REVISIT: Nothing is done here. Only interrupt line 0 is used by - * this driver and ILS was already cleared above. - */ - - /* Enable only interrupt line 0. */ - - fdcan_putreg(priv, STM32_FDCAN_ILE_OFFSET, FDCAN_ILE_EINT0); - - /* Disable initialization mode to enable normal operation */ - - regval = fdcan_getreg(priv, STM32_FDCAN_CCCR_OFFSET); - regval &= ~FDCAN_CCCR_INIT; - fdcan_putreg(priv, STM32_FDCAN_CCCR_OFFSET, regval); - - return OK; -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_fdcaninitialize - * - * Description: - * Initialize the selected FDCAN port - * - * Input Parameters: - * port - Port number (for hardware that has multiple FDCAN interfaces), - * 1=FDCAN1. - * - * Returned Value: - * Valid CAN device structure reference on success; a NULL on failure - * - ****************************************************************************/ - -struct can_dev_s *stm32_fdcaninitialize(int port) -{ - struct can_dev_s *dev = NULL; - struct stm32_fdcan_s *priv = NULL; - const struct stm32_config_s *config = NULL; - - caninfo("FDCAN%d\n", port); - - /* Select FDCAN peripheral to be initialized */ - -#ifdef CONFIG_STM32F0L0G0_FDCAN1 - if (port == FDCAN1) - { - /* Select the FDCAN1 device structure */ - - dev = &g_fdcan1dev; - priv = &g_fdcan1priv; - config = &g_fdcan1const; - } - else -#endif - { - canerr("ERROR: Unsupported port %d\n", port); - return NULL; - } - - /* Perform one time data initialization */ - - memset(priv, 0, sizeof(struct stm32_fdcan_s)); - priv->config = config; - - /* Set the initial bit timing. This might change subsequently - * due to IOCTL command processing. - */ - - priv->nbtp = config->nbtp; - priv->dbtp = config->dbtp; - - dev->cd_ops = &g_fdcanops; - dev->cd_priv = (void *)priv; - - /* And put the hardware in the initial state */ - - fdcan_reset(dev); - - return dev; -} diff --git a/arch/arm/src/stm32f0l0g0/stm32_fdcan.h b/arch/arm/src/stm32f0l0g0/stm32_fdcan.h deleted file mode 100644 index b96772738a2c1..0000000000000 --- a/arch/arm/src/stm32f0l0g0/stm32_fdcan.h +++ /dev/null @@ -1,112 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_fdcan.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_STM32_FDCAN_H -#define __ARCH_ARM_SRC_STM32F0L0G0_STM32_FDCAN_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "chip.h" -#include "hardware/stm32_fdcan.h" - -#include - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Port numbers for use with stm32_fdcan_initialize() */ - -#define FDCAN1 1 - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -#ifndef __ASSEMBLY__ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -#ifdef CONFIG_STM32F0L0G0_FDCAN_CHARDRIVER - -/**************************************************************************** - * Name: stm32_fdcaninitialize - * - * Description: - * Initialize the selected FDCAN port - * - * Input Parameters: - * Port number (for hardware that has multiple FDCAN interfaces) - * - * Returned Value: - * Valid FDCAN device structure reference on success; a NULL on failure - * - ****************************************************************************/ - -struct can_dev_s *stm32_fdcaninitialize(int port); -#endif - -#ifdef CONFIG_STM32F0L0G0_FDCAN_SOCKET - -/**************************************************************************** - * Name: stm32_fdcansockinitialize - * - * Description: - * Initialize the selected FDCAN port as SocketCAN interface - * - * Input Parameters: - * Port number (for hardware that has multiple FDCAN interfaces) - * - * Returned Value: - * OK on success; Negated errno on failure. - * - ****************************************************************************/ - -int stm32_fdcansockinitialize(int port); -#endif - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_STM32_FDCAN_H */ diff --git a/arch/arm/src/stm32f0l0g0/stm32_fdcan_sock.c b/arch/arm/src/stm32f0l0g0/stm32_fdcan_sock.c deleted file mode 100644 index 46464bec39533..0000000000000 --- a/arch/arm/src/stm32f0l0g0/stm32_fdcan_sock.c +++ /dev/null @@ -1,2991 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_fdcan_sock.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -#include -#include -#include - -#include "arm_internal.h" -#include "stm32_fdcan.h" -#include "hardware/stm32_pinmap.h" -#include "stm32_gpio.h" -#include "stm32_rcc.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Pool configuration *******************************************************/ - -#define POOL_SIZE (1) - -/* Work queue support is required. */ - -#if !defined(CONFIG_SCHED_WORKQUEUE) -# error Work queue support is required -#endif - -/* The low priority work queue is preferred. If it is not enabled, LPWORK - * will be the same as HPWORK. - * - * NOTE: However, the network should NEVER run on the high priority work - * queue! That queue is intended only to service short back end interrupt - * processing that never suspends. Suspending the high priority work queue - * may bring the system to its knees! - */ - -#define CANWORK LPWORK - -/* Clock source *************************************************************/ - -#define FDCANCLK_PDIV (0) - -#if FDCANCLK_PDIV == 0 -# define STM32_FDCANCLK_FREQUENCY (STM32_FDCAN_FREQUENCY / (1)) -#else -# define STM32_FDCANCLK_FREQUENCY (STM32_FDCAN_FREQUENCY / (2 * FDCANCLK_PDIV)) -#endif - -/* General Configuration ****************************************************/ - -#if defined(CONFIG_ARCH_CHIP_STM32C0) - -/* FDCAN Message RAM */ - -# define FDCAN_MSGRAM_WORDS (212) -# define STM32_CANRAM1_BASE (STM32_CANRAM_BASE + 0x0000) - -# ifdef CONFIG_STM32F0L0G0_FDCAN1 -# define FDCAN1_STDFILTER_SIZE (28) -# define FDCAN1_EXTFILTER_SIZE (8) -# define FDCAN1_RXFIFO0_SIZE (3) -# define FDCAN1_RXFIFO1_SIZE (3) -# define FDCAN1_TXEVENTFIFO_SIZE (3) -# define FDCAN1_TXFIFIOQ_SIZE (3) - -# define FDCAN1_STDFILTER_WORDS (28) -# define FDCAN1_EXTFILTER_WORDS (16) -# define FDCAN1_RXFIFO0_WORDS (54) -# define FDCAN1_RXFIFO1_WORDS (54) -# define FDCAN1_TXEVENTFIFO_WORDS (6) -# define FDCAN1_TXFIFIOQ_WORDS (54) -# endif -#else -# error -#endif - -/* FDCAN1 Configuration *****************************************************/ - -#ifdef CONFIG_STM32F0L0G0_FDCAN1 - -/* Bit timing */ - -# define FDCAN1_NTSEG1 (CONFIG_STM32F0L0G0_FDCAN1_NTSEG1 - 1) -# define FDCAN1_NTSEG2 (CONFIG_STM32F0L0G0_FDCAN1_NTSEG2 - 1) -# define FDCAN1_NBRP ((STM32_FDCANCLK_FREQUENCY / \ - ((FDCAN1_NTSEG1 + FDCAN1_NTSEG2 + 3) * \ - CONFIG_STM32F0L0G0_FDCAN1_BITRATE)) - 1) -# define FDCAN1_NSJW (CONFIG_STM32F0L0G0_FDCAN1_NSJW - 1) - -# if FDCAN1_NTSEG1 > FDCAN_NBTP_NTSEG1_MAX -# error Invalid FDCAN1 NTSEG1 -# endif -# if FDCAN1_NTSEG2 > FDCAN_NBTP_NTSEG2_MAX -# error Invalid FDCAN1 NTSEG2 -# endif -# if FDCAN1_NSJW > FDCAN_NBTP_NSJW_MAX -# error Invalid FDCAN1 NSJW -# endif -# if FDCAN1_NBRP > FDCAN_NBTP_NBRP_MAX -# error Invalid FDCAN1 NBRP -# endif - -# ifdef CONFIG_STM32F0L0G0_FDCAN1_FD_BRS -# define FDCAN1_DTSEG1 (CONFIG_STM32F0L0G0_FDCAN1_DTSEG1 - 1) -# define FDCAN1_DTSEG2 (CONFIG_STM32F0L0G0_FDCAN1_DTSEG2 - 1) -# define FDCAN1_DBRP ((STM32_FDCANCLK_FREQUENCY / \ - ((FDCAN1_DTSEG1 + FDCAN1_DTSEG2 + 3) * \ - CONFIG_STM32F0L0G0_FDCAN1_DBITRATE)) - 1) -# define FDCAN1_DSJW (CONFIG_STM32F0L0G0_FDCAN1_DSJW - 1) -# else -# define FDCAN1_DTSEG1 1 -# define FDCAN1_DTSEG2 1 -# define FDCAN1_DBRP 1 -# define FDCAN1_DSJW 1 -# endif /* CONFIG_STM32F0L0G0_FDCAN1_FD_BRS */ - -# if FDCAN1_DTSEG1 > FDCAN_DBTP_DTSEG1_MAX -# error Invalid FDCAN1 DTSEG1 -# endif -# if FDCAN1_DTSEG2 > FDCAN_DBTP_DTSEG2_MAX -# error Invalid FDCAN1 DTSEG2 -# endif -# if FDCAN1_DBRP > FDCAN_DBTP_DBRP_MAX -# error Invalid FDCAN1 DBRP -# endif -# if FDCAN1_DSJW > FDCAN_DBTP_DSJW_MAX -# error Invalid FDCAN1 DSJW -# endif - -/* FDCAN1 Message RAM Configuration *****************************************/ - -/* FDCAN1 Message RAM Layout */ - -# define FDCAN1_STDFILTER_INDEX 0 -# define FDCAN1_EXTFILTERS_INDEX (FDCAN1_STDFILTER_INDEX + FDCAN1_STDFILTER_WORDS) -# define FDCAN1_RXFIFO0_INDEX (FDCAN1_EXTFILTERS_INDEX + FDCAN1_EXTFILTER_WORDS) -# define FDCAN1_RXFIFO1_INDEX (FDCAN1_RXFIFO0_INDEX + FDCAN1_RXFIFO0_WORDS) -# define FDCAN1_TXEVENTFIFO_INDEX (FDCAN1_RXFIFO1_INDEX + FDCAN1_RXFIFO1_WORDS) -# define FDCAN1_TXFIFOQ_INDEX (FDCAN1_TXEVENTFIFO_INDEX + FDCAN1_TXEVENTFIFO_WORDS) -# define FDCAN1_MSGRAM_WORDS (FDCAN1_TXFIFOQ_INDEX + FDCAN1_TXFIFIOQ_WORDS) - -#endif /* CONFIG_STM32F0L0G0_FDCAN1 */ - -/* Loopback mode */ - -#undef STM32_FDCAN_LOOPBACK -#if defined(CONFIG_STM32F0L0G0_FDCAN1_LOOPBACK) -# define STM32_FDCAN_LOOPBACK 1 -#endif - -/* Interrupts ***************************************************************/ - -/* Common interrupts - * - * FDCAN_INT_TSW - Timestamp Wraparound - * FDCAN_INT_MRAF - Message RAM Access Failure - * FDCAN_INT_TOO - Timeout Occurred - * FDCAN_INT_ELO - Error Logging Overflow - * FDCAN_INT_EP - Error Passive - * FDCAN_INT_EW - Warning Status - * FDCAN_INT_BO - Bus_Off Status - * FDCAN_INT_WDI - Watchdog Interrupt - * FDCAN_INT_PEA - Protocol Error in Arbritration Phase - * FDCAN_INT_PED - Protocol Error in Data Phase - */ - -#define FDCAN_CMNERR_INTS (FDCAN_INT_MRAF | FDCAN_INT_TOO | FDCAN_INT_EP | \ - FDCAN_INT_BO | FDCAN_INT_WDI | FDCAN_INT_PEA | \ - FDCAN_INT_PED) - -/* RXFIFO mode interrupts - * - * FDCAN_INT_RF0N - Receive FIFO 0 New Message - * FDCAN_INT_RF0F - Receive FIFO 0 Full - * FDCAN_INT_RF0L - Receive FIFO 0 Message Lost - * FDCAN_INT_RF1N - Receive FIFO 1 New Message - * FDCAN_INT_RF1F - Receive FIFO 1 Full - * FDCAN_INT_RF1L - Receive FIFO 1 Message Lost - * FDCAN_INT_HPM - High Priority Message Received - * - */ - -#define FDCAN_RXFIFO0_INTS (FDCAN_INT_RF0N | FDCAN_INT_RF0L) -#define FDCAN_RXFIFO1_INTS (FDCAN_INT_RF1N | FDCAN_INT_RF1L) - -#define FDCAN_RXERR_INTS (FDCAN_INT_RF0L | FDCAN_INT_RF1L) - -/* TX FIFOQ mode interrupts - * - * FDCAN_INT_TFE - Tx FIFO Empty - * - * TX Event FIFO interrupts - * - * FDCAN_INT_TEFN - Tx Event FIFO New Entry - * FDCAN_INT_TEFF - Tx Event FIFO Full - * FDCAN_INT_TEFL - Tx Event FIFO Element Lost - * - * Mode-independent TX-related interrupts - * - * FDCAN_INT_TC - Transmission Completed - * FDCAN_INT_TCF - Transmission Cancellation Finished - */ - -#define FDCAN_TXCOMMON_INTS (FDCAN_INT_TC | FDCAN_INT_TCF) -#define FDCAN_TXFIFOQ_INTS (FDCAN_INT_TFE | FDCAN_TXCOMMON_INTS) -#define FDCAN_TXEVFIFO_INTS (FDCAN_INT_TEFN | FDCAN_INT_TEFF | \ - FDCAN_INT_TEFL) - -#define FDCAN_TXERR_INTS (FDCAN_INT_TEFL | FDCAN_INT_PEA | FDCAN_INT_PED) - -/* Common-, TX- and RX-Error-Mask */ - -#define FDCAN_ANYERR_INTS (FDCAN_CMNERR_INTS | FDCAN_RXERR_INTS | FDCAN_TXERR_INTS) - -/* Convenience macro for clearing all interrupts */ - -#define FDCAN_INT_ALL 0x3fcfffff - -/* Debug ********************************************************************/ - -/* Debug configurations that may be enabled just for testing FDCAN */ - -#ifndef CONFIG_DEBUG_NET_INFO -# undef CONFIG_STM32F0L0G0_FDCAN_REGDEBUG -#endif - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/* CAN frame format */ - -enum stm32_frameformat_e -{ - FDCAN_ISO11898_1_FORMAT = 0, /* Frame format according to ISO11898-1 */ - FDCAN_NONISO_BOSCH_V1_FORMAT = 1 /* Frame format according to Bosch CAN FD V1.0 */ -}; - -/* CAN mode of operation */ - -enum stm32_canmode_e -{ - FDCAN_CLASSIC_MODE = 0, /* Classic CAN operation */ -#ifdef CONFIG_NET_CAN_CANFD - FDCAN_FD_MODE = 1, /* CAN FD operation */ - FDCAN_FD_BRS_MODE = 2 /* CAN FD operation with bit rate switching */ -#endif -}; - -/* CAN driver state */ - -enum can_state_s -{ - FDCAN_STATE_UNINIT = 0, /* Not yet initialized */ - FDCAN_STATE_RESET, /* Initialized, reset state */ - FDCAN_STATE_SETUP, /* fdcan_setup() has been called */ - FDCAN_STATE_DISABLED /* Disabled by a fdcan_shutdown() */ -}; - -/* This structure describes the FDCAN message RAM layout */ - -struct stm32_msgram_s -{ - volatile uint32_t *stdfilters; /* Standard filters */ - volatile uint32_t *extfilters; /* Extended filters */ - volatile uint32_t *rxfifo0; /* RX FIFO0 */ - volatile uint32_t *rxfifo1; /* RX FIFO1 */ - volatile uint32_t *txeventfifo; /* TX event FIFO */ - volatile uint32_t *txfifoq; /* TX FIFO queue */ -}; - -/* This structure provides the constant configuration of a FDCAN peripheral */ - -struct stm32_config_s -{ - uint32_t rxpinset; /* RX pin configuration */ - uint32_t txpinset; /* TX pin configuration */ - uintptr_t base; /* Base address of the FDCAN registers */ - uint32_t baud; /* Configured baud */ - uint32_t nbtp; /* Nominal bit timing/prescaler register setting */ - uint32_t dbtp; /* Data bit timing/prescaler register setting */ - uint8_t port; /* FDCAN port number (1 or 2) */ - uint8_t irq0; /* FDCAN peripheral IRQ number for interrupt line 0 */ - uint8_t irq1; /* FDCAN peripheral IRQ number for interrupt line 1 */ - uint8_t mode; /* See enum stm32_canmode_e */ - uint8_t format; /* See enum stm32_frameformat_e */ - uint8_t nstdfilters; /* Number of standard filters */ - uint8_t nextfilters; /* Number of extended filters */ - uint8_t nrxfifo0; /* Number of RX FIFO0 elements */ - uint8_t nrxfifo1; /* Number of RX FIFO1 elements */ - uint8_t ntxeventfifo; /* Number of TXevent FIFO elements */ - uint8_t ntxfifoq; /* Number of TX FIFO queue elements */ - uint8_t rxfifo0esize; /* RX FIFO0 element size (words) */ - uint8_t rxfifo1esize; /* RX FIFO1 element size (words) */ - uint8_t txeventesize; /* TXevent element size (words) */ - uint8_t txbufferesize; /* TX buffer element size (words) */ -#ifdef STM32_FDCAN_LOOPBACK - bool loopback; /* True: Loopback mode */ -#endif - - /* FDCAN message RAM layout */ - - struct stm32_msgram_s msgram; -}; - -/* This structure provides the current state of a FDCAN peripheral */ - -struct stm32_fdcan_s -{ - /* The constant configuration */ - - const struct stm32_config_s *config; - - uint8_t state; /* See enum can_state_s */ -#ifdef CONFIG_NET_CAN_EXTID - uint8_t nextalloc; /* Number of allocated extended filters */ -#endif - uint8_t nstdalloc; /* Number of allocated standard filters */ - uint32_t nbtp; /* Current nominal bit timing */ - uint32_t dbtp; /* Current data bit timing */ - -#ifdef CONFIG_NET_CAN_EXTID - uint32_t extfilters[2]; /* Extended filter bit allocator. 2*32=64 */ -#endif - uint32_t stdfilters[4]; /* Standard filter bit allocator. 4*32=128 */ - -#ifdef CONFIG_STM32F0L0G0_FDCAN_REGDEBUG - uintptr_t regaddr; /* Last register address read */ - uint32_t regval; /* Last value read from the register */ - unsigned int count; /* Number of times that the value was read */ -#endif - - bool bifup; /* true:ifup false:ifdown */ - struct net_driver_s dev; /* Interface understood by the network */ - - struct work_s irqwork; /* For deferring interrupt work to the wq */ - struct work_s pollwork; /* For deferring poll work to the work wq */ - - /* A pointers to the list of TX/RX descriptors */ - - struct can_frame *txdesc; - struct can_frame *rxdesc; - - /* TX/RX pool */ - -#ifdef CONFIG_NET_CAN_CANFD - uint8_t tx_pool[sizeof(struct canfd_frame)*POOL_SIZE]; - uint8_t rx_pool[sizeof(struct canfd_frame)*POOL_SIZE]; -#else - uint8_t tx_pool[sizeof(struct can_frame)*POOL_SIZE]; - uint8_t rx_pool[sizeof(struct can_frame)*POOL_SIZE]; -#endif -}; - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -/* FDCAN Register access */ - -static uint32_t fdcan_getreg(struct stm32_fdcan_s *priv, int offset); -static void fdcan_putreg(struct stm32_fdcan_s *priv, int offset, - uint32_t regval); -#ifdef CONFIG_STM32F0L0G0_FDCAN_REGDEBUG -static void fdcan_dumpregs(struct stm32_fdcan_s *priv, - const char *msg); -static void fdcan_dumprxregs(struct stm32_fdcan_s *priv, - const char *msg); -static void fdcan_dumptxregs(struct stm32_fdcan_s *priv, - const char *msg); -static void fdcan_dumpramlayout(struct stm32_fdcan_s *priv); -#else -# define fdcan_dumpregs(priv,msg) -# define fdcan_dumprxregs(priv,msg) -# define fdcan_dumptxregs(priv,msg) -# define fdcan_dumpramlayout(priv) -#endif - -/* CAN interrupt enable functions */ - -static void fdcan_rx0int(struct stm32_fdcan_s *priv, bool enable); -static void fdcan_rx1int(struct stm32_fdcan_s *priv, bool enable); -static void fdcan_txint(struct stm32_fdcan_s *priv, bool enable); -#ifdef CONFIG_NET_CAN_ERRORS -static void fdcan_errint(struct stm32_fdcan_s *priv, bool enable); -#endif - -/* Common TX logic */ - -static int fdcan_send(struct stm32_fdcan_s *priv); -static bool fdcan_txready(struct stm32_fdcan_s *priv); -static int fdcan_txpoll(struct net_driver_s *dev); - -/* CAN RX interrupt handling */ - -static void fdcan_rx0interrupt_work(void *arg); -static void fdcan_rx1interrupt_work(void *arg); - -/* CAN TX interrupt handling */ - -static void fdcan_txdone_work(void *arg); -static void fdcan_txdone(struct stm32_fdcan_s *priv); - -#ifdef CONFIG_NET_CAN_ERRORS -/* CAN errors interrupt handling */ - -static void fdcan_error_work(void *arg); -#endif - -/* FDCAN interrupt handling */ - -#ifdef CONFIG_NET_CAN_ERRORS -static void fdcan_error(struct stm32_fdcan_s *priv, uint32_t status); -#endif -static void fdcan_receive(struct stm32_fdcan_s *priv, - volatile uint32_t *rxbuffer, - unsigned long nwords); -static int fdcan_interrupt(int irq, void *context, void *arg); - -/* Initialization */ - -static void fdcan_reset(struct stm32_fdcan_s *priv); -static int fdcan_setup(struct stm32_fdcan_s *priv); -static void fdcan_shutdown(struct stm32_fdcan_s *priv); - -/* FDCAN helpers */ - -#if 0 /* not used for now */ -static int -fdcan_start_busoff_recovery_sequence(struct stm32_fdcan_s *priv); -#endif - -/* Hardware initialization */ - -static int fdcan_hw_initialize(struct stm32_fdcan_s *priv); - -/* NuttX callback functions */ - -static int fdcan_ifup(struct net_driver_s *dev); -static int fdcan_ifdown(struct net_driver_s *dev); - -static void fdcan_txavail_work(void *arg); -static int fdcan_txavail(struct net_driver_s *dev); - -#ifdef CONFIG_NETDEV_IOCTL -static int fdcan_netdev_ioctl(struct net_driver_s *dev, int cmd, - unsigned long arg); -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -#ifdef CONFIG_STM32F0L0G0_FDCAN1 -/* Message RAM allocation */ - -/* Constant configuration */ - -static const struct stm32_config_s g_fdcan1const = -{ - .rxpinset = GPIO_FDCAN1_RX, - .txpinset = GPIO_FDCAN1_TX, - .base = STM32_FDCAN1_BASE, - .baud = CONFIG_STM32F0L0G0_FDCAN1_BITRATE, - .nbtp = FDCAN_NBTP_NBRP(FDCAN1_NBRP) | - FDCAN_NBTP_NTSEG1(FDCAN1_NTSEG1) | - FDCAN_NBTP_NTSEG2(FDCAN1_NTSEG2) | - FDCAN_NBTP_NSJW(FDCAN1_NSJW), - .dbtp = FDCAN_DBTP_DBRP(FDCAN1_DBRP) | - FDCAN_DBTP_DTSEG1(FDCAN1_DTSEG1) | - FDCAN_DBTP_DTSEG2(FDCAN1_DTSEG2) | - FDCAN_DBTP_DSJW(FDCAN1_DSJW), - .port = 1, - .irq0 = STM32_IRQ_FDCAN1_0, - .irq1 = STM32_IRQ_FDCAN1_1, -#if defined(CONFIG_STM32F0L0G0_FDCAN1_CLASSIC) - .mode = FDCAN_CLASSIC_MODE, -#elif defined(CONFIG_STM32F0L0G0_FDCAN1_FD) - .mode = FDCAN_FD_MODE, -#else - .mode = FDCAN_FD_BRS_MODE, -#endif -#if defined(CONFIG_STM32F0L0G0_FDCAN1_NONISO_FORMAT) - .format = FDCAN_NONISO_BOSCH_V1_FORMAT, -#else - .format = FDCAN_ISO11898_1_FORMAT, -#endif - .nstdfilters = FDCAN1_STDFILTER_SIZE, - .nextfilters = FDCAN1_EXTFILTER_SIZE, - .nrxfifo0 = FDCAN1_RXFIFO0_SIZE, - .nrxfifo1 = FDCAN1_RXFIFO1_SIZE, - .ntxeventfifo = FDCAN1_TXEVENTFIFO_SIZE, - .ntxfifoq = FDCAN1_TXFIFIOQ_SIZE, - .rxfifo0esize = (FDCAN1_RXFIFO0_WORDS / FDCAN1_RXFIFO0_SIZE), - .rxfifo1esize = (FDCAN1_RXFIFO1_WORDS / FDCAN1_RXFIFO1_SIZE), - .txeventesize = (FDCAN1_TXEVENTFIFO_WORDS / FDCAN1_TXEVENTFIFO_SIZE), - .txbufferesize = (FDCAN1_TXFIFIOQ_WORDS / FDCAN1_TXFIFIOQ_SIZE), - -#ifdef CONFIG_STM32F0L0G0_FDCAN1_LOOPBACK - .loopback = true, -#endif - - /* FDCAN1 Message RAM */ - - .msgram = - { - (uint32_t *)(STM32_CANRAM1_BASE + (FDCAN1_STDFILTER_INDEX << 2)), - (uint32_t *)(STM32_CANRAM1_BASE + (FDCAN1_EXTFILTERS_INDEX << 2)), - (uint32_t *)(STM32_CANRAM1_BASE + (FDCAN1_RXFIFO0_INDEX << 2)), - (uint32_t *)(STM32_CANRAM1_BASE + (FDCAN1_RXFIFO1_INDEX << 2)), - (uint32_t *)(STM32_CANRAM1_BASE + (FDCAN1_TXEVENTFIFO_INDEX << 2)), - (uint32_t *)(STM32_CANRAM1_BASE + (FDCAN1_TXFIFOQ_INDEX << 2)) - } -}; - -/* FDCAN1 variable driver state */ - -static struct stm32_fdcan_s g_fdcan1priv; - -#endif /* CONFIG_STM32F0L0G0_FDCAN1 */ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: fdcan_getreg - * - * Description: - * Read the value of a FDCAN register. - * - * Input Parameters: - * priv - A reference to the FDCAN peripheral state - * offset - The offset to the register to read - * - * Returned Value: - * - ****************************************************************************/ - -#ifdef CONFIG_STM32F0L0G0_FDCAN_REGDEBUG -static uint32_t fdcan_getreg(struct stm32_fdcan_s *priv, int offset) -{ - const struct stm32_config_s *config = priv->config; - uintptr_t regaddr = 0; - uint32_t regval = 0; - - /* Read the value from the register */ - - regaddr = config->base + offset; - regval = getreg32(regaddr); - - /* Is this the same value that we read from the same register last time? - * Are we polling the register? If so, suppress some of the output. - */ - - if (regaddr == priv->regaddr && regval == priv->regval) - { - if (priv->count == 0xffffffff || ++priv->count > 3) - { - if (priv->count == 4) - { - ninfo("...\n"); - } - - return regval; - } - } - - /* No this is a new address or value */ - - else - { - /* Did we print "..." for the previous value? */ - - if (priv->count > 3) - { - /* Yes.. then show how many times the value repeated */ - - ninfo("[repeats %d more times]\n", priv->count - 3); - } - - /* Save the new address, value, and count */ - - priv->regaddr = regaddr; - priv->regval = regval; - priv->count = 1; - } - - /* Show the register value read */ - - ninfo("%08" PRIx32 "->%08" PRIx32 "\n", regaddr, regval); - return regval; -} - -#else -static uint32_t fdcan_getreg(struct stm32_fdcan_s *priv, int offset) -{ - const struct stm32_config_s *config = priv->config; - return getreg32(config->base + offset); -} - -#endif - -/**************************************************************************** - * Name: fdcan_putreg - * - * Description: - * Set the value of a FDCAN register. - * - * Input Parameters: - * priv - A reference to the FDCAN peripheral state - * offset - The offset to the register to write - * regval - The value to write to the register - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef CONFIG_STM32F0L0G0_FDCAN_REGDEBUG -static void fdcan_putreg(struct stm32_fdcan_s *priv, int offset, - uint32_t regval) -{ - const struct stm32_config_s *config = priv->config; - uintptr_t regaddr = config->base + offset; - - /* Show the register value being written */ - - ninfo("%08" PRIx32 "->%08" PRIx32 "\n", regaddr, regval); - - /* Write the value */ - - putreg32(regval, regaddr); -} - -#else -static void fdcan_putreg(struct stm32_fdcan_s *priv, int offset, - uint32_t regval) -{ - const struct stm32_config_s *config = priv->config; - putreg32(regval, config->base + offset); -} - -#endif - -/**************************************************************************** - * Name: fdcan_dumpctrlregs - * - * Description: - * Dump the contents of all CAN control registers - * - * Input Parameters: - * priv - A reference to the CAN block status - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef CONFIG_STM32F0L0G0_FDCAN_REGDEBUG -static void fdcan_dumpregs(struct stm32_fdcan_s *priv, - const char *msg) -{ - const struct stm32_config_s *config = priv->config; - - ninfo("CAN%d Control and Status Registers: %s\n", config->port, msg); - ninfo(" Base: %08" PRIx32 "\n", config->base); - - /* CAN control and status registers */ - - ninfo(" CCCR: %08" PRIx32 " TEST: %08" PRIx32 "\n", - getreg32(config->base + STM32_FDCAN_CCCR_OFFSET), - getreg32(config->base + STM32_FDCAN_TEST_OFFSET)); - - ninfo(" NBTP: %08" PRIx32 " DBTP: %08" PRIx32 "\n", - getreg32(config->base + STM32_FDCAN_NBTP_OFFSET), - getreg32(config->base + STM32_FDCAN_DBTP_OFFSET)); - - ninfo(" IE: %08" PRIx32 " TIE: %08" PRIx32 "\n", - getreg32(config->base + STM32_FDCAN_IE_OFFSET), - getreg32(config->base + STM32_FDCAN_TXBTIE_OFFSET)); - - ninfo(" ILE: %08" PRIx32 " ILS: %08" PRIx32 "\n", - getreg32(config->base + STM32_FDCAN_ILE_OFFSET), - getreg32(config->base + STM32_FDCAN_ILS_OFFSET)); - - ninfo(" TXBC: %08" PRIx32 "\n", - getreg32(config->base + STM32_FDCAN_TXBC_OFFSET)); -} -#endif - -/**************************************************************************** - * Name: fdcan_dumprxregs - * - * Description: - * Dump the contents of all Rx status registers - * - * Input Parameters: - * priv - A reference to the CAN block status - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef CONFIG_STM32F0L0G0_FDCAN_REGDEBUG -static void fdcan_dumprxregs(struct stm32_fdcan_s *priv, - const char *msg) -{ - const struct stm32_config_s *config = priv->config; - - ninfo("CAN%d Rx Registers: %s\n", config->port, msg); - ninfo(" Base: %08" PRIx32 "\n", config->base); - - ninfo(" PSR: %08" PRIx32 " ECR: %08" PRIx32 - " HPMS: %08" PRIx32 "\n", - getreg32(config->base + STM32_FDCAN_PSR_OFFSET), - getreg32(config->base + STM32_FDCAN_ECR_OFFSET), - getreg32(config->base + STM32_FDCAN_HPMS_OFFSET)); - - ninfo(" RXF0S: %08" PRIx32 " RXF0A: %08" PRIx32 "\n", - getreg32(config->base + STM32_FDCAN_RXF0S_OFFSET), - getreg32(config->base + STM32_FDCAN_RXF0A_OFFSET)); - - ninfo(" RXF1S: %08" PRIx32 " RXF1A: %08" PRIx32 "\n", - getreg32(config->base + STM32_FDCAN_RXF1S_OFFSET), - getreg32(config->base + STM32_FDCAN_RXF1A_OFFSET)); - - ninfo(" IR: %08" PRIx32 " IE: %08" PRIx32 "\n", - getreg32(config->base + STM32_FDCAN_IR_OFFSET), - getreg32(config->base + STM32_FDCAN_IE_OFFSET)); -} -#endif - -/**************************************************************************** - * Name: fdcan_dumptxregs - * - * Description: - * Dump the contents of all Tx buffer registers - * - * Input Parameters: - * priv - A reference to the CAN block status - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef CONFIG_STM32F0L0G0_FDCAN_REGDEBUG -static void fdcan_dumptxregs(struct stm32_fdcan_s *priv, - const char *msg) -{ - const struct stm32_config_s *config = priv->config; - - ninfo("CAN%d Tx Registers: %s\n", config->port, msg); - ninfo(" Base: %08" PRIx32 "\n", config->base); - - ninfo(" PSR: %08" PRIx32 " ECR: %08" PRIx32 "\n", - getreg32(config->base + STM32_FDCAN_PSR_OFFSET), - getreg32(config->base + STM32_FDCAN_ECR_OFFSET)); - - ninfo(" TXQFS: %08" PRIx32 " TXBAR: %08" PRIx32 - " TXBRP: %08" PRIx32 "\n", - getreg32(config->base + STM32_FDCAN_TXFQS_OFFSET), - getreg32(config->base + STM32_FDCAN_TXBAR_OFFSET), - getreg32(config->base + STM32_FDCAN_TXBRP_OFFSET)); - - ninfo(" TXBTO: %08" PRIx32 " TXBCR: %08" PRIx32 "\n", - getreg32(config->base + STM32_FDCAN_TXBTO_OFFSET), - getreg32(config->base + STM32_FDCAN_TXBCR_OFFSET)); - - ninfo(" TXEFS: %08" PRIx32 " TXEFA: %08" PRIx32 "\n", - getreg32(config->base + STM32_FDCAN_TXEFS_OFFSET), - getreg32(config->base + STM32_FDCAN_TXEFA_OFFSET)); - - ninfo(" IR: %08" PRIx32 " IE: %08" PRIx32 - " TIE: %08" PRIx32 "\n", - getreg32(config->base + STM32_FDCAN_IR_OFFSET), - getreg32(config->base + STM32_FDCAN_IE_OFFSET), - getreg32(config->base + STM32_FDCAN_TXBTIE_OFFSET)); -} -#endif - -/**************************************************************************** - * Name: fdcan_dumpramlayout - * - * Description: - * Print the layout of the message RAM - * - * Input Parameters: - * priv - A reference to the CAN block status - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef CONFIG_STM32F0L0G0_FDCAN_REGDEBUG -static void fdcan_dumpramlayout(struct stm32_fdcan_s *priv) -{ - const struct stm32_config_s *config = priv->config; - - ninfo(" ******* FDCAN%d Message RAM layout *******\n", config->port); - ninfo(" Start # Elmnt Elmnt size (words)\n"); - - if (config->nstdfilters > 0) - { - ninfo("STD filters %p %4d %2d\n", - config->msgram.stdfilters, - config->nstdfilters, - 1); - } - - if (config->nextfilters > 0) - { - ninfo("EXT filters %p %4d %2d\n", - config->msgram.extfilters, - config->nextfilters, - 2); - } - - if (config->nrxfifo0 > 0) - { - ninfo("RX FIFO 0 %p %4d %2d\n", - config->msgram.rxfifo0, - config->nrxfifo0, - config->rxfifo0esize); - } - - if (config->nrxfifo1 > 0) - { - ninfo("RX FIFO 1 %p %4d %2d\n", - config->msgram.rxfifo1, - config->nrxfifo1, - config->rxfifo1esize); - } - - if (config->ntxeventfifo > 0) - { - ninfo("TX EVENT %p %4d %2d\n", - config->msgram.txeventfifo, - config->ntxeventfifo, - config->txeventesize); - } - - if (config->ntxfifoq > 0) - { - ninfo("TX FIFO %p %4d %2d\n", - config->msgram.txfifoq, - config->ntxfifoq, - config->txbufferesize); - } -} -#endif - -/**************************************************************************** - * Name: fdcan_start_busoff_recovery_sequence - * - * Description: - * This function initiates the BUS-OFF recovery sequence. - * CAN Specification Rev. 2.0 or ISO11898-1:2015. - * According the STM32G4 datasheet section 44.3.2 Software initialziation. - * - * Input Parameters: - * priv - An instance of the FDCAN driver state structure. - * - * Returned Value: - * Zero (OK) is returned on success. Otherwise a negated errno value is - * returned to indicate the nature of the error. - * - ****************************************************************************/ - -#if 0 /* not used for now */ -static int -fdcan_start_busoff_recovery_sequence(struct stm32_fdcan_s *priv) -{ - uint32_t regval = 0; - - DEBUGASSERT(priv); - - /* Only start BUS-OFF recovery if we are in BUS-OFF state */ - - regval = fdcan_getreg(priv, STM32_FDCAN_PSR_OFFSET); - if ((regval & FDCAN_PSR_BO) == 0) - { - return -EPERM; - } - - /* Disable initialization mode to issue the recovery sequence */ - - regval = fdcan_getreg(priv, STM32_FDCAN_CCCR_OFFSET); - regval &= ~FDCAN_CCCR_INIT; - fdcan_putreg(priv, STM32_FDCAN_CCCR_OFFSET, regval); - - return OK; -} -#endif - -/**************************************************************************** - * Name: fdcan_reset - * - * Description: - * Reset the FDCAN device. Called early to initialize the hardware. This - * function is called, before fdcan_setup() and on error conditions. - * - * Input Parameters: - * dev - An instance of the "upper half" can driver state structure. - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void fdcan_reset(struct stm32_fdcan_s *priv) -{ - const struct stm32_config_s *config = NULL; - uint32_t regval = 0; - irqstate_t flags; - - DEBUGASSERT(priv); - config = priv->config; - DEBUGASSERT(config); - - ninfo("FDCAN%d\n", config->port); - UNUSED(config); - - /* Disable all interrupts */ - - fdcan_putreg(priv, STM32_FDCAN_IE_OFFSET, 0); - fdcan_putreg(priv, STM32_FDCAN_TXBTIE_OFFSET, 0); - - /* Make sure that all buffers are released. - * - * REVISIT: What if a thread is waiting for a buffer? The following - * will not wake up any waiting threads. - */ - - /* Disable the FDCAN controller. - * REVISIT: Should fdcan_shutdown() be called here? - */ - - /* Reset the FD CAN. - * REVISIT: Since there is only a single reset for both FDCAN - * controllers, do we really want to use the RCC reset here? - * This will nuke operation of the second controller if another - * device is registered. - */ - - flags = enter_critical_section(); - regval = getreg32(STM32_RCC_APB1RSTR); - regval |= RCC_APB1RSTR_FDCANRST; - putreg32(regval, STM32_RCC_APB1RSTR); - - regval &= ~RCC_APB1RSTR_FDCANRST; - putreg32(regval, STM32_RCC_APB1RSTR); - leave_critical_section(flags); - - priv->state = FDCAN_STATE_RESET; -} - -/**************************************************************************** - * Name: fdcan_setup - * - * Description: - * Configure the FDCAN. This method is called the first time that the FDCAN - * device is opened. This will occur when the port is first opened. - * This setup includes configuring and attaching FDCAN interrupts. - * All FDCAN interrupts are disabled upon return. - * - * Input Parameters: - * dev - An instance of the "upper half" can driver state structure. - * - * Returned Value: - * Zero on success; a negated errno on failure - * - ****************************************************************************/ - -static int fdcan_setup(struct stm32_fdcan_s *priv) -{ - const struct stm32_config_s *config = NULL; - int ret = 0; - - DEBUGASSERT(priv); - config = priv->config; - DEBUGASSERT(config); - - ninfo("FDCAN%d\n", config->port); - - /* FDCAN hardware initialization */ - - ret = fdcan_hw_initialize(priv); - if (ret < 0) - { - nerr("ERROR: FDCAN%d H/W initialization failed: %d\n", - config->port, ret); - return ret; - } - - fdcan_dumpregs(priv, "After hardware initialization"); - - /* Attach the FDCAN interrupt handlers */ - - ret = irq_attach(config->irq0, fdcan_interrupt, priv); - if (ret < 0) - { - nerr("ERROR: Failed to attach FDCAN%d line 0 IRQ (%d)", - config->port, config->irq0); - return ret; - } - - ret = irq_attach(config->irq1, fdcan_interrupt, priv); - if (ret < 0) - { - nerr("ERROR: Failed to attach FDCAN%d line 1 IRQ (%d)", - config->port, config->irq1); - return ret; - } - - priv->state = FDCAN_STATE_SETUP; - - /* Enable the interrupts at the NVIC (they are still disabled at the FDCAN - * peripheral). - */ - - up_enable_irq(config->irq0); - up_enable_irq(config->irq1); - - return OK; -} - -/**************************************************************************** - * Name: fdcan_shutdown - * - * Description: - * Disable the FDCAN. This method is called when the FDCAN device - * is closed. This method reverses the operation the setup method. - * - * Input Parameters: - * dev - An instance of the "upper half" can driver state structure. - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void fdcan_shutdown(struct stm32_fdcan_s *priv) -{ - const struct stm32_config_s *config = NULL; - uint32_t regval = 0; - - DEBUGASSERT(priv); - config = priv->config; - DEBUGASSERT(config); - - ninfo("FDCAN%d\n", config->port); - - /* Disable FDCAN interrupts at the NVIC */ - - up_disable_irq(config->irq0); - up_disable_irq(config->irq1); - - /* Disable all interrupts from the FDCAN peripheral */ - - fdcan_putreg(priv, STM32_FDCAN_IE_OFFSET, 0); - fdcan_putreg(priv, STM32_FDCAN_TXBTIE_OFFSET, 0); - - /* Detach the FDCAN interrupt handler */ - - irq_detach(config->irq0); - irq_detach(config->irq1); - - /* Disable device by setting the Clock Stop Request bit */ - - regval = fdcan_getreg(priv, STM32_FDCAN_CCCR_OFFSET); - regval |= FDCAN_CCCR_CSR; - fdcan_putreg(priv, STM32_FDCAN_CCCR_OFFSET, regval); - - /* Wait for Init and Clock Stop Acknowledge bits to verify - * device is in the powered down state - */ - - while ((fdcan_getreg(priv, STM32_FDCAN_CCCR_OFFSET) & FDCAN_CCCR_INIT) - == 0); - while ((fdcan_getreg(priv, STM32_FDCAN_CCCR_OFFSET) & FDCAN_CCCR_CSA) - == 0); - priv->state = FDCAN_STATE_DISABLED; -} - -/**************************************************************************** - * Name: fdcan_rx0int - * - * Description: - * Call to enable or disable RX0 interrupts. - * - * Input Parameters: - * priv - reference to the private CAN driver state structure - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void fdcan_rx0int(struct stm32_fdcan_s *priv, bool enable) -{ - const struct stm32_config_s *config = NULL; - uint32_t regval = 0; - - DEBUGASSERT(priv); - config = priv->config; - DEBUGASSERT(config); - - ninfo("CAN%" PRIu8 "RX0 enable: %d\n", config->port, enable); - - /* Enable/disable the FIFO 0 message pending interrupt */ - - regval = fdcan_getreg(priv, STM32_FDCAN_IE_OFFSET); - - if (enable) - { - regval |= FDCAN_RXFIFO0_INTS; - } - else - { - regval &= ~FDCAN_RXFIFO0_INTS; - } - - fdcan_putreg(priv, STM32_FDCAN_IE_OFFSET, regval); -} - -/**************************************************************************** - * Name: fdcan_rx1int - * - * Description: - * Call to enable or disable RX1 interrupts. - * - * Input Parameters: - * priv - reference to the private CAN driver state structure - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void fdcan_rx1int(struct stm32_fdcan_s *priv, bool enable) -{ - const struct stm32_config_s *config = NULL; - uint32_t regval = 0; - - DEBUGASSERT(priv); - config = priv->config; - DEBUGASSERT(config); - - ninfo("CAN%" PRIu8 "RX1 enable: %d\n", config->port, enable); - - /* Enable/disable the FIFO 1 message pending interrupt */ - - regval = fdcan_getreg(priv, STM32_FDCAN_IE_OFFSET); - - if (enable) - { - regval |= FDCAN_RXFIFO1_INTS; - } - else - { - regval &= ~FDCAN_RXFIFO1_INTS; - } - - fdcan_putreg(priv, STM32_FDCAN_IE_OFFSET, regval); -} - -/**************************************************************************** - * Name: fdcan_txint - * - * Description: - * Call to enable or disable TX interrupts. - * - * Input Parameters: - * dev - An instance of the "upper half" can driver state structure. - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void fdcan_txint(struct stm32_fdcan_s *priv, bool enable) -{ - const struct stm32_config_s *config = NULL; - uint32_t regval = 0; - - DEBUGASSERT(priv); - config = priv->config; - DEBUGASSERT(config); - - ninfo("CAN%" PRIu8 "TX enable: %d\n", config->port, enable); - - /* Enable/disable the receive interrupts */ - - regval = fdcan_getreg(priv, STM32_FDCAN_IE_OFFSET); - - if (enable) - { - regval |= FDCAN_TXFIFOQ_INTS; - } - else - { - regval &= ~FDCAN_TXFIFOQ_INTS; - } - - fdcan_putreg(priv, STM32_FDCAN_IE_OFFSET, regval); -} - -#ifdef CONFIG_NET_CAN_ERRORS -/**************************************************************************** - * Name: fdcan_txint - * - * Description: - * Call to enable or disable CAN SCE interrupts. - * - * Input Parameters: - * priv - reference to the private CAN driver state structure - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void fdcan_errint(struct stm32_fdcan_s *priv, bool enable) -{ - const struct stm32_config_s *config = NULL; - uint32_t regval = 0; - - DEBUGASSERT(priv); - config = priv->config; - DEBUGASSERT(config); - - ninfo("CAN%" PRIu8 "ERR enable: %d\n", config->port, enable); - - /* Enable/disable the transmit mailbox interrupt */ - - regval = fdcan_getreg(priv, STM32_FDCAN_IE_OFFSET); - if (enable) - { - regval |= FDCAN_ANYERR_INTS; - } - else - { - regval &= ~FDCAN_ANYERR_INTS; - } - - fdcan_putreg(priv, STM32_FDCAN_IE_OFFSET, regval); -} -#endif - -/**************************************************************************** - * Name: fdcan_send - * - * Description: - * Send one can message. - * - * One CAN-message consists of a maximum of 10 bytes. A message is - * composed of at least the first 2 bytes (when there are no data bytes). - * - * Byte 0: Bits 0-7: Bits 3-10 of the 11-bit CAN identifier - * Byte 1: Bits 5-7: Bits 0-2 of the 11-bit CAN identifier - * Bit 4: Remote Transmission Request (RTR) - * Bits 0-3: Data Length Code (DLC) - * Bytes 2-10: CAN data - * - * Input Parameters: - * dev - An instance of the "upper half" can driver state structure. - * - * Returned Value: - * Zero on success; a negated errno on failure - * - ****************************************************************************/ - -static int fdcan_send(struct stm32_fdcan_s *priv) -{ - const struct stm32_config_s *config = NULL; - volatile uint32_t *txbuffer = NULL; - const uint8_t *src = NULL; - uint32_t *dest = NULL; - uint32_t regval = 0; - unsigned int ndx = 0; - unsigned int nbytes = 0; - uint32_t wordbuffer = 0; - unsigned int i = 0; - - DEBUGASSERT(priv); - config = priv->config; - DEBUGASSERT(config); - - fdcan_dumptxregs(priv, "Before send"); - - /* That that FIFO elements were configured */ - - DEBUGASSERT(config->ntxfifoq > 0); - - /* Get our reserved Tx FIFO/queue put index */ - - regval = fdcan_getreg(priv, STM32_FDCAN_TXFQS_OFFSET); - DEBUGASSERT((regval & FDCAN_TXFQS_TFQF) == 0); - - ndx = (regval & FDCAN_TXFQS_TFQPI_MASK) >> FDCAN_TXFQS_TFQPI_SHIFT; - - /* And the TX buffer corresponding to this index */ - - txbuffer = (config->msgram.txfifoq + ndx * config->txbufferesize); - - /* Format the TX FIFOQ entry - * - * Format word T0: - * Transfer message ID (ID) - Value from message structure - * Remote Transmission Request (RTR) - Value from message structure - * Extended Identifier (XTD) - Depends on configuration. - * Error state indicator (ESI) - ESI bit in CAN FD - * - * Format word T1: - * Data Length Code (DLC) - Value from message structure - * Bit Rate Switch (BRS) - Bit rate switching for CAN FD - * FD format (FDF) - Frame transmitted in CAN FD format - * Event FIFO Control (EFC) - Do not store events. - * Message Marker (MM) - Always zero - */ - - txbuffer[0] = 0; - txbuffer[1] = 0; - - /* CAN 2.0 or CAN FD */ - - if (priv->dev.d_len == sizeof(struct can_frame)) - { - struct can_frame *frame = NULL; - - frame = (struct can_frame *)priv->dev.d_buf; - - ninfo("CAN%" PRIu8 " 2.0 ID: %" PRIu32 " DLC: %" PRIu8 "\n", - config->port, (uint32_t)frame->can_id, frame->can_dlc); - - /* Extended or standard ID */ - -#ifdef CONFIG_NET_CAN_EXTID - if ((frame->can_id & CAN_EFF_FLAG) != 0) - { - DEBUGASSERT((frame->can_id ^ CAN_EFF_FLAG) < (1 << 29)); - - txbuffer[0] |= BUFFER_R0_EXTID(frame->can_id) | BUFFER_R0_XTD; - } - else -#endif - { - DEBUGASSERT(frame->can_id < (1 << 11)); - - txbuffer[0] |= BUFFER_R0_STDID(frame->can_id); - } - - /* Set DLC */ - - txbuffer[1] |= BUFFER_R1_DLC(frame->can_dlc); - - /* Set flags */ - - if ((frame->can_id & CAN_RTR_FLAG) != 0) - { - txbuffer[0] |= BUFFER_R0_RTR; - } - - /* Reset CAN FD bits */ - - txbuffer[0] &= ~BUFFER_R0_ESI; - txbuffer[1] &= ~BUFFER_R1_FDF; - txbuffer[1] &= ~BUFFER_R1_BRS; - - /* Followed by the amount of data corresponding to the DLC (T2..) */ - - src = frame->data; - nbytes = frame->can_dlc; - } -#ifdef CONFIG_NET_CAN_CANFD - else /* CAN FD frame */ - { - struct canfd_frame *frame = (struct canfd_frame *)priv->dev.d_buf; - - frame = (struct canfd_frame *)priv->dev.d_buf; - - ninfo("CAN%" PRIu8 " FD ID: %" PRIu32 " len: %" PRIu8 "\n", - config->port, (uint32_t)frame->can_id, frame->len); - - /* Extended or standard ID */ - -#ifdef CONFIG_NET_CAN_EXTID - if ((frame->can_id & CAN_EFF_FLAG) != 0) - { - DEBUGASSERT(frame->can_id < (1 << 29)); - - txbuffer[0] |= BUFFER_R0_EXTID(frame->can_id) | BUFFER_R0_XTD; - } - else -#endif - { - DEBUGASSERT(frame->can_id < (1 << 11)); - - txbuffer[0] |= BUFFER_R0_STDID(frame->can_id); - } - - /* CANFD frame */ - - txbuffer[1] |= BUFFER_R1_FDF; - - /* Set DLC */ - - txbuffer[1] |= BUFFER_R1_DLC(g_len_to_can_dlc[frame->len]); - - /* Set flags */ - - if ((frame->can_id & CAN_RTR_FLAG) != 0) - { - txbuffer[0] |= BUFFER_R0_RTR; - } - - if ((frame->flags & CANFD_BRS) != 0) - { - txbuffer[1] |= BUFFER_R1_BRS; - } - - if ((frame->flags & CANFD_ESI) != 0) - { - txbuffer[0] |= BUFFER_R0_ESI; - } - - /* Followed by the amount of data corresponding to the DLC (T2..) */ - - src = frame->data; - nbytes = frame->len; - } -#endif - - dest = (uint32_t *)&txbuffer[2]; - - /* Writes must be word length */ - - for (i = 0; i < nbytes; i += 4) - { - /* Little endian is assumed */ - - wordbuffer = src[0] | - (src[1] << 8) | - (src[2] << 16) | - (src[3] << 24); - src += 4; - - *dest++ = wordbuffer; - } - - /* Enable transmit interrupts from the TX FIFOQ buffer by setting TC - * interrupt bit in IR (also requires that the TC interrupt is enabled) - */ - - fdcan_putreg(priv, STM32_FDCAN_TXBTIE_OFFSET, (1 << ndx)); - - /* And request to send the packet */ - - fdcan_putreg(priv, STM32_FDCAN_TXBAR_OFFSET, (1 << ndx)); - - return OK; -} - -/**************************************************************************** - * Name: fdcan_txready - * - * Description: - * Return true if the FDCAN hardware can accept another TX message. - * - * Input Parameters: - * dev - An instance of the "upper half" can driver state structure. - * - * Returned Value: - * True if the FDCAN hardware is ready to accept another TX message. - * - ****************************************************************************/ - -static bool fdcan_txready(struct stm32_fdcan_s *priv) -{ - uint32_t regval = 0; - bool notfull = false; - - /* Return the state of the TX FIFOQ. Return TRUE if the TX FIFO/Queue is - * not full. - */ - - regval = fdcan_getreg(priv, STM32_FDCAN_TXFQS_OFFSET); - notfull = ((regval & FDCAN_TXFQS_TFQF) == 0); - - return notfull; -} - -/**************************************************************************** - * Name: fdcan_rx0interrupt_work - * - * Description: - * CAN RX FIFO 0 worker - * - ****************************************************************************/ - -static void fdcan_rx0interrupt_work(void *arg) -{ - struct stm32_fdcan_s *priv = (struct stm32_fdcan_s *)arg; - const struct stm32_config_s *config = NULL; - uint32_t regval = 0; - unsigned int nelem = 0; - unsigned int ndx = 0; - - DEBUGASSERT(priv); - config = priv->config; - DEBUGASSERT(config); - - /* Clear the RX FIFO0 new message interrupt */ - - fdcan_putreg(priv, STM32_FDCAN_IR_OFFSET, FDCAN_INT_RF0N); - - regval = fdcan_getreg(priv, STM32_FDCAN_RXF0S_OFFSET); - nelem = (regval & FDCAN_RXFS_FFL_MASK) >> FDCAN_RXFS_FFL_SHIFT; - if (nelem > 0) - { - /* Handle the newly received message in FIFO0 */ - - ndx = (regval & FDCAN_RXFS_FGI_MASK) >> FDCAN_RXFS_FGI_SHIFT; - - if ((regval & FDCAN_RXFS_RFL) != 0) - { - nerr("ERROR: Message lost: %08" PRIx32 "\n", regval); - } - else - { - fdcan_receive(priv, - config->msgram.rxfifo0 + - (ndx * priv->config->rxfifo0esize), - priv->config->rxfifo0esize); - -#ifdef CONFIG_NET_CAN_ERRORS - /* Turning back on all configured RX error interrupts */ - - regval = fdcan_getreg(priv, STM32_FDCAN_IE_OFFSET); - regval |= FDCAN_RXERR_INTS; - fdcan_putreg(priv, STM32_FDCAN_IE_OFFSET, regval); -#endif - } - - /* Acknowledge reading the FIFO entry */ - - fdcan_putreg(priv, STM32_FDCAN_RXF0A_OFFSET, ndx); - } - - /* Re-enable CAN RX interrupts */ - - fdcan_rx0int(priv, true); -} - -/**************************************************************************** - * Name: fdcan_rx1interrupt_work - * - * Description: - * CAN RX FIFO 1 worker - * - ****************************************************************************/ - -static void fdcan_rx1interrupt_work(void *arg) -{ - struct stm32_fdcan_s *priv = (struct stm32_fdcan_s *)arg; - const struct stm32_config_s *config = NULL; - uint32_t regval = 0; - unsigned int nelem = 0; - unsigned int ndx = 0; - - DEBUGASSERT(priv); - config = priv->config; - DEBUGASSERT(config); - - /* Clear the RX FIFO1 new message interrupt */ - - fdcan_putreg(priv, STM32_FDCAN_IR_OFFSET, FDCAN_INT_RF1N); - - /* Check if there is anything in RX FIFO1 */ - - regval = fdcan_getreg(priv, STM32_FDCAN_RXF1S_OFFSET); - nelem = (regval & FDCAN_RXFS_FFL_MASK) >> FDCAN_RXFS_FFL_SHIFT; - if (nelem == 0) - { - /* Clear the RX FIFO1 interrupt (and all other FIFO1-related - * interrupts) - */ - - /* Handle the newly received message in FIFO1 */ - - ndx = (regval & FDCAN_RXFS_FGI_MASK) >> FDCAN_RXFS_FGI_SHIFT; - - if ((regval & FDCAN_RXFS_RFL) != 0) - { - nerr("ERROR: Message lost: %08" PRIx32 "\n", regval); - } - else - { - fdcan_receive(priv, - config->msgram.rxfifo1 + - (ndx * priv->config->rxfifo1esize), - priv->config->rxfifo1esize); - -#ifdef CONFIG_NET_CAN_ERRORS - /* Turning back on all configured RX error interrupts */ - - regval = fdcan_getreg(priv, STM32_FDCAN_IE_OFFSET); - regval |= FDCAN_RXERR_INTS; - fdcan_putreg(priv, STM32_FDCAN_IE_OFFSET, regval); -#endif - } - - /* Acknowledge reading the FIFO entry */ - - fdcan_putreg(priv, STM32_FDCAN_RXF1A_OFFSET, ndx); - } - - /* Re-enable CAN RX interrupts */ - - fdcan_rx1int(priv, true); -} - -/**************************************************************************** - * Name: fdcan_txdone_work - ****************************************************************************/ - -static void fdcan_txdone_work(void *arg) -{ - struct stm32_fdcan_s *priv = (struct stm32_fdcan_s *)arg; - - fdcan_txdone(priv); - - /* There should be space for a new TX in any event. Poll the network for - * new XMIT data - */ - - net_lock(); - devif_poll(&priv->dev, fdcan_txpoll); - net_unlock(); -} - -/**************************************************************************** - * Name: fdcan_txdone - ****************************************************************************/ - -static void fdcan_txdone(struct stm32_fdcan_s *priv) -{ - const struct stm32_config_s *config = NULL; - unsigned int ndx = 0; - uint32_t regval = 0; - - DEBUGASSERT(priv); - config = priv->config; - DEBUGASSERT(config); - - /* Clear the pending TX completion interrupt (and all - * other TX-related interrupts) - */ - - fdcan_putreg(priv, STM32_FDCAN_IR_OFFSET, FDCAN_TXFIFOQ_INTS); - - /* Check all TX buffers */ - - regval = fdcan_getreg(priv, STM32_FDCAN_TXBTO_OFFSET); - for (ndx = 0; ndx < config->ntxfifoq; ndx++) - { - if ((regval & (1 << ndx)) != 0) - { - /* Tell the upper half that the transfer is finished. */ - - NETDEV_TXDONE(&priv->dev); - } - } - -#ifdef CONFIG_NET_CAN_ERRORS - /* Turning back on PEA and PED error interrupts */ - - regval = fdcan_getreg(priv, STM32_FDCAN_IE_OFFSET); - regval |= (FDCAN_INT_PEA | FDCAN_INT_PED); - fdcan_putreg(priv, STM32_FDCAN_IE_OFFSET, regval); -#endif - - /* Re-enable TX interrupts */ - - fdcan_txint(priv, true); -} - -#ifdef CONFIG_NET_CAN_ERRORS -/**************************************************************************** - * Name: fdcan_error_work - ****************************************************************************/ - -static void fdcan_error_work(void *arg) -{ - struct stm32_fdcan_s *priv = (struct stm32_fdcan_s *)arg; - uint32_t pending = 0; - uint32_t ir = 0; - uint32_t ie = 0; - uint32_t psr = 0; - - /* Get the set of pending interrupts. */ - - ir = fdcan_getreg(priv, STM32_FDCAN_IR_OFFSET); - ie = fdcan_getreg(priv, STM32_FDCAN_IE_OFFSET); - - pending = (ir & ie); - ie |= FDCAN_ANYERR_INTS; - - /* Check for common errors */ - - if ((pending & FDCAN_CMNERR_INTS) != 0) - { - /* When a protocol error occurs, the problem is recorded in - * the LEC/DLEC fields of the PSR register. In lieu of - * separate interrupt flags for each error, the hardware - * groups protocol errors under a single interrupt each for - * arbitration and data phases. - * - * These errors have a tendency to flood the system with - * interrupts, so they are disabled here until we get a - * successful transfer/receive on the hardware - */ - - psr = fdcan_getreg(priv, STM32_FDCAN_PSR_OFFSET); - - if ((psr & FDCAN_PSR_LEC_MASK) != 0) - { - ie &= ~(FDCAN_INT_PEA | FDCAN_INT_PED); - } - - /* Clear the error indications */ - - fdcan_putreg(priv, STM32_FDCAN_IR_OFFSET, FDCAN_CMNERR_INTS); - } - - /* Check for transmission errors */ - - if ((pending & FDCAN_TXERR_INTS) != 0) - { - /* An Acknowledge-Error will occur if for example the device - * is not connected to the bus. - * - * The CAN-Standard states that the Chip has to retry the - * message forever, which will produce an ACKE every time. - * To prevent this Interrupt-Flooding and the high CPU-Load - * we disable the ACKE here as long we didn't transfer at - * least one message successfully (see FDCAN_INT_TC below). - */ - - /* Clear the error indications */ - - fdcan_putreg(priv, STM32_FDCAN_IR_OFFSET, FDCAN_TXERR_INTS); - } - - /* Check for reception errors */ - - if ((pending & FDCAN_RXERR_INTS) != 0) - { - /* To prevent Interrupt-Flooding the current active - * RX error interrupts are disabled. After successfully - * receiving at least one CAN packet all RX error interrupts - * are turned back on. - * - * The Interrupt-Flooding can for example occur if the - * configured CAN speed does not match the speed of the other - * CAN nodes in the network. - */ - - ie &= ~(pending & FDCAN_RXERR_INTS); - - /* Clear the error indications */ - - fdcan_putreg(priv, STM32_FDCAN_IR_OFFSET, FDCAN_RXERR_INTS); - } - - /* Report errors */ - - net_lock(); - fdcan_error(priv, pending & FDCAN_ANYERR_INTS); - net_unlock(); - - /* Re-enable ERROR interrupts */ - - fdcan_putreg(priv, STM32_FDCAN_IE_OFFSET, ie); -} - -/**************************************************************************** - * Name: fdcan_error - * - * Description: - * Report a CAN error - * - * Input Parameters: - * dev - CAN-common state data - * status - Interrupt status with error bits set - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void fdcan_error(struct stm32_fdcan_s *priv, uint32_t status) -{ - struct can_frame *frame = (struct can_frame *)priv->rxdesc; - uint32_t psr = 0; - uint16_t errbits = 0; - uint8_t data[CAN_ERR_DLC]; - - DEBUGASSERT(priv != NULL); - - /* Encode error bits */ - - errbits = 0; - memset(data, 0, sizeof(data)); - - /* Always fill in "static" error conditions, but set the signaling bit - * only if the condition has changed (see IRQ-Flags below) - * They have to be filled in every time CAN_ERROR_CONTROLLER is set. - */ - - psr = fdcan_getreg(priv, STM32_FDCAN_PSR_OFFSET); - if ((psr & FDCAN_PSR_EP) != 0) - { - data[1] |= (CAN_ERR_CRTL_RX_PASSIVE | CAN_ERR_CRTL_TX_PASSIVE); - } - - if ((psr & FDCAN_PSR_EW) != 0) - { - data[1] |= (CAN_ERR_CRTL_RX_WARNING | CAN_ERR_CRTL_TX_WARNING); - } - - if ((status & (FDCAN_INT_EP | FDCAN_INT_EW)) != 0) - { - /* "Error Passive" or "Error Warning" status changed */ - - errbits |= CAN_ERR_CRTL; - } - - if ((status & FDCAN_INT_PEA) != 0) - { - /* Protocol Error in Arbitration Phase */ - - if ((psr & FDCAN_PSR_LEC_MASK) != 0) - { - /* Error code present */ - - if ((psr & FDCAN_PSR_LEC(FDCAN_PSR_EC_STUFF_ERROR)) != 0) - { - /* Stuff Error */ - - errbits |= CAN_ERR_PROT; - data[2] |= CAN_ERR_PROT_STUFF; - } - - if ((psr & FDCAN_PSR_LEC(FDCAN_PSR_EC_FORM_ERROR)) != 0) - { - /* Format Error */ - - errbits |= CAN_ERR_PROT; - data[2] |= CAN_ERR_PROT_FORM; - } - - if ((psr & FDCAN_PSR_LEC(FDCAN_PSR_EC_ACK_ERROR)) != 0) - { - /* Acknowledge Error */ - - errbits |= CAN_ERR_ACK; - } - - if ((psr & FDCAN_PSR_LEC(FDCAN_PSR_EC_BIT0_ERROR)) != 0) - { - /* Bit0 Error */ - - errbits |= CAN_ERR_PROT; - data[2] |= CAN_ERR_PROT_BIT0; - } - - if ((psr & FDCAN_PSR_LEC(FDCAN_PSR_EC_BIT1_ERROR)) != 0) - { - /* Bit1 Error */ - - errbits |= CAN_ERR_PROT; - data[2] |= CAN_ERR_PROT_BIT1; - } - - if ((psr & FDCAN_PSR_LEC(FDCAN_PSR_EC_CRC_ERROR)) != 0) - { - /* Receive CRC Error */ - - errbits |= CAN_ERR_PROT; - data[3] |= (CAN_ERR_PROT_LOC_CRC_SEQ | - CAN_ERR_PROT_LOC_CRC_DEL); - } - - if ((psr & FDCAN_PSR_LEC(FDCAN_PSR_EC_NO_CHANGE)) != 0) - { - /* No Change in Error */ - - errbits |= CAN_ERR_PROT; - data[2] |= CAN_ERR_PROT_UNSPEC; - } - } - } - - if ((status & FDCAN_INT_PED) != 0) - { - /* Protocol Error in Data Phase */ - - if ((psr & FDCAN_PSR_DLEC_MASK) != 0) - { - /* Error code present */ - - if ((psr & FDCAN_PSR_DLEC(FDCAN_PSR_EC_STUFF_ERROR)) != 0) - { - /* Stuff Error */ - - errbits |= CAN_ERR_PROT; - data[2] |= CAN_ERR_PROT_STUFF; - } - - if ((psr & FDCAN_PSR_DLEC(FDCAN_PSR_EC_FORM_ERROR)) != 0) - { - /* Format Error */ - - errbits |= CAN_ERR_PROT; - data[2] |= CAN_ERR_PROT_FORM; - } - - if ((psr & FDCAN_PSR_DLEC(FDCAN_PSR_EC_ACK_ERROR)) != 0) - { - /* Acknowledge Error */ - - errbits |= CAN_ERR_ACK; - } - - if ((psr & FDCAN_PSR_DLEC(FDCAN_PSR_EC_BIT0_ERROR)) != 0) - { - /* Bit0 Error */ - - errbits |= CAN_ERR_PROT; - data[2] |= CAN_ERR_PROT_BIT0; - } - - if ((psr & FDCAN_PSR_DLEC(FDCAN_PSR_EC_BIT1_ERROR)) != 0) - { - /* Bit1 Error */ - - errbits |= CAN_ERR_PROT; - data[2] |= CAN_ERR_PROT_BIT1; - } - - if ((psr & FDCAN_PSR_DLEC(FDCAN_PSR_EC_CRC_ERROR)) != 0) - { - /* Receive CRC Error */ - - errbits |= CAN_ERR_PROT; - data[3] |= (CAN_ERR_PROT_LOC_CRC_SEQ | - CAN_ERR_PROT_LOC_CRC_DEL); - } - - if ((psr & FDCAN_PSR_DLEC(FDCAN_PSR_EC_NO_CHANGE)) != 0) - { - /* No Change in Error */ - - errbits |= CAN_ERR_PROT; - data[2] |= CAN_ERR_PROT_UNSPEC; - } - } - } - - if ((status & FDCAN_INT_BO) != 0) - { - /* Bus_Off Status changed */ - - if ((psr & FDCAN_PSR_BO) != 0) - { - errbits |= CAN_ERR_BUSOFF; - } - else - { - errbits |= CAN_ERR_RESTARTED; - } - } - - if ((status & (FDCAN_INT_RF0L | FDCAN_INT_RF1L)) != 0) - { - /* Receive FIFO 0/1 Message Lost - * Receive FIFO 1 Message Lost - */ - - errbits |= CAN_ERR_CRTL; - data[1] |= CAN_ERR_CRTL_RX_OVERFLOW; - } - - if ((status & FDCAN_INT_TEFL) != 0) - { - /* Tx Event FIFO Element Lost */ - - errbits |= CAN_ERR_CRTL; - data[1] |= CAN_ERR_CRTL_TX_OVERFLOW; - } - - if ((status & FDCAN_INT_TOO) != 0) - { - /* Timeout Occurred */ - - errbits |= CAN_ERR_TX_TIMEOUT; - } - - if ((status & (FDCAN_INT_MRAF | FDCAN_INT_ELO)) != 0) - { - /* Message RAM Access Failure - * Error Logging Overflow - */ - - errbits |= CAN_ERR_CRTL; - data[1] |= CAN_ERR_CRTL_UNSPEC; - } - - if (errbits != 0) - { - nerr("ERROR: errbits = %08" PRIx16 "\n", errbits); - - /* Copy frame */ - - frame->can_id = errbits; - frame->can_dlc = CAN_ERR_DLC; - - memcpy(frame->data, data, CAN_ERR_DLC); - - /* Copy the buffer pointer to priv->dev.. Set amount of data - * in priv->dev.d_len - */ - - priv->dev.d_len = sizeof(struct can_frame); - priv->dev.d_buf = (uint8_t *)frame; - - /* Send to socket interface */ - - NETDEV_ERRORS(&priv->dev); - - can_input(&priv->dev); - - /* Point the packet buffer back to the next Tx buffer that will be - * used during the next write. If the write queue is full, then - * this will point at an active buffer, which must not be written - * to. This is OK because devif_poll won't be called unless the - * queue is not full. - */ - - priv->dev.d_buf = (uint8_t *)priv->txdesc; - } -} -#endif /* CONFIG_NET_CAN_ERRORS */ - -/**************************************************************************** - * Name: fdcan_receive - * - * Description: - * Receive an FDCAN messages - * - * Input Parameters: - * dev - CAN-common state data - * rxbuffer - The RX buffer containing the received messages - * nwords - The length of the RX buffer (element size in words). - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void fdcan_receive(struct stm32_fdcan_s *priv, - volatile uint32_t *rxbuffer, - unsigned long nwords) -{ - fdcan_dumprxregs(dev->cd_priv, "Before receive"); - - /* CAN 2.0 or CAN FD */ - -#ifdef CONFIG_NET_CAN_CANFD - if ((rxbuffer[1] & BUFFER_R1_FDF) != 0) - { - struct canfd_frame *frame = (struct canfd_frame *)priv->rxdesc; - - /* Format the CAN FD header */ - - /* Extract the RTR bit */ - - if ((rxbuffer[0] & BUFFER_R0_RTR) != 0) - { - frame->can_id |= CAN_RTR_FLAG; - } - -#ifdef CONFIG_NET_CAN_EXTID - if ((rxbuffer[0] & BUFFER_R0_XTD) != 0) - { - /* Save the extended ID of the newly received message */ - - frame->can_id = ((rxbuffer[0] & BUFFER_R0_EXTID_MASK) >> - BUFFER_R0_EXTID_SHIFT); - frame->can_id |= CAN_EFF_FLAG; - } - else - { - frame->can_id = ((rxbuffer[0] & BUFFER_R0_STDID_MASK) >> - BUFFER_R0_STDID_SHIFT); - frame->can_id &= ~CAN_EFF_FLAG; - } -#else - if ((rxbuffer[0] & BUFFER_R0_XTD) != 0) - { - /* Drop any messages with extended IDs */ - - return; - } - - /* Save the standard ID of the newly received message */ - - frame->can_id = ((rxbuffer[0] & BUFFER_R0_STDID_MASK) >> - BUFFER_R0_STDID_SHIFT); -#endif - - /* Word R1 contains the DLC and timestamp */ - - frame->len = g_can_dlc_to_len[((rxbuffer[1] & BUFFER_R1_DLC_MASK) >> - BUFFER_R1_DLC_SHIFT)]; - - /* Get CANFD flags */ - - frame->flags = 0; - - if ((rxbuffer[0] & BUFFER_R0_ESI) != 0) - { - frame->flags |= CANFD_ESI; - } - - if ((rxbuffer[1] & BUFFER_R1_BRS) != 0) - { - frame->flags |= CANFD_BRS; - } - - /* Save the message data */ - - memcpy(frame->data, (void *)&rxbuffer[2], frame->len); - - /* Copy the buffer pointer to priv->dev.. Set amount of data - * in priv->dev.d_len - */ - - priv->dev.d_len = sizeof(struct canfd_frame); - priv->dev.d_buf = (uint8_t *)frame; - } - else -#endif - { - struct can_frame *frame = (struct can_frame *)priv->rxdesc; - - /* Format the CAN header */ - - /* Extract the RTR bit */ - - if ((rxbuffer[0] & BUFFER_R0_RTR) != 0) - { - frame->can_id |= CAN_RTR_FLAG; - } - -#ifdef CONFIG_NET_CAN_EXTID - if ((rxbuffer[0] & BUFFER_R0_XTD) != 0) - { - /* Save the extended ID of the newly received message */ - - frame->can_id = ((rxbuffer[0] & BUFFER_R0_EXTID_MASK) >> - BUFFER_R0_EXTID_SHIFT); - frame->can_id |= CAN_EFF_FLAG; - } - else - { - frame->can_id = ((rxbuffer[0] & BUFFER_R0_STDID_MASK) >> - BUFFER_R0_STDID_SHIFT); - frame->can_id &= ~CAN_EFF_FLAG; - } -#else - if ((rxbuffer[0] & BUFFER_R0_XTD) != 0) - { - /* Drop any messages with extended IDs */ - - return; - } - - /* Save the standard ID of the newly received message */ - - frame->can_id = ((rxbuffer[0] & BUFFER_R0_STDID_MASK) >> - BUFFER_R0_STDID_SHIFT); -#endif - - /* Word R1 contains the DLC and timestamp */ - - frame->can_dlc = ((rxbuffer[1] & BUFFER_R1_DLC_MASK) >> - BUFFER_R1_DLC_SHIFT); - - /* Save the message data */ - - memcpy(frame->data, (void *)&rxbuffer[2], frame->can_dlc); - - /* Copy the buffer pointer to priv->dev.. Set amount of data - * in priv->dev.d_len - */ - - priv->dev.d_len = sizeof(struct can_frame); - priv->dev.d_buf = (uint8_t *)frame; - } - - /* Send to socket interface */ - - NETDEV_RXPACKETS(&priv->dev); - - can_input(&priv->dev); - - /* Point the packet buffer back to the next Tx buffer that will be - * used during the next write. If the write queue is full, then - * this will point at an active buffer, which must not be written - * to. This is OK because devif_poll won't be called unless the - * queue is not full. - */ - - priv->dev.d_buf = (uint8_t *)priv->txdesc; -} - -/**************************************************************************** - * Name: fdcan_interrupt - * - * Description: - * Common FDCAN interrupt handler - * - * irq - The IRQ number of the interrupt. - * context - The register state save array at the time of the interrupt. - * - * Returned Value: - * Zero on success; a negated errno on failure - * - ****************************************************************************/ - -static int fdcan_interrupt(int irq, void *context, void *arg) -{ - struct stm32_fdcan_s *priv = (struct stm32_fdcan_s *)arg; - uint32_t pending = 0; - - DEBUGASSERT(priv != NULL); - - /* Get the set of pending interrupts. */ - - pending = fdcan_getreg(priv, STM32_FDCAN_IR_OFFSET); - -#ifdef CONFIG_NET_CAN_ERRORS - /* Check for any errors */ - - if ((pending & FDCAN_ANYERR_INTS) != 0) - { - /* Disable further CAN ERROR interrupts and schedule to perform the - * interrupt processing on the worker thread - */ - - fdcan_errint(priv, false); - work_queue(CANWORK, &priv->irqwork, fdcan_error_work, priv, 0); - } -#endif - - /* Check for successful completion of a transmission */ - - if ((pending & FDCAN_INT_TC) != 0) - { - /* Disable further TX CAN interrupts. here can be no race - * condition here. - */ - - fdcan_txint(priv, false); - work_queue(CANWORK, &priv->irqwork, fdcan_txdone_work, priv, 0); - } - else if ((pending & FDCAN_TXFIFOQ_INTS) != 0) - { - /* Clear unhandled TX events */ - - fdcan_putreg(priv, STM32_FDCAN_IR_OFFSET, FDCAN_TXFIFOQ_INTS); - } - - if (pending & FDCAN_INT_RF1N) - { - /* Disable further CAN RX interrupts and schedule to perform the - * interrupt processing on the worker thread - */ - - fdcan_rx1int(priv, false); - work_queue(CANWORK, &priv->irqwork, - fdcan_rx1interrupt_work, priv, 0); - } - - /* Clear the RX FIFO0 new message interrupt */ - - if (pending & FDCAN_INT_RF0N) - { - /* Disable further CAN RX interrupts and schedule to perform the - * interrupt processing on the worker thread - */ - - fdcan_rx0int(priv, false); - work_queue(CANWORK, &priv->irqwork, - fdcan_rx0interrupt_work, priv, 0); - } - - return OK; -} - -/**************************************************************************** - * Name: fdcan_hw_initialize - * - * Description: - * FDCAN hardware initialization - * - * Input Parameters: - * priv - A pointer to the private data structure for this FDCAN peripheral - * - * Returned Value: - * Zero on success; a negated errno value on failure. - * - ****************************************************************************/ - -static int fdcan_hw_initialize(struct stm32_fdcan_s *priv) -{ - const struct stm32_config_s *config = NULL; - volatile uint32_t *msgram = NULL; - uint32_t regval = 0; - uint32_t cntr = 0; - - DEBUGASSERT(priv); - config = priv->config; - DEBUGASSERT(config); - - ninfo("FDCAN%d\n", config->port); - - /* Clean message RAM */ - - msgram = config->msgram.stdfilters; - cntr = (FDCAN_MSGRAM_WORDS + 1); - while (cntr > 0) - { - *msgram++ = 0; - cntr--; - } - - /* Configure FDCAN pins */ - - stm32_configgpio(config->rxpinset); - stm32_configgpio(config->txpinset); - - /* Re-enable device if previously disabled in fdcan_shutdown() */ - - if (priv->state == FDCAN_STATE_DISABLED) - { - /* Reset Clock Stop Request bit */ - - regval = fdcan_getreg(priv, STM32_FDCAN_CCCR_OFFSET); - regval &= ~FDCAN_CCCR_CSR; - fdcan_putreg(priv, STM32_FDCAN_CCCR_OFFSET, regval); - - /* Wait for Clock Stop Acknowledge bit reset to indicate - * device is operational - */ - - while ((fdcan_getreg(priv, STM32_FDCAN_CCCR_OFFSET) & FDCAN_CCCR_CSA) - != 0); - } - - /* Enable the Initialization state */ - - regval = fdcan_getreg(priv, STM32_FDCAN_CCCR_OFFSET); - regval |= FDCAN_CCCR_INIT; - fdcan_putreg(priv, STM32_FDCAN_CCCR_OFFSET, regval); - - /* Wait for initialization mode to take effect */ - - while ((fdcan_getreg(priv, STM32_FDCAN_CCCR_OFFSET) & FDCAN_CCCR_INIT) - == 0); - - /* Enable writing to configuration registers */ - - regval = fdcan_getreg(priv, STM32_FDCAN_CCCR_OFFSET); - regval |= FDCAN_CCCR_CCE; - fdcan_putreg(priv, STM32_FDCAN_CCCR_OFFSET, regval); - - /* Global Filter Configuration: - * - * ANFS=0: Store all non matching standard frame in RX FIFO0 - * ANFE=0: Store all non matching extended frame in RX FIFO0 - */ - - regval = FDCAN_RXGFC_ANFE_RX_FIFO0 | FDCAN_RXGFC_ANFS_RX_FIFO0; - fdcan_putreg(priv, STM32_FDCAN_RXGFC_OFFSET, regval); - - /* Extended ID Filter AND mask */ - - fdcan_putreg(priv, STM32_FDCAN_XIDAM_OFFSET, 0x1fffffff); - - /* Disable all interrupts */ - - fdcan_putreg(priv, STM32_FDCAN_IE_OFFSET, 0); - fdcan_putreg(priv, STM32_FDCAN_TXBTIE_OFFSET, 0); - - /* All interrupts directed to Line 0. But disable both interrupt lines 0 - * and 1 for now. - * - * REVISIT: Only interrupt line 0 is used by this driver. - */ - - fdcan_putreg(priv, STM32_FDCAN_ILS_OFFSET, 0); - fdcan_putreg(priv, STM32_FDCAN_ILE_OFFSET, 0); - - /* Clear all pending interrupts. */ - - fdcan_putreg(priv, STM32_FDCAN_IR_OFFSET, FDCAN_INT_ALL); - - /* Configure FDCAN bit timing */ - - fdcan_putreg(priv, STM32_FDCAN_NBTP_OFFSET, priv->nbtp); - fdcan_putreg(priv, STM32_FDCAN_DBTP_OFFSET, priv->dbtp); - - /* Configure message RAM starting addresses and sizes. */ - - regval = FDCAN_RXGFC_LSS(config->nstdfilters); - regval |= FDCAN_RXGFC_LSE(config->nextfilters); - fdcan_putreg(priv, STM32_FDCAN_RXGFC_OFFSET, regval); - - /* Dump RAM layout */ - - fdcan_dumpramlayout(priv); - - /* Configure Message Filters */ - - /* Disable all standard filters */ - - msgram = config->msgram.stdfilters; - cntr = config->nstdfilters; - while (cntr > 0) - { - *msgram++ = STDFILTER_S0_SFEC_DISABLE; - cntr--; - } - - /* Disable all extended filters */ - - msgram = config->msgram.extfilters; - cntr = config->nextfilters; - while (cntr > 0) - { - *msgram = EXTFILTER_F0_EFEC_DISABLE; - msgram = msgram + 2; - cntr--; - } - - /* Input clock divider configuration */ - - regval = FDCANCLK_PDIV; - fdcan_putreg(priv, STM32_FDCAN_CKDIV_OFFSET, regval); - - /* CC control register */ - - regval = fdcan_getreg(priv, STM32_FDCAN_CCCR_OFFSET); - regval &= ~(FDCAN_CCCR_NISO | FDCAN_CCCR_FDOE | FDCAN_CCCR_BRSE); - - /* Select ISO11898-1 or Non ISO Bosch CAN FD Specification V1.0 */ - - switch (config->format) - { - case FDCAN_ISO11898_1_FORMAT: - { - break; - } - - case FDCAN_NONISO_BOSCH_V1_FORMAT: - { - regval |= FDCAN_CCCR_NISO; - break; - } - - default: - { - return -EINVAL; - } - } - - /* Select Classic CAN mode or FD mode with or without fast bit rate - * switching - */ - - switch (config->mode) - { - case FDCAN_CLASSIC_MODE: - { - break; - } - -#ifdef CONFIG_NET_CAN_CANFD - case FDCAN_FD_MODE: - { - regval |= FDCAN_CCCR_FDOE; - break; - } - - case FDCAN_FD_BRS_MODE: - { - regval |= (FDCAN_CCCR_FDOE | FDCAN_CCCR_BRSE); - break; - } -#endif - - default: - { - return -EINVAL; - } - } - - /* Set the initial CAN mode */ - - fdcan_putreg(priv, STM32_FDCAN_CCCR_OFFSET, regval); - - /* Enable FIFO/Queue mode */ - - regval = fdcan_getreg(priv, STM32_FDCAN_TXBC_OFFSET); -#ifdef CONFIG_STM32F0L0G0_FDCAN_QUEUE_MODE - regval |= FDCAN_TXBC_TFQM; -#else - regval &= ~FDCAN_TXBC_TFQM; -#endif - fdcan_putreg(priv, STM32_FDCAN_TXBC_OFFSET, regval); - -#ifdef STM32_FDCAN_LOOPBACK - /* Is loopback mode selected for this peripheral? */ - - if (config->loopback) - { - /* FDCAN_CCCR_TEST - Test mode enable - * FDCAN_CCCR_MON - Bus monitoring mode (for internal loopback) - * FDCAN_TEST_LBCK - Loopback mode - */ - - regval = fdcan_getreg(priv, STM32_FDCAN_CCCR_OFFSET); - regval |= (FDCAN_CCCR_TEST | FDCAN_CCCR_MON); - fdcan_putreg(priv, STM32_FDCAN_CCCR_OFFSET, regval); - - regval = fdcan_getreg(priv, STM32_FDCAN_TEST_OFFSET); - regval |= FDCAN_TEST_LBCK; - fdcan_putreg(priv, STM32_FDCAN_TEST_OFFSET, regval); - } -#endif - - /* Configure interrupt lines */ - - /* Direct all interrupts to Line 0. - * - * Bits in the ILS register correspond to each FDCAN interrupt; A bit - * set to '1' is directed to interrupt line 1; a bit cleared to '0' - * is directed interrupt line 0. - * - * REVISIT: Nothing is done here. Only interrupt line 0 is used by - * this driver and ILS was already cleared above. - */ - - /* Enable only interrupt line 0. */ - - fdcan_putreg(priv, STM32_FDCAN_ILE_OFFSET, FDCAN_ILE_EINT0); - - /* Disable initialization mode to enable normal operation */ - - regval = fdcan_getreg(priv, STM32_FDCAN_CCCR_OFFSET); - regval &= ~FDCAN_CCCR_INIT; - fdcan_putreg(priv, STM32_FDCAN_CCCR_OFFSET, regval); - - return OK; -} - -/**************************************************************************** - * Function: fdcan_ifup - * - * Description: - * NuttX Callback: Bring up the Ethernet interface when an IP address is - * provided - * - * Input Parameters: - * dev - Reference to the NuttX driver state structure - * - * Returned Value: - * None - * - * Assumptions: - * - ****************************************************************************/ - -static int fdcan_ifup(struct net_driver_s *dev) -{ - struct stm32_fdcan_s *priv = - (struct stm32_fdcan_s *)dev->d_private; - const struct stm32_config_s *config = NULL; - - DEBUGASSERT(priv); - config = priv->config; - DEBUGASSERT(config); - - /* Setup CAN */ - - fdcan_setup(priv); - - /* Enable interrupts */ - - fdcan_rx0int(priv, true); - fdcan_rx1int(priv, true); - fdcan_txint(priv, true); -#ifdef CONFIG_NET_CAN_ERRORS - fdcan_errint(priv, true); -#endif - - /* Enable the interrupts at the NVIC */ - - up_enable_irq(config->irq0); - up_enable_irq(config->irq1); - - priv->bifup = true; - - priv->txdesc = (struct can_frame *)priv->tx_pool; - priv->rxdesc = (struct can_frame *)priv->rx_pool; - - priv->dev.d_buf = (uint8_t *)priv->txdesc; - - return OK; -} - -/**************************************************************************** - * Function: fdcan_ifdown - * - * Description: - * NuttX Callback: Stop the interface. - * - * Input Parameters: - * dev - Reference to the NuttX driver state structure - * - * Returned Value: - * None - * - * Assumptions: - * - ****************************************************************************/ - -static int fdcan_ifdown(struct net_driver_s *dev) -{ - struct stm32_fdcan_s *priv = - (struct stm32_fdcan_s *)dev->d_private; - - /* Disable CAN interrupts */ - - fdcan_shutdown(priv); - - /* Reset CAN */ - - fdcan_reset(priv); - - return OK; -} - -/**************************************************************************** - * Function: fdcan_txpoll - * - * Description: - * The transmitter is available, check if the network has any outgoing - * packets ready to send. This is a callback from devif_poll(). - * devif_poll() may be called: - * - * 1. When the preceding TX packet send is complete, - * 2. When the preceding TX packet send timesout and the interface is reset - * 3. During normal TX polling - * - * Input Parameters: - * dev - Reference to the NuttX driver state structure - * - * Returned Value: - * OK on success; a negated errno on failure - * - * Assumptions: - * May or may not be called from an interrupt handler. In either case, - * global interrupts are disabled, either explicitly or indirectly through - * interrupt handling logic. - * - ****************************************************************************/ - -static int fdcan_txpoll(struct net_driver_s *dev) -{ - struct stm32_fdcan_s *priv = - (struct stm32_fdcan_s *)dev->d_private; - - /* If the polling resulted in data that should be sent out on the network, - * the field d_len is set to a value > 0. - */ - - if (priv->dev.d_len > 0) - { - fdcan_txdone(priv); - - /* Send the packet */ - - fdcan_send(priv); - - /* Check if there is room in the device to hold another packet. If - * not, return a non-zero value to terminate the poll. - */ - - if (fdcan_txready(priv) == false) - { - return -EBUSY; - } - } - - /* If zero is returned, the polling will continue until all connections - * have been examined. - */ - - return 0; -} - -/**************************************************************************** - * Function: fdcan_txavail_work - * - * Description: - * Perform an out-of-cycle poll on the worker thread. - * - * Input Parameters: - * arg - Reference to the NuttX driver state structure (cast to void*) - * - * Returned Value: - * None - * - * Assumptions: - * Called on the higher priority worker thread. - * - ****************************************************************************/ - -static void fdcan_txavail_work(void *arg) -{ - struct stm32_fdcan_s *priv = (struct stm32_fdcan_s *)arg; - - /* Ignore the notification if the interface is not yet up */ - - net_lock(); - if (priv->bifup) - { - /* Check if there is room in the hardware to hold another outgoing - * packet. - */ - - if (fdcan_txready(priv)) - { - /* No, there is space for another transfer. Poll the network for - * new XMIT data. - */ - - devif_poll(&priv->dev, fdcan_txpoll); - } - } - - net_unlock(); -} - -/**************************************************************************** - * Function: fdcan_txavail - * - * Description: - * Driver callback invoked when new TX data is available. This is a - * stimulus perform an out-of-cycle poll and, thereby, reduce the TX - * latency. - * - * Input Parameters: - * dev - Reference to the NuttX driver state structure - * - * Returned Value: - * None - * - * Assumptions: - * Called in normal user mode - * - ****************************************************************************/ - -static int fdcan_txavail(struct net_driver_s *dev) -{ - struct stm32_fdcan_s *priv = - (struct stm32_fdcan_s *)dev->d_private; - - /* Is our single work structure available? It may not be if there are - * pending interrupt actions and we will have to ignore the Tx - * availability action. - */ - - if (work_available(&priv->pollwork)) - { - /* Schedule to serialize the poll on the worker thread. */ - - fdcan_txavail_work(priv); - } - - return OK; -} - -/**************************************************************************** - * Function: fdcan_ioctl - * - * Description: - * PHY ioctl command handler - * - * Input Parameters: - * dev - Reference to the NuttX driver state structure - * cmd - ioctl command - * arg - Argument accompanying the command - * - * Returned Value: - * Zero (OK) on success; a negated errno value on failure. - * - * Assumptions: - * - ****************************************************************************/ - -#ifdef CONFIG_NETDEV_IOCTL -static int fdcan_netdev_ioctl(struct net_driver_s *dev, int cmd, - unsigned long arg); -{ - struct stm32_fdcan_s *priv = - (struct stm32_fdcan_s *)dev->d_private; - int ret = OK; - - DEBUGASSERT(priv); - - switch (cmd) - { - /* TODO */ - - default: - ret = -ENOTTY; - break; - } - - return ret; -} -#endif /* CONFIG_NETDEV_IOCTL */ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_cansockinitialize - * - * Description: - * Initialize the selected FDCAN port as CAN socket interface - * - * Input Parameters: - * Port number (for hardware that has multiple FDCAN interfaces) - * - * Returned Value: - * OK on success; Negated errno on failure. - * - ****************************************************************************/ - -int stm32_fdcansockinitialize(int port) -{ - struct stm32_fdcan_s *priv = NULL; - const struct stm32_config_s *config = NULL; - int ret = OK; - - ninfo("FDCAN%d\n", port); - - /* Select FDCAN peripheral to be initialized */ - -#ifdef CONFIG_STM32F0L0G0_FDCAN1 - if (port == FDCAN1) - { - /* Select the FDCAN1 device structure */ - - priv = &g_fdcan1priv; - config = &g_fdcan1const; - } - else -#endif - { - nerr("ERROR: Unsupported port %d\n", port); - ret = -EINVAL; - goto errout; - } - - /* Perform one time data initialization */ - - memset(priv, 0, sizeof(struct stm32_fdcan_s)); - priv->config = config; - - /* Set the initial bit timing. This might change subsequently - * due to IOCTL command processing. - */ - - priv->nbtp = config->nbtp; - priv->dbtp = config->dbtp; - - /* Initialize the driver structure */ - - priv->dev.d_ifup = fdcan_ifup; - priv->dev.d_ifdown = fdcan_ifdown; - priv->dev.d_txavail = fdcan_txavail; -#ifdef CONFIG_NETDEV_IOCTL - priv->dev.d_ioctl = fdcan_netdev_ioctl; -#endif - priv->dev.d_private = priv; - - /* Put the interface in the down state. This usually amounts to resetting - * the device and/or calling fdcan_ifdown(). - */ - - ninfo("callbacks done\n"); - - fdcan_ifdown(&priv->dev); - - /* Register the device with the OS so that socket IOCTLs can be performed */ - - ret = netdev_register(&priv->dev, NET_LL_CAN); - -errout: - return ret; -} - -/**************************************************************************** - * Name: arm_netinitialize - * - * Description: - * Initialize the CAN device interfaces. If there is more than one device - * interface in the chip, then board-specific logic will have to provide - * this function to determine which, if any, CAN interfaces should be - * initialized. - * - ****************************************************************************/ - -#if !defined(CONFIG_NETDEV_LATEINIT) -void arm_netinitialize(void) -{ -#ifdef CONFIG_STM32F0L0G0_CAN1 - stm32_fdcansockinitialize(FDCAN1); -#endif -} -#endif diff --git a/arch/arm/src/stm32f0l0g0/stm32_flash.c b/arch/arm/src/stm32f0l0g0/stm32_flash.c deleted file mode 100644 index 8e2d4b7dd592f..0000000000000 --- a/arch/arm/src/stm32f0l0g0/stm32_flash.c +++ /dev/null @@ -1,37 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_flash.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#if defined(CONFIG_STM32F0L0G0_STM32G0) || defined(CONFIG_STM32F0L0G0_STM32C0) -# include "stm32g0c0_flash.c" -#else -# error "Flash driver unsupported on selected chip." -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ diff --git a/arch/arm/src/stm32f0l0g0/stm32_flash.h b/arch/arm/src/stm32f0l0g0/stm32_flash.h deleted file mode 100644 index 1c670fa862c7a..0000000000000 --- a/arch/arm/src/stm32f0l0g0/stm32_flash.h +++ /dev/null @@ -1,67 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_flash.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_STM32_FLASH_H -#define __ARCH_ARM_SRC_STM32F0L0G0_STM32_FLASH_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include "chip.h" -#include "hardware/stm32_flash.h" - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#ifndef __ASSEMBLY__ - -#undef EXTERN -#if defined(__cplusplus) -# define EXTERN extern "C" -extern "C" -{ -#else -# define EXTERN extern -#endif - -void stm32_flash_getopt(uint32_t *opt); - -int stm32_flash_optmodify(uint32_t clear, uint32_t set); - -void stm32_flash_lock(void); - -void stm32_flash_unlock(void); - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ - -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_STM32_FLASH_H */ \ No newline at end of file diff --git a/arch/arm/src/stm32f0l0g0/stm32_gpio.c b/arch/arm/src/stm32f0l0g0/stm32_gpio.c deleted file mode 100644 index 19d50cf7637cc..0000000000000 --- a/arch/arm/src/stm32f0l0g0/stm32_gpio.c +++ /dev/null @@ -1,451 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_gpio.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include - -#include -#include -#include - -#include "arm_internal.h" -#include "chip.h" -#include "stm32_gpio.h" - -#if defined(CONFIG_STM32F0L0G0_HAVE_IP_EXTI_V1) -# include "hardware/stm32_syscfg.h" -#elif defined(CONFIG_STM32F0L0G0_HAVE_IP_EXTI_V2) -# include "hardware/stm32_exti.h" -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -static spinlock_t g_configgpio_lock = SP_UNLOCKED; - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/* Base addresses for each GPIO block */ - -const uint32_t g_gpiobase[STM32_NPORTS] = -{ -#if STM32_NPORTS > 0 - STM32_GPIOA_BASE, /* One GPIO ports, GPIOA */ -#endif -#if STM32_NPORTS > 1 - STM32_GPIOB_BASE, /* Two GPIO ports, GPIOA-B */ -#endif -#if STM32_NPORTS > 2 - STM32_GPIOC_BASE, /* Three GPIO ports, GPIOA-C */ -#endif -#if STM32_NPORTS > 3 - STM32_GPIOD_BASE, /* Four GPIO ports, GPIOA-D */ -#endif -#if defined(STM32_GPIOE_BASE) - STM32_GPIOE_BASE, /* GPIOE */ -#endif -#if defined(STM32_GPIOF_BASE) - STM32_GPIOF_BASE, /* GPIOF */ -#endif -#if defined(STM32_GPIOH_BASE) - STM32_GPIOH_BASE, /* GPIOH */ -#endif -}; - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Function: stm32_gpioinit - * - * Description: - * Based on configuration within the .config file, it does: - * - Remaps positions of alternative functions. - * - * Typically called from stm32_start(). - * - * Assumptions: - * This function is called early in the initialization sequence so that - * no mutual exclusion is necessary. - * - ****************************************************************************/ - -void stm32_gpioinit(void) -{ -} - -/**************************************************************************** - * Name: stm32_configgpio - * - * Description: - * Configure a GPIO pin based on bit-encoded description of the pin. - * Once it is configured as Alternative (GPIO_ALT|GPIO_CNF_AFPP|...) - * function, it must be unconfigured with stm32_unconfiggpio() with - * the same cfgset first before it can be set to non-alternative function. - * - * Returned Value: - * OK on success - * A negated errno value on invalid port, or when pin is locked as ALT - * function. - * - * To-Do: Auto Power Enable - ****************************************************************************/ - -int stm32_configgpio(uint32_t cfgset) -{ - uintptr_t base; - uint32_t regval; - uint32_t setting; - unsigned int regoffset; - unsigned int port; - unsigned int pin; - unsigned int pos; - unsigned int pinmode; - irqstate_t flags; - - /* Verify that this hardware supports the select GPIO port */ - - port = (cfgset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; - if (port >= STM32_NPORTS) - { - return -EINVAL; - } - - /* Get the port base address */ - - base = g_gpiobase[port]; - - /* Get the pin number and select the port configuration register for that - * pin - */ - - pin = (cfgset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT; - - /* Set up the mode register (and remember whether the pin mode) */ - - switch (cfgset & GPIO_MODE_MASK) - { - default: - case GPIO_INPUT: /* Input mode */ - pinmode = GPIO_MODER_INPUT; - break; - - case GPIO_OUTPUT: /* General purpose output mode */ - stm32_gpiowrite(cfgset, - (cfgset & GPIO_OUTPUT_SET) != 0); /* Set the initial output value */ - pinmode = GPIO_MODER_OUTPUT; - break; - - case GPIO_ALT: /* Alternate function mode */ - pinmode = GPIO_MODER_ALT; - break; - - case GPIO_ANALOG: /* Analog mode */ - pinmode = GPIO_MODER_ANALOG; - break; - } - - /* Interrupts must be disabled from here on out so that we have mutually - * exclusive access to all of the GPIO configuration registers. - */ - - flags = spin_lock_irqsave(&g_configgpio_lock); - - /* Now apply the configuration to the mode register */ - - regval = getreg32(base + STM32_GPIO_MODER_OFFSET); - regval &= ~GPIO_MODER_MASK(pin); - regval |= ((uint32_t)pinmode << GPIO_MODER_SHIFT(pin)); - putreg32(regval, base + STM32_GPIO_MODER_OFFSET); - - /* Set up the pull-up/pull-down configuration (all but analog pins) */ - - setting = GPIO_PUPDR_NONE; - if (pinmode != GPIO_MODER_ANALOG) - { - switch (cfgset & GPIO_PUPD_MASK) - { - default: - case GPIO_FLOAT: /* No pull-up, pull-down */ - break; - - case GPIO_PULLUP: /* Pull-up */ - setting = GPIO_PUPDR_PULLUP; - break; - - case GPIO_PULLDOWN: /* Pull-down */ - setting = GPIO_PUPDR_PULLDOWN; - break; - } - } - - regval = getreg32(base + STM32_GPIO_PUPDR_OFFSET); - regval &= ~GPIO_PUPDR_MASK(pin); - regval |= (setting << GPIO_PUPDR_SHIFT(pin)); - putreg32(regval, base + STM32_GPIO_PUPDR_OFFSET); - - /* Set the alternate function (Only alternate function pins) */ - - if (pinmode == GPIO_MODER_ALT) - { - setting = (cfgset & GPIO_AF_MASK) >> GPIO_AF_SHIFT; - } - else - { - setting = 0; - } - - if (pin < 8) - { - regoffset = STM32_GPIO_AFRL_OFFSET; - pos = pin; - } - else - { - regoffset = STM32_GPIO_AFRH_OFFSET; - pos = pin - 8; - } - - regval = getreg32(base + regoffset); - regval &= ~GPIO_AFR_MASK(pos); - regval |= (setting << GPIO_AFR_SHIFT(pos)); - putreg32(regval, base + regoffset); - - /* Set speed (Only outputs and alternate function pins) */ - - if (pinmode == GPIO_MODER_OUTPUT || pinmode == GPIO_MODER_ALT) - { - switch (cfgset & GPIO_SPEED_MASK) - { - default: -#if defined(STM32_GPIO_VERY_LOW_SPEED) - case GPIO_SPPED_VERYLOW: /* Very Low speed output */ - setting = GPIO_OSPEED_VERYLOW; - break; - - case GPIO_SPEED_LOW: /* Low speed output */ - setting = GPIO_OSPEED_LOW; - break; - - case GPIO_SPEED_MEDIUM: /* Medium speed output */ - setting = GPIO_OSPEED_MEDIUM; - break; - - case GPIO_SPEED_HIGH: /* High speed output */ - setting = GPIO_OSPEED_HIGH; - break; -#else - case GPIO_SPEED_LOW: /* Low speed output */ - setting = GPIO_OSPEED_LOW; - break; - - case GPIO_SPEED_MEDIUM: /* Medium speed output */ - setting = GPIO_OSPEED_MEDIUM; - break; - - case GPIO_SPEED_HIGH: /* High speed output */ - setting = GPIO_OSPEED_HIGH; - break; -#endif - } - } - else - { - setting = 0; - } - - regval = getreg32(base + STM32_GPIO_OSPEED_OFFSET); - regval &= ~GPIO_OSPEED_MASK(pin); - regval |= (setting << GPIO_OSPEED_SHIFT(pin)); - putreg32(regval, base + STM32_GPIO_OSPEED_OFFSET); - - /* Set push-pull/open-drain (Only outputs and alternate function pins) */ - - regval = getreg32(base + STM32_GPIO_OTYPER_OFFSET); - setting = GPIO_OTYPER_OD(pin); - - if ((pinmode == GPIO_MODER_OUTPUT || pinmode == GPIO_MODER_ALT) && - (cfgset & GPIO_OPENDRAIN) != 0) - { - regval |= setting; - } - else - { - regval &= ~setting; - } - - putreg32(regval, base + STM32_GPIO_OTYPER_OFFSET); - - /* Otherwise, it is an input pin. - * Should it configured as an EXTI interrupt? - */ - - if ((pinmode != GPIO_MODER_OUTPUT) && ((cfgset & GPIO_EXTI) != 0)) - { - uint32_t regaddr; - int shift; - -#if defined(CONFIG_STM32F0L0G0_HAVE_IP_EXTI_V1) - /* Set the bits in the SYSCFG EXTICR register */ - - regaddr = STM32_SYSCFG_EXTICR(pin); - regval = getreg32(regaddr); - shift = SYSCFG_EXTICR_EXTI_SHIFT(pin); - regval &= ~(SYSCFG_EXTICR_PORT_MASK << shift); - regval |= (((uint32_t)port) << shift); - - putreg32(regval, regaddr); -#elif defined(CONFIG_STM32F0L0G0_HAVE_IP_EXTI_V2) - /* Set the bits in the EXTI EXTICR register */ - - regaddr = STM32_EXTI_EXTICR(pin); - regval = getreg32(regaddr); - shift = EXTI_EXTICR_EXTI_SHIFT(pin); - regval &= ~(EXTI_EXTICR_PORT_MASK << shift); - regval |= (((uint32_t)port) << shift); - - putreg32(regval, regaddr); -#else -# error unknown EXTI IP core -#endif - } - - spin_unlock_irqrestore(&g_configgpio_lock, flags); - return OK; -} - -/**************************************************************************** - * Name: stm32_unconfiggpio - * - * Description: - * Unconfigure a GPIO pin based on bit-encoded description of the pin, set - * it into default HiZ state (and possibly mark it's unused) and unlock it - * whether it was previously selected as alternative function - * (GPIO_ALT|GPIO_CNF_AFPP|...). - * - * This is a safety function and prevents hardware from shocks, as - * unexpected write to the Timer Channel Output GPIO to fixed '1' or '0' - * while it should operate in PWM mode could produce excessive on-board - * currents and trigger over-current/alarm function. - * - * Returned Value: - * OK on success - * A negated errno value on invalid port - * - * To-Do: Auto Power Disable - ****************************************************************************/ - -int stm32_unconfiggpio(uint32_t cfgset) -{ - /* Reuse port and pin number and set it to default HiZ INPUT */ - - cfgset &= GPIO_PORT_MASK | GPIO_PIN_MASK; - cfgset |= GPIO_INPUT | GPIO_FLOAT; - - /* To-Do: Mark its unuse for automatic power saving options */ - - return stm32_configgpio(cfgset); -} - -/**************************************************************************** - * Name: stm32_gpiowrite - * - * Description: - * Write one or zero to the selected GPIO pin - * - ****************************************************************************/ - -void stm32_gpiowrite(uint32_t pinset, bool value) -{ - uint32_t base; - uint32_t bit; - unsigned int port; - unsigned int pin; - - port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; - if (port < STM32_NPORTS) - { - /* Get the port base address */ - - base = g_gpiobase[port]; - - /* Get the pin number */ - - pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT; - - /* Set or clear the output on the pin */ - - if (value) - { - bit = GPIO_BSRR_SET(pin); - } - else - { - bit = GPIO_BSRR_RESET(pin); - } - - putreg32(bit, base + STM32_GPIO_BSRR_OFFSET); - } -} - -/**************************************************************************** - * Name: stm32_gpioread - * - * Description: - * Read one or zero from the selected GPIO pin - * - ****************************************************************************/ - -bool stm32_gpioread(uint32_t pinset) -{ - uint32_t base; - unsigned int port; - unsigned int pin; - - port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; - if (port < STM32_NPORTS) - { - /* Get the port base address */ - - base = g_gpiobase[port]; - - /* Get the pin number and return the input state of that pin */ - - pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT; - return ((getreg32(base + STM32_GPIO_IDR_OFFSET) & (1 << pin)) != 0); - } - - return 0; -} diff --git a/arch/arm/src/stm32f0l0g0/stm32_gpio.h b/arch/arm/src/stm32f0l0g0/stm32_gpio.h deleted file mode 100644 index d4a90cc57128c..0000000000000 --- a/arch/arm/src/stm32f0l0g0/stm32_gpio.h +++ /dev/null @@ -1,367 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_gpio.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_STM32_GPIO_H -#define __ARCH_ARM_SRC_STM32F0L0G0_STM32_GPIO_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#ifndef __ASSEMBLY__ -# include -# include -#endif - -#include -#include - -#include "chip.h" -#include "hardware/stm32_gpio.h" -#include "hardware/stm32_pinmap.h" - -/**************************************************************************** - * Pre-Processor Declarations - ****************************************************************************/ - -/* Bit-encoded input to stm32_configgpio() */ - -/* Each port bit of the general-purpose I/O (GPIO) ports can be individually - * configured by software in several modes: - * - * - Input floating - * - Input pull-up - * - Input-pull-down - * - Output open-drain with pull-up or pull-down capability - * - Output push-pull with pull-up or pull-down capability - * - Alternate function push-pull with pull-up or pull-down capability - * - Alternate function open-drain with pull-up or pull-down capability - * - Analog - * - * 20-bit Encoding: 1111 1111 1100 0000 0000 - * 9876 5432 1098 7654 3210 - * ---- ---- ---- ---- ---- - * Inputs: MMUU .... ...X PPPP BBBB - * Outputs: MMUU .... FFOV PPPP BBBB - * Alternate Functions: MMUU .AAA FFO. PPPP BBBB - * Analog: MM.. .... .... PPPP BBBB - */ - -/* Mode: - * - * 1111 1111 1100 0000 0000 - * 9876 5432 1098 7654 3210 - * ---- ---- ---- ---- ---- - * MM.. .... .... .... .... - */ - -#define GPIO_MODE_SHIFT (18) /* Bits 18-19: GPIO port mode */ -#define GPIO_MODE_MASK (3 << GPIO_MODE_SHIFT) -# define GPIO_INPUT (0 << GPIO_MODE_SHIFT) /* Input mode */ -# define GPIO_OUTPUT (1 << GPIO_MODE_SHIFT) /* General purpose output mode */ -# define GPIO_ALT (2 << GPIO_MODE_SHIFT) /* Alternate function mode */ -# define GPIO_ANALOG (3 << GPIO_MODE_SHIFT) /* Analog mode */ - -/* Input/output pull-ups/downs (not used with analog): - * - * 1111 1111 1100 0000 0000 - * 9876 5432 1098 7654 3210 - * ---- ---- ---- ---- ---- - * ..UU .... .... .... .... - */ - -#define GPIO_PUPD_SHIFT (16) /* Bits 16-17: Pull-up/pull down */ -#define GPIO_PUPD_MASK (3 << GPIO_PUPD_SHIFT) -# define GPIO_FLOAT (0 << GPIO_PUPD_SHIFT) /* No pull-up, pull-down */ -# define GPIO_PULLUP (1 << GPIO_PUPD_SHIFT) /* Pull-up */ -# define GPIO_PULLDOWN (2 << GPIO_PUPD_SHIFT) /* Pull-down */ - -/* Alternate Functions: - * - * 1111 1111 1100 0000 0000 - * 9876 5432 1098 7654 3210 - * ---- ---- ---- ---- ---- - * .... .AAA .... .... .... - */ - -#define GPIO_AF_SHIFT (12) /* Bits 12-14: Alternate function */ -#define GPIO_AF_MASK (7 << GPIO_AF_SHIFT) -# define GPIO_AF(n) ((n) << GPIO_AF_SHIFT) -# define GPIO_AF0 (0 << GPIO_AF_SHIFT) -# define GPIO_AF1 (1 << GPIO_AF_SHIFT) -# define GPIO_AF2 (2 << GPIO_AF_SHIFT) -# define GPIO_AF3 (3 << GPIO_AF_SHIFT) -# define GPIO_AF4 (4 << GPIO_AF_SHIFT) -# define GPIO_AF5 (5 << GPIO_AF_SHIFT) -# define GPIO_AF6 (6 << GPIO_AF_SHIFT) -# define GPIO_AF7 (7 << GPIO_AF_SHIFT) - -/* Output/Alt function frequency selection: - * - * 1111 1111 1100 0000 0000 - * 9876 5432 1098 7654 3210 - * ---- ---- ---- ---- ---- - * .... .... FF.. .... .... - */ - -#define GPIO_SPEED_SHIFT (10) /* Bits 10-11: GPIO frequency selection */ -#define GPIO_SPEED_MASK (3 << GPIO_SPEED_SHIFT) - -#if defined(STM32_GPIO_VERY_LOW_SPEED) -# define GPIO_SPPED_VERYLOW (0 << GPIO_SPEED_SHIFT) /* 400 kHz Very low speed */ -# define GPIO_SPEED_LOW (1 << GPIO_SPEED_SHIFT) /* 2 MHz Low speed output */ -# define GPIO_SPEED_MEDIUM (2 << GPIO_SPEED_SHIFT) /* 10 MHz Medium speed output */ -# define GPIO_SPEED_HIGH (3 << GPIO_SPEED_SHIFT) /* 40 MHz High speed output */ -#else -# define GPIO_SPEED_LOW (0 << GPIO_SPEED_SHIFT) /* 2 MHz Low speed output */ -# define GPIO_SPEED_MEDIUM (1 << GPIO_SPEED_SHIFT) /* 10 MHz Medium speed output */ -# define GPIO_SPEED_HIGH (3 << GPIO_SPEED_SHIFT) /* 50 MHz High speed output */ -#endif - -/* Output/Alt function type selection: - * - * 1111 1111 1100 0000 0000 - * 9876 5432 1098 7654 3210 - * ---- ---- ---- ---- ---- - * .... .... ..O. .... .... - */ - -#define GPIO_OPENDRAIN (1 << 9) /* Bit9: 1=Open-drain output */ -#define GPIO_PUSHPULL (0) /* Bit9: 0=Push-pull output */ - -/* If the pin is a GPIO digital output, then this identifies the initial - * output value. - * If the pin is an input, this bit is overloaded to provide the qualifier - * to distinguish input pull-up and -down: - * - * 1111 1111 1100 0000 0000 - * 9876 5432 1098 7654 3210 - * ---- ---- ---- ---- ---- - * .... .... ...V .... .... - */ - -#define GPIO_OUTPUT_SET (1 << 8) /* Bit 8: If output, initial value of output */ -#define GPIO_OUTPUT_CLEAR (0) - -/* External interrupt selection (GPIO inputs only): - * - * 1111 1111 1100 0000 0000 - * 9876 5432 1098 7654 3210 - * ---- ---- ---- ---- ---- - * .... .... ...X .... .... - */ - -#define GPIO_EXTI (1 << 8) /* Bit 8: Configure as EXTI interrupt */ - -/* This identifies the GPIO port: - * - * 1111 1111 1100 0000 0000 - * 9876 5432 1098 7654 3210 - * ---- ---- ---- ---- ---- - * .... .... .... PPPP .... - */ - -#define GPIO_PORT_SHIFT (4) /* Bit 4-7: Port number */ -#define GPIO_PORT_MASK (15 << GPIO_PORT_SHIFT) -# define GPIO_PORTA (0 << GPIO_PORT_SHIFT) /* GPIOA */ -# define GPIO_PORTB (1 << GPIO_PORT_SHIFT) /* GPIOB */ -# define GPIO_PORTC (2 << GPIO_PORT_SHIFT) /* GPIOC */ -# define GPIO_PORTD (3 << GPIO_PORT_SHIFT) /* GPIOD */ -#if defined (CONFIG_STM32F0L0G0_STM32F03X) -# define GPIO_PORTF (4 << GPIO_PORT_SHIFT) /* GPIOF */ -#else -# define GPIO_PORTE (4 << GPIO_PORT_SHIFT) /* GPIOE */ -#if defined (CONFIG_ARCH_CHIP_STM32L0) -# define GPIO_PORTH (5 << GPIO_PORT_SHIFT) /* GPIOH */ -#else -# define GPIO_PORTF (5 << GPIO_PORT_SHIFT) /* GPIOF */ -#endif -#endif - -/* This identifies the bit in the port: - * - * 1111 1111 1100 0000 0000 - * 9876 5432 1098 7654 3210 - * ---- ---- ---- ---- ---- - * .... .... .... .... BBBB - */ - -#define GPIO_PIN_SHIFT (0) /* Bits 0-3: GPIO number: 0-15 */ -#define GPIO_PIN_MASK (15 << GPIO_PIN_SHIFT) -# define GPIO_PIN0 (0 << GPIO_PIN_SHIFT) -# define GPIO_PIN1 (1 << GPIO_PIN_SHIFT) -# define GPIO_PIN2 (2 << GPIO_PIN_SHIFT) -# define GPIO_PIN3 (3 << GPIO_PIN_SHIFT) -# define GPIO_PIN4 (4 << GPIO_PIN_SHIFT) -# define GPIO_PIN5 (5 << GPIO_PIN_SHIFT) -# define GPIO_PIN6 (6 << GPIO_PIN_SHIFT) -# define GPIO_PIN7 (7 << GPIO_PIN_SHIFT) -# define GPIO_PIN8 (8 << GPIO_PIN_SHIFT) -# define GPIO_PIN9 (9 << GPIO_PIN_SHIFT) -# define GPIO_PIN10 (10 << GPIO_PIN_SHIFT) -# define GPIO_PIN11 (11 << GPIO_PIN_SHIFT) -# define GPIO_PIN12 (12 << GPIO_PIN_SHIFT) -# define GPIO_PIN13 (13 << GPIO_PIN_SHIFT) -# define GPIO_PIN14 (14 << GPIO_PIN_SHIFT) -# define GPIO_PIN15 (15 << GPIO_PIN_SHIFT) - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -#ifndef __ASSEMBLY__ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/* Base addresses for each GPIO block */ - -EXTERN const uint32_t g_gpiobase[STM32_NPORTS]; - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_configgpio - * - * Description: - * Configure a GPIO pin based on bit-encoded description of the pin. - * Once it is configured as Alternative (GPIO_ALT|GPIO_CNF_AFPP|...) - * function, it must be unconfigured with stm32_unconfiggpio() with - * the same cfgset first before it can be set to non-alternative function. - * - * Returned Value: - * OK on success - * ERROR on invalid port, or when pin is locked as ALT function. - * - ****************************************************************************/ - -int stm32_configgpio(uint32_t cfgset); - -/**************************************************************************** - * Name: stm32_unconfiggpio - * - * Description: - * Unconfigure a GPIO pin based on bit-encoded description of the pin, set - * it into default HiZ state (and possibly mark it's unused) and unlock it - * whether it was previously selected as alternative function - * (GPIO_ALT|GPIO_CNF_AFPP|...). - * - * This is a safety function and prevents hardware from shocks, as - * unexpected write to the Timer Channel Output GPIO to fixed '1' or '0' - * while it should operate in PWM mode could produce excessive on-board - * currents and trigger over-current/alarm function. - * - * Returned Value: - * OK on success - * ERROR on invalid port - * - ****************************************************************************/ - -int stm32_unconfiggpio(uint32_t cfgset); - -/**************************************************************************** - * Name: stm32_gpiowrite - * - * Description: - * Write one or zero to the selected GPIO pin - * - ****************************************************************************/ - -void stm32_gpiowrite(uint32_t pinset, bool value); - -/**************************************************************************** - * Name: stm32_gpioread - * - * Description: - * Read one or zero from the selected GPIO pin - * - ****************************************************************************/ - -bool stm32_gpioread(uint32_t pinset); - -/**************************************************************************** - * Name: stm32_gpiosetevent - * - * Description: - * Sets/clears GPIO based event and interrupt triggers. - * - * Input Parameters: - * pinset - GPIO pin configuration - * risingedge - Enables interrupt on rising edges - * fallingedge - Enables interrupt on falling edges - * event - Generate event when set - * func - When non-NULL, generate interrupt - * arg - Argument passed to the interrupt callback - * - * Returned Value: - * Zero (OK) is returned on success, otherwise a negated errno value is - * returned to indicate the nature of the failure. - * - ****************************************************************************/ - -int stm32_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, - bool event, xcpt_t func, void *arg); - -/**************************************************************************** - * Function: stm32_dumpgpio - * - * Description: - * Dump all GPIO registers associated with the provided base address - * - ****************************************************************************/ - -#ifdef CONFIG_DEBUG_FEATURES -int stm32_dumpgpio(uint32_t pinset, const char *msg); -#else -# define stm32_dumpgpio(p,m) -#endif - -/**************************************************************************** - * Function: stm32_gpioinit - * - * Description: - * Based on configuration within the .config file, it does: - * - Remaps positions of alternative functions. - * - * Typically called from stm32_start(). - * - ****************************************************************************/ - -void stm32_gpioinit(void); - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_STM32_GPIO_H */ diff --git a/arch/arm/src/stm32f0l0g0/stm32_hsi48.c b/arch/arm/src/stm32f0l0g0/stm32_hsi48.c deleted file mode 100644 index 9902f196f26b0..0000000000000 --- a/arch/arm/src/stm32f0l0g0/stm32_hsi48.c +++ /dev/null @@ -1,187 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_hsi48.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "arm_internal.h" -#include "chip.h" -#include "hardware/stm32_rcc.h" -#include "hardware/stm32_crs.h" - -#include "stm32_hsi48.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#if defined(CONFIG_ARCH_CHIP_STM32F0) -# define STM32_HSI48_REG STM32_RCC_CR2 -# define STM32_HSI48ON RCC_CR2_HSI48ON -# define STM32_HSI48RDY RCC_CR2_HSI48RDY -#elif defined(CONFIG_ARCH_CHIP_STM32L0) -# define STM32_HSI48_REG STM32_RCC_CRRCR -# define STM32_HSI48ON RCC_CRRCR_HSI48ON -# define STM32_HSI48RDY RCC_CRRCR_HSI48RDY -#elif defined(CONFIG_ARCH_CHIP_STM32G0) -# define STM32_HSI48_REG STM32_RCC_CR -# define STM32_HSI48ON RCC_CR_HSI48ON -# define STM32_HSI48RDY RCC_CR_HSI48RDY -#else -# error "Unsupported STM32F0/L0 HSI48" -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_enable_hsi48 - * - * Description: - * On STM32F04x, STM32F07x and STM32F09x devices only, the HSI48 clock - * signal is generated from an internal 48 MHz RC oscillator and can be - * used directly as a system clock or divided and be used as PLL input. - * - * The internal 48MHz RC oscillator is mainly dedicated to provide a high - * precision clock to the USB peripheral by means of a special Clock - * Recovery System (CRS) circuitry, which could use the USB SOF signal or - * the LSE or an external signal to automatically adjust the oscillator - * frequency on-fly, in a very small steps. This oscillator can also be - * used as a system clock source when the system is in run mode; it will - * be disabled as soon as the system enters in Stop or Standby mode. When - * the CRS is not used, the HSI48 RC oscillator runs on its default - * frequency which is subject to manufacturing process variations. - * - * Input Parameters: - * Identifies the synchronization source for the HSI48. When used as the - * USB source clock, this must be set to SYNCSRC_USB. - * - * Returned Value: - * None - * - ****************************************************************************/ - -void stm32_enable_hsi48(enum syncsrc_e syncsrc) -{ - uint32_t regval; - - /* Enable the HSI48 clock. - * - * The HSI48 RC can be switched on and off using the HSI48ON bit in the - * Clock control register (RCC_CR). - * - * The USB clock may be derived from either the PLL clock or from the - * HSI48 clock. This oscillator will be also automatically enabled (by - * hardware forcing HSI48ON bit to one) as soon as it is chosen as a clock - * source for the USB and the peripheral is - * enabled. - */ - - regval = getreg32(STM32_HSI48_REG); - regval |= STM32_HSI48ON; - putreg32(regval, STM32_HSI48_REG); - - /* Wait for the HSI48 clock to stabilize */ - - while ((getreg32(STM32_HSI48_REG) & STM32_HSI48RDY) == 0); - - /* Return if no synchronization */ - - if (syncsrc == SYNCSRC_NONE) - { - return; - } - - /* The CRS synchronization (SYNC) source, selectable through the CRS_CFGR - * register, can be the signal from the external CRS_SYNC pin, the LSE - * clock or the USB SOF signal. - */ - - regval = getreg32(STM32_CRS_CFGR); - regval &= ~CRS_CFGR_SYNCSRC_MASK; - - switch (syncsrc) - { - default: - case SYNCSRC_GPIO: /* GPIO selected as SYNC signal source */ - regval |= CRS_CFGR_SYNCSRC_GPIO; - break; - - case SYNCSRC_LSE: /* LSE selected as SYNC signal source */ - regval |= CRS_CFGR_SYNCSRC_LSE; - break; - - case SYNCSRC_USB: /* USB SOF selected as SYNC signal source */ - regval |= CRS_CFGR_SYNCSRC_USBSOF; - break; - } - - putreg32(regval, STM32_CRS_CFGR); - - /* Set the AUTOTRIMEN bit the CRS_CR register to enables the automatic - * hardware adjustment of TRIM bits according to the measured frequency - * error between the selected SYNC event. - */ - - regval = getreg32(STM32_CRS_CR); - regval |= CRS_CR_AUTOTRIMEN; - putreg32(regval, STM32_CRS_CR); -} - -/**************************************************************************** - * Name: stm32_disable_hsi48 - * - * Description: - * Disable the HSI48 clock. - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -void stm32_disable_hsi48(void) -{ - uint32_t regval; - - /* Disable the HSI48 clock */ - - regval = getreg32(STM32_HSI48_REG); - regval &= ~STM32_HSI48ON; - putreg32(regval, STM32_HSI48_REG); - - /* Set other registers to the default settings. */ - - regval = getreg32(STM32_CRS_CFGR); - regval &= ~CRS_CFGR_SYNCSRC_MASK; - putreg32(regval, STM32_CRS_CFGR); - - regval = getreg32(STM32_CRS_CR); - regval &= ~CRS_CR_AUTOTRIMEN; - putreg32(regval, STM32_CRS_CR); -} diff --git a/arch/arm/src/stm32f0l0g0/stm32_hsi48.h b/arch/arm/src/stm32f0l0g0/stm32_hsi48.h deleted file mode 100644 index 37a6981ff5d5b..0000000000000 --- a/arch/arm/src/stm32f0l0g0/stm32_hsi48.h +++ /dev/null @@ -1,96 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_hsi48.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_STM32_HSI48_H -#define __ARCH_ARM_SRC_STM32F0L0G0_STM32_HSI48_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#ifdef CONFIG_STM32F0L0G0_HAVE_HSI48 - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -enum syncsrc_e -{ - SYNCSRC_NONE = 0, /* No SYNC signal */ - SYNCSRC_GPIO, /* GPIO selected as SYNC signal source */ - SYNCSRC_LSE, /* LSE selected as SYNC signal source */ - SYNCSRC_USB, /* USB SOF selected as SYNC signal source */ -}; - -/**************************************************************************** - * Public Functions Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_enable_hsi48 - * - * Description: - * On STM32F04x, STM32F07x and STM32F09x devices only, the HSI48 clock - * signal is generated from an internal 48 MHz RC oscillator and can be - * used directly as a system clock or divided and be used as PLL input. - * - * The internal 48MHz RC oscillator is mainly dedicated to provide a high - * precision clock to the USB peripheral by means of a special Clock - * Recovery System (CRS) circuitry, which could use the USB SOF signal or - * the LSE or an external signal to automatically adjust the oscillator - * frequency on-fly, in a very small steps. This oscillator can also be - * used as a system clock source when the system is in run mode; it will - * be disabled as soon as the system enters in Stop or Standby mode. When - * the CRS is not used, the HSI48 RC oscillator runs on its default - * frequency which is subject to manufacturing process variations. - * - * Input Parameters: - * Identifies the synchronization source for the HSI48. When used as the - * USB source clock, this must be set to SYNCSRC_USB. - * - * Returned Value: - * None - * - ****************************************************************************/ - -void stm32_enable_hsi48(enum syncsrc_e syncsrc); - -/**************************************************************************** - * Name: stm32_disable_hsi48 - * - * Description: - * Disable the HSI48 clock. - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -void stm32_disable_hsi48(void); - -#endif /* CONFIG_STM32F0L0G0_HAVE_HSI48 */ -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_STM32_HSI48_H */ diff --git a/arch/arm/src/stm32f0l0g0/stm32_i2c.c b/arch/arm/src/stm32f0l0g0/stm32_i2c.c deleted file mode 100644 index 1991004a026a0..0000000000000 --- a/arch/arm/src/stm32f0l0g0/stm32_i2c.c +++ /dev/null @@ -1,2814 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_i2c.c - * - * SPDX-License-Identifier: BSD-3-Clause - * SPDX-FileCopyrightText: 2011 Uros Platise. All rights reserved. - * SPDX-FileCopyrightText: 2016-2017 Gregory Nutt. All rights reserved. - * SPDX-FileCopyrightText: 2016 Doug Vetter. All rights reserved. - * SPDX-FileContributor: Uros Platise - * SPDX-FileContributor: Gregory Nutt - * SPDX-FileContributor: John Wharington - * SPDX-FileContributor: David Sidrane - * SPDX-FileContributor: Bob Feretich - * SPDX-FileContributor: Doug Vetter - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -/* -------------------------------------------------------------------------- - * - * STM32 I2C IPv2 I2C Driver - * - * Supports: - * - Master operation: - * Standard-mode (up to 100 kHz) - * Fast-mode (up to 400 kHz) - * Fast-mode Plus (up to 1 MHz) - * fI2CCLK clock source selection is based on STM32_RCC_DCKCFGR2_I2CxSRC - * being set to HSI and the calculations are based on - * STM32_HSI_FREQUENCY of 16mHz - * - * - Multiple instances (shared bus) - * - Interrupt based operation - * - RELOAD support - * - * Unsupported, possible future work: - * - More effective error reporting to higher layers - * - Slave operation - * - Support of fI2CCLK frequencies other than 16Mhz - * - Polled operation (code present but untested) - * - SMBus support - * - Multi-master support - * - IPMI - * - * Test Environment: - * - * - B-L072Z-LRWAN1 - * - * Operational Status: - * - * All supported features have been tested and found to be operational. - * - * Although the RELOAD capability has been tested as it was required to - * implement the I2C_M_NOSTART flag on F3 hardware, the associated - * logic to support the transfer messages with more than 255 byte - * payloads has not been tested as the author lacked access to a real - * device supporting these types of transfers. - * - * Performance Benchmarks: TBD - * - * Time to transfer two messages, each a byte in length, in addition to - * the START condition, in interrupt mode: - * - * DEBUG enabled (development): TBDms - * Excessive delay here is caused by printing to the console and - * is of no concern. - * - * DEBUG disabled (production): TBSus - * Between Messages: TBDus - * Between Bytes: TBDus - * - * Implementation: - * - * - Device: structure as defined by the nuttx/i2c/i2c.h - * - * - Instance: represents each individual access to the I2C driver, obtained - * by the i2c_init(); it extends the Device structure from the - * nuttx/i2c/i2c.h; - * Instance points to OPS, to common I2C Hardware private data and - * contains its own private data including frequency, address and mode of - * operation. - * - * - Private: Private data of an I2C Hardware - * - * High Level Functional Description - * - * This driver works with I2C "messages" (struct i2c_msg_s), which carry a - * buffer intended to transfer data to, or store data read from, the I2C bus. - * - * As the hardware can only transmit or receive one byte at a time the basic - * job of the driver (and the ISR specifically) is to process each message in - * the order they are stored in the message list, one byte at a time. When - * no messages are left the ISR exits and returns the result to the caller. - * - * The order of the list of I2C messages provided to the driver is important - * and dependent upon the hardware in use. A typical I2C transaction between - * the F3 as an I2C Master and some other IC as a I2C Slave requires two - * messages that communicate the: - * - * 1) Subaddress (register offset on the slave device) - * 2) Data sent to or read from the device - * - * These messages will typically be one byte in length but may be up to 2^31 - * bytes in length. Incidentally, the maximum length is limited only because - * i2c_msg_s.length is a signed int for some odd reason. - * - * Interrupt mode relies on the following interrupt events: - * - * TXIS - Transmit interrupt - * (data transmitted to bus and acknowledged) - * NACKF - Not Acknowledge Received - * (data transmitted to bus and NOT acknowledged) - * RXNE - Receive interrupt - * (data received from bus) - * TC - Transfer Complete - * (All bytes in message transferred) - * TCR - Transfer Complete (Reload) - * (Current batch of bytes in message transferred) - * - * The driver currently supports Single Master mode only. Slave mode is not - * supported. Additionally, the driver runs in Software End Mode (AUTOEND - * disabled) so the driver is responsible for telling the hardware what to - * do at the end of a transfer. - * - * -------------------------------------------------------------------------- - * - * Configuration: - * - * To use this driver, enable the following configuration variable: - * - * CONFIG_STM32F0L0G0_I2C1 - * CONFIG_STM32F0L0G0_I2C2 - * CONFIG_STM32F0L0G0_I2C3 - * CONFIG_STM32F0L0G0_I2C4 - * - * To configure the ISR timeout using fixed values - * (CONFIG_STM32F0L0G0_I2C_DYNTIMEO=n): - * - * CONFIG_STM32F0L0G0_I2CTIMEOSEC (Timeout in seconds) - * CONFIG_STM32F0L0G0_I2CTIMEOMS (Timeout in milliseconds) - * CONFIG_STM32F0L0G0_I2CTIMEOTICKS (Timeout in ticks) - * - * To configure the ISR timeout using dynamic values - * (CONFIG_STM32F0L0G0_I2C_DYNTIMEO=y): - * - * CONFIG_STM32F0L0G0_I2C_DYNTIMEO_USECPERBYTE - * (Timeout in microseconds per byte) - * CONFIG_STM32F0L0G0_I2C_DYNTIMEO_STARTSTOP - * (Timeout for start/stop in milliseconds) - * - * Debugging output enabled with: - * - * CONFIG_DEBUG_FEATURES and CONFIG_DEBUG_I2C_{ERROR|WARN|INFO} - * - * ISR Debugging output may be enabled with: - * - * CONFIG_DEBUG_FEATURES and CONFIG_DEBUG_I2C_INFO - * - * -------------------------------------------------------------------------- - * - * References: - * - * RM0431: - * ST STM322xxx and STM323xxx Reference Manual - * Document ID: DocID029480 Revision 1, Jan 2017. - * - * RM0316: - * ST STM326xxx and STM327xxx Reference Manual - * Document ID: DocID028270 Revision 2, April 2016. - * - * DATASHEET: - * ST STM3277xx/STM3278Ax/STM3279x Datasheet - * Document ID: DocID028294, Revision 3, May 2016. - * - * ERRATA: - * STM326xxx/STM327xxx Errata sheet Rev A device limitations - * Document ID: DocID028806, Revision 2, April 2016. - * - * I2CSPEC: - * I2C Bus Specification and User Manual - * Document ID: UM10204, Revision 6, April 2014. - * - * -------------------------------------------------------------------------- - */ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include - -#include - -#include "arm_internal.h" -#include "stm32_rcc.h" -#include "stm32_i2c.h" -#include "stm32_gpio.h" - -/* At least one I2C peripheral must be enabled */ - -#if defined(CONFIG_STM32F0L0G0_I2C1) || defined(CONFIG_STM32F0L0G0_I2C2) || \ - defined(CONFIG_STM32F0L0G0_I2C3) || defined(CONFIG_STM32F0L0G0_I2C4) - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#undef INVALID_CLOCK_SOURCE - -#warning TODO: check I2C clock source and clock frequency. It must be HSI! - -/* CONFIG_I2C_POLLED may be set so that I2C interrupts will not be used. - * Instead, CPU-intensive polling will be used. - */ - -/* Interrupt wait timeout in seconds and milliseconds */ - -#if !defined(CONFIG_STM32F0L0G0_I2CTIMEOSEC) && !defined(CONFIG_STM32F0L0G0_I2CTIMEOMS) -# define CONFIG_STM32F0L0G0_I2CTIMEOSEC 0 -# define CONFIG_STM32F0L0G0_I2CTIMEOMS 500 /* Default is 500 milliseconds */ -# warning "Using Default 500 Ms Timeout" -#elif !defined(CONFIG_STM32F0L0G0_I2CTIMEOSEC) -# define CONFIG_STM32F0L0G0_I2CTIMEOSEC 0 /* User provided milliseconds */ -#elif !defined(CONFIG_STM32F0L0G0_I2CTIMEOMS) -# define CONFIG_STM32F0L0G0_I2CTIMEOMS 0 /* User provided seconds */ -#endif - -/* Interrupt wait time timeout in system timer ticks */ - -#ifndef CONFIG_STM32F0L0G0_I2CTIMEOTICKS -# define CONFIG_STM32F0L0G0_I2CTIMEOTICKS \ - (SEC2TICK(CONFIG_STM32F0L0G0_I2CTIMEOSEC) + MSEC2TICK(CONFIG_STM32F0L0G0_I2CTIMEOMS)) -#endif - -#ifndef CONFIG_STM32F0L0G0_I2C_DYNTIMEO_STARTSTOP -# define CONFIG_STM32F0L0G0_I2C_DYNTIMEO_STARTSTOP TICK2USEC(CONFIG_STM32F0L0G0_I2CTIMEOTICKS) -#endif - -/* Macros to convert a I2C pin to a GPIO output */ - -#define I2C_OUTPUT (GPIO_OUTPUT | GPIO_FLOAT | GPIO_OPENDRAIN |\ - GPIO_SPEED_50MHz | GPIO_OUTPUT_SET) - -#define MKI2C_OUTPUT(p) (((p) & (GPIO_PORT_MASK | GPIO_PIN_MASK)) | I2C_OUTPUT) - -#define I2C_CR1_TXRX (I2C_CR1_RXIE | I2C_CR1_TXIE) -#define I2C_CR1_ALLINTS (I2C_CR1_TXRX | I2C_CR1_TCIE | I2C_CR1_ERRIE) - -/* Unused bit in I2c_ISR used to communicate a bad state has occurred in - * the isr processing - */ - -#define I2C_INT_BAD_STATE 0x8000000 - -/* I2C event tracing - * - * To enable tracing statements which show the details of the state machine - * enable the following configuration variable: - * - * CONFIG_I2C_TRACE - * - * Note: This facility uses syslog, which sends output to the console by - * default. No other debug configuration variables are required. - */ - -#ifndef CONFIG_I2C_TRACE -# define stm32_i2c_tracereset(p) -# define stm32_i2c_tracenew(p,s) -# define stm32_i2c_traceevent(p,e,a) -# define stm32_i2c_tracedump(p) -#endif - -#ifndef CONFIG_I2C_NTRACE -# define CONFIG_I2C_NTRACE 32 -#endif - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/* Interrupt state */ - -enum stm32_intstate_e -{ - INTSTATE_IDLE = 0, /* No I2C activity */ - INTSTATE_WAITING, /* Waiting for completion of interrupt activity */ - INTSTATE_DONE, /* Interrupt activity complete */ -}; - -/* Trace events */ - -enum stm32_trace_e -{ - I2CEVENT_NONE = 0, - I2CEVENT_STATE_ERROR, - I2CEVENT_ISR_SHUTDOWN, - I2CEVENT_ISR_CALL, - I2CEVENT_ISR_EMPTY_CALL, - I2CEVENT_MSG_HANDLING, - I2CEVENT_POLL_NOT_READY, - I2CEVENT_EMPTY_MSG, - I2CEVENT_START, - I2CEVENT_ADDRESS_ACKED, - I2CEVENT_ADDRESS_NACKED, - I2CEVENT_NACK, - I2CEVENT_READ, - I2CEVENT_READ_ERROR, - I2CEVENT_WRITE_TO_DR, - I2CEVENT_WRITE_STOP, - I2CEVENT_WRITE_RESTART, - I2CEVENT_WRITE_NO_RESTART, - I2CEVENT_WRITE_ERROR, - I2CEVENT_WRITE_FLAG_ERROR, - I2CEVENT_TC_RESTART, - I2CEVENT_TC_NO_RESTART -}; - -/* Trace data */ - -struct stm32_trace_s -{ - uint32_t status; /* I2C 32-bit SR2|SR1 status */ - uint32_t count; /* Interrupt count when status change */ - enum stm32_intstate_e event; /* Last event that occurred with this status */ - uint32_t parm; /* Parameter associated with the event */ - clock_t time; /* First of event or first status */ -}; - -/* I2C Device hardware configuration */ - -struct stm32_i2c_config_s -{ - uint32_t base; /* I2C base address */ - uint32_t clk_bit; /* Clock enable bit */ - uint32_t reset_bit; /* Reset bit */ - uint32_t scl_pin; /* GPIO configuration for SCL as SCL */ - uint32_t sda_pin; /* GPIO configuration for SDA as SDA */ -#ifndef CONFIG_I2C_POLLED - uint32_t irq; /* IRQ */ -#endif -}; - -/* I2C Device Private Data */ - -struct stm32_i2c_priv_s -{ - /* Port configuration */ - - const struct stm32_i2c_config_s *config; - - int refs; /* Reference count */ - - mutex_t lock; /* Mutual exclusion mutex */ -#ifndef CONFIG_I2C_POLLED - sem_t sem_isr; /* Interrupt wait semaphore */ -#endif - volatile uint8_t intstate; /* Interrupt handshake (see enum stm32_intstate_e) */ - - uint8_t msgc; /* Message count */ - struct i2c_msg_s *msgv; /* Message list */ - uint8_t *ptr; /* Current message buffer */ - uint32_t frequency; /* Current I2C frequency */ - int dcnt; /* Current message bytes remaining to transfer */ - uint16_t flags; /* Current message flags */ - bool astart; /* START sent */ - - /* I2C trace support */ - -#ifdef CONFIG_I2C_TRACE - int tndx; /* Trace array index */ - clock_t start_time; /* Time when the trace was started */ - - /* The actual trace data */ - - struct stm32_trace_s trace[CONFIG_I2C_NTRACE]; -#endif - - uint32_t status; /* End of transfer SR2|SR1 status */ - -#ifdef CONFIG_PM - struct pm_callback_s pm_cb; /* PM callbacks */ -#endif -}; - -/* I2C Device, Instance */ - -struct stm32_i2c_inst_s -{ - const struct i2c_ops_s *ops; /* Standard I2C operations */ - struct stm32_i2c_priv_s *priv; /* Common driver private data structure */ -}; - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -static inline uint16_t stm32_i2c_getreg(struct stm32_i2c_priv_s *priv, - uint8_t offset); -static inline void stm32_i2c_putreg(struct stm32_i2c_priv_s *priv, - uint8_t offset, uint16_t value); -static inline void stm32_i2c_putreg32(struct stm32_i2c_priv_s *priv, - uint8_t offset, uint32_t value); -static inline void stm32_i2c_modifyreg32(struct stm32_i2c_priv_s *priv, - uint8_t offset, uint32_t clearbits, - uint32_t setbits); -#ifdef CONFIG_STM32F0L0G0_I2C_DYNTIMEO -static uint32_t stm32_i2c_toticks(int msgc, struct i2c_msg_s *msgs); -#endif /* CONFIG_STM32F0L0G0_I2C_DYNTIMEO */ -static inline int stm32_i2c_sem_waitdone(struct stm32_i2c_priv_s *priv); -static inline void stm32_i2c_sem_waitstop(struct stm32_i2c_priv_s *priv); -#ifdef CONFIG_I2C_TRACE -static void stm32_i2c_tracereset(struct stm32_i2c_priv_s *priv); -static void stm32_i2c_tracenew(struct stm32_i2c_priv_s *priv, - uint32_t status); -static void stm32_i2c_traceevent(struct stm32_i2c_priv_s *priv, - enum stm32_trace_e event, uint32_t parm); -static void stm32_i2c_tracedump(struct stm32_i2c_priv_s *priv); -#endif /* CONFIG_I2C_TRACE */ -static void stm32_i2c_setclock(struct stm32_i2c_priv_s *priv, - uint32_t frequency); -static inline void stm32_i2c_sendstart(struct stm32_i2c_priv_s *priv); -static inline void stm32_i2c_sendstop(struct stm32_i2c_priv_s *priv); -static inline -uint32_t stm32_i2c_getstatus(struct stm32_i2c_priv_s *priv); -static int stm32_i2c_isr_process(struct stm32_i2c_priv_s *priv); -#ifndef CONFIG_I2C_POLLED -static int stm32_i2c_isr(int irq, void *context, void *arg); -#endif -static int stm32_i2c_init(struct stm32_i2c_priv_s *priv); -static int stm32_i2c_deinit(struct stm32_i2c_priv_s *priv); - -static int stm32_i2c_process(struct i2c_master_s *dev, - struct i2c_msg_s *msgs, int count); -static int stm32_i2c_transfer(struct i2c_master_s *dev, - struct i2c_msg_s *msgs, int count); -#ifdef CONFIG_I2C_RESET -static int stm32_i2c_reset(struct i2c_master_s *dev); -#endif -#ifdef CONFIG_PM -static int stm32_i2c_pm_prepare(struct pm_callback_s *cb, - int domain, enum pm_state_e pmstate); -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -#ifdef CONFIG_STM32F0L0G0_I2C1 -static const struct stm32_i2c_config_s stm32_i2c1_config = -{ - .base = STM32_I2C1_BASE, - .clk_bit = RCC_APB1ENR_I2C1EN, - .reset_bit = RCC_APB1RSTR_I2C1RST, - .scl_pin = GPIO_I2C1_SCL, - .sda_pin = GPIO_I2C1_SDA, -#ifndef CONFIG_I2C_POLLED - .irq = STM32_IRQ_I2C1 -#endif -}; - -static struct stm32_i2c_priv_s stm32_i2c1_priv = -{ - .config = &stm32_i2c1_config, - .refs = 0, - .lock = NXMUTEX_INITIALIZER, -#ifndef CONFIG_I2C_POLLED - .sem_isr = SEM_INITIALIZER(0), -#endif - .intstate = INTSTATE_IDLE, - .msgc = 0, - .msgv = NULL, - .ptr = NULL, - .frequency = 0, - .dcnt = 0, - .flags = 0, - .status = 0, -#ifdef CONFIG_PM - .pm_cb.prepare = stm32_i2c_pm_prepare, -#endif -}; -#endif - -#ifdef CONFIG_STM32F0L0G0_I2C2 -static const struct stm32_i2c_config_s stm32_i2c2_config = -{ - .base = STM32_I2C2_BASE, - .clk_bit = RCC_APB1ENR_I2C2EN, - .reset_bit = RCC_APB1RSTR_I2C2RST, - .scl_pin = GPIO_I2C2_SCL, - .sda_pin = GPIO_I2C2_SDA, -#ifndef CONFIG_I2C_POLLED - .irq = STM32_IRQ_I2C2 -#endif -}; - -static struct stm32_i2c_priv_s stm32_i2c2_priv = -{ - .config = &stm32_i2c2_config, - .refs = 0, - .lock = NXMUTEX_INITIALIZER, -#ifndef CONFIG_I2C_POLLED - .sem_isr = SEM_INITIALIZER(0), -#endif - .intstate = INTSTATE_IDLE, - .msgc = 0, - .msgv = NULL, - .ptr = NULL, - .frequency = 0, - .dcnt = 0, - .flags = 0, - .status = 0, -#ifdef CONFIG_PM - .pm_cb.prepare = stm32_i2c_pm_prepare, -#endif -}; -#endif - -#ifdef CONFIG_STM32F0L0G0_I2C3 -static const struct stm32_i2c_config_s stm32_i2c3_config = -{ - .base = STM32_I2C3_BASE, - .clk_bit = RCC_APB1ENR_I2C3EN, - .reset_bit = RCC_APB1RSTR_I2C3RST, - .scl_pin = GPIO_I2C3_SCL, - .sda_pin = GPIO_I2C3_SDA, -#ifndef CONFIG_I2C_POLLED - .irq = STM32_IRQ_I2C3 -#endif -}; - -static struct stm32_i2c_priv_s stm32_i2c3_priv = -{ - .config = &stm32_i2c3_config, - .refs = 0, - .lock = NXMUTEX_INITIALIZER, -#ifndef CONFIG_I2C_POLLED - .sem_isr = SEM_INITIALIZER(0), -#endif - .intstate = INTSTATE_IDLE, - .msgc = 0, - .msgv = NULL, - .ptr = NULL, - .frequency = 0, - .dcnt = 0, - .flags = 0, - .status = 0, -#ifdef CONFIG_PM - .pm_cb.prepare = stm32_i2c_pm_prepare, -#endif -}; -#endif - -#ifdef CONFIG_STM32F0L0G0_I2C4 -static const struct stm32_i2c_config_s stm32_i2c4_config = -{ - .base = STM32_I2C4_BASE, - .clk_bit = RCC_APB1ENR_I2C4EN, - .reset_bit = RCC_APB1RSTR_I2C4RST, - .scl_pin = GPIO_I2C4_SCL, - .sda_pin = GPIO_I2C4_SDA, -#ifndef CONFIG_I2C_POLLED - .irq = STM32_IRQ_I2C4 -#endif -}; - -static struct stm32_i2c_priv_s stm32_i2c4_priv = -{ - .config = &stm32_i2c4_config, - .refs = 0, - .lock = NXMUTEX_INITIALIZER, -#ifndef CONFIG_I2C_POLLED - .sem_isr = SEM_INITIALIZER(0), -#endif - .intstate = INTSTATE_IDLE, - .msgc = 0, - .msgv = NULL, - .ptr = NULL, - .frequency = 0, - .dcnt = 0, - .flags = 0, - .status = 0, -#ifdef CONFIG_PM - .pm_cb.prepare = stm32_i2c_pm_prepare, -#endif -}; -#endif - -/* Device Structures, Instantiation */ - -static const struct i2c_ops_s stm32_i2c_ops = -{ - .transfer = stm32_i2c_transfer, -#ifdef CONFIG_I2C_RESET - .reset = stm32_i2c_reset, -#endif -}; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_i2c_getreg - * - * Description: - * Get a 16-bit register value by offset - * - ****************************************************************************/ - -static inline uint16_t stm32_i2c_getreg(struct stm32_i2c_priv_s *priv, - uint8_t offset) -{ - return getreg16(priv->config->base + offset); -} - -/**************************************************************************** - * Name: stm32_i2c_getreg32 - * - * Description: - * Get a 32-bit register value by offset - * - ****************************************************************************/ - -static inline uint32_t stm32_i2c_getreg32(struct stm32_i2c_priv_s *priv, - uint8_t offset) -{ - return getreg32(priv->config->base + offset); -} - -/**************************************************************************** - * Name: stm32_i2c_putreg - * - * Description: - * Put a 16-bit register value by offset - * - ****************************************************************************/ - -static inline void stm32_i2c_putreg(struct stm32_i2c_priv_s *priv, - uint8_t offset, uint16_t value) -{ - putreg16(value, priv->config->base + offset); -} - -/**************************************************************************** - * Name: stm32_i2c_putreg32 - * - * Description: - * Put a 32-bit register value by offset - * - ****************************************************************************/ - -static inline void stm32_i2c_putreg32(struct stm32_i2c_priv_s *priv, - uint8_t offset, uint32_t value) -{ - putreg32(value, priv->config->base + offset); -} - -/**************************************************************************** - * Name: stm32_i2c_modifyreg32 - * - * Description: - * Modify a 32-bit register value by offset - * - ****************************************************************************/ - -static inline void stm32_i2c_modifyreg32(struct stm32_i2c_priv_s *priv, - uint8_t offset, uint32_t clearbits, - uint32_t setbits) -{ - modifyreg32(priv->config->base + offset, clearbits, setbits); -} - -/**************************************************************************** - * Name: stm32_i2c_toticks - * - * Description: - * Return a micro-second delay based on the number of bytes left to be - * processed. - * - ****************************************************************************/ - -#ifdef CONFIG_STM32F0L0G0_I2C_DYNTIMEO -static uint32_t stm32_i2c_toticks(int msgc, struct i2c_msg_s *msgs) -{ - size_t bytecount = 0; - int i; - - /* Count the number of bytes left to process */ - - for (i = 0; i < msgc; i++) - { - bytecount += msgs[i].length; - } - - /* Then return a number of microseconds based on a user provided scaling - * factor. - */ - - return USEC2TICK(CONFIG_STM32F0L0G0_I2C_DYNTIMEO_USECPERBYTE * bytecount); -} -#endif - -/**************************************************************************** - * Name: stm32_i2c_enableinterrupts - * - * Description: - * Enable I2C interrupts - * - ****************************************************************************/ - -#ifndef CONFIG_I2C_POLLED -static inline void stm32_i2c_enableinterrupts(struct stm32_i2c_priv_s *priv) -{ - stm32_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, 0, - (I2C_CR1_TXRX | I2C_CR1_NACKIE)); -} -#endif - -/**************************************************************************** - * Name: stm32_i2c_sem_waitdone - * - * Description: - * Wait for a transfer to complete - * - * There are two versions of this function. The first is included when - * using interrupts while the second is used if polling - * (CONFIG_I2C_POLLED=y). - * - ****************************************************************************/ - -#ifndef CONFIG_I2C_POLLED -static inline int stm32_i2c_sem_waitdone(struct stm32_i2c_priv_s *priv) -{ - irqstate_t flags; - int ret; - - flags = enter_critical_section(); - - /* Enable I2C interrupts */ - - /* The TXIE and RXIE interrupts are enabled initially in stm32_i2c_process. - * The remainder of the interrupts, including error-related, are enabled - * here. - */ - - stm32_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, 0, - (I2C_CR1_ALLINTS & ~I2C_CR1_TXRX)); - - /* Signal the interrupt handler that we are waiting */ - - priv->intstate = INTSTATE_WAITING; - do - { - /* Wait until either the transfer is complete or the timeout expires */ - -#ifdef CONFIG_STM32F0L0G0_I2C_DYNTIMEO - ret = nxsem_tickwait_uninterruptible(&priv->sem_isr, - stm32_i2c_toticks(priv->msgc, priv->msgv)); -#else - ret = nxsem_tickwait_uninterruptible(&priv->sem_isr, - CONFIG_STM32F0L0G0_I2CTIMEOTICKS); -#endif - if (ret < 0) - { - /* Break out of the loop on irrecoverable errors. This would - * include timeouts and mystery errors reported by - * nxsem_tickwait_uninterruptible. - */ - - break; - } - } - - /* Loop until the interrupt level transfer is complete. */ - - while (priv->intstate != INTSTATE_DONE); - - /* Set the interrupt state back to IDLE */ - - priv->intstate = INTSTATE_IDLE; - - /* Disable I2C interrupts */ - - stm32_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, I2C_CR1_ALLINTS, 0); - - leave_critical_section(flags); - return ret; -} -#else -static inline int stm32_i2c_sem_waitdone(struct stm32_i2c_priv_s *priv) -{ - clock_t timeout; - clock_t start; - clock_t elapsed; - int ret; - - /* Get the timeout value */ - -#ifdef CONFIG_STM32F0L0G0_I2C_DYNTIMEO - timeout = stm32_i2c_toticks(priv->msgc, priv->msgv); -#else - timeout = CONFIG_STM32F0L0G0_I2CTIMEOTICKS; -#endif - - /* Signal the interrupt handler that we are waiting. NOTE: Interrupts - * are currently disabled but will be temporarily re-enabled below when - * nxsem_tickwait_uninterruptible() sleeps. - */ - - priv->intstate = INTSTATE_WAITING; - start = clock_systime_ticks(); - - do - { - /* Calculate the elapsed time */ - - elapsed = clock_systime_ticks() - start; - - /* Poll by simply calling the timer interrupt handler until it - * reports that it is done. - */ - - stm32_i2c_isr_process(priv); - } - - /* Loop until the transfer is complete. */ - - while (priv->intstate != INTSTATE_DONE && elapsed < timeout); - - i2cinfo("intstate: %d elapsed: %ld threshold: %ld" - " status: 0x%08" PRIx32 "\n", - priv->intstate, (long)elapsed, (long)timeout, priv->status); - - /* Set the interrupt state back to IDLE */ - - ret = priv->intstate == INTSTATE_DONE ? OK : -ETIMEDOUT; - priv->intstate = INTSTATE_IDLE; - return ret; -} -#endif - -/**************************************************************************** - * Name: stm32_i2c_set_7bit_address - * - * Description: - * - ****************************************************************************/ - -static inline void -stm32_i2c_set_7bit_address(struct stm32_i2c_priv_s *priv) -{ - stm32_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, I2C_CR2_SADD7_MASK, - ((priv->msgv->addr & 0x7f) << I2C_CR2_SADD7_SHIFT)); -} - -/**************************************************************************** - * Name: stm32_i2c_set_bytes_to_transfer - * - * Description: - * - ****************************************************************************/ - -static inline void -stm32_i2c_set_bytes_to_transfer(struct stm32_i2c_priv_s *priv, - uint8_t n_bytes) -{ - stm32_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, I2C_CR2_NBYTES_MASK, - (n_bytes << I2C_CR2_NBYTES_SHIFT)); -} - -/**************************************************************************** - * Name: stm32_i2c_set_write_transfer_dir - * - * Description: - * - ****************************************************************************/ - -static inline void -stm32_i2c_set_write_transfer_dir(struct stm32_i2c_priv_s *priv) -{ - stm32_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, I2C_CR2_RD_WRN, 0); -} - -/**************************************************************************** - * Name: stm32_i2c_set_read_transfer_dir - * - * Description: - * - ****************************************************************************/ - -static inline void -stm32_i2c_set_read_transfer_dir(struct stm32_i2c_priv_s *priv) -{ - stm32_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, 0, I2C_CR2_RD_WRN); -} - -/**************************************************************************** - * Name: stm32_i2c_enable_reload - * - * Description: - * - ****************************************************************************/ - -static inline void -stm32_i2c_enable_reload(struct stm32_i2c_priv_s *priv) -{ - stm32_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, 0, I2C_CR2_RELOAD); -} - -/**************************************************************************** - * Name: stm32_i2c_disable_reload - * - * Description: - * - ****************************************************************************/ - -static inline void -stm32_i2c_disable_reload(struct stm32_i2c_priv_s *priv) -{ - stm32_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, I2C_CR2_RELOAD, 0); -} - -/**************************************************************************** - * Name: stm32_i2c_sem_waitstop - * - * Description: - * Wait for a STOP to complete - * - ****************************************************************************/ - -static inline void stm32_i2c_sem_waitstop(struct stm32_i2c_priv_s *priv) -{ - clock_t start; - clock_t elapsed; - clock_t timeout; - uint32_t cr; - uint32_t sr; - - /* Select a timeout */ - -#ifdef CONFIG_STM32F0L0G0_I2C_DYNTIMEO - timeout = USEC2TICK(CONFIG_STM32F0L0G0_I2C_DYNTIMEO_STARTSTOP); -#else - timeout = CONFIG_STM32F0L0G0_I2CTIMEOTICKS; -#endif - - /* Wait as stop might still be in progress */ - - start = clock_systime_ticks(); - do - { - /* Calculate the elapsed time */ - - elapsed = clock_systime_ticks() - start; - - /* Check for STOP condition */ - - cr = stm32_i2c_getreg32(priv, STM32_I2C_CR2_OFFSET); - if ((cr & I2C_CR2_STOP) == 0) - { - return; - } - - /* Check for timeout error */ - - sr = stm32_i2c_getreg(priv, STM32_I2C_ISR_OFFSET); - if ((sr & I2C_INT_TIMEOUT) != 0) - { - return; - } - } - - /* Loop until the stop is complete or a timeout occurs. */ - - while (elapsed < timeout); - - /* If we get here then a timeout occurred with the STOP condition - * still pending. - */ - - i2cinfo("Timeout with CR: %04" PRIx32 " SR: %04" PRIx32 "\n", - cr, sr); -} - -/**************************************************************************** - * Name: stm32_i2c_trace* - * - * Description: - * I2C trace instrumentation - * - ****************************************************************************/ - -#ifdef CONFIG_I2C_TRACE -static void stm32_i2c_traceclear(struct stm32_i2c_priv_s *priv) -{ - struct stm32_trace_s *trace = &priv->trace[priv->tndx]; - - trace->status = 0; /* I2C 32-bit status */ - trace->count = 0; /* Interrupt count when status change */ - trace->event = I2CEVENT_NONE; /* Last event that occurred with this status */ - trace->parm = 0; /* Parameter associated with the event */ - trace->time = 0; /* Time of first status or event */ -} - -static void stm32_i2c_tracereset(struct stm32_i2c_priv_s *priv) -{ - /* Reset the trace info for a new data collection */ - - priv->tndx = 0; - priv->start_time = clock_systime_ticks(); - stm32_i2c_traceclear(priv); -} - -static void stm32_i2c_tracenew(struct stm32_i2c_priv_s *priv, - uint32_t status) -{ - struct stm32_trace_s *trace = &priv->trace[priv->tndx]; - - /* Is the current entry uninitialized? Has the status changed? */ - - if (trace->count == 0 || status != trace->status) - { - /* Yes.. Was it the status changed? */ - - if (trace->count != 0) - { - /* Yes.. bump up the trace index - * (unless we are out of trace entries) - */ - - if (priv->tndx >= (CONFIG_I2C_NTRACE - 1)) - { - i2cerr("ERROR: Trace table overflow\n"); - return; - } - - priv->tndx++; - trace = &priv->trace[priv->tndx]; - } - - /* Initialize the new trace entry */ - - stm32_i2c_traceclear(priv); - trace->status = status; - trace->count = 1; - trace->time = clock_systime_ticks(); - } - else - { - /* Just increment the count of times that we have seen this status */ - - trace->count++; - } -} - -static void stm32_i2c_traceevent(struct stm32_i2c_priv_s *priv, - enum stm32_trace_e event, uint32_t parm) -{ - struct stm32_trace_s *trace; - - if (event != I2CEVENT_NONE) - { - trace = &priv->trace[priv->tndx]; - - /* Initialize the new trace entry */ - - trace->event = event; - trace->parm = parm; - - /* Bump up the trace index (unless we are out of trace entries) */ - - if (priv->tndx >= (CONFIG_I2C_NTRACE - 1)) - { - i2cerr("ERROR: Trace table overflow\n"); - return; - } - - priv->tndx++; - stm32_i2c_traceclear(priv); - } -} - -static void stm32_i2c_tracedump(struct stm32_i2c_priv_s *priv) -{ - struct stm32_trace_s *trace; - int i; - - syslog(LOG_DEBUG, "Elapsed time: %d\n", - (int)(clock_systime_ticks() - priv->start_time)); - - for (i = 0; i < priv->tndx; i++) - { - trace = &priv->trace[i]; - syslog(LOG_DEBUG, - "%2d. STATUS: %08" PRIx32 " COUNT: %3d EVENT: %2d" - " PARM: %08" PRIx32 " TIME: %d\n", - i + 1, trace->status, trace->count, trace->event, trace->parm, - (int)(trace->time - priv->start_time)); - } -} -#endif /* CONFIG_I2C_TRACE */ - -/**************************************************************************** - * Name: stm32_i2c_setclock - * - * Description: - * - * Sets the I2C bus clock frequency by configuring the I2C_TIMINGR - * register. - * - * This function supports bus clock frequencies of: - * - * 1000Khz (Fast Mode+) - * 400Khz (Fast Mode) - * 100Khz (Standard Mode) - * 10Khz (Standard Mode) - * - * Attempts to set a different frequency will quietly provision the - * default of 10Khz. - * - * The only differences between the various modes of operation (std, fast, - * fast+) are the bus clock speed and setup/hold times. Setup/hold times - * are specified as a MINIMUM time for the given mode, and naturally std - * mode has the longest minimum times. As a result, by provisioning - * setup/hold times for std mode they are also compatible with fast/fast+, - * though some performance degradation occurs in fast/fast+ as a result of - * the times being somewhat longer than strictly required. The values - * remain as they are because reliability is favored over performance. - * - * Clock Selection: - * - * The I2C peripheral clock can be provided by either PCLK1, SYSCLK or the - * HSI. - * - * PCLK1 >------|\ I2CCLK - * SYSCLK >------| |---------> - * HSI >------|/ - * - * HSI is the default and is always 16Mhz. - * - * SYSCLK can, in turn, be derived from the HSI, HSE, PPLCLK. - * - * HSI >------|\ - * | | SYSCLK - * PLL >------| |---------> - * | | - * HSE >------|/ - * - * - * References: - * - * App Note AN4235 and the associated software STSW-STM32126. - * - ****************************************************************************/ - -static void stm32_i2c_setclock(struct stm32_i2c_priv_s *priv, - uint32_t frequency) -{ - uint8_t presc; - uint8_t scl_delay; - uint8_t sda_delay; - uint8_t scl_h_period; - uint8_t scl_l_period; - - /* I2C peripheral must be disabled to update clocking configuration. - * This will SW reset the device. - */ - - stm32_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, I2C_CR1_PE, 0); - - if (frequency != priv->frequency) - { - /* The Speed and timing calculation are based on the following - * fI2CCLK = HSI and is 16Mhz - * Analog filter is on, - * Digital filter off - * Rise Time is 120 ns and fall is 10ns - * Mode is FastMode - */ - - if (frequency == 100000) - { - presc = 0; - scl_delay = 5; - sda_delay = 0; - scl_h_period = 61; - scl_l_period = 89; - } - else if (frequency == 400000) - { - presc = 0; - scl_delay = 3; - sda_delay = 0; - scl_h_period = 6; - scl_l_period = 24; - } - else if (frequency == 1000000) - { - presc = 0; - scl_delay = 2; - sda_delay = 0; - scl_h_period = 1; - scl_l_period = 5; - } - else - { - presc = 7; - scl_delay = 0; - sda_delay = 0; - scl_h_period = 35; - scl_l_period = 162; - } - - uint32_t timingr = - (presc << I2C_TIMINGR_PRESC_SHIFT) | - (scl_delay << I2C_TIMINGR_SCLDEL_SHIFT) | - (sda_delay << I2C_TIMINGR_SDADEL_SHIFT) | - (scl_h_period << I2C_TIMINGR_SCLH_SHIFT) | - (scl_l_period << I2C_TIMINGR_SCLL_SHIFT); - - stm32_i2c_putreg32(priv, STM32_I2C_TIMINGR_OFFSET, timingr); - priv->frequency = frequency; - } - - /* Enable I2C peripheral */ - - stm32_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, 0, I2C_CR1_PE); -} - -/**************************************************************************** - * Name: stm32_i2c_sendstart - * - * Description: - * Send the START condition / force Master mode - * - * A START condition in I2C consists of a single byte that contains both - * the 7 bit slave address and a read/write bit (0 = WRITE, 1 = READ). - * If the address is recognized by one of the slave devices that slave - * device will ACK the byte so that data transfers can begin. - * - * A RESTART (or repeated START per the I2CSPEC) is simply a START - * condition issued in the middle of a transfer (i.e. after the initial - * START and before a STOP). A RESTART sends a new address byte and R/W - * bit to the bus. A RESTART is optional in most cases but mandatory in - * the event the transfer direction is changed. - * - * Most of the time reading data from an I2C slave requires a WRITE of - * the subaddress followed by a READ (and hence a RESTART in between). - * Writing to an I2C slave typically requires only WRITE operations and - * hence no RESTARTs. - * - * This function is therefore called both at the beginning of a transfer - * (START) and at appropriate times during a transfer (RESTART). - * - ****************************************************************************/ - -static inline void stm32_i2c_sendstart(struct stm32_i2c_priv_s *priv) -{ - bool next_norestart = false; - - /* Set the private "current message" data used in protocol processing. - * - * ptr: A pointer to the start of the current message buffer. This is - * advanced after each byte in the current message is transferred. - * - * dcnt: A running counter of the bytes in the current message waiting - * to be transferred. This is decremented each time a byte is - * transferred. - * The hardware normally accepts a maximum of 255 bytes per transfer - * but can support more via the RELOAD mechanism. If dcnt initially - * exceeds 255, the RELOAD mechanism will be enabled automatically. - * - * flags: Used to characterize handling of the current message. - * - * The default flags value is 0 which specifies: - * - * - A transfer direction of WRITE (R/W bit = 0) - * - RESTARTs between all messages - * - * The following flags can be used to override this behavior as follows: - * - * - I2C_M_READ: Sets the transfer direction to READ (R/W bit = 1) - * - I2C_M_NOSTART: Prevents a RESTART from being issued prior to the - * transfer of the message (where allowed by the protocol). - * - */ - - priv->ptr = priv->msgv->buffer; - priv->dcnt = priv->msgv->length; - priv->flags = priv->msgv->flags; - - if ((priv->flags & I2C_M_NOSTART) == 0) - { - /* Flag the first byte as an address byte */ - - priv->astart = true; - } - - /* Enabling RELOAD allows the transfer of: - * - * - individual messages with a payload exceeding 255 bytes - * - multiple messages back to back without a RESTART in between - * - * so we enable it if either of those conditions exist and disable - * it otherwise. - */ - - /* Check if there are multiple messages and the next is a continuation */ - - if (priv->msgc > 1) - { - next_norestart = (((priv->msgv + 1)->flags & I2C_M_NOSTART) != 0); - } - - if (next_norestart || priv->dcnt > 255) - { - i2cinfo("RELOAD enabled: dcnt = %i msgc = %i\n", - priv->dcnt, priv->msgc); - stm32_i2c_enable_reload(priv); - } - else - { - i2cinfo("RELOAD disable: dcnt = %i msgc = %i\n", - priv->dcnt, priv->msgc); - stm32_i2c_disable_reload(priv); - } - - /* Set the number of bytes to transfer (I2C_CR2->NBYTES) to the number of - * bytes in the current message or 255, whichever is lower so as to not - * exceed the hardware maximum allowed. - */ - - if (priv->dcnt > 255) - { - stm32_i2c_set_bytes_to_transfer(priv, 255); - } - else - { - stm32_i2c_set_bytes_to_transfer(priv, priv->dcnt); - } - - /* Set the (7 bit) address. - * 10 bit addressing is not yet supported. - */ - - stm32_i2c_set_7bit_address(priv); - - /* The flag of the current message is used to determine the direction of - * transfer required for the current message. - */ - - if (priv->flags & I2C_M_READ) - { - stm32_i2c_set_read_transfer_dir(priv); - } - else - { - stm32_i2c_set_write_transfer_dir(priv); - } - - /* Set the I2C_CR2->START bit to 1 to instruct the hardware to send the - * START condition using the address and transfer direction data entered. - */ - - i2cinfo("Sending START: dcnt=%i msgc=%i flags=0x%04x\n", - priv->dcnt, priv->msgc, priv->flags); - - stm32_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, 0, I2C_CR2_START); -} - -/**************************************************************************** - * Name: stm32_i2c_sendstop - * - * Description: - * Send the STOP conditions - * - * A STOP condition can be requested by setting the STOP bit in the I2C_CR2 - * register. Setting the STOP bit clears the TC flag and the STOP condition - * is sent on the bus. - * - ****************************************************************************/ - -static inline void stm32_i2c_sendstop(struct stm32_i2c_priv_s *priv) -{ - i2cinfo("Sending STOP\n"); - stm32_i2c_traceevent(priv, I2CEVENT_WRITE_STOP, 0); - - stm32_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, 0, I2C_CR2_STOP); -} - -/**************************************************************************** - * Name: stm32_i2c_getstatus - * - * Description: - * Get 32-bit status (SR1 and SR2 combined) - * - ****************************************************************************/ - -static inline uint32_t stm32_i2c_getstatus(struct stm32_i2c_priv_s *priv) -{ - return getreg32(priv->config->base + STM32_I2C_ISR_OFFSET); -} - -/**************************************************************************** - * Name: stm32_i2c_clearinterrupts - * - * Description: - * Clear all interrupts - * - ****************************************************************************/ - -static inline void stm32_i2c_clearinterrupts(struct stm32_i2c_priv_s *priv) -{ - stm32_i2c_modifyreg32(priv, STM32_I2C_ICR_OFFSET, 0, I2C_ICR_CLEARMASK); -} - -/**************************************************************************** - * Name: stm32_i2c_isr_process - * - * Description: - * Common interrupt service routine (ISR) that handles I2C protocol logic. - * This is instantiated for each configured I2C interface - * (I2C1, I2C2, I2C3). - * - * This ISR is activated and deactivated by: - * - * stm32_i2c_process - * and - * stm32_i2c_waitdone - * - * Input Parameters: - * priv - The private struct of the I2C driver. - * - ****************************************************************************/ - -static int stm32_i2c_isr_process(struct stm32_i2c_priv_s *priv) -{ - uint32_t status; - - /* Get state of the I2C controller */ - - status = stm32_i2c_getreg32(priv, STM32_I2C_ISR_OFFSET); - - i2cinfo("ENTER: status = 0x%08" PRIx32 "\n", status); - - /* Update private version of the state assuming a good state */ - - priv->status = status & ~I2C_INT_BAD_STATE; - - /* If this is a new transmission set up the trace table accordingly */ - - stm32_i2c_tracenew(priv, status); - stm32_i2c_traceevent(priv, I2CEVENT_ISR_CALL, 0); - - /* ------------------- Start of I2C protocol handling ------------------ */ - - /* I2C protocol logic follows. - * It's organized in an if else chain such that only one mode of operation - * is executed every time the ISR is called. - * - * If you need to add additional states to support new features be sure - * they continue the chain (i.e. begin with "else if") and are placed - * before the empty call / error states at the end of the chain. - */ - - /* NACK Handling - * - * This branch is only triggered when the NACK (Not Acknowledge Received) - * interrupt occurs. This interrupt will only fire when the - * I2C_CR1->NACKIE bit is 1. - * - * I2C_ISR->NACKF is set by hardware when a NACK is received after a byte - * is transmitted and the slave fails to acknowledge it. This is the - * opposite of, and mutually exclusive to, the I2C_ISR->TXIS event. - * - * In response to the NACK the hardware automatically triggers generation - * of a STOP condition, terminating the transfer. The only valid response - * to this state is to exit the ISR and report the failure. - * - * To differentiate an "address NACK" from a NACK that might occur during - * the transfer of other bytes the "priv->astart" parameter is - * used. This flag is set to TRUE in sendstart() and set to FALSE when - * the first TXIS event is received, which would be after the first byte - * (the address) is transmitted successfully (acknowledged). - */ - - if (status & I2C_INT_NACK) - { - if (priv->astart == true) - { - /* NACK received on first (address) byte: address is invalid */ - - i2cinfo("NACK: Address invalid: dcnt=%i msgc=%i " - "status=0x%08" PRIx32 "\n", - priv->dcnt, priv->msgc, status); - stm32_i2c_traceevent(priv, - I2CEVENT_ADDRESS_NACKED, priv->msgv->addr); - } - else - { - /* NACK received on regular byte */ - - i2cinfo("NACK: NACK received: dcnt=%i msgc=%i " - "status=0x%08" PRIx32 "\n", - priv->dcnt, priv->msgc, status); - stm32_i2c_traceevent(priv, - I2CEVENT_ADDRESS_NACKED, priv->msgv->addr); - } - - /* Set flags to terminate message transmission: - * - * set message length to -1 to indicate last byte of message sent - * set message count to 0 to indicate no more messages to send - * - * As we fall through the logic in the ISR the message handling block - * will be triggered by these flags and signal the ISR to terminate. - */ - - priv->dcnt = -1; - priv->msgc = 0; - } - - /* Transmit Interrupt Status (TXIS) Handler - * - * This branch is only triggered when the TXIS interrupt occurs. This - * interrupt will only fire when the I2C_CR1->TXIE bit is 1. - * - * This indicates the transmit data register I2C_TXDR has been emptied - * following the successful transmission of a byte and slave - * acknowledgment. - * In this state the I2C_TXDR register is ready to accept another byte - * for transmission. The TXIS bit will be cleared automatically when - * the next byte is written to I2C_TXDR. - * - * The number of TXIS events during the transfer corresponds to NBYTES. - * - * The TXIS flag is not set when a NACK is received. - * - * When RELOAD is disabled (RELOAD=0) and NBYTES data have been - * transferred: - * - * - In Automatic End Mode (AUTOEND=1), a STOP is automatically sent. - * - * Note: Automatic End Mode is not currently supported. - * - * - In Software End Mode (AUTOEND=0), the TC event occurs and the SCL - * line is stretched low in order to allow software actions (STOP, - * RESTART). - * - * When RELOAD is enabled (RELOAD=1) and NBYTES bytes have been - * transferred a TCR event occurs instead and that handler simply updates - * NBYTES which causes TXIS events to continue. The process repeats until - * all bytes in the message have been transferred. - */ - - else if ((priv->flags & (I2C_M_READ)) == 0 && - (status & (I2C_ISR_TXIS)) != 0) - { - /* TXIS interrupt occurred, address valid, ready to transmit */ - - stm32_i2c_traceevent(priv, I2CEVENT_WRITE, 0); - i2cinfo("TXIS: ENTER dcnt = %i msgc = %i status 0x%08" PRIx32 "\n", - priv->dcnt, priv->msgc, status); - - /* The first event after the address byte is sent will be either TXIS - * or NACKF so it's safe to set the astart flag to false on - * the first TXIS event to indicate that it is no longer necessary to - * check for address validity. - */ - - if (priv->astart == true) - { - i2cinfo("TXIS: Address Valid\n"); - stm32_i2c_traceevent(priv, I2CEVENT_ADDRESS_ACKED, - priv->msgv->addr); - priv->astart = false; - } - - /* If one or more bytes in the current message are ready to transmit */ - - if (priv->dcnt > 0) - { - /* Prepare to transmit the current byte */ - - stm32_i2c_traceevent(priv, I2CEVENT_WRITE_TO_DR, priv->dcnt); - i2cinfo("TXIS: Write Data 0x%02x\n", *priv->ptr); - - /* Decrement byte counter */ - - priv->dcnt--; - - /* If we are about to transmit the last byte in the current - * message - */ - - if (priv->dcnt == 0) - { - /* If this is also the last message to send, disable RELOAD so - * TC fires next and issues STOP condition. If we don't do - * this TCR will fire next, and since there are no bytes to - * send we can't write NBYTES to clear TCR so it will fire - * forever. - */ - - if (priv->msgc == 1) - { - stm32_i2c_disable_reload(priv); - } - } - - /* Transmit current byte */ - - stm32_i2c_putreg(priv, STM32_I2C_TXDR_OFFSET, *priv->ptr); - - /* Advance to next byte */ - - priv->ptr++; - } - else - { - /* Unsupported state */ - - i2cerr("ERROR: TXIS Unsupported state detected, dcnt=%i, " - "status 0x%08" PRIx32 "\n", - priv->dcnt, status); - stm32_i2c_traceevent(priv, I2CEVENT_WRITE_ERROR, 0); - - /* Indicate the bad state, - * so that on termination HW will be reset - */ - - priv->status |= I2C_INT_BAD_STATE; - } - - i2cinfo("TXIS: EXIT dcnt = %i msgc = %i status 0x%08" PRIx32 "\n", - priv->dcnt, priv->msgc, status); - } - - /* Receive Buffer Not Empty (RXNE) State Handler - * - * This branch is only triggered when the RXNE interrupt occurs. This - * interrupt will only fire when the I2C_CR1->RXIE bit is 1. - * - * This indicates data has been received from the bus and is waiting to - * be read from the I2C_RXDR register. When I2C_RXDR is read this bit - * is automatically cleared and then an ACK or NACK is sent depending on - * whether we have more bytes to receive. - * - * When RELOAD is disabled and bytes remain to be transferred an - * acknowledge is automatically sent on the bus and the RXNE events - * continue until the last byte is received. - * - * When RELOAD is disabled (RELOAD=0) and BYTES have been transferred: - * - * - In Automatic End Mode (AUTOEND=1), a NACK and a STOP are - * automatically sent after the last received byte. - * - * Note: Automatic End Mode is not currently supported. - * - * - In Software End Mode (AUTOEND=0), a NACK is automatically sent - * after the last received byte, the TC event occurs and the SCL line - * is stretched low in order to allow software actions (STOP, RESTART). - * - * When RELOAD is enabled (RELOAD=1) and NBYTES bytes have been transferred - * a TCR event occurs and that handler simply updates NBYTES which causes - * RXNE events to continue until all bytes have been transferred. - */ - - else if ((priv->flags & (I2C_M_READ)) != 0 && (status & I2C_ISR_RXNE) != 0) - { - /* When read flag is set and the receive buffer is not empty - * (RXNE is set) then the driver can read from the data register. - */ - - stm32_i2c_traceevent(priv, I2CEVENT_READ, 0); - i2cinfo("RXNE: ENTER dcnt = %i msgc = %i status 0x%08" PRIx32 "\n", - priv->dcnt, priv->msgc, status); - - /* If more bytes in the current message */ - - if (priv->dcnt > 0) - { - stm32_i2c_traceevent(priv, I2CEVENT_RCVBYTE, priv->dcnt); - - /* No interrupts or context switches may occur in the following - * sequence. Otherwise, additional bytes may be received. - */ - -#ifdef CONFIG_I2C_POLLED - irqstate_t state = enter_critical_section(); -#endif - /* Receive a byte */ - - *priv->ptr = stm32_i2c_getreg(priv, STM32_I2C_RXDR_OFFSET); - - i2cinfo("RXNE: Read Data 0x%02x\n", *priv->ptr); - - /* Advance buffer to the next byte in the message */ - - priv->ptr++; - - /* Signal byte received */ - - priv->dcnt--; - -#ifdef CONFIG_I2C_POLLED - leave_critical_section(state); -#endif - } - else - { - /* Unsupported state */ - - stm32_i2c_traceevent(priv, I2CEVENT_READ_ERROR, 0); - status = stm32_i2c_getreg(priv, STM32_I2C_ISR_OFFSET); - i2cerr("ERROR: RXNE Unsupported state detected, dcnt=%i, " - "status 0x%08" PRIx32 "\n", - priv->dcnt, status); - - /* Set signals that will terminate ISR and wake waiting thread */ - - priv->status |= I2C_INT_BAD_STATE; - priv->dcnt = -1; - priv->msgc = 0; - } - - i2cinfo("RXNE: EXIT dcnt = %i msgc = %i status 0x%08" PRIx32 "\n", - priv->dcnt, priv->msgc, status); - } - - /* Transfer Complete (TC) State Handler - * - * This branch is only triggered when the TC interrupt occurs. This - * interrupt will only fire when: - * - * I2C_CR1->TCIE = 1 (Transfer Complete Interrupts Enabled) - * I2C_CR2->RELOAD = 0 (Reload Mode Disabled) - * I2C_CR2->AUTOEND = 0 (Autoend Mode Disabled, i.e. Software End Mode) - * - * This event indicates that the number of bytes initially defined - * in NBYTES, meaning, the number of bytes in the current message - * (priv->dcnt) has been successfully transmitted or received. - * - * When the TC interrupt occurs we have two choices to clear it and move - * on, regardless of the transfer direction: - * - * - if more messages follow, perform a repeated START if required - * and then fall through to transmit or receive the next message. - * - * - if no messages follow, perform a STOP and set flags needed to - * exit the ISR. - * - * The fact that the hardware must either RESTART or STOP when a TC - * event occurs explains why, when messages must be sent back to back - * (i.e. without a restart by specifying the I2C_M_NOSTART flag), - * RELOAD mode must be enabled and TCR event(s) must be generated - * instead. See the TCR handler for more. - */ - - else if ((status & I2C_ISR_TC) != 0) - { - i2cinfo("TC: ENTER dcnt = %i msgc = %i status 0x%08" PRIx32 "\n", - priv->dcnt, priv->msgc, status); - - /* Prior message has been sent successfully. Or there could have - * been an error that set msgc to 0; So test for that case as - * we do not want to decrement msgc less then zero nor move msgv - * past the last message. - */ - - if (priv->msgc > 0) - { - priv->msgc--; - } - - /* Are there additional messages remain to be transmitted / received? */ - - if (priv->msgc > 0) - { - i2cinfo("TC: RESTART: dcnt=%i, msgc=%i\n", - priv->dcnt, priv->msgc); - stm32_i2c_traceevent(priv, I2CEVENT_TC_NO_RESTART, priv->msgc); - - /* Issue a START condition. - * - * Note that the first thing sendstart does is update the - * private structure "current message" data (ptr, dcnt, flags) - * so they all reflect the next message in the list so we - * update msgv before we get there. - */ - - /* Advance to the next message in the list */ - - priv->msgv++; - - stm32_i2c_sendstart(priv); - } - else - { - /* Issue a STOP conditions. - * - * No additional messages to transmit / receive, so the - * transfer is indeed complete. Nothing else to do but - * issue a STOP and exit. - */ - - i2cinfo("TC: STOP: dcnt=%i msgc=%i\n", - priv->dcnt, priv->msgc); - stm32_i2c_traceevent(priv, I2CEVENT_STOP, priv->dcnt); - - stm32_i2c_sendstop(priv); - - /* Set signals that will terminate ISR and wake waiting thread */ - - priv->dcnt = -1; - priv->msgc = 0; - } - - i2cinfo("TC: EXIT dcnt = %i msgc = %i status 0x%08" PRIx32 "\n", - priv->dcnt, priv->msgc, status); - } - - /* Transfer Complete (Reload) State Handler - * - * This branch is only triggered when the TCR interrupt occurs. This - * interrupt will only fire when: - * - * I2C_CR1->TCIE = 1 (Transfer Complete Interrupts Enabled) - * I2C_CR2->RELOAD = 1 (Reload Mode Active) - * I2C_CR2->AUTOEND = 0 (Autoend Mode Disabled, i.e. Software End Mode) - * - * This is similar to the TC event except that TCR assumes that additional - * bytes are available to transfer. So despite what its name might imply - * the transfer really isn't complete. - * - * There are two reasons RELOAD would be enabled: - * - * 1) We're trying to send a message with a payload greater than 255 - * bytes. - * 2) We're trying to send messages back to back, regardless of their - * payload size, to avoid a RESTART (i.e. I2C_M_NOSTART flag is set). - * - * These conditions may be true simultaneously, as would be the case if - * we're sending multiple messages with payloads > 255 bytes. So we - * only advance to the next message if we arrive here and dcnt is 0, - * meaning, we're finished with the last message and ready to move to the - * next. - * - * This logic supports the transfer of bytes limited only by the size of - * the i2c_msg_s length variable. The SCL line will be stretched low - * until NBYTES is written with a non-zero value, allowing the transfer - * to continue. - * - * TODO: RESTARTs are required by the I2CSPEC if the next message transfer - * direction changes. Right now the NORESTART flag overrides this - * behavior. May have to introduce logic to issue sendstart, assuming it's - * legal with the hardware in the TCR state. - */ - - else if ((status & I2C_ISR_TCR) != 0) - { - i2cinfo("TCR: ENTER dcnt = %i msgc = %i status 0x%08" PRIx32 "\n", - priv->dcnt, priv->msgc, status); - - /* If no more bytes in the current message to transfer */ - - if (priv->dcnt == 0) - { - /* Prior message has been sent successfully */ - - priv->msgc--; - - /* Advance to the next message in the list */ - - priv->msgv++; - - /* Update current message data */ - - priv->ptr = priv->msgv->buffer; - priv->dcnt = priv->msgv->length; - priv->flags = priv->msgv->flags; - - /* if this is the last message, disable reload so the - * TC event fires next time. - */ - - if (priv->msgc == 0) - { - i2cinfo("TCR: DISABLE RELOAD: dcnt = %i msgc = %i\n", - priv->dcnt, priv->msgc); - - stm32_i2c_disable_reload(priv); - } - - /* Update NBYTES with length of current message */ - - i2cinfo("TCR: NEXT MSG dcnt = %i msgc = %i\n", - priv->dcnt, priv->msgc); - - stm32_i2c_set_bytes_to_transfer(priv, priv->dcnt); - } - else - { - /* More bytes in the current (greater than 255 byte payload - * length) message, so set NBYTES according to the bytes - * remaining in the message, up to a maximum each cycle of 255. - */ - - if (priv->dcnt > 255) - { - i2cinfo( - "TCR: ENABLE RELOAD: NBYTES = 255 dcnt = %i msgc = %i\n", - priv->dcnt, priv->msgc); - - /* More than 255 bytes to transfer so the RELOAD bit is - * set in order to generate a TCR event rather than a TC - * event when 255 bytes are successfully transferred. - * This forces us to return here to update NBYTES and - * continue until NBYTES is set to less than 255 bytes, - * at which point RELOAD will be disabled and a TC - * event will (eventually) follow to officially terminate - * the transfer. - */ - - stm32_i2c_enable_reload(priv); - - stm32_i2c_set_bytes_to_transfer(priv, 255); - } - else - { - /* Less than 255 bytes left to transfer, which means we'll - * complete the transfer of all bytes in the current message - * the next time around. - * - * This means we need to disable the RELOAD functionality so - * we receive a TC event next time which will allow us to - * either RESTART and continue sending the contents of the - * next message or send a STOP condition and exit the ISR. - */ - - i2cinfo("TCR: DISABLE RELOAD: NBYTES = dcnt = %i msgc = %i\n", - priv->dcnt, priv->msgc); - - stm32_i2c_set_bytes_to_transfer(priv, priv->dcnt); - - stm32_i2c_disable_reload(priv); - } - - i2cinfo("TCR: EXIT dcnt = %i msgc = %i status 0x%08" PRIx32 "\n", - priv->dcnt, priv->msgc, status); - } - } - - /* Empty call handler - * - * Case to handle an empty call to the ISR where it has nothing to - * do and should exit immediately. - */ - - else if (priv->dcnt == -1 && priv->msgc == 0) - { - status = stm32_i2c_getreg(priv, STM32_I2C_ISR_OFFSET); - i2cwarn("WARNING: EMPTY CALL: Stopping ISR: status 0x%08" PRIx32 "\n", - status); - stm32_i2c_traceevent(priv, I2CEVENT_ISR_EMPTY_CALL, 0); - } - - /* Error handler - * - * We get to this branch only if we can't handle the current state. - * - * This can happen in interrupt based operation on ARLO & BUSY. - * - * This will happen during polled operation when the device is not - * in one of the supported states when polled. - */ - - else - { -#ifdef CONFIG_I2C_POLLED - stm32_i2c_traceevent(priv, I2CEVENT_POLL_DEV_NOT_RDY, 0); -#else - /* Read rest of the state */ - - status = stm32_i2c_getreg(priv, STM32_I2C_ISR_OFFSET); - - i2cerr("ERROR: Invalid state detected, status 0x%08" PRIx32 "\n", - status); - - /* set condition to terminate ISR and wake waiting thread */ - - priv->status |= I2C_INT_BAD_STATE; - priv->dcnt = -1; - priv->msgc = 0; - stm32_i2c_traceevent(priv, I2CEVENT_STATE_ERROR, 0); -#endif - } - - /* ------------------- End of I2C protocol handling ----------------- */ - - /* Message Handling - * - * Transmission of the whole message chain has been completed. We have to - * terminate the ISR and wake up stm32_i2c_process() that is waiting for - * the ISR cycle to handle the sending/receiving of the messages. - */ - - if (priv->dcnt == -1 && priv->msgc == 0) - { - i2cinfo("MSG: Shutting down I2C ISR\n"); - - stm32_i2c_traceevent(priv, I2CEVENT_ISR_SHUTDOWN, 0); - - /* clear pointer to message content to reflect we are done - * with the current transaction. - */ - - priv->msgv = NULL; - -#ifdef CONFIG_I2C_POLLED - priv->intstate = INTSTATE_DONE; -#else - - /* We will update private state to capture NACK which is used in - * combination with the astart flag to report the type of NACK - * received (address vs data) to the upper layers once we exit the ISR. - * - * Note: status is captured prior to clearing interrupts because - * the NACKF flag will naturally be cleared by that process. - */ - - status = stm32_i2c_getreg32(priv, STM32_I2C_ISR_OFFSET); - - /* Clear all interrupts */ - - stm32_i2c_modifyreg32(priv, STM32_I2C_ICR_OFFSET, 0, - I2C_ICR_CLEARMASK); - - /* Was a bad state detected in the processing? */ - - if (priv->status & I2C_INT_BAD_STATE) - { - /* SW reset device */ - - stm32_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, I2C_CR1_PE, 0); - } - - /* Update private status from above sans I2C_INT_BAD_STATE */ - - priv->status = status; - - /* If a thread is waiting then inform it transfer is complete */ - - if (priv->intstate == INTSTATE_WAITING) - { - nxsem_post(&priv->sem_isr); - priv->intstate = INTSTATE_DONE; - } -#endif - } - - status = stm32_i2c_getreg32(priv, STM32_I2C_ISR_OFFSET); - i2cinfo("EXIT: status = 0x%08" PRIx32 "\n", status); - - return OK; -} - -/**************************************************************************** - * Name: stm32_i2c_isr - * - * Description: - * Common I2C interrupt service routine - * - ****************************************************************************/ - -#ifndef CONFIG_I2C_POLLED -static int stm32_i2c_isr(int irq, void *context, void *arg) -{ - struct stm32_i2c_priv_s *priv = (struct stm32_i2c_priv_s *)arg; - - DEBUGASSERT(priv != NULL); - return stm32_i2c_isr_process(priv); -} -#endif - -/**************************************************************************** - * Name: stm32_i2c_init - * - * Description: - * Setup the I2C hardware, ready for operation with defaults - * - ****************************************************************************/ - -static int stm32_i2c_init(struct stm32_i2c_priv_s *priv) -{ - /* Power-up and configure GPIOs */ - - /* Enable power and reset the peripheral */ - - modifyreg32(STM32_RCC_APB1ENR, 0, priv->config->clk_bit); - modifyreg32(STM32_RCC_APB1RSTR, 0, priv->config->reset_bit); - modifyreg32(STM32_RCC_APB1RSTR, priv->config->reset_bit, 0); - - /* Configure pins */ - - if (stm32_configgpio(priv->config->scl_pin) < 0) - { - return ERROR; - } - - if (stm32_configgpio(priv->config->sda_pin) < 0) - { - stm32_unconfiggpio(priv->config->scl_pin); - return ERROR; - } - -#ifndef CONFIG_I2C_POLLED - /* Attach error and event interrupts to the ISRs */ - - irq_attach(priv->config->irq, stm32_i2c_isr, priv); - up_enable_irq(priv->config->irq); -#endif - - /* TODO: - * - Provide means to set peripheral clock source via RCC_CFGR3_I2CxSW - * - Set to HSI by default, make Kconfig option - */ - - /* Force a frequency update */ - - priv->frequency = 0; - stm32_i2c_setclock(priv, 100000); - - return OK; -} - -/**************************************************************************** - * Name: stm32_i2c_deinit - * - * Description: - * Shutdown the I2C hardware - * - ****************************************************************************/ - -static int stm32_i2c_deinit(struct stm32_i2c_priv_s *priv) -{ - /* Disable I2C */ - - stm32_i2c_putreg32(priv, STM32_I2C_CR1_OFFSET, 0); - - /* Unconfigure GPIO pins */ - - stm32_unconfiggpio(priv->config->scl_pin); - stm32_unconfiggpio(priv->config->sda_pin); - -#ifndef CONFIG_I2C_POLLED - - /* Disable and detach interrupts */ - - up_disable_irq(priv->config->irq); - irq_detach(priv->config->irq); -#endif - - /* Disable clocking */ - - modifyreg32(STM32_RCC_APB1ENR, priv->config->clk_bit, 0); - - return OK; -} - -/**************************************************************************** - * Name: stm32_i2c_process - * - * Description: - * Common I2C transfer logic - * - * Initiates a master mode transaction on the I2C bus to transfer the - * provided messages to and from the slave devices. - * - ****************************************************************************/ - -static int stm32_i2c_process(struct i2c_master_s *dev, - struct i2c_msg_s *msgs, int count) -{ - struct stm32_i2c_inst_s *inst = (struct stm32_i2c_inst_s *)dev; - struct stm32_i2c_priv_s *priv = inst->priv; - uint32_t status = 0; - uint32_t cr1; - uint32_t cr2; - int errval = 0; - int waitrc = 0; - - DEBUGASSERT(count > 0); - - /* Wait for any STOP in progress */ - - stm32_i2c_sem_waitstop(priv); - - /* Clear any pending error interrupts */ - - stm32_i2c_clearinterrupts(priv); - - /* Old transfers are done */ - - priv->msgv = msgs; - priv->msgc = count; - - /* Reset I2C trace logic */ - - stm32_i2c_tracereset(priv); - - /* Set I2C clock frequency toggles I2C_CR1_PE performing a SW reset! */ - - stm32_i2c_setclock(priv, msgs->frequency); - - /* Trigger start condition, then the process moves into the ISR. I2C - * interrupts will be enabled within stm32_i2c_waitdone(). - */ - - priv->status = 0; - -#ifndef CONFIG_I2C_POLLED - /* Enable transmit and receive interrupts here so when we send the start - * condition below the ISR will fire if the data was sent and some - * response from the slave received. All other interrupts relevant to - * our needs are enabled in stm32_i2c_sem_waitdone() below. - */ - - stm32_i2c_enableinterrupts(priv); -#endif - - /* Trigger START condition generation, which also sends the slave address - * with read/write flag and the data in the first message - */ - - stm32_i2c_sendstart(priv); - - /* Wait for the ISR to tell us that the transfer is complete by attempting - * to grab the semaphore that is initially locked by the ISR. If the ISR - * does not release the lock so we can obtain it here prior to the end of - * the timeout period waitdone returns error and we report a timeout. - */ - - waitrc = stm32_i2c_sem_waitdone(priv); - - cr1 = stm32_i2c_getreg32(priv, STM32_I2C_CR1_OFFSET); - cr2 = stm32_i2c_getreg32(priv, STM32_I2C_CR2_OFFSET); -#if !defined(CONFIG_DEBUG_I2C) - UNUSED(cr1); - UNUSED(cr2); -#endif - - /* Status after a normal / good exit is usually 0x00000001, meaning the TXE - * bit is set. That occurs as a result of the I2C_TXDR register being - * empty, and it naturally will be after the last byte is transmitted. - * This bit is cleared when we attempt communications again and re-enable - * the peripheral. The priv->status field can hold additional information - * like a NACK, so we reset the status field to include that information. - */ - - status = stm32_i2c_getstatus(priv); - - /* The priv->status field can hold additional information like a NACK - * event so we include that information. - */ - - status = priv->status & 0xffffffff; - - if (waitrc < 0) - { - /* Connection timed out */ - - errval = ETIMEDOUT; - i2cerr("ERROR: Waitdone timed out CR1: 0x%08" PRIx32 - " CR2: 0x%08" PRIx32 " status: 0x%08" PRIx32 "\n", - cr1, cr2, status); - } - else - { - i2cinfo("Waitdone success: CR1: 0x%08" PRIx32 - " CR2: 0x%08" PRIx32 " status: 0x%08" PRIx32 "\n", - cr1, cr2, status); - } - - UNUSED(cr1); - UNUSED(cr2); - - i2cinfo("priv->status: 0x%08" PRIx32 "\n", priv->status); - - /* Check for error status conditions */ - - if ((status & (I2C_INT_BERR | - I2C_INT_ARLO | - I2C_INT_OVR | - I2C_INT_PECERR | - I2C_INT_TIMEOUT | - I2C_INT_NACK)) != 0) - - { - /* one or more errors in the mask are present */ - - if (status & I2C_INT_BERR) - { - /* Bus Error, ignore it because of errata (revision A,Z) */ - - i2cerr("ERROR: I2C Bus Error\n"); - - /* errval = EIO; */ - } - else if (status & I2C_INT_ARLO) - { - /* Arbitration Lost (master mode) */ - - i2cerr("ERROR: I2C Arbitration Lost\n"); - errval = EAGAIN; - } - - else if (status & I2C_INT_OVR) - { - /* Overrun/Underrun */ - - i2cerr("ERROR: I2C Overrun/Underrun\n"); - errval = EIO; - } - else if (status & I2C_INT_PECERR) - { - /* PEC Error in reception (SMBus Only) */ - - i2cerr("ERROR: I2C PEC Error\n"); - errval = EPROTO; - } - else if (status & I2C_INT_TIMEOUT) - { - /* Timeout or Tlow Error (SMBus Only) */ - - i2cerr("ERROR: I2C Timeout / Tlow Error\n"); - errval = ETIME; - } - else if (status & I2C_INT_NACK) - { - /* NACK Received, flag as "communication error on send" */ - - if (priv->astart == TRUE) - { - i2cwarn("WARNING: I2C Address NACK\n"); - errval = EADDRNOTAVAIL; - } - else - { - i2cwarn("WARNING: I2C Data NACK\n"); - errval = ECOMM; - } - } - else - { - /* Unrecognized error */ - - i2cerr("ERROR: I2C Unrecognized Error"); - errval = EINTR; - } - } - - /* This is not an error, but should not happen. The BUSY signal can be - * present if devices on the bus are in an odd state and need to be reset. - * NOTE: We will only see this busy indication if stm32_i2c_sem_waitdone() - * fails above; Otherwise it is cleared. - */ - - else if ((status & I2C_ISR_BUSY) != 0) - { - /* I2C Bus Busy - * - * This is a status condition rather than an error. - * - * We will only see this busy indication if stm32_i2c_sem_waitdone() - * fails above; Otherwise it is cleared by the hardware when the ISR - * wraps up the transfer with a STOP condition. - */ - - clock_t start = clock_systime_ticks(); - clock_t timeout = USEC2TICK(USEC_PER_SEC / priv->frequency) + 1; - - status = stm32_i2c_getstatus(priv); - - while (status & I2C_ISR_BUSY) - { - if ((clock_systime_ticks() - start) > timeout) - { - i2cerr("ERROR: I2C Bus busy"); - errval = EBUSY; - break; - } - - status = stm32_i2c_getstatus(priv); - } - } - - /* Dump the trace result */ - - stm32_i2c_tracedump(priv); - nxmutex_unlock(&priv->lock); - - return -errval; -} - -/**************************************************************************** - * Name: stm32_i2c_transfer - * - * Description: - * Generic I2C transfer function - * - ****************************************************************************/ - -static int stm32_i2c_transfer(struct i2c_master_s *dev, - struct i2c_msg_s *msgs, int count) -{ - struct stm32_i2c_priv_s *priv; - int ret; - - DEBUGASSERT(dev); - - /* Get I2C private structure */ - - priv = ((struct stm32_i2c_inst_s *)dev)->priv; - - /* Ensure that address or flags don't change meanwhile */ - - ret = nxmutex_lock(&priv->lock); - if (ret >= 0) - { - ret = stm32_i2c_process(dev, msgs, count); - } - - return ret; -} - -/**************************************************************************** - * Name: stm32_i2c_reset - * - * Description: - * Reset an I2C bus - * - ****************************************************************************/ - -#ifdef CONFIG_I2C_RESET -static int stm32_i2c_reset(struct i2c_master_s *dev) -{ - struct stm32_i2c_priv_s *priv; - unsigned int clock_count; - unsigned int stretch_count; - uint32_t scl_gpio; - uint32_t sda_gpio; - uint32_t frequency; - int ret; - - DEBUGASSERT(dev); - - /* Get I2C private structure */ - - priv = ((struct stm32_i2c_inst_s *)dev)->priv; - - /* Our caller must own a ref */ - - DEBUGASSERT(priv->refs > 0); - - /* Lock out other clients */ - - ret = nxmutex_lock(&priv->lock); - if (ret < 0) - { - return ret; - } - - ret = -EIO; - - /* Save the current frequency */ - - frequency = priv->frequency; - - /* De-init the port */ - - stm32_i2c_deinit(priv); - - /* Use GPIO configuration to un-wedge the bus */ - - scl_gpio = MKI2C_OUTPUT(priv->config->scl_pin); - sda_gpio = MKI2C_OUTPUT(priv->config->sda_pin); - - stm32_configgpio(sda_gpio); - stm32_configgpio(scl_gpio); - - /* Let SDA go high */ - - stm32_gpiowrite(sda_gpio, 1); - - /* Clock the bus until any slaves currently driving it let it go. */ - - clock_count = 0; - while (!stm32_gpioread(sda_gpio)) - { - /* Give up if we have tried too hard */ - - if (clock_count++ > 10) - { - goto out; - } - - /* Sniff to make sure that clock stretching has finished. - * - * If the bus never relaxes, the reset has failed. - */ - - stretch_count = 0; - while (!stm32_gpioread(scl_gpio)) - { - /* Give up if we have tried too hard */ - - if (stretch_count++ > 10) - { - goto out; - } - - up_udelay(10); - } - - /* Drive SCL low */ - - stm32_gpiowrite(scl_gpio, 0); - up_udelay(10); - - /* Drive SCL high again */ - - stm32_gpiowrite(scl_gpio, 1); - up_udelay(10); - } - - /* Generate a start followed by a stop to reset slave - * state machines. - */ - - stm32_gpiowrite(sda_gpio, 0); - up_udelay(10); - stm32_gpiowrite(scl_gpio, 0); - up_udelay(10); - stm32_gpiowrite(scl_gpio, 1); - up_udelay(10); - stm32_gpiowrite(sda_gpio, 1); - up_udelay(10); - - /* Revert the GPIO configuration. */ - - stm32_unconfiggpio(sda_gpio); - stm32_unconfiggpio(scl_gpio); - - /* Re-init the port */ - - stm32_i2c_init(priv); - - /* Restore the frequency */ - - stm32_i2c_setclock(priv, frequency); - ret = OK; - -out: - - /* Release the port for reuse by other clients */ - - nxmutex_unlock(&priv->lock); - return ret; -} -#endif /* CONFIG_I2C_RESET */ - -/**************************************************************************** - * Name: stm32_i2c_pm_prepare - * - * Description: - * Request the driver to prepare for a new power state. This is a - * warning that the system is about to enter into a new power state. The - * driver should begin whatever operations that may be required to enter - * power state. The driver may abort the state change mode by returning - * a non-zero value from the callback function. - * - * Input Parameters: - * cb - Returned to the driver. The driver version of the callback - * structure may include additional, driver-specific state - * data at the end of the structure. - * domain - Identifies the activity domain of the state change - * pmstate - Identifies the new PM state - * - * Returned Value: - * 0 (OK) means the event was successfully processed and that the driver - * is prepared for the PM state change. Non-zero means that the driver - * is not prepared to perform the tasks needed achieve this power setting - * and will cause the state change to be aborted. NOTE: The prepare - * method will also be recalled when reverting from lower back to higher - * power consumption modes (say because another driver refused a lower - * power state change). Drivers are not permitted to return non-zero - * values when reverting back to higher power consumption modes! - * - ****************************************************************************/ - -#ifdef CONFIG_PM -static int stm32_i2c_pm_prepare(struct pm_callback_s *cb, int domain, - enum pm_state_e pmstate) -{ - struct stm32_i2c_priv_s *priv = - (struct stm32_i2c_priv_s *)((char *)cb - - offsetof(struct stm32_i2c_priv_s, pm_cb)); - - /* Logic to prepare for a reduced power state goes here. */ - - switch (pmstate) - { - case PM_NORMAL: - case PM_IDLE: - break; - - case PM_STANDBY: - case PM_SLEEP: - - /* Check if exclusive lock for I2C bus is held. */ - - if (nxmutex_is_locked(&priv->lock)) - { - /* Exclusive lock is held, do not allow entry to deeper PM - * states. - */ - - return -EBUSY; - } - - break; - - default: - - /* Should not get here */ - - break; - } - - return OK; -} -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_i2cbus_initialize - * - * Description: - * Initialize one I2C bus - * - ****************************************************************************/ - -struct i2c_master_s *stm32_i2cbus_initialize(int port) -{ - struct stm32_i2c_priv_s *priv = NULL; /* private data of device with multiple instances */ - struct stm32_i2c_inst_s *inst = NULL; /* device, single instance */ - - /* Get I2C private structure */ - - switch (port) - { -#ifdef CONFIG_STM32F0L0G0_I2C1 - case 1: - priv = (struct stm32_i2c_priv_s *)&stm32_i2c1_priv; - break; -#endif -#ifdef CONFIG_STM32F0L0G0_I2C2 - case 2: - priv = (struct stm32_i2c_priv_s *)&stm32_i2c2_priv; - break; -#endif -#ifdef CONFIG_STM32F0L0G0_I2C3 - case 3: - priv = (struct stm32_i2c_priv_s *)&stm32_i2c3_priv; - break; -#endif -#ifdef CONFIG_STM32F0L0G0_I2C4 - case 4: - priv = (struct stm32_i2c_priv_s *)&stm32_i2c4_priv; - break; -#endif - default: - return NULL; - } - - /* Allocate instance */ - - if (!(inst = kmm_malloc(sizeof(struct stm32_i2c_inst_s)))) - { - return NULL; - } - - /* Initialize instance */ - - inst->ops = &stm32_i2c_ops; - inst->priv = priv; - - /* Init private data for the first time, increment refs count, - * power-up hardware and configure GPIOs. - */ - - nxmutex_lock(&priv->lock); - - if (priv->refs++ == 0) - { - stm32_i2c_init(priv); - -#ifdef CONFIG_PM - /* Register to receive power management callbacks */ - - DEBUGVERIFY(pm_register(&priv->pm_cb)); -#endif - } - - nxmutex_unlock(&priv->lock); - return (struct i2c_master_s *)inst; -} - -/**************************************************************************** - * Name: stm32_i2cbus_uninitialize - * - * Description: - * Uninitialize an I2C bus - * - ****************************************************************************/ - -int stm32_i2cbus_uninitialize(struct i2c_master_s *dev) -{ - struct stm32_i2c_priv_s *priv; - - DEBUGASSERT(dev); - priv = ((struct stm32_i2c_inst_s *)dev)->priv; - - /* Decrement refs and check for underflow */ - - if (priv->refs == 0) - { - return ERROR; - } - - nxmutex_lock(&priv->lock); - if (--priv->refs) - { - nxmutex_unlock(&priv->lock); - kmm_free(dev); - return OK; - } - -#ifdef CONFIG_PM - /* Unregister power management callbacks */ - - pm_unregister(&priv->pm_cb); -#endif - - /* Disable power and other HW resource (GPIO's) */ - - stm32_i2c_deinit(priv); - nxmutex_unlock(&priv->lock); - - kmm_free(dev); - return OK; -} - -#endif /* CONFIG_STM32F0L0G0_I2C1 || CONFIG_STM32F0L0G0_I2C2 || \ - * CONFIG_STM32F0L0G0_I2C3 || CONFIG_STM32F0L0G0_I2C4 */ diff --git a/arch/arm/src/stm32f0l0g0/stm32_i2c.h b/arch/arm/src/stm32f0l0g0/stm32_i2c.h deleted file mode 100644 index 0a52455ba3374..0000000000000 --- a/arch/arm/src/stm32f0l0g0/stm32_i2c.h +++ /dev/null @@ -1,91 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_i2c.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_STM32_I2C_H -#define __ARCH_ARM_SRC_STM32F0L0G0_STM32_I2C_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include - -#include "chip.h" -#include "hardware/stm32_i2c.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* If a dynamic timeout is selected, then a non-negative, non-zero micro- - * seconds per byte value must be provided as well. - */ - -#ifdef CONFIG_STM32F0L0G0_I2C_DYNTIMEO -# if CONFIG_STM32F0L0G0_I2C_DYNTIMEO_USECPERBYTE < 1 -# warning "Ignoring CONFIG_STM32F0L0G0_I2C_DYNTIMEO because of CONFIG_STM32F0L0G0_I2C_DYNTIMEO_USECPERBYTE" -# undef CONFIG_STM32F0L0G0_I2C_DYNTIMEO -# endif -#endif - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_i2cbus_initialize - * - * Description: - * Initialize the selected I2C port. And return a unique instance of struct - * struct i2c_master_s. This function may be called to obtain multiple - * instances of the interface, each of which may be set up with a - * different frequency and slave address. - * - * Input Parameters: - * Port number (for hardware that has multiple I2C interfaces) - * - * Returned Value: - * Valid I2C device structure reference on success; a NULL on failure - * - ****************************************************************************/ - -struct i2c_master_s *stm32_i2cbus_initialize(int port); - -/**************************************************************************** - * Name: stm32_i2cbus_uninitialize - * - * Description: - * De-initialize the selected I2C port, and power down the device. - * - * Input Parameters: - * Device structure as returned by the stm32_i2cbus_initialize() - * - * Returned Value: - * OK on success, ERROR when internal reference count mismatch or dev - * points to invalid hardware device. - * - ****************************************************************************/ - -int stm32_i2cbus_uninitialize(struct i2c_master_s *dev); - -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_STM32_I2C_H */ diff --git a/arch/arm/src/stm32f0l0g0/stm32_idle.c b/arch/arm/src/stm32f0l0g0/stm32_idle.c deleted file mode 100644 index e6f004d60995b..0000000000000 --- a/arch/arm/src/stm32f0l0g0/stm32_idle.c +++ /dev/null @@ -1,97 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_idle.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include - -#include - -#include "arm_internal.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Does the board support an IDLE LED to indicate that the board is in the - * IDLE state? - */ - -#if defined(CONFIG_ARCH_LEDS) && defined(LED_IDLE) -# define BEGIN_IDLE() board_autoled_on(LED_IDLE) -# define END_IDLE() board_autoled_off(LED_IDLE) -#else -# define BEGIN_IDLE() -# define END_IDLE() -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: up_idle - * - * Description: - * up_idle() is the logic that will be executed when there is no other - * ready-to-run task. This is processor idle time and will continue until - * some interrupt occurs to cause a context switch from the idle task. - * - * Processing in this state may be processor-specific. e.g., this is where - * power management operations might be performed. - * - ****************************************************************************/ - -void up_idle(void) -{ -#if defined(CONFIG_SUPPRESS_INTERRUPTS) || defined(CONFIG_SUPPRESS_TIMER_INTS) - /* If the system is idle and there are no timer interrupts, then process - * "fake" timer interrupts. Hopefully, something will wake up. - */ - - nxsched_process_timer(); -#else - -/* If the g_dma_inprogress is zero, then there is no DMA in progress. This - * value is needed in the IDLE loop to determine if the IDLE loop should - * go into lower power power consumption modes. According to the LPC17xx - * User Manual: "The DMA controller can continue to work in Sleep mode, and - * has access to the peripheral SRAMs and all peripheral registers. The - * flash memory and the Main SRAM are not available in Sleep mode, they are - * disabled in order to save power." - */ - -#ifdef CONFIG_STM32F0L0G0_GPDMA - if (g_dma_inprogress == 0) -#endif - { - /* Sleep until an interrupt occurs in order to save power */ - - BEGIN_IDLE(); - asm("WFI"); - END_IDLE(); - } -#endif -} diff --git a/arch/arm/src/stm32f0l0g0/stm32_irq.c b/arch/arm/src/stm32f0l0g0/stm32_irq.c deleted file mode 100644 index a6e21b8ca8e4a..0000000000000 --- a/arch/arm/src/stm32f0l0g0/stm32_irq.c +++ /dev/null @@ -1,314 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_irq.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include -#include -#include - -#include "nvic.h" -#include "arm_internal.h" - -/* #include "stm32_irq.h" */ - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Get a 32-bit version of the default priority */ - -#define DEFPRIORITY32 \ - (NVIC_SYSH_PRIORITY_DEFAULT << 24 | NVIC_SYSH_PRIORITY_DEFAULT << 16 | \ - NVIC_SYSH_PRIORITY_DEFAULT << 8 | NVIC_SYSH_PRIORITY_DEFAULT) - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_dumpnvic - * - * Description: - * Dump some interesting NVIC registers - * - ****************************************************************************/ - -#if defined(CONFIG_DEBUG_IRQ_INFO) -static void stm32_dumpnvic(const char *msg, int irq) -{ - irqstate_t flags; - - flags = enter_critical_section(); - - irqinfo("NVIC (%s, irq=%d):\n", msg, irq); - irqinfo(" ISER: %08" PRIx32 " ICER: %08" PRIx32 "\n", - getreg32(ARMV6M_NVIC_ISER), getreg32(ARMV6M_NVIC_ICER)); - irqinfo(" ISPR: %08" PRIx32 " ICPR: %08" PRIx32 "\n", - getreg32(ARMV6M_NVIC_ISPR), getreg32(ARMV6M_NVIC_ICPR)); - irqinfo(" IRQ PRIO: %08" PRIx32 " %08" PRIx32 " %08" PRIx32 - " %08" PRIx32 "\n", - getreg32(ARMV6M_NVIC_IPR0), getreg32(ARMV6M_NVIC_IPR1), - getreg32(ARMV6M_NVIC_IPR2), getreg32(ARMV6M_NVIC_IPR3)); - irqinfo(" %08" PRIx32 " %08" PRIx32 " %08" PRIx32 - " %08" PRIx32 "\n", - getreg32(ARMV6M_NVIC_IPR4), getreg32(ARMV6M_NVIC_IPR5), - getreg32(ARMV6M_NVIC_IPR6), getreg32(ARMV6M_NVIC_IPR7)); - - irqinfo("SYSCON:\n"); - irqinfo(" CPUID: %08" PRIx32 "\n", - getreg32(ARMV6M_SYSCON_CPUID)); - irqinfo(" ICSR: %08" PRIx32 " AIRCR: %08" PRIx32 "\n", - getreg32(ARMV6M_SYSCON_ICSR), getreg32(ARMV6M_SYSCON_AIRCR)); - irqinfo(" SCR: %08" PRIx32 " CCR: %08" PRIx32 "\n", - getreg32(ARMV6M_SYSCON_SCR), getreg32(ARMV6M_SYSCON_CCR)); - irqinfo(" SHPR2: %08" PRIx32 " SHPR3: %08" PRIx32 "\n", - getreg32(ARMV6M_SYSCON_SHPR2), getreg32(ARMV6M_SYSCON_SHPR3)); - - leave_critical_section(flags); -} - -#else -# define stm32_dumpnvic(msg, irq) -#endif - -/**************************************************************************** - * Name: stm32_nmi, stm32_busfault, stm32_usagefault, stm32_pendsv, - * stm32_dbgmonitor, stm32_pendsv, stm32_reserved - * - * Description: - * Handlers for various exceptions. None are handled and all are fatal - * error conditions. The only advantage these provided over the default - * unexpected interrupt handler is that they provide a diagnostic output. - * - ****************************************************************************/ - -#ifdef CONFIG_DEBUG_FEATURES -static int stm32_nmi(int irq, void *context, void *arg) -{ - up_irq_save(); - _err("PANIC!!! NMI received\n"); - PANIC(); - return 0; -} - -static int stm32_pendsv(int irq, void *context, void *arg) -{ - up_irq_save(); - _err("PANIC!!! PendSV received\n"); - PANIC(); - return 0; -} - -static int stm32_reserved(int irq, void *context, void *arg) -{ - up_irq_save(); - _err("PANIC!!! Reserved interrupt\n"); - PANIC(); - return 0; -} -#endif - -/**************************************************************************** - * Name: stm32_clrpend - * - * Description: - * Clear a pending interrupt at the NVIC. - * - ****************************************************************************/ - -static inline void stm32_clrpend(int irq) -{ - /* This will be called on each interrupt exit whether the interrupt can be - * enambled or not. So this assertion is necessarily lame. - */ - - DEBUGASSERT((unsigned)irq < NR_IRQS); - - /* Check for an external interrupt */ - - if (irq >= STM32_IRQ_EXTINT && irq < (STM32_IRQ_EXTINT + 32)) - { - /* Set the appropriate bit in the ISER register to enable the - * interrupt - */ - - putreg32((1 << (irq - STM32_IRQ_EXTINT)), ARMV6M_NVIC_ICPR); - } -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: up_irqinitialize - ****************************************************************************/ - -void up_irqinitialize(void) -{ - uint32_t regaddr; - int i; - - /* Disable all interrupts */ - - putreg32(0xffffffff, ARMV6M_NVIC_ICER); - - /* Set all interrupts (and exceptions) to the default priority */ - - putreg32(DEFPRIORITY32, ARMV6M_SYSCON_SHPR2); - putreg32(DEFPRIORITY32, ARMV6M_SYSCON_SHPR3); - - /* Now set all of the interrupt lines to the default priority */ - - for (i = 0; i < 8; i++) - { - regaddr = ARMV6M_NVIC_IPR(i); - putreg32(DEFPRIORITY32, regaddr); - } - - /* Attach the SVCall and Hard Fault exception handlers. The SVCall - * exception is used for performing context switches; The Hard Fault - * must also be caught because a SVCall may show up as a Hard Fault - * under certain conditions. - */ - - irq_attach(STM32_IRQ_SVCALL, arm_svcall, NULL); - irq_attach(STM32_IRQ_HARDFAULT, arm_hardfault, NULL); - - /* Attach all other processor exceptions (except reset and sys tick) */ - -#ifdef CONFIG_DEBUG_FEATURES - irq_attach(STM32_IRQ_NMI, stm32_nmi, NULL); - irq_attach(STM32_IRQ_PENDSV, stm32_pendsv, NULL); - irq_attach(STM32_IRQ_RESERVED, stm32_reserved, NULL); -#endif - - stm32_dumpnvic("initial", NR_IRQS); - - /* Initialize logic to support a second level of interrupt decoding for - * configured pin interrupts. - */ - -#ifdef CONFIG_STM32F0L0G0_GPIOIRQ - stm32_gpioirqinitialize(); -#endif - -#ifndef CONFIG_SUPPRESS_INTERRUPTS - - /* And finally, enable interrupts */ - - arm_color_intstack(); - up_irq_enable(); -#endif -} - -/**************************************************************************** - * Name: up_disable_irq - * - * Description: - * Disable the IRQ specified by 'irq' - * - ****************************************************************************/ - -void up_disable_irq(int irq) -{ - DEBUGASSERT((unsigned)irq < NR_IRQS); - - /* Check for an external interrupt */ - - if (irq >= STM32_IRQ_EXTINT && irq < (STM32_IRQ_EXTINT + 32)) - { - /* Set the appropriate bit in the ICER register to disable the - * interrupt - */ - - putreg32((1 << (irq - STM32_IRQ_EXTINT)), ARMV6M_NVIC_ICER); - } - - /* Handle processor exceptions. Only SysTick can be disabled */ - - else if (irq == STM32_IRQ_SYSTICK) - { - modifyreg32(ARMV6M_SYSTICK_CSR, SYSTICK_CSR_ENABLE, 0); - } - - stm32_dumpnvic("disable", irq); -} - -/**************************************************************************** - * Name: up_enable_irq - * - * Description: - * Enable the IRQ specified by 'irq' - * - ****************************************************************************/ - -void up_enable_irq(int irq) -{ - /* This will be called on each interrupt exit whether the interrupt can be - * enabled or not. So this assertion is necessarily lame. - */ - - DEBUGASSERT((unsigned)irq < NR_IRQS); - - /* Check for external interrupt */ - - if (irq >= STM32_IRQ_EXTINT && irq < (STM32_IRQ_EXTINT + 32)) - { - /* Set the appropriate bit in the ISER register to enable the - * interrupt - */ - - putreg32((1 << (irq - STM32_IRQ_EXTINT)), ARMV6M_NVIC_ISER); - } - - /* Handle processor exceptions. Only SysTick can be disabled */ - - else if (irq == STM32_IRQ_SYSTICK) - { - modifyreg32(ARMV6M_SYSTICK_CSR, 0, SYSTICK_CSR_ENABLE); - } - - stm32_dumpnvic("enable", irq); -} - -/**************************************************************************** - * Name: arm_ack_irq - * - * Description: - * Acknowledge the IRQ - * - ****************************************************************************/ - -void arm_ack_irq(int irq) -{ - stm32_clrpend(irq); -} diff --git a/arch/arm/src/stm32f0l0g0/stm32_iwdg.c b/arch/arm/src/stm32f0l0g0/stm32_iwdg.c deleted file mode 100644 index f282194202027..0000000000000 --- a/arch/arm/src/stm32f0l0g0/stm32_iwdg.c +++ /dev/null @@ -1,593 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_iwdg.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include - -#include -#include -#include -#include - -#include -#include -#include -#include -#include - -#include "arm_internal.h" -#include "stm32_rcc.h" -#include "hardware/stm32_dbgmcu.h" -#include "stm32_wdg.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Clocking *****************************************************************/ - -/* The minimum frequency of the IWDG clock is: - * - * Fmin = Flsi / 256 - * - * So the maximum delay (in milliseconds) is then: - * - * 1000 * IWDG_RLR_MAX / Fmin - * - * For example, if Flsi = 30Khz (the nominal, uncalibrated value), then the - * maximum delay is: - * - * Fmin = 117.1875 - * 1000 * 4095 / Fmin = 34,944 MSec - */ - -#define IWDG_FMIN (STM32_LSI_FREQUENCY / 256) -#define IWDG_MAXTIMEOUT (1000 * IWDG_RLR_MAX / IWDG_FMIN) - -/* Configuration ************************************************************/ - -/* REVISIT: It appears that you can only setup the prescaler and reload - * registers once. After that, the SR register's PVU and RVU bits never go - * to zero. So we defer setting up these registers until the watchdog - * is started, then refuse any further attempts to change timeout. - */ - -#define CONFIG_STM32_IWDG_ONETIMESETUP 1 - -/* REVISIT: Another possibility is that we CAN change the prescaler and - * reload values after starting the timer. This option is untested but the - * implementation place conditioned on the following: - */ - -#undef CONFIG_STM32_IWDG_DEFERREDSETUP - -/* But you can only try one at a time */ - -#if defined(CONFIG_STM32_IWDG_ONETIMESETUP) && defined(CONFIG_STM32_IWDG_DEFERREDSETUP) -# error "Both CONFIG_STM32_IWDG_ONETIMESETUP and CONFIG_STM32_IWDG_DEFERREDSETUP are defined" -#endif - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/* This structure provides the private representation of the "lower-half" - * driver state structure. This structure must be cast-compatible with the - * well-known watchdog_lowerhalf_s structure. - */ - -struct stm32_lowerhalf_s -{ - const struct watchdog_ops_s *ops; /* Lower half operations */ - uint32_t lsifreq; /* The calibrated frequency of the LSI oscillator */ - uint32_t timeout; /* The (actual) selected timeout */ - uint32_t lastreset; /* The last reset time */ - bool started; /* true: The watchdog timer has been started */ - uint8_t prescaler; /* Clock prescaler value */ - uint16_t reload; /* Timer reload value */ -}; - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -/* Register operations ******************************************************/ - -static inline void stm32_setprescaler(struct stm32_lowerhalf_s *priv); - -/* "Lower half" driver methods **********************************************/ - -static int stm32_start(struct watchdog_lowerhalf_s *lower); -static int stm32_stop(struct watchdog_lowerhalf_s *lower); -static int stm32_keepalive(struct watchdog_lowerhalf_s *lower); -static int stm32_getstatus(struct watchdog_lowerhalf_s *lower, - struct watchdog_status_s *status); -static int stm32_settimeout(struct watchdog_lowerhalf_s *lower, - uint32_t timeout); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* "Lower half" driver methods */ - -static const struct watchdog_ops_s g_wdgops = -{ - .start = stm32_start, - .stop = stm32_stop, - .keepalive = stm32_keepalive, - .getstatus = stm32_getstatus, - .settimeout = stm32_settimeout, - .capture = NULL, - .ioctl = NULL, -}; - -/* "Lower half" driver state */ - -static struct stm32_lowerhalf_s g_wdgdev; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_setprescaler - * - * Description: - * Set up the prescaler and reload values. This seems to be something - * that can only be done one time. - * - * Input Parameters: - * priv - A pointer the internal representation of the "lower-half" - * driver state structure. - * - ****************************************************************************/ - -static inline void stm32_setprescaler(struct stm32_lowerhalf_s *priv) -{ - /* Enable write access to IWDG_PR and IWDG_RLR registers */ - - putreg32(IWDG_KR_KEY_ENABLE, STM32_IWDG_KR); - - /* Wait for the PVU and RVU bits to be reset be hardware. These bits - * were set the last time that the PR register was written and may not - * yet be cleared. - * - * If the setup is only permitted one time, then this wait should not - * be necessary. - */ - -#ifndef CONFIG_STM32_IWDG_ONETIMESETUP - while ((getreg32(STM32_IWDG_SR) & (IWDG_SR_PVU | IWDG_SR_RVU)) != 0); -#endif - - /* Set the prescaler */ - - putreg32((uint16_t)priv->prescaler << IWDG_PR_SHIFT, STM32_IWDG_PR); - - /* Set the reload value */ - - putreg32((uint16_t)priv->reload, STM32_IWDG_RLR); - - /* Reload the counter (and disable write access) */ - - putreg32(IWDG_KR_KEY_RELOAD, STM32_IWDG_KR); -} - -/**************************************************************************** - * Name: stm32_start - * - * Description: - * Start the watchdog timer, resetting the time to the current timeout, - * - * Input Parameters: - * lower - A pointer the publicly visible representation of the - * "lower-half" driver state structure. - * - * Returned Value: - * Zero on success; a negated errno value on failure. - * - ****************************************************************************/ - -static int stm32_start(struct watchdog_lowerhalf_s *lower) -{ - struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; - irqstate_t flags; - - wdinfo("Entry: started\n"); - DEBUGASSERT(priv); - - /* Have we already been started? */ - - if (!priv->started) - { - /* REVISIT: It appears that you can only setup the prescaler and reload - * registers once. After that, the SR register's PVU and RVU bits never - * go to 0. So we defer setting up these registers until the watchdog - * is started, then refuse any further attempts to change timeout. - */ - - /* Set up prescaler and reload value for the selected timeout before - * starting the watchdog timer. - */ - -#if defined(CONFIG_STM32_IWDG_ONETIMESETUP) || defined(CONFIG_STM32_IWDG_DEFERREDSETUP) - stm32_setprescaler(priv); -#endif - - /* Enable IWDG (the LSI oscillator will be enabled by hardware). NOTE: - * If the "Hardware watchdog" feature is enabled through the device - * option bits, the watchdog is automatically enabled at power-on. - */ - - flags = enter_critical_section(); - putreg32(IWDG_KR_KEY_START, STM32_IWDG_KR); - priv->lastreset = clock_systime_ticks(); - priv->started = true; - leave_critical_section(flags); - } - - return OK; -} - -/**************************************************************************** - * Name: stm32_stop - * - * Description: - * Stop the watchdog timer - * - * Input Parameters: - * lower - A pointer the publicly visible representation of the - * "lower-half" driver state structure. - * - * Returned Value: - * Zero on success; a negated errno value on failure. - * - ****************************************************************************/ - -static int stm32_stop(struct watchdog_lowerhalf_s *lower) -{ - /* There is no way to disable the IDWG timer once it has been started */ - - wdinfo("Entry\n"); - return -ENOSYS; -} - -/**************************************************************************** - * Name: stm32_keepalive - * - * Description: - * Reset the watchdog timer to the current timeout value, prevent any - * imminent watchdog timeouts. This is sometimes referred as "pinging" - * the watchdog timer or "petting the dog". - * - * Input Parameters: - * lower - A pointer the publicly visible representation of the - * "lower-half" driver state structure. - * - * Returned Value: - * Zero on success; a negated errno value on failure. - * - ****************************************************************************/ - -static int stm32_keepalive(struct watchdog_lowerhalf_s *lower) -{ - struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; - irqstate_t flags; - - wdinfo("Entry\n"); - - /* Reload the IWDG timer */ - - flags = enter_critical_section(); - putreg32(IWDG_KR_KEY_RELOAD, STM32_IWDG_KR); - priv->lastreset = clock_systime_ticks(); - leave_critical_section(flags); - - return OK; -} - -/**************************************************************************** - * Name: stm32_getstatus - * - * Description: - * Get the current watchdog timer status - * - * Input Parameters: - * lower - A pointer the publicly visible representation of the - * "lower-half" driver state structure. - * status - The location to return the watchdog status information. - * - * Returned Value: - * Zero on success; a negated errno value on failure. - * - ****************************************************************************/ - -static int stm32_getstatus(struct watchdog_lowerhalf_s *lower, - struct watchdog_status_s *status) -{ - struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; - uint32_t ticks; - uint32_t elapsed; - - wdinfo("Entry\n"); - DEBUGASSERT(priv); - - /* Return the status bit */ - - status->flags = WDFLAGS_RESET; - if (priv->started) - { - status->flags |= WDFLAGS_ACTIVE; - } - - /* Return the actual timeout in milliseconds */ - - status->timeout = priv->timeout; - - /* Get the elapsed time since the last ping */ - - ticks = clock_systime_ticks() - priv->lastreset; - elapsed = (int32_t)TICK2MSEC(ticks); - - if (elapsed > priv->timeout) - { - elapsed = priv->timeout; - } - - /* Return the approximate time until the watchdog timer expiration */ - - status->timeleft = priv->timeout - elapsed; - - wdinfo("Status :\n"); - wdinfo(" flags : %08" PRIx32 "\n", status->flags); - wdinfo(" timeout : %" PRId32 "\n", status->timeout); - wdinfo(" timeleft : %" PRId32 "\n", status->timeleft); - return OK; -} - -/**************************************************************************** - * Name: stm32_settimeout - * - * Description: - * Set a new timeout value (and reset the watchdog timer) - * - * Input Parameters: - * lower - A pointer the publicly visible representation of the - * "lower-half" driver state structure. - * timeout - The new timeout value in milliseconds. - * - * Returned Value: - * Zero on success; a negated errno value on failure. - * - ****************************************************************************/ - -static int stm32_settimeout(struct watchdog_lowerhalf_s *lower, - uint32_t timeout) -{ - struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; - uint32_t fiwdg; - uint64_t reload; - int prescaler; - int shift; - - wdinfo("Entry: timeout=%" PRId32 "\n", timeout); - DEBUGASSERT(priv); - - /* Can this timeout be represented? */ - - if (timeout < 1 || timeout > IWDG_MAXTIMEOUT) - { - wderr("ERROR: Cannot represent timeout=%" PRId32 " > %d\n", - timeout, IWDG_MAXTIMEOUT); - return -ERANGE; - } - - /* REVISIT: It appears that you can only setup the prescaler and reload - * registers once. After that, the SR register's PVU and RVU bits never go - * to zero. - */ - -#ifdef CONFIG_STM32_IWDG_ONETIMESETUP - if (priv->started) - { - wdwarn("WARNING: Timer is already started\n"); - return -EBUSY; - } -#endif - - /* Select the smallest prescaler that will result in a reload value that is - * less than the maximum. - */ - - for (prescaler = 0; ; prescaler++) - { - /* PR = 0 -> Divider = 4 = 1 << 2 - * PR = 1 -> Divider = 8 = 1 << 3 - * PR = 2 -> Divider = 16 = 1 << 4 - * PR = 3 -> Divider = 32 = 1 << 5 - * PR = 4 -> Divider = 64 = 1 << 6 - * PR = 5 -> Divider = 128 = 1 << 7 - * PR = 6 -> Divider = 256 = 1 << 8 - * PR = n -> Divider = 1 << (n+2) - */ - - shift = prescaler + 2; - - /* Get the IWDG counter frequency in Hz. For a nominal 32Khz LSI clock, - * this is value in the range of 7500 and 125. - */ - - fiwdg = priv->lsifreq >> shift; - - /* We want: - * 1000 * reload / Fiwdg = timeout - * Or: - * reload = Fiwdg * timeout / 1000 - */ - - reload = (uint64_t)fiwdg * (uint64_t)timeout / 1000; - - /* If this reload valid is less than the maximum or we are not ready - * at the prescaler value, then break out of the loop to use these - * settings. - */ - - if (reload <= IWDG_RLR_MAX || prescaler == 6) - { - /* Note that we explicitly break out of the loop rather than using - * the 'for' loop termination logic because we do not want the - * value of prescaler to be incremented. - */ - - break; - } - } - - /* Make sure that the final reload value is within range */ - - if (reload > IWDG_RLR_MAX) - { - reload = IWDG_RLR_MAX; - } - - /* Get the actual timeout value in milliseconds. - * - * We have: - * reload = Fiwdg * timeout / 1000 - * So we want: - * timeout = 1000 * reload / Fiwdg - */ - - priv->timeout = (1000 * (uint32_t)reload) / fiwdg; - - /* Save setup values for later use */ - - priv->prescaler = prescaler; - priv->reload = reload; - - /* Write the prescaler and reload values to the IWDG registers. - * - * REVISIT: It appears that you can only setup the prescaler and reload - * registers once. After that, the SR register's PVU and RVU bits never go - * to zero. - */ - -#ifndef CONFIG_STM32_IWDG_ONETIMESETUP - /* If CONFIG_STM32_IWDG_DEFERREDSETUP is selected, then perform the - * register configuration only if the timer has been started. - */ - -#ifdef CONFIG_STM32_IWDG_DEFERREDSETUP - if (priv->started) -#endif - { - stm32_setprescaler(priv); - } -#endif - - wdinfo("prescaler=%d fiwdg=%" PRId32 " reload=%" PRId64 "\n", - prescaler, fiwdg, reload); - - return OK; -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_iwdginitialize - * - * Description: - * Initialize the IWDG watchdog timer. The watchdog timer is initialized - * and registers as 'devpath'. The initial state of the watchdog timer is - * disabled. - * - * Input Parameters: - * devpath - The full path to the watchdog. This should be of the form - * /dev/watchdog0 - * lsifreq - The calibrated LSI clock frequency - * - * Returned Value: - * None - * - ****************************************************************************/ - -void stm32_iwdginitialize(const char *devpath, uint32_t lsifreq) -{ - struct stm32_lowerhalf_s *priv = &g_wdgdev; - - wdinfo("Entry: devpath=%s lsifreq=%" PRId32 "\n", devpath, lsifreq); - - /* NOTE we assume that clocking to the IWDG has already been provided by - * the RCC initialization logic. - */ - - /* Initialize the driver state structure. */ - - priv->ops = &g_wdgops; - priv->lsifreq = lsifreq; - priv->started = false; - - /* Make sure that the LSI oscillator is enabled. NOTE: The LSI oscillator - * is enabled here but is not disabled by this file, because this file does - * not know the global usage of the oscillator. Any clock management - * logic (say, as part of a power management scheme) needs handle other - * LSI controls outside of this file. - */ - - stm32_rcc_enablelsi(); -#ifdef STM32_RCC_CSR - wdinfo("RCC CSR: %08" PRIx32 "\n", getreg32(STM32_RCC_CSR)); -#else - wdinfo("RCC CSR: %08" PRIx32 "\n", getreg32(STM32_RCC_CSR1)); -#endif - - /* Select an arbitrary initial timeout value. But don't start the watchdog - * yet. NOTE: If the "Hardware watchdog" feature is enabled through the - * device option bits, the watchdog is automatically enabled at power-on. - */ - - stm32_settimeout((struct watchdog_lowerhalf_s *)priv, IWDG_MAXTIMEOUT); - - /* Register the watchdog driver as /dev/watchdog0 */ - - watchdog_register(devpath, (struct watchdog_lowerhalf_s *)priv); - - /* When the microcontroller enters debug mode (core halted), - * the IWDG counter either continues to work normally or stops, depending - * on DBG_IWDG_STOP configuration bit in DBG module. - */ - -#ifdef CONFIG_DEBUG_FEATURES - { - uint32_t cr = getreg32(STM32_DBGMCU_APB1_FZ); - cr |= DBGMCU_APB1_IWDGSTOP; - putreg32(cr, STM32_DBGMCU_APB1_FZ); - } -#endif -} diff --git a/arch/arm/src/stm32f0l0g0/stm32_lowputc.c b/arch/arm/src/stm32f0l0g0/stm32_lowputc.c deleted file mode 100644 index b15eb7eb39f4e..0000000000000 --- a/arch/arm/src/stm32f0l0g0/stm32_lowputc.c +++ /dev/null @@ -1,40 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_lowputc.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include "chip.h" - -#if defined(CONFIG_STM32F0L0G0_HAVE_IP_USART_V1) -# include "stm32_lowputc_v1.c" -#elif defined(CONFIG_STM32F0L0G0_HAVE_IP_USART_V2) -# include "stm32_lowputc_v2.c" -#else -# error "Unsupported STM32 M0 serial" -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ diff --git a/arch/arm/src/stm32f0l0g0/stm32_lowputc.h b/arch/arm/src/stm32f0l0g0/stm32_lowputc.h deleted file mode 100644 index 8158c50f81339..0000000000000 --- a/arch/arm/src/stm32f0l0g0/stm32_lowputc.h +++ /dev/null @@ -1,66 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_lowputc.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_STM32_LOWPUTC_H -#define __ARCH_ARM_SRC_STM32F0L0G0_STM32_LOWPUTC_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "chip.h" - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -#ifndef __ASSEMBLY__ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Name: stm32_lowsetup - * - * Description: - * Called at the very beginning of _start. Performs low level - * initialization of serial console. - * - ****************************************************************************/ - -void stm32_lowsetup(void); - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_STM32_LOWPUTC_H */ diff --git a/arch/arm/src/stm32f0l0g0/stm32_lowputc_v1.c b/arch/arm/src/stm32f0l0g0/stm32_lowputc_v1.c deleted file mode 100644 index 81bcd23faf2e9..0000000000000 --- a/arch/arm/src/stm32f0l0g0/stm32_lowputc_v1.c +++ /dev/null @@ -1,394 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_lowputc_v1.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include - -#include "arm_internal.h" -#include "chip.h" - -#include "stm32_rcc.h" -#include "stm32_gpio.h" -#include "stm32_uart.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Select USART parameters for the selected console */ - -#ifdef HAVE_CONSOLE -# if defined(CONFIG_USART1_SERIAL_CONSOLE) -# define STM32_CONSOLE_BASE STM32_USART1_BASE -# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY -# define STM32_CONSOLE_BAUD CONFIG_USART1_BAUD -# define STM32_CONSOLE_BITS CONFIG_USART1_BITS -# define STM32_CONSOLE_PARITY CONFIG_USART1_PARITY -# define STM32_CONSOLE_2STOP CONFIG_USART1_2STOP -# ifdef CONFIG_USART1_RS485 -# define STM32_CONSOLE_RS485_DIR GPIO_USART1_RS485_DIR -# if (CONFIG_USART1_RS485_DIR_POLARITY == 0) -# define STM32_CONSOLE_RS485_DIR_POLARITY false -# else -# define STM32_CONSOLE_RS485_DIR_POLARITY true -# endif -# endif -# elif defined(CONFIG_USART2_SERIAL_CONSOLE) -# define STM32_CONSOLE_BASE STM32_USART2_BASE -# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY -# define STM32_CONSOLE_BAUD CONFIG_USART2_BAUD -# define STM32_CONSOLE_BITS CONFIG_USART2_BITS -# define STM32_CONSOLE_PARITY CONFIG_USART2_PARITY -# define STM32_CONSOLE_2STOP CONFIG_USART2_2STOP -# ifdef CONFIG_USART2_RS485 -# define STM32_CONSOLE_RS485_DIR GPIO_USART2_RS485_DIR -# if (CONFIG_USART2_RS485_DIR_POLARITY == 0) -# define STM32_CONSOLE_RS485_DIR_POLARITY false -# else -# define STM32_CONSOLE_RS485_DIR_POLARITY true -# endif -# endif -# elif defined(CONFIG_USART3_SERIAL_CONSOLE) -# define STM32_CONSOLE_BASE STM32_USART3_BASE -# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY -# define STM32_CONSOLE_BAUD CONFIG_USART3_BAUD -# define STM32_CONSOLE_BITS CONFIG_USART3_BITS -# define STM32_CONSOLE_PARITY CONFIG_USART3_PARITY -# define STM32_CONSOLE_2STOP CONFIG_USART3_2STOP -# ifdef CONFIG_USART3_RS485 -# define STM32_CONSOLE_RS485_DIR GPIO_USART3_RS485_DIR -# if (CONFIG_USART3_RS485_DIR_POLARITY == 0) -# define STM32_CONSOLE_RS485_DIR_POLARITY false -# else -# define STM32_CONSOLE_RS485_DIR_POLARITY true -# endif -# endif -# elif defined(CONFIG_USART4_SERIAL_CONSOLE) -# define STM32_CONSOLE_BASE STM32_USART4_BASE -# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY -# define STM32_CONSOLE_BAUD CONFIG_USART4_BAUD -# define STM32_CONSOLE_BITS CONFIG_USART4_BITS -# define STM32_CONSOLE_PARITY CONFIG_USART4_PARITY -# define STM32_CONSOLE_2STOP CONFIG_USART4_2STOP -# ifdef CONFIG_USART4_RS485 -# define STM32_CONSOLE_RS485_DIR GPIO_USART4_RS485_DIR -# if (CONFIG_USART4_RS485_DIR_POLARITY == 0) -# define STM32_CONSOLE_RS485_DIR_POLARITY false -# else -# define STM32_CONSOLE_RS485_DIR_POLARITY true -# endif -# endif -# elif defined(CONFIG_USART5_SERIAL_CONSOLE) -# define STM32_CONSOLE_BASE STM32_USART5_BASE -# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY -# define STM32_CONSOLE_BAUD CONFIG_USART5_BAUD -# define STM32_CONSOLE_BITS CONFIG_USART5_BITS -# define STM32_CONSOLE_PARITY CONFIG_USART5_PARITY -# define STM32_CONSOLE_2STOP CONFIG_USART5_2STOP -# ifdef CONFIG_USART5_RS485 -# define STM32_CONSOLE_RS485_DIR GPIO_USART5_RS485_DIR -# if (CONFIG_USART5_RS485_DIR_POLARITY == 0) -# define STM32_CONSOLE_RS485_DIR_POLARITY false -# else -# define STM32_CONSOLE_RS485_DIR_POLARITY true -# endif -# endif -# endif - - /* CR1 settings */ - -# if STM32_CONSOLE_BITS == 9 -# define USART_CR1_M0_VALUE USART_CR1_M0 -# define USART_CR1_M1_VALUE 0 -# elif STM32_CONSOLE_BITS == 7 -# define USART_CR1_M0_VALUE 0 -# define USART_CR1_M1_VALUE USART_CR1_M1 -# else /* 8 bits */ -# define USART_CR1_M0_VALUE 0 -# define USART_CR1_M1_VALUE 0 -# endif - -# if STM32_CONSOLE_PARITY == 1 /* odd parity */ -# define USART_CR1_PARITY_VALUE (USART_CR1_PCE|USART_CR1_PS) -# elif STM32_CONSOLE_PARITY == 2 /* even parity */ -# define USART_CR1_PARITY_VALUE USART_CR1_PCE -# else /* no parity */ -# define USART_CR1_PARITY_VALUE 0 -# endif - -# define USART_CR1_CLRBITS \ - (USART_CR1_UESM | USART_CR1_RE | USART_CR1_TE | USART_CR1_PS | \ - USART_CR1_PCE | USART_CR1_WAKE | USART_CR1_M0 | USART_CR1_M1 | \ - USART_CR1_MME | USART_CR1_OVER8 | USART_CR1_DEDT_MASK | \ - USART_CR1_DEAT_MASK | USART_CR1_ALLINTS) - -# define USART_CR1_SETBITS (USART_CR1_M0_VALUE|USART_CR1_M1_VALUE|USART_CR1_PARITY_VALUE) - - /* CR2 settings */ - -# if STM32_CONSOLE_2STOP != 0 -# define USART_CR2_STOP2_VALUE USART_CR2_STOP2 -# else -# define USART_CR2_STOP2_VALUE 0 -# endif - -# define USART_CR2_CLRBITS \ - (USART_CR2_ADDM7 | USART_CR2_LBDL | USART_CR2_LBDIE | USART_CR2_LBCL | \ - USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_CLKEN | USART_CR2_STOP_MASK | \ - USART_CR2_LINEN | USART_CR2_SWAP | USART_CR2_RXINV | USART_CR2_TXINV | \ - USART_CR2_DATAINV | USART_CR2_MSBFIRST | USART_CR2_ABREN | \ - USART_CR2_ABRMOD_MASK | USART_CR2_RTOEN | USART_CR2_ADD_MASK) - -# define USART_CR2_SETBITS USART_CR2_STOP2_VALUE - - /* CR3 settings */ - -# define USART_CR3_CLRBITS \ - (USART_CR3_EIE | USART_CR3_IREN | USART_CR3_IRLP | USART_CR3_HDSEL | \ - USART_CR3_NACK | USART_CR3_SCEN | USART_CR3_DMAR | USART_CR3_DMAT | \ - USART_CR3_RTSE | USART_CR3_CTSE | USART_CR3_CTSIE | USART_CR3_ONEBIT | \ - USART_CR3_OVRDIS | USART_CR3_DDRE | USART_CR3_DEM | USART_CR3_DEP | \ - USART_CR3_SCARCNT_MASK | USART_CR3_WUS_MASK | USART_CR3_WUFIE) - -# define USART_CR3_SETBITS 0 - -# undef USE_OVER8 - - /* Calculate USART BAUD rate divider */ - - /* Baud rate for standard USART (SPI mode included): - * - * In case of oversampling by 16, the equation is: - * baud = fCK / UARTDIV - * UARTDIV = fCK / baud - * - * In case of oversampling by 8, the equation is: - * - * baud = 2 * fCK / UARTDIV - * UARTDIV = 2 * fCK / baud - */ - -# define STM32_USARTDIV8 \ - (((STM32_APBCLOCK << 1) + (STM32_CONSOLE_BAUD >> 1)) / STM32_CONSOLE_BAUD) -# define STM32_USARTDIV16 \ - ((STM32_APBCLOCK + (STM32_CONSOLE_BAUD >> 1)) / STM32_CONSOLE_BAUD) - -/* Use oversamply by 8 only if the divisor is small. But what is small? */ - -# if STM32_USARTDIV8 > 100 -# define STM32_BRR_VALUE STM32_USARTDIV16 -# else -# define USE_OVER8 1 -# define STM32_BRR_VALUE \ - ((STM32_USARTDIV8 & 0xfff0) | ((STM32_USARTDIV8 & 0x000f) >> 1)) -# endif - -#endif /* HAVE_CONSOLE */ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: arm_lowputc - * - * Description: - * Output one byte on the serial console - * - ****************************************************************************/ - -void arm_lowputc(char ch) -{ -#ifdef HAVE_CONSOLE - /* Wait until the TX data register is empty */ - - while ((getreg32(STM32_CONSOLE_BASE + STM32_USART_ISR_OFFSET) & - USART_ISR_TXE) == 0); -#ifdef STM32_CONSOLE_RS485_DIR - stm32_gpiowrite(STM32_CONSOLE_RS485_DIR, - STM32_CONSOLE_RS485_DIR_POLARITY); -#endif - - /* Then send the character */ - - putreg32((uint32_t)ch, STM32_CONSOLE_BASE + STM32_USART_TDR_OFFSET); - -#ifdef STM32_CONSOLE_RS485_DIR - while ((getreg32(STM32_CONSOLE_BASE + STM32_USART_ISR_OFFSET) & - USART_ISR_TC) == 0); - stm32_gpiowrite(STM32_CONSOLE_RS485_DIR, - !STM32_CONSOLE_RS485_DIR_POLARITY); -#endif - -#endif /* HAVE_CONSOLE */ -} - -/**************************************************************************** - * Name: stm32_lowsetup - * - * Description: - * This performs basic initialization of the USART used for the serial - * console. Its purpose is to get the console output available as soon - * as possible. - * - ****************************************************************************/ - -void stm32_lowsetup(void) -{ -#if defined(HAVE_USART) -#if defined(HAVE_CONSOLE) && !defined(CONFIG_SUPPRESS_UART_CONFIG) - uint32_t cr; -#endif - - /* Setup clocking and GPIO pins for all configured USARTs */ - -#ifdef CONFIG_STM32F0L0G0_USART1 - /* Enable USART APB2 clock */ - - modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_USART1EN); - - /* Configure RX/TX pins */ - - stm32_configgpio(GPIO_USART1_TX); - stm32_configgpio(GPIO_USART1_RX); - -#ifdef CONFIG_USART1_RS485 - stm32_configgpio(GPIO_USART1_RS485_DIR); - stm32_gpiowrite(GPIO_USART1_RS485_DIR, !CONFIG_USART1_RS485_DIR_POLARITY); -#endif -#endif - -#ifdef CONFIG_STM32F0L0G0_USART2 - /* Enable USART APB1 clock */ - - modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_USART2EN); - - /* Configure RX/TX pins */ - - stm32_configgpio(GPIO_USART2_TX); - stm32_configgpio(GPIO_USART2_RX); - -#ifdef CONFIG_USART2_RS485 - stm32_configgpio(GPIO_USART2_RS485_DIR); - stm32_gpiowrite(GPIO_USART2_RS485_DIR, !CONFIG_USART2_RS485_DIR_POLARITY); -#endif -#endif - -#ifdef CONFIG_STM32F0L0G0_USART3 - /* Enable USART APB1 clock */ - - modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_USART3EN); - - /* Configure RX/TX pins */ - - stm32_configgpio(GPIO_USART3_TX); - stm32_configgpio(GPIO_USART3_RX); - -#ifdef CONFIG_USART3_RS485 - stm32_configgpio(GPIO_USART3_RS485_DIR); - stm32_gpiowrite(GPIO_USART3_RS485_DIR, !CONFIG_USART3_RS485_DIR_POLARITY); -#endif -#endif - -#ifdef CONFIG_STM32F0L0G0_USART4 - /* Enable USART APB1 clock */ - - modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_USART4EN); - - /* Configure RX/TX pins */ - - stm32_configgpio(GPIO_USART4_TX); - stm32_configgpio(GPIO_USART4_RX); - -#ifdef CONFIG_USART4_RS485 - stm32_configgpio(GPIO_USART4_RS485_DIR); - stm32_gpiowrite(GPIO_USART4_RS485_DIR, !CONFIG_USART4_RS485_DIR_POLARITY); -#endif -#endif - -#ifdef CONFIG_STM32F0L0G0_USART5 - /* Enable USART APB1 clock */ - - modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_USART5EN); - - /* Configure RX/TX pins */ - - stm32_configgpio(GPIO_USART5_TX); - stm32_configgpio(GPIO_USART5_RX); - -#ifdef CONFIG_USART5_RS485 - stm32_configgpio(GPIO_USART5_RS485_DIR); - stm32_gpiowrite(GPIO_USART5_RS485_DIR, !CONFIG_USART5_RS485_DIR_POLARITY); -#endif -#endif - - /* Enable and configure the selected console device */ - -#if defined(HAVE_CONSOLE) && !defined(CONFIG_SUPPRESS_UART_CONFIG) - /* Configure CR2 */ - - cr = getreg32(STM32_CONSOLE_BASE + STM32_USART_CR2_OFFSET); - cr &= ~USART_CR2_CLRBITS; - cr |= USART_CR2_SETBITS; - putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR2_OFFSET); - - /* Configure CR1 */ - - cr = getreg32(STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET); - cr &= ~USART_CR1_CLRBITS; - cr |= USART_CR1_SETBITS; - putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET); - - /* Configure CR3 */ - - cr = getreg32(STM32_CONSOLE_BASE + STM32_USART_CR3_OFFSET); - cr &= ~USART_CR3_CLRBITS; - cr |= USART_CR3_SETBITS; - putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR3_OFFSET); - - /* Configure the USART Baud Rate */ - - putreg32(STM32_BRR_VALUE, STM32_CONSOLE_BASE + STM32_USART_BRR_OFFSET); - - /* Select oversampling by 8 */ - - cr = getreg32(STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET); -#ifdef USE_OVER8 - cr |= USART_CR1_OVER8; - putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET); -#endif - - /* Enable Rx, Tx, and the USART */ - - cr |= (USART_CR1_UE | USART_CR1_TE | USART_CR1_RE); - putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET); - -#endif /* HAVE_CONSOLE && !CONFIG_SUPPRESS_UART_CONFIG */ -#endif /* HAVE_USART */ -} diff --git a/arch/arm/src/stm32f0l0g0/stm32_lowputc_v2.c b/arch/arm/src/stm32f0l0g0/stm32_lowputc_v2.c deleted file mode 100644 index db8065517c3f1..0000000000000 --- a/arch/arm/src/stm32f0l0g0/stm32_lowputc_v2.c +++ /dev/null @@ -1,354 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_lowputc_v2.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include "arm_internal.h" -#include "chip.h" - -#include "hardware/stm32_pinmap.h" -#include "stm32_rcc.h" -#include "stm32_gpio.h" -#include "stm32_uart.h" - -#include - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Select USART parameters for the selected console */ - -#ifdef HAVE_CONSOLE -# if defined(CONFIG_USART1_SERIAL_CONSOLE) -# define STM32_CONSOLE_BASE STM32_USART1_BASE -# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY -# define STM32_CONSOLE_APBREG STM32_RCC_APB2ENR -# define STM32_CONSOLE_APBEN RCC_APB2ENR_USART1EN -# define STM32_CONSOLE_BAUD CONFIG_USART1_BAUD -# define STM32_CONSOLE_BITS CONFIG_USART1_BITS -# define STM32_CONSOLE_PARITY CONFIG_USART1_PARITY -# define STM32_CONSOLE_2STOP CONFIG_USART1_2STOP -# define STM32_CONSOLE_TX GPIO_USART1_TX -# define STM32_CONSOLE_RX GPIO_USART1_RX -# ifdef CONFIG_USART1_RS485 -# define STM32_CONSOLE_RS485_DIR GPIO_USART1_RS485_DIR -# if (CONFIG_USART1_RS485_DIR_POLARITY == 0) -# define STM32_CONSOLE_RS485_DIR_POLARITY false -# else -# define STM32_CONSOLE_RS485_DIR_POLARITY true -# endif -# endif -# elif defined(CONFIG_USART2_SERIAL_CONSOLE) -# define STM32_CONSOLE_BASE STM32_USART2_BASE -# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY -# define STM32_CONSOLE_APBREG STM32_RCC_APB1ENR -# define STM32_CONSOLE_APBEN RCC_APB1ENR_USART2EN -# define STM32_CONSOLE_BAUD CONFIG_USART2_BAUD -# define STM32_CONSOLE_BITS CONFIG_USART2_BITS -# define STM32_CONSOLE_PARITY CONFIG_USART2_PARITY -# define STM32_CONSOLE_2STOP CONFIG_USART2_2STOP -# define STM32_CONSOLE_TX GPIO_USART2_TX -# define STM32_CONSOLE_RX GPIO_USART2_RX -# ifdef CONFIG_USART2_RS485 -# define STM32_CONSOLE_RS485_DIR GPIO_USART2_RS485_DIR -# if (CONFIG_USART2_RS485_DIR_POLARITY == 0) -# define STM32_CONSOLE_RS485_DIR_POLARITY false -# else -# define STM32_CONSOLE_RS485_DIR_POLARITY true -# endif -# endif -# elif defined(CONFIG_USART3_SERIAL_CONSOLE) -# define STM32_CONSOLE_BASE STM32_USART3_BASE -# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY -# define STM32_CONSOLE_APBREG STM32_RCC_APB1ENR -# define STM32_CONSOLE_APBEN RCC_APB1ENR_USART3EN -# define STM32_CONSOLE_BAUD CONFIG_USART3_BAUD -# define STM32_CONSOLE_BITS CONFIG_USART3_BITS -# define STM32_CONSOLE_PARITY CONFIG_USART3_PARITY -# define STM32_CONSOLE_2STOP CONFIG_USART3_2STOP -# define STM32_CONSOLE_TX GPIO_USART3_TX -# define STM32_CONSOLE_RX GPIO_USART3_RX -# ifdef CONFIG_USART3_RS485 -# define STM32_CONSOLE_RS485_DIR GPIO_USART3_RS485_DIR -# if (CONFIG_USART3_RS485_DIR_POLARITY == 0) -# define STM32_CONSOLE_RS485_DIR_POLARITY false -# else -# define STM32_CONSOLE_RS485_DIR_POLARITY true -# endif -# endif -# elif defined(CONFIG_USART4_SERIAL_CONSOLE) -# define STM32_CONSOLE_BASE STM32_USART4_BASE -# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY -# define STM32_CONSOLE_APBREG STM32_RCC_APB1ENR -# define STM32_CONSOLE_APBEN RCC_APB1ENR_USART4EN -# define STM32_CONSOLE_BAUD CONFIG_USART4_BAUD -# define STM32_CONSOLE_BITS CONFIG_USART4_BITS -# define STM32_CONSOLE_PARITY CONFIG_USART4_PARITY -# define STM32_CONSOLE_2STOP CONFIG_USART4_2STOP -# define STM32_CONSOLE_TX GPIO_USART4_TX -# define STM32_CONSOLE_RX GPIO_USART4_RX -# ifdef CONFIG_USART4_RS485 -# define STM32_CONSOLE_RS485_DIR GPIO_USART4_RS485_DIR -# if (CONFIG_USART4_RS485_DIR_POLARITY == 0) -# define STM32_CONSOLE_RS485_DIR_POLARITY false -# else -# define STM32_CONSOLE_RS485_DIR_POLARITY true -# endif -# endif -# endif - - /* CR1 settings */ - -# if STM32_CONSOLE_BITS == 7 -# define USART_CR_M01_VALUE USART_CR1_M1 -# elif STM32_CONSOLE_BITS == 9 -# define USART_CR_M01_VALUE USART_CR1_M0 -# else /* STM32_CONSOLE_BITS == 8 */ -# define USART_CR_M01_VALUE 0 -# endif - -# if STM32_CONSOLE_PARITY == 1 -# define USART_CR1_PARITY_VALUE (USART_CR1_PCE|USART_CR1_PS) -# elif STM32_CONSOLE_PARITY == 2 -# define USART_CR1_PARITY_VALUE USART_CR1_PCE -# else -# define USART_CR1_PARITY_VALUE 0 -# endif - -# define USART_CR1_CLRBITS \ - (USART_CR1_RE | USART_CR1_TE | USART_CR1_PS | USART_CR1_PCE | \ - USART_CR1_WAKE | USART_CR1_M0 | USART_CR1_MME | USART_CR1_OVER8 | \ - USART_CR1_DEDT_MASK | USART_CR1_DEAT_MASK | USART_CR1_ALLINTS) - -# define USART_CR1_SETBITS (USART_CR_M01_VALUE | USART_CR1_PARITY_VALUE) - - /* CR2 settings */ - -# if STM32_CONSOLE_2STOP != 0 -# define USART_CR2_STOP2_VALUE USART_CR2_STOP2 -# else -# define USART_CR2_STOP2_VALUE 0 -# endif - -# define USART_CR2_CLRBITS \ - (USART_CR2_ADDM7 | USART_CR2_LBDL | USART_CR2_LBDIE | USART_CR2_LBCL | \ - USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_CLKEN | USART_CR2_STOP_MASK | \ - USART_CR2_LINEN | USART_CR2_RXINV | USART_CR2_TXINV | USART_CR2_DATAINV | \ - USART_CR2_MSBFIRST | USART_CR2_ABREN | USART_CR2_ABRMOD_MASK | \ - USART_CR2_RTOEN | USART_CR2_ADD8_MASK) - -# define USART_CR2_SETBITS USART_CR2_STOP2_VALUE - - /* CR3 settings */ - -# define USART_CR3_CLRBITS \ - (USART_CR3_EIE | USART_CR3_IREN | USART_CR3_IRLP | USART_CR3_HDSEL | \ - USART_CR3_NACK | USART_CR3_SCEN | USART_CR3_DMAR | USART_CR3_DMAT | \ - USART_CR3_RTSE | USART_CR3_CTSE | USART_CR3_CTSIE | USART_CR3_ONEBIT | \ - USART_CR3_OVRDIS | USART_CR3_DDRE | USART_CR3_DEM | USART_CR3_DEP | \ - USART_CR3_SCARCNT_MASK) - -# define USART_CR3_SETBITS 0 - - /* Only the STM32 F3 supports oversampling by 8 */ - -# undef USE_OVER8 - -/* Calculate USART BAUD rate divider */ - -/* Baud rate for standard USART (SPI mode included): - * - * In case of oversampling by 16, the equation is: - * baud = fCK / UARTDIV - * UARTDIV = fCK / baud - * - * In case of oversampling by 8, the equation is: - * - * baud = 2 * fCK / UARTDIV - * UARTDIV = 2 * fCK / baud - */ - -# define STM32_USARTDIV8 \ - (((STM32_APBCLOCK << 1) + (STM32_CONSOLE_BAUD >> 1)) / STM32_CONSOLE_BAUD) -# define STM32_USARTDIV16 \ - ((STM32_APBCLOCK + (STM32_CONSOLE_BAUD >> 1)) / STM32_CONSOLE_BAUD) - -/* Use oversampling by 8 only if the divisor is small. But what is small? */ - -# if STM32_USARTDIV8 > 100 -# define STM32_BRR_VALUE STM32_USARTDIV16 -# else -# define USE_OVER8 1 -# define STM32_BRR_VALUE \ - ((STM32_USARTDIV8 & 0xfff0) | ((STM32_USARTDIV8 & 0x000f) >> 1)) -# endif -#endif /* HAVE_CONSOLE */ - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: arm_lowputc - * - * Description: - * Output one byte on the serial console - * - ****************************************************************************/ - -void arm_lowputc(char ch) -{ -#ifdef HAVE_CONSOLE - /* Wait until the TX data register is empty */ - - while ((getreg32(STM32_CONSOLE_BASE + STM32_USART_ISR_OFFSET) & - USART_ISR_TXE) == 0); -#ifdef STM32_CONSOLE_RS485_DIR - stm32_gpiowrite(STM32_CONSOLE_RS485_DIR, STM32_CONSOLE_RS485_DIR_POLARITY); -#endif - - /* Then send the character */ - - putreg32((uint32_t)ch, STM32_CONSOLE_BASE + STM32_USART_TDR_OFFSET); - -#ifdef STM32_CONSOLE_RS485_DIR - while ((getreg32(STM32_CONSOLE_BASE + STM32_USART_ISR_OFFSET) & - USART_ISR_TC) == 0); - stm32_gpiowrite(STM32_CONSOLE_RS485_DIR, - !STM32_CONSOLE_RS485_DIR_POLARITY); -#endif - -#endif /* HAVE_CONSOLE */ -} - -/**************************************************************************** - * Name: stm32_lowsetup - * - * Description: - * This performs basic initialization of the USART used for the serial - * console. Its purpose is to get the console output available as soon - * as possible. - * - ****************************************************************************/ - -void stm32_lowsetup(void) -{ -#if defined(HAVE_USART) -#if defined(HAVE_CONSOLE) && !defined(CONFIG_SUPPRESS_UART_CONFIG) - uint32_t cr; -#endif - -#if defined(HAVE_CONSOLE) - /* Enable USART APB1/2 clock */ - - modifyreg32(STM32_CONSOLE_APBREG, 0, STM32_CONSOLE_APBEN); -#endif - - /* Enable the console USART and configure GPIO pins needed for rx/tx. - * - * NOTE: Clocking for selected U[S]ARTs was already provided in stm32_rcc.c - */ - -#ifdef STM32_CONSOLE_TX - stm32_configgpio(STM32_CONSOLE_TX); -#endif -#ifdef STM32_CONSOLE_RX - stm32_configgpio(STM32_CONSOLE_RX); -#endif - -#ifdef STM32_CONSOLE_RS485_DIR - stm32_configgpio(STM32_CONSOLE_RS485_DIR); - stm32_gpiowrite(STM32_CONSOLE_RS485_DIR, - !STM32_CONSOLE_RS485_DIR_POLARITY); -#endif - - /* Enable and configure the selected console device */ - -#if defined(HAVE_CONSOLE) && !defined(CONFIG_SUPPRESS_UART_CONFIG) - /* Configure CR2 */ - - cr = getreg32(STM32_CONSOLE_BASE + STM32_USART_CR2_OFFSET); - cr &= ~USART_CR2_CLRBITS; - cr |= USART_CR2_SETBITS; - putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR2_OFFSET); - - /* Configure CR1 */ - - cr = getreg32(STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET); - cr &= ~USART_CR1_CLRBITS; - cr |= USART_CR1_SETBITS; - putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET); - - /* Configure CR3 */ - - cr = getreg32(STM32_CONSOLE_BASE + STM32_USART_CR3_OFFSET); - cr &= ~USART_CR3_CLRBITS; - cr |= USART_CR3_SETBITS; - putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR3_OFFSET); - - /* Configure the USART Baud Rate */ - - putreg32(STM32_BRR_VALUE, STM32_CONSOLE_BASE + STM32_USART_BRR_OFFSET); - - /* Select oversampling by 8 */ - - cr = getreg32(STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET); -#ifdef USE_OVER8 - cr |= USART_CR1_OVER8; - putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET); -#endif - - /* Enable Rx, Tx and the USART */ - - cr |= (USART_CR1_UE | USART_CR1_TE | USART_CR1_RE); - putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET); - -#endif /* HAVE_CONSOLE && !CONFIG_SUPPRESS_UART_CONFIG */ -#endif /* HAVE_USART */ -} diff --git a/arch/arm/src/stm32f0l0g0/stm32_lse.c b/arch/arm/src/stm32f0l0g0/stm32_lse.c deleted file mode 100644 index 9fb81ae318eb0..0000000000000 --- a/arch/arm/src/stm32f0l0g0/stm32_lse.c +++ /dev/null @@ -1,104 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_lse.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "arm_internal.h" -#include "stm32_pwr.h" -#include "stm32_rcc.h" - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_rcc_enablelse - * - * Description: - * Enable the External Low-Speed (LSE) oscillator. - * - * Todo: - * Check for LSE good timeout and return with -1, - * - ****************************************************************************/ - -void stm32_rcc_enablelse(void) -{ -#ifdef HAVE_PWR_DBP - /* The LSE is in the RTC domain and write access is denied to this domain - * after reset, you have to enable write access using DBP bit in the PWR CR - * register before to configuring the LSE. - */ - - stm32_pwr_enablebkp(true); -#endif - -#if defined(CONFIG_ARCH_CHIP_STM32L0) - /* Enable the External Low-Speed (LSE) oscillator by setting the LSEON bit - * the RCC CSR register. - */ - - modifyreg32(STM32_RCC_CSR, 0, RCC_CSR_LSEON); - - /* Wait for the LSE clock to be ready */ - - while ((getreg32(STM32_RCC_CSR) & RCC_CSR_LSERDY) == 0) - { - } - -#elif defined(CONFIG_ARCH_CHIP_STM32F0) - /* Enable the External Low-Speed (LSE) oscillator by setting the LSEON bit - * the RCC BDCR register. - */ - - modifyreg16(STM32_RCC_BDCR, 0, RCC_BDCR_LSEON); - - /* Wait for the LSE clock to be ready */ - - while ((getreg16(STM32_RCC_BDCR) & RCC_BDCR_LSERDY) == 0) - { - } - -#elif defined(CONFIG_ARCH_CHIP_STM32C0) - /* Enable the External Low-Speed (LSE) oscillator by setting the LSEON bit - * the RCC CSR1 register. - */ - - modifyreg32(STM32_RCC_CSR1, 0, RCC_CSR1_LSEON); - - /* Wait for the LSE clock to be ready */ - - while ((getreg32(STM32_RCC_CSR1) & RCC_CSR1_LSERDY) == 0) - { - } -#endif - -#ifdef HAVE_PWR_DBP - /* Disable backup domain access if it was disabled on entry */ - - stm32_pwr_enablebkp(false); -#endif -} diff --git a/arch/arm/src/stm32f0l0g0/stm32_lsi.c b/arch/arm/src/stm32f0l0g0/stm32_lsi.c deleted file mode 100644 index cfcc05e19027c..0000000000000 --- a/arch/arm/src/stm32f0l0g0/stm32_lsi.c +++ /dev/null @@ -1,94 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_lsi.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "arm_internal.h" -#include "stm32_rcc.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* STM32C0 use the second CSR register for LSI */ - -#ifdef CONFIG_ARCH_CHIP_STM32C0 -# define STM32_RCC_CSR STM32_RCC_CSR2 -# define RCC_CSR_LSION RCC_CSR2_LSION -# define RCC_CSR_LSIRDY RCC_CSR2_LSIRDY -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_rcc_enablelsi - * - * Description: - * Enable the Internal Low-Speed (LSI) RC Oscillator. - * - ****************************************************************************/ - -void stm32_rcc_enablelsi(void) -{ - /* Enable the Internal Low-Speed (LSI) RC Oscillator by setting the LSION - * bit in the RCC CSR register. - */ - - modifyreg32(STM32_RCC_CSR, 0, RCC_CSR_LSION); - - /* Wait for the internal RC 40 kHz oscillator to be stable. */ - - while ((getreg32(STM32_RCC_CSR) & RCC_CSR_LSIRDY) == 0); -} - -/**************************************************************************** - * Name: stm32_rcc_disablelsi - * - * Description: - * Disable the Internal Low-Speed (LSI) RC Oscillator. - * - ****************************************************************************/ - -void stm32_rcc_disablelsi(void) -{ - /* Enable the Internal Low-Speed (LSI) RC Oscillator by setting the LSION - * bit in the RCC CSR register. - */ - - modifyreg32(STM32_RCC_CSR, RCC_CSR_LSION, 0); - - /* LSIRDY should go low after 3 LSI clock cycles */ -} diff --git a/arch/arm/src/stm32f0l0g0/stm32_pulsecount.c b/arch/arm/src/stm32f0l0g0/stm32_pulsecount.c deleted file mode 100644 index a60c576c4a59a..0000000000000 --- a/arch/arm/src/stm32f0l0g0/stm32_pulsecount.c +++ /dev/null @@ -1,1277 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_pulsecount.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include - -#include -#include -#include - -#include "arm_internal.h" -#include "chip.h" -#include "stm32_gpio.h" -#include "stm32_pulsecount.h" -#include "stm32_rcc.h" -#include "stm32_tim.h" - -/* This module only supports pulse count on advanced timers. */ - -#ifdef CONFIG_STM32F0L0G0_TIM1_PULSECOUNT - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Pulse count is supported by advanced timers only. */ - -#define TIMTYPE_ADVANCED 4 /* Advanced timers: TIM1 */ -#define TIMTYPE_TIM1 TIMTYPE_ADVANCED - -#define HAVE_IP_TIMERS_V2 1 - -/* CCMR2 */ - -#define HAVE_CCMR2 1 - -#ifdef STM32_APB2_TIM1_CLKIN -# define PULSECOUNT_TIM1_CLKIN STM32_APB2_TIM1_CLKIN -#else -# define PULSECOUNT_TIM1_CLKIN STM32_APB1_TIM1_CLKIN -#endif - -#if CONFIG_STM32F0L0G0_TIM1_PULSECOUNT_CHANNEL == 1 -# define PULSECOUNT_TIM1_CHCFG GPIO_TIM1_CH1OUT -#elif CONFIG_STM32F0L0G0_TIM1_PULSECOUNT_CHANNEL == 2 -# define PULSECOUNT_TIM1_CHCFG GPIO_TIM1_CH2OUT -#elif CONFIG_STM32F0L0G0_TIM1_PULSECOUNT_CHANNEL == 3 -# define PULSECOUNT_TIM1_CHCFG GPIO_TIM1_CH3OUT -#elif CONFIG_STM32F0L0G0_TIM1_PULSECOUNT_CHANNEL == 4 -# define PULSECOUNT_TIM1_CHCFG GPIO_TIM1_CH4OUT -#else -# error Unsupported TIM1 pulse count channel -#endif - -/* Debug ********************************************************************/ - -#ifdef CONFIG_DEBUG_TIMER_INFO -# define pulsecount_dumpgpio(p,m) -# warning "pulsecount_dumpgpio not implemented" -#else -# define pulsecount_dumpgpio(p,m) -#endif - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -struct stm32_pulsecountchan_s -{ - uint8_t channel; - uint32_t pincfg; -}; - -/* This structure represents the state of one pulsecount timer */ - -struct stm32_pulsecounttimer_s -{ - const struct pulsecount_ops_s *ops; - struct stm32_pulsecountchan_s channel; - uint8_t timid; - uint8_t timtype; - uint8_t irq; - uint32_t prev; - uint32_t curr; - uint32_t count; - uint32_t base; - uint32_t pclk; - void *handle; -}; - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -/* Register access */ - -static uint32_t stm32pulsecount_getreg(struct stm32_pulsecounttimer_s *priv, - int offset); -static void stm32pulsecount_putreg(struct stm32_pulsecounttimer_s *priv, - int offset, uint32_t value); -static void stm32pulsecount_modifyreg(struct stm32_pulsecounttimer_s *priv, - uint32_t offset, uint32_t clearbits, - uint32_t setbits); - -#ifdef CONFIG_DEBUG_TIMER_INFO -static void stm32pulsecount_dumpregs(struct stm32_pulsecounttimer_s *priv, - const char *msg); -#else -# define stm32pulsecount_dumpregs(priv,msg) -#endif - -/* Timer management */ - -static int -stm32pulsecount_output_configure(struct stm32_pulsecounttimer_s *priv, - uint8_t channel); -static int stm32pulsecount_timer(struct stm32_pulsecounttimer_s *priv, - const struct pulsecount_info_s *info); -static void stm32pulsecount_setapbclock( - struct stm32_pulsecounttimer_s *priv, bool on); -static int stm32pulsecount_interrupt(struct stm32_pulsecounttimer_s *priv); -static int stm32pulsecount_tim1interrupt(int irq, void *context, void *arg); -static uint32_t stm32pulsecount_pulsecount(uint32_t count); - -/* Pulsecount driver methods */ - -static int stm32pulsecount_setup(struct pulsecount_lowerhalf_s *dev); -static int stm32pulsecount_shutdown(struct pulsecount_lowerhalf_s *dev); - -static int stm32pulsecount_start(struct pulsecount_lowerhalf_s *dev, - const struct pulsecount_info_s *info, - void *handle); - -static int stm32pulsecount_stop(struct pulsecount_lowerhalf_s *dev); -static int stm32pulsecount_ioctl(struct pulsecount_lowerhalf_s *dev, - int cmd, unsigned long arg); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* This is the list of lower half pulsecount driver methods used by the upper - * half driver. - */ - -static const struct pulsecount_ops_s g_pulsecountops = -{ - .setup = stm32pulsecount_setup, - .shutdown = stm32pulsecount_shutdown, - .start = stm32pulsecount_start, - .stop = stm32pulsecount_stop, - .ioctl = stm32pulsecount_ioctl, -}; - -#ifdef CONFIG_STM32F0L0G0_TIM1_PULSECOUNT -static struct stm32_pulsecounttimer_s g_pulsecount1dev = -{ - .ops = &g_pulsecountops, - .timid = 1, - .channel = - { - .channel = CONFIG_STM32F0L0G0_TIM1_PULSECOUNT_CHANNEL, - .pincfg = PULSECOUNT_TIM1_CHCFG, - }, - .timtype = TIMTYPE_TIM1, - .irq = STM32_IRQ_TIM1_BRK, - .base = STM32_TIM1_BASE, - .pclk = PULSECOUNT_TIM1_CLKIN, -}; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32pulsecount_reg_is_32bit - * - * Description: - * Verify whether the timer register is 32bit or not. - * - * Input Parameters: - * timtype - The type of the timer. See the TIMTYPE_* definitions - * offset - The offset to the register to read - * - * Returned Value: - * Return true for 32 bits register; false otherwise. - * - ****************************************************************************/ - -static bool stm32pulsecount_reg_is_32bit(uint8_t timtype, uint32_t offset) -{ - if (timtype == TIMTYPE_ADVANCED) - { - if (offset == STM32_ATIM_CR2_OFFSET || - offset == STM32_ATIM_CCMR1_OFFSET || - offset == STM32_ATIM_CCMR2_OFFSET || - offset == STM32_ATIM_CCER_OFFSET || - offset == STM32_ATIM_BDTR_OFFSET || - offset == STM32_ATIM_DMAR_OFFSET || - offset == STM32_ATIM_AF1_OFFSET || - offset == STM32_ATIM_TISEL_OFFSET) - { - return true; - } - } - - return false; -} - -/**************************************************************************** - * Name: stm32pulsecount_getreg - * - * Description: - * Read the value of an pulsecount timer register - * - * Input Parameters: - * priv - A reference to the pulsecount timer status - * offset - The offset to the register to read - * - * Returned Value: - * The current contents of the specified register - * - ****************************************************************************/ - -static uint32_t stm32pulsecount_getreg( - struct stm32_pulsecounttimer_s *priv, int offset) -{ - uint32_t retval; - - if (stm32pulsecount_reg_is_32bit(priv->timtype, offset) == true) - { - /* 32-bit register */ - - retval = getreg32(priv->base + offset); - } - else - { - /* 16-bit register */ - - retval = getreg16(priv->base + offset); - } - - /* Return 32-bit value */ - - return retval; -} - -/**************************************************************************** - * Name: stm32pulsecount_putreg - * - * Description: - * Read the value of an pulsecount timer register - * - * Input Parameters: - * priv - A reference to the pulsecount timer status - * offset - The offset to the register to read - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void stm32pulsecount_putreg(struct stm32_pulsecounttimer_s *priv, - int offset, uint32_t value) -{ - if (stm32pulsecount_reg_is_32bit(priv->timtype, offset) == true) - { - /* 32-bit register */ - - putreg32(value, priv->base + offset); - } - else - { - /* 16-bit register */ - - putreg16((uint16_t)value, priv->base + offset); - } -} - -/**************************************************************************** - * Name: stm32pulsecount_modifyreg - * - * Description: - * Modify timer register (32-bit or 16-bit) - * - * Input Parameters: - * priv - A reference to the pulsecount timer status - * offset - The offset to the register to read - * clrbits - The bits to clear - * setbits - The bits to set - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void stm32pulsecount_modifyreg(struct stm32_pulsecounttimer_s *priv, - uint32_t offset, uint32_t clearbits, - uint32_t setbits) -{ - if (stm32pulsecount_reg_is_32bit(priv->timtype, offset) == true) - { - /* 32-bit register */ - - modifyreg32(priv->base + offset, clearbits, setbits); - } - else - { - /* 16-bit register */ - - modifyreg16(priv->base + offset, clearbits, setbits); - } -} - -/**************************************************************************** - * Name: stm32pulsecount_dumpregs - * - * Description: - * Dump all timer registers. - * - * Input Parameters: - * priv - A reference to the pulsecount timer status - * msg - A message to be printed on the screen - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef CONFIG_DEBUG_TIMER_INFO -static void stm32pulsecount_dumpregs(struct stm32_pulsecounttimer_s *priv, - const char *msg) -{ - _info("%s:\n", msg); - _info(" CR1: %04x CR2: %04x SMCR: %04x DIER: %04x\n", - stm32pulsecount_getreg(priv, STM32_GTIM_CR1_OFFSET), - stm32pulsecount_getreg(priv, STM32_GTIM_CR2_OFFSET), - stm32pulsecount_getreg(priv, STM32_GTIM_SMCR_OFFSET), - stm32pulsecount_getreg(priv, STM32_GTIM_DIER_OFFSET)); - _info(" SR: %04x EGR: %04x CCMR1: %04x CCMR2: %04x\n", - stm32pulsecount_getreg(priv, STM32_GTIM_SR_OFFSET), - stm32pulsecount_getreg(priv, STM32_GTIM_EGR_OFFSET), - stm32pulsecount_getreg(priv, STM32_GTIM_CCMR1_OFFSET), - stm32pulsecount_getreg(priv, STM32_GTIM_CCMR2_OFFSET)); - _info(" CCER: %04x CNT: %04x PSC: %04x ARR: %04x\n", - stm32pulsecount_getreg(priv, STM32_GTIM_CCER_OFFSET), - stm32pulsecount_getreg(priv, STM32_GTIM_CNT_OFFSET), - stm32pulsecount_getreg(priv, STM32_GTIM_PSC_OFFSET), - stm32pulsecount_getreg(priv, STM32_GTIM_ARR_OFFSET)); - _info(" CCR1: %04x CCR2: %04x CCR3: %04x CCR4: %04x\n", - stm32pulsecount_getreg(priv, STM32_GTIM_CCR1_OFFSET), - stm32pulsecount_getreg(priv, STM32_GTIM_CCR2_OFFSET), - stm32pulsecount_getreg(priv, STM32_GTIM_CCR3_OFFSET), - stm32pulsecount_getreg(priv, STM32_GTIM_CCR4_OFFSET)); - if (priv->timtype == TIMTYPE_ADVANCED) - { - _info(" RCR: %04x BDTR: %04x DCR: %04x DMAR: %04x\n", - stm32pulsecount_getreg(priv, STM32_ATIM_RCR_OFFSET), - stm32pulsecount_getreg(priv, STM32_ATIM_BDTR_OFFSET), - stm32pulsecount_getreg(priv, STM32_ATIM_DCR_OFFSET), - stm32pulsecount_getreg(priv, STM32_ATIM_DMAR_OFFSET)); - - _info(" AF1: %04x TISEL: %04x\n", - stm32pulsecount_getreg(priv, STM32_ATIM_AF1_OFFSET), - stm32pulsecount_getreg(priv, STM32_ATIM_TISEL_OFFSET)); - } -} -#endif - -/**************************************************************************** - * Name: stm32pulsecount_output_configure - * - * Description: - * Configure pulsecount output for given channel - * - * Input Parameters: - * priv - A reference to the pulsecount timer status - * channel - Timer output channel - * - * Returned Value: - * Zero on success; - ****************************************************************************/ - -static int -stm32pulsecount_output_configure(struct stm32_pulsecounttimer_s *priv, - uint8_t channel) -{ - uint32_t cr2; - uint32_t ccer; - - /* Get current registers state */ - - cr2 = stm32pulsecount_getreg(priv, STM32_GTIM_CR2_OFFSET); - ccer = stm32pulsecount_getreg(priv, STM32_GTIM_CCER_OFFSET); - - /* Reset the output polarity level of all channels (selects high - * polarity) - */ - - ccer &= ~(GTIM_CCER_CC1P << ((channel - 1) * 4)); - - /* Enable the output state of the selected channels */ - - ccer |= (GTIM_CCER_CC1E << ((channel - 1) * 4)); - - if (priv->timtype == TIMTYPE_ADVANCED) - { - cr2 &= ~(ATIM_CR2_OIS1 << ((channel - 1) * 2)); - } - - stm32pulsecount_modifyreg(priv, STM32_GTIM_CR2_OFFSET, 0, cr2); - stm32pulsecount_modifyreg(priv, STM32_GTIM_CCER_OFFSET, 0, ccer); - - return OK; -} - -/**************************************************************************** - * Name: stm32pulsecount_timer - * - * Description: - * (Re-)initialize the timer resources and start the pulsed output - * - * Input Parameters: - * priv - A reference to the lower half pulsecount driver state structure - * info - A reference to the characteristics of the pulsed output - * - * Returned Value: - * Zero on success; a negated errno value on failure - * - ****************************************************************************/ - -static int stm32pulsecount_timer(struct stm32_pulsecounttimer_s *priv, - const struct pulsecount_info_s *info) -{ - /* Calculated values */ - - uint32_t prescaler; - uint32_t timclk; - uint32_t reload; - uint32_t ccr; - ub16_t duty; - uint32_t chanmode = GTIM_CCMR_MODE_PWM1; - uint8_t channel; - - /* Register contents */ - - uint32_t cr1; - uint32_t ccmr1; -#if defined(HAVE_CCMR2) - uint32_t ccmr2; - uint32_t ocmode2; -#endif - - /* New timer register bit settings */ - - uint32_t ocmode1; - - DEBUGASSERT(priv != NULL && info != NULL); - - ccmr1 = stm32pulsecount_getreg(priv, STM32_GTIM_CCMR1_OFFSET); - -#if defined(HAVE_CCMR2) - ccmr2 = stm32pulsecount_getreg(priv, STM32_GTIM_CCMR2_OFFSET); -#endif - - _info("TIM%u channel: %u high: %" PRIu32 " ns low: %" PRIu32 - " ns count: %" PRIu32 "\n", - priv->timid, priv->channel.channel, info->high_ns, - info->low_ns, info->count); - - DEBUGASSERT(pulsecount_frequency(info) > 0); - - /* Disable all interrupts and DMA requests, clear all pending status */ - - stm32pulsecount_putreg(priv, STM32_GTIM_DIER_OFFSET, 0); - stm32pulsecount_putreg(priv, STM32_GTIM_SR_OFFSET, 0); - - /* Calculate optimal values for the timer prescaler and for the timer - * reload register. If 'frequency' is the desired frequency, then - * - * reload = timclk / frequency - * timclk = pclk / presc - * - * Or, - * - * reload = pclk / presc / frequency - * - * There are many solutions to this, but the best solution will be the - * one that has the largest reload value and the smallest prescaler value. - * That is the solution that should give us the most accuracy in the timer - * control. Subject to: - * - * 0 <= presc <= 65536 - * 1 <= reload <= 65535 - * - * So presc = pclk / 65535 / frequency would be optimal. - * - * Example: - * - * pclk = 42 MHz - * frequency = 100 Hz - * - * prescaler = 42,000,000 / 65,535 / 100 - * = 6.4 (or 7 -- taking the ceiling always) - * timclk = 42,000,000 / 7 - * = 6,000,000 - * reload = 6,000,000 / 100 - * = 60,000 - */ - - prescaler = (priv->pclk / pulsecount_frequency(info) + 65534) / 65535; - if (prescaler < 1) - { - prescaler = 1; - } - else if (prescaler > 65536) - { - prescaler = 65536; - } - - timclk = priv->pclk / prescaler; - - reload = timclk / pulsecount_frequency(info); - - if (reload < 2) - { - reload = 1; - } - else if (reload > 65535) - { - reload = 65535; - } - else - { - reload--; - } - - _info("TIM%u PCLK: %" PRIu32 " frequency: %" PRIu32 " " - "TIMCLK: %" PRIu32 " prescaler: %" PRIu32 - " reload: %" PRIu32 "\n", - priv->timid, priv->pclk, pulsecount_frequency(info), timclk, - prescaler, reload); - - /* Set up the timer CR1 register: - * - * 1,8 CKD[1:0] ARPE CMS[1:0] DIR OPM URS UDIS CEN - * 2-5 CKD[1:0] ARPE CMS DIR OPM URS UDIS CEN - * 6-7 ARPE OPM URS UDIS CEN - * 9-14 CKD[1:0] ARPE URS UDIS CEN - * 15-17 CKD[1:0] ARPE OPM URS UDIS CEN - */ - - cr1 = stm32pulsecount_getreg(priv, STM32_GTIM_CR1_OFFSET); - - /* Disable the timer until we get it configured */ - - cr1 &= ~GTIM_CR1_CEN; - - cr1 &= ~(GTIM_CR1_DIR | GTIM_CR1_CMS_MASK); - - cr1 |= GTIM_CR1_EDGE; - - /* Set the clock division to zero for all (but the basic timers, but there - * should be no basic timers in this context - */ - - cr1 &= ~GTIM_CR1_CKD_MASK; - stm32pulsecount_putreg(priv, STM32_GTIM_CR1_OFFSET, cr1); - - /* Set the reload and prescaler values */ - - stm32pulsecount_putreg(priv, STM32_GTIM_ARR_OFFSET, reload); - stm32pulsecount_putreg(priv, STM32_GTIM_PSC_OFFSET, (prescaler - 1)); - - /* Set the advanced timer's repetition counter */ - - if (priv->timtype == TIMTYPE_ADVANCED) - { - /* If a non-zero repetition count has been selected, then set the - * repetition counter to the count-1. stm32pulsecount_start() has - * already assured us that the count value is within range. - */ - - if (info->count > 0) - { - /* Save the remaining count and the number of counts that will have - * elapsed on the first interrupt. - */ - - /* If the first interrupt occurs at the end end of the first - * repetition count, then the count will be the same as the RCR - * value. - */ - - priv->prev = stm32pulsecount_pulsecount(info->count); - stm32pulsecount_putreg(priv, STM32_ATIM_RCR_OFFSET, - priv->prev - 1); - - /* Generate an update event to reload the prescaler. This should - * preload the RCR into active repetition counter. - */ - - stm32pulsecount_putreg(priv, STM32_ATIM_EGR_OFFSET, ATIM_EGR_UG); - - /* Now set the value of the RCR that will be loaded on the next - * update event. - */ - - priv->count = info->count; - priv->curr = stm32pulsecount_pulsecount(info->count - - priv->prev); - stm32pulsecount_putreg(priv, STM32_ATIM_RCR_OFFSET, - priv->curr - 1); - } - - /* Otherwise, just clear the repetition counter */ - - else - { - /* Set the repetition counter to zero */ - - stm32pulsecount_putreg(priv, STM32_ATIM_RCR_OFFSET, 0); - - /* Generate an update event to reload the prescaler */ - - stm32pulsecount_putreg(priv, STM32_ATIM_EGR_OFFSET, ATIM_EGR_UG); - } - } - - /* Handle channel specific setup */ - - ocmode1 = 0; -#if defined(HAVE_CCMR2) - ocmode2 = 0; -#endif - - duty = pulsecount_duty(info); - channel = priv->channel.channel; - - /* Duty cycle: - * - * duty cycle = ccr / reload (fractional value) - */ - - ccr = b16toi(duty * reload + b16HALF); - - _info("ccr: %" PRIu32 "\n", ccr); - - switch (channel) - { - case 1: - ocmode1 |= (GTIM_CCMR_CCS_CCOUT << GTIM_CCMR1_CC1S_SHIFT) | - (chanmode << GTIM_CCMR1_OC1M_SHIFT) | - GTIM_CCMR1_OC1PE; - stm32pulsecount_putreg(priv, STM32_GTIM_CCR1_OFFSET, ccr); - ccmr1 &= ~(GTIM_CCMR1_CC1S_MASK | GTIM_CCMR1_OC1M_MASK | - GTIM_CCMR1_OC1PE | GTIM_CCMR1_OC1M); - break; - - case 2: - ocmode1 |= (GTIM_CCMR_CCS_CCOUT << GTIM_CCMR1_CC2S_SHIFT) | - (chanmode << GTIM_CCMR1_OC2M_SHIFT) | - GTIM_CCMR1_OC2PE; - stm32pulsecount_putreg(priv, STM32_GTIM_CCR2_OFFSET, ccr); - ccmr1 &= ~(GTIM_CCMR1_CC2S_MASK | GTIM_CCMR1_OC2M_MASK | - GTIM_CCMR1_OC2PE | GTIM_CCMR1_OC2M); - break; - - case 3: - ocmode2 |= (ATIM_CCMR_CCS_CCOUT << ATIM_CCMR2_CC3S_SHIFT) | - (chanmode << ATIM_CCMR2_OC3M_SHIFT) | - ATIM_CCMR2_OC3PE; - stm32pulsecount_putreg(priv, STM32_ATIM_CCR3_OFFSET, ccr); - ccmr2 &= ~(ATIM_CCMR2_CC3S_MASK | ATIM_CCMR2_OC3M_MASK | - ATIM_CCMR2_OC3PE | ATIM_CCMR2_OC3M); - break; - - case 4: - ocmode2 |= (ATIM_CCMR_CCS_CCOUT << ATIM_CCMR2_CC4S_SHIFT) | - (chanmode << ATIM_CCMR2_OC4M_SHIFT) | - ATIM_CCMR2_OC4PE; - stm32pulsecount_putreg(priv, STM32_ATIM_CCR4_OFFSET, ccr); - ccmr2 &= ~(ATIM_CCMR2_CC4S_MASK | ATIM_CCMR2_OC4M_MASK | - ATIM_CCMR2_OC4PE | ATIM_CCMR2_OC4M); - break; - - default: - _err("ERROR: No such channel: %u\n", channel); - return -EINVAL; - } - - stm32pulsecount_output_configure(priv, channel); - - ccmr1 |= ocmode1; -#if defined(HAVE_CCMR2) - ccmr2 |= ocmode2; -#endif - - if (priv->timtype == TIMTYPE_ADVANCED) - { - uint32_t bdtr; - - /* Get current register state */ - - bdtr = stm32pulsecount_getreg(priv, STM32_ATIM_BDTR_OFFSET); - - bdtr &= ~(ATIM_BDTR_OSSI | ATIM_BDTR_OSSR); - bdtr |= ATIM_BDTR_MOE; - - stm32pulsecount_putreg(priv, STM32_ATIM_BDTR_OFFSET, bdtr); - } - - /* Save the modified register values */ - - putreg32(ccmr1, priv->base + STM32_GTIM_CCMR1_OFFSET); -#if defined(HAVE_CCMR2) - putreg32(ccmr2, priv->base + STM32_ATIM_CCMR2_OFFSET); -#endif - - /* Set the ARR Preload Bit */ - - cr1 = stm32pulsecount_getreg(priv, STM32_GTIM_CR1_OFFSET); - cr1 |= GTIM_CR1_ARPE; - stm32pulsecount_putreg(priv, STM32_GTIM_CR1_OFFSET, cr1); - - /* Setup update interrupt. If info->count is > 0, then we can - * be assured that stm32pulsecount_start() has already verified: (1) that - * this is an advanced timer, and that (2) the repetition count is within - * range. - */ - - if (info->count > 0) - { - /* Clear all pending interrupts and enable the update interrupt. */ - - stm32pulsecount_putreg(priv, STM32_GTIM_SR_OFFSET, 0); - stm32pulsecount_putreg(priv, STM32_GTIM_DIER_OFFSET, GTIM_DIER_UIE); - - /* Enable the timer */ - - cr1 |= GTIM_CR1_CEN; - stm32pulsecount_putreg(priv, STM32_GTIM_CR1_OFFSET, cr1); - - /* And enable timer interrupts at the NVIC */ - - up_enable_irq(priv->irq); - } - else - { - /* Just enable the timer, leaving all interrupts disabled */ - - cr1 |= GTIM_CR1_CEN; - stm32pulsecount_putreg(priv, STM32_GTIM_CR1_OFFSET, cr1); - } - - stm32pulsecount_dumpregs(priv, "After starting"); - return OK; -} - -/**************************************************************************** - * Name: stm32pulsecount_interrupt - * - * Description: - * Handle timer interrupts. - * - * Input Parameters: - * priv - A reference to the lower half pulsecount driver state structure - * - * Returned Value: - * Zero on success; a negated errno value on failure - ****************************************************************************/ - -static int stm32pulsecount_interrupt(struct stm32_pulsecounttimer_s *priv) -{ - uint16_t regval; - - /* Verify that this is an update interrupt. Nothing else is expected. */ - - regval = stm32pulsecount_getreg(priv, STM32_ATIM_SR_OFFSET); - DEBUGASSERT((regval & ATIM_SR_UIF) != 0); - - /* Clear the UIF interrupt bit */ - - stm32pulsecount_putreg(priv, STM32_ATIM_SR_OFFSET, regval & ~ATIM_SR_UIF); - - /* Calculate the new count by subtracting the number of pulses - * since the last interrupt. - */ - - if (priv->count <= priv->prev) - { - /* We are finished. Turn off the mast output to stop the output as - * quickly as possible. - */ - - regval = stm32pulsecount_getreg(priv, STM32_ATIM_BDTR_OFFSET); - regval &= ~ATIM_BDTR_MOE; - stm32pulsecount_putreg(priv, STM32_ATIM_BDTR_OFFSET, regval); - - /* Disable first interrupts, stop and reset the timer */ - - stm32pulsecount_stop((struct pulsecount_lowerhalf_s *)priv); - - /* Then perform the callback into the upper half driver */ - - pulsecount_expired(priv->handle); - - priv->handle = NULL; - priv->count = 0; - priv->prev = 0; - priv->curr = 0; - } - else - { - /* Decrement the count of pulses remaining using the number of - * pulses generated since the last interrupt. - */ - - priv->count -= priv->prev; - - /* Set up the next RCR. Set 'prev' to the value of the RCR that - * was loaded when the update occurred (just before this interrupt) - * and set 'curr' to the current value of the RCR register (which - * will bet loaded on the next update event). - */ - - priv->prev = priv->curr; - priv->curr = stm32pulsecount_pulsecount(priv->count - priv->prev); - stm32pulsecount_putreg(priv, STM32_ATIM_RCR_OFFSET, priv->curr - 1); - } - - /* Now all of the time critical stuff is done so we can do some debug - * output - */ - - _info("Update interrupt SR: %04x prev: %" PRIu32 " curr: %" PRIu32 - " count: %" PRIu32 "\n", - regval, priv->prev, priv->curr, priv->count); - - return OK; -} - -/**************************************************************************** - * Name: stm32pulsecount_tim1interrupt - * - * Description: - * Handle timer 1 interrupts. - * - * Input Parameters: - * Standard NuttX interrupt inputs - * - * Returned Value: - * Zero on success; a negated errno value on failure - * - ****************************************************************************/ - -static int stm32pulsecount_tim1interrupt(int irq, void *context, void *arg) -{ - return stm32pulsecount_interrupt(&g_pulsecount1dev); -} - -/**************************************************************************** - * Name: stm32pulsecount_pulsecount - * - * Description: - * Pick an optimal pulse count to program the RCR. - * - * Input Parameters: - * count - The total count remaining - * - * Returned Value: - * The recommended pulse count - * - ****************************************************************************/ - -static uint32_t stm32pulsecount_pulsecount(uint32_t count) -{ - /* The the remaining pulse count is less than or equal to the maximum, the - * just return the count. - */ - - if (count <= ATIM_RCR_REP_MAX) - { - return count; - } - - /* Otherwise, we have to be careful. We do not want a small number of - * counts at the end because we might have trouble responding fast enough. - * If the remaining count is less than 150% of the maximum, then return - * half of the maximum. In this case the final sequence will be between 64 - * and 128. - */ - - else if (count < (3 * ATIM_RCR_REP_MAX / 2)) - { - return (ATIM_RCR_REP_MAX + 1) >> 1; - } - - /* Otherwise, return the maximum. The final count will be 64 or more */ - - else - { - return ATIM_RCR_REP_MAX; - } -} - -/**************************************************************************** - * Name: stm32pulsecount_setapbclock - * - * Description: - * Enable or disable APB clock for the timer peripheral - * - * Input Parameters: - * dev - A reference to the lower half pulsecount driver state structure - * on - Enable clock if 'on' is 'true' and disable if 'false' - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void stm32pulsecount_setapbclock( - struct stm32_pulsecounttimer_s *priv, bool on) -{ - uint32_t en_bit; - uint32_t regaddr; - - /* Determine which timer to configure */ - - switch (priv->timid) - { -#ifdef CONFIG_STM32F0L0G0_TIM1_PULSECOUNT - case 1: - regaddr = STM32_RCC_APB2ENR; - en_bit = RCC_APB2ENR_TIM1EN; - break; -#endif - default: - return; - } - - /* Enable/disable APB 1/2 clock for timer */ - - if (on) - { - modifyreg32(regaddr, 0, en_bit); - } - else - { - modifyreg32(regaddr, en_bit, 0); - } -} - -/**************************************************************************** - * Name: stm32pulsecount_setup - * - * Description: - * This method is called when the driver is opened. The lower half driver - * should configure and initialize the device so that it is ready for use. - * It should not, however, output pulses until the start method is called. - * - * Input Parameters: - * dev - A reference to the lower half pulsecount driver state structure - * - * Returned Value: - * Zero on success; a negated errno value on failure - * - * Assumptions: - * APB1 or 2 clocking for the GPIOs has already been configured by the RCC - * logic at power up. - * - ****************************************************************************/ - -static int stm32pulsecount_setup(struct pulsecount_lowerhalf_s *dev) -{ - struct stm32_pulsecounttimer_s *priv = - (struct stm32_pulsecounttimer_s *)dev; - uint32_t pincfg; - - _info("TIM%u\n", priv->timid); - stm32pulsecount_dumpregs(priv, "Initially"); - - /* Enable APB1/2 clocking for timer. */ - - stm32pulsecount_setapbclock(priv, true); - - /* Configure the pulsecount output pins, but do not start the timer yet */ - - pincfg = priv->channel.pincfg; - if (pincfg != 0) - { - _info("pincfg: %08" PRIx32 "\n", pincfg); - - stm32_configgpio(pincfg); - } - - pulsecount_dumpgpio(pincfg, "pulsecount setup"); - - return OK; -} - -/**************************************************************************** - * Name: stm32pulsecount_shutdown - * - * Description: - * This method is called when the driver is closed. The lower half driver - * stop pulsed output, free any resources, disable the timer hardware, and - * put the system into the lowest possible power usage state - * - * Input Parameters: - * dev - A reference to the lower half pulsecount driver state structure - * - * Returned Value: - * Zero on success; a negated errno value on failure - * - ****************************************************************************/ - -static int stm32pulsecount_shutdown(struct pulsecount_lowerhalf_s *dev) -{ - struct stm32_pulsecounttimer_s *priv = - (struct stm32_pulsecounttimer_s *)dev; - uint32_t pincfg; - - _info("TIM%u\n", priv->timid); - - /* Make sure that the output has been stopped */ - - stm32pulsecount_stop(dev); - - /* Disable APB1/2 clocking for timer. */ - - stm32pulsecount_setapbclock(priv, false); - - /* Then put the GPIO pins back to the default state */ - - pincfg = priv->channel.pincfg; - if (pincfg != 0) - { - _info("pincfg: %08" PRIx32 "\n", pincfg); - - pincfg &= (GPIO_PORT_MASK | GPIO_PIN_MASK); - pincfg |= GPIO_INPUT | GPIO_FLOAT; - - stm32_configgpio(pincfg); - } - - return OK; -} - -/**************************************************************************** - * Name: stm32pulsecount_start - * - * Description: - * (Re-)initialize the timer resources and start the pulsed output - * - * Input Parameters: - * dev - A reference to the lower half pulsecount driver state structure - * info - A reference to the characteristics of the pulsed output - * - * Returned Value: - * Zero on success; a negated errno value on failure - * - ****************************************************************************/ - -static int stm32pulsecount_start(struct pulsecount_lowerhalf_s *dev, - const struct pulsecount_info_s *info, - void *handle) -{ - struct stm32_pulsecounttimer_s *priv = - (struct stm32_pulsecounttimer_s *)dev; - - /* Check if a pulsecount has been selected */ - - if (info->count > 0) - { - /* Only the advanced timers (TIM1,8 can support the pulse counting) */ - - if (priv->timtype != TIMTYPE_ADVANCED) - { - _err("ERROR: TIM%u cannot support pulse count: %" PRIu32 "\n", - priv->timid, info->count); - return -EPERM; - } - } - - /* Save the handle */ - - priv->handle = handle; - - /* Start the time */ - - return stm32pulsecount_timer(priv, info); -} - -/**************************************************************************** - * Name: stm32pulsecount_stop - * - * Description: - * Stop the pulsed output and reset the timer resources - * - * Input Parameters: - * dev - A reference to the lower half pulsecount driver state structure - * - * Returned Value: - * Zero on success; a negated errno value on failure - * - * Assumptions: - * This function is called to stop the pulsed output at anytime. This - * method is also called from the timer interrupt handler when a repetition - * count expires... automatically stopping the timer. - * - ****************************************************************************/ - -static int stm32pulsecount_stop(struct pulsecount_lowerhalf_s *dev) -{ - struct stm32_pulsecounttimer_s *priv = - (struct stm32_pulsecounttimer_s *)dev; - uint32_t resetbit; - uint32_t regaddr; - uint32_t regval; - irqstate_t flags; - - _info("TIM%u\n", priv->timid); - - /* Disable interrupts momentary to stop any ongoing timer processing and - * to prevent any concurrent access to the reset register. - */ - - flags = enter_critical_section(); - - /* Disable further interrupts and stop the timer */ - - stm32pulsecount_putreg(priv, STM32_GTIM_DIER_OFFSET, 0); - stm32pulsecount_putreg(priv, STM32_GTIM_SR_OFFSET, 0); - - /* Determine which timer to reset */ - - switch (priv->timid) - { -#ifdef CONFIG_STM32F0L0G0_TIM1_PULSECOUNT - case 1: - regaddr = STM32_RCC_APB2RSTR; - resetbit = RCC_APB2RSTR_TIM1RST; - break; -#endif - - default: - leave_critical_section(flags); - return -EINVAL; - } - - /* Reset the timer - stopping the output and putting the timer back - * into a state where stm32pulsecount_start() can be called. - */ - - regval = getreg32(regaddr); - regval |= resetbit; - putreg32(regval, regaddr); - - regval &= ~resetbit; - putreg32(regval, regaddr); - leave_critical_section(flags); - - _info("regaddr: %08" PRIx32 " resetbit: %08" PRIx32 "\n", - regaddr, resetbit); - stm32pulsecount_dumpregs(priv, "After stop"); - return OK; -} - -/**************************************************************************** - * Name: stm32pulsecount_ioctl - * - * Description: - * Lower-half logic may support platform-specific ioctl commands - * - * Input Parameters: - * dev - A reference to the lower half pulsecount driver state structure - * cmd - The ioctl command - * arg - The argument accompanying the ioctl command - * - * Returned Value: - * Zero on success; a negated errno value on failure - * - ****************************************************************************/ - -static int stm32pulsecount_ioctl(struct pulsecount_lowerhalf_s *dev, int cmd, - unsigned long arg) -{ -#ifdef CONFIG_DEBUG_TIMER_INFO - struct stm32_pulsecounttimer_s *priv = - (struct stm32_pulsecounttimer_s *)dev; - - /* There are no platform-specific ioctl commands */ - - _info("TIM%u\n", priv->timid); -#endif - return -ENOTTY; -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_pulsecountinitialize - * - * Description: - * Initialize one timer for use with the upper-level pulsecount driver. - * - * Input Parameters: - * timer - A number identifying the timer use. The number of valid timer - * IDs varies with the STM32 MCU and MCU family. This pulsecount driver - * supports TIM1 only on STM32F0/L0/G0. - * - * Returned Value: - * On success, a pointer to the STM32 lower half pulsecount driver is - * returned. NULL is returned on any failure. - * - ****************************************************************************/ - -struct pulsecount_lowerhalf_s *stm32_pulsecountinitialize(int timer) -{ - struct stm32_pulsecounttimer_s *lower; - - _info("TIM%u\n", timer); - - switch (timer) - { -#ifdef CONFIG_STM32F0L0G0_TIM1_PULSECOUNT - case 1: - lower = &g_pulsecount1dev; - - /* Attach but disable the TIM1 update interrupt */ - - irq_attach(lower->irq, stm32pulsecount_tim1interrupt, NULL); - up_disable_irq(lower->irq); - break; -#endif - - default: - _err("ERROR: No such timer configured\n"); - return NULL; - } - - return (struct pulsecount_lowerhalf_s *)lower; -} - -#endif /* CONFIG_STM32F0L0G0_TIMx_PULSECOUNT */ diff --git a/arch/arm/src/stm32f0l0g0/stm32_pulsecount.h b/arch/arm/src/stm32f0l0g0/stm32_pulsecount.h deleted file mode 100644 index 8c8aca535f1a7..0000000000000 --- a/arch/arm/src/stm32f0l0g0/stm32_pulsecount.h +++ /dev/null @@ -1,39 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_pulsecount.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_STM32_PULSECOUNT_H -#define __ARCH_ARM_SRC_STM32F0L0G0_STM32_PULSECOUNT_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -struct pulsecount_lowerhalf_s *stm32_pulsecountinitialize(int timer); - -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_STM32_PULSECOUNT_H */ diff --git a/arch/arm/src/stm32f0l0g0/stm32_pwm.c b/arch/arm/src/stm32f0l0g0/stm32_pwm.c deleted file mode 100644 index df066d05163a3..0000000000000 --- a/arch/arm/src/stm32f0l0g0/stm32_pwm.c +++ /dev/null @@ -1,1911 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_pwm.c - * - * SPDX-License-Identifier: BSD-3-Clause - * SPDX-FileCopyrightText: 2019 Fundação CERTI. All rights reserved. - * SPDX-FileContributor: Daniel Pereira Volpato - * SPDX-FileContributor: Guillherme da Silva Amaral - * SPDX-FileContributor: Gregory Nutt - * SPDX-FileContributor: Paul Alexander Patience - * SPDX-FileContributor: Mateusz Szafoni - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include - -#include -#include -#include - -#include "arm_internal.h" -#include "chip.h" -#include "stm32_gpio.h" -#include "stm32_pwm.h" -#include "stm32_rcc.h" - -/* This module then only compiles if there is at least one enabled timer - * intended for use with the PWM upper half driver. - */ - -#if defined(CONFIG_STM32F0L0G0_TIM1_PWM) || defined(CONFIG_STM32F0L0G0_TIM2_PWM) || \ - defined(CONFIG_STM32F0L0G0_TIM3_PWM) || defined(CONFIG_STM32F0L0G0_TIM14_PWM) || \ - defined(CONFIG_STM32F0L0G0_TIM15_PWM) || defined(CONFIG_STM32F0L0G0_TIM16_PWM) || \ - defined(CONFIG_STM32F0L0G0_TIM17_PWM) - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* PWM/Timer Definitions ****************************************************/ - -/* The following definitions are used to identify the various time types */ - -#define TIMTYPE_BASIC 0 /* Basic timers: TIM6,7 */ -#define TIMTYPE_GENERAL16 1 /* General 16-bit timers: TIM3 */ -#define TIMTYPE_COUNTUP16 2 /* General 16-bit count-up timers: TIM14 */ -#define TIMTYPE_GENERAL32 3 /* General 32-bit timers: TIM2 */ -#define TIMTYPE_ADVANCED 4 /* Advanced timers: TIM1 */ -#define TIMTYPE_COUNTUP16_N 5 /* General 16-bit count-up timers with - * one complementary output: TIM15-17 - */ - -#define TIMTYPE_TIM1 TIMTYPE_ADVANCED -#define TIMTYPE_TIM2 TIMTYPE_GENERAL32 -#define TIMTYPE_TIM3 TIMTYPE_GENERAL16 -#define TIMTYPE_TIM6 TIMTYPE_BASIC -#define TIMTYPE_TIM7 TIMTYPE_BASIC -#define TIMTYPE_TIM14 TIMTYPE_COUNTUP16 -#define TIMTYPE_TIM15 TIMTYPE_COUNTUP16_N /* Treated as ADVTIM */ -#define TIMTYPE_TIM16 TIMTYPE_COUNTUP16_N /* Treated as ADVTIM */ -#define TIMTYPE_TIM17 TIMTYPE_COUNTUP16_N /* Treated as ADVTIM */ - -/* Advanced timer */ - -#if defined (CONFIG_STM32F0L0G0_TIM1_PWM) -# define HAVE_IP_TIMERS_V2 1 -#endif - -#if defined(CONFIG_STM32F0L0G0_TIM1_PWM) || \ - defined(CONFIG_STM32F0L0G0_TIM8_PWM) || \ - defined(CONFIG_STM32F0L0G0_TIM15_PWM) || \ - defined(CONFIG_STM32F0L0G0_TIM16_PWM) || \ - defined(CONFIG_STM32F0L0G0_TIM17_PWM) -# define HAVE_ADVTIM -#else -# undef HAVE_ADVTIM -#endif - -/* CCMR2 */ - -#if defined(CONFIG_STM32F0L0G0_TIM1_PWM) || \ - defined(CONFIG_STM32F0L0G0_TIM3_PWM) -# define HAVE_CCMR2 -#else -# undef HAVE_CCMR2 -#endif - -/* Debug ********************************************************************/ - -#ifdef CONFIG_DEBUG_PWM_INFO -# define pwm_dumpgpio(p,m) -# warning "pwm_dumpgpio not implemented" -#else -# define pwm_dumpgpio(p,m) -#endif - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -enum stm32_timmode_e -{ - STM32_TIMMODE_COUNTUP = 0, - STM32_TIMMODE_COUNTDOWN = 1, - STM32_TIMMODE_CENTER1 = 2, - STM32_TIMMODE_CENTER2 = 3, - STM32_TIMMODE_CENTER3 = 4, -}; - -enum stm32_chanmode_e -{ - STM32_CHANMODE_PWM1 = 0, - STM32_CHANMODE_PWM2 = 1, - STM32_CHANMODE_COMBINED1 = 2, - STM32_CHANMODE_COMBINED2 = 3, - STM32_CHANMODE_ASYMMETRIC1 = 4, - STM32_CHANMODE_ASYMMETRIC2 = 5, -}; - -struct stm32_pwmchan_s -{ - uint8_t channel; /* Timer output channel: {1,..4} */ - enum stm32_chanmode_e mode; - uint32_t pincfg; /* Output pin configuration */ - uint32_t npincfg; /* Complementary output pin configuration - * (only TIM1,8 CH1-3 and TIM15,16,17 CH1) - */ -}; - -/* This structure represents the state of one PWM timer */ - -struct stm32_pwmtimer_s -{ - const struct pwm_ops_s *ops; /* PWM operations */ - struct stm32_pwmchan_s channels[PWM_NCHANNELS]; - uint8_t timid; /* Timer ID {1,...,17} */ - uint8_t timtype; /* See the TIMTYPE_* definitions */ - enum stm32_timmode_e mode; - uint32_t frequency; /* Current frequency setting */ - uint32_t base; /* The base address of the timer */ - uint32_t pclk; /* The frequency of the peripheral clock - * that drives the timer module. */ -}; - -/**************************************************************************** - * Static Function Prototypes - ****************************************************************************/ - -/* Register access */ - -static uint32_t stm32pwm_getreg(struct stm32_pwmtimer_s *priv, int offset); -static void stm32pwm_putreg(struct stm32_pwmtimer_s *priv, int offset, - uint32_t value); -static void stm32pwm_modifyreg(struct stm32_pwmtimer_s *priv, - uint32_t offset, uint32_t clearbits, - uint32_t setbits); - -#ifdef CONFIG_DEBUG_PWM_INFO -static void stm32pwm_dumpregs(struct stm32_pwmtimer_s *priv, - const char *msg); -#else -# define stm32pwm_dumpregs(priv,msg) -#endif - -/* Timer management */ - -static int stm32pwm_timer(struct stm32_pwmtimer_s *priv, - const struct pwm_info_s *info); -static int stm32pwm_output_configure(struct stm32_pwmtimer_s *priv, - uint8_t channel); -static int stm32pwm_update_duty(struct stm32_pwmtimer_s *priv, - uint8_t channel, ub16_t duty); -static void stm32pwm_setapbclock(struct stm32_pwmtimer_s *priv, bool on); - -/* PWM driver methods */ - -static int stm32pwm_setup(struct pwm_lowerhalf_s *dev); -static int stm32pwm_shutdown(struct pwm_lowerhalf_s *dev); - -static int stm32pwm_start(struct pwm_lowerhalf_s *dev, - const struct pwm_info_s *info); - -static int stm32pwm_stop(struct pwm_lowerhalf_s *dev); -static int stm32pwm_ioctl(struct pwm_lowerhalf_s *dev, - int cmd, unsigned long arg); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* This is the list of lower half PWM driver methods used by the upper half - * driver - */ - -static const struct pwm_ops_s g_pwmops = -{ - .setup = stm32pwm_setup, - .shutdown = stm32pwm_shutdown, - .start = stm32pwm_start, - .stop = stm32pwm_stop, - .ioctl = stm32pwm_ioctl, -}; - -#ifdef CONFIG_STM32F0L0G0_TIM1_PWM -static struct stm32_pwmtimer_s g_pwm1dev = -{ - .ops = &g_pwmops, - .timid = 1, - .channels = - { -#ifdef CONFIG_STM32F0L0G0_TIM1_CHANNEL1 - { - .channel = 1, - .pincfg = PWM_TIM1_CH1CFG, - .mode = CONFIG_STM32F0L0G0_TIM1_CH1MODE, - .npincfg = PWM_TIM1_CH1NCFG, - }, -#endif -#ifdef CONFIG_STM32F0L0G0_TIM1_CHANNEL2 - { - .channel = 2, - .pincfg = PWM_TIM1_CH2CFG, - .mode = CONFIG_STM32F0L0G0_TIM1_CH2MODE, - .npincfg = PWM_TIM1_CH2NCFG, - }, -#endif -#ifdef CONFIG_STM32F0L0G0_TIM1_CHANNEL3 - { - .channel = 3, - .pincfg = PWM_TIM1_CH3CFG, - .mode = CONFIG_STM32F0L0G0_TIM1_CH3MODE, - .npincfg = PWM_TIM1_CH3NCFG, - }, -#endif -#ifdef CONFIG_STM32F0L0G0_TIM1_CHANNEL4 - { - .channel = 4, - .pincfg = PWM_TIM1_CH4CFG, - .mode = CONFIG_STM32F0L0G0_TIM1_CH4MODE, - .npincfg = 0, - }, -#endif - }, - .timtype = TIMTYPE_TIM1, - .mode = CONFIG_STM32F0L0G0_TIM1_MODE, - .base = STM32_TIM1_BASE, - .pclk = STM32_APB2_TIM1_CLKIN, -}; -#endif - -#ifdef CONFIG_STM32F0L0G0_TIM2_PWM -static struct stm32_pwmtimer_s g_pwm2dev = -{ - .ops = &g_pwmops, - .timid = 2, - .channels = - { -#ifdef CONFIG_STM32F0L0G0_TIM2_CHANNEL1 - { - .channel = 1, - .pincfg = PWM_TIM2_CH1CFG, - .mode = CONFIG_STM32F0L0G0_TIM2_CH1MODE, - .npincfg = 0, - }, -#endif -#ifdef CONFIG_STM32F0L0G0_TIM2_CHANNEL2 - { - .channel = 2, - .pincfg = PWM_TIM2_CH2CFG, - .mode = CONFIG_STM32F0L0G0_TIM2_CH2MODE, - .npincfg = 0, - }, -#endif -#ifdef CONFIG_STM32F0L0G0_TIM2_CHANNEL3 - { - .channel = 3, - .pincfg = PWM_TIM2_CH3CFG, - .mode = CONFIG_STM32F0L0G0_TIM2_CH3MODE, - .npincfg = 0, - }, -#endif -#ifdef CONFIG_STM32F0L0G0_TIM2_CHANNEL4 - { - .channel = 4, - .pincfg = PWM_TIM2_CH4CFG, - .mode = CONFIG_STM32F0L0G0_TIM2_CH4MODE, - .npincfg = 0, - }, -#endif - }, - .timtype = TIMTYPE_TIM2, - .mode = CONFIG_STM32F0L0G0_TIM2_MODE, - .base = STM32_TIM2_BASE, - .pclk = STM32_APB1_TIM2_CLKIN, -}; -#endif - -#ifdef CONFIG_STM32F0L0G0_TIM3_PWM -static struct stm32_pwmtimer_s g_pwm3dev = -{ - .ops = &g_pwmops, - .timid = 3, - .channels = - { -#ifdef CONFIG_STM32F0L0G0_TIM3_CHANNEL1 - { - .channel = 1, - .pincfg = PWM_TIM3_CH1CFG, - .mode = CONFIG_STM32F0L0G0_TIM3_CH1MODE, - .npincfg = 0, - }, -#endif -#ifdef CONFIG_STM32F0L0G0_TIM3_CHANNEL2 - { - .channel = 2, - .pincfg = PWM_TIM3_CH2CFG, - .mode = CONFIG_STM32F0L0G0_TIM3_CH2MODE, - .npincfg = 0, - }, -#endif -#ifdef CONFIG_STM32F0L0G0_TIM3_CHANNEL3 - { - .channel = 3, - .pincfg = PWM_TIM3_CH3CFG, - .mode = CONFIG_STM32F0L0G0_TIM3_CH3MODE, - .npincfg = 0, - }, -#endif -#ifdef CONFIG_STM32F0L0G0_TIM3_CHANNEL4 - { - .channel = 4, - .pincfg = PWM_TIM3_CH4CFG, - .mode = CONFIG_STM32F0L0G0_TIM3_CH4MODE, - .npincfg = 0, - }, -#endif - }, - .timtype = TIMTYPE_TIM3, - .mode = CONFIG_STM32F0L0G0_TIM3_MODE, - .base = STM32_TIM3_BASE, - .pclk = STM32_APB1_TIM3_CLKIN, -}; -#endif - -#ifdef CONFIG_STM32F0L0G0_TIM14_PWM -static struct stm32_pwmtimer_s g_pwm14dev = -{ - .ops = &g_pwmops, - .timid = 14, - .channels = - { -#ifdef CONFIG_STM32F0L0G0_TIM14_CHANNEL1 - { - .channel = 1, - .pincfg = PWM_TIM14_CH1CFG, - .mode = CONFIG_STM32F0L0G0_TIM14_CH1MODE, - .npincfg = PWM_TIM14_CH1NCFG, - }, -#endif - }, - .timtype = TIMTYPE_TIM14, - .mode = STM32_TIMMODE_COUNTUP, - .base = STM32_TIM14_BASE, - .pclk = STM32_APB2_TIM14_CLKIN, -}; -#endif - -#ifdef CONFIG_STM32F0L0G0_TIM15_PWM -static struct stm32_pwmtimer_s g_pwm15dev = -{ - .ops = &g_pwmops, - .timid = 15, - .channels = - { -#ifdef CONFIG_STM32F0L0G0_TIM15_CHANNEL1 - { - .channel = 1, - .pincfg = PWM_TIM15_CH1CFG, - .mode = CONFIG_STM32F0L0G0_TIM15_CH1MODE, - .npincfg = PWM_TIM15_CH1NCFG, - }, -#endif -#ifdef CONFIG_STM32F0L0G0_TIM15_CHANNEL2 - { - .channel = 2, - .pincfg = PWM_TIM15_CH2CFG, - .mode = CONFIG_STM32F0L0G0_TIM15_CH2MODE, - .npincfg = 0, - }, -#endif - }, - .timtype = TIMTYPE_TIM15, - .mode = STM32_TIMMODE_COUNTUP, - .base = STM32_TIM15_BASE, - .pclk = STM32_APB2_TIM15_CLKIN, -}; -#endif - -#ifdef CONFIG_STM32F0L0G0_TIM16_PWM -static struct stm32_pwmtimer_s g_pwm16dev = -{ - .ops = &g_pwmops, - .timid = 16, - .channels = - { -#ifdef CONFIG_STM32F0L0G0_TIM16_CHANNEL1 - { - .channel = 1, - .pincfg = PWM_TIM16_CH1CFG, - .mode = CONFIG_STM32F0L0G0_TIM16_CH1MODE, - .npincfg = PWM_TIM16_CH1NCFG, - }, -#endif - }, - .timtype = TIMTYPE_TIM16, - .mode = STM32_TIMMODE_COUNTUP, - .base = STM32_TIM16_BASE, - .pclk = STM32_APB2_TIM16_CLKIN, -}; -#endif - -#ifdef CONFIG_STM32F0L0G0_TIM17_PWM -static struct stm32_pwmtimer_s g_pwm17dev = -{ - .ops = &g_pwmops, - .timid = 17, - .channels = - { -#ifdef CONFIG_STM32F0L0G0_TIM17_CHANNEL1 - { - .channel = 1, - .pincfg = PWM_TIM17_CH1CFG, - .mode = CONFIG_STM32F0L0G0_TIM17_CH1MODE, - .npincfg = PWM_TIM17_CH1NCFG, - }, -#endif - }, - .timtype = TIMTYPE_TIM17, - .mode = STM32_TIMMODE_COUNTUP, - .base = STM32_TIM17_BASE, - .pclk = STM32_APB2_TIM17_CLKIN, -}; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32pwm_reg_is_32bit - * - * Description: - * Verify whether the timer register is 32bit or not. - * - * Input Parameters: - * timtype - The type of the timer. See the TIMTYPE_* definitions - * offset - The offset to the register to read - * - * Returned Value: - * Return true for 32 bits register; false otherwise. - * - ****************************************************************************/ - -static bool stm32pwm_reg_is_32bit(uint8_t timtype, uint32_t offset) -{ - if (offset == STM32_GTIM_CCMR1_OFFSET || - offset == STM32_GTIM_SMCR_OFFSET || - offset == STM32_GTIM_BDTR_OFFSET) - { - return true; - } - - if (timtype == TIMTYPE_GENERAL16) - { - if (offset == STM32_GTIM_CCMR2_OFFSET || - offset == STM32_GTIM_AF1_OFFSET || - offset == STM32_GTIM_TISEL_OFFSET) - { - return true; - } - } - else if (timtype == TIMTYPE_GENERAL32) - { - if (offset == STM32_GTIM_CNT_OFFSET || - offset == STM32_GTIM_ARR_OFFSET || - offset == STM32_GTIM_CCR1_OFFSET || - offset == STM32_GTIM_CCR2_OFFSET || - offset == STM32_GTIM_CCR3_OFFSET || - offset == STM32_GTIM_CCR4_OFFSET) - { - return true; - } - } - else if (timtype == TIMTYPE_ADVANCED) - { - if (offset == STM32_ATIM_CR2_OFFSET || - offset == STM32_ATIM_CCMR2_OFFSET || - offset == STM32_ATIM_CCER_OFFSET || - offset == STM32_ATIM_DMAR_OFFSET || - offset == STM32_ATIM_CCMR3_OFFSET || - offset == STM32_ATIM_CCR5_OFFSET || - offset == STM32_ATIM_AF1_OFFSET || - offset == STM32_ATIM_TISEL_OFFSET) - { - return true; - } - } - - return false; -} - -/**************************************************************************** - * Name: stm32pwm_getreg - * - * Description: - * Read the value of an PWM timer register - * - * Input Parameters: - * priv - A reference to the PWM block status - * offset - The offset to the register to read - * - * Returned Value: - * The current contents of the specified register - * - ****************************************************************************/ - -static uint32_t stm32pwm_getreg(struct stm32_pwmtimer_s *priv, int offset) -{ - uint32_t retval; - - if (stm32pwm_reg_is_32bit(priv->timtype, offset) == true) - { - /* 32-bit register */ - - retval = getreg32(priv->base + offset); - } - else - { - /* 16-bit register */ - - retval = getreg16(priv->base + offset); - } - - /* Return 32-bit value */ - - return retval; -} - -/**************************************************************************** - * Name: stm32pwm_putreg - * - * Description: - * Read the value of an PWM timer register - * - * Input Parameters: - * priv - A reference to the PWM block status - * offset - The offset to the register to read - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void stm32pwm_putreg(struct stm32_pwmtimer_s *priv, int offset, - uint32_t value) -{ - if (stm32pwm_reg_is_32bit(priv->timtype, offset) == true) - { - /* 32-bit register */ - - putreg32(value, priv->base + offset); - } - else - { - /* 16-bit register */ - - putreg16((uint16_t)value, priv->base + offset); - } -} - -/**************************************************************************** - * Name: stm32pwm_modifyreg - * - * Description: - * Modify PWM register (32-bit or 16-bit) - * - * Input Parameters: - * priv - A reference to the PWM block status - * offset - The offset to the register to read - * clrbits - The bits to clear - * setbits - The bits to set - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void stm32pwm_modifyreg(struct stm32_pwmtimer_s *priv, - uint32_t offset, uint32_t clearbits, - uint32_t setbits) -{ - if (stm32pwm_reg_is_32bit(priv->timtype, offset) == true) - { - /* 32-bit register */ - - modifyreg32(priv->base + offset, clearbits, setbits); - } - else - { - /* 16-bit register */ - - modifyreg16(priv->base + offset, clearbits, setbits); - } -} - -/**************************************************************************** - * Name: stm32pwm_dumpregs - * - * Description: - * Dump all timer registers. - * - * Input Parameters: - * priv - A reference to the PWM block status - * msg - A message to be printed on the screen - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef CONFIG_DEBUG_PWM_INFO -static void stm32pwm_dumpregs(struct stm32_pwmtimer_s *priv, - const char *msg) -{ - pwminfo("%s:\n", msg); - pwminfo(" CR1: %04x CR2: %04x SMCR: %04x DIER: %04x\n", - stm32pwm_getreg(priv, STM32_GTIM_CR1_OFFSET), - stm32pwm_getreg(priv, STM32_GTIM_CR2_OFFSET), - stm32pwm_getreg(priv, STM32_GTIM_SMCR_OFFSET), - stm32pwm_getreg(priv, STM32_GTIM_DIER_OFFSET)); - pwminfo(" SR: %04x EGR: %04x CCMR1: %04x CCMR2: %04x\n", - stm32pwm_getreg(priv, STM32_GTIM_SR_OFFSET), - stm32pwm_getreg(priv, STM32_GTIM_EGR_OFFSET), - stm32pwm_getreg(priv, STM32_GTIM_CCMR1_OFFSET), - stm32pwm_getreg(priv, STM32_GTIM_CCMR2_OFFSET)); - pwminfo(" CCER: %04x CNT: %04x PSC: %04x ARR: %04x\n", - stm32pwm_getreg(priv, STM32_GTIM_CCER_OFFSET), - stm32pwm_getreg(priv, STM32_GTIM_CNT_OFFSET), - stm32pwm_getreg(priv, STM32_GTIM_PSC_OFFSET), - stm32pwm_getreg(priv, STM32_GTIM_ARR_OFFSET)); - pwminfo(" CCR1: %04x CCR2: %04x CCR3: %04x CCR4: %04x\n", - stm32pwm_getreg(priv, STM32_GTIM_CCR1_OFFSET), - stm32pwm_getreg(priv, STM32_GTIM_CCR2_OFFSET), - stm32pwm_getreg(priv, STM32_GTIM_CCR3_OFFSET), - stm32pwm_getreg(priv, STM32_GTIM_CCR4_OFFSET)); -#if defined(CONFIG_STM32F0L0G0_TIM1_PWM) || defined(CONFIG_STM32F0L0G0_TIM8_PWM) - if (priv->timtype == TIMTYPE_ADVANCED) - { - pwminfo(" RCR: %04x BDTR: %04x DCR: %04x DMAR: %04x\n", - stm32pwm_getreg(priv, STM32_ATIM_RCR_OFFSET), - stm32pwm_getreg(priv, STM32_ATIM_BDTR_OFFSET), - stm32pwm_getreg(priv, STM32_ATIM_DCR_OFFSET), - stm32pwm_getreg(priv, STM32_ATIM_DMAR_OFFSET)); - - pwminfo(" AF1: %04x TISEL: %04x\n", - stm32pwm_getreg(priv, STM32_ATIM_AF1_OFFSET), - stm32pwm_getreg(priv, STM32_ATIM_TISEL_OFFSET)); - } - else -#endif - { - pwminfo(" RCR: %04x BDTR: %04x DCR: %04x DMAR: %04x\n", - stm32pwm_getreg(priv, STM32_GTIM_RCR_OFFSET), - stm32pwm_getreg(priv, STM32_GTIM_BDTR_OFFSET), - stm32pwm_getreg(priv, STM32_GTIM_DCR_OFFSET), - stm32pwm_getreg(priv, STM32_GTIM_DMAR_OFFSET)); - pwminfo(" AF1: %04x TISEL: %04x\n", - stm32pwm_getreg(priv, STM32_GTIM_AF1_OFFSET), - stm32pwm_getreg(priv, STM32_GTIM_TISEL_OFFSET)); - } -} -#endif - -/**************************************************************************** - * Name: stm32pwm_output_configure - * - * Description: - * Configure PWM output for given channel - * - * Input Parameters: - * priv - A reference to the PWM block status - * channel - Timer output channel - * - * Returned Value: - * Zero on success; - ****************************************************************************/ - -static int stm32pwm_output_configure(struct stm32_pwmtimer_s *priv, - uint8_t channel) -{ - uint32_t cr2; - uint32_t ccer; - - /* Get current registers state */ - - cr2 = stm32pwm_getreg(priv, STM32_GTIM_CR2_OFFSET); - ccer = stm32pwm_getreg(priv, STM32_GTIM_CCER_OFFSET); - - /* Reset the output polarity level of all channels (selects high - * polarity) - */ - - ccer &= ~(GTIM_CCER_CC1P << ((channel - 1) * 4)); - - /* Enable the output state of the selected channels */ - - ccer |= (GTIM_CCER_CC1E << ((channel - 1) * 4)); - -#ifdef HAVE_ADVTIM - if (priv->timtype == TIMTYPE_ADVANCED || - priv->timtype == TIMTYPE_COUNTUP16_N) - { - cr2 &= ~(ATIM_CR2_OIS1 << ((channel - 1) * 2)); - } -#ifdef HAVE_PWM_COMPLEMENTARY - - /* Verify if the current complementary channel is defined */ - - if (priv->channels[channel - 1].npincfg != 0) - { - /* Configure complementary output IDLE state */ - - cr2 &= ~(ATIM_CR2_OIS1N << ((channel - 1) * 2)); - - /* Enable the complementary output state of the selected channels */ - - ccer |= (ATIM_CCER_CC1NE << ((channel - 1) * 4)); - - /* Configure complementary output polarity */ - - ccer &= ~(ATIM_CCER_CC1NP << ((channel - 1) * 4)); - } -#endif /* HAVE_PWM_COMPLEMENTARY */ -#endif /* HAVE_ADVTIM */ - - stm32pwm_modifyreg(priv, STM32_GTIM_CR2_OFFSET, 0, cr2); - stm32pwm_modifyreg(priv, STM32_GTIM_CCER_OFFSET, 0, ccer); - - return OK; -} - -/**************************************************************************** - * Name: stm32pwm_timer - * - * Description: - * (Re-)initialize the timer resources and start the pulsed output - * - * Input Parameters: - * priv - A reference to the lower half PWM driver state structure - * info - A reference to the characteristics of the pulsed output - * - * Returned Value: - * Zero on success; a negated errno value on failure - * - ****************************************************************************/ - -static int stm32pwm_timer(struct stm32_pwmtimer_s *priv, - const struct pwm_info_s *info) -{ - int i; - - /* Calculated values */ - - uint32_t prescaler; - uint32_t timclk; - uint32_t reload; - uint32_t ccr; - - /* Register contents */ - - uint32_t cr1; - uint32_t ccmr1; -#if defined(HAVE_CCMR2) - uint32_t ccmr2; - uint32_t ocmode2; -#endif - - /* New timer register bit settings */ - - uint32_t ocmode1; - - DEBUGASSERT(priv != NULL && info != NULL); - - ccmr1 = stm32pwm_getreg(priv, STM32_GTIM_CCMR1_OFFSET); - -#if defined(HAVE_CCMR2) - ccmr2 = stm32pwm_getreg(priv, STM32_GTIM_CCMR2_OFFSET); -#endif - - pwminfo("TIM%u frequency: %" PRIu32 "\n", - priv->timid, info->frequency); - - DEBUGASSERT(info->frequency > 0); - - /* Disable all interrupts and DMA requests, clear all pending status */ - - /* Calculate optimal values for the timer prescaler and for the timer - * reload register. If 'frequency' is the desired frequency, then - * - * reload = timclk / frequency - * timclk = pclk / presc - * - * Or, - * - * reload = pclk / presc / frequency - * - * There are many solutions to this, but the best solution will be the - * one that has the largest reload value and the smallest prescaler value. - * That is the solution that should give us the most accuracy in the timer - * control. Subject to: - * - * 0 <= presc <= 65536 - * 1 <= reload <= 65535 - * - * So presc = pclk / 65535 / frequency would be optimal. - * - * Example: - * - * pclk = 42 MHz - * frequency = 100 Hz - * - * prescaler = 42,000,000 / 65,535 / 100 - * = 6.4 (or 7 -- taking the ceiling always) - * timclk = 42,000,000 / 7 - * = 6,000,000 - * reload = 6,000,000 / 100 - * = 60,000 - */ - - prescaler = (priv->pclk / info->frequency + 65534) / 65535; - if (prescaler < 1) - { - prescaler = 1; - } - else if (prescaler > 65536) - { - prescaler = 65536; - } - - timclk = priv->pclk / prescaler; - - reload = timclk / info->frequency; - - /* In center-aligned mode, the timer performs upcounting from zero to ARR - * value and then performs downcounting from ARR to zero and repeat. In - * other words, in one cycle the timer counts 2*ARR. For that reason, the - * reload (ARR) value is divided by 2. - */ - - if (priv->mode == STM32_TIMMODE_CENTER1 || - priv->mode == STM32_TIMMODE_CENTER2 || - priv->mode == STM32_TIMMODE_CENTER3) - { - reload /= 2; - } - - if (reload < 2) - { - reload = 1; - } - else if (reload > 65535) - { - reload = 65535; - } - else - { - reload--; - } - - pwminfo("TIM%u PCLK: %" PRIu32 " frequency: %" PRIu32 " " - "TIMCLK: %" PRIu32 " prescaler: %" PRIu32 - " reload: %" PRIu32 "\n", - priv->timid, priv->pclk, info->frequency, timclk, - prescaler, reload); - - /* Set up the timer CR1 register: - * - * 1,8 CKD[1:0] ARPE CMS[1:0] DIR OPM URS UDIS CEN - * 2-5 CKD[1:0] ARPE CMS DIR OPM URS UDIS CEN - * 6-7 ARPE OPM URS UDIS CEN - * 9-14 CKD[1:0] ARPE URS UDIS CEN - * 15-17 CKD[1:0] ARPE OPM URS UDIS CEN - */ - - cr1 = stm32pwm_getreg(priv, STM32_GTIM_CR1_OFFSET); - - /* Disable the timer until we get it configured */ - - cr1 &= ~GTIM_CR1_CEN; - - /* Set the counter mode for the advanced timers (1,8) and most general - * purpose timers (all 2-5, but not 9-17), i.e., all but TIMTYPE_COUNTUP16 - * and TIMTYPE_BASIC - */ - -#if defined(CONFIG_STM32F0L0G0_TIM1_PWM) || defined(CONFIG_STM32F0L0G0_TIM2_PWM) || \ - defined(CONFIG_STM32F0L0G0_TIM3_PWM) || defined(CONFIG_STM32F0L0G0_TIM4_PWM) || \ - defined(CONFIG_STM32F0L0G0_TIM5_PWM) || defined(CONFIG_STM32F0L0G0_TIM8_PWM) - - if (priv->timtype != TIMTYPE_BASIC && priv->timtype != TIMTYPE_COUNTUP16 && - priv->timtype != TIMTYPE_COUNTUP16_N) - { - /* Select the Counter Mode: - * - * GTIM_CR1_EDGE: The counter counts up or down depending on the - * direction bit (DIR). - * GTIM_CR1_CENTER1, GTIM_CR1_CENTER2, GTIM_CR1_CENTER3: The counter - * counts up then down. - * GTIM_CR1_DIR: 0: count up, 1: count down - */ - - cr1 &= ~(GTIM_CR1_DIR | GTIM_CR1_CMS_MASK); - - switch (priv->mode) - { - case STM32_TIMMODE_COUNTUP: - cr1 |= GTIM_CR1_EDGE; - break; - - case STM32_TIMMODE_COUNTDOWN: - cr1 |= GTIM_CR1_EDGE | GTIM_CR1_DIR; - break; - - case STM32_TIMMODE_CENTER1: - cr1 |= GTIM_CR1_CENTER1; - break; - - case STM32_TIMMODE_CENTER2: - cr1 |= GTIM_CR1_CENTER2; - break; - - case STM32_TIMMODE_CENTER3: - cr1 |= GTIM_CR1_CENTER3; - break; - - default: - pwmerr("ERROR: No such timer mode: %u\n", - (unsigned int)priv->mode); - return -EINVAL; - } - } -#endif - - /* Set the clock division to zero for all (but the basic timers, but there - * should be no basic timers in this context - */ - - cr1 &= ~GTIM_CR1_CKD_MASK; - stm32pwm_putreg(priv, STM32_GTIM_CR1_OFFSET, cr1); - - /* Set the reload and prescaler values */ - - stm32pwm_putreg(priv, STM32_GTIM_ARR_OFFSET, reload); - stm32pwm_putreg(priv, STM32_GTIM_PSC_OFFSET, (prescaler - 1)); - - /* Set the advanced timer's repetition counter */ - -#if defined(CONFIG_STM32F0L0G0_TIM1_PWM) || defined(CONFIG_STM32F0L0G0_TIM8_PWM) - if (priv->timtype == TIMTYPE_ADVANCED) - { - /* If a non-zero repetition count has been selected, then set the - * repetition counter to the count-1 (stm32pwm_start() has already - * assured us that the count value is within range). - */ - - { - /* Set the repetition counter to zero */ - - stm32pwm_putreg(priv, STM32_ATIM_RCR_OFFSET, 0); - - /* Generate an update event to reload the prescaler */ - - stm32pwm_putreg(priv, STM32_ATIM_EGR_OFFSET, ATIM_EGR_UG); - } - } - else -#endif - { - /* Generate an update event to reload the prescaler (all timers) */ - - stm32pwm_putreg(priv, STM32_GTIM_EGR_OFFSET, GTIM_EGR_UG); - } - - /* Handle channel specific setup */ - - ocmode1 = 0; -#if defined(HAVE_CCMR2) - ocmode2 = 0; -#endif - - for (i = 0; i < CONFIG_PWM_NCHANNELS; i++) - { - ub16_t duty; - uint32_t chanmode; - bool ocmbit = false; - uint8_t channel; - int j; - enum stm32_chanmode_e mode; - - /* Break the loop if all following channels are not configured */ - - if (info->channels[i].channel == -1) - { - break; - } - - duty = info->channels[i].duty; - channel = info->channels[i].channel; - - /* A value of zero means to skip this channel */ - - if (channel == 0) - { - continue; - } - - /* Find the channel */ - - for (j = 0; j < PWM_NCHANNELS; j++) - { - if (priv->channels[j].channel == channel) - { - mode = priv->channels[j].mode; - break; - } - } - - if (j >= PWM_NCHANNELS) - { - pwmerr("ERROR: No such channel: %u\n", channel); - return -EINVAL; - } - - /* Duty cycle: - * - * duty cycle = ccr / reload (fractional value) - */ - - ccr = b16toi(duty * reload + b16HALF); - - pwminfo("ccr: %" PRIu32 "\n", ccr); - - switch (mode) - { - case STM32_CHANMODE_PWM1: - chanmode = GTIM_CCMR_MODE_PWM1; - break; - - case STM32_CHANMODE_PWM2: - chanmode = GTIM_CCMR_MODE_PWM2; - break; - - case STM32_CHANMODE_COMBINED1: - chanmode = GTIM_CCMR_MODE_COMBINED1; - ocmbit = true; - break; - - case STM32_CHANMODE_COMBINED2: - chanmode = GTIM_CCMR_MODE_COMBINED2; - ocmbit = true; - break; - - case STM32_CHANMODE_ASYMMETRIC1: - chanmode = GTIM_CCMR_MODE_ASYMMETRIC1; - ocmbit = true; - break; - - case STM32_CHANMODE_ASYMMETRIC2: - chanmode = GTIM_CCMR_MODE_ASYMMETRIC2; - ocmbit = true; - break; - - default: - pwmerr("ERROR: No such mode: %u\n", (unsigned int)mode); - return -EINVAL; - } - - switch (channel) - { - case 1: /* PWM Mode configuration: Channel 1 */ - { - /* Set the CCMR1 mode values (leave CCMR2 zero) */ - - ocmode1 |= (GTIM_CCMR_CCS_CCOUT << GTIM_CCMR1_CC1S_SHIFT) | - (chanmode << GTIM_CCMR1_OC1M_SHIFT) | - GTIM_CCMR1_OC1PE; - - if (ocmbit) - { - ocmode1 |= GTIM_CCMR1_OC1M; - } - - /* Set the duty cycle by writing to the CCR register for this - * channel. - */ - - stm32pwm_putreg(priv, STM32_GTIM_CCR1_OFFSET, ccr); - - /* Reset the Output Compare Mode Bits and set the select - * output compare mode. - */ - - ccmr1 &= ~(GTIM_CCMR1_CC1S_MASK | GTIM_CCMR1_OC1M_MASK | - GTIM_CCMR1_OC1PE | GTIM_CCMR1_OC1M); - stm32pwm_output_configure(priv, channel); - } - break; - - case 2: /* PWM Mode configuration: Channel 2 */ - { - /* Set the CCMR1 mode values (leave CCMR2 zero) */ - - ocmode1 |= (GTIM_CCMR_CCS_CCOUT << GTIM_CCMR1_CC2S_SHIFT) | - (chanmode << GTIM_CCMR1_OC2M_SHIFT) | - GTIM_CCMR1_OC2PE; - - if (ocmbit) - { - ocmode1 |= GTIM_CCMR1_OC2M; - } - - /* Set the duty cycle by writing to the CCR register for this - * channel. - */ - - stm32pwm_putreg(priv, STM32_GTIM_CCR2_OFFSET, ccr); - - /* Reset the Output Compare Mode Bits and set the select - * output compare mode. - */ - - ccmr1 &= ~(GTIM_CCMR1_CC2S_MASK | GTIM_CCMR1_OC2M_MASK | - GTIM_CCMR1_OC2PE | GTIM_CCMR1_OC2M); - stm32pwm_output_configure(priv, channel); - } - break; - -#if defined(HAVE_CCMR2) - case 3: /* PWM Mode configuration: Channel 3 */ - { - /* Set the CCMR2 mode values (leave CCMR1 zero) */ - - ocmode2 |= (ATIM_CCMR_CCS_CCOUT << ATIM_CCMR2_CC3S_SHIFT) | - (chanmode << ATIM_CCMR2_OC3M_SHIFT) | - ATIM_CCMR2_OC3PE; - - if (ocmbit) - { - ocmode2 |= ATIM_CCMR2_OC3M; - } - - /* Set the duty cycle by writing to the CCR register for this - * channel. - */ - - stm32pwm_putreg(priv, STM32_ATIM_CCR3_OFFSET, ccr); - - /* Reset the Output Compare Mode Bits and set the select - * output compare mode. - */ - - ccmr2 &= ~(ATIM_CCMR2_CC3S_MASK | ATIM_CCMR2_OC3M_MASK | - ATIM_CCMR2_OC3PE | ATIM_CCMR2_OC3M); - stm32pwm_output_configure(priv, channel); - } - break; - - case 4: /* PWM Mode configuration: Channel 4 */ - { - /* Set the CCMR2 mode values (leave CCMR1 zero) */ - - ocmode2 |= (ATIM_CCMR_CCS_CCOUT << ATIM_CCMR2_CC4S_SHIFT) | - (chanmode << ATIM_CCMR2_OC4M_SHIFT) | - ATIM_CCMR2_OC4PE; - - if (ocmbit) - { - ocmode2 |= ATIM_CCMR2_OC4M; - } - - /* Set the duty cycle by writing to the CCR register for this - * channel. - */ - - stm32pwm_putreg(priv, STM32_ATIM_CCR4_OFFSET, ccr); - - /* Reset the Output Compare Mode Bits and set the select - * output compare mode. - */ - - ccmr2 &= ~(ATIM_CCMR2_CC4S_MASK | ATIM_CCMR2_OC4M_MASK | - ATIM_CCMR2_OC4PE | ATIM_CCMR2_OC4M); - stm32pwm_output_configure(priv, channel); - } - break; -#endif /* HAVE_CCMR2 */ - default: - pwmerr("ERROR: No such channel: %u\n", channel); - return -EINVAL; - } - } - - ccmr1 |= ocmode1; -#if defined(HAVE_CCMR2) - ccmr2 |= ocmode2; -#endif - - /* Special configuration for HAVE_ADVTIM */ - -#ifdef HAVE_ADVTIM - if (priv->timtype == TIMTYPE_ADVANCED || - priv->timtype == TIMTYPE_COUNTUP16_N) - { - uint32_t bdtr; - - /* Get current register state */ - - bdtr = stm32pwm_getreg(priv, STM32_ATIM_BDTR_OFFSET); - - /* Update deadtime */ - - bdtr &= ~(ATIM_BDTR_OSSI | ATIM_BDTR_OSSR); - bdtr |= ATIM_BDTR_MOE; - - stm32pwm_putreg(priv, STM32_ATIM_BDTR_OFFSET, bdtr); - } -#endif - - /* Save the modified register values */ - - putreg32(ccmr1, priv->base + STM32_GTIM_CCMR1_OFFSET); -#if defined(HAVE_CCMR2) - putreg32(ccmr2, priv->base + STM32_ATIM_CCMR2_OFFSET); -#endif - - /* Set the ARR Preload Bit */ - - cr1 = stm32pwm_getreg(priv, STM32_GTIM_CR1_OFFSET); - cr1 |= GTIM_CR1_ARPE; - stm32pwm_putreg(priv, STM32_GTIM_CR1_OFFSET, cr1); - - /* Just enable the timer, leaving all interrupts disabled */ - - cr1 |= GTIM_CR1_CEN; - stm32pwm_putreg(priv, STM32_GTIM_CR1_OFFSET, cr1); - - stm32pwm_dumpregs(priv, "After starting"); - return OK; -} - -/**************************************************************************** - * Name: stm32pwm_update_duty - * - * Description: - * Try to change only channel duty. - * - * Input Parameters: - * priv - A reference to the lower half PWM driver state structure - * channel - Channel to be updated - * duty - New duty. - * - * Returned Value: - * Zero on success; a negated errno value on failure - * - ****************************************************************************/ - -static int stm32pwm_update_duty(struct stm32_pwmtimer_s *priv, - uint8_t channel, ub16_t duty) -{ - /* Register offset */ - - int ccr_offset; - - /* Calculated values */ - - uint32_t reload; - uint32_t ccr; - - DEBUGASSERT(priv != NULL); - - pwminfo("TIM%u channel: %u duty: %08" PRIx32 "\n", - priv->timid, channel, duty); - - /* Get the reload values */ - - reload = stm32pwm_getreg(priv, STM32_GTIM_ARR_OFFSET); - - /* Duty cycle: - * - * duty cycle = ccr / reload (fractional value) - */ - - ccr = b16toi(duty * reload + b16HALF); - - pwminfo("ccr: %" PRIu32 "\n", ccr); - - switch (channel) - { - case 1: /* Register offset for Channel 1 */ - ccr_offset = STM32_GTIM_CCR1_OFFSET; - break; - - case 2: /* Register offset for Channel 2 */ - ccr_offset = STM32_GTIM_CCR2_OFFSET; - break; - - case 3: /* Register offset for Channel 3 */ - ccr_offset = STM32_GTIM_CCR3_OFFSET; - break; - - case 4: /* Register offset for Channel 4 */ - ccr_offset = STM32_GTIM_CCR4_OFFSET; - break; - - default: - pwmerr("ERROR: No such channel: %u\n", channel); - return -EINVAL; - } - - /* Set the duty cycle by writing to the CCR register for this channel */ - - stm32pwm_putreg(priv, ccr_offset, ccr); - - return OK; -} - -/**************************************************************************** - * Name: stm32pwm_setapbclock - * - * Description: - * Enable or disable APB clock for the timer peripheral - * - * Input Parameters: - * dev - A reference to the lower half PWM driver state structure - * on - Enable clock if 'on' is 'true' and disable if 'false' - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void stm32pwm_setapbclock(struct stm32_pwmtimer_s *priv, bool on) -{ - uint32_t en_bit; - uint32_t regaddr; - - /* Determine which timer to configure */ - - switch (priv->timid) - { -#ifdef CONFIG_STM32F0L0G0_TIM1_PWM - case 1: - regaddr = STM32_RCC_APB2ENR; - en_bit = RCC_APB2ENR_TIM1EN; - break; -#endif -#ifdef CONFIG_STM32F0L0G0_TIM2_PWM - case 2: - regaddr = STM32_RCC_APB1ENR; - en_bit = RCC_APB1ENR_TIM2EN; - break; -#endif -#ifdef CONFIG_STM32F0L0G0_TIM3_PWM - case 3: - regaddr = STM32_RCC_APB1ENR; - en_bit = RCC_APB1ENR_TIM3EN; - break; -#endif -#ifdef CONFIG_STM32F0L0G0_TIM14_PWM - case 14: - regaddr = STM32_RCC_APB2ENR; - en_bit = RCC_APB2ENR_TIM14EN; - break; -#endif -#ifdef CONFIG_STM32F0L0G0_TIM15_PWM - case 15: - regaddr = STM32_RCC_APB2ENR; - en_bit = RCC_APB2ENR_TIM15EN; - break; -#endif -#ifdef CONFIG_STM32F0L0G0_TIM16_PWM - case 16: - regaddr = STM32_RCC_APB2ENR; - en_bit = RCC_APB2ENR_TIM16EN; - break; -#endif -#ifdef CONFIG_STM32F0L0G0_TIM17_PWM - case 17: - regaddr = STM32_RCC_APB2ENR; - en_bit = RCC_APB2ENR_TIM17EN; - break; -#endif - default: - return; - } - - /* Enable/disable APB 1/2 clock for timer */ - - if (on) - { - modifyreg32(regaddr, 0, en_bit); - } - else - { - modifyreg32(regaddr, en_bit, 0); - } -} - -/**************************************************************************** - * Name: stm32pwm_setup - * - * Description: - * This method is called when the driver is opened. The lower half driver - * should configure and initialize the device so that it is ready for use. - * It should not, however, output pulses until the start method is called. - * - * Input Parameters: - * dev - A reference to the lower half PWM driver state structure - * - * Returned Value: - * Zero on success; a negated errno value on failure - * - * Assumptions: - * APB1 or 2 clocking for the GPIOs has already been configured by the RCC - * logic at power up. - * - ****************************************************************************/ - -static int stm32pwm_setup(struct pwm_lowerhalf_s *dev) -{ - struct stm32_pwmtimer_s *priv = (struct stm32_pwmtimer_s *)dev; - uint32_t pincfg; - int i; - - pwminfo("TIM%u\n", priv->timid); - stm32pwm_dumpregs(priv, "Initially"); - - /* Enable APB1/2 clocking for timer. */ - - stm32pwm_setapbclock(priv, true); - - /* Configure the PWM output pins, but do not start the timer yet */ - - for (i = 0; i < PWM_NCHANNELS; i++) - { - pincfg = priv->channels[i].pincfg; - if (pincfg != 0) - { - pwminfo("pincfg: %08" PRIx32 "\n", pincfg); - - stm32_configgpio(pincfg); - } - - /* Enable complementary channel if available */ - - pincfg = priv->channels[i].npincfg; - if (pincfg != 0) - { - pwminfo("npincfg: %08" PRIx32 "\n", pincfg); - - stm32_configgpio(pincfg); - } - - pwm_dumpgpio(pincfg, "PWM setup"); - } - - return OK; -} - -/**************************************************************************** - * Name: stm32pwm_shutdown - * - * Description: - * This method is called when the driver is closed. The lower half driver - * stop pulsed output, free any resources, disable the timer hardware, and - * put the system into the lowest possible power usage state - * - * Input Parameters: - * dev - A reference to the lower half PWM driver state structure - * - * Returned Value: - * Zero on success; a negated errno value on failure - * - ****************************************************************************/ - -static int stm32pwm_shutdown(struct pwm_lowerhalf_s *dev) -{ - struct stm32_pwmtimer_s *priv = (struct stm32_pwmtimer_s *)dev; - uint32_t pincfg; - int i; - - pwminfo("TIM%u\n", priv->timid); - - /* Make sure that the output has been stopped */ - - stm32pwm_stop(dev); - - /* Disable APB1/2 clocking for timer. */ - - stm32pwm_setapbclock(priv, false); - - /* Then put the GPIO pins back to the default state */ - - for (i = 0; i < PWM_NCHANNELS; i++) - { - pincfg = priv->channels[i].pincfg; - if (pincfg != 0) - { - pwminfo("pincfg: %08" PRIx32 "\n", pincfg); - - pincfg &= (GPIO_PORT_MASK | GPIO_PIN_MASK); - pincfg |= GPIO_INPUT | GPIO_FLOAT; - - stm32_configgpio(pincfg); - } - - pincfg = priv->channels[i].npincfg; - if (pincfg != 0) - { - pwminfo("npincfg: %08" PRIx32 "\n", pincfg); - - pincfg &= (GPIO_PORT_MASK | GPIO_PIN_MASK); - pincfg |= GPIO_INPUT | GPIO_FLOAT; - - stm32_configgpio(pincfg); - } - } - - return OK; -} - -/**************************************************************************** - * Name: stm32pwm_start - * - * Description: - * (Re-)initialize the timer resources and start the pulsed output - * - * Input Parameters: - * dev - A reference to the lower half PWM driver state structure - * info - A reference to the characteristics of the pulsed output - * - * Returned Value: - * Zero on success; a negated errno value on failure - * - ****************************************************************************/ - -static int stm32pwm_start(struct pwm_lowerhalf_s *dev, - const struct pwm_info_s *info) -{ - int ret = OK; - struct stm32_pwmtimer_s *priv = (struct stm32_pwmtimer_s *)dev; - - /* if frequency has not changed we just update duty */ - - if (info->frequency == priv->frequency) - { - int i; - - for (i = 0; ret == OK && i < CONFIG_PWM_NCHANNELS; i++) - { - /* Break the loop if all following channels are not configured */ - - if (info->channels[i].channel == -1) - { - break; - } - - /* Set output if channel configured */ - - if (info->channels[i].channel != 0) - { - ret = stm32pwm_update_duty(priv, info->channels[i].channel, - info->channels[i].duty); - } - } - } - else - { - ret = stm32pwm_timer(priv, info); - - /* Save current frequency */ - - if (ret == OK) - { - priv->frequency = info->frequency; - } - } - - return ret; -} - -/**************************************************************************** - * Name: stm32pwm_stop - * - * Description: - * Stop the pulsed output and reset the timer resources - * - * Input Parameters: - * dev - A reference to the lower half PWM driver state structure - * - * Returned Value: - * Zero on success; a negated errno value on failure - * - * Assumptions: - * This function is called to stop the pulsed output at anytime. This - * method is also called from the timer interrupt handler when a repetition - * count expires... automatically stopping the timer. - * - ****************************************************************************/ - -static int stm32pwm_stop(struct pwm_lowerhalf_s *dev) -{ - struct stm32_pwmtimer_s *priv = (struct stm32_pwmtimer_s *)dev; - uint32_t resetbit; - uint32_t regaddr; - uint32_t regval; - irqstate_t flags; - - pwminfo("TIM%u\n", priv->timid); - - /* Disable interrupts momentary to stop any ongoing timer processing and - * to prevent any concurrent access to the reset register. - */ - - flags = enter_critical_section(); - - /* Stopped so frequency is zero */ - - priv->frequency = 0; - - /* Disable further interrupts and stop the timer */ - - stm32pwm_putreg(priv, STM32_GTIM_DIER_OFFSET, 0); - stm32pwm_putreg(priv, STM32_GTIM_SR_OFFSET, 0); - - /* Determine which timer to reset */ - - switch (priv->timid) - { -#ifdef CONFIG_STM32F0L0G0_TIM1_PWM - case 1: - regaddr = STM32_RCC_APB2RSTR; - resetbit = RCC_APB2RSTR_TIM1RST; - break; -#endif - -#ifdef CONFIG_STM32F0L0G0_TIM2_PWM - case 2: - regaddr = STM32_RCC_APB1RSTR; - resetbit = RCC_APB1RSTR_TIM2RST; - break; -#endif - -#ifdef CONFIG_STM32F0L0G0_TIM3_PWM - case 3: - regaddr = STM32_RCC_APB1RSTR; - resetbit = RCC_APB1RSTR_TIM3RST; - break; -#endif - -#ifdef CONFIG_STM32F0L0G0_TIM4_PWM - case 4: - regaddr = STM32_RCC_APB1RSTR; - resetbit = RCC_APB1RSTR_TIM4RST; - break; -#endif - -#ifdef CONFIG_STM32F0L0G0_TIM5_PWM - case 5: - regaddr = STM32_RCC_APB1RSTR; - resetbit = RCC_APB1RSTR_TIM5RST; - break; -#endif - -#ifdef CONFIG_STM32F0L0G0_TIM8_PWM - case 8: - regaddr = STM32_RCC_APB2RSTR; - resetbit = RCC_APB2RSTR_TIM8RST; - break; -#endif - -#ifdef CONFIG_STM32F0L0G0_TIM14_PWM - case 14: - regaddr = STM32_RCC_APB2RSTR; - resetbit = RCC_APB2RSTR_TIM14RST; - break; -#endif - -#ifdef CONFIG_STM32F0L0G0_TIM15_PWM - case 15: - regaddr = STM32_RCC_APB2RSTR; - resetbit = RCC_APB2RSTR_TIM15RST; - break; -#endif - -#ifdef CONFIG_STM32F0L0G0_TIM16_PWM - case 16: - regaddr = STM32_RCC_APB2RSTR; - resetbit = RCC_APB2RSTR_TIM16RST; - break; -#endif - -#ifdef CONFIG_STM32F0L0G0_TIM17_PWM - case 17: - regaddr = STM32_RCC_APB2RSTR; - resetbit = RCC_APB2RSTR_TIM17RST; - break; -#endif - - default: - leave_critical_section(flags); - return -EINVAL; - } - - /* Reset the timer - stopping the output and putting the timer back - * into a state where stm32pwm_start() can be called. - */ - - regval = getreg32(regaddr); - regval |= resetbit; - putreg32(regval, regaddr); - - regval &= ~resetbit; - putreg32(regval, regaddr); - leave_critical_section(flags); - - pwminfo("regaddr: %08" PRIx32 " resetbit: %08" PRIx32 "\n", - regaddr, resetbit); - stm32pwm_dumpregs(priv, "After stop"); - return OK; -} - -/**************************************************************************** - * Name: stm32pwm_ioctl - * - * Description: - * Lower-half logic may support platform-specific ioctl commands - * - * Input Parameters: - * dev - A reference to the lower half PWM driver state structure - * cmd - The ioctl command - * arg - The argument accompanying the ioctl command - * - * Returned Value: - * Zero on success; a negated errno value on failure - * - ****************************************************************************/ - -static int stm32pwm_ioctl(struct pwm_lowerhalf_s *dev, int cmd, - unsigned long arg) -{ -#ifdef CONFIG_DEBUG_PWM_INFO - struct stm32_pwmtimer_s *priv = (struct stm32_pwmtimer_s *)dev; - - /* There are no platform-specific ioctl commands */ - - pwminfo("TIM%u\n", priv->timid); -#endif - return -ENOTTY; -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_pwminitialize - * - * Description: - * Initialize one timer for use with the upper_level PWM driver. - * - * Input Parameters: - * timer - A number identifying the timer use. The number of valid timer - * IDs varies with the STM32 MCU and MCU family but is somewhere in - * the range of {1,..,17}. - * - * Returned Value: - * On success, a pointer to the STM32 lower half PWM driver is returned. - * NULL is returned on any failure. - * - ****************************************************************************/ - -struct pwm_lowerhalf_s *stm32_pwminitialize(int timer) -{ - struct stm32_pwmtimer_s *lower; - - pwminfo("TIM%u\n", timer); - - switch (timer) - { -#ifdef CONFIG_STM32F0L0G0_TIM1_PWM - case 1: - lower = &g_pwm1dev; - - /* Attach but disable the TIM1 update interrupt */ - - break; -#endif - -#ifdef CONFIG_STM32F0L0G0_TIM2_PWM - case 2: - lower = &g_pwm2dev; - break; -#endif - -#ifdef CONFIG_STM32F0L0G0_TIM3_PWM - case 3: - lower = &g_pwm3dev; - break; -#endif - -#ifdef CONFIG_STM32F0L0G0_TIM4_PWM - case 4: - lower = &g_pwm4dev; - break; -#endif - -#ifdef CONFIG_STM32F0L0G0_TIM5_PWM - case 5: - lower = &g_pwm5dev; - break; -#endif - -#ifdef CONFIG_STM32F0L0G0_TIM8_PWM - case 8: - lower = &g_pwm8dev; - - /* Attach but disable the TIM8 update interrupt */ - - break; -#endif - -#ifdef CONFIG_STM32F0L0G0_TIM14_PWM - case 14: - lower = &g_pwm14dev; - break; -#endif - -#ifdef CONFIG_STM32F0L0G0_TIM15_PWM - case 15: - lower = &g_pwm15dev; - break; -#endif - -#ifdef CONFIG_STM32F0L0G0_TIM16_PWM - case 16: - lower = &g_pwm16dev; - break; -#endif - -#ifdef CONFIG_STM32F0L0G0_TIM17_PWM - case 17: - lower = &g_pwm17dev; - break; -#endif - - default: - pwmerr("ERROR: No such timer configured\n"); - return NULL; - } - - return (struct pwm_lowerhalf_s *)lower; -} - -#endif /* CONFIG_STM32F0L0G0_TIMx_PWM */ diff --git a/arch/arm/src/stm32f0l0g0/stm32_pwm.h b/arch/arm/src/stm32f0l0g0/stm32_pwm.h deleted file mode 100644 index 88683b9b6626e..0000000000000 --- a/arch/arm/src/stm32f0l0g0/stm32_pwm.h +++ /dev/null @@ -1,571 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_pwm.h - * - * SPDX-License-Identifier: BSD-3-Clause - * SPDX-FileCopyrightText: 2019 Fundação CERTI. All rights reserved. - * SPDX-FileContributor: Daniel Pereira Volpato - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_STM32_PWM_H -#define __ARCH_ARM_SRC_STM32F0L0G0_STM32_PWM_H - -/* The STM32F0L0G0 does not have dedicated PWM hardware. Rather, pulsed - * output control is a capability of the STM32F0L0G0 timers. The logic in - * this file implements the lower half of the standard, NuttX PWM interface - * using the STM32F0L0G0 timers. That interface is described in - * include/nuttx/timers/pwm.h. - */ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include - -#include - -#include "chip.h" -#include "hardware/stm32_tim.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -/* Timer devices may be used for different purposes. One special purpose is - * to generate modulated outputs for such things as motor control. If - * CONFIG_STM32F0L0G0_TIMn is defined then the CONFIG_STM32F0L0G0_TIMn_PWM - * must also be defined to indicate that timer "n" is intended to be used for - * pulsed output signal generation. - */ - -#ifndef CONFIG_STM32F0L0G0_TIM1 -# undef CONFIG_STM32F0L0G0_TIM1_PWM -#endif -#ifndef CONFIG_STM32F0L0G0_TIM2 -# undef CONFIG_STM32F0L0G0_TIM2_PWM -#endif -#ifndef CONFIG_STM32F0L0G0_TIM3 -# undef CONFIG_STM32F0L0G0_TIM3_PWM -#endif -#ifndef CONFIG_STM32F0L0G0_TIM14 -# undef CONFIG_STM32F0L0G0_TIM14_PWM -#endif -#ifndef CONFIG_STM32F0L0G0_TIM15 -# undef CONFIG_STM32F0L0G0_TIM15_PWM -#endif -#ifndef CONFIG_STM32F0L0G0_TIM16 -# undef CONFIG_STM32F0L0G0_TIM16_PWM -#endif -#ifndef CONFIG_STM32F0L0G0_TIM17 -# undef CONFIG_STM32F0L0G0_TIM17_PWM -#endif - -/* The basic timers (timer 6 and 7) - * are not capable of generating output pulses - */ - -#undef CONFIG_STM32F0L0G0_TIM6_PWM -#undef CONFIG_STM32F0L0G0_TIM7_PWM - -/* Check if PWM support for any channel is enabled. */ - -#if defined(CONFIG_STM32F0L0G0_TIM1_PWM) || defined(CONFIG_STM32F0L0G0_TIM2_PWM) || \ - defined(CONFIG_STM32F0L0G0_TIM3_PWM) || defined(CONFIG_STM32F0L0G0_TIM14_PWM) || \ - defined(CONFIG_STM32F0L0G0_TIM15_PWM) || defined(CONFIG_STM32F0L0G0_TIM16_PWM) || \ - defined(CONFIG_STM32F0L0G0_TIM17_PWM) - -#ifdef CONFIG_STM32F0L0G0_PWM_MULTICHAN - -#ifdef CONFIG_STM32F0L0G0_TIM1_CHANNEL1 -# ifdef CONFIG_STM32F0L0G0_TIM1_CH1OUT -# define PWM_TIM1_CH1CFG GPIO_TIM1_CH1OUT -# else -# define PWM_TIM1_CH1CFG 0 -# endif -# ifdef CONFIG_STM32F0L0G0_TIM1_CH1NOUT -# define PWM_TIM1_CH1NCFG GPIO_TIM1_CH1NOUT -# else -# define PWM_TIM1_CH1NCFG 0 -# endif -# define PWM_TIM1_CHANNEL1 1 -#else -# define PWM_TIM1_CHANNEL1 0 -#endif -#ifdef CONFIG_STM32F0L0G0_TIM1_CHANNEL2 -# ifdef CONFIG_STM32F0L0G0_TIM1_CH2OUT -# define PWM_TIM1_CH2CFG GPIO_TIM1_CH2OUT -# else -# define PWM_TIM1_CH2CFG 0 -# endif -# ifdef CONFIG_STM32F0L0G0_TIM1_CH2NOUT -# define PWM_TIM1_CH2NCFG GPIO_TIM1_CH2NOUT -# else -# define PWM_TIM1_CH2NCFG 0 -# endif -# define PWM_TIM1_CHANNEL2 1 -#else -# define PWM_TIM1_CHANNEL2 0 -#endif -#ifdef CONFIG_STM32F0L0G0_TIM1_CHANNEL3 -# ifdef CONFIG_STM32F0L0G0_TIM1_CH3OUT -# define PWM_TIM1_CH3CFG GPIO_TIM1_CH3OUT -# else -# define PWM_TIM1_CH3CFG 0 -# endif -# ifdef CONFIG_STM32F0L0G0_TIM1_CH3NOUT -# define PWM_TIM1_CH3NCFG GPIO_TIM1_CH3NOUT -# else -# define PWM_TIM1_CH3NCFG 0 -# endif -# define PWM_TIM1_CHANNEL3 1 -#else -# define PWM_TIM1_CHANNEL3 0 -#endif -#ifdef CONFIG_STM32F0L0G0_TIM1_CHANNEL4 -# ifdef CONFIG_STM32F0L0G0_TIM1_CH4OUT -# define PWM_TIM1_CH4CFG GPIO_TIM1_CH4OUT -# else -# define PWM_TIM1_CH4CFG 0 -# endif -# define PWM_TIM1_CHANNEL4 1 -#else -# define PWM_TIM1_CHANNEL4 0 -#endif -#define PWM_TIM1_NCHANNELS (PWM_TIM1_CHANNEL1 + PWM_TIM1_CHANNEL2 + \ - PWM_TIM1_CHANNEL3 + PWM_TIM1_CHANNEL4) - -#ifdef CONFIG_STM32F0L0G0_TIM2_CHANNEL1 -# ifdef CONFIG_STM32F0L0G0_TIM2_CH1OUT -# define PWM_TIM2_CH1CFG GPIO_TIM2_CH1OUT -# else -# define PWM_TIM2_CH1CFG 0 -# endif -# define PWM_TIM2_CHANNEL1 1 -#else -# define PWM_TIM2_CHANNEL1 0 -#endif -#ifdef CONFIG_STM32F0L0G0_TIM2_CHANNEL2 -# ifdef CONFIG_STM32F0L0G0_TIM2_CH2OUT -# define PWM_TIM2_CH2CFG GPIO_TIM2_CH2OUT -# else -# define PWM_TIM2_CH2CFG 0 -# endif -# define PWM_TIM2_CHANNEL2 1 -#else -# define PWM_TIM2_CHANNEL2 0 -#endif -#ifdef CONFIG_STM32F0L0G0_TIM2_CHANNEL3 -# ifdef CONFIG_STM32F0L0G0_TIM2_CH3OUT -# define PWM_TIM2_CH3CFG GPIO_TIM2_CH3OUT -# else -# define PWM_TIM2_CH3CFG 0 -# endif -# define PWM_TIM2_CHANNEL3 1 -#else -# define PWM_TIM2_CHANNEL3 0 -#endif -#ifdef CONFIG_STM32F0L0G0_TIM2_CHANNEL4 -# ifdef CONFIG_STM32F0L0G0_TIM2_CH4OUT -# define PWM_TIM2_CH4CFG GPIO_TIM2_CH4OUT -# else -# define PWM_TIM2_CH4CFG 0 -# endif -# define PWM_TIM2_CHANNEL4 1 -#else -# define PWM_TIM2_CHANNEL4 0 -#endif -#define PWM_TIM2_NCHANNELS (PWM_TIM2_CHANNEL1 + PWM_TIM2_CHANNEL2 + \ - PWM_TIM2_CHANNEL3 + PWM_TIM2_CHANNEL4) - -#ifdef CONFIG_STM32F0L0G0_TIM3_CHANNEL1 -# ifdef CONFIG_STM32F0L0G0_TIM3_CH1OUT -# define PWM_TIM3_CH1CFG GPIO_TIM3_CH1OUT -# else -# define PWM_TIM3_CH1CFG 0 -# endif -# define PWM_TIM3_CHANNEL1 1 -#else -# define PWM_TIM3_CHANNEL1 0 -#endif -#ifdef CONFIG_STM32F0L0G0_TIM3_CHANNEL2 -# ifdef CONFIG_STM32F0L0G0_TIM3_CH2OUT -# define PWM_TIM3_CH2CFG GPIO_TIM3_CH2OUT -# else -# define PWM_TIM3_CH2CFG 0 -# endif -# define PWM_TIM3_CHANNEL2 1 -#else -# define PWM_TIM3_CHANNEL2 0 -#endif -#ifdef CONFIG_STM32F0L0G0_TIM3_CHANNEL3 -# ifdef CONFIG_STM32F0L0G0_TIM3_CH3OUT -# define PWM_TIM3_CH3CFG GPIO_TIM3_CH3OUT -# else -# define PWM_TIM3_CH3CFG 0 -# endif -# define PWM_TIM3_CHANNEL3 1 -#else -# define PWM_TIM3_CHANNEL3 0 -#endif -#ifdef CONFIG_STM32F0L0G0_TIM3_CHANNEL4 -# ifdef CONFIG_STM32F0L0G0_TIM3_CH4OUT -# define PWM_TIM3_CH4CFG GPIO_TIM3_CH4OUT -# else -# define PWM_TIM3_CH4CFG 0 -# endif -# define PWM_TIM3_CHANNEL4 1 -#else -# define PWM_TIM3_CHANNEL4 0 -#endif -#define PWM_TIM3_NCHANNELS (PWM_TIM3_CHANNEL1 + PWM_TIM3_CHANNEL2 + \ - PWM_TIM3_CHANNEL3 + PWM_TIM3_CHANNEL4) - -#ifdef CONFIG_STM32F0L0G0_TIM14_CHANNEL1 -# ifdef CONFIG_STM32F0L0G0_TIM14_CH1OUT -# define PWM_TIM14_CH1CFG GPIO_TIM14_CH1OUT -# else -# define PWM_TIM14_CH1CFG 0 -# endif -# ifdef CONFIG_STM32F0L0G0_TIM14_CH1NOUT -# define PWM_TIM14_CH1NCFG GPIO_TIM14_CH1NOUT -# else -# define PWM_TIM14_CH1NCFG 0 -# endif -# define PWM_TIM14_CHANNEL1 1 -#else -# define PWM_TIM14_CHANNEL1 0 -#endif -#define PWM_TIM14_NCHANNELS PWM_TIM14_CHANNEL1 - -#ifdef CONFIG_STM32F0L0G0_TIM15_CHANNEL1 -# ifdef CONFIG_STM32F0L0G0_TIM15_CH1OUT -# define PWM_TIM15_CH1CFG GPIO_TIM15_CH1OUT -# else -# define PWM_TIM15_CH1CFG 0 -# endif -# ifdef CONFIG_STM32F0L0G0_TIM15_CH1NOUT -# define PWM_TIM15_CH1NCFG GPIO_TIM15_CH1NOUT -# else -# define PWM_TIM15_CH1NCFG 0 -# endif -# define PWM_TIM15_CHANNEL1 1 -#else -# define PWM_TIM15_CHANNEL1 0 -#endif -#ifdef CONFIG_STM32F0L0G0_TIM15_CHANNEL2 -# ifdef CONFIG_STM32F0L0G0_TIM15_CH2OUT -# define PWM_TIM15_CH2CFG GPIO_TIM15_CH2OUT -# else -# define PWM_TIM15_CH2CFG 0 -# endif -# define PWM_TIM15_CHANNEL2 1 -#else -# define PWM_TIM15_CHANNEL2 0 -#endif -#define PWM_TIM15_NCHANNELS (PWM_TIM15_CHANNEL1 + PWM_TIM15_CHANNEL2) - -#ifdef CONFIG_STM32F0L0G0_TIM16_CHANNEL1 -# ifdef CONFIG_STM32F0L0G0_TIM16_CH1OUT -# define PWM_TIM16_CH1CFG GPIO_TIM16_CH1OUT -# else -# define PWM_TIM16_CH1CFG 0 -# endif -# ifdef CONFIG_STM32F0L0G0_TIM16_CH1NOUT -# define PWM_TIM16_CH1NCFG GPIO_TIM16_CH1NOUT -# else -# define PWM_TIM16_CH1NCFG 0 -# endif -# define PWM_TIM16_CHANNEL1 1 -#else -# define PWM_TIM16_CHANNEL1 0 -#endif -#define PWM_TIM16_NCHANNELS PWM_TIM16_CHANNEL1 - -#ifdef CONFIG_STM32F0L0G0_TIM17_CHANNEL1 -# ifdef CONFIG_STM32F0L0G0_TIM17_CH1OUT -# define PWM_TIM17_CH1CFG GPIO_TIM17_CH1OUT -# else -# define PWM_TIM17_CH1CFG 0 -# endif -# ifdef CONFIG_STM32F0L0G0_TIM17_CH1NOUT -# define PWM_TIM17_CH1NCFG GPIO_TIM17_CH1NOUT -# else -# define PWM_TIM17_CH1NCFG 0 -# endif -# define PWM_TIM17_CHANNEL1 1 -#else -# define PWM_TIM17_CHANNEL1 0 -#endif -#define PWM_TIM17_NCHANNELS PWM_TIM17_CHANNEL1 - -#define PWM_NCHANNELS MAX(PWM_TIM1_NCHANNELS, \ - MAX(PWM_TIM2_NCHANNELS, \ - MAX(PWM_TIM3_NCHANNELS, \ - MAX(PWM_TIM14_NCHANNELS, \ - MAX(PWM_TIM15_NCHANNELS, \ - MAX(PWM_TIM16_NCHANNELS, \ - PWM_TIM17_NCHANNELS)))))) - -#else /* !CONFIG_STM32F0L0G0_PWM_MULTICHAN */ - -/* For each timer that is enabled for PWM usage, we need the following - * additional configuration settings: - * - * CONFIG_STM32F0L0G0_TIMx_CHANNEL - Specifies the timer output channel - * {1,..,4} - * PWM_TIMx_CHn - One of the values defined in chip/stm32*_pinmap.h. - * In the case where there are multiple pin selections, the correct - * setting must be provided in the arch/board/board.h file. - * - * NOTE: - * The STM32 timers are each capable of generating different signals on - * each of the four channels with different duty cycles. That capability - * is not supported by this driver: Only one output channel per timer. - */ - -#ifdef CONFIG_STM32F0L0G0_TIM1_PWM -# if !defined(CONFIG_STM32F0L0G0_TIM1_CHANNEL) -# error "CONFIG_STM32F0L0G0_TIM1_CHANNEL must be provided" -# elif CONFIG_STM32F0L0G0_TIM1_CHANNEL == 1 -# define CONFIG_STM32F0L0G0_TIM1_CHANNEL1 1 -# define CONFIG_STM32F0L0G0_TIM1_CH1MODE CONFIG_STM32F0L0G0_TIM1_CHMODE -# define PWM_TIM1_CH1CFG GPIO_TIM1_CH1OUT -# define PWM_TIM1_CH1NCFG 0 -# elif CONFIG_STM32F0L0G0_TIM1_CHANNEL == 2 -# define CONFIG_STM32F0L0G0_TIM1_CHANNEL2 1 -# define CONFIG_STM32F0L0G0_TIM1_CH2MODE CONFIG_STM32F0L0G0_TIM1_CHMODE -# define PWM_TIM1_CH2CFG GPIO_TIM1_CH2OUT -# define PWM_TIM1_CH2NCFG 0 -# elif CONFIG_STM32F0L0G0_TIM1_CHANNEL == 3 -# define CONFIG_STM32F0L0G0_TIM1_CHANNEL3 1 -# define CONFIG_STM32F0L0G0_TIM1_CH3MODE CONFIG_STM32F0L0G0_TIM1_CHMODE -# define PWM_TIM1_CH3CFG GPIO_TIM1_CH3OUT -# define PWM_TIM1_CH3NCFG 0 -# elif CONFIG_STM32F0L0G0_TIM1_CHANNEL == 4 -# define CONFIG_STM32F0L0G0_TIM1_CHANNEL4 1 -# define CONFIG_STM32F0L0G0_TIM1_CH4MODE CONFIG_STM32F0L0G0_TIM1_CHMODE -# define PWM_TIM1_CH4CFG GPIO_TIM1_CH4OUT -# else -# error "Unsupported value of CONFIG_STM32F0L0G0_TIM1_CHANNEL" -# endif -# define PWM_TIM1_NCHANNELS 1 -#endif - -#ifdef CONFIG_STM32F0L0G0_TIM2_PWM -# if !defined(CONFIG_STM32F0L0G0_TIM2_CHANNEL) -# error "CONFIG_STM32F0L0G0_TIM2_CHANNEL must be provided" -# elif CONFIG_STM32F0L0G0_TIM2_CHANNEL == 1 -# define CONFIG_STM32F0L0G0_TIM2_CHANNEL1 1 -# define CONFIG_STM32F0L0G0_TIM2_CH1MODE CONFIG_STM32F0L0G0_TIM2_CHMODE -# define PWM_TIM2_CH1CFG GPIO_TIM2_CH1OUT -# elif CONFIG_STM32F0L0G0_TIM2_CHANNEL == 2 -# define CONFIG_STM32F0L0G0_TIM2_CHANNEL2 1 -# define CONFIG_STM32F0L0G0_TIM2_CH2MODE CONFIG_STM32F0L0G0_TIM2_CHMODE -# define PWM_TIM2_CH2CFG GPIO_TIM2_CH2OUT -# elif CONFIG_STM32F0L0G0_TIM2_CHANNEL == 3 -# define CONFIG_STM32F0L0G0_TIM2_CHANNEL3 1 -# define CONFIG_STM32F0L0G0_TIM2_CH3MODE CONFIG_STM32F0L0G0_TIM2_CHMODE -# define PWM_TIM2_CH3CFG GPIO_TIM2_CH3OUT -# elif CONFIG_STM32F0L0G0_TIM2_CHANNEL == 4 -# define CONFIG_STM32F0L0G0_TIM2_CHANNEL4 1 -# define CONFIG_STM32F0L0G0_TIM2_CH4MODE CONFIG_STM32F0L0G0_TIM2_CHMODE -# define PWM_TIM2_CH4CFG GPIO_TIM2_CH4OUT -# else -# error "Unsupported value of CONFIG_STM32F0L0G0_TIM2_CHANNEL" -# endif -# define PWM_TIM2_NCHANNELS 1 -#endif - -#ifdef CONFIG_STM32F0L0G0_TIM3_PWM -# if !defined(CONFIG_STM32F0L0G0_TIM3_CHANNEL) -# error "CONFIG_STM32F0L0G0_TIM3_CHANNEL must be provided" -# elif CONFIG_STM32F0L0G0_TIM3_CHANNEL == 1 -# define CONFIG_STM32F0L0G0_TIM3_CHANNEL1 1 -# define CONFIG_STM32F0L0G0_TIM3_CH1MODE CONFIG_STM32F0L0G0_TIM3_CHMODE -# define PWM_TIM3_CH1CFG GPIO_TIM3_CH1OUT -# elif CONFIG_STM32F0L0G0_TIM3_CHANNEL == 2 -# define CONFIG_STM32F0L0G0_TIM3_CHANNEL2 1 -# define CONFIG_STM32F0L0G0_TIM3_CH2MODE CONFIG_STM32F0L0G0_TIM3_CHMODE -# define PWM_TIM3_CH2CFG GPIO_TIM3_CH2OUT -# elif CONFIG_STM32F0L0G0_TIM3_CHANNEL == 3 -# define CONFIG_STM32F0L0G0_TIM3_CHANNEL3 1 -# define CONFIG_STM32F0L0G0_TIM3_CH3MODE CONFIG_STM32F0L0G0_TIM3_CHMODE -# define PWM_TIM3_CH3CFG GPIO_TIM3_CH3OUT -# elif CONFIG_STM32F0L0G0_TIM3_CHANNEL == 4 -# define CONFIG_STM32F0L0G0_TIM3_CHANNEL4 1 -# define CONFIG_STM32F0L0G0_TIM3_CH4MODE CONFIG_STM32F0L0G0_TIM3_CHMODE -# define PWM_TIM3_CH4CFG GPIO_TIM3_CH4OUT -# else -# error "Unsupported value of CONFIG_STM32F0L0G0_TIM3_CHANNEL" -# endif -# define PWM_TIM3_NCHANNELS 1 -#endif - -#ifdef CONFIG_STM32F0L0G0_TIM14_PWM -# if !defined(CONFIG_STM32F0L0G0_TIM14_CHANNEL) -# error "CONFIG_STM32F0L0G0_TIM14_CHANNEL must be provided" -# elif CONFIG_STM32F0L0G0_TIM14_CHANNEL == 1 -# define CONFIG_STM32F0L0G0_TIM14_CHANNEL1 1 -# define CONFIG_STM32F0L0G0_TIM14_CH1MODE CONFIG_STM32F0L0G0_TIM14_CHMODE -# define PWM_TIM14_CH1CFG GPIO_TIM14_CH1OUT -# define PWM_TIM14_CH1NCFG 0 -# else -# error "Unsupported value of CONFIG_STM32F0L0G0_TIM14_CHANNEL" -# endif -# define PWM_TIM14_NCHANNELS 1 -#endif - -#ifdef CONFIG_STM32F0L0G0_TIM15_PWM -# if !defined(CONFIG_STM32F0L0G0_TIM15_CHANNEL) -# error "CONFIG_STM32F0L0G0_TIM15_CHANNEL must be provided" -# elif CONFIG_STM32F0L0G0_TIM15_CHANNEL == 1 -# define CONFIG_STM32F0L0G0_TIM15_CHANNEL1 1 -# define CONFIG_STM32F0L0G0_TIM15_CH1MODE CONFIG_STM32F0L0G0_TIM15_CHMODE -# define PWM_TIM15_CH1CFG GPIO_TIM15_CH1OUT -# define PWM_TIM15_CH1NCFG 0 -# elif CONFIG_STM32F0L0G0_TIM15_CHANNEL == 2 -# define CONFIG_STM32F0L0G0_TIM15_CHANNEL2 1 -# define CONFIG_STM32F0L0G0_TIM15_CH2MODE CONFIG_STM32F0L0G0_TIM15_CHMODE -# define PWM_TIM15_CH2CFG GPIO_TIM15_CH2OUT -# else -# error "Unsupported value of CONFIG_STM32F0L0G0_TIM15_CHANNEL" -# endif -# define PWM_TIM15_NCHANNELS 1 -#endif - -#ifdef CONFIG_STM32F0L0G0_TIM16_PWM -# if !defined(CONFIG_STM32F0L0G0_TIM16_CHANNEL) -# error "CONFIG_STM32F0L0G0_TIM16_CHANNEL must be provided" -# elif CONFIG_STM32F0L0G0_TIM16_CHANNEL == 1 -# define CONFIG_STM32F0L0G0_TIM16_CHANNEL1 1 -# define CONFIG_STM32F0L0G0_TIM16_CH1MODE CONFIG_STM32F0L0G0_TIM16_CHMODE -# define PWM_TIM16_CH1CFG GPIO_TIM16_CH1OUT -# define PWM_TIM16_CH1NCFG 0 -# else -# error "Unsupported value of CONFIG_STM32F0L0G0_TIM16_CHANNEL" -# endif -# define PWM_TIM16_NCHANNELS 1 -#endif - -#ifdef CONFIG_STM32F0L0G0_TIM17_PWM -# if !defined(CONFIG_STM32F0L0G0_TIM17_CHANNEL) -# error "CONFIG_STM32F0L0G0_TIM17_CHANNEL must be provided" -# elif CONFIG_STM32F0L0G0_TIM17_CHANNEL == 1 -# define CONFIG_STM32F0L0G0_TIM17_CHANNEL1 1 -# define CONFIG_STM32F0L0G0_TIM17_CH1MODE CONFIG_STM32F0L0G0_TIM17_CHMODE -# define PWM_TIM17_CH1CFG GPIO_TIM17_CH1OUT -# define PWM_TIM17_CH1NCFG 0 -# else -# error "Unsupported value of CONFIG_STM32F0L0G0_TIM17_CHANNEL" -# endif -# define PWM_TIM17_NCHANNELS 1 -#endif - -#define PWM_NCHANNELS 1 - -#endif /* CONFIG_STM32F0L0G0_PWM_MULTICHAN */ - -/* Complementary outputs support */ - -#if defined(CONFIG_STM32F0L0G0_TIM1_CH1NOUT) || defined(CONFIG_STM32F0L0G0_TIM1_CH2NOUT) || \ - defined(CONFIG_STM32F0L0G0_TIM1_CH3NOUT) -# define HAVE_TIM1_COMPLEMENTARY -#endif -#if defined(CONFIG_STM32F0L0G0_TIM15_CH1NOUT) -# define HAVE_TIM15_COMPLEMENTARY -#endif -#if defined(CONFIG_STM32F0L0G0_TIM16_CH1NOUT) -# define HAVE_TIM16_COMPLEMENTARY -#endif -#if defined(CONFIG_STM32F0L0G0_TIM17_CH1NOUT) -# define HAVE_TIM17_COMPLEMENTARY -#endif -#if defined(HAVE_TIM1_COMPLEMENTARY) || defined(HAVE_TIM8_COMPLEMENTARY) || \ - defined(HAVE_TIM15_COMPLEMENTARY) || defined(HAVE_TIM16_COMPLEMENTARY) || \ - defined(HAVE_TIM17_COMPLEMENTARY) -# define HAVE_PWM_COMPLEMENTARY -#endif - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -#ifndef __ASSEMBLY__ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Public Functions Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_pwminitialize - * - * Description: - * Initialize one timer for use with the upper_level PWM driver. - * - * Input Parameters: - * timer - A number identifying the timer use. The number of valid timer - * IDs varies with the STM32 MCU and MCU family but is somewhere in - * the range of {1,..,17}. - * - * Returned Value: - * On success, a pointer to the STM32 lower half PWM driver is returned. - * NULL is returned on any failure. - * - ****************************************************************************/ - -struct pwm_lowerhalf_s *stm32_pwminitialize(int timer); - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ - -#endif /* CONFIG_STM32F0L0G0_TIMx_PWM */ - -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_STM32_PWM_H */ diff --git a/arch/arm/src/stm32f0l0g0/stm32_pwr.c b/arch/arm/src/stm32f0l0g0/stm32_pwr.c deleted file mode 100644 index 76f6b07bf9cd4..0000000000000 --- a/arch/arm/src/stm32f0l0g0/stm32_pwr.c +++ /dev/null @@ -1,42 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_pwr.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include "chip.h" - -/* This file is only a thin shell that includes the proper PWR implementation - * according to the selected MCU family. - */ - -#if defined(CONFIG_STM32F0L0G0_STM32G0) -# include "stm32g0_pwr.c" -#elif defined(CONFIG_STM32F0L0G0_STM32F0) || defined(CONFIG_STM32F0L0G0_STM32L0) -# include "stm32f0l0_pwr.c" -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ diff --git a/arch/arm/src/stm32f0l0g0/stm32_pwr.h b/arch/arm/src/stm32f0l0g0/stm32_pwr.h deleted file mode 100644 index 21673d02c3ea2..0000000000000 --- a/arch/arm/src/stm32f0l0g0/stm32_pwr.h +++ /dev/null @@ -1,228 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_pwr.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_STM32_PWR_H -#define __ARCH_ARM_SRC_STM32F0L0G0_STM32_PWR_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include "chip.h" -#include "hardware/stm32_pwr.h" - -#ifdef CONFIG_STM32F0L0G0_PWR - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#ifndef __ASSEMBLY__ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -/* Identify MCU-specific wakeup pin. Different STM32 parts support differing - * numbers of wakeup pins. - */ - -enum stm32_pwr_wupin_e -{ - PWR_WUPIN_1 = 0, /* Wake-up pin 1 (all parts) */ - PWR_WUPIN_2, /* Wake-up pin 2 */ - PWR_WUPIN_3 /* Wake-up pin 3 */ -}; - -/**************************************************************************** - * Public Functions Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_pwr_initbkp - * - * Description: - * Insures the referenced count access to the backup domain (RTC registers, - * RTC backup data registers and backup SRAM is consistent with the HW - * state without relying on a variable. - * - * NOTE: This function should only be called by SoC Start up code. - * - * Input Parameters: - * writable - set the initial state of the enable and the - * bkp_writable_counter - * - * Returned Value: - * None - * - ****************************************************************************/ - -void stm32_pwr_initbkp(bool writable); - -/**************************************************************************** - * Name: stm32_pwr_enablebkp - * - * Description: - * Enables access to the backup domain (RTC registers, RTC backup data - * registers and backup SRAM). - * - * NOTE: - * Reference counting is used in order to supported nested calls to this - * function. As a consequence, every call to stm32_pwr_enablebkp(true) - * must be followed by a matching call to stm32_pwr_enablebkp(false). - * - * Input Parameters: - * writable - True: enable ability to write to backup domain registers - * - * Returned Value: - * None - * - ****************************************************************************/ - -void stm32_pwr_enablebkp(bool writable); - -/**************************************************************************** - * Name: stm32_pwr_enablewkup - * - * Description: - * Enables the WKUP pin. - * - * Input Parameters: - * wupin - Selects the WKUP pin to enable/disable - * wupon - state to set it to - * - * Returned Value: - * Zero (OK) is returned on success; A negated errno value is returned on - * any failure. The only cause of failure is if the selected MCU does not - * support the requested wakeup pin. - * - ****************************************************************************/ - -int stm32_pwr_enablewkup(enum stm32_pwr_wupin_e wupin, bool wupon); - -/**************************************************************************** - * Name: stm32_pwr_getsbf - * - * Description: - * Return the standby flag. - * - ****************************************************************************/ - -bool stm32_pwr_getsbf(void); - -/**************************************************************************** - * Name: stm32_pwr_getwuf - * - * Description: - * Return the wakeup flag. - * - ****************************************************************************/ - -bool stm32_pwr_getwuf(void); - -/**************************************************************************** - * Name: stm32_pwr_setvos - * - * Description: - * Set voltage scaling for EnergyLite devices. - * - * Input Parameters: - * vos - Properly aligned voltage scaling select bits for the PWR_CR - * register. - * - * Returned Value: - * None - * - * Assumptions: - * At present, this function is called only from initialization logic. If - * used for any other purpose that protection to assure that its operation - * is atomic will be required. - * - ****************************************************************************/ - -#if defined(CONFIG_STM32F0L0G0_ENERGYLITE) || defined(CONFIG_STM32F0L0G0_STM32G0) -void stm32_pwr_setvos(uint16_t vos); -#endif /* CONFIG_STM32F0L0G0_ENERGYLITE || CONFIG_STM32F0L0G0_STM32G0 */ - -/**************************************************************************** - * Name: stm32_pwr_setpvd - * - * Description: - * Sets power voltage detector for EnergyLite devices. - * - * Input Parameters: - * pls - PVD level - * - * Returned Value: - * None - * - * Assumptions: - * At present, this function is called only from initialization logic. - * - ****************************************************************************/ - -#if defined(CONFIG_STM32F0L0G0_ENERGYLITE) -void stm32_pwr_setpvd(uint16_t pls); - -/**************************************************************************** - * Name: stm32_pwr_enablepvd - * - * Description: - * Enable the Programmable Voltage Detector - * - ****************************************************************************/ - -void stm32_pwr_enablepvd(void); - -/**************************************************************************** - * Name: stm32_pwr_disablepvd - * - * Description: - * Disable the Programmable Voltage Detector - * - ****************************************************************************/ - -void stm32_pwr_disablepvd(void); - -#endif /* CONFIG_STM32F0L0G0_ENERGYLITE */ - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ -#endif /* CONFIG_STM32F0L0G0_PWR */ -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_STM32_PWR_H */ diff --git a/arch/arm/src/stm32f0l0g0/stm32_qencoder.c b/arch/arm/src/stm32f0l0g0/stm32_qencoder.c deleted file mode 100644 index 8f09d5596fb15..0000000000000 --- a/arch/arm/src/stm32f0l0g0/stm32_qencoder.c +++ /dev/null @@ -1,1254 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_qencoder.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include - -#include -#include -#include -#include - -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32.h" -#include "stm32_gpio.h" -#include "stm32_tim.h" -#include "stm32_qencoder.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Timers *******************************************************************/ - -#ifndef CONFIG_STM32F0L0G0_QENCODER_DISABLE_EXTEND16BTIMERS -# undef HAVE_32BIT_TIMERS -# undef HAVE_16BIT_TIMERS - -/* If TIM2 is enabled and is 32-bit, then we have 32-bit timers */ - -# if defined(CONFIG_STM32F0L0G0_TIM2_QE) && defined(HAVE_TIM2_32BIT) -# define HAVE_32BIT_TIMERS 1 -# endif - -/* If TIM1, TIM2 (16-bit variant), TIM3, or TIM4 are enabled, we have - * 16-bit timers - */ - -# if defined(CONFIG_STM32F0L0G0_TIM1_QE) || defined(CONFIG_STM32F0L0G0_TIM3_QE) || \ - defined(CONFIG_STM32F0L0G0_TIM4_QE) || \ - (defined(CONFIG_STM32F0L0G0_TIM2_QE) && defined(HAVE_TIM2_16BIT)) -# define HAVE_16BIT_TIMERS 1 -# endif - -/* The width in bits of each timer */ - -# define TIM1_BITWIDTH 16 -# ifdef HAVE_TIM2_16BIT -# define TIM2_BITWIDTH 16 -# else -# define TIM2_BITWIDTH 32 -# endif -# define TIM3_BITWIDTH 16 -# define TIM4_BITWIDTH 16 - -/* Do we need to support mixed 16- and 32-bit timers */ - -# undef HAVE_MIXEDWIDTH_TIMERS -# if defined(HAVE_16BIT_TIMERS) && defined(HAVE_32BIT_TIMERS) -# define HAVE_MIXEDWIDTH_TIMERS 1 -# endif -#endif - -/* Input filter *************************************************************/ - -#ifdef CONFIG_STM32F0L0G0_QENCODER_FILTER -# if defined(CONFIG_STM32F0L0G0_QENCODER_SAMPLE_FDTS) -# if defined(CONFIG_STM32F0L0G0_QENCODER_SAMPLE_EVENT_1) -# define STM32F0L0G0_QENCODER_ICF GTIM_CCMR_ICF_NOFILT -# endif -# elif defined(CONFIG_STM32F0L0G0_QENCODER_SAMPLE_CKINT) -# if defined(CONFIG_STM32F0L0G0_QENCODER_SAMPLE_EVENT_2) -# define STM32F0L0G0_QENCODER_ICF GTIM_CCMR_ICF_FCKINT2 -# elif defined(CONFIG_STM32F0L0G0_QENCODER_SAMPLE_EVENT_4) -# define STM32F0L0G0_QENCODER_ICF GTIM_CCMR_ICF_FCKINT4 -# elif defined(CONFIG_STM32F0L0G0_QENCODER_SAMPLE_EVENT_8) -# define STM32F0L0G0_QENCODER_ICF GTIM_CCMR_ICF_FCKINT8 -# endif -# elif defined(CONFIG_STM32F0L0G0_QENCODER_SAMPLE_FDTS_2) -# if defined(CONFIG_STM32F0L0G0_QENCODER_SAMPLE_EVENT_6) -# define STM32F0L0G0_QENCODER_ICF GTIM_CCMR_ICF_FDTSd26 -# elif defined(CONFIG_STM32F0L0G0_QENCODER_SAMPLE_EVENT_8) -# define STM32F0L0G0_QENCODER_ICF GTIM_CCMR_ICF_FDTSd28 -# endif -# elif defined(CONFIG_STM32F0L0G0_QENCODER_SAMPLE_FDTS_4) -# if defined(CONFIG_STM32F0L0G0_QENCODER_SAMPLE_EVENT_6) -# define STM32F0L0G0_QENCODER_ICF GTIM_CCMR_ICF_FDTSd46 -# elif defined(CONFIG_STM32F0L0G0_QENCODER_SAMPLE_EVENT_8) -# define STM32F0L0G0_QENCODER_ICF GTIM_CCMR_ICF_FDTSd48 -# endif -# elif defined(CONFIG_STM32F0L0G0_QENCODER_SAMPLE_FDTS_8) -# if defined(CONFIG_STM32F0L0G0_QENCODER_SAMPLE_EVENT_6) -# define STM32F0L0G0_QENCODER_ICF GTIM_CCMR_ICF_FDTSd86 -# elif defined(CONFIG_STM32F0L0G0_QENCODER_SAMPLE_EVENT_8) -# define STM32F0L0G0_QENCODER_ICF GTIM_CCMR_ICF_FDTSd88 -# endif -# elif defined(CONFIG_STM32F0L0G0_QENCODER_SAMPLE_FDTS_16) -# if defined(CONFIG_STM32F0L0G0_QENCODER_SAMPLE_EVENT_5) -# define STM32F0L0G0_QENCODER_ICF GTIM_CCMR_ICF_FDTSd165 -# elif defined(CONFIG_STM32F0L0G0_QENCODER_SAMPLE_EVENT_6) -# define STM32F0L0G0_QENCODER_ICF GTIM_CCMR_ICF_FDTSd166 -# elif defined(CONFIG_STM32F0L0G0_QENCODER_SAMPLE_EVENT_8) -# define STM32F0L0G0_QENCODER_ICF GTIM_CCMR_ICF_FDTSd168 -# endif -# elif defined(CONFIG_STM32F0L0G0_QENCODER_SAMPLE_FDTS_32) -# if defined(CONFIG_STM32F0L0G0_QENCODER_SAMPLE_EVENT_5) -# define STM32F0L0G0_QENCODER_ICF GTIM_CCMR_ICF_FDTSd325 -# elif defined(CONFIG_STM32F0L0G0_QENCODER_SAMPLE_EVENT_6) -# define STM32F0L0G0_QENCODER_ICF GTIM_CCMR_ICF_FDTSd326 -# elif defined(CONFIG_STM32F0L0G0_QENCODER_SAMPLE_EVENT_8) -# define STM32F0L0G0_QENCODER_ICF GTIM_CCMR_ICF_FDTSd328 -# endif -# endif - -# ifndef STM32F0L0G0_QENCODER_ICF -# warning "Invalid encoder filter combination, filter disabled" -# endif -#endif - -#ifndef STM32F0L0G0_QENCODER_ICF -# define STM32F0L0G0_QENCODER_ICF GTIM_CCMR_ICF_NOFILT -#endif - -#define STM32F0L0G0_GPIO_INPUT_FLOAT (GPIO_INPUT | GPIO_FLOAT) - -/* Debug ********************************************************************/ - -/* Non-standard debug that may be enabled just for testing the quadrature - * encoder - */ - -#ifndef CONFIG_DEBUG_FEATURES -# undef CONFIG_DEBUG_SENSORS -#endif - -#ifdef CONFIG_DEBUG_SENSORS -# ifdef CONFIG_DEBUG_INFO -# define qe_dumpgpio(p,m) stm32_dumpgpio(p,m) -# else -# define qe_dumpgpio(p,m) -# endif -#else -# define qe_dumpgpio(p,m) -#endif - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/* Constant configuration structure that is retained in FLASH */ - -struct stm32_qeconfig_s -{ - uint8_t timid; /* Timer ID {1,2,3,4,5,8} */ - uint8_t irq; /* Timer update IRQ */ -#ifdef HAVE_MIXEDWIDTH_TIMERS - uint8_t width; /* Timer width (16- or 32-bits) */ -#endif - uint32_t ti1cfg; /* TI1 input pin configuration (20-bit encoding) */ - uint32_t ti2cfg; /* TI2 input pin configuration (20-bit encoding) */ - uint32_t base; /* Register base address */ - uint32_t psc; /* Encoder pulses prescaler */ -}; - -/* Overall, RAM-based state structure */ - -struct stm32_lowerhalf_s -{ - /* The first field of this state structure must be a pointer to the lower- - * half callback structure: - */ - - const struct qe_ops_s *ops; - - /* STM32 driver-specific fields: */ - - const struct stm32_qeconfig_s *config; - - bool inuse; /* True: The lower-half driver is in-use */ - -#ifdef CONFIG_STM32F0L0G0_QENCODER_INDEX_PIN - uint32_t index_pin; /* Index pin GPIO */ - bool index_use; /* True: Index pin is configured */ - int32_t index_offset; /* Index pin offset */ -#endif - -#ifndef CONFIG_STM32F0L0G0_QENCODER_DISABLE_EXTEND16BTIMERS - volatile int32_t position; /* The current position offset */ -#endif - spinlock_t lock; /* Spinlock */ -}; - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -/* Helper functions */ - -static uint16_t stm32_getreg16(struct stm32_lowerhalf_s *priv, int offset); -static void stm32_putreg16(struct stm32_lowerhalf_s *priv, int offset, - uint16_t value); -static uint32_t stm32_getreg32(struct stm32_lowerhalf_s *priv, int offset); -static void stm32_putreg32(struct stm32_lowerhalf_s *priv, int offset, - uint32_t value); - -#if defined(CONFIG_DEBUG_SENSORS) && defined(CONFIG_DEBUG_INFO) -static void stm32_dumpregs(struct stm32_lowerhalf_s *priv, - const char *msg); -#else -# define stm32_dumpregs(priv, msg) -#endif - -static struct stm32_lowerhalf_s *stm32_tim2lower(int tim); - -/* Interrupt handling */ - -#ifdef CONFIG_STM32F0L0G0_QENCODER_INDEX_PIN -static int stm32_qe_index_irq(int irq, void *context, void *arg); -#endif - -#ifndef CONFIG_STM32F0L0G0_QENCODER_DISABLE_EXTEND16BTIMERS -static int stm32_interrupt(int irq, void *context, void *arg); -#endif - -/* Lower-half Quadrature Encoder Driver Methods */ - -static int stm32_setup(struct qe_lowerhalf_s *lower); -static int stm32_shutdown(struct qe_lowerhalf_s *lower); -static int stm32_position(struct qe_lowerhalf_s *lower, int32_t *pos); -static int stm32_setposmax(struct qe_lowerhalf_s *lower, uint32_t pos); -static int stm32_reset(struct qe_lowerhalf_s *lower); -static int stm32_setindex(struct qe_lowerhalf_s *lower, uint32_t pos); -static int stm32_ioctl(struct qe_lowerhalf_s *lower, int cmd, - unsigned long arg); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* The lower half callback structure */ - -static const struct qe_ops_s g_qecallbacks = -{ - .setup = stm32_setup, - .shutdown = stm32_shutdown, - .position = stm32_position, - .setposmax = stm32_setposmax, - .reset = stm32_reset, - .setindex = stm32_setindex, - .ioctl = stm32_ioctl, -}; - -/* Per-timer state structures */ - -#ifdef CONFIG_STM32F0L0G0_TIM1_QE -static const struct stm32_qeconfig_s g_tim1config = -{ - .timid = 1, - .irq = STM32_IRQ_TIM1_BRK, -#ifdef HAVE_MIXEDWIDTH_TIMERS - .width = TIM1_BITWIDTH, -#endif - .base = STM32_TIM1_BASE, - .psc = CONFIG_STM32F0L0G0_TIM1_QEPSC, - .ti1cfg = GPIO_TIM1_CH1IN, - .ti2cfg = GPIO_TIM1_CH2IN, -}; - -static struct stm32_lowerhalf_s g_tim1lower = -{ - .ops = &g_qecallbacks, - .config = &g_tim1config, - .inuse = false, - .lock = SP_UNLOCKED, -}; - -#endif - -#ifdef CONFIG_STM32F0L0G0_TIM2_QE -static const struct stm32_qeconfig_s g_tim2config = -{ - .timid = 2, - .irq = STM32_IRQ_TIM2, -#ifdef HAVE_MIXEDWIDTH_TIMERS - .width = TIM2_BITWIDTH, -#endif - .base = STM32_TIM2_BASE, - .psc = CONFIG_STM32F0L0G0_TIM2_QEPSC, - .ti1cfg = GPIO_TIM2_CH1IN, - .ti2cfg = GPIO_TIM2_CH2IN, -}; - -static struct stm32_lowerhalf_s g_tim2lower = -{ - .ops = &g_qecallbacks, - .config = &g_tim2config, - .inuse = false, - .lock = SP_UNLOCKED, -}; - -#endif - -#ifdef CONFIG_STM32F0L0G0_TIM3_QE -static const struct stm32_qeconfig_s g_tim3config = -{ - .timid = 3, - .irq = STM32_IRQ_TIM3, -#ifdef HAVE_MIXEDWIDTH_TIMERS - .width = TIM3_BITWIDTH, -#endif - .base = STM32_TIM3_BASE, - .psc = CONFIG_STM32F0L0G0_TIM3_QEPSC, - .ti1cfg = GPIO_TIM3_CH1IN, - .ti2cfg = GPIO_TIM3_CH2IN, -}; - -static struct stm32_lowerhalf_s g_tim3lower = -{ - .ops = &g_qecallbacks, - .config = &g_tim3config, - .inuse = false, - .lock = SP_UNLOCKED, -}; - -#endif - -#ifdef CONFIG_STM32F0L0G0_TIM4_QE -static const struct stm32_qeconfig_s g_tim4config = -{ - .timid = 4, - .irq = STM32_IRQ_TIM4, -#ifdef HAVE_MIXEDWIDTH_TIMERS - .width = TIM4_BITWIDTH, -#endif - .base = STM32_TIM4_BASE, - .psc = CONFIG_STM32F0L0G0_TIM4_QEPSC, - .ti1cfg = GPIO_TIM4_CH1IN, - .ti2cfg = GPIO_TIM4_CH2IN, -}; - -static struct stm32_lowerhalf_s g_tim4lower = -{ - .ops = &g_qecallbacks, - .config = &g_tim4config, - .inuse = false, - .lock = SP_UNLOCKED, -}; - -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_getreg16 - * - * Description: - * Read the value of a 16-bit timer register. - * - * Input Parameters: - * priv - A reference to the lower half status - * offset - The offset to the register to read - * - * Returned Value: - * The current contents of the specified register - * - ****************************************************************************/ - -static uint16_t stm32_getreg16(struct stm32_lowerhalf_s *priv, int offset) -{ - return getreg16(priv->config->base + offset); -} - -/**************************************************************************** - * Name: stm32_putreg16 - * - * Description: - * Write a value to a 16-bit timer register. - * - * Input Parameters: - * priv - A reference to the lower half status - * offset - The offset to the register to read - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void stm32_putreg16(struct stm32_lowerhalf_s *priv, int offset, - uint16_t value) -{ - putreg16(value, priv->config->base + offset); -} - -/**************************************************************************** - * Name: stm32_getreg32 - * - * Description: - * Read the value of a 32-bit timer register. - * This applies only for the STM32 F4 32-bit registers (CNT, ARR, CRR1-4) - * in the 32-bit timers TIM2-5 (but works OK with the 16-bit TIM1,8 - * and F1 registers as well). - * - * Input Parameters: - * priv - A reference to the lower half status - * offset - The offset to the register to read - * - * Returned Value: - * The current contents of the specified register - * - ****************************************************************************/ - -static uint32_t stm32_getreg32(struct stm32_lowerhalf_s *priv, int offset) -{ - return getreg32(priv->config->base + offset); -} - -/**************************************************************************** - * Name: stm32_putreg16 - * - * Description: - * Write a value to a 32-bit timer register. - * This applies only for the STM32 F4 32-bit registers (CNT, ARR, CRR1-4) - * in the 32-bit timers TIM2-5 (but works OK with the 16-bit TIM1,8 - * and F1 registers). - * - * Input Parameters: - * priv - A reference to the lower half status - * offset - The offset to the register to read - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void stm32_putreg32(struct stm32_lowerhalf_s *priv, int offset, - uint32_t value) -{ - putreg32(value, priv->config->base + offset); -} - -/**************************************************************************** - * Name: stm32_dumpregs - * - * Description: - * Dump all timer registers. - * - * Input Parameters: - * priv - A reference to the QENCODER block status - * - * Returned Value: - * None - * - ****************************************************************************/ - -#if defined(CONFIG_DEBUG_SENSORS) && defined(CONFIG_DEBUG_INFO) -static void stm32_dumpregs(struct stm32_lowerhalf_s *priv, - const char *msg) -{ - sninfo("%s:\n", msg); - sninfo(" CR1: %04x CR2: %04x SMCR: %08" PRIx32 " DIER: %04x\n", - stm32_getreg16(priv, STM32_GTIM_CR1_OFFSET), - stm32_getreg16(priv, STM32_GTIM_CR2_OFFSET), - stm32_getreg32(priv, STM32_GTIM_SMCR_OFFSET), - stm32_getreg16(priv, STM32_GTIM_DIER_OFFSET)); - sninfo(" SR: %04x EGR: %04x CCMR1: %08" PRIx32 - " CCMR2: %08" PRIx32 "\n", - stm32_getreg16(priv, STM32_GTIM_SR_OFFSET), - stm32_getreg16(priv, STM32_GTIM_EGR_OFFSET), - stm32_getreg32(priv, STM32_GTIM_CCMR1_OFFSET), - stm32_getreg32(priv, STM32_GTIM_CCMR2_OFFSET)); - sninfo(" CCER: %04x CNT: %08" PRIx32 " PSC: %04x" - " ARR: %08" PRIx32 "\n", - stm32_getreg16(priv, STM32_GTIM_CCER_OFFSET), - stm32_getreg32(priv, STM32_GTIM_CNT_OFFSET), - stm32_getreg16(priv, STM32_GTIM_PSC_OFFSET), - stm32_getreg32(priv, STM32_GTIM_ARR_OFFSET)); - sninfo(" CCR1: %08" PRIx32 " CCR2: %08" PRIx32 "\n", - stm32_getreg32(priv, STM32_GTIM_CCR1_OFFSET), - stm32_getreg32(priv, STM32_GTIM_CCR2_OFFSET)); - sninfo(" CCR3: %08" PRIx32 " CCR4: %08" PRIx32 "\n", - stm32_getreg32(priv, STM32_GTIM_CCR3_OFFSET), - stm32_getreg32(priv, STM32_GTIM_CCR4_OFFSET)); -#if defined(CONFIG_STM32F0L0G0_TIM1_QE) - if (priv->config->timid == 1) - { - sninfo(" RCR: %04x BDTR: %04x DCR: %04x DMAR: %04x\n", - stm32_getreg16(priv, STM32_ATIM_RCR_OFFSET), - stm32_getreg16(priv, STM32_ATIM_BDTR_OFFSET), - stm32_getreg16(priv, STM32_ATIM_DCR_OFFSET), - stm32_getreg16(priv, STM32_ATIM_DMAR_OFFSET)); - } - else -#endif - { - sninfo(" DCR: %04x DMAR: %04x\n", - stm32_getreg16(priv, STM32_GTIM_DCR_OFFSET), - stm32_getreg16(priv, STM32_GTIM_DMAR_OFFSET)); - } -} -#endif - -/**************************************************************************** - * Name: stm32_tim2lower - * - * Description: - * Map a timer number to a device structure - * - ****************************************************************************/ - -static struct stm32_lowerhalf_s *stm32_tim2lower(int tim) -{ - switch (tim) - { -#ifdef CONFIG_STM32F0L0G0_TIM1_QE - case 1: - return &g_tim1lower; -#endif -#ifdef CONFIG_STM32F0L0G0_TIM2_QE - case 2: - return &g_tim2lower; -#endif -#ifdef CONFIG_STM32F0L0G0_TIM3_QE - case 3: - return &g_tim3lower; -#endif -#ifdef CONFIG_STM32F0L0G0_TIM4_QE - case 4: - return &g_tim4lower; -#endif - default: - return NULL; - } -} - -/**************************************************************************** - * Name: stm32_qe_index_irq - * - * Description: - * Common encoder index pin interrupt. - * - ****************************************************************************/ - -#ifdef CONFIG_STM32F0L0G0_QENCODER_INDEX_PIN -static int stm32_qe_index_irq(int irq, void *context, void *arg) -{ - struct stm32_lowerhalf_s *priv; - bool valid = false; - - DEBUGASSERT(arg); - - priv = (struct stm32_lowerhalf_s *)arg; - - valid = stm32_gpioread(priv->index_pin); - - if (valid == true) - { - stm32_putreg32(priv, STM32_GTIM_CNT_OFFSET, priv->index_offset); - } - - return OK; -} -#endif - -/**************************************************************************** - * Name: stm32_interrupt - * - * Description: - * Common timer interrupt handling. NOTE: Only 16-bit timers require timer - * interrupts. - * - ****************************************************************************/ - -#ifndef CONFIG_STM32F0L0G0_QENCODER_DISABLE_EXTEND16BTIMERS -static int stm32_interrupt(int irq, void *context, void *arg) -{ - struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)arg; - uint16_t regval; - - DEBUGASSERT(priv != NULL); - - /* Verify that this is an update interrupt. - * Nothing else is expected. - */ - - regval = stm32_getreg16(priv, STM32_GTIM_SR_OFFSET); - DEBUGASSERT((regval & ATIM_SR_UIF) != 0); - - /* Clear the UIF interrupt bit */ - - stm32_putreg16(priv, STM32_GTIM_SR_OFFSET, regval & ~GTIM_SR_UIF); - - /* Check the direction bit in the CR1 register and add or subtract the - * maximum value, as appropriate. - */ - - regval = stm32_getreg16(priv, STM32_GTIM_CR1_OFFSET); - if ((regval & ATIM_CR1_DIR) != 0) - { - priv->position -= (int32_t)0x0000ffff; - } - else - { - priv->position += (int32_t)0x0000ffff; - } - - return OK; -} -#endif - -/**************************************************************************** - * Name: stm32_setup - * - * Description: - * This method is called when the driver is opened. The lower half driver - * should configure and initialize the device so that it is ready for use. - * The initial position value should be zero. * - * - ****************************************************************************/ - -static int stm32_setup(struct qe_lowerhalf_s *lower) -{ - struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; - uint16_t dier; - uint32_t smcr; - uint32_t ccmr1; - uint16_t ccer; - uint16_t cr1; -#ifndef CONFIG_STM32F0L0G0_QENCODER_DISABLE_EXTEND16BTIMERS - uint16_t regval; - int ret; -#endif - - /* NOTE: - * Clocking should have been enabled in the low-level RCC logic at boot-up - */ - - /* Timer base configuration */ - - cr1 = stm32_getreg16(priv, STM32_GTIM_CR1_OFFSET); - - /* Clear the direction bit (0=count up) and select the Counter Mode - * (0=Edge aligned) - * (Timers 2-5 and 1-8 only) - */ - - cr1 &= ~(GTIM_CR1_DIR | GTIM_CR1_CMS_MASK); - stm32_putreg16(priv, STM32_GTIM_CR1_OFFSET, cr1); - - /* Set the Autoreload value */ - -#if defined(HAVE_MIXEDWIDTH_TIMERS) - if (priv->config->width == 32) - { - stm32_putreg32(priv, STM32_GTIM_ARR_OFFSET, 0xffffffff); - } - else - { - stm32_putreg16(priv, STM32_GTIM_ARR_OFFSET, 0xffff); - } -#elif defined(HAVE_32BIT_TIMERS) - stm32_putreg32(priv, STM32_GTIM_ARR_OFFSET, 0xffffffff); -#else - stm32_putreg16(priv, STM32_GTIM_ARR_OFFSET, 0xffff); -#endif - - /* Set the timer prescaler value. */ - - stm32_putreg16(priv, - STM32_GTIM_PSC_OFFSET, (uint16_t)priv->config->psc); - -#if defined(CONFIG_STM32F0L0G0_TIM1_QE) - if (priv->config->timid == 1) - { - /* Clear the Repetition Counter value */ - - stm32_putreg16(priv, STM32_ATIM_RCR_OFFSET, 0); - } -#endif - - /* Generate an update event to reload the Prescaler - * and the repetition counter (only for TIM1) value immediately - */ - - stm32_putreg16(priv, STM32_GTIM_EGR_OFFSET, GTIM_EGR_UG); - - /* GPIO pin configuration */ - - stm32_configgpio(priv->config->ti1cfg); - stm32_configgpio(priv->config->ti2cfg); - - /* Set the encoder Mode 3 */ - - smcr = stm32_getreg32(priv, STM32_GTIM_SMCR_OFFSET); - smcr &= ~GTIM_SMCR_SMS_MASK; - smcr |= GTIM_SMCR_ENCMD3; - stm32_putreg32(priv, STM32_GTIM_SMCR_OFFSET, smcr); - - /* TI1 Channel Configuration */ - - /* Disable the Channel 1: Reset the CC1E Bit */ - - ccer = stm32_getreg16(priv, STM32_GTIM_CCER_OFFSET); - ccer &= ~GTIM_CCER_CC1E; - stm32_putreg16(priv, STM32_GTIM_CCER_OFFSET, ccer); - - ccmr1 = stm32_getreg32(priv, STM32_GTIM_CCMR1_OFFSET); - ccer = stm32_getreg16(priv, STM32_GTIM_CCER_OFFSET); - - /* Select the Input IC1=TI1 and set the filter fSAMPLING=fDTS/4, N=6 */ - - ccmr1 &= ~(GTIM_CCMR1_CC1S_MASK | GTIM_CCMR1_IC1F_MASK); - ccmr1 |= GTIM_CCMR_CCS_CCIN1 << GTIM_CCMR1_CC1S_SHIFT; - ccmr1 |= STM32F0L0G0_QENCODER_ICF << GTIM_CCMR1_IC1F_SHIFT; - - /* Select the Polarity=rising and set the CC1E Bit */ - - ccer &= ~(GTIM_CCER_CC1P | GTIM_CCER_CC1NP); - ccer |= GTIM_CCER_CC1E; - - /* Write to TIM CCMR1 and CCER registers */ - - stm32_putreg32(priv, STM32_GTIM_CCMR1_OFFSET, ccmr1); - stm32_putreg16(priv, STM32_GTIM_CCER_OFFSET, ccer); - - /* Set the Input Capture Prescaler value: Capture performed each time an - * edge is detected on the capture input. - */ - - ccmr1 = stm32_getreg32(priv, STM32_GTIM_CCMR1_OFFSET); - ccmr1 &= ~GTIM_CCMR1_IC1PSC_MASK; - ccmr1 |= (GTIM_CCMR_ICPSC_NOPSC << GTIM_CCMR1_IC1PSC_SHIFT); - stm32_putreg32(priv, STM32_GTIM_CCMR1_OFFSET, ccmr1); - - /* TI2 Channel Configuration */ - - /* Disable the Channel 2: Reset the CC2E Bit */ - - ccer = stm32_getreg16(priv, STM32_GTIM_CCER_OFFSET); - ccer &= ~GTIM_CCER_CC2E; - stm32_putreg16(priv, STM32_GTIM_CCER_OFFSET, ccer); - - ccmr1 = stm32_getreg32(priv, STM32_GTIM_CCMR1_OFFSET); - ccer = stm32_getreg16(priv, STM32_GTIM_CCER_OFFSET); - - /* Select the Input IC2=TI2 and set the filter fSAMPLING=fDTS/4, N=6 */ - - ccmr1 &= ~(GTIM_CCMR1_CC2S_MASK | GTIM_CCMR1_IC2F_MASK); - ccmr1 |= GTIM_CCMR_CCS_CCIN1 << GTIM_CCMR1_CC2S_SHIFT; - ccmr1 |= STM32F0L0G0_QENCODER_ICF << GTIM_CCMR1_IC2F_SHIFT; - - /* Select the Polarity=rising and set the CC2E Bit */ - - ccer &= ~(GTIM_CCER_CC2P | GTIM_CCER_CC2NP); - ccer |= GTIM_CCER_CC2E; - - /* Write to TIM CCMR1 and CCER registers */ - - stm32_putreg32(priv, STM32_GTIM_CCMR1_OFFSET, ccmr1); - stm32_putreg16(priv, STM32_GTIM_CCER_OFFSET, ccer); - - /* Set the Input Capture Prescaler value: Capture performed each time an - * edge is detected on the capture input. - */ - - ccmr1 = stm32_getreg32(priv, STM32_GTIM_CCMR1_OFFSET); - ccmr1 &= ~GTIM_CCMR1_IC2PSC_MASK; - ccmr1 |= (GTIM_CCMR_ICPSC_NOPSC << GTIM_CCMR1_IC2PSC_SHIFT); - stm32_putreg32(priv, STM32_GTIM_CCMR1_OFFSET, ccmr1); - - /* Disable the update interrupt */ - - dier = stm32_getreg16(priv, STM32_GTIM_DIER_OFFSET); - dier &= ~GTIM_DIER_UIE; - stm32_putreg16(priv, STM32_GTIM_DIER_OFFSET, dier); - - /* There is no need for interrupts with 32-bit timers */ - -#ifndef CONFIG_STM32F0L0G0_QENCODER_DISABLE_EXTEND16BTIMERS -#ifdef HAVE_MIXEDWIDTH_TIMERS - if (priv->config->width != 32) -#endif - { - /* Attach the interrupt handler */ - - ret = irq_attach(priv->config->irq, stm32_interrupt, priv); - if (ret < 0) - { - stm32_shutdown(lower); - return ret; - } - - /* Enable the update/global interrupt at the NVIC */ - - up_enable_irq(priv->config->irq); - } -#endif - - /* Reset the Update Disable Bit */ - - cr1 = stm32_getreg16(priv, STM32_GTIM_CR1_OFFSET); - cr1 &= ~GTIM_CR1_UDIS; - stm32_putreg16(priv, STM32_GTIM_CR1_OFFSET, cr1); - - /* Reset the URS Bit */ - - cr1 &= ~GTIM_CR1_URS; - stm32_putreg16(priv, STM32_GTIM_CR1_OFFSET, cr1); - - /* There is no need for interrupts with 32-bit timers */ - -#ifndef CONFIG_STM32F0L0G0_QENCODER_DISABLE_EXTEND16BTIMERS -#ifdef HAVE_MIXEDWIDTH_TIMERS - if (priv->config->width != 32) -#endif - { - /* Clear any pending update interrupts */ - - regval = stm32_getreg16(priv, STM32_GTIM_SR_OFFSET); - stm32_putreg16(priv, STM32_GTIM_SR_OFFSET, regval & ~GTIM_SR_UIF); - - /* Then enable the update interrupt */ - - dier = stm32_getreg16(priv, STM32_GTIM_DIER_OFFSET); - dier |= GTIM_DIER_UIE; - stm32_putreg16(priv, STM32_GTIM_DIER_OFFSET, dier); - } -#endif - -#ifdef CONFIG_STM32F0L0G0_QENCODER_INDEX_PIN - priv->index_offset = 0; -#endif - - /* Enable the TIM Counter */ - - cr1 = stm32_getreg16(priv, STM32_GTIM_CR1_OFFSET); - cr1 |= GTIM_CR1_CEN; - stm32_putreg16(priv, STM32_GTIM_CR1_OFFSET, cr1); - - stm32_dumpregs(priv, "After setup"); - - return OK; -} - -/**************************************************************************** - * Name: stm32_shutdown - * - * Description: - * This method is called when the driver is closed. The lower half driver - * should stop data collection, free any resources, disable timer hardware, - * and put the system into the lowest possible power usage state * - * - ****************************************************************************/ - -static int stm32_shutdown(struct qe_lowerhalf_s *lower) -{ - struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; - irqstate_t flags; - uint32_t regaddr; - uint32_t regval; - uint32_t resetbit; - uint32_t pincfg; - - /* Disable the update/global interrupt at the NVIC */ - - flags = enter_critical_section(); - up_disable_irq(priv->config->irq); - - /* Detach the interrupt handler */ - - irq_detach(priv->config->irq); - - /* Disable interrupts momentary to stop any ongoing timer processing and - * to prevent any concurrent access to the reset register. - */ - - /* Disable further interrupts and stop the timer */ - - stm32_putreg16(priv, STM32_GTIM_DIER_OFFSET, 0); - stm32_putreg16(priv, STM32_GTIM_SR_OFFSET, 0); - - /* Determine which timer to reset */ - - switch (priv->config->timid) - { -#ifdef CONFIG_STM32F0L0G0_TIM1_QE - case 1: - regaddr = STM32_RCC_APB2RSTR; - resetbit = RCC_APB2RSTR_TIM1RST; - break; -#endif -#ifdef CONFIG_STM32F0L0G0_TIM2_QE - case 2: - regaddr = STM32_RCC_APB1RSTR; - resetbit = RCC_APB1RSTR_TIM2RST; - break; -#endif -#ifdef CONFIG_STM32F0L0G0_TIM3_QE - case 3: - regaddr = STM32_RCC_APB1RSTR; - resetbit = RCC_APB1RSTR_TIM3RST; - break; -#endif -#ifdef CONFIG_STM32F0L0G0_TIM4_QE - case 4: - regaddr = STM32_RCC_APB1RSTR; - resetbit = RCC_APB1RSTR_TIM4RST; - break; -#endif - default: - leave_critical_section(flags); - return -EINVAL; - } - - /* Reset the timer - stopping the output and putting the timer back - * into a state where stm32_start() can be called. - */ - - regval = getreg32(regaddr); - regval |= resetbit; - putreg32(regval, regaddr); - - regval &= ~resetbit; - putreg32(regval, regaddr); - leave_critical_section(flags); - - sninfo("regaddr: %08" PRIx32 " resetbit: %08" PRIx32 "\n", - regaddr, resetbit); - stm32_dumpregs(priv, "After stop"); - - /* Put the TI1 GPIO pin back to its default state */ - - pincfg = priv->config->ti1cfg & (GPIO_PORT_MASK | GPIO_PIN_MASK); - pincfg |= STM32F0L0G0_GPIO_INPUT_FLOAT; - - stm32_configgpio(pincfg); - - /* Put the TI2 GPIO pin back to its default state */ - - pincfg = priv->config->ti2cfg & (GPIO_PORT_MASK | GPIO_PIN_MASK); - pincfg |= STM32F0L0G0_GPIO_INPUT_FLOAT; - - stm32_configgpio(pincfg); - return OK; -} - -/**************************************************************************** - * Name: stm32_position - * - * Description: - * Return the current position measurement. - * - ****************************************************************************/ - -static int stm32_position(struct qe_lowerhalf_s *lower, int32_t *pos) -{ - struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; -#ifndef CONFIG_STM32F0L0G0_QENCODER_DISABLE_EXTEND16BTIMERS - irqstate_t flags; - int32_t position; - int32_t verify; - uint32_t count; - - DEBUGASSERT(lower && priv->inuse); - - /* Loop until we are certain that no interrupt occurred between samples */ - - flags = spin_lock_irqsave(&priv->lock); - do - { - position = priv->position; - count = stm32_getreg32(priv, STM32_GTIM_CNT_OFFSET); - verify = priv->position; - } - while (position != verify); - spin_unlock_irqrestore(&priv->lock, flags); - - /* Return the position measurement */ - - *pos = position + (int32_t)count; -#else - /* Return the counter value */ - - *pos = (int32_t)stm32_getreg32(priv, STM32_GTIM_CNT_OFFSET); -#endif - return OK; -} - -/**************************************************************************** - * Name: stm32_reset - * - * Description: - * Reset the position measurement to zero. - * - ****************************************************************************/ - -static int stm32_reset(struct qe_lowerhalf_s *lower) -{ - struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; -#ifndef CONFIG_STM32F0L0G0_QENCODER_DISABLE_EXTEND16BTIMERS - irqstate_t flags; - - sninfo("Resetting position to zero\n"); - DEBUGASSERT(lower && priv->inuse); - - /* Reset the timer and the counter. - * Interrupts are disabled to make this atomic (if possible) - */ - - flags = spin_lock_irqsave(&priv->lock); - stm32_putreg32(priv, STM32_GTIM_CNT_OFFSET, 0); - priv->position = 0; - spin_unlock_irqrestore(&priv->lock, flags); -#else - sninfo("Resetting position to zero\n"); - DEBUGASSERT(lower && priv->inuse); - - /* Reset the counter to zero */ - - stm32_putreg32(priv, STM32_GTIM_CNT_OFFSET, 0); -#endif - return OK; -} - -/**************************************************************************** - * Name: stm32_setposmax - * - * Description: - * Set the maximum encoder position. - * - ****************************************************************************/ - -static int stm32_setposmax(struct qe_lowerhalf_s *lower, uint32_t pos) -{ - struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; - - DEBUGASSERT(lower && priv->inuse); - -#if defined(HAVE_MIXEDWIDTH_TIMERS) - if (priv->config->width == 32) - { - stm32_putreg32(priv, STM32_GTIM_ARR_OFFSET, pos); - } - else - { - stm32_putreg16(priv, STM32_GTIM_ARR_OFFSET, pos); - } -#elif defined(HAVE_32BIT_TIMERS) - stm32_putreg32(priv, STM32_GTIM_ARR_OFFSET, pos); -#else - stm32_putreg16(priv, STM32_GTIM_ARR_OFFSET, pos); -#endif - - return OK; -} - -/**************************************************************************** - * Name: stm32_setindex - * - * Description: - * Set the index pin position - * - ****************************************************************************/ - -static int stm32_setindex(struct qe_lowerhalf_s *lower, uint32_t pos) -{ -#ifdef CONFIG_STM32F0L0G0_QENCODER_INDEX_PIN - struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; - int ret = OK; - - sninfo("Set QE TIM%d the index pin position %" PRIx32 "\n", - priv->config->timid, pos); - DEBUGASSERT(lower && priv->inuse); - - if (priv->index_use == false) - { - snerr("ERROR: QE TIM%d index not registered\n", - priv->config->timid); - ret = -EPERM; - goto errout; - } - - priv->index_offset = pos; - -errout: - return ret; -#else - return -ENOTTY; -#endif -} - -/**************************************************************************** - * Name: stm32_ioctl - * - * Description: - * Lower-half logic may support platform-specific ioctl commands - * - ****************************************************************************/ - -static int stm32_ioctl(struct qe_lowerhalf_s *lower, int cmd, - unsigned long arg) -{ - /* No ioctl commands supported */ - - /* TODO add an IOCTL to control the encoder pulse count prescaler */ - - return -ENOTTY; -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_qeinitialize - * - * Description: - * Initialize a quadrature encoder interface. - * This function must be called from board-specific logic. - * - * Input Parameters: - * devpath - The full path to the driver to register. E.g., "/dev/qe0" - * tim - The timer number to used. 'tim' must be an element of - * {1,2,3,4} - * - * Returned Value: - * Zero on success; A negated errno value is returned on failure. - * - ****************************************************************************/ - -int stm32_qeinitialize(const char *devpath, int tim) -{ - struct stm32_lowerhalf_s *priv; - int ret; - - /* Find the pre-allocated timer state structure corresponding to this - * timer - */ - - priv = stm32_tim2lower(tim); - if (!priv) - { - snerr("ERROR: TIM%d support not configured\n", tim); - return -ENXIO; - } - - /* Make sure that it is available */ - - if (priv->inuse) - { - snerr("ERROR: TIM%d is in-use\n", tim); - return -EBUSY; - } - - /* Register the priv-half driver */ - - ret = qe_register(devpath, (struct qe_lowerhalf_s *)priv); - if (ret < 0) - { - snerr("ERROR: qe_register failed: %d\n", ret); - return ret; - } - - /* Make sure that the timer is in the shutdown state */ - - stm32_shutdown((struct qe_lowerhalf_s *)priv); - - /* The driver is now in-use */ - - priv->inuse = true; - return OK; -} - -#ifdef CONFIG_STM32F0L0G0_QENCODER_INDEX_PIN -/**************************************************************************** - * Name: stm32_qe_index_init - * - * Description: - * Register the encoder index pin to a given Qencoder timer - * - * Input Parameters: - * tim - The qenco timer number - * gpio - gpio pin configuration - * - * Returned Value: - * Zero on success; A negated errno value is returned on failure. - * - ****************************************************************************/ - -int stm32_qe_index_init(int tim, uint32_t gpio) -{ - struct stm32_lowerhalf_s *priv; - int ret = OK; - - priv = stm32_tim2lower(tim); - if (!priv) - { - snerr("ERROR: TIM%d support not configured\n", tim); - return -ENXIO; - } - - if (priv->inuse == false) - { - snerr("ERROR: TIM%d is not in-use\n", tim); - ret = -EINVAL; - } - - priv->index_pin = gpio; - stm32_configgpio(priv->index_pin); - - ret = stm32_gpiosetevent(gpio, true, false, true, - stm32_qe_index_irq, priv); - if (ret < 0) - { - snerr("ERROR: QE TIM%d failed register irq\n", tim); - goto errout; - } - - priv->index_use = true; - -errout: - return ret; -} -#endif diff --git a/arch/arm/src/stm32f0l0g0/stm32_qencoder.h b/arch/arm/src/stm32f0l0g0/stm32_qencoder.h deleted file mode 100644 index b6f1c4c9d9c7d..0000000000000 --- a/arch/arm/src/stm32f0l0g0/stm32_qencoder.h +++ /dev/null @@ -1,116 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_qencoder.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_STM32_QENCODER_H -#define __ARCH_ARM_SRC_STM32F0L0G0_STM32_QENCODER_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "chip.h" - -#ifdef CONFIG_SENSORS_QENCODER - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Timer devices may be used for different purposes. One special purpose is - * as a quadrature encoder input device. If CONFIG_STM32F0L0G0_TIMn is - * defined then the CONFIG_STM32F0L0G0_TIMn_QE must also be defined to - * indicate that timer "n" is intended to be used for as a quadrature - * encoder. - */ - -#ifndef CONFIG_STM32F0L0G0_TIM1 -# undef CONFIG_STM32F0L0G0_TIM1_QE -#endif -#ifndef CONFIG_STM32F0L0G0_TIM2 -# undef CONFIG_STM32F0L0G0_TIM2_QE -#endif -#ifndef CONFIG_STM32F0L0G0_TIM3 -# undef CONFIG_STM32F0L0G0_TIM3_QE -#endif -#ifndef CONFIG_STM32F0L0G0_TIM4 -# undef CONFIG_STM32F0L0G0_TIM4_QE -#endif - -/* Only timers 1-4 can be used as a quadrature encoder (timers with - * encoder mode support). - * TIM6, TIM7, TIM14-17 are basic/general purpose timers without encoder - * capability. - */ - -#undef CONFIG_STM32F0L0G0_TIM6_QE -#undef CONFIG_STM32F0L0G0_TIM7_QE -#undef CONFIG_STM32F0L0G0_TIM14_QE -#undef CONFIG_STM32F0L0G0_TIM15_QE -#undef CONFIG_STM32F0L0G0_TIM16_QE -#undef CONFIG_STM32F0L0G0_TIM17_QE - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_qeinitialize - * - * Description: - * Initialize a quadrature encoder interface. - * This function must be called from board-specific logic. - * - * Input Parameters: - * devpath - The full path to the driver to register. E.g., "/dev/qe0" - * tim - The timer number to used. - * 'tim' must be an element of {1,2,3,4} - * - * Returned Value: - * Zero on success; A negated errno value is returned on failure. - * - ****************************************************************************/ - -int stm32_qeinitialize(const char *devpath, int tim); - -#ifdef CONFIG_STM32F0L0G0_QENCODER_INDEX_PIN -/**************************************************************************** - * Name: stm32_qe_index_init - * - * Description: - * Register the encoder index pin to a given Qencoder timer - * - * Input Parameters: - * tim - The qenco timer number - * gpio - gpio pin configuration - * - * Returned Value: - * Zero on success; A negated errno value is returned on failure. - * - ****************************************************************************/ - -int stm32_qe_index_init(int tim, uint32_t gpio); -#endif - -#endif /* CONFIG_SENSORS_QENCODER */ -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_STM32_QENCODER_H */ diff --git a/arch/arm/src/stm32f0l0g0/stm32_rcc.c b/arch/arm/src/stm32f0l0g0/stm32_rcc.c deleted file mode 100644 index 7e89c4b1e20da..0000000000000 --- a/arch/arm/src/stm32f0l0g0/stm32_rcc.c +++ /dev/null @@ -1,230 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_rcc.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include - -#include - -#include "arm_internal.h" -#include "hardware/stm32_flash.h" -#include "stm32_rcc.h" -#include "stm32_hsi48.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#ifdef CONFIG_STM32F0L0G0_RNG -# ifndef STM32_USE_CLK48 -# error RNG requires CLK48 enabled -# endif -#endif - -#ifdef CONFIG_STM32F0L0G0_USB -# ifndef STM32_USE_CLK48 -# error USB requires CLK48 enabled -# endif -#endif - -static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1, - "Configure BOARD_LOOPSPERMSEC to non-default value."); - -/* Allow up to 100 milliseconds for the high speed clock to become ready. - * that is a very long delay, but if the clock does not become ready we are - * hosed anyway. - */ - -#define HSERDY_TIMEOUT (100 * CONFIG_BOARD_LOOPSPERMSEC) - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -/* Include chip-specific clocking initialization logic */ - -#if defined(CONFIG_ARCH_CHIP_STM32F0) -# include "stm32f0_rcc.c" -#elif defined(CONFIG_ARCH_CHIP_STM32L0) -# include "stm32l0_rcc.c" -#elif defined(CONFIG_ARCH_CHIP_STM32G0) -# include "stm32g0_rcc.c" -#elif defined(CONFIG_ARCH_CHIP_STM32C0) -# include "stm32c0_rcc.c" -#else -# error "Unsupported STM32F0/L0 RCC" -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: rcc_resetbkp - * - * Description: - * The RTC needs to reset the Backup Domain to change RTCSEL and resetting - * the Backup Domain renders to disabling the LSE as consequence. - * In order to avoid resetting the Backup Domain when we already configured - * LSE we will reset the Backup Domain early (here). - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -#if defined(CONFIG_STM32F0L0G0_RTC) && defined(CONFIG_STM32F0L0G0_PWR) -static inline void rcc_resetbkp(void) -{ - uint32_t regval; - - /* Check if the RTC is already configured */ - - stm32_pwr_initbkp(false); - - regval = getreg32(RTC_MAGIC_REG); - if (regval != RTC_MAGIC && regval != RTC_MAGIC_TIME_SET) - { - stm32_pwr_enablebkp(true); - - /* We might be changing RTCSEL - to ensure such changes work, we must - * reset the backup domain (having backed up the RTC_MAGIC token) - */ - - modifyreg32(STM32_RCC_BDCR, 0, RCC_BDCR_BDRST); - modifyreg32(STM32_RCC_BDCR, RCC_BDCR_BDRST, 0); - - stm32_pwr_enablebkp(false); - } -} -#else -# define rcc_resetbkp() -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_clockconfig - * - * Description: - * Called to establish the clock settings based on the values in board.h. - * This function (by default) will reset most everything, enable the PLL, - * and enable peripheral clocking for all peripherals enabled in the NuttX - * configuration file. - * - * If CONFIG_ARCH_BOARD_STM32F0G0L0_CUSTOM_CLOCKCONFIG is defined, then - * clocking will be enabled by an externally provided, board-specific - * function called stm32_board_clockconfig(). - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -void stm32_clockconfig(void) -{ - /* Make sure that we are starting in the reset state */ - - rcc_reset(); - - /* Reset backup domain if appropriate */ - - rcc_resetbkp(); - -#if defined(CONFIG_ARCH_BOARD_STM32F0G0L0_CUSTOM_CLOCKCONFIG) - /* Invoke Board Custom Clock Configuration */ - - stm32_board_clockconfig(); - -#else - /* Invoke standard, fixed clock configuration based on definitions - * in board.h - */ - - stm32_stdclockconfig(); - -#endif - - /* Enable peripheral clocking */ - - rcc_enableperipherals(); -} - -/**************************************************************************** - * Name: stm32_clockenable - * - * Description: - * Re-enable the clock and restore the clock settings based on settings in - * board.h. This function is only available to support low-power modes of - * operation: When re-awakening from deep-sleep modes, it is necessary to - * re-enable/re-start the PLL - * - * This functional performs a subset of the operations performed by - * stm32_clockconfig(): It does not reset any devices, and it does not - * reset the currently enabled peripheral clocks. - * - * If CONFIG_ARCH_BOARD_STM32F0G0L0_CUSTOM_CLOCKCONFIG is defined, then - * clocking will be enabled by an externally provided, board-specific - * function called stm32_board_clockconfig(). - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef CONFIG_PM -void stm32_clockenable(void) -{ -#if defined(CONFIG_ARCH_BOARD_STM32F0G0L0_CUSTOM_CLOCKCONFIG) - /* Invoke Board Custom Clock Configuration */ - - stm32_board_clockconfig(); - -#else - /* Invoke standard, fixed clock configuration based on definitions - * in board.h - */ - - stm32_stdclockconfig(); - -#endif -} -#endif diff --git a/arch/arm/src/stm32f0l0g0/stm32_rcc.h b/arch/arm/src/stm32f0l0g0/stm32_rcc.h deleted file mode 100644 index 3a45a94a0cdc4..0000000000000 --- a/arch/arm/src/stm32f0l0g0/stm32_rcc.h +++ /dev/null @@ -1,90 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_rcc.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_STM32_RCC_H -#define __ARCH_ARM_SRC_STM32F0L0G0_STM32_RCC_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "arm_internal.h" -#include "chip.h" - -#include "hardware/stm32_rcc.h" - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_clockconfig - * - * Description: - * Called to initialize the STM32F0XX. - * This does whatever setup is needed to put the MCU in a usable state. - * This includes the initialization of clocking using the settings - * in board.h. - * - ****************************************************************************/ - -void stm32_clockconfig(void); - -/**************************************************************************** - * Name: stm32_rcc_enablelse - * - * Description: - * Enable the External Low-Speed (LSE) Oscillator. - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -void stm32_rcc_enablelse(void); - -/**************************************************************************** - * Name: stm32_rcc_enablelsi - * - * Description: - * Enable the Internal Low-Speed (LSI) RC Oscillator. - * - ****************************************************************************/ - -void stm32_rcc_enablelsi(void); - -/**************************************************************************** - * Name: stm32_rcc_disablelsi - * - * Description: - * Disable the Internal Low-Speed (LSI) RC Oscillator. - * - ****************************************************************************/ - -void stm32_rcc_disablelsi(void); - -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_STM32_RCC_H */ diff --git a/arch/arm/src/stm32f0l0g0/stm32_rng.c b/arch/arm/src/stm32f0l0g0/stm32_rng.c deleted file mode 100644 index 49b43f2796e76..0000000000000 --- a/arch/arm/src/stm32f0l0g0/stm32_rng.c +++ /dev/null @@ -1,314 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_rng.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include - -#include "hardware/stm32_rng.h" -#include "arm_internal.h" - -#if defined(CONFIG_STM32F0L0G0_RNG) -#if defined(CONFIG_DEV_RANDOM) || defined(CONFIG_DEV_URANDOM_ARCH) - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -static int stm32_rng_initialize(void); -static int stm32_rng_interrupt(int irq, void *context, void *arg); -static void stm32_rng_enable(void); -static void stm32_rng_disable(void); -static ssize_t stm32_rng_read(struct file *filep, char *buffer, size_t); - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -struct rng_dev_s -{ - mutex_t rd_devlock; /* Threads can only exclusively access the RNG */ - sem_t rd_readsem; /* To block until the buffer is filled */ - char *rd_buf; - size_t rd_buflen; - uint32_t rd_lastval; - bool rd_first; -}; - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -static struct rng_dev_s g_rngdev = -{ - .rd_devlock = NXMUTEX_INITIALIZER, - .rd_readsem = SEM_INITIALIZER(0), -}; - -static const struct file_operations g_rngops = -{ - NULL, /* open */ - NULL, /* close */ - stm32_rng_read, /* read */ -}; - -/**************************************************************************** - * Private functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_rng_initialize - ****************************************************************************/ - -static int stm32_rng_initialize(void) -{ - uint32_t regval; - - _info("Initializing RNG\n"); - - if (irq_attach(STM32_IRQ_RNG, stm32_rng_interrupt, NULL)) - { - /* We could not attach the ISR to the interrupt */ - - _info("Could not attach IRQ.\n"); - - return -EAGAIN; - } - - /* Enable interrupts */ - - regval = getreg32(STM32_RNG_CR); - regval |= RNG_CR_IE; - putreg32(regval, STM32_RNG_CR); - - up_enable_irq(STM32_IRQ_RNG); - - return OK; -} - -/**************************************************************************** - * Name: stm32_rng_enable - ****************************************************************************/ - -static void stm32_rng_enable(void) -{ - uint32_t regval; - - g_rngdev.rd_first = true; - - regval = getreg32(STM32_RNG_CR); - regval |= RNG_CR_RNGEN; - putreg32(regval, STM32_RNG_CR); -} - -/**************************************************************************** - * Name: stm32_rng_disable - ****************************************************************************/ - -static void stm32_rng_disable(void) -{ - uint32_t regval; - regval = getreg32(STM32_RNG_CR); - regval &= ~RNG_CR_RNGEN; - putreg32(regval, STM32_RNG_CR); -} - -/**************************************************************************** - * Name: stm32_rng_interrupt - ****************************************************************************/ - -static int stm32_rng_interrupt(int irq, void *context, void *arg) -{ - uint32_t rngsr; - uint32_t data; - - rngsr = getreg32(STM32_RNG_SR); - - if ((rngsr & (RNG_SR_SEIS | RNG_SR_CEIS)) /* Check for error bits */ - || !(rngsr & RNG_SR_DRDY)) /* Data ready must be set */ - { - /* This random value is not valid, we will try again. */ - - return OK; - } - - data = getreg32(STM32_RNG_DR); - - /* As required by the FIPS PUB (Federal Information Processing Standard - * Publication) 140-2, the first random number generated after setting the - * RNGEN bit should not be used, but saved for comparison with the next - * generated random number. Each subsequent generated random number has to - * be compared with the previously generated number. The test fails if any - * two compared numbers are equal - * (continuous random number generator test). - */ - - if (g_rngdev.rd_first) - { - g_rngdev.rd_first = false; - g_rngdev.rd_lastval = data; - return OK; - } - - if (g_rngdev.rd_lastval == data) - { - /* Two subsequent same numbers, we will try again. */ - - return OK; - } - - /* If we get here, the random number is valid. */ - - g_rngdev.rd_lastval = data; - - if (g_rngdev.rd_buflen >= 4) - { - g_rngdev.rd_buflen -= 4; - *(uint32_t *)&g_rngdev.rd_buf[g_rngdev.rd_buflen] = data; - } - else - { - while (g_rngdev.rd_buflen > 0) - { - g_rngdev.rd_buf[--g_rngdev.rd_buflen] = (char)data; - data >>= 8; - } - } - - if (g_rngdev.rd_buflen == 0) - { - /* Buffer filled, stop further interrupts. */ - - stm32_rng_disable(); - nxsem_post(&g_rngdev.rd_readsem); - } - - return OK; -} - -/**************************************************************************** - * Name: stm32_rng_read - ****************************************************************************/ - -static ssize_t stm32_rng_read(struct file *filep, - char *buffer, size_t buflen) -{ - int ret; - - ret = nxmutex_lock(&g_rngdev.rd_devlock); - if (ret < 0) - { - return ret; - } - - /* We've got the semaphore. */ - - /* Reset the operation semaphore with 0 for blocking until the - * buffer is filled from interrupts. - */ - - nxsem_reset(&g_rngdev.rd_readsem, 0); - - g_rngdev.rd_buflen = buflen; - g_rngdev.rd_buf = buffer; - - /* Enable RNG with interrupts */ - - stm32_rng_enable(); - - /* Wait until the buffer is filled */ - - ret = nxsem_wait(&g_rngdev.rd_readsem); - - /* Free RNG for next use */ - - nxmutex_unlock(&g_rngdev.rd_devlock); - return ret < 0 ? ret : buflen; -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: devrandom_register - * - * Description: - * Initialize the RNG hardware and register the /dev/random driver. - * Must be called BEFORE devurandom_register. - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef CONFIG_DEV_RANDOM -void devrandom_register(void) -{ - stm32_rng_initialize(); - register_driver("/dev/random", &g_rngops, 0444, NULL); -} -#endif - -/**************************************************************************** - * Name: devurandom_register - * - * Description: - * Register /dev/urandom - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef CONFIG_DEV_URANDOM_ARCH -void devurandom_register(void) -{ -#ifndef CONFIG_DEV_RANDOM - stm32_rng_initialize(); -#endif - register_driver("/dev/urandom", &g_rngops, 0444, NULL); -} -#endif - -#endif /* CONFIG_DEV_RANDOM || CONFIG_DEV_URANDOM_ARCH */ -#endif /* CONFIG_STM32F0L0G0_RNG */ diff --git a/arch/arm/src/stm32f0l0g0/stm32_serial.c b/arch/arm/src/stm32f0l0g0/stm32_serial.c deleted file mode 100644 index a0d8178b52fb0..0000000000000 --- a/arch/arm/src/stm32f0l0g0/stm32_serial.c +++ /dev/null @@ -1,46 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_serial.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include "chip.h" - -/* This file is only a thin shell that includes the correct serial - * implementation for the selected STM32 IP core: - * - STM32 UART IP version 1 - F0, L0 - * - STM32 UART IP version 2 - G0 - */ - -#if defined(CONFIG_STM32F0L0G0_HAVE_IP_USART_V1) -# include "stm32_serial_v1.c" -#elif defined(CONFIG_STM32F0L0G0_HAVE_IP_USART_V2) -# include "stm32_serial_v2.c" -#else -# error "Unsupported STM32 M0 serial" -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ diff --git a/arch/arm/src/stm32f0l0g0/stm32_serial.h b/arch/arm/src/stm32f0l0g0/stm32_serial.h deleted file mode 100644 index 725db01e52176..0000000000000 --- a/arch/arm/src/stm32f0l0g0/stm32_serial.h +++ /dev/null @@ -1,36 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_serial.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_STM32_SERIAL_H -#define __ARCH_ARM_SRC_STM32F0L0G0_STM32_SERIAL_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_STM32_SERIAL_H */ diff --git a/arch/arm/src/stm32f0l0g0/stm32_serial_v1.c b/arch/arm/src/stm32f0l0g0/stm32_serial_v1.c deleted file mode 100644 index 55f290837bf9c..0000000000000 --- a/arch/arm/src/stm32f0l0g0/stm32_serial_v1.c +++ /dev/null @@ -1,2614 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_serial_v1.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include - -#ifdef CONFIG_SERIAL_TERMIOS -# include -#endif - -#include "arm_internal.h" -#include "chip.h" -#include "stm32_gpio.h" -#include "stm32_uart.h" -#include "stm32_rcc.h" -#include "hardware/stm32_pinmap.h" - -/* board.h should be included last. It may depend on definitions from - * previous header files and it may, in certain cases, override definitions - * provided in previous header files. - */ - -#include - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Some sanity checks *******************************************************/ - -/* DMA configuration */ - -/* If DMA is enabled on any USART, then very that other pre-requisites - * have also been selected. - * USART DMA1 DMA2 - * 1 X X - * 2 X - * 3 X - * 4 X - * 5 X - */ - -#ifdef SERIAL_HAVE_RXDMA - -/* Verify that DMA has been enabled and the DMA channel has been defined. - */ - -# if defined(CONFIG_USART2_RXDMA) || defined(CONFIG_USART3_RXDMA) -# ifndef CONFIG_STM32F0L0G0_DMA1 -# error STM32F0 USART2/3 receive DMA requires CONFIG_STM32F0L0G0_DMA1 -# endif -# endif - -# if defined(CONFIG_USART4_RXDMA) || defined(CONFIG_USART5_RXDMA) -# ifndef CONFIG_STM32F0L0G0_DMA2 -# error STM32F0 USART4/5 receive DMA requires CONFIG_STM32F0L0G0_DMA2 -# endif -# endif - -/* Currently RS-485 support cannot be enabled when RXDMA is in use due to - * lack of testing - RS-485 support was developed on STM32F1x - */ - -# if (defined(CONFIG_USART1_RXDMA) && defined(CONFIG_USART1_RS485)) || \ - (defined(CONFIG_USART2_RXDMA) && defined(CONFIG_USART2_RS485)) || \ - (defined(CONFIG_USART3_RXDMA) && defined(CONFIG_USART3_RS485)) || \ - (defined(CONFIG_USART4_RXDMA) && defined(CONFIG_USART4_RS485)) || \ - (defined(CONFIG_USART5_RXDMA) && defined(CONFIG_USART5_RS485)) -# error "RXDMA and RS-485 cannot be enabled at the same time for the same U[S]ART" -# endif - -/* For the L4, there are alternate DMA channels for USART1. - * Logic in the board.h file make the DMA channel selection by defining - * the following in the board.h file. - */ - -# if defined(CONFIG_USART1_RXDMA) && !defined(DMAMAP_USART1_RX) -# error "USART1 DMA channel not defined (DMAMAP_USART1_RX)" -# endif - -/* USART2-5 have no alternate channels */ - -# define DMAMAP_USART2_RX DMACHAN_USART2_RX -# define DMAMAP_USART3_RX DMACHAN_USART3_RX -# define DMAMAP_USART4_RX DMACHAN_USART4_RX -# define DMAMAP_USART5_RX DMACHAN_USART5_RX - -/* The DMA buffer size when using RX DMA to emulate a FIFO. - * - * When streaming data, the generic serial layer will be called - * every time the FIFO receives half this number of bytes. - */ - -# define RXDMA_BUFFER_SIZE 32 - -/* DMA priority */ - -# ifndef CONFIG_USART_RXDMAPRIO -# define CONFIG_USART_RXDMAPRIO DMA_CCR_PRIMED -# endif -# if (CONFIG_USART_RXDMAPRIO & ~DMA_CCR_PL_MASK) != 0 -# error "Illegal value for CONFIG_USART_RXDMAPRIO" -# endif - -/* DMA control words */ - -# define SERIAL_DMA_CONTROL_WORD \ - (DMA_CCR_CIRC | \ - DMA_CCR_MINC | \ - DMA_CCR_PSIZE_8BITS | \ - DMA_CCR_MSIZE_8BITS | \ - CONFIG_USART_RXDMAPRIO) -# ifdef CONFIG_SERIAL_IFLOWCONTROL -# define SERIAL_DMA_IFLOW_CONTROL_WORD \ - (DMA_CCR_MINC | \ - DMA_CCR_PSIZE_8BITS | \ - DMA_CCR_MSIZE_8BITS | \ - CONFIG_USART_RXDMAPRIO) -# endif - -#endif - -/* Power management definitions */ - -#if defined(CONFIG_PM) && !defined(CONFIG_STM32F0L0G0_PM_SERIAL_ACTIVITY) -# define CONFIG_STM32F0L0G0_PM_SERIAL_ACTIVITY 10 -#endif - -/* Keep track if a Break was set - * - * Note: - * - * 1) This value is set in the priv->ie but never written to the control - * register. It must not collide with USART_CR1_USED_INTS or USART_CR3_EIE - * 2) USART_CR3_EIE is also carried in the up_dev_s ie member. - * - * See stm32serial_restoreusartint where the masking is done. - */ - -#ifdef CONFIG_STM32F0L0G0_SERIALBRK_BSDCOMPAT -# define USART_CR1_IE_BREAK_INPROGRESS_SHFTS 15 -# define USART_CR1_IE_BREAK_INPROGRESS (1 << USART_CR1_IE_BREAK_INPROGRESS_SHFTS) -#endif - -#ifdef USE_SERIALDRIVER -#ifdef HAVE_USART - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -struct stm32_serial_s -{ - struct uart_dev_s dev; /* Generic USART device */ - uint16_t ie; /* Saved interrupt mask bits value */ - uint16_t sr; /* Saved status bits */ - - /* If termios are supported, then the following fields may vary at - * runtime. - */ - -#ifdef CONFIG_SERIAL_TERMIOS - uint8_t parity; /* 0=none, 1=odd, 2=even */ - uint8_t bits; /* Number of bits (7 or 8) */ - bool stopbits2; /* True: Configure with 2 stop bits instead of 1 */ -#ifdef CONFIG_SERIAL_IFLOWCONTROL - bool iflow; /* input flow control (RTS) enabled */ -#endif -#ifdef CONFIG_SERIAL_OFLOWCONTROL - bool oflow; /* output flow control (CTS) enabled */ -#endif - uint32_t baud; /* Configured baud */ -#else - const uint8_t parity; /* 0=none, 1=odd, 2=even */ - const uint8_t bits; /* Number of bits (7 or 8) */ - const bool stopbits2; /* True: Configure with 2 stop bits instead of 1 */ -#ifdef CONFIG_SERIAL_IFLOWCONTROL - const bool iflow; /* input flow control (RTS) enabled */ -#endif -#ifdef CONFIG_SERIAL_OFLOWCONTROL - const bool oflow; /* output flow control (CTS) enabled */ -#endif - const uint32_t baud; /* Configured baud */ -#endif - - const uint8_t irq; /* IRQ associated with this USART */ - const uint32_t apbclock; /* PCLK 1 or 2 frequency */ - const uint32_t usartbase; /* Base address of USART registers */ - const uint32_t tx_gpio; /* U[S]ART TX GPIO pin configuration */ - const uint32_t rx_gpio; /* U[S]ART RX GPIO pin configuration */ -#ifdef CONFIG_SERIAL_IFLOWCONTROL - const uint32_t rts_gpio; /* U[S]ART RTS GPIO pin configuration */ -#endif -#ifdef CONFIG_SERIAL_OFLOWCONTROL - const uint32_t cts_gpio; /* U[S]ART CTS GPIO pin configuration */ -#endif - -#ifdef SERIAL_HAVE_RXDMA - const unsigned int rxdma_channel; /* DMA channel assigned */ -#endif - - /* RX DMA state */ - -#ifdef SERIAL_HAVE_RXDMA - DMA_HANDLE rxdma; /* currently-open receive DMA stream */ - bool rxenable; /* DMA-based reception en/disable */ - uint32_t rxdmanext; /* Next byte in the DMA buffer to be read */ - char *const rxfifo; /* Receive DMA buffer */ -#endif - -#ifdef HAVE_RS485 - const uint32_t rs485_dir_gpio; /* U[S]ART RS-485 DIR GPIO pin configuration */ - const bool rs485_dir_polarity; /* U[S]ART RS-485 DIR pin state for TX enabled */ -#endif - spinlock_t lock; /* Spinlock */ -}; - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -#ifndef CONFIG_SUPPRESS_UART_CONFIG -static void stm32serial_setformat(struct uart_dev_s *dev); -#endif -static int stm32serial_setup(struct uart_dev_s *dev); -static void stm32serial_shutdown(struct uart_dev_s *dev); -static int stm32serial_attach(struct uart_dev_s *dev); -static void stm32serial_detach(struct uart_dev_s *dev); -static int up_interrupt(int irq, void *context, void *arg); -static int stm32serial_ioctl(struct file *filep, int cmd, - unsigned long arg); -#ifndef SERIAL_HAVE_ONLY_DMA -static int stm32serial_receive(struct uart_dev_s *dev, - unsigned int *status); -static void stm32serial_rxint(struct uart_dev_s *dev, bool enable); -static bool stm32serial_rxavailable(struct uart_dev_s *dev); -#endif -#ifdef CONFIG_SERIAL_IFLOWCONTROL -static bool stm32serial_rxflowcontrol(struct uart_dev_s *dev, - unsigned int nbuffered, bool upper); -#endif -static void stm32serial_send(struct uart_dev_s *dev, int ch); -static void stm32serial_txint(struct uart_dev_s *dev, bool enable); -static bool stm32serial_txready(struct uart_dev_s *dev); - -#ifdef SERIAL_HAVE_RXDMA -static int stm32serial_dmasetup(struct uart_dev_s *dev); -static void stm32serial_dmashutdown(struct uart_dev_s *dev); -static int stm32serial_dmareceive(struct uart_dev_s *dev, - unsigned int *status); -static void stm32serial_dmarxint(struct uart_dev_s *dev, bool enable); -static bool stm32serial_dmarxavailable(struct uart_dev_s *dev); - -static void stm32serial_dmarxcallback(DMA_HANDLE handle, uint8_t status, - void *arg); -#endif - -#ifdef CONFIG_PM -static void stm32serial_pmnotify(struct pm_callback_s *cb, int domain, - enum pm_state_e pmstate); -static int stm32serial_pmprepare(struct pm_callback_s *cb, int domain, - enum pm_state_e pmstate); -#endif - -/**************************************************************************** - * Private Variables - ****************************************************************************/ - -#ifndef SERIAL_HAVE_ONLY_DMA -static const struct uart_ops_s g_uart_ops = -{ - .setup = stm32serial_setup, - .shutdown = stm32serial_shutdown, - .attach = stm32serial_attach, - .detach = stm32serial_detach, - .ioctl = stm32serial_ioctl, - .receive = stm32serial_receive, - .rxint = stm32serial_rxint, - .rxavailable = stm32serial_rxavailable, -# ifdef CONFIG_SERIAL_IFLOWCONTROL - .rxflowcontrol = stm32serial_rxflowcontrol, -# endif - .send = stm32serial_send, - .txint = stm32serial_txint, - .txready = stm32serial_txready, - .txempty = stm32serial_txready, -}; -#endif - -#ifdef SERIAL_HAVE_RXDMA -static const struct uart_ops_s g_uart_dma_ops = -{ - .setup = stm32serial_dmasetup, - .shutdown = stm32serial_dmashutdown, - .attach = stm32serial_attach, - .detach = stm32serial_detach, - .ioctl = stm32serial_ioctl, - .receive = stm32serial_dmareceive, - .rxint = stm32serial_dmarxint, - .rxavailable = stm32serial_dmarxavailable, -# ifdef CONFIG_SERIAL_IFLOWCONTROL - .rxflowcontrol = stm32serial_rxflowcontrol, -# endif - .send = stm32serial_send, - .txint = stm32serial_txint, - .txready = stm32serial_txready, - .txempty = stm32serial_txready, -}; -#endif - -/* I/O buffers */ - -#ifdef CONFIG_STM32F0L0G0_USART1 -static char g_usart1rxbuffer[CONFIG_USART1_RXBUFSIZE]; -static char g_usart1txbuffer[CONFIG_USART1_TXBUFSIZE]; -# ifdef CONFIG_USART1_RXDMA -static char g_usart1rxfifo[RXDMA_BUFFER_SIZE]; -# endif -#endif - -#ifdef CONFIG_STM32F0L0G0_USART2 -static char g_usart2rxbuffer[CONFIG_USART2_RXBUFSIZE]; -static char g_usart2txbuffer[CONFIG_USART2_TXBUFSIZE]; -# ifdef CONFIG_USART2_RXDMA -static char g_usart2rxfifo[RXDMA_BUFFER_SIZE]; -# endif -#endif - -#ifdef CONFIG_STM32F0L0G0_USART3 -static char g_usart3rxbuffer[CONFIG_USART3_RXBUFSIZE]; -static char g_usart3txbuffer[CONFIG_USART3_TXBUFSIZE]; -# ifdef CONFIG_USART3_RXDMA -static char g_usart3rxfifo[RXDMA_BUFFER_SIZE]; -# endif -#endif - -#ifdef CONFIG_STM32F0L0G0_USART4 -static char g_usart4rxbuffer[CONFIG_USART4_RXBUFSIZE]; -static char g_usart4txbuffer[CONFIG_USART4_TXBUFSIZE]; -# ifdef CONFIG_USART4_RXDMA -static char g_usart4rxfifo[RXDMA_BUFFER_SIZE]; -# endif -#endif - -#ifdef CONFIG_STM32F0L0G0_USART5 -static char g_usart5rxbuffer[CONFIG_USART5_RXBUFSIZE]; -static char g_usart5txbuffer[CONFIG_USART5_TXBUFSIZE]; -# ifdef CONFIG_USART5_RXDMA -static char g_usart5rxfifo[RXDMA_BUFFER_SIZE]; -# endif -#endif - -/* This describes the state of the STM32 USART1 ports. */ - -#ifdef CONFIG_STM32F0L0G0_USART1 -static struct stm32_serial_s g_usart1priv = -{ - .dev = - { -# if CONSOLE_USART == 1 - .isconsole = true, -# endif - .recv = - { - .size = CONFIG_USART1_RXBUFSIZE, - .buffer = g_usart1rxbuffer, - }, - .xmit = - { - .size = CONFIG_USART1_TXBUFSIZE, - .buffer = g_usart1txbuffer, - }, -# ifdef CONFIG_USART1_RXDMA - .ops = &g_uart_dma_ops, -# else - .ops = &g_uart_ops, -# endif - .priv = &g_usart1priv, - }, - - .irq = STM32_IRQ_USART1, - .parity = CONFIG_USART1_PARITY, - .bits = CONFIG_USART1_BITS, - .stopbits2 = CONFIG_USART1_2STOP, - .baud = CONFIG_USART1_BAUD, - .apbclock = STM32_PCLK2_FREQUENCY, - .usartbase = STM32_USART1_BASE, - .tx_gpio = GPIO_USART1_TX, - .rx_gpio = GPIO_USART1_RX, -# if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_USART1_OFLOWCONTROL) - .oflow = true, - .cts_gpio = GPIO_USART1_CTS, -# endif -# if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_USART1_IFLOWCONTROL) - .iflow = true, - .rts_gpio = GPIO_USART1_RTS, -# endif -# ifdef CONFIG_USART1_RXDMA - .rxdma_channel = DMAMAP_USART1_RX, - .rxfifo = g_usart1rxfifo, -# endif - -# ifdef CONFIG_USART1_RS485 - .rs485_dir_gpio = GPIO_USART1_RS485_DIR, -# if (CONFIG_USART1_RS485_DIR_POLARITY == 0) - .rs485_dir_polarity = false, -# else - .rs485_dir_polarity = true, -# endif -# endif - .lock = SP_UNLOCKED, -}; -#endif - -/* This describes the state of the STM32 USART2 port. */ - -#ifdef CONFIG_STM32F0L0G0_USART2 -static struct stm32_serial_s g_usart2priv = -{ - .dev = - { -# if CONSOLE_USART == 2 - .isconsole = true, -# endif - .recv = - { - .size = CONFIG_USART2_RXBUFSIZE, - .buffer = g_usart2rxbuffer, - }, - .xmit = - { - .size = CONFIG_USART2_TXBUFSIZE, - .buffer = g_usart2txbuffer, - }, -# ifdef CONFIG_USART2_RXDMA - .ops = &g_uart_dma_ops, -# else - .ops = &g_uart_ops, -# endif - .priv = &g_usart2priv, - }, - - .irq = STM32_IRQ_USART2, - .parity = CONFIG_USART2_PARITY, - .bits = CONFIG_USART2_BITS, - .stopbits2 = CONFIG_USART2_2STOP, - .baud = CONFIG_USART2_BAUD, - .apbclock = STM32_PCLK1_FREQUENCY, - .usartbase = STM32_USART2_BASE, - .tx_gpio = GPIO_USART2_TX, - .rx_gpio = GPIO_USART2_RX, -# if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_USART2_OFLOWCONTROL) - .oflow = true, - .cts_gpio = GPIO_USART2_CTS, -# endif -# if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_USART2_IFLOWCONTROL) - .iflow = true, - .rts_gpio = GPIO_USART2_RTS, -# endif -# ifdef CONFIG_USART2_RXDMA - .rxdma_channel = DMAMAP_USART2_RX, - .rxfifo = g_usart2rxfifo, -# endif - -# ifdef CONFIG_USART2_RS485 - .rs485_dir_gpio = GPIO_USART2_RS485_DIR, -# if (CONFIG_USART2_RS485_DIR_POLARITY == 0) - .rs485_dir_polarity = false, -# else - .rs485_dir_polarity = true, -# endif -# endif - .lock = SP_UNLOCKED, -}; -#endif - -/* This describes the state of the STM32 USART3 port. */ - -#ifdef CONFIG_STM32F0L0G0_USART3 -static struct stm32_serial_s g_usart3priv = -{ - .dev = - { -# if CONSOLE_USART == 3 - .isconsole = true, -# endif - .recv = - { - .size = CONFIG_USART3_RXBUFSIZE, - .buffer = g_usart3rxbuffer, - }, - .xmit = - { - .size = CONFIG_USART3_TXBUFSIZE, - .buffer = g_usart3txbuffer, - }, -# ifdef CONFIG_USART3_RXDMA - .ops = &g_uart_dma_ops, -# else - .ops = &g_uart_ops, -# endif - .priv = &g_usart3priv, - }, - - .irq = STM32_IRQ_USART3, - .parity = CONFIG_USART3_PARITY, - .bits = CONFIG_USART3_BITS, - .stopbits2 = CONFIG_USART3_2STOP, - .baud = CONFIG_USART3_BAUD, - .apbclock = STM32_PCLK1_FREQUENCY, - .usartbase = STM32_USART3_BASE, - .tx_gpio = GPIO_USART3_TX, - .rx_gpio = GPIO_USART3_RX, -# if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_USART3_OFLOWCONTROL) - .oflow = true, - .cts_gpio = GPIO_USART3_CTS, -# endif -# if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_USART3_IFLOWCONTROL) - .iflow = true, - .rts_gpio = GPIO_USART3_RTS, -# endif -# ifdef CONFIG_USART3_RXDMA - .rxdma_channel = DMAMAP_USART3_RX, - .rxfifo = g_usart3rxfifo, -# endif - -# ifdef CONFIG_USART3_RS485 - .rs485_dir_gpio = GPIO_USART3_RS485_DIR, -# if (CONFIG_USART3_RS485_DIR_POLARITY == 0) - .rs485_dir_polarity = false, -# else - .rs485_dir_polarity = true, -# endif -# endif - .lock = SP_UNLOCKED, -}; -#endif - -/* This describes the state of the STM32 USART4 port. */ - -#ifdef CONFIG_STM32F0L0G0_USART4 -static struct stm32_serial_s g_usart4priv = -{ - .dev = - { -# if CONSOLE_USART == 4 - .isconsole = true, -# endif - .recv = - { - .size = CONFIG_USART4_RXBUFSIZE, - .buffer = g_usart4rxbuffer, - }, - .xmit = - { - .size = CONFIG_USART4_TXBUFSIZE, - .buffer = g_usart4txbuffer, - }, -# ifdef CONFIG_USART4_RXDMA - .ops = &g_uart_dma_ops, -# else - .ops = &g_uart_ops, -# endif - .priv = &g_usart4priv, - }, - - .irq = STM32_IRQ_USART4, - .parity = CONFIG_USART4_PARITY, - .bits = CONFIG_USART4_BITS, - .stopbits2 = CONFIG_USART4_2STOP, -# ifdef CONFIG_SERIAL_IFLOWCONTROL - .iflow = false, -# endif -# ifdef CONFIG_SERIAL_OFLOWCONTROL - .oflow = false, -# endif - .baud = CONFIG_USART4_BAUD, - .apbclock = STM32_PCLK1_FREQUENCY, - .usartbase = STM32_USART4_BASE, - .tx_gpio = GPIO_USART4_TX, - .rx_gpio = GPIO_USART4_RX, -# ifdef CONFIG_SERIAL_OFLOWCONTROL - .cts_gpio = 0, -# endif -# ifdef CONFIG_SERIAL_IFLOWCONTROL - .rts_gpio = 0, -# endif -# ifdef CONFIG_USART4_RXDMA - .rxdma_channel = DMAMAP_USART4_RX, - .rxfifo = g_usart4rxfifo, -# endif - -# ifdef CONFIG_USART4_RS485 - .rs485_dir_gpio = GPIO_USART4_RS485_DIR, -# if (CONFIG_USART4_RS485_DIR_POLARITY == 0) - .rs485_dir_polarity = false, -# else - .rs485_dir_polarity = true, -# endif -# endif - .lock = SP_UNLOCKED, -}; -#endif - -/* This describes the state of the STM32 USART5 port. */ - -#ifdef CONFIG_STM32F0L0G0_USART5 -static struct stm32_serial_s g_usart5priv = -{ - .dev = - { -# if CONSOLE_USART == 5 - .isconsole = true, -# endif - .recv = - { - .size = CONFIG_USART5_RXBUFSIZE, - .buffer = g_usart5rxbuffer, - }, - .xmit = - { - .size = CONFIG_USART5_TXBUFSIZE, - .buffer = g_usart5txbuffer, - }, -# ifdef CONFIG_USART5_RXDMA - .ops = &g_uart_dma_ops, -# else - .ops = &g_uart_ops, -# endif - .priv = &g_usart5priv, - }, - - .irq = STM32_IRQ_USART5, - .parity = CONFIG_USART5_PARITY, - .bits = CONFIG_USART5_BITS, - .stopbits2 = CONFIG_USART5_2STOP, -# ifdef CONFIG_SERIAL_IFLOWCONTROL - .iflow = false, -# endif -# ifdef CONFIG_SERIAL_OFLOWCONTROL - .oflow = false, -# endif - .baud = CONFIG_USART5_BAUD, - .apbclock = STM32_PCLK1_FREQUENCY, - .usartbase = STM32_USART5_BASE, - .tx_gpio = GPIO_USART5_TX, - .rx_gpio = GPIO_USART5_RX, -# ifdef CONFIG_SERIAL_OFLOWCONTROL - .cts_gpio = 0, -# endif -# ifdef CONFIG_SERIAL_IFLOWCONTROL - .rts_gpio = 0, -# endif -# ifdef CONFIG_USART5_RXDMA - .rxdma_channel = DMAMAP_USART5_RX, - .rxfifo = g_usart5rxfifo, -# endif - -# ifdef CONFIG_USART5_RS485 - .rs485_dir_gpio = GPIO_USART5_RS485_DIR, -# if (CONFIG_USART5_RS485_DIR_POLARITY == 0) - .rs485_dir_polarity = false, -# else - .rs485_dir_polarity = true, -# endif -# endif - .lock = SP_UNLOCKED, -}; -#endif - -/* This table lets us iterate over the configured USARTs */ - -static struct stm32_serial_s * const g_uart_devs[STM32_NUSART] = -{ -#ifdef CONFIG_STM32F0L0G0_USART1 - [0] = &g_usart1priv, -#endif -#ifdef CONFIG_STM32F0L0G0_USART2 - [1] = &g_usart2priv, -#endif -#ifdef CONFIG_STM32F0L0G0_USART3 - [2] = &g_usart3priv, -#endif -#ifdef CONFIG_STM32F0L0G0_USART4 - [3] = &g_usart4priv, -#endif -#ifdef CONFIG_STM32F0L0G0_USART5 - [4] = &g_usart5priv, -#endif -}; - -#ifdef CONFIG_PM -static struct pm_callback_s g_serialcb = -{ - .notify = stm32serial_pmnotify, - .prepare = stm32serial_pmprepare, -}; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32serial_getreg - ****************************************************************************/ - -static inline uint32_t stm32serial_getreg(struct stm32_serial_s *priv, - int offset) -{ - return getreg32(priv->usartbase + offset); -} - -/**************************************************************************** - * Name: stm32serial_putreg - ****************************************************************************/ - -static inline void stm32serial_putreg(struct stm32_serial_s *priv, - int offset, uint32_t value) -{ - putreg32(value, priv->usartbase + offset); -} - -/**************************************************************************** - * Name: stm32serial_setusartint - ****************************************************************************/ - -static void stm32serial_setusartint(struct stm32_serial_s *priv, - uint16_t ie) -{ - uint32_t cr; - - /* Save the interrupt mask */ - - priv->ie = ie; - - /* And restore the interrupt state - * (see the interrupt enable/usage table above) - */ - - cr = stm32serial_getreg(priv, STM32_USART_CR1_OFFSET); - cr &= ~(USART_CR1_USED_INTS); - cr |= (ie & (USART_CR1_USED_INTS)); - stm32serial_putreg(priv, STM32_USART_CR1_OFFSET, cr); - - cr = stm32serial_getreg(priv, STM32_USART_CR3_OFFSET); - cr &= ~USART_CR3_EIE; - cr |= (ie & USART_CR3_EIE); - stm32serial_putreg(priv, STM32_USART_CR3_OFFSET, cr); -} - -/**************************************************************************** - * Name: stm32serial_restoreusartint - ****************************************************************************/ - -static void stm32serial_restoreusartint(struct stm32_serial_s *priv, - uint16_t ie) -{ - irqstate_t flags; - - flags = enter_critical_section(); - - stm32serial_setusartint(priv, ie); - - leave_critical_section(flags); -} - -/**************************************************************************** - * Name: stm32serial_disableusartint - ****************************************************************************/ - -static void stm32serial_disableusartint(struct stm32_serial_s *priv, - uint16_t *ie) -{ - irqstate_t flags; - - flags = spin_lock_irqsave(&priv->lock); - - if (ie) - { - uint32_t cr1; - uint32_t cr3; - - /* USART interrupts: - * - * Enable Status Meaning Usage - * ---------------- -------------- ----------------------- ---------- - * USART_CR1_IDLEIE USART_ISR_IDLE Idle Line Detected (not used) - * USART_CR1_RXNEIE USART_ISR_RXNE Received Data Ready - * to be Read - * " " USART_ISR_ORE Overrun Error Detected - * USART_CR1_TCIE USART_ISR_TC Transmission Complete (used only - * for RS-485) - * USART_CR1_TXEIE USART_ISR_TXE Transmit Data Register - * Empty - * USART_CR1_PEIE USART_ISR_PE Parity Error - * - * USART_CR2_LBDIE USART_ISR_LBD Break Flag (not used) - * USART_CR3_EIE USART_ISR_FE Framing Error - * " " USART_ISR_NF Noise Flag - * " " USART_ISR_ORE Overrun Error Detected - * USART_CR3_CTSIE USART_ISR_CTS CTS flag (not used) - */ - - cr1 = stm32serial_getreg(priv, STM32_USART_CR1_OFFSET); - cr3 = stm32serial_getreg(priv, STM32_USART_CR3_OFFSET); - - /* Return the current interrupt mask value for the used interrupts. - * Notice that this depends on the fact that none of the used interrupt - * enable bits overlap. - * This logic would fail if we needed the break interrupt! - */ - - *ie = (cr1 & (USART_CR1_USED_INTS)) | (cr3 & USART_CR3_EIE); - } - - /* Disable all interrupts */ - - stm32serial_setusartint(priv, 0); - - spin_unlock_irqrestore(&priv->lock, flags); -} - -/**************************************************************************** - * Name: stm32serial_dmanextrx - * - * Description: - * Returns the index into the RX FIFO where the DMA will place the next - * byte that it receives. - * - ****************************************************************************/ - -#ifdef SERIAL_HAVE_RXDMA -static int stm32serial_dmanextrx(struct stm32_serial_s *priv) -{ - size_t dmaresidual; - - dmaresidual = stm32_dmaresidual(priv->rxdma); - - return (RXDMA_BUFFER_SIZE - (int)dmaresidual); -} -#endif - -/**************************************************************************** - * Name: stm32serial_setformat - * - * Description: - * Set the serial line format and speed. - * - ****************************************************************************/ - -#ifndef CONFIG_SUPPRESS_UART_CONFIG -static void stm32serial_setformat(struct uart_dev_s *dev) -{ - struct stm32_serial_s *priv = (struct stm32_serial_s *)dev->priv; - uint32_t regval; - - /* This first implementation is for U[S]ARTs that support oversampling - * by 8 in additional to the standard oversampling by 16. - */ - - uint32_t usartdiv8; - uint32_t cr1; - uint32_t brr; - - /* In case of oversampling by 8, the equation is: - * - * baud = 2 * fCK / usartdiv8 - * usartdiv8 = 2 * fCK / baud - */ - - usartdiv8 = ((priv->apbclock << 1) + (priv->baud >> 1)) / priv->baud; - - /* Baud rate for standard USART (SPI mode included): - * - * In case of oversampling by 16, the equation is: - * baud = fCK / usartdiv16 - * usartdiv16 = fCK / baud - * = 2 * usartdiv8 - */ - - /* Use oversamply by 8 only if the divisor is small. But what is small? */ - - cr1 = stm32serial_getreg(priv, STM32_USART_CR1_OFFSET); - if (usartdiv8 > 100) - { - /* Use usartdiv16 */ - - brr = (usartdiv8 + 1) >> 1; - - /* Clear oversampling by 8 to enable oversampling by 16 */ - - cr1 &= ~USART_CR1_OVER8; - } - else - { - DEBUGASSERT(usartdiv8 >= 8); - - /* Perform mysterious operations on bits 0-3 */ - - brr = ((usartdiv8 & 0xfff0) | ((usartdiv8 & 0x000f) >> 1)); - - /* Set oversampling by 8 */ - - cr1 |= USART_CR1_OVER8; - } - - stm32serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1); - stm32serial_putreg(priv, STM32_USART_BRR_OFFSET, brr); - - /* Configure parity mode */ - - regval = stm32serial_getreg(priv, STM32_USART_CR1_OFFSET); - regval &= ~(USART_CR1_PCE | USART_CR1_PS | USART_CR1_M0 | USART_CR1_M1); - - if (priv->parity == 1) /* Odd parity */ - { - regval |= (USART_CR1_PCE | USART_CR1_PS); - } - else if (priv->parity == 2) /* Even parity */ - { - regval |= USART_CR1_PCE; - } - - /* Configure word length (parity uses one of configured bits) - * - * Default: 1 start, 8 data (no parity), n stop, OR - * 1 start, 7 data + parity, n stop - */ - - if (priv->bits == 9 || (priv->bits == 8 && priv->parity != 0)) - { - /* Select: 1 start, 8 data + parity, n stop, OR - * 1 start, 9 data (no parity), n stop. - */ - - regval |= USART_CR1_M0; - } - else if (priv->bits == 7 && priv->parity == 0) - { - /* Select: 1 start, 7 data (no parity), n stop, OR - */ - - regval |= USART_CR1_M1; - } - - /* Else Select: 1 start, 7 data + parity, n stop, OR - * 1 start, 8 data (no parity), n stop. - */ - - stm32serial_putreg(priv, STM32_USART_CR1_OFFSET, regval); - - /* Configure STOP bits */ - - regval = stm32serial_getreg(priv, STM32_USART_CR2_OFFSET); - regval &= ~(USART_CR2_STOP_MASK); - - if (priv->stopbits2) - { - regval |= USART_CR2_STOP2; - } - - stm32serial_putreg(priv, STM32_USART_CR2_OFFSET, regval); - - /* Configure hardware flow control */ - - regval = stm32serial_getreg(priv, STM32_USART_CR3_OFFSET); - regval &= ~(USART_CR3_CTSE | USART_CR3_RTSE); - -#if defined(CONFIG_SERIAL_IFLOWCONTROL) && !defined(CONFIG_STM32F0L0G0_FLOWCONTROL_BROKEN) - if (priv->iflow && (priv->rts_gpio != 0)) - { - regval |= USART_CR3_RTSE; - } -#endif - -#ifdef CONFIG_SERIAL_OFLOWCONTROL - if (priv->oflow && (priv->cts_gpio != 0)) - { - regval |= USART_CR3_CTSE; - } -#endif - - stm32serial_putreg(priv, STM32_USART_CR3_OFFSET, regval); -} -#endif /* CONFIG_SUPPRESS_UART_CONFIG */ - -/**************************************************************************** - * Name: stm32serial_setapbclock - * - * Description: - * Enable or disable APB clock for the USART peripheral - * - * Input Parameters: - * dev - A reference to the USART driver state structure - * on - Enable clock if 'on' is 'true' and disable if 'false' - * - ****************************************************************************/ - -static void stm32serial_setapbclock(struct uart_dev_s *dev, bool on) -{ - struct stm32_serial_s *priv = (struct stm32_serial_s *)dev->priv; - uint32_t rcc_en; - uint32_t regaddr; - - /* Determine which USART to configure */ - - switch (priv->usartbase) - { - default: - return; -#ifdef CONFIG_STM32F0L0G0_USART1 - case STM32_USART1_BASE: - rcc_en = RCC_APB2ENR_USART1EN; - regaddr = STM32_RCC_APB2ENR; - break; -#endif -#ifdef CONFIG_STM32F0L0G0_USART2 - case STM32_USART2_BASE: - rcc_en = RCC_APB1ENR_USART2EN; - regaddr = STM32_RCC_APB1ENR; - break; -#endif -#ifdef CONFIG_STM32F0L0G0_USART3 - case STM32_USART3_BASE: - rcc_en = RCC_APB1ENR_USART3EN; - regaddr = STM32_RCC_APB1ENR; - break; -#endif -#ifdef CONFIG_STM32F0L0G0_USART4 - case STM32_USART4_BASE: - rcc_en = RCC_APB1ENR_USART4EN; - regaddr = STM32_RCC_APB1ENR; - break; -#endif -#ifdef CONFIG_STM32F0L0G0_USART5 - case STM32_USART5_BASE: - rcc_en = RCC_APB1ENR_USART5EN; - regaddr = STM32_RCC_APB1ENR; - break; -#endif - } - - /* Enable/disable APB 1/2 clock for USART */ - - if (on) - { - modifyreg32(regaddr, 0, rcc_en); - } - else - { - modifyreg32(regaddr, rcc_en, 0); - } -} - -/**************************************************************************** - * Name: stm32serial_setup - * - * Description: - * Configure the USART baud, bits, parity, etc. This method is called the - * first time that the serial port is opened. - * - ****************************************************************************/ - -static int stm32serial_setup(struct uart_dev_s *dev) -{ - struct stm32_serial_s *priv = (struct stm32_serial_s *)dev->priv; - -#ifndef CONFIG_SUPPRESS_UART_CONFIG - uint32_t regval; - - /* Note: The logic here depends on the fact that that the USART module - * was enabled in stm32_lowsetup(). - */ - - /* Enable USART APB1/2 clock */ - - stm32serial_setapbclock(dev, true); - - /* Configure pins for USART use */ - - stm32_configgpio(priv->tx_gpio); - stm32_configgpio(priv->rx_gpio); - -#ifdef CONFIG_SERIAL_OFLOWCONTROL - if (priv->cts_gpio != 0) - { - stm32_configgpio(priv->cts_gpio); - } -#endif - -#ifdef CONFIG_SERIAL_IFLOWCONTROL - if (priv->rts_gpio != 0) - { - uint32_t config = priv->rts_gpio; - -#ifdef CONFIG_STM32F0L0G0_FLOWCONTROL_BROKEN - /* Instead of letting hw manage this pin, we will bitbang */ - - config = (config & ~GPIO_MODE_MASK) | GPIO_OUTPUT; -#endif - stm32_configgpio(config); - } -#endif - -#ifdef HAVE_RS485 - if (priv->rs485_dir_gpio != 0) - { - stm32_configgpio(priv->rs485_dir_gpio); - stm32_gpiowrite(priv->rs485_dir_gpio, !priv->rs485_dir_polarity); - } -#endif - - /* Configure CR2 - * - * Clear STOP, CLKEN, CPOL, CPHA, LBCL, and interrupt enable bits - */ - - regval = stm32serial_getreg(priv, STM32_USART_CR2_OFFSET); - regval &= ~(USART_CR2_STOP_MASK | USART_CR2_CLKEN | USART_CR2_CPOL | - USART_CR2_CPHA | USART_CR2_LBCL | USART_CR2_LBDIE); - - /* Configure STOP bits */ - - if (priv->stopbits2) - { - regval |= USART_CR2_STOP2; - } - - stm32serial_putreg(priv, STM32_USART_CR2_OFFSET, regval); - - /* Configure CR1 - * - * Clear TE, REm and all interrupt enable bits - */ - - regval = stm32serial_getreg(priv, STM32_USART_CR1_OFFSET); - regval &= ~(USART_CR1_TE | USART_CR1_RE | USART_CR1_ALLINTS); - - stm32serial_putreg(priv, STM32_USART_CR1_OFFSET, regval); - - /* Configure CR3 - * - * Clear CTSE, RTSE, and all interrupt enable bits - */ - - regval = stm32serial_getreg(priv, STM32_USART_CR3_OFFSET); - regval &= ~(USART_CR3_CTSIE | USART_CR3_CTSE | USART_CR3_RTSE | - USART_CR3_EIE); - - stm32serial_putreg(priv, STM32_USART_CR3_OFFSET, regval); - - /* Configure the USART line format and speed. */ - - stm32serial_setformat(dev); - - /* Enable Rx, Tx, and the USART */ - - regval = stm32serial_getreg(priv, STM32_USART_CR1_OFFSET); - regval |= (USART_CR1_UE | USART_CR1_TE | USART_CR1_RE); - stm32serial_putreg(priv, STM32_USART_CR1_OFFSET, regval); - -#endif /* CONFIG_SUPPRESS_UART_CONFIG */ - - /* Set up the cached interrupt enables value */ - - priv->ie = 0; - return OK; -} - -/**************************************************************************** - * Name: stm32serial_dmasetup - * - * Description: - * Configure the USART baud, bits, parity, etc. This method is called the - * first time that the serial port is opened. - * - ****************************************************************************/ - -#ifdef SERIAL_HAVE_RXDMA -static int stm32serial_dmasetup(struct uart_dev_s *dev) -{ - struct stm32_serial_s *priv = (struct stm32_serial_s *)dev->priv; - int result; - uint32_t regval; - - /* Do the basic USART setup first, unless we are the console */ - - if (!dev->isconsole) - { - result = stm32serial_setup(dev); - if (result != OK) - { - return result; - } - } - - /* Acquire the DMA channel. This should always succeed. */ - - priv->rxdma = stm32_dmachannel(priv->rxdma_channel); - -#ifdef CONFIG_SERIAL_IFLOWCONTROL - if (priv->iflow) - { - /* Configure for non-circular DMA reception into the RX FIFO */ - - stm32_dmasetup(priv->rxdma, - priv->usartbase + STM32_USART_RDR_OFFSET, - (uint32_t)priv->rxfifo, - RXDMA_BUFFER_SIZE, - SERIAL_DMA_IFLOW_CONTROL_WORD); - } - else -#endif - { - /* Configure for circular DMA reception into the RX FIFO */ - - stm32_dmasetup(priv->rxdma, - priv->usartbase + STM32_USART_RDR_OFFSET, - (uint32_t)priv->rxfifo, - RXDMA_BUFFER_SIZE, - SERIAL_DMA_CONTROL_WORD); - } - - /* Reset our DMA shadow pointer to match the address just - * programmed above. - */ - - priv->rxdmanext = 0; - - /* Enable receive DMA for the USART */ - - regval = stm32serial_getreg(priv, STM32_USART_CR3_OFFSET); - regval |= USART_CR3_DMAR; - stm32serial_putreg(priv, STM32_USART_CR3_OFFSET, regval); - -#ifdef CONFIG_SERIAL_IFLOWCONTROL - if (priv->iflow) - { - /* Start the DMA channel, and arrange for callbacks at the full point - * in the FIFO. After buffer gets full, hardware flow-control kicks - * in and DMA transfer is stopped. - */ - - stm32_dmastart(priv->rxdma, stm32serial_dmarxcallback, - (void *)priv, false); - } - else -#endif - { - /* Start the DMA channel, and arrange for callbacks at the half and - * full points in the FIFO. This ensures that we have half a FIFO - * worth of time to claim bytes before they are overwritten. - */ - - stm32_dmastart(priv->rxdma, stm32serial_dmarxcallback, - (void *)priv, true); - } - - return OK; -} -#endif - -/**************************************************************************** - * Name: stm32serial_shutdown - * - * Description: - * Disable the USART. This method is called when the serial - * port is closed - * - ****************************************************************************/ - -static void stm32serial_shutdown(struct uart_dev_s *dev) -{ - struct stm32_serial_s *priv = (struct stm32_serial_s *)dev->priv; - uint32_t regval; - - /* Disable all interrupts */ - - stm32serial_disableusartint(priv, NULL); - - /* Disable USART APB1/2 clock */ - - stm32serial_setapbclock(dev, false); - - /* Disable Rx, Tx, and the USART */ - - regval = stm32serial_getreg(priv, STM32_USART_CR1_OFFSET); - regval &= ~(USART_CR1_UE | USART_CR1_TE | USART_CR1_RE); - stm32serial_putreg(priv, STM32_USART_CR1_OFFSET, regval); - - /* Release pins. "If the serial-attached device is powered down, the TX - * pin causes back-powering, potentially confusing the device to the point - * of complete lock-up." - * - * REVISIT: Is unconfiguring the pins appropriate for all device? If not, - * then this may need to be a configuration option. - */ - - stm32_unconfiggpio(priv->tx_gpio); - stm32_unconfiggpio(priv->rx_gpio); - -#ifdef CONFIG_SERIAL_OFLOWCONTROL - if (priv->cts_gpio != 0) - { - stm32_unconfiggpio(priv->cts_gpio); - } -#endif - -#ifdef CONFIG_SERIAL_IFLOWCONTROL - if (priv->rts_gpio != 0) - { - stm32_unconfiggpio(priv->rts_gpio); - } -#endif - -#ifdef HAVE_RS485 - if (priv->rs485_dir_gpio != 0) - { - stm32_unconfiggpio(priv->rs485_dir_gpio); - } -#endif -} - -/**************************************************************************** - * Name: stm32serial_dmashutdown - * - * Description: - * Disable the USART. This method is called when the serial - * port is closed - * - ****************************************************************************/ - -#ifdef SERIAL_HAVE_RXDMA -static void stm32serial_dmashutdown(struct uart_dev_s *dev) -{ - struct stm32_serial_s *priv = (struct stm32_serial_s *)dev->priv; - - /* Perform the normal USART shutdown */ - - stm32serial_shutdown(dev); - - /* Stop the DMA channel */ - - stm32_dmastop(priv->rxdma); - - /* Release the DMA channel */ - - stm32_dmafree(priv->rxdma); - priv->rxdma = NULL; -} -#endif - -/**************************************************************************** - * Name: stm32serial_attach - * - * Description: - * Configure the USART to operation in interrupt driven mode. This method - * is called when the serial port is opened. Normally, this is just after - * the setup() method is called, however, the serial console may - * operate in a non-interrupt driven mode during the boot phase. - * - * RX and TX interrupts are not enabled when by the attach method (unless - * the hardware supports multiple levels of interrupt enabling). The RX - * and TX interrupts are not enabled until the txint() and rxint() methods - * are called. - * - ****************************************************************************/ - -static int stm32serial_attach(struct uart_dev_s *dev) -{ - struct stm32_serial_s *priv = (struct stm32_serial_s *)dev->priv; - int ret; - - /* Attach and enable the IRQ */ - - ret = irq_attach(priv->irq, up_interrupt, priv); - if (ret == OK) - { - /* Enable the interrupt (RX and TX interrupts are still disabled - * in the USART - */ - - up_enable_irq(priv->irq); - } - - return ret; -} - -/**************************************************************************** - * Name: stm32serial_detach - * - * Description: - * Detach USART interrupts. This method is called when the serial port - * is closed normally just before the shutdown method is called. - * The exception is the serial console which is never shutdown. - * - ****************************************************************************/ - -static void stm32serial_detach(struct uart_dev_s *dev) -{ - struct stm32_serial_s *priv = (struct stm32_serial_s *)dev->priv; - up_disable_irq(priv->irq); - irq_detach(priv->irq); -} - -/**************************************************************************** - * Name: up_interrupt - * - * Description: - * This is the USART interrupt handler. It will be invoked when an - * interrupt is received on the 'irq'. It should call uart_xmitchars or - * uart_recvchars to perform the appropriate data transfers. The - * interrupt handling logic must be able to map the 'arg' to the - * appropriate stm32_serial_s structure in order to call these functions. - * - ****************************************************************************/ - -static int up_interrupt(int irq, void *context, void *arg) -{ - struct stm32_serial_s *priv = (struct stm32_serial_s *)arg; - int passes; - bool handled; - - DEBUGASSERT(priv != NULL); - - /* Report serial activity to the power management logic */ - -#if defined(CONFIG_PM) && CONFIG_STM32F0L0G0_PM_SERIAL_ACTIVITY > 0 - pm_activity(PM_IDLE_DOMAIN, CONFIG_STM32F0L0G0_PM_SERIAL_ACTIVITY); -#endif - - /* Loop until there are no characters to be transferred or, - * until we have been looping for a long time. - */ - - handled = true; - for (passes = 0; passes < 256 && handled; passes++) - { - handled = false; - - /* Get the masked USART status word. */ - - priv->sr = stm32serial_getreg(priv, STM32_USART_ISR_OFFSET); - - /* USART interrupts: - * - * Enable Status Meaning Usage - * ---------------- -------------- ---------------------- ---------- - * USART_CR1_IDLEIE USART_ISR_IDLE Idle Line Detected (not used) - * USART_CR1_RXNEIE USART_ISR_RXNE Received Data Ready - * to be Read - * " " USART_ISR_ORE Overrun Error Detected - * USART_CR1_TCIE USART_ISR_TC Transmission Complete (used only - * for RS-485) - * USART_CR1_TXEIE USART_ISR_TXE Transmit Data Register - * Empty - * USART_CR1_PEIE USART_ISR_PE Parity Error - * - * USART_CR2_LBDIE USART_ISR_LBD Break Flag (not used) - * USART_CR3_EIE USART_ISR_FE Framing Error - * " " USART_ISR_NE Noise Error - * " " USART_ISR_ORE Overrun Error - * Detected - * USART_CR3_CTSIE USART_ISR_CTS CTS flag (not used) - * - * NOTE: - * Some of these status bits must be cleared by explicitly writing - * zero to the SR register: USART_ISR_CTS, USART_ISR_LBD. - * Note of those are currently being used. - */ - -#ifdef HAVE_RS485 - /* Transmission of whole buffer is over - TC is set, TXEIE is - * cleared. Note - this should be first, to have the most recent TC - * bit value from SR register - sending data affects TC, but without - * refresh we will not know that... - */ - - if ((priv->sr & USART_ISR_TC) != 0 && - (priv->ie & USART_CR1_TCIE) != 0 && - (priv->ie & USART_CR1_TXEIE) == 0) - { - stm32_gpiowrite(priv->rs485_dir_gpio, !priv->rs485_dir_polarity); - stm32serial_restoreusartint(priv, priv->ie & ~USART_CR1_TCIE); - } -#endif - - /* Handle incoming, receive bytes. */ - - if ((priv->sr & USART_ISR_RXNE) != 0 && - (priv->ie & USART_CR1_RXNEIE) != 0) - { - /* Received data ready... process incoming bytes. NOTE the check - * for RXNEIE: We cannot call uart_recvchards of RX interrupts - * are disabled. - */ - - uart_recvchars(&priv->dev); - handled = true; - } - - /* We may still have to read from the DR register to clear any pending - * error conditions. - */ - - else if ((priv->sr & - (USART_ISR_ORE | USART_ISR_NF | USART_ISR_FE)) != 0) - { - /* These errors are cleared by writing the corresponding bit to - * the interrupt clear register (ICR). - */ - - stm32serial_putreg(priv, STM32_USART_ICR_OFFSET, - (USART_ICR_NCF | USART_ICR_ORECF | - USART_ICR_FECF)); - } - - /* Handle outgoing, transmit bytes */ - - if ((priv->sr & USART_ISR_TXE) != 0 && - (priv->ie & USART_CR1_TXEIE) != 0) - { - /* Transmit data register empty ... - * process outgoing bytes - */ - - uart_xmitchars(&priv->dev); - handled = true; - } - } - - return OK; -} - -/**************************************************************************** - * Name: stm32serial_ioctl - * - * Description: - * All ioctl calls will be routed through this method - * - ****************************************************************************/ - -static int stm32serial_ioctl(struct file *filep, int cmd, - unsigned long arg) -{ -#if defined(CONFIG_SERIAL_TERMIOS) || defined(CONFIG_SERIAL_TIOCSERGSTRUCT) - struct inode *inode = filep->f_inode; - struct uart_dev_s *dev = inode->i_private; -#endif -#if defined(CONFIG_SERIAL_TERMIOS) - struct stm32_serial_s *priv = (struct stm32_serial_s *)dev->priv; -#endif - int ret = OK; - - switch (cmd) - { -#ifdef CONFIG_SERIAL_TIOCSERGSTRUCT - case TIOCSERGSTRUCT: - { - struct stm32_serial_s *user = (struct stm32_serial_s *)arg; - if (!user) - { - ret = -EINVAL; - } - else - { - memcpy(user, dev, sizeof(struct stm32_serial_s)); - } - } - break; -#endif - -#ifdef CONFIG_STM32F0L0G0_USART_SINGLEWIRE -#warning please review the potential use of ALTERNATE_FUNCTION_OPENDRAIN - case TIOCSSINGLEWIRE: - { - /* Change the TX port to be open-drain/push-pull and - * enable/disable half-duplex mode. - */ - - uint32_t cr = stm32serial_getreg(priv, STM32_USART_CR3_OFFSET); - - if ((arg & SER_SINGLEWIRE_ENABLED) != 0) - { - uint32_t gpio_val = (arg & SER_SINGLEWIRE_PUSHPULL) == - SER_SINGLEWIRE_PUSHPULL ? - GPIO_PUSHPULL : GPIO_OPENDRAIN; - gpio_val |= - (arg & SER_SINGLEWIRE_PULL_MASK) == - SER_SINGLEWIRE_PULLUP ? - GPIO_PULLUP : GPIO_FLOAT; - gpio_val |= - (arg & SER_SINGLEWIRE_PULL_MASK) == - SER_SINGLEWIRE_PULLDOWN ? - GPIO_PULLDOWN : GPIO_FLOAT; - stm32_configgpio((priv->tx_gpio & - ~(GPIO_PUPD_MASK | GPIO_OPENDRAIN)) | - gpio_val); - cr |= USART_CR3_HDSEL; - } - else - { - stm32_configgpio((priv->tx_gpio & - ~(GPIO_PUPD_MASK | GPIO_OPENDRAIN)) | - GPIO_PUSHPULL); - cr &= ~USART_CR3_HDSEL; - } - - stm32serial_putreg(priv, STM32_USART_CR3_OFFSET, cr); - } - break; -#endif - -#ifdef CONFIG_SERIAL_TERMIOS - case TCGETS: - { - struct termios *termiosp = (struct termios *)arg; - - if (!termiosp) - { - ret = -EINVAL; - break; - } - - cfsetispeed(termiosp, priv->baud); - - /* Note that since we only support 8/9 bit modes and - * there is no way to report 9-bit mode, we always claim 8. - */ - - termiosp->c_cflag = - ((priv->parity != 0) ? PARENB : 0) | - ((priv->parity == 1) ? PARODD : 0) | - ((priv->stopbits2) ? CSTOPB : 0) | -#ifdef CONFIG_SERIAL_OFLOWCONTROL - ((priv->oflow) ? CCTS_OFLOW : 0) | -#endif -#ifdef CONFIG_SERIAL_IFLOWCONTROL - ((priv->iflow) ? CRTS_IFLOW : 0) | -#endif - CS8; - - /* TODO: CRTS_IFLOW, CCTS_OFLOW */ - } - break; - - case TCSETS: - { - struct termios *termiosp = (struct termios *)arg; - - if (!termiosp) - { - ret = -EINVAL; - break; - } - - /* Perform some sanity checks before accepting any changes */ - - if (((termiosp->c_cflag & CSIZE) != CS8) -#ifdef CONFIG_SERIAL_OFLOWCONTROL - || ((termiosp->c_cflag & CCTS_OFLOW) && - (priv->cts_gpio == 0)) -#endif -#ifdef CONFIG_SERIAL_IFLOWCONTROL - || ((termiosp->c_cflag & CRTS_IFLOW) && - (priv->rts_gpio == 0)) -#endif - ) - { - ret = -EINVAL; - break; - } - - if (termiosp->c_cflag & PARENB) - { - priv->parity = (termiosp->c_cflag & PARODD) ? 1 : 2; - } - else - { - priv->parity = 0; - } - - priv->stopbits2 = (termiosp->c_cflag & CSTOPB) != 0; -#ifdef CONFIG_SERIAL_OFLOWCONTROL - priv->oflow = (termiosp->c_cflag & CCTS_OFLOW) != 0; -#endif -#ifdef CONFIG_SERIAL_IFLOWCONTROL - priv->iflow = (termiosp->c_cflag & CRTS_IFLOW) != 0; -#endif - - /* Note that since there is no way to request 9-bit mode - * and no way to support 5/6/7-bit modes, we ignore them - * all here. - */ - - /* Note that only cfgetispeed is used because we have knowledge - * that only one speed is supported. - */ - - priv->baud = cfgetispeed(termiosp); - - /* Effect the changes immediately - note that we do not implement - * TCSADRAIN / TCSAFLUSH - */ - - stm32serial_setformat(dev); - } - break; -#endif /* CONFIG_SERIAL_TERMIOS */ - -#ifdef CONFIG_STM32F0L0G0_USART_BREAKS -# ifdef CONFIG_STM32F0L0G0_SERIALBRK_BSDCOMPAT - case TIOCSBRK: /* BSD compatibility: Turn break on, unconditionally */ - { - irqstate_t flags; - uint32_t tx_break; - - flags = enter_critical_section(); - - /* Disable any further tx activity */ - - priv->ie |= USART_CR1_IE_BREAK_INPROGRESS; - - stm32serial_txint(dev, false); - - /* Configure TX as a GPIO output pin and Send a break signal */ - - tx_break = GPIO_OUTPUT | - (~(GPIO_MODE_MASK | GPIO_OUTPUT_SET) & priv->tx_gpio); - stm32_configgpio(tx_break); - - leave_critical_section(flags); - } - break; - - case TIOCCBRK: /* BSD compatibility: Turn break off, unconditionally */ - { - irqstate_t flags; - - flags = enter_critical_section(); - - /* Configure TX back to U(S)ART */ - - stm32_configgpio(priv->tx_gpio); - - priv->ie &= ~USART_CR1_IE_BREAK_INPROGRESS; - - /* Enable further tx activity */ - - stm32serial_txint(dev, true); - - leave_critical_section(flags); - } - break; -# else - case TIOCSBRK: /* No BSD compatibility: Turn break on for M bit times */ - { - uint32_t cr1; - irqstate_t flags; - - flags = enter_critical_section(); - cr1 = stm32serial_getreg(priv, STM32_USART_CR1_OFFSET); - stm32serial_putreg(priv, STM32_USART_CR1_OFFSET, - cr1 | USART_CR1_SBK); - leave_critical_section(flags); - } - break; - - case TIOCCBRK: /* No BSD compatibility: May turn off break too soon */ - { - uint32_t cr1; - irqstate_t flags; - - flags = enter_critical_section(); - cr1 = stm32serial_getreg(priv, STM32_USART_CR1_OFFSET); - stm32serial_putreg(priv, STM32_USART_CR1_OFFSET, - cr1 & ~USART_CR1_SBK); - leave_critical_section(flags); - } - break; -# endif -#endif - - default: - ret = -ENOTTY; - break; - } - - return ret; -} - -/**************************************************************************** - * Name: stm32serial_receive - * - * Description: - * Called (usually) from the interrupt level to receive one - * character from the USART. Error bits associated with the - * receipt are provided in the return 'status'. - * - ****************************************************************************/ - -#ifndef SERIAL_HAVE_ONLY_DMA -static int stm32serial_receive(struct uart_dev_s *dev, - unsigned int *status) -{ - struct stm32_serial_s *priv = (struct stm32_serial_s *)dev->priv; - uint32_t rdr; - - /* Get the Rx byte */ - - rdr = stm32serial_getreg(priv, STM32_USART_RDR_OFFSET); - - /* Get the Rx byte plux error information. Return those in status */ - - *status = priv->sr << 16 | rdr; - priv->sr = 0; - - /* Then return the actual received byte */ - - return rdr & 0xff; -} -#endif - -/**************************************************************************** - * Name: stm32serial_rxint - * - * Description: - * Call to enable or disable RX interrupts - * - ****************************************************************************/ - -#ifndef SERIAL_HAVE_ONLY_DMA -static void stm32serial_rxint(struct uart_dev_s *dev, bool enable) -{ - struct stm32_serial_s *priv = (struct stm32_serial_s *)dev->priv; - irqstate_t flags; - uint16_t ie; - - /* USART receive interrupts: - * - * Enable Status Meaning Usage - * ---------------- -------------- ----------------------- ---------- - * USART_CR1_IDLEIE USART_ISR_IDLE Idle Line Detected (not used) - * USART_CR1_RXNEIE USART_ISR_RXNE Received Data Ready - * to be Read - * " " USART_ISR_ORE Overrun Error Detected - * USART_CR1_PEIE USART_ISR_PE Parity Error - * - * USART_CR2_LBDIE USART_ISR_LBD Break Flag (not used) - * USART_CR3_EIE USART_ISR_FE Framing Error - * " " USART_ISR_NF Noise Flag - * " " USART_ISR_ORE Overrun Error Detected - */ - - flags = enter_critical_section(); - ie = priv->ie; - if (enable) - { - /* Receive an interrupt when their is anything in the Rx data - * register (or an Rx timeout occurs). - */ - -#ifndef CONFIG_SUPPRESS_SERIAL_INTS -#ifdef CONFIG_USART_ERRINTS - ie |= (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR3_EIE); -#else - ie |= USART_CR1_RXNEIE; -#endif -#endif - } - else - { - ie &= ~(USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR3_EIE); - } - - /* Then set the new interrupt state */ - - stm32serial_restoreusartint(priv, ie); - leave_critical_section(flags); -} -#endif - -/**************************************************************************** - * Name: stm32serial_rxavailable - * - * Description: - * Return true if the receive register is not empty - * - ****************************************************************************/ - -#ifndef SERIAL_HAVE_ONLY_DMA -static bool stm32serial_rxavailable(struct uart_dev_s *dev) -{ - struct stm32_serial_s *priv = (struct stm32_serial_s *)dev->priv; - return ((stm32serial_getreg(priv, - STM32_USART_ISR_OFFSET) & USART_ISR_RXNE) != - 0); -} -#endif - -/**************************************************************************** - * Name: stm32serial_rxflowcontrol - * - * Description: - * Called when Rx buffer is full (or exceeds configured watermark levels - * if CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS is defined). - * Return true if USART activated RX flow control to block more incoming - * data - * - * Input Parameters: - * dev - USART device instance - * nbuffered - the number of characters currently buffered - * (if CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS is - * not defined the value will be 0 for an empty buffer or the - * defined buffer size for a full buffer) - * upper - true indicates the upper watermark was crossed where - * false indicates the lower watermark has been crossed - * - * Returned Value: - * true if RX flow control activated. - * - ****************************************************************************/ - -#ifdef CONFIG_SERIAL_IFLOWCONTROL -static bool stm32serial_rxflowcontrol(struct uart_dev_s *dev, - unsigned int nbuffered, bool upper) -{ - struct stm32_serial_s *priv = (struct stm32_serial_s *)dev->priv; - -#if defined(CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS) && \ - defined(CONFIG_STM32F0L0G0_FLOWCONTROL_BROKEN) - if (priv->iflow && (priv->rts_gpio != 0)) - { - /* Assert/de-assert nRTS set it high resume/stop sending */ - - stm32_gpiowrite(priv->rts_gpio, upper); - return upper; - } - -#else - if (priv->iflow) - { - /* Is the RX buffer full? */ - - if (upper) - { - /* Disable Rx interrupt to prevent more data being from - * peripheral. When hardware RTS is enabled, this will - * prevent more data from coming in. - * - * This function is only called when USART recv buffer is full, - * that is: "dev->recv.head + 1 == dev->recv.tail". - * - * Logic in "uart_read" will automatically toggle Rx interrupts - * when buffer is read empty and thus we do not have to re- - * enable Rx interrupts. - */ - - uart_disablerxint(dev); - return true; - } - - /* No.. The RX buffer is empty */ - - else - { - /* We might leave Rx interrupt disabled if full recv buffer was - * read empty. Enable Rx interrupt to make sure that more input - * is received. - */ - - uart_enablerxint(dev); - } - } -#endif - - return false; -} -#endif - -/**************************************************************************** - * Name: stm32serial_dmareceive - * - * Description: - * Called (usually) from the interrupt level to receive one - * character from the USART. Error bits associated with the - * receipt are provided in the return 'status'. - * - ****************************************************************************/ - -#ifdef SERIAL_HAVE_RXDMA -static int stm32serial_dmareceive(struct uart_dev_s *dev, - unsigned int *status) -{ - struct stm32_serial_s *priv = (struct stm32_serial_s *)dev->priv; - int c = 0; - - if (stm32serial_dmanextrx(priv) != priv->rxdmanext) - { - c = priv->rxfifo[priv->rxdmanext]; - - priv->rxdmanext++; - if (priv->rxdmanext == RXDMA_BUFFER_SIZE) - { -#ifdef CONFIG_SERIAL_IFLOWCONTROL - if (priv->iflow) - { - /* RX DMA buffer full. RX paused, RTS line pulled up to prevent - * more input data from other end. - */ - } - else -#endif - { - priv->rxdmanext = 0; - } - } - } - - return c; -} -#endif - -/**************************************************************************** - * Name: stm32serial_dmareenable - * - * Description: - * Call to re-enable RX DMA. - * - ****************************************************************************/ - -#if defined(SERIAL_HAVE_RXDMA) && defined(CONFIG_SERIAL_IFLOWCONTROL) -static void stm32serial_dmareenable(struct stm32_serial_s *priv) -{ - /* Configure for non-circular DMA reception into the RX fifo */ - - stm32_dmasetup(priv->rxdma, - priv->usartbase + STM32_USART_RDR_OFFSET, - (uint32_t)priv->rxfifo, - RXDMA_BUFFER_SIZE, - SERIAL_DMA_IFLOW_CONTROL_WORD); - - /* Reset our DMA shadow pointer to match the address just - * programmed above. - */ - - priv->rxdmanext = 0; - - /* Start the DMA channel, and arrange for callbacks at the full point in - * the FIFO. After buffer gets full, hardware flow-control kicks in and - * DMA transfer is stopped. - */ - - stm32_dmastart(priv->rxdma, stm32serial_dmarxcallback, (void *)priv, - false); -} -#endif - -/**************************************************************************** - * Name: stm32serial_dmarxint - * - * Description: - * Call to enable or disable RX interrupts - * - ****************************************************************************/ - -#ifdef SERIAL_HAVE_RXDMA -static void stm32serial_dmarxint(struct uart_dev_s *dev, bool enable) -{ - struct stm32_serial_s *priv = (struct stm32_serial_s *)dev->priv; - - /* En/disable DMA reception. - * - * Note that it is not safe to check for available bytes and immediately - * pass them to uart_recvchars as that could potentially recurse back - * to us again. Instead, bytes must wait until the next up_dma_poll or - * DMA event. - */ - - priv->rxenable = enable; - -#ifdef CONFIG_SERIAL_IFLOWCONTROL - if (priv->iflow && priv->rxenable && - (priv->rxdmanext == RXDMA_BUFFER_SIZE)) - { - /* Re-enable RX DMA. */ - - stm32serial_dmareenable(priv); - } -#endif -} -#endif - -/**************************************************************************** - * Name: stm32serial_dmarxavailable - * - * Description: - * Return true if the receive register is not empty - * - ****************************************************************************/ - -#ifdef SERIAL_HAVE_RXDMA -static bool stm32serial_dmarxavailable(struct uart_dev_s *dev) -{ - struct stm32_serial_s *priv = (struct stm32_serial_s *)dev->priv; - - /* Compare our receive pointer to the current DMA pointer, if they - * do not match, then there are bytes to be received. - */ - - return (stm32serial_dmanextrx(priv) != priv->rxdmanext); -} -#endif - -/**************************************************************************** - * Name: stm32serial_send - * - * Description: - * This method will send one byte on the USART - * - ****************************************************************************/ - -static void stm32serial_send(struct uart_dev_s *dev, int ch) -{ - struct stm32_serial_s *priv = (struct stm32_serial_s *)dev->priv; - -#ifdef HAVE_RS485 - if (priv->rs485_dir_gpio != 0) - { - stm32_gpiowrite(priv->rs485_dir_gpio, priv->rs485_dir_polarity); - } -#endif - - stm32serial_putreg(priv, STM32_USART_TDR_OFFSET, (uint32_t)ch); -} - -/**************************************************************************** - * Name: stm32serial_txint - * - * Description: - * Call to enable or disable TX interrupts - * - ****************************************************************************/ - -static void stm32serial_txint(struct uart_dev_s *dev, bool enable) -{ - struct stm32_serial_s *priv = (struct stm32_serial_s *)dev->priv; - irqstate_t flags; - - /* USART transmit interrupts: - * - * Enable Status Meaning Usage - * --------------- ------------- --------------- ---------- - * USART_CR1_TCIE USART_ISR_TC Transmission (used only - * Complete for RS-485) - * USART_CR1_TXEIE USART_ISR_TXE Transmit Data - * Register Empty - * USART_CR3_CTSIE USART_ISR_CTS CTS flag (not used) - */ - - flags = enter_critical_section(); - if (enable) - { - /* Set to receive an interrupt when the TX data register - * is empty - */ - -#ifndef CONFIG_SUPPRESS_SERIAL_INTS - uint16_t ie = priv->ie | USART_CR1_TXEIE; - - /* If RS-485 is supported on this U[S]ART, then also enable the - * transmission complete interrupt. - */ - -# ifdef HAVE_RS485 - if (priv->rs485_dir_gpio != 0) - { - ie |= USART_CR1_TCIE; - } -# endif - -# ifdef CONFIG_STM32F0L0G0_SERIALBRK_BSDCOMPAT - if (priv->ie & USART_CR1_IE_BREAK_INPROGRESS) - { - leave_critical_section(flags); - return; - } -# endif - - stm32serial_restoreusartint(priv, ie); - - /* Fake a TX interrupt here by just calling uart_xmitchars() with - * interrupts disabled (note this may recurse). - */ - - uart_xmitchars(dev); -#endif - } - else - { - /* Disable the TX interrupt */ - - stm32serial_restoreusartint(priv, priv->ie & ~USART_CR1_TXEIE); - } - - leave_critical_section(flags); -} - -/**************************************************************************** - * Name: stm32serial_txready - * - * Description: - * Return true if the transmit data register is empty - * - ****************************************************************************/ - -static bool stm32serial_txready(struct uart_dev_s *dev) -{ - struct stm32_serial_s *priv = (struct stm32_serial_s *)dev->priv; - return ((stm32serial_getreg(priv, - STM32_USART_ISR_OFFSET) & USART_ISR_TXE) != 0); -} - -/**************************************************************************** - * Name: stm32serial_dmarxcallback - * - * Description: - * This function checks the current DMA state and calls the generic - * serial stack when bytes appear to be available. - * - ****************************************************************************/ - -#ifdef SERIAL_HAVE_RXDMA -static void stm32serial_dmarxcallback(DMA_HANDLE handle, uint8_t status, - void *arg) -{ - struct stm32_serial_s *priv = (struct stm32_serial_s *)arg; - - if (priv->rxenable && stm32serial_dmarxavailable(&priv->dev)) - { - uart_recvchars(&priv->dev); - -#ifdef CONFIG_SERIAL_IFLOWCONTROL - if (priv->iflow && priv->rxenable && - (priv->rxdmanext == RXDMA_BUFFER_SIZE)) - { - /* Re-enable RX DMA. */ - - stm32serial_dmareenable(priv); - } -#endif - } -} -#endif - -/**************************************************************************** - * Name: stm32serial_pmnotify - * - * Description: - * Notify the driver of new power state. This callback is called after - * all drivers have had the opportunity to prepare for the new power state. - * - * Input Parameters: - * - * cb - Returned to the driver. The driver version of the callback - * structure may include additional, driver-specific state data at - * the end of the structure. - * - * pmstate - Identifies the new PM state - * - * Returned Value: - * None - The driver already agreed to transition to the low power - * consumption state when when it returned OK to the prepare() call. - * - * - ****************************************************************************/ - -#ifdef CONFIG_PM -static void stm32serial_pmnotify(struct pm_callback_s *cb, int domain, - enum pm_state_e pmstate) -{ - switch (pmstate) - { - case (PM_NORMAL): - { - /* Logic for PM_NORMAL goes here */ - } - break; - - case (PM_IDLE): - { - /* Logic for PM_IDLE goes here */ - } - break; - - case (PM_STANDBY): - { - /* Logic for PM_STANDBY goes here */ - } - break; - - case (PM_SLEEP): - { - /* Logic for PM_SLEEP goes here */ - } - break; - - default: - - /* Should not get here */ - - break; - } -} -#endif - -/**************************************************************************** - * Name: stm32serial_pmprepare - * - * Description: - * Request the driver to prepare for a new power state. This is a warning - * that the system is about to enter into a new power state. The driver - * should begin whatever operations that may be required to enter power - * state. The driver may abort the state change mode by returning a - * non-zero value from the callback function. - * - * Input Parameters: - * - * cb - Returned to the driver. The driver version of the callback - * structure may include additional, driver-specific state data at - * the end of the structure. - * - * pmstate - Identifies the new PM state - * - * Returned Value: - * Zero - (OK) means the event was successfully processed and that the - * driver is prepared for the PM state change. - * - * Non-zero - means that the driver is not prepared to perform the tasks - * needed achieve this power setting and will cause the state - * change to be aborted. NOTE: The prepare() method will also - * be called when reverting from lower back to higher power - * consumption modes (say because another driver refused a - * lower power state change). Drivers are not permitted to - * return non-zero values when reverting back to higher power - * consumption modes! - * - ****************************************************************************/ - -#ifdef CONFIG_PM -static int stm32serial_pmprepare(struct pm_callback_s *cb, int domain, - enum pm_state_e pmstate) -{ - /* Logic to prepare for a reduced power state goes here. */ - - return OK; -} -#endif -#endif /* HAVE_USART */ -#endif /* USE_SERIALDRIVER */ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -#ifdef USE_SERIALDRIVER - -/**************************************************************************** - * Name: arm_earlyserialinit - * - * Description: - * Performs the low level USART initialization early in debug so that the - * serial console will be available during boot up. This must be called - * before stm32serial_getregit. - * - ****************************************************************************/ - -#ifdef USE_EARLYSERIALINIT -void arm_earlyserialinit(void) -{ -#ifdef HAVE_USART - unsigned i; - - /* Disable all USART interrupts */ - - for (i = 0; i < STM32_NUSART; i++) - { - if (g_uart_devs[i]) - { - stm32serial_disableusartint(g_uart_devs[i], NULL); - } - } - - /* Configure whichever one is the console */ - -#if CONSOLE_USART > 0 - stm32serial_setup(&g_uart_devs[CONSOLE_USART - 1]->dev); -#endif -#endif /* HAVE USART */ -} -#endif - -/**************************************************************************** - * Name: stm32serial_getregit - * - * Description: - * Register serial console and serial ports. This assumes - * that arm_earlyserialinit was called previously. - * - ****************************************************************************/ - -void arm_serialinit(void) -{ -#ifdef HAVE_USART - char devname[16]; - unsigned i; - unsigned minor = 0; -#ifdef CONFIG_PM - int ret; -#endif - - /* Register to receive power management callbacks */ - -#ifdef CONFIG_PM - ret = pm_register(&g_serialcb); - DEBUGASSERT(ret == OK); - UNUSED(ret); -#endif - - /* Register the console */ - -#if CONSOLE_USART > 0 - uart_register("/dev/console", &g_uart_devs[CONSOLE_USART - 1]->dev); - -#ifndef CONFIG_STM32F0L0G0_SERIAL_DISABLE_REORDERING - /* If not disabled, register the console USART to ttyS0 and exclude - * it from initializing it further down - */ - - uart_register("/dev/ttyS0", &g_uart_devs[CONSOLE_USART - 1]->dev); - minor = 1; -#endif - -#ifdef SERIAL_HAVE_CONSOLE_DMA - /* If we need to re-initialise the console to enable DMA do that here. */ - - stm32serial_dmasetup(&g_uart_devs[CONSOLE_USART - 1]->dev); -#endif -#endif /* CONSOLE_USART > 0 */ - - /* Register all remaining USARTs */ - - strlcpy(devname, "/dev/ttySx", sizeof(devname)); - - for (i = 0; i < STM32_NUSART; i++) - { - /* Don't create a device for non-configured ports. */ - - if (g_uart_devs[i] == 0) - { - continue; - } - -#ifndef CONFIG_STM32F0L0G0_SERIAL_DISABLE_REORDERING - /* Don't create a device for the console - we did that above */ - - if (g_uart_devs[i]->dev.isconsole) - { - continue; - } -#endif - - /* Register USARTs as devices in increasing order */ - - devname[9] = '0' + minor++; - uart_register(devname, &g_uart_devs[i]->dev); - } -#endif /* HAVE USART */ -} - -/**************************************************************************** - * Name: stm32serial_dmapoll - * - * Description: - * Checks receive DMA buffers for received bytes that have not accumulated - * to the point where the DMA half/full interrupt has triggered. - * - * This function should be called from a timer or other periodic context. - * - ****************************************************************************/ - -#ifdef SERIAL_HAVE_RXDMA -void stm32serial_dmapoll(void) -{ - irqstate_t flags; - - flags = enter_critical_section(); - -#ifdef CONFIG_USART1_RXDMA - if (g_usart1priv.rxdma != NULL) - { - stm32serial_dmarxcallback(g_usart1priv.rxdma, 0, &g_usart1priv); - } -#endif - -#ifdef CONFIG_USART2_RXDMA - if (g_usart2priv.rxdma != NULL) - { - stm32serial_dmarxcallback(g_usart2priv.rxdma, 0, &g_usart2priv); - } -#endif - -#ifdef CONFIG_USART3_RXDMA - if (g_usart3priv.rxdma != NULL) - { - stm32serial_dmarxcallback(g_usart3priv.rxdma, 0, &g_usart3priv); - } -#endif - -#ifdef CONFIG_USART4_RXDMA - if (g_usart4priv.rxdma != NULL) - { - stm32serial_dmarxcallback(g_usart4priv.rxdma, 0, &g_usart4priv); - } -#endif - -#ifdef CONFIG_USART5_RXDMA - if (g_usart5priv.rxdma != NULL) - { - stm32serial_dmarxcallback(g_usart5priv.rxdma, 0, &g_usart5priv); - } -#endif - - leave_critical_section(flags); -} -#endif - -/**************************************************************************** - * Name: up_putc - * - * Description: - * Provide priority, low-level access to support OS debug writes - * - ****************************************************************************/ - -void up_putc(int ch) -{ -#if CONSOLE_USART > 0 - struct stm32_serial_s *priv = g_uart_devs[CONSOLE_USART - 1]; - uint16_t ie; - - stm32serial_disableusartint(priv, &ie); - arm_lowputc(ch); - stm32serial_restoreusartint(priv, ie); -#endif -} - -#else /* USE_SERIALDRIVER */ - -/**************************************************************************** - * Name: up_putc - * - * Description: - * Provide priority, low-level access to support OS debug writes - * - ****************************************************************************/ - -void up_putc(int ch) -{ -#if CONSOLE_USART > 0 - arm_lowputc(ch); -#endif -} - -#endif /* USE_SERIALDRIVER */ diff --git a/arch/arm/src/stm32f0l0g0/stm32_serial_v2.c b/arch/arm/src/stm32f0l0g0/stm32_serial_v2.c deleted file mode 100644 index d286bb036d507..0000000000000 --- a/arch/arm/src/stm32f0l0g0/stm32_serial_v2.c +++ /dev/null @@ -1,2048 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_serial_v2.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include - -#ifdef CONFIG_SERIAL_TERMIOS -# include -#endif - -#include "arm_internal.h" -#include "chip.h" -#include "stm32_gpio.h" -#include "hardware/stm32_pinmap.h" -#include "stm32_rcc.h" -#include "stm32_uart.h" - -#include - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Some sanity checks *******************************************************/ - -/* Total number of possible serial devices */ - -#define STM32_NSERIAL (STM32_NUSART) -#define HAVE_UART - -/* Power management definitions */ - -#if defined(CONFIG_PM) && !defined(CONFIG_STM32F0L0G0_PM_SERIAL_ACTIVITY) -# define CONFIG_STM32F0L0G0_PM_SERIAL_ACTIVITY 10 -#endif - -/* Keep track if a Break was set - * - * Note: - * - * 1) This value is set in the priv->ie but never written to the control - * register. It must not collide with USART_CR1_USED_INTS or USART_CR3_EIE - * 2) USART_CR3_EIE is also carried in the up_dev_s ie member. - * - * See up_restoreusartint where the masking is done. - */ - -#ifdef CONFIG_STM32F0L0G0_SERIALBRK_BSDCOMPAT -# define USART_CR1_IE_BREAK_INPROGRESS_SHFTS 15 -# define USART_CR1_IE_BREAK_INPROGRESS (1 << USART_CR1_IE_BREAK_INPROGRESS_SHFTS) -#endif - -#ifdef USE_SERIALDRIVER -#ifdef HAVE_UART - -/* Warnings for potentially unsafe configuration combinations. */ - -#if defined(CONFIG_STM32F0L0G0_FLOWCONTROL_BROKEN) && \ - !defined(CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS) -# error "CONFIG_STM32F0L0G0_FLOWCONTROL_BROKEN requires \ - CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS to be enabled." -#endif - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -struct up_dev_s -{ - struct uart_dev_s dev; /* Generic UART device */ - uint16_t ie; /* Saved interrupt mask bits value */ - uint16_t sr; /* Saved status bits */ - - /* Has been initialized and HW is setup. */ - - bool initialized; - - /* If termios are supported, then the following fields may vary at - * runtime. - */ - -#ifdef CONFIG_SERIAL_TERMIOS - uint8_t rxftcfg; /* Rx FIFO threshold level */ - uint8_t parity; /* 0=none, 1=odd, 2=even */ - uint8_t bits; /* Number of bits (7 or 8) */ - bool stopbits2; /* True: Configure with 2 stop bits instead of 1 */ -#ifdef CONFIG_SERIAL_IFLOWCONTROL - bool iflow; /* input flow control (RTS) enabled */ -#endif -#ifdef CONFIG_SERIAL_OFLOWCONTROL - bool oflow; /* output flow control (CTS) enabled */ -#endif - uint32_t baud; /* Configured baud */ -#else - const uint8_t rxftcfg; /* Rx FIFO threshold level */ - const uint8_t parity; /* 0=none, 1=odd, 2=even */ - const uint8_t bits; /* Number of bits (7 or 8) */ - const bool stopbits2; /* True: Configure with 2 stop bits instead of 1 */ -#ifdef CONFIG_SERIAL_IFLOWCONTROL - const bool iflow; /* input flow control (RTS) enabled */ -#endif -#ifdef CONFIG_SERIAL_OFLOWCONTROL - const bool oflow; /* output flow control (CTS) enabled */ -#endif - const uint32_t baud; /* Configured baud */ -#endif - - const uint8_t irq; /* IRQ associated with this USART */ - const uint32_t apbclock; /* PCLK 1 or 2 frequency */ - const uint32_t usartbase; /* Base address of USART registers */ - const uint32_t tx_gpio; /* U[S]ART TX GPIO pin configuration */ - const uint32_t rx_gpio; /* U[S]ART RX GPIO pin configuration */ -#ifdef CONFIG_SERIAL_IFLOWCONTROL - const uint32_t rts_gpio; /* U[S]ART RTS GPIO pin configuration */ -#endif -#ifdef CONFIG_SERIAL_OFLOWCONTROL - const uint32_t cts_gpio; /* U[S]ART CTS GPIO pin configuration */ -#endif - -#ifdef HAVE_RS485 - const uint32_t rs485_dir_gpio; /* U[S]ART RS-485 DIR GPIO pin configuration */ - const bool rs485_dir_polarity; /* U[S]ART RS-485 DIR pin state for TX enabled */ -#endif - spinlock_t lock; -}; - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -static void up_set_format(struct uart_dev_s *dev); -static int up_setup(struct uart_dev_s *dev); -static void up_shutdown(struct uart_dev_s *dev); -static int up_attach(struct uart_dev_s *dev); -static void up_detach(struct uart_dev_s *dev); -static int up_interrupt(int irq, void *context, void *arg); -static int up_ioctl(struct file *filep, int cmd, unsigned long arg); -static int up_receive(struct uart_dev_s *dev, unsigned int *status); -static void up_rxint(struct uart_dev_s *dev, bool enable); -static bool up_rxavailable(struct uart_dev_s *dev); -#ifdef CONFIG_SERIAL_IFLOWCONTROL -static bool up_rxflowcontrol(struct uart_dev_s *dev, unsigned int nbuffered, - bool upper); -#endif -static void up_send(struct uart_dev_s *dev, int ch); -static void up_txint(struct uart_dev_s *dev, bool enable); -static bool up_txready(struct uart_dev_s *dev); - -#ifdef CONFIG_PM -static void up_pm_notify(struct pm_callback_s *cb, int domain, - enum pm_state_e pmstate); -static int up_pm_prepare(struct pm_callback_s *cb, int domain, - enum pm_state_e pmstate); -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -static const struct uart_ops_s g_uart_ops = -{ - .setup = up_setup, - .shutdown = up_shutdown, - .attach = up_attach, - .detach = up_detach, - .ioctl = up_ioctl, - .receive = up_receive, - .rxint = up_rxint, - .rxavailable = up_rxavailable, -#ifdef CONFIG_SERIAL_IFLOWCONTROL - .rxflowcontrol = up_rxflowcontrol, -#endif - .send = up_send, - .txint = up_txint, - .txready = up_txready, - .txempty = up_txready, -}; - -/* Receive/Transmit buffers */ - -#ifdef CONFIG_STM32F0L0G0_USART1 -static char g_usart1rxbuffer[CONFIG_USART1_RXBUFSIZE]; -static char g_usart1txbuffer[CONFIG_USART1_TXBUFSIZE]; -#endif - -#ifdef CONFIG_STM32F0L0G0_USART2 -static char g_usart2rxbuffer[CONFIG_USART2_RXBUFSIZE]; -static char g_usart2txbuffer[CONFIG_USART2_TXBUFSIZE]; -#endif - -#ifdef CONFIG_STM32F0L0G0_USART3 -static char g_usart3rxbuffer[CONFIG_USART3_RXBUFSIZE]; -static char g_usart3txbuffer[CONFIG_USART3_TXBUFSIZE]; -#endif - -#ifdef CONFIG_STM32F0L0G0_USART4 -static char g_usart4rxbuffer[CONFIG_USART4_RXBUFSIZE]; -static char g_usart4txbuffer[CONFIG_USART4_TXBUFSIZE]; -#endif - -/* This describes the state of the STM32 USART1 ports. */ - -#ifdef CONFIG_STM32F0L0G0_USART1 -static struct up_dev_s g_usart1priv = -{ - .dev = - { -#if CONSOLE_USART == 1 - .isconsole = true, -#endif - .recv = - { - .size = CONFIG_USART1_RXBUFSIZE, - .buffer = g_usart1rxbuffer, - }, - .xmit = - { - .size = CONFIG_USART1_TXBUFSIZE, - .buffer = g_usart1txbuffer, - }, - .ops = &g_uart_ops, - .priv = &g_usart1priv, - }, - - .irq = STM32_IRQ_USART1, - .rxftcfg = CONFIG_USART1_RXFIFO_THRES, - .parity = CONFIG_USART1_PARITY, - .bits = CONFIG_USART1_BITS, - .stopbits2 = CONFIG_USART1_2STOP, - .baud = CONFIG_USART1_BAUD, - .apbclock = STM32_PCLK1_FREQUENCY, - .usartbase = STM32_USART1_BASE, - .tx_gpio = GPIO_USART1_TX, - .rx_gpio = GPIO_USART1_RX, -#if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_USART1_OFLOWCONTROL) - .oflow = true, - .cts_gpio = GPIO_USART1_CTS, -#endif -#if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_USART1_IFLOWCONTROL) - .iflow = true, - .rts_gpio = GPIO_USART1_RTS, -#endif - -#ifdef CONFIG_USART1_RS485 - .rs485_dir_gpio = GPIO_USART1_RS485_DIR, -# if (CONFIG_USART1_RS485_DIR_POLARITY == 0) - .rs485_dir_polarity = false, -# else - .rs485_dir_polarity = true, -# endif -#endif - .lock = SP_UNLOCKED, -}; -#endif - -/* This describes the state of the STM32 USART2 port. */ - -#ifdef CONFIG_STM32F0L0G0_USART2 -static struct up_dev_s g_usart2priv = -{ - .dev = - { -#if CONSOLE_USART == 2 - .isconsole = true, -#endif - .recv = - { - .size = CONFIG_USART2_RXBUFSIZE, - .buffer = g_usart2rxbuffer, - }, - .xmit = - { - .size = CONFIG_USART2_TXBUFSIZE, - .buffer = g_usart2txbuffer, - }, - .ops = &g_uart_ops, - .priv = &g_usart2priv, - }, - - .irq = STM32_IRQ_USART2, - .rxftcfg = CONFIG_USART2_RXFIFO_THRES, - .parity = CONFIG_USART2_PARITY, - .bits = CONFIG_USART2_BITS, - .stopbits2 = CONFIG_USART2_2STOP, - .baud = CONFIG_USART2_BAUD, - .apbclock = STM32_PCLK1_FREQUENCY, - .usartbase = STM32_USART2_BASE, - .tx_gpio = GPIO_USART2_TX, - .rx_gpio = GPIO_USART2_RX, -#if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_USART2_OFLOWCONTROL) - .oflow = true, - .cts_gpio = GPIO_USART2_CTS, -#endif -#if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_USART2_IFLOWCONTROL) - .iflow = true, - .rts_gpio = GPIO_USART2_RTS, -#endif - -#ifdef CONFIG_USART2_RS485 - .rs485_dir_gpio = GPIO_USART2_RS485_DIR, -# if (CONFIG_USART2_RS485_DIR_POLARITY == 0) - .rs485_dir_polarity = false, -# else - .rs485_dir_polarity = true, -# endif -#endif - .lock = SP_UNLOCKED, -}; -#endif - -/* This describes the state of the STM32 USART3 port. */ - -#ifdef CONFIG_STM32F0L0G0_USART3 -static struct up_dev_s g_usart3priv = -{ - .dev = - { -#if CONSOLE_USART == 3 - .isconsole = true, -#endif - .recv = - { - .size = CONFIG_USART3_RXBUFSIZE, - .buffer = g_usart3rxbuffer, - }, - .xmit = - { - .size = CONFIG_USART3_TXBUFSIZE, - .buffer = g_usart3txbuffer, - }, - .ops = &g_uart_ops, - .priv = &g_usart3priv, - }, - - .irq = STM32_IRQ_USART3, - .rxftcfg = 0, /* No FIFO */ - .parity = CONFIG_USART3_PARITY, - .bits = CONFIG_USART3_BITS, - .stopbits2 = CONFIG_USART3_2STOP, - .baud = CONFIG_USART3_BAUD, - .apbclock = STM32_PCLK1_FREQUENCY, - .usartbase = STM32_USART3_BASE, - .tx_gpio = GPIO_USART3_TX, - .rx_gpio = GPIO_USART3_RX, -#if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_USART3_OFLOWCONTROL) - .oflow = true, - .cts_gpio = GPIO_USART3_CTS, -#endif -#if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_USART3_IFLOWCONTROL) - .iflow = true, - .rts_gpio = GPIO_USART3_RTS, -#endif - -#ifdef CONFIG_USART3_RS485 - .rs485_dir_gpio = GPIO_USART3_RS485_DIR, -# if (CONFIG_USART3_RS485_DIR_POLARITY == 0) - .rs485_dir_polarity = false, -# else - .rs485_dir_polarity = true, -# endif -#endif - .lock = SP_UNLOCKED, -}; -#endif - -/* This describes the state of the STM32 USART4 port. */ - -#ifdef CONFIG_STM32F0L0G0_USART4 -static struct up_dev_s g_usart4priv = -{ - .dev = - { -#if CONSOLE_USART == 4 - .isconsole = true, -#endif - .recv = - { - .size = CONFIG_USART4_RXBUFSIZE, - .buffer = g_usart4rxbuffer, - }, - .xmit = - { - .size = CONFIG_USART4_TXBUFSIZE, - .buffer = g_usart4txbuffer, - }, - .ops = &g_uart_ops, - .priv = &g_usart4priv, - }, - - .irq = STM32_IRQ_USART4, - .rxftcfg = 0, /* No FIFO */ - .parity = CONFIG_USART4_PARITY, - .bits = CONFIG_USART4_BITS, - .stopbits2 = CONFIG_USART4_2STOP, - .baud = CONFIG_USART4_BAUD, - .apbclock = STM32_PCLK1_FREQUENCY, - .usartbase = STM32_USART4_BASE, - .tx_gpio = GPIO_USART4_TX, - .rx_gpio = GPIO_USART4_RX, -#if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_USART4_OFLOWCONTROL) - .oflow = true, - .cts_gpio = GPIO_USART4_CTS, -#endif -#if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_USART4_IFLOWCONTROL) - .iflow = true, - .rts_gpio = GPIO_USART4_RTS, -#endif - -#ifdef CONFIG_USART4_RS485 - .rs485_dir_gpio = GPIO_USART4_RS485_DIR, -# if (CONFIG_USART4_RS485_DIR_POLARITY == 0) - .rs485_dir_polarity = false, -# else - .rs485_dir_polarity = true, -# endif -#endif - .lock = SP_UNLOCKED, -}; -#endif - -/* This table lets us iterate over the configured USARTs */ - -static struct up_dev_s * const g_uart_devs[STM32_NSERIAL] = -{ -#ifdef CONFIG_STM32F0L0G0_USART1 - [0] = &g_usart1priv, -#endif -#ifdef CONFIG_STM32F0L0G0_USART2 - [1] = &g_usart2priv, -#endif -#ifdef CONFIG_STM32F0L0G0_USART3 - [2] = &g_usart3priv, -#endif -#ifdef CONFIG_STM32F0L0G0_USART4 - [3] = &g_usart4priv -#endif -}; - -#ifdef CONFIG_PM -static struct pm_callback_s g_serialcb = -{ - .notify = up_pm_notify, - .prepare = up_pm_prepare, -}; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: up_serialin - ****************************************************************************/ - -static inline uint32_t up_serialin(struct up_dev_s *priv, int offset) -{ - return getreg32(priv->usartbase + offset); -} - -/**************************************************************************** - * Name: up_serialout - ****************************************************************************/ - -static inline void up_serialout(struct up_dev_s *priv, - int offset, uint32_t value) -{ - putreg32(value, priv->usartbase + offset); -} - -/**************************************************************************** - * Name: up_setusartint - ****************************************************************************/ - -static inline void up_setusartint(struct up_dev_s *priv, uint16_t ie) -{ - uint32_t cr; - - /* Save the interrupt mask */ - - priv->ie = ie; - - /* And restore the interrupt state - * (see the interrupt enable/usage table above) - */ - - cr = up_serialin(priv, STM32_USART_CR1_OFFSET); - cr &= ~(USART_CR1_USED_INTS); - cr |= (ie & (USART_CR1_USED_INTS)); - up_serialout(priv, STM32_USART_CR1_OFFSET, cr); - - cr = up_serialin(priv, STM32_USART_CR3_OFFSET); - cr &= ~USART_CR3_EIE; - cr |= (ie & USART_CR3_EIE); - up_serialout(priv, STM32_USART_CR3_OFFSET, cr); -} - -/**************************************************************************** - * Name: up_restoreusartint - ****************************************************************************/ - -static void up_restoreusartint(struct up_dev_s *priv, uint16_t ie) -{ - irqstate_t flags; - - flags = spin_lock_irqsave(&priv->lock); - - up_setusartint(priv, ie); - - spin_unlock_irqrestore(&priv->lock, flags); -} - -/**************************************************************************** - * Name: up_disableusartint - ****************************************************************************/ - -static void up_disableusartint(struct up_dev_s *priv, uint16_t *ie) -{ - irqstate_t flags; - - flags = spin_lock_irqsave(&priv->lock); - - if (ie) - { - uint32_t cr1; - uint32_t cr3; - - /* USART interrupts: - * - * Enable Status Meaning Usage - * ---------------- -------------- ----------------------- ---------- - * USART_CR1_IDLEIE USART_ISR_IDLE Idle Line Detected (not used) - * USART_CR1_RXNEIE USART_ISR_RXNE Received Data Ready - * to be Read - * " " USART_ISR_ORE Overrun Error Detected - * USART_CR1_TCIE USART_ISR_TC Transmission Complete (used only - * for RS-485) - * USART_CR1_TXEIE USART_ISR_TXE Transmit Data Register - * Empty - * USART_CR1_PEIE USART_ISR_PE Parity Error - * - * USART_CR2_LBDIE USART_ISR_LBD Break Flag (not used) - * USART_CR3_EIE USART_ISR_FE Framing Error - * " " USART_ISR_NF Noise Error - * " " USART_ISR_ORE Overrun Error Detected - * USART_CR3_CTSIE USART_ISR_CTS CTS flag (not used) - */ - - cr1 = up_serialin(priv, STM32_USART_CR1_OFFSET); - cr3 = up_serialin(priv, STM32_USART_CR3_OFFSET); - - /* Return the current interrupt mask value for the used interrupts. - * Notice that this depends on the fact that none of the used interrupt - * enable bits overlap. - * This logic would fail if we needed the break interrupt! - */ - - *ie = (cr1 & (USART_CR1_USED_INTS)) | (cr3 & USART_CR3_EIE); - } - - /* Disable all interrupts */ - - up_setusartint(priv, 0); - - spin_unlock_irqrestore(&priv->lock, flags); -} - -/**************************************************************************** - * Name: up_set_format - * - * Description: - * Set the serial line format and speed. - * - ****************************************************************************/ - -#ifndef CONFIG_SUPPRESS_UART_CONFIG -static void up_set_format(struct uart_dev_s *dev) -{ - struct up_dev_s *priv = (struct up_dev_s *)dev->priv; - uint32_t regval; - uint32_t usartdiv8; - uint32_t cr1; - uint32_t cr1_ue; - uint32_t brr; - irqstate_t flags; - - flags = enter_critical_section(); - - /* Get the original state of UE */ - - cr1 = up_serialin(priv, STM32_USART_CR1_OFFSET); - cr1_ue = cr1 & USART_CR1_UE; - cr1 &= ~USART_CR1_UE; - - /* Disable UE as the format bits and baud rate registers can not be - * updated while UE = 1 - */ - - up_serialout(priv, STM32_USART_CR1_OFFSET, cr1); - - /* In case of oversampling by 8, the equation is: - * - * baud = 2 * fCK / usartdiv8 - * usartdiv8 = 2 * fCK / baud - */ - - usartdiv8 = ((priv->apbclock << 1) + (priv->baud >> 1)) / priv->baud; - - /* Baud rate for standard USART (SPI mode included): - * - * In case of oversampling by 16, the equation is: - * baud = fCK / usartdiv16 - * usartdiv16 = fCK / baud - * = 2 * usartdiv8 - */ - - /* Use oversamply by 8 only if the divisor is small. But what is small? */ - - if (usartdiv8 > 100) - { - /* Use usartdiv16 */ - - brr = (usartdiv8 + 1) >> 1; - - /* Clear oversampling by 8 to enable oversampling by 16 */ - - cr1 &= ~USART_CR1_OVER8; - } - else - { - DEBUGASSERT(usartdiv8 >= 8); - - /* Perform mysterious operations on bits 0-3 */ - - brr = ((usartdiv8 & 0xfff0) | ((usartdiv8 & 0x000f) >> 1)); - - /* Set oversampling by 8 */ - - cr1 |= USART_CR1_OVER8; - } - - up_serialout(priv, STM32_USART_CR1_OFFSET, cr1); - up_serialout(priv, STM32_USART_BRR_OFFSET, brr); - - /* Configure parity mode */ - - cr1 &= ~(USART_CR1_PCE | USART_CR1_PS | USART_CR1_M0 | USART_CR1_M1); - - if (priv->parity == 1) /* Odd parity */ - { - cr1 |= (USART_CR1_PCE | USART_CR1_PS); - } - else if (priv->parity == 2) /* Even parity */ - { - cr1 |= USART_CR1_PCE; - } - - /* Configure word length (parity uses one of configured bits) - * - * Default: 1 start, 8 data (no parity), n stop, OR - * 1 start, 7 data + parity, n stop - */ - - if (priv->bits == 9 || (priv->bits == 8 && priv->parity != 0)) - { - /* Select: 1 start, 8 data + parity, n stop, OR - * 1 start, 9 data (no parity), n stop. - */ - - cr1 |= USART_CR1_M0; - } - else if (priv->bits == 7 && priv->parity == 0) - { - /* Select: 1 start, 7 data (no parity), n stop, OR - */ - - cr1 |= USART_CR1_M1; - } - - /* Else Select: 1 start, 7 data + parity, n stop, OR - * 1 start, 8 data (no parity), n stop. - */ - - up_serialout(priv, STM32_USART_CR1_OFFSET, cr1); - - /* Configure STOP bits */ - - regval = up_serialin(priv, STM32_USART_CR2_OFFSET); - regval &= ~(USART_CR2_STOP_MASK); - - if (priv->stopbits2) - { - regval |= USART_CR2_STOP2; - } - - up_serialout(priv, STM32_USART_CR2_OFFSET, regval); - - /* Configure hardware flow control */ - - regval = up_serialin(priv, STM32_USART_CR3_OFFSET); - regval &= ~(USART_CR3_CTSE | USART_CR3_RTSE); - -#if defined(CONFIG_SERIAL_IFLOWCONTROL) && \ - !defined(CONFIG_STM32F0L0G0_FLOWCONTROL_BROKEN) - if (priv->iflow && (priv->rts_gpio != 0)) - { - regval |= USART_CR3_RTSE; - } -#endif - -#ifdef CONFIG_SERIAL_OFLOWCONTROL - if (priv->oflow && (priv->cts_gpio != 0)) - { - regval |= USART_CR3_CTSE; - } -#endif - - up_serialout(priv, STM32_USART_CR3_OFFSET, regval); - up_serialout(priv, STM32_USART_CR1_OFFSET, cr1 | cr1_ue); - leave_critical_section(flags); -} -#endif /* CONFIG_SUPPRESS_UART_CONFIG */ - -/**************************************************************************** - * Name: up_set_apb_clock - * - * Description: - * Enable or disable APB clock for the USART peripheral - * - * Input Parameters: - * dev - A reference to the UART driver state structure - * on - Enable clock if 'on' is 'true' and disable if 'false' - * - ****************************************************************************/ - -static void up_set_apb_clock(struct uart_dev_s *dev, bool on) -{ - struct up_dev_s *priv = (struct up_dev_s *)dev->priv; - uint32_t rcc_en; - uint32_t regaddr; - - /* Determine which USART to configure */ - - switch (priv->usartbase) - { - default: - return; -#ifdef CONFIG_STM32F0L0G0_USART1 - case STM32_USART1_BASE: - rcc_en = RCC_APB2ENR_USART1EN; - regaddr = STM32_RCC_APB2ENR; - break; -#endif -#ifdef CONFIG_STM32F0L0G0_USART2 - case STM32_USART2_BASE: - rcc_en = RCC_APB1ENR_USART2EN; - regaddr = STM32_RCC_APB1ENR; - break; -#endif -#ifdef CONFIG_STM32F0L0G0_USART3 - case STM32_USART3_BASE: - rcc_en = RCC_APB1ENR_USART3EN; - regaddr = STM32_RCC_APB1ENR; - break; -#endif -#ifdef CONFIG_STM32F0L0G0_USART4 - case STM32_USART4_BASE: - rcc_en = RCC_APB1ENR_USART4EN; - regaddr = STM32_RCC_APB1ENR; - break; -#endif - } - - /* Enable/disable APB 1/2 clock for USART */ - - if (on) - { - modifyreg32(regaddr, 0, rcc_en); - } - else - { - modifyreg32(regaddr, rcc_en, 0); - } -} - -/**************************************************************************** - * Name: up_setup - * - * Description: - * Configure the USART baud, bits, parity, etc. This method is called the - * first time that the serial port is opened. - * - ****************************************************************************/ - -static int up_setup(struct uart_dev_s *dev) -{ - struct up_dev_s *priv = (struct up_dev_s *)dev->priv; - - /* Make sure that USART is disabled */ - - up_serialout(priv, STM32_USART_CR1_OFFSET, 0); - -#ifndef CONFIG_SUPPRESS_UART_CONFIG - uint32_t regval; - - /* Note: The logic here depends on the fact that that the USART module - * was enabled in stm32_lowsetup(). - */ - - /* Enable USART APB1/2 clock */ - - up_set_apb_clock(dev, true); - - /* Configure pins for USART use */ - - stm32_configgpio(priv->tx_gpio); - stm32_configgpio(priv->rx_gpio); - -#ifdef CONFIG_SERIAL_OFLOWCONTROL - if (priv->cts_gpio != 0) - { - stm32_configgpio(priv->cts_gpio); - } -#endif - -#ifdef CONFIG_SERIAL_IFLOWCONTROL - if (priv->rts_gpio != 0) - { - uint32_t config = priv->rts_gpio; - -#ifdef CONFIG_STM32F0L0G0_FLOWCONTROL_BROKEN - /* Instead of letting hw manage this pin, we will bitbang */ - - config = (config & ~GPIO_MODE_MASK) | GPIO_OUTPUT; -#endif - stm32_configgpio(config); - } -#endif - -#ifdef HAVE_RS485 - if (priv->rs485_dir_gpio != 0) - { - stm32_configgpio(priv->rs485_dir_gpio); - stm32_gpiowrite(priv->rs485_dir_gpio, !priv->rs485_dir_polarity); - } -#endif - - /* Configure CR2 - * - * Clear STOP, CLKEN, CPOL, CPHA, LBCL, and interrupt enable bits - */ - - regval = up_serialin(priv, STM32_USART_CR2_OFFSET); - regval &= ~(USART_CR2_STOP_MASK | USART_CR2_CLKEN | USART_CR2_CPOL | - USART_CR2_CPHA | USART_CR2_LBCL | USART_CR2_LBDIE); - - /* Configure STOP bits */ - - if (priv->stopbits2) - { - regval |= USART_CR2_STOP2; - } - - up_serialout(priv, STM32_USART_CR2_OFFSET, regval); - - /* Configure CR1 - * - * Clear TE, REm and all interrupt enable bits - */ - - regval = up_serialin(priv, STM32_USART_CR1_OFFSET); - regval &= ~(USART_CR1_TE | USART_CR1_RE | USART_CR1_ALLINTS); - - up_serialout(priv, STM32_USART_CR1_OFFSET, regval); - - /* Configure CR3 - * - * Clear CTSE, RTSE, and all interrupt enable bits - */ - - regval = up_serialin(priv, STM32_USART_CR3_OFFSET); - regval &= ~(USART_CR3_CTSIE | USART_CR3_CTSE | - USART_CR3_RTSE | USART_CR3_EIE); - - /* Set Rx FIFO threshold to the configured level */ - - regval |= USART_CR3_RXFTCFG(priv->rxftcfg); - - up_serialout(priv, STM32_USART_CR3_OFFSET, regval); - - /* Configure the USART line format and speed. */ - - up_set_format(dev); - - /* Enable Rx, Tx, and the USART */ - - /* Enable FIFO */ - - regval = up_serialin(priv, STM32_USART_CR1_OFFSET); - regval |= (USART_CR1_UE | USART_CR1_TE | USART_CR1_RE); - regval |= USART_CR1_FIFOEN; - - up_serialout(priv, STM32_USART_CR1_OFFSET, regval); - -#endif /* CONFIG_SUPPRESS_UART_CONFIG */ - - /* Set up the cached interrupt enables value */ - - priv->ie = 0; - - /* Mark device as initialized. */ - - priv->initialized = true; - - return OK; -} - -/**************************************************************************** - * Name: up_shutdown - * - * Description: - * Disable the USART. This method is called when the serial - * port is closed - * - ****************************************************************************/ - -static void up_shutdown(struct uart_dev_s *dev) -{ - struct up_dev_s *priv = (struct up_dev_s *)dev->priv; - uint32_t regval; - - /* Mark device as uninitialized. */ - - priv->initialized = false; - - /* Disable all interrupts */ - - up_disableusartint(priv, NULL); - - /* Disable USART APB1/2 clock */ - - up_set_apb_clock(dev, false); - - /* Disable Rx, Tx, and the UART */ - - regval = up_serialin(priv, STM32_USART_CR1_OFFSET); - regval &= ~(USART_CR1_UE | USART_CR1_TE | USART_CR1_RE); - up_serialout(priv, STM32_USART_CR1_OFFSET, regval); - - /* Release pins. - * "If the serial-attached device is powered down, the TX pin causes - * back-powering, potentially confusing the device to the point of - * complete lock-up." - * - * REVISIT: Is unconfiguring the pins appropriate for all device? - * If not, then this may need to be a configuration option. - */ - - stm32_unconfiggpio(priv->tx_gpio); - stm32_unconfiggpio(priv->rx_gpio); - -#ifdef CONFIG_SERIAL_OFLOWCONTROL - if (priv->cts_gpio != 0) - { - stm32_unconfiggpio(priv->cts_gpio); - } -#endif - -#ifdef CONFIG_SERIAL_IFLOWCONTROL - if (priv->rts_gpio != 0) - { - stm32_unconfiggpio(priv->rts_gpio); - } -#endif - -#ifdef HAVE_RS485 - if (priv->rs485_dir_gpio != 0) - { - stm32_unconfiggpio(priv->rs485_dir_gpio); - } -#endif -} - -/**************************************************************************** - * Name: up_attach - * - * Description: - * Configure the USART to operation in interrupt driven mode. This method - * is called when the serial port is opened. Normally, this is just after - * the setup() method is called, however, the serial console may - * operate in a non-interrupt driven mode during the boot phase. - * - * RX and TX interrupts are not enabled when by the attach method (unless - * the hardware supports multiple levels of interrupt enabling). The RX - * and TX interrupts are not enabled until the txint() and rxint() methods - * are called. - * - ****************************************************************************/ - -static int up_attach(struct uart_dev_s *dev) -{ - struct up_dev_s *priv = (struct up_dev_s *)dev->priv; - int ret; - - /* Attach and enable the IRQ */ - - ret = irq_attach(priv->irq, up_interrupt, priv); - if (ret == OK) - { - /* Enable the interrupt (RX and TX interrupts are still disabled - * in the USART - */ - - up_enable_irq(priv->irq); - } - - return ret; -} - -/**************************************************************************** - * Name: up_detach - * - * Description: - * Detach USART interrupts. This method is called when the serial port is - * closed normally just before the shutdown method is called. - * The exception is the serial console which is never shutdown. - * - ****************************************************************************/ - -static void up_detach(struct uart_dev_s *dev) -{ - struct up_dev_s *priv = (struct up_dev_s *)dev->priv; - up_disable_irq(priv->irq); - irq_detach(priv->irq); -} - -/**************************************************************************** - * Name: up_interrupt - * - * Description: - * This is the USART interrupt handler. It will be invoked when an - * interrupt is received on the 'irq'. It should call uart_xmitchars or - * uart_recvchars to perform the appropriate data transfers. The - * interrupt handling logic must be able to map the 'arg' to the - * appropriate uart_dev_s structure in order to call these functions. - * - ****************************************************************************/ - -static int up_interrupt(int irq, void *context, void *arg) -{ - struct up_dev_s *priv = (struct up_dev_s *)arg; - int passes; - bool handled; - - DEBUGASSERT(priv != NULL); - - /* Report serial activity to the power management logic */ - -#if defined(CONFIG_PM) && CONFIG_STM32F0L0G0_PM_SERIAL_ACTIVITY > 0 - pm_activity(PM_IDLE_DOMAIN, CONFIG_STM32F0L0G0_PM_SERIAL_ACTIVITY); -#endif - - /* Loop until there are no characters to be transferred or, - * until we have been looping for a long time. - */ - - handled = true; - for (passes = 0; passes < 256 && handled; passes++) - { - handled = false; - - /* Get the masked USART status word. */ - - priv->sr = up_serialin(priv, STM32_USART_ISR_OFFSET); - - /* USART interrupts: - * - * Enable Status Meaning Usage - * ---------------- -------------- ----------------------- ---------- - * USART_CR1_IDLEIE USART_ISR_IDLE Idle Line Detected (not used) - * USART_CR1_RXNEIE USART_ISR_RXNE Received Data Ready - * to be Read - * " " USART_ISR_ORE Overrun Error Detected - * USART_CR1_TCIE USART_ISR_TC Transmission Complete (used only - * for RS-485) - * USART_CR1_TXEIE USART_ISR_TXE Transmit Data - * Register Empty - * USART_CR1_PEIE USART_ISR_PE Parity Error - * - * USART_CR2_LBDIE USART_ISR_LBD Break Flag (not used) - * USART_CR3_EIE USART_ISR_FE Framing Error - * " " USART_ISR_NF Noise Error - * " " USART_ISR_ORE Overrun Error Detected - * USART_CR3_CTSIE USART_ISR_CTS CTS flag (not used) - * - * NOTE: - * Some of these status bits must be cleared by explicitly writing zero - * to the SR register: USART_ISR_CTS, USART_ISR_LBD. Note of those are - * currently being used. - */ - -#ifdef HAVE_RS485 - /* Transmission of whole buffer is over - TC is set, TXEIE is cleared. - * Note - this should be first, to have the most recent TC bit value - * from SR register - sending data affects TC, but without refresh we - * will not know that... - */ - - if ((priv->sr & USART_ISR_TC) != 0 && - (priv->ie & USART_CR1_TCIE) != 0 && - (priv->ie & USART_CR1_TXEIE) == 0) - { - stm32_gpiowrite(priv->rs485_dir_gpio, !priv->rs485_dir_polarity); - up_restoreusartint(priv, priv->ie & ~USART_CR1_TCIE); - } -#endif - - /* Handle incoming, receive bytes. */ - - if ((priv->sr & USART_ISR_RXNE) != 0 && - (priv->ie & USART_CR1_RXNEIE) != 0) - { - /* Received data ready... process incoming bytes. NOTE the check - * for RXNEIE: We cannot call uart_recvchards of RX interrupts are - * disabled. - */ - - uart_recvchars(&priv->dev); - handled = true; - } - - /* We may still have to read from the DR register to clear any pending - * error conditions. - */ - - else if ((priv->sr & - (USART_ISR_ORE | USART_ISR_NE | USART_ISR_FE)) != 0) - { - /* These errors are cleared by writing the corresponding bit to the - * interrupt clear register (ICR). - */ - - up_serialout(priv, STM32_USART_ICR_OFFSET, - (USART_ICR_NCF | USART_ICR_ORECF | USART_ICR_FECF)); - } - - /* Handle outgoing, transmit bytes */ - - if ((priv->sr & USART_ISR_TXE) != 0 && - (priv->ie & USART_CR1_TXEIE) != 0) - { - /* Transmit data register empty ... process outgoing bytes */ - - uart_xmitchars(&priv->dev); - handled = true; - } - } - - return OK; -} - -/**************************************************************************** - * Name: up_ioctl - * - * Description: - * All ioctl calls will be routed through this method - * - ****************************************************************************/ - -static int up_ioctl(struct file *filep, int cmd, unsigned long arg) -{ -#if defined(CONFIG_SERIAL_TERMIOS) || defined(CONFIG_SERIAL_TIOCSERGSTRUCT) \ - || defined(CONFIG_STM32F0L0G0_USART_SINGLEWIRE) \ - || defined(CONFIG_STM32F0L0G0_SERIALBRK_BSDCOMPAT) - struct inode *inode = filep->f_inode; - struct uart_dev_s *dev = inode->i_private; -#endif -#if defined(CONFIG_SERIAL_TERMIOS) \ - || defined(CONFIG_STM32F0L0G0_USART_SINGLEWIRE) \ - || defined(CONFIG_STM32F0L0G0_SERIALBRK_BSDCOMPAT) - struct up_dev_s *priv = (struct up_dev_s *)dev->priv; -#endif - int ret = OK; - - switch (cmd) - { -#ifdef CONFIG_SERIAL_TIOCSERGSTRUCT - case TIOCSERGSTRUCT: - { - struct up_dev_s *user = (struct up_dev_s *)arg; - if (!user) - { - ret = -EINVAL; - } - else - { - memcpy(user, dev, sizeof(struct up_dev_s)); - } - } - break; -#endif - -#ifdef CONFIG_STM32F0L0G0_USART_SINGLEWIRE - case TIOCSSINGLEWIRE: - { - uint32_t cr1; - uint32_t cr1_ue; - irqstate_t flags; - - flags = enter_critical_section(); - - /* Get the original state of UE */ - - cr1 = up_serialin(priv, STM32_USART_CR1_OFFSET); - cr1_ue = cr1 & USART_CR1_UE; - cr1 &= ~USART_CR1_UE; - - /* Disable UE, HDSEL can only be written when UE=0 */ - - up_serialout(priv, STM32_USART_CR1_OFFSET, cr1); - - /* Change the TX port to be open-drain/push-pull and enable/disable - * half-duplex mode. - */ - - uint32_t cr = up_serialin(priv, STM32_USART_CR3_OFFSET); - - if ((arg & SER_SINGLEWIRE_ENABLED) != 0) - { - uint32_t gpio_val = (arg & SER_SINGLEWIRE_PUSHPULL) == - SER_SINGLEWIRE_PUSHPULL ? - GPIO_PUSHPULL : GPIO_OPENDRAIN; - gpio_val |= (arg & SER_SINGLEWIRE_PULL_MASK) == - SER_SINGLEWIRE_PULLUP ? - GPIO_PULLUP : GPIO_FLOAT; - gpio_val |= (arg & SER_SINGLEWIRE_PULL_MASK) == - SER_SINGLEWIRE_PULLDOWN ? - GPIO_PULLDOWN : GPIO_FLOAT; - stm32_configgpio((priv->tx_gpio & - ~(GPIO_PUPD_MASK | GPIO_OPENDRAIN)) | gpio_val); - cr |= USART_CR3_HDSEL; - } - else - { - stm32_configgpio((priv->tx_gpio & - ~(GPIO_PUPD_MASK | GPIO_OPENDRAIN)) | - GPIO_PUSHPULL); - cr &= ~USART_CR3_HDSEL; - } - - up_serialout(priv, STM32_USART_CR3_OFFSET, cr); - - /* Re-enable UE if appropriate */ - - up_serialout(priv, STM32_USART_CR1_OFFSET, cr1 | cr1_ue); - leave_critical_section(flags); - } - break; -#endif - -#ifdef CONFIG_SERIAL_TERMIOS - case TCGETS: - { - struct termios *termiosp = (struct termios *)arg; - - if (!termiosp) - { - ret = -EINVAL; - break; - } - - cfsetispeed(termiosp, priv->baud); - - /* Note that since we only support 8/9 bit modes and - * there is no way to report 9-bit mode, we always claim 8. - */ - - termiosp->c_cflag = - ((priv->parity != 0) ? PARENB : 0) | - ((priv->parity == 1) ? PARODD : 0) | - ((priv->stopbits2) ? CSTOPB : 0) | -#ifdef CONFIG_SERIAL_OFLOWCONTROL - ((priv->oflow) ? CCTS_OFLOW : 0) | -#endif -#ifdef CONFIG_SERIAL_IFLOWCONTROL - ((priv->iflow) ? CRTS_IFLOW : 0) | -#endif - CS8; - - /* TODO: CRTS_IFLOW, CCTS_OFLOW */ - } - break; - - case TCSETS: - { - struct termios *termiosp = (struct termios *)arg; - - if (!termiosp) - { - ret = -EINVAL; - break; - } - - /* Perform some sanity checks before accepting any changes */ - - if (((termiosp->c_cflag & CSIZE) != CS8) -#ifdef CONFIG_SERIAL_OFLOWCONTROL - || ((termiosp->c_cflag & CCTS_OFLOW) && (priv->cts_gpio == 0)) -#endif -#ifdef CONFIG_SERIAL_IFLOWCONTROL - || ((termiosp->c_cflag & CRTS_IFLOW) && (priv->rts_gpio == 0)) -#endif - ) - { - ret = -EINVAL; - break; - } - - if (termiosp->c_cflag & PARENB) - { - priv->parity = (termiosp->c_cflag & PARODD) ? 1 : 2; - } - else - { - priv->parity = 0; - } - - priv->stopbits2 = (termiosp->c_cflag & CSTOPB) != 0; -#ifdef CONFIG_SERIAL_OFLOWCONTROL - priv->oflow = (termiosp->c_cflag & CCTS_OFLOW) != 0; -#endif -#ifdef CONFIG_SERIAL_IFLOWCONTROL - priv->iflow = (termiosp->c_cflag & CRTS_IFLOW) != 0; -#endif - - /* Note that since there is no way to request 9-bit mode - * and no way to support 5/6/7-bit modes, we ignore them - * all here. - */ - - /* Note that only cfgetispeed is used because we have knowledge - * that only one speed is supported. - */ - - priv->baud = cfgetispeed(termiosp); - - /* Effect the changes immediately - note that we do not implement - * TCSADRAIN / TCSAFLUSH - */ - - up_set_format(dev); - } - break; -#endif /* CONFIG_SERIAL_TERMIOS */ - -#ifdef CONFIG_STM32F0L0G0_USART_BREAKS -# ifdef CONFIG_STM32F0L0G0_SERIALBRK_BSDCOMPAT - case TIOCSBRK: /* BSD compatibility: Turn break on, unconditionally */ - { - irqstate_t flags; - uint32_t tx_break; - - flags = enter_critical_section(); - - /* Disable any further tx activity */ - - priv->ie |= USART_CR1_IE_BREAK_INPROGRESS; - - up_txint(dev, false); - - /* Configure TX as a GPIO output pin and Send a break signal */ - - tx_break = GPIO_OUTPUT | (~(GPIO_MODE_MASK | GPIO_OUTPUT_SET) & - priv->tx_gpio); - stm32_configgpio(tx_break); - - leave_critical_section(flags); - } - break; - - case TIOCCBRK: /* BSD compatibility: Turn break off, unconditionally */ - { - irqstate_t flags; - - flags = enter_critical_section(); - - /* Configure TX back to U(S)ART */ - - stm32_configgpio(priv->tx_gpio); - - priv->ie &= ~USART_CR1_IE_BREAK_INPROGRESS; - - /* Enable further tx activity */ - - up_txint(dev, true); - - leave_critical_section(flags); - } - break; -# else - case TIOCSBRK: /* No BSD compatibility: Turn break on for M bit times */ - { - uint32_t cr1; - irqstate_t flags; - - flags = enter_critical_section(); - cr1 = up_serialin(priv, STM32_USART_CR1_OFFSET); - up_serialout(priv, STM32_USART_RQR_OFFSET, cr1 | USART_RQR_SBKRQ); - leave_critical_section(flags); - } - break; - - case TIOCCBRK: /* No BSD compatibility: HW does not support stopping a break */ - break; -# endif -#endif - - default: - ret = -ENOTTY; - break; - } - - return ret; -} - -/**************************************************************************** - * Name: up_receive - * - * Description: - * Called (usually) from the interrupt level to receive one - * character from the USART. Error bits associated with the - * receipt are provided in the return 'status'. - * - ****************************************************************************/ - -static int up_receive(struct uart_dev_s *dev, unsigned int *status) -{ - struct up_dev_s *priv = (struct up_dev_s *)dev->priv; - uint32_t rdr; - - /* Get the Rx byte */ - - rdr = up_serialin(priv, STM32_USART_RDR_OFFSET); - - /* Get the Rx byte plux error information. Return those in status */ - - *status = priv->sr << 16 | rdr; - priv->sr = 0; - - /* Then return the actual received byte */ - - return rdr & 0xff; -} - -/**************************************************************************** - * Name: up_rxint - * - * Description: - * Call to enable or disable RX interrupts - * - ****************************************************************************/ - -static void up_rxint(struct uart_dev_s *dev, bool enable) -{ - struct up_dev_s *priv = (struct up_dev_s *)dev->priv; - irqstate_t flags; - uint16_t ie; - - /* USART receive interrupts: - * - * Enable Status Meaning Usage - * ---------------- -------------- ----------------------- ---------- - * USART_CR1_IDLEIE USART_ISR_IDLE Idle Line Detected (not used) - * USART_CR1_RXNEIE USART_ISR_RXNE Received Data Ready - * to be Read - * " " USART_ISR_ORE Overrun Error Detected - * USART_CR1_PEIE USART_ISR_PE Parity Error - * - * USART_CR2_LBDIE USART_ISR_LBD Break Flag (not used) - * USART_CR3_EIE USART_ISR_FE Framing Error - * " " USART_ISR_NF Noise Error - * " " USART_ISR_ORE Overrun Error Detected - */ - - flags = enter_critical_section(); - ie = priv->ie; - if (enable) - { - /* Receive an interrupt when their is anything in the Rx data register - * (or an Rx timeout occurs). - */ - -#ifndef CONFIG_SUPPRESS_SERIAL_INTS -#ifdef CONFIG_USART_ERRINTS - ie |= (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR3_EIE); -#else - ie |= USART_CR1_RXNEIE; -#endif -#endif - } - else - { - ie &= ~(USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR3_EIE); - } - - /* Then set the new interrupt state */ - - up_restoreusartint(priv, ie); - leave_critical_section(flags); -} - -/**************************************************************************** - * Name: up_rxavailable - * - * Description: - * Return true if the receive register is not empty - * - ****************************************************************************/ - -static bool up_rxavailable(struct uart_dev_s *dev) -{ - struct up_dev_s *priv = (struct up_dev_s *)dev->priv; - return ((up_serialin(priv, STM32_USART_ISR_OFFSET) & USART_ISR_RXNE) != 0); -} - -/**************************************************************************** - * Name: up_rxflowcontrol - * - * Description: - * Called when Rx buffer is full (or exceeds configured watermark levels - * if CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS is defined). - * Return true if UART activated RX flow control to block more incoming - * data - * - * Input Parameters: - * dev - UART device instance - * nbuffered - the number of characters currently buffered - * (if CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS is - * not defined the value will be 0 for an empty buffer or the - * defined buffer size for a full buffer) - * upper - true indicates the upper watermark was crossed where - * false indicates the lower watermark has been crossed - * - * Returned Value: - * true if RX flow control activated. - * - ****************************************************************************/ - -#ifdef CONFIG_SERIAL_IFLOWCONTROL -static bool up_rxflowcontrol(struct uart_dev_s *dev, - unsigned int nbuffered, bool upper) -{ - struct up_dev_s *priv = (struct up_dev_s *)dev->priv; - -#if defined(CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS) && \ - defined(CONFIG_STM32F0L0G0_FLOWCONTROL_BROKEN) - if (priv->iflow && (priv->rts_gpio != 0)) - { - /* Assert/de-assert nRTS set it high resume/stop sending */ - - stm32_gpiowrite(priv->rts_gpio, upper); - - if (upper) - { - /* With heavy Rx traffic, RXNE might be set and data pending. - * Returning 'true' in such case would cause RXNE left unhandled - * and causing interrupt storm. Sending end might be also be slow - * to react on nRTS, and returning 'true' here would prevent - * processing that data. - * - * Therefore, return 'false' so input data is still being processed - * until sending end reacts on nRTS signal and stops sending more. - */ - - return false; - } - - return upper; - } - -#else - if (priv->iflow) - { - /* Is the RX buffer full? */ - - if (upper) - { - /* Disable Rx interrupt to prevent more data being from - * peripheral. When hardware RTS is enabled, this will - * prevent more data from coming in. - * - * This function is only called when UART recv buffer is full, - * that is: "dev->recv.head + 1 == dev->recv.tail". - * - * Logic in "uart_read" will automatically toggle Rx interrupts - * when buffer is read empty and thus we do not have to re- - * enable Rx interrupts. - */ - - uart_disablerxint(dev); - return true; - } - - /* No.. The RX buffer is empty */ - - else - { - /* We might leave Rx interrupt disabled if full recv buffer was - * read empty. Enable Rx interrupt to make sure that more input is - * received. - */ - - uart_enablerxint(dev); - } - } -#endif - - return false; -} -#endif - -/**************************************************************************** - * Name: up_send - * - * Description: - * This method will send one byte on the USART - * - ****************************************************************************/ - -static void up_send(struct uart_dev_s *dev, int ch) -{ - struct up_dev_s *priv = (struct up_dev_s *)dev->priv; - -#ifdef HAVE_RS485 - if (priv->rs485_dir_gpio != 0) - { - stm32_gpiowrite(priv->rs485_dir_gpio, priv->rs485_dir_polarity); - } -#endif - - up_serialout(priv, STM32_USART_TDR_OFFSET, (uint32_t)ch); -} - -/**************************************************************************** - * Name: up_txint - * - * Description: - * Call to enable or disable TX interrupts - * - ****************************************************************************/ - -static void up_txint(struct uart_dev_s *dev, bool enable) -{ - struct up_dev_s *priv = (struct up_dev_s *)dev->priv; - irqstate_t flags; - - /* USART transmit interrupts: - * - * Enable Status Meaning Usage - * ---------------- ------------- --------------------- ---------- - * USART_CR1_TCIE USART_ISR_TC Transmission Complete (used only - * for RS-485) - * USART_CR1_TXEIE USART_ISR_TXE Transmit Data - * Register Empty - * USART_CR3_CTSIE USART_ISR_CTS CTS flag (not used) - */ - - flags = enter_critical_section(); - if (enable) - { - /* Set to receive an interrupt when the TX data register is empty */ - -#ifndef CONFIG_SUPPRESS_SERIAL_INTS - uint16_t ie = priv->ie | USART_CR1_TXEIE; - - /* If RS-485 is supported on this U[S]ART, then also enable the - * transmission complete interrupt. - */ - -# ifdef HAVE_RS485 - if (priv->rs485_dir_gpio != 0) - { - ie |= USART_CR1_TCIE; - } -# endif - -# ifdef CONFIG_STM32_SERIALBRK_BSDCOMPAT - if (priv->ie & USART_CR1_IE_BREAK_INPROGRESS) - { - leave_critical_section(flags); - return; - } -# endif - - up_restoreusartint(priv, ie); - - /* Fake a TX interrupt here by just calling uart_xmitchars() with - * interrupts disabled (note this may recurse). - */ - - uart_xmitchars(dev); -#endif - } - else - { - /* Disable the TX interrupt */ - - up_restoreusartint(priv, priv->ie & ~USART_CR1_TXEIE); - } - - leave_critical_section(flags); -} - -/**************************************************************************** - * Name: up_txready - * - * Description: - * Return true if the transmit data register is empty - * - ****************************************************************************/ - -static bool up_txready(struct uart_dev_s *dev) -{ - struct up_dev_s *priv = (struct up_dev_s *)dev->priv; - return ((up_serialin(priv, STM32_USART_ISR_OFFSET) & USART_ISR_TXE) != 0); -} - -/**************************************************************************** - * Name: up_pm_notify - * - * Description: - * Notify the driver of new power state. This callback is called after - * all drivers have had the opportunity to prepare for the new power state. - * - * Input Parameters: - * - * cb - Returned to the driver. The driver version of the callback - * structure may include additional, driver-specific state data at - * the end of the structure. - * - * pmstate - Identifies the new PM state - * - * Returned Value: - * None - The driver already agreed to transition to the low power - * consumption state when when it returned OK to the prepare() call. - * - * - ****************************************************************************/ - -#ifdef CONFIG_PM -static void up_pm_notify(struct pm_callback_s *cb, int domain, - enum pm_state_e pmstate) -{ - switch (pmstate) - { - case (PM_NORMAL): - { - /* Logic for PM_NORMAL goes here */ - } - break; - - case (PM_IDLE): - { - /* Logic for PM_IDLE goes here */ - } - break; - - case (PM_STANDBY): - { - /* Logic for PM_STANDBY goes here */ - } - break; - - case (PM_SLEEP): - { - /* Logic for PM_SLEEP goes here */ - } - break; - - default: - - /* Should not get here */ - - break; - } -} -#endif - -/**************************************************************************** - * Name: up_pm_prepare - * - * Description: - * Request the driver to prepare for a new power state. This is a warning - * that the system is about to enter into a new power state. The driver - * should begin whatever operations that may be required to enter power - * state. The driver may abort the state change mode by returning a - * non-zero value from the callback function. - * - * Input Parameters: - * - * cb - Returned to the driver. The driver version of the callback - * structure may include additional, driver-specific state data at - * the end of the structure. - * - * pmstate - Identifies the new PM state - * - * Returned Value: - * Zero - (OK) means the event was successfully processed and that the - * driver is prepared for the PM state change. - * - * Non-zero - means that the driver is not prepared to perform the tasks - * needed achieve this power setting and will cause the state - * change to be aborted. NOTE: The prepare() method will also - * be called when reverting from lower back to higher power - * consumption modes (say because another driver refused a - * lower power state change). Drivers are not permitted to - * return non-zero values when reverting back to higher power - * consumption modes! - * - ****************************************************************************/ - -#ifdef CONFIG_PM -static int up_pm_prepare(struct pm_callback_s *cb, int domain, - enum pm_state_e pmstate) -{ - /* Logic to prepare for a reduced power state goes here. */ - - return OK; -} -#endif -#endif /* HAVE_UART */ -#endif /* USE_SERIALDRIVER */ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -#ifdef USE_SERIALDRIVER - -/**************************************************************************** - * Name: stm32_serial_get_uart - * - * Description: - * Get serial driver structure for STM32 USART - * - ****************************************************************************/ - -uart_dev_t *stm32_serial_get_uart(int uart_num) -{ - int uart_idx = uart_num - 1; - - if (uart_idx < 0 || uart_idx >= STM32_NSERIAL || !g_uart_devs[uart_idx]) - { - return NULL; - } - - if (!g_uart_devs[uart_idx]->initialized) - { - return NULL; - } - - return &g_uart_devs[uart_idx]->dev; -} - -/**************************************************************************** - * Name: arm_earlyserialinit - * - * Description: - * Performs the low level USART initialization early in debug so that the - * serial console will be available during boot up. This must be called - * before arm_serialinit. - * - ****************************************************************************/ - -#ifdef USE_EARLYSERIALINIT -void arm_earlyserialinit(void) -{ -#ifdef HAVE_UART - unsigned i; - - /* Disable all USART interrupts */ - - for (i = 0; i < STM32_NSERIAL; i++) - { - if (g_uart_devs[i]) - { - up_disableusartint(g_uart_devs[i], NULL); - } - } - - /* Configure whichever one is the console */ - -#if CONSOLE_USART > 0 - up_setup(&g_uart_devs[CONSOLE_USART - 1]->dev); -#endif -#endif /* HAVE UART */ -} -#endif - -/**************************************************************************** - * Name: arm_serialinit - * - * Description: - * Register serial console and serial ports. This assumes - * that arm_earlyserialinit was called previously. - * - ****************************************************************************/ - -void arm_serialinit(void) -{ -#ifdef HAVE_UART - char devname[16]; - unsigned i; - unsigned minor = 0; -#ifdef CONFIG_PM - int ret; -#endif - - /* Register to receive power management callbacks */ - -#ifdef CONFIG_PM - ret = pm_register(&g_serialcb); - DEBUGASSERT(ret == OK); - UNUSED(ret); -#endif - - /* Register the console */ - -#if CONSOLE_USART > 0 - uart_register("/dev/console", &g_uart_devs[CONSOLE_USART - 1]->dev); - -#ifndef CONFIG_STM32F0L0G0_SERIAL_DISABLE_REORDERING - /* If not disabled, register the console UART to ttyS0 and exclude - * it from initializing it further down - */ - - uart_register("/dev/ttyS0", &g_uart_devs[CONSOLE_USART - 1]->dev); - minor = 1; -#endif - -#endif /* CONSOLE_USART > 0 */ - - /* Register all remaining USARTs */ - - strlcpy(devname, "/dev/ttySx", sizeof(devname)); - - for (i = 0; i < STM32_NSERIAL; i++) - { - /* Don't create a device for non-configured ports. */ - - if (g_uart_devs[i] == 0) - { - continue; - } - -#ifndef CONFIG_STM32F0L0G0_SERIAL_DISABLE_REORDERING - /* Don't create a device for the console - we did that above */ - - if (g_uart_devs[i]->dev.isconsole) - { - continue; - } -#endif - - /* Register USARTs as devices in increasing order */ - - devname[9] = '0' + minor++; - uart_register(devname, &g_uart_devs[i]->dev); - } -#endif /* HAVE UART */ -} - -/**************************************************************************** - * Name: up_putc - * - * Description: - * Provide priority, low-level access to support OS debug writes - * - ****************************************************************************/ - -void up_putc(int ch) -{ -#if CONSOLE_USART > 0 - struct up_dev_s *priv = g_uart_devs[CONSOLE_USART - 1]; - uint16_t ie; - - up_disableusartint(priv, &ie); - arm_lowputc(ch); - up_restoreusartint(priv, ie); - -#endif -} - -#else /* USE_SERIALDRIVER */ - -/**************************************************************************** - * Name: up_putc - * - * Description: - * Provide priority, low-level access to support OS debug writes - * - ****************************************************************************/ - -void up_putc(int ch) -{ -#if CONSOLE_USART > 0 - arm_lowputc(ch); -#endif -} - -#endif /* USE_SERIALDRIVER */ diff --git a/arch/arm/src/stm32f0l0g0/stm32_spi.c b/arch/arm/src/stm32f0l0g0/stm32_spi.c deleted file mode 100644 index c23914442ca82..0000000000000 --- a/arch/arm/src/stm32f0l0g0/stm32_spi.c +++ /dev/null @@ -1,2134 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_spi.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status must - * be provided by board-specific logic. They are implementations of the - * select and status methods of the SPI interface defined by - * struct spi_ops_s (see include/nuttx/spi/spi.h). All other methods - * (including stm32_spibus_initialize()) are provided by common STM32 logic. - * To use this common SPI logic on your board: - * - * 1. Provide logic in stm32_board_initialize() to configure SPI chip - * select pins. - * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() functions - * in your board-specific logic. These functions will perform chip - * selection and status operations using GPIOs in the way your board is - * configured. - * 3. Add a calls to stm32_spibus_initialize() in your low level - * application initialization logic - * 4. The handle returned by stm32_spibus_initialize() may then be used to - * bind the SPI driver to higher level logic (e.g., calling - * mmcsd_spislotinitialize(), for example, will bind the SPI driver to - * the SPI MMC/SD driver). - * - ****************************************************************************/ - -/* This driver is ported from the stm32 one, which only supports 8 and 16 - * bits transfers. The STM32 family supports frame size from 4 to 16 bits, - * but we do not support that yet. For the moment, we replace uses of the - * CR1_DFF bit with a check of the CR2_DS[0..3] bits. If the value is - * SPI_CR2_DS_16BIT it means 16 bits, else 8 bits. - */ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include - -#include "arm_internal.h" -#include "chip.h" -#include "stm32.h" -#include "stm32_gpio.h" -#include "stm32_dma.h" -#include "stm32_spi.h" - -#include - -#ifdef CONFIG_STM32F0L0G0_SPI - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -/* SPI interrupts */ - -#ifdef CONFIG_STM32F0L0G0_SPI_INTERRUPTS -# error "Interrupt driven SPI not yet supported" -#endif - -/* Can't have both interrupt driven SPI and SPI DMA */ - -#if defined(CONFIG_STM32F0L0G0_SPI_INTERRUPTS) && defined(CONFIG_STM32F0L0G0_SPI_DMA) -# error "Cannot enable both interrupt mode and DMA mode for SPI" -#endif - -/* SPI DMA priority */ - -#ifdef CONFIG_STM32F0L0G0_SPI_DMA - -# if defined(CONFIG_SPI_DMAPRIO) -# define SPI_DMA_PRIO CONFIG_SPI_DMAPRIO -# else -# define SPI_DMA_PRIO DMA_CCR_PRIMED -# endif - -# if (SPI_DMA_PRIO & ~DMA_CCR_PL_MASK) != 0 -# error "Illegal value for CONFIG_SPI_DMAPRIO" -# endif - -#endif - -/* DMA channel configuration */ - -#define SPI_RXDMA16_CONFIG (SPI_DMA_PRIO|DMA_CCR_MSIZE_16BITS|DMA_CCR_PSIZE_16BITS|DMA_CCR_MINC ) -#define SPI_RXDMA8_CONFIG (SPI_DMA_PRIO|DMA_CCR_MSIZE_8BITS |DMA_CCR_PSIZE_8BITS |DMA_CCR_MINC ) -#define SPI_RXDMA16NULL_CONFIG (SPI_DMA_PRIO|DMA_CCR_MSIZE_8BITS |DMA_CCR_PSIZE_16BITS ) -#define SPI_RXDMA8NULL_CONFIG (SPI_DMA_PRIO|DMA_CCR_MSIZE_8BITS |DMA_CCR_PSIZE_8BITS ) -#define SPI_TXDMA16_CONFIG (SPI_DMA_PRIO|DMA_CCR_MSIZE_16BITS|DMA_CCR_PSIZE_16BITS|DMA_CCR_MINC|DMA_CCR_DIR) -#define SPI_TXDMA8_CONFIG (SPI_DMA_PRIO|DMA_CCR_MSIZE_8BITS |DMA_CCR_PSIZE_8BITS |DMA_CCR_MINC|DMA_CCR_DIR) -#define SPI_TXDMA16NULL_CONFIG (SPI_DMA_PRIO|DMA_CCR_MSIZE_8BITS |DMA_CCR_PSIZE_16BITS |DMA_CCR_DIR) -#define SPI_TXDMA8NULL_CONFIG (SPI_DMA_PRIO|DMA_CCR_MSIZE_8BITS |DMA_CCR_PSIZE_8BITS |DMA_CCR_DIR) - -/* SPI clocks */ - -#if defined(CONFIG_STM32F0L0G0_STM32F0) || defined(CONFIG_STM32F0L0G0_STM32L0) -# define SPI1_PCLK_FREQUENCY STM32_PCLK2_FREQUENCY -# define SPI2_PCLK_FREQUENCY STM32_PCLK1_FREQUENCY -#elif defined(CONFIG_STM32F0L0G0_STM32G0) -# define SPI1_PCLK_FREQUENCY STM32_PCLK1_FREQUENCY -# define SPI2_PCLK_FREQUENCY STM32_PCLK1_FREQUENCY -# define SPI3_PCLK_FREQUENCY STM32_PCLK1_FREQUENCY -#else -# error Unsupported family -#endif - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -enum spi_config_e -{ - FULL_DUPLEX = 0, - SIMPLEX_TX, - SIMPLEX_RX, - HALF_DUPLEX -}; - -struct stm32_spidev_s -{ - struct spi_dev_s spidev; /* Externally visible part of the SPI interface */ - uint32_t spibase; /* SPIn base address */ - uint32_t spiclock; /* Clocking for the SPI module */ -#ifdef CONFIG_STM32F0L0G0_SPI_INTERRUPTS - uint8_t spiirq; /* SPI IRQ number */ -#endif -#ifdef CONFIG_STM32F0L0G0_SPI_DMA - volatile uint8_t rxresult; /* Result of the RX DMA */ - volatile uint8_t txresult; /* Result of the RX DMA */ -#ifdef CONFIG_SPI_TRIGGER - bool defertrig; /* Flag indicating that trigger should be deferred */ - bool trigarmed; /* Flag indicating that the trigger is armed */ -#endif - uint16_t rxch; /* The RX DMA channel number */ - uint16_t txch; /* The TX DMA channel number */ - DMA_HANDLE rxdma; /* DMA channel handle for RX transfers */ - DMA_HANDLE txdma; /* DMA channel handle for TX transfers */ - sem_t rxsem; /* Wait for RX DMA to complete */ - sem_t txsem; /* Wait for TX DMA to complete */ - uint32_t txccr; /* DMA control register for TX transfers */ - uint32_t rxccr; /* DMA control register for RX transfers */ -#endif - bool initialized; /* Has SPI interface been initialized */ - mutex_t lock; /* Held while chip is selected for mutual exclusion */ - uint32_t frequency; /* Requested clock frequency */ - uint32_t actual; /* Actual clock frequency */ - uint8_t nbits; /* Width of word in bits (4 through 16) */ - uint8_t mode; /* Mode 0,1,2,3 */ -#ifdef CONFIG_PM - struct pm_callback_s pm_cb; /* PM callbacks */ -#endif - enum spi_config_e config; /* full/half duplex, simplex transmit/read only */ - bool rx_now; /* Half duplex only: receiving data now */ - bool rx_mode; /* Half duplex only: SPI_CR1_BIDIOE bit status */ -}; - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -/* Helpers */ - -static inline uint16_t spi_getreg(struct stm32_spidev_s *priv, - uint8_t offset); -static inline void spi_putreg(struct stm32_spidev_s *priv, - uint8_t offset, uint16_t value); -static inline void spi_rx_mode(struct stm32_spidev_s *priv, bool enable); -static inline uint16_t spi_readword(struct stm32_spidev_s *priv); -static inline void spi_writeword(struct stm32_spidev_s *priv, - uint16_t byte); -static inline bool spi_16bitmode(struct stm32_spidev_s *priv); - -static void spi_modifycr(uint32_t addr, struct stm32_spidev_s *priv, - uint16_t setbits, uint16_t clrbits); - -/* DMA support */ - -#ifdef CONFIG_STM32F0L0G0_SPI_DMA -static int spi_dmarxwait(struct stm32_spidev_s *priv); -static int spi_dmatxwait(struct stm32_spidev_s *priv); -static inline void spi_dmarxwakeup(struct stm32_spidev_s *priv); -static inline void spi_dmatxwakeup(struct stm32_spidev_s *priv); -static void spi_dmarxcallback(DMA_HANDLE handle, uint8_t isr, - void *arg); -static void spi_dmatxcallback(DMA_HANDLE handle, uint8_t isr, - void *arg); -static void spi_dmarxsetup(struct stm32_spidev_s *priv, - void *rxbuffer, void *rxdummy, - size_t nwords); -static void spi_dmatxsetup(struct stm32_spidev_s *priv, - const void *txbuffer, - const void *txdummy, size_t nwords); -static inline void spi_dmarxstart(struct stm32_spidev_s *priv); -static inline void spi_dmatxstart(struct stm32_spidev_s *priv); -#endif - -/* SPI methods */ - -static int spi_lock(struct spi_dev_s *dev, bool lock); -static uint32_t spi_setfrequency(struct spi_dev_s *dev, - uint32_t frequency); -static void spi_setmode(struct spi_dev_s *dev, - enum spi_mode_e mode); -static void spi_setbits(struct spi_dev_s *dev, int nbits); -#ifdef CONFIG_SPI_HWFEATURES -static int spi_hwfeatures(struct spi_dev_s *dev, - spi_hwfeatures_t features); -#endif -static uint32_t spi_send(struct spi_dev_s *dev, uint32_t wd); -static void spi_exchange(struct spi_dev_s *dev, - const void *txbuffer, void *rxbuffer, - size_t nwords); - -#ifdef CONFIG_STM32F0L0G0_SPI_DMA -static void spi_exchange_nodma(struct spi_dev_s *dev, - const void *txbuffer, void *rxbuffer, - size_t nwords); -#endif - -#ifdef CONFIG_SPI_TRIGGER -static int spi_trigger(struct spi_dev_s *dev); -#endif -#ifndef CONFIG_SPI_EXCHANGE -static void spi_sndblock(struct spi_dev_s *dev, - const void *txbuffer, size_t nwords); -static void spi_recvblock(struct spi_dev_s *dev, - void *rxbuffer, size_t nwords); -#endif - -/* Initialization */ - -static void spi_bus_initialize(struct stm32_spidev_s *priv); - -/* PM interface */ - -#ifdef CONFIG_PM -static int spi_pm_prepare(struct pm_callback_s *cb, int domain, - enum pm_state_e pmstate); -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -#ifdef CONFIG_STM32F0L0G0_SPI1 -static const struct spi_ops_s g_spi1ops = -{ - .lock = spi_lock, - .select = stm32_spi1select, - .setfrequency = spi_setfrequency, - .setmode = spi_setmode, - .setbits = spi_setbits, -#ifdef CONFIG_SPI_HWFEATURES - .hwfeatures = spi_hwfeatures, -#endif - .status = stm32_spi1status, -#ifdef CONFIG_SPI_CMDDATA - .cmddata = stm32_spi1cmddata, -#endif - .send = spi_send, -#ifdef CONFIG_SPI_EXCHANGE - .exchange = spi_exchange, -#else - .sndblock = spi_sndblock, - .recvblock = spi_recvblock, -#endif -#ifdef CONFIG_SPI_TRIGGER - .trigger = spi_trigger, -#endif -#ifdef CONFIG_SPI_CALLBACK - .registercallback = stm32_spi1register, /* Provided externally */ -#else - .registercallback = 0, /* Not implemented */ -#endif -}; - -static struct stm32_spidev_s g_spi1dev = -{ - .spidev = - { - .ops = &g_spi1ops, - }, - .spibase = STM32_SPI1_BASE, - .spiclock = SPI1_PCLK_FREQUENCY, -#ifdef CONFIG_STM32F0L0G0_SPI_INTERRUPTS - .spiirq = STM32_IRQ_SPI1, -#endif -#ifdef CONFIG_STM32F0L0G0_SPI1_DMA - /* lines must be configured in board.h */ - - .rxch = DMACHAN_SPI1_RX, - .txch = DMACHAN_SPI1_TX, - .rxsem = SEM_INITIALIZER(0), - .txsem = SEM_INITIALIZER(0), -#endif - .lock = NXMUTEX_INITIALIZER, -#ifdef CONFIG_PM - .pm_cb.prepare = spi_pm_prepare, -#endif - .config = CONFIG_STM32F0L0G0_SPI1_COMMTYPE, -}; -#endif - -#ifdef CONFIG_STM32F0L0G0_SPI2 -static const struct spi_ops_s g_spi2ops = -{ - .lock = spi_lock, - .select = stm32_spi2select, - .setfrequency = spi_setfrequency, - .setmode = spi_setmode, - .setbits = spi_setbits, -#ifdef CONFIG_SPI_HWFEATURES - .hwfeatures = spi_hwfeatures, -#endif - .status = stm32_spi2status, -#ifdef CONFIG_SPI_CMDDATA - .cmddata = stm32_spi2cmddata, -#endif - .send = spi_send, -#ifdef CONFIG_SPI_EXCHANGE - .exchange = spi_exchange, -#else - .sndblock = spi_sndblock, - .recvblock = spi_recvblock, -#endif -#ifdef CONFIG_SPI_TRIGGER - .trigger = spi_trigger, -#endif -#ifdef CONFIG_SPI_CALLBACK - .registercallback = stm32_spi2register, /* provided externally */ -#else - .registercallback = 0, /* not implemented */ -#endif -}; - -static struct stm32_spidev_s g_spi2dev = -{ - .spidev = - { - .ops = &g_spi2ops, - }, - .spibase = STM32_SPI2_BASE, - .spiclock = SPI1_PCLK_FREQUENCY, -#ifdef CONFIG_STM32F0L0G0_SPI_INTERRUPTS - .spiirq = STM32_IRQ_SPI2, -#endif -#ifdef CONFIG_STM32F0L0G0_SPI2_DMA - .rxch = DMACHAN_SPI2_RX, - .txch = DMACHAN_SPI2_TX, - .rxsem = SEM_INITIALIZER(0), - .txsem = SEM_INITIALIZER(0), -#endif - .lock = NXMUTEX_INITIALIZER, -#ifdef CONFIG_PM - .pm_cb.prepare = spi_pm_prepare, -#endif - .config = CONFIG_STM32F0L0G0_SPI2_COMMTYPE, -}; -#endif - -#ifdef CONFIG_STM32F0L0G0_SPI3 -static const struct spi_ops_s g_spi3ops = -{ - .lock = spi_lock, - .select = stm32_spi3select, - .setfrequency = spi_setfrequency, - .setmode = spi_setmode, - .setbits = spi_setbits, -#ifdef CONFIG_SPI_HWFEATURES - .hwfeatures = spi_hwfeatures, -#endif - .status = stm32_spi3status, -#ifdef CONFIG_SPI_CMDDATA - .cmddata = stm32_spi3cmddata, -#endif - .send = spi_send, -#ifdef CONFIG_SPI_EXCHANGE - .exchange = spi_exchange, -#else - .sndblock = spi_sndblock, - .recvblock = spi_recvblock, -#endif -#ifdef CONFIG_SPI_TRIGGER - .trigger = spi_trigger, -#endif -#ifdef CONFIG_SPI_CALLBACK - .registercallback = stm32_spi3register, /* provided externally */ -#else - .registercallback = 0, /* not implemented */ -#endif -}; - -static struct stm32_spidev_s g_spi3dev = -{ - .spidev = - { - .ops = &g_spi3ops, - }, - .spibase = STM32_SPI3_BASE, - .spiclock = SPI1_PCLK_FREQUENCY, -#ifdef CONFIG_STM32F0L0G0_SPI_INTERRUPTS - .spiirq = STM32_IRQ_SPI3, -#endif -#ifdef CONFIG_STM32F0L0G0_SPI3_DMA - .rxch = DMACHAN_SPI3_RX, - .txch = DMACHAN_SPI3_TX, - .rxsem = SEM_INITIALIZER(0), - .txsem = SEM_INITIALIZER(0), -#endif - .lock = NXMUTEX_INITIALIZER, -#ifdef CONFIG_PM - .pm_cb.prepare = spi_pm_prepare, -#endif - .config = CONFIG_STM32F0L0G0_SPI3_COMMTYPE, -}; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: spi_getreg - * - * Description: - * Get the contents of the SPI register at offset - * - * Input Parameters: - * priv - private SPI device structure - * offset - offset to the register of interest - * - * Returned Value: - * The contents of the 16-bit register - * - ****************************************************************************/ - -static inline uint16_t spi_getreg(struct stm32_spidev_s *priv, - uint8_t offset) -{ - return getreg16(priv->spibase + offset); -} - -/**************************************************************************** - * Name: spi_putreg - * - * Description: - * Write a 16-bit value to the SPI register at offset - * - * Input Parameters: - * priv - private SPI device structure - * offset - offset to the register of interest - * value - the 16-bit value to be written - * - * Returned Value: - * The contents of the 16-bit register - * - ****************************************************************************/ - -static inline void spi_putreg(struct stm32_spidev_s *priv, - uint8_t offset, uint16_t value) -{ - putreg16(value, priv->spibase + offset); -} - -/**************************************************************************** - * Name: spi_rx_mode - * - * Description: - * Activate SPI RX or SPI TX for the half-duplex mode - * - ****************************************************************************/ - -static inline void spi_rx_mode(struct stm32_spidev_s *priv, bool enable) -{ - if (enable) - { - /* Enable RX */ - - if (!priv->rx_mode) - { - /* Disable SPI */ - - spi_modifycr(STM32_SPI_CR1_OFFSET, priv, 0, SPI_CR1_SPE); - - /* Disable output for half-duplex mode - SPI starts to - * automatically output clocks. - */ - - spi_modifycr(STM32_SPI_CR1_OFFSET, priv, 0, SPI_CR1_BIDIOE); - - /* Enable SPI */ - - spi_modifycr(STM32_SPI_CR1_OFFSET, priv, SPI_CR1_SPE, 0); - - priv->rx_mode = true; - } - } - else - { - /* Enable TX */ - - if (priv->rx_mode) - { - /* Disable SPI */ - - spi_modifycr(STM32_SPI_CR1_OFFSET, priv, 0, SPI_CR1_SPE); - - /* Enable TX output */ - - spi_modifycr(STM32_SPI_CR1_OFFSET, priv, SPI_CR1_BIDIOE, 0); - - /* Enable SPI */ - - spi_modifycr(STM32_SPI_CR1_OFFSET, priv, SPI_CR1_SPE, 0); - - priv->rx_mode = false; - } - } -} - -/**************************************************************************** - * Name: spi_getreg8 - * - * Description: - * Get the contents of the SPI register at offset - * - * Input Parameters: - * priv - private SPI device structure - * offset - offset to the register of interest - * - * Returned Value: - * The contents of the 8-bit register - * - ****************************************************************************/ - -#ifdef HAVE_IP_SPI_V2 -static inline uint8_t spi_getreg8(struct stm32_spidev_s *priv, - uint8_t offset) -{ - return getreg8(priv->spibase + offset); -} -#endif - -/**************************************************************************** - * Name: spi_putreg8 - * - * Description: - * Write a 8-bit value to the SPI register at offset - * - * Input Parameters: - * priv - private SPI device structure - * offset - offset to the register of interest - * value - the 8-bit value to be written - * - ****************************************************************************/ - -#ifdef HAVE_IP_SPI_V2 -static inline void spi_putreg8(struct stm32_spidev_s *priv, - uint8_t offset, uint8_t value) -{ - putreg8(value, priv->spibase + offset); -} -#endif - -/**************************************************************************** - * Name: spi_readword - * - * Description: - * Read one word (TWO bytes!) from SPI - * - * Input Parameters: - * priv - Device-specific state data - * - * Returned Value: - * Word as read - * - ****************************************************************************/ - -static inline uint16_t spi_readword(struct stm32_spidev_s *priv) -{ - /* Can't receive in tx only mode */ - - if (priv->config == SIMPLEX_TX) - { - return 0; - } - - if (priv->config == HALF_DUPLEX) - { - spi_rx_mode(priv, true); - } - - /* Wait until the receive buffer is not empty */ - - while ((spi_getreg(priv, STM32_SPI_SR_OFFSET) & SPI_SR_RXNE) == 0); - - if (priv->config == HALF_DUPLEX) - { - spi_rx_mode(priv, false); - } - - /* Then return the received byte */ - -#ifdef HAVE_IP_SPI_V2 - if (priv->nbits < 9) - { - return (uint16_t)spi_getreg8(priv, STM32_SPI_DR_OFFSET); - } - else -#endif - { - return spi_getreg(priv, STM32_SPI_DR_OFFSET); - } -} - -/**************************************************************************** - * Name: spi_writeword - * - * Description: - * Write one 16-bit frame to the SPI FIFO - * - * Input Parameters: - * priv - Device-specific state data - * byte - Word to send - * - * Returned Value: - * None - * - ****************************************************************************/ - -static inline void spi_writeword(struct stm32_spidev_s *priv, - uint16_t word) -{ - /* Can't transmit in rx only mode */ - - if (priv->config == SIMPLEX_RX) - { - return; - } - - if (priv->config == HALF_DUPLEX) - { - spi_rx_mode(priv, false); - } - - /* Wait until the transmit buffer is empty */ - - while ((spi_getreg(priv, STM32_SPI_SR_OFFSET) & SPI_SR_TXE) == 0) - { - } - - /* Then send the word */ - -#ifdef HAVE_IP_SPI_V2 - /* "When the data frame size fits into one byte (less than or equal to 8 - * bits), data packing is used automatically when any read or write 16-bit - * access is performed on the SPIx_DR register. The double data frame - * pattern is handled in parallel in this case. At first, the SPI operates - * using the pattern stored in the LSB of the accessed word, then with the - * other half stored in the MSB... - * - * "A specific problem appears if an odd number of such "fit into one - * byte" data frames must be handled. On the transmitter side, writing - * the last data frame of any odd sequence with an 8-bit access to - * SPIx_DR is enough. ..." - * - * REVISIT: "...The receiver has to change the Rx_FIFO threshold level for - * the last data frame received in the odd sequence of frames in order to - * generate the RXNE event." - */ - - if (priv->nbits < 9) - { - spi_putreg8(priv, STM32_SPI_DR_OFFSET, (uint8_t)word); - } - else -#endif - { - spi_putreg(priv, STM32_SPI_DR_OFFSET, word); - } - - if (priv->config == HALF_DUPLEX) - { - /* Wait for data transfer to be completed */ - - while ((spi_getreg(priv, STM32_SPI_SR_OFFSET) & SPI_SR_BSY) != 0); - } -} - -/**************************************************************************** - * Name: spi_16bitmode - * - * Description: - * Check if the SPI is operating in 16-bit mode - * - * Input Parameters: - * priv - Device-specific state data - * - * Returned Value: - * true: 16-bit mode, false: 8-bit mode - * - ****************************************************************************/ - -static inline bool spi_16bitmode(struct stm32_spidev_s *priv) -{ -#ifdef HAVE_IP_SPI_V2 - return (priv->nbits > 8); -#else - return ((spi_getreg(priv, STM32_SPI_CR1_OFFSET) & SPI_CR1_DFF) != 0); -#endif -} - -/**************************************************************************** - * Name: spi_dmarxwait - * - * Description: - * Wait for DMA to complete. - * - ****************************************************************************/ - -#ifdef CONFIG_STM32F0L0G0_SPI_DMA -static int spi_dmarxwait(struct stm32_spidev_s *priv) -{ - int ret; - - /* Take the semaphore (perhaps waiting). If the result is zero, then the - * DMA must not really have completed??? - */ - - do - { - ret = nxsem_wait_uninterruptible(&priv->rxsem); - - /* The only expected error is ECANCELED which would occur if the - * calling thread were canceled. - */ - - DEBUGASSERT(ret == OK || ret == -ECANCELED); - } - while (priv->rxresult == 0 && ret == OK); - - return ret; -} -#endif - -/**************************************************************************** - * Name: spi_dmatxwait - * - * Description: - * Wait for DMA to complete. - * - ****************************************************************************/ - -#ifdef CONFIG_STM32F0L0G0_SPI_DMA -static int spi_dmatxwait(struct stm32_spidev_s *priv) -{ - int ret; - - /* Take the semaphore (perhaps waiting). If the result is zero, then the - * DMA must not really have completed??? - */ - - do - { - ret = nxsem_wait_uninterruptible(&priv->txsem); - - /* The only expected error is ECANCELED which would occur if the - * calling thread were canceled. - */ - - DEBUGASSERT(ret == OK || ret == -ECANCELED); - } - while (priv->txresult == 0 && ret == OK); - - return ret; -} -#endif - -/**************************************************************************** - * Name: spi_dmarxwakeup - * - * Description: - * Signal that DMA is complete - * - ****************************************************************************/ - -#ifdef CONFIG_STM32F0L0G0_SPI_DMA -static inline void spi_dmarxwakeup(struct stm32_spidev_s *priv) -{ - nxsem_post(&priv->rxsem); -} -#endif - -/**************************************************************************** - * Name: spi_dmatxwakeup - * - * Description: - * Signal that DMA is complete - * - ****************************************************************************/ - -#ifdef CONFIG_STM32F0L0G0_SPI_DMA -static inline void spi_dmatxwakeup(struct stm32_spidev_s *priv) -{ - nxsem_post(&priv->txsem); -} -#endif - -/**************************************************************************** - * Name: spi_dmarxcallback - * - * Description: - * Called when the RX DMA completes - * - ****************************************************************************/ - -#ifdef CONFIG_STM32F0L0G0_SPI_DMA -static void spi_dmarxcallback(DMA_HANDLE handle, uint8_t isr, void *arg) -{ - struct stm32_spidev_s *priv = (struct stm32_spidev_s *)arg; - - /* Wake-up the SPI driver */ - - priv->rxresult = isr | 0x080; /* OR'ed with 0x80 to assure non-zero */ - spi_dmarxwakeup(priv); -} -#endif - -/**************************************************************************** - * Name: spi_dmatxcallback - * - * Description: - * Called when the RX DMA completes - * - ****************************************************************************/ - -#ifdef CONFIG_STM32F0L0G0_SPI_DMA -static void spi_dmatxcallback(DMA_HANDLE handle, uint8_t isr, void *arg) -{ - struct stm32_spidev_s *priv = (struct stm32_spidev_s *)arg; - - /* Wake-up the SPI driver */ - - priv->txresult = isr | 0x080; /* OR'ed with 0x80 to assure non-zero */ - spi_dmatxwakeup(priv); -} -#endif - -/**************************************************************************** - * Name: spi_dmarxsetup - * - * Description: - * Setup to perform RX DMA - * - ****************************************************************************/ - -#ifdef CONFIG_STM32F0L0G0_SPI_DMA -static void spi_dmarxsetup(struct stm32_spidev_s *priv, - void *rxbuffer, void *rxdummy, - size_t nwords) -{ - /* 8- or 16-bit mode? */ - - if (spi_16bitmode(priv)) - { - /* 16-bit mode -- is there a buffer to receive data in? */ - - if (rxbuffer) - { - priv->rxccr = SPI_RXDMA16_CONFIG; - } - else - { - rxbuffer = rxdummy; - priv->rxccr = SPI_RXDMA16NULL_CONFIG; - } - } - else - { - /* 8-bit mode -- is there a buffer to receive data in? */ - - if (rxbuffer) - { - priv->rxccr = SPI_RXDMA8_CONFIG; - } - else - { - rxbuffer = rxdummy; - priv->rxccr = SPI_RXDMA8NULL_CONFIG; - } - } - - /* Configure the RX DMA */ - - stm32_dmasetup(priv->rxdma, priv->spibase + STM32_SPI_DR_OFFSET, - (uint32_t)rxbuffer, nwords, priv->rxccr); -} -#endif - -/**************************************************************************** - * Name: spi_dmatxsetup - * - * Description: - * Setup to perform TX DMA - * - ****************************************************************************/ - -#ifdef CONFIG_STM32F0L0G0_SPI_DMA -static void spi_dmatxsetup(struct stm32_spidev_s *priv, - const void *txbuffer, const void *txdummy, - size_t nwords) -{ - /* 8- or 16-bit mode? */ - - if (spi_16bitmode(priv)) - { - /* 16-bit mode -- is there a buffer to transfer data from? */ - - if (txbuffer) - { - priv->txccr = SPI_TXDMA16_CONFIG; - } - else - { - txbuffer = txdummy; - priv->txccr = SPI_TXDMA16NULL_CONFIG; - } - } - else - { - /* 8-bit mode -- is there a buffer to transfer data from? */ - - if (txbuffer) - { - priv->txccr = SPI_TXDMA8_CONFIG; - } - else - { - txbuffer = txdummy; - priv->txccr = SPI_TXDMA8NULL_CONFIG; - } - } - - /* Setup the TX DMA */ - - stm32_dmasetup(priv->txdma, priv->spibase + STM32_SPI_DR_OFFSET, - (uint32_t)txbuffer, nwords, priv->txccr); -} -#endif - -/**************************************************************************** - * Name: spi_dmarxstart - * - * Description: - * Start RX DMA - * - ****************************************************************************/ - -#ifdef CONFIG_STM32F0L0G0_SPI_DMA -static inline void spi_dmarxstart(struct stm32_spidev_s *priv) -{ - priv->rxresult = 0; - stm32_dmastart(priv->rxdma, spi_dmarxcallback, priv, false); -} -#endif - -/**************************************************************************** - * Name: spi_dmatxstart - * - * Description: - * Start TX DMA - * - ****************************************************************************/ - -#ifdef CONFIG_STM32F0L0G0_SPI_DMA -static inline void spi_dmatxstart(struct stm32_spidev_s *priv) -{ - priv->txresult = 0; - stm32_dmastart(priv->txdma, spi_dmatxcallback, priv, false); -} -#endif - -/**************************************************************************** - * Name: spi_modifycr - * - * Description: - * Clear and set bits in the CR1 or CR2 register - * - * Input Parameters: - * priv - Device-specific state data - * clrbits - The bits to clear - * setbits - The bits to set - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void spi_modifycr(uint32_t addr, struct stm32_spidev_s *priv, - uint16_t setbits, uint16_t clrbits) -{ - uint16_t cr; - - cr = spi_getreg(priv, addr); - cr &= ~clrbits; - cr |= setbits; - spi_putreg(priv, addr, cr); -} - -/**************************************************************************** - * Name: spi_lock - * - * Description: - * On SPI buses where there are multiple devices, it will be necessary to - * lock SPI to have exclusive access to the buses for a sequence of - * transfers. The bus should be locked before the chip is selected. After - * locking the SPI bus, the caller should then also call the setfrequency, - * setbits, and setmode methods to make sure that the SPI is properly - * configured for the device. If the SPI bus is being shared, then it - * may have been left in an incompatible state. - * - * Input Parameters: - * dev - Device-specific state data - * lock - true: Lock spi bus, false: unlock SPI bus - * - * Returned Value: - * None - * - ****************************************************************************/ - -static int spi_lock(struct spi_dev_s *dev, bool lock) -{ - struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev; - int ret; - - if (lock) - { - ret = nxmutex_lock(&priv->lock); - } - else - { - ret = nxmutex_unlock(&priv->lock); - } - - return ret; -} - -/**************************************************************************** - * Name: spi_setfrequency - * - * Description: - * Set the SPI frequency. - * - * Input Parameters: - * dev - Device-specific state data - * frequency - The SPI frequency requested - * - * Returned Value: - * Returns the actual frequency selected - * - ****************************************************************************/ - -static uint32_t spi_setfrequency(struct spi_dev_s *dev, - uint32_t frequency) -{ - struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev; - uint16_t setbits; - uint32_t actual; - - /* Limit to max possible (if STM32_SPI_CLK_MAX is defined in board.h) */ - - if (frequency > STM32_SPI_CLK_MAX) - { - frequency = STM32_SPI_CLK_MAX; - } - - /* Has the frequency changed? */ - - if (frequency != priv->frequency) - { - /* Choices are limited by PCLK frequency with a set of divisors */ - - if (frequency >= priv->spiclock >> 1) - { - /* More than fPCLK/2. This is as fast as we can go */ - - setbits = SPI_CR1_FPCLCKd2; /* 000: fPCLK/2 */ - actual = priv->spiclock >> 1; - } - else if (frequency >= priv->spiclock >> 2) - { - /* Between fPCLCK/2 and fPCLCK/4, pick the slower */ - - setbits = SPI_CR1_FPCLCKd4; /* 001: fPCLK/4 */ - actual = priv->spiclock >> 2; - } - else if (frequency >= priv->spiclock >> 3) - { - /* Between fPCLCK/4 and fPCLCK/8, pick the slower */ - - setbits = SPI_CR1_FPCLCKd8; /* 010: fPCLK/8 */ - actual = priv->spiclock >> 3; - } - else if (frequency >= priv->spiclock >> 4) - { - /* Between fPCLCK/8 and fPCLCK/16, pick the slower */ - - setbits = SPI_CR1_FPCLCKd16; /* 011: fPCLK/16 */ - actual = priv->spiclock >> 4; - } - else if (frequency >= priv->spiclock >> 5) - { - /* Between fPCLCK/16 and fPCLCK/32, pick the slower */ - - setbits = SPI_CR1_FPCLCKd32; /* 100: fPCLK/32 */ - actual = priv->spiclock >> 5; - } - else if (frequency >= priv->spiclock >> 6) - { - /* Between fPCLCK/32 and fPCLCK/64, pick the slower */ - - setbits = SPI_CR1_FPCLCKd64; /* 101: fPCLK/64 */ - actual = priv->spiclock >> 6; - } - else if (frequency >= priv->spiclock >> 7) - { - /* Between fPCLCK/64 and fPCLCK/128, pick the slower */ - - setbits = SPI_CR1_FPCLCKd128; /* 110: fPCLK/128 */ - actual = priv->spiclock >> 7; - } - else - { - /* Less than fPCLK/128. This is as slow as we can go */ - - setbits = SPI_CR1_FPCLCKd256; /* 111: fPCLK/256 */ - actual = priv->spiclock >> 8; - } - - spi_modifycr(STM32_SPI_CR1_OFFSET, priv, 0, SPI_CR1_SPE); - spi_modifycr(STM32_SPI_CR1_OFFSET, priv, setbits, SPI_CR1_BR_MASK); - spi_modifycr(STM32_SPI_CR1_OFFSET, priv, SPI_CR1_SPE, 0); - - /* Save the frequency selection so that subsequent reconfigurations - * will be faster. - */ - - spiinfo("Frequency %" PRId32 "->% " PRId32 "\n", frequency, actual); - - priv->frequency = frequency; - priv->actual = actual; - } - - return priv->actual; -} - -/**************************************************************************** - * Name: spi_setmode - * - * Description: - * Set the SPI mode. see enum spi_mode_e for mode definitions - * - * Input Parameters: - * dev - Device-specific state data - * mode - The SPI mode requested - * - * Returned Value: - * Returns the actual frequency selected - * - ****************************************************************************/ - -static void spi_setmode(struct spi_dev_s *dev, enum spi_mode_e mode) -{ - struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev; - uint16_t setbits; - uint16_t clrbits; - - spiinfo("mode=%d\n", mode); - - /* Has the mode changed? */ - - if (mode != priv->mode) - { - /* Yes... Set CR1 appropriately */ - - switch (mode) - { - case SPIDEV_MODE0: /* CPOL=0; CPHA=0 */ - setbits = 0; - clrbits = SPI_CR1_CPOL | SPI_CR1_CPHA; - break; - - case SPIDEV_MODE1: /* CPOL=0; CPHA=1 */ - setbits = SPI_CR1_CPHA; - clrbits = SPI_CR1_CPOL; - break; - - case SPIDEV_MODE2: /* CPOL=1; CPHA=0 */ - setbits = SPI_CR1_CPOL; - clrbits = SPI_CR1_CPHA; - break; - - case SPIDEV_MODE3: /* CPOL=1; CPHA=1 */ - setbits = SPI_CR1_CPOL | SPI_CR1_CPHA; - clrbits = 0; - break; - - default: - return; - } - - spi_modifycr(STM32_SPI_CR1_OFFSET, priv, 0, SPI_CR1_SPE); - spi_modifycr(STM32_SPI_CR1_OFFSET, priv, setbits, clrbits); - spi_modifycr(STM32_SPI_CR1_OFFSET, priv, SPI_CR1_SPE, 0); - - /* Save the mode so that subsequent re-configurations will be - * faster. - */ - - priv->mode = mode; - } -} - -/**************************************************************************** - * Name: spi_setbits - * - * Description: - * Set the number of bits per word. With STM32, this is not restricted to - * 8 or 16, but can be any value between 4 and 16. - * - * Input Parameters: - * dev - Device-specific state data - * nbits - The number of bits requested, negative value means LSB first. - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void spi_setbits(struct spi_dev_s *dev, int nbits) -{ - struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev; - uint16_t setbits; - uint16_t clrbits; - - spiinfo("nbits=%d\n", nbits); - - /* Has the number of bits changed? */ - - if (nbits != priv->nbits) - { -#ifdef HAVE_IP_SPI_V2 - /* Yes... Set CR2 appropriately */ - - /* Set the number of bits (valid range 4-16) */ - - if (nbits < 4 || nbits > 16) - { - spierr("ERROR: nbits out of range: %d\n", nbits); - return; - } - - clrbits = SPI_CR2_DS_MASK; - setbits = SPI_CR2_DS_VAL(nbits); - - /* If nbits is <=8, then we are in byte mode and FRXTH shall be set - * (else, transaction will not complete). - */ - - if (nbits < 9) - { - setbits |= SPI_CR2_FRXTH; /* RX FIFO Threshold = 1 byte */ - } - else - { - clrbits |= SPI_CR2_FRXTH; /* RX FIFO Threshold = 2 bytes */ - } - - spi_modifycr(STM32_SPI_CR1_OFFSET, priv, 0, SPI_CR1_SPE); - spi_modifycr(STM32_SPI_CR2_OFFSET, priv, setbits, clrbits); - spi_modifycr(STM32_SPI_CR1_OFFSET, priv, SPI_CR1_SPE, 0); -#else - /* Yes... Set CR1 appropriately */ - - switch (nbits) - { - case 8: - setbits = 0; - clrbits = SPI_CR1_DFF; - break; - - case 16: - setbits = SPI_CR1_DFF; - clrbits = 0; - break; - - default: - return; - } - - spi_modifycr(STM32_SPI_CR1_OFFSET, priv, 0, SPI_CR1_SPE); - spi_modifycr(STM32_SPI_CR1_OFFSET, priv, setbits, clrbits); - spi_modifycr(STM32_SPI_CR1_OFFSET, priv, SPI_CR1_SPE, 0); -#endif - - /* Save the selection so that subsequent re-configurations will be - * faster. - */ - - priv->nbits = nbits; - } -} - -/**************************************************************************** - * Name: spi_hwfeatures - * - * Description: - * Set hardware-specific feature flags. - * - * Input Parameters: - * dev - Device-specific state data - * features - H/W feature flags - * - * Returned Value: - * Zero (OK) if the selected H/W features are enabled; A negated errno - * value if any H/W feature is not supportable. - * - ****************************************************************************/ - -#ifdef CONFIG_SPI_HWFEATURES -static int spi_hwfeatures(struct spi_dev_s *dev, - spi_hwfeatures_t features) -{ -#if defined(CONFIG_SPI_BITORDER) || defined(CONFIG_SPI_TRIGGER) - struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev; -#endif - -#ifdef CONFIG_SPI_BITORDER - uint16_t setbits; - uint16_t clrbits; - - spiinfo("features=%08x\n", features); - - /* Transfer data LSB first? */ - - if ((features & HWFEAT_LSBFIRST) != 0) - { - setbits = SPI_CR1_LSBFIRST; - clrbits = 0; - } - else - { - setbits = 0; - clrbits = SPI_CR1_LSBFIRST; - } - - spi_modifycr(STM32_SPI_CR1_OFFSET, priv, 0, SPI_CR1_SPE); - spi_modifycr(STM32_SPI_CR1_OFFSET, priv, setbits, clrbits); - spi_modifycr(STM32_SPI_CR1_OFFSET, priv, SPI_CR1_SPE, 0); - - features &= ~HWFEAT_LSBFIRST; -#endif - -#ifdef CONFIG_SPI_TRIGGER -/* Turn deferred trigger mode on or off. Only applicable for DMA mode. If a - * transfer is deferred then the DMA will not actually be triggered until a - * subsequent call to SPI_TRIGGER to set it off. The thread will be waiting - * on the transfer completing as normal. - */ - - priv->defertrig = ((features & HWFEAT_TRIGGER) != 0); - features &= ~HWFEAT_TRIGGER; -#endif - - /* Other H/W features are not supported */ - - return (features == 0) ? OK : -ENOSYS; -} -#endif - -/**************************************************************************** - * Name: spi_send - * - * Description: - * Exchange one word on SPI - * - * Input Parameters: - * dev - Device-specific state data - * wd - The word to send. the size of the data is determined by the - * number of bits selected for the SPI interface. - * - * Returned Value: - * response - * - ****************************************************************************/ - -static uint32_t spi_send(struct spi_dev_s *dev, uint32_t wd) -{ - struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev; - uint32_t regval; - uint32_t ret = 0; - - DEBUGASSERT(priv && priv->spibase); - - if (priv->config != HALF_DUPLEX) - { - spi_writeword(priv, (uint16_t)(wd & 0xffff)); - ret = (uint32_t)spi_readword(priv); - } - else - { - /* In half duplex we must send data and receive data in separate - * spi_send() calls. - */ - - if (!priv->rx_now) - { - spi_writeword(priv, (uint16_t)(wd & 0xffff)); - } - else - { - ret = (uint32_t)spi_readword(priv); - - priv->rx_now = false; - } - } - - /* Check and clear any error flags (Reading from the SR clears the error - * flags) - */ - - regval = spi_getreg(priv, STM32_SPI_SR_OFFSET); - - spiinfo("Sent: %04" PRIx32 " Return: %04" PRIx32 - " Status: %02" PRIx32 "\n", wd, ret, regval); - UNUSED(regval); - - return ret; -} - -/**************************************************************************** - * Name: spi_exchange (no DMA). aka spi_exchange_nodma - * - * Description: - * Exchange a block of data on SPI without using DMA - * - * Input Parameters: - * dev - Device-specific state data - * txbuffer - A pointer to the buffer of data to be sent - * rxbuffer - A pointer to a buffer in which to receive data - * nwords - the length of data to be exchanged in units of words. - * The wordsize is determined by the number of bits-per-word - * selected for the SPI interface. If nbits <= 8, the data is - * packed into uint8_t's; if nbits >8, the data is packed into - * uint16_t's - * - * Returned Value: - * None - * - ****************************************************************************/ - -#if !defined(CONFIG_STM32F0L0G0_SPI_DMA) -static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, - void *rxbuffer, size_t nwords) -#else -static void spi_exchange_nodma(struct spi_dev_s *dev, - const void *txbuffer, void *rxbuffer, - size_t nwords) -#endif -{ - struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev; - DEBUGASSERT(priv && priv->spibase); - - spiinfo("txbuffer=%p rxbuffer=%p nwords=%d\n", txbuffer, rxbuffer, nwords); - - /* 8- or 16-bit mode? */ - - if (spi_16bitmode(priv)) - { - /* 16-bit mode */ - - const uint16_t *src = (const uint16_t *)txbuffer; - uint16_t *dest = (uint16_t *)rxbuffer; - uint16_t word; - - while (nwords-- > 0) - { - /* Get the next word to write. Is there a source buffer? */ - - if (src) - { - word = *src++; - priv->rx_now = false; - } - else - { - word = 0xffff; - priv->rx_now = true; - } - - /* Exchange one word */ - - word = (uint16_t)spi_send(dev, (uint32_t)word); - - /* Is there a buffer to receive the return value? */ - - if (dest) - { - *dest++ = word; - } - } - } - else - { - /* 8-bit mode */ - - const uint8_t *src = (const uint8_t *)txbuffer; - uint8_t *dest = (uint8_t *)rxbuffer; - uint8_t word; - - while (nwords-- > 0) - { - /* Get the next word to write. Is there a source buffer? */ - - if (src) - { - word = *src++; - priv->rx_now = false; - } - else - { - word = 0xff; - priv->rx_now = true; - } - - /* Exchange one word */ - - word = (uint8_t)spi_send(dev, (uint32_t)word); - - /* Is there a buffer to receive the return value? */ - - if (dest) - { - *dest++ = word; - } - } - } -} - -/**************************************************************************** - * Name: spi_exchange (with DMA capability) - * - * Description: - * Exchange a block of data on SPI using DMA - * - * Input Parameters: - * dev - Device-specific state data - * txbuffer - A pointer to the buffer of data to be sent - * rxbuffer - A pointer to a buffer in which to receive data - * nwords - the length of data to be exchanged in units of words. - * The wordsize is determined by the number of bits-per-word - * selected for the SPI interface. If nbits <= 8, the data is - * packed into uint8_t's; if nbits >8, the data is packed into - * uint16_t's - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef CONFIG_STM32F0L0G0_SPI_DMA -static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, - void *rxbuffer, size_t nwords) -{ - struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev; - int ret = OK; - - if ((priv->rxdma == NULL) || (priv->txdma == NULL) || - up_interrupt_context()) - { - /* Invalid DMA channels, or interrupt context, fall - * back to non-DMA method. - */ - - spi_exchange_nodma(dev, txbuffer, rxbuffer, nwords); - return; - } - -#ifdef CONFIG_STM32F0L0G0_DMACAPABLE - if ((txbuffer && - !stm32_dmacapable((uintptr_t)txbuffer, nwords, priv->txccr)) || - (rxbuffer && - !stm32_dmacapable((uintptr_t)rxbuffer, nwords, priv->rxccr))) - { - /* Unsupported memory region, fall back to non-DMA method. */ - - spi_exchange_nodma(dev, txbuffer, rxbuffer, nwords); - } - else -#endif - { - static uint16_t rxdummy = 0xffff; - static const uint16_t txdummy = 0xffff; - - spiinfo("txbuffer=%p rxbuffer=%p nwords=%d\n", - txbuffer, rxbuffer, nwords); - DEBUGASSERT(priv && priv->spibase); - - /* Setup DMAs */ - - spi_dmarxsetup(priv, rxbuffer, &rxdummy, nwords); - spi_dmatxsetup(priv, txbuffer, &txdummy, nwords); - -#ifdef CONFIG_SPI_TRIGGER - /* Is deferred triggering in effect? */ - - if (!priv->defertrig) - { - /* No.. Start the DMAs */ - - spi_dmarxstart(priv); - spi_dmatxstart(priv); - } - else - { - /* Yes.. indicated that we are ready to be started */ - - priv->trigarmed = true; - } -#else - /* Start the DMAs */ - - spi_dmarxstart(priv); - spi_dmatxstart(priv); -#endif - - /* Then wait for each to complete */ - - ret = spi_dmarxwait(priv); - if (ret >= 0) - { - ret = spi_dmatxwait(priv); - UNUSED(ret); - } - -#ifdef CONFIG_SPI_TRIGGER - priv->trigarmed = false; -#endif - } -} -#endif /* CONFIG_STM32F0L0G0_SPI_DMA */ - -/**************************************************************************** - * Name: spi_trigger - * - * Description: - * Trigger a previously configured DMA transfer. - * - * Input Parameters: - * dev - Device-specific state data - * - * Returned Value: - * OK - Trigger was fired - * ENOTSUP - Trigger not fired due to lack of DMA support - * EIO - Trigger not fired because not previously primed - * - ****************************************************************************/ - -#ifdef CONFIG_SPI_TRIGGER -static int spi_trigger(struct spi_dev_s *dev) -{ -#ifdef CONFIG_STM32F0L0G0_SPI_DMA - struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev; - - if (!priv->trigarmed) - { - return -EIO; - } - - spi_dmarxstart(priv); - spi_dmatxstart(priv); - - return OK; -#else - return -ENOSYS; -#endif -} -#endif - -/**************************************************************************** - * Name: spi_sndblock - * - * Description: - * Send a block of data on SPI - * - * Input Parameters: - * dev - Device-specific state data - * txbuffer - A pointer to the buffer of data to be sent - * nwords - the length of data to send from the buffer in number of - * words. The wordsize is determined by the number of - * bits-per-word selected for the SPI interface. If nbits <= 8, - * the data is packed into uint8_t's; if nbits >8, the data is - * packed into uint16_t's - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifndef CONFIG_SPI_EXCHANGE -static void spi_sndblock(struct spi_dev_s *dev, const void *txbuffer, - size_t nwords) -{ - spiinfo("txbuffer=%p nwords=%d\n", txbuffer, nwords); - return spi_exchange(dev, txbuffer, NULL, nwords); -} -#endif - -/**************************************************************************** - * Name: spi_recvblock - * - * Description: - * Receive a block of data from SPI - * - * Input Parameters: - * dev - Device-specific state data - * rxbuffer - A pointer to the buffer in which to receive data - * nwords - the length of data that can be received in the buffer in - * number of words. The wordsize is determined by the number of - * bits-per-word selected for the SPI interface. If nbits <= 8, - * the data is packed into uint8_t's; if nbits >8, the data is - * packed into uint16_t's - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifndef CONFIG_SPI_EXCHANGE -static void spi_recvblock(struct spi_dev_s *dev, void *rxbuffer, - size_t nwords) -{ - spiinfo("rxbuffer=%p nwords=%d\n", rxbuffer, nwords); - return spi_exchange(dev, NULL, rxbuffer, nwords); -} -#endif - -/**************************************************************************** - * Name: spi_pm_prepare - * - * Description: - * Request the driver to prepare for a new power state. This is a - * warning that the system is about to enter into a new power state. The - * driver should begin whatever operations that may be required to enter - * power state. The driver may abort the state change mode by returning - * a non-zero value from the callback function. - * - * Input Parameters: - * cb - Returned to the driver. The driver version of the callback - * structure may include additional, driver-specific state - * data at the end of the structure. - * domain - Identifies the activity domain of the state change - * pmstate - Identifies the new PM state - * - * Returned Value: - * 0 (OK) means the event was successfully processed and that the driver - * is prepared for the PM state change. Non-zero means that the driver - * is not prepared to perform the tasks needed achieve this power setting - * and will cause the state change to be aborted. NOTE: The prepare - * method will also be recalled when reverting from lower back to higher - * power consumption modes (say because another driver refused a lower - * power state change). Drivers are not permitted to return non-zero - * values when reverting back to higher power consumption modes! - * - ****************************************************************************/ - -#ifdef CONFIG_PM -static int spi_pm_prepare(struct pm_callback_s *cb, int domain, - enum pm_state_e pmstate) -{ - struct stm32_spidev_s *priv = - (struct stm32_spidev_s *)((char *)cb - - offsetof(struct stm32_spidev_s, pm_cb)); - - /* Logic to prepare for a reduced power state goes here. */ - - switch (pmstate) - { - case PM_NORMAL: - case PM_IDLE: - break; - - case PM_STANDBY: - case PM_SLEEP: - - if (nxmutex_is_locked(&priv->lock)) - { - /* Exclusive lock is held, do not allow entry to deeper PM - * states. - */ - - return -EBUSY; - } - - break; - - default: - - /* Should not get here */ - - break; - } - - return OK; -} -#endif - -/**************************************************************************** - * Name: spi_bus_initialize - * - * Description: - * Initialize the selected SPI bus in its default state (Master, 8-bit, - * mode 0, etc.) - * - * Input Parameters: - * priv - private SPI device structure - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void spi_bus_initialize(struct stm32_spidev_s *priv) -{ - uint16_t setbits; - uint16_t clrbits; -#ifdef CONFIG_PM - int ret; -#endif - -#ifdef HAVE_IP_SPI_V2 - /* Configure CR1 and CR2. Default configuration: - * Mode 0: CR1.CPHA=0 and CR1.CPOL=0 - * Master: CR1.MSTR=1 - * 8-bit: CR2.DS=7 - * MSB transmitted first: CR1.LSBFIRST=0 - * Replace NSS with SSI & SSI=1: CR1.SSI=1 CR1.SSM=1 (prevents MODF - * error) - * Two lines full duplex: CR1.BIDIMODE=0 CR1.BIDIOIE=(Don't care) - * and CR1.RXONLY=0 - */ - - clrbits = SPI_CR1_CPHA | SPI_CR1_CPOL | SPI_CR1_BR_MASK | - SPI_CR1_LSBFIRST; - setbits = SPI_CR1_MSTR | SPI_CR1_SSI | SPI_CR1_SSM; - - switch (priv->config) - { - default: - case FULL_DUPLEX: - clrbits |= SPI_CR1_BIDIOE | SPI_CR1_BIDIMODE | SPI_CR1_RXONLY; - setbits |= 0; - break; - case SIMPLEX_TX: - clrbits |= SPI_CR1_BIDIOE | SPI_CR1_BIDIMODE | SPI_CR1_RXONLY; - setbits |= 0; - break; - case SIMPLEX_RX: - clrbits |= SPI_CR1_BIDIOE | SPI_CR1_BIDIMODE; - setbits |= SPI_CR1_RXONLY; - break; - case HALF_DUPLEX: - clrbits |= SPI_CR1_RXONLY; - setbits |= SPI_CR1_BIDIOE | SPI_CR1_BIDIMODE; /* TX mode */ - priv->rx_mode = false; - break; - } - - spi_modifycr(STM32_SPI_CR1_OFFSET, priv, setbits, clrbits); - - clrbits = SPI_CR2_DS_MASK; - setbits = SPI_CR2_DS_8BIT | SPI_CR2_FRXTH; /* FRXTH must be high in 8-bit mode */ - spi_modifycr(STM32_SPI_CR2_OFFSET, priv, setbits, clrbits); -#else - /* Configure CR1. Default configuration: - * Mode 0: CPHA=0 and CPOL=0 - * Master: MSTR=1 - * 8-bit: DFF=0 - * MSB transmitted first: LSBFIRST=0 - * Replace NSS with SSI & SSI=1: SSI=1 SSM=1 (prevents MODF error) - * Two lines full duplex: BIDIMODE=0 BIDIOIE=(Don't care) and - * RXONLY=0 - */ - - clrbits = SPI_CR1_CPHA | SPI_CR1_CPOL | SPI_CR1_BR_MASK | - SPI_CR1_LSBFIRST | SPI_CR1_DFF; - setbits = SPI_CR1_MSTR | SPI_CR1_SSI | SPI_CR1_SSM; - - switch (priv->config) - { - default: - case FULL_DUPLEX: - clrbits |= SPI_CR1_BIDIOE | SPI_CR1_BIDIMODE | SPI_CR1_RXONLY; - setbits |= 0; - break; - case SIMPLEX_TX: - clrbits |= SPI_CR1_BIDIOE | SPI_CR1_BIDIMODE | SPI_CR1_RXONLY; - setbits |= 0; - break; - case SIMPLEX_RX: - clrbits |= SPI_CR1_BIDIOE | SPI_CR1_BIDIMODE; - setbits |= SPI_CR1_RXONLY; - break; - case HALF_DUPLEX: - clrbits |= SPI_CR1_RXONLY; - setbits |= SPI_CR1_BIDIOE | SPI_CR1_BIDIMODE; /* TX mode */ - priv->rx_mode = false; - break; - } - - spi_modifycr(STM32_SPI_CR1_OFFSET, priv, setbits, clrbits); -#endif - - priv->frequency = 0; - priv->nbits = 8; - priv->mode = SPIDEV_MODE0; - - /* Select a default frequency of approx. 400KHz */ - - spi_setfrequency((struct spi_dev_s *)priv, 400000); - - /* CRCPOLY configuration */ - - spi_putreg(priv, STM32_SPI_CRCPR_OFFSET, 7); - -#ifdef CONFIG_STM32F0L0G0_SPI_DMA - if (priv->rxch && priv->txch) - { - /* Get DMA channels. NOTE: stm32_dmachannel() will always assign the - * DMA channel. If the channel is not available, then - * stm32_dmachannel() will block and wait until the channel becomes - * available. WARNING: If you have another device sharing a DMA channel - * with SPI and the code never releases that channel, then the call to - * stm32_dmachannel() will hang forever in this function! - * Don't let your design do that! - */ - - priv->rxdma = stm32_dmachannel(priv->rxch); - priv->txdma = stm32_dmachannel(priv->txch); - DEBUGASSERT(priv->rxdma && priv->txdma); - - spi_modifycr(STM32_SPI_CR2_OFFSET, priv, - SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN, 0); - } - else - { - priv->rxdma = NULL; - priv->txdma = NULL; - } -#endif - - /* Enable spi */ - - spi_modifycr(STM32_SPI_CR1_OFFSET, priv, SPI_CR1_SPE, 0); - -#ifdef CONFIG_PM - /* Register to receive power management callbacks */ - - ret = pm_register(&priv->pm_cb); - DEBUGASSERT(ret == OK); - UNUSED(ret); -#endif -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_spibus_initialize - * - * Description: - * Initialize the selected SPI bus - * - * Input Parameters: - * Port number (for hardware that has multiple SPI interfaces) - * - * Returned Value: - * Valid SPI device structure reference on success; a NULL on failure - * - ****************************************************************************/ - -struct spi_dev_s *stm32_spibus_initialize(int bus) -{ - struct stm32_spidev_s *priv = NULL; - - irqstate_t flags = enter_critical_section(); - -#ifdef CONFIG_STM32F0L0G0_SPI1 - if (bus == 1) - { - /* Select SPI1 */ - - priv = &g_spi1dev; - - /* Only configure if the bus is not already configured */ - - if (!priv->initialized) - { - /* Configure SPI1 pins: SCK, MISO, and MOSI */ - - stm32_configgpio(GPIO_SPI1_SCK); - stm32_configgpio(GPIO_SPI1_MOSI); - - if (priv->config == FULL_DUPLEX || priv->config == SIMPLEX_RX) - { - stm32_configgpio(GPIO_SPI1_MISO); - } - } - } - else -#endif -#ifdef CONFIG_STM32F0L0G0_SPI2 - if (bus == 2) - { - /* Select SPI2 */ - - priv = &g_spi2dev; - - /* Only configure if the bus is not already configured */ - - if (!priv->initialized) - { - /* Configure SPI2 pins: SCK, MISO, and MOSI */ - - stm32_configgpio(GPIO_SPI2_SCK); - stm32_configgpio(GPIO_SPI2_MOSI); - - if (priv->config == FULL_DUPLEX || priv->config == SIMPLEX_RX) - { - stm32_configgpio(GPIO_SPI2_MISO); - } - } - } - else -#endif -#ifdef CONFIG_STM32F0L0G0_SPI3 - if (bus == 3) - { - /* Select SPI3 */ - - priv = &g_spi3dev; - - /* Only configure if the bus is not already configured */ - - if (!priv->initialized) - { - /* Configure SPI3 pins: SCK, MISO, and MOSI */ - - stm32_configgpio(GPIO_SPI3_SCK); - stm32_configgpio(GPIO_SPI3_MOSI); - - if (priv->config == FULL_DUPLEX || priv->config == SIMPLEX_RX) - { - stm32_configgpio(GPIO_SPI3_MISO); - } - } - } - else -#endif - { - spierr("ERROR: Unsupported SPI bus: %d\n", bus); - priv = NULL; - goto errout; - } - -#ifdef CONFIG_STM32F0L0G0_SPI_DMA - /* SPI DMA supported only for full-duplex mode */ - - if (priv->rxch && priv->txch && priv->config != FULL_DUPLEX) - { - priv = NULL; - spierr("ERROR: SPI DMA supported only for full duplex mode\n"); - goto errout; - } -#endif - - /* Set up default configuration: Master, 8-bit, etc. */ - - spi_bus_initialize(priv); - priv->initialized = true; - -errout: - leave_critical_section(flags); - return (struct spi_dev_s *)priv; -} - -#endif /* CONFIG_STM32F0L0G0_SPI */ diff --git a/arch/arm/src/stm32f0l0g0/stm32_spi.h b/arch/arm/src/stm32f0l0g0/stm32_spi.h deleted file mode 100644 index e6ea4bdc555bb..0000000000000 --- a/arch/arm/src/stm32f0l0g0/stm32_spi.h +++ /dev/null @@ -1,171 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_spi.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_STM32_SPI_H -#define __ARCH_ARM_SRC_STM32F0L0G0_STM32_SPI_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "chip.h" -#include "hardware/stm32_spi.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#ifndef __ASSEMBLY__ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -struct spi_dev_s; - -/**************************************************************************** - * Public Functions Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_spibus_initialize - * - * Description: - * Initialize the selected SPI bus - * - * Input Parameters: - * bus number (for hardware that has multiple SPI interfaces) - * - * Returned Value: - * Valid SPI device structure reference on success; a NULL on failure - * - ****************************************************************************/ - -struct spi_dev_s *stm32_spibus_initialize(int bus); - -/**************************************************************************** - * Name: stm32_spi1/2/...select and stm32_spi1/2/...status - * - * Description: - * The external functions, stm32_spi1/2/...select, stm32_spi1/2/...status, - * and stm32_spi1/2/...cmddata must be provided by board-specific logic. - * These are implementations of the select, status, and cmddata methods of - * the SPI interface defined by struct spi_ops_s - * (see include/nuttx/spi/spi.h). All other methods (including - * stm32_spibus_initialize()) are provided by common STM32 logic. - * To use this common SPI logic on your board: - * - * 1. Provide logic in stm32_board_initialize() to configure SPI chip - * select pins. - * 2. Provide stm32_spi1/2/...select() and stm32_spi1/2/...status() - * functions in your board-specific logic. These functions will perform - * chip selection and status operations using GPIOs in the way your - * board is configured. - * 3. If CONFIG_SPI_CMDDATA is defined in your NuttX configuration file, - * then provide stm32_spi1/2/...cmddata() functions in your - * board-specific logic. These functions will perform cmd/data selection - * operations using GPIOs in the way your board is configured. - * 4. Add a calls to stm32_spibus_initialize() in your low level - * application initialization logic - * 5. The handle returned by stm32_spibus_initialize() may then be used - * to bind the SPI driver to higher level logic (e.g., calling - * mmcsd_spislotinitialize(), for example, will bind the SPI driver - * to the SPI MMC/SD driver). - * - ****************************************************************************/ - -#ifdef CONFIG_STM32F0L0G0_SPI1 -void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, - bool selected); -uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid); -int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); -#endif - -#ifdef CONFIG_STM32F0L0G0_SPI2 -void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid, - bool selected); -uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid); -int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); -#endif - -#ifdef CONFIG_STM32F0L0G0_SPI3 -void stm32_spi3select(struct spi_dev_s *dev, uint32_t devid, - bool selected); -uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid); -int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); -#endif - -/**************************************************************************** - * Name: stm32_spi1/2/...register - * - * Description: - * If the board supports a card detect callback to inform the SPI-based - * MMC/SD driver when an SD card is inserted or removed, then - * CONFIG_SPI_CALLBACK should be defined and the following function(s) - * must be implemented. These functions implements the registercallback - * method of the SPI interface (see include/nuttx/spi/spi.h for details) - * - * Input Parameters: - * dev - Device-specific state data - * callback - The function to call on the media change - * arg - A caller provided value to return with the callback - * - * Returned Value: - * 0 on success; negated errno on failure. - * - ****************************************************************************/ - -#ifdef CONFIG_SPI_CALLBACK -#ifdef CONFIG_STM32F0L0G0_SPI1 -int stm32_spi1register(struct spi_dev_s *dev, spi_mediachange_t callback, - void *arg); -#endif - -#ifdef CONFIG_STM32F0L0G0_SPI2 -int stm32_spi2register(struct spi_dev_s *dev, spi_mediachange_t callback, - void *arg); -#endif - -#ifdef CONFIG_STM32F0L0G0_SPI3 -int stm32_spi3register(struct spi_dev_s *dev, spi_mediachange_t callback, - void *arg); -#endif -#endif - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_STM32_SPI_H */ diff --git a/arch/arm/src/stm32f0l0g0/stm32_start.c b/arch/arm/src/stm32f0l0g0/stm32_start.c deleted file mode 100644 index 9b1449d4fb716..0000000000000 --- a/arch/arm/src/stm32f0l0g0/stm32_start.c +++ /dev/null @@ -1,157 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_start.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include "arm_internal.h" -#include "stm32_rcc.h" -#include "stm32_lowputc.h" -#include "stm32_start.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#define IDLE_STACK ((uint32_t)_ebss + CONFIG_IDLETHREAD_STACKSIZE) - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -const uintptr_t g_idle_topstack = IDLE_STACK; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: showprogress - * - * Description: - * Print a character on the CONSOLE USART to show boot status. - * - ****************************************************************************/ - -#ifdef CONFIG_DEBUG_FEATURES -# define showprogress(c) arm_lowputc(c) -#else -# define showprogress(c) -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: __start - * - * Description: - * This is the reset entry point. - * - ****************************************************************************/ - -void __start(void) -{ - const uint32_t *src; - uint32_t *dest; - - /* Configure the uart so that we can get debug output as soon as possible */ - - stm32_clockconfig(); - stm32_lowsetup(); - showprogress('A'); - - /* Clear .bss. We'll do this inline (vs. calling memset) just to be - * certain that there are no issues with the state of global variables. - */ - - for (dest = (uint32_t *)_sbss; dest < (uint32_t *)_ebss; ) - { - *dest++ = 0; - } - - showprogress('B'); - - /* Move the initialized data section from his temporary holding spot in - * FLASH into the correct place in SRAM. The correct place in SRAM is - * give by _sdata and _edata. The temporary location is in FLASH at the - * end of all of the other read-only data (.text, .rodata) at _eronly. - */ - - for (src = (const uint32_t *)_eronly, - dest = (uint32_t *)_sdata; dest < (uint32_t *)_edata; - ) - { - *dest++ = *src++; - } - - showprogress('C'); - -#ifdef CONFIG_ARCH_PERF_EVENTS - up_perf_init((void *)STM32_SYSCLK_FREQUENCY); -#endif - - /* Perform early serial initialization */ - -#ifdef USE_EARLYSERIALINIT - arm_earlyserialinit(); -#endif - showprogress('D'); - - /* For the case of the separate user-/kernel-space build, perform whatever - * platform specific initialization of the user memory is required. - * Normally this just means initializing the user space .data and .bss - * segments. - */ - -#ifdef CONFIG_BUILD_PROTECTED - stm32_userspace(); - showprogress('E'); -#endif - - /* Initialize onboard resources */ - - stm32_boardinitialize(); - showprogress('F'); - - /* Then start NuttX */ - - showprogress('\r'); - showprogress('\n'); - - nx_start(); - - /* Shouldn't get here */ - - for (; ; ); -} diff --git a/arch/arm/src/stm32f0l0g0/stm32_start.h b/arch/arm/src/stm32f0l0g0/stm32_start.h deleted file mode 100644 index 34691d3ac8013..0000000000000 --- a/arch/arm/src/stm32f0l0g0/stm32_start.h +++ /dev/null @@ -1,64 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_start.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_STM32_START_H -#define __ARCH_ARM_SRC_STM32F0L0G0_STM32_START_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -#ifndef __ASSEMBLY__ -#ifdef __cplusplus -extern "C" -{ -#endif - -/**************************************************************************** - * Public Functions Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_boardinitialize - * - * Description: - * All STM32 architectures must provide the following entry point. This - * entry point is called early in the initialization -- after all memory - * has been configured and mapped but before any devices have been - * initialized. - * - ****************************************************************************/ - -void stm32_boardinitialize(void); - -#ifdef __cplusplus -} -#endif -#endif /* __ASSEMBLY__ */ - -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_STM32_START_H */ diff --git a/arch/arm/src/stm32f0l0g0/stm32_tim.c b/arch/arm/src/stm32f0l0g0/stm32_tim.c deleted file mode 100644 index f3c76fa97e280..0000000000000 --- a/arch/arm/src/stm32f0l0g0/stm32_tim.c +++ /dev/null @@ -1,1502 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_tim.c - * - * SPDX-License-Identifier: BSD-3-Clause - * SPDX-FileCopyrightText: 2019 Fundação CERTI. All rights reserved. - * SPDX-FileContributor: Daniel Pereira Volpato - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include - -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32_rcc.h" -#include "stm32_gpio.h" -#include "stm32_tim.h" - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/* Configuration ************************************************************/ - -/* Timer devices may be used for different purposes. Such special purposes - * include: - * - * - To generate modulated outputs for such things as motor control. If - * CONFIG_STM32F0L0G0_TIMn is defined then the CONFIG_STM32F0L0G0_TIMn_PWM - * may also be defined to indicate that the timer is intended to be used - * for pulsed output modulation. - * - * - To control periodic ADC input sampling. If CONFIG_STM32F0L0G0_TIMn is - * defined then CONFIG_STM32F0L0G0_TIMn_ADC may also be defined to indicate - * that timer "n" is intended to be used for that purpose. - * - * - To control periodic DAC outputs. If CONFIG_STM32F0L0G0_TIMn is defined - * then CONFIG_STM32F0L0G0_TIMn_DAC may also be defined to indicate that - * timer "n" is intended to be used for that purpose. - * - * - To use a Quadrature Encoder. If CONFIG_STM32F0L0G0_TIMn is defined then - * CONFIG_STM32F0L0G0_TIMn_QE may also be defined to indicate that timer - * "n" is intended to be used for that purpose. - * - * In any of these cases, the timer will not be used by this timer module. - */ - -#if defined(CONFIG_STM32F0L0G0_TIM1_PWM) || defined(CONFIG_STM32F0L0G0_TIM1_ADC) || \ - defined(CONFIG_STM32F0L0G0_TIM1_DAC) || defined(CONFIG_STM32F0L0G0_TIM1_QE) -# undef CONFIG_STM32F0L0G0_TIM1 -#endif - -#if defined(CONFIG_STM32F0L0G0_TIM2_PWM) || defined(CONFIG_STM32F0L0G0_TIM2_ADC) || \ - defined(CONFIG_STM32F0L0G0_TIM2_DAC) || defined(CONFIG_STM32F0L0G0_TIM2_QE) -# undef CONFIG_STM32F0L0G0_TIM2 -#endif - -#if defined(CONFIG_STM32F0L0G0_TIM3_PWM) || defined(CONFIG_STM32F0L0G0_TIM3_ADC) || \ - defined(CONFIG_STM32F0L0G0_TIM3_DAC) || defined(CONFIG_STM32F0L0G0_TIM3_QE) -# undef CONFIG_STM32F0L0G0_TIM3 -#endif - -#if defined(CONFIG_STM32F0L0G0_TIM4_PWM) || defined(CONFIG_STM32F0L0G0_TIM4_ADC) || \ - defined(CONFIG_STM32F0L0G0_TIM4_DAC) || defined(CONFIG_STM32F0L0G0_TIM4_QE) -# undef CONFIG_STM32F0L0G0_TIM4 -#endif - -#if defined(CONFIG_STM32F0L0G0_TIM5_PWM) || defined(CONFIG_STM32F0L0G0_TIM5_ADC) || \ - defined(CONFIG_STM32F0L0G0_TIM5_DAC) || defined(CONFIG_STM32F0L0G0_TIM5_QE) -# undef CONFIG_STM32F0L0G0_TIM5 -#endif - -#if defined(CONFIG_STM32F0L0G0_TIM6_PWM) || defined(CONFIG_STM32F0L0G0_TIM6_ADC) || \ - defined(CONFIG_STM32F0L0G0_TIM6_DAC) || defined(CONFIG_STM32F0L0G0_TIM6_QE) -# undef CONFIG_STM32F0L0G0_TIM6 -#endif - -#if defined(CONFIG_STM32F0L0G0_TIM7_PWM) || defined(CONFIG_STM32F0L0G0_TIM7_ADC) || \ - defined(CONFIG_STM32F0L0G0_TIM7_DAC) || defined(CONFIG_STM32F0L0G0_TIM7_QE) -# undef CONFIG_STM32F0L0G0_TIM7 -#endif - -#if defined(CONFIG_STM32F0L0G0_TIM8_PWM) || defined(CONFIG_STM32F0L0G0_TIM8_ADC) || \ - defined(CONFIG_STM32F0L0G0_TIM8_DAC) || defined(CONFIG_STM32F0L0G0_TIM8_QE) -# undef CONFIG_STM32F0L0G0_TIM8 -#endif - -#if defined(CONFIG_STM32F0L0G0_TIM12_PWM) || defined(CONFIG_STM32F0L0G0_TIM12_ADC) || \ - defined(CONFIG_STM32F0L0G0_TIM12_DAC) || defined(CONFIG_STM32F0L0G0_TIM12_QE) -# undef CONFIG_STM32F0L0G0_TIM12 -#endif - -#if defined(CONFIG_STM32F0L0G0_TIM13_PWM) || defined(CONFIG_STM32F0L0G0_TIM13_ADC) || \ - defined(CONFIG_STM32F0L0G0_TIM13_DAC) || defined(CONFIG_STM32F0L0G0_TIM13_QE) -# undef CONFIG_STM32F0L0G0_TIM13 -#endif - -#if defined(CONFIG_STM32F0L0G0_TIM14_PWM) || defined(CONFIG_STM32F0L0G0_TIM14_ADC) || \ - defined(CONFIG_STM32F0L0G0_TIM14_DAC) || defined(CONFIG_STM32F0L0G0_TIM14_QE) -# undef CONFIG_STM32F0L0G0_TIM14 -#endif - -#if defined(CONFIG_STM32F0L0G0_TIM15_PWM) || defined(CONFIG_STM32F0L0G0_TIM15_ADC) || \ - defined(CONFIG_STM32F0L0G0_TIM15_DAC) || defined(CONFIG_STM32F0L0G0_TIM15_QE) -# undef CONFIG_STM32F0L0G0_TIM15 -#endif - -#if defined(CONFIG_STM32F0L0G0_TIM16_PWM) || defined(CONFIG_STM32F0L0G0_TIM16_ADC) || \ - defined(CONFIG_STM32F0L0G0_TIM16_DAC) || defined(CONFIG_STM32F0L0G0_TIM16_QE) -# undef CONFIG_STM32F0L0G0_TIM16 -#endif - -#if defined(CONFIG_STM32F0L0G0_TIM17_PWM) || defined(CONFIG_STM32F0L0G0_TIM17_ADC) || \ - defined(CONFIG_STM32F0L0G0_TIM17_DAC) || defined(CONFIG_STM32F0L0G0_TIM17_QE) -# undef CONFIG_STM32F0L0G0_TIM17 -#endif - -#if defined(CONFIG_STM32F0L0G0_TIM1) -# if defined(GPIO_TIM1_CH1OUT) || defined(GPIO_TIM1_CH2OUT) || \ - defined(GPIO_TIM1_CH3OUT) || defined(GPIO_TIM1_CH4OUT) || \ - defined(GPIO_TIM1_CH5OUT) || defined(GPIO_TIM1_CH6OUT) -# define HAVE_TIM1_GPIOCONFIG 1 -# endif -#endif - -#if defined(CONFIG_STM32F0L0G0_TIM2) -# if defined(GPIO_TIM2_CH1OUT) || defined(GPIO_TIM2_CH2OUT) || \ - defined(GPIO_TIM2_CH3OUT) || defined(GPIO_TIM2_CH4OUT) -# define HAVE_TIM2_GPIOCONFIG 1 -# endif -#endif - -#if defined(CONFIG_STM32F0L0G0_TIM3) -# if defined(GPIO_TIM3_CH1OUT) || defined(GPIO_TIM3_CH2OUT) || \ - defined(GPIO_TIM3_CH3OUT) || defined(GPIO_TIM3_CH4OUT) -# define HAVE_TIM3_GPIOCONFIG 1 -# endif -#endif - -#if defined(CONFIG_STM32F0L0G0_TIM4) -# if defined(GPIO_TIM4_CH1OUT) || defined(GPIO_TIM4_CH2OUT) || \ - defined(GPIO_TIM4_CH3OUT) || defined(GPIO_TIM4_CH4OUT) -# define HAVE_TIM4_GPIOCONFIG 1 -# endif -#endif - -#if defined(CONFIG_STM32F0L0G0_TIM5) -# if defined(GPIO_TIM5_CH1OUT) || defined(GPIO_TIM5_CH2OUT) || \ - defined(GPIO_TIM5_CH3OUT) || defined(GPIO_TIM5_CH4OUT) -# define HAVE_TIM5_GPIOCONFIG 1 -# endif -#endif - -#if defined(CONFIG_STM32F0L0G0_TIM8) -# if defined(GPIO_TIM8_CH1OUT) || defined(GPIO_TIM8_CH2OUT) || \ - defined(GPIO_TIM8_CH3OUT) || defined(GPIO_TIM8_CH4OUT) || \ - defined(GPIO_TIM8_CH5OUT) || defined(GPIO_TIM8_CH6OUT) -# define HAVE_TIM8_GPIOCONFIG 1 -# endif -#endif - -#if defined(CONFIG_STM32F0L0G0_TIM12) -# if defined(GPIO_TIM12_CH1OUT) || defined(GPIO_TIM12_CH2OUT) -# define HAVE_TIM12_GPIOCONFIG 1 -# endif -#endif - -#if defined(CONFIG_STM32F0L0G0_TIM13) -# if defined(GPIO_TIM13_CH1OUT) -# define HAVE_TIM13_GPIOCONFIG 1 -# endif -#endif - -#if defined(CONFIG_STM32F0L0G0_TIM14) -# if defined(GPIO_TIM14_CH1OUT) -# define HAVE_TIM14_GPIOCONFIG 1 -# endif -#endif - -#if defined(CONFIG_STM32F0L0G0_TIM15) -# if defined(GPIO_TIM15_CH1OUT) || defined(GPIO_TIM15_CH2OUT) -# define HAVE_TIM15_GPIOCONFIG 1 -# endif -#endif - -#if defined(CONFIG_STM32F0L0G0_TIM16) -# if defined(GPIO_TIM16_CH1OUT) -# define HAVE_TIM16_GPIOCONFIG 1 -# endif -#endif - -#if defined(CONFIG_STM32F0L0G0_TIM17) -# if defined(GPIO_TIM17_CH1OUT) -# define HAVE_TIM17_GPIOCONFIG 1 -# endif -#endif - -/* This module then only compiles if there are enabled timers that are not - * intended for some other purpose. - */ - -#if defined(CONFIG_STM32F0L0G0_TIM1) || defined(CONFIG_STM32F0L0G0_TIM2) || \ - defined(CONFIG_STM32F0L0G0_TIM3) || defined(CONFIG_STM32F0L0G0_TIM4) || \ - defined(CONFIG_STM32F0L0G0_TIM5) || defined(CONFIG_STM32F0L0G0_TIM6) || \ - defined(CONFIG_STM32F0L0G0_TIM7) || defined(CONFIG_STM32F0L0G0_TIM8) || \ - defined(CONFIG_STM32F0L0G0_TIM12) || defined(CONFIG_STM32F0L0G0_TIM13) || \ - defined(CONFIG_STM32F0L0G0_TIM14) || defined(CONFIG_STM32F0L0G0_TIM15) || \ - defined(CONFIG_STM32F0L0G0_TIM16) || defined(CONFIG_STM32F0L0G0_TIM17) - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/* TIM Device Structure */ - -struct stm32_tim_priv_s -{ - const struct stm32_tim_ops_s *ops; - stm32_tim_mode_t mode; - uint32_t base; /* TIMn base address */ -}; - -/**************************************************************************** - * Private Function prototypes - ****************************************************************************/ - -/* Timer helpers */ - -static void stm32_tim_reload_counter(struct stm32_tim_dev_s *dev); -static void stm32_tim_enable(struct stm32_tim_dev_s *dev); -static void stm32_tim_disable(struct stm32_tim_dev_s *dev); -static void stm32_tim_reset(struct stm32_tim_dev_s *dev); - -/* Timer methods */ - -static int stm32_tim_setmode(struct stm32_tim_dev_s *dev, - stm32_tim_mode_t mode); -static int stm32_tim_setclock(struct stm32_tim_dev_s *dev, - uint32_t freq); -static uint32_t stm32_tim_getclock(struct stm32_tim_dev_s *dev); -static void stm32_tim_setperiod(struct stm32_tim_dev_s *dev, - uint32_t period); -static uint32_t stm32_tim_getperiod(struct stm32_tim_dev_s *dev); -static uint32_t stm32_tim_getcounter(struct stm32_tim_dev_s *dev); -static int stm32_tim_getwidth(struct stm32_tim_dev_s *dev); -static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, - uint8_t channel, - stm32_tim_channel_t mode); -static int stm32_tim_setcompare(struct stm32_tim_dev_s *dev, - uint8_t channel, - uint32_t compare); -static int stm32_tim_getcapture(struct stm32_tim_dev_s *dev, - uint8_t channel); -static int stm32_tim_setisr(struct stm32_tim_dev_s *dev, xcpt_t handler, - void *arg, int source); -static void stm32_tim_enableint(struct stm32_tim_dev_s *dev, int source); -static void stm32_tim_disableint(struct stm32_tim_dev_s *dev, - int source); -static void stm32_tim_ackint(struct stm32_tim_dev_s *dev, int source); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -static const struct stm32_tim_ops_s stm32_tim_ops = -{ - .enable = &stm32_tim_enable, - .disable = &stm32_tim_disable, - .setmode = &stm32_tim_setmode, - .setclock = &stm32_tim_setclock, - .getclock = &stm32_tim_getclock, - .setperiod = &stm32_tim_setperiod, - .getperiod = &stm32_tim_getperiod, - .getcounter = &stm32_tim_getcounter, - .getwidth = &stm32_tim_getwidth, - .setchannel = &stm32_tim_setchannel, - .setcompare = &stm32_tim_setcompare, - .getcapture = &stm32_tim_getcapture, - .setisr = &stm32_tim_setisr, - .enableint = &stm32_tim_enableint, - .disableint = &stm32_tim_disableint, - .ackint = &stm32_tim_ackint -}; - -#ifdef CONFIG_STM32F0L0G0_TIM1 -struct stm32_tim_priv_s stm32_tim1_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM1_BASE, -}; -#endif -#ifdef CONFIG_STM32F0L0G0_TIM2 -struct stm32_tim_priv_s stm32_tim2_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM2_BASE, -}; -#endif - -#ifdef CONFIG_STM32F0L0G0_TIM3 -struct stm32_tim_priv_s stm32_tim3_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM3_BASE, -}; -#endif - -#ifdef CONFIG_STM32F0L0G0_TIM4 -struct stm32_tim_priv_s stm32_tim4_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM4_BASE, -}; -#endif - -#ifdef CONFIG_STM32F0L0G0_TIM5 -struct stm32_tim_priv_s stm32_tim5_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM5_BASE, -}; -#endif - -#ifdef CONFIG_STM32F0L0G0_TIM6 -struct stm32_tim_priv_s stm32_tim6_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM6_BASE, -}; -#endif - -#ifdef CONFIG_STM32F0L0G0_TIM7 -struct stm32_tim_priv_s stm32_tim7_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM7_BASE, -}; -#endif - -#ifdef CONFIG_STM32F0L0G0_TIM8 -struct stm32_tim_priv_s stm32_tim8_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM8_BASE, -}; -#endif - -#ifdef CONFIG_STM32F0L0G0_TIM12 -struct stm32_tim_priv_s stm32_tim12_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM12_BASE, -}; -#endif - -#ifdef CONFIG_STM32F0L0G0_TIM13 -struct stm32_tim_priv_s stm32_tim13_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM13_BASE, -}; -#endif - -#ifdef CONFIG_STM32F0L0G0_TIM14 -struct stm32_tim_priv_s stm32_tim14_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM14_BASE, -}; -#endif - -#ifdef CONFIG_STM32F0L0G0_TIM15 -struct stm32_tim_priv_s stm32_tim15_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM15_BASE, -}; -#endif - -#ifdef CONFIG_STM32F0L0G0_TIM16 -struct stm32_tim_priv_s stm32_tim16_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM16_BASE, -}; -#endif - -#ifdef CONFIG_STM32F0L0G0_TIM17 -struct stm32_tim_priv_s stm32_tim17_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM17_BASE, -}; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/* Get a 16-bit register value by offset */ - -static inline uint16_t stm32_getreg16(struct stm32_tim_dev_s *dev, - uint8_t offset) -{ - return getreg16(((struct stm32_tim_priv_s *)dev)->base + offset); -} - -/* Put a 16-bit register value by offset */ - -static inline void stm32_putreg16(struct stm32_tim_dev_s *dev, - uint8_t offset, uint16_t value) -{ - putreg16(value, ((struct stm32_tim_priv_s *)dev)->base + offset); -} - -/* Modify a 16-bit register value by offset */ - -static inline void stm32_modifyreg16(struct stm32_tim_dev_s *dev, - uint8_t offset, uint16_t clearbits, - uint16_t setbits) -{ - modifyreg16(((struct stm32_tim_priv_s *)dev)->base + offset, clearbits, - setbits); -} - -/* Get a 32-bit register value by offset. This applies only for the STM32 F4 - * 32-bit registers (CNT, ARR, CRR1-4) in the 32-bit timers TIM2-5. - */ - -static inline uint32_t stm32_getreg32(struct stm32_tim_dev_s *dev, - uint8_t offset) -{ - return getreg32(((struct stm32_tim_priv_s *)dev)->base + offset); -} - -/* Put a 32-bit register value by offset. This applies only for the STM32 F4 - * 32-bit registers (CNT, ARR, CRR1-4) in the 32-bit timers TIM2-5. - */ - -static inline void stm32_putreg32(struct stm32_tim_dev_s *dev, - uint8_t offset, uint32_t value) -{ - putreg32(value, ((struct stm32_tim_priv_s *)dev)->base + offset); -} - -static void stm32_tim_reload_counter(struct stm32_tim_dev_s *dev) -{ - uint16_t val = stm32_getreg16(dev, STM32_GTIM_EGR_OFFSET); - val |= GTIM_EGR_UG; - stm32_putreg16(dev, STM32_GTIM_EGR_OFFSET, val); -} - -static void stm32_tim_enable(struct stm32_tim_dev_s *dev) -{ - uint16_t val = stm32_getreg16(dev, STM32_GTIM_CR1_OFFSET); - val |= GTIM_CR1_CEN; - stm32_tim_reload_counter(dev); - stm32_putreg16(dev, STM32_GTIM_CR1_OFFSET, val); -} - -static void stm32_tim_disable(struct stm32_tim_dev_s *dev) -{ - uint16_t val = stm32_getreg16(dev, STM32_GTIM_CR1_OFFSET); - val &= ~GTIM_CR1_CEN; - stm32_putreg16(dev, STM32_GTIM_CR1_OFFSET, val); -} - -/* Reset timer into system default state, but do not affect output/input - * pins - */ - -static void stm32_tim_reset(struct stm32_tim_dev_s *dev) -{ - ((struct stm32_tim_priv_s *)dev)->mode = STM32_TIM_MODE_DISABLED; - stm32_tim_disable(dev); -} - -#if defined(HAVE_TIM1_GPIOCONFIG) || defined(HAVE_TIM2_GPIOCONFIG) || \ - defined(HAVE_TIM3_GPIOCONFIG) || defined(HAVE_TIM4_GPIOCONFIG) || \ - defined(HAVE_TIM5_GPIOCONFIG) || defined(HAVE_TIM6_GPIOCONFIG) || \ - defined(HAVE_TIM7_GPIOCONFIG) || defined(HAVE_TIM8_GPIOCONFIG) || \ - defined(HAVE_TIM12_GPIOCONFIG) || defined(HAVE_TIM13_GPIOCONFIG) || \ - defined(HAVE_TIM14_GPIOCONFIG) || defined(HAVE_TIM15_GPIOCONFIG) || \ - defined(HAVE_TIM16_GPIOCONFIG) || defined(HAVE_TIM17_GPIOCONFIG) -static void stm32_tim_gpioconfig(uint32_t cfg, stm32_tim_channel_t mode) -{ - /* TODO: Add support for input capture and bipolar dual outputs for TIM8 */ - - if (mode & STM32_TIM_CH_MODE_MASK) - { - stm32_configgpio(cfg); - } - else - { - stm32_unconfiggpio(cfg); - } -} -#endif - -/**************************************************************************** - * Basic Functions - ****************************************************************************/ - -static int stm32_tim_setclock(struct stm32_tim_dev_s *dev, uint32_t freq) -{ - uint32_t freqin; - int prescaler; - - tmrinfo("Set clock=%" PRId32 "\n", freq); - - DEBUGASSERT(dev != NULL); - - /* Disable Timer? */ - - if (freq == 0) - { - stm32_tim_disable(dev); - return 0; - } - - /* Get the input clock frequency for this timer. These vary with - * different timer clock sources, MCU-specific timer configuration, and - * board-specific clock configuration. The correct input clock frequency - * must be defined in the board.h header file. - */ - - switch (((struct stm32_tim_priv_s *)dev)->base) - { -#ifdef CONFIG_STM32F0L0G0_TIM1 - case STM32_TIM1_BASE: - freqin = STM32_APB2_TIM1_CLKIN; - break; -#endif -#ifdef CONFIG_STM32F0L0G0_TIM2 - case STM32_TIM2_BASE: - freqin = STM32_APB1_TIM2_CLKIN; - break; -#endif -#ifdef CONFIG_STM32F0L0G0_TIM3 - case STM32_TIM3_BASE: - freqin = STM32_APB1_TIM3_CLKIN; - break; -#endif -#ifdef CONFIG_STM32F0L0G0_TIM6 - case STM32_TIM6_BASE: - freqin = STM32_APB1_TIM6_CLKIN; - break; -#endif -#ifdef CONFIG_STM32F0L0G0_TIM7 - case STM32_TIM7_BASE: - freqin = STM32_APB1_TIM7_CLKIN; - break; -#endif -#ifdef CONFIG_STM32F0L0G0_TIM14 - case STM32_TIM14_BASE: - freqin = STM32_APB2_TIM14_CLKIN; - break; -#endif -#ifdef CONFIG_STM32F0L0G0_TIM15 - case STM32_TIM15_BASE: - freqin = STM32_APB2_TIM15_CLKIN; - break; -#endif -#ifdef CONFIG_STM32F0L0G0_TIM16 - case STM32_TIM16_BASE: - freqin = STM32_APB2_TIM16_CLKIN; - break; -#endif -#ifdef CONFIG_STM32F0L0G0_TIM17 - case STM32_TIM17_BASE: - freqin = STM32_APB2_TIM17_CLKIN; - break; -#endif - default: - return -EINVAL; - } - - /* Select a pre-scaler value for this timer using the input clock - * frequency. - */ - - prescaler = freqin / freq; - tmrinfo(" timer freq=%" PRId32 "\n", freqin); - tmrinfo(" prescaler=%d\n", prescaler); - - /* We need to decrement value for '1', but only, if that will not to - * cause underflow. - */ - - if (prescaler > 0) - { - prescaler--; - } - - /* Check for overflow as well. */ - - if (prescaler > 0xffff) - { - prescaler = 0xffff; - } - - tmrinfo(" prescaler (adjusted)=%d\n", prescaler); - - /* PSC_OFFSET is the same for ATIM, BTIM or GTIM */ - - stm32_putreg16(dev, STM32_GTIM_PSC_OFFSET, prescaler); - stm32_tim_enable(dev); - - return prescaler; -} - -static uint32_t stm32_tim_getclock(struct stm32_tim_dev_s *dev) -{ - uint32_t freqin; - uint32_t clock; - uint32_t prescaler; - DEBUGASSERT(dev != NULL); - - /* Get the input clock frequency for this timer. These vary with - * different timer clock sources, MCU-specific timer configuration, and - * board-specific clock configuration. The correct input clock frequency - * must be defined in the board.h header file. - */ - - switch (((struct stm32_tim_priv_s *)dev)->base) - { -#ifdef CONFIG_STM32F0L0G0_TIM1 - case STM32_TIM1_BASE: - freqin = STM32_APB2_TIM1_CLKIN; - break; -#endif -#ifdef CONFIG_STM32F0L0G0_TIM2 - case STM32_TIM2_BASE: - freqin = STM32_APB1_TIM2_CLKIN; - break; -#endif -#ifdef CONFIG_STM32F0L0G0_TIM3 - case STM32_TIM3_BASE: - freqin = STM32_APB1_TIM3_CLKIN; - break; -#endif -#ifdef CONFIG_STM32F0L0G0_TIM6 - case STM32_TIM6_BASE: - freqin = STM32_APB1_TIM6_CLKIN; - break; -#endif -#ifdef CONFIG_STM32F0L0G0_TIM7 - case STM32_TIM7_BASE: - freqin = STM32_APB1_TIM7_CLKIN; - break; -#endif -#ifdef CONFIG_STM32F0L0G0_TIM14 - case STM32_TIM14_BASE: - freqin = STM32_APB2_TIM14_CLKIN; - break; -#endif -#ifdef CONFIG_STM32F0L0G0_TIM15 - case STM32_TIM15_BASE: - freqin = STM32_APB2_TIM15_CLKIN; - break; -#endif -#ifdef CONFIG_STM32F0L0G0_TIM16 - case STM32_TIM16_BASE: - freqin = STM32_APB2_TIM16_CLKIN; - break; -#endif -#ifdef CONFIG_STM32F0L0G0_TIM17 - case STM32_TIM17_BASE: - freqin = STM32_APB2_TIM17_CLKIN; - break; -#endif - default: - return -EINVAL; - } - - prescaler = stm32_getreg16(dev, STM32_GTIM_PSC_OFFSET); - clock = freqin / (prescaler + 1); - return clock; -} - -static void stm32_tim_setperiod(struct stm32_tim_dev_s *dev, - uint32_t period) -{ - tmrinfo("Set period=%" PRId32 "\n", period); - DEBUGASSERT(dev != NULL); - - /* ARR_OFFSET is the same for ATIM, BTIM or GTIM */ - - stm32_putreg32(dev, STM32_GTIM_ARR_OFFSET, period); -} - -static uint32_t stm32_tim_getperiod (struct stm32_tim_dev_s *dev) -{ - DEBUGASSERT(dev != NULL); - return stm32_getreg32 (dev, STM32_GTIM_ARR_OFFSET); -} - -static int stm32_tim_getwidth(struct stm32_tim_dev_s *dev) -{ - DEBUGASSERT(dev != NULL); - -#ifdef HAVE_TIM2_32BIT - /* TIM2 is 16-bit on L0 */ - - if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM2_BASE) - { - return 32; - } -#endif - - /* All other timers are 16-bit */ - - return 16; -} - -static uint32_t stm32_tim_getcounter(struct stm32_tim_dev_s *dev) -{ - DEBUGASSERT(dev != NULL); - return stm32_tim_getwidth(dev) > 16 ? - stm32_getreg32(dev, STM32_GTIM_CNT_OFFSET) : - (uint32_t)stm32_getreg16(dev, STM32_GTIM_CNT_OFFSET); -} - -static int stm32_tim_setisr(struct stm32_tim_dev_s *dev, - xcpt_t handler, void *arg, int source) -{ - int vectorno; - - tmrinfo("Set ISR\n"); - - DEBUGASSERT(dev != NULL); - DEBUGASSERT(source == 0); - - switch (((struct stm32_tim_priv_s *)dev)->base) - { -#ifdef CONFIG_STM32F0L0G0_TIM1 - case STM32_TIM1_BASE: - vectorno = STM32_IRQ_TIM1_BRK; - break; -#endif -#ifdef CONFIG_STM32F0L0G0_TIM2 - case STM32_TIM2_BASE: - vectorno = STM32_IRQ_TIM2; - break; -#endif -#ifdef CONFIG_STM32F0L0G0_TIM3 - case STM32_TIM3_BASE: - vectorno = STM32_IRQ_TIM3; - break; -#endif -#ifdef CONFIG_STM32F0L0G0_TIM6 - case STM32_TIM6_BASE: - vectorno = STM32_IRQ_TIM6; - break; -#endif -#ifdef CONFIG_STM32F0L0G0_TIM7 - case STM32_TIM7_BASE: - vectorno = STM32_IRQ_TIM7; - break; -#endif -#ifdef CONFIG_STM32F0L0G0_TIM13 - case STM32_TIM13_BASE: - vectorno = STM32_IRQ_TIM13; - break; -#endif -#ifdef CONFIG_STM32F0L0G0_TIM14 - case STM32_TIM14_BASE: - vectorno = STM32_IRQ_TIM14; - break; -#endif -#ifdef CONFIG_STM32F0L0G0_TIM15 - case STM32_TIM15_BASE: - vectorno = STM32_IRQ_TIM15; - break; -#endif -#ifdef CONFIG_STM32F0L0G0_TIM16 - case STM32_TIM16_BASE: - vectorno = STM32_IRQ_TIM16; - break; -#endif -#ifdef CONFIG_STM32F0L0G0_TIM17 - case STM32_TIM17_BASE: - vectorno = STM32_IRQ_TIM17; - break; -#endif - - default: - return -EINVAL; - } - - /* Disable interrupt when callback is removed */ - - if (!handler) - { - up_disable_irq(vectorno); - irq_detach(vectorno); - return OK; - } - - /* Otherwise set callback and enable interrupt */ - - irq_attach(vectorno, handler, arg); - up_enable_irq(vectorno); - -#ifdef CONFIG_ARCH_IRQPRIO - /* Set the interrupt priority */ - - up_prioritize_irq(vectorno, NVIC_SYSH_PRIORITY_DEFAULT); -#endif - - return OK; -} - -static void stm32_tim_enableint(struct stm32_tim_dev_s *dev, int source) -{ - DEBUGASSERT(dev != NULL); - - /* DIER_OFFSET is the same for ATIM, BTIM or GTIM */ - - stm32_modifyreg16(dev, STM32_GTIM_DIER_OFFSET, 0, source); -} - -static void stm32_tim_disableint(struct stm32_tim_dev_s *dev, int source) -{ - DEBUGASSERT(dev != NULL); - - /* DIER_OFFSET is the same for ATIM, BTIM or GTIM */ - - stm32_modifyreg16(dev, STM32_GTIM_DIER_OFFSET, source, 0); -} - -static void stm32_tim_ackint(struct stm32_tim_dev_s *dev, int source) -{ - /* SR_OFFSET is the same for ATIM, BTIM or GTIM */ - - stm32_putreg16(dev, STM32_GTIM_SR_OFFSET, ~source); -} - -/**************************************************************************** - * General Functions - ****************************************************************************/ - -static int stm32_tim_setmode(struct stm32_tim_dev_s *dev, - stm32_tim_mode_t mode) -{ - tmrinfo("Set mode=%d\n", mode); - uint16_t val = GTIM_CR1_CEN | GTIM_CR1_ARPE; - - DEBUGASSERT(dev != NULL); - - /* This function is not supported on basic timers. To enable or - * disable it, simply set its clock to valid frequency or zero. - */ - -#ifdef STM32_TIM6_BASE - if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM6_BASE) - { - return -EINVAL; - } -#endif - -#ifdef STM32_TIM7_BASE - if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM7_BASE) - { - return -EINVAL; - } -#endif - - /* Decode operational modes */ - - switch (mode & STM32_TIM_MODE_MASK) - { - case STM32_TIM_MODE_DISABLED: - val = 0; - break; - - case STM32_TIM_MODE_DOWN: - val |= GTIM_CR1_DIR; - - case STM32_TIM_MODE_UP: - break; - - case STM32_TIM_MODE_UPDOWN: - val |= GTIM_CR1_CENTER1; - - /* Our default: Interrupts are generated on compare, when counting - * down - */ - - break; - - case STM32_TIM_MODE_PULSE: - val |= GTIM_CR1_OPM; - break; - - default: - return -EINVAL; - } - - stm32_tim_reload_counter(dev); - - /* CR1_OFFSET is the same for ATIM, BTIM or GTIM */ - - stm32_putreg16(dev, STM32_GTIM_CR1_OFFSET, val); - - /* Advanced registers require Main Output Enable */ -#if defined(CONFIG_STM32F0L0G0_TIM1) || defined(CONFIG_STM32F0L0G0_TIM8) - if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM1_BASE -# if defined(CONFIG_STM32F0L0G0_TIM8) - || ((struct stm32_tim_priv_s *)dev)->base == STM32_TIM8_BASE -# endif - ) - { - stm32_modifyreg16(dev, STM32_ATIM_BDTR_OFFSET, 0, ATIM_BDTR_MOE); - } -#endif /* CONFIG_STM32F0L0G0_TIM1 || CONFIG_STM32F0L0G0_TIM8 */ - - return OK; -} - -static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, - uint8_t channel, stm32_tim_channel_t mode) -{ - uint16_t ccmr_orig = 0; - uint16_t ccmr_val = 0; - uint16_t ccmr_mask = 0xff; - - /* CCER_OFFSET and CCMR1_OFFSET are the same for ATIM and GTIM */ - - uint16_t ccer_val = stm32_getreg16(dev, STM32_GTIM_CCER_OFFSET); - uint8_t ccmr_offset = STM32_GTIM_CCMR1_OFFSET; - - DEBUGASSERT(dev != NULL); - - /* Further we use range as 0..3; if channel=0 it will also overflow here */ - - if (--channel > 4) - { - return -EINVAL; - } - - /* Assume that channel is disabled and polarity is active high */ - - ccer_val &= ~((GTIM_CCER_CC1P | GTIM_CCER_CC1E) << - GTIM_CCER_CCXBASE(channel)); - - /* This function is not supported on basic timers. To enable or - * disable it, simply set its clock to valid frequency or zero. - */ - -#ifdef STM32_TIM6_BASE - if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM6_BASE) - { - return -EINVAL; - } -#endif - -#ifdef STM32_TIM7_BASE - if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM7_BASE) - { - return -EINVAL; - } -#endif - - /* Decode configuration */ - - switch (mode & STM32_TIM_CH_MODE_MASK) - { - case STM32_TIM_CH_DISABLED: - break; - - case STM32_TIM_CH_OUTPWM: - ccmr_val = (GTIM_CCMR_MODE_PWM1 << GTIM_CCMR1_OC1M_SHIFT) + - GTIM_CCMR1_OC1PE; - ccer_val |= GTIM_CCER_CC1E << GTIM_CCER_CCXBASE(channel); - break; - - default: - return -EINVAL; - } - - /* Set polarity */ - - if (mode & STM32_TIM_CH_POLARITY_NEG) - { - ccer_val |= GTIM_CCER_CC1P << GTIM_CCER_CCXBASE(channel); - } - - /* Define its position (shift) and get register offset */ - - if (channel & 1) - { - ccmr_val <<= 8; - ccmr_mask <<= 8; - } - - if (channel > 1) - { - ccmr_offset = STM32_GTIM_CCMR2_OFFSET; - } - - ccmr_orig = stm32_getreg16(dev, ccmr_offset); - ccmr_orig &= ~ccmr_mask; - ccmr_orig |= ccmr_val; - stm32_putreg16(dev, ccmr_offset, ccmr_orig); - stm32_putreg16(dev, STM32_GTIM_CCER_OFFSET, ccer_val); - - /* set GPIO */ - - switch (((struct stm32_tim_priv_s *)dev)->base) - { -#ifdef CONFIG_STM32F0L0G0_TIM1 - case STM32_TIM1_BASE: - switch (channel) - { -# if defined(GPIO_TIM1_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM1_CH1OUT, mode); break; -# endif -# if defined(GPIO_TIM1_CH2OUT) - case 1: - stm32_tim_gpioconfig(GPIO_TIM1_CH2OUT, mode); break; -# endif -# if defined(GPIO_TIM1_CH3OUT) - case 2: - stm32_tim_gpioconfig(GPIO_TIM1_CH3OUT, mode); break; -# endif -# if defined(GPIO_TIM1_CH4OUT) - case 3: - stm32_tim_gpioconfig(GPIO_TIM1_CH4OUT, mode); break; -# endif -# if defined(GPIO_TIM1_CH5OUT) - case 4: - stm32_tim_gpioconfig(GPIO_TIM1_CH5OUT, mode); break; -# endif -# if defined(GPIO_TIM1_CH6OUT) - case 5: - stm32_tim_gpioconfig(GPIO_TIM1_CH6OUT, mode); break; -# endif - default: - return -EINVAL; - } - break; -#endif - -#ifdef CONFIG_STM32F0L0G0_TIM2 - case STM32_TIM2_BASE: - switch (channel) - { -# if defined(GPIO_TIM2_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM2_CH1OUT, mode); - break; -# endif -# if defined(GPIO_TIM2_CH2OUT) - case 1: - stm32_tim_gpioconfig(GPIO_TIM2_CH2OUT, mode); - break; -# endif -# if defined(GPIO_TIM2_CH3OUT) - case 2: - stm32_tim_gpioconfig(GPIO_TIM2_CH3OUT, mode); - break; -# endif -# if defined(GPIO_TIM2_CH4OUT) - case 3: - stm32_tim_gpioconfig(GPIO_TIM2_CH4OUT, mode); - break; -#endif - default: - return -EINVAL; - } - break; -#endif - -#ifdef CONFIG_STM32F0L0G0_TIM3 - case STM32_TIM3_BASE: - switch (channel) - { -# if defined(GPIO_TIM3_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM3_CH1OUT, mode); - break; -# endif -# if defined(GPIO_TIM3_CH2OUT) - case 1: - stm32_tim_gpioconfig(GPIO_TIM3_CH2OUT, mode); - break; -# endif -# if defined(GPIO_TIM3_CH3OUT) - case 2: - stm32_tim_gpioconfig(GPIO_TIM3_CH3OUT, mode); - break; -# endif -# if defined(GPIO_TIM3_CH4OUT) - case 3: - stm32_tim_gpioconfig(GPIO_TIM3_CH4OUT, mode); - break; -#endif - default: - return -EINVAL; - } - break; -#endif - -#ifdef CONFIG_STM32F0L0G0_TIM13 - case STM32_TIM13_BASE: - switch (channel) - { -# if defined(GPIO_TIM13_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM13_CH1OUT, mode); - break; -# endif - default: - return -EINVAL; - } - break; -#endif - -#ifdef CONFIG_STM32F0L0G0_TIM14 - case STM32_TIM14_BASE: - switch (channel) - { -# if defined(GPIO_TIM14_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM14_CH1OUT, mode); - break; -# endif - default: - return -EINVAL; - } - break; -#endif - -#ifdef CONFIG_STM32F0L0G0_TIM15 - case STM32_TIM15_BASE: - switch (channel) - { -# if defined(GPIO_TIM15_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM15_CH1OUT, mode); - break; -# endif -# if defined(GPIO_TIM15_CH2OUT) - case 1: - stm32_tim_gpioconfig(GPIO_TIM15_CH2OUT, mode); - break; -# endif - default: - return -EINVAL; - } - break; -#endif - -#ifdef CONFIG_STM32F0L0G0_TIM16 - case STM32_TIM16_BASE: - switch (channel) - { -# if defined(GPIO_TIM16_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM16_CH1OUT, mode); - break; -# endif - default: - return -EINVAL; - } - break; -#endif - -#ifdef CONFIG_STM32F0L0G0_TIM17 - case STM32_TIM17_BASE: - switch (channel) - { -# if defined(GPIO_TIM17_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM17_CH1OUT, mode); - break; -# endif - default: - return -EINVAL; - } - break; -#endif - } - - return OK; -} - -static int stm32_tim_setcompare(struct stm32_tim_dev_s *dev, - uint8_t channel, uint32_t compare) -{ - DEBUGASSERT(dev != NULL); - - switch (channel) - { - case 1: - stm32_putreg32(dev, STM32_GTIM_CCR1_OFFSET, compare); - break; - - case 2: - stm32_putreg32(dev, STM32_GTIM_CCR2_OFFSET, compare); - break; - - case 3: - stm32_putreg32(dev, STM32_GTIM_CCR3_OFFSET, compare); - break; - - case 4: - stm32_putreg32(dev, STM32_GTIM_CCR4_OFFSET, compare); - break; - - default: - return -EINVAL; - } - - return OK; -} - -static int stm32_tim_getcapture(struct stm32_tim_dev_s *dev, - uint8_t channel) -{ - DEBUGASSERT(dev != NULL); - - switch (channel) - { - case 1: - return stm32_getreg32(dev, STM32_GTIM_CCR1_OFFSET); - - case 2: - return stm32_getreg32(dev, STM32_GTIM_CCR2_OFFSET); - - case 3: - return stm32_getreg32(dev, STM32_GTIM_CCR3_OFFSET); - - case 4: - return stm32_getreg32(dev, STM32_GTIM_CCR4_OFFSET); - } - - return -EINVAL; -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -struct stm32_tim_dev_s *stm32_tim_init(int timer) -{ - struct stm32_tim_dev_s *dev = NULL; - - /* Get structure and enable power */ - - switch (timer) - { -#ifdef CONFIG_STM32F0L0G0_TIM1 - case 1: - dev = (struct stm32_tim_dev_s *)&stm32_tim1_priv; - modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM1EN); - break; -#endif -#ifdef CONFIG_STM32F0L0G0_TIM2 - case 2: - dev = (struct stm32_tim_dev_s *)&stm32_tim2_priv; - modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM2EN); - break; -#endif -#ifdef CONFIG_STM32F0L0G0_TIM3 - case 3: - dev = (struct stm32_tim_dev_s *)&stm32_tim3_priv; - modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM3EN); - break; -#endif -#ifdef CONFIG_STM32F0L0G0_TIM4 - case 4: - dev = (struct stm32_tim_dev_s *)&stm32_tim4_priv; - modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM4EN); - break; -#endif -#ifdef CONFIG_STM32F0L0G0_TIM5 - case 5: - dev = (struct stm32_tim_dev_s *)&stm32_tim5_priv; - modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM5EN); - break; -#endif -#ifdef CONFIG_STM32F0L0G0_TIM6 - case 6: - dev = (struct stm32_tim_dev_s *)&stm32_tim6_priv; - modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM6EN); - break; -#endif -#ifdef CONFIG_STM32F0L0G0_TIM7 - case 7: - dev = (struct stm32_tim_dev_s *)&stm32_tim7_priv; - modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM7EN); - break; -#endif -#ifdef CONFIG_STM32F0L0G0_TIM8 - case 8: - dev = (struct stm32_tim_dev_s *)&stm32_tim8_priv; - modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM8EN); - break; -#endif -#ifdef CONFIG_STM32F0L0G0_TIM12 - case 12: - dev = (struct stm32_tim_dev_s *)&stm32_tim12_priv; - modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM12EN); - break; -#endif -#ifdef CONFIG_STM32F0L0G0_TIM13 - case 13: - dev = (struct stm32_tim_dev_s *)&stm32_tim13_priv; - modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM13EN); - break; -#endif -#ifdef CONFIG_STM32F0L0G0_TIM14 - case 14: - dev = (struct stm32_tim_dev_s *)&stm32_tim14_priv; - modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM14EN); - break; -#endif -#ifdef CONFIG_STM32F0L0G0_TIM15 - case 15: - dev = (struct stm32_tim_dev_s *)&stm32_tim15_priv; - modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM15EN); - break; -#endif -#ifdef CONFIG_STM32F0L0G0_TIM16 - case 16: - dev = (struct stm32_tim_dev_s *)&stm32_tim16_priv; - modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM16EN); - break; -#endif -#ifdef CONFIG_STM32F0L0G0_TIM17 - case 17: - dev = (struct stm32_tim_dev_s *)&stm32_tim17_priv; - modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM17EN); - break; -#endif - default: - return NULL; - } - - /* Is device already allocated */ - - if (((struct stm32_tim_priv_s *)dev)->mode != STM32_TIM_MODE_UNUSED) - { - return NULL; - } - - stm32_tim_reset(dev); - - return dev; -} - -/* TODO: Detach interrupts, and close down all TIM Channels */ - -int stm32_tim_deinit(struct stm32_tim_dev_s * dev) -{ - DEBUGASSERT(dev != NULL); - - /* Disable power */ - - switch (((struct stm32_tim_priv_s *)dev)->base) - { -#ifdef CONFIG_STM32F0L0G0_TIM1 - case STM32_TIM1_BASE: - modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM1EN, 0); - break; -#endif -#ifdef CONFIG_STM32F0L0G0_TIM2 - case STM32_TIM2_BASE: - modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM2EN, 0); - break; -#endif -#ifdef CONFIG_STM32F0L0G0_TIM3 - case STM32_TIM3_BASE: - modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM3EN, 0); - break; -#endif -#ifdef CONFIG_STM32F0L0G0_TIM4 - case STM32_TIM4_BASE: - modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM4EN, 0); - break; -#endif -#ifdef CONFIG_STM32F0L0G0_TIM5 - case STM32_TIM5_BASE: - modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM5EN, 0); - break; -#endif -#ifdef CONFIG_STM32F0L0G0_TIM6 - case STM32_TIM6_BASE: - modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM6EN, 0); - break; -#endif -#ifdef CONFIG_STM32F0L0G0_TIM7 - case STM32_TIM7_BASE: - modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM7EN, 0); - break; -#endif -#ifdef CONFIG_STM32F0L0G0_TIM8 - case STM32_TIM8_BASE: - modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM8EN, 0); - break; -#endif -#ifdef CONFIG_STM32F0L0G0_TIM12 - case STM32_TIM12_BASE: - modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM12EN, 0); - break; -#endif -#ifdef CONFIG_STM32F0L0G0_TIM13 - case STM32_TIM13_BASE: - modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM13EN, 0); - break; -#endif -#ifdef CONFIG_STM32F0L0G0_TIM14 - case STM32_TIM14_BASE: - modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM14EN, 0); - break; -#endif -#ifdef CONFIG_STM32F0L0G0_TIM15 - case STM32_TIM15_BASE: - modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM15EN, 0); - break; -#endif -#ifdef CONFIG_STM32F0L0G0_TIM16 - case STM32_TIM16_BASE: - modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM16EN, 0); - break; -#endif -#ifdef CONFIG_STM32F0L0G0_TIM17 - case STM32_TIM17_BASE: - modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM17EN, 0); - break; -#endif - default: - return -EINVAL; - } - - /* Mark it as free */ - - ((struct stm32_tim_priv_s *)dev)->mode = STM32_TIM_MODE_UNUSED; - - return OK; -} - -#endif /* defined(CONFIG_STM32F0L0G0_TIM1 || ... || TIM17) */ diff --git a/arch/arm/src/stm32f0l0g0/stm32_tim.h b/arch/arm/src/stm32f0l0g0/stm32_tim.h deleted file mode 100644 index ba9d7c7fbc4b8..0000000000000 --- a/arch/arm/src/stm32f0l0g0/stm32_tim.h +++ /dev/null @@ -1,233 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_tim.h - * - * SPDX-License-Identifier: BSD-3-Clause - * SPDX-FileCopyrightText: 2019 Fundação CERTI. All rights reserved. - * SPDX-FileContributor: Daniel Pereira Volpato - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_STM32_TIM_H -#define __ARCH_ARM_SRC_STM32F0L0G0_STM32_TIM_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "chip.h" -#include "hardware/stm32_tim.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Helpers ******************************************************************/ - -#define STM32_TIM_SETMODE(d,mode) ((d)->ops->setmode(d,mode)) -#define STM32_TIM_SETCLOCK(d,freq) ((d)->ops->setclock(d,freq)) -#define STM32_TIM_GETCLOCK(d) ((d)->ops->getclock(d)) -#define STM32_TIM_SETPERIOD(d,period) ((d)->ops->setperiod(d,period)) -#define STM32_TIM_GETPERIOD(d) ((d)->ops->getperiod(d)) -#define STM32_TIM_GETCOUNTER(d) ((d)->ops->getcounter(d)) -#define STM32_TIM_GETWIDTH(d) ((d)->ops->getwidth(d)) -#define STM32_TIM_SETCHANNEL(d,ch,mode) ((d)->ops->setchannel(d,ch,mode)) -#define STM32_TIM_SETCOMPARE(d,ch,comp) ((d)->ops->setcompare(d,ch,comp)) -#define STM32_TIM_GETCAPTURE(d,ch) ((d)->ops->getcapture(d,ch)) -#define STM32_TIM_SETISR(d,hnd,arg,s) ((d)->ops->setisr(d,hnd,arg,s)) -#define STM32_TIM_ENABLEINT(d,s) ((d)->ops->enableint(d,s)) -#define STM32_TIM_DISABLEINT(d,s) ((d)->ops->disableint(d,s)) -#define STM32_TIM_ACKINT(d,s) ((d)->ops->ackint(d,s)) -#define STM32_TIM_ENABLE(d) ((d)->ops->enable(d)) -#define STM32_TIM_DISABLE(d) ((d)->ops->disable(d)) - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -#ifndef __ASSEMBLY__ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/* TIM Device Structure */ - -struct stm32_tim_dev_s -{ - struct stm32_tim_ops_s *ops; -}; - -/* TIM Modes of Operation */ - -typedef enum -{ - STM32_TIM_MODE_UNUSED = -1, - - /* One of the following */ - - STM32_TIM_MODE_MASK = 0x0310, - STM32_TIM_MODE_DISABLED = 0x0000, - STM32_TIM_MODE_UP = 0x0100, - STM32_TIM_MODE_DOWN = 0x0110, - STM32_TIM_MODE_UPDOWN = 0x0200, - STM32_TIM_MODE_PULSE = 0x0300, - - /* One of the following */ - - STM32_TIM_MODE_CK_INT = 0x0000, -#if 0 - STM32_TIM_MODE_CK_INT_TRIG = 0x0400, - STM32_TIM_MODE_CK_EXT = 0x0800, - STM32_TIM_MODE_CK_EXT_TRIG = 0x0c00, -#endif - - /* Clock sources, OR'ed with CK_EXT */ - -#if 0 - STM32_TIM_MODE_CK_CHINVALID = 0x0000, - STM32_TIM_MODE_CK_CH1 = 0x0001, - STM32_TIM_MODE_CK_CH2 = 0x0002, - STM32_TIM_MODE_CK_CH3 = 0x0003, - STM32_TIM_MODE_CK_CH4 = 0x0004 -#endif - - /* TODO external trigger block */ -} stm32_tim_mode_t; - -/* TIM Channel Modes */ - -typedef enum -{ - STM32_TIM_CH_DISABLED = 0x00, - - /* Common configuration */ - - STM32_TIM_CH_POLARITY_POS = 0x00, - STM32_TIM_CH_POLARITY_NEG = 0x01, - - /* MODES: */ - - STM32_TIM_CH_MODE_MASK = 0x06, - - /* Output Compare Modes */ - - STM32_TIM_CH_OUTPWM = 0x04, /* Enable standard PWM mode, active high when counter < compare */ -#if 0 - STM32_TIM_CH_OUTCOMPARE = 0x06, - - /* TODO other modes ... as PWM capture, ENCODER and Hall Sensor */ - - STM32_TIM_CH_INCAPTURE = 0x10, - STM32_TIM_CH_INPWM = 0x20 - STM32_TIM_CH_DRIVE_OC = open collector mode -#endif -} stm32_tim_channel_t; - -/* TIM Operations */ - -struct stm32_tim_ops_s -{ - /* Basic Timers */ - - void (*enable)(struct stm32_tim_dev_s *dev); - void (*disable)(struct stm32_tim_dev_s *dev); - int (*setmode)(struct stm32_tim_dev_s *dev, stm32_tim_mode_t mode); - int (*setclock)(struct stm32_tim_dev_s *dev, uint32_t freq); - uint32_t (*getclock)(struct stm32_tim_dev_s *dev); - void (*setperiod)(struct stm32_tim_dev_s *dev, uint32_t period); - uint32_t (*getperiod)(struct stm32_tim_dev_s *dev); - uint32_t (*getcounter)(struct stm32_tim_dev_s *dev); - int (*getwidth)(struct stm32_tim_dev_s *dev); - - /* General and Advanced Timers Adds */ - - int (*setchannel)(struct stm32_tim_dev_s *dev, uint8_t channel, - stm32_tim_channel_t mode); - int (*setcompare)(struct stm32_tim_dev_s *dev, uint8_t channel, - uint32_t compare); - int (*getcapture)(struct stm32_tim_dev_s *dev, uint8_t channel); - - /* Timer interrupts */ - - int (*setisr)(struct stm32_tim_dev_s *dev, xcpt_t handler, void *arg, - int source); - void (*enableint)(struct stm32_tim_dev_s *dev, int source); - void (*disableint)(struct stm32_tim_dev_s *dev, int source); - void (*ackint)(struct stm32_tim_dev_s *dev, int source); -}; - -/**************************************************************************** - * Public Functions Prototypes - ****************************************************************************/ - -/* Power-up timer and get its structure */ - -struct stm32_tim_dev_s *stm32_tim_init(int timer); - -/* Power-down timer, mark it as unused */ - -int stm32_tim_deinit(struct stm32_tim_dev_s *dev); - -/**************************************************************************** - * Name: stm32_timer_initialize - * - * Description: - * Bind the configuration timer to a timer lower half instance and - * register the timer drivers at 'devpath' - * - * Input Parameters: - * devpath - The full path to the timer device. This should be of the - * form /dev/timer0 - * timer - the timer number. - * - * Returned Values: - * Zero (OK) is returned on success; A negated errno value is returned - * to indicate the nature of any failure. - * - ****************************************************************************/ - -#ifdef CONFIG_TIMER -int stm32_timer_initialize(const char *devpath, int timer); -#endif - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_STM32_TIM_H */ diff --git a/arch/arm/src/stm32f0l0g0/stm32_tim_lowerhalf.c b/arch/arm/src/stm32f0l0g0/stm32_tim_lowerhalf.c deleted file mode 100644 index 25e8257960468..0000000000000 --- a/arch/arm/src/stm32f0l0g0/stm32_tim_lowerhalf.c +++ /dev/null @@ -1,668 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_tim_lowerhalf.c - * - * SPDX-License-Identifier: BSD-3-Clause - * SPDX-FileCopyrightText: 2019 Fundação CERTI. All rights reserved. - * SPDX-FileContributor: Daniel Pereira Volpato - * SPDX-FileContributor: Wail Khemir - * SPDX-FileContributor: Paul Alexander Patience - * SPDX-FileContributor: dev@ziggurat29.com - * SPDX-FileContributor: Sebastien Lorquet - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include -#include -#include -#include -#include - -#include -#include -#include - -#include - -#include "stm32_tim.h" - -#if defined(CONFIG_TIMER) && \ - (defined(CONFIG_STM32F0L0G0_TIM1) || defined(CONFIG_STM32F0L0G0_TIM2) || \ - defined(CONFIG_STM32F0L0G0_TIM3) || defined(CONFIG_STM32F0L0G0_TIM4) || \ - defined(CONFIG_STM32F0L0G0_TIM5) || defined(CONFIG_STM32F0L0G0_TIM6) || \ - defined(CONFIG_STM32F0L0G0_TIM7) || defined(CONFIG_STM32F0L0G0_TIM8) || \ - defined(CONFIG_STM32F0L0G0_TIM12) || defined(CONFIG_STM32F0L0G0_TIM13) || \ - defined(CONFIG_STM32F0L0G0_TIM14) || defined(CONFIG_STM32F0L0G0_TIM15) || \ - defined(CONFIG_STM32F0L0G0_TIM16) || defined(CONFIG_STM32F0L0G0_TIM17)) - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#define STM32_TIM1_RES 16 -#define STM32_TIM2_RES 16 -#define STM32_TIM3_RES 16 -#define STM32_TIM4_RES 16 -#define STM32_TIM5_RES 16 -#define STM32_TIM6_RES 16 -#define STM32_TIM7_RES 16 -#define STM32_TIM8_RES 16 -#define STM32_TIM9_RES 16 -#define STM32_TIM10_RES 16 -#define STM32_TIM11_RES 16 -#define STM32_TIM12_RES 16 -#define STM32_TIM13_RES 16 -#define STM32_TIM14_RES 16 -#define STM32_TIM15_RES 16 -#define STM32_TIM16_RES 16 -#define STM32_TIM17_RES 16 - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/* This structure provides the private representation of the "lower-half" - * driver state structure. This structure must be cast-compatible with the - * timer_lowerhalf_s structure. - */ - -struct stm32_lowerhalf_s -{ - const struct timer_ops_s *ops; /* Lower half operations */ - struct stm32_tim_dev_s *tim; /* stm32 timer driver */ - tccb_t callback; /* Current user interrupt callback */ - void *arg; /* Argument passed to upper half callback */ - bool started; /* True: Timer has been started */ - const uint8_t resolution; /* Number of bits in the timer (16 or 32 bits) */ -}; - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -static int stm32_timer_handler(int irq, void * context, void * arg); - -/* "Lower half" driver methods **********************************************/ - -static int stm32_start(struct timer_lowerhalf_s *lower); -static int stm32_stop(struct timer_lowerhalf_s *lower); -static int stm32_getstatus(struct timer_lowerhalf_s *lower, - struct timer_status_s *status); -static int stm32_settimeout(struct timer_lowerhalf_s *lower, - uint32_t timeout); -static void stm32_setcallback(struct timer_lowerhalf_s *lower, - tccb_t callback, void *arg); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* "Lower half" driver methods */ - -static const struct timer_ops_s g_timer_ops = -{ - .start = stm32_start, - .stop = stm32_stop, - .getstatus = stm32_getstatus, - .settimeout = stm32_settimeout, - .setcallback = stm32_setcallback, - .ioctl = NULL, -}; - -#ifdef CONFIG_STM32F0L0G0_TIM1 -static struct stm32_lowerhalf_s g_tim1_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM1_RES, -}; -#endif - -#ifdef CONFIG_STM32F0L0G0_TIM2 -static struct stm32_lowerhalf_s g_tim2_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM2_RES, -}; -#endif - -#ifdef CONFIG_STM32F0L0G0_TIM3 -static struct stm32_lowerhalf_s g_tim3_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM3_RES, -}; -#endif - -#ifdef CONFIG_STM32F0L0G0_TIM4 -static struct stm32_lowerhalf_s g_tim4_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM4_RES, -}; -#endif - -#ifdef CONFIG_STM32F0L0G0_TIM5 -static struct stm32_lowerhalf_s g_tim5_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM5_RES, -}; -#endif - -#ifdef CONFIG_STM32F0L0G0_TIM6 -static struct stm32_lowerhalf_s g_tim6_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM6_RES, -}; -#endif - -#ifdef CONFIG_STM32F0L0G0_TIM7 -static struct stm32_lowerhalf_s g_tim7_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM7_RES, -}; -#endif - -#ifdef CONFIG_STM32F0L0G0_TIM8 -static struct stm32_lowerhalf_s g_tim8_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM8_RES, -}; -#endif - -#ifdef CONFIG_STM32F0L0G0_TIM12 -static struct stm32_lowerhalf_s g_tim12_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM12_RES, -}; -#endif - -#ifdef CONFIG_STM32F0L0G0_TIM13 -static struct stm32_lowerhalf_s g_tim13_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM13_RES, -}; -#endif - -#ifdef CONFIG_STM32F0L0G0_TIM14 -static struct stm32_lowerhalf_s g_tim14_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM14_RES, -}; -#endif - -#ifdef CONFIG_STM32F0L0G0_TIM15 -static struct stm32_lowerhalf_s g_tim15_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM15_RES, -}; -#endif - -#ifdef CONFIG_STM32F0L0G0_TIM16 -static struct stm32_lowerhalf_s g_tim16_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM16_RES, -}; -#endif - -#ifdef CONFIG_STM32F0L0G0_TIM17 -static struct stm32_lowerhalf_s g_tim17_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM17_RES, -}; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_timer_handler - * - * Description: - * timer interrupt handler - * - * Input Parameters: - * - * Returned Value: - * - ****************************************************************************/ - -static int stm32_timer_handler(int irq, void * context, void * arg) -{ - struct stm32_lowerhalf_s *lower = (struct stm32_lowerhalf_s *) arg; - uint32_t next_interval_us = 0; - - STM32_TIM_ACKINT(lower->tim, ATIM_DIER_UIE); - - if (lower->callback(&next_interval_us, lower->arg)) - { - if (next_interval_us > 0) - { - STM32_TIM_SETPERIOD(lower->tim, next_interval_us); - } - } - else - { - stm32_stop((struct timer_lowerhalf_s *)lower); - } - - return OK; -} - -/**************************************************************************** - * Name: stm32_start - * - * Description: - * Start the timer, resetting the time to the current timeout, - * - * Input Parameters: - * lower - A pointer the publicly visible representation of the - * "lower-half" driver state structure. - * - * Returned Value: - * Zero on success; a negated errno value on failure. - * - ****************************************************************************/ - -static int stm32_start(struct timer_lowerhalf_s *lower) -{ - struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; - - tmrinfo("Start\n"); - - if (!priv->started) - { - STM32_TIM_SETMODE(priv->tim, STM32_TIM_MODE_UP); - - if (priv->callback != NULL) - { - STM32_TIM_SETISR(priv->tim, stm32_timer_handler, priv, 0); - STM32_TIM_ENABLEINT(priv->tim, ATIM_DIER_UIE); - } - - priv->started = true; - return OK; - } - - /* Return EBUSY to indicate that the timer was already running */ - - return -EBUSY; -} - -/**************************************************************************** - * Name: stm32_stop - * - * Description: - * Stop the timer - * - * Input Parameters: - * lower - A pointer the publicly visible representation of the - * "lower-half" driver state structure. - * - * Returned Value: - * Zero on success; a negated errno value on failure. - * - ****************************************************************************/ - -static int stm32_stop(struct timer_lowerhalf_s *lower) -{ - struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; - - if (priv->started) - { - STM32_TIM_SETMODE(priv->tim, STM32_TIM_MODE_DISABLED); - STM32_TIM_DISABLEINT(priv->tim, ATIM_DIER_UIE); - STM32_TIM_SETISR(priv->tim, NULL, NULL, 0); - priv->started = false; - return OK; - } - - /* Return ENODEV to indicate that the timer was not running */ - - return -ENODEV; -} - -/**************************************************************************** - * Name: stm32_getstatus - * - * Description: - * get timer status - * - * Input Parameters: - * lower - A pointer the publicly visible representation of the "lower- - * half" driver state structure. - * status - The location to return the status information. - * - * Returned Value: - * Zero on success; a negated errno value on failure. - * - ****************************************************************************/ - -static int stm32_getstatus(struct timer_lowerhalf_s *lower, - struct timer_status_s *status) -{ - struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; - uint32_t timeout; - uint32_t clock; - uint32_t period; - uint32_t counter; - - DEBUGASSERT(priv); - - /* Return the status bit */ - - status->flags = 0; - if (priv->started) - { - status->flags |= TCFLAGS_ACTIVE; - } - - if (priv->callback) - { - status->flags |= TCFLAGS_HANDLER; - } - - /* Get timeout */ - - clock = STM32_TIM_GETCLOCK(priv->tim); - period = STM32_TIM_GETPERIOD(priv->tim); - - if (clock == 1000000) - { - timeout = period; - } - else - { - timeout = ((uint64_t)period * 1000000) / clock; - } - - status->timeout = timeout; - - /* Get the time remaining until the timer expires (in microseconds) */ - - counter = STM32_TIM_GETCOUNTER(priv->tim); - status->timeleft = ((uint64_t)(timeout - counter) * clock) / 1000000; - tmrinfo("timeout=%" PRIu32 " counter=%" PRIu32 "\n", timeout, counter); - tmrinfo("timeleft=%" PRIu32 "\n", status->timeleft); - return OK; -} - -/**************************************************************************** - * Name: stm32_settimeout - * - * Description: - * Set a new timeout value (and reset the timer) - * - * Input Parameters: - * lower - A pointer the publicly visible representation of the "lower- - * half" driver state structure. - * timeout - The new timeout value in microseconds. - * - * Returned Value: - * Zero on success; a negated errno value on failure. - * - ****************************************************************************/ - -static int stm32_settimeout(struct timer_lowerhalf_s *lower, - uint32_t timeout) -{ - struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; - uint64_t maxtimeout; - uint32_t clock; - uint32_t period; - - if (priv->started) - { - return -EPERM; - } - - tmrinfo("Set timeout=%" PRId32 "\n", timeout); - - maxtimeout = ((uint64_t)1 << priv->resolution) - 1; - if (timeout > maxtimeout) - { - uint64_t freq = (maxtimeout * 1000000) / timeout; - clock = (uint32_t) freq; - period = (uint32_t) maxtimeout; - } - else - { - clock = (uint32_t) 1000000; - period = (uint32_t) timeout; - } - - tmrinfo(" clock=%" PRIu32 " period=%" PRIu32 " maxtimeout=%" PRIu32 "\n", - clock, period, (uint32_t)maxtimeout); - STM32_TIM_SETCLOCK(priv->tim, clock); - STM32_TIM_SETPERIOD(priv->tim, period); - - return OK; -} - -/**************************************************************************** - * Name: stm32_setcallback - * - * Description: - * Call this user provided timeout callback. - * - * Input Parameters: - * lower - A pointer the publicly visible representation of the - * "lower-half" driver state structure. - * callback - The new timer expiration function pointer. If this - * function pointer is NULL, then the reset-on-expiration - * behavior is restored, - * arg - Argument that will be provided in the callback - * - * Returned Value: - * The previous timer expiration function pointer or NULL is there was - * no previous function pointer. - * - ****************************************************************************/ - -static void stm32_setcallback(struct timer_lowerhalf_s *lower, - tccb_t callback, void *arg) -{ - struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; - - irqstate_t flags = enter_critical_section(); - - /* Save the new callback */ - - priv->callback = callback; - priv->arg = arg; - - if (callback != NULL && priv->started) - { - STM32_TIM_SETISR(priv->tim, stm32_timer_handler, priv, 0); - STM32_TIM_ENABLEINT(priv->tim, ATIM_DIER_UIE); - } - else - { - STM32_TIM_DISABLEINT(priv->tim, ATIM_DIER_UIE); - STM32_TIM_SETISR(priv->tim, NULL, NULL, 0); - } - - leave_critical_section(flags); -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_timer_initialize - * - * Description: - * Bind the configuration timer to a timer lower half instance and - * register the timer drivers at 'devpath' - * - * Input Parameters: - * devpath - The full path to the timer device. This should be of the - * form /dev/timer0 - * timer - the timer's number. - * - * Returned Value: - * Zero (OK) is returned on success; A negated errno value is returned - * to indicate the nature of any failure. - * - ****************************************************************************/ - -int stm32_timer_initialize(const char *devpath, int timer) -{ - struct stm32_lowerhalf_s *lower; - - tmrinfo("Init TIM%d\n", timer); - - switch (timer) - { -#ifdef CONFIG_STM32F0L0G0_TIM1 - case 1: - lower = &g_tim1_lowerhalf; - break; -#endif -#ifdef CONFIG_STM32F0L0G0_TIM2 - case 2: - lower = &g_tim2_lowerhalf; - break; -#endif -#ifdef CONFIG_STM32F0L0G0_TIM3 - case 3: - lower = &g_tim3_lowerhalf; - break; -#endif -#ifdef CONFIG_STM32F0L0G0_TIM4 - case 4: - lower = &g_tim4_lowerhalf; - break; -#endif -#ifdef CONFIG_STM32F0L0G0_TIM5 - case 5: - lower = &g_tim5_lowerhalf; - break; -#endif -#ifdef CONFIG_STM32F0L0G0_TIM6 - case 6: - lower = &g_tim6_lowerhalf; - break; -#endif -#ifdef CONFIG_STM32F0L0G0_TIM7 - case 7: - lower = &g_tim7_lowerhalf; - break; -#endif -#ifdef CONFIG_STM32F0L0G0_TIM8 - case 8: - lower = &g_tim8_lowerhalf; - break; -#endif -#ifdef CONFIG_STM32F0L0G0_TIM12 - case 12: - lower = &g_tim12_lowerhalf; - break; -#endif -#ifdef CONFIG_STM32F0L0G0_TIM13 - case 13: - lower = &g_tim13_lowerhalf; - break; -#endif -#ifdef CONFIG_STM32F0L0G0_TIM14 - case 14: - lower = &g_tim14_lowerhalf; - break; -#endif -#ifdef CONFIG_STM32F0L0G0_TIM15 - case 15: - lower = &g_tim15_lowerhalf; - break; -#endif -#ifdef CONFIG_STM32F0L0G0_TIM16 - case 16: - lower = &g_tim16_lowerhalf; - break; -#endif -#ifdef CONFIG_STM32F0L0G0_TIM17 - case 17: - lower = &g_tim17_lowerhalf; - break; -#endif - default: - return -ENODEV; - } - - /* Initialize the elements of lower half state structure */ - - lower->started = false; - lower->callback = NULL; - lower->tim = stm32_tim_init(timer); - - if (lower->tim == NULL) - { - return -EINVAL; - } - - /* Register the timer driver as /dev/timerX. The returned value from - * timer_register is a handle that could be used with timer_unregister(). - * REVISIT: The returned handle is discard here. - */ - - void *drvr = timer_register(devpath, - (struct timer_lowerhalf_s *)lower); - if (drvr == NULL) - { - /* The actual cause of the failure may have been a failure to allocate - * perhaps a failure to register the timer driver (such as if the - * 'depath' were not unique). We know here but we return EEXIST to - * indicate the failure (implying the non-unique devpath). - */ - - return -EEXIST; - } - - return OK; -} - -#endif /* CONFIG_TIMER */ diff --git a/arch/arm/src/stm32f0l0g0/stm32_timerisr.c b/arch/arm/src/stm32f0l0g0/stm32_timerisr.c deleted file mode 100644 index 5a0737c414442..0000000000000 --- a/arch/arm/src/stm32f0l0g0/stm32_timerisr.c +++ /dev/null @@ -1,152 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_timerisr.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include -#include - -#include "nvic.h" -#include "clock/clock.h" -#include "arm_internal.h" -#include "chip.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* "The CLKSOURCE bit in SysTick Control and Status register selects either - * the core clock (when CLKSOURCE = 1) or a divide-by-16 of the core clock - * (when CLKSOURCE = 0). ..." - */ - -#if defined(CONFIG_STM32F0L0G0_SYSTICK_CORECLK) -# define SYSTICK_CLOCK STM32_SYSCLK_FREQUENCY /* Core clock */ -#elif defined(CONFIG_STM32F0L0G0_SYSTICK_CORECLK_DIV16) -# define SYSTICK_CLOCK (STM32_SYSCLK_FREQUENCY / 16) /* Core clock divided by 16 */ -#endif - -/* The desired timer interrupt frequency is provided by the definition - * CLK_TCK (see include/time.h). CLK_TCK defines the desired number of - * system clock ticks per second. That value is a user configurable setting - * that defaults to 100 (100 ticks per second = 10 MS interval). - * - * Then, for example, if the external high speed crystal is the SysTick - * clock source and BOARD_XTALHI_FREQUENCY is 12MHz and CLK_TCK is 100, then - * the reload value would be: - * - * SYSTICK_RELOAD = (12,000,000 / 100) - 1 - * = 119,999 - * = 0x1d4bf - * - * Which fits within the maximum 24-bit reload value. - */ - -#define SYSTICK_RELOAD ((SYSTICK_CLOCK / CLK_TCK) - 1) - -/* The size of the reload field is 24 bits. Verify that the reload value - * will fit in the reload register. - */ - -#if SYSTICK_RELOAD > 0x00ffffff -# error SYSTICK_RELOAD exceeds the range of the RELOAD register -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Function: stm32_timerisr - * - * Description: - * The timer ISR will perform a variety of services for various portions - * of the systems. - * - ****************************************************************************/ - -static int stm32_timerisr(int irq, uint32_t *regs, void *arg) -{ - /* Process timer interrupt */ - - nxsched_process_timer(); - return 0; -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Function: up_timer_initialize - * - * Description: - * This function is called during start-up to initialize - * the timer interrupt. - * - ****************************************************************************/ - -void up_timer_initialize(void) -{ - uint32_t regval; - - /* Set the SysTick interrupt to the default priority */ - - regval = getreg32(ARMV6M_SYSCON_SHPR3); - regval &= ~SYSCON_SHPR3_PRI_15_MASK; - regval |= (NVIC_SYSH_PRIORITY_DEFAULT << SYSCON_SHPR3_PRI_15_SHIFT); - putreg32(regval, ARMV6M_SYSCON_SHPR3); - - /* Configure SysTick to interrupt at the requested rate */ - - putreg32(SYSTICK_RELOAD, ARMV6M_SYSTICK_RVR); - - /* Attach the timer interrupt vector */ - - irq_attach(STM32_IRQ_SYSTICK, (xcpt_t)stm32_timerisr, NULL); - - /* Enable SysTick interrupts. "The CLKSOURCE bit in SysTick Control and - * Status register selects either the core clock (when CLKSOURCE = 1) or - * a divide-by-16 of the core clock (when CLKSOURCE = 0). ..." - */ - -#ifdef CONFIG_STM32F0L0G0_SYSTICK_CORECLK - putreg32((SYSTICK_CSR_CLKSOURCE | - SYSTICK_CSR_TICKINT | - SYSTICK_CSR_ENABLE), - ARMV6M_SYSTICK_CSR); -#else - putreg32((SYSTICK_CSR_TICKINT | SYSTICK_CSR_ENABLE), ARMV6M_SYSTICK_CSR); -#endif - - /* And enable the timer interrupt */ - - up_enable_irq(STM32_IRQ_SYSTICK); -} diff --git a/arch/arm/src/stm32f0l0g0/stm32_uart.h b/arch/arm/src/stm32f0l0g0/stm32_uart.h deleted file mode 100644 index 92e2e7ceb777f..0000000000000 --- a/arch/arm/src/stm32f0l0g0/stm32_uart.h +++ /dev/null @@ -1,452 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_uart.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_STM32_UART_H -#define __ARCH_ARM_SRC_STM32F0L0G0_STM32_UART_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "chip.h" - -#include "hardware/stm32_uart.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Make sure that we have not enabled more U[S]ARTs than are supported by the - * device. - */ - -#if STM32_NUSART < 8 || !defined(CONFIG_STM32F0L0G0_HAVE_USART8) -# undef CONFIG_STM32F0L0G0_USART8 -#endif -#if STM32_NUSART < 7 || !defined(CONFIG_STM32F0L0G0_HAVE_USART7) -# undef CONFIG_STM32F0L0G0_USART7 -#endif -#if STM32_NUSART < 6 || !defined(CONFIG_STM32F0L0G0_HAVE_USART6) -# undef CONFIG_STM32F0L0G0_USART6 -#endif -#if STM32_NUSART < 5 || !defined(CONFIG_STM32F0L0G0_HAVE_USART5) -# undef CONFIG_STM32F0L0G0_USART5 -#endif -#if STM32_NUSART < 4 || !defined(CONFIG_STM32F0L0G0_HAVE_USART4) -# undef CONFIG_STM32F0L0G0_USART4 -#endif -#if STM32_NUSART < 3 || !defined(CONFIG_STM32F0L0G0_HAVE_USART3) -# undef CONFIG_STM32F0L0G0_USART3 -#endif -#if STM32_NUSART < 2 -# undef CONFIG_STM32F0L0G0_USART2 -#endif -#if STM32_NUSART < 1 -# undef CONFIG_STM32F0L0G0_USART1 -#endif - -/* USART 3-8 are multiplexed to the same interrupt. Current interrupt - * handling logic will support only one USART in that range. That is - * not an issue for currently supported chips but could become an - * issue in the future. - */ - -#if defined(CONFIG_STM32F0L0G0_USART3) -# undef CONFIG_STM32F0L0G0_USART4 -# undef CONFIG_STM32F0L0G0_USART5 -# undef CONFIG_STM32F0L0G0_USART6 -# undef CONFIG_STM32F0L0G0_USART7 -# undef CONFIG_STM32F0L0G0_USART8 -#elif defined(CONFIG_STM32F0L0G0_USART4) -# undef CONFIG_STM32F0L0G0_USART5 -# undef CONFIG_STM32F0L0G0_USART6 -# undef CONFIG_STM32F0L0G0_USART7 -# undef CONFIG_STM32F0L0G0_USART8 -#elif defined(CONFIG_STM32F0L0G0_USART5) -# undef CONFIG_STM32F0L0G0_USART6 -# undef CONFIG_STM32F0L0G0_USART7 -# undef CONFIG_STM32F0L0G0_USART8 -#elif defined(CONFIG_STM32F0L0G0_USART6) -# undef CONFIG_STM32F0L0G0_USART7 -# undef CONFIG_STM32F0L0G0_USART8 -#elif defined(CONFIG_STM32F0L0G0_USART7) -# undef CONFIG_STM32F0L0G0_USART8 -#endif - -/* Is there a USART enabled? */ - -#if defined(CONFIG_STM32F0L0G0_USART1) || defined(CONFIG_STM32F0L0G0_USART2) || \ - defined(CONFIG_STM32F0L0G0_USART3) || defined(CONFIG_STM32F0L0G0_USART4) || \ - defined(CONFIG_STM32F0L0G0_USART5) || defined(CONFIG_STM32F0L0G0_USART6) || \ - defined(CONFIG_STM32F0L0G0_USART7) || defined(CONFIG_STM32F0L0G0_USART8) -# define HAVE_USART 1 -#endif - -/* Sanity checks */ - -#if !defined(CONFIG_STM32F0L0G0_USART1) -# undef CONFIG_STM32F0L0G0_USART1_SERIALDRIVER -# undef CONFIG_STM32F0L0G0_USART1_1WIREDRIVER -#endif -#if !defined(CONFIG_STM32F0L0G0_USART2) -# undef CONFIG_STM32F0L0G0_USART2_SERIALDRIVER -# undef CONFIG_STM32F0L0G0_USART2_1WIREDRIVER -#endif -#if !defined(CONFIG_STM32F0L0G0_USART3) -# undef CONFIG_STM32F0L0G0_USART3_SERIALDRIVER -# undef CONFIG_STM32F0L0G0_USART3_1WIREDRIVER -#endif -#if !defined(CONFIG_STM32F0L0G0_USART4) -# undef CONFIG_STM32F0L0G0_USART4_SERIALDRIVER -# undef CONFIG_STM32F0L0G0_USART4_1WIREDRIVER -#endif -#if !defined(CONFIG_STM32F0L0G0_USART5) -# undef CONFIG_STM32F0L0G0_USART5_SERIALDRIVER -# undef CONFIG_STM32F0L0G0_USART5_1WIREDRIVER -#endif -#if !defined(CONFIG_STM32F0L0G0_USART6) -# undef CONFIG_STM32F0L0G0_USART6_SERIALDRIVER -# undef CONFIG_STM32F0L0G0_USART6_1WIREDRIVER -#endif -#if !defined(CONFIG_STM32F0L0G0_USART7) -# undef CONFIG_STM32F0L0G0_USART7_SERIALDRIVER -# undef CONFIG_STM32F0L0G0_USART7_1WIREDRIVER -#endif -#if !defined(CONFIG_STM32F0L0G0_USART8) -# undef CONFIG_STM32F0L0G0_USART8_SERIALDRIVER -# undef CONFIG_STM32F0L0G0_USART8_1WIREDRIVER -#endif - -/* Check 1-Wire and U(S)ART conflicts */ - -#if defined(CONFIG_STM32F0L0G0_USART1_1WIREDRIVER) && defined(CONFIG_STM32F0L0G0_USART1_SERIALDRIVER) -# error Both CONFIG_STM32F0L0G0_USART1_1WIREDRIVER and CONFIG_STM32F0L0G0_USART1_SERIALDRIVER defined -# undef CONFIG_STM32F0L0G0_USART1_1WIREDRIVER -#endif -#if defined(CONFIG_STM32F0L0G0_USART2_1WIREDRIVER) && defined(CONFIG_STM32F0L0G0_USART2_SERIALDRIVER) -# error Both CONFIG_STM32F0L0G0_USART2_1WIREDRIVER and CONFIG_STM32F0L0G0_USART2_SERIALDRIVER defined -# undef CONFIG_STM32F0L0G0_USART2_1WIREDRIVER -#endif -#if defined(CONFIG_STM32F0L0G0_USART3_1WIREDRIVER) && defined(CONFIG_STM32F0L0G0_USART3_SERIALDRIVER) -# error Both CONFIG_STM32F0L0G0_USART3_1WIREDRIVER and CONFIG_STM32F0L0G0_USART3_SERIALDRIVER defined -# undef CONFIG_STM32F0L0G0_USART3_1WIREDRIVER -#endif -#if defined(CONFIG_STM32F0L0G0_USART4_1WIREDRIVER) && defined(CONFIG_STM32F0L0G0_USART4_SERIALDRIVER) -# error Both CONFIG_STM32F0L0G0_USART4_1WIREDRIVER and CONFIG_STM32F0L0G0_USART4_SERIALDRIVER defined -# undef CONFIG_STM32F0L0G0_USART4_1WIREDRIVER -#endif -#if defined(CONFIG_STM32F0L0G0_USART5_1WIREDRIVER) && defined(CONFIG_STM32F0L0G0_USART5_SERIALDRIVER) -# error Both CONFIG_STM32F0L0G0_USART5_1WIREDRIVER and CONFIG_STM32F0L0G0_USART5_SERIALDRIVER defined -# undef CONFIG_STM32F0L0G0_USART5_1WIREDRIVER -#endif -#if defined(CONFIG_STM32F0L0G0_USART6_1WIREDRIVER) && defined(CONFIG_STM32F0L0G0_USART6_SERIALDRIVER) -# error Both CONFIG_STM32F0L0G0_USART6_1WIREDRIVER and CONFIG_STM32F0L0G0_USART6_SERIALDRIVER defined -# undef CONFIG_STM32F0L0G0_USART6_1WIREDRIVER -#endif -#if defined(CONFIG_STM32F0L0G0_USART7_1WIREDRIVER) && defined(CONFIG_STM32F0L0G0_USART7_SERIALDRIVER) -# error Both CONFIG_STM32F0L0G0_USART7_1WIREDRIVER and CONFIG_STM32F0L0G0_USART7_SERIALDRIVER defined -# undef CONFIG_STM32F0L0G0_USART7_1WIREDRIVER -#endif -#if defined(CONFIG_STM32F0L0G0_USART8_1WIREDRIVER) && defined(CONFIG_STM32F0L0G0_USART8_SERIALDRIVER) -# error Both CONFIG_STM32F0L0G0_USART8_1WIREDRIVER and CONFIG_STM32F0L0G0_USART8_SERIALDRIVER defined -# undef CONFIG_STM32F0L0G0_USART8_1WIREDRIVER -#endif - -/* Is the serial driver enabled? */ - -#if defined(CONFIG_STM32F0L0G0_USART1_SERIALDRIVER) || defined(CONFIG_STM32F0L0G0_USART2_SERIALDRIVER) || \ - defined(CONFIG_STM32F0L0G0_USART3_SERIALDRIVER) || defined(CONFIG_STM32F0L0G0_USART4_SERIALDRIVER) || \ - defined(CONFIG_STM32F0L0G0_USART5_SERIALDRIVER) || defined(CONFIG_STM32F0L0G0_USART6_SERIALDRIVER) || \ - defined(CONFIG_STM32F0L0G0_USART7_SERIALDRIVER) || defined(CONFIG_STM32F0L0G0_USART8_SERIALDRIVER) -# define HAVE_SERIALDRIVER 1 -#endif - -/* Is the 1-Wire driver? */ - -#if defined(CONFIG_STM32F0L0G0_USART1_1WIREDRIVER) || defined(CONFIG_STM32F0L0G0_USART2_1WIREDRIVER) || \ - defined(CONFIG_STM32F0L0G0_USART3_1WIREDRIVER) || defined(CONFIG_STM32F0L0G0_USART4_1WIREDRIVER) || \ - defined(CONFIG_STM32F0L0G0_USART5_1WIREDRIVER) || defined(CONFIG_STM32F0L0G0_USART6_1WIREDRIVER) || \ - defined(CONFIG_STM32F0L0G0_USART7_1WIREDRIVER) || defined(CONFIG_STM32F0L0G0_USART8_1WIREDRIVER) -# define HAVE_1WIREDRIVER 1 -#endif - -/* Is there a serial console? */ - -#if defined(CONFIG_USART1_SERIAL_CONSOLE) && defined(CONFIG_STM32F0L0G0_USART1_SERIALDRIVER) -# undef CONFIG_USART2_SERIAL_CONSOLE -# undef CONFIG_USART3_SERIAL_CONSOLE -# undef CONFIG_USART4_SERIAL_CONSOLE -# undef CONFIG_USART5_SERIAL_CONSOLE -# undef CONFIG_USART6_SERIAL_CONSOLE -# undef CONFIG_USART7_SERIAL_CONSOLE -# undef CONFIG_USART8_SERIAL_CONSOLE -# define CONSOLE_USART 1 -# define HAVE_CONSOLE 1 -#elif defined(CONFIG_USART2_SERIAL_CONSOLE) && defined(CONFIG_STM32F0L0G0_USART2_SERIALDRIVER) -# undef CONFIG_USART1_SERIAL_CONSOLE -# undef CONFIG_USART3_SERIAL_CONSOLE -# undef CONFIG_USART4_SERIAL_CONSOLE -# undef CONFIG_USART5_SERIAL_CONSOLE -# undef CONFIG_USART6_SERIAL_CONSOLE -# undef CONFIG_USART7_SERIAL_CONSOLE -# undef CONFIG_USART8_SERIAL_CONSOLE -# define CONSOLE_USART 2 -# define HAVE_CONSOLE 1 -#elif defined(CONFIG_USART3_SERIAL_CONSOLE) && defined(CONFIG_STM32F0L0G0_USART3_SERIALDRIVER) -# undef CONFIG_USART1_SERIAL_CONSOLE -# undef CONFIG_USART2_SERIAL_CONSOLE -# undef CONFIG_USART4_SERIAL_CONSOLE -# undef CONFIG_USART5_SERIAL_CONSOLE -# undef CONFIG_USART6_SERIAL_CONSOLE -# undef CONFIG_USART7_SERIAL_CONSOLE -# undef CONFIG_USART8_SERIAL_CONSOLE -# define CONSOLE_USART 3 -# define HAVE_CONSOLE 1 -#elif defined(CONFIG_USART4_SERIAL_CONSOLE) && defined(CONFIG_STM32F0L0G0_USART4_SERIALDRIVER) -# undef CONFIG_USART1_SERIAL_CONSOLE -# undef CONFIG_USART2_SERIAL_CONSOLE -# undef CONFIG_USART3_SERIAL_CONSOLE -# undef CONFIG_USART5_SERIAL_CONSOLE -# undef CONFIG_USART6_SERIAL_CONSOLE -# undef CONFIG_USART7_SERIAL_CONSOLE -# undef CONFIG_USART8_SERIAL_CONSOLE -# define CONSOLE_USART 4 -# define HAVE_CONSOLE 1 -#elif defined(CONFIG_USART5_SERIAL_CONSOLE) && defined(CONFIG_STM32F0L0G0_USART5_SERIALDRIVER) -# undef CONFIG_USART1_SERIAL_CONSOLE -# undef CONFIG_USART2_SERIAL_CONSOLE -# undef CONFIG_USART3_SERIAL_CONSOLE -# undef CONFIG_USART4_SERIAL_CONSOLE -# undef CONFIG_USART6_SERIAL_CONSOLE -# undef CONFIG_USART7_SERIAL_CONSOLE -# undef CONFIG_USART8_SERIAL_CONSOLE -# define CONSOLE_USART 5 -# define HAVE_CONSOLE 1 -#elif defined(CONFIG_USART6_SERIAL_CONSOLE) && defined(CONFIG_STM32F0L0G0_USART6_SERIALDRIVER) -# undef CONFIG_USART1_SERIAL_CONSOLE -# undef CONFIG_USART2_SERIAL_CONSOLE -# undef CONFIG_USART3_SERIAL_CONSOLE -# undef CONFIG_USART4_SERIAL_CONSOLE -# undef CONFIG_USART5_SERIAL_CONSOLE -# undef CONFIG_USART7_SERIAL_CONSOLE -# undef CONFIG_USART8_SERIAL_CONSOLE -# define CONSOLE_USART 6 -# define HAVE_CONSOLE 1 -#elif defined(CONFIG_USART7_SERIAL_CONSOLE) && defined(CONFIG_STM32F0L0G0_USART7_SERIALDRIVER) -# undef CONFIG_USART1_SERIAL_CONSOLE -# undef CONFIG_USART2_SERIAL_CONSOLE -# undef CONFIG_USART3_SERIAL_CONSOLE -# undef CONFIG_USART4_SERIAL_CONSOLE -# undef CONFIG_USART5_SERIAL_CONSOLE -# undef CONFIG_USART6_SERIAL_CONSOLE -# undef CONFIG_USART5_SERIAL_CONSOLE -# undef CONFIG_USART8_SERIAL_CONSOLE -# define CONSOLE_USART 7 -# define HAVE_CONSOLE 1 -#elif defined(CONFIG_USART8_SERIAL_CONSOLE) && defined(CONFIG_STM32F0L0G0_USART8_SERIALDRIVER) -# undef CONFIG_USART1_SERIAL_CONSOLE -# undef CONFIG_USART2_SERIAL_CONSOLE -# undef CONFIG_USART3_SERIAL_CONSOLE -# undef CONFIG_USART4_SERIAL_CONSOLE -# undef CONFIG_USART6_SERIAL_CONSOLE -# undef CONFIG_USART6_SERIAL_CONSOLE -# undef CONFIG_USART7_SERIAL_CONSOLE -# define CONSOLE_USART 8 -# define HAVE_CONSOLE 1 -#else -# undef CONFIG_USART1_SERIAL_CONSOLE -# undef CONFIG_USART2_SERIAL_CONSOLE -# undef CONFIG_USART3_SERIAL_CONSOLE -# undef CONFIG_USART4_SERIAL_CONSOLE -# undef CONFIG_USART5_SERIAL_CONSOLE -# undef CONFIG_USART6_SERIAL_CONSOLE -# undef CONFIG_USART7_SERIAL_CONSOLE -# undef CONFIG_USART8_SERIAL_CONSOLE -# define CONSOLE_USART 0 -# undef HAVE_CONSOLE -#endif - -/* DMA support is only provided if CONFIG_ARCH_DMA is in the NuttX - * configuration - */ - -#if !defined(HAVE_SERIALDRIVER) || !defined(CONFIG_ARCH_DMA) -# undef CONFIG_USART1_RXDMA -# undef CONFIG_USART2_RXDMA -# undef CONFIG_USART3_RXDMA -# undef CONFIG_USART4_RXDMA -# undef CONFIG_USART5_RXDMA -# undef CONFIG_USART6_RXDMA -# undef CONFIG_USART7_RXDMA -# undef CONFIG_USART8_RXDMA -#endif - -/* Disable the DMA configuration on all unused USARTs */ - -#ifndef CONFIG_STM32F0L0G0_USART1_SERIALDRIVER -# undef CONFIG_USART1_RXDMA -#endif - -#ifndef CONFIG_STM32F0L0G0_USART2_SERIALDRIVER -# undef CONFIG_USART2_RXDMA -#endif - -#ifndef CONFIG_STM32F0L0G0_USART3_SERIALDRIVER -# undef CONFIG_USART3_RXDMA -#endif - -#ifndef CONFIG_STM32F0L0G0_USART4_SERIALDRIVER -# undef CONFIG_USART4_RXDMA -#endif - -#ifndef CONFIG_STM32F0L0G0_USART5_SERIALDRIVER -# undef CONFIG_USART5_RXDMA -#endif - -#ifndef CONFIG_STM32F0L0G0_USART6_SERIALDRIVER -# undef CONFIG_USART6_RXDMA -#endif - -#ifndef CONFIG_STM32F0L0G0_USART7_SERIALDRIVER -# undef CONFIG_USART7_RXDMA -#endif - -#ifndef CONFIG_STM32F0L0G0_USART8_SERIALDRIVER -# undef CONFIG_USART8_RXDMA -#endif - -/* Is DMA available on any (enabled) USART? */ - -#undef SERIAL_HAVE_RXDMA -#if defined(CONFIG_USART1_RXDMA) || defined(CONFIG_USART2_RXDMA) || \ - defined(CONFIG_USART3_RXDMA) || defined(CONFIG_USART4_RXDMA) || \ - defined(CONFIG_USART5_RXDMA) || defined(CONFIG_USART6_RXDMA) || \ - defined(CONFIG_USART7_RXDMA) || defined(CONFIG_USART8_RXDMA) -# define SERIAL_HAVE_RXDMA 1 -#endif - -/* Is DMA used on the console USART? */ - -#undef SERIAL_HAVE_CONSOLE_DMA -#if defined(CONFIG_USART1_SERIAL_CONSOLE) && defined(CONFIG_USART1_RXDMA) -# define SERIAL_HAVE_CONSOLE_DMA 1 -#elif defined(CONFIG_USART2_SERIAL_CONSOLE) && defined(CONFIG_USART2_RXDMA) -# define SERIAL_HAVE_CONSOLE_DMA 1 -#elif defined(CONFIG_USART3_SERIAL_CONSOLE) && defined(CONFIG_USART3_RXDMA) -# define SERIAL_HAVE_CONSOLE_DMA 1 -#elif defined(CONFIG_USART4_SERIAL_CONSOLE) && defined(CONFIG_USART4_RXDMA) -# define SERIAL_HAVE_CONSOLE_DMA 1 -#elif defined(CONFIG_USART5_SERIAL_CONSOLE) && defined(CONFIG_USART5_RXDMA) -# define SERIAL_HAVE_CONSOLE_DMA 1 -#elif defined(CONFIG_USART6_SERIAL_CONSOLE) && defined(CONFIG_USART6_RXDMA) -# define SERIAL_HAVE_CONSOLE_DMA 1 -#elif defined(CONFIG_USART7_SERIAL_CONSOLE) && defined(CONFIG_USART7_RXDMA) -# define SERIAL_HAVE_CONSOLE_DMA 1 -#elif defined(CONFIG_USART8_SERIAL_CONSOLE) && defined(CONFIG_USART8_RXDMA) -# define SERIAL_HAVE_CONSOLE_DMA 1 -#endif - -/* Is DMA used on all (enabled) USARTs */ - -#define SERIAL_HAVE_ONLY_DMA 1 -#if defined(CONFIG_STM32F0L0G0_USART1_SERIALDRIVER) && !defined(CONFIG_USART1_RXDMA) -# undef SERIAL_HAVE_ONLY_DMA -#elif defined(CONFIG_STM32F0L0G0_USART2_SERIALDRIVER) && !defined(CONFIG_USART2_RXDMA) -# undef SERIAL_HAVE_ONLY_DMA -#elif defined(CONFIG_STM32F0L0G0_USART3_SERIALDRIVER) && !defined(CONFIG_USART3_RXDMA) -# undef SERIAL_HAVE_ONLY_DMA -#elif defined(CONFIG_STM32F0L0G0_USART4_SERIALDRIVER) && !defined(CONFIG_USART4_RXDMA) -# undef SERIAL_HAVE_ONLY_DMA -#elif defined(CONFIG_STM32F0L0G0_USART5_SERIALDRIVER) && !defined(CONFIG_USART5_RXDMA) -# undef SERIAL_HAVE_ONLY_DMA -#elif defined(CONFIG_STM32F0L0G0_USART6_SERIALDRIVER) && !defined(CONFIG_USART6_RXDMA) -# undef SERIAL_HAVE_ONLY_DMA -#elif defined(CONFIG_STM32F0L0G0_USART7_SERIALDRIVER) && !defined(CONFIG_USART7_RXDMA) -# undef SERIAL_HAVE_ONLY_DMA -#elif defined(CONFIG_STM32F0L0G0_USART8_SERIALDRIVER) && !defined(CONFIG_USART8_RXDMA) -# undef SERIAL_HAVE_ONLY_DMA -#endif - -/* Is RS-485 used? */ - -#if defined(CONFIG_USART1_RS485) || defined(CONFIG_USART2_RS485) || \ - defined(CONFIG_USART3_RS485) || defined(CONFIG_USART4_RS485) || \ - defined(CONFIG_USART5_RS485) || defined(CONFIG_USART6_RS485) || \ - defined(CONFIG_USART7_RS485) || defined(CONFIG_USART8_RS485) -# define HAVE_RS485 1 -#endif - -#ifdef HAVE_RS485 -# define USART_CR1_USED_INTS (USART_CR1_RXNEIE | USART_CR1_TXEIE | USART_CR1_PEIE | USART_CR1_TCIE) -#else -# define USART_CR1_USED_INTS (USART_CR1_RXNEIE | USART_CR1_TXEIE | USART_CR1_PEIE) -#endif - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -#ifndef __ASSEMBLY__ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Public Functions Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_serial_dma_poll - * - * Description: - * Must be called periodically if any STM32 USART is configured for DMA. - * The DMA callback is triggered for each fifo size/2 bytes, but this can - * result in some bytes being transferred but not collected if the incoming - * data is not a whole multiple of half the FIFO size. - * - * May be safely called from either interrupt or thread context. - * - ****************************************************************************/ - -#ifdef SERIAL_HAVE_RXDMA -void stm32_serial_dma_poll(void); -#endif - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_STM32_UART_H */ diff --git a/arch/arm/src/stm32f0l0g0/stm32_uid.c b/arch/arm/src/stm32f0l0g0/stm32_uid.c deleted file mode 100644 index a57b048b8a79a..0000000000000 --- a/arch/arm/src/stm32f0l0g0/stm32_uid.c +++ /dev/null @@ -1,47 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_uid.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - **************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "hardware/stm32_memorymap.h" - -#include "stm32_uid.h" - -#ifdef STM32_SYSMEM_UID - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -void stm32_get_uniqueid(uint32_t *uid) -{ - int i; - - for (i = 0; i < 3; i++) - { - *(uid + i) = *((uint32_t *)(STM32_SYSMEM_UID) + i); - } -} - -#endif /* STM32_SYSMEM_UID */ diff --git a/arch/arm/src/stm32f0l0g0/stm32_uid.h b/arch/arm/src/stm32f0l0g0/stm32_uid.h deleted file mode 100644 index 34661df85deb7..0000000000000 --- a/arch/arm/src/stm32f0l0g0/stm32_uid.h +++ /dev/null @@ -1,38 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_uid.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_STM32_UID_H -#define __ARCH_ARM_SRC_STM32F0L0G0_STM32_UID_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -void stm32_get_uniqueid(uint32_t *uid); - -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_STM32_UID_H */ \ No newline at end of file diff --git a/arch/arm/src/stm32f0l0g0/stm32_usbdev.c b/arch/arm/src/stm32f0l0g0/stm32_usbdev.c deleted file mode 100644 index 9cfd7df85bda0..0000000000000 --- a/arch/arm/src/stm32f0l0g0/stm32_usbdev.c +++ /dev/null @@ -1,3888 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_usbdev.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* Ported from the STM32 F1 implementation. References: - * - RM0008 Reference manual, STMicro document ID 13902 - * - STM32F10xxx USB development kit, UM0424, STMicro - */ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include - -#include - -#include "arm_internal.h" -#include "hardware/stm32_rcc.h" -#include "hardware/stm32_usbdev.h" -#include "stm32_gpio.h" -#include "stm32_usbdev.h" - -#if defined(CONFIG_USBDEV) && defined(CONFIG_STM32F0L0G0_USB) - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -#ifndef CONFIG_USBDEV_EP0_MAXSIZE -# define CONFIG_USBDEV_EP0_MAXSIZE 64 -#endif - -#ifndef CONFIG_USBDEV_SETUP_MAXDATASIZE -# define CONFIG_USBDEV_SETUP_MAXDATASIZE CONFIG_USBDEV_EP0_MAXSIZE -#endif - -/* Extremely detailed register debug that you would normally never want - * enabled. - */ - -#ifndef CONFIG_DEBUG_USB_INFO -# undef CONFIG_STM32F0L0G0_USBDEV_REGDEBUG -#endif - -/* Initial interrupt mask: Reset + Suspend + Correct Transfer */ - -#define STM32_CNTR_SETUP (USB_CNTR_RESETM|USB_CNTR_SUSPM|USB_CNTR_CTRM) - -/* Endpoint identifiers. The STM32 supports up to 16 mono-directional or 8 - * bidirectional endpoints. However, when you take into account PMA buffer - * usage (see below) and the fact that EP0 is bidirectional, then there is - * a functional limitation of EP0 + 5 mono-directional endpoints = 6. We'll - * define STM32_NENDPOINTS to be 8, however, because that is how many - * endpoint register sets there are. - */ - -#define EP0 (0) -#define EP1 (1) -#define EP2 (2) -#define EP3 (3) -#define EP4 (4) -#define EP5 (5) -#define EP6 (6) -#define EP7 (7) - -#define STM32_ENDP_BIT(ep) (1 << (ep)) -#define STM32_ENDP_ALLSET 0xff - -/* Packet sizes. We us a fixed 64 max packet size for all endpoint types */ - -#define STM32_MAXPACKET_SHIFT (6) -#define STM32_MAXPACKET_SIZE (1 << (STM32_MAXPACKET_SHIFT)) -#define STM32_MAXPACKET_MASK (STM32_MAXPACKET_SIZE-1) - -#define STM32_EP0MAXPACKET STM32_MAXPACKET_SIZE - -/* Buffer descriptor table. We assume that USB has exclusive use of CAN/USB - * memory. The buffer table is positioned at the beginning of the 512-byte - * CAN/USB memory. - * We will use the first STM32_NENDPOINTS*4 words for the buffer table. - * That is exactly 64 bytes, leaving 7*64 bytes for endpoint buffers. - */ - -#define STM32_BTABLE_ADDRESS (0x00) /* Start at the beginning of USB/CAN RAM */ -#define STM32_DESC_SIZE (8) /* Each descriptor is 4*2=8 bytes in size */ -#define STM32_BTABLE_SIZE (STM32_NENDPOINTS*STM32_DESC_SIZE) - -/* Buffer layout. Assume that all buffers are 64-bytes (maxpacketsize), then - * we have space for only 7 buffers; endpoint 0 will require two buffers, - * leaving 5 for other endpoints. - */ - -#define STM32_BUFFER_START STM32_BTABLE_SIZE -#define STM32_EP0_RXADDR STM32_BUFFER_START -#define STM32_EP0_TXADDR (STM32_EP0_RXADDR+STM32_EP0MAXPACKET) - -#define STM32_BUFFER_EP0 0x03 -#define STM32_NBUFFERS 7 -#define STM32_BUFFER_BIT(bn) (1 << (bn)) -#define STM32_BUFFER_ALLSET 0x7f -#define STM32_BUFNO2BUF(bn) (STM32_BUFFER_START+((bn)<head == NULL) -#define stm32_rqpeek(ep) ((ep)->head) - -/* USB trace ****************************************************************/ - -/* Trace error codes */ - -#define STM32_TRACEERR_ALLOCFAIL 0x0001 -#define STM32_TRACEERR_BADCLEARFEATURE 0x0002 -#define STM32_TRACEERR_BADDEVGETSTATUS 0x0003 -#define STM32_TRACEERR_BADEPGETSTATUS 0x0004 -#define STM32_TRACEERR_BADEPNO 0x0005 -#define STM32_TRACEERR_BADEPTYPE 0x0006 -#define STM32_TRACEERR_BADGETCONFIG 0x0007 -#define STM32_TRACEERR_BADGETSETDESC 0x0008 -#define STM32_TRACEERR_BADGETSTATUS 0x0009 -#define STM32_TRACEERR_BADSETADDRESS 0x000a -#define STM32_TRACEERR_BADSETCONFIG 0x000b -#define STM32_TRACEERR_BADSETFEATURE 0x000c -#define STM32_TRACEERR_BINDFAILED 0x000d -#define STM32_TRACEERR_DISPATCHSTALL 0x000e -#define STM32_TRACEERR_DRIVER 0x000f -#define STM32_TRACEERR_DRIVERREGISTERED 0x0010 -#define STM32_TRACEERR_EP0BADCTR 0x0011 -#define STM32_TRACEERR_EP0SETUPSTALLED 0x0012 -#define STM32_TRACEERR_EPBUFFER 0x0013 -#define STM32_TRACEERR_EPDISABLED 0x0014 -#define STM32_TRACEERR_EPOUTNULLPACKET 0x0015 -#define STM32_TRACEERR_EPRESERVE 0x0016 -#define STM32_TRACEERR_INVALIDCTRLREQ 0x0017 -#define STM32_TRACEERR_INVALIDPARMS 0x0018 -#define STM32_TRACEERR_IRQREGISTRATION 0x0019 -#define STM32_TRACEERR_NOTCONFIGURED 0x001a -#define STM32_TRACEERR_REQABORTED 0x001b - -/* Trace interrupt codes */ - -#define STM32_TRACEINTID_CLEARFEATURE 0x0001 -#define STM32_TRACEINTID_DEVGETSTATUS 0x0002 -#define STM32_TRACEINTID_DISPATCH 0x0003 -#define STM32_TRACEINTID_EP0IN 0x0004 -#define STM32_TRACEINTID_EP0INDONE 0x0005 -#define STM32_TRACEINTID_EP0OUTDONE 0x0006 -#define STM32_TRACEINTID_EP0SETUPDONE 0x0007 -#define STM32_TRACEINTID_EP0SETUPSETADDRESS 0x0008 -#define STM32_TRACEINTID_EPGETSTATUS 0x0009 -#define STM32_TRACEINTID_EPINDONE 0x000a -#define STM32_TRACEINTID_EPINQEMPTY 0x000b -#define STM32_TRACEINTID_EPOUTDONE 0x000c -#define STM32_TRACEINTID_EPOUTPENDING 0x000d -#define STM32_TRACEINTID_EPOUTQEMPTY 0x000e -#define STM32_TRACEINTID_ESOF 0x000f -#define STM32_TRACEINTID_GETCONFIG 0x0010 -#define STM32_TRACEINTID_GETSETDESC 0x0011 -#define STM32_TRACEINTID_GETSETIF 0x0012 -#define STM32_TRACEINTID_GETSTATUS 0x0013 -#define STM32_TRACEINTID_INTERRUPT 0x0014 -#define STM32_TRACEINTID_IFGETSTATUS 0x0015 -#define STM32_TRACEINTID_LPCTR 0x0016 -#define STM32_TRACEINTID_NOSTDREQ 0x0017 -#define STM32_TRACEINTID_RESET 0x0018 -#define STM32_TRACEINTID_SETCONFIG 0x0019 -#define STM32_TRACEINTID_SETFEATURE 0x001a -#define STM32_TRACEINTID_SUSP 0x001b -#define STM32_TRACEINTID_SYNCHFRAME 0x001c -#define STM32_TRACEINTID_WKUP 0x001d -#define STM32_TRACEINTID_EP0SETUPOUT 0x001e -#define STM32_TRACEINTID_EP0SETUPOUTDATA 0x001f - -/* Byte ordering in host-based values */ - -#ifdef CONFIG_ENDIAN_BIG -# define LSB 1 -# define MSB 0 -#else -# define LSB 0 -# define MSB 1 -#endif - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/* The various states of a control pipe */ - -enum stm32_ep0state_e -{ - EP0STATE_IDLE = 0, /* No request in progress */ - EP0STATE_SETUP_OUT, /* Set up received with data for device OUT in progress */ - EP0STATE_SETUP_READY, /* Set up was received prior and is in ctrl, - * now the data has arrived */ - EP0STATE_WRREQUEST, /* Write request in progress */ - EP0STATE_RDREQUEST, /* Read request in progress */ - EP0STATE_STALLED /* We are stalled */ -}; - -/* Resume states */ - -enum stm32_rsmstate_e -{ - RSMSTATE_IDLE = 0, /* Device is either fully suspended or running */ - RSMSTATE_STARTED, /* Resume sequence has been started */ - RSMSTATE_WAITING /* Waiting (on ESOFs) for end of sequence */ -}; - -union wb_u -{ - uint16_t w; - uint8_t b[2]; -}; - -/* A container for a request so that the request make be retained in a list */ - -struct stm32_req_s -{ - struct usbdev_req_s req; /* Standard USB request */ - struct stm32_req_s *flink; /* Supports a singly linked list */ -}; - -/* This is the internal representation of an endpoint */ - -struct stm32_ep_s -{ - /* Common endpoint fields. This must be the first thing defined in the - * structure so that it is possible to simply cast from struct usbdev_ep_s - * to struct stm32_ep_s. - */ - - struct usbdev_ep_s ep; /* Standard endpoint structure */ - - /* STR71X-specific fields */ - - struct stm32_usbdev_s *dev; /* Reference to private driver data */ - struct stm32_req_s *head; /* Request list for this endpoint */ - struct stm32_req_s *tail; - uint8_t bufno; /* Allocated buffer number */ - uint8_t stalled:1; /* true: Endpoint is stalled */ - uint8_t halted:1; /* true: Endpoint feature halted */ - uint8_t txbusy:1; /* true: TX endpoint FIFO full */ - uint8_t txnullpkt:1; /* Null packet needed at end of transfer */ -}; - -struct stm32_usbdev_s -{ - /* Common device fields. This must be the first thing defined in the - * structure so that it is possible to simply cast from struct usbdev_s - * to structstm32_usbdev_s. - */ - - struct usbdev_s usbdev; - - /* The bound device class driver */ - - struct usbdevclass_driver_s *driver; - - /* STM32-specific fields */ - - uint8_t ep0state; /* State of EP0 (see enum stm32_ep0state_e) */ - uint8_t rsmstate; /* Resume state (see enum stm32_rsmstate_e) */ - uint8_t nesofs; /* ESOF counter (for resume support) */ - uint8_t rxpending:1; /* 1: OUT data in PMA, but no read requests */ - uint8_t selfpowered:1; /* 1: Device is self powered */ - uint8_t epavail; /* Bitset of available endpoints */ - uint8_t bufavail; /* Bitset of available buffers */ - uint16_t rxstatus; /* Saved during interrupt processing */ - uint16_t txstatus; /* " " " " " " " " */ - uint16_t imask; /* Current interrupt mask */ - - /* E0 SETUP data buffering. - * - * ctrl - * The 8-byte SETUP request is received on the EP0 OUT endpoint and is - * saved. - * - * ep0data - * For OUT SETUP requests, the SETUP data phase must also complete before - * the SETUP command can be processed. The ep0 packet receipt logic - * stm32_ep0_rdrequest will save the accompanying EP0 OUT data in - * ep0data[] before the SETUP command is re-processed. - * - * ep0datlen - * Length of OUT DATA received in ep0data[] - */ - - struct usb_ctrlreq_s ctrl; /* Last EP0 request */ - - uint8_t ep0data[CONFIG_USBDEV_SETUP_MAXDATASIZE]; - uint16_t ep0datlen; - - /* The endpoint list */ - - struct stm32_ep_s eplist[STM32_NENDPOINTS]; -}; - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -/* Register operations ******************************************************/ - -#ifdef CONFIG_STM32F0L0G0_USBDEV_REGDEBUG -static uint16_t stm32_getreg(uint32_t addr); -static void stm32_putreg(uint16_t val, uint32_t addr); -static void stm32_dumpep(int epno); -#else -# define stm32_getreg(addr) getreg16(addr) -# define stm32_putreg(val,addr) putreg16(val,addr) -# define stm32_dumpep(epno) -#endif - -/* Low-Level Helpers ********************************************************/ - -static inline void stm32_seteptxcount(uint8_t epno, - uint16_t count); -static inline void stm32_seteptxaddr(uint8_t epno, - uint16_t addr); -static inline uint16_t stm32_geteptxaddr(uint8_t epno); -static void stm32_seteprxcount(uint8_t epno, uint16_t count); -static inline uint16_t stm32_geteprxcount(uint8_t epno); -static inline void stm32_seteprxaddr(uint8_t epno, uint16_t addr); -static inline uint16_t stm32_geteprxaddr(uint8_t epno); -static inline void stm32_setepaddress(uint8_t epno, uint16_t addr); -static inline void stm32_seteptype(uint8_t epno, uint16_t type); -static inline void stm32_seteptxaddr(uint8_t epno, uint16_t addr); -static inline void stm32_clrstatusout(uint8_t epno); -static void stm32_clrrxdtog(uint8_t epno); -static void stm32_clrtxdtog(uint8_t epno); -static void stm32_clrepctrrx(uint8_t epno); -static void stm32_clrepctrtx(uint8_t epno); -static void stm32_seteptxstatus(uint8_t epno, uint16_t state); -static void stm32_seteprxstatus(uint8_t epno, uint16_t state); -static inline uint16_t stm32_geteptxstatus(uint8_t epno); -static inline uint16_t stm32_geteprxstatus(uint8_t epno); -static bool stm32_eptxstalled(uint8_t epno); -static bool stm32_eprxstalled(uint8_t epno); -static void stm32_setimask(struct stm32_usbdev_s *priv, - uint16_t setbits, - uint16_t clrbits); - -/* Suspend/Resume Helpers ***************************************************/ - -static void stm32_suspend(struct stm32_usbdev_s *priv); -static void stm32_initresume(struct stm32_usbdev_s *priv); -static void stm32_esofpoll(struct stm32_usbdev_s *priv) ; - -/* Request Helpers **********************************************************/ - -static void stm32_copytopma(const uint8_t *buffer, - uint16_t pma, uint16_t nbytes); -static inline void stm32_copyfrompma(uint8_t *buffer, - uint16_t pma, uint16_t nbytes); -static struct stm32_req_s * stm32_rqdequeue(struct stm32_ep_s *privep); -static void stm32_rqenqueue(struct stm32_ep_s *privep, - struct stm32_req_s *req); -static inline void stm32_abortrequest(struct stm32_ep_s *privep, - struct stm32_req_s *privreq, - int16_t result); -static void stm32_reqcomplete(struct stm32_ep_s *privep, int16_t result); -static void stm32_epwrite(struct stm32_usbdev_s *buf, - struct stm32_ep_s *privep, - const uint8_t *data, uint32_t nbytes); -static int stm32_wrrequest(struct stm32_usbdev_s *priv, - struct stm32_ep_s *privep); -inline static int stm32_wrrequest_ep0(struct stm32_usbdev_s *priv, - struct stm32_ep_s *privep); -static inline int stm32_ep0_rdrequest(struct stm32_usbdev_s *priv); -static int stm32_rdrequest(struct stm32_usbdev_s *priv, - struct stm32_ep_s *privep); -static void stm32_cancelrequests(struct stm32_ep_s *privep); - -/* Interrupt level processing ***********************************************/ - -static void stm32_dispatchrequest(struct stm32_usbdev_s *priv); -static void stm32_epdone(struct stm32_usbdev_s *priv, uint8_t epno); -static void stm32_setdevaddr(struct stm32_usbdev_s *priv, uint8_t value); -static void stm32_ep0setup(struct stm32_usbdev_s *priv); -static void stm32_ep0out(struct stm32_usbdev_s *priv); -static void stm32_ep0in(struct stm32_usbdev_s *priv); -static inline void - stm32_ep0done(struct stm32_usbdev_s *priv, uint16_t istr); -static void stm32_lptransfer(struct stm32_usbdev_s *priv); -static int stm32_usb_interrupt(int irq, void *context, void *arg); - -/* Endpoint helpers *********************************************************/ - -static inline struct stm32_ep_s * - stm32_epreserve(struct stm32_usbdev_s *priv, uint8_t epset); -static inline void - stm32_epunreserve(struct stm32_usbdev_s *priv, - struct stm32_ep_s *privep); -static inline bool - stm32_epreserved(struct stm32_usbdev_s *priv, int epno); -static int stm32_epallocpma(struct stm32_usbdev_s *priv); -static inline void - stm32_epfreepma(struct stm32_usbdev_s *priv, - struct stm32_ep_s *privep); - -/* Endpoint operations ******************************************************/ - -static int stm32_epconfigure(struct usbdev_ep_s *ep, - const struct usb_epdesc_s *desc, bool last); -static int stm32_epdisable(struct usbdev_ep_s *ep); -static struct usbdev_req_s * - stm32_epallocreq(struct usbdev_ep_s *ep); -static void stm32_epfreereq(struct usbdev_ep_s *ep, - struct usbdev_req_s *); -static int stm32_epsubmit(struct usbdev_ep_s *ep, - struct usbdev_req_s *req); -static int stm32_epcancel(struct usbdev_ep_s *ep, - struct usbdev_req_s *req); -static int stm32_epstall(struct usbdev_ep_s *ep, bool resume); - -/* USB device controller operations *****************************************/ - -static struct usbdev_ep_s * - stm32_allocep(struct usbdev_s *dev, uint8_t epno, bool in, - uint8_t eptype); -static void stm32_freeep(struct usbdev_s *dev, struct usbdev_ep_s *ep); -static int stm32_getframe(struct usbdev_s *dev); -static int stm32_wakeup(struct usbdev_s *dev); -static int stm32_selfpowered(struct usbdev_s *dev, bool selfpowered); - -/* Initialization/Reset *****************************************************/ - -static void stm32_reset(struct stm32_usbdev_s *priv); -static void stm32_hwreset(struct stm32_usbdev_s *priv); -static void stm32_hwsetup(struct stm32_usbdev_s *priv); -static void stm32_hwshutdown(struct stm32_usbdev_s *priv); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* Since there is only a single USB interface, all status information can be - * be simply retained in a single global instance. - */ - -static struct stm32_usbdev_s g_usbdev; - -static const struct usbdev_epops_s g_epops = -{ - .configure = stm32_epconfigure, - .disable = stm32_epdisable, - .allocreq = stm32_epallocreq, - .freereq = stm32_epfreereq, - .submit = stm32_epsubmit, - .cancel = stm32_epcancel, - .stall = stm32_epstall, -}; - -static const struct usbdev_ops_s g_devops = -{ - .allocep = stm32_allocep, - .freeep = stm32_freeep, - .getframe = stm32_getframe, - .wakeup = stm32_wakeup, - .selfpowered = stm32_selfpowered, - .pullup = stm32_usbpullup, -}; - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -#ifdef CONFIG_USBDEV_TRACE_STRINGS -const struct trace_msg_t g_usb_trace_strings_intdecode[] = -{ - TRACE_STR(STM32_TRACEINTID_CLEARFEATURE), - TRACE_STR(STM32_TRACEINTID_DEVGETSTATUS), - TRACE_STR(STM32_TRACEINTID_DISPATCH), - TRACE_STR(STM32_TRACEINTID_EP0IN), - TRACE_STR(STM32_TRACEINTID_EP0INDONE), - TRACE_STR(STM32_TRACEINTID_EP0OUTDONE), - TRACE_STR(STM32_TRACEINTID_EP0SETUPDONE), - TRACE_STR(STM32_TRACEINTID_EP0SETUPSETADDRESS), - TRACE_STR(STM32_TRACEINTID_EPGETSTATUS), - TRACE_STR(STM32_TRACEINTID_EPINDONE), - TRACE_STR(STM32_TRACEINTID_EPINQEMPTY), - TRACE_STR(STM32_TRACEINTID_EPOUTDONE), - TRACE_STR(STM32_TRACEINTID_EPOUTPENDING), - TRACE_STR(STM32_TRACEINTID_EPOUTQEMPTY), - TRACE_STR(STM32_TRACEINTID_ESOF), - TRACE_STR(STM32_TRACEINTID_GETCONFIG), - TRACE_STR(STM32_TRACEINTID_GETSETDESC), - TRACE_STR(STM32_TRACEINTID_GETSETIF), - TRACE_STR(STM32_TRACEINTID_GETSTATUS), - TRACE_STR(STM32_TRACEINTID_INTERRUPT), - TRACE_STR(STM32_TRACEINTID_IFGETSTATUS), - TRACE_STR(STM32_TRACEINTID_LPCTR), - TRACE_STR(STM32_TRACEINTID_NOSTDREQ), - TRACE_STR(STM32_TRACEINTID_RESET), - TRACE_STR(STM32_TRACEINTID_SETCONFIG), - TRACE_STR(STM32_TRACEINTID_SETFEATURE), - TRACE_STR(STM32_TRACEINTID_SUSP), - TRACE_STR(STM32_TRACEINTID_SYNCHFRAME), - TRACE_STR(STM32_TRACEINTID_WKUP), - TRACE_STR(STM32_TRACEINTID_EP0SETUPOUT), - TRACE_STR(STM32_TRACEINTID_EP0SETUPOUTDATA), - TRACE_STR_END -}; -#endif - -#ifdef CONFIG_USBDEV_TRACE_STRINGS -const struct trace_msg_t g_usb_trace_strings_deverror[] = -{ - TRACE_STR(STM32_TRACEERR_ALLOCFAIL), - TRACE_STR(STM32_TRACEERR_BADCLEARFEATURE), - TRACE_STR(STM32_TRACEERR_BADDEVGETSTATUS), - TRACE_STR(STM32_TRACEERR_BADEPGETSTATUS), - TRACE_STR(STM32_TRACEERR_BADEPNO), - TRACE_STR(STM32_TRACEERR_BADEPTYPE), - TRACE_STR(STM32_TRACEERR_BADGETCONFIG), - TRACE_STR(STM32_TRACEERR_BADGETSETDESC), - TRACE_STR(STM32_TRACEERR_BADGETSTATUS), - TRACE_STR(STM32_TRACEERR_BADSETADDRESS), - TRACE_STR(STM32_TRACEERR_BADSETCONFIG), - TRACE_STR(STM32_TRACEERR_BADSETFEATURE), - TRACE_STR(STM32_TRACEERR_BINDFAILED), - TRACE_STR(STM32_TRACEERR_DISPATCHSTALL), - TRACE_STR(STM32_TRACEERR_DRIVER), - TRACE_STR(STM32_TRACEERR_DRIVERREGISTERED), - TRACE_STR(STM32_TRACEERR_EP0BADCTR), - TRACE_STR(STM32_TRACEERR_EP0SETUPSTALLED), - TRACE_STR(STM32_TRACEERR_EPBUFFER), - TRACE_STR(STM32_TRACEERR_EPDISABLED), - TRACE_STR(STM32_TRACEERR_EPOUTNULLPACKET), - TRACE_STR(STM32_TRACEERR_EPRESERVE), - TRACE_STR(STM32_TRACEERR_INVALIDCTRLREQ), - TRACE_STR(STM32_TRACEERR_INVALIDPARMS), - TRACE_STR(STM32_TRACEERR_IRQREGISTRATION), - TRACE_STR(STM32_TRACEERR_NOTCONFIGURED), - TRACE_STR(STM32_TRACEERR_REQABORTED), - TRACE_STR_END -}; -#endif - -/**************************************************************************** - * Private Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Register Operations - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_getreg - ****************************************************************************/ - -#ifdef CONFIG_STM32F0L0G0_USBDEV_REGDEBUG -static uint16_t stm32_getreg(uint32_t addr) -{ - static uint32_t prevaddr = 0; - static uint16_t preval = 0; - static uint32_t count = 0; - - /* Read the value from the register */ - - uint16_t val = getreg16(addr); - - /* Is this the same value that we read from the same register last time? - * Are we polling the register? If so, suppress some of the output. - */ - - if (addr == prevaddr && val == preval) - { - if (count == 0xffffffff || ++count > 3) - { - if (count == 4) - { - uinfo("...\n"); - } - return val; - } - } - - /* No this is a new address or value */ - - else - { - /* Did we print "..." for the previous value? */ - - if (count > 3) - { - /* Yes.. then show how many times the value repeated */ - - uinfo("[repeats %d more times]\n", count - 3); - } - - /* Save the new address, value, and count */ - - prevaddr = addr; - preval = val; - count = 1; - } - - /* Show the register value read */ - - uinfo("%08" PRIx32 "->%04x\n", addr, val); - return val; -} -#endif - -/**************************************************************************** - * Name: stm32_putreg - ****************************************************************************/ - -#ifdef CONFIG_STM32F0L0G0_USBDEV_REGDEBUG -static void stm32_putreg(uint16_t val, uint32_t addr) -{ - /* Show the register value being written */ - - uinfo("%08" PRIx32 "<-%04x\n", addr, val); - - /* Write the value */ - - putreg16(val, addr); -} -#endif - -/**************************************************************************** - * Name: stm32_dumpep - ****************************************************************************/ - -#ifdef CONFIG_STM32F0L0G0_USBDEV_REGDEBUG -static void stm32_dumpep(int epno) -{ - uint32_t addr; - - /* Common registers */ - - uinfo("CNTR: %04x\n", getreg16(STM32_USB_CNTR)); - uinfo("ISTR: %04x\n", getreg16(STM32_USB_ISTR)); - uinfo("FNR: %04x\n", getreg16(STM32_USB_FNR)); - uinfo("DADDR: %04x\n", getreg16(STM32_USB_DADDR)); - uinfo("BTABLE: %04x\n", getreg16(STM32_USB_BTABLE)); - - /* Endpoint register */ - - addr = STM32_USB_EPR(epno); - uinfo("EPR%d: [%08" PRIx32 "] %04x\n", epno, addr, getreg16(addr)); - - /* Endpoint descriptor */ - - addr = STM32_USB_BTABLE_ADDR(epno, 0); - uinfo("DESC: %08" PRIx32 "\n", addr); - - /* Endpoint buffer descriptor */ - - addr = STM32_USB_ADDR_TX(epno); - uinfo(" TX ADDR: [%08" PRIx32 "] %04x\n", addr, getreg16(addr)); - - addr = STM32_USB_COUNT_TX(epno); - uinfo(" COUNT: [%08" PRIx32 "] %04x\n", addr, getreg16(addr)); - - addr = STM32_USB_ADDR_RX(epno); - uinfo(" RX ADDR: [%08" PRIx32 "] %04x\n", addr, getreg16(addr)); - - addr = STM32_USB_COUNT_RX(epno); - uinfo(" COUNT: [%08" PRIx32 "] %04x\n", addr, getreg16(addr)); -} -#endif - -/**************************************************************************** - * Low-Level Helpers - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_seteptxcount - ****************************************************************************/ - -static inline void stm32_seteptxcount(uint8_t epno, uint16_t count) -{ - volatile uint32_t *epaddr = (uint32_t *)STM32_USB_COUNT_TX(epno); - *epaddr = count; -} - -/**************************************************************************** - * Name: stm32_seteptxaddr - ****************************************************************************/ - -static inline void stm32_seteptxaddr(uint8_t epno, uint16_t addr) -{ - volatile uint32_t *txaddr = (uint32_t *)STM32_USB_ADDR_TX(epno); - *txaddr = addr; -} - -/**************************************************************************** - * Name: stm32_geteptxaddr - ****************************************************************************/ - -static inline uint16_t stm32_geteptxaddr(uint8_t epno) -{ - volatile uint32_t *txaddr = (uint32_t *)STM32_USB_ADDR_TX(epno); - return (uint16_t)*txaddr; -} - -/**************************************************************************** - * Name: stm32_seteprxcount - ****************************************************************************/ - -static void stm32_seteprxcount(uint8_t epno, uint16_t count) -{ - volatile uint32_t *epaddr = (uint32_t *)STM32_USB_COUNT_RX(epno); - uint32_t rxcount = 0; - uint16_t nblocks; - - /* The upper bits of the RX COUNT value contain the size of allocated - * RX buffer. This is based on a block size of 2 or 32: - * - * USB_COUNT_RX_BL_SIZE not set: - * nblocks is in units of 2 bytes. - * 00000 - not allowed - * 00001 - 2 bytes - * .... - * 11111 - 62 bytes - * - * USB_COUNT_RX_BL_SIZE set: - * 00000 - 32 bytes - * 00001 - 64 bytes - * ... - * 01111 - 512 bytes - * 1xxxx - Not allowed - */ - - if (count > 62) - { - /* Blocks of 32 (with 0 meaning one block of 32) */ - - nblocks = (count >> 5) - 1 ; - DEBUGASSERT(nblocks <= 0x0f); - rxcount = (uint32_t)((nblocks << - USB_COUNT_RX_NUM_BLOCK_SHIFT) | - USB_COUNT_RX_BL_SIZE); - } - else if (count > 0) - { - /* Blocks of 2 (with 1 meaning one block of 2) */ - - nblocks = (count + 1) >> 1; - DEBUGASSERT(nblocks > 0 && nblocks < 0x1f); - rxcount = (uint32_t)(nblocks << USB_COUNT_RX_NUM_BLOCK_SHIFT); - } - *epaddr = rxcount; -} - -/**************************************************************************** - * Name: stm32_geteprxcount - ****************************************************************************/ - -static inline uint16_t stm32_geteprxcount(uint8_t epno) -{ - volatile uint32_t *epaddr = (uint32_t *)STM32_USB_COUNT_RX(epno); - return (*epaddr) & USB_COUNT_RX_MASK; -} - -/**************************************************************************** - * Name: stm32_seteprxaddr - ****************************************************************************/ - -static inline void stm32_seteprxaddr(uint8_t epno, uint16_t addr) -{ - volatile uint32_t *rxaddr = (uint32_t *)STM32_USB_ADDR_RX(epno); - *rxaddr = addr; -} - -/**************************************************************************** - * Name: stm32_seteprxaddr - ****************************************************************************/ - -static inline uint16_t stm32_geteprxaddr(uint8_t epno) -{ - volatile uint32_t *rxaddr = (uint32_t *)STM32_USB_ADDR_RX(epno); - return (uint16_t)*rxaddr; -} - -/**************************************************************************** - * Name: stm32_setepaddress - ****************************************************************************/ - -static inline void stm32_setepaddress(uint8_t epno, uint16_t addr) -{ - uint32_t epaddr = STM32_USB_EPR(epno); - uint16_t regval; - - regval = stm32_getreg(epaddr); - regval &= EPR_NOTOG_MASK; - regval &= ~USB_EPR_EA_MASK; - regval |= (addr << USB_EPR_EA_SHIFT); - stm32_putreg(regval, epaddr); -} - -/**************************************************************************** - * Name: stm32_seteptype - ****************************************************************************/ - -static inline void stm32_seteptype(uint8_t epno, uint16_t type) -{ - uint32_t epaddr = STM32_USB_EPR(epno); - uint16_t regval; - - regval = stm32_getreg(epaddr); - regval &= EPR_NOTOG_MASK; - regval &= ~USB_EPR_EPTYPE_MASK; - regval |= type; - stm32_putreg(regval, epaddr); -} - -/**************************************************************************** - * Name: stm32_clrstatusout - ****************************************************************************/ - -static inline void stm32_clrstatusout(uint8_t epno) -{ - uint32_t epaddr = STM32_USB_EPR(epno); - uint16_t regval; - - /* For a BULK endpoint the EP_KIND bit is used to enabled double buffering; - * for a CONTROL endpoint, it is set to indicate that a status OUT - * transaction is expected. The bit is not used with out endpoint types. - */ - - regval = stm32_getreg(epaddr); - regval &= EPR_NOTOG_MASK; - regval &= ~USB_EPR_EP_KIND; - stm32_putreg(regval, epaddr); -} - -/**************************************************************************** - * Name: stm32_clrrxdtog - ****************************************************************************/ - -static void stm32_clrrxdtog(uint8_t epno) -{ - uint32_t epaddr = STM32_USB_EPR(epno); - uint16_t regval; - - regval = stm32_getreg(epaddr); - if ((regval & USB_EPR_DTOG_RX) != 0) - { - regval &= EPR_NOTOG_MASK; - regval |= USB_EPR_DTOG_RX; - stm32_putreg(regval, epaddr); - } -} - -/**************************************************************************** - * Name: stm32_clrtxdtog - ****************************************************************************/ - -static void stm32_clrtxdtog(uint8_t epno) -{ - uint32_t epaddr = STM32_USB_EPR(epno); - uint16_t regval; - - regval = stm32_getreg(epaddr); - if ((regval & USB_EPR_DTOG_TX) != 0) - { - regval &= EPR_NOTOG_MASK; - regval |= USB_EPR_DTOG_TX; - stm32_putreg(regval, epaddr); - } -} - -/**************************************************************************** - * Name: stm32_clrepctrrx - ****************************************************************************/ - -static void stm32_clrepctrrx(uint8_t epno) -{ - uint32_t epaddr = STM32_USB_EPR(epno); - uint16_t regval; - - regval = stm32_getreg(epaddr); - regval &= EPR_NOTOG_MASK; - regval &= ~USB_EPR_CTR_RX; - stm32_putreg(regval, epaddr); -} - -/**************************************************************************** - * Name: stm32_clrepctrtx - ****************************************************************************/ - -static void stm32_clrepctrtx(uint8_t epno) -{ - uint32_t epaddr = STM32_USB_EPR(epno); - uint16_t regval; - - regval = stm32_getreg(epaddr); - regval &= EPR_NOTOG_MASK; - regval &= ~USB_EPR_CTR_TX; - stm32_putreg(regval, epaddr); -} - -/**************************************************************************** - * Name: stm32_geteptxstatus - ****************************************************************************/ - -static inline uint16_t stm32_geteptxstatus(uint8_t epno) -{ - return (uint16_t)(stm32_getreg(STM32_USB_EPR(epno)) & - USB_EPR_STATTX_MASK); -} - -/**************************************************************************** - * Name: stm32_geteprxstatus - ****************************************************************************/ - -static inline uint16_t stm32_geteprxstatus(uint8_t epno) -{ - return (stm32_getreg(STM32_USB_EPR(epno)) & USB_EPR_STATRX_MASK); -} - -/**************************************************************************** - * Name: stm32_seteptxstatus - ****************************************************************************/ - -static void stm32_seteptxstatus(uint8_t epno, uint16_t state) -{ - uint32_t epaddr = STM32_USB_EPR(epno); - uint16_t regval; - - /* The bits in the STAT_TX field can be toggled by software to set their - * value. When set to 0, the value remains unchanged; when set to one, - * value toggles. - */ - - regval = stm32_getreg(epaddr); - - /* The exclusive OR will set STAT_TX bits to 1 if there value is - * different from the bits requested in 'state' - */ - - regval ^= state; - regval &= EPR_TXDTOG_MASK; - stm32_putreg(regval, epaddr); -} - -/**************************************************************************** - * Name: stm32_seteprxstatus - ****************************************************************************/ - -static void stm32_seteprxstatus(uint8_t epno, uint16_t state) -{ - uint32_t epaddr = STM32_USB_EPR(epno); - uint16_t regval; - - /* The bits in the STAT_RX field can be toggled by software to set their - * value. When set to 0, the value remains unchanged; when set to one, - * value toggles. - */ - - regval = stm32_getreg(epaddr); - - /* The exclusive OR will set STAT_RX bits to 1 if there value is - * different from the bits requested in 'state' - */ - - regval ^= state; - regval &= EPR_RXDTOG_MASK; - stm32_putreg(regval, epaddr); -} - -/**************************************************************************** - * Name: stm32_eptxstalled - ****************************************************************************/ - -static inline bool stm32_eptxstalled(uint8_t epno) -{ - return (stm32_geteptxstatus(epno) == USB_EPR_STATTX_STALL); -} - -/**************************************************************************** - * Name: stm32_eprxstalled - ****************************************************************************/ - -static inline bool stm32_eprxstalled(uint8_t epno) -{ - return (stm32_geteprxstatus(epno) == USB_EPR_STATRX_STALL); -} - -/**************************************************************************** - * Request Helpers - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_copytopma - ****************************************************************************/ - -static void stm32_copytopma(const uint8_t *buffer, - uint16_t pma, uint16_t nbytes) -{ - uint16_t *dest; - uint16_t ms; - uint16_t ls; - int nwords = (nbytes + 1) >> 1; - int i; - - /* Copy loop. Source=user buffer, Dest=packet memory */ - - dest = (uint16_t *)(STM32_USBRAM_BASE + ((uint32_t)pma << 1)); - for (i = nwords; i != 0; i--) - { - /* Read two bytes and pack into on 16-bit word */ - - ls = (uint16_t)(*buffer++); - ms = (uint16_t)(*buffer++); - *dest = ms << 8 | ls; - - /* Source address increments by 2*sizeof(uint8_t) = 2; Dest address - * increments by 2*sizeof(uint16_t) = 4. - */ - - dest += 2; - } -} - -/**************************************************************************** - * Name: stm32_copyfrompma - ****************************************************************************/ - -static inline void -stm32_copyfrompma(uint8_t *buffer, uint16_t pma, uint16_t nbytes) -{ - uint32_t *src; - int nwords = (nbytes + 1) >> 1; - int i; - - /* Copy loop. Source=packet memory, Dest=user buffer */ - - src = (uint32_t *)(STM32_USBRAM_BASE + ((uint32_t)pma << 1)); - for (i = nwords; i != 0; i--) - { - /* Copy 16-bits from packet memory to user buffer. */ - - *(uint16_t *)buffer = *src++; - - /* Source address increments by 1*sizeof(uint32_t) = 4; Dest address - * increments by 2*sizeof(uint8_t) = 2. - */ - - buffer += 2; - } -} - -/**************************************************************************** - * Name: stm32_rqdequeue - ****************************************************************************/ - -static struct stm32_req_s *stm32_rqdequeue(struct stm32_ep_s *privep) -{ - struct stm32_req_s *ret = privep->head; - - if (ret) - { - privep->head = ret->flink; - if (!privep->head) - { - privep->tail = NULL; - } - - ret->flink = NULL; - } - - return ret; -} - -/**************************************************************************** - * Name: stm32_rqenqueue - ****************************************************************************/ - -static void stm32_rqenqueue(struct stm32_ep_s *privep, - struct stm32_req_s *req) -{ - req->flink = NULL; - if (!privep->head) - { - privep->head = req; - privep->tail = req; - } - else - { - privep->tail->flink = req; - privep->tail = req; - } -} - -/**************************************************************************** - * Name: stm32_abortrequest - ****************************************************************************/ - -static inline void -stm32_abortrequest(struct stm32_ep_s *privep, - struct stm32_req_s *privreq, - int16_t result) -{ - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_REQABORTED), - (uint16_t)USB_EPNO(privep->ep.eplog)); - - /* Save the result in the request structure */ - - privreq->req.result = result; - - /* Callback to the request completion handler */ - - privreq->req.callback(&privep->ep, &privreq->req); -} - -/**************************************************************************** - * Name: stm32_reqcomplete - ****************************************************************************/ - -static void stm32_reqcomplete(struct stm32_ep_s *privep, int16_t result) -{ - struct stm32_req_s *privreq; - irqstate_t flags; - - /* Remove the completed request at the head of the endpoint request list */ - - flags = enter_critical_section(); - privreq = stm32_rqdequeue(privep); - leave_critical_section(flags); - - if (privreq) - { - /* If endpoint 0, temporarily reflect the state of protocol stalled - * in the callback. - */ - - bool stalled = privep->stalled; - if (USB_EPNO(privep->ep.eplog) == EP0) - { - privep->stalled = (privep->dev->ep0state == EP0STATE_STALLED); - } - - /* Save the result in the request structure */ - - privreq->req.result = result; - - /* Callback to the request completion handler */ - - privreq->flink = NULL; - privreq->req.callback(&privep->ep, &privreq->req); - - /* Restore the stalled indication */ - - privep->stalled = stalled; - } -} - -/**************************************************************************** - * Name: tm32_epwrite - ****************************************************************************/ - -static void stm32_epwrite(struct stm32_usbdev_s *priv, - struct stm32_ep_s *privep, - const uint8_t *buf, uint32_t nbytes) -{ - uint8_t epno = USB_EPNO(privep->ep.eplog); - usbtrace(TRACE_WRITE(epno), nbytes); - - /* Check for a zero-length packet */ - - if (nbytes > 0) - { - /* Copy the data from the user buffer into packet memory for this - * endpoint - */ - - stm32_copytopma(buf, stm32_geteptxaddr(epno), nbytes); - } - - /* Send the packet (might be a null packet nbytes == 0) */ - - stm32_seteptxcount(epno, nbytes); - priv->txstatus = USB_EPR_STATTX_VALID; - - /* Indicate that there is data in the TX packet memory. - * This will be cleared when the next data out interrupt is received. - */ - - privep->txbusy = true; -} - -/**************************************************************************** - * Name: stm32_wrrequest_ep0 - * - * Description: - * Handle the ep0 state on writes. - * - ****************************************************************************/ - -inline static int stm32_wrrequest_ep0(struct stm32_usbdev_s *priv, - struct stm32_ep_s *privep) -{ - int ret; - ret = stm32_wrrequest(priv, privep); - priv->ep0state = ((ret == OK) ? EP0STATE_WRREQUEST : EP0STATE_IDLE); - return ret; -} - -/**************************************************************************** - * Name: stm32_wrrequest - ****************************************************************************/ - -static int stm32_wrrequest(struct stm32_usbdev_s *priv, - struct stm32_ep_s *privep) -{ - struct stm32_req_s *privreq; - uint8_t *buf; - uint8_t epno; - int nbytes; - int bytesleft; - - /* We get here when an IN endpoint interrupt occurs. So now we know that - * there is no TX transfer in progress. - */ - - privep->txbusy = false; - - /* Check the request from the head of the endpoint request queue */ - - privreq = stm32_rqpeek(privep); - if (!privreq) - { - /* There is no TX transfer in progress and no new pending TX - * requests to send. - */ - - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPINQEMPTY), 0); - return -ENOENT; - } - - epno = USB_EPNO(privep->ep.eplog); - uinfo("epno=%d req=%p: len=%zu xfrd=%zu nullpkt=%d\n", - epno, privreq, privreq->req.len, - privreq->req.xfrd, privep->txnullpkt); - UNUSED(epno); - - /* Get the number of bytes left to be sent in the packet */ - - bytesleft = privreq->req.len - privreq->req.xfrd; - nbytes = bytesleft; - -#warning "REVISIT: If the EP supports double buffering, then we can do better" - - /* Either - * (1) we are committed to sending the null packet - * (because txnullpkt == 1 && nbytes == 0), or - * (2) we have not yet send the last packet (nbytes > 0). - * In either case, it is appropriate to clearn txnullpkt now. - */ - - privep->txnullpkt = 0; - - /* If we are not sending a NULL packet, then clip the size to maxpacket - * and check if we need to send a following NULL packet. - */ - - if (nbytes > 0) - { - /* Either send the maxpacketsize or all of the remaining data in - * the request. - */ - - if (nbytes >= privep->ep.maxpacket) - { - nbytes = privep->ep.maxpacket; - - /* Handle the case where this packet is exactly the - * maxpacketsize. Do we need to send a zero-length packet - * in this case? - */ - - if (bytesleft == privep->ep.maxpacket && - (privreq->req.flags & USBDEV_REQFLAGS_NULLPKT) != 0) - { - privep->txnullpkt = 1; - } - } - } - - /* Send the packet (might be a null packet nbytes == 0) */ - - buf = privreq->req.buf + privreq->req.xfrd; - stm32_epwrite(priv, privep, buf, nbytes); - - /* Update for the next data IN interrupt */ - - privreq->req.xfrd += nbytes; - bytesleft = privreq->req.len - privreq->req.xfrd; - - /* If all of the bytes were sent (including any final null packet) - * then we are finished with the request buffer). - */ - - if (bytesleft == 0 && !privep->txnullpkt) - { - /* Return the write request to the class driver */ - - usbtrace(TRACE_COMPLETE(USB_EPNO(privep->ep.eplog)), - privreq->req.xfrd); - privep->txnullpkt = 0; - stm32_reqcomplete(privep, OK); - } - - return OK; -} - -/**************************************************************************** - * Name: stm32_ep0_rdrequest - * - * Description: - * This function is called from the stm32_ep0out handler when the ep0state - * is EP0STATE_SETUP_OUT and upon new incoming data is available in the - * endpoint 0's buffer. - * This function will simply copy the OUT data into ep0data. - * - ****************************************************************************/ - -static inline int stm32_ep0_rdrequest(struct stm32_usbdev_s *priv) -{ - uint32_t src; - int pmalen; - int readlen; - - /* Get the number of bytes to read from packet memory */ - - pmalen = stm32_geteprxcount(EP0); - - uinfo("EP0: pmalen=%d\n", pmalen); - usbtrace(TRACE_READ(EP0), pmalen); - - /* Read the data into our special buffer for SETUP data */ - - readlen = MIN(CONFIG_USBDEV_SETUP_MAXDATASIZE, pmalen); - src = stm32_geteprxaddr(EP0); - - /* Receive the next packet */ - - stm32_copyfrompma(&priv->ep0data[0], src, readlen); - - /* Now we can process the setup command */ - - priv->ep0state = EP0STATE_SETUP_READY; - priv->ep0datlen = readlen; - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EP0SETUPOUTDATA), readlen); - - stm32_ep0setup(priv); - priv->ep0datlen = 0; /* mark the date consumed */ - - return OK; -} - -/**************************************************************************** - * Name: stm32_rdrequest - ****************************************************************************/ - -static int stm32_rdrequest(struct stm32_usbdev_s *priv, - struct stm32_ep_s *privep) -{ - struct stm32_req_s *privreq; - uint32_t src; - uint8_t *dest; - uint8_t epno; - int pmalen; - int readlen; - - /* Check the request from the head of the endpoint request queue */ - - epno = USB_EPNO(privep->ep.eplog); - privreq = stm32_rqpeek(privep); - if (!privreq) - { - /* Incoming data available in PMA, but no packet to receive the data. - * Mark that the RX data is pending and hope that a packet is returned - * soon. - */ - - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPOUTQEMPTY), epno); - return -ENOENT; - } - - uinfo("EP%d: len=%zu xfrd=%zu\n", - epno, privreq->req.len, privreq->req.xfrd); - - /* Ignore any attempt to receive a zero length packet */ - - if (privreq->req.len == 0) - { - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EPOUTNULLPACKET), 0); - stm32_reqcomplete(privep, OK); - return OK; - } - - usbtrace(TRACE_READ(USB_EPNO(privep->ep.eplog)), privreq->req.xfrd); - - /* Get the source and destination transfer addresses */ - - dest = privreq->req.buf + privreq->req.xfrd; - src = stm32_geteprxaddr(epno); - - /* Get the number of bytes to read from packet memory */ - - pmalen = stm32_geteprxcount(epno); - readlen = MIN(privreq->req.len, pmalen); - - /* Receive the next packet */ - - stm32_copyfrompma(dest, src, readlen); - - /* If the receive buffer is full or this is a partial packet, - * then we are finished with the request buffer). - */ - - privreq->req.xfrd += readlen; - if (pmalen < privep->ep.maxpacket || privreq->req.xfrd >= privreq->req.len) - { - /* Return the read request to the class driver. */ - - usbtrace(TRACE_COMPLETE(epno), privreq->req.xfrd); - stm32_reqcomplete(privep, OK); - } - - return OK; -} - -/**************************************************************************** - * Name: stm32_cancelrequests - ****************************************************************************/ - -static void stm32_cancelrequests(struct stm32_ep_s *privep) -{ - while (!stm32_rqempty(privep)) - { - usbtrace(TRACE_COMPLETE(USB_EPNO(privep->ep.eplog)), - (stm32_rqpeek(privep))->req.xfrd); - stm32_reqcomplete(privep, -ESHUTDOWN); - } -} - -/**************************************************************************** - * Interrupt Level Processing - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_dispatchrequest - ****************************************************************************/ - -static void stm32_dispatchrequest(struct stm32_usbdev_s *priv) -{ - int ret; - - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_DISPATCH), 0); - if (priv && priv->driver) - { - /* Forward to the control request to the class driver implementation */ - - ret = CLASS_SETUP(priv->driver, &priv->usbdev, &priv->ctrl, - priv->ep0data, priv->ep0datlen); - if (ret < 0) - { - /* Stall on failure */ - - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_DISPATCHSTALL), 0); - priv->ep0state = EP0STATE_STALLED; - } - } -} - -/**************************************************************************** - * Name: stm32_epdone - ****************************************************************************/ - -static void stm32_epdone(struct stm32_usbdev_s *priv, uint8_t epno) -{ - struct stm32_ep_s *privep; - uint16_t epr; - - /* Decode and service non control endpoints interrupt */ - - epr = stm32_getreg(STM32_USB_EPR(epno)); - privep = &priv->eplist[epno]; - - /* OUT: host-to-device - * CTR_RX is set by the hardware when an OUT/SETUP transaction - * successfully completed on this endpoint. - */ - - if ((epr & USB_EPR_CTR_RX) != 0) - { - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPOUTDONE), epr); - - /* Handle read requests. First check if a read request is available to - * accept the host data. - */ - - if (!stm32_rqempty(privep)) - { - /* Read host data into the current read request */ - - stm32_rdrequest(priv, privep); - - /* "After the received data is processed, the application software - * should set the STAT_RX bits to '11' (Valid) in the USB_EPnR, - * enabling further transactions. " - */ - - priv->rxstatus = USB_EPR_STATRX_VALID; - } - - /* NAK further OUT packets if there there no more read requests */ - - if (stm32_rqempty(privep)) - { - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPOUTPENDING), - (uint16_t)epno); - - /* Mark the RX processing as pending and NAK any OUT actions - * on this endpoint. "While the STAT_RX bits are equal to '10' - * (NAK), any OUT request addressed to that endpoint is NAKed, - * indicating a flow control condition: the USB host will retry - * the transaction until it succeeds." - */ - - priv->rxstatus = USB_EPR_STATRX_NAK; - priv->rxpending = true; - } - - /* Clear the interrupt status and set the new RX status */ - - stm32_clrepctrrx(epno); - stm32_seteprxstatus(epno, priv->rxstatus); - } - - /* IN: device-to-host - * CTR_TX is set when an IN transaction successfully completes on - * an endpoint - */ - - else if ((epr & USB_EPR_CTR_TX) != 0) - { - /* Clear interrupt status */ - - stm32_clrepctrtx(epno); - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPINDONE), epr); - - /* Handle write requests */ - - priv->txstatus = USB_EPR_STATTX_NAK; - if (epno == EP0) - { - stm32_wrrequest_ep0(priv, privep); - } - else - { - stm32_wrrequest(priv, privep); - } - - /* Set the new TX status */ - - stm32_seteptxstatus(epno, priv->txstatus); - } -} - -/**************************************************************************** - * Name: stm32_setdevaddr - ****************************************************************************/ - -static void stm32_setdevaddr(struct stm32_usbdev_s *priv, uint8_t value) -{ - int epno; - - /* Set address in every allocated endpoint */ - - for (epno = 0; epno < STM32_NENDPOINTS; epno++) - { - if (stm32_epreserved(priv, epno)) - { - stm32_setepaddress((uint8_t)epno, (uint8_t)epno); - } - } - - /* Set the device address and enable function */ - - stm32_putreg(value | USB_DADDR_EF, STM32_USB_DADDR); -} - -/**************************************************************************** - * Name: stm32_ep0setup - ****************************************************************************/ - -static void stm32_ep0setup(struct stm32_usbdev_s *priv) -{ - struct stm32_ep_s *ep0 = &priv->eplist[EP0]; - struct stm32_req_s *privreq = stm32_rqpeek(ep0); - struct stm32_ep_s *privep; - union wb_u value; - union wb_u index; - union wb_u len; - union wb_u response; - bool handled = false; - uint8_t epno; - int nbytes = 0; /* Assume zero-length packet */ - - /* Terminate any pending requests (doesn't work if the pending request - * was a zero-length transfer!) - */ - - while (!stm32_rqempty(ep0)) - { - int16_t result = OK; - if (privreq->req.xfrd != privreq->req.len) - { - result = -EPROTO; - } - - usbtrace(TRACE_COMPLETE(ep0->ep.eplog), privreq->req.xfrd); - stm32_reqcomplete(ep0, result); - } - - /* Assume NOT stalled; no TX in progress */ - - ep0->stalled = 0; - ep0->txbusy = 0; - - /* Check to see if called from the DATA phase of a SETUP Transfer */ - - if (priv->ep0state != EP0STATE_SETUP_READY) - { - /* Not the data phase */ - - /* Get a 32-bit PMA address and use that to get the 8-byte setup - * request - */ - - stm32_copyfrompma((uint8_t *)&priv->ctrl, stm32_geteprxaddr(EP0), - USB_SIZEOF_CTRLREQ); - - /* And extract the little-endian 16-bit values to host order */ - - value.w = GETUINT16(priv->ctrl.value); - index.w = GETUINT16(priv->ctrl.index); - len.w = GETUINT16(priv->ctrl.len); - - uinfo("SETUP: type=%02x req=%02x value=%04x index=%04x len=%04x\n", - priv->ctrl.type, priv->ctrl.req, value.w, index.w, len.w); - - /* Is this an setup with OUT and data of length > 0 */ - - if (USB_REQ_ISOUT(priv->ctrl.type) && len.w > 0) - { - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EP0SETUPOUT), len.w); - - /* At this point priv->ctrl is the setup packet. */ - - priv->ep0state = EP0STATE_SETUP_OUT; - return; - } - else - { - priv->ep0state = EP0STATE_SETUP_READY; - } - } - - /* Dispatch any non-standard requests */ - - if ((priv->ctrl.type & USB_REQ_TYPE_MASK) != USB_REQ_TYPE_STANDARD) - { - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_NOSTDREQ), priv->ctrl.type); - - /* Let the class implementation handle all non-standar requests */ - - stm32_dispatchrequest(priv); - return; - } - - /* Handle standard request. Pick off the things of interest to the - * USB device controller driver; pass what is left to the class driver - */ - - switch (priv->ctrl.req) - { - case USB_REQ_GETSTATUS: - { - /* type: device-to-host; recipient = device, interface, endpoint - * value: 0 - * index: zero interface endpoint - * len: 2; data = status - */ - - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_GETSTATUS), - priv->ctrl.type); - if (len.w != 2 || (priv->ctrl.type & USB_REQ_DIR_IN) == 0 || - index.b[MSB] != 0 || value.w != 0) - { - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADEPGETSTATUS), 0); - priv->ep0state = EP0STATE_STALLED; - } - else - { - switch (priv->ctrl.type & USB_REQ_RECIPIENT_MASK) - { - case USB_REQ_RECIPIENT_ENDPOINT: - { - epno = USB_EPNO(index.b[LSB]); - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPGETSTATUS), - epno); - if (epno >= STM32_NENDPOINTS) - { - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADEPGETSTATUS), - epno); - priv->ep0state = EP0STATE_STALLED; - } - else - { - response.w = 0; /* Not stalled */ - nbytes = 2; /* Response size: 2 bytes */ - - if (USB_ISEPIN(index.b[LSB])) - { - /* IN endpoint */ - - if (stm32_eptxstalled(epno)) - { - /* IN Endpoint stalled */ - - response.b[LSB] = 1; /* Stalled */ - } - } - else - { - /* OUT endpoint */ - - if (stm32_eprxstalled(epno)) - { - /* OUT Endpoint stalled */ - - response.b[LSB] = 1; /* Stalled */ - } - } - } - } - break; - - case USB_REQ_RECIPIENT_DEVICE: - { - if (index.w == 0) - { - usbtrace(TRACE_INTDECODE( - STM32_TRACEINTID_DEVGETSTATUS), 0); - - /* Features: Remote Wakeup=YES; selfpowered=? */ - - response.w = 0; - response.b[LSB] = (priv->selfpowered << - USB_FEATURE_SELFPOWERED) | - (1 << USB_FEATURE_REMOTEWAKEUP); - nbytes = 2; /* Response size: 2 bytes */ - } - else - { - usbtrace(TRACE_DEVERROR( - STM32_TRACEERR_BADDEVGETSTATUS), 0); - priv->ep0state = EP0STATE_STALLED; - } - } - break; - - case USB_REQ_RECIPIENT_INTERFACE: - { - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_IFGETSTATUS), 0); - response.w = 0; - nbytes = 2; /* Response size: 2 bytes */ - } - break; - - default: - { - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADGETSTATUS), 0); - priv->ep0state = EP0STATE_STALLED; - } - break; - } - } - } - break; - - case USB_REQ_CLEARFEATURE: - { - /* type: host-to-device; recipient = device, interface or endpoint - * value: feature selector - * index: zero interface endpoint; - * len: zero, data = none - */ - - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_CLEARFEATURE), - priv->ctrl.type); - if ((priv->ctrl.type & USB_REQ_RECIPIENT_MASK) != - USB_REQ_RECIPIENT_ENDPOINT) - { - /* Let the class implementation handle all recipients - * (except for the endpoint recipient) - */ - - stm32_dispatchrequest(priv); - handled = true; - } - else - { - /* Endpoint recipient */ - - epno = USB_EPNO(index.b[LSB]); - if (epno < STM32_NENDPOINTS && index.b[MSB] == 0 && - value.w == USB_FEATURE_ENDPOINTHALT && len.w == 0) - { - privep = &priv->eplist[epno]; - privep->halted = 0; - stm32_epstall(&privep->ep, true); - } - else - { - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADCLEARFEATURE), 0); - priv->ep0state = EP0STATE_STALLED; - } - } - } - break; - - case USB_REQ_SETFEATURE: - { - /* type: host-to-device; recipient = device, interface, endpoint - * value: feature selector - * index: zero interface endpoint; - * len: 0; data = none - */ - - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SETFEATURE), - priv->ctrl.type); - if (((priv->ctrl.type & USB_REQ_RECIPIENT_MASK) == - USB_REQ_RECIPIENT_DEVICE) && - value.w == USB_FEATURE_TESTMODE) - { - /* Special case recipient=device test mode */ - - uinfo("test mode: %d\n", index.w); - } - else if ((priv->ctrl.type & USB_REQ_RECIPIENT_MASK) != - USB_REQ_RECIPIENT_ENDPOINT) - { - /* The class driver handles all recipients except - * recipient=endpoint - */ - - stm32_dispatchrequest(priv); - handled = true; - } - else - { - /* Handler recipient=endpoint */ - - epno = USB_EPNO(index.b[LSB]); - if (epno < STM32_NENDPOINTS && index.b[MSB] == 0 && - value.w == USB_FEATURE_ENDPOINTHALT && len.w == 0) - { - privep = &priv->eplist[epno]; - privep->halted = 1; - stm32_epstall(&privep->ep, false); - } - else - { - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADSETFEATURE), 0); - priv->ep0state = EP0STATE_STALLED; - } - } - } - break; - - case USB_REQ_SETADDRESS: - { - /* type: host-to-device; recipient = device - * value: device address - * index: 0 - * len: 0; data = none - */ - - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EP0SETUPSETADDRESS), - value.w); - if ((priv->ctrl.type & USB_REQ_RECIPIENT_MASK) != - USB_REQ_RECIPIENT_DEVICE || - index.w != 0 || len.w != 0 || value.w > 127) - { - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADSETADDRESS), 0); - priv->ep0state = EP0STATE_STALLED; - } - - /* Note that setting of the device address will be deferred. - * A zero-length packet will be sent and the device address will - * be set when the zero- length packet transfer completes. - */ - } - break; - - case USB_REQ_GETDESCRIPTOR: - /* type: device-to-host; recipient = device - * value: descriptor type and index - * index: 0 or language ID; - * len: descriptor len; data = descriptor - */ - - case USB_REQ_SETDESCRIPTOR: - /* type: host-to-device; recipient = device - * value: descriptor type and index - * index: 0 or language ID; - * len: descriptor len; data = descriptor - */ - - { - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_GETSETDESC), - priv->ctrl.type); - if ((priv->ctrl.type & USB_REQ_RECIPIENT_MASK) == - USB_REQ_RECIPIENT_DEVICE) - { - /* The request seems valid... - * let the class implementation handle it - */ - - stm32_dispatchrequest(priv); - handled = true; - } - else - { - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADGETSETDESC), 0); - priv->ep0state = EP0STATE_STALLED; - } - } - break; - - case USB_REQ_GETCONFIGURATION: - /* type: device-to-host; recipient = device - * value: 0; - * index: 0; - * len: 1; data = configuration value - */ - - { - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_GETCONFIG), - priv->ctrl.type); - if ((priv->ctrl.type & USB_REQ_RECIPIENT_MASK) == - USB_REQ_RECIPIENT_DEVICE && - value.w == 0 && index.w == 0 && len.w == 1) - { - /* The request seems valid... - * let the class implementation handle it - */ - - stm32_dispatchrequest(priv); - handled = true; - } - else - { - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADGETCONFIG), 0); - priv->ep0state = EP0STATE_STALLED; - } - } - break; - - case USB_REQ_SETCONFIGURATION: - /* type: host-to-device; recipient = device - * value: configuration value - * index: 0; - * len: 0; data = none - */ - - { - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SETCONFIG), - priv->ctrl.type); - if ((priv->ctrl.type & USB_REQ_RECIPIENT_MASK) == - USB_REQ_RECIPIENT_DEVICE && - index.w == 0 && len.w == 0) - { - /* The request seems valid... - * let the class implementation handle it - */ - - stm32_dispatchrequest(priv); - handled = true; - } - else - { - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADSETCONFIG), 0); - priv->ep0state = EP0STATE_STALLED; - } - } - break; - - case USB_REQ_GETINTERFACE: - /* type: device-to-host; recipient = interface - * value: 0 - * index: interface; - * len: 1; data = alt interface - */ - - case USB_REQ_SETINTERFACE: - /* type: host-to-device; recipient = interface - * value: alternate setting - * index: interface; - * len: 0; data = none - */ - - { - /* Let the class implementation handle the request */ - - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_GETSETIF), - priv->ctrl.type); - stm32_dispatchrequest(priv); - handled = true; - } - break; - - case USB_REQ_SYNCHFRAME: - /* type: device-to-host; recipient = endpoint - * value: 0 - * index: endpoint; - * len: 2; data = frame number - */ - - { - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SYNCHFRAME), 0); - } - break; - - default: - { - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDCTRLREQ), - priv->ctrl.req); - priv->ep0state = EP0STATE_STALLED; - } - break; - } - - /* At this point, the request has been handled and there are three - * possible outcomes: - * - * 1. The setup request was successfully handled above and a response - * packet must be sent (may be a zero length packet). - * 2. The request was successfully handled by the class implementation. - * In case, the EP0 IN response has already been queued and the local - * variable 'handled' will be set to true and - * ep0state != EP0STATE_STALLED; - * 3. An error was detected in either the above logic or by the class - * implementation logic. In either case, priv->state will be set - * EP0STATE_STALLED to indicate this case. - * - * NOTE: Non-standard requests are a special case. They are handled by the - * class implementation and this function returned early above, skipping - * this logic altogether. - */ - - if (priv->ep0state != EP0STATE_STALLED && !handled) - { - /* We will response. First, restrict the data length to the length - * requested in the setup packet - */ - - if (nbytes > len.w) - { - nbytes = len.w; - } - - /* Send the response (might be a zero-length packet) */ - - stm32_epwrite(priv, ep0, response.b, nbytes); - priv->ep0state = EP0STATE_IDLE; - } -} - -/**************************************************************************** - * Name: stm32_ep0in - ****************************************************************************/ - -static void stm32_ep0in(struct stm32_usbdev_s *priv) -{ - /* There is no longer anything in the EP0 TX packet memory */ - - priv->eplist[EP0].txbusy = false; - - /* Are we processing the completion of one packet of an outgoing request - * from the class driver? - */ - - if (priv->ep0state == EP0STATE_WRREQUEST) - { - stm32_wrrequest_ep0(priv, &priv->eplist[EP0]); - } - - /* No.. Are we processing the completion of a status response? */ - - else if (priv->ep0state == EP0STATE_IDLE) - { - /* Look at the saved SETUP command. Was it a SET ADDRESS request? - * If so, then now is the time to set the address. - */ - - if (priv->ctrl.req == USB_REQ_SETADDRESS && - (priv->ctrl.type & REQRECIPIENT_MASK) == - (USB_REQ_TYPE_STANDARD | USB_REQ_RECIPIENT_DEVICE)) - { - union wb_u value; - value.w = GETUINT16(priv->ctrl.value); - stm32_setdevaddr(priv, value.b[LSB]); - } - } - else - { - priv->ep0state = EP0STATE_STALLED; - } -} - -/**************************************************************************** - * Name: stm32_ep0out - ****************************************************************************/ - -static void stm32_ep0out(struct stm32_usbdev_s *priv) -{ - int ret; - - struct stm32_ep_s *privep = &priv->eplist[EP0]; - switch (priv->ep0state) - { - case EP0STATE_RDREQUEST: /* Read request in progress */ - case EP0STATE_IDLE: /* No transfer in progress */ - ret = stm32_rdrequest(priv, privep); - priv->ep0state = ((ret == OK) ? EP0STATE_RDREQUEST : EP0STATE_IDLE); - break; - - case EP0STATE_SETUP_OUT: /* SETUP was waiting for data */ - ret = stm32_ep0_rdrequest(priv); /* Off load the data and run the - * last set up command with the OUT - * data - */ - priv->ep0state = EP0STATE_IDLE; /* There is no notion of receiving OUT - * data greater then the length of - * CONFIG_USBDEV_SETUP_MAXDATASIZE - * so we are done - */ - break; - - default: - /* Unexpected state OR host aborted the OUT transfer before it - * completed, STALL the endpoint in either case - */ - - priv->ep0state = EP0STATE_STALLED; - break; - } -} - -/**************************************************************************** - * Name: stm32_ep0done - ****************************************************************************/ - -static inline void stm32_ep0done(struct stm32_usbdev_s *priv, uint16_t istr) -{ - uint16_t epr; - - /* Initialize RX and TX status. We shouldn't have to actually look at the - * status because the hardware is supposed to set the both RX and TX status - * to NAK when an EP0 SETUP occurs (of course, this might not be a setup) - */ - - priv->rxstatus = USB_EPR_STATRX_NAK; - priv->txstatus = USB_EPR_STATTX_NAK; - - /* Set both RX and TX status to NAK */ - - stm32_seteprxstatus(EP0, USB_EPR_STATRX_NAK); - stm32_seteptxstatus(EP0, USB_EPR_STATTX_NAK); - - /* Check the direction bit to determine if this the completion of an EP0 - * packet sent to or received from the host PC. - */ - - if ((istr & USB_ISTR_DIR) == 0) - { - /* EP0 IN: device-to-host (DIR=0) */ - - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EP0IN), istr); - stm32_clrepctrtx(EP0); - stm32_ep0in(priv); - } - else - { - /* EP0 OUT: host-to-device (DIR=1) */ - - epr = stm32_getreg(STM32_USB_EPR(EP0)); - - /* CTR_TX is set when an IN transaction successfully - * completes on an endpoint - */ - - if ((epr & USB_EPR_CTR_TX) != 0) - { - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EP0INDONE), epr); - stm32_clrepctrtx(EP0); - stm32_ep0in(priv); - } - - /* SETUP is set by the hardware when the last completed - * transaction was a control endpoint SETUP - */ - - else if ((epr & USB_EPR_SETUP) != 0) - { - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EP0SETUPDONE), epr); - stm32_clrepctrrx(EP0); - stm32_ep0setup(priv); - } - - /* Set by the hardware when an OUT/SETUP transaction successfully - * completed on this endpoint. - */ - - else if ((epr & USB_EPR_CTR_RX) != 0) - { - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EP0OUTDONE), epr); - stm32_clrepctrrx(EP0); - stm32_ep0out(priv); - } - - /* None of the above */ - - else - { - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EP0BADCTR), epr); - return; /* Does this ever happen? */ - } - } - - /* Make sure that the EP0 packet size is still OK (superstitious?) */ - - stm32_seteprxcount(EP0, STM32_EP0MAXPACKET); - - /* Now figure out the new RX/TX status. Here are all possible - * consequences of the above EP0 operations: - * - * rxstatus txstatus ep0state MEANING - * -------- -------- --------- --------------------------------- - * NAK NAK IDLE Nothing happened - * NAK VALID IDLE EP0 response sent from USBDEV driver - * NAK VALID WRREQUEST EP0 response sent from class driver - * NAK --- STALL Some protocol error occurred - * - * First handle the STALL condition: - */ - - if (priv->ep0state == EP0STATE_STALLED) - { - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EP0SETUPSTALLED), - priv->ep0state); - priv->rxstatus = USB_EPR_STATRX_STALL; - priv->txstatus = USB_EPR_STATTX_STALL; - } - - /* Was a transmission started? If so, txstatus will be VALID. The - * only special case to handle is when both are set to NAK. In that - * case, we need to set RX status to VALID in order to accept the next - * SETUP request. - */ - - else if (priv->rxstatus == USB_EPR_STATRX_NAK && - priv->txstatus == USB_EPR_STATTX_NAK) - { - priv->rxstatus = USB_EPR_STATRX_VALID; - } - - /* Now set the new TX and RX status */ - - stm32_seteprxstatus(EP0, priv->rxstatus); - stm32_seteptxstatus(EP0, priv->txstatus); -} - -/**************************************************************************** - * Name: stm32_lptransfer - ****************************************************************************/ - -static void stm32_lptransfer(struct stm32_usbdev_s *priv) -{ - uint8_t epno; - uint16_t istr; - - /* Stay in loop while LP interrupts are pending */ - - while (((istr = stm32_getreg(STM32_USB_ISTR)) & USB_ISTR_CTR) != 0) - { - stm32_putreg((uint16_t)~USB_ISTR_CTR, STM32_USB_ISTR); - - /* Extract highest priority endpoint number */ - - epno = (uint8_t)(istr & USB_ISTR_EPID_MASK); - - /* Handle EP0 completion events */ - - if (epno == 0) - { - stm32_ep0done(priv, istr); - } - - /* Handle other endpoint completion events */ - - else - { - stm32_epdone(priv, epno); - } - } -} - -/**************************************************************************** - * Name: stm32_usb_interrupt - ****************************************************************************/ - -static int stm32_usb_interrupt(int irq, void *context, void *arg) -{ - struct stm32_usbdev_s *priv = (struct stm32_usbdev_s *)arg; - uint16_t istr; - uint8_t epno; - - DEBUGASSERT(priv != NULL); - - /* High priority interrupts are only triggered by a correct transfer event - * for isochronous and double-buffer bulk transfers. - */ - - istr = stm32_getreg(STM32_USB_ISTR); - usbtrace(TRACE_INTENTRY(STM32_TRACEINTID_INTERRUPT), istr); - while ((istr & USB_ISTR_CTR) != 0) - { - stm32_putreg((uint16_t)~USB_ISTR_CTR, STM32_USB_ISTR); - - /* Extract highest priority endpoint number */ - - epno = (uint8_t)(istr & USB_ISTR_EPID_MASK); - - /* And handle the completion event */ - - stm32_epdone(priv, epno); - - /* Fetch the status again for the next time through the loop */ - - istr = stm32_getreg(STM32_USB_ISTR); - } - - /* Handle Reset interrupts. When this event occurs, the peripheral is left - * in the same conditions it is left by the system reset (but with the - * USB controller enabled). - */ - - if ((istr & USB_ISTR_RESET) != 0) - { - /* Reset interrupt received. Clear the RESET interrupt status. */ - - stm32_putreg(~USB_ISTR_RESET, STM32_USB_ISTR); - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_RESET), istr); - - /* Restore our power-up state and exit now because istr is no longer - * valid. - */ - - stm32_reset(priv); - goto exit_interrupt; - } - - /* Handle Wakeup interrupts. - * This interrupt is only enable while the USB is suspended. - */ - - if ((istr & USB_ISTR_WKUP & priv->imask) != 0) - { - /* Wakeup interrupt received. Clear the WKUP interrupt status. - * The cause of the resume is indicated in the FNR register - */ - - stm32_putreg(~USB_ISTR_WKUP, STM32_USB_ISTR); - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_WKUP), - stm32_getreg(STM32_USB_FNR)); - - /* Perform the wakeup action */ - - stm32_initresume(priv); - priv->rsmstate = RSMSTATE_IDLE; - - /* Disable ESOF polling, disable the wakeup interrupt, and - * re-enable the suspend interrupt. Clear any pending SUSP - * interrupts. - */ - - stm32_setimask(priv, USB_CNTR_SUSPM, USB_CNTR_ESOFM | USB_CNTR_WKUPM); - stm32_putreg(~USB_CNTR_SUSPM, STM32_USB_ISTR); - } - - if ((istr & USB_ISTR_SUSP & priv->imask) != 0) - { - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SUSP), 0); - stm32_suspend(priv); - - /* Clear of the ISTR bit must be done after setting of - * USB_CNTR_FSUSP - */ - - stm32_putreg(~USB_ISTR_SUSP, STM32_USB_ISTR); - } - - if ((istr & USB_ISTR_ESOF & priv->imask) != 0) - { - stm32_putreg(~USB_ISTR_ESOF, STM32_USB_ISTR); - - /* Resume handling timing is made with ESOFs */ - - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_ESOF), 0); - stm32_esofpoll(priv); - } - - if ((istr & USB_ISTR_CTR & priv->imask) != 0) - { - /* Low priority endpoint correct transfer interrupt */ - - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_LPCTR), istr); - stm32_lptransfer(priv); - } - -exit_interrupt: - usbtrace(TRACE_INTEXIT(STM32_TRACEINTID_INTERRUPT), 0); - return OK; -} - -/**************************************************************************** - * Name: stm32_setimask - ****************************************************************************/ - -static void -stm32_setimask(struct stm32_usbdev_s *priv, - uint16_t setbits, uint16_t clrbits) -{ - uint16_t regval; - - /* Adjust the interrupt mask bits in the shadow copy first */ - - priv->imask &= ~clrbits; - priv->imask |= setbits; - - /* Then make the interrupt mask bits in the CNTR register match the - * shadow register (Hmmm... who is shadowing whom?) - */ - - regval = stm32_getreg(STM32_USB_CNTR); - regval &= ~USB_CNTR_ALLINTS; - regval |= priv->imask; - stm32_putreg(regval, STM32_USB_CNTR); -} - -/**************************************************************************** - * Suspend/Resume Helpers - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_suspend - ****************************************************************************/ - -static void stm32_suspend(struct stm32_usbdev_s *priv) -{ - uint16_t regval; - - /* Notify the class driver of the suspend event */ - - if (priv->driver) - { - CLASS_SUSPEND(priv->driver, &priv->usbdev); - } - - /* Disable ESOF polling, disable the SUSP interrupt, and enable the WKUP - * interrupt. Clear any pending WKUP interrupt. - */ - - stm32_setimask(priv, USB_CNTR_WKUPM, USB_CNTR_ESOFM | USB_CNTR_SUSPM); - stm32_putreg(~USB_ISTR_WKUP, STM32_USB_ISTR); - - /* Set the FSUSP bit in the CNTR register. This activates suspend mode - * within the USB peripheral and disables further SUSP interrupts. - */ - - regval = stm32_getreg(STM32_USB_CNTR); - regval |= USB_CNTR_FSUSP; - stm32_putreg(regval, STM32_USB_CNTR); - - /* If we are not a self-powered device, the got to low-power mode */ - - if (!priv->selfpowered) - { - /* Setting LPMODE in the CNTR register removes static power - * consumption in the USB analog transceivers but keeps them - * able to detect resume activity - */ - - regval = stm32_getreg(STM32_USB_CNTR); - regval |= USB_CNTR_LPMODE; - stm32_putreg(regval, STM32_USB_CNTR); - } - - /* Let the board-specific logic know that we have entered the suspend - * state - */ - - stm32_usbsuspend((struct usbdev_s *)priv, false); -} - -/**************************************************************************** - * Name: stm32_initresume - ****************************************************************************/ - -static void stm32_initresume(struct stm32_usbdev_s *priv) -{ - uint16_t regval; - - /* This function is called when either (1) a WKUP interrupt is received - * from the host PC, or (2) the class device implementation calls the - * wakeup() method. - */ - - /* Clear the USB low power mode (lower power mode was not set if this is - * a self-powered device. Also, low power mode is automatically cleared - * by hardware when a WKUP interrupt event occurs). - */ - - regval = stm32_getreg(STM32_USB_CNTR); - regval &= (~USB_CNTR_LPMODE); - stm32_putreg(regval, STM32_USB_CNTR); - - /* Restore full power -- whatever that means for this particular board */ - - stm32_usbsuspend((struct usbdev_s *)priv, true); - - /* Reset FSUSP bit and enable normal interrupt handling */ - - stm32_putreg(STM32_CNTR_SETUP, STM32_USB_CNTR); - - /* Notify the class driver of the resume event */ - - if (priv->driver) - { - CLASS_RESUME(priv->driver, &priv->usbdev); - } -} - -/**************************************************************************** - * Name: stm32_esofpoll - ****************************************************************************/ - -static void stm32_esofpoll(struct stm32_usbdev_s *priv) -{ - uint16_t regval; - - /* Called periodically from ESOF interrupt after RSMSTATE_STARTED */ - - switch (priv->rsmstate) - { - /* One ESOF after internal resume requested */ - - case RSMSTATE_STARTED: - regval = stm32_getreg(STM32_USB_CNTR); - regval |= USB_CNTR_RESUME; - stm32_putreg(regval, STM32_USB_CNTR); - priv->rsmstate = RSMSTATE_WAITING; - priv->nesofs = 10; - break; - - /* Countdown before completing the operation */ - - case RSMSTATE_WAITING: - priv->nesofs--; - if (priv->nesofs == 0) - { - /* Okay.. we are ready to resume normal operation */ - - regval = stm32_getreg(STM32_USB_CNTR); - regval &= (~USB_CNTR_RESUME); - stm32_putreg(regval, STM32_USB_CNTR); - priv->rsmstate = RSMSTATE_IDLE; - - /* Disable ESOF polling, disable the SUSP interrupt, and enable - * the WKUP interrupt. Clear any pending WKUP interrupt. - */ - - stm32_setimask(priv, - USB_CNTR_WKUPM, USB_CNTR_ESOFM | USB_CNTR_SUSPM); - stm32_putreg(~USB_ISTR_WKUP, STM32_USB_ISTR); - } - break; - - case RSMSTATE_IDLE: - default: - priv->rsmstate = RSMSTATE_IDLE; - break; - } -} - -/**************************************************************************** - * Endpoint Helpers - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_epreserve - ****************************************************************************/ - -static inline struct stm32_ep_s * -stm32_epreserve(struct stm32_usbdev_s *priv, uint8_t epset) -{ - struct stm32_ep_s *privep = NULL; - irqstate_t flags; - int epndx = 0; - - flags = enter_critical_section(); - epset &= priv->epavail; - if (epset) - { - /* Select the lowest bit in the set of matching, available endpoints - * (skipping EP0) - */ - - for (epndx = 1; epndx < STM32_NENDPOINTS; epndx++) - { - uint8_t bit = STM32_ENDP_BIT(epndx); - if ((epset & bit) != 0) - { - /* Mark the endpoint no longer available */ - - priv->epavail &= ~bit; - - /* And return the pointer to the standard endpoint structure */ - - privep = &priv->eplist[epndx]; - break; - } - } - } - - leave_critical_section(flags); - return privep; -} - -/**************************************************************************** - * Name: stm32_epunreserve - ****************************************************************************/ - -static inline void -stm32_epunreserve(struct stm32_usbdev_s *priv, struct stm32_ep_s *privep) -{ - irqstate_t flags = enter_critical_section(); - priv->epavail |= STM32_ENDP_BIT(USB_EPNO(privep->ep.eplog)); - leave_critical_section(flags); -} - -/**************************************************************************** - * Name: stm32_epreserved - ****************************************************************************/ - -static inline bool -stm32_epreserved(struct stm32_usbdev_s *priv, int epno) -{ - return ((priv->epavail & STM32_ENDP_BIT(epno)) == 0); -} - -/**************************************************************************** - * Name: stm32_epallocpma - ****************************************************************************/ - -static int stm32_epallocpma(struct stm32_usbdev_s *priv) -{ - irqstate_t flags; - int bufno = ERROR; - int bufndx; - - flags = enter_critical_section(); - for (bufndx = 2; bufndx < STM32_NBUFFERS; bufndx++) - { - /* Check if this buffer is available */ - - uint8_t bit = STM32_BUFFER_BIT(bufndx); - if ((priv->bufavail & bit) != 0) - { - /* Yes.. Mark the endpoint no longer available */ - - priv->bufavail &= ~bit; - - /* And return the index of the allocated buffer */ - - bufno = bufndx; - break; - } - } - - leave_critical_section(flags); - return bufno; -} - -/**************************************************************************** - * Name: stm32_epfreepma - ****************************************************************************/ - -static inline void -stm32_epfreepma(struct stm32_usbdev_s *priv, struct stm32_ep_s *privep) -{ - irqstate_t flags = enter_critical_section(); - priv->epavail |= STM32_ENDP_BIT(privep->bufno); - leave_critical_section(flags); -} - -/**************************************************************************** - * Endpoint operations - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_epconfigure - ****************************************************************************/ - -static int stm32_epconfigure(struct usbdev_ep_s *ep, - const struct usb_epdesc_s *desc, - bool last) -{ - struct stm32_ep_s *privep = (struct stm32_ep_s *)ep; - uint16_t pma; - uint16_t setting; - uint16_t maxpacket; - uint8_t epno; - -#ifdef CONFIG_DEBUG_FEATURES - if (!ep || !desc) - { - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); - uerr("ERROR: ep=%p desc=%p\n", ep, desc); - return -EINVAL; - } -#endif - - /* Get the unadorned endpoint address */ - - epno = USB_EPNO(desc->addr); - usbtrace(TRACE_EPCONFIGURE, (uint16_t)epno); - DEBUGASSERT(epno == USB_EPNO(ep->eplog)); - - /* Set the requested type */ - - switch (desc->attr & USB_EP_ATTR_XFERTYPE_MASK) - { - case USB_EP_ATTR_XFER_INT: /* Interrupt endpoint */ - setting = USB_EPR_EPTYPE_INTERRUPT; - break; - - case USB_EP_ATTR_XFER_BULK: /* Bulk endpoint */ - setting = USB_EPR_EPTYPE_BULK; - break; - - case USB_EP_ATTR_XFER_ISOC: /* Isochronous endpoint */ -#warning "REVISIT: Need to review isochronous EP setup" - setting = USB_EPR_EPTYPE_ISOC; - break; - - case USB_EP_ATTR_XFER_CONTROL: /* Control endpoint */ - setting = USB_EPR_EPTYPE_CONTROL; - break; - - default: - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADEPTYPE), - (uint16_t)desc->type); - return -EINVAL; - } - - stm32_seteptype(epno, setting); - - /* Get the address of the PMA buffer allocated for this endpoint */ - -#warning "REVISIT: Should configure BULK EPs using double buffer feature" - pma = STM32_BUFNO2BUF(privep->bufno); - - /* Get the maxpacket size of the endpoint. */ - - maxpacket = GETUINT16(desc->mxpacketsize); - DEBUGASSERT(maxpacket <= STM32_MAXPACKET_SIZE); - ep->maxpacket = maxpacket; - - /* Get the subset matching the requested direction */ - - if (USB_ISEPIN(desc->addr)) - { - /* The full, logical EP number includes direction */ - - ep->eplog = USB_EPIN(epno); - - /* Set up TX; disable RX */ - - stm32_seteptxaddr(epno, pma); - stm32_seteptxstatus(epno, USB_EPR_STATTX_NAK); - stm32_seteprxstatus(epno, USB_EPR_STATRX_DIS); - } - else - { - /* The full, logical EP number includes direction */ - - ep->eplog = USB_EPOUT(epno); - - /* Set up RX; disable TX */ - - stm32_seteprxaddr(epno, pma); - stm32_seteprxcount(epno, maxpacket); - stm32_seteprxstatus(epno, USB_EPR_STATRX_VALID); - stm32_seteptxstatus(epno, USB_EPR_STATTX_DIS); - } - - stm32_dumpep(epno); - return OK; -} - -/**************************************************************************** - * Name: stm32_epdisable - ****************************************************************************/ - -static int stm32_epdisable(struct usbdev_ep_s *ep) -{ - struct stm32_ep_s *privep = (struct stm32_ep_s *)ep; - irqstate_t flags; - uint8_t epno; - -#ifdef CONFIG_DEBUG_FEATURES - if (!ep) - { - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); - uerr("ERROR: ep=%p\n", ep); - return -EINVAL; - } -#endif - - epno = USB_EPNO(ep->eplog); - usbtrace(TRACE_EPDISABLE, epno); - - /* Cancel any ongoing activity */ - - flags = enter_critical_section(); - stm32_cancelrequests(privep); - - /* Disable TX; disable RX */ - - stm32_seteprxcount(epno, 0); - stm32_seteprxstatus(epno, USB_EPR_STATRX_DIS); - stm32_seteptxstatus(epno, USB_EPR_STATTX_DIS); - - leave_critical_section(flags); - return OK; -} - -/**************************************************************************** - * Name: stm32_epallocreq - ****************************************************************************/ - -static struct usbdev_req_s *stm32_epallocreq(struct usbdev_ep_s *ep) -{ - struct stm32_req_s *privreq; - -#ifdef CONFIG_DEBUG_FEATURES - if (!ep) - { - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); - return NULL; - } -#endif - usbtrace(TRACE_EPALLOCREQ, USB_EPNO(ep->eplog)); - - privreq = kmm_malloc(sizeof(struct stm32_req_s)); - if (!privreq) - { - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_ALLOCFAIL), 0); - return NULL; - } - - memset(privreq, 0, sizeof(struct stm32_req_s)); - return &privreq->req; -} - -/**************************************************************************** - * Name: stm32_epfreereq - ****************************************************************************/ - -static void stm32_epfreereq(struct usbdev_ep_s *ep, struct usbdev_req_s *req) -{ - struct stm32_req_s *privreq = (struct stm32_req_s *)req; - -#ifdef CONFIG_DEBUG_FEATURES - if (!ep || !req) - { - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); - return; - } -#endif - usbtrace(TRACE_EPFREEREQ, USB_EPNO(ep->eplog)); - - kmm_free(privreq); -} - -/**************************************************************************** - * Name: stm32_epsubmit - ****************************************************************************/ - -static int stm32_epsubmit(struct usbdev_ep_s *ep, - struct usbdev_req_s *req) -{ - struct stm32_req_s *privreq = (struct stm32_req_s *)req; - struct stm32_ep_s *privep = (struct stm32_ep_s *)ep; - struct stm32_usbdev_s *priv; - irqstate_t flags; - uint8_t epno; - int ret = OK; - -#ifdef CONFIG_DEBUG_FEATURES - if (!req || !req->callback || !req->buf || !ep) - { - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); - uerr("ERROR: req=%p callback=%p buf=%p ep=%p\n", - req, req->callback, req->buf, ep); - return -EINVAL; - } -#endif - - usbtrace(TRACE_EPSUBMIT, USB_EPNO(ep->eplog)); - priv = privep->dev; - -#ifdef CONFIG_DEBUG_FEATURES - if (!priv->driver) - { - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_NOTCONFIGURED), - priv->usbdev.speed); - uerr("ERROR: driver=%p\n", priv->driver); - return -ESHUTDOWN; - } -#endif - - /* Handle the request from the class driver */ - - epno = USB_EPNO(ep->eplog); - req->result = -EINPROGRESS; - req->xfrd = 0; - flags = enter_critical_section(); - - /* If we are stalled, then drop all requests on the floor */ - - if (privep->stalled) - { - stm32_abortrequest(privep, privreq, -EBUSY); - uerr("ERROR: stalled\n"); - ret = -EBUSY; - } - - /* Handle IN (device-to-host) requests. NOTE: If the class device is - * using the bi-directional EP0, then we assume that they intend the EP0 - * IN functionality. - */ - - else if (USB_ISEPIN(ep->eplog) || epno == EP0) - { - /* Add the new request to the request queue for the IN endpoint */ - - stm32_rqenqueue(privep, privreq); - usbtrace(TRACE_INREQQUEUED(epno), req->len); - - /* If the IN endpoint FIFO is available, then transfer the data now */ - - if (!privep->txbusy) - { - priv->txstatus = USB_EPR_STATTX_NAK; - if (epno == EP0) - { - ret = stm32_wrrequest_ep0(priv, privep); - } - else - { - ret = stm32_wrrequest(priv, privep); - } - - /* Set the new TX status */ - - stm32_seteptxstatus(epno, priv->txstatus); - } - } - - /* Handle OUT (host-to-device) requests */ - - else - { - /* Add the new request to the request queue for the OUT endpoint */ - - privep->txnullpkt = 0; - stm32_rqenqueue(privep, privreq); - usbtrace(TRACE_OUTREQQUEUED(epno), req->len); - - /* This there a incoming data pending the availability of a - * request? - */ - - if (priv->rxpending) - { - /* Set STAT_RX bits to '11' in the USB_EPnR, enabling further - * transactions. "While the STAT_RX bits are equal to '10' - * (NAK), any OUT request addressed to that endpoint is NAKed, - * indicating a flow control condition: the USB host will retry - * the transaction until it succeeds." - */ - - priv->rxstatus = USB_EPR_STATRX_VALID; - stm32_seteprxstatus(epno, priv->rxstatus); - - /* Data is no longer pending */ - - priv->rxpending = false; - } - } - - leave_critical_section(flags); - return ret; -} - -/**************************************************************************** - * Name: stm32_epcancel - ****************************************************************************/ - -static int stm32_epcancel(struct usbdev_ep_s *ep, - struct usbdev_req_s *req) -{ - struct stm32_ep_s *privep = (struct stm32_ep_s *)ep; - irqstate_t flags; - -#ifdef CONFIG_DEBUG_USB - if (!ep || !req) - { - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); - return -EINVAL; - } -#endif - usbtrace(TRACE_EPCANCEL, USB_EPNO(ep->eplog)); - - flags = enter_critical_section(); - stm32_cancelrequests(privep); - leave_critical_section(flags); - return OK; -} - -/**************************************************************************** - * Name: stm32_epstall - ****************************************************************************/ - -static int stm32_epstall(struct usbdev_ep_s *ep, bool resume) -{ - struct stm32_ep_s *privep; - struct stm32_usbdev_s *priv; - uint8_t epno; - uint16_t status; - irqstate_t flags; - -#ifdef CONFIG_DEBUG_USB - if (!ep) - { - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); - return -EINVAL; - } -#endif - - privep = (struct stm32_ep_s *)ep; - priv = (struct stm32_usbdev_s *)privep->dev; - epno = USB_EPNO(ep->eplog); - - /* STALL or RESUME the endpoint */ - - flags = enter_critical_section(); - usbtrace(resume ? TRACE_EPRESUME : TRACE_EPSTALL, USB_EPNO(ep->eplog)); - - /* Get status of the endpoint; stall the request if the endpoint is - * disabled - */ - - if (USB_ISEPIN(ep->eplog)) - { - status = stm32_geteptxstatus(epno); - } - else - { - status = stm32_geteprxstatus(epno); - } - - if (status == 0) - { - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EPDISABLED), 0); - - if (epno == 0) - { - priv->ep0state = EP0STATE_STALLED; - } - - leave_critical_section(flags); - return -ENODEV; - } - - /* Handle the resume condition */ - - if (resume) - { - /* Resuming a stalled endpoint */ - - usbtrace(TRACE_EPRESUME, epno); - privep->stalled = false; - - if (USB_ISEPIN(ep->eplog)) - { - /* IN endpoint */ - - if (stm32_eptxstalled(epno)) - { - stm32_clrtxdtog(epno); - - /* Restart any queued write requests */ - - priv->txstatus = USB_EPR_STATTX_NAK; - if (epno == EP0) - { - stm32_wrrequest_ep0(priv, privep); - } - else - { - stm32_wrrequest(priv, privep); - } - - /* Set the new TX status */ - - stm32_seteptxstatus(epno, priv->txstatus); - } - } - else - { - /* OUT endpoint */ - - if (stm32_eprxstalled(epno)) - { - if (epno == EP0) - { - /* After clear the STALL, - * enable the default endpoint receiver - */ - - stm32_seteprxcount(epno, ep->maxpacket); - } - else - { - stm32_clrrxdtog(epno); - } - - priv->rxstatus = USB_EPR_STATRX_VALID; - stm32_seteprxstatus(epno, USB_EPR_STATRX_VALID); - } - } - } - - /* Handle the stall condition */ - - else - { - usbtrace(TRACE_EPSTALL, epno); - privep->stalled = true; - - if (USB_ISEPIN(ep->eplog)) - { - /* IN endpoint */ - - priv->txstatus = USB_EPR_STATTX_STALL; - stm32_seteptxstatus(epno, USB_EPR_STATTX_STALL); - } - else - { - /* OUT endpoint */ - - priv->rxstatus = USB_EPR_STATRX_STALL; - stm32_seteprxstatus(epno, USB_EPR_STATRX_STALL); - } - } - - leave_critical_section(flags); - return OK; -} - -/**************************************************************************** - * Device Controller Operations - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_allocep - ****************************************************************************/ - -static struct usbdev_ep_s *stm32_allocep(struct usbdev_s *dev, - uint8_t epno, - bool in, uint8_t eptype) -{ - struct stm32_usbdev_s *priv = (struct stm32_usbdev_s *)dev; - struct stm32_ep_s *privep = NULL; - uint8_t epset = STM32_ENDP_ALLSET; - int bufno; - - usbtrace(TRACE_DEVALLOCEP, (uint16_t)epno); -#ifdef CONFIG_DEBUG_USB - if (!dev) - { - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); - return NULL; - } -#endif - - /* Ignore any direction bits in the logical address */ - - epno = USB_EPNO(epno); - - /* A logical address of 0 means that any endpoint will do */ - - if (epno > 0) - { - /* Otherwise, we will return the endpoint structure only for the - * requested 'logical' endpoint. - * All of the other checks will still be performed. - * - * First, verify that the logical endpoint is in the range supported by - * by the hardware. - */ - - if (epno >= STM32_NENDPOINTS) - { - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADEPNO), (uint16_t)epno); - return NULL; - } - - /* Convert the logical address to a physical OUT endpoint address and - * remove all of the candidate endpoints from the bitset except for the - * the IN/OUT pair for this logical address. - */ - - epset = STM32_ENDP_BIT(epno); - } - - /* Check if the selected endpoint number is available */ - - privep = stm32_epreserve(priv, epset); - if (!privep) - { - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EPRESERVE), (uint16_t)epset); - goto errout; - } - - /* Allocate a PMA buffer for this endpoint */ - -#warning "REVISIT: Should configure BULK EPs using double buffer feature" - bufno = stm32_epallocpma(priv); - if (bufno < 0) - { - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EPBUFFER), 0); - goto errout_with_ep; - } - - privep->bufno = (uint8_t)bufno; - return &privep->ep; - -errout_with_ep: - stm32_epunreserve(priv, privep); -errout: - return NULL; -} - -/**************************************************************************** - * Name: stm32_freeep - ****************************************************************************/ - -static void stm32_freeep(struct usbdev_s *dev, struct usbdev_ep_s *ep) -{ - struct stm32_usbdev_s *priv; - struct stm32_ep_s *privep; - -#ifdef CONFIG_DEBUG_USB - if (!dev || !ep) - { - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); - return; - } -#endif - priv = (struct stm32_usbdev_s *)dev; - privep = (struct stm32_ep_s *)ep; - usbtrace(TRACE_DEVFREEEP, (uint16_t)USB_EPNO(ep->eplog)); - - if (priv && privep) - { - /* Free the PMA buffer assigned to this endpoint */ - - stm32_epfreepma(priv, privep); - - /* Mark the endpoint as available */ - - stm32_epunreserve(priv, privep); - } -} - -/**************************************************************************** - * Name: stm32_getframe - ****************************************************************************/ - -static int stm32_getframe(struct usbdev_s *dev) -{ - uint16_t fnr; - -#ifdef CONFIG_DEBUG_USB - if (!dev) - { - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); - return -EINVAL; - } -#endif - - /* Return the last frame number detected by the hardware */ - - fnr = stm32_getreg(STM32_USB_FNR); - usbtrace(TRACE_DEVGETFRAME, fnr); - return (fnr & USB_FNR_FN_MASK); -} - -/**************************************************************************** - * Name: stm32_wakeup - ****************************************************************************/ - -static int stm32_wakeup(struct usbdev_s *dev) -{ - struct stm32_usbdev_s *priv = (struct stm32_usbdev_s *)dev; - irqstate_t flags; - - usbtrace(TRACE_DEVWAKEUP, 0); -#ifdef CONFIG_DEBUG_USB - if (!dev) - { - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); - return -EINVAL; - } -#endif - - /* Start the resume sequence. The actual resume steps will be driven - * by the ESOF interrupt. - */ - - flags = enter_critical_section(); - stm32_initresume(priv); - priv->rsmstate = RSMSTATE_STARTED; - - /* Disable the SUSP interrupt (until we are fully resumed), disable - * the WKUP interrupt (we are already waking up), and enable the - * ESOF interrupt that will drive the resume operations. Clear any - * pending ESOF interrupt. - */ - - stm32_setimask(priv, USB_CNTR_ESOFM, USB_CNTR_WKUPM | USB_CNTR_SUSPM); - stm32_putreg(~USB_ISTR_ESOF, STM32_USB_ISTR); - leave_critical_section(flags); - return OK; -} - -/**************************************************************************** - * Name: stm32_selfpowered - ****************************************************************************/ - -static int stm32_selfpowered(struct usbdev_s *dev, bool selfpowered) -{ - struct stm32_usbdev_s *priv = (struct stm32_usbdev_s *)dev; - - usbtrace(TRACE_DEVSELFPOWERED, (uint16_t)selfpowered); - -#ifdef CONFIG_DEBUG_USB - if (!dev) - { - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); - return -ENODEV; - } -#endif - - priv->selfpowered = selfpowered; - return OK; -} - -/**************************************************************************** - * Initialization/Reset - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_reset - ****************************************************************************/ - -static void stm32_reset(struct stm32_usbdev_s *priv) -{ - int epno; - - /* Put the USB controller in reset, disable all interrupts */ - - stm32_putreg(USB_CNTR_FRES, STM32_USB_CNTR); - - /* Tell the class driver that we are disconnected. The class driver - * should then accept any new configurations. - */ - - CLASS_DISCONNECT(priv->driver, &priv->usbdev); - - /* Reset the device state structure */ - - priv->ep0state = EP0STATE_IDLE; - priv->rsmstate = RSMSTATE_IDLE; - priv->rxpending = false; - - /* Reset endpoints */ - - for (epno = 0; epno < STM32_NENDPOINTS; epno++) - { - struct stm32_ep_s *privep = &priv->eplist[epno]; - - /* Cancel any queued requests. Since they are canceled - * with status -ESHUTDOWN, then will not be requeued - * until the configuration is reset. NOTE: This should - * not be necessary... the CLASS_DISCONNECT above should - * result in the class implementation calling stm32_epdisable - * for each of its configured endpoints. - */ - - stm32_cancelrequests(privep); - - /* Reset endpoint status */ - - privep->stalled = false; - privep->halted = false; - privep->txbusy = false; - privep->txnullpkt = false; - } - - /* Re-configure the USB controller in its initial, unconnected state */ - - stm32_hwreset(priv); - priv->usbdev.speed = USB_SPEED_FULL; -} - -/**************************************************************************** - * Name: stm32_hwreset - ****************************************************************************/ - -static void stm32_hwreset(struct stm32_usbdev_s *priv) -{ - /* Put the USB controller into reset, clear all interrupt enables */ - - stm32_putreg(USB_CNTR_FRES, STM32_USB_CNTR); - - /* Disable interrupts (and perhaps take the USB controller out of reset) */ - - priv->imask = 0; - stm32_putreg(priv->imask, STM32_USB_CNTR); - - /* Set the STM32 BTABLE address */ - - stm32_putreg(STM32_BTABLE_ADDRESS & 0xfff8, STM32_USB_BTABLE); - - /* Initialize EP0 */ - - stm32_seteptype(EP0, USB_EPR_EPTYPE_CONTROL); - stm32_seteptxstatus(EP0, USB_EPR_STATTX_NAK); - stm32_seteprxaddr(EP0, STM32_EP0_RXADDR); - stm32_seteprxcount(EP0, STM32_EP0MAXPACKET); - stm32_seteptxaddr(EP0, STM32_EP0_TXADDR); - stm32_clrstatusout(EP0); - stm32_seteprxstatus(EP0, USB_EPR_STATRX_VALID); - - /* Set the device to respond on default address */ - - stm32_setdevaddr(priv, 0); - - /* Clear any pending interrupts */ - - stm32_putreg(0, STM32_USB_ISTR); - - /* Enable interrupts at the USB controller */ - - stm32_setimask(priv, STM32_CNTR_SETUP, - (USB_CNTR_ALLINTS & ~STM32_CNTR_SETUP)); - stm32_dumpep(EP0); -} - -/**************************************************************************** - * Name: stm32_hwsetup - ****************************************************************************/ - -static void stm32_hwsetup(struct stm32_usbdev_s *priv) -{ - int epno; - - /* Power the USB controller, put the USB controller into reset, disable - * all USB interrupts - */ - - stm32_putreg(USB_CNTR_FRES | USB_CNTR_PDWN, STM32_USB_CNTR); - - /* Disconnect the device / disable the pull-up. We don't want the - * host to enumerate us until the class driver is registered. - */ - - stm32_usbpullup(&priv->usbdev, false); - - /* Initialize the device state structure. NOTE: many fields - * have the initial value of zero and, hence, are not explicitly - * initialized here. - */ - - memset(priv, 0, sizeof(struct stm32_usbdev_s)); - priv->usbdev.ops = &g_devops; - priv->usbdev.ep0 = &priv->eplist[EP0].ep; - priv->epavail = STM32_ENDP_ALLSET & ~STM32_ENDP_BIT(EP0); - priv->bufavail = STM32_BUFFER_ALLSET & ~STM32_BUFFER_EP0; - - /* Initialize the endpoint list */ - - for (epno = 0; epno < STM32_NENDPOINTS; epno++) - { - /* Set endpoint operations, reference to driver structure (not - * really necessary because there is only one controller), and - * the (physical) endpoint number which is just the index to the - * endpoint. - */ - - priv->eplist[epno].ep.ops = &g_epops; - priv->eplist[epno].dev = priv; - priv->eplist[epno].ep.eplog = epno; - - /* We will use a fixed maxpacket size for all endpoints (perhaps - * ISOC endpoints could have larger maxpacket???). A smaller - * packet size can be selected when the endpoint is configured. - */ - - priv->eplist[epno].ep.maxpacket = STM32_MAXPACKET_SIZE; - } - - /* Select a smaller endpoint size for EP0 */ - -#if STM32_EP0MAXPACKET < STM32_MAXPACKET_SIZE - priv->eplist[EP0].ep.maxpacket = STM32_EP0MAXPACKET; -#endif - - /* Configure the USB controller. USB uses the following GPIO pins: - * - * PA9 - VBUS - * PA10 - ID - * PA11 - DM - * PA12 - DP - * - * "As soon as the USB is enabled, these pins [DM and DP] are connected to - * the USB internal transceiver automatically." - */ - - /* Power up the USB controller, holding it in reset. There is a delay of - * about 1uS after applying power before the USB will behave predictably. - * A 5MS delay is more than enough. NOTE that we leave the USB controller - * in the reset state; the hardware will not be initialized until the - * class driver has been bound. - */ - - stm32_putreg(USB_CNTR_FRES, STM32_USB_CNTR); - up_mdelay(5); -} - -/**************************************************************************** - * Name: stm32_hwshutdown - ****************************************************************************/ - -static void stm32_hwshutdown(struct stm32_usbdev_s *priv) -{ - priv->usbdev.speed = USB_SPEED_UNKNOWN; - - /* Disable all interrupts and force the USB controller into reset */ - - stm32_putreg(USB_CNTR_FRES, STM32_USB_CNTR); - - /* Clear any pending interrupts */ - - stm32_putreg(0, STM32_USB_ISTR); - - /* Disconnect the device / disable the pull-up */ - - stm32_usbpullup(&priv->usbdev, false); - - /* Power down the USB controller */ - - stm32_putreg(USB_CNTR_FRES | USB_CNTR_PDWN, STM32_USB_CNTR); -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: arm_usbinitialize - * Description: - * Initialize the USB driver - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -void arm_usbinitialize(void) -{ - /* For now there is only one USB controller, but we will always refer to - * it using a pointer to make any future ports to multiple USB controllers - * easier. - */ - - struct stm32_usbdev_s *priv = &g_usbdev; - uint32_t regval; - - usbtrace(TRACE_DEVINIT, 0); - - /* Configure USB GPIO alternate function pins */ - - stm32_configgpio(GPIO_USB_DM); - stm32_configgpio(GPIO_USB_DP); - - /* Enable clocking to the USB peripheral */ - - regval = getreg32(STM32_RCC_APB1RSTR); - regval &= ~RCC_APB1ENR_USBEN; - putreg32(regval, STM32_RCC_APB1RSTR); - - /* Power up the USB controller, but leave it in the reset state */ - - stm32_hwsetup(priv); - - /* Attach USB controller interrupt handlers. The hardware will not be - * initialized and interrupts will not be enabled until the class device - * driver is bound. Getting the IRQs here only makes sure that we have - * them when we need them later. - */ - - if (irq_attach(STM32_IRQ_USB, stm32_usb_interrupt, priv) != 0) - { - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_IRQREGISTRATION), - (uint16_t)STM32_IRQ_USB); - goto errout; - } - - return; - -errout: - arm_usbuninitialize(); -} - -/**************************************************************************** - * Name: arm_usbuninitialize - * Description: - * Initialize the USB driver - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -void arm_usbuninitialize(void) -{ - /* For now there is only one USB controller, but we will always refer to - * it using a pointer to make any future ports to multiple USB controllers - * easier. - */ - - struct stm32_usbdev_s *priv = &g_usbdev; - irqstate_t flags; - - flags = enter_critical_section(); - usbtrace(TRACE_DEVUNINIT, 0); - - /* Disable and detach the USB IRQs */ - - up_disable_irq(STM32_IRQ_USB); - irq_detach(STM32_IRQ_USB); - - if (priv->driver) - { - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_DRIVERREGISTERED), 0); - usbdev_unregister(priv->driver); - } - - /* Put the hardware in an inactive state */ - - stm32_hwshutdown(priv); - leave_critical_section(flags); -} - -/**************************************************************************** - * Name: usbdev_register - * - * Description: - * Register a USB device class driver. The class driver's bind() method - * will be called to bind it to a USB device driver. - * - ****************************************************************************/ - -int usbdev_register(struct usbdevclass_driver_s *driver) -{ - /* For now there is only one USB controller, but we will always refer to - * it using a pointer to make any future ports to multiple USB controllers - * easier. - */ - - struct stm32_usbdev_s *priv = &g_usbdev; - int ret; - - usbtrace(TRACE_DEVREGISTER, 0); - -#ifdef CONFIG_DEBUG_USB - if (!driver || !driver->ops->bind || !driver->ops->unbind || - !driver->ops->disconnect || !driver->ops->setup) - { - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); - return -EINVAL; - } - - if (priv->driver) - { - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_DRIVER), 0); - return -EBUSY; - } -#endif - - /* First hook up the driver */ - - priv->driver = driver; - - /* Then bind the class driver */ - - ret = CLASS_BIND(driver, &priv->usbdev); - if (ret) - { - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BINDFAILED), - (uint16_t) - ret); - } - else - { - /* Setup the USB controller -- enabling interrupts at the USB - * controller - */ - - stm32_hwreset(priv); - - /* Enable USB controller interrupts at the NVIC */ - - up_enable_irq(STM32_IRQ_USB); - - /* Enable pull-up to connect the device. The host should enumerate - * us some time after this - */ - - stm32_usbpullup(&priv->usbdev, true); - priv->usbdev.speed = USB_SPEED_FULL; - } - - return ret; -} - -/**************************************************************************** - * Name: usbdev_unregister - * - * Description: - * Un-register usbdev class driver. If the USB device is connected to a - * USB host, it will first disconnect(). The driver is also requested to - * unbind() and clean up any device state, before this procedure finally - * returns. - * - ****************************************************************************/ - -int usbdev_unregister(struct usbdevclass_driver_s *driver) -{ - /* For now there is only one USB controller, but we will always refer to - * it using a pointer to make any future ports to multiple USB controllers - * easier. - */ - - struct stm32_usbdev_s *priv = &g_usbdev; - irqstate_t flags; - - usbtrace(TRACE_DEVUNREGISTER, 0); - -#ifdef CONFIG_DEBUG_USB - if (driver != priv->driver) - { - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); - return -EINVAL; - } -#endif - - /* Reset the hardware and cancel all requests. All requests must be - * canceled while the class driver is still bound. - */ - - flags = enter_critical_section(); - stm32_reset(priv); - - /* Unbind the class driver */ - - CLASS_UNBIND(driver, &priv->usbdev); - - /* Disable USB controller interrupts (but keep them attached) */ - - up_disable_irq(STM32_IRQ_USB); - - /* Put the hardware in an inactive state. Then bring the hardware back up - * in the reset state (this is probably not necessary, the stm32_reset() - * call above was probably sufficient). - */ - - stm32_hwshutdown(priv); - stm32_hwsetup(priv); - - /* Unhook the driver */ - - priv->driver = NULL; - leave_critical_section(flags); - return OK; -} - -#endif /* CONFIG_USBDEV && CONFIG_STM32F0L0G0_USB */ diff --git a/arch/arm/src/stm32f0l0g0/stm32_usbdev.h b/arch/arm/src/stm32f0l0g0/stm32_usbdev.h deleted file mode 100644 index afa99490451f9..0000000000000 --- a/arch/arm/src/stm32f0l0g0/stm32_usbdev.h +++ /dev/null @@ -1,84 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_usbdev.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_STM32_USBDEV_H -#define __ARCH_ARM_SRC_STM32F0L0G0_STM32_USBDEV_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include -#include - -#include "chip.h" -#include "hardware/stm32_usbdev.h" - -/**************************************************************************** - * Public Functions Prototypes - ****************************************************************************/ - -#ifndef __ASSEMBLY__ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Name: stm32_usbpullup - * - * Description: - * If USB is supported and the board supports a pullup via GPIO - * (for USB software connect and disconnect), then the board software must - * provide stm32_pullup. - * See include/nuttx/usb/usbdev.h for additional description of this method. - * - ****************************************************************************/ - -int stm32_usbpullup(struct usbdev_s *dev, bool enable); - -/**************************************************************************** - * Name: stm32_usbsuspend - * - * Description: - * Board logic must provide the stm32_usbsuspend logic if the USBDEV driver - * is used. This function is called whenever the USB enters or leaves - * suspend mode. This is an opportunity for the board logic to shutdown - * clocks, power, etc. while the USB is suspended. - * - ****************************************************************************/ - -void stm32_usbsuspend(struct usbdev_s *dev, bool resume); - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_STM32_USBDEV_H */ diff --git a/arch/arm/src/stm32f0l0g0/stm32_wdg.h b/arch/arm/src/stm32f0l0g0/stm32_wdg.h deleted file mode 100644 index 1d688da6b3898..0000000000000 --- a/arch/arm/src/stm32f0l0g0/stm32_wdg.h +++ /dev/null @@ -1,104 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_wdg.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_STM32_WDG_H -#define __ARCH_ARM_SRC_STM32F0L0G0_STM32_WDG_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "chip.h" -#include "hardware/stm32_wdg.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#ifndef __ASSEMBLY__ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_iwdginitialize - * - * Description: - * Initialize the IWDG watchdog time. The watchdog timer is initialized - * and registers as 'devpath. The initial state of the watchdog time is - * disabled. - * - * Input Parameters: - * devpath - The full path to the watchdog. This should be of the form - * /dev/watchdog0 - * lsifreq - The calibrated LSI clock frequency - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef CONFIG_STM32F0L0G0_IWDG -void stm32_iwdginitialize(const char *devpath, uint32_t lsifreq); -#endif - -/**************************************************************************** - * Name: stm32_wwdginitialize - * - * Description: - * Initialize the WWDG watchdog time. The watchdog timer is initializeed - * and registers as 'devpath. The initial state of the watchdog time is - * disabled. - * - * Input Parameters: - * devpath - The full path to the watchdog. This should be of the form - * /dev/watchdog0 - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef CONFIG_STM32F0L0G0_WWDG -void stm32_wwdginitialize(const char *devpath); -#endif - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ - -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_STM32_WDG_H */ diff --git a/arch/arm/src/stm32f0l0g0/stm32_wwdg.c b/arch/arm/src/stm32f0l0g0/stm32_wwdg.c deleted file mode 100644 index f8717ce0f2c33..0000000000000 --- a/arch/arm/src/stm32f0l0g0/stm32_wwdg.c +++ /dev/null @@ -1,684 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_wwdg.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include - -#include -#include -#include - -#include -#include -#include -#include - -#include "arm_internal.h" -#include "hardware/stm32_dbgmcu.h" -#include "stm32_wdg.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Clocking *****************************************************************/ - -/* The minimum frequency of the WWDG clock is: - * - * Fmin = PCLK1 / 4096 / 8 - * - * So the maximum delay (in milliseconds) is then: - * - * 1000 * (WWDG_CR_T_MAX+1) / Fmin - * - * For example, if PCLK1 = 42MHz, then the maximum delay is: - * - * Fmin = 1281.74 - * 1000 * 64 / Fmin = 49.93 msec - */ - -#define WWDG_FMIN (STM32_PCLK1_FREQUENCY / 4096 / 8) -#define WWDG_MAXTIMEOUT (1000 * (WWDG_CR_T_MAX+1) / WWDG_FMIN) - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/* This structure provides the private representation of the "lower-half" - * driver state structure. This structure must be cast-compatible with the - * well-known watchdog_lowerhalf_s structure. - */ - -struct stm32_lowerhalf_s -{ - const struct watchdog_ops_s *ops; /* Lower half operations */ - xcpt_t handler; /* Current EWI interrupt handler */ - uint32_t timeout; /* The actual timeout value */ - uint32_t fwwdg; /* WWDG clock frequency */ - bool started; /* The timer has been started */ - uint8_t reload; /* The 7-bit reload field reset value */ - uint8_t window; /* The 7-bit window (W) field value */ -}; - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -/* Register operations ******************************************************/ - -static void stm32_setwindow(struct stm32_lowerhalf_s *priv, uint8_t window); - -/* Interrupt handling *******************************************************/ - -static int stm32_interrupt(int irq, void *context, void *arg); - -/* "Lower half" driver methods **********************************************/ - -static int stm32_start(struct watchdog_lowerhalf_s *lower); -static int stm32_stop(struct watchdog_lowerhalf_s *lower); -static int stm32_keepalive(struct watchdog_lowerhalf_s *lower); -static int stm32_getstatus(struct watchdog_lowerhalf_s *lower, - struct watchdog_status_s *status); -static int stm32_settimeout(struct watchdog_lowerhalf_s *lower, - uint32_t timeout); -static xcpt_t stm32_capture(struct watchdog_lowerhalf_s *lower, - xcpt_t handler); -static int stm32_ioctl(struct watchdog_lowerhalf_s *lower, int cmd, - unsigned long arg); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* "Lower half" driver methods */ - -static const struct watchdog_ops_s g_wdgops = -{ - .start = stm32_start, - .stop = stm32_stop, - .keepalive = stm32_keepalive, - .getstatus = stm32_getstatus, - .settimeout = stm32_settimeout, - .capture = stm32_capture, - .ioctl = stm32_ioctl, -}; - -/* "Lower half" driver state */ - -static struct stm32_lowerhalf_s g_wdgdev; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_setwindow - * - * Description: - * Set the CFR window value. The window value is compared to the down- - * counter when the counter is updated. The WWDG counter should be updated - * only when the counter is below this window value (and greater than 64) - * otherwise a reset will be generated - * - ****************************************************************************/ - -static void stm32_setwindow(struct stm32_lowerhalf_s *priv, uint8_t window) -{ - uint16_t regval; - - /* Set W[6:0] bits according to selected window value */ - - regval = getreg32(STM32_WWDG_CFR); - regval &= ~WWDG_CFR_W_MASK; - regval |= window << WWDG_CFR_W_SHIFT; - putreg32(regval, STM32_WWDG_CFR); - - /* Remember the window setting */ - - priv->window = window; -} - -/**************************************************************************** - * Name: stm32_interrupt - * - * Description: - * WWDG early warning interrupt - * - * Input Parameters: - * Usual interrupt handler arguments. - * - * Returned Value: - * Always returns OK. - * - ****************************************************************************/ - -static int stm32_interrupt(int irq, void *context, void *arg) -{ - struct stm32_lowerhalf_s *priv = &g_wdgdev; - uint16_t regval; - - /* Check if the EWI interrupt is really pending */ - - regval = getreg32(STM32_WWDG_SR); - if ((regval & WWDG_SR_EWIF) != 0) - { - /* Is there a registered handler? */ - - if (priv->handler) - { - /* Yes... NOTE: This interrupt service routine (ISR) must reload - * the WWDG counter to prevent the reset. Otherwise, we will reset - * upon return. - */ - - priv->handler(irq, context, arg); - } - - /* The EWI interrupt is cleared by writing '0' to the EWIF bit in the - * WWDG_SR register. - */ - - regval &= ~WWDG_SR_EWIF; - putreg32(regval, STM32_WWDG_SR); - } - - return OK; -} - -/**************************************************************************** - * Name: stm32_start - * - * Description: - * Start the watchdog timer, resetting the time to the current timeout, - * - * Input Parameters: - * lower - A pointer the publicly visible representation of the "lower- - * half" driver state structure. - * - * Returned Value: - * Zero on success; a negated errno value on failure. - * - ****************************************************************************/ - -static int stm32_start(struct watchdog_lowerhalf_s *lower) -{ - struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; - - wdinfo("Entry\n"); - DEBUGASSERT(priv); - - /* The watchdog is always disabled after a reset. It is enabled by setting - * the WDGA bit in the WWDG_CR register, then it cannot be disabled again - * except by a reset. - */ - - putreg32(WWDG_CR_WDGA | WWDG_CR_T_RESET | priv->reload, STM32_WWDG_CR); - priv->started = true; - return OK; -} - -/**************************************************************************** - * Name: stm32_stop - * - * Description: - * Stop the watchdog timer - * - * Input Parameters: - * lower - A pointer the publicly visible representation of the "lower- - * half" driver state structure. - * - * Returned Value: - * Zero on success; a negated errno value on failure. - * - ****************************************************************************/ - -static int stm32_stop(struct watchdog_lowerhalf_s *lower) -{ - /* The watchdog is always disabled after a reset. It is enabled by setting - * the WDGA bit in the WWDG_CR register, then it cannot be disabled again - * except by a reset. - */ - - wdinfo("Entry\n"); - return -ENOSYS; -} - -/**************************************************************************** - * Name: stm32_keepalive - * - * Description: - * Reset the watchdog timer to the current timeout value, prevent any - * imminent watchdog timeouts. This is sometimes referred as "pinging" - * the watchdog timer or "petting the dog". - * - * The application program must write in the WWDG_CR register at regular - * intervals during normal operation to prevent an MCU reset. This - * operation must occur only when the counter value is lower than the - * window register value. The value to be stored in the WWDG_CR register - * must be between 0xff and 0xC0: - * - * Input Parameters: - * lower - A pointer the publicly visible representation of the "lower- - * half" driver state structure. - * - * Returned Value: - * Zero on success; a negated errno value on failure. - * - ****************************************************************************/ - -static int stm32_keepalive(struct watchdog_lowerhalf_s *lower) -{ - struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; - - wdinfo("Entry\n"); - DEBUGASSERT(priv); - - /* Write to T[6:0] bits to configure the counter value, no need to do - * a read-modify-write; writing a 0 to WDGA bit does nothing. - */ - - putreg32((WWDG_CR_T_RESET | priv->reload), STM32_WWDG_CR); - return OK; -} - -/**************************************************************************** - * Name: stm32_getstatus - * - * Description: - * Get the current watchdog timer status - * - * Input Parameters: - * lower - A pointer the publicly visible representation of the "lower- - * half" driver state structure. - * status - The location to return the watchdog status information. - * - * Returned Value: - * Zero on success; a negated errno value on failure. - * - ****************************************************************************/ - -static int stm32_getstatus(struct watchdog_lowerhalf_s *lower, - struct watchdog_status_s *status) -{ - struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; - uint32_t elapsed; - uint16_t reload; - - wdinfo("Entry\n"); - DEBUGASSERT(priv); - - /* Return the status bit */ - - status->flags = WDFLAGS_RESET; - if (priv->started) - { - status->flags |= WDFLAGS_ACTIVE; - } - - if (priv->handler) - { - status->flags |= WDFLAGS_CAPTURE; - } - - /* Return the actual timeout is milliseconds */ - - status->timeout = priv->timeout; - - /* Get the time remaining until the watchdog expires (in milliseconds) */ - - reload = (getreg32(STM32_WWDG_CR) >> WWDG_CR_T_SHIFT) & 0x7f; - elapsed = priv->reload - reload; - status->timeleft = (priv->timeout * elapsed) / (priv->reload + 1); - - wdinfo("Status :\n"); - wdinfo(" flags : %08x\n", (unsigned)status->flags); - wdinfo(" timeout : %u\n", (unsigned)status->timeout); - wdinfo(" timeleft : %u\n", (unsigned)status->flags); - return OK; -} - -/**************************************************************************** - * Name: stm32_settimeout - * - * Description: - * Set a new timeout value (and reset the watchdog timer) - * - * Input Parameters: - * lower - A pointer the publicly visible representation of the - * "lower-half" driver state structure. - * timeout - The new timeout value in milliseconds. - * - * Returned Value: - * Zero on success; a negated errno value on failure. - * - ****************************************************************************/ - -static int stm32_settimeout(struct watchdog_lowerhalf_s *lower, - uint32_t timeout) -{ - struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; - uint32_t fwwdg; - uint32_t reload; - uint16_t regval; - int wdgtb; - - DEBUGASSERT(priv); - wdinfo("Entry: timeout=%u\n", (unsigned)timeout); - - /* Can this timeout be represented? */ - - if (timeout < 1 || timeout > WWDG_MAXTIMEOUT) - { - wderr("ERROR: Cannot represent timeout=%u > %lu\n", - (unsigned)timeout, WWDG_MAXTIMEOUT); - return -ERANGE; - } - - /* Determine prescaler value. - * - * Fwwdg = PCLK1/4096/prescaler. - * - * Where - * Fwwwdg is the frequency of the WWDG clock - * wdgtb is one of {1, 2, 4, or 8} - */ - - /* Select the smallest prescaler that will result in a reload field value - * that is less than the maximum. - */ - - for (wdgtb = 0; ; wdgtb++) - { - /* WDGTB = 0 -> Divider = 1 = 1 << 0 - * WDGTB = 1 -> Divider = 2 = 1 << 1 - * WDGTB = 2 -> Divider = 4 = 1 << 2 - * WDGTB = 3 -> Divider = 8 = 1 << 3 - */ - - /* Get the WWDG counter frequency in Hz. */ - - fwwdg = (STM32_PCLK1_FREQUENCY / 4096) >> wdgtb; - - /* The formula to calculate the timeout value is given by: - * - * timeout = 1000 * (reload + 1) / Fwwdg, OR - * reload = timeout * Fwwdg / 1000 - 1 - * - * Where - * timeout is the desired timeout in milliseconds - * reload is the contents of T{5:0] - * Fwwdg is the frequency of the WWDG clock - */ - - reload = timeout * fwwdg / 1000 - 1; - - /* If this reload valid is less than the maximum or we are not ready - * at the prescaler value, then break out of the loop to use these - * settings. - */ - -#if 0 - wdinfo("wdgtb=%d fwwdg=%d reload=%d timeout=%d\n", - wdgtb, fwwdg, reload, 1000 * (reload + 1) / fwwdg); -#endif - if (reload <= WWDG_CR_T_MAX || wdgtb == 3) - { - /* Note that we explicitly break out of the loop rather than using - * the 'for' loop termination logic because we do not want the - * value of wdgtb to be incremented. - */ - - break; - } - } - - /* Make sure that the final reload value is within range */ - - if (reload > WWDG_CR_T_MAX) - { - reload = WWDG_CR_T_MAX; - } - - /* Calculate and save the actual timeout value in milliseconds: - * - * timeout = 1000 * (reload + 1) / Fwwdg - */ - - priv->timeout = 1000 * (reload + 1) / fwwdg; - - /* Remember the selected values */ - - priv->fwwdg = fwwdg; - priv->reload = reload; - - wdinfo("wdgtb=%d fwwdg=%u reload=%u timeout=%u\n", - wdgtb, (unsigned)fwwdg, (unsigned)reload, (unsigned)priv->timeout); - - /* Set WDGTB[1:0] bits according to calculated value */ - - regval = getreg32(STM32_WWDG_CFR); - regval &= ~WWDG_CFR_WDGTB_MASK; - regval |= (uint16_t)wdgtb << WWDG_CFR_WDGTB_SHIFT; - putreg32(regval, STM32_WWDG_CFR); - - /* Reset the 7-bit window value to the maximum value.. essentially - * disabling the lower limit of the watchdog reset time. - */ - - stm32_setwindow(priv, 0x7f); - return OK; -} - -/**************************************************************************** - * Name: stm32_capture - * - * Description: - * Don't reset on watchdog timer timeout; instead, call this user provider - * timeout handler. NOTE: Providing handler==NULL will restore the reset - * behavior. - * - * Input Parameters: - * lower - A pointer the publicly visible representation of the - * "lower-half" driver state structure. - * newhandler - The new watchdog expiration function pointer. If this - * function pointer is NULL, then the reset-on-expiration - * behavior is restored, - * - * Returned Value: - * The previous watchdog expiration function pointer or NULL is there was - * no previous function pointer, i.e., if the previous behavior was - * reset-on-expiration (NULL is also returned if an error occurs). - * - ****************************************************************************/ - -static xcpt_t stm32_capture(struct watchdog_lowerhalf_s *lower, - xcpt_t handler) -{ - struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; - irqstate_t flags; - xcpt_t oldhandler; - uint16_t regval; - - DEBUGASSERT(priv); - wdinfo("Entry: handler=%p\n", handler); - - /* Get the old handler return value */ - - flags = enter_critical_section(); - oldhandler = priv->handler; - - /* Save the new handler */ - - priv->handler = handler; - - /* Are we attaching or detaching the handler? */ - - regval = getreg32(STM32_WWDG_CFR); - if (handler) - { - /* Attaching... Enable the EWI interrupt */ - - regval |= WWDG_CFR_EWI; - putreg32(regval, STM32_WWDG_CFR); - - up_enable_irq(STM32_IRQ_WWDG); - } - else - { - /* Detaching... Disable the EWI interrupt */ - - regval &= ~WWDG_CFR_EWI; - putreg32(regval, STM32_WWDG_CFR); - - up_disable_irq(STM32_IRQ_WWDG); - } - - leave_critical_section(flags); - return oldhandler; -} - -/**************************************************************************** - * Name: stm32_ioctl - * - * Description: - * Any ioctl commands that are not recognized by the "upper-half" driver - * are forwarded to the lower half driver through this method. - * - * Input Parameters: - * lower - A pointer the publicly visible representation of the "lower- - * half" driver state structure. - * cmd - The ioctl command value - * arg - The optional argument that accompanies the 'cmd'. The - * interpretation of this argument depends on the particular - * command. - * - * Returned Value: - * Zero on success; a negated errno value on failure. - * - ****************************************************************************/ - -static int stm32_ioctl(struct watchdog_lowerhalf_s *lower, int cmd, - unsigned long arg) -{ - struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; - int ret = -ENOTTY; - - DEBUGASSERT(priv); - wdinfo("Entry: cmd=%d arg=%ld\n", cmd, arg); - - /* WDIOC_MINTIME: Set the minimum ping time. If two keepalive ioctls - * are received within this time, a reset event will be generated. - * Argument: A 32-bit time value in milliseconds. - */ - - if (cmd == WDIOC_MINTIME) - { - uint32_t mintime = (uint32_t)arg; - - /* The minimum time should be strictly less than the total delay - * which, in turn, will be less than or equal to WWDG_CR_T_MAX - */ - - ret = -EINVAL; - if (mintime < priv->timeout) - { - uint32_t window = (priv->timeout - mintime) * priv->fwwdg / - 1000 - 1; - DEBUGASSERT(window < priv->reload); - stm32_setwindow(priv, window | WWDG_CR_T_RESET); - ret = OK; - } - } - - return ret; -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_wwdginitialize - * - * Description: - * Initialize the WWDG watchdog timer. The watchdog timer is initialized - * and registers as 'devpath'. The initial state of the watchdog timer is - * disabled. - * - * Input Parameters: - * devpath - The full path to the watchdog. This should be of the form - * /dev/watchdog0 - * - * Returned Value: - * None - * - ****************************************************************************/ - -void stm32_wwdginitialize(const char *devpath) -{ - struct stm32_lowerhalf_s *priv = &g_wdgdev; - - wdinfo("Entry: devpath=%s\n", devpath); - - /* NOTE we assume that clocking to the WWDG has already been provided by - * the RCC initialization logic. - */ - - /* Initialize the driver state structure. Here we assume: (1) the state - * structure lies in .bss and was zeroed at reset time. (2) This function - * is only called once so it is never necessary to re-zero the structure. - */ - - priv->ops = &g_wdgops; - - /* Attach our EWI interrupt handler (But don't enable it yet) */ - - irq_attach(STM32_IRQ_WWDG, stm32_interrupt, NULL); - - /* Select an arbitrary initial timeout value. But don't start the watchdog - * yet. NOTE: If the "Hardware watchdog" feature is enabled through the - * device option bits, the watchdog is automatically enabled at power-on. - */ - - stm32_settimeout((struct watchdog_lowerhalf_s *)priv, WWDG_MAXTIMEOUT); - - /* Register the watchdog driver as /dev/watchdog0 */ - - watchdog_register(devpath, (struct watchdog_lowerhalf_s *)priv); - - /* When the microcontroller enters debug mode (Cortex-M core halted), - * the WWDG counter either continues to work normally or stops, depending - * on DBG_WWDG_STOP configuration bit in DBG module. - */ - -#ifdef CONFIG_DEBUG_FEATURES - { - uint32_t cr = getreg32(STM32_DBGMCU_APB1_FZ); - cr |= DBGMCU_APB1_WWDGSTOP; - putreg32(cr, STM32_DBGMCU_APB1_FZ); - } -#endif -} diff --git a/arch/arm/src/stm32f0l0g0/stm32f0l0_pwr.c b/arch/arm/src/stm32f0l0g0/stm32f0l0_pwr.c deleted file mode 100644 index ab65b569e9674..0000000000000 --- a/arch/arm/src/stm32f0l0g0/stm32f0l0_pwr.c +++ /dev/null @@ -1,396 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32f0l0_pwr.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include - -#include -#include - -#include "arm_internal.h" -#include "stm32_pwr.h" - -#if defined(CONFIG_STM32F0L0G0_PWR) - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* Parts only support a single Wake-up pin do not include the numeric suffix - * in the naming. - */ - -#ifndef PWR_CSR_EWUP1 -# define PWR_CSR_EWUP1 PWR_CSR_EWUP -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -static uint16_t g_bkp_writable_counter = 0; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -static inline uint32_t stm32_pwr_getreg32(uint8_t offset) -{ - return getreg32(STM32_PWR_BASE + (uint32_t)offset); -} - -static inline void stm32_pwr_putreg32(uint8_t offset, uint32_t value) -{ - putreg32(value, STM32_PWR_BASE + (uint32_t)offset); -} - -static inline void stm32_pwr_modifyreg32(uint8_t offset, uint32_t clearbits, - uint32_t setbits) -{ - modifyreg32(STM32_PWR_BASE + (uint32_t)offset, clearbits, setbits); -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_pwr_initbkp - * - * Description: - * Insures the referenced count access to the backup domain (RTC registers, - * RTC backup data registers and backup SRAM is consistent with the HW - * state without relying on a variable. - * - * NOTE: This function should only be called by SoC Start up code. - * - * Input Parameters: - * writable - True: enable ability to write to backup domain registers - * - * Returned Value: - * None - * - ****************************************************************************/ - -void stm32_pwr_initbkp(bool writable) -{ - uint16_t regval; - - /* Make the HW not writable */ - - regval = stm32_pwr_getreg32(STM32_PWR_CR_OFFSET); - regval &= ~PWR_CR_DBP; - stm32_pwr_putreg32(STM32_PWR_CR_OFFSET, regval); - - /* Make the reference count agree */ - - g_bkp_writable_counter = 0; - stm32_pwr_enablebkp(writable); -} - -/**************************************************************************** - * Name: stm32_pwr_enablebkp - * - * Description: - * Enables access to the backup domain (RTC registers, RTC backup data - * registers and backup SRAM). - * - * NOTE: Reference counting is used in order to supported nested calls to - * this function. As a consequence, every call to stm32_pwr_enablebkp - * (true) must be followed by a matching call to stm32_pwr_enablebkp(false). - * - * Input Parameters: - * writable - True: enable ability to write to backup domain registers - * - * Returned Value: - * None - * - ****************************************************************************/ - -void stm32_pwr_enablebkp(bool writable) -{ - irqstate_t flags; - uint16_t regval; - bool waswritable; - bool wait = false; - - flags = enter_critical_section(); - - /* Get the current state of the STM32 PWR control register */ - - regval = stm32_pwr_getreg32(STM32_PWR_CR_OFFSET); - waswritable = ((regval & PWR_CR_DBP) != 0); - - if (writable) - { - DEBUGASSERT(g_bkp_writable_counter < UINT16_MAX); - g_bkp_writable_counter++; - } - else if (g_bkp_writable_counter > 0) - { - g_bkp_writable_counter--; - } - - /* Enable or disable the ability to write */ - - if (waswritable && g_bkp_writable_counter == 0) - { - /* Disable backup domain access */ - - regval &= ~PWR_CR_DBP; - stm32_pwr_putreg32(STM32_PWR_CR_OFFSET, regval); - } - else if (!waswritable && g_bkp_writable_counter > 0) - { - /* Enable backup domain access */ - - regval |= PWR_CR_DBP; - stm32_pwr_putreg32(STM32_PWR_CR_OFFSET, regval); - - wait = true; - } - - leave_critical_section(flags); - - if (wait) - { - /* Enable does not happen right away */ - - up_udelay(4); - } -} - -/**************************************************************************** - * Name: stm32_pwr_enablewkup - * - * Description: - * Enables the WKUP pin. - * - * Input Parameters: - * wupin - Selects the WKUP pin to enable/disable - * wupon - state to set it to - * - * Returned Value: - * Zero (OK) is returned on success; A negated errno value is returned on - * any failure. The only cause of failure is if the selected MCU does not - * support the requested wakeup pin. - * - ****************************************************************************/ - -int stm32_pwr_enablewkup(enum stm32_pwr_wupin_e wupin, bool wupon) -{ - uint16_t pinmask; - - /* Select the PWR_CSR bit associated with the requested wakeup pin */ - - switch (wupin) - { - case PWR_WUPIN_1: /* Wake-up pin 1 (all parts) */ - pinmask = PWR_CSR_EWUP1; - break; - -#ifdef HAVE_PWR_WKUP2 - case PWR_WUPIN_2: /* Wake-up pin 2 */ - pinmask = PWR_CSR_EWUP2; - break; -#endif - -#ifdef HAVE_PWR_WKUP3 - case PWR_WUPIN_3: /* Wake-up pin 3 */ - pinmask = PWR_CSR_EWUP3; - break; -#endif - - default: - return -EINVAL; - } - - /* Set/clear the wakeup pin enable bit in the CSR. This must be done - * within a critical section because the CSR is shared with other functions - * that may be running concurrently on another thread. - */ - - if (wupon) - { - /* Enable the wakeup pin by setting the bit in the CSR. */ - - stm32_pwr_modifyreg32(STM32_PWR_CSR_OFFSET, 0, pinmask); - } - else - { - /* Disable the wakeup pin by clearing the bit in the CSR. */ - - stm32_pwr_modifyreg32(STM32_PWR_CSR_OFFSET, pinmask, 0); - } - - return OK; -} - -/**************************************************************************** - * Name: stm32_pwr_getsbf - * - * Description: - * Return the standby flag. - * - ****************************************************************************/ - -bool stm32_pwr_getsbf(void) -{ - return (stm32_pwr_getreg32(STM32_PWR_CSR_OFFSET) & PWR_CSR_SBF) != 0; -} - -/**************************************************************************** - * Name: stm32_pwr_getwuf - * - * Description: - * Return the wakeup flag. - * - ****************************************************************************/ - -bool stm32_pwr_getwuf(void) -{ - return (stm32_pwr_getreg32(STM32_PWR_CSR_OFFSET) & PWR_CSR_WUF) != 0; -} - -/**************************************************************************** - * Name: stm32_pwr_setvos - * - * Description: - * Set voltage scaling for EnergyLite devices. - * - * Input Parameters: - * vos - Properly aligned voltage scaling select bits for the PWR_CR - * register. - * - * Returned Value: - * None - * - * Assumptions: - * At present, this function is called only from initialization logic. If - * used for any other purpose that protection to assure that its operation - * is atomic will be required. - * - ****************************************************************************/ - -#ifdef CONFIG_STM32F0L0G0_ENERGYLITE -void stm32_pwr_setvos(uint16_t vos) -{ - uint16_t regval; - - /* The following sequence is required to program the voltage regulator - * ranges: - * 1. Check VDD to identify which ranges are allowed... - * 2. Poll VOSF bit of in PWR_CSR. Wait until it is reset to 0. - * 3. Configure the voltage scaling range by setting the VOS bits in the - * PWR_CR register. - * 4. Poll VOSF bit of in PWR_CSR register. Wait until it is reset to 0. - */ - - while ((stm32_pwr_getreg32(STM32_PWR_CSR_OFFSET) & PWR_CSR_VOSF) != 0) - { - } - - regval = stm32_pwr_getreg32(STM32_PWR_CR_OFFSET); - regval &= ~PWR_CR_VOS_MASK; - regval |= (vos & PWR_CR_VOS_MASK); - stm32_pwr_putreg32(STM32_PWR_CR_OFFSET, regval); - - while ((stm32_pwr_getreg32(STM32_PWR_CSR_OFFSET) & PWR_CSR_VOSF) != 0) - { - } -} - -/**************************************************************************** - * Name: stm32_pwr_setpvd - * - * Description: - * Sets power voltage detector - * - * Input Parameters: - * pls - PVD level - * - * Returned Value: - * None - * - * Assumptions: - * At present, this function is called only from initialization logic. If - * used for any other purpose that protection to assure that its operation - * is atomic will be required. - * - ****************************************************************************/ - -void stm32_pwr_setpvd(uint16_t pls) -{ - uint16_t regval; - - /* Set PLS */ - - regval = stm32_pwr_getreg32(STM32_PWR_CR_OFFSET); - regval &= ~PWR_CR_PLS_MASK; - regval |= (pls & PWR_CR_PLS_MASK); - - /* Write value to register */ - - stm32_pwr_putreg32(STM32_PWR_CR_OFFSET, regval); -} - -/**************************************************************************** - * Name: stm32_pwr_enablepvd - * - * Description: - * Enable the Programmable Voltage Detector - * - ****************************************************************************/ - -void stm32_pwr_enablepvd(void) -{ - /* Enable PVD by setting the PVDE bit in PWR_CR register. */ - - stm32_pwr_modifyreg32(STM32_PWR_CR_OFFSET, 0, PWR_CR_PVDE); -} - -/**************************************************************************** - * Name: stm32_pwr_disablepvd - * - * Description: - * Disable the Programmable Voltage Detector - * - ****************************************************************************/ - -void stm32_pwr_disablepvd(void) -{ - /* Disable PVD by clearing the PVDE bit in PWR_CR register. */ - - stm32_pwr_modifyreg32(STM32_PWR_CR_OFFSET, PWR_CR_PVDE, 0); -} - -#endif /* CONFIG_STM32F0L0G0_ENERGYLITE */ - -#endif /* CONFIG_STM32F0L0G0_PWR */ diff --git a/arch/arm/src/stm32f0l0g0/stm32g0_pwr.c b/arch/arm/src/stm32f0l0g0/stm32g0_pwr.c deleted file mode 100644 index 162a715f142cd..0000000000000 --- a/arch/arm/src/stm32f0l0g0/stm32g0_pwr.c +++ /dev/null @@ -1,96 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32g0_pwr.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include "arm_internal.h" -#include "stm32_pwr.h" - -#if defined(CONFIG_STM32F0L0G0_PWR) - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -static inline uint32_t stm32_pwr_getreg32(uint8_t offset) -{ - return getreg32(STM32_PWR_BASE + (uint32_t)offset); -} - -static inline void stm32_pwr_putreg32(uint8_t offset, uint32_t value) -{ - putreg32(value, STM32_PWR_BASE + (uint32_t)offset); -} - -static inline void stm32_pwr_modifyreg32(uint8_t offset, uint32_t clearbits, - uint32_t setbits) -{ - modifyreg32(STM32_PWR_BASE + (uint32_t)offset, clearbits, setbits); -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -void stm32_pwr_setvos(uint16_t vos) -{ - uint16_t regval; - - /* The following sequence is required to program the voltage regulator - * ranges: - * 1. Wait until VOSF flag is cleared in Power Status register 2 (PWR_SR2). - * 2. Configure the voltage scaling range by setting the VOS bits in the - * PWR_CR1 register. - * 3. Wait until VOSF flag is cleared in Power Status register 2 (PWR_SR2). - * - * No checking is performed to ensure the VOS value to be set is within the - * valid range. - */ - - while ((stm32_pwr_getreg32(STM32_PWR_SR2_OFFSET) & PWR_SR2_VOSF) != 0) - { - } - - regval = stm32_pwr_getreg32(STM32_PWR_CR1_OFFSET); - regval &= ~PWR_CR1_VOS_MASK; - regval |= (vos & PWR_CR1_VOS_MASK); - stm32_pwr_putreg32(STM32_PWR_CR1_OFFSET, regval); - - while ((stm32_pwr_getreg32(STM32_PWR_SR2_OFFSET) & PWR_SR2_VOSF) != 0) - { - } -} - -/* TODO Other stm32_pwr_* functions need to be implemented */ - -#endif /* CONFIG_STM32F0L0G0_PWR */ diff --git a/arch/arm/src/stm32f0l0g0/stm32g0c0_flash.c b/arch/arm/src/stm32f0l0g0/stm32g0c0_flash.c deleted file mode 100644 index 201619738e26a..0000000000000 --- a/arch/arm/src/stm32f0l0g0/stm32g0c0_flash.c +++ /dev/null @@ -1,901 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32g0c0_flash.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* Provides standard flash access functions, to be used by the flash mtd - * driver. The interface is defined in the include/nuttx/progmem.h - * - * Notes: - * - Terminology: the G0xx reference manual [RM0444] refers to erase blocks - * as 'pages'. In this file, erase blocks are referred to as 'blocks' and - * the smallest write allowed is referred to as a 'page'. The STMicro - * reference manuals are not consistent in naming convention. - * - Blocking Nature: up_progmem_write() and up_progmem_eraseblock() will - * both block without releasing (up_udelay) while waiting for flash - * operations to complete. Take this into account for applications - * that use these functions. - */ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include "stm32_flash.h" - -#include -#include -#include -#include -#include - -#include - -#include -#include -#include - -#include "hardware/stm32_flash.h" -#include "hardware/stm32_memorymap.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#define _K(x) ((x)*1024) -#define FLASH_BLOCK_SIZE _K(2) -#define FLASH_PAGE_SIZE 8 - -#if !defined(CONFIG_STM32F0L0G0_FLASH_CONFIG_4) && \ - !defined(CONFIG_STM32F0L0G0_FLASH_CONFIG_6) && \ - !defined(CONFIG_STM32F0L0G0_FLASH_CONFIG_8) && \ - !defined(CONFIG_STM32F0L0G0_FLASH_CONFIG_B) && \ - !defined(CONFIG_STM32F0L0G0_FLASH_CONFIG_C) && \ - !defined(CONFIG_STM32F0L0G0_FLASH_CONFIG_E) && \ - !defined(CONFIG_STM32F0L0G0_FLASH_OVERRIDE) -# error "No valid flash configuration was defined." -#endif - -#ifdef CONFIG_STM32F0L0G0_FLASH_OVERRIDE -# undef CONFIG_STM32F0L0G0_FLASH_CONFIG_4 -# undef CONFIG_STM32F0L0G0_FLASH_CONFIG_6 -# undef CONFIG_STM32F0L0G0_FLASH_CONFIG_8 -# undef CONFIG_STM32F0L0G0_FLASH_CONFIG_B -# undef CONFIG_STM32F0L0G0_FLASH_CONFIG_C -# undef CONFIG_STM32F0L0G0_FLASH_CONFIG_E -# if defined(CONFIG_STM32F0L0G0_FLASH_OVERRIDE_4) -# define CONFIG_STM32F0L0G0_FLASH_CONFIG_4 -# elif defined(CONFIG_STM32F0L0G0_FLASH_OVERRIDE_6) -# define CONFIG_STM32F0L0G0_FLASH_CONFIG_6 -# elif defined(CONFIG_STM32F0L0G0_FLASH_OVERRIDE_8) -# define CONFIG_STM32F0L0G0_FLASH_CONFIG_8 -# elif defined(CONFIG_STM32F0L0G0_FLASH_OVERRIDE_B) -# define CONFIG_STM32F0L0G0_FLASH_CONFIG_B -# elif defined(CONFIG_STM32F0L0G0_FLASH_OVERRIDE_C) -# define CONFIG_STM32F0L0G0_FLASH_CONFIG_C -# elif defined(CONFIG_STM32F0L0G0_FLASH_OVERRIDE_E) -# define CONFIG_STM32F0L0G0_FLASH_CONFIG_E -# else -# error "Invalid flash configuration override provided" -# endif -#endif - -#if defined(CONFIG_STM32F0L0G0_FLASH_CONFIG_4) -# define FLASH_NBLOCKS 8 -#elif defined(CONFIG_STM32F0L0G0_FLASH_CONFIG_6) -# define FLASH_NBLOCKS 16 -#elif defined(CONFIG_STM32F0L0G0_FLASH_CONFIG_8) -# define FLASH_NBLOCKS 32 -#elif defined(CONFIG_STM32F0L0G0_FLASH_CONFIG_B) -# define FLASH_NBLOCKS 64 -#elif defined(CONFIG_STM32F0L0G0_FLASH_CONFIG_C) -# define FLASH_NBLOCKS 128 -# ifdef CONFIG_ARCH_CHIP_STM32G0 -# define FLASH_DUAL_BANK 1 -# define FLASH_BANK2_BASE 0x08020000 -# endif -#elif defined(CONFIG_STM32F0L0G0_FLASH_CONFIG_E) -# define FLASH_NBLOCKS 256 -# ifdef CONFIG_ARCH_CHIP_STM32G0 -# define FLASH_DUAL_BANK 1 -# define FLASH_BANK2_BASE 0x08040000 -# endif -#else -# error "Invalid flash configuration defined" -#endif - -#ifdef FLASH_DUAL_BANK -# define FLASH_BANKSIZE (FLASH_NBLOCKS * FLASH_BLOCK_SIZE / 2) -# define FLASH_SR_BSY (FLASH_SR_BSY1 | FLASH_SR_BSY2) -#else -# define FLASH_BANKSIZE (FLASH_NBLOCKS * FLASH_BLOCK_SIZE) -# define FLASH_SR_BSY (FLASH_SR_BSY1) -#endif - -/* Dual bank G0B1 MCUs have a non-linear mapping of block number between - * banks. Bank 2 starts at block number 256, even if bank 1 ends at 63 - * or 127. - */ - -#define FLASH_BANK2_START_BLOCKNUM 256 - -#define FLASH_TOTALSIZE (FLASH_NBLOCKS * FLASH_BLOCK_SIZE) -#define FLASH_NPAGES (FLASH_NBLOCKS * FLASH_BLOCK_SIZE / FLASH_PAGE_SIZE) -#define FLASH_KEY1 0x45670123 -#define FLASH_KEY2 0xcdef89ab -#define FLASH_OPTKEY1 0x08192a3b -#define FLASH_OPTKEY2 0x4c5d6e7f -#define FLASH_ERASEDVALUE 0xffu -#define FLASH_ERASEDVALUE_DW 0xffffffffu - -#define FLASH_TIMEOUT 5000000 /* 5s */ - -#define FLASH_SR_CLEAR_ERROR_FLAGS (FLASH_SR_OPERR|FLASH_SR_PROGERR|FLASH_SR_WRPERR|\ - FLASH_SR_PGAERR|FLASH_SR_SIZERR|FLASH_SR_PGSERR|\ - FLASH_SR_MISSERR|FLASH_SR_FASTERR|FLASH_SR_RDERR|FLASH_SR_OPTVERR) - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -struct stm32_flash_priv_s -{ - uint32_t base; /* FLASH base address */ - uint32_t stblock; /* The first block number */ - uint32_t stpage; /* The first page number */ -}; - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -static void flash_unlock_cr(void); -static void flash_lock_cr(void); -static bool flash_unlock_opt(void); -static void flash_lock_opt(void); -static int flash_israngeerased(size_t startaddress, size_t size); -static inline struct stm32_flash_priv_s *flash_bank(size_t address); -static int flash_wait_for_operation(void); -static int flash_verify_blocknum(size_t block); -static uint32_t flash_block_address(size_t block); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -static struct stm32_flash_priv_s flash_bank1_priv = -{ - .base = STM32_FLASH_BASE, - .stblock = 0, - .stpage = 0 -}; - -#ifdef FLASH_DUAL_BANK -static struct stm32_flash_priv_s flash_bank2_priv = -{ - .base = FLASH_BANK2_BASE, - .stblock = FLASH_BANK2_START_BLOCKNUM, - .stpage = (FLASH_NPAGES / 2) -}; -#endif - -static mutex_t g_lock = NXMUTEX_INITIALIZER; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: flash_bank - * - * Description: - * Returns the priv pointer to the correct bank - * - ****************************************************************************/ - -static inline struct stm32_flash_priv_s *flash_bank(size_t address) -{ - struct stm32_flash_priv_s *priv = NULL; - - if (address >= flash_bank1_priv.base && - address < flash_bank1_priv.base + FLASH_BANKSIZE) - { - priv = &flash_bank1_priv; - } -#ifdef FLASH_DUAL_BANK - else if (address >= flash_bank2_priv.base && - address < flash_bank2_priv.base + FLASH_BANKSIZE) - { - priv = &flash_bank2_priv; - } -#endif - - return priv; -} - -/**************************************************************************** - * Name: flash_israngeerased - * - * Description: - * Returns count of non-erased words - * - ****************************************************************************/ - -static int flash_israngeerased(size_t startaddress, size_t size) -{ - uint32_t *addr; - uint8_t *baddr; - size_t count = 0; - size_t bwritten = 0; - - if (!flash_bank(startaddress) || !flash_bank(startaddress + size - 1)) - { - return -EIO; - } - - addr = (uint32_t *)startaddress; - - while (count + 4 <= size) - { - if (getreg32(addr) != FLASH_ERASEDVALUE_DW) - { - bwritten++; - } - - addr++; - count += 4; - } - - baddr = (uint8_t *)addr; - - while (count < size) - { - if (getreg8(baddr) != FLASH_ERASEDVALUE) - { - /* Technically counting more than once per word but OK since - * anything that is non-zero is a failure anyways. - */ - - bwritten++; - } - - baddr++; - count++; - } - - return bwritten; -} - -/**************************************************************************** - * Name: flash_wait_for_operation() - * - * Description: - * Wait for last write/erase operation to finish - * Return error in case of timeout - * - * Returned Value: - * Zero or error value - * - * -EBUSY: Timeout while waiting for previous write/erase operation to - * complete - * - ****************************************************************************/ - -static int flash_wait_for_operation(void) -{ - int i; - bool timeout = true; - - UP_DSB(); - - for (i = 0; i < FLASH_TIMEOUT; i += 10) - { - if (!(getreg32(STM32_FLASH_SR) & (FLASH_SR_CFGBSY | FLASH_SR_BSY))) - { - timeout = false; - break; - } - - up_udelay(10); - } - - if (timeout) - { - return -EBUSY; - } - - return 0; -} - -/**************************************************************************** - * Name: flash_unlock_cr - * - * Description: - * Unlock flash control register, if it is not already unlocked. - * - ****************************************************************************/ - -static void flash_unlock_cr(void) -{ - /* FLASH_CR cannot be written when BSY1 flag set */ - - while (getreg32(STM32_FLASH_SR) & (FLASH_SR_BSY1 | FLASH_SR_CFGBSY)) - { - } - - if (getreg32(STM32_FLASH_CR) & FLASH_CR_LOCK) - { - putreg32(FLASH_KEY1, STM32_FLASH_KEYR); - putreg32(FLASH_KEY2, STM32_FLASH_KEYR); - } - - DEBUGASSERT((getreg32(STM32_FLASH_CR) & FLASH_CR_LOCK) == 0); -} - -/**************************************************************************** - * Name: flash_lock_cr - * - * Description: - * Lock flash control register. - * - ****************************************************************************/ - -static void flash_lock_cr(void) -{ - modifyreg32(STM32_FLASH_CR, 0, FLASH_CR_LOCK); -} - -/**************************************************************************** - * Name: flash_unlock_opt - * - * Description: - * Unlock flash option bytes register, if it is not already unlocked. - * - ****************************************************************************/ - -static bool flash_unlock_opt(void) -{ - bool was_locked = false; - flash_unlock_cr(); - - if (getreg32(STM32_FLASH_CR) & FLASH_CR_OPTLOCK) - { - was_locked = true; - - putreg32(FLASH_OPTKEY1, STM32_FLASH_OPTKEYR); - putreg32(FLASH_OPTKEY2, STM32_FLASH_OPTKEYR); - } - - DEBUGASSERT((getreg32(STM32_FLASH_CR) & FLASH_CR_OPTLOCK) == 0); - - return was_locked; -} - -/**************************************************************************** - * Name: flash_lock_opt - * - * Description: - * Lock flash option bytes register. - * - ****************************************************************************/ - -static void flash_lock_opt(void) -{ - modifyreg32(STM32_FLASH_CR, 0, FLASH_CR_OPTLOCK); -} - -/**************************************************************************** - * Name: flash_verify_blocknum - * - * Description: - * Verify the provided block number is valid based on the flash - * configuration. This is done because the reference implementation and - * reference manual refer to non-contiguous block (page) numbers for the - * flash layout on dual-bank devices. - * - * Returned Value: - * Zero or negated errno value. - * - * -EFAULT: Block number provided falls outside of the ranges specified in - * reference manual. - * - ****************************************************************************/ - -static int flash_verify_blocknum(size_t block) -{ -#ifdef FLASH_DUAL_BANK -#if defined(CONFIG_STM32F0L0G0_FLASH_CONFIG_C) - if ((block < 0 || block > 63) && (block < 256 || block > 319)) - { - return -EFAULT; - } -#elif defined(CONFIG_STM32F0L0G0_FLASH_CONFIG_E) - if ((block < 0 || block > 127) && (block < 256 || block > 383)) - { - return -EFAULT; - } -#else -# error "Dual bank flash config not supported by flash driver" -#endif -#else - if (block > FLASH_NBLOCKS) - { - return -EFAULT; - } -#endif - - return 0; -} - -/**************************************************************************** - * Name: flash_block_address - * - * Description: - * Find the start address for the given block number. - * - * Returned Value: - * Memory address corresponding to given block number. - * - * Assumptions: - * This function assumes the block number has already been verified. Take - * care to make sure the block number is valid for the specific chip using - * flash_verify_blocknum() first. - * - ****************************************************************************/ - -static uint32_t flash_block_address(size_t block) -{ - uint32_t addr; -#ifdef FLASH_DUAL_BANK - if (block >= flash_bank2_priv.stblock) - { - addr = flash_bank2_priv.base + - (block - flash_bank2_priv.stblock) * FLASH_BLOCK_SIZE; - } - else - { - addr = flash_bank1_priv.base + block * FLASH_BLOCK_SIZE; - } -#else - addr = flash_bank1_priv.base + block * FLASH_BLOCK_SIZE; -#endif - return addr; -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_flash_unlock - * - * Description: - * Unlock flash control register (FLASH_CR) - * - ****************************************************************************/ - -void stm32_flash_unlock(void) -{ - nxmutex_lock(&g_lock); - flash_unlock_cr(); - nxmutex_unlock(&g_lock); -} - -/**************************************************************************** - * Name: stm32_flash_lock - * - * Description: - * Lock flash control register (FLASH_CR) - * - ****************************************************************************/ - -void stm32_flash_lock(void) -{ - nxmutex_lock(&g_lock); - flash_lock_cr(); - nxmutex_unlock(&g_lock); -} - -/**************************************************************************** - * Name: stm32_flash_getopt - * - * Description: - * Read the current flash option bytes from FLASH_OPTR - * - * Input Parameters: - * opt - location to store read of FLASH_OPTR - * - ****************************************************************************/ - -void stm32_flash_getopt(uint32_t *opt) -{ - *opt = getreg32(STM32_FLASH_OPTR); -} - -/**************************************************************************** - * Name: stm32_flash_optmodify - * - * Description: - * Modifies the current flash option bytes, given bits to set and clear. - * - * Input Parameters: - * clear - clear bits for FLASH_OPTR - * set - set bits for FLASH_OPTR - * - * Returned Value: - * Zero or error value - * - * -EBUSY: Timeout waiting for previous FLASH operation to occur, or - * there was data in the flash data buffer. - * - * Notes: - * This function WILL BLOCK and NOT release the thread. This is a sensitive - * operation with the potential to brick the device if interrupted. So, for - * the actual opt modify start, this function uses a tight while loop to - * wait for completion. - * - ****************************************************************************/ - -int stm32_flash_optmodify(uint32_t clear, uint32_t set) -{ - int ret; - bool was_locked; - - ret = flash_wait_for_operation(); - if (ret != 0) - { - return -EBUSY; - } - - was_locked = flash_unlock_opt(); - modifyreg32(STM32_FLASH_SR, 0, FLASH_SR_CLEAR_ERROR_FLAGS); - - modifyreg32(STM32_FLASH_OPTR, clear, set); - - while (getreg32(STM32_FLASH_SR) & FLASH_SR_BSY1) - { - } - - modifyreg32(STM32_FLASH_CR, 0, FLASH_CR_OPTSTRT); - - while (getreg32(STM32_FLASH_SR) & FLASH_SR_BSY1) - { - } - - if (was_locked) - { - flash_lock_opt(); - } - - return 0; -} - -#ifdef CONFIG_ARCH_HAVE_PROGMEM - -/* up_progmem_x functions defined in nuttx/include/nuttx/progmem.h - * - * Notes on Implementation: - * - The driver implementations DO NOT enforce memory address boundaries. - * For processors with less than 2MB flash, the user is responsible for - * not writing to memory between banks. - * - */ - -size_t up_progmem_pagesize(size_t page) -{ - return FLASH_PAGE_SIZE; -} - -ssize_t up_progmem_getpage(size_t addr) -{ - struct stm32_flash_priv_s *priv; - - priv = flash_bank(addr); - - if (priv == NULL) - { - return -EFAULT; - } - - return priv->stpage + ((addr - priv->base) / FLASH_PAGE_SIZE); -} - -size_t up_progmem_getaddress(size_t page) -{ - struct stm32_flash_priv_s *priv; - - if (page >= FLASH_NPAGES) - { - return SIZE_MAX; - } - - priv = flash_bank(STM32_FLASH_BASE + (page * FLASH_PAGE_SIZE)); - - if (!priv) - { - return SIZE_MAX; - } - - return priv->base + (page - priv->stpage) * FLASH_PAGE_SIZE; -} - -size_t up_progmem_neraseblocks(void) -{ - return FLASH_NBLOCKS; -} - -bool up_progmem_isuniform(void) -{ - /* So... Every other implementation of this in STM chips returns this as - * true. However, the description in include/nuttx/progmem.h states this to - * mean "does size of erase 'page' == size of read/write 'page'". Which is - * NOT true for most of these chips. - * - * On the G0, erase blocks are 2K and read/write page is 64 bit. - */ - - return false; -} - -ssize_t up_progmem_ispageerased(size_t page) -{ - size_t addr; - size_t count; - size_t bwritten = 0; - - if (page >= FLASH_NPAGES) - { - return -EFAULT; - } - - /* Verify */ - - for (addr = up_progmem_getaddress(page), count = up_progmem_pagesize(page); - count; count--, addr++) - { - if (getreg8(addr) != FLASH_ERASEDVALUE) - { - bwritten++; - } - } - - return bwritten; -} - -size_t up_progmem_erasesize(size_t block) -{ - return FLASH_BLOCK_SIZE; -} - -ssize_t up_progmem_eraseblock(size_t block) -{ - int ret; - size_t block_address; - - ret = flash_verify_blocknum(block); - if (ret < 0) - { - return -EFAULT; - } - - block_address = flash_block_address(block); - - ret = nxmutex_lock(&g_lock); - if (ret < 0) - { - return (ssize_t)ret; - } - - if (flash_wait_for_operation()) - { - ret = -EIO; - goto exit_with_lock; - } - - /* Get flash ready and begin erasing single block */ - - flash_unlock_cr(); - - modifyreg32(STM32_FLASH_SR, 0, FLASH_SR_CLEAR_ERROR_FLAGS); - - /* By now, know that the block number is valid and corresponds to a - * bank (if dual bank). So, don't need to verify that it is in bounds. - */ - -#ifdef FLASH_DUAL_BANK - - /* Note to future developers: The CR register definition in the reference - * manual [RM0444] is not clear on if bank selection is necessary. The PNB - * definition seems to imply that writing block numbers corresponding to - * bank 2 should just work. This is NOT the case. Writing 256 to PNB will - * cause block (page) 0 to be erased. Therefore, must switch BKER bit to - * match the correct bank. - */ - - if (block >= flash_bank2_priv.stblock) - { - modifyreg32(STM32_FLASH_CR, 0, FLASH_CR_BKER); - } - else - { - modifyreg32(STM32_FLASH_CR, FLASH_CR_BKER, 0); - } -#endif - - /* Setup erase parameters and start */ - - modifyreg32(STM32_FLASH_CR, FLASH_CR_PNB_MASK, - FLASH_CR_PER | (block << FLASH_CR_PNB_SHIFT)); - modifyreg32(STM32_FLASH_CR, 0, FLASH_CR_STRT); - - /* Wait for erase operation to complete */ - - if (flash_wait_for_operation()) - { - ret = -EIO; - goto exit_with_unlock; - } - - modifyreg32(STM32_FLASH_CR, FLASH_CR_PNB_MASK | FLASH_CR_PER, 0); - - ret = 0; - up_invalidate_dcache(block_address, block_address + FLASH_BLOCK_SIZE); - -exit_with_unlock: - flash_lock_cr(); - -exit_with_lock: - nxmutex_unlock(&g_lock); - - if (ret == 0 && - flash_israngeerased(block_address, up_progmem_erasesize(block)) == 0) - { - ret = up_progmem_erasesize(block); /* Success */ - } - else - { - ret = -EIO; - } - - return ret; -} - -ssize_t up_progmem_write(size_t addr, const void *buf, size_t count) -{ - struct stm32_flash_priv_s *priv; - uint32_t *fp; - uint32_t *rp; - uint32_t *ll = (uint32_t *)buf; - size_t faddr; - size_t written = count; - int ret; - const size_t pagesize = up_progmem_pagesize(0); /* 64-bit, 8 bytes per page */ - const size_t llperpage = pagesize / sizeof(uint32_t); - size_t pcount = count / pagesize; - - priv = flash_bank(addr); - - if (priv == NULL) - { - return -EFAULT; - } - - /* Check for valid address range */ - - if (addr < priv->base || - addr + count > priv->base + (FLASH_BANKSIZE)) - { - return -EFAULT; - } - - ret = nxmutex_lock(&g_lock); - if (ret < 0) - { - return (ssize_t)ret; - } - - /* Check address and count alignment */ - - DEBUGASSERT(!(addr % pagesize)); - DEBUGASSERT(!(count % pagesize)); - - if (flash_wait_for_operation()) - { - written = -EIO; - goto exit_with_lock; - } - - /* Get flash ready for write */ - - flash_unlock_cr(); - - modifyreg32(STM32_FLASH_SR, 0, FLASH_SR_CLEAR_ERROR_FLAGS); - modifyreg32(STM32_FLASH_CR, 0, FLASH_CR_PG); - - /* Write */ - - for (ll = (uint32_t *)buf, faddr = addr; pcount; - pcount -= 1, ll += llperpage, faddr += pagesize) - { - fp = (uint32_t *)faddr; - rp = ll; - - UP_MB(); - - /* Write 2 32 bit word and wait to complete */ - - *fp++ = *rp++; - *fp++ = *rp++; - - /* Data synchronous Barrier (DSB) just after the write operation. This - * will force the CPU to respect the sequence of instruction (no - * optimization). - */ - - UP_MB(); - - if (flash_wait_for_operation()) - { - written = -EIO; - goto exit_with_unlock; - } - - /* Future improvements may add ECC checking here (STM32G0 only). */ - } - - modifyreg32(STM32_FLASH_CR, FLASH_CR_PG, 0); - -exit_with_unlock: - flash_lock_cr(); - - if (written > 0) - { - for (ll = (uint32_t *)buf, faddr = addr, pcount = count / pagesize; - pcount; pcount -= 1, ll += llperpage, faddr += pagesize) - { - fp = (uint32_t *)faddr; - rp = ll; - - modifyreg32(STM32_FLASH_SR, 0, FLASH_SR_CLEAR_ERROR_FLAGS); - - if ((*fp++ != *rp++) || - (*fp++ != *rp++)) - { - written = -EIO; - break; - } - - /* Future improvements may add ECC checking here (STM32G0 only). */ - } - - modifyreg32(STM32_FLASH_SR, 0, FLASH_SR_CLEAR_ERROR_FLAGS); - } - -exit_with_lock: - nxmutex_unlock(&g_lock); - return written; -} - -uint8_t up_progmem_erasestate(void) -{ - return FLASH_ERASEDVALUE; -} - -#endif /* CONFIG_ARCH_HAVE_PROGMEM */ diff --git a/arch/arm/src/stm32f1/CMakeLists.txt b/arch/arm/src/stm32f1/CMakeLists.txt new file mode 100644 index 0000000000000..2126b9b6e336a --- /dev/null +++ b/arch/arm/src/stm32f1/CMakeLists.txt @@ -0,0 +1,28 @@ +# ############################################################################## +# arch/arm/src/stm32f1/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(SRCS) + +list(APPEND SRCS stm32_rcc.c) + +target_sources(arch PRIVATE ${SRCS}) +add_subdirectory(${NUTTX_DIR}/arch/arm/src/common/stm32 stm32_common) diff --git a/arch/arm/src/stm32f1/Kconfig b/arch/arm/src/stm32f1/Kconfig new file mode 100644 index 0000000000000..43349d58bce89 --- /dev/null +++ b/arch/arm/src/stm32f1/Kconfig @@ -0,0 +1,481 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# +comment "STM32 F1 configuration" + +if ARCH_CHIP_STM32F1 + +choice + prompt "STM32F1 Chip Selection" + default ARCH_CHIP_STM32F103ZE + depends on ARCH_CHIP_STM32F1 + +config ARCH_CHIP_STM32F100C8 + bool "STM32F100C8" + select STM32_STM32F10XX + select STM32F1_VALUELINE + select STM32F1_MEDIUMDENSITY + select STM32_HAVE_DAC1 + select STM32_HAVE_I2C2 + select STM32_HAVE_TIM4 + +config ARCH_CHIP_STM32F100CB + bool "STM32F100CB" + select STM32_STM32F10XX + select STM32F1_VALUELINE + select STM32F1_MEDIUMDENSITY + select STM32_HAVE_DAC1 + select STM32_HAVE_I2C2 + select STM32_HAVE_TIM4 + +config ARCH_CHIP_STM32F100R8 + bool "STM32F100R8" + select STM32_STM32F10XX + select STM32F1_VALUELINE + select STM32F1_MEDIUMDENSITY + select STM32_HAVE_DAC1 + select STM32_HAVE_I2C2 + select STM32_HAVE_TIM4 + +config ARCH_CHIP_STM32F100RB + bool "STM32F100RB" + select STM32_STM32F10XX + select STM32F1_VALUELINE + select STM32F1_MEDIUMDENSITY + select STM32_HAVE_DAC1 + select STM32_HAVE_I2C2 + select STM32_HAVE_TIM4 + +config ARCH_CHIP_STM32F100RC + bool "STM32F100RC" + select STM32_STM32F10XX + select STM32F1_VALUELINE + select STM32F1_HIGHDENSITY + select STM32_HAVE_DAC1 + select STM32_HAVE_I2C2 + select STM32_HAVE_TIM4 + +config ARCH_CHIP_STM32F100RD + bool "STM32F100RD" + select STM32_STM32F10XX + select STM32F1_VALUELINE + select STM32F1_HIGHDENSITY + select STM32_HAVE_DAC1 + select STM32_HAVE_I2C2 + select STM32_HAVE_TIM4 + +config ARCH_CHIP_STM32F100RE + bool "STM32F100RE" + select STM32_STM32F10XX + select STM32F1_VALUELINE + select STM32F1_HIGHDENSITY + select STM32_HAVE_DAC1 + select STM32_HAVE_I2C2 + select STM32_HAVE_TIM4 + +config ARCH_CHIP_STM32F100V8 + bool "STM32F100V8" + select STM32_STM32F10XX + select STM32F1_VALUELINE + select STM32F1_MEDIUMDENSITY + select STM32_HAVE_DAC1 + select STM32_HAVE_I2C2 + select STM32_HAVE_TIM4 + +config ARCH_CHIP_STM32F100VB + bool "STM32F100VB" + select STM32_STM32F10XX + select STM32F1_VALUELINE + select STM32F1_MEDIUMDENSITY + select STM32_HAVE_DAC1 + select STM32_HAVE_I2C2 + select STM32_HAVE_TIM4 + +config ARCH_CHIP_STM32F100VC + bool "STM32F100VC" + select STM32_STM32F10XX + select STM32F1_VALUELINE + select STM32F1_HIGHDENSITY + select STM32_HAVE_DAC1 + select STM32_HAVE_I2C2 + select STM32_HAVE_TIM4 + +config ARCH_CHIP_STM32F100VD + bool "STM32F100VD" + select STM32_STM32F10XX + select STM32F1_VALUELINE + select STM32F1_HIGHDENSITY + select STM32_HAVE_DAC1 + select STM32_HAVE_I2C2 + select STM32_HAVE_TIM4 + +config ARCH_CHIP_STM32F100VE + bool "STM32F100VE" + select STM32_STM32F10XX + select STM32F1_VALUELINE + select STM32F1_HIGHDENSITY + select STM32_HAVE_DAC1 + select STM32_HAVE_I2C2 + select STM32_HAVE_TIM4 + +config ARCH_CHIP_STM32F102CB + bool "STM32F102CB" + select STM32_STM32F10XX + select STM32F1_USBACCESSLINE + select STM32F1_MEDIUMDENSITY + select STM32_HAVE_I2C2 + select STM32_HAVE_TIM4 + +config ARCH_CHIP_STM32F103T8 + bool "STM32F103T8" + select STM32_STM32F10XX + select STM32F1_PERFORMANCELINE + select STM32F1_MEDIUMDENSITY + select STM32_HAVE_TIM4 + +config ARCH_CHIP_STM32F103TB + bool "STM32F103TB" + select STM32_STM32F10XX + select STM32F1_PERFORMANCELINE + select STM32F1_MEDIUMDENSITY + select STM32_HAVE_TIM4 + +config ARCH_CHIP_STM32F103C4 + bool "STM32F103C4" + select STM32_STM32F10XX + select STM32F1_PERFORMANCELINE + select STM32F1_LOWDENSITY + +config ARCH_CHIP_STM32F103C8 + bool "STM32F103C8" + select STM32_STM32F10XX + select STM32F1_PERFORMANCELINE + select STM32F1_MEDIUMDENSITY + select STM32_HAVE_I2C2 + select STM32_HAVE_TIM4 + +config ARCH_CHIP_STM32F103CB + bool "STM32F103CB" + select STM32_STM32F10XX + select STM32F1_PERFORMANCELINE + select STM32F1_MEDIUMDENSITY + select STM32_HAVE_I2C2 + select STM32_HAVE_TIM4 + +config ARCH_CHIP_STM32F103R8 + bool "STM32F103R8" + select STM32_STM32F10XX + select STM32F1_PERFORMANCELINE + select STM32F1_MEDIUMDENSITY + select STM32_HAVE_I2C2 + select STM32_HAVE_TIM4 + +config ARCH_CHIP_STM32F103RB + bool "STM32F103RB" + select STM32_STM32F10XX + select STM32F1_PERFORMANCELINE + select STM32F1_MEDIUMDENSITY + select STM32_HAVE_I2C2 + select STM32_HAVE_TIM4 + +config ARCH_CHIP_STM32F103RC + bool "STM32F103RC" + select STM32_STM32F10XX + select STM32F1_PERFORMANCELINE + select STM32F1_HIGHDENSITY + select STM32_HAVE_DAC1 + select STM32_HAVE_I2C2 + select STM32_HAVE_TIM4 + +config ARCH_CHIP_STM32F103RD + bool "STM32F103RD" + select STM32_STM32F10XX + select STM32F1_PERFORMANCELINE + select STM32F1_HIGHDENSITY + select STM32_HAVE_DAC1 + select STM32_HAVE_I2C2 + select STM32_HAVE_TIM4 + +config ARCH_CHIP_STM32F103RE + bool "STM32F103RE" + select STM32_STM32F10XX + select STM32F1_PERFORMANCELINE + select STM32F1_HIGHDENSITY + select STM32_HAVE_DAC1 + select STM32_HAVE_I2C2 + select STM32_HAVE_TIM4 + +config ARCH_CHIP_STM32F103RG + bool "STM32F103RG" + select STM32_STM32F10XX + select STM32F1_PERFORMANCELINE + select STM32F1_HIGHDENSITY + select STM32_HAVE_DAC1 + select STM32_HAVE_I2C2 + select STM32_HAVE_TIM4 + +config ARCH_CHIP_STM32F103V8 + bool "STM32F103V8" + select STM32_STM32F10XX + select STM32F1_PERFORMANCELINE + select STM32F1_MEDIUMDENSITY + select STM32_HAVE_I2C2 + select STM32_HAVE_TIM4 + +config ARCH_CHIP_STM32F103VB + bool "STM32F103VB" + select STM32_STM32F10XX + select STM32F1_PERFORMANCELINE + select STM32F1_MEDIUMDENSITY + select STM32_HAVE_I2C2 + select STM32_HAVE_TIM4 + +config ARCH_CHIP_STM32F103VC + bool "STM32F103VC" + select STM32_STM32F10XX + select STM32F1_PERFORMANCELINE + select STM32F1_HIGHDENSITY + select STM32_HAVE_DAC1 + select STM32_HAVE_I2C2 + select STM32_HAVE_TIM4 + +config ARCH_CHIP_STM32F103VE + bool "STM32F103VE" + select STM32_STM32F10XX + select STM32F1_PERFORMANCELINE + select STM32F1_HIGHDENSITY + select STM32_HAVE_DAC1 + select STM32_HAVE_I2C2 + select STM32_HAVE_TIM4 + +config ARCH_CHIP_STM32F103ZE + bool "STM32F103ZE" + select STM32_STM32F10XX + select STM32F1_PERFORMANCELINE + select STM32F1_HIGHDENSITY + select STM32_HAVE_DAC1 + select STM32_HAVE_I2C2 + select STM32_HAVE_TIM4 + +config ARCH_CHIP_STM32F105VB + bool "STM32F105VBT7" + select STM32_STM32F10XX + select STM32F1_CONNECTIVITYLINE + select STM32_HAVE_DAC1 + select STM32_HAVE_I2C2 + select STM32_HAVE_TIM4 + +config ARCH_CHIP_STM32F105RB + bool "STM32F105RB" + select STM32_STM32F10XX + select STM32F1_CONNECTIVITYLINE + select STM32_HAVE_DAC1 + select STM32_HAVE_I2C2 + select STM32_HAVE_TIM4 + +config ARCH_CHIP_STM32F107VC + bool "STM32F107VC" + select STM32_STM32F10XX + select STM32F1_CONNECTIVITYLINE + select STM32_HAVE_DAC1 + select STM32_HAVE_TIM4 + +endchoice + +endif + +config STM32_STM32F10XX + bool + default n + select STM32_HAVE_DMA1 + select STM32_HAVE_DMA2 if !STM32F1_VALUELINE || STM32F1_HIGHDENSITY + select ARCH_CORTEXM3 + select STM32_HAVE_I2C1 + select STM32_HAVE_SPI1 + select STM32_HAVE_SYSCFG if STM32F1_CONNECTIVITYLINE + select STM32_HAVE_USART1 + select STM32_HAVE_USART2 + select STM32_HAVE_SPI2 if STM32F1_HIGHDENSITY || STM32F1_MEDIUMDENSITY + select STM32_HAVE_SPI3 if STM32F1_HIGHDENSITY || STM32F1_MEDIUMDENSITY + select STM32_HAVE_RTC_COUNTER + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM3 + select STM32_HAVE_IP_AES_M3M4_V1 if STM32_HAVE_AES + select STM32_HAVE_IP_BBSRAM_M3M4_V1 + select STM32_HAVE_IP_BKP_M3M4_V1 + select STM32_HAVE_IP_CAN_BXCAN_M3M4_V1 + select STM32_HAVE_IP_CCM_M3M4_V1 if STM32_HAVE_CCM + select STM32_HAVE_IP_CRYPTO_M3M4_V1 + select STM32_HAVE_IP_DBGMCU_M3M4_V1 + select STM32_HAVE_IP_ADC_M3M4_V1_BASIC + select STM32_HAVE_COMMON_FOC + select STM32_HAVE_IP_DCMI_V1 + select STM32_HAVE_IP_DAC_M3M4_V1 + select STM32_HAVE_IP_DFUMODE_M3M4_V1 + select STM32_HAVE_IP_DMA_V1 + select STM32_HAVE_IP_DMA_V1_8CH + select STM32_HAVE_ETHERNET if STM32_HAVE_ETHMAC + select STM32_HAVE_IP_EXTI_V1 + select STM32_HAVE_IP_ETHMAC_M3M4_V1 if STM32_HAVE_ETHMAC + select STM32_HAVE_IP_FLASH_M3M4_V1 + select STM32_HAVE_IP_FLASH_M3M4_F1F3 + select STM32_HAVE_IP_FMC_M3M4_V1 if STM32_HAVE_FMC + select STM32_HAVE_IP_FREERUN_M3M4_V1 + select STM32_HAVE_IP_FSMC_M3M4_V1 if STM32_HAVE_FSMC + select STM32_HAVE_IP_GPIO_M3M4_V1 + select STM32_HAVE_IP_I2C_M3M4_V1 + select STM32_HAVE_IP_I2S_M3M4_V1 + select STM32_HAVE_IP_ONESHOT_M3M4_V1 + select STM32_HAVE_IP_PWR_M3M4_V1 + select STM32_HAVE_IP_RTC_COUNTER_M3M4_V1 + select STM32_HAVE_IP_RTC_M3M4_V1 + select STM32_HAVE_IP_SDIO_M3M4_V1 if !STM32F1_CONNECTIVITYLINE && !STM32F1_VALUELINE + select STM32_HAVE_IP_SPI_V1 + select STM32_HAVE_IP_SYSCFG_M3M4_V1 + select STM32_HAVE_IP_TIMERS_M3M4_V1 + select STM32_HAVE_IP_USART_V1 + select STM32_HAVE_IP_USBDEV_M3M4_V1 if STM32_HAVE_USBDEV + select STM32_HAVE_IP_USBFS_M3M4_V1 if STM32_HAVE_USBFS + select STM32_HAVE_IP_OTGFS_M3M4_V1 if STM32_HAVE_OTGFS + select STM32_HAVE_IP_WDG_M3M4_V1 + +config STM32F1_VALUELINE + bool + default n + select STM32_VALUELINE + select STM32_HAVE_USART3 + select STM32_HAVE_UART4 + select STM32_HAVE_UART5 + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM5 + select STM32_HAVE_TIM6 + select STM32_HAVE_TIM7 + select STM32_HAVE_TIM12 + select STM32_HAVE_TIM13 + select STM32_HAVE_TIM14 + select STM32_HAVE_TIM15 + select STM32_HAVE_TIM16 + select STM32_HAVE_TIM17 + select STM32_HAVE_SPI2 if STM32F1_HIGHDENSITY + select STM32_HAVE_SPI3 if STM32F1_HIGHDENSITY + +config STM32F1_CONNECTIVITYLINE + bool + default n + select STM32_CONNECTIVITYLINE + select STM32_HAVE_OTGFS + select STM32_HAVE_USART3 + select STM32_HAVE_UART4 + select STM32_HAVE_UART5 + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM5 + select STM32_HAVE_TIM6 + select STM32_HAVE_TIM7 + select STM32_HAVE_ADC2 + select STM32_HAVE_CAN1 + select STM32_HAVE_CAN2 + select STM32_HAVE_ETHMAC + select STM32_HAVE_SPI2 + select STM32_HAVE_SPI3 + +config STM32F1_PERFORMANCELINE + bool + default n + select STM32_HAVE_USBDEV + select STM32_HAVE_USART3 + select STM32_HAVE_UART4 + select STM32_HAVE_UART5 + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM5 + select STM32_HAVE_TIM6 + select STM32_HAVE_TIM7 + select STM32_HAVE_TIM8 + select STM32_HAVE_ADC2 + select STM32_HAVE_CAN1 + +config STM32F1_USBACCESSLINE + bool + default n + select STM32_HAVE_USBDEV + select STM32_HAVE_FSMC + select STM32_HAVE_USART3 + select STM32_HAVE_SPI2 + + +config STM32F1_MEDIUMPLUSDENSITY + bool + default n + +config STM32F1_HIGHDENSITY + bool + default n + select STM32_HIGHDENSITY + select STM32_HAVE_FSMC + select STM32_HAVE_USART3 + select STM32_HAVE_UART4 + select STM32_HAVE_UART5 + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM5 + select STM32_HAVE_TIM6 + select STM32_HAVE_TIM7 + select STM32_HAVE_TIM8 + select STM32_HAVE_ADC2 + select STM32_HAVE_ADC3 + select STM32_HAVE_CAN1 + +config STM32F1_MEDIUMDENSITY + bool + default n + select STM32_MEDIUMDENSITY + select STM32_HAVE_USART3 + select STM32_HAVE_UART4 + select STM32_HAVE_UART5 + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM5 + select STM32_HAVE_TIM6 + select STM32_HAVE_TIM7 + select STM32_HAVE_TIM8 + select STM32_HAVE_ADC2 + select STM32_HAVE_ADC3 + select STM32_HAVE_CAN1 + +config STM32F1_LOWDENSITY + bool + default n + select STM32_LOWDENSITY + select STM32_HAVE_USART3 + select STM32_HAVE_UART4 + select STM32_HAVE_UART5 + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM5 + select STM32_HAVE_TIM6 + select STM32_HAVE_TIM7 + select STM32_HAVE_TIM8 + select STM32_HAVE_ADC2 + select STM32_HAVE_CAN1 if !STM32F1_VALUELINE + +# Compatibility symbols kept private to STM32F1 selection. Existing driver +# code still keys off these historical names. + +config STM32_VALUELINE + bool + +config STM32_CONNECTIVITYLINE + bool + +config STM32_HIGHDENSITY + bool + +config STM32_MEDIUMDENSITY + bool + +config STM32_LOWDENSITY + bool + +source "arch/arm/src/stm32f1/Kconfig.pinmap" diff --git a/arch/arm/src/stm32f1/Kconfig.pinmap b/arch/arm/src/stm32f1/Kconfig.pinmap new file mode 100644 index 0000000000000..f04d44944be0f --- /dev/null +++ b/arch/arm/src/stm32f1/Kconfig.pinmap @@ -0,0 +1,182 @@ +menu "Alternate Pin Mapping" + depends on STM32_STM32F10XX + +choice + prompt "CAN1 Alternate Pin Mappings" + depends on STM32_STM32F10XX && STM32_CAN1 + default STM32_CAN1_NO_REMAP + +config STM32_CAN1_NO_REMAP + bool "No pin remapping" + +config STM32_CAN1_REMAP1 + bool "CAN1 alternate pin remapping #1" + +config STM32_CAN1_REMAP2 + bool "CAN1 alternate pin remapping #2" + +endchoice + +config STM32_CAN2_REMAP + bool "CAN2 Alternate Pin Mapping" + default n + depends on STM32F1_CONNECTIVITYLINE && STM32_CAN2 + +config STM32_CEC_REMAP + bool "CEC Alternate Pin Mapping" + default n + depends on STM32_STM32F10XX && STM32_CEC + +config STM32_ETH_REMAP + bool "Ethernet Alternate Pin Mapping" + default n + depends on STM32F1_CONNECTIVITYLINE && STM32_ETHMAC + +config STM32_I2C1_REMAP + bool "I2C1 Alternate Pin Mapping" + default n + depends on STM32_STM32F10XX && STM32_I2C1 + +config STM32_SPI1_REMAP + bool "SPI1 Alternate Pin Mapping" + default n + depends on STM32_STM32F10XX && STM32_SPI1 + +config STM32_SPI3_REMAP + bool "SPI3 Alternate Pin Mapping" + default n + depends on STM32_STM32F10XX && STM32_SPI3 && !STM32F1_VALUELINE + +config STM32_I2S3_REMAP + bool "I2S3 Alternate Pin Mapping" + default n + depends on STM32_STM32F10XX && STM32_I2S3 && !STM32F1_VALUELINE + +choice + prompt "TIM1 Alternate Pin Mappings" + depends on STM32_STM32F10XX && STM32_TIM1 + default STM32_TIM1_NO_REMAP + +config STM32_TIM1_NO_REMAP + bool "No pin remapping" + +config STM32_TIM1_FULL_REMAP + bool "Full pin remapping" + +config STM32_TIM1_PARTIAL_REMAP + bool "Partial pin remapping" + +endchoice + +choice + prompt "TIM2 Alternate Pin Mappings" + depends on STM32_STM32F10XX && STM32_TIM2 + default STM32_TIM2_NO_REMAP + +config STM32_TIM2_NO_REMAP + bool "No pin remapping" + +config STM32_TIM2_FULL_REMAP + bool "Full pin remapping" + +config STM32_TIM2_PARTIAL_REMAP_1 + bool "Partial pin remapping #1" + +config STM32_TIM2_PARTIAL_REMAP_2 + bool "Partial pin remapping #2" + +endchoice + +choice + prompt "TIM3 Alternate Pin Mappings" + depends on STM32_STM32F10XX && STM32_TIM3 + default STM32_TIM3_NO_REMAP + +config STM32_TIM3_NO_REMAP + bool "No pin remapping" + +config STM32_TIM3_FULL_REMAP + bool "Full pin remapping" + +config STM32_TIM3_PARTIAL_REMAP + bool "Partial pin remapping" + +endchoice + +config STM32_TIM4_REMAP + bool "TIM4 Alternate Pin Mapping" + default n + depends on STM32_STM32F10XX && STM32_TIM4 + +config STM32_TIM9_REMAP + bool "TIM9 Alternate Pin Mapping" + default n + depends on STM32_STM32F10XX && STM32_TIM9 + +config STM32_TIM10_REMAP + bool "TIM10 Alternate Pin Mapping" + default n + depends on STM32_STM32F10XX && STM32_TIM10 + +config STM32_TIM11_REMAP + bool "TIM11 Alternate Pin Mapping" + default n + depends on STM32_STM32F10XX && STM32_TIM11 + +config STM32_TIM12_REMAP + bool "TIM12 Alternate Pin Mapping" + default n + depends on STM32_STM32F10XX && STM32_TIM12 + +config STM32_TIM13_REMAP + bool "TIM13 Alternate Pin Mapping" + default n + depends on STM32_STM32F10XX && STM32_TIM13 + +config STM32_TIM14_REMAP + bool "TIM14 Alternate Pin Mapping" + default n + depends on STM32_STM32F10XX && STM32_TIM14 + +config STM32_TIM15_REMAP + bool "TIM15 Alternate Pin Mapping" + default n + depends on STM32_STM32F10XX && STM32_TIM15 + +config STM32_TIM16_REMAP + bool "TIM16 Alternate Pin Mapping" + default n + depends on STM32_STM32F10XX && STM32_TIM16 + +config STM32_TIM17_REMAP + bool "TIM17 Alternate Pin Mapping" + default n + depends on STM32_STM32F10XX && STM32_TIM17 + +config STM32_USART1_REMAP + bool "USART1 Alternate Pin Mapping" + default n + depends on STM32_STM32F10XX && STM32_USART1 + +config STM32_USART2_REMAP + bool "USART2 Alternate Pin Mapping" + default n + depends on STM32_STM32F10XX && STM32_USART2 + +choice + prompt "USART3 Alternate Pin Mappings" + depends on STM32_STM32F10XX && STM32_USART3 + default STM32_USART3_NO_REMAP + +config STM32_USART3_NO_REMAP + bool "No pin remapping" + +config STM32_USART3_FULL_REMAP + bool "Full pin remapping" + +config STM32_USART3_PARTIAL_REMAP + bool "Partial pin remapping" + +endchoice + +endmenu diff --git a/arch/arm/src/stm32f1/Make.defs b/arch/arm/src/stm32f1/Make.defs new file mode 100644 index 0000000000000..0f8a65ef5a865 --- /dev/null +++ b/arch/arm/src/stm32f1/Make.defs @@ -0,0 +1,27 @@ +############################################################################ +# arch/arm/src/stm32f1/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include armv7-m/Make.defs + +CHIP_CSRCS = stm32_rcc.c + +include common/stm32/Make.defs diff --git a/arch/arm/src/stm32f1/chip.h b/arch/arm/src/stm32f1/chip.h new file mode 100644 index 0000000000000..9f3e121b8db11 --- /dev/null +++ b/arch/arm/src/stm32f1/chip.h @@ -0,0 +1,59 @@ +/**************************************************************************** + * arch/arm/src/stm32f1/chip.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32F1_CHIP_H +#define __ARCH_ARM_SRC_STM32F1_CHIP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/* Include the chip capabilities file */ + +#include + +/* Include the chip interrupt definition file */ + +#include + +/* Include the chip memory map */ + +#include "hardware/stm32_memorymap.h" + +/* Include the chip pinmap */ + +#include "hardware/stm32_pinmap.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Provide the required number of peripheral interrupt vector + * definitions as * well. The definition STM32_IRQ_NEXTINTS simply comes + * from the chip-specific * IRQ header file included by arch/stm32/irq.h. + */ + +#define ARMV7M_PERIPHERAL_INTERRUPTS STM32_IRQ_NEXTINTS + +#endif /* __ARCH_ARM_SRC_STM32F1_CHIP_H */ diff --git a/arch/arm/src/stm32f1/hardware/stm32_memorymap.h b/arch/arm/src/stm32f1/hardware/stm32_memorymap.h new file mode 100644 index 0000000000000..027e14eaf9b69 --- /dev/null +++ b/arch/arm/src/stm32f1/hardware/stm32_memorymap.h @@ -0,0 +1,17 @@ +/**************************************************************************** + * arch/arm/src/stm32f1/hardware/stm32_memorymap.h + * + * SPDX-License-Identifier: Apache-2.0 + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32F1_HARDWARE_STM32_MEMORYMAP_H +#define __ARCH_ARM_SRC_STM32F1_HARDWARE_STM32_MEMORYMAP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "hardware/stm32f10xxx_memorymap.h" + +#endif /* __ARCH_ARM_SRC_STM32F1_HARDWARE_STM32_MEMORYMAP_H */ diff --git a/arch/arm/src/stm32f1/hardware/stm32_pinmap.h b/arch/arm/src/stm32f1/hardware/stm32_pinmap.h new file mode 100644 index 0000000000000..ed4b8e68f0f51 --- /dev/null +++ b/arch/arm/src/stm32f1/hardware/stm32_pinmap.h @@ -0,0 +1,46 @@ +/**************************************************************************** + * arch/arm/src/stm32f1/hardware/stm32_pinmap.h + * + * SPDX-License-Identifier: Apache-2.0 + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32F1_HARDWARE_STM32_PINMAP_H +#define __ARCH_ARM_SRC_STM32F1_HARDWARE_STM32_PINMAP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#if defined(CONFIG_STM32_VALUELINE) +# include "hardware/stm32f100_pinmap.h" +#elif defined(CONFIG_ARCH_CHIP_STM32F102CB) +# include "hardware/stm32f102_pinmap.h" +#elif defined(CONFIG_ARCH_CHIP_STM32F103C4) || \ + defined(CONFIG_ARCH_CHIP_STM32F103C8) || \ + defined(CONFIG_ARCH_CHIP_STM32F103CB) +# include "hardware/stm32f103c_pinmap.h" +#elif defined(CONFIG_ARCH_CHIP_STM32F103RB) || \ + defined(CONFIG_ARCH_CHIP_STM32F103RC) || \ + defined(CONFIG_ARCH_CHIP_STM32F103RD) || \ + defined(CONFIG_ARCH_CHIP_STM32F103RE) || \ + defined(CONFIG_ARCH_CHIP_STM32F103RG) +# include "hardware/stm32f103r_pinmap.h" +#elif defined(CONFIG_ARCH_CHIP_STM32F103VC) || \ + defined(CONFIG_ARCH_CHIP_STM32F103VE) +# include "hardware/stm32f103v_pinmap.h" +#elif defined(CONFIG_ARCH_CHIP_STM32F103ZE) +# include "hardware/stm32f103z_pinmap.h" +#elif defined(CONFIG_ARCH_CHIP_STM32F105VB) +# include "hardware/stm32f105v_pinmap.h" +#elif defined(CONFIG_ARCH_CHIP_STM32F105RB) +# include "hardware/stm32f105r_pinmap.h" +#elif defined(CONFIG_ARCH_CHIP_STM32F107VC) +# include "hardware/stm32f107v_pinmap.h" +#else +# error "Unsupported STM32F1 pin map" +#endif + +#endif /* __ARCH_ARM_SRC_STM32F1_HARDWARE_STM32_PINMAP_H */ diff --git a/arch/arm/src/stm32/hardware/stm32f100_pinmap.h b/arch/arm/src/stm32f1/hardware/stm32f100_pinmap.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32f100_pinmap.h rename to arch/arm/src/stm32f1/hardware/stm32f100_pinmap.h index e50de324c47dd..56174b632211a 100644 --- a/arch/arm/src/stm32/hardware/stm32f100_pinmap.h +++ b/arch/arm/src/stm32f1/hardware/stm32f100_pinmap.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32f100_pinmap.h + * arch/arm/src/stm32f1/hardware/stm32f100_pinmap.h * * SPDX-License-Identifier: BSD-3-Clause * SPDX-FileCopyrightText: 2009 Gregory Nutt. All rights reserved. diff --git a/arch/arm/src/stm32/hardware/stm32f102_pinmap.h b/arch/arm/src/stm32f1/hardware/stm32f102_pinmap.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32f102_pinmap.h rename to arch/arm/src/stm32f1/hardware/stm32f102_pinmap.h index a54ff133eab24..8d85291705b77 100644 --- a/arch/arm/src/stm32/hardware/stm32f102_pinmap.h +++ b/arch/arm/src/stm32f1/hardware/stm32f102_pinmap.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32f102_pinmap.h + * arch/arm/src/stm32f1/hardware/stm32f102_pinmap.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/hardware/stm32f103c_pinmap.h b/arch/arm/src/stm32f1/hardware/stm32f103c_pinmap.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32f103c_pinmap.h rename to arch/arm/src/stm32f1/hardware/stm32f103c_pinmap.h index fa8052df02656..b11796ad7bd29 100644 --- a/arch/arm/src/stm32/hardware/stm32f103c_pinmap.h +++ b/arch/arm/src/stm32f1/hardware/stm32f103c_pinmap.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32f103c_pinmap.h + * arch/arm/src/stm32f1/hardware/stm32f103c_pinmap.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/hardware/stm32f103r_pinmap.h b/arch/arm/src/stm32f1/hardware/stm32f103r_pinmap.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32f103r_pinmap.h rename to arch/arm/src/stm32f1/hardware/stm32f103r_pinmap.h index 0f5596cd8b0a9..7ad6aa3e63bc0 100644 --- a/arch/arm/src/stm32/hardware/stm32f103r_pinmap.h +++ b/arch/arm/src/stm32f1/hardware/stm32f103r_pinmap.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32f103r_pinmap.h + * arch/arm/src/stm32f1/hardware/stm32f103r_pinmap.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/hardware/stm32f103v_pinmap.h b/arch/arm/src/stm32f1/hardware/stm32f103v_pinmap.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32f103v_pinmap.h rename to arch/arm/src/stm32f1/hardware/stm32f103v_pinmap.h index 8d15dd04fd4f6..3074b6fec4398 100644 --- a/arch/arm/src/stm32/hardware/stm32f103v_pinmap.h +++ b/arch/arm/src/stm32f1/hardware/stm32f103v_pinmap.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32f103v_pinmap.h + * arch/arm/src/stm32f1/hardware/stm32f103v_pinmap.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/hardware/stm32f103z_pinmap.h b/arch/arm/src/stm32f1/hardware/stm32f103z_pinmap.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32f103z_pinmap.h rename to arch/arm/src/stm32f1/hardware/stm32f103z_pinmap.h index 95a21a58da3bb..1af5f6ef0d15f 100644 --- a/arch/arm/src/stm32/hardware/stm32f103z_pinmap.h +++ b/arch/arm/src/stm32f1/hardware/stm32f103z_pinmap.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32f103z_pinmap.h + * arch/arm/src/stm32f1/hardware/stm32f103z_pinmap.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/hardware/stm32f105r_pinmap.h b/arch/arm/src/stm32f1/hardware/stm32f105r_pinmap.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32f105r_pinmap.h rename to arch/arm/src/stm32f1/hardware/stm32f105r_pinmap.h index 5701c4af5030a..5956145aa28cb 100644 --- a/arch/arm/src/stm32/hardware/stm32f105r_pinmap.h +++ b/arch/arm/src/stm32f1/hardware/stm32f105r_pinmap.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32f105r_pinmap.h + * arch/arm/src/stm32f1/hardware/stm32f105r_pinmap.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/hardware/stm32f105v_pinmap.h b/arch/arm/src/stm32f1/hardware/stm32f105v_pinmap.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32f105v_pinmap.h rename to arch/arm/src/stm32f1/hardware/stm32f105v_pinmap.h index a0f07baaa035c..b4ce3444d97ed 100644 --- a/arch/arm/src/stm32/hardware/stm32f105v_pinmap.h +++ b/arch/arm/src/stm32f1/hardware/stm32f105v_pinmap.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32f105v_pinmap.h + * arch/arm/src/stm32f1/hardware/stm32f105v_pinmap.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/hardware/stm32f107v_pinmap.h b/arch/arm/src/stm32f1/hardware/stm32f107v_pinmap.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32f107v_pinmap.h rename to arch/arm/src/stm32f1/hardware/stm32f107v_pinmap.h index e034bf01647a5..7433722c087a8 100644 --- a/arch/arm/src/stm32/hardware/stm32f107v_pinmap.h +++ b/arch/arm/src/stm32f1/hardware/stm32f107v_pinmap.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32f107v_pinmap.h + * arch/arm/src/stm32f1/hardware/stm32f107v_pinmap.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/hardware/stm32f10xxx_gpio.h b/arch/arm/src/stm32f1/hardware/stm32f10xxx_gpio.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32f10xxx_gpio.h rename to arch/arm/src/stm32f1/hardware/stm32f10xxx_gpio.h index 9dd7264b6f1f5..4ba272eebf596 100644 --- a/arch/arm/src/stm32/hardware/stm32f10xxx_gpio.h +++ b/arch/arm/src/stm32f1/hardware/stm32f10xxx_gpio.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32f10xxx_gpio.h + * arch/arm/src/stm32f1/hardware/stm32f10xxx_gpio.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/hardware/stm32f10xxx_memorymap.h b/arch/arm/src/stm32f1/hardware/stm32f10xxx_memorymap.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32f10xxx_memorymap.h rename to arch/arm/src/stm32f1/hardware/stm32f10xxx_memorymap.h index c11e00c13b6fa..ec755efb47b86 100644 --- a/arch/arm/src/stm32/hardware/stm32f10xxx_memorymap.h +++ b/arch/arm/src/stm32f1/hardware/stm32f10xxx_memorymap.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32f10xxx_memorymap.h + * arch/arm/src/stm32f1/hardware/stm32f10xxx_memorymap.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/hardware/stm32f10xxx_rcc.h b/arch/arm/src/stm32f1/hardware/stm32f10xxx_rcc.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32f10xxx_rcc.h rename to arch/arm/src/stm32f1/hardware/stm32f10xxx_rcc.h index 457fea592df83..54828425c3c5e 100644 --- a/arch/arm/src/stm32/hardware/stm32f10xxx_rcc.h +++ b/arch/arm/src/stm32f1/hardware/stm32f10xxx_rcc.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32f10xxx_rcc.h + * arch/arm/src/stm32f1/hardware/stm32f10xxx_rcc.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32f1/stm32.h b/arch/arm/src/stm32f1/stm32.h new file mode 100644 index 0000000000000..5707089d7b890 --- /dev/null +++ b/arch/arm/src/stm32f1/stm32.h @@ -0,0 +1,69 @@ +/**************************************************************************** + * arch/arm/src/stm32f1/stm32.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32_STM32_H +#define __ARCH_ARM_SRC_STM32_STM32_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include +#include + +#include "arm_internal.h" + +/* Peripherals **************************************************************/ + +#include "chip.h" +#include "stm32_adc.h" +#include "stm32_can.h" +#include "stm32_comp.h" +#include "stm32_dbgmcu.h" +#include "stm32_dma.h" +#include "stm32_dac_m3m4_v1.h" +#include "stm32_exti.h" +#include "stm32_flash.h" +#include "stm32_fmc_m3m4_v1.h" +#include "stm32_fsmc_m3m4_v1.h" +#include "stm32_gpio.h" +#include "stm32_i2c.h" +#include "stm32_ltdc_m3m4_v1.h" +#include "stm32_opamp_m3m4_v1.h" +#include "stm32_pwr.h" +#include "stm32_rcc.h" +#include "stm32_rtc.h" +#include "stm32_sdio_m3m4_v1.h" +#include "stm32_spi.h" +#include "stm32_i2s.h" +#include "stm32_tim.h" +#include "stm32_uart.h" +#if defined(CONFIG_USBDEV) && defined(CONFIG_STM32_USB) +# include "stm32_usbdev.h" +#endif +#include "stm32_wdg.h" +#include "stm32_lowputc.h" +#include "stm32_eth_m3m4_v1.h" + +#endif /* __ARCH_ARM_SRC_STM32_STM32_H */ diff --git a/arch/arm/src/stm32f1/stm32_rcc.c b/arch/arm/src/stm32f1/stm32_rcc.c new file mode 100644 index 0000000000000..f78d3e0a1897b --- /dev/null +++ b/arch/arm/src/stm32f1/stm32_rcc.c @@ -0,0 +1,234 @@ +/**************************************************************************** + * arch/arm/src/stm32f1/stm32_rcc.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include + +#include "arm_internal.h" +#include "chip.h" +#include "stm32_gpio.h" +#include "stm32_rcc.h" +#include "stm32_rtc.h" +#include "stm32_flash.h" +#include "stm32.h" +#include "stm32_waste.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1, + "Configure BOARD_LOOPSPERMSEC to non-default value."); + +/* Allow up to 100 milliseconds for the high speed clock to become ready. + * that is a very long delay, but if the clock does not become ready we are + * hosed anyway. + */ + +#define HSERDY_TIMEOUT (100 * CONFIG_BOARD_LOOPSPERMSEC) + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/* Include chip-specific clocking initialization logic */ + +#include "stm32f10xxx_rcc.c" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#if defined(CONFIG_STM32_STM32L15XX) +# define STM32_RCC_XXX STM32_RCC_CSR +# define RCC_XXX_YYYRST RCC_CSR_RTCRST +#else +# define STM32_RCC_XXX STM32_RCC_BDCR +# define RCC_XXX_YYYRST RCC_BDCR_BDRST +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: rcc_resetbkp + * + * Description: + * The RTC needs to reset the Backup Domain to change RTCSEL and resetting + * the Backup Domain renders to disabling the LSE as consequence. + * In order to avoid resetting the Backup Domain when we already + * configured LSE we will reset the Backup Domain early (here). + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +#if defined(CONFIG_STM32_RTC) && defined(CONFIG_STM32_PWR) && !defined(CONFIG_STM32_STM32F10XX) +static inline void rcc_resetbkp(void) +{ + uint32_t regval; + + /* Check if the RTC is already configured */ + + stm32_pwr_initbkp(false); + + regval = getreg32(RTC_MAGIC_REG); + if (regval != RTC_MAGIC && regval != RTC_MAGIC_TIME_SET) + { + stm32_pwr_enablebkp(true); + + /* We might be changing RTCSEL - to ensure such changes work, we must + * reset the backup domain (having backed up the RTC_MAGIC token) + */ + + modifyreg32(STM32_RCC_XXX, 0, RCC_XXX_YYYRST); + modifyreg32(STM32_RCC_XXX, RCC_XXX_YYYRST, 0); + + stm32_pwr_enablebkp(false); + } +} +#else +# define rcc_resetbkp() +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_clockconfig + * + * Description: + * Called to establish the clock settings based on the values in board.h. + * This function (by default) will reset most everything, enable the PLL, + * and enable peripheral clocking for all peripherals enabled in the NuttX + * configuration file. + * + * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then clocking + * will be enabled by an externally provided, board-specific function + * called stm32_board_clockconfig(). + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void stm32_clockconfig(void) +{ + /* Make sure that we are starting in the reset state */ + + rcc_reset(); + + /* Reset backup domain if appropriate */ + + rcc_resetbkp(); + +#if defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) + + /* Invoke Board Custom Clock Configuration */ + + stm32_board_clockconfig(); + +#else + + /* Invoke standard, fixed clock configuration based on definitions + * in board.h + */ + + stm32_stdclockconfig(); + +#endif + + /* Enable peripheral clocking */ + + rcc_enableperipherals(); + +#ifdef CONFIG_STM32_SYSCFG_IOCOMPENSATION + /* Enable I/O Compensation */ + + stm32_iocompensation(); +#endif +} + +/**************************************************************************** + * Name: stm32_clockenable + * + * Description: + * Re-enable the clock and restore the clock settings based on settings + * in board.h. This function is only available to support low-power + * modes of operation: When re-awakening from deep-sleep modes, it is + * necessary to re-enable/re-start the PLL + * + * This functional performs a subset of the operations performed by + * stm32_clockconfig(): It does not reset any devices, and it does not + * reset the currently enabled peripheral clocks. + * + * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then clocking + * will be enabled by an externally provided, board-specific function + * called stm32_board_clockconfig(). + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_PM +void stm32_clockenable(void) +{ +#if defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) + + /* Invoke Board Custom Clock Configuration */ + + stm32_board_clockconfig(); + +#else + + /* Invoke standard, fixed clock configuration based on definitions + * in board.h + */ + + stm32_stdclockconfig(); + +#endif +} +#endif diff --git a/arch/arm/src/stm32/stm32f10xxx_rcc.c b/arch/arm/src/stm32f1/stm32f10xxx_rcc.c similarity index 99% rename from arch/arm/src/stm32/stm32f10xxx_rcc.c rename to arch/arm/src/stm32f1/stm32f10xxx_rcc.c index fa8c0debe6946..8b2604a55a22b 100644 --- a/arch/arm/src/stm32/stm32f10xxx_rcc.c +++ b/arch/arm/src/stm32f1/stm32f10xxx_rcc.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32f10xxx_rcc.c + * arch/arm/src/stm32f1/stm32f10xxx_rcc.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32f2/CMakeLists.txt b/arch/arm/src/stm32f2/CMakeLists.txt new file mode 100644 index 0000000000000..79b7a47029770 --- /dev/null +++ b/arch/arm/src/stm32f2/CMakeLists.txt @@ -0,0 +1,28 @@ +# ############################################################################## +# arch/arm/src/stm32f2/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(SRCS) + +list(APPEND SRCS stm32_rcc.c) + +target_sources(arch PRIVATE ${SRCS}) +add_subdirectory(${NUTTX_DIR}/arch/arm/src/common/stm32 stm32_common) diff --git a/arch/arm/src/stm32f2/Kconfig b/arch/arm/src/stm32f2/Kconfig new file mode 100644 index 0000000000000..139cff56f9059 --- /dev/null +++ b/arch/arm/src/stm32f2/Kconfig @@ -0,0 +1,178 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# +comment "STM32 F2 configuration" + +if ARCH_CHIP_STM32F2 + +choice + prompt "STM32F2 Chip Selection" + depends on ARCH_CHIP_STM32F2 + +config ARCH_CHIP_STM32F205RG + bool "STM32F205RG" + select STM32_STM32F20XX + select STM32_STM32F205 + +config ARCH_CHIP_STM32F207VC + bool "STM32F207VC" + select STM32_STM32F20XX + select STM32_STM32F207 + +config ARCH_CHIP_STM32F207VE + bool "STM32F207VE" + select STM32_STM32F20XX + select STM32_STM32F207 + +config ARCH_CHIP_STM32F207VF + bool "STM32F207VF" + select STM32_STM32F20XX + select STM32_STM32F207 + +config ARCH_CHIP_STM32F207VG + bool "STM32F207VG" + select STM32_STM32F20XX + select STM32_STM32F207 + +config ARCH_CHIP_STM32F207IC + bool "STM32F207IC" + select STM32_STM32F20XX + select STM32_STM32F207 + +config ARCH_CHIP_STM32F207IE + bool "STM32F207IE" + select STM32_STM32F20XX + select STM32_STM32F207 + +config ARCH_CHIP_STM32F207IF + bool "STM32F207IF" + select STM32_STM32F20XX + select STM32_STM32F207 + +config ARCH_CHIP_STM32F207IG + bool "STM32F207IG" + select STM32_STM32F20XX + select STM32_STM32F207 + +config ARCH_CHIP_STM32F207ZC + bool "STM32F207ZC" + select STM32_STM32F20XX + select STM32_STM32F207 + +config ARCH_CHIP_STM32F207ZE + bool "STM32F207ZE" + select STM32_STM32F20XX + select STM32_STM32F207 + +config ARCH_CHIP_STM32F207ZF + bool "STM32F207ZF" + select STM32_STM32F20XX + select STM32_STM32F207 + +config ARCH_CHIP_STM32F207ZG + bool "STM32F207ZG" + select STM32_STM32F20XX + select STM32_STM32F207 + +endchoice + +endif + +config STM32_STM32F20XX + bool + default n + select STM32_HAVE_DMA1 + select STM32_HAVE_DMA2 + select ARCH_CORTEXM3 + select STM32_HAVE_DCMI + select STM32_HAVE_USART1 + select STM32_HAVE_USART2 + select STM32_HAVE_FLASH_ICACHE + select STM32_HAVE_FLASH_DCACHE + select STM32_HAVE_CRYP + select STM32_HAVE_HASH + select STM32_HAVE_I2C1 + select STM32_HAVE_OTGFS + select STM32_HAVE_OTGHS + select STM32_HAVE_SPI1 + select STM32_HAVE_USART3 + select STM32_HAVE_UART4 + select STM32_HAVE_UART5 + select STM32_HAVE_USART6 + select STM32_HAVE_SYSCFG + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM3 + select STM32_HAVE_TIM4 + select STM32_HAVE_TIM5 + select STM32_HAVE_TIM6 + select STM32_HAVE_TIM7 + select STM32_HAVE_TIM8 + select STM32_HAVE_TIM9 + select STM32_HAVE_TIM10 + select STM32_HAVE_TIM11 + select STM32_HAVE_TIM12 + select STM32_HAVE_TIM13 + select STM32_HAVE_TIM14 + select STM32_HAVE_ADC2 + select STM32_HAVE_ADC3 + select STM32_HAVE_DAC1 + select STM32_HAVE_I2C2 + select STM32_HAVE_I2C3 + select STM32_HAVE_CAN1 + select STM32_HAVE_CAN2 + select STM32_HAVE_RNG + select STM32_HAVE_SPI2 + select STM32_HAVE_SPI3 + select STM32_HAVE_IOCOMPENSATION + select STM32_HAVE_IP_AES_M3M4_V1 if STM32_HAVE_AES + select STM32_HAVE_IP_BBSRAM_M3M4_V1 + select STM32_HAVE_IP_BKP_M3M4_V1 + select STM32_HAVE_IP_CAN_BXCAN_M3M4_V1 + select STM32_HAVE_IP_CCM_M3M4_V1 if STM32_HAVE_CCM + select STM32_HAVE_IP_CRYPTO_M3M4_V1 + select STM32_HAVE_IP_DBGMCU_M3M4_V2 + select STM32_HAVE_IP_ADC_M3M4_V1 + select STM32_HAVE_COMMON_FOC + select STM32_HAVE_IP_DCMI_V1 + select STM32_HAVE_IP_DAC_M3M4_V1 + select STM32_HAVE_IP_DFUMODE_M3M4_V1 + select STM32_HAVE_IP_DMA_V2 + select STM32_HAVE_IP_DMA_V2_STREAM + select STM32_HAVE_ETHERNET if STM32_HAVE_ETHMAC + select STM32_HAVE_IP_EXTI_V1 + select STM32_HAVE_IP_ETHMAC_M3M4_V1 if STM32_HAVE_ETHMAC + select STM32_HAVE_IP_FLASH_M3M4_V1 + select STM32_HAVE_IP_FLASH_M3M4_F2F4 + select STM32_HAVE_IP_FMC_M3M4_V1 if STM32_HAVE_FMC + select STM32_HAVE_IP_FREERUN_M3M4_V1 + select STM32_HAVE_IP_FSMC_M3M4_V1 if STM32_HAVE_FSMC + select STM32_HAVE_IP_GPIO_M3M4_V1 + select STM32_HAVE_IP_I2C_M3M4_V1 + select STM32_HAVE_IP_I2S_M3M4_V1 + select STM32_HAVE_IP_ONESHOT_M3M4_V1 + select STM32_HAVE_IP_OTGFS_M3M4_V1 if STM32_HAVE_OTGFS + select STM32_HAVE_IP_OTGHS_M3M4_V1 + select STM32_HAVE_IP_PWR_M3M4_V1 + select STM32_HAVE_IP_RNG_M3M4_V1 if STM32_HAVE_RNG + select STM32_HAVE_IP_RTC_M3M4_V1 + select STM32_HAVE_IP_RTCC_M3M4_V1 + select STM32_HAVE_IP_SDIO_M3M4_V1 + select STM32_HAVE_IP_SPI_V2 + select STM32_HAVE_IP_SYSCFG_M3M4_V1 + select STM32_HAVE_IP_TIMERS_M3M4_V1 + select STM32_HAVE_IP_USART_V2 + select STM32_HAVE_IP_USBDEV_M3M4_V1 if STM32_HAVE_USBDEV + select STM32_HAVE_IP_USBFS_M3M4_V1 if STM32_HAVE_USBFS + select STM32_HAVE_IP_WDG_M3M4_V1 + +config STM32_STM32F205 + bool + default n + +config STM32_STM32F207 + bool + default n + select STM32_HAVE_FSMC + select STM32_HAVE_ETHMAC diff --git a/arch/arm/src/stm32f2/Make.defs b/arch/arm/src/stm32f2/Make.defs new file mode 100644 index 0000000000000..b98256025f3e6 --- /dev/null +++ b/arch/arm/src/stm32f2/Make.defs @@ -0,0 +1,27 @@ +############################################################################ +# arch/arm/src/stm32f2/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include armv7-m/Make.defs + +CHIP_CSRCS = stm32_rcc.c + +include common/stm32/Make.defs diff --git a/arch/arm/src/stm32f2/chip.h b/arch/arm/src/stm32f2/chip.h new file mode 100644 index 0000000000000..4b555d13fb72a --- /dev/null +++ b/arch/arm/src/stm32f2/chip.h @@ -0,0 +1,59 @@ +/**************************************************************************** + * arch/arm/src/stm32f2/chip.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32F2_CHIP_H +#define __ARCH_ARM_SRC_STM32F2_CHIP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/* Include the chip capabilities file */ + +#include + +/* Include the chip interrupt definition file */ + +#include + +/* Include the chip memory map */ + +#include "hardware/stm32_memorymap.h" + +/* Include the chip pinmap */ + +#include "hardware/stm32_pinmap.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Provide the required number of peripheral interrupt vector + * definitions as * well. The definition STM32_IRQ_NEXTINTS simply comes + * from the chip-specific * IRQ header file included by arch/stm32/irq.h. + */ + +#define ARMV7M_PERIPHERAL_INTERRUPTS STM32_IRQ_NEXTINTS + +#endif /* __ARCH_ARM_SRC_STM32F2_CHIP_H */ diff --git a/arch/arm/src/stm32f2/hardware/stm32_memorymap.h b/arch/arm/src/stm32f2/hardware/stm32_memorymap.h new file mode 100644 index 0000000000000..4037ce463e154 --- /dev/null +++ b/arch/arm/src/stm32f2/hardware/stm32_memorymap.h @@ -0,0 +1,17 @@ +/**************************************************************************** + * arch/arm/src/stm32f2/hardware/stm32_memorymap.h + * + * SPDX-License-Identifier: Apache-2.0 + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32F2_HARDWARE_STM32_MEMORYMAP_H +#define __ARCH_ARM_SRC_STM32F2_HARDWARE_STM32_MEMORYMAP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "hardware/stm32f20xxx_memorymap.h" + +#endif /* __ARCH_ARM_SRC_STM32F2_HARDWARE_STM32_MEMORYMAP_H */ diff --git a/arch/arm/src/stm32f2/hardware/stm32_pinmap.h b/arch/arm/src/stm32f2/hardware/stm32_pinmap.h new file mode 100644 index 0000000000000..e9a0e492b35ef --- /dev/null +++ b/arch/arm/src/stm32f2/hardware/stm32_pinmap.h @@ -0,0 +1,17 @@ +/**************************************************************************** + * arch/arm/src/stm32f2/hardware/stm32_pinmap.h + * + * SPDX-License-Identifier: Apache-2.0 + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32F2_HARDWARE_STM32_PINMAP_H +#define __ARCH_ARM_SRC_STM32F2_HARDWARE_STM32_PINMAP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "hardware/stm32f20xxx_pinmap.h" + +#endif /* __ARCH_ARM_SRC_STM32F2_HARDWARE_STM32_PINMAP_H */ diff --git a/arch/arm/src/stm32/hardware/stm32f20xxx_gpio.h b/arch/arm/src/stm32f2/hardware/stm32f20xxx_gpio.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32f20xxx_gpio.h rename to arch/arm/src/stm32f2/hardware/stm32f20xxx_gpio.h index ebb059482823f..32ab85cc3dfa0 100644 --- a/arch/arm/src/stm32/hardware/stm32f20xxx_gpio.h +++ b/arch/arm/src/stm32f2/hardware/stm32f20xxx_gpio.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32f20xxx_gpio.h + * arch/arm/src/stm32f2/hardware/stm32f20xxx_gpio.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/hardware/stm32f20xxx_memorymap.h b/arch/arm/src/stm32f2/hardware/stm32f20xxx_memorymap.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32f20xxx_memorymap.h rename to arch/arm/src/stm32f2/hardware/stm32f20xxx_memorymap.h index 189e5a7a0814a..d55645a1ac50f 100644 --- a/arch/arm/src/stm32/hardware/stm32f20xxx_memorymap.h +++ b/arch/arm/src/stm32f2/hardware/stm32f20xxx_memorymap.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32f20xxx_memorymap.h + * arch/arm/src/stm32f2/hardware/stm32f20xxx_memorymap.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/hardware/stm32f20xxx_pinmap.h b/arch/arm/src/stm32f2/hardware/stm32f20xxx_pinmap.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32f20xxx_pinmap.h rename to arch/arm/src/stm32f2/hardware/stm32f20xxx_pinmap.h index aa7f4da6bfb45..544806fd18111 100644 --- a/arch/arm/src/stm32/hardware/stm32f20xxx_pinmap.h +++ b/arch/arm/src/stm32f2/hardware/stm32f20xxx_pinmap.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32f20xxx_pinmap.h + * arch/arm/src/stm32f2/hardware/stm32f20xxx_pinmap.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/hardware/stm32f20xxx_rcc.h b/arch/arm/src/stm32f2/hardware/stm32f20xxx_rcc.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32f20xxx_rcc.h rename to arch/arm/src/stm32f2/hardware/stm32f20xxx_rcc.h index c447c70bf6a54..31af35f07a1bf 100644 --- a/arch/arm/src/stm32/hardware/stm32f20xxx_rcc.h +++ b/arch/arm/src/stm32f2/hardware/stm32f20xxx_rcc.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32f20xxx_rcc.h + * arch/arm/src/stm32f2/hardware/stm32f20xxx_rcc.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/hardware/stm32f20xxx_syscfg.h b/arch/arm/src/stm32f2/hardware/stm32f20xxx_syscfg.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32f20xxx_syscfg.h rename to arch/arm/src/stm32f2/hardware/stm32f20xxx_syscfg.h index 954c04663318d..c4ad192e1ee00 100644 --- a/arch/arm/src/stm32/hardware/stm32f20xxx_syscfg.h +++ b/arch/arm/src/stm32f2/hardware/stm32f20xxx_syscfg.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32f20xxx_syscfg.h + * arch/arm/src/stm32f2/hardware/stm32f20xxx_syscfg.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32f2/stm32.h b/arch/arm/src/stm32f2/stm32.h new file mode 100644 index 0000000000000..9069ebcbca61e --- /dev/null +++ b/arch/arm/src/stm32f2/stm32.h @@ -0,0 +1,69 @@ +/**************************************************************************** + * arch/arm/src/stm32f2/stm32.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32_STM32_H +#define __ARCH_ARM_SRC_STM32_STM32_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include +#include + +#include "arm_internal.h" + +/* Peripherals **************************************************************/ + +#include "chip.h" +#include "stm32_adc.h" +#include "stm32_can.h" +#include "stm32_comp.h" +#include "stm32_dbgmcu.h" +#include "stm32_dma.h" +#include "stm32_dac_m3m4_v1.h" +#include "stm32_exti.h" +#include "stm32_flash.h" +#include "stm32_fmc_m3m4_v1.h" +#include "stm32_fsmc_m3m4_v1.h" +#include "stm32_gpio.h" +#include "stm32_i2c.h" +#include "stm32_ltdc_m3m4_v1.h" +#include "stm32_opamp_m3m4_v1.h" +#include "stm32_pwr.h" +#include "stm32_rcc.h" +#include "stm32_rtc.h" +#include "stm32_sdio_m3m4_v1.h" +#include "stm32_spi.h" +#include "stm32_i2s.h" +#include "stm32_tim.h" +#include "stm32_uart.h" +#if defined(CONFIG_USBDEV) && defined(CONFIG_STM32_USB) +# include "stm32_usbdev.h" +#endif +#include "stm32_wdg.h" +#include "stm32_lowputc.h" +#include "stm32_eth_m3m4_v1.h" + +#endif /* __ARCH_ARM_SRC_STM32_STM32_H */ diff --git a/arch/arm/src/stm32f2/stm32_rcc.c b/arch/arm/src/stm32f2/stm32_rcc.c new file mode 100644 index 0000000000000..7452375136a26 --- /dev/null +++ b/arch/arm/src/stm32f2/stm32_rcc.c @@ -0,0 +1,234 @@ +/**************************************************************************** + * arch/arm/src/stm32f2/stm32_rcc.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include + +#include "arm_internal.h" +#include "chip.h" +#include "stm32_gpio.h" +#include "stm32_rcc.h" +#include "stm32_rtc.h" +#include "stm32_flash.h" +#include "stm32.h" +#include "stm32_waste.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1, + "Configure BOARD_LOOPSPERMSEC to non-default value."); + +/* Allow up to 100 milliseconds for the high speed clock to become ready. + * that is a very long delay, but if the clock does not become ready we are + * hosed anyway. + */ + +#define HSERDY_TIMEOUT (100 * CONFIG_BOARD_LOOPSPERMSEC) + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/* Include chip-specific clocking initialization logic */ + +#include "stm32f20xxx_rcc.c" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#if defined(CONFIG_STM32_STM32L15XX) +# define STM32_RCC_XXX STM32_RCC_CSR +# define RCC_XXX_YYYRST RCC_CSR_RTCRST +#else +# define STM32_RCC_XXX STM32_RCC_BDCR +# define RCC_XXX_YYYRST RCC_BDCR_BDRST +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: rcc_resetbkp + * + * Description: + * The RTC needs to reset the Backup Domain to change RTCSEL and resetting + * the Backup Domain renders to disabling the LSE as consequence. + * In order to avoid resetting the Backup Domain when we already + * configured LSE we will reset the Backup Domain early (here). + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +#if defined(CONFIG_STM32_RTC) && defined(CONFIG_STM32_PWR) && !defined(CONFIG_STM32_STM32F10XX) +static inline void rcc_resetbkp(void) +{ + uint32_t regval; + + /* Check if the RTC is already configured */ + + stm32_pwr_initbkp(false); + + regval = getreg32(RTC_MAGIC_REG); + if (regval != RTC_MAGIC && regval != RTC_MAGIC_TIME_SET) + { + stm32_pwr_enablebkp(true); + + /* We might be changing RTCSEL - to ensure such changes work, we must + * reset the backup domain (having backed up the RTC_MAGIC token) + */ + + modifyreg32(STM32_RCC_XXX, 0, RCC_XXX_YYYRST); + modifyreg32(STM32_RCC_XXX, RCC_XXX_YYYRST, 0); + + stm32_pwr_enablebkp(false); + } +} +#else +# define rcc_resetbkp() +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_clockconfig + * + * Description: + * Called to establish the clock settings based on the values in board.h. + * This function (by default) will reset most everything, enable the PLL, + * and enable peripheral clocking for all peripherals enabled in the NuttX + * configuration file. + * + * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then clocking + * will be enabled by an externally provided, board-specific function + * called stm32_board_clockconfig(). + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void stm32_clockconfig(void) +{ + /* Make sure that we are starting in the reset state */ + + rcc_reset(); + + /* Reset backup domain if appropriate */ + + rcc_resetbkp(); + +#if defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) + + /* Invoke Board Custom Clock Configuration */ + + stm32_board_clockconfig(); + +#else + + /* Invoke standard, fixed clock configuration based on definitions + * in board.h + */ + + stm32_stdclockconfig(); + +#endif + + /* Enable peripheral clocking */ + + rcc_enableperipherals(); + +#ifdef CONFIG_STM32_SYSCFG_IOCOMPENSATION + /* Enable I/O Compensation */ + + stm32_iocompensation(); +#endif +} + +/**************************************************************************** + * Name: stm32_clockenable + * + * Description: + * Re-enable the clock and restore the clock settings based on settings + * in board.h. This function is only available to support low-power + * modes of operation: When re-awakening from deep-sleep modes, it is + * necessary to re-enable/re-start the PLL + * + * This functional performs a subset of the operations performed by + * stm32_clockconfig(): It does not reset any devices, and it does not + * reset the currently enabled peripheral clocks. + * + * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then clocking + * will be enabled by an externally provided, board-specific function + * called stm32_board_clockconfig(). + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_PM +void stm32_clockenable(void) +{ +#if defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) + + /* Invoke Board Custom Clock Configuration */ + + stm32_board_clockconfig(); + +#else + + /* Invoke standard, fixed clock configuration based on definitions + * in board.h + */ + + stm32_stdclockconfig(); + +#endif +} +#endif diff --git a/arch/arm/src/stm32/stm32f20xxx_rcc.c b/arch/arm/src/stm32f2/stm32f20xxx_rcc.c similarity index 99% rename from arch/arm/src/stm32/stm32f20xxx_rcc.c rename to arch/arm/src/stm32f2/stm32f20xxx_rcc.c index eb9e97e0ed8bf..30c8f34740dfb 100644 --- a/arch/arm/src/stm32/stm32f20xxx_rcc.c +++ b/arch/arm/src/stm32f2/stm32f20xxx_rcc.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32f20xxx_rcc.c + * arch/arm/src/stm32f2/stm32f20xxx_rcc.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32f3/CMakeLists.txt b/arch/arm/src/stm32f3/CMakeLists.txt new file mode 100644 index 0000000000000..36707fa80f197 --- /dev/null +++ b/arch/arm/src/stm32f3/CMakeLists.txt @@ -0,0 +1,28 @@ +# ############################################################################## +# arch/arm/src/stm32f3/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(SRCS) + +list(APPEND SRCS stm32_rcc.c) + +target_sources(arch PRIVATE ${SRCS}) +add_subdirectory(${NUTTX_DIR}/arch/arm/src/common/stm32 stm32_common) diff --git a/arch/arm/src/stm32f3/Kconfig b/arch/arm/src/stm32f3/Kconfig new file mode 100644 index 0000000000000..ace83673f311d --- /dev/null +++ b/arch/arm/src/stm32f3/Kconfig @@ -0,0 +1,611 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# +comment "STM32 F3 configuration" + +if ARCH_CHIP_STM32F3 + +choice + prompt "STM32F3 Chip Selection" + depends on ARCH_CHIP_STM32F3 + +config ARCH_CHIP_STM32F302K6 + bool "STM32F302K6" + select STM32_STM32F30XX + select STM32_STM32F302 + select STM32_HAVE_I2C3 + +config ARCH_CHIP_STM32F302K8 + bool "STM32F302K8" + select STM32_STM32F30XX + select STM32_STM32F302 + select STM32_HAVE_I2C3 + +config ARCH_CHIP_STM32F302C6 + bool "STM32F302C6" + select STM32_STM32F30XX + select STM32_STM32F302 + +config ARCH_CHIP_STM32F302C8 + bool "STM32F302C8" + select STM32_STM32F30XX + select STM32_STM32F302 + +config ARCH_CHIP_STM32F302R6 + bool "STM32F302R6" + select STM32_STM32F30XX + select STM32_STM32F302 + +config ARCH_CHIP_STM32F302R8 + bool "STM32F302R8" + select STM32_STM32F30XX + select STM32_STM32F302 + +config ARCH_CHIP_STM32F302CB + bool "STM32F302CB" + select STM32_STM32F30XX + select STM32_STM32F302 + select STM32_HAVE_ADC2 + select STM32_HAVE_USART3 + +config ARCH_CHIP_STM32F302CC + bool "STM32F302CC" + select STM32_STM32F30XX + select STM32_STM32F302 + select STM32_HAVE_ADC2 + select STM32_HAVE_USART3 + +config ARCH_CHIP_STM32F302RB + bool "STM32F302RB" + select STM32_STM32F30XX + select STM32_STM32F302 + select STM32_HAVE_ADC2 + select STM32_HAVE_USART3 + select STM32_HAVE_UART4 + select STM32_HAVE_UART5 + +config ARCH_CHIP_STM32F302RC + bool "STM32F302RC" + select STM32_STM32F30XX + select STM32_STM32F302 + select STM32_HAVE_ADC2 + select STM32_HAVE_USART3 + select STM32_HAVE_UART4 + select STM32_HAVE_UART5 + +config ARCH_CHIP_STM32F302VB + bool "STM32F302VB" + select STM32_STM32F30XX + select STM32_STM32F302 + select STM32_HAVE_ADC2 + select STM32_HAVE_USART3 + select STM32_HAVE_UART4 + select STM32_HAVE_UART5 + +config ARCH_CHIP_STM32F302VC + bool "STM32F302VC" + select STM32_STM32F30XX + select STM32_STM32F302 + select STM32_HAVE_ADC2 + select STM32_HAVE_USART3 + select STM32_HAVE_UART4 + select STM32_HAVE_UART5 + +config ARCH_CHIP_STM32F303K6 + bool "STM32F303K6" + select STM32_STM32F30XX + select STM32_STM32F303 + select STM32_HAVE_DAC2 + +config ARCH_CHIP_STM32F303K8 + bool "STM32F303K8" + select STM32_STM32F30XX + select STM32_STM32F303 + select STM32_HAVE_DAC2 + +config ARCH_CHIP_STM32F303C6 + bool "STM32F303C6" + select STM32_STM32F30XX + select STM32_STM32F303 + select STM32_HAVE_DAC2 + select STM32_HAVE_USART3 + +config ARCH_CHIP_STM32F303C8 + bool "STM32F303C8" + select STM32_STM32F30XX + select STM32_STM32F303 + select STM32_HAVE_DAC2 + select STM32_HAVE_USART3 + +config ARCH_CHIP_STM32F303CB + bool "STM32F303CB" + select STM32_STM32F30XX + select STM32_STM32F303 + select STM32_HAVE_ADC3 + select STM32_HAVE_ADC4 + select STM32_HAVE_I2C2 + select STM32_HAVE_SPI2 + select STM32_HAVE_SPI3 + select STM32_HAVE_TIM4 + select STM32_HAVE_TIM8 + select STM32_HAVE_USART3 + select STM32_HAVE_USBDEV + +config ARCH_CHIP_STM32F303CC + bool "STM32F303CC" + select STM32_STM32F30XX + select STM32_STM32F303 + select STM32_HAVE_ADC3 + select STM32_HAVE_ADC4 + select STM32_HAVE_I2C2 + select STM32_HAVE_SPI2 + select STM32_HAVE_SPI3 + select STM32_HAVE_TIM4 + select STM32_HAVE_TIM8 + select STM32_HAVE_USART3 + select STM32_HAVE_USBDEV + +config ARCH_CHIP_STM32F303RB + bool "STM32F303RB" + select STM32_STM32F30XX + select STM32_STM32F303 + select STM32_HAVE_ADC3 + select STM32_HAVE_ADC4 + select STM32_HAVE_I2C2 + select STM32_HAVE_SPI2 + select STM32_HAVE_SPI3 + select STM32_HAVE_TIM4 + select STM32_HAVE_TIM8 + select STM32_HAVE_USART3 + select STM32_HAVE_UART4 + select STM32_HAVE_UART5 + select STM32_HAVE_USBDEV + +config ARCH_CHIP_STM32F303RC + bool "STM32F303RC" + select STM32_STM32F30XX + select STM32_STM32F303 + select STM32_HAVE_ADC3 + select STM32_HAVE_ADC4 + select STM32_HAVE_I2C2 + select STM32_HAVE_SPI2 + select STM32_HAVE_SPI3 + select STM32_HAVE_TIM4 + select STM32_HAVE_TIM8 + select STM32_HAVE_USART3 + select STM32_HAVE_UART4 + select STM32_HAVE_UART5 + select STM32_HAVE_USBDEV + +config ARCH_CHIP_STM32F303RD + bool "STM32F303RD" + select STM32_STM32F30XX + select STM32_STM32F303 + select STM32_HAVE_ADC3 + select STM32_HAVE_ADC4 + select STM32_HAVE_I2C2 + select STM32_HAVE_I2C3 + select STM32_HAVE_SPI2 + select STM32_HAVE_SPI3 + select STM32_HAVE_SPI4 + select STM32_HAVE_TIM4 + select STM32_HAVE_TIM8 + select STM32_HAVE_USART3 + select STM32_HAVE_UART4 + select STM32_HAVE_UART5 + select STM32_HAVE_USBDEV + +config ARCH_CHIP_STM32F303RE + bool "STM32F303RE" + select STM32_STM32F30XX + select STM32_STM32F303 + select STM32_HAVE_ADC3 + select STM32_HAVE_ADC4 + select STM32_HAVE_I2C2 + select STM32_HAVE_I2C3 + select STM32_HAVE_SPI2 + select STM32_HAVE_SPI3 + select STM32_HAVE_SPI4 + select STM32_HAVE_TIM4 + select STM32_HAVE_TIM8 + select STM32_HAVE_USART3 + select STM32_HAVE_UART4 + select STM32_HAVE_UART5 + select STM32_HAVE_USBDEV + +config ARCH_CHIP_STM32F303VB + bool "STM32F303VB" + select STM32_STM32F30XX + select STM32_STM32F303 + select STM32_HAVE_ADC3 + select STM32_HAVE_ADC4 + select STM32_HAVE_I2C2 + select STM32_HAVE_SPI2 + select STM32_HAVE_SPI3 + select STM32_HAVE_TIM4 + select STM32_HAVE_TIM8 + select STM32_HAVE_USART3 + select STM32_HAVE_UART4 + select STM32_HAVE_UART5 + select STM32_HAVE_USBDEV + +config ARCH_CHIP_STM32F303VC + bool "STM32F303VC" + select STM32_STM32F30XX + select STM32_STM32F303 + select STM32_HAVE_ADC3 + select STM32_HAVE_ADC4 + select STM32_HAVE_I2C2 + select STM32_HAVE_SPI2 + select STM32_HAVE_SPI3 + select STM32_HAVE_TIM4 + select STM32_HAVE_TIM8 + select STM32_HAVE_USART3 + select STM32_HAVE_UART4 + select STM32_HAVE_UART5 + select STM32_HAVE_USBDEV + +config ARCH_CHIP_STM32F303VD + bool "STM32F303VD" + select STM32_STM32F30XX + select STM32_STM32F303 + select STM32_HAVE_ADC3 + select STM32_HAVE_ADC4 + select STM32_HAVE_USART3 + +config ARCH_CHIP_STM32F303VE + bool "STM32F303VE" + select STM32_STM32F30XX + select STM32_STM32F303 + select STM32_HAVE_ADC3 + select STM32_HAVE_ADC4 + select STM32_HAVE_USART3 + +config ARCH_CHIP_STM32F303ZD + bool "STM32F303ZD" + select STM32_STM32F30XX + select STM32_STM32F303 + select STM32_HAVE_ADC3 + select STM32_HAVE_ADC4 + select STM32_HAVE_USART3 + +config ARCH_CHIP_STM32F303ZE + bool "STM32F303ZE" + select STM32_STM32F30XX + select STM32_STM32F303 + select STM32_HAVE_ADC3 + select STM32_HAVE_ADC4 + select STM32_HAVE_USART3 + +config ARCH_CHIP_STM32F334K4 + bool "STM32F334K4" + select STM32_STM32F33XX + +config ARCH_CHIP_STM32F334K6 + bool "STM32F334K6" + select STM32_STM32F33XX + +config ARCH_CHIP_STM32F334K8 + bool "STM32F334K8" + select STM32_STM32F33XX + +config ARCH_CHIP_STM32F334C4 + bool "STM32F334C4" + select STM32_STM32F33XX + +config ARCH_CHIP_STM32F334C6 + bool "STM32F334C6" + select STM32_STM32F33XX + +config ARCH_CHIP_STM32F334C8 + bool "STM32F334C8" + select STM32_STM32F33XX + +config ARCH_CHIP_STM32F334R4 + bool "STM32F334R4" + select STM32_STM32F33XX + +config ARCH_CHIP_STM32F334R6 + bool "STM32F334R6" + select STM32_STM32F33XX + +config ARCH_CHIP_STM32F334R8 + bool "STM32F334R8" + select STM32_STM32F33XX + +config ARCH_CHIP_STM32F372C8 + bool "STM32F372C8" + select STM32_STM32F37XX + +config ARCH_CHIP_STM32F372R8 + bool "STM32F372R8" + select STM32_STM32F37XX + +config ARCH_CHIP_STM32F372V8 + bool "STM32F372V8" + select STM32_STM32F37XX + +config ARCH_CHIP_STM32F372CB + bool "STM32F372CB" + select STM32_STM32F37XX + +config ARCH_CHIP_STM32F372RB + bool "STM32F372RB" + select STM32_STM32F37XX + +config ARCH_CHIP_STM32F372VB + bool "STM32F372VB" + select STM32_STM32F37XX + +config ARCH_CHIP_STM32F372CC + bool "STM32F372CC" + select STM32_STM32F37XX + +config ARCH_CHIP_STM32F372RC + bool "STM32F372RC" + select STM32_STM32F37XX + +config ARCH_CHIP_STM32F372VC + bool "STM32F372VC" + select STM32_STM32F37XX + +config ARCH_CHIP_STM32F373C8 + bool "STM32F373C8" + select STM32_STM32F37XX + +config ARCH_CHIP_STM32F373R8 + bool "STM32F373R8" + select STM32_STM32F37XX + +config ARCH_CHIP_STM32F373V8 + bool "STM32F373V8" + select STM32_STM32F37XX + +config ARCH_CHIP_STM32F373CB + bool "STM32F373CB" + select STM32_STM32F37XX + +config ARCH_CHIP_STM32F373RB + bool "STM32F373RB" + select STM32_STM32F37XX + +config ARCH_CHIP_STM32F373VB + bool "STM32F373VB" + select STM32_STM32F37XX + +config ARCH_CHIP_STM32F373CC + bool "STM32F373CC" + select STM32_STM32F37XX + +config ARCH_CHIP_STM32F373RC + bool "STM32F373RC" + select STM32_STM32F37XX + +config ARCH_CHIP_STM32F373VC + bool "STM32F373VC" + select STM32_STM32F37XX + +endchoice + +endif + +config STM32_STM32F30XX + bool + default n + select STM32_HAVE_DMA1 + select STM32_HAVE_DMA2 + select ARCH_CORTEXM4 + select ARCH_HAVE_FPU + select STM32_HAVE_I2C1 + select STM32_HAVE_SPI1 + select STM32_HAVE_SYSCFG + select STM32_HAVE_USART1 + select STM32_HAVE_USART2 + select STM32_HAVE_CAN1 + select STM32_HAVE_DAC1 + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM3 + select STM32_HAVE_TIM6 + select STM32_HAVE_TIM15 + select STM32_HAVE_TIM16 + select STM32_HAVE_TIM17 + select STM32_HAVE_TSC + select STM32_HAVE_IP_AES_M3M4_V1 if STM32_HAVE_AES + select STM32_HAVE_IP_BBSRAM_M3M4_V1 + select STM32_HAVE_IP_BKP_M3M4_V1 + select STM32_HAVE_IP_CAN_BXCAN_M3M4_V1 + select STM32_HAVE_IP_CCM_M3M4_V1 if STM32_HAVE_CCM + select STM32_HAVE_IP_CRYPTO_M3M4_V1 + select STM32_HAVE_IP_DBGMCU_M3M4_V2 + select STM32_HAVE_IP_ADC_M3M4_V2 + select STM32_HAVE_COMMON_FOC + select STM32_HAVE_IP_DCMI_V1 + select STM32_HAVE_IP_DAC_M3M4_V1 + select STM32_HAVE_IP_DFUMODE_M3M4_V1 + select STM32_HAVE_IP_DMA_V1 + select STM32_HAVE_IP_DMA_V1_8CH + select STM32_HAVE_IP_EXTI_V1 + select STM32_HAVE_IP_ETHMAC_M3M4_V1 if STM32_HAVE_ETHMAC + select STM32_HAVE_IP_FLASH_M3M4_V1 + select STM32_HAVE_IP_FLASH_M3M4_F1F3 + select STM32_HAVE_IP_FMC_M3M4_V1 if STM32_HAVE_FMC + select STM32_HAVE_IP_FREERUN_M3M4_V1 + select STM32_HAVE_IP_FSMC_M3M4_V1 if STM32_HAVE_FSMC + select STM32_HAVE_IP_GPIO_M3M4_V1 + select STM32_HAVE_IP_HRTIM_M3M4_V1 if STM32_HAVE_HRTIM1 + select STM32_HAVE_IP_I2C_M3M4_V2 + select STM32_HAVE_IP_I2S_M3M4_V1 + select STM32_HAVE_IP_ONESHOT_M3M4_V1 + select STM32_HAVE_IP_PWR_M3M4_V1 + select STM32_HAVE_IP_RTC_M3M4_V1 + select STM32_HAVE_IP_RTCC_M3M4_V1 + select STM32_HAVE_IP_SDIO_M3M4_V1 + select STM32_HAVE_IP_SPI_V3 + select STM32_HAVE_IP_SYSCFG_M3M4_V1 + select STM32_HAVE_IP_TIMERS_M3M4_V2 + select STM32_HAVE_IP_USART_V3 + select STM32_HAVE_IP_USBDEV_M3M4_V1 if STM32_HAVE_USBDEV + select STM32_HAVE_IP_USBFS_M3M4_V1 if STM32_HAVE_USBFS + select STM32_HAVE_IP_OTGFS_M3M4_V1 if STM32_HAVE_OTGFS + select STM32_HAVE_IP_WDG_M3M4_V1 + +config STM32_STM32F302 + bool + default n + select STM32_HAVE_ADC2 + select STM32_HAVE_I2C2 + select STM32_HAVE_SPI2 + select STM32_HAVE_SPI3 + select STM32_HAVE_TIM4 + select STM32_HAVE_USBDEV + +config STM32_STM32F303 + bool + default n + select STM32_HAVE_ADC2 + select STM32_HAVE_CCM + select STM32_HAVE_TIM7 + +config STM32_STM32F33XX + bool + default n + select STM32_HAVE_DMA1 + select STM32_HAVE_COMP + select STM32_HAVE_DMA2 + select ARCH_CORTEXM4 + select ARCH_HAVE_FPU + select STM32_HAVE_I2C1 + select STM32_HAVE_HRTIM1 + select STM32_HAVE_COMP2 + select STM32_HAVE_COMP4 + select STM32_HAVE_COMP6 + select STM32_HAVE_OPAMP2 + select STM32_HAVE_CCM + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM6 + select STM32_HAVE_TIM7 + select STM32_HAVE_TIM15 + select STM32_HAVE_TIM16 + select STM32_HAVE_TIM17 + select STM32_HAVE_TSC + select STM32_HAVE_ADC2 + select STM32_HAVE_CAN1 + select STM32_HAVE_DAC1 + select STM32_HAVE_DAC2 + select STM32_HAVE_SPI1 + select STM32_HAVE_SYSCFG + select STM32_HAVE_USART2 + select STM32_HAVE_USART3 + select STM32_HAVE_IP_AES_M3M4_V1 if STM32_HAVE_AES + select STM32_HAVE_IP_BBSRAM_M3M4_V1 + select STM32_HAVE_IP_BKP_M3M4_V1 + select STM32_HAVE_IP_CAN_BXCAN_M3M4_V1 + select STM32_HAVE_IP_CCM_M3M4_V1 if STM32_HAVE_CCM + select STM32_HAVE_IP_CRYPTO_M3M4_V1 + select STM32_HAVE_IP_DBGMCU_M3M4_V2 + select STM32_HAVE_IP_ADC_M3M4_V2 + select STM32_HAVE_IP_COMP_M3M4_V1 + select STM32_HAVE_COMMON_FOC + select STM32_HAVE_IP_DCMI_V1 + select STM32_HAVE_IP_DAC_M3M4_V1 + select STM32_HAVE_IP_DFUMODE_M3M4_V1 + select STM32_HAVE_IP_DMA_V1 + select STM32_HAVE_IP_DMA_V1_8CH + select STM32_HAVE_IP_EXTI_V1 + select STM32_HAVE_IP_ETHMAC_M3M4_V1 if STM32_HAVE_ETHMAC + select STM32_HAVE_IP_FLASH_M3M4_V1 + select STM32_HAVE_IP_FLASH_M3M4_F1F3 + select STM32_HAVE_IP_FMC_M3M4_V1 if STM32_HAVE_FMC + select STM32_HAVE_IP_FREERUN_M3M4_V1 + select STM32_HAVE_IP_FSMC_M3M4_V1 if STM32_HAVE_FSMC + select STM32_HAVE_IP_GPIO_M3M4_V1 + select STM32_HAVE_IP_HRTIM_M3M4_V1 if STM32_HAVE_HRTIM1 + select STM32_HAVE_IP_I2C_M3M4_V2 + select STM32_HAVE_IP_I2S_M3M4_V1 + select STM32_HAVE_IP_ONESHOT_M3M4_V1 + select STM32_HAVE_IP_OPAMP_M3M4_V1 if STM32_HAVE_OPAMP1 || STM32_HAVE_OPAMP2 || STM32_HAVE_OPAMP3 || STM32_HAVE_OPAMP4 || STM32_HAVE_OPAMP5 || STM32_HAVE_OPAMP6 + select STM32_HAVE_IP_PWR_M3M4_V1 + select STM32_HAVE_IP_RTC_M3M4_V1 + select STM32_HAVE_IP_RTCC_M3M4_V1 + select STM32_HAVE_IP_SDIO_M3M4_V1 + select STM32_HAVE_IP_SPI_V3 + select STM32_HAVE_IP_SYSCFG_M3M4_V1 + select STM32_HAVE_IP_TIMERS_M3M4_V2 + select STM32_HAVE_IP_USART_V3 + select STM32_HAVE_IP_USBDEV_M3M4_V1 if STM32_HAVE_USBDEV + select STM32_HAVE_IP_USBFS_M3M4_V1 if STM32_HAVE_USBFS + select STM32_HAVE_IP_OTGFS_M3M4_V1 if STM32_HAVE_OTGFS + select STM32_HAVE_IP_WDG_M3M4_V1 + +config STM32_STM32F37XX + bool + default n + select STM32_HAVE_DMA1 + select STM32_HAVE_DMA2 + select ARCH_CORTEXM4 + select ARCH_HAVE_FPU + select STM32_HAVE_I2C1 + select STM32_HAVE_SPI1 + select STM32_HAVE_SYSCFG + select STM32_HAVE_USBDEV + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM3 + select STM32_HAVE_TIM4 + select STM32_HAVE_TIM5 + select STM32_HAVE_TIM6 + select STM32_HAVE_TIM7 + select STM32_HAVE_TIM15 + select STM32_HAVE_TIM16 + select STM32_HAVE_TIM17 + select STM32_HAVE_TSC + select STM32_HAVE_SDADC1 + select STM32_HAVE_SDADC2 + select STM32_HAVE_SDADC3 + select STM32_HAVE_CAN1 + select STM32_HAVE_DAC1 + select STM32_HAVE_DAC2 + select STM32_HAVE_I2C2 + select STM32_HAVE_SPI2 + select STM32_HAVE_SPI3 + select STM32_HAVE_USART3 + select STM32_HAVE_IP_AES_M3M4_V1 if STM32_HAVE_AES + select STM32_HAVE_IP_BBSRAM_M3M4_V1 + select STM32_HAVE_IP_BKP_M3M4_V1 + select STM32_HAVE_IP_CAN_BXCAN_M3M4_V1 + select STM32_HAVE_IP_CCM_M3M4_V1 if STM32_HAVE_CCM + select STM32_HAVE_IP_CRYPTO_M3M4_V1 + select STM32_HAVE_IP_TIMERS_M3M4_V1 + select STM32_HAVE_IP_ADC_M3M4_V1_BASIC + select STM32_HAVE_COMMON_FOC + select STM32_HAVE_IP_DCMI_V1 + select STM32_HAVE_IP_DAC_M3M4_V1 + select STM32_HAVE_IP_DFUMODE_M3M4_V1 + select STM32_HAVE_IP_DMA_V1 + select STM32_HAVE_IP_DMA_V1_8CH + select STM32_HAVE_IP_EXTI_V1 + select STM32_HAVE_IP_ETHMAC_M3M4_V1 if STM32_HAVE_ETHMAC + select STM32_HAVE_IP_FLASH_M3M4_V1 + select STM32_HAVE_IP_FLASH_M3M4_F1F3 + select STM32_HAVE_IP_FMC_M3M4_V1 if STM32_HAVE_FMC + select STM32_HAVE_IP_FREERUN_M3M4_V1 + select STM32_HAVE_IP_FSMC_M3M4_V1 if STM32_HAVE_FSMC + select STM32_HAVE_IP_GPIO_M3M4_V1 + select STM32_HAVE_IP_HRTIM_M3M4_V1 if STM32_HAVE_HRTIM1 + select STM32_HAVE_IP_I2C_M3M4_V2 + select STM32_HAVE_IP_I2S_M3M4_V1 + select STM32_HAVE_IP_ONESHOT_M3M4_V1 + select STM32_HAVE_IP_PWR_M3M4_V1 + select STM32_HAVE_IP_RTC_M3M4_V1 + select STM32_HAVE_IP_RTCC_M3M4_V1 + select STM32_HAVE_IP_SDADC_M3M4_V1 + select STM32_HAVE_IP_SDIO_M3M4_V1 + select STM32_HAVE_IP_SPI_V3 + select STM32_HAVE_IP_SYSCFG_M3M4_V1 + select STM32_HAVE_IP_USART_V3 + select STM32_HAVE_IP_USBDEV_M3M4_V1 if STM32_HAVE_USBDEV + select STM32_HAVE_IP_USBFS_M3M4_V1 if STM32_HAVE_USBFS + select STM32_HAVE_IP_OTGFS_M3M4_V1 if STM32_HAVE_OTGFS + select STM32_HAVE_IP_WDG_M3M4_V1 diff --git a/arch/arm/src/stm32f3/Make.defs b/arch/arm/src/stm32f3/Make.defs new file mode 100644 index 0000000000000..e847b60c00751 --- /dev/null +++ b/arch/arm/src/stm32f3/Make.defs @@ -0,0 +1,27 @@ +############################################################################ +# arch/arm/src/stm32f3/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include armv7-m/Make.defs + +CHIP_CSRCS = stm32_rcc.c + +include common/stm32/Make.defs diff --git a/arch/arm/src/stm32f3/chip.h b/arch/arm/src/stm32f3/chip.h new file mode 100644 index 0000000000000..c3961139c12ee --- /dev/null +++ b/arch/arm/src/stm32f3/chip.h @@ -0,0 +1,59 @@ +/**************************************************************************** + * arch/arm/src/stm32f3/chip.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32F3_CHIP_H +#define __ARCH_ARM_SRC_STM32F3_CHIP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/* Include the chip capabilities file */ + +#include + +/* Include the chip interrupt definition file */ + +#include + +/* Include the chip memory map */ + +#include "hardware/stm32_memorymap.h" + +/* Include the chip pinmap */ + +#include "hardware/stm32_pinmap.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Provide the required number of peripheral interrupt vector + * definitions as * well. The definition STM32_IRQ_NEXTINTS simply comes + * from the chip-specific * IRQ header file included by arch/stm32/irq.h. + */ + +#define ARMV7M_PERIPHERAL_INTERRUPTS STM32_IRQ_NEXTINTS + +#endif /* __ARCH_ARM_SRC_STM32F3_CHIP_H */ diff --git a/arch/arm/src/stm32f3/hardware/stm32_memorymap.h b/arch/arm/src/stm32f3/hardware/stm32_memorymap.h new file mode 100644 index 0000000000000..475cd8800a33c --- /dev/null +++ b/arch/arm/src/stm32f3/hardware/stm32_memorymap.h @@ -0,0 +1,27 @@ +/**************************************************************************** + * arch/arm/src/stm32f3/hardware/stm32_memorymap.h + * + * SPDX-License-Identifier: Apache-2.0 + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32F3_HARDWARE_STM32_MEMORYMAP_H +#define __ARCH_ARM_SRC_STM32F3_HARDWARE_STM32_MEMORYMAP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#if defined(CONFIG_STM32_STM32F30XX) +# include "hardware/stm32f30xxx_memorymap.h" +#elif defined(CONFIG_STM32_STM32F33XX) +# include "hardware/stm32f33xxx_memorymap.h" +#elif defined(CONFIG_STM32_STM32F37XX) +# include "hardware/stm32f37xxx_memorymap.h" +#else +# error "Unsupported STM32F3 memory map" +#endif + +#endif /* __ARCH_ARM_SRC_STM32F3_HARDWARE_STM32_MEMORYMAP_H */ diff --git a/arch/arm/src/stm32f3/hardware/stm32_pinmap.h b/arch/arm/src/stm32f3/hardware/stm32_pinmap.h new file mode 100644 index 0000000000000..35a22b5600934 --- /dev/null +++ b/arch/arm/src/stm32f3/hardware/stm32_pinmap.h @@ -0,0 +1,27 @@ +/**************************************************************************** + * arch/arm/src/stm32f3/hardware/stm32_pinmap.h + * + * SPDX-License-Identifier: Apache-2.0 + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32F3_HARDWARE_STM32_PINMAP_H +#define __ARCH_ARM_SRC_STM32F3_HARDWARE_STM32_PINMAP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#if defined(CONFIG_STM32_STM32F30XX) +# include "hardware/stm32f30xxx_pinmap.h" +#elif defined(CONFIG_STM32_STM32F33XX) +# include "hardware/stm32f33xxx_pinmap.h" +#elif defined(CONFIG_STM32_STM32F37XX) +# include "hardware/stm32f37xxx_pinmap.h" +#else +# error "Unsupported STM32F3 pin map" +#endif + +#endif /* __ARCH_ARM_SRC_STM32F3_HARDWARE_STM32_PINMAP_H */ diff --git a/arch/arm/src/stm32/hardware/stm32f30xxx_gpio.h b/arch/arm/src/stm32f3/hardware/stm32f30xxx_gpio.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32f30xxx_gpio.h rename to arch/arm/src/stm32f3/hardware/stm32f30xxx_gpio.h index 47087489a38c3..247900fd222e8 100644 --- a/arch/arm/src/stm32/hardware/stm32f30xxx_gpio.h +++ b/arch/arm/src/stm32f3/hardware/stm32f30xxx_gpio.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32f30xxx_gpio.h + * arch/arm/src/stm32f3/hardware/stm32f30xxx_gpio.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/hardware/stm32f30xxx_memorymap.h b/arch/arm/src/stm32f3/hardware/stm32f30xxx_memorymap.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32f30xxx_memorymap.h rename to arch/arm/src/stm32f3/hardware/stm32f30xxx_memorymap.h index 23667f3b7c974..9471911d8c4cb 100644 --- a/arch/arm/src/stm32/hardware/stm32f30xxx_memorymap.h +++ b/arch/arm/src/stm32f3/hardware/stm32f30xxx_memorymap.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32f30xxx_memorymap.h + * arch/arm/src/stm32f3/hardware/stm32f30xxx_memorymap.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/hardware/stm32f30xxx_pinmap.h b/arch/arm/src/stm32f3/hardware/stm32f30xxx_pinmap.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32f30xxx_pinmap.h rename to arch/arm/src/stm32f3/hardware/stm32f30xxx_pinmap.h index d92b45de89a95..02c86632c64d0 100644 --- a/arch/arm/src/stm32/hardware/stm32f30xxx_pinmap.h +++ b/arch/arm/src/stm32f3/hardware/stm32f30xxx_pinmap.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32f30xxx_pinmap.h + * arch/arm/src/stm32f3/hardware/stm32f30xxx_pinmap.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/hardware/stm32f30xxx_rcc.h b/arch/arm/src/stm32f3/hardware/stm32f30xxx_rcc.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32f30xxx_rcc.h rename to arch/arm/src/stm32f3/hardware/stm32f30xxx_rcc.h index 9d86d13a7040d..10d8c30c617b5 100644 --- a/arch/arm/src/stm32/hardware/stm32f30xxx_rcc.h +++ b/arch/arm/src/stm32f3/hardware/stm32f30xxx_rcc.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32f30xxx_rcc.h + * arch/arm/src/stm32f3/hardware/stm32f30xxx_rcc.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/hardware/stm32f30xxx_syscfg.h b/arch/arm/src/stm32f3/hardware/stm32f30xxx_syscfg.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32f30xxx_syscfg.h rename to arch/arm/src/stm32f3/hardware/stm32f30xxx_syscfg.h index 74900826244b4..e9fa174e4e7cd 100644 --- a/arch/arm/src/stm32/hardware/stm32f30xxx_syscfg.h +++ b/arch/arm/src/stm32f3/hardware/stm32f30xxx_syscfg.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32f30xxx_syscfg.h + * arch/arm/src/stm32f3/hardware/stm32f30xxx_syscfg.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/hardware/stm32f33xxx_comp.h b/arch/arm/src/stm32f3/hardware/stm32f33xxx_comp.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32f33xxx_comp.h rename to arch/arm/src/stm32f3/hardware/stm32f33xxx_comp.h index d12e43317d560..0cc9a568c7b93 100644 --- a/arch/arm/src/stm32/hardware/stm32f33xxx_comp.h +++ b/arch/arm/src/stm32f3/hardware/stm32f33xxx_comp.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32f33xxx_comp.h + * arch/arm/src/stm32f3/hardware/stm32f33xxx_comp.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/hardware/stm32f33xxx_hrtim.h b/arch/arm/src/stm32f3/hardware/stm32f33xxx_hrtim.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32f33xxx_hrtim.h rename to arch/arm/src/stm32f3/hardware/stm32f33xxx_hrtim.h index 7c6ff331f9ae3..94480b138758a 100644 --- a/arch/arm/src/stm32/hardware/stm32f33xxx_hrtim.h +++ b/arch/arm/src/stm32f3/hardware/stm32f33xxx_hrtim.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32f33xxx_hrtim.h + * arch/arm/src/stm32f3/hardware/stm32f33xxx_hrtim.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/hardware/stm32f33xxx_memorymap.h b/arch/arm/src/stm32f3/hardware/stm32f33xxx_memorymap.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32f33xxx_memorymap.h rename to arch/arm/src/stm32f3/hardware/stm32f33xxx_memorymap.h index eb59aba7e218e..ce0e3889d20af 100644 --- a/arch/arm/src/stm32/hardware/stm32f33xxx_memorymap.h +++ b/arch/arm/src/stm32f3/hardware/stm32f33xxx_memorymap.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32f33xxx_memorymap.h + * arch/arm/src/stm32f3/hardware/stm32f33xxx_memorymap.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/hardware/stm32f33xxx_opamp.h b/arch/arm/src/stm32f3/hardware/stm32f33xxx_opamp.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32f33xxx_opamp.h rename to arch/arm/src/stm32f3/hardware/stm32f33xxx_opamp.h index 3235866bcee08..a2a1a269b9657 100644 --- a/arch/arm/src/stm32/hardware/stm32f33xxx_opamp.h +++ b/arch/arm/src/stm32f3/hardware/stm32f33xxx_opamp.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32f33xxx_opamp.h + * arch/arm/src/stm32f3/hardware/stm32f33xxx_opamp.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/hardware/stm32f33xxx_pinmap.h b/arch/arm/src/stm32f3/hardware/stm32f33xxx_pinmap.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32f33xxx_pinmap.h rename to arch/arm/src/stm32f3/hardware/stm32f33xxx_pinmap.h index 3d3be1182a6e3..d26376e3af588 100644 --- a/arch/arm/src/stm32/hardware/stm32f33xxx_pinmap.h +++ b/arch/arm/src/stm32f3/hardware/stm32f33xxx_pinmap.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32f33xxx_pinmap.h + * arch/arm/src/stm32f3/hardware/stm32f33xxx_pinmap.h * * SPDX-License-Identifier: Apache-2.0 * @@ -150,7 +150,7 @@ /* JTAG/SWD */ #define GPIO_JTDI_0 (GPIO_ALT|GPIO_AF0|GPIO_PORTA|GPIO_PIN15) -#define GPIO_JTDO_TRACES_WO_0GPIO_ALT|GPIO_AF0|GPIO_PORTB|GPIO_PIN3) +#define GPIO_JTDO_TRACES_WO_0 (GPIO_ALT|GPIO_AF0|GPIO_PORTB|GPIO_PIN3) #define GPIO_NJTRST_0 (GPIO_ALT|GPIO_AF0|GPIO_PORTB|GPIO_PIN4) #define GPIO_SWCLK_JTCK_0 (GPIO_ALT|GPIO_AF0|GPIO_PORTA|GPIO_PIN14) #define GPIO_SWDIO_JTMS_0 (GPIO_ALT|GPIO_AF0|GPIO_PORTA|GPIO_PIN13) diff --git a/arch/arm/src/stm32/hardware/stm32f33xxx_rcc.h b/arch/arm/src/stm32f3/hardware/stm32f33xxx_rcc.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32f33xxx_rcc.h rename to arch/arm/src/stm32f3/hardware/stm32f33xxx_rcc.h index 1e26281fb4380..05348c760ecc6 100644 --- a/arch/arm/src/stm32/hardware/stm32f33xxx_rcc.h +++ b/arch/arm/src/stm32f3/hardware/stm32f33xxx_rcc.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32f33xxx_rcc.h + * arch/arm/src/stm32f3/hardware/stm32f33xxx_rcc.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/hardware/stm32f33xxx_syscfg.h b/arch/arm/src/stm32f3/hardware/stm32f33xxx_syscfg.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32f33xxx_syscfg.h rename to arch/arm/src/stm32f3/hardware/stm32f33xxx_syscfg.h index 5c3764b2d4ded..a3270a48b35c9 100644 --- a/arch/arm/src/stm32/hardware/stm32f33xxx_syscfg.h +++ b/arch/arm/src/stm32f3/hardware/stm32f33xxx_syscfg.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32f33xxx_syscfg.h + * arch/arm/src/stm32f3/hardware/stm32f33xxx_syscfg.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/hardware/stm32f37xxx_memorymap.h b/arch/arm/src/stm32f3/hardware/stm32f37xxx_memorymap.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32f37xxx_memorymap.h rename to arch/arm/src/stm32f3/hardware/stm32f37xxx_memorymap.h index fd05c2477b9fa..26baaf49cd444 100644 --- a/arch/arm/src/stm32/hardware/stm32f37xxx_memorymap.h +++ b/arch/arm/src/stm32f3/hardware/stm32f37xxx_memorymap.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32f37xxx_memorymap.h + * arch/arm/src/stm32f3/hardware/stm32f37xxx_memorymap.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/hardware/stm32f37xxx_pinmap.h b/arch/arm/src/stm32f3/hardware/stm32f37xxx_pinmap.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32f37xxx_pinmap.h rename to arch/arm/src/stm32f3/hardware/stm32f37xxx_pinmap.h index f830d6868dc02..f26a6c33f29b9 100644 --- a/arch/arm/src/stm32/hardware/stm32f37xxx_pinmap.h +++ b/arch/arm/src/stm32f3/hardware/stm32f37xxx_pinmap.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32f37xxx_pinmap.h + * arch/arm/src/stm32f3/hardware/stm32f37xxx_pinmap.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/hardware/stm32f37xxx_rcc.h b/arch/arm/src/stm32f3/hardware/stm32f37xxx_rcc.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32f37xxx_rcc.h rename to arch/arm/src/stm32f3/hardware/stm32f37xxx_rcc.h index a0f658aa6d7d0..ef555856d7c47 100644 --- a/arch/arm/src/stm32/hardware/stm32f37xxx_rcc.h +++ b/arch/arm/src/stm32f3/hardware/stm32f37xxx_rcc.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32f37xxx_rcc.h + * arch/arm/src/stm32f3/hardware/stm32f37xxx_rcc.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/hardware/stm32f37xxx_sdadc.h b/arch/arm/src/stm32f3/hardware/stm32f37xxx_sdadc.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32f37xxx_sdadc.h rename to arch/arm/src/stm32f3/hardware/stm32f37xxx_sdadc.h index f75141295021c..908ccda789f19 100644 --- a/arch/arm/src/stm32/hardware/stm32f37xxx_sdadc.h +++ b/arch/arm/src/stm32f3/hardware/stm32f37xxx_sdadc.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32f37xxx_sdadc.h + * arch/arm/src/stm32f3/hardware/stm32f37xxx_sdadc.h * * SPDX-License-Identifier: BSD-3-Clause * SPDX-FileCopyrightText: 2016 Studelec SA. All rights reserved. diff --git a/arch/arm/src/stm32/hardware/stm32f37xxx_syscfg.h b/arch/arm/src/stm32f3/hardware/stm32f37xxx_syscfg.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32f37xxx_syscfg.h rename to arch/arm/src/stm32f3/hardware/stm32f37xxx_syscfg.h index 6849a95cbb639..d6a726471485b 100644 --- a/arch/arm/src/stm32/hardware/stm32f37xxx_syscfg.h +++ b/arch/arm/src/stm32f3/hardware/stm32f37xxx_syscfg.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32f37xxx_syscfg.h + * arch/arm/src/stm32f3/hardware/stm32f37xxx_syscfg.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32f3/stm32.h b/arch/arm/src/stm32f3/stm32.h new file mode 100644 index 0000000000000..f7eb0f45c819d --- /dev/null +++ b/arch/arm/src/stm32f3/stm32.h @@ -0,0 +1,69 @@ +/**************************************************************************** + * arch/arm/src/stm32f3/stm32.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32_STM32_H +#define __ARCH_ARM_SRC_STM32_STM32_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include +#include + +#include "arm_internal.h" + +/* Peripherals **************************************************************/ + +#include "chip.h" +#include "stm32_adc.h" +#include "stm32_can.h" +#include "stm32_comp.h" +#include "stm32_dbgmcu.h" +#include "stm32_dma.h" +#include "stm32_dac_m3m4_v1.h" +#include "stm32_exti.h" +#include "stm32_flash.h" +#include "stm32_fmc_m3m4_v1.h" +#include "stm32_fsmc_m3m4_v1.h" +#include "stm32_gpio.h" +#include "stm32_i2c.h" +#include "stm32_ltdc_m3m4_v1.h" +#include "stm32_opamp_m3m4_v1.h" +#include "stm32_pwr.h" +#include "stm32_rcc.h" +#include "stm32_rtc.h" +#include "stm32_sdio_m3m4_v1.h" +#include "stm32_spi.h" +#include "stm32_i2s.h" +#include "stm32_tim.h" +#include "stm32_uart.h" +#if defined(CONFIG_USBDEV) && defined(CONFIG_STM32_USB) +# include "stm32_usbdev.h" +#endif +#include "stm32_wdg.h" +#include "stm32_lowputc.h" +#include "stm32_eth_m3m4_v1.h" + +#endif /* __ARCH_ARM_SRC_STM32_STM32_H */ diff --git a/arch/arm/src/stm32f3/stm32_rcc.c b/arch/arm/src/stm32f3/stm32_rcc.c new file mode 100644 index 0000000000000..32d4bbca0f3cd --- /dev/null +++ b/arch/arm/src/stm32f3/stm32_rcc.c @@ -0,0 +1,242 @@ +/**************************************************************************** + * arch/arm/src/stm32f3/stm32_rcc.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include + +#include "arm_internal.h" +#include "chip.h" +#include "stm32_gpio.h" +#include "stm32_rcc.h" +#include "stm32_rtc.h" +#include "stm32_flash.h" +#include "stm32.h" +#include "stm32_waste.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1, + "Configure BOARD_LOOPSPERMSEC to non-default value."); + +/* Allow up to 100 milliseconds for the high speed clock to become ready. + * that is a very long delay, but if the clock does not become ready we are + * hosed anyway. + */ + +#define HSERDY_TIMEOUT (100 * CONFIG_BOARD_LOOPSPERMSEC) + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/* Include chip-specific clocking initialization logic */ + +#if defined(CONFIG_STM32_STM32F30XX) +# include "stm32f30xxx_rcc.c" +#elif defined(CONFIG_STM32_STM32F33XX) +# include "stm32f33xxx_rcc.c" +#elif defined(CONFIG_STM32_STM32F37XX) +# include "stm32f37xxx_rcc.c" +#else +# error "Unsupported STM32F3 chip" +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#if defined(CONFIG_STM32_STM32L15XX) +# define STM32_RCC_XXX STM32_RCC_CSR +# define RCC_XXX_YYYRST RCC_CSR_RTCRST +#else +# define STM32_RCC_XXX STM32_RCC_BDCR +# define RCC_XXX_YYYRST RCC_BDCR_BDRST +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: rcc_resetbkp + * + * Description: + * The RTC needs to reset the Backup Domain to change RTCSEL and resetting + * the Backup Domain renders to disabling the LSE as consequence. + * In order to avoid resetting the Backup Domain when we already + * configured LSE we will reset the Backup Domain early (here). + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +#if defined(CONFIG_STM32_RTC) && defined(CONFIG_STM32_PWR) && !defined(CONFIG_STM32_STM32F10XX) +static inline void rcc_resetbkp(void) +{ + uint32_t regval; + + /* Check if the RTC is already configured */ + + stm32_pwr_initbkp(false); + + regval = getreg32(RTC_MAGIC_REG); + if (regval != RTC_MAGIC && regval != RTC_MAGIC_TIME_SET) + { + stm32_pwr_enablebkp(true); + + /* We might be changing RTCSEL - to ensure such changes work, we must + * reset the backup domain (having backed up the RTC_MAGIC token) + */ + + modifyreg32(STM32_RCC_XXX, 0, RCC_XXX_YYYRST); + modifyreg32(STM32_RCC_XXX, RCC_XXX_YYYRST, 0); + + stm32_pwr_enablebkp(false); + } +} +#else +# define rcc_resetbkp() +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_clockconfig + * + * Description: + * Called to establish the clock settings based on the values in board.h. + * This function (by default) will reset most everything, enable the PLL, + * and enable peripheral clocking for all peripherals enabled in the NuttX + * configuration file. + * + * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then clocking + * will be enabled by an externally provided, board-specific function + * called stm32_board_clockconfig(). + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void stm32_clockconfig(void) +{ + /* Make sure that we are starting in the reset state */ + + rcc_reset(); + + /* Reset backup domain if appropriate */ + + rcc_resetbkp(); + +#if defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) + + /* Invoke Board Custom Clock Configuration */ + + stm32_board_clockconfig(); + +#else + + /* Invoke standard, fixed clock configuration based on definitions + * in board.h + */ + + stm32_stdclockconfig(); + +#endif + + /* Enable peripheral clocking */ + + rcc_enableperipherals(); + +#ifdef CONFIG_STM32_SYSCFG_IOCOMPENSATION + /* Enable I/O Compensation */ + + stm32_iocompensation(); +#endif +} + +/**************************************************************************** + * Name: stm32_clockenable + * + * Description: + * Re-enable the clock and restore the clock settings based on settings + * in board.h. This function is only available to support low-power + * modes of operation: When re-awakening from deep-sleep modes, it is + * necessary to re-enable/re-start the PLL + * + * This functional performs a subset of the operations performed by + * stm32_clockconfig(): It does not reset any devices, and it does not + * reset the currently enabled peripheral clocks. + * + * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then clocking + * will be enabled by an externally provided, board-specific function + * called stm32_board_clockconfig(). + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_PM +void stm32_clockenable(void) +{ +#if defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) + + /* Invoke Board Custom Clock Configuration */ + + stm32_board_clockconfig(); + +#else + + /* Invoke standard, fixed clock configuration based on definitions + * in board.h + */ + + stm32_stdclockconfig(); + +#endif +} +#endif diff --git a/arch/arm/src/stm32/stm32f30xxx_rcc.c b/arch/arm/src/stm32f3/stm32f30xxx_rcc.c similarity index 99% rename from arch/arm/src/stm32/stm32f30xxx_rcc.c rename to arch/arm/src/stm32f3/stm32f30xxx_rcc.c index 8c0f606c7651e..79eeff67e83e3 100644 --- a/arch/arm/src/stm32/stm32f30xxx_rcc.c +++ b/arch/arm/src/stm32f3/stm32f30xxx_rcc.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32f30xxx_rcc.c + * arch/arm/src/stm32f3/stm32f30xxx_rcc.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/stm32f33xxx_rcc.c b/arch/arm/src/stm32f3/stm32f33xxx_rcc.c similarity index 99% rename from arch/arm/src/stm32/stm32f33xxx_rcc.c rename to arch/arm/src/stm32f3/stm32f33xxx_rcc.c index bf3edc0727579..d55f756b53b44 100644 --- a/arch/arm/src/stm32/stm32f33xxx_rcc.c +++ b/arch/arm/src/stm32f3/stm32f33xxx_rcc.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32f33xxx_rcc.c + * arch/arm/src/stm32f3/stm32f33xxx_rcc.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/stm32f37xxx_rcc.c b/arch/arm/src/stm32f3/stm32f37xxx_rcc.c similarity index 99% rename from arch/arm/src/stm32/stm32f37xxx_rcc.c rename to arch/arm/src/stm32f3/stm32f37xxx_rcc.c index 6c8a157a48ec8..c640835f69645 100644 --- a/arch/arm/src/stm32/stm32f37xxx_rcc.c +++ b/arch/arm/src/stm32f3/stm32f37xxx_rcc.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32f37xxx_rcc.c + * arch/arm/src/stm32f3/stm32f37xxx_rcc.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32f4/CMakeLists.txt b/arch/arm/src/stm32f4/CMakeLists.txt new file mode 100644 index 0000000000000..7b5008db37150 --- /dev/null +++ b/arch/arm/src/stm32f4/CMakeLists.txt @@ -0,0 +1,28 @@ +# ############################################################################## +# arch/arm/src/stm32f4/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(SRCS) + +list(APPEND SRCS stm32_rcc.c) + +target_sources(arch PRIVATE ${SRCS}) +add_subdirectory(${NUTTX_DIR}/arch/arm/src/common/stm32 stm32_common) diff --git a/arch/arm/src/stm32f4/Kconfig b/arch/arm/src/stm32f4/Kconfig new file mode 100644 index 0000000000000..698e52b602f85 --- /dev/null +++ b/arch/arm/src/stm32f4/Kconfig @@ -0,0 +1,618 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# +comment "STM32 F4 configuration" + +if ARCH_CHIP_STM32F4 + +choice + prompt "STM32F4 Chip Selection" + depends on ARCH_CHIP_STM32F4 + +config ARCH_CHIP_STM32F401CB + bool "STM32F401CB" + select STM32_STM32F401xBC + +config ARCH_CHIP_STM32F401RB + bool "STM32F401RB" + select STM32_STM32F401xBC + +config ARCH_CHIP_STM32F401VB + bool "STM32F401VB" + select STM32_STM32F401xBC + +config ARCH_CHIP_STM32F401CC + bool "STM32F401CC" + select STM32_STM32F401xBC + +config ARCH_CHIP_STM32F401RC + bool "STM32F401RC" + select STM32_STM32F401xBC + +config ARCH_CHIP_STM32F401VC + bool "STM32F401VC" + select STM32_STM32F401xBC + +config ARCH_CHIP_STM32F401CD + bool "STM32F401CD" + select STM32_STM32F401xDE + +config ARCH_CHIP_STM32F401RD + bool "STM32F401RD" + select STM32_STM32F401xDE + +config ARCH_CHIP_STM32F401VD + bool "STM32F401VD" + select STM32_STM32F401xDE + +config ARCH_CHIP_STM32F401CE + bool "STM32F401CE" + select STM32_STM32F401xDE + +config ARCH_CHIP_STM32F401RE + bool "STM32F401RE" + select STM32_STM32F401xDE + +config ARCH_CHIP_STM32F401VE + bool "STM32F401VE" + select STM32_STM32F401xDE + +config ARCH_CHIP_STM32F410RB + bool "STM32F410RB" + select STM32_STM32F4XXX + select STM32_STM32F410 + +config ARCH_CHIP_STM32F411CE + bool "STM32F411CE" + select STM32_STM32F4XXX + select STM32_STM32F411 + +config ARCH_CHIP_STM32F411RE + bool "STM32F411RE" + select STM32_STM32F4XXX + select STM32_STM32F411 + +config ARCH_CHIP_STM32F411VE + bool "STM32F411VE" + select STM32_STM32F4XXX + select STM32_STM32F411 + +config ARCH_CHIP_STM32F412CE + bool "STM32F412CE" + select STM32_STM32F4XXX + select STM32_STM32F412 + +config ARCH_CHIP_STM32F412ZG + bool "STM32F412ZG" + select STM32_STM32F4XXX + select STM32_STM32F412 + +config ARCH_CHIP_STM32F405RG + bool "STM32F405RG" + select STM32_STM32F4XXX + select STM32_STM32F405 + +config ARCH_CHIP_STM32F405VG + bool "STM32F405VG" + select STM32_STM32F4XXX + select STM32_STM32F405 + +config ARCH_CHIP_STM32F405ZG + bool "STM32F405ZG" + select STM32_STM32F4XXX + select STM32_STM32F405 + +config ARCH_CHIP_STM32F407VE + bool "STM32F407VE" + select STM32_STM32F4XXX + select STM32_STM32F407 + +config ARCH_CHIP_STM32F407VG + bool "STM32F407VG" + select STM32_STM32F4XXX + select STM32_STM32F407 + +config ARCH_CHIP_STM32F407ZE + bool "STM32F407ZE" + select STM32_STM32F4XXX + select STM32_STM32F407 + +config ARCH_CHIP_STM32F407ZG + bool "STM32F407ZG" + select STM32_STM32F4XXX + select STM32_STM32F407 + +config ARCH_CHIP_STM32F407IE + bool "STM32F407IE" + select STM32_STM32F4XXX + select STM32_STM32F407 + +config ARCH_CHIP_STM32F407IG + bool "STM32F407IG" + select STM32_STM32F4XXX + select STM32_STM32F407 + +config ARCH_CHIP_STM32F427V + bool "STM32F427V" + select STM32_STM32F4XXX + select STM32_STM32F427 + +config ARCH_CHIP_STM32F427Z + bool "STM32F427Z" + select STM32_STM32F4XXX + select STM32_STM32F427 + +config ARCH_CHIP_STM32F427I + bool "STM32F427I" + select STM32_STM32F4XXX + select STM32_STM32F427 + +config ARCH_CHIP_STM32F429V + bool "STM32F429V" + select STM32_STM32F4XXX + select STM32_STM32F429 + +config ARCH_CHIP_STM32F429Z + bool "STM32F429Z" + select STM32_STM32F4XXX + select STM32_STM32F429 + +config ARCH_CHIP_STM32F429I + bool "STM32F429I" + select STM32_STM32F4XXX + select STM32_STM32F429 + +config ARCH_CHIP_STM32F429B + bool "STM32F429B" + select STM32_STM32F4XXX + select STM32_STM32F429 + +config ARCH_CHIP_STM32F429N + bool "STM32F429N" + select STM32_STM32F4XXX + select STM32_STM32F429 + +config ARCH_CHIP_STM32F446M + bool "STM32F446M" + select STM32_STM32F4XXX + select STM32_STM32F446 + +config ARCH_CHIP_STM32F446R + bool "STM32F446R" + select STM32_STM32F4XXX + select STM32_STM32F446 + +config ARCH_CHIP_STM32F446V + bool "STM32F446V" + select STM32_STM32F4XXX + select STM32_STM32F446 + +config ARCH_CHIP_STM32F446Z + bool "STM32F446Z" + select STM32_STM32F4XXX + select STM32_STM32F446 + +config ARCH_CHIP_STM32F469A + bool "STM32F469A" + select STM32_STM32F4XXX + select STM32_STM32F469 + +config ARCH_CHIP_STM32F469I + bool "STM32F469I" + select STM32_STM32F4XXX + select STM32_STM32F469 + select STM32_HAVE_ETHMAC + +config ARCH_CHIP_STM32F469B + bool "STM32F469B" + select STM32_STM32F4XXX + select STM32_STM32F469 + select STM32_HAVE_ETHMAC + +config ARCH_CHIP_STM32F469N + bool "STM32F469N" + select STM32_STM32F4XXX + select STM32_STM32F469 + select STM32_HAVE_ETHMAC + +endchoice + +endif + +config STM32_STM32F4XXX + bool + default n + select STM32_HAVE_DMA1 + select STM32_HAVE_DMA2 + select ARCH_CORTEXM4 + select ARCH_HAVE_FPU + select STM32_HAVE_DCMI + select STM32_HAVE_HASH + select STM32_HAVE_I2C1 + select STM32_HAVE_SPI1 + select STM32_HAVE_SYSCFG + select STM32_HAVE_USART1 + select STM32_HAVE_USART2 + select STM32_HAVE_FLASH_ICACHE + select STM32_HAVE_FLASH_DCACHE + select STM32_HAVE_CRYP + select STM32_HAVE_SPI2 + select STM32_HAVE_I2C2 + select STM32_HAVE_IOCOMPENSATION + select STM32_HAVE_IP_AES_M3M4_V1 if STM32_HAVE_AES + select STM32_HAVE_IP_BBSRAM_M3M4_V1 + select STM32_HAVE_IP_BKP_M3M4_V1 + select STM32_HAVE_IP_CAN_BXCAN_M3M4_V1 + select STM32_HAVE_IP_CCM_M3M4_V1 if STM32_HAVE_CCM + select STM32_HAVE_IP_CRYPTO_M3M4_V1 + select STM32_HAVE_IP_DBGMCU_M3M4_V2 + select STM32_HAVE_IP_ADC_M3M4_V1 + select STM32_HAVE_COMMON_FOC + select STM32_HAVE_IP_DCMI_V1 + select STM32_HAVE_IP_DAC_M3M4_V1 + select STM32_HAVE_IP_DFUMODE_M3M4_V1 + select STM32_HAVE_IP_DMA_V2 + select STM32_HAVE_IP_DMA_V2_STREAM + select STM32_HAVE_ETHERNET if STM32_HAVE_ETHMAC + select STM32_HAVE_IP_EXTI_V1 + select STM32_HAVE_IP_ETHMAC_M3M4_V1 if STM32_HAVE_ETHMAC + select STM32_HAVE_IP_FLASH_M3M4_V1 + select STM32_HAVE_IP_FLASH_M3M4_F2F4 + select STM32_HAVE_IP_FMC_M3M4_V1 if STM32_HAVE_FMC + select STM32_HAVE_IP_FREERUN_M3M4_V1 + select STM32_HAVE_IP_FSMC_M3M4_V1 if STM32_HAVE_FSMC + select STM32_HAVE_IP_GPIO_M3M4_V1 + select STM32_HAVE_IP_I2C_M3M4_V1 + select STM32_HAVE_IP_I2S_M3M4_V1 + select STM32_HAVE_IP_ONESHOT_M3M4_V1 + select STM32_HAVE_IP_OTGHS_M3M4_V1 + select STM32_HAVE_IP_OTGFS_M3M4_V1 if STM32_HAVE_OTGFS + select STM32_HAVE_IP_PWR_M3M4_V1 + select STM32_HAVE_IP_RNG_M3M4_V1 if STM32_HAVE_RNG + select STM32_HAVE_IP_RTC_M3M4_V1 + select STM32_HAVE_IP_RTCC_M3M4_F4 + select STM32_HAVE_IP_SDIO_M3M4_V1 + select STM32_HAVE_IP_SPI_V2 + select STM32_HAVE_IP_SYSCFG_M3M4_V1 + select STM32_HAVE_IP_TIMERS_M3M4_V1 + select STM32_HAVE_IP_USART_V2 + select STM32_HAVE_IP_USBDEV_M3M4_V1 if STM32_HAVE_USBDEV + select STM32_HAVE_IP_USBFS_M3M4_V1 if STM32_HAVE_USBFS + select STM32_HAVE_IP_LTDC_M3M4_V1 if STM32_HAVE_LTDC + select STM32_HAVE_IP_WDG_M3M4_V1 + +config STM32_STM32F401xBC + bool + default n + select STM32_STM32F401 + +config STM32_STM32F401xDE + bool + default n + select STM32_STM32F401 + +config STM32_STM32F401 + bool + default n + select ARCH_CORTEXM4 + select STM32_STM32F4XXX + select STM32_HAVE_USART6 + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM3 + select STM32_HAVE_TIM4 + select STM32_HAVE_TIM5 + select STM32_HAVE_TIM9 + select STM32_HAVE_TIM10 + select STM32_HAVE_TIM11 + select STM32_HAVE_SPI2 + select STM32_HAVE_SPI3 + select STM32_HAVE_I2S3 + select STM32_HAVE_I2C3 + select STM32_HAVE_OTGFS + +config STM32_STM32F410 + bool + default n + select STM32_HAVE_USART6 + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM5 + select STM32_HAVE_TIM6 + select STM32_HAVE_TIM9 + select STM32_HAVE_TIM11 + select STM32_HAVE_SPI5 + select STM32_HAVE_DAC1 + +config STM32_STM32F411 + bool + default n + select STM32_HAVE_USART6 + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM3 + select STM32_HAVE_TIM4 + select STM32_HAVE_TIM5 + select STM32_HAVE_TIM9 + select STM32_HAVE_TIM10 + select STM32_HAVE_TIM11 + select STM32_HAVE_SPI2 + select STM32_HAVE_SPI3 + select STM32_HAVE_SPI4 + select STM32_HAVE_SPI5 + select STM32_HAVE_I2S3 + select STM32_HAVE_I2C3 + select STM32_HAVE_OTGFS + +config STM32_STM32F412 + bool + default n + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM3 + select STM32_HAVE_TIM4 + select STM32_HAVE_TIM5 + select STM32_HAVE_TIM8 + select STM32_HAVE_TIM9 + select STM32_HAVE_TIM12 + select STM32_HAVE_TIM13 + select STM32_HAVE_TIM14 + select STM32_HAVE_USART3 + select STM32_HAVE_USART2 + select STM32_HAVE_USART6 + select STM32_HAVE_I2C1 + select STM32_HAVE_I2C2 + select STM32_HAVE_I2C3 + select STM32_HAVE_SPI1 + select STM32_HAVE_SPI2 + select STM32_HAVE_SPI3 + select STM32_HAVE_CAN1 + select STM32_HAVE_CAN2 + select STM32_HAVE_OTGFS + select STM32_HAVE_I2SPLL + +config STM32_STM32F405 + bool + default n + select STM32_HAVE_FSMC + select STM32_HAVE_CCM + select STM32_HAVE_USART3 + select STM32_HAVE_UART4 + select STM32_HAVE_UART5 + select STM32_HAVE_USART6 + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM3 + select STM32_HAVE_TIM4 + select STM32_HAVE_TIM5 + select STM32_HAVE_TIM6 + select STM32_HAVE_TIM7 + select STM32_HAVE_TIM8 + select STM32_HAVE_TIM9 + select STM32_HAVE_TIM10 + select STM32_HAVE_TIM11 + select STM32_HAVE_TIM12 + select STM32_HAVE_TIM13 + select STM32_HAVE_TIM14 + select STM32_HAVE_ADC2 + select STM32_HAVE_ADC3 + select STM32_HAVE_CAN1 + select STM32_HAVE_CAN2 + select STM32_HAVE_DAC1 + select STM32_HAVE_DAC2 + select STM32_HAVE_SPI3 + select STM32_HAVE_I2S3 + select STM32_HAVE_I2C3 + select STM32_HAVE_RNG + select STM32_HAVE_OTGFS + +config STM32_STM32F407 + bool + default n + select STM32_HAVE_FSMC + select STM32_HAVE_CCM + select STM32_HAVE_USART3 + select STM32_HAVE_UART4 + select STM32_HAVE_UART5 + select STM32_HAVE_USART6 + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM3 + select STM32_HAVE_TIM4 + select STM32_HAVE_TIM5 + select STM32_HAVE_TIM6 + select STM32_HAVE_TIM7 + select STM32_HAVE_TIM8 + select STM32_HAVE_TIM9 + select STM32_HAVE_TIM10 + select STM32_HAVE_TIM11 + select STM32_HAVE_TIM12 + select STM32_HAVE_TIM13 + select STM32_HAVE_TIM14 + select STM32_HAVE_ADC2 + select STM32_HAVE_ADC3 + select STM32_HAVE_CAN1 + select STM32_HAVE_CAN2 + select STM32_HAVE_DAC1 + select STM32_HAVE_SPI3 + select STM32_HAVE_I2S3 + select STM32_HAVE_I2C3 + select STM32_HAVE_RNG + select STM32_HAVE_ETHMAC + select STM32_HAVE_OTGFS + +# This is really 427/437, but we treat the two the same. + +config STM32_STM32F427 + bool + default n + select STM32_HAVE_OVERDRIVE + select STM32_HAVE_FMC + select STM32_HAVE_CCM + select STM32_HAVE_USART3 + select STM32_HAVE_UART4 + select STM32_HAVE_UART5 + select STM32_HAVE_USART6 + select STM32_HAVE_UART7 + select STM32_HAVE_UART8 + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM3 + select STM32_HAVE_TIM4 + select STM32_HAVE_TIM5 + select STM32_HAVE_TIM6 + select STM32_HAVE_TIM7 + select STM32_HAVE_TIM8 + select STM32_HAVE_TIM9 + select STM32_HAVE_TIM10 + select STM32_HAVE_TIM11 + select STM32_HAVE_TIM12 + select STM32_HAVE_TIM13 + select STM32_HAVE_TIM14 + select STM32_HAVE_ADC2 + select STM32_HAVE_ADC3 + select STM32_HAVE_CAN1 + select STM32_HAVE_CAN2 + select STM32_HAVE_DAC1 + select STM32_HAVE_RNG + select STM32_HAVE_ETHMAC + select STM32_HAVE_SPI2 + select STM32_HAVE_SPI3 + select STM32_HAVE_SPI4 + select STM32_HAVE_SPI5 + select STM32_HAVE_I2S3 + select STM32_HAVE_I2C3 + select STM32_HAVE_OTGFS + select STM32_HAVE_SPI6 + select STM32_HAVE_I2SPLL + +# This is really 429/439, but we treat the two the same. + +config STM32_STM32F429 + bool + default n + select STM32_HAVE_DMA2D + select STM32_HAVE_IP_DMA2D_M3M4_V1 + select STM32_HAVE_OVERDRIVE + select STM32_HAVE_FMC + select STM32_HAVE_LTDC + select STM32_HAVE_CCM + select STM32_HAVE_USART3 + select STM32_HAVE_UART4 + select STM32_HAVE_UART5 + select STM32_HAVE_USART6 + select STM32_HAVE_UART7 + select STM32_HAVE_UART8 + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM3 + select STM32_HAVE_TIM4 + select STM32_HAVE_TIM5 + select STM32_HAVE_TIM6 + select STM32_HAVE_TIM7 + select STM32_HAVE_TIM8 + select STM32_HAVE_TIM9 + select STM32_HAVE_TIM10 + select STM32_HAVE_TIM11 + select STM32_HAVE_TIM12 + select STM32_HAVE_TIM13 + select STM32_HAVE_TIM14 + select STM32_HAVE_ADC2 + select STM32_HAVE_ADC3 + select STM32_HAVE_CAN1 + select STM32_HAVE_CAN2 + select STM32_HAVE_DAC1 + select STM32_HAVE_RNG + select STM32_HAVE_ETHMAC + select STM32_HAVE_SPI2 + select STM32_HAVE_SPI3 + select STM32_HAVE_I2S3 + select STM32_HAVE_SPI4 + select STM32_HAVE_SPI5 + select STM32_HAVE_SPI6 + select STM32_HAVE_I2S3 + select STM32_HAVE_I2C3 + select STM32_HAVE_OTGFS + +config STM32_STM32F446 + bool + default n + select STM32_HAVE_OVERDRIVE + select STM32_HAVE_USART3 + select STM32_HAVE_UART4 + select STM32_HAVE_UART5 + select STM32_HAVE_USART6 + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM3 + select STM32_HAVE_TIM4 + select STM32_HAVE_TIM5 + select STM32_HAVE_TIM6 + select STM32_HAVE_TIM7 + select STM32_HAVE_TIM8 + select STM32_HAVE_TIM9 + select STM32_HAVE_TIM10 + select STM32_HAVE_TIM11 + select STM32_HAVE_TIM12 + select STM32_HAVE_TIM13 + select STM32_HAVE_TIM14 + select STM32_HAVE_ADC2 + select STM32_HAVE_ADC3 + select STM32_HAVE_CAN1 + select STM32_HAVE_CAN2 + select STM32_HAVE_DAC1 + select STM32_HAVE_SPI3 + select STM32_HAVE_SPI4 + select STM32_HAVE_I2S3 + select STM32_HAVE_I2C3 + select STM32_HAVE_OTGFS + select STM32_HAVE_SAIPLL + select STM32_HAVE_I2SPLL + +# This is really 469/479, but we treat the two the same. + +config STM32_STM32F469 + bool + default n + select STM32_HAVE_DMA2D + select STM32_HAVE_IP_DMA2D_M3M4_V1 + select STM32_HAVE_OVERDRIVE + select STM32_HAVE_FMC + select STM32_HAVE_LTDC + select STM32_HAVE_CCM + select STM32_HAVE_USART3 + select STM32_HAVE_UART4 + select STM32_HAVE_UART5 + select STM32_HAVE_USART6 + select STM32_HAVE_UART7 + select STM32_HAVE_UART8 + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM3 + select STM32_HAVE_TIM4 + select STM32_HAVE_TIM5 + select STM32_HAVE_TIM6 + select STM32_HAVE_TIM7 + select STM32_HAVE_TIM8 + select STM32_HAVE_TIM9 + select STM32_HAVE_TIM10 + select STM32_HAVE_TIM11 + select STM32_HAVE_TIM12 + select STM32_HAVE_TIM13 + select STM32_HAVE_TIM14 + select STM32_HAVE_ADC2 + select STM32_HAVE_ADC3 + select STM32_HAVE_CAN1 + select STM32_HAVE_CAN2 + select STM32_HAVE_DAC1 + select STM32_HAVE_RNG + select STM32_HAVE_SPI3 + select STM32_HAVE_SPI4 + select STM32_HAVE_SPI5 + select STM32_HAVE_SPI6 + select STM32_HAVE_OTGFS + select STM32_HAVE_SAIPLL + select STM32_HAVE_I2SPLL + select STM32_HAVE_I2S3 + select STM32_HAVE_I2C3 diff --git a/arch/arm/src/stm32f4/Make.defs b/arch/arm/src/stm32f4/Make.defs new file mode 100644 index 0000000000000..061c17116243d --- /dev/null +++ b/arch/arm/src/stm32f4/Make.defs @@ -0,0 +1,27 @@ +############################################################################ +# arch/arm/src/stm32f4/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include armv7-m/Make.defs + +CHIP_CSRCS = stm32_rcc.c + +include common/stm32/Make.defs diff --git a/arch/arm/src/stm32f4/chip.h b/arch/arm/src/stm32f4/chip.h new file mode 100644 index 0000000000000..647bbd778c82e --- /dev/null +++ b/arch/arm/src/stm32f4/chip.h @@ -0,0 +1,59 @@ +/**************************************************************************** + * arch/arm/src/stm32f4/chip.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32F4_CHIP_H +#define __ARCH_ARM_SRC_STM32F4_CHIP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/* Include the chip capabilities file */ + +#include + +/* Include the chip interrupt definition file */ + +#include + +/* Include the chip memory map */ + +#include "hardware/stm32_memorymap.h" + +/* Include the chip pinmap */ + +#include "hardware/stm32_pinmap.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Provide the required number of peripheral interrupt vector + * definitions as * well. The definition STM32_IRQ_NEXTINTS simply comes + * from the chip-specific * IRQ header file included by arch/stm32/irq.h. + */ + +#define ARMV7M_PERIPHERAL_INTERRUPTS STM32_IRQ_NEXTINTS + +#endif /* __ARCH_ARM_SRC_STM32F4_CHIP_H */ diff --git a/arch/arm/src/stm32f4/hardware/stm32_memorymap.h b/arch/arm/src/stm32f4/hardware/stm32_memorymap.h new file mode 100644 index 0000000000000..c2b208c9c2719 --- /dev/null +++ b/arch/arm/src/stm32f4/hardware/stm32_memorymap.h @@ -0,0 +1,17 @@ +/**************************************************************************** + * arch/arm/src/stm32f4/hardware/stm32_memorymap.h + * + * SPDX-License-Identifier: Apache-2.0 + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32F4_HARDWARE_STM32_MEMORYMAP_H +#define __ARCH_ARM_SRC_STM32F4_HARDWARE_STM32_MEMORYMAP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "hardware/stm32f40xxx_memorymap.h" + +#endif /* __ARCH_ARM_SRC_STM32F4_HARDWARE_STM32_MEMORYMAP_H */ diff --git a/arch/arm/src/stm32f4/hardware/stm32_pinmap.h b/arch/arm/src/stm32f4/hardware/stm32_pinmap.h new file mode 100644 index 0000000000000..35b04147293aa --- /dev/null +++ b/arch/arm/src/stm32f4/hardware/stm32_pinmap.h @@ -0,0 +1,25 @@ +/**************************************************************************** + * arch/arm/src/stm32f4/hardware/stm32_pinmap.h + * + * SPDX-License-Identifier: Apache-2.0 + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32F4_HARDWARE_STM32_PINMAP_H +#define __ARCH_ARM_SRC_STM32F4_HARDWARE_STM32_PINMAP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#if defined(CONFIG_STM32_STM32F412) +# include "hardware/stm32f412xx_pinmap.h" +#elif defined(CONFIG_STM32_STM32F4XXX) +# include "hardware/stm32f40xxx_pinmap.h" +#else +# error "Unsupported STM32F4 pin map" +#endif + +#endif /* __ARCH_ARM_SRC_STM32F4_HARDWARE_STM32_PINMAP_H */ diff --git a/arch/arm/src/stm32/hardware/stm32f40xxx_gpio.h b/arch/arm/src/stm32f4/hardware/stm32f40xxx_gpio.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32f40xxx_gpio.h rename to arch/arm/src/stm32f4/hardware/stm32f40xxx_gpio.h index 95ce98d3d930e..167dedbd48409 100644 --- a/arch/arm/src/stm32/hardware/stm32f40xxx_gpio.h +++ b/arch/arm/src/stm32f4/hardware/stm32f40xxx_gpio.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32f40xxx_gpio.h + * arch/arm/src/stm32f4/hardware/stm32f40xxx_gpio.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/hardware/stm32f40xxx_memorymap.h b/arch/arm/src/stm32f4/hardware/stm32f40xxx_memorymap.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32f40xxx_memorymap.h rename to arch/arm/src/stm32f4/hardware/stm32f40xxx_memorymap.h index 72fe218a4441b..c1549f7b99444 100644 --- a/arch/arm/src/stm32/hardware/stm32f40xxx_memorymap.h +++ b/arch/arm/src/stm32f4/hardware/stm32f40xxx_memorymap.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32f40xxx_memorymap.h + * arch/arm/src/stm32f4/hardware/stm32f40xxx_memorymap.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/hardware/stm32f40xxx_pinmap.h b/arch/arm/src/stm32f4/hardware/stm32f40xxx_pinmap.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32f40xxx_pinmap.h rename to arch/arm/src/stm32f4/hardware/stm32f40xxx_pinmap.h index 0b40bdd84223e..4f97953d1606c 100644 --- a/arch/arm/src/stm32/hardware/stm32f40xxx_pinmap.h +++ b/arch/arm/src/stm32f4/hardware/stm32f40xxx_pinmap.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32f40xxx_pinmap.h + * arch/arm/src/stm32f4/hardware/stm32f40xxx_pinmap.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/hardware/stm32f40xxx_rcc.h b/arch/arm/src/stm32f4/hardware/stm32f40xxx_rcc.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32f40xxx_rcc.h rename to arch/arm/src/stm32f4/hardware/stm32f40xxx_rcc.h index 08bd4e7328ed3..d4e56f3f29654 100644 --- a/arch/arm/src/stm32/hardware/stm32f40xxx_rcc.h +++ b/arch/arm/src/stm32f4/hardware/stm32f40xxx_rcc.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32f40xxx_rcc.h + * arch/arm/src/stm32f4/hardware/stm32f40xxx_rcc.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/hardware/stm32f40xxx_syscfg.h b/arch/arm/src/stm32f4/hardware/stm32f40xxx_syscfg.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32f40xxx_syscfg.h rename to arch/arm/src/stm32f4/hardware/stm32f40xxx_syscfg.h index 19da1a40b392b..9beeef94ebbcf 100644 --- a/arch/arm/src/stm32/hardware/stm32f40xxx_syscfg.h +++ b/arch/arm/src/stm32f4/hardware/stm32f40xxx_syscfg.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32f40xxx_syscfg.h + * arch/arm/src/stm32f4/hardware/stm32f40xxx_syscfg.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/hardware/stm32f412xx_pinmap.h b/arch/arm/src/stm32f4/hardware/stm32f412xx_pinmap.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32f412xx_pinmap.h rename to arch/arm/src/stm32f4/hardware/stm32f412xx_pinmap.h index 0ecba4ca90387..305547e1888df 100644 --- a/arch/arm/src/stm32/hardware/stm32f412xx_pinmap.h +++ b/arch/arm/src/stm32f4/hardware/stm32f412xx_pinmap.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32f412xx_pinmap.h + * arch/arm/src/stm32f4/hardware/stm32f412xx_pinmap.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32f4/stm32.h b/arch/arm/src/stm32f4/stm32.h new file mode 100644 index 0000000000000..56a9dbc8151a7 --- /dev/null +++ b/arch/arm/src/stm32f4/stm32.h @@ -0,0 +1,69 @@ +/**************************************************************************** + * arch/arm/src/stm32f4/stm32.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32_STM32_H +#define __ARCH_ARM_SRC_STM32_STM32_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include +#include + +#include "arm_internal.h" + +/* Peripherals **************************************************************/ + +#include "chip.h" +#include "stm32_adc.h" +#include "stm32_can.h" +#include "stm32_comp.h" +#include "stm32_dbgmcu.h" +#include "stm32_dma.h" +#include "stm32_dac_m3m4_v1.h" +#include "stm32_exti.h" +#include "stm32_flash.h" +#include "stm32_fmc_m3m4_v1.h" +#include "stm32_fsmc_m3m4_v1.h" +#include "stm32_gpio.h" +#include "stm32_i2c.h" +#include "stm32_ltdc_m3m4_v1.h" +#include "stm32_opamp_m3m4_v1.h" +#include "stm32_pwr.h" +#include "stm32_rcc.h" +#include "stm32_rtc.h" +#include "stm32_sdio_m3m4_v1.h" +#include "stm32_spi.h" +#include "stm32_i2s.h" +#include "stm32_tim.h" +#include "stm32_uart.h" +#if defined(CONFIG_USBDEV) && defined(CONFIG_STM32_USB) +# include "stm32_usbdev.h" +#endif +#include "stm32_wdg.h" +#include "stm32_lowputc.h" +#include "stm32_eth_m3m4_v1.h" + +#endif /* __ARCH_ARM_SRC_STM32_STM32_H */ diff --git a/arch/arm/src/stm32f4/stm32_rcc.c b/arch/arm/src/stm32f4/stm32_rcc.c new file mode 100644 index 0000000000000..0c03fece5cda6 --- /dev/null +++ b/arch/arm/src/stm32f4/stm32_rcc.c @@ -0,0 +1,234 @@ +/**************************************************************************** + * arch/arm/src/stm32f4/stm32_rcc.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include + +#include "arm_internal.h" +#include "chip.h" +#include "stm32_gpio.h" +#include "stm32_rcc.h" +#include "stm32_rtc.h" +#include "stm32_flash.h" +#include "stm32.h" +#include "stm32_waste.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1, + "Configure BOARD_LOOPSPERMSEC to non-default value."); + +/* Allow up to 100 milliseconds for the high speed clock to become ready. + * that is a very long delay, but if the clock does not become ready we are + * hosed anyway. + */ + +#define HSERDY_TIMEOUT (100 * CONFIG_BOARD_LOOPSPERMSEC) + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/* Include chip-specific clocking initialization logic */ + +#include "stm32f40xxx_rcc.c" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#if defined(CONFIG_STM32_STM32L15XX) +# define STM32_RCC_XXX STM32_RCC_CSR +# define RCC_XXX_YYYRST RCC_CSR_RTCRST +#else +# define STM32_RCC_XXX STM32_RCC_BDCR +# define RCC_XXX_YYYRST RCC_BDCR_BDRST +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: rcc_resetbkp + * + * Description: + * The RTC needs to reset the Backup Domain to change RTCSEL and resetting + * the Backup Domain renders to disabling the LSE as consequence. + * In order to avoid resetting the Backup Domain when we already + * configured LSE we will reset the Backup Domain early (here). + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +#if defined(CONFIG_STM32_RTC) && defined(CONFIG_STM32_PWR) && !defined(CONFIG_STM32_STM32F10XX) +static inline void rcc_resetbkp(void) +{ + uint32_t regval; + + /* Check if the RTC is already configured */ + + stm32_pwr_initbkp(false); + + regval = getreg32(RTC_MAGIC_REG); + if (regval != RTC_MAGIC && regval != RTC_MAGIC_TIME_SET) + { + stm32_pwr_enablebkp(true); + + /* We might be changing RTCSEL - to ensure such changes work, we must + * reset the backup domain (having backed up the RTC_MAGIC token) + */ + + modifyreg32(STM32_RCC_XXX, 0, RCC_XXX_YYYRST); + modifyreg32(STM32_RCC_XXX, RCC_XXX_YYYRST, 0); + + stm32_pwr_enablebkp(false); + } +} +#else +# define rcc_resetbkp() +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_clockconfig + * + * Description: + * Called to establish the clock settings based on the values in board.h. + * This function (by default) will reset most everything, enable the PLL, + * and enable peripheral clocking for all peripherals enabled in the NuttX + * configuration file. + * + * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then clocking + * will be enabled by an externally provided, board-specific function + * called stm32_board_clockconfig(). + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void stm32_clockconfig(void) +{ + /* Make sure that we are starting in the reset state */ + + rcc_reset(); + + /* Reset backup domain if appropriate */ + + rcc_resetbkp(); + +#if defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) + + /* Invoke Board Custom Clock Configuration */ + + stm32_board_clockconfig(); + +#else + + /* Invoke standard, fixed clock configuration based on definitions + * in board.h + */ + + stm32_stdclockconfig(); + +#endif + + /* Enable peripheral clocking */ + + rcc_enableperipherals(); + +#ifdef CONFIG_STM32_SYSCFG_IOCOMPENSATION + /* Enable I/O Compensation */ + + stm32_iocompensation(); +#endif +} + +/**************************************************************************** + * Name: stm32_clockenable + * + * Description: + * Re-enable the clock and restore the clock settings based on settings + * in board.h. This function is only available to support low-power + * modes of operation: When re-awakening from deep-sleep modes, it is + * necessary to re-enable/re-start the PLL + * + * This functional performs a subset of the operations performed by + * stm32_clockconfig(): It does not reset any devices, and it does not + * reset the currently enabled peripheral clocks. + * + * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then clocking + * will be enabled by an externally provided, board-specific function + * called stm32_board_clockconfig(). + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_PM +void stm32_clockenable(void) +{ +#if defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) + + /* Invoke Board Custom Clock Configuration */ + + stm32_board_clockconfig(); + +#else + + /* Invoke standard, fixed clock configuration based on definitions + * in board.h + */ + + stm32_stdclockconfig(); + +#endif +} +#endif diff --git a/arch/arm/src/stm32/stm32f40xxx_alarm.h b/arch/arm/src/stm32f4/stm32f40xxx_alarm.h similarity index 98% rename from arch/arm/src/stm32/stm32f40xxx_alarm.h rename to arch/arm/src/stm32f4/stm32f40xxx_alarm.h index 98daa796e7b24..04e096a63cb65 100644 --- a/arch/arm/src/stm32/stm32f40xxx_alarm.h +++ b/arch/arm/src/stm32f4/stm32f40xxx_alarm.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32f40xxx_alarm.h + * arch/arm/src/stm32f4/stm32f40xxx_alarm.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/stm32f40xxx_rcc.c b/arch/arm/src/stm32f4/stm32f40xxx_rcc.c similarity index 99% rename from arch/arm/src/stm32/stm32f40xxx_rcc.c rename to arch/arm/src/stm32f4/stm32f40xxx_rcc.c index 453ced82d2b37..f5f8dc84a6f71 100644 --- a/arch/arm/src/stm32/stm32f40xxx_rcc.c +++ b/arch/arm/src/stm32f4/stm32f40xxx_rcc.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32f40xxx_rcc.c + * arch/arm/src/stm32f4/stm32f40xxx_rcc.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32f7/CMakeLists.txt b/arch/arm/src/stm32f7/CMakeLists.txt index 89cca465803d9..bc870799cdd66 100644 --- a/arch/arm/src/stm32f7/CMakeLists.txt +++ b/arch/arm/src/stm32f7/CMakeLists.txt @@ -33,17 +33,15 @@ list( stm32_rcc.c stm32_serial.c stm32_start.c - stm32_capture.c - stm32_uid.c - stm32_waste.c) + stm32_capture.c) -if(CONFIG_STM32F7_TICKLESS_TIMER) +if(CONFIG_STM32_TICKLESS_TIMER) list(APPEND SRCS stm32_tickless.c) else() list(APPEND SRCS stm32_timerisr.c) endif() -if(CONFIG_STM32F7_PROGMEM) +if(CONFIG_STM32_PROGMEM) list(APPEND SRCS stm32_flash.c) endif() @@ -55,7 +53,7 @@ if(CONFIG_ARMV7M_DTCM) list(APPEND SRCS stm32_dtcm.c) endif() -if(CONFIG_STM32F7_DMA) +if(CONFIG_STM32_DMA) list(APPEND SRCS stm32_dma.c) endif() @@ -66,11 +64,11 @@ if(CONFIG_PM) endif() endif() -if(CONFIG_STM32F7_PWR) +if(CONFIG_STM32_PWR) list(APPEND SRCS stm32_pwr.c stm32_exti_pwr.c) endif() -if(CONFIG_STM32F7_RTC) +if(CONFIG_STM32_RTC) list(APPEND SRCS stm32_rtc.c) if(CONFIG_RTC_ALARM) list(APPEND SRCS stm32_exti_alarm.c) @@ -83,27 +81,31 @@ if(CONFIG_STM32F7_RTC) endif() endif() -if(CONFIG_STM32F7_IWDG OR CONFIG_STM32F7_RTC_LSICLOCK) +if(CONFIG_STM32_FMC) + list(APPEND SRCS stm32_fmc.c) +endif() + +if(CONFIG_STM32_IWDG OR CONFIG_STM32_RTC_LSICLOCK) list(APPEND SRCS stm32_lsi.c) endif() -if(CONFIG_STM32F7_RTC_LSECLOCK) +if(CONFIG_STM32_RTC_LSECLOCK) list(APPEND SRCS stm32_lse.c) endif() -if(CONFIG_STM32F7_I2C) +if(CONFIG_STM32_I2C) list(APPEND SRCS stm32_i2c.c) endif() -if(CONFIG_STM32F7_I2S) +if(CONFIG_STM32_I2S) list(APPEND SRCS stm32_i2s.c) endif() -if(CONFIG_STM32F7_SPI) +if(CONFIG_STM32_SPI) list(APPEND SRCS stm32_spi.c) endif() -if(CONFIG_STM32F7_SDMMC) +if(CONFIG_STM32_SDMMC) list(APPEND SRCS stm32_sdmmc.c) endif() @@ -120,25 +122,25 @@ if(CONFIG_USBHOST) endif() endif() -if(CONFIG_STM32F7_TIM) +if(CONFIG_STM32_TIM) list(APPEND SRCS stm32_tim.c stm32_tim_lowerhalf.c) endif() -if(CONFIG_STM32F7_ADC) +if(CONFIG_STM32_ADC) list(APPEND SRCS stm32_adc.c) endif() -if(CONFIG_STM32F7_QUADSPI) +if(CONFIG_STM32_QSPI) list(APPEND SRCS stm32_qspi.c) endif() -if(CONFIG_STM32F7_RTC) +if(CONFIG_STM32_RTC) if(CONFIG_RTC_ALARM) list(APPEND SRCS stm32_exti_alarm.c) endif() endif() -if(CONFIG_STM32F7_ETHMAC) +if(CONFIG_STM32_ETHMAC) list(APPEND SRCS stm32_ethernet.c) endif() @@ -146,19 +148,19 @@ if(CONFIG_DEBUG_FEATURES) list(APPEND SRCS stm32_dumpgpio.c) endif() -if(CONFIG_STM32F7_BBSRAM) +if(CONFIG_STM32_BBSRAM) list(APPEND SRCS stm32_bbsram.c) endif() -if(CONFIG_STM32F7_RNG) +if(CONFIG_STM32_RNG) list(APPEND SRCS stm32_rng.c) endif() -if(CONFIG_STM32F7_LTDC) +if(CONFIG_STM32_LTDC) list(APPEND SRCS stm32_ltdc.c) endif() -if(CONFIG_STM32F7_DMA2D) +if(CONFIG_STM32_DMA2D) list(APPEND SRCS stm32_dma2d.c) endif() @@ -166,19 +168,19 @@ if(CONFIG_SENSORS_QENCODER) list(APPEND SRCS stm32_qencoder.c) endif() -if(CONFIG_STM32F7_CAN_CHARDRIVER) +if(CONFIG_STM32_CAN_CHARDRIVER) list(APPEND SRCS stm32_can.c) endif() -if(CONFIG_STM32F7_CAN_SOCKET) +if(CONFIG_STM32_CAN_SOCKET) list(APPEND SRCS stm32_can_sock.c) endif() -if(CONFIG_STM32F7_SAI) +if(CONFIG_STM32_SAI) list(APPEND SRCS stm32_sai.c) endif() -if(CONFIG_STM32F7_PWM) +if(CONFIG_STM32_PWM) list(APPEND SRCS stm32_pwm.c) endif() @@ -186,8 +188,10 @@ if(CONFIG_PULSECOUNT) list(APPEND SRCS stm32_pulsecount.c) endif() -if(CONFIG_STM32F7_FOC) +if(CONFIG_STM32_FOC) list(APPEND SRCS stm32_foc.c) endif() target_sources(arch PRIVATE ${SRCS}) + +add_subdirectory(${NUTTX_DIR}/arch/arm/src/common/stm32 stm32_common) diff --git a/arch/arm/src/stm32f7/Kconfig b/arch/arm/src/stm32f7/Kconfig index ec6c5361ede17..c1d9712cd83dc 100644 --- a/arch/arm/src/stm32f7/Kconfig +++ b/arch/arm/src/stm32f7/Kconfig @@ -7,6 +7,43 @@ if ARCH_CHIP_STM32F7 comment "STM32 F7 Configuration Options" +config STM32_F7_PERIPHERALS + bool + default ARCH_CHIP_STM32F7 + select STM32_HAVE_ADC1 + select STM32_HAVE_ADC2 + select STM32_HAVE_ADC3 + select STM32_HAVE_COMMON_FOC + select STM32_HAVE_DAC1 + select STM32_HAVE_DAC2 + select STM32_HAVE_DMA1 + select STM32_HAVE_DMA2 + select STM32_HAVE_ETHERNET if STM32_HAVE_ETHRNET + select STM32_HAVE_I2C1 + select STM32_HAVE_I2C2 + select STM32_HAVE_I2C3 + select STM32_HAVE_I2C4 + select STM32_HAVE_I2S3 if !STM32_SPI3 + select STM32_HAVE_IOCOMPENSATION + select STM32_HAVE_LPTIM1 + select STM32_HAVE_OTGFS + select STM32_HAVE_RTC_SUBSECONDS + select STM32_HAVE_SDMMC1 + select STM32_HAVE_SPI1 + select STM32_HAVE_SPI2 + select STM32_HAVE_SPI3 + select STM32_HAVE_SYSCFG + select STM32_HAVE_UART4 + select STM32_HAVE_UART5 + select STM32_HAVE_UART7 + select STM32_HAVE_UART8 + select STM32_HAVE_USART1 + select STM32_HAVE_USART2 + select STM32_HAVE_USART3 + select STM32_HAVE_USART6 + select STM32_HAVE_FLASH_ART_ACCELERATOR + select STM32_HAVE_IP_WDG_M3M4_V1 + choice prompt "STM32 F7 Chip Selection" default ARCH_CHIP_STM32F746NG @@ -14,7494 +51,1151 @@ choice config ARCH_CHIP_STM32F722RC bool "STM32F722RC" - select STM32F7_STM32F722XX - select STM32F7_FLASH_CONFIG_C + select STM32_STM32F722XX + select STM32_FLASH_CONFIG_C select STM32F7_IO_CONFIG_R ---help--- STM32 F7 Cortex M7, 256 FLASH, 256K (176+16+64) Kb SRAM config ARCH_CHIP_STM32F722RE bool "STM32F722RE" - select STM32F7_STM32F722XX - select STM32F7_FLASH_CONFIG_E + select STM32_STM32F722XX + select STM32_FLASH_CONFIG_E select STM32F7_IO_CONFIG_R ---help--- STM32 F7 Cortex M7, 512 FLASH, 256K (176+16+64) Kb SRAM config ARCH_CHIP_STM32F722VC bool "STM32F722VC" - select STM32F7_STM32F722XX - select STM32F7_FLASH_CONFIG_C + select STM32_STM32F722XX + select STM32_FLASH_CONFIG_C select STM32F7_IO_CONFIG_V ---help--- STM32 F7 Cortex M7, 256 FLASH, 256K (176+16+64) Kb SRAM config ARCH_CHIP_STM32F722VE bool "STM32F722VE" - select STM32F7_STM32F722XX - select STM32F7_FLASH_CONFIG_E + select STM32_STM32F722XX + select STM32_FLASH_CONFIG_E select STM32F7_IO_CONFIG_V ---help--- STM32 F7 Cortex M7, 512 FLASH, 256K (176+16+64) Kb SRAM config ARCH_CHIP_STM32F722ZC bool "STM32F722ZC" - select STM32F7_STM32F722XX - select STM32F7_FLASH_CONFIG_C + select STM32_STM32F722XX + select STM32_FLASH_CONFIG_C select STM32F7_IO_CONFIG_Z ---help--- STM32 F7 Cortex M7, 256 FLASH, 256K (176+16+64) Kb SRAM config ARCH_CHIP_STM32F722ZE bool "STM32F722ZE" - select STM32F7_STM32F722XX - select STM32F7_FLASH_CONFIG_E + select STM32_STM32F722XX + select STM32_FLASH_CONFIG_E select STM32F7_IO_CONFIG_Z ---help--- STM32 F7 Cortex M7, 512 FLASH, 256K (176+16+64) Kb SRAM config ARCH_CHIP_STM32F722IC bool "STM32F722IC" - select STM32F7_STM32F722XX - select STM32F7_FLASH_CONFIG_C + select STM32_STM32F722XX + select STM32_FLASH_CONFIG_C select STM32F7_IO_CONFIG_I ---help--- STM32 F7 Cortex M7, 256 FLASH, 256K (176+16+64) Kb SRAM config ARCH_CHIP_STM32F722IE bool "STM32F722IE" - select STM32F7_STM32F722XX - select STM32F7_FLASH_CONFIG_E + select STM32_STM32F722XX + select STM32_FLASH_CONFIG_E select STM32F7_IO_CONFIG_I ---help--- STM32 F7 Cortex M7, 512 FLASH, 256K (176+16+64) Kb SRAM config ARCH_CHIP_STM32F723RC bool "STM32F723RC" - select STM32F7_STM32F723XX - select STM32F7_FLASH_CONFIG_C + select STM32_STM32F723XX + select STM32_FLASH_CONFIG_C select STM32F7_IO_CONFIG_R ---help--- STM32 F7 Cortex M7, 256 FLASH, 256K (176+16+64) Kb SRAM config ARCH_CHIP_STM32F723RE bool "STM32F723RE" - select STM32F7_STM32F723XX - select STM32F7_FLASH_CONFIG_E + select STM32_STM32F723XX + select STM32_FLASH_CONFIG_E select STM32F7_IO_CONFIG_R ---help--- STM32 F7 Cortex M7, 512 FLASH, 256K (176+16+64) Kb SRAM config ARCH_CHIP_STM32F723VC bool "STM32F723VC" - select STM32F7_STM32F723XX - select STM32F7_HAVE_INTERNAL_ULPI - select STM32F7_FLASH_CONFIG_C + select STM32_STM32F723XX + select STM32_HAVE_INTERNAL_ULPI + select STM32_FLASH_CONFIG_C select STM32F7_IO_CONFIG_V ---help--- STM32 F7 Cortex M7, 256 FLASH, 256K (176+16+64) Kb SRAM config ARCH_CHIP_STM32F723VE bool "STM32F723VE" - select STM32F7_STM32F723XX - select STM32F7_HAVE_INTERNAL_ULPI - select STM32F7_FLASH_CONFIG_E + select STM32_STM32F723XX + select STM32_HAVE_INTERNAL_ULPI + select STM32_FLASH_CONFIG_E select STM32F7_IO_CONFIG_V ---help--- STM32 F7 Cortex M7, 512 FLASH, 256K (176+16+64) Kb SRAM config ARCH_CHIP_STM32F723ZC bool "STM32F723ZC" - select STM32F7_STM32F723XX - select STM32F7_HAVE_INTERNAL_ULPI - select STM32F7_FLASH_CONFIG_C + select STM32_STM32F723XX + select STM32_HAVE_INTERNAL_ULPI + select STM32_FLASH_CONFIG_C select STM32F7_IO_CONFIG_Z ---help--- STM32 F7 Cortex M7, 256 FLASH, 256K (176+16+64) Kb SRAM config ARCH_CHIP_STM32F723ZE bool "STM32F723ZE" - select STM32F7_STM32F723XX - select STM32F7_HAVE_INTERNAL_ULPI - select STM32F7_FLASH_CONFIG_E + select STM32_STM32F723XX + select STM32_HAVE_INTERNAL_ULPI + select STM32_FLASH_CONFIG_E select STM32F7_IO_CONFIG_Z ---help--- STM32 F7 Cortex M7, 512 FLASH, 256K (176+16+64) Kb SRAM config ARCH_CHIP_STM32F723IC bool "STM32F723IC" - select STM32F7_STM32F723XX - select STM32F7_HAVE_INTERNAL_ULPI - select STM32F7_FLASH_CONFIG_C + select STM32_STM32F723XX + select STM32_HAVE_INTERNAL_ULPI + select STM32_FLASH_CONFIG_C select STM32F7_IO_CONFIG_I ---help--- STM32 F7 Cortex M7, 256 FLASH, 256K (176+16+64) Kb SRAM config ARCH_CHIP_STM32F723IE bool "STM32F723IE" - select STM32F7_STM32F723XX - select STM32F7_HAVE_INTERNAL_ULPI - select STM32F7_FLASH_CONFIG_E + select STM32_STM32F723XX + select STM32_HAVE_INTERNAL_ULPI + select STM32_FLASH_CONFIG_E select STM32F7_IO_CONFIG_I ---help--- STM32 F7 Cortex M7, 512 FLASH, 256K (176+16+64) Kb SRAM config ARCH_CHIP_STM32F745VG bool "STM32F745VG" - select STM32F7_STM32F745XX - select STM32F7_FLASH_CONFIG_G + select STM32_STM32F745XX + select STM32_FLASH_CONFIG_G select STM32F7_IO_CONFIG_V ---help--- STM32 F7 Cortex M7, 1024 FLASH, 320K (240+16+64) Kb SRAM config ARCH_CHIP_STM32F745VE bool "STM32F745VE" - select STM32F7_STM32F745XX - select STM32F7_FLASH_CONFIG_E + select STM32_STM32F745XX + select STM32_FLASH_CONFIG_E select STM32F7_IO_CONFIG_V ---help--- STM32 F7 Cortex M7, 512 FLASH, 320K (240+16+64) Kb SRAM config ARCH_CHIP_STM32F745IG bool "STM32F745IG" - select STM32F7_STM32F745XX - select STM32F7_FLASH_CONFIG_G + select STM32_STM32F745XX + select STM32_FLASH_CONFIG_G select STM32F7_IO_CONFIG_I ---help--- STM32 F7 Cortex M7, 1024 FLASH, 320K (240+16+64) Kb SRAM config ARCH_CHIP_STM32F745IE bool "STM32F745IE" - select STM32F7_STM32F745XX - select STM32F7_FLASH_CONFIG_E + select STM32_STM32F745XX + select STM32_FLASH_CONFIG_E select STM32F7_IO_CONFIG_I ---help--- STM32 F7 Cortex M7, 512 FLASH, 320K (240+16+64) Kb SRAM config ARCH_CHIP_STM32F745ZE bool "STM32F745ZE" - select STM32F7_STM32F745XX - select STM32F7_FLASH_CONFIG_E + select STM32_STM32F745XX + select STM32_FLASH_CONFIG_E select STM32F7_IO_CONFIG_Z ---help--- STM32 F7 Cortex M7, 512 FLASH, 320K (240+16+64) Kb SRAM config ARCH_CHIP_STM32F745ZG bool "STM32F745ZG" - select STM32F7_STM32F745XX - select STM32F7_FLASH_CONFIG_G + select STM32_STM32F745XX + select STM32_FLASH_CONFIG_G select STM32F7_IO_CONFIG_Z ---help--- STM32 F7 Cortex M7, 1024 FLASH, 320K (240+16+64) Kb SRAM config ARCH_CHIP_STM32F746BG bool "STM32F746BG" - select STM32F7_STM32F746XX - select STM32F7_FLASH_CONFIG_G + select STM32_STM32F746XX + select STM32_FLASH_CONFIG_G select STM32F7_IO_CONFIG_B ---help--- STM32 F7 Cortex M7, 1024 FLASH, 320K (240+16+64) Kb SRAM config ARCH_CHIP_STM32F746VG bool "STM32F746VG" - select STM32F7_STM32F746XX - select STM32F7_FLASH_CONFIG_G + select STM32_STM32F746XX + select STM32_FLASH_CONFIG_G select STM32F7_IO_CONFIG_V ---help--- STM32 F7 Cortex M7, 1024 FLASH, 320K (240+16+64) Kb SRAM config ARCH_CHIP_STM32F746VE bool "STM32F746VE" - select STM32F7_STM32F746XX - select STM32F7_FLASH_CONFIG_E + select STM32_STM32F746XX + select STM32_FLASH_CONFIG_E select STM32F7_IO_CONFIG_V ---help--- STM32 F7 Cortex M7, 512 FLASH, 320K (240+16+64) Kb SRAM config ARCH_CHIP_STM32F746BE bool "STM32F746BE" - select STM32F7_STM32F746XX - select STM32F7_FLASH_CONFIG_E + select STM32_STM32F746XX + select STM32_FLASH_CONFIG_E select STM32F7_IO_CONFIG_B ---help--- STM32 F7 Cortex M7, 512 FLASH, 320K (240+16+64) Kb SRAM config ARCH_CHIP_STM32F746ZG bool "STM32F746ZG" - select STM32F7_STM32F746XX - select STM32F7_FLASH_CONFIG_G + select STM32_STM32F746XX + select STM32_FLASH_CONFIG_G select STM32F7_IO_CONFIG_Z ---help--- STM32 F7 Cortex M7, 1024 FLASH, 320K (240+16+64) Kb SRAM config ARCH_CHIP_STM32F746IE bool "STM32F746IE" - select STM32F7_STM32F746XX - select STM32F7_FLASH_CONFIG_E + select STM32_STM32F746XX + select STM32_FLASH_CONFIG_E select STM32F7_IO_CONFIG_I ---help--- STM32 F7 Cortex M7, 512 FLASH, 320K (240+16+64) Kb SRAM config ARCH_CHIP_STM32F746NG bool "STM32F746NG" - select STM32F7_STM32F746XX - select STM32F7_FLASH_CONFIG_G + select STM32_STM32F746XX + select STM32_FLASH_CONFIG_G select STM32F7_IO_CONFIG_N ---help--- STM32 F7 Cortex M7, 1024 FLASH, 320K (240+16+64) Kb SRAM config ARCH_CHIP_STM32F746NE bool "STM32F746NE" - select STM32F7_STM32F746XX - select STM32F7_FLASH_CONFIG_E + select STM32_STM32F746XX + select STM32_FLASH_CONFIG_E select STM32F7_IO_CONFIG_N ---help--- STM32 F7 Cortex M7, 512 FLASH, 320K (240+16+64) Kb SRAM config ARCH_CHIP_STM32F746ZE bool "STM32F746ZE" - select STM32F7_STM32F746XX - select STM32F7_FLASH_CONFIG_E + select STM32_STM32F746XX + select STM32_FLASH_CONFIG_E select STM32F7_IO_CONFIG_Z ---help--- STM32 F7 Cortex M7, 512 FLASH, 320K (240+16+64) Kb SRAM config ARCH_CHIP_STM32F746IG bool "STM32F746IG" - select STM32F7_STM32F746XX - select STM32F7_FLASH_CONFIG_G + select STM32_STM32F746XX + select STM32_FLASH_CONFIG_G select STM32F7_IO_CONFIG_I ---help--- STM32 F7 Cortex M7, 1024 FLASH, 320K (240+16+64) Kb SRAM config ARCH_CHIP_STM32F756NG bool "STM32F756NG" - select STM32F7_STM32F756XX - select STM32F7_FLASH_CONFIG_G + select STM32_STM32F756XX + select STM32_FLASH_CONFIG_G select STM32F7_IO_CONFIG_N ---help--- STM32 F7 Cortex M7, 1024 FLASH, 320K (240+16+64) Kb SRAM config ARCH_CHIP_STM32F756BG bool "STM32F756BG" - select STM32F7_STM32F756XX - select STM32F7_FLASH_CONFIG_G + select STM32_STM32F756XX + select STM32_FLASH_CONFIG_G select STM32F7_IO_CONFIG_B ---help--- STM32 F7 Cortex M7, 1024 FLASH, 320K (240+16+64) Kb SRAM config ARCH_CHIP_STM32F756IG bool "STM32F756IG" - select STM32F7_STM32F756XX - select STM32F7_FLASH_CONFIG_G + select STM32_STM32F756XX + select STM32_FLASH_CONFIG_G select STM32F7_IO_CONFIG_I ---help--- STM32 F7 Cortex M7, 1024 FLASH, 320K (240+16+64) Kb SRAM config ARCH_CHIP_STM32F756VG bool "STM32F756VG" - select STM32F7_STM32F756XX - select STM32F7_FLASH_CONFIG_G + select STM32_STM32F756XX + select STM32_FLASH_CONFIG_G select STM32F7_IO_CONFIG_V ---help--- STM32 F7 Cortex M7, 1024 FLASH, 320K (240+16+64) Kb SRAM config ARCH_CHIP_STM32F756ZG bool "STM32F756ZG" - select STM32F7_STM32F756XX - select STM32F7_FLASH_CONFIG_G + select STM32_STM32F756XX + select STM32_FLASH_CONFIG_G select STM32F7_IO_CONFIG_Z ---help--- STM32 F7 Cortex M7, 1024 FLASH, 320K (240+16+64) Kb SRAM config ARCH_CHIP_STM32F765NI bool "STM32F765NI" - select STM32F7_STM32F765XX - select STM32F7_FLASH_CONFIG_I + select STM32_STM32F765XX + select STM32_FLASH_CONFIG_I select STM32F7_IO_CONFIG_N ---help--- STM32 F7 Cortex M7, 2048 FLASH, 512K (368+16+128) Kb SRAM config ARCH_CHIP_STM32F765VI bool "STM32F765VI" - select STM32F7_STM32F765XX - select STM32F7_FLASH_CONFIG_I + select STM32_STM32F765XX + select STM32_FLASH_CONFIG_I select STM32F7_IO_CONFIG_V ---help--- STM32 F7 Cortex M7, 2048 FLASH, 512K (368+16+128) Kb SRAM config ARCH_CHIP_STM32F765VG bool "STM32F765VG" - select STM32F7_STM32F765XX - select STM32F7_FLASH_CONFIG_G + select STM32_STM32F765XX + select STM32_FLASH_CONFIG_G select STM32F7_IO_CONFIG_V ---help--- STM32 F7 Cortex M7, 1024 FLASH, 512K (368+16+128) Kb SRAM config ARCH_CHIP_STM32F765BI bool "STM32F765BI" - select STM32F7_STM32F765XX - select STM32F7_FLASH_CONFIG_I + select STM32_STM32F765XX + select STM32_FLASH_CONFIG_I select STM32F7_IO_CONFIG_B ---help--- STM32 F7 Cortex M7, 2048 FLASH, 512K (368+16+128) Kb SRAM config ARCH_CHIP_STM32F765NG bool "STM32F765NG" - select STM32F7_STM32F765XX - select STM32F7_FLASH_CONFIG_G + select STM32_STM32F765XX + select STM32_FLASH_CONFIG_G select STM32F7_IO_CONFIG_N ---help--- STM32 F7 Cortex M7, 1024 FLASH, 512K (368+16+128) Kb SRAM config ARCH_CHIP_STM32F765ZG bool "STM32F765ZG" - select STM32F7_STM32F765XX - select STM32F7_FLASH_CONFIG_G + select STM32_STM32F765XX + select STM32_FLASH_CONFIG_G select STM32F7_IO_CONFIG_Z ---help--- STM32 F7 Cortex M7, 1024 FLASH, 512K (368+16+128) Kb SRAM config ARCH_CHIP_STM32F765ZI bool "STM32F765ZI" - select STM32F7_STM32F765XX - select STM32F7_FLASH_CONFIG_I + select STM32_STM32F765XX + select STM32_FLASH_CONFIG_I select STM32F7_IO_CONFIG_Z ---help--- STM32 F7 Cortex M7, 2048 FLASH, 512K (368+16+128) Kb SRAM config ARCH_CHIP_STM32F765IG bool "STM32F765IG" - select STM32F7_STM32F765XX - select STM32F7_FLASH_CONFIG_G + select STM32_STM32F765XX + select STM32_FLASH_CONFIG_G select STM32F7_IO_CONFIG_I ---help--- STM32 F7 Cortex M7, 1024 FLASH, 512K (368+16+128) Kb SRAM config ARCH_CHIP_STM32F765BG bool "STM32F765BG" - select STM32F7_STM32F765XX - select STM32F7_FLASH_CONFIG_G + select STM32_STM32F765XX + select STM32_FLASH_CONFIG_G select STM32F7_IO_CONFIG_B ---help--- STM32 F7 Cortex M7, 1024 FLASH, 512K (368+16+128) Kb SRAM config ARCH_CHIP_STM32F765II bool "STM32F765II" - select STM32F7_STM32F765XX - select STM32F7_FLASH_CONFIG_I + select STM32_STM32F765XX + select STM32_FLASH_CONFIG_I select STM32F7_IO_CONFIG_I ---help--- STM32 F7 Cortex M7, 2048 FLASH, 512K (368+16+128) Kb SRAM config ARCH_CHIP_STM32F767NG bool "STM32F767NG" - select STM32F7_STM32F767XX - select STM32F7_FLASH_CONFIG_G + select STM32_STM32F767XX + select STM32_FLASH_CONFIG_G select STM32F7_IO_CONFIG_N ---help--- STM32 F7 Cortex M7, 1024 FLASH, 512K (368+16+128) Kb SRAM config ARCH_CHIP_STM32F767IG bool "STM32F767IG" - select STM32F7_STM32F767XX - select STM32F7_FLASH_CONFIG_G + select STM32_STM32F767XX + select STM32_FLASH_CONFIG_G select STM32F7_IO_CONFIG_I ---help--- STM32 F7 Cortex M7, 1024 FLASH, 512K (368+16+128) Kb SRAM config ARCH_CHIP_STM32F767VG bool "STM32F767VG" - select STM32F7_STM32F767XX - select STM32F7_FLASH_CONFIG_G + select STM32_STM32F767XX + select STM32_FLASH_CONFIG_G select STM32F7_IO_CONFIG_V ---help--- STM32 F7 Cortex M7, 1024 FLASH, 512K (368+16+128) Kb SRAM config ARCH_CHIP_STM32F767ZG bool "STM32F767ZG" - select STM32F7_STM32F767XX - select STM32F7_FLASH_CONFIG_G + select STM32_STM32F767XX + select STM32_FLASH_CONFIG_G select STM32F7_IO_CONFIG_Z ---help--- STM32 F7 Cortex M7, 1024 FLASH, 512K (368+16+128) Kb SRAM config ARCH_CHIP_STM32F767NI bool "STM32F767NI" - select STM32F7_STM32F767XX - select STM32F7_FLASH_CONFIG_I + select STM32_STM32F767XX + select STM32_FLASH_CONFIG_I select STM32F7_IO_CONFIG_N ---help--- STM32 F7 Cortex M7, 2048 FLASH, 512K (368+16+128) Kb SRAM config ARCH_CHIP_STM32F767VI bool "STM32F767VI" - select STM32F7_STM32F767XX - select STM32F7_FLASH_CONFIG_I + select STM32_STM32F767XX + select STM32_FLASH_CONFIG_I select STM32F7_IO_CONFIG_V ---help--- STM32 F7 Cortex M7, 2048 FLASH, 512K (368+16+128) Kb SRAM config ARCH_CHIP_STM32F767BG bool "STM32F767BG" - select STM32F7_STM32F767XX - select STM32F7_FLASH_CONFIG_G + select STM32_STM32F767XX + select STM32_FLASH_CONFIG_G select STM32F7_IO_CONFIG_B ---help--- STM32 F7 Cortex M7, 1024 FLASH, 512K (368+16+128) Kb SRAM config ARCH_CHIP_STM32F767ZI bool "STM32F767ZI" - select STM32F7_STM32F767XX - select STM32F7_FLASH_CONFIG_I + select STM32_STM32F767XX + select STM32_FLASH_CONFIG_I select STM32F7_IO_CONFIG_Z ---help--- STM32 F7 Cortex M7, 2048 FLASH, 512K (368+16+128) Kb SRAM config ARCH_CHIP_STM32F767II bool "STM32F767II" - select STM32F7_STM32F767XX - select STM32F7_FLASH_CONFIG_I + select STM32_STM32F767XX + select STM32_FLASH_CONFIG_I select STM32F7_IO_CONFIG_I ---help--- STM32 F7 Cortex M7, 2048 FLASH, 512K (368+16+128) Kb SRAM config ARCH_CHIP_STM32F769BI bool "STM32F769BI" - select STM32F7_STM32F769XX - select STM32F7_FLASH_CONFIG_I + select STM32_STM32F769XX + select STM32_FLASH_CONFIG_I select STM32F7_IO_CONFIG_B ---help--- STM32 F7 Cortex M7, 2048 FLASH, 512K (368+16+128) Kb SRAM config ARCH_CHIP_STM32F769II bool "STM32F769II" - select STM32F7_STM32F769XX - select STM32F7_FLASH_CONFIG_I + select STM32_STM32F769XX + select STM32_FLASH_CONFIG_I select STM32F7_IO_CONFIG_I ---help--- STM32 F7 Cortex M7, 2048 FLASH, 512K (368+16+128) Kb SRAM config ARCH_CHIP_STM32F769BG bool "STM32F769BG" - select STM32F7_STM32F769XX - select STM32F7_FLASH_CONFIG_G + select STM32_STM32F769XX + select STM32_FLASH_CONFIG_G select STM32F7_IO_CONFIG_B ---help--- STM32 F7 Cortex M7, 1024 FLASH, 512K (368+16+128) Kb SRAM config ARCH_CHIP_STM32F769NI bool "STM32F769NI" - select STM32F7_STM32F769XX - select STM32F7_FLASH_CONFIG_I + select STM32_STM32F769XX + select STM32_FLASH_CONFIG_I select STM32F7_IO_CONFIG_N ---help--- STM32 F7 Cortex M7, 2048 FLASH, 512K (368+16+128) Kb SRAM config ARCH_CHIP_STM32F769AI bool "STM32F769AI" - select STM32F7_STM32F769AX - select STM32F7_FLASH_CONFIG_I + select STM32_STM32F769AX + select STM32_FLASH_CONFIG_I select STM32F7_IO_CONFIG_A ---help--- STM32 F7 Cortex M7, 2048 FLASH, 512K (368+16+128) Kb SRAM config ARCH_CHIP_STM32F769NG bool "STM32F769NG" - select STM32F7_STM32F769XX - select STM32F7_FLASH_CONFIG_G + select STM32_STM32F769XX + select STM32_FLASH_CONFIG_G select STM32F7_IO_CONFIG_N ---help--- STM32 F7 Cortex M7, 1024 FLASH, 512K (368+16+128) Kb SRAM config ARCH_CHIP_STM32F769IG bool "STM32F769IG" - select STM32F7_STM32F769XX - select STM32F7_FLASH_CONFIG_G + select STM32_STM32F769XX + select STM32_FLASH_CONFIG_G select STM32F7_IO_CONFIG_I ---help--- STM32 F7 Cortex M7, 1024 FLASH, 512K (368+16+128) Kb SRAM config ARCH_CHIP_STM32F777ZI bool "STM32F777ZI" - select STM32F7_STM32F777XX - select STM32F7_FLASH_CONFIG_I + select STM32_STM32F777XX + select STM32_FLASH_CONFIG_I select STM32F7_IO_CONFIG_Z ---help--- STM32 F7 Cortex M7, 2048 FLASH, 512K (368+16+128) Kb SRAM config ARCH_CHIP_STM32F777VI bool "STM32F777VI" - select STM32F7_STM32F777XX - select STM32F7_FLASH_CONFIG_I + select STM32_STM32F777XX + select STM32_FLASH_CONFIG_I select STM32F7_IO_CONFIG_V ---help--- STM32 F7 Cortex M7, 2048 FLASH, 512K (368+16+128) Kb SRAM config ARCH_CHIP_STM32F777NI bool "STM32F777NI" - select STM32F7_STM32F777XX - select STM32F7_FLASH_CONFIG_I + select STM32_STM32F777XX + select STM32_FLASH_CONFIG_I select STM32F7_IO_CONFIG_N ---help--- STM32 F7 Cortex M7, 2048 FLASH, 512K (368+16+128) Kb SRAM config ARCH_CHIP_STM32F777BI bool "STM32F777BI" - select STM32F7_STM32F777XX - select STM32F7_FLASH_CONFIG_I + select STM32_STM32F777XX + select STM32_FLASH_CONFIG_I select STM32F7_IO_CONFIG_B ---help--- STM32 F7 Cortex M7, 2048 FLASH, 512K (368+16+128) Kb SRAM config ARCH_CHIP_STM32F777II bool "STM32F777II" - select STM32F7_STM32F777XX - select STM32F7_FLASH_CONFIG_I + select STM32_STM32F777XX + select STM32_FLASH_CONFIG_I select STM32F7_IO_CONFIG_I ---help--- STM32 F7 Cortex M7, 2048 FLASH, 512K (368+16+128) Kb SRAM config ARCH_CHIP_STM32F778AI bool "STM32F778AI" - select STM32F7_STM32F778AX - select STM32F7_FLASH_CONFIG_I + select STM32_STM32F778AX + select STM32_FLASH_CONFIG_I select STM32F7_IO_CONFIG_A ---help--- STM32 F7 Cortex M7, 2048 FLASH, 512K (368+16+128) Kb SRAM config ARCH_CHIP_STM32F779II bool "STM32F779II" - select STM32F7_STM32F779XX - select STM32F7_FLASH_CONFIG_I + select STM32_STM32F779XX + select STM32_FLASH_CONFIG_I select STM32F7_IO_CONFIG_I ---help--- STM32 F7 Cortex M7, 2048 FLASH, 512K (368+16+128) Kb SRAM config ARCH_CHIP_STM32F779NI bool "STM32F779NI" - select STM32F7_STM32F779XX - select STM32F7_FLASH_CONFIG_I + select STM32_STM32F779XX + select STM32_FLASH_CONFIG_I select STM32F7_IO_CONFIG_N ---help--- STM32 F7 Cortex M7, 2048 FLASH, 512K (368+16+128) Kb SRAM config ARCH_CHIP_STM32F779BI bool "STM32F779BI" - select STM32F7_STM32F779XX - select STM32F7_FLASH_CONFIG_I + select STM32_STM32F779XX + select STM32_FLASH_CONFIG_I select STM32F7_IO_CONFIG_B ---help--- STM32 F7 Cortex M7, 2048 FLASH, 512K (368+16+128) Kb SRAM config ARCH_CHIP_STM32F779AI bool "STM32F779AI" - select STM32F7_STM32F779XX - select STM32F7_FLASH_CONFIG_I + select STM32_STM32F779XX + select STM32_FLASH_CONFIG_I select STM32F7_IO_CONFIG_A ---help--- STM32 F7 Cortex M7, 2048 FLASH, 512K (368+16+128) Kb SRAM endchoice # STM32 F7 Chip Selection -config STM32F7_STM32F72XX - bool - default n - -config STM32F7_STM32F73XX - bool - default n - -config STM32F7_STM32F74XX - bool - default n - -config STM32F7_STM32F75XX - bool - default n - -config STM32F7_STM32F76XX - bool - default n - -config STM32F7_STM32F77XX - bool - default n +config STM32_STM32F72XX + bool + default n + select STM32_HAVE_CAN1 + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM3 + select STM32_HAVE_TIM4 + select STM32_HAVE_TIM5 + select STM32_HAVE_TIM6 + select STM32_HAVE_TIM7 + select STM32_HAVE_TIM8 + select STM32_HAVE_TIM9 + select STM32_HAVE_TIM10 + select STM32_HAVE_TIM11 + select STM32_HAVE_TIM12 + select STM32_HAVE_TIM13 + select STM32_HAVE_TIM14 + +config STM32_STM32F73XX + bool + default n + select STM32_HAVE_CAN1 + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM3 + select STM32_HAVE_TIM4 + select STM32_HAVE_TIM5 + select STM32_HAVE_TIM6 + select STM32_HAVE_TIM7 + select STM32_HAVE_TIM8 + select STM32_HAVE_TIM9 + select STM32_HAVE_TIM10 + select STM32_HAVE_TIM11 + select STM32_HAVE_TIM12 + select STM32_HAVE_TIM13 + select STM32_HAVE_TIM14 + +config STM32_STM32F74XX + bool + default n + select STM32_HAVE_CAN1 + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM3 + select STM32_HAVE_TIM4 + select STM32_HAVE_TIM5 + select STM32_HAVE_TIM6 + select STM32_HAVE_TIM7 + select STM32_HAVE_TIM8 + select STM32_HAVE_TIM9 + select STM32_HAVE_TIM10 + select STM32_HAVE_TIM11 + select STM32_HAVE_TIM12 + select STM32_HAVE_TIM13 + select STM32_HAVE_TIM14 + +config STM32_STM32F75XX + bool + default n + select STM32_HAVE_CAN1 + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM3 + select STM32_HAVE_TIM4 + select STM32_HAVE_TIM5 + select STM32_HAVE_TIM6 + select STM32_HAVE_TIM7 + select STM32_HAVE_TIM8 + select STM32_HAVE_TIM9 + select STM32_HAVE_TIM10 + select STM32_HAVE_TIM11 + select STM32_HAVE_TIM12 + select STM32_HAVE_TIM13 + select STM32_HAVE_TIM14 + +config STM32_STM32F76XX + bool + default n + select STM32_HAVE_CAN1 + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM3 + select STM32_HAVE_TIM4 + select STM32_HAVE_TIM5 + select STM32_HAVE_TIM6 + select STM32_HAVE_TIM7 + select STM32_HAVE_TIM8 + select STM32_HAVE_TIM9 + select STM32_HAVE_TIM10 + select STM32_HAVE_TIM11 + select STM32_HAVE_TIM12 + select STM32_HAVE_TIM13 + select STM32_HAVE_TIM14 + +config STM32_STM32F77XX + bool + default n + select STM32_HAVE_CAN1 + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM3 + select STM32_HAVE_TIM4 + select STM32_HAVE_TIM5 + select STM32_HAVE_TIM6 + select STM32_HAVE_TIM7 + select STM32_HAVE_TIM8 + select STM32_HAVE_TIM9 + select STM32_HAVE_TIM10 + select STM32_HAVE_TIM11 + select STM32_HAVE_TIM12 + select STM32_HAVE_TIM13 + select STM32_HAVE_TIM14 config STM32F7_IO_CONFIG_R + # Package designator R bool default n config STM32F7_IO_CONFIG_V + # Package designator V bool default n config STM32F7_IO_CONFIG_I + # Package designator I bool default n config STM32F7_IO_CONFIG_Z + # Package designator Z bool default n config STM32F7_IO_CONFIG_N + # Package designator N bool default n config STM32F7_IO_CONFIG_B + # Package designator B bool default n config STM32F7_IO_CONFIG_A + # Package designator A bool default n -config STM32F7_STM32F722XX +config STM32_STM32F722XX bool default n - select STM32F7_STM32F72XX + select STM32_STM32F72XX select ARCH_HAVE_FPU select ARMV7M_HAVE_ICACHE select ARMV7M_HAVE_DCACHE select ARMV7M_HAVE_ITCM select ARMV7M_HAVE_DTCM - select STM32F7_HAVE_FMC - select STM32F7_HAVE_RNG - select STM32F7_HAVE_SPI4 if !STM32F7_IO_CONFIG_R - select STM32F7_HAVE_SPI5 if !(STM32F7_IO_CONFIG_R || STM32F7_IO_CONFIG_V) - select STM32F7_HAVE_CRYP - select STM32F7_HAVE_SDMMC2 if !STM32F7_IO_CONFIG_R - select STM32F7_HAVE_EXTERNAL_ULPI + select STM32_HAVE_FMC + select STM32_HAVE_RNG + select STM32_HAVE_SPI4 if !STM32F7_IO_CONFIG_R + select STM32_HAVE_SPI5 if !(STM32F7_IO_CONFIG_R || STM32F7_IO_CONFIG_V) + select STM32_HAVE_CRYP + select STM32_HAVE_IP_CRYPTO_M3M4_V1 + select STM32_HAVE_SDMMC2 if !STM32F7_IO_CONFIG_R + select STM32_HAVE_EXTERNAL_ULPI -config STM32F7_STM32F723XX +config STM32_STM32F723XX bool default n - select STM32F7_STM32F72XX + select STM32_STM32F72XX select ARCH_HAVE_FPU select ARMV7M_HAVE_ICACHE select ARMV7M_HAVE_DCACHE select ARMV7M_HAVE_ITCM select ARMV7M_HAVE_DTCM - select STM32F7_HAVE_FMC - select STM32F7_HAVE_RNG - select STM32F7_HAVE_SPI4 if !STM32F7_IO_CONFIG_R - select STM32F7_HAVE_SPI5 if !(STM32F7_IO_CONFIG_R || STM32F7_IO_CONFIG_V) - select STM32F7_HAVE_CRYP - select STM32F7_HAVE_SDMMC2 if !STM32F7_IO_CONFIG_R + select STM32_HAVE_FMC + select STM32_HAVE_RNG + select STM32_HAVE_SPI4 if !STM32F7_IO_CONFIG_R + select STM32_HAVE_SPI5 if !(STM32F7_IO_CONFIG_R || STM32F7_IO_CONFIG_V) + select STM32_HAVE_CRYP + select STM32_HAVE_IP_CRYPTO_M3M4_V1 + select STM32_HAVE_SDMMC2 if !STM32F7_IO_CONFIG_R -config STM32F7_STM32F745XX +config STM32_STM32F745XX bool default n - select STM32F7_STM32F74XX + select STM32_STM32F74XX select ARCH_HAVE_FPU select ARMV7M_HAVE_ICACHE select ARMV7M_HAVE_DCACHE select ARMV7M_HAVE_ITCM select ARMV7M_HAVE_DTCM - select STM32F7_HAVE_FMC - select STM32F7_HAVE_ETHRNET - select STM32F7_HAVE_RNG - select STM32F7_HAVE_SPI5 if !STM32F7_IO_CONFIG_V - select STM32F7_HAVE_SPI6 if !STM32F7_IO_CONFIG_V - select STM32F7_HAVE_DCMI - select STM32F7_HAVE_DMA2D - select STM32F7_HAVE_CAN2 - select STM32F7_HAVE_SPI4 + select STM32_HAVE_FMC + select STM32_HAVE_ETHRNET + select STM32_HAVE_RNG + select STM32_HAVE_SPI5 if !STM32F7_IO_CONFIG_V + select STM32_HAVE_SPI6 if !STM32F7_IO_CONFIG_V + select STM32_HAVE_DCMI + select STM32_HAVE_DMA2D + select STM32_HAVE_IP_DMA2D_M3M4_V1 + select STM32_HAVE_CAN2 + select STM32_HAVE_SPI4 -config STM32F7_STM32F746XX +config STM32_STM32F746XX bool default n - select STM32F7_STM32F74XX + select STM32_STM32F74XX select ARCH_HAVE_FPU select ARMV7M_HAVE_ICACHE select ARMV7M_HAVE_DCACHE select ARMV7M_HAVE_ITCM select ARMV7M_HAVE_DTCM - select STM32F7_HAVE_FMC - select STM32F7_HAVE_ETHRNET - select STM32F7_HAVE_RNG - select STM32F7_HAVE_SPI5 if !STM32F7_IO_CONFIG_V - select STM32F7_HAVE_SPI6 if !STM32F7_IO_CONFIG_V - select STM32F7_HAVE_DCMI - select STM32F7_HAVE_LTDC - select STM32F7_HAVE_DMA2D - select STM32F7_HAVE_CAN2 - select STM32F7_HAVE_SPI4 - select STM32F7_HAVE_EXTERNAL_ULPI - select STM32F7_HAVE_SAI1 - select STM32F7_HAVE_SAI2 - -config STM32F7_STM32F756XX - bool - default n - select STM32F7_STM32F75XX + select STM32_HAVE_FMC + select STM32_HAVE_ETHRNET + select STM32_HAVE_RNG + select STM32_HAVE_SPI5 if !STM32F7_IO_CONFIG_V + select STM32_HAVE_SPI6 if !STM32F7_IO_CONFIG_V + select STM32_HAVE_DCMI + select STM32_HAVE_LTDC + select STM32_HAVE_DMA2D + select STM32_HAVE_IP_DMA2D_M3M4_V1 + select STM32_HAVE_CAN2 + select STM32_HAVE_SPI4 + select STM32_HAVE_EXTERNAL_ULPI + select STM32_HAVE_SAI1 + select STM32_HAVE_SAI2 + +config STM32_STM32F756XX + bool + default n + select STM32_STM32F75XX select ARCH_HAVE_FPU select ARMV7M_HAVE_ICACHE select ARMV7M_HAVE_DCACHE select ARMV7M_HAVE_ITCM select ARMV7M_HAVE_DTCM - select STM32F7_HAVE_FMC - select STM32F7_HAVE_ETHRNET - select STM32F7_HAVE_RNG - select STM32F7_HAVE_SPI5 if !STM32F7_IO_CONFIG_V - select STM32F7_HAVE_SPI6 if !STM32F7_IO_CONFIG_V - select STM32F7_HAVE_LTDC - select STM32F7_HAVE_DMA2D - select STM32F7_HAVE_CRYP - select STM32F7_HAVE_HASH - select STM32F7_HAVE_CAN2 - select STM32F7_HAVE_SPI4 - -config STM32F7_STM32F765XX - bool - default n - select STM32F7_STM32F76XX + select STM32_HAVE_FMC + select STM32_HAVE_ETHRNET + select STM32_HAVE_RNG + select STM32_HAVE_SPI5 if !STM32F7_IO_CONFIG_V + select STM32_HAVE_SPI6 if !STM32F7_IO_CONFIG_V + select STM32_HAVE_LTDC + select STM32_HAVE_DMA2D + select STM32_HAVE_IP_DMA2D_M3M4_V1 + select STM32_HAVE_CRYP + select STM32_HAVE_IP_CRYPTO_M3M4_V1 + select STM32_HAVE_HASH + select STM32_HAVE_CAN2 + select STM32_HAVE_SPI4 + +config STM32_STM32F765XX + bool + default n + select STM32_STM32F76XX select ARCH_HAVE_FPU select ARCH_HAVE_DPFPU select ARMV7M_HAVE_ICACHE select ARMV7M_HAVE_DCACHE select ARMV7M_HAVE_ITCM select ARMV7M_HAVE_DTCM - select STM32F7_HAVE_FMC - select STM32F7_HAVE_ETHRNET - select STM32F7_HAVE_RNG # data sheet says yes, Product matrix says no - select STM32F7_HAVE_SPI5 if !STM32F7_IO_CONFIG_V - select STM32F7_HAVE_SPI6 if !STM32F7_IO_CONFIG_V - select STM32F7_HAVE_SDMMC2 if !STM32F7_IO_CONFIG_V - select STM32F7_HAVE_CAN3 - select STM32F7_HAVE_DCMI - select STM32F7_HAVE_DMA2D - select STM32F7_HAVE_DFSDM1 - select STM32F7_HAVE_CAN2 - select STM32F7_HAVE_SPI4 - -config STM32F7_STM32F767XX - bool - default n - select STM32F7_STM32F76XX + select STM32_HAVE_FMC + select STM32_HAVE_ETHRNET + select STM32_HAVE_RNG # data sheet says yes, Product matrix says no + select STM32_HAVE_SPI5 if !STM32F7_IO_CONFIG_V + select STM32_HAVE_SPI6 if !STM32F7_IO_CONFIG_V + select STM32_HAVE_SDMMC2 if !STM32F7_IO_CONFIG_V + select STM32_HAVE_CAN3 + select STM32_HAVE_DCMI + select STM32_HAVE_DMA2D + select STM32_HAVE_IP_DMA2D_M3M4_V1 + select STM32_HAVE_DFSDM1 + select STM32_HAVE_CAN2 + select STM32_HAVE_SPI4 + +config STM32_STM32F767XX + bool + default n + select STM32_STM32F76XX select ARCH_HAVE_FPU select ARCH_HAVE_DPFPU select ARMV7M_HAVE_ICACHE select ARMV7M_HAVE_DCACHE select ARMV7M_HAVE_ITCM select ARMV7M_HAVE_DTCM - select STM32F7_HAVE_FMC - select STM32F7_HAVE_ETHRNET - select STM32F7_HAVE_RNG - select STM32F7_HAVE_SPI5 if !STM32F7_IO_CONFIG_V - select STM32F7_HAVE_SPI6 if !STM32F7_IO_CONFIG_V - select STM32F7_HAVE_SDMMC2 if !STM32F7_IO_CONFIG_V - select STM32F7_HAVE_CAN3 - select STM32F7_HAVE_DCMI - select STM32F7_HAVE_DSIHOST if !(STM32F7_IO_CONFIG_V || STM32F7_IO_CONFIG_Z) - select STM32F7_HAVE_LTDC - select STM32F7_HAVE_DMA2D - select STM32F7_HAVE_JPEG - select STM32F7_HAVE_DFSDM1 - select STM32F7_HAVE_CAN2 - select STM32F7_HAVE_SPI4 - -config STM32F7_STM32F768XX # Revisit When parts released - bool - default n - select STM32F7_STM32F76XX + select STM32_HAVE_FMC + select STM32_HAVE_ETHRNET + select STM32_HAVE_RNG + select STM32_HAVE_SPI5 if !STM32F7_IO_CONFIG_V + select STM32_HAVE_SPI6 if !STM32F7_IO_CONFIG_V + select STM32_HAVE_SDMMC2 if !STM32F7_IO_CONFIG_V + select STM32_HAVE_CAN3 + select STM32_HAVE_DCMI + select STM32_HAVE_DSIHOST if !(STM32F7_IO_CONFIG_V || STM32F7_IO_CONFIG_Z) + select STM32_HAVE_LTDC + select STM32_HAVE_DMA2D + select STM32_HAVE_IP_DMA2D_M3M4_V1 + select STM32_HAVE_JPEG + select STM32_HAVE_DFSDM1 + select STM32_HAVE_CAN2 + select STM32_HAVE_SPI4 + +config STM32_STM32F768XX # Revisit When parts released + bool + default n + select STM32_STM32F76XX select ARCH_HAVE_FPU select ARCH_HAVE_DPFPU select ARMV7M_HAVE_ICACHE select ARMV7M_HAVE_DCACHE select ARMV7M_HAVE_ITCM select ARMV7M_HAVE_DTCM - select STM32F7_HAVE_FMC - select STM32F7_HAVE_ETHRNET - select STM32F7_HAVE_RNG - select STM32F7_HAVE_SPI5 if !STM32F7_IO_CONFIG_V - select STM32F7_HAVE_SPI6 if !STM32F7_IO_CONFIG_V - select STM32F7_HAVE_SDMMC2 if !STM32F7_IO_CONFIG_V - select STM32F7_HAVE_CAN3 - select STM32F7_HAVE_DCMI - select STM32F7_HAVE_DSIHOST if !(STM32F7_IO_CONFIG_V || STM32F7_IO_CONFIG_Z) - select STM32F7_HAVE_LTDC - select STM32F7_HAVE_DMA2D - select STM32F7_HAVE_JPEG - select STM32F7_HAVE_DFSDM1 - select STM32F7_HAVE_CAN2 - select STM32F7_HAVE_SPI4 - -config STM32F7_STM32F768AX # Revisit When parts released - bool - default n - select STM32F7_STM32F76XX + select STM32_HAVE_FMC + select STM32_HAVE_ETHRNET + select STM32_HAVE_RNG + select STM32_HAVE_SPI5 if !STM32F7_IO_CONFIG_V + select STM32_HAVE_SPI6 if !STM32F7_IO_CONFIG_V + select STM32_HAVE_SDMMC2 if !STM32F7_IO_CONFIG_V + select STM32_HAVE_CAN3 + select STM32_HAVE_DCMI + select STM32_HAVE_DSIHOST if !(STM32F7_IO_CONFIG_V || STM32F7_IO_CONFIG_Z) + select STM32_HAVE_LTDC + select STM32_HAVE_DMA2D + select STM32_HAVE_IP_DMA2D_M3M4_V1 + select STM32_HAVE_JPEG + select STM32_HAVE_DFSDM1 + select STM32_HAVE_CAN2 + select STM32_HAVE_SPI4 + +config STM32_STM32F768AX # Revisit When parts released + bool + default n + select STM32_STM32F76XX select ARCH_HAVE_FPU select ARCH_HAVE_DPFPU select ARMV7M_HAVE_ICACHE select ARMV7M_HAVE_DCACHE select ARMV7M_HAVE_ITCM select ARMV7M_HAVE_DTCM - select STM32F7_HAVE_FMC - select STM32F7_HAVE_RNG - select STM32F7_HAVE_SPI5 - select STM32F7_HAVE_SPI6 - select STM32F7_HAVE_SDMMC2 - select STM32F7_HAVE_CAN3 - select STM32F7_HAVE_DCMI - select STM32F7_HAVE_DSIHOST - select STM32F7_HAVE_LTDC - select STM32F7_HAVE_DMA2D - select STM32F7_HAVE_JPEG - select STM32F7_HAVE_DFSDM1 - select STM32F7_HAVE_CAN2 - select STM32F7_HAVE_SPI4 - -config STM32F7_STM32F769XX - bool - default n - select STM32F7_STM32F76XX + select STM32_HAVE_FMC + select STM32_HAVE_RNG + select STM32_HAVE_SPI5 + select STM32_HAVE_SPI6 + select STM32_HAVE_SDMMC2 + select STM32_HAVE_CAN3 + select STM32_HAVE_DCMI + select STM32_HAVE_DSIHOST + select STM32_HAVE_LTDC + select STM32_HAVE_DMA2D + select STM32_HAVE_IP_DMA2D_M3M4_V1 + select STM32_HAVE_JPEG + select STM32_HAVE_DFSDM1 + select STM32_HAVE_CAN2 + select STM32_HAVE_SPI4 + +config STM32_STM32F769XX + bool + default n + select STM32_STM32F76XX select ARCH_HAVE_FPU select ARCH_HAVE_DPFPU select ARMV7M_HAVE_ICACHE select ARMV7M_HAVE_DCACHE select ARMV7M_HAVE_ITCM select ARMV7M_HAVE_DTCM - select STM32F7_HAVE_FMC - select STM32F7_HAVE_ETHRNET - select STM32F7_HAVE_RNG - select STM32F7_HAVE_SPI5 if !STM32F7_IO_CONFIG_V - select STM32F7_HAVE_SPI6 if !STM32F7_IO_CONFIG_V - select STM32F7_HAVE_SDMMC2 if !STM32F7_IO_CONFIG_V - select STM32F7_HAVE_CAN3 - select STM32F7_HAVE_DCMI - select STM32F7_HAVE_DSIHOST if !(STM32F7_IO_CONFIG_V || STM32F7_IO_CONFIG_Z) - select STM32F7_HAVE_LTDC - select STM32F7_HAVE_DMA2D - select STM32F7_HAVE_JPEG - select STM32F7_HAVE_DFSDM1 - select STM32F7_HAVE_CAN2 - select STM32F7_HAVE_SPI4 - -config STM32F7_STM32F769AX # Revisit When parts released - bool - default n - select STM32F7_STM32F76XX + select STM32_HAVE_FMC + select STM32_HAVE_ETHRNET + select STM32_HAVE_RNG + select STM32_HAVE_SPI5 if !STM32F7_IO_CONFIG_V + select STM32_HAVE_SPI6 if !STM32F7_IO_CONFIG_V + select STM32_HAVE_SDMMC2 if !STM32F7_IO_CONFIG_V + select STM32_HAVE_CAN3 + select STM32_HAVE_DCMI + select STM32_HAVE_DSIHOST if !(STM32F7_IO_CONFIG_V || STM32F7_IO_CONFIG_Z) + select STM32_HAVE_LTDC + select STM32_HAVE_DMA2D + select STM32_HAVE_IP_DMA2D_M3M4_V1 + select STM32_HAVE_JPEG + select STM32_HAVE_DFSDM1 + select STM32_HAVE_CAN2 + select STM32_HAVE_SPI4 + +config STM32_STM32F769AX # Revisit When parts released + bool + default n + select STM32_STM32F76XX select ARCH_HAVE_FPU select ARCH_HAVE_DPFPU select ARMV7M_HAVE_ICACHE select ARMV7M_HAVE_DCACHE select ARMV7M_HAVE_ITCM select ARMV7M_HAVE_DTCM - select STM32F7_HAVE_FMC - select STM32F7_HAVE_RNG - select STM32F7_HAVE_SPI5 - select STM32F7_HAVE_SPI6 - select STM32F7_HAVE_SDMMC2 - select STM32F7_HAVE_CAN3 - select STM32F7_HAVE_DCMI - select STM32F7_HAVE_DSIHOST - select STM32F7_HAVE_LTDC - select STM32F7_HAVE_DMA2D - select STM32F7_HAVE_JPEG - select STM32F7_HAVE_DFSDM1 - select STM32F7_HAVE_CAN2 - select STM32F7_HAVE_SPI4 - -config STM32F7_STM32F777XX - bool - default n - select STM32F7_STM32F77XX + select STM32_HAVE_FMC + select STM32_HAVE_RNG + select STM32_HAVE_SPI5 + select STM32_HAVE_SPI6 + select STM32_HAVE_SDMMC2 + select STM32_HAVE_CAN3 + select STM32_HAVE_DCMI + select STM32_HAVE_DSIHOST + select STM32_HAVE_LTDC + select STM32_HAVE_DMA2D + select STM32_HAVE_IP_DMA2D_M3M4_V1 + select STM32_HAVE_JPEG + select STM32_HAVE_DFSDM1 + select STM32_HAVE_CAN2 + select STM32_HAVE_SPI4 + +config STM32_STM32F777XX + bool + default n + select STM32_STM32F77XX select ARCH_HAVE_FPU select ARCH_HAVE_DPFPU select ARMV7M_HAVE_ICACHE select ARMV7M_HAVE_DCACHE select ARMV7M_HAVE_ITCM select ARMV7M_HAVE_DTCM - select STM32F7_HAVE_FMC - select STM32F7_HAVE_ETHRNET - select STM32F7_HAVE_RNG - select STM32F7_HAVE_SPI5 if !STM32F7_IO_CONFIG_V - select STM32F7_HAVE_SPI6 if !STM32F7_IO_CONFIG_V - select STM32F7_HAVE_SDMMC2 if !STM32F7_IO_CONFIG_V - select STM32F7_HAVE_CAN3 - select STM32F7_HAVE_DCMI - select STM32F7_HAVE_DSIHOST if !(STM32F7_IO_CONFIG_V || STM32F7_IO_CONFIG_Z) - select STM32F7_HAVE_LTDC - select STM32F7_HAVE_DMA2D - select STM32F7_HAVE_JPEG - select STM32F7_HAVE_CRYP - select STM32F7_HAVE_HASH - select STM32F7_HAVE_DFSDM1 - select STM32F7_HAVE_CAN2 - select STM32F7_HAVE_SPI4 - -config STM32F7_STM32F778XX # Revisit when parts released - bool - default n - select STM32F7_STM32F77XX + select STM32_HAVE_FMC + select STM32_HAVE_ETHRNET + select STM32_HAVE_RNG + select STM32_HAVE_SPI5 if !STM32F7_IO_CONFIG_V + select STM32_HAVE_SPI6 if !STM32F7_IO_CONFIG_V + select STM32_HAVE_SDMMC2 if !STM32F7_IO_CONFIG_V + select STM32_HAVE_CAN3 + select STM32_HAVE_DCMI + select STM32_HAVE_DSIHOST if !(STM32F7_IO_CONFIG_V || STM32F7_IO_CONFIG_Z) + select STM32_HAVE_LTDC + select STM32_HAVE_DMA2D + select STM32_HAVE_IP_DMA2D_M3M4_V1 + select STM32_HAVE_JPEG + select STM32_HAVE_CRYP + select STM32_HAVE_IP_CRYPTO_M3M4_V1 + select STM32_HAVE_HASH + select STM32_HAVE_DFSDM1 + select STM32_HAVE_CAN2 + select STM32_HAVE_SPI4 + +config STM32_STM32F778XX # Revisit when parts released + bool + default n + select STM32_STM32F77XX select ARCH_HAVE_FPU select ARCH_HAVE_DPFPU select ARMV7M_HAVE_ICACHE select ARMV7M_HAVE_DCACHE select ARMV7M_HAVE_ITCM select ARMV7M_HAVE_DTCM - select STM32F7_HAVE_FMC - select STM32F7_HAVE_ETHRNET - select STM32F7_HAVE_RNG - select STM32F7_HAVE_SPI5 if !STM32F7_IO_CONFIG_V - select STM32F7_HAVE_SPI6 if !STM32F7_IO_CONFIG_V - select STM32F7_HAVE_SDMMC2 if !STM32F7_IO_CONFIG_V - select STM32F7_HAVE_CAN3 - select STM32F7_HAVE_DCMI - select STM32F7_HAVE_DSIHOST - select STM32F7_HAVE_LTDC - select STM32F7_HAVE_DMA2D - select STM32F7_HAVE_JPEG - select STM32F7_HAVE_CRYP - select STM32F7_HAVE_HASH - select STM32F7_HAVE_DFSDM1 - select STM32F7_HAVE_CAN2 - select STM32F7_HAVE_SPI4 - -config STM32F7_STM32F778AX - bool - default n - select STM32F7_STM32F77XX + select STM32_HAVE_FMC + select STM32_HAVE_ETHRNET + select STM32_HAVE_RNG + select STM32_HAVE_SPI5 if !STM32F7_IO_CONFIG_V + select STM32_HAVE_SPI6 if !STM32F7_IO_CONFIG_V + select STM32_HAVE_SDMMC2 if !STM32F7_IO_CONFIG_V + select STM32_HAVE_CAN3 + select STM32_HAVE_DCMI + select STM32_HAVE_DSIHOST + select STM32_HAVE_LTDC + select STM32_HAVE_DMA2D + select STM32_HAVE_IP_DMA2D_M3M4_V1 + select STM32_HAVE_JPEG + select STM32_HAVE_CRYP + select STM32_HAVE_IP_CRYPTO_M3M4_V1 + select STM32_HAVE_HASH + select STM32_HAVE_DFSDM1 + select STM32_HAVE_CAN2 + select STM32_HAVE_SPI4 + +config STM32_STM32F778AX + bool + default n + select STM32_STM32F77XX select ARCH_HAVE_FPU select ARCH_HAVE_DPFPU select ARMV7M_HAVE_ICACHE select ARMV7M_HAVE_DCACHE select ARMV7M_HAVE_ITCM select ARMV7M_HAVE_DTCM - select STM32F7_HAVE_FMC - select STM32F7_HAVE_RNG - select STM32F7_HAVE_SPI5 - select STM32F7_HAVE_SPI6 - select STM32F7_HAVE_SDMMC2 - select STM32F7_HAVE_CAN3 - select STM32F7_HAVE_DCMI - select STM32F7_HAVE_DSIHOST - select STM32F7_HAVE_LTDC - select STM32F7_HAVE_DMA2D - select STM32F7_HAVE_JPEG - select STM32F7_HAVE_CRYP - select STM32F7_HAVE_HASH - select STM32F7_HAVE_DFSDM1 - select STM32F7_HAVE_CAN2 - select STM32F7_HAVE_SPI4 - -config STM32F7_STM32F779XX - bool - default n - select STM32F7_STM32F77XX + select STM32_HAVE_FMC + select STM32_HAVE_RNG + select STM32_HAVE_SPI5 + select STM32_HAVE_SPI6 + select STM32_HAVE_SDMMC2 + select STM32_HAVE_CAN3 + select STM32_HAVE_DCMI + select STM32_HAVE_DSIHOST + select STM32_HAVE_LTDC + select STM32_HAVE_DMA2D + select STM32_HAVE_IP_DMA2D_M3M4_V1 + select STM32_HAVE_JPEG + select STM32_HAVE_CRYP + select STM32_HAVE_IP_CRYPTO_M3M4_V1 + select STM32_HAVE_HASH + select STM32_HAVE_DFSDM1 + select STM32_HAVE_CAN2 + select STM32_HAVE_SPI4 + +config STM32_STM32F779XX + bool + default n + select STM32_STM32F77XX select ARCH_HAVE_FPU select ARCH_HAVE_DPFPU select ARMV7M_HAVE_ICACHE select ARMV7M_HAVE_DCACHE select ARMV7M_HAVE_ITCM select ARMV7M_HAVE_DTCM - select STM32F7_HAVE_FMC - select STM32F7_HAVE_ETHRNET - select STM32F7_HAVE_RNG - select STM32F7_HAVE_SPI5 if !STM32F7_IO_CONFIG_V - select STM32F7_HAVE_SPI6 if !STM32F7_IO_CONFIG_V - select STM32F7_HAVE_SDMMC2 if !STM32F7_IO_CONFIG_V - select STM32F7_HAVE_CAN3 - select STM32F7_HAVE_DCMI - select STM32F7_HAVE_DSIHOST if !(STM32F7_IO_CONFIG_V || STM32F7_IO_CONFIG_Z) - select STM32F7_HAVE_LTDC - select STM32F7_HAVE_DMA2D - select STM32F7_HAVE_JPEG - select STM32F7_HAVE_CRYP - select STM32F7_HAVE_HASH - select STM32F7_HAVE_DFSDM1 - select STM32F7_HAVE_CAN2 - select STM32F7_HAVE_SPI4 - -config STM32F7_STM32F779AX - bool - default n - select STM32F7_STM32F77XX + select STM32_HAVE_FMC + select STM32_HAVE_ETHRNET + select STM32_HAVE_RNG + select STM32_HAVE_SPI5 if !STM32F7_IO_CONFIG_V + select STM32_HAVE_SPI6 if !STM32F7_IO_CONFIG_V + select STM32_HAVE_SDMMC2 if !STM32F7_IO_CONFIG_V + select STM32_HAVE_CAN3 + select STM32_HAVE_DCMI + select STM32_HAVE_DSIHOST if !(STM32F7_IO_CONFIG_V || STM32F7_IO_CONFIG_Z) + select STM32_HAVE_LTDC + select STM32_HAVE_DMA2D + select STM32_HAVE_IP_DMA2D_M3M4_V1 + select STM32_HAVE_JPEG + select STM32_HAVE_CRYP + select STM32_HAVE_IP_CRYPTO_M3M4_V1 + select STM32_HAVE_HASH + select STM32_HAVE_DFSDM1 + select STM32_HAVE_CAN2 + select STM32_HAVE_SPI4 + +config STM32_STM32F779AX + bool + default n + select STM32_STM32F77XX select ARCH_HAVE_FPU select ARCH_HAVE_DPFPU select ARMV7M_HAVE_ICACHE select ARMV7M_HAVE_DCACHE select ARMV7M_HAVE_ITCM select ARMV7M_HAVE_DTCM - select STM32F7_HAVE_FMC - select STM32F7_HAVE_RNG - select STM32F7_HAVE_SPI5 if !STM32F7_IO_CONFIG_V - select STM32F7_HAVE_SPI6 if !STM32F7_IO_CONFIG_V - select STM32F7_HAVE_SDMMC2 if !STM32F7_IO_CONFIG_V - select STM32F7_HAVE_CAN3 - select STM32F7_HAVE_DCMI - select STM32F7_HAVE_DSIHOST if !(STM32F7_IO_CONFIG_V || STM32F7_IO_CONFIG_Z) - select STM32F7_HAVE_LTDC - select STM32F7_HAVE_DMA2D - select STM32F7_HAVE_JPEG - select STM32F7_HAVE_CRYP - select STM32F7_HAVE_HASH - select STM32F7_HAVE_DFSDM1 - select STM32F7_HAVE_CAN2 - select STM32F7_HAVE_SPI4 - -config STM32F7_FLASH_CONFIG_E - bool - default n - -config STM32F7_FLASH_CONFIG_G - bool - default n - -config STM32F7_FLASH_CONFIG_I - bool - default n - -choice - prompt "Override Flash Size Designator" - depends on ARCH_CHIP_STM32F7 - default STM32F7_FLASH_OVERRIDE_DEFAULT - ---help--- - STM32F7 series parts numbering (sans the package type) ends with a letter - that designates the FLASH size. - - Designator Size in KiB - C 256 - E 512 - G 1024 - I 2048 - - This configuration option defaults to using the configuration based on that designator - or the default smaller size if there is no last character designator is present in the - STM32 Chip Selection. - - Examples: - If the STM32F745VE is chosen, the Flash configuration would be 'E', if a variant of - the part with a 2048 KiB Flash is released in the future one could simply select - the 'I' designator here. - - If an STM32F7xxx Series parts is chosen the default Flash configuration will be set - herein and can be changed. - -config STM32F7_FLASH_OVERRIDE_DEFAULT - bool "Default" - -config STM32F7_FLASH_OVERRIDE_C - bool "C 256KiB" - -config STM32F7_FLASH_OVERRIDE_E - bool "E 512KiB" - -config STM32F7_FLASH_OVERRIDE_G - bool "G 1024KiB" - -config STM32F7_FLASH_OVERRIDE_I - bool "I 2048KiB" - -endchoice # "Override Flash Size Designator" - -config STM32F7_FLASH_ART_ACCELERATOR - bool "Flash ART Accelerator" - default n - ---help--- - ART Accelerator on the flash memory ITCM interface accelerates code execution - with a system of instruction prefetch and cache lines. - - Enable if code and/or read-only data is accessed through ITCM bus instead of - AXIM bus. - -config STM32F7_PROGMEM - bool "Flash progmem support" - default n - ---help--- - Add progmem support, start block and end block options are provided to - obtain an uniform flash memory mapping. - -menu "STM32 Peripheral Support" - -# These "hidden" settings determine whether a peripheral option is available -# for the selected MCU - -config STM32F7_HAVE_LTDC - bool - default n - -config STM32F7_HAVE_FMC - bool - default n - -config STM32F7_HAVE_ETHRNET - bool - default n - -config STM32F7_HAVE_PHY_POLLED - bool - default n - -config STM32F7_HAVE_RNG - bool - default n - -config STM32F7_HAVE_SPI4 - bool - default n - -config STM32F7_HAVE_SPI5 - bool - default n - -config STM32F7_HAVE_SPI6 - bool - default n - -config STM32F7_HAVE_SDMMC2 - bool - default n - -config STM32F7_HAVE_ADC1_DMA - bool - default n - -config STM32F7_HAVE_ADC2_DMA - bool - default n - -config STM32F7_HAVE_ADC3_DMA - bool - default n - -config STM32F7_HAVE_CAN2 - bool - default n - -config STM32F7_HAVE_CAN3 - bool - default n - -config STM32F7_HAVE_DCMI - bool - default n - -config STM32F7_HAVE_DSIHOST - bool - default n - -config STM32F7_HAVE_LTDC - bool - default n - -config STM32F7_HAVE_DMA2D - bool - default n - -config STM32F7_HAVE_JPEG - bool - default n - -config STM32F7_HAVE_CRYP - bool - default n - -config STM32F7_HAVE_HASH - bool - default n - -config STM32F7_HAVE_DFSDM1 - bool - default n - -config STM32F7_HAVE_INTERNAL_ULPI - bool - default n - -config STM32F7_HAVE_EXTERNAL_ULPI - bool - default n - -config STM32F7_I2S - bool - default n - select STM32F7_SPI_DMA - -config STM32F7_HAVE_SAI1 - bool - default n - -config STM32F7_HAVE_SAI2 - bool - default n - -# These "hidden" settings are the OR of individual peripheral selections -# indicating that the general capability is required. - -config STM32F7_ADC - bool - default n - -config STM32F7_CAN - bool - default n - -config STM32F7_DAC - bool - default n - -config STM32F7_DMA - bool - default n - -config STM32F7_I2C - bool - default n - -config STM32F7_SAI - bool - default n - -config STM32F7_SDMMC - bool - default n - -config STM32F7_SPI - bool - default n - -config STM32F7_SPI_DMA - bool - default n - -config STM32F7_TIM - bool - default n - -config STM32F7_PWM - bool - default n - -config STM32F7_USART - bool - default n - -# These are the peripheral selections proper - -config STM32F7_ADC1 - bool "ADC1" - default n - select STM32F7_ADC - select STM32F7_HAVE_ADC1_DMA if STM32F7_DMA2 - -config STM32F7_ADC2 - bool "ADC2" - default n - select STM32F7_ADC - select STM32F7_HAVE_ADC2_DMA if STM32F7_DMA2 - -config STM32F7_ADC3 - bool "ADC3" - default n - select STM32F7_ADC - select STM32F7_HAVE_ADC3_DMA if STM32F7_DMA2 - -config STM32F7_BKPSRAM - bool "Enable BKP RAM Domain" - default n - -config STM32F7_CAN1 - bool "CAN1" - default n - select CAN - select STM32F7_CAN - -config STM32F7_CAN2 - bool "CAN2" - default n - select CAN - select STM32F7_CAN - -config STM32F7_CAN3 - bool "CAN3" - default n - select CAN - select STM32F7_CAN - depends on STM32F7_HAVE_CAN3 - -config STM32F7_CEC - bool "CEC" - default n - depends on STM32F7_VALUELINE - -config STM32F7_CRC - bool "CRC" - default n - -config STM32F7_CRYP - bool "CRYP" - depends on STM32F7_HAVE_CRYP - default n - -config STM32F7_DFSDM1 - bool "DFSDM1" - default n - depends on STM32F7_HAVE_DFSDM1 - select ARCH_HAVE_DFSDM1 - -config STM32F7_DMA1 - bool "DMA1" - default n - select STM32F7_DMA - select ARCH_DMA - -config STM32F7_DMA2 - bool "DMA2" - default n - select STM32F7_DMA - select ARCH_DMA - -config STM32F7_DAC1 - bool "DAC1" - default n - select STM32F7_DAC - -config STM32F7_DAC2 - bool "DAC2" - default n - select STM32F7_DAC - -config STM32F7_DCMI - bool "DCMI" - default n - depends on STM32F7_HAVE_DCMI - ---help--- - The devices embed a camera interface that can connect with camera - modules and CMOS sensors through an 8-bit to 14-bit parallel interface, - to receive video data. - -config STM32F7_DSIHOST - bool "DSIHOST" - default n - depends on STM32F7_HAVE_DSIHOST - ---help--- - The DSI Host is a dedicated peripheral for interfacing with MIPI® DSI - compliant displays. - -config STM32F7_DMA2D - bool "DMA2D" - default n - select FB - select FB_OVERLAY - depends on STM32F7_HAVE_DMA2D - ---help--- - The STM32 DMA2D is an Chrom-Art Accelerator for image manipulation - available on the STM32 F7 devices. - -config STM32F7_JPEG - bool "JPEG" - default n - depends on STM32F7_HAVE_JPEG - ---help--- - The JPEG codec provides an fast and simple hardware compressor and - decompressor of JPEG images with full management of JPEG headers. - -config STM32F7_ETHMAC - bool "Ethernet MAC" - default n - depends on STM32F7_HAVE_ETHRNET - select NETDEVICES - select ARCH_HAVE_PHY - select STM32F7_HAVE_PHY_POLLED - -config STM32F7_FMC - bool "FMC" - depends on STM32F7_HAVE_FMC - default n - -config STM32F7_HASH - bool "HASH" - default n - depends on STM32F7_HAVE_HASH - select ARCH_HAVE_HASH - -config STM32F7_CEC - bool "HDMI-CEC" - default n - -config STM32F7_I2C1 - bool "I2C1" - default n - select STM32F7_I2C - -config STM32F7_I2C2 - bool "I2C2" - default n - select STM32F7_I2C - -config STM32F7_I2C3 - bool "I2C3" - default n - select STM32F7_I2C - -config STM32F7_I2C4 - bool "I2C4" - default n - select STM32F7_I2C - -config STM32F7_LPTIM1 - bool "Low-power timer 1" - default n - -config STM32F7_LTDC - bool "LTDC" - default n - select FB - depends on STM32F7_HAVE_LTDC - ---help--- - The STM32 LTDC is an LCD-TFT Display Controller available on - the STM32F7x6, STM32F7x7, STM32F7x8 and STM32F7x9 devices. - It features a standard RGB888 parallel video interface (along - with HSYNC, VSYNC, etc.) for controlling TFT LCD displays. - With the STM32F7x8/9, the graphics signals can optionally - be output via DSI instead of the parallel interface: - See config options STM32F7_DSIHOST and STM32F7_LTDC_USE_DSI. - -config STM32F7_OTGFS - bool "OTG FS" - default n - select USBHOST_HAVE_ASYNCH if USBHOST - -config STM32F7_OTGFSHS - bool "OTG FS/HS" - default n - select USBHOST_HAVE_ASYNCH if USBHOST - -config STM32F7_QUADSPI - bool "QuadSPI" - default n - -config STM32F7_USBDEV_REGDEBUG - bool "OTG USBDEV REGDEBUG" - default n - depends on USBDEV - -config STM32F7_USBHOST_REGDEBUG - bool "OTG USBHOST REGDEBUG" - default n - depends on USBHOST - -config STM32F7_USBHOST_PKTDUMP - bool "OTG USBHOST PKTDUMP" - default n - depends on USBHOST - -config STM32F7_RTC - bool "RTC" - default n - select RTC - -config STM32F7_PWR - bool "PWR" - default n - -config STM32F7_RNG - bool "RNG" - default n - depends on STM32F7_HAVE_RNG - select ARCH_HAVE_RNG - -config STM32F7_I2S1 - bool "I2S1" - default n - depends on !STM32F7_SPI1 - select STM32F7_I2S - -config STM32F7_I2S2 - bool "I2S2" - default n - depends on !STM32F7_SPI2 - select STM32F7_I2S - -config STM32F7_I2S3 - bool "I2S3" - default n - depends on !STM32F7_SPI3 - select STM32F7_I2S - -config STM32F7_SAI1 - bool "SAI1" - default n - depends on STM32F7_HAVE_SAI1 - -config STM32F7_SAI1_A - bool "SAI1 Block A" - default n - select AUDIO - select I2S - select SCHED_HPWORK - select STM32F7_SAI - depends on STM32F7_SAI1 - -config STM32F7_SAI1_B - bool "SAI1 Block B" - default n - select AUDIO - select I2S - select SCHED_HPWORK - select STM32F7_SAI - depends on STM32F7_SAI1 - -config STM32F7_SAI2 - bool "SAI2" - default n - select STM32F7_HAVE_SAI2 - -config STM32F7_SAI2_A - bool "SAI2 Block A" - default n - select AUDIO - select I2S - select SCHED_HPWORK - select STM32F7_SAI - depends on STM32F7_SAI2 - -config STM32F7_SAI2_B - bool "SAI2 Block B" - default n - select AUDIO - select I2S - select SCHED_HPWORK - select STM32F7_SAI - depends on STM32F7_SAI2 - -config STM32F7_SDMMC1 - bool "SDMMC1" - default n - select STM32F7_SDMMC - select ARCH_HAVE_SDIO - select ARCH_HAVE_SDIOWAIT_WRCOMPLETE - select ARCH_HAVE_SDIO_PREFLIGHT - select SDIO_BLOCKSETUP - -config STM32F7_SDMMC2 - bool "SDMMC2" - default n - depends on STM32F7_HAVE_SDMMC2 - select STM32F7_SDMMC - select ARCH_HAVE_SDIO - select ARCH_HAVE_SDIOWAIT_WRCOMPLETE - select ARCH_HAVE_SDIO_PREFLIGHT - select SDIO_BLOCKSETUP - -config STM32F7_SPDIFRX - bool "SPDIFRX" - default n - -config STM32F7_SPI1 - bool "SPI1" - default n - select SPI - select STM32F7_SPI - -config STM32F7_SPI2 - bool "SPI2" - default n - select SPI - select STM32F7_SPI - -config STM32F7_SPI3 - bool "SPI3" - default n - select SPI - select STM32F7_SPI - -config STM32F7_SPI4 - bool "SPI4" - default n - depends on STM32F7_HAVE_SPI4 - select SPI - select STM32F7_SPI - -config STM32F7_SPI5 - bool "SPI5" - default n - depends on STM32F7_HAVE_SPI5 - select SPI - select STM32F7_SPI - -config STM32F7_SPI6 - bool "SPI6" - default n - depends on STM32F7_HAVE_SPI6 - select SPI - select STM32F7_SPI - -config STM32F7_SYSCFG - bool "SYSCFG" - default y - -config STM32F7_TIM1 - bool "TIM1" - default n - select STM32F7_TIM - -config STM32F7_TIM2 - bool "TIM2" - default n - select STM32F7_TIM - -config STM32F7_TIM3 - bool "TIM3" - default n - select STM32F7_TIM - -config STM32F7_TIM4 - bool "TIM4" - default n - select STM32F7_TIM - -config STM32F7_TIM5 - bool "TIM5" - default n - select STM32F7_TIM - -config STM32F7_TIM6 - bool "TIM6" - default n - select STM32F7_TIM - -config STM32F7_TIM7 - bool "TIM7" - default n - select STM32F7_TIM - -config STM32F7_TIM8 - bool "TIM8" - default n - select STM32F7_TIM - -config STM32F7_TIM9 - bool "TIM9" - default n - select STM32F7_TIM - -config STM32F7_TIM10 - bool "TIM10" - default n - select STM32F7_TIM - -config STM32F7_TIM11 - bool "TIM11" - default n - select STM32F7_TIM - -config STM32F7_TIM12 - bool "TIM12" - default n - select STM32F7_TIM - -config STM32F7_TIM13 - bool "TIM13" - default n - select STM32F7_TIM - -config STM32F7_TIM14 - bool "TIM14" - default n - select STM32F7_TIM - -config STM32F7_USART1 - bool "USART1" - default n - select USART1_SERIALDRIVER - select ARCH_HAVE_SERIAL_TERMIOS - select STM32F7_USART - -config STM32F7_USART2 - bool "USART2" - default n - select USART2_SERIALDRIVER - select ARCH_HAVE_SERIAL_TERMIOS - select STM32F7_USART - -config STM32F7_USART3 - bool "USART3" - default n - select ARCH_HAVE_SERIAL_TERMIOS - select USART3_SERIALDRIVER - select STM32F7_USART - -config STM32F7_UART4 - bool "UART4" - default n - select ARCH_HAVE_SERIAL_TERMIOS - select UART4_SERIALDRIVER - select STM32F7_USART - -config STM32F7_UART5 - bool "UART5" - default n - select ARCH_HAVE_SERIAL_TERMIOS - select UART5_SERIALDRIVER - select STM32F7_USART - -config STM32F7_USART6 - bool "USART6" - default n - select ARCH_HAVE_SERIAL_TERMIOS - select USART6_SERIALDRIVER - select STM32F7_USART - -config STM32F7_UART7 - bool "UART7" - default n - select ARCH_HAVE_SERIAL_TERMIOS - select UART7_SERIALDRIVER - select STM32F7_USART - -config STM32F7_UART8 - bool "UART8" - default n - select ARCH_HAVE_SERIAL_TERMIOS - select UART8_SERIALDRIVER - select STM32F7_USART - -config STM32F7_IWDG - bool "IWDG" - default n - select WATCHDOG - -config STM32F7_WWDG - bool "WWDG" - default n - select WATCHDOG - -endmenu - -config STM32F7_SYSCFG_IOCOMPENSATION - bool "SYSCFG I/O Compensation" - default n - ---help--- - By default the I/O compensation cell is not used. However when the I/O - output buffer speed is configured in 50 MHz or 100 MHz mode, it is - recommended to use the compensation cell for slew rate control on I/O - tf(IO)out)/tr(IO)out commutation to reduce the I/O noise on power supply. - - The I/O compensation cell can be used only when the supply voltage ranges - from 2.4 to 3.6 V. - -menu "OTG Configuration" - depends on STM32F7_OTGFS - -config OTG_ID_GPIO_DISABLE - bool "Disable the use of GPIO_OTG_ID pin." - default n - ---help--- - Disables/Enables the use of GPIO_OTG_ID pin. This allows non OTG use - cases to reuse this GPIO pin and ensure it is not set incorrectlty - during OS boot. - -endmenu - -menu "U[S]ART Configuration" - depends on STM32F7_USART - -config USART1_RS485 - bool "RS-485 on USART1" - default n - depends on STM32F7_USART1 - ---help--- - Enable RS-485 interface on USART1. Your board config will have to - provide GPIO_USART1_RS485_DIR pin definition. Currently it cannot be - used with USART1_RXDMA. - -config USART1_RS485_DIR_POLARITY - int "USART1 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on USART1_RS485 - ---help--- - Polarity of DIR pin for RS-485 on USART1. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config USART1_RXDMA - bool "USART1 Rx DMA" - default n - depends on STM32F7_USART1 && STM32F7_DMA2 - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -config USART1_TXDMA - bool "USART1 Tx DMA" - default n - depends on STM32F7_USART1 && STM32F7_DMA2 - ---help--- - In high data rate usage, Rx DMA may reduce CPU Load - -config USART2_RS485 - bool "RS-485 on USART2" - default n - depends on STM32F7_USART2 - ---help--- - Enable RS-485 interface on USART2. Your board config will have to - provide GPIO_USART2_RS485_DIR pin definition. Currently it cannot be - used with USART2_RXDMA. - -config USART2_RS485_DIR_POLARITY - int "USART2 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on USART2_RS485 - ---help--- - Polarity of DIR pin for RS-485 on USART2. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config USART2_RXDMA - bool "USART2 Rx DMA" - default n - depends on STM32F7_USART2 && STM32F7_DMA1 - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -config USART2_TXDMA - bool "USART2 Tx DMA" - default n - depends on STM32F7_USART2 && STM32F7_DMA1 - ---help--- - In high data rate usage, Rx DMA may reduce CPU Load - -config USART3_RS485 - bool "RS-485 on USART3" - default n - depends on STM32F7_USART3 - ---help--- - Enable RS-485 interface on USART3. Your board config will have to - provide GPIO_USART3_RS485_DIR pin definition. Currently it cannot be - used with USART3_RXDMA. - -config USART3_RS485_DIR_POLARITY - int "USART3 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on USART3_RS485 - ---help--- - Polarity of DIR pin for RS-485 on USART3. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config USART3_RXDMA - bool "USART3 Rx DMA" - default n - depends on STM32F7_USART3 && STM32F7_DMA1 - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -config USART3_TXDMA - bool "USART3 Tx DMA" - default n - depends on STM32F7_USART3 && STM32F7_DMA1 - ---help--- - In high data rate usage, Rx DMA may reduce CPU Load - -config UART4_RS485 - bool "RS-485 on UART4" - default n - depends on STM32F7_UART4 - ---help--- - Enable RS-485 interface on UART4. Your board config will have to - provide GPIO_UART4_RS485_DIR pin definition. Currently it cannot be - used with UART4_RXDMA. - -config UART4_RS485_DIR_POLARITY - int "UART4 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on UART4_RS485 - ---help--- - Polarity of DIR pin for RS-485 on UART4. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config UART4_RXDMA - bool "UART4 Rx DMA" - default n - depends on STM32F7_UART4 && STM32F7_DMA1 - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -config UART4_TXDMA - bool "UART4 Tx DMA" - default n - depends on STM32F7_UART4 && STM32F7_DMA1 - ---help--- - In high data rate usage, Rx DMA may reduce CPU Load - -config UART5_RS485 - bool "RS-485 on UART5" - default n - depends on STM32F7_UART5 - ---help--- - Enable RS-485 interface on UART5. Your board config will have to - provide GPIO_UART5_RS485_DIR pin definition. Currently it cannot be - used with UART5_RXDMA. - -config UART5_RS485_DIR_POLARITY - int "UART5 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on UART5_RS485 - ---help--- - Polarity of DIR pin for RS-485 on UART5. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config UART5_RXDMA - bool "UART5 Rx DMA" - default n - depends on STM32F7_UART5 && STM32F7_DMA1 - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -config UART5_TXDMA - bool "UART5 Tx DMA" - default n - depends on STM32F7_UART5 && STM32F7_DMA1 - ---help--- - In high data rate usage, Rx DMA may reduce CPU Load - -config USART6_RS485 - bool "RS-485 on USART6" - default n - depends on STM32F7_USART6 - ---help--- - Enable RS-485 interface on USART6. Your board config will have to - provide GPIO_USART6_RS485_DIR pin definition. Currently it cannot be - used with USART6_RXDMA. - -config USART6_RS485_DIR_POLARITY - int "USART6 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on USART6_RS485 - ---help--- - Polarity of DIR pin for RS-485 on USART6. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config USART6_RXDMA - bool "USART6 Rx DMA" - default n - depends on STM32F7_USART6 && STM32F7_DMA2 - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -config USART6_TXDMA - bool "USART6 Tx DMA" - default n - depends on STM32F7_USART6 && STM32F7_DMA2 - ---help--- - In high data rate usage, Rx DMA may reduce CPU Load - -config UART7_RS485 - bool "RS-485 on UART7" - default n - depends on STM32F7_UART7 - ---help--- - Enable RS-485 interface on UART7. Your board config will have to - provide GPIO_UART7_RS485_DIR pin definition. Currently it cannot be - used with UART7_RXDMA. - -config UART7_RS485_DIR_POLARITY - int "UART7 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on UART7_RS485 - ---help--- - Polarity of DIR pin for RS-485 on UART7. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config UART7_RXDMA - bool "UART7 Rx DMA" - default n - depends on STM32F7_UART7 && STM32F7_DMA1 - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -config UART7_TXDMA - bool "UART7 Tx DMA" - default n - depends on STM32F7_UART7 && STM32F7_DMA1 - ---help--- - In high data rate usage, Rx DMA may reduce CPU Load - -config UART8_RS485 - bool "RS-485 on UART8" - default n - depends on STM32F7_UART8 - ---help--- - Enable RS-485 interface on UART8. Your board config will have to - provide GPIO_UART8_RS485_DIR pin definition. Currently it cannot be - used with UART8_RXDMA. - -config UART8_RS485_DIR_POLARITY - int "UART8 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on UART8_RS485 - ---help--- - Polarity of DIR pin for RS-485 on UART8. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config UART8_RXDMA - bool "UART8 Rx DMA" - default n - depends on STM32F7_UART8 && STM32F7_DMA1 - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -config UART8_TXDMA - bool "UART8 Tx DMA" - default n - depends on STM32F7_UART8 && STM32F7_DMA1 - ---help--- - In high data rate usage, Rx DMA may reduce CPU Load - -config STM32F7_SERIAL_RXDMA_BUFFER_SIZE - int "Rx DMA buffer size" - default 32 - depends on USART1_RXDMA || USART2_RXDMA || USART3_RXDMA || UART4_RXDMA || UART5_RXDMA || USART6_RXDMA || UART7_RXDMA || UART8_RXDMA - ---help--- - The DMA buffer size when using RX DMA to emulate a FIFO. - - When streaming data, the generic serial layer will be called - every time the FIFO receives half this number of bytes. - - Value given here will be rounded up to next multiple of 32 bytes. - -config STM32F7_SERIAL_DISABLE_REORDERING - bool "Disable reordering of ttySx devices." - depends on STM32F7_USART1 || STM32F7_USART2 || STM32F7_USART3 || STM32F7_UART4 || STM32F7_UART5 || STM32F7_USART6 || STM32F7_UART7 || STM32F7_UART8 - default n - ---help--- - NuttX per default reorders the serial ports (/dev/ttySx) so that the - console is always on /dev/ttyS0. If more than one UART is in use this - can, however, have the side-effect that all port mappings - (hardware USART1 -> /dev/ttyS0) change if the console is moved to another - UART. This is in particular relevant if a project uses the USB console - in some boards and a serial console in other boards, but does not - want the side effect of having all serial port names change when just - the console is moved from serial to USB. - -config STM32F7_FLOWCONTROL_BROKEN - bool "Use Software UART RTS flow control" - depends on STM32F7_USART && SERIAL_IFLOWCONTROL_WATERMARKS - default n - ---help--- - Enable UART RTS flow control using Software. Because STM - Current STM32 have broken HW based RTS behavior (they assert - nRTS after every byte received) Enable this setting workaround - this issue by using software based management of RTS - -config STM32F7_USART_BREAKS - bool "Add TIOxSBRK to support sending Breaks" - depends on STM32F7_USART - default n - ---help--- - Add TIOCxBRK routines to send a line break per the STM32 manual, the - break will be a pulse based on the value M. This is not a BSD compatible - break. - -config STM32F7_SERIALBRK_BSDCOMPAT - bool "Use GPIO To send Break" - depends on STM32F7_USART && STM32F7_USART_BREAKS - default n - ---help--- - Enable using GPIO on the TX pin to send a BSD compatible break: - TIOCSBRK will start the break and TIOCCBRK will end the break. - The current STM32F7 U[S]ARTS have no way to leave the break on - (TX=LOW) because software starts the break and then the hardware - automatically clears the break. This makes it difficult to send - a long break. - -config STM32F7_USART_SINGLEWIRE - bool "Single Wire Support" - default n - depends on STM32F7_USART - ---help--- - Enable single wire UART support. The option enables support for the - TIOCSSINGLEWIRE ioctl in the STM32F7 serial driver. - -config STM32F7_USART_INVERT - bool "Signal Invert Support" - default n - depends on STM32F7_USART - ---help--- - Enable signal inversion UART support. The option enables support for the - TIOCSINVERT ioctl in the STM32F7 serial driver. - -config STM32F7_USART_SWAP - bool "Swap RX/TX pins support" - default n - depends on STM32F7_USART - ---help--- - Enable RX/TX pin swapping support. The option enables support for the - TIOCSSWAP ioctl in the STM32F7 serial driver. - -if PM - -config STM32F7_PM_SERIAL_ACTIVITY - int "PM serial activity" - default 10 - ---help--- - PM activity reported to power management logic on every serial - interrupt. - -endif - -endmenu # U[S]ART Configuration - -menu "STM32F7_OTG_HS Configuration" - depends on STM32F7_OTGFSHS - -choice - prompt "ULPI Selection" - default STM32F7_NO_ULPI - -config STM32F7_NO_ULPI - bool "No External ULPI" - ---help--- - Select to enable the presence of an external ULPI PHY - -config STM32F7_EXTERNAL_ULPI - bool "External ULPI" - depends on STM32F7_HAVE_EXTERNAL_ULPI - ---help--- - Select to enable the presence of an external ULPI PHY - -config STM32F7_INTERNAL_ULPI - bool "Internal ULPI PHY" - depends on STM32F7_HAVE_INTERNAL_ULPI - ---help--- - Select to enable the internal ULPI for USB HS -endchoice #"ULPI Selection" - -endmenu # OTG_HS Config - -config STM32F7_EXTERNAL_RAM - bool "External RAM on FMC" - default n - depends on STM32F7_FMC - select ARCH_HAVE_HEAP2 - ---help--- - In addition to internal SDRAM, external RAM may be available through the FMC. - -menu "QuadSPI Configuration" - depends on STM32F7_QUADSPI - -config STM32F7_QSPI_FLASH_SIZE - int "Size of attached serial flash, bytes" - default 16777216 - range 1 2147483648 - ---help--- - The STM32F7 QSPI peripheral requires the size of the Flash be specified - -config STM32F7_QSPI_FIFO_THESHOLD - int "Number of bytes before asserting FIFO threshold flag" - default 4 - range 1 16 - ---help--- - The STM32F7 QSPI peripheral requires that the FIFO threshold be specified - I would leave it at the default value of 4 unless you know what you are doing. - -config STM32F7_QSPI_CSHT - int "Number of cycles Chip Select must be inactive between transactions" - default 1 - range 1 8 - ---help--- - The STM32F7 QSPI peripheral requires that it be specified the minimum number - of AHB cycles that Chip Select be held inactive between transactions. - -choice - prompt "Transfer technique" - default STM32F7_QSPI_DMA - ---help--- - You can choose between using polling, interrupts, or DMA to transfer data - over the QSPI interface. - -config STM32F7_QSPI_POLLING - bool "Polling" - ---help--- - Use conventional register I/O with status polling to transfer data. - -config STM32F7_QSPI_INTERRUPTS - bool "Interrupts" - ---help--- - User interrupt driven I/O transfers. - -config STM32F7_QSPI_DMA - bool "DMA" - depends on STM32F7_DMA - ---help--- - Use DMA to improve QSPI transfer performance. - -endchoice - -choice - prompt "Bank selection" - default STM32F7_QSPI_MODE_BANK1 - ---help--- - You can choose between using polling, interrupts, or DMA to transfer data - over the QSPI interface. - -config STM32F7_QSPI_MODE_BANK1 - bool "Bank 1" - -config STM32F7_QSPI_MODE_BANK2 - bool "Bank 2" - -config STM32F7_QSPI_MODE_DUAL - bool "Dual Bank" - -endchoice - -choice - prompt "DMA Priority" - default STM32F7_QSPI_DMAPRIORITY_MEDIUM - depends on STM32F7_DMA - ---help--- - The DMA controller supports priority levels. You are probably fine - with the default of 'medium' except for special cases. In the event - of contention between to channels at the same priority, the lower - numbered channel has hardware priority over the higher numbered one. - -config STM32F7_QSPI_DMAPRIORITY_VERYHIGH - bool "Very High priority" - depends on STM32F7_DMA - ---help--- - 'Highest' priority. - -config STM32F7_QSPI_DMAPRIORITY_HIGH - bool "High priority" - depends on STM32F7_DMA - ---help--- - 'High' priority. - -config STM32F7_QSPI_DMAPRIORITY_MEDIUM - bool "Medium priority" - depends on STM32F7_DMA - ---help--- - 'Medium' priority. - -config STM32F7_QSPI_DMAPRIORITY_LOW - bool "Low priority" - depends on STM32F7_DMA - ---help--- - 'Low' priority. - -endchoice - -config STM32F7_QSPI_DMATHRESHOLD - int "QSPI DMA threshold" - default 4 - depends on STM32F7_QSPI_DMA - ---help--- - When QSPI DMA is enabled, small DMA transfers will still be performed - by polling logic. This value is the threshold below which transfers - will still be performed by conventional register status polling. - -config STM32F7_QSPI_DMADEBUG - bool "QSPI DMA transfer debug" - depends on STM32F7_QSPI_DMA && DEBUG_SPI && DEBUG_DMA - default n - ---help--- - Enable special debug instrumentation to analyze QSPI DMA data transfers. - This logic is as non-invasive as possible: It samples DMA - registers at key points in the data transfer and then dumps all of - the registers at the end of the transfer. - -config STM32F7_QSPI_REGDEBUG - bool "QSPI Register level debug" - depends on DEBUG_SPI_INFO - default n - ---help--- - Output detailed register-level QSPI device debug information. - Requires also CONFIG_DEBUG_SPI_INFO. - -endmenu - -menu "SPI Configuration" - depends on STM32F7_SPI - -config STM32F7_SPI_INTERRUPTS - bool "Interrupt driver SPI" - default n - ---help--- - Select to enable interrupt driven SPI support. Non-interrupt-driven, - poll-waiting is recommended if the interrupt rate would be to high in - the interrupt driven case. - -config STM32F7_SPI_DMATHRESHOLD - int "SPI DMA threshold" - default 4 - depends on STM32F7_SPI_DMA - ---help--- - When SPI DMA is enabled, small DMA transfers will still be performed - by polling logic. But we need a threshold value to determine what - is small. - -config STM32F7_SPI1_DMA - bool "SPI1 DMA" - default n - depends on STM32F7_SPI1 && !STM32F7_SPI_INTERRUPT - select STM32F7_SPI_DMA - ---help--- - Use DMA to improve SPI1 transfer performance. Cannot be used with STM32F7_SPI_INTERRUPT. - -config STM32F7_SPI1_DMA_BUFFER - int "SPI1 DMA buffer size" - default 0 - depends on STM32F7_SPI1_DMA - ---help--- - Add a properly aligned DMA buffer for RX and TX DMA for SPI1. - -config STM32F7_SPI2_DMA - bool "SPI2 DMA" - default n - depends on STM32F7_SPI2 && !STM32F7_SPI_INTERRUPT - select STM32F7_SPI_DMA - ---help--- - Use DMA to improve SPI2 transfer performance. Cannot be used with STM32F7_SPI_INTERRUPT. - -config STM32F7_SPI2_DMA_BUFFER - int "SPI2 DMA buffer size" - default 0 - depends on STM32F7_SPI2_DMA - ---help--- - Add a properly aligned DMA buffer for RX and TX DMA for SPI2. - -config STM32F7_SPI3_DMA - bool "SPI3 DMA" - default n - depends on STM32F7_SPI3 && !STM32F7_SPI_INTERRUPT - select STM32F7_SPI_DMA - ---help--- - Use DMA to improve SPI3 transfer performance. Cannot be used with STM32F7_SPI_INTERRUPT. - -config STM32F7_SPI3_DMA_BUFFER - int "SPI3 DMA buffer size" - default 0 - depends on STM32F7_SPI3_DMA - ---help--- - Add a properly aligned DMA buffer for RX and TX DMA for SPI3. - -config STM32F7_SPI4_DMA - bool "SPI4 DMA" - default n - depends on STM32F7_SPI4 && !STM32F7_SPI_INTERRUPT - select STM32F7_SPI_DMA - ---help--- - Use DMA to improve SPI4 transfer performance. Cannot be used with STM32F7_SPI_INTERRUPT. - -config STM32F7_SPI4_DMA_BUFFER - int "SPI4 DMA buffer size" - default 0 - depends on STM32F7_SPI4_DMA - ---help--- - Add a properly aligned DMA buffer for RX and TX DMA for SPI4. - -config STM32F7_SPI5_DMA - bool "SPI5 DMA" - default n - depends on STM32F7_SPI5 && !STM32F7_SPI_INTERRUPT - select STM32F7_SPI_DMA - ---help--- - Use DMA to improve SPI5 transfer performance. Cannot be used with STM32F7_SPI_INTERRUPT. - -config STM32F7_SPI5_DMA_BUFFER - int "SPI5 DMA buffer size" - default 0 - depends on STM32F7_SPI5_DMA - ---help--- - Add a properly aligned DMA buffer for RX and TX DMA for SPI5. - -config STM32F7_SPI6_DMA - bool "SPI6 DMA" - default n - depends on STM32F7_SPI6 && !STM32F7_SPI_INTERRUPT - select STM32F7_SPI_DMA - ---help--- - Use DMA to improve SPI6 transfer performance. Cannot be used with STM32F7_SPI_INTERRUPT. - -config STM32F7_SPI6_DMA_BUFFER - int "SPI6 DMA buffer size" - default 0 - depends on STM32F7_SPI6_DMA - ---help--- - Add a properly aligned DMA buffer for RX and TX DMA for SPI6. - -endmenu # "SPI Configuration" - -menu "I2S Configuration" - depends on STM32F7_I2S - -config STM32F7_I2S_MAXINFLIGHT - int "I2S queue size" - default 16 - ---help--- - This is the total number of transfers, both RX and TX, that can be - enqueue before the caller is required to wait. This setting - determines the number certain queue data structures that will be - pre-allocated. - -if STM32F7_I2S1 - -comment "I2S1 Configuration" - -config STM32F7_I2S1_MCK - bool "I2S1_MCK" - default n - ---help--- - TBD. - -config STM32F7_I2S1_RX - bool "Enable I2S1 receiver" - default n - ---help--- - Enable I2S receipt logic - -config STM32F7_I2S1_TX - bool "Enable I2S1 transmitter" - default n - ---help--- - Enable I2S transmission logic - -config STM32F7_I2S1_DATALEN - int "I2S1 Data width (bits)" - default 16 - ---help--- - Data width in bits. This is a default value and may be change - via the I2S interface - -endif #STM32F7_I2S1 - -if STM32F7_I2S2 - -comment "I2S2 Configuration" - -config STM32F7_I2S2_MCK - bool "I2S2_MCK" - default n - ---help--- - TBD. - -config STM32F7_I2S2_RX - bool "Enable I2S2 receiver" - default n - ---help--- - Enable I2S receipt logic - -config STM32F7_I2S2_TX - bool "Enable I2S2 transmitter" - default n - ---help--- - Enable I2S transmission logic - -config STM32F7_I2S2_DATALEN - int "I2S2 Data width (bits)" - default 16 - ---help--- - Data width in bits. This is a default value and may be change - via the I2S interface - -endif #STM32F7_I2S2 - -if STM32F7_I2S3 - -comment "I2S3 Configuration" - -config STM32F7_I2S3_MCK - bool "I2S3_MCK" - default n - ---help--- - TBD. - -config STM32F7_I2S3_RX - bool "Enable I2S3 receiver" - default n - ---help--- - Enable I2S receipt logic - -config STM32F7_I2S3_TX - bool "Enable I2S3 transmitter" - default n - ---help--- - Enable I2S transmission logic - -config STM32_I2S3_DATALEN - int "I2S3 Data width (bits)" - default 16 - ---help--- - Data width in bits. This is a default value and may be change - via the I2S interface - -endif #STM32F7_I2S3 - -config STM32F7_I2S_DMADEBUG - bool "I2S DMA transfer debug" - depends on DEBUG_DMA - default n - ---help--- - Enable special debug instrumentation analyze I2S DMA data transfers. - This logic is as non-invasive as possible: It samples DMA - registers at key points in the data transfer and then dumps all of - the registers at the end of the transfer. - -config STM32_I2S_REGDEBUG - bool "SSC Register level debug" - depends on DEBUG - default n - ---help--- - Output detailed register-level SSC device debug information. - Very invasive! Requires also DEBUG. - -endmenu # I2S Configuration - -menu "I2C Configuration" - depends on STM32F7_I2C - -config STM32F7_I2C_DYNTIMEO - bool "Use dynamic timeouts" - default n - depends on STM32F7_I2C - -config STM32F7_I2C_DYNTIMEO_USECPERBYTE - int "Timeout Microseconds per Byte" - default 500 - depends on STM32F7_I2C_DYNTIMEO - -config STM32F7_I2C_DYNTIMEO_STARTSTOP - int "Timeout for Start/Stop (Milliseconds)" - default 1000 - depends on STM32F7_I2C_DYNTIMEO - -config STM32F7_I2CTIMEOSEC - int "Timeout seconds" - default 0 - depends on STM32F7_I2C - -config STM32F7_I2CTIMEOMS - int "Timeout Milliseconds" - default 500 - depends on STM32F7_I2C && !STM32F7_I2C_DYNTIMEO - -config STM32F7_I2CTIMEOTICKS - int "Timeout for Done and Stop (ticks)" - default 500 - depends on STM32F7_I2C && !STM32F7_I2C_DYNTIMEO - -endmenu # "I2C Configuration" - -menu "SD/MMC Configuration" - depends on STM32F7_SDMMC - -config STM32F7_SDMMC_XFRDEBUG - bool "SDMMC transfer debug" - depends on DEBUG_FS_INFO - default n - ---help--- - Enable special debug instrumentation analyze SDMMC data transfers. - This logic is as non-invasive as possible: It samples SDMMC - registers at key points in the data transfer and then dumps all of - the registers at the end of the transfer. If DEBUG_DMA is also - enabled, then DMA register will be collected as well. Requires also - DEBUG_FS and CONFIG_DEBUG_INFO. - -config STM32F7_SDMMC_DMA - bool "Support DMA data transfers" - default n - select SDIO_DMA - depends on STM32F7_DMA - ---help--- - Support DMA data transfers. - -menu "SDMMC1 Configuration" - depends on STM32F7_SDMMC1 - -config STM32F7_SDMMC1_DMAPRIO - hex "SDMMC1 DMA priority" - default 0x00010000 - ---help--- - Select SDMMC1 DMA priority. - - Options are: 0x00000000 low, 0x00010000 medium, - 0x00020000 high, 0x00030000 very high. Default: medium. - -config SDMMC1_WIDTH_D1_ONLY - bool "Use D1 only on SDMMC1" - default n - ---help--- - Select 1-bit transfer mode. Default: 4-bit transfer mode. - -config SDMMC1_SDIO_MODE - bool "SDIO Card Support" - default n - ---help--- - Build in additional support needed only for SDIO cards (vs. SD - memory cards) - -config SDMMC1_SDIO_PULLUP - bool "Enable internal Pull-Ups" - default n - ---help--- - If you are using an external SDCard module that does not have the - pull-up resistors for the SDIO interface (like the Gadgeteer SD Card - Module) then enable this option to activate the internal pull-up - resistors. - -endmenu # "SDMMC1 Configuration" - -menu "SDMMC2 Configuration" - depends on STM32F7_SDMMC2 - -config STM32F7_SDMMC2_DMAPRIO - hex "SDMMC2 DMA priority" - default 0x00010000 - ---help--- - Select SDMMC2 DMA priority. - - Options are: 0x00000000 low, 0x00010000 medium, - 0x00020000 high, 0x00030000 very high. Default: medium. - -config SDMMC2_WIDTH_D1_ONLY - bool "Use D1 only on SDMMC2" - default n - ---help--- - Select 1-bit transfer mode. Default: 4-bit transfer mode. - -config SDMMC2_SDIO_MODE - bool "SDIO Card Support" - default n - ---help--- - Build in additional support needed only for SDIO cards (vs. SD - memory cards) - -config SDMMC2_SDIO_PULLUP - bool "Enable internal Pull-Ups" - default n - ---help--- - If you are using an external SDCard module that does not have the - pull-up resistors for the SDIO interface (like the Gadgeteer SD Card - Module) then enable this option to activate the internal pull-up - resistors. - -endmenu # "SDMMC2 Configuration" -endmenu # "SD/MMC Configuration" - -if STM32F7_BKPSRAM - -config STM32F7_BBSRAM - bool "BBSRAM File Support" - default n - -config STM32F7_BBSRAM_FILES - int "Max Files to support in BBSRAM" - default 4 - depends on STM32F7_BBSRAM - -config STM32F7_SAVE_CRASHDUMP - bool "Enable Saving Panic to BBSRAM" - default n - depends on STM32F7_BBSRAM - -endif # STM32F7_BKPSRAM - -config STM32F7_HAVE_RTC_SUBSECONDS - bool - select ARCH_HAVE_RTC_SUBSECONDS - default y - -menu "RTC Configuration" - depends on STM32F7_RTC - -config STM32F7_RTC_MAGIC_REG - int "BKP register" - default 0 - range 0 31 - ---help--- - The BKP register used to store/check the Magic value to determine if - RTC is already setup - -config STM32F7_RTC_MAGIC - hex "RTC Magic 1" - default 0xfacefeed - ---help--- - Value used as Magic to determine if the RTC is already setup - -config STM32F7_RTC_MAGIC_TIME_SET - hex "RTC Magic 2" - default 0xf00dface - ---help--- - Value used as Magic to determine if the RTC has been setup and has - time set - -choice - prompt "RTC clock source" - default STM32F7_RTC_LSECLOCK - -config STM32F7_RTC_HSECLOCK - bool "HSE clock" - ---help--- - Drive the RTC with the HSE clock, divided down to 1MHz. - -config STM32F7_RTC_LSECLOCK - bool "LSE clock" - ---help--- - Drive the RTC with the LSE clock - -config STM32F7_RTC_LSICLOCK - bool "LSI clock" - ---help--- - Drive the RTC with the LSI clock - -endchoice #"RTC clock source" - -if STM32F7_RTC_LSECLOCK - -config STM32F7_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY - bool "Automatically boost the LSE oscillator drive capability level until it starts-up" - default n - ---help--- - This will cycle through the values from low to high. To avoid - damaging the crystal. We want to use the lowest setting that gets - the OSC running. See app note AN2867 - - 0 = Low drive capability (default) - 1 = Medium high drive capability - 2 = Medium low drive capability - 3 = High drive capability - -config STM32F7_RTC_LSECLOCK_START_DRV_CAPABILITY - int "LSE oscillator drive capability level at LSE start-up" - default 0 - range 0 3 - depends on !STM32F7_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY - ---help--- - 0 = Low drive capability (default) - 1 = Medium high drive capability - 2 = Medium low drive capability - 3 = High drive capability - -config STM32F7_RTC_LSECLOCK_RUN_DRV_CAPABILITY - int "LSE oscillator drive capability level after LSE start-up" - default 0 - range 0 3 - depends on !STM32F7_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY - ---help--- - 0 = Low drive capability (default) - 1 = Medium high drive capability - 2 = Medium low drive capability - 3 = High drive capability - -endif # STM32F7_RTC_LSECLOCK - -endmenu # RTC Configuration - -config STM32F7_CUSTOM_CLOCKCONFIG - bool "Custom clock configuration" - default n - ---help--- - Enables special, board-specific STM32 clock configuration. - -config STM32F7_DTCMEXCLUDE - bool "Exclude DTCM SRAM from the heap" - default LIBC_ARCH_ELF - depends on ARMV7M_HAVE_DTCM - ---help--- - Exclude DTCM SRAM from the HEAP because it appears to be impossible - to execute ELF modules from DTCM RAM (REVISIT!). - -config STM32F7_DTCM_PROCFS - bool "DTCM SRAM PROCFS support" - default n - depends on ARMV7M_DTCM && FS_PROCFS - ---help--- - Select to build in support for /proc/dtcm. Reading from /proc/dtcm - will provide statistics about DTCM memory use similar to what you - would get from mallinfo() for the user heap. - -config STM32F7_DMACAPABLE - bool "Workaround non-DMA capable memory" - depends on ARCH_DMA - default n - ---help--- - This option enables the DMA interface stm32_dmacapable that can be - used to check if it is possible to do DMA from the selected address. - Drivers then may use this information to determine if they should - attempt the DMA or fall back to a different transfer method. - -config STM32F7_DMACAPABLE_ASSUME_CACHE_ALIGNED - bool "Do not disqualify DMA capability based on cache alignment" - depends on STM32F7_DMACAPABLE && ARMV7M_DCACHE && !ARMV7M_DCACHE_WRITETHROUGH - default n - ---help--- - This option configures the stm32_dmacapable to not disqualify - DMA operations on memory that is not dcache aligned based solely - on the starting address and byte count. - - Use this when ALL buffer extents are known to be aligned, but the - the count does not use the complete buffer. - -menu "Timer Configuration" - -if SCHED_TICKLESS - -config STM32F7_TICKLESS_TIMER - int "Tickless hardware timer" - default 2 - range 1 14 - ---help--- - If the Tickless OS feature is enabled, then one clock must be - assigned to provided the timer needed by the OS. - -config STM32F7_TICKLESS_CHANNEL - int "Tickless timer channel" - default 1 - range 1 4 - ---help--- - If the Tickless OS feature is enabled, the one clock must be - assigned to provided the free-running timer needed by the OS - and one channel on that clock is needed to handle intervals. - -endif # SCHED_TICKLESS - -config STM32F7_PWM_LL_OPS - bool "PWM low-level operations" - default n - ---help--- - Enable low-level PWM ops. - -config STM32F7_TIM1_PWM - bool "TIM1 PWM" - default n - depends on STM32F7_TIM1 - select STM32F7_PWM - ---help--- - Reserve timer 1 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32F7_TIM1 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32F7_TIM1_PWM - -config STM32F7_TIM1_MODE - int "TIM1 Mode" - default 0 - range 0 4 - ---help--- - Specifies the timer mode. - -config STM32F7_TIM1_LOCK - int "TIM1 Lock Level Configuration" - default 0 - range 0 3 - ---help--- - Timer 1 lock level configuration - -config STM32F7_TIM1_TDTS - int "TIM1 t_DTS Division" - default 0 - range 0 2 - ---help--- - Timer 1 dead-time and sampling clock (t_DTS) division - -config STM32F7_TIM1_DEADTIME - int "TIM1 Initial Dead-time" - default 0 - range 0 255 - ---help--- - Timer 1 initial dead-time - -if STM32F7_PWM_MULTICHAN - -config STM32F7_TIM1_CHANNEL1 - bool "TIM1 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32F7_TIM1_CHANNEL1 - -config STM32F7_TIM1_CH1MODE - int "TIM1 Channel 1 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32F7_TIM1_CH1OUT - bool "TIM1 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -config STM32F7_TIM1_CH1NOUT - bool "TIM1 Channel 1 Complementary Output" - default n - ---help--- - Enables channel 1 Complementary Output. - -endif # STM32F7_TIM1_CHANNEL1 - -config STM32F7_TIM1_CHANNEL2 - bool "TIM1 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32F7_TIM1_CHANNEL2 - -config STM32F7_TIM1_CH2MODE - int "TIM1 Channel 2 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32F7_TIM1_CH2OUT - bool "TIM1 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -config STM32F7_TIM1_CH2NOUT - bool "TIM1 Channel 2 Complementary Output" - default n - ---help--- - Enables channel 2 Complementary Output. - -endif # STM32F7_TIM1_CHANNEL2 - -config STM32F7_TIM1_CHANNEL3 - bool "TIM1 Channel 3" - default n - ---help--- - Enables channel 3. - -if STM32F7_TIM1_CHANNEL3 - -config STM32F7_TIM1_CH3MODE - int "TIM1 Channel 3 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32F7_TIM1_CH3OUT - bool "TIM1 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -config STM32F7_TIM1_CH3NOUT - bool "TIM1 Channel 3 Complementary Output" - default n - ---help--- - Enables channel 3 Complementary Output. - -endif # STM32F7_TIM1_CHANNEL3 - -config STM32F7_TIM1_CHANNEL4 - bool "TIM1 Channel 4" - default n - ---help--- - Enables channel 4. - -if STM32F7_TIM1_CHANNEL4 - -config STM32F7_TIM1_CH4MODE - int "TIM1 Channel 4 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32F7_TIM1_CH4OUT - bool "TIM1 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32F7_TIM1_CHANNEL4 - -config STM32F7_TIM1_CHANNEL5 - bool "TIM1 Channel 5 (internal)" - default n - ---help--- - Enables channel 5 (not available externally) - -if STM32F7_TIM1_CHANNEL5 - -config STM32F7_TIM1_CH5MODE - int "TIM1 Channel 5 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32F7_TIM1_CH5OUT - bool "TIM1 Channel 5 Output" - default n - ---help--- - Enables channel 5 output. - -endif # STM32F7_TIM1_CHANNEL5 - -config STM32F7_TIM1_CHANNEL6 - bool "TIM1 Channel 6 (internal)" - default n - ---help--- - Enables channel 6 (not available externally) - -if STM32F7_TIM1_CHANNEL6 - -config STM32F7_TIM1_CH6MODE - int "TIM1 Channel 6 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32F7_TIM1_CH6OUT - bool "TIM1 Channel 6 Output" - default n - ---help--- - Enables channel 6 output. - -endif # STM32F7_TIM1_CHANNEL6 - -endif # STM32F7_PWM_MULTICHAN - -if !STM32F7_PWM_MULTICHAN - -config STM32F7_TIM1_CHANNEL - int "TIM1 PWM Output Channel" - default 1 - range 1 4 - ---help--- - If TIM1 is enabled for PWM usage, you also need specifies the timer output - channel {1,..,4} - -if STM32F7_TIM1_CHANNEL = 1 - -config STM32F7_TIM1_CH1OUT - bool "TIM1 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -config STM32F7_TIM1_CH1NOUT - bool "TIM1 Channel 1 Complementary Output" - default n - ---help--- - Enables channel 1 Complementary Output. - -endif # STM32F7_TIM1_CHANNEL = 1 - -if STM32F7_TIM1_CHANNEL = 2 - -config STM32F7_TIM1_CH2OUT - bool "TIM1 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -config STM32F7_TIM1_CH2NOUT - bool "TIM1 Channel 2 Complementary Output" - default n - ---help--- - Enables channel 2 Complementary Output. - -endif # STM32F7_TIM1_CHANNEL = 2 - -if STM32F7_TIM1_CHANNEL = 3 - -config STM32F7_TIM1_CH3OUT - bool "TIM1 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -config STM32F7_TIM1_CH3NOUT - bool "TIM1 Channel 3 Complementary Output" - default n - ---help--- - Enables channel 3 Complementary Output. - -endif # STM32F7_TIM1_CHANNEL = 3 - -if STM32F7_TIM1_CHANNEL = 4 - -config STM32F7_TIM1_CH4OUT - bool "TIM1 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32F7_TIM1_CHANNEL = 4 - -config STM32F7_TIM1_CHMODE - int "TIM1 Channel Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32F7_PWM_MULTICHAN - -endif # STM32F7_TIM1_PWM - -config STM32F7_TIM2_PWM - bool "TIM2 PWM" - default n - depends on STM32F7_TIM2 - select STM32F7_PWM - ---help--- - Reserve timer 2 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32F7_TIM2 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32F7_TIM2_PWM - -config STM32F7_TIM2_MODE - int "TIM2 Mode" - default 0 - range 0 4 - ---help--- - Specifies the timer mode. - -if STM32F7_PWM_MULTICHAN - -config STM32F7_TIM2_CHANNEL1 - bool "TIM2 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32F7_TIM2_CHANNEL1 - -config STM32F7_TIM2_CH1MODE - int "TIM2 Channel 1 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32F7_TIM2_CH1OUT - bool "TIM2 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32F7_TIM2_CHANNEL1 - -config STM32F7_TIM2_CHANNEL2 - bool "TIM2 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32F7_TIM2_CHANNEL2 - -config STM32F7_TIM2_CH2MODE - int "TIM2 Channel 2 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32F7_TIM2_CH2OUT - bool "TIM2 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32F7_TIM2_CHANNEL2 - -config STM32F7_TIM2_CHANNEL3 - bool "TIM2 Channel 3" - default n - ---help--- - Enables channel 3. - -if STM32F7_TIM2_CHANNEL3 - -config STM32F7_TIM2_CH3MODE - int "TIM2 Channel 3 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32F7_TIM2_CH3OUT - bool "TIM2 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -endif # STM32F7_TIM2_CHANNEL3 - -config STM32F7_TIM2_CHANNEL4 - bool "TIM2 Channel 4" - default n - ---help--- - Enables channel 4. - -if STM32F7_TIM2_CHANNEL4 - -config STM32F7_TIM2_CH4MODE - int "TIM2 Channel 4 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32F7_TIM2_CH4OUT - bool "TIM2 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32F7_TIM2_CHANNEL4 - -endif # STM32F7_PWM_MULTICHAN - -if !STM32F7_PWM_MULTICHAN - -config STM32F7_TIM2_CHANNEL - int "TIM2 PWM Output Channel" - default 1 - range 1 4 - ---help--- - If TIM2 is enabled for PWM usage, you also need specifies the timer output - channel {1,..,4} - -if STM32F7_TIM2_CHANNEL = 1 - -config STM32F7_TIM2_CH1OUT - bool "TIM2 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32F7_TIM2_CHANNEL = 1 - -if STM32F7_TIM2_CHANNEL = 2 - -config STM32F7_TIM2_CH2OUT - bool "TIM2 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32F7_TIM2_CHANNEL = 2 - -if STM32F7_TIM2_CHANNEL = 3 - -config STM32F7_TIM2_CH3OUT - bool "TIM2 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -endif # STM32F7_TIM2_CHANNEL = 3 - -if STM32F7_TIM2_CHANNEL = 4 - -config STM32F7_TIM2_CH4OUT - bool "TIM2 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32F7_TIM2_CHANNEL = 4 - -config STM32F7_TIM2_CHMODE - int "TIM2 Channel Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32F7_PWM_MULTICHAN - -endif # STM32F7_TIM2_PWM - -config STM32F7_TIM3_PWM - bool "TIM3 PWM" - default n - depends on STM32F7_TIM3 - select STM32F7_PWM - ---help--- - Reserve timer 3 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32F7_TIM3 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32F7_TIM3_PWM - -config STM32F7_TIM3_MODE - int "TIM3 Mode" - default 0 - range 0 4 - ---help--- - Specifies the timer mode. - -if STM32F7_PWM_MULTICHAN - -config STM32F7_TIM3_CHANNEL1 - bool "TIM3 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32F7_TIM3_CHANNEL1 - -config STM32F7_TIM3_CH1MODE - int "TIM3 Channel 1 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32F7_TIM3_CH1OUT - bool "TIM3 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32F7_TIM3_CHANNEL1 - -config STM32F7_TIM3_CHANNEL2 - bool "TIM3 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32F7_TIM3_CHANNEL2 - -config STM32F7_TIM3_CH2MODE - int "TIM3 Channel 2 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32F7_TIM3_CH2OUT - bool "TIM3 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32F7_TIM3_CHANNEL2 - -config STM32F7_TIM3_CHANNEL3 - bool "TIM3 Channel 3" - default n - ---help--- - Enables channel 3. - -if STM32F7_TIM3_CHANNEL3 - -config STM32F7_TIM3_CH3MODE - int "TIM3 Channel 3 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32F7_TIM3_CH3OUT - bool "TIM3 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -endif # STM32F7_TIM3_CHANNEL3 - -config STM32F7_TIM3_CHANNEL4 - bool "TIM3 Channel 4" - default n - ---help--- - Enables channel 4. - -if STM32F7_TIM3_CHANNEL4 - -config STM32F7_TIM3_CH4MODE - int "TIM3 Channel 4 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32F7_TIM3_CH4OUT - bool "TIM3 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32F7_TIM3_CHANNEL4 - -endif # STM32F7_PWM_MULTICHAN - -if !STM32F7_PWM_MULTICHAN - -config STM32F7_TIM3_CHANNEL - int "TIM3 PWM Output Channel" - default 1 - range 1 4 - ---help--- - If TIM3 is enabled for PWM usage, you also need specifies the timer output - channel {1,..,4} - -if STM32F7_TIM3_CHANNEL = 1 - -config STM32F7_TIM3_CH1OUT - bool "TIM3 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32F7_TIM3_CHANNEL = 1 - -if STM32F7_TIM3_CHANNEL = 2 - -config STM32F7_TIM3_CH2OUT - bool "TIM3 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32F7_TIM3_CHANNEL = 2 - -if STM32F7_TIM3_CHANNEL = 3 - -config STM32F7_TIM3_CH3OUT - bool "TIM3 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -endif # STM32F7_TIM3_CHANNEL = 3 - -if STM32F7_TIM3_CHANNEL = 4 - -config STM32F7_TIM3_CH4OUT - bool "TIM3 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32F7_TIM3_CHANNEL = 4 - -config STM32F7_TIM3_CHMODE - int "TIM3 Channel Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32F7_PWM_MULTICHAN - -endif # STM32F7_TIM3_PWM - -config STM32F7_TIM4_PWM - bool "TIM4 PWM" - default n - depends on STM32F7_TIM4 - select STM32F7_PWM - ---help--- - Reserve timer 4 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32F7_TIM4 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32F7_TIM4_PWM - -config STM32F7_TIM4_MODE - int "TIM4 Mode" - default 0 - range 0 4 - ---help--- - Specifies the timer mode. - -if STM32F7_PWM_MULTICHAN - -config STM32F7_TIM4_CHANNEL1 - bool "TIM4 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32F7_TIM4_CHANNEL1 - -config STM32F7_TIM4_CH1MODE - int "TIM4 Channel 1 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32F7_TIM4_CH1OUT - bool "TIM4 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32F7_TIM4_CHANNEL1 - -config STM32F7_TIM4_CHANNEL2 - bool "TIM4 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32F7_TIM4_CHANNEL2 - -config STM32F7_TIM4_CH2MODE - int "TIM4 Channel 2 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32F7_TIM4_CH2OUT - bool "TIM4 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32F7_TIM4_CHANNEL2 - -config STM32F7_TIM4_CHANNEL3 - bool "TIM4 Channel 3" - default n - ---help--- - Enables channel 3. - -if STM32F7_TIM4_CHANNEL3 - -config STM32F7_TIM4_CH3MODE - int "TIM4 Channel 3 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32F7_TIM4_CH3OUT - bool "TIM4 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -endif # STM32F7_TIM4_CHANNEL3 - -config STM32F7_TIM4_CHANNEL4 - bool "TIM4 Channel 4" - default n - ---help--- - Enables channel 4. - -if STM32F7_TIM4_CHANNEL4 - -config STM32F7_TIM4_CH4MODE - int "TIM4 Channel 4 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32F7_TIM4_CH4OUT - bool "TIM4 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32F7_TIM4_CHANNEL4 - -endif # STM32F7_PWM_MULTICHAN - -if !STM32F7_PWM_MULTICHAN - -config STM32F7_TIM4_CHANNEL - int "TIM4 PWM Output Channel" - default 1 - range 1 4 - ---help--- - If TIM4 is enabled for PWM usage, you also need specifies the timer output - channel {1,..,4} - -if STM32F7_TIM4_CHANNEL = 1 - -config STM32F7_TIM4_CH1OUT - bool "TIM4 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32F7_TIM4_CHANNEL = 1 - -if STM32F7_TIM4_CHANNEL = 2 - -config STM32F7_TIM4_CH2OUT - bool "TIM4 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32F7_TIM4_CHANNEL = 2 - -if STM32F7_TIM4_CHANNEL = 3 - -config STM32F7_TIM4_CH3OUT - bool "TIM4 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -endif # STM32F7_TIM4_CHANNEL = 3 - -if STM32F7_TIM4_CHANNEL = 4 - -config STM32F7_TIM4_CH4OUT - bool "TIM4 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32F7_TIM4_CHANNEL = 4 - -config STM32F7_TIM4_CHMODE - int "TIM4 Channel Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32F7_PWM_MULTICHAN - -endif # STM32F7_TIM4_PWM - -config STM32F7_TIM5_PWM - bool "TIM5 PWM" - default n - depends on STM32F7_TIM5 - select STM32F7_PWM - ---help--- - Reserve timer 5 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32F7_TIM5 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32F7_TIM5_PWM - -config STM32F7_TIM5_MODE - int "TIM5 Mode" - default 0 - range 0 4 - ---help--- - Specifies the timer mode. - -if STM32F7_PWM_MULTICHAN - -config STM32F7_TIM5_CHANNEL1 - bool "TIM5 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32F7_TIM5_CHANNEL1 - -config STM32F7_TIM5_CH1MODE - int "TIM5 Channel 1 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32F7_TIM5_CH1OUT - bool "TIM5 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32F7_TIM5_CHANNEL1 - -config STM32F7_TIM5_CHANNEL2 - bool "TIM5 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32F7_TIM5_CHANNEL2 - -config STM32F7_TIM5_CH2MODE - int "TIM5 Channel 2 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32F7_TIM5_CH2OUT - bool "TIM5 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32F7_TIM5_CHANNEL2 - -config STM32F7_TIM5_CHANNEL3 - bool "TIM5 Channel 3" - default n - ---help--- - Enables channel 3. - -if STM32F7_TIM5_CHANNEL3 - -config STM32F7_TIM5_CH3MODE - int "TIM5 Channel 3 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32F7_TIM5_CH3OUT - bool "TIM5 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -endif # STM32F7_TIM5_CHANNEL3 - -config STM32F7_TIM5_CHANNEL4 - bool "TIM5 Channel 4" - default n - ---help--- - Enables channel 4. - -if STM32F7_TIM5_CHANNEL4 - -config STM32F7_TIM5_CH4MODE - int "TIM5 Channel 4 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32F7_TIM5_CH4OUT - bool "TIM5 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32F7_TIM5_CHANNEL4 - -endif # STM32F7_PWM_MULTICHAN - -if !STM32F7_PWM_MULTICHAN - -config STM32F7_TIM5_CHANNEL - int "TIM5 PWM Output Channel" - default 1 - range 1 4 - ---help--- - If TIM5 is enabled for PWM usage, you also need specifies the timer output - channel {1,..,4} - -if STM32F7_TIM5_CHANNEL = 1 - -config STM32F7_TIM5_CH1OUT - bool "TIM5 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32F7_TIM5_CHANNEL = 1 - -if STM32F7_TIM5_CHANNEL = 2 - -config STM32F7_TIM5_CH2OUT - bool "TIM5 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32F7_TIM5_CHANNEL = 2 - -if STM32F7_TIM5_CHANNEL = 3 - -config STM32F7_TIM5_CH3OUT - bool "TIM5 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -endif # STM32F7_TIM5_CHANNEL = 3 - -if STM32F7_TIM5_CHANNEL = 4 - -config STM32F7_TIM5_CH4OUT - bool "TIM5 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32F7_TIM5_CHANNEL = 4 - -config STM32F7_TIM5_CHMODE - int "TIM5 Channel Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32F7_PWM_MULTICHAN - -endif # STM32F7_TIM5_PWM - -config STM32F7_TIM8_PWM - bool "TIM8 PWM" - default n - depends on STM32F7_TIM8 - select STM32F7_PWM - ---help--- - Reserve timer 8 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32F7_TIM8 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32F7_TIM8_PWM - -config STM32F7_TIM8_MODE - int "TIM8 Mode" - default 0 - range 0 4 - ---help--- - Specifies the timer mode. - -config STM32F7_TIM8_LOCK - int "TIM8 Lock Level Configuration" - default 0 - range 0 3 - ---help--- - Timer 8 lock level configuration - -config STM32F7_TIM8_DEADTIME - int "TIM8 Initial Dead-time" - default 0 - range 0 255 - ---help--- - Timer 8 initial dead-time - -config STM32F7_TIM8_TDTS - int "TIM8 t_DTS Division" - default 0 - range 0 2 - ---help--- - Timer 8 dead-time and sampling clock (t_DTS) division - -if STM32F7_PWM_MULTICHAN - -config STM32F7_TIM8_CHANNEL1 - bool "TIM8 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32F7_TIM8_CHANNEL1 - -config STM32F7_TIM8_CH1MODE - int "TIM8 Channel 1 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32F7_TIM8_CH1OUT - bool "TIM8 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -config STM32F7_TIM8_CH1NOUT - bool "TIM8 Channel 1 Complementary Output" - default n - ---help--- - Enables channel 1 Complementary Output. - -endif # STM32F7_TIM8_CHANNEL1 - -config STM32F7_TIM8_CHANNEL2 - bool "TIM8 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32F7_TIM8_CHANNEL2 - -config STM32F7_TIM8_CH2MODE - int "TIM8 Channel 2 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32F7_TIM8_CH2OUT - bool "TIM8 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -config STM32F7_TIM8_CH2NOUT - bool "TIM8 Channel 2 Complementary Output" - default n - ---help--- - Enables channel 2 Complementary Output. - -endif # STM32F7_TIM8_CHANNEL2 - -config STM32F7_TIM8_CHANNEL3 - bool "TIM8 Channel 3" - default n - ---help--- - Enables channel 3. - -if STM32F7_TIM8_CHANNEL3 - -config STM32F7_TIM8_CH3MODE - int "TIM8 Channel 3 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32F7_TIM8_CH3OUT - bool "TIM8 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -config STM32F7_TIM8_CH3NOUT - bool "TIM8 Channel 3 Complementary Output" - default n - ---help--- - Enables channel 3 Complementary Output. - -endif # STM32F7_TIM8_CHANNEL3 - -config STM32F7_TIM8_CHANNEL4 - bool "TIM8 Channel 4" - default n - ---help--- - Enables channel 4. - -if STM32F7_TIM8_CHANNEL4 - -config STM32F7_TIM8_CH4MODE - int "TIM8 Channel 4 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32F7_TIM8_CH4OUT - bool "TIM8 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32F7_TIM8_CHANNEL4 - -config STM32F7_TIM8_CHANNEL5 - bool "TIM8 Channel 5 (internal)" - default n - ---help--- - Enables channel 5 (not available externally) - -if STM32F7_TIM8_CHANNEL5 - -config STM32F7_TIM8_CH5MODE - int "TIM8 Channel 5 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32F7_TIM8_CH5OUT - bool "TIM8 Channel 5 Output" - default n - ---help--- - Enables channel 5 output. - -endif # STM32F7_TIM8_CHANNEL5 - -config STM32F7_TIM8_CHANNEL6 - bool "TIM8 Channel 6 (internal)" - default n - ---help--- - Enables channel 6 (not available externally) - -if STM32F7_TIM8_CHANNEL6 - -config STM32F7_TIM8_CH6MODE - int "TIM8 Channel 6 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32F7_TIM8_CH6OUT - bool "TIM8 Channel 6 Output" - default n - ---help--- - Enables channel 6 output. - -endif # STM32F7_TIM8_CHANNEL6 - -endif # STM32F7_PWM_MULTICHAN - -if !STM32F7_PWM_MULTICHAN - -config STM32F7_TIM8_CHANNEL - int "TIM8 PWM Output Channel" - default 1 - range 1 4 - ---help--- - If TIM8 is enabled for PWM usage, you also need specifies the timer output - channel {1,..,4} - -if STM32F7_TIM8_CHANNEL = 1 - -config STM32F7_TIM8_CH1OUT - bool "TIM8 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -config STM32F7_TIM8_CH1NOUT - bool "TIM8 Channel 1 Complementary Output" - default n - ---help--- - Enables channel 1 Complementary Output. - -endif # STM32F7_TIM8_CHANNEL = 1 - -if STM32F7_TIM8_CHANNEL = 2 - -config STM32F7_TIM8_CH2OUT - bool "TIM8 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -config STM32F7_TIM8_CH2NOUT - bool "TIM8 Channel 2 Complementary Output" - default n - ---help--- - Enables channel 2 Complementary Output. - -endif # STM32F7_TIM8_CHANNEL = 2 - -if STM32F7_TIM8_CHANNEL = 3 - -config STM32F7_TIM8_CH3OUT - bool "TIM8 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -config STM32F7_TIM8_CH3NOUT - bool "TIM8 Channel 3 Complementary Output" - default n - ---help--- - Enables channel 3 Complementary Output. - -endif # STM32F7_TIM8_CHANNEL = 3 - -if STM32F7_TIM8_CHANNEL = 4 - -config STM32F7_TIM8_CH4OUT - bool "TIM8 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32F7_TIM8_CHANNEL = 4 - -config STM32F7_TIM8_CHMODE - int "TIM8 Channel Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32F7_PWM_MULTICHAN - -endif # STM32F7_TIM8_PWM - -config STM32F7_TIM9_PWM - bool "TIM9 PWM" - default n - depends on STM32F7_TIM9 - select STM32F7_PWM - ---help--- - Reserve timer 9 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32F7_TIM9 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32F7_TIM9_PWM - -if STM32F7_PWM_MULTICHAN - -config STM32F7_TIM9_CHANNEL1 - bool "TIM9 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32F7_TIM9_CHANNEL1 - -config STM32F7_TIM9_CH1MODE - int "TIM9 Channel 1 Mode" - default 6 - range 0 9 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32F7_TIM9_CH1OUT - bool "TIM9 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32F7_TIM9_CHANNEL1 - -config STM32F7_TIM9_CHANNEL2 - bool "TIM9 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32F7_TIM9_CHANNEL2 - -config STM32F7_TIM9_CH2MODE - int "TIM9 Channel 2 Mode" - default 6 - range 0 9 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32F7_TIM9_CH2OUT - bool "TIM9 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32F7_TIM9_CHANNEL2 - -endif # STM32F7_PWM_MULTICHAN - -if !STM32F7_PWM_MULTICHAN - -config STM32F7_TIM9_CHANNEL - int "TIM9 PWM Output Channel" - default 1 - range 1 2 - ---help--- - If TIM9 is enabled for PWM usage, you also need specifies the timer output - channel {1,2} - -if STM32F7_TIM9_CHANNEL = 1 - -config STM32F7_TIM9_CH1OUT - bool "TIM9 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32F7_TIM9_CHANNEL = 1 - -if STM32F7_TIM9_CHANNEL = 2 - -config STM32F7_TIM9_CH2OUT - bool "TIM9 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32F7_TIM9_CHANNEL = 2 - -config STM32F7_TIM9_CHMODE - int "TIM9 Channel Mode" - default 6 - range 0 9 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32F7_PWM_MULTICHAN - -endif # STM32F7_TIM9_PWM - -config STM32F7_TIM10_PWM - bool "TIM10 PWM" - default n - depends on STM32F7_TIM10 - select STM32F7_PWM - ---help--- - Reserve timer 10 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32F7_TIM10 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32F7_TIM10_PWM - -if STM32F7_PWM_MULTICHAN - -config STM32F7_TIM10_CHANNEL1 - bool "TIM10 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32F7_TIM10_CHANNEL1 - -config STM32F7_TIM10_CH1MODE - int "TIM10 Channel 1 Mode" - default 6 - range 0 7 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32F7_TIM10_CH1OUT - bool "TIM10 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32F7_TIM10_CHANNEL1 - -endif # STM32F7_PWM_MULTICHAN - -if !STM32F7_PWM_MULTICHAN - -config STM32F7_TIM10_CHANNEL - int "TIM10 PWM Output Channel" - default 1 - range 1 1 - ---help--- - If TIM10 is enabled for PWM usage, you also need specifies the timer output - channel {1} - -if STM32F7_TIM10_CHANNEL = 1 - -config STM32F7_TIM10_CH1OUT - bool "TIM10 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32F7_TIM10_CHANNEL = 1 - -config STM32F7_TIM10_CHMODE - int "TIM10 Channel Mode" - default 6 - range 0 7 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32F7_PWM_MULTICHAN - -endif # STM32F7_TIM10_PWM - -config STM32F7_TIM11_PWM - bool "TIM11 PWM" - default n - depends on STM32F7_TIM11 - select STM32F7_PWM - ---help--- - Reserve timer 11 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32F7_TIM11 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32F7_TIM11_PWM - -if STM32F7_PWM_MULTICHAN - -config STM32F7_TIM11_CHANNEL1 - bool "TIM11 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32F7_TIM11_CHANNEL1 - -config STM32F7_TIM11_CH1MODE - int "TIM11 Channel 1 Mode" - default 6 - range 0 7 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32F7_TIM11_CH1OUT - bool "TIM11 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32F7_TIM11_CHANNEL1 - -endif # STM32F7_PWM_MULTICHAN - -if !STM32F7_PWM_MULTICHAN - -config STM32F7_TIM11_CHANNEL - int "TIM11 PWM Output Channel" - default 1 - range 1 1 - ---help--- - If TIM11 is enabled for PWM usage, you also need specifies the timer output - channel {1} - -if STM32F7_TIM11_CHANNEL = 1 - -config STM32F7_TIM11_CH1OUT - bool "TIM11 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32F7_TIM11_CHANNEL = 1 - -config STM32F7_TIM11_CHMODE - int "TIM11 Channel Mode" - default 6 - range 0 7 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32F7_PWM_MULTICHAN - -endif # STM32F7_TIM11_PWM - -config STM32F7_TIM12_PWM - bool "TIM12 PWM" - default n - depends on STM32F7_TIM12 - select STM32F7_PWM - ---help--- - Reserve timer 12 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32F7_TIM12 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32F7_TIM12_PWM - -if STM32F7_PWM_MULTICHAN - -config STM32F7_TIM12_CHANNEL1 - bool "TIM12 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32F7_TIM12_CHANNEL1 - -config STM32F7_TIM12_CH1MODE - int "TIM12 Channel 1 Mode" - default 6 - range 0 9 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32F7_TIM12_CH1OUT - bool "TIM12 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32F7_TIM12_CHANNEL1 - -config STM32F7_TIM12_CHANNEL2 - bool "TIM12 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32F7_TIM12_CHANNEL2 - -config STM32F7_TIM12_CH2MODE - int "TIM12 Channel 2 Mode" - default 6 - range 0 9 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32F7_TIM12_CH2OUT - bool "TIM12 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32F7_TIM12_CHANNEL2 - -endif # STM32F7_PWM_MULTICHAN - -if !STM32F7_PWM_MULTICHAN - -config STM32F7_TIM12_CHANNEL - int "TIM12 PWM Output Channel" - default 1 - range 1 2 - ---help--- - If TIM12 is enabled for PWM usage, you also need specifies the timer output - channel {1,2} - -if STM32F7_TIM12_CHANNEL = 1 - -config STM32F7_TIM12_CH1OUT - bool "TIM12 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32F7_TIM12_CHANNEL = 1 - -if STM32F7_TIM12_CHANNEL = 2 - -config STM32F7_TIM12_CH2OUT - bool "TIM12 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32F7_TIM12_CHANNEL = 2 - -config STM32F7_TIM12_CHMODE - int "TIM12 Channel Mode" - default 6 - range 0 9 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32F7_PWM_MULTICHAN - -endif # STM32F7_TIM12_PWM - -config STM32F7_TIM13_PWM - bool "TIM13 PWM" - default n - depends on STM32F7_TIM13 - select STM32F7_PWM - ---help--- - Reserve timer 13 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32F7_TIM13 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32F7_TIM13_PWM - -if STM32F7_PWM_MULTICHAN - -config STM32F7_TIM13_CHANNEL1 - bool "TIM13 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32F7_TIM13_CHANNEL1 - -config STM32F7_TIM13_CH1MODE - int "TIM13 Channel 1 Mode" - default 6 - range 0 7 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32F7_TIM13_CH1OUT - bool "TIM13 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32F7_TIM13_CHANNEL1 - -endif # STM32F7_PWM_MULTICHAN - -if !STM32F7_PWM_MULTICHAN - -config STM32F7_TIM13_CHANNEL - int "TIM13 PWM Output Channel" - default 1 - range 1 1 - ---help--- - If TIM13 is enabled for PWM usage, you also need specifies the timer output - channel {1} - -if STM32F7_TIM13_CHANNEL = 1 - -config STM32F7_TIM13_CH1OUT - bool "TIM13 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32F7_TIM13_CHANNEL = 1 - -config STM32F7_TIM13_CHMODE - int "TIM13 Channel Mode" - default 6 - range 0 7 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32F7_PWM_MULTICHAN - -endif # STM32F7_TIM13_PWM - -config STM32F7_TIM14_PWM - bool "TIM14 PWM" - default n - depends on STM32F7_TIM14 - select STM32F7_PWM - ---help--- - Reserve timer 14 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32F7_TIM14 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32F7_TIM14_PWM - -if STM32F7_PWM_MULTICHAN - -config STM32F7_TIM14_CHANNEL1 - bool "TIM14 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32F7_TIM14_CHANNEL1 - -config STM32F7_TIM14_CH1MODE - int "TIM14 Channel 1 Mode" - default 6 - range 0 7 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32F7_TIM14_CH1OUT - bool "TIM14 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32F7_TIM14_CHANNEL1 - -endif # STM32F7_PWM_MULTICHAN - -if !STM32F7_PWM_MULTICHAN - -config STM32F7_TIM14_CHANNEL - int "TIM14 PWM Output Channel" - default 1 - range 1 1 - ---help--- - If TIM14 is enabled for PWM usage, you also need specifies the timer output - channel {1} - -if STM32F7_TIM14_CHANNEL = 1 - -config STM32F7_TIM14_CH1OUT - bool "TIM14 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32F7_TIM14_CHANNEL = 1 - -config STM32F7_TIM14_CHMODE - int "TIM14 Channel Mode" - default 6 - range 0 7 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32F7_PWM_MULTICHAN - -endif # STM32F7_TIM14_PWM - -config STM32F7_PWM_MULTICHAN - bool "PWM Multiple Output Channels" - default n - depends on STM32F7_PWM - ---help--- - Specifies that the PWM driver supports multiple output - channels per timer. - -config STM32F7_PWM_TRGO - bool "TIM PWM TRGO support" - default n - depends on STM32F7_PWM - ---help--- - Enable TRGO support for PWM driver - -config STM32F7_PULSECOUNT - bool - default n - select ARCH_HAVE_PULSECOUNT - select PULSECOUNT - -config STM32F7_TIM1_PULSECOUNT - bool "TIM1 pulse count" - default n - depends on STM32F7_TIM1 - select STM32F7_PULSECOUNT - ---help--- - Reserve timer 1 for pulse count output. - -if STM32F7_TIM1_PULSECOUNT - -config STM32F7_TIM1_PULSECOUNT_TDTS - int "TIM1 pulse count clock division" - default 0 - range 0 2 - -config STM32F7_TIM1_PULSECOUNT_CHANNEL - int "TIM1 pulse count channel" - default 1 - range 1 4 - ---help--- - Specifies the timer channel {1,..,4}. - -config STM32F7_TIM1_PULSECOUNT_POL - int "TIM1 pulse count output polarity" - default 0 - range 0 1 - -config STM32F7_TIM1_PULSECOUNT_IDLE - int "TIM1 pulse count idle state" - default 0 - range 0 1 - -endif # STM32F7_TIM1_PULSECOUNT - -config STM32F7_TIM8_PULSECOUNT - bool "TIM8 pulse count" - default n - depends on STM32F7_TIM8 - select STM32F7_PULSECOUNT - ---help--- - Reserve timer 8 for pulse count output. - -if STM32F7_TIM8_PULSECOUNT - -config STM32F7_TIM8_PULSECOUNT_TDTS - int "TIM8 pulse count clock division" - default 0 - range 0 2 - -config STM32F7_TIM8_PULSECOUNT_CHANNEL - int "TIM8 pulse count channel" - default 1 - range 1 4 - ---help--- - Specifies the timer channel {1,..,4}. - -config STM32F7_TIM8_PULSECOUNT_POL - int "TIM8 pulse count output polarity" - default 0 - range 0 1 - -config STM32F7_TIM8_PULSECOUNT_IDLE - int "TIM8 pulse count idle state" - default 0 - range 0 1 - -endif # STM32F7_TIM8_PULSECOUNT -config STM32F7_TIM1_ADC - bool "TIM1 ADC" - default n - depends on STM32F7_TIM1 && STM32F7_ADC - ---help--- - Reserve timer 1 for use by ADC - - Timer devices may be used for different purposes. If STM32F7_TIM1 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - -choice - prompt "Select TIM1 ADC channel" - default STM32F7_TIM1_ADC1 - depends on STM32F7_TIM1_ADC - -config STM32F7_TIM1_ADC1 - bool "TIM1 ADC channel 1" - depends on STM32F7_ADC1 - select STM32F7_HAVE_ADC1_TIMER - ---help--- - Reserve TIM1 to trigger ADC1 - -config STM32F7_TIM1_ADC2 - bool "TIM1 ADC channel 2" - depends on STM32F7_ADC2 - select STM32F7_HAVE_ADC2_TIMER - ---help--- - Reserve TIM1 to trigger ADC2 - -config STM32F7_TIM1_ADC3 - bool "TIM1 ADC channel 3" - depends on STM32F7_ADC3 - select STM32F7_HAVE_ADC3_TIMER - ---help--- - Reserve TIM1 to trigger ADC3 - -endchoice - -config STM32F7_TIM2_ADC - bool "TIM2 ADC" - default n - depends on STM32F7_TIM2 && STM32F7_ADC - ---help--- - Reserve timer 1 for use by ADC - - Timer devices may be used for different purposes. If STM32F7_TIM2 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - -choice - prompt "Select TIM2 ADC channel" - default STM32F7_TIM2_ADC1 - depends on STM32F7_TIM2_ADC - -config STM32F7_TIM2_ADC1 - bool "TIM2 ADC channel 1" - depends on STM32F7_ADC1 - select STM32F7_HAVE_ADC1_TIMER - ---help--- - Reserve TIM2 to trigger ADC1 - -config STM32F7_TIM2_ADC2 - bool "TIM2 ADC channel 2" - depends on STM32F7_ADC2 - select STM32F7_HAVE_ADC2_TIMER - ---help--- - Reserve TIM2 to trigger ADC2 - -config STM32F7_TIM2_ADC3 - bool "TIM2 ADC channel 3" - depends on STM32F7_ADC3 - select STM32F7_HAVE_ADC3_TIMER - ---help--- - Reserve TIM2 to trigger ADC3 - -endchoice - -config STM32F7_TIM3_ADC - bool "TIM3 ADC" - default n - depends on STM32F7_TIM3 && STM32F7_ADC - ---help--- - Reserve timer 1 for use by ADC - - Timer devices may be used for different purposes. If STM32F7_TIM3 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - -choice - prompt "Select TIM3 ADC channel" - default STM32F7_TIM3_ADC1 - depends on STM32F7_TIM3_ADC - -config STM32F7_TIM3_ADC1 - bool "TIM3 ADC channel 1" - depends on STM32F7_ADC1 - select STM32F7_HAVE_ADC1_TIMER - ---help--- - Reserve TIM3 to trigger ADC1 - -config STM32F7_TIM3_ADC2 - bool "TIM3 ADC channel 2" - depends on STM32F7_ADC2 - select STM32F7_HAVE_ADC2_TIMER - ---help--- - Reserve TIM3 to trigger ADC2 - -config STM32F7_TIM3_ADC3 - bool "TIM3 ADC channel 3" - depends on STM32F7_ADC3 - select STM32F7_HAVE_ADC3_TIMER - ---help--- - Reserve TIM3 to trigger ADC3 - -endchoice - -config STM32F7_TIM4_ADC - bool "TIM4 ADC" - default n - depends on STM32F7_TIM4 && STM32F7_ADC - ---help--- - Reserve timer 1 for use by ADC - - Timer devices may be used for different purposes. If STM32F7_TIM4 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - -choice - prompt "Select TIM4 ADC channel" - default STM32F7_TIM4_ADC1 - depends on STM32F7_TIM4_ADC - -config STM32F7_TIM4_ADC1 - bool "TIM4 ADC channel 1" - depends on STM32F7_ADC1 - select STM32F7_HAVE_ADC1_TIMER - ---help--- - Reserve TIM4 to trigger ADC1 - -config STM32F7_TIM4_ADC2 - bool "TIM4 ADC channel 2" - depends on STM32F7_ADC2 - select STM32F7_HAVE_ADC2_TIMER - ---help--- - Reserve TIM4 to trigger ADC2 - -config STM32F7_TIM4_ADC3 - bool "TIM4 ADC channel 3" - depends on STM32F7_ADC3 - select STM32F7_HAVE_ADC3_TIMER - ---help--- - Reserve TIM4 to trigger ADC3 - -endchoice - -config STM32F7_TIM5_ADC - bool "TIM5 ADC" - default n - depends on STM32F7_TIM5 && STM32F7_ADC - ---help--- - Reserve timer 1 for use by ADC - - Timer devices may be used for different purposes. If STM32F7_TIM5 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - -choice - prompt "Select TIM5 ADC channel" - default STM32F7_TIM5_ADC1 - depends on STM32F7_TIM5_ADC - -config STM32F7_TIM5_ADC1 - bool "TIM5 ADC channel 1" - depends on STM32F7_ADC1 - select STM32F7_HAVE_ADC1_TIMER - ---help--- - Reserve TIM5 to trigger ADC1 - -config STM32F7_TIM5_ADC2 - bool "TIM5 ADC channel 2" - depends on STM32F7_ADC2 - select STM32F7_HAVE_ADC2_TIMER - ---help--- - Reserve TIM5 to trigger ADC2 - -config STM32F7_TIM5_ADC3 - bool "TIM5 ADC channel 3" - depends on STM32F7_ADC3 - select STM32F7_HAVE_ADC3_TIMER - ---help--- - Reserve TIM5 to trigger ADC3 - -endchoice - -config STM32F7_TIM8_ADC - bool "TIM8 ADC" - default n - depends on STM32F7_TIM8 && STM32F7_ADC - ---help--- - Reserve timer 1 for use by ADC - - Timer devices may be used for different purposes. If STM32F7_TIM8 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - -choice - prompt "Select TIM8 ADC channel" - default STM32F7_TIM8_ADC1 - depends on STM32F7_TIM8_ADC - -config STM32F7_TIM8_ADC1 - bool "TIM8 ADC channel 1" - depends on STM32F7_ADC1 - select STM32F7_HAVE_ADC1_TIMER - ---help--- - Reserve TIM8 to trigger ADC1 - -config STM32F7_TIM8_ADC2 - bool "TIM8 ADC channel 2" - depends on STM32F7_ADC2 - select STM32F7_HAVE_ADC2_TIMER - ---help--- - Reserve TIM8 to trigger ADC2 - -config STM32F7_TIM8_ADC3 - bool "TIM8 ADC channel 3" - depends on STM32F7_ADC3 - select STM32F7_HAVE_ADC3_TIMER - ---help--- - Reserve TIM8 to trigger ADC3 - -endchoice - -config STM32F7_HAVE_ADC1_TIMER - bool - -config STM32F7_HAVE_ADC2_TIMER - bool - -config STM32F7_HAVE_ADC3_TIMER - bool - -config STM32F7_ADC1_SAMPLE_FREQUENCY - int "ADC1 Sampling Frequency" - default 100 - depends on STM32F7_HAVE_ADC1_TIMER - ---help--- - ADC1 sampling frequency. Default: 100Hz - -config STM32F7_ADC1_TIMTRIG - int "ADC1 Timer Trigger" - default 0 - range 0 5 - depends on STM32F7_HAVE_ADC1_TIMER - ---help--- - Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO 5:TRGO2 - -config STM32F7_ADC2_SAMPLE_FREQUENCY - int "ADC2 Sampling Frequency" - default 100 - depends on STM32F7_HAVE_ADC2_TIMER - ---help--- - ADC2 sampling frequency. Default: 100Hz - -config STM32F7_ADC2_TIMTRIG - int "ADC2 Timer Trigger" - default 0 - range 0 5 - depends on STM32F7_HAVE_ADC2_TIMER - ---help--- - Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO 5:TRGO2 - -config STM32F7_ADC3_SAMPLE_FREQUENCY - int "ADC3 Sampling Frequency" - default 100 - depends on STM32F7_HAVE_ADC3_TIMER - ---help--- - ADC3 sampling frequency. Default: 100Hz - -config STM32F7_ADC3_TIMTRIG - int "ADC3 Timer Trigger" - default 0 - range 0 5 - depends on STM32F7_HAVE_ADC3_TIMER - ---help--- - Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO 5:TRGO2 - -config STM32F7_TIM1_DAC - bool "TIM1 DAC" - default n - depends on STM32F7_TIM1 && STM32F7_DAC - ---help--- - Reserve timer 1 for use by DAC - - Timer devices may be used for different purposes. If STM32F7_TIM1 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -choice - prompt "Select TIM1 DAC channel" - default STM32F7_TIM1_DAC1 - depends on STM32F7_TIM1_DAC - -config STM32F7_TIM1_DAC1 - bool "TIM1 DAC channel 1" - ---help--- - Reserve TIM1 to trigger DAC1 - -config STM32F7_TIM1_DAC2 - bool "TIM1 DAC channel 2" - ---help--- - Reserve TIM1 to trigger DAC2 - -endchoice - -config STM32F7_TIM2_DAC - bool "TIM2 DAC" - default n - depends on STM32F7_TIM2 && STM32F7_DAC - ---help--- - Reserve timer 2 for use by DAC - - Timer devices may be used for different purposes. If STM32F7_TIM2 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -choice - prompt "Select TIM2 DAC channel" - default STM32F7_TIM2_DAC1 - depends on STM32F7_TIM2_DAC - -config STM32F7_TIM2_DAC1 - bool "TIM2 DAC channel 1" - ---help--- - Reserve TIM2 to trigger DAC1 - -config STM32F7_TIM2_DAC2 - bool "TIM2 DAC channel 2" - ---help--- - Reserve TIM2 to trigger DAC2 - -endchoice - -config STM32F7_TIM3_DAC - bool "TIM3 DAC" - default n - depends on STM32F7_TIM3 && STM32F7_DAC - ---help--- - Reserve timer 3 for use by DAC - - Timer devices may be used for different purposes. If STM32F7_TIM3 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -choice - prompt "Select TIM3 DAC channel" - default STM32F7_TIM3_DAC1 - depends on STM32F7_TIM3_DAC - -config STM32F7_TIM3_DAC1 - bool "TIM3 DAC channel 1" - ---help--- - Reserve TIM3 to trigger DAC1 - -config STM32F7_TIM3_DAC2 - bool "TIM3 DAC channel 2" - ---help--- - Reserve TIM3 to trigger DAC2 - -endchoice - -config STM32F7_TIM4_DAC - bool "TIM4 DAC" - default n - depends on STM32F7_TIM4 && STM32F7_DAC - ---help--- - Reserve timer 4 for use by DAC - - Timer devices may be used for different purposes. If STM32F7_TIM4 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -choice - prompt "Select TIM4 DAC channel" - default STM32F7_TIM4_DAC1 - depends on STM32F7_TIM4_DAC - -config STM32F7_TIM4_DAC1 - bool "TIM4 DAC channel 1" - ---help--- - Reserve TIM4 to trigger DAC1 - -config STM32F7_TIM4_DAC2 - bool "TIM4 DAC channel 2" - ---help--- - Reserve TIM4 to trigger DAC2 - -endchoice - -config STM32F7_TIM5_DAC - bool "TIM5 DAC" - default n - depends on STM32F7_TIM5 && STM32F7_DAC - ---help--- - Reserve timer 5 for use by DAC - - Timer devices may be used for different purposes. If STM32F7_TIM5 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -choice - prompt "Select TIM5 DAC channel" - default STM32F7_TIM5_DAC1 - depends on STM32F7_TIM5_DAC - -config STM32F7_TIM5_DAC1 - bool "TIM5 DAC channel 1" - ---help--- - Reserve TIM5 to trigger DAC1 - -config STM32F7_TIM5_DAC2 - bool "TIM5 DAC channel 2" - ---help--- - Reserve TIM5 to trigger DAC2 - -endchoice - -config STM32F7_TIM6_DAC - bool "TIM6 DAC" - default n - depends on STM32F7_TIM6 && STM32F7_DAC - ---help--- - Reserve timer 6 for use by DAC - - Timer devices may be used for different purposes. If STM32F7_TIM6 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -choice - prompt "Select TIM6 DAC channel" - default STM32F7_TIM6_DAC1 - depends on STM32F7_TIM6_DAC - -config STM32F7_TIM6_DAC1 - bool "TIM6 DAC channel 1" - ---help--- - Reserve TIM6 to trigger DAC1 - -config STM32F7_TIM6_DAC2 - bool "TIM6 DAC channel 2" - ---help--- - Reserve TIM6 to trigger DAC2 - -endchoice - -config STM32F7_TIM7_DAC - bool "TIM7 DAC" - default n - depends on STM32F7_TIM7 && STM32F7_DAC - ---help--- - Reserve timer 7 for use by DAC - - Timer devices may be used for different purposes. If STM32F7_TIM7 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -choice - prompt "Select TIM7 DAC channel" - default STM32F7_TIM7_DAC1 - depends on STM32F7_TIM7_DAC - -config STM32F7_TIM7_DAC1 - bool "TIM7 DAC channel 1" - ---help--- - Reserve TIM7 to trigger DAC1 - -config STM32F7_TIM7_DAC2 - bool "TIM7 DAC channel 2" - ---help--- - Reserve TIM7 to trigger DAC2 - -endchoice - -config STM32F7_TIM8_DAC - bool "TIM8 DAC" - default n - depends on STM32F7_TIM8 && STM32F7_DAC - ---help--- - Reserve timer 8 for use by DAC - - Timer devices may be used for different purposes. If STM32F7_TIM8 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -choice - prompt "Select TIM8 DAC channel" - default STM32F7_TIM8_DAC1 - depends on STM32F7_TIM8_DAC - -config STM32F7_TIM8_DAC1 - bool "TIM8 DAC channel 1" - ---help--- - Reserve TIM8 to trigger DAC1 - -config STM32F7_TIM8_DAC2 - bool "TIM8 DAC channel 2" - ---help--- - Reserve TIM8 to trigger DAC2 - -endchoice - -config STM32F7_TIM9_DAC - bool "TIM9 DAC" - default n - depends on STM32F7_TIM9 && STM32F7_DAC - ---help--- - Reserve timer 9 for use by DAC - - Timer devices may be used for different purposes. If STM32F7_TIM9 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -choice - prompt "Select TIM9 DAC channel" - default STM32F7_TIM9_DAC1 - depends on STM32F7_TIM9_DAC - -config STM32F7_TIM9_DAC1 - bool "TIM9 DAC channel 1" - ---help--- - Reserve TIM9 to trigger DAC1 - -config STM32F7_TIM9_DAC2 - bool "TIM9 DAC channel 2" - ---help--- - Reserve TIM9 to trigger DAC2 - -endchoice - -config STM32F7_TIM10_DAC - bool "TIM10 DAC" - default n - depends on STM32F7_TIM10 && STM32F7_DAC - ---help--- - Reserve timer 10 for use by DAC - - Timer devices may be used for different purposes. If STM32F7_TIM10 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -choice - prompt "Select TIM10 DAC channel" - default STM32F7_TIM10_DAC1 - depends on STM32F7_TIM10_DAC - -config STM32F7_TIM10_DAC1 - bool "TIM10 DAC channel 1" - ---help--- - Reserve TIM10 to trigger DAC1 - -config STM32F7_TIM10_DAC2 - bool "TIM10 DAC channel 2" - ---help--- - Reserve TIM10 to trigger DAC2 - -endchoice - -config STM32F7_TIM11_DAC - bool "TIM11 DAC" - default n - depends on STM32F7_TIM11 && STM32F7_DAC - ---help--- - Reserve timer 11 for use by DAC - - Timer devices may be used for different purposes. If STM32F7_TIM11 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -choice - prompt "Select TIM11 DAC channel" - default STM32F7_TIM11_DAC1 - depends on STM32F7_TIM11_DAC - -config STM32F7_TIM11_DAC1 - bool "TIM11 DAC channel 1" - ---help--- - Reserve TIM11 to trigger DAC1 - -config STM32F7_TIM11_DAC2 - bool "TIM11 DAC channel 2" - ---help--- - Reserve TIM11 to trigger DAC2 - -endchoice - -config STM32F7_TIM12_DAC - bool "TIM12 DAC" - default n - depends on STM32F7_TIM12 && STM32F7_DAC - ---help--- - Reserve timer 12 for use by DAC - - Timer devices may be used for different purposes. If STM32F7_TIM12 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -choice - prompt "Select TIM12 DAC channel" - default STM32F7_TIM12_DAC1 - depends on STM32F7_TIM12_DAC - -config STM32F7_TIM12_DAC1 - bool "TIM12 DAC channel 1" - ---help--- - Reserve TIM12 to trigger DAC1 - -config STM32F7_TIM12_DAC2 - bool "TIM12 DAC channel 2" - ---help--- - Reserve TIM12 to trigger DAC2 - -endchoice - -config STM32F7_TIM13_DAC - bool "TIM13 DAC" - default n - depends on STM32F7_TIM13 && STM32F7_DAC - ---help--- - Reserve timer 13 for use by DAC - - Timer devices may be used for different purposes. If STM32F7_TIM13 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -choice - prompt "Select TIM13 DAC channel" - default STM32F7_TIM13_DAC1 - depends on STM32F7_TIM13_DAC - -config STM32F7_TIM13_DAC1 - bool "TIM13 DAC channel 1" - ---help--- - Reserve TIM13 to trigger DAC1 - -config STM32F7_TIM13_DAC2 - bool "TIM13 DAC channel 2" - ---help--- - Reserve TIM13 to trigger DAC2 - -endchoice - -config STM32F7_TIM14_DAC - bool "TIM14 DAC" - default n - depends on STM32F7_TIM14 && STM32F7_DAC - ---help--- - Reserve timer 14 for use by DAC - - Timer devices may be used for different purposes. If STM32F7_TIM14 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -choice - prompt "Select TIM14 DAC channel" - default STM32F7_TIM14_DAC1 - depends on STM32F7_TIM14_DAC - -config STM32F7_TIM14_DAC1 - bool "TIM14 DAC channel 1" - ---help--- - Reserve TIM14 to trigger DAC1 - -config STM32F7_TIM14_DAC2 - bool "TIM14 DAC channel 2" - ---help--- - Reserve TIM14 to trigger DAC2 - -endchoice - -config STM32F7_TIM1_CAP - bool "TIM1 Capture" - default n - depends on STM32F7_TIM1 - ---help--- - Reserve timer 1 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -config STM32F7_TIM2_CAP - bool "TIM2 Capture" - default n - depends on STM32F7_TIM2 - ---help--- - Reserve timer 2 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -config STM32F7_TIM3_CAP - bool "TIM3 Capture" - default n - depends on STM32F7_TIM3 - ---help--- - Reserve timer 3 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -config STM32F7_TIM4_CAP - bool "TIM4 Capture" - default n - depends on STM32F7_TIM4 - ---help--- - Reserve timer 4 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -config STM32F7_TIM5_CAP - bool "TIM5 Capture" - default n - depends on STM32F7_TIM5 - ---help--- - Reserve timer 5 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -config STM32F7_TIM8_CAP - bool "TIM8 Capture" - default n - depends on STM32F7_TIM8 - ---help--- - Reserve timer 8 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -config STM32F7_TIM9_CAP - bool "TIM9 Capture" - default n - depends on STM32F7_TIM9 - ---help--- - Reserve timer 9 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -config STM32F7_TIM10_CAP - bool "TIM10 Capture" - default n - depends on STM32F7_TIM10 - ---help--- - Reserve timer 10 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -config STM32F7_TIM11_CAP - bool "TIM11 Capture" - default n - depends on STM32F7_TIM11 - ---help--- - Reserve timer 11 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -config STM32F7_TIM12_CAP - bool "TIM12 Capture" - default n - depends on STM32F7_TIM12 - ---help--- - Reserve timer 12 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -config STM32F7_TIM13_CAP - bool "TIM13 Capture" - default n - depends on STM32F7_TIM13 - ---help--- - Reserve timer 13 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -config STM32F7_TIM14_CAP - bool "TIM14 Capture" - default n - depends on STM32F7_TIM14 - ---help--- - Reserve timer 14 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -menu "STM32 TIMx Outputs Configuration" - -config STM32F7_TIM1_CH1POL - int "TIM1 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32F7_TIM1_CH1OUT - ---help--- - TIM1 Channel 1 output polarity - -config STM32F7_TIM1_CH1IDLE - int "TIM1 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32F7_TIM1_CH1OUT - ---help--- - TIM1 Channel 1 output IDLE - -config STM32F7_TIM1_CH1NPOL - int "TIM1 Channel 1 Complementary Output polarity" - default 0 - range 0 1 - depends on STM32F7_TIM1_CH1NOUT - ---help--- - TIM1 Channel 1 Complementary Output polarity - -config STM32F7_TIM1_CH1NIDLE - int "TIM1 Channel 1 Complementary Output IDLE" - default 0 - range 0 1 - depends on STM32F7_TIM1_CH1NOUT - ---help--- - TIM1 Channel 1 Complementary Output IDLE - -config STM32F7_TIM1_CH2POL - int "TIM1 Channel 2 Output polarity" - default 0 - range 0 1 - depends on STM32F7_TIM1_CH2OUT - ---help--- - TIM1 Channel 2 output polarity - -config STM32F7_TIM1_CH2IDLE - int "TIM1 Channel 2 Output IDLE" - default 0 - range 0 1 - depends on STM32F7_TIM1_CH2OUT - ---help--- - TIM1 Channel 2 output IDLE - -config STM32F7_TIM1_CH2NPOL - int "TIM1 Channel 2 Complementary Output polarity" - default 0 - range 0 1 - depends on STM32F7_TIM1_CH2NOUT - ---help--- - TIM1 Channel 2 Complementary Output polarity - -config STM32F7_TIM1_CH2NIDLE - int "TIM1 Channel 2 Complementary Output IDLE" - default 0 - range 0 1 - depends on STM32F7_TIM1_CH2NOUT - ---help--- - TIM1 Channel 2 Complementary Output IDLE - -config STM32F7_TIM1_CH3POL - int "TIM1 Channel 3 Output polarity" - default 0 - range 0 1 - depends on STM32F7_TIM1_CH3OUT - ---help--- - TIM1 Channel 3 output polarity - -config STM32F7_TIM1_CH3IDLE - int "TIM1 Channel 3 Output IDLE" - default 0 - range 0 1 - depends on STM32F7_TIM1_CH3OUT - ---help--- - TIM1 Channel 3 output IDLE - -config STM32F7_TIM1_CH3NPOL - int "TIM1 Channel 3 Complementary Output polarity" - default 0 - range 0 1 - depends on STM32F7_TIM1_CH3NOUT - ---help--- - TIM1 Channel 3 Complementary Output polarity - -config STM32F7_TIM1_CH3NIDLE - int "TIM1 Channel 3 Complementary Output IDLE" - default 0 - range 0 1 - depends on STM32F7_TIM1_CH3NOUT - ---help--- - TIM1 Channel 3 Complementary Output IDLE - -config STM32F7_TIM1_CH4POL - int "TIM1 Channel 4 Output polarity" - default 0 - range 0 1 - depends on STM32F7_TIM1_CH4OUT - ---help--- - TIM1 Channel 4 output polarity - -config STM32F7_TIM1_CH4IDLE - int "TIM1 Channel 4 Output IDLE" - default 0 - range 0 1 - depends on STM32F7_TIM1_CH4OUT - ---help--- - TIM1 Channel 4 output IDLE - -config STM32F7_TIM1_CH5POL - int "TIM1 Channel 5 Output polarity" - default 0 - range 0 1 - depends on STM32F7_TIM1_CH5OUT - ---help--- - TIM1 Channel 5 output polarity - -config STM32F7_TIM1_CH5IDLE - int "TIM1 Channel 5 Output IDLE" - default 0 - range 0 1 - depends on STM32F7_TIM1_CH5OUT - ---help--- - TIM1 Channel 5 output IDLE - -config STM32F7_TIM1_CH6POL - int "TIM1 Channel 6 Output polarity" - default 0 - range 0 1 - depends on STM32F7_TIM1_CH6OUT - ---help--- - TIM1 Channel 6 output polarity - -config STM32F7_TIM1_CH6IDLE - int "TIM1 Channel 6 Output IDLE" - default 0 - range 0 1 - depends on STM32F7_TIM1_CH6OUT - ---help--- - TIM1 Channel 6 output IDLE - -config STM32F7_TIM2_CH1POL - int "TIM2 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32F7_TIM2_CH1OUT - ---help--- - TIM2 Channel 1 output polarity - -config STM32F7_TIM2_CH1IDLE - int "TIM2 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32F7_TIM2_CH1OUT - ---help--- - TIM2 Channel 1 output IDLE - -config STM32F7_TIM2_CH2POL - int "TIM2 Channel 2 Output polarity" - default 0 - range 0 1 - depends on STM32F7_TIM2_CH2OUT - ---help--- - TIM2 Channel 2 output polarity - -config STM32F7_TIM2_CH2IDLE - int "TIM2 Channel 2 Output IDLE" - default 0 - range 0 1 - depends on STM32F7_TIM2_CH2OUT - ---help--- - TIM2 Channel 2 output IDLE - -config STM32F7_TIM2_CH3POL - int "TIM2 Channel 3 Output polarity" - default 0 - range 0 1 - depends on STM32F7_TIM2_CH3OUT - ---help--- - TIM2 Channel 3 output polarity - -config STM32F7_TIM2_CH3IDLE - int "TIM2 Channel 3 Output IDLE" - default 0 - range 0 1 - depends on STM32F7_TIM2_CH3OUT - ---help--- - TIM2 Channel 3 output IDLE - -config STM32F7_TIM2_CH4POL - int "TIM2 Channel 4 Output polarity" - default 0 - range 0 1 - depends on STM32F7_TIM2_CH4OUT - ---help--- - TIM2 Channel 4 output polarity - -config STM32F7_TIM2_CH4IDLE - int "TIM2 Channel 4 Output IDLE" - default 0 - range 0 1 - depends on STM32F7_TIM2_CH4OUT - ---help--- - TIM2 Channel 4 output IDLE - -config STM32F7_TIM3_CH1POL - int "TIM3 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32F7_TIM3_CH1OUT - ---help--- - TIM3 Channel 1 output polarity - -config STM32F7_TIM3_CH1IDLE - int "TIM3 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32F7_TIM3_CH1OUT - ---help--- - TIM3 Channel 1 output IDLE - -config STM32F7_TIM3_CH2POL - int "TIM3 Channel 2 Output polarity" - default 0 - range 0 1 - depends on STM32F7_TIM3_CH2OUT - ---help--- - TIM3 Channel 2 output polarity - -config STM32F7_TIM3_CH2IDLE - int "TIM3 Channel 2 Output IDLE" - default 0 - range 0 1 - depends on STM32F7_TIM3_CH2OUT - ---help--- - TIM3 Channel 2 output IDLE - -config STM32F7_TIM3_CH3POL - int "TIM3 Channel 3 Output polarity" - default 0 - range 0 1 - depends on STM32F7_TIM3_CH3OUT - ---help--- - TIM3 Channel 3 output polarity - -config STM32F7_TIM3_CH3IDLE - int "TIM3 Channel 3 Output IDLE" - default 0 - range 0 1 - depends on STM32F7_TIM3_CH3OUT - ---help--- - TIM3 Channel 3 output IDLE - -config STM32F7_TIM3_CH4POL - int "TIM3 Channel 4 Output polarity" - default 0 - range 0 1 - depends on STM32F7_TIM3_CH4OUT - ---help--- - TIM3 Channel 4 output polarity - -config STM32F7_TIM3_CH4IDLE - int "TIM3 Channel 4 Output IDLE" - default 0 - range 0 1 - depends on STM32F7_TIM3_CH4OUT - ---help--- - TIM3 Channel 4 output IDLE - -config STM32F7_TIM4_CH1POL - int "TIM4 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32F7_TIM4_CH1OUT - ---help--- - TIM4 Channel 1 output polarity - -config STM32F7_TIM4_CH1IDLE - int "TIM4 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32F7_TIM4_CH1OUT - ---help--- - TIM4 Channel 1 output IDLE - -config STM32F7_TIM4_CH2POL - int "TIM4 Channel 2 Output polarity" - default 0 - range 0 1 - depends on STM32F7_TIM4_CH2OUT - ---help--- - TIM4 Channel 2 output polarity - -config STM32F7_TIM4_CH2IDLE - int "TIM4 Channel 2 Output IDLE" - default 0 - range 0 1 - depends on STM32F7_TIM4_CH2OUT - ---help--- - TIM4 Channel 2 output IDLE - -config STM32F7_TIM4_CH3POL - int "TIM4 Channel 3 Output polarity" - default 0 - range 0 1 - depends on STM32F7_TIM4_CH3OUT - ---help--- - TIM4 Channel 3 output polarity - -config STM32F7_TIM4_CH3IDLE - int "TIM4 Channel 3 Output IDLE" - default 0 - range 0 1 - depends on STM32F7_TIM4_CH3OUT - ---help--- - TIM4 Channel 3 output IDLE - -config STM32F7_TIM4_CH4POL - int "TIM4 Channel 4 Output polarity" - default 0 - range 0 1 - depends on STM32F7_TIM4_CH4OUT - ---help--- - TIM4 Channel 4 output polarity - -config STM32F7_TIM4_CH4IDLE - int "TIM4 Channel 4 Output IDLE" - default 0 - range 0 1 - depends on STM32F7_TIM4_CH4OUT - ---help--- - TIM4 Channel 4 output IDLE - -config STM32F7_TIM5_CH1POL - int "TIM5 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32F7_TIM5_CH1OUT - ---help--- - TIM5 Channel 1 output polarity - -config STM32F7_TIM5_CH1IDLE - int "TIM5 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32F7_TIM5_CH1OUT - ---help--- - TIM5 Channel 1 output IDLE - -config STM32F7_TIM5_CH2POL - int "TIM5 Channel 2 Output polarity" - default 0 - range 0 1 - depends on STM32F7_TIM5_CH2OUT - ---help--- - TIM5 Channel 2 output polarity - -config STM32F7_TIM5_CH2IDLE - int "TIM5 Channel 2 Output IDLE" - default 0 - range 0 1 - depends on STM32F7_TIM5_CH2OUT - ---help--- - TIM5 Channel 2 output IDLE - -config STM32F7_TIM5_CH3POL - int "TIM5 Channel 3 Output polarity" - default 0 - range 0 1 - depends on STM32F7_TIM5_CH3OUT - ---help--- - TIM5 Channel 3 output polarity - -config STM32F7_TIM5_CH3IDLE - int "TIM5 Channel 3 Output IDLE" - default 0 - range 0 1 - depends on STM32F7_TIM5_CH3OUT - ---help--- - TIM5 Channel 3 output IDLE - -config STM32F7_TIM5_CH4POL - int "TIM5 Channel 4 Output polarity" - default 0 - range 0 1 - depends on STM32F7_TIM5_CH4OUT - ---help--- - TIM5 Channel 4 output polarity - -config STM32F7_TIM5_CH4IDLE - int "TIM5 Channel 4 Output IDLE" - default 0 - range 0 1 - depends on STM32F7_TIM5_CH4OUT - ---help--- - TIM5 Channel 4 output IDLE - -config STM32F7_TIM8_CH1POL - int "TIM8 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32F7_TIM8_CH1OUT - ---help--- - TIM8 Channel 1 output polarity - -config STM32F7_TIM8_CH1IDLE - int "TIM8 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32F7_TIM8_CH1OUT - ---help--- - TIM8 Channel 1 output IDLE - -config STM32F7_TIM8_CH1NPOL - int "TIM8 Channel 1 Complementary Output polarity" - default 0 - range 0 1 - depends on STM32F7_TIM8_CH1NOUT - ---help--- - TIM8 Channel 1 Complementary Output polarity - -config STM32F7_TIM8_CH1NIDLE - int "TIM8 Channel 1 Complementary Output IDLE" - default 0 - range 0 1 - depends on STM32F7_TIM8_CH1NOUT - ---help--- - TIM8 Channel 1 Complementary Output IDLE - -config STM32F7_TIM8_CH2POL - int "TIM8 Channel 2 Output polarity" - default 0 - range 0 1 - depends on STM32F7_TIM8_CH2OUT - ---help--- - TIM8 Channel 2 output polarity - -config STM32F7_TIM8_CH2IDLE - int "TIM8 Channel 2 Output IDLE" - default 0 - range 0 1 - depends on STM32F7_TIM8_CH2OUT - ---help--- - TIM8 Channel 2 output IDLE - -config STM32F7_TIM8_CH2NPOL - int "TIM8 Channel 2 Complementary Output polarity" - default 0 - range 0 1 - depends on STM32F7_TIM8_CH2NOUT - ---help--- - TIM8 Channel 2 Complementary Output polarity - -config STM32F7_TIM8_CH2NIDLE - int "TIM8 Channel 2 Complementary Output IDLE" - default 0 - range 0 1 - depends on STM32F7_TIM8_CH2NOUT - ---help--- - TIM8 Channel 2 Complementary Output IDLE - -config STM32F7_TIM8_CH3POL - int "TIM8 Channel 3 Output polarity" - default 0 - range 0 1 - depends on STM32F7_TIM8_CH3OUT - ---help--- - TIM8 Channel 3 output polarity - -config STM32F7_TIM8_CH3IDLE - int "TIM8 Channel 3 Output IDLE" - default 0 - range 0 1 - depends on STM32F7_TIM8_CH3OUT - ---help--- - TIM8 Channel 3 output IDLE - -config STM32F7_TIM8_CH3NPOL - int "TIM8 Channel 3 Complementary Output polarity" - default 0 - range 0 1 - depends on STM32F7_TIM8_CH3NOUT - ---help--- - TIM8 Channel 3 Complementary Output polarity - -config STM32F7_TIM8_CH3NIDLE - int "TIM8 Channel 3 Complementary Output IDLE" - default 0 - range 0 1 - depends on STM32F7_TIM8_CH3NOUT - ---help--- - TIM8 Channel 3 Complementary Output IDLE - -config STM32F7_TIM8_CH4POL - int "TIM8 Channel 4 Output polarity" - default 0 - range 0 1 - depends on STM32F7_TIM8_CH4OUT - ---help--- - TIM8 Channel 4 output polarity - -config STM32F7_TIM8_CH4IDLE - int "TIM8 Channel 4 Output IDLE" - default 0 - range 0 1 - depends on STM32F7_TIM8_CH4OUT - ---help--- - TIM8 Channel 4 output IDLE - -config STM32F7_TIM8_CH5POL - int "TIM8 Channel 5 Output polarity" - default 0 - range 0 1 - depends on STM32F7_TIM8_CH5OUT - ---help--- - TIM8 Channel 5 output polarity - -config STM32F7_TIM8_CH5IDLE - int "TIM8 Channel 5 Output IDLE" - default 0 - range 0 1 - depends on STM32F7_TIM8_CH5OUT - ---help--- - TIM8 Channel 5 output IDLE - -config STM32F7_TIM8_CH6POL - int "TIM8 Channel 6 Output polarity" - default 0 - range 0 1 - depends on STM32F7_TIM8_CH6OUT - ---help--- - TIM8 Channel 6 output polarity - -config STM32F7_TIM8_CH6IDLE - int "TIM8 Channel 6 Output IDLE" - default 0 - range 0 1 - depends on STM32F7_TIM8_CH6OUT - ---help--- - TIM8 Channel 6 output IDLE - -config STM32F7_TIM9_CH1POL - int "TIM9 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32F7_TIM9_CH1OUT - ---help--- - TIM9 Channel 1 output polarity - -config STM32F7_TIM9_CH1IDLE - int "TIM9 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32F7_TIM9_CH1OUT - ---help--- - TIM9 Channel 1 output IDLE - -config STM32F7_TIM9_CH2POL - int "TIM9 Channel 2 Output polarity" - default 0 - range 0 1 - depends on STM32F7_TIM9_CH2OUT - ---help--- - TIM9 Channel 2 output polarity - -config STM32F7_TIM9_CH2IDLE - int "TIM9 Channel 2 Output IDLE" - default 0 - range 0 1 - depends on STM32F7_TIM9_CH2OUT - ---help--- - TIM9 Channel 2 output IDLE - -config STM32F7_TIM10_CH1POL - int "TIM10 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32F7_TIM10_CH1OUT - ---help--- - TIM10 Channel 1 output polarity - -config STM32F7_TIM10_CH1IDLE - int "TIM10 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32F7_TIM10_CH1OUT - ---help--- - TIM10 Channel 1 output IDLE - -config STM32F7_TIM11_CH1POL - int "TIM11 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32F7_TIM11_CH1OUT - ---help--- - TIM11 Channel 1 output polarity - -config STM32F7_TIM11_CH1IDLE - int "TIM11 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32F7_TIM11_CH1OUT - ---help--- - TIM11 Channel 1 output IDLE - -config STM32F7_TIM12_CH1POL - int "TIM12 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32F7_TIM12_CH1OUT - ---help--- - TIM12 Channel 1 output polarity - -config STM32F7_TIM12_CH1IDLE - int "TIM12 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32F7_TIM12_CH1OUT - ---help--- - TIM12 Channel 1 output IDLE - -config STM32F7_TIM12_CH2POL - int "TIM12 Channel 2 Output polarity" - default 0 - range 0 1 - depends on STM32F7_TIM12_CH2OUT - ---help--- - TIM12 Channel 2 output polarity - -config STM32F7_TIM12_CH2IDLE - int "TIM12 Channel 2 Output IDLE" - default 0 - range 0 1 - depends on STM32F7_TIM12_CH2OUT - ---help--- - TIM12 Channel 2 output IDLE - -config STM32F7_TIM13_CH1POL - int "TIM13 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32F7_TIM13_CH1OUT - ---help--- - TIM13 Channel 1 output polarity - -config STM32F7_TIM13_CH1IDLE - int "TIM13 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32F7_TIM13_CH1OUT - ---help--- - TIM13 Channel 1 output IDLE - -config STM32F7_TIM14_CH1POL - int "TIM14 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32F7_TIM14_CH1OUT - ---help--- - TIM14 Channel 1 output polarity - -config STM32F7_TIM14_CH1IDLE - int "TIM14 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32F7_TIM14_CH1OUT - ---help--- - TIM14 Channel 1 output IDLE - -endmenu #STM32 TIMx Outputs Configuration - -endmenu # Timer Configuration - -menu "CAN driver configuration" - depends on STM32F7_CAN - -choice - prompt "CAN character driver or SocketCAN support" - default STM32F7_CAN_CHARDRIVER - -config STM32F7_CAN_CHARDRIVER - bool "STM32F7 CAN character driver support" - select ARCH_HAVE_CAN_ERRORS - select CAN - -config STM32F7_CAN_SOCKET - bool "STM32F7 CAN SocketCAN support" - select NET_CAN_HAVE_ERRORS - -endchoice # CAN character driver or SocketCAN support - -config STM32F7_CAN1_BAUD - int "CAN1 BAUD" - default 250000 - depends on STM32F7_CAN1 - ---help--- - CAN1 BAUD rate. Required if CONFIG_STM32F7_CAN1 is defined. - -config STM32F7_CAN2_BAUD - int "CAN2 BAUD" - default 250000 - depends on STM32F7_CAN2 - ---help--- - CAN2 BAUD rate. Required if CONFIG_STM32F7_CAN2 is defined. - -config STM32F7_CAN3_BAUD - int "CAN3 BAUD" - default 250000 - depends on STM32F7_CAN3 - ---help--- - CAN2 BAUD rate. Required if CONFIG_STM32F7_CAN2 is defined. - -config STM32F7_CAN_TSEG1 - int "TSEG1 quanta" - default 6 - ---help--- - The number of CAN time quanta in segment 1. Default: 6 - -config STM32F7_CAN_TSEG2 - int "TSEG2 quanta" - default 7 - ---help--- - The number of CAN time quanta in segment 2. Default: 7 - -config STM32F7_CAN_REGDEBUG - bool "CAN Register level debug" - depends on DEBUG_CAN_INFO - default n - ---help--- - Output detailed register-level CAN device debug information. - Requires also CONFIG_DEBUG_CAN_INFO. - -endmenu - -menu "ADC Configuration" - depends on STM32F7_ADC - -config STM32F7_ADC1_RESOLUTION - int "ADC1 resolution" - depends on STM32F7_ADC1 - default 0 - range 0 3 - ---help--- - ADC1 resolution. 0 - 12 bit, 1 - 10 bit, 2 - 8 bit, 3 - 6 bit - -config STM32F7_ADC2_RESOLUTION - int "ADC2 resolution" - depends on STM32F7_ADC2 - default 0 - range 0 3 - ---help--- - ADC2 resolution. 0 - 12 bit, 1 - 10 bit, 2 - 8 bit, 3 - 6 bit - -config STM32F7_ADC3_RESOLUTION - int "ADC3 resolution" - depends on STM32F7_ADC3 - default 0 - range 0 3 - ---help--- - ADC3 resolution. 0 - 12 bit, 1 - 10 bit, 2 - 8 bit, 3 - 6 bit - -config STM32F7_ADC_MAX_SAMPLES - int "The maximum number of channels that can be sampled" - default 16 - ---help--- - The maximum number of samples which can be handled without - overrun depends on various factors. This is the user's - responsibility to correctly select this value. - Since the interface to update the sampling time is available - for all supported devices, the user can change the default - values in the board initialization logic and avoid ADC overrun. - -config STM32F7_ADC_NO_STARTUP_CONV - bool "Do not start conversion when opening ADC device" - default n - ---help--- - Do not start conversion when opening ADC device. - -config STM32F7_ADC_NOIRQ - bool "Do not use default ADC interrupts" - default n - ---help--- - Do not use default ADC interrupts handlers. - -config STM32F7_ADC_LL_OPS - bool "ADC low-level operations" - default n - ---help--- - Enable low-level ADC ops. - -config STM32F7_ADC_CHANGE_SAMPLETIME - bool "ADC sample time configuration" - default n - depends on STM32F7_ADC_LL_OPS - ---help--- - Enable ADC sample time configuration (SMPRx registers). - -config STM32F7_ADC1_DMA - bool "ADC1 DMA" - depends on STM32F7_ADC1 && STM32F7_HAVE_ADC1_DMA - default n - ---help--- - If DMA is selected, then the ADC may be configured to support - DMA transfer, which is necessary if multiple channels are read - or if very high trigger frequencies are used. - -config STM32F7_ADC1_SCAN - bool "ADC1 scan mode" - depends on STM32F7_ADC1 - default STM32F7_ADC1_DMA - default n - -config STM32F7_ADC1_DMA_CFG - int "ADC1 DMA configuration" - depends on STM32F7_ADC1_DMA - range 0 1 - default 0 - ---help--- - 0 - ADC1 DMA in One Shot Mode, 1 - ADC1 DMA in Circular Mode - -config STM32F7_ADC1_DMA_BATCH - int "ADC1 DMA number of conversions" - depends on STM32F7_ADC1 && STM32F7_ADC1_DMA - default 1 - ---help--- - This option allows you to select the number of regular group conversions - that will trigger a DMA callback transerring data to the upper-half driver. - By default, this value is 1, which means that data is transferred after - each group conversion. - -config STM32F7_ADC1_ANIOC_TRIGGER - int "ADC1 software trigger (ANIOC_TRIGGER) configuration" - depends on STM32F7_ADC1 - range 1 3 - default 3 - ---help--- - 1 - ANIOC_TRIGGER only starts regular conversion - 2 - ANIOC_TRIGGER only starts injected conversion - 3 - ANIOC_TRIGGER starts both regular and injected conversions - -config STM32F7_ADC2_DMA - bool "ADC2 DMA" - depends on STM32F7_ADC2 && STM32F7_HAVE_ADC2_DMA - default n - ---help--- - If DMA is selected, then the ADC may be configured to support - DMA transfer, which is necessary if multiple channels are read - or if very high trigger frequencies are used. - -config STM32F7_ADC2_SCAN - bool "ADC2 scan mode" - depends on STM32F7_ADC2 - default STM32F7_ADC2_DMA - -config STM32F7_ADC2_DMA_CFG - int "ADC2 DMA configuration" - depends on STM32F7_ADC2_DMA - range 0 1 - default 0 - ---help--- - 0 - ADC2 DMA in One Shot Mode, 1 - ADC2 DMA in Circular Mode - -config STM32F7_ADC2_DMA_BATCH - int "ADC2 DMA number of conversions" - depends on STM32F7_ADC2 && STM32F7_ADC2_DMA - default 1 - ---help--- - This option allows you to select the number of regular group conversions - that will trigger a DMA callback transerring data to the upper-half driver. - By default, this value is 1, which means that data is transferred after - each group conversion. - -config STM32F7_ADC2_ANIOC_TRIGGER - int "ADC2 software trigger (ANIOC_TRIGGER) configuration" - depends on STM32F7_ADC2 - range 1 3 - default 3 - ---help--- - 1 - ANIOC_TRIGGER only starts regular conversion - 2 - ANIOC_TRIGGER only starts injected conversion - 3 - ANIOC_TRIGGER starts both regular and injected conversions - -config STM32F7_ADC3_DMA - bool "ADC3 DMA" - depends on STM32F7_ADC3 && STM32F7_HAVE_ADC3_DMA - default n - ---help--- - If DMA is selected, then the ADC may be configured to support - DMA transfer, which is necessary if multiple channels are read - or if very high trigger frequencies are used. - -config STM32F7_ADC3_SCAN - bool "ADC3 scan mode" - depends on STM32F7_ADC3 - default STM32F7_ADC3_DMA - -config STM32F7_ADC3_DMA_CFG - int "ADC3 DMA configuration" - depends on STM32F7_ADC3_DMA - range 0 1 - default 0 - ---help--- - 0 - ADC3 DMA in One Shot Mode, 1 - ADC3 DMA in Circular Mode - -config STM32F7_ADC3_DMA_BATCH - int "ADC3 DMA number of conversions" - depends on STM32F7_ADC3 && STM32F7_ADC3_DMA - default 1 - ---help--- - This option allows you to select the number of regular group conversions - that will trigger a DMA callback transerring data to the upper-half driver. - By default, this value is 1, which means that data is transferred after - each group conversion. - -config STM32F7_ADC3_ANIOC_TRIGGER - int "ADC3 software trigger (ANIOC_TRIGGER) configuration" - depends on STM32F7_ADC3 - range 1 3 - default 3 - ---help--- - 1 - ANIOC_TRIGGER only starts regular conversion - 2 - ANIOC_TRIGGER only starts injected conversion - 3 - ANIOC_TRIGGER starts both regular and injected conversions - -config STM32F7_ADC1_INJECTED_CHAN - int "ADC1 injected channels" - depends on STM32F7_ADC1 - range 0 4 - default 0 - ---help--- - Support for ADC1 injected channels. - -config STM32F7_ADC2_INJECTED_CHAN - int "ADC2 injected channels" - depends on STM32F7_ADC2 - range 0 4 - default 0 - ---help--- - Support for ADC2 injected channels. - -config STM32F7_ADC3_INJECTED_CHAN - int "ADC3 injected channels" - depends on STM32F7_ADC3 - range 0 4 - default 0 - ---help--- - Support for ADC3 injected channels. - -config STM32F7_ADC1_EXTSEL - bool "ADC1 external trigger for regular group" - depends on STM32F7_ADC1 && !STM32F7_HAVE_ADC1_TIMER - default n - ---help--- - Enable EXTSEL for ADC1. - -config STM32F7_ADC2_EXTSEL - bool "ADC2 external trigger for regular group" - depends on STM32F7_ADC2 && !STM32F7_HAVE_ADC2_TIMER - default n - ---help--- - Enable EXTSEL for ADC2. - -config STM32F7_ADC3_EXTSEL - bool "ADC3 external trigger for regular group" - depends on STM32F7_ADC3 && !STM32F7_HAVE_ADC3_TIMER - default n - ---help--- - Enable EXTSEL for ADC3. - -config STM32F7_ADC1_JEXTSEL - bool "ADC1 external trigger for injected group" - depends on STM32F7_ADC1 - default n - ---help--- - Enable JEXTSEL for ADC1. - -config STM32F7_ADC2_JEXTSEL - bool "ADC2 external trigger for injected group" - depends on STM32F7_ADC2 - default n - ---help--- - Enable JEXTSEL for ADC2. - -config STM32F7_ADC3_JEXTSEL - bool "ADC3 external trigger for injected group" - depends on STM32F7_ADC3 - default n - ---help--- - Enable JEXTSEL for ADC3. - -endmenu # "ADC Configuration" - -menu "Ethernet MAC configuration" - depends on STM32F7_ETHMAC - -config STM32F7_PHYADDR - int "PHY address" - default 1 - ---help--- - The 5-bit address of the PHY on the board. Default: 1 - -config STM32F7_PHYINIT - bool "Board-specific PHY Initialization" - default n - ---help--- - Some boards require specialized initialization of the PHY before it can be used. - This may include such things as configuring GPIOs, resetting the PHY, etc. If - STM32F7_PHYINIT is defined in the configuration then the board specific logic must - provide stm32_phyinitialize(); The STM32 Ethernet driver will call this function - one time before it first uses the PHY. - -config STM32F7_PHY_POLLING - bool "Support network monitoring by polling the PHY" - default n - depends on STM32F7_HAVE_PHY_POLLED - select ARCH_PHY_POLLED - ---help--- - Some boards may not have an interrupt connected to the PHY. - This option allows the network monitor to be used by polling the - the PHY for status. - -config STM32F7_MII - bool "Use MII interface" - default n - ---help--- - Support Ethernet MII interface. - -choice - prompt "MII clock configuration" - default STM32F7_MII_EXTCLK - depends on STM32F7_MII - -config STM32F7_MII_MCO1 - bool "Use MC01 as MII clock" - ---help--- - Use MCO1 to clock the MII interface. - -config STM32F7_MII_MCO2 - bool "Use MC02 as MII clock" - ---help--- - Use MCO2 to clock the MII interface. - -config STM32F7_MII_EXTCLK - bool "External MII clock" - ---help--- - Clocking is provided by external logic. - -endchoice - -config STM32F7_AUTONEG - bool "Use autonegotiation" - default y - ---help--- - Use PHY autonegotiation to determine speed and mode - -config STM32F7_ETHFD - bool "Full duplex" - default n - depends on !STM32F7_AUTONEG - ---help--- - If STM32F7_AUTONEG is not defined, then this may be defined to select full duplex - mode. Default: half-duplex - -config STM32F7_ETH100MBPS - bool "100 Mbps" - default n - depends on !STM32F7_AUTONEG - ---help--- - If STM32F7_AUTONEG is not defined, then this may be defined to select 100 MBps - speed. Default: 10 Mbps - -config STM32F7_PHYSR - int "PHY Status Register Address (decimal)" - depends on STM32F7_AUTONEG - ---help--- - This must be provided if STM32F7_AUTONEG is defined. The PHY status register - address may diff from PHY to PHY. This configuration sets the address of - the PHY status register. - -config STM32F7_PHYSR_ALTCONFIG - bool "PHY Status Alternate Bit Layout" - default n - depends on STM32F7_AUTONEG - ---help--- - Different PHYs present speed and mode information in different ways. Some - will present separate information for speed and mode (this is the default). - Those PHYs, for example, may provide a 10/100 Mbps indication and a separate - full/half duplex indication. This options selects an alternative representation - where speed and mode information are combined. This might mean, for example, - separate bits for 10HD, 100HD, 10FD and 100FD. - -config STM32F7_PHYSR_SPEED - hex "PHY Speed Mask" - depends on STM32F7_AUTONEG && !STM32F7_PHYSR_ALTCONFIG - ---help--- - This must be provided if STM32F7_AUTONEG is defined. This provides bit mask - for isolating the 10 or 100MBps speed indication. - -config STM32F7_PHYSR_100MBPS - hex "PHY 100Mbps Speed Value" - depends on STM32F7_AUTONEG && !STM32F7_PHYSR_ALTCONFIG - ---help--- - This must be provided if STM32F7_AUTONEG is defined. This provides the value - of the speed bit(s) indicating 100MBps speed. - -config STM32F7_PHYSR_MODE - hex "PHY Mode Mask" - depends on STM32F7_AUTONEG && !STM32F7_PHYSR_ALTCONFIG - ---help--- - This must be provided if STM32F7_AUTONEG is defined. This provide bit mask - for isolating the full or half duplex mode bits. - -config STM32F7_PHYSR_FULLDUPLEX - hex "PHY Full Duplex Mode Value" - depends on STM32F7_AUTONEG && !STM32F7_PHYSR_ALTCONFIG - ---help--- - This must be provided if STM32F7_AUTONEG is defined. This provides the - value of the mode bits indicating full duplex mode. - -config STM32F7_PHYSR_ALTMODE - hex "PHY Mode Mask" - depends on STM32F7_AUTONEG && STM32F7_PHYSR_ALTCONFIG - ---help--- - This must be provided if STM32F7_AUTONEG is defined. This provide bit mask - for isolating the speed and full/half duplex mode bits. - -config STM32F7_PHYSR_10HD - hex "10MBase-T Half Duplex Value" - depends on STM32F7_AUTONEG && STM32F7_PHYSR_ALTCONFIG - ---help--- - This must be provided if STM32F7_AUTONEG is defined. This is the value - under the bit mask that represents the 10Mbps, half duplex setting. - -config STM32F7_PHYSR_100HD - hex "100Base-T Half Duplex Value" - depends on STM32F7_AUTONEG && STM32F7_PHYSR_ALTCONFIG - ---help--- - This must be provided if STM32F7_AUTONEG is defined. This is the value - under the bit mask that represents the 100Mbps, half duplex setting. - -config STM32F7_PHYSR_10FD - hex "10Base-T Full Duplex Value" - depends on STM32F7_AUTONEG && STM32F7_PHYSR_ALTCONFIG - ---help--- - This must be provided if STM32F7_AUTONEG is defined. This is the value - under the bit mask that represents the 10Mbps, full duplex setting. - -config STM32F7_PHYSR_100FD - hex "100Base-T Full Duplex Value" - depends on STM32F7_AUTONEG && STM32F7_PHYSR_ALTCONFIG - ---help--- - This must be provided if STM32F7_AUTONEG is defined. This is the value - under the bit mask that represents the 100Mbps, full duplex setting. - -config STM32F7_ETH_PTP - bool "Precision Time Protocol (PTP)" - default n - ---help--- - Precision Time Protocol (PTP). Not supported but some hooks are indicated - with this condition. - -config STM32F7_RMII - bool - default !STM32F7_MII - -choice - prompt "RMII clock configuration" - default STM32F7_RMII_EXTCLK - depends on STM32F7_RMII - -config STM32F7_RMII_MCO1 - bool "Use MC01 as RMII clock" - ---help--- - Use MCO1 to clock the RMII interface. - -config STM32F7_RMII_MCO2 - bool "Use MC02 as RMII clock" - ---help--- - Use MCO2 to clock the RMII interface. - -config STM32F7_RMII_EXTCLK - bool "External RMII clock" - ---help--- - Clocking is provided by external logic. - -endchoice # RMII clock configuration - -config STM32F7_ETHMAC_REGDEBUG - bool "Register-Level Debug" - default n - depends on DEBUG_NET_INFO - ---help--- - Enable very low-level register access debug. Depends on - CONFIG_DEBUG_FEATURES. - -endmenu # Ethernet MAC configuration - -if STM32F7_LTDC - -menu "LTDC Configuration" - -config STM32F7_LTDC_USE_DSI - bool "Use DSI as display connection" - default n - depends on STM32F7_DSIHOST - ---help--- - Select this if your display is connected via DSI. - Deselect option if your display is connected via digital - RGB+HSYNC+VSYNC - -config STM32F7_LTDC_BACKLIGHT - bool "Backlight support" - default y - -config STM32F7_LTDC_DEFBACKLIGHT - hex "Default backlight level" - default 0xf0 - -config STM32F7_LTDC_BACKCOLOR - hex "Background color" - default 0x0 - ---help--- - This is the background color that will be used as the LTDC - background layer color. It is an RGB888 format value, - which gets written unmodified to register LTDC_BCCR. - -config STM32F7_LTDC_DITHER - bool "Dither support" - default n - -config STM32F7_LTDC_DITHER_RED - depends on STM32F7_LTDC_DITHER - int "Dither red width" - range 0 7 - default 2 - ---help--- - This is the dither red width. - -config STM32F7_LTDC_DITHER_GREEN - depends on STM32F7_LTDC_DITHER - int "Dither green width" - range 0 7 - default 2 - ---help--- - This is the dither green width. - -config STM32F7_LTDC_DITHER_BLUE - depends on STM32F7_LTDC_DITHER - int "Dither blue width" - range 0 7 - default 2 - ---help--- - This is the dither blue width. - -config STM32F7_LTDC_FB_BASE - hex "Framebuffer memory start address" - default 0 - ---help--- - If you are using the LTDC, then you must provide the address - of the start of the framebuffer. This address will typically - be in the SRAM or SDRAM memory region of the FMC. - -config STM32F7_LTDC_FB_SIZE - int "Framebuffer memory size (bytes)" - default 0 - ---help--- - Must be the whole size of the active LTDC layer. - -config STM32F7_LTDC_L1_CHROMAKEYEN - bool "Enable chromakey support for layer 1" - default y - -config STM32F7_LTDC_L1_CHROMAKEY - hex "Layer L1 initial chroma key" - default 0x00000000 - -config STM32F7_LTDC_L1_COLOR - hex "Layer L1 default color" - default 0x00000000 - -choice - prompt "Layer 1 color format" - default STM32F7_LTDC_L1_RGB565 - -config STM32F7_LTDC_L1_L8 - bool "8 bpp L8 (8-bit CLUT)" - depends on STM32F7_FB_CMAP - -config STM32F7_LTDC_L1_AL44 - bool "8 bpp AL44 (4-bit alpha + 4-bit CLUT)" - depends on STM32F7_FB_CMAP - -config STM32F7_LTDC_L1_AL88 - bool "16 bpp AL88 (8-bit alpha + 8-bit CLUT)" - depends on STM32F7_FB_CMAP - -config STM32F7_LTDC_L1_RGB565 - bool "16 bpp RGB 565" - depends on !STM32F7_FB_CMAP - -config STM32F7_LTDC_L1_ARGB4444 - bool "16 bpp ARGB 4444" - depends on !STM32F7_FB_CMAP - -config STM32F7_LTDC_L1_ARGB1555 - bool "16 bpp ARGB 1555" - depends on !STM32F7_FB_CMAP - -config STM32F7_LTDC_L1_RGB888 - bool "24 bpp RGB 888" - depends on !STM32F7_FB_CMAP - -config STM32F7_LTDC_L1_ARGB8888 - bool "32 bpp ARGB 8888" - depends on !STM32F7_FB_CMAP - -endchoice # Layer 1 color format - -config STM32F7_LTDC_L2 - bool "Enable Layer 2 support" - default y - -if STM32F7_LTDC_L2 - -config STM32F7_LTDC_L2_COLOR - hex "Layer L2 default color" - default 0x00000000 - -config STM32F7_LTDC_L2_CHROMAKEYEN - bool "Enable chromakey support for layer 2" - default y - -config STM32F7_LTDC_L2_CHROMAKEY - hex "Layer L2 initial chroma key" - default 0x00000000 - -choice - prompt "Layer 2 (top layer) color format" - default STM32F7_LTDC_L2_RGB565 - -config STM32F7_LTDC_L2_L8 - depends on STM32F7_LTDC_L1_L8 - bool "8 bpp L8 (8-bit CLUT)" - -config STM32F7_LTDC_L2_AL44 - depends on STM32F7_LTDC_L1_AL44 - bool "8 bpp AL44 (4-bit alpha + 4-bit CLUT)" - -config STM32F7_LTDC_L2_AL88 - depends on STM32F7_LTDC_L1_AL88 - bool "16 bpp AL88 (8-bit alpha + 8-bit CLUT)" - -config STM32F7_LTDC_L2_RGB565 - depends on STM32F7_LTDC_L1_RGB565 - bool "16 bpp RGB 565" - -config STM32F7_LTDC_L2_ARGB4444 - depends on STM32F7_LTDC_L1_ARGB4444 - bool "16 bpp ARGB 4444" - -config STM32F7_LTDC_L2_ARGB1555 - depends on STM32F7_LTDC_L1_ARGB1555 - bool "16 bpp ARGB 1555" - -config STM32F7_LTDC_L2_RGB888 - depends on STM32F7_LTDC_L1_RGB888 - bool "24 bpp RGB 888" - -config STM32F7_LTDC_L2_ARGB8888 - depends on STM32F7_LTDC_L1_ARGB8888 - bool "32 bpp ARGB 8888" - -endchoice # Layer 2 color format - -endif # STM32F7_LTDC_L2 - -config STM32F7_FB_CMAP - bool "Color map support" - default y - select FB_CMAP - ---help--- - EnablingEnablescolor map support is necessary for ltdc L8 format. - -config STM32F7_FB_TRANSPARENCY - bool "Transparency color map support" - default y - depends on STM32F7_FB_CMAP - select FB_TRANSPARENCY - ---help--- - Enables transparency color map support is necessary for ltdc L8 format. - -config STM32F7_LTDC_REGDEBUG - bool "Enable LTDC register value debug messages" - default n - ---help--- - This gives additional messages for LTDC related register values. - Additionally, you have to select "Low-level LCD Debug Features" - to enable the debug messages. - -endmenu - -endif # STM32F7_LTDC - -if STM32F7_DMA2D - -menu "DMA2D Configuration" - -config STM32F7_DMA2D_NLAYERS - int "Number DMA2D overlays" - default 1 - range 1 256 - ---help--- - Number of supported DMA2D layer. - -config STM32F7_DMA2D_LAYER_SHARED - bool "Overlays shared memory region" - default n - ---help--- - Several overlays can share the same memory region. - Setup a whole memory area (usually multiple size of the visible screen) - allows image preprocessing before they become visible by blit operation. - -config STM32F7_DMA2D_LAYER_PPLINE - int "Pixel per line" - default 1 - range 1 65535 - ---help--- - If you are using the DMA2D, then you must provide the pixel per line or - width of the overlay. - -config STM32F7_DMA2D_FB_BASE - hex "Framebuffer memory start address" - default 0 - ---help--- - If you are using the DMA2D, then you must provide the address - of the start of the DMA2D overlays framebuffer. This address will typically - be in the SRAM or SDRAM memory region of the FSMC. - -config STM32F7_DMA2D_FB_SIZE - int "Framebuffer memory size (bytes)" - default 0 - ---help--- - Must be the whole size of all DMA2D overlays. - -menu "Supported pixel format" - -config STM32F7_DMA2D_L8 - depends on STM32F7_FB_CMAP && STM32F7_LTDC_L1_L8 - bool "8 bpp L8 (8-bit CLUT)" - default y - -config STM32F7_DMA2D_AL44 - depends on STM32F7_FB_CMAP && STM32F7_LTDC_L1_AL44 - bool "8 bpp AL44 (4-bit alpha + 4-bit CLUT)" - default y - -config STM32F7_DMA2D_AL88 - depends on STM32F7_FB_CMAP && STM32F7_LTDC_L1_AL88 - bool "16 bpp AL88 (8-bit alpha + 8-bit CLUT)" - default y - -config STM32F7_DMA2D_RGB565 - bool "16 bpp RGB 565" - depends on STM32F7_LTDC_L1_RGB565 - default y - -config STM32F7_DMA2D_ARGB4444 - bool "16 bpp ARGB 4444" - depends on STM32F7_LTDC_L1_ARGB4444 - default y - -config STM32F7_DMA2D_ARGB1555 - bool "16 bpp ARGB 1555" - depends on STM32F7_LTDC_L1_ARGB15555 - default y - -config STM32F7_DMA2D_RGB888 - bool "24 bpp RGB 888" - depends on STM32F7_LTDC_L1_RGB888 - default y - -config STM32F7_DMA2D_ARGB8888 - bool "32 bpp ARGB 8888" - depends on STM32F7_LTDC_L1_ARGB8888 - default y - -endmenu - -config STM32F7_DMA2D_REGDEBUG - bool "DMA2D Register level debug" - depends on DEBUG_INFO && DEBUG_LCD - default n - ---help--- - Output detailed register-level DMA2D device debug information. - -endmenu -endif # STM32F7_DMA2D - -menu "QEncoder Driver" - depends on SENSORS_QENCODER - depends on STM32F7_TIM1 || STM32F7_TIM2 || STM32F7_TIM3 || STM32F7_TIM4 || STM32F7_TIM5 || STM32F7_TIM8 - -config STM32F7_TIM1_QE - bool "TIM1" - default n - depends on STM32F7_TIM1 - ---help--- - Reserve TIM1 for use by QEncoder. - -if STM32F7_TIM1_QE - -config STM32F7_TIM1_QEPSC - int "TIM1 pulse prescaler" - default 1 - ---help--- - This prescaler divides the number of recorded encoder pulses, - limiting the count rate at the expense of resolution. - -endif - -config STM32F7_TIM2_QE - bool "TIM2" - default n - depends on STM32F7_TIM2 - ---help--- - Reserve TIM2 for use by QEncoder. - -if STM32F7_TIM2_QE - -config STM32F7_TIM2_QEPSC - int "TIM2 pulse prescaler" - default 1 - ---help--- - This prescaler divides the number of recorded encoder pulses, - limiting the count rate at the expense of resolution. - -endif - -config STM32F7_TIM3_QE - bool "TIM3" - default n - depends on STM32F7_TIM3 - ---help--- - Reserve TIM3 for use by QEncoder. - -if STM32F7_TIM3_QE - -config STM32F7_TIM3_QEPSC - int "TIM3 pulse prescaler" - default 1 - ---help--- - This prescaler divides the number of recorded encoder pulses, - limiting the count rate at the expense of resolution. - -endif - -config STM32F7_TIM4_QE - bool "TIM4" - default n - depends on STM32F7_TIM4 - ---help--- - Reserve TIM4 for use by QEncoder. - -if STM32F7_TIM4_QE - -config STM32F7_TIM4_QEPSC - int "TIM4 pulse prescaler" - default 1 - ---help--- - This prescaler divides the number of recorded encoder pulses, - limiting the count rate at the expense of resolution. - -endif - -config STM32F7_TIM5_QE - bool "TIM5" - default n - depends on STM32F7_TIM5 - ---help--- - Reserve TIM5 for use by QEncoder. - -if STM32F7_TIM5_QE - -config STM32F7_TIM5_QEPSC - int "TIM5 pulse prescaler" - default 1 - ---help--- - This prescaler divides the number of recorded encoder pulses, - limiting the count rate at the expense of resolution. - -endif - -config STM32F7_TIM8_QE - bool "TIM8" - default n - depends on STM32F7_TIM8 - ---help--- - Reserve TIM8 for use by QEncoder. - -if STM32F7_TIM8_QE - -config STM32F7_TIM8_QEPSC - int "TIM8 pulse prescaler" - default 1 - ---help--- - This prescaler divides the number of recorded encoder pulses, - limiting the count rate at the expense of resolution. - -endif - -config STM32F7_QENCODER_FILTER - bool "Enable filtering on STM32 QEncoder input" - default y - -choice - depends on STM32F7_QENCODER_FILTER - prompt "Input channel sampling frequency" - default STM32F7_QENCODER_SAMPLE_FDTS_4 - -config STM32F7_QENCODER_SAMPLE_FDTS - bool "fDTS" - -config STM32F7_QENCODER_SAMPLE_CKINT - bool "fCK_INT" - -config STM32F7_QENCODER_SAMPLE_FDTS_2 - bool "fDTS/2" - -config STM32F7_QENCODER_SAMPLE_FDTS_4 - bool "fDTS/4" - -config STM32F7_QENCODER_SAMPLE_FDTS_8 - bool "fDTS/8" - -config STM32F7_QENCODER_SAMPLE_FDTS_16 - bool "fDTS/16" - -config STM32F7_QENCODER_SAMPLE_FDTS_32 - bool "fDTS/32" - -endchoice - -choice - depends on STM32F7_QENCODER_FILTER - prompt "Input channel event count" - default STM32F7_QENCODER_SAMPLE_EVENT_6 - -config STM32F7_QENCODER_SAMPLE_EVENT_1 - depends on STM32F7_QENCODER_SAMPLE_FDTS - bool "1" - -config STM32F7_QENCODER_SAMPLE_EVENT_2 - depends on STM32F7_QENCODER_SAMPLE_CKINT - bool "2" - -config STM32F7_QENCODER_SAMPLE_EVENT_4 - depends on STM32F7_QENCODER_SAMPLE_CKINT - bool "4" - -config STM32F7_QENCODER_SAMPLE_EVENT_5 - depends on STM32F7_QENCODER_SAMPLE_FDTS_16 || STM32F7_QENCODER_SAMPLE_FDTS_32 - bool "5" - -config STM32F7_QENCODER_SAMPLE_EVENT_6 - depends on !STM32F7_QENCODER_SAMPLE_FDTS && !STM32F7_QENCODER_SAMPLE_CKINT - bool "6" - -config STM32F7_QENCODER_SAMPLE_EVENT_8 - depends on !STM32F7_QENCODER_SAMPLE_FDTS - bool "8" - -endchoice - -endmenu - -menu "SAI Configuration" - depends on STM32F7_SAI - -choice - prompt "Operation mode" - default STM32F7_SAI_DMA - ---help--- - Select the operation mode the SAI driver should use. - -config STM32F7_SAI_POLLING - bool "Polling" - ---help--- - The SAI registers are polled for events. - -config STM32F7_SAI_INTERRUPTS - bool "Interrupt" - ---help--- - Select to enable interrupt driven SAI support. - -config STM32F7_SAI_DMA - bool "DMA" - ---help--- - Use DMA to improve SAI transfer performance. - -endchoice # Operation mode - -choice - prompt "SAI1 synchronization enable" - default STM32F7_SAI1_BOTH_ASYNC - depends on STM32F7_SAI1_A && STM32F7_SAI1_B - ---help--- - Select the synchronization mode of the SAI sub-blocks - -config STM32F7_SAI1_BOTH_ASYNC - bool "Both asynchronous" - -config STM32F7_SAI1_A_SYNC_WITH_B - bool "Block A is synchronous with Block B" - -config STM32F7_SAI1_B_SYNC_WITH_A - bool "Block B is synchronous with Block A" - -endchoice # SAI1 synchronization enable - -choice - prompt "SAI2 synchronization enable" - default STM32F7_SAI2_BOTH_ASYNC - depends on STM32F7_SAI2_A && STM32F7_SAI2_B - ---help--- - Select the synchronization mode of the SAI sub-blocks - -config STM32F7_SAI2_BOTH_ASYNC - bool "Both asynchronous" - -config STM32F7_SAI2_A_SYNC_WITH_B - bool "Block A is synchronous with Block B" - -config STM32F7_SAI2_B_SYNC_WITH_A - bool "Block B is synchronous with Block A" - -endchoice # SAI2 synchronization enable - -endmenu - -menuconfig STM32F7_FOC - bool "STM32 lower-half FOC support" - default n - select ARCH_IRQPRIO - select STM32F7_PWM_MULTICHAN - select STM32F7_PWM_LL_OPS - select STM32F7_ADC_LL_OPS - select STM32F7_ADC_CHANGE_SAMPLETIME - select STM32F7_ADC_NO_STARTUP_CONV - -if STM32F7_FOC - -config STM32F7_FOC_FOC0 - bool "FOC0 device (TIM1 for PWM modulation)" - default n - select STM32F7_FOC_USE_TIM1 - ---help--- - Enable support for FOC0 device that uses TIM1 for PWM modulation - -config STM32F7_FOC_FOC1 - bool "FOC1 device (TIM8 for PWM modulation)" - default n - select STM32F7_FOC_USE_TIM8 - ---help--- - Enable support for FOC1 device that uses TIM8 for PWM modulation - -choice - prompt "FOC ADC trigger selection" - default STM32F7_FOC_ADC_TRGO - -config STM32F7_FOC_ADC_CCR4 - bool "FOC uses CCR4 as ADC trigger" - ---help--- - This option uses the software frequency prescaler and is - not possible for 4-phase output. - -config STM32F7_FOC_ADC_TRGO - bool "FOC uses TRGO as ADC trigger" - depends on !STM32F7_FOC_FOC1 - select STM32F7_PWM_TRGO - ---help--- - This option allows you to use higher PWM frequency and works for 4-phase output. - It is not possible for ADC IPv1 if FOC1 enabled (no T8TRGO in JEXTSEL). - -endchoice # "FOC ADC trigger selection" - -if STM32F7_FOC_FOC0 - -choice - prompt "FOC0 device ADC selection" - default STM32F7_FOC_FOC0_ADC1 - -config STM32F7_FOC_FOC0_ADC1 - bool "FOC0 uses ADC1" - select STM32F7_FOC_USE_ADC1 - -config STM32F7_FOC_FOC0_ADC2 - bool "FOC0 uses ADC2" - select STM32F7_FOC_USE_ADC2 - -config STM32F7_FOC_FOC0_ADC3 - bool "FOC0 uses ADC3" - select STM32F7_FOC_USE_ADC3 - -endchoice # "FOC0 device ADC selection" - -endif # STM32F7_FOC_FOC0 - -if STM32F7_FOC_FOC1 - -choice - prompt "FOC1 device ADC selection" - default STM32F7_FOC_FOC1_ADC2 - -config STM32F7_FOC_FOC1_ADC1 - bool "FOC1 uses ADC1" - select STM32F7_FOC_USE_ADC1 - -config STM32F7_FOC_FOC1_ADC2 - bool "FOC1 uses ADC2" - select STM32F7_FOC_USE_ADC2 - -config STM32F7_FOC_FOC1_ADC3 - bool "FOC1 uses ADC3" - select STM32F7_FOC_USE_ADC3 - -endchoice # "FOC0 device ADC selection" - -endif # STM32F7_FOC_FOC1 - -config STM32F7_FOC_HAS_PWM_COMPLEMENTARY - bool "FOC PWM has complementary outputs" - default n - ---help--- - Enable complementary outputs for the FOC PWM (sometimes called 6-PWM mode) - -# hidden variables and automatic configuration - -config STM32F7_FOC_USE_TIM1 - bool - default n - select STM32F7_TIM1 - select STM32F7_TIM1_PWM - select STM32F7_TIM1_CHANNEL1 - select STM32F7_TIM1_CHANNEL2 - select STM32F7_TIM1_CHANNEL3 - select STM32F7_TIM1_CHANNEL4 if STM32F7_FOC_ADC_CCR4 - select STM32F7_TIM1_CH1OUT - select STM32F7_TIM1_CH2OUT - select STM32F7_TIM1_CH3OUT - select STM32F7_TIM1_CH4OUT if STM32F7_FOC_ADC_CCR4 - select STM32F7_TIM1_CH1NOUT if STM32F7_FOC_HAS_PWM_COMPLEMENTARY - select STM32F7_TIM1_CH2NOUT if STM32F7_FOC_HAS_PWM_COMPLEMENTARY - select STM32F7_TIM1_CH3NOUT if STM32F7_FOC_HAS_PWM_COMPLEMENTARY - ---help--- - The TIM1 generates PWM for the FOC - -config STM32F7_FOC_USE_TIM8 - bool - default n - select STM32F7_TIM8 - select STM32F7_TIM8_PWM - select STM32F7_TIM8_CHANNEL1 - select STM32F7_TIM8_CHANNEL2 - select STM32F7_TIM8_CHANNEL3 - select STM32F7_TIM8_CHANNEL4 if STM32F7_FOC_ADC_CCR4 - select STM32F7_TIM8_CH1OUT - select STM32F7_TIM8_CH2OUT - select STM32F7_TIM8_CH3OUT - select STM32F7_TIM8_CH4OUT if STM32F7_FOC_ADC_CCR4 - select STM32F7_TIM8_CH1NOUT if STM32F7_FOC_HAS_PWM_COMPLEMENTARY - select STM32F7_TIM8_CH2NOUT if STM32F7_FOC_HAS_PWM_COMPLEMENTARY - select STM32F7_TIM8_CH3NOUT if STM32F7_FOC_HAS_PWM_COMPLEMENTARY - ---help--- - The TIM8 generates PWM for the FOC - -config STM32F7_FOC_USE_ADC1 - bool - default n - select STM32F7_ADC1 - select STM32F7_ADC1_SCAN - select STM32F7_ADC1_JEXTSEL - -config STM32F7_FOC_USE_ADC2 - bool - default n - select STM32F7_ADC2 - select STM32F7_ADC2_SCAN - select STM32F7_ADC2_JEXTSEL - -config STM32F7_FOC_USE_ADC3 - bool - default n - select STM32F7_ADC3 - select STM32F7_ADC3_SCAN - select STM32F7_ADC3_JEXTSEL + select STM32_HAVE_FMC + select STM32_HAVE_RNG + select STM32_HAVE_SPI5 if !STM32F7_IO_CONFIG_V + select STM32_HAVE_SPI6 if !STM32F7_IO_CONFIG_V + select STM32_HAVE_SDMMC2 if !STM32F7_IO_CONFIG_V + select STM32_HAVE_CAN3 + select STM32_HAVE_DCMI + select STM32_HAVE_DSIHOST if !(STM32F7_IO_CONFIG_V || STM32F7_IO_CONFIG_Z) + select STM32_HAVE_LTDC + select STM32_HAVE_DMA2D + select STM32_HAVE_IP_DMA2D_M3M4_V1 + select STM32_HAVE_JPEG + select STM32_HAVE_CRYP + select STM32_HAVE_IP_CRYPTO_M3M4_V1 + select STM32_HAVE_HASH + select STM32_HAVE_DFSDM1 + select STM32_HAVE_CAN2 + select STM32_HAVE_SPI4 -endif #STM32F7_FOC endif # ARCH_CHIP_STM32F7 diff --git a/arch/arm/src/stm32f7/Make.defs b/arch/arm/src/stm32f7/Make.defs index 04f0514666b05..9a6d59e952187 100644 --- a/arch/arm/src/stm32f7/Make.defs +++ b/arch/arm/src/stm32f7/Make.defs @@ -26,12 +26,13 @@ # Common ARM and Cortex-M7 files include armv7-m/Make.defs +include common/stm32/Make.defs # Required STM32F7 files -CHIP_CSRCS = stm32_allocateheap.c stm32_exti_gpio.c stm32_gpio.c +CHIP_CSRCS += stm32_allocateheap.c stm32_exti_gpio.c stm32_gpio.c CHIP_CSRCS += stm32_irq.c stm32_lowputc.c stm32_rcc.c stm32_serial.c -CHIP_CSRCS += stm32_start.c stm32_capture.c stm32_uid.c stm32_waste.c +CHIP_CSRCS += stm32_start.c stm32_capture.c ifneq ($(CONFIG_SCHED_TICKLESS),y) CHIP_CSRCS += stm32_timerisr.c @@ -39,7 +40,7 @@ else CHIP_CSRCS += stm32_tickless.c endif -ifeq ($(CONFIG_STM32F7_PROGMEM),y) +ifeq ($(CONFIG_STM32_PROGMEM),y) CHIP_CSRCS += stm32_flash.c endif @@ -51,11 +52,11 @@ ifeq ($(CONFIG_ARMV7M_DTCM),y) CHIP_CSRCS += stm32_dtcm.c endif -ifeq ($(CONFIG_STM32F7_DMA),y) +ifeq ($(CONFIG_STM32_DMA),y) CHIP_CSRCS += stm32_dma.c endif -ifeq ($(CONFIG_STM32F7_FMC),y) +ifeq ($(CONFIG_STM32_FMC),y) CHIP_CSRCS += stm32_fmc.c endif @@ -66,11 +67,11 @@ CHIP_CSRCS += stm32_pminitialize.c endif endif -ifeq ($(CONFIG_STM32F7_PWR),y) +ifeq ($(CONFIG_STM32_PWR),y) CHIP_CSRCS += stm32_pwr.c stm32_exti_pwr.c endif -ifeq ($(CONFIG_STM32F7_RTC),y) +ifeq ($(CONFIG_STM32_RTC),y) CHIP_CSRCS += stm32_rtc.c ifeq ($(CONFIG_RTC_ALARM),y) CHIP_CSRCS += stm32_exti_alarm.c @@ -83,27 +84,27 @@ CHIP_CSRCS += stm32_rtc_lowerhalf.c endif endif -ifeq ($(filter y,$(CONFIG_STM32F7_IWDG) $(CONFIG_STM32F7_RTC_LSICLOCK)),y) +ifeq ($(filter y,$(CONFIG_STM32_IWDG) $(CONFIG_STM32_RTC_LSICLOCK)),y) CHIP_CSRCS += stm32_lsi.c endif -ifeq ($(CONFIG_STM32F7_RTC_LSECLOCK),y) +ifeq ($(CONFIG_STM32_RTC_LSECLOCK),y) CHIP_CSRCS += stm32_lse.c endif -ifeq ($(CONFIG_STM32F7_I2C),y) +ifeq ($(CONFIG_STM32_I2C),y) CHIP_CSRCS += stm32_i2c.c endif -ifeq ($(CONFIG_STM32F7_I2S),y) +ifeq ($(CONFIG_STM32_I2S),y) CHIP_CSRCS += stm32_i2s.c endif -ifeq ($(CONFIG_STM32F7_SPI),y) +ifeq ($(CONFIG_STM32_SPI),y) CHIP_CSRCS += stm32_spi.c endif -ifeq ($(CONFIG_STM32F7_SDMMC),y) +ifeq ($(CONFIG_STM32_SDMMC),y) CHIP_CSRCS += stm32_sdmmc.c endif @@ -122,25 +123,25 @@ endif endif endif -ifeq ($(CONFIG_STM32F7_TIM),y) +ifeq ($(CONFIG_STM32_TIM),y) CHIP_CSRCS += stm32_tim.c stm32_tim_lowerhalf.c endif -ifeq ($(CONFIG_STM32F7_ADC),y) +ifeq ($(CONFIG_STM32_ADC),y) CHIP_CSRCS += stm32_adc.c endif -ifeq ($(CONFIG_STM32F7_QUADSPI),y) +ifeq ($(CONFIG_STM32_QSPI),y) CHIP_CSRCS += stm32_qspi.c endif -ifeq ($(CONFIG_STM32F7_RTC),y) +ifeq ($(CONFIG_STM32_RTC),y) ifeq ($(CONFIG_RTC_ALARM),y) CHIP_CSRCS += stm32_exti_alarm.c endif endif -ifeq ($(CONFIG_STM32F7_ETHMAC),y) +ifeq ($(CONFIG_STM32_ETHMAC),y) CHIP_CSRCS += stm32_ethernet.c endif @@ -148,19 +149,19 @@ ifeq ($(CONFIG_DEBUG_FEATURES),y) CHIP_CSRCS += stm32_dumpgpio.c endif -ifeq ($(CONFIG_STM32F7_BBSRAM),y) +ifeq ($(CONFIG_STM32_BBSRAM),y) CHIP_CSRCS += stm32_bbsram.c endif -ifeq ($(CONFIG_STM32F7_RNG),y) +ifeq ($(CONFIG_STM32_RNG),y) CHIP_CSRCS += stm32_rng.c endif -ifeq ($(CONFIG_STM32F7_LTDC),y) +ifeq ($(CONFIG_STM32_LTDC),y) CHIP_CSRCS += stm32_ltdc.c endif -ifeq ($(CONFIG_STM32F7_DMA2D),y) +ifeq ($(CONFIG_STM32_DMA2D),y) CHIP_CSRCS += stm32_dma2d.c endif @@ -168,26 +169,26 @@ ifeq ($(CONFIG_SENSORS_QENCODER),y) CHIP_CSRCS += stm32_qencoder.c endif -ifeq ($(CONFIG_STM32F7_CAN_CHARDRIVER),y) +ifeq ($(CONFIG_STM32_CAN_CHARDRIVER),y) CHIP_CSRCS += stm32_can.c endif -ifeq ($(CONFIG_STM32F7_CAN_SOCKET),y) +ifeq ($(CONFIG_STM32_CAN_SOCKET),y) CHIP_CSRCS += stm32_can_sock.c endif -ifeq ($(CONFIG_STM32F7_SAI),y) +ifeq ($(CONFIG_STM32_SAI),y) CHIP_CSRCS += stm32_sai.c endif -ifeq ($(CONFIG_STM32F7_PWM),y) +ifeq ($(CONFIG_STM32_PWM),y) CHIP_CSRCS += stm32_pwm.c endif -ifeq ($(CONFIG_STM32F7_PULSECOUNT),y) +ifeq ($(CONFIG_STM32_PULSECOUNT),y) CHIP_CSRCS += stm32_pulsecount.c endif -ifeq ($(CONFIG_STM32F7_FOC),y) +ifeq ($(CONFIG_STM32_FOC),y) CHIP_CSRCS += stm32_foc.c endif diff --git a/arch/arm/src/stm32f7/hardware/stm32_adc.h b/arch/arm/src/stm32f7/hardware/stm32_adc.h index cabbd5921ef55..f8e8fb4423c48 100644 --- a/arch/arm/src/stm32f7/hardware/stm32_adc.h +++ b/arch/arm/src/stm32f7/hardware/stm32_adc.h @@ -30,10 +30,10 @@ #include #include "chip.h" -#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX) +#if defined(CONFIG_STM32_STM32F72XX) || defined(CONFIG_STM32_STM32F73XX) # include "hardware/stm32f72xx73xx_adc.h" -#elif defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) || \ - defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) +#elif defined(CONFIG_STM32_STM32F74XX) || defined(CONFIG_STM32_STM32F75XX) || \ + defined(CONFIG_STM32_STM32F76XX) || defined(CONFIG_STM32_STM32F77XX) # include "hardware/stm32f74xx77xx_adc.h" #else # error "Unsupported STM32 F7 sub family" diff --git a/arch/arm/src/stm32f7/hardware/stm32_can.h b/arch/arm/src/stm32f7/hardware/stm32_can.h index c5da101f134ac..8124ae8815f44 100644 --- a/arch/arm/src/stm32f7/hardware/stm32_can.h +++ b/arch/arm/src/stm32f7/hardware/stm32_can.h @@ -123,7 +123,7 @@ /* Register Addresses *******************************************************/ -#if defined(CONFIG_STM32F7_CAN1) +#if defined(CONFIG_STM32_CAN1) # define STM32_CAN1_MCR (STM32_CAN1_BASE+STM32_CAN_MCR_OFFSET) # define STM32_CAN1_MSR (STM32_CAN1_BASE+STM32_CAN_MSR_OFFSET) # define STM32_CAN1_TSR (STM32_CAN1_BASE+STM32_CAN_TSR_OFFSET) @@ -177,7 +177,7 @@ # define STM32_CAN1_FIR(b,i) (STM32_CAN1_BASE+STM32_CAN_FIR_OFFSET(b,i)) #endif -#if defined(CONFIG_STM32F7_CAN2) +#if defined(CONFIG_STM32_CAN2) # define STM32_CAN2_MCR (STM32_CAN2_BASE+STM32_CAN_MCR_OFFSET) # define STM32_CAN2_MSR (STM32_CAN2_BASE+STM32_CAN_MSR_OFFSET) # define STM32_CAN2_TSR (STM32_CAN2_BASE+STM32_CAN_TSR_OFFSET) @@ -231,7 +231,7 @@ # define STM32_CAN2_FIR(b,i) (STM32_CAN2_BASE+STM32_CAN_FIR_OFFSET(b,i)) #endif -#if defined(CONFIG_STM32F7_CAN3) +#if defined(CONFIG_STM32_CAN3) # define STM32_CAN3_MCR (STM32_CAN3_BASE+STM32_CAN_MCR_OFFSET) # define STM32_CAN3_MSR (STM32_CAN3_BASE+STM32_CAN_MSR_OFFSET) # define STM32_CAN3_TSR (STM32_CAN3_BASE+STM32_CAN_TSR_OFFSET) diff --git a/arch/arm/src/stm32f7/hardware/stm32_dbgmcu.h b/arch/arm/src/stm32f7/hardware/stm32_dbgmcu.h index 4bc19f87b6d8f..2603a97063a3f 100644 --- a/arch/arm/src/stm32f7/hardware/stm32_dbgmcu.h +++ b/arch/arm/src/stm32f7/hardware/stm32_dbgmcu.h @@ -30,11 +30,11 @@ #include #include "chip.h" -#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX) +#if defined(CONFIG_STM32_STM32F72XX) || defined(CONFIG_STM32_STM32F73XX) # include "hardware/stm32f72xx73xx_dbgmcu.h" -#elif defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) +#elif defined(CONFIG_STM32_STM32F74XX) || defined(CONFIG_STM32_STM32F75XX) # include "hardware/stm32f74xx75xx_dbgmcu.h" -#elif defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) +#elif defined(CONFIG_STM32_STM32F76XX) || defined(CONFIG_STM32_STM32F77XX) # include "hardware/stm32f76xx77xx_dbgmcu.h" #else # error "Unsupported STM32 F7 part" diff --git a/arch/arm/src/stm32f7/hardware/stm32_dma.h b/arch/arm/src/stm32f7/hardware/stm32_dma.h index 9df147e270441..1084640b37801 100644 --- a/arch/arm/src/stm32f7/hardware/stm32_dma.h +++ b/arch/arm/src/stm32f7/hardware/stm32_dma.h @@ -30,11 +30,11 @@ #include #include "chip.h" -#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX) +#if defined(CONFIG_STM32_STM32F72XX) || defined(CONFIG_STM32_STM32F73XX) # include "hardware/stm32f72xx73xx_dma.h" -#elif defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) +#elif defined(CONFIG_STM32_STM32F74XX) || defined(CONFIG_STM32_STM32F75XX) # include "hardware/stm32f74xx75xx_dma.h" -#elif defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) +#elif defined(CONFIG_STM32_STM32F76XX) || defined(CONFIG_STM32_STM32F77XX) # include "hardware/stm32f76xx77xx_dma.h" #else # error "Unsupported STM32 F7 part" diff --git a/arch/arm/src/stm32f7/hardware/stm32_ethernet.h b/arch/arm/src/stm32f7/hardware/stm32_ethernet.h index ff9a5be351cd6..b2e403ca83d32 100644 --- a/arch/arm/src/stm32f7/hardware/stm32_ethernet.h +++ b/arch/arm/src/stm32f7/hardware/stm32_ethernet.h @@ -33,8 +33,8 @@ * families */ -#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) || \ - defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) +#if defined(CONFIG_STM32_STM32F74XX) || defined(CONFIG_STM32_STM32F75XX) || \ + defined(CONFIG_STM32_STM32F76XX) || defined(CONFIG_STM32_STM32F77XX) /**************************************************************************** * Pre-processor Definitions @@ -810,7 +810,7 @@ struct eth_txdesc_s /* Enhanced DMA descriptor words with time stamp */ -#ifdef CONFIG_STM32F7_ETH_ENHANCEDDESC +#ifdef CONFIG_STM32_ETH_ENHANCEDDESC volatile uint32_t tdes4; /* Reserved */ volatile uint32_t tdes5; /* Reserved */ volatile uint32_t tdes6; /* Time Stamp Low value for transmit and receive */ @@ -829,7 +829,7 @@ struct eth_rxdesc_s /* Enhanced DMA descriptor words with time stamp and PTP support */ -#ifdef CONFIG_STM32F7_ETH_ENHANCEDDESC +#ifdef CONFIG_STM32_ETH_ENHANCEDDESC volatile uint32_t rdes4; /* Extended status for PTP receive descriptor */ volatile uint32_t rdes5; /* Reserved */ volatile uint32_t rdes6; /* Time Stamp Low value for transmit and receive */ @@ -842,5 +842,5 @@ struct eth_rxdesc_s ****************************************************************************/ #endif /* __ASSEMBLY__ */ -#endif /* CONFIG_STM32F7_STM32F74XX || CONFIG_STM32F7_STM32F75XX || CONFIG_STM32F7_STM32F76XX || CONFIG_STM32F7_STM32F77XX */ +#endif /* CONFIG_STM32_STM32F74XX || CONFIG_STM32_STM32F75XX || CONFIG_STM32_STM32F76XX || CONFIG_STM32_STM32F77XX */ #endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32_ETHERNET_H */ diff --git a/arch/arm/src/stm32f7/hardware/stm32_exti.h b/arch/arm/src/stm32f7/hardware/stm32_exti.h index b846f19c0f837..62fe35128bc8c 100644 --- a/arch/arm/src/stm32f7/hardware/stm32_exti.h +++ b/arch/arm/src/stm32f7/hardware/stm32_exti.h @@ -34,9 +34,9 @@ * families */ -#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX) || \ - defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) || \ - defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) +#if defined(CONFIG_STM32_STM32F72XX) || defined(CONFIG_STM32_STM32F73XX) || \ + defined(CONFIG_STM32_STM32F74XX) || defined(CONFIG_STM32_STM32F75XX) || \ + defined(CONFIG_STM32_STM32F76XX) || defined(CONFIG_STM32_STM32F77XX) /**************************************************************************** * Pre-processor Definitions @@ -116,5 +116,5 @@ #define EXTI_PR_SHIFT (0) /* Bits 0-X: Pending bit for all lines */ #define EXTI_PR_MASK STM32_EXTI_MASK -#endif /* CONFIG_STM32F7_STM32F74XX || CONFIG_STM32F7_STM32F75XX || CONFIG_STM32F7_STM32F76XX || CONFIG_STM32F7_STM32F77XX */ +#endif /* CONFIG_STM32_STM32F74XX || CONFIG_STM32_STM32F75XX || CONFIG_STM32_STM32F76XX || CONFIG_STM32_STM32F77XX */ #endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32_EXTI_H */ diff --git a/arch/arm/src/stm32f7/hardware/stm32_flash.h b/arch/arm/src/stm32f7/hardware/stm32_flash.h index 37551dde1b822..79050bf7c7bab 100644 --- a/arch/arm/src/stm32f7/hardware/stm32_flash.h +++ b/arch/arm/src/stm32f7/hardware/stm32_flash.h @@ -30,11 +30,11 @@ #include #include "chip.h" -#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX) +#if defined(CONFIG_STM32_STM32F72XX) || defined(CONFIG_STM32_STM32F73XX) # include "hardware/stm32f72xx73xx_flash.h" -#elif defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) +#elif defined(CONFIG_STM32_STM32F74XX) || defined(CONFIG_STM32_STM32F75XX) # include "hardware/stm32f74xx75xx_flash.h" -#elif defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) +#elif defined(CONFIG_STM32_STM32F76XX) || defined(CONFIG_STM32_STM32F77XX) # include "hardware/stm32f76xx77xx_flash.h" #else # error "Unsupported STM32 F7 part" diff --git a/arch/arm/src/stm32f7/hardware/stm32_gpio.h b/arch/arm/src/stm32f7/hardware/stm32_gpio.h index 9449df0fa0694..03f642dac61fa 100644 --- a/arch/arm/src/stm32f7/hardware/stm32_gpio.h +++ b/arch/arm/src/stm32f7/hardware/stm32_gpio.h @@ -30,11 +30,11 @@ #include #include "chip.h" -#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX) +#if defined(CONFIG_STM32_STM32F72XX) || defined(CONFIG_STM32_STM32F73XX) # include "hardware/stm32f72xx73xx_gpio.h" -#elif defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) +#elif defined(CONFIG_STM32_STM32F74XX) || defined(CONFIG_STM32_STM32F75XX) # include "hardware/stm32f74xx75xx_gpio.h" -#elif defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) +#elif defined(CONFIG_STM32_STM32F76XX) || defined(CONFIG_STM32_STM32F77XX) # include "hardware/stm32f76xx77xx_gpio.h" #else # error "Unsupported STM32 F7 part" diff --git a/arch/arm/src/stm32f7/hardware/stm32_i2c.h b/arch/arm/src/stm32f7/hardware/stm32_i2c.h index 15456f503b3e1..bacc9e367e8b4 100644 --- a/arch/arm/src/stm32f7/hardware/stm32_i2c.h +++ b/arch/arm/src/stm32f7/hardware/stm32_i2c.h @@ -30,9 +30,9 @@ #include #include "chip.h" -#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX) || \ - defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) || \ - defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) +#if defined(CONFIG_STM32_STM32F72XX) || defined(CONFIG_STM32_STM32F73XX) || \ + defined(CONFIG_STM32_STM32F74XX) || defined(CONFIG_STM32_STM32F75XX) || \ + defined(CONFIG_STM32_STM32F76XX) || defined(CONFIG_STM32_STM32F77XX) # include "hardware/stm32f74xx77xx_i2c.h" #else # error "Unsupported STM32 F7 sub family" diff --git a/arch/arm/src/stm32f7/hardware/stm32_memorymap.h b/arch/arm/src/stm32f7/hardware/stm32_memorymap.h index fe51a5ccc2420..57a9b1298f63a 100644 --- a/arch/arm/src/stm32f7/hardware/stm32_memorymap.h +++ b/arch/arm/src/stm32f7/hardware/stm32_memorymap.h @@ -30,11 +30,11 @@ #include #include "chip.h" -#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX) +#if defined(CONFIG_STM32_STM32F72XX) || defined(CONFIG_STM32_STM32F73XX) # include "hardware/stm32f72xx73xx_memorymap.h" -#elif defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) +#elif defined(CONFIG_STM32_STM32F74XX) || defined(CONFIG_STM32_STM32F75XX) # include "hardware/stm32f74xx75xx_memorymap.h" -#elif defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) +#elif defined(CONFIG_STM32_STM32F76XX) || defined(CONFIG_STM32_STM32F77XX) # include "hardware/stm32f76xx77xx_memorymap.h" #else # error "Unsupported STM32 F7 memory map" diff --git a/arch/arm/src/stm32f7/hardware/stm32_pinmap.h b/arch/arm/src/stm32f7/hardware/stm32_pinmap.h index dad7c1251f86d..5c10f75322c73 100644 --- a/arch/arm/src/stm32f7/hardware/stm32_pinmap.h +++ b/arch/arm/src/stm32f7/hardware/stm32_pinmap.h @@ -30,11 +30,11 @@ #include #include "chip.h" -#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX) +#if defined(CONFIG_STM32_STM32F72XX) || defined(CONFIG_STM32_STM32F73XX) # include "hardware/stm32f72xx73xx_pinmap.h" -#elif defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) +#elif defined(CONFIG_STM32_STM32F74XX) || defined(CONFIG_STM32_STM32F75XX) # include "hardware/stm32f74xx75xx_pinmap.h" -#elif defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) +#elif defined(CONFIG_STM32_STM32F76XX) || defined(CONFIG_STM32_STM32F77XX) # include "hardware/stm32f76xx77xx_pinmap.h" #else # error "Unsupported STM32 F7 Pin map" diff --git a/arch/arm/src/stm32f7/hardware/stm32_pwr.h b/arch/arm/src/stm32f7/hardware/stm32_pwr.h index 9eff00fa4929b..09792a2458dfd 100644 --- a/arch/arm/src/stm32f7/hardware/stm32_pwr.h +++ b/arch/arm/src/stm32f7/hardware/stm32_pwr.h @@ -30,11 +30,11 @@ #include #include "chip.h" -#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX) +#if defined(CONFIG_STM32_STM32F72XX) || defined(CONFIG_STM32_STM32F73XX) # include "hardware/stm32f72xx73xx_pwr.h" -#elif defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) +#elif defined(CONFIG_STM32_STM32F74XX) || defined(CONFIG_STM32_STM32F75XX) # include "hardware/stm32f74xx75xx_pwr.h" -#elif defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) +#elif defined(CONFIG_STM32_STM32F76XX) || defined(CONFIG_STM32_STM32F77XX) # include "hardware/stm32f76xx77xx_pwr.h" #else # error "Unsupported STM32 F7 part" diff --git a/arch/arm/src/stm32f7/hardware/stm32_qspi.h b/arch/arm/src/stm32f7/hardware/stm32_qspi.h index 31cf04e853476..b857ca463b5ec 100644 --- a/arch/arm/src/stm32f7/hardware/stm32_qspi.h +++ b/arch/arm/src/stm32f7/hardware/stm32_qspi.h @@ -38,8 +38,8 @@ /* General Characteristics **************************************************/ -#define STM32F7_QSPI_MINBITS 8 /* Minimum word width */ -#define STM32F7_QSPI_MAXBITS 32 /* Maximum word width */ +#define STM32_QSPI_MINBITS 8 /* Minimum word width */ +#define STM32_QSPI_MAXBITS 32 /* Maximum word width */ /* QSPI register offsets ****************************************************/ diff --git a/arch/arm/src/stm32f7/hardware/stm32_rcc.h b/arch/arm/src/stm32f7/hardware/stm32_rcc.h index bc41cad8beb99..61a34dd8460b5 100644 --- a/arch/arm/src/stm32f7/hardware/stm32_rcc.h +++ b/arch/arm/src/stm32f7/hardware/stm32_rcc.h @@ -30,11 +30,11 @@ #include #include "chip.h" -#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX) +#if defined(CONFIG_STM32_STM32F72XX) || defined(CONFIG_STM32_STM32F73XX) # include "hardware/stm32f72xx73xx_rcc.h" -#elif defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) +#elif defined(CONFIG_STM32_STM32F74XX) || defined(CONFIG_STM32_STM32F75XX) # include "hardware/stm32f74xx75xx_rcc.h" -#elif defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) +#elif defined(CONFIG_STM32_STM32F76XX) || defined(CONFIG_STM32_STM32F77XX) # include "hardware/stm32f76xx77xx_rcc.h" #else # error "Unsupported STM32 F7 part" diff --git a/arch/arm/src/stm32f7/hardware/stm32_sai.h b/arch/arm/src/stm32f7/hardware/stm32_sai.h index c71d7adc87ff0..b93784989026a 100644 --- a/arch/arm/src/stm32f7/hardware/stm32_sai.h +++ b/arch/arm/src/stm32f7/hardware/stm32_sai.h @@ -36,67 +36,67 @@ /* Register Offsets *********************************************************/ -#define STM32F7_SAI_GCR_OFFSET 0x0000 /* SAI Global Configuration Register */ +#define STM32_SAI_GCR_OFFSET 0x0000 /* SAI Global Configuration Register */ -#define STM32F7_SAI_A_OFFSET 0x0004 -#define STM32F7_SAI_B_OFFSET 0x0024 +#define STM32_SAI_A_OFFSET 0x0004 +#define STM32_SAI_B_OFFSET 0x0024 -#define STM32F7_SAI_CR1_OFFSET 0x0000 /* SAI Configuration Register 1 A */ -#define STM32F7_SAI_CR2_OFFSET 0x0004 /* SAI Configuration Register 2 A */ -#define STM32F7_SAI_FRCR_OFFSET 0x0008 /* SAI Frame Configuration Register A */ -#define STM32F7_SAI_SLOTR_OFFSET 0x000c /* SAI Slot Register A */ -#define STM32F7_SAI_IM_OFFSET 0x0010 /* SAI Interrupt Mask Register 2 A */ -#define STM32F7_SAI_SR_OFFSET 0x0014 /* SAI Status Register A */ -#define STM32F7_SAI_CLRFR_OFFSET 0x0018 /* SAI Clear Flag Register A */ -#define STM32F7_SAI_DR_OFFSET 0x001c /* SAI Data Register A */ +#define STM32_SAI_CR1_OFFSET 0x0000 /* SAI Configuration Register 1 A */ +#define STM32_SAI_CR2_OFFSET 0x0004 /* SAI Configuration Register 2 A */ +#define STM32_SAI_FRCR_OFFSET 0x0008 /* SAI Frame Configuration Register A */ +#define STM32_SAI_SLOTR_OFFSET 0x000c /* SAI Slot Register A */ +#define STM32_SAI_IM_OFFSET 0x0010 /* SAI Interrupt Mask Register 2 A */ +#define STM32_SAI_SR_OFFSET 0x0014 /* SAI Status Register A */ +#define STM32_SAI_CLRFR_OFFSET 0x0018 /* SAI Clear Flag Register A */ +#define STM32_SAI_DR_OFFSET 0x001c /* SAI Data Register A */ /* Register Addresses *******************************************************/ -#define STM32F7_SAI1_GCR (STM32_SAI1_BASE+STM32F7_SAI_GCR_OFFSET) - -#define STM32F7_SAI1_A_BASE (STM32_SAI1_BASE+STM32F7_SAI_A_OFFSET) -#define STM32F7_SAI1_B_BASE (STM32_SAI1_BASE+STM32F7_SAI_B_OFFSET) - -#define STM32F7_SAI1_ACR1 (STM32F7_SAI1_A_BASE+STM32F7_SAI_CR1_OFFSET) -#define STM32F7_SAI1_ACR2 (STM32F7_SAI1_A_BASE+STM32F7_SAI_CR2_OFFSET) -#define STM32F7_SAI1_AFRCR (STM32F7_SAI1_A_BASE+STM32F7_SAI_FRCR_OFFSET) -#define STM32F7_SAI1_ASLOTR (STM32F7_SAI1_A_BASE+STM32F7_SAI_SLOTR_OFFSET) -#define STM32F7_SAI1_AIM (STM32F7_SAI1_A_BASE+STM32F7_SAI_IM_OFFSET) -#define STM32F7_SAI1_ASR (STM32F7_SAI1_A_BASE+STM32F7_SAI_SR_OFFSET) -#define STM32F7_SAI1_ACLRFR (STM32F7_SAI1_A_BASE+STM32F7_SAI_CLRFR_OFFSET) -#define STM32F7_SAI1_ADR (STM32F7_SAI1_A_BASE+STM32F7_SAI_DR_OFFSET) - -#define STM32F7_SAI1_BCR1 (STM32F7_SAI1_B_BASE+STM32F7_SAI_CR1_OFFSET) -#define STM32F7_SAI1_BCR2 (STM32F7_SAI1_B_BASE+STM32F7_SAI_CR2_OFFSET) -#define STM32F7_SAI1_BFRCR (STM32F7_SAI1_B_BASE+STM32F7_SAI_FRCR_OFFSET) -#define STM32F7_SAI1_BSLOTR (STM32F7_SAI1_B_BASE+STM32F7_SAI_SLOTR_OFFSET) -#define STM32F7_SAI1_BIM (STM32F7_SAI1_B_BASE+STM32F7_SAI_IM_OFFSET) -#define STM32F7_SAI1_BSR (STM32F7_SAI1_B_BASE+STM32F7_SAI_SR_OFFSET) -#define STM32F7_SAI1_BCLRFR (STM32F7_SAI1_B_BASE+STM32F7_SAI_CLRFR_OFFSET) -#define STM32F7_SAI1_BDR (STM32F7_SAI1_B_BASE+STM32F7_SAI_DR_OFFSET) - -#define STM32F7_SAI2_GCR (STM32_SAI2_BASE+STM32F7_SAI_GCR_OFFSET) - -#define STM32F7_SAI2_A_BASE (STM32_SAI2_BASE+STM32F7_SAI_A_OFFSET) -#define STM32F7_SAI2_B_BASE (STM32_SAI2_BASE+STM32F7_SAI_B_OFFSET) - -#define STM32F7_SAI2_ACR1 (STM32F7_SAI2_A_BASE+STM32F7_SAI_CR1_OFFSET) -#define STM32F7_SAI2_ACR2 (STM32F7_SAI2_A_BASE+STM32F7_SAI_CR2_OFFSET) -#define STM32F7_SAI2_AFRCR (STM32F7_SAI2_A_BASE+STM32F7_SAI_FRCR_OFFSET) -#define STM32F7_SAI2_ASLOTR (STM32F7_SAI2_A_BASE+STM32F7_SAI_SLOTR_OFFSET) -#define STM32F7_SAI2_AIM (STM32F7_SAI2_A_BASE+STM32F7_SAI_IM_OFFSET) -#define STM32F7_SAI2_ASR (STM32F7_SAI2_A_BASE+STM32F7_SAI_SR_OFFSET) -#define STM32F7_SAI2_ACLRFR (STM32F7_SAI2_A_BASE+STM32F7_SAI_CLRFR_OFFSET) -#define STM32F7_SAI2_ADR (STM32F7_SAI2_A_BASE+STM32F7_SAI_DR_OFFSET) - -#define STM32F7_SAI2_BCR1 (STM32F7_SAI2_B_BASE+STM32F7_SAI_CR1_OFFSET) -#define STM32F7_SAI2_BCR2 (STM32F7_SAI2_B_BASE+STM32F7_SAI_CR2_OFFSET) -#define STM32F7_SAI2_BFRCR (STM32F7_SAI2_B_BASE+STM32F7_SAI_FRCR_OFFSET) -#define STM32F7_SAI2_BSLOTR (STM32F7_SAI2_B_BASE+STM32F7_SAI_SLOTR_OFFSET) -#define STM32F7_SAI2_BIM (STM32F7_SAI2_B_BASE+STM32F7_SAI_IM_OFFSET) -#define STM32F7_SAI2_BSR (STM32F7_SAI2_B_BASE+STM32F7_SAI_SR_OFFSET) -#define STM32F7_SAI2_BCLRFR (STM32F7_SAI2_B_BASE+STM32F7_SAI_CLRFR_OFFSET) -#define STM32F7_SAI2_BDR (STM32F7_SAI2_B_BASE+STM32F7_SAI_DR_OFFSET) +#define STM32_SAI1_GCR (STM32_SAI1_BASE+STM32_SAI_GCR_OFFSET) + +#define STM32_SAI1_A_BASE (STM32_SAI1_BASE+STM32_SAI_A_OFFSET) +#define STM32_SAI1_B_BASE (STM32_SAI1_BASE+STM32_SAI_B_OFFSET) + +#define STM32_SAI1_ACR1 (STM32_SAI1_A_BASE+STM32_SAI_CR1_OFFSET) +#define STM32_SAI1_ACR2 (STM32_SAI1_A_BASE+STM32_SAI_CR2_OFFSET) +#define STM32_SAI1_AFRCR (STM32_SAI1_A_BASE+STM32_SAI_FRCR_OFFSET) +#define STM32_SAI1_ASLOTR (STM32_SAI1_A_BASE+STM32_SAI_SLOTR_OFFSET) +#define STM32_SAI1_AIM (STM32_SAI1_A_BASE+STM32_SAI_IM_OFFSET) +#define STM32_SAI1_ASR (STM32_SAI1_A_BASE+STM32_SAI_SR_OFFSET) +#define STM32_SAI1_ACLRFR (STM32_SAI1_A_BASE+STM32_SAI_CLRFR_OFFSET) +#define STM32_SAI1_ADR (STM32_SAI1_A_BASE+STM32_SAI_DR_OFFSET) + +#define STM32_SAI1_BCR1 (STM32_SAI1_B_BASE+STM32_SAI_CR1_OFFSET) +#define STM32_SAI1_BCR2 (STM32_SAI1_B_BASE+STM32_SAI_CR2_OFFSET) +#define STM32_SAI1_BFRCR (STM32_SAI1_B_BASE+STM32_SAI_FRCR_OFFSET) +#define STM32_SAI1_BSLOTR (STM32_SAI1_B_BASE+STM32_SAI_SLOTR_OFFSET) +#define STM32_SAI1_BIM (STM32_SAI1_B_BASE+STM32_SAI_IM_OFFSET) +#define STM32_SAI1_BSR (STM32_SAI1_B_BASE+STM32_SAI_SR_OFFSET) +#define STM32_SAI1_BCLRFR (STM32_SAI1_B_BASE+STM32_SAI_CLRFR_OFFSET) +#define STM32_SAI1_BDR (STM32_SAI1_B_BASE+STM32_SAI_DR_OFFSET) + +#define STM32_SAI2_GCR (STM32_SAI2_BASE+STM32_SAI_GCR_OFFSET) + +#define STM32_SAI2_A_BASE (STM32_SAI2_BASE+STM32_SAI_A_OFFSET) +#define STM32_SAI2_B_BASE (STM32_SAI2_BASE+STM32_SAI_B_OFFSET) + +#define STM32_SAI2_ACR1 (STM32_SAI2_A_BASE+STM32_SAI_CR1_OFFSET) +#define STM32_SAI2_ACR2 (STM32_SAI2_A_BASE+STM32_SAI_CR2_OFFSET) +#define STM32_SAI2_AFRCR (STM32_SAI2_A_BASE+STM32_SAI_FRCR_OFFSET) +#define STM32_SAI2_ASLOTR (STM32_SAI2_A_BASE+STM32_SAI_SLOTR_OFFSET) +#define STM32_SAI2_AIM (STM32_SAI2_A_BASE+STM32_SAI_IM_OFFSET) +#define STM32_SAI2_ASR (STM32_SAI2_A_BASE+STM32_SAI_SR_OFFSET) +#define STM32_SAI2_ACLRFR (STM32_SAI2_A_BASE+STM32_SAI_CLRFR_OFFSET) +#define STM32_SAI2_ADR (STM32_SAI2_A_BASE+STM32_SAI_DR_OFFSET) + +#define STM32_SAI2_BCR1 (STM32_SAI2_B_BASE+STM32_SAI_CR1_OFFSET) +#define STM32_SAI2_BCR2 (STM32_SAI2_B_BASE+STM32_SAI_CR2_OFFSET) +#define STM32_SAI2_BFRCR (STM32_SAI2_B_BASE+STM32_SAI_FRCR_OFFSET) +#define STM32_SAI2_BSLOTR (STM32_SAI2_B_BASE+STM32_SAI_SLOTR_OFFSET) +#define STM32_SAI2_BIM (STM32_SAI2_B_BASE+STM32_SAI_IM_OFFSET) +#define STM32_SAI2_BSR (STM32_SAI2_B_BASE+STM32_SAI_SR_OFFSET) +#define STM32_SAI2_BCLRFR (STM32_SAI2_B_BASE+STM32_SAI_CLRFR_OFFSET) +#define STM32_SAI2_BDR (STM32_SAI2_B_BASE+STM32_SAI_DR_OFFSET) /* Register Bitfield Definitions ********************************************/ diff --git a/arch/arm/src/stm32f7/hardware/stm32_sdmmc.h b/arch/arm/src/stm32f7/hardware/stm32_sdmmc.h index 563818cc6c2b6..59f1f7ad3cb42 100644 --- a/arch/arm/src/stm32f7/hardware/stm32_sdmmc.h +++ b/arch/arm/src/stm32f7/hardware/stm32_sdmmc.h @@ -30,9 +30,9 @@ #include #include "chip.h" -#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX) || \ - defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) || \ - defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) +#if defined(CONFIG_STM32_STM32F72XX) || defined(CONFIG_STM32_STM32F73XX) || \ + defined(CONFIG_STM32_STM32F74XX) || defined(CONFIG_STM32_STM32F75XX) || \ + defined(CONFIG_STM32_STM32F76XX) || defined(CONFIG_STM32_STM32F77XX) #else # error "Unsupported STM32 F7 part" #endif diff --git a/arch/arm/src/stm32f7/hardware/stm32_spi.h b/arch/arm/src/stm32f7/hardware/stm32_spi.h index 1411319566d4b..94fe7c794cfe3 100644 --- a/arch/arm/src/stm32f7/hardware/stm32_spi.h +++ b/arch/arm/src/stm32f7/hardware/stm32_spi.h @@ -30,10 +30,10 @@ #include #include "chip.h" -#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX) +#if defined(CONFIG_STM32_STM32F72XX) || defined(CONFIG_STM32_STM32F73XX) # include "hardware/stm32f72xx73xx_spi.h" -#elif defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) || \ - defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) +#elif defined(CONFIG_STM32_STM32F74XX) || defined(CONFIG_STM32_STM32F75XX) || \ + defined(CONFIG_STM32_STM32F76XX) || defined(CONFIG_STM32_STM32F77XX) # include "hardware/stm32f74xx77xx_spi.h" #else # error "Unsupported STM32 F7 sub family" diff --git a/arch/arm/src/stm32f7/hardware/stm32_syscfg.h b/arch/arm/src/stm32f7/hardware/stm32_syscfg.h index 5112e47413064..18ff0709820ed 100644 --- a/arch/arm/src/stm32f7/hardware/stm32_syscfg.h +++ b/arch/arm/src/stm32f7/hardware/stm32_syscfg.h @@ -30,11 +30,11 @@ #include #include "chip.h" -#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX) +#if defined(CONFIG_STM32_STM32F72XX) || defined(CONFIG_STM32_STM32F73XX) # include "hardware/stm32f72xx73xx_syscfg.h" -#elif defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) +#elif defined(CONFIG_STM32_STM32F74XX) || defined(CONFIG_STM32_STM32F75XX) # include "hardware/stm32f74xx75xx_syscfg.h" -#elif defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) +#elif defined(CONFIG_STM32_STM32F76XX) || defined(CONFIG_STM32_STM32F77XX) # include "hardware/stm32f76xx77xx_syscfg.h" #else # error "Unsupported STM32 F7 part" diff --git a/arch/arm/src/stm32f7/hardware/stm32_tim.h b/arch/arm/src/stm32f7/hardware/stm32_tim.h index 46ffb0f4b1186..6dfc200978cb5 100644 --- a/arch/arm/src/stm32f7/hardware/stm32_tim.h +++ b/arch/arm/src/stm32f7/hardware/stm32_tim.h @@ -30,11 +30,11 @@ #include #include "chip.h" -#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX) +#if defined(CONFIG_STM32_STM32F72XX) || defined(CONFIG_STM32_STM32F73XX) # include "hardware/stm32f72xx73xx_tim.h" -#elif defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) +#elif defined(CONFIG_STM32_STM32F74XX) || defined(CONFIG_STM32_STM32F75XX) # include "hardware/stm32f74xx75xx_tim.h" -#elif defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) +#elif defined(CONFIG_STM32_STM32F76XX) || defined(CONFIG_STM32_STM32F77XX) # include "hardware/stm32f76xx77xx_tim.h" #else # error "Unsupported STM32 F7 sub family" diff --git a/arch/arm/src/stm32f7/hardware/stm32_uart.h b/arch/arm/src/stm32f7/hardware/stm32_uart.h index 4ef7a625794d5..0cd6b9c8d9663 100644 --- a/arch/arm/src/stm32f7/hardware/stm32_uart.h +++ b/arch/arm/src/stm32f7/hardware/stm32_uart.h @@ -30,10 +30,10 @@ #include #include "chip.h" -#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX) +#if defined(CONFIG_STM32_STM32F72XX) || defined(CONFIG_STM32_STM32F73XX) # include "hardware/stm32f72xx73xx_uart.h" -#elif defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) || \ - defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) +#elif defined(CONFIG_STM32_STM32F74XX) || defined(CONFIG_STM32_STM32F75XX) || \ + defined(CONFIG_STM32_STM32F76XX) || defined(CONFIG_STM32_STM32F77XX) # include "hardware/stm32f74xx77xx_uart.h" #else # error "Unsupported STM32 F7 part" diff --git a/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_adc.h b/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_adc.h index e02cfef5ecfca..0c529af4b75d0 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_adc.h +++ b/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_adc.h @@ -64,7 +64,7 @@ /* Register Addresses *******************************************************/ -#if STM32F7_NADC > 0 +#if STM32_NADC > 0 # define STM32_ADC1_SR (STM32_ADC1_BASE+STM32_ADC_SR_OFFSET) # define STM32_ADC1_CR1 (STM32_ADC1_BASE+STM32_ADC_CR1_OFFSET) # define STM32_ADC1_CR2 (STM32_ADC1_BASE+STM32_ADC_CR2_OFFSET) @@ -87,7 +87,7 @@ # define STM32_ADC1_DR (STM32_ADC1_BASE+STM32_ADC_DR_OFFSET) #endif -#if STM32F7_NADC > 1 +#if STM32_NADC > 1 # define STM32_ADC2_SR (STM32_ADC2_BASE+STM32_ADC_SR_OFFSET) # define STM32_ADC2_CR1 (STM32_ADC2_BASE+STM32_ADC_CR1_OFFSET) # define STM32_ADC2_CR2 (STM32_ADC2_BASE+STM32_ADC_CR2_OFFSET) @@ -110,7 +110,7 @@ # define STM32_ADC2_DR (STM32_ADC2_BASE+STM32_ADC_DR_OFFSET) #endif -#if STM32F7_NADC > 2 +#if STM32_NADC > 2 # define STM32_ADC3_SR (STM32_ADC3_BASE+STM32_ADC_SR_OFFSET) # define STM32_ADC3_CR1 (STM32_ADC3_BASE+STM32_ADC_CR1_OFFSET) # define STM32_ADC3_CR2 (STM32_ADC3_BASE+STM32_ADC_CR2_OFFSET) diff --git a/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_dma.h b/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_dma.h index 7347b6b06d221..e0b4f0d71fee6 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_dma.h +++ b/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_dma.h @@ -29,7 +29,7 @@ #include -#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX) +#if defined(CONFIG_STM32_STM32F72XX) || defined(CONFIG_STM32_STM32F73XX) /**************************************************************************** * Pre-processor Definitions @@ -539,5 +539,5 @@ #define DMAMAP_SDMMC2_1 STM32_DMA_MAP(DMA2,DMA_STREAM0,DMA_CHAN11) #define DMAMAP_SDMMC2_2 STM32_DMA_MAP(DMA2,DMA_STREAM5,DMA_CHAN11) -#endif /* CONFIG_STM32F7_STM32F72XX || CONFIG_STM32F7_STM32F73XX */ +#endif /* CONFIG_STM32_STM32F72XX || CONFIG_STM32_STM32F73XX */ #endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F72XX73XX_DMA_H */ diff --git a/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_flash.h b/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_flash.h index a7596397397b4..e24ebcdafbc9c 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_flash.h +++ b/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_flash.h @@ -29,10 +29,10 @@ /* Flash size is known from the chip selection: * - * When CONFIG_STM32F7_FLASH_OVERRIDE_DEFAULT is set the - * CONFIG_STM32F7_FLASH_CONFIG_x selects the default FLASH size based on + * When CONFIG_STM32_FLASH_OVERRIDE_DEFAULT is set the + * CONFIG_STM32_FLASH_CONFIG_x selects the default FLASH size based on * the chip part number. - * This value can be overridden with CONFIG_STM32F7_FLASH_OVERRIDE_x + * This value can be overridden with CONFIG_STM32_FLASH_OVERRIDE_x * * Parts STM32F72xxC have 256Kb of FLASH * Parts STM32F72xxE have 512Kb of FLASH @@ -44,38 +44,38 @@ #define _K(x) ((x)*1024) -#if !defined(CONFIG_STM32F7_FLASH_OVERRIDE_DEFAULT) && \ - !defined(CONFIG_STM32F7_FLASH_OVERRIDE_E) && \ - !defined(CONFIG_STM32F7_FLASH_OVERRIDE_C) && \ - !defined(CONFIG_STM32F7_FLASH_CONFIG_E) && \ - !defined(CONFIG_STM32F7_FLASH_CONFIG_C) -# define CONFIG_STM32F7_FLASH_OVERRIDE_C +#if !defined(CONFIG_STM32_FLASH_OVERRIDE_DEFAULT) && \ + !defined(CONFIG_STM32_FLASH_OVERRIDE_E) && \ + !defined(CONFIG_STM32_FLASH_OVERRIDE_C) && \ + !defined(CONFIG_STM32_FLASH_CONFIG_E) && \ + !defined(CONFIG_STM32_FLASH_CONFIG_C) +# define CONFIG_STM32_FLASH_OVERRIDE_C # warning "Flash size not defined defaulting to 256KiB (C)" #endif -#if !defined(CONFIG_STM32F7_FLASH_OVERRIDE_DEFAULT) +#if !defined(CONFIG_STM32_FLASH_OVERRIDE_DEFAULT) -# undef CONFIG_STM32F7_FLASH_CONFIG_C -# undef CONFIG_STM32F7_FLASH_CONFIG_E -# undef CONFIG_STM32F7_FLASH_CONFIG_G +# undef CONFIG_STM32_FLASH_CONFIG_C +# undef CONFIG_STM32_FLASH_CONFIG_E +# undef CONFIG_STM32_FLASH_CONFIG_G -# if defined(CONFIG_STM32F7_FLASH_OVERRIDE_C) -# define CONFIG_STM32F7_FLASH_CONFIG_C +# if defined(CONFIG_STM32_FLASH_OVERRIDE_C) +# define CONFIG_STM32_FLASH_CONFIG_C -# elif defined(CONFIG_STM32F7_FLASH_OVERRIDE_E) -# define CONFIG_STM32F7_FLASH_CONFIG_E +# elif defined(CONFIG_STM32_FLASH_OVERRIDE_E) +# define CONFIG_STM32_FLASH_CONFIG_E # endif #endif -#if defined(CONFIG_STM32F7_FLASH_CONFIG_C) +#if defined(CONFIG_STM32_FLASH_CONFIG_C) # define STM32_FLASH_NPAGES 6 # define STM32_FLASH_SIZE _K((4 * 16) + (1 * 64) + (1 * 128)) # define STM32_FLASH_SIZES {_K(16), _K(16), _K(16), _K(16), \ _K(64), _K(128)} -#elif defined(CONFIG_STM32F7_FLASH_CONFIG_E) +#elif defined(CONFIG_STM32_FLASH_CONFIG_E) # define STM32_FLASH_NPAGES 8 # define STM32_FLASH_SIZE _K((4 * 16) + (1 * 64) + (3 * 128)) diff --git a/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_gpio.h b/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_gpio.h index 07752be9bf57c..3f961686b388d 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_gpio.h +++ b/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_gpio.h @@ -30,7 +30,7 @@ #include #include -#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX) +#if defined(CONFIG_STM32_STM32F72XX) || defined(CONFIG_STM32_STM32F73XX) /**************************************************************************** * Pre-processor Definitions @@ -51,7 +51,7 @@ /* Register Addresses *******************************************************/ -#if STM32F7_NGPIO > 0 +#if STM32_NGPIO > 0 # define STM32_GPIOA_MODER (STM32_GPIOA_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOA_OTYPER (STM32_GPIOA_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOA_OSPEED (STM32_GPIOA_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -64,7 +64,7 @@ # define STM32_GPIOA_AFRH (STM32_GPIOA_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32F7_NGPIO > 1 +#if STM32_NGPIO > 1 # define STM32_GPIOB_MODER (STM32_GPIOB_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOB_OTYPER (STM32_GPIOB_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOB_OSPEED (STM32_GPIOB_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -77,7 +77,7 @@ # define STM32_GPIOB_AFRH (STM32_GPIOB_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32F7_NGPIO > 2 +#if STM32_NGPIO > 2 # define STM32_GPIOC_MODER (STM32_GPIOC_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOC_OTYPER (STM32_GPIOC_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOC_OSPEED (STM32_GPIOC_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -90,7 +90,7 @@ # define STM32_GPIOC_AFRH (STM32_GPIOC_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32F7_NGPIO > 3 +#if STM32_NGPIO > 3 # define STM32_GPIOD_MODER (STM32_GPIOD_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOD_OTYPER (STM32_GPIOD_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOD_OSPEED (STM32_GPIOD_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -103,7 +103,7 @@ # define STM32_GPIOD_AFRH (STM32_GPIOD_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32F7_NGPIO > 4 +#if STM32_NGPIO > 4 # define STM32_GPIOE_MODER (STM32_GPIOE_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOE_OTYPER (STM32_GPIOE_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOE_OSPEED (STM32_GPIOE_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -116,7 +116,7 @@ # define STM32_GPIOE_AFRH (STM32_GPIOE_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32F7_NGPIO > 5 +#if STM32_NGPIO > 5 # define STM32_GPIOF_MODER (STM32_GPIOF_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOF_OTYPER (STM32_GPIOF_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOF_OSPEED (STM32_GPIOF_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -129,7 +129,7 @@ # define STM32_GPIOF_AFRH (STM32_GPIOF_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32F7_NGPIO > 6 +#if STM32_NGPIO > 6 # define STM32_GPIOG_MODER (STM32_GPIOG_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOG_OTYPER (STM32_GPIOG_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOG_OSPEED (STM32_GPIOG_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -142,7 +142,7 @@ # define STM32_GPIOG_AFRH (STM32_GPIOG_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32F7_NGPIO > 7 +#if STM32_NGPIO > 7 # define STM32_GPIOH_MODER (STM32_GPIOH_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOH_OTYPER (STM32_GPIOH_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOH_OSPEED (STM32_GPIOH_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -155,7 +155,7 @@ # define STM32_GPIOH_AFRH (STM32_GPIOH_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32F7_NGPIO > 8 +#if STM32_NGPIO > 8 # define STM32_GPIOI_MODER (STM32_GPIOI_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOI_OTYPER (STM32_GPIOI_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOI_OSPEED (STM32_GPIOI_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -168,7 +168,7 @@ # define STM32_GPIOI_AFRH (STM32_GPIOI_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32F7_NGPIO > 9 +#if STM32_NGPIO > 9 # define STM32_GPIOJ_MODER (STM32_GPIOJ_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOJ_OTYPER (STM32_GPIOJ_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOJ_OSPEED (STM32_GPIOJ_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -181,7 +181,7 @@ # define STM32_GPIOJ_AFRH (STM32_GPIOJ_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32F7_NGPIO > 10 +#if STM32_NGPIO > 10 # define STM32_GPIOK_MODER (STM32_GPIOK_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOK_OTYPER (STM32_GPIOK_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOK_OSPEED (STM32_GPIOK_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -386,5 +386,5 @@ #define GPIO_AFRH15_SHIFT (28) #define GPIO_AFRH15_MASK (15 << GPIO_AFRH15_SHIFT) -#endif /* CONFIG_STM32F7_STM32F72XX || CONFIG_STM32F7_STM32F73XX */ +#endif /* CONFIG_STM32_STM32F72XX || CONFIG_STM32_STM32F73XX */ #endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F72XX73XX_GPIO_H */ diff --git a/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_memorymap.h b/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_memorymap.h index 1e10e0c06b17d..0ee93e4ee04e4 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_memorymap.h +++ b/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_memorymap.h @@ -29,7 +29,7 @@ #include -#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX) +#if defined(CONFIG_STM32_STM32F72XX) || defined(CONFIG_STM32_STM32F73XX) /**************************************************************************** * Pre-processor Definitions @@ -188,5 +188,5 @@ #define STM32_DEBUGMCU_BASE 0xe0042000 -#endif /* CONFIG_STM32F7_STM32F72XX || CONFIG_STM32F7_STM32F73XX */ +#endif /* CONFIG_STM32_STM32F72XX || CONFIG_STM32_STM32F73XX */ #endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F72XX73XX_MEMORYMAP_H */ diff --git a/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_pinmap.h b/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_pinmap.h index 51ef59e85acd4..9e649c192cea9 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_pinmap.h +++ b/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_pinmap.h @@ -31,7 +31,7 @@ #include "stm32_gpio.h" -#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX) +#if defined(CONFIG_STM32_STM32F72XX) || defined(CONFIG_STM32_STM32F73XX) /**************************************************************************** * Pre-processor Definitions @@ -923,5 +923,5 @@ #define GPIO_UART8_RX_0 (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN0) #define GPIO_UART8_TX_0 (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN1) -#endif /* CONFIG_STM32F7_STM32F72XX || CONFIG_STM32F7_STM32F73XX */ +#endif /* CONFIG_STM32_STM32F72XX || CONFIG_STM32_STM32F73XX */ #endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F72XX73XX_PINMAP_H */ diff --git a/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_pwr.h b/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_pwr.h index b712b40aa6fab..206807751d1ed 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_pwr.h +++ b/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_pwr.h @@ -29,7 +29,7 @@ #include -#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX) +#if defined(CONFIG_STM32_STM32F72XX) || defined(CONFIG_STM32_STM32F73XX) /**************************************************************************** * Pre-processor Definitions @@ -144,5 +144,5 @@ #define PWR_CSR2_EWUP5 (1 << 12) /* Bit 12: Enable wakeup pin for PI8 */ #define PWR_CSR2_EWUP6 (1 << 13) /* Bit 13: Enable wakeup pin for PI11 */ -#endif /* CONFIG_STM32F7_STM32F72XX || CONFIG_STM32F7_STM32F73XX */ +#endif /* CONFIG_STM32_STM32F72XX || CONFIG_STM32_STM32F73XX */ #endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F72XX73XX_PWR_H */ diff --git a/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_rcc.h b/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_rcc.h index a9dc161a5aef5..c7e53682bdd15 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_rcc.h +++ b/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_rcc.h @@ -29,7 +29,7 @@ #include -#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX) +#if defined(CONFIG_STM32_STM32F72XX) || defined(CONFIG_STM32_STM32F73XX) /**************************************************************************** * Pre-processor Definitions @@ -677,5 +677,5 @@ # define RCC_DCKCFGR2_SDMMC2SEL_48MHZ (0 << RCC_DCKCFGR2_SDMMC2SEL_SHIFT) /* 48 MHz clock is selected as SDMMC clock */ # define RCC_DCKCFGR2_SDMMC2SEL_SYSCLK (1 << RCC_DCKCFGR2_SDMMC2SEL_SHIFT) /* System clock is selected as SDMMC clock */ -#endif /* CONFIG_STM32F7_STM32F72XX || CONFIG_STM32F7_STM32F73XX */ +#endif /* CONFIG_STM32_STM32F72XX || CONFIG_STM32_STM32F73XX */ #endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F74XX75XX_RCC_H */ diff --git a/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_spi.h b/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_spi.h index cbcba08dbf47f..00fe52c6f7cda 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_spi.h +++ b/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_spi.h @@ -54,7 +54,7 @@ /* Register Addresses *******************************************************/ -#if STM32F7_NSPI > 0 +#if STM32_NSPI > 0 # define STM32_SPI1_CR1 (STM32_SPI1_BASE+STM32_SPI_CR1_OFFSET) # define STM32_SPI1_CR2 (STM32_SPI1_BASE+STM32_SPI_CR2_OFFSET) # define STM32_SPI1_SR (STM32_SPI1_BASE+STM32_SPI_SR_OFFSET) @@ -64,7 +64,7 @@ # define STM32_SPI1_TXCRCR (STM32_SPI1_BASE+STM32_SPI_TXCRCR_OFFSET) #endif -#if STM32F7_NSPI > 1 +#if STM32_NSPI > 1 # define STM32_SPI2_CR1 (STM32_SPI2_BASE+STM32_SPI_CR1_OFFSET) # define STM32_SPI2_CR2 (STM32_SPI2_BASE+STM32_SPI_CR2_OFFSET) # define STM32_SPI2_SR (STM32_SPI2_BASE+STM32_SPI_SR_OFFSET) @@ -76,7 +76,7 @@ # define STM32_SPI2_I2SPR (STM32_SPI2_BASE+STM32_SPI_I2SPR_OFFSET) #endif -#if STM32F7_NSPI > 2 +#if STM32_NSPI > 2 # define STM32_SPI3_CR1 (STM32_SPI3_BASE+STM32_SPI_CR1_OFFSET) # define STM32_SPI3_CR2 (STM32_SPI3_BASE+STM32_SPI_CR2_OFFSET) # define STM32_SPI3_SR (STM32_SPI3_BASE+STM32_SPI_SR_OFFSET) @@ -88,7 +88,7 @@ # define STM32_SPI3_I2SPR (STM32_SPI3_BASE+STM32_SPI_I2SPR_OFFSET) #endif -#if STM32F7_NSPI > 3 +#if STM32_NSPI > 3 # define STM32_SPI4_CR1 (STM32_SPI4_BASE+STM32_SPI_CR1_OFFSET) # define STM32_SPI4_CR2 (STM32_SPI4_BASE+STM32_SPI_CR2_OFFSET) # define STM32_SPI4_SR (STM32_SPI4_BASE+STM32_SPI_SR_OFFSET) @@ -100,7 +100,7 @@ # define STM32_SPI4_I2SPR (STM32_SPI4_BASE+STM32_SPI_I2SPR_OFFSET) #endif -#if STM32F7_NSPI > 4 +#if STM32_NSPI > 4 # define STM32_SPI5_CR1 (STM32_SPI5_BASE+STM32_SPI_CR1_OFFSET) # define STM32_SPI5_CR2 (STM32_SPI5_BASE+STM32_SPI_CR2_OFFSET) # define STM32_SPI5_SR (STM32_SPI5_BASE+STM32_SPI_SR_OFFSET) @@ -112,7 +112,7 @@ # define STM32_SPI5_I2SPR (STM32_SPI5_BASE+STM32_SPI_I2SPR_OFFSET) #endif -#if STM32F7_NSPI > 5 +#if STM32_NSPI > 5 # define STM32_SPI6_CR1 (STM32_SPI6_BASE+STM32_SPI_CR1_OFFSET) # define STM32_SPI6_CR2 (STM32_SPI6_BASE+STM32_SPI_CR2_OFFSET) # define STM32_SPI6_SR (STM32_SPI6_BASE+STM32_SPI_SR_OFFSET) diff --git a/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_syscfg.h b/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_syscfg.h index 6c206fcebfcea..d777cdddb4cb1 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_syscfg.h +++ b/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_syscfg.h @@ -30,7 +30,7 @@ #include #include "chip.h" -#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX) +#if defined(CONFIG_STM32_STM32F72XX) || defined(CONFIG_STM32_STM32F73XX) /**************************************************************************** * Pre-processor Definitions @@ -145,5 +145,5 @@ #define SYSCFG_CMPCR_CMPPD (1 << 0) /* Bit 0: Compensation cell power-down */ #define SYSCFG_CMPCR_READY (1 << 8) /* Bit 8: Compensation cell ready flag */ -#endif /* CONFIG_STM32F7_STM32F72XX || CONFIG_STM32F7_STM32F73XX */ +#endif /* CONFIG_STM32_STM32F72XX || CONFIG_STM32_STM32F73XX */ #endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F72XX73XX_SYSCFG_H */ diff --git a/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_tim.h b/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_tim.h index d9d897fe1e321..5a3e8dbb1d480 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_tim.h +++ b/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_tim.h @@ -97,7 +97,7 @@ /* Advanced Timers - TIM1 and TIM8 */ -#if STM32F7_NATIM > 0 +#if STM32_NATIM > 0 # define STM32_TIM1_CR1 (STM32_TIM1_BASE+STM32_ATIM_CR1_OFFSET) # define STM32_TIM1_CR2 (STM32_TIM1_BASE+STM32_ATIM_CR2_OFFSET) # define STM32_TIM1_SMCR (STM32_TIM1_BASE+STM32_ATIM_SMCR_OFFSET) @@ -123,7 +123,7 @@ # define STM32_TIM1_CCR6 (STM32_TIM1_BASE+STM32_ATIM_CCR6_OFFSET) #endif -#if STM32F7_NATIM > 1 +#if STM32_NATIM > 1 # define STM32_TIM8_CR1 (STM32_TIM8_BASE+STM32_ATIM_CR1_OFFSET) # define STM32_TIM8_CR2 (STM32_TIM8_BASE+STM32_ATIM_CR2_OFFSET) # define STM32_TIM8_SMCR (STM32_TIM8_BASE+STM32_ATIM_SMCR_OFFSET) @@ -153,7 +153,7 @@ * All timers are 16-bit except for TIM2 and 5 are 32-bit */ -#if (STM32F7_NGTIM16+STM32F7_NGTIM32) > 0 +#if (STM32_NGTIM16+STM32_NGTIM32) > 0 # define STM32_TIM2_CR1 (STM32_TIM2_BASE+STM32_GTIM_CR1_OFFSET) # define STM32_TIM2_CR2 (STM32_TIM2_BASE+STM32_GTIM_CR2_OFFSET) # define STM32_TIM2_SMCR (STM32_TIM2_BASE+STM32_GTIM_SMCR_OFFSET) @@ -175,7 +175,7 @@ # define STM32_TIM2_OR (STM32_TIM2_BASE+STM32_GTIM_OR_OFFSET) #endif -#if (STM32F7_NGTIM16+STM32F7_NGTIM32) > 1 +#if (STM32_NGTIM16+STM32_NGTIM32) > 1 # define STM32_TIM3_CR1 (STM32_TIM3_BASE+STM32_GTIM_CR1_OFFSET) # define STM32_TIM3_CR2 (STM32_TIM3_BASE+STM32_GTIM_CR2_OFFSET) # define STM32_TIM3_SMCR (STM32_TIM3_BASE+STM32_GTIM_SMCR_OFFSET) @@ -196,7 +196,7 @@ # define STM32_TIM3_DMAR (STM32_TIM3_BASE+STM32_GTIM_DMAR_OFFSET) #endif -#if (STM32F7_NGTIM16+STM32F7_NGTIM32) > 2 +#if (STM32_NGTIM16+STM32_NGTIM32) > 2 # define STM32_TIM4_CR1 (STM32_TIM4_BASE+STM32_GTIM_CR1_OFFSET) # define STM32_TIM4_CR2 (STM32_TIM4_BASE+STM32_GTIM_CR2_OFFSET) # define STM32_TIM4_SMCR (STM32_TIM4_BASE+STM32_GTIM_SMCR_OFFSET) @@ -217,7 +217,7 @@ # define STM32_TIM4_DMAR (STM32_TIM4_BASE+STM32_GTIM_DMAR_OFFSET) #endif -#if (STM32F7_NGTIM16+STM32F7_NGTIM32) > 3 +#if (STM32_NGTIM16+STM32_NGTIM32) > 3 # define STM32_TIM5_CR1 (STM32_TIM5_BASE+STM32_GTIM_CR1_OFFSET) # define STM32_TIM5_CR2 (STM32_TIM5_BASE+STM32_GTIM_CR2_OFFSET) # define STM32_TIM5_SMCR (STM32_TIM5_BASE+STM32_GTIM_SMCR_OFFSET) @@ -244,7 +244,7 @@ * (2) TIM9 and TIM12 differ from the others. */ -#if STM32F7_NGTIMNDMA > 0 +#if STM32_NGTIMNDMA > 0 # define STM32_TIM9_CR1 (STM32_TIM9_BASE+STM32_GTIM_CR1_OFFSET) # define STM32_TIM9_CR2 (STM32_TIM9_BASE+STM32_GTIM_CR2_OFFSET) # define STM32_TIM9_DIER (STM32_TIM9_BASE+STM32_GTIM_DIER_OFFSET) @@ -259,7 +259,7 @@ # define STM32_TIM9_CCR2 (STM32_TIM9_BASE+STM32_GTIM_CCR2_OFFSET) #endif -#if STM32F7_NGTIMNDMA > 1 +#if STM32_NGTIMNDMA > 1 # define STM32_TIM10_CR1 (STM32_TIM10_BASE+STM32_GTIM_CR1_OFFSET) # define STM32_TIM10_DIER (STM32_TIM10_BASE+STM32_GTIM_DIER_OFFSET) # define STM32_TIM10_SR (STM32_TIM10_BASE+STM32_GTIM_SR_OFFSET) @@ -272,7 +272,7 @@ # define STM32_TIM10_CCR1 (STM32_TIM10_BASE+STM32_GTIM_CCR1_OFFSET) #endif -#if STM32F7_NGTIMNDMA > 2 +#if STM32_NGTIMNDMA > 2 # define STM32_TIM11_CR1 (STM32_TIM11_BASE+STM32_GTIM_CR1_OFFSET) # define STM32_TIM11_DIER (STM32_TIM11_BASE+STM32_GTIM_DIER_OFFSET) # define STM32_TIM11_SR (STM32_TIM11_BASE+STM32_GTIM_SR_OFFSET) @@ -286,7 +286,7 @@ # define STM32_TIM11_OR (STM32_TIM11_BASE+STM32_GTIM_OR_OFFSET) #endif -#if STM32F7_NGTIMNDMA > 3 +#if STM32_NGTIMNDMA > 3 # define STM32_TIM12_CR1 (STM32_TIM12_BASE+STM32_GTIM_CR1_OFFSET) # define STM32_TIM12_CR2 (STM32_TIM9_BASE+STM32_GTIM_CR2_OFFSET) # define STM32_TIM12_DIER (STM32_TIM12_BASE+STM32_GTIM_DIER_OFFSET) @@ -301,7 +301,7 @@ # define STM32_TIM12_CCR2 (STM32_TIM12_BASE+STM32_GTIM_CCR2_OFFSET) #endif -#if STM32F7_NGTIMNDMA > 4 +#if STM32_NGTIMNDMA > 4 # define STM32_TIM13_CR1 (STM32_TIM13_BASE+STM32_GTIM_CR1_OFFSET) # define STM32_TIM13_DIER (STM32_TIM13_BASE+STM32_GTIM_DIER_OFFSET) # define STM32_TIM13_SR (STM32_TIM13_BASE+STM32_GTIM_SR_OFFSET) @@ -314,7 +314,7 @@ # define STM32_TIM13_CCR1 (STM32_TIM13_BASE+STM32_GTIM_CCR1_OFFSET) #endif -#if STM32F7_NGTIMNDMA > 5 +#if STM32_NGTIMNDMA > 5 # define STM32_TIM14_CR1 (STM32_TIM14_BASE+STM32_GTIM_CR1_OFFSET) # define STM32_TIM14_DIER (STM32_TIM14_BASE+STM32_GTIM_DIER_OFFSET) # define STM32_TIM14_SR (STM32_TIM14_BASE+STM32_GTIM_SR_OFFSET) @@ -329,7 +329,7 @@ /* Basic Timers - TIM6 and TIM7 */ -#if STM32F7_NBTIM > 0 +#if STM32_NBTIM > 0 # define STM32_TIM6_CR1 (STM32_TIM6_BASE+STM32_BTIM_CR1_OFFSET) # define STM32_TIM6_CR2 (STM32_TIM6_BASE+STM32_BTIM_CR2_OFFSET) # define STM32_TIM6_DIER (STM32_TIM6_BASE+STM32_BTIM_DIER_OFFSET) @@ -340,7 +340,7 @@ # define STM32_TIM6_ARR (STM32_TIM6_BASE+STM32_BTIM_ARR_OFFSET) #endif -#if STM32F7_NBTIM > 1 +#if STM32_NBTIM > 1 # define STM32_TIM7_CR1 (STM32_TIM7_BASE+STM32_BTIM_CR1_OFFSET) # define STM32_TIM7_CR2 (STM32_TIM7_BASE+STM32_BTIM_CR2_OFFSET) # define STM32_TIM7_DIER (STM32_TIM7_BASE+STM32_BTIM_DIER_OFFSET) diff --git a/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_uart.h b/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_uart.h index 6473f22947bf1..997b618630326 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_uart.h +++ b/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_uart.h @@ -29,7 +29,7 @@ #include -#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX) +#if defined(CONFIG_STM32_STM32F72XX) || defined(CONFIG_STM32_STM32F73XX) /**************************************************************************** * Pre-processor Definitions @@ -51,7 +51,7 @@ /* Register Addresses *******************************************************/ -#if STM32F7_NUSART > 0 +#if STM32_NUSART > 0 # define STM32_USART1_CR1 (STM32_USART1_BASE+STM32_USART_CR1_OFFSET) # define STM32_USART1_CR2 (STM32_USART1_BASE+STM32_USART_CR2_OFFSET) # define STM32_USART1_CR3 (STM32_USART1_BASE+STM32_USART_CR3_OFFSET) @@ -66,7 +66,7 @@ # define STM32_USART1_TDR (STM32_USART1_BASE+STM32_USART_TDR_OFFSET) #endif -#if STM32F7_NUSART > 1 +#if STM32_NUSART > 1 # define STM32_USART2_CR1 (STM32_USART2_BASE+STM32_USART_CR1_OFFSET) # define STM32_USART2_CR2 (STM32_USART2_BASE+STM32_USART_CR2_OFFSET) # define STM32_USART2_CR3 (STM32_USART2_BASE+STM32_USART_CR3_OFFSET) @@ -81,7 +81,7 @@ # define STM32_USART2_TDR (STM32_USART2_BASE+STM32_USART_TDR_OFFSET) #endif -#if STM32F7_NUSART > 2 +#if STM32_NUSART > 2 # define STM32_USART3_CR1 (STM32_USART3_BASE+STM32_USART_CR1_OFFSET) # define STM32_USART3_CR2 (STM32_USART3_BASE+STM32_USART_CR2_OFFSET) # define STM32_USART3_CR3 (STM32_USART3_BASE+STM32_USART_CR3_OFFSET) @@ -96,7 +96,7 @@ # define STM32_USART3_TDR (STM32_USART3_BASE+STM32_USART_TDR_OFFSET) #endif -#if STM32F7_NUSART > 3 +#if STM32_NUSART > 3 # define STM32_USART6_CR1 (STM32_USART6_BASE+STM32_USART_CR1_OFFSET) # define STM32_USART6_CR2 (STM32_USART6_BASE+STM32_USART_CR2_OFFSET) # define STM32_USART6_CR3 (STM32_USART6_BASE+STM32_USART_CR3_OFFSET) @@ -111,7 +111,7 @@ # define STM32_USART6_TDR (STM32_USART6_BASE+STM32_USART_TDR_OFFSET) #endif -#if STM32F7_NUART > 0 +#if STM32_NUART > 0 # define STM32_UART4_CR1 (STM32_UART4_BASE+STM32_USART_CR1_OFFSET) # define STM32_UART4_CR2 (STM32_UART4_BASE+STM32_USART_CR2_OFFSET) # define STM32_UART4_CR3 (STM32_UART4_BASE+STM32_USART_CR3_OFFSET) @@ -126,7 +126,7 @@ # define STM32_UART4_TDR (STM32_UART4_BASE+STM32_USART_TDR_OFFSET) #endif -#if STM32F7_NUART > 1 +#if STM32_NUART > 1 # define STM32_UART5_CR1 (STM32_UART5_BASE+STM32_USART_CR1_OFFSET) # define STM32_UART5_CR2 (STM32_UART5_BASE+STM32_USART_CR2_OFFSET) # define STM32_UART5_CR3 (STM32_UART5_BASE+STM32_USART_CR3_OFFSET) @@ -141,7 +141,7 @@ # define STM32_UART5_TDR (STM32_UART5_BASE+STM32_USART_TDR_OFFSET) #endif -#if STM32F7_NUART > 2 +#if STM32_NUART > 2 # define STM32_UART7_CR1 (STM32_UART7_BASE+STM32_USART_CR1_OFFSET) # define STM32_UART7_CR2 (STM32_UART7_BASE+STM32_USART_CR2_OFFSET) # define STM32_UART7_CR3 (STM32_UART7_BASE+STM32_USART_CR3_OFFSET) @@ -156,7 +156,7 @@ # define STM32_UART7_TDR (STM32_UART7_BASE+STM32_USART_TDR_OFFSET) #endif -#if STM32F7_NUART > 3 +#if STM32_NUART > 3 # define STM32_UART8_CR1 (STM32_UART8_BASE+STM32_USART_CR1_OFFSET) # define STM32_UART8_CR2 (STM32_UART8_BASE+STM32_USART_CR2_OFFSET) # define STM32_UART8_CR3 (STM32_UART8_BASE+STM32_USART_CR3_OFFSET) @@ -354,5 +354,5 @@ #define USART_TDR_SHIFT (0) /* Bits 8:0: Transmit data value */ #define USART_TDR_MASK (0x1ff << USART_TDR_SHIFT) -#endif /* CONFIG_STM32F7_STM32F72XX || CONFIG_STM32F7_STM32F73XX */ +#endif /* CONFIG_STM32_STM32F72XX || CONFIG_STM32_STM32F73XX */ #endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F72XX73XX_UART_H */ diff --git a/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_dma.h b/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_dma.h index d82ff66c0a25a..58a50d908c944 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_dma.h +++ b/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_dma.h @@ -29,7 +29,7 @@ #include -#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) +#if defined(CONFIG_STM32_STM32F74XX) || defined(CONFIG_STM32_STM32F75XX) /**************************************************************************** * Pre-processor Definitions @@ -545,5 +545,5 @@ #define DMAMAP_TIM8_TRIG STM32_DMA_MAP(DMA2,DMA_STREAM7,DMA_CHAN7) #define DMAMAP_TIM8_COM STM32_DMA_MAP(DMA2,DMA_STREAM7,DMA_CHAN7) -#endif /* CONFIG_STM32F7_STM32F74XX || CONFIG_STM32F7_STM32F75XX */ +#endif /* CONFIG_STM32_STM32F74XX || CONFIG_STM32_STM32F75XX */ #endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F74XX75XX_DMA_H */ diff --git a/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_flash.h b/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_flash.h index 23ba0cc2f6bc9..3ed343c6612d6 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_flash.h +++ b/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_flash.h @@ -29,10 +29,10 @@ /* Flash size is known from the chip selection: * - * When CONFIG_STM32F7_FLASH_OVERRIDE_DEFAULT is set the - * CONFIG_STM32F7_FLASH_CONFIG_x selects the default FLASH size based on + * When CONFIG_STM32_FLASH_OVERRIDE_DEFAULT is set the + * CONFIG_STM32_FLASH_CONFIG_x selects the default FLASH size based on * the chip part number. - * This value can be overridden with CONFIG_STM32F7_FLASH_OVERRIDE_x + * This value can be overridden with CONFIG_STM32_FLASH_OVERRIDE_x * * Parts STM32F74xxE have 512Kb of FLASH * Parts STM32F74xxG have 1024Kb of FLASH @@ -42,39 +42,39 @@ #define _K(x) ((x)*1024) -#if !defined(CONFIG_STM32F7_FLASH_OVERRIDE_DEFAULT) && \ - !defined(CONFIG_STM32F7_FLASH_OVERRIDE_E) && \ - !defined(CONFIG_STM32F7_FLASH_OVERRIDE_G) && \ - !defined(CONFIG_STM32F7_FLASH_CONFIG_E) && \ - !defined(CONFIG_STM32F7_FLASH_CONFIG_G) -# define CONFIG_STM32F7_FLASH_OVERRIDE_E +#if !defined(CONFIG_STM32_FLASH_OVERRIDE_DEFAULT) && \ + !defined(CONFIG_STM32_FLASH_OVERRIDE_E) && \ + !defined(CONFIG_STM32_FLASH_OVERRIDE_G) && \ + !defined(CONFIG_STM32_FLASH_CONFIG_E) && \ + !defined(CONFIG_STM32_FLASH_CONFIG_G) +# define CONFIG_STM32_FLASH_OVERRIDE_E # warning "Flash size not defined defaulting to 512KiB (E)" #endif -#if !defined(CONFIG_STM32F7_FLASH_OVERRIDE_DEFAULT) +#if !defined(CONFIG_STM32_FLASH_OVERRIDE_DEFAULT) -# undef CONFIG_STM32F7_FLASH_CONFIG_E -# undef CONFIG_STM32F7_FLASH_CONFIG_G +# undef CONFIG_STM32_FLASH_CONFIG_E +# undef CONFIG_STM32_FLASH_CONFIG_G -# if defined(CONFIG_STM32F7_FLASH_OVERRIDE_E) +# if defined(CONFIG_STM32_FLASH_OVERRIDE_E) -# define CONFIG_STM32F7_FLASH_CONFIG_E +# define CONFIG_STM32_FLASH_CONFIG_E -# elif defined(CONFIG_STM32F7_FLASH_OVERRIDE_G) +# elif defined(CONFIG_STM32_FLASH_OVERRIDE_G) -# define CONFIG_STM32F7_FLASH_CONFIG_G +# define CONFIG_STM32_FLASH_CONFIG_G # endif #endif -#if defined(CONFIG_STM32F7_FLASH_CONFIG_E) +#if defined(CONFIG_STM32_FLASH_CONFIG_E) # define STM32_FLASH_NPAGES 6 # define STM32_FLASH_SIZE _K((4 * 32) + (1 * 128) + (1 * 256)) # define STM32_FLASH_SIZES {_K(32), _K(32), _K(32), _K(32), \ _K(128), _K(256)} -#elif defined(CONFIG_STM32F7_FLASH_CONFIG_G) +#elif defined(CONFIG_STM32_FLASH_CONFIG_G) # define STM32_FLASH_NPAGES 8 # define STM32_FLASH_SIZE _K((4 * 32) + (1 * 128) + (3 * 256)) diff --git a/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_gpio.h b/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_gpio.h index 7d40fb94d08a2..a423e8c659f1c 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_gpio.h +++ b/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_gpio.h @@ -30,7 +30,7 @@ #include #include -#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) +#if defined(CONFIG_STM32_STM32F74XX) || defined(CONFIG_STM32_STM32F75XX) /**************************************************************************** * Pre-processor Definitions @@ -51,7 +51,7 @@ /* Register Addresses *******************************************************/ -#if STM32F7_NGPIO > 0 +#if STM32_NGPIO > 0 # define STM32_GPIOA_MODER (STM32_GPIOA_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOA_OTYPER (STM32_GPIOA_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOA_OSPEED (STM32_GPIOA_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -64,7 +64,7 @@ # define STM32_GPIOA_AFRH (STM32_GPIOA_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32F7_NGPIO > 1 +#if STM32_NGPIO > 1 # define STM32_GPIOB_MODER (STM32_GPIOB_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOB_OTYPER (STM32_GPIOB_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOB_OSPEED (STM32_GPIOB_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -77,7 +77,7 @@ # define STM32_GPIOB_AFRH (STM32_GPIOB_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32F7_NGPIO > 2 +#if STM32_NGPIO > 2 # define STM32_GPIOC_MODER (STM32_GPIOC_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOC_OTYPER (STM32_GPIOC_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOC_OSPEED (STM32_GPIOC_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -90,7 +90,7 @@ # define STM32_GPIOC_AFRH (STM32_GPIOC_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32F7_NGPIO > 3 +#if STM32_NGPIO > 3 # define STM32_GPIOD_MODER (STM32_GPIOD_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOD_OTYPER (STM32_GPIOD_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOD_OSPEED (STM32_GPIOD_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -103,7 +103,7 @@ # define STM32_GPIOD_AFRH (STM32_GPIOD_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32F7_NGPIO > 4 +#if STM32_NGPIO > 4 # define STM32_GPIOE_MODER (STM32_GPIOE_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOE_OTYPER (STM32_GPIOE_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOE_OSPEED (STM32_GPIOE_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -116,7 +116,7 @@ # define STM32_GPIOE_AFRH (STM32_GPIOE_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32F7_NGPIO > 5 +#if STM32_NGPIO > 5 # define STM32_GPIOF_MODER (STM32_GPIOF_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOF_OTYPER (STM32_GPIOF_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOF_OSPEED (STM32_GPIOF_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -129,7 +129,7 @@ # define STM32_GPIOF_AFRH (STM32_GPIOF_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32F7_NGPIO > 6 +#if STM32_NGPIO > 6 # define STM32_GPIOG_MODER (STM32_GPIOG_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOG_OTYPER (STM32_GPIOG_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOG_OSPEED (STM32_GPIOG_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -142,7 +142,7 @@ # define STM32_GPIOG_AFRH (STM32_GPIOG_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32F7_NGPIO > 7 +#if STM32_NGPIO > 7 # define STM32_GPIOH_MODER (STM32_GPIOH_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOH_OTYPER (STM32_GPIOH_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOH_OSPEED (STM32_GPIOH_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -155,7 +155,7 @@ # define STM32_GPIOH_AFRH (STM32_GPIOH_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32F7_NGPIO > 8 +#if STM32_NGPIO > 8 # define STM32_GPIOI_MODER (STM32_GPIOI_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOI_OTYPER (STM32_GPIOI_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOI_OSPEED (STM32_GPIOI_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -168,7 +168,7 @@ # define STM32_GPIOI_AFRH (STM32_GPIOI_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32F7_NGPIO > 9 +#if STM32_NGPIO > 9 # define STM32_GPIOJ_MODER (STM32_GPIOJ_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOJ_OTYPER (STM32_GPIOJ_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOJ_OSPEED (STM32_GPIOJ_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -181,7 +181,7 @@ # define STM32_GPIOJ_AFRH (STM32_GPIOJ_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32F7_NGPIO > 10 +#if STM32_NGPIO > 10 # define STM32_GPIOK_MODER (STM32_GPIOK_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOK_OTYPER (STM32_GPIOK_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOK_OSPEED (STM32_GPIOK_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -386,5 +386,5 @@ #define GPIO_AFRH15_SHIFT (28) #define GPIO_AFRH15_MASK (15 << GPIO_AFRH15_SHIFT) -#endif /* CONFIG_STM32F7_STM32F74XX || CONFIG_STM32F7_STM32F75XX */ +#endif /* CONFIG_STM32_STM32F74XX || CONFIG_STM32_STM32F75XX */ #endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F74XX75XX_GPIO_H */ diff --git a/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_memorymap.h b/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_memorymap.h index 350f17cc26039..74f18438de7e5 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_memorymap.h +++ b/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_memorymap.h @@ -29,7 +29,7 @@ #include -#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) +#if defined(CONFIG_STM32_STM32F74XX) || defined(CONFIG_STM32_STM32F75XX) /**************************************************************************** * Pre-processor Definitions @@ -199,5 +199,5 @@ #define STM32_DEBUGMCU_BASE 0xe0042000 -#endif /* CONFIG_STM32F7_STM32F74XX || CONFIG_STM32F7_STM32F75XX */ +#endif /* CONFIG_STM32_STM32F74XX || CONFIG_STM32_STM32F75XX */ #endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F74XXX75XXX_MEMORYMAP_H */ diff --git a/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_pinmap.h b/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_pinmap.h index 322f006d44d78..4f355760b2350 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_pinmap.h +++ b/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_pinmap.h @@ -31,7 +31,7 @@ #include "stm32_gpio.h" -#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) +#if defined(CONFIG_STM32_STM32F74XX) || defined(CONFIG_STM32_STM32F75XX) /**************************************************************************** * Pre-processor Definitions @@ -808,7 +808,7 @@ * * Note that the below configures GPIO_SPEED_50MHz I/O, that means for using * the SDIO that you must enable I/O Compensation via the configuration - * option CONFIG_STM32F7_SYSCFG_IOCOMPENSATION=y. + * option CONFIG_STM32_SYSCFG_IOCOMPENSATION=y. */ #define GPIO_SDMMC1_CK_0 (GPIO_ALT|GPIO_AF12|GPIO_PORTC|GPIO_PIN12) @@ -1171,5 +1171,5 @@ #define GPIO_UART8_RX_0 (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN0) #define GPIO_UART8_TX_0 (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN1) -#endif /* CONFIG_STM32F7_STM32F74XX || CONFIG_STM32F7_STM32F75XX */ +#endif /* CONFIG_STM32_STM32F74XX || CONFIG_STM32_STM32F75XX */ #endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F74XX75XX_PINMAP_H */ diff --git a/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_pwr.h b/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_pwr.h index 45fda531bd7fc..984af74a9980b 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_pwr.h +++ b/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_pwr.h @@ -29,7 +29,7 @@ #include -#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) +#if defined(CONFIG_STM32_STM32F74XX) || defined(CONFIG_STM32_STM32F75XX) /**************************************************************************** * Pre-processor Definitions @@ -144,5 +144,5 @@ #define PWR_CSR2_EWUP5 (1 << 12) /* Bit 12: Enable wakeup pin for PI8 */ #define PWR_CSR2_EWUP6 (1 << 13) /* Bit 13: Enable wakeup pin for PI11 */ -#endif /* CONFIG_STM32F7_STM32F74XX || CONFIG_STM32F7_STM32F75XX */ +#endif /* CONFIG_STM32_STM32F74XX || CONFIG_STM32_STM32F75XX */ #endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F74XX75XX_PWR_H */ diff --git a/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_rcc.h b/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_rcc.h index 2af6d3397204c..ef250fe77ba7a 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_rcc.h +++ b/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_rcc.h @@ -29,7 +29,7 @@ #include -#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) +#if defined(CONFIG_STM32_STM32F74XX) || defined(CONFIG_STM32_STM32F75XX) /**************************************************************************** * Pre-processor Definitions @@ -723,5 +723,5 @@ # define RCC_DCKCFGR2_SDMMCSEL_48MHZ (0 << RCC_DCKCFGR2_SDMMCSEL_SHIFT) /* 48 MHz clock is selected as SDMMC clock */ # define RCC_DCKCFGR2_SDMMCSEL_SYSCLK (1 << RCC_DCKCFGR2_SDMMCSEL_SHIFT) /* System clock is selected as SDMMC clock */ -#endif /* CONFIG_STM32F7_STM32F74XX || CONFIG_STM32F7_STM32F75XX */ +#endif /* CONFIG_STM32_STM32F74XX || CONFIG_STM32_STM32F75XX */ #endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F74XX75XX_RCC_H */ diff --git a/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_syscfg.h b/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_syscfg.h index 5072c16d68151..e634ebdb7ebc5 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_syscfg.h +++ b/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_syscfg.h @@ -30,7 +30,7 @@ #include #include "chip.h" -#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) +#if defined(CONFIG_STM32_STM32F74XX) || defined(CONFIG_STM32_STM32F75XX) /**************************************************************************** * Pre-processor Definitions @@ -143,5 +143,5 @@ #define SYSCFG_CMPCR_CMPPD (1 << 0) /* Bit 0: Compensation cell power-down */ #define SYSCFG_CMPCR_READY (1 << 8) /* Bit 8: Compensation cell ready flag */ -#endif /* CONFIG_STM32F7_STM32F74XX || CONFIG_STM32F7_STM32F75XX */ +#endif /* CONFIG_STM32_STM32F74XX || CONFIG_STM32_STM32F75XX */ #endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F74XX75XX_SYSCFG_H */ diff --git a/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_tim.h b/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_tim.h index 44bea32690327..f3144d3568da8 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_tim.h +++ b/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_tim.h @@ -97,7 +97,7 @@ /* Advanced Timers - TIM1 and TIM8 */ -#if STM32F7_NATIM > 0 +#if STM32_NATIM > 0 # define STM32_TIM1_CR1 (STM32_TIM1_BASE+STM32_ATIM_CR1_OFFSET) # define STM32_TIM1_CR2 (STM32_TIM1_BASE+STM32_ATIM_CR2_OFFSET) # define STM32_TIM1_SMCR (STM32_TIM1_BASE+STM32_ATIM_SMCR_OFFSET) @@ -123,7 +123,7 @@ # define STM32_TIM1_CCR6 (STM32_TIM1_BASE+STM32_ATIM_CCR6_OFFSET) #endif -#if STM32F7_NATIM > 1 +#if STM32_NATIM > 1 # define STM32_TIM8_CR1 (STM32_TIM8_BASE+STM32_ATIM_CR1_OFFSET) # define STM32_TIM8_CR2 (STM32_TIM8_BASE+STM32_ATIM_CR2_OFFSET) # define STM32_TIM8_SMCR (STM32_TIM8_BASE+STM32_ATIM_SMCR_OFFSET) @@ -153,7 +153,7 @@ * All timers are 16-bit except for TIM2 and 5 are 32-bit */ -#if (STM32F7_NGTIM16+STM32F7_NGTIM32) > 0 +#if (STM32_NGTIM16+STM32_NGTIM32) > 0 # define STM32_TIM2_CR1 (STM32_TIM2_BASE+STM32_GTIM_CR1_OFFSET) # define STM32_TIM2_CR2 (STM32_TIM2_BASE+STM32_GTIM_CR2_OFFSET) # define STM32_TIM2_SMCR (STM32_TIM2_BASE+STM32_GTIM_SMCR_OFFSET) @@ -175,7 +175,7 @@ # define STM32_TIM2_OR (STM32_TIM2_BASE+STM32_GTIM_OR_OFFSET) #endif -#if (STM32F7_NGTIM16+STM32F7_NGTIM32) > 1 +#if (STM32_NGTIM16+STM32_NGTIM32) > 1 # define STM32_TIM3_CR1 (STM32_TIM3_BASE+STM32_GTIM_CR1_OFFSET) # define STM32_TIM3_CR2 (STM32_TIM3_BASE+STM32_GTIM_CR2_OFFSET) # define STM32_TIM3_SMCR (STM32_TIM3_BASE+STM32_GTIM_SMCR_OFFSET) @@ -196,7 +196,7 @@ # define STM32_TIM3_DMAR (STM32_TIM3_BASE+STM32_GTIM_DMAR_OFFSET) #endif -#if (STM32F7_NGTIM16+STM32F7_NGTIM32) > 2 +#if (STM32_NGTIM16+STM32_NGTIM32) > 2 # define STM32_TIM4_CR1 (STM32_TIM4_BASE+STM32_GTIM_CR1_OFFSET) # define STM32_TIM4_CR2 (STM32_TIM4_BASE+STM32_GTIM_CR2_OFFSET) # define STM32_TIM4_SMCR (STM32_TIM4_BASE+STM32_GTIM_SMCR_OFFSET) @@ -217,7 +217,7 @@ # define STM32_TIM4_DMAR (STM32_TIM4_BASE+STM32_GTIM_DMAR_OFFSET) #endif -#if (STM32F7_NGTIM16+STM32F7_NGTIM32) > 3 +#if (STM32_NGTIM16+STM32_NGTIM32) > 3 # define STM32_TIM5_CR1 (STM32_TIM5_BASE+STM32_GTIM_CR1_OFFSET) # define STM32_TIM5_CR2 (STM32_TIM5_BASE+STM32_GTIM_CR2_OFFSET) # define STM32_TIM5_SMCR (STM32_TIM5_BASE+STM32_GTIM_SMCR_OFFSET) @@ -244,7 +244,7 @@ * (2) TIM9 and TIM12 differ from the others. */ -#if STM32F7_NGTIMNDMA > 0 +#if STM32_NGTIMNDMA > 0 # define STM32_TIM9_CR1 (STM32_TIM9_BASE+STM32_GTIM_CR1_OFFSET) # define STM32_TIM9_CR2 (STM32_TIM9_BASE+STM32_GTIM_CR2_OFFSET) # define STM32_TIM9_DIER (STM32_TIM9_BASE+STM32_GTIM_DIER_OFFSET) @@ -259,7 +259,7 @@ # define STM32_TIM9_CCR2 (STM32_TIM9_BASE+STM32_GTIM_CCR2_OFFSET) #endif -#if STM32F7_NGTIMNDMA > 1 +#if STM32_NGTIMNDMA > 1 # define STM32_TIM10_CR1 (STM32_TIM10_BASE+STM32_GTIM_CR1_OFFSET) # define STM32_TIM10_DIER (STM32_TIM10_BASE+STM32_GTIM_DIER_OFFSET) # define STM32_TIM10_SR (STM32_TIM10_BASE+STM32_GTIM_SR_OFFSET) @@ -272,7 +272,7 @@ # define STM32_TIM10_CCR1 (STM32_TIM10_BASE+STM32_GTIM_CCR1_OFFSET) #endif -#if STM32F7_NGTIMNDMA > 2 +#if STM32_NGTIMNDMA > 2 # define STM32_TIM11_CR1 (STM32_TIM11_BASE+STM32_GTIM_CR1_OFFSET) # define STM32_TIM11_DIER (STM32_TIM11_BASE+STM32_GTIM_DIER_OFFSET) # define STM32_TIM11_SR (STM32_TIM11_BASE+STM32_GTIM_SR_OFFSET) @@ -286,7 +286,7 @@ # define STM32_TIM11_OR (STM32_TIM11_BASE+STM32_GTIM_OR_OFFSET) #endif -#if STM32F7_NGTIMNDMA > 3 +#if STM32_NGTIMNDMA > 3 # define STM32_TIM12_CR1 (STM32_TIM12_BASE+STM32_GTIM_CR1_OFFSET) # define STM32_TIM12_CR2 (STM32_TIM9_BASE+STM32_GTIM_CR2_OFFSET) # define STM32_TIM12_DIER (STM32_TIM12_BASE+STM32_GTIM_DIER_OFFSET) @@ -301,7 +301,7 @@ # define STM32_TIM12_CCR2 (STM32_TIM12_BASE+STM32_GTIM_CCR2_OFFSET) #endif -#if STM32F7_NGTIMNDMA > 4 +#if STM32_NGTIMNDMA > 4 # define STM32_TIM13_CR1 (STM32_TIM13_BASE+STM32_GTIM_CR1_OFFSET) # define STM32_TIM13_DIER (STM32_TIM13_BASE+STM32_GTIM_DIER_OFFSET) # define STM32_TIM13_SR (STM32_TIM13_BASE+STM32_GTIM_SR_OFFSET) @@ -314,7 +314,7 @@ # define STM32_TIM13_CCR1 (STM32_TIM13_BASE+STM32_GTIM_CCR1_OFFSET) #endif -#if STM32F7_NGTIMNDMA > 5 +#if STM32_NGTIMNDMA > 5 # define STM32_TIM14_CR1 (STM32_TIM14_BASE+STM32_GTIM_CR1_OFFSET) # define STM32_TIM14_DIER (STM32_TIM14_BASE+STM32_GTIM_DIER_OFFSET) # define STM32_TIM14_SR (STM32_TIM14_BASE+STM32_GTIM_SR_OFFSET) @@ -329,7 +329,7 @@ /* Basic Timers - TIM6 and TIM7 */ -#if STM32F7_NBTIM > 0 +#if STM32_NBTIM > 0 # define STM32_TIM6_CR1 (STM32_TIM6_BASE+STM32_BTIM_CR1_OFFSET) # define STM32_TIM6_CR2 (STM32_TIM6_BASE+STM32_BTIM_CR2_OFFSET) # define STM32_TIM6_DIER (STM32_TIM6_BASE+STM32_BTIM_DIER_OFFSET) @@ -340,7 +340,7 @@ # define STM32_TIM6_ARR (STM32_TIM6_BASE+STM32_BTIM_ARR_OFFSET) #endif -#if STM32F7_NBTIM > 1 +#if STM32_NBTIM > 1 # define STM32_TIM7_CR1 (STM32_TIM7_BASE+STM32_BTIM_CR1_OFFSET) # define STM32_TIM7_CR2 (STM32_TIM7_BASE+STM32_BTIM_CR2_OFFSET) # define STM32_TIM7_DIER (STM32_TIM7_BASE+STM32_BTIM_DIER_OFFSET) diff --git a/arch/arm/src/stm32f7/hardware/stm32f74xx77xx_adc.h b/arch/arm/src/stm32f7/hardware/stm32f74xx77xx_adc.h index 4d6e8e398786a..8f2ede7053f76 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f74xx77xx_adc.h +++ b/arch/arm/src/stm32f7/hardware/stm32f74xx77xx_adc.h @@ -64,7 +64,7 @@ /* Register Addresses *******************************************************/ -#if STM32F7_NADC > 0 +#if STM32_NADC > 0 # define STM32_ADC1_SR (STM32_ADC1_BASE+STM32_ADC_SR_OFFSET) # define STM32_ADC1_CR1 (STM32_ADC1_BASE+STM32_ADC_CR1_OFFSET) # define STM32_ADC1_CR2 (STM32_ADC1_BASE+STM32_ADC_CR2_OFFSET) @@ -87,7 +87,7 @@ # define STM32_ADC1_DR (STM32_ADC1_BASE+STM32_ADC_DR_OFFSET) #endif -#if STM32F7_NADC > 1 +#if STM32_NADC > 1 # define STM32_ADC2_SR (STM32_ADC2_BASE+STM32_ADC_SR_OFFSET) # define STM32_ADC2_CR1 (STM32_ADC2_BASE+STM32_ADC_CR1_OFFSET) # define STM32_ADC2_CR2 (STM32_ADC2_BASE+STM32_ADC_CR2_OFFSET) @@ -110,7 +110,7 @@ # define STM32_ADC2_DR (STM32_ADC2_BASE+STM32_ADC_DR_OFFSET) #endif -#if STM32F7_NADC > 2 +#if STM32_NADC > 2 # define STM32_ADC3_SR (STM32_ADC3_BASE+STM32_ADC_SR_OFFSET) # define STM32_ADC3_CR1 (STM32_ADC3_BASE+STM32_ADC_CR1_OFFSET) # define STM32_ADC3_CR2 (STM32_ADC3_BASE+STM32_ADC_CR2_OFFSET) diff --git a/arch/arm/src/stm32f7/hardware/stm32f74xx77xx_i2c.h b/arch/arm/src/stm32f7/hardware/stm32f74xx77xx_i2c.h index 0194d61ee7479..a6417e0d4a817 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f74xx77xx_i2c.h +++ b/arch/arm/src/stm32f7/hardware/stm32f74xx77xx_i2c.h @@ -43,7 +43,7 @@ /* Register Addresses *******************************************************/ -#if STM32F7_NI2C > 0 +#if STM32_NI2C > 0 # define STM32_I2C1_CR1 (STM32_I2C1_BASE+STM32_I2C_CR1_OFFSET) # define STM32_I2C1_CR2 (STM32_I2C1_BASE+STM32_I2C_CR2_OFFSET) # define STM32_I2C1_OAR1 (STM32_I2C1_BASE+STM32_I2C_OAR1_OFFSET) @@ -57,7 +57,7 @@ # define STM32_I2C1_TXDR (STM32_I2C1_BASE+STM32_I2C_TXDR_OFFSET) #endif -#if STM32F7_NI2C > 1 +#if STM32_NI2C > 1 # define STM32_I2C2_CR1 (STM32_I2C2_BASE+STM32_I2C_CR1_OFFSET) # define STM32_I2C2_CR2 (STM32_I2C2_BASE+STM32_I2C_CR2_OFFSET) # define STM32_I2C2_OAR1 (STM32_I2C2_BASE+STM32_I2C_OAR1_OFFSET) @@ -71,7 +71,7 @@ # define STM32_I2C2_TXDR (STM32_I2C2_BASE+STM32_I2C_TXDR_OFFSET) #endif -#if STM32F7_NI2C > 2 +#if STM32_NI2C > 2 # define STM32_I2C3_CR1 (STM32_I2C3_BASE+STM32_I2C_CR1_OFFSET) # define STM32_I2C3_CR2 (STM32_I2C3_BASE+STM32_I2C_CR2_OFFSET) # define STM32_I2C3_OAR1 (STM32_I2C3_BASE+STM32_I2C_OAR1_OFFSET) @@ -85,7 +85,7 @@ # define STM32_I2C3_TXDR (STM32_I2C3_BASE+STM32_I2C_TXDR_OFFSET) #endif -#if STM32F7_NI2C > 3 +#if STM32_NI2C > 3 # define STM32_I2C4_CR1 (STM32_I2C4_BASE+STM32_I2C_CR1_OFFSET) # define STM32_I2C4_CR2 (STM32_I2C4_BASE+STM32_I2C_CR2_OFFSET) # define STM32_I2C4_OAR1 (STM32_I2C4_BASE+STM32_I2C_OAR1_OFFSET) diff --git a/arch/arm/src/stm32f7/hardware/stm32f74xx77xx_spi.h b/arch/arm/src/stm32f7/hardware/stm32f74xx77xx_spi.h index dd0d8963188a0..c1bfd5b133926 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f74xx77xx_spi.h +++ b/arch/arm/src/stm32f7/hardware/stm32f74xx77xx_spi.h @@ -38,9 +38,9 @@ * (both pclk1 and pclk2) */ -#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) +#if defined(CONFIG_STM32_STM32F74XX) || defined(CONFIG_STM32_STM32F75XX) # define STM32_SPI_CLK_MAX 50000000UL -#elif defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) +#elif defined(CONFIG_STM32_STM32F76XX) || defined(CONFIG_STM32_STM32F77XX) # define STM32_SPI_CLK_MAX 54000000UL #endif @@ -58,7 +58,7 @@ /* Register Addresses *******************************************************/ -#if STM32F7_NSPI > 0 +#if STM32_NSPI > 0 # define STM32_SPI1_CR1 (STM32_SPI1_BASE+STM32_SPI_CR1_OFFSET) # define STM32_SPI1_CR2 (STM32_SPI1_BASE+STM32_SPI_CR2_OFFSET) # define STM32_SPI1_SR (STM32_SPI1_BASE+STM32_SPI_SR_OFFSET) @@ -68,7 +68,7 @@ # define STM32_SPI1_TXCRCR (STM32_SPI1_BASE+STM32_SPI_TXCRCR_OFFSET) #endif -#if STM32F7_NSPI > 1 +#if STM32_NSPI > 1 # define STM32_SPI2_CR1 (STM32_SPI2_BASE+STM32_SPI_CR1_OFFSET) # define STM32_SPI2_CR2 (STM32_SPI2_BASE+STM32_SPI_CR2_OFFSET) # define STM32_SPI2_SR (STM32_SPI2_BASE+STM32_SPI_SR_OFFSET) @@ -80,7 +80,7 @@ # define STM32_SPI2_I2SPR (STM32_SPI2_BASE+STM32_SPI_I2SPR_OFFSET) #endif -#if STM32F7_NSPI > 2 +#if STM32_NSPI > 2 # define STM32_SPI3_CR1 (STM32_SPI3_BASE+STM32_SPI_CR1_OFFSET) # define STM32_SPI3_CR2 (STM32_SPI3_BASE+STM32_SPI_CR2_OFFSET) # define STM32_SPI3_SR (STM32_SPI3_BASE+STM32_SPI_SR_OFFSET) @@ -92,7 +92,7 @@ # define STM32_SPI3_I2SPR (STM32_SPI3_BASE+STM32_SPI_I2SPR_OFFSET) #endif -#if STM32F7_NSPI > 3 +#if STM32_NSPI > 3 # define STM32_SPI4_CR1 (STM32_SPI4_BASE+STM32_SPI_CR1_OFFSET) # define STM32_SPI4_CR2 (STM32_SPI4_BASE+STM32_SPI_CR2_OFFSET) # define STM32_SPI4_SR (STM32_SPI4_BASE+STM32_SPI_SR_OFFSET) @@ -104,7 +104,7 @@ # define STM32_SPI4_I2SPR (STM32_SPI4_BASE+STM32_SPI_I2SPR_OFFSET) #endif -#if STM32F7_NSPI > 4 +#if STM32_NSPI > 4 # define STM32_SPI5_CR1 (STM32_SPI5_BASE+STM32_SPI_CR1_OFFSET) # define STM32_SPI5_CR2 (STM32_SPI5_BASE+STM32_SPI_CR2_OFFSET) # define STM32_SPI5_SR (STM32_SPI5_BASE+STM32_SPI_SR_OFFSET) @@ -116,7 +116,7 @@ # define STM32_SPI5_I2SPR (STM32_SPI5_BASE+STM32_SPI_I2SPR_OFFSET) #endif -#if STM32F7_NSPI > 5 +#if STM32_NSPI > 5 # define STM32_SPI6_CR1 (STM32_SPI6_BASE+STM32_SPI_CR1_OFFSET) # define STM32_SPI6_CR2 (STM32_SPI6_BASE+STM32_SPI_CR2_OFFSET) # define STM32_SPI6_SR (STM32_SPI6_BASE+STM32_SPI_SR_OFFSET) diff --git a/arch/arm/src/stm32f7/hardware/stm32f74xx77xx_uart.h b/arch/arm/src/stm32f7/hardware/stm32f74xx77xx_uart.h index 6dfbba5177a97..bfefcbffcdeea 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f74xx77xx_uart.h +++ b/arch/arm/src/stm32f7/hardware/stm32f74xx77xx_uart.h @@ -29,8 +29,8 @@ #include -#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) || \ - defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) +#if defined(CONFIG_STM32_STM32F74XX) || defined(CONFIG_STM32_STM32F75XX) || \ + defined(CONFIG_STM32_STM32F76XX) || defined(CONFIG_STM32_STM32F77XX) /**************************************************************************** * Pre-processor Definitions @@ -52,7 +52,7 @@ /* Register Addresses *******************************************************/ -#if STM32F7_NUSART > 0 +#if STM32_NUSART > 0 # define STM32_USART1_CR1 (STM32_USART1_BASE+STM32_USART_CR1_OFFSET) # define STM32_USART1_CR2 (STM32_USART1_BASE+STM32_USART_CR2_OFFSET) # define STM32_USART1_CR3 (STM32_USART1_BASE+STM32_USART_CR3_OFFSET) @@ -67,7 +67,7 @@ # define STM32_USART1_TDR (STM32_USART1_BASE+STM32_USART_TDR_OFFSET) #endif -#if STM32F7_NUSART > 1 +#if STM32_NUSART > 1 # define STM32_USART2_CR1 (STM32_USART2_BASE+STM32_USART_CR1_OFFSET) # define STM32_USART2_CR2 (STM32_USART2_BASE+STM32_USART_CR2_OFFSET) # define STM32_USART2_CR3 (STM32_USART2_BASE+STM32_USART_CR3_OFFSET) @@ -82,7 +82,7 @@ # define STM32_USART2_TDR (STM32_USART2_BASE+STM32_USART_TDR_OFFSET) #endif -#if STM32F7_NUSART > 2 +#if STM32_NUSART > 2 # define STM32_USART3_CR1 (STM32_USART3_BASE+STM32_USART_CR1_OFFSET) # define STM32_USART3_CR2 (STM32_USART3_BASE+STM32_USART_CR2_OFFSET) # define STM32_USART3_CR3 (STM32_USART3_BASE+STM32_USART_CR3_OFFSET) @@ -97,7 +97,7 @@ # define STM32_USART3_TDR (STM32_USART3_BASE+STM32_USART_TDR_OFFSET) #endif -#if STM32F7_NUSART > 3 +#if STM32_NUSART > 3 # define STM32_USART6_CR1 (STM32_USART6_BASE+STM32_USART_CR1_OFFSET) # define STM32_USART6_CR2 (STM32_USART6_BASE+STM32_USART_CR2_OFFSET) # define STM32_USART6_CR3 (STM32_USART6_BASE+STM32_USART_CR3_OFFSET) @@ -112,7 +112,7 @@ # define STM32_USART6_TDR (STM32_USART6_BASE+STM32_USART_TDR_OFFSET) #endif -#if STM32F7_NUART > 0 +#if STM32_NUART > 0 # define STM32_UART4_CR1 (STM32_UART4_BASE+STM32_USART_CR1_OFFSET) # define STM32_UART4_CR2 (STM32_UART4_BASE+STM32_USART_CR2_OFFSET) # define STM32_UART4_CR3 (STM32_UART4_BASE+STM32_USART_CR3_OFFSET) @@ -127,7 +127,7 @@ # define STM32_UART4_TDR (STM32_UART4_BASE+STM32_USART_TDR_OFFSET) #endif -#if STM32F7_NUART > 1 +#if STM32_NUART > 1 # define STM32_UART5_CR1 (STM32_UART5_BASE+STM32_USART_CR1_OFFSET) # define STM32_UART5_CR2 (STM32_UART5_BASE+STM32_USART_CR2_OFFSET) # define STM32_UART5_CR3 (STM32_UART5_BASE+STM32_USART_CR3_OFFSET) @@ -142,7 +142,7 @@ # define STM32_UART5_TDR (STM32_UART5_BASE+STM32_USART_TDR_OFFSET) #endif -#if STM32F7_NUART > 2 +#if STM32_NUART > 2 # define STM32_UART7_CR1 (STM32_UART7_BASE+STM32_USART_CR1_OFFSET) # define STM32_UART7_CR2 (STM32_UART7_BASE+STM32_USART_CR2_OFFSET) # define STM32_UART7_CR3 (STM32_UART7_BASE+STM32_USART_CR3_OFFSET) @@ -157,7 +157,7 @@ # define STM32_UART7_TDR (STM32_UART7_BASE+STM32_USART_TDR_OFFSET) #endif -#if STM32F7_NUART > 3 +#if STM32_NUART > 3 # define STM32_UART8_CR1 (STM32_UART8_BASE+STM32_USART_CR1_OFFSET) # define STM32_UART8_CR2 (STM32_UART8_BASE+STM32_USART_CR2_OFFSET) # define STM32_UART8_CR3 (STM32_UART8_BASE+STM32_USART_CR3_OFFSET) @@ -356,5 +356,5 @@ #define USART_TDR_SHIFT (0) /* Bits 8:0: Transmit data value */ #define USART_TDR_MASK (0x1ff << USART_TDR_SHIFT) -#endif /* CONFIG_STM32F7_STM32F74XX || CONFIG_STM32F7_STM32F75XX */ +#endif /* CONFIG_STM32_STM32F74XX || CONFIG_STM32_STM32F75XX */ #endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F74XX77XX_UART_H */ diff --git a/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_dma.h b/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_dma.h index dbe7de5cf2f0b..208693831dfe5 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_dma.h +++ b/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_dma.h @@ -29,7 +29,7 @@ #include -#if defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) +#if defined(CONFIG_STM32_STM32F76XX) || defined(CONFIG_STM32_STM32F77XX) /**************************************************************************** * Pre-processor Definitions @@ -585,5 +585,5 @@ #define DMAMAP_QUADSPI_1 STM32_DMA_MAP(DMA2,DMA_STREAM2,DMA_CHAN11) #define DMAMAP_SDMMC2_2 STM32_DMA_MAP(DMA2,DMA_STREAM5,DMA_CHAN11) -#endif /* CONFIG_STM32F7_STM32F76XX || CONFIG_STM32F7_STM32F77XX */ +#endif /* CONFIG_STM32_STM32F76XX || CONFIG_STM32_STM32F77XX */ #endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F76XX77XX_DMA_H */ diff --git a/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_flash.h b/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_flash.h index 84e638d078a67..99463d161364e 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_flash.h +++ b/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_flash.h @@ -29,10 +29,10 @@ /* Flash size is known from the chip selection: * - * When CONFIG_STM32F7_FLASH_OVERRIDE_DEFAULT is set the - * CONFIG_STM32F7_FLASH_CONFIG_x selects the default FLASH size based on + * When CONFIG_STM32_FLASH_OVERRIDE_DEFAULT is set the + * CONFIG_STM32_FLASH_CONFIG_x selects the default FLASH size based on * the chip part number. - * This value can be overridden with CONFIG_STM32F7_FLASH_OVERRIDE_x + * This value can be overridden with CONFIG_STM32_FLASH_OVERRIDE_x * * Parts STM32F74xxE have 512Kb of FLASH * Parts STM32F74xxG have 1024Kb of FLASH @@ -42,53 +42,53 @@ #define _K(x) ((x)*1024) -#if !defined(CONFIG_STM32F7_FLASH_OVERRIDE_DEFAULT) && \ - !defined(CONFIG_STM32F7_FLASH_OVERRIDE_E) && \ - !defined(CONFIG_STM32F7_FLASH_OVERRIDE_G) && \ - !defined(CONFIG_STM32F7_FLASH_OVERRIDE_I) && \ - !defined(CONFIG_STM32F7_FLASH_CONFIG_E) && \ - !defined(CONFIG_STM32F7_FLASH_CONFIG_G) && \ - !defined(CONFIG_STM32F7_FLASH_CONFIG_I) -# define CONFIG_STM32F7_FLASH_OVERRIDE_E +#if !defined(CONFIG_STM32_FLASH_OVERRIDE_DEFAULT) && \ + !defined(CONFIG_STM32_FLASH_OVERRIDE_E) && \ + !defined(CONFIG_STM32_FLASH_OVERRIDE_G) && \ + !defined(CONFIG_STM32_FLASH_OVERRIDE_I) && \ + !defined(CONFIG_STM32_FLASH_CONFIG_E) && \ + !defined(CONFIG_STM32_FLASH_CONFIG_G) && \ + !defined(CONFIG_STM32_FLASH_CONFIG_I) +# define CONFIG_STM32_FLASH_OVERRIDE_E # warning "Flash size not defined defaulting to 512KiB (E)" #endif -#if !defined(CONFIG_STM32F7_FLASH_OVERRIDE_DEFAULT) +#if !defined(CONFIG_STM32_FLASH_OVERRIDE_DEFAULT) -# undef CONFIG_STM32F7_FLASH_CONFIG_E -# undef CONFIG_STM32F7_FLASH_CONFIG_G -# undef CONFIG_STM32F7_FLASH_CONFIG_I +# undef CONFIG_STM32_FLASH_CONFIG_E +# undef CONFIG_STM32_FLASH_CONFIG_G +# undef CONFIG_STM32_FLASH_CONFIG_I -# if defined(CONFIG_STM32F7_FLASH_OVERRIDE_E) +# if defined(CONFIG_STM32_FLASH_OVERRIDE_E) -# define CONFIG_STM32F7_FLASH_CONFIG_E +# define CONFIG_STM32_FLASH_CONFIG_E -# elif defined(CONFIG_STM32F7_FLASH_OVERRIDE_G) +# elif defined(CONFIG_STM32_FLASH_OVERRIDE_G) -# define CONFIG_STM32F7_FLASH_CONFIG_G +# define CONFIG_STM32_FLASH_CONFIG_G -# elif defined(CONFIG_STM32F7_FLASH_OVERRIDE_I) +# elif defined(CONFIG_STM32_FLASH_OVERRIDE_I) -# define CONFIG_STM32F7_FLASH_CONFIG_I +# define CONFIG_STM32_FLASH_CONFIG_I # endif #endif -#if defined(CONFIG_STM32F7_FLASH_CONFIG_E) +#if defined(CONFIG_STM32_FLASH_CONFIG_E) # define STM32_FLASH_NPAGES 6 # define STM32_FLASH_SIZE _K((4 * 32) + (1 * 128) + (1 * 256)) # define STM32_FLASH_SIZES {_K(32), _K(32), _K(32), _K(32), \ _K(128), _K(256)} -#elif defined(CONFIG_STM32F7_FLASH_CONFIG_G) +#elif defined(CONFIG_STM32_FLASH_CONFIG_G) # define STM32_FLASH_NPAGES 8 # define STM32_FLASH_SIZE _K((4 * 32) + (1 * 128) + (3 * 256)) # define STM32_FLASH_SIZES {_K(32), _K(32), _K(32), _K(32), \ _K(128), _K(256), _K(256), _K(256)} -#elif defined(CONFIG_STM32F7_FLASH_CONFIG_I) +#elif defined(CONFIG_STM32_FLASH_CONFIG_I) # define STM32_FLASH_NPAGES 12 # define STM32_FLASH_SIZE _K((4 * 32) + (1 * 128) + (7 * 256)) diff --git a/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_gpio.h b/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_gpio.h index dc76911406292..a63ce45ffc1d0 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_gpio.h +++ b/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_gpio.h @@ -30,7 +30,7 @@ #include #include -#if defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) +#if defined(CONFIG_STM32_STM32F76XX) || defined(CONFIG_STM32_STM32F77XX) /**************************************************************************** * Pre-processor Definitions @@ -51,7 +51,7 @@ /* Register Addresses *******************************************************/ -#if STM32F7_NGPIO > 0 +#if STM32_NGPIO > 0 # define STM32_GPIOA_MODER (STM32_GPIOA_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOA_OTYPER (STM32_GPIOA_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOA_OSPEED (STM32_GPIOA_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -64,7 +64,7 @@ # define STM32_GPIOA_AFRH (STM32_GPIOA_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32F7_NGPIO > 1 +#if STM32_NGPIO > 1 # define STM32_GPIOB_MODER (STM32_GPIOB_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOB_OTYPER (STM32_GPIOB_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOB_OSPEED (STM32_GPIOB_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -77,7 +77,7 @@ # define STM32_GPIOB_AFRH (STM32_GPIOB_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32F7_NGPIO > 2 +#if STM32_NGPIO > 2 # define STM32_GPIOC_MODER (STM32_GPIOC_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOC_OTYPER (STM32_GPIOC_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOC_OSPEED (STM32_GPIOC_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -90,7 +90,7 @@ # define STM32_GPIOC_AFRH (STM32_GPIOC_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32F7_NGPIO > 3 +#if STM32_NGPIO > 3 # define STM32_GPIOD_MODER (STM32_GPIOD_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOD_OTYPER (STM32_GPIOD_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOD_OSPEED (STM32_GPIOD_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -103,7 +103,7 @@ # define STM32_GPIOD_AFRH (STM32_GPIOD_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32F7_NGPIO > 4 +#if STM32_NGPIO > 4 # define STM32_GPIOE_MODER (STM32_GPIOE_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOE_OTYPER (STM32_GPIOE_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOE_OSPEED (STM32_GPIOE_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -116,7 +116,7 @@ # define STM32_GPIOE_AFRH (STM32_GPIOE_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32F7_NGPIO > 5 +#if STM32_NGPIO > 5 # define STM32_GPIOF_MODER (STM32_GPIOF_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOF_OTYPER (STM32_GPIOF_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOF_OSPEED (STM32_GPIOF_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -129,7 +129,7 @@ # define STM32_GPIOF_AFRH (STM32_GPIOF_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32F7_NGPIO > 6 +#if STM32_NGPIO > 6 # define STM32_GPIOG_MODER (STM32_GPIOG_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOG_OTYPER (STM32_GPIOG_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOG_OSPEED (STM32_GPIOG_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -142,7 +142,7 @@ # define STM32_GPIOG_AFRH (STM32_GPIOG_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32F7_NGPIO > 7 +#if STM32_NGPIO > 7 # define STM32_GPIOH_MODER (STM32_GPIOH_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOH_OTYPER (STM32_GPIOH_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOH_OSPEED (STM32_GPIOH_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -155,7 +155,7 @@ # define STM32_GPIOH_AFRH (STM32_GPIOH_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32F7_NGPIO > 8 +#if STM32_NGPIO > 8 # define STM32_GPIOI_MODER (STM32_GPIOI_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOI_OTYPER (STM32_GPIOI_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOI_OSPEED (STM32_GPIOI_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -168,7 +168,7 @@ # define STM32_GPIOI_AFRH (STM32_GPIOI_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32F7_NGPIO > 9 +#if STM32_NGPIO > 9 # define STM32_GPIOJ_MODER (STM32_GPIOJ_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOJ_OTYPER (STM32_GPIOJ_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOJ_OSPEED (STM32_GPIOJ_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -181,7 +181,7 @@ # define STM32_GPIOJ_AFRH (STM32_GPIOJ_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32F7_NGPIO > 10 +#if STM32_NGPIO > 10 # define STM32_GPIOK_MODER (STM32_GPIOK_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOK_OTYPER (STM32_GPIOK_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOK_OSPEED (STM32_GPIOK_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -386,5 +386,5 @@ #define GPIO_AFRH15_SHIFT (28) #define GPIO_AFRH15_MASK (15 << GPIO_AFRH15_SHIFT) -#endif /* CONFIG_STM32F7_STM32F76XX || CONFIG_STM32F7_STM32F77XX */ +#endif /* CONFIG_STM32_STM32F76XX || CONFIG_STM32_STM32F77XX */ #endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F76XX77XX_GPIO_H */ diff --git a/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_memorymap.h b/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_memorymap.h index 1f9e1673df36a..b60c2f882c580 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_memorymap.h +++ b/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_memorymap.h @@ -29,7 +29,7 @@ #include -#if defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) +#if defined(CONFIG_STM32_STM32F76XX) || defined(CONFIG_STM32_STM32F77XX) /**************************************************************************** * Pre-processor Definitions @@ -205,5 +205,5 @@ #define STM32_DEBUGMCU_BASE 0xe0042000 -#endif /* CONFIG_STM32F7_STM32F74XX || CONFIG_STM32F7_STM32F75XX */ +#endif /* CONFIG_STM32_STM32F74XX || CONFIG_STM32_STM32F75XX */ #endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F74XX75XX_MEMORYMAP_H */ diff --git a/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_pinmap.h b/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_pinmap.h index 82d795a98c044..5ef7ae8ecde01 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_pinmap.h +++ b/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_pinmap.h @@ -31,7 +31,7 @@ #include "stm32_gpio.h" -#if defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) +#if defined(CONFIG_STM32_STM32F76XX) || defined(CONFIG_STM32_STM32F77XX) /**************************************************************************** * Pre-processor Definitions @@ -916,7 +916,7 @@ * * Note that the below configures GPIO_SPEED_50MHz I/O, that means for using * the SDIO that you must enable I/O Compensation via the configuration - * option CONFIG_STM32F7_SYSCFG_IOCOMPENSATION=y. + * option CONFIG_STM32_SYSCFG_IOCOMPENSATION=y. */ #define GPIO_SDMMC1_CK_0 (GPIO_ALT|GPIO_AF12|GPIO_PORTC|GPIO_PIN12) @@ -1330,5 +1330,5 @@ #define GPIO_UART8_RX_0 (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN0) #define GPIO_UART8_TX_0 (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN1) -#endif /* CONFIG_STM32F7_STM32F76XX || CONFIG_STM32F7_STM32F77XX */ +#endif /* CONFIG_STM32_STM32F76XX || CONFIG_STM32_STM32F77XX */ #endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F76XX77XX_PINMAP_H */ diff --git a/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_pwr.h b/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_pwr.h index 54afc5d9d3d7f..b6d554f765b23 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_pwr.h +++ b/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_pwr.h @@ -29,7 +29,7 @@ #include -#if defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) +#if defined(CONFIG_STM32_STM32F76XX) || defined(CONFIG_STM32_STM32F77XX) /**************************************************************************** * Pre-processor Definitions @@ -143,5 +143,5 @@ #define PWR_CSR2_EWUP5 (1 << 12) /* Bit 12: Enable wakeup pin for PI8 */ #define PWR_CSR2_EWUP6 (1 << 13) /* Bit 13: Enable wakeup pin for PI11 */ -#endif /* CONFIG_STM32F7_STM32F76XX || CONFIG_STM32F7_STM32F77XX */ +#endif /* CONFIG_STM32_STM32F76XX || CONFIG_STM32_STM32F77XX */ #endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F76XX77XX_PWR_H */ diff --git a/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_rcc.h b/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_rcc.h index 7b72de0e625a2..6a56b4494b5dd 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_rcc.h +++ b/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_rcc.h @@ -29,7 +29,7 @@ #include -#if defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) +#if defined(CONFIG_STM32_STM32F76XX) || defined(CONFIG_STM32_STM32F77XX) /**************************************************************************** * Pre-processor Definitions @@ -756,5 +756,5 @@ # define RCC_DCKCFGR2_DSISEL_PHY (0 << RCC_DCKCFGR2_DSISEL_SHIFT) /* DSI PHY sources DSI clock */ # define RCC_DCKCFGR2_DSISEL_SYSCLK (1 << RCC_DCKCFGR2_DSISEL_SHIFT) /* System clock is selected as DSI clock */ -#endif /* CONFIG_STM32F7_STM32F76XX || CONFIG_STM32F7_STM32F77XX */ +#endif /* CONFIG_STM32_STM32F76XX || CONFIG_STM32_STM32F77XX */ #endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F76XX77XX_RCC_H */ diff --git a/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_syscfg.h b/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_syscfg.h index 11b42882cff3b..ef63b7dede8e1 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_syscfg.h +++ b/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_syscfg.h @@ -30,7 +30,7 @@ #include #include "chip.h" -#if defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) +#if defined(CONFIG_STM32_STM32F76XX) || defined(CONFIG_STM32_STM32F77XX) /**************************************************************************** * Pre-processor Definitions @@ -163,5 +163,5 @@ #define SYSCFG_CMPCR_CMPPD (1 << 0) /* Bit 0: Compensation cell power-down */ #define SYSCFG_CMPCR_READY (1 << 8) /* Bit 8: Compensation cell ready flag */ -#endif /* CONFIG_STM32F7_STM32F76XX || CONFIG_STM32F7_STM32F77XX */ +#endif /* CONFIG_STM32_STM32F76XX || CONFIG_STM32_STM32F77XX */ #endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F76XX77XX_SYSCFG_H */ diff --git a/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_tim.h b/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_tim.h index fc2fa7bec8174..b2586544aa498 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_tim.h +++ b/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_tim.h @@ -99,7 +99,7 @@ /* Advanced Timers - TIM1 and TIM8 */ -#if STM32F7_NATIM > 0 +#if STM32_NATIM > 0 # define STM32_TIM1_CR1 (STM32_TIM1_BASE+STM32_ATIM_CR1_OFFSET) # define STM32_TIM1_CR2 (STM32_TIM1_BASE+STM32_ATIM_CR2_OFFSET) # define STM32_TIM1_SMCR (STM32_TIM1_BASE+STM32_ATIM_SMCR_OFFSET) @@ -127,7 +127,7 @@ # define STM32_TIM1_AF2 (STM32_TIM1_BASE+STM32_ATIM_AF2_OFFSET) #endif -#if STM32F7_NATIM > 1 +#if STM32_NATIM > 1 # define STM32_TIM8_CR1 (STM32_TIM8_BASE+STM32_ATIM_CR1_OFFSET) # define STM32_TIM8_CR2 (STM32_TIM8_BASE+STM32_ATIM_CR2_OFFSET) # define STM32_TIM8_SMCR (STM32_TIM8_BASE+STM32_ATIM_SMCR_OFFSET) @@ -159,7 +159,7 @@ * All timers are 16-bit except for TIM2 and 5 are 32-bit */ -#if (STM32F7_NGTIM16+STM32F7_NGTIM32) > 0 +#if (STM32_NGTIM16+STM32_NGTIM32) > 0 # define STM32_TIM2_CR1 (STM32_TIM2_BASE+STM32_GTIM_CR1_OFFSET) # define STM32_TIM2_CR2 (STM32_TIM2_BASE+STM32_GTIM_CR2_OFFSET) # define STM32_TIM2_SMCR (STM32_TIM2_BASE+STM32_GTIM_SMCR_OFFSET) @@ -181,7 +181,7 @@ # define STM32_TIM2_OR (STM32_TIM2_BASE+STM32_GTIM_OR_OFFSET) #endif -#if (STM32F7_NGTIM16+STM32F7_NGTIM32) > 1 +#if (STM32_NGTIM16+STM32_NGTIM32) > 1 # define STM32_TIM3_CR1 (STM32_TIM3_BASE+STM32_GTIM_CR1_OFFSET) # define STM32_TIM3_CR2 (STM32_TIM3_BASE+STM32_GTIM_CR2_OFFSET) # define STM32_TIM3_SMCR (STM32_TIM3_BASE+STM32_GTIM_SMCR_OFFSET) @@ -202,7 +202,7 @@ # define STM32_TIM3_DMAR (STM32_TIM3_BASE+STM32_GTIM_DMAR_OFFSET) #endif -#if (STM32F7_NGTIM16+STM32F7_NGTIM32) > 2 +#if (STM32_NGTIM16+STM32_NGTIM32) > 2 # define STM32_TIM4_CR1 (STM32_TIM4_BASE+STM32_GTIM_CR1_OFFSET) # define STM32_TIM4_CR2 (STM32_TIM4_BASE+STM32_GTIM_CR2_OFFSET) # define STM32_TIM4_SMCR (STM32_TIM4_BASE+STM32_GTIM_SMCR_OFFSET) @@ -223,7 +223,7 @@ # define STM32_TIM4_DMAR (STM32_TIM4_BASE+STM32_GTIM_DMAR_OFFSET) #endif -#if (STM32F7_NGTIM16+STM32F7_NGTIM32) > 3 +#if (STM32_NGTIM16+STM32_NGTIM32) > 3 # define STM32_TIM5_CR1 (STM32_TIM5_BASE+STM32_GTIM_CR1_OFFSET) # define STM32_TIM5_CR2 (STM32_TIM5_BASE+STM32_GTIM_CR2_OFFSET) # define STM32_TIM5_SMCR (STM32_TIM5_BASE+STM32_GTIM_SMCR_OFFSET) @@ -250,7 +250,7 @@ * (2) TIM9 and TIM12 differ from the others. */ -#if STM32F7_NGTIMNDMA > 0 +#if STM32_NGTIMNDMA > 0 # define STM32_TIM9_CR1 (STM32_TIM9_BASE+STM32_GTIM_CR1_OFFSET) # define STM32_TIM9_CR2 (STM32_TIM9_BASE+STM32_GTIM_CR2_OFFSET) # define STM32_TIM9_DIER (STM32_TIM9_BASE+STM32_GTIM_DIER_OFFSET) @@ -265,7 +265,7 @@ # define STM32_TIM9_CCR2 (STM32_TIM9_BASE+STM32_GTIM_CCR2_OFFSET) #endif -#if STM32F7_NGTIMNDMA > 1 +#if STM32_NGTIMNDMA > 1 # define STM32_TIM10_CR1 (STM32_TIM10_BASE+STM32_GTIM_CR1_OFFSET) # define STM32_TIM10_DIER (STM32_TIM10_BASE+STM32_GTIM_DIER_OFFSET) # define STM32_TIM10_SR (STM32_TIM10_BASE+STM32_GTIM_SR_OFFSET) @@ -278,7 +278,7 @@ # define STM32_TIM10_CCR1 (STM32_TIM10_BASE+STM32_GTIM_CCR1_OFFSET) #endif -#if STM32F7_NGTIMNDMA > 2 +#if STM32_NGTIMNDMA > 2 # define STM32_TIM11_CR1 (STM32_TIM11_BASE+STM32_GTIM_CR1_OFFSET) # define STM32_TIM11_DIER (STM32_TIM11_BASE+STM32_GTIM_DIER_OFFSET) # define STM32_TIM11_SR (STM32_TIM11_BASE+STM32_GTIM_SR_OFFSET) @@ -292,7 +292,7 @@ # define STM32_TIM11_OR (STM32_TIM11_BASE+STM32_GTIM_OR_OFFSET) #endif -#if STM32F7_NGTIMNDMA > 3 +#if STM32_NGTIMNDMA > 3 # define STM32_TIM12_CR1 (STM32_TIM12_BASE+STM32_GTIM_CR1_OFFSET) # define STM32_TIM12_CR2 (STM32_TIM9_BASE+STM32_GTIM_CR2_OFFSET) # define STM32_TIM12_DIER (STM32_TIM12_BASE+STM32_GTIM_DIER_OFFSET) @@ -307,7 +307,7 @@ # define STM32_TIM12_CCR2 (STM32_TIM12_BASE+STM32_GTIM_CCR2_OFFSET) #endif -#if STM32F7_NGTIMNDMA > 4 +#if STM32_NGTIMNDMA > 4 # define STM32_TIM13_CR1 (STM32_TIM13_BASE+STM32_GTIM_CR1_OFFSET) # define STM32_TIM13_DIER (STM32_TIM13_BASE+STM32_GTIM_DIER_OFFSET) # define STM32_TIM13_SR (STM32_TIM13_BASE+STM32_GTIM_SR_OFFSET) @@ -320,7 +320,7 @@ # define STM32_TIM13_CCR1 (STM32_TIM13_BASE+STM32_GTIM_CCR1_OFFSET) #endif -#if STM32F7_NGTIMNDMA > 5 +#if STM32_NGTIMNDMA > 5 # define STM32_TIM14_CR1 (STM32_TIM14_BASE+STM32_GTIM_CR1_OFFSET) # define STM32_TIM14_DIER (STM32_TIM14_BASE+STM32_GTIM_DIER_OFFSET) # define STM32_TIM14_SR (STM32_TIM14_BASE+STM32_GTIM_SR_OFFSET) @@ -335,7 +335,7 @@ /* Basic Timers - TIM6 and TIM7 */ -#if STM32F7_NBTIM > 0 +#if STM32_NBTIM > 0 # define STM32_TIM6_CR1 (STM32_TIM6_BASE+STM32_BTIM_CR1_OFFSET) # define STM32_TIM6_CR2 (STM32_TIM6_BASE+STM32_BTIM_CR2_OFFSET) # define STM32_TIM6_DIER (STM32_TIM6_BASE+STM32_BTIM_DIER_OFFSET) @@ -346,7 +346,7 @@ # define STM32_TIM6_ARR (STM32_TIM6_BASE+STM32_BTIM_ARR_OFFSET) #endif -#if STM32F7_NBTIM > 1 +#if STM32_NBTIM > 1 # define STM32_TIM7_CR1 (STM32_TIM7_BASE+STM32_BTIM_CR1_OFFSET) # define STM32_TIM7_CR2 (STM32_TIM7_BASE+STM32_BTIM_CR2_OFFSET) # define STM32_TIM7_DIER (STM32_TIM7_BASE+STM32_BTIM_DIER_OFFSET) diff --git a/arch/arm/src/stm32f7/stm32.h b/arch/arm/src/stm32f7/stm32.h new file mode 100644 index 0000000000000..99c030c63377e --- /dev/null +++ b/arch/arm/src/stm32f7/stm32.h @@ -0,0 +1,60 @@ +/**************************************************************************** + * arch/arm/src/stm32f7/stm32.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32F7_STM32_H +#define __ARCH_ARM_SRC_STM32F7_STM32_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include +#include + +#include "arm_internal.h" + +/* Peripherals **************************************************************/ + +#include "chip.h" +#include "stm32_adc.h" +#include "stm32_can.h" +#include "stm32_dbgmcu.h" +#include "stm32_dma.h" +#include "stm32_exti.h" +#include "stm32_fmc.h" +#include "stm32_gpio.h" +#include "stm32_i2c.h" +#include "stm32_ltdc.h" +#include "stm32_pwr.h" +#include "stm32_rcc.h" +#include "stm32_rtc.h" +#include "stm32_sdmmc.h" +#include "stm32_spi.h" +#include "stm32_i2s.h" +#include "stm32_tim.h" +#include "stm32_uart.h" +#include "stm32_lowputc.h" +#include "stm32_ethernet.h" + +#endif /* __ARCH_ARM_SRC_STM32F7_STM32_H */ diff --git a/arch/arm/src/stm32f7/stm32_adc.c b/arch/arm/src/stm32f7/stm32_adc.c index e875c19c71a54..90f56057b4ca5 100644 --- a/arch/arm/src/stm32f7/stm32_adc.c +++ b/arch/arm/src/stm32f7/stm32_adc.c @@ -59,7 +59,7 @@ /* STM32 ADC "lower-half" support must be enabled */ -#ifdef CONFIG_STM32F7_ADC +#ifdef CONFIG_STM32_ADC /* This implementation is for the STM32 ADC IP version 1 */ @@ -121,21 +121,21 @@ /* ADC scan mode support */ -#ifndef CONFIG_STM32F7_ADC1_SCAN -# define CONFIG_STM32F7_ADC1_SCAN 0 +#ifndef CONFIG_STM32_ADC1_SCAN +# define CONFIG_STM32_ADC1_SCAN 0 #endif -#ifndef CONFIG_STM32F7_ADC2_SCAN -# define CONFIG_STM32F7_ADC2_SCAN 0 +#ifndef CONFIG_STM32_ADC2_SCAN +# define CONFIG_STM32_ADC2_SCAN 0 #endif -#ifndef CONFIG_STM32F7_ADC3_SCAN -# define CONFIG_STM32F7_ADC3_SCAN 0 +#ifndef CONFIG_STM32_ADC3_SCAN +# define CONFIG_STM32_ADC3_SCAN 0 #endif /* We have to support ADC callbacks if default ADC interrupts or * DMA transfer are enabled */ -#if !defined(CONFIG_STM32F7_ADC_NOIRQ) || defined(ADC_HAVE_DMA) +#if !defined(CONFIG_STM32_ADC_NOIRQ) || defined(ADC_HAVE_DMA) # define ADC_HAVE_CB #else # undef ADC_HAVE_CB @@ -184,7 +184,7 @@ struct adccmn_data_s struct stm32_dev_s { -#ifdef CONFIG_STM32F7_ADC_LL_OPS +#ifdef CONFIG_STM32_ADC_LL_OPS const struct stm32_adc_ops_s *llops; /* Low-level ADC ops */ struct adc_dev_s *dev; /* Upper-half ADC reference */ #endif @@ -210,7 +210,7 @@ struct stm32_dev_s uint16_t dmabatch; /* Number of conversions for DMA batch */ #endif bool scan; /* True: Scan mode */ -#ifdef CONFIG_STM32F7_ADC_CHANGE_SAMPLETIME +#ifdef CONFIG_STM32_ADC_CHANGE_SAMPLETIME /* Sample time selection. These bits must be written only when ADON=0. * REVISIT: this takes too much space. We need only 3 bits per channel. */ @@ -252,7 +252,7 @@ struct stm32_dev_s /* List of selected ADC channels to sample */ - uint8_t r_chanlist[CONFIG_STM32F7_ADC_MAX_SAMPLES]; + uint8_t r_chanlist[CONFIG_STM32_ADC_MAX_SAMPLES]; #ifdef ADC_HAVE_INJECTED /* List of selected ADC injected channels to sample */ @@ -293,10 +293,10 @@ static void adc_rccreset(struct stm32_dev_s *priv, bool reset); /* ADC Interrupt Handler */ -#ifndef CONFIG_STM32F7_ADC_NOIRQ +#ifndef CONFIG_STM32_ADC_NOIRQ static int adc_interrupt(struct adc_dev_s *dev); static int adc123_interrupt(int irq, void *context, void *arg); -#endif /* CONFIG_STM32F7_ADC_NOIRQ */ +#endif /* CONFIG_STM32_ADC_NOIRQ */ /* ADC Driver Methods */ @@ -321,7 +321,7 @@ static void adc_timstart(struct stm32_dev_s *priv, bool enable); static int adc_timinit(struct stm32_dev_s *priv); #endif -#if defined(ADC_HAVE_DMA) && !defined(CONFIG_STM32F7_ADC_NOIRQ) +#if defined(ADC_HAVE_DMA) && !defined(CONFIG_STM32_ADC_NOIRQ) static void adc_dmaconvcallback(DMA_HANDLE handle, uint8_t isr, void *arg); #endif @@ -346,7 +346,7 @@ static int adc_jextcfg_set(struct stm32_dev_s *priv, uint32_t jextcfg); static void adc_dumpregs(struct stm32_dev_s *priv); -#ifdef CONFIG_STM32F7_ADC_LL_OPS +#ifdef CONFIG_STM32_ADC_LL_OPS static int adc_llops_setup(struct stm32_adc_dev_s *dev); static void adc_llops_shutdown(struct stm32_adc_dev_s *dev); static void adc_intack(struct stm32_adc_dev_s *dev, uint32_t source); @@ -375,7 +375,7 @@ static uint32_t adc_injget(struct stm32_adc_dev_s *dev, uint8_t chan); static void adc_llops_inj_startconv(struct stm32_adc_dev_s *dev, bool enable); # endif -# ifdef CONFIG_STM32F7_ADC_CHANGE_SAMPLETIME +# ifdef CONFIG_STM32_ADC_CHANGE_SAMPLETIME static void adc_sampletime_set(struct stm32_adc_dev_s *dev, struct adc_sample_time_s *time_samples); static void adc_sampletime_write(struct stm32_adc_dev_s *dev); @@ -403,7 +403,7 @@ static const struct adc_ops_s g_adcops = /* Publicly visible ADC lower-half operations */ -#ifdef CONFIG_STM32F7_ADC_LL_OPS +#ifdef CONFIG_STM32_ADC_LL_OPS static const struct stm32_adc_ops_s g_adc_llops = { .setup = adc_llops_setup, @@ -428,7 +428,7 @@ static const struct stm32_adc_ops_s g_adc_llops = .inj_get = adc_injget, .inj_startconv = adc_llops_inj_startconv, # endif -# ifdef CONFIG_STM32F7_ADC_CHANGE_SAMPLETIME +# ifdef CONFIG_STM32_ADC_CHANGE_SAMPLETIME .stime_set = adc_sampletime_set, .stime_write = adc_sampletime_write, # endif @@ -454,27 +454,27 @@ struct adccmn_data_s g_adc123_cmn = /* ADC1 state */ -#ifdef CONFIG_STM32F7_ADC1 +#ifdef CONFIG_STM32_ADC1 #ifdef ADC1_HAVE_DMA -static uint16_t g_adc1_dmabuffer[CONFIG_STM32F7_ADC_MAX_SAMPLES * - CONFIG_STM32F7_ADC1_DMA_BATCH]; +static uint16_t g_adc1_dmabuffer[CONFIG_STM32_ADC_MAX_SAMPLES * + CONFIG_STM32_ADC1_DMA_BATCH]; #endif static struct stm32_dev_s g_adcpriv1 = { -#ifdef CONFIG_STM32F7_ADC_LL_OPS +#ifdef CONFIG_STM32_ADC_LL_OPS .llops = &g_adc_llops, #endif -#ifndef CONFIG_STM32F7_ADC_NOIRQ +#ifndef CONFIG_STM32_ADC_NOIRQ .irq = STM32_IRQ_ADC, .isr = adc123_interrupt, -#endif /* CONFIG_STM32F7_ADC_NOIRQ */ +#endif /* CONFIG_STM32_ADC_NOIRQ */ .cmn = &ADC1CMN_DATA, .intf = 1, .initialized = 0, - .anioc_trg = CONFIG_STM32F7_ADC1_ANIOC_TRIGGER, - .resolution = CONFIG_STM32F7_ADC1_RESOLUTION, + .anioc_trg = CONFIG_STM32_ADC1_ANIOC_TRIGGER, + .resolution = CONFIG_STM32_ADC1_RESOLUTION, .base = STM32_ADC1_BASE, #ifdef ADC1_HAVE_EXTCFG .extcfg = ADC1_EXTCFG_VALUE, @@ -483,19 +483,19 @@ static struct stm32_dev_s g_adcpriv1 = .jextcfg = ADC1_JEXTCFG_VALUE, #endif #ifdef ADC1_HAVE_TIMER - .trigger = CONFIG_STM32F7_ADC1_TIMTRIG, + .trigger = CONFIG_STM32_ADC1_TIMTRIG, .tbase = ADC1_TIMER_BASE, .pclck = ADC1_TIMER_PCLK_FREQUENCY, - .freq = CONFIG_STM32F7_ADC1_SAMPLE_FREQUENCY, + .freq = CONFIG_STM32_ADC1_SAMPLE_FREQUENCY, #endif #ifdef ADC1_HAVE_DMA .dmachan = ADC1_DMA_CHAN, - .dmacfg = CONFIG_STM32F7_ADC1_DMA_CFG, + .dmacfg = CONFIG_STM32_ADC1_DMA_CFG, .hasdma = true, .r_dmabuffer = g_adc1_dmabuffer, - .dmabatch = CONFIG_STM32F7_ADC1_DMA_BATCH, + .dmabatch = CONFIG_STM32_ADC1_DMA_BATCH, #endif - .scan = CONFIG_STM32F7_ADC1_SCAN, + .scan = CONFIG_STM32_ADC1_SCAN, #ifdef CONFIG_PM .pm_callback = { @@ -513,27 +513,27 @@ static struct adc_dev_s g_adcdev1 = /* ADC2 state */ -#ifdef CONFIG_STM32F7_ADC2 +#ifdef CONFIG_STM32_ADC2 #ifdef ADC2_HAVE_DMA -static uint16_t g_adc2_dmabuffer[CONFIG_STM32F7_ADC_MAX_SAMPLES * - CONFIG_STM32F7_ADC2_DMA_BATCH]; +static uint16_t g_adc2_dmabuffer[CONFIG_STM32_ADC_MAX_SAMPLES * + CONFIG_STM32_ADC2_DMA_BATCH]; #endif static struct stm32_dev_s g_adcpriv2 = { -#ifdef CONFIG_STM32F7_ADC_LL_OPS +#ifdef CONFIG_STM32_ADC_LL_OPS .llops = &g_adc_llops, #endif -#ifndef CONFIG_STM32F7_ADC_NOIRQ +#ifndef CONFIG_STM32_ADC_NOIRQ .irq = STM32_IRQ_ADC, .isr = adc123_interrupt, -#endif /* CONFIG_STM32F7_ADC_NOIRQ */ +#endif /* CONFIG_STM32_ADC_NOIRQ */ .cmn = &ADC2CMN_DATA, .intf = 2, .initialized = 0, - .anioc_trg = CONFIG_STM32F7_ADC2_ANIOC_TRIGGER, - .resolution = CONFIG_STM32F7_ADC2_RESOLUTION, + .anioc_trg = CONFIG_STM32_ADC2_ANIOC_TRIGGER, + .resolution = CONFIG_STM32_ADC2_RESOLUTION, .base = STM32_ADC2_BASE, #ifdef ADC2_HAVE_EXTCFG .extcfg = ADC2_EXTCFG_VALUE, @@ -542,19 +542,19 @@ static struct stm32_dev_s g_adcpriv2 = .jextcfg = ADC2_JEXTCFG_VALUE, #endif #ifdef ADC2_HAVE_TIMER - .trigger = CONFIG_STM32F7_ADC2_TIMTRIG, + .trigger = CONFIG_STM32_ADC2_TIMTRIG, .tbase = ADC2_TIMER_BASE, .pclck = ADC2_TIMER_PCLK_FREQUENCY, - .freq = CONFIG_STM32F7_ADC2_SAMPLE_FREQUENCY, + .freq = CONFIG_STM32_ADC2_SAMPLE_FREQUENCY, #endif #ifdef ADC2_HAVE_DMA .dmachan = ADC2_DMA_CHAN, - .dmacfg = CONFIG_STM32F7_ADC2_DMA_CFG, + .dmacfg = CONFIG_STM32_ADC2_DMA_CFG, .hasdma = true, .r_dmabuffer = g_adc2_dmabuffer, - .dmabatch = CONFIG_STM32F7_ADC2_DMA_BATCH, + .dmabatch = CONFIG_STM32_ADC2_DMA_BATCH, #endif - .scan = CONFIG_STM32F7_ADC2_SCAN, + .scan = CONFIG_STM32_ADC2_SCAN, #ifdef CONFIG_PM .pm_callback = { @@ -572,27 +572,27 @@ static struct adc_dev_s g_adcdev2 = /* ADC3 state */ -#ifdef CONFIG_STM32F7_ADC3 +#ifdef CONFIG_STM32_ADC3 #ifdef ADC3_HAVE_DMA -static uint16_t g_adc3_dmabuffer[CONFIG_STM32F7_ADC_MAX_SAMPLES * - CONFIG_STM32F7_ADC3_DMA_BATCH]; +static uint16_t g_adc3_dmabuffer[CONFIG_STM32_ADC_MAX_SAMPLES * + CONFIG_STM32_ADC3_DMA_BATCH]; #endif static struct stm32_dev_s g_adcpriv3 = { -#ifdef CONFIG_STM32F7_ADC_LL_OPS +#ifdef CONFIG_STM32_ADC_LL_OPS .llops = &g_adc_llops, #endif -#ifndef CONFIG_STM32F7_ADC_NOIRQ +#ifndef CONFIG_STM32_ADC_NOIRQ .irq = STM32_IRQ_ADC, .isr = adc123_interrupt, -#endif /* CONFIG_STM32F7_ADC_NOIRQ */ +#endif /* CONFIG_STM32_ADC_NOIRQ */ .cmn = &ADC3CMN_DATA, .intf = 3, .initialized = 0, - .anioc_trg = CONFIG_STM32F7_ADC3_ANIOC_TRIGGER, - .resolution = CONFIG_STM32F7_ADC3_RESOLUTION, + .anioc_trg = CONFIG_STM32_ADC3_ANIOC_TRIGGER, + .resolution = CONFIG_STM32_ADC3_RESOLUTION, .base = STM32_ADC3_BASE, #ifdef ADC3_HAVE_EXTCFG .extcfg = ADC3_EXTCFG_VALUE, @@ -601,19 +601,19 @@ static struct stm32_dev_s g_adcpriv3 = .jextcfg = ADC3_JEXTCFG_VALUE, #endif #ifdef ADC3_HAVE_TIMER - .trigger = CONFIG_STM32F7_ADC3_TIMTRIG, + .trigger = CONFIG_STM32_ADC3_TIMTRIG, .tbase = ADC3_TIMER_BASE, .pclck = ADC3_TIMER_PCLK_FREQUENCY, - .freq = CONFIG_STM32F7_ADC3_SAMPLE_FREQUENCY, + .freq = CONFIG_STM32_ADC3_SAMPLE_FREQUENCY, #endif #ifdef ADC3_HAVE_DMA .dmachan = ADC3_DMA_CHAN, - .dmacfg = CONFIG_STM32F7_ADC3_DMA_CFG, + .dmacfg = CONFIG_STM32_ADC3_DMA_CFG, .hasdma = true, .r_dmabuffer = g_adc3_dmabuffer, - .dmabatch = CONFIG_STM32F7_ADC3_DMA_BATCH, + .dmabatch = CONFIG_STM32_ADC3_DMA_BATCH, #endif - .scan = CONFIG_STM32F7_ADC3_SCAN, + .scan = CONFIG_STM32_ADC3_SCAN, #ifdef CONFIG_PM .pm_callback = { @@ -1455,7 +1455,7 @@ static void adc_enable(struct stm32_dev_s *priv, bool enable) * ****************************************************************************/ -#if defined(ADC_HAVE_DMA) && !defined(CONFIG_STM32F7_ADC_NOIRQ) +#if defined(ADC_HAVE_DMA) && !defined(CONFIG_STM32_ADC_NOIRQ) static void adc_dmaconvcallback(DMA_HANDLE handle, uint8_t isr, void *arg) { @@ -1587,7 +1587,7 @@ static void adc_sampletime_cfg(struct adc_dev_s *dev) * During sample cycles channel selection bits must remain unchanged. */ -#ifdef CONFIG_STM32F7_ADC_CHANGE_SAMPLETIME +#ifdef CONFIG_STM32_ADC_CHANGE_SAMPLETIME adc_sampletime_write((struct stm32_adc_dev_s *)dev->ad_priv); #else struct stm32_dev_s *priv = (struct stm32_dev_s *)dev->ad_priv; @@ -1673,7 +1673,7 @@ static void adc_dma_start(struct adc_dev_s *dev) priv->dma = stm32_dmachannel(priv->dmachan); -#ifndef CONFIG_STM32F7_ADC_NOIRQ +#ifndef CONFIG_STM32_ADC_NOIRQ /* Start DMA only if standard ADC interrupts used */ stm32_dmasetup(priv->dma, @@ -1853,7 +1853,7 @@ static int adc_setup(struct adc_dev_s *dev) /* Attach the ADC interrupt */ -#ifndef CONFIG_STM32F7_ADC_NOIRQ +#ifndef CONFIG_STM32_ADC_NOIRQ ret = irq_attach(priv->irq, priv->isr, NULL); if (ret < 0) { @@ -1885,7 +1885,7 @@ static int adc_setup(struct adc_dev_s *dev) /* As default conversion is started here */ -#ifndef CONFIG_STM32F7_ADC_NO_STARTUP_CONV +#ifndef CONFIG_STM32_ADC_NO_STARTUP_CONV /* Start regular conversion */ adc_reg_startconv(priv, true); @@ -1909,7 +1909,7 @@ static int adc_setup(struct adc_dev_s *dev) { /* Enable the ADC interrupt */ -#ifndef CONFIG_STM32F7_ADC_NOIRQ +#ifndef CONFIG_STM32_ADC_NOIRQ ainfo("Enable the ADC interrupt: irq=%d\n", priv->irq); up_enable_irq(priv->irq); #endif @@ -1967,7 +1967,7 @@ static void adc_shutdown(struct adc_dev_s *dev) if (priv->cmn->refcount <= 1) { -#ifndef CONFIG_STM32F7_ADC_NOIRQ +#ifndef CONFIG_STM32_ADC_NOIRQ /* Disable ADC interrupts and detach the ADC interrupt handler */ up_disable_irq(priv->irq); @@ -2469,7 +2469,7 @@ static int adc_ioctl(struct adc_dev_s *dev, int cmd, unsigned long arg) return ret; } -#ifndef CONFIG_STM32F7_ADC_NOIRQ +#ifndef CONFIG_STM32_ADC_NOIRQ /**************************************************************************** * Name: adc_interrupt @@ -2570,23 +2570,23 @@ static int adc_interrupt(struct adc_dev_s *dev) static int adc123_interrupt(int irq, void *context, void *arg) { -#ifdef CONFIG_STM32F7_ADC1 +#ifdef CONFIG_STM32_ADC1 adc_interrupt(&g_adcdev1); #endif -#ifdef CONFIG_STM32F7_ADC2 +#ifdef CONFIG_STM32_ADC2 adc_interrupt(&g_adcdev2); #endif -#ifdef CONFIG_STM32F7_ADC3 +#ifdef CONFIG_STM32_ADC3 adc_interrupt(&g_adcdev3); #endif return OK; } -#endif /* CONFIG_STM32F7_ADC_NOIRQ */ +#endif /* CONFIG_STM32_ADC_NOIRQ */ -#ifdef CONFIG_STM32F7_ADC_LL_OPS +#ifdef CONFIG_STM32_ADC_LL_OPS /**************************************************************************** * Name: adc_llops_setup @@ -2821,7 +2821,7 @@ static void adc_llops_inj_startconv(struct stm32_adc_dev_s *dev, * ****************************************************************************/ -#ifdef CONFIG_STM32F7_ADC_CHANGE_SAMPLETIME +#ifdef CONFIG_STM32_ADC_CHANGE_SAMPLETIME static void adc_sampletime_write(struct stm32_adc_dev_s *dev) { struct stm32_dev_s *priv = (struct stm32_dev_s *)dev; @@ -2911,7 +2911,7 @@ void adc_sampletime_set(struct stm32_adc_dev_s *dev, } } } -#endif /* CONFIG_STM32F7_ADC_CHANGE_SAMPLETIME */ +#endif /* CONFIG_STM32_ADC_CHANGE_SAMPLETIME */ /**************************************************************************** * Name: adc_llops_dumpregs @@ -3017,7 +3017,7 @@ static void adc_llops_enable(struct stm32_adc_dev_s *dev, bool enable) adc_enable(priv, enable); } -#endif /* CONFIG_STM32F7_ADC_LL_OPS */ +#endif /* CONFIG_STM32_ADC_LL_OPS */ /**************************************************************************** * Public Functions @@ -3032,7 +3032,7 @@ static void adc_llops_enable(struct stm32_adc_dev_s *dev, bool enable) * The logic allow initialize ADC regular and injected channels. * * The number of injected channels for given ADC is selected from Kconfig - * with CONFIG_STM32F7_ADCx_INJECTED_CHAN definitions + * with CONFIG_STM32_ADCx_INJECTED_CHAN definitions * * The number of regular channels is obtained from the equation: * @@ -3056,9 +3056,9 @@ static void adc_llops_enable(struct stm32_adc_dev_s *dev, bool enable) * chanlist[channels] -> ADC_JSQR_ISQy * * where: - * y = CONFIG_STM32F7_ADCx_INJECTED_CHAN, and y > 0 + * y = CONFIG_STM32_ADCx_INJECTED_CHAN, and y > 0 * - * If CONFIG_STM32F7_ADCx_INJECTED_CHAN = 0, then all channels from + * If CONFIG_STM32_ADCx_INJECTED_CHAN = 0, then all channels from * chanlist are regular channels. * * Input Parameters: @@ -3085,12 +3085,12 @@ struct adc_dev_s *stm32_adc_initialize(int intf, switch (intf) { -#ifdef CONFIG_STM32F7_ADC1 +#ifdef CONFIG_STM32_ADC1 case 1: { ainfo("ADC1 selected\n"); dev = &g_adcdev1; - cj_channels = CONFIG_STM32F7_ADC1_INJECTED_CHAN; + cj_channels = CONFIG_STM32_ADC1_INJECTED_CHAN; cr_channels = channels - cj_channels; # ifdef ADC_HAVE_INJECTED if (cj_channels > 0) @@ -3100,14 +3100,14 @@ struct adc_dev_s *stm32_adc_initialize(int intf, # endif break; } -#endif /* CONFIG_STM32F7_ADC1 */ +#endif /* CONFIG_STM32_ADC1 */ -#ifdef CONFIG_STM32F7_ADC2 +#ifdef CONFIG_STM32_ADC2 case 2: { ainfo("ADC2 selected\n"); dev = &g_adcdev2; - cj_channels = CONFIG_STM32F7_ADC2_INJECTED_CHAN; + cj_channels = CONFIG_STM32_ADC2_INJECTED_CHAN; cr_channels = channels - cj_channels; # ifdef ADC_HAVE_INJECTED if (cj_channels > 0) @@ -3117,14 +3117,14 @@ struct adc_dev_s *stm32_adc_initialize(int intf, # endif break; } -#endif /* CONFIG_STM32F7_ADC2 */ +#endif /* CONFIG_STM32_ADC2 */ -#ifdef CONFIG_STM32F7_ADC3 +#ifdef CONFIG_STM32_ADC3 case 3: { ainfo("ADC3 selected\n"); dev = &g_adcdev3; - cj_channels = CONFIG_STM32F7_ADC3_INJECTED_CHAN; + cj_channels = CONFIG_STM32_ADC3_INJECTED_CHAN; cr_channels = channels - cj_channels; # ifdef ADC_HAVE_INJECTED if (cj_channels > 0) @@ -3135,7 +3135,7 @@ struct adc_dev_s *stm32_adc_initialize(int intf, break; } -#endif /* CONFIG_STM32F7_ADC3 */ +#endif /* CONFIG_STM32_ADC3 */ default: { @@ -3150,10 +3150,10 @@ struct adc_dev_s *stm32_adc_initialize(int intf, /* Configure regular channels */ - DEBUGASSERT(cr_channels <= CONFIG_STM32F7_ADC_MAX_SAMPLES); - if (cr_channels > CONFIG_STM32F7_ADC_MAX_SAMPLES) + DEBUGASSERT(cr_channels <= CONFIG_STM32_ADC_MAX_SAMPLES); + if (cr_channels > CONFIG_STM32_ADC_MAX_SAMPLES) { - cr_channels = CONFIG_STM32F7_ADC_MAX_SAMPLES; + cr_channels = CONFIG_STM32_ADC_MAX_SAMPLES; } priv->cr_channels = cr_channels; @@ -3172,14 +3172,14 @@ struct adc_dev_s *stm32_adc_initialize(int intf, memcpy(priv->j_chanlist, j_chanlist, cj_channels); #endif -#ifdef CONFIG_STM32F7_ADC_CHANGE_SAMPLETIME +#ifdef CONFIG_STM32_ADC_CHANGE_SAMPLETIME /* Assign default values for the sample time table */ memset(priv->sample_rate, ADC_SMPR_DEFAULT, ADC_CHANNELS_NUMBER); priv->adc_channels = ADC_CHANNELS_NUMBER; #endif -#ifdef CONFIG_STM32F7_ADC_LL_OPS +#ifdef CONFIG_STM32_ADC_LL_OPS /* Store reference to the upper-half ADC device */ priv->dev = dev; @@ -3195,4 +3195,4 @@ struct adc_dev_s *stm32_adc_initialize(int intf, return dev; } -#endif /* CONFIG_STM32F7_ADC */ +#endif /* CONFIG_STM32_ADC */ diff --git a/arch/arm/src/stm32f7/stm32_adc.h b/arch/arm/src/stm32f7/stm32_adc.h index b7e65e975886c..58b2aff989260 100644 --- a/arch/arm/src/stm32f7/stm32_adc.h +++ b/arch/arm/src/stm32f7/stm32_adc.h @@ -58,80 +58,80 @@ /* Configuration ************************************************************/ /* Timer devices may be used for different purposes. One special purpose is - * to control periodic ADC sampling. If CONFIG_STM32F7_TIMn is defined then - * CONFIG_STM32F7_TIMn_ADC must also be defined to indicate that timer "n" + * to control periodic ADC sampling. If CONFIG_STM32_TIMn is defined then + * CONFIG_STM32_TIMn_ADC must also be defined to indicate that timer "n" * is intended to be used for that purpose. Timers 1-6 and 8 may be used. */ -#ifndef CONFIG_STM32F7_TIM1 -# undef CONFIG_STM32F7_TIM1_ADC -# undef CONFIG_STM32F7_TIM1_ADC1 -# undef CONFIG_STM32F7_TIM1_ADC2 -# undef CONFIG_STM32F7_TIM1_ADC3 +#ifndef CONFIG_STM32_TIM1 +# undef CONFIG_STM32_TIM1_ADC +# undef CONFIG_STM32_TIM1_ADC1 +# undef CONFIG_STM32_TIM1_ADC2 +# undef CONFIG_STM32_TIM1_ADC3 #endif -#ifndef CONFIG_STM32F7_TIM2 -# undef CONFIG_STM32F7_TIM2_ADC -# undef CONFIG_STM32F7_TIM2_ADC1 -# undef CONFIG_STM32F7_TIM2_ADC2 -# undef CONFIG_STM32F7_TIM2_ADC3 +#ifndef CONFIG_STM32_TIM2 +# undef CONFIG_STM32_TIM2_ADC +# undef CONFIG_STM32_TIM2_ADC1 +# undef CONFIG_STM32_TIM2_ADC2 +# undef CONFIG_STM32_TIM2_ADC3 #endif -#ifndef CONFIG_STM32F7_TIM3 -# undef CONFIG_STM32F7_TIM3_ADC -# undef CONFIG_STM32F7_TIM3_ADC1 -# undef CONFIG_STM32F7_TIM3_ADC2 -# undef CONFIG_STM32F7_TIM3_ADC3 +#ifndef CONFIG_STM32_TIM3 +# undef CONFIG_STM32_TIM3_ADC +# undef CONFIG_STM32_TIM3_ADC1 +# undef CONFIG_STM32_TIM3_ADC2 +# undef CONFIG_STM32_TIM3_ADC3 #endif -#ifndef CONFIG_STM32F7_TIM4 -# undef CONFIG_STM32F7_TIM4_ADC -# undef CONFIG_STM32F7_TIM4_ADC1 -# undef CONFIG_STM32F7_TIM4_ADC2 -# undef CONFIG_STM32F7_TIM4_ADC3 +#ifndef CONFIG_STM32_TIM4 +# undef CONFIG_STM32_TIM4_ADC +# undef CONFIG_STM32_TIM4_ADC1 +# undef CONFIG_STM32_TIM4_ADC2 +# undef CONFIG_STM32_TIM4_ADC3 #endif -#ifndef CONFIG_STM32F7_TIM5 -# undef CONFIG_STM32F7_TIM5_ADC -# undef CONFIG_STM32F7_TIM5_ADC1 -# undef CONFIG_STM32F7_TIM5_ADC2 -# undef CONFIG_STM32F7_TIM5_ADC3 +#ifndef CONFIG_STM32_TIM5 +# undef CONFIG_STM32_TIM5_ADC +# undef CONFIG_STM32_TIM5_ADC1 +# undef CONFIG_STM32_TIM5_ADC2 +# undef CONFIG_STM32_TIM5_ADC3 #endif -#ifndef CONFIG_STM32F7_TIM6 -# undef CONFIG_STM32F7_TIM6_ADC -# undef CONFIG_STM32F7_TIM6_ADC1 -# undef CONFIG_STM32F7_TIM6_ADC2 -# undef CONFIG_STM32F7_TIM6_ADC3 +#ifndef CONFIG_STM32_TIM6 +# undef CONFIG_STM32_TIM6_ADC +# undef CONFIG_STM32_TIM6_ADC1 +# undef CONFIG_STM32_TIM6_ADC2 +# undef CONFIG_STM32_TIM6_ADC3 #endif -#ifndef CONFIG_STM32F7_TIM8 -# undef CONFIG_STM32F7_TIM8_ADC -# undef CONFIG_STM32F7_TIM8_ADC1 -# undef CONFIG_STM32F7_TIM8_ADC2 -# undef CONFIG_STM32F7_TIM8_ADC3 +#ifndef CONFIG_STM32_TIM8 +# undef CONFIG_STM32_TIM8_ADC +# undef CONFIG_STM32_TIM8_ADC1 +# undef CONFIG_STM32_TIM8_ADC2 +# undef CONFIG_STM32_TIM8_ADC3 #endif /* Up to 3 ADC interfaces are supported */ -#if defined(CONFIG_STM32F7_ADC1) || defined(CONFIG_STM32F7_ADC2) || \ - defined(CONFIG_STM32F7_ADC3) +#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) || \ + defined(CONFIG_STM32_ADC3) /* DMA support */ #undef ADC_HAVE_DMA -#if defined(CONFIG_STM32F7_ADC1_DMA) || defined(CONFIG_STM32F7_ADC2_DMA) || \ - defined(CONFIG_STM32F7_ADC3_DMA) +#if defined(CONFIG_STM32_ADC1_DMA) || defined(CONFIG_STM32_ADC2_DMA) || \ + defined(CONFIG_STM32_ADC3_DMA) # define ADC_HAVE_DMA 1 #endif -#ifdef CONFIG_STM32F7_ADC1_DMA +#ifdef CONFIG_STM32_ADC1_DMA # define ADC1_HAVE_DMA 1 #else # undef ADC1_HAVE_DMA #endif -#ifdef CONFIG_STM32F7_ADC2_DMA +#ifdef CONFIG_STM32_ADC2_DMA # define ADC2_HAVE_DMA 1 #else # undef ADC2_HAVE_DMA #endif -#ifdef CONFIG_STM32F7_ADC3_DMA +#ifdef CONFIG_STM32_ADC3_DMA # define ADC3_HAVE_DMA 1 #else # undef ADC3_HAVE_DMA @@ -139,9 +139,9 @@ /* Injected channels support */ -#if (defined(CONFIG_STM32F7_ADC1) && (CONFIG_STM32F7_ADC1_INJECTED_CHAN > 0)) || \ - (defined(CONFIG_STM32F7_ADC2) && (CONFIG_STM32F7_ADC2_INJECTED_CHAN > 0)) || \ - (defined(CONFIG_STM32F7_ADC3) && (CONFIG_STM32F7_ADC3_INJECTED_CHAN > 0)) +#if (defined(CONFIG_STM32_ADC1) && (CONFIG_STM32_ADC1_INJECTED_CHAN > 0)) || \ + (defined(CONFIG_STM32_ADC2) && (CONFIG_STM32_ADC2_INJECTED_CHAN > 0)) || \ + (defined(CONFIG_STM32_ADC3) && (CONFIG_STM32_ADC3_INJECTED_CHAN > 0)) # define ADC_HAVE_INJECTED #endif @@ -149,31 +149,31 @@ * information about the timer. */ -#if defined(CONFIG_STM32F7_TIM1_ADC1) +#if defined(CONFIG_STM32_TIM1_ADC1) # define ADC1_HAVE_TIMER 1 # define ADC1_TIMER_BASE STM32_TIM1_BASE # define ADC1_TIMER_PCLK_FREQUENCY STM32_APB2_TIM1_CLKIN -#elif defined(CONFIG_STM32F7_TIM2_ADC1) +#elif defined(CONFIG_STM32_TIM2_ADC1) # define ADC1_HAVE_TIMER 1 # define ADC1_TIMER_BASE STM32_TIM2_BASE # define ADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM2_CLKIN -#elif defined(CONFIG_STM32F7_TIM3_ADC1) +#elif defined(CONFIG_STM32_TIM3_ADC1) # define ADC1_HAVE_TIMER 1 # define ADC1_TIMER_BASE STM32_TIM3_BASE # define ADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM3_CLKIN -#elif defined(CONFIG_STM32F7_TIM4_ADC1) +#elif defined(CONFIG_STM32_TIM4_ADC1) # define ADC1_HAVE_TIMER 1 # define ADC1_TIMER_BASE STM32_TIM4_BASE # define ADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM4_CLKIN -#elif defined(CONFIG_STM32F7_TIM5_ADC1) +#elif defined(CONFIG_STM32_TIM5_ADC1) # define ADC1_HAVE_TIMER 1 # define ADC1_TIMER_BASE STM32_TIM5_BASE # define ADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM5_CLKIN -#elif defined(CONFIG_STM32F7_TIM6_ADC1) +#elif defined(CONFIG_STM32_TIM6_ADC1) # define ADC1_HAVE_TIMER 1 # define ADC1_TIMER_BASE STM32_TIM6_BASE # define ADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM6_CLKIN -#elif defined(CONFIG_STM32F7_TIM8_ADC1) +#elif defined(CONFIG_STM32_TIM8_ADC1) # define ADC1_HAVE_TIMER 1 # define ADC1_TIMER_BASE STM32_TIM8_BASE # define ADC1_TIMER_PCLK_FREQUENCY STM32_APB2_TIM8_CLKIN @@ -182,40 +182,40 @@ #endif #ifdef ADC1_HAVE_TIMER -# ifndef CONFIG_STM32F7_ADC1_SAMPLE_FREQUENCY -# error "CONFIG_STM32F7_ADC1_SAMPLE_FREQUENCY not defined" +# ifndef CONFIG_STM32_ADC1_SAMPLE_FREQUENCY +# error "CONFIG_STM32_ADC1_SAMPLE_FREQUENCY not defined" # endif -# ifndef CONFIG_STM32F7_ADC1_TIMTRIG -# error "CONFIG_STM32F7_ADC1_TIMTRIG not defined" +# ifndef CONFIG_STM32_ADC1_TIMTRIG +# error "CONFIG_STM32_ADC1_TIMTRIG not defined" # warning "Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO 5:TRGO2" # endif #endif -#if defined(CONFIG_STM32F7_TIM1_ADC2) +#if defined(CONFIG_STM32_TIM1_ADC2) # define ADC2_HAVE_TIMER 1 # define ADC2_TIMER_BASE STM32_TIM1_BASE # define ADC2_TIMER_PCLK_FREQUENCY STM32_APB2_TIM1_CLKIN -#elif defined(CONFIG_STM32F7_TIM2_ADC2) +#elif defined(CONFIG_STM32_TIM2_ADC2) # define ADC2_HAVE_TIMER 1 # define ADC2_TIMER_BASE STM32_TIM2_BASE # define ADC2_TIMER_PCLK_FREQUENCY STM32_APB1_TIM2_CLKIN -#elif defined(CONFIG_STM32F7_TIM3_ADC2) +#elif defined(CONFIG_STM32_TIM3_ADC2) # define ADC2_HAVE_TIMER 1 # define ADC2_TIMER_BASE STM32_TIM3_BASE # define ADC2_TIMER_PCLK_FREQUENCY STM32_APB1_TIM3_CLKIN -#elif defined(CONFIG_STM32F7_TIM4_ADC2) +#elif defined(CONFIG_STM32_TIM4_ADC2) # define ADC2_HAVE_TIMER 1 # define ADC2_TIMER_BASE STM32_TIM4_BASE # define ADC2_TIMER_PCLK_FREQUENCY STM32_APB1_TIM4_CLKIN -#elif defined(CONFIG_STM32F7_TIM5_ADC2) +#elif defined(CONFIG_STM32_TIM5_ADC2) # define ADC2_HAVE_TIMER 1 # define ADC2_TIMER_BASE STM32_TIM5_BASE # define ADC2_TIMER_PCLK_FREQUENCY STM32_APB1_TIM5_CLKIN -#elif defined(CONFIG_STM32F7_TIM6_ADC2) +#elif defined(CONFIG_STM32_TIM6_ADC2) # define ADC2_HAVE_TIMER 1 # define ADC2_TIMER_BASE STM32_TIM6_BASE # define ADC2_TIMER_PCLK_FREQUENCY STM32_APB1_TIM6_CLKIN -#elif defined(CONFIG_STM32F7_TIM8_ADC2) +#elif defined(CONFIG_STM32_TIM8_ADC2) # define ADC2_HAVE_TIMER 1 # define ADC2_TIMER_BASE STM32_TIM8_BASE # define ADC2_TIMER_PCLK_FREQUENCY STM32_APB2_TIM8_CLKIN @@ -224,36 +224,36 @@ #endif #ifdef ADC2_HAVE_TIMER -# ifndef CONFIG_STM32F7_ADC2_SAMPLE_FREQUENCY -# error "CONFIG_STM32F7_ADC2_SAMPLE_FREQUENCY not defined" +# ifndef CONFIG_STM32_ADC2_SAMPLE_FREQUENCY +# error "CONFIG_STM32_ADC2_SAMPLE_FREQUENCY not defined" # endif -# ifndef CONFIG_STM32F7_ADC2_TIMTRIG -# error "CONFIG_STM32F7_ADC2_TIMTRIG not defined" +# ifndef CONFIG_STM32_ADC2_TIMTRIG +# error "CONFIG_STM32_ADC2_TIMTRIG not defined" # warning "Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO 5:TRGO2" # endif #endif -#if defined(CONFIG_STM32F7_TIM1_ADC3) +#if defined(CONFIG_STM32_TIM1_ADC3) # define ADC3_HAVE_TIMER 1 # define ADC3_TIMER_BASE STM32_TIM1_BASE # define ADC3_TIMER_PCLK_FREQUENCY STM32_APB2_TIM1_CLKIN -#elif defined(CONFIG_STM32F7_TIM2_ADC3) +#elif defined(CONFIG_STM32_TIM2_ADC3) # define ADC3_HAVE_TIMER 1 # define ADC3_TIMER_BASE STM32_TIM2_BASE # define ADC3_TIMER_PCLK_FREQUENCY STM32_APB1_TIM2_CLKIN -#elif defined(CONFIG_STM32F7_TIM3_ADC3) +#elif defined(CONFIG_STM32_TIM3_ADC3) # define ADC3_HAVE_TIMER 1 # define ADC3_TIMER_BASE STM32_TIM3_BASE # define ADC3_TIMER_PCLK_FREQUENCY STM32_APB1_TIM3_CLKIN -#elif defined(CONFIG_STM32F7_TIM4_ADC3) +#elif defined(CONFIG_STM32_TIM4_ADC3) # define ADC3_HAVE_TIMER 1 # define ADC3_TIMER_BASE STM32_TIM4_BASE # define ADC3_TIMER_PCLK_FREQUENCY STM32_APB1_TIM4_CLKIN -#elif defined(CONFIG_STM32F7_TIM5_ADC3) +#elif defined(CONFIG_STM32_TIM5_ADC3) # define ADC3_HAVE_TIMER 1 # define ADC3_TIMER_BASE STM32_TIM5_BASE # define ADC3_TIMER_PCLK_FREQUENCY STM32_APB1_TIM5_CLKIN -#elif defined(CONFIG_STM32F7_TIM8_ADC3) +#elif defined(CONFIG_STM32_TIM8_ADC3) # define ADC3_HAVE_TIMER 1 # define ADC3_TIMER_BASE STM32_TIM8_BASE # define ADC3_TIMER_PCLK_FREQUENCY STM32_APB2_TIM8_CLKIN @@ -262,11 +262,11 @@ #endif #ifdef ADC3_HAVE_TIMER -# ifndef CONFIG_STM32F7_ADC3_SAMPLE_FREQUENCY -# error "CONFIG_STM32F7_ADC3_SAMPLE_FREQUENCY not defined" +# ifndef CONFIG_STM32_ADC3_SAMPLE_FREQUENCY +# error "CONFIG_STM32_ADC3_SAMPLE_FREQUENCY not defined" # endif -# ifndef CONFIG_STM32F7_ADC3_TIMTRIG -# error "CONFIG_STM32F7_ADC3_TIMTRIG not defined" +# ifndef CONFIG_STM32_ADC3_TIMTRIG +# error "CONFIG_STM32_ADC3_TIMTRIG not defined" # warning "Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO 5:TRGO2" # endif #endif @@ -408,320 +408,320 @@ /* EXTSEL configuration *****************************************************/ /* NOTE: - * this configuration if used only if CONFIG_STM32F7_TIMx_ADCy is selected. + * this configuration if used only if CONFIG_STM32_TIMx_ADCy is selected. * You can still connect the ADC with a timer trigger using the - * CONFIG_STM32F7_ADCx_EXTSEL option. + * CONFIG_STM32_ADCx_EXTSEL option. */ -#if defined(CONFIG_STM32F7_TIM1_ADC1) -# if CONFIG_STM32F7_ADC1_TIMTRIG == 0 +#if defined(CONFIG_STM32_TIM1_ADC1) +# if CONFIG_STM32_ADC1_TIMTRIG == 0 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T1CC1 -# elif CONFIG_STM32F7_ADC1_TIMTRIG == 1 +# elif CONFIG_STM32_ADC1_TIMTRIG == 1 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T1CC2 -# elif CONFIG_STM32F7_ADC1_TIMTRIG == 2 +# elif CONFIG_STM32_ADC1_TIMTRIG == 2 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T1CC3 -# elif CONFIG_STM32F7_ADC1_TIMTRIG == 3 +# elif CONFIG_STM32_ADC1_TIMTRIG == 3 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T1CC4 -# elif CONFIG_STM32F7_ADC1_TIMTRIG == 4 +# elif CONFIG_STM32_ADC1_TIMTRIG == 4 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T1TRGO -# elif CONFIG_STM32F7_ADC1_TIMTRIG == 5 +# elif CONFIG_STM32_ADC1_TIMTRIG == 5 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T1TRGO2 # else -# error "CONFIG_STM32F7_ADC1_TIMTRIG is out of range" +# error "CONFIG_STM32_ADC1_TIMTRIG is out of range" # endif -#elif defined(CONFIG_STM32F7_TIM2_ADC1) -# if CONFIG_STM32F7_ADC1_TIMTRIG == 0 +#elif defined(CONFIG_STM32_TIM2_ADC1) +# if CONFIG_STM32_ADC1_TIMTRIG == 0 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T2CC1 -# elif CONFIG_STM32F7_ADC1_TIMTRIG == 1 +# elif CONFIG_STM32_ADC1_TIMTRIG == 1 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T2CC2 -# elif CONFIG_STM32F7_ADC1_TIMTRIG == 2 +# elif CONFIG_STM32_ADC1_TIMTRIG == 2 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T2CC3 -# elif CONFIG_STM32F7_ADC1_TIMTRIG == 3 +# elif CONFIG_STM32_ADC1_TIMTRIG == 3 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T2CC4 -# elif CONFIG_STM32F7_ADC1_TIMTRIG == 4 +# elif CONFIG_STM32_ADC1_TIMTRIG == 4 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T2TRGO # else -# error "CONFIG_STM32F7_ADC1_TIMTRIG is out of range" +# error "CONFIG_STM32_ADC1_TIMTRIG is out of range" # endif -#elif defined(CONFIG_STM32F7_TIM3_ADC1) -# if CONFIG_STM32F7_ADC1_TIMTRIG == 0 +#elif defined(CONFIG_STM32_TIM3_ADC1) +# if CONFIG_STM32_ADC1_TIMTRIG == 0 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T3CC1 -# elif CONFIG_STM32F7_ADC1_TIMTRIG == 1 +# elif CONFIG_STM32_ADC1_TIMTRIG == 1 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T3CC2 -# elif CONFIG_STM32F7_ADC1_TIMTRIG == 2 +# elif CONFIG_STM32_ADC1_TIMTRIG == 2 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T3CC3 -# elif CONFIG_STM32F7_ADC1_TIMTRIG == 3 +# elif CONFIG_STM32_ADC1_TIMTRIG == 3 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T3CC4 -# elif CONFIG_STM32F7_ADC1_TIMTRIG == 4 +# elif CONFIG_STM32_ADC1_TIMTRIG == 4 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T3TRGO # else -# error "CONFIG_STM32F7_ADC1_TIMTRIG is out of range" +# error "CONFIG_STM32_ADC1_TIMTRIG is out of range" # endif -#elif defined(CONFIG_STM32F7_TIM4_ADC1) -# if CONFIG_STM32F7_ADC1_TIMTRIG == 0 +#elif defined(CONFIG_STM32_TIM4_ADC1) +# if CONFIG_STM32_ADC1_TIMTRIG == 0 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T4CC1 -# elif CONFIG_STM32F7_ADC1_TIMTRIG == 1 +# elif CONFIG_STM32_ADC1_TIMTRIG == 1 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T4CC2 -# elif CONFIG_STM32F7_ADC1_TIMTRIG == 2 +# elif CONFIG_STM32_ADC1_TIMTRIG == 2 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T4CC3 -# elif CONFIG_STM32F7_ADC1_TIMTRIG == 3 +# elif CONFIG_STM32_ADC1_TIMTRIG == 3 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T4CC4 -# elif CONFIG_STM32F7_ADC1_TIMTRIG == 4 +# elif CONFIG_STM32_ADC1_TIMTRIG == 4 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T4TRGO # else -# error "CONFIG_STM32F7_ADC1_TIMTRIG is out of range" +# error "CONFIG_STM32_ADC1_TIMTRIG is out of range" # endif -#elif defined(CONFIG_STM32F7_TIM5_ADC1) -# if CONFIG_STM32F7_ADC1_TIMTRIG == 0 +#elif defined(CONFIG_STM32_TIM5_ADC1) +# if CONFIG_STM32_ADC1_TIMTRIG == 0 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T5CC1 -# elif CONFIG_STM32F7_ADC1_TIMTRIG == 1 +# elif CONFIG_STM32_ADC1_TIMTRIG == 1 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T5CC2 -# elif CONFIG_STM32F7_ADC1_TIMTRIG == 2 +# elif CONFIG_STM32_ADC1_TIMTRIG == 2 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T5CC3 -# elif CONFIG_STM32F7_ADC1_TIMTRIG == 3 +# elif CONFIG_STM32_ADC1_TIMTRIG == 3 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T5CC4 -# elif CONFIG_STM32F7_ADC1_TIMTRIG == 4 +# elif CONFIG_STM32_ADC1_TIMTRIG == 4 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T5TRGO # else -# error "CONFIG_STM32F7_ADC1_TIMTRIG is out of range" +# error "CONFIG_STM32_ADC1_TIMTRIG is out of range" # endif -#elif defined(CONFIG_STM32F7_TIM6_ADC1) -# if CONFIG_STM32F7_ADC1_TIMTRIG == 0 +#elif defined(CONFIG_STM32_TIM6_ADC1) +# if CONFIG_STM32_ADC1_TIMTRIG == 0 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T6CC1 -# elif CONFIG_STM32F7_ADC1_TIMTRIG == 1 +# elif CONFIG_STM32_ADC1_TIMTRIG == 1 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T6CC2 -# elif CONFIG_STM32F7_ADC1_TIMTRIG == 2 +# elif CONFIG_STM32_ADC1_TIMTRIG == 2 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T6CC3 -# elif CONFIG_STM32F7_ADC1_TIMTRIG == 3 +# elif CONFIG_STM32_ADC1_TIMTRIG == 3 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T6CC4 -# elif CONFIG_STM32F7_ADC1_TIMTRIG == 4 +# elif CONFIG_STM32_ADC1_TIMTRIG == 4 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T6TRGO # else -# error "CONFIG_STM32F7_ADC1_TIMTRIG is out of range" +# error "CONFIG_STM32_ADC1_TIMTRIG is out of range" # endif -#elif defined(CONFIG_STM32F7_TIM8_ADC1) -# if CONFIG_STM32F7_ADC1_TIMTRIG == 0 +#elif defined(CONFIG_STM32_TIM8_ADC1) +# if CONFIG_STM32_ADC1_TIMTRIG == 0 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T8CC1 -# elif CONFIG_STM32F7_ADC1_TIMTRIG == 1 +# elif CONFIG_STM32_ADC1_TIMTRIG == 1 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T8CC2 -# elif CONFIG_STM32F7_ADC1_TIMTRIG == 2 +# elif CONFIG_STM32_ADC1_TIMTRIG == 2 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T8CC3 -# elif CONFIG_STM32F7_ADC1_TIMTRIG == 3 +# elif CONFIG_STM32_ADC1_TIMTRIG == 3 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T8CC4 -# elif CONFIG_STM32F7_ADC1_TIMTRIG == 4 +# elif CONFIG_STM32_ADC1_TIMTRIG == 4 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T8TRGO -# elif CONFIG_STM32F7_ADC1_TIMTRIG == 5 +# elif CONFIG_STM32_ADC1_TIMTRIG == 5 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T8TRGO2 # else -# error "CONFIG_STM32F7_ADC1_TIMTRIG is out of range" +# error "CONFIG_STM32_ADC1_TIMTRIG is out of range" # endif #endif -#if defined(CONFIG_STM32F7_TIM1_ADC2) -# if CONFIG_STM32F7_ADC2_TIMTRIG == 0 +#if defined(CONFIG_STM32_TIM1_ADC2) +# if CONFIG_STM32_ADC2_TIMTRIG == 0 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T1CC1 -# elif CONFIG_STM32F7_ADC2_TIMTRIG == 1 +# elif CONFIG_STM32_ADC2_TIMTRIG == 1 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T1CC2 -# elif CONFIG_STM32F7_ADC2_TIMTRIG == 2 +# elif CONFIG_STM32_ADC2_TIMTRIG == 2 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T1CC3 -# elif CONFIG_STM32F7_ADC2_TIMTRIG == 3 +# elif CONFIG_STM32_ADC2_TIMTRIG == 3 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T1CC4 -# elif CONFIG_STM32F7_ADC2_TIMTRIG == 4 +# elif CONFIG_STM32_ADC2_TIMTRIG == 4 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T1TRGO -# elif CONFIG_STM32F7_ADC2_TIMTRIG == 5 +# elif CONFIG_STM32_ADC2_TIMTRIG == 5 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T1TRGO2 # else -# error "CONFIG_STM32F7_ADC2_TIMTRIG is out of range" +# error "CONFIG_STM32_ADC2_TIMTRIG is out of range" # endif -#elif defined(CONFIG_STM32F7_TIM2_ADC2) -# if CONFIG_STM32F7_ADC2_TIMTRIG == 0 +#elif defined(CONFIG_STM32_TIM2_ADC2) +# if CONFIG_STM32_ADC2_TIMTRIG == 0 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T2CC1 -# elif CONFIG_STM32F7_ADC2_TIMTRIG == 1 +# elif CONFIG_STM32_ADC2_TIMTRIG == 1 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T2CC2 -# elif CONFIG_STM32F7_ADC2_TIMTRIG == 2 +# elif CONFIG_STM32_ADC2_TIMTRIG == 2 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T2CC3 -# elif CONFIG_STM32F7_ADC2_TIMTRIG == 3 +# elif CONFIG_STM32_ADC2_TIMTRIG == 3 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T2CC4 -# elif CONFIG_STM32F7_ADC2_TIMTRIG == 4 +# elif CONFIG_STM32_ADC2_TIMTRIG == 4 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T2TRGO # else -# error "CONFIG_STM32F7_ADC2_TIMTRIG is out of range" +# error "CONFIG_STM32_ADC2_TIMTRIG is out of range" # endif -#elif defined(CONFIG_STM32F7_TIM3_ADC2) -# if CONFIG_STM32F7_ADC2_TIMTRIG == 0 +#elif defined(CONFIG_STM32_TIM3_ADC2) +# if CONFIG_STM32_ADC2_TIMTRIG == 0 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T3CC1 -# elif CONFIG_STM32F7_ADC2_TIMTRIG == 1 +# elif CONFIG_STM32_ADC2_TIMTRIG == 1 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T3CC2 -# elif CONFIG_STM32F7_ADC2_TIMTRIG == 2 +# elif CONFIG_STM32_ADC2_TIMTRIG == 2 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T3CC3 -# elif CONFIG_STM32F7_ADC2_TIMTRIG == 3 +# elif CONFIG_STM32_ADC2_TIMTRIG == 3 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T3CC4 -# elif CONFIG_STM32F7_ADC2_TIMTRIG == 4 +# elif CONFIG_STM32_ADC2_TIMTRIG == 4 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T3TRGO # else -# error "CONFIG_STM32F7_ADC2_TIMTRIG is out of range" +# error "CONFIG_STM32_ADC2_TIMTRIG is out of range" # endif -#elif defined(CONFIG_STM32F7_TIM4_ADC2) -# if CONFIG_STM32F7_ADC2_TIMTRIG == 0 +#elif defined(CONFIG_STM32_TIM4_ADC2) +# if CONFIG_STM32_ADC2_TIMTRIG == 0 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T4CC1 -# elif CONFIG_STM32F7_ADC2_TIMTRIG == 1 +# elif CONFIG_STM32_ADC2_TIMTRIG == 1 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T4CC2 -# elif CONFIG_STM32F7_ADC2_TIMTRIG == 2 +# elif CONFIG_STM32_ADC2_TIMTRIG == 2 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T4CC3 -# elif CONFIG_STM32F7_ADC2_TIMTRIG == 3 +# elif CONFIG_STM32_ADC2_TIMTRIG == 3 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T4CC4 -# elif CONFIG_STM32F7_ADC2_TIMTRIG == 4 +# elif CONFIG_STM32_ADC2_TIMTRIG == 4 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T4TRGO # else -# error "CONFIG_STM32F7_ADC2_TIMTRIG is out of range" +# error "CONFIG_STM32_ADC2_TIMTRIG is out of range" # endif -#elif defined(CONFIG_STM32F7_TIM5_ADC2) -# if CONFIG_STM32F7_ADC2_TIMTRIG == 0 +#elif defined(CONFIG_STM32_TIM5_ADC2) +# if CONFIG_STM32_ADC2_TIMTRIG == 0 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T5CC1 -# elif CONFIG_STM32F7_ADC2_TIMTRIG == 1 +# elif CONFIG_STM32_ADC2_TIMTRIG == 1 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T5CC2 -# elif CONFIG_STM32F7_ADC2_TIMTRIG == 2 +# elif CONFIG_STM32_ADC2_TIMTRIG == 2 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T5CC3 -# elif CONFIG_STM32F7_ADC2_TIMTRIG == 3 +# elif CONFIG_STM32_ADC2_TIMTRIG == 3 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T5CC4 -# elif CONFIG_STM32F7_ADC2_TIMTRIG == 4 +# elif CONFIG_STM32_ADC2_TIMTRIG == 4 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T5TRGO # else -# error "CONFIG_STM32F7_ADC2_TIMTRIG is out of range" +# error "CONFIG_STM32_ADC2_TIMTRIG is out of range" # endif -#elif defined(CONFIG_STM32F7_TIM6_ADC2) -# if CONFIG_STM32F7_ADC2_TIMTRIG == 0 +#elif defined(CONFIG_STM32_TIM6_ADC2) +# if CONFIG_STM32_ADC2_TIMTRIG == 0 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T6CC1 -# elif CONFIG_STM32F7_ADC2_TIMTRIG == 1 +# elif CONFIG_STM32_ADC2_TIMTRIG == 1 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T6CC2 -# elif CONFIG_STM32F7_ADC2_TIMTRIG == 2 +# elif CONFIG_STM32_ADC2_TIMTRIG == 2 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T6CC3 -# elif CONFIG_STM32F7_ADC2_TIMTRIG == 3 +# elif CONFIG_STM32_ADC2_TIMTRIG == 3 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T6CC4 -# elif CONFIG_STM32F7_ADC2_TIMTRIG == 4 +# elif CONFIG_STM32_ADC2_TIMTRIG == 4 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T6TRGO # else -# error "CONFIG_STM32F7_ADC2_TIMTRIG is out of range" +# error "CONFIG_STM32_ADC2_TIMTRIG is out of range" # endif -#elif defined(CONFIG_STM32F7_TIM8_ADC2) -# if CONFIG_STM32F7_ADC2_TIMTRIG == 0 +#elif defined(CONFIG_STM32_TIM8_ADC2) +# if CONFIG_STM32_ADC2_TIMTRIG == 0 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T8CC1 -# elif CONFIG_STM32F7_ADC2_TIMTRIG == 1 +# elif CONFIG_STM32_ADC2_TIMTRIG == 1 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T8CC2 -# elif CONFIG_STM32F7_ADC2_TIMTRIG == 2 +# elif CONFIG_STM32_ADC2_TIMTRIG == 2 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T8CC3 -# elif CONFIG_STM32F7_ADC2_TIMTRIG == 3 +# elif CONFIG_STM32_ADC2_TIMTRIG == 3 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T8CC4 -# elif CONFIG_STM32F7_ADC2_TIMTRIG == 4 +# elif CONFIG_STM32_ADC2_TIMTRIG == 4 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T8TRGO -# elif CONFIG_STM32F7_ADC2_TIMTRIG == 5 +# elif CONFIG_STM32_ADC2_TIMTRIG == 5 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T8TRGO2 # else -# error "CONFIG_STM32F7_ADC2_TIMTRIG is out of range" +# error "CONFIG_STM32_ADC2_TIMTRIG is out of range" # endif #endif -#if defined(CONFIG_STM32F7_TIM1_ADC3) -# if CONFIG_STM32F7_ADC3_TIMTRIG == 0 +#if defined(CONFIG_STM32_TIM1_ADC3) +# if CONFIG_STM32_ADC3_TIMTRIG == 0 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T1CC1 -# elif CONFIG_STM32F7_ADC3_TIMTRIG == 1 +# elif CONFIG_STM32_ADC3_TIMTRIG == 1 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T1CC2 -# elif CONFIG_STM32F7_ADC3_TIMTRIG == 2 +# elif CONFIG_STM32_ADC3_TIMTRIG == 2 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T1CC3 -# elif CONFIG_STM32F7_ADC3_TIMTRIG == 3 +# elif CONFIG_STM32_ADC3_TIMTRIG == 3 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T1CC4 -# elif CONFIG_STM32F7_ADC3_TIMTRIG == 4 +# elif CONFIG_STM32_ADC3_TIMTRIG == 4 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T1TRGO -# elif CONFIG_STM32F7_ADC3_TIMTRIG == 5 +# elif CONFIG_STM32_ADC3_TIMTRIG == 5 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T1TRGO2 # else -# error "CONFIG_STM32F7_ADC3_TIMTRIG is out of range" +# error "CONFIG_STM32_ADC3_TIMTRIG is out of range" # endif -#elif defined(CONFIG_STM32F7_TIM2_ADC3) -# if CONFIG_STM32F7_ADC3_TIMTRIG == 0 +#elif defined(CONFIG_STM32_TIM2_ADC3) +# if CONFIG_STM32_ADC3_TIMTRIG == 0 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T2CC1 -# elif CONFIG_STM32F7_ADC3_TIMTRIG == 1 +# elif CONFIG_STM32_ADC3_TIMTRIG == 1 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T2CC2 -# elif CONFIG_STM32F7_ADC3_TIMTRIG == 2 +# elif CONFIG_STM32_ADC3_TIMTRIG == 2 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T2CC3 -# elif CONFIG_STM32F7_ADC3_TIMTRIG == 3 +# elif CONFIG_STM32_ADC3_TIMTRIG == 3 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T2CC4 -# elif CONFIG_STM32F7_ADC3_TIMTRIG == 4 +# elif CONFIG_STM32_ADC3_TIMTRIG == 4 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T2TRGO # else -# error "CONFIG_STM32F7_ADC3_TIMTRIG is out of range" +# error "CONFIG_STM32_ADC3_TIMTRIG is out of range" # endif -#elif defined(CONFIG_STM32F7_TIM3_ADC3) -# if CONFIG_STM32F7_ADC3_TIMTRIG == 0 +#elif defined(CONFIG_STM32_TIM3_ADC3) +# if CONFIG_STM32_ADC3_TIMTRIG == 0 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T3CC1 -# elif CONFIG_STM32F7_ADC3_TIMTRIG == 1 +# elif CONFIG_STM32_ADC3_TIMTRIG == 1 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T3CC2 -# elif CONFIG_STM32F7_ADC3_TIMTRIG == 2 +# elif CONFIG_STM32_ADC3_TIMTRIG == 2 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T3CC3 -# elif CONFIG_STM32F7_ADC3_TIMTRIG == 3 +# elif CONFIG_STM32_ADC3_TIMTRIG == 3 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T3CC4 -# elif CONFIG_STM32F7_ADC3_TIMTRIG == 4 +# elif CONFIG_STM32_ADC3_TIMTRIG == 4 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T3TRGO # else -# error "CONFIG_STM32F7_ADC3_TIMTRIG is out of range" +# error "CONFIG_STM32_ADC3_TIMTRIG is out of range" # endif -#elif defined(CONFIG_STM32F7_TIM4_ADC3) -# if CONFIG_STM32F7_ADC3_TIMTRIG == 0 +#elif defined(CONFIG_STM32_TIM4_ADC3) +# if CONFIG_STM32_ADC3_TIMTRIG == 0 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T4CC1 -# elif CONFIG_STM32F7_ADC3_TIMTRIG == 1 +# elif CONFIG_STM32_ADC3_TIMTRIG == 1 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T4CC2 -# elif CONFIG_STM32F7_ADC3_TIMTRIG == 2 +# elif CONFIG_STM32_ADC3_TIMTRIG == 2 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T4CC3 -# elif CONFIG_STM32F7_ADC3_TIMTRIG == 3 +# elif CONFIG_STM32_ADC3_TIMTRIG == 3 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T4CC4 -# elif CONFIG_STM32F7_ADC3_TIMTRIG == 4 +# elif CONFIG_STM32_ADC3_TIMTRIG == 4 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T4TRGO # else -# error "CONFIG_STM32F7_ADC3_TIMTRIG is out of range" +# error "CONFIG_STM32_ADC3_TIMTRIG is out of range" # endif -#elif defined(CONFIG_STM32F7_TIM5_ADC3) -# if CONFIG_STM32F7_ADC3_TIMTRIG == 0 +#elif defined(CONFIG_STM32_TIM5_ADC3) +# if CONFIG_STM32_ADC3_TIMTRIG == 0 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T5CC1 -# elif CONFIG_STM32F7_ADC3_TIMTRIG == 1 +# elif CONFIG_STM32_ADC3_TIMTRIG == 1 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T5CC2 -# elif CONFIG_STM32F7_ADC3_TIMTRIG == 2 +# elif CONFIG_STM32_ADC3_TIMTRIG == 2 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T5CC3 -# elif CONFIG_STM32F7_ADC3_TIMTRIG == 3 +# elif CONFIG_STM32_ADC3_TIMTRIG == 3 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T5CC4 -# elif CONFIG_STM32F7_ADC3_TIMTRIG == 4 +# elif CONFIG_STM32_ADC3_TIMTRIG == 4 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T5TRGO # else -# error "CONFIG_STM32F7_ADC3_TIMTRIG is out of range" +# error "CONFIG_STM32_ADC3_TIMTRIG is out of range" # endif -#elif defined(CONFIG_STM32F7_TIM6_ADC3) -# if CONFIG_STM32F7_ADC3_TIMTRIG == 0 +#elif defined(CONFIG_STM32_TIM6_ADC3) +# if CONFIG_STM32_ADC3_TIMTRIG == 0 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T6CC1 -# elif CONFIG_STM32F7_ADC3_TIMTRIG == 1 +# elif CONFIG_STM32_ADC3_TIMTRIG == 1 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T6CC2 -# elif CONFIG_STM32F7_ADC3_TIMTRIG == 2 +# elif CONFIG_STM32_ADC3_TIMTRIG == 2 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T6CC3 -# elif CONFIG_STM32F7_ADC3_TIMTRIG == 3 +# elif CONFIG_STM32_ADC3_TIMTRIG == 3 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T6CC4 -# elif CONFIG_STM32F7_ADC3_TIMTRIG == 4 +# elif CONFIG_STM32_ADC3_TIMTRIG == 4 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T6TRGO # else -# error "CONFIG_STM32F7_ADC3_TIMTRIG is out of range" +# error "CONFIG_STM32_ADC3_TIMTRIG is out of range" # endif -#elif defined(CONFIG_STM32F7_TIM8_ADC3) -# if CONFIG_STM32F7_ADC3_TIMTRIG == 0 +#elif defined(CONFIG_STM32_TIM8_ADC3) +# if CONFIG_STM32_ADC3_TIMTRIG == 0 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T8CC1 -# elif CONFIG_STM32F7_ADC3_TIMTRIG == 1 +# elif CONFIG_STM32_ADC3_TIMTRIG == 1 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T8CC2 -# elif CONFIG_STM32F7_ADC3_TIMTRIG == 2 +# elif CONFIG_STM32_ADC3_TIMTRIG == 2 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T8CC3 -# elif CONFIG_STM32F7_ADC3_TIMTRIG == 3 +# elif CONFIG_STM32_ADC3_TIMTRIG == 3 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T8CC4 -# elif CONFIG_STM32F7_ADC3_TIMTRIG == 4 +# elif CONFIG_STM32_ADC3_TIMTRIG == 4 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T8TRGO -# elif CONFIG_STM32F7_ADC3_TIMTRIG == 5 +# elif CONFIG_STM32_ADC3_TIMTRIG == 5 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T8TRGO2 # else -# error "CONFIG_STM32F7_ADC3_TIMTRIG is out of range" +# error "CONFIG_STM32_ADC3_TIMTRIG is out of range" # endif #endif @@ -730,7 +730,7 @@ #ifdef ADC1_EXTSEL_VALUE # define ADC1_HAVE_EXTCFG 1 # define ADC1_EXTCFG_VALUE (ADC1_EXTSEL_VALUE | ADC_EXTREG_EXTEN_DEFAULT) -#elif defined(CONFIG_STM32F7_ADC1_EXTSEL) +#elif defined(CONFIG_STM32_ADC1_EXTSEL) # define ADC1_HAVE_EXTCFG 1 # define ADC1_EXTCFG_VALUE 0 #else @@ -739,7 +739,7 @@ #ifdef ADC2_EXTSEL_VALUE # define ADC2_HAVE_EXTCFG 1 # define ADC2_EXTCFG_VALUE (ADC2_EXTSEL_VALUE | ADC_EXTREG_EXTEN_DEFAULT) -#elif defined(CONFIG_STM32F7_ADC2_EXTSEL) +#elif defined(CONFIG_STM32_ADC2_EXTSEL) # define ADC2_HAVE_EXTCFG 1 # define ADC2_EXTCFG_VALUE 0 #else @@ -748,7 +748,7 @@ #ifdef ADC3_EXTSEL_VALUE # define ADC3_HAVE_EXTCFG 1 # define ADC3_EXTCFG_VALUE (ADC3_EXTSEL_VALUE | ADC_EXTREG_EXTEN_DEFAULT) -#elif defined(CONFIG_STM32F7_ADC3_EXTSEL) +#elif defined(CONFIG_STM32_ADC3_EXTSEL) # define ADC3_HAVE_EXTCFG 1 # define ADC3_EXTCFG_VALUE 0 #else @@ -771,7 +771,7 @@ #ifdef ADC1_JEXTSEL_VALUE # define ADC1_HAVE_JEXTCFG 1 # define ADC1_JEXTCFG_VALUE (ADC1_JEXTSEL_VALUE | ADC_JEXTREG_JEXTEN_DEFAULT) -#elif defined(CONFIG_STM32F7_ADC1_JEXTSEL) +#elif defined(CONFIG_STM32_ADC1_JEXTSEL) # define ADC1_HAVE_JEXTCFG 1 # define ADC1_JEXTCFG_VALUE 0 #else @@ -780,7 +780,7 @@ #ifdef ADC2_JEXTSEL_VALUE # define ADC2_HAVE_JEXTCFG 1 # define ADC2_JEXTCFG_VALUE (ADC2_JEXTSEL_VALUE | ADC_JEXTREG_JEXTEN_DEFAULT) -#elif defined(CONFIG_STM32F7_ADC2_JEXTSEL) +#elif defined(CONFIG_STM32_ADC2_JEXTSEL) # define ADC2_HAVE_JEXTCFG 1 # define ADC2_JEXTCFG_VALUE 0 #else @@ -789,7 +789,7 @@ #ifdef ADC3_JEXTSEL_VALUE # define ADC3_HAVE_JEXTCFG 1 # define ADC3_JEXTCFG_VALUE (ADC3_JEXTSEL_VALUE | ADC_JEXTREG_JEXTEN_DEFAULT) -#elif defined(CONFIG_STM32F7_ADC3_JEXTSEL) +#elif defined(CONFIG_STM32_ADC3_JEXTSEL) # define ADC3_HAVE_JEXTCFG 1 # define ADC3_JEXTCFG_VALUE 0 #else @@ -914,9 +914,9 @@ enum stm32_adc_multimode_e ADC_MULTIMODE_ATM3 = 14, /* Triple alternate trigger mode only */ }; -#ifdef CONFIG_STM32F7_ADC_LL_OPS +#ifdef CONFIG_STM32_ADC_LL_OPS -#ifdef CONFIG_STM32F7_ADC_CHANGE_SAMPLETIME +#ifdef CONFIG_STM32_ADC_CHANGE_SAMPLETIME /* Channel and sample time pair */ @@ -941,7 +941,7 @@ struct adc_sample_time_s * same value of the sample time */ uint8_t all_ch_sample_time:3; /* Sample time for all channels */ }; -#endif /* CONFIG_STM32F7_ADC_CHANGE_SAMPLETIME */ +#endif /* CONFIG_STM32_ADC_CHANGE_SAMPLETIME */ /* This structure provides the publicly visible representation of the * "lower-half" ADC driver structure. @@ -1024,7 +1024,7 @@ struct stm32_adc_ops_s void (*inj_startconv)(struct stm32_adc_dev_s *dev, bool state); #endif -#ifdef CONFIG_STM32F7_ADC_CHANGE_SAMPLETIME +#ifdef CONFIG_STM32_ADC_CHANGE_SAMPLETIME /* Set ADC sample time */ void (*stime_set)(struct stm32_adc_dev_s *dev, @@ -1046,7 +1046,7 @@ struct stm32_adc_ops_s void (*enable)(struct stm32_adc_dev_s *dev, bool enable); }; -#endif /* CONFIG_STM32F7_ADC_LL_OPS */ +#endif /* CONFIG_STM32_ADC_LL_OPS */ /**************************************************************************** * Public Function Prototypes @@ -1088,7 +1088,7 @@ struct adc_dev_s *stm32_adc_initialize(int intf, #endif #endif /* __ASSEMBLY__ */ -#endif /* CONFIG_STM32F7_ADC1 || CONFIG_STM32F7_ADC2 || - * CONFIG_STM32F7_ADC3 +#endif /* CONFIG_STM32_ADC1 || CONFIG_STM32_ADC2 || + * CONFIG_STM32_ADC3 */ #endif /* __ARCH_ARM_SRC_STM32F7_STM32_ADC_H */ diff --git a/arch/arm/src/stm32f7/stm32_allocateheap.c b/arch/arm/src/stm32f7/stm32_allocateheap.c index 0991bcece13cb..8c0a72c9ce1eb 100644 --- a/arch/arm/src/stm32f7/stm32_allocateheap.c +++ b/arch/arm/src/stm32f7/stm32_allocateheap.c @@ -62,8 +62,8 @@ * the FMC. In order to use FMC RAM, the following additional things need * to be present in the NuttX configuration file: * - * CONFIG_STM32F7_FMC=y : Enables the FMC - * CONFIG_STM32F7_FMC_S[D]RAM=y : SRAM and/or SDRAM is available via the FMC. + * CONFIG_STM32_FMC=y : Enables the FMC + * CONFIG_STM32_FMC_S[D]RAM=y : SRAM and/or SDRAM is available via the FMC. * Either of these autoselects * CONFIG_ARCH_HAVE_HEAP2 * which is what we are interested in here. @@ -79,10 +79,10 @@ /* Set the start and end of SRAM1 and SRAM2 */ #define SRAM1_START STM32_SRAM1_BASE -#define SRAM1_END (SRAM1_START + STM32F7_SRAM1_SIZE) +#define SRAM1_END (SRAM1_START + STM32_SRAM1_SIZE) #define SRAM2_START STM32_SRAM2_BASE -#define SRAM2_END (SRAM2_START + STM32F7_SRAM2_SIZE) +#define SRAM2_END (SRAM2_START + STM32_SRAM2_SIZE) /* The STM32 F7 has DTCM memory */ @@ -94,15 +94,15 @@ /* DTCM to be excluded from the main heap. */ -#ifdef CONFIG_STM32F7_DTCMEXCLUDE +#ifdef CONFIG_STM32_DTCMEXCLUDE # undef HAVE_DTCM #endif /* We can't possibly have FMC external RAM if the FMC is not enabled */ -#ifndef CONFIG_STM32F7_FMC +#ifndef CONFIG_STM32_FMC # ifdef CONFIG_ARCH_HAVE_HEAP2 -# error CONFIG_ARCH_HAVE_HEAP2 but not CONFIG_STM32F7_FMC! Kconfig flawed? +# error CONFIG_ARCH_HAVE_HEAP2 but not CONFIG_STM32_FMC! Kconfig flawed? # endif # undef CONFIG_ARCH_HAVE_HEAP2 #endif diff --git a/arch/arm/src/stm32f7/stm32_bbsram.c b/arch/arm/src/stm32f7/stm32_bbsram.c index 36d92cc7de361..65a5b0e510fdb 100644 --- a/arch/arm/src/stm32f7/stm32_bbsram.c +++ b/arch/arm/src/stm32f7/stm32_bbsram.c @@ -51,14 +51,14 @@ #include "stm32_pwr.h" #include "stm32_rtc.h" -#ifdef CONFIG_STM32F7_BBSRAM +#ifdef CONFIG_STM32_BBSRAM /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ -#if !defined(CONFIG_STM32F7_BKPSRAM) -#error Driver Requires CONFIG_STM32F7_BKPSRAM to be enabled +#if !defined(CONFIG_STM32_BKPSRAM) +#error Driver Requires CONFIG_STM32_BKPSRAM to be enabled #endif #define MAX_OPENCNT (255) /* Limit of uint8_t */ @@ -130,7 +130,7 @@ static int stm32_bbsram_unlink(struct inode *inode); ****************************************************************************/ #if defined(CONFIG_BBSRAM_DEBUG) -static uint8_t debug[STM32F7_BBSRAM_SIZE]; +static uint8_t debug[STM32_BBSRAM_SIZE]; #endif static const struct file_operations g_stm32_bbsram_fops = @@ -147,7 +147,7 @@ static const struct file_operations g_stm32_bbsram_fops = #endif }; -static struct stm32_bbsram_s g_bbsram[CONFIG_STM32F7_BBSRAM_FILES]; +static struct stm32_bbsram_s g_bbsram[CONFIG_STM32_BBSRAM_FILES]; /**************************************************************************** * Private Functions @@ -544,7 +544,7 @@ static int stm32_bbsram_ioctl(struct file *filep, int cmd, DEBUGASSERT(inode->i_private); bbr = inode->i_private; - if (cmd == STM32F7_BBSRAM_GETDESC_IOCTL) + if (cmd == STM32_BBSRAM_GETDESC_IOCTL) { struct bbsramd_s *bbrr = (struct bbsramd_s *)((uintptr_t)arg); @@ -627,13 +627,13 @@ static int stm32_bbsram_unlink(struct inode *inode) static int stm32_bbsram_probe(int *ent, struct stm32_bbsram_s pdev[]) { int i; - int avail = STM32F7_BBSRAM_SIZE; + int avail = STM32_BBSRAM_SIZE; int alloc; int size; int ret = -EFBIG; struct bbsramfh_s *pf = (struct bbsramfh_s *) STM32_BKPSRAM_BASE; - for (i = 0; (i < CONFIG_STM32F7_BBSRAM_FILES) && ent[i] && (avail > 0); + for (i = 0; (i < CONFIG_STM32_BBSRAM_FILES) && ent[i] && (avail > 0); i++) { /* Validate the actual allocations against what is in the BBSRAM */ @@ -784,7 +784,7 @@ int stm32_bbsraminitialize(char *devpath, int *sizes) * ****************************************************************************/ -#if defined(CONFIG_STM32F7_SAVE_CRASHDUMP) +#if defined(CONFIG_STM32_SAVE_CRASHDUMP) int stm32_bbsram_savepanic(int fileno, uint8_t *context, int length) { struct bbsramfh_s *bbf; @@ -802,7 +802,7 @@ int stm32_bbsram_savepanic(int fileno, uint8_t *context, int length) { once = true; - DEBUGASSERT(fileno > 0 && fileno < CONFIG_STM32F7_BBSRAM_FILES); + DEBUGASSERT(fileno > 0 && fileno < CONFIG_STM32_BBSRAM_FILES); bbf = g_bbsram[fileno].bbf; diff --git a/arch/arm/src/stm32f7/stm32_bbsram.h b/arch/arm/src/stm32f7/stm32_bbsram.h index 4d080578c4eeb..a660e0e02b97f 100644 --- a/arch/arm/src/stm32f7/stm32_bbsram.h +++ b/arch/arm/src/stm32f7/stm32_bbsram.h @@ -25,7 +25,7 @@ /**************************************************************************** * The purpose of this driver is to add battery backup file to the file - * system. There can be CONFIG_STM32F7_BBRSRAM_COUNT files defined. + * system. There can be CONFIG_STM32_BBRSRAM_COUNT files defined. * These files are of fixed size up to the maximum of the backing 4K SRAM. * * If CONFIG_SAVE_CRASHDUMP is defined The driver also supports a feature @@ -44,22 +44,22 @@ * Pre-processor Definitions ****************************************************************************/ -#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) || \ - defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) -# define STM32F7_BBSRAM_SIZE 4096 +#if defined(CONFIG_STM32_STM32F74XX) || defined(CONFIG_STM32_STM32F75XX) || \ + defined(CONFIG_STM32_STM32F76XX) || defined(CONFIG_STM32_STM32F77XX) +# define STM32_BBSRAM_SIZE 4096 #else # error "No backup SRAM on this STM32 Device" #endif -#if !defined(CONFIG_STM32F7_BBSRAM_FILES) -# define CONFIG_STM32F7_BBSRAM_FILES 4 +#if !defined(CONFIG_STM32_BBSRAM_FILES) +# define CONFIG_STM32_BBSRAM_FILES 4 #endif -/* REVISIT: What guarantees that STM32F7_BBSRAM_GETDESC_IOCTL has a unique +/* REVISIT: What guarantees that STM32_BBSRAM_GETDESC_IOCTL has a unique * value among all over _DIOC() values? */ -#define STM32F7_BBSRAM_GETDESC_IOCTL _DIOC(0x0010) /* Returns a bbsramd_s */ +#define STM32_BBSRAM_GETDESC_IOCTL _DIOC(0x0010) /* Returns a bbsramd_s */ /**************************************************************************** * Public Types @@ -110,8 +110,8 @@ extern "C" * the last entry should be 0 * A size of -1 will use all the remaining spaces * - * If the length of sizes is greater then CONFIG_STM32F7_BBSRAM_FILES - * CONFIG_STM32F7_BBSRAM_FILES will be returned. + * If the length of sizes is greater then CONFIG_STM32_BBSRAM_FILES + * CONFIG_STM32_BBSRAM_FILES will be returned. * * Returned Value: * Number of files created on success; Negated errno on failure. @@ -129,7 +129,7 @@ int stm32_bbsraminitialize(char *devpath, int *sizes); * Saves the panic context in a previously allocated BBSRAM file * * Parameters: - * fileno - the value returned by the ioctl STM32F7_BBSRAM_GETDESC_IOCTL + * fileno - the value returned by the ioctl STM32_BBSRAM_GETDESC_IOCTL * context - Pointer to a any array of bytes to save * length - The length of the data pointed to byt context * @@ -140,7 +140,7 @@ int stm32_bbsraminitialize(char *devpath, int *sizes); * ****************************************************************************/ -#if defined(CONFIG_STM32F7_SAVE_CRASHDUMP) +#if defined(CONFIG_STM32_SAVE_CRASHDUMP) int stm32_bbsram_savepanic(int fileno, uint8_t *context, int length); #endif diff --git a/arch/arm/src/stm32f7/stm32_can.c b/arch/arm/src/stm32f7/stm32_can.c index b51547ebe3544..2d571c61b8dc3 100644 --- a/arch/arm/src/stm32f7/stm32_can.c +++ b/arch/arm/src/stm32f7/stm32_can.c @@ -48,8 +48,8 @@ #include "stm32_gpio.h" #if defined(CONFIG_CAN) && \ - (defined(CONFIG_STM32F7_CAN1) || defined(CONFIG_STM32F7_CAN2) || \ - defined(CONFIG_STM32F7_CAN3)) + (defined(CONFIG_STM32_CAN1) || defined(CONFIG_STM32_CAN2) || \ + defined(CONFIG_STM32_CAN3)) /**************************************************************************** * Pre-processor Definitions @@ -63,7 +63,7 @@ /* Bit timing ***************************************************************/ -#define CAN_BIT_QUANTA (CONFIG_STM32F7_CAN_TSEG1 + CONFIG_STM32F7_CAN_TSEG2 + 1) +#define CAN_BIT_QUANTA (CONFIG_STM32_CAN_TSEG1 + CONFIG_STM32_CAN_TSEG2 + 1) #ifndef CONFIG_DEBUG_CAN_INFO # undef CONFIG_STM32_CAN_REGDEBUG @@ -179,7 +179,7 @@ static const struct can_ops_s g_canops = .co_txempty = stm32can_txempty, }; -#ifdef CONFIG_STM32F7_CAN1 +#ifdef CONFIG_STM32_CAN1 static struct stm32_can_s g_can1priv = { .port = 1, @@ -192,7 +192,7 @@ static struct stm32_can_s g_can1priv = .filter = 0, .base = STM32_CAN1_BASE, .fbase = STM32_CAN1_BASE, - .baud = CONFIG_STM32F7_CAN1_BAUD, + .baud = CONFIG_STM32_CAN1_BAUD, }; static struct can_dev_s g_can1dev = @@ -202,7 +202,7 @@ static struct can_dev_s g_can1dev = }; #endif -#ifdef CONFIG_STM32F7_CAN2 +#ifdef CONFIG_STM32_CAN2 static struct stm32_can_s g_can2priv = { .port = 2, @@ -215,7 +215,7 @@ static struct stm32_can_s g_can2priv = .filter = CAN_NFILTERS / 2, .base = STM32_CAN2_BASE, .fbase = STM32_CAN1_BASE, - .baud = CONFIG_STM32F7_CAN2_BAUD, + .baud = CONFIG_STM32_CAN2_BAUD, }; static struct can_dev_s g_can2dev = @@ -225,7 +225,7 @@ static struct can_dev_s g_can2dev = }; #endif -#ifdef CONFIG_STM32F7_CAN3 +#ifdef CONFIG_STM32_CAN3 static struct stm32_can_s g_can3priv = { .port = 3, @@ -238,7 +238,7 @@ static struct stm32_can_s g_can3priv = .filter = 0, .base = STM32_CAN3_BASE, .fbase = STM32_CAN3_BASE, - .baud = CONFIG_STM32F7_CAN3_BAUD, + .baud = CONFIG_STM32_CAN3_BAUD, }; static struct can_dev_s g_can3dev = @@ -582,21 +582,21 @@ static void stm32can_reset(struct can_dev_s *dev) /* Get the bits in the AHB1RSTR register needed to reset this CAN device */ -#ifdef CONFIG_STM32F7_CAN1 +#ifdef CONFIG_STM32_CAN1 if (priv->port == 1) { regbit = RCC_APB1RSTR_CAN1RST; } else #endif -#ifdef CONFIG_STM32F7_CAN2 +#ifdef CONFIG_STM32_CAN2 if (priv->port == 2) { regbit = RCC_APB1RSTR_CAN2RST; } else #endif -#ifdef CONFIG_STM32F7_CAN3 +#ifdef CONFIG_STM32_CAN3 if (priv->port == 3) { regbit = RCC_APB1RSTR_CAN3RST; @@ -1789,8 +1789,8 @@ static int stm32can_bittiming(struct stm32_can_s *priv) else { - ts1 = CONFIG_STM32F7_CAN_TSEG1; - ts2 = CONFIG_STM32F7_CAN_TSEG2; + ts1 = CONFIG_STM32_CAN_TSEG1; + ts2 = CONFIG_STM32_CAN_TSEG2; brp = (tmp + (CAN_BIT_QUANTA / 2)) / CAN_BIT_QUANTA; DEBUGASSERT(brp >= 1 && brp <= CAN_BTR_BRP_MAX); } @@ -2038,7 +2038,7 @@ static int stm32can_filterinit(struct stm32_can_s *priv) regval |= CAN_FMR_FINIT; stm32can_putfreg(priv, STM32_CAN_FMR_OFFSET, regval); -#if defined(CONFIG_STM32F7_CAN1) || defined(CONFIG_STM32F7_CAN2) +#if defined(CONFIG_STM32_CAN1) || defined(CONFIG_STM32_CAN2) if (priv->port == 1 || priv->port == 2) { /* Assign half the filters to CAN1, half to CAN2 */ @@ -2270,7 +2270,7 @@ struct can_dev_s *stm32_caninitialize(int port) * by stm32_clockconfig() early in the reset sequence. */ -#ifdef CONFIG_STM32F7_CAN1 +#ifdef CONFIG_STM32_CAN1 if (port == 1) { /* Select the CAN1 device structure */ @@ -2286,7 +2286,7 @@ struct can_dev_s *stm32_caninitialize(int port) } else #endif -#ifdef CONFIG_STM32F7_CAN2 +#ifdef CONFIG_STM32_CAN2 if (port == 2) { /* Select the CAN2 device structure */ @@ -2302,7 +2302,7 @@ struct can_dev_s *stm32_caninitialize(int port) } else #endif -#ifdef CONFIG_STM32F7_CAN3 +#ifdef CONFIG_STM32_CAN3 if (port == 3) { /* Select the CAN3 device structure */ diff --git a/arch/arm/src/stm32f7/stm32_can.h b/arch/arm/src/stm32f7/stm32_can.h index 05dbe1e10c650..cf080ba400d33 100644 --- a/arch/arm/src/stm32f7/stm32_can.h +++ b/arch/arm/src/stm32f7/stm32_can.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_STM32F7_CAN_H -#define __ARCH_ARM_SRC_STM32_STM32F7_CAN_H +#ifndef __ARCH_ARM_SRC_STM32F7_STM32_CAN_H +#define __ARCH_ARM_SRC_STM32F7_STM32_CAN_H /**************************************************************************** * Included Files @@ -40,45 +40,45 @@ /* Configuration ************************************************************/ -#if defined(CONFIG_CAN) && (defined(CONFIG_STM32F7_CAN1) || \ - defined(CONFIG_STM32F7_CAN2) || defined(CONFIG_STM32F7_CAN3)) +#if defined(CONFIG_CAN) && (defined(CONFIG_STM32_CAN1) || \ + defined(CONFIG_STM32_CAN2) || defined(CONFIG_STM32_CAN3)) /* CAN BAUD */ -#if defined(CONFIG_STM32F7_CAN1) && !defined(CONFIG_STM32F7_CAN1_BAUD) -# error "CONFIG_STM32F7_CAN1_BAUD is not defined" +#if defined(CONFIG_STM32_CAN1) && !defined(CONFIG_STM32_CAN1_BAUD) +# error "CONFIG_STM32_CAN1_BAUD is not defined" #endif -#if defined(CONFIG_STM32F7_CAN2) && !defined(CONFIG_STM32F7_CAN2_BAUD) -# error "CONFIG_STM32F7_CAN2_BAUD is not defined" +#if defined(CONFIG_STM32_CAN2) && !defined(CONFIG_STM32_CAN2_BAUD) +# error "CONFIG_STM32_CAN2_BAUD is not defined" #endif -#if defined(CONFIG_STM32F7_CAN3) && !defined(CONFIG_STM32F7_CAN3_BAUD) -# error "CONFIG_STM32F7_CAN3_BAUD is not defined" +#if defined(CONFIG_STM32_CAN3) && !defined(CONFIG_STM32_CAN3_BAUD) +# error "CONFIG_STM32_CAN3_BAUD is not defined" #endif /* User-defined TSEG1 and TSEG2 settings may be used. * - * CONFIG_STM32F7_CAN_TSEG1 = the number of CAN time quanta in segment 1 - * CONFIG_STM32F7_CAN_TSEG2 = the number of CAN time quanta in segment 2 + * CONFIG_STM32_CAN_TSEG1 = the number of CAN time quanta in segment 1 + * CONFIG_STM32_CAN_TSEG2 = the number of CAN time quanta in segment 2 * CAN_BIT_QUANTA = The number of CAN time quanta in on bit time */ -#ifndef CONFIG_STM32F7_CAN_TSEG1 -# define CONFIG_STM32F7_CAN_TSEG1 6 +#ifndef CONFIG_STM32_CAN_TSEG1 +# define CONFIG_STM32_CAN_TSEG1 6 #endif -#if CONFIG_STM32F7_CAN_TSEG1 < 1 || \ - CONFIG_STM32F7_CAN_TSEG1 > CAN_BTR_TSEG1_MAX +#if CONFIG_STM32_CAN_TSEG1 < 1 || \ + CONFIG_STM32_CAN_TSEG1 > CAN_BTR_TSEG1_MAX # error "CONFIG_STM32_CAN_TSEG1 is out of range" #endif -#ifndef CONFIG_STM32F7_CAN_TSEG2 -# define CONFIG_STM32F7_CAN_TSEG2 7 +#ifndef CONFIG_STM32_CAN_TSEG2 +# define CONFIG_STM32_CAN_TSEG2 7 #endif -#if CONFIG_STM32F7_CAN_TSEG2 < 1 || \ - CONFIG_STM32F7_CAN_TSEG2 > CAN_BTR_TSEG2_MAX +#if CONFIG_STM32_CAN_TSEG2 < 1 || \ + CONFIG_STM32_CAN_TSEG2 > CAN_BTR_TSEG2_MAX # error "CONFIG_STM32_CAN_TSEG2 is out of range" #endif @@ -105,7 +105,7 @@ extern "C" * Public Function Prototypes ****************************************************************************/ -#ifdef CONFIG_STM32F7_CAN_CHARDRIVER +#ifdef CONFIG_STM32_CAN_CHARDRIVER /**************************************************************************** * Name: stm32_caninitialize @@ -125,7 +125,7 @@ struct can_dev_s; struct can_dev_s *stm32_caninitialize(int port); #endif -#ifdef CONFIG_STM32F7_CAN_SOCKET +#ifdef CONFIG_STM32_CAN_SOCKET /**************************************************************************** * Name: stm32_cansockinitialize @@ -151,4 +151,4 @@ int stm32_cansockinitialize(int port); #endif /* __ASSEMBLY__ */ #endif /* CONFIG_CAN && (CONFIG_STM32_CAN1 || CONFIG_STM32_CAN2) */ -#endif /* __ARCH_ARM_SRC_STM32_STM32_CAN_H */ +#endif /* __ARCH_ARM_SRC_STM32F7_STM32_CAN_H */ diff --git a/arch/arm/src/stm32f7/stm32_can_sock.c b/arch/arm/src/stm32f7/stm32_can_sock.c index c421e4c0e5e1f..327dc5c59a78a 100644 --- a/arch/arm/src/stm32f7/stm32_can_sock.c +++ b/arch/arm/src/stm32f7/stm32_can_sock.c @@ -49,7 +49,7 @@ #include "stm32_rcc.h" #include "stm32_can.h" -/* Ported form arch/arm/src/stm32/stm32_can_sock.c */ +/* Ported form arch/arm/src/common/stm32/stm32_can_m3m4_v1_sock.c */ /**************************************************************************** * Pre-processor Definitions @@ -63,10 +63,10 @@ /* Bit timing ***************************************************************/ -#define CAN_BIT_QUANTA (CONFIG_STM32F7_CAN_TSEG1 + CONFIG_STM32F7_CAN_TSEG2 + 1) +#define CAN_BIT_QUANTA (CONFIG_STM32_CAN_TSEG1 + CONFIG_STM32_CAN_TSEG2 + 1) #ifndef CONFIG_DEBUG_CAN_INFO -# undef CONFIG_STM32F7_CAN_REGDEBUG +# undef CONFIG_STM32_CAN_REGDEBUG #endif /* Pool configuration *******************************************************/ @@ -146,7 +146,7 @@ static void stm32can_putreg(struct stm32_can_s *priv, int offset, uint32_t value); static void stm32can_putfreg(struct stm32_can_s *priv, int offset, uint32_t value); -#ifdef CONFIG_STM32F7_CAN_REGDEBUG +#ifdef CONFIG_STM32_CAN_REGDEBUG static void stm32can_dumpctrlregs(struct stm32_can_s *priv, const char *msg); static void stm32can_dumpmbregs(struct stm32_can_s *priv, @@ -233,7 +233,7 @@ static int stm32can_netdev_ioctl(struct net_driver_s *dev, int cmd, * Private Data ****************************************************************************/ -#ifdef CONFIG_STM32F7_CAN1 +#ifdef CONFIG_STM32_CAN1 static struct stm32_can_s g_can1priv = { @@ -250,12 +250,12 @@ static struct stm32_can_s g_can1priv = .filter = 0, .base = STM32_CAN1_BASE, .fbase = STM32_CAN1_BASE, - .baud = CONFIG_STM32F7_CAN1_BAUD, + .baud = CONFIG_STM32_CAN1_BAUD, }; #endif -#ifdef CONFIG_STM32F7_CAN2 +#ifdef CONFIG_STM32_CAN2 static struct stm32_can_s g_can2priv = { @@ -272,12 +272,12 @@ static struct stm32_can_s g_can2priv = .filter = CAN_NFILTERS / 2, .base = STM32_CAN2_BASE, .fbase = STM32_CAN1_BASE, - .baud = CONFIG_STM32F7_CAN2_BAUD, + .baud = CONFIG_STM32_CAN2_BAUD, }; #endif -#ifdef CONFIG_STM32F7_CAN3 +#ifdef CONFIG_STM32_CAN3 static struct stm32_can_s g_can3priv = { @@ -294,7 +294,7 @@ static struct stm32_can_s g_can3priv = .filter = CAN_NFILTERS / 2, .base = STM32_CAN3_BASE, .fbase = STM32_CAN3_BASE, - .baud = CONFIG_STM32F7_CAN3_BAUD, + .baud = CONFIG_STM32_CAN3_BAUD, }; #endif @@ -312,7 +312,7 @@ static struct stm32_can_s g_can3priv = * ****************************************************************************/ -#ifdef CONFIG_STM32F7_CAN_REGDEBUG +#ifdef CONFIG_STM32_CAN_REGDEBUG static uint32_t stm32can_vgetreg(uint32_t addr) { static uint32_t prevaddr = 0; @@ -398,7 +398,7 @@ static uint32_t stm32can_getfreg(struct stm32_can_s *priv, int offset) * ****************************************************************************/ -#ifdef CONFIG_STM32F7_CAN_REGDEBUG +#ifdef CONFIG_STM32_CAN_REGDEBUG static void stm32can_vputreg(uint32_t addr, uint32_t value) { /* Show the register value being written */ @@ -451,7 +451,7 @@ static void stm32can_putfreg(struct stm32_can_s *priv, int offset, * ****************************************************************************/ -#ifdef CONFIG_STM32F7_CAN_REGDEBUG +#ifdef CONFIG_STM32_CAN_REGDEBUG static void stm32can_dumpctrlregs(struct stm32_can_s *priv, const char *msg) { @@ -497,7 +497,7 @@ static void stm32can_dumpctrlregs(struct stm32_can_s *priv, * ****************************************************************************/ -#ifdef CONFIG_STM32F7_CAN_REGDEBUG +#ifdef CONFIG_STM32_CAN_REGDEBUG static void stm32can_dumpmbregs(struct stm32_can_s *priv, const char *msg) { @@ -564,7 +564,7 @@ static void stm32can_dumpmbregs(struct stm32_can_s *priv, * ****************************************************************************/ -#ifdef CONFIG_STM32F7_CAN_REGDEBUG +#ifdef CONFIG_STM32_CAN_REGDEBUG static void stm32can_dumpfiltregs(struct stm32_can_s *priv, const char *msg) { @@ -729,7 +729,7 @@ static void stm32can_errint(struct stm32_can_s *priv, bool enable) } else { - regval &= ~STM32F7_CAN_ERRINT; + regval &= ~STM32_CAN_ERRINT; } stm32can_putreg(priv, STM32_CAN_IER_OFFSET, regval); @@ -1860,15 +1860,15 @@ static int stm32can_bittiming(struct stm32_can_s *priv) } } - /* Otherwise, nquanta is CAN_BIT_QUANTA, ts1 is CONFIG_STM32F7_CAN_TSEG1, - * ts2 is CONFIG_STM32F7_CAN_TSEG2 and we calculate brp to achieve + /* Otherwise, nquanta is CAN_BIT_QUANTA, ts1 is CONFIG_STM32_CAN_TSEG1, + * ts2 is CONFIG_STM32_CAN_TSEG2 and we calculate brp to achieve * CAN_BIT_QUANTA quanta in the bit time */ else { - ts1 = CONFIG_STM32F7_CAN_TSEG1; - ts2 = CONFIG_STM32F7_CAN_TSEG2; + ts1 = CONFIG_STM32_CAN_TSEG1; + ts2 = CONFIG_STM32_CAN_TSEG2; brp = (tmp + (CAN_BIT_QUANTA / 2)) / CAN_BIT_QUANTA; DEBUGASSERT(brp >= 1 && brp <= CAN_BTR_BRP_MAX); } @@ -2036,21 +2036,21 @@ static void stm32can_reset(struct stm32_can_s *priv) /* Get the bits in the AHB1RSTR register needed to reset this CAN device */ -#ifdef CONFIG_STM32F7_CAN1 +#ifdef CONFIG_STM32_CAN1 if (priv->port == 1) { regbit = RCC_APB1RSTR_CAN1RST; } else #endif -#ifdef CONFIG_STM32F7_CAN2 +#ifdef CONFIG_STM32_CAN2 if (priv->port == 2) { regbit = RCC_APB1RSTR_CAN2RST; } else #endif -#ifdef CONFIG_STM32F7_CAN3 +#ifdef CONFIG_STM32_CAN3 if (priv->port == 3) { regbit = RCC_APB1RSTR_CAN3RST; @@ -2298,9 +2298,9 @@ static int stm32can_filterinit(struct stm32_can_s *priv) /* Assign half the filters to CAN1, half to CAN2 */ -#if defined(CONFIG_STM32F7_CONNECTIVITYLINE) || \ - defined(CONFIG_STM32F7_STM32F20XX) || \ - defined(CONFIG_STM32F7_STM32F4XXX) +#if defined(CONFIG_STM32_CONNECTIVITYLINE) || \ + defined(CONFIG_STM32_STM32F20XX) || \ + defined(CONFIG_STM32_STM32F4XXX) regval = stm32can_getfreg(priv, STM32_CAN_FMR_OFFSET); regval &= CAN_FMR_CAN2SB_MASK; regval |= (CAN_NFILTERS / 2) << CAN_FMR_CAN2SB_SHIFT; @@ -2432,7 +2432,7 @@ int stm32_cansockinitialize(int port) * by stm32_clockconfig() early in the reset sequence. */ -#ifdef CONFIG_STM32F7_CAN1 +#ifdef CONFIG_STM32_CAN1 if (port == 1) { /* Select the CAN1 device structure */ @@ -2448,7 +2448,7 @@ int stm32_cansockinitialize(int port) } else #endif -#ifdef CONFIG_STM32F7_CAN2 +#ifdef CONFIG_STM32_CAN2 if (port == 2) { /* Select the CAN2 device structure */ @@ -2464,7 +2464,7 @@ int stm32_cansockinitialize(int port) } else #endif -#ifdef CONFIG_STM32F7_CAN3 +#ifdef CONFIG_STM32_CAN3 if (port == 3) { /* Select the CAN3 device structure */ @@ -2526,15 +2526,15 @@ int stm32_cansockinitialize(int port) #if !defined(CONFIG_NETDEV_LATEINIT) void arm_netinitialize(void) { -#ifdef CONFIG_STM32F7_CAN1 +#ifdef CONFIG_STM32_CAN1 stm32_cansockinitialize(1); #endif -#ifdef CONFIG_STM32F7_CAN2 +#ifdef CONFIG_STM32_CAN2 stm32_cansockinitialize(2); #endif -#ifdef CONFIG_STM32F7_CAN3 +#ifdef CONFIG_STM32_CAN3 stm32_cansockinitialize(3); #endif } diff --git a/arch/arm/src/stm32f7/stm32_capture.c b/arch/arm/src/stm32f7/stm32_capture.c index 6e650a6e849e6..84efc445174b5 100644 --- a/arch/arm/src/stm32f7/stm32_capture.c +++ b/arch/arm/src/stm32f7/stm32_capture.c @@ -92,18 +92,18 @@ * intended for some other purpose. */ -#if defined(CONFIG_STM32F7_TIM1_CAP) || \ - defined(CONFIG_STM32F7_TIM2_CAP) || \ - defined(CONFIG_STM32F7_TIM3_CAP) || \ - defined(CONFIG_STM32F7_TIM4_CAP) || \ - defined(CONFIG_STM32F7_TIM5_CAP) || \ - defined(CONFIG_STM32F7_TIM8_CAP) || \ - defined(CONFIG_STM32F7_TIM9_CAP) || \ - defined(CONFIG_STM32F7_TIM10_CAP) || \ - defined(CONFIG_STM32F7_TIM11_CAP) || \ - defined(CONFIG_STM32F7_TIM12_CAP) || \ - defined(CONFIG_STM32F7_TIM13_CAP) || \ - defined(CONFIG_STM32F7_TIM14_CAP) +#if defined(CONFIG_STM32_TIM1_CAP) || \ + defined(CONFIG_STM32_TIM2_CAP) || \ + defined(CONFIG_STM32_TIM3_CAP) || \ + defined(CONFIG_STM32_TIM4_CAP) || \ + defined(CONFIG_STM32_TIM5_CAP) || \ + defined(CONFIG_STM32_TIM8_CAP) || \ + defined(CONFIG_STM32_TIM9_CAP) || \ + defined(CONFIG_STM32_TIM10_CAP) || \ + defined(CONFIG_STM32_TIM11_CAP) || \ + defined(CONFIG_STM32_TIM12_CAP) || \ + defined(CONFIG_STM32_TIM13_CAP) || \ + defined(CONFIG_STM32_TIM14_CAP) /**************************************************************************** * Private Types @@ -182,7 +182,7 @@ stm32_cap_gpio(const struct stm32_cap_priv_s *priv, int channel) { switch (priv->base) { -#ifdef CONFIG_STM32F7_TIM1_CAP +#ifdef CONFIG_STM32_TIM1_CAP case STM32_TIM1_BASE: switch (channel) { @@ -209,7 +209,7 @@ stm32_cap_gpio(const struct stm32_cap_priv_s *priv, int channel) } break; #endif -#ifdef CONFIG_STM32F7_TIM2_CAP +#ifdef CONFIG_STM32_TIM2_CAP case STM32_TIM2_BASE: switch (channel) { @@ -236,7 +236,7 @@ stm32_cap_gpio(const struct stm32_cap_priv_s *priv, int channel) } break; #endif -#ifdef CONFIG_STM32F7_TIM3_CAP +#ifdef CONFIG_STM32_TIM3_CAP case STM32_TIM3_BASE: switch (channel) { @@ -263,7 +263,7 @@ stm32_cap_gpio(const struct stm32_cap_priv_s *priv, int channel) } break; #endif -#ifdef CONFIG_STM32F7_TIM4_CAP +#ifdef CONFIG_STM32_TIM4_CAP case STM32_TIM4_BASE: switch (channel) { @@ -290,7 +290,7 @@ stm32_cap_gpio(const struct stm32_cap_priv_s *priv, int channel) } break; #endif -#ifdef CONFIG_STM32F7_TIM5_CAP +#ifdef CONFIG_STM32_TIM5_CAP case STM32_TIM5_BASE: switch (channel) { @@ -320,7 +320,7 @@ stm32_cap_gpio(const struct stm32_cap_priv_s *priv, int channel) /* TIM6 and TIM7 cannot be used in capture */ -#ifdef CONFIG_STM32F7_TIM8_CAP +#ifdef CONFIG_STM32_TIM8_CAP case STM32_TIM8_BASE: switch (channel) { @@ -348,7 +348,7 @@ stm32_cap_gpio(const struct stm32_cap_priv_s *priv, int channel) break; #endif -#ifdef CONFIG_STM32F7_TIM9_CAP +#ifdef CONFIG_STM32_TIM9_CAP case STM32_TIM9_BASE: switch (channel) { @@ -376,7 +376,7 @@ stm32_cap_gpio(const struct stm32_cap_priv_s *priv, int channel) break; #endif -#ifdef CONFIG_STM32F7_TIM10_CAP +#ifdef CONFIG_STM32_TIM10_CAP case STM32_TIM10_BASE: switch (channel) { @@ -404,7 +404,7 @@ stm32_cap_gpio(const struct stm32_cap_priv_s *priv, int channel) break; #endif -#ifdef CONFIG_STM32F7_TIM11_CAP +#ifdef CONFIG_STM32_TIM11_CAP case STM32_TIM11_BASE: switch (channel) { @@ -432,7 +432,7 @@ stm32_cap_gpio(const struct stm32_cap_priv_s *priv, int channel) break; #endif -#ifdef CONFIG_STM32F7_TIM12_CAP +#ifdef CONFIG_STM32_TIM12_CAP case STM32_TIM12_BASE: switch (channel) { @@ -460,7 +460,7 @@ stm32_cap_gpio(const struct stm32_cap_priv_s *priv, int channel) break; #endif -#ifdef CONFIG_STM32F7_TIM13_CAP +#ifdef CONFIG_STM32_TIM13_CAP case STM32_TIM13_BASE: switch (channel) { @@ -488,7 +488,7 @@ stm32_cap_gpio(const struct stm32_cap_priv_s *priv, int channel) break; #endif -#ifdef CONFIG_STM32F7_TIM14_CAP +#ifdef CONFIG_STM32_TIM14_CAP case STM32_TIM14_BASE: switch (channel) { @@ -528,31 +528,31 @@ static inline int stm32_cap_set_rcc(const struct stm32_cap_priv_s *priv, switch (priv->base) { -#ifdef CONFIG_STM32F7_TIM1_CAP +#ifdef CONFIG_STM32_TIM1_CAP case STM32_TIM1_BASE: offset = STM32_RCC_APB2ENR; mask = RCC_APB2ENR_TIM1EN; break; #endif -#ifdef CONFIG_STM32F7_TIM2_CAP +#ifdef CONFIG_STM32_TIM2_CAP case STM32_TIM2_BASE: offset = STM32_RCC_APB1ENR; mask = RCC_APB1ENR_TIM2EN; break; #endif -#ifdef CONFIG_STM32F7_TIM3_CAP +#ifdef CONFIG_STM32_TIM3_CAP case STM32_TIM3_BASE: offset = STM32_RCC_APB1ENR; mask = RCC_APB1ENR_TIM3EN; break; #endif -#ifdef CONFIG_STM32F7_TIM4_CAP +#ifdef CONFIG_STM32_TIM4_CAP case STM32_TIM4_BASE: offset = STM32_RCC_APB1ENR; mask = RCC_APB1ENR_TIM4EN; break; #endif -#ifdef CONFIG_STM32F7_TIM5_CAP +#ifdef CONFIG_STM32_TIM5_CAP case STM32_TIM5_BASE: offset = STM32_RCC_APB1ENR; mask = RCC_APB1ENR_TIM5EN; @@ -561,43 +561,43 @@ static inline int stm32_cap_set_rcc(const struct stm32_cap_priv_s *priv, /* TIM6 and TIM7 cannot be used in capture */ -#ifdef CONFIG_STM32F7_TIM8_CAP +#ifdef CONFIG_STM32_TIM8_CAP case STM32_TIM8_BASE: offset = STM32_RCC_APB2ENR; mask = RCC_APB2ENR_TIM8EN; break; #endif -#ifdef CONFIG_STM32F7_TIM9_CAP +#ifdef CONFIG_STM32_TIM9_CAP case STM32_TIM9_BASE: offset = STM32_RCC_APB2ENR; mask = RCC_APB2ENR_TIM9EN; break; #endif -#ifdef CONFIG_STM32F7_TIM10_CAP +#ifdef CONFIG_STM32_TIM10_CAP case STM32_TIM10_BASE: offset = STM32_RCC_APB2ENR; mask = RCC_APB2ENR_TIM10EN; break; #endif -#ifdef CONFIG_STM32F7_TIM11_CAP +#ifdef CONFIG_STM32_TIM11_CAP case STM32_TIM11_BASE: offset = STM32_RCC_APB2ENR; mask = RCC_APB2ENR_TIM11EN; break; #endif -#ifdef CONFIG_STM32F7_TIM12_CAP +#ifdef CONFIG_STM32_TIM12_CAP case STM32_TIM12_BASE: offset = STM32_RCC_APB1ENR; mask = RCC_APB1ENR_TIM12EN; break; #endif -#ifdef CONFIG_STM32F7_TIM13_CAP +#ifdef CONFIG_STM32_TIM13_CAP case STM32_TIM13_BASE: offset = STM32_RCC_APB1ENR; mask = RCC_APB1ENR_TIM13EN; break; #endif -#ifdef CONFIG_STM32F7_TIM14_CAP +#ifdef CONFIG_STM32_TIM14_CAP case STM32_TIM14_BASE: offset = STM32_RCC_APB1ENR; mask = RCC_APB1ENR_TIM14EN; @@ -1082,7 +1082,7 @@ struct stm32_cap_ops_s stm32_cap_ops = .getflags = &stm32_cap_getflags }; -#ifdef CONFIG_STM32F7_TIM1_CAP +#ifdef CONFIG_STM32_TIM1_CAP const struct stm32_cap_priv_s stm32_tim1_priv = { .ops = &stm32_cap_ops, @@ -1094,7 +1094,7 @@ const struct stm32_cap_priv_s stm32_tim1_priv = }; #endif -#ifdef CONFIG_STM32F7_TIM2_CAP +#ifdef CONFIG_STM32_TIM2_CAP const struct stm32_cap_priv_s stm32_tim2_priv = { .ops = &stm32_cap_ops, @@ -1106,7 +1106,7 @@ const struct stm32_cap_priv_s stm32_tim2_priv = }; #endif -#ifdef CONFIG_STM32F7_TIM3_CAP +#ifdef CONFIG_STM32_TIM3_CAP const struct stm32_cap_priv_s stm32_tim3_priv = { .ops = &stm32_cap_ops, @@ -1118,7 +1118,7 @@ const struct stm32_cap_priv_s stm32_tim3_priv = }; #endif -#ifdef CONFIG_STM32F7_TIM4_CAP +#ifdef CONFIG_STM32_TIM4_CAP const struct stm32_cap_priv_s stm32_tim4_priv = { .ops = &stm32_cap_ops, @@ -1130,7 +1130,7 @@ const struct stm32_cap_priv_s stm32_tim4_priv = }; #endif -#ifdef CONFIG_STM32F7_TIM5_CAP +#ifdef CONFIG_STM32_TIM5_CAP const struct stm32_cap_priv_s stm32_tim5_priv = { .ops = &stm32_cap_ops, @@ -1144,7 +1144,7 @@ const struct stm32_cap_priv_s stm32_tim5_priv = /* TIM6 and TIM7 cannot be used in capture */ -#ifdef CONFIG_STM32F7_TIM8_CAP +#ifdef CONFIG_STM32_TIM8_CAP const struct stm32_cap_priv_s stm32_tim8_priv = { .ops = &stm32_cap_ops, @@ -1156,7 +1156,7 @@ const struct stm32_cap_priv_s stm32_tim8_priv = }; #endif -#ifdef CONFIG_STM32F7_TIM9_CAP +#ifdef CONFIG_STM32_TIM9_CAP const struct stm32_cap_priv_s stm32_tim9_priv = { .ops = &stm32_cap_ops, @@ -1168,7 +1168,7 @@ const struct stm32_cap_priv_s stm32_tim9_priv = }; #endif -#ifdef CONFIG_STM32F7_TIM10_CAP +#ifdef CONFIG_STM32_TIM10_CAP const struct stm32_cap_priv_s stm32_tim10_priv = { .ops = &stm32_cap_ops, @@ -1180,7 +1180,7 @@ const struct stm32_cap_priv_s stm32_tim10_priv = }; #endif -#ifdef CONFIG_STM32F7_TIM11_CAP +#ifdef CONFIG_STM32_TIM11_CAP const struct stm32_cap_priv_s stm32_tim11_priv = { .ops = &stm32_cap_ops, @@ -1192,7 +1192,7 @@ const struct stm32_cap_priv_s stm32_tim11_priv = }; #endif -#ifdef CONFIG_STM32F7_TIM12_CAP +#ifdef CONFIG_STM32_TIM12_CAP const struct stm32_cap_priv_s stm32_tim12_priv = { .ops = &stm32_cap_ops, @@ -1204,7 +1204,7 @@ const struct stm32_cap_priv_s stm32_tim12_priv = }; #endif -#ifdef CONFIG_STM32F7_TIM13_CAP +#ifdef CONFIG_STM32_TIM13_CAP const struct stm32_cap_priv_s stm32_tim13_priv = { .ops = &stm32_cap_ops, @@ -1216,7 +1216,7 @@ const struct stm32_cap_priv_s stm32_tim13_priv = }; #endif -#ifdef CONFIG_STM32F7_TIM14_CAP +#ifdef CONFIG_STM32_TIM14_CAP const struct stm32_cap_priv_s stm32_tim14_priv = { .ops = &stm32_cap_ops, @@ -1232,54 +1232,54 @@ static inline const struct stm32_cap_priv_s * stm32_cap_get_priv(int timer) { switch (timer) { -#ifdef CONFIG_STM32F7_TIM1_CAP +#ifdef CONFIG_STM32_TIM1_CAP case 1: return &stm32_tim1_priv; #endif -#ifdef CONFIG_STM32F7_TIM2_CAP +#ifdef CONFIG_STM32_TIM2_CAP case 2: return &stm32_tim2_priv; #endif -#ifdef CONFIG_STM32F7_TIM3_CAP +#ifdef CONFIG_STM32_TIM3_CAP case 3: return &stm32_tim3_priv; #endif -#ifdef CONFIG_STM32F7_TIM4_CAP +#ifdef CONFIG_STM32_TIM4_CAP case 4: return &stm32_tim4_priv; #endif -#ifdef CONFIG_STM32F7_TIM5_CAP +#ifdef CONFIG_STM32_TIM5_CAP case 5: return &stm32_tim5_priv; #endif /* TIM6 and TIM7 cannot be used in capture */ -#ifdef CONFIG_STM32F7_TIM8_CAP +#ifdef CONFIG_STM32_TIM8_CAP case 8: return &stm32_tim8_priv; #endif -#ifdef CONFIG_STM32F7_TIM9_CAP +#ifdef CONFIG_STM32_TIM9_CAP case 9: return &stm32_tim9_priv; #endif -#ifdef CONFIG_STM32F7_TIM10_CAP +#ifdef CONFIG_STM32_TIM10_CAP case 10: return &stm32_tim10_priv; #endif -#ifdef CONFIG_STM32F7_TIM11_CAP +#ifdef CONFIG_STM32_TIM11_CAP case 11: return &stm32_tim11_priv; #endif -#ifdef CONFIG_STM32F7_TIM12_CAP +#ifdef CONFIG_STM32_TIM12_CAP case 12: return &stm32_tim12_priv; #endif -#ifdef CONFIG_STM32F7_TIM13_CAP +#ifdef CONFIG_STM32_TIM13_CAP case 13: return &stm32_tim13_priv; #endif -#ifdef CONFIG_STM32F7_TIM14_CAP +#ifdef CONFIG_STM32_TIM14_CAP case 14: return &stm32_tim14_priv; #endif @@ -1336,4 +1336,4 @@ int stm32_cap_deinit(struct stm32_cap_dev_s * dev) return OK; } -#endif /* defined(CONFIG_STM32F7_TIM1 || ... || TIM14) */ +#endif /* defined(CONFIG_STM32_TIM1 || ... || TIM14) */ diff --git a/arch/arm/src/stm32f7/stm32_config.h b/arch/arm/src/stm32f7/stm32_config.h index 9bec9e5870441..c017552e64dc7 100644 --- a/arch/arm/src/stm32f7/stm32_config.h +++ b/arch/arm/src/stm32f7/stm32_config.h @@ -38,62 +38,62 @@ /* GPIO IRQs ****************************************************************/ -#ifndef CONFIG_STM32F7_GPIO_IRQ -# undef CONFIG_STM32F7_GPIOA_IRQ -# undef CONFIG_STM32F7_GPIOB_IRQ -# undef CONFIG_STM32F7_GPIOC_IRQ -# undef CONFIG_STM32F7_GPIOD_IRQ -# undef CONFIG_STM32F7_GPIOE_IRQ +#ifndef CONFIG_STM32_GPIO_IRQ +# undef CONFIG_STM32_GPIOA_IRQ +# undef CONFIG_STM32_GPIOB_IRQ +# undef CONFIG_STM32_GPIOC_IRQ +# undef CONFIG_STM32_GPIOD_IRQ +# undef CONFIG_STM32_GPIOE_IRQ #endif -#if STM32F7_NPORTS < 1 -# undef CONFIG_STM32F7_GPIOA_IRQ +#if STM32_NPORTS < 1 +# undef CONFIG_STM32_GPIOA_IRQ #endif -#if STM32F7_NPORTS < 2 -# undef CONFIG_STM32F7_GPIOB_IRQ +#if STM32_NPORTS < 2 +# undef CONFIG_STM32_GPIOB_IRQ #endif -#if STM32F7_NPORTS < 3 -# undef CONFIG_STM32F7_GPIOC_IRQ +#if STM32_NPORTS < 3 +# undef CONFIG_STM32_GPIOC_IRQ #endif -#if STM32F7_NPORTS < 4 -# undef CONFIG_STM32F7_GPIOD_IRQ +#if STM32_NPORTS < 4 +# undef CONFIG_STM32_GPIOD_IRQ #endif -#if STM32F7_NPORTS < 5 -# undef CONFIG_STM32F7_GPIOE_IRQ +#if STM32_NPORTS < 5 +# undef CONFIG_STM32_GPIOE_IRQ #endif /* UARTs ********************************************************************/ /* Don't enable UARTs not supported by the chip. */ -#if STM32F7_NUART < 1 -# undef CONFIG_STM32F7_UART0 -# undef CONFIG_STM32F7_UART1 -# undef CONFIG_STM32F7_UART2 -# undef CONFIG_STM32F7_UART3 -# undef CONFIG_STM32F7_UART4 -#elif STM32F7_NUART < 2 -# undef CONFIG_STM32F7_UART1 -# undef CONFIG_STM32F7_UART2 -# undef CONFIG_STM32F7_UART3 -# undef CONFIG_STM32F7_UART4 -#elif STM32F7_NUART < 3 -# undef CONFIG_STM32F7_UART2 -# undef CONFIG_STM32F7_UART3 -# undef CONFIG_STM32F7_UART4 -#elif STM32F7_NUART < 4 -# undef CONFIG_STM32F7_UART3 -# undef CONFIG_STM32F7_UART4 -#elif STM32F7_NUART < 5 -# undef CONFIG_STM32F7_UART4 +#if STM32_NUART < 1 +# undef CONFIG_STM32_UART0 +# undef CONFIG_STM32_UART1 +# undef CONFIG_STM32_UART2 +# undef CONFIG_STM32_UART3 +# undef CONFIG_STM32_UART4 +#elif STM32_NUART < 2 +# undef CONFIG_STM32_UART1 +# undef CONFIG_STM32_UART2 +# undef CONFIG_STM32_UART3 +# undef CONFIG_STM32_UART4 +#elif STM32_NUART < 3 +# undef CONFIG_STM32_UART2 +# undef CONFIG_STM32_UART3 +# undef CONFIG_STM32_UART4 +#elif STM32_NUART < 4 +# undef CONFIG_STM32_UART3 +# undef CONFIG_STM32_UART4 +#elif STM32_NUART < 5 +# undef CONFIG_STM32_UART4 #endif /* Are any UARTs enabled? */ #undef HAVE_UART_DEVICE -#if defined(CONFIG_STM32F7_UART0) || defined(CONFIG_STM32F7_UART1) || \ - defined(CONFIG_STM32F7_UART2) || defined(CONFIG_STM32F7_UART3) || \ - defined(CONFIG_STM32F7_UART4) +#if defined(CONFIG_STM32_UART0) || defined(CONFIG_STM32_UART1) || \ + defined(CONFIG_STM32_UART2) || defined(CONFIG_STM32_UART3) || \ + defined(CONFIG_STM32_UART4) # define HAVE_UART_DEVICE 1 #endif @@ -104,32 +104,32 @@ */ #ifndef CONFIG_USART0_SERIALDRIVER -# undef CONFIG_STM32F7_USART0 +# undef CONFIG_STM32_USART0 #endif #ifndef CONFIG_USART1_SERIALDRIVER -# undef CONFIG_STM32F7_USART1 +# undef CONFIG_STM32_USART1 #endif #ifndef CONFIG_USART2_SERIALDRIVER -# undef CONFIG_STM32F7_USART2 +# undef CONFIG_STM32_USART2 #endif /* Don't enable USARTs not supported by the chip. */ -#if STM32F7_NUSART < 1 -# undef CONFIG_STM32F7_USART0 -# undef CONFIG_STM32F7_USART1 -# undef CONFIG_STM32F7_USART2 -#elif STM32F7_NUSART < 2 -# undef CONFIG_STM32F7_USART1 -# undef CONFIG_STM32F7_USART2 -#elif STM32F7_NUSART < 3 -# undef CONFIG_STM32F7_USART2 +#if STM32_NUSART < 1 +# undef CONFIG_STM32_USART0 +# undef CONFIG_STM32_USART1 +# undef CONFIG_STM32_USART2 +#elif STM32_NUSART < 2 +# undef CONFIG_STM32_USART1 +# undef CONFIG_STM32_USART2 +#elif STM32_NUSART < 3 +# undef CONFIG_STM32_USART2 #endif /* Are any USARTs enabled? */ -#if defined(CONFIG_STM32F7_USART0) || defined(CONFIG_STM32F7_USART1) || \ - defined(CONFIG_STM32F7_USART2) +#if defined(CONFIG_STM32_USART0) || defined(CONFIG_STM32_USART1) || \ + defined(CONFIG_STM32_USART2) # undef HAVE_UART_DEVICE # define HAVE_UART_DEVICE 1 #endif @@ -158,12 +158,12 @@ /* Is there a serial console? There should be no more than one defined. * It could be on any: - * UARTn, n=1..STM32F7_NUART, or - * USARTn, n=1..STM32F7_NUSART + * UARTn, n=1..STM32_NUART, or + * USARTn, n=1..STM32_NUSART */ #undef HAVE_SERIAL_CONSOLE -#if defined(CONFIG_UART0_SERIAL_CONSOLE) && defined(CONFIG_STM32F7_UART0) +#if defined(CONFIG_UART0_SERIAL_CONSOLE) && defined(CONFIG_STM32_UART0) # undef CONFIG_UART1_SERIAL_CONSOLE # undef CONFIG_UART2_SERIAL_CONSOLE # undef CONFIG_UART3_SERIAL_CONSOLE @@ -172,7 +172,7 @@ # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # define HAVE_SERIAL_CONSOLE 1 -#elif defined(CONFIG_UART1_SERIAL_CONSOLE) && defined(CONFIG_STM32F7_UART1) +#elif defined(CONFIG_UART1_SERIAL_CONSOLE) && defined(CONFIG_STM32_UART1) # undef CONFIG_UART0_SERIAL_CONSOLE # undef CONFIG_UART2_SERIAL_CONSOLE # undef CONFIG_UART3_SERIAL_CONSOLE @@ -181,7 +181,7 @@ # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # define HAVE_SERIAL_CONSOLE 1 -#elif defined(CONFIG_UART2_SERIAL_CONSOLE) && defined(CONFIG_STM32F7_UART2) +#elif defined(CONFIG_UART2_SERIAL_CONSOLE) && defined(CONFIG_STM32_UART2) # undef CONFIG_UART0_SERIAL_CONSOLE # undef CONFIG_UART1_SERIAL_CONSOLE # undef CONFIG_UART3_SERIAL_CONSOLE @@ -190,7 +190,7 @@ # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # define HAVE_SERIAL_CONSOLE 1 -#elif defined(CONFIG_UART3_SERIAL_CONSOLE) && defined(CONFIG_STM32F7_UART3) +#elif defined(CONFIG_UART3_SERIAL_CONSOLE) && defined(CONFIG_STM32_UART3) # undef CONFIG_UART0_SERIAL_CONSOLE # undef CONFIG_UART1_SERIAL_CONSOLE # undef CONFIG_UART2_SERIAL_CONSOLE @@ -199,7 +199,7 @@ # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # define HAVE_SERIAL_CONSOLE 1 -#elif defined(CONFIG_UART4_SERIAL_CONSOLE) && defined(CONFIG_STM32F7_UART4) +#elif defined(CONFIG_UART4_SERIAL_CONSOLE) && defined(CONFIG_STM32_UART4) # undef CONFIG_UART0_SERIAL_CONSOLE # undef CONFIG_UART1_SERIAL_CONSOLE # undef CONFIG_UART2_SERIAL_CONSOLE @@ -208,7 +208,7 @@ # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # define HAVE_SERIAL_CONSOLE 1 -#elif defined(CONFIG_USART0_SERIAL_CONSOLE) && defined(CONFIG_STM32F7_USART0) +#elif defined(CONFIG_USART0_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART0) # undef CONFIG_UART0_SERIAL_CONSOLE # undef CONFIG_UART1_SERIAL_CONSOLE # undef CONFIG_UART2_SERIAL_CONSOLE @@ -217,7 +217,7 @@ # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # define HAVE_SERIAL_CONSOLE 1 -#elif defined(CONFIG_USART1_SERIAL_CONSOLE) && defined(CONFIG_STM32F7_USART1) +#elif defined(CONFIG_USART1_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART1) # undef CONFIG_UART0_SERIAL_CONSOLE # undef CONFIG_UART1_SERIAL_CONSOLE # undef CONFIG_UART2_SERIAL_CONSOLE @@ -226,7 +226,7 @@ # undef CONFIG_USART0_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # define HAVE_SERIAL_CONSOLE 1 -#elif defined(CONFIG_USART2_SERIAL_CONSOLE) && defined(CONFIG_STM32F7_USART2) +#elif defined(CONFIG_USART2_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART2) # undef CONFIG_UART0_SERIAL_CONSOLE # undef CONFIG_UART1_SERIAL_CONSOLE # undef CONFIG_UART2_SERIAL_CONSOLE @@ -251,21 +251,21 @@ /* Don't enable SPI peripherals not supported by the chip. */ #if CHIP_NSPI < 1 -# undef CONFIG_STM32F7_SPI0 -# undef CONFIG_STM32F7_SPI1 +# undef CONFIG_STM32_SPI0 +# undef CONFIG_STM32_SPI1 #elif CHIP_NSPI < 2 -# undef CONFIG_STM32F7_SPI1 +# undef CONFIG_STM32_SPI1 #endif -#ifndef CONFIG_STM32F7_HAVE_SPI -# undef CONFIG_STM32F7_SPI0 -# undef CONFIG_STM32F7_SPI1 +#ifndef CONFIG_STM32_HAVE_SPI +# undef CONFIG_STM32_SPI0 +# undef CONFIG_STM32_SPI1 #endif /* Are any SPI peripherals enabled? */ -#if !defined(CONFIG_STM32F7_SPI0) && !defined(CONFIG_STM32F7_SPI0) -# undef CONFIG_STM32F7_HAVE_SPI +#if !defined(CONFIG_STM32_SPI0) && !defined(CONFIG_STM32_SPI0) +# undef CONFIG_STM32_HAVE_SPI #endif /**************************************************************************** diff --git a/arch/arm/src/stm32f7/stm32_dma.c b/arch/arm/src/stm32f7/stm32_dma.c index 72e2d1f52d360..75c9f5d952435 100644 --- a/arch/arm/src/stm32f7/stm32_dma.c +++ b/arch/arm/src/stm32f7/stm32_dma.c @@ -46,16 +46,16 @@ * families */ -#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM33F75XX) \ - || defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) \ - || defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) +#if defined(CONFIG_STM32_STM32F72XX) || defined(CONFIG_STM32_STM33F75XX) \ + || defined(CONFIG_STM32_STM32F74XX) || defined(CONFIG_STM32_STM32F75XX) \ + || defined(CONFIG_STM32_STM32F76XX) || defined(CONFIG_STM32_STM32F77XX) /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ #define DMA1_NSTREAMS 8 -#if STM32F7_NDMA > 1 +#if STM32_NDMA > 1 # define DMA2_NSTREAMS 8 # define DMA_NSTREAMS (DMA1_NSTREAMS+DMA2_NSTREAMS) #else @@ -148,7 +148,7 @@ static struct stm32_dma_s g_dma[DMA_NSTREAMS] = .sem = SEM_INITIALIZER(1), .base = STM32_DMA1_BASE + STM32_DMA_OFFSET(7), }, -#if STM32F7_NDMA > 1 +#if STM32_NDMA > 1 { .stream = 0, .irq = STM32_IRQ_DMA2S0, @@ -268,13 +268,13 @@ static inline struct stm32_dma_s *stm32_dmastream(unsigned int stream, { int index; - DEBUGASSERT(stream < DMA_NSTREAMS && controller < STM32F7_NDMA); + DEBUGASSERT(stream < DMA_NSTREAMS && controller < STM32_NDMA); /* Convert the controller + stream based on the fact that there are * 8 streams per controller. */ -#if STM32F7_NDMA > 1 +#if STM32_NDMA > 1 index = controller << 3 | stream; #else index = stream; @@ -376,7 +376,7 @@ static int stm32_dmainterrupt(int irq, void *context, void *arg) controller = DMA1; } else -#if STM32F7_NDMA > 1 +#if STM32_NDMA > 1 if (irq >= STM32_IRQ_DMA2S0 && irq <= STM32_IRQ_DMA2S4) { stream = irq - STM32_IRQ_DMA2S0; @@ -596,7 +596,7 @@ void stm32_dmasetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr, " ntransfers: %zu scr: %08" PRIx32 "\n", paddr, maddr, ntransfers, scr); -#ifdef CONFIG_STM32F7_DMACAPABLE +#ifdef CONFIG_STM32_DMACAPABLE DEBUGASSERT(stm32_dmacapable(maddr, ntransfers, scr)); #endif @@ -895,7 +895,7 @@ size_t stm32_dmaresidual(DMA_HANDLE handle) * ****************************************************************************/ -#ifdef CONFIG_STM32F7_DMACAPABLE +#ifdef CONFIG_STM32_DMACAPABLE bool stm32_dmacapable(uintptr_t maddr, uint32_t count, uint32_t ccr) { uint32_t transfer_size; @@ -958,7 +958,7 @@ bool stm32_dmacapable(uintptr_t maddr, uint32_t count, uint32_t ccr) dmawarn("stm32_dmacapable:" " dcache unaligned maddr:0x%08" PRIxPTR " mend:0x%08" PRIx32 "\n", maddr, mend); -#if !defined(CONFIG_STM32F7_DMACAPABLE_ASSUME_CACHE_ALIGNED) +#if !defined(CONFIG_STM32_DMACAPABLE_ASSUME_CACHE_ALIGNED) return false; #endif } @@ -1121,4 +1121,4 @@ void stm32_dmadump(DMA_HANDLE handle, const struct stm32_dmaregs_s *regs, } #endif -#endif /* CONFIG_STM32F7_STM32F74XX || CONFIG_STM32F7_STM32F75XX */ +#endif /* CONFIG_STM32_STM32F74XX || CONFIG_STM32_STM32F75XX */ diff --git a/arch/arm/src/stm32f7/stm32_dma.h b/arch/arm/src/stm32f7/stm32_dma.h index d858a62c14ff6..7ad69cd3ec2f5 100644 --- a/arch/arm/src/stm32f7/stm32_dma.h +++ b/arch/arm/src/stm32f7/stm32_dma.h @@ -242,7 +242,7 @@ size_t stm32_dmaresidual(DMA_HANDLE handle); * ****************************************************************************/ -#ifdef CONFIG_STM32F7_DMACAPABLE +#ifdef CONFIG_STM32_DMACAPABLE bool stm32_dmacapable(uintptr_t maddr, uint32_t count, uint32_t ccr); #else # define stm32_dmacapable(maddr, count, ccr) (true) diff --git a/arch/arm/src/stm32f7/stm32_dma2d.c b/arch/arm/src/stm32f7/stm32_dma2d.c index f8cd2d298bb69..cb8cdc15fe60a 100644 --- a/arch/arm/src/stm32f7/stm32_dma2d.c +++ b/arch/arm/src/stm32f7/stm32_dma2d.c @@ -91,7 +91,7 @@ /* Debug option */ -#ifdef CONFIG_STM32F7_DMA2D_REGDEBUG +#ifdef CONFIG_STM32_DMA2D_REGDEBUG # define regerr lcderr # define reginfo lcdinfo #else @@ -109,7 +109,7 @@ struct stm32_dma2d_s { struct dma2d_layer_s dma2d; /* Public dma2d interface */ -#ifdef CONFIG_STM32F7_FB_CMAP +#ifdef CONFIG_STM32_FB_CMAP uint32_t *clut; /* Color lookup table */ #endif @@ -172,7 +172,7 @@ static const uintptr_t stm32_color_layer_t[DMA2D_NLAYERS] = STM32_DMA2D_OCOLR }; -#ifdef CONFIG_STM32F7_FB_CMAP +#ifdef CONFIG_STM32_FB_CMAP /* DMA2D clut memory address register */ static const uintptr_t stm32_cmar_layer_t[DMA2D_NLAYERS - 1] = @@ -192,7 +192,7 @@ static void stm32_dma2d_control(uint32_t setbits, uint32_t clrbits); static int stm32_dma2dirq(int irq, void *context, void *arg); static int stm32_dma2d_waitforirq(void); static int stm32_dma2d_start(void); -#ifdef CONFIG_STM32F7_FB_CMAP +#ifdef CONFIG_STM32_FB_CMAP static int stm32_dma2d_loadclut(uintptr_t reg); #endif static uint32_t @@ -212,7 +212,7 @@ static void stm32_dma2d_lpfc(int lid, uint32_t blendmode, uint8_t alpha, /* Public Functions */ -#ifdef CONFIG_STM32F7_FB_CMAP +#ifdef CONFIG_STM32_FB_CMAP static int stm32_dma2d_setclut(const struct fb_cmap_s *cmap); #endif static int stm32_dma2d_fillcolor(struct stm32_dma2d_overlay_s *oinfo, @@ -239,15 +239,15 @@ static bool g_initialized; /* Allocate clut */ -#ifdef CONFIG_STM32F7_FB_CMAP +#ifdef CONFIG_STM32_FB_CMAP static uint32_t g_clut[STM32_DMA2D_NCLUT * -# ifdef CONFIG_STM32F7_FB_TRANSPARENCY +# ifdef CONFIG_STM32_FB_TRANSPARENCY 4 # else 3 # endif / 4]; -#endif /* CONFIG_STM32F7_FB_CMAP */ +#endif /* CONFIG_STM32_FB_CMAP */ /* The DMA2D mutex that enforces mutually exclusive access */ @@ -270,14 +270,14 @@ static struct stm32_dma2d_s g_dma2ddev = { .dma2d = { -#ifdef CONFIG_STM32F7_FB_CMAP +#ifdef CONFIG_STM32_FB_CMAP .setclut = stm32_dma2d_setclut, #endif .fillcolor = stm32_dma2d_fillcolor, .blit = stm32_dma2d_blit, .blend = stm32_dma2d_blend }, -#ifdef CONFIG_STM32F7_FB_CMAP +#ifdef CONFIG_STM32_FB_CMAP .clut = g_clut, #endif .lock = &g_lock @@ -344,7 +344,7 @@ static int stm32_dma2dirq(int irq, void *context, void *arg) putreg32(DMA2D_IFCR_CTCIF, STM32_DMA2D_IFCR); priv->error = OK; } -#ifdef CONFIG_STM32F7_DMA2D_L8 +#ifdef CONFIG_STM32_DMA2D_L8 else if (regval & DMA2D_ISR_CTCIF) { /* CLUT transfer complete interrupt */ @@ -461,7 +461,7 @@ static int stm32_dma2d_waitforirq(void) * ****************************************************************************/ -#ifdef CONFIG_STM32F7_DMA2D_L8 +#ifdef CONFIG_STM32_DMA2D_L8 static int stm32_dma2d_loadclut(uintptr_t pfcreg) { int ret; @@ -681,7 +681,7 @@ static void stm32_dma2d_lpfc(int lid, uint32_t blendmode, uint8_t alpha, pfccrreg = DMA2D_XGPFCCR_CM(fmt); -#ifdef CONFIG_STM32F7_FB_CMAP +#ifdef CONFIG_STM32_FB_CMAP if (fmt == DMA2D_PF_L8) { struct stm32_dma2d_s *layer = &g_dma2ddev; @@ -692,7 +692,7 @@ static void stm32_dma2d_lpfc(int lid, uint32_t blendmode, uint8_t alpha, /* Set the CLUT color mode */ -# ifndef CONFIG_STM32F7_FB_TRANSPARENCY +# ifndef CONFIG_STM32_FB_TRANSPARENCY pfccrreg |= DMA2D_XGPFCCR_CCM; # endif @@ -708,7 +708,7 @@ static void stm32_dma2d_lpfc(int lid, uint32_t blendmode, uint8_t alpha, stm32_dma2d_loadclut(stm32_pfccr_layer_t[lid]); } -#endif /* CONFIG_STM32F7_FB_CMAP */ +#endif /* CONFIG_STM32_FB_CMAP */ /* Set alpha blend mode */ @@ -744,7 +744,7 @@ static void stm32_dma2d_lpfc(int lid, uint32_t blendmode, uint8_t alpha, * ****************************************************************************/ -#ifdef CONFIG_STM32F7_FB_CMAP +#ifdef CONFIG_STM32_FB_CMAP static int stm32_dma2d_setclut(const struct fb_cmap_s *cmap) { int n; @@ -760,7 +760,7 @@ static int stm32_dma2d_setclut(const struct fb_cmap_s *cmap) * blit operation becomes active */ -# ifndef CONFIG_STM32F7_FB_TRANSPARENCY +# ifndef CONFIG_STM32_FB_TRANSPARENCY uint8_t *clut = (uint8_t *)g_dma2ddev.clut; uint16_t offset = 3 * n; @@ -789,7 +789,7 @@ static int stm32_dma2d_setclut(const struct fb_cmap_s *cmap) nxmutex_unlock(priv->lock); return OK; } -#endif /* CONFIG_STM32F7_FB_CMAP */ +#endif /* CONFIG_STM32_FB_CMAP */ /**************************************************************************** * Name: stm32_dma2d_fillcolor @@ -822,7 +822,7 @@ static int stm32_dma2d_fillcolor(struct stm32_dma2d_overlay_s *oinfo, lcdinfo("oinfo=%p, argb=%08" PRIx32 "\n", oinfo, argb); -#ifdef CONFIG_STM32F7_FB_CMAP +#ifdef CONFIG_STM32_FB_CMAP if (oinfo->fmt == DMA2D_PF_L8) { /* CLUT output not supported */ @@ -1006,7 +1006,7 @@ static int stm32_dma2d_blend(struct stm32_dma2d_overlay_s *doverlay, "barea.h=%d\n", doverlay, destxpos, destypos, foverlay, forexpos, foreypos, boverlay, barea, barea->x, barea->y, barea->w, barea->h); -#ifdef CONFIG_STM32F7_FB_CMAP +#ifdef CONFIG_STM32_FB_CMAP if (doverlay->fmt == DMA2D_PF_L8) { /* CLUT output not supported */ @@ -1095,7 +1095,7 @@ int stm32_dma2dinitialize(void) * arch/arm/src/stm32f7/stm32f7xxxx_rcc.c */ -#ifdef CONFIG_STM32F7_FB_CMAP +#ifdef CONFIG_STM32_FB_CMAP /* Enable dma2d transfer and clut loading interrupts only */ stm32_dma2d_control(DMA2D_CR_TCIE | DMA2D_CR_CTCIE, DMA2D_CR_TEIE | diff --git a/arch/arm/src/stm32f7/stm32_dma2d.h b/arch/arm/src/stm32f7/stm32_dma2d.h index 0f84a7732bf37..06ace50a01d2f 100644 --- a/arch/arm/src/stm32f7/stm32_dma2d.h +++ b/arch/arm/src/stm32f7/stm32_dma2d.h @@ -65,7 +65,7 @@ struct dma2d_layer_s * On error - -EINVAL */ -#ifdef CONFIG_STM32F7_FB_CMAP +#ifdef CONFIG_STM32_FB_CMAP int (*setclut)(const struct fb_cmap_s * cmap); #endif diff --git a/arch/arm/src/stm32f7/stm32_dtcm.h b/arch/arm/src/stm32f7/stm32_dtcm.h index 980add5f69fee..4299724554458 100644 --- a/arch/arm/src/stm32f7/stm32_dtcm.h +++ b/arch/arm/src/stm32f7/stm32_dtcm.h @@ -43,11 +43,11 @@ /* The STM32 F7 have DTCM memory */ -#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX) \ - || defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) +#if defined(CONFIG_STM32_STM32F72XX) || defined(CONFIG_STM32_STM32F73XX) \ + || defined(CONFIG_STM32_STM32F74XX) || defined(CONFIG_STM32_STM32F75XX) # define DTCM_START 0x20000000 # define DTCM_END 0x20010000 -#elif defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) +#elif defined(CONFIG_STM32_STM32F76XX) || defined(CONFIG_STM32_STM32F77XX) # define DTCM_START 0x20000000 # define DTCM_END 0x20020000 #else @@ -58,7 +58,7 @@ * heap. */ -#ifndef CONFIG_STM32F7_DTCMEXCLUDE +#ifndef CONFIG_STM32_DTCMEXCLUDE # undef HAVE_DTCM_HEAP #endif diff --git a/arch/arm/src/stm32f7/stm32_dumpgpio.c b/arch/arm/src/stm32f7/stm32_dumpgpio.c index bf70e68ec45f4..727ac68639a25 100644 --- a/arch/arm/src/stm32f7/stm32_dumpgpio.c +++ b/arch/arm/src/stm32f7/stm32_dumpgpio.c @@ -44,9 +44,9 @@ * families */ -#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) \ - || defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) \ - || defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) +#if defined(CONFIG_STM32_STM32F74XX) || defined(CONFIG_STM32_STM32F75XX) \ + || defined(CONFIG_STM32_STM32F74XX) || defined(CONFIG_STM32_STM32F75XX) \ + || defined(CONFIG_STM32_STM32F76XX) || defined(CONFIG_STM32_STM32F77XX) /**************************************************************************** * Private Data @@ -54,31 +54,31 @@ /* Port letters for prettier debug output */ -static const char g_portchar[STM32F7_NGPIO] = +static const char g_portchar[STM32_NGPIO] = { -#if STM32F7_NGPIO > 11 +#if STM32_NGPIO > 11 # error "Additional support required for this number of GPIOs" -#elif STM32F7_NGPIO > 10 +#elif STM32_NGPIO > 10 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 'I', 'J', 'K' -#elif STM32F7_NGPIO > 9 +#elif STM32_NGPIO > 9 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 'I', 'J' -#elif STM32F7_NGPIO > 8 +#elif STM32_NGPIO > 8 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 'I' -#elif STM32F7_NGPIO > 7 +#elif STM32_NGPIO > 7 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H' -#elif STM32F7_NGPIO > 6 +#elif STM32_NGPIO > 6 'A', 'B', 'C', 'D', 'E', 'F', 'G' -#elif STM32F7_NGPIO > 5 +#elif STM32_NGPIO > 5 'A', 'B', 'C', 'D', 'E', 'F' -#elif STM32F7_NGPIO > 4 +#elif STM32_NGPIO > 4 'A', 'B', 'C', 'D', 'E' -#elif STM32F7_NGPIO > 3 +#elif STM32_NGPIO > 3 'A', 'B', 'C', 'D' -#elif STM32F7_NGPIO > 2 +#elif STM32_NGPIO > 2 'A', 'B', 'C' -#elif STM32F7_NGPIO > 1 +#elif STM32_NGPIO > 1 'A', 'B' -#elif STM32F7_NGPIO > 0 +#elif STM32_NGPIO > 0 'A' #else # error "Bad number of GPIOs" @@ -112,7 +112,7 @@ int stm32_dumpgpio(uint32_t pinset, const char *msg) flags = enter_critical_section(); - DEBUGASSERT(port < STM32F7_NGPIO); + DEBUGASSERT(port < STM32_NGPIO); gpioinfo("GPIO%c pinset: %08" PRIx32 " base: %08" PRIx32 " -- %s\n", g_portchar[port], pinset, base, msg); @@ -144,5 +144,5 @@ int stm32_dumpgpio(uint32_t pinset, const char *msg) return OK; } -#endif /* CONFIG_STM32F7_STM32F74XX || CONFIG_STM32F7_STM32F75XX */ +#endif /* CONFIG_STM32_STM32F74XX || CONFIG_STM32_STM32F75XX */ #endif /* CONFIG_DEBUG_GPIO_INFO */ diff --git a/arch/arm/src/stm32f7/stm32_ethernet.c b/arch/arm/src/stm32f7/stm32_ethernet.c index 22c185ac8f825..666186b2cebb7 100644 --- a/arch/arm/src/stm32f7/stm32_ethernet.c +++ b/arch/arm/src/stm32f7/stm32_ethernet.c @@ -65,12 +65,12 @@ #include -/* STM32F7_NETHERNET determines the number of physical interfaces that can - * be supported by the hardware. CONFIG_STM32F7_ETHMAC will defined if +/* STM32_NETHERNET determines the number of physical interfaces that can + * be supported by the hardware. CONFIG_STM32_ETHMAC will defined if * any STM32F7 Ethernet support is enabled in the configuration. */ -#if STM32F7_NETHERNET > 0 && defined(CONFIG_STM32F7_ETHMAC) +#if STM32_NETHERNET > 0 && defined(CONFIG_STM32_ETHMAC) /**************************************************************************** * Pre-processor Definitions @@ -78,7 +78,7 @@ /* Configuration ************************************************************/ -#if STM32F7_NETHERNET > 1 +#if STM32_NETHERNET > 1 # error "Logic to support multiple Ethernet interfaces is incomplete" #endif @@ -101,76 +101,76 @@ #define ETHWORK LPWORK -#ifndef CONFIG_STM32F7_PHYADDR -# error "CONFIG_STM32F7_PHYADDR must be defined in the NuttX configuration" +#ifndef CONFIG_STM32_PHYADDR +# error "CONFIG_STM32_PHYADDR must be defined in the NuttX configuration" #endif -#if !defined(CONFIG_STM32F7_MII) && !defined(CONFIG_STM32F7_RMII) -# warning "Neither CONFIG_STM32F7_MII nor CONFIG_STM32F7_RMII defined" +#if !defined(CONFIG_STM32_MII) && !defined(CONFIG_STM32_RMII) +# warning "Neither CONFIG_STM32_MII nor CONFIG_STM32_RMII defined" #endif -#if defined(CONFIG_STM32F7_MII) && defined(CONFIG_STM32F7_RMII) -# error "Both CONFIG_STM32F7_MII and CONFIG_STM32F7_RMII defined" +#if defined(CONFIG_STM32_MII) && defined(CONFIG_STM32_RMII) +# error "Both CONFIG_STM32_MII and CONFIG_STM32_RMII defined" #endif -#ifdef CONFIG_STM32F7_MII -# if !defined(CONFIG_STM32F7_MII_MCO1) && !defined(CONFIG_STM32F7_MII_MCO2) && \ - !defined(CONFIG_STM32F7_MII_EXTCLK) -# warning "Neither CONFIG_STM32F7_MII_MCO1, CONFIG_STM32F7_MII_MCO2, nor CONFIG_STM32F7_MII_EXTCLK defined" +#ifdef CONFIG_STM32_MII +# if !defined(CONFIG_STM32_MII_MCO1) && !defined(CONFIG_STM32_MII_MCO2) && \ + !defined(CONFIG_STM32_MII_EXTCLK) +# warning "Neither CONFIG_STM32_MII_MCO1, CONFIG_STM32_MII_MCO2, nor CONFIG_STM32_MII_EXTCLK defined" # endif -# if defined(CONFIG_STM32F7_MII_MCO1) && defined(CONFIG_STM32F7_MII_MCO2) -# error "Both CONFIG_STM32F7_MII_MCO1 and CONFIG_STM32F7_MII_MCO2 defined" +# if defined(CONFIG_STM32_MII_MCO1) && defined(CONFIG_STM32_MII_MCO2) +# error "Both CONFIG_STM32_MII_MCO1 and CONFIG_STM32_MII_MCO2 defined" # endif #endif -#ifdef CONFIG_STM32F7_RMII -# if !defined(CONFIG_STM32F7_RMII_MCO1) && !defined(CONFIG_STM32F7_RMII_MCO2) && \ - !defined(CONFIG_STM32F7_RMII_EXTCLK) -# warning "Neither CONFIG_STM32F7_RMII_MCO1, CONFIG_STM32F7_RMII_MCO2, nor CONFIG_STM32F7_RMII_EXTCLK defined" +#ifdef CONFIG_STM32_RMII +# if !defined(CONFIG_STM32_RMII_MCO1) && !defined(CONFIG_STM32_RMII_MCO2) && \ + !defined(CONFIG_STM32_RMII_EXTCLK) +# warning "Neither CONFIG_STM32_RMII_MCO1, CONFIG_STM32_RMII_MCO2, nor CONFIG_STM32_RMII_EXTCLK defined" # endif -# if defined(CONFIG_STM32F7_RMII_MCO1) && defined(CONFIG_STM32F7_RMII_MCO2) -# error "Both CONFIG_STM32F7_RMII_MCO1 and CONFIG_STM32F7_RMII_MCO2 defined" +# if defined(CONFIG_STM32_RMII_MCO1) && defined(CONFIG_STM32_RMII_MCO2) +# error "Both CONFIG_STM32_RMII_MCO1 and CONFIG_STM32_RMII_MCO2 defined" # endif #endif -#ifdef CONFIG_STM32F7_AUTONEG -# ifndef CONFIG_STM32F7_PHYSR -# error "CONFIG_STM32F7_PHYSR must be defined in the NuttX configuration" +#ifdef CONFIG_STM32_AUTONEG +# ifndef CONFIG_STM32_PHYSR +# error "CONFIG_STM32_PHYSR must be defined in the NuttX configuration" # endif -# ifdef CONFIG_STM32F7_PHYSR_ALTCONFIG -# ifndef CONFIG_STM32F7_PHYSR_ALTMODE -# error "CONFIG_STM32F7_PHYSR_ALTMODE must be defined in the NuttX configuration" +# ifdef CONFIG_STM32_PHYSR_ALTCONFIG +# ifndef CONFIG_STM32_PHYSR_ALTMODE +# error "CONFIG_STM32_PHYSR_ALTMODE must be defined in the NuttX configuration" # endif -# ifndef CONFIG_STM32F7_PHYSR_10HD -# error "CONFIG_STM32F7_PHYSR_10HD must be defined in the NuttX configuration" +# ifndef CONFIG_STM32_PHYSR_10HD +# error "CONFIG_STM32_PHYSR_10HD must be defined in the NuttX configuration" # endif -# ifndef CONFIG_STM32F7_PHYSR_100HD -# error "CONFIG_STM32F7_PHYSR_100HD must be defined in the NuttX configuration" +# ifndef CONFIG_STM32_PHYSR_100HD +# error "CONFIG_STM32_PHYSR_100HD must be defined in the NuttX configuration" # endif -# ifndef CONFIG_STM32F7_PHYSR_10FD -# error "CONFIG_STM32F7_PHYSR_10FD must be defined in the NuttX configuration" +# ifndef CONFIG_STM32_PHYSR_10FD +# error "CONFIG_STM32_PHYSR_10FD must be defined in the NuttX configuration" # endif -# ifndef CONFIG_STM32F7_PHYSR_100FD -# error "CONFIG_STM32F7_PHYSR_100FD must be defined in the NuttX configuration" +# ifndef CONFIG_STM32_PHYSR_100FD +# error "CONFIG_STM32_PHYSR_100FD must be defined in the NuttX configuration" # endif # else -# ifndef CONFIG_STM32F7_PHYSR_SPEED -# error "CONFIG_STM32F7_PHYSR_SPEED must be defined in the NuttX configuration" +# ifndef CONFIG_STM32_PHYSR_SPEED +# error "CONFIG_STM32_PHYSR_SPEED must be defined in the NuttX configuration" # endif -# ifndef CONFIG_STM32F7_PHYSR_100MBPS -# error "CONFIG_STM32F7_PHYSR_100MBPS must be defined in the NuttX configuration" +# ifndef CONFIG_STM32_PHYSR_100MBPS +# error "CONFIG_STM32_PHYSR_100MBPS must be defined in the NuttX configuration" # endif -# ifndef CONFIG_STM32F7_PHYSR_MODE -# error "CONFIG_STM32F7_PHYSR_MODE must be defined in the NuttX configuration" +# ifndef CONFIG_STM32_PHYSR_MODE +# error "CONFIG_STM32_PHYSR_MODE must be defined in the NuttX configuration" # endif -# ifndef CONFIG_STM32F7_PHYSR_FULLDUPLEX -# error "CONFIG_STM32F7_PHYSR_FULLDUPLEX must be defined in the NuttX configuration" +# ifndef CONFIG_STM32_PHYSR_FULLDUPLEX +# error "CONFIG_STM32_PHYSR_FULLDUPLEX must be defined in the NuttX configuration" # endif # endif #endif -#ifdef CONFIG_STM32F7_ETH_PTP -# warning "CONFIG_STM32F7_ETH_PTP is not yet supported" +#ifdef CONFIG_STM32_ETH_PTP +# warning "CONFIG_STM32_ETH_PTP is not yet supported" #endif /* This driver does not use enhanced descriptors. Enhanced descriptors must @@ -178,8 +178,8 @@ * supported. */ -#undef CONFIG_STM32F7_ETH_ENHANCEDDESC -#undef CONFIG_STM32F7_ETH_HWCHECKSUM +#undef CONFIG_STM32_ETH_ENHANCEDDESC +#undef CONFIG_STM32_ETH_HWCHECKSUM /* Add 4 to the configured buffer size to account for the 2 byte checksum * memory needed at the end of the maximum size packet. Buffer sizes must @@ -189,8 +189,8 @@ #define OPTIMAL_ETH_BUFSIZE ((CONFIG_NET_ETH_PKTSIZE + 4 + 15) & ~15) -#ifdef CONFIG_STM32F7_ETH_BUFSIZE -# define ETH_BUFSIZE CONFIG_STM32F7_ETH_BUFSIZE +#ifdef CONFIG_STM32_ETH_BUFSIZE +# define ETH_BUFSIZE CONFIG_STM32_ETH_BUFSIZE #else # define ETH_BUFSIZE OPTIMAL_ETH_BUFSIZE #endif @@ -207,16 +207,16 @@ # warning "You using an incomplete/untested configuration" #endif -#ifndef CONFIG_STM32F7_ETH_NRXDESC -# define CONFIG_STM32F7_ETH_NRXDESC 8 +#ifndef CONFIG_STM32_ETH_NRXDESC +# define CONFIG_STM32_ETH_NRXDESC 8 #endif -#ifndef CONFIG_STM32F7_ETH_NTXDESC -# define CONFIG_STM32F7_ETH_NTXDESC 4 +#ifndef CONFIG_STM32_ETH_NTXDESC +# define CONFIG_STM32_ETH_NTXDESC 4 #endif /* We need at least one more free buffer than transmit buffers */ -#define STM32_ETH_NFREEBUFFERS (CONFIG_STM32F7_ETH_NTXDESC+1) +#define STM32_ETH_NFREEBUFFERS (CONFIG_STM32_ETH_NTXDESC+1) /* Buffers use for DMA access must begin on an address aligned with the * D-Cache line and must be an even multiple of the D-Cache line size. @@ -231,7 +231,7 @@ #define DMA_ALIGN_UP(n) (((n) + DMA_BUFFER_MASK) & ~DMA_BUFFER_MASK) #define DMA_ALIGN_DOWN(n) ((n) & ~DMA_BUFFER_MASK) -#ifndef CONFIG_STM32F7_ETH_ENHANCEDDESC +#ifndef CONFIG_STM32_ETH_ENHANCEDDESC # define RXDESC_SIZE 16 # define TXDESC_SIZE 16 #else @@ -243,21 +243,21 @@ #define TXDESC_PADSIZE DMA_ALIGN_UP(TXDESC_SIZE) #define ALIGNED_BUFSIZE DMA_ALIGN_UP(ETH_BUFSIZE) -#define RXTABLE_SIZE (STM32F7_NETHERNET * CONFIG_STM32F7_ETH_NRXDESC) -#define TXTABLE_SIZE (STM32F7_NETHERNET * CONFIG_STM32F7_ETH_NTXDESC) +#define RXTABLE_SIZE (STM32_NETHERNET * CONFIG_STM32_ETH_NRXDESC) +#define TXTABLE_SIZE (STM32_NETHERNET * CONFIG_STM32_ETH_NTXDESC) -#define RXBUFFER_SIZE (CONFIG_STM32F7_ETH_NRXDESC * ALIGNED_BUFSIZE) -#define RXBUFFER_ALLOC (STM32F7_NETHERNET * RXBUFFER_SIZE) +#define RXBUFFER_SIZE (CONFIG_STM32_ETH_NRXDESC * ALIGNED_BUFSIZE) +#define RXBUFFER_ALLOC (STM32_NETHERNET * RXBUFFER_SIZE) #define TXBUFFER_SIZE (STM32_ETH_NFREEBUFFERS * ALIGNED_BUFSIZE) -#define TXBUFFER_ALLOC (STM32F7_NETHERNET * TXBUFFER_SIZE) +#define TXBUFFER_ALLOC (STM32_NETHERNET * TXBUFFER_SIZE) /* Extremely detailed register debug that you would normally never want * enabled. */ #ifndef CONFIG_DEBUG_NET_INFO -# undef CONFIG_STM32F7_ETHMAC_REGDEBUG +# undef CONFIG_STM32_ETHMAC_REGDEBUG #endif /* Clocking *****************************************************************/ @@ -338,7 +338,7 @@ * ETH_MACCR_APCS Automatic pad/CRC stripping 0 (disabled) * ETH_MACCR_RD Retry disable 1 (disabled) * ETH_MACCR_IPCO IPv4 checksum offload Depends on - * CONFIG_STM32F7_ETH_HWCHECKSUM + * CONFIG_STM32_ETH_HWCHECKSUM * ETH_MACCR_LM Loopback mode 0 (disabled) * ETH_MACCR_ROD Receive own disable 0 (enabled) * ETH_MACCR_CSD Carrier sense disable 0 (enabled) @@ -353,7 +353,7 @@ * ETH_MACCR_FES Fast Ethernet speed Depends on priv->mbps100 */ -#ifdef CONFIG_STM32F7_ETH_HWCHECKSUM +#ifdef CONFIG_STM32_ETH_HWCHECKSUM # define MACCR_SET_BITS \ (ETH_MACCR_BL_10 | ETH_MACCR_RD | ETH_MACCR_IPCO | ETH_MACCR_IFG(96)) #else @@ -471,13 +471,13 @@ * ETH_DMAOMR_TTC Transmit threshold control 0 (64 bytes) * ETH_DMAOMR_FTF Flush transmit FIFO 0 (no flush) * ETH_DMAOMR_TSF Transmit store and forward Depends on - * CONFIG_STM32F7_ETH_HWCHECKSUM + * CONFIG_STM32_ETH_HWCHECKSUM * ETH_DMAOMR_DFRF Disable flushing of 0 (enabled) * received frames * ETH_DMAOMR_RSF Receive store and forward Depends on - * CONFIG_STM32F7_ETH_HWCHECKSUM + * CONFIG_STM32_ETH_HWCHECKSUM * TH_DMAOMR_DTCEFD Dropping of TCP/IP checksum Depends on - * error frames disable CONFIG_STM32F7_ETH_HWCHECKSUM + * error frames disable CONFIG_STM32_ETH_HWCHECKSUM * * When the checksum offload feature is enabled, we need to enable the Store * and Forward mode: the store and forward guarantee that a whole frame is @@ -485,7 +485,7 @@ * checksum is OK the DMA can handle the frame otherwise the frame is dropped */ -#ifdef CONFIG_STM32F7_ETH_HWCHECKSUM +#ifdef CONFIG_STM32_ETH_HWCHECKSUM # define DMAOMR_SET_MASK \ (ETH_DMAOMR_OSF | ETH_DMAOMR_RTC_64 | ETH_DMAOMR_TTC_64 | \ ETH_DMAOMR_TSF | ETH_DMAOMR_RSF) @@ -525,7 +525,7 @@ * ETH_DMABMR_DA DMA Arbitration 0 (round robin) * ETH_DMABMR_DSL Descriptor skip length 0 * ETH_DMABMR_EDFE Enhanced descriptor Depends on - * format enable CONFIG_STM32F7_ETH_ENHANCEDDESC + * format enable CONFIG_STM32_ETH_ENHANCEDDESC * ETH_DMABMR_PBL Programmable burst length 32 beats * ETH_DMABMR_RTPR RX TX priority ratio 2:1 * ETH_DMABMR_FB Fixed burst 1 (enabled) @@ -536,7 +536,7 @@ * ETH_DMABMR_MB Mixed burst 0 (disabled, F2/F4 only) */ -#ifdef CONFIG_STM32F7_ETH_ENHANCEDDESC +#ifdef CONFIG_STM32_ETH_ENHANCEDDESC # define DMABMR_SET_MASK \ (ETH_DMABMR_DSL(0) | ETH_DMABMR_PBL(32) | ETH_DMABMR_EDFE | ETH_DMABMR_RTPR_2TO1 | \ ETH_DMABMR_FB | ETH_DMABMR_RDP(32) | ETH_DMABMR_USP | ETH_DMABMR_AAB) @@ -659,7 +659,7 @@ static uint8_t g_txbuffer[TXBUFFER_ALLOC] /* These are the pre-allocated Ethernet device structures */ -static struct stm32_ethmac_s g_stm32ethmac[STM32F7_NETHERNET]; +static struct stm32_ethmac_s g_stm32ethmac[STM32_NETHERNET]; /**************************************************************************** * Private Function Prototypes @@ -667,7 +667,7 @@ static struct stm32_ethmac_s g_stm32ethmac[STM32F7_NETHERNET]; /* Register operations ******************************************************/ -#ifdef CONFIG_STM32F7_ETHMAC_REGDEBUG +#ifdef CONFIG_STM32_ETHMAC_REGDEBUG static uint32_t stm32_getreg(uint32_t addr); static void stm32_putreg(uint32_t val, uint32_t addr); static void stm32_checksetup(void); @@ -754,10 +754,10 @@ static int stm32_phyinit(struct stm32_ethmac_s *priv); /* MAC/DMA Initialization */ -#ifdef CONFIG_STM32F7_MII +#ifdef CONFIG_STM32_MII static inline void stm32_selectmii(void); #endif -#ifdef CONFIG_STM32F7_RMII +#ifdef CONFIG_STM32_RMII static inline void stm32_selectrmii(void); #endif static inline void stm32_ethgpioconfig(struct stm32_ethmac_s *priv); @@ -787,7 +787,7 @@ static int stm32_ethconfig(struct stm32_ethmac_s *priv); * ****************************************************************************/ -#ifdef CONFIG_STM32F7_ETHMAC_REGDEBUG +#ifdef CONFIG_STM32_ETHMAC_REGDEBUG static uint32_t stm32_getreg(uint32_t addr) { static uint32_t prevaddr = 0; @@ -859,7 +859,7 @@ static uint32_t stm32_getreg(uint32_t addr) * ****************************************************************************/ -#ifdef CONFIG_STM32F7_ETHMAC_REGDEBUG +#ifdef CONFIG_STM32_ETHMAC_REGDEBUG static void stm32_putreg(uint32_t val, uint32_t addr) { /* Show the register value being written */ @@ -886,7 +886,7 @@ static void stm32_putreg(uint32_t val, uint32_t addr) * ****************************************************************************/ -#ifdef CONFIG_STM32F7_ETHMAC_REGDEBUG +#ifdef CONFIG_STM32_ETHMAC_REGDEBUG static void stm32_checksetup(void) { } @@ -1210,7 +1210,7 @@ static int stm32_transmit(struct stm32_ethmac_s *priv) * un-stoppable transmit events. */ - if (priv->inflight >= CONFIG_STM32F7_ETH_NTXDESC) + if (priv->inflight >= CONFIG_STM32_ETH_NTXDESC) { stm32_disableint(priv, ETH_DMAINT_RI); } @@ -1284,7 +1284,7 @@ static int stm32_txpoll(struct net_driver_s *dev) * In a race condition, ETH_TDES0_OWN may be cleared BUT still * not available because stm32_freeframe() has not yet run. If * stm32_freeframe() has run, the buffer1 pointer (tdes2) will be - * nullified (and inflight should be < CONFIG_STM32F7_ETH_NTXDESC). + * nullified (and inflight should be < CONFIG_STM32_ETH_NTXDESC). */ if ((priv->txhead->tdes0 & ETH_TDES0_OWN) != 0 || @@ -1353,7 +1353,7 @@ static void stm32_dopoll(struct stm32_ethmac_s *priv) * In a race condition, ETH_TDES0_OWN may be cleared BUT still * not available because stm32_freeframe() has not yet run. If * stm32_freeframe() has run, the buffer1 pointer (tdes2) will be - * nullified (and inflight should be < CONFIG_STM32F7_ETH_NTXDESC). + * nullified (and inflight should be < CONFIG_STM32_ETH_NTXDESC). */ if ((priv->txhead->tdes0 & ETH_TDES0_OWN) == 0 && @@ -1582,8 +1582,8 @@ static int stm32_recvframe(struct stm32_ethmac_s *priv) for (i = 0; (rxdesc->rdes0 & ETH_RDES0_OWN) == 0 && - i < CONFIG_STM32F7_ETH_NRXDESC && - priv->inflight < CONFIG_STM32F7_ETH_NTXDESC; + i < CONFIG_STM32_ETH_NRXDESC && + priv->inflight < CONFIG_STM32_ETH_NTXDESC; i++) { /* Check if this is the first segment in the frame */ @@ -2657,7 +2657,7 @@ static void stm32_txdescinit(struct stm32_ethmac_s *priv, /* Initialize each TX descriptor */ - for (i = 0; i < CONFIG_STM32F7_ETH_NTXDESC; i++) + for (i = 0; i < CONFIG_STM32_ETH_NTXDESC; i++) { txdesc = &txtable[i].txdesc; @@ -2681,7 +2681,7 @@ static void stm32_txdescinit(struct stm32_ethmac_s *priv, * the Next Descriptor Polling Enable */ - if (i < (CONFIG_STM32F7_ETH_NTXDESC - 1)) + if (i < (CONFIG_STM32_ETH_NTXDESC - 1)) { /* Set next descriptor address register with next descriptor base * address @@ -2751,7 +2751,7 @@ static void stm32_rxdescinit(struct stm32_ethmac_s *priv, /* Initialize each RX descriptor */ - for (i = 0; i < CONFIG_STM32F7_ETH_NRXDESC; i++) + for (i = 0; i < CONFIG_STM32_ETH_NRXDESC; i++) { rxdesc = &rxtable[i].rxdesc; @@ -2773,7 +2773,7 @@ static void stm32_rxdescinit(struct stm32_ethmac_s *priv, * the Next Descriptor Polling Enable */ - if (i < (CONFIG_STM32F7_ETH_NRXDESC - 1)) + if (i < (CONFIG_STM32_ETH_NRXDESC - 1)) { /* Set next descriptor address register with next descriptor base * address @@ -2863,7 +2863,7 @@ static int stm32_ioctl(struct net_driver_s *dev, int cmd, unsigned long arg) { struct mii_ioctl_data_s *req = (struct mii_ioctl_data_s *)((uintptr_t)arg); - req->phy_id = CONFIG_STM32F7_PHYADDR; + req->phy_id = CONFIG_STM32_PHYADDR; ret = OK; } break; @@ -3070,7 +3070,7 @@ static inline int stm32_dm9161(struct stm32_ethmac_s *priv) * indication that check if the DM9161 PHY CHIP is not ready. */ - ret = stm32_phyread(CONFIG_STM32F7_PHYADDR, MII_PHYID1, &phyval); + ret = stm32_phyread(CONFIG_STM32_PHYADDR, MII_PHYID1, &phyval); if (ret < 0) { nerr("ERROR: Failed to read the PHY ID1: %d\n", ret); @@ -3090,7 +3090,7 @@ static inline int stm32_dm9161(struct stm32_ethmac_s *priv) /* Now check the "DAVICOM Specified Configuration Register (DSCR)"(16) */ - ret = stm32_phyread(CONFIG_STM32F7_PHYADDR, 16, &phyval); + ret = stm32_phyread(CONFIG_STM32_PHYADDR, 16, &phyval); if (ret < 0) { nerr("ERROR: Failed to read the PHY Register 0x10: %d\n", ret); @@ -3128,7 +3128,7 @@ static inline int stm32_dm9161(struct stm32_ethmac_s *priv) static int stm32_phyinit(struct stm32_ethmac_s *priv) { -#ifdef CONFIG_STM32F7_AUTONEG +#ifdef CONFIG_STM32_AUTONEG volatile uint32_t timeout; #endif uint32_t regval; @@ -3149,7 +3149,7 @@ static int stm32_phyinit(struct stm32_ethmac_s *priv) /* Put the PHY in reset mode */ - ret = stm32_phywrite(CONFIG_STM32F7_PHYADDR, MII_MCR, MII_MCR_RESET); + ret = stm32_phywrite(CONFIG_STM32_PHYADDR, MII_MCR, MII_MCR_RESET); if (ret < 0) { nerr("ERROR: Failed to reset the PHY: %d\n", ret); @@ -3160,7 +3160,7 @@ static int stm32_phyinit(struct stm32_ethmac_s *priv) /* Perform any necessary, board-specific PHY initialization */ -#ifdef CONFIG_STM32F7_PHYINIT +#ifdef CONFIG_STM32_PHYINIT ret = stm32_phy_boardinitialize(0); if (ret < 0) { @@ -3181,12 +3181,12 @@ static int stm32_phyinit(struct stm32_ethmac_s *priv) /* Perform auto-negotiation if so configured */ -#ifdef CONFIG_STM32F7_AUTONEG +#ifdef CONFIG_STM32_AUTONEG /* Wait for link status */ for (timeout = 0; timeout < PHY_RETRY_TIMEOUT; timeout++) { - ret = stm32_phyread(CONFIG_STM32F7_PHYADDR, MII_MSR, &phyval); + ret = stm32_phyread(CONFIG_STM32_PHYADDR, MII_MSR, &phyval); if (ret < 0) { nerr("ERROR: Failed to read the PHY MSR: %d\n", ret); @@ -3208,7 +3208,7 @@ static int stm32_phyinit(struct stm32_ethmac_s *priv) /* Enable auto-negotiation */ - ret = stm32_phywrite(CONFIG_STM32F7_PHYADDR, MII_MCR, MII_MCR_ANENABLE); + ret = stm32_phywrite(CONFIG_STM32_PHYADDR, MII_MCR, MII_MCR_ANENABLE); if (ret < 0) { nerr("ERROR: Failed to enable auto-negotiation: %d\n", ret); @@ -3219,7 +3219,7 @@ static int stm32_phyinit(struct stm32_ethmac_s *priv) for (timeout = 0; timeout < PHY_RETRY_TIMEOUT; timeout++) { - ret = stm32_phyread(CONFIG_STM32F7_PHYADDR, MII_MSR, &phyval); + ret = stm32_phyread(CONFIG_STM32_PHYADDR, MII_MSR, &phyval); if (ret < 0) { nerr("ERROR: Failed to read the PHY MSR: %d\n", ret); @@ -3241,7 +3241,7 @@ static int stm32_phyinit(struct stm32_ethmac_s *priv) /* Read the result of the auto-negotiation from the PHY-specific register */ - ret = stm32_phyread(CONFIG_STM32F7_PHYADDR, CONFIG_STM32F7_PHYSR, &phyval); + ret = stm32_phyread(CONFIG_STM32_PHYADDR, CONFIG_STM32_PHYSR, &phyval); if (ret < 0) { nerr("ERROR: Failed to read PHY status register\n"); @@ -3250,38 +3250,38 @@ static int stm32_phyinit(struct stm32_ethmac_s *priv) /* Remember the selected speed and duplex modes */ - ninfo("PHYSR[%d]: %04x\n", CONFIG_STM32F7_PHYSR, phyval); + ninfo("PHYSR[%d]: %04x\n", CONFIG_STM32_PHYSR, phyval); /* Different PHYs present speed and mode information in different ways. - * IF This CONFIG_STM32F7_PHYSR_ALTCONFIG is selected, this indicates that + * IF This CONFIG_STM32_PHYSR_ALTCONFIG is selected, this indicates that * the PHY represents speed and mode information are combined, for example, * with separate bits for 10HD, 100HD, 10FD and 100FD. */ -#ifdef CONFIG_STM32F7_PHYSR_ALTCONFIG - switch (phyval & CONFIG_STM32F7_PHYSR_ALTMODE) +#ifdef CONFIG_STM32_PHYSR_ALTCONFIG + switch (phyval & CONFIG_STM32_PHYSR_ALTMODE) { default: nerr("ERROR: Unrecognized PHY status setting\n"); /* Falls through */ - case CONFIG_STM32F7_PHYSR_10HD: + case CONFIG_STM32_PHYSR_10HD: priv->fduplex = 0; priv->mbps100 = 0; break; - case CONFIG_STM32F7_PHYSR_100HD: + case CONFIG_STM32_PHYSR_100HD: priv->fduplex = 0; priv->mbps100 = 1; break; - case CONFIG_STM32F7_PHYSR_10FD: + case CONFIG_STM32_PHYSR_10FD: priv->fduplex = 1; priv->mbps100 = 0; break; - case CONFIG_STM32F7_PHYSR_100FD: + case CONFIG_STM32_PHYSR_100FD: priv->fduplex = 1; priv->mbps100 = 1; break; @@ -3294,13 +3294,13 @@ static int stm32_phyinit(struct stm32_ethmac_s *priv) */ #else - if ((phyval & CONFIG_STM32F7_PHYSR_MODE) == - CONFIG_STM32F7_PHYSR_FULLDUPLEX) + if ((phyval & CONFIG_STM32_PHYSR_MODE) == + CONFIG_STM32_PHYSR_FULLDUPLEX) { priv->fduplex = 1; } - if ((phyval & CONFIG_STM32F7_PHYSR_SPEED) == CONFIG_STM32F7_PHYSR_100MBPS) + if ((phyval & CONFIG_STM32_PHYSR_SPEED) == CONFIG_STM32_PHYSR_100MBPS) { priv->mbps100 = 1; } @@ -3309,14 +3309,14 @@ static int stm32_phyinit(struct stm32_ethmac_s *priv) #else /* Auto-negotiation not selected */ phyval = 0; -#ifdef CONFIG_STM32F7_ETHFD +#ifdef CONFIG_STM32_ETHFD phyval |= MII_MCR_FULLDPLX; #endif -#ifdef CONFIG_STM32F7_ETH100MBPS +#ifdef CONFIG_STM32_ETH100MBPS phyval |= MII_MCR_SPEED100; #endif - ret = stm32_phywrite(CONFIG_STM32F7_PHYADDR, MII_MCR, phyval); + ret = stm32_phywrite(CONFIG_STM32_PHYADDR, MII_MCR, phyval); if (ret < 0) { nerr("ERROR: Failed to write the PHY MCR: %d\n", ret); @@ -3327,10 +3327,10 @@ static int stm32_phyinit(struct stm32_ethmac_s *priv) /* Remember the selected speed and duplex modes */ -#ifdef CONFIG_STM32F7_ETHFD +#ifdef CONFIG_STM32_ETHFD priv->fduplex = 1; #endif -#ifdef CONFIG_STM32F7_ETH100MBPS +#ifdef CONFIG_STM32_ETH100MBPS priv->mbps100 = 1; #endif #endif @@ -3356,7 +3356,7 @@ static int stm32_phyinit(struct stm32_ethmac_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32F7_MII +#ifdef CONFIG_STM32_MII static inline void stm32_selectmii(void) { uint32_t regval; @@ -3381,7 +3381,7 @@ static inline void stm32_selectmii(void) * ****************************************************************************/ -#ifdef CONFIG_STM32F7_RMII +#ifdef CONFIG_STM32_RMII static inline void stm32_selectrmii(void) { uint32_t regval; @@ -3412,7 +3412,7 @@ static inline void stm32_ethgpioconfig(struct stm32_ethmac_s *priv) { /* Configure GPIO pins to support Ethernet */ -#if defined(CONFIG_STM32F7_MII) || defined(CONFIG_STM32F7_RMII) +#if defined(CONFIG_STM32_MII) || defined(CONFIG_STM32_RMII) /* MDC and MDIO are common to both modes */ @@ -3421,7 +3421,7 @@ static inline void stm32_ethgpioconfig(struct stm32_ethmac_s *priv) /* Set up the MII interface */ -# if defined(CONFIG_STM32F7_MII) +# if defined(CONFIG_STM32_MII) /* Select the MII interface */ @@ -3436,7 +3436,7 @@ static inline void stm32_ethgpioconfig(struct stm32_ethmac_s *priv) * PLLI2S clock (through a configurable prescaler) on PC9 pin." */ -# if defined(CONFIG_STM32F7_MII_MCO1) +# if defined(CONFIG_STM32_MII_MCO1) /* Configure MC01 to drive the PHY. Board logic must provide MC01 clocking * info. */ @@ -3444,7 +3444,7 @@ static inline void stm32_ethgpioconfig(struct stm32_ethmac_s *priv) stm32_configgpio(GPIO_MCO1); stm32_mco1config(BOARD_CFGR_MC01_SOURCE, BOARD_CFGR_MC01_DIVIDER); -# elif defined(CONFIG_STM32F7_MII_MCO2) +# elif defined(CONFIG_STM32_MII_MCO2) /* Configure MC02 to drive the PHY. Board logic must provide MC02 clocking * info. */ @@ -3452,7 +3452,7 @@ static inline void stm32_ethgpioconfig(struct stm32_ethmac_s *priv) stm32_configgpio(GPIO_MCO2); stm32_mco2config(BOARD_CFGR_MC02_SOURCE, BOARD_CFGR_MC02_DIVIDER); -# elif defined(CONFIG_STM32F7_MII_MCO) +# elif defined(CONFIG_STM32_MII_MCO) /* Setup MCO pin for alternative usage */ stm32_configgpio(GPIO_MCO); @@ -3483,7 +3483,7 @@ static inline void stm32_ethgpioconfig(struct stm32_ethmac_s *priv) /* Set up the RMII interface. */ -# elif defined(CONFIG_STM32F7_RMII) +# elif defined(CONFIG_STM32_RMII) /* Select the RMII interface */ @@ -3498,7 +3498,7 @@ static inline void stm32_ethgpioconfig(struct stm32_ethmac_s *priv) * PLLI2S clock (through a configurable prescaler) on PC9 pin." */ -# if defined(CONFIG_STM32F7_RMII_MCO1) +# if defined(CONFIG_STM32_RMII_MCO1) /* Configure MC01 to drive the PHY. Board logic must provide MC01 clocking * info. */ @@ -3506,7 +3506,7 @@ static inline void stm32_ethgpioconfig(struct stm32_ethmac_s *priv) stm32_configgpio(GPIO_MCO1); stm32_mco1config(BOARD_CFGR_MC01_SOURCE, BOARD_CFGR_MC01_DIVIDER); -# elif defined(CONFIG_STM32F7_RMII_MCO2) +# elif defined(CONFIG_STM32_RMII_MCO2) /* Configure MC02 to drive the PHY. Board logic must provide MC02 clocking * info. */ @@ -3514,7 +3514,7 @@ static inline void stm32_ethgpioconfig(struct stm32_ethmac_s *priv) stm32_configgpio(GPIO_MCO2); stm32_mco2config(BOARD_CFGR_MC02_SOURCE, BOARD_CFGR_MC02_DIVIDER); -# elif defined(CONFIG_STM32F7_RMII_MCO) +# elif defined(CONFIG_STM32_RMII_MCO) /* Setup MCO pin for alternative usage */ stm32_configgpio(GPIO_MCO); @@ -3538,7 +3538,7 @@ static inline void stm32_ethgpioconfig(struct stm32_ethmac_s *priv) # endif #endif -#ifdef CONFIG_STM32F7_ETH_PTP +#ifdef CONFIG_STM32_ETH_PTP /* Enable pulse-per-second (PPS) output signal */ stm32_configgpio(GPIO_ETH_PPS_OUT); @@ -3861,12 +3861,12 @@ static int stm32_ethconfig(struct stm32_ethmac_s *priv) /* Initialize TX Descriptors list: Chain Mode */ stm32_txdescinit(priv, - &g_txtable[priv->intf * CONFIG_STM32F7_ETH_NTXDESC]); + &g_txtable[priv->intf * CONFIG_STM32_ETH_NTXDESC]); /* Initialize RX Descriptors list: Chain Mode */ stm32_rxdescinit(priv, - &g_rxtable[priv->intf * CONFIG_STM32F7_ETH_NRXDESC], + &g_rxtable[priv->intf * CONFIG_STM32_ETH_NRXDESC], &g_rxbuffer[priv->intf * RXBUFFER_SIZE]); /* Enable normal MAC operation */ @@ -3899,7 +3899,7 @@ static int stm32_ethconfig(struct stm32_ethmac_s *priv) * ****************************************************************************/ -#if STM32F7_NETHERNET == 1 || defined(CONFIG_NETDEV_LATEINIT) +#if STM32_NETHERNET == 1 || defined(CONFIG_NETDEV_LATEINIT) static inline #endif int stm32_ethinitialize(int intf) @@ -3912,7 +3912,7 @@ int stm32_ethinitialize(int intf) /* Get the interface structure associated with this interface number. */ - DEBUGASSERT(intf < STM32F7_NETHERNET); + DEBUGASSERT(intf < STM32_NETHERNET); priv = &g_stm32ethmac[intf]; /* Initialize the driver structure */ @@ -3973,7 +3973,7 @@ int stm32_ethinitialize(int intf) * * Description: * This is the "standard" network initialization logic called from the - * low-level initialization logic in arm_initialize.c. If STM32F7_NETHERNET + * low-level initialization logic in arm_initialize.c. If STM32_NETHERNET * greater than one, then board specific logic will have to supply a * version of arm_netinitialize() that calls stm32_ethinitialize() with * the appropriate interface number. @@ -3988,11 +3988,11 @@ int stm32_ethinitialize(int intf) * ****************************************************************************/ -#if STM32F7_NETHERNET == 1 && !defined(CONFIG_NETDEV_LATEINIT) +#if STM32_NETHERNET == 1 && !defined(CONFIG_NETDEV_LATEINIT) void arm_netinitialize(void) { stm32_ethinitialize(0); } #endif -#endif /* STM32F7_NETHERNET > 0 && CONFIG_STM32F7_ETHMAC */ +#endif /* STM32_NETHERNET > 0 && CONFIG_STM32_ETHMAC */ diff --git a/arch/arm/src/stm32f7/stm32_ethernet.h b/arch/arm/src/stm32f7/stm32_ethernet.h index 26d0e98ab891f..c23f2dcd21717 100644 --- a/arch/arm/src/stm32f7/stm32_ethernet.h +++ b/arch/arm/src/stm32f7/stm32_ethernet.h @@ -31,7 +31,7 @@ #include "hardware/stm32_ethernet.h" -#if STM32F7_NETHERNET > 0 +#if STM32_NETHERNET > 0 #ifndef __ASSEMBLY__ /**************************************************************************** @@ -67,7 +67,7 @@ extern "C" * ****************************************************************************/ -#if STM32F7_NETHERNET > 1 || defined(CONFIG_NETDEV_LATEINIT) +#if STM32_NETHERNET > 1 || defined(CONFIG_NETDEV_LATEINIT) int stm32_ethinitialize(int intf); #endif @@ -77,7 +77,7 @@ int stm32_ethinitialize(int intf); * Description: * Some boards require specialized initialization of the PHY before it can * be used. This may include such things as configuring GPIOs, resetting - * the PHY, etc. If CONFIG_STM32F7_PHYINIT is defined in the + * the PHY, etc. If CONFIG_STM32_PHYINIT is defined in the * configuration then the board specific logic must provide * stm32_phyinitialize(); The STM32 Ethernet driver will call this * function one time before it first uses the PHY. @@ -92,7 +92,7 @@ int stm32_ethinitialize(int intf); * ****************************************************************************/ -#ifdef CONFIG_STM32F7_PHYINIT +#ifdef CONFIG_STM32_PHYINIT int stm32_phy_boardinitialize(int intf); #endif @@ -102,5 +102,5 @@ int stm32_phy_boardinitialize(int intf); #endif #endif /* __ASSEMBLY__ */ -#endif /* STM32F7_NETHERNET > 0 */ +#endif /* STM32_NETHERNET > 0 */ #endif /* __ARCH_ARM_SRC_STM32F7_STM32_ETHERNET_H */ diff --git a/arch/arm/src/stm32f7/stm32_exti_gpio.c b/arch/arm/src/stm32f7/stm32_exti_gpio.c index 39f3c0a943d18..4081d9cba2404 100644 --- a/arch/arm/src/stm32f7/stm32_exti_gpio.c +++ b/arch/arm/src/stm32f7/stm32_exti_gpio.c @@ -44,9 +44,9 @@ * families */ -#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX) \ - || defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) \ - || defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) +#if defined(CONFIG_STM32_STM32F72XX) || defined(CONFIG_STM32_STM32F73XX) \ + || defined(CONFIG_STM32_STM32F74XX) || defined(CONFIG_STM32_STM32F75XX) \ + || defined(CONFIG_STM32_STM32F76XX) || defined(CONFIG_STM32_STM32F77XX) /**************************************************************************** * Private Types @@ -376,4 +376,4 @@ int stm32_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, return OK; } -#endif /* CONFIG_STM32F7_STM32F74XX || CONFIG_STM32F7_STM32F75XX */ +#endif /* CONFIG_STM32_STM32F74XX || CONFIG_STM32_STM32F75XX */ diff --git a/arch/arm/src/stm32f7/stm32_fmc.c b/arch/arm/src/stm32f7/stm32_fmc.c index 03eaea6826d45..d5e955133a487 100644 --- a/arch/arm/src/stm32f7/stm32_fmc.c +++ b/arch/arm/src/stm32f7/stm32_fmc.c @@ -26,7 +26,7 @@ #include -#if defined(CONFIG_STM32F7_FMC) +#if defined(CONFIG_STM32_FMC) #include #include @@ -234,4 +234,4 @@ void stm32_fmc_sdram_command(uint32_t cmd) putreg32(val, STM32_FMC_SDCMR); } -#endif /* CONFIG_STM32F7_FMC */ +#endif /* CONFIG_STM32_FMC */ diff --git a/arch/arm/src/stm32f7/stm32_foc.c b/arch/arm/src/stm32f7/stm32_foc.c index cddddee17d64d..9f51388aaee5b 100644 --- a/arch/arm/src/stm32f7/stm32_foc.c +++ b/arch/arm/src/stm32f7/stm32_foc.c @@ -78,7 +78,8 @@ * * Currently, up to two FOC instances are supported. * - * This implementation is based on arch/arm/src/stm32/stm32_foc.c + * This implementation is based on + * arch/arm/src/common/stm32/stm32_foc_m3m4_v1.c */ /* Verify system configuration **********************************************/ @@ -89,22 +90,22 @@ /* PWM lower-half ops and ADC lower-half ops must be enabled */ -#ifndef CONFIG_STM32F7_PWM_LL_OPS +#ifndef CONFIG_STM32_PWM_LL_OPS # error PWM low-level operations interface must be enabled #endif -#ifndef CONFIG_STM32F7_ADC_LL_OPS +#ifndef CONFIG_STM32_ADC_LL_OPS # error ADC low-level operations interface must be enabled #endif /* We don't want start conversion during ADC setup */ -#ifndef CONFIG_STM32F7_ADC_NO_STARTUP_CONV +#ifndef CONFIG_STM32_ADC_NO_STARTUP_CONV # error ADC startup conversion must be disabled #endif /* We need interface to change ADC sample-time */ -#ifndef CONFIG_STM32F7_ADC_CHANGE_SAMPLETIME +#ifndef CONFIG_STM32_ADC_CHANGE_SAMPLETIME # error ADC sample-time configuration interface must be enabled #endif @@ -114,35 +115,35 @@ /* FOC0 always use TIMER1 for PWM */ -#ifdef CONFIG_STM32F7_FOC_FOC0 +#ifdef CONFIG_STM32_FOC_FOC0 # define FOC0_PWM (1) # define FOC0_PWM_NCHANNELS (PWM_TIM1_NCHANNELS) # define FOC0_PWM_BASE (STM32_TIM1_BASE) # define FOC0_PWM_FZ_BIT (DBGMCU_APB2_TIM1STOP) -# if CONFIG_STM32F7_TIM1_MODE != 2 +# if CONFIG_STM32_TIM1_MODE != 2 # error TIM1 must be configured in center-aligned mode 1 # endif -#endif /* CONFIG_STM32F7_FOC_FOC0 */ +#endif /* CONFIG_STM32_FOC_FOC0 */ /* FOC1 always use TIMER8 for PWM */ -#ifdef CONFIG_STM32F7_FOC_FOC1 +#ifdef CONFIG_STM32_FOC_FOC1 # define FOC1_PWM (8) # define FOC1_PWM_NCHANNELS (PWM_TIM8_NCHANNELS) # define FOC1_PWM_BASE (STM32_TIM8_BASE) # define FOC1_PWM_FZ_BIT (DBGMCU_APB2_TIM8STOP) -# if CONFIG_STM32F7_TIM8_MODE != 2 +# if CONFIG_STM32_TIM8_MODE != 2 # error TIM8 must be configured in center-aligned mode 1 # endif #endif /* The maximum supported number of phases depends on the ADC trigger */ -#if defined(CONFIG_STM32F7_FOC_ADC_CCR4) +#if defined(CONFIG_STM32_FOC_ADC_CCR4) # if CONFIG_MOTOR_FOC_PHASES > 3 # error max 3 phases supported # endif -#elif defined(CONFIG_STM32F7_FOC_ADC_TRGO) +#elif defined(CONFIG_STM32_FOC_ADC_TRGO) # if CONFIG_MOTOR_FOC_PHASES > 4 # error max 4 phases supported # endif @@ -158,7 +159,7 @@ /* Only one ADC trigger must be selected */ -#if defined(CONFIG_STM32F7_FOC_ADC_CCR4) && defined(CONFIG_STM32F7_FOC_ADC_TRGO) +#if defined(CONFIG_STM32_FOC_ADC_CCR4) && defined(CONFIG_STM32_FOC_ADC_TRGO) # error Invalid ADC trigger configuration #endif @@ -174,7 +175,7 @@ * V0 for CNTR = 0 */ -#if defined(CONFIG_STM32F7_FOC_ADC_CCR4) +#if defined(CONFIG_STM32_FOC_ADC_CCR4) /* FOC ADC trigger on CCR4 **************************************************/ @@ -183,12 +184,12 @@ * - 1 channel for ADC injection sequence trigger (CCR4) */ -# if defined(CONFIG_STM32F7_FOC_FOC0) +# if defined(CONFIG_STM32_FOC_FOC0) # if FOC0_PWM_NCHANNELS != (CONFIG_MOTOR_FOC_PHASES + 1) # error Invalid channels configuration # endif # endif -# if defined(CONFIG_STM32F7_FOC_FOC1) +# if defined(CONFIG_STM32_FOC_FOC1) # if FOC1_PWM_NCHANNELS != (CONFIG_MOTOR_FOC_PHASES + 1) # error Invalid channels configuration # endif @@ -202,10 +203,10 @@ * TIMx CCR4 = (ARR - trigger_offset) */ -#ifdef CONFIG_STM32F7_FOC_USE_TIM1 +#ifdef CONFIG_STM32_FOC_USE_TIM1 # define ADC_JEXTSEL_T1CC4 (ADC_CR2_JEXTSEL_T1CC4) #endif -#ifdef CONFIG_STM32F7_FOC_USE_TIM8 +#ifdef CONFIG_STM32_FOC_USE_TIM8 # define ADC_JEXTSEL_T8CC4 (ADC_CR2_JEXTSEL_T8CC4) #endif @@ -213,20 +214,20 @@ # define ADC_TRIGGER_OFFSET (1) -# ifdef CONFIG_STM32F7_FOC_FOC0 +# ifdef CONFIG_STM32_FOC_FOC0 # define FOC0_ADC_JEXTSEL (ADC_JEXTSEL_T1CC4) # endif -# ifdef CONFIG_STM32F7_FOC_FOC1 +# ifdef CONFIG_STM32_FOC_FOC1 # define FOC1_ADC_JEXTSEL (ADC_JEXTSEL_T8CC4) # endif -#elif defined(CONFIG_STM32F7_FOC_ADC_TRGO) +#elif defined(CONFIG_STM32_FOC_ADC_TRGO) /* FOC ADC trigger on TRGO **************************************************/ /* PWM TRGO support must be enabled */ -# ifndef CONFIG_STM32F7_PWM_TRGO +# ifndef CONFIG_STM32_PWM_TRGO # error PWM TRGO support must be enabled # endif @@ -238,12 +239,12 @@ * - n channels for phases PWM (CCR1, CCR2, CCR3, CCR4) */ -# if defined(CONFIG_STM32F7_FOC_FOC0) +# if defined(CONFIG_STM32_FOC_FOC0) # if FOC0_PWM_NCHANNELS != (CONFIG_MOTOR_FOC_PHASES) # error Invalid channels configuration # endif # endif -# if defined(CONFIG_STM32F7_FOC_FOC1) +# if defined(CONFIG_STM32_FOC_FOC1) # if FOC1_PWM_NCHANNELS != (CONFIG_MOTOR_FOC_PHASES) # error Invalid channels configuration # endif @@ -257,17 +258,17 @@ * TIMx TRGO = (ARR) */ -#ifdef CONFIG_STM32F7_FOC_USE_TIM1 +#ifdef CONFIG_STM32_FOC_USE_TIM1 # define ADC_JEXTSEL_T1TRGO (ADC_CR2_JEXTSEL_T1TRGO) #endif -#ifdef CONFIG_STM32F7_FOC_USE_TIM8 +#ifdef CONFIG_STM32_FOC_USE_TIM8 # error TIM8 and TRGO trigger not supported for ADC IPv1 #endif -# ifdef CONFIG_STM32F7_FOC_FOC0 +# ifdef CONFIG_STM32_FOC_FOC0 # define FOC0_ADC_JEXTSEL (ADC_JEXTSEL_T1TRGO) # endif -# ifdef CONFIG_STM32F7_FOC_FOC1 +# ifdef CONFIG_STM32_FOC_FOC1 # define FOC1_ADC_JEXTSEL (ADC_JEXTSEL_T8TRGO) # endif @@ -280,28 +281,28 @@ /* Phase current samples for FOC0 */ -#ifdef CONFIG_STM32F7_FOC_FOC0 -# ifdef CONFIG_STM32F7_FOC_FOC0_ADC1 +#ifdef CONFIG_STM32_FOC_FOC0 +# ifdef CONFIG_STM32_FOC_FOC0_ADC1 # define FOC0_ADC 1 # endif -# ifdef CONFIG_STM32F7_FOC_FOC0_ADC2 +# ifdef CONFIG_STM32_FOC_FOC0_ADC2 # define FOC0_ADC 2 # endif -# ifdef CONFIG_STM32F7_FOC_FOC0_ADC3 +# ifdef CONFIG_STM32_FOC_FOC0_ADC3 # define FOC0_ADC 3 # endif #endif /* Phase current samples for FOC1 */ -#ifdef CONFIG_STM32F7_FOC_FOC1 -# ifdef CONFIG_STM32F7_FOC_FOC1_ADC1 +#ifdef CONFIG_STM32_FOC_FOC1 +# ifdef CONFIG_STM32_FOC_FOC1_ADC1 # define FOC1_ADC 1 # endif -# ifdef CONFIG_STM32F7_FOC_FOC1_ADC2 +# ifdef CONFIG_STM32_FOC_FOC1_ADC2 # define FOC1_ADC 2 # endif -# ifdef CONFIG_STM32F7_FOC_FOC1_ADC3 +# ifdef CONFIG_STM32_FOC_FOC1_ADC3 # define FOC1_ADC 3 # endif #endif @@ -316,55 +317,55 @@ * 3. ADC software trigger starts only regular conversion. */ -#ifdef CONFIG_STM32F7_FOC_USE_ADC1 -# ifndef CONFIG_STM32F7_ADC1 +#ifdef CONFIG_STM32_FOC_USE_ADC1 +# ifndef CONFIG_STM32_ADC1 # error ADC1 not supported ! # endif # ifndef ADC1_HAVE_JEXTCFG # error ADC1 must support JEXTCFG # endif -# if CONFIG_STM32F7_ADC1_ANIOC_TRIGGER != 1 -# error CONFIG_STM32F7_ADC1_ANIOC_TRIGGER must be 1 +# if CONFIG_STM32_ADC1_ANIOC_TRIGGER != 1 +# error CONFIG_STM32_ADC1_ANIOC_TRIGGER must be 1 # endif -# if CONFIG_STM32F7_ADC1_INJECTED_CHAN != FOC_ADC_INJ_CHAN_REQUIRED +# if CONFIG_STM32_ADC1_INJECTED_CHAN != FOC_ADC_INJ_CHAN_REQUIRED # error Invalid configuration for ADC1 injected channels # endif #endif -#ifdef CONFIG_STM32F7_FOC_USE_ADC2 -# ifndef CONFIG_STM32F7_ADC2 +#ifdef CONFIG_STM32_FOC_USE_ADC2 +# ifndef CONFIG_STM32_ADC2 # error ADC2 not supported ! # endif # ifndef ADC2_HAVE_JEXTCFG # error ADC2 must support JEXTCFG # endif -# if CONFIG_STM32F7_ADC2_ANIOC_TRIGGER != 1 -# error CONFIG_STM32F7_ADC2_ANIOC_TRIGGER must be 1 +# if CONFIG_STM32_ADC2_ANIOC_TRIGGER != 1 +# error CONFIG_STM32_ADC2_ANIOC_TRIGGER must be 1 # endif -# if CONFIG_STM32F7_ADC2_INJECTED_CHAN != FOC_ADC_INJ_CHAN_REQUIRED +# if CONFIG_STM32_ADC2_INJECTED_CHAN != FOC_ADC_INJ_CHAN_REQUIRED # error Invalid configuration for ADC2 injected channels # endif #endif -#ifdef CONFIG_STM32F7_FOC_USE_ADC3 -# ifndef CONFIG_STM32F7_ADC3 +#ifdef CONFIG_STM32_FOC_USE_ADC3 +# ifndef CONFIG_STM32_ADC3 # error ADC3 not supported ! # endif # ifndef ADC3_HAVE_JEXTCFG # error ADC3 must support JEXTCFG # endif -# if CONFIG_STM32F7_ADC3_ANIOC_TRIGGER != 1 -# error CONFIG_STM32F7_ADC3_ANIOC_TRIGGER must be 1 +# if CONFIG_STM32_ADC3_ANIOC_TRIGGER != 1 +# error CONFIG_STM32_ADC3_ANIOC_TRIGGER must be 1 # endif -# if CONFIG_STM32F7_ADC3_INJECTED_CHAN != FOC_ADC_INJ_CHAN_REQUIRED +# if CONFIG_STM32_ADC3_INJECTED_CHAN != FOC_ADC_INJ_CHAN_REQUIRED # error Invalid configuration for ADC3 injected channels # endif #endif /* Combine JEXTSEL with JEXTEN default */ -#ifdef CONFIG_STM32F7_FOC_FOC0 +#ifdef CONFIG_STM32_FOC_FOC0 # define FOC0_ADC_JEXT (ADC_JEXTREG_JEXTEN_DEFAULT | FOC0_ADC_JEXTSEL) #endif -#ifdef CONFIG_STM32F7_FOC_FOC1 +#ifdef CONFIG_STM32_FOC_FOC1 # define FOC1_ADC_JEXT (ADC_JEXTREG_JEXTEN_DEFAULT | FOC1_ADC_JEXTSEL) #endif @@ -376,9 +377,9 @@ /* ADC1 + ADC2 + ADC3 interrupt */ -#define STM32F7_IRQ_ADC1_FOC STM32_IRQ_ADC -#define STM32F7_IRQ_ADC2_FOC STM32_IRQ_ADC -#define STM32F7_IRQ_ADC3_FOC STM32_IRQ_ADC +#define STM32_IRQ_ADC1_FOC STM32_IRQ_ADC +#define STM32_IRQ_ADC2_FOC STM32_IRQ_ADC +#define STM32_IRQ_ADC3_FOC STM32_IRQ_ADC /* ADC common ***************************************************************/ @@ -390,40 +391,40 @@ /* FOC ADC configuration ****************************************************/ -#ifdef CONFIG_STM32F7_FOC_FOC0 -# ifdef CONFIG_STM32F7_FOC_FOC0_ADC1 -# define FOC0_ADC_IRQ STM32F7_IRQ_ADC1_FOC +#ifdef CONFIG_STM32_FOC_FOC0 +# ifdef CONFIG_STM32_FOC_FOC0_ADC1 +# define FOC0_ADC_IRQ STM32_IRQ_ADC1_FOC # define FOC0_ADC_CMN FOC_ADC1_CMN # endif -# ifdef CONFIG_STM32F7_FOC_FOC0_ADC2 -# define FOC0_ADC_IRQ STM32F7_IRQ_ADC2_FOC +# ifdef CONFIG_STM32_FOC_FOC0_ADC2 +# define FOC0_ADC_IRQ STM32_IRQ_ADC2_FOC # define FOC0_ADC_CMN FOC_ADC2_CMN # endif -# ifdef CONFIG_STM32F7_FOC_FOC0_ADC3 -# define FOC0_ADC_IRQ STM32F7_IRQ_ADC3_FOC +# ifdef CONFIG_STM32_FOC_FOC0_ADC3 +# define FOC0_ADC_IRQ STM32_IRQ_ADC3_FOC # define FOC0_ADC_CMN FOC_ADC3_CMN # endif -# ifdef CONFIG_STM32F7_FOC_FOC0_ADC4 -# define FOC0_ADC_IRQ STM32F7_IRQ_ADC4_FOC +# ifdef CONFIG_STM32_FOC_FOC0_ADC4 +# define FOC0_ADC_IRQ STM32_IRQ_ADC4_FOC # define FOC0_ADC_CMN FOC_ADC4_CMN # endif #endif -#ifdef CONFIG_STM32F7_FOC_FOC1 -# ifdef CONFIG_STM32F7_FOC_FOC1_ADC1 -# define FOC1_ADC_IRQ STM32F7_IRQ_ADC1_FOC +#ifdef CONFIG_STM32_FOC_FOC1 +# ifdef CONFIG_STM32_FOC_FOC1_ADC1 +# define FOC1_ADC_IRQ STM32_IRQ_ADC1_FOC # define FOC1_ADC_CMN FOC_ADC1_CMN # endif -# ifdef CONFIG_STM32F7_FOC_FOC1_ADC2 -# define FOC1_ADC_IRQ STM32F7_IRQ_ADC2_FOC +# ifdef CONFIG_STM32_FOC_FOC1_ADC2 +# define FOC1_ADC_IRQ STM32_IRQ_ADC2_FOC # define FOC1_ADC_CMN FOC_ADC2_CMN # endif -# ifdef CONFIG_STM32F7_FOC_FOC1_ADC3 -# define FOC1_ADC_IRQ STM32F7_IRQ_ADC3_FOC +# ifdef CONFIG_STM32_FOC_FOC1_ADC3 +# define FOC1_ADC_IRQ STM32_IRQ_ADC3_FOC # define FOC1_ADC_CMN FOC_ADC3_CMN # endif -# ifdef CONFIG_STM32F7_FOC_FOC1_ADC4 -# define FOC1_ADC_IRQ STM32F7_IRQ_ADC4_FOC +# ifdef CONFIG_STM32_FOC_FOC1_ADC4 +# define FOC1_ADC_IRQ STM32_IRQ_ADC4_FOC # define FOC1_ADC_CMN FOC_ADC4_CMN # endif #endif @@ -502,7 +503,7 @@ /* Define PWM all outputs */ -#ifdef CONFIG_STM32F7_FOC_HAS_PWM_COMPLEMENTARY +#ifdef CONFIG_STM32_FOC_HAS_PWM_COMPLEMENTARY # define PMW_OUTPUTS_ALL_COMP (STM32_PWM_OUT1N| \ STM32_PWM_OUT2N| \ STM32_PWM_OUT3N) @@ -510,7 +511,7 @@ # define PMW_OUTPUTS_ALL_COMP (0) #endif -#if defined(CONFIG_STM32F7_FOC_ADC_CCR4) || (CONFIG_MOTOR_FOC_PHASES > 3) +#if defined(CONFIG_STM32_FOC_ADC_CCR4) || (CONFIG_MOTOR_FOC_PHASES > 3) # define PMW_OUTPUTS_ALL_OUT4 (STM32_PWM_OUT4) #else # define PMW_OUTPUTS_ALL_OUT4 (0) @@ -683,10 +684,10 @@ static int stm32_foc_adc_start(struct foc_dev_s *dev, bool state); static int stm32_foc_calibration_start(struct foc_dev_s *dev); static int stm32_foc_pwm_freq_set(struct foc_dev_s *dev, uint32_t freq); -#if defined(CONFIG_STM32F7_FOC_ADC_CCR4) +#if defined(CONFIG_STM32_FOC_ADC_CCR4) static void stm32_foc_adc_ccr4_trg_set(struct foc_dev_s *dev, uint32_t offset); -#elif defined(CONFIG_STM32F7_FOC_ADC_TRGO) +#elif defined(CONFIG_STM32_FOC_ADC_TRGO) static void stm32_foc_adc_trgo_trg_set(struct foc_dev_s *dev, uint8_t rcr); #else @@ -772,7 +773,7 @@ void stm32_foc_sync_all(void) /* Store EGR register address */ - egr_reg[i] = foc_dev->pwm_base + STM32F7_GTIM_EGR_OFFSET; + egr_reg[i] = foc_dev->pwm_base + STM32_GTIM_EGR_OFFSET; } /* Write all registers at once */ @@ -813,7 +814,7 @@ static int stm32_foc_pwm_cfg(struct foc_dev_s *dev, uint32_t freq) goto errout; } -#ifdef CONFIG_STM32F7_FOC_HAS_PWM_COMPLEMENTARY +#ifdef CONFIG_STM32_FOC_HAS_PWM_COMPLEMENTARY /* Configure deadtime */ PWM_DT_UPDATE(pwm, (uint8_t)board->data->pwm_dt); @@ -1015,7 +1016,7 @@ static int stm32_foc_adc_cfg(struct foc_dev_s *dev) return OK; } -#if defined(CONFIG_STM32F7_FOC_ADC_CCR4) +#if defined(CONFIG_STM32_FOC_ADC_CCR4) /**************************************************************************** * Name: stm32_foc_adc_ccr4_trg_set @@ -1047,7 +1048,7 @@ static void stm32_foc_adc_ccr4_trg_set(struct foc_dev_s *dev, PWM_CCR_UPDATE(pwm, STM32_PWM_CHAN4, offset); } -#elif defined(CONFIG_STM32F7_FOC_ADC_TRGO) +#elif defined(CONFIG_STM32_FOC_ADC_TRGO) /**************************************************************************** * Name: stm32_foc_adc_trgo_trg_set @@ -1140,9 +1141,9 @@ static int stm32_foc_configure(struct foc_dev_s *dev, DEBUGASSERT(priv->data.per != 0); -#if defined(CONFIG_STM32F7_FOC_ADC_CCR4) +#if defined(CONFIG_STM32_FOC_ADC_CCR4) stm32_foc_adc_ccr4_trg_set(dev, (priv->data.per - ADC_TRIGGER_OFFSET)); -#elif defined(CONFIG_STM32F7_FOC_ADC_TRGO) +#elif defined(CONFIG_STM32_FOC_ADC_TRGO) stm32_foc_adc_trgo_trg_set(dev, (dev->cfg.pwm_freq / priv->data.adc_freq) * 2); #else @@ -1156,7 +1157,7 @@ static int stm32_foc_configure(struct foc_dev_s *dev, /* REVISIT: synchronise instances if TRGO trigger selected */ #if (CONFIG_MOTOR_FOC_INST > 1) -# if defined(CONFIG_STM32F7_FOC_ADC_TRGO) +# if defined(CONFIG_STM32_FOC_ADC_TRGO) # error stm32_foc_sync_all breaks TRGO event on V0 vector # endif @@ -1704,9 +1705,9 @@ static int stm32_foc_calibration_start(struct foc_dev_s *dev) DEBUGASSERT(priv->data.per != 0); -#if defined(CONFIG_STM32F7_FOC_ADC_CCR4) +#if defined(CONFIG_STM32_FOC_ADC_CCR4) stm32_foc_adc_ccr4_trg_set(dev, (priv->data.per - ADC_TRIGGER_OFFSET)); -#elif defined(CONFIG_STM32F7_FOC_ADC_TRGO) +#elif defined(CONFIG_STM32_FOC_ADC_TRGO) stm32_foc_adc_trgo_trg_set(dev, 1); #else # error Invalid FOC ADC trigger @@ -2039,7 +2040,7 @@ static int stm32_foc_notifier_cfg(struct foc_dev_s *dev, uint32_t freq) goto errout; } -#if defined(CONFIG_STM32F7_FOC_ADC_CCR4) +#if defined(CONFIG_STM32_FOC_ADC_CCR4) /* ADC interrupts frequency is PWM frequency */ priv->data.adc_freq = dev->cfg.pwm_freq; @@ -2048,7 +2049,7 @@ static int stm32_foc_notifier_cfg(struct foc_dev_s *dev, uint32_t freq) priv->data.notifier_div = (dev->cfg.pwm_freq / freq); -#elif defined(CONFIG_STM32F7_FOC_ADC_TRGO) +#elif defined(CONFIG_STM32_FOC_ADC_TRGO) /* Call work on every ADC interrupt */ priv->data.notifier_div = 1; @@ -2250,7 +2251,7 @@ stm32_foc_initialize(int inst, struct stm32_foc_board_s *board) switch (inst) { -#ifdef CONFIG_STM32F7_FOC_FOC0 +#ifdef CONFIG_STM32_FOC_FOC0 case 0: { pwm_inst = FOC0_PWM; @@ -2264,7 +2265,7 @@ stm32_foc_initialize(int inst, struct stm32_foc_board_s *board) } #endif -#ifdef CONFIG_STM32F7_FOC_FOC1 +#ifdef CONFIG_STM32_FOC_FOC1 case 1: { pwm_inst = FOC1_PWM; diff --git a/arch/arm/src/stm32f7/stm32_gpio.c b/arch/arm/src/stm32f7/stm32_gpio.c index 0033faf47da72..611cf9987fda5 100644 --- a/arch/arm/src/stm32f7/stm32_gpio.c +++ b/arch/arm/src/stm32f7/stm32_gpio.c @@ -44,9 +44,9 @@ * families */ -#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX) \ - || defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) \ - || defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) +#if defined(CONFIG_STM32_STM32F72XX) || defined(CONFIG_STM32_STM32F73XX) \ + || defined(CONFIG_STM32_STM32F74XX) || defined(CONFIG_STM32_STM32F75XX) \ + || defined(CONFIG_STM32_STM32F76XX) || defined(CONFIG_STM32_STM32F77XX) /**************************************************************************** * Private Data @@ -60,39 +60,39 @@ static spinlock_t g_configgpio_lock = SP_UNLOCKED; /* Base addresses for each GPIO block */ -const uint32_t g_gpiobase[STM32F7_NGPIO] = +const uint32_t g_gpiobase[STM32_NGPIO] = { -#if STM32F7_NGPIO > 0 +#if STM32_NGPIO > 0 STM32_GPIOA_BASE, #endif -#if STM32F7_NGPIO > 1 +#if STM32_NGPIO > 1 STM32_GPIOB_BASE, #endif -#if STM32F7_NGPIO > 2 +#if STM32_NGPIO > 2 STM32_GPIOC_BASE, #endif -#if STM32F7_NGPIO > 3 +#if STM32_NGPIO > 3 STM32_GPIOD_BASE, #endif -#if STM32F7_NGPIO > 4 +#if STM32_NGPIO > 4 STM32_GPIOE_BASE, #endif -#if STM32F7_NGPIO > 5 +#if STM32_NGPIO > 5 STM32_GPIOF_BASE, #endif -#if STM32F7_NGPIO > 6 +#if STM32_NGPIO > 6 STM32_GPIOG_BASE, #endif -#if STM32F7_NGPIO > 7 +#if STM32_NGPIO > 7 STM32_GPIOH_BASE, #endif -#if STM32F7_NGPIO > 8 +#if STM32_NGPIO > 8 STM32_GPIOI_BASE, #endif -#if STM32F7_NGPIO > 9 +#if STM32_NGPIO > 9 STM32_GPIOJ_BASE, #endif -#if STM32F7_NGPIO > 10 +#if STM32_NGPIO > 10 STM32_GPIOK_BASE, #endif }; @@ -134,7 +134,7 @@ int stm32_configgpio(uint32_t cfgset) /* Verify that this hardware supports the select GPIO port */ port = (cfgset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; - if (port >= STM32F7_NGPIO) + if (port >= STM32_NGPIO) { return -EINVAL; } @@ -409,7 +409,7 @@ void stm32_gpiowrite(uint32_t pinset, bool value) unsigned int pin; port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; - if (port < STM32F7_NGPIO) + if (port < STM32_NGPIO) { /* Get the port base address */ @@ -449,7 +449,7 @@ bool stm32_gpioread(uint32_t pinset) unsigned int pin; port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; - if (port < STM32F7_NGPIO) + if (port < STM32_NGPIO) { /* Get the port base address */ @@ -502,4 +502,4 @@ void stm32_iocompensation(void) } } -#endif /* CONFIG_STM32F7_STM32F72XX || ... || CONFIG_STM32F7_STM32F77XX */ +#endif /* CONFIG_STM32_STM32F72XX || ... || CONFIG_STM32_STM32F77XX */ diff --git a/arch/arm/src/stm32f7/stm32_gpio.h b/arch/arm/src/stm32f7/stm32_gpio.h index 00fee28b71a14..97fcbc8dfafef 100644 --- a/arch/arm/src/stm32f7/stm32_gpio.h +++ b/arch/arm/src/stm32f7/stm32_gpio.h @@ -240,7 +240,7 @@ extern "C" /* Base addresses for each GPIO block */ -EXTERN const uint32_t g_gpiobase[STM32F7_NGPIO]; +EXTERN const uint32_t g_gpiobase[STM32_NGPIO]; /**************************************************************************** * Public Function Prototypes diff --git a/arch/arm/src/stm32f7/stm32_i2c.c b/arch/arm/src/stm32f7/stm32_i2c.c index e805129f8e877..4c3dc112a8b1b 100644 --- a/arch/arm/src/stm32f7/stm32_i2c.c +++ b/arch/arm/src/stm32f7/stm32_i2c.c @@ -155,34 +155,34 @@ * * One of: * - * CONFIG_STM32F7_STM32F72XX - * CONFIG_STM32F7_STM32F73XX - * CONFIG_STM32F7_STM32F74XX - * CONFIG_STM32F7_STM32F75XX - * CONFIG_STM32F7_STM32F76XX - * CONFIG_STM32F7_STM32F77XX + * CONFIG_STM32_STM32F72XX + * CONFIG_STM32_STM32F73XX + * CONFIG_STM32_STM32F74XX + * CONFIG_STM32_STM32F75XX + * CONFIG_STM32_STM32F76XX + * CONFIG_STM32_STM32F77XX * * * and one or more interfaces: * - * CONFIG_STM32F7_I2C1 - * CONFIG_STM32F7_I2C2 - * CONFIG_STM32F7_I2C3 - * CONFIG_STM32F7_I2C4 + * CONFIG_STM32_I2C1 + * CONFIG_STM32_I2C2 + * CONFIG_STM32_I2C3 + * CONFIG_STM32_I2C4 * * To configure the ISR timeout using fixed values - * (CONFIG_STM32F7_I2C_DYNTIMEO=n): + * (CONFIG_STM32_I2C_DYNTIMEO=n): * - * CONFIG_STM32F7_I2CTIMEOSEC (Timeout in seconds) - * CONFIG_STM32F7_I2CTIMEOMS (Timeout in milliseconds) - * CONFIG_STM32F7_I2CTIMEOTICKS (Timeout in ticks) + * CONFIG_STM32_I2CTIMEOSEC (Timeout in seconds) + * CONFIG_STM32_I2CTIMEOMS (Timeout in milliseconds) + * CONFIG_STM32_I2CTIMEOTICKS (Timeout in ticks) * * To configure the ISR timeout using dynamic values - * (CONFIG_STM32F7_I2C_DYNTIMEO=y): + * (CONFIG_STM32_I2C_DYNTIMEO=y): * - * CONFIG_STM32F7_I2C_DYNTIMEO_USECPERBYTE + * CONFIG_STM32_I2C_DYNTIMEO_USECPERBYTE * (Timeout in microseconds per byte) - * CONFIG_STM32F7_I2C_DYNTIMEO_STARTSTOP + * CONFIG_STM32_I2C_DYNTIMEO_STARTSTOP * (Timeout for start/stop in milliseconds) * * Debugging output enabled with: @@ -256,8 +256,8 @@ /* At least one I2C peripheral must be enabled */ -#if defined(CONFIG_STM32F7_I2C1) || defined(CONFIG_STM32F7_I2C2) || \ - defined(CONFIG_STM32F7_I2C3) || defined(CONFIG_STM32F7_I2C4) +#if defined(CONFIG_STM32_I2C1) || defined(CONFIG_STM32_I2C2) || \ + defined(CONFIG_STM32_I2C3) || defined(CONFIG_STM32_I2C4) /**************************************************************************** * Pre-processor Definitions @@ -265,25 +265,25 @@ #undef INVALID_CLOCK_SOURCE -#ifdef CONFIG_STM32F7_I2C1 +#ifdef CONFIG_STM32_I2C1 # if STM32_RCC_DCKCFGR2_I2C1SRC != RCC_DCKCFGR2_I2C1SEL_HSI # warning "Clock Source STM32_RCC_DCKCFGR2_I2C1SRC must be HSI" # define INVALID_CLOCK_SOURCE # endif #endif -#ifdef CONFIG_STM32F7_I2C2 +#ifdef CONFIG_STM32_I2C2 # if STM32_RCC_DCKCFGR2_I2C2SRC != RCC_DCKCFGR2_I2C2SEL_HSI # warning "Clock Source STM32_RCC_DCKCFGR2_I2C2SRC must be HSI" # define INVALID_CLOCK_SOURCE # endif #endif -#ifdef CONFIG_STM32F7_I2C3 +#ifdef CONFIG_STM32_I2C3 # if STM32_RCC_DCKCFGR2_I2C3SRC != RCC_DCKCFGR2_I2C3SEL_HSI # warning "Clock Source STM32_RCC_DCKCFGR2_I2C3SRC must be HSI" # define INVALID_CLOCK_SOURCE # endif #endif -#ifdef CONFIG_STM32F7_I2C4 +#ifdef CONFIG_STM32_I2C4 # if STM32_RCC_DCKCFGR2_I2C4SRC != RCC_DCKCFGR2_I2C4SEL_HSI # warning "Clock Source STM32_RCC_DCKCFGR2_I2C4SRC must be HSI" # define INVALID_CLOCK_SOURCE @@ -300,25 +300,25 @@ /* Interrupt wait timeout in seconds and milliseconds */ -#if !defined(CONFIG_STM32F7_I2CTIMEOSEC) && !defined(CONFIG_STM32F7_I2CTIMEOMS) -# define CONFIG_STM32F7_I2CTIMEOSEC 0 -# define CONFIG_STM32F7_I2CTIMEOMS 500 /* Default is 500 milliseconds */ +#if !defined(CONFIG_STM32_I2CTIMEOSEC) && !defined(CONFIG_STM32_I2CTIMEOMS) +# define CONFIG_STM32_I2CTIMEOSEC 0 +# define CONFIG_STM32_I2CTIMEOMS 500 /* Default is 500 milliseconds */ # warning "Using Default 500 Ms Timeout" -#elif !defined(CONFIG_STM32F7_I2CTIMEOSEC) -# define CONFIG_STM32F7_I2CTIMEOSEC 0 /* User provided milliseconds */ -#elif !defined(CONFIG_STM32F7_I2CTIMEOMS) -# define CONFIG_STM32F7_I2CTIMEOMS 0 /* User provided seconds */ +#elif !defined(CONFIG_STM32_I2CTIMEOSEC) +# define CONFIG_STM32_I2CTIMEOSEC 0 /* User provided milliseconds */ +#elif !defined(CONFIG_STM32_I2CTIMEOMS) +# define CONFIG_STM32_I2CTIMEOMS 0 /* User provided seconds */ #endif /* Interrupt wait time timeout in system timer ticks */ -#ifndef CONFIG_STM32F7_I2CTIMEOTICKS -# define CONFIG_STM32F7_I2CTIMEOTICKS \ - (SEC2TICK(CONFIG_STM32F7_I2CTIMEOSEC) + MSEC2TICK(CONFIG_STM32F7_I2CTIMEOMS)) +#ifndef CONFIG_STM32_I2CTIMEOTICKS +# define CONFIG_STM32_I2CTIMEOTICKS \ + (SEC2TICK(CONFIG_STM32_I2CTIMEOSEC) + MSEC2TICK(CONFIG_STM32_I2CTIMEOMS)) #endif -#ifndef CONFIG_STM32F7_I2C_DYNTIMEO_STARTSTOP -# define CONFIG_STM32F7_I2C_DYNTIMEO_STARTSTOP TICK2USEC(CONFIG_STM32F7_I2CTIMEOTICKS) +#ifndef CONFIG_STM32_I2C_DYNTIMEO_STARTSTOP +# define CONFIG_STM32_I2C_DYNTIMEO_STARTSTOP TICK2USEC(CONFIG_STM32_I2CTIMEOTICKS) #endif /* Macros to convert a I2C pin to a GPIO output */ @@ -482,9 +482,9 @@ static inline void stm32_i2c_putreg32(struct stm32_i2c_priv_s *priv, static inline void stm32_i2c_modifyreg32(struct stm32_i2c_priv_s *priv, uint8_t offset, uint32_t clearbits, uint32_t setbits); -#ifdef CONFIG_STM32F7_I2C_DYNTIMEO +#ifdef CONFIG_STM32_I2C_DYNTIMEO static uint32_t stm32_i2c_toticks(int msgc, struct i2c_msg_s *msgs); -#endif /* CONFIG_STM32F7_I2C_DYNTIMEO */ +#endif /* CONFIG_STM32_I2C_DYNTIMEO */ static inline int stm32_i2c_sem_waitdone(struct stm32_i2c_priv_s *priv); static inline void stm32_i2c_sem_waitstop(struct stm32_i2c_priv_s *priv); #ifdef CONFIG_I2C_TRACE @@ -534,7 +534,7 @@ static const struct i2c_ops_s stm32_i2c_ops = #endif }; -#ifdef CONFIG_STM32F7_I2C1 +#ifdef CONFIG_STM32_I2C1 static const struct stm32_i2c_config_s stm32_i2c1_config = { .base = STM32_I2C1_BASE, @@ -571,7 +571,7 @@ static struct stm32_i2c_priv_s stm32_i2c1_priv = }; #endif -#ifdef CONFIG_STM32F7_I2C2 +#ifdef CONFIG_STM32_I2C2 static const struct stm32_i2c_config_s stm32_i2c2_config = { .base = STM32_I2C2_BASE, @@ -608,7 +608,7 @@ static struct stm32_i2c_priv_s stm32_i2c2_priv = }; #endif -#ifdef CONFIG_STM32F7_I2C3 +#ifdef CONFIG_STM32_I2C3 static const struct stm32_i2c_config_s stm32_i2c3_config = { .base = STM32_I2C3_BASE, @@ -645,7 +645,7 @@ static struct stm32_i2c_priv_s stm32_i2c3_priv = }; #endif -#ifdef CONFIG_STM32F7_I2C4 +#ifdef CONFIG_STM32_I2C4 static const struct stm32_i2c_config_s stm32_i2c4_config = { .base = STM32_I2C4_BASE, @@ -766,7 +766,7 @@ static inline void stm32_i2c_modifyreg32(struct stm32_i2c_priv_s *priv, * ****************************************************************************/ -#ifdef CONFIG_STM32F7_I2C_DYNTIMEO +#ifdef CONFIG_STM32_I2C_DYNTIMEO static uint32_t stm32_i2c_toticks(int msgc, struct i2c_msg_s *msgs) { size_t bytecount = 0; @@ -783,7 +783,7 @@ static uint32_t stm32_i2c_toticks(int msgc, struct i2c_msg_s *msgs) * factor. */ - return USEC2TICK(CONFIG_STM32F7_I2C_DYNTIMEO_USECPERBYTE * bytecount); + return USEC2TICK(CONFIG_STM32_I2C_DYNTIMEO_USECPERBYTE * bytecount); } #endif @@ -839,12 +839,12 @@ static inline int stm32_i2c_sem_waitdone(struct stm32_i2c_priv_s *priv) { /* Wait until either the transfer is complete or the timeout expires */ -#ifdef CONFIG_STM32F7_I2C_DYNTIMEO +#ifdef CONFIG_STM32_I2C_DYNTIMEO ret = nxsem_tickwait_uninterruptible(&priv->sem_isr, stm32_i2c_toticks(priv->msgc, priv->msgv)); #else ret = nxsem_tickwait_uninterruptible(&priv->sem_isr, - CONFIG_STM32F7_I2CTIMEOTICKS); + CONFIG_STM32_I2CTIMEOTICKS); #endif if (ret < 0) { @@ -882,10 +882,10 @@ static inline int stm32_i2c_sem_waitdone(struct stm32_i2c_priv_s *priv) /* Get the timeout value */ -#ifdef CONFIG_STM32F7_I2C_DYNTIMEO +#ifdef CONFIG_STM32_I2C_DYNTIMEO timeout = stm32_i2c_toticks(priv->msgc, priv->msgv); #else - timeout = CONFIG_STM32F7_I2CTIMEOTICKS; + timeout = CONFIG_STM32_I2CTIMEOTICKS; #endif /* Signal the interrupt handler that we are waiting. NOTE: Interrupts @@ -1023,10 +1023,10 @@ static inline void stm32_i2c_sem_waitstop(struct stm32_i2c_priv_s *priv) /* Select a timeout */ -#ifdef CONFIG_STM32F7_I2C_DYNTIMEO - timeout = USEC2TICK(CONFIG_STM32F7_I2C_DYNTIMEO_STARTSTOP); +#ifdef CONFIG_STM32_I2C_DYNTIMEO + timeout = USEC2TICK(CONFIG_STM32_I2C_DYNTIMEO_STARTSTOP); #else - timeout = CONFIG_STM32F7_I2CTIMEOTICKS; + timeout = CONFIG_STM32_I2CTIMEOTICKS; #endif /* Wait as stop might still be in progress */ @@ -2740,22 +2740,22 @@ struct i2c_master_s *stm32_i2cbus_initialize(int port) switch (port) { -#ifdef CONFIG_STM32F7_I2C1 +#ifdef CONFIG_STM32_I2C1 case 1: priv = (struct stm32_i2c_priv_s *)&stm32_i2c1_priv; break; #endif -#ifdef CONFIG_STM32F7_I2C2 +#ifdef CONFIG_STM32_I2C2 case 2: priv = (struct stm32_i2c_priv_s *)&stm32_i2c2_priv; break; #endif -#ifdef CONFIG_STM32F7_I2C3 +#ifdef CONFIG_STM32_I2C3 case 3: priv = (struct stm32_i2c_priv_s *)&stm32_i2c3_priv; break; #endif -#ifdef CONFIG_STM32F7_I2C4 +#ifdef CONFIG_STM32_I2C4 case 4: priv = (struct stm32_i2c_priv_s *)&stm32_i2c4_priv; break; @@ -2827,5 +2827,5 @@ int stm32_i2cbus_uninitialize(struct i2c_master_s *dev) return OK; } -#endif /* CONFIG_STM32F7_I2C1 || CONFIG_STM32F7_I2C2 || \ - * CONFIG_STM32F7_I2C3 || CONFIG_STM32F7_I2C4 */ +#endif /* CONFIG_STM32_I2C1 || CONFIG_STM32_I2C2 || \ + * CONFIG_STM32_I2C3 || CONFIG_STM32_I2C4 */ diff --git a/arch/arm/src/stm32f7/stm32_i2c.h b/arch/arm/src/stm32f7/stm32_i2c.h index e9bb1656b2937..4580980d9d4dc 100644 --- a/arch/arm/src/stm32f7/stm32_i2c.h +++ b/arch/arm/src/stm32f7/stm32_i2c.h @@ -41,10 +41,10 @@ * seconds per byte value must be provided as well. */ -#ifdef CONFIG_STM32F7_I2C_DYNTIMEO -# if CONFIG_STM32F7_I2C_DYNTIMEO_USECPERBYTE < 1 -# warning "Ignoring CONFIG_STM32F7_I2C_DYNTIMEO because of CONFIG_STM32F7_I2C_DYNTIMEO_USECPERBYTE" -# undef CONFIG_STM32F7_I2C_DYNTIMEO +#ifdef CONFIG_STM32_I2C_DYNTIMEO +# if CONFIG_STM32_I2C_DYNTIMEO_USECPERBYTE < 1 +# warning "Ignoring CONFIG_STM32_I2C_DYNTIMEO because of CONFIG_STM32_I2C_DYNTIMEO_USECPERBYTE" +# undef CONFIG_STM32_I2C_DYNTIMEO # endif #endif diff --git a/arch/arm/src/stm32f7/stm32_i2s.c b/arch/arm/src/stm32f7/stm32_i2s.c index f6f6d0c027208..3aa1ef321d4ee 100644 --- a/arch/arm/src/stm32f7/stm32_i2s.c +++ b/arch/arm/src/stm32f7/stm32_i2s.c @@ -76,7 +76,7 @@ #include "stm32_spi.h" #include "stm32_rcc.h" -#if defined(CONFIG_STM32F7_I2S1) || defined(CONFIG_STM32F7_I2S2) || defined(CONFIG_STM32F7_I2S3) +#if defined(CONFIG_STM32_I2S1) || defined(CONFIG_STM32_I2S2) || defined(CONFIG_STM32_I2S3) /**************************************************************************** * Pre-processor Definitions @@ -92,8 +92,8 @@ # error CONFIG_AUDIO required by this driver #endif -#ifndef CONFIG_STM32F7_I2S_MAXINFLIGHT -# define CONFIG_STM32F7_I2S_MAXINFLIGHT 16 +#ifndef CONFIG_STM32_I2S_MAXINFLIGHT +# define CONFIG_STM32_I2S_MAXINFLIGHT 16 #endif /* Assume no RX/TX support until we learn better */ @@ -103,28 +103,28 @@ /* Check for I2S RX support */ -# if defined(CONFIG_STM32F7_I2S1_RX) +# if defined(CONFIG_STM32_I2S1_RX) # define I2S_HAVE_RX 1 -# ifdef CONFIG_STM32F7_I2S1_MCK +# ifdef CONFIG_STM32_I2S1_MCK # define I2S_HAVE_MCK 1 # endif # endif -# if defined(CONFIG_STM32F7_I2S2_RX) +# if defined(CONFIG_STM32_I2S2_RX) # define I2S_HAVE_RX 1 -# ifdef CONFIG_STM32F7_I2S2_MCK +# ifdef CONFIG_STM32_I2S2_MCK # define I2S_HAVE_MCK 1 # endif # endif -# if defined(CONFIG_STM32F7_I2S3_RX) +# if defined(CONFIG_STM32_I2S3_RX) # define I2S_HAVE_RX 1 -# ifdef CONFIG_STM32F7_I2S3_MCK +# ifdef CONFIG_STM32_I2S3_MCK # define I2S_HAVE_MCK 1 # endif @@ -132,28 +132,28 @@ /* Check for I2S3 TX support */ -# if defined(CONFIG_STM32F7_I2S1_TX) +# if defined(CONFIG_STM32_I2S1_TX) # define I2S_HAVE_TX 1 -# ifdef CONFIG_STM32F7_I2S1_MCK +# ifdef CONFIG_STM32_I2S1_MCK # define I2S_HAVE_MCK 1 # endif # endif -# if defined(CONFIG_STM32F7_I2S2_TX) +# if defined(CONFIG_STM32_I2S2_TX) # define I2S_HAVE_TX 1 -# ifdef CONFIG_STM32F7_I2S2_MCK +# ifdef CONFIG_STM32_I2S2_MCK # define I2S_HAVE_MCK 1 # endif # endif -# if defined(CONFIG_STM32F7_I2S3_TX) +# if defined(CONFIG_STM32_I2S3_TX) # define I2S_HAVE_TX 1 -# ifdef CONFIG_STM32F7_I2S3_MCK +# ifdef CONFIG_STM32_I2S3_MCK # define I2S_HAVE_MCK 1 # endif @@ -163,19 +163,19 @@ /* I2S interrupts */ -#ifdef CONFIG_STM32F7_SPI_INTERRUPTS +#ifdef CONFIG_STM32_SPI_INTERRUPTS # error "Interrupt driven I2S not yet supported" #endif /* Can't have both interrupt driven SPI and SPI DMA */ -#if defined(CONFIG_STM32F7_SPI_INTERRUPTS) && defined(CONFIG_STM32F7_SPI_DMA) +#if defined(CONFIG_STM32_SPI_INTERRUPTS) && defined(CONFIG_STM32_SPI_DMA) # error "Cannot enable both interrupt mode and DMA mode for SPI" #endif /* SPI DMA priority */ -#ifdef CONFIG_STM32F7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA # if defined(CONFIG_SPI_DMAPRIO) # define SPI_DMA_PRIO CONFIG_SPI_DMAPRIO @@ -200,7 +200,7 @@ # define SPI_TXDMA16NULL_CONFIG (SPI_DMA_PRIO|DMA_SCR_MSIZE_8BITS |DMA_SCR_PSIZE_16BITS |DMA_SCR_DIR_M2P) # define SPI_TXDMA8NULL_CONFIG (SPI_DMA_PRIO|DMA_SCR_MSIZE_8BITS |DMA_SCR_PSIZE_8BITS |DMA_SCR_DIR_M2P) -#endif /* CONFIG_STM32F7_SPI_DMA */ +#endif /* CONFIG_STM32_SPI_DMA */ /* Debug ********************************************************************/ @@ -209,56 +209,56 @@ */ #ifndef CONFIG_DEBUG_I2S_INFO -# undef CONFIG_STM32F7_I2S_DMADEBUG -# undef CONFIG_STM32F7_I2S_REGDEBUG -# undef CONFIG_STM32F7_I2S_QDEBUG -# undef CONFIG_STM32F7_I2S_DUMPBUFFERS +# undef CONFIG_STM32_I2S_DMADEBUG +# undef CONFIG_STM32_I2S_REGDEBUG +# undef CONFIG_STM32_I2S_QDEBUG +# undef CONFIG_STM32_I2S_DUMPBUFFERS #endif /* The I2S can handle most any bit width from 8 to 32. However, the DMA * logic here is constrained to byte, half-word, and word sizes. */ -#ifndef CONFIG_STM32F7_I2S1_DATALEN -# define CONFIG_STM32F7_I2S1_DATALEN 16 +#ifndef CONFIG_STM32_I2S1_DATALEN +# define CONFIG_STM32_I2S1_DATALEN 16 #endif -#ifndef CONFIG_STM32F7_I2S2_DATALEN -# define CONFIG_STM32F7_I2S2_DATALEN 16 +#ifndef CONFIG_STM32_I2S2_DATALEN +# define CONFIG_STM32_I2S2_DATALEN 16 #endif -#ifndef CONFIG_STM32F7_I2S3_DATALEN -# define CONFIG_STM32F7_I2S3_DATALEN 16 +#ifndef CONFIG_STM32_I2S3_DATALEN +# define CONFIG_STM32_I2S3_DATALEN 16 #endif -#if CONFIG_STM32F7_I2S1_DATALEN == 8 -# define STM32F7_I2S1_DATAMASK 0 -#elif CONFIG_STM32F7_I2S1_DATALEN == 16 -# define STM32F7_I2S1_DATAMASK 1 -#elif CONFIG_STM32F7_I2S1_DATALEN < 8 || CONFIG_STM32F7_I2S1_DATALEN > 16 -# error Invalid value for CONFIG_STM32F7_I2S1_DATALEN +#if CONFIG_STM32_I2S1_DATALEN == 8 +# define STM32_I2S1_DATAMASK 0 +#elif CONFIG_STM32_I2S1_DATALEN == 16 +# define STM32_I2S1_DATAMASK 1 +#elif CONFIG_STM32_I2S1_DATALEN < 8 || CONFIG_STM32_I2S1_DATALEN > 16 +# error Invalid value for CONFIG_STM32_I2S1_DATALEN #else -# error Valid but supported value for CONFIG_STM32F7_I2S1_DATALEN +# error Valid but supported value for CONFIG_STM32_I2S1_DATALEN #endif -#if CONFIG_STM32F7_I2S2_DATALEN == 8 -# define STM32F7_I2S2_DATAMASK 0 -#elif CONFIG_STM32F7_I2S2_DATALEN == 16 -# define STM32F7_I2S2_DATAMASK 1 -#elif CONFIG_STM32F7_I2S2_DATALEN < 8 || CONFIG_STM32F7_I2S2_DATALEN > 16 -# error Invalid value for CONFIG_STM32F7_I2S2_DATALEN +#if CONFIG_STM32_I2S2_DATALEN == 8 +# define STM32_I2S2_DATAMASK 0 +#elif CONFIG_STM32_I2S2_DATALEN == 16 +# define STM32_I2S2_DATAMASK 1 +#elif CONFIG_STM32_I2S2_DATALEN < 8 || CONFIG_STM32_I2S2_DATALEN > 16 +# error Invalid value for CONFIG_STM32_I2S2_DATALEN #else -# error Valid but supported value for CONFIG_STM32F7_I2S1_DATALEN +# error Valid but supported value for CONFIG_STM32_I2S1_DATALEN #endif -#if CONFIG_STM32F7_I2S3_DATALEN == 8 -# define STM32F7_I2S3_DATAMASK 0 -#elif CONFIG_STM32F7_I2S3_DATALEN == 16 -# define STM32F7_I2S3_DATAMASK 1 -#elif CONFIG_STM32F7_I2S3_DATALEN < 8 || CONFIG_STM32F7_I2S3_DATALEN > 16 -# error Invalid value for CONFIG_STM32F7_I2S3_DATALEN +#if CONFIG_STM32_I2S3_DATALEN == 8 +# define STM32_I2S3_DATAMASK 0 +#elif CONFIG_STM32_I2S3_DATALEN == 16 +# define STM32_I2S3_DATAMASK 1 +#elif CONFIG_STM32_I2S3_DATALEN < 8 || CONFIG_STM32_I2S3_DATALEN > 16 +# error Invalid value for CONFIG_STM32_I2S3_DATALEN #else -# error Valid but supported value for CONFIG_STM32F7_I2S3_DATALEN +# error Valid but supported value for CONFIG_STM32_I2S3_DATALEN #endif /* Check if we need to build RX and/or TX support */ @@ -266,7 +266,7 @@ #if defined(I2S_HAVE_RX) || defined(I2S_HAVE_TX) #ifndef CONFIG_DEBUG_DMA -# undef CONFIG_STM32F7_I2S_DMADEBUG +# undef CONFIG_STM32_I2S_DMADEBUG #endif #define DMA_INITIAL 0 @@ -309,7 +309,7 @@ struct stm32_transport_s sq_queue_t done; /* A queue of completed transfers */ struct work_s work; /* Supports worker thread operations */ -#ifdef CONFIG_STM32F7_I2S_DMADEBUG +#ifdef CONFIG_STM32_I2S_DMADEBUG struct stm32_dmaregs_s dmaregs[DMA_NSAMPLES]; #endif }; @@ -344,11 +344,11 @@ struct stm32_i2s_s sem_t bufsem; /* Buffer wait semaphore */ struct stm32_buffer_s *freelist; /* A list a free buffer containers */ - struct stm32_buffer_s containers[CONFIG_STM32F7_I2S_MAXINFLIGHT]; + struct stm32_buffer_s containers[CONFIG_STM32_I2S_MAXINFLIGHT]; /* Debug stuff */ -#ifdef CONFIG_STM32F7_I2S_REGDEBUG +#ifdef CONFIG_STM32_I2S_REGDEBUG bool wr; /* Last was a write */ uint32_t regaddr; /* Last address */ uint16_t regval; /* Last value */ @@ -362,7 +362,7 @@ struct stm32_i2s_s /* Register helpers */ -#ifdef CONFIG_STM32F7_I2S_REGDEBUG +#ifdef CONFIG_STM32_I2S_REGDEBUG static bool i2s_checkreg(struct stm32_i2s_s *priv, bool wr, uint16_t regval, uint32_t regaddr); #else @@ -379,7 +379,7 @@ static void i2s_dump_regs(struct stm32_i2s_s *priv, const char *msg); # define i2s_dump_regs(s,m) #endif -#ifdef CONFIG_STM32F7_I2S_DUMPBUFFERS +#ifdef CONFIG_STM32_I2S_DUMPBUFFERS # define i2s_init_buffer(b,s) memset(b, 0x55, s); # define i2s_dump_buffer(m,b,s) lib_dumpbuffer(m,b,s) #else @@ -397,12 +397,12 @@ static void i2s_buf_initialize(struct stm32_i2s_s *priv); /* DMA support */ -#ifdef CONFIG_STM32F7_I2S_DMADEBUG +#ifdef CONFIG_STM32_I2S_DMADEBUG static void i2s_dma_sampleinit(struct stm32_i2s_s *priv, struct stm32_transport_s *xpt); #endif -#if defined(CONFIG_STM32F7_I2S_DMADEBUG) && defined(I2S_HAVE_RX) +#if defined(CONFIG_STM32_I2S_DMADEBUG) && defined(I2S_HAVE_RX) # define i2s_rxdma_sample(s,i) stm32_dmasample((s)->rx.dma, &(s)->rx.dmaregs[i]) # define i2s_rxdma_sampleinit(s) i2s_dma_sampleinit(s, &(s)->rx) static void i2s_rxdma_sampledone(struct stm32_i2s_s *priv, int result); @@ -414,7 +414,7 @@ static void i2s_rxdma_sampledone(struct stm32_i2s_s *priv, int result); #endif -#if defined(CONFIG_STM32F7_I2S_DMADEBUG) && defined(I2S_HAVE_TX) +#if defined(CONFIG_STM32_I2S_DMADEBUG) && defined(I2S_HAVE_TX) # define i2s_txdma_sample(s,i) stm32_dmasample((s)->tx.dma, &(s)->tx.dmaregs[i]) # define i2s_txdma_sampleinit(s) i2s_dma_sampleinit(s, &(s)->tx) static void i2s_txdma_sampledone(struct stm32_i2s_s *priv, int result); @@ -467,15 +467,15 @@ static int i2s_dma_flags(struct stm32_i2s_s *priv); static int i2s_dma_allocate(struct stm32_i2s_s *priv); static void i2s_dma_free(struct stm32_i2s_s *priv); -#ifdef CONFIG_STM32F7_I2S1 +#ifdef CONFIG_STM32_I2S1 static void i2s1_configure(struct stm32_i2s_s *priv); #endif -#ifdef CONFIG_STM32F7_I2S2 +#ifdef CONFIG_STM32_I2S2 static void i2s2_configure(struct stm32_i2s_s *priv); #endif -#ifdef CONFIG_STM32F7_I2S3 +#ifdef CONFIG_STM32_I2S3 static void i2s3_configure(struct stm32_i2s_s *priv); #endif @@ -520,7 +520,7 @@ static const struct i2s_ops_s g_i2sops = * ****************************************************************************/ -#ifdef CONFIG_STM32F7_I2S_REGDEBUG +#ifdef CONFIG_STM32_I2S_REGDEBUG static bool i2s_checkreg(struct stm32_i2s_s *priv, bool wr, uint16_t regval, uint32_t regaddr) { @@ -579,7 +579,7 @@ static inline uint16_t i2s_getreg(struct stm32_i2s_s *priv, uint32_t regaddr = priv->base + offset; uint16_t regval = getreg16(regaddr); -#ifdef CONFIG_STM32F7_I2S_REGDEBUG +#ifdef CONFIG_STM32_I2S_REGDEBUG if (i2s_checkreg(priv, false, regval, regaddr)) { i2sinfo("%08" PRIx32 "->%04x\n", regaddr, regval); @@ -610,7 +610,7 @@ static inline void i2s_putreg(struct stm32_i2s_s *priv, uint8_t offset, { uint32_t regaddr = priv->base + offset; -#ifdef CONFIG_STM32F7_I2S_REGDEBUG +#ifdef CONFIG_STM32_I2S_REGDEBUG if (i2s_checkreg(priv, true, regval, regaddr)) { i2sinfo("%08" PRIx32 "<-%04x\n", regaddr, regval); @@ -759,9 +759,9 @@ static void i2s_buf_initialize(struct stm32_i2s_s *priv) int i; priv->freelist = NULL; - nxsem_init(&priv->bufsem, 0, CONFIG_STM32F7_I2S_MAXINFLIGHT); + nxsem_init(&priv->bufsem, 0, CONFIG_STM32_I2S_MAXINFLIGHT); - for (i = 0; i < CONFIG_STM32F7_I2S_MAXINFLIGHT; i++) + for (i = 0; i < CONFIG_STM32_I2S_MAXINFLIGHT; i++) { i2s_buf_free(priv, &priv->containers[i]); } @@ -771,7 +771,7 @@ static void i2s_buf_initialize(struct stm32_i2s_s *priv) * Name: i2s_dma_sampleinit * * Description: - * Initialize sampling of DMA registers (if CONFIG_STM32F7_I2S_DMADEBUG) + * Initialize sampling of DMA registers (if CONFIG_STM32_I2S_DMADEBUG) * * Input Parameters: * priv - I2S state instance @@ -781,7 +781,7 @@ static void i2s_buf_initialize(struct stm32_i2s_s *priv) * ****************************************************************************/ -#if defined(CONFIG_STM32F7_I2S_DMADEBUG) +#if defined(CONFIG_STM32_I2S_DMADEBUG) static void i2s_dma_sampleinit(struct stm32_i2s_s *priv, struct stm32_transport_s *xpt) { @@ -809,7 +809,7 @@ static void i2s_dma_sampleinit(struct stm32_i2s_s *priv, * ****************************************************************************/ -#if defined(CONFIG_STM32F7_I2S_DMADEBUG) && defined(I2S_HAVE_RX) +#if defined(CONFIG_STM32_I2S_DMADEBUG) && defined(I2S_HAVE_RX) static void i2s_rxdma_sampledone(struct stm32_i2s_s *priv, int result) { i2sinfo("result: %d\n", result); @@ -875,7 +875,7 @@ static void i2s_rxdma_sampledone(struct stm32_i2s_s *priv, int result) * ****************************************************************************/ -#if defined(CONFIG_STM32F7_I2S_DMADEBUG) && defined(I2S_HAVE_TX) +#if defined(CONFIG_STM32_I2S_DMADEBUG) && defined(I2S_HAVE_TX) static void i2s_txdma_sampledone(struct stm32_i2s_s *priv, int result) { i2sinfo("result: %d\n", result); @@ -1145,7 +1145,7 @@ static void i2s_rx_worker(void *arg) if (sq_empty(&priv->rx.act)) { -#ifdef CONFIG_STM32F7_I2S_DMADEBUG +#ifdef CONFIG_STM32_I2S_DMADEBUG bfcontainer = (struct stm32_buffer_s *)sq_peek(&priv->rx.done); if (bfcontainer) { @@ -1543,7 +1543,7 @@ static void i2s_tx_worker(void *arg) if (sq_empty(&priv->tx.act)) { -#ifdef CONFIG_STM32F7_I2S_DMADEBUG +#ifdef CONFIG_STM32_I2S_DMADEBUG bfcontainer = (struct stm32_buffer_s *)sq_peek(&priv->tx.done); if (bfcontainer) { @@ -2441,7 +2441,7 @@ static void i2s_dma_free(struct stm32_i2s_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32F7_I2S1 +#ifdef CONFIG_STM32_I2S1 static void i2s1_configure(struct stm32_i2s_s *priv) { /* Configure multiplexed pins as connected on the board. Chip @@ -2450,7 +2450,7 @@ static void i2s1_configure(struct stm32_i2s_s *priv) priv->base = STM32_I2S1_BASE; -#ifdef CONFIG_STM32F7_I2S1_RX +#ifdef CONFIG_STM32_I2S1_RX priv->rxenab = true; if (!priv->initialized) @@ -2463,9 +2463,9 @@ static void i2s1_configure(struct stm32_i2s_s *priv) stm32_configgpio(GPIO_I2S1_WS); priv->initialized = true; } -#endif /* CONFIG_STM32F7_I2S1_RX */ +#endif /* CONFIG_STM32_I2S1_RX */ -#ifdef CONFIG_STM32F7_I2S1_TX +#ifdef CONFIG_STM32_I2S1_TX priv->txenab = true; /* Only configure if the port is not already configured */ @@ -2480,16 +2480,16 @@ static void i2s1_configure(struct stm32_i2s_s *priv) stm32_configgpio(GPIO_I2S1_WS); priv->initialized = true; } -#endif /* CONFIG_STM32F7_I2S1_TX */ +#endif /* CONFIG_STM32_I2S1_TX */ /* Configure driver state specific to this I2S peripheral */ - priv->datalen = CONFIG_STM32F7_I2S1_DATALEN; + priv->datalen = CONFIG_STM32_I2S1_DATALEN; #ifdef CONFIG_DEBUG - priv->align = STM32F7_I2S2_DATAMASK; + priv->align = STM32_I2S2_DATAMASK; #endif } -#endif /* CONFIG_STM32F7_I2S1 */ +#endif /* CONFIG_STM32_I2S1 */ /**************************************************************************** * Name: i2s2_configure @@ -2506,7 +2506,7 @@ static void i2s1_configure(struct stm32_i2s_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32F7_I2S2 +#ifdef CONFIG_STM32_I2S2 static void i2s2_configure(struct stm32_i2s_s *priv) { /* Configure multiplexed pins as connected on the board. Chip @@ -2515,7 +2515,7 @@ static void i2s2_configure(struct stm32_i2s_s *priv) priv->base = STM32_I2S2_BASE; -#ifdef CONFIG_STM32F7_I2S2_RX +#ifdef CONFIG_STM32_I2S2_RX priv->rxenab = true; if (!priv->initialized) @@ -2528,9 +2528,9 @@ static void i2s2_configure(struct stm32_i2s_s *priv) stm32_configgpio(GPIO_I2S2_WS); priv->initialized = true; } -#endif /* CONFIG_STM32F7_I2S2_RX */ +#endif /* CONFIG_STM32_I2S2_RX */ -#ifdef CONFIG_STM32F7_I2S2_TX +#ifdef CONFIG_STM32_I2S2_TX priv->txenab = true; /* Only configure if the port is not already configured */ @@ -2545,16 +2545,16 @@ static void i2s2_configure(struct stm32_i2s_s *priv) stm32_configgpio(GPIO_I2S2_WS); priv->initialized = true; } -#endif /* CONFIG_STM32F7_I2S2_TX */ +#endif /* CONFIG_STM32_I2S2_TX */ /* Configure driver state specific to this I2S peripheral */ - priv->datalen = CONFIG_STM32F7_I2S2_DATALEN; + priv->datalen = CONFIG_STM32_I2S2_DATALEN; #ifdef CONFIG_DEBUG - priv->align = STM32F7_I2S2_DATAMASK; + priv->align = STM32_I2S2_DATAMASK; #endif } -#endif /* CONFIG_STM32F7_I2S2 */ +#endif /* CONFIG_STM32_I2S2 */ /**************************************************************************** * Name: i2s3_configure @@ -2571,7 +2571,7 @@ static void i2s2_configure(struct stm32_i2s_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32F7_I2S3 +#ifdef CONFIG_STM32_I2S3 static void i2s3_configure(struct stm32_i2s_s *priv) { /* Configure multiplexed pins as connected on the board. Chip @@ -2580,7 +2580,7 @@ static void i2s3_configure(struct stm32_i2s_s *priv) priv->base = STM32_I2S3_BASE; -#ifdef CONFIG_STM32F7_I2S3_RX +#ifdef CONFIG_STM32_I2S3_RX priv->rxenab = true; if (!priv->initialized) @@ -2593,9 +2593,9 @@ static void i2s3_configure(struct stm32_i2s_s *priv) stm32_configgpio(GPIO_I2S3_WS); priv->initialized = true; } -#endif /* CONFIG_STM32F7_I2S3_RX */ +#endif /* CONFIG_STM32_I2S3_RX */ -#ifdef CONFIG_STM32F7_I2S3_TX +#ifdef CONFIG_STM32_I2S3_TX priv->txenab = true; /* Only configure if the port is not already configured */ @@ -2610,16 +2610,16 @@ static void i2s3_configure(struct stm32_i2s_s *priv) stm32_configgpio(GPIO_I2S3_WS); priv->initialized = true; } -#endif /* CONFIG_STM32F7_I2S3_TX */ +#endif /* CONFIG_STM32_I2S3_TX */ /* Configure driver state specific to this I2S peripheral */ - priv->datalen = CONFIG_STM32F7_I2S3_DATALEN; + priv->datalen = CONFIG_STM32_I2S3_DATALEN; #ifdef CONFIG_DEBUG - priv->align = STM32F7_I2S3_DATAMASK; + priv->align = STM32_I2S3_DATAMASK; #endif } -#endif /* CONFIG_STM32F7_I2S3 */ +#endif /* CONFIG_STM32_I2S3 */ /**************************************************************************** * Public Functions @@ -2677,7 +2677,7 @@ struct i2s_dev_s *stm32_i2sbus_initialize(int port) flags = enter_critical_section(); -#ifdef CONFIG_STM32F7_I2S1 +#ifdef CONFIG_STM32_I2S1 if (port == 1) { /* Select I2S1 */ @@ -2686,7 +2686,7 @@ struct i2s_dev_s *stm32_i2sbus_initialize(int port) } else #endif -#ifdef CONFIG_STM32F7_I2S2 +#ifdef CONFIG_STM32_I2S2 if (port == 2) { /* Select I2S2 */ @@ -2695,7 +2695,7 @@ struct i2s_dev_s *stm32_i2sbus_initialize(int port) } else #endif -#ifdef CONFIG_STM32F7_I2S3 +#ifdef CONFIG_STM32_I2S3 if (port == 3) { /* Select I2S3 */ @@ -2736,4 +2736,4 @@ struct i2s_dev_s *stm32_i2sbus_initialize(int port) } #endif /* I2S_HAVE_RX || I2S_HAVE_TX */ -#endif /* CONFIG_STM32F7_I2S1 || CONFIG_STM32F7_I2S2 || CONFIG_STM32F7_I2S3 */ +#endif /* CONFIG_STM32_I2S1 || CONFIG_STM32_I2S2 || CONFIG_STM32_I2S3 */ diff --git a/arch/arm/src/stm32f7/stm32_irq.c b/arch/arm/src/stm32f7/stm32_irq.c index 0d7080377e8cf..5b768bb9bcdf8 100644 --- a/arch/arm/src/stm32f7/stm32_irq.c +++ b/arch/arm/src/stm32f7/stm32_irq.c @@ -40,7 +40,7 @@ #include "ram_vectors.h" #include "arm_internal.h" -#ifdef CONFIG_STM32F7_GPIO_IRQ +#ifdef CONFIG_STM32_GPIO_IRQ # include "stm32_gpio.h" #endif @@ -402,7 +402,7 @@ void up_irqinitialize(void) * GPIO pins. */ -#ifdef CONFIG_STM32F7_GPIO_IRQ +#ifdef CONFIG_STM32_GPIO_IRQ stm32_gpioirqinitialize(); #endif @@ -446,7 +446,7 @@ void up_disable_irq(int irq) putreg32(regval, regaddr); } } -#ifdef CONFIG_STM32F7_GPIO_IRQ +#ifdef CONFIG_STM32_GPIO_IRQ else { /* Maybe it is a (derived) GPIO IRQ */ @@ -493,7 +493,7 @@ void up_enable_irq(int irq) putreg32(regval, regaddr); } } -#ifdef CONFIG_STM32F7_GPIO_IRQ +#ifdef CONFIG_STM32_GPIO_IRQ else { /* Maybe it is a (derived) GPIO IRQ */ diff --git a/arch/arm/src/stm32f7/stm32_lse.c b/arch/arm/src/stm32f7/stm32_lse.c index 10846796bba52..ecc5b01ca3d55 100644 --- a/arch/arm/src/stm32f7/stm32_lse.c +++ b/arch/arm/src/stm32f7/stm32_lse.c @@ -41,16 +41,16 @@ static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1, #define LSERDY_TIMEOUT (500 * CONFIG_BOARD_LOOPSPERMSEC) -#ifdef CONFIG_STM32F7_RTC_LSECLOCK_START_DRV_CAPABILITY -# if CONFIG_STM32F7_RTC_LSECLOCK_START_DRV_CAPABILITY < 0 || \ - CONFIG_STM32F7_RTC_LSECLOCK_START_DRV_CAPABILITY > 3 +#ifdef CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY +# if CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY < 0 || \ + CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY > 3 # error "Invalid LSE drive capability setting" # endif #endif -#ifdef CONFIG_STM32F7_RTC_LSECLOCK_RUN_DRV_CAPABILITY -# if CONFIG_STM32F7_RTC_LSECLOCK_RUN_DRV_CAPABILITY < 0 || \ - CONFIG_STM32F7_RTC_LSECLOCK_RUN_DRV_CAPABILITY > 3 +#ifdef CONFIG_STM32_RTC_LSECLOCK_RUN_DRV_CAPABILITY +# if CONFIG_STM32_RTC_LSECLOCK_RUN_DRV_CAPABILITY < 0 || \ + CONFIG_STM32_RTC_LSECLOCK_RUN_DRV_CAPABILITY > 3 # error "Invalid LSE drive capability setting" # endif #endif @@ -59,7 +59,7 @@ static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1, * Private Data ****************************************************************************/ -#ifdef CONFIG_STM32F7_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY +#ifdef CONFIG_STM32_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY static const uint32_t drives[4] = { RCC_BDCR_LSEDRV_LOW, @@ -85,7 +85,7 @@ void stm32_rcc_enablelse(void) { uint32_t regval; volatile int32_t timeout; -#ifdef CONFIG_STM32F7_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY +#ifdef CONFIG_STM32_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY volatile int32_t drive = 0; #endif @@ -109,17 +109,17 @@ void stm32_rcc_enablelse(void) regval |= RCC_BDCR_LSEON; -#ifdef CONFIG_STM32F7_RTC_LSECLOCK_START_DRV_CAPABILITY +#ifdef CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY /* Set start-up drive capability for LSE oscillator. With the * enable on. */ regval &= ~(RCC_BDCR_LSEDRV_MASK); - regval |= CONFIG_STM32F7_RTC_LSECLOCK_START_DRV_CAPABILITY << + regval |= CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY << RCC_BDCR_LSEDRV_SHIFT; #endif -#ifdef CONFIG_STM32F7_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY +#ifdef CONFIG_STM32_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY do { regval &= ~(RCC_BDCR_LSEDRV_MASK); @@ -145,7 +145,7 @@ void stm32_rcc_enablelse(void) } } -#ifdef CONFIG_STM32F7_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY +#ifdef CONFIG_STM32_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY if (timeout != 0) { break; @@ -153,13 +153,13 @@ void stm32_rcc_enablelse(void) } while (drive < sizeof(drives) / sizeof(drives[0])); #endif -#if defined(CONFIG_STM32F7_RTC_LSECLOCK_RUN_DRV_CAPABILITY) && \ - CONFIG_STM32F7_RTC_LSECLOCK_START_DRV_CAPABILITY != \ - CONFIG_STM32F7_RTC_LSECLOCK_RUN_DRV_CAPABILITY +#if defined(CONFIG_STM32_RTC_LSECLOCK_RUN_DRV_CAPABILITY) && \ + CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY != \ + CONFIG_STM32_RTC_LSECLOCK_RUN_DRV_CAPABILITY /* Set running drive capability for LSE oscillator. */ regval &= ~RCC_BDCR_LSEDRV_MASK; - regval |= CONFIG_STM32F7_RTC_LSECLOCK_RUN_DRV_CAPABILITY << + regval |= CONFIG_STM32_RTC_LSECLOCK_RUN_DRV_CAPABILITY << RCC_BDCR_LSEDRV_SHIFT; putreg32(regval, STM32_RCC_BDCR); #endif diff --git a/arch/arm/src/stm32f7/stm32_ltdc.c b/arch/arm/src/stm32f7/stm32_ltdc.c index c7f1aff78d63c..e33dd053ee37f 100644 --- a/arch/arm/src/stm32f7/stm32_ltdc.c +++ b/arch/arm/src/stm32f7/stm32_ltdc.c @@ -129,8 +129,8 @@ /* Configuration ************************************************************/ -#ifndef CONFIG_STM32F7_LTDC_DEFBACKLIGHT -# define CONFIG_STM32F7_LTDC_DEFBACKLIGHT 0xf0 +#ifndef CONFIG_STM32_LTDC_DEFBACKLIGHT +# define CONFIG_STM32_LTDC_DEFBACKLIGHT 0xf0 #endif #define STM32_LTDC_BACKLIGHT_OFF 0x00 @@ -138,23 +138,23 @@ /* Layer 1 format */ -#if defined(CONFIG_STM32F7_LTDC_L1_L8) +#if defined(CONFIG_STM32_LTDC_L1_L8) # define STM32_LTDC_L1_BPP 8 # define STM32_LTDC_L1_COLOR_FMT FB_FMT_RGB8 # define STM32_LTDC_L1PFCR_PF LTDC_LXPFCR_PF(LTDC_PF_L8) # define STM32_LTDC_L1_DMA2D_PF DMA2D_PF_L8 # define STM32_LTDC_L1CMAP -#elif defined(CONFIG_STM32F7_LTDC_L1_RGB565) +#elif defined(CONFIG_STM32_LTDC_L1_RGB565) # define STM32_LTDC_L1_BPP 16 # define STM32_LTDC_L1_COLOR_FMT FB_FMT_RGB16_565 # define STM32_LTDC_L1PFCR_PF LTDC_LXPFCR_PF(LTDC_PF_RGB565) # define STM32_LTDC_L1_DMA2D_PF DMA2D_PF_RGB565 -#elif defined(CONFIG_STM32F7_LTDC_L1_RGB888) +#elif defined(CONFIG_STM32_LTDC_L1_RGB888) # define STM32_LTDC_L1_BPP 24 # define STM32_LTDC_L1_COLOR_FMT FB_FMT_RGB24 # define STM32_LTDC_L1PFCR_PF LTDC_LXPFCR_PF(LTDC_PF_RGB888) # define STM32_LTDC_L1_DMA2D_PF DMA2D_PF_RGB888 -#elif defined(CONFIG_STM32F7_LTDC_L1_ARGB8888) +#elif defined(CONFIG_STM32_LTDC_L1_ARGB8888) # define STM32_LTDC_L1_BPP 32 # define STM32_LTDC_L1_COLOR_FMT FB_FMT_RGB32 # define STM32_LTDC_L1PFCR_PF LTDC_LXPFCR_PF(LTDC_PF_ARGB8888) @@ -165,24 +165,24 @@ /* Layer 2 format */ -#ifdef CONFIG_STM32F7_LTDC_L2 -# if defined(CONFIG_STM32F7_LTDC_L2_L8) +#ifdef CONFIG_STM32_LTDC_L2 +# if defined(CONFIG_STM32_LTDC_L2_L8) # define STM32_LTDC_L2_BPP 8 # define STM32_LTDC_L2_COLOR_FMT FB_FMT_RGB8 # define STM32_LTDC_L2PFCR_PF LTDC_LXPFCR_PF(LTDC_PF_L8) # define STM32_LTDC_L2_DMA2D_PF DMA2D_PF_L8 # define STM32_LTDC_L2CMAP -# elif defined(CONFIG_STM32F7_LTDC_L2_RGB565) +# elif defined(CONFIG_STM32_LTDC_L2_RGB565) # define STM32_LTDC_L2_BPP 16 # define STM32_LTDC_L2_COLOR_FMT FB_FMT_RGB16_565 # define STM32_LTDC_L2PFCR_PF LTDC_LXPFCR_PF(LTDC_PF_RGB565) # define STM32_LTDC_L2_DMA2D_PF DMA2D_PF_RGB565 -# elif defined(CONFIG_STM32F7_LTDC_L2_RGB888) +# elif defined(CONFIG_STM32_LTDC_L2_RGB888) # define STM32_LTDC_L2_BPP 24 # define STM32_LTDC_L2_COLOR_FMT FB_FMT_RGB24 # define STM32_LTDC_L2PFCR_PF LTDC_LXPFCR_PF(LTDC_PF_RGB888) # define STM32_LTDC_L2_DMA2D_PF DMA2D_PF_RGB888 -# elif defined(CONFIG_STM32F7_LTDC_L2_ARGB8888) +# elif defined(CONFIG_STM32_LTDC_L2_ARGB8888) # define STM32_LTDC_L2_BPP 32 # define STM32_LTDC_L2_COLOR_FMT FB_FMT_RGB32 # define STM32_LTDC_L2PFCR_PF LTDC_LXPFCR_PF(LTDC_PF_ARGB8888) @@ -190,7 +190,7 @@ # else # error "LTDC pixel format not supported" # endif -#endif /* CONFIG_STM32F7_LTDC_L2 */ +#endif /* CONFIG_STM32_LTDC_L2 */ /* Framebuffer sizes in bytes */ @@ -212,37 +212,37 @@ #define STM32_LTDC_L1_FBSIZE (STM32_LTDC_L1_STRIDE * STM32_LTDC_HEIGHT) -#ifdef CONFIG_STM32F7_LTDC_L2 -# ifndef CONFIG_STM32F7_LTDC_L2_WIDTH -# define CONFIG_STM32F7_LTDC_L2_WIDTH STM32_LTDC_WIDTH +#ifdef CONFIG_STM32_LTDC_L2 +# ifndef CONFIG_STM32_LTDC_L2_WIDTH +# define CONFIG_STM32_LTDC_L2_WIDTH STM32_LTDC_WIDTH # endif -# if CONFIG_STM32F7_LTDC_L2_WIDTH > STM32_LTDC_WIDTH +# if CONFIG_STM32_LTDC_L2_WIDTH > STM32_LTDC_WIDTH # error Width of Layer 2 exceeds the width of the display # endif -# ifndef CONFIG_STM32F7_LTDC_L2_HEIGHT -# define CONFIG_STM32F7_LTDC_L2_HEIGHT STM32_LTDC_HEIGHT +# ifndef CONFIG_STM32_LTDC_L2_HEIGHT +# define CONFIG_STM32_LTDC_L2_HEIGHT STM32_LTDC_HEIGHT # endif -# if CONFIG_STM32F7_LTDC_L2_HEIGHT > STM32_LTDC_HEIGHT +# if CONFIG_STM32_LTDC_L2_HEIGHT > STM32_LTDC_HEIGHT # error Height of Layer 2 exceeds the height of the display # endif # if STM32_LTDC_L2_BPP == 8 -# define STM32_LTDC_L2_STRIDE (CONFIG_STM32F7_LTDC_L2_WIDTH) +# define STM32_LTDC_L2_STRIDE (CONFIG_STM32_LTDC_L2_WIDTH) # elif STM32_LTDC_L2_BPP == 16 -# define STM32_LTDC_L2_STRIDE ((CONFIG_STM32F7_LTDC_L2_WIDTH * 16 + 7) / 8) +# define STM32_LTDC_L2_STRIDE ((CONFIG_STM32_LTDC_L2_WIDTH * 16 + 7) / 8) # elif STM32_LTDC_L2_BPP == 24 -# define STM32_LTDC_L2_STRIDE ((CONFIG_STM32F7_LTDC_L2_WIDTH * 24 + 7) / 8) +# define STM32_LTDC_L2_STRIDE ((CONFIG_STM32_LTDC_L2_WIDTH * 24 + 7) / 8) # elif STM32_LTDC_L2_BPP == 32 -# define STM32_LTDC_L2_STRIDE ((CONFIG_STM32F7_LTDC_L2_WIDTH * 32 + 7) / 8) +# define STM32_LTDC_L2_STRIDE ((CONFIG_STM32_LTDC_L2_WIDTH * 32 + 7) / 8) # else # error Undefined or unrecognized base resolution # endif # define STM32_LTDC_L2_FBSIZE (STM32_LTDC_L2_STRIDE * \ - CONFIG_STM32F7_LTDC_L2_HEIGHT) + CONFIG_STM32_LTDC_L2_HEIGHT) #else # define STM32_LTDC_L2_FBSIZE (0) @@ -256,7 +256,7 @@ /* Debug option */ -#ifdef CONFIG_STM32F7_LTDC_REGDEBUG +#ifdef CONFIG_STM32_LTDC_REGDEBUG # define regerr lcderr # define reginfo lcdinfo #else @@ -271,10 +271,10 @@ * against wild framebuffer writes. */ -#define STM32_LTDC_BUFFER_SIZE CONFIG_STM32F7_LTDC_FB_SIZE +#define STM32_LTDC_BUFFER_SIZE CONFIG_STM32_LTDC_FB_SIZE #define STM32_LTDC_BUFFER_FREE (STM32_LTDC_BUFFER_SIZE - \ STM32_LTDC_TOTAL_FBSIZE) -#define STM32_LTDC_BUFFER_START (CONFIG_STM32F7_LTDC_FB_BASE + \ +#define STM32_LTDC_BUFFER_START (CONFIG_STM32_LTDC_FB_BASE + \ STM32_LTDC_BUFFER_FREE/2) #if STM32_LTDC_BUFFER_FREE < 0 @@ -287,7 +287,7 @@ #define STM32_LTDC_ENDBUF_L1 (STM32_LTDC_BUFFER_L1 + \ STM32_LTDC_L1_FBSIZE) -#ifdef CONFIG_STM32F7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 # define STM32_LTDC_BUFFER_L2 STM32_LTDC_ENDBUF_L1 # define STM32_LTDC_ENDBUF_L2 (STM32_LTDC_BUFFER_L2 + \ STM32_LTDC_L2_FBSIZE) @@ -297,7 +297,7 @@ /* LTDC layer */ -#ifdef CONFIG_STM32F7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 # define LTDC_NLAYERS 2 #else # define LTDC_NLAYERS 1 @@ -305,27 +305,27 @@ /* DMA2D layer */ -#ifdef CONFIG_STM32F7_DMA2D -# define DMA2D_NLAYERS CONFIG_STM32F7_DMA2D_NLAYERS +#ifdef CONFIG_STM32_DMA2D +# define DMA2D_NLAYERS CONFIG_STM32_DMA2D_NLAYERS # if DMA2D_NLAYERS < 1 # error "DMA2D must at least support 1 overlay" # endif -#define STM32_DMA2D_WIDTH CONFIG_STM32F7_DMA2D_LAYER_PPLINE +#define STM32_DMA2D_WIDTH CONFIG_STM32_DMA2D_LAYER_PPLINE -# if defined(CONFIG_STM32F7_DMA2D_L8) +# if defined(CONFIG_STM32_DMA2D_L8) # define STM32_DMA2D_STRIDE (STM32_DMA2D_WIDTH) # define STM32_DMA2D_BPP 8 # define STM32_DMA2D_COLOR_FMT DMA2D_PF_L8 -# elif defined(CONFIG_STM32F7_DMA2D_RGB565) +# elif defined(CONFIG_STM32_DMA2D_RGB565) # define STM32_DMA2D_STRIDE ((STM32_DMA2D_WIDTH * 16 + 7) / 8) # define STM32_DMA2D_BPP 16 # define STM32_DMA2D_COLOR_FMT DMA2D_PF_RGB565 -# elif defined(CONFIG_STM32F7_DMA2D_RGB888) +# elif defined(CONFIG_STM32_DMA2D_RGB888) # define STM32_DMA2D_STRIDE ((STM32_DMA2D_WIDTH * 24 + 7) / 8) # define STM32_DMA2D_BPP 24 # define STM32_DMA2D_COLOR_FMT DMA2D_PF_RGB888 -# elif defined(CONFIG_STM32F7_DMA2D_ARGB8888) +# elif defined(CONFIG_STM32_DMA2D_ARGB8888) # define STM32_DMA2D_STRIDE ((STM32_DMA2D_WIDTH * 32 + 7) / 8) # define STM32_DMA2D_BPP 32 # define STM32_DMA2D_COLOR_FMT DMA2D_PF_ARGB8888 @@ -333,63 +333,63 @@ # error "DMA2D pixel format not supported" # endif -# ifdef CONFIG_STM32F7_DMA2D_LAYER_SHARED -# define STM32_DMA2D_FBSIZE CONFIG_STM32F7_DMA2D_FB_SIZE +# ifdef CONFIG_STM32_DMA2D_LAYER_SHARED +# define STM32_DMA2D_FBSIZE CONFIG_STM32_DMA2D_FB_SIZE # define STM32_DMA2D_LAYER_SIZE 0 # else -# define STM32_DMA2D_FBSIZE CONFIG_STM32F7_DMA2D_FB_SIZE / DMA2D_NLAYERS +# define STM32_DMA2D_FBSIZE CONFIG_STM32_DMA2D_FB_SIZE / DMA2D_NLAYERS # define STM32_DMA2D_LAYER_SIZE STM32_DMA2D_FBSIZE -# if STM32_DMA2D_FBSIZE * DMA2D_NLAYERS > CONFIG_STM32F7_DMA2D_FB_SIZE +# if STM32_DMA2D_FBSIZE * DMA2D_NLAYERS > CONFIG_STM32_DMA2D_FB_SIZE # error "DMA2D framebuffer size to small for configured number of overlays" # endif -# endif /* CONFIG_STM32F7_DMA2D_LAYER_SHARED */ +# endif /* CONFIG_STM32_DMA2D_LAYER_SHARED */ # define STM32_DMA2D_HEIGHT STM32_DMA2D_FBSIZE / STM32_DMA2D_STRIDE -# define STM32_DMA2D_BUFFER_START CONFIG_STM32F7_DMA2D_FB_BASE +# define STM32_DMA2D_BUFFER_START CONFIG_STM32_DMA2D_FB_BASE #else # define DMA2D_NLAYERS 0 -#endif /* CONFIG_STM32F7_DMA2D */ +#endif /* CONFIG_STM32_DMA2D */ #define LTDC_NOVERLAYS LTDC_NLAYERS + DMA2D_NLAYERS /* Dithering */ -#ifndef CONFIG_STM32F7_LTDC_DITHER_RED +#ifndef CONFIG_STM32_LTDC_DITHER_RED # define STM32_LTDC_DITHER_RED 0 #else -# define STM32_LTDC_DITHER_RED CONFIG_STM32F7_LTDC_DITHER_RED +# define STM32_LTDC_DITHER_RED CONFIG_STM32_LTDC_DITHER_RED #endif -#ifndef CONFIG_STM32F7_LTDC_DITHER_GREEN +#ifndef CONFIG_STM32_LTDC_DITHER_GREEN # define STM32_LTDC_DITHER_GREEN 0 #else -# define STM32_LTDC_DITHER_GREEN CONFIG_STM32F7_LTDC_DITHER_GREEN +# define STM32_LTDC_DITHER_GREEN CONFIG_STM32_LTDC_DITHER_GREEN #endif -#ifndef CONFIG_STM32F7_LTDC_DITHER_BLUE +#ifndef CONFIG_STM32_LTDC_DITHER_BLUE # define STM32_LTDC_DITHER_BLUE 0 #else -# define STM32_LTDC_DITHER_BLUE CONFIG_STM32F7_LTDC_DITHER_BLUE +# define STM32_LTDC_DITHER_BLUE CONFIG_STM32_LTDC_DITHER_BLUE #endif /* Background color */ -#ifndef CONFIG_STM32F7_LTDC_BACKCOLOR +#ifndef CONFIG_STM32_LTDC_BACKCOLOR # define STM32_LTDC_BACKCOLOR 0 #else -# define STM32_LTDC_BACKCOLOR CONFIG_STM32F7_LTDC_BACKCOLOR +# define STM32_LTDC_BACKCOLOR CONFIG_STM32_LTDC_BACKCOLOR #endif /* Layer default color */ -#ifdef CONFIG_STM32F7_LTDC_L1_COLOR -# define STM32_LTDC_L1_COLOR CONFIG_STM32F7_LTDC_L1_COLOR +#ifdef CONFIG_STM32_LTDC_L1_COLOR +# define STM32_LTDC_L1_COLOR CONFIG_STM32_LTDC_L1_COLOR #else # define STM32_LTDC_L1_COLOR 0x000000 #endif -#ifdef CONFIG_STM32F7_LTDC_L2 -# ifdef CONFIG_STM32F7_LTDC_L2_COLOR -# define STM32_LTDC_L2_COLOR CONFIG_STM32F7_LTDC_L2_COLOR +#ifdef CONFIG_STM32_LTDC_L2 +# ifdef CONFIG_STM32_LTDC_L2_COLOR +# define STM32_LTDC_L2_COLOR CONFIG_STM32_LTDC_L2_COLOR # else # define STM32_LTDC_L2_COLOR 0x000000 # endif @@ -423,28 +423,28 @@ /* Check pixel format support by DMA2D driver */ -#ifdef CONFIG_STM32F7_DMA2D -# if defined(CONFIG_STM32F7_LTDC_L1_L8) || \ - defined(CONFIG_STM32F7_LTDC_L2_L8) -# if !defined(CONFIG_STM32F7_DMA2D_L8) +#ifdef CONFIG_STM32_DMA2D +# if defined(CONFIG_STM32_LTDC_L1_L8) || \ + defined(CONFIG_STM32_LTDC_L2_L8) +# if !defined(CONFIG_STM32_DMA2D_L8) # error "DMA2D must support FB_FMT_RGB8 pixel format" # endif # endif -# if defined(CONFIG_STM32F7_LTDC_L1_RGB565) || \ - defined(CONFIG_STM32F7_LTDC_L2_RGB565) -# if !defined(CONFIG_STM32F7_DMA2D_RGB565) +# if defined(CONFIG_STM32_LTDC_L1_RGB565) || \ + defined(CONFIG_STM32_LTDC_L2_RGB565) +# if !defined(CONFIG_STM32_DMA2D_RGB565) # error "DMA2D must support FB_FMT_RGB16_565 pixel format" # endif # endif -# if defined(CONFIG_STM32F7_LTDC_L1_RGB888) || \ - defined(CONFIG_STM32F7_LTDC_L2_RGB888) -# if !defined(CONFIG_STM32F7_DMA2D_RGB888) +# if defined(CONFIG_STM32_LTDC_L1_RGB888) || \ + defined(CONFIG_STM32_LTDC_L2_RGB888) +# if !defined(CONFIG_STM32_DMA2D_RGB888) # error "DMA2D must support FB_FMT_RGB24 pixel format" # endif # endif -# if defined(CONFIG_STM32F7_LTDC_L1_ARGB8888) || \ - defined(CONFIG_STM32F7_LTDC_L2_ARGB8888) -# if !defined(CONFIG_STM32F7_DMA2D_ARGB8888) +# if defined(CONFIG_STM32_LTDC_L1_ARGB8888) || \ + defined(CONFIG_STM32_LTDC_L2_ARGB8888) +# if !defined(CONFIG_STM32_DMA2D_ARGB8888) # error "DMA2D must support FB_FMT_RGB32 pixel format" # endif # endif @@ -452,12 +452,12 @@ /* Calculate the size of the layers clut table */ -#ifdef CONFIG_STM32F7_FB_CMAP -# if defined(CONFIG_STM32F7_DMA2D) && !defined(CONFIG_STM32F7_DMA2D_L8) +#ifdef CONFIG_STM32_FB_CMAP +# if defined(CONFIG_STM32_DMA2D) && !defined(CONFIG_STM32_DMA2D_L8) # error "DMA2D must also support L8 CLUT pixel format if supported by LTDC" # endif # ifdef STM32_LTDC_L1CMAP -# ifdef CONFIG_STM32F7_FB_TRANSPARENCY +# ifdef CONFIG_STM32_FB_TRANSPARENCY # define STM32_LAYER_CLUT_SIZE STM32_LTDC_NCLUT * sizeof(uint32_t) # else # define STM32_LAYER_CLUT_SIZE STM32_LTDC_NCLUT * 3 * sizeof(uint8_t) @@ -465,7 +465,7 @@ # endif # ifdef STM32_LTDC_L2CMAP # undef STM32_LAYER_CLUT_SIZE -# ifdef CONFIG_STM32F7_FB_TRANSPARENCY +# ifdef CONFIG_STM32_FB_TRANSPARENCY # define STM32_LAYER_CLUT_SIZE STM32_LTDC_NCLUT * sizeof(uint32_t) * 2 # else # define STM32_LAYER_CLUT_SIZE STM32_LTDC_NCLUT * 3 * sizeof(uint8_t) * 2 @@ -473,7 +473,7 @@ # endif #endif -#ifndef CONFIG_STM32F7_FB_CMAP +#ifndef CONFIG_STM32_FB_CMAP # if defined(STM32_LTDC_L1CMAP) || defined(STM32_LTDC_L2CMAP) # undef STM32_LTDC_L1CMAP # undef STM32_LTDC_L2CMAP @@ -510,9 +510,9 @@ /* Acceleration support for LTDC overlays */ -#ifdef CONFIG_STM32F7_LTDC_L1_CHROMAKEYEN +#ifdef CONFIG_STM32_LTDC_L1_CHROMAKEYEN # define STM32_LTDC_L1_CHROMAEN true -# define STM32_LTDC_L1_CHROMAKEY CONFIG_STM32F7_LTDC_L1_CHROMAKEY +# define STM32_LTDC_L1_CHROMAKEY CONFIG_STM32_LTDC_L1_CHROMAKEY # define LTDC_LTDC_ACCL_L1 FB_ACCL_TRANSP | FB_ACCL_CHROMA #else # define STM32_LTDC_L1_CHROMAEN false @@ -520,9 +520,9 @@ # define LTDC_LTDC_ACCL_L1 FB_ACCL_TRANSP #endif -#ifdef CONFIG_STM32F7_LTDC_L2_CHROMAKEYEN +#ifdef CONFIG_STM32_LTDC_L2_CHROMAKEYEN # define STM32_LTDC_L2_CHROMAEN true -# define STM32_LTDC_L2_CHROMAKEY CONFIG_STM32F7_LTDC_L2_CHROMAKEY +# define STM32_LTDC_L2_CHROMAKEY CONFIG_STM32_LTDC_L2_CHROMAKEY # define LTDC_LTDC_ACCL_L2 FB_ACCL_TRANSP | FB_ACCL_CHROMA #else # define STM32_LTDC_L2_CHROMAEN false @@ -530,34 +530,34 @@ # define LTDC_LTDC_ACCL_L2 FB_ACCL_TRANSP #endif -#ifdef CONFIG_STM32F7_DMA2D +#ifdef CONFIG_STM32_DMA2D # ifdef CONFIG_FB_OVERLAY_BLIT -# ifdef CONFIG_STM32F7_FB_CMAP +# ifdef CONFIG_STM32_FB_CMAP # define LTDC_BLIT_ACCL FB_ACCL_BLIT # else # define LTDC_BLIT_ACCL FB_ACCL_BLIT | FB_ACCL_BLEND -# endif /* CONFIG_STM32F7_FB_CMAP */ +# endif /* CONFIG_STM32_FB_CMAP */ # else # define LTDC_BLIT_ACCL 0 # endif /* CONFIG_FB_OVERLAY_BLIT */ -# ifdef CONFIG_STM32F7_FB_CMAP +# ifdef CONFIG_STM32_FB_CMAP # define LTDC_DMA2D_ACCL LTDC_BLIT_ACCL # else # define LTDC_DMA2D_ACCL FB_ACCL_COLOR | LTDC_BLIT_ACCL -# endif /* CONFIG_STM32F7_FB_CMAP */ +# endif /* CONFIG_STM32_FB_CMAP */ #else # define LTDC_DMA2D_ACCL 0 -#endif /* CONFIG_STM32F7_DMA2D */ +#endif /* CONFIG_STM32_DMA2D */ #define LTDC_L1_ACCL LTDC_LTDC_ACCL_L1 | LTDC_DMA2D_ACCL -#ifdef CONFIG_STM32F7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 # define LTDC_L2_ACCL LTDC_LTDC_ACCL_L2 | LTDC_DMA2D_ACCL #endif /* Acceleration support for DMA2D overlays */ -#ifdef CONFIG_STM32F7_FB_CMAP +#ifdef CONFIG_STM32_FB_CMAP # ifdef CONFIG_FB_OVERLAY_BLIT # define DMA2D_ACCL FB_ACCL_BLIT | FB_ACCL_AREA # else @@ -579,7 +579,7 @@ /* Color normalization */ -#if defined(CONFIG_STM32F7_LTDC_L1_RGB565) +#if defined(CONFIG_STM32_LTDC_L1_RGB565) # define RGB888_R(x) (((((x) >> 11) & 0x1f) * 527 + 23) >> 6) # define RGB888_G(x) (((((x) >> 5) & 0x3f) * 259 + 33) >> 6) # define RGB888_B(x) ((((x) & 0x1f) * 527 + 23) >> 6) @@ -612,7 +612,7 @@ struct stm32_ltdc_s struct fb_overlayinfo_s oinfo; /* Overlay info */ #endif -#ifdef CONFIG_STM32F7_DMA2D +#ifdef CONFIG_STM32_DMA2D struct stm32_dma2d_overlay_s dma2dinfo; /* Overlay info for DMA2D */ #endif @@ -637,7 +637,7 @@ struct stm32_ltdcdev_s /* Cmap information */ -#ifdef CONFIG_STM32F7_FB_CMAP +#ifdef CONFIG_STM32_FB_CMAP struct fb_cmap_s cmap; #endif @@ -645,7 +645,7 @@ struct stm32_ltdcdev_s struct stm32_ltdc_s layer[LTDC_NOVERLAYS]; -#ifdef CONFIG_STM32F7_DMA2D +#ifdef CONFIG_STM32_DMA2D /* Interface to the dma2d controller */ struct dma2d_layer_s *dma2d; @@ -693,7 +693,7 @@ static void stm32_ltdc_lchromakeyenable(struct stm32_ltdc_s *layer, bool enable); static void stm32_ltdc_linit(uint8_t lid); -#ifdef CONFIG_STM32F7_DMA2D +#ifdef CONFIG_STM32_DMA2D static void stm32_ltdc_dma2dlinit(void); # ifdef CONFIG_FB_OVERLAY_BLIT @@ -702,7 +702,7 @@ static bool stm32_ltdc_lvalidate(const struct stm32_ltdc_s *layer, # endif #endif -#ifdef CONFIG_STM32F7_FB_CMAP +#ifdef CONFIG_STM32_FB_CMAP static void stm32_ltdc_lputclut(struct stm32_ltdc_s *layer, const struct fb_cmap_s *cmap); static void stm32_ltdc_lgetclut(struct stm32_ltdc_s *layer, @@ -725,7 +725,7 @@ static int stm32_getplaneinfo(struct fb_vtable_s *vtable, * mapping */ -#ifdef CONFIG_STM32F7_FB_CMAP +#ifdef CONFIG_STM32_FB_CMAP static int stm32_getcmap(struct fb_vtable_s *vtable, struct fb_cmap_s *cmap); static int stm32_putcmap(struct fb_vtable_s *vtable, @@ -795,16 +795,16 @@ static const uint32_t g_ltdcpins[] = #define STM32_LTDC_NPINCONFIGS (sizeof(g_ltdcpins) / sizeof(uint32_t)) -#ifdef CONFIG_STM32F7_FB_CMAP +#ifdef CONFIG_STM32_FB_CMAP /* The layers clut table entries */ static uint8_t g_redclut[STM32_LTDC_NCLUT]; static uint8_t g_greenclut[STM32_LTDC_NCLUT]; static uint8_t g_blueclut[STM32_LTDC_NCLUT]; -# ifdef CONFIG_STM32F7_FB_TRANSPARENCY +# ifdef CONFIG_STM32_FB_TRANSPARENCY static uint8_t g_transpclut[STM32_LTDC_NCLUT]; # endif -#endif /* CONFIG_STM32F7_FB_CMAP */ +#endif /* CONFIG_STM32_FB_CMAP */ /* The LTDC mutex that enforces mutually exclusive access */ @@ -836,7 +836,7 @@ static struct stm32_ltdcdev_s g_vtable = .waitforvsync = stm32_waitforvsync #endif -#ifdef CONFIG_STM32F7_FB_CMAP +#ifdef CONFIG_STM32_FB_CMAP , .getcmap = stm32_getcmap, .putcmap = stm32_putcmap @@ -857,7 +857,7 @@ static struct stm32_ltdcdev_s g_vtable = # endif #endif /* CONFIG_FB_OVERLAY */ }, -#ifdef CONFIG_STM32F7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 .pinfo = { .fbmem = (uint8_t *)STM32_LTDC_BUFFER_L2, @@ -895,9 +895,9 @@ static struct stm32_ltdcdev_s g_vtable = .noverlays = LTDC_NOVERLAYS # endif } -#endif /* CONFIG_STM32F7_LTDC_L2 */ +#endif /* CONFIG_STM32_LTDC_L2 */ , -#ifdef CONFIG_STM32F7_FB_CMAP +#ifdef CONFIG_STM32_FB_CMAP .cmap = { .first = 0, @@ -905,7 +905,7 @@ static struct stm32_ltdcdev_s g_vtable = .red = g_redclut, .green = g_greenclut, .blue = g_blueclut, -# ifdef CONFIG_STM32F7_FB_TRANSPARENCY +# ifdef CONFIG_STM32_FB_TRANSPARENCY .transp = g_transpclut # endif } @@ -941,7 +941,7 @@ static struct stm32_ltdcdev_s g_vtable = }, #endif -#ifdef CONFIG_STM32F7_DMA2D +#ifdef CONFIG_STM32_DMA2D .dma2dinfo = { .fmt = STM32_LTDC_L1_DMA2D_PF, @@ -953,7 +953,7 @@ static struct stm32_ltdcdev_s g_vtable = #endif .lock = &g_lock } -#ifdef CONFIG_STM32F7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 , .layer[LTDC_LAYER_L2] = { @@ -985,7 +985,7 @@ static struct stm32_ltdcdev_s g_vtable = }, #endif -#ifdef CONFIG_STM32F7_DMA2D +#ifdef CONFIG_STM32_DMA2D .dma2dinfo = { .fmt = STM32_LTDC_L2_DMA2D_PF, @@ -1007,7 +1007,7 @@ static struct stm32_ltdcdev_s g_vtable = static const uint32_t stm32_width_layer_t[LTDC_NLAYERS] = { STM32_LTDC_WIDTH -#ifdef CONFIG_STM32F7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 , STM32_LTDC_WIDTH #endif }; @@ -1017,7 +1017,7 @@ static const uint32_t stm32_width_layer_t[LTDC_NLAYERS] = static const uint32_t stm32_height_layer_t[LTDC_NLAYERS] = { STM32_LTDC_HEIGHT -#ifdef CONFIG_STM32F7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 , STM32_LTDC_HEIGHT #endif }; @@ -1027,7 +1027,7 @@ static const uint32_t stm32_height_layer_t[LTDC_NLAYERS] = static const uint32_t stm32_stride_layer_t[LTDC_NLAYERS] = { STM32_LTDC_L1_STRIDE -#ifdef CONFIG_STM32F7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 , STM32_LTDC_L2_STRIDE #endif }; @@ -1037,7 +1037,7 @@ static const uint32_t stm32_stride_layer_t[LTDC_NLAYERS] = static const uint32_t stm32_bpp_layer_t[LTDC_NLAYERS] = { STM32_LTDC_L1_BPP -#ifdef CONFIG_STM32F7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 , STM32_LTDC_L2_BPP #endif }; @@ -1047,7 +1047,7 @@ static const uint32_t stm32_bpp_layer_t[LTDC_NLAYERS] = static const uint32_t stm32_fblen_layer_t[LTDC_NLAYERS] = { STM32_LTDC_L1_FBSIZE -#ifdef CONFIG_STM32F7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 , STM32_LTDC_L2_FBSIZE #endif }; @@ -1057,7 +1057,7 @@ static const uint32_t stm32_fblen_layer_t[LTDC_NLAYERS] = static const uint32_t stm32_fbmem_layer_t[LTDC_NLAYERS] = { STM32_LTDC_BUFFER_L1 -#ifdef CONFIG_STM32F7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 , STM32_LTDC_BUFFER_L2 #endif }; @@ -1067,7 +1067,7 @@ static const uint32_t stm32_fbmem_layer_t[LTDC_NLAYERS] = static const uint32_t stm32_defaultcolor_layer_t[LTDC_NLAYERS] = { STM32_LTDC_L1_COLOR -#ifdef CONFIG_STM32F7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 , STM32_LTDC_L2_COLOR #endif }; @@ -1077,7 +1077,7 @@ static const uint32_t stm32_defaultcolor_layer_t[LTDC_NLAYERS] = static const uint32_t stm32_chromakey_layer_t[LTDC_NLAYERS] = { STM32_LTDC_L1_CHROMAKEY -#ifdef CONFIG_STM32F7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 , STM32_LTDC_L2_CHROMAKEY #endif }; @@ -1087,7 +1087,7 @@ static const uint32_t stm32_chromakey_layer_t[LTDC_NLAYERS] = static const bool stm32_chromakeyen_layer_t[LTDC_NLAYERS] = { STM32_LTDC_L1_CHROMAEN -#ifdef CONFIG_STM32F7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 , STM32_LTDC_L2_CHROMAEN #endif }; @@ -1097,7 +1097,7 @@ static const bool stm32_chromakeyen_layer_t[LTDC_NLAYERS] = static const uint32_t stm32_fmt_layer_t[LTDC_NLAYERS] = { STM32_LTDC_L1PFCR_PF -#ifdef CONFIG_STM32F7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 , STM32_LTDC_L2PFCR_PF #endif }; @@ -1109,7 +1109,7 @@ static const uint32_t stm32_fmt_layer_t[LTDC_NLAYERS] = static const uintptr_t stm32_cr_layer_t[LTDC_NLAYERS] = { STM32_LTDC_L1CR -#ifdef CONFIG_STM32F7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 , STM32_LTDC_L2CR #endif }; @@ -1119,7 +1119,7 @@ static const uintptr_t stm32_cr_layer_t[LTDC_NLAYERS] = static const uintptr_t stm32_whpcr_layer_t[LTDC_NLAYERS] = { STM32_LTDC_L1WHPCR -#ifdef CONFIG_STM32F7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 , STM32_LTDC_L2WHPCR #endif }; @@ -1129,7 +1129,7 @@ static const uintptr_t stm32_whpcr_layer_t[LTDC_NLAYERS] = static const uintptr_t stm32_wvpcr_layer_t[LTDC_NLAYERS] = { STM32_LTDC_L1WVPCR -#ifdef CONFIG_STM32F7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 , STM32_LTDC_L2WVPCR #endif }; @@ -1139,7 +1139,7 @@ static const uintptr_t stm32_wvpcr_layer_t[LTDC_NLAYERS] = static const uintptr_t stm32_pfcr_layer_t[LTDC_NLAYERS] = { STM32_LTDC_L1PFCR -#ifdef CONFIG_STM32F7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 , STM32_LTDC_L2PFCR #endif }; @@ -1149,7 +1149,7 @@ static const uintptr_t stm32_pfcr_layer_t[LTDC_NLAYERS] = static const uintptr_t stm32_dccr_layer_t[LTDC_NLAYERS] = { STM32_LTDC_L1DCCR -#ifdef CONFIG_STM32F7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 , STM32_LTDC_L2DCCR #endif }; @@ -1159,7 +1159,7 @@ static const uintptr_t stm32_dccr_layer_t[LTDC_NLAYERS] = static const uintptr_t stm32_ckcr_layer_t[LTDC_NLAYERS] = { STM32_LTDC_L1CKCR -#ifdef CONFIG_STM32F7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 , STM32_LTDC_L2CKCR #endif }; @@ -1169,7 +1169,7 @@ static const uintptr_t stm32_ckcr_layer_t[LTDC_NLAYERS] = static const uintptr_t stm32_cacr_layer_t[LTDC_NLAYERS] = { STM32_LTDC_L1CACR -#ifdef CONFIG_STM32F7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 , STM32_LTDC_L2CACR #endif }; @@ -1179,7 +1179,7 @@ static const uintptr_t stm32_cacr_layer_t[LTDC_NLAYERS] = static const uintptr_t stm32_bfcr_layer_t[LTDC_NLAYERS] = { STM32_LTDC_L1BFCR -#ifdef CONFIG_STM32F7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 , STM32_LTDC_L2BFCR #endif }; @@ -1189,7 +1189,7 @@ static const uintptr_t stm32_bfcr_layer_t[LTDC_NLAYERS] = static const uintptr_t stm32_cfbar_layer_t[LTDC_NLAYERS] = { STM32_LTDC_L1CFBAR -#ifdef CONFIG_STM32F7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 , STM32_LTDC_L2CFBAR #endif }; @@ -1199,7 +1199,7 @@ static const uintptr_t stm32_cfbar_layer_t[LTDC_NLAYERS] = static const uintptr_t stm32_cfblr_layer_t[LTDC_NLAYERS] = { STM32_LTDC_L1CFBLR -#ifdef CONFIG_STM32F7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 , STM32_LTDC_L2CFBLR #endif }; @@ -1209,22 +1209,22 @@ static const uintptr_t stm32_cfblr_layer_t[LTDC_NLAYERS] = static const uintptr_t stm32_cfblnr_layer_t[LTDC_NLAYERS] = { STM32_LTDC_L1CFBLNR -#ifdef CONFIG_STM32F7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 , STM32_LTDC_L2CFBLNR #endif }; /* LTDC_LxCLUTWR */ -#ifdef CONFIG_STM32F7_FB_CMAP +#ifdef CONFIG_STM32_FB_CMAP static const uintptr_t stm32_clutwr_layer_t[LTDC_NLAYERS] = { STM32_LTDC_L1CLUTWR -# ifdef CONFIG_STM32F7_LTDC_L2 +# ifdef CONFIG_STM32_LTDC_L2 , STM32_LTDC_L2CLUTWR # endif }; -#endif /* CONFIG_STM32F7_FB_CMAP */ +#endif /* CONFIG_STM32_FB_CMAP */ /* The initialized state of the driver */ @@ -1648,7 +1648,7 @@ static void stm32_ltdc_globalconfig(void) /* Configure dither */ stm32_ltdc_dither( -#ifdef CONFIG_STM32F7_LTDC_DITHER +#ifdef CONFIG_STM32_LTDC_DITHER true, #else false, @@ -1920,7 +1920,7 @@ static void stm32_ltdc_lchromakey(struct stm32_ltdc_s *layer, /* Set chromakey */ -#ifdef CONFIG_STM32F7_FB_CMAP +#ifdef CONFIG_STM32_FB_CMAP uint8_t r = g_vtable.cmap.red[chroma]; uint8_t g = g_vtable.cmap.green[chroma]; uint8_t b = g_vtable.cmap.blue[chroma]; @@ -1990,7 +1990,7 @@ static void stm32_ltdc_lchromakeyenable(struct stm32_ltdc_s *layer, * ****************************************************************************/ -#ifdef CONFIG_STM32F7_FB_CMAP +#ifdef CONFIG_STM32_FB_CMAP static void stm32_ltdc_lclutenable(struct stm32_ltdc_s *layer, bool enable) { @@ -2095,7 +2095,7 @@ static void stm32_ltdc_lgetclut(struct stm32_ltdc_s *layer, for (n = cmap->first; n < cmap->len && n < STM32_LTDC_NCLUT; n++) { -# ifdef CONFIG_STM32F7_FB_TRANSPARENCY +# ifdef CONFIG_STM32_FB_TRANSPARENCY cmap->transp[n] = priv_cmap->transp[n]; # endif cmap->red[n] = priv_cmap->red[n]; @@ -2104,7 +2104,7 @@ static void stm32_ltdc_lgetclut(struct stm32_ltdc_s *layer, reginfo("color = %d, transp=%02x, red=%02x, green=%02x, blue=%02x\n", n, -# ifdef CONFIG_STM32F7_FB_TRANSPARENCY +# ifdef CONFIG_STM32_FB_TRANSPARENCY cmap->transp[n], # endif cmap->red[n], @@ -2112,7 +2112,7 @@ static void stm32_ltdc_lgetclut(struct stm32_ltdc_s *layer, cmap->blue[n]); } } -#endif /* CONFIG_STM32F7_FB_CMAP */ +#endif /* CONFIG_STM32_FB_CMAP */ /**************************************************************************** * Name: stm32_ltdc_lclear @@ -2144,7 +2144,7 @@ static void stm32_ltdc_lclear(uint8_t overlayno) * ****************************************************************************/ -#if defined(CONFIG_STM32F7_DMA2D) && defined(CONFIG_FB_OVERLAY_BLIT) +#if defined(CONFIG_STM32_DMA2D) && defined(CONFIG_FB_OVERLAY_BLIT) static bool stm32_ltdc_lvalidate(const struct stm32_ltdc_s *layer, const struct fb_area_s *area) { @@ -2155,7 +2155,7 @@ static bool stm32_ltdc_lvalidate(const struct stm32_ltdc_s *layer, return (offset <= layer->oinfo.fblen && area->w > 0 && area->h > 0); } -#endif /* defined(CONFIG_STM32F7_DMA2D) && defined(CONFIG_FB_OVERLAY_BLIT) */ +#endif /* defined(CONFIG_STM32_DMA2D) && defined(CONFIG_FB_OVERLAY_BLIT) */ /**************************************************************************** * Name: stm32_ltdc_linit @@ -2215,7 +2215,7 @@ static void stm32_ltdc_linit(uint8_t overlay) stm32_ltdc_lchromakeyenable(layer, stm32_chromakeyen_layer_t[overlay]); -#ifdef CONFIG_STM32F7_FB_CMAP +#ifdef CONFIG_STM32_FB_CMAP /* Disable clut by default */ if (dev->vinfo.fmt == FB_FMT_RGB8) @@ -2255,7 +2255,7 @@ static void stm32_ltdc_linit(uint8_t overlay) * ****************************************************************************/ -#ifdef CONFIG_STM32F7_DMA2D +#ifdef CONFIG_STM32_DMA2D static void stm32_ltdc_dma2dlinit(void) { int n; @@ -2291,7 +2291,7 @@ static void stm32_ltdc_dma2dlinit(void) layer->dma2dinfo.oinfo = &layer->oinfo; } } -#endif /* CONFIG_STM32F7_DMA2D */ +#endif /* CONFIG_STM32_DMA2D */ /**************************************************************************** * Public Functions @@ -2378,7 +2378,7 @@ static int stm32_getplaneinfo(struct fb_vtable_s *vtable, int planeno, * ****************************************************************************/ -#ifdef CONFIG_STM32F7_FB_CMAP +#ifdef CONFIG_STM32_FB_CMAP static int stm32_getcmap(struct fb_vtable_s *vtable, struct fb_cmap_s *cmap) { @@ -2408,7 +2408,7 @@ static int stm32_getcmap(struct fb_vtable_s *vtable, */ struct stm32_ltdc_s *layer; -# ifdef CONFIG_STM32F7_LTDC_L2 +# ifdef CONFIG_STM32_LTDC_L2 layer = &priv->layer[LTDC_LAYER_L2]; # else layer = &priv->layer[LTDC_LAYER_L1]; @@ -2478,7 +2478,7 @@ static int stm32_putcmap(struct fb_vtable_s *vtable, priv_cmap->red[n] = cmap->red[n]; priv_cmap->green[n] = cmap->green[n]; priv_cmap->blue[n] = cmap->blue[n]; -# ifdef CONFIG_STM32F7_FB_TRANSPARENCY +# ifdef CONFIG_STM32_FB_TRANSPARENCY /* Not supported by LTDC */ priv_cmap->transp[n] = cmap->transp[n]; @@ -2498,7 +2498,7 @@ static int stm32_putcmap(struct fb_vtable_s *vtable, stm32_ltdc_lputclut(layer, priv_cmap); } -# ifdef CONFIG_STM32F7_DMA2D +# ifdef CONFIG_STM32_DMA2D /* Update dma2d cmap */ priv->dma2d->setclut(cmap); @@ -2510,7 +2510,7 @@ static int stm32_putcmap(struct fb_vtable_s *vtable, return ret; } -#endif /* CONFIG_STM32F7_FB_CMAP */ +#endif /* CONFIG_STM32_FB_CMAP */ /**************************************************************************** * Name: stm32_ioctl_waitforvsync @@ -2589,7 +2589,7 @@ static int stm32_settransp(struct fb_vtable_s *vtable, layer->oinfo.transp.transp = oinfo->transp.transp; layer->oinfo.transp.transp_mode = oinfo->transp.transp_mode; -# ifdef CONFIG_STM32F7_DMA2D +# ifdef CONFIG_STM32_DMA2D if (layer->oinfo.transp.transp_mode == 0) { layer->dma2dinfo.transp_mode = STM32_DMA2D_PFCCR_AM_CONST; @@ -2636,14 +2636,14 @@ static int stm32_setchromakey(struct fb_vtable_s *vtable, int ret; struct stm32_ltdc_s *layer = &priv->layer[oinfo->overlay]; -# ifndef CONFIG_STM32F7_LTDC_L1_CHROMAKEY +# ifndef CONFIG_STM32_LTDC_L1_CHROMAKEY if (oinfo->overlay == LTDC_LAYER_L1) { return -ENOSYS; } # endif -# ifndef CONFIG_STM32F7_LTDC_L2_CHROMAKEY +# ifndef CONFIG_STM32_LTDC_L2_CHROMAKEY if (oinfo->overlay == LTDC_LAYER_L2) { return -ENOSYS; @@ -2651,7 +2651,7 @@ static int stm32_setchromakey(struct fb_vtable_s *vtable, # endif nxmutex_lock(layer->lock); -# ifdef CONFIG_STM32F7_FB_CMAP +# ifdef CONFIG_STM32_FB_CMAP if (oinfo->chromakey >= g_vtable.cmap.len) { lcderr("ERROR: Clut index %d is out of range\n", oinfo->chromakey); @@ -2671,7 +2671,7 @@ static int stm32_setchromakey(struct fb_vtable_s *vtable, nxmutex_unlock(layer->lock); return ret; } -# ifdef CONFIG_STM32F7_DMA2D +# ifdef CONFIG_STM32_DMA2D else if (oinfo->overlay < LTDC_NOVERLAYS) { /* Chromakey not supported by DMA2D */ @@ -2699,7 +2699,7 @@ static int stm32_setcolor(struct fb_vtable_s *vtable, if (oinfo->overlay < LTDC_NOVERLAYS) { -# ifdef CONFIG_STM32F7_DMA2D +# ifdef CONFIG_STM32_DMA2D /* Set color within the active overlay is not supported by LTDC. So use * DMA2D controller instead when configured. @@ -2760,7 +2760,7 @@ static int stm32_setblank(struct fb_vtable_s *vtable, return OK; } -# ifdef CONFIG_STM32F7_DMA2D +# ifdef CONFIG_STM32_DMA2D else if (oinfo->overlay < LTDC_NOVERLAYS) { /* DMA2D overlays are non visible */ @@ -2794,7 +2794,7 @@ static int stm32_setarea(struct fb_vtable_s *vtable, return -ENOSYS; } -# ifdef CONFIG_STM32F7_DMA2D +# ifdef CONFIG_STM32_DMA2D if (oinfo->overlay < LTDC_NOVERLAYS) { struct stm32_ltdcdev_s *priv = @@ -2830,7 +2830,7 @@ static int stm32_blit(struct fb_vtable_s *vtable, if (blit->dest.overlay < LTDC_NOVERLAYS && blit->src.overlay < LTDC_NOVERLAYS) { -# ifdef CONFIG_STM32F7_DMA2D +# ifdef CONFIG_STM32_DMA2D int ret; struct fb_area_s sarea; const struct fb_area_s *darea = &blit->dest.area; @@ -2892,7 +2892,7 @@ static int stm32_blend(struct fb_vtable_s *vtable, blend->foreground.overlay < LTDC_NOVERLAYS && blend->background.overlay < LTDC_NOVERLAYS) { -# ifdef CONFIG_STM32F7_DMA2D +# ifdef CONFIG_STM32_DMA2D int ret; struct fb_area_s barea; const struct fb_area_s *darea = &blend->dest.area; @@ -3006,7 +3006,7 @@ int stm32_ltdcinitialize(void) lcdinfo("Configure global register\n"); stm32_ltdc_globalconfig(); -#ifdef CONFIG_STM32F7_DMA2D +#ifdef CONFIG_STM32_DMA2D /* Initialize the dma2d controller */ ret = stm32_dma2dinitialize(); @@ -3022,31 +3022,31 @@ int stm32_ltdcinitialize(void) DEBUGASSERT(g_vtable.dma2d != NULL); #endif -#ifdef CONFIG_STM32F7_FB_CMAP +#ifdef CONFIG_STM32_FB_CMAP /* Cleanup clut */ memset(&g_redclut, 0, STM32_LTDC_NCLUT); memset(&g_blueclut, 0, STM32_LTDC_NCLUT); memset(&g_greenclut, 0, STM32_LTDC_NCLUT); -# ifdef CONFIG_STM32F7_FB_TRANSPARENCY +# ifdef CONFIG_STM32_FB_TRANSPARENCY memset(&g_transpclut, 0, STM32_LTDC_NCLUT); # endif -#endif /* CONFIG_STM32F7_FB_CMAP */ +#endif /* CONFIG_STM32_FB_CMAP */ /* Initialize ltdc layer */ lcdinfo("Initialize ltdc layer\n"); stm32_ltdc_linit(LTDC_LAYER_L1); -#ifdef CONFIG_STM32F7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 stm32_ltdc_linit(LTDC_LAYER_L2); #endif -#ifdef CONFIG_STM32F7_DMA2D +#ifdef CONFIG_STM32_DMA2D stm32_ltdc_dma2dlinit(); #endif /* Enable the backlight */ -#ifdef CONFIG_STM32F7_LCD_BACKLIGHT +#ifdef CONFIG_STM32_LCD_BACKLIGHT stm32_backlight(true); #endif @@ -3132,10 +3132,10 @@ void stm32_ltdcuninitialize(void) * ****************************************************************************/ -#ifdef CONFIG_STM32F7_LCD_BACKLIGHT +#ifdef CONFIG_STM32_LCD_BACKLIGHT void stm32_backlight(bool blon) { - /* Set default backlight level CONFIG_STM32F7_LTDC_DEFBACKLIGHT */ + /* Set default backlight level CONFIG_STM32_LTDC_DEFBACKLIGHT */ lcderr("ERROR: Not supported\n"); } diff --git a/arch/arm/src/stm32f7/stm32_ltdc.h b/arch/arm/src/stm32f7/stm32_ltdc.h index d7a432a01cdac..420be63b38599 100644 --- a/arch/arm/src/stm32f7/stm32_ltdc.h +++ b/arch/arm/src/stm32f7/stm32_ltdc.h @@ -91,12 +91,12 @@ struct fb_vtable_s *stm32_ltdcgetvplane(int vplane); * Name: stm32_lcd_backlight * * Description: - * If CONFIG_STM32F7_LCD_BACKLIGHT is defined, then the board-specific + * If CONFIG_STM32_LCD_BACKLIGHT is defined, then the board-specific * logic must provide this interface to turn the backlight on and off. * ****************************************************************************/ -#ifdef CONFIG_STM32F7_LCD_BACKLIGHT +#ifdef CONFIG_STM32_LCD_BACKLIGHT void stm32_backlight(bool blon); #endif #endif /* __ARCH_ARM_SRC_STM32F7_STM32_LTDC_H */ diff --git a/arch/arm/src/stm32f7/stm32_otg.h b/arch/arm/src/stm32f7/stm32_otg.h index a0d5426727863..9b146f21e61da 100644 --- a/arch/arm/src/stm32f7/stm32_otg.h +++ b/arch/arm/src/stm32f7/stm32_otg.h @@ -34,7 +34,7 @@ #include "chip.h" #include "hardware/stm32_otg.h" -#if defined(CONFIG_STM32F7_OTGFS) || defined(CONFIG_STM32F7_OTGFSHS) +#if defined(CONFIG_STM32_OTGFS) || defined(CONFIG_STM32_OTGFSHS) /**************************************************************************** * Pre-processor Definitions @@ -46,7 +46,7 @@ # define CONFIG_OTG_PRI NVIC_SYSH_PRIORITY_DEFAULT #endif -#if defined(CONFIG_STM32F7_OTGFS) +#if defined(CONFIG_STM32_OTGFS) # define STM32_IRQ_OTG STM32_IRQ_OTGFS # define STM32_OTG_BASE STM32_USBOTGFS_BASE # define STM32_NENDPOINTS (6) /* ep0-5 x 2 for IN and OUT */ @@ -58,7 +58,7 @@ # define STM32_OTG_FIFO_SIZE 1280 #endif -#if defined(CONFIG_STM32F7_OTGFSHS) +#if defined(CONFIG_STM32_OTGFSHS) # define STM32_IRQ_OTG STM32_IRQ_OTGHS # define STM32_OTG_BASE STM32_USBOTGHS_BASE # define STM32_NENDPOINTS (7) /* ep0-8 x 2 for IN and OUT but driver internals use byte to map + one bit for direction */ @@ -135,5 +135,5 @@ void stm32_usbsuspend(struct usbdev_s *dev, bool resume); #endif #endif /* __ASSEMBLY__ */ -#endif /* CONFIG_STM32F7_OTGFS */ +#endif /* CONFIG_STM32_OTGFS */ #endif /* __ARCH_ARM_SRC_STM32F7_STM32_OTG_H */ diff --git a/arch/arm/src/stm32f7/stm32_otgdev.c b/arch/arm/src/stm32f7/stm32_otgdev.c index 7a1fe72b80c97..96be757e9e3f9 100644 --- a/arch/arm/src/stm32f7/stm32_otgdev.c +++ b/arch/arm/src/stm32f7/stm32_otgdev.c @@ -52,8 +52,8 @@ #include "stm32_rcc.h" #include "arm_internal.h" -#if defined(CONFIG_USBDEV) && (defined(CONFIG_STM32F7_OTGFS) || \ - defined(CONFIG_STM32F7_OTGFSHS)) +#if defined(CONFIG_USBDEV) && (defined(CONFIG_STM32_OTGFS) || \ + defined(CONFIG_STM32_OTGFSHS)) /**************************************************************************** * Pre-processor Definitions @@ -254,7 +254,7 @@ * present */ -# ifdef CONFIG_STM32F7_OTGFSHS +# ifdef CONFIG_STM32_OTGFSHS # define OTG_GINT_RESERVED OTG_GINT_RESERVED_HS # define OTG_GINT_RC_W1 OTG_GINT_RC_W1_HS # else @@ -373,7 +373,7 @@ /* Maximum packet sizes for full speed endpoints */ -# ifdef CONFIG_STM32F7_OTGFSHS +# ifdef CONFIG_STM32_OTGFSHS # define STM32_MAXPACKET (512) /* Max packet size (1-512) */ # else # define STM32_MAXPACKET (64) /* Max packet size (1-64) */ @@ -573,7 +573,7 @@ struct stm32_usbdev_s /* Register operations ******************************************************/ -# if defined(CONFIG_STM32F7_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES) +# if defined(CONFIG_STM32_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES) static uint32_t stm32_getreg(uint32_t addr); static void stm32_putreg(uint32_t val, uint32_t addr); # else @@ -898,7 +898,7 @@ const struct trace_msg_t g_usb_trace_strings_intdecode[] = * ****************************************************************************/ -# if defined(CONFIG_STM32F7_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES) +# if defined(CONFIG_STM32_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES) static uint32_t stm32_getreg(uint32_t addr) { static uint32_t prevaddr = 0; @@ -961,7 +961,7 @@ static uint32_t stm32_getreg(uint32_t addr) * ****************************************************************************/ -# if defined(CONFIG_STM32F7_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES) +# if defined(CONFIG_STM32_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES) static void stm32_putreg(uint32_t val, uint32_t addr) { /* Show the register value being written */ @@ -2163,7 +2163,7 @@ static void stm32_usbreset(struct stm32_usbdev_s *priv) stm32_setaddress(priv, 0); priv->devstate = DEVSTATE_DEFAULT; -# if defined(CONFIG_STM32F7_INTERNAL_ULPI) || defined(CONFIG_STM32F7_EXTERNAL_ULPI) +# if defined(CONFIG_STM32_INTERNAL_ULPI) || defined(CONFIG_STM32_EXTERNAL_ULPI) priv->usbdev.speed = USB_SPEED_HIGH; # else priv->usbdev.speed = USB_SPEED_FULL; @@ -3461,7 +3461,7 @@ static inline void stm32_enuminterrupt(struct stm32_usbdev_s *priv) regval = stm32_getreg(STM32_OTG_GUSBCFG); regval &= ~OTG_GUSBCFG_TRDT_MASK; -# ifdef CONFIG_STM32F7_OTGFSHS +# ifdef CONFIG_STM32_OTGFSHS regval |= OTG_GUSBCFG_TRDT(9); # else regval |= OTG_GUSBCFG_TRDT(6); @@ -5345,15 +5345,15 @@ static void stm32_hwinitialize(struct stm32_usbdev_s *priv) stm32_putreg(OTG_GAHBCFG_TXFELVL, STM32_OTG_GAHBCFG); -# ifdef CONFIG_STM32F7_OTGFSHS +# ifdef CONFIG_STM32_OTGFSHS -# ifdef CONFIG_STM32F7_NO_ULPI +# ifdef CONFIG_STM32_NO_ULPI regval = stm32_getreg(STM32_OTG_GUSBCFG); regval |= OTG_GUSBCFG_PHYSEL; stm32_putreg(regval, STM32_OTG_GUSBCFG); -# else /* CONFIG_STM32F7_NO_ULPI */ +# else /* CONFIG_STM32_NO_ULPI */ /* Switch off FS transceiver */ @@ -5376,7 +5376,7 @@ static void stm32_hwinitialize(struct stm32_usbdev_s *priv) regval &= ~(OTG_GUSBCFG_ULPIEVBUSD | OTG_GUSBCFG_ULPIEVBUSI); stm32_putreg(regval, STM32_OTG_GUSBCFG); -# ifdef CONFIG_STM32F7_INTERNAL_ULPI +# ifdef CONFIG_STM32_INTERNAL_ULPI /* Select UTMI/ULPI Interface */ @@ -5421,9 +5421,9 @@ static void stm32_hwinitialize(struct stm32_usbdev_s *priv) up_udelay(2000); -# endif /* CONFIG_STM32F7_INTERNAL_ULPI */ -# endif /* CONFIG_STM32F7_NO_ULPI */ -# endif /* CONFIG_STM32F7_OTGFSHS */ +# endif /* CONFIG_STM32_INTERNAL_ULPI */ +# endif /* CONFIG_STM32_NO_ULPI */ +# endif /* CONFIG_STM32_OTGFSHS */ /* Common USB OTG core initialization */ @@ -5465,7 +5465,7 @@ static void stm32_hwinitialize(struct stm32_usbdev_s *priv) regval = stm32_getreg(STM32_OTG_GCCFG); -# if (defined(CONFIG_STM32F7_OTGFS) || defined(CONFIG_STM32F7_NO_ULPI)) +# if (defined(CONFIG_STM32_OTGFS) || defined(CONFIG_STM32_NO_ULPI)) regval |= OTG_GCCFG_PWRDWN; # endif @@ -5509,7 +5509,7 @@ static void stm32_hwinitialize(struct stm32_usbdev_s *priv) regval = stm32_getreg(STM32_OTG_DCFG); regval &= ~OTG_DCFG_DSPD_MASK; -# ifdef CONFIG_STM32F7_OTGFSHS +# ifdef CONFIG_STM32_OTGFSHS regval |= OTG_DCFG_DSPD_HS; # else regval |= OTG_DCFG_DSPD_FS; @@ -5652,7 +5652,7 @@ static void stm32_hwinitialize(struct stm32_usbdev_s *priv) regval &= OTG_GINT_RESERVED; stm32_putreg(regval | OTG_GINT_RC_W1, STM32_OTG_GINTSTS); -# if defined(CONFIG_STM32F7_OTGFSHS) && defined(CONFIG_STM32F7_NO_ULPI) +# if defined(CONFIG_STM32_OTGFSHS) && defined(CONFIG_STM32_NO_ULPI) /* Disable the ULPI Clock enable in RCC AHB1 Register. This must be done * because if both the ULPI and the FS PHY clock enable bits are set at the * same time, the ARM never awakens from WFI due to some bug / errata in @@ -5747,7 +5747,7 @@ void arm_usbinitialize(void) /* SOF output pin configuration is configurable. */ -# ifdef CONFIG_STM32F7_OTG_SOFOUTPUT +# ifdef CONFIG_STM32_OTG_SOFOUTPUT stm32_configgpio(GPIO_OTG_SOF); # endif @@ -5919,7 +5919,7 @@ int usbdev_register(struct usbdevclass_driver_s *driver) */ stm32_pullup(&priv->usbdev, true); -# if defined(CONFIG_STM32F7_INTERNAL_ULPI) || defined(CONFIG_STM32F7_EXTERNAL_ULPI) +# if defined(CONFIG_STM32_INTERNAL_ULPI) || defined(CONFIG_STM32_EXTERNAL_ULPI) priv->usbdev.speed = USB_SPEED_HIGH; # else priv->usbdev.speed = USB_SPEED_FULL; @@ -5991,4 +5991,4 @@ int usbdev_unregister(struct usbdevclass_driver_s *driver) return OK; } -#endif /* CONFIG_USBDEV && CONFIG_STM32F7_OTGDEV */ +#endif /* CONFIG_USBDEV && CONFIG_STM32_OTGDEV */ diff --git a/arch/arm/src/stm32f7/stm32_otghost.c b/arch/arm/src/stm32f7/stm32_otghost.c index 69681d2479b37..d66c084a888fe 100644 --- a/arch/arm/src/stm32f7/stm32_otghost.c +++ b/arch/arm/src/stm32f7/stm32_otghost.c @@ -60,7 +60,7 @@ #include "stm32_otg.h" #include "stm32_usbhost.h" -#if defined(CONFIG_USBHOST) && defined(CONFIG_STM32F7_OTGFS) +#if defined(CONFIG_USBHOST) && defined(CONFIG_STM32_OTGFS) /**************************************************************************** * Pre-processor Definitions @@ -73,61 +73,61 @@ * Pre-requisites * * CONFIG_USBHOST - Enable general USB host support - * CONFIG_STM32F7_OTGFS - Enable the STM32 USB OTG FS block - * CONFIG_STM32F7_SYSCFG_IOCOMPENSATION - Needed + * CONFIG_STM32_OTGFS - Enable the STM32 USB OTG FS block + * CONFIG_STM32_SYSCFG_IOCOMPENSATION - Needed * * Options: * - * CONFIG_STM32F7_OTG_RXFIFO_SIZE - Size of the RX FIFO in 32-bit words. + * CONFIG_STM32_OTG_RXFIFO_SIZE - Size of the RX FIFO in 32-bit words. * Default 128 (512 bytes) - * CONFIG_STM32F7_OTG_NPTXFIFO_SIZE - Size of the non-periodic Tx FIFO + * CONFIG_STM32_OTG_NPTXFIFO_SIZE - Size of the non-periodic Tx FIFO * in 32-bit words. Default 96 (384 bytes) - * CONFIG_STM32F7_OTG_PTXFIFO_SIZE - Size of the periodic Tx FIFO in 32-bit + * CONFIG_STM32_OTG_PTXFIFO_SIZE - Size of the periodic Tx FIFO in 32-bit * words. Default 96 (384 bytes) - * CONFIG_STM32F7_OTG_DESCSIZE - Maximum size of a descriptor. Default: 128 - * CONFIG_STM32F7_OTG_SOFINTR - Enable SOF interrupts. Why would you ever + * CONFIG_STM32_OTG_DESCSIZE - Maximum size of a descriptor. Default: 128 + * CONFIG_STM32_OTG_SOFINTR - Enable SOF interrupts. Why would you ever * want to do that? - * CONFIG_STM32F7_USBHOST_REGDEBUG - Enable very low-level register access + * CONFIG_STM32_USBHOST_REGDEBUG - Enable very low-level register access * debug. Depends on CONFIG_DEBUG_FEATURES. - * CONFIG_STM32F7_USBHOST_PKTDUMP - Dump all incoming and outgoing USB + * CONFIG_STM32_USBHOST_PKTDUMP - Dump all incoming and outgoing USB * packets. Depends on CONFIG_DEBUG_FEATURES. */ /* Pre-requisites (partial) */ -#ifndef CONFIG_STM32F7_SYSCFG_IOCOMPENSATION -# error "CONFIG_STM32F7_SYSCFG_IOCOMPENSATION is required" +#ifndef CONFIG_STM32_SYSCFG_IOCOMPENSATION +# error "CONFIG_STM32_SYSCFG_IOCOMPENSATION is required" #endif /* Default RxFIFO size */ -#ifndef CONFIG_STM32F7_OTG_RXFIFO_SIZE -# define CONFIG_STM32F7_OTG_RXFIFO_SIZE 128 +#ifndef CONFIG_STM32_OTG_RXFIFO_SIZE +# define CONFIG_STM32_OTG_RXFIFO_SIZE 128 #endif /* Default host non-periodic Tx FIFO size */ -#ifndef CONFIG_STM32F7_OTG_NPTXFIFO_SIZE -# define CONFIG_STM32F7_OTG_NPTXFIFO_SIZE 96 +#ifndef CONFIG_STM32_OTG_NPTXFIFO_SIZE +# define CONFIG_STM32_OTG_NPTXFIFO_SIZE 96 #endif /* Default host periodic Tx fifo size register */ -#ifndef CONFIG_STM32F7_OTG_PTXFIFO_SIZE -# define CONFIG_STM32F7_OTG_PTXFIFO_SIZE 96 +#ifndef CONFIG_STM32_OTG_PTXFIFO_SIZE +# define CONFIG_STM32_OTG_PTXFIFO_SIZE 96 #endif /* Maximum size of a descriptor */ -#ifndef CONFIG_STM32F7_OTG_DESCSIZE -# define CONFIG_STM32F7_OTG_DESCSIZE 128 +#ifndef CONFIG_STM32_OTG_DESCSIZE +# define CONFIG_STM32_OTG_DESCSIZE 128 #endif /* Register/packet debug depends on CONFIG_DEBUG_FEATURES */ #ifndef CONFIG_DEBUG_FEATURES -# undef CONFIG_STM32F7_USBHOST_REGDEBUG -# undef CONFIG_STM32F7_USBHOST_PKTDUMP +# undef CONFIG_STM32_USBHOST_REGDEBUG +# undef CONFIG_STM32_USBHOST_PKTDUMP #endif /* HCD Setup ****************************************************************/ @@ -272,7 +272,7 @@ struct stm32_usbhost_s /* Register operations ******************************************************/ -#ifdef CONFIG_STM32F7_USBHOST_REGDEBUG +#ifdef CONFIG_STM32_USBHOST_REGDEBUG static void stm32_printreg(uint32_t addr, uint32_t val, bool iswrite); static void stm32_checkreg(uint32_t addr, uint32_t val, bool iswrite); static uint32_t stm32_getreg(uint32_t addr); @@ -285,7 +285,7 @@ static void stm32_putreg(uint32_t addr, uint32_t value); static inline void stm32_modifyreg(uint32_t addr, uint32_t clrbits, uint32_t setbits); -#ifdef CONFIG_STM32F7_USBHOST_PKTDUMP +#ifdef CONFIG_STM32_USBHOST_PKTDUMP # define stm32_pktdump(m,b,n) lib_dumpbuffer(m,b,n) #else # define stm32_pktdump(m,b,n) @@ -380,7 +380,7 @@ static void stm32_gint_disconnected(struct stm32_usbhost_s *priv); /* Second level interrupt handlers */ -#ifdef CONFIG_STM32F7_OTG_SOFINTR +#ifdef CONFIG_STM32_OTG_SOFINTR static inline void stm32_gint_sofisr(struct stm32_usbhost_s *priv); #endif static inline void stm32_gint_rxflvlisr(struct stm32_usbhost_s *priv); @@ -496,7 +496,7 @@ static struct usbhost_connection_s g_usbconn = * ****************************************************************************/ -#ifdef CONFIG_STM32F7_USBHOST_REGDEBUG +#ifdef CONFIG_STM32_USBHOST_REGDEBUG static void stm32_printreg(uint32_t addr, uint32_t val, bool iswrite) { uinfo("%08" PRIx32 "%s%08" PRIx32 "\n", addr, iswrite ? "<-" : "->", val); @@ -511,7 +511,7 @@ static void stm32_printreg(uint32_t addr, uint32_t val, bool iswrite) * ****************************************************************************/ -#ifdef CONFIG_STM32F7_USBHOST_REGDEBUG +#ifdef CONFIG_STM32_USBHOST_REGDEBUG static void stm32_checkreg(uint32_t addr, uint32_t val, bool iswrite) { static uint32_t prevaddr = 0; @@ -575,7 +575,7 @@ static void stm32_checkreg(uint32_t addr, uint32_t val, bool iswrite) * ****************************************************************************/ -#ifdef CONFIG_STM32F7_USBHOST_REGDEBUG +#ifdef CONFIG_STM32_USBHOST_REGDEBUG static uint32_t stm32_getreg(uint32_t addr) { /* Read the value from the register */ @@ -597,7 +597,7 @@ static uint32_t stm32_getreg(uint32_t addr) * ****************************************************************************/ -#ifdef CONFIG_STM32F7_USBHOST_REGDEBUG +#ifdef CONFIG_STM32_USBHOST_REGDEBUG static void stm32_putreg(uint32_t addr, uint32_t val) { /* Check if we need to print this value */ @@ -2987,7 +2987,7 @@ static void stm32_gint_disconnected(struct stm32_usbhost_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32F7_OTG_SOFINTR +#ifdef CONFIG_STM32_OTG_SOFINTR static inline void stm32_gint_sofisr(struct stm32_usbhost_s *priv) { /* Handle SOF interrupt */ @@ -3555,7 +3555,7 @@ static int stm32_gint_isr(int irq, void *context, void *arg) /* Handle the start of frame interrupt */ -#ifdef CONFIG_STM32F7_OTG_SOFINTR +#ifdef CONFIG_STM32_OTG_SOFINTR if ((pending & OTG_GINT_SOF) != 0) { usbhost_vtrace1(OTG_VTRACE1_GINT_SOF, 0); @@ -3721,7 +3721,7 @@ static inline void stm32_hostinit_enable(void) * OTG_GINT_DISC : Disconnect detected interrupt */ -#ifdef CONFIG_STM32F7_OTG_SOFINTR +#ifdef CONFIG_STM32_OTG_SOFINTR regval |= (OTG_GINT_SOF | OTG_GINT_RXFLVL | OTG_GINT_IISOOXFR | OTG_GINT_HPRT | OTG_GINT_HC | OTG_GINT_DISC); #else @@ -4245,7 +4245,7 @@ static int stm32_alloc(struct usbhost_driver_s *drvr, /* There is no special memory requirement for the STM32. */ - alloc = kmm_malloc(CONFIG_STM32F7_OTG_DESCSIZE); + alloc = kmm_malloc(CONFIG_STM32_OTG_DESCSIZE); if (!alloc) { return -ENOMEM; @@ -4254,7 +4254,7 @@ static int stm32_alloc(struct usbhost_driver_s *drvr, /* Return the allocated address and size of the descriptor buffer */ *buffer = alloc; - *maxlen = CONFIG_STM32F7_OTG_DESCSIZE; + *maxlen = CONFIG_STM32_OTG_DESCSIZE; return OK; } @@ -5121,21 +5121,21 @@ static void stm32_host_initialize(struct stm32_usbhost_s *priv) /* Configure Rx FIFO size (GRXFSIZ) */ - stm32_putreg(STM32_OTG_GRXFSIZ, CONFIG_STM32F7_OTG_RXFIFO_SIZE); - offset = CONFIG_STM32F7_OTG_RXFIFO_SIZE; + stm32_putreg(STM32_OTG_GRXFSIZ, CONFIG_STM32_OTG_RXFIFO_SIZE); + offset = CONFIG_STM32_OTG_RXFIFO_SIZE; /* Setup the host non-periodic Tx FIFO size (HNPTXFSIZ) */ regval = (offset | - (CONFIG_STM32F7_OTG_NPTXFIFO_SIZE << + (CONFIG_STM32_OTG_NPTXFIFO_SIZE << OTG_HNPTXFSIZ_NPTXFD_SHIFT)); stm32_putreg(STM32_OTG_HNPTXFSIZ, regval); - offset += CONFIG_STM32F7_OTG_NPTXFIFO_SIZE; + offset += CONFIG_STM32_OTG_NPTXFIFO_SIZE; /* Set up the host periodic Tx fifo size register (HPTXFSIZ) */ regval = (offset | - (CONFIG_STM32F7_OTG_PTXFIFO_SIZE << + (CONFIG_STM32_OTG_PTXFIFO_SIZE << OTG_HPTXFSIZ_PTXFD_SHIFT)); stm32_putreg(STM32_OTG_HPTXFSIZ, regval); @@ -5407,7 +5407,7 @@ struct usbhost_connection_s *stm32_otgfshost_initialize(int controller) /* SOF output pin configuration is configurable */ -#ifdef CONFIG_STM32F7_OTG_SOFOUTPUT +#ifdef CONFIG_STM32_OTG_SOFOUTPUT stm32_configgpio(GPIO_OTG_SOF); #endif @@ -5433,4 +5433,4 @@ struct usbhost_connection_s *stm32_otgfshost_initialize(int controller) return &g_usbconn; } -#endif /* CONFIG_USBHOST && CONFIG_STM32F7_OTGFS */ +#endif /* CONFIG_USBHOST && CONFIG_STM32_OTGFS */ diff --git a/arch/arm/src/stm32f7/stm32_pulsecount.c b/arch/arm/src/stm32f7/stm32_pulsecount.c index ed0a19ae07992..664dd33dabd54 100644 --- a/arch/arm/src/stm32f7/stm32_pulsecount.c +++ b/arch/arm/src/stm32f7/stm32_pulsecount.c @@ -173,10 +173,10 @@ static int pulsecount_configure(struct pulsecount_lowerhalf_s *dev); static int pulsecount_timer(struct pulsecount_lowerhalf_s *dev, const struct pulsecount_info_s *info); static int pulsecount_interrupt(struct pulsecount_lowerhalf_s *dev); -# ifdef CONFIG_STM32F7_TIM1_PULSECOUNT +# ifdef CONFIG_STM32_TIM1_PULSECOUNT static int pulsecount_tim1interrupt(int irq, void *context, void *arg); # endif -# ifdef CONFIG_STM32F7_TIM8_PULSECOUNT +# ifdef CONFIG_STM32_TIM8_PULSECOUNT static int pulsecount_tim8interrupt(int irq, void *context, void *arg); # endif static uint8_t pulsecount_count(uint32_t count); @@ -203,107 +203,107 @@ static int pulsecount_ioctl(struct pulsecount_lowerhalf_s *dev, * Private Data ****************************************************************************/ -#ifdef CONFIG_STM32F7_TIM1_PULSECOUNT +#ifdef CONFIG_STM32_TIM1_PULSECOUNT static struct stm32_tim_s g_pulsecount1dev = { .channel = { - .channel = CONFIG_STM32F7_TIM1_PULSECOUNT_CHANNEL, -#if CONFIG_STM32F7_TIM1_PULSECOUNT_CHANNEL == 1 + .channel = CONFIG_STM32_TIM1_PULSECOUNT_CHANNEL, +#if CONFIG_STM32_TIM1_PULSECOUNT_CHANNEL == 1 .out1 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM1_PULSECOUNT_POL, - .idle = CONFIG_STM32F7_TIM1_PULSECOUNT_IDLE, + .pol = CONFIG_STM32_TIM1_PULSECOUNT_POL, + .idle = CONFIG_STM32_TIM1_PULSECOUNT_IDLE, .pincfg = GPIO_TIM1_CH1OUT, }, -#elif CONFIG_STM32F7_TIM1_PULSECOUNT_CHANNEL == 2 +#elif CONFIG_STM32_TIM1_PULSECOUNT_CHANNEL == 2 .out1 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM1_PULSECOUNT_POL, - .idle = CONFIG_STM32F7_TIM1_PULSECOUNT_IDLE, + .pol = CONFIG_STM32_TIM1_PULSECOUNT_POL, + .idle = CONFIG_STM32_TIM1_PULSECOUNT_IDLE, .pincfg = GPIO_TIM1_CH2OUT, }, -#elif CONFIG_STM32F7_TIM1_PULSECOUNT_CHANNEL == 3 +#elif CONFIG_STM32_TIM1_PULSECOUNT_CHANNEL == 3 .out1 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM1_PULSECOUNT_POL, - .idle = CONFIG_STM32F7_TIM1_PULSECOUNT_IDLE, + .pol = CONFIG_STM32_TIM1_PULSECOUNT_POL, + .idle = CONFIG_STM32_TIM1_PULSECOUNT_IDLE, .pincfg = GPIO_TIM1_CH3OUT, }, -#elif CONFIG_STM32F7_TIM1_PULSECOUNT_CHANNEL == 4 +#elif CONFIG_STM32_TIM1_PULSECOUNT_CHANNEL == 4 .out1 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM1_PULSECOUNT_POL, - .idle = CONFIG_STM32F7_TIM1_PULSECOUNT_IDLE, + .pol = CONFIG_STM32_TIM1_PULSECOUNT_POL, + .idle = CONFIG_STM32_TIM1_PULSECOUNT_IDLE, .pincfg = GPIO_TIM1_CH4OUT, }, #endif }, .timid = 1, .timtype = TIMTYPE_TIM1, - .t_dts = CONFIG_STM32F7_TIM1_PULSECOUNT_TDTS, + .t_dts = CONFIG_STM32_TIM1_PULSECOUNT_TDTS, .irq = STM32_IRQ_TIM1UP, .base = STM32_TIM1_BASE, .pclk = TIMCLK_TIM1, }; -#endif /* CONFIG_STM32F7_TIM1_PULSECOUNT */ +#endif /* CONFIG_STM32_TIM1_PULSECOUNT */ -#ifdef CONFIG_STM32F7_TIM8_PULSECOUNT +#ifdef CONFIG_STM32_TIM8_PULSECOUNT static struct stm32_tim_s g_pulsecount8dev = { .channel = { - .channel = CONFIG_STM32F7_TIM8_PULSECOUNT_CHANNEL, -#if CONFIG_STM32F7_TIM8_PULSECOUNT_CHANNEL == 1 + .channel = CONFIG_STM32_TIM8_PULSECOUNT_CHANNEL, +#if CONFIG_STM32_TIM8_PULSECOUNT_CHANNEL == 1 .out1 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM8_PULSECOUNT_POL, - .idle = CONFIG_STM32F7_TIM8_PULSECOUNT_IDLE, + .pol = CONFIG_STM32_TIM8_PULSECOUNT_POL, + .idle = CONFIG_STM32_TIM8_PULSECOUNT_IDLE, .pincfg = GPIO_TIM8_CH1OUT, }, -#elif CONFIG_STM32F7_TIM8_PULSECOUNT_CHANNEL == 2 +#elif CONFIG_STM32_TIM8_PULSECOUNT_CHANNEL == 2 .out1 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM8_PULSECOUNT_POL, - .idle = CONFIG_STM32F7_TIM8_PULSECOUNT_IDLE, + .pol = CONFIG_STM32_TIM8_PULSECOUNT_POL, + .idle = CONFIG_STM32_TIM8_PULSECOUNT_IDLE, .pincfg = GPIO_TIM8_CH2OUT, }, -#elif CONFIG_STM32F7_TIM8_PULSECOUNT_CHANNEL == 3 +#elif CONFIG_STM32_TIM8_PULSECOUNT_CHANNEL == 3 .out1 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM8_PULSECOUNT_POL, - .idle = CONFIG_STM32F7_TIM8_PULSECOUNT_IDLE, + .pol = CONFIG_STM32_TIM8_PULSECOUNT_POL, + .idle = CONFIG_STM32_TIM8_PULSECOUNT_IDLE, .pincfg = GPIO_TIM8_CH3OUT, }, -#elif CONFIG_STM32F7_TIM8_PULSECOUNT_CHANNEL == 4 +#elif CONFIG_STM32_TIM8_PULSECOUNT_CHANNEL == 4 .out1 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM8_PULSECOUNT_POL, - .idle = CONFIG_STM32F7_TIM8_PULSECOUNT_IDLE, + .pol = CONFIG_STM32_TIM8_PULSECOUNT_POL, + .idle = CONFIG_STM32_TIM8_PULSECOUNT_IDLE, .pincfg = GPIO_TIM8_CH4OUT, }, #endif }, .timid = 8, .timtype = TIMTYPE_TIM8, - .t_dts = CONFIG_STM32F7_TIM8_PULSECOUNT_TDTS, + .t_dts = CONFIG_STM32_TIM8_PULSECOUNT_TDTS, .irq = STM32_IRQ_TIM8UP, .base = STM32_TIM8_BASE, .pclk = TIMCLK_TIM8, }; -#endif /* CONFIG_STM32F7_TIM8_PULSECOUNT */ +#endif /* CONFIG_STM32_TIM8_PULSECOUNT */ static const struct pulsecount_ops_s g_pulsecountops = { @@ -314,7 +314,7 @@ static const struct pulsecount_ops_s g_pulsecountops = .ioctl = pulsecount_ioctl, }; -#ifdef CONFIG_STM32F7_TIM1_PULSECOUNT +#ifdef CONFIG_STM32_TIM1_PULSECOUNT static struct stm32_pulsecount_s g_pulsecount1lower = { .ops = &g_pulsecountops, @@ -322,7 +322,7 @@ static struct stm32_pulsecount_s g_pulsecount1lower = }; #endif -#ifdef CONFIG_STM32F7_TIM8_PULSECOUNT +#ifdef CONFIG_STM32_TIM8_PULSECOUNT static struct stm32_pulsecount_s g_pulsecount8lower = { .ops = &g_pulsecountops, @@ -1303,21 +1303,21 @@ static int pulsecount_interrupt(struct pulsecount_lowerhalf_s *dev) * ****************************************************************************/ -#ifdef CONFIG_STM32F7_TIM1_PULSECOUNT +#ifdef CONFIG_STM32_TIM1_PULSECOUNT static int pulsecount_tim1interrupt(int irq, void *context, void *arg) { return pulsecount_interrupt((struct pulsecount_lowerhalf_s *) &g_pulsecount1dev); } -#endif /* CONFIG_STM32F7_TIM1_PULSECOUNT */ +#endif /* CONFIG_STM32_TIM1_PULSECOUNT */ -#ifdef CONFIG_STM32F7_TIM8_PULSECOUNT +#ifdef CONFIG_STM32_TIM8_PULSECOUNT static int pulsecount_tim8interrupt(int irq, void *context, void *arg) { return pulsecount_interrupt((struct pulsecount_lowerhalf_s *) &g_pulsecount8dev); } -#endif /* CONFIG_STM32F7_TIM8_PULSECOUNT */ +#endif /* CONFIG_STM32_TIM8_PULSECOUNT */ /**************************************************************************** * Name: pulsecount_count @@ -1390,7 +1390,7 @@ static int pulsecount_set_apb_clock(struct stm32_tim_s *priv, bool on) switch (priv->timid) { -#ifdef CONFIG_STM32F7_TIM1_PULSECOUNT +#ifdef CONFIG_STM32_TIM1_PULSECOUNT case 1: { regaddr = TIMRCCEN_TIM1; @@ -1399,7 +1399,7 @@ static int pulsecount_set_apb_clock(struct stm32_tim_s *priv, bool on) } #endif -#ifdef CONFIG_STM32F7_TIM8_PULSECOUNT +#ifdef CONFIG_STM32_TIM8_PULSECOUNT case 8: { regaddr = TIMRCCEN_TIM8; @@ -1717,7 +1717,7 @@ struct pulsecount_lowerhalf_s *stm32_pulsecountinitialize(int timer) switch (timer) { -#ifdef CONFIG_STM32F7_TIM1_PULSECOUNT +#ifdef CONFIG_STM32_TIM1_PULSECOUNT case 1: { lower = &g_pulsecount1lower; @@ -1727,7 +1727,7 @@ struct pulsecount_lowerhalf_s *stm32_pulsecountinitialize(int timer) } #endif -#ifdef CONFIG_STM32F7_TIM8_PULSECOUNT +#ifdef CONFIG_STM32_TIM8_PULSECOUNT case 8: { lower = &g_pulsecount8lower; diff --git a/arch/arm/src/stm32f7/stm32_pwm.c b/arch/arm/src/stm32f7/stm32_pwm.c index 66f1f90ca68bf..1494220031ae0 100644 --- a/arch/arm/src/stm32f7/stm32_pwm.c +++ b/arch/arm/src/stm32f7/stm32_pwm.c @@ -42,7 +42,7 @@ #include "stm32_rcc.h" #include "stm32_gpio.h" -#ifdef CONFIG_STM32F7_PWM +#ifdef CONFIG_STM32_PWM /**************************************************************************** * Pre-processor Definitions @@ -149,7 +149,7 @@ /* Advanced Timer support */ -#if defined(CONFIG_STM32F7_TIM1_PWM) || defined(CONFIG_STM32F7_TIM8_PWM) +#if defined(CONFIG_STM32_TIM1_PWM) || defined(CONFIG_STM32_TIM8_PWM) # define HAVE_ADVTIM #else # undef HAVE_ADVTIM @@ -157,14 +157,14 @@ /* TRGO/TRGO2 support */ -#ifdef CONFIG_STM32F7_PWM_TRGO +#ifdef CONFIG_STM32_PWM_TRGO # define HAVE_TRGO #endif /* Break support */ -#if defined(CONFIG_STM32F7_TIM1_BREAK1) || defined(CONFIG_STM32F7_TIM1_BREAK2) || \ - defined(CONFIG_STM32F7_TIM8_BREAK1) || defined(CONFIG_STM32F7_TIM8_BREAK2) +#if defined(CONFIG_STM32_TIM1_BREAK1) || defined(CONFIG_STM32_TIM1_BREAK2) || \ + defined(CONFIG_STM32_TIM8_BREAK1) || defined(CONFIG_STM32_TIM8_BREAK2) # defined HAVE_BREAK #endif @@ -225,7 +225,7 @@ struct stm32_pwmchan_s struct stm32_pwmtimer_s { const struct pwm_ops_s *ops; /* PWM operations */ -#ifdef CONFIG_STM32F7_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS const struct stm32_pwm_ops_s *llops; /* Low-level PWM ops */ #endif struct stm32_pwmchan_s *channels; /* Channels configuration */ @@ -298,10 +298,10 @@ static int pwm_break_dt_configure(struct stm32_pwmtimer_s *priv); static int pwm_trgo_configure(struct pwm_lowerhalf_s *dev, uint8_t trgo); #endif -#if defined(HAVE_PWM_COMPLEMENTARY) && defined(CONFIG_STM32F7_PWM_LL_OPS) +#if defined(HAVE_PWM_COMPLEMENTARY) && defined(CONFIG_STM32_PWM_LL_OPS) static int pwm_deadtime_update(struct pwm_lowerhalf_s *dev, uint8_t dt); #endif -#ifdef CONFIG_STM32F7_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS static uint32_t pwm_ccr_get(struct pwm_lowerhalf_s *dev, uint8_t index); static uint16_t pwm_rcr_get(struct pwm_lowerhalf_s *dev); #endif @@ -342,7 +342,7 @@ static const struct pwm_ops_s g_pwmops = .ioctl = pwm_ioctl, }; -#ifdef CONFIG_STM32F7_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS static const struct stm32_pwm_ops_s g_llpwmops = { .configure = pwm_configure, @@ -372,138 +372,138 @@ static const struct stm32_pwm_ops_s g_llpwmops = }; #endif -#ifdef CONFIG_STM32F7_TIM1_PWM +#ifdef CONFIG_STM32_TIM1_PWM static struct stm32_pwmchan_s g_pwm1channels[] = { /* TIM1 has 4 channels, 4 complementary */ -#ifdef CONFIG_STM32F7_TIM1_CHANNEL1 +#ifdef CONFIG_STM32_TIM1_CHANNEL1 { .channel = 1, - .mode = CONFIG_STM32F7_TIM1_CH1MODE, + .mode = CONFIG_STM32_TIM1_CH1MODE, #ifdef HAVE_BREAK .brk = { -#ifdef CONFIG_STM32F7_TIM1_BREAK1 +#ifdef CONFIG_STM32_TIM1_BREAK1 .en1 = 1, - .pol1 = CONFIG_STM32F7_TIM1_BRK1POL, + .pol1 = CONFIG_STM32_TIM1_BRK1POL, #endif -#ifdef CONFIG_STM32F7_TIM1_BREAK2 +#ifdef CONFIG_STM32_TIM1_BREAK2 .en2 = 1, - .pol2 = CONFIG_STM32F7_TIM1_BRK2POL, - .flt2 = CONFIG_STM32F7_TIM1_BRK2FLT, + .pol2 = CONFIG_STM32_TIM1_BRK2POL, + .flt2 = CONFIG_STM32_TIM1_BRK2FLT, #endif }, #endif -#ifdef CONFIG_STM32F7_TIM1_CH1OUT +#ifdef CONFIG_STM32_TIM1_CH1OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM1_CH1POL, - .idle = CONFIG_STM32F7_TIM1_CH1IDLE, + .pol = CONFIG_STM32_TIM1_CH1POL, + .idle = CONFIG_STM32_TIM1_CH1IDLE, .pincfg = PWM_TIM1_CH1CFG, }, #endif -#ifdef CONFIG_STM32F7_TIM1_CH1NOUT +#ifdef CONFIG_STM32_TIM1_CH1NOUT .out2 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM1_CH1NPOL, - .idle = CONFIG_STM32F7_TIM1_CH1NIDLE, + .pol = CONFIG_STM32_TIM1_CH1NPOL, + .idle = CONFIG_STM32_TIM1_CH1NIDLE, .pincfg = PWM_TIM1_CH1NCFG, } #endif }, #endif -#ifdef CONFIG_STM32F7_TIM1_CHANNEL2 +#ifdef CONFIG_STM32_TIM1_CHANNEL2 { .channel = 2, - .mode = CONFIG_STM32F7_TIM1_CH2MODE, -#ifdef CONFIG_STM32F7_TIM1_CH2OUT + .mode = CONFIG_STM32_TIM1_CH2MODE, +#ifdef CONFIG_STM32_TIM1_CH2OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM1_CH2POL, - .idle = CONFIG_STM32F7_TIM1_CH2IDLE, + .pol = CONFIG_STM32_TIM1_CH2POL, + .idle = CONFIG_STM32_TIM1_CH2IDLE, .pincfg = PWM_TIM1_CH2CFG, }, #endif -#ifdef CONFIG_STM32F7_TIM1_CH2NOUT +#ifdef CONFIG_STM32_TIM1_CH2NOUT .out2 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM1_CH2NPOL, - .idle = CONFIG_STM32F7_TIM1_CH2NIDLE, + .pol = CONFIG_STM32_TIM1_CH2NPOL, + .idle = CONFIG_STM32_TIM1_CH2NIDLE, .pincfg = PWM_TIM1_CH2NCFG, } #endif }, #endif -#ifdef CONFIG_STM32F7_TIM1_CHANNEL3 +#ifdef CONFIG_STM32_TIM1_CHANNEL3 { .channel = 3, - .mode = CONFIG_STM32F7_TIM1_CH3MODE, -#ifdef CONFIG_STM32F7_TIM1_CH3OUT + .mode = CONFIG_STM32_TIM1_CH3MODE, +#ifdef CONFIG_STM32_TIM1_CH3OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM1_CH3POL, - .idle = CONFIG_STM32F7_TIM1_CH3IDLE, + .pol = CONFIG_STM32_TIM1_CH3POL, + .idle = CONFIG_STM32_TIM1_CH3IDLE, .pincfg = PWM_TIM1_CH3CFG, }, #endif -#ifdef CONFIG_STM32F7_TIM1_CH3NOUT +#ifdef CONFIG_STM32_TIM1_CH3NOUT .out2 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM1_CH3NPOL, - .idle = CONFIG_STM32F7_TIM1_CH3NIDLE, + .pol = CONFIG_STM32_TIM1_CH3NPOL, + .idle = CONFIG_STM32_TIM1_CH3NIDLE, .pincfg = PWM_TIM1_CH3NCFG, } #endif }, #endif -#ifdef CONFIG_STM32F7_TIM1_CHANNEL4 +#ifdef CONFIG_STM32_TIM1_CHANNEL4 { .channel = 4, - .mode = CONFIG_STM32F7_TIM1_CH4MODE, -#ifdef CONFIG_STM32F7_TIM1_CH4OUT + .mode = CONFIG_STM32_TIM1_CH4MODE, +#ifdef CONFIG_STM32_TIM1_CH4OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM1_CH4POL, - .idle = CONFIG_STM32F7_TIM1_CH4IDLE, + .pol = CONFIG_STM32_TIM1_CH4POL, + .idle = CONFIG_STM32_TIM1_CH4IDLE, .pincfg = PWM_TIM1_CH4CFG, } #endif }, #endif -#ifdef CONFIG_STM32F7_TIM1_CHANNEL5 +#ifdef CONFIG_STM32_TIM1_CHANNEL5 { .channel = 5, - .mode = CONFIG_STM32F7_TIM1_CH5MODE, -#ifdef CONFIG_STM32F7_TIM1_CH5OUT + .mode = CONFIG_STM32_TIM1_CH5MODE, +#ifdef CONFIG_STM32_TIM1_CH5OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM1_CH5POL, - .idle = CONFIG_STM32F7_TIM1_CH5IDLE, + .pol = CONFIG_STM32_TIM1_CH5POL, + .idle = CONFIG_STM32_TIM1_CH5IDLE, .pincfg = 0, /* Not available externally */ } #endif }, #endif -#ifdef CONFIG_STM32F7_TIM1_CHANNEL6 +#ifdef CONFIG_STM32_TIM1_CHANNEL6 { .channel = 6, - .mode = CONFIG_STM32F7_TIM1_CH6MODE, -#ifdef CONFIG_STM32F7_TIM1_CH6OUT + .mode = CONFIG_STM32_TIM1_CH6MODE, +#ifdef CONFIG_STM32_TIM1_CH6OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM1_CH6POL, - .idle = CONFIG_STM32F7_TIM1_CH6IDLE, + .pol = CONFIG_STM32_TIM1_CH6POL, + .idle = CONFIG_STM32_TIM1_CH6IDLE, .pincfg = 0, /* Not available externally */ } #endif @@ -514,18 +514,18 @@ static struct stm32_pwmchan_s g_pwm1channels[] = static struct stm32_pwmtimer_s g_pwm1dev = { .ops = &g_pwmops, -#ifdef CONFIG_STM32F7_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS .llops = &g_llpwmops, #endif .timid = 1, .chan_num = PWM_TIM1_NCHANNELS, .channels = g_pwm1channels, .timtype = TIMTYPE_TIM1, - .mode = CONFIG_STM32F7_TIM1_MODE, - .lock = CONFIG_STM32F7_TIM1_LOCK, - .t_dts = CONFIG_STM32F7_TIM1_TDTS, + .mode = CONFIG_STM32_TIM1_MODE, + .lock = CONFIG_STM32_TIM1_LOCK, + .t_dts = CONFIG_STM32_TIM1_TDTS, #ifdef HAVE_PWM_COMPLEMENTARY - .deadtime = CONFIG_STM32F7_TIM1_DEADTIME, + .deadtime = CONFIG_STM32_TIM1_DEADTIME, #endif #if defined(HAVE_TRGO) && defined(STM32_TIM1_TRGO) .trgo = STM32_TIM1_TRGO, @@ -533,72 +533,72 @@ static struct stm32_pwmtimer_s g_pwm1dev = .base = STM32_TIM1_BASE, .pclk = TIMCLK_TIM1, }; -#endif /* CONFIG_STM32F7_TIM1_PWM */ +#endif /* CONFIG_STM32_TIM1_PWM */ -#ifdef CONFIG_STM32F7_TIM2_PWM +#ifdef CONFIG_STM32_TIM2_PWM static struct stm32_pwmchan_s g_pwm2channels[] = { /* TIM2 has 4 channels */ -#ifdef CONFIG_STM32F7_TIM2_CHANNEL1 +#ifdef CONFIG_STM32_TIM2_CHANNEL1 { .channel = 1, - .mode = CONFIG_STM32F7_TIM2_CH1MODE, -#ifdef CONFIG_STM32F7_TIM2_CH1OUT + .mode = CONFIG_STM32_TIM2_CH1MODE, +#ifdef CONFIG_STM32_TIM2_CH1OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM2_CH1POL, - .idle = CONFIG_STM32F7_TIM2_CH1IDLE, + .pol = CONFIG_STM32_TIM2_CH1POL, + .idle = CONFIG_STM32_TIM2_CH1IDLE, .pincfg = PWM_TIM2_CH1CFG, } #endif /* No complementary outputs */ }, #endif -#ifdef CONFIG_STM32F7_TIM2_CHANNEL2 +#ifdef CONFIG_STM32_TIM2_CHANNEL2 { .channel = 2, - .mode = CONFIG_STM32F7_TIM2_CH2MODE, -#ifdef CONFIG_STM32F7_TIM2_CH2OUT + .mode = CONFIG_STM32_TIM2_CH2MODE, +#ifdef CONFIG_STM32_TIM2_CH2OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM2_CH2POL, - .idle = CONFIG_STM32F7_TIM2_CH2IDLE, + .pol = CONFIG_STM32_TIM2_CH2POL, + .idle = CONFIG_STM32_TIM2_CH2IDLE, .pincfg = PWM_TIM2_CH2CFG, } #endif /* No complementary outputs */ }, #endif -#ifdef CONFIG_STM32F7_TIM2_CHANNEL3 +#ifdef CONFIG_STM32_TIM2_CHANNEL3 { .channel = 3, - .mode = CONFIG_STM32F7_TIM2_CH3MODE, -#ifdef CONFIG_STM32F7_TIM2_CH3OUT + .mode = CONFIG_STM32_TIM2_CH3MODE, +#ifdef CONFIG_STM32_TIM2_CH3OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM2_CH3POL, - .idle = CONFIG_STM32F7_TIM2_CH3IDLE, + .pol = CONFIG_STM32_TIM2_CH3POL, + .idle = CONFIG_STM32_TIM2_CH3IDLE, .pincfg = PWM_TIM2_CH3CFG, } #endif /* No complementary outputs */ }, #endif -#ifdef CONFIG_STM32F7_TIM2_CHANNEL4 +#ifdef CONFIG_STM32_TIM2_CHANNEL4 { .channel = 4, - .mode = CONFIG_STM32F7_TIM2_CH4MODE, -#ifdef CONFIG_STM32F7_TIM2_CH4OUT + .mode = CONFIG_STM32_TIM2_CH4MODE, +#ifdef CONFIG_STM32_TIM2_CH4OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM2_CH4POL, - .idle = CONFIG_STM32F7_TIM2_CH4IDLE, + .pol = CONFIG_STM32_TIM2_CH4POL, + .idle = CONFIG_STM32_TIM2_CH4IDLE, .pincfg = PWM_TIM2_CH4CFG, } #endif @@ -610,14 +610,14 @@ static struct stm32_pwmchan_s g_pwm2channels[] = static struct stm32_pwmtimer_s g_pwm2dev = { .ops = &g_pwmops, -#ifdef CONFIG_STM32F7_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS .llops = &g_llpwmops, #endif .timid = 2, .chan_num = PWM_TIM2_NCHANNELS, .channels = g_pwm2channels, .timtype = TIMTYPE_TIM2, - .mode = CONFIG_STM32F7_TIM2_MODE, + .mode = CONFIG_STM32_TIM2_MODE, .lock = 0, /* No lock */ .t_dts = 0, /* No t_dts */ #ifdef HAVE_PWM_COMPLEMENTARY @@ -629,72 +629,72 @@ static struct stm32_pwmtimer_s g_pwm2dev = .base = STM32_TIM2_BASE, .pclk = TIMCLK_TIM2, }; -#endif /* CONFIG_STM32F7_TIM2_PWM */ +#endif /* CONFIG_STM32_TIM2_PWM */ -#ifdef CONFIG_STM32F7_TIM3_PWM +#ifdef CONFIG_STM32_TIM3_PWM static struct stm32_pwmchan_s g_pwm3channels[] = { /* TIM3 has 4 channels */ -#ifdef CONFIG_STM32F7_TIM3_CHANNEL1 +#ifdef CONFIG_STM32_TIM3_CHANNEL1 { .channel = 1, - .mode = CONFIG_STM32F7_TIM3_CH1MODE, -#ifdef CONFIG_STM32F7_TIM3_CH1OUT + .mode = CONFIG_STM32_TIM3_CH1MODE, +#ifdef CONFIG_STM32_TIM3_CH1OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM3_CH1POL, - .idle = CONFIG_STM32F7_TIM3_CH1IDLE, + .pol = CONFIG_STM32_TIM3_CH1POL, + .idle = CONFIG_STM32_TIM3_CH1IDLE, .pincfg = PWM_TIM3_CH1CFG, } #endif /* No complementary outputs */ }, #endif -#ifdef CONFIG_STM32F7_TIM3_CHANNEL2 +#ifdef CONFIG_STM32_TIM3_CHANNEL2 { .channel = 2, - .mode = CONFIG_STM32F7_TIM3_CH2MODE, -#ifdef CONFIG_STM32F7_TIM3_CH2OUT + .mode = CONFIG_STM32_TIM3_CH2MODE, +#ifdef CONFIG_STM32_TIM3_CH2OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM3_CH2POL, - .idle = CONFIG_STM32F7_TIM3_CH2IDLE, + .pol = CONFIG_STM32_TIM3_CH2POL, + .idle = CONFIG_STM32_TIM3_CH2IDLE, .pincfg = PWM_TIM3_CH2CFG, } #endif /* No complementary outputs */ }, #endif -#ifdef CONFIG_STM32F7_TIM3_CHANNEL3 +#ifdef CONFIG_STM32_TIM3_CHANNEL3 { .channel = 3, - .mode = CONFIG_STM32F7_TIM3_CH3MODE, -#ifdef CONFIG_STM32F7_TIM3_CH3OUT + .mode = CONFIG_STM32_TIM3_CH3MODE, +#ifdef CONFIG_STM32_TIM3_CH3OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM3_CH3POL, - .idle = CONFIG_STM32F7_TIM3_CH3IDLE, + .pol = CONFIG_STM32_TIM3_CH3POL, + .idle = CONFIG_STM32_TIM3_CH3IDLE, .pincfg = PWM_TIM3_CH3CFG, } #endif /* No complementary outputs */ }, #endif -#ifdef CONFIG_STM32F7_TIM3_CHANNEL4 +#ifdef CONFIG_STM32_TIM3_CHANNEL4 { .channel = 4, - .mode = CONFIG_STM32F7_TIM3_CH4MODE, -#ifdef CONFIG_STM32F7_TIM3_CH4OUT + .mode = CONFIG_STM32_TIM3_CH4MODE, +#ifdef CONFIG_STM32_TIM3_CH4OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM3_CH4POL, - .idle = CONFIG_STM32F7_TIM3_CH4IDLE, + .pol = CONFIG_STM32_TIM3_CH4POL, + .idle = CONFIG_STM32_TIM3_CH4IDLE, .pincfg = PWM_TIM3_CH4CFG, } #endif @@ -706,14 +706,14 @@ static struct stm32_pwmchan_s g_pwm3channels[] = static struct stm32_pwmtimer_s g_pwm3dev = { .ops = &g_pwmops, -#ifdef CONFIG_STM32F7_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS .llops = &g_llpwmops, #endif .timid = 3, .chan_num = PWM_TIM3_NCHANNELS, .channels = g_pwm3channels, .timtype = TIMTYPE_TIM3, - .mode = CONFIG_STM32F7_TIM3_MODE, + .mode = CONFIG_STM32_TIM3_MODE, .lock = 0, /* No lock */ .t_dts = 0, /* No t_dts */ #ifdef HAVE_PWM_COMPLEMENTARY @@ -725,72 +725,72 @@ static struct stm32_pwmtimer_s g_pwm3dev = .base = STM32_TIM3_BASE, .pclk = TIMCLK_TIM3, }; -#endif /* CONFIG_STM32F7_TIM3_PWM */ +#endif /* CONFIG_STM32_TIM3_PWM */ -#ifdef CONFIG_STM32F7_TIM4_PWM +#ifdef CONFIG_STM32_TIM4_PWM static struct stm32_pwmchan_s g_pwm4channels[] = { /* TIM4 has 4 channels */ -#ifdef CONFIG_STM32F7_TIM4_CHANNEL1 +#ifdef CONFIG_STM32_TIM4_CHANNEL1 { .channel = 1, - .mode = CONFIG_STM32F7_TIM4_CH1MODE, -#ifdef CONFIG_STM32F7_TIM4_CH1OUT + .mode = CONFIG_STM32_TIM4_CH1MODE, +#ifdef CONFIG_STM32_TIM4_CH1OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM4_CH1POL, - .idle = CONFIG_STM32F7_TIM4_CH1IDLE, + .pol = CONFIG_STM32_TIM4_CH1POL, + .idle = CONFIG_STM32_TIM4_CH1IDLE, .pincfg = PWM_TIM4_CH1CFG, } #endif /* No complementary outputs */ }, #endif -#ifdef CONFIG_STM32F7_TIM4_CHANNEL2 +#ifdef CONFIG_STM32_TIM4_CHANNEL2 { .channel = 2, - .mode = CONFIG_STM32F7_TIM4_CH2MODE, -#ifdef CONFIG_STM32F7_TIM4_CH2OUT + .mode = CONFIG_STM32_TIM4_CH2MODE, +#ifdef CONFIG_STM32_TIM4_CH2OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM4_CH2POL, - .idle = CONFIG_STM32F7_TIM4_CH2IDLE, + .pol = CONFIG_STM32_TIM4_CH2POL, + .idle = CONFIG_STM32_TIM4_CH2IDLE, .pincfg = PWM_TIM4_CH2CFG, } #endif /* No complementary outputs */ }, #endif -#ifdef CONFIG_STM32F7_TIM4_CHANNEL3 +#ifdef CONFIG_STM32_TIM4_CHANNEL3 { .channel = 3, - .mode = CONFIG_STM32F7_TIM4_CH3MODE, -#ifdef CONFIG_STM32F7_TIM4_CH3OUT + .mode = CONFIG_STM32_TIM4_CH3MODE, +#ifdef CONFIG_STM32_TIM4_CH3OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM4_CH3POL, - .idle = CONFIG_STM32F7_TIM4_CH3IDLE, + .pol = CONFIG_STM32_TIM4_CH3POL, + .idle = CONFIG_STM32_TIM4_CH3IDLE, .pincfg = PWM_TIM4_CH3CFG, } #endif /* No complementary outputs */ }, #endif -#ifdef CONFIG_STM32F7_TIM4_CHANNEL4 +#ifdef CONFIG_STM32_TIM4_CHANNEL4 { .channel = 4, - .mode = CONFIG_STM32F7_TIM4_CH4MODE, -#ifdef CONFIG_STM32F7_TIM4_CH4OUT + .mode = CONFIG_STM32_TIM4_CH4MODE, +#ifdef CONFIG_STM32_TIM4_CH4OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM4_CH4POL, - .idle = CONFIG_STM32F7_TIM4_CH4IDLE, + .pol = CONFIG_STM32_TIM4_CH4POL, + .idle = CONFIG_STM32_TIM4_CH4IDLE, .pincfg = PWM_TIM4_CH4CFG, } #endif @@ -802,14 +802,14 @@ static struct stm32_pwmchan_s g_pwm4channels[] = static struct stm32_pwmtimer_s g_pwm4dev = { .ops = &g_pwmops, -#ifdef CONFIG_STM32F7_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS .llops = &g_llpwmops, #endif .timid = 4, .chan_num = PWM_TIM4_NCHANNELS, .channels = g_pwm4channels, .timtype = TIMTYPE_TIM4, - .mode = CONFIG_STM32F7_TIM4_MODE, + .mode = CONFIG_STM32_TIM4_MODE, .lock = 0, /* No lock */ .t_dts = 0, /* No t_dts */ #ifdef HAVE_PWM_COMPLEMENTARY @@ -821,71 +821,71 @@ static struct stm32_pwmtimer_s g_pwm4dev = .base = STM32_TIM4_BASE, .pclk = TIMCLK_TIM4, }; -#endif /* CONFIG_STM32F7_TIM4_PWM */ +#endif /* CONFIG_STM32_TIM4_PWM */ -#ifdef CONFIG_STM32F7_TIM5_PWM +#ifdef CONFIG_STM32_TIM5_PWM static struct stm32_pwmchan_s g_pwm5channels[] = { /* TIM5 has 4 channels */ -#ifdef CONFIG_STM32F7_TIM5_CHANNEL1 +#ifdef CONFIG_STM32_TIM5_CHANNEL1 { .channel = 1, - .mode = CONFIG_STM32F7_TIM5_CH1MODE, -#ifdef CONFIG_STM32F7_TIM5_CH1OUT + .mode = CONFIG_STM32_TIM5_CH1MODE, +#ifdef CONFIG_STM32_TIM5_CH1OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM5_CH1POL, - .idle = CONFIG_STM32F7_TIM5_CH1IDLE, + .pol = CONFIG_STM32_TIM5_CH1POL, + .idle = CONFIG_STM32_TIM5_CH1IDLE, .pincfg = PWM_TIM5_CH1CFG, } #endif /* No complementary outputs */ }, #endif -#ifdef CONFIG_STM32F7_TIM5_CHANNEL2 +#ifdef CONFIG_STM32_TIM5_CHANNEL2 { .channel = 2, - .mode = CONFIG_STM32F7_TIM5_CH2MODE, -#ifdef CONFIG_STM32F7_TIM5_CH2OUT + .mode = CONFIG_STM32_TIM5_CH2MODE, +#ifdef CONFIG_STM32_TIM5_CH2OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM5_CH2POL, - .idle = CONFIG_STM32F7_TIM5_CH2IDLE, + .pol = CONFIG_STM32_TIM5_CH2POL, + .idle = CONFIG_STM32_TIM5_CH2IDLE, .pincfg = PWM_TIM5_CH2CFG, } #endif /* No complementary outputs */ }, #endif -#ifdef CONFIG_STM32F7_TIM5_CHANNEL3 +#ifdef CONFIG_STM32_TIM5_CHANNEL3 { .channel = 3, - .mode = CONFIG_STM32F7_TIM5_CH3MODE, -#ifdef CONFIG_STM32F7_TIM5_CH3OUT + .mode = CONFIG_STM32_TIM5_CH3MODE, +#ifdef CONFIG_STM32_TIM5_CH3OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM5_CH3POL, - .idle = CONFIG_STM32F7_TIM5_CH3IDLE, + .pol = CONFIG_STM32_TIM5_CH3POL, + .idle = CONFIG_STM32_TIM5_CH3IDLE, .pincfg = PWM_TIM5_CH3CFG, } #endif }, #endif -#ifdef CONFIG_STM32F7_TIM5_CHANNEL4 +#ifdef CONFIG_STM32_TIM5_CHANNEL4 { .channel = 4, - .mode = CONFIG_STM32F7_TIM5_CH4MODE, -#ifdef CONFIG_STM32F7_TIM5_CH4OUT + .mode = CONFIG_STM32_TIM5_CH4MODE, +#ifdef CONFIG_STM32_TIM5_CH4OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM5_CH4POL, - .idle = CONFIG_STM32F7_TIM5_CH4IDLE, + .pol = CONFIG_STM32_TIM5_CH4POL, + .idle = CONFIG_STM32_TIM5_CH4IDLE, .pincfg = PWM_TIM5_CH4CFG, } #endif @@ -896,14 +896,14 @@ static struct stm32_pwmchan_s g_pwm5channels[] = static struct stm32_pwmtimer_s g_pwm5dev = { .ops = &g_pwmops, -#ifdef CONFIG_STM32F7_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS .llops = &g_llpwmops, #endif .timid = 5, .chan_num = PWM_TIM5_NCHANNELS, .channels = g_pwm5channels, .timtype = TIMTYPE_TIM5, - .mode = CONFIG_STM32F7_TIM5_MODE, + .mode = CONFIG_STM32_TIM5_MODE, .lock = 0, /* No lock */ .t_dts = 0, /* No t_dts */ #ifdef HAVE_PWM_COMPLEMENTARY @@ -915,140 +915,140 @@ static struct stm32_pwmtimer_s g_pwm5dev = .base = STM32_TIM5_BASE, .pclk = TIMCLK_TIM5, }; -#endif /* CONFIG_STM32F7_TIM5_PWM */ +#endif /* CONFIG_STM32_TIM5_PWM */ -#ifdef CONFIG_STM32F7_TIM8_PWM +#ifdef CONFIG_STM32_TIM8_PWM static struct stm32_pwmchan_s g_pwm8channels[] = { /* TIM8 has 4 channels, 4 complementary */ -#ifdef CONFIG_STM32F7_TIM8_CHANNEL1 +#ifdef CONFIG_STM32_TIM8_CHANNEL1 { .channel = 1, - .mode = CONFIG_STM32F7_TIM8_CH1MODE, + .mode = CONFIG_STM32_TIM8_CH1MODE, #ifdef HAVE_BREAK .brk = { -#ifdef CONFIG_STM32F7_TIM8_BREAK1 +#ifdef CONFIG_STM32_TIM8_BREAK1 .en1 = 1, - .pol1 = CONFIG_STM32F7_TIM8_BRK1POL, + .pol1 = CONFIG_STM32_TIM8_BRK1POL, #endif -#ifdef CONFIG_STM32F7_TIM8_BREAK2 +#ifdef CONFIG_STM32_TIM8_BREAK2 .en2 = 1, - .pol2 = CONFIG_STM32F7_TIM8_BRK2POL, - .flt2 = CONFIG_STM32F7_TIM8_BRK2FLT, + .pol2 = CONFIG_STM32_TIM8_BRK2POL, + .flt2 = CONFIG_STM32_TIM8_BRK2FLT, #endif }, #endif -#ifdef CONFIG_STM32F7_TIM8_CH1OUT +#ifdef CONFIG_STM32_TIM8_CH1OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM8_CH1POL, - .idle = CONFIG_STM32F7_TIM8_CH1IDLE, + .pol = CONFIG_STM32_TIM8_CH1POL, + .idle = CONFIG_STM32_TIM8_CH1IDLE, .pincfg = PWM_TIM8_CH1CFG, }, #endif -#ifdef CONFIG_STM32F7_TIM8_CH1NOUT +#ifdef CONFIG_STM32_TIM8_CH1NOUT .out2 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM8_CH1NPOL, - .idle = CONFIG_STM32F7_TIM8_CH1NIDLE, + .pol = CONFIG_STM32_TIM8_CH1NPOL, + .idle = CONFIG_STM32_TIM8_CH1NIDLE, .pincfg = PWM_TIM8_CH1NCFG, } #endif }, #endif -#ifdef CONFIG_STM32F7_TIM8_CHANNEL2 +#ifdef CONFIG_STM32_TIM8_CHANNEL2 { .channel = 2, - .mode = CONFIG_STM32F7_TIM8_CH2MODE, -#ifdef CONFIG_STM32F7_TIM8_CH2OUT + .mode = CONFIG_STM32_TIM8_CH2MODE, +#ifdef CONFIG_STM32_TIM8_CH2OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM8_CH2POL, - .idle = CONFIG_STM32F7_TIM8_CH2IDLE, + .pol = CONFIG_STM32_TIM8_CH2POL, + .idle = CONFIG_STM32_TIM8_CH2IDLE, .pincfg = PWM_TIM8_CH2CFG, }, #endif -#ifdef CONFIG_STM32F7_TIM8_CH2NOUT +#ifdef CONFIG_STM32_TIM8_CH2NOUT .out2 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM8_CH2NPOL, - .idle = CONFIG_STM32F7_TIM8_CH2NIDLE, + .pol = CONFIG_STM32_TIM8_CH2NPOL, + .idle = CONFIG_STM32_TIM8_CH2NIDLE, .pincfg = PWM_TIM8_CH2NCFG, } #endif }, #endif -#ifdef CONFIG_STM32F7_TIM8_CHANNEL3 +#ifdef CONFIG_STM32_TIM8_CHANNEL3 { .channel = 3, - .mode = CONFIG_STM32F7_TIM8_CH3MODE, -#ifdef CONFIG_STM32F7_TIM8_CH3OUT + .mode = CONFIG_STM32_TIM8_CH3MODE, +#ifdef CONFIG_STM32_TIM8_CH3OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM8_CH3POL, - .idle = CONFIG_STM32F7_TIM8_CH3IDLE, + .pol = CONFIG_STM32_TIM8_CH3POL, + .idle = CONFIG_STM32_TIM8_CH3IDLE, .pincfg = PWM_TIM8_CH3CFG, }, #endif -#ifdef CONFIG_STM32F7_TIM8_CH3NOUT +#ifdef CONFIG_STM32_TIM8_CH3NOUT .out2 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM8_CH3NPOL, - .idle = CONFIG_STM32F7_TIM8_CH3NIDLE, + .pol = CONFIG_STM32_TIM8_CH3NPOL, + .idle = CONFIG_STM32_TIM8_CH3NIDLE, .pincfg = PWM_TIM8_CH3NCFG, } #endif }, #endif -#ifdef CONFIG_STM32F7_TIM8_CHANNEL4 +#ifdef CONFIG_STM32_TIM8_CHANNEL4 { .channel = 4, - .mode = CONFIG_STM32F7_TIM8_CH4MODE, -#ifdef CONFIG_STM32F7_TIM8_CH4OUT + .mode = CONFIG_STM32_TIM8_CH4MODE, +#ifdef CONFIG_STM32_TIM8_CH4OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM8_CH4POL, - .idle = CONFIG_STM32F7_TIM8_CH4IDLE, + .pol = CONFIG_STM32_TIM8_CH4POL, + .idle = CONFIG_STM32_TIM8_CH4IDLE, .pincfg = PWM_TIM8_CH4CFG, } #endif }, #endif -#ifdef CONFIG_STM32F7_TIM8_CHANNEL5 +#ifdef CONFIG_STM32_TIM8_CHANNEL5 { .channel = 5, - .mode = CONFIG_STM32F7_TIM8_CH5MODE, -#ifdef CONFIG_STM32F7_TIM8_CH5OUT + .mode = CONFIG_STM32_TIM8_CH5MODE, +#ifdef CONFIG_STM32_TIM8_CH5OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM8_CH5POL, - .idle = CONFIG_STM32F7_TIM8_CH5IDLE, + .pol = CONFIG_STM32_TIM8_CH5POL, + .idle = CONFIG_STM32_TIM8_CH5IDLE, .pincfg = 0, /* Not available externally */ } #endif }, #endif -#ifdef CONFIG_STM32F7_TIM8_CHANNEL6 +#ifdef CONFIG_STM32_TIM8_CHANNEL6 { .channel = 6, - .mode = CONFIG_STM32F7_TIM8_CH6MODE, -#ifdef CONFIG_STM32F7_TIM8_CH6OUT + .mode = CONFIG_STM32_TIM8_CH6MODE, +#ifdef CONFIG_STM32_TIM8_CH6OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM8_CH6POL, - .idle = CONFIG_STM32F7_TIM8_CH6IDLE, + .pol = CONFIG_STM32_TIM8_CH6POL, + .idle = CONFIG_STM32_TIM8_CH6IDLE, .pincfg = 0, /* Not available externally */ } #endif @@ -1059,18 +1059,18 @@ static struct stm32_pwmchan_s g_pwm8channels[] = static struct stm32_pwmtimer_s g_pwm8dev = { .ops = &g_pwmops, -#ifdef CONFIG_STM32F7_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS .llops = &g_llpwmops, #endif .timid = 8, .chan_num = PWM_TIM8_NCHANNELS, .channels = g_pwm8channels, .timtype = TIMTYPE_TIM8, - .mode = CONFIG_STM32F7_TIM8_MODE, - .lock = CONFIG_STM32F7_TIM8_LOCK, - .t_dts = CONFIG_STM32F7_TIM8_TDTS, + .mode = CONFIG_STM32_TIM8_MODE, + .lock = CONFIG_STM32_TIM8_LOCK, + .t_dts = CONFIG_STM32_TIM8_TDTS, #ifdef HAVE_PWM_COMPLEMENTARY - .deadtime = CONFIG_STM32F7_TIM8_DEADTIME, + .deadtime = CONFIG_STM32_TIM8_DEADTIME, #endif #if defined(HAVE_TRGO) && defined(STM32_TIM8_TRGO) .trgo = STM32_TIM8_TRGO, @@ -1078,40 +1078,40 @@ static struct stm32_pwmtimer_s g_pwm8dev = .base = STM32_TIM8_BASE, .pclk = TIMCLK_TIM8, }; -#endif /* CONFIG_STM32F7_TIM8_PWM */ +#endif /* CONFIG_STM32_TIM8_PWM */ -#ifdef CONFIG_STM32F7_TIM9_PWM +#ifdef CONFIG_STM32_TIM9_PWM static struct stm32_pwmchan_s g_pwm9channels[] = { /* TIM9 has 2 channels */ -#ifdef CONFIG_STM32F7_TIM9_CHANNEL1 +#ifdef CONFIG_STM32_TIM9_CHANNEL1 { .channel = 1, - .mode = CONFIG_STM32F7_TIM9_CH1MODE, -#ifdef CONFIG_STM32F7_TIM9_CH1OUT + .mode = CONFIG_STM32_TIM9_CH1MODE, +#ifdef CONFIG_STM32_TIM9_CH1OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM9_CH1POL, - .idle = CONFIG_STM32F7_TIM9_CH1IDLE, + .pol = CONFIG_STM32_TIM9_CH1POL, + .idle = CONFIG_STM32_TIM9_CH1IDLE, .pincfg = PWM_TIM9_CH1CFG, } #endif /* No complementary outputs */ }, #endif -#ifdef CONFIG_STM32F7_TIM9_CHANNEL2 +#ifdef CONFIG_STM32_TIM9_CHANNEL2 { .channel = 2, - .mode = CONFIG_STM32F7_TIM9_CH2MODE, -#ifdef CONFIG_STM32F7_TIM9_CH2OUT + .mode = CONFIG_STM32_TIM9_CH2MODE, +#ifdef CONFIG_STM32_TIM9_CH2OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM9_CH2POL, - .idle = CONFIG_STM32F7_TIM9_CH2IDLE, + .pol = CONFIG_STM32_TIM9_CH2POL, + .idle = CONFIG_STM32_TIM9_CH2IDLE, .pincfg = PWM_TIM9_CH2CFG, } #endif @@ -1123,7 +1123,7 @@ static struct stm32_pwmchan_s g_pwm9channels[] = static struct stm32_pwmtimer_s g_pwm9dev = { .ops = &g_pwmops, -#ifdef CONFIG_STM32F7_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS .llops = &g_llpwmops, #endif .timid = 9, @@ -1142,24 +1142,24 @@ static struct stm32_pwmtimer_s g_pwm9dev = .base = STM32_TIM9_BASE, .pclk = TIMCLK_TIM9, }; -#endif /* CONFIG_STM32F7_TIM9_PWM */ +#endif /* CONFIG_STM32_TIM9_PWM */ -#ifdef CONFIG_STM32F7_TIM10_PWM +#ifdef CONFIG_STM32_TIM10_PWM static struct stm32_pwmchan_s g_pwm10channels[] = { /* TIM10 has 1 channel */ -#ifdef CONFIG_STM32F7_TIM10_CHANNEL1 +#ifdef CONFIG_STM32_TIM10_CHANNEL1 { .channel = 1, - .mode = CONFIG_STM32F7_TIM10_CH1MODE, -#ifdef CONFIG_STM32F7_TIM10_CH1OUT + .mode = CONFIG_STM32_TIM10_CH1MODE, +#ifdef CONFIG_STM32_TIM10_CH1OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM10_CH1POL, - .idle = CONFIG_STM32F7_TIM10_CH1IDLE, + .pol = CONFIG_STM32_TIM10_CH1POL, + .idle = CONFIG_STM32_TIM10_CH1IDLE, .pincfg = PWM_TIM10_CH1CFG, } #endif @@ -1171,7 +1171,7 @@ static struct stm32_pwmchan_s g_pwm10channels[] = static struct stm32_pwmtimer_s g_pwm10dev = { .ops = &g_pwmops, -#ifdef CONFIG_STM32F7_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS .llops = &g_llpwmops, #endif .timid = 10, @@ -1190,24 +1190,24 @@ static struct stm32_pwmtimer_s g_pwm10dev = .base = STM32_TIM10_BASE, .pclk = TIMCLK_TIM10, }; -#endif /* CONFIG_STM32F7_TIM10_PWM */ +#endif /* CONFIG_STM32_TIM10_PWM */ -#ifdef CONFIG_STM32F7_TIM11_PWM +#ifdef CONFIG_STM32_TIM11_PWM static struct stm32_pwmchan_s g_pwm11channels[] = { /* TIM11 has 1 channel */ -#ifdef CONFIG_STM32F7_TIM11_CHANNEL1 +#ifdef CONFIG_STM32_TIM11_CHANNEL1 { .channel = 1, - .mode = CONFIG_STM32F7_TIM11_CH1MODE, -#ifdef CONFIG_STM32F7_TIM11_CH1OUT + .mode = CONFIG_STM32_TIM11_CH1MODE, +#ifdef CONFIG_STM32_TIM11_CH1OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM11_CH1POL, - .idle = CONFIG_STM32F7_TIM11_CH1IDLE, + .pol = CONFIG_STM32_TIM11_CH1POL, + .idle = CONFIG_STM32_TIM11_CH1IDLE, .pincfg = PWM_TIM11_CH1CFG, } #endif @@ -1219,7 +1219,7 @@ static struct stm32_pwmchan_s g_pwm11channels[] = static struct stm32_pwmtimer_s g_pwm11dev = { .ops = &g_pwmops, -#ifdef CONFIG_STM32F7_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS .llops = &g_llpwmops, #endif .timid = 11, @@ -1238,40 +1238,40 @@ static struct stm32_pwmtimer_s g_pwm11dev = .base = STM32_TIM11_BASE, .pclk = TIMCLK_TIM11, }; -#endif /* CONFIG_STM32F7_TIM11_PWM */ +#endif /* CONFIG_STM32_TIM11_PWM */ -#ifdef CONFIG_STM32F7_TIM12_PWM +#ifdef CONFIG_STM32_TIM12_PWM static struct stm32_pwmchan_s g_pwm12channels[] = { /* TIM12 has 2 channels */ -#ifdef CONFIG_STM32F7_TIM12_CHANNEL1 +#ifdef CONFIG_STM32_TIM12_CHANNEL1 { .channel = 1, - .mode = CONFIG_STM32F7_TIM12_CH1MODE, -#ifdef CONFIG_STM32F7_TIM12_CH1OUT + .mode = CONFIG_STM32_TIM12_CH1MODE, +#ifdef CONFIG_STM32_TIM12_CH1OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM12_CH1POL, - .idle = CONFIG_STM32F7_TIM12_CH1IDLE, + .pol = CONFIG_STM32_TIM12_CH1POL, + .idle = CONFIG_STM32_TIM12_CH1IDLE, .pincfg = PWM_TIM12_CH1CFG, } #endif /* No complementary outputs */ }, #endif -#ifdef CONFIG_STM32F7_TIM12_CHANNEL2 +#ifdef CONFIG_STM32_TIM12_CHANNEL2 { .channel = 2, - .mode = CONFIG_STM32F7_TIM12_CH2MODE, -#ifdef CONFIG_STM32F7_TIM12_CH2OUT + .mode = CONFIG_STM32_TIM12_CH2MODE, +#ifdef CONFIG_STM32_TIM12_CH2OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM12_CH2POL, - .idle = CONFIG_STM32F7_TIM12_CH2IDLE, + .pol = CONFIG_STM32_TIM12_CH2POL, + .idle = CONFIG_STM32_TIM12_CH2IDLE, .pincfg = PWM_TIM12_CH2CFG, } #endif @@ -1283,7 +1283,7 @@ static struct stm32_pwmchan_s g_pwm12channels[] = static struct stm32_pwmtimer_s g_pwm12dev = { .ops = &g_pwmops, -#ifdef CONFIG_STM32F7_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS .llops = &g_llpwmops, #endif .timid = 12, @@ -1302,24 +1302,24 @@ static struct stm32_pwmtimer_s g_pwm12dev = .base = STM32_TIM12_BASE, .pclk = TIMCLK_TIM12, }; -#endif /* CONFIG_STM32F7_TIM12_PWM */ +#endif /* CONFIG_STM32_TIM12_PWM */ -#ifdef CONFIG_STM32F7_TIM13_PWM +#ifdef CONFIG_STM32_TIM13_PWM static struct stm32_pwmchan_s g_pwm13channels[] = { /* TIM13 has 1 channel */ -#ifdef CONFIG_STM32F7_TIM13_CHANNEL1 +#ifdef CONFIG_STM32_TIM13_CHANNEL1 { .channel = 1, - .mode = CONFIG_STM32F7_TIM13_CH1MODE, -#ifdef CONFIG_STM32F7_TIM13_CH1OUT + .mode = CONFIG_STM32_TIM13_CH1MODE, +#ifdef CONFIG_STM32_TIM13_CH1OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM13_CH1POL, - .idle = CONFIG_STM32F7_TIM13_CH1IDLE, + .pol = CONFIG_STM32_TIM13_CH1POL, + .idle = CONFIG_STM32_TIM13_CH1IDLE, .pincfg = PWM_TIM13_CH1CFG, } #endif @@ -1331,7 +1331,7 @@ static struct stm32_pwmchan_s g_pwm13channels[] = static struct stm32_pwmtimer_s g_pwm13dev = { .ops = &g_pwmops, -#ifdef CONFIG_STM32F7_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS .llops = &g_llpwmops, #endif .timid = 13, @@ -1350,24 +1350,24 @@ static struct stm32_pwmtimer_s g_pwm13dev = .base = STM32_TIM13_BASE, .pclk = TIMCLK_TIM13, }; -#endif /* CONFIG_STM32F7_TIM13_PWM */ +#endif /* CONFIG_STM32_TIM13_PWM */ -#ifdef CONFIG_STM32F7_TIM14_PWM +#ifdef CONFIG_STM32_TIM14_PWM static struct stm32_pwmchan_s g_pwm14channels[] = { /* TIM14 has 1 channel */ -#ifdef CONFIG_STM32F7_TIM14_CHANNEL1 +#ifdef CONFIG_STM32_TIM14_CHANNEL1 { .channel = 1, - .mode = CONFIG_STM32F7_TIM14_CH1MODE, -#ifdef CONFIG_STM32F7_TIM14_CH1OUT + .mode = CONFIG_STM32_TIM14_CH1MODE, +#ifdef CONFIG_STM32_TIM14_CH1OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM14_CH1POL, - .idle = CONFIG_STM32F7_TIM14_CH1IDLE, + .pol = CONFIG_STM32_TIM14_CH1POL, + .idle = CONFIG_STM32_TIM14_CH1IDLE, .pincfg = PWM_TIM14_CH1CFG, } #endif @@ -1379,7 +1379,7 @@ static struct stm32_pwmchan_s g_pwm14channels[] = static struct stm32_pwmtimer_s g_pwm14dev = { .ops = &g_pwmops, -#ifdef CONFIG_STM32F7_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS .llops = &g_llpwmops, #endif .timid = 14, @@ -1398,7 +1398,7 @@ static struct stm32_pwmtimer_s g_pwm14dev = .base = STM32_TIM14_BASE, .pclk = TIMCLK_TIM14, }; -#endif /* CONFIG_STM32F7_TIM14_PWM */ +#endif /* CONFIG_STM32_TIM14_PWM */ /**************************************************************************** * Private Functions @@ -1698,7 +1698,7 @@ static int pwm_ccr_update(struct pwm_lowerhalf_s *dev, uint8_t index, * Name: pwm_ccr_get ****************************************************************************/ -#ifdef CONFIG_STM32F7_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS static uint32_t pwm_ccr_get(struct pwm_lowerhalf_s *dev, uint8_t index) { struct stm32_pwmtimer_s *priv = (struct stm32_pwmtimer_s *)dev; @@ -1753,7 +1753,7 @@ static uint32_t pwm_ccr_get(struct pwm_lowerhalf_s *dev, uint8_t index) return pwm_getreg(priv, offset); } -#endif /* CONFIG_STM32F7_PWM_LL_OPS */ +#endif /* CONFIG_STM32_PWM_LL_OPS */ /**************************************************************************** * Name: pwm_arr_update @@ -1798,7 +1798,7 @@ static int pwm_rcr_update(struct pwm_lowerhalf_s *dev, uint16_t rcr) } #endif -#ifdef CONFIG_STM32F7_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS /**************************************************************************** * Name: pwm_rcr_get ****************************************************************************/ @@ -2486,7 +2486,7 @@ static int pwm_outputs_enable(struct pwm_lowerhalf_s *dev, return OK; } -#if defined(HAVE_PWM_COMPLEMENTARY) && defined(CONFIG_STM32F7_PWM_LL_OPS) +#if defined(HAVE_PWM_COMPLEMENTARY) && defined(CONFIG_STM32_PWM_LL_OPS) /**************************************************************************** * Name: pwm_deadtime_update @@ -3033,7 +3033,7 @@ static int pwm_set_apb_clock(struct stm32_pwmtimer_s *priv, bool on) switch (priv->timid) { -#ifdef CONFIG_STM32F7_TIM1_PWM +#ifdef CONFIG_STM32_TIM1_PWM case 1: { regaddr = TIMRCCEN_TIM1; @@ -3042,7 +3042,7 @@ static int pwm_set_apb_clock(struct stm32_pwmtimer_s *priv, bool on) } #endif -#ifdef CONFIG_STM32F7_TIM2_PWM +#ifdef CONFIG_STM32_TIM2_PWM case 2: { regaddr = TIMRCCEN_TIM2; @@ -3051,7 +3051,7 @@ static int pwm_set_apb_clock(struct stm32_pwmtimer_s *priv, bool on) } #endif -#ifdef CONFIG_STM32F7_TIM3_PWM +#ifdef CONFIG_STM32_TIM3_PWM case 3: { regaddr = TIMRCCEN_TIM3; @@ -3060,7 +3060,7 @@ static int pwm_set_apb_clock(struct stm32_pwmtimer_s *priv, bool on) } #endif -#ifdef CONFIG_STM32F7_TIM4_PWM +#ifdef CONFIG_STM32_TIM4_PWM case 4: { regaddr = TIMRCCEN_TIM4; @@ -3069,7 +3069,7 @@ static int pwm_set_apb_clock(struct stm32_pwmtimer_s *priv, bool on) } #endif -#ifdef CONFIG_STM32F7_TIM5_PWM +#ifdef CONFIG_STM32_TIM5_PWM case 5: { regaddr = TIMRCCEN_TIM5; @@ -3078,7 +3078,7 @@ static int pwm_set_apb_clock(struct stm32_pwmtimer_s *priv, bool on) } #endif -#ifdef CONFIG_STM32F7_TIM8_PWM +#ifdef CONFIG_STM32_TIM8_PWM case 8: { regaddr = TIMRCCEN_TIM8; @@ -3087,7 +3087,7 @@ static int pwm_set_apb_clock(struct stm32_pwmtimer_s *priv, bool on) } #endif -#ifdef CONFIG_STM32F7_TIM9_PWM +#ifdef CONFIG_STM32_TIM9_PWM case 9: { regaddr = TIMRCCEN_TIM9; @@ -3096,7 +3096,7 @@ static int pwm_set_apb_clock(struct stm32_pwmtimer_s *priv, bool on) } #endif -#ifdef CONFIG_STM32F7_TIM10_PWM +#ifdef CONFIG_STM32_TIM10_PWM case 10: { regaddr = TIMRCCEN_TIM10; @@ -3105,7 +3105,7 @@ static int pwm_set_apb_clock(struct stm32_pwmtimer_s *priv, bool on) } #endif -#ifdef CONFIG_STM32F7_TIM11_PWM +#ifdef CONFIG_STM32_TIM11_PWM case 11: { regaddr = TIMRCCEN_TIM11; @@ -3114,7 +3114,7 @@ static int pwm_set_apb_clock(struct stm32_pwmtimer_s *priv, bool on) } #endif -#ifdef CONFIG_STM32F7_TIM12_PWM +#ifdef CONFIG_STM32_TIM12_PWM case 12: { regaddr = TIMRCCEN_TIM12; @@ -3123,7 +3123,7 @@ static int pwm_set_apb_clock(struct stm32_pwmtimer_s *priv, bool on) } #endif -#ifdef CONFIG_STM32F7_TIM13_PWM +#ifdef CONFIG_STM32_TIM13_PWM case 13: { regaddr = TIMRCCEN_TIM13; @@ -3132,7 +3132,7 @@ static int pwm_set_apb_clock(struct stm32_pwmtimer_s *priv, bool on) } #endif -#ifdef CONFIG_STM32F7_TIM14_PWM +#ifdef CONFIG_STM32_TIM14_PWM case 14: { regaddr = TIMRCCEN_TIM14; @@ -3520,7 +3520,7 @@ struct pwm_lowerhalf_s *stm32_pwminitialize(int timer) switch (timer) { -#ifdef CONFIG_STM32F7_TIM1_PWM +#ifdef CONFIG_STM32_TIM1_PWM case 1: { lower = &g_pwm1dev; @@ -3531,7 +3531,7 @@ struct pwm_lowerhalf_s *stm32_pwminitialize(int timer) } #endif -#ifdef CONFIG_STM32F7_TIM2_PWM +#ifdef CONFIG_STM32_TIM2_PWM case 2: { lower = &g_pwm2dev; @@ -3539,7 +3539,7 @@ struct pwm_lowerhalf_s *stm32_pwminitialize(int timer) } #endif -#ifdef CONFIG_STM32F7_TIM3_PWM +#ifdef CONFIG_STM32_TIM3_PWM case 3: { lower = &g_pwm3dev; @@ -3547,7 +3547,7 @@ struct pwm_lowerhalf_s *stm32_pwminitialize(int timer) } #endif -#ifdef CONFIG_STM32F7_TIM4_PWM +#ifdef CONFIG_STM32_TIM4_PWM case 4: { lower = &g_pwm4dev; @@ -3555,7 +3555,7 @@ struct pwm_lowerhalf_s *stm32_pwminitialize(int timer) } #endif -#ifdef CONFIG_STM32F7_TIM5_PWM +#ifdef CONFIG_STM32_TIM5_PWM case 5: { lower = &g_pwm5dev; @@ -3563,7 +3563,7 @@ struct pwm_lowerhalf_s *stm32_pwminitialize(int timer) } #endif -#ifdef CONFIG_STM32F7_TIM8_PWM +#ifdef CONFIG_STM32_TIM8_PWM case 8: { lower = &g_pwm8dev; @@ -3574,7 +3574,7 @@ struct pwm_lowerhalf_s *stm32_pwminitialize(int timer) } #endif -#ifdef CONFIG_STM32F7_TIM9_PWM +#ifdef CONFIG_STM32_TIM9_PWM case 9: { lower = &g_pwm9dev; @@ -3582,7 +3582,7 @@ struct pwm_lowerhalf_s *stm32_pwminitialize(int timer) } #endif -#ifdef CONFIG_STM32F7_TIM10_PWM +#ifdef CONFIG_STM32_TIM10_PWM case 10: { lower = &g_pwm10dev; @@ -3591,7 +3591,7 @@ struct pwm_lowerhalf_s *stm32_pwminitialize(int timer) #endif -#ifdef CONFIG_STM32F7_TIM11_PWM +#ifdef CONFIG_STM32_TIM11_PWM case 11: { lower = &g_pwm11dev; @@ -3599,7 +3599,7 @@ struct pwm_lowerhalf_s *stm32_pwminitialize(int timer) } #endif -#ifdef CONFIG_STM32F7_TIM12_PWM +#ifdef CONFIG_STM32_TIM12_PWM case 12: { lower = &g_pwm12dev; @@ -3607,7 +3607,7 @@ struct pwm_lowerhalf_s *stm32_pwminitialize(int timer) } #endif -#ifdef CONFIG_STM32F7_TIM13_PWM +#ifdef CONFIG_STM32_TIM13_PWM case 13: { lower = &g_pwm13dev; @@ -3615,7 +3615,7 @@ struct pwm_lowerhalf_s *stm32_pwminitialize(int timer) } #endif -#ifdef CONFIG_STM32F7_TIM14_PWM +#ifdef CONFIG_STM32_TIM14_PWM case 14: { lower = &g_pwm14dev; @@ -3635,4 +3635,4 @@ struct pwm_lowerhalf_s *stm32_pwminitialize(int timer) return (struct pwm_lowerhalf_s *)lower; } -#endif /* CONFIG_STM32F7_PWM */ +#endif /* CONFIG_STM32_PWM */ diff --git a/arch/arm/src/stm32f7/stm32_pwm.h b/arch/arm/src/stm32f7/stm32_pwm.h index 06a7671301ab8..0aa3aed6d7143 100644 --- a/arch/arm/src/stm32f7/stm32_pwm.h +++ b/arch/arm/src/stm32f7/stm32_pwm.h @@ -39,7 +39,7 @@ #include "chip.h" -#ifdef CONFIG_STM32F7_PWM +#ifdef CONFIG_STM32_PWM # include # include "hardware/stm32_tim.h" #endif @@ -52,89 +52,89 @@ /* Timer devices may be used for different purposes. One special purpose is * to generate modulated outputs for such things as motor control. - * If CONFIG_STM32F7_TIMn is defined then the CONFIG_STM32F7_TIMn_PWM must + * If CONFIG_STM32_TIMn is defined then the CONFIG_STM32_TIMn_PWM must * also be defined to indicate that timer "n" is intended to be used for * pulsed output signal generation. */ -#ifndef CONFIG_STM32F7_TIM1 -# undef CONFIG_STM32F7_TIM1_PWM +#ifndef CONFIG_STM32_TIM1 +# undef CONFIG_STM32_TIM1_PWM #endif -#ifndef CONFIG_STM32F7_TIM2 -# undef CONFIG_STM32F7_TIM2_PWM +#ifndef CONFIG_STM32_TIM2 +# undef CONFIG_STM32_TIM2_PWM #endif -#ifndef CONFIG_STM32F7_TIM3 -# undef CONFIG_STM32F7_TIM3_PWM +#ifndef CONFIG_STM32_TIM3 +# undef CONFIG_STM32_TIM3_PWM #endif -#ifndef CONFIG_STM32F7_TIM4 -# undef CONFIG_STM32F7_TIM4_PWM +#ifndef CONFIG_STM32_TIM4 +# undef CONFIG_STM32_TIM4_PWM #endif -#ifndef CONFIG_STM32F7_TIM5 -# undef CONFIG_STM32F7_TIM5_PWM +#ifndef CONFIG_STM32_TIM5 +# undef CONFIG_STM32_TIM5_PWM #endif -#ifndef CONFIG_STM32F7_TIM8 -# undef CONFIG_STM32F7_TIM8_PWM +#ifndef CONFIG_STM32_TIM8 +# undef CONFIG_STM32_TIM8_PWM #endif -#ifndef CONFIG_STM32F7_TIM9 -# undef CONFIG_STM32F7_TIM9_PWM +#ifndef CONFIG_STM32_TIM9 +# undef CONFIG_STM32_TIM9_PWM #endif -#ifndef CONFIG_STM32F7_TIM10 -# undef CONFIG_STM32F7_TIM10_PWM +#ifndef CONFIG_STM32_TIM10 +# undef CONFIG_STM32_TIM10_PWM #endif -#ifndef CONFIG_STM32F7_TIM11 -# undef CONFIG_STM32F7_TIM11_PWM +#ifndef CONFIG_STM32_TIM11 +# undef CONFIG_STM32_TIM11_PWM #endif -#ifndef CONFIG_STM32F7_TIM12 -# undef CONFIG_STM32F7_TIM12_PWM +#ifndef CONFIG_STM32_TIM12 +# undef CONFIG_STM32_TIM12_PWM #endif -#ifndef CONFIG_STM32F7_TIM13 -# undef CONFIG_STM32F7_TIM13_PWM +#ifndef CONFIG_STM32_TIM13 +# undef CONFIG_STM32_TIM13_PWM #endif -#ifndef CONFIG_STM32F7_TIM14 -# undef CONFIG_STM32F7_TIM14_PWM +#ifndef CONFIG_STM32_TIM14 +# undef CONFIG_STM32_TIM14_PWM #endif /* The basic timers (timer 6 and 7) are not capable of generating output * pulses */ -#undef CONFIG_STM32F7_TIM6_PWM -#undef CONFIG_STM32F7_TIM7_PWM +#undef CONFIG_STM32_TIM6_PWM +#undef CONFIG_STM32_TIM7_PWM /* Check if PWM support for any channel is enabled. */ -#ifdef CONFIG_STM32F7_PWM +#ifdef CONFIG_STM32_PWM /* PWM driver channels configuration */ -#ifdef CONFIG_STM32F7_PWM_MULTICHAN +#ifdef CONFIG_STM32_PWM_MULTICHAN -#ifdef CONFIG_STM32F7_TIM1_CHANNEL1 +#ifdef CONFIG_STM32_TIM1_CHANNEL1 # define PWM_TIM1_CHANNEL1 1 #else # define PWM_TIM1_CHANNEL1 0 #endif -#ifdef CONFIG_STM32F7_TIM1_CHANNEL2 +#ifdef CONFIG_STM32_TIM1_CHANNEL2 # define PWM_TIM1_CHANNEL2 1 #else # define PWM_TIM1_CHANNEL2 0 #endif -#ifdef CONFIG_STM32F7_TIM1_CHANNEL3 +#ifdef CONFIG_STM32_TIM1_CHANNEL3 # define PWM_TIM1_CHANNEL3 1 #else # define PWM_TIM1_CHANNEL3 0 #endif -#ifdef CONFIG_STM32F7_TIM1_CHANNEL4 +#ifdef CONFIG_STM32_TIM1_CHANNEL4 # define PWM_TIM1_CHANNEL4 1 #else # define PWM_TIM1_CHANNEL4 0 #endif -#ifdef CONFIG_STM32F7_TIM1_CHANNEL5 +#ifdef CONFIG_STM32_TIM1_CHANNEL5 # define PWM_TIM1_CHANNEL5 1 #else # define PWM_TIM1_CHANNEL5 0 #endif -#ifdef CONFIG_STM32F7_TIM1_CHANNEL6 +#ifdef CONFIG_STM32_TIM1_CHANNEL6 # define PWM_TIM1_CHANNEL6 1 #else # define PWM_TIM1_CHANNEL6 0 @@ -143,22 +143,22 @@ PWM_TIM1_CHANNEL3 + PWM_TIM1_CHANNEL4 + \ PWM_TIM1_CHANNEL5 + PWM_TIM1_CHANNEL6) -#ifdef CONFIG_STM32F7_TIM2_CHANNEL1 +#ifdef CONFIG_STM32_TIM2_CHANNEL1 # define PWM_TIM2_CHANNEL1 1 #else # define PWM_TIM2_CHANNEL1 0 #endif -#ifdef CONFIG_STM32F7_TIM2_CHANNEL2 +#ifdef CONFIG_STM32_TIM2_CHANNEL2 # define PWM_TIM2_CHANNEL2 1 #else # define PWM_TIM2_CHANNEL2 0 #endif -#ifdef CONFIG_STM32F7_TIM2_CHANNEL3 +#ifdef CONFIG_STM32_TIM2_CHANNEL3 # define PWM_TIM2_CHANNEL3 1 #else # define PWM_TIM2_CHANNEL3 0 #endif -#ifdef CONFIG_STM32F7_TIM2_CHANNEL4 +#ifdef CONFIG_STM32_TIM2_CHANNEL4 # define PWM_TIM2_CHANNEL4 1 #else # define PWM_TIM2_CHANNEL4 0 @@ -166,22 +166,22 @@ #define PWM_TIM2_NCHANNELS (PWM_TIM2_CHANNEL1 + PWM_TIM2_CHANNEL2 + \ PWM_TIM2_CHANNEL3 + PWM_TIM2_CHANNEL4) -#ifdef CONFIG_STM32F7_TIM3_CHANNEL1 +#ifdef CONFIG_STM32_TIM3_CHANNEL1 # define PWM_TIM3_CHANNEL1 1 #else # define PWM_TIM3_CHANNEL1 0 #endif -#ifdef CONFIG_STM32F7_TIM3_CHANNEL2 +#ifdef CONFIG_STM32_TIM3_CHANNEL2 # define PWM_TIM3_CHANNEL2 1 #else # define PWM_TIM3_CHANNEL2 0 #endif -#ifdef CONFIG_STM32F7_TIM3_CHANNEL3 +#ifdef CONFIG_STM32_TIM3_CHANNEL3 # define PWM_TIM3_CHANNEL3 1 #else # define PWM_TIM3_CHANNEL3 0 #endif -#ifdef CONFIG_STM32F7_TIM3_CHANNEL4 +#ifdef CONFIG_STM32_TIM3_CHANNEL4 # define PWM_TIM3_CHANNEL4 1 #else # define PWM_TIM3_CHANNEL4 0 @@ -189,22 +189,22 @@ #define PWM_TIM3_NCHANNELS (PWM_TIM3_CHANNEL1 + PWM_TIM3_CHANNEL2 + \ PWM_TIM3_CHANNEL3 + PWM_TIM3_CHANNEL4) -#ifdef CONFIG_STM32F7_TIM4_CHANNEL1 +#ifdef CONFIG_STM32_TIM4_CHANNEL1 # define PWM_TIM4_CHANNEL1 1 #else # define PWM_TIM4_CHANNEL1 0 #endif -#ifdef CONFIG_STM32F7_TIM4_CHANNEL2 +#ifdef CONFIG_STM32_TIM4_CHANNEL2 # define PWM_TIM4_CHANNEL2 1 #else # define PWM_TIM4_CHANNEL2 0 #endif -#ifdef CONFIG_STM32F7_TIM4_CHANNEL3 +#ifdef CONFIG_STM32_TIM4_CHANNEL3 # define PWM_TIM4_CHANNEL3 1 #else # define PWM_TIM4_CHANNEL3 0 #endif -#ifdef CONFIG_STM32F7_TIM4_CHANNEL4 +#ifdef CONFIG_STM32_TIM4_CHANNEL4 # define PWM_TIM4_CHANNEL4 1 #else # define PWM_TIM4_CHANNEL4 0 @@ -212,22 +212,22 @@ #define PWM_TIM4_NCHANNELS (PWM_TIM4_CHANNEL1 + PWM_TIM4_CHANNEL2 + \ PWM_TIM4_CHANNEL3 + PWM_TIM4_CHANNEL4) -#ifdef CONFIG_STM32F7_TIM5_CHANNEL1 +#ifdef CONFIG_STM32_TIM5_CHANNEL1 # define PWM_TIM5_CHANNEL1 1 #else # define PWM_TIM5_CHANNEL1 0 #endif -#ifdef CONFIG_STM32F7_TIM5_CHANNEL2 +#ifdef CONFIG_STM32_TIM5_CHANNEL2 # define PWM_TIM5_CHANNEL2 1 #else # define PWM_TIM5_CHANNEL2 0 #endif -#ifdef CONFIG_STM32F7_TIM5_CHANNEL3 +#ifdef CONFIG_STM32_TIM5_CHANNEL3 # define PWM_TIM5_CHANNEL3 1 #else # define PWM_TIM5_CHANNEL3 0 #endif -#ifdef CONFIG_STM32F7_TIM5_CHANNEL4 +#ifdef CONFIG_STM32_TIM5_CHANNEL4 # define PWM_TIM5_CHANNEL4 1 #else # define PWM_TIM5_CHANNEL4 0 @@ -235,32 +235,32 @@ #define PWM_TIM5_NCHANNELS (PWM_TIM5_CHANNEL1 + PWM_TIM5_CHANNEL2 + \ PWM_TIM5_CHANNEL3 + PWM_TIM5_CHANNEL4) -#ifdef CONFIG_STM32F7_TIM8_CHANNEL1 +#ifdef CONFIG_STM32_TIM8_CHANNEL1 # define PWM_TIM8_CHANNEL1 1 #else # define PWM_TIM8_CHANNEL1 0 #endif -#ifdef CONFIG_STM32F7_TIM8_CHANNEL2 +#ifdef CONFIG_STM32_TIM8_CHANNEL2 # define PWM_TIM8_CHANNEL2 1 #else # define PWM_TIM8_CHANNEL2 0 #endif -#ifdef CONFIG_STM32F7_TIM8_CHANNEL3 +#ifdef CONFIG_STM32_TIM8_CHANNEL3 # define PWM_TIM8_CHANNEL3 1 #else # define PWM_TIM8_CHANNEL3 0 #endif -#ifdef CONFIG_STM32F7_TIM8_CHANNEL4 +#ifdef CONFIG_STM32_TIM8_CHANNEL4 # define PWM_TIM8_CHANNEL4 1 #else # define PWM_TIM8_CHANNEL4 0 #endif -#ifdef CONFIG_STM32F7_TIM8_CHANNEL5 +#ifdef CONFIG_STM32_TIM8_CHANNEL5 # define PWM_TIM8_CHANNEL5 1 #else # define PWM_TIM8_CHANNEL5 0 #endif -#ifdef CONFIG_STM32F7_TIM8_CHANNEL6 +#ifdef CONFIG_STM32_TIM8_CHANNEL6 # define PWM_TIM8_CHANNEL6 1 #else # define PWM_TIM8_CHANNEL6 0 @@ -269,64 +269,64 @@ PWM_TIM8_CHANNEL3 + PWM_TIM8_CHANNEL4 + \ PWM_TIM8_CHANNEL5 + PWM_TIM8_CHANNEL6) -#ifdef CONFIG_STM32F7_TIM9_CHANNEL1 +#ifdef CONFIG_STM32_TIM9_CHANNEL1 # define PWM_TIM9_CHANNEL1 1 #else # define PWM_TIM9_CHANNEL1 0 #endif -#ifdef CONFIG_STM32F7_TIM9_CHANNEL2 +#ifdef CONFIG_STM32_TIM9_CHANNEL2 # define PWM_TIM9_CHANNEL2 1 #else # define PWM_TIM9_CHANNEL2 0 #endif #define PWM_TIM9_NCHANNELS (PWM_TIM9_CHANNEL1 + PWM_TIM9_CHANNEL2) -#ifdef CONFIG_STM32F7_TIM10_CHANNEL1 +#ifdef CONFIG_STM32_TIM10_CHANNEL1 # define PWM_TIM10_CHANNEL1 1 #else # define PWM_TIM10_CHANNEL1 0 #endif #define PWM_TIM10_NCHANNELS (PWM_TIM10_CHANNEL1) -#ifdef CONFIG_STM32F7_TIM11_CHANNEL1 +#ifdef CONFIG_STM32_TIM11_CHANNEL1 # define PWM_TIM11_CHANNEL1 1 #else # define PWM_TIM11_CHANNEL1 0 #endif #define PWM_TIM11_NCHANNELS (PWM_TIM11_CHANNEL1) -#ifdef CONFIG_STM32F7_TIM12_CHANNEL1 +#ifdef CONFIG_STM32_TIM12_CHANNEL1 # define PWM_TIM12_CHANNEL1 1 #else # define PWM_TIM12_CHANNEL1 0 #endif -#ifdef CONFIG_STM32F7_TIM12_CHANNEL2 +#ifdef CONFIG_STM32_TIM12_CHANNEL2 # define PWM_TIM12_CHANNEL2 1 #else # define PWM_TIM12_CHANNEL2 0 #endif #define PWM_TIM12_NCHANNELS (PWM_TIM12_CHANNEL1 + PWM_TIM12_CHANNEL2) -#ifdef CONFIG_STM32F7_TIM13_CHANNEL1 +#ifdef CONFIG_STM32_TIM13_CHANNEL1 # define PWM_TIM13_CHANNEL1 1 #else # define PWM_TIM13_CHANNEL1 0 #endif #define PWM_TIM13_NCHANNELS (PWM_TIM13_CHANNEL1) -#ifdef CONFIG_STM32F7_TIM14_CHANNEL1 +#ifdef CONFIG_STM32_TIM14_CHANNEL1 # define PWM_TIM14_CHANNEL1 1 #else # define PWM_TIM14_CHANNEL1 0 #endif #define PWM_TIM14_NCHANNELS (PWM_TIM14_CHANNEL1) -#else /* !CONFIG_STM32F7_PWM_MULTICHAN */ +#else /* !CONFIG_STM32_PWM_MULTICHAN */ /* For each timer that is enabled for PWM usage, we need the following * additional configuration settings: * - * CONFIG_STM32F7_TIMx_CHANNEL - Specifies the timer output channel {1,..,4} + * CONFIG_STM32_TIMx_CHANNEL - Specifies the timer output channel {1,..,4} * PWM_TIMx_CHn - One of the values defined in chip/stm32*_pinmap.h. In the * case where there are multiple pin selections, the correct setting must be * provided in the arch/board/board.h file. @@ -336,410 +336,410 @@ * not supported by this driver: Only one output channel per timer. */ -#ifdef CONFIG_STM32F7_TIM1_PWM -# if !defined(CONFIG_STM32F7_TIM1_CHANNEL) -# error "CONFIG_STM32F7_TIM1_CHANNEL must be provided" -# elif CONFIG_STM32F7_TIM1_CHANNEL == 1 -# define CONFIG_STM32F7_TIM1_CHANNEL1 1 -# define CONFIG_STM32F7_TIM1_CH1MODE CONFIG_STM32F7_TIM1_CHMODE -# elif CONFIG_STM32F7_TIM1_CHANNEL == 2 -# define CONFIG_STM32F7_TIM1_CHANNEL2 1 -# define CONFIG_STM32F7_TIM1_CH2MODE CONFIG_STM32F7_TIM1_CHMODE -# elif CONFIG_STM32F7_TIM1_CHANNEL == 3 -# define CONFIG_STM32F7_TIM1_CHANNEL3 1 -# define CONFIG_STM32F7_TIM1_CH3MODE CONFIG_STM32F7_TIM1_CHMODE -# elif CONFIG_STM32F7_TIM1_CHANNEL == 4 -# define CONFIG_STM32F7_TIM1_CHANNEL4 1 -# define CONFIG_STM32F7_TIM1_CH4MODE CONFIG_STM32F7_TIM1_CHMODE +#ifdef CONFIG_STM32_TIM1_PWM +# if !defined(CONFIG_STM32_TIM1_CHANNEL) +# error "CONFIG_STM32_TIM1_CHANNEL must be provided" +# elif CONFIG_STM32_TIM1_CHANNEL == 1 +# define CONFIG_STM32_TIM1_CHANNEL1 1 +# define CONFIG_STM32_TIM1_CH1MODE CONFIG_STM32_TIM1_CHMODE +# elif CONFIG_STM32_TIM1_CHANNEL == 2 +# define CONFIG_STM32_TIM1_CHANNEL2 1 +# define CONFIG_STM32_TIM1_CH2MODE CONFIG_STM32_TIM1_CHMODE +# elif CONFIG_STM32_TIM1_CHANNEL == 3 +# define CONFIG_STM32_TIM1_CHANNEL3 1 +# define CONFIG_STM32_TIM1_CH3MODE CONFIG_STM32_TIM1_CHMODE +# elif CONFIG_STM32_TIM1_CHANNEL == 4 +# define CONFIG_STM32_TIM1_CHANNEL4 1 +# define CONFIG_STM32_TIM1_CH4MODE CONFIG_STM32_TIM1_CHMODE # else -# error "Unsupported value of CONFIG_STM32F7_TIM1_CHANNEL" +# error "Unsupported value of CONFIG_STM32_TIM1_CHANNEL" # endif # define PWM_TIM1_NCHANNELS 1 #endif -#ifdef CONFIG_STM32F7_TIM2_PWM -# if !defined(CONFIG_STM32F7_TIM2_CHANNEL) -# error "CONFIG_STM32F7_TIM2_CHANNEL must be provided" -# elif CONFIG_STM32F7_TIM2_CHANNEL == 1 -# define CONFIG_STM32F7_TIM2_CHANNEL1 1 -# define CONFIG_STM32F7_TIM2_CH1MODE CONFIG_STM32F7_TIM2_CHMODE -# elif CONFIG_STM32F7_TIM2_CHANNEL == 2 -# define CONFIG_STM32F7_TIM2_CHANNEL2 1 -# define CONFIG_STM32F7_TIM2_CH2MODE CONFIG_STM32F7_TIM2_CHMODE -# elif CONFIG_STM32F7_TIM2_CHANNEL == 3 -# define CONFIG_STM32F7_TIM2_CHANNEL3 1 -# define CONFIG_STM32F7_TIM2_CH3MODE CONFIG_STM32F7_TIM2_CHMODE -# elif CONFIG_STM32F7_TIM2_CHANNEL == 4 -# define CONFIG_STM32F7_TIM2_CHANNEL4 1 -# define CONFIG_STM32F7_TIM2_CH4MODE CONFIG_STM32F7_TIM2_CHMODE +#ifdef CONFIG_STM32_TIM2_PWM +# if !defined(CONFIG_STM32_TIM2_CHANNEL) +# error "CONFIG_STM32_TIM2_CHANNEL must be provided" +# elif CONFIG_STM32_TIM2_CHANNEL == 1 +# define CONFIG_STM32_TIM2_CHANNEL1 1 +# define CONFIG_STM32_TIM2_CH1MODE CONFIG_STM32_TIM2_CHMODE +# elif CONFIG_STM32_TIM2_CHANNEL == 2 +# define CONFIG_STM32_TIM2_CHANNEL2 1 +# define CONFIG_STM32_TIM2_CH2MODE CONFIG_STM32_TIM2_CHMODE +# elif CONFIG_STM32_TIM2_CHANNEL == 3 +# define CONFIG_STM32_TIM2_CHANNEL3 1 +# define CONFIG_STM32_TIM2_CH3MODE CONFIG_STM32_TIM2_CHMODE +# elif CONFIG_STM32_TIM2_CHANNEL == 4 +# define CONFIG_STM32_TIM2_CHANNEL4 1 +# define CONFIG_STM32_TIM2_CH4MODE CONFIG_STM32_TIM2_CHMODE # else -# error "Unsupported value of CONFIG_STM32F7_TIM2_CHANNEL" +# error "Unsupported value of CONFIG_STM32_TIM2_CHANNEL" # endif # define PWM_TIM2_NCHANNELS 1 #endif -#ifdef CONFIG_STM32F7_TIM3_PWM -# if !defined(CONFIG_STM32F7_TIM3_CHANNEL) -# error "CONFIG_STM32F7_TIM3_CHANNEL must be provided" -# elif CONFIG_STM32F7_TIM3_CHANNEL == 1 -# define CONFIG_STM32F7_TIM3_CHANNEL1 1 -# define CONFIG_STM32F7_TIM3_CH1MODE CONFIG_STM32F7_TIM3_CHMODE -# elif CONFIG_STM32F7_TIM3_CHANNEL == 2 -# define CONFIG_STM32F7_TIM3_CHANNEL2 1 -# define CONFIG_STM32F7_TIM3_CH2MODE CONFIG_STM32F7_TIM3_CHMODE -# elif CONFIG_STM32F7_TIM3_CHANNEL == 3 -# define CONFIG_STM32F7_TIM3_CHANNEL3 1 -# define CONFIG_STM32F7_TIM3_CH3MODE CONFIG_STM32F7_TIM3_CHMODE -# elif CONFIG_STM32F7_TIM3_CHANNEL == 4 -# define CONFIG_STM32F7_TIM3_CHANNEL4 1 -# define CONFIG_STM32F7_TIM3_CH4MODE CONFIG_STM32F7_TIM3_CHMODE +#ifdef CONFIG_STM32_TIM3_PWM +# if !defined(CONFIG_STM32_TIM3_CHANNEL) +# error "CONFIG_STM32_TIM3_CHANNEL must be provided" +# elif CONFIG_STM32_TIM3_CHANNEL == 1 +# define CONFIG_STM32_TIM3_CHANNEL1 1 +# define CONFIG_STM32_TIM3_CH1MODE CONFIG_STM32_TIM3_CHMODE +# elif CONFIG_STM32_TIM3_CHANNEL == 2 +# define CONFIG_STM32_TIM3_CHANNEL2 1 +# define CONFIG_STM32_TIM3_CH2MODE CONFIG_STM32_TIM3_CHMODE +# elif CONFIG_STM32_TIM3_CHANNEL == 3 +# define CONFIG_STM32_TIM3_CHANNEL3 1 +# define CONFIG_STM32_TIM3_CH3MODE CONFIG_STM32_TIM3_CHMODE +# elif CONFIG_STM32_TIM3_CHANNEL == 4 +# define CONFIG_STM32_TIM3_CHANNEL4 1 +# define CONFIG_STM32_TIM3_CH4MODE CONFIG_STM32_TIM3_CHMODE # else -# error "Unsupported value of CONFIG_STM32F7_TIM3_CHANNEL" +# error "Unsupported value of CONFIG_STM32_TIM3_CHANNEL" # endif # define PWM_TIM3_NCHANNELS 1 #endif -#ifdef CONFIG_STM32F7_TIM4_PWM -# if !defined(CONFIG_STM32F7_TIM4_CHANNEL) -# error "CONFIG_STM32F7_TIM4_CHANNEL must be provided" -# elif CONFIG_STM32F7_TIM4_CHANNEL == 1 -# define CONFIG_STM32F7_TIM4_CHANNEL1 1 -# define CONFIG_STM32F7_TIM4_CH1MODE CONFIG_STM32F7_TIM4_CHMODE -# elif CONFIG_STM32F7_TIM4_CHANNEL == 2 -# define CONFIG_STM32F7_TIM4_CHANNEL2 1 -# define CONFIG_STM32F7_TIM4_CH2MODE CONFIG_STM32F7_TIM4_CHMODE -# elif CONFIG_STM32F7_TIM4_CHANNEL == 3 -# define CONFIG_STM32F7_TIM4_CHANNEL3 1 -# define CONFIG_STM32F7_TIM4_CH3MODE CONFIG_STM32F7_TIM4_CHMODE -# elif CONFIG_STM32F7_TIM4_CHANNEL == 4 -# define CONFIG_STM32F7_TIM4_CHANNEL4 1 -# define CONFIG_STM32F7_TIM4_CH4MODE CONFIG_STM32F7_TIM4_CHMODE +#ifdef CONFIG_STM32_TIM4_PWM +# if !defined(CONFIG_STM32_TIM4_CHANNEL) +# error "CONFIG_STM32_TIM4_CHANNEL must be provided" +# elif CONFIG_STM32_TIM4_CHANNEL == 1 +# define CONFIG_STM32_TIM4_CHANNEL1 1 +# define CONFIG_STM32_TIM4_CH1MODE CONFIG_STM32_TIM4_CHMODE +# elif CONFIG_STM32_TIM4_CHANNEL == 2 +# define CONFIG_STM32_TIM4_CHANNEL2 1 +# define CONFIG_STM32_TIM4_CH2MODE CONFIG_STM32_TIM4_CHMODE +# elif CONFIG_STM32_TIM4_CHANNEL == 3 +# define CONFIG_STM32_TIM4_CHANNEL3 1 +# define CONFIG_STM32_TIM4_CH3MODE CONFIG_STM32_TIM4_CHMODE +# elif CONFIG_STM32_TIM4_CHANNEL == 4 +# define CONFIG_STM32_TIM4_CHANNEL4 1 +# define CONFIG_STM32_TIM4_CH4MODE CONFIG_STM32_TIM4_CHMODE # else -# error "Unsupported value of CONFIG_STM32F7_TIM4_CHANNEL" +# error "Unsupported value of CONFIG_STM32_TIM4_CHANNEL" # endif # define PWM_TIM4_NCHANNELS 1 #endif -#ifdef CONFIG_STM32F7_TIM5_PWM -# if !defined(CONFIG_STM32F7_TIM5_CHANNEL) -# error "CONFIG_STM32F7_TIM5_CHANNEL must be provided" -# elif CONFIG_STM32F7_TIM5_CHANNEL == 1 -# define CONFIG_STM32F7_TIM5_CHANNEL1 1 -# define CONFIG_STM32F7_TIM5_CH1MODE CONFIG_STM32F7_TIM5_CHMODE -# elif CONFIG_STM32F7_TIM5_CHANNEL == 2 -# define CONFIG_STM32F7_TIM5_CHANNEL2 1 -# define CONFIG_STM32F7_TIM5_CH2MODE CONFIG_STM32F7_TIM5_CHMODE -# elif CONFIG_STM32F7_TIM5_CHANNEL == 3 -# define CONFIG_STM32F7_TIM5_CHANNEL3 1 -# define CONFIG_STM32F7_TIM5_CH3MODE CONFIG_STM32F7_TIM5_CHMODE -# elif CONFIG_STM32F7_TIM5_CHANNEL == 4 -# define CONFIG_STM32F7_TIM5_CHANNEL4 1 -# define CONFIG_STM32F7_TIM5_CH4MODE CONFIG_STM32F7_TIM5_CHMODE +#ifdef CONFIG_STM32_TIM5_PWM +# if !defined(CONFIG_STM32_TIM5_CHANNEL) +# error "CONFIG_STM32_TIM5_CHANNEL must be provided" +# elif CONFIG_STM32_TIM5_CHANNEL == 1 +# define CONFIG_STM32_TIM5_CHANNEL1 1 +# define CONFIG_STM32_TIM5_CH1MODE CONFIG_STM32_TIM5_CHMODE +# elif CONFIG_STM32_TIM5_CHANNEL == 2 +# define CONFIG_STM32_TIM5_CHANNEL2 1 +# define CONFIG_STM32_TIM5_CH2MODE CONFIG_STM32_TIM5_CHMODE +# elif CONFIG_STM32_TIM5_CHANNEL == 3 +# define CONFIG_STM32_TIM5_CHANNEL3 1 +# define CONFIG_STM32_TIM5_CH3MODE CONFIG_STM32_TIM5_CHMODE +# elif CONFIG_STM32_TIM5_CHANNEL == 4 +# define CONFIG_STM32_TIM5_CHANNEL4 1 +# define CONFIG_STM32_TIM5_CH4MODE CONFIG_STM32_TIM5_CHMODE # else -# error "Unsupported value of CONFIG_STM32F7_TIM5_CHANNEL" +# error "Unsupported value of CONFIG_STM32_TIM5_CHANNEL" # endif # define PWM_TIM5_NCHANNELS 1 #endif -#ifdef CONFIG_STM32F7_TIM8_PWM -# if !defined(CONFIG_STM32F7_TIM8_CHANNEL) -# error "CONFIG_STM32F7_TIM8_CHANNEL must be provided" -# elif CONFIG_STM32F7_TIM8_CHANNEL == 1 -# define CONFIG_STM32F7_TIM8_CHANNEL1 1 -# define CONFIG_STM32F7_TIM8_CH1MODE CONFIG_STM32F7_TIM8_CHMODE -# elif CONFIG_STM32F7_TIM8_CHANNEL == 2 -# define CONFIG_STM32F7_TIM8_CHANNEL2 1 -# define CONFIG_STM32F7_TIM8_CH2MODE CONFIG_STM32F7_TIM8_CHMODE -# elif CONFIG_STM32F7_TIM8_CHANNEL == 3 -# define CONFIG_STM32F7_TIM8_CHANNEL3 1 -# define CONFIG_STM32F7_TIM8_CH3MODE CONFIG_STM32F7_TIM8_CHMODE -# elif CONFIG_STM32F7_TIM8_CHANNEL == 4 -# define CONFIG_STM32F7_TIM8_CHANNEL4 1 -# define CONFIG_STM32F7_TIM8_CH4MODE CONFIG_STM32F7_TIM8_CHMODE +#ifdef CONFIG_STM32_TIM8_PWM +# if !defined(CONFIG_STM32_TIM8_CHANNEL) +# error "CONFIG_STM32_TIM8_CHANNEL must be provided" +# elif CONFIG_STM32_TIM8_CHANNEL == 1 +# define CONFIG_STM32_TIM8_CHANNEL1 1 +# define CONFIG_STM32_TIM8_CH1MODE CONFIG_STM32_TIM8_CHMODE +# elif CONFIG_STM32_TIM8_CHANNEL == 2 +# define CONFIG_STM32_TIM8_CHANNEL2 1 +# define CONFIG_STM32_TIM8_CH2MODE CONFIG_STM32_TIM8_CHMODE +# elif CONFIG_STM32_TIM8_CHANNEL == 3 +# define CONFIG_STM32_TIM8_CHANNEL3 1 +# define CONFIG_STM32_TIM8_CH3MODE CONFIG_STM32_TIM8_CHMODE +# elif CONFIG_STM32_TIM8_CHANNEL == 4 +# define CONFIG_STM32_TIM8_CHANNEL4 1 +# define CONFIG_STM32_TIM8_CH4MODE CONFIG_STM32_TIM8_CHMODE # else -# error "Unsupported value of CONFIG_STM32F7_TIM8_CHANNEL" +# error "Unsupported value of CONFIG_STM32_TIM8_CHANNEL" # endif # define PWM_TIM8_NCHANNELS 1 #endif -#ifdef CONFIG_STM32F7_TIM9_PWM -# if !defined(CONFIG_STM32F7_TIM9_CHANNEL) -# error "CONFIG_STM32F7_TIM9_CHANNEL must be provided" -# elif CONFIG_STM32F7_TIM9_CHANNEL == 1 -# define CONFIG_STM32F7_TIM9_CHANNEL1 1 -# define CONFIG_STM32F7_TIM9_CH1MODE CONFIG_STM32F7_TIM9_CHMODE -# elif CONFIG_STM32F7_TIM9_CHANNEL == 2 -# define CONFIG_STM32F7_TIM9_CHANNEL2 1 -# define CONFIG_STM32F7_TIM9_CH2MODE CONFIG_STM32F7_TIM9_CHMODE +#ifdef CONFIG_STM32_TIM9_PWM +# if !defined(CONFIG_STM32_TIM9_CHANNEL) +# error "CONFIG_STM32_TIM9_CHANNEL must be provided" +# elif CONFIG_STM32_TIM9_CHANNEL == 1 +# define CONFIG_STM32_TIM9_CHANNEL1 1 +# define CONFIG_STM32_TIM9_CH1MODE CONFIG_STM32_TIM9_CHMODE +# elif CONFIG_STM32_TIM9_CHANNEL == 2 +# define CONFIG_STM32_TIM9_CHANNEL2 1 +# define CONFIG_STM32_TIM9_CH2MODE CONFIG_STM32_TIM9_CHMODE # else -# error "Unsupported value of CONFIG_STM32F7_TIM9_CHANNEL" +# error "Unsupported value of CONFIG_STM32_TIM9_CHANNEL" # endif # define PWM_TIM9_NCHANNELS 1 #endif -#ifdef CONFIG_STM32F7_TIM10_PWM -# if !defined(CONFIG_STM32F7_TIM10_CHANNEL) -# error "CONFIG_STM32F7_TIM10_CHANNEL must be provided" -# elif CONFIG_STM32F7_TIM10_CHANNEL == 1 -# define CONFIG_STM32F7_TIM10_CHANNEL1 1 -# define CONFIG_STM32F7_TIM10_CH1MODE CONFIG_STM32F7_TIM10_CHMODE +#ifdef CONFIG_STM32_TIM10_PWM +# if !defined(CONFIG_STM32_TIM10_CHANNEL) +# error "CONFIG_STM32_TIM10_CHANNEL must be provided" +# elif CONFIG_STM32_TIM10_CHANNEL == 1 +# define CONFIG_STM32_TIM10_CHANNEL1 1 +# define CONFIG_STM32_TIM10_CH1MODE CONFIG_STM32_TIM10_CHMODE # else -# error "Unsupported value of CONFIG_STM32F7_TIM10_CHANNEL" +# error "Unsupported value of CONFIG_STM32_TIM10_CHANNEL" # endif # define PWM_TIM10_NCHANNELS 1 #endif -#ifdef CONFIG_STM32F7_TIM11_PWM -# if !defined(CONFIG_STM32F7_TIM11_CHANNEL) -# error "CONFIG_STM32F7_TIM11_CHANNEL must be provided" -# elif CONFIG_STM32F7_TIM11_CHANNEL == 1 -# define CONFIG_STM32F7_TIM11_CHANNEL1 1 -# define CONFIG_STM32F7_TIM11_CH1MODE CONFIG_STM32F7_TIM11_CHMODE +#ifdef CONFIG_STM32_TIM11_PWM +# if !defined(CONFIG_STM32_TIM11_CHANNEL) +# error "CONFIG_STM32_TIM11_CHANNEL must be provided" +# elif CONFIG_STM32_TIM11_CHANNEL == 1 +# define CONFIG_STM32_TIM11_CHANNEL1 1 +# define CONFIG_STM32_TIM11_CH1MODE CONFIG_STM32_TIM11_CHMODE # else -# error "Unsupported value of CONFIG_STM32F7_TIM11_CHANNEL" +# error "Unsupported value of CONFIG_STM32_TIM11_CHANNEL" # endif # define PWM_TIM11_NCHANNELS 1 #endif -#ifdef CONFIG_STM32F7_TIM12_PWM -# if !defined(CONFIG_STM32F7_TIM12_CHANNEL) -# error "CONFIG_STM32F7_TIM12_CHANNEL must be provided" -# elif CONFIG_STM32F7_TIM12_CHANNEL == 1 -# define CONFIG_STM32F7_TIM12_CHANNEL1 1 -# define CONFIG_STM32F7_TIM12_CH1MODE CONFIG_STM32F7_TIM12_CHMODE -# elif CONFIG_STM32F7_TIM12_CHANNEL == 2 -# define CONFIG_STM32F7_TIM12_CHANNEL2 1 -# define CONFIG_STM32F7_TIM12_CH2MODE CONFIG_STM32F7_TIM12_CHMODE +#ifdef CONFIG_STM32_TIM12_PWM +# if !defined(CONFIG_STM32_TIM12_CHANNEL) +# error "CONFIG_STM32_TIM12_CHANNEL must be provided" +# elif CONFIG_STM32_TIM12_CHANNEL == 1 +# define CONFIG_STM32_TIM12_CHANNEL1 1 +# define CONFIG_STM32_TIM12_CH1MODE CONFIG_STM32_TIM12_CHMODE +# elif CONFIG_STM32_TIM12_CHANNEL == 2 +# define CONFIG_STM32_TIM12_CHANNEL2 1 +# define CONFIG_STM32_TIM12_CH2MODE CONFIG_STM32_TIM12_CHMODE # else -# error "Unsupported value of CONFIG_STM32F7_TIM12_CHANNEL" +# error "Unsupported value of CONFIG_STM32_TIM12_CHANNEL" # endif # define PWM_TIM12_NCHANNELS 1 #endif -#ifdef CONFIG_STM32F7_TIM13_PWM -# if !defined(CONFIG_STM32F7_TIM13_CHANNEL) -# error "CONFIG_STM32F7_TIM13_CHANNEL must be provided" -# elif CONFIG_STM32F7_TIM13_CHANNEL == 1 -# define CONFIG_STM32F7_TIM13_CHANNEL1 1 -# define CONFIG_STM32F7_TIM13_CH1MODE CONFIG_STM32F7_TIM13_CHMODE +#ifdef CONFIG_STM32_TIM13_PWM +# if !defined(CONFIG_STM32_TIM13_CHANNEL) +# error "CONFIG_STM32_TIM13_CHANNEL must be provided" +# elif CONFIG_STM32_TIM13_CHANNEL == 1 +# define CONFIG_STM32_TIM13_CHANNEL1 1 +# define CONFIG_STM32_TIM13_CH1MODE CONFIG_STM32_TIM13_CHMODE # else -# error "Unsupported value of CONFIG_STM32F7_TIM13_CHANNEL" +# error "Unsupported value of CONFIG_STM32_TIM13_CHANNEL" # endif # define PWM_TIM13_NCHANNELS 1 #endif -#ifdef CONFIG_STM32F7_TIM14_PWM -# if !defined(CONFIG_STM32F7_TIM14_CHANNEL) -# error "CONFIG_STM32F7_TIM14_CHANNEL must be provided" -# elif CONFIG_STM32F7_TIM14_CHANNEL == 1 -# define CONFIG_STM32F7_TIM14_CHANNEL1 1 -# define CONFIG_STM32F7_TIM14_CH1MODE CONFIG_STM32F7_TIM14_CHMODE +#ifdef CONFIG_STM32_TIM14_PWM +# if !defined(CONFIG_STM32_TIM14_CHANNEL) +# error "CONFIG_STM32_TIM14_CHANNEL must be provided" +# elif CONFIG_STM32_TIM14_CHANNEL == 1 +# define CONFIG_STM32_TIM14_CHANNEL1 1 +# define CONFIG_STM32_TIM14_CH1MODE CONFIG_STM32_TIM14_CHMODE # else -# error "Unsupported value of CONFIG_STM32F7_TIM14_CHANNEL" +# error "Unsupported value of CONFIG_STM32_TIM14_CHANNEL" # endif # define PWM_TIM14_NCHANNELS 1 #endif -#endif /* CONFIG_STM32F7_PWM_MULTICHAN */ +#endif /* CONFIG_STM32_PWM_MULTICHAN */ -#ifdef CONFIG_STM32F7_TIM1_CH1OUT +#ifdef CONFIG_STM32_TIM1_CH1OUT # define PWM_TIM1_CH1CFG GPIO_TIM1_CH1OUT #else # define PWM_TIM1_CH1CFG 0 #endif -#ifdef CONFIG_STM32F7_TIM1_CH1NOUT +#ifdef CONFIG_STM32_TIM1_CH1NOUT # define PWM_TIM1_CH1NCFG GPIO_TIM1_CH1NOUT #else # define PWM_TIM1_CH1NCFG 0 #endif -#ifdef CONFIG_STM32F7_TIM1_CH2OUT +#ifdef CONFIG_STM32_TIM1_CH2OUT # define PWM_TIM1_CH2CFG GPIO_TIM1_CH2OUT #else # define PWM_TIM1_CH2CFG 0 #endif -#ifdef CONFIG_STM32F7_TIM1_CH2NOUT +#ifdef CONFIG_STM32_TIM1_CH2NOUT # define PWM_TIM1_CH2NCFG GPIO_TIM1_CH2NOUT #else # define PWM_TIM1_CH2NCFG 0 #endif -#ifdef CONFIG_STM32F7_TIM1_CH3OUT +#ifdef CONFIG_STM32_TIM1_CH3OUT # define PWM_TIM1_CH3CFG GPIO_TIM1_CH3OUT #else # define PWM_TIM1_CH3CFG 0 #endif -#ifdef CONFIG_STM32F7_TIM1_CH3NOUT +#ifdef CONFIG_STM32_TIM1_CH3NOUT # define PWM_TIM1_CH3NCFG GPIO_TIM1_CH3NOUT #else # define PWM_TIM1_CH3NCFG 0 #endif -#ifdef CONFIG_STM32F7_TIM1_CH4OUT +#ifdef CONFIG_STM32_TIM1_CH4OUT # define PWM_TIM1_CH4CFG GPIO_TIM1_CH4OUT #else # define PWM_TIM1_CH4CFG 0 #endif -#ifdef CONFIG_STM32F7_TIM2_CH1OUT +#ifdef CONFIG_STM32_TIM2_CH1OUT # define PWM_TIM2_CH1CFG GPIO_TIM2_CH1OUT #else # define PWM_TIM2_CH1CFG 0 #endif -#ifdef CONFIG_STM32F7_TIM2_CH2OUT +#ifdef CONFIG_STM32_TIM2_CH2OUT # define PWM_TIM2_CH2CFG GPIO_TIM2_CH2OUT #else # define PWM_TIM2_CH2CFG 0 #endif -#ifdef CONFIG_STM32F7_TIM2_CH3OUT +#ifdef CONFIG_STM32_TIM2_CH3OUT # define PWM_TIM2_CH3CFG GPIO_TIM2_CH3OUT #else # define PWM_TIM2_CH3CFG 0 #endif -#ifdef CONFIG_STM32F7_TIM2_CH4OUT +#ifdef CONFIG_STM32_TIM2_CH4OUT # define PWM_TIM2_CH4CFG GPIO_TIM2_CH4OUT #else # define PWM_TIM2_CH4CFG 0 #endif -#ifdef CONFIG_STM32F7_TIM3_CH1OUT +#ifdef CONFIG_STM32_TIM3_CH1OUT # define PWM_TIM3_CH1CFG GPIO_TIM3_CH1OUT #else # define PWM_TIM3_CH1CFG 0 #endif -#ifdef CONFIG_STM32F7_TIM3_CH2OUT +#ifdef CONFIG_STM32_TIM3_CH2OUT # define PWM_TIM3_CH2CFG GPIO_TIM3_CH2OUT #else # define PWM_TIM3_CH2CFG 0 #endif -#ifdef CONFIG_STM32F7_TIM3_CH3OUT +#ifdef CONFIG_STM32_TIM3_CH3OUT # define PWM_TIM3_CH3CFG GPIO_TIM3_CH3OUT #else # define PWM_TIM3_CH3CFG 0 #endif -#ifdef CONFIG_STM32F7_TIM3_CH4OUT +#ifdef CONFIG_STM32_TIM3_CH4OUT # define PWM_TIM3_CH4CFG GPIO_TIM3_CH4OUT #else # define PWM_TIM3_CH4CFG 0 #endif -#ifdef CONFIG_STM32F7_TIM4_CH1OUT +#ifdef CONFIG_STM32_TIM4_CH1OUT # define PWM_TIM4_CH1CFG GPIO_TIM4_CH1OUT #else # define PWM_TIM4_CH1CFG 0 #endif -#ifdef CONFIG_STM32F7_TIM4_CH2OUT +#ifdef CONFIG_STM32_TIM4_CH2OUT # define PWM_TIM4_CH2CFG GPIO_TIM4_CH2OUT #else # define PWM_TIM4_CH2CFG 0 #endif -#ifdef CONFIG_STM32F7_TIM4_CH3OUT +#ifdef CONFIG_STM32_TIM4_CH3OUT # define PWM_TIM4_CH3CFG GPIO_TIM4_CH3OUT #else # define PWM_TIM4_CH3CFG 0 #endif -#ifdef CONFIG_STM32F7_TIM4_CH4OUT +#ifdef CONFIG_STM32_TIM4_CH4OUT # define PWM_TIM4_CH4CFG GPIO_TIM4_CH4OUT #else # define PWM_TIM4_CH4CFG 0 #endif -#ifdef CONFIG_STM32F7_TIM5_CH1OUT +#ifdef CONFIG_STM32_TIM5_CH1OUT # define PWM_TIM5_CH1CFG GPIO_TIM5_CH1OUT #else # define PWM_TIM5_CH1CFG 0 #endif -#ifdef CONFIG_STM32F7_TIM5_CH2OUT +#ifdef CONFIG_STM32_TIM5_CH2OUT # define PWM_TIM5_CH2CFG GPIO_TIM5_CH2OUT #else # define PWM_TIM5_CH2CFG 0 #endif -#ifdef CONFIG_STM32F7_TIM5_CH3OUT +#ifdef CONFIG_STM32_TIM5_CH3OUT # define PWM_TIM5_CH3CFG GPIO_TIM5_CH3OUT #else # define PWM_TIM5_CH3CFG 0 #endif -#ifdef CONFIG_STM32F7_TIM5_CH4OUT +#ifdef CONFIG_STM32_TIM5_CH4OUT # define PWM_TIM5_CH4CFG GPIO_TIM5_CH4OUT #else # define PWM_TIM5_CH4CFG 0 #endif -#ifdef CONFIG_STM32F7_TIM8_CH1OUT +#ifdef CONFIG_STM32_TIM8_CH1OUT # define PWM_TIM8_CH1CFG GPIO_TIM8_CH1OUT #else # define PWM_TIM8_CH1CFG 0 #endif -#ifdef CONFIG_STM32F7_TIM8_CH1NOUT +#ifdef CONFIG_STM32_TIM8_CH1NOUT # define PWM_TIM8_CH1NCFG GPIO_TIM8_CH1NOUT #else # define PWM_TIM8_CH1NCFG 0 #endif -#ifdef CONFIG_STM32F7_TIM8_CH2OUT +#ifdef CONFIG_STM32_TIM8_CH2OUT # define PWM_TIM8_CH2CFG GPIO_TIM8_CH2OUT #else # define PWM_TIM8_CH2CFG 0 #endif -#ifdef CONFIG_STM32F7_TIM8_CH2NOUT +#ifdef CONFIG_STM32_TIM8_CH2NOUT # define PWM_TIM8_CH2NCFG GPIO_TIM8_CH2NOUT #else # define PWM_TIM8_CH2NCFG 0 #endif -#ifdef CONFIG_STM32F7_TIM8_CH3OUT +#ifdef CONFIG_STM32_TIM8_CH3OUT # define PWM_TIM8_CH3CFG GPIO_TIM8_CH3OUT #else # define PWM_TIM8_CH3CFG 0 #endif -#ifdef CONFIG_STM32F7_TIM8_CH3NOUT +#ifdef CONFIG_STM32_TIM8_CH3NOUT # define PWM_TIM8_CH3NCFG GPIO_TIM8_CH3NOUT #else # define PWM_TIM8_CH3NCFG 0 #endif -#ifdef CONFIG_STM32F7_TIM8_CH4OUT +#ifdef CONFIG_STM32_TIM8_CH4OUT # define PWM_TIM8_CH4CFG GPIO_TIM8_CH4OUT #else # define PWM_TIM8_CH4CFG 0 #endif -#ifdef CONFIG_STM32F7_TIM9_CH1OUT +#ifdef CONFIG_STM32_TIM9_CH1OUT # define PWM_TIM9_CH1CFG GPIO_TIM9_CH1OUT #else # define PWM_TIM9_CH1CFG 0 #endif -#ifdef CONFIG_STM32F7_TIM9_CH2OUT +#ifdef CONFIG_STM32_TIM9_CH2OUT # define PWM_TIM9_CH2CFG GPIO_TIM9_CH2OUT #else # define PWM_TIM9_CH2CFG 0 #endif -#ifdef CONFIG_STM32F7_TIM10_CH1OUT +#ifdef CONFIG_STM32_TIM10_CH1OUT # define PWM_TIM10_CH1CFG GPIO_TIM10_CH1OUT #else # define PWM_TIM10_CH1CFG 0 #endif -#ifdef CONFIG_STM32F7_TIM11_CH1OUT +#ifdef CONFIG_STM32_TIM11_CH1OUT # define PWM_TIM11_CH1CFG GPIO_TIM11_CH1OUT #else # define PWM_TIM11_CH1CFG 0 #endif -#ifdef CONFIG_STM32F7_TIM12_CH1OUT +#ifdef CONFIG_STM32_TIM12_CH1OUT # define PWM_TIM12_CH1CFG GPIO_TIM12_CH1OUT #else # define PWM_TIM12_CH1CFG 0 #endif -#ifdef CONFIG_STM32F7_TIM12_CH2OUT +#ifdef CONFIG_STM32_TIM12_CH2OUT # define PWM_TIM12_CH2CFG GPIO_TIM12_CH2OUT #else # define PWM_TIM12_CH2CFG 0 #endif -#ifdef CONFIG_STM32F7_TIM13_CH1OUT +#ifdef CONFIG_STM32_TIM13_CH1OUT # define PWM_TIM13_CH1CFG GPIO_TIM13_CH1OUT #else # define PWM_TIM13_CH1CFG 0 #endif -#ifdef CONFIG_STM32F7_TIM14_CH1OUT +#ifdef CONFIG_STM32_TIM14_CH1OUT # define PWM_TIM14_CH1CFG GPIO_TIM14_CH1OUT #else # define PWM_TIM14_CH1CFG 0 @@ -747,12 +747,12 @@ /* Complementary outputs support */ -#if defined(CONFIG_STM32F7_TIM1_CH1NOUT) || defined(CONFIG_STM32F7_TIM1_CH2NOUT) || \ - defined(CONFIG_STM32F7_TIM1_CH3NOUT) +#if defined(CONFIG_STM32_TIM1_CH1NOUT) || defined(CONFIG_STM32_TIM1_CH2NOUT) || \ + defined(CONFIG_STM32_TIM1_CH3NOUT) # define HAVE_TIM1_COMPLEMENTARY #endif -#if defined(CONFIG_STM32F7_TIM8_CH1NOUT) || defined(CONFIG_STM32F7_TIM8_CH2NOUT) || \ - defined(CONFIG_STM32F7_TIM8_CH3NOUT) +#if defined(CONFIG_STM32_TIM8_CH1NOUT) || defined(CONFIG_STM32_TIM8_CH2NOUT) || \ + defined(CONFIG_STM32_TIM8_CH3NOUT) # define HAVE_TIM8_COMPLEMENTARY #endif #if defined(HAVE_TIM1_COMPLEMENTARY) || defined(HAVE_TIM8_COMPLEMENTARY) @@ -761,7 +761,7 @@ /* Low-level ops helpers ****************************************************/ -#ifdef CONFIG_STM32F7_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS /* NOTE: * low-level ops accept pwm_lowerhalf_s as first argument, but llops access @@ -786,7 +786,7 @@ (dev)->llops->rcr_update((struct pwm_lowerhalf_s *)dev, rcr) #define PWM_RCR_GET(dev) \ (dev)->llops->rcr_get((struct pwm_lowerhalf_s *)dev) -#ifdef CONFIG_STM32F7_PWM_TRGO +#ifdef CONFIG_STM32_PWM_TRGO # define PWM_TRGO_SET(dev, trgo) \ (dev)->llops->trgo_set((struct pwm_lowerhalf_s *)dev, trgo) #endif @@ -898,7 +898,7 @@ enum stm32_pwm_output_e /* 1 << 11 reserved - no complementary output for CH6 */ }; -#ifdef CONFIG_STM32F7_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS /* This structure provides the publicly visible representation of the * "lower-half" PWM driver structure. @@ -954,7 +954,7 @@ struct stm32_pwm_ops_s uint16_t (*rcr_get)(struct pwm_lowerhalf_s *dev); -#ifdef CONFIG_STM32F7_PWM_TRGO +#ifdef CONFIG_STM32_PWM_TRGO /* Set TRGO/TRGO2 register */ int (*trgo_set)(struct pwm_lowerhalf_s *dev, uint8_t trgo); @@ -998,7 +998,7 @@ struct stm32_pwm_ops_s #endif }; -#endif /* CONFIG_STM32F7_PWM_LL_OPS */ +#endif /* CONFIG_STM32_PWM_LL_OPS */ /**************************************************************************** * Public Data @@ -1044,5 +1044,5 @@ struct pwm_lowerhalf_s *stm32_pwminitialize(int timer); #endif #endif /* __ASSEMBLY__ */ -#endif /* CONFIG_STM32F7_PWM */ +#endif /* CONFIG_STM32_PWM */ #endif /* __ARCH_ARM_SRC_STM32F7_STM32_PWM_H */ diff --git a/arch/arm/src/stm32f7/stm32_pwr.c b/arch/arm/src/stm32f7/stm32_pwr.c index c86b70a247493..5fac63ef0257d 100644 --- a/arch/arm/src/stm32f7/stm32_pwr.c +++ b/arch/arm/src/stm32f7/stm32_pwr.c @@ -35,7 +35,7 @@ #include "arm_internal.h" #include "stm32_pwr.h" -#if defined(CONFIG_STM32F7_PWR) +#if defined(CONFIG_STM32_PWR) /**************************************************************************** * Private Data diff --git a/arch/arm/src/stm32f7/stm32_qencoder.c b/arch/arm/src/stm32f7/stm32_qencoder.c index e3afc99eb670c..fdf06b3bb0d4a 100644 --- a/arch/arm/src/stm32f7/stm32_qencoder.c +++ b/arch/arm/src/stm32f7/stm32_qencoder.c @@ -60,14 +60,14 @@ /* If TIM2 or TIM5 are enabled, then we have 32-bit timers */ -#if defined(CONFIG_STM32F7_TIM2_QE) || defined(CONFIG_STM32F7_TIM5_QE) +#if defined(CONFIG_STM32_TIM2_QE) || defined(CONFIG_STM32_TIM5_QE) # define HAVE_32BIT_TIMERS 1 #endif /* If TIM1,3,4, or 8 are enabled, then we have 16-bit timers */ -#if defined(CONFIG_STM32F7_TIM1_QE) || defined(CONFIG_STM32F7_TIM3_QE) || \ - defined(CONFIG_STM32F7_TIM4_QE) || defined(CONFIG_STM32F7_TIM8_QE) +#if defined(CONFIG_STM32_TIM1_QE) || defined(CONFIG_STM32_TIM3_QE) || \ + defined(CONFIG_STM32_TIM4_QE) || defined(CONFIG_STM32_TIM8_QE) # define HAVE_16BIT_TIMERS 1 #endif @@ -89,51 +89,51 @@ /* Input filter *************************************************************/ -#ifdef CONFIG_STM32F7_QENCODER_FILTER -# if defined(CONFIG_STM32F7_QENCODER_SAMPLE_FDTS) -# if defined(CONFIG_STM32F7_QENCODER_SAMPLE_EVENT_1) +#ifdef CONFIG_STM32_QENCODER_FILTER +# if defined(CONFIG_STM32_QENCODER_SAMPLE_FDTS) +# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_1) # define STM32_QENCODER_ICF GTIM_CCMR_ICF_NOFILT # endif -# elif defined(CONFIG_STM32F7_QENCODER_SAMPLE_CKINT) -# if defined(CONFIG_STM32F7_QENCODER_SAMPLE_EVENT_2) +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_CKINT) +# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_2) # define STM32_QENCODER_ICF GTIM_CCMR_ICF_FCKINT2 -# elif defined(CONFIG_STM32F7_QENCODER_SAMPLE_EVENT_4) +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_4) # define STM32_QENCODER_ICF GTIM_CCMR_ICF_FCKINT4 -# elif defined(CONFIG_STM32F7_QENCODER_SAMPLE_EVENT_8) +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_8) # define STM32_QENCODER_ICF GTIM_CCMR_ICF_FCKINT8 # endif -# elif defined(CONFIG_STM32F7_QENCODER_SAMPLE_FDTS_2) -# if defined(CONFIG_STM32F7_QENCODER_SAMPLE_EVENT_6) +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_FDTS_2) +# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_6) # define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd26 -# elif defined(CONFIG_STM32F7_QENCODER_SAMPLE_EVENT_8) +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_8) # define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd28 # endif -# elif defined(CONFIG_STM32F7_QENCODER_SAMPLE_FDTS_4) -# if defined(CONFIG_STM32F7_QENCODER_SAMPLE_EVENT_6) +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_FDTS_4) +# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_6) # define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd46 -# elif defined(CONFIG_STM32F7_QENCODER_SAMPLE_EVENT_8) +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_8) # define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd48 # endif -# elif defined(CONFIG_STM32F7_QENCODER_SAMPLE_FDTS_8) -# if defined(CONFIG_STM32F7_QENCODER_SAMPLE_EVENT_6) +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_FDTS_8) +# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_6) # define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd86 -# elif defined(CONFIG_STM32F7_QENCODER_SAMPLE_EVENT_8) +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_8) # define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd88 # endif -# elif defined(CONFIG_STM32F7_QENCODER_SAMPLE_FDTS_16) -# if defined(CONFIG_STM32F7_QENCODER_SAMPLE_EVENT_5) +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_FDTS_16) +# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_5) # define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd165 -# elif defined(CONFIG_STM32F7_QENCODER_SAMPLE_EVENT_6) +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_6) # define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd166 -# elif defined(CONFIG_STM32F7_QENCODER_SAMPLE_EVENT_8) +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_8) # define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd168 # endif -# elif defined(CONFIG_STM32F7_QENCODER_SAMPLE_FDTS_32) -# if defined(CONFIG_STM32F7_QENCODER_SAMPLE_EVENT_5) +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_FDTS_32) +# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_5) # define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd325 -# elif defined(CONFIG_STM32F7_QENCODER_SAMPLE_EVENT_6) +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_6) # define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd326 -# elif defined(CONFIG_STM32F7_QENCODER_SAMPLE_EVENT_8) +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_8) # define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd328 # endif # endif @@ -276,7 +276,7 @@ static const struct qe_ops_s g_qecallbacks = /* Per-timer state structures */ -#ifdef CONFIG_STM32F7_TIM1_QE +#ifdef CONFIG_STM32_TIM1_QE static const struct stm32_qeconfig_s g_tim1config = { .timid = 1, @@ -287,7 +287,7 @@ static const struct stm32_qeconfig_s g_tim1config = .regaddr = STM32_RCC_APB2ENR, .enable = RCC_APB2ENR_TIM1EN, .base = STM32_TIM1_BASE, - .psc = CONFIG_STM32F7_TIM1_QEPSC, + .psc = CONFIG_STM32_TIM1_QEPSC, .ti1cfg = GPIO_TIM1_CH1IN, .ti2cfg = GPIO_TIM1_CH2IN, }; @@ -302,7 +302,7 @@ static struct stm32_lowerhalf_s g_tim1lower = #endif -#ifdef CONFIG_STM32F7_TIM2_QE +#ifdef CONFIG_STM32_TIM2_QE static const struct stm32_qeconfig_s g_tim2config = { .timid = 2, @@ -313,7 +313,7 @@ static const struct stm32_qeconfig_s g_tim2config = .regaddr = STM32_RCC_APB1ENR, .enable = RCC_APB1ENR_TIM2EN, .base = STM32_TIM2_BASE, - .psc = CONFIG_STM32F7_TIM2_QEPSC, + .psc = CONFIG_STM32_TIM2_QEPSC, .ti1cfg = GPIO_TIM2_CH1IN, .ti2cfg = GPIO_TIM2_CH2IN, }; @@ -328,7 +328,7 @@ static struct stm32_lowerhalf_s g_tim2lower = #endif -#ifdef CONFIG_STM32F7_TIM3_QE +#ifdef CONFIG_STM32_TIM3_QE static const struct stm32_qeconfig_s g_tim3config = { .timid = 3, @@ -339,7 +339,7 @@ static const struct stm32_qeconfig_s g_tim3config = .regaddr = STM32_RCC_APB1ENR, .enable = RCC_APB1ENR_TIM3EN, .base = STM32_TIM3_BASE, - .psc = CONFIG_STM32F7_TIM3_QEPSC, + .psc = CONFIG_STM32_TIM3_QEPSC, .ti1cfg = GPIO_TIM3_CH1IN, .ti2cfg = GPIO_TIM3_CH2IN, }; @@ -354,7 +354,7 @@ static struct stm32_lowerhalf_s g_tim3lower = #endif -#ifdef CONFIG_STM32F7_TIM4_QE +#ifdef CONFIG_STM32_TIM4_QE static const struct stm32_qeconfig_s g_tim4config = { .timid = 4, @@ -365,7 +365,7 @@ static const struct stm32_qeconfig_s g_tim4config = .regaddr = STM32_RCC_APB1ENR, .enable = RCC_APB1ENR_TIM4EN, .base = STM32_TIM4_BASE, - .psc = CONFIG_STM32F7_TIM4_QEPSC, + .psc = CONFIG_STM32_TIM4_QEPSC, .ti1cfg = GPIO_TIM4_CH1IN, .ti2cfg = GPIO_TIM4_CH2IN, }; @@ -380,7 +380,7 @@ static struct stm32_lowerhalf_s g_tim4lower = #endif -#ifdef CONFIG_STM32F7_TIM5_QE +#ifdef CONFIG_STM32_TIM5_QE static const struct stm32_qeconfig_s g_tim5config = { .timid = 5, @@ -391,7 +391,7 @@ static const struct stm32_qeconfig_s g_tim5config = .regaddr = STM32_RCC_APB1ENR, .enable = RCC_APB1ENR_TIM5EN, .base = STM32_TIM5_BASE, - .psc = CONFIG_STM32F7_TIM5_QEPSC, + .psc = CONFIG_STM32_TIM5_QEPSC, .ti1cfg = GPIO_TIM5_CH1IN, .ti2cfg = GPIO_TIM5_CH2IN, }; @@ -406,7 +406,7 @@ static struct stm32_lowerhalf_s g_tim5lower = #endif -#ifdef CONFIG_STM32F7_TIM8_QE +#ifdef CONFIG_STM32_TIM8_QE static const struct stm32_qeconfig_s g_tim8config = { .timid = 8, @@ -417,7 +417,7 @@ static const struct stm32_qeconfig_s g_tim8config = .regaddr = STM32_RCC_APB2ENR, .enable = RCC_APB2ENR_TIM8EN, .base = STM32_TIM8_BASE, - .psc = CONFIG_STM32F7_TIM8_QEPSC, + .psc = CONFIG_STM32_TIM8_QEPSC, .ti1cfg = GPIO_TIM8_CH1IN, .ti2cfg = GPIO_TIM8_CH2IN, }; @@ -562,7 +562,7 @@ static void stm32_dumpregs(struct stm32_lowerhalf_s *priv, stm32_getreg16(priv, STM32_GTIM_CCR2_OFFSET), stm32_getreg16(priv, STM32_GTIM_CCR3_OFFSET), stm32_getreg16(priv, STM32_GTIM_CCR4_OFFSET)); -#if defined(CONFIG_STM32F7_TIM1_QE) || defined(CONFIG_STM32F7_TIM8_QE) +#if defined(CONFIG_STM32_TIM1_QE) || defined(CONFIG_STM32_TIM8_QE) if (priv->config->timid == 1 || priv->config->timid == 8) { sninfo(" RCR: %04x BDTR: %04x DCR: %04x DMAR: %04x\n", @@ -593,27 +593,27 @@ static struct stm32_lowerhalf_s *stm32_tim2lower(int tim) { switch (tim) { -#ifdef CONFIG_STM32F7_TIM1_QE +#ifdef CONFIG_STM32_TIM1_QE case 1: return &g_tim1lower; #endif -#ifdef CONFIG_STM32F7_TIM2_QE +#ifdef CONFIG_STM32_TIM2_QE case 2: return &g_tim2lower; #endif -#ifdef CONFIG_STM32F7_TIM3_QE +#ifdef CONFIG_STM32_TIM3_QE case 3: return &g_tim3lower; #endif -#ifdef CONFIG_STM32F7_TIM4_QE +#ifdef CONFIG_STM32_TIM4_QE case 4: return &g_tim4lower; #endif -#ifdef CONFIG_STM32F7_TIM5_QE +#ifdef CONFIG_STM32_TIM5_QE case 5: return &g_tim5lower; #endif -#ifdef CONFIG_STM32F7_TIM8_QE +#ifdef CONFIG_STM32_TIM8_QE case 8: return &g_tim8lower; #endif @@ -733,7 +733,7 @@ static int stm32_setup(struct qe_lowerhalf_s *lower) stm32_putreg16(priv, STM32_GTIM_PSC_OFFSET, (uint16_t)priv->config->psc); -#if defined(CONFIG_STM32F7_TIM1_QE) || defined(CONFIG_STM32F7_TIM8_QE) +#if defined(CONFIG_STM32_TIM1_QE) || defined(CONFIG_STM32_TIM8_QE) if (priv->config->timid == 1 || priv->config->timid == 8) { /* Clear the Repetition Counter value */ @@ -943,37 +943,37 @@ static int stm32_shutdown(struct qe_lowerhalf_s *lower) switch (priv->config->timid) { -#ifdef CONFIG_STM32F7_TIM1_QE +#ifdef CONFIG_STM32_TIM1_QE case 1: regaddr = STM32_RCC_APB2RSTR; resetbit = RCC_APB2RSTR_TIM1RST; break; #endif -#ifdef CONFIG_STM32F7_TIM2_QE +#ifdef CONFIG_STM32_TIM2_QE case 2: regaddr = STM32_RCC_APB1RSTR; resetbit = RCC_APB1RSTR_TIM2RST; break; #endif -#ifdef CONFIG_STM32F7_TIM3_QE +#ifdef CONFIG_STM32_TIM3_QE case 3: regaddr = STM32_RCC_APB1RSTR; resetbit = RCC_APB1RSTR_TIM3RST; break; #endif -#ifdef CONFIG_STM32F7_TIM4_QE +#ifdef CONFIG_STM32_TIM4_QE case 4: regaddr = STM32_RCC_APB1RSTR; resetbit = RCC_APB1RSTR_TIM4RST; break; #endif -#ifdef CONFIG_STM32F7_TIM5_QE +#ifdef CONFIG_STM32_TIM5_QE case 5: regaddr = STM32_RCC_APB1RSTR; resetbit = RCC_APB1RSTR_TIM5RST; break; #endif -#ifdef CONFIG_STM32F7_TIM8_QE +#ifdef CONFIG_STM32_TIM8_QE case 8: regaddr = STM32_RCC_APB2RSTR; resetbit = RCC_APB2RSTR_TIM8RST; diff --git a/arch/arm/src/stm32f7/stm32_qencoder.h b/arch/arm/src/stm32f7/stm32_qencoder.h index 3531846389ca6..cb0399814da57 100644 --- a/arch/arm/src/stm32f7/stm32_qencoder.h +++ b/arch/arm/src/stm32f7/stm32_qencoder.h @@ -38,42 +38,42 @@ ****************************************************************************/ /* Timer devices may be used for different purposes. One special purpose is - * as a quadrature encoder input device. If CONFIG_STM32F7_TIMn is defined - * then the CONFIG_STM32F7_TIMn_QE must also be defined to indicate that + * as a quadrature encoder input device. If CONFIG_STM32_TIMn is defined + * then the CONFIG_STM32_TIMn_QE must also be defined to indicate that * timer "n" is intended to be used for as a quadrature encoder. */ -#ifndef CONFIG_STM32F7_TIM1 -# undef CONFIG_STM32F7_TIM1_QE +#ifndef CONFIG_STM32_TIM1 +# undef CONFIG_STM32_TIM1_QE #endif -#ifndef CONFIG_STM32F7_TIM2 -# undef CONFIG_STM32F7_TIM2_QE +#ifndef CONFIG_STM32_TIM2 +# undef CONFIG_STM32_TIM2_QE #endif -#ifndef CONFIG_STM32F7_TIM3 -# undef CONFIG_STM32F7_TIM3_QE +#ifndef CONFIG_STM32_TIM3 +# undef CONFIG_STM32_TIM3_QE #endif -#ifndef CONFIG_STM32F7_TIM4 -# undef CONFIG_STM32F7_TIM4_QE +#ifndef CONFIG_STM32_TIM4 +# undef CONFIG_STM32_TIM4_QE #endif -#ifndef CONFIG_STM32F7_TIM5 -# undef CONFIG_STM32F7_TIM5_QE +#ifndef CONFIG_STM32_TIM5 +# undef CONFIG_STM32_TIM5_QE #endif -#ifndef CONFIG_STM32F7_TIM8 -# undef CONFIG_STM32F7_TIM8_QE +#ifndef CONFIG_STM32_TIM8 +# undef CONFIG_STM32_TIM8_QE #endif /* Only timers 2-5, and 1 & 8 can be used as a quadrature encoder * (at least for the STM32 F7) */ -#undef CONFIG_STM32F7_TIM6_QE -#undef CONFIG_STM32F7_TIM7_QE -#undef CONFIG_STM32F7_TIM9_QE -#undef CONFIG_STM32F7_TIM10_QE -#undef CONFIG_STM32F7_TIM11_QE -#undef CONFIG_STM32F7_TIM12_QE -#undef CONFIG_STM32F7_TIM13_QE -#undef CONFIG_STM32F7_TIM14_QE +#undef CONFIG_STM32_TIM6_QE +#undef CONFIG_STM32_TIM7_QE +#undef CONFIG_STM32_TIM9_QE +#undef CONFIG_STM32_TIM10_QE +#undef CONFIG_STM32_TIM11_QE +#undef CONFIG_STM32_TIM12_QE +#undef CONFIG_STM32_TIM13_QE +#undef CONFIG_STM32_TIM14_QE /**************************************************************************** * Included Files diff --git a/arch/arm/src/stm32f7/stm32_qspi.c b/arch/arm/src/stm32f7/stm32_qspi.c index a9e46655548cf..e43268126c707 100644 --- a/arch/arm/src/stm32f7/stm32_qspi.c +++ b/arch/arm/src/stm32f7/stm32_qspi.c @@ -56,7 +56,7 @@ #include "stm32_rcc.h" #include "hardware/stm32_qspi.h" -#ifdef CONFIG_STM32F7_QUADSPI +#ifdef CONFIG_STM32_QSPI /**************************************************************************** * Pre-processor Definitions @@ -67,7 +67,7 @@ /* Check if QSPI debug is enabled */ #ifndef CONFIG_DEBUG_DMA -# undef CONFIG_STM32F7_QSPI_DMADEBUG +# undef CONFIG_STM32_QSPI_DMADEBUG #endif #define DMA_INITIAL 0 @@ -80,7 +80,7 @@ /* Can't have both interrupt-driven QSPI and DMA QSPI */ -#if defined(CONFIG_STM32F7_QSPI_INTERRUPTS) && defined(CONFIG_STM32F7_QSPI_DMA) +#if defined(CONFIG_STM32_QSPI_INTERRUPTS) && defined(CONFIG_STM32_QSPI_DMA) # error "Cannot enable both interrupt mode and DMA mode for QSPI" #endif @@ -92,7 +92,7 @@ GPIO_QSPI_IO1 GPIO_QSPI_IO2 GPIO_QSPI_IO3 GPIO_QSPI_SCK in your board.h #endif -#ifdef CONFIG_STM32F7_QSPI_DMA +#ifdef CONFIG_STM32_QSPI_DMA # ifdef DMAMAP_QUADSPI @@ -104,26 +104,26 @@ # define DMACHAN_QUADSPI DMAMAP_QUADSPI # endif -# if defined(CONFIG_STM32F7_QSPI_DMAPRIORITY_LOW) +# if defined(CONFIG_STM32_QSPI_DMAPRIORITY_LOW) # define QSPI_DMA_PRIO DMA_SCR_PRILO -# elif defined(CONFIG_STM32F7_QSPI_DMAPRIORITY_MEDIUM) +# elif defined(CONFIG_STM32_QSPI_DMAPRIORITY_MEDIUM) # define QSPI_DMA_PRIO DMA_SCR_PRIMED -# elif defined(CONFIG_STM32F7_QSPI_DMAPRIORITY_HIGH) +# elif defined(CONFIG_STM32_QSPI_DMAPRIORITY_HIGH) # define QSPI_DMA_PRIO DMA_SCR_PRIHI -# elif defined(CONFIG_STM32F7_QSPI_DMAPRIORITY_VERYHIGH) +# elif defined(CONFIG_STM32_QSPI_DMAPRIORITY_VERYHIGH) # define QSPI_DMA_PRIO DMA_SCR_PRIVERYHI # else # define QSPI_DMA_PRIO DMA_SCR_PRIMED # endif -#endif /* CONFIG_STM32F7_QSPI_DMA */ +#endif /* CONFIG_STM32_QSPI_DMA */ #ifndef STM32_SYSCLK_FREQUENCY # error your board.h needs to define the value of STM32_SYSCLK_FREQUENCY #endif -#if !defined(CONFIG_STM32F7_QSPI_FLASH_SIZE) || 0 == CONFIG_STM32F7_QSPI_FLASH_SIZE -# error you must specify a positive flash size via CONFIG_STM32F7_QSPI_FLASH_SIZE +#if !defined(CONFIG_STM32_QSPI_FLASH_SIZE) || 0 == CONFIG_STM32_QSPI_FLASH_SIZE +# error you must specify a positive flash size via CONFIG_STM32_QSPI_FLASH_SIZE #endif /* DMA timeout. The value is not critical; we just don't want the system to @@ -164,14 +164,14 @@ struct stm32f7_qspidev_s mutex_t lock; /* Assures mutually exclusive access to QSPI */ bool memmap; /* TRUE: Controller is in memory mapped mode */ -#ifdef CONFIG_STM32F7_QSPI_INTERRUPTS +#ifdef CONFIG_STM32_QSPI_INTERRUPTS xcpt_t handler; /* Interrupt handler */ uint8_t irq; /* Interrupt number */ sem_t op_sem; /* Block until complete */ struct qspi_xctnspec_s *xctn; /* context of transaction in progress */ #endif -#ifdef CONFIG_STM32F7_QSPI_DMA +#ifdef CONFIG_STM32_QSPI_DMA bool candma; /* DMA is supported */ sem_t dmawait; /* Used to wait for DMA completion */ int result; /* DMA result */ @@ -181,11 +181,11 @@ struct stm32f7_qspidev_s /* Debug stuff */ -#ifdef CONFIG_STM32F7_QSPI_DMADEBUG +#ifdef CONFIG_STM32_QSPI_DMADEBUG struct stm32f7_dmaregs_s dmaregs[DMA_NSAMPLES]; #endif -#ifdef CONFIG_STM32F7_QSPI_REGDEBUG +#ifdef CONFIG_STM32_QSPI_REGDEBUG bool wrlast; /* Last was a write */ uint32_t addresslast; /* Last address */ uint32_t valuelast; /* Last value */ @@ -222,7 +222,7 @@ struct qspi_xctnspec_s uint8_t isddr; /* true if 'double data rate' */ uint8_t issioo; /* true if 'send instruction only once' mode */ -#ifdef CONFIG_STM32F7_QSPI_INTERRUPTS +#ifdef CONFIG_STM32_QSPI_INTERRUPTS uint8_t function; /* functional mode; to distinguish a read or write */ int8_t disposition; /* how it all turned out */ uint32_t idxnow; /* index into databuffer of current byte in transfer */ @@ -235,7 +235,7 @@ struct qspi_xctnspec_s /* Helpers */ -#ifdef CONFIG_STM32F7_QSPI_REGDEBUG +#ifdef CONFIG_STM32_QSPI_REGDEBUG static bool qspi_checkreg(struct stm32f7_qspidev_s *priv, bool wr, uint32_t value, uint32_t address); #else @@ -262,16 +262,16 @@ static void qspi_dumpgpioconfig(const char *msg); /* Interrupts */ -#ifdef CONFIG_STM32F7_QSPI_INTERRUPTS +#ifdef CONFIG_STM32_QSPI_INTERRUPTS static int qspi0_interrupt(int irq, void *context, void *arg); #endif /* DMA support */ -#ifdef CONFIG_STM32F7_QSPI_DMA +#ifdef CONFIG_STM32_QSPI_DMA -# ifdef CONFIG_STM32F7_QSPI_DMADEBUG +# ifdef CONFIG_STM32_QSPI_DMADEBUG # define qspi_dma_sample(s,i) stm32f7_dmasample((s)->dmach, &(s)->dmaregs[i]) static void qspi_dma_sampleinit(struct stm32f7_qspidev_s *priv); static void qspi_dma_sampledone(struct stm32f7_qspidev_s *priv); @@ -281,8 +281,8 @@ static void qspi_dma_sampledone(struct stm32f7_qspidev_s *priv); # define qspi_dma_sampledone(s) # endif -# ifndef CONFIG_STM32F7_QSPI_DMATHRESHOLD -# define CONFIG_STM32F7_QSPI_DMATHRESHOLD 4 +# ifndef CONFIG_STM32_QSPI_DMATHRESHOLD +# define CONFIG_STM32_QSPI_DMATHRESHOLD 4 # endif #endif @@ -336,13 +336,13 @@ static struct stm32f7_qspidev_s g_qspi0dev = }, .base = STM32_QUADSPI_BASE, .lock = NXMUTEX_INITIALIZER, -#ifdef CONFIG_STM32F7_QSPI_INTERRUPTS +#ifdef CONFIG_STM32_QSPI_INTERRUPTS .handler = qspi0_interrupt, .irq = STM32_IRQ_QUADSPI, .op_sem = SEM_INITIALIZER(0), #endif .intf = 0, -#ifdef CONFIG_STM32F7_QSPI_DMA +#ifdef CONFIG_STM32_QSPI_DMA .candma = true, .dmawait = SEM_INITIALIZER(0), #endif @@ -368,7 +368,7 @@ static struct stm32f7_qspidev_s g_qspi0dev = * ****************************************************************************/ -#ifdef CONFIG_STM32F7_QSPI_REGDEBUG +#ifdef CONFIG_STM32_QSPI_REGDEBUG static bool qspi_checkreg(struct stm32f7_qspidev_s *priv, bool wr, uint32_t value, uint32_t address) { @@ -420,7 +420,7 @@ static inline uint32_t qspi_getreg(struct stm32f7_qspidev_s *priv, uint32_t address = priv->base + offset; uint32_t value = getreg32(address); -#ifdef CONFIG_STM32F7_QSPI_REGDEBUG +#ifdef CONFIG_STM32_QSPI_REGDEBUG if (qspi_checkreg(priv, false, value, address)) { spiinfo("%08" PRIx32 "->%08" PRIx32 "\n", address, value); @@ -443,7 +443,7 @@ static inline void qspi_putreg(struct stm32f7_qspidev_s *priv, { uint32_t address = priv->base + offset; -#ifdef CONFIG_STM32F7_QSPI_REGDEBUG +#ifdef CONFIG_STM32_QSPI_REGDEBUG if (qspi_checkreg(priv, true, value, address)) { spiinfo("%08" PRIx32 "<-%08" PRIx32 "\n", address, value); @@ -625,7 +625,7 @@ static void qspi_dumpgpioconfig(const char *msg) } #endif -#ifdef CONFIG_STM32F7_QSPI_DMADEBUG +#ifdef CONFIG_STM32_QSPI_DMADEBUG /**************************************************************************** * Name: qspi_dma_sampleinit * @@ -831,7 +831,7 @@ static int qspi_setupxctnfromcmd(struct qspi_xctnspec_s *xctn, xctn->isddr = 0; } -#if defined(CONFIG_STM32F7_QSPI_INTERRUPTS) +#if defined(CONFIG_STM32_QSPI_INTERRUPTS) xctn->function = QSPICMD_ISWRITE(cmdinfo->flags) ? CCR_FMODE_INDWR : CCR_FMODE_INDRD; xctn->disposition = - EIO; @@ -962,7 +962,7 @@ static int qspi_setupxctnfrommem(struct qspi_xctnspec_s *xctn, xctn->isddr = 0; -#if defined(CONFIG_STM32F7_QSPI_INTERRUPTS) +#if defined(CONFIG_STM32_QSPI_INTERRUPTS) xctn->function = QSPIMEM_ISWRITE(meminfo->flags) ? CCR_FMODE_INDWR : CCR_FMODE_INDRD; xctn->disposition = - EIO; @@ -1086,7 +1086,7 @@ static void qspi_ccrconfig(struct stm32f7_qspidev_s *priv, } } -#if defined(CONFIG_STM32F7_QSPI_INTERRUPTS) +#if defined(CONFIG_STM32_QSPI_INTERRUPTS) /**************************************************************************** * Name: qspi0_interrupt * @@ -1313,7 +1313,7 @@ static int qspi0_interrupt(int irq, void *context, void *arg) return OK; } -#elif defined(CONFIG_STM32F7_QSPI_DMA) +#elif defined(CONFIG_STM32_QSPI_DMA) /**************************************************************************** * Name: qspi_dma_timeout * @@ -1579,7 +1579,7 @@ static int qspi_memory_dma(struct stm32f7_qspidev_s *priv, } #endif -#if !defined(CONFIG_STM32F7_QSPI_INTERRUPTS) +#if !defined(CONFIG_STM32_QSPI_INTERRUPTS) /**************************************************************************** * Name: qspi_receive_blocking * @@ -2011,7 +2011,7 @@ static int qspi_command(struct qspi_dev_s *dev, QSPI_FCR_CTEF | QSPI_FCR_CTCF | QSPI_FCR_CSMF | QSPI_FCR_CTOF, STM32_QUADSPI_FCR_OFFSET); -#ifdef CONFIG_STM32F7_QSPI_INTERRUPTS +#ifdef CONFIG_STM32_QSPI_INTERRUPTS /* interrupt mode will need access to the transaction context */ priv->xctn = &xctn; @@ -2192,7 +2192,7 @@ static int qspi_memory(struct qspi_dev_s *dev, QSPI_FCR_CTEF | QSPI_FCR_CTCF | QSPI_FCR_CSMF | QSPI_FCR_CTOF, STM32_QUADSPI_FCR_OFFSET); -#ifdef CONFIG_STM32F7_QSPI_INTERRUPTS +#ifdef CONFIG_STM32_QSPI_INTERRUPTS /* interrupt mode will need access to the transaction context */ priv->xctn = &xctn; @@ -2253,11 +2253,11 @@ static int qspi_memory(struct qspi_dev_s *dev, ret = xctn.disposition; -#elif defined(CONFIG_STM32F7_QSPI_DMA) +#elif defined(CONFIG_STM32_QSPI_DMA) /* Can we perform DMA? Should we perform DMA? */ if (priv->candma && - meminfo->buflen > CONFIG_STM32F7_QSPI_DMATHRESHOLD && + meminfo->buflen > CONFIG_STM32_QSPI_DMATHRESHOLD && IS_ALIGNED((uintptr_t)meminfo->buffer, 4) && IS_ALIGNED(meminfo->buflen, 4)) { @@ -2419,18 +2419,18 @@ static int qspi_hw_initialize(struct stm32f7_qspidev_s *priv) regval &= ~(QSPI_CR_TEIE | QSPI_CR_TCIE | QSPI_CR_FTIE | QSPI_CR_SMIE | QSPI_CR_TOIE | QSPI_CR_FSEL | QSPI_CR_DFM); -#if defined(CONFIG_STM32F7_QSPI_MODE_BANK2) +#if defined(CONFIG_STM32_QSPI_MODE_BANK2) regval |= QSPI_CR_FSEL; #endif -#if defined(CONFIG_STM32F7_QSPI_MODE_DUAL) +#if defined(CONFIG_STM32_QSPI_MODE_DUAL) regval |= QSPI_CR_DFM; #endif /* Configure QSPI FIFO Threshold */ regval &= ~(QSPI_CR_FTHRES_MASK); - regval |= ((CONFIG_STM32F7_QSPI_FIFO_THESHOLD - 1) + regval |= ((CONFIG_STM32_QSPI_FIFO_THESHOLD - 1) << QSPI_CR_FTHRES_SHIFT); qspi_putreg(priv, regval, STM32_QUADSPI_CR_OFFSET); @@ -2451,10 +2451,10 @@ static int qspi_hw_initialize(struct stm32f7_qspidev_s *priv) regval = qspi_getreg(priv, STM32_QUADSPI_DCR_OFFSET); regval &= ~(QSPI_DCR_CKMODE | QSPI_DCR_CSHT_MASK | QSPI_DCR_FSIZE_MASK); regval |= (0x00); - regval |= ((CONFIG_STM32F7_QSPI_CSHT - 1) << QSPI_DCR_CSHT_SHIFT); - if (0 != CONFIG_STM32F7_QSPI_FLASH_SIZE) + regval |= ((CONFIG_STM32_QSPI_CSHT - 1) << QSPI_DCR_CSHT_SHIFT); + if (0 != CONFIG_STM32_QSPI_FLASH_SIZE) { - unsigned int nsize = CONFIG_STM32F7_QSPI_FLASH_SIZE; + unsigned int nsize = CONFIG_STM32_QSPI_FLASH_SIZE; int nlog2size = 31; while ((nsize & 0x80000000) == 0) @@ -2489,7 +2489,7 @@ static int qspi_hw_initialize(struct stm32f7_qspidev_s *priv) ****************************************************************************/ /**************************************************************************** - * Name: stm32f7_qspi_initialize + * Name: stm32_qspi_initialize * * Description: * Initialize the selected QSPI port in master mode @@ -2502,7 +2502,7 @@ static int qspi_hw_initialize(struct stm32f7_qspidev_s *priv) * ****************************************************************************/ -struct qspi_dev_s *stm32f7_qspi_initialize(int intf) +struct qspi_dev_s *stm32_qspi_initialize(int intf) { struct stm32f7_qspidev_s *priv; uint32_t regval; @@ -2560,7 +2560,7 @@ struct qspi_dev_s *stm32f7_qspi_initialize(int intf) { /* Now perform one time initialization. */ -#ifdef CONFIG_STM32F7_QSPI_DMA +#ifdef CONFIG_STM32_QSPI_DMA /* Pre-allocate DMA channels. */ if (priv->candma) @@ -2574,7 +2574,7 @@ struct qspi_dev_s *stm32f7_qspi_initialize(int intf) } #endif -#ifdef CONFIG_STM32F7_QSPI_INTERRUPTS +#ifdef CONFIG_STM32_QSPI_INTERRUPTS /* Attach the interrupt handler */ ret = irq_attach(priv->irq, priv->handler, NULL); @@ -2600,7 +2600,7 @@ struct qspi_dev_s *stm32f7_qspi_initialize(int intf) priv->initialized = true; priv->memmap = false; -#ifdef CONFIG_STM32F7_QSPI_INTERRUPTS +#ifdef CONFIG_STM32_QSPI_INTERRUPTS up_enable_irq(priv->irq); #endif } @@ -2608,12 +2608,12 @@ struct qspi_dev_s *stm32f7_qspi_initialize(int intf) return &priv->qspi; errout_with_irq: -#ifdef CONFIG_STM32F7_QSPI_INTERRUPTS +#ifdef CONFIG_STM32_QSPI_INTERRUPTS irq_detach(priv->irq); errout_with_dmach: #endif -#ifdef CONFIG_STM32F7_QSPI_DMA +#ifdef CONFIG_STM32_QSPI_DMA if (priv->dmach) { stm32_dmafree(priv->dmach); @@ -2625,7 +2625,7 @@ struct qspi_dev_s *stm32f7_qspi_initialize(int intf) } /**************************************************************************** - * Name: stm32f7_qspi_enter_memorymapped + * Name: stm32_qspi_enter_memorymapped * * Description: * Put the QSPI device into memory mapped mode @@ -2639,7 +2639,7 @@ struct qspi_dev_s *stm32f7_qspi_initialize(int intf) * ****************************************************************************/ -void stm32f7_qspi_enter_memorymapped(struct qspi_dev_s *dev, +void stm32_qspi_enter_memorymapped(struct qspi_dev_s *dev, const struct qspi_meminfo_s *meminfo, uint32_t lpto) { @@ -2679,7 +2679,7 @@ void stm32f7_qspi_enter_memorymapped(struct qspi_dev_s *dev, qspi_putreg(&g_qspi0dev, QSPI_FCR_CTOF, STM32_QUADSPI_FCR_OFFSET); -#ifdef CONFIG_STM32F7_QSPI_INTERRUPTS +#ifdef CONFIG_STM32_QSPI_INTERRUPTS /* Enable Timeout interrupt */ regval = qspi_getreg(priv, STM32_QUADSPI_CR_OFFSET); @@ -2698,7 +2698,7 @@ void stm32f7_qspi_enter_memorymapped(struct qspi_dev_s *dev, qspi_setupxctnfrommem(&xctn, meminfo); -#ifdef CONFIG_STM32F7_QSPI_INTERRUPTS +#ifdef CONFIG_STM32_QSPI_INTERRUPTS priv->xctn = NULL; #endif @@ -2717,7 +2717,7 @@ void stm32f7_qspi_enter_memorymapped(struct qspi_dev_s *dev, } /**************************************************************************** - * Name: stm32f7_qspi_exit_memorymapped + * Name: stm32_qspi_exit_memorymapped * * Description: * Take the QSPI device out of memory mapped mode @@ -2730,7 +2730,7 @@ void stm32f7_qspi_enter_memorymapped(struct qspi_dev_s *dev, * ****************************************************************************/ -void stm32f7_qspi_exit_memorymapped(struct qspi_dev_s *dev) +void stm32_qspi_exit_memorymapped(struct qspi_dev_s *dev) { struct stm32f7_qspidev_s *priv = (struct stm32f7_qspidev_s *)dev; @@ -2744,4 +2744,4 @@ void stm32f7_qspi_exit_memorymapped(struct qspi_dev_s *dev) qspi_lock(dev, false); } -#endif /* CONFIG_STM32F7_QSPI */ +#endif /* CONFIG_STM32_QSPI */ diff --git a/arch/arm/src/stm32f7/stm32_qspi.h b/arch/arm/src/stm32f7/stm32_qspi.h index 018bf0c117399..c10cb95d8bbb7 100644 --- a/arch/arm/src/stm32f7/stm32_qspi.h +++ b/arch/arm/src/stm32f7/stm32_qspi.h @@ -35,7 +35,7 @@ #include "chip.h" -#ifdef CONFIG_STM32F7_QUADSPI +#ifdef CONFIG_STM32_QSPI /**************************************************************************** * Pre-processor Definitions @@ -83,7 +83,7 @@ extern "C" ****************************************************************************/ struct qspi_dev_s; -struct qspi_dev_s *stm32f7_qspi_initialize(int intf); +struct qspi_dev_s *stm32_qspi_initialize(int intf); /**************************************************************************** * Name: stm32l4_qspi_enter_memorymapped @@ -101,7 +101,7 @@ struct qspi_dev_s *stm32f7_qspi_initialize(int intf); * ****************************************************************************/ -void stm32f7_qspi_enter_memorymapped(struct qspi_dev_s *dev, +void stm32_qspi_enter_memorymapped(struct qspi_dev_s *dev, const struct qspi_meminfo_s *meminfo, uint32_t lpto); @@ -119,7 +119,7 @@ void stm32f7_qspi_enter_memorymapped(struct qspi_dev_s *dev, * ****************************************************************************/ -void stm32f7_qspi_exit_memorymapped(struct qspi_dev_s *dev); +void stm32_qspi_exit_memorymapped(struct qspi_dev_s *dev); #undef EXTERN #if defined(__cplusplus) @@ -127,5 +127,5 @@ void stm32f7_qspi_exit_memorymapped(struct qspi_dev_s *dev); #endif #endif /* __ASSEMBLY__ */ -#endif /* CONFIG_STM32F7_QSPI */ +#endif /* CONFIG_STM32_QSPI */ #endif /* __ARCH_ARM_SRC_STM32F7_STM32_QSPI_H */ diff --git a/arch/arm/src/stm32f7/stm32_rcc.c b/arch/arm/src/stm32f7/stm32_rcc.c index 92b4ec75fef6a..b0c35860a24fb 100644 --- a/arch/arm/src/stm32f7/stm32_rcc.c +++ b/arch/arm/src/stm32f7/stm32_rcc.c @@ -63,11 +63,11 @@ static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1, /* Include chip-specific clocking initialization logic */ -#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX) +#if defined(CONFIG_STM32_STM32F72XX) || defined(CONFIG_STM32_STM32F73XX) # include "stm32f72xx73xx_rcc.c" -#elif defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) +#elif defined(CONFIG_STM32_STM32F74XX) || defined(CONFIG_STM32_STM32F75XX) # include "stm32f74xx75xx_rcc.c" -#elif defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) +#elif defined(CONFIG_STM32_STM32F76XX) || defined(CONFIG_STM32_STM32F77XX) # include "stm32f76xx77xx_rcc.c" #else # error "Unsupported STM32 F7 chip" @@ -86,7 +86,7 @@ static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1, * and enable peripheral clocking for all peripherals enabled in the NuttX * configurationfile. * - * If CONFIG_STM32F7_CUSTOM_CLOCKCONFIG is defined, then clocking + * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then clocking * will be enabled by an externally provided, board-specific function * called stm32_board_clockconfig(). * @@ -104,14 +104,14 @@ void stm32_clockconfig(void) rcc_reset(); -#if defined(CONFIG_STM32F7_PWR) +#if defined(CONFIG_STM32_PWR) /* Insure the bkp is initialized */ stm32_pwr_initbkp(false); #endif -#if defined(CONFIG_STM32F7_CUSTOM_CLOCKCONFIG) +#if defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) /* Invoke Board Custom Clock Configuration */ @@ -131,7 +131,7 @@ void stm32_clockconfig(void) rcc_enableperipherals(); -#ifdef CONFIG_STM32F7_SYSCFG_IOCOMPENSATION +#ifdef CONFIG_STM32_SYSCFG_IOCOMPENSATION /* Enable I/O Compensation */ stm32_iocompensation(); @@ -151,7 +151,7 @@ void stm32_clockconfig(void) * stm32_clockconfig(): It does not reset any devices, and it does not * reset the currently enabled peripheral clocks. * - * If CONFIG_STM32F7_CUSTOM_CLOCKCONFIG is defined, then clocking + * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then clocking * will be enabled by an externally provided, board-specific function * called stm32_board_clockconfig(). * @@ -166,7 +166,7 @@ void stm32_clockconfig(void) #ifdef CONFIG_PM void stm32_clockenable(void) { -#if defined(CONFIG_STM32F7_CUSTOM_CLOCKCONFIG) +#if defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) /* Invoke Board Custom Clock Configuration */ diff --git a/arch/arm/src/stm32f7/stm32_rcc.h b/arch/arm/src/stm32f7/stm32_rcc.h index b1c7aaefe37fb..2bf57bb9855ab 100644 --- a/arch/arm/src/stm32f7/stm32_rcc.h +++ b/arch/arm/src/stm32f7/stm32_rcc.h @@ -124,9 +124,9 @@ static inline void stm32_mco2config(uint32_t source, uint32_t div) * and enable peripheral clocking for all peripherals enabled in the NuttX * configuration file. * - * If CONFIG_STM32F7_CUSTOM_CLOCKCONFIG is defined, then clocking will be - * enabled by an externally provided, board-specific function called - * stm32_board_clockconfig(). + * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then clocking + * will be enabled by an externally provided, board-specific function + * called stm32_board_clockconfig(). * * Input Parameters: * None @@ -147,7 +147,7 @@ void stm32_clockconfig(void); * ****************************************************************************/ -#ifdef CONFIG_STM32F7_CUSTOM_CLOCKCONFIG +#ifdef CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG void stm32_board_clockconfig(void); #endif @@ -164,9 +164,9 @@ void stm32_board_clockconfig(void); * stm32_clockconfig(): It does not reset any devices, and it does not * reset the currently enabled peripheral clocks. * - * If CONFIG_STM32F7_CUSTOM_CLOCKCONFIG is defined, then clocking will - * be enabled by an externally provided, board-specific function called - * stm32_board_clockconfig(). + * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then clocking + * will be enabled by an externally provided, board-specific function + * called stm32_board_clockconfig(). * * Input Parameters: * None @@ -216,26 +216,26 @@ void stm32_rcc_enablelsi(void); void stm32_rcc_disablelsi(void); -#if defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) +#if defined(CONFIG_STM32_STM32F76XX) || defined(CONFIG_STM32_STM32F77XX) /**************************************************************************** - * Name: stm32f7x9_rcc_dsisrcphy + * Name: stm32_rcc_dsisrcphy * * Description: * Set DSI clock source to DSI PHY * ****************************************************************************/ -void stm32f7x9_rcc_dsisrcphy(void); +void stm32_rcc_dsisrcphy(void); /**************************************************************************** - * Name: stm32f7x9_rcc_dsisrcpllr + * Name: stm32_rcc_dsisrcpllr * * Description: * Set DSI clock source to PLLR * ****************************************************************************/ -void stm32f7x9_rcc_dsisrcpllr(void); +void stm32_rcc_dsisrcpllr(void); #endif #undef EXTERN diff --git a/arch/arm/src/stm32f7/stm32_rng.c b/arch/arm/src/stm32f7/stm32_rng.c index 7eeb2d4916c6f..10bad1e664e32 100644 --- a/arch/arm/src/stm32f7/stm32_rng.c +++ b/arch/arm/src/stm32f7/stm32_rng.c @@ -40,7 +40,7 @@ #include "hardware/stm32_rng.h" #include "arm_internal.h" -#if defined(CONFIG_STM32F7_RNG) +#if defined(CONFIG_STM32_RNG) #if defined(CONFIG_DEV_RANDOM) || defined(CONFIG_DEV_URANDOM_ARCH) /**************************************************************************** @@ -329,4 +329,4 @@ void devurandom_register(void) #endif #endif /* CONFIG_DEV_RANDOM || CONFIG_DEV_URANDOM_ARCH */ -#endif /* CONFIG_STM32F7_RNG */ +#endif /* CONFIG_STM32_RNG */ diff --git a/arch/arm/src/stm32f7/stm32_rtc.c b/arch/arm/src/stm32f7/stm32_rtc.c index c5d1cc56096b3..9e2deaff4a05f 100644 --- a/arch/arm/src/stm32f7/stm32_rtc.c +++ b/arch/arm/src/stm32f7/stm32_rtc.c @@ -44,7 +44,7 @@ #include -#ifdef CONFIG_STM32F7_RTC +#ifdef CONFIG_STM32_RTC /**************************************************************************** * Pre-processor Definitions @@ -65,17 +65,17 @@ # error "CONFIG_RTC_HIRES must NOT be set with this driver" #endif -#ifndef CONFIG_STM32F7_PWR -# error "CONFIG_STM32F7_PWR must selected to use this driver" +#ifndef CONFIG_STM32_PWR +# error "CONFIG_STM32_PWR must selected to use this driver" #endif /* Constants ****************************************************************/ -#if defined(CONFIG_STM32F7_RTC_HSECLOCK) +#if defined(CONFIG_STM32_RTC_HSECLOCK) # define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_HSE -#elif defined(CONFIG_STM32F7_RTC_LSICLOCK) +#elif defined(CONFIG_STM32_RTC_LSICLOCK) # define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_LSI -#elif defined(CONFIG_STM32F7_RTC_LSECLOCK) +#elif defined(CONFIG_STM32_RTC_LSECLOCK) # define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_LSE #else # warning "RCC_BDCR_RTCSEL_NOCLK has been selected - RTC will not count" @@ -491,7 +491,7 @@ static int rtc_setup(void) /* Configure RTC pre-scaler with the required values */ -#ifdef CONFIG_STM32F7_RTC_HSECLOCK +#ifdef CONFIG_STM32_RTC_HSECLOCK /* STMicro app note AN4759 suggests using 7999 and 124 to * get exactly 1MHz when using the RTC at 8MHz. */ @@ -940,17 +940,17 @@ int up_rtc_initialize(void) * external high rate clock */ -#ifdef CONFIG_STM32F7_RTC_HSECLOCK +#ifdef CONFIG_STM32_RTC_HSECLOCK /* Use the HSE clock as the input to the RTC block */ rtc_dumpregs("On reset HSE"); -#elif defined(CONFIG_STM32F7_RTC_LSICLOCK) +#elif defined(CONFIG_STM32_RTC_LSICLOCK) /* Use the LSI clock as the input to the RTC block */ rtc_dumpregs("On reset LSI"); -#elif defined(CONFIG_STM32F7_RTC_LSECLOCK) +#elif defined(CONFIG_STM32_RTC_LSECLOCK) /* Use the LSE clock as the input to the RTC block */ rtc_dumpregs("On reset LSE"); @@ -1102,7 +1102,7 @@ int up_rtc_initialize(void) * ****************************************************************************/ -#ifdef CONFIG_STM32F7_HAVE_RTC_SUBSECONDS +#ifdef CONFIG_STM32_HAVE_RTC_SUBSECONDS int stm32_rtc_getdatetime_with_subseconds(struct tm *tp, long *nsec) #else int up_rtc_getdatetime(struct tm *tp) @@ -1111,7 +1111,7 @@ int up_rtc_getdatetime(struct tm *tp) uint32_t dr; uint32_t tr; uint32_t tmp; -#ifdef CONFIG_STM32F7_HAVE_RTC_SUBSECONDS +#ifdef CONFIG_STM32_HAVE_RTC_SUBSECONDS uint32_t ssr; uint32_t prediv_s; uint32_t usecs; @@ -1129,7 +1129,7 @@ int up_rtc_getdatetime(struct tm *tp) { dr = getreg32(STM32_RTC_DR); tr = getreg32(STM32_RTC_TR); -#ifdef CONFIG_STM32F7_HAVE_RTC_SUBSECONDS +#ifdef CONFIG_STM32_HAVE_RTC_SUBSECONDS ssr = getreg32(STM32_RTC_SSR); tmp = getreg32(STM32_RTC_TR); if (tmp != tr) @@ -1186,7 +1186,7 @@ int up_rtc_getdatetime(struct tm *tp) clock_daysbeforemonth(tp->tm_mon, clock_isleapyear(tp->tm_year + 1900)); tp->tm_isdst = 0; -#ifdef CONFIG_STM32F7_HAVE_RTC_SUBSECONDS +#ifdef CONFIG_STM32_HAVE_RTC_SUBSECONDS /* Return RTC sub-seconds if a non-NULL value * of nsec has been provided to receive the sub-second value. */ @@ -1207,7 +1207,7 @@ int up_rtc_getdatetime(struct tm *tp) } rtc_dumptime((const struct tm *)tp, &usecs, "Returning"); -#else /* CONFIG_STM32F7_HAVE_RTC_SUBSECONDS */ +#else /* CONFIG_STM32_HAVE_RTC_SUBSECONDS */ rtc_dumptime((const struct tm *)tp, NULL, "Returning"); #endif @@ -1237,7 +1237,7 @@ int up_rtc_getdatetime(struct tm *tp) * ****************************************************************************/ -#ifdef CONFIG_STM32F7_HAVE_RTC_SUBSECONDS +#ifdef CONFIG_STM32_HAVE_RTC_SUBSECONDS int up_rtc_getdatetime(struct tm *tp) { return stm32_rtc_getdatetime_with_subseconds(tp, NULL); @@ -1270,8 +1270,8 @@ int up_rtc_getdatetime(struct tm *tp) ****************************************************************************/ #ifdef CONFIG_ARCH_HAVE_RTC_SUBSECONDS -# ifndef CONFIG_STM32F7_HAVE_RTC_SUBSECONDS -# error "Invalid config, enable CONFIG_STM32F7_HAVE_RTC_SUBSECONDS." +# ifndef CONFIG_STM32_HAVE_RTC_SUBSECONDS +# error "Invalid config, enable CONFIG_STM32_HAVE_RTC_SUBSECONDS." # endif int up_rtc_getdatetime_with_subseconds(struct tm *tp, long *nsec) { @@ -1775,11 +1775,11 @@ int stm32_rtc_setperiodic(const struct timespec *period, uint32_t secs; uint32_t millisecs; -#if defined(CONFIG_STM32F7_RTC_HSECLOCK) +#if defined(CONFIG_STM32_RTC_HSECLOCK) # error "Periodic wakeup not available for HSE" -#elif defined(CONFIG_STM32F7_RTC_LSICLOCK) +#elif defined(CONFIG_STM32_RTC_LSICLOCK) # error "Periodic wakeup not available for LSI (and it is too inaccurate!)" -#elif defined(CONFIG_STM32F7_RTC_LSECLOCK) +#elif defined(CONFIG_STM32_RTC_LSECLOCK) const uint32_t rtc_div16_max_msecs = 16 * 1000 * 0xffffu / STM32_LSE_FREQUENCY; #else @@ -1950,4 +1950,4 @@ int stm32_rtc_cancelperiodic(void) } #endif -#endif /* CONFIG_STM32F7_RTC */ +#endif /* CONFIG_STM32_RTC */ diff --git a/arch/arm/src/stm32f7/stm32_rtc.h b/arch/arm/src/stm32f7/stm32_rtc.h index 91ce504952357..b6130256949f0 100644 --- a/arch/arm/src/stm32f7/stm32_rtc.h +++ b/arch/arm/src/stm32f7/stm32_rtc.h @@ -46,21 +46,21 @@ #define STM32_RTC_PRESCALER_SECOND 32767 /* Default prescaler to get a second base */ #define STM32_RTC_PRESCALER_MIN 1 /* Maximum speed of 16384 Hz */ -#if !defined(CONFIG_STM32F7_RTC_MAGIC) -# define CONFIG_STM32F7_RTC_MAGIC (0xfacefeed) +#if !defined(CONFIG_STM32_RTC_MAGIC) +# define CONFIG_STM32_RTC_MAGIC (0xfacefeed) #endif -#if !defined(CONFIG_STM32F7_RTC_MAGIC_TIME_SET) -# define CONFIG_STM32F7_RTC_MAGIC_TIME_SET (0xf00dface) +#if !defined(CONFIG_STM32_RTC_MAGIC_TIME_SET) +# define CONFIG_STM32_RTC_MAGIC_TIME_SET (0xf00dface) #endif -#if !defined(CONFIG_STM32F7_RTC_MAGIC_REG) -# define CONFIG_STM32F7_RTC_MAGIC_REG (0) +#if !defined(CONFIG_STM32_RTC_MAGIC_REG) +# define CONFIG_STM32_RTC_MAGIC_REG (0) #endif -#define RTC_MAGIC CONFIG_STM32F7_RTC_MAGIC -#define RTC_MAGIC_TIME_SET CONFIG_STM32F7_RTC_MAGIC_TIME_SET -#define RTC_MAGIC_REG STM32_RTC_BKR(CONFIG_STM32F7_RTC_MAGIC_REG) +#define RTC_MAGIC CONFIG_STM32_RTC_MAGIC +#define RTC_MAGIC_TIME_SET CONFIG_STM32_RTC_MAGIC_TIME_SET +#define RTC_MAGIC_REG STM32_RTC_BKR(CONFIG_STM32_RTC_MAGIC_REG) /**************************************************************************** * Public Types @@ -106,7 +106,7 @@ extern "C" * ****************************************************************************/ -#ifdef CONFIG_STM32F7_HAVE_RTC_SUBSECONDS +#ifdef CONFIG_STM32_HAVE_RTC_SUBSECONDS int stm32_rtc_getdatetime_with_subseconds(struct tm *tp, long *nsec); #endif diff --git a/arch/arm/src/stm32f7/stm32_sai.c b/arch/arm/src/stm32f7/stm32_sai.c index 3883278b6f33a..c037660ac41da 100644 --- a/arch/arm/src/stm32f7/stm32_sai.c +++ b/arch/arm/src/stm32f7/stm32_sai.c @@ -68,7 +68,7 @@ #include "stm32_sai.h" #include "stm32_pwr.h" -#ifdef CONFIG_STM32F7_SAI +#ifdef CONFIG_STM32_SAI /**************************************************************************** * Pre-processor Definitions @@ -86,49 +86,49 @@ # error CONFIG_I2S required by this driver #endif -#ifdef CONFIG_STM32F7_SAI_POLLING +#ifdef CONFIG_STM32_SAI_POLLING # error "Polling SAI not yet supported" #endif -#ifdef CONFIG_STM32F7_SAI_INTERRUPTS +#ifdef CONFIG_STM32_SAI_INTERRUPTS # error "Interrupt driven SAI not yet supported" #endif -#ifndef CONFIG_STM32F7_SAI_DEFAULT_SAMPLERATE -# define CONFIG_STM32F7_SAI_DEFAULT_SAMPLERATE (48000) +#ifndef CONFIG_STM32_SAI_DEFAULT_SAMPLERATE +# define CONFIG_STM32_SAI_DEFAULT_SAMPLERATE (48000) #endif -#ifndef CONFIG_STM32F7_SAI_DEFAULT_DATALEN -# define CONFIG_STM32F7_SAI_DEFAULT_DATALEN (16) +#ifndef CONFIG_STM32_SAI_DEFAULT_DATALEN +# define CONFIG_STM32_SAI_DEFAULT_DATALEN (16) #endif -#ifndef CONFIG_STM32F7_SAI_MAXINFLIGHT -# define CONFIG_STM32F7_SAI_MAXINFLIGHT (16) +#ifndef CONFIG_STM32_SAI_MAXINFLIGHT +# define CONFIG_STM32_SAI_MAXINFLIGHT (16) #endif -#ifdef CONFIG_STM32F7_SAI1 -#ifndef STM32F7_SAI1_FREQUENCY -# error "Please define STM32F7_SAI1_FREQUENCY in board.h" +#ifdef CONFIG_STM32_SAI1 +#ifndef STM32_SAI1_FREQUENCY +# error "Please define STM32_SAI1_FREQUENCY in board.h" #endif #endif -#ifdef CONFIG_STM32F7_SAI2 -#ifndef STM32F7_SAI2_FREQUENCY -# error "Please define STM32F7_SAI1_FREQUENCY in board.h" +#ifdef CONFIG_STM32_SAI2 +#ifndef STM32_SAI2_FREQUENCY +# error "Please define STM32_SAI1_FREQUENCY in board.h" #endif #endif -#ifdef CONFIG_STM32F7_SAI_DMA +#ifdef CONFIG_STM32_SAI_DMA /* SAI DMA priority */ -# if defined(CONFIG_STM32F7_SAI_DMAPRIO) -# define SAI_DMA_PRIO CONFIG_STM32F7_SAI_DMAPRIO +# if defined(CONFIG_STM32_SAI_DMAPRIO) +# define SAI_DMA_PRIO CONFIG_STM32_SAI_DMAPRIO # else # define SAI_DMA_PRIO DMA_SCR_PRIVERYHI # endif # if (SAI_DMA_PRIO & ~DMA_SCR_PL_MASK) != 0 -# error "Illegal value for CONFIG_STM32F7_SAI_DMAPRIO" +# error "Illegal value for CONFIG_STM32_SAI_DMAPRIO" # endif /* DMA channel/stream configuration register settings. The following @@ -194,7 +194,7 @@ struct stm32f7_sai_s mutex_t lock; /* Assures mutually exclusive access to SAI */ uint32_t frequency; /* SAI clock frequency */ uint32_t syncen; /* Synchronization setting */ -#ifdef CONFIG_STM32F7_SAI_DMA +#ifdef CONFIG_STM32_SAI_DMA uint16_t dma_ch; /* DMA channel number */ DMA_HANDLE dma; /* DMA channel handle */ uint32_t dma_ccr; /* DMA control register */ @@ -213,7 +213,7 @@ struct stm32f7_sai_s sem_t bufsem; /* Buffer wait semaphore */ struct sai_buffer_s *freelist; /* A list a free buffer containers */ - struct sai_buffer_s containers[CONFIG_STM32F7_SAI_MAXINFLIGHT]; + struct sai_buffer_s containers[CONFIG_STM32_SAI_MAXINFLIGHT]; }; /**************************************************************************** @@ -236,7 +236,7 @@ static void sai_buf_initialize(struct stm32f7_sai_s *priv); /* DMA support */ -#ifdef CONFIG_STM32F7_SAI_DMA +#ifdef CONFIG_STM32_SAI_DMA static void sai_schedule(struct stm32f7_sai_s *priv, int result); static void sai_dma_callback(DMA_HANDLE handle, uint8_t isr, void *arg); #endif @@ -274,89 +274,89 @@ static const struct i2s_ops_s g_i2sops = /* SAI1 state */ -#ifdef CONFIG_STM32F7_SAI1_A +#ifdef CONFIG_STM32_SAI1_A static struct stm32f7_sai_s g_sai1a_priv = { .dev.ops = &g_i2sops, - .base = STM32F7_SAI1_A_BASE, + .base = STM32_SAI1_A_BASE, .lock = NXMUTEX_INITIALIZER, - .frequency = STM32F7_SAI1_FREQUENCY, -#ifdef CONFIG_STM32F7_SAI1_A_SYNC_WITH_B + .frequency = STM32_SAI1_FREQUENCY, +#ifdef CONFIG_STM32_SAI1_A_SYNC_WITH_B .syncen = SAI_CR1_SYNCEN_INTERNAL, #else .syncen = SAI_CR1_SYNCEN_ASYNCH, #endif -#ifdef CONFIG_STM32F7_SAI_DMA +#ifdef CONFIG_STM32_SAI_DMA .dma_ch = DMACHAN_SAI1_A, #endif - .datalen = CONFIG_STM32F7_SAI_DEFAULT_DATALEN, - .samplerate = CONFIG_STM32F7_SAI_DEFAULT_SAMPLERATE, - .bufsem = SEM_INITIALIZER(CONFIG_STM32F7_SAI_MAXINFLIGHT), + .datalen = CONFIG_STM32_SAI_DEFAULT_DATALEN, + .samplerate = CONFIG_STM32_SAI_DEFAULT_SAMPLERATE, + .bufsem = SEM_INITIALIZER(CONFIG_STM32_SAI_MAXINFLIGHT), }; #endif -#ifdef CONFIG_STM32F7_SAI1_B +#ifdef CONFIG_STM32_SAI1_B static struct stm32f7_sai_s g_sai1b_priv = { .dev.ops = &g_i2sops, - .base = STM32F7_SAI1_B_BASE, + .base = STM32_SAI1_B_BASE, .lock = NXMUTEX_INITIALIZER, - .frequency = STM32F7_SAI1_FREQUENCY, -#ifdef CONFIG_STM32F7_SAI1_B_SYNC_WITH_A + .frequency = STM32_SAI1_FREQUENCY, +#ifdef CONFIG_STM32_SAI1_B_SYNC_WITH_A .syncen = SAI_CR1_SYNCEN_INTERNAL, #else .syncen = SAI_CR1_SYNCEN_ASYNCH, #endif -#ifdef CONFIG_STM32F7_SAI_DMA +#ifdef CONFIG_STM32_SAI_DMA .dma_ch = DMACHAN_SAI1_B, #endif - .datalen = CONFIG_STM32F7_SAI_DEFAULT_DATALEN, - .samplerate = CONFIG_STM32F7_SAI_DEFAULT_SAMPLERATE, - .bufsem = SEM_INITIALIZER(CONFIG_STM32F7_SAI_MAXINFLIGHT), + .datalen = CONFIG_STM32_SAI_DEFAULT_DATALEN, + .samplerate = CONFIG_STM32_SAI_DEFAULT_SAMPLERATE, + .bufsem = SEM_INITIALIZER(CONFIG_STM32_SAI_MAXINFLIGHT), }; #endif /* SAI2 state */ -#ifdef CONFIG_STM32F7_SAI2_A +#ifdef CONFIG_STM32_SAI2_A static struct stm32f7_sai_s g_sai2a_priv = { .dev.ops = &g_i2sops, - .base = STM32F7_SAI2_A_BASE, + .base = STM32_SAI2_A_BASE, .lock = NXMUTEX_INITIALIZER, - .frequency = STM32F7_SAI2_FREQUENCY, -#ifdef CONFIG_STM32F7_SAI2_A_SYNC_WITH_B + .frequency = STM32_SAI2_FREQUENCY, +#ifdef CONFIG_STM32_SAI2_A_SYNC_WITH_B .syncen = SAI_CR1_SYNCEN_INTERNAL, #else .syncen = SAI_CR1_SYNCEN_ASYNCH, #endif -#ifdef CONFIG_STM32F7_SAI_DMA +#ifdef CONFIG_STM32_SAI_DMA .dma_ch = DMACHAN_SAI2_A, #endif - .datalen = CONFIG_STM32F7_SAI_DEFAULT_DATALEN, - .samplerate = CONFIG_STM32F7_SAI_DEFAULT_SAMPLERATE, - .bufsem = SEM_INITIALIZER(CONFIG_STM32F7_SAI_MAXINFLIGHT), + .datalen = CONFIG_STM32_SAI_DEFAULT_DATALEN, + .samplerate = CONFIG_STM32_SAI_DEFAULT_SAMPLERATE, + .bufsem = SEM_INITIALIZER(CONFIG_STM32_SAI_MAXINFLIGHT), }; #endif -#ifdef CONFIG_STM32F7_SAI2_B +#ifdef CONFIG_STM32_SAI2_B static struct stm32f7_sai_s g_sai2b_priv = { .dev.ops = &g_i2sops, - .base = STM32F7_SAI2_B_BASE, + .base = STM32_SAI2_B_BASE, .lock = NXMUTEX_INITIALIZER, - .frequency = STM32F7_SAI2_FREQUENCY, -#ifdef CONFIG_STM32F7_SAI2_B_SYNC_WITH_A + .frequency = STM32_SAI2_FREQUENCY, +#ifdef CONFIG_STM32_SAI2_B_SYNC_WITH_A .syncen = SAI_CR1_SYNCEN_INTERNAL, #else .syncen = SAI_CR1_SYNCEN_ASYNCH, #endif -#ifdef CONFIG_STM32F7_SAI_DMA +#ifdef CONFIG_STM32_SAI_DMA .dma_ch = DMACHAN_SAI2_B, #endif - .datalen = CONFIG_STM32F7_SAI_DEFAULT_DATALEN, - .samplerate = CONFIG_STM32F7_SAI_DEFAULT_SAMPLERATE, - .bufsem = SEM_INITIALIZER(CONFIG_STM32F7_SAI_MAXINFLIGHT), + .datalen = CONFIG_STM32_SAI_DEFAULT_DATALEN, + .samplerate = CONFIG_STM32_SAI_DEFAULT_SAMPLERATE, + .bufsem = SEM_INITIALIZER(CONFIG_STM32_SAI_MAXINFLIGHT), }; #endif @@ -479,30 +479,30 @@ static void sai_dump_regs(struct stm32f7_sai_s *priv, const char *msg) #if 0 i2sinfo("CR1:%08" PRIx32 " CR2:%08" PRIx32 " FRCR:%08" PRIx32 " SLOTR:%08" PRIx32 "\n", - sai_getreg(priv, STM32F7_SAI_CR1_OFFSET), - sai_getreg(priv, STM32F7_SAI_CR2_OFFSET), - sai_getreg(priv, STM32F7_SAI_FRCR_OFFSET), - sai_getreg(priv, STM32F7_SAI_SLOTR_OFFSET)); + sai_getreg(priv, STM32_SAI_CR1_OFFSET), + sai_getreg(priv, STM32_SAI_CR2_OFFSET), + sai_getreg(priv, STM32_SAI_FRCR_OFFSET), + sai_getreg(priv, STM32_SAI_SLOTR_OFFSET)); i2sinfo(" IM:%08" PRIx32 " SR:%08" PRIx32 " CLRFR:%08" PRIx32 "\n", - sai_getreg(priv, STM32F7_SAI_IM_OFFSET), - sai_getreg(priv, STM32F7_SAI_SR_OFFSET), - sai_getreg(priv, STM32F7_SAI_CLRFR_OFFSET)); + sai_getreg(priv, STM32_SAI_IM_OFFSET), + sai_getreg(priv, STM32_SAI_SR_OFFSET), + sai_getreg(priv, STM32_SAI_CLRFR_OFFSET)); #else /* GCR */ -#ifdef CONFIG_STM32F7_SAI1 - uint32_t gcr = getreg32(STM32F7_SAI1_GCR); - i2sinfo("GCR: *%08x = %08" PRIx32 "\n", STM32F7_SAI1_GCR, gcr); +#ifdef CONFIG_STM32_SAI1 + uint32_t gcr = getreg32(STM32_SAI1_GCR); + i2sinfo("GCR: *%08x = %08" PRIx32 "\n", STM32_SAI1_GCR, gcr); #else - uint32_t gcr = getreg32(STM32F7_SAI2_GCR); - i2sinfo("GCR: *%08x = %08" PRIx32 "\n", STM32F7_SAI2_GCR, gcr); + uint32_t gcr = getreg32(STM32_SAI2_GCR); + i2sinfo("GCR: *%08x = %08" PRIx32 "\n", STM32_SAI2_GCR, gcr); #endif /* CR1 */ - uint32_t cr1 = sai_getreg(priv, STM32F7_SAI_CR1_OFFSET); - i2sinfo("CR1: *%08" PRIx32 " = %08x\n", STM32F7_SAI_CR1_OFFSET, cr1); + uint32_t cr1 = sai_getreg(priv, STM32_SAI_CR1_OFFSET); + i2sinfo("CR1: *%08" PRIx32 " = %08x\n", STM32_SAI_CR1_OFFSET, cr1); uint32_t mode = (cr1 & SAI_CR1_MODE_MASK) >> SAI_CR1_MODE_SHIFT; const char *mode_string[] = @@ -584,8 +584,8 @@ static void sai_dump_regs(struct stm32f7_sai_s *priv, const char *msg) /* CR2 */ - uint32_t cr2 = sai_getreg(priv, STM32F7_SAI_CR2_OFFSET); - i2sinfo("CR2: *%08x = %08" PRIx32 "\n", STM32F7_SAI_CR2_OFFSET, cr2); + uint32_t cr2 = sai_getreg(priv, STM32_SAI_CR2_OFFSET); + i2sinfo("CR2: *%08x = %08" PRIx32 "\n", STM32_SAI_CR2_OFFSET, cr2); uint32_t fth = (cr2 & SAI_CR2_FTH_MASK) >> SAI_CR2_FTH_SHIFT; const char *fth_string[] = { "FIFO empty", @@ -638,8 +638,8 @@ static void sai_dump_regs(struct stm32f7_sai_s *priv, const char *msg) /* FRCR */ - uint32_t frcr = sai_getreg(priv, STM32F7_SAI_FRCR_OFFSET); - i2sinfo("FRCR: *%08x = %08" PRIx32 "\n", STM32F7_SAI_FRCR_OFFSET, frcr); + uint32_t frcr = sai_getreg(priv, STM32_SAI_FRCR_OFFSET); + i2sinfo("FRCR: *%08x = %08" PRIx32 "\n", STM32_SAI_FRCR_OFFSET, frcr); uint32_t frl = (frcr & SAI_FRCR_FRL_MASK) >> SAI_FRCR_FRL_SHIFT; i2sinfo("\t\tFRCR: FRL[7:0] = %d\n", frl); @@ -662,8 +662,8 @@ static void sai_dump_regs(struct stm32f7_sai_s *priv, const char *msg) /* SLOTR */ - uint32_t slotr = sai_getreg(priv, STM32F7_SAI_SLOTR_OFFSET); - i2sinfo("SLOTR: *%08x = %08" PRIx32 "\n", STM32F7_SAI_SLOTR_OFFSET, slotr); + uint32_t slotr = sai_getreg(priv, STM32_SAI_SLOTR_OFFSET); + i2sinfo("SLOTR: *%08x = %08" PRIx32 "\n", STM32_SAI_SLOTR_OFFSET, slotr); uint32_t fboff = (slotr & SAI_SLOTR_FBOFF_MASK) >> SAI_SLOTR_FBOFF_SHIFT; i2sinfo("\t\tSLOTR: FBOFF[4:0] = %d\n", fboff); @@ -731,7 +731,7 @@ static void sai_mckdivider(struct stm32f7_sai_s *priv) mckdiv += 1; } - sai_modifyreg(priv, STM32F7_SAI_CR1_OFFSET, SAI_CR1_MCKDIV_MASK, + sai_modifyreg(priv, STM32_SAI_CR1_OFFSET, SAI_CR1_MCKDIV_MASK, mckdiv << SAI_CR1_MCKDIV_SHIFT); } @@ -757,7 +757,7 @@ static void sai_timeout(wdparm_t arg) struct stm32f7_sai_s *priv = (struct stm32f7_sai_s *)arg; DEBUGASSERT(priv != NULL); -#ifdef CONFIG_STM32F7_SAI_DMA +#ifdef CONFIG_STM32_SAI_DMA /* Cancel the DMA */ stm32_dmastop(priv->dma); @@ -787,7 +787,7 @@ static void sai_timeout(wdparm_t arg) * ****************************************************************************/ -#ifdef CONFIG_STM32F7_SAI_DMA +#ifdef CONFIG_STM32_SAI_DMA static int sai_dma_setup(struct stm32f7_sai_s *priv) { struct sai_buffer_s *bfcontainer; @@ -878,7 +878,7 @@ static int sai_dma_setup(struct stm32f7_sai_s *priv) DEBUGASSERT(ntransfers > 0); - stm32_dmasetup(priv->dma, priv->base + STM32F7_SAI_DR_OFFSET, + stm32_dmasetup(priv->dma, priv->base + STM32_SAI_DR_OFFSET, samp, ntransfers, priv->dma_ccr); /* Add the container to the list of active DMAs */ @@ -891,7 +891,7 @@ static int sai_dma_setup(struct stm32f7_sai_s *priv) /* Enable the transmitter */ - sai_modifyreg(priv, STM32F7_SAI_CR1_OFFSET, 0, SAI_CR1_SAIEN); + sai_modifyreg(priv, STM32_SAI_CR1_OFFSET, 0, SAI_CR1_SAIEN); /* Start a watchdog to catch DMA timeouts */ @@ -959,7 +959,7 @@ static void sai_worker(void *arg) */ flags = enter_critical_section(); -#ifdef CONFIG_STM32F7_SAI_DMA +#ifdef CONFIG_STM32_SAI_DMA sai_dma_setup(priv); #endif leave_critical_section(flags); @@ -1071,7 +1071,7 @@ static void sai_schedule(struct stm32f7_sai_s *priv, int result) * ****************************************************************************/ -#ifdef CONFIG_STM32F7_SAI_DMA +#ifdef CONFIG_STM32_SAI_DMA static void sai_dma_callback(DMA_HANDLE handle, uint8_t isr, void *arg) { struct stm32f7_sai_s *priv = (struct stm32f7_sai_s *)arg; @@ -1169,9 +1169,9 @@ static uint32_t sai_datawidth(struct i2s_dev_s *dev, int bits) return 0; } - sai_modifyreg(priv, STM32F7_SAI_CR1_OFFSET, SAI_CR1_DS_MASK, setbits); + sai_modifyreg(priv, STM32_SAI_CR1_OFFSET, SAI_CR1_DS_MASK, setbits); - sai_modifyreg(priv, STM32F7_SAI_FRCR_OFFSET, + sai_modifyreg(priv, STM32_SAI_FRCR_OFFSET, SAI_FRCR_FSALL_MASK | SAI_FRCR_FRL_MASK, SAI_FRCR_FSALL(bits) | SAI_FRCR_FRL(bits * 2)); @@ -1244,7 +1244,7 @@ static int sai_receive(struct i2s_dev_s *dev, struct ap_buffer_s *apb, } mode = priv->syncen ? SAI_CR1_MODE_SLAVE_RX : SAI_CR1_MODE_MASTER_RX; - sai_modifyreg(priv, STM32F7_SAI_CR1_OFFSET, SAI_CR1_MODE_MASK, mode); + sai_modifyreg(priv, STM32_SAI_CR1_OFFSET, SAI_CR1_MODE_MASK, mode); priv->rxenab = true; /* Add a reference to the audio buffer */ @@ -1268,7 +1268,7 @@ static int sai_receive(struct i2s_dev_s *dev, struct ap_buffer_s *apb, * progress, then this will do nothing. */ -#ifdef CONFIG_STM32F7_SAI_DMA +#ifdef CONFIG_STM32_SAI_DMA ret = sai_dma_setup(priv); #endif DEBUGASSERT(ret == OK); @@ -1344,7 +1344,7 @@ static int sai_send(struct i2s_dev_s *dev, struct ap_buffer_s *apb, } mode = priv->syncen ? SAI_CR1_MODE_SLAVE_TX : SAI_CR1_MODE_MASTER_TX; - sai_modifyreg(priv, STM32F7_SAI_CR1_OFFSET, SAI_CR1_MODE_MASK, mode); + sai_modifyreg(priv, STM32_SAI_CR1_OFFSET, SAI_CR1_MODE_MASK, mode); priv->txenab = true; /* Add a reference to the audio buffer */ @@ -1368,7 +1368,7 @@ static int sai_send(struct i2s_dev_s *dev, struct ap_buffer_s *apb, * progress, then this will do nothing. */ -#ifdef CONFIG_STM32F7_SAI_DMA +#ifdef CONFIG_STM32_SAI_DMA ret = sai_dma_setup(priv); #endif DEBUGASSERT(ret == OK); @@ -1485,7 +1485,7 @@ static void sai_buf_initialize(struct stm32f7_sai_s *priv) int i; priv->freelist = NULL; - for (i = 0; i < CONFIG_STM32F7_SAI_MAXINFLIGHT; i++) + for (i = 0; i < CONFIG_STM32_SAI_MAXINFLIGHT; i++) { sai_buf_free(priv, &priv->containers[i]); } @@ -1520,36 +1520,36 @@ static void sai_portinitialize(struct stm32f7_sai_s *priv) /* Configure the data width */ sai_datawidth((struct i2s_dev_s *)priv, - CONFIG_STM32F7_SAI_DEFAULT_DATALEN); + CONFIG_STM32_SAI_DEFAULT_DATALEN); -#ifdef CONFIG_STM32F7_SAI_DMA +#ifdef CONFIG_STM32_SAI_DMA /* Get DMA channel */ priv->dma = stm32_dmachannel(priv->dma_ch); DEBUGASSERT(priv->dma); - sai_modifyreg(priv, STM32F7_SAI_CR1_OFFSET, 0, SAI_CR1_DMAEN); + sai_modifyreg(priv, STM32_SAI_CR1_OFFSET, 0, SAI_CR1_DMAEN); #endif - sai_modifyreg(priv, STM32F7_SAI_CR1_OFFSET, SAI_CR1_SYNCEN_MASK, + sai_modifyreg(priv, STM32_SAI_CR1_OFFSET, SAI_CR1_SYNCEN_MASK, priv->syncen); - sai_modifyreg(priv, STM32F7_SAI_CR1_OFFSET, 0, SAI_CR1_OUTDRIV); + sai_modifyreg(priv, STM32_SAI_CR1_OFFSET, 0, SAI_CR1_OUTDRIV); - sai_modifyreg(priv, STM32F7_SAI_CR2_OFFSET, SAI_CR2_FTH_MASK, + sai_modifyreg(priv, STM32_SAI_CR2_OFFSET, SAI_CR2_FTH_MASK, SAI_CR2_FTH_1QF); - sai_modifyreg(priv, STM32F7_SAI_FRCR_OFFSET, + sai_modifyreg(priv, STM32_SAI_FRCR_OFFSET, SAI_FRCR_FSDEF | SAI_FRCR_FSPOL | SAI_FRCR_FSOFF, SAI_FRCR_FSDEF_CHID | SAI_FRCR_FSPOL_LOW | SAI_FRCR_FSOFF_BFB); - sai_modifyreg(priv, STM32F7_SAI_SLOTR_OFFSET, + sai_modifyreg(priv, STM32_SAI_SLOTR_OFFSET, SAI_SLOTR_NBSLOT_MASK | SAI_SLOTR_SLOTEN_MASK, SAI_SLOTR_NBSLOT(2) | SAI_SLOTR_SLOTEN_0 | SAI_SLOTR_SLOTEN_1); - sai_modifyreg(priv, STM32F7_SAI_CR1_OFFSET, 0, SAI_CR1_SAIEN); + sai_modifyreg(priv, STM32_SAI_CR1_OFFSET, 0, SAI_CR1_SAIEN); sai_dump_regs(priv, "After initialization"); } @@ -1581,7 +1581,7 @@ struct i2s_dev_s *stm32_sai_initialize(int intf, switch (intf) { -#ifdef CONFIG_STM32F7_SAI1_A +#ifdef CONFIG_STM32_SAI1_A case SAI1_BLOCK_A: { i2sinfo("SAI1 Block A Selected\n"); @@ -1589,7 +1589,7 @@ struct i2s_dev_s *stm32_sai_initialize(int intf, priv->sampleratecb = sampleratecb; stm32_configgpio(GPIO_SAI1_SD_A); -# ifndef CONFIG_STM32F7_SAI1_A_SYNC_WITH_B +# ifndef CONFIG_STM32_SAI1_A_SYNC_WITH_B stm32_configgpio(GPIO_SAI1_FS_A); stm32_configgpio(GPIO_SAI1_SCK_A); stm32_configgpio(GPIO_SAI1_MCLK_A); @@ -1598,7 +1598,7 @@ struct i2s_dev_s *stm32_sai_initialize(int intf, } #endif -#ifdef CONFIG_STM32F7_SAI1_B +#ifdef CONFIG_STM32_SAI1_B case SAI1_BLOCK_B: { i2sinfo("SAI1 Block B Selected\n"); @@ -1606,7 +1606,7 @@ struct i2s_dev_s *stm32_sai_initialize(int intf, priv->sampleratecb = sampleratecb; stm32_configgpio(GPIO_SAI1_SD_B); -# ifndef CONFIG_STM32F7_SAI1_B_SYNC_WITH_A +# ifndef CONFIG_STM32_SAI1_B_SYNC_WITH_A stm32_configgpio(GPIO_SAI1_FS_B); stm32_configgpio(GPIO_SAI1_SCK_B); stm32_configgpio(GPIO_SAI1_MCLK_B); @@ -1615,7 +1615,7 @@ struct i2s_dev_s *stm32_sai_initialize(int intf, } #endif -#ifdef CONFIG_STM32F7_SAI2_A +#ifdef CONFIG_STM32_SAI2_A case SAI2_BLOCK_A: { i2sinfo("SAI2 Block A Selected\n"); @@ -1623,7 +1623,7 @@ struct i2s_dev_s *stm32_sai_initialize(int intf, priv->sampleratecb = sampleratecb; stm32_configgpio(GPIO_SAI2_SD_A); -# ifndef CONFIG_STM32F7_SAI2_A_SYNC_WITH_B +# ifndef CONFIG_STM32_SAI2_A_SYNC_WITH_B stm32_configgpio(GPIO_SAI2_FS_A); stm32_configgpio(GPIO_SAI2_SCK_A); stm32_configgpio(GPIO_SAI2_MCLK_A); @@ -1632,7 +1632,7 @@ struct i2s_dev_s *stm32_sai_initialize(int intf, } #endif -#ifdef CONFIG_STM32F7_SAI2_B +#ifdef CONFIG_STM32_SAI2_B case SAI2_BLOCK_B: { i2sinfo("SAI2 Block B Selected\n"); @@ -1640,7 +1640,7 @@ struct i2s_dev_s *stm32_sai_initialize(int intf, priv->sampleratecb = sampleratecb; stm32_configgpio(GPIO_SAI2_SD_B); -# ifndef CONFIG_STM32F7_SAI2_B_SYNC_WITH_A +# ifndef CONFIG_STM32_SAI2_B_SYNC_WITH_A stm32_configgpio(GPIO_SAI2_FS_B); stm32_configgpio(GPIO_SAI2_SCK_B); stm32_configgpio(GPIO_SAI2_MCLK_B); diff --git a/arch/arm/src/stm32f7/stm32_sdmmc.c b/arch/arm/src/stm32f7/stm32_sdmmc.c index 1bf6eac7bafbf..d82877095a158 100644 --- a/arch/arm/src/stm32f7/stm32_sdmmc.c +++ b/arch/arm/src/stm32f7/stm32_sdmmc.c @@ -53,7 +53,7 @@ #include "stm32_rcc.h" #include "stm32_sdmmc.h" -#if defined(CONFIG_STM32F7_SDMMC1) || defined(CONFIG_STM32F7_SDMMC2) +#if defined(CONFIG_STM32_SDMMC1) || defined(CONFIG_STM32_SDMMC2) /**************************************************************************** * Pre-processor Definitions @@ -65,7 +65,7 @@ * * CONFIG_ARCH_DMA - Enable architecture-specific DMA subsystem * initialization. Required if CONFIG_SDMMC[1|2]_DMA is enabled. - * CONFIG_STM32F7_DMA2 - Enable STM32 DMA2 support. Required if + * CONFIG_STM32_DMA2 - Enable STM32 DMA2 support. Required if * CONFIG_SDMMC[1|2]_DMA is enabled * CONFIG_SCHED_WORKQUEUE -- Callback support requires work queue support. * @@ -74,15 +74,15 @@ * CONFIG_SDIO_MUXBUS - Setting this configuration enables some locking * APIs to manage concurrent accesses on the SDMMC bus. This is not * needed for the simple case of a single SD card, for example. - * CONFIG_STM32F7_SDMMC_DMA - Enable SDMMC. This is a marginally optional. + * CONFIG_STM32_SDMMC_DMA - Enable SDMMC. This is a marginally optional. * For most usages, SDMMC will cause data overruns if used without DMA. * NOTE the above system DMA configuration options. * CONFIG_SDMMC1/2_WIDTH_D1_ONLY - This may be selected to force the driver * operate with only a single data line (the default is to use all * 4 SD data lines). * CONFIG_SDMMC_DMAPRIO - SDMMC DMA priority. This can be selected if - * CONFIG_STM32F7_SDMMC_DMA is enabled. - * CONFIG_STM32F7_SDMMC_XFRDEBUG - Enables some very low-level debug + * CONFIG_STM32_SDMMC_DMA is enabled. + * CONFIG_STM32_SDMMC_XFRDEBUG - Enables some very low-level debug * output. This also requires CONFIG_DEBUG_FS and CONFIG_DEBUG_INFO * * CONFIG_SDMMC1/2_SDIO_MODE @@ -100,20 +100,20 @@ * hence, if only SDMMC2 is defined it will be slot 0. */ -#if !defined(CONFIG_STM32F7_SDMMC1) +#if !defined(CONFIG_STM32_SDMMC1) # define SDMMC2_SLOT 0 #else # define SDMMC2_SLOT 1 #endif -#ifndef CONFIG_STM32F7_SDMMC_DMA +#ifndef CONFIG_STM32_SDMMC_DMA # warning "Large Non-DMA transfer may result in RX overrun failures" #else -# ifndef CONFIG_STM32F7_DMA2 -# error "CONFIG_STM32F7_SDMMC_DMA support requires CONFIG_STM32F7_DMA2" +# ifndef CONFIG_STM32_DMA2 +# error "CONFIG_STM32_SDMMC_DMA support requires CONFIG_STM32_DMA2" # endif # ifndef CONFIG_SDIO_DMA -# error CONFIG_SDIO_DMA must be defined with CONFIG_STM32F7_SDMMC_DMA +# error CONFIG_SDIO_DMA must be defined with CONFIG_STM32_SDMMC_DMA # endif #endif @@ -121,16 +121,16 @@ # error "Callback support requires CONFIG_SCHED_WORKQUEUE and CONFIG_SCHED_HPWORK" #endif -#ifdef CONFIG_STM32F7_SDMMC1 -# ifdef CONFIG_STM32F7_SDMMC_DMA -# ifndef CONFIG_STM32F7_SDMMC1_DMAPRIO -# define CONFIG_STM32F7_SDMMC1_DMAPRIO DMA_SCR_PRIVERYHI +#ifdef CONFIG_STM32_SDMMC1 +# ifdef CONFIG_STM32_SDMMC_DMA +# ifndef CONFIG_STM32_SDMMC1_DMAPRIO +# define CONFIG_STM32_SDMMC1_DMAPRIO DMA_SCR_PRIVERYHI # endif -# if (CONFIG_STM32F7_SDMMC1_DMAPRIO & ~DMA_SCR_PL_MASK) != 0 -# error "Illegal value for CONFIG_STM32F7_SDMMC1_DMAPRIO" +# if (CONFIG_STM32_SDMMC1_DMAPRIO & ~DMA_SCR_PL_MASK) != 0 +# error "Illegal value for CONFIG_STM32_SDMMC1_DMAPRIO" # endif # else -# undef CONFIG_STM32F7_SDMMC1_DMAPRIO +# undef CONFIG_STM32_SDMMC1_DMAPRIO # endif # if STM32_RCC_DCKCFGR2_SDMMCSRC == RCC_DCKCFGR2_SDMMCSEL_48MHZ # define STM32_SDMMC1_CLK UINT32_C(48000000) @@ -139,16 +139,16 @@ # endif #endif -#ifdef CONFIG_STM32F7_SDMMC2 -# ifdef CONFIG_STM32F7_SDMMC_DMA -# ifndef CONFIG_STM32F7_SDMMC2_DMAPRIO -# define CONFIG_STM32F7_SDMMC2_DMAPRIO DMA_SCR_PRIVERYHI +#ifdef CONFIG_STM32_SDMMC2 +# ifdef CONFIG_STM32_SDMMC_DMA +# ifndef CONFIG_STM32_SDMMC2_DMAPRIO +# define CONFIG_STM32_SDMMC2_DMAPRIO DMA_SCR_PRIVERYHI # endif -# if (CONFIG_STM32F7_SDMMC2_DMAPRIO & ~DMA_SCR_PL_MASK) != 0 -# error "Illegal value for CONFIG_STM32F7_SDMMC2_DMAPRIO" +# if (CONFIG_STM32_SDMMC2_DMAPRIO & ~DMA_SCR_PL_MASK) != 0 +# error "Illegal value for CONFIG_STM32_SDMMC2_DMAPRIO" # endif # else -# undef CONFIG_STM32F7_SDMMC2_DMAPRIO +# undef CONFIG_STM32_SDMMC2_DMAPRIO # endif # if STM32_RCC_DCKCFGR2_SDMMCSRC == RCC_DCKCFGR2_SDMMCSEL_48MHZ # define STM32_SDMMC2_CLK UINT32_C(48000000) @@ -163,7 +163,7 @@ #endif #if !defined(CONFIG_DEBUG_FS) || !defined(CONFIG_DEBUG_FEATURES) -# undef CONFIG_STM32F7_SDMMC_XFRDEBUG +# undef CONFIG_STM32_SDMMC_XFRDEBUG #endif #ifdef CONFIG_SDMMC1_SDIO_PULLUP @@ -345,8 +345,8 @@ /* Register logging support */ -#ifdef CONFIG_STM32F7_SDMMC_XFRDEBUG -# ifdef CONFIG_STM32F7_SDMMC_DMA +#ifdef CONFIG_STM32_SDMMC_XFRDEBUG +# ifdef CONFIG_STM32_SDMMC_DMA # define SAMPLENDX_BEFORE_SETUP 0 # define SAMPLENDX_BEFORE_ENABLE 1 # define SAMPLENDX_AFTER_SETUP 2 @@ -379,7 +379,7 @@ struct stm32_dev_s #ifdef CONFIG_MMCSD_SDIOWAIT_WRCOMPLETE uint32_t d0_gpio; #endif -#ifdef CONFIG_STM32F7_SDMMC_DMA +#ifdef CONFIG_STM32_SDMMC_DMA uint32_t dmapri; #endif @@ -409,7 +409,7 @@ struct stm32_dev_s bool widebus; /* Required for DMA support */ bool onebit; /* true: Only 1-bit transfers are supported */ -#ifdef CONFIG_STM32F7_SDMMC_DMA +#ifdef CONFIG_STM32_SDMMC_DMA volatile uint8_t xfrflags; /* Used to synchronize SDMMC and DMA completion events */ bool dmamode; /* true: DMA mode transfer */ DMA_HANDLE dma; /* Handle for DMA channel */ @@ -433,7 +433,7 @@ struct stm32_dev_s /* Register logging support */ -#ifdef CONFIG_STM32F7_SDMMC_XFRDEBUG +#ifdef CONFIG_STM32_SDMMC_XFRDEBUG struct stm32_sdioregs_s { uint8_t power; @@ -450,7 +450,7 @@ struct stm32_sdioregs_s struct stm32_sampleregs_s { struct stm32_sdioregs_s sdio; -#if defined(CONFIG_DEBUG_DMA_INFO) && defined(CONFIG_STM32F7_SDMMC_DMA) +#if defined(CONFIG_DEBUG_DMA_INFO) && defined(CONFIG_STM32_SDMMC_DMA) struct stm32_dmaregs_s dma; #endif }; @@ -473,7 +473,7 @@ static void stm32_setpwrctrl(struct stm32_dev_s *priv, uint32_t pwrctrl); /* DMA Helpers **************************************************************/ -#ifdef CONFIG_STM32F7_SDMMC_XFRDEBUG +#ifdef CONFIG_STM32_SDMMC_XFRDEBUG static void stm32_sampleinit(void); static void stm32_sdiosample(struct stm32_dev_s *priv, struct stm32_sdioregs_s *regs); @@ -488,7 +488,7 @@ static void stm32_dumpsamples(struct stm32_dev_s *priv); # define stm32_dumpsamples(priv) #endif -#ifdef CONFIG_STM32F7_SDMMC_DMA +#ifdef CONFIG_STM32_SDMMC_DMA static void stm32_dmacallback(DMA_HANDLE handle, uint8_t status, void *arg); #endif @@ -563,7 +563,7 @@ static int stm32_registercallback(struct sdio_dev_s *dev, /* DMA */ -#ifdef CONFIG_STM32F7_SDMMC_DMA +#ifdef CONFIG_STM32_SDMMC_DMA #ifdef CONFIG_ARCH_HAVE_SDIO_PREFLIGHT static int stm32_dmapreflight(struct sdio_dev_s *dev, const uint8_t *buffer, size_t buflen); @@ -572,7 +572,7 @@ static int stm32_dmarecvsetup(struct sdio_dev_s *dev, uint8_t *buffer, size_t buflen); static int stm32_dmasendsetup(struct sdio_dev_s *dev, const uint8_t *buffer, size_t buflen); -#endif /* CONFIG_STM32F7_SDMMC_DMA */ +#endif /* CONFIG_STM32_SDMMC_DMA */ /* Initialization/uninitialization/reset ************************************/ @@ -583,7 +583,7 @@ static void stm32_default(struct stm32_dev_s *priv); * Private Data ****************************************************************************/ -#ifdef CONFIG_STM32F7_SDMMC1 +#ifdef CONFIG_STM32_SDMMC1 struct stm32_dev_s g_sdmmcdev1 = { .dev = @@ -615,7 +615,7 @@ struct stm32_dev_s g_sdmmcdev1 = .callbackenable = stm32_callbackenable, .registercallback = stm32_registercallback, #ifdef CONFIG_SDIO_DMA -#ifdef CONFIG_STM32F7_SDMMC_DMA +#ifdef CONFIG_STM32_SDMMC_DMA #ifdef CONFIG_ARCH_HAVE_SDIO_PREFLIGHT .dmapreflight = stm32_dmapreflight, #endif @@ -627,7 +627,7 @@ struct stm32_dev_s g_sdmmcdev1 = #endif .dmarecvsetup = stm32_recvsetup, .dmasendsetup = stm32_sendsetup, -#endif /* CONFIG_STM32F7_SDMMC_DMA */ +#endif /* CONFIG_STM32_SDMMC_DMA */ #endif /* CONFIG_SDIO_DMA*/ }, .base = STM32_SDMMC1_BASE, @@ -636,8 +636,8 @@ struct stm32_dev_s g_sdmmcdev1 = #ifdef CONFIG_MMCSD_SDIOWAIT_WRCOMPLETE .d0_gpio = SDMMC1_SDIO_PULL(GPIO_SDMMC1_D0), #endif -#ifdef CONFIG_STM32F7_SDMMC1_DMAPRIO - .dmapri = CONFIG_STM32F7_SDMMC1_DMAPRIO, +#ifdef CONFIG_STM32_SDMMC1_DMAPRIO + .dmapri = CONFIG_STM32_SDMMC1_DMAPRIO, #endif .waitsem = SEM_INITIALIZER(0), #ifdef HAVE_SDMMC_SDIO_MODE @@ -651,7 +651,7 @@ struct stm32_dev_s g_sdmmcdev1 = }; #endif -#ifdef CONFIG_STM32F7_SDMMC2 +#ifdef CONFIG_STM32_SDMMC2 struct stm32_dev_s g_sdmmcdev2 = { .dev = @@ -696,8 +696,8 @@ struct stm32_dev_s g_sdmmcdev2 = #ifdef CONFIG_MMCSD_SDIOWAIT_WRCOMPLETE .d0_gpio = SDMMC2_SDIO_PULL(GPIO_SDMMC2_D0), #endif -#ifdef CONFIG_STM32F7_SDMMC2_DMAPRIO - .dmapri = CONFIG_STM32F7_SDMMC2_DMAPRIO, +#ifdef CONFIG_STM32_SDMMC2_DMAPRIO + .dmapri = CONFIG_STM32_SDMMC2_DMAPRIO, #endif .waitsem = SEM_INITIALIZER(0), #ifdef HAVE_SDMMC_SDIO_MODE @@ -712,7 +712,7 @@ struct stm32_dev_s g_sdmmcdev2 = #endif /* Register logging support */ -#ifdef CONFIG_STM32F7_SDMMC_XFRDEBUG +#ifdef CONFIG_STM32_SDMMC_XFRDEBUG static struct stm32_sampleregs_s g_sampleregs[DEBUG_NSAMPLES]; #endif @@ -859,7 +859,7 @@ static void stm32_configwaitints(struct stm32_dev_s *priv, uint32_t waitmask, priv->waitevents = waitevents; priv->wkupevent = wkupevent; priv->waitmask = waitmask; -#ifdef CONFIG_STM32F7_SDMMC_DMA +#ifdef CONFIG_STM32_SDMMC_DMA priv->xfrflags = 0; #endif @@ -952,7 +952,7 @@ static void stm32_setpwrctrl(struct stm32_dev_s *priv, uint32_t pwrctrl) * ****************************************************************************/ -#ifdef CONFIG_STM32F7_SDMMC_XFRDEBUG +#ifdef CONFIG_STM32_SDMMC_XFRDEBUG static void stm32_sampleinit(void) { memset(g_sampleregs, 0xff, DEBUG_NSAMPLES * @@ -968,7 +968,7 @@ static void stm32_sampleinit(void) * ****************************************************************************/ -#ifdef CONFIG_STM32F7_SDMMC_XFRDEBUG +#ifdef CONFIG_STM32_SDMMC_XFRDEBUG static void stm32_sdiosample(struct stm32_dev_s *priv, struct stm32_sdioregs_s *regs) { @@ -992,12 +992,12 @@ static void stm32_sdiosample(struct stm32_dev_s *priv, * ****************************************************************************/ -#ifdef CONFIG_STM32F7_SDMMC_XFRDEBUG +#ifdef CONFIG_STM32_SDMMC_XFRDEBUG static void stm32_sample(struct stm32_dev_s *priv, int index) { struct stm32_sampleregs_s *regs = &g_sampleregs[index]; -#if defined(CONFIG_DEBUG_DMA_INFO) && defined(CONFIG_STM32F7_SDMMC_DMA) +#if defined(CONFIG_DEBUG_DMA_INFO) && defined(CONFIG_STM32_SDMMC_DMA) if (priv->dmamode) { stm32_dmasample(priv->dma, ®s->dma); @@ -1016,7 +1016,7 @@ static void stm32_sample(struct stm32_dev_s *priv, int index) * ****************************************************************************/ -#ifdef CONFIG_STM32F7_SDMMC_XFRDEBUG +#ifdef CONFIG_STM32_SDMMC_XFRDEBUG static void stm32_sdiodump(struct stm32_sdioregs_s *regs, const char *msg) { mcinfo("SDIO Registers: %s\n", msg); @@ -1046,12 +1046,12 @@ static void stm32_sdiodump(struct stm32_sdioregs_s *regs, const char *msg) * ****************************************************************************/ -#ifdef CONFIG_STM32F7_SDMMC_XFRDEBUG +#ifdef CONFIG_STM32_SDMMC_XFRDEBUG static void stm32_dumpsample(struct stm32_dev_s *priv, struct stm32_sampleregs_s *regs, const char *msg) { -#if defined(CONFIG_DEBUG_DMA_INFO) && defined(CONFIG_STM32F7_SDMMC_DMA) +#if defined(CONFIG_DEBUG_DMA_INFO) && defined(CONFIG_STM32_SDMMC_DMA) if (priv->dmamode) { stm32_dmadump(priv->dma, ®s->dma, msg); @@ -1070,13 +1070,13 @@ static void stm32_dumpsample(struct stm32_dev_s *priv, * ****************************************************************************/ -#ifdef CONFIG_STM32F7_SDMMC_XFRDEBUG +#ifdef CONFIG_STM32_SDMMC_XFRDEBUG static void stm32_dumpsamples(struct stm32_dev_s *priv) { stm32_dumpsample(priv, &g_sampleregs[SAMPLENDX_BEFORE_SETUP], "Before setup"); -#if defined(CONFIG_DEBUG_DMA_INFO) && defined(CONFIG_STM32F7_SDMMC_DMA) +#if defined(CONFIG_DEBUG_DMA_INFO) && defined(CONFIG_STM32_SDMMC_DMA) if (priv->dmamode) { stm32_dumpsample(priv, &g_sampleregs[SAMPLENDX_BEFORE_ENABLE], @@ -1089,7 +1089,7 @@ static void stm32_dumpsamples(struct stm32_dev_s *priv) stm32_dumpsample(priv, &g_sampleregs[SAMPLENDX_END_TRANSFER], "End of transfer"); -#if defined(CONFIG_DEBUG_DMA_INFO) && defined(CONFIG_STM32F7_SDMMC_DMA) +#if defined(CONFIG_DEBUG_DMA_INFO) && defined(CONFIG_STM32_SDMMC_DMA) if (priv->dmamode) { stm32_dumpsample(priv, &g_sampleregs[SAMPLENDX_DMA_CALLBACK], @@ -1107,7 +1107,7 @@ static void stm32_dumpsamples(struct stm32_dev_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32F7_SDMMC_DMA +#ifdef CONFIG_STM32_SDMMC_DMA static void stm32_dmacallback(DMA_HANDLE handle, uint8_t status, void *arg) { struct stm32_dev_s *priv = (struct stm32_dev_s *)arg; @@ -1515,7 +1515,7 @@ static void stm32_endtransfer(struct stm32_dev_s *priv, /* If this was a DMA transfer, make sure that DMA is stopped */ -#ifdef CONFIG_STM32F7_SDMMC_DMA +#ifdef CONFIG_STM32_SDMMC_DMA if (priv->dmamode) { /* DMA debug instrumentation */ @@ -1625,7 +1625,7 @@ static int stm32_sdmmc_interrupt(int irq, void *context, void *arg) pending = enabled & priv->xfrmask; if (pending != 0) { -#ifdef CONFIG_STM32F7_SDMMC_DMA +#ifdef CONFIG_STM32_SDMMC_DMA if (!priv->dmamode) #endif { @@ -1664,7 +1664,7 @@ static int stm32_sdmmc_interrupt(int irq, void *context, void *arg) /* Was this transfer performed in DMA mode? */ -#ifdef CONFIG_STM32F7_SDMMC_DMA +#ifdef CONFIG_STM32_SDMMC_DMA if (priv->dmamode) { /* Yes.. Terminate the transfers only if the DMA has also @@ -1884,7 +1884,7 @@ static void stm32_reset(struct sdio_dev_s *dev) priv->waitevents = 0; /* Set of events to be waited for */ priv->waitmask = 0; /* Interrupt enables for event waiting */ priv->wkupevent = 0; /* The event that caused the wakeup */ -#ifdef CONFIG_STM32F7_SDMMC_DMA +#ifdef CONFIG_STM32_SDMMC_DMA priv->xfrflags = 0; /* Used to synchronize SDIO and DMA * completion events */ #endif @@ -1903,7 +1903,7 @@ static void stm32_reset(struct sdio_dev_s *dev) /* DMA data transfer support */ priv->widebus = false; /* Required for DMA support */ -#ifdef CONFIG_STM32F7_SDMMC_DMA +#ifdef CONFIG_STM32_SDMMC_DMA priv->dmamode = false; /* true: DMA mode transfer */ priv->rxbuffer = 0; priv->rxend = 0; @@ -1944,7 +1944,7 @@ static sdio_capset_t stm32_capabilities(struct sdio_dev_s *dev) caps |= SDIO_CAPS_1BIT_ONLY; } -#ifdef CONFIG_STM32F7_SDMMC_DMA +#ifdef CONFIG_STM32_SDMMC_DMA caps |= SDIO_CAPS_DMASUPPORTED; #endif @@ -2241,7 +2241,7 @@ static int stm32_recvsetup(struct sdio_dev_s *dev, uint8_t *buffer, priv->buffer = (uint32_t *)buffer; priv->remaining = nbytes; -#ifdef CONFIG_STM32F7_SDMMC_DMA +#ifdef CONFIG_STM32_SDMMC_DMA priv->dmamode = false; priv->rxbuffer = 0; #endif @@ -2298,7 +2298,7 @@ static int stm32_sendsetup(struct sdio_dev_s *dev, const priv->buffer = (uint32_t *)buffer; priv->remaining = nbytes; -#ifdef CONFIG_STM32F7_SDMMC_DMA +#ifdef CONFIG_STM32_SDMMC_DMA priv->dmamode = false; priv->rxbuffer = 0; #endif @@ -2354,7 +2354,7 @@ static int stm32_cancel(struct sdio_dev_s *dev) /* If this was a DMA transfer, make sure that DMA is stopped */ -#ifdef CONFIG_STM32F7_SDMMC_DMA +#ifdef CONFIG_STM32_SDMMC_DMA if (priv->dmamode) { /* Make sure that the DMA is stopped (it will be stopped automatically @@ -2871,7 +2871,7 @@ static sdio_eventset_t stm32_eventwait(struct sdio_dev_s *dev) errout_with_waitints: stm32_configwaitints(priv, 0, 0, 0); -#ifdef CONFIG_STM32F7_SDMMC_DMA +#ifdef CONFIG_STM32_SDMMC_DMA priv->xfrflags = 0; #endif @@ -2968,11 +2968,11 @@ static int stm32_registercallback(struct sdio_dev_s *dev, * OK on success; a negated errno on failure ****************************************************************************/ -#if defined(CONFIG_STM32F7_SDMMC_DMA) && defined(CONFIG_ARCH_HAVE_SDIO_PREFLIGHT) +#if defined(CONFIG_STM32_SDMMC_DMA) && defined(CONFIG_ARCH_HAVE_SDIO_PREFLIGHT) static int stm32_dmapreflight(struct sdio_dev_s *dev, const uint8_t *buffer, size_t buflen) { -#ifdef CONFIG_STM32F7_DMACAPABLE +#ifdef CONFIG_STM32_DMACAPABLE struct stm32_dev_s *priv = (struct stm32_dev_s *)dev; DEBUGASSERT(priv != NULL && buffer != NULL && buflen > 0); @@ -3009,7 +3009,7 @@ static int stm32_dmapreflight(struct sdio_dev_s *dev, * ****************************************************************************/ -#ifdef CONFIG_STM32F7_SDMMC_DMA +#ifdef CONFIG_STM32_SDMMC_DMA static int stm32_dmarecvsetup(struct sdio_dev_s *dev, uint8_t *buffer, size_t buflen) { @@ -3112,7 +3112,7 @@ static int stm32_dmarecvsetup(struct sdio_dev_s *dev, * ****************************************************************************/ -#ifdef CONFIG_STM32F7_SDMMC_DMA +#ifdef CONFIG_STM32_SDMMC_DMA static int stm32_dmasendsetup(struct sdio_dev_s *dev, const uint8_t *buffer, size_t buflen) { @@ -3315,18 +3315,18 @@ static void stm32_default(struct stm32_dev_s *priv) struct sdio_dev_s *sdio_initialize(int slotno) { struct stm32_dev_s *priv = NULL; -#ifdef CONFIG_STM32F7_SDMMC_DMA +#ifdef CONFIG_STM32_SDMMC_DMA unsigned int dmachan; #endif -#ifdef CONFIG_STM32F7_SDMMC1 +#ifdef CONFIG_STM32_SDMMC1 if (slotno == 0) { /* Select SDMMC 1 */ priv = &g_sdmmcdev1; -# ifdef CONFIG_STM32F7_SDMMC_DMA +# ifdef CONFIG_STM32_SDMMC_DMA dmachan = SDMMC1_DMACHAN; # endif @@ -3356,14 +3356,14 @@ struct sdio_dev_s *sdio_initialize(int slotno) } else #endif -#ifdef CONFIG_STM32F7_SDMMC2 +#ifdef CONFIG_STM32_SDMMC2 if (slotno == SDMMC2_SLOT) { /* Select SDMMC 2 */ priv = &g_sdmmcdev2; -# ifdef CONFIG_STM32F7_SDMMC_DMA +# ifdef CONFIG_STM32_SDMMC_DMA dmachan = SDMMC2_DMACHAN; # endif @@ -3398,7 +3398,7 @@ struct sdio_dev_s *sdio_initialize(int slotno) return NULL; } -#ifdef CONFIG_STM32F7_SDMMC_DMA +#ifdef CONFIG_STM32_SDMMC_DMA /* Allocate a DMA channel */ priv->dma = stm32_dmachannel(dmachan); @@ -3499,7 +3499,7 @@ void sdio_wrprotect(struct sdio_dev_s *dev, bool wrprotect) mcinfo("cdstatus: %02x\n", priv->cdstatus); leave_critical_section(flags); } -#endif /* CONFIG_STM32F7_SDMMC1 || CONFIG_STM32F7_SDMMC2 */ +#endif /* CONFIG_STM32_SDMMC1 || CONFIG_STM32_SDMMC2 */ #ifdef HAVE_SDMMC_SDIO_MODE void sdio_set_sdio_card_isr(struct sdio_dev_s *dev, diff --git a/arch/arm/src/stm32f7/stm32_serial.c b/arch/arm/src/stm32f7/stm32_serial.c index dd5a10c0ee0b6..c73b64b0548ce 100644 --- a/arch/arm/src/stm32f7/stm32_serial.c +++ b/arch/arm/src/stm32f7/stm32_serial.c @@ -64,7 +64,7 @@ /* Total number of possible serial devices */ -#define STM32_NSERIAL (STM32F7_NUSART + STM32F7_NUART) +#define STM32_NSERIAL (STM32_NUSART + STM32_NUART) /* DMA configuration */ @@ -78,16 +78,16 @@ */ # if defined(CONFIG_USART1_RXDMA) || defined(CONFIG_USART6_RXDMA) -# ifndef CONFIG_STM32F7_DMA2 -# error STM32 USART1/6 receive DMA requires CONFIG_STM32F7_DMA2 +# ifndef CONFIG_STM32_DMA2 +# error STM32 USART1/6 receive DMA requires CONFIG_STM32_DMA2 # endif # endif # if defined(CONFIG_USART2_RXDMA) || defined(CONFIG_USART3_RXDMA) || \ defined(CONFIG_UART4_RXDMA) || defined(CONFIG_UART5_RXDMA) || \ defined(CONFIG_UART7_RXDMA) || defined(CONFIG_UART8_RXDMA) -# ifndef CONFIG_STM32F7_DMA1 -# error STM32 USART2/3/4/5/7/8 receive DMA requires CONFIG_STM32F7_DMA1 +# ifndef CONFIG_STM32_DMA1 +# error STM32 USART2/3/4/5/7/8 receive DMA requires CONFIG_STM32_DMA1 # endif # endif @@ -135,14 +135,14 @@ # define ARMV7M_DCACHE_LINESIZE 32 # endif -# if !defined(CONFIG_STM32F7_SERIAL_RXDMA_BUFFER_SIZE) || \ - (CONFIG_STM32F7_SERIAL_RXDMA_BUFFER_SIZE < ARMV7M_DCACHE_LINESIZE) -# undef CONFIG_STM32F7_SERIAL_RXDMA_BUFFER_SIZE -# define CONFIG_STM32F7_SERIAL_RXDMA_BUFFER_SIZE ARMV7M_DCACHE_LINESIZE +# if !defined(CONFIG_STM32_SERIAL_RXDMA_BUFFER_SIZE) || \ + (CONFIG_STM32_SERIAL_RXDMA_BUFFER_SIZE < ARMV7M_DCACHE_LINESIZE) +# undef CONFIG_STM32_SERIAL_RXDMA_BUFFER_SIZE +# define CONFIG_STM32_SERIAL_RXDMA_BUFFER_SIZE ARMV7M_DCACHE_LINESIZE # endif # define RXDMA_BUFFER_MASK (ARMV7M_DCACHE_LINESIZE - 1) -# define RXDMA_BUFFER_SIZE ((CONFIG_STM32F7_SERIAL_RXDMA_BUFFER_SIZE \ +# define RXDMA_BUFFER_SIZE ((CONFIG_STM32_SERIAL_RXDMA_BUFFER_SIZE \ + RXDMA_BUFFER_MASK) & ~RXDMA_BUFFER_MASK) /* DMA priority */ @@ -172,16 +172,16 @@ */ #if defined(CONFIG_USART1_TXDMA) || defined(CONFIG_USART6_TXDMA) -# ifndef CONFIG_STM32F7_DMA2 -# error STM32 USART1/6 transmit DMA requires CONFIG_STM32F7_DMA2 +# ifndef CONFIG_STM32_DMA2 +# error STM32 USART1/6 transmit DMA requires CONFIG_STM32_DMA2 # endif #endif #if defined(CONFIG_USART2_TXDMA) || defined(CONFIG_USART3_TXDMA) || \ defined(CONFIG_UART4_TXDMA) || defined(CONFIG_UART5_TXDMA) || \ defined(CONFIG_UART7_TXDMA) || defined(CONFIG_UART8_TXDMA) -# ifndef CONFIG_STM32F7_DMA1 -# error STM32 USART2/3/4/5/7/8 transmit DMA requires CONFIG_STM32F7_DMA1 +# ifndef CONFIG_STM32_DMA1 +# error STM32 USART2/3/4/5/7/8 transmit DMA requires CONFIG_STM32_DMA1 # endif #endif @@ -228,7 +228,7 @@ #endif #define TXDMA_BUFFER_MASK (ARMV7M_DCACHE_LINESIZE - 1) -#define TXDMA_BUFFER_SIZE ((CONFIG_STM32F7_SERIAL_RXDMA_BUFFER_SIZE \ +#define TXDMA_BUFFER_SIZE ((CONFIG_STM32_SERIAL_RXDMA_BUFFER_SIZE \ + RXDMA_BUFFER_MASK) & ~RXDMA_BUFFER_MASK) /* If built with CONFIG_ARMV7M_DCACHE Buffers need to be aligned and @@ -331,8 +331,8 @@ /* Power management definitions */ -#if defined(CONFIG_PM) && !defined(CONFIG_STM32F7_PM_SERIAL_ACTIVITY) -# define CONFIG_STM32F7_PM_SERIAL_ACTIVITY 10 +#if defined(CONFIG_PM) && !defined(CONFIG_STM32_PM_SERIAL_ACTIVITY) +# define CONFIG_STM32_PM_SERIAL_ACTIVITY 10 #endif /* Since RX DMA or TX DMA or both may be enabled for a given U[S]ART. @@ -354,7 +354,7 @@ * See up_restoreusartint where the masking is done. */ -#ifdef CONFIG_STM32F7_SERIALBRK_BSDCOMPAT +#ifdef CONFIG_STM32_SERIALBRK_BSDCOMPAT # define USART_CR1_IE_BREAK_INPROGRESS_SHFTS 15 # define USART_CR1_IE_BREAK_INPROGRESS (1 << USART_CR1_IE_BREAK_INPROGRESS_SHFTS) #endif @@ -364,13 +364,13 @@ /* Warnings for potentially unsafe configuration combinations. */ -#if defined(CONFIG_STM32F7_FLOWCONTROL_BROKEN) && \ +#if defined(CONFIG_STM32_FLOWCONTROL_BROKEN) && \ !defined(CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS) -# error "CONFIG_STM32F7_FLOWCONTROL_BROKEN requires \ +# error "CONFIG_STM32_FLOWCONTROL_BROKEN requires \ CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS to be enabled." #endif -#ifndef CONFIG_STM32F7_FLOWCONTROL_BROKEN +#ifndef CONFIG_STM32_FLOWCONTROL_BROKEN /* Combination of RXDMA + IFLOWCONTROL does not work as one might expect. * Since RXDMA uses circular DMA-buffer, DMA will always keep reading new * data from USART peripheral even if DMA buffer underruns. Thus this @@ -413,7 +413,7 @@ # warning "RXDMA and IFLOWCONTROL both enabled for UART8. \ This combination can lead to data loss." # endif -#endif /* CONFIG_STM32F7_FLOWCONTROL_BROKEN */ +#endif /* CONFIG_STM32_FLOWCONTROL_BROKEN */ /**************************************************************************** * Private Types @@ -720,49 +720,49 @@ static char g_uart8rxfifo[RXDMA_BUFFER_SIZE] /* Receive/Transmit buffers */ -#ifdef CONFIG_STM32F7_USART1 +#ifdef CONFIG_STM32_USART1 static char g_usart1rxbuffer[CONFIG_USART1_RXBUFSIZE]; static char g_usart1txbuffer[USART1_TXBUFSIZE_ADJUSTED] \ USART1_TXBUFSIZE_ALGN; #endif -#ifdef CONFIG_STM32F7_USART2 +#ifdef CONFIG_STM32_USART2 static char g_usart2rxbuffer[CONFIG_USART2_RXBUFSIZE]; static char g_usart2txbuffer[USART2_TXBUFSIZE_ADJUSTED] \ USART2_TXBUFSIZE_ALGN; #endif -#ifdef CONFIG_STM32F7_USART3 +#ifdef CONFIG_STM32_USART3 static char g_usart3rxbuffer[CONFIG_USART3_RXBUFSIZE]; static char g_usart3txbuffer[USART3_TXBUFSIZE_ADJUSTED] \ USART3_TXBUFSIZE_ALGN; #endif -#ifdef CONFIG_STM32F7_UART4 +#ifdef CONFIG_STM32_UART4 static char g_uart4rxbuffer[CONFIG_UART4_RXBUFSIZE]; static char g_uart4txbuffer[UART4_TXBUFSIZE_ADJUSTED] \ UART4_TXBUFSIZE_ALGN; #endif -#ifdef CONFIG_STM32F7_UART5 +#ifdef CONFIG_STM32_UART5 static char g_uart5rxbuffer[CONFIG_UART5_RXBUFSIZE]; static char g_uart5txbuffer[UART5_TXBUFSIZE_ADJUSTED] \ UART5_TXBUFSIZE_ALGN; #endif -#ifdef CONFIG_STM32F7_USART6 +#ifdef CONFIG_STM32_USART6 static char g_usart6rxbuffer[CONFIG_USART6_RXBUFSIZE]; static char g_usart6txbuffer[USART6_TXBUFSIZE_ADJUSTED] \ USART6_TXBUFSIZE_ALGN; #endif -#ifdef CONFIG_STM32F7_UART7 +#ifdef CONFIG_STM32_UART7 static char g_uart7rxbuffer[CONFIG_UART7_RXBUFSIZE]; static char g_uart7txbuffer[UART7_TXBUFSIZE_ADJUSTED] \ UART7_TXBUFSIZE_ALGN; #endif -#ifdef CONFIG_STM32F7_UART8 +#ifdef CONFIG_STM32_UART8 static char g_uart8rxbuffer[CONFIG_UART8_RXBUFSIZE]; static char g_uart8txbuffer[UART8_TXBUFSIZE_ADJUSTED] \ UART8_TXBUFSIZE_ALGN; @@ -770,7 +770,7 @@ static char g_uart8txbuffer[UART8_TXBUFSIZE_ADJUSTED] \ /* This describes the state of the STM32 USART1 ports. */ -#ifdef CONFIG_STM32F7_USART1 +#ifdef CONFIG_STM32_USART1 static struct up_dev_s g_usart1priv = { .dev = @@ -839,7 +839,7 @@ static struct up_dev_s g_usart1priv = /* This describes the state of the STM32 USART2 port. */ -#ifdef CONFIG_STM32F7_USART2 +#ifdef CONFIG_STM32_USART2 static struct up_dev_s g_usart2priv = { .dev = @@ -908,7 +908,7 @@ static struct up_dev_s g_usart2priv = /* This describes the state of the STM32 USART3 port. */ -#ifdef CONFIG_STM32F7_USART3 +#ifdef CONFIG_STM32_USART3 static struct up_dev_s g_usart3priv = { .dev = @@ -977,7 +977,7 @@ static struct up_dev_s g_usart3priv = /* This describes the state of the STM32 UART4 port. */ -#ifdef CONFIG_STM32F7_UART4 +#ifdef CONFIG_STM32_UART4 static struct up_dev_s g_uart4priv = { .dev = @@ -1046,7 +1046,7 @@ static struct up_dev_s g_uart4priv = /* This describes the state of the STM32 UART5 port. */ -#ifdef CONFIG_STM32F7_UART5 +#ifdef CONFIG_STM32_UART5 static struct up_dev_s g_uart5priv = { .dev = @@ -1115,7 +1115,7 @@ static struct up_dev_s g_uart5priv = /* This describes the state of the STM32 USART6 port. */ -#ifdef CONFIG_STM32F7_USART6 +#ifdef CONFIG_STM32_USART6 static struct up_dev_s g_usart6priv = { .dev = @@ -1184,7 +1184,7 @@ static struct up_dev_s g_usart6priv = /* This describes the state of the STM32 UART7 port. */ -#ifdef CONFIG_STM32F7_UART7 +#ifdef CONFIG_STM32_UART7 static struct up_dev_s g_uart7priv = { .dev = @@ -1253,7 +1253,7 @@ static struct up_dev_s g_uart7priv = /* This describes the state of the STM32 UART8 port. */ -#ifdef CONFIG_STM32F7_UART8 +#ifdef CONFIG_STM32_UART8 static struct up_dev_s g_uart8priv = { .dev = @@ -1324,28 +1324,28 @@ static struct up_dev_s g_uart8priv = static struct up_dev_s * const g_uart_devs[STM32_NSERIAL] = { -#ifdef CONFIG_STM32F7_USART1 +#ifdef CONFIG_STM32_USART1 [0] = &g_usart1priv, #endif -#ifdef CONFIG_STM32F7_USART2 +#ifdef CONFIG_STM32_USART2 [1] = &g_usart2priv, #endif -#ifdef CONFIG_STM32F7_USART3 +#ifdef CONFIG_STM32_USART3 [2] = &g_usart3priv, #endif -#ifdef CONFIG_STM32F7_UART4 +#ifdef CONFIG_STM32_UART4 [3] = &g_uart4priv, #endif -#ifdef CONFIG_STM32F7_UART5 +#ifdef CONFIG_STM32_UART5 [4] = &g_uart5priv, #endif -#ifdef CONFIG_STM32F7_USART6 +#ifdef CONFIG_STM32_USART6 [5] = &g_usart6priv, #endif -#ifdef CONFIG_STM32F7_UART7 +#ifdef CONFIG_STM32_UART7 [6] = &g_uart7priv, #endif -#ifdef CONFIG_STM32F7_UART8 +#ifdef CONFIG_STM32_UART8 [7] = &g_uart8priv, #endif }; @@ -1635,7 +1635,7 @@ static void up_set_format(struct uart_dev_s *dev) regval &= ~(USART_CR3_CTSE | USART_CR3_RTSE); #if defined(CONFIG_SERIAL_IFLOWCONTROL) && \ - !defined(CONFIG_STM32F7_FLOWCONTROL_BROKEN) + !defined(CONFIG_STM32_FLOWCONTROL_BROKEN) if (priv->iflow && (priv->rts_gpio != 0)) { regval |= USART_CR3_RTSE; @@ -1790,7 +1790,7 @@ static void up_pm_setsuspend(bool suspend) g_serialpm.serial_suspended = suspend; - for (n = 0; n < STM32F7_NUSART + STM32F7_NUART; n++) + for (n = 0; n < STM32_NUSART + STM32_NUART; n++) { struct up_dev_s *priv = g_uart_devs[n]; @@ -1828,49 +1828,49 @@ static void up_set_apb_clock(struct uart_dev_s *dev, bool on) { default: return; -#ifdef CONFIG_STM32F7_USART1 +#ifdef CONFIG_STM32_USART1 case STM32_USART1_BASE: rcc_en = RCC_APB2ENR_USART1EN; regaddr = STM32_RCC_APB2ENR; break; #endif -#ifdef CONFIG_STM32F7_USART2 +#ifdef CONFIG_STM32_USART2 case STM32_USART2_BASE: rcc_en = RCC_APB1ENR_USART2EN; regaddr = STM32_RCC_APB1ENR; break; #endif -#ifdef CONFIG_STM32F7_USART3 +#ifdef CONFIG_STM32_USART3 case STM32_USART3_BASE: rcc_en = RCC_APB1ENR_USART3EN; regaddr = STM32_RCC_APB1ENR; break; #endif -#ifdef CONFIG_STM32F7_UART4 +#ifdef CONFIG_STM32_UART4 case STM32_UART4_BASE: rcc_en = RCC_APB1ENR_UART4EN; regaddr = STM32_RCC_APB1ENR; break; #endif -#ifdef CONFIG_STM32F7_UART5 +#ifdef CONFIG_STM32_UART5 case STM32_UART5_BASE: rcc_en = RCC_APB1ENR_UART5EN; regaddr = STM32_RCC_APB1ENR; break; #endif -#ifdef CONFIG_STM32F7_USART6 +#ifdef CONFIG_STM32_USART6 case STM32_USART6_BASE: rcc_en = RCC_APB2ENR_USART6EN; regaddr = STM32_RCC_APB2ENR; break; #endif -#ifdef CONFIG_STM32F7_UART7 +#ifdef CONFIG_STM32_UART7 case STM32_UART7_BASE: rcc_en = RCC_APB1ENR_UART7EN; regaddr = STM32_RCC_APB1ENR; break; #endif -#ifdef CONFIG_STM32F7_UART8 +#ifdef CONFIG_STM32_UART8 case STM32_UART8_BASE: rcc_en = RCC_APB1ENR_UART8EN; regaddr = STM32_RCC_APB1ENR; @@ -1938,7 +1938,7 @@ static int up_setup(struct uart_dev_s *dev) { uint32_t config = priv->rts_gpio; -#ifdef CONFIG_STM32F7_FLOWCONTROL_BROKEN +#ifdef CONFIG_STM32_FLOWCONTROL_BROKEN /* Instead of letting hw manage this pin, we will bitbang */ config = (config & ~GPIO_MODE_MASK) | GPIO_OUTPUT; @@ -2291,8 +2291,8 @@ static int up_interrupt(int irq, void *context, void *arg) /* Report serial activity to the power management logic */ -#if defined(CONFIG_PM) && CONFIG_STM32F7_PM_SERIAL_ACTIVITY > 0 - pm_activity(PM_IDLE_DOMAIN, CONFIG_STM32F7_PM_SERIAL_ACTIVITY); +#if defined(CONFIG_PM) && CONFIG_STM32_PM_SERIAL_ACTIVITY > 0 + pm_activity(PM_IDLE_DOMAIN, CONFIG_STM32_PM_SERIAL_ACTIVITY); #endif /* Loop until there are no characters to be transferred or, @@ -2405,11 +2405,11 @@ static int up_interrupt(int irq, void *context, void *arg) static int up_ioctl(struct file *filep, int cmd, unsigned long arg) { #if defined(CONFIG_SERIAL_TERMIOS) || defined(CONFIG_SERIAL_TIOCSERGSTRUCT) \ - || defined(CONFIG_STM32F7_SERIALBRK_BSDCOMPAT) + || defined(CONFIG_STM32_SERIALBRK_BSDCOMPAT) struct inode *inode = filep->f_inode; struct uart_dev_s *dev = inode->i_private; #endif -#if defined(CONFIG_SERIAL_TERMIOS) || defined(CONFIG_STM32F7_SERIALBRK_BSDCOMPAT) +#if defined(CONFIG_SERIAL_TERMIOS) || defined(CONFIG_STM32_SERIALBRK_BSDCOMPAT) struct up_dev_s *priv = (struct up_dev_s *)dev->priv; #endif int ret = OK; @@ -2432,7 +2432,7 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg) break; #endif -#ifdef CONFIG_STM32F7_USART_SINGLEWIRE +#ifdef CONFIG_STM32_USART_SINGLEWIRE case TIOCSSINGLEWIRE: { uint32_t cr1; @@ -2499,7 +2499,7 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg) break; #endif -#ifdef CONFIG_STM32F7_USART_INVERT +#ifdef CONFIG_STM32_USART_INVERT case TIOCSINVERT: { uint32_t cr1; @@ -2550,7 +2550,7 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg) break; #endif -#ifdef CONFIG_STM32F7_USART_SWAP +#ifdef CONFIG_STM32_USART_SWAP case TIOCSSWAP: { uint32_t cr1; @@ -2687,8 +2687,8 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg) break; #endif /* CONFIG_SERIAL_TERMIOS */ -#ifdef CONFIG_STM32F7_USART_BREAKS -# ifdef CONFIG_STM32F7_SERIALBRK_BSDCOMPAT +#ifdef CONFIG_STM32_USART_BREAKS +# ifdef CONFIG_STM32_SERIALBRK_BSDCOMPAT case TIOCSBRK: /* BSD compatibility: Turn break on, unconditionally */ { irqstate_t flags; @@ -2907,7 +2907,7 @@ static bool up_rxflowcontrol(struct uart_dev_s *dev, struct up_dev_s *priv = (struct up_dev_s *)dev->priv; #if defined(CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS) && \ - defined(CONFIG_STM32F7_FLOWCONTROL_BROKEN) + defined(CONFIG_STM32_FLOWCONTROL_BROKEN) if (priv->iflow && (priv->rts_gpio != 0)) { /* Assert/de-assert nRTS set it high resume/stop sending */ @@ -3565,7 +3565,7 @@ static int up_pm_prepare(struct pm_callback_s *cb, int domain, * buffers. */ - for (n = 0; n < STM32F7_NUSART + STM32F7_NUART; n++) + for (n = 0; n < STM32_NUSART + STM32_NUART; n++) { struct up_dev_s *priv = g_uart_devs[n]; @@ -3699,7 +3699,7 @@ void arm_serialinit(void) #if CONSOLE_UART > 0 uart_register("/dev/console", &g_uart_devs[CONSOLE_UART - 1]->dev); -#ifndef CONFIG_STM32F7_SERIAL_DISABLE_REORDERING +#ifndef CONFIG_STM32_SERIAL_DISABLE_REORDERING /* If not disabled, register the console UART to ttyS0 and exclude * it from initializing it further down */ @@ -3728,7 +3728,7 @@ void arm_serialinit(void) continue; } -#ifndef CONFIG_STM32F7_SERIAL_DISABLE_REORDERING +#ifndef CONFIG_STM32_SERIAL_DISABLE_REORDERING /* Don't create a device for the console - we did that above */ if (g_uart_devs[i]->dev.isconsole) diff --git a/arch/arm/src/stm32f7/stm32_spi.c b/arch/arm/src/stm32f7/stm32_spi.c index 4ddc01a553905..2b43927a3ec48 100644 --- a/arch/arm/src/stm32f7/stm32_spi.c +++ b/arch/arm/src/stm32f7/stm32_spi.c @@ -73,9 +73,9 @@ #include "stm32_dma.h" #include "stm32_spi.h" -#if defined(CONFIG_STM32F7_SPI1) || defined(CONFIG_STM32F7_SPI2) || \ - defined(CONFIG_STM32F7_SPI3) || defined(CONFIG_STM32F7_SPI4) || \ - defined(CONFIG_STM32F7_SPI5) || defined(CONFIG_STM32F7_SPI6) +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || \ + defined(CONFIG_STM32_SPI3) || defined(CONFIG_STM32_SPI4) || \ + defined(CONFIG_STM32_SPI5) || defined(CONFIG_STM32_SPI6) /**************************************************************************** * Pre-processor Definitions @@ -85,19 +85,19 @@ /* SPI interrupts */ -#ifdef CONFIG_STM32F7_SPI_INTERRUPTS +#ifdef CONFIG_STM32_SPI_INTERRUPTS # error "Interrupt driven SPI not yet supported" #endif /* Can't have both interrupt driven SPI and SPI DMA */ -#if defined(CONFIG_STM32F7_SPI_INTERRUPTS) && defined(CONFIG_STM32F7_SPI_DMA) +#if defined(CONFIG_STM32_SPI_INTERRUPTS) && defined(CONFIG_STM32_SPI_DMA) # error "Cannot enable both interrupt mode and DMA mode for SPI" #endif /* SPI DMA priority */ -#ifdef CONFIG_STM32F7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA # if defined(CONFIG_SPI_DMAPRIO) # define SPI_DMA_PRIO CONFIG_SPI_DMAPRIO @@ -135,39 +135,39 @@ # define SPIDMA_BUF_ALIGN # endif -# if defined(CONFIG_STM32F7_SPI1_DMA_BUFFER) && \ - CONFIG_STM32F7_SPI1_DMA_BUFFER > 0 -# define SPI1_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32F7_SPI1_DMA_BUFFER) +# if defined(CONFIG_STM32_SPI1_DMA_BUFFER) && \ + CONFIG_STM32_SPI1_DMA_BUFFER > 0 +# define SPI1_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32_SPI1_DMA_BUFFER) # define SPI1_DMABUFSIZE_ALGN SPIDMA_BUF_ALIGN # endif -# if defined(CONFIG_STM32F7_SPI2_DMA_BUFFER) && \ - CONFIG_STM32F7_SPI2_DMA_BUFFER > 0 -# define SPI2_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32F7_SPI2_DMA_BUFFER) +# if defined(CONFIG_STM32_SPI2_DMA_BUFFER) && \ + CONFIG_STM32_SPI2_DMA_BUFFER > 0 +# define SPI2_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32_SPI2_DMA_BUFFER) # define SPI2_DMABUFSIZE_ALGN SPIDMA_BUF_ALIGN # endif -# if defined(CONFIG_STM32F7_SPI3_DMA_BUFFER) && \ - CONFIG_STM32F7_SPI3_DMA_BUFFER > 0 -# define SPI3_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32F7_SPI3_DMA_BUFFER) +# if defined(CONFIG_STM32_SPI3_DMA_BUFFER) && \ + CONFIG_STM32_SPI3_DMA_BUFFER > 0 +# define SPI3_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32_SPI3_DMA_BUFFER) # define SPI3_DMABUFSIZE_ALGN SPIDMA_BUF_ALIGN # endif -# if defined(CONFIG_STM32F7_SPI4_DMA_BUFFER) && \ - CONFIG_STM32F7_SPI4_DMA_BUFFER > 0 -# define SPI4_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32F7_SPI4_DMA_BUFFER) +# if defined(CONFIG_STM32_SPI4_DMA_BUFFER) && \ + CONFIG_STM32_SPI4_DMA_BUFFER > 0 +# define SPI4_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32_SPI4_DMA_BUFFER) # define SPI4_DMABUFSIZE_ALGN SPIDMA_BUF_ALIGN # endif -# if defined(CONFIG_STM32F7_SPI5_DMA_BUFFER) && \ - CONFIG_STM32F7_SPI5_DMA_BUFFER > 0 -# define SPI5_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32F7_SPI5_DMA_BUFFER) +# if defined(CONFIG_STM32_SPI5_DMA_BUFFER) && \ + CONFIG_STM32_SPI5_DMA_BUFFER > 0 +# define SPI5_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32_SPI5_DMA_BUFFER) # define SPI5_DMABUFSIZE_ALGN SPIDMA_BUF_ALIGN # endif -#if defined(CONFIG_STM32F7_SPI6_DMA_BUFFER) && \ - CONFIG_STM32F7_SPI6_DMA_BUFFER > 0 -# define SPI6_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32F7_SPI6_DMA_BUFFER) +#if defined(CONFIG_STM32_SPI6_DMA_BUFFER) && \ + CONFIG_STM32_SPI6_DMA_BUFFER > 0 +# define SPI6_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32_SPI6_DMA_BUFFER) # define SPI6_DMABUFSIZE_ALGN SPIDMA_BUF_ALIGN # endif @@ -182,10 +182,10 @@ struct stm32_spidev_s struct spi_dev_s spidev; /* Externally visible part of the SPI interface */ uint32_t spibase; /* SPIn base address */ uint32_t spiclock; /* Clocking for the SPI module */ -#ifdef CONFIG_STM32F7_SPI_INTERRUPTS +#ifdef CONFIG_STM32_SPI_INTERRUPTS uint8_t spiirq; /* SPI IRQ number */ #endif -#ifdef CONFIG_STM32F7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA volatile uint8_t rxresult; /* Result of the RX DMA */ volatile uint8_t txresult; /* Result of the RX DMA */ #ifdef CONFIG_SPI_TRIGGER @@ -231,7 +231,7 @@ static inline void spi_writeword(struct stm32_spidev_s *priv, /* DMA support */ -#ifdef CONFIG_STM32F7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static int spi_dmarxwait(struct stm32_spidev_s *priv); static int spi_dmatxwait(struct stm32_spidev_s *priv); static inline void spi_dmarxwakeup(struct stm32_spidev_s *priv); @@ -291,7 +291,7 @@ static int spi_pm_prepare(struct pm_callback_s *cb, int domain, * Private Data ****************************************************************************/ -#ifdef CONFIG_STM32F7_SPI1 +#ifdef CONFIG_STM32_SPI1 static const struct spi_ops_s g_sp1iops = { .lock = spi_lock, @@ -336,11 +336,11 @@ static struct stm32_spidev_s g_spi1dev = }, .spibase = STM32_SPI1_BASE, .spiclock = STM32_PCLK2_FREQUENCY, -#ifdef CONFIG_STM32F7_SPI_INTERRUPTS +#ifdef CONFIG_STM32_SPI_INTERRUPTS .spiirq = STM32_IRQ_SPI1, #endif -#ifdef CONFIG_STM32F7_SPI_DMA -# ifdef CONFIG_STM32F7_SPI1_DMA +#ifdef CONFIG_STM32_SPI_DMA +# ifdef CONFIG_STM32_SPI1_DMA .rxch = DMAMAP_SPI1_RX, .txch = DMAMAP_SPI1_TX, # ifdef SPI1_DMABUFSIZE_ADJUSTED @@ -362,7 +362,7 @@ static struct stm32_spidev_s g_spi1dev = }; #endif -#ifdef CONFIG_STM32F7_SPI2 +#ifdef CONFIG_STM32_SPI2 static const struct spi_ops_s g_sp2iops = { .lock = spi_lock, @@ -407,11 +407,11 @@ static struct stm32_spidev_s g_spi2dev = }, .spibase = STM32_SPI2_BASE, .spiclock = STM32_PCLK1_FREQUENCY, -#ifdef CONFIG_STM32F7_SPI_INTERRUPTS +#ifdef CONFIG_STM32_SPI_INTERRUPTS .spiirq = STM32_IRQ_SPI2, #endif -#ifdef CONFIG_STM32F7_SPI_DMA -# ifdef CONFIG_STM32F7_SPI2_DMA +#ifdef CONFIG_STM32_SPI_DMA +# ifdef CONFIG_STM32_SPI2_DMA .rxch = DMAMAP_SPI2_RX, .txch = DMAMAP_SPI2_TX, # ifdef SPI3_DMABUFSIZE_ADJUSTED @@ -433,7 +433,7 @@ static struct stm32_spidev_s g_spi2dev = }; #endif -#ifdef CONFIG_STM32F7_SPI3 +#ifdef CONFIG_STM32_SPI3 static const struct spi_ops_s g_sp3iops = { .lock = spi_lock, @@ -478,11 +478,11 @@ static struct stm32_spidev_s g_spi3dev = }, .spibase = STM32_SPI3_BASE, .spiclock = STM32_PCLK1_FREQUENCY, -#ifdef CONFIG_STM32F7_SPI_INTERRUPTS +#ifdef CONFIG_STM32_SPI_INTERRUPTS .spiirq = STM32_IRQ_SPI3, #endif -#ifdef CONFIG_STM32F7_SPI_DMA -# ifdef CONFIG_STM32F7_SPI3_DMA +#ifdef CONFIG_STM32_SPI_DMA +# ifdef CONFIG_STM32_SPI3_DMA .rxch = DMAMAP_SPI3_RX, .txch = DMAMAP_SPI3_TX, # ifdef SPI3_DMABUFSIZE_ADJUSTED @@ -504,7 +504,7 @@ static struct stm32_spidev_s g_spi3dev = }; #endif -#ifdef CONFIG_STM32F7_SPI4 +#ifdef CONFIG_STM32_SPI4 static const struct spi_ops_s g_sp4iops = { .lock = spi_lock, @@ -549,11 +549,11 @@ static struct stm32_spidev_s g_spi4dev = }, .spibase = STM32_SPI4_BASE, .spiclock = STM32_PCLK2_FREQUENCY, -#ifdef CONFIG_STM32F7_SPI_INTERRUPTS +#ifdef CONFIG_STM32_SPI_INTERRUPTS .spiirq = STM32_IRQ_SPI4, #endif -#ifdef CONFIG_STM32F7_SPI_DMA -# ifdef CONFIG_STM32F7_SPI4_DMA +#ifdef CONFIG_STM32_SPI_DMA +# ifdef CONFIG_STM32_SPI4_DMA .rxch = DMAMAP_SPI4_RX, .txch = DMAMAP_SPI4_TX, # ifdef SPI4_DMABUFSIZE_ADJUSTED @@ -575,7 +575,7 @@ static struct stm32_spidev_s g_spi4dev = }; #endif -#ifdef CONFIG_STM32F7_SPI5 +#ifdef CONFIG_STM32_SPI5 static const struct spi_ops_s g_sp5iops = { .lock = spi_lock, @@ -620,11 +620,11 @@ static struct stm32_spidev_s g_spi5dev = }, .spibase = STM32_SPI5_BASE, .spiclock = STM32_PCLK2_FREQUENCY, -#ifdef CONFIG_STM32F7_SPI_INTERRUPTS +#ifdef CONFIG_STM32_SPI_INTERRUPTS .spiirq = STM32_IRQ_SPI5, #endif -#ifdef CONFIG_STM32F7_SPI_DMA -# ifdef CONFIG_STM32F7_SPI5_DMA +#ifdef CONFIG_STM32_SPI_DMA +# ifdef CONFIG_STM32_SPI5_DMA .rxch = DMAMAP_SPI5_RX, .txch = DMAMAP_SPI5_TX, # ifdef SPI5_DMABUFSIZE_ADJUSTED @@ -646,7 +646,7 @@ static struct stm32_spidev_s g_spi5dev = }; #endif -#ifdef CONFIG_STM32F7_SPI6 +#ifdef CONFIG_STM32_SPI6 static const struct spi_ops_s g_sp6iops = { .lock = spi_lock, @@ -691,11 +691,11 @@ static struct stm32_spidev_s g_spi6dev = }, .spibase = STM32_SPI6_BASE, .spiclock = STM32_PCLK2_FREQUENCY, -#ifdef CONFIG_STM32F7_SPI_INTERRUPTS +#ifdef CONFIG_STM32_SPI_INTERRUPTS .spiirq = STM32_IRQ_SPI6, #endif -#ifdef CONFIG_STM32F7_SPI_DMA -# ifdef CONFIG_STM32F7_SPI6_DMA +#ifdef CONFIG_STM32_SPI_DMA +# ifdef CONFIG_STM32_SPI6_DMA .rxch = DMAMAP_SPI6_RX, .txch = DMAMAP_SPI6_TX, # ifdef SPI6_DMABUFSIZE_ADJUSTED @@ -916,7 +916,7 @@ static inline void spi_writebyte(struct stm32_spidev_s *priv, * ****************************************************************************/ -#ifdef CONFIG_STM32F7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static int spi_dmarxwait(struct stm32_spidev_s *priv) { int ret; @@ -949,7 +949,7 @@ static int spi_dmarxwait(struct stm32_spidev_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32F7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static int spi_dmatxwait(struct stm32_spidev_s *priv) { int ret; @@ -982,7 +982,7 @@ static int spi_dmatxwait(struct stm32_spidev_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32F7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static inline void spi_dmarxwakeup(struct stm32_spidev_s *priv) { nxsem_post(&priv->rxsem); @@ -997,7 +997,7 @@ static inline void spi_dmarxwakeup(struct stm32_spidev_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32F7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static inline void spi_dmatxwakeup(struct stm32_spidev_s *priv) { nxsem_post(&priv->txsem); @@ -1012,7 +1012,7 @@ static inline void spi_dmatxwakeup(struct stm32_spidev_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32F7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_dmarxcallback(DMA_HANDLE handle, uint8_t isr, void *arg) { struct stm32_spidev_s *priv = (struct stm32_spidev_s *)arg; @@ -1032,7 +1032,7 @@ static void spi_dmarxcallback(DMA_HANDLE handle, uint8_t isr, void *arg) * ****************************************************************************/ -#ifdef CONFIG_STM32F7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_dmatxcallback(DMA_HANDLE handle, uint8_t isr, void *arg) { struct stm32_spidev_s *priv = (struct stm32_spidev_s *)arg; @@ -1052,7 +1052,7 @@ static void spi_dmatxcallback(DMA_HANDLE handle, uint8_t isr, void *arg) * ****************************************************************************/ -#ifdef CONFIG_STM32F7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_dmarxsetup(struct stm32_spidev_s *priv, void *rxbuffer, void *rxdummy, size_t nwords) @@ -1103,7 +1103,7 @@ static void spi_dmarxsetup(struct stm32_spidev_s *priv, * ****************************************************************************/ -#ifdef CONFIG_STM32F7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_dmatxsetup(struct stm32_spidev_s *priv, const void *txbuffer, const void *txdummy, size_t nwords) @@ -1154,7 +1154,7 @@ static void spi_dmatxsetup(struct stm32_spidev_s *priv, * ****************************************************************************/ -#ifdef CONFIG_STM32F7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_dmarxstart(struct stm32_spidev_s *priv) { priv->rxresult = 0; @@ -1170,7 +1170,7 @@ static void spi_dmarxstart(struct stm32_spidev_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32F7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_dmatxstart(struct stm32_spidev_s *priv) { priv->txresult = 0; @@ -1397,7 +1397,7 @@ static void spi_setmode(struct spi_dev_s *dev, enum spi_mode_e mode) struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev; uint16_t setbits; uint16_t clrbits; -#ifdef CONFIG_STM32F7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA uint16_t cr2bits; #endif @@ -1440,7 +1440,7 @@ static void spi_setmode(struct spi_dev_s *dev, enum spi_mode_e mode) spi_modifycr1(priv, 0, SPI_CR1_SPE); spi_modifycr1(priv, setbits, clrbits); -#ifdef CONFIG_STM32F7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA /* Enabling SPI causes a spurious received character indication * which confuse the DMA controller so we disable DMA during that * enabling; and flush the SPI RX FIFO before re-enabling DMA. @@ -1461,7 +1461,7 @@ static void spi_setmode(struct spi_dev_s *dev, enum spi_mode_e mode) spi_getreg(priv, STM32_SPI_DR_OFFSET); } -#ifdef CONFIG_STM32F7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA /* Re-enable DMA (with SPI disabled) */ @@ -1691,9 +1691,9 @@ static uint32_t spi_send(struct spi_dev_s *dev, uint32_t wd) * ****************************************************************************/ -#if !defined(CONFIG_STM32F7_SPI_DMA) || defined(CONFIG_STM32F7_DMACAPABLE) || \ - defined(CONFIG_STM32F7_SPI_DMATHRESHOLD) -#if !defined(CONFIG_STM32F7_SPI_DMA) +#if !defined(CONFIG_STM32_SPI_DMA) || defined(CONFIG_STM32_DMACAPABLE) || \ + defined(CONFIG_STM32_SPI_DMATHRESHOLD) +#if !defined(CONFIG_STM32_SPI_DMA) static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, void *rxbuffer, size_t nwords) #else @@ -1777,8 +1777,8 @@ static void spi_exchange_nodma(struct spi_dev_s *dev, } } -#endif /* !CONFIG_STM32F7_SPI_DMA || CONFIG_STM32F7_DMACAPABLE || - * CONFIG_STM32F7_SPI_DMATHRESHOLD +#endif /* !CONFIG_STM32_SPI_DMA || CONFIG_STM32_DMACAPABLE || + * CONFIG_STM32_SPI_DMATHRESHOLD */ /**************************************************************************** @@ -1802,7 +1802,7 @@ static void spi_exchange_nodma(struct spi_dev_s *dev, * ****************************************************************************/ -#ifdef CONFIG_STM32F7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, void *rxbuffer, size_t nwords) { @@ -1816,13 +1816,13 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, size_t nbytes = (priv->nbits > 8) ? nwords << 1 : nwords; -#ifdef CONFIG_STM32F7_SPI_DMATHRESHOLD +#ifdef CONFIG_STM32_SPI_DMATHRESHOLD /* If this is a small SPI transfer, then let spi_exchange_nodma() * do the work. */ - if (nbytes <= CONFIG_STM32F7_SPI_DMATHRESHOLD) + if (nbytes <= CONFIG_STM32_SPI_DMATHRESHOLD) { spi_exchange_nodma(dev, txbuffer, rxbuffer, nwords); return; @@ -1840,7 +1840,7 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, return; } -#ifdef CONFIG_STM32F7_DMACAPABLE +#ifdef CONFIG_STM32_DMACAPABLE /* If this bus uses a in driver DMA aligned buffers we can skip the test */ if ((txbuffer && priv->txbuf == 0 && @@ -1948,7 +1948,7 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, } } } -#endif /* CONFIG_STM32F7_SPI_DMA */ +#endif /* CONFIG_STM32_SPI_DMA */ /**************************************************************************** * Name: spi_trigger @@ -1969,7 +1969,7 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, #ifdef CONFIG_SPI_TRIGGER static int spi_trigger(struct spi_dev_s *dev) { -#ifdef CONFIG_STM32F7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev; if (!priv->trigarmed) @@ -2173,7 +2173,7 @@ static void spi_bus_initialize(struct stm32_spidev_s *priv) spi_putreg(priv, STM32_SPI_CRCPR_OFFSET, 7); -#ifdef CONFIG_STM32F7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA if (priv->rxch && priv->txch) { /* Get DMA channels. NOTE: stm32_dmachannel() will always assign the @@ -2235,7 +2235,7 @@ struct spi_dev_s *stm32_spibus_initialize(int bus) irqstate_t flags = enter_critical_section(); -#ifdef CONFIG_STM32F7_SPI1 +#ifdef CONFIG_STM32_SPI1 if (bus == 1) { /* Select SPI1 */ @@ -2260,7 +2260,7 @@ struct spi_dev_s *stm32_spibus_initialize(int bus) } else #endif -#ifdef CONFIG_STM32F7_SPI2 +#ifdef CONFIG_STM32_SPI2 if (bus == 2) { /* Select SPI2 */ @@ -2285,7 +2285,7 @@ struct spi_dev_s *stm32_spibus_initialize(int bus) } else #endif -#ifdef CONFIG_STM32F7_SPI3 +#ifdef CONFIG_STM32_SPI3 if (bus == 3) { /* Select SPI3 */ @@ -2310,7 +2310,7 @@ struct spi_dev_s *stm32_spibus_initialize(int bus) } else #endif -#ifdef CONFIG_STM32F7_SPI4 +#ifdef CONFIG_STM32_SPI4 if (bus == 4) { /* Select SPI4 */ @@ -2335,7 +2335,7 @@ struct spi_dev_s *stm32_spibus_initialize(int bus) } else #endif -#ifdef CONFIG_STM32F7_SPI5 +#ifdef CONFIG_STM32_SPI5 if (bus == 5) { /* Select SPI5 */ @@ -2360,7 +2360,7 @@ struct spi_dev_s *stm32_spibus_initialize(int bus) } else #endif -#ifdef CONFIG_STM32F7_SPI6 +#ifdef CONFIG_STM32_SPI6 if (bus == 6) { /* Select SPI6 */ @@ -2393,6 +2393,6 @@ struct spi_dev_s *stm32_spibus_initialize(int bus) return (struct spi_dev_s *)priv; } -#endif /* CONFIG_STM32F7_SPI1 || CONFIG_STM32F7_SPI2 || CONFIG_STM32F7_SPI3 || - * CONFIG_STM32F7_SPI4 || CONFIG_STM32F7_SPI5 || CONFIG_STM32F7_SPI6 +#endif /* CONFIG_STM32_SPI1 || CONFIG_STM32_SPI2 || CONFIG_STM32_SPI3 || + * CONFIG_STM32_SPI4 || CONFIG_STM32_SPI5 || CONFIG_STM32_SPI6 */ diff --git a/arch/arm/src/stm32f7/stm32_spi.h b/arch/arm/src/stm32f7/stm32_spi.h index f4adbac6a5e16..346af6685970f 100644 --- a/arch/arm/src/stm32f7/stm32_spi.h +++ b/arch/arm/src/stm32f7/stm32_spi.h @@ -98,42 +98,42 @@ struct spi_dev_s *stm32_spibus_initialize(int bus); * ****************************************************************************/ -#ifdef CONFIG_STM32F7_SPI1 +#ifdef CONFIG_STM32_SPI1 void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, bool selected); uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid); int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); #endif -#ifdef CONFIG_STM32F7_SPI2 +#ifdef CONFIG_STM32_SPI2 void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid, bool selected); uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid); int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); #endif -#ifdef CONFIG_STM32F7_SPI3 +#ifdef CONFIG_STM32_SPI3 void stm32_spi3select(struct spi_dev_s *dev, uint32_t devid, bool selected); uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid); int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); #endif -#ifdef CONFIG_STM32F7_SPI4 +#ifdef CONFIG_STM32_SPI4 void stm32_spi4select(struct spi_dev_s *dev, uint32_t devid, bool selected); uint8_t stm32_spi4status(struct spi_dev_s *dev, uint32_t devid); int stm32_spi4cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); #endif -#ifdef CONFIG_STM32F7_SPI5 +#ifdef CONFIG_STM32_SPI5 void stm32_spi5select(struct spi_dev_s *dev, uint32_t devid, bool selected); uint8_t stm32_spi5status(struct spi_dev_s *dev, uint32_t devid); int stm32_spi5cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); #endif -#ifdef CONFIG_STM32F7_SPI6 +#ifdef CONFIG_STM32_SPI6 void stm32_spi6select(struct spi_dev_s *dev, uint32_t devid, bool selected); uint8_t stm32_spi6status(struct spi_dev_s *dev, uint32_t devid); @@ -161,32 +161,32 @@ int stm32_spi6cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); ****************************************************************************/ #ifdef CONFIG_SPI_CALLBACK -#ifdef CONFIG_STM32F7_SPI1 +#ifdef CONFIG_STM32_SPI1 int stm32_spi1register(struct spi_dev_s *dev, spi_mediachange_t callback, void *arg); #endif -#ifdef CONFIG_STM32F7_SPI2 +#ifdef CONFIG_STM32_SPI2 int stm32_spi2register(struct spi_dev_s *dev, spi_mediachange_t callback, void *arg); #endif -#ifdef CONFIG_STM32F7_SPI3 +#ifdef CONFIG_STM32_SPI3 int stm32_spi3register(struct spi_dev_s *dev, spi_mediachange_t callback, void *arg); #endif -#ifdef CONFIG_STM32F7_SPI4 +#ifdef CONFIG_STM32_SPI4 int stm32_spi4register(struct spi_dev_s *dev, spi_mediachange_t callback, void *arg); #endif -#ifdef CONFIG_STM32F7_SPI5 +#ifdef CONFIG_STM32_SPI5 int stm32_spi5register(struct spi_dev_s *dev, spi_mediachange_t callback, void *arg); #endif -#ifdef CONFIG_STM32F7_SPI6 +#ifdef CONFIG_STM32_SPI6 int stm32_spi6register(struct spi_dev_s *dev, spi_mediachange_t callback, void *arg); #endif diff --git a/arch/arm/src/stm32f7/stm32_tickless.c b/arch/arm/src/stm32f7/stm32_tickless.c index 52ddb0e04bd20..d348d93cadb66 100644 --- a/arch/arm/src/stm32f7/stm32_tickless.c +++ b/arch/arm/src/stm32f7/stm32_tickless.c @@ -107,18 +107,18 @@ #undef HAVE_32BIT_TICKLESS -#if (CONFIG_STM32F7_TICKLESS_TIMER == 2) || \ - (CONFIG_STM32F7_TICKLESS_TIMER == 5) +#if (CONFIG_STM32_TICKLESS_TIMER == 2) || \ + (CONFIG_STM32_TICKLESS_TIMER == 5) #define HAVE_32BIT_TICKLESS 1 #endif -#if CONFIG_STM32F7_TICKLESS_CHANNEL == 1 +#if CONFIG_STM32_TICKLESS_CHANNEL == 1 #define DIER_CAPT_IE GTIM_DIER_CC1IE -#elif CONFIG_STM32F7_TICKLESS_CHANNEL == 2 +#elif CONFIG_STM32_TICKLESS_CHANNEL == 2 #define DIER_CAPT_IE GTIM_DIER_CC2IE -#elif CONFIG_STM32F7_TICKLESS_CHANNEL == 3 +#elif CONFIG_STM32_TICKLESS_CHANNEL == 3 #define DIER_CAPT_IE GTIM_DIER_CC3IE -#elif CONFIG_STM32F7_TICKLESS_CHANNEL == 4 +#elif CONFIG_STM32_TICKLESS_CHANNEL == 4 #define DIER_CAPT_IE GTIM_DIER_CC4IE #endif @@ -426,43 +426,43 @@ static uint64_t stm32_get_counter(void) void up_timer_initialize(void) { - switch (CONFIG_STM32F7_TICKLESS_TIMER) + switch (CONFIG_STM32_TICKLESS_TIMER) { -#ifdef CONFIG_STM32F7_TIM1 +#ifdef CONFIG_STM32_TIM1 case 1: g_tickless.base = STM32_TIM1_BASE; modifyreg32(STM32_DBGMCU_APB2_FZ, 0, DBGMCU_APB2_TIM1STOP); break; #endif -#ifdef CONFIG_STM32F7_TIM2 +#ifdef CONFIG_STM32_TIM2 case 2: g_tickless.base = STM32_TIM2_BASE; modifyreg32(STM32_DBGMCU_APB1_FZ, 0, DBGMCU_APB1_TIM2STOP); break; #endif -#ifdef CONFIG_STM32F7_TIM3 +#ifdef CONFIG_STM32_TIM3 case 3: g_tickless.base = STM32_TIM3_BASE; modifyreg32(STM32_DBGMCU_APB1_FZ, 0, DBGMCU_APB1_TIM3STOP); break; #endif -#ifdef CONFIG_STM32F7_TIM4 +#ifdef CONFIG_STM32_TIM4 case 4: g_tickless.base = STM32_TIM4_BASE; modifyreg32(STM32_DBGMCU_APB1_FZ, 0, DBGMCU_APB1_TIM4STOP); break; #endif -#ifdef CONFIG_STM32F7_TIM5 +#ifdef CONFIG_STM32_TIM5 case 5: g_tickless.base = STM32_TIM5_BASE; modifyreg32(STM32_DBGMCU_APB1_FZ, 0, DBGMCU_APB1_TIM5STOP); break; #endif -#ifdef CONFIG_STM32F7_TIM6 +#ifdef CONFIG_STM32_TIM6 case 6: /* Basic timers not supported by this implementation */ @@ -471,7 +471,7 @@ void up_timer_initialize(void) break; #endif -#ifdef CONFIG_STM32F7_TIM7 +#ifdef CONFIG_STM32_TIM7 case 7: /* Basic timers not supported by this implementation */ @@ -480,52 +480,52 @@ void up_timer_initialize(void) break; #endif -#ifdef CONFIG_STM32F7_TIM8 +#ifdef CONFIG_STM32_TIM8 case 8: g_tickless.base = STM32_TIM8_BASE; modifyreg32(STM32_DBGMCU_APB2_FZ, 0, DBGMCU_APB2_TIM8STOP); break; #endif -#ifdef CONFIG_STM32F7_TIM9 +#ifdef CONFIG_STM32_TIM9 case 9: g_tickless.base = STM32_TIM9_BASE; modifyreg32(STM32_DBGMCU_APB2_FZ, 0, DBGMCU_APB2_TIM9STOP); break; #endif -#ifdef CONFIG_STM32F7_TIM10 +#ifdef CONFIG_STM32_TIM10 case 10: g_tickless.base = STM32_TIM10_BASE; modifyreg32(STM32_DBGMCU_APB2_FZ, 0, DBGMCU_APB2_TIM10STOP); break; #endif -#ifdef CONFIG_STM32F7_TIM11 +#ifdef CONFIG_STM32_TIM11 case 11: g_tickless.base = STM32_TIM11_BASE; modifyreg32(STM32_DBGMCU_APB2_FZ, 0, DBGMCU_APB2_TIM11STOP); break; #endif -#ifdef CONFIG_STM32F7_TIM12 +#ifdef CONFIG_STM32_TIM12 case 12: g_tickless.base = STM32_TIM12_BASE; modifyreg32(STM32_DBGMCU_APB1_FZ, 0, DBGMCU_APB1_TIM12STOP); break; #endif -#ifdef CONFIG_STM32F7_TIM13 +#ifdef CONFIG_STM32_TIM13 case 13: g_tickless.base = STM32_TIM13_BASE; modifyreg32(STM32_DBGMCU_APB1_FZ, 0, DBGMCU_APB1_TIM13STOP); break; #endif -#ifdef CONFIG_STM32F7_TIM14 +#ifdef CONFIG_STM32_TIM14 case 14: g_tickless.base = STM32_TIM14_BASE; modifyreg32(STM32_DBGMCU_APB1_FZ, 0, DBGMCU_APB1_TIM14STOP); break; #endif -#ifdef CONFIG_STM32F7_TIM15 +#ifdef CONFIG_STM32_TIM15 case 15: g_tickless.base = STM32_TIM15_BASE; @@ -534,7 +534,7 @@ void up_timer_initialize(void) break; #endif -#ifdef CONFIG_STM32F7_TIM16 +#ifdef CONFIG_STM32_TIM16 case 16: g_tickless.base = STM32_TIM16_BASE; @@ -543,7 +543,7 @@ void up_timer_initialize(void) break; #endif -#ifdef CONFIG_STM32F7_TIM17 +#ifdef CONFIG_STM32_TIM17 case 17: g_tickless.base = STM32_TIM17_BASE; @@ -559,8 +559,8 @@ void up_timer_initialize(void) /* Get the TC frequency that corresponds to the requested resolution */ g_tickless.frequency = USEC_PER_SEC / (uint32_t)CONFIG_USEC_PER_TICK; - g_tickless.timer = CONFIG_STM32F7_TICKLESS_TIMER; - g_tickless.channel = CONFIG_STM32F7_TICKLESS_CHANNEL; + g_tickless.timer = CONFIG_STM32_TICKLESS_TIMER; + g_tickless.channel = CONFIG_STM32_TICKLESS_CHANNEL; g_tickless.pending = false; g_tickless.period = 0; g_tickless.overflow = 0; @@ -1027,10 +1027,10 @@ int up_alarm_start(const struct timespec *ts) flags = enter_critical_section(); - STM32_TIM_SETCOMPARE(g_tickless.tch, CONFIG_STM32F7_TICKLESS_CHANNEL, tm); + STM32_TIM_SETCOMPARE(g_tickless.tch, CONFIG_STM32_TICKLESS_CHANNEL, tm); stm32_tickless_ackint(g_tickless.channel); - stm32_tickless_enableint(CONFIG_STM32F7_TICKLESS_CHANNEL); + stm32_tickless_enableint(CONFIG_STM32_TICKLESS_CHANNEL); g_tickless.pending = true; @@ -1047,7 +1047,7 @@ int up_alarm_start(const struct timespec *ts) while (tm <= stm32_get_counter()) { tm = stm32_get_counter() + offset++; - STM32_TIM_SETCOMPARE(g_tickless.tch, CONFIG_STM32F7_TICKLESS_CHANNEL, + STM32_TIM_SETCOMPARE(g_tickless.tch, CONFIG_STM32_TICKLESS_CHANNEL, tm); } @@ -1068,7 +1068,7 @@ int up_alarm_cancel(struct timespec *ts) ts->tv_sec = nsecs / NSEC_PER_SEC; ts->tv_nsec = nsecs - ts->tv_sec * NSEC_PER_SEC; - stm32_tickless_disableint(CONFIG_STM32F7_TICKLESS_CHANNEL); + stm32_tickless_disableint(CONFIG_STM32_TICKLESS_CHANNEL); return 0; } diff --git a/arch/arm/src/stm32f7/stm32_tim.c b/arch/arm/src/stm32f7/stm32_tim.c index e5ba58297196f..b69490b7e4666 100644 --- a/arch/arm/src/stm32f7/stm32_tim.c +++ b/arch/arm/src/stm32f7/stm32_tim.c @@ -53,159 +53,159 @@ * Such special purposes include: * * - To generate modulated outputs for such things as motor control. If - * CONFIG_STM32F7_TIMn is defined then the CONFIG_STM32F7_TIMn_PWM may also + * CONFIG_STM32_TIMn is defined then the CONFIG_STM32_TIMn_PWM may also * be defined to indicate that the timer is intended to be used for pulsed * output modulation. * - * - To control periodic ADC input sampling. If CONFIG_STM32F7_TIMn is - * defined then CONFIG_STM32F7_TIMn_ADC may also be defined to indicate + * - To control periodic ADC input sampling. If CONFIG_STM32_TIMn is + * defined then CONFIG_STM32_TIMn_ADC may also be defined to indicate * that timer "n" is intended to be used for that purpose. * - * - To control periodic DAC outputs. If CONFIG_STM32F7_TIMn is defined - * then CONFIG_STM32F7_TIMn_DAC may also be defined to indicate that timer + * - To control periodic DAC outputs. If CONFIG_STM32_TIMn is defined + * then CONFIG_STM32_TIMn_DAC may also be defined to indicate that timer * "n" is intended to be used for that purpose. * - * - To use a Quadrature Encoder. If CONFIG_STM32F7_TIMn is defined then - * CONFIG_STM32F7_TIMn_QE may also be defined to indicate that timer + * - To use a Quadrature Encoder. If CONFIG_STM32_TIMn is defined then + * CONFIG_STM32_TIMn_QE may also be defined to indicate that timer * "n" is intended to be used for that purpose. * * In any of these cases, the timer will not be used by this timer module. */ -#if defined(CONFIG_STM32F7_TIM1_PWM) || defined (CONFIG_STM32F7_TIM1_ADC) || \ - defined(CONFIG_STM32F7_TIM1_DAC) || defined(CONFIG_STM32F7_TIM1_QE) -# undef CONFIG_STM32F7_TIM1 +#if defined(CONFIG_STM32_TIM1_PWM) || defined (CONFIG_STM32_TIM1_ADC) || \ + defined(CONFIG_STM32_TIM1_DAC) || defined(CONFIG_STM32_TIM1_QE) +# undef CONFIG_STM32_TIM1 #endif -#if defined(CONFIG_STM32F7_TIM2_PWM) || defined (CONFIG_STM32F7_TIM2_ADC) || \ - defined(CONFIG_STM32F7_TIM2_DAC) || defined(CONFIG_STM32F7_TIM2_QE) -# undef CONFIG_STM32F7_TIM2 +#if defined(CONFIG_STM32_TIM2_PWM) || defined (CONFIG_STM32_TIM2_ADC) || \ + defined(CONFIG_STM32_TIM2_DAC) || defined(CONFIG_STM32_TIM2_QE) +# undef CONFIG_STM32_TIM2 #endif -#if defined(CONFIG_STM32F7_TIM3_PWM) || defined (CONFIG_STM32F7_TIM3_ADC) || \ - defined(CONFIG_STM32F7_TIM3_DAC) || defined(CONFIG_STM32F7_TIM3_QE) -# undef CONFIG_STM32F7_TIM3 +#if defined(CONFIG_STM32_TIM3_PWM) || defined (CONFIG_STM32_TIM3_ADC) || \ + defined(CONFIG_STM32_TIM3_DAC) || defined(CONFIG_STM32_TIM3_QE) +# undef CONFIG_STM32_TIM3 #endif -#if defined(CONFIG_STM32F7_TIM4_PWM) || defined (CONFIG_STM32F7_TIM4_ADC) || \ - defined(CONFIG_STM32F7_TIM4_DAC) || defined(CONFIG_STM32F7_TIM4_QE) -# undef CONFIG_STM32F7_TIM4 +#if defined(CONFIG_STM32_TIM4_PWM) || defined (CONFIG_STM32_TIM4_ADC) || \ + defined(CONFIG_STM32_TIM4_DAC) || defined(CONFIG_STM32_TIM4_QE) +# undef CONFIG_STM32_TIM4 #endif -#if defined(CONFIG_STM32F7_TIM5_PWM) || defined (CONFIG_STM32F7_TIM5_ADC) || \ - defined(CONFIG_STM32F7_TIM5_DAC) || defined(CONFIG_STM32F7_TIM5_QE) -# undef CONFIG_STM32F7_TIM5 +#if defined(CONFIG_STM32_TIM5_PWM) || defined (CONFIG_STM32_TIM5_ADC) || \ + defined(CONFIG_STM32_TIM5_DAC) || defined(CONFIG_STM32_TIM5_QE) +# undef CONFIG_STM32_TIM5 #endif -#if defined(CONFIG_STM32F7_TIM6_PWM) || defined (CONFIG_STM32F7_TIM6_ADC) || \ - defined(CONFIG_STM32F7_TIM6_DAC) || defined(CONFIG_STM32F7_TIM6_QE) -# undef CONFIG_STM32F7_TIM6 +#if defined(CONFIG_STM32_TIM6_PWM) || defined (CONFIG_STM32_TIM6_ADC) || \ + defined(CONFIG_STM32_TIM6_DAC) || defined(CONFIG_STM32_TIM6_QE) +# undef CONFIG_STM32_TIM6 #endif -#if defined(CONFIG_STM32F7_TIM7_PWM) || defined (CONFIG_STM32F7_TIM7_ADC) || \ - defined(CONFIG_STM32F7_TIM7_DAC) || defined(CONFIG_STM32F7_TIM7_QE) -# undef CONFIG_STM32F7_TIM7 +#if defined(CONFIG_STM32_TIM7_PWM) || defined (CONFIG_STM32_TIM7_ADC) || \ + defined(CONFIG_STM32_TIM7_DAC) || defined(CONFIG_STM32_TIM7_QE) +# undef CONFIG_STM32_TIM7 #endif -#if defined(CONFIG_STM32F7_TIM8_PWM) || defined (CONFIG_STM32F7_TIM8_ADC) || \ - defined(CONFIG_STM32F7_TIM8_DAC) || defined(CONFIG_STM32F7_TIM8_QE) -# undef CONFIG_STM32F7_TIM8 +#if defined(CONFIG_STM32_TIM8_PWM) || defined (CONFIG_STM32_TIM8_ADC) || \ + defined(CONFIG_STM32_TIM8_DAC) || defined(CONFIG_STM32_TIM8_QE) +# undef CONFIG_STM32_TIM8 #endif -#if defined(CONFIG_STM32F7_TIM9_PWM) || defined (CONFIG_STM32F7_TIM9_ADC) || \ - defined(CONFIG_STM32F7_TIM9_DAC) || defined(CONFIG_STM32F7_TIM9_QE) -# undef CONFIG_STM32F7_TIM9 +#if defined(CONFIG_STM32_TIM9_PWM) || defined (CONFIG_STM32_TIM9_ADC) || \ + defined(CONFIG_STM32_TIM9_DAC) || defined(CONFIG_STM32_TIM9_QE) +# undef CONFIG_STM32_TIM9 #endif -#if defined(CONFIG_STM32F7_TIM10_PWM) || defined (CONFIG_STM32F7_TIM10_ADC) || \ - defined(CONFIG_STM32F7_TIM10_DAC) || defined(CONFIG_STM32F7_TIM10_QE) -# undef CONFIG_STM32F7_TIM10 +#if defined(CONFIG_STM32_TIM10_PWM) || defined (CONFIG_STM32_TIM10_ADC) || \ + defined(CONFIG_STM32_TIM10_DAC) || defined(CONFIG_STM32_TIM10_QE) +# undef CONFIG_STM32_TIM10 #endif -#if defined(CONFIG_STM32F7_TIM11_PWM) || defined (CONFIG_STM32F7_TIM11_ADC) || \ - defined(CONFIG_STM32F7_TIM11_DAC) || defined(CONFIG_STM32F7_TIM11_QE) -# undef CONFIG_STM32F7_TIM11 +#if defined(CONFIG_STM32_TIM11_PWM) || defined (CONFIG_STM32_TIM11_ADC) || \ + defined(CONFIG_STM32_TIM11_DAC) || defined(CONFIG_STM32_TIM11_QE) +# undef CONFIG_STM32_TIM11 #endif -#if defined(CONFIG_STM32F7_TIM12_PWM) || defined (CONFIG_STM32F7_TIM12_ADC) || \ - defined(CONFIG_STM32F7_TIM12_DAC) || defined(CONFIG_STM32F7_TIM12_QE) -# undef CONFIG_STM32F7_TIM12 +#if defined(CONFIG_STM32_TIM12_PWM) || defined (CONFIG_STM32_TIM12_ADC) || \ + defined(CONFIG_STM32_TIM12_DAC) || defined(CONFIG_STM32_TIM12_QE) +# undef CONFIG_STM32_TIM12 #endif -#if defined(CONFIG_STM32F7_TIM13_PWM) || defined (CONFIG_STM32F7_TIM13_ADC) || \ - defined(CONFIG_STM32F7_TIM13_DAC) || defined(CONFIG_STM32F7_TIM13_QE) -# undef CONFIG_STM32F7_TIM13 +#if defined(CONFIG_STM32_TIM13_PWM) || defined (CONFIG_STM32_TIM13_ADC) || \ + defined(CONFIG_STM32_TIM13_DAC) || defined(CONFIG_STM32_TIM13_QE) +# undef CONFIG_STM32_TIM13 #endif -#if defined(CONFIG_STM32F7_TIM14_PWM) || defined (CONFIG_STM32F7_TIM14_ADC) || \ - defined(CONFIG_STM32F7_TIM14_DAC) || defined(CONFIG_STM32F7_TIM14_QE) -# undef CONFIG_STM32F7_TIM14 +#if defined(CONFIG_STM32_TIM14_PWM) || defined (CONFIG_STM32_TIM14_ADC) || \ + defined(CONFIG_STM32_TIM14_DAC) || defined(CONFIG_STM32_TIM14_QE) +# undef CONFIG_STM32_TIM14 #endif -#if defined(CONFIG_STM32F7_TIM1) +#if defined(CONFIG_STM32_TIM1) # if defined(GPIO_TIM1_CH1OUT) ||defined(GPIO_TIM1_CH2OUT)||\ defined(GPIO_TIM1_CH3OUT) ||defined(GPIO_TIM1_CH4OUT) # define HAVE_TIM1_GPIOCONFIG 1 #endif #endif -#if defined(CONFIG_STM32F7_TIM2) +#if defined(CONFIG_STM32_TIM2) # if defined(GPIO_TIM2_CH1OUT) ||defined(GPIO_TIM2_CH2OUT)||\ defined(GPIO_TIM2_CH3OUT) ||defined(GPIO_TIM2_CH4OUT) # define HAVE_TIM2_GPIOCONFIG 1 #endif #endif -#if defined(CONFIG_STM32F7_TIM3) +#if defined(CONFIG_STM32_TIM3) # if defined(GPIO_TIM3_CH1OUT) ||defined(GPIO_TIM3_CH2OUT)||\ defined(GPIO_TIM3_CH3OUT) ||defined(GPIO_TIM3_CH4OUT) # define HAVE_TIM3_GPIOCONFIG 1 #endif #endif -#if defined(CONFIG_STM32F7_TIM4) +#if defined(CONFIG_STM32_TIM4) # if defined(GPIO_TIM4_CH1OUT) ||defined(GPIO_TIM4_CH2OUT)||\ defined(GPIO_TIM4_CH3OUT) ||defined(GPIO_TIM4_CH4OUT) # define HAVE_TIM4_GPIOCONFIG 1 #endif #endif -#if defined(CONFIG_STM32F7_TIM5) +#if defined(CONFIG_STM32_TIM5) # if defined(GPIO_TIM5_CH1OUT) ||defined(GPIO_TIM5_CH2OUT)||\ defined(GPIO_TIM5_CH3OUT) ||defined(GPIO_TIM5_CH4OUT) # define HAVE_TIM5_GPIOCONFIG 1 #endif #endif -#if defined(CONFIG_STM32F7_TIM8) +#if defined(CONFIG_STM32_TIM8) # if defined(GPIO_TIM8_CH1OUT) ||defined(GPIO_TIM8_CH2OUT)||\ defined(GPIO_TIM8_CH3OUT) ||defined(GPIO_TIM8_CH4OUT) # define HAVE_TIM8_GPIOCONFIG 1 #endif #endif -#if defined(CONFIG_STM32F7_TIM9) +#if defined(CONFIG_STM32_TIM9) # if defined(GPIO_TIM9_CH1OUT) ||defined(GPIO_TIM9_CH2OUT)||\ defined(GPIO_TIM9_CH3OUT) ||defined(GPIO_TIM9_CH4OUT) # define HAVE_TIM9_GPIOCONFIG 1 #endif #endif -#if defined(CONFIG_STM32F7_TIM10) +#if defined(CONFIG_STM32_TIM10) # if defined(GPIO_TIM10_CH1OUT) ||defined(GPIO_TIM10_CH2OUT)||\ defined(GPIO_TIM10_CH3OUT) ||defined(GPIO_TIM10_CH4OUT) # define HAVE_TIM10_GPIOCONFIG 1 #endif #endif -#if defined(CONFIG_STM32F7_TIM11) +#if defined(CONFIG_STM32_TIM11) # if defined(GPIO_TIM11_CH1OUT) ||defined(GPIO_TIM11_CH2OUT)||\ defined(GPIO_TIM11_CH3OUT) ||defined(GPIO_TIM11_CH4OUT) # define HAVE_TIM11_GPIOCONFIG 1 #endif #endif -#if defined(CONFIG_STM32F7_TIM12) +#if defined(CONFIG_STM32_TIM12) # if defined(GPIO_TIM12_CH1OUT) ||defined(GPIO_TIM12_CH2OUT)||\ defined(GPIO_TIM12_CH3OUT) ||defined(GPIO_TIM12_CH4OUT) # define HAVE_TIM12_GPIOCONFIG 1 #endif #endif -#if defined(CONFIG_STM32F7_TIM13) +#if defined(CONFIG_STM32_TIM13) # if defined(GPIO_TIM13_CH1OUT) ||defined(GPIO_TIM13_CH2OUT)||\ defined(GPIO_TIM13_CH3OUT) ||defined(GPIO_TIM13_CH4OUT) # define HAVE_TIM13_GPIOCONFIG 1 #endif #endif -#if defined(CONFIG_STM32F7_TIM14) +#if defined(CONFIG_STM32_TIM14) # if defined(GPIO_TIM14_CH1OUT) ||defined(GPIO_TIM14_CH2OUT)||\ defined(GPIO_TIM14_CH3OUT) ||defined(GPIO_TIM14_CH4OUT) # define HAVE_TIM14_GPIOCONFIG 1 @@ -216,13 +216,13 @@ * intended for some other purpose. */ -#if defined(CONFIG_STM32F7_TIM1) || defined(CONFIG_STM32F7_TIM2) || \ - defined(CONFIG_STM32F7_TIM3) || defined(CONFIG_STM32F7_TIM4) || \ - defined(CONFIG_STM32F7_TIM5) || defined(CONFIG_STM32F7_TIM6) || \ - defined(CONFIG_STM32F7_TIM7) || defined(CONFIG_STM32F7_TIM8) || \ - defined(CONFIG_STM32F7_TIM9) || defined(CONFIG_STM32F7_TIM10) || \ - defined(CONFIG_STM32F7_TIM11) || defined(CONFIG_STM32F7_TIM12) || \ - defined(CONFIG_STM32F7_TIM13) || defined(CONFIG_STM32F7_TIM14) +#if defined(CONFIG_STM32_TIM1) || defined(CONFIG_STM32_TIM2) || \ + defined(CONFIG_STM32_TIM3) || defined(CONFIG_STM32_TIM4) || \ + defined(CONFIG_STM32_TIM5) || defined(CONFIG_STM32_TIM6) || \ + defined(CONFIG_STM32_TIM7) || defined(CONFIG_STM32_TIM8) || \ + defined(CONFIG_STM32_TIM9) || defined(CONFIG_STM32_TIM10) || \ + defined(CONFIG_STM32_TIM11) || defined(CONFIG_STM32_TIM12) || \ + defined(CONFIG_STM32_TIM13) || defined(CONFIG_STM32_TIM14) /**************************************************************************** * Private Types @@ -326,14 +326,14 @@ static int stm32_tim_getwidth(struct stm32_tim_dev_s *dev) { /* TIM2 is 32-bits on all except F10x, L0x, and L1x lines */ -#if defined(CONFIG_STM32F7_TIM2) +#if defined(CONFIG_STM32_TIM2) case STM32_TIM2_BASE: return 32; #endif /* TIM5 is 32-bits on all except F10x lines */ -#if defined(CONFIG_STM32F7_TIM5) +#if defined(CONFIG_STM32_TIM5) case STM32_TIM5_BASE: return 32; #endif @@ -431,72 +431,72 @@ static int stm32_tim_setclock(struct stm32_tim_dev_s *dev, uint32_t freq) switch (((struct stm32_tim_priv_s *)dev)->base) { -#ifdef CONFIG_STM32F7_TIM1 +#ifdef CONFIG_STM32_TIM1 case STM32_TIM1_BASE: freqin = STM32_APB2_TIM1_CLKIN; break; #endif -#ifdef CONFIG_STM32F7_TIM2 +#ifdef CONFIG_STM32_TIM2 case STM32_TIM2_BASE: freqin = STM32_APB1_TIM2_CLKIN; break; #endif -#ifdef CONFIG_STM32F7_TIM3 +#ifdef CONFIG_STM32_TIM3 case STM32_TIM3_BASE: freqin = STM32_APB1_TIM3_CLKIN; break; #endif -#ifdef CONFIG_STM32F7_TIM4 +#ifdef CONFIG_STM32_TIM4 case STM32_TIM4_BASE: freqin = STM32_APB1_TIM4_CLKIN; break; #endif -#ifdef CONFIG_STM32F7_TIM5 +#ifdef CONFIG_STM32_TIM5 case STM32_TIM5_BASE: freqin = STM32_APB1_TIM5_CLKIN; break; #endif -#ifdef CONFIG_STM32F7_TIM6 +#ifdef CONFIG_STM32_TIM6 case STM32_TIM6_BASE: freqin = STM32_APB1_TIM6_CLKIN; break; #endif -#ifdef CONFIG_STM32F7_TIM7 +#ifdef CONFIG_STM32_TIM7 case STM32_TIM7_BASE: freqin = STM32_APB1_TIM7_CLKIN; break; #endif -#ifdef CONFIG_STM32F7_TIM8 +#ifdef CONFIG_STM32_TIM8 case STM32_TIM8_BASE: freqin = STM32_APB2_TIM8_CLKIN; break; #endif -#ifdef CONFIG_STM32F7_TIM9 +#ifdef CONFIG_STM32_TIM9 case STM32_TIM9_BASE: freqin = STM32_APB2_TIM9_CLKIN; break; #endif -#ifdef CONFIG_STM32F7_TIM10 +#ifdef CONFIG_STM32_TIM10 case STM32_TIM10_BASE: freqin = STM32_APB2_TIM10_CLKIN; break; #endif -#ifdef CONFIG_STM32F7_TIM11 +#ifdef CONFIG_STM32_TIM11 case STM32_TIM11_BASE: freqin = STM32_APB2_TIM11_CLKIN; break; #endif -#ifdef CONFIG_STM32F7_TIM12 +#ifdef CONFIG_STM32_TIM12 case STM32_TIM12_BASE: freqin = STM32_APB1_TIM12_CLKIN; break; #endif -#ifdef CONFIG_STM32F7_TIM13 +#ifdef CONFIG_STM32_TIM13 case STM32_TIM13_BASE: freqin = STM32_APB1_TIM13_CLKIN; break; #endif -#ifdef CONFIG_STM32F7_TIM14 +#ifdef CONFIG_STM32_TIM14 case STM32_TIM14_BASE: freqin = STM32_APB1_TIM14_CLKIN; break; @@ -550,72 +550,72 @@ static int stm32_tim_setisr(struct stm32_tim_dev_s *dev, switch (((struct stm32_tim_priv_s *)dev)->base) { -#ifdef CONFIG_STM32F7_TIM1 +#ifdef CONFIG_STM32_TIM1 case STM32_TIM1_BASE: vectorno = STM32_IRQ_TIM1UP; break; #endif -#ifdef CONFIG_STM32F7_TIM2 +#ifdef CONFIG_STM32_TIM2 case STM32_TIM2_BASE: vectorno = STM32_IRQ_TIM2; break; #endif -#ifdef CONFIG_STM32F7_TIM3 +#ifdef CONFIG_STM32_TIM3 case STM32_TIM3_BASE: vectorno = STM32_IRQ_TIM3; break; #endif -#ifdef CONFIG_STM32F7_TIM4 +#ifdef CONFIG_STM32_TIM4 case STM32_TIM4_BASE: vectorno = STM32_IRQ_TIM4; break; #endif -#ifdef CONFIG_STM32F7_TIM5 +#ifdef CONFIG_STM32_TIM5 case STM32_TIM5_BASE: vectorno = STM32_IRQ_TIM5; break; #endif -#ifdef CONFIG_STM32F7_TIM6 +#ifdef CONFIG_STM32_TIM6 case STM32_TIM6_BASE: vectorno = STM32_IRQ_TIM6; break; #endif -#ifdef CONFIG_STM32F7_TIM7 +#ifdef CONFIG_STM32_TIM7 case STM32_TIM7_BASE: vectorno = STM32_IRQ_TIM7; break; #endif -#ifdef CONFIG_STM32F7_TIM8 +#ifdef CONFIG_STM32_TIM8 case STM32_TIM8_BASE: vectorno = STM32_IRQ_TIM8UP; break; #endif -#ifdef CONFIG_STM32F7_TIM9 +#ifdef CONFIG_STM32_TIM9 case STM32_TIM9_BASE: vectorno = STM32_IRQ_TIM9; break; #endif -#ifdef CONFIG_STM32F7_TIM10 +#ifdef CONFIG_STM32_TIM10 case STM32_TIM10_BASE: vectorno = STM32_IRQ_TIM10; break; #endif -#ifdef CONFIG_STM32F7_TIM11 +#ifdef CONFIG_STM32_TIM11 case STM32_TIM11_BASE: vectorno = STM32_IRQ_TIM11; break; #endif -#ifdef CONFIG_STM32F7_TIM12 +#ifdef CONFIG_STM32_TIM12 case STM32_TIM12_BASE: vectorno = STM32_IRQ_TIM12; break; #endif -#ifdef CONFIG_STM32F7_TIM13 +#ifdef CONFIG_STM32_TIM13 case STM32_TIM13_BASE: vectorno = STM32_IRQ_TIM13; break; #endif -#ifdef CONFIG_STM32F7_TIM14 +#ifdef CONFIG_STM32_TIM14 case STM32_TIM14_BASE: vectorno = STM32_IRQ_TIM14; break; @@ -818,7 +818,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, switch (((struct stm32_tim_priv_s *)dev)->base) { -#ifdef CONFIG_STM32F7_TIM1 +#ifdef CONFIG_STM32_TIM1 case STM32_TIM1_BASE: switch (channel) { @@ -843,7 +843,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32F7_TIM2 +#ifdef CONFIG_STM32_TIM2 case STM32_TIM2_BASE: switch (channel) { @@ -872,7 +872,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32F7_TIM3 +#ifdef CONFIG_STM32_TIM3 case STM32_TIM3_BASE: switch (channel) { @@ -901,7 +901,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32F7_TIM4 +#ifdef CONFIG_STM32_TIM4 case STM32_TIM4_BASE: switch (channel) { @@ -930,7 +930,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32F7_TIM5 +#ifdef CONFIG_STM32_TIM5 case STM32_TIM5_BASE: switch (channel) { @@ -959,7 +959,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32F7_TIM8 +#ifdef CONFIG_STM32_TIM8 case STM32_TIM8_BASE: switch (channel) { @@ -984,7 +984,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, } break; #endif -# ifdef CONFIG_STM32F7_TIM9 +# ifdef CONFIG_STM32_TIM9 case STM32_TIM9_BASE: switch (channel) { @@ -1013,7 +1013,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32F7_TIM10 +#ifdef CONFIG_STM32_TIM10 case STM32_TIM10_BASE: switch (channel) { @@ -1042,7 +1042,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32F7_TIM11 +#ifdef CONFIG_STM32_TIM11 case STM32_TIM11_BASE: switch (channel) { @@ -1071,7 +1071,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32F7_TIM12 +#ifdef CONFIG_STM32_TIM12 case STM32_TIM12_BASE: switch (channel) { @@ -1100,7 +1100,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32F7_TIM13 +#ifdef CONFIG_STM32_TIM13 case STM32_TIM13_BASE: switch (channel) { @@ -1129,7 +1129,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32F7_TIM14 +#ifdef CONFIG_STM32_TIM14 case STM32_TIM14_BASE: switch (channel) { @@ -1240,7 +1240,7 @@ struct stm32_tim_ops_s stm32_tim_ops = .checkint = stm32_tim_checkint, }; -#ifdef CONFIG_STM32F7_TIM1 +#ifdef CONFIG_STM32_TIM1 struct stm32_tim_priv_s stm32_tim1_priv = { .ops = &stm32_tim_ops, @@ -1249,7 +1249,7 @@ struct stm32_tim_priv_s stm32_tim1_priv = }; #endif -#ifdef CONFIG_STM32F7_TIM2 +#ifdef CONFIG_STM32_TIM2 struct stm32_tim_priv_s stm32_tim2_priv = { .ops = &stm32_tim_ops, @@ -1258,7 +1258,7 @@ struct stm32_tim_priv_s stm32_tim2_priv = }; #endif -#ifdef CONFIG_STM32F7_TIM3 +#ifdef CONFIG_STM32_TIM3 struct stm32_tim_priv_s stm32_tim3_priv = { .ops = &stm32_tim_ops, @@ -1267,7 +1267,7 @@ struct stm32_tim_priv_s stm32_tim3_priv = }; #endif -#ifdef CONFIG_STM32F7_TIM4 +#ifdef CONFIG_STM32_TIM4 struct stm32_tim_priv_s stm32_tim4_priv = { .ops = &stm32_tim_ops, @@ -1276,7 +1276,7 @@ struct stm32_tim_priv_s stm32_tim4_priv = }; #endif -#ifdef CONFIG_STM32F7_TIM5 +#ifdef CONFIG_STM32_TIM5 struct stm32_tim_priv_s stm32_tim5_priv = { .ops = &stm32_tim_ops, @@ -1285,7 +1285,7 @@ struct stm32_tim_priv_s stm32_tim5_priv = }; #endif -#ifdef CONFIG_STM32F7_TIM6 +#ifdef CONFIG_STM32_TIM6 struct stm32_tim_priv_s stm32_tim6_priv = { .ops = &stm32_tim_ops, @@ -1294,7 +1294,7 @@ struct stm32_tim_priv_s stm32_tim6_priv = }; #endif -#ifdef CONFIG_STM32F7_TIM7 +#ifdef CONFIG_STM32_TIM7 struct stm32_tim_priv_s stm32_tim7_priv = { .ops = &stm32_tim_ops, @@ -1303,7 +1303,7 @@ struct stm32_tim_priv_s stm32_tim7_priv = }; #endif -#ifdef CONFIG_STM32F7_TIM8 +#ifdef CONFIG_STM32_TIM8 struct stm32_tim_priv_s stm32_tim8_priv = { .ops = &stm32_tim_ops, @@ -1312,7 +1312,7 @@ struct stm32_tim_priv_s stm32_tim8_priv = }; #endif -#ifdef CONFIG_STM32F7_TIM9 +#ifdef CONFIG_STM32_TIM9 struct stm32_tim_priv_s stm32_tim9_priv = { .ops = &stm32_tim_ops, @@ -1321,7 +1321,7 @@ struct stm32_tim_priv_s stm32_tim9_priv = }; #endif -#ifdef CONFIG_STM32F7_TIM10 +#ifdef CONFIG_STM32_TIM10 struct stm32_tim_priv_s stm32_tim10_priv = { .ops = &stm32_tim_ops, @@ -1330,7 +1330,7 @@ struct stm32_tim_priv_s stm32_tim10_priv = }; #endif -#ifdef CONFIG_STM32F7_TIM11 +#ifdef CONFIG_STM32_TIM11 struct stm32_tim_priv_s stm32_tim11_priv = { .ops = &stm32_tim_ops, @@ -1339,7 +1339,7 @@ struct stm32_tim_priv_s stm32_tim11_priv = }; #endif -#ifdef CONFIG_STM32F7_TIM12 +#ifdef CONFIG_STM32_TIM12 struct stm32_tim_priv_s stm32_tim12_priv = { .ops = &stm32_tim_ops, @@ -1348,7 +1348,7 @@ struct stm32_tim_priv_s stm32_tim12_priv = }; #endif -#ifdef CONFIG_STM32F7_TIM13 +#ifdef CONFIG_STM32_TIM13 struct stm32_tim_priv_s stm32_tim13_priv = { .ops = &stm32_tim_ops, @@ -1357,7 +1357,7 @@ struct stm32_tim_priv_s stm32_tim13_priv = }; #endif -#ifdef CONFIG_STM32F7_TIM14 +#ifdef CONFIG_STM32_TIM14 struct stm32_tim_priv_s stm32_tim14_priv = { .ops = &stm32_tim_ops, @@ -1378,85 +1378,85 @@ struct stm32_tim_dev_s *stm32_tim_init(int timer) switch (timer) { -#ifdef CONFIG_STM32F7_TIM1 +#ifdef CONFIG_STM32_TIM1 case 1: dev = (struct stm32_tim_dev_s *)&stm32_tim1_priv; modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM1EN); break; #endif -#ifdef CONFIG_STM32F7_TIM2 +#ifdef CONFIG_STM32_TIM2 case 2: dev = (struct stm32_tim_dev_s *)&stm32_tim2_priv; modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM2EN); break; #endif -#ifdef CONFIG_STM32F7_TIM3 +#ifdef CONFIG_STM32_TIM3 case 3: dev = (struct stm32_tim_dev_s *)&stm32_tim3_priv; modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM3EN); break; #endif -#ifdef CONFIG_STM32F7_TIM4 +#ifdef CONFIG_STM32_TIM4 case 4: dev = (struct stm32_tim_dev_s *)&stm32_tim4_priv; modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM4EN); break; #endif -#ifdef CONFIG_STM32F7_TIM5 +#ifdef CONFIG_STM32_TIM5 case 5: dev = (struct stm32_tim_dev_s *)&stm32_tim5_priv; modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM5EN); break; #endif -#ifdef CONFIG_STM32F7_TIM6 +#ifdef CONFIG_STM32_TIM6 case 6: dev = (struct stm32_tim_dev_s *)&stm32_tim6_priv; modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM6EN); break; #endif -#ifdef CONFIG_STM32F7_TIM7 +#ifdef CONFIG_STM32_TIM7 case 7: dev = (struct stm32_tim_dev_s *)&stm32_tim7_priv; modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM7EN); break; #endif -#ifdef CONFIG_STM32F7_TIM8 +#ifdef CONFIG_STM32_TIM8 case 8: dev = (struct stm32_tim_dev_s *)&stm32_tim8_priv; modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM8EN); break; #endif -#ifdef CONFIG_STM32F7_TIM9 +#ifdef CONFIG_STM32_TIM9 case 9: dev = (struct stm32_tim_dev_s *)&stm32_tim9_priv; modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM9EN); break; #endif -#ifdef CONFIG_STM32F7_TIM10 +#ifdef CONFIG_STM32_TIM10 case 10: dev = (struct stm32_tim_dev_s *)&stm32_tim10_priv; modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM10EN); break; #endif -#ifdef CONFIG_STM32F7_TIM11 +#ifdef CONFIG_STM32_TIM11 case 11: dev = (struct stm32_tim_dev_s *)&stm32_tim11_priv; modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM11EN); break; #endif -#ifdef CONFIG_STM32F7_TIM12 +#ifdef CONFIG_STM32_TIM12 case 12: dev = (struct stm32_tim_dev_s *)&stm32_tim12_priv; modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM12EN); break; #endif -#ifdef CONFIG_STM32F7_TIM13 +#ifdef CONFIG_STM32_TIM13 case 13: dev = (struct stm32_tim_dev_s *)&stm32_tim13_priv; modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM13EN); break; #endif -#ifdef CONFIG_STM32F7_TIM14 +#ifdef CONFIG_STM32_TIM14 case 14: dev = (struct stm32_tim_dev_s *)&stm32_tim14_priv; modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM14EN); @@ -1488,72 +1488,72 @@ int stm32_tim_deinit(struct stm32_tim_dev_s * dev) switch (((struct stm32_tim_priv_s *)dev)->base) { -#ifdef CONFIG_STM32F7_TIM1 +#ifdef CONFIG_STM32_TIM1 case STM32_TIM1_BASE: modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM1EN, 0); break; #endif -#ifdef CONFIG_STM32F7_TIM2 +#ifdef CONFIG_STM32_TIM2 case STM32_TIM2_BASE: modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM2EN, 0); break; #endif -#ifdef CONFIG_STM32F7_TIM3 +#ifdef CONFIG_STM32_TIM3 case STM32_TIM3_BASE: modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM3EN, 0); break; #endif -#ifdef CONFIG_STM32F7_TIM4 +#ifdef CONFIG_STM32_TIM4 case STM32_TIM4_BASE: modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM4EN, 0); break; #endif -#ifdef CONFIG_STM32F7_TIM5 +#ifdef CONFIG_STM32_TIM5 case STM32_TIM5_BASE: modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM5EN, 0); break; #endif -#ifdef CONFIG_STM32F7_TIM6 +#ifdef CONFIG_STM32_TIM6 case STM32_TIM6_BASE: modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM6EN, 0); break; #endif -#ifdef CONFIG_STM32F7_TIM7 +#ifdef CONFIG_STM32_TIM7 case STM32_TIM7_BASE: modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM7EN, 0); break; #endif -#ifdef CONFIG_STM32F7_TIM8 +#ifdef CONFIG_STM32_TIM8 case STM32_TIM8_BASE: modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM8EN, 0); break; #endif -#ifdef CONFIG_STM32F7_TIM9 +#ifdef CONFIG_STM32_TIM9 case STM32_TIM9_BASE: modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM9EN, 0); break; #endif -#ifdef CONFIG_STM32F7_TIM10 +#ifdef CONFIG_STM32_TIM10 case STM32_TIM10_BASE: modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM10EN, 0); break; #endif -#ifdef CONFIG_STM32F7_TIM11 +#ifdef CONFIG_STM32_TIM11 case STM32_TIM11_BASE: modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM11EN, 0); break; #endif -#ifdef CONFIG_STM32F7_TIM12 +#ifdef CONFIG_STM32_TIM12 case STM32_TIM12_BASE: modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM12EN, 0); break; #endif -#ifdef CONFIG_STM32F7_TIM13 +#ifdef CONFIG_STM32_TIM13 case STM32_TIM13_BASE: modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM13EN, 0); break; #endif -#ifdef CONFIG_STM32F7_TIM14 +#ifdef CONFIG_STM32_TIM14 case STM32_TIM14_BASE: modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM14EN, 0); break; @@ -1569,4 +1569,4 @@ int stm32_tim_deinit(struct stm32_tim_dev_s * dev) return OK; } -#endif /* defined(CONFIG_STM32F7_TIM1 || ... || TIM8) */ +#endif /* defined(CONFIG_STM32_TIM1 || ... || TIM8) */ diff --git a/arch/arm/src/stm32f7/stm32_tim_lowerhalf.c b/arch/arm/src/stm32f7/stm32_tim_lowerhalf.c index f0f5dda38f092..1005d174f7569 100644 --- a/arch/arm/src/stm32f7/stm32_tim_lowerhalf.c +++ b/arch/arm/src/stm32f7/stm32_tim_lowerhalf.c @@ -56,13 +56,13 @@ #include "stm32_tim.h" #if defined(CONFIG_TIMER) && \ - (defined(CONFIG_STM32F7_TIM1) || defined(CONFIG_STM32F7_TIM2) || \ - defined(CONFIG_STM32F7_TIM3) || defined(CONFIG_STM32F7_TIM4) || \ - defined(CONFIG_STM32F7_TIM5) || defined(CONFIG_STM32F7_TIM6) || \ - defined(CONFIG_STM32F7_TIM7) || defined(CONFIG_STM32F7_TIM8) || \ - defined(CONFIG_STM32F7_TIM9) || defined(CONFIG_STM32F7_TIM10) || \ - defined(CONFIG_STM32F7_TIM11) || defined(CONFIG_STM32F7_TIM12) || \ - defined(CONFIG_STM32F7_TIM13) || defined(CONFIG_STM32F7_TIM14)) + (defined(CONFIG_STM32_TIM1) || defined(CONFIG_STM32_TIM2) || \ + defined(CONFIG_STM32_TIM3) || defined(CONFIG_STM32_TIM4) || \ + defined(CONFIG_STM32_TIM5) || defined(CONFIG_STM32_TIM6) || \ + defined(CONFIG_STM32_TIM7) || defined(CONFIG_STM32_TIM8) || \ + defined(CONFIG_STM32_TIM9) || defined(CONFIG_STM32_TIM10) || \ + defined(CONFIG_STM32_TIM11) || defined(CONFIG_STM32_TIM12) || \ + defined(CONFIG_STM32_TIM13) || defined(CONFIG_STM32_TIM14)) /**************************************************************************** * Pre-processor Definitions @@ -144,7 +144,7 @@ static const struct timer_ops_s g_timer_ops = .ioctl = NULL, }; -#ifdef CONFIG_STM32F7_TIM1 +#ifdef CONFIG_STM32_TIM1 static struct stm32_lowerhalf_s g_tim1_lowerhalf = { .ops = &g_timer_ops, @@ -152,7 +152,7 @@ static struct stm32_lowerhalf_s g_tim1_lowerhalf = }; #endif -#ifdef CONFIG_STM32F7_TIM2 +#ifdef CONFIG_STM32_TIM2 static struct stm32_lowerhalf_s g_tim2_lowerhalf = { .ops = &g_timer_ops, @@ -160,7 +160,7 @@ static struct stm32_lowerhalf_s g_tim2_lowerhalf = }; #endif -#ifdef CONFIG_STM32F7_TIM3 +#ifdef CONFIG_STM32_TIM3 static struct stm32_lowerhalf_s g_tim3_lowerhalf = { .ops = &g_timer_ops, @@ -168,7 +168,7 @@ static struct stm32_lowerhalf_s g_tim3_lowerhalf = }; #endif -#ifdef CONFIG_STM32F7_TIM4 +#ifdef CONFIG_STM32_TIM4 static struct stm32_lowerhalf_s g_tim4_lowerhalf = { .ops = &g_timer_ops, @@ -176,7 +176,7 @@ static struct stm32_lowerhalf_s g_tim4_lowerhalf = }; #endif -#ifdef CONFIG_STM32F7_TIM5 +#ifdef CONFIG_STM32_TIM5 static struct stm32_lowerhalf_s g_tim5_lowerhalf = { .ops = &g_timer_ops, @@ -184,7 +184,7 @@ static struct stm32_lowerhalf_s g_tim5_lowerhalf = }; #endif -#ifdef CONFIG_STM32F7_TIM6 +#ifdef CONFIG_STM32_TIM6 static struct stm32_lowerhalf_s g_tim6_lowerhalf = { .ops = &g_timer_ops, @@ -192,7 +192,7 @@ static struct stm32_lowerhalf_s g_tim6_lowerhalf = }; #endif -#ifdef CONFIG_STM32F7_TIM7 +#ifdef CONFIG_STM32_TIM7 static struct stm32_lowerhalf_s g_tim7_lowerhalf = { .ops = &g_timer_ops, @@ -200,7 +200,7 @@ static struct stm32_lowerhalf_s g_tim7_lowerhalf = }; #endif -#ifdef CONFIG_STM32F7_TIM8 +#ifdef CONFIG_STM32_TIM8 static struct stm32_lowerhalf_s g_tim8_lowerhalf = { .ops = &g_timer_ops, @@ -208,7 +208,7 @@ static struct stm32_lowerhalf_s g_tim8_lowerhalf = }; #endif -#ifdef CONFIG_STM32F7_TIM9 +#ifdef CONFIG_STM32_TIM9 static struct stm32_lowerhalf_s g_tim9_lowerhalf = { .ops = &g_timer_ops, @@ -216,7 +216,7 @@ static struct stm32_lowerhalf_s g_tim9_lowerhalf = }; #endif -#ifdef CONFIG_STM32F7_TIM10 +#ifdef CONFIG_STM32_TIM10 static struct stm32_lowerhalf_s g_tim10_lowerhalf = { .ops = &g_timer_ops, @@ -224,7 +224,7 @@ static struct stm32_lowerhalf_s g_tim10_lowerhalf = }; #endif -#ifdef CONFIG_STM32F7_TIM11 +#ifdef CONFIG_STM32_TIM11 static struct stm32_lowerhalf_s g_tim11_lowerhalf = { .ops = &g_timer_ops, @@ -232,7 +232,7 @@ static struct stm32_lowerhalf_s g_tim11_lowerhalf = }; #endif -#ifdef CONFIG_STM32F7_TIM12 +#ifdef CONFIG_STM32_TIM12 static struct stm32_lowerhalf_s g_tim12_lowerhalf = { .ops = &g_timer_ops, @@ -240,7 +240,7 @@ static struct stm32_lowerhalf_s g_tim12_lowerhalf = }; #endif -#ifdef CONFIG_STM32F7_TIM13 +#ifdef CONFIG_STM32_TIM13 static struct stm32_lowerhalf_s g_tim13_lowerhalf = { .ops = &g_timer_ops, @@ -248,7 +248,7 @@ static struct stm32_lowerhalf_s g_tim13_lowerhalf = }; #endif -#ifdef CONFIG_STM32F7_TIM14 +#ifdef CONFIG_STM32_TIM14 static struct stm32_lowerhalf_s g_tim14_lowerhalf = { .ops = &g_timer_ops, @@ -482,72 +482,72 @@ int stm32_timer_initialize(const char *devpath, int timer) switch (timer) { -#ifdef CONFIG_STM32F7_TIM1 +#ifdef CONFIG_STM32_TIM1 case 1: lower = &g_tim1_lowerhalf; break; #endif -#ifdef CONFIG_STM32F7_TIM2 +#ifdef CONFIG_STM32_TIM2 case 2: lower = &g_tim2_lowerhalf; break; #endif -#ifdef CONFIG_STM32F7_TIM3 +#ifdef CONFIG_STM32_TIM3 case 3: lower = &g_tim3_lowerhalf; break; #endif -#ifdef CONFIG_STM32F7_TIM4 +#ifdef CONFIG_STM32_TIM4 case 4: lower = &g_tim4_lowerhalf; break; #endif -#ifdef CONFIG_STM32F7_TIM5 +#ifdef CONFIG_STM32_TIM5 case 5: lower = &g_tim5_lowerhalf; break; #endif -#ifdef CONFIG_STM32F7_TIM6 +#ifdef CONFIG_STM32_TIM6 case 6: lower = &g_tim6_lowerhalf; break; #endif -#ifdef CONFIG_STM32F7_TIM7 +#ifdef CONFIG_STM32_TIM7 case 7: lower = &g_tim7_lowerhalf; break; #endif -#ifdef CONFIG_STM32F7_TIM8 +#ifdef CONFIG_STM32_TIM8 case 8: lower = &g_tim8_lowerhalf; break; #endif -#ifdef CONFIG_STM32F7_TIM9 +#ifdef CONFIG_STM32_TIM9 case 9: lower = &g_tim9_lowerhalf; break; #endif -#ifdef CONFIG_STM32F7_TIM10 +#ifdef CONFIG_STM32_TIM10 case 10: lower = &g_tim10_lowerhalf; break; #endif -#ifdef CONFIG_STM32F7_TIM11 +#ifdef CONFIG_STM32_TIM11 case 11: lower = &g_tim11_lowerhalf; break; #endif -#ifdef CONFIG_STM32F7_TIM12 +#ifdef CONFIG_STM32_TIM12 case 12: lower = &g_tim12_lowerhalf; break; #endif -#ifdef CONFIG_STM32F7_TIM13 +#ifdef CONFIG_STM32_TIM13 case 13: lower = &g_tim13_lowerhalf; break; #endif -#ifdef CONFIG_STM32F7_TIM14 +#ifdef CONFIG_STM32_TIM14 case 14: lower = &g_tim14_lowerhalf; break; diff --git a/arch/arm/src/stm32f7/stm32_uart.h b/arch/arm/src/stm32f7/stm32_uart.h index 447a020e51f6d..e3f555f43ad5d 100644 --- a/arch/arm/src/stm32f7/stm32_uart.h +++ b/arch/arm/src/stm32f7/stm32_uart.h @@ -40,44 +40,44 @@ * device. */ -#if STM32F7_NUART < 4 -# undef CONFIG_STM32F7_UART8 +#if STM32_NUART < 4 +# undef CONFIG_STM32_UART8 #endif -#if STM32F7_NUART < 3 -# undef CONFIG_STM32F7_UART7 +#if STM32_NUART < 3 +# undef CONFIG_STM32_UART7 #endif -#if STM32F7_NUART < 2 -# undef CONFIG_STM32F7_UART5 +#if STM32_NUART < 2 +# undef CONFIG_STM32_UART5 #endif -#if STM32F7_NUART < 1 -# undef CONFIG_STM32F7_UART4 +#if STM32_NUART < 1 +# undef CONFIG_STM32_UART4 #endif -#if STM32F7_NUSART < 4 -# undef CONFIG_STM32F7_USART6 +#if STM32_NUSART < 4 +# undef CONFIG_STM32_USART6 #endif -#if STM32F7_NUSART < 3 -# undef CONFIG_STM32F7_USART3 +#if STM32_NUSART < 3 +# undef CONFIG_STM32_USART3 #endif -#if STM32F7_NUSART < 2 -# undef CONFIG_STM32F7_USART2 +#if STM32_NUSART < 2 +# undef CONFIG_STM32_USART2 #endif -#if STM32F7_NUSART < 1 -# undef CONFIG_STM32F7_USART1 +#if STM32_NUSART < 1 +# undef CONFIG_STM32_USART1 #endif /* Is there a USART enabled? */ -#if defined(CONFIG_STM32F7_USART1) || defined(CONFIG_STM32F7_USART2) || \ - defined(CONFIG_STM32F7_USART3) || defined(CONFIG_STM32F7_UART4) || \ - defined(CONFIG_STM32F7_UART5) || defined(CONFIG_STM32F7_USART6) || \ - defined(CONFIG_STM32F7_UART7) || defined(CONFIG_STM32F7_UART8) +#if defined(CONFIG_STM32_USART1) || defined(CONFIG_STM32_USART2) || \ + defined(CONFIG_STM32_USART3) || defined(CONFIG_STM32_UART4) || \ + defined(CONFIG_STM32_UART5) || defined(CONFIG_STM32_USART6) || \ + defined(CONFIG_STM32_UART7) || defined(CONFIG_STM32_UART8) # define HAVE_UART 1 #endif /* Is there a serial console? */ -#if defined(CONFIG_USART1_SERIAL_CONSOLE) && defined(CONFIG_STM32F7_USART1) +#if defined(CONFIG_USART1_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART1) # undef CONFIG_USART2_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE # undef CONFIG_UART4_SERIAL_CONSOLE @@ -87,7 +87,7 @@ # undef CONFIG_UART8_SERIAL_CONSOLE # define CONSOLE_UART 1 # define HAVE_CONSOLE 1 -#elif defined(CONFIG_USART2_SERIAL_CONSOLE) && defined(CONFIG_STM32F7_USART2) +#elif defined(CONFIG_USART2_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART2) # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE # undef CONFIG_UART4_SERIAL_CONSOLE @@ -97,7 +97,7 @@ # undef CONFIG_UART8_SERIAL_CONSOLE # define CONSOLE_UART 2 # define HAVE_CONSOLE 1 -#elif defined(CONFIG_USART3_SERIAL_CONSOLE) && defined(CONFIG_STM32F7_USART3) +#elif defined(CONFIG_USART3_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART3) # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # undef CONFIG_UART4_SERIAL_CONSOLE @@ -107,7 +107,7 @@ # undef CONFIG_UART8_SERIAL_CONSOLE # define CONSOLE_UART 3 # define HAVE_CONSOLE 1 -#elif defined(CONFIG_UART4_SERIAL_CONSOLE) && defined(CONFIG_STM32F7_UART4) +#elif defined(CONFIG_UART4_SERIAL_CONSOLE) && defined(CONFIG_STM32_UART4) # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE @@ -117,7 +117,7 @@ # undef CONFIG_UART8_SERIAL_CONSOLE # define CONSOLE_UART 4 # define HAVE_CONSOLE 1 -#elif defined(CONFIG_UART5_SERIAL_CONSOLE) && defined(CONFIG_STM32F7_UART5) +#elif defined(CONFIG_UART5_SERIAL_CONSOLE) && defined(CONFIG_STM32_UART5) # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE @@ -127,7 +127,7 @@ # undef CONFIG_UART8_SERIAL_CONSOLE # define CONSOLE_UART 5 # define HAVE_CONSOLE 1 -#elif defined(CONFIG_USART6_SERIAL_CONSOLE) && defined(CONFIG_STM32F7_USART6) +#elif defined(CONFIG_USART6_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART6) # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE @@ -137,7 +137,7 @@ # undef CONFIG_UART8_SERIAL_CONSOLE # define CONSOLE_UART 6 # define HAVE_CONSOLE 1 -#elif defined(CONFIG_UART7_SERIAL_CONSOLE) && defined(CONFIG_STM32F7_UART7) +#elif defined(CONFIG_UART7_SERIAL_CONSOLE) && defined(CONFIG_STM32_UART7) # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE @@ -147,7 +147,7 @@ # undef CONFIG_UART8_SERIAL_CONSOLE # define CONSOLE_UART 7 # define HAVE_CONSOLE 1 -#elif defined(CONFIG_UART8_SERIAL_CONSOLE) && defined(CONFIG_STM32F7_UART8) +#elif defined(CONFIG_UART8_SERIAL_CONSOLE) && defined(CONFIG_STM32_UART8) # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE @@ -195,42 +195,42 @@ /* Disable the DMA configuration on all unused USARTs */ -#ifndef CONFIG_STM32F7_USART1 +#ifndef CONFIG_STM32_USART1 # undef CONFIG_USART1_RXDMA # undef CONFIG_USART1_TXDMA #endif -#ifndef CONFIG_STM32F7_USART2 +#ifndef CONFIG_STM32_USART2 # undef CONFIG_USART2_RXDMA # undef CONFIG_USART2_TXDMA #endif -#ifndef CONFIG_STM32F7_USART3 +#ifndef CONFIG_STM32_USART3 # undef CONFIG_USART3_RXDMA # undef CONFIG_USART3_TXDMA #endif -#ifndef CONFIG_STM32F7_UART4 +#ifndef CONFIG_STM32_UART4 # undef CONFIG_UART4_RXDMA # undef CONFIG_UART4_TXDMA #endif -#ifndef CONFIG_STM32F7_UART5 +#ifndef CONFIG_STM32_UART5 # undef CONFIG_UART5_RXDMA # undef CONFIG_UART5_TXDMA #endif -#ifndef CONFIG_STM32F7_USART6 +#ifndef CONFIG_STM32_USART6 # undef CONFIG_USART6_RXDMA # undef CONFIG_USART6_TXDMA #endif -#ifndef CONFIG_STM32F7_UART7 +#ifndef CONFIG_STM32_UART7 # undef CONFIG_UART7_RXDMA # undef CONFIG_UART7_TXDMA #endif -#ifndef CONFIG_STM32F7_UART8 +#ifndef CONFIG_STM32_UART8 # undef CONFIG_UART8_RXDMA # undef CONFIG_UART8_TXDMA #endif @@ -300,42 +300,42 @@ /* Is RX DMA used on all (enabled) USARTs */ #define SERIAL_HAVE_ONLY_RXDMA 1 -#if defined(CONFIG_STM32F7_USART1) && !defined(CONFIG_USART1_RXDMA) +#if defined(CONFIG_STM32_USART1) && !defined(CONFIG_USART1_RXDMA) # undef SERIAL_HAVE_ONLY_RXDMA -#elif defined(CONFIG_STM32F7_USART2) && !defined(CONFIG_USART2_RXDMA) +#elif defined(CONFIG_STM32_USART2) && !defined(CONFIG_USART2_RXDMA) # undef SERIAL_HAVE_ONLY_RXDMA -#elif defined(CONFIG_STM32F7_USART3) && !defined(CONFIG_USART3_RXDMA) +#elif defined(CONFIG_STM32_USART3) && !defined(CONFIG_USART3_RXDMA) # undef SERIAL_HAVE_ONLY_RXDMA -#elif defined(CONFIG_STM32F7_UART4) && !defined(CONFIG_UART4_RXDMA) +#elif defined(CONFIG_STM32_UART4) && !defined(CONFIG_UART4_RXDMA) # undef SERIAL_HAVE_ONLY_RXDMA -#elif defined(CONFIG_STM32F7_UART5) && !defined(CONFIG_UART5_RXDMA) +#elif defined(CONFIG_STM32_UART5) && !defined(CONFIG_UART5_RXDMA) # undef SERIAL_HAVE_ONLY_RXDMA -#elif defined(CONFIG_STM32F7_USART6) && !defined(CONFIG_USART6_RXDMA) +#elif defined(CONFIG_STM32_USART6) && !defined(CONFIG_USART6_RXDMA) # undef SERIAL_HAVE_ONLY_RXDMA -#elif defined(CONFIG_STM32F7_UART7) && !defined(CONFIG_UART7_RXDMA) +#elif defined(CONFIG_STM32_UART7) && !defined(CONFIG_UART7_RXDMA) # undef SERIAL_HAVE_ONLY_RXDMA -#elif defined(CONFIG_STM32F7_UART8) && !defined(CONFIG_UART8_RXDMA) +#elif defined(CONFIG_STM32_UART8) && !defined(CONFIG_UART8_RXDMA) # undef SERIAL_HAVE_ONLY_RXDMA #endif /* Is TX DMA used on all (enabled) USARTs */ #define SERIAL_HAVE_ONLY_TXDMA 1 -#if defined(CONFIG_STM32F7_USART1) && !defined(CONFIG_USART1_TXDMA) +#if defined(CONFIG_STM32_USART1) && !defined(CONFIG_USART1_TXDMA) # undef SERIAL_HAVE_ONLY_TXDMA -#elif defined(CONFIG_STM32F7_USART2) && !defined(CONFIG_USART2_TXDMA) +#elif defined(CONFIG_STM32_USART2) && !defined(CONFIG_USART2_TXDMA) # undef SERIAL_HAVE_ONLY_TXDMA -#elif defined(CONFIG_STM32F7_USART3) && !defined(CONFIG_USART3_TXDMA) +#elif defined(CONFIG_STM32_USART3) && !defined(CONFIG_USART3_TXDMA) # undef SERIAL_HAVE_ONLY_TXDMA -#elif defined(CONFIG_STM32F7_UART4) && !defined(CONFIG_UART4_TXDMA) +#elif defined(CONFIG_STM32_UART4) && !defined(CONFIG_UART4_TXDMA) # undef SERIAL_HAVE_ONLY_TXDMA -#elif defined(CONFIG_STM32F7_UART5) && !defined(CONFIG_UART5_TXDMA) +#elif defined(CONFIG_STM32_UART5) && !defined(CONFIG_UART5_TXDMA) # undef SERIAL_HAVE_ONLY_TXDMA -#elif defined(CONFIG_STM32F7_USART6) && !defined(CONFIG_USART6_TXDMA) +#elif defined(CONFIG_STM32_USART6) && !defined(CONFIG_USART6_TXDMA) # undef SERIAL_HAVE_ONLY_TXDMA -#elif defined(CONFIG_STM32F7_UART7) && !defined(CONFIG_UART7_TXDMA) +#elif defined(CONFIG_STM32_UART7) && !defined(CONFIG_UART7_TXDMA) # undef SERIAL_HAVE_ONLY_TXDMA -#elif defined(CONFIG_STM32F7_UART8) && !defined(CONFIG_UART8_TXDMA) +#elif defined(CONFIG_STM32_UART8) && !defined(CONFIG_UART8_TXDMA) # undef SERIAL_HAVE_ONLY_TXDMA #endif diff --git a/arch/arm/src/stm32f7/stm32_uid.c b/arch/arm/src/stm32f7/stm32_uid.c deleted file mode 100644 index e1f64404cd856..0000000000000 --- a/arch/arm/src/stm32f7/stm32_uid.c +++ /dev/null @@ -1,63 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32f7/stm32_uid.c - * - * SPDX-License-Identifier: BSD-3-Clause - * SPDX-FileCopyrightText: 2015 Marawan Ragab. All rights reserved. - * SPDX-FileContributor: Marawan Ragab - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "hardware/stm32_memorymap.h" - -#include "stm32_uid.h" - -#ifdef STM32_SYSMEM_UID - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -void stm32_get_uniqueid(uint8_t uniqueid[12]) -{ - int i; - - for (i = 0; i < 12; i++) - { - uniqueid[i] = *((uint8_t *)(STM32_SYSMEM_UID) + i); - } -} - -#endif /* STM32_SYSMEM_UID */ diff --git a/arch/arm/src/stm32f7/stm32_uid.h b/arch/arm/src/stm32f7/stm32_uid.h deleted file mode 100644 index 8e92f0219a7aa..0000000000000 --- a/arch/arm/src/stm32f7/stm32_uid.h +++ /dev/null @@ -1,52 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32f7/stm32_uid.h - * - * SPDX-License-Identifier: BSD-3-Clause - * SPDX-FileCopyrightText: 2015 Marawan Ragab. All rights reserved. - * SPDX-FileContributor: Marawan Ragab - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32F7_STM32_UID_H -#define __ARCH_ARM_SRC_STM32F7_STM32_UID_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -void stm32_get_uniqueid(uint8_t uniqueid[12]); - -#endif /* __ARCH_ARM_SRC_STM32F7_STM32_UID_H */ diff --git a/arch/arm/src/stm32f7/stm32_usbhost.h b/arch/arm/src/stm32f7/stm32_usbhost.h index 7ae4f8e9d2536..6a1500043ae06 100644 --- a/arch/arm/src/stm32f7/stm32_usbhost.h +++ b/arch/arm/src/stm32f7/stm32_usbhost.h @@ -28,23 +28,23 @@ * Pre-requisites * * CONFIG_USBHOST - Enable general USB host support - * CONFIG_STM32F7_OTGFS - Enable the STM32 USB OTG FS block + * CONFIG_STM32_OTGFS - Enable the STM32 USB OTG FS block * or - * CONFIG_STM32F7_OTGFSHS - Enable the STM32 USB OTG HS block - * CONFIG_STM32F7_SYSCFG - Needed + * CONFIG_STM32_OTGFSHS - Enable the STM32 USB OTG HS block + * CONFIG_STM32_SYSCFG - Needed * * Options: * - * CONFIG_STM32F7_OTG_RXFIFO_SIZE - Size of the RX FIFO in 32-bit words. + * CONFIG_STM32_OTG_RXFIFO_SIZE - Size of the RX FIFO in 32-bit words. * Default 128 (512 bytes) - * CONFIG_STM32F7_OTG_NPTXFIFO_SIZE - Size of the non-periodic Tx FIFO + * CONFIG_STM32_OTG_NPTXFIFO_SIZE - Size of the non-periodic Tx FIFO * in 32-bit words. Default 96 (384 bytes) - * CONFIG_STM32F7_OTG_PTXFIFO_SIZE - Size of the periodic Tx FIFO in 32-bit + * CONFIG_STM32_OTG_PTXFIFO_SIZE - Size of the periodic Tx FIFO in 32-bit * words. Default 96 (384 bytes) - * CONFIG_STM32F7_OTG_SOFINTR - Enable SOF interrupts. Why would you ever + * CONFIG_STM32_OTG_SOFINTR - Enable SOF interrupts. Why would you ever * want to do that? * - * CONFIG_STM32F7_USBHOST_REGDEBUG - Enable very low-level register access + * CONFIG_STM32_USBHOST_REGDEBUG - Enable very low-level register access * debug. Depends on CONFIG_DEBUG_FEATURES. */ @@ -58,7 +58,7 @@ #include #include -#if (defined(CONFIG_STM32F7_OTGFS) || defined(CONFIG_STM32F7_OTGFSHS)) && \ +#if (defined(CONFIG_STM32_OTGFS) || defined(CONFIG_STM32_OTGFSHS)) && \ defined(CONFIG_USBHOST) #ifdef HAVE_USBHOST_TRACE @@ -190,5 +190,5 @@ void stm32_usbhost_vbusdrive(int iface, bool enable); #endif #endif /* __ASSEMBLY__ */ -#endif /* (CONFIG_STM32F7_OTGFS || CONFIG_STM32F7_OTGFSHS) && CONFIG_USBHOST */ +#endif /* (CONFIG_STM32_OTGFS || CONFIG_STM32_OTGFSHS) && CONFIG_USBHOST */ #endif /* __ARCH_ARM_SRC_STM32F7_STM32_USBHOST_H */ diff --git a/arch/arm/src/stm32f7/stm32_waste.c b/arch/arm/src/stm32f7/stm32_waste.c deleted file mode 100644 index 5bbc052d872bd..0000000000000 --- a/arch/arm/src/stm32f7/stm32_waste.c +++ /dev/null @@ -1,44 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32f7/stm32_waste.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include -#include "stm32_waste.h" - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -uint32_t g_waste_counter = 0; - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -void stm32_waste(void) -{ - g_waste_counter++; -} diff --git a/arch/arm/src/stm32f7/stm32_waste.h b/arch/arm/src/stm32f7/stm32_waste.h deleted file mode 100644 index 96eb7e6b40b3c..0000000000000 --- a/arch/arm/src/stm32f7/stm32_waste.h +++ /dev/null @@ -1,66 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32f7/stm32_waste.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32_STM32_WASTE_H -#define __ARCH_ARM_SRC_STM32_STM32_WASTE_H - -/* Waste CPU Time */ - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#ifndef __ASSEMBLY__ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/* Waste CPU Time - * - * stm32_waste() is the logic that will be executed when portions of kernel - * or user-app is polling some register or similar, waiting for desired - * status. This time is wasted away. This function offers a measure of - * badly written piece of software or some undesired behavior. - * - * At the same time this function adds to some IDLE time which portion - * cannot be used for other purposes (yet). - */ - -void stm32_waste(void); - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32_STM32_WASTE_H */ diff --git a/arch/arm/src/stm32f7/stm32f72xx73xx_rcc.c b/arch/arm/src/stm32f7/stm32f72xx73xx_rcc.c index 19d3e90346bd3..5911b6a713921 100644 --- a/arch/arm/src/stm32f7/stm32f72xx73xx_rcc.c +++ b/arch/arm/src/stm32f7/stm32f72xx73xx_rcc.c @@ -132,48 +132,48 @@ static inline void rcc_enableahb1(void) /* Enable GPIOA, GPIOB, .... GPIOI */ -#if STM32F7_NGPIO > 0 +#if STM32_NGPIO > 0 regval |= (RCC_AHB1ENR_GPIOAEN -#if STM32F7_NGPIO > 1 +#if STM32_NGPIO > 1 | RCC_AHB1ENR_GPIOBEN #endif -#if STM32F7_NGPIO > 2 +#if STM32_NGPIO > 2 | RCC_AHB1ENR_GPIOCEN #endif -#if STM32F7_NGPIO > 3 +#if STM32_NGPIO > 3 | RCC_AHB1ENR_GPIODEN #endif -#if STM32F7_NGPIO > 4 +#if STM32_NGPIO > 4 | RCC_AHB1ENR_GPIOEEN #endif -#if STM32F7_NGPIO > 5 +#if STM32_NGPIO > 5 | RCC_AHB1ENR_GPIOFEN #endif -#if STM32F7_NGPIO > 6 +#if STM32_NGPIO > 6 | RCC_AHB1ENR_GPIOGEN #endif -#if STM32F7_NGPIO > 7 +#if STM32_NGPIO > 7 | RCC_AHB1ENR_GPIOHEN #endif -#if STM32F7_NGPIO > 8 +#if STM32_NGPIO > 8 | RCC_AHB1ENR_GPIOIEN #endif -#if STM32F7_NGPIO > 9 +#if STM32_NGPIO > 9 | RCC_AHB1ENR_GPIOJEN #endif -#if STM32F7_NGPIO > 10 +#if STM32_NGPIO > 10 | RCC_AHB1ENR_GPIOKEN #endif ); #endif -#ifdef CONFIG_STM32F7_CRC +#ifdef CONFIG_STM32_CRC /* CRC clock enable */ regval |= RCC_AHB1ENR_CRCEN; #endif -#ifdef CONFIG_STM32F7_BKPSRAM +#ifdef CONFIG_STM32_BKPSRAM /* Backup SRAM clock enable */ regval |= RCC_AHB1ENR_BKPSRAMEN; @@ -185,31 +185,31 @@ static inline void rcc_enableahb1(void) regval |= RCC_AHB1ENR_DTCMRAMEN; #endif -#ifdef CONFIG_STM32F7_DMA1 +#ifdef CONFIG_STM32_DMA1 /* DMA 1 clock enable */ regval |= RCC_AHB1ENR_DMA1EN; #endif -#ifdef CONFIG_STM32F7_DMA2 +#ifdef CONFIG_STM32_DMA2 /* DMA 2 clock enable */ regval |= RCC_AHB1ENR_DMA2EN; #endif -#ifdef CONFIG_STM32F7_DMA2D +#ifdef CONFIG_STM32_DMA2D /* DMA2D clock */ regval |= RCC_AHB1ENR_DMA2DEN; #endif -#ifdef CONFIG_STM32F7_ETHMAC +#ifdef CONFIG_STM32_ETHMAC /* Ethernet MAC clocking */ regval |= (RCC_AHB1ENR_ETHMACEN | RCC_AHB1ENR_ETHMACTXEN | \ RCC_AHB1ENR_ETHMACRXEN); -#ifdef CONFIG_STM32F7_ETH_PTP +#ifdef CONFIG_STM32_ETH_PTP /* Precision Time Protocol (PTP) */ regval |= RCC_AHB1ENR_ETHMACPTPEN; @@ -217,9 +217,9 @@ static inline void rcc_enableahb1(void) #endif #endif -#ifdef CONFIG_STM32F7_OTGFSHS -# if defined(CONFIG_STM32F7_INTERNAL_ULPI) || - defined(CONFIG_STM32F7_EXTERNAL_ULPI) +#ifdef CONFIG_STM32_OTGFSHS +# if defined(CONFIG_STM32_INTERNAL_ULPI) || + defined(CONFIG_STM32_EXTERNAL_ULPI) /* Enable clocking for USB OTG HS and external PHY */ @@ -229,7 +229,7 @@ static inline void rcc_enableahb1(void) regval |= RCC_AHB1ENR_OTGHSEN; #endif -#endif /* CONFIG_STM32F7_OTGFSHS */ +#endif /* CONFIG_STM32_OTGFSHS */ putreg32(regval, STM32_RCC_AHB1ENR); /* Enable peripherals */ } @@ -252,31 +252,31 @@ static inline void rcc_enableahb2(void) regval = getreg32(STM32_RCC_AHB2ENR); -#ifdef CONFIG_STM32F7_DCMI +#ifdef CONFIG_STM32_DCMI /* Camera interface enable */ regval |= RCC_AHB2ENR_DCMIEN; #endif -#ifdef CONFIG_STM32F7_CRYP +#ifdef CONFIG_STM32_CRYP /* Cryptographic modules clock enable */ regval |= RCC_AHB2ENR_CRYPEN; #endif -#ifdef CONFIG_STM32F7_HASH +#ifdef CONFIG_STM32_HASH /* Hash modules clock enable */ regval |= RCC_AHB2ENR_HASHEN; #endif -#ifdef CONFIG_STM32F7_RNG +#ifdef CONFIG_STM32_RNG /* Random number generator clock enable */ regval |= RCC_AHB2ENR_RNGEN; #endif -#ifdef CONFIG_STM32F7_OTGFS +#ifdef CONFIG_STM32_OTGFS /* USB OTG FS clock enable */ regval |= RCC_AHB2ENR_OTGFSEN; @@ -303,13 +303,13 @@ static inline void rcc_enableahb3(void) regval = getreg32(STM32_RCC_AHB3ENR); -#ifdef CONFIG_STM32F7_FMC +#ifdef CONFIG_STM32_FMC /* Flexible static memory controller module clock enable */ regval |= RCC_AHB3ENR_FMCEN; #endif -#ifdef CONFIG_STM32F7_QUADSPI +#ifdef CONFIG_STM32_QSPI /* FQuad SPI memory controller clock enable */ regval |= RCC_AHB3ENR_QSPIEN; @@ -336,151 +336,151 @@ static inline void rcc_enableapb1(void) regval = getreg32(STM32_RCC_APB1ENR); -#ifdef CONFIG_STM32F7_TIM2 +#ifdef CONFIG_STM32_TIM2 /* TIM2 clock enable */ regval |= RCC_APB1ENR_TIM2EN; #endif -#ifdef CONFIG_STM32F7_TIM3 +#ifdef CONFIG_STM32_TIM3 /* TIM3 clock enable */ regval |= RCC_APB1ENR_TIM3EN; #endif -#ifdef CONFIG_STM32F7_TIM4 +#ifdef CONFIG_STM32_TIM4 /* TIM4 clock enable */ regval |= RCC_APB1ENR_TIM4EN; #endif -#ifdef CONFIG_STM32F7_TIM5 +#ifdef CONFIG_STM32_TIM5 /* TIM5 clock enable */ regval |= RCC_APB1ENR_TIM5EN; #endif -#ifdef CONFIG_STM32F7_TIM6 +#ifdef CONFIG_STM32_TIM6 /* TIM6 clock enable */ regval |= RCC_APB1ENR_TIM6EN; #endif -#ifdef CONFIG_STM32F7_TIM7 +#ifdef CONFIG_STM32_TIM7 /* TIM7 clock enable */ regval |= RCC_APB1ENR_TIM7EN; #endif -#ifdef CONFIG_STM32F7_TIM12 +#ifdef CONFIG_STM32_TIM12 /* TIM12 clock enable */ regval |= RCC_APB1ENR_TIM12EN; #endif -#ifdef CONFIG_STM32F7_TIM13 +#ifdef CONFIG_STM32_TIM13 /* TIM13 clock enable */ regval |= RCC_APB1ENR_TIM13EN; #endif -#ifdef CONFIG_STM32F7_TIM14 +#ifdef CONFIG_STM32_TIM14 /* TIM14 clock enable */ regval |= RCC_APB1ENR_TIM14EN; #endif -#ifdef CONFIG_STM32F7_LPTIM1 +#ifdef CONFIG_STM32_LPTIM1 /* Low-power timer 1 clock enable */ regval |= RCC_APB1ENR_LPTIM1EN; #endif -#ifdef CONFIG_STM32F7_WWDG +#ifdef CONFIG_STM32_WWDG /* Window watchdog clock enable */ regval |= RCC_APB1ENR_WWDGEN; #endif -#ifdef CONFIG_STM32F7_SPI2 +#ifdef CONFIG_STM32_SPI2 /* SPI2 clock enable */ regval |= RCC_APB1ENR_SPI2EN; #endif -#ifdef CONFIG_STM32F7_SPI3 +#ifdef CONFIG_STM32_SPI3 /* SPI3 clock enable */ regval |= RCC_APB1ENR_SPI3EN; #endif -#ifdef CONFIG_STM32F7_SPDIFRX +#ifdef CONFIG_STM32_SPDIFRX /* SPDIFRX clock enable */ regval |= RCC_APB1ENR_SPDIFRXEN; #endif -#ifdef CONFIG_STM32F7_USART2 +#ifdef CONFIG_STM32_USART2 /* USART 2 clock enable */ regval |= RCC_APB1ENR_USART2EN; #endif -#ifdef CONFIG_STM32F7_USART3 +#ifdef CONFIG_STM32_USART3 /* USART3 clock enable */ regval |= RCC_APB1ENR_USART3EN; #endif -#ifdef CONFIG_STM32F7_UART4 +#ifdef CONFIG_STM32_UART4 /* UART4 clock enable */ regval |= RCC_APB1ENR_UART4EN; #endif -#ifdef CONFIG_STM32F7_UART5 +#ifdef CONFIG_STM32_UART5 /* UART5 clock enable */ regval |= RCC_APB1ENR_UART5EN; #endif -#ifdef CONFIG_STM32F7_I2C1 +#ifdef CONFIG_STM32_I2C1 /* I2C1 clock enable */ regval |= RCC_APB1ENR_I2C1EN; #endif -#ifdef CONFIG_STM32F7_I2C2 +#ifdef CONFIG_STM32_I2C2 /* I2C2 clock enable */ regval |= RCC_APB1ENR_I2C2EN; #endif -#ifdef CONFIG_STM32F7_I2C3 +#ifdef CONFIG_STM32_I2C3 /* I2C3 clock enable */ regval |= RCC_APB1ENR_I2C3EN; #endif -#ifdef CONFIG_STM32F7_I2C4 +#ifdef CONFIG_STM32_I2C4 /* I2C4 clock enable */ regval |= RCC_APB1ENR_I2C4EN; #endif -#ifdef CONFIG_STM32F7_CAN1 +#ifdef CONFIG_STM32_CAN1 /* CAN 1 clock enable */ regval |= RCC_APB1ENR_CAN1EN; #endif -#ifdef CONFIG_STM32F7_CAN2 +#ifdef CONFIG_STM32_CAN2 /* CAN2 clock enable. NOTE: CAN2 needs CAN1 clock as well. */ regval |= (RCC_APB1ENR_CAN1EN | RCC_APB1ENR_CAN2EN); #endif -#ifdef CONFIG_STM32F7_CEC +#ifdef CONFIG_STM32_CEC /* CEC clock enable. */ regval |= RCC_APB1ENR_CECEN; @@ -492,19 +492,19 @@ static inline void rcc_enableapb1(void) regval |= RCC_APB1ENR_PWREN; -#if defined (CONFIG_STM32F7_DAC1) || defined(CONFIG_STM32F7_DAC2) +#if defined (CONFIG_STM32_DAC1) || defined(CONFIG_STM32_DAC2) /* DAC interface clock enable */ regval |= RCC_APB1ENR_DACEN; #endif -#ifdef CONFIG_STM32F7_UART7 +#ifdef CONFIG_STM32_UART7 /* UART7 clock enable */ regval |= RCC_APB1ENR_UART7EN; #endif -#ifdef CONFIG_STM32F7_UART8 +#ifdef CONFIG_STM32_UART8 /* UART8 clock enable */ regval |= RCC_APB1ENR_UART8EN; @@ -531,67 +531,67 @@ static inline void rcc_enableapb2(void) regval = getreg32(STM32_RCC_APB2ENR); -#ifdef CONFIG_STM32F7_TIM1 +#ifdef CONFIG_STM32_TIM1 /* TIM1 clock enable */ regval |= RCC_APB2ENR_TIM1EN; #endif -#ifdef CONFIG_STM32F7_TIM8 +#ifdef CONFIG_STM32_TIM8 /* TIM8 clock enable */ regval |= RCC_APB2ENR_TIM8EN; #endif -#ifdef CONFIG_STM32F7_USART1 +#ifdef CONFIG_STM32_USART1 /* USART1 clock enable */ regval |= RCC_APB2ENR_USART1EN; #endif -#ifdef CONFIG_STM32F7_USART6 +#ifdef CONFIG_STM32_USART6 /* USART6 clock enable */ regval |= RCC_APB2ENR_USART6EN; #endif -#ifdef CONFIG_STM32F7_ADC1 +#ifdef CONFIG_STM32_ADC1 /* ADC1 clock enable */ regval |= RCC_APB2ENR_ADC1EN; #endif -#ifdef CONFIG_STM32F7_ADC2 +#ifdef CONFIG_STM32_ADC2 /* ADC2 clock enable */ regval |= RCC_APB2ENR_ADC2EN; #endif -#ifdef CONFIG_STM32F7_ADC3 +#ifdef CONFIG_STM32_ADC3 /* ADC3 clock enable */ regval |= RCC_APB2ENR_ADC3EN; #endif -#ifdef CONFIG_STM32F7_SDMMC1 +#ifdef CONFIG_STM32_SDMMC1 /* SDIO clock enable */ regval |= RCC_APB2ENR_SDMMC1EN; #endif -#ifdef CONFIG_STM32F7_SDMMC2 +#ifdef CONFIG_STM32_SDMMC2 /* SDIO clock enable */ regval |= RCC_APB2ENR_SDMMC2EN; #endif -#ifdef CONFIG_STM32F7_SPI1 +#ifdef CONFIG_STM32_SPI1 /* SPI1 clock enable */ regval |= RCC_APB2ENR_SPI1EN; #endif -#ifdef CONFIG_STM32F7_SPI4 +#ifdef CONFIG_STM32_SPI4 /* SPI4 clock enable */ regval |= RCC_APB2ENR_SPI4EN; @@ -601,56 +601,56 @@ static inline void rcc_enableapb2(void) regval |= RCC_APB2ENR_SYSCFGEN; -#ifdef CONFIG_STM32F7_TIM9 +#ifdef CONFIG_STM32_TIM9 /* TIM9 clock enable */ regval |= RCC_APB2ENR_TIM9EN; #endif -#ifdef CONFIG_STM32F7_TIM10 +#ifdef CONFIG_STM32_TIM10 /* TIM10 clock enable */ regval |= RCC_APB2ENR_TIM10EN; #endif -#ifdef CONFIG_STM32F7_TIM11 +#ifdef CONFIG_STM32_TIM11 /* TIM11 clock enable */ regval |= RCC_APB2ENR_TIM11EN; #endif -#ifdef CONFIG_STM32F7_SPI5 +#ifdef CONFIG_STM32_SPI5 /* SPI5 clock enable */ regval |= RCC_APB2ENR_SPI5EN; #endif -#ifdef CONFIG_STM32F7_SPI6 +#ifdef CONFIG_STM32_SPI6 /* SPI6 clock enable */ regval |= RCC_APB2ENR_SPI6EN; #endif -#ifdef CONFIG_STM32F7_SAI1 +#ifdef CONFIG_STM32_SAI1 /* SPI6 clock enable */ regval |= RCC_APB2ENR_SAI1EN; #endif -#ifdef CONFIG_STM32F7_SAI2 +#ifdef CONFIG_STM32_SAI2 /* SPI6 clock enable */ regval |= RCC_APB2ENR_SAI2EN; #endif -#ifdef CONFIG_STM32F7_LTDC +#ifdef CONFIG_STM32_LTDC /* LTDC clock enable */ regval |= RCC_APB2ENR_LTDCEN; #endif -#ifdef CONFIG_STM32F7_OTGFSHS -#ifdef CONFIG_STM32F7_INTERNAL_ULPI +#ifdef CONFIG_STM32_OTGFSHS +#ifdef CONFIG_STM32_INTERNAL_ULPI regval |= RCC_APB2ENR_OTGPHYCEN; #endif @@ -669,7 +669,7 @@ static inline void rcc_enableapb2(void) * power clocking modes! ****************************************************************************/ -#ifndef CONFIG_STM32F7_CUSTOM_CLOCKCONFIG +#ifndef CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG static void stm32_stdclockconfig(void) { uint32_t regval; @@ -764,7 +764,7 @@ static void stm32_stdclockconfig(void) regval |= STM32_RCC_CFGR_PPRE1; putreg32(regval, STM32_RCC_CFGR); -#ifdef CONFIG_STM32F7_RTC_HSECLOCK +#ifdef CONFIG_STM32_RTC_HSECLOCK /* Set the RTC clock divisor */ regval = getreg32(STM32_RCC_CFGR); @@ -831,7 +831,7 @@ static void stm32_stdclockconfig(void) regval = FLASH_ACR_LATENCY(BOARD_FLASH_WAITSTATES); -#ifdef CONFIG_STM32F7_FLASH_ART_ACCELERATOR +#ifdef CONFIG_STM32_FLASH_ART_ACCELERATOR /* The Flash memory interface accelerates code execution with a system * of instruction prefetch and cache lines on ITCM interface (ART * Accelerator™). @@ -857,7 +857,7 @@ static void stm32_stdclockconfig(void) { } -#if defined(CONFIG_STM32F7_LTDC) || defined(CONFIG_STM32F7_PLLSAI) +#if defined(CONFIG_STM32_LTDC) || defined(CONFIG_STM32_PLLSAI) /* Configure PLLSAI */ @@ -865,14 +865,14 @@ static void stm32_stdclockconfig(void) regval &= ~(RCC_PLLSAICFGR_PLLSAIN_MASK | RCC_PLLSAICFGR_PLLSAIP_MASK | RCC_PLLSAICFGR_PLLSAIQ_MASK -# if defined(CONFIG_STM32F7_LTDC) +# if defined(CONFIG_STM32_LTDC) | RCC_PLLSAICFGR_PLLSAIR_MASK # endif ); regval |= (STM32_RCC_PLLSAICFGR_PLLSAIN | STM32_RCC_PLLSAICFGR_PLLSAIP | STM32_RCC_PLLSAICFGR_PLLSAIQ -# if defined(CONFIG_STM32F7_LTDC) +# if defined(CONFIG_STM32_LTDC) | STM32_RCC_PLLSAICFGR_PLLSAIR # endif ); @@ -881,7 +881,7 @@ static void stm32_stdclockconfig(void) regval = getreg32(STM32_RCC_DCKCFGR1); regval &= ~(RCC_DCKCFGR1_PLLI2SDIVQ_MASK | RCC_DCKCFGR1_PLLSAIDIVQ_MASK -# if defined(CONFIG_STM32F7_LTDC) +# if defined(CONFIG_STM32_LTDC) | RCC_DCKCFGR1_PLLSAIDIVR_MASK # endif | RCC_DCKCFGR1_SAI1SEL_MASK @@ -890,7 +890,7 @@ static void stm32_stdclockconfig(void) regval |= (STM32_RCC_DCKCFGR1_PLLI2SDIVQ | STM32_RCC_DCKCFGR1_PLLSAIDIVQ -# if defined(CONFIG_STM32F7_LTDC) +# if defined(CONFIG_STM32_LTDC) | STM32_RCC_DCKCFGR1_PLLSAIDIVR # endif | STM32_RCC_DCKCFGR1_SAI1SRC @@ -912,20 +912,20 @@ static void stm32_stdclockconfig(void) } #endif -#if defined(CONFIG_STM32F7_PLLI2S) || \ +#if defined(CONFIG_STM32_PLLI2S) || \ (STM32_RCC_DCKCFGR1_SAI1SRC == RCC_DCKCFGR1_SAI1SEL(1)) || \ (STM32_RCC_DCKCFGR1_SAI2SRC == RCC_DCKCFGR1_SAI2SEL(1)) /* Configure PLLI2S */ regval = getreg32(STM32_RCC_PLLI2SCFGR); regval &= ~(RCC_PLLI2SCFGR_PLLI2SN_MASK -# if !defined(CONFIG_STM32F7_STM32F72XX) && !defined(CONFIG_STM32F7_STM32F73XX) +# if !defined(CONFIG_STM32_STM32F72XX) && !defined(CONFIG_STM32_STM32F73XX) | RCC_PLLI2SCFGR_PLLI2SP_MASK # endif | RCC_PLLI2SCFGR_PLLI2SQ_MASK | RCC_PLLI2SCFGR_PLLI2SR_MASK); regval |= (STM32_RCC_PLLI2SCFGR_PLLI2SN -# if !defined(CONFIG_STM32F7_STM32F72XX) && !defined(CONFIG_STM32F7_STM32F73XX) +# if !defined(CONFIG_STM32_STM32F72XX) && !defined(CONFIG_STM32_STM32F73XX) | STM32_RCC_PLLI2SCFGR_PLLI2SP # endif | STM32_RCC_PLLI2SCFGR_PLLI2SQ @@ -956,7 +956,7 @@ static void stm32_stdclockconfig(void) | RCC_DCKCFGR2_I2C1SEL_MASK | RCC_DCKCFGR2_I2C2SEL_MASK | RCC_DCKCFGR2_I2C3SEL_MASK -# if !defined(CONFIG_STM32F7_STM32F72XX) && !defined(CONFIG_STM32F7_STM32F73XX) +# if !defined(CONFIG_STM32_STM32F72XX) && !defined(CONFIG_STM32_STM32F73XX) | RCC_DCKCFGR2_I2C4SEL_MASK | RCC_DCKCFGR2_CECSEL_MASK # endif @@ -975,7 +975,7 @@ static void stm32_stdclockconfig(void) | STM32_RCC_DCKCFGR2_I2C1SRC | STM32_RCC_DCKCFGR2_I2C2SRC | STM32_RCC_DCKCFGR2_I2C3SRC -# if !defined(CONFIG_STM32F7_STM32F72XX) && !defined(CONFIG_STM32F7_STM32F73XX) +# if !defined(CONFIG_STM32_STM32F72XX) && !defined(CONFIG_STM32_STM32F73XX) | STM32_RCC_DCKCFGR2_I2C4SRC | STM32_RCC_DCKCFGR2_CECSRC # endif @@ -986,13 +986,13 @@ static void stm32_stdclockconfig(void) putreg32(regval, STM32_RCC_DCKCFGR2); -#if defined(CONFIG_STM32F7_IWDG) || defined(CONFIG_STM32F7_RTC_LSICLOCK) +#if defined(CONFIG_STM32_IWDG) || defined(CONFIG_STM32_RTC_LSICLOCK) /* Low speed internal clock source LSI */ stm32_rcc_enablelsi(); #endif -#if defined(CONFIG_STM32F7_RTC_LSECLOCK) +#if defined(CONFIG_STM32_RTC_LSECLOCK) /* Low speed external clock source LSE * * TODO: There is another case where the LSE needs to diff --git a/arch/arm/src/stm32f7/stm32f74xx75xx_rcc.c b/arch/arm/src/stm32f7/stm32f74xx75xx_rcc.c index fac08c1146722..4da3ddffceb5f 100644 --- a/arch/arm/src/stm32f7/stm32f74xx75xx_rcc.c +++ b/arch/arm/src/stm32f7/stm32f74xx75xx_rcc.c @@ -134,48 +134,48 @@ static inline void rcc_enableahb1(void) /* Enable GPIOA, GPIOB, .... GPIOI */ -#if STM32F7_NGPIO > 0 +#if STM32_NGPIO > 0 regval |= (RCC_AHB1ENR_GPIOAEN -#if STM32F7_NGPIO > 1 +#if STM32_NGPIO > 1 | RCC_AHB1ENR_GPIOBEN #endif -#if STM32F7_NGPIO > 2 +#if STM32_NGPIO > 2 | RCC_AHB1ENR_GPIOCEN #endif -#if STM32F7_NGPIO > 3 +#if STM32_NGPIO > 3 | RCC_AHB1ENR_GPIODEN #endif -#if STM32F7_NGPIO > 4 +#if STM32_NGPIO > 4 | RCC_AHB1ENR_GPIOEEN #endif -#if STM32F7_NGPIO > 5 +#if STM32_NGPIO > 5 | RCC_AHB1ENR_GPIOFEN #endif -#if STM32F7_NGPIO > 6 +#if STM32_NGPIO > 6 | RCC_AHB1ENR_GPIOGEN #endif -#if STM32F7_NGPIO > 7 +#if STM32_NGPIO > 7 | RCC_AHB1ENR_GPIOHEN #endif -#if STM32F7_NGPIO > 8 +#if STM32_NGPIO > 8 | RCC_AHB1ENR_GPIOIEN #endif -#if STM32F7_NGPIO > 9 +#if STM32_NGPIO > 9 | RCC_AHB1ENR_GPIOJEN #endif -#if STM32F7_NGPIO > 10 +#if STM32_NGPIO > 10 | RCC_AHB1ENR_GPIOKEN #endif ); #endif -#ifdef CONFIG_STM32F7_CRC +#ifdef CONFIG_STM32_CRC /* CRC clock enable */ regval |= RCC_AHB1ENR_CRCEN; #endif -#ifdef CONFIG_STM32F7_BKPSRAM +#ifdef CONFIG_STM32_BKPSRAM /* Backup SRAM clock enable */ regval |= RCC_AHB1ENR_BKPSRAMEN; @@ -187,31 +187,31 @@ static inline void rcc_enableahb1(void) regval |= RCC_AHB1ENR_DTCMRAMEN; #endif -#ifdef CONFIG_STM32F7_DMA1 +#ifdef CONFIG_STM32_DMA1 /* DMA 1 clock enable */ regval |= RCC_AHB1ENR_DMA1EN; #endif -#ifdef CONFIG_STM32F7_DMA2 +#ifdef CONFIG_STM32_DMA2 /* DMA 2 clock enable */ regval |= RCC_AHB1ENR_DMA2EN; #endif -#ifdef CONFIG_STM32F7_DMA2D +#ifdef CONFIG_STM32_DMA2D /* DMA2D clock */ regval |= RCC_AHB1ENR_DMA2DEN; #endif -#ifdef CONFIG_STM32F7_ETHMAC +#ifdef CONFIG_STM32_ETHMAC /* Ethernet MAC clocking */ regval |= (RCC_AHB1ENR_ETHMACEN | RCC_AHB1ENR_ETHMACTXEN | \ RCC_AHB1ENR_ETHMACRXEN); -#ifdef CONFIG_STM32F7_ETH_PTP +#ifdef CONFIG_STM32_ETH_PTP /* Precision Time Protocol (PTP) */ regval |= RCC_AHB1ENR_ETHMACPTPEN; @@ -219,9 +219,9 @@ static inline void rcc_enableahb1(void) #endif #endif -#ifdef CONFIG_STM32F7_OTGFSHS -# if defined(CONFIG_STM32F7_INTERNAL_ULPI) || \ - defined(CONFIG_STM32F7_EXTERNAL_ULPI) +#ifdef CONFIG_STM32_OTGFSHS +# if defined(CONFIG_STM32_INTERNAL_ULPI) || \ + defined(CONFIG_STM32_EXTERNAL_ULPI) /* Enable clocking for USB OTG HS and external PHY */ @@ -231,7 +231,7 @@ static inline void rcc_enableahb1(void) regval |= RCC_AHB1ENR_OTGHSEN; #endif -#endif /* CONFIG_STM32F7_OTGFSHS */ +#endif /* CONFIG_STM32_OTGFSHS */ putreg32(regval, STM32_RCC_AHB1ENR); /* Enable peripherals */ } @@ -254,31 +254,31 @@ static inline void rcc_enableahb2(void) regval = getreg32(STM32_RCC_AHB2ENR); -#ifdef CONFIG_STM32F7_DCMI +#ifdef CONFIG_STM32_DCMI /* Camera interface enable */ regval |= RCC_AHB2ENR_DCMIEN; #endif -#ifdef CONFIG_STM32F7_CRYP +#ifdef CONFIG_STM32_CRYP /* Cryptographic modules clock enable */ regval |= RCC_AHB2ENR_CRYPEN; #endif -#ifdef CONFIG_STM32F7_HASH +#ifdef CONFIG_STM32_HASH /* Hash modules clock enable */ regval |= RCC_AHB2ENR_HASHEN; #endif -#ifdef CONFIG_STM32F7_RNG +#ifdef CONFIG_STM32_RNG /* Random number generator clock enable */ regval |= RCC_AHB2ENR_RNGEN; #endif -#ifdef CONFIG_STM32F7_OTGFS +#ifdef CONFIG_STM32_OTGFS /* USB OTG FS clock enable */ regval |= RCC_AHB2ENR_OTGFSEN; @@ -305,13 +305,13 @@ static inline void rcc_enableahb3(void) regval = getreg32(STM32_RCC_AHB3ENR); -#ifdef CONFIG_STM32F7_FMC +#ifdef CONFIG_STM32_FMC /* Flexible static memory controller module clock enable */ regval |= RCC_AHB3ENR_FMCEN; #endif -#ifdef CONFIG_STM32F7_QUADSPI +#ifdef CONFIG_STM32_QSPI /* FQuad SPI memory controller clock enable */ regval |= RCC_AHB3ENR_QSPIEN; @@ -338,151 +338,151 @@ static inline void rcc_enableapb1(void) regval = getreg32(STM32_RCC_APB1ENR); -#ifdef CONFIG_STM32F7_TIM2 +#ifdef CONFIG_STM32_TIM2 /* TIM2 clock enable */ regval |= RCC_APB1ENR_TIM2EN; #endif -#ifdef CONFIG_STM32F7_TIM3 +#ifdef CONFIG_STM32_TIM3 /* TIM3 clock enable */ regval |= RCC_APB1ENR_TIM3EN; #endif -#ifdef CONFIG_STM32F7_TIM4 +#ifdef CONFIG_STM32_TIM4 /* TIM4 clock enable */ regval |= RCC_APB1ENR_TIM4EN; #endif -#ifdef CONFIG_STM32F7_TIM5 +#ifdef CONFIG_STM32_TIM5 /* TIM5 clock enable */ regval |= RCC_APB1ENR_TIM5EN; #endif -#ifdef CONFIG_STM32F7_TIM6 +#ifdef CONFIG_STM32_TIM6 /* TIM6 clock enable */ regval |= RCC_APB1ENR_TIM6EN; #endif -#ifdef CONFIG_STM32F7_TIM7 +#ifdef CONFIG_STM32_TIM7 /* TIM7 clock enable */ regval |= RCC_APB1ENR_TIM7EN; #endif -#ifdef CONFIG_STM32F7_TIM12 +#ifdef CONFIG_STM32_TIM12 /* TIM12 clock enable */ regval |= RCC_APB1ENR_TIM12EN; #endif -#ifdef CONFIG_STM32F7_TIM13 +#ifdef CONFIG_STM32_TIM13 /* TIM13 clock enable */ regval |= RCC_APB1ENR_TIM13EN; #endif -#ifdef CONFIG_STM32F7_TIM14 +#ifdef CONFIG_STM32_TIM14 /* TIM14 clock enable */ regval |= RCC_APB1ENR_TIM14EN; #endif -#ifdef CONFIG_STM32F7_LPTIM1 +#ifdef CONFIG_STM32_LPTIM1 /* Low-power timer 1 clock enable */ regval |= RCC_APB1ENR_LPTIM1EN; #endif -#ifdef CONFIG_STM32F7_WWDG +#ifdef CONFIG_STM32_WWDG /* Window watchdog clock enable */ regval |= RCC_APB1ENR_WWDGEN; #endif -#ifdef CONFIG_STM32F7_SPI2 +#ifdef CONFIG_STM32_SPI2 /* SPI2 clock enable */ regval |= RCC_APB1ENR_SPI2EN; #endif -#ifdef CONFIG_STM32F7_SPI3 +#ifdef CONFIG_STM32_SPI3 /* SPI3 clock enable */ regval |= RCC_APB1ENR_SPI3EN; #endif -#ifdef CONFIG_STM32F7_SPDIFRX +#ifdef CONFIG_STM32_SPDIFRX /* SPDIFRX clock enable */ regval |= RCC_APB1ENR_SPDIFRXEN; #endif -#ifdef CONFIG_STM32F7_USART2 +#ifdef CONFIG_STM32_USART2 /* USART 2 clock enable */ regval |= RCC_APB1ENR_USART2EN; #endif -#ifdef CONFIG_STM32F7_USART3 +#ifdef CONFIG_STM32_USART3 /* USART3 clock enable */ regval |= RCC_APB1ENR_USART3EN; #endif -#ifdef CONFIG_STM32F7_UART4 +#ifdef CONFIG_STM32_UART4 /* UART4 clock enable */ regval |= RCC_APB1ENR_UART4EN; #endif -#ifdef CONFIG_STM32F7_UART5 +#ifdef CONFIG_STM32_UART5 /* UART5 clock enable */ regval |= RCC_APB1ENR_UART5EN; #endif -#ifdef CONFIG_STM32F7_I2C1 +#ifdef CONFIG_STM32_I2C1 /* I2C1 clock enable */ regval |= RCC_APB1ENR_I2C1EN; #endif -#ifdef CONFIG_STM32F7_I2C2 +#ifdef CONFIG_STM32_I2C2 /* I2C2 clock enable */ regval |= RCC_APB1ENR_I2C2EN; #endif -#ifdef CONFIG_STM32F7_I2C3 +#ifdef CONFIG_STM32_I2C3 /* I2C3 clock enable */ regval |= RCC_APB1ENR_I2C3EN; #endif -#ifdef CONFIG_STM32F7_I2C4 +#ifdef CONFIG_STM32_I2C4 /* I2C4 clock enable */ regval |= RCC_APB1ENR_I2C4EN; #endif -#ifdef CONFIG_STM32F7_CAN1 +#ifdef CONFIG_STM32_CAN1 /* CAN 1 clock enable */ regval |= RCC_APB1ENR_CAN1EN; #endif -#ifdef CONFIG_STM32F7_CAN2 +#ifdef CONFIG_STM32_CAN2 /* CAN2 clock enable. NOTE: CAN2 needs CAN1 clock as well. */ regval |= (RCC_APB1ENR_CAN1EN | RCC_APB1ENR_CAN2EN); #endif -#ifdef CONFIG_STM32F7_CEC +#ifdef CONFIG_STM32_CEC /* CEC clock enable. */ regval |= RCC_APB1ENR_CECEN; @@ -494,19 +494,19 @@ static inline void rcc_enableapb1(void) regval |= RCC_APB1ENR_PWREN; -#if defined (CONFIG_STM32F7_DAC1) || defined(CONFIG_STM32F7_DAC2) +#if defined (CONFIG_STM32_DAC1) || defined(CONFIG_STM32_DAC2) /* DAC interface clock enable */ regval |= RCC_APB1ENR_DACEN; #endif -#ifdef CONFIG_STM32F7_UART7 +#ifdef CONFIG_STM32_UART7 /* UART7 clock enable */ regval |= RCC_APB1ENR_UART7EN; #endif -#ifdef CONFIG_STM32F7_UART8 +#ifdef CONFIG_STM32_UART8 /* UART8 clock enable */ regval |= RCC_APB1ENR_UART8EN; @@ -533,67 +533,67 @@ static inline void rcc_enableapb2(void) regval = getreg32(STM32_RCC_APB2ENR); -#ifdef CONFIG_STM32F7_TIM1 +#ifdef CONFIG_STM32_TIM1 /* TIM1 clock enable */ regval |= RCC_APB2ENR_TIM1EN; #endif -#ifdef CONFIG_STM32F7_TIM8 +#ifdef CONFIG_STM32_TIM8 /* TIM8 clock enable */ regval |= RCC_APB2ENR_TIM8EN; #endif -#ifdef CONFIG_STM32F7_USART1 +#ifdef CONFIG_STM32_USART1 /* USART1 clock enable */ regval |= RCC_APB2ENR_USART1EN; #endif -#ifdef CONFIG_STM32F7_USART6 +#ifdef CONFIG_STM32_USART6 /* USART6 clock enable */ regval |= RCC_APB2ENR_USART6EN; #endif -#ifdef CONFIG_STM32F7_ADC1 +#ifdef CONFIG_STM32_ADC1 /* ADC1 clock enable */ regval |= RCC_APB2ENR_ADC1EN; #endif -#ifdef CONFIG_STM32F7_ADC2 +#ifdef CONFIG_STM32_ADC2 /* ADC2 clock enable */ regval |= RCC_APB2ENR_ADC2EN; #endif -#ifdef CONFIG_STM32F7_ADC3 +#ifdef CONFIG_STM32_ADC3 /* ADC3 clock enable */ regval |= RCC_APB2ENR_ADC3EN; #endif -#ifdef CONFIG_STM32F7_SDMMC1 +#ifdef CONFIG_STM32_SDMMC1 /* SDIO_1 clock enable */ regval |= RCC_APB2ENR_SDMMC1EN; #endif -#ifdef CONFIG_STM32F7_SDMMC2 +#ifdef CONFIG_STM32_SDMMC2 /* SDIO_2 clock enable */ regval |= RCC_APB2ENR_SDMMC2EN; #endif -#ifdef CONFIG_STM32F7_SPI1 +#ifdef CONFIG_STM32_SPI1 /* SPI1 clock enable */ regval |= RCC_APB2ENR_SPI1EN; #endif -#ifdef CONFIG_STM32F7_SPI4 +#ifdef CONFIG_STM32_SPI4 /* SPI4 clock enable */ regval |= RCC_APB2ENR_SPI4EN; @@ -603,49 +603,49 @@ static inline void rcc_enableapb2(void) regval |= RCC_APB2ENR_SYSCFGEN; -#ifdef CONFIG_STM32F7_TIM9 +#ifdef CONFIG_STM32_TIM9 /* TIM9 clock enable */ regval |= RCC_APB2ENR_TIM9EN; #endif -#ifdef CONFIG_STM32F7_TIM10 +#ifdef CONFIG_STM32_TIM10 /* TIM10 clock enable */ regval |= RCC_APB2ENR_TIM10EN; #endif -#ifdef CONFIG_STM32F7_TIM11 +#ifdef CONFIG_STM32_TIM11 /* TIM11 clock enable */ regval |= RCC_APB2ENR_TIM11EN; #endif -#ifdef CONFIG_STM32F7_SPI5 +#ifdef CONFIG_STM32_SPI5 /* SPI5 clock enable */ regval |= RCC_APB2ENR_SPI5EN; #endif -#ifdef CONFIG_STM32F7_SPI6 +#ifdef CONFIG_STM32_SPI6 /* SPI6 clock enable */ regval |= RCC_APB2ENR_SPI6EN; #endif -#ifdef CONFIG_STM32F7_SAI1 +#ifdef CONFIG_STM32_SAI1 /* SPI6 clock enable */ regval |= RCC_APB2ENR_SAI1EN; #endif -#ifdef CONFIG_STM32F7_SAI2 +#ifdef CONFIG_STM32_SAI2 /* SPI6 clock enable */ regval |= RCC_APB2ENR_SAI2EN; #endif -#ifdef CONFIG_STM32F7_LTDC +#ifdef CONFIG_STM32_LTDC /* LTDC clock enable */ regval |= RCC_APB2ENR_LTDCEN; @@ -664,7 +664,7 @@ static inline void rcc_enableapb2(void) * power clocking modes! ****************************************************************************/ -#ifndef CONFIG_STM32F7_CUSTOM_CLOCKCONFIG +#ifndef CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG static void stm32_stdclockconfig(void) { uint32_t regval; @@ -759,7 +759,7 @@ static void stm32_stdclockconfig(void) regval |= STM32_RCC_CFGR_PPRE1; putreg32(regval, STM32_RCC_CFGR); -#ifdef CONFIG_STM32F7_RTC_HSECLOCK +#ifdef CONFIG_STM32_RTC_HSECLOCK /* Set the RTC clock divisor */ regval = getreg32(STM32_RCC_CFGR); @@ -826,7 +826,7 @@ static void stm32_stdclockconfig(void) regval = FLASH_ACR_LATENCY(BOARD_FLASH_WAITSTATES); -#ifdef CONFIG_STM32F7_FLASH_ART_ACCELERATOR +#ifdef CONFIG_STM32_FLASH_ART_ACCELERATOR /* The Flash memory interface accelerates code execution with a system * of instruction prefetch and cache lines on ITCM interface (ART * Accelerator™). @@ -852,7 +852,7 @@ static void stm32_stdclockconfig(void) { } -#if defined(CONFIG_STM32F7_LTDC) || defined(CONFIG_STM32F7_PLLSAI) +#if defined(CONFIG_STM32_LTDC) || defined(CONFIG_STM32_PLLSAI) /* Configure PLLSAI */ @@ -897,7 +897,7 @@ static void stm32_stdclockconfig(void) } #endif -#if defined(CONFIG_STM32F7_PLLI2S) || \ +#if defined(CONFIG_STM32_PLLI2S) || \ (STM32_RCC_DCKCFGR1_SAI1SRC == RCC_DCKCFGR1_SAI1SEL(1)) || \ (STM32_RCC_DCKCFGR1_SAI2SRC == RCC_DCKCFGR1_SAI2SEL(1)) /* Configure PLLI2S */ @@ -961,13 +961,13 @@ static void stm32_stdclockconfig(void) putreg32(regval, STM32_RCC_DCKCFGR2); -#if defined(CONFIG_STM32F7_IWDG) || defined(CONFIG_STM32F7_RTC_LSICLOCK) +#if defined(CONFIG_STM32_IWDG) || defined(CONFIG_STM32_RTC_LSICLOCK) /* Low speed internal clock source LSI */ stm32_rcc_enablelsi(); #endif -#if defined(CONFIG_STM32F7_RTC_LSECLOCK) +#if defined(CONFIG_STM32_RTC_LSECLOCK) /* Low speed external clock source LSE * * TODO: There is another case where the LSE needs to diff --git a/arch/arm/src/stm32f7/stm32f76xx77xx_rcc.c b/arch/arm/src/stm32f7/stm32f76xx77xx_rcc.c index ff026b7f8e733..95eb7e6a59260 100644 --- a/arch/arm/src/stm32f7/stm32f76xx77xx_rcc.c +++ b/arch/arm/src/stm32f7/stm32f76xx77xx_rcc.c @@ -52,7 +52,7 @@ static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1, #define HSE_DIVISOR (STM32_HSE_FREQUENCY + 500000) / 1000000 -/* If CONFIG_STM32F7_DSIHOST is defined in the board configuration, then +/* If CONFIG_STM32_DSIHOST is defined in the board configuration, then * STM32_RCC_DCKCFGR2_DSISRC must also be defined to select the clock * source. */ @@ -142,48 +142,48 @@ static inline void rcc_enableahb1(void) /* Enable GPIOA, GPIOB, .... GPIOI */ -#if STM32F7_NGPIO > 0 +#if STM32_NGPIO > 0 regval |= (RCC_AHB1ENR_GPIOAEN -#if STM32F7_NGPIO > 1 +#if STM32_NGPIO > 1 | RCC_AHB1ENR_GPIOBEN #endif -#if STM32F7_NGPIO > 2 +#if STM32_NGPIO > 2 | RCC_AHB1ENR_GPIOCEN #endif -#if STM32F7_NGPIO > 3 +#if STM32_NGPIO > 3 | RCC_AHB1ENR_GPIODEN #endif -#if STM32F7_NGPIO > 4 +#if STM32_NGPIO > 4 | RCC_AHB1ENR_GPIOEEN #endif -#if STM32F7_NGPIO > 5 +#if STM32_NGPIO > 5 | RCC_AHB1ENR_GPIOFEN #endif -#if STM32F7_NGPIO > 6 +#if STM32_NGPIO > 6 | RCC_AHB1ENR_GPIOGEN #endif -#if STM32F7_NGPIO > 7 +#if STM32_NGPIO > 7 | RCC_AHB1ENR_GPIOHEN #endif -#if STM32F7_NGPIO > 8 +#if STM32_NGPIO > 8 | RCC_AHB1ENR_GPIOIEN #endif -#if STM32F7_NGPIO > 9 +#if STM32_NGPIO > 9 | RCC_AHB1ENR_GPIOJEN #endif -#if STM32F7_NGPIO > 10 +#if STM32_NGPIO > 10 | RCC_AHB1ENR_GPIOKEN #endif ); #endif -#ifdef CONFIG_STM32F7_CRC +#ifdef CONFIG_STM32_CRC /* CRC clock enable */ regval |= RCC_AHB1ENR_CRCEN; #endif -#ifdef CONFIG_STM32F7_BKPSRAM +#ifdef CONFIG_STM32_BKPSRAM /* Backup SRAM clock enable */ regval |= RCC_AHB1ENR_BKPSRAMEN; @@ -195,31 +195,31 @@ static inline void rcc_enableahb1(void) regval |= RCC_AHB1ENR_DTCMRAMEN; #endif -#ifdef CONFIG_STM32F7_DMA1 +#ifdef CONFIG_STM32_DMA1 /* DMA 1 clock enable */ regval |= RCC_AHB1ENR_DMA1EN; #endif -#ifdef CONFIG_STM32F7_DMA2 +#ifdef CONFIG_STM32_DMA2 /* DMA 2 clock enable */ regval |= RCC_AHB1ENR_DMA2EN; #endif -#ifdef CONFIG_STM32F7_DMA2D +#ifdef CONFIG_STM32_DMA2D /* DMA2D clock */ regval |= RCC_AHB1ENR_DMA2DEN; #endif -#ifdef CONFIG_STM32F7_ETHMAC +#ifdef CONFIG_STM32_ETHMAC /* Ethernet MAC clocking */ regval |= (RCC_AHB1ENR_ETHMACEN | RCC_AHB1ENR_ETHMACTXEN | \ RCC_AHB1ENR_ETHMACRXEN); -#ifdef CONFIG_STM32F7_ETH_PTP +#ifdef CONFIG_STM32_ETH_PTP /* Precision Time Protocol (PTP) */ regval |= RCC_AHB1ENR_ETHMACPTPEN; @@ -227,9 +227,9 @@ static inline void rcc_enableahb1(void) #endif #endif -#ifdef CONFIG_STM32F7_OTGFSHS -# if defined(CONFIG_STM32F7_INTERNAL_ULPI) || \ - defined(CONFIG_STM32F7_EXTERNAL_ULPI) +#ifdef CONFIG_STM32_OTGFSHS +# if defined(CONFIG_STM32_INTERNAL_ULPI) || \ + defined(CONFIG_STM32_EXTERNAL_ULPI) /* Enable clocking for USB OTG HS and external PHY */ @@ -239,7 +239,7 @@ static inline void rcc_enableahb1(void) regval |= RCC_AHB1ENR_OTGHSEN; #endif -#endif /* CONFIG_STM32F7_OTGFSHS */ +#endif /* CONFIG_STM32_OTGFSHS */ putreg32(regval, STM32_RCC_AHB1ENR); /* Enable peripherals */ } @@ -262,31 +262,31 @@ static inline void rcc_enableahb2(void) regval = getreg32(STM32_RCC_AHB2ENR); -#ifdef CONFIG_STM32F7_DCMI +#ifdef CONFIG_STM32_DCMI /* Camera interface enable */ regval |= RCC_AHB2ENR_DCMIEN; #endif -#ifdef CONFIG_STM32F7_CRYP +#ifdef CONFIG_STM32_CRYP /* Cryptographic modules clock enable */ regval |= RCC_AHB2ENR_CRYPEN; #endif -#ifdef CONFIG_STM32F7_HASH +#ifdef CONFIG_STM32_HASH /* Hash modules clock enable */ regval |= RCC_AHB2ENR_HASHEN; #endif -#ifdef CONFIG_STM32F7_RNG +#ifdef CONFIG_STM32_RNG /* Random number generator clock enable */ regval |= RCC_AHB2ENR_RNGEN; #endif -#ifdef CONFIG_STM32F7_OTGFS +#ifdef CONFIG_STM32_OTGFS /* USB OTG FS clock enable */ regval |= RCC_AHB2ENR_OTGFSEN; @@ -313,13 +313,13 @@ static inline void rcc_enableahb3(void) regval = getreg32(STM32_RCC_AHB3ENR); -#ifdef CONFIG_STM32F7_FMC +#ifdef CONFIG_STM32_FMC /* Flexible static memory controller module clock enable */ regval |= RCC_AHB3ENR_FMCEN; #endif -#ifdef CONFIG_STM32F7_QUADSPI +#ifdef CONFIG_STM32_QSPI /* FQuad SPI memory controller clock enable */ regval |= RCC_AHB3ENR_QSPIEN; @@ -346,157 +346,157 @@ static inline void rcc_enableapb1(void) regval = getreg32(STM32_RCC_APB1ENR); -#ifdef CONFIG_STM32F7_TIM2 +#ifdef CONFIG_STM32_TIM2 /* TIM2 clock enable */ regval |= RCC_APB1ENR_TIM2EN; #endif -#ifdef CONFIG_STM32F7_TIM3 +#ifdef CONFIG_STM32_TIM3 /* TIM3 clock enable */ regval |= RCC_APB1ENR_TIM3EN; #endif -#ifdef CONFIG_STM32F7_TIM4 +#ifdef CONFIG_STM32_TIM4 /* TIM4 clock enable */ regval |= RCC_APB1ENR_TIM4EN; #endif -#ifdef CONFIG_STM32F7_TIM5 +#ifdef CONFIG_STM32_TIM5 /* TIM5 clock enable */ regval |= RCC_APB1ENR_TIM5EN; #endif -#ifdef CONFIG_STM32F7_TIM6 +#ifdef CONFIG_STM32_TIM6 /* TIM6 clock enable */ regval |= RCC_APB1ENR_TIM6EN; #endif -#ifdef CONFIG_STM32F7_TIM7 +#ifdef CONFIG_STM32_TIM7 /* TIM7 clock enable */ regval |= RCC_APB1ENR_TIM7EN; #endif -#ifdef CONFIG_STM32F7_TIM12 +#ifdef CONFIG_STM32_TIM12 /* TIM12 clock enable */ regval |= RCC_APB1ENR_TIM12EN; #endif -#ifdef CONFIG_STM32F7_TIM13 +#ifdef CONFIG_STM32_TIM13 /* TIM13 clock enable */ regval |= RCC_APB1ENR_TIM13EN; #endif -#ifdef CONFIG_STM32F7_TIM14 +#ifdef CONFIG_STM32_TIM14 /* TIM14 clock enable */ regval |= RCC_APB1ENR_TIM14EN; #endif -#ifdef CONFIG_STM32F7_LPTIM1 +#ifdef CONFIG_STM32_LPTIM1 /* Low-power timer 1 clock enable */ regval |= RCC_APB1ENR_LPTIM1EN; #endif -#ifdef CONFIG_STM32F7_WWDG +#ifdef CONFIG_STM32_WWDG /* Window watchdog clock enable */ regval |= RCC_APB1ENR_WWDGEN; #endif -#if defined(CONFIG_STM32F7_SPI2) || defined(CONFIG_STM32F7_I2S2) +#if defined(CONFIG_STM32_SPI2) || defined(CONFIG_STM32_I2S2) /* SPI2 clock enable */ regval |= RCC_APB1ENR_SPI2EN; #endif -#if defined(CONFIG_STM32F7_SPI3) || defined(CONFIG_STM32F7_I2S3) +#if defined(CONFIG_STM32_SPI3) || defined(CONFIG_STM32_I2S3) /* SPI3 clock enable */ regval |= RCC_APB1ENR_SPI3EN; #endif -#ifdef CONFIG_STM32F7_SPDIFRX +#ifdef CONFIG_STM32_SPDIFRX /* SPDIFRX clock enable */ regval |= RCC_APB1ENR_SPDIFRXEN; #endif -#ifdef CONFIG_STM32F7_USART2 +#ifdef CONFIG_STM32_USART2 /* USART 2 clock enable */ regval |= RCC_APB1ENR_USART2EN; #endif -#ifdef CONFIG_STM32F7_USART3 +#ifdef CONFIG_STM32_USART3 /* USART3 clock enable */ regval |= RCC_APB1ENR_USART3EN; #endif -#ifdef CONFIG_STM32F7_UART4 +#ifdef CONFIG_STM32_UART4 /* UART4 clock enable */ regval |= RCC_APB1ENR_UART4EN; #endif -#ifdef CONFIG_STM32F7_UART5 +#ifdef CONFIG_STM32_UART5 /* UART5 clock enable */ regval |= RCC_APB1ENR_UART5EN; #endif -#ifdef CONFIG_STM32F7_I2C1 +#ifdef CONFIG_STM32_I2C1 /* I2C1 clock enable */ regval |= RCC_APB1ENR_I2C1EN; #endif -#ifdef CONFIG_STM32F7_I2C2 +#ifdef CONFIG_STM32_I2C2 /* I2C2 clock enable */ regval |= RCC_APB1ENR_I2C2EN; #endif -#ifdef CONFIG_STM32F7_I2C3 +#ifdef CONFIG_STM32_I2C3 /* I2C3 clock enable */ regval |= RCC_APB1ENR_I2C3EN; #endif -#ifdef CONFIG_STM32F7_I2C4 +#ifdef CONFIG_STM32_I2C4 /* I2C4 clock enable */ regval |= RCC_APB1ENR_I2C4EN; #endif -#ifdef CONFIG_STM32F7_CAN1 +#ifdef CONFIG_STM32_CAN1 /* CAN 1 clock enable */ regval |= RCC_APB1ENR_CAN1EN; #endif -#ifdef CONFIG_STM32F7_CAN2 +#ifdef CONFIG_STM32_CAN2 /* CAN2 clock enable. NOTE: CAN2 needs CAN1 clock as well. */ regval |= (RCC_APB1ENR_CAN1EN | RCC_APB1ENR_CAN2EN); #endif -#ifdef CONFIG_STM32F7_CAN3 +#ifdef CONFIG_STM32_CAN3 /* CAN3 clock enable. */ regval |= (RCC_APB1ENR_CAN3EN); #endif -#ifdef CONFIG_STM32F7_CEC +#ifdef CONFIG_STM32_CEC /* CEC clock enable. */ regval |= RCC_APB1ENR_CECEN; @@ -508,19 +508,19 @@ static inline void rcc_enableapb1(void) regval |= RCC_APB1ENR_PWREN; -#if defined (CONFIG_STM32F7_DAC1) || defined(CONFIG_STM32F7_DAC2) +#if defined (CONFIG_STM32_DAC1) || defined(CONFIG_STM32_DAC2) /* DAC interface clock enable */ regval |= RCC_APB1ENR_DACEN; #endif -#ifdef CONFIG_STM32F7_UART7 +#ifdef CONFIG_STM32_UART7 /* UART7 clock enable */ regval |= RCC_APB1ENR_UART7EN; #endif -#ifdef CONFIG_STM32F7_UART8 +#ifdef CONFIG_STM32_UART8 /* UART8 clock enable */ regval |= RCC_APB1ENR_UART8EN; @@ -547,67 +547,67 @@ static inline void rcc_enableapb2(void) regval = getreg32(STM32_RCC_APB2ENR); -#ifdef CONFIG_STM32F7_TIM1 +#ifdef CONFIG_STM32_TIM1 /* TIM1 clock enable */ regval |= RCC_APB2ENR_TIM1EN; #endif -#ifdef CONFIG_STM32F7_TIM8 +#ifdef CONFIG_STM32_TIM8 /* TIM8 clock enable */ regval |= RCC_APB2ENR_TIM8EN; #endif -#ifdef CONFIG_STM32F7_USART1 +#ifdef CONFIG_STM32_USART1 /* USART1 clock enable */ regval |= RCC_APB2ENR_USART1EN; #endif -#ifdef CONFIG_STM32F7_USART6 +#ifdef CONFIG_STM32_USART6 /* USART6 clock enable */ regval |= RCC_APB2ENR_USART6EN; #endif -#ifdef CONFIG_STM32F7_ADC1 +#ifdef CONFIG_STM32_ADC1 /* ADC1 clock enable */ regval |= RCC_APB2ENR_ADC1EN; #endif -#ifdef CONFIG_STM32F7_ADC2 +#ifdef CONFIG_STM32_ADC2 /* ADC2 clock enable */ regval |= RCC_APB2ENR_ADC2EN; #endif -#ifdef CONFIG_STM32F7_ADC3 +#ifdef CONFIG_STM32_ADC3 /* ADC3 clock enable */ regval |= RCC_APB2ENR_ADC3EN; #endif -#ifdef CONFIG_STM32F7_SDMMC1 +#ifdef CONFIG_STM32_SDMMC1 /* SDIO_1 clock enable */ regval |= RCC_APB2ENR_SDMMC1EN; #endif -#ifdef CONFIG_STM32F7_SDMMC2 +#ifdef CONFIG_STM32_SDMMC2 /* SDIO_2 clock enable */ regval |= RCC_APB2ENR_SDMMC2EN; #endif -#ifdef CONFIG_STM32F7_SPI1 +#ifdef CONFIG_STM32_SPI1 /* SPI1 clock enable */ regval |= RCC_APB2ENR_SPI1EN; #endif -#ifdef CONFIG_STM32F7_SPI4 +#ifdef CONFIG_STM32_SPI4 /* SPI4 clock enable */ regval |= RCC_APB2ENR_SPI4EN; @@ -617,55 +617,55 @@ static inline void rcc_enableapb2(void) regval |= RCC_APB2ENR_SYSCFGEN; -#ifdef CONFIG_STM32F7_TIM9 +#ifdef CONFIG_STM32_TIM9 /* TIM9 clock enable */ regval |= RCC_APB2ENR_TIM9EN; #endif -#ifdef CONFIG_STM32F7_TIM10 +#ifdef CONFIG_STM32_TIM10 /* TIM10 clock enable */ regval |= RCC_APB2ENR_TIM10EN; #endif -#ifdef CONFIG_STM32F7_TIM11 +#ifdef CONFIG_STM32_TIM11 /* TIM11 clock enable */ regval |= RCC_APB2ENR_TIM11EN; #endif -#ifdef CONFIG_STM32F7_SPI5 +#ifdef CONFIG_STM32_SPI5 /* SPI5 clock enable */ regval |= RCC_APB2ENR_SPI5EN; #endif -#ifdef CONFIG_STM32F7_SPI6 +#ifdef CONFIG_STM32_SPI6 /* SPI6 clock enable */ regval |= RCC_APB2ENR_SPI6EN; #endif -#ifdef CONFIG_STM32F7_SAI1 +#ifdef CONFIG_STM32_SAI1 /* SPI6 clock enable */ regval |= RCC_APB2ENR_SAI1EN; #endif -#ifdef CONFIG_STM32F7_SAI2 +#ifdef CONFIG_STM32_SAI2 /* SPI6 clock enable */ regval |= RCC_APB2ENR_SAI2EN; #endif -#ifdef CONFIG_STM32F7_LTDC +#ifdef CONFIG_STM32_LTDC /* LTDC clock enable */ regval |= RCC_APB2ENR_LTDCEN; #endif -#ifdef CONFIG_STM32F7_DSIHOST +#ifdef CONFIG_STM32_DSIHOST /* LTDC clock enable */ regval |= RCC_APB2ENR_DSIEN; @@ -684,7 +684,7 @@ static inline void rcc_enableapb2(void) * power clocking modes! ****************************************************************************/ -#ifndef CONFIG_STM32F7_CUSTOM_CLOCKCONFIG +#ifndef CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG static void stm32_stdclockconfig(void) { uint32_t regval; @@ -779,7 +779,7 @@ static void stm32_stdclockconfig(void) regval |= STM32_RCC_CFGR_PPRE1; putreg32(regval, STM32_RCC_CFGR); -#ifdef CONFIG_STM32F7_RTC_HSECLOCK +#ifdef CONFIG_STM32_RTC_HSECLOCK /* Set the RTC clock divisor */ regval = getreg32(STM32_RCC_CFGR); @@ -846,7 +846,7 @@ static void stm32_stdclockconfig(void) regval = FLASH_ACR_LATENCY(BOARD_FLASH_WAITSTATES); -#ifdef CONFIG_STM32F7_FLASH_ART_ACCELERATOR +#ifdef CONFIG_STM32_FLASH_ART_ACCELERATOR /* The Flash memory interface accelerates code execution with a system * of instruction prefetch and cache lines on ITCM interface (ART * Accelerator™). @@ -872,7 +872,7 @@ static void stm32_stdclockconfig(void) { } -#if defined(CONFIG_STM32F7_LTDC) || defined(CONFIG_STM32F7_PLLSAI) +#if defined(CONFIG_STM32_LTDC) || defined(CONFIG_STM32_PLLSAI) /* Configure PLLSAI */ @@ -921,7 +921,7 @@ static void stm32_stdclockconfig(void) } #endif -#if defined(CONFIG_STM32F7_PLLI2S) || \ +#if defined(CONFIG_STM32_PLLI2S) || \ (STM32_RCC_DCKCFGR1_SAI1SRC == RCC_DCKCFGR1_SAI1SEL(1)) || \ (STM32_RCC_DCKCFGR1_SAI2SRC == RCC_DCKCFGR1_SAI2SEL(1)) @@ -990,13 +990,13 @@ static void stm32_stdclockconfig(void) putreg32(regval, STM32_RCC_DCKCFGR2); -#if defined(CONFIG_STM32F7_IWDG) || defined(CONFIG_STM32F7_RTC_LSICLOCK) +#if defined(CONFIG_STM32_IWDG) || defined(CONFIG_STM32_RTC_LSICLOCK) /* Low speed internal clock source LSI */ stm32_rcc_enablelsi(); #endif -#if defined(CONFIG_STM32F7_RTC_LSECLOCK) +#if defined(CONFIG_STM32_RTC_LSECLOCK) /* Low speed external clock source LSE * * TODO: There is another case where the LSE needs to @@ -1040,14 +1040,14 @@ static inline void rcc_enableperipherals(void) ****************************************************************************/ /**************************************************************************** - * Name: stm32f7x9_rcc_dsisrcphy + * Name: stm32_rcc_dsisrcphy * * Description: * Set DSI clock source to DSI PHY * ****************************************************************************/ -void stm32f7x9_rcc_dsisrcphy(void) +void stm32_rcc_dsisrcphy(void) { uint32_t regval; regval = getreg32(STM32_RCC_DCKCFGR2); @@ -1058,14 +1058,14 @@ void stm32f7x9_rcc_dsisrcphy(void) } /**************************************************************************** - * Name: stm32f7x9_rcc_dsisrcpllr + * Name: stm32_rcc_dsisrcpllr * * Description: * Set DSI clock source to PLLR * ****************************************************************************/ -void stm32f7x9_rcc_dsisrcpllr(void) +void stm32_rcc_dsisrcpllr(void) { uint32_t regval; regval = getreg32(STM32_RCC_DCKCFGR2); diff --git a/arch/arm/src/stm32g0/CMakeLists.txt b/arch/arm/src/stm32g0/CMakeLists.txt new file mode 100644 index 0000000000000..d2d126dda46d8 --- /dev/null +++ b/arch/arm/src/stm32g0/CMakeLists.txt @@ -0,0 +1,32 @@ +# ############################################################################## +# arch/arm/src/stm32g0/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(SRCS) + +list(APPEND SRCS stm32_rcc.c) + +if(CONFIG_BUILD_PROTECTED) + list(APPEND SRCS stm32_userspace.c) +endif() + +target_sources(arch PRIVATE ${SRCS}) +add_subdirectory(${NUTTX_DIR}/arch/arm/src/common/stm32 stm32_common) diff --git a/arch/arm/src/stm32g0/Kconfig b/arch/arm/src/stm32g0/Kconfig new file mode 100644 index 0000000000000..29f751b93534b --- /dev/null +++ b/arch/arm/src/stm32g0/Kconfig @@ -0,0 +1,429 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# +comment "STM32 G0 configuration" + +if ARCH_CHIP_STM32G0 + +choice + prompt "ST STM32G0 Chip Selection" + default ARCH_CHIP_STM32G071RB + depends on ARCH_CHIP_STM32G0 + +config ARCH_CHIP_STM32G070CB + bool "STM32G070CB" + select STM32_STM32G070 + select STM32_FLASH_CONFIG_B + depends on ARCH_CHIP_STM32G0 + +config ARCH_CHIP_STM32G070KB + bool "STM32G070KB" + select STM32_STM32G070 + select STM32_FLASH_CONFIG_B + depends on ARCH_CHIP_STM32G0 + +config ARCH_CHIP_STM32G070RB + bool "STM32G070RB" + select STM32_STM32G070 + select STM32_FLASH_CONFIG_B + depends on ARCH_CHIP_STM32G0 + +config ARCH_CHIP_STM32G071EB + bool "STM32G071EB" + select STM32_STM32G071 + select STM32_FLASH_CONFIG_B + depends on ARCH_CHIP_STM32G0 + +config ARCH_CHIP_STM32G071G8 + bool "STM32G071G8" + select STM32_STM32G071 + select STM32_FLASH_CONFIG_8 + depends on ARCH_CHIP_STM32G0 + +config ARCH_CHIP_STM32G071GB + bool "STM32G071GB" + select STM32_STM32G071 + select STM32_FLASH_CONFIG_B + depends on ARCH_CHIP_STM32G0 + +config ARCH_CHIP_STM32G071G8XN + bool "STM32G071G8XN" + select STM32_STM32G071 + select STM32_FLASH_CONFIG_8 + depends on ARCH_CHIP_STM32G0 + +config ARCH_CHIP_STM32G071GBXN + bool "STM32G071GBXN" + select STM32_STM32G071 + select STM32_FLASH_CONFIG_B + depends on ARCH_CHIP_STM32G0 + +config ARCH_CHIP_STM32G071K8 + bool "STM32G071K8" + select STM32_STM32G071 + select STM32_FLASH_CONFIG_8 + depends on ARCH_CHIP_STM32G0 + +config ARCH_CHIP_STM32G071KB + bool "STM32G071KB" + select STM32_STM32G071 + select STM32_FLASH_CONFIG_B + depends on ARCH_CHIP_STM32G0 + +config ARCH_CHIP_STM32G071K8XN + bool "STM32G071K8XN" + select STM32_STM32G071 + select STM32_FLASH_CONFIG_8 + depends on ARCH_CHIP_STM32G0 + +config ARCH_CHIP_STM32G071KBXN + bool "STM32G071KBXN" + select STM32_STM32G071 + select STM32_FLASH_CONFIG_B + depends on ARCH_CHIP_STM32G0 + +config ARCH_CHIP_STM32G071C8 + bool "STM32G071C8" + select STM32_STM32G071 + select STM32_FLASH_CONFIG_8 + depends on ARCH_CHIP_STM32G0 + +config ARCH_CHIP_STM32G071CB + bool "STM32G071CB" + select STM32_STM32G071 + select STM32_FLASH_CONFIG_B + depends on ARCH_CHIP_STM32G0 + +config ARCH_CHIP_STM32G071R8 + bool "STM32G071R8" + select STM32_STM32G071 + select STM32_FLASH_CONFIG_8 + depends on ARCH_CHIP_STM32G0 + +config ARCH_CHIP_STM32G071RB + bool "STM32G071RB" + select STM32_STM32G071 + select STM32_FLASH_CONFIG_B + depends on ARCH_CHIP_STM32G0 + +config ARCH_CHIP_STM32G0B1KB + bool "STM32G0B1KB" + select STM32_STM32G0B1 + select STM32_FLASH_CONFIG_B + depends on ARCH_CHIP_STM32G0 + +config ARCH_CHIP_STM32G0B1CB + bool "STM32G0B1CB" + select STM32_STM32G0B1 + select STM32_FLASH_CONFIG_B + depends on ARCH_CHIP_STM32G0 + +config ARCH_CHIP_STM32G0B1RB + bool "STM32G0B1RB" + select STM32_STM32G0B1 + select STM32_FLASH_CONFIG_B + depends on ARCH_CHIP_STM32G0 + +config ARCH_CHIP_STM32G0B1MB + bool "STM32G0B1MB" + select STM32_STM32G0B1 + select STM32_FLASH_CONFIG_B + depends on ARCH_CHIP_STM32G0 + +config ARCH_CHIP_STM32G0B1VB + bool "STM32G0B1VB" + select STM32_STM32G0B1 + select STM32_FLASH_CONFIG_B + depends on ARCH_CHIP_STM32G0 + +config ARCH_CHIP_STM32G0B1KC + bool "STM32G0B1KC" + select STM32_STM32G0B1 + select STM32_FLASH_CONFIG_C + depends on ARCH_CHIP_STM32G0 + +config ARCH_CHIP_STM32G0B1CC + bool "STM32G0B1CC" + select STM32_STM32G0B1 + select STM32_FLASH_CONFIG_C + depends on ARCH_CHIP_STM32G0 + +config ARCH_CHIP_STM32G0B1RC + bool "STM32G0B1RC" + select STM32_STM32G0B1 + select STM32_FLASH_CONFIG_C + depends on ARCH_CHIP_STM32G0 + +config ARCH_CHIP_STM32G0B1MC + bool "STM32G0B1MC" + select STM32_STM32G0B1 + select STM32_FLASH_CONFIG_C + depends on ARCH_CHIP_STM32G0 + +config ARCH_CHIP_STM32G0B1VC + bool "STM32G0B1VC" + select STM32_STM32G0B1 + select STM32_FLASH_CONFIG_C + depends on ARCH_CHIP_STM32G0 + +config ARCH_CHIP_STM32G0B1KE + bool "STM32G0B1KE" + select STM32_STM32G0B1 + select STM32_FLASH_CONFIG_E + depends on ARCH_CHIP_STM32G0 + +config ARCH_CHIP_STM32G0B1CE + bool "STM32G0B1CE" + select STM32_STM32G0B1 + select STM32_FLASH_CONFIG_E + depends on ARCH_CHIP_STM32G0 + +config ARCH_CHIP_STM32G0B1RE + bool "STM32G0B1RE" + select STM32_STM32G0B1 + select STM32_FLASH_CONFIG_E + depends on ARCH_CHIP_STM32G0 + +config ARCH_CHIP_STM32G0B1NE + bool "STM32G0B1NE" + select STM32_STM32G0B1 + select STM32_FLASH_CONFIG_E + depends on ARCH_CHIP_STM32G0 + +config ARCH_CHIP_STM32G0B1ME + bool "STM32G0B1ME" + select STM32_STM32G0B1 + select STM32_FLASH_CONFIG_E + depends on ARCH_CHIP_STM32G0 + +config ARCH_CHIP_STM32G0B1VE + bool "STM32G0B1VE" + select STM32_STM32G0B1 + select STM32_FLASH_CONFIG_E + depends on ARCH_CHIP_STM32G0 + +endchoice + +endif + +config STM32_STM32G0 + bool + default n + select STM32_HAVE_DMA1 + select STM32_HAVE_USART1 + select STM32_HAVE_USART2 + select STM32_HAVE_I2C1 + select STM32_HAVE_SPI1 + select STM32_HAVE_DMAMUX + select STM32_HAVE_IP_ADC_M0_V1 + select STM32_HAVE_IP_AES_M0_V1 if STM32_HAVE_AES + select STM32_HAVE_IP_COMP_M0_V1 if STM32_HAVE_COMP + select STM32_HAVE_IP_DAC_M0_V1 if STM32_HAVE_DAC1 + select STM32_HAVE_IP_DBGMCU_M0_V1 + select STM32_HAVE_IP_DMA_V1 + select STM32_HAVE_IP_DMA_V1_7CH_DMAMUX + select STM32_HAVE_IP_EXTI_V2 + select STM32_HAVE_IP_FDCAN_MCAN_M0_V1 + select STM32_HAVE_IP_FLASH_M0_V1 + select STM32_HAVE_IP_FLASH_M0_G0C0 + select STM32_HAVE_IP_GPIO_M0_V1 + select STM32_HAVE_IP_I2C_M0_V1 + select STM32_HAVE_IP_PWR_G0 + select STM32_HAVE_IP_RNG_M0_V1 if STM32_HAVE_RNG + select STM32_HAVE_IP_RTCC_M0_V1 + select STM32_HAVE_IP_SPI_V2 + select STM32_HAVE_IP_TIMERS_M0_V1 + select STM32_HAVE_IP_USART_V4 + select STM32_HAVE_IP_WDG_M0_V1 + select STM32_HAVE_IP_USBDEV_M0_V1 if STM32_HAVE_USBDEV + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM3 + select STM32_HAVE_TIM14 + select STM32_HAVE_TIM16 + select STM32_HAVE_TIM17 + select STM32_HAVE_I2C2 + select ARCH_HAVE_PROGMEM + +config STM32_STM32G030 + bool + default n + select STM32_STM32G0 + select STM32_STM32G03X + +config STM32_STM32G031 + bool + default n + select STM32_STM32G0 + select STM32_STM32G03X + select STM32_HAVE_LPUART1 + +config STM32_STM32G03X + bool + default n + +config STM32_STM32G041 + bool + default n + select STM32_STM32G0 + select STM32_HAVE_RNG + select STM32_HAVE_AES + select STM32_HAVE_LPUART1 + +config STM32_STM32G050 + bool + default n + select STM32_STM32G0 + select STM32_STM32G05X + +config STM32_STM32G051 + bool + default n + select STM32_STM32G0 + select STM32_STM32G05X + select STM32_HAVE_DAC1 + select STM32_HAVE_COMP1 + select STM32_HAVE_COMP2 + select STM32_HAVE_TIM15 + select STM32_HAVE_LPUART1 + +config STM32_STM32G05X + bool + default n + select STM32_HAVE_TIM6 + select STM32_HAVE_TIM7 + +config STM32_STM32G061 + bool + default n + select STM32_STM32G0 + select STM32_HAVE_RNG + select STM32_HAVE_AES + select STM32_HAVE_DAC1 + select STM32_HAVE_COMP1 + select STM32_HAVE_COMP2 + select STM32_HAVE_TIM6 + select STM32_HAVE_TIM7 + select STM32_HAVE_TIM15 + select STM32_HAVE_LPUART1 + +config STM32_STM32G070 + bool + default n + select STM32_STM32G0 + select STM32_STM32G07X + +config STM32_STM32G071 + bool + default n + select STM32_STM32G0 + select STM32_STM32G07X + select STM32_HAVE_DAC1 + select STM32_HAVE_COMP1 + select STM32_HAVE_COMP2 + select STM32_HAVE_CEC + select STM32_HAVE_LPUART1 + +config STM32_STM32G07X + bool + default n + select STM32_HAVE_USART3 + select STM32_HAVE_USART4 + select STM32_HAVE_TIM6 + select STM32_HAVE_TIM7 + select STM32_HAVE_TIM15 + select STM32_HAVE_UCPD1 + select STM32_HAVE_UCPD2 + +config STM32_STM32G081 + bool + default n + select STM32_STM32G0 + select STM32_HAVE_USART3 + select STM32_HAVE_USART4 + select STM32_HAVE_RNG + select STM32_HAVE_AES + select STM32_HAVE_DAC1 + select STM32_HAVE_COMP1 + select STM32_HAVE_COMP2 + select STM32_HAVE_TIM6 + select STM32_HAVE_TIM7 + select STM32_HAVE_TIM15 + select STM32_HAVE_UCPD1 + select STM32_HAVE_UCPD2 + select STM32_HAVE_CEC + select STM32_HAVE_LPUART1 + +config STM32_STM32G0B0 + bool + default n + select STM32_STM32G0 + select STM32_STM32G0BX + +config STM32_STM32G0B1 + bool + default n + select STM32_STM32G0 + select STM32_STM32G0BX + select STM32_HAVE_DAC1 + select STM32_HAVE_COMP1 + select STM32_HAVE_COMP2 + select STM32_HAVE_COMP3 + select STM32_HAVE_FDCAN1 + select STM32_HAVE_FDCAN2 + select STM32_HAVE_CEC + +config STM32_STM32G0BX + bool + default n + select STM32_HAVE_DMA2 + select STM32_HAVE_USART3 + select STM32_HAVE_USART4 + select STM32_HAVE_USART5 + select STM32_HAVE_USART6 + select STM32_HAVE_LPUART1 + select STM32_HAVE_LPUART2 + select STM32_HAVE_CRS + select STM32_HAVE_TIM4 + select STM32_HAVE_TIM6 + select STM32_HAVE_TIM7 + select STM32_HAVE_TIM15 + select STM32_HAVE_I2C3 + select STM32_HAVE_SPI3 + select STM32_HAVE_I2S2 + select STM32_HAVE_USBDEV + select STM32_HAVE_UCPD1 + select STM32_HAVE_UCPD2 + select STM32_HAVE_HSI48 + +config STM32_STM32G0C1 + bool + default n + select STM32_STM32G0 + select STM32_HAVE_DMA2 + select STM32_HAVE_USART3 + select STM32_HAVE_USART4 + select STM32_HAVE_USART5 + select STM32_HAVE_USART6 + select STM32_HAVE_CRS + select STM32_HAVE_RNG + select STM32_HAVE_AES + select STM32_HAVE_DAC1 + select STM32_HAVE_COMP1 + select STM32_HAVE_COMP2 + select STM32_HAVE_COMP3 + select STM32_HAVE_TIM4 + select STM32_HAVE_TIM6 + select STM32_HAVE_TIM7 + select STM32_HAVE_TIM15 + select STM32_HAVE_I2C3 + select STM32_HAVE_SPI3 + select STM32_HAVE_I2S2 + select STM32_HAVE_LPUART2 + select STM32_HAVE_USBDEV + select STM32_HAVE_UCPD1 + select STM32_HAVE_UCPD2 + select STM32_HAVE_FDCAN1 + select STM32_HAVE_FDCAN2 + select STM32_HAVE_CEC + select STM32_HAVE_HSI48 diff --git a/arch/arm/src/stm32g0/Make.defs b/arch/arm/src/stm32g0/Make.defs new file mode 100644 index 0000000000000..75f1a3a88a880 --- /dev/null +++ b/arch/arm/src/stm32g0/Make.defs @@ -0,0 +1,31 @@ +############################################################################ +# arch/arm/src/stm32g0/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include armv6-m/Make.defs + +CHIP_CSRCS = stm32_rcc.c + +ifeq ($(CONFIG_BUILD_PROTECTED),y) +CHIP_CSRCS += stm32_userspace.c +endif + +include common/stm32/Make.defs diff --git a/arch/arm/src/stm32g0/chip.h b/arch/arm/src/stm32g0/chip.h new file mode 100644 index 0000000000000..1569d0603c762 --- /dev/null +++ b/arch/arm/src/stm32g0/chip.h @@ -0,0 +1,44 @@ +/**************************************************************************** + * arch/arm/src/stm32g0/chip.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32G0_CHIP_H +#define __ARCH_ARM_SRC_STM32G0_CHIP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include "nvic.h" + +/* Include the chip capabilities file */ + +#include + +/* Include the memory map file. + * Other chip hardware files should then include this file for the proper + * setup. + */ + +#include "hardware/stm32_memorymap.h" + +#endif /* __ARCH_ARM_SRC_STM32G0_CHIP_H */ diff --git a/arch/arm/src/stm32g0/hardware/stm32_memorymap.h b/arch/arm/src/stm32g0/hardware/stm32_memorymap.h new file mode 100644 index 0000000000000..cd95640e9a64b --- /dev/null +++ b/arch/arm/src/stm32g0/hardware/stm32_memorymap.h @@ -0,0 +1,17 @@ +/**************************************************************************** + * arch/arm/src/stm32g0/hardware/stm32_memorymap.h + * + * SPDX-License-Identifier: Apache-2.0 + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32G0_HARDWARE_STM32_MEMORYMAP_H +#define __ARCH_ARM_SRC_STM32G0_HARDWARE_STM32_MEMORYMAP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "hardware/stm32g0_memorymap.h" + +#endif /* __ARCH_ARM_SRC_STM32G0_HARDWARE_STM32_MEMORYMAP_H */ diff --git a/arch/arm/src/stm32g0/hardware/stm32_pinmap.h b/arch/arm/src/stm32g0/hardware/stm32_pinmap.h new file mode 100644 index 0000000000000..56faffa2e66c7 --- /dev/null +++ b/arch/arm/src/stm32g0/hardware/stm32_pinmap.h @@ -0,0 +1,17 @@ +/**************************************************************************** + * arch/arm/src/stm32g0/hardware/stm32_pinmap.h + * + * SPDX-License-Identifier: Apache-2.0 + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32G0_HARDWARE_STM32_PINMAP_H +#define __ARCH_ARM_SRC_STM32G0_HARDWARE_STM32_PINMAP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "hardware/stm32g0_pinmap.h" + +#endif /* __ARCH_ARM_SRC_STM32G0_HARDWARE_STM32_PINMAP_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32g0_dmamux.h b/arch/arm/src/stm32g0/hardware/stm32g0_dmamux.h similarity index 98% rename from arch/arm/src/stm32f0l0g0/hardware/stm32g0_dmamux.h rename to arch/arm/src/stm32g0/hardware/stm32g0_dmamux.h index 2f1161c7d3777..d8ac7f51795bb 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32g0_dmamux.h +++ b/arch/arm/src/stm32g0/hardware/stm32g0_dmamux.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32g0_dmamux.h + * arch/arm/src/stm32g0/hardware/stm32g0_dmamux.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32G0_DMAMUX_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32G0_DMAMUX_H +#ifndef __ARCH_ARM_SRC_STM32G0_HARDWARE_STM32G0_DMAMUX_H +#define __ARCH_ARM_SRC_STM32G0_HARDWARE_STM32G0_DMAMUX_H /**************************************************************************** * Included Files @@ -322,4 +322,4 @@ #define DMAMUX_SYNC_LPTIM2_OUT 21 #define DMAMUX_SYNC_TIM14_OC 22 -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32G0_DMAMUX_H */ +#endif /* __ARCH_ARM_SRC_STM32G0_HARDWARE_STM32G0_DMAMUX_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32g0_exti.h b/arch/arm/src/stm32g0/hardware/stm32g0_exti.h similarity index 95% rename from arch/arm/src/stm32f0l0g0/hardware/stm32g0_exti.h rename to arch/arm/src/stm32g0/hardware/stm32g0_exti.h index bfbd8802918f9..695a57836a50c 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32g0_exti.h +++ b/arch/arm/src/stm32g0/hardware/stm32g0_exti.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32g0_exti.h + * arch/arm/src/stm32g0/hardware/stm32g0_exti.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32G0_EXTI_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32G0_EXTI_H +#ifndef __ARCH_ARM_SRC_STM32G0_HARDWARE_STM32G0_EXTI_H +#define __ARCH_ARM_SRC_STM32G0_HARDWARE_STM32G0_EXTI_H /**************************************************************************** * Included Files @@ -87,4 +87,4 @@ /* TODO */ -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32G0_EXTI_H */ +#endif /* __ARCH_ARM_SRC_STM32G0_HARDWARE_STM32G0_EXTI_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32g0_flash.h b/arch/arm/src/stm32g0/hardware/stm32g0_flash.h similarity index 98% rename from arch/arm/src/stm32f0l0g0/hardware/stm32g0_flash.h rename to arch/arm/src/stm32g0/hardware/stm32g0_flash.h index 5d5780116bf01..779011abd8313 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32g0_flash.h +++ b/arch/arm/src/stm32g0/hardware/stm32g0_flash.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32g0_flash.h + * arch/arm/src/stm32g0/hardware/stm32g0_flash.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32G0_FLASH_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32G0_FLASH_H +#ifndef __ARCH_ARM_SRC_STM32G0_HARDWARE_STM32G0_FLASH_H +#define __ARCH_ARM_SRC_STM32G0_HARDWARE_STM32G0_FLASH_H /**************************************************************************** * Included Files @@ -279,4 +279,4 @@ #define FLASH_SECR_SEC_SIZE2_MASK (0xff << FLASH_SECR_SEC_SIZE2_SHIFT) /* Bits 28-31: Reserved */ -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32G0_FLASH_H */ +#endif /* __ARCH_ARM_SRC_STM32G0_HARDWARE_STM32G0_FLASH_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32g0_memorymap.h b/arch/arm/src/stm32g0/hardware/stm32g0_memorymap.h similarity index 96% rename from arch/arm/src/stm32f0l0g0/hardware/stm32g0_memorymap.h rename to arch/arm/src/stm32g0/hardware/stm32g0_memorymap.h index 595e1886b4cfa..c5455b4df9729 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32g0_memorymap.h +++ b/arch/arm/src/stm32g0/hardware/stm32g0_memorymap.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32g0_memorymap.h + * arch/arm/src/stm32g0/hardware/stm32g0_memorymap.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32G0_MEMORYMAP_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32G0_MEMORYMAP_H +#ifndef __ARCH_ARM_SRC_STM32G0_HARDWARE_STM32G0_MEMORYMAP_H +#define __ARCH_ARM_SRC_STM32G0_HARDWARE_STM32G0_MEMORYMAP_H /**************************************************************************** * Pre-processor Definitions @@ -131,4 +131,4 @@ #define STM32_SYSMEM_UID 0x1fff7590 /* The 96-bit unique device identifier */ -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32G0_MEMORYMAP_H */ +#endif /* __ARCH_ARM_SRC_STM32G0_HARDWARE_STM32G0_MEMORYMAP_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32g0_pinmap.h b/arch/arm/src/stm32g0/hardware/stm32g0_pinmap.h similarity index 98% rename from arch/arm/src/stm32f0l0g0/hardware/stm32g0_pinmap.h rename to arch/arm/src/stm32g0/hardware/stm32g0_pinmap.h index efbb5415b7448..3cc3b5b08500e 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32g0_pinmap.h +++ b/arch/arm/src/stm32g0/hardware/stm32g0_pinmap.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32g0_pinmap.h + * arch/arm/src/stm32g0/hardware/stm32g0_pinmap.h * * SPDX-License-Identifier: BSD-3-Clause * SPDX-FileCopyrightText: 2019 Gregory Nutt. All rights reserved. @@ -36,8 +36,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32G0_PINMAP_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32G0_PINMAP_H +#ifndef __ARCH_ARM_SRC_STM32G0_HARDWARE_STM32G0_PINMAP_H +#define __ARCH_ARM_SRC_STM32G0_HARDWARE_STM32G0_PINMAP_H /**************************************************************************** * Included Files @@ -283,4 +283,4 @@ /* TODO: CEC */ -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32G0_PINMAP_H */ +#endif /* __ARCH_ARM_SRC_STM32G0_HARDWARE_STM32G0_PINMAP_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32g0_pwr.h b/arch/arm/src/stm32g0/hardware/stm32g0_pwr.h similarity index 97% rename from arch/arm/src/stm32f0l0g0/hardware/stm32g0_pwr.h rename to arch/arm/src/stm32g0/hardware/stm32g0_pwr.h index ae226f9fca6aa..2df357db170b9 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32g0_pwr.h +++ b/arch/arm/src/stm32g0/hardware/stm32g0_pwr.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32g0_pwr.h + * arch/arm/src/stm32g0/hardware/stm32g0_pwr.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32G0_PWR_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32G0_PWR_H +#ifndef __ARCH_ARM_SRC_STM32G0_HARDWARE_STM32G0_PWR_H +#define __ARCH_ARM_SRC_STM32G0_HARDWARE_STM32G0_PWR_H /**************************************************************************** * Included Files @@ -175,4 +175,4 @@ #define PWR_SCR_CWUF5 (1 << 4) /* Bit 4: Clear wakeup flag 5 */ #define PWR_SCR_CSBF (1 << 8) /* Bit 8: Clear standby flag */ -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32G0_PWR_H */ +#endif /* __ARCH_ARM_SRC_STM32G0_HARDWARE_STM32G0_PWR_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32g0_rcc.h b/arch/arm/src/stm32g0/hardware/stm32g0_rcc.h similarity index 99% rename from arch/arm/src/stm32f0l0g0/hardware/stm32g0_rcc.h rename to arch/arm/src/stm32g0/hardware/stm32g0_rcc.h index 940cb9e6ba2ca..3c5f8ca45217e 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32g0_rcc.h +++ b/arch/arm/src/stm32g0/hardware/stm32g0_rcc.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32g0_rcc.h + * arch/arm/src/stm32g0/hardware/stm32g0_rcc.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32G0_RCC_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32G0_RCC_H +#ifndef __ARCH_ARM_SRC_STM32G0_HARDWARE_STM32G0_RCC_H +#define __ARCH_ARM_SRC_STM32G0_HARDWARE_STM32G0_RCC_H /**************************************************************************** * Pre-processor Definitions @@ -363,4 +363,4 @@ #define RCC_CSR_WWDGRSTF (1 << 30) /* Bit 30: WWDG reset flag */ #define RCC_CSR_LPWRRSTF (1 << 31) /* Bit 31: Low-power reset flag */ -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32G0_RCC_H */ +#endif /* __ARCH_ARM_SRC_STM32G0_HARDWARE_STM32G0_RCC_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32g0_syscfg.h b/arch/arm/src/stm32g0/hardware/stm32g0_syscfg.h similarity index 98% rename from arch/arm/src/stm32f0l0g0/hardware/stm32g0_syscfg.h rename to arch/arm/src/stm32g0/hardware/stm32g0_syscfg.h index cb4f9bb9c39d5..7ca1ecbbce17d 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32g0_syscfg.h +++ b/arch/arm/src/stm32g0/hardware/stm32g0_syscfg.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32g0_syscfg.h + * arch/arm/src/stm32g0/hardware/stm32g0_syscfg.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32G0_SYSCFG_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32G0_SYSCFG_H +#ifndef __ARCH_ARM_SRC_STM32G0_HARDWARE_STM32G0_SYSCFG_H +#define __ARCH_ARM_SRC_STM32G0_HARDWARE_STM32G0_SYSCFG_H /**************************************************************************** * Included Files @@ -300,4 +300,4 @@ #define SYSCFG_ITLINE30_RNG (1 << 0) /* Bit 0: RNG interrupt request pending */ #define SYSCFG_ITLINE30_AES (1 << 1) /* Bit 1: AES interrupt request pending */ -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32G0_SYSCFG_H */ +#endif /* __ARCH_ARM_SRC_STM32G0_HARDWARE_STM32G0_SYSCFG_H */ diff --git a/arch/arm/src/stm32g0/stm32.h b/arch/arm/src/stm32g0/stm32.h new file mode 100644 index 0000000000000..9e70f1bf95f02 --- /dev/null +++ b/arch/arm/src/stm32g0/stm32.h @@ -0,0 +1,54 @@ +/**************************************************************************** + * arch/arm/src/stm32g0/stm32.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32G0_STM32_H +#define __ARCH_ARM_SRC_STM32G0_STM32_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include +#include + +#include "arm_internal.h" + +/* Peripherals **************************************************************/ + +#include "chip.h" +#include "stm32_dma.h" +#include "stm32_gpio.h" +#include "stm32_i2c.h" +#include "stm32_pwr.h" +#include "stm32_rcc.h" +#include "stm32_spi.h" +#include "stm32_uart.h" +#include "stm32_lowputc.h" +#include "stm32_adc.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#endif /* __ARCH_ARM_SRC_STM32G0_STM32_H */ diff --git a/arch/arm/src/stm32g0/stm32_rcc.c b/arch/arm/src/stm32g0/stm32_rcc.c new file mode 100644 index 0000000000000..f2f084012f86e --- /dev/null +++ b/arch/arm/src/stm32g0/stm32_rcc.c @@ -0,0 +1,220 @@ +/**************************************************************************** + * arch/arm/src/stm32g0/stm32_rcc.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include + +#include "arm_internal.h" +#include "hardware/stm32_flash.h" +#include "stm32_rcc.h" +#include "stm32_hsi48_m0_v1.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifdef CONFIG_STM32_RNG +# ifndef STM32_USE_CLK48 +# error RNG requires CLK48 enabled +# endif +#endif + +#ifdef CONFIG_STM32_USB +# ifndef STM32_USE_CLK48 +# error USB requires CLK48 enabled +# endif +#endif + +static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1, + "Configure BOARD_LOOPSPERMSEC to non-default value."); + +/* Allow up to 100 milliseconds for the high speed clock to become ready. + * that is a very long delay, but if the clock does not become ready we are + * hosed anyway. + */ + +#define HSERDY_TIMEOUT (100 * CONFIG_BOARD_LOOPSPERMSEC) + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/* Include chip-specific clocking initialization logic */ + +#include "stm32g0_rcc.c" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: rcc_resetbkp + * + * Description: + * The RTC needs to reset the Backup Domain to change RTCSEL and resetting + * the Backup Domain renders to disabling the LSE as consequence. + * In order to avoid resetting the Backup Domain when we already configured + * LSE we will reset the Backup Domain early (here). + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +#if defined(CONFIG_STM32_RTC) && defined(CONFIG_STM32_PWR) +static inline void rcc_resetbkp(void) +{ + uint32_t regval; + + /* Check if the RTC is already configured */ + + stm32_pwr_initbkp(false); + + regval = getreg32(RTC_MAGIC_REG); + if (regval != RTC_MAGIC && regval != RTC_MAGIC_TIME_SET) + { + stm32_pwr_enablebkp(true); + + /* We might be changing RTCSEL - to ensure such changes work, we must + * reset the backup domain (having backed up the RTC_MAGIC token) + */ + + modifyreg32(STM32_RCC_BDCR, 0, RCC_BDCR_BDRST); + modifyreg32(STM32_RCC_BDCR, RCC_BDCR_BDRST, 0); + + stm32_pwr_enablebkp(false); + } +} +#else +# define rcc_resetbkp() +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_clockconfig + * + * Description: + * Called to establish the clock settings based on the values in board.h. + * This function (by default) will reset most everything, enable the PLL, + * and enable peripheral clocking for all peripherals enabled in the NuttX + * configuration file. + * + * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then + * clocking will be enabled by an externally provided, board-specific + * function called stm32_board_clockconfig(). + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void stm32_clockconfig(void) +{ + /* Make sure that we are starting in the reset state */ + + rcc_reset(); + + /* Reset backup domain if appropriate */ + + rcc_resetbkp(); + +#if defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) + /* Invoke Board Custom Clock Configuration */ + + stm32_board_clockconfig(); + +#else + /* Invoke standard, fixed clock configuration based on definitions + * in board.h + */ + + stm32_stdclockconfig(); + +#endif + + /* Enable peripheral clocking */ + + rcc_enableperipherals(); +} + +/**************************************************************************** + * Name: stm32_clockenable + * + * Description: + * Re-enable the clock and restore the clock settings based on settings in + * board.h. This function is only available to support low-power modes of + * operation: When re-awakening from deep-sleep modes, it is necessary to + * re-enable/re-start the PLL + * + * This functional performs a subset of the operations performed by + * stm32_clockconfig(): It does not reset any devices, and it does not + * reset the currently enabled peripheral clocks. + * + * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then + * clocking will be enabled by an externally provided, board-specific + * function called stm32_board_clockconfig(). + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_PM +void stm32_clockenable(void) +{ +#if defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) + /* Invoke Board Custom Clock Configuration */ + + stm32_board_clockconfig(); + +#else + /* Invoke standard, fixed clock configuration based on definitions + * in board.h + */ + + stm32_stdclockconfig(); + +#endif +} +#endif diff --git a/arch/arm/src/stm32f0l0g0/stm32g0_rcc.c b/arch/arm/src/stm32g0/stm32g0_rcc.c similarity index 91% rename from arch/arm/src/stm32f0l0g0/stm32g0_rcc.c rename to arch/arm/src/stm32g0/stm32g0_rcc.c index b12d4ea61baac..b79a0224392b8 100644 --- a/arch/arm/src/stm32f0l0g0/stm32g0_rcc.c +++ b/arch/arm/src/stm32g0/stm32g0_rcc.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32g0_rcc.c + * arch/arm/src/stm32g0/stm32g0_rcc.c * * SPDX-License-Identifier: Apache-2.0 * @@ -124,37 +124,37 @@ static inline void rcc_enableahb(void) regval = getreg32(STM32_RCC_AHBENR); -#ifdef CONFIG_STM32F0L0G0_DMA1 +#ifdef CONFIG_STM32_DMA1 /* DMA 1 clock enable */ regval |= RCC_AHBENR_DMA1EN; #endif -#ifdef CONFIG_STM32F0L0G0_DMA2 +#ifdef CONFIG_STM32_DMA2 /* DMA 1 clock enable */ regval |= RCC_AHBENR_DMA2EN; #endif -#ifdef CONFIG_STM32F0L0G0_MIF +#ifdef CONFIG_STM32_MIF /* Memory interface clock enable */ regval |= RCC_AHBENR_MIFEN; #endif -#ifdef CONFIG_STM32F0L0G0_CRC +#ifdef CONFIG_STM32_CRC /* CRC clock enable */ regval |= RCC_AHBENR_CRCEN; #endif -#ifdef CONFIG_STM32F0L0G0_RNG +#ifdef CONFIG_STM32_RNG /* Random number generator clock enable */ regval |= RCC_AHBENR_RNGEN; #endif -#ifdef CONFIG_STM32F0L0G0_AES +#ifdef CONFIG_STM32_AES /* AES modules clock enable */ regval |= RCC_AHBENR_AESEN; @@ -181,91 +181,91 @@ static inline void rcc_enableapb1(void) regval = getreg32(STM32_RCC_APB1ENR); -#ifdef CONFIG_STM32F0L0G0_TIM2 +#ifdef CONFIG_STM32_TIM2 /* Timer 2 clock enable */ regval |= RCC_APB1ENR_TIM2EN; #endif -#ifdef CONFIG_STM32F0L0G0_TIM3 +#ifdef CONFIG_STM32_TIM3 /* Timer 3 clock enable */ regval |= RCC_APB1ENR_TIM3EN; #endif -#ifdef CONFIG_STM32F0L0G0_TIM6 +#ifdef CONFIG_STM32_TIM6 /* Timer 6 clock enable */ regval |= RCC_APB1ENR_TIM6EN; #endif -#ifdef CONFIG_STM32F0L0G0_TIM7 +#ifdef CONFIG_STM32_TIM7 /* Timer 7 clock enable */ regval |= RCC_APB1ENR_TIM7EN; #endif -#ifdef CONFIG_STM32F0L0G0_SPI2 +#ifdef CONFIG_STM32_SPI2 /* SPI 2 clock enable */ regval |= RCC_APB1ENR_SPI2EN; #endif -#ifdef CONFIG_STM32F0L0G0_USART2 +#ifdef CONFIG_STM32_USART2 /* USART 2 clock enable */ regval |= RCC_APB1ENR_USART2EN; #endif -#ifdef CONFIG_STM32F0L0G0_USART3 +#ifdef CONFIG_STM32_USART3 /* USART 3 clock enable */ regval |= RCC_APB1ENR_USART3EN; #endif -#ifdef CONFIG_STM32F0L0G0_USART4 +#ifdef CONFIG_STM32_USART4 /* USART 4 clock enable */ regval |= RCC_APB1ENR_USART4EN; #endif -#ifdef CONFIG_STM32F0L0G0_LPUSART1 +#ifdef CONFIG_STM32_LPUSART1 /* USART 5 clock enable */ regval |= RCC_APB1ENR_LPUSART1EN; #endif -#ifdef CONFIG_STM32F0L0G0_I2C1 +#ifdef CONFIG_STM32_I2C1 /* I2C 1 clock enable */ regval |= RCC_APB1ENR_I2C1EN; #endif -#ifdef CONFIG_STM32F0L0G0_I2C2 +#ifdef CONFIG_STM32_I2C2 /* I2C 2 clock enable */ regval |= RCC_APB1ENR_I2C2EN; #endif -#ifdef CONFIG_STM32F0L0G0_PWR +#ifdef CONFIG_STM32_PWR /* Power interface clock enable */ regval |= RCC_APB1ENR_PWREN; #endif -#ifdef CONFIG_STM32F0L0G0_DAC1 +#ifdef CONFIG_STM32_DAC1 /* DAC 1 interface clock enable */ regval |= RCC_APB1ENR_DAC1EN; #endif -#ifdef CONFIG_STM32F0L0G0_LPTIM1 +#ifdef CONFIG_STM32_LPTIM1 /* LPTIM1 clock enable */ regval |= RCC_APB1ENR_LPTIM1EN; #endif -#ifdef CONFIG_STM32F0L0G0_LPTIM2 +#ifdef CONFIG_STM32_LPTIM2 /* LPTIM2 clock enable */ regval |= RCC_APB1ENR_LPTIM2EN; @@ -292,55 +292,55 @@ static inline void rcc_enableapb2(void) regval = getreg32(STM32_RCC_APB2ENR); -#ifdef CONFIG_STM32F0L0G0_SYSCFG +#ifdef CONFIG_STM32_SYSCFG /* SYSCFG clock */ regval |= RCC_APB2ENR_SYSCFGEN; #endif -#ifdef CONFIG_STM32F0L0G0_TIM1 +#ifdef CONFIG_STM32_TIM1 /* TIM1 Timer clock enable */ regval |= RCC_APB2ENR_TIM1EN; #endif -#ifdef CONFIG_STM32F0L0G0_SPI1 +#ifdef CONFIG_STM32_SPI1 /* SPI 1 clock enable */ regval |= RCC_APB2ENR_SPI1EN; #endif -#ifdef CONFIG_STM32F0L0G0_USART1 +#ifdef CONFIG_STM32_USART1 /* USART1 clock enable */ regval |= RCC_APB2ENR_USART1EN; #endif -#ifdef CONFIG_STM32F0L0G0_TIM14 +#ifdef CONFIG_STM32_TIM14 /* TIM14 Timer clock enable */ regval |= RCC_APB2ENR_TIM14EN; #endif -#ifdef CONFIG_STM32F0L0G0_TIM15 +#ifdef CONFIG_STM32_TIM15 /* TIM5 Timer clock enable */ regval |= RCC_APB2ENR_TIM15EN; #endif -#ifdef CONFIG_STM32F0L0G0_TIM16 +#ifdef CONFIG_STM32_TIM16 /* TIM16 Timer clock enable */ regval |= RCC_APB2ENR_TIM16EN; #endif -#ifdef CONFIG_STM32F0L0G0_TIM17 +#ifdef CONFIG_STM32_TIM17 /* TIM17 Timer clock enable */ regval |= RCC_APB2ENR_TIM17EN; #endif -#ifdef CONFIG_STM32F0L0G0_ADC1 +#ifdef CONFIG_STM32_ADC1 /* ADC 1 clock enable */ regval |= RCC_APB2ENR_ADC1EN; @@ -407,14 +407,14 @@ static inline bool stm32_rcc_enablehse(void) * ****************************************************************************/ -#ifndef CONFIG_ARCH_BOARD_STM32F0G0L0_CUSTOM_CLOCKCONFIG +#ifndef CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG static void stm32_stdclockconfig(void) { uint32_t regval; -#if defined(CONFIG_STM32F0L0G0_RTC_HSECLOCK) || defined(CONFIG_LCD_HSECLOCK) +#if defined(CONFIG_STM32_RTC_HSECLOCK) || defined(CONFIG_LCD_HSECLOCK) uint16_t pwrcr; #endif -#ifdef CONFIG_STM32F0L0G0_PWR +#ifdef CONFIG_STM32_PWR uint32_t pwr_vos; #endif uint32_t flash_ws; @@ -451,7 +451,7 @@ static void stm32_stdclockconfig(void) if (STM32_SYSCLK_FREQUENCY > 16000000) { -#ifdef CONFIG_STM32F0L0G0_PWR +#ifdef CONFIG_STM32_PWR pwr_vos = PWR_CR1_VOS_RANGE1; #endif @@ -470,7 +470,7 @@ static void stm32_stdclockconfig(void) } else { -#ifdef CONFIG_STM32F0L0G0_PWR +#ifdef CONFIG_STM32_PWR pwr_vos = PWR_CR1_VOS_RANGE2; #endif @@ -484,11 +484,11 @@ static void stm32_stdclockconfig(void) } } -#ifdef CONFIG_STM32F0L0G0_PWR +#ifdef CONFIG_STM32_PWR stm32_pwr_setvos(pwr_vos); #endif -#if defined(CONFIG_STM32F0L0G0_RTC_HSECLOCK) || defined(CONFIG_LCD_HSECLOCK) +#if defined(CONFIG_STM32_RTC_HSECLOCK) || defined(CONFIG_LCD_HSECLOCK) /* If RTC / LCD selects HSE as clock source, the RTC prescaler * needs to be set before HSEON bit is set. */ @@ -626,8 +626,8 @@ static void stm32_stdclockconfig(void) while ((getreg32(STM32_RCC_CFGR) & RCC_CFGR_SWS_MASK) != STM32_SYSCLK_SWS); -#if defined(CONFIG_STM32F0L0G0_IWDG) || \ - defined(CONFIG_STM32F0L0G0_RTC_LSICLOCK) || defined(CONFIG_LCD_LSICLOCK) +#if defined(CONFIG_STM32_IWDG) || \ + defined(CONFIG_STM32_RTC_LSICLOCK) || defined(CONFIG_LCD_LSICLOCK) /* Low speed internal clock source LSI * * TODO: There is another case where the LSI needs to @@ -638,7 +638,7 @@ static void stm32_stdclockconfig(void) #endif -#if defined(CONFIG_STM32F0L0G0_RTC_LSECLOCK) || defined(CONFIG_LCD_LSECLOCK) +#if defined(CONFIG_STM32_RTC_LSECLOCK) || defined(CONFIG_LCD_LSECLOCK) /* Low speed external clock source LSE * * TODO: There is another case where the LSE needs to diff --git a/arch/arm/src/stm32g4/CMakeLists.txt b/arch/arm/src/stm32g4/CMakeLists.txt new file mode 100644 index 0000000000000..24e6c94b34226 --- /dev/null +++ b/arch/arm/src/stm32g4/CMakeLists.txt @@ -0,0 +1,28 @@ +# ############################################################################## +# arch/arm/src/stm32g4/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(SRCS) + +list(APPEND SRCS stm32_rcc.c) + +target_sources(arch PRIVATE ${SRCS}) +add_subdirectory(${NUTTX_DIR}/arch/arm/src/common/stm32 stm32_common) diff --git a/arch/arm/src/stm32g4/Kconfig b/arch/arm/src/stm32g4/Kconfig new file mode 100644 index 0000000000000..b46ea854ddfe0 --- /dev/null +++ b/arch/arm/src/stm32g4/Kconfig @@ -0,0 +1,335 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# +comment "STM32 G4 configuration" + +if ARCH_CHIP_STM32G4 + +choice + prompt "STM32G4 Chip Selection" + depends on ARCH_CHIP_STM32G4 + +config ARCH_CHIP_STM32G431K + bool "STM32G431K" + select STM32_STM32G43XX + select STM32_STM32G4XXK + select STM32_STM32G431K + +config ARCH_CHIP_STM32G431C + bool "STM32G431C" + select STM32_STM32G43XX + select STM32_STM32G4XXC + select STM32_STM32G431C + +config ARCH_CHIP_STM32G431R + bool "STM32G431R" + select STM32_STM32G43XX + select STM32_STM32G4XXR + select STM32_STM32G431R + +config ARCH_CHIP_STM32G431M + bool "STM32G431M" + select STM32_STM32G43XX + select STM32_STM32G4XXM + select STM32_STM32G431M + +config ARCH_CHIP_STM32G431V + bool "STM32G431V" + select STM32_STM32G43XX + select STM32_STM32G4XXV + select STM32_STM32G431V + +config ARCH_CHIP_STM32G474C + bool "STM32G474C" + select STM32_STM32G47XX + select STM32_STM32G4XXC + select STM32_STM32G474C + +config ARCH_CHIP_STM32G474M + bool "STM32G474M" + select STM32_STM32G47XX + select STM32_STM32G4XXM + select STM32_STM32G474M + +config ARCH_CHIP_STM32G474R + bool "STM32G474R" + select STM32_STM32G47XX + select STM32_STM32G4XXR + select STM32_STM32G474R + select STM32_HAVE_USBFS + +config ARCH_CHIP_STM32G474Q + bool "STM32G474Q" + select STM32_STM32G47XX + select STM32_STM32G4XXQ + select STM32_STM32G474Q + +config ARCH_CHIP_STM32G474V + bool "STM32G474V" + select STM32_STM32G47XX + select STM32_STM32G4XXV + select STM32_STM32G474V + +endchoice + +endif + +config STM32_STM32G4XXX + bool + default n + select STM32_HAVE_DMA1 + select STM32_HAVE_COMP + select STM32_HAVE_DMA2 + select ARCH_CORTEXM4 + select ARCH_HAVE_FPU + select STM32_HAVE_I2C1 + select STM32_HAVE_SPI1 + select STM32_HAVE_SYSCFG + select STM32_HAVE_USART1 + select STM32_HAVE_USART2 + select STM32_HAVE_DMAMUX + select STM32_HAVE_IP_AES_M3M4_V1 if STM32_HAVE_AES + select STM32_HAVE_IP_BBSRAM_M3M4_V1 + select STM32_HAVE_IP_BKP_M3M4_V1 + select STM32_HAVE_IP_CAN_BXCAN_M3M4_V1 + select STM32_HAVE_IP_CCM_M3M4_V1 if STM32_HAVE_CCM + select STM32_HAVE_IP_CRYPTO_M3M4_V1 + select STM32_HAVE_IP_DBGMCU_M3M4_V3 + select STM32_HAVE_IP_ADC_M3M4_V2 + select STM32_FOC_HAVE_ADC_CHAN0_WORKAROUND + select STM32_HAVE_COMMON_FOC + select STM32_HAVE_IP_COMP_M3M4_V2 + select STM32_HAVE_IP_CORDIC_M3M4_V1 if STM32_HAVE_CORDIC + select STM32_HAVE_IP_DAC_M3M4_V2 + select STM32_HAVE_IP_DCMI_V1 + select STM32_HAVE_IP_DFUMODE_M3M4_V1 + select STM32_HAVE_IP_DMA_V1 + select STM32_HAVE_IP_DMA_V1_8CH_DMAMUX + select STM32_HAVE_IP_EXTI_V2 + select STM32_HAVE_IP_ETHMAC_M3M4_V1 if STM32_HAVE_ETHMAC + select STM32_HAVE_IP_FDCAN_MCAN_M3M4_V1 + select STM32_HAVE_IP_FLASH_M3M4_V1 + select STM32_HAVE_IP_FLASH_M3M4_G4 + select STM32_HAVE_IP_FMC_M3M4_V1 if STM32_HAVE_FMC + select STM32_HAVE_IP_FREERUN_M3M4_V1 + select STM32_HAVE_IP_FSMC_M3M4_V1 if STM32_HAVE_FSMC + select STM32_HAVE_IP_GPIO_M3M4_V1 + select STM32_HAVE_IP_HRTIM_M3M4_V1 if STM32_HAVE_HRTIM1 + select STM32_HAVE_IP_I2C_M3M4_V2 + select STM32_HAVE_IP_I2S_M3M4_V1 + select STM32_HAVE_IP_ONESHOT_M3M4_V1 + select STM32_HAVE_IP_OPAMP_M3M4_V1 if STM32_HAVE_OPAMP1 || STM32_HAVE_OPAMP2 || STM32_HAVE_OPAMP3 || STM32_HAVE_OPAMP4 || STM32_HAVE_OPAMP5 || STM32_HAVE_OPAMP6 + select STM32_HAVE_IP_PWR_M3M4_V1 + select STM32_HAVE_IP_RNG_M3M4_V1 if STM32_HAVE_RNG + select STM32_HAVE_IP_RTC_M3M4_V1 + select STM32_HAVE_IP_RTCC_M3M4_V1 + select STM32_HAVE_IP_SPI_V3 + select STM32_HAVE_IP_SYSCFG_M3M4_V1 + select STM32_HAVE_IP_TIMERS_M3M4_V3 + select STM32_HAVE_IP_USART_V4 + select STM32_HAVE_IP_USBDEV_M3M4_V1 if STM32_HAVE_USBDEV + select STM32_HAVE_IP_USBFS_M3M4_V1 if STM32_HAVE_USBFS + select STM32_HAVE_IP_OTGFS_M3M4_V1 if STM32_HAVE_OTGFS + select STM32_HAVE_IP_WDG_M3M4_V1 + +config STM32_STM32G4_CAT2 + bool + default n + +config STM32_STM32G4_CAT3 + bool + default n + +config STM32_STM32G4_CAT4 + bool + default n + +config STM32_STM32G4XXK + bool + default n + +config STM32_STM32G4XXC + bool + default n + +config STM32_STM32G4XXR + bool + default n + +config STM32_STM32G4XXM + bool + default n + +config STM32_STM32G4XXV + bool + default n + +config STM32_STM32G4XXP + bool + default n + +config STM32_STM32G4XXQ + bool + default n + +config STM32_STM32G43XX + bool + default n + select STM32_STM32G4XXX + select STM32_STM32G4_CAT2 + select STM32_HAVE_ADC2 + select STM32_HAVE_CCM + select STM32_HAVE_COMP1 + select STM32_HAVE_COMP2 + select STM32_HAVE_COMP3 + select STM32_HAVE_COMP4 + select STM32_HAVE_CORDIC + select STM32_HAVE_CRS + select STM32_HAVE_DAC1 + select STM32_HAVE_DAC3 + select STM32_HAVE_FMAC + select STM32_HAVE_FDCAN1 + select STM32_HAVE_I2C2 + select STM32_HAVE_I2C3 + select STM32_HAVE_LPTIM1 + select STM32_HAVE_LPUART1 + select STM32_HAVE_OPAMP1 + select STM32_HAVE_OPAMP2 + select STM32_HAVE_OPAMP3 + select STM32_HAVE_RNG + select STM32_HAVE_SPI2 + select STM32_HAVE_SPI3 + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM15 + select STM32_HAVE_TIM16 + select STM32_HAVE_TIM17 + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM3 + select STM32_HAVE_TIM4 + select STM32_HAVE_TIM8 + select STM32_HAVE_UCPD + select STM32_HAVE_USBDEV + +config STM32_STM32G431K + bool + default n + +config STM32_STM32G431C + bool + default n + select STM32_HAVE_USART3 + +config STM32_STM32G431R + bool + default n + select STM32_HAVE_USART3 + select STM32_HAVE_UART4 + +config STM32_STM32G431M + bool + default n + select STM32_HAVE_USART3 + select STM32_HAVE_UART4 + +config STM32_STM32G431V + bool + default n + select STM32_HAVE_USART3 + select STM32_HAVE_UART4 + +config STM32_STM32G47XX + bool + default n + select STM32_STM32G4XXX + select STM32_STM32G4_CAT3 + select STM32_HAVE_ADC2 + select STM32_HAVE_ADC3 + select STM32_HAVE_ADC4 + select STM32_HAVE_ADC5 + select STM32_HAVE_CCM + select STM32_HAVE_COMP1 + select STM32_HAVE_COMP2 + select STM32_HAVE_COMP3 + select STM32_HAVE_COMP4 + select STM32_HAVE_COMP5 + select STM32_HAVE_COMP6 + select STM32_HAVE_COMP7 + select STM32_HAVE_CORDIC + select STM32_HAVE_CRS + select STM32_HAVE_DAC1 + select STM32_HAVE_DAC2 + select STM32_HAVE_DAC3 + select STM32_HAVE_DAC4 + select STM32_HAVE_FSMC + select STM32_HAVE_FMAC + select STM32_HAVE_FDCAN1 + select STM32_HAVE_FDCAN2 + select STM32_HAVE_HRTIM1 + select STM32_HAVE_I2C2 + select STM32_HAVE_I2C3 + select STM32_HAVE_I2C4 + select STM32_HAVE_I2S3 + select STM32_HAVE_LPTIM1 + select STM32_HAVE_LPUART1 + select STM32_HAVE_OPAMP1 + select STM32_HAVE_OPAMP2 + select STM32_HAVE_OPAMP3 + select STM32_HAVE_OPAMP4 + select STM32_HAVE_OPAMP5 + select STM32_HAVE_OPAMP6 + select STM32_HAVE_QSPI + select STM32_HAVE_RNG + select STM32_HAVE_SPI2 + select STM32_HAVE_SPI3 + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM15 + select STM32_HAVE_TIM16 + select STM32_HAVE_TIM17 + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM20 + select STM32_HAVE_TIM3 + select STM32_HAVE_TIM4 + select STM32_HAVE_TIM5 + select STM32_HAVE_TIM8 + select STM32_HAVE_USART3 + select STM32_HAVE_UCPD + select STM32_HAVE_USBDEV + +config STM32_STM32G474C + bool + default n + select STM32_HAVE_FDCAN3 + +config STM32_STM32G474M + bool + default n + select STM32_HAVE_FDCAN3 + select STM32_HAVE_SPI4 + select STM32_HAVE_UART4 + select STM32_HAVE_UART5 + +config STM32_STM32G474R + bool + default n + select STM32_HAVE_FDCAN3 + select STM32_HAVE_UART4 + select STM32_HAVE_UART5 + +config STM32_STM32G474Q + bool + default n + select STM32_HAVE_FDCAN3 + select STM32_HAVE_FMC + select STM32_HAVE_SPI4 + select STM32_HAVE_UART4 + select STM32_HAVE_UART5 + +config STM32_STM32G474V + bool + default n + select STM32_HAVE_FDCAN3 + select STM32_HAVE_FMC + select STM32_HAVE_SPI4 + select STM32_HAVE_UART4 + select STM32_HAVE_UART5 diff --git a/arch/arm/src/stm32g4/Make.defs b/arch/arm/src/stm32g4/Make.defs new file mode 100644 index 0000000000000..e8ec4e1184e64 --- /dev/null +++ b/arch/arm/src/stm32g4/Make.defs @@ -0,0 +1,27 @@ +############################################################################ +# arch/arm/src/stm32g4/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include armv7-m/Make.defs + +CHIP_CSRCS = stm32_rcc.c + +include common/stm32/Make.defs diff --git a/arch/arm/src/stm32g4/chip.h b/arch/arm/src/stm32g4/chip.h new file mode 100644 index 0000000000000..2be83d370f594 --- /dev/null +++ b/arch/arm/src/stm32g4/chip.h @@ -0,0 +1,59 @@ +/**************************************************************************** + * arch/arm/src/stm32g4/chip.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32G4_CHIP_H +#define __ARCH_ARM_SRC_STM32G4_CHIP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/* Include the chip capabilities file */ + +#include + +/* Include the chip interrupt definition file */ + +#include + +/* Include the chip memory map */ + +#include "hardware/stm32_memorymap.h" + +/* Include the chip pinmap */ + +#include "hardware/stm32_pinmap.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Provide the required number of peripheral interrupt vector + * definitions as * well. The definition STM32_IRQ_NEXTINTS simply comes + * from the chip-specific * IRQ header file included by arch/stm32/irq.h. + */ + +#define ARMV7M_PERIPHERAL_INTERRUPTS STM32_IRQ_NEXTINTS + +#endif /* __ARCH_ARM_SRC_STM32G4_CHIP_H */ diff --git a/arch/arm/src/stm32g4/hardware/stm32_memorymap.h b/arch/arm/src/stm32g4/hardware/stm32_memorymap.h new file mode 100644 index 0000000000000..5c737c84db3e1 --- /dev/null +++ b/arch/arm/src/stm32g4/hardware/stm32_memorymap.h @@ -0,0 +1,17 @@ +/**************************************************************************** + * arch/arm/src/stm32g4/hardware/stm32_memorymap.h + * + * SPDX-License-Identifier: Apache-2.0 + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32G4_HARDWARE_STM32_MEMORYMAP_H +#define __ARCH_ARM_SRC_STM32G4_HARDWARE_STM32_MEMORYMAP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "hardware/stm32g4xxxx_memorymap.h" + +#endif /* __ARCH_ARM_SRC_STM32G4_HARDWARE_STM32_MEMORYMAP_H */ diff --git a/arch/arm/src/stm32g4/hardware/stm32_pinmap.h b/arch/arm/src/stm32g4/hardware/stm32_pinmap.h new file mode 100644 index 0000000000000..24148a4582831 --- /dev/null +++ b/arch/arm/src/stm32g4/hardware/stm32_pinmap.h @@ -0,0 +1,17 @@ +/**************************************************************************** + * arch/arm/src/stm32g4/hardware/stm32_pinmap.h + * + * SPDX-License-Identifier: Apache-2.0 + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32G4_HARDWARE_STM32_PINMAP_H +#define __ARCH_ARM_SRC_STM32G4_HARDWARE_STM32_PINMAP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "hardware/stm32g4xxxx_pinmap.h" + +#endif /* __ARCH_ARM_SRC_STM32G4_HARDWARE_STM32_PINMAP_H */ diff --git a/arch/arm/src/stm32/hardware/stm32g47xxx_hrtim.h b/arch/arm/src/stm32g4/hardware/stm32g47xxx_hrtim.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32g47xxx_hrtim.h rename to arch/arm/src/stm32g4/hardware/stm32g47xxx_hrtim.h index 4e2a6445bfa4e..21a1dc772c5a3 100644 --- a/arch/arm/src/stm32/hardware/stm32g47xxx_hrtim.h +++ b/arch/arm/src/stm32g4/hardware/stm32g47xxx_hrtim.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32g47xxx_hrtim.h + * arch/arm/src/stm32g4/hardware/stm32g47xxx_hrtim.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/hardware/stm32g4xxc_pinmap.h b/arch/arm/src/stm32g4/hardware/stm32g4xxc_pinmap.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32g4xxc_pinmap.h rename to arch/arm/src/stm32g4/hardware/stm32g4xxc_pinmap.h index ce52049659085..6712ccc160f99 100644 --- a/arch/arm/src/stm32/hardware/stm32g4xxc_pinmap.h +++ b/arch/arm/src/stm32g4/hardware/stm32g4xxc_pinmap.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32g4xxc_pinmap.h + * arch/arm/src/stm32g4/hardware/stm32g4xxc_pinmap.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/hardware/stm32g4xxk_pinmap.h b/arch/arm/src/stm32g4/hardware/stm32g4xxk_pinmap.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32g4xxk_pinmap.h rename to arch/arm/src/stm32g4/hardware/stm32g4xxk_pinmap.h index 44701877d520e..0061b3e7fd49d 100644 --- a/arch/arm/src/stm32/hardware/stm32g4xxk_pinmap.h +++ b/arch/arm/src/stm32g4/hardware/stm32g4xxk_pinmap.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32g4xxk_pinmap.h + * arch/arm/src/stm32g4/hardware/stm32g4xxk_pinmap.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/hardware/stm32g4xxm_pinmap.h b/arch/arm/src/stm32g4/hardware/stm32g4xxm_pinmap.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32g4xxm_pinmap.h rename to arch/arm/src/stm32g4/hardware/stm32g4xxm_pinmap.h index 1f28684b1368f..c8ef978d5cccb 100644 --- a/arch/arm/src/stm32/hardware/stm32g4xxm_pinmap.h +++ b/arch/arm/src/stm32g4/hardware/stm32g4xxm_pinmap.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32g4xxm_pinmap.h + * arch/arm/src/stm32g4/hardware/stm32g4xxm_pinmap.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/hardware/stm32g4xxp_pinmap.h b/arch/arm/src/stm32g4/hardware/stm32g4xxp_pinmap.h similarity index 96% rename from arch/arm/src/stm32/hardware/stm32g4xxp_pinmap.h rename to arch/arm/src/stm32g4/hardware/stm32g4xxp_pinmap.h index 860e449abacd9..2d3ad17853477 100644 --- a/arch/arm/src/stm32/hardware/stm32g4xxp_pinmap.h +++ b/arch/arm/src/stm32g4/hardware/stm32g4xxp_pinmap.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32g4xxp_pinmap.h + * arch/arm/src/stm32g4/hardware/stm32g4xxp_pinmap.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/hardware/stm32g4xxq_pinmap.h b/arch/arm/src/stm32g4/hardware/stm32g4xxq_pinmap.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32g4xxq_pinmap.h rename to arch/arm/src/stm32g4/hardware/stm32g4xxq_pinmap.h index 82d1c4b86429b..92b1d059c20ec 100644 --- a/arch/arm/src/stm32/hardware/stm32g4xxq_pinmap.h +++ b/arch/arm/src/stm32g4/hardware/stm32g4xxq_pinmap.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32g4xxq_pinmap.h + * arch/arm/src/stm32g4/hardware/stm32g4xxq_pinmap.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/hardware/stm32g4xxr_pinmap.h b/arch/arm/src/stm32g4/hardware/stm32g4xxr_pinmap.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32g4xxr_pinmap.h rename to arch/arm/src/stm32g4/hardware/stm32g4xxr_pinmap.h index 53806263bc7e0..009b98fe1f5ae 100644 --- a/arch/arm/src/stm32/hardware/stm32g4xxr_pinmap.h +++ b/arch/arm/src/stm32g4/hardware/stm32g4xxr_pinmap.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32g4xxr_pinmap.h + * arch/arm/src/stm32g4/hardware/stm32g4xxr_pinmap.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/hardware/stm32g4xxv_pinmap.h b/arch/arm/src/stm32g4/hardware/stm32g4xxv_pinmap.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32g4xxv_pinmap.h rename to arch/arm/src/stm32g4/hardware/stm32g4xxv_pinmap.h index a6cd76129e0ed..78197031a2cdd 100644 --- a/arch/arm/src/stm32/hardware/stm32g4xxv_pinmap.h +++ b/arch/arm/src/stm32g4/hardware/stm32g4xxv_pinmap.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32g4xxv_pinmap.h + * arch/arm/src/stm32g4/hardware/stm32g4xxv_pinmap.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/hardware/stm32g4xxxx_comp.h b/arch/arm/src/stm32g4/hardware/stm32g4xxxx_comp.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32g4xxxx_comp.h rename to arch/arm/src/stm32g4/hardware/stm32g4xxxx_comp.h index 4a9ec781e0708..aff65335c071e 100644 --- a/arch/arm/src/stm32/hardware/stm32g4xxxx_comp.h +++ b/arch/arm/src/stm32g4/hardware/stm32g4xxxx_comp.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32g4xxxx_comp.h + * arch/arm/src/stm32g4/hardware/stm32g4xxxx_comp.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/hardware/stm32g4xxxx_cordic.h b/arch/arm/src/stm32g4/hardware/stm32g4xxxx_cordic.h similarity index 98% rename from arch/arm/src/stm32/hardware/stm32g4xxxx_cordic.h rename to arch/arm/src/stm32g4/hardware/stm32g4xxxx_cordic.h index c0e5c6669cb3a..d664710669c03 100644 --- a/arch/arm/src/stm32/hardware/stm32g4xxxx_cordic.h +++ b/arch/arm/src/stm32g4/hardware/stm32g4xxxx_cordic.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32g4xxxx_cordic.h + * arch/arm/src/stm32g4/hardware/stm32g4xxxx_cordic.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/hardware/stm32g4xxxx_dmamux.h b/arch/arm/src/stm32g4/hardware/stm32g4xxxx_dmamux.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32g4xxxx_dmamux.h rename to arch/arm/src/stm32g4/hardware/stm32g4xxxx_dmamux.h index a5d58546c6ca7..7e7c994dc30e1 100644 --- a/arch/arm/src/stm32/hardware/stm32g4xxxx_dmamux.h +++ b/arch/arm/src/stm32g4/hardware/stm32g4xxxx_dmamux.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32g4xxxx_dmamux.h + * arch/arm/src/stm32g4/hardware/stm32g4xxxx_dmamux.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/hardware/stm32g4xxxx_gpio.h b/arch/arm/src/stm32g4/hardware/stm32g4xxxx_gpio.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32g4xxxx_gpio.h rename to arch/arm/src/stm32g4/hardware/stm32g4xxxx_gpio.h index 661060cb87681..7136812cdf6e6 100644 --- a/arch/arm/src/stm32/hardware/stm32g4xxxx_gpio.h +++ b/arch/arm/src/stm32g4/hardware/stm32g4xxxx_gpio.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32g4xxxx_gpio.h + * arch/arm/src/stm32g4/hardware/stm32g4xxxx_gpio.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/hardware/stm32g4xxxx_memorymap.h b/arch/arm/src/stm32g4/hardware/stm32g4xxxx_memorymap.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32g4xxxx_memorymap.h rename to arch/arm/src/stm32g4/hardware/stm32g4xxxx_memorymap.h index e0d72cf4cf186..fe1b4330269dc 100644 --- a/arch/arm/src/stm32/hardware/stm32g4xxxx_memorymap.h +++ b/arch/arm/src/stm32g4/hardware/stm32g4xxxx_memorymap.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32g4xxxx_memorymap.h + * arch/arm/src/stm32g4/hardware/stm32g4xxxx_memorymap.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/hardware/stm32g4xxxx_opamp.h b/arch/arm/src/stm32g4/hardware/stm32g4xxxx_opamp.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32g4xxxx_opamp.h rename to arch/arm/src/stm32g4/hardware/stm32g4xxxx_opamp.h index 89cddf6e59b66..d607bd4d2b586 100644 --- a/arch/arm/src/stm32/hardware/stm32g4xxxx_opamp.h +++ b/arch/arm/src/stm32g4/hardware/stm32g4xxxx_opamp.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32g4xxxx_opamp.h + * arch/arm/src/stm32g4/hardware/stm32g4xxxx_opamp.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/hardware/stm32g4xxxx_pinmap.h b/arch/arm/src/stm32g4/hardware/stm32g4xxxx_pinmap.h similarity index 97% rename from arch/arm/src/stm32/hardware/stm32g4xxxx_pinmap.h rename to arch/arm/src/stm32g4/hardware/stm32g4xxxx_pinmap.h index b8a5dc9546c20..04f177f6ce8a2 100644 --- a/arch/arm/src/stm32/hardware/stm32g4xxxx_pinmap.h +++ b/arch/arm/src/stm32g4/hardware/stm32g4xxxx_pinmap.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32g4xxxx_pinmap.h + * arch/arm/src/stm32g4/hardware/stm32g4xxxx_pinmap.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/hardware/stm32g4xxxx_pwr.h b/arch/arm/src/stm32g4/hardware/stm32g4xxxx_pwr.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32g4xxxx_pwr.h rename to arch/arm/src/stm32g4/hardware/stm32g4xxxx_pwr.h index c5af4b8e15790..20bf5247308ef 100644 --- a/arch/arm/src/stm32/hardware/stm32g4xxxx_pwr.h +++ b/arch/arm/src/stm32g4/hardware/stm32g4xxxx_pwr.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32g4xxxx_pwr.h + * arch/arm/src/stm32g4/hardware/stm32g4xxxx_pwr.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/hardware/stm32g4xxxx_rcc.h b/arch/arm/src/stm32g4/hardware/stm32g4xxxx_rcc.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32g4xxxx_rcc.h rename to arch/arm/src/stm32g4/hardware/stm32g4xxxx_rcc.h index 543d369f3ebf7..6070eeea00fb7 100644 --- a/arch/arm/src/stm32/hardware/stm32g4xxxx_rcc.h +++ b/arch/arm/src/stm32g4/hardware/stm32g4xxxx_rcc.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32g4xxxx_rcc.h + * arch/arm/src/stm32g4/hardware/stm32g4xxxx_rcc.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/hardware/stm32g4xxxx_syscfg.h b/arch/arm/src/stm32g4/hardware/stm32g4xxxx_syscfg.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32g4xxxx_syscfg.h rename to arch/arm/src/stm32g4/hardware/stm32g4xxxx_syscfg.h index a7fdf99c74b94..4de4a00d94e69 100644 --- a/arch/arm/src/stm32/hardware/stm32g4xxxx_syscfg.h +++ b/arch/arm/src/stm32g4/hardware/stm32g4xxxx_syscfg.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32g4xxxx_syscfg.h + * arch/arm/src/stm32g4/hardware/stm32g4xxxx_syscfg.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/hardware/stm32g4xxxx_vrefbuf.h b/arch/arm/src/stm32g4/hardware/stm32g4xxxx_vrefbuf.h similarity index 98% rename from arch/arm/src/stm32/hardware/stm32g4xxxx_vrefbuf.h rename to arch/arm/src/stm32g4/hardware/stm32g4xxxx_vrefbuf.h index 5591bfe744a53..4b3d532c27f37 100644 --- a/arch/arm/src/stm32/hardware/stm32g4xxxx_vrefbuf.h +++ b/arch/arm/src/stm32g4/hardware/stm32g4xxxx_vrefbuf.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32g4xxxx_vrefbuf.h + * arch/arm/src/stm32g4/hardware/stm32g4xxxx_vrefbuf.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32g4/stm32.h b/arch/arm/src/stm32g4/stm32.h new file mode 100644 index 0000000000000..07776d682753f --- /dev/null +++ b/arch/arm/src/stm32g4/stm32.h @@ -0,0 +1,69 @@ +/**************************************************************************** + * arch/arm/src/stm32g4/stm32.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32_STM32_H +#define __ARCH_ARM_SRC_STM32_STM32_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include +#include + +#include "arm_internal.h" + +/* Peripherals **************************************************************/ + +#include "chip.h" +#include "stm32_adc.h" +#include "stm32_can.h" +#include "stm32_comp.h" +#include "stm32_dbgmcu.h" +#include "stm32_dma.h" +#include "stm32_dac_m3m4_v1.h" +#include "stm32_exti.h" +#include "stm32_flash.h" +#include "stm32_fmc_m3m4_v1.h" +#include "stm32_fsmc_m3m4_v1.h" +#include "stm32_gpio.h" +#include "stm32_i2c.h" +#include "stm32_ltdc_m3m4_v1.h" +#include "stm32_opamp_m3m4_v1.h" +#include "stm32_pwr.h" +#include "stm32_rcc.h" +#include "stm32_rtc.h" +#include "stm32_sdio_m3m4_v1.h" +#include "stm32_spi.h" +#include "stm32_i2s.h" +#include "stm32_tim.h" +#include "stm32_uart.h" +#if defined(CONFIG_USBDEV) && defined(CONFIG_STM32_USB) +# include "stm32_usbdev.h" +#endif +#include "stm32_wdg.h" +#include "stm32_lowputc.h" +#include "stm32_eth_m3m4_v1.h" + +#endif /* __ARCH_ARM_SRC_STM32_STM32_H */ diff --git a/arch/arm/src/stm32g4/stm32_rcc.c b/arch/arm/src/stm32g4/stm32_rcc.c new file mode 100644 index 0000000000000..49cfab73fb945 --- /dev/null +++ b/arch/arm/src/stm32g4/stm32_rcc.c @@ -0,0 +1,234 @@ +/**************************************************************************** + * arch/arm/src/stm32g4/stm32_rcc.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include + +#include "arm_internal.h" +#include "chip.h" +#include "stm32_gpio.h" +#include "stm32_rcc.h" +#include "stm32_rtc.h" +#include "stm32_flash.h" +#include "stm32.h" +#include "stm32_waste.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1, + "Configure BOARD_LOOPSPERMSEC to non-default value."); + +/* Allow up to 100 milliseconds for the high speed clock to become ready. + * that is a very long delay, but if the clock does not become ready we are + * hosed anyway. + */ + +#define HSERDY_TIMEOUT (100 * CONFIG_BOARD_LOOPSPERMSEC) + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/* Include chip-specific clocking initialization logic */ + +#include "stm32g4xxxx_rcc.c" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#if defined(CONFIG_STM32_STM32L15XX) +# define STM32_RCC_XXX STM32_RCC_CSR +# define RCC_XXX_YYYRST RCC_CSR_RTCRST +#else +# define STM32_RCC_XXX STM32_RCC_BDCR +# define RCC_XXX_YYYRST RCC_BDCR_BDRST +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: rcc_resetbkp + * + * Description: + * The RTC needs to reset the Backup Domain to change RTCSEL and resetting + * the Backup Domain renders to disabling the LSE as consequence. + * In order to avoid resetting the Backup Domain when we already + * configured LSE we will reset the Backup Domain early (here). + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +#if defined(CONFIG_STM32_RTC) && defined(CONFIG_STM32_PWR) && !defined(CONFIG_STM32_STM32F10XX) +static inline void rcc_resetbkp(void) +{ + uint32_t regval; + + /* Check if the RTC is already configured */ + + stm32_pwr_initbkp(false); + + regval = getreg32(RTC_MAGIC_REG); + if (regval != RTC_MAGIC && regval != RTC_MAGIC_TIME_SET) + { + stm32_pwr_enablebkp(true); + + /* We might be changing RTCSEL - to ensure such changes work, we must + * reset the backup domain (having backed up the RTC_MAGIC token) + */ + + modifyreg32(STM32_RCC_XXX, 0, RCC_XXX_YYYRST); + modifyreg32(STM32_RCC_XXX, RCC_XXX_YYYRST, 0); + + stm32_pwr_enablebkp(false); + } +} +#else +# define rcc_resetbkp() +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_clockconfig + * + * Description: + * Called to establish the clock settings based on the values in board.h. + * This function (by default) will reset most everything, enable the PLL, + * and enable peripheral clocking for all peripherals enabled in the NuttX + * configuration file. + * + * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then clocking + * will be enabled by an externally provided, board-specific function + * called stm32_board_clockconfig(). + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void stm32_clockconfig(void) +{ + /* Make sure that we are starting in the reset state */ + + rcc_reset(); + + /* Reset backup domain if appropriate */ + + rcc_resetbkp(); + +#if defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) + + /* Invoke Board Custom Clock Configuration */ + + stm32_board_clockconfig(); + +#else + + /* Invoke standard, fixed clock configuration based on definitions + * in board.h + */ + + stm32_stdclockconfig(); + +#endif + + /* Enable peripheral clocking */ + + rcc_enableperipherals(); + +#ifdef CONFIG_STM32_SYSCFG_IOCOMPENSATION + /* Enable I/O Compensation */ + + stm32_iocompensation(); +#endif +} + +/**************************************************************************** + * Name: stm32_clockenable + * + * Description: + * Re-enable the clock and restore the clock settings based on settings + * in board.h. This function is only available to support low-power + * modes of operation: When re-awakening from deep-sleep modes, it is + * necessary to re-enable/re-start the PLL + * + * This functional performs a subset of the operations performed by + * stm32_clockconfig(): It does not reset any devices, and it does not + * reset the currently enabled peripheral clocks. + * + * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then clocking + * will be enabled by an externally provided, board-specific function + * called stm32_board_clockconfig(). + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_PM +void stm32_clockenable(void) +{ +#if defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) + + /* Invoke Board Custom Clock Configuration */ + + stm32_board_clockconfig(); + +#else + + /* Invoke standard, fixed clock configuration based on definitions + * in board.h + */ + + stm32_stdclockconfig(); + +#endif +} +#endif diff --git a/arch/arm/src/stm32/stm32g4xxxx_rcc.c b/arch/arm/src/stm32g4/stm32g4xxxx_rcc.c similarity index 99% rename from arch/arm/src/stm32/stm32g4xxxx_rcc.c rename to arch/arm/src/stm32g4/stm32g4xxxx_rcc.c index 8f93746577855..f92d785d74287 100644 --- a/arch/arm/src/stm32/stm32g4xxxx_rcc.c +++ b/arch/arm/src/stm32g4/stm32g4xxxx_rcc.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32g4xxxx_rcc.c + * arch/arm/src/stm32g4/stm32g4xxxx_rcc.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32h5/CMakeLists.txt b/arch/arm/src/stm32h5/CMakeLists.txt index 37874fe58c99d..f413964d7b898 100644 --- a/arch/arm/src/stm32h5/CMakeLists.txt +++ b/arch/arm/src/stm32h5/CMakeLists.txt @@ -24,7 +24,7 @@ set(SRCS) # Common ARM and Cortex-M33 files -if(CONFIG_STM32H5_PROGMEM) +if(CONFIG_STM32_PROGMEM) list(APPEND SRCS stm32_flash.c) endif() @@ -41,10 +41,9 @@ list( stm32_pwr.c stm32_timerisr.c stm32_lse.c - stm32_lsi.c - stm32_uid.c) + stm32_lsi.c) -if(CONFIG_STM32H5_USART) +if(CONFIG_STM32_USART) list(APPEND SRCS stm32_serial.c) endif() @@ -56,7 +55,7 @@ if(CONFIG_TIMER) list(APPEND SRCS stm32_tim_lowerhalf.c) endif() -if(CONFIG_STM32H5_I2C) +if(CONFIG_STM32_I2C) list(APPEND SRCS stm32_i2c.c) endif() @@ -64,55 +63,55 @@ if(CONFIG_ADC) list(APPEND SRCS stm32_adc.c) endif() -if(CONFIG_STM32H5_FDCAN_CHARDRIVER) +if(CONFIG_STM32_FDCAN_CHARDRIVER) list(APPEND SRCS stm32_fdcan.c) endif() -if(CONFIG_STM32H5_RNG) +if(CONFIG_STM32_RNG) list(APPEND SRCS stm32_rng.c) endif() -if(CONFIG_STM32H5_ICACHE) +if(CONFIG_STM32_ICACHE) list(APPEND SRCS stm32_icache.c) endif() -if(CONFIG_STM32H5_SPI) +if(CONFIG_STM32_SPI) list(APPEND SRCS stm32_spi.c) endif() -if(CONFIG_STM32H5_QSPI1) +if(CONFIG_STM32_QSPI1) list(APPEND SRCS stm32_qspi.c) endif() -if(CONFIG_STM32H5_TIM) +if(CONFIG_STM32_TIM) list(APPEND SRCS stm32_tim.c) endif() -if(CONFIG_STM32H5_HAVE_HSI48) +if(CONFIG_STM32_HAVE_HSI48) list(APPEND SRCS stm32_hsi48.c) endif() -if(CONFIG_STM32H5_USBFS) +if(CONFIG_STM32_USBFS) list(APPEND SRCS stm32_usbfs.c) endif() -if(CONFIG_STM32H5_USBFS_HOST) +if(CONFIG_STM32_USBFS_HOST) list(APPEND SRCS stm32_usbdrdhost.c) endif() -if(CONFIG_STM32H5_ETHMAC) +if(CONFIG_STM32_ETHMAC) list(APPEND SRCS stm32_ethernet.c) endif() -if(CONFIG_STM32H5_DMA) +if(CONFIG_STM32_DMA) list(APPEND SRCS stm32_dma.c) endif() -if(CONFIG_STM32H5_DTS) +if(CONFIG_STM32_DTS) list(APPEND SRCS stm32_dts.c) endif() -if(CONFIG_STM32H5_PWM) +if(CONFIG_STM32_PWM) list(APPEND SRCS stm32_pwm.c) endif() @@ -122,8 +121,10 @@ endif() # Required chip type specific files -if(CONFIG_STM32H5_STM32H5XXXX) +if(CONFIG_STM32_STM32H5XXXX) list(APPEND SRCS stm32h5xx_rcc.c) endif() target_sources(arch PRIVATE ${SRCS}) + +add_subdirectory(${NUTTX_DIR}/arch/arm/src/common/stm32 stm32_common) diff --git a/arch/arm/src/stm32h5/Kconfig b/arch/arm/src/stm32h5/Kconfig index 14730b3b84ee8..002e693e1a9ec 100644 --- a/arch/arm/src/stm32h5/Kconfig +++ b/arch/arm/src/stm32h5/Kconfig @@ -7,6 +7,28 @@ if ARCH_CHIP_STM32H5 comment "STM32H5 Configuration Options" +config STM32_H5_PERIPHERALS + bool + default y + select STM32_HAVE_DMA1 + select STM32_HAVE_DMA2 + select STM32_HAVE_I2C1 + select STM32_HAVE_I2C2 + select STM32_HAVE_I2C3 + select STM32_HAVE_I2C4 + select STM32_HAVE_RNG + select STM32_HAVE_SPI1 + select STM32_HAVE_SPI2 + select STM32_HAVE_SPI3 + select STM32_HAVE_SYSCFG + select STM32_HAVE_DTS + select STM32_HAVE_QSPI1 + select STM32_HAVE_USBFS_MODE + select STM32_HAVE_USBDRD_HOST + select STM32_HAVE_ADC_H5 + select STM32_HAVE_USART_H5 + select STM32_HAVE_I2C_H5 + choice prompt "STM32 H5 Chip Selection" default ARCH_CHIP_STM32H563ZI @@ -15,11 +37,11 @@ choice config ARCH_CHIP_STM32H563ZI bool "STM32H563ZI" select ARCH_CORTEXM33 - select STM32H5_STM32H5XXXX - select STM32H5_STM32H56XXX - select STM32H5_STM32H563XX - select STM32H5_STM32H5X3XX - select STM32H5_FLASH_CONFIG_I + select STM32_STM32H5XXXX + select STM32_STM32H56XXX + select STM32_STM32H563XX + select STM32_STM32H5X3XX + select STM32_FLASH_CONFIG_I select STM32H5_IO_CONFIG_Z ---help--- STM32 H5 Cortex M33, 512 Kb FLASH, 256 Kb SRAM @@ -28,6212 +50,113 @@ endchoice # STM32 H5 Chip Selection # Chip families: -config STM32H5_STM32H5XXXX +config STM32_STM32H5XXXX bool default n select ARCH_HAVE_FPU - select STM32H5_HAVE_ICACHE - -config STM32H5_STM32H56XXX - bool - default n - select STM32H5_HAVE_FDCAN1 - select STM32H5_HAVE_FDCAN2 - select STM32H5_HAVE_LPUART1 - select STM32H5_HAVE_USART1 - select STM32H5_HAVE_USART2 - select STM32H5_HAVE_USART3 - select STM32H5_HAVE_UART4 - select STM32H5_HAVE_UART5 - select STM32H5_HAVE_USART6 - select STM32H5_HAVE_UART7 - select STM32H5_HAVE_UART8 - select STM32H5_HAVE_UART9 - select STM32H5_HAVE_USART10 - select STM32H5_HAVE_USART11 - select STM32H5_HAVE_UART12 - select STM32H5_HAVE_SPI4 - select STM32H5_HAVE_SPI5 - select STM32H5_HAVE_SPI6 - select STM32H5_HAVE_I2C4 - select STM32H5_HAVE_USBFS - select STM32H5_HAVE_HSI48 - select STM32H5_HAVE_ICACHE_REMAP - -config STM32H5_STM32H563XX + select STM32_HAVE_ICACHE + +config STM32_STM32H56XXX + bool + default n + select STM32_HAVE_CORDIC + select STM32_HAVE_FDCAN1 + select STM32_HAVE_FDCAN2 + select STM32_HAVE_IP_CORDIC_M3M4_V1 + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM3 + select STM32_HAVE_TIM4 + select STM32_HAVE_TIM5 + select STM32_HAVE_TIM6 + select STM32_HAVE_TIM7 + select STM32_HAVE_TIM8 + select STM32_HAVE_TIM12 + select STM32_HAVE_TIM13 + select STM32_HAVE_TIM14 + select STM32_HAVE_TIM15 + select STM32_HAVE_TIM16 + select STM32_HAVE_TIM17 + select STM32_HAVE_LPUART1 + select STM32_HAVE_USART1 + select STM32_HAVE_USART2 + select STM32_HAVE_USART3 + select STM32_HAVE_UART4 + select STM32_HAVE_UART5 + select STM32_HAVE_USART6 + select STM32_HAVE_UART7 + select STM32_HAVE_UART8 + select STM32_HAVE_UART9 + select STM32_HAVE_USART10 + select STM32_HAVE_USART11 + select STM32_HAVE_UART12 + select STM32_HAVE_SPI4 + select STM32_HAVE_SPI5 + select STM32_HAVE_SPI6 + select STM32_HAVE_I2C4 + select STM32_HAVE_USBFS + select STM32_HAVE_HSI48 + select STM32_HAVE_ICACHE_REMAP + +config STM32_STM32H563XX # STM32H552 and STM32H562 devices documented in RM0439 bool default n - select STM32H5_HAVE_ETHERNET - -choice - prompt "Override Flash Size Designator" - depends on ARCH_CHIP_STM32H5 - default STM32H5_FLASH_OVERRIDE_DEFAULT - ---help--- - STM32H5 series parts numbering (sans the package type) ends with a letter - that designates the FLASH size. - - Designator Size in KiB - 8 64 - B 128 - C 256 - E 512 - G 1024 - I 2048 - - This configuration option defaults to using the configuration based on that designator - or the default smaller size if there is no last character designator is present in the - STM32 Chip Selection. - - Examples: - If the STM32H576VE is chosen, the Flash configuration would be 'E', if a variant of - the part with a 1024 KiB Flash is released in the future one could simply select - the 'G' designator here. - - If an STM32H5xxx Series parts is chosen the default Flash configuration will be set - herein and can be changed. - -config STM32H5_FLASH_OVERRIDE_DEFAULT - bool "Default" - -config STM32H5_FLASH_OVERRIDE_8 - bool "8 64 KB" - -config STM32H5_FLASH_OVERRIDE_B - bool "B 128 KB" - -config STM32H5_FLASH_OVERRIDE_C - bool "C 256 KB" - -config STM32H5_FLASH_OVERRIDE_E - bool "E 512 KB" - -config STM32H5_FLASH_OVERRIDE_G - bool "G 1024 KB" - -config STM32H5_FLASH_OVERRIDE_I - bool "I 2048 KB" - -endchoice # "Override Flash Size Designator" - -# Flash configurations - -config STM32H5_FLASH_CONFIG_B - bool - default n - depends on STM32H5_STM32H50XXX - -config STM32H5_FLASH_CONFIG_C - bool - default n - depends on STM32H5_STM32H52XXX - -config STM32H5_FLASH_CONFIG_E - bool - default n - depends on STM32H5_STM32H52XXX || STM32H5_STM32H53XXX - -config STM32H5_FLASH_CONFIG_G - bool - default n - depends on STM32H5_STM32H56XXX + select STM32_HAVE_ETHERNET -config STM32H5_FLASH_CONFIG_I - bool - default n - depends on STM32H5_STM32H56XXX || STM32H5_STM32H57XXX # Pin/package configurations config STM32H5_IO_CONFIG_K + # Package designator K bool default n config STM32H5_IO_CONFIG_T + # Package designator T bool default n config STM32H5_IO_CONFIG_C + # Package designator C bool default n config STM32H5_IO_CONFIG_R + # Package designator R bool default n config STM32H5_IO_CONFIG_J + # Package designator J bool default n config STM32H5_IO_CONFIG_M + # Package designator M bool default n config STM32H5_IO_CONFIG_V + # Package designator V bool default n config STM32H5_IO_CONFIG_Q + # Package designator Q bool default n config STM32H5_IO_CONFIG_Z + # Package designator Z bool default n config STM32H5_IO_CONFIG_A + # Package designator A bool default n comment "STM32H5 SRAM2 Options" -config STM32H5_SRAM2_HEAP - bool "SRAM2 is used for heap" - default n - select STM32H5_SRAM2_INIT - -config STM32H5_SRAM2_INIT - bool "SRAM2 is initialized to zero" - default n - ---help--- - If the SRAM2 is being used for it's battery-backed capability, - this may be undesirable (because it will destroy the contents). In that - case, the board should handle the initialization itself at the appropriate - time. - -config STM32H5_PROGMEM - bool "Flash progmem support" - default n - ---help--- - Add progmem support, start block and end block options are provided to - obtain a uniform flash memory mapping. - -comment "STM32H5 Peripherals" - -menu "STM32H5 Peripheral Selection" - -# These "hidden" settings determine if a peripheral option is available -# for the selected MCU - -config STM32H5_HAVE_ETHERNET - bool - default n - -config STM32H5_HAVE_PHY_POLLED - bool - default n - -config STM32H5_HAVE_FDCAN1 - bool - default n - -config STM32H5_HAVE_FDCAN2 - bool - default n - -config STM32H5_HAVE_HSI48 - bool - default n - -config STM32H5_HAVE_ICACHE - bool - default n - -config STM32H5_HAVE_I2C4 - bool - default n - -config STM32H5_HAVE_LPUART1 - bool - default n - -config STM32H5_HAVE_SPI5 - bool - default n - -config STM32H5_HAVE_SPI6 - bool - default n - -config STM32H5_HAVE_USART1 - bool - default n - -config STM32H5_HAVE_USART2 - bool - default n - -config STM32H5_HAVE_USART3 - bool - default n - -config STM32H5_HAVE_UART4 - bool - default n - -config STM32H5_HAVE_UART5 - bool - default n - -config STM32H5_HAVE_USART6 - bool - default n - -config STM32H5_HAVE_UART7 - bool - default n - -config STM32H5_HAVE_UART8 - bool - default n - -config STM32H5_HAVE_UART9 - bool - default n - -config STM32H5_HAVE_USART10 - bool - default n - -config STM32H5_HAVE_USART11 - bool - default n - -config STM32H5_HAVE_UART12 - bool - default n - -config STM32H5_HAVE_USBFS - bool - default n - -# These "hidden" settings are the OR of individual peripheral selections -# indicating that the general capability is required. - -config STM32H5_ADC - bool - default n - -config STM32H5_DMA - bool - default n - -config STM32H5_FDCAN - bool - default n - -config STM32H5_PWM - bool - default n - -config STM32H5_SPI - bool - default n - -config STM32H5_SPI_DMA - bool - default n - -config STM32H5_TIM - bool - default n - -config STM32H5_USART - bool - default n - -# These are the peripheral selections proper - -config STM32H5_ADC1 - bool "ADC1" - default n - select STM32H5_ADC - -config STM32H5_ADC2 - bool "ADC2" - default n - select STM32H5_ADC - -config STM32H5_RNG - bool "RNG" - default n - select ARCH_HAVE_RNG - -config STM32H5_DMA1 - bool "DMA1" - default n - select STM32H5_DMA - select ARCH_DMA - -config STM32H5_DMA2 - bool "DMA2" - default n - select STM32H5_DMA - select ARCH_DMA - -config STM32H5_DTS - bool "DTS" - default n - ---help--- - Enable support for the on‑die digital temperature sensor (DTS) - built into STM32H5 devices. When enabled, the driver will register - a `/dev/sensor_tempX` device using the common NuttX sensor framework. - -config STM32H5_ETHMAC - bool "Ethernet MAC" - default n - depends on STM32H5_HAVE_ETHERNET - select NETDEVICES - select ARCH_HAVE_PHY - select STM32H5_HAVE_PHY_POLLED - -config STM32H5_FDCAN1 - bool "FDCAN1" - default n - depends on STM32H5_HAVE_FDCAN1 - select STM32H5_FDCAN - -config STM32H5_FDCAN2 - bool "FDCAN2" - default n - depends on STM32H5_HAVE_FDCAN2 - select STM32H5_FDCAN - -config STM32H5_ICACHE - bool "ICACHE" - default n - depends on STM32H5_HAVE_ICACHE - -config STM32H5_QSPI1 - bool "QSPI1" - default n - -menu "U[S]ART/LPUART Selection" - -config STM32H5_UART4 - bool "UART4" - default n - depends on STM32H5_HAVE_UART4 - select ARCH_HAVE_SERIAL_TERMIOS - select STM32H5_USART - -config STM32H5_UART5 - bool "UART5" - default n - depends on STM32H5_HAVE_UART5 - select ARCH_HAVE_SERIAL_TERMIOS - select STM32H5_USART - -config STM32H5_UART7 - bool "UART7" - default n - depends on STM32H5_HAVE_UART7 - select ARCH_HAVE_SERIAL_TERMIOS - select STM32H5_USART - -config STM32H5_UART8 - bool "UART8" - default n - depends on STM32H5_HAVE_UART8 - select ARCH_HAVE_SERIAL_TERMIOS - select STM32H5_USART - -config STM32H5_UART9 - bool "UART9" - default n - depends on STM32H5_HAVE_UART9 - select ARCH_HAVE_SERIAL_TERMIOS - select STM32H5_USART - -config STM32H5_UART12 - bool "UART12" - default n - depends on STM32H5_HAVE_UART12 - select ARCH_HAVE_SERIAL_TERMIOS - select STM32H5_USART - -config STM32H5_USART1 - bool "USART1" - default n - depends on STM32H5_HAVE_USART1 - select ARCH_HAVE_SERIAL_TERMIOS - select STM32H5_USART - -config STM32H5_USART2 - bool "USART2" - default n - depends on STM32H5_HAVE_USART2 - select ARCH_HAVE_SERIAL_TERMIOS - select STM32H5_USART - -config STM32H5_USART3 - bool "USART3" - default n - depends on STM32H5_HAVE_USART3 - select ARCH_HAVE_SERIAL_TERMIOS - select STM32H5_USART - -config STM32H5_USART6 - bool "USART6" - default n - depends on STM32H5_HAVE_USART6 - select ARCH_HAVE_SERIAL_TERMIOS - select STM32H5_USART - -config STM32H5_USART10 - bool "USART10" - default n - depends on STM32H5_HAVE_USART10 - select ARCH_HAVE_SERIAL_TERMIOS - select STM32H5_USART - -config STM32H5_USART11 - bool "USART11" - default n - depends on STM32H5_HAVE_USART11 - select ARCH_HAVE_SERIAL_TERMIOS - select STM32H5_USART - -config STM32H5_LPUART1 - bool "LPUART1" - default n - depends on STM32H5_HAVE_LPUART1 - select ARCH_HAVE_SERIAL_TERMIOS - select STM32H5_USART - -endmenu # U[S]ART/LPUART Selection - -menu "I2C Selection" - -config STM32H5_I2C - bool - default n - -config STM32H5_I2C1 - bool "I2C1" - default n - select STM32H5_I2C - -config STM32H5_I2C2 - bool "I2C2" - default n - select STM32H5_I2C - -config STM32H5_I2C3 - bool "I2C3" - default n - select STM32H5_I2C - -config STM32H5_I2C4 - bool "I2C4" - default n - depends on STM32H5_HAVE_I2C4 - select STM32H5_I2C - -endmenu # I2C Selection - -menu "SPI Selection" - -config STM32H5_SPI1 - bool "SPI1" - default n - select SPI - select STM32H5_SPI - -config STM32H5_SPI2 - bool "SPI2" - default n - select SPI - select STM32H5_SPI - -config STM32H5_SPI3 - bool "SPI3" - default n - select SPI - select STM32H5_SPI - -config STM32H5_SPI4 - bool "SPI4" - default n - depends on STM32H5_HAVE_SPI4 - select SPI - select STM32H5_SPI - -config STM32H5_SPI5 - bool "SPI5" - default n - depends on STM32H5_HAVE_SPI5 - select SPI - select STM32H5_SPI - -config STM32H5_SPI6 - bool "SPI6" - default n - depends on STM32H5_HAVE_SPI6 - select SPI - select STM32H5_SPI - -endmenu # SPI Selection - -menu "STM32H5 Timer Selection" - -config STM32H5_TIM1 - bool "TIM1" - default n - select STM32H5_TIM - -config STM32H5_TIM2 - bool "TIM2" - default n - select STM32H5_TIM - -config STM32H5_TIM3 - bool "TIM3" - default n - select STM32H5_TIM - -config STM32H5_TIM4 - bool "TIM4" - default n - select STM32H5_TIM - -config STM32H5_TIM5 - bool "TIM5" - default n - select STM32H5_TIM - -config STM32H5_TIM6 - bool "TIM6" - default n - select STM32H5_TIM - -config STM32H5_TIM7 - bool "TIM7" - default n - select STM32H5_TIM - -config STM32H5_TIM8 - bool "TIM8" - default n - select STM32H5_TIM - -config STM32H5_TIM12 - bool "TIM12" - default n - select STM32H5_TIM - -config STM32H5_TIM13 - bool "TIM13" - default n - select STM32H5_TIM - -config STM32H5_TIM14 - bool "TIM14" - default n - select STM32H5_TIM - -config STM32H5_TIM15 - bool "TIM15" - default n - select STM32H5_TIM - -config STM32H5_TIM16 - bool "TIM16" - default n - select STM32H5_TIM - -config STM32H5_TIM17 - bool "TIM17" - default n - select STM32H5_TIM - -endmenu # STM32H5 Timer Selection - -choice STM32H5_USBFS_MODE - prompt "USB FS Mode" - depends on STM32H5_HAVE_USBFS - default STM32H5_USBFS_NONE - ---help--- - Select the operating mode for the USB_DRD_FS peripheral. - The hardware supports Device or Host, but not simultaneously. - -config STM32H5_USBFS_NONE - bool "Disabled" - -config STM32H5_USBFS - bool "USB Device" - select USBDEV - -config STM32H5_USBFS_HOST - bool "USB Host" - select USBHOST_HAVE_ASYNCH - select USBHOST - ---help--- - Enable USB host mode for USB_DRD_FS peripheral. - -endchoice - -endmenu # STM32H5 Peripheral Selection - -menu "DTS Configuration" - depends on STM32H5_DTS - -config STM32H5_DTS_REFCLK_LSE - bool "Use LSE (32.768 kHz crystal) as DTS reference clock" - default n - ---help--- - Select the low‑speed external (LSE) oscillator as the reference clock - for the DTS. When enabled, DTS_CFGR1.REFCLK_SEL=1 and the driver will - measure FM(T) pulses over N LSE cycles. - - If disabled, the DTS will use the APB‑bus clock (PCLK) as the reference - (REFCLK_SEL=0) and you must supply a valid HSREF_CLK_DIV to keep the - calibration prescaler ≤ 1 MHz. - -config STM32H5_DTS_SMP_TIME - int "DTS sampling time (TS1_SMP_TIME[3:0])" - default 1 - range 1 15 - ---help--- - Number of reference‑clock cycles (PCLK or LSE) counted per - DTS measurement. Valid range 1 (1 cycle) through 15 (15 cycles). - -config STM32H5_DTS_TRIGGER - int "DTS hardware trigger source (TS1_INTRIG_SEL[3:0])" - default 0 - ---help--- - If non‑zero, DTS will start measurements on the rising edge of - the selected hardware line. Values match RM0481 Table 275: - 0=Software Trigger, 1=LPTIM1_CH1,  - 2=LPTIM2_CH1, 3=LPTIM3_CH1, 4=EXTI13, 5-15 are reserved. - -config STM32H5_DTS_LOW_THRESHOLD - int "DTS low‑threshold (°C)" - default 0 - ---help--- - The temperature (in whole °C) below which the DTS window comparator will - assert the low‑threshold flag (TS1_ITLF). To disable, set equal to 0. - -config STM32H5_DTS_HIGH_THRESHOLD - int "DTS high‑threshold (°C)" - default 100 - ---help--- - The temperature (in whole °C) above which the DTS window comparator will - assert the high‑threshold flag (TS1_ITHF). Must be >= LOW_THRESHOLD. - -config STM32H5_DTS_ITEN_ITEF - bool "Enable DTS end‑of‑measurement interrupt (TS1_ITEF)" - default y - ---help--- - Enable the synchronous “end of measurement” interrupt for the - digital temperature sensor. When set, the driver will attach - and unmask TS1_ITEF and will call your ISR on every fresh sample. - -config STM32H5_DTS_ITEN_ITLF - bool "Enable DTS low‑threshold interrupt (TS1_ITLF)" - default n - ---help--- - Enable the synchronous “low threshold crossed” interrupt for the - digital temperature sensor. When set, the driver will unmask - TS1_ITLF so you can get notified whenever the measured value - drops below your programmed low‑threshold. - -config STM32H5_DTS_ITEN_ITHF - bool "Enable DTS high‑threshold interrupt (TS1_ITHF)" - default n - ---help--- - Enable the synchronous “high threshold crossed” interrupt for the - digital temperature sensor. When set, the driver will unmask - TS1_ITHF so you can get notified whenever the measured value - exceeds your programmed high‑threshold. - -config STM32H5_DTS_AITEN_AITEF - bool "Enable DTS asynchronous end‑of‑measurement interrupt (TS1_AITEF)" - depends on STM32H5_DTS_REFCLK_LSE - default n - ---help--- - Enable the asynchronous end‑of‑measurement interrupt. This will - set TS1_AITEEN in DTS_ITENR and cause an _asynchronous_ wakeup - event when a conversion completes (in Stop/Sleep modes). - -config STM32H5_DTS_AITEN_AITLF - bool "Enable DTS asynchronous low‑threshold interrupt (TS1_AITLF)" - depends on STM32H5_DTS_REFCLK_LSE - default n - ---help--- - Enable the asynchronous low‑threshold comparator interrupt. This - will set TS1_AITLEN in DTS_ITENR and generate a wakeup event - when the measurement drops below your low threshold. - -config STM32H5_DTS_AITEN_AITHF - bool "Enable DTS asynchronous high‑threshold interrupt (TS1_AITHF)" - depends on STM32H5_DTS_REFCLK_LSE - default n - ---help--- - Enable the asynchronous high‑threshold comparator interrupt. This - will set TS1_AITHEN in DTS_ITENR and generate a wakeup event - when the measurement exceeds your high threshold. - -endmenu # DTS Configuration - -config STM32H5_FLASH_PREFETCH - bool "Enable FLASH Pre-fetch" - default y - ---help--- - Enable FLASH prefetch - -menu "ICACHE Configuration" - depends on STM32H5_ICACHE - -config STM32H5_ICACHE_MONITOR_EN - bool "Enable ICACHE Hit/Miss Counters" - default n - -config STM32H5_ICACHE_DIRECT - bool "Enable 1-Way Direct Mapped Cache (N-Way = default)" - default n - -menu "ICACHE Interrupt Configuration" - depends on STM32H5_ICACHE - -config STM32H5_ICACHE_INV_INT - bool "Enable interrupts on full invalidation completion." - default n - -config STM32H5_ICACHE_ERR_INT - bool "Enable interrupts on occurrences of cache errors." - default n - -endmenu # ICACHE Interrupt Configuration - -menu "ICACHE Region Configuration" - depends on STM32H5_ICACHE - -config STM32H5_ICACHE_REGION0 - bool "Enable Configuration of ICACHE Region 0" - default n - -config STM32H5_ICACHE_REGION1 - bool "Enable Configuration of ICACHE Region 1" - default n - -config STM32H5_ICACHE_REGION2 - bool "Enable Configuration of ICACHE Region 2" - default n - -config STM32H5_ICACHE_REGION3 - bool "Enable Configuration of ICACHE Region 3" - default n - -menu "Region 0 Configuration" - depends on STM32H5_ICACHE_REGION0 && STM32H5_HAVE_ICACHE_REMAP - -config STM32H5_ICACHE_REGION0_BADDR - hex "ICACHE Region 0 Base Address Bits [28:21]" - default 0 - range 0 255 - depends on STM32H5_ICACHE_REGION0 - ---help--- - Set bits [28:21] of the base address for ICACHE Region 0. - -config STM32H5_ICACHE_REGION0_RSIZE - int "ICACHE Region 0 Size" - default 1 - range 1 7 - depends on STM32H5_ICACHE_REGION0 - ---help--- - Set the size of Region 0. - 1 = 2 Mbytes, 2 = 4 Mbytes, 3 = 8 Mbytes, 4 = 16 Mbytes, - 5 = 2 Mbytes, 6 = 64 Mbytes, 7 = 128 Mbytes. - -config STM32H5_ICACHE_REGION0_REMAPADDR - hex "ICACHE Region 0 Remap Address Bits [31:21]" - default 0 - range 0 2047 - depends on STM32H5_ICACHE_REGION0 - ---help--- - Set bits [31:21] of ICACHE Region 0 Remap Address.. - -config STM32H5_ICACHE_REGION0_MSTSEL - int "ICACHE Region 0 Master Select (0 or 1)" - default 0 - range 0 1 - depends on STM32H5_ICACHE_REGION0 - ---help--- - Select ICACHE Region 0 Master 1 (0) or Master 2 (1). - -config STM32H5_ICACHE_REGION0_HBURST - int "ICACHE Region 0 Output Burst Type (0 = Wrap, 1 = Incr)" - default 0 - range 0 1 - depends on STM32H5_ICACHE_REGION0 - ---help--- - Select Wrap (0) or Increment (1) Output Burst Type. - -endmenu # Region 0 Configuration - -menu "Region 1 Configuration" - depends on STM32H5_ICACHE_REGION1 && STM32H5_HAVE_ICACHE_REMAP - -config STM32H5_ICACHE_REGION1_BADDR - hex "ICACHE Region 1 Base Address Bits [28:21]" - default 0 - range 0 255 - depends on STM32H5_ICACHE_REGION1 - ---help--- - Set bits [28:21] of the base address for ICACHE Region 1. - -config STM32H5_ICACHE_REGION1_RSIZE - int "ICACHE Region 1 Size" - default 1 - range 1 7 - depends on STM32H5_ICACHE_REGION1 - ---help--- - Set the size of Region 1. - 1 = 2 Mbytes, 2 = 4 Mbytes, 3 = 8 Mbytes, 4 = 16 Mbytes, - 5 = 2 Mbytes, 6 = 64 Mbytes, 7 = 128 Mbytes. - -config STM32H5_ICACHE_REGION1_REMAPADDR - hex "ICACHE Region 1 Remap Address Bits [31:21]" - default 0 - range 0 2047 - depends on STM32H5_ICACHE_REGION1 - ---help--- - Set bits [31:21] of ICACHE Region 1 Remap Address.. - -config STM32H5_ICACHE_REGION1_MSTSEL - int "ICACHE Region 1 Master Select (0 or 1)" - default 0 - range 0 1 - depends on STM32H5_ICACHE_REGION1 - ---help--- - Select ICACHE Region 1 Master 1 (0) or Master 2 (1). - -config STM32H5_ICACHE_REGION1_HBURST - int "ICACHE Region 1 Output Burst Type (0 = Wrap, 1 = Incr)" - default 0 - range 0 1 - depends on STM32H5_ICACHE_REGION1 - ---help--- - Select Wrap (0) or Increment (1) Output Burst Type. - -endmenu # Region 1 Configuration - -menu "Region 2 Configuration" - depends on STM32H5_ICACHE_REGION2 && STM32H5_HAVE_ICACHE_REMAP - -config STM32H5_ICACHE_REGION2_BADDR - hex "ICACHE Region 2 Base Address Bits [28:21]" - default 0 - range 0 255 - depends on STM32H5_ICACHE_REGION2 - ---help--- - Set bits [28:21] of the base address for ICACHE Region 2. - -config STM32H5_ICACHE_REGION2_RSIZE - int "ICACHE Region 2 Size" - default 1 - range 1 7 - depends on STM32H5_ICACHE_REGION2 - ---help--- - Set the size of Region 2. - 1 = 2 Mbytes, 2 = 4 Mbytes, 3 = 8 Mbytes, 4 = 16 Mbytes, - 5 = 2 Mbytes, 6 = 64 Mbytes, 7 = 128 Mbytes. - -config STM32H5_ICACHE_REGION2_REMAPADDR - hex "ICACHE Region 2 Remap Address Bits [31:21]" - default 0 - range 0 2047 - depends on STM32H5_ICACHE_REGION2 - ---help--- - Set bits [31:21] of ICACHE Region 2 Remap Address.. - -config STM32H5_ICACHE_REGION2_MSTSEL - int "ICACHE Region 2 Master Select (0 or 1)" - default 0 - range 0 1 - depends on STM32H5_ICACHE_REGION2 - ---help--- - Select ICACHE Region 2 Master 1 (0) or Master 2 (1). - -config STM32H5_ICACHE_REGION2_HBURST - int "ICACHE Region 2 Output Burst Type (0 = Wrap, 1 = Incr)" - default 0 - range 0 1 - depends on STM32H5_ICACHE_REGION2 - ---help--- - Select Wrap (0) or Increment (1) Output Burst Type. - -endmenu # Region 2 Configuration - -menu "Region 3 Configuration" - depends on STM32H5_ICACHE_REGION3 && STM32H5_HAVE_ICACHE_REMAP - -config STM32H5_ICACHE_REGION3_BADDR - hex "ICACHE Region 3 Base Address Bits [28:21]" - default 0 - range 0 255 - depends on STM32H5_ICACHE_REGION3 - ---help--- - Set bits [28:21] of the base address for ICACHE Region 3. - -config STM32H5_ICACHE_REGION3_RSIZE - int "ICACHE Region 3 Size" - default 1 - range 1 7 - depends on STM32H5_ICACHE_REGION3 - ---help--- - Set the size of Region 3. - 1 = 2 Mbytes, 2 = 4 Mbytes, 3 = 8 Mbytes, 4 = 16 Mbytes, - 5 = 2 Mbytes, 6 = 64 Mbytes, 7 = 128 Mbytes. - -config STM32H5_ICACHE_REGION3_REMAPADDR - hex "ICACHE Region 3 Remap Address Bits [31:21]" - default 0 - range 0 2047 - depends on STM32H5_ICACHE_REGION3 - ---help--- - Set bits [31:21] of ICACHE Region 3 Remap Address.. - -config STM32H5_ICACHE_REGION3_MSTSEL - int "ICACHE Region 3 Master Select (0 or 1)" - default 0 - range 0 1 - depends on STM32H5_ICACHE_REGION3 - ---help--- - Select ICACHE Region 3 Master 1 (0) or Master 2 (1). - -config STM32H5_ICACHE_REGION3_HBURST - int "ICACHE Region 3 Output Burst Type (0 = Wrap, 1 = Incr)" - default 0 - range 0 1 - depends on STM32H5_ICACHE_REGION3 - ---help--- - Select Wrap (0) or Increment (1) Output Burst Type. - -endmenu # Region 3 Configuration - -endmenu # ICACHE Region Configuration - -endmenu # ICACHE Configuration - -config STM32H5_DISABLE_IDLE_SLEEP_DURING_DEBUG - bool "Disable IDLE Sleep (WFI) in debug mode" - default n - ---help--- - In debug configuration, disables the WFI instruction in the IDLE loop - to prevent the JTAG from disconnecting. With some JTAG debuggers, such - as the ST-LINK2 with OpenOCD, if the ARM is put to sleep via the WFI - instruction, the debugger will disconnect, terminating the debug session. - -config ARCH_BOARD_STM32H5_CUSTOM_CLOCKCONFIG - bool "Custom clock configuration" - default n - ---help--- - Enables special, board-specific STM32 clock configuration. - -menu "ADC Configuration" - depends on STM32H5_ADC - -config STM32H5_ADC_MAX_SAMPLES - int "The maximum number of channels that can be sampled" - default 16 - ---help--- - The maximum number of samples which can be handled without - overrun depends on various factors. This is the user's - responsibility to correctly select this value. - Since the interface to update the sampling time is available - for all supported devices, the user can change the default - values in the board initialization logic and avoid ADC overrun. - -config STM32H5_ADC1_RESOLUTION - int "ADC1 resolution" - depends on STM32H5_ADC1 - default 0 - range 0 3 - ---help--- - ADC1 resolution. 0 - 12 bit, 1 - 10 bit, 2 - 8 bit, 3 - 6 bit - -config STM32H5_ADC1_DMA - bool "ADC1 DMA Enable" - depends on STM32H5_ADC1 && STM32H5_DMA - default n - ---help--- - If DMA is selected, then the ADC may be configured to support DMA - transfer, which is necessary if multiple channels are read or if - very high trigger frequencies are used. - -config STM32H5_ADC1_DMA_BATCH - int "ADC1 DMA number of conversions" - depends on STM32H5_ADC1 && STM32H5_ADC1_DMA - default 1 - ---help--- - This option allows you to select the number of regular group conversions - that will trigger a DMA callback transerring data to the upper-half driver. - By default, this value is 1, which means that data is transferred after - each group conversion. - -config STM32H5_ADC1_DMA_CFG - bool "ADC1 DMA configuration" - depends on STM32H5_ADC1 && STM32H5_ADC1_DMA - default n - ---help--- - 0 - ADC1 DMA in One Shot Mode, 1 - ADC1 DMA in Circular Mode - -config STM32H5_ADC1_OVERSAMPLE - bool "Enable ADC1 hardware oversampling support" - depends on STM32H5_ADC1 - default n - ---help--- - Enable the on-chip ADC oversampling/accumulation block (CFGR2.OVSE). - Only STM32G0 and STM32L0 series include this hardware block. - -if STM32H5_ADC1_OVERSAMPLE - -config STM32H5_ADC1_TROVS - bool "Enable triggered oversampling (CFGR2.TROVS)" - default n - ---help--- - If set, oversampling will only occur when a trigger event occurs. - If not set, oversampling occurs continuously (TOVS=0). - -config STM32H5_ADC1_OVSR - int "Oversampling ratio (CFGR2.OVSR)" - default 0 - range 0 7 - ---help--- - Sets the oversampling ratio as 2^(OVSR+1). For example: - 0 -> 2× - 1 -> 4× - 2 -> 8× - ... - 7 -> 256× - -config STM32H5_ADC1_OVSS - int "Oversampling right-shift bits (CFGR2.OVSS)" - default 0 - range 0 8 - ---help--- - Sets how many bits the accumulated result is right-shifted. - Max of 8-bits. - -endif # STM32H5_ADC1_OVERSAMPLE - -config STM32H5_ADC1_WDG1 - bool "Enable STM32H5 ADC1 Watchdog 1" - depends on STM32H5_ADC1 - default n - ---help--- - Enable STM32H5 ADC1 Watchdog 1. - -config STM32H5_ADC1_WDG1_FLT - int "Set ADC1 Watchdog 1 Filter" - depends on STM32H5_ADC1_WDG1 - default 0 - range 0 7 - ---help--- - N+1 watchdog events generates an interrupt. - Default: 0. - -config STM32H5_ADC1_WDG1_LOWTHRESH - int "Set ADC1 Watchdog 1 Low Threshold" - depends on STM32H5_ADC1_WDG1 - default 0 - range 0 4095 - ---help--- - Set the ADC1 Watchdog 1 low threshold value. - Default: 0. - -config STM32H5_ADC1_WDG1_HIGHTHRESH - int "Set ADC1 Watchdog 1 High Threshold" - depends on STM32H5_ADC1_WDG1 - default 4095 - range 0 4095 - ---help--- - Set the ADC1 Watchdog 1 high threshold value. - Default: 4095. - -config STM32H5_ADC1_WDG1_SGL - bool "Enable STM32H5 ADC1 Watchdog 1 on a single channel" - depends on STM32H5_ADC1_WDG1 - default n - ---help--- - This option determines if ADC1 Watchdog 1 is enabled on all - channels or just a single channel. - -config STM32H5_ADC1_WDG1_CHAN - int "STM32H5 ADC1 Watchdog 1 Channel Selection" - depends on STM32H5_ADC1_WDG1_SGL - default 0 - range 0 19 - ---help--- - Select the channel to enable for ADC1 Watchdog 1. - -config STM32H5_ADC2_RESOLUTION - int "ADC2 resolution" - depends on STM32H5_ADC2 - default 0 - range 0 3 - ---help--- - ADC1 resolution. 0 - 12 bit, 1 - 10 bit, 2 - 8 bit, 3 - 6 bit - -config STM32H5_ADC2_DMA - bool "ADC2 DMA Enable" - depends on STM32H5_ADC2 && STM32H5_DMA - default n - ---help--- - If DMA is selected, then the ADC may be configured to support DMA - transfer, which is necessary if multiple channels are read or if - very high trigger frequencies are used. - -config STM32H5_ADC2_DMA_BATCH - int "ADC2 DMA number of conversions" - depends on STM32H5_ADC2 && STM32H5_ADC2_DMA - default 1 - ---help--- - This option allows you to select the number of regular group conversions - that will trigger a DMA callback transerring data to the upper-half driver. - By default, this value is 1, which means that data is transferred after - each group conversion. - -config STM32H5_ADC2_DMA_CFG - int "ADC2 DMA configuration" - depends on STM32H5_ADC2_DMA && STM32H5_DMA - range 0 1 - default 0 - ---help--- - 0 - ADC2 DMA in One Shot Mode, 1 - ADC2 DMA in Circular Mode - -config STM32H5_ADC2_OVERSAMPLE - bool "Enable ADC2 hardware oversampling support" - depends on STM32H5_ADC2 - default n - ---help--- - Enable the on-chip ADC oversampling/accumulation block (CFGR2.OVSE). - Only STM32G0 and STM32L0 series include this hardware block. - -if STM32H5_ADC2_OVERSAMPLE - -config STM32H5_ADC2_TROVS - bool "Enable triggered oversampling (CFGR2.TROVS)" - default n - ---help--- - If set, oversampling will only occur when a trigger event occurs. - If not set, oversampling occurs continuously (TOVS=0). - -config STM32H5_ADC2_OVSR - int "Oversampling ratio (CFGR2.OVSR)" - default 0 - range 0 7 - ---help--- - Sets the oversampling ratio as 2^(OVSR+1). For example: - 0 -> 2× - 1 -> 4× - 2 -> 8× - ... - 7 -> 256× - -config STM32H5_ADC2_OVSS - int "Oversampling right-shift bits (CFGR2.OVSS)" - default 0 - range 0 8 - ---help--- - Sets how many bits the accumulated result is right-shifted. - Max of 8-bits. - -endif # STM32H5_ADC2_OVERSAMPLE - -config STM32H5_ADC2_WDG1 - bool "Enable STM32H5 ADC2 Watchdog 1" - depends on STM32H5_ADC2 - default n - ---help--- - Enable STM32H5 ADC2 Watchdog 1. - -config STM32H5_ADC2_WDG1_FLT - int "Set ADC2 Watchdog 1 Filter" - depends on STM32H5_ADC2_WDG1 - default 0 - range 0 7 - ---help--- - N+1 watchdog events generates an interrupt. - Default: 0. - -config STM32H5_ADC2_WDG1_LOWTHRESH - int "Set ADC2 Watchdog 1 Low Threshold" - depends on STM32H5_ADC2_WDG1 - default 0 - range 0 4095 - ---help--- - Set the ADC2 Watchdog 1 low threshold value. - Default: 0. - -config STM32H5_ADC2_WDG1_HIGHTHRESH - int "Set ADC2 Watchdog 1 High Threshold" - depends on STM32H5_ADC2_WDG1 - default 4095 - range 0 4095 - ---help--- - Set the ADC2 Watchdog 1 high threshold value. - Default: 4095. - -config STM32H5_ADC2_WDG1_SGL - bool "Enable STM32H5 ADC2 Watchdog 1 on a single channel" - depends on STM32H5_ADC2_WDG1 - default n - ---help--- - This option determines if ADC2 Watchdog 1 is enabled on all - channels or just a single channel. - -config STM32H5_ADC2_WDG1_CHAN - int "STM32H5 ADC2 Watchdog 1 Channel Selection" - depends on STM32H5_ADC2_WDG1_SGL - default 0 - range 0 19 - ---help--- - Select the channel to enable for ADC2 Watchdog 1. - -endmenu # ADC Configuration - -menu "SPI Configuration" - depends on STM32H5_SPI - -config STM32H5_SPI_INTERRUPTS - bool "Interrupt driver SPI" - default n - ---help--- - Select to enable interrupt driven SPI support. Non-interrupt-driven, - poll-waiting is recommended if the interrupt rate would be too high in - the interrupt driven case. - -config STM32H5_SPI_DMATHRESHOLD - int "SPI DMA threshold" - default 4 - depends on STM32H5_SPI_DMA - ---help--- - When SPI DMA is enabled, small DMA transfers will still be performed - by polling logic. But we need a threshold value to determine what - is small. - -config STM32H5_SPI1_DMA - bool "SPI1 DMA" - default n - depends on STM32H5_SPI1 && !STM32H5_SPI_INTERRUPT - select STM32H5_SPI_DMA - ---help--- - Use DMA to improve SPI1 transfer performance. Cannot be used with STM32H5_SPI_INTERRUPT - -config STM32H5_SPI1_DMA_BUFFER - int "SPI1 DMA buffer size" - default 0 - depends on STM32H5_SPI1_DMA - ---help--- - Add a properly aligned DMA buffer for RX and TX DMA for SPI1. - -config STM32H5_SPI1_COMMTYPE - int "SPI1 Operation mode" - default 0 - range 0 3 - depends on STM32H5_SPI1 - ---help--- - Select full-duplex (0), simplex tx (1), simplex rx (2) or half-duplex (3) - -config STM32H5_SPI2_DMA - bool "SPI2 DMA" - default n - depends on STM32H5_SPI2 && !STM32H5_SPI_INTERRUPT - select STM32H5_SPI_DMA - ---help--- - Use DMA to improve SPI2 transfer performance. Cannot be used with STM32H5_SPI_INTERRUPT - -config STM32H5_SPI2_DMA_BUFFER - int "SPI2 DMA buffer size" - default 0 - depends on STM32H5_SPI2_DMA - ---help--- - Add a properly aligned DMA buffer for RX and TX DMA for SPI2. - -config STM32H5_SPI2_COMMTYPE - int "SPI2 Operation mode" - default 0 - range 0 3 - depends on STM32H5_SPI2 - ---help--- - Select full-duplex (0), simplex tx (1), simplex rx (2) or half-duplex (3) - -config STM32H5_SPI3_DMA - bool "SPI3 DMA" - default n - depends on STM32H5_SPI3 && !STM32H5_SPI_INTERRUPT - select STM32H5_SPI_DMA - ---help--- - Use DMA to improve SPI3 transfer performance. Cannot be used with STM32H5_SPI_INTERRUPT - -config STM32H5_SPI3_DMA_BUFFER - int "SPI3 DMA buffer size" - default 0 - depends on STM32H5_SPI3_DMA - ---help--- - Add a properly aligned DMA buffer for RX and TX DMA for SPI3. - -config STM32H5_SPI3_COMMTYPE - int "SPI3 Operation mode" - default 0 - range 0 3 - depends on STM32H5_SPI3 - ---help--- - Select full-duplex (0), simplex tx (1), simplex rx (2) or half-duplex (3) - -config STM32H5_SPI4_DMA - bool "SPI4 DMA" - default n - depends on STM32H5_SPI4 && !STM32H5_SPI_INTERRUPT - select STM32H5_SPI_DMA - ---help--- - Use DMA to improve SPI4 transfer performance. Cannot be used with STM32H5_SPI_INTERRUPT - -config STM32H5_SPI4_DMA_BUFFER - int "SPI4 DMA buffer size" - default 0 - depends on STM32H5_SPI4_DMA - ---help--- - Add a properly aligned DMA buffer for RX and TX DMA for SPI4. - -config STM32H5_SPI4_COMMTYPE - int "SPI4 Operation mode" - default 0 - range 0 3 - depends on STM32H5_SPI4 - ---help--- - Select full-duplex (0), simplex tx (1), simplex rx (2) or half-duplex (3) - -config STM32H5_SPI5_DMA - bool "SPI5 DMA" - default n - depends on STM32H5_SPI5 && !STM32H5_SPI_INTERRUPT - select STM32H5_SPI_DMA - ---help--- - Use DMA to improve SPI5 transfer performance. Cannot be used with STM32H5_SPI_INTERRUPT - -config STM32H5_SPI5_DMA_BUFFER - int "SPI5 DMA buffer size" - default 0 - depends on STM32H5_SPI5_DMA - ---help--- - Add a properly aligned DMA buffer for RX and TX DMA for SPI5. - -config STM32H5_SPI5_COMMTYPE - int "SPI5 Operation mode" - default 0 - range 0 3 - depends on STM32H5_SPI5 - ---help--- - Select full-duplex (0), simplex tx (1), simplex rx (2) or half-duplex (3) - -config STM32H5_SPI6_DMA - bool "SPI6 DMA" - default n - depends on STM32H5_SPI6 && !STM32H5_SPI_INTERRUPT - select STM32H5_SPI_DMA - ---help--- - Use DMA to improve SPI6 transfer performance. Cannot be used with STM32H5_SPI_INTERRUPT - -config STM32H5_SPI6_DMA_BUFFER - int "SPI6 DMA buffer size" - default 0 - depends on STM32H5_SPI6_DMA - ---help--- - Add a properly aligned DMA buffer for RX and TX DMA for SPI6. - -config STM32H5_SPI6_COMMTYPE - int "SPI6 Operation mode" - default 0 - range 0 3 - depends on STM32H5_SPI6 - ---help--- - Select full-duplex (0), simplex tx (1), simplex rx (2) or half-duplex (3) - -endmenu # "SPI Configuration" - -menu "Timer Configuration" - -if SCHED_TICKLESS - -config STM32H5_TICKLESS_TIMER - int "Tickless hardware timer" - default 2 - range 1 17 - ---help--- - If the Tickless OS feature is enabled, then one clock must be - assigned to provided the timer needed by the OS. - -config STM32H5_TICKLESS_CHANNEL - int "Tickless timer channel" - default 1 - range 1 4 - ---help--- - If the Tickless OS feature is enabled, the one clock must be - assigned to provided the free-running timer needed by the OS - and one channel on that clock is needed to handle intervals. - -endif # SCHED_TICKLESS - -config STM32H5_ONESHOT - bool "TIM one-shot wrapper" - default n - ---help--- - Enable a wrapper around the low level timer/counter functions to - support one-shot timer. - -config STM32H5_ONESHOT_MAXTIMERS - int "Maximum number of oneshot timers" - default 1 - range 1 8 - depends on STM32H5_ONESHOT - ---help--- - Determines the maximum number of oneshot timers that can be - supported. This setting pre-allocates some minimal support for each - of the timers and places an upper limit on the number of oneshot - timers that you can use. - -config STM32H5_PWM_LL_OPS - bool "PWM low-level operations" - default n - ---help--- - Enable low-level PWM ops. - -config STM32H5_TIM1_PWM - bool "TIM1 PWM" - default n - depends on STM32H5_TIM1 - select STM32H5_PWM - ---help--- - Reserve timer 1 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32H5_TIM1 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32H5_TIM1_PWM - -config STM32H5_TIM1_MODE - int "TIM1 Mode" - default 0 - range 0 4 - ---help--- - Specifies the timer mode. - -config STM32H5_TIM1_LOCK - int "TIM1 Lock Level Configuration" - default 0 - range 0 3 - ---help--- - Timer 1 lock level configuration - -config STM32H5_TIM1_TDTS - int "TIM1 t_DTS Division" - default 0 - range 0 2 - ---help--- - Timer 1 dead-time and sampling clock (t_DTS) division - -config STM32H5_TIM1_DEADTIME - int "TIM1 Initial Dead-time" - default 0 - range 0 255 - ---help--- - Timer 1 initial dead-time - -if STM32H5_PWM_MULTICHAN - -config STM32H5_TIM1_CHANNEL1 - bool "TIM1 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32H5_TIM1_CHANNEL1 - -config STM32H5_TIM1_CH1MODE - int "TIM1 Channel 1 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H5_TIM1_CH1OUT - bool "TIM1 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -config STM32H5_TIM1_CH1NOUT - bool "TIM1 Channel 1 Complementary Output" - default n - ---help--- - Enables channel 1 Complementary Output. - -endif # STM32H5_TIM1_CHANNEL1 - -config STM32H5_TIM1_CHANNEL2 - bool "TIM1 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32H5_TIM1_CHANNEL2 - -config STM32H5_TIM1_CH2MODE - int "TIM1 Channel 2 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H5_TIM1_CH2OUT - bool "TIM1 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -config STM32H5_TIM1_CH2NOUT - bool "TIM1 Channel 2 Complementary Output" - default n - ---help--- - Enables channel 2 Complementary Output. - -endif # STM32H5_TIM1_CHANNEL2 - -config STM32H5_TIM1_CHANNEL3 - bool "TIM1 Channel 3" - default n - ---help--- - Enables channel 3. - -if STM32H5_TIM1_CHANNEL3 - -config STM32H5_TIM1_CH3MODE - int "TIM1 Channel 3 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H5_TIM1_CH3OUT - bool "TIM1 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -config STM32H5_TIM1_CH3NOUT - bool "TIM1 Channel 3 Complementary Output" - default n - ---help--- - Enables channel 3 Complementary Output. - -endif # STM32H5_TIM1_CHANNEL3 - -config STM32H5_TIM1_CHANNEL4 - bool "TIM1 Channel 4" - default n - ---help--- - Enables channel 4. - -if STM32H5_TIM1_CHANNEL4 - -config STM32H5_TIM1_CH4MODE - int "TIM1 Channel 4 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H5_TIM1_CH4OUT - bool "TIM1 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32H5_TIM1_CHANNEL4 - -config STM32H5_TIM1_CHANNEL5 - bool "TIM1 Channel 5 (internal)" - default n - ---help--- - Enables channel 5 (not available externally) - -if STM32H5_TIM1_CHANNEL5 - -config STM32H5_TIM1_CH5MODE - int "TIM1 Channel 5 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H5_TIM1_CH5OUT - bool "TIM1 Channel 5 Output" - default n - ---help--- - Enables channel 5 output. - -endif # STM32H5_TIM1_CHANNEL5 - -config STM32H5_TIM1_CHANNEL6 - bool "TIM1 Channel 6 (internal)" - default n - ---help--- - Enables channel 6 (not available externally) - -if STM32H5_TIM1_CHANNEL6 - -config STM32H5_TIM1_CH6MODE - int "TIM1 Channel 6 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H5_TIM1_CH6OUT - bool "TIM1 Channel 6 Output" - default n - ---help--- - Enables channel 6 output. - -endif # STM32H5_TIM1_CHANNEL6 - -endif # STM32H5_PWM_MULTICHAN - -if !STM32H5_PWM_MULTICHAN - -config STM32H5_TIM1_CHANNEL - int "TIM1 PWM Output Channel" - default 1 - range 1 4 - ---help--- - If TIM1 is enabled for PWM usage, you also need specifies the timer output - channel {1,..,4} - -if STM32H5_TIM1_CHANNEL = 1 - -config STM32H5_TIM1_CH1OUT - bool "TIM1 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -config STM32H5_TIM1_CH1NOUT - bool "TIM1 Channel 1 Complementary Output" - default n - ---help--- - Enables channel 1 Complementary Output. - -endif # STM32H5_TIM1_CHANNEL = 1 - -if STM32H5_TIM1_CHANNEL = 2 - -config STM32H5_TIM1_CH2OUT - bool "TIM1 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -config STM32H5_TIM1_CH2NOUT - bool "TIM1 Channel 2 Complementary Output" - default n - ---help--- - Enables channel 2 Complementary Output. - -endif # STM32H5_TIM1_CHANNEL = 2 - -if STM32H5_TIM1_CHANNEL = 3 - -config STM32H5_TIM1_CH3OUT - bool "TIM1 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -config STM32H5_TIM1_CH3NOUT - bool "TIM1 Channel 3 Complementary Output" - default n - ---help--- - Enables channel 3 Complementary Output. - -endif # STM32H5_TIM1_CHANNEL = 3 - -if STM32H5_TIM1_CHANNEL = 4 - -config STM32H5_TIM1_CH4OUT - bool "TIM1 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32H5_TIM1_CHANNEL = 4 - -config STM32H5_TIM1_CHMODE - int "TIM1 Channel Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32H5_PWM_MULTICHAN - -endif # STM32H5_TIM1_PWM - -config STM32H5_TIM2_PWM - bool "TIM2 PWM" - default n - depends on STM32H5_TIM2 - select STM32H5_PWM - ---help--- - Reserve timer 2 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32H5_TIM2 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32H5_TIM2_PWM - -config STM32H5_TIM2_MODE - int "TIM2 Mode" - default 0 - range 0 4 - ---help--- - Specifies the timer mode. - -if STM32H5_PWM_MULTICHAN - -config STM32H5_TIM2_CHANNEL1 - bool "TIM2 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32H5_TIM2_CHANNEL1 - -config STM32H5_TIM2_CH1MODE - int "TIM2 Channel 1 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H5_TIM2_CH1OUT - bool "TIM2 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32H5_TIM2_CHANNEL1 - -config STM32H5_TIM2_CHANNEL2 - bool "TIM2 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32H5_TIM2_CHANNEL2 - -config STM32H5_TIM2_CH2MODE - int "TIM2 Channel 2 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H5_TIM2_CH2OUT - bool "TIM2 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32H5_TIM2_CHANNEL2 - -config STM32H5_TIM2_CHANNEL3 - bool "TIM2 Channel 3" - default n - ---help--- - Enables channel 3. - -if STM32H5_TIM2_CHANNEL3 - -config STM32H5_TIM2_CH3MODE - int "TIM2 Channel 3 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H5_TIM2_CH3OUT - bool "TIM2 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -endif # STM32H5_TIM2_CHANNEL3 - -config STM32H5_TIM2_CHANNEL4 - bool "TIM2 Channel 4" - default n - ---help--- - Enables channel 4. - -if STM32H5_TIM2_CHANNEL4 - -config STM32H5_TIM2_CH4MODE - int "TIM2 Channel 4 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H5_TIM2_CH4OUT - bool "TIM2 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32H5_TIM2_CHANNEL4 - -endif # STM32H5_PWM_MULTICHAN - -if !STM32H5_PWM_MULTICHAN - -config STM32H5_TIM2_CHANNEL - int "TIM2 PWM Output Channel" - default 1 - range 1 4 - ---help--- - If TIM2 is enabled for PWM usage, you also need specifies the timer output - channel {1,..,4} - -if STM32H5_TIM2_CHANNEL = 1 - -config STM32H5_TIM2_CH1OUT - bool "TIM2 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32H5_TIM2_CHANNEL = 1 - -if STM32H5_TIM2_CHANNEL = 2 - -config STM32H5_TIM2_CH2OUT - bool "TIM2 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32H5_TIM2_CHANNEL = 2 - -if STM32H5_TIM2_CHANNEL = 3 - -config STM32H5_TIM2_CH3OUT - bool "TIM2 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -endif # STM32H5_TIM2_CHANNEL = 3 - -if STM32H5_TIM2_CHANNEL = 4 - -config STM32H5_TIM2_CH4OUT - bool "TIM2 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32H5_TIM2_CHANNEL = 4 - -config STM32H5_TIM2_CHMODE - int "TIM2 Channel Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32H5_PWM_MULTICHAN - -endif # STM32H5_TIM2_PWM - -config STM32H5_TIM3_PWM - bool "TIM3 PWM" - default n - depends on STM32H5_TIM3 - select STM32H5_PWM - ---help--- - Reserve timer 3 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32H5_TIM3 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32H5_TIM3_PWM - -config STM32H5_TIM3_MODE - int "TIM3 Mode" - default 0 - range 0 4 - ---help--- - Specifies the timer mode. - -if STM32H5_PWM_MULTICHAN - -config STM32H5_TIM3_CHANNEL1 - bool "TIM3 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32H5_TIM3_CHANNEL1 - -config STM32H5_TIM3_CH1MODE - int "TIM3 Channel 1 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H5_TIM3_CH1OUT - bool "TIM3 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32H5_TIM3_CHANNEL1 - -config STM32H5_TIM3_CHANNEL2 - bool "TIM3 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32H5_TIM3_CHANNEL2 - -config STM32H5_TIM3_CH2MODE - int "TIM3 Channel 2 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H5_TIM3_CH2OUT - bool "TIM3 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32H5_TIM3_CHANNEL2 - -config STM32H5_TIM3_CHANNEL3 - bool "TIM3 Channel 3" - default n - ---help--- - Enables channel 3. - -if STM32H5_TIM3_CHANNEL3 - -config STM32H5_TIM3_CH3MODE - int "TIM3 Channel 3 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H5_TIM3_CH3OUT - bool "TIM3 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -endif # STM32H5_TIM3_CHANNEL3 - -config STM32H5_TIM3_CHANNEL4 - bool "TIM3 Channel 4" - default n - ---help--- - Enables channel 4. - -if STM32H5_TIM3_CHANNEL4 - -config STM32H5_TIM3_CH4MODE - int "TIM3 Channel 4 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H5_TIM3_CH4OUT - bool "TIM3 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32H5_TIM3_CHANNEL4 - -endif # STM32H5_PWM_MULTICHAN - -if !STM32H5_PWM_MULTICHAN - -config STM32H5_TIM3_CHANNEL - int "TIM3 PWM Output Channel" - default 1 - range 1 4 - ---help--- - If TIM3 is enabled for PWM usage, you also need specifies the timer output - channel {1,..,4} - -if STM32H5_TIM3_CHANNEL = 1 - -config STM32H5_TIM3_CH1OUT - bool "TIM3 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32H5_TIM3_CHANNEL = 1 - -if STM32H5_TIM3_CHANNEL = 2 - -config STM32H5_TIM3_CH2OUT - bool "TIM3 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32H5_TIM3_CHANNEL = 2 - -if STM32H5_TIM3_CHANNEL = 3 - -config STM32H5_TIM3_CH3OUT - bool "TIM3 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -endif # STM32H5_TIM3_CHANNEL = 3 - -if STM32H5_TIM3_CHANNEL = 4 - -config STM32H5_TIM3_CH4OUT - bool "TIM3 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32H5_TIM3_CHANNEL = 4 - -config STM32H5_TIM3_CHMODE - int "TIM3 Channel Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32H5_PWM_MULTICHAN - -endif # STM32H5_TIM3_PWM - -config STM32H5_TIM4_PWM - bool "TIM4 PWM" - default n - depends on STM32H5_TIM4 - select STM32H5_PWM - ---help--- - Reserve timer 4 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32H5_TIM4 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32H5_TIM4_PWM - -config STM32H5_TIM4_MODE - int "TIM4 Mode" - default 0 - range 0 4 - ---help--- - Specifies the timer mode. - -if STM32H5_PWM_MULTICHAN - -config STM32H5_TIM4_CHANNEL1 - bool "TIM4 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32H5_TIM4_CHANNEL1 - -config STM32H5_TIM4_CH1MODE - int "TIM4 Channel 1 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H5_TIM4_CH1OUT - bool "TIM4 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32H5_TIM4_CHANNEL1 - -config STM32H5_TIM4_CHANNEL2 - bool "TIM4 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32H5_TIM4_CHANNEL2 - -config STM32H5_TIM4_CH2MODE - int "TIM4 Channel 2 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H5_TIM4_CH2OUT - bool "TIM4 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32H5_TIM4_CHANNEL2 - -config STM32H5_TIM4_CHANNEL3 - bool "TIM4 Channel 3" - default n - ---help--- - Enables channel 3. - -if STM32H5_TIM4_CHANNEL3 - -config STM32H5_TIM4_CH3MODE - int "TIM4 Channel 3 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H5_TIM4_CH3OUT - bool "TIM4 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -endif # STM32H5_TIM4_CHANNEL3 - -config STM32H5_TIM4_CHANNEL4 - bool "TIM4 Channel 4" - default n - ---help--- - Enables channel 4. - -if STM32H5_TIM4_CHANNEL4 - -config STM32H5_TIM4_CH4MODE - int "TIM4 Channel 4 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H5_TIM4_CH4OUT - bool "TIM4 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32H5_TIM4_CHANNEL4 - -endif # STM32H5_PWM_MULTICHAN - -if !STM32H5_PWM_MULTICHAN - -config STM32H5_TIM4_CHANNEL - int "TIM4 PWM Output Channel" - default 1 - range 1 4 - ---help--- - If TIM4 is enabled for PWM usage, you also need specifies the timer output - channel {1,..,4} - -if STM32H5_TIM4_CHANNEL = 1 - -config STM32H5_TIM4_CH1OUT - bool "TIM4 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32H5_TIM4_CHANNEL = 1 - -if STM32H5_TIM4_CHANNEL = 2 - -config STM32H5_TIM4_CH2OUT - bool "TIM4 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32H5_TIM4_CHANNEL = 2 - -if STM32H5_TIM4_CHANNEL = 3 - -config STM32H5_TIM4_CH3OUT - bool "TIM4 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -endif # STM32H5_TIM4_CHANNEL = 3 - -if STM32H5_TIM4_CHANNEL = 4 - -config STM32H5_TIM4_CH4OUT - bool "TIM4 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32H5_TIM4_CHANNEL = 4 - -config STM32H5_TIM4_CHMODE - int "TIM4 Channel Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32H5_PWM_MULTICHAN - -endif # STM32H5_TIM4_PWM - -config STM32H5_TIM5_PWM - bool "TIM5 PWM" - default n - depends on STM32H5_TIM5 - select STM32H5_PWM - ---help--- - Reserve timer 5 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32H5_TIM5 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32H5_TIM5_PWM - -config STM32H5_TIM5_MODE - int "TIM5 Mode" - default 0 - range 0 4 - ---help--- - Specifies the timer mode. - -if STM32H5_PWM_MULTICHAN - -config STM32H5_TIM5_CHANNEL1 - bool "TIM5 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32H5_TIM5_CHANNEL1 - -config STM32H5_TIM5_CH1MODE - int "TIM5 Channel 1 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H5_TIM5_CH1OUT - bool "TIM5 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32H5_TIM5_CHANNEL1 - -config STM32H5_TIM5_CHANNEL2 - bool "TIM5 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32H5_TIM5_CHANNEL2 - -config STM32H5_TIM5_CH2MODE - int "TIM5 Channel 2 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H5_TIM5_CH2OUT - bool "TIM5 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32H5_TIM5_CHANNEL2 - -config STM32H5_TIM5_CHANNEL3 - bool "TIM5 Channel 3" - default n - ---help--- - Enables channel 3. - -if STM32H5_TIM5_CHANNEL3 - -config STM32H5_TIM5_CH3MODE - int "TIM5 Channel 3 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H5_TIM5_CH3OUT - bool "TIM5 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -endif # STM32H5_TIM5_CHANNEL3 - -config STM32H5_TIM5_CHANNEL4 - bool "TIM5 Channel 4" - default n - ---help--- - Enables channel 4. - -if STM32H5_TIM5_CHANNEL4 - -config STM32H5_TIM5_CH4MODE - int "TIM5 Channel 4 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H5_TIM5_CH4OUT - bool "TIM5 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32H5_TIM5_CHANNEL4 - -endif # STM32H5_PWM_MULTICHAN - -if !STM32H5_PWM_MULTICHAN - -config STM32H5_TIM5_CHANNEL - int "TIM5 PWM Output Channel" - default 1 - range 1 4 - ---help--- - If TIM5 is enabled for PWM usage, you also need specifies the timer output - channel {1,..,4} - -if STM32H5_TIM5_CHANNEL = 1 - -config STM32H5_TIM5_CH1OUT - bool "TIM5 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32H5_TIM5_CHANNEL = 1 - -if STM32H5_TIM5_CHANNEL = 2 - -config STM32H5_TIM5_CH2OUT - bool "TIM5 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32H5_TIM5_CHANNEL = 2 - -if STM32H5_TIM5_CHANNEL = 3 - -config STM32H5_TIM5_CH3OUT - bool "TIM5 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -endif # STM32H5_TIM5_CHANNEL = 3 - -if STM32H5_TIM5_CHANNEL = 4 - -config STM32H5_TIM5_CH4OUT - bool "TIM5 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32H5_TIM5_CHANNEL = 4 - -config STM32H5_TIM5_CHMODE - int "TIM5 Channel Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32H5_PWM_MULTICHAN - -endif # STM32H5_TIM5_PWM - -config STM32H5_TIM8_PWM - bool "TIM8 PWM" - default n - depends on STM32H5_TIM8 - select STM32H5_PWM - ---help--- - Reserve timer 8 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32H5_TIM8 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32H5_TIM8_PWM - -config STM32H5_TIM8_MODE - int "TIM8 Mode" - default 0 - range 0 4 - ---help--- - Specifies the timer mode. - -config STM32H5_TIM8_LOCK - int "TIM8 Lock Level Configuration" - default 0 - range 0 3 - ---help--- - Timer 8 lock level configuration - -config STM32H5_TIM8_DEADTIME - int "TIM8 Initial Dead-time" - default 0 - range 0 255 - ---help--- - Timer 8 initial dead-time - -config STM32H5_TIM8_TDTS - int "TIM8 t_DTS Division" - default 0 - range 0 2 - ---help--- - Timer 8 dead-time and sampling clock (t_DTS) division - -if STM32H5_PWM_MULTICHAN - -config STM32H5_TIM8_CHANNEL1 - bool "TIM8 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32H5_TIM8_CHANNEL1 - -config STM32H5_TIM8_CH1MODE - int "TIM8 Channel 1 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H5_TIM8_CH1OUT - bool "TIM8 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -config STM32H5_TIM8_CH1NOUT - bool "TIM8 Channel 1 Complementary Output" - default n - ---help--- - Enables channel 1 Complementary Output. - -endif # STM32H5_TIM8_CHANNEL1 - -config STM32H5_TIM8_CHANNEL2 - bool "TIM8 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32H5_TIM8_CHANNEL2 - -config STM32H5_TIM8_CH2MODE - int "TIM8 Channel 2 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H5_TIM8_CH2OUT - bool "TIM8 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -config STM32H5_TIM8_CH2NOUT - bool "TIM8 Channel 2 Complementary Output" - default n - ---help--- - Enables channel 2 Complementary Output. - -endif # STM32H5_TIM8_CHANNEL2 - -config STM32H5_TIM8_CHANNEL3 - bool "TIM8 Channel 3" - default n - ---help--- - Enables channel 3. - -if STM32H5_TIM8_CHANNEL3 - -config STM32H5_TIM8_CH3MODE - int "TIM8 Channel 3 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H5_TIM8_CH3OUT - bool "TIM8 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -config STM32H5_TIM8_CH3NOUT - bool "TIM8 Channel 3 Complementary Output" - default n - ---help--- - Enables channel 3 Complementary Output. - -endif # STM32H5_TIM8_CHANNEL3 - -config STM32H5_TIM8_CHANNEL4 - bool "TIM8 Channel 4" - default n - ---help--- - Enables channel 4. - -if STM32H5_TIM8_CHANNEL4 - -config STM32H5_TIM8_CH4MODE - int "TIM8 Channel 4 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H5_TIM8_CH4OUT - bool "TIM8 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32H5_TIM8_CHANNEL4 - -config STM32H5_TIM8_CHANNEL5 - bool "TIM8 Channel 5 (internal)" - default n - ---help--- - Enables channel 5 (not available externally) - -if STM32H5_TIM8_CHANNEL5 - -config STM32H5_TIM8_CH5MODE - int "TIM8 Channel 5 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H5_TIM8_CH5OUT - bool "TIM8 Channel 5 Output" - default n - ---help--- - Enables channel 5 output. - -endif # STM32H5_TIM8_CHANNEL5 - -config STM32H5_TIM8_CHANNEL6 - bool "TIM8 Channel 6 (internal)" - default n - ---help--- - Enables channel 6 (not available externally) - -if STM32H5_TIM8_CHANNEL6 - -config STM32H5_TIM8_CH6MODE - int "TIM8 Channel 6 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H5_TIM8_CH6OUT - bool "TIM8 Channel 6 Output" - default n - ---help--- - Enables channel 6 output. - -endif # STM32H5_TIM8_CHANNEL6 - -endif # STM32H5_PWM_MULTICHAN - -if !STM32H5_PWM_MULTICHAN - -config STM32H5_TIM8_CHANNEL - int "TIM8 PWM Output Channel" - default 1 - range 1 4 - ---help--- - If TIM8 is enabled for PWM usage, you also need specifies the timer output - channel {1,..,4} - -if STM32H5_TIM8_CHANNEL = 1 - -config STM32H5_TIM8_CH1OUT - bool "TIM8 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -config STM32H5_TIM8_CH1NOUT - bool "TIM8 Channel 1 Complementary Output" - default n - ---help--- - Enables channel 1 Complementary Output. - -endif # STM32H5_TIM8_CHANNEL = 1 - -if STM32H5_TIM8_CHANNEL = 2 - -config STM32H5_TIM8_CH2OUT - bool "TIM8 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -config STM32H5_TIM8_CH2NOUT - bool "TIM8 Channel 2 Complementary Output" - default n - ---help--- - Enables channel 2 Complementary Output. - -endif # STM32H5_TIM8_CHANNEL = 2 - -if STM32H5_TIM8_CHANNEL = 3 - -config STM32H5_TIM8_CH3OUT - bool "TIM8 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -config STM32H5_TIM8_CH3NOUT - bool "TIM8 Channel 3 Complementary Output" - default n - ---help--- - Enables channel 3 Complementary Output. - -endif # STM32H5_TIM8_CHANNEL = 3 - -if STM32H5_TIM8_CHANNEL = 4 - -config STM32H5_TIM8_CH4OUT - bool "TIM8 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32H5_TIM8_CHANNEL = 4 - -config STM32H5_TIM8_CHMODE - int "TIM8 Channel Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32H5_PWM_MULTICHAN - -endif # STM32H5_TIM8_PWM - -config STM32H5_TIM12_PWM - bool "TIM12 PWM" - default n - depends on STM32H5_TIM12 - select STM32H5_PWM - ---help--- - Reserve timer 12 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32H5_TIM12 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32H5_TIM12_PWM - -if STM32H5_PWM_MULTICHAN - -config STM32H5_TIM12_CHANNEL1 - bool "TIM12 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32H5_TIM12_CHANNEL1 - -config STM32H5_TIM12_CH1MODE - int "TIM12 Channel 1 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H5_TIM12_CH1OUT - bool "TIM12 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32H5_TIM12_CHANNEL1 - -config STM32H5_TIM12_CHANNEL2 - bool "TIM12 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32H5_TIM12_CHANNEL2 - -config STM32H5_TIM12_CH2MODE - int "TIM12 Channel 2 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H5_TIM12_CH2OUT - bool "TIM12 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32H5_TIM12_CHANNEL2 - -endif # STM32H5_PWM_MULTICHAN - -if !STM32H5_PWM_MULTICHAN - -config STM32H5_TIM12_CHANNEL - int "TIM12 PWM Output Channel" - default 1 - range 1 2 - ---help--- - If TIM12 is enabled for PWM usage, you also need specifies the timer output - channel {1,2} - -if STM32H5_TIM12_CHANNEL = 1 - -config STM32H5_TIM12_CH1OUT - bool "TIM12 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32H5_TIM12_CHANNEL = 1 - -if STM32H5_TIM12_CHANNEL = 2 - -config STM32H5_TIM12_CH2OUT - bool "TIM12 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32H5_TIM12_CHANNEL = 2 - -config STM32H5_TIM12_CHMODE - int "TIM12 Channel Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32H5_PWM_MULTICHAN - -endif # STM32H5_TIM12_PWM - -config STM32H5_TIM13_PWM - bool "TIM13 PWM" - default n - depends on STM32H5_TIM13 - select STM32H5_PWM - ---help--- - Reserve timer 13 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32H5_TIM13 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32H5_TIM13_PWM - -if STM32H5_PWM_MULTICHAN - -config STM32H5_TIM13_CHANNEL1 - bool "TIM13 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32H5_TIM13_CHANNEL1 - -config STM32H5_TIM13_CH1MODE - int "TIM13 Channel 1 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H5_TIM13_CH1OUT - bool "TIM13 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32H5_TIM13_CHANNEL1 - -endif # STM32H5_PWM_MULTICHAN - -if !STM32H5_PWM_MULTICHAN - -config STM32H5_TIM13_CHANNEL - int "TIM13 PWM Output Channel" - default 1 - range 1 1 - ---help--- - If TIM13 is enabled for PWM usage, you also need specifies the timer output - channel {1} - -if STM32H5_TIM13_CHANNEL = 1 - -config STM32H5_TIM13_CH1OUT - bool "TIM13 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32H5_TIM13_CHANNEL = 1 - -config STM32H5_TIM13_CHMODE - int "TIM13 Channel Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32H5_PWM_MULTICHAN - -endif # STM32H5_TIM13_PWM - -config STM32H5_TIM14_PWM - bool "TIM14 PWM" - default n - depends on STM32H5_TIM14 - select STM32H5_PWM - ---help--- - Reserve timer 14 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32H5_TIM14 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32H5_TIM14_PWM - -if STM32H5_PWM_MULTICHAN - -config STM32H5_TIM14_CHANNEL1 - bool "TIM14 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32H5_TIM14_CHANNEL1 - -config STM32H5_TIM14_CH1MODE - int "TIM14 Channel 1 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H5_TIM14_CH1OUT - bool "TIM14 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32H5_TIM14_CHANNEL1 - -endif # STM32H5_PWM_MULTICHAN - -if !STM32H5_PWM_MULTICHAN - -config STM32H5_TIM14_CHANNEL - int "TIM14 PWM Output Channel" - default 1 - range 1 1 - ---help--- - If TIM14 is enabled for PWM usage, you also need specifies the timer output - channel {1} - -if STM32H5_TIM14_CHANNEL = 1 - -config STM32H5_TIM14_CH1OUT - bool "TIM14 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32H5_TIM14_CHANNEL = 1 - -config STM32H5_TIM14_CHMODE - int "TIM14 Channel Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32H5_PWM_MULTICHAN - -endif # STM32H5_TIM14_PWM - -config STM32H5_TIM15_PWM - bool "TIM15 PWM" - default n - depends on STM32H5_TIM15 - select STM32H5_PWM - ---help--- - Reserve timer 15 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32H5_TIM15 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32H5_TIM15_PWM - -config STM32H5_TIM15_LOCK - int "TIM15 Lock Level Configuration" - default 0 - range 0 3 - ---help--- - Timer 15 lock level configuration - -config STM32H5_TIM15_TDTS - int "TIM15 t_DTS Division" - default 0 - range 0 2 - ---help--- - Timer 15 dead-time and sampling clock (t_DTS) division - -config STM32H5_TIM15_DEADTIME - int "TIM15 Initial Dead-time" - default 0 - range 0 255 - ---help--- - Timer 15 initial dead-time - -if STM32H5_PWM_MULTICHAN - -config STM32H5_TIM15_CHANNEL1 - bool "TIM15 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32H5_TIM15_CHANNEL1 - -config STM32H5_TIM15_CH1MODE - int "TIM15 Channel 1 Mode" - default 6 - range 0 9 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H5_TIM15_CH1OUT - bool "TIM15 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -config STM32H5_TIM15_CH1NOUT - bool "TIM15 Channel 1 Complementary Output" - default n - ---help--- - Enables channel 1 Complementary Output. - -endif # STM32H5_TIM15_CHANNEL1 - -config STM32H5_TIM15_CHANNEL2 - bool "TIM15 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32H5_TIM15_CHANNEL2 - -config STM32H5_TIM15_CH2MODE - int "TIM15 Channel 2 Mode" - default 6 - range 0 9 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H5_TIM15_CH2OUT - bool "TIM15 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32H5_TIM15_CHANNEL2 - -endif # STM32H5_PWM_MULTICHAN - -if !STM32H5_PWM_MULTICHAN - -config STM32H5_TIM15_CHANNEL - int "TIM15 PWM Output Channel" - default 1 - range 1 2 - ---help--- - If TIM15 is enabled for PWM usage, you also need specifies the timer output - channel {1,2} - -if STM32H5_TIM15_CHANNEL = 1 - -config STM32H5_TIM15_CH1OUT - bool "TIM15 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -config STM32H5_TIM15_CH1NOUT - bool "TIM15 Channel 1 Complementary Output" - default n - ---help--- - Enables channel 1 Complementary Output. - -endif # STM32H5_TIM15_CHANNEL = 1 - -if STM32H5_TIM15_CHANNEL = 2 - -config STM32H5_TIM15_CH2OUT - bool "TIM15 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -config STM32H5_TIM15_CH2NOUT - bool "TIM15 Channel 2 Complementary Output" - default n - ---help--- - Enables channel 2 Complementary Output. - -endif # STM32H5_TIM15_CHANNEL = 2 - -config STM32H5_TIM15_CHMODE - int "TIM15 Channel Mode" - default 6 - range 0 9 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32H5_PWM_MULTICHAN - -endif # STM32H5_TIM15_PWM - -config STM32H5_TIM16_PWM - bool "TIM16 PWM" - default n - depends on STM32H5_TIM16 - select STM32H5_PWM - ---help--- - Reserve timer 16 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32H5_TIM16 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32H5_TIM16_PWM - -config STM32H5_TIM16_LOCK - int "TIM16 Lock Level Configuration" - default 0 - range 0 3 - ---help--- - Timer 16 lock level configuration - -config STM32H5_TIM16_TDTS - int "TIM16 t_DTS division" - default 0 - range 0 2 - ---help--- - Timer 16 dead-time and sampling clock (t_DTS) division - -config STM32H5_TIM16_DEADTIME - int "TIM16 Initial Dead-time" - default 0 - range 0 255 - ---help--- - Timer 16 initial dead-time - -if STM32H5_PWM_MULTICHAN - -config STM32H5_TIM16_CHANNEL1 - bool "TIM16 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32H5_TIM16_CHANNEL1 - -config STM32H5_TIM16_CH1MODE - int "TIM16 Channel 1 Mode" - default 6 - range 0 7 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H5_TIM16_CH1OUT - bool "TIM16 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32H5_TIM16_CHANNEL1 - -endif # STM32H5_PWM_MULTICHAN - -if !STM32H5_PWM_MULTICHAN - -config STM32H5_TIM16_CHANNEL - int "TIM16 PWM Output Channel" - default 1 - range 1 1 - ---help--- - If TIM16 is enabled for PWM usage, you also need specifies the timer output - channel {1} - -if STM32H5_TIM16_CHANNEL = 1 - -config STM32H5_TIM16_CH1OUT - bool "TIM16 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32H5_TIM16_CHANNEL = 1 - -config STM32H5_TIM16_CHMODE - int "TIM16 Channel Mode" - default 6 - range 0 7 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32H5_PWM_MULTICHAN - -endif # STM32H5_TIM16_PWM - -config STM32H5_TIM17_PWM - bool "TIM17 PWM" - default n - depends on STM32H5_TIM17 - select STM32H5_PWM - ---help--- - Reserve timer 17 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32H5_TIM17 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32H5_TIM17_PWM - -config STM32H5_TIM17_LOCK - int "TIM17 Lock Level Configuration" - default 0 - range 0 3 - ---help--- - Timer 17 lock level configuration - -config STM32H5_TIM17_TDTS - int "TIM17 t_DTS Division" - default 0 - range 0 2 - ---help--- - Timer 17 dead-time and sampling clock (t_DTS) division - -config STM32H5_TIM17_DEADTIME - int "TIM17 Initial Dead-time" - default 0 - range 0 255 - ---help--- - Timer 17 initial dead-time - -if STM32H5_PWM_MULTICHAN - -config STM32H5_TIM17_CHANNEL1 - bool "TIM17 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32H5_TIM17_CHANNEL1 - -config STM32H5_TIM17_CH1MODE - int "TIM17 Channel 1 Mode" - default 6 - range 0 7 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H5_TIM17_CH1OUT - bool "TIM17 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32H5_TIM17_CHANNEL1 - -endif # STM32H5_PWM_MULTICHAN - -if !STM32H5_PWM_MULTICHAN - -config STM32H5_TIM17_CHANNEL - int "TIM17 PWM Output Channel" - default 1 - range 1 1 - ---help--- - If TIM17 is enabled for PWM usage, you also need specifies the timer output - channel {1} - -if STM32H5_TIM17_CHANNEL = 1 - -config STM32H5_TIM17_CH1OUT - bool "TIM17 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32H5_TIM17_CHANNEL = 1 - -config STM32H5_TIM17_CHMODE - int "TIM17 Channel Mode" - default 6 - range 0 7 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32H5_PWM_MULTICHAN - -endif # STM32H5_TIM17_PWM - -config STM32H5_PWM_MULTICHAN - bool "PWM Multiple Output Channels" - default n - depends on STM32H5_PWM - ---help--- - Specifies that the PWM driver supports multiple output - channels per timer. - -config STM32H5_PULSECOUNT - bool - default n - select ARCH_HAVE_PULSECOUNT - select PULSECOUNT - -config STM32H5_TIM1_PULSECOUNT - bool "TIM1 pulse count" - default n - depends on STM32H5_TIM1 - select STM32H5_PULSECOUNT - ---help--- - Reserve timer 1 for pulse count output. - -if STM32H5_TIM1_PULSECOUNT - -config STM32H5_TIM1_PULSECOUNT_TDTS - int "TIM1 pulse count clock division" - default 0 - range 0 2 - -config STM32H5_TIM1_PULSECOUNT_CHANNEL - int "TIM1 pulse count channel" - default 1 - range 1 4 - ---help--- - Specifies the timer channel {1,..,4}. - -config STM32H5_TIM1_PULSECOUNT_POL - int "TIM1 pulse count output polarity" - default 0 - range 0 1 - -config STM32H5_TIM1_PULSECOUNT_IDLE - int "TIM1 pulse count idle state" - default 0 - range 0 1 - -endif # STM32H5_TIM1_PULSECOUNT - -config STM32H5_TIM8_PULSECOUNT - bool "TIM8 pulse count" - default n - depends on STM32H5_TIM8 - select STM32H5_PULSECOUNT - ---help--- - Reserve timer 8 for pulse count output. - -if STM32H5_TIM8_PULSECOUNT - -config STM32H5_TIM8_PULSECOUNT_TDTS - int "TIM8 pulse count clock division" - default 0 - range 0 2 - -config STM32H5_TIM8_PULSECOUNT_CHANNEL - int "TIM8 pulse count channel" - default 1 - range 1 4 - ---help--- - Specifies the timer channel {1,..,4}. - -config STM32H5_TIM8_PULSECOUNT_POL - int "TIM8 pulse count output polarity" - default 0 - range 0 1 - -config STM32H5_TIM8_PULSECOUNT_IDLE - int "TIM8 pulse count idle state" - default 0 - range 0 1 - -endif # STM32H5_TIM8_PULSECOUNT -config STM32H5_TIM1_ADC - bool "TIM1 ADC" - default n - depends on STM32H5_TIM1 && STM32H5_ADC - ---help--- - Reserve timer 1 for use by an ADC - - Timer devices may be used for different purposes. If STM32H5_TIM1 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - -choice - prompt "Select ADC for use with TIM1" - default STM32H5_TIM1_ADC1 - depends on STM32H5_TIM1_ADC - -config STM32H5_TIM1_ADC1 - bool "Use TIM1 for ADC1" - depends on STM32H5_ADC1 - select STM32H5_HAVE_ADC1_TIMER - ---help--- - Reserve TIM1 to trigger ADC1 - -config STM32H5_TIM1_ADC2 - bool "Use TIM1 for ADC2" - depends on STM32H5_ADC2 - select STM32H5_HAVE_ADC2_TIMER - ---help--- - Reserve TIM1 to trigger ADC2 - -endchoice - -config STM32H5_TIM2_ADC - bool "TIM2 ADC" - default n - depends on STM32H5_TIM2 && STM32H5_ADC - ---help--- - Reserve timer 2 for use by an ADC - - Timer devices may be used for different purposes. If STM32H5_TIM2 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - -choice - prompt "Select ADC for use with TIM2" - default STM32H5_TIM2_ADC1 - depends on STM32H5_TIM2_ADC - -config STM32H5_TIM2_ADC1 - bool "Use TIM2 for ADC1" - depends on STM32H5_ADC1 - select STM32H5_HAVE_ADC1_TIMER - ---help--- - Reserve TIM2 to trigger ADC1 - -config STM32H5_TIM2_ADC2 - bool "Use TIM2 for ADC2" - depends on STM32H5_ADC2 - select STM32H5_HAVE_ADC2_TIMER - ---help--- - Reserve TIM2 to trigger ADC2 - -endchoice - -config STM32H5_TIM3_ADC - bool "TIM3 ADC" - default n - depends on STM32H5_TIM3 && STM32H5_ADC - ---help--- - Reserve timer 3 for use by an ADC - - Timer devices may be used for different purposes. If STM32H5_TIM3 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - -choice - prompt "Select ADC for use with TIM3" - default STM32H5_TIM3_ADC1 - depends on STM32H5_TIM3_ADC - -config STM32H5_TIM3_ADC1 - bool "Use TIM3 for ADC1" - depends on STM32H5_ADC1 - select STM32H5_HAVE_ADC1_TIMER - ---help--- - Reserve TIM3 to trigger ADC1 - -config STM32H5_TIM3_ADC2 - bool "Use TIM3 for ADC2" - depends on STM32H5_ADC2 - select STM32H5_HAVE_ADC2_TIMER - ---help--- - Reserve TIM3 to trigger ADC2 - -endchoice - -config STM32H5_TIM4_ADC - bool "TIM4 ADC" - default n - depends on STM32H5_TIM4 && STM32H5_ADC - ---help--- - Reserve timer 4 for use by ADC - - Timer devices may be used for different purposes. If STM32H5_TIM4 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - -choice - prompt "Select ADC for use with TIM4" - default STM32H5_TIM4_ADC1 - depends on STM32H5_TIM4_ADC - -config STM32H5_TIM4_ADC1 - bool "Use TIM4 for ADC1" - depends on STM32H5_ADC1 - select STM32H5_HAVE_ADC1_TIMER - ---help--- - Reserve TIM4 to trigger ADC1 - -config STM32H5_TIM4_ADC2 - bool "Use TIM4 for ADC2" - depends on STM32H5_ADC2 - select STM32H5_HAVE_ADC2_TIMER - ---help--- - Reserve TIM4 to trigger ADC2 - -endchoice - -config STM32H5_TIM6_ADC - bool "TIM6 ADC" - default n - depends on STM32H5_TIM6 && STM32H5_ADC - ---help--- - Reserve timer 6 for use by ADC - - Timer devices may be used for different purposes. If STM32H5_TIM6 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - -choice - prompt "Select ADC for use with TIM6" - default STM32H5_TIM6_ADC1 - depends on STM32H5_TIM6_ADC - -config STM32H5_TIM6_ADC1 - bool "Use TIM6 for ADC1" - depends on STM32H5_ADC1 - select STM32H5_HAVE_ADC1_TIMER - ---help--- - Reserve TIM6 to trigger ADC1 - -config STM32H5_TIM6_ADC2 - bool "Use TIM6 for ADC2" - depends on STM32H5_ADC2 - select STM32H5_HAVE_ADC2_TIMER - ---help--- - Reserve TIM6 to trigger ADC2 - -endchoice - -config STM32H5_TIM8_ADC - bool "TIM8 ADC" - default n - depends on STM32H5_TIM8 && STM32H5_ADC - ---help--- - Reserve timer 8 for use by ADC - - Timer devices may be used for different purposes. If STM32H5_TIM8 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - -choice - prompt "Select ADC for use with TIM8" - default STM32H5_TIM8_ADC1 - depends on STM32H5_TIM8_ADC - -config STM32H5_TIM8_ADC1 - bool "Use TIM8 for ADC1" - depends on STM32H5_ADC1 - select STM32H5_HAVE_ADC1_TIMER - ---help--- - Reserve TIM8 to trigger ADC1 - -config STM32H5_TIM8_ADC2 - bool "Use TIM8 for ADC2" - depends on STM32H5_ADC2 - select STM32H5_HAVE_ADC2_TIMER - ---help--- - Reserve TIM8 to trigger ADC2 - -endchoice - -config STM32H5_TIM15_ADC - bool "TIM15 ADC" - default n - depends on STM32H5_TIM15 && STM32H5_ADC - ---help--- - Reserve timer 15 for use by ADC - - Timer devices may be used for different purposes. If STM32H5_TIM15 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - -choice - prompt "Select ADC for use with TIM15" - default STM32H5_TIM15_ADC1 - depends on STM32H5_TIM15_ADC - -config STM32H5_TIM15_ADC1 - bool "Use TIM15 for ADC1" - depends on STM32H5_ADC1 - select STM32H5_HAVE_ADC1_TIMER - ---help--- - Reserve TIM15 to trigger ADC1 - -config STM32H5_TIM15_ADC2 - bool "Use TIM15 for ADC2" - depends on STM32H5_ADC2 - select STM32H5_HAVE_ADC2_TIMER - ---help--- - Reserve TIM15 to trigger ADC2 - -endchoice - -config STM32H5_HAVE_ADC1_TIMER - bool - -config STM32H5_HAVE_ADC2_TIMER - bool - -config STM32H5_ADC1_SAMPLE_FREQUENCY - int "ADC1 Sampling Frequency" - default 100 - depends on STM32H5_HAVE_ADC1_TIMER - ---help--- - ADC1 sampling frequency. Default: 100Hz - -config STM32H5_ADC1_TIMTRIG - int "ADC1 Timer Trigger" - default 0 - range 0 5 - depends on STM32H5_HAVE_ADC1_TIMER - ---help--- - Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO 5:TRGO2 - -config STM32H5_ADC2_SAMPLE_FREQUENCY - int "ADC2 Sampling Frequency" - default 100 - depends on STM32H5_HAVE_ADC2_TIMER - ---help--- - ADC2 sampling frequency. Default: 100Hz - -config STM32H5_ADC2_TIMTRIG - int "ADC2 Timer Trigger" - default 0 - range 0 5 - depends on STM32H5_HAVE_ADC2_TIMER - ---help--- - Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO 5:TRGO2 - -config STM32H5_TIM1_CAP - bool "TIM1 Capture" - default n - depends on STM32H5_TIM1 - ---help--- - Reserve timer 1 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -config STM32H5_TIM2_CAP - bool "TIM2 Capture" - default n - depends on STM32H5_TIM2 - ---help--- - Reserve timer 2 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -config STM32H5_TIM3_CAP - bool "TIM3 Capture" - default n - depends on STM32H5_TIM3 - ---help--- - Reserve timer 3 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -config STM32H5_TIM4_CAP - bool "TIM4 Capture" - default n - depends on STM32H5_TIM4 - ---help--- - Reserve timer 4 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -config STM32H5_TIM5_CAP - bool "TIM5 Capture" - default n - depends on STM32H5_TIM5 - ---help--- - Reserve timer 5 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -config STM32H5_TIM8_CAP - bool "TIM8 Capture" - default n - depends on STM32H5_TIM8 - ---help--- - Reserve timer 8 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -config STM32H5_TIM12_CAP - bool "TIM12 Capture" - default n - depends on STM32H5_TIM12 - ---help--- - Reserve timer 12 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -config STM32H5_TIM13_CAP - bool "TIM13 Capture" - default n - depends on STM32H5_TIM13 - ---help--- - Reserve timer 13 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -config STM32H5_TIM14_CAP - bool "TIM14 Capture" - default n - depends on STM32H5_TIM14 - ---help--- - Reserve timer 14 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -config STM32H5_TIM15_CAP - bool "TIM15 Capture" - default n - depends on STM32H5_TIM15 - ---help--- - Reserve timer 15 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -config STM32H5_TIM16_CAP - bool "TIM16 Capture" - default n - depends on STM32H5_TIM16 - ---help--- - Reserve timer 16 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -config STM32H5_TIM17_CAP - bool "TIM14 Capture" - default n - depends on STM32H5_TIM17 - ---help--- - Reserve timer 17 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -menu "STM32 TIMx Outputs Configuration" - -config STM32H5_TIM1_CH1POL - int "TIM1 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32H5_TIM1_CH1OUT - ---help--- - TIM1 Channel 1 output polarity - -config STM32H5_TIM1_CH1IDLE - int "TIM1 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32H5_TIM1_CH1OUT - ---help--- - TIM1 Channel 1 output IDLE - -config STM32H5_TIM1_CH1NPOL - int "TIM1 Channel 1 Complementary Output polarity" - default 0 - range 0 1 - depends on STM32H5_TIM1_CH1NOUT - ---help--- - TIM1 Channel 1 Complementary Output polarity - -config STM32H5_TIM1_CH1NIDLE - int "TIM1 Channel 1 Complementary Output IDLE" - default 0 - range 0 1 - depends on STM32H5_TIM1_CH1NOUT - ---help--- - TIM1 Channel 1 Complementary Output IDLE - -config STM32H5_TIM1_CH2POL - int "TIM1 Channel 2 Output polarity" - default 0 - range 0 1 - depends on STM32H5_TIM1_CH2OUT - ---help--- - TIM1 Channel 2 output polarity - -config STM32H5_TIM1_CH2IDLE - int "TIM1 Channel 2 Output IDLE" - default 0 - range 0 1 - depends on STM32H5_TIM1_CH2OUT - ---help--- - TIM1 Channel 2 output IDLE - -config STM32H5_TIM1_CH2NPOL - int "TIM1 Channel 2 Complementary Output polarity" - default 0 - range 0 1 - depends on STM32H5_TIM1_CH2NOUT - ---help--- - TIM1 Channel 2 Complementary Output polarity - -config STM32H5_TIM1_CH2NIDLE - int "TIM1 Channel 2 Complementary Output IDLE" - default 0 - range 0 1 - depends on STM32H5_TIM1_CH2NOUT - ---help--- - TIM1 Channel 2 Complementary Output IDLE - -config STM32H5_TIM1_CH3POL - int "TIM1 Channel 3 Output polarity" - default 0 - range 0 1 - depends on STM32H5_TIM1_CH3OUT - ---help--- - TIM1 Channel 3 output polarity - -config STM32H5_TIM1_CH3IDLE - int "TIM1 Channel 3 Output IDLE" - default 0 - range 0 1 - depends on STM32H5_TIM1_CH3OUT - ---help--- - TIM1 Channel 3 output IDLE - -config STM32H5_TIM1_CH3NPOL - int "TIM1 Channel 3 Complementary Output polarity" - default 0 - range 0 1 - depends on STM32H5_TIM1_CH3NOUT - ---help--- - TIM1 Channel 3 Complementary Output polarity - -config STM32H5_TIM1_CH3NIDLE - int "TIM1 Channel 3 Complementary Output IDLE" - default 0 - range 0 1 - depends on STM32H5_TIM1_CH3NOUT - ---help--- - TIM1 Channel 3 Complementary Output IDLE - -config STM32H5_TIM1_CH4POL - int "TIM1 Channel 4 Output polarity" - default 0 - range 0 1 - depends on STM32H5_TIM1_CH4OUT - ---help--- - TIM1 Channel 4 output polarity - -config STM32H5_TIM1_CH4IDLE - int "TIM1 Channel 4 Output IDLE" - default 0 - range 0 1 - depends on STM32H5_TIM1_CH4OUT - ---help--- - TIM1 Channel 4 output IDLE - -config STM32H5_TIM1_CH5POL - int "TIM1 Channel 5 Output polarity" - default 0 - range 0 1 - depends on STM32H5_TIM1_CH5OUT - ---help--- - TIM1 Channel 5 output polarity - -config STM32H5_TIM1_CH5IDLE - int "TIM1 Channel 5 Output IDLE" - default 0 - range 0 1 - depends on STM32H5_TIM1_CH5OUT - ---help--- - TIM1 Channel 5 output IDLE - -config STM32H5_TIM1_CH6POL - int "TIM1 Channel 6 Output polarity" - default 0 - range 0 1 - depends on STM32H5_TIM1_CH6OUT - ---help--- - TIM1 Channel 6 output polarity - -config STM32H5_TIM1_CH6IDLE - int "TIM1 Channel 6 Output IDLE" - default 0 - range 0 1 - depends on STM32H5_TIM1_CH6OUT - ---help--- - TIM1 Channel 6 output IDLE - -config STM32H5_TIM2_CH1POL - int "TIM2 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32H5_TIM2_CH1OUT - ---help--- - TIM2 Channel 1 output polarity - -config STM32H5_TIM2_CH1IDLE - int "TIM2 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32H5_TIM2_CH1OUT - ---help--- - TIM2 Channel 1 output IDLE - -config STM32H5_TIM2_CH2POL - int "TIM2 Channel 2 Output polarity" - default 0 - range 0 1 - depends on STM32H5_TIM2_CH2OUT - ---help--- - TIM2 Channel 2 output polarity - -config STM32H5_TIM2_CH2IDLE - int "TIM2 Channel 2 Output IDLE" - default 0 - range 0 1 - depends on STM32H5_TIM2_CH2OUT - ---help--- - TIM2 Channel 2 output IDLE - -config STM32H5_TIM2_CH3POL - int "TIM2 Channel 3 Output polarity" - default 0 - range 0 1 - depends on STM32H5_TIM2_CH3OUT - ---help--- - TIM2 Channel 3 output polarity - -config STM32H5_TIM2_CH3IDLE - int "TIM2 Channel 3 Output IDLE" - default 0 - range 0 1 - depends on STM32H5_TIM2_CH3OUT - ---help--- - TIM2 Channel 3 output IDLE - -config STM32H5_TIM2_CH4POL - int "TIM2 Channel 4 Output polarity" - default 0 - range 0 1 - depends on STM32H5_TIM2_CH4OUT - ---help--- - TIM2 Channel 4 output polarity - -config STM32H5_TIM2_CH4IDLE - int "TIM2 Channel 4 Output IDLE" - default 0 - range 0 1 - depends on STM32H5_TIM2_CH4OUT - ---help--- - TIM2 Channel 4 output IDLE - -config STM32H5_TIM3_CH1POL - int "TIM3 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32H5_TIM3_CH1OUT - ---help--- - TIM3 Channel 1 output polarity - -config STM32H5_TIM3_CH1IDLE - int "TIM3 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32H5_TIM3_CH1OUT - ---help--- - TIM3 Channel 1 output IDLE - -config STM32H5_TIM3_CH2POL - int "TIM3 Channel 2 Output polarity" - default 0 - range 0 1 - depends on STM32H5_TIM3_CH2OUT - ---help--- - TIM3 Channel 2 output polarity - -config STM32H5_TIM3_CH2IDLE - int "TIM3 Channel 2 Output IDLE" - default 0 - range 0 1 - depends on STM32H5_TIM3_CH2OUT - ---help--- - TIM3 Channel 2 output IDLE - -config STM32H5_TIM3_CH3POL - int "TIM3 Channel 3 Output polarity" - default 0 - range 0 1 - depends on STM32H5_TIM3_CH3OUT - ---help--- - TIM3 Channel 3 output polarity - -config STM32H5_TIM3_CH3IDLE - int "TIM3 Channel 3 Output IDLE" - default 0 - range 0 1 - depends on STM32H5_TIM3_CH3OUT - ---help--- - TIM3 Channel 3 output IDLE - -config STM32H5_TIM3_CH4POL - int "TIM3 Channel 4 Output polarity" - default 0 - range 0 1 - depends on STM32H5_TIM3_CH4OUT - ---help--- - TIM3 Channel 4 output polarity - -config STM32H5_TIM3_CH4IDLE - int "TIM3 Channel 4 Output IDLE" - default 0 - range 0 1 - depends on STM32H5_TIM3_CH4OUT - ---help--- - TIM3 Channel 4 output IDLE - -config STM32H5_TIM4_CH1POL - int "TIM4 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32H5_TIM4_CH1OUT - ---help--- - TIM4 Channel 1 output polarity - -config STM32H5_TIM4_CH1IDLE - int "TIM4 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32H5_TIM4_CH1OUT - ---help--- - TIM4 Channel 1 output IDLE - -config STM32H5_TIM4_CH2POL - int "TIM4 Channel 2 Output polarity" - default 0 - range 0 1 - depends on STM32H5_TIM4_CH2OUT - ---help--- - TIM4 Channel 2 output polarity - -config STM32H5_TIM4_CH2IDLE - int "TIM4 Channel 2 Output IDLE" - default 0 - range 0 1 - depends on STM32H5_TIM4_CH2OUT - ---help--- - TIM4 Channel 2 output IDLE - -config STM32H5_TIM4_CH3POL - int "TIM4 Channel 3 Output polarity" - default 0 - range 0 1 - depends on STM32H5_TIM4_CH3OUT - ---help--- - TIM4 Channel 3 output polarity - -config STM32H5_TIM4_CH3IDLE - int "TIM4 Channel 3 Output IDLE" - default 0 - range 0 1 - depends on STM32H5_TIM4_CH3OUT - ---help--- - TIM4 Channel 3 output IDLE - -config STM32H5_TIM4_CH4POL - int "TIM4 Channel 4 Output polarity" - default 0 - range 0 1 - depends on STM32H5_TIM4_CH4OUT - ---help--- - TIM4 Channel 4 output polarity - -config STM32H5_TIM4_CH4IDLE - int "TIM4 Channel 4 Output IDLE" - default 0 - range 0 1 - depends on STM32H5_TIM4_CH4OUT - ---help--- - TIM4 Channel 4 output IDLE - -config STM32H5_TIM5_CH1POL - int "TIM5 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32H5_TIM5_CH1OUT - ---help--- - TIM5 Channel 1 output polarity - -config STM32H5_TIM5_CH1IDLE - int "TIM5 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32H5_TIM5_CH1OUT - ---help--- - TIM5 Channel 1 output IDLE - -config STM32H5_TIM5_CH2POL - int "TIM5 Channel 2 Output polarity" - default 0 - range 0 1 - depends on STM32H5_TIM5_CH2OUT - ---help--- - TIM5 Channel 2 output polarity - -config STM32H5_TIM5_CH2IDLE - int "TIM5 Channel 2 Output IDLE" - default 0 - range 0 1 - depends on STM32H5_TIM5_CH2OUT - ---help--- - TIM5 Channel 2 output IDLE - -config STM32H5_TIM5_CH3POL - int "TIM5 Channel 3 Output polarity" - default 0 - range 0 1 - depends on STM32H5_TIM5_CH3OUT - ---help--- - TIM5 Channel 3 output polarity - -config STM32H5_TIM5_CH3IDLE - int "TIM5 Channel 3 Output IDLE" - default 0 - range 0 1 - depends on STM32H5_TIM5_CH3OUT - ---help--- - TIM5 Channel 3 output IDLE - -config STM32H5_TIM5_CH4POL - int "TIM5 Channel 4 Output polarity" - default 0 - range 0 1 - depends on STM32H5_TIM5_CH4OUT - ---help--- - TIM5 Channel 4 output polarity - -config STM32H5_TIM5_CH4IDLE - int "TIM5 Channel 4 Output IDLE" - default 0 - range 0 1 - depends on STM32H5_TIM5_CH4OUT - ---help--- - TIM5 Channel 4 output IDLE - -config STM32H5_TIM8_CH1POL - int "TIM8 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32H5_TIM8_CH1OUT - ---help--- - TIM8 Channel 1 output polarity - -config STM32H5_TIM8_CH1IDLE - int "TIM8 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32H5_TIM8_CH1OUT - ---help--- - TIM8 Channel 1 output IDLE - -config STM32H5_TIM8_CH1NPOL - int "TIM8 Channel 1 Complementary Output polarity" - default 0 - range 0 1 - depends on STM32H5_TIM8_CH1NOUT - ---help--- - TIM8 Channel 1 Complementary Output polarity - -config STM32H5_TIM8_CH1NIDLE - int "TIM8 Channel 1 Complementary Output IDLE" - default 0 - range 0 1 - depends on STM32H5_TIM8_CH1NOUT - ---help--- - TIM8 Channel 1 Complementary Output IDLE - -config STM32H5_TIM8_CH2POL - int "TIM8 Channel 2 Output polarity" - default 0 - range 0 1 - depends on STM32H5_TIM8_CH2OUT - ---help--- - TIM8 Channel 2 output polarity - -config STM32H5_TIM8_CH2IDLE - int "TIM8 Channel 2 Output IDLE" - default 0 - range 0 1 - depends on STM32H5_TIM8_CH2OUT - ---help--- - TIM8 Channel 2 output IDLE - -config STM32H5_TIM8_CH2NPOL - int "TIM8 Channel 2 Complementary Output polarity" - default 0 - range 0 1 - depends on STM32H5_TIM8_CH2NOUT - ---help--- - TIM8 Channel 2 Complementary Output polarity - -config STM32H5_TIM8_CH2NIDLE - int "TIM8 Channel 2 Complementary Output IDLE" - default 0 - range 0 1 - depends on STM32H5_TIM8_CH2NOUT - ---help--- - TIM8 Channel 2 Complementary Output IDLE - -config STM32H5_TIM8_CH3POL - int "TIM8 Channel 3 Output polarity" - default 0 - range 0 1 - depends on STM32H5_TIM8_CH3OUT - ---help--- - TIM8 Channel 3 output polarity - -config STM32H5_TIM8_CH3IDLE - int "TIM8 Channel 3 Output IDLE" - default 0 - range 0 1 - depends on STM32H5_TIM8_CH3OUT - ---help--- - TIM8 Channel 3 output IDLE - -config STM32H5_TIM8_CH3NPOL - int "TIM8 Channel 3 Complementary Output polarity" - default 0 - range 0 1 - depends on STM32H5_TIM8_CH3NOUT - ---help--- - TIM8 Channel 3 Complementary Output polarity - -config STM32H5_TIM8_CH3NIDLE - int "TIM8 Channel 3 Complementary Output IDLE" - default 0 - range 0 1 - depends on STM32H5_TIM8_CH3NOUT - ---help--- - TIM8 Channel 3 Complementary Output IDLE - -config STM32H5_TIM8_CH4POL - int "TIM8 Channel 4 Output polarity" - default 0 - range 0 1 - depends on STM32H5_TIM8_CH4OUT - ---help--- - TIM8 Channel 4 output polarity - -config STM32H5_TIM8_CH4IDLE - int "TIM8 Channel 4 Output IDLE" - default 0 - range 0 1 - depends on STM32H5_TIM8_CH4OUT - ---help--- - TIM8 Channel 4 output IDLE - -config STM32H5_TIM8_CH5POL - int "TIM8 Channel 5 Output polarity" - default 0 - range 0 1 - depends on STM32H5_TIM8_CH5OUT - ---help--- - TIM8 Channel 5 output polarity - -config STM32H5_TIM8_CH5IDLE - int "TIM8 Channel 5 Output IDLE" - default 0 - range 0 1 - depends on STM32H5_TIM8_CH5OUT - ---help--- - TIM8 Channel 5 output IDLE - -config STM32H5_TIM8_CH6POL - int "TIM8 Channel 6 Output polarity" - default 0 - range 0 1 - depends on STM32H5_TIM8_CH6OUT - ---help--- - TIM8 Channel 6 output polarity - -config STM32H5_TIM8_CH6IDLE - int "TIM8 Channel 6 Output IDLE" - default 0 - range 0 1 - depends on STM32H5_TIM8_CH6OUT - ---help--- - TIM8 Channel 6 output IDLE - -config STM32H5_TIM12_CH1POL - int "TIM12 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32H5_TIM12_CH1OUT - ---help--- - TIM12 Channel 1 output polarity - -config STM32H5_TIM12_CH1IDLE - int "TIM12 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32H5_TIM12_CH1OUT - ---help--- - TIM12 Channel 1 output IDLE - -config STM32H5_TIM12_CH2POL - int "TIM12 Channel 2 Output polarity" - default 0 - range 0 1 - depends on STM32H5_TIM12_CH2OUT - ---help--- - TIM12 Channel 2 output polarity - -config STM32H5_TIM12_CH2IDLE - int "TIM12 Channel 2 Output IDLE" - default 0 - range 0 1 - depends on STM32H5_TIM12_CH2OUT - ---help--- - TIM12 Channel 2 output IDLE - -config STM32H5_TIM13_CH1POL - int "TIM13 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32H5_TIM13_CH1OUT - ---help--- - TIM13 Channel 1 output polarity - -config STM32H5_TIM13_CH1IDLE - int "TIM13 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32H5_TIM13_CH1OUT - ---help--- - TIM13 Channel 1 output IDLE - -config STM32H5_TIM14_CH1POL - int "TIM14 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32H5_TIM14_CH1OUT - ---help--- - TIM14 Channel 1 output polarity - -config STM32H5_TIM14_CH1IDLE - int "TIM14 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32H5_TIM14_CH1OUT - ---help--- - TIM14 Channel 1 output IDLE - -config STM32H5_TIM15_CH1POL - int "TIM15 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32H5_TIM15_CH1OUT - ---help--- - TIM15 Channel 1 output polarity - -config STM32H5_TIM15_CH1IDLE - int "TIM15 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32H5_TIM15_CH1OUT - ---help--- - TIM15 Channel 1 output IDLE - -config STM32H5_TIM15_CH1NPOL - int "TIM15 Channel 1 Complementary Output polarity" - default 0 - range 0 1 - depends on STM32H5_TIM15_CH1NOUT - ---help--- - TIM15 Channel 1 Complementary Output polarity - -config STM32H5_TIM15_CH1NIDLE - int "TIM15 Channel 1 Complementary Output IDLE" - default 0 - range 0 1 - depends on STM32H5_TIM15_CH1NOUT - ---help--- - TIM15 Channel 1 Complementary Output IDLE - -config STM32H5_TIM15_CH2POL - int "TIM15 Channel 2 Output polarity" - default 0 - range 0 1 - depends on STM32H5_TIM15_CH2OUT - ---help--- - TIM15 Channel 2 output polarity - -config STM32H5_TIM15_CH2IDLE - int "TIM15 Channel 2 Output IDLE" - default 0 - range 0 1 - depends on STM32H5_TIM15_CH2OUT - ---help--- - TIM15 Channel 2 output IDLE - -config STM32H5_TIM15_CH2NPOL - int "TIM15 Channel 2 Complementary Output polarity" - default 0 - range 0 1 - depends on STM32H5_TIM15_CH2NOUT - ---help--- - TIM15 Channel 2 Complementary Output polarity - -config STM32H5_TIM15_CH2NIDLE - int "TIM15 Channel 2 Complementary Output IDLE" - default 0 - range 0 1 - depends on STM32H5_TIM15_CH2NOUT - ---help--- - TIM15 Channel 2 Complementary Output IDLE - -config STM32H5_TIM16_CH1POL - int "TIM16 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32H5_TIM16_CH1OUT - ---help--- - TIM16 Channel 1 output polarity - -config STM32H5_TIM16_CH1IDLE - int "TIM16 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32H5_TIM16_CH1OUT - ---help--- - TIM16 Channel 1 output IDLE - -config STM32H5_TIM17_CH1POL - int "TIM17 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32H5_TIM17_CH1OUT - ---help--- - TIM17 Channel 1 output polarity - -config STM32H5_TIM17_CH1IDLE - int "TIM17 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32H5_TIM17_CH1OUT - ---help--- - TIM17 Channel 1 output IDLE - -endmenu #STM32 TIMx Outputs Configuration - -endmenu # Timer Configuration - -comment "USB Device Configuration" - -menu "USB Full Speed Device Configuration" - depends on STM32H5_USBFS - -config STM32H5_USBFS_REGDEBUG - bool "Register-Level Debug" - default n - depends on STM32H5_USBFS && DEBUG_USB_INFO - ---help--- - Enable very low-level register access debug. - -endmenu - -comment "USB Host Configuration" - -menu "USB Full Speed Host Configuration" - depends on STM32H5_USBFS_HOST - -config STM32H5_USBDRD_NCHANNELS - int "Number of host channels" - default 8 - range 1 8 - depends on STM32H5_USBFS_HOST - ---help--- - Number of USB host channels to use. - -config STM32H5_USBDRD_DESCSIZE - int "Descriptor buffer size" - default 128 - depends on STM32H5_USBFS_HOST - ---help--- - Size of descriptor/request buffers. - -endmenu - -config STM32H5_SERIALDRIVER - bool - -menu "[LP]U[S]ART Configuration" - depends on STM32H5_USART - -choice - prompt "LPUART1 Driver Configuration" - default STM32H5_LPUART1_SERIALDRIVER - depends on STM32H5_LPUART1 - -config STM32H5_LPUART1_SERIALDRIVER - bool "Standard serial driver" - select LPUART1_SERIALDRIVER - select STM32H5_SERIALDRIVER - -endchoice # LPUART1 Driver Configuration - -if LPUART1_SERIALDRIVER - -config LPUART1_RS485 - bool "RS-485 on LPUART1" - default n - depends on STM32H5_LPUART1 - ---help--- - Enable RS-485 interface on LPUART1. Your board config will have to - provide GPIO_LPUART1_RS485_DIR pin definition. Currently it cannot be - used with LPUART1_RXDMA. - -config LPUART1_RS485_DIR_POLARITY - int "LPUART1 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on LPUART1_RS485 - ---help--- - Polarity of DIR pin for RS-485 on LPUART1. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config LPUART1_RXDMA - bool "LPUART1 RX DMA" - default n - depends on STM32H5_LPUART1 && (STM32H5_DMA1 || STM32H5_DMA2) - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -config LPUART1_UNCONFIG_RX_ON_CLOSE - bool "Unconfigure LPUART1 RX pin on close" - default n - -config LPUART1_UNCONFIG_TX_ON_CLOSE - bool "Unconfigure LPUART1 TX pin on close" - default n - -config LPUART1_UNCONFIG_DIR_ON_CLOSE - depends on LPUART1_RS485 - bool "Unconfigure LPUART1 DIR pin on close" - default n - -endif # LPUART1_SERIALDRIVER - -choice - prompt "USART1 Driver Configuration" - default STM32H5_USART1_SERIALDRIVER - depends on STM32H5_USART1 - -config STM32H5_USART1_SERIALDRIVER - bool "Standard serial driver" - select USART1_SERIALDRIVER - select STM32H5_SERIALDRIVER - -endchoice # USART1 Driver Configuration - -if USART1_SERIALDRIVER - -config USART1_RS485 - bool "RS-485 on USART1" - default n - depends on STM32H5_USART1 - ---help--- - Enable RS-485 interface on USART1. Your board config will have to - provide GPIO_USART1_RS485_DIR pin definition. Currently it cannot be - used with USART1_RXDMA. - -config USART1_RS485_DIR_POLARITY - int "USART1 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on USART1_RS485 - ---help--- - Polarity of DIR pin for RS-485 on USART1. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config USART1_RXDMA - bool "USART1 RX DMA" - default n - depends on STM32H5_USART1 && (STM32H5_DMA1 || STM32H5_DMA2) - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -config USART1_UNCONFIG_RX_ON_CLOSE - bool "Unconfigure USART1 RX pin on close" - default n - -config USART1_UNCONFIG_TX_ON_CLOSE - bool "Unconfigure USART1 TX pin on close" - default n - -config USART1_UNCONFIG_DIR_ON_CLOSE - depends on USART1_RS485 - bool "Unconfigure USART1 DIR pin on close" - default n - -endif # USART1_SERIALDRIVER - -choice - prompt "USART2 Driver Configuration" - default STM32H5_USART2_SERIALDRIVER - depends on STM32H5_USART2 - -config STM32H5_USART2_SERIALDRIVER - bool "Standard serial driver" - select USART2_SERIALDRIVER - select STM32H5_SERIALDRIVER - -endchoice # USART2 Driver Configuration - -if USART2_SERIALDRIVER - -config USART2_RS485 - bool "RS-485 on USART2" - default n - depends on STM32H5_USART2 - ---help--- - Enable RS-485 interface on USART2. Your board config will have to - provide GPIO_USART2_RS485_DIR pin definition. Currently it cannot be - used with USART2_RXDMA. - -config USART2_RS485_DIR_POLARITY - int "USART2 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on USART2_RS485 - ---help--- - Polarity of DIR pin for RS-485 on USART2. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config USART2_RXDMA - bool "USART2 RX DMA" - default n - depends on STM32H5_USART2 && (STM32H5_DMA1 || STM32H5_DMA2) - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -config USART2_UNCONFIG_RX_ON_CLOSE - bool "Unconfigure USART2 RX pin on close" - default n - -config USART2_UNCONFIG_TX_ON_CLOSE - bool "Unconfigure USART2 TX pin on close" - default n - -config USART2_UNCONFIG_DIR_ON_CLOSE - depends on USART2_RS485 - bool "Unconfigure USART2 DIR pin on close" - default n - -endif # USART2_SERIALDRIVER - -choice - prompt "USART3 Driver Configuration" - default STM32H5_USART3_SERIALDRIVER - depends on STM32H5_USART3 - -config STM32H5_USART3_SERIALDRIVER - bool "Standard serial driver" - select USART3_SERIALDRIVER - select STM32H5_SERIALDRIVER - -endchoice # USART3 Driver Configuration - -if USART3_SERIALDRIVER - -config USART3_RS485 - bool "RS-485 on USART3" - default n - depends on STM32H5_USART3 - ---help--- - Enable RS-485 interface on USART3. Your board config will have to - provide GPIO_USART3_RS485_DIR pin definition. Currently it cannot be - used with USART3_RXDMA. - -config USART3_RS485_DIR_POLARITY - int "USART3 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on USART3_RS485 - ---help--- - Polarity of DIR pin for RS-485 on USART3. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config USART3_RXDMA - bool "USART3 RX DMA" - default n - depends on STM32H5_USART3 && (STM32H5_DMA1 || STM32H5_DMA2) - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -config USART3_UNCONFIG_RX_ON_CLOSE - bool "Unconfigure USART3 RX pin on close" - default n - -config USART3_UNCONFIG_TX_ON_CLOSE - bool "Unconfigure USART3 TX pin on close" - default n - -config USART3_UNCONFIG_DIR_ON_CLOSE - depends on USART3_RS485 - bool "Unconfigure USART3 DIR pin on close" - default n - -endif # USART3_SERIALDRIVER - -choice - prompt "UART4 Driver Configuration" - default STM32H5_UART4_SERIALDRIVER - depends on STM32H5_UART4 - -config STM32H5_UART4_SERIALDRIVER - bool "Standard serial driver" - select UART4_SERIALDRIVER - select STM32H5_SERIALDRIVER - -endchoice # UART4 Driver Configuration - -if UART4_SERIALDRIVER - -config UART4_RS485 - bool "RS-485 on UART4" - default n - depends on STM32H5_UART4 - ---help--- - Enable RS-485 interface on UART4. Your board config will have to - provide GPIO_UART4_RS485_DIR pin definition. Currently it cannot be - used with UART4_RXDMA. - -config UART4_RS485_DIR_POLARITY - int "UART4 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on UART4_RS485 - ---help--- - Polarity of DIR pin for RS-485 on UART4. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config UART4_RXDMA - bool "UART4 RX DMA" - default n - depends on STM32H5_UART4 && (STM32H5_DMA1 || STM32H5_DMA2) - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -config UART4_UNCONFIG_RX_ON_CLOSE - bool "Unconfigure UART4 RX pin on close" - default n - -config UART4_UNCONFIG_TX_ON_CLOSE - bool "Unconfigure UART4 TX pin on close" - default n - -config UART4_UNCONFIG_DIR_ON_CLOSE - depends on UART4_RS485 - bool "Unconfigure UART4 DIR pin on close" - default n - -endif # UART4_SERIALDRIVER - -choice - prompt "UART5 Driver Configuration" - default STM32H5_UART5_SERIALDRIVER - depends on STM32H5_UART5 - -config STM32H5_UART5_SERIALDRIVER - bool "Standard serial driver" - select UART5_SERIALDRIVER - select STM32H5_SERIALDRIVER - -endchoice # UART5 Driver Configuration - -if UART5_SERIALDRIVER - -config UART5_RS485 - bool "RS-485 on UART5" - default n - depends on STM32H5_UART5 - ---help--- - Enable RS-485 interface on UART5. Your board config will have to - provide GPIO_UART5_RS485_DIR pin definition. Currently it cannot be - used with UART5_RXDMA. - -config UART5_RS485_DIR_POLARITY - int "UART5 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on UART5_RS485 - ---help--- - Polarity of DIR pin for RS-485 on UART5. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config UART5_RXDMA - bool "UART5 RX DMA" - default n - depends on STM32H5_UART5 && (STM32H5_DMA1 || STM32H5_DMA2) - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -config UART5_UNCONFIG_RX_ON_CLOSE - bool "Unconfigure UART5 RX pin on close" - default n - -config UART5_UNCONFIG_TX_ON_CLOSE - bool "Unconfigure UART5 TX pin on close" - default n - -config UART5_UNCONFIG_DIR_ON_CLOSE - depends on UART5_RS485 - bool "Unconfigure UART5 DIR pin on close" - default n - -endif # UART5_SERIALDRIVER - -choice - prompt "USART6 Driver Configuration" - default STM32H5_USART6_SERIALDRIVER - depends on STM32H5_USART6 - -config STM32H5_USART6_SERIALDRIVER - bool "Standard serial driver" - select USART6_SERIALDRIVER - select STM32H5_SERIALDRIVER - -endchoice # USART6 Driver Configuration - -if USART6_SERIALDRIVER - -config USART6_RS485 - bool "RS-485 on USART6" - default n - depends on STM32H5_USART6 - ---help--- - Enable RS-485 interface on USART6. Your board config will have to - provide GPIO_USART6_RS485_DIR pin definition. Currently it cannot be - used with USART6_RXDMA. - -config USART6_RS485_DIR_POLARITY - int "USART6 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on USART6_RS485 - ---help--- - Polarity of DIR pin for RS-485 on USART6. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config USART6_RXDMA - bool "USART6 RX DMA" - default n - depends on STM32H5_USART6 && (STM32H5_DMA1 || STM32H5_DMA2) - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -config USART6_UNCONFIG_RX_ON_CLOSE - bool "Unconfigure USART6 RX pin on close" - default n - -config USART6_UNCONFIG_TX_ON_CLOSE - bool "Unconfigure USART6 TX pin on close" - default n - -config USART6_UNCONFIG_DIR_ON_CLOSE - depends on USART6_RS485 - bool "Unconfigure USART6 DIR pin on close" - default n - -endif # USART6_SERIALDRIVER - -if UART7_SERIALDRIVER - -config UART7_RS485 - bool "RS-485 on UART7" - default n - depends on STM32H5_UART7 - ---help--- - Enable RS-485 interface on UART7. Your board config will have to - provide GPIO_UART7_RS485_DIR pin definition. Currently it cannot be - used with UART7_RXDMA. - -config UART7_RS485_DIR_POLARITY - int "UART7 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on UART7_RS485 - ---help--- - Polarity of DIR pin for RS-485 on UART7. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config UART7_RXDMA - bool "UART7 RX DMA" - default n - depends on STM32H5_UART7 && (STM32H5_DMA1 || STM32H5_DMA2) - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -config UART7_UNCONFIG_RX_ON_CLOSE - bool "Unconfigure UART7 RX pin on close" - default n - -config UART7_UNCONFIG_TX_ON_CLOSE - bool "Unconfigure UART7 TX pin on close" - default n - -config UART7_UNCONFIG_DIR_ON_CLOSE - depends on UART7_RS485 - bool "Unconfigure UART7 DIR pin on close" - default n - -endif # UART7_SERIALDRIVER - -if UART8_SERIALDRIVER - -config UART8_RS485 - bool "RS-485 on UART8" - default n - depends on STM32H5_UART8 - ---help--- - Enable RS-485 interface on UART8. Your board config will have to - provide GPIO_UART8_RS485_DIR pin definition. Currently it cannot be - used with UART8_RXDMA. - -config UART8_RS485_DIR_POLARITY - int "UART8 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on UART8_RS485 - ---help--- - Polarity of DIR pin for RS-485 on UART8. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config UART8_RXDMA - bool "UART8 RX DMA" - default n - depends on STM32H5_UART8 && (STM32H5_DMA1 || STM32H5_DMA2) - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -config UART8_UNCONFIG_RX_ON_CLOSE - bool "Unconfigure UART8 RX pin on close" - default n - -config UART8_UNCONFIG_TX_ON_CLOSE - bool "Unconfigure UART8 TX pin on close" - default n - -config UART8_UNCONFIG_DIR_ON_CLOSE - depends on UART8_RS485 - bool "Unconfigure UART8 DIR pin on close" - default n - -endif # UART8_SERIALDRIVER - -if UART9_SERIALDRIVER - -config UART9_RS485 - bool "RS-485 on UART9" - default n - depends on STM32H5_UART9 - ---help--- - Enable RS-485 interface on UART9. Your board config will have to - provide GPIO_UART9_RS485_DIR pin definition. Currently it cannot be - used with UART9_RXDMA. - -config UART9_RS485_DIR_POLARITY - int "UART9 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on UART9_RS485 - ---help--- - Polarity of DIR pin for RS-485 on UART9. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config UART9_RXDMA - bool "UART9 RX DMA" - default n - depends on STM32H5_UART9 && (STM32H5_DMA1 || STM32H5_DMA2) - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -config UART9_UNCONFIG_RX_ON_CLOSE - bool "Unconfigure UART9 RX pin on close" - default n - -config UART9_UNCONFIG_TX_ON_CLOSE - bool "Unconfigure UART9 TX pin on close" - default n - -config UART9_UNCONFIG_DIR_ON_CLOSE - depends on UART9_RS485 - bool "Unconfigure UART9 DIR pin on close" - default n - -endif # UART9_SERIALDRIVER - -if USART10_SERIALDRIVER - -config USART10_RS485 - bool "RS-485 on USART10" - default n - depends on STM32H5_USART10 - ---help--- - Enable RS-485 interface on USART10. Your board config will have to - provide GPIO_USART10_RS485_DIR pin definition. Currently it cannot be - used with USART10_RXDMA. - -config USART10_RS485_DIR_POLARITY - int "USART10 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on USART10_RS485 - ---help--- - Polarity of DIR pin for RS-485 on USART10. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config USART10_RXDMA - bool "USART10 RX DMA" - default n - depends on STM32H5_USART10 && (STM32H5_DMA1 || STM32H5_DMA2) - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -config USART10_UNCONFIG_RX_ON_CLOSE - bool "Unconfigure USART10 RX pin on close" - default n - -config USART10_UNCONFIG_TX_ON_CLOSE - bool "Unconfigure USART10 TX pin on close" - default n - -config USART10_UNCONFIG_DIR_ON_CLOSE - depends on USART10_RS485 - bool "Unconfigure USART10 DIR pin on close" - default n - -endif # USART10_SERIALDRIVER - -if USART11_SERIALDRIVER - -config USART11_RS485 - bool "RS-485 on USART11" - default n - depends on STM32H5_USART11 - ---help--- - Enable RS-485 interface on USART11. Your board config will have to - provide GPIO_USART11_RS485_DIR pin definition. Currently it cannot be - used with USART11_RXDMA. - -config USART11_RS485_DIR_POLARITY - int "USART11 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on USART11_RS485 - ---help--- - Polarity of DIR pin for RS-485 on USART11. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config USART11_RXDMA - bool "USART11 RX DMA" - default n - depends on STM32H5_USART11 && (STM32H5_DMA1 || STM32H5_DMA2) - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -config USART11_UNCONFIG_RX_ON_CLOSE - bool "Unconfigure USART11 RX pin on close" - default n - -config USART11_UNCONFIG_TX_ON_CLOSE - bool "Unconfigure USART11 TX pin on close" - default n - -config USART11_UNCONFIG_DIR_ON_CLOSE - depends on USART11_RS485 - bool "Unconfigure USART11 DIR pin on close" - default n - -endif # USART11_SERIALDRIVER - -if UART12_SERIALDRIVER - -config UART12_RS485 - bool "RS-485 on UART12" - default n - depends on STM32H5_UART12 - ---help--- - Enable RS-485 interface on UART12. Your board config will have to - provide GPIO_UART12_RS485_DIR pin definition. Currently it cannot be - used with UART12_RXDMA. - -config UART12_RS485_DIR_POLARITY - int "UART12 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on UART12_RS485 - ---help--- - Polarity of DIR pin for RS-485 on UART12. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config UART12_RXDMA - bool "UART12 RX DMA" - default n - depends on STM32H5_UART12 && (STM32H5_DMA1 || STM32H5_DMA2) - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -config UART12_UNCONFIG_RX_ON_CLOSE - bool "Unconfigure UART12 RX pin on close" - default n - -config UART12_UNCONFIG_TX_ON_CLOSE - bool "Unconfigure UART12 TX pin on close" - default n - -config UART12_UNCONFIG_DIR_ON_CLOSE - depends on UART12_RS485 - bool "Unconfigure UART12 DIR pin on close" - default n - -endif # UART12_SERIALDRIVER - -if STM32H5_SERIALDRIVER - -comment "Serial Driver Configuration" - -config STM32H5_SERIAL_RXDMA_BUFFER_SIZE - int "Rx DMA buffer size" - default 32 - depends on USART1_RXDMA || USART2_RXDMA || USART3_RXDMA || USART6_RXDMA || USART10_RXDMA || \ - USART11_RXDMA || UART4_RXDMA || UART5_RXDMA || UART7_RXDMA || UART8_RXDMA || \ - UART9_RXDMA || UART12_RXDMA || LPUART1_RXDMA - ---help--- - The DMA buffer size when using RX DMA to emulate a FIFO. - - When streaming data, the generic serial layer will be called - every time the FIFO receives half this number of bytes. - - Value given here will be rounded up to next multiple of 32 bytes. - -config STM32H5_SERIAL_DISABLE_REORDERING - bool "Disable reordering of ttySx devices." - depends on STM32H5_USART1 || STM32H5_USART2 || STM32H5_USART3 || STM32H5_UART4 || STM32H5_UART5 - default n - ---help--- - NuttX per default reorders the serial ports (/dev/ttySx) so that the - console is always on /dev/ttyS0. If more than one UART is in use this - can, however, have the side-effect that all port mappings - (hardware USART1 -> /dev/ttyS0) change if the console is moved to another - UART. This is in particular relevant if a project uses the USB console - in some boards and a serial console in other boards, but does not - want the side effect of having all serial port names change when just - the console is moved from serial to USB. - -config STM32H5_FLOWCONTROL_BROKEN - bool "Use Software UART RTS flow control" - depends on STM32H5_USART - default n - ---help--- - Enable UART RTS flow control using Software. Because STM - Current STM32 have broken HW based RTS behavior (they assert - nRTS after every byte received) Enable this setting workaround - this issue by using software based management of RTS - -config STM32H5_USART_BREAKS - bool "Add TIOxSBRK to support sending Breaks" - depends on STM32H5_USART - default n - ---help--- - Add TIOCxBRK routines to send a line break per the STM32 manual, the - break will be a pulse based on the value M. This is not a BSD compatible - break. - -config STM32H5_SERIALBRK_BSDCOMPAT - bool "Use GPIO To send Break" - depends on STM32H5_USART && STM32H5_USART_BREAKS - default n - ---help--- - Enable using GPIO on the TX pin to send a BSD compatible break: - TIOCSBRK will start the break and TIOCCBRK will end the break. - The current STM32H5 U[S]ARTS have no way to leave the break on - (TX=LOW) because software starts the break and then the hardware - automatically clears the break. This makes it difficult to send - a long break. - -config STM32H5_USART_SINGLEWIRE - bool "Single Wire Support" - default n - depends on STM32H5_USART - ---help--- - Enable single wire UART support. The option enables support for the - TIOCSSINGLEWIRE ioctl in the STM32H5 serial driver. - -config STM32H5_USART_INVERT - bool "Signal Invert Support" - default n - depends on STM32H5_USART - ---help--- - Enable signal inversion UART support. The option enables support for the - TIOCSINVERT ioctl in the STM32H5 serial driver. - -config STM32H5_USART_SWAP - bool "Swap RX/TX pins support" - default n - depends on STM32H5_USART - ---help--- - Enable RX/TX pin swapping support. The option enables support for the - TIOCSSWAP ioctl in the STM32H5 serial driver. - -if PM - -config STM32H5_PM_SERIAL_ACTIVITY - int "PM serial activity" - default 10 - ---help--- - PM activity reported to power management logic on every serial - interrupt. - -endif -endif # STM32H5_SERIALDRIVER - -endmenu # U[S]ART Configuration - -menu "Ethernet MAC Configuration" - depends on STM32H5_ETHMAC - -config STM32H5_PHYADDR - int "PHY address" - default 0 - ---help--- - The 5-bit address of the PHY on the board. Default: 0 - -config STM32H5_PHYINIT - bool "Board-specific PHY Initialization" - default n - ---help--- - Some boards require specialized initialization of the PHY before it can be used. - This may include such things as configuring GPIOs, resetting the PHY, etc. - If STM32H5_PHYINIT is defined in the configuration then the board specific logic - must provide stm32_phyinitialize(); The STM32 Ethernet driver will call this - function one time before it first uses the PHY. - -config STM32H5_PHY_POLLING - bool "Support network monitoring by polling the PHY" - default n - depends on STM32H5_HAVE_PHY_POLLED - select ARCH_PHY_POLLED - ---help--- - Some boards may not have an interrupt connected to the PHY. - This option allows the network monitor to be used by polling the PHY for status. - -config STM32H5_MII - bool "Use MII interface" - default n - ---help--- - Support Ethernet MII interface. - -choice - prompt "MII clock configuration" - default STM32H5_MII_EXTCLK - depends on STM32H5_MII - -config STM32H5_MII_MCO1 - bool "Use MC01 as MII clock" - ---help--- - Use MC01 to clock the MII interface. - -config STM32H5_MII_MCO2 - bool "Use MC02 as MII clock" - ---help--- - Use MC02 to clock the MII interface. - -config STM32H5_MII_EXTCLK - bool "External MII clock" - ---help--- - Clocking is provided by external logic. - -endchoice - -config STM32H5_AUTONEG - bool "Use autonegotiation" - default y - ---help--- - Use PHY autonegotiation to determine speed and mode - -config STM32H5_ETH_NRXDESC - int "Number of RX descriptors" - default 8 - ---help--- - Number of RX DMA descriptors to use. - -config STM32H5_ETH_NTXDESC - int "Number of TX descriptors" - default 4 - ---help--- - Number of TX DMA descriptors to use. - -config STM32H5_ETH_HWCHECKSUM - bool "Enable ethernet hardware checksum" - default n - ---help--- - Enable the IPv4/IPv6 header and TCP/UDP/ICMP payload checksum offload - engine in the Ethernet MAC. - When enabled, hardware generates checksums for TX and checks RX frames. - Be sure to disable software checksums (NET_TCP_CHECKSUMS, NET_UDP_CHECKSUMS, - NET_ICMP_CHECKSUMS, NET_IPV4_CHECKSUMS, NET_IPV6_CHECKSUMS) to avoid - redundant verification in the network stack. - -config STM32H5_ETHFD - bool "Full duplex" - default n - depends on !STM32H5_AUTONEG - ---help--- - If STM32H5_AUTONEG is not defined, then this may be defined to select full duplex - mode. Default: half-duplex - -config STM32H5_ETH100MBPS - bool "100 Mbps" - default n - depends on !STM32H5_AUTONEG - ---help--- - If STM32H5_AUTONEG is not defined, then this may be defined to select 100 MBps - speed. Default: 10 Mbps - -config STM32H5_PHYSR - int "PHY Status Register Address (decimal)" - depends on STM32H5_AUTONEG - ---help--- - This must be provided if STM32H5_AUTONEG is defined. The PHY status register - address may diff from PHY to PHY. This configuration sets the address of - the PHY status register. - -config STM32H5_PHYSR_ALTCONFIG - bool "PHY Status Alternate Bit Layout" - default n - depends on STM32H5_AUTONEG - ---help--- - Different PHYs present speed and mode information in different ways. Some - will present separate information for speed and mode (this is the default). - Those PHYs, for example, may provide a 10/100 Mbps indication and a separate - full/half duplex indication. This options selects an alternative representation - where speed and mode information are combined. This might mean, for example, - separate bits for 10HD, 100HD, 10FD and 100FD. - -config STM32H5_PHYSR_SPEED - hex "PHY Speed Mask" - depends on STM32H5_AUTONEG && !STM32H5_PHYSR_ALTCONFIG - ---help--- - This must be provided if STM32H5_AUTONEG is defined. This provides bit mask - for isolating the 10 or 100MBps speed indication. - -config STM32H5_PHYSR_100MBPS - hex "PHY 100Mbps Speed Value" - depends on STM32H5_AUTONEG && !STM32H5_PHYSR_ALTCONFIG - ---help--- - This must be provided if STM32H5_AUTONEG is defined. This provides the value - of the speed bit(s) indicating 100MBps speed. - -config STM32H5_PHYSR_MODE - hex "PHY Mode Mask" - depends on STM32H5_AUTONEG && !STM32H5_PHYSR_ALTCONFIG - ---help--- - This must be provided if STM32H5_AUTONEG is defined. This provide bit mask - for isolating the full or half duplex mode bits. - -config STM32H5_PHYSR_FULLDUPLEX - hex "PHY Full Duplex Mode Value" - depends on STM32H5_AUTONEG && !STM32H5_PHYSR_ALTCONFIG - ---help--- - This must be provided if STM32H5_AUTONEG is defined. This provides the - value of the mode bits indicating full duplex mode. - -config STM32H5_PHYSR_ALTMODE - hex "PHY Mode Mask" - depends on STM32H5_AUTONEG && STM32H5_PHYSR_ALTCONFIG - ---help--- - This must be provided if STM32H5_AUTONEG is defined. This provide bit mask - for isolating the speed and full/half duplex mode bits. - -config STM32H5_PHYSR_10HD - hex "10MBase-T Half Duplex Value" - depends on STM32H5_AUTONEG && STM32H5_PHYSR_ALTCONFIG - ---help--- - This must be provided if STM32H5_AUTONEG is defined. This is the value - under the bit mask that represents the 10Mbps, half duplex setting. - -config STM32H5_PHYSR_100HD - hex "100Base-T Half Duplex Value" - depends on STM32H5_AUTONEG && STM32H5_PHYSR_ALTCONFIG - ---help--- - This must be provided if STM32H5_AUTONEG is defined. This is the value - under the bit mask that represents the 100Mbps, half duplex setting. - -config STM32H5_PHYSR_10FD - hex "10Base-T Full Duplex Value" - depends on STM32H5_AUTONEG && STM32H5_PHYSR_ALTCONFIG - ---help--- - This must be provided if STM32H5_AUTONEG is defined. This is the value - under the bit mask that represents the 10Mbps, full duplex setting. - -config STM32H5_PHYSR_100FD - hex "100Base-T Full Duplex Value" - depends on STM32H5_AUTONEG && STM32H5_PHYSR_ALTCONFIG - ---help--- - This must be provided if STM32H5_AUTONEG is defined. This is the value - under the bit mask that represents the 100Mbps, full duplex setting. - -config STM32H5_ETH_PTP - bool "Precision Time Protocol (PTP)" - default n - ---help--- - Precision Time Protocol (PTP). Not supported but some hooks are indicated - with this condition. - -config STM32H5_RMII - bool - default !STM32H5_MII - -choice - prompt "RMII clock configuration" - default STM32H5_RMII_EXTCLK - depends on STM32H5_RMII - -config STM32H5_RMII_MCO1 - bool "Use MC01 as RMII clock" - ---help--- - Use MCO1 to clock the RMII interface. - -config STM32H5_RMII_MCO2 - bool "Use MC02 as RMII clock" - ---help--- - Use MCO2 to clock the RMII interface. - -config STM32H5_RMII_EXTCLK - bool "External RMII clock" - ---help--- - Clocking is provided by external logic. - -endchoice # RMII clock configuration - -config STM32H5_ETHMAC_REGDEBUG - bool "Register-Level Debug" - default n - depends on DEBUG_NET_INFO - ---help--- - Enable very low-level register access debug. Depends on - CONFIG_DEBUG_FEATURES. - -config STM32H5_NO_PHY - bool "MAC has no PHY" - default n - -endmenu # Ethernet MAC Configuration - -menu "FDCAN driver configuration" - depends on STM32H5_FDCAN - -choice - prompt "FDCAN character driver or SocketCAN support" - default STM32H5_FDCAN_CHARDRIVER - -config STM32H5_FDCAN_CHARDRIVER - bool "STM32 FDCAN character driver support" - select ARCH_HAVE_CAN_ERRORS - select CAN - -config STM32H5_FDCAN_SOCKET - bool "STM32 FDCAN SocketCAN support" - select NET_CAN_HAVE_ERRORS - select NET_CAN_HAVE_CANFD - -endchoice # FDCAN character driver or SocketCAN support - -config STM32H5_FDCAN_REGDEBUG - bool "CAN Register level debug" - depends on DEBUG_CAN_INFO - default n - ---help--- - Output detailed register-level CAN device debug information. - Requires also CONFIG_DEBUG_CAN_INFO. - -config STM32H5_FDCAN_QUEUE_MODE - bool "FDCAN QUEUE mode (vs FIFO mode)" - default n - -menu "FDCAN1 device driver options" - depends on STM32H5_FDCAN1 - -choice - prompt "FDCAN1 frame format" - default STM32H5_FDCAN1_ISO11898_1 - -config STM32H5_FDCAN1_ISO11898_1 - bool "ISO11898-1" - ---help--- - Enable ISO11898-1 frame format - -config STM32H5_FDCAN1_NONISO_FORMAT - bool "Non ISO" - ---help--- - Enable Non ISO, Bosch CAN FD Specification V1.0 - -endchoice # FDCAN1 frame format - -choice - prompt "FDCAN1 mode" - default STM32H5_FDCAN1_CLASSIC - -config STM32H5_FDCAN1_CLASSIC - bool "Classic CAN" - ---help--- - Enable Classic CAN mode - -config STM32H5_FDCAN1_FD - bool "CAN FD" - depends on CAN_FD || NET_CAN_CANFD - ---help--- - Enable CAN FD mode - -config STM32H5_FDCAN1_FD_BRS - bool "CAN FD with fast bit rate switching" - depends on CAN_FD || NET_CAN_CANFD - ---help--- - Enable CAN FD mode with fast bit rate switching mode. - -endchoice # FDCAN1 mode - -menu "FDCAN1 Bit Timing" - -config STM32H5_FDCAN1_AUTO_BIT_TIMING - bool "FDCAN1 Automatic Bit Timing" - default y - ---help--- - Automatically determine FDCAN1 bit timing (nominal and data) based on bitrate. - -comment "Nominal Bit Timing" - -config STM32H5_FDCAN1_BITRATE - int "FDCAN bitrate" - default 500000 - range 0 1000000 - ---help--- - FDCAN1 bitrate in bits per second. Required if STM32H5_FDCAN1 is defined. - -config STM32H5_FDCAN1_NTSEG1 - int "FDCAN1 NTSEG1 (PropSeg + PhaseSeg1)" - default 6 - range 1 256 - depends on !STM32H5_FDCAN1_AUTO_BIT_TIMING - ---help--- - The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). - -config STM32H5_FDCAN1_NTSEG2 - int "FDCAN1 NTSEG2 (PhaseSeg2)" - default 7 - range 1 128 - depends on !STM32H5_FDCAN1_AUTO_BIT_TIMING - ---help--- - The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). - -config STM32H5_FDCAN1_NSJW - int "FDCAN1 synchronization jump width" - default 1 - range 1 128 - depends on !STM32H5_FDCAN1_AUTO_BIT_TIMING - ---help--- - The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). - -comment "Data Bit Timing" - depends on CAN_FD && STM32H5_FDCAN1_FD_BRS - -config STM32H5_FDCAN1_DBITRATE - int "FDCAN1 data bitrate" - default 2000000 - depends on CAN_FD && STM32H5_FDCAN1_FD_BRS - ---help--- - FDCAN1 bitrate in bits per second. Required if operating in FD mode with bit rate switching (BRS). - -config STM32H5_FDCAN1_DTSEG1 - int "FDCAN1 DTSEG1 (PropSeg + PhaseSeg1 of data phase)" - default 4 - range 1 31 - depends on CAN_FD && STM32H5_FDCAN1_FD_BRS && !STM32H5_FDCAN1_AUTO_BIT_TIMING - ---help--- - The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). - -config STM32H5_FDCAN1_DTSEG2 - int "FDCAN1 DTSEG2 (PhaseSeg2 of data phase)" - default 4 - range 1 15 - depends on CAN_FD && STM32H5_FDCAN1_FD_BRS && !STM32H5_FDCAN1_AUTO_BIT_TIMING - ---help--- - The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). - -config STM32H5_FDCAN1_DSJW - int "FDCAN1 fast synchronization jump width" - default 2 - range 1 15 - depends on CAN_FD && STM32H5_FDCAN1_FD_BRS && !STM32H5_FDCAN1_AUTO_BIT_TIMING - ---help--- - The duration of a synchronization jump is Tcan_clk x DSJW. - -endmenu # FDCAN1 Bit Timing - -config STM32H5_FDCAN1_LOOPBACK - bool "Enable FDCAN1 loopback mode" - default n - ---help--- - Enable the FDCAN1 local loopback mode for testing purposes. - -endmenu # FDCAN1 device driver options - -menu "FDCAN2 device driver options" - depends on STM32H5_FDCAN2 - -choice - prompt "FDCAN2 frame format" - default STM32H5_FDCAN2_ISO11898_1 - -config STM32H5_FDCAN2_ISO11898_1 - bool "ISO11898-1" - ---help--- - Enable ISO11898-1 frame format - -config STM32H5_FDCAN2_NONISO_FORMAT - bool "Non ISO" - ---help--- - Enable Non ISO, Bosch CAN FD Specification V1.0 - -endchoice # FDCAN2 frame format - -choice - prompt "FDCAN2 mode" - default STM32H5_FDCAN2_CLASSIC - -config STM32H5_FDCAN2_CLASSIC - bool "Classic CAN" - ---help--- - Enable Classic CAN mode - -config STM32H5_FDCAN2_FD - bool "CAN FD" - depends on CAN_FD || NET_CAN_CANFD - ---help--- - Enable CAN FD mode - -config STM32H5_FDCAN2_FD_BRS - bool "CAN FD with fast bit rate switching" - depends on CAN_FD || NET_CAN_CANFD - ---help--- - Enable CAN FD mode with fast bit rate switching mode. - -endchoice # FDCAN2 mode - -menu "FDCAN2 Bit Timing" - -config STM32H5_FDCAN2_AUTO_BIT_TIMING - bool "FDCAN2 Automatic Bit Timing" - default y - ---help--- - Automatically determine FDCAN2 bit timing (nominal and data) based on bitrate. - -comment "Nominal Bit Timing" - -config STM32H5_FDCAN2_BITRATE - int "FDCAN bitrate" - default 500000 - range 0 1000000 - ---help--- - FDCAN2 bitrate in bits per second. Required if STM32H5_FDCAN2 is defined. - -config STM32H5_FDCAN2_NTSEG1 - int "FDCAN2 NTSEG1 (PropSeg + PhaseSeg1)" - default 6 - range 1 256 - depends on !STM32H5_FDCAN2_AUTO_BIT_TIMING - ---help--- - The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). - -config STM32H5_FDCAN2_NTSEG2 - int "FDCAN2 NTSEG2 (PhaseSeg2)" - default 7 - range 1 128 - depends on !STM32H5_FDCAN2_AUTO_BIT_TIMING - ---help--- - The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). - -config STM32H5_FDCAN2_NSJW - int "FDCAN2 synchronization jump width" - default 1 - range 1 128 - depends on !STM32H5_FDCAN2_AUTO_BIT_TIMING - ---help--- - The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). - -comment "Data Bit Timing" - depends on CAN_FD && STM32H5_FDCAN2_FD_BRS - -config STM32H5_FDCAN2_DBITRATE - int "FDCAN2 data bitrate" - default 2000000 - depends on CAN_FD && STM32H5_FDCAN2_FD_BRS - ---help--- - FDCAN2 bitrate in bits per second. Required if operating in FD mode with bit rate switching (BRS). - -config STM32H5_FDCAN2_DTSEG1 - int "FDCAN2 DTSEG1 (PropSeg + PhaseSeg1 of data phase)" - default 4 - range 1 31 - depends on CAN_FD && STM32H5_FDCAN2_FD_BRS && !STM32H5_FDCAN2_AUTO_BIT_TIMING - ---help--- - The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). - -config STM32H5_FDCAN2_DTSEG2 - int "FDCAN2 DTSEG2 (PhaseSeg2 of data phase)" - default 4 - range 1 15 - depends on CAN_FD && STM32H5_FDCAN2_FD_BRS && !STM32H5_FDCAN2_AUTO_BIT_TIMING - ---help--- - The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). - -config STM32H5_FDCAN2_DSJW - int "FDCAN2 fast synchronization jump width" - default 2 - range 1 15 - depends on CAN_FD && STM32H5_FDCAN2_FD_BRS && !STM32H5_FDCAN2_AUTO_BIT_TIMING - ---help--- - The duration of a synchronization jump is Tcan_clk x DSJW. - -endmenu # FDCAN2 Bit Timing - -config STM32H5_FDCAN2_LOOPBACK - bool "Enable FDCAN2 loopback mode" - default n - ---help--- - Enable the FDCAN2 local loopback mode for testing purposes. - -endmenu # FDCAN2 device driver options - -endmenu # "FDCAN driver configuration" - -menu "I2C Configuration" - depends on STM32H5_I2C - -menu "Clock Selection" - -choice - depends on STM32H5_I2C1 - prompt "I2C1 Input Clock Selection" - default STM32H5_I2C1_CLK_PCLK1 - -config STM32H5_I2C1_CLK_CSI - bool "CSI" - -config STM32H5_I2C1_CLK_HSI - bool "HSI" - -config STM32H5_I2C1_CLK_PCLK1 - bool "PCLK1" - -config STM32H5_I2C1_CLK_PLL3R - bool "PLL3R" - -endchoice # I2C1 Input Clock Selection - -choice - depends on STM32H5_I2C2 - prompt "I2C2 Input Clock Selection" - default STM32H5_I2C2_CLK_PCLK1 - -config STM32H5_I2C2_CLK_CSI - bool "CSI" - -config STM32H5_I2C2_CLK_HSI - bool "HSI" - -config STM32H5_I2C2_CLK_PCLK1 - bool "PCLK1" - -config STM32H5_I2C2_CLK_PLL3R - bool "PLL3R" - -endchoice # I2C2 Input Clock Selection - -choice - depends on STM32H5_I2C3 - prompt "I2C3 Input Clock Selection" - default STM32H5_I2C3_CLK_PCLK3 - -config STM32H5_I2C3_CLK_CSI - bool "CSI" - -config STM32H5_I2C3_CLK_HSI - bool "HSI" - -config STM32H5_I2C3_CLK_PCLK3 - bool "PCLK3" - -config STM32H5_I2C3_CLK_PLL3R - bool "PLL3R" - -endchoice # I2C3 Input Clock Selection - -choice - depends on STM32H5_I2C4 - prompt "I2C4 Input Clock Selection" - default STM32H5_I2C4_CLK_PCLK3 - -config STM32H5_I2C4_CLK_CSI - bool "CSI" - -config STM32H5_I2C4_CLK_HSI - bool "HSI" - -config STM32H5_I2C4_CLK_PCLK3 - bool "PCLK3" - -config STM32H5_I2C4_CLK_PLL3R - bool "PLL3R" - -endchoice # I2C4 Input Clock Selection - -endmenu # Clock Selection - -menu "Rise/Fall Override" - -config STM32H5_I2C1_RF_OVERRIDE - bool "I2C1" - default n - depends on STM32H5_I2C1 - -config STM32H5_I2C2_RF_OVERRIDE - bool "I2C2" - default n - depends on STM32H5_I2C2 - -config STM32H5_I2C3_RF_OVERRIDE - bool "I2C3" - default n - depends on STM32H5_I2C3 - -config STM32H5_I2C4_RF_OVERRIDE - bool "I2C4" - default n - depends on STM32H5_I2C4 - -menu "Rise/Fall Values" - -config STM32H5_I2C1_RISE - int "I2C1 Rise Time (ns)" - range 0 1000 - default 20 - depends on STM32H5_I2C1_RF_OVERRIDE - -config STM32H5_I2C1_FALL - int "I2C1 Fall Time (ns)" - range 0 300 - default 20 - depends on STM32H5_I2C1_RF_OVERRIDE - -config STM32H5_I2C2_RISE - int "I2C2 Rise Time (ns)" - range 0 1000 - default 20 - depends on STM32H5_I2C2_RF_OVERRIDE - -config STM32H5_I2C2_FALL - int "I2C2 Fall Time (ns)" - range 0 300 - default 20 - depends on STM32H5_I2C2_RF_OVERRIDE - -config STM32H5_I2C3_RISE - int "I2C3 Rise Time (ns)" - range 0 1000 - default 20 - depends on STM32H5_I2C3_RF_OVERRIDE - -config STM32H5_I2C3_FALL - int "I2C3 Fall Time (ns)" - range 0 300 - default 20 - depends on STM32H5_I2C3_RF_OVERRIDE - -config STM32H5_I2C4_RISE - int "I2C4 Rise Time (ns)" - range 0 1000 - default 20 - depends on STM32H5_I2C4_RF_OVERRIDE - -config STM32H5_I2C4_FALL - int "I2C4 Fall Time (ns)" - range 0 300 - default 20 - depends on STM32H5_I2C4_RF_OVERRIDE - -endmenu # Rise/Fall Values - -endmenu # Rise/Fall Override - -menu "Filtering" - -menu "Digital Filters" - -config STM32H5_I2C1_DNF - int "I2C1 Digital Noise Filter" - range 0 15 - default 0 - depends on STM32H5_I2C1 - -config STM32H5_I2C2_DNF - int "I2C2 Digital Noise Filter" - range 0 15 - default 0 - depends on STM32H5_I2C2 - -config STM32H5_I2C3_DNF - int "I2C3 Digital Noise Filter" - range 0 15 - default 0 - depends on STM32H5_I2C3 - -config STM32H5_I2C4_DNF - int "I2C4 Digital Noise Filter" - range 0 15 - default 0 - depends on STM32H5_I2C4 - -endmenu # Digital Filters - -menu "Analog Filters" - -config STM32H5_I2C1_ANFOFF - int "Turn off I2C1 Analog Filter (0=on, 1=off)" - default 1 - range 0 1 - depends on STM32H5_I2C1 - -config STM32H5_I2C2_ANFOFF - int "Turn off I2C2 Analog Filter (0=on, 1=off)" - default 1 - range 0 1 - depends on STM32H5_I2C2 - -config STM32H5_I2C3_ANFOFF - int "Turn off I2C3 Analog Filter (0=on, 1=off)" - default 1 - range 0 1 - depends on STM32H5_I2C3 - -config STM32H5_I2C4_ANFOFF - int "Turn off I2C4 Analog Filter (0=on, 1=off)" - default 1 - range 0 1 - depends on STM32H5_I2C4 - -endmenu # Analog Filters - -endmenu # Filtering - -config STM32H5_I2C_DYNTIMEO - bool "Use dynamic timeouts" - default n - depends on STM32H5_I2C - -config STM32H5_I2C_DYNTIMEO_USECPERBYTE - int "Timeout Microseconds per Byte" - default 500 - depends on STM32H5_I2C_DYNTIMEO - -config STM32H5_I2C_DYNTIMEO_STARTSTOP - int "Timeout for Start/Stop (Milliseconds)" - default 1000 - depends on STM32H5_I2C_DYNTIMEO - -config STM32H5_I2CTIMEOSEC - int "Timeout seconds" - default 0 - depends on STM32H5_I2C - -config STM32H5_I2CTIMEOMS - int "Timeout Milliseconds" - default 500 - depends on STM32H5_I2C && !STM32H5_I2C_DYNTIMEO - -config STM32H5_I2CTIMEOTICKS - int "Timeout for Done and Stop (ticks)" - default 500 - depends on STM32H5_I2C && !STM32H5_I2C_DYNTIMEO - -endmenu # "I2C Configuration" - -menu "QuadSPI Configuration" - depends on STM32H5_QSPI1 - -config STM32H5_QSPI_FLASH_SIZE - int "Size of attached serial flash, bytes" - default 16777216 - range 1 2147483648 - ---help--- - The STM32H5 QSPI peripheral requires the size of the Flash be specified - -config STM32H5_QSPI_FIFO_THESHOLD - int "Number of bytes before asserting FIFO threshold flag" - default 4 - range 1 32 - ---help--- - The STM32H5 QSPI peripheral requires that the FIFO threshold be specified - I would leave it at the default value of 4 unless you know what you are doing. - -config STM32H5_QSPI_CSHT - int "Number of cycles Chip Select must be inactive between transactions" - default 5 - range 1 64 - ---help--- - The STM32H5 QSPI peripheral requires that it be specified the minimum number - of AHB cycles that Chip Select be held inactive between transactions. - -choice - prompt "Transfer technique" - default STM32H5_QSPI_DMA - ---help--- - You can choose between using polling, interrupts, or DMA to transfer data - over the QSPI interface. - -config STM32H5_QSPI_POLLING - bool "Polling" - ---help--- - Use conventional register I/O with status polling to transfer data. - -config STM32H5_QSPI_INTERRUPTS - bool "Interrupts" - ---help--- - User interrupt driven I/O transfers. - -config STM32H5_QSPI_DMA - bool "DMA" - depends on STM32H5_DMA - ---help--- - Use DMA to improve QSPI transfer performance. - -endchoice - -choice - prompt "Bank selection" - default STM32H5_QSPI_MODE_BANK1 - ---help--- - You can choose between using polling, interrupts, or DMA to transfer data - over the QSPI interface. - -config STM32H5_QSPI_MODE_BANK1 - bool "Bank 1" - -config STM32H5_QSPI_MODE_BANK2 - bool "Bank 2" - -config STM32H5_QSPI_MODE_DUAL - bool "Dual Bank" - -endchoice - -choice - prompt "DMA Priority" - default STM32H5_QSPI_DMAPRIORITY_MEDIUM - depends on STM32H5_DMA - ---help--- - The DMA controller supports priority levels. You are probably fine - with the default of 'medium' except for special cases. In the event - of contention between to channels at the same priority, the lower - numbered channel has hardware priority over the higher numbered one. - -config STM32H5_QSPI_DMAPRIORITY_VERYHIGH - bool "Very High priority" - depends on STM32H5_DMA - ---help--- - 'Highest' priority. - -config STM32H5_QSPI_DMAPRIORITY_HIGH - bool "High priority" - depends on STM32H5_DMA - ---help--- - 'High' priority. - -config STM32H5_QSPI_DMAPRIORITY_MEDIUM - bool "Medium priority" - depends on STM32H5_DMA - ---help--- - 'Medium' priority. - -config STM32H5_QSPI_DMAPRIORITY_LOW - bool "Low priority" - depends on STM32H5_DMA - ---help--- - 'Low' priority. - -endchoice - -config STM32H5_QSPI_DMATHRESHOLD - int "QSPI DMA threshold" - default 4 - depends on STM32H5_QSPI_DMA - ---help--- - When QSPI DMA is enabled, small DMA transfers will still be performed - by polling logic. This value is the threshold below which transfers - will still be performed by conventional register status polling. - -config STM32H5_QSPI_DMADEBUG - bool "QSPI DMA transfer debug" - depends on STM32H5_QSPI_DMA && DEBUG_SPI && DEBUG_DMA - default n - ---help--- - Enable special debug instrumentation to analyze QSPI DMA data transfers. - This logic is as non-invasive as possible: It samples DMA - registers at key points in the data transfer and then dumps all of - the registers at the end of the transfer. - -config STM32H5_QSPI_REGDEBUG - bool "QSPI Register level debug" - depends on DEBUG_SPI_INFO - default n - ---help--- - Output detailed register-level QSPI device debug information. - Requires also CONFIG_DEBUG_SPI_INFO. - -endmenu - endif # ARCH_CHIP_STM32H5 diff --git a/arch/arm/src/stm32h5/Make.defs b/arch/arm/src/stm32h5/Make.defs index ca7e9a796197c..ec8db4beccfab 100644 --- a/arch/arm/src/stm32h5/Make.defs +++ b/arch/arm/src/stm32h5/Make.defs @@ -28,8 +28,9 @@ HEAD_ASRC = # Common ARM and Cortex-M33 files include armv8-m/Make.defs +include common/stm32/Make.defs -ifeq ($(CONFIG_STM32H5_PROGMEM),y) +ifeq ($(CONFIG_STM32_PROGMEM),y) CHIP_CSRCS += stm32_flash.c endif @@ -38,13 +39,12 @@ endif CHIP_CSRCS += stm32_gpio.c stm32_irq.c stm32_lowputc.c stm32_rcc.c CHIP_CSRCS += stm32_start.c stm32_pwr.c stm32_timerisr.c CHIP_CSRCS += stm32_lse.c stm32_lsi.c -CHIP_CSRCS += stm32_uid.c ifneq ($(CONFIG_ARCH_IDLE_CUSTOM),y) CHIP_CSRCS += stm32_idle.c endif -ifeq ($(CONFIG_STM32H5_USART),y) +ifeq ($(CONFIG_STM32_USART),y) CHIP_CSRCS += stm32_serial.c endif @@ -52,7 +52,7 @@ ifeq ($(CONFIG_TIMER),y) CHIP_CSRCS += stm32_tim_lowerhalf.c endif -ifeq ($(CONFIG_STM32H5_I2C),y) +ifeq ($(CONFIG_STM32_I2C),y) CHIP_CSRCS += stm32_i2c.c endif @@ -60,64 +60,64 @@ ifeq ($(CONFIG_ADC),y) CHIP_CSRCS += stm32_adc.c endif -ifeq ($(CONFIG_STM32H5_FDCAN_CHARDRIVER),y) +ifeq ($(CONFIG_STM32_FDCAN_CHARDRIVER),y) CHIP_CSRCS += stm32_fdcan.c endif -ifeq ($(CONFIG_STM32H5_RNG),y) +ifeq ($(CONFIG_STM32_RNG),y) CHIP_CSRCS += stm32_rng.c endif -ifeq ($(CONFIG_STM32H5_ICACHE),y) +ifeq ($(CONFIG_STM32_ICACHE),y) CHIP_CSRCS += stm32_icache.c endif -ifeq ($(CONFIG_STM32H5_SPI),y) +ifeq ($(CONFIG_STM32_SPI),y) CHIP_CSRCS += stm32_spi.c endif -ifeq ($(CONFIG_STM32H5_QSPI1),y) +ifeq ($(CONFIG_STM32_QSPI1),y) CHIP_CSRCS += stm32_qspi.c endif -ifeq ($(CONFIG_STM32H5_TIM),y) +ifeq ($(CONFIG_STM32_TIM),y) CHIP_CSRCS += stm32_tim.c endif -ifeq ($(CONFIG_STM32H5_HAVE_HSI48),y) +ifeq ($(CONFIG_STM32_HAVE_HSI48),y) CHIP_CSRCS += stm32_hsi48.c endif -ifeq ($(CONFIG_STM32H5_USBFS),y) +ifeq ($(CONFIG_STM32_USBFS),y) CHIP_CSRCS += stm32_usbfs.c endif -ifeq ($(CONFIG_STM32H5_USBFS_HOST),y) +ifeq ($(CONFIG_STM32_USBFS_HOST),y) CHIP_CSRCS += stm32_usbdrdhost.c endif -ifeq ($(CONFIG_STM32H5_ETHMAC),y) +ifeq ($(CONFIG_STM32_ETHMAC),y) CHIP_CSRCS += stm32_ethernet.c endif -ifeq ($(CONFIG_STM32H5_DMA),y) +ifeq ($(CONFIG_STM32_DMA),y) CHIP_CSRCS += stm32_dma.c endif -ifeq ($(CONFIG_STM32H5_DTS),y) +ifeq ($(CONFIG_STM32_DTS),y) CHIP_CSRCS += stm32_dts.c endif -ifeq ($(CONFIG_STM32H5_PWM),y) +ifeq ($(CONFIG_STM32_PWM),y) CHIP_CSRCS += stm32_pwm.c endif -ifeq ($(CONFIG_STM32H5_PULSECOUNT),y) +ifeq ($(CONFIG_STM32_PULSECOUNT),y) CHIP_CSRCS += stm32_pulsecount.c endif # Required chip type specific files -ifeq ($(CONFIG_STM32H5_STM32H5XXXX),y) +ifeq ($(CONFIG_STM32_STM32H5XXXX),y) CHIP_CSRCS += stm32h5xx_rcc.c endif diff --git a/arch/arm/src/stm32h5/hardware/stm32_ethernet.h b/arch/arm/src/stm32h5/hardware/stm32_ethernet.h index 420f624695c7f..b328ec952ce3d 100644 --- a/arch/arm/src/stm32h5/hardware/stm32_ethernet.h +++ b/arch/arm/src/stm32h5/hardware/stm32_ethernet.h @@ -33,7 +33,7 @@ /* Ethernet support only on STM32H563/573 chips. */ -#if defined(CONFIG_STM32H5_STM32H56XXX) +#if defined(CONFIG_STM32_STM32H56XXX) /**************************************************************************** * Pre-processor Definitions @@ -681,5 +681,5 @@ struct eth_desc_s ****************************************************************************/ #endif /* __ASSEMBLY__ */ -#endif /* CONFIG_STM32H5_STM32H56XXX */ +#endif /* CONFIG_STM32_STM32H56XXX */ #endif /* __ARCH_ARM_SRC_STM32H5_HARDWARE_STM32_ETHERNET_H */ \ No newline at end of file diff --git a/arch/arm/src/stm32h5/hardware/stm32_flash.h b/arch/arm/src/stm32h5/hardware/stm32_flash.h index f49c7d02d958f..417c6fdabee2e 100644 --- a/arch/arm/src/stm32h5/hardware/stm32_flash.h +++ b/arch/arm/src/stm32h5/hardware/stm32_flash.h @@ -30,7 +30,7 @@ #include #include "chip.h" -#if defined(CONFIG_STM32H5_STM32H56XXX) +#if defined(CONFIG_STM32_STM32H56XXX) # include "hardware/stm32h5xxx_flash.h" #else # error "Unsupported STM32 H5 flash" diff --git a/arch/arm/src/stm32h5/hardware/stm32_gpdma.h b/arch/arm/src/stm32h5/hardware/stm32_gpdma.h index 47125c3173df4..997c2180495ec 100644 --- a/arch/arm/src/stm32h5/hardware/stm32_gpdma.h +++ b/arch/arm/src/stm32h5/hardware/stm32_gpdma.h @@ -30,7 +30,7 @@ #include #include "chip.h" -#if defined(CONFIG_STM32H5_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX) +#if defined(CONFIG_STM32_STM32H56XXX) || defined(CONFIG_STM32_STM32H57XXX) # include "stm32h56x_dmasigmap.h" #else # error "Unsupported STM32 H5 DMA map" diff --git a/arch/arm/src/stm32h5/hardware/stm32_gpio.h b/arch/arm/src/stm32h5/hardware/stm32_gpio.h index 0218cb504299a..8ff9b98ab8407 100644 --- a/arch/arm/src/stm32h5/hardware/stm32_gpio.h +++ b/arch/arm/src/stm32h5/hardware/stm32_gpio.h @@ -30,8 +30,8 @@ #include #include "chip.h" -#if defined(CONFIG_STM32H5_STM32H52XXX) || defined(CONFIG_STM32H5_STM32H53XXX) || \ - defined(CONFIG_STM32H5_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX) +#if defined(CONFIG_STM32_STM32H52XXX) || defined(CONFIG_STM32_STM32H53XXX) || \ + defined(CONFIG_STM32_STM32H56XXX) || defined(CONFIG_STM32_STM32H57XXX) # include "hardware/stm32h5xxx_gpio.h" #else # error "Unsupported STM32 H5 PWR" diff --git a/arch/arm/src/stm32h5/hardware/stm32_i2c.h b/arch/arm/src/stm32h5/hardware/stm32_i2c.h index 0969c2732df79..d564ba5f1ec04 100644 --- a/arch/arm/src/stm32h5/hardware/stm32_i2c.h +++ b/arch/arm/src/stm32h5/hardware/stm32_i2c.h @@ -30,8 +30,8 @@ #include #include "chip.h" -#if defined(CONFIG_STM32H5_STM32H52XXX) || defined(CONFIG_STM32H5_STM32H53XXX) || \ - defined(CONFIG_STM32H5_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX) +#if defined(CONFIG_STM32_STM32H52XXX) || defined(CONFIG_STM32_STM32H53XXX) || \ + defined(CONFIG_STM32_STM32H56XXX) || defined(CONFIG_STM32_STM32H57XXX) # include "hardware/stm32h5xxx_i2c.h" #else # error "Unsupported STM32 H5 I2C" diff --git a/arch/arm/src/stm32h5/hardware/stm32_memorymap.h b/arch/arm/src/stm32h5/hardware/stm32_memorymap.h index 2900aff29cc13..ff9b80be0fe14 100644 --- a/arch/arm/src/stm32h5/hardware/stm32_memorymap.h +++ b/arch/arm/src/stm32h5/hardware/stm32_memorymap.h @@ -30,8 +30,8 @@ #include #include "chip.h" -#if defined(CONFIG_STM32H5_STM32H52XXX) || defined(CONFIG_STM32H5_STM32H53XXX) || \ - defined(CONFIG_STM32H5_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX) +#if defined(CONFIG_STM32_STM32H52XXX) || defined(CONFIG_STM32_STM32H53XXX) || \ + defined(CONFIG_STM32_STM32H56XXX) || defined(CONFIG_STM32_STM32H57XXX) # include "hardware/stm32h5xxx_memorymap.h" #else # error "Unsupported STM32 H5 memory map" diff --git a/arch/arm/src/stm32h5/hardware/stm32_pinmap.h b/arch/arm/src/stm32h5/hardware/stm32_pinmap.h index 40b57ccf9e52f..555cf41bd49e4 100644 --- a/arch/arm/src/stm32h5/hardware/stm32_pinmap.h +++ b/arch/arm/src/stm32h5/hardware/stm32_pinmap.h @@ -30,7 +30,7 @@ #include #include "chip.h" -#if defined(CONFIG_STM32H5_STM32H56XXX) +#if defined(CONFIG_STM32_STM32H56XXX) # include "hardware/stm32h56xxx_pinmap.h" #else # error "Unsupported STM32 H5 pin map" diff --git a/arch/arm/src/stm32h5/hardware/stm32_pwr.h b/arch/arm/src/stm32h5/hardware/stm32_pwr.h index 1d4ec6386977c..24cddd0b400e6 100644 --- a/arch/arm/src/stm32h5/hardware/stm32_pwr.h +++ b/arch/arm/src/stm32h5/hardware/stm32_pwr.h @@ -30,8 +30,8 @@ #include #include "chip.h" -#if defined(CONFIG_STM32H5_STM32H52XXX) || defined(CONFIG_STM32H5_STM32H53XXX) || \ - defined(CONFIG_STM32H5_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX) +#if defined(CONFIG_STM32_STM32H52XXX) || defined(CONFIG_STM32_STM32H53XXX) || \ + defined(CONFIG_STM32_STM32H56XXX) || defined(CONFIG_STM32_STM32H57XXX) # include "hardware/stm32h5xxx_pwr.h" #else # error "Unsupported STM32 H5 PWR" diff --git a/arch/arm/src/stm32h5/hardware/stm32_qspi.h b/arch/arm/src/stm32h5/hardware/stm32_qspi.h index bda49dd568b11..e4ea385ead69e 100644 --- a/arch/arm/src/stm32h5/hardware/stm32_qspi.h +++ b/arch/arm/src/stm32h5/hardware/stm32_qspi.h @@ -36,8 +36,8 @@ /* General Characteristics **************************************************/ -#define STM32H5_QSPI_MINBITS 8 /* Minimum word width */ -#define STM32H5_QSPI_MAXBITS 32 /* Maximum word width */ +#define STM32_QSPI_MINBITS 8 /* Minimum word width */ +#define STM32_QSPI_MAXBITS 32 /* Maximum word width */ /* QSPI register offsets ****************************************************/ diff --git a/arch/arm/src/stm32h5/hardware/stm32_rcc.h b/arch/arm/src/stm32h5/hardware/stm32_rcc.h index 239af8377fcaa..ecfa04f7d52db 100644 --- a/arch/arm/src/stm32h5/hardware/stm32_rcc.h +++ b/arch/arm/src/stm32h5/hardware/stm32_rcc.h @@ -30,8 +30,8 @@ #include #include "chip.h" -#if defined(CONFIG_STM32H5_STM32H52XXX) || defined(CONFIG_STM32H5_STM32H53XXX) || \ - defined(CONFIG_STM32H5_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX) +#if defined(CONFIG_STM32_STM32H52XXX) || defined(CONFIG_STM32_STM32H53XXX) || \ + defined(CONFIG_STM32_STM32H56XXX) || defined(CONFIG_STM32_STM32H57XXX) # include "hardware/stm32h5xxx_rcc.h" #else # error "Unsupported STM32 H5 rcc" diff --git a/arch/arm/src/stm32h5/hardware/stm32_sbs.h b/arch/arm/src/stm32h5/hardware/stm32_sbs.h index 7ea88c87705c8..06c8a9fb6cfb9 100644 --- a/arch/arm/src/stm32h5/hardware/stm32_sbs.h +++ b/arch/arm/src/stm32h5/hardware/stm32_sbs.h @@ -30,10 +30,10 @@ #include #include "chip.h" -#if !defined(CONFIG_STM32H5_STM32H52XXX) && \ - !defined(CONFIG_STM32H5_STM32H53XXX) && \ - !defined(CONFIG_STM32H5_STM32H56XXX) && \ - !defined(CONFIG_STM32H5_STM32H57XXX) +#if !defined(CONFIG_STM32_STM32H52XXX) && \ + !defined(CONFIG_STM32_STM32H53XXX) && \ + !defined(CONFIG_STM32_STM32H56XXX) && \ + !defined(CONFIG_STM32_STM32H57XXX) # warning "SBS not verified on STM32H50x variants." #endif diff --git a/arch/arm/src/stm32h5/hardware/stm32_uart.h b/arch/arm/src/stm32h5/hardware/stm32_uart.h index 9ee7d1e1379fe..1b974188d5d30 100644 --- a/arch/arm/src/stm32h5/hardware/stm32_uart.h +++ b/arch/arm/src/stm32h5/hardware/stm32_uart.h @@ -30,8 +30,8 @@ #include #include "chip.h" -#if defined(CONFIG_STM32H5_STM32H52XXX) || defined(CONFIG_STM32H5_STM32H53XXX) || \ - defined(CONFIG_STM32H5_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX) +#if defined(CONFIG_STM32_STM32H52XXX) || defined(CONFIG_STM32_STM32H53XXX) || \ + defined(CONFIG_STM32_STM32H56XXX) || defined(CONFIG_STM32_STM32H57XXX) # include "hardware/stm32h5xxx_uart.h" #else # error "Unsupported STM32 H5 uart" diff --git a/arch/arm/src/stm32h5/hardware/stm32_usbfs.h b/arch/arm/src/stm32h5/hardware/stm32_usbfs.h index 2f90303f54577..88bf401c4dc69 100644 --- a/arch/arm/src/stm32h5/hardware/stm32_usbfs.h +++ b/arch/arm/src/stm32h5/hardware/stm32_usbfs.h @@ -30,7 +30,7 @@ #include #include -#ifdef CONFIG_STM32H5_HAVE_USBFS +#ifdef CONFIG_STM32_HAVE_USBFS /**************************************************************************** * Pre-processor Definitions @@ -331,5 +331,5 @@ #define USB_COUNT_RX_SHIFT (16) /* Bits 25-16: Reception Byte Count */ #define USB_COUNT_RX_MASK (0x3ff << USB_COUNT_RX_SHIFT) -#endif /* CONFIG_STM32H5_HAVE_USBFS */ +#endif /* CONFIG_STM32_HAVE_USBFS */ #endif /* __ARCH_ARM_SRC_STM32H5_HARDWARE_STM32_USBFS_H */ diff --git a/arch/arm/src/stm32h5/hardware/stm32h56xxx_pinmap.h b/arch/arm/src/stm32h5/hardware/stm32h56xxx_pinmap.h index a388e2f69fdd0..57284c4e07cf8 100644 --- a/arch/arm/src/stm32h5/hardware/stm32h56xxx_pinmap.h +++ b/arch/arm/src/stm32h5/hardware/stm32h56xxx_pinmap.h @@ -29,8 +29,8 @@ #include -#if defined(CONFIG_STM32H5_STM32H563XX) || \ - defined(CONFIG_STM32H5_STM32H562XX) +#if defined(CONFIG_STM32_STM32H563XX) || \ + defined(CONFIG_STM32_STM32H562XX) /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ @@ -786,5 +786,5 @@ #define GPIO_ADC2_INN18_0 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN5) #define GPIO_ADC2_INP19_0 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN5) -#endif /* CONFIG_STM32H5_STM32H563XX*/ +#endif /* CONFIG_STM32_STM32H563XX*/ #endif /* __ARCH_ARM_SRC_STM32H5_HARDWARE_STM32H56XXX_PINMAP_H */ diff --git a/arch/arm/src/stm32h5/hardware/stm32h5xxx_flash.h b/arch/arm/src/stm32h5/hardware/stm32h5xxx_flash.h index 0b93384d725e3..78fffb5e695bb 100644 --- a/arch/arm/src/stm32h5/hardware/stm32h5xxx_flash.h +++ b/arch/arm/src/stm32h5/hardware/stm32h5xxx_flash.h @@ -481,12 +481,12 @@ #define FLASH_SECWM1R_CUR_SECWM1_STRT_SHIFT (0) #define FLASH_SECWM1R_CUR_SECWM1_END_SHIFT (16) -#if defined(CONFIG_STM32H5_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX) +#if defined(CONFIG_STM32_STM32H56XXX) || defined(CONFIG_STM32_STM32H57XXX) # define FLASH_SECWM1R_CUR_SECWM1_STRT_MASK (0x7f << FLASH_SECWM1R_CUR_SECWM1_STRT_SHIFT) # define FLASH_SECWM1R_CUR_SECWM1_END_MASK (0x7f << FLASH_SECWM1R_CUR_SECWM1_END_SHIFT) #endif -#if defined(CONFIG_STM32H5_STM32H52XXX) || defined(CONFIG_STM32H5_STM32H53XXX) +#if defined(CONFIG_STM32_STM32H52XXX) || defined(CONFIG_STM32_STM32H53XXX) # define FLASH_SECWM1R_CUR_SECWM1_STRT_MASK (0x1f << FLASH_SECWM1R_CUR_SECWM1_STRT_SHIFT) # define FLASH_SECWM1R_CUR_SECWM1_END_MASK (0x1f << FLASH_SECWM1R_CUR_SECWM1_END_SHIFT) #endif @@ -496,12 +496,12 @@ #define FLASH_SECWM1R_PRG_SECWM1_STRT_SHIFT (0) #define FLASH_SECWM1R_PRG_SECWM1_END_SHIFT (16) -#if defined(CONFIG_STM32H5_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX) +#if defined(CONFIG_STM32_STM32H56XXX) || defined(CONFIG_STM32_STM32H57XXX) # define FLASH_SECWM1R_PRG_SECWM1_STRT_MASK (0x7f << FLASH_SECWM1R_PRG_SECWM1_STRT_SHIFT) # define FLASH_SECWM1R_PRG_SECWM1_END_MASK (0x7f << FLASH_SECWM1R_PRG_SECWM1_END_SHIFT) #endif -#if defined(CONFIG_STM32H5_STM32H52XXX) || defined(CONFIG_STM32H5_STM32H53XXX) +#if defined(CONFIG_STM32_STM32H52XXX) || defined(CONFIG_STM32_STM32H53XXX) # define FLASH_SECWM1R_PRG_SECWM1_STRT_MASK (0x1f << FLASH_SECWM1R_PRG_SECWM1_STRT_SHIFT) # define FLASH_SECWM1R_PRG_SECWM1_END_MASK (0x1f << FLASH_SECWM1R_PRG_SECWM1_END_SHIFT) #endif @@ -527,12 +527,12 @@ #define FLASH_HDP1R_CUR_HDP1_STRT_SHIFT (0) #define FLASH_HDP1R_CUR_HDP1_END_SHIFT (0) -#if defined(CONFIG_STM32H5_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX) +#if defined(CONFIG_STM32_STM32H56XXX) || defined(CONFIG_STM32_STM32H57XXX) # define FLASH_HDP1R_CUR_HDP1_STRT_MASK (0x7f << FLASH_HDP1R_PRG_HDP1_STRT_SHIFT) # define FLASH_HDP1R_CUR_HDP1_END_MASK (0x7f << FLASH_HDP1R_PRG_HDP1_END_SHIFT) #endif -#if defined(CONFIG_STM32H5_STM32H52XXX) || defined(CONFIG_STM32H5_STM32H53XXX) +#if defined(CONFIG_STM32_STM32H52XXX) || defined(CONFIG_STM32_STM32H53XXX) # define FLASH_HDP1R_CUR_HDP1_STRT_MASK (0x1f << FLASH_HDP1R_PRG_HDP1_STRT_SHIFT) # define FLASH_HDP1R_CUR_HDP1_END_MASK (0x1f << FLASH_HDP1R_PRG_HDP1_END_SHIFT) #endif @@ -542,12 +542,12 @@ #define FLASH_HDP1R_PRG_HDP1_STRT_SHIFT (0) #define FLASH_HDP1R_PRG_HDP1_END_SHIFT (0) -#if defined(CONFIG_STM32H5_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX) +#if defined(CONFIG_STM32_STM32H56XXX) || defined(CONFIG_STM32_STM32H57XXX) # define FLASH_HDP1R_PRG_HDP1_STRT_MASK (0x7f << FLASH_HDP1R_PRG_HDP1_STRT_SHIFT) # define FLASH_HDP1R_PRG_HDP1_END_MASK (0x7f << FLASH_HDP1R_PRG_HDP1_END_SHIFT) #endif -#if defined(CONFIG_STM32H5_STM32H52XXX) || defined(CONFIG_STM32H5_STM32H53XXX) +#if defined(CONFIG_STM32_STM32H52XXX) || defined(CONFIG_STM32_STM32H53XXX) # define FLASH_HDP1R_PRG_HDP1_STRT_MASK (0x1f << FLASH_HDP1R_PRG_HDP1_STRT_SHIFT) # define FLASH_HDP1R_PRG_HDP1_END_MASK (0x1f << FLASH_HDP1R_PRG_HDP1_END_SHIFT) #endif @@ -587,12 +587,12 @@ #define FLASH_SECWM2R_PRG_SECWM2_STRT_SHIFT (0) #define FLASH_SECWM2R_PRG_SECWM2_END_SHIFT (16) -#if defined(CONFIG_STM32H5_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX) +#if defined(CONFIG_STM32_STM32H56XXX) || defined(CONFIG_STM32_STM32H57XXX) # define FLASH_SECWM2R_PRG_SECWM2_STRT_MASK (0x7f << FLASH_SECWM2R_PRG_SECWM2_STRT_SHIFT) # define FLASH_SECWM2R_PRG_SECWM2_END_MASK (0x7f << FLASH_SECWM2R_PRG_SECWM2_END_SHIFT) #endif -#if defined(CONFIG_STM32H5_STM32H52XXX) || defined(CONFIG_STM32H5_STM32H53XXX) +#if defined(CONFIG_STM32_STM32H52XXX) || defined(CONFIG_STM32_STM32H53XXX) # define FLASH_SECWM2R_PRG_SECWM2_STRT_MASK (0x1f << FLASH_SECWM2R_PRG_SECWM2_STRT_SHIFT) # define FLASH_SECWM2R_PRG_SECWM2_END_MASK (0x1f << FLASH_SECWM2R_PRG_SECWM2_END_SHIFT) #endif @@ -618,12 +618,12 @@ #define FLASH_HDP2R_CUR_HDP2_STRT_SHIFT (0) #define FLASH_HDP2R_CUR_HDP2_END_SHIFT (0) -#if defined(CONFIG_STM32H5_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX) +#if defined(CONFIG_STM32_STM32H56XXX) || defined(CONFIG_STM32_STM32H57XXX) # define FLASH_HDP2R_CUR_HDP2_STRT_MASK (0x7f << FLASH_HDP2R_PRG_HDP2_STRT_SHIFT) # define FLASH_HDP2R_CUR_HDP2_END_MASK (0x7f << FLASH_HDP2R_PRG_HDP2_END_SHIFT) #endif -#if defined(CONFIG_STM32H5_STM32H52XXX) || defined(CONFIG_STM32H5_STM32H53XXX) +#if defined(CONFIG_STM32_STM32H52XXX) || defined(CONFIG_STM32_STM32H53XXX) # define FLASH_HDP2R_CUR_HDP2_STRT_MASK (0x1f << FLASH_HDP2R_PRG_HDP2_STRT_SHIFT) # define FLASH_HDP2R_CUR_HDP2_END_MASK (0x1f << FLASH_HDP2R_PRG_HDP2_END_SHIFT) #endif @@ -633,12 +633,12 @@ #define FLASH_HDP2R_PRG_HDP2_STRT_SHIFT (0) #define FLASH_HDP2R_PRG_HDP2_END_SHIFT (0) -#if defined(CONFIG_STM32H5_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX) +#if defined(CONFIG_STM32_STM32H56XXX) || defined(CONFIG_STM32_STM32H57XXX) # define FLASH_HDP2R_PRG_HDP2_STRT_MASK (0x7f << FLASH_HDP2R_PRG_HDP2_STRT_SHIFT) # define FLASH_HDP2R_PRG_HDP2_END_MASK (0x7f << FLASH_HDP2R_PRG_HDP2_END_SHIFT) #endif -#if defined(CONFIG_STM32H5_STM32H52XXX) || defined(CONFIG_STM32H5_STM32H53XXX) +#if defined(CONFIG_STM32_STM32H52XXX) || defined(CONFIG_STM32_STM32H53XXX) # define FLASH_HDP2R_PRG_HDP2_STRT_MASK (0x1f << FLASH_HDP2R_PRG_HDP2_STRT_SHIFT) # define FLASH_HDP2R_PRG_HDP2_END_MASK (0x1f << FLASH_HDP2R_PRG_HDP2_END_SHIFT) #endif diff --git a/arch/arm/src/stm32h5/hardware/stm32h5xxx_gpio.h b/arch/arm/src/stm32h5/hardware/stm32h5xxx_gpio.h index 915d6b4d4b0a8..9718063e46175 100644 --- a/arch/arm/src/stm32h5/hardware/stm32h5xxx_gpio.h +++ b/arch/arm/src/stm32h5/hardware/stm32h5xxx_gpio.h @@ -53,7 +53,7 @@ /* Register Addresses *******************************************************/ -#if STM32H5_NPORTS > 0 +#if STM32_NPORTS > 0 # define STM32_GPIOA_MODER (STM32_GPIOA_BASE + STM32_GPIO_MODER_OFFSET) # define STM32_GPIOA_OTYPER (STM32_GPIOA_BASE + STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOA_OSPEED (STM32_GPIOA_BASE + STM32_GPIO_OSPEED_OFFSET) @@ -69,7 +69,7 @@ # define STM32_GPIOA_SECCFGR (STM32_GPIOA_BASE + STM32_GPIO_SECCFGR_OFFSET) #endif -#if STM32H5_NPORTS > 1 +#if STM32_NPORTS > 1 # define STM32_GPIOB_MODER (STM32_GPIOB_BASE + STM32_GPIO_MODER_OFFSET) # define STM32_GPIOB_OTYPER (STM32_GPIOB_BASE + STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOB_OSPEED (STM32_GPIOB_BASE + STM32_GPIO_OSPEED_OFFSET) @@ -85,7 +85,7 @@ # define STM32_GPIOB_SECCFGR (STM32_GPIOB_BASE + STM32_GPIO_SECCFGR_OFFSET) #endif -#if STM32H5_NPORTS > 2 +#if STM32_NPORTS > 2 # define STM32_GPIOC_MODER (STM32_GPIOC_BASE + STM32_GPIO_MODER_OFFSET) # define STM32_GPIOC_OTYPER (STM32_GPIOC_BASE + STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOC_OSPEED (STM32_GPIOC_BASE + STM32_GPIO_OSPEED_OFFSET) @@ -101,7 +101,7 @@ # define STM32_GPIOC_SECCFGR (STM32_GPIOC_BASE + STM32_GPIO_SECCFGR_OFFSET) #endif -#if STM32H5_NPORTS > 3 +#if STM32_NPORTS > 3 # define STM32_GPIOD_MODER (STM32_GPIOD_BASE + STM32_GPIO_MODER_OFFSET) # define STM32_GPIOD_OTYPER (STM32_GPIOD_BASE + STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOD_OSPEED (STM32_GPIOD_BASE + STM32_GPIO_OSPEED_OFFSET) @@ -117,7 +117,7 @@ # define STM32_GPIOD_SECCFGR (STM32_GPIOD_BASE + STM32_GPIO_SECCFGR_OFFSET) #endif -#if STM32H5_NPORTS > 4 +#if STM32_NPORTS > 4 # define STM32_GPIOE_MODER (STM32_GPIOE_BASE + STM32_GPIO_MODER_OFFSET) # define STM32_GPIOE_OTYPER (STM32_GPIOE_BASE + STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOE_OSPEED (STM32_GPIOE_BASE + STM32_GPIO_OSPEED_OFFSET) @@ -133,7 +133,7 @@ # define STM32_GPIOE_SECCFGR (STM32_GPIOE_BASE + STM32_GPIO_SECCFGR_OFFSET) #endif -#if STM32H5_NPORTS > 5 +#if STM32_NPORTS > 5 # define STM32_GPIOF_MODER (STM32_GPIOF_BASE + STM32_GPIO_MODER_OFFSET) # define STM32_GPIOF_OTYPER (STM32_GPIOF_BASE + STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOF_OSPEED (STM32_GPIOF_BASE + STM32_GPIO_OSPEED_OFFSET) @@ -149,7 +149,7 @@ # define STM32_GPIOF_SECCFGR (STM32_GPIOF_BASE + STM32_GPIO_SECCFGR_OFFSET) #endif -#if STM32H5_NPORTS > 6 +#if STM32_NPORTS > 6 # define STM32_GPIOG_MODER (STM32_GPIOG_BASE + STM32_GPIO_MODER_OFFSET) # define STM32_GPIOG_OTYPER (STM32_GPIOG_BASE + STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOG_OSPEED (STM32_GPIOG_BASE + STM32_GPIO_OSPEED_OFFSET) @@ -165,7 +165,7 @@ # define STM32_GPIOG_SECCFGR (STM32_GPIOG_BASE + STM32_GPIO_SECCFGR_OFFSET) #endif -#if STM32H5_NPORTS > 7 +#if STM32_NPORTS > 7 # define STM32_GPIOH_MODER (STM32_GPIOH_BASE + STM32_GPIO_MODER_OFFSET) # define STM32_GPIOH_OTYPER (STM32_GPIOH_BASE + STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOH_OSPEED (STM32_GPIOH_BASE + STM32_GPIO_OSPEED_OFFSET) @@ -181,7 +181,7 @@ # define STM32_GPIOH_SECCFGR (STM32_GPIOH_BASE + STM32_GPIO_SECCFGR_OFFSET) #endif -#if STM32H5_NPORTS > 8 +#if STM32_NPORTS > 8 # define STM32_GPIOI_MODER (STM32_GPIOI_BASE + STM32_GPIO_MODER_OFFSET) # define STM32_GPIOI_OTYPER (STM32_GPIOI_BASE + STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOI_OSPEED (STM32_GPIOI_BASE + STM32_GPIO_OSPEED_OFFSET) diff --git a/arch/arm/src/stm32h5/hardware/stm32h5xxx_i2c.h b/arch/arm/src/stm32h5/hardware/stm32h5xxx_i2c.h index eb36e1b58c56a..5b3adf5963e8e 100644 --- a/arch/arm/src/stm32h5/hardware/stm32h5xxx_i2c.h +++ b/arch/arm/src/stm32h5/hardware/stm32h5xxx_i2c.h @@ -43,7 +43,7 @@ /* Register Addresses *******************************************************/ -#if STM32H5_NI2C > 0 +#if STM32_NI2C > 0 # define STM32_I2C1_CR1 (STM32_I2C1_BASE+STM32_I2C_CR1_OFFSET) # define STM32_I2C1_CR2 (STM32_I2C1_BASE+STM32_I2C_CR2_OFFSET) # define STM32_I2C1_OAR1 (STM32_I2C1_BASE+STM32_I2C_OAR1_OFFSET) @@ -57,7 +57,7 @@ # define STM32_I2C1_TXDR (STM32_I2C1_BASE+STM32_I2C_TXDR_OFFSET) #endif -#if STM32H5_NI2C > 1 +#if STM32_NI2C > 1 # define STM32_I2C2_CR1 (STM32_I2C2_BASE+STM32_I2C_CR1_OFFSET) # define STM32_I2C2_CR2 (STM32_I2C2_BASE+STM32_I2C_CR2_OFFSET) # define STM32_I2C2_OAR1 (STM32_I2C2_BASE+STM32_I2C_OAR1_OFFSET) @@ -71,7 +71,7 @@ # define STM32_I2C2_TXDR (STM32_I2C2_BASE+STM32_I2C_TXDR_OFFSET) #endif -#if STM32H5_NI2C > 2 +#if STM32_NI2C > 2 # define STM32_I2C3_CR1 (STM32_I2C3_BASE+STM32_I2C_CR1_OFFSET) # define STM32_I2C3_CR2 (STM32_I2C3_BASE+STM32_I2C_CR2_OFFSET) # define STM32_I2C3_OAR1 (STM32_I2C3_BASE+STM32_I2C_OAR1_OFFSET) @@ -85,7 +85,7 @@ # define STM32_I2C3_TXDR (STM32_I2C3_BASE+STM32_I2C_TXDR_OFFSET) #endif -#if STM32H5_NI2C > 3 +#if STM32_NI2C > 3 # define STM32_I2C4_CR1 (STM32_I2C4_BASE+STM32_I2C_CR1_OFFSET) # define STM32_I2C4_CR2 (STM32_I2C4_BASE+STM32_I2C_CR2_OFFSET) # define STM32_I2C4_OAR1 (STM32_I2C4_BASE+STM32_I2C_OAR1_OFFSET) diff --git a/arch/arm/src/stm32h5/hardware/stm32h5xxx_pwr.h b/arch/arm/src/stm32h5/hardware/stm32h5xxx_pwr.h index 1329727d65df8..8c065d39c4bd5 100644 --- a/arch/arm/src/stm32h5/hardware/stm32h5xxx_pwr.h +++ b/arch/arm/src/stm32h5/hardware/stm32h5xxx_pwr.h @@ -93,13 +93,13 @@ #define PWR_PMCR_ETHERNETSO (1 << 16) /* Ethernet RAM shut-off in Stop Mode */ #define PWR_PMCR_SRAM3SO (1 << 23) /* AHB SRAM3 shut-off in Stop mode */ -#if defined(CONFIG_STM32H5_STM32H56X) || defined(CONFIG_STM32H5_STM32H7X) +#if defined(CONFIG_STM32_STM32H56X) || defined(CONFIG_STM32_STM32H7X) #define PWR_PMCR_SRAM2_16SO (1 << 24) /* AHB SRAM3 16-Kbyte shut-off in Stop mode **/ #define PWR_PMCR_SRAM2_48SO (1 << 25) /* AHB SRAM2 48-Kbyte shut-off in Stop mode **/ #define PWR_PMCR_SRAM1SO (1 << 26) /* AHB SRAM1 shut-off in Stop mode * */ -#elif defined(CONFIG_STM32H5_STM32H2X) || defined(CONFIG_STM32H5_STM32H3X) +#elif defined(CONFIG_STM32_STM32H2X) || defined(CONFIG_STM32_STM32H3X) #define PWR_PMCR_SRAM2_16LSO (1 << 24) /* AHB SRAM3 16-Kbyte Low shut-off in Stop mode **/ #define PWR_PMCR_SRAM2_16HSO (1 << 25) /* AHB SRAM3 16-Kbyte High shut-off in Stop mode **/ diff --git a/arch/arm/src/stm32h5/hardware/stm32h5xxx_rcc.h b/arch/arm/src/stm32h5/hardware/stm32h5xxx_rcc.h index df39354494518..3e025922ad4a9 100644 --- a/arch/arm/src/stm32h5/hardware/stm32h5xxx_rcc.h +++ b/arch/arm/src/stm32h5/hardware/stm32h5xxx_rcc.h @@ -29,7 +29,7 @@ #include -#if defined(CONFIG_STM32H5_STM32H5XXXX) +#if defined(CONFIG_STM32_STM32H5XXXX) /**************************************************************************** * Pre-processor Definitions @@ -1242,5 +1242,5 @@ #define RCC_PRIVCFGR_SPRIV (1 << 0) /* Secure functions privilege configuration */ #define RCC_PRIVCFGR_NSPRIV (1 << 1) /* Non-secure functions privilege configuration */ -#endif /* CONFIG_STM32H5_STM32H562XX */ +#endif /* CONFIG_STM32_STM32H562XX */ #endif /* __ARCH_ARM_SRC_STM32H5_HARDWARE_STM32H5XXX_RCC_H */ diff --git a/arch/arm/src/stm32h5/hardware/stm32h5xxx_spi.h b/arch/arm/src/stm32h5/hardware/stm32h5xxx_spi.h index 1ef4fae584542..14418be67370a 100644 --- a/arch/arm/src/stm32h5/hardware/stm32h5xxx_spi.h +++ b/arch/arm/src/stm32h5/hardware/stm32h5xxx_spi.h @@ -29,7 +29,7 @@ #include -#if defined(CONFIG_STM32H5_STM32H5XXXX) +#if defined(CONFIG_STM32_STM32H5XXXX) /**************************************************************************** * Pre-processor Definitions @@ -60,7 +60,7 @@ /* Register Addresses *******************************************************/ -#if STM32H5_NSPI > 0 +#if STM32_NSPI > 0 # define STM32_SPI1_CR1 (STM32_SPI1_BASE+STM32_SPI_CR1_OFFSET) # define STM32_SPI1_CR2 (STM32_SPI1_BASE+STM32_SPI_CR2_OFFSET) # define STM32_SPI1_CFG1 (STM32_SPI1_BASE+STM32_SPI_CFG1_OFFSET) @@ -77,7 +77,7 @@ # define STM32_SPI1_I2SCFGR (STM32_SPI1_BASE+STM32_SPI_I2SCFGR_OFFSET) #endif -#if STM32H5_NSPI > 1 +#if STM32_NSPI > 1 # define STM32_SPI2_CR1 (STM32_SPI2_BASE+STM32_SPI_CR1_OFFSET) # define STM32_SPI2_CR2 (STM32_SPI2_BASE+STM32_SPI_CR2_OFFSET) # define STM32_SPI2_CFG1 (STM32_SPI2_BASE+STM32_SPI_CFG1_OFFSET) @@ -94,7 +94,7 @@ # define STM32_SPI2_I2SCFGR (STM32_SPI2_BASE+STM32_SPI_I2SCFGR_OFFSET) #endif -#if STM32H5_NSPI > 2 +#if STM32_NSPI > 2 # define STM32_SPI3_CR1 (STM32_SPI3_BASE+STM32_SPI_CR1_OFFSET) # define STM32_SPI3_CR2 (STM32_SPI3_BASE+STM32_SPI_CR2_OFFSET) # define STM32_SPI3_CFG1 (STM32_SPI3_BASE+STM32_SPI_CFG1_OFFSET) @@ -111,7 +111,7 @@ # define STM32_SPI3_I2SCFGR (STM32_SPI3_BASE+STM32_SPI_I2SCFGR_OFFSET) #endif -#if STM32H5_NSPI > 3 +#if STM32_NSPI > 3 # define STM32_SPI4_CR1 (STM32_SPI4_BASE+STM32_SPI_CR1_OFFSET) # define STM32_SPI4_CR2 (STM32_SPI4_BASE+STM32_SPI_CR2_OFFSET) # define STM32_SPI4_CFG1 (STM32_SPI4_BASE+STM32_SPI_CFG1_OFFSET) @@ -128,7 +128,7 @@ # define STM32_SPI4_I2SCFGR (STM32_SPI4_BASE+STM32_SPI_I2SCFGR_OFFSET) #endif -#if STM32H5_NSPI > 4 +#if STM32_NSPI > 4 # define STM32_SPI5_CR1 (STM32_SPI5_BASE+STM32_SPI_CR1_OFFSET) # define STM32_SPI5_CR2 (STM32_SPI5_BASE+STM32_SPI_CR2_OFFSET) # define STM32_SPI5_CFG1 (STM32_SPI5_BASE+STM32_SPI_CFG1_OFFSET) @@ -145,7 +145,7 @@ # define STM32_SPI5_I2SCFGR (STM32_SPI5_BASE+STM32_SPI_I2SCFGR_OFFSET) #endif -#if STM32H5_NSPI > 5 +#if STM32_NSPI > 5 # define STM32_SPI6_CR1 (STM32_SPI6_BASE+STM32_SPI_CR1_OFFSET) # define STM32_SPI6_CR2 (STM32_SPI6_BASE+STM32_SPI_CR2_OFFSET) # define STM32_SPI6_CFG1 (STM32_SPI6_BASE+STM32_SPI_CFG1_OFFSET) @@ -489,5 +489,5 @@ #define SPI_I2SCFGR_ODD (1 << 24) /* Bit 24: Odd Factor for the Prescaler */ #define SPI_I2SCFGR_MCKOE (1 << 25) /* Bit 24: Master Clock Output Enable */ -#endif /* CONFIG_STM32H5_STM32H5XXX */ +#endif /* CONFIG_STM32_STM32H5XXX */ #endif /* __ARCH_ARM_SRC_STM32H5_HARDWARE_STM32H5XXX_SPI_H */ diff --git a/arch/arm/src/stm32h5/hardware/stm32h5xxx_uart.h b/arch/arm/src/stm32h5/hardware/stm32h5xxx_uart.h index 74d23099c033c..3e9cf17197605 100644 --- a/arch/arm/src/stm32h5/hardware/stm32h5xxx_uart.h +++ b/arch/arm/src/stm32h5/hardware/stm32h5xxx_uart.h @@ -52,7 +52,7 @@ /* Register Addresses *******************************************************/ -#if STM32H5_NLPUART > 0 +#if STM32_NLPUART > 0 # define STM32_LPUART1_CR1 (STM32_LPUART1_BASE + STM32_USART_CR1_OFFSET) # define STM32_LPUART1_CR2 (STM32_LPUART1_BASE + STM32_USART_CR2_OFFSET) # define STM32_LPUART1_CR3 (STM32_LPUART1_BASE + STM32_USART_CR3_OFFSET) @@ -67,7 +67,7 @@ # define STM32_LPUART1_PRESC (STM32_LPUART1_BASE + STM32_USART_PRESC_OFFSET) #endif -#if STM32H5_NUSART > 0 +#if STM32_NUSART > 0 # define STM32_USART1_CR1 (STM32_USART1_BASE + STM32_USART_CR1_OFFSET) # define STM32_USART1_CR2 (STM32_USART1_BASE + STM32_USART_CR2_OFFSET) # define STM32_USART1_CR3 (STM32_USART1_BASE + STM32_USART_CR3_OFFSET) @@ -82,7 +82,7 @@ # define STM32_USART1_PRESC (STM32_USART1_BASE + STM32_USART_PRESC_OFFSET) #endif -#if STM32H5_NUSART > 1 +#if STM32_NUSART > 1 # define STM32_USART2_CR1 (STM32_USART2_BASE + STM32_USART_CR1_OFFSET) # define STM32_USART2_CR2 (STM32_USART2_BASE + STM32_USART_CR2_OFFSET) # define STM32_USART2_CR3 (STM32_USART2_BASE + STM32_USART_CR3_OFFSET) @@ -97,7 +97,7 @@ # define STM32_USART2_PRESC (STM32_USART2_BASE + STM32_USART_PRESC_OFFSET) #endif -#if STM32H5_NUSART > 2 +#if STM32_NUSART > 2 # define STM32_USART3_CR1 (STM32_USART3_BASE + STM32_USART_CR1_OFFSET) # define STM32_USART3_CR2 (STM32_USART3_BASE + STM32_USART_CR2_OFFSET) # define STM32_USART3_CR3 (STM32_USART3_BASE + STM32_USART_CR3_OFFSET) @@ -112,7 +112,7 @@ # define STM32_USART3_PRESC (STM32_USART3_BASE + STM32_USART_PRESC_OFFSET) #endif -#if STM32H5_NUSART > 4 +#if STM32_NUSART > 4 # define STM32_USART6_CR1 (STM32_USART6_BASE + STM32_USART_CR1_OFFSET) # define STM32_USART6_CR2 (STM32_USART6_BASE + STM32_USART_CR2_OFFSET) # define STM32_USART6_CR3 (STM32_USART6_BASE + STM32_USART_CR3_OFFSET) @@ -127,7 +127,7 @@ # define STM32_USART6_PRESC (STM32_USART6_BASE + STM32_USART_PRESC_OFFSET) #endif -#if STM32H5_NUSART > 5 +#if STM32_NUSART > 5 # define STM32_USART10_CR1 (STM32_USART10_BASE + STM32_USART_CR1_OFFSET) # define STM32_USART10_CR2 (STM32_USART10_BASE + STM32_USART_CR2_OFFSET) # define STM32_USART10_CR3 (STM32_USART10_BASE + STM32_USART_CR3_OFFSET) @@ -142,7 +142,7 @@ # define STM32_USART10_PRESC (STM32_USART10_BASE + STM32_USART_PRESC_OFFSET) #endif -#if STM32H5_NUSART > 6 +#if STM32_NUSART > 6 # define STM32_USART11_CR1 (STM32_USART11_BASE + STM32_USART_CR1_OFFSET) # define STM32_USART11_CR2 (STM32_USART11_BASE + STM32_USART_CR2_OFFSET) # define STM32_USART11_CR3 (STM32_USART11_BASE + STM32_USART_CR3_OFFSET) @@ -157,7 +157,7 @@ # define STM32_USART11_PRESC (STM32_USART11_BASE + STM32_USART_PRESC_OFFSET) #endif -#if STM32H5_NUART > 0 +#if STM32_NUART > 0 # define STM32_UART4_CR1 (STM32_UART4_BASE + STM32_USART_CR1_OFFSET) # define STM32_UART4_CR2 (STM32_UART4_BASE + STM32_USART_CR2_OFFSET) # define STM32_UART4_CR3 (STM32_UART4_BASE + STM32_USART_CR3_OFFSET) @@ -172,7 +172,7 @@ # define STM32_UART4_PRESC (STM32_UART4_BASE + STM32_USART_PRESC_OFFSET) #endif -#if STM32H5_NUART > 1 +#if STM32_NUART > 1 # define STM32_UART5_CR1 (STM32_UART5_BASE + STM32_USART_CR1_OFFSET) # define STM32_UART5_CR2 (STM32_UART5_BASE + STM32_USART_CR2_OFFSET) # define STM32_UART5_CR3 (STM32_UART5_BASE + STM32_USART_CR3_OFFSET) @@ -187,7 +187,7 @@ # define STM32_UART5_PRESC (STM32_UART5_BASE + STM32_USART_PRESC_OFFSET) #endif -#if STM32H5_NUART > 2 +#if STM32_NUART > 2 # define STM32_UART7_CR1 (STM32_UART7_BASE + STM32_USART_CR1_OFFSET) # define STM32_UART7_CR2 (STM32_UART7_BASE + STM32_USART_CR2_OFFSET) # define STM32_UART7_CR3 (STM32_UART7_BASE + STM32_USART_CR3_OFFSET) @@ -202,7 +202,7 @@ # define STM32_UART7_PRESC (STM32_UART7_BASE + STM32_USART_PRESC_OFFSET) #endif -#if STM32H5_NUART > 3 +#if STM32_NUART > 3 # define STM32_UART8_CR1 (STM32_UART8_BASE + STM32_USART_CR1_OFFSET) # define STM32_UART8_CR2 (STM32_UART8_BASE + STM32_USART_CR2_OFFSET) # define STM32_UART8_CR3 (STM32_UART8_BASE + STM32_USART_CR3_OFFSET) @@ -217,7 +217,7 @@ # define STM32_UART8_PRESC (STM32_UART8_BASE + STM32_USART_PRESC_OFFSET) #endif -#if STM32H5_NUART > 4 +#if STM32_NUART > 4 # define STM32_UART9_CR1 (STM32_UART9_BASE + STM32_USART_CR1_OFFSET) # define STM32_UART9_CR2 (STM32_UART9_BASE + STM32_USART_CR2_OFFSET) # define STM32_UART9_CR3 (STM32_UART9_BASE + STM32_USART_CR3_OFFSET) @@ -232,7 +232,7 @@ # define STM32_UART9_PRESC (STM32_UART9_BASE + STM32_USART_PRESC_OFFSET) #endif -#if STM32H5_NUART > 5 +#if STM32_NUART > 5 # define STM32_UART12_CR1 (STM32_UART12_BASE + STM32_USART_CR1_OFFSET) # define STM32_UART12_CR2 (STM32_UART12_BASE + STM32_USART_CR2_OFFSET) # define STM32_UART12_CR3 (STM32_UART12_BASE + STM32_USART_CR3_OFFSET) diff --git a/arch/arm/src/stm32h5/stm32_adc.c b/arch/arm/src/stm32h5/stm32_adc.c index 75bb194c5dad4..38f58f057df45 100644 --- a/arch/arm/src/stm32h5/stm32_adc.c +++ b/arch/arm/src/stm32h5/stm32_adc.c @@ -53,7 +53,7 @@ #ifdef CONFIG_ADC -#if defined(CONFIG_STM32H5_ADC1) || defined(CONFIG_STM32H5_ADC2) +#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) /**************************************************************************** * Pre-processor Definitions @@ -168,7 +168,7 @@ struct stm32_dev_s /* List of selected ADC channels to sample */ - uint8_t chanlist[CONFIG_STM32H5_ADC_MAX_SAMPLES]; + uint8_t chanlist[CONFIG_STM32_ADC_MAX_SAMPLES]; }; /**************************************************************************** @@ -260,7 +260,7 @@ static const struct adc_ops_s g_adcops = /* ADC1 state */ -#ifdef CONFIG_STM32H5_ADC1 +#ifdef CONFIG_STM32_ADC1 /* Double the size of the buffer in circular mode * Circular mode utilizes half-transfer DMA interrupts and a 2x buffer @@ -269,10 +269,10 @@ static const struct adc_ops_s g_adcops = */ #ifdef ADC1_HAVE_DMA -# define ADC1_CHAN_BUFFER_SIZE (CONFIG_STM32H5_ADC_MAX_SAMPLES *\ - CONFIG_STM32H5_ADC1_DMA_BATCH) +# define ADC1_CHAN_BUFFER_SIZE (CONFIG_STM32_ADC_MAX_SAMPLES *\ + CONFIG_STM32_ADC1_DMA_BATCH) -# ifdef CONFIG_STM32H5_ADC1_DMA_CFG +# if CONFIG_STM32_ADC1_DMA_CFG == 1 # define ADC1_DMA_BUFFER_SIZE (ADC1_CHAN_BUFFER_SIZE * 2) # else # define ADC1_DMA_BUFFER_SIZE (ADC1_CHAN_BUFFER_SIZE) @@ -290,18 +290,18 @@ static struct stm32_dev_s g_adcpriv1 = .irq = STM32_IRQ_ADC1, .isr = adc12_interrupt, .intf = 1, - .resolution = CONFIG_STM32H5_ADC1_RESOLUTION, + .resolution = CONFIG_STM32_ADC1_RESOLUTION, .base = STM32_ADC1_BASE, .mbase = STM32_ADC1_BASE, .initialized = false, #ifdef ADC1_HAVE_TIMER - .trigger = CONFIG_STM32H5_ADC1_TIMTRIG, + .trigger = CONFIG_STM32_ADC1_TIMTRIG, .tbase = ADC1_TIMER_BASE, .trcc_enr = ADC1_TIMER_RCC_ENR, .trcc_en = ADC1_TIMER_RCC_EN, .extsel = ADC1_EXTSEL_VALUE, .pclck = ADC1_TIMER_PCLK_FREQUENCY, - .freq = CONFIG_STM32H5_ADC1_SAMPLE_FREQUENCY, + .freq = CONFIG_STM32_ADC1_SAMPLE_FREQUENCY, #endif #ifdef BOARD_ADC1_DIFSEL @@ -326,8 +326,8 @@ static struct stm32_dev_s g_adcpriv1 = .hasdma = true, .r_chanbuffer = g_adc1_chanbuffer, .r_dmabuffer = g_adc1_dmabuffer, - .dmabatch = CONFIG_STM32H5_ADC1_DMA_BATCH, -# ifdef CONFIG_STM32H5_ADC1_DMA_CFG + .dmabatch = CONFIG_STM32_ADC1_DMA_BATCH, +# if CONFIG_STM32_ADC1_DMA_CFG == 1 .circular = true, # else .circular = false, @@ -338,25 +338,25 @@ static struct stm32_dev_s g_adcpriv1 = #ifdef ADC1_HAVE_OVERSAMPLE .oversample = true, -# ifdef CONFIG_STM32H5_ADC1_TROVS +# ifdef CONFIG_STM32_ADC1_TROVS .trovs = true, # else .trovs = false, # endif - .ovsr = CONFIG_STM32H5_ADC1_OVSR, - .ovss = CONFIG_STM32H5_ADC1_OVSS, + .ovsr = CONFIG_STM32_ADC1_OVSR, + .ovss = CONFIG_STM32_ADC1_OVSS, #else .oversample = false, #endif -#ifdef CONFIG_STM32H5_ADC1_WDG1 +#ifdef CONFIG_STM32_ADC1_WDG1 .wdg1_enable = true, - .wdg1_flt = CONFIG_STM32H5_ADC1_WDG1_FLT, - .wdg1_low_thresh = CONFIG_STM32H5_ADC1_WDG1_LOWTHRESH, - .wdg1_high_thresh = CONFIG_STM32H5_ADC1_WDG1_HIGHTHRESH, -# ifdef CONFIG_STM32H5_ADC1_WDG1_SGL + .wdg1_flt = CONFIG_STM32_ADC1_WDG1_FLT, + .wdg1_low_thresh = CONFIG_STM32_ADC1_WDG1_LOWTHRESH, + .wdg1_high_thresh = CONFIG_STM32_ADC1_WDG1_HIGHTHRESH, +# ifdef CONFIG_STM32_ADC1_WDG1_SGL .wdg1_single_chan = true, - .wdg1_chan = CONFIG_STM32H5_ADC1_WDG1_CHAN, + .wdg1_chan = CONFIG_STM32_ADC1_WDG1_CHAN, # else .wdg1_single_chan = false, .wdg1_chan = 0, @@ -375,13 +375,13 @@ static struct adc_dev_s g_adcdev1 = /* ADC2 state */ -#ifdef CONFIG_STM32H5_ADC2 +#ifdef CONFIG_STM32_ADC2 #ifdef ADC2_HAVE_DMA -# define ADC2_CHAN_BUFFER_SIZE (CONFIG_STM32H5_ADC_MAX_SAMPLES *\ - CONFIG_STM32H5_ADC2_DMA_BATCH) +# define ADC2_CHAN_BUFFER_SIZE (CONFIG_STM32_ADC_MAX_SAMPLES *\ + CONFIG_STM32_ADC2_DMA_BATCH) -# ifdef CONFIG_STM32H5_ADC2_DMA_CFG +# ifdef CONFIG_STM32_ADC2_DMA_CFG # define ADC2_DMA_BUFFER_SIZE (ADC2_CHAN_BUFFER_SIZE * 2) # else # define ADC2_DMA_BUFFER_SIZE (ADC2_CHAN_BUFFER_SIZE) @@ -399,18 +399,18 @@ static struct stm32_dev_s g_adcpriv2 = .irq = STM32_IRQ_ADC2, .isr = adc12_interrupt, .intf = 2, - .resolution = CONFIG_STM32H5_ADC2_RESOLUTION, + .resolution = CONFIG_STM32_ADC2_RESOLUTION, .base = STM32_ADC2_BASE, .mbase = STM32_ADC2_BASE, .initialized = false, #ifdef ADC2_HAVE_TIMER - .trigger = CONFIG_STM32H5_ADC2_TIMTRIG, + .trigger = CONFIG_STM32_ADC2_TIMTRIG, .tbase = ADC2_TIMER_BASE, .trcc_enr = ADC2_TIMER_RCC_ENR, .trcc_en = ADC2_TIMER_RCC_EN, .extsel = ADC2_EXTSEL_VALUE, .pclck = ADC2_TIMER_PCLK_FREQUENCY, - .freq = CONFIG_STM32H5_ADC2_SAMPLE_FREQUENCY, + .freq = CONFIG_STM32_ADC2_SAMPLE_FREQUENCY, #endif #ifdef BOARD_ADC2_DIFSEL @@ -435,8 +435,8 @@ static struct stm32_dev_s g_adcpriv2 = .hasdma = true, .r_chanbuffer = g_adc2_chanbuffer, .r_dmabuffer = g_adc2_dmabuffer, - .dmabatch = CONFIG_STM32H5_ADC2_DMA_BATCH, -# ifdef CONFIG_STM32H5_ADC2_DMA_CFG + .dmabatch = CONFIG_STM32_ADC2_DMA_BATCH, +# ifdef CONFIG_STM32_ADC2_DMA_CFG .circular = true, # else .circular = false, @@ -447,25 +447,25 @@ static struct stm32_dev_s g_adcpriv2 = #ifdef ADC2_HAVE_OVERSAMPLE .oversample = true, -# ifdef CONFIG_STM32H5_ADC2_TROVS +# ifdef CONFIG_STM32_ADC2_TROVS .trovs = true, # else .trovs = false, # endif - .ovsr = CONFIG_STM32H5_ADC2_OVSR, - .ovss = CONFIG_STM32H5_ADC2_OVSS, + .ovsr = CONFIG_STM32_ADC2_OVSR, + .ovss = CONFIG_STM32_ADC2_OVSS, #else .oversample = false, #endif -#ifdef CONFIG_STM32H5_ADC2_WDG1 +#ifdef CONFIG_STM32_ADC2_WDG1 .wdg1_enable = true, - .wdg1_flt = CONFIG_STM32H5_ADC2_WDG1_FLT, - .wdg1_low_thresh = CONFIG_STM32H5_ADC2_WDG1_LOWTHRESH, - .wdg1_high_thresh = CONFIG_STM32H5_ADC2_WDG1_HIGHTHRESH, -# ifdef CONFIG_STM32H5_ADC2_WDG1_SGL + .wdg1_flt = CONFIG_STM32_ADC2_WDG1_FLT, + .wdg1_low_thresh = CONFIG_STM32_ADC2_WDG1_LOWTHRESH, + .wdg1_high_thresh = CONFIG_STM32_ADC2_WDG1_HIGHTHRESH, +# ifdef CONFIG_STM32_ADC2_WDG1_SGL .wdg1_single_chan = true, - .wdg1_chan = CONFIG_STM32H5_ADC2_WDG1_CHAN, + .wdg1_chan = CONFIG_STM32_ADC2_WDG1_CHAN, # else .wdg1_single_chan = false, .wdg1_chan = 0, @@ -1409,7 +1409,7 @@ static int adc_setup(struct adc_dev_s *dev) * ADC1 and ADC2 are enabled.) */ -#if defined(CONFIG_STM32H5_ADC1) && defined(CONFIG_STM32H5_ADC2) +#if defined(CONFIG_STM32_ADC1) && defined(CONFIG_STM32_ADC2) if ((dev == &g_adcdev1 && !((struct stm32_dev_s *)g_adcdev2.ad_priv)->initialized) || (dev == &g_adcdev2 && @@ -1687,7 +1687,7 @@ static int adc_set_ch(struct adc_dev_s *dev, uint8_t ch) priv->rnchannels = 1; } - DEBUGASSERT(priv->rnchannels <= CONFIG_STM32H5_ADC_MAX_SAMPLES); + DEBUGASSERT(priv->rnchannels <= CONFIG_STM32_ADC_MAX_SAMPLES); bits = adc_sqrbits(priv, ADC_SQR4_FIRST, ADC_SQR4_LAST, ADC_SQR4_SQ_OFFSET); @@ -2032,13 +2032,13 @@ static int adc_interrupt(struct adc_dev_s *dev, uint32_t adcisr) * ****************************************************************************/ -#if defined(CONFIG_STM32H5_ADC1) || defined(CONFIG_STM32H5_ADC2) +#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) static int adc12_interrupt(int irq, void *context, void *arg) { uint32_t regval; uint32_t pending; -#ifdef CONFIG_STM32H5_ADC1 +#ifdef CONFIG_STM32_ADC1 regval = getreg32(STM32_ADC1_ISR); pending = regval & ADC_INT_MASK; if (pending != 0) @@ -2047,7 +2047,7 @@ static int adc12_interrupt(int irq, void *context, void *arg) } #endif -#ifdef CONFIG_STM32H5_ADC2 +#ifdef CONFIG_STM32_ADC2 regval = getreg32(STM32_ADC2_ISR); pending = regval & ADC_INT_MASK; if (pending != 0) @@ -2584,10 +2584,10 @@ static int adc_timinit(struct stm32_dev_s *priv) ****************************************************************************/ /**************************************************************************** - * Name: stm32h5_adc_initialize + * Name: stm32_adc_initialize ****************************************************************************/ -struct adc_dev_s *stm32h5_adc_initialize(int intf, +struct adc_dev_s *stm32_adc_initialize(int intf, const uint8_t *chanlist, int cchannels) { @@ -2598,13 +2598,13 @@ struct adc_dev_s *stm32h5_adc_initialize(int intf, switch (intf) { -#ifdef CONFIG_STM32H5_ADC1 +#ifdef CONFIG_STM32_ADC1 case 1: ainfo("ADC1 selected\n"); dev = &g_adcdev1; break; #endif -#ifdef CONFIG_STM32H5_ADC2 +#ifdef CONFIG_STM32_ADC2 case 2: ainfo("ADC2 selected\n"); dev = &g_adcdev2; @@ -2620,10 +2620,10 @@ struct adc_dev_s *stm32h5_adc_initialize(int intf, priv = (struct stm32_dev_s *)dev->ad_priv; priv->cb = NULL; - DEBUGASSERT(cchannels <= CONFIG_STM32H5_ADC_MAX_SAMPLES); - if (cchannels > CONFIG_STM32H5_ADC_MAX_SAMPLES) + DEBUGASSERT(cchannels <= CONFIG_STM32_ADC_MAX_SAMPLES); + if (cchannels > CONFIG_STM32_ADC_MAX_SAMPLES) { - cchannels = CONFIG_STM32H5_ADC_MAX_SAMPLES; + cchannels = CONFIG_STM32_ADC_MAX_SAMPLES; } priv->cchannels = cchannels; @@ -2639,6 +2639,5 @@ struct adc_dev_s *stm32h5_adc_initialize(int intf, return dev; } -#endif /* CONFIG_STM32H5_ADC1 || CONFIG_STM32H5_ADC2 */ +#endif /* CONFIG_STM32_ADC1 || CONFIG_STM32_ADC2 */ #endif /* CONFIG_ADC */ - diff --git a/arch/arm/src/stm32h5/stm32_adc.h b/arch/arm/src/stm32h5/stm32_adc.h index 7777d539376ca..ec1aca6e19b41 100644 --- a/arch/arm/src/stm32h5/stm32_adc.h +++ b/arch/arm/src/stm32h5/stm32_adc.h @@ -36,95 +36,95 @@ * Pre-processor Definitions ****************************************************************************/ -#if defined(CONFIG_STM32H5_ADC1) || defined(CONFIG_STM32H5_ADC2) +#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) /* Configuration ************************************************************/ /* Timer devices may be used for different purposes. One special purpose is - * to control periodic ADC sampling. If CONFIG_STM32H5_TIMn is defined then - * CONFIG_STM32H5_TIMn_ADC must also be defined to indicate that timer "n" + * to control periodic ADC sampling. If CONFIG_STM32_TIMn is defined then + * CONFIG_STM32_TIMn_ADC must also be defined to indicate that timer "n" * is intended to be used for that purpose. */ -#ifndef CONFIG_STM32H5_TIM1 -# undef CONFIG_STM32H5_TIM1_ADC -# undef CONFIG_STM32H5_TIM1_ADC1 -# undef CONFIG_STM32H5_TIM1_ADC2 +#ifndef CONFIG_STM32_TIM1 +# undef CONFIG_STM32_TIM1_ADC +# undef CONFIG_STM32_TIM1_ADC1 +# undef CONFIG_STM32_TIM1_ADC2 #endif -#ifndef CONFIG_STM32H5_TIM2 -# undef CONFIG_STM32H5_TIM2_ADC -# undef CONFIG_STM32H5_TIM2_ADC1 -# undef CONFIG_STM32H5_TIM2_ADC2 +#ifndef CONFIG_STM32_TIM2 +# undef CONFIG_STM32_TIM2_ADC +# undef CONFIG_STM32_TIM2_ADC1 +# undef CONFIG_STM32_TIM2_ADC2 #endif -#ifndef CONFIG_STM32H5_TIM3 -# undef CONFIG_STM32H5_TIM3_ADC -# undef CONFIG_STM32H5_TIM3_ADC1 -# undef CONFIG_STM32H5_TIM3_ADC2 +#ifndef CONFIG_STM32_TIM3 +# undef CONFIG_STM32_TIM3_ADC +# undef CONFIG_STM32_TIM3_ADC1 +# undef CONFIG_STM32_TIM3_ADC2 #endif -#ifndef CONFIG_STM32H5_TIM4 -# undef CONFIG_STM32H5_TIM4_ADC -# undef CONFIG_STM32H5_TIM4_ADC1 -# undef CONFIG_STM32H5_TIM4_ADC2 +#ifndef CONFIG_STM32_TIM4 +# undef CONFIG_STM32_TIM4_ADC +# undef CONFIG_STM32_TIM4_ADC1 +# undef CONFIG_STM32_TIM4_ADC2 #endif -#ifndef CONFIG_STM32H5_TIM6 -# undef CONFIG_STM32H5_TIM6_ADC -# undef CONFIG_STM32H5_TIM6_ADC1 -# undef CONFIG_STM32H5_TIM6_ADC2 +#ifndef CONFIG_STM32_TIM6 +# undef CONFIG_STM32_TIM6_ADC +# undef CONFIG_STM32_TIM6_ADC1 +# undef CONFIG_STM32_TIM6_ADC2 #endif -#ifndef CONFIG_STM32H5_TIM8 -# undef CONFIG_STM32H5_TIM8_ADC -# undef CONFIG_STM32H5_TIM8_ADC1 -# undef CONFIG_STM32H5_TIM8_ADC2 +#ifndef CONFIG_STM32_TIM8 +# undef CONFIG_STM32_TIM8_ADC +# undef CONFIG_STM32_TIM8_ADC1 +# undef CONFIG_STM32_TIM8_ADC2 #endif -#ifndef CONFIG_STM32H5_TIM15 -# undef CONFIG_STM32H5_TIM15_ADC -# undef CONFIG_STM32H5_TIM15_ADC1 -# undef CONFIG_STM32H5_TIM15_ADC2 +#ifndef CONFIG_STM32_TIM15 +# undef CONFIG_STM32_TIM15_ADC +# undef CONFIG_STM32_TIM15_ADC1 +# undef CONFIG_STM32_TIM15_ADC2 #endif /* DMA support */ #undef ADC_HAVE_DMA -#if defined(CONFIG_STM32H5_ADC1_DMA) || defined(CONFIG_STM32H5_ADC2_DMA) +#if defined(CONFIG_STM32_ADC1_DMA) || defined(CONFIG_STM32_ADC2_DMA) # define ADC_HAVE_DMA 1 #endif -#if defined(CONFIG_STM32H5_ADC1_DMA) +#if defined(CONFIG_STM32_ADC1_DMA) # define ADC1_HAVE_DMA 1 #endif -#if defined(CONFIG_STM32H5_ADC2_DMA) +#if defined(CONFIG_STM32_ADC2_DMA) # define ADC2_HAVE_DMA 1 #endif /* Oversampling support */ #undef ADC_HAVE_OVERSAMPLE -#if defined(CONFIG_STM32H5_ADC1_OVERSAMPLE) || \ - defined(CONFIG_STM32H5_ADC2_OVERSAMPLE) +#if defined(CONFIG_STM32_ADC1_OVERSAMPLE) || \ + defined(CONFIG_STM32_ADC2_OVERSAMPLE) # define ADC_HAVE_OVERSAMPLE 1 #endif -#if defined(CONFIG_STM32H5_ADC1_OVERSAMPLE) +#if defined(CONFIG_STM32_ADC1_OVERSAMPLE) # define ADC1_HAVE_OVERSAMPLE 1 #endif -#if defined(CONFIG_STM32H5_ADC2_OVERSAMPLE) +#if defined(CONFIG_STM32_ADC2_OVERSAMPLE) # define ADC2_HAVE_OVERSAMPLE 1 #endif #undef ADC_HAVE_WDG1 -#if defined(CONFIG_STM32H5_ADC1_WDG1) || defined(CONFIG_STM32H5_ADC2_WDG1) +#if defined(CONFIG_STM32_ADC1_WDG1) || defined(CONFIG_STM32_ADC2_WDG1) # define ADC_HAVE_WDG1 1 #endif #undef ADC_HAVE_WDG2 -#if defined(CONFIG_STM32H5_ADC1_WDG2) || defined(CONFIG_STM32H5_ADC2_WDG2) +#if defined(CONFIG_STM32_ADC1_WDG2) || defined(CONFIG_STM32_ADC2_WDG2) # define ADC_HAVE_WDG2 1 #endif #undef ADC_HAVE_WDG3 -#if defined(CONFIG_STM32H5_ADC1_WDG3) || defined(CONFIG_STM32H5_ADC2_WDG3) +#if defined(CONFIG_STM32_ADC1_WDG3) || defined(CONFIG_STM32_ADC2_WDG3) # define ADC_HAVE_WDG3 1 #endif @@ -136,43 +136,43 @@ * information about the timer. */ -#if defined(CONFIG_STM32H5_TIM1_ADC1) +#if defined(CONFIG_STM32_TIM1_ADC1) # define ADC1_HAVE_TIMER 1 # define ADC1_TIMER_BASE STM32_TIM1_BASE # define ADC1_TIMER_PCLK_FREQUENCY STM32_APB2_TIM1_CLKIN # define ADC1_TIMER_RCC_ENR STM32_RCC_APB2ENR # define ADC1_TIMER_RCC_EN RCC_APB2ENR_TIM1EN -#elif defined(CONFIG_STM32H5_TIM2_ADC1) +#elif defined(CONFIG_STM32_TIM2_ADC1) # define ADC1_HAVE_TIMER 1 # define ADC1_TIMER_BASE STM32_TIM2_BASE # define ADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM2_CLKIN # define ADC1_TIMER_RCC_ENR STM32_RCC_APB1LENR # define ADC1_TIMER_RCC_EN RCC_APB1LENR_TIM2EN -#elif defined(CONFIG_STM32H5_TIM3_ADC1) +#elif defined(CONFIG_STM32_TIM3_ADC1) # define ADC1_HAVE_TIMER 1 # define ADC1_TIMER_BASE STM32_TIM3_BASE # define ADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM3_CLKIN # define ADC1_TIMER_RCC_ENR STM32_RCC_APB1LENR # define ADC1_TIMER_RCC_EN RCC_APB1LENR_TIM3EN -#elif defined(CONFIG_STM32H5_TIM4_ADC1) +#elif defined(CONFIG_STM32_TIM4_ADC1) # define ADC1_HAVE_TIMER 1 # define ADC1_TIMER_BASE STM32_TIM4_BASE # define ADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM4_CLKIN # define ADC1_TIMER_RCC_ENR STM32_RCC_APB1LENR # define ADC1_TIMER_RCC_EN RCC_APB1LENR_TIM4EN -#elif defined(CONFIG_STM32H5_TIM6_ADC1) +#elif defined(CONFIG_STM32_TIM6_ADC1) # define ADC1_HAVE_TIMER 1 # define ADC1_TIMER_BASE STM32_TIM6_BASE # define ADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM6_CLKIN # define ADC1_TIMER_RCC_ENR STM32_RCC_APB1LENR # define ADC1_TIMER_RCC_EN RCC_APB1LENR_TIM6EN -#elif defined(CONFIG_STM32H5_TIM8_ADC1) +#elif defined(CONFIG_STM32_TIM8_ADC1) # define ADC1_HAVE_TIMER 1 # define ADC1_TIMER_BASE STM32_TIM8_BASE # define ADC1_TIMER_PCLK_FREQUENCY STM32_APB2_TIM8_CLKIN # define ADC1_TIMER_RCC_ENR STM32_RCC_APB2ENR # define ADC1_TIMER_RCC_EN RCC_APB2ENR_TIM8EN -#elif defined(CONFIG_STM32H5_TIM15_ADC1) +#elif defined(CONFIG_STM32_TIM15_ADC1) # define ADC1_HAVE_TIMER 1 # define ADC1_TIMER_BASE STM32_TIM15_BASE # define ADC1_TIMER_PCLK_FREQUENCY STM32_APB2_TIM15_CLKIN @@ -183,52 +183,52 @@ #endif #ifdef ADC1_HAVE_TIMER -# ifndef CONFIG_STM32H5_ADC1_SAMPLE_FREQUENCY -# error "CONFIG_STM32H5_ADC1_SAMPLE_FREQUENCY not defined" +# ifndef CONFIG_STM32_ADC1_SAMPLE_FREQUENCY +# error "CONFIG_STM32_ADC1_SAMPLE_FREQUENCY not defined" # endif -# ifndef CONFIG_STM32H5_ADC1_TIMTRIG -# error "CONFIG_STM32H5_ADC1_TIMTRIG not defined" +# ifndef CONFIG_STM32_ADC1_TIMTRIG +# error "CONFIG_STM32_ADC1_TIMTRIG not defined" # warning "Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO" # endif #endif -#if defined(CONFIG_STM32H5_TIM1_ADC2) +#if defined(CONFIG_STM32_TIM1_ADC2) # define ADC2_HAVE_TIMER 1 # define ADC2_TIMER_BASE STM32_TIM1_BASE # define ADC2_TIMER_PCLK_FREQUENCY STM32_APB2_TIM1_CLKIN # define ADC2_TIMER_RCC_ENR STM32_RCC_APB2ENR # define ADC2_TIMER_RCC_EN RCC_APB2ENR_TIM1EN -#elif defined(CONFIG_STM32H5_TIM2_ADC2) +#elif defined(CONFIG_STM32_TIM2_ADC2) # define ADC2_HAVE_TIMER 1 # define ADC2_TIMER_BASE STM32_TIM2_BASE # define ADC2_TIMER_PCLK_FREQUENCY STM32_APB1_TIM2_CLKIN # define ADC2_TIMER_RCC_ENR STM32_RCC_APB1LENR # define ADC2_TIMER_RCC_EN RCC_APB1LENR_TIM2EN -#elif defined(CONFIG_STM32H5_TIM3_ADC2) +#elif defined(CONFIG_STM32_TIM3_ADC2) # define ADC2_HAVE_TIMER 1 # define ADC2_TIMER_BASE STM32_TIM3_BASE # define ADC2_TIMER_PCLK_FREQUENCY STM32_APB1_TIM3_CLKIN # define ADC2_TIMER_RCC_ENR STM32_RCC_APB1LENR # define ADC2_TIMER_RCC_EN RCC_APB1LENR_TIM3EN -#elif defined(CONFIG_STM32H5_TIM4_ADC2) +#elif defined(CONFIG_STM32_TIM4_ADC2) # define ADC2_HAVE_TIMER 1 # define ADC2_TIMER_BASE STM32_TIM4_BASE # define ADC2_TIMER_PCLK_FREQUENCY STM32_APB1_TIM4_CLKIN # define ADC2_TIMER_RCC_ENR STM32_RCC_APB1LENR # define ADC2_TIMER_RCC_EN RCC_APB1LENR_TIM4EN -#elif defined(CONFIG_STM32H5_TIM6_ADC2) +#elif defined(CONFIG_STM32_TIM6_ADC2) # define ADC2_HAVE_TIMER 1 # define ADC2_TIMER_BASE STM32_TIM6_BASE # define ADC2_TIMER_PCLK_FREQUENCY STM32_APB1_TIM6_CLKIN # define ADC2_TIMER_RCC_ENR STM32_RCC_APB1LENR # define ADC2_TIMER_RCC_EN RCC_APB1LENR_TIM6EN -#elif defined(CONFIG_STM32H5_TIM8_ADC2) +#elif defined(CONFIG_STM32_TIM8_ADC2) # define ADC2_HAVE_TIMER 1 # define ADC2_TIMER_BASE STM32_TIM8_BASE # define ADC2_TIMER_PCLK_FREQUENCY STM32_APB2_TIM8_CLKIN # define ADC2_TIMER_RCC_ENR STM32_RCC_APB2ENR # define ADC2_TIMER_RCC_EN RCC_APB2ENR_TIM8EN -#elif defined(CONFIG_STM32H5_TIM15_ADC2) +#elif defined(CONFIG_STM32_TIM15_ADC2) # define ADC2_HAVE_TIMER 1 # define ADC2_TIMER_BASE STM32_TIM15_BASE # define ADC2_TIMER_PCLK_FREQUENCY STM32_APB2_TIM15_CLKIN @@ -239,11 +239,11 @@ #endif #ifdef ADC2_HAVE_TIMER -# ifndef CONFIG_STM32H5_ADC2_SAMPLE_FREQUENCY -# error "CONFIG_STM32H5_ADC2_SAMPLE_FREQUENCY not defined" +# ifndef CONFIG_STM32_ADC2_SAMPLE_FREQUENCY +# error "CONFIG_STM32_ADC2_SAMPLE_FREQUENCY not defined" # endif -# ifndef CONFIG_STM32H5_ADC2_TIMTRIG -# error "CONFIG_STM32H5_ADC2_TIMTRIG not defined" +# ifndef CONFIG_STM32_ADC2_TIMTRIG +# error "CONFIG_STM32_ADC2_TIMTRIG not defined" # warning "Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO" # endif #endif @@ -254,231 +254,231 @@ # undef ADC_HAVE_TIMER #endif -#if defined(CONFIG_STM32H5_TIM1_ADC1) -# if CONFIG_STM32H5_ADC1_TIMTRIG == 0 +#if defined(CONFIG_STM32_TIM1_ADC1) +# if CONFIG_STM32_ADC1_TIMTRIG == 0 # define ADC1_EXTSEL_VALUE ADC_CFGR_EXTSEL_T1CC1 -# elif CONFIG_STM32H5_ADC1_TIMTRIG == 1 +# elif CONFIG_STM32_ADC1_TIMTRIG == 1 # define ADC1_EXTSEL_VALUE ADC_CFGR_EXTSEL_T1CC2 -# elif CONFIG_STM32H5_ADC1_TIMTRIG == 2 +# elif CONFIG_STM32_ADC1_TIMTRIG == 2 # define ADC1_EXTSEL_VALUE ADC_CFGR__EXTSEL_T1CC3 -# elif CONFIG_STM32H5_ADC1_TIMTRIG == 3 +# elif CONFIG_STM32_ADC1_TIMTRIG == 3 # define ADC1_EXTSEL_VALUE ADC_CFGR_EXTSEL_T1CC4 -# elif CONFIG_STM32H5_ADC1_TIMTRIG == 4 +# elif CONFIG_STM32_ADC1_TIMTRIG == 4 # define ADC1_EXTSEL_VALUE ADC_CFGR_EXTSEL_T1TRGO -# elif CONFIG_STM32H5_ADC1_TIMTRIG == 5 +# elif CONFIG_STM32_ADC1_TIMTRIG == 5 # define ADC1_EXTSEL_VALUE ADC_CFGR_EXTSEL_T1TRGO2 # else -# error "CONFIG_STM32H5_ADC1_TIMTRIG is out of range (TIM1)" +# error "CONFIG_STM32_ADC1_TIMTRIG is out of range (TIM1)" # endif -#elif defined(CONFIG_STM32H5_TIM2_ADC1) -# if CONFIG_STM32H5_ADC1_TIMTRIG == 0 -# error "CONFIG_STM32H5_ADC1_TIMTRIG is invalid (TIM2)" -# elif CONFIG_STM32H5_ADC1_TIMTRIG == 1 +#elif defined(CONFIG_STM32_TIM2_ADC1) +# if CONFIG_STM32_ADC1_TIMTRIG == 0 +# error "CONFIG_STM32_ADC1_TIMTRIG is invalid (TIM2)" +# elif CONFIG_STM32_ADC1_TIMTRIG == 1 # define ADC1_EXTSEL_VALUE ADC_CFGR_EXTSEL_T2CC2 -# elif CONFIG_STM32H5_ADC1_TIMTRIG == 2 -# error "CONFIG_STM32H5_ADC1_TIMTRIG is invalid (TIM2)" -# elif CONFIG_STM32H5_ADC1_TIMTRIG == 3 -# error "CONFIG_STM32H5_ADC1_TIMTRIG is invalid (TIM2)" -# elif CONFIG_STM32H5_ADC1_TIMTRIG == 4 +# elif CONFIG_STM32_ADC1_TIMTRIG == 2 +# error "CONFIG_STM32_ADC1_TIMTRIG is invalid (TIM2)" +# elif CONFIG_STM32_ADC1_TIMTRIG == 3 +# error "CONFIG_STM32_ADC1_TIMTRIG is invalid (TIM2)" +# elif CONFIG_STM32_ADC1_TIMTRIG == 4 # define ADC1_EXTSEL_VALUE ADC_CFGR_EXTSEL_T2TRGO -# elif CONFIG_STM32H5_ADC1_TIMTRIG == 5 -# error "CONFIG_STM32H5_ADC1_TIMTRIG is invalid (TIM2)" +# elif CONFIG_STM32_ADC1_TIMTRIG == 5 +# error "CONFIG_STM32_ADC1_TIMTRIG is invalid (TIM2)" # else -# error "CONFIG_STM32H5_ADC1_TIMTRIG is out of range (TIM2)" +# error "CONFIG_STM32_ADC1_TIMTRIG is out of range (TIM2)" # endif -#elif defined(CONFIG_STM32H5_TIM3_ADC1) -# if CONFIG_STM32H5_ADC1_TIMTRIG == 0 -# error "CONFIG_STM32H5_ADC1_TIMTRIG is invalid (TIM3)" -# elif CONFIG_STM32H5_ADC1_TIMTRIG == 1 -# error "CONFIG_STM32H5_ADC1_TIMTRIG is invalid (TIM3)" -# elif CONFIG_STM32H5_ADC1_TIMTRIG == 2 -# error "CONFIG_STM32H5_ADC1_TIMTRIG is invalid (TIM3)" -# elif CONFIG_STM32H5_ADC1_TIMTRIG == 3 +#elif defined(CONFIG_STM32_TIM3_ADC1) +# if CONFIG_STM32_ADC1_TIMTRIG == 0 +# error "CONFIG_STM32_ADC1_TIMTRIG is invalid (TIM3)" +# elif CONFIG_STM32_ADC1_TIMTRIG == 1 +# error "CONFIG_STM32_ADC1_TIMTRIG is invalid (TIM3)" +# elif CONFIG_STM32_ADC1_TIMTRIG == 2 +# error "CONFIG_STM32_ADC1_TIMTRIG is invalid (TIM3)" +# elif CONFIG_STM32_ADC1_TIMTRIG == 3 # define ADC1_EXTSEL_VALUE ADC_CFGR_EXTSEL_T3CC4 -# elif CONFIG_STM32H5_ADC1_TIMTRIG == 4 +# elif CONFIG_STM32_ADC1_TIMTRIG == 4 # define ADC1_EXTSEL_VALUE ADC_CFGR_EXTSEL_T3TRGO -# elif CONFIG_STM32H5_ADC1_TIMTRIG == 5 -# error "CONFIG_STM32H5_ADC1_TIMTRIG is invalid (TIM3)" +# elif CONFIG_STM32_ADC1_TIMTRIG == 5 +# error "CONFIG_STM32_ADC1_TIMTRIG is invalid (TIM3)" # else -# error "CONFIG_STM32H5_ADC1_TIMTRIG is out of range (TIM3)" +# error "CONFIG_STM32_ADC1_TIMTRIG is out of range (TIM3)" # endif -#elif defined(CONFIG_STM32H5_TIM4_ADC1) -# if CONFIG_STM32H5_ADC1_TIMTRIG == 0 -# error "CONFIG_STM32H5_ADC1_TIMTRIG is invalid (TIM4)" -# elif CONFIG_STM32H5_ADC1_TIMTRIG == 1 -# error "CONFIG_STM32H5_ADC1_TIMTRIG is invalid (TIM4)" -# elif CONFIG_STM32H5_ADC1_TIMTRIG == 2 -# error "CONFIG_STM32H5_ADC1_TIMTRIG is invalid (TIM4)" -# elif CONFIG_STM32H5_ADC1_TIMTRIG == 3 +#elif defined(CONFIG_STM32_TIM4_ADC1) +# if CONFIG_STM32_ADC1_TIMTRIG == 0 +# error "CONFIG_STM32_ADC1_TIMTRIG is invalid (TIM4)" +# elif CONFIG_STM32_ADC1_TIMTRIG == 1 +# error "CONFIG_STM32_ADC1_TIMTRIG is invalid (TIM4)" +# elif CONFIG_STM32_ADC1_TIMTRIG == 2 +# error "CONFIG_STM32_ADC1_TIMTRIG is invalid (TIM4)" +# elif CONFIG_STM32_ADC1_TIMTRIG == 3 # define ADC1_EXTSEL_VALUE ADC_CFGR_EXTSEL_T4CC4 -# elif CONFIG_STM32H5_ADC1_TIMTRIG == 4 +# elif CONFIG_STM32_ADC1_TIMTRIG == 4 # define ADC1_EXTSEL_VALUE ADC_CRFT_EXTSEL_T4TRGO -# elif CONFIG_STM32H5_ADC1_TIMTRIG == 5 -# error "CONFIG_STM32H5_ADC1_TIMTRIG is invalid (TIM4)" +# elif CONFIG_STM32_ADC1_TIMTRIG == 5 +# error "CONFIG_STM32_ADC1_TIMTRIG is invalid (TIM4)" # else -# error "CONFIG_STM32H5_ADC1_TIMTRIG is out of range (TIM4)" +# error "CONFIG_STM32_ADC1_TIMTRIG is out of range (TIM4)" # endif -#elif defined(CONFIG_STM32H5_TIM6_ADC1) -# if CONFIG_STM32H5_ADC1_TIMTRIG == 0 -# error "CONFIG_STM32H5_ADC1_TIMTRIG is invalid (TIM6)" -# elif CONFIG_STM32H5_ADC1_TIMTRIG == 1 -# error "CONFIG_STM32H5_ADC1_TIMTRIG is invalid (TIM6)" -# elif CONFIG_STM32H5_ADC1_TIMTRIG == 2 -# error "CONFIG_STM32H5_ADC1_TIMTRIG is invalid (TIM6)" -# elif CONFIG_STM32H5_ADC1_TIMTRIG == 3 -# error "CONFIG_STM32H5_ADC1_TIMTRIG is invalid (TIM6)" -# elif CONFIG_STM32H5_ADC1_TIMTRIG == 4 +#elif defined(CONFIG_STM32_TIM6_ADC1) +# if CONFIG_STM32_ADC1_TIMTRIG == 0 +# error "CONFIG_STM32_ADC1_TIMTRIG is invalid (TIM6)" +# elif CONFIG_STM32_ADC1_TIMTRIG == 1 +# error "CONFIG_STM32_ADC1_TIMTRIG is invalid (TIM6)" +# elif CONFIG_STM32_ADC1_TIMTRIG == 2 +# error "CONFIG_STM32_ADC1_TIMTRIG is invalid (TIM6)" +# elif CONFIG_STM32_ADC1_TIMTRIG == 3 +# error "CONFIG_STM32_ADC1_TIMTRIG is invalid (TIM6)" +# elif CONFIG_STM32_ADC1_TIMTRIG == 4 # define ADC1_EXTSEL_VALUE ADC_CFGR_EXTSEL_T6TRGO -# elif CONFIG_STM32H5_ADC1_TIMTRIG == 5 -# error "CONFIG_STM32H5_ADC1_TIMTRIG is invalid (TIM6)" +# elif CONFIG_STM32_ADC1_TIMTRIG == 5 +# error "CONFIG_STM32_ADC1_TIMTRIG is invalid (TIM6)" # else -# error "CONFIG_STM32H5_ADC1_TIMTRIG is out of range (TIM6)" +# error "CONFIG_STM32_ADC1_TIMTRIG is out of range (TIM6)" # endif -#elif defined(CONFIG_STM32H5_TIM8_ADC1) -# if CONFIG_STM32H5_ADC1_TIMTRIG == 0 -# error "CONFIG_STM32H5_ADC1_TIMTRIG is invalid (TIM8)" -# elif CONFIG_STM32H5_ADC1_TIMTRIG == 1 -# error "CONFIG_STM32H5_ADC1_TIMTRIG is invalid (TIM8)" -# elif CONFIG_STM32H5_ADC1_TIMTRIG == 2 -# error "CONFIG_STM32H5_ADC1_TIMTRIG is invalid (TIM8)" -# elif CONFIG_STM32H5_ADC1_TIMTRIG == 3 -# error "CONFIG_STM32H5_ADC1_TIMTRIG is invalid (TIM8)" -# elif CONFIG_STM32H5_ADC1_TIMTRIG == 4 +#elif defined(CONFIG_STM32_TIM8_ADC1) +# if CONFIG_STM32_ADC1_TIMTRIG == 0 +# error "CONFIG_STM32_ADC1_TIMTRIG is invalid (TIM8)" +# elif CONFIG_STM32_ADC1_TIMTRIG == 1 +# error "CONFIG_STM32_ADC1_TIMTRIG is invalid (TIM8)" +# elif CONFIG_STM32_ADC1_TIMTRIG == 2 +# error "CONFIG_STM32_ADC1_TIMTRIG is invalid (TIM8)" +# elif CONFIG_STM32_ADC1_TIMTRIG == 3 +# error "CONFIG_STM32_ADC1_TIMTRIG is invalid (TIM8)" +# elif CONFIG_STM32_ADC1_TIMTRIG == 4 # define ADC1_EXTSEL_VALUE ADC_CFGR_EXTSEL_T8TRGO -# elif CONFIG_STM32H5_ADC1_TIMTRIG == 5 +# elif CONFIG_STM32_ADC1_TIMTRIG == 5 # define ADC1_EXTSEL_VALUE ADC_CFGR_EXTSEL_T8TRGO2 # else -# error "CONFIG_STM32H5_ADC1_TIMTRIG is out of range (TIM8)" +# error "CONFIG_STM32_ADC1_TIMTRIG is out of range (TIM8)" # endif -#elif defined(CONFIG_STM32H5_TIM15_ADC1) -# if CONFIG_STM32H5_ADC1_TIMTRIG == 0 -# error "CONFIG_STM32H5_ADC1_TIMTRIG is invalid (TIM15)" -# elif CONFIG_STM32H5_ADC1_TIMTRIG == 1 -# error "CONFIG_STM32H5_ADC1_TIMTRIG is invalid (TIM15)" -# elif CONFIG_STM32H5_ADC1_TIMTRIG == 2 -# error "CONFIG_STM32H5_ADC1_TIMTRIG is invalid (TIM15)" -# elif CONFIG_STM32H5_ADC1_TIMTRIG == 3 -# error "CONFIG_STM32H5_ADC1_TIMTRIG is invalid (TIM15)" -# elif CONFIG_STM32H5_ADC1_TIMTRIG == 4 +#elif defined(CONFIG_STM32_TIM15_ADC1) +# if CONFIG_STM32_ADC1_TIMTRIG == 0 +# error "CONFIG_STM32_ADC1_TIMTRIG is invalid (TIM15)" +# elif CONFIG_STM32_ADC1_TIMTRIG == 1 +# error "CONFIG_STM32_ADC1_TIMTRIG is invalid (TIM15)" +# elif CONFIG_STM32_ADC1_TIMTRIG == 2 +# error "CONFIG_STM32_ADC1_TIMTRIG is invalid (TIM15)" +# elif CONFIG_STM32_ADC1_TIMTRIG == 3 +# error "CONFIG_STM32_ADC1_TIMTRIG is invalid (TIM15)" +# elif CONFIG_STM32_ADC1_TIMTRIG == 4 # define ADC1_EXTSEL_VALUE ADC_CFGR_EXTSEL_T15TRGO -# elif CONFIG_STM32H5_ADC1_TIMTRIG == 5 -# error "CONFIG_STM32H5_ADC1_TIMTRIG is invalid (TIM15)" +# elif CONFIG_STM32_ADC1_TIMTRIG == 5 +# error "CONFIG_STM32_ADC1_TIMTRIG is invalid (TIM15)" # else -# error "CONFIG_STM32H5_ADC1_TIMTRIG is out of range (TIM15)" +# error "CONFIG_STM32_ADC1_TIMTRIG is out of range (TIM15)" # endif #endif -#if defined(CONFIG_STM32H5_TIM1_ADC2) -# if CONFIG_STM32H5_ADC2_TIMTRIG == 0 +#if defined(CONFIG_STM32_TIM1_ADC2) +# if CONFIG_STM32_ADC2_TIMTRIG == 0 # define ADC2_EXTSEL_VALUE ADC_CFGR_EXTSEL_T1CC1 -# elif CONFIG_STM32H5_ADC2_TIMTRIG == 1 +# elif CONFIG_STM32_ADC2_TIMTRIG == 1 # define ADC2_EXTSEL_VALUE ADC_CFGR_EXTSEL_T1CC2 -# elif CONFIG_STM32H5_ADC2_TIMTRIG == 2 +# elif CONFIG_STM32_ADC2_TIMTRIG == 2 # define ADC2_EXTSEL_VALUE ADC_CFGR_EXTSEL_T1CC3 -# elif CONFIG_STM32H5_ADC2_TIMTRIG == 3 +# elif CONFIG_STM32_ADC2_TIMTRIG == 3 # define ADC2_EXTSEL_VALUE ADC_CFGR_EXTSEL_T1CC4 -# elif CONFIG_STM32H5_ADC2_TIMTRIG == 4 +# elif CONFIG_STM32_ADC2_TIMTRIG == 4 # define ADC2_EXTSEL_VALUE ADC_CFGR_EXTSEL_T1TRGO -# elif CONFIG_STM32H5_ADC2_TIMTRIG == 5 +# elif CONFIG_STM32_ADC2_TIMTRIG == 5 # define ADC2_EXTSEL_VALUE ADC_CFGR_EXTSEL_T1TRGO2 # else -# error "CONFIG_STM32H5_ADC2_TIMTRIG is out of range (TIM1)" +# error "CONFIG_STM32_ADC2_TIMTRIG is out of range (TIM1)" # endif -#elif defined(CONFIG_STM32H5_TIM2_ADC2) -# if CONFIG_STM32H5_ADC2_TIMTRIG == 0 -# error "CONFIG_STM32H5_ADC2_TIMTRIG is invalid (TIM2)" -# elif CONFIG_STM32H5_ADC2_TIMTRIG == 1 +#elif defined(CONFIG_STM32_TIM2_ADC2) +# if CONFIG_STM32_ADC2_TIMTRIG == 0 +# error "CONFIG_STM32_ADC2_TIMTRIG is invalid (TIM2)" +# elif CONFIG_STM32_ADC2_TIMTRIG == 1 # define ADC2_EXTSEL_VALUE ADC_CFGR_EXTSEL_T2CC2 -# elif CONFIG_STM32H5_ADC2_TIMTRIG == 2 -# error "CONFIG_STM32H5_ADC2_TIMTRIG is invalid (TIM2)" -# elif CONFIG_STM32H5_ADC2_TIMTRIG == 3 -# error "CONFIG_STM32H5_ADC2_TIMTRIG is invalid (TIM2)" -# elif CONFIG_STM32H5_ADC2_TIMTRIG == 4 +# elif CONFIG_STM32_ADC2_TIMTRIG == 2 +# error "CONFIG_STM32_ADC2_TIMTRIG is invalid (TIM2)" +# elif CONFIG_STM32_ADC2_TIMTRIG == 3 +# error "CONFIG_STM32_ADC2_TIMTRIG is invalid (TIM2)" +# elif CONFIG_STM32_ADC2_TIMTRIG == 4 # define ADC2_EXTSEL_VALUE ADC_CFGR_EXTSEL_T2TRGO -# elif CONFIG_STM32H5_ADC2_TIMTRIG == 5 -# error "CONFIG_STM32H5_ADC2_TIMTRIG is invalid (TIM2)" +# elif CONFIG_STM32_ADC2_TIMTRIG == 5 +# error "CONFIG_STM32_ADC2_TIMTRIG is invalid (TIM2)" # else -# error "CONFIG_STM32H5_ADC2_TIMTRIG is out of range (TIM2)" +# error "CONFIG_STM32_ADC2_TIMTRIG is out of range (TIM2)" # endif -#elif defined(CONFIG_STM32H5_TIM3_ADC2) -# if CONFIG_STM32H5_ADC2_TIMTRIG == 0 -# error "CONFIG_STM32H5_ADC2_TIMTRIG is invalid (TIM3)" -# elif CONFIG_STM32H5_ADC2_TIMTRIG == 1 -# error "CONFIG_STM32H5_ADC2_TIMTRIG is invalid (TIM3)" -# elif CONFIG_STM32H5_ADC2_TIMTRIG == 2 -# error "CONFIG_STM32H5_ADC2_TIMTRIG is invalid (TIM3)" -# elif CONFIG_STM32H5_ADC2_TIMTRIG == 3 +#elif defined(CONFIG_STM32_TIM3_ADC2) +# if CONFIG_STM32_ADC2_TIMTRIG == 0 +# error "CONFIG_STM32_ADC2_TIMTRIG is invalid (TIM3)" +# elif CONFIG_STM32_ADC2_TIMTRIG == 1 +# error "CONFIG_STM32_ADC2_TIMTRIG is invalid (TIM3)" +# elif CONFIG_STM32_ADC2_TIMTRIG == 2 +# error "CONFIG_STM32_ADC2_TIMTRIG is invalid (TIM3)" +# elif CONFIG_STM32_ADC2_TIMTRIG == 3 # define ADC2_EXTSEL_VALUE ADC_CFGR_EXTSEL_T3CC4 -# elif CONFIG_STM32H5_ADC2_TIMTRIG == 4 +# elif CONFIG_STM32_ADC2_TIMTRIG == 4 # define ADC2_EXTSEL_VALUE ADC_CFGR_EXTSEL_T3TRGO -# elif CONFIG_STM32H5_ADC2_TIMTRIG == 5 -# error "CONFIG_STM32H5_ADC2_TIMTRIG is invalid (TIM3)" +# elif CONFIG_STM32_ADC2_TIMTRIG == 5 +# error "CONFIG_STM32_ADC2_TIMTRIG is invalid (TIM3)" # else -# error "CONFIG_STM32H5_ADC2_TIMTRIG is out of range (TIM3)" +# error "CONFIG_STM32_ADC2_TIMTRIG is out of range (TIM3)" # endif -#elif defined(CONFIG_STM32H5_TIM4_ADC2) -# if CONFIG_STM32H5_ADC2_TIMTRIG == 0 -# error "CONFIG_STM32H5_ADC2_TIMTRIG is invalid (TIM4)" -# elif CONFIG_STM32H5_ADC2_TIMTRIG == 1 -# error "CONFIG_STM32H5_ADC2_TIMTRIG is invalid (TIM4)" -# elif CONFIG_STM32H5_ADC2_TIMTRIG == 2 -# error "CONFIG_STM32H5_ADC2_TIMTRIG is invalid (TIM4)" -# elif CONFIG_STM32H5_ADC2_TIMTRIG == 3 +#elif defined(CONFIG_STM32_TIM4_ADC2) +# if CONFIG_STM32_ADC2_TIMTRIG == 0 +# error "CONFIG_STM32_ADC2_TIMTRIG is invalid (TIM4)" +# elif CONFIG_STM32_ADC2_TIMTRIG == 1 +# error "CONFIG_STM32_ADC2_TIMTRIG is invalid (TIM4)" +# elif CONFIG_STM32_ADC2_TIMTRIG == 2 +# error "CONFIG_STM32_ADC2_TIMTRIG is invalid (TIM4)" +# elif CONFIG_STM32_ADC2_TIMTRIG == 3 # define ADC2_EXTSEL_VALUE ADC_CFGR_EXTSEL_T4CC4 -# elif CONFIG_STM32H5_ADC2_TIMTRIG == 4 +# elif CONFIG_STM32_ADC2_TIMTRIG == 4 # define ADC2_EXTSEL_VALUE ADC_CFGR_EXTSEL_T4TRGO -# elif CONFIG_STM32H5_ADC2_TIMTRIG == 5 -# error "CONFIG_STM32H5_ADC2_TIMTRIG is invalid (TIM4)" +# elif CONFIG_STM32_ADC2_TIMTRIG == 5 +# error "CONFIG_STM32_ADC2_TIMTRIG is invalid (TIM4)" # else -# error "CONFIG_STM32H5_ADC2_TIMTRIG is out of range (TIM4)" +# error "CONFIG_STM32_ADC2_TIMTRIG is out of range (TIM4)" # endif -#elif defined(CONFIG_STM32H5_TIM6_ADC2) -# if CONFIG_STM32H5_ADC2_TIMTRIG == 0 -# error "CONFIG_STM32H5_ADC2_TIMTRIG is invalid (TIM6)" -# elif CONFIG_STM32H5_ADC2_TIMTRIG == 1 -# error "CONFIG_STM32H5_ADC2_TIMTRIG is invalid (TIM6)" -# elif CONFIG_STM32H5_ADC2_TIMTRIG == 2 -# error "CONFIG_STM32H5_ADC2_TIMTRIG is invalid (TIM6)" -# elif CONFIG_STM32H5_ADC2_TIMTRIG == 3 -# error "CONFIG_STM32H5_ADC2_TIMTRIG is invalid (TIM6)" -# elif CONFIG_STM32H5_ADC2_TIMTRIG == 4 +#elif defined(CONFIG_STM32_TIM6_ADC2) +# if CONFIG_STM32_ADC2_TIMTRIG == 0 +# error "CONFIG_STM32_ADC2_TIMTRIG is invalid (TIM6)" +# elif CONFIG_STM32_ADC2_TIMTRIG == 1 +# error "CONFIG_STM32_ADC2_TIMTRIG is invalid (TIM6)" +# elif CONFIG_STM32_ADC2_TIMTRIG == 2 +# error "CONFIG_STM32_ADC2_TIMTRIG is invalid (TIM6)" +# elif CONFIG_STM32_ADC2_TIMTRIG == 3 +# error "CONFIG_STM32_ADC2_TIMTRIG is invalid (TIM6)" +# elif CONFIG_STM32_ADC2_TIMTRIG == 4 # define ADC2_EXTSEL_VALUE ADC_CFGR_EXTSEL_T6TRGO -# elif CONFIG_STM32H5_ADC2_TIMTRIG == 5 -# error "CONFIG_STM32H5_ADC2_TIMTRIG is invalid (TIM6)" +# elif CONFIG_STM32_ADC2_TIMTRIG == 5 +# error "CONFIG_STM32_ADC2_TIMTRIG is invalid (TIM6)" # else -# error "CONFIG_STM32H5_ADC2_TIMTRIG is out of range (TIM6)" +# error "CONFIG_STM32_ADC2_TIMTRIG is out of range (TIM6)" # endif -#elif defined(CONFIG_STM32H5_TIM8_ADC2) -# if CONFIG_STM32H5_ADC2_TIMTRIG == 0 -# error "CONFIG_STM32H5_ADC2_TIMTRIG is invalid (TIM8)" -# elif CONFIG_STM32H5_ADC2_TIMTRIG == 1 -# error "CONFIG_STM32H5_ADC2_TIMTRIG is invalid (TIM8)" -# elif CONFIG_STM32H5_ADC2_TIMTRIG == 2 -# error "CONFIG_STM32H5_ADC2_TIMTRIG is invalid (TIM8)" -# elif CONFIG_STM32H5_ADC2_TIMTRIG == 3 -# error "CONFIG_STM32H5_ADC2_TIMTRIG is invalid (TIM8)" -# elif CONFIG_STM32H5_ADC2_TIMTRIG == 4 +#elif defined(CONFIG_STM32_TIM8_ADC2) +# if CONFIG_STM32_ADC2_TIMTRIG == 0 +# error "CONFIG_STM32_ADC2_TIMTRIG is invalid (TIM8)" +# elif CONFIG_STM32_ADC2_TIMTRIG == 1 +# error "CONFIG_STM32_ADC2_TIMTRIG is invalid (TIM8)" +# elif CONFIG_STM32_ADC2_TIMTRIG == 2 +# error "CONFIG_STM32_ADC2_TIMTRIG is invalid (TIM8)" +# elif CONFIG_STM32_ADC2_TIMTRIG == 3 +# error "CONFIG_STM32_ADC2_TIMTRIG is invalid (TIM8)" +# elif CONFIG_STM32_ADC2_TIMTRIG == 4 # define ADC2_EXTSEL_VALUE ADC_CFGR_EXTSEL_T8TRGO -# elif CONFIG_STM32H5_ADC2_TIMTRIG == 5 +# elif CONFIG_STM32_ADC2_TIMTRIG == 5 # define ADC2_EXTSEL_VALUE ADC_CFGR_EXTSEL_T8TRGO2 # else -# error "CONFIG_STM32H5_ADC2_TIMTRIG is out of range (TIM8)" +# error "CONFIG_STM32_ADC2_TIMTRIG is out of range (TIM8)" # endif -#elif defined(CONFIG_STM32H5_TIM15_ADC2) -# if CONFIG_STM32H5_ADC2_TIMTRIG == 0 -# error "CONFIG_STM32H5_ADC2_TIMTRIG is invalid (TIM15)" -# elif CONFIG_STM32H5_ADC2_TIMTRIG == 1 -# error "CONFIG_STM32H5_ADC2_TIMTRIG is invalid (TIM15)" -# elif CONFIG_STM32H5_ADC2_TIMTRIG == 2 -# error "CONFIG_STM32H5_ADC2_TIMTRIG is invalid (TIM15)" -# elif CONFIG_STM32H5_ADC2_TIMTRIG == 3 -# error "CONFIG_STM32H5_ADC2_TIMTRIG is invalid (TIM15)" -# elif CONFIG_STM32H5_ADC2_TIMTRIG == 4 +#elif defined(CONFIG_STM32_TIM15_ADC2) +# if CONFIG_STM32_ADC2_TIMTRIG == 0 +# error "CONFIG_STM32_ADC2_TIMTRIG is invalid (TIM15)" +# elif CONFIG_STM32_ADC2_TIMTRIG == 1 +# error "CONFIG_STM32_ADC2_TIMTRIG is invalid (TIM15)" +# elif CONFIG_STM32_ADC2_TIMTRIG == 2 +# error "CONFIG_STM32_ADC2_TIMTRIG is invalid (TIM15)" +# elif CONFIG_STM32_ADC2_TIMTRIG == 3 +# error "CONFIG_STM32_ADC2_TIMTRIG is invalid (TIM15)" +# elif CONFIG_STM32_ADC2_TIMTRIG == 4 # define ADC2_EXTSEL_VALUE ADC_CFGR_EXTSEL_T15TRGO -# elif CONFIG_STM32H5_ADC2_TIMTRIG == 5 -# error "CONFIG_STM32H5_ADC2_TIMTRIG is invalid (TIM15)" +# elif CONFIG_STM32_ADC2_TIMTRIG == 5 +# error "CONFIG_STM32_ADC2_TIMTRIG is invalid (TIM15)" # else -# error "CONFIG_STM32H5_ADC2_TIMTRIG is out of range (TIM15)" +# error "CONFIG_STM32_ADC2_TIMTRIG is out of range (TIM15)" # endif #endif @@ -500,7 +500,7 @@ extern "C" #endif /**************************************************************************** - * Name: stm32h5_adc_initialize + * Name: stm32_adc_initialize * * Description: * Initialize the ADC. @@ -516,7 +516,7 @@ extern "C" ****************************************************************************/ struct adc_dev_s; -struct adc_dev_s *stm32h5_adc_initialize(int intf, +struct adc_dev_s *stm32_adc_initialize(int intf, const uint8_t *chanlist, int nchannels); #undef EXTERN @@ -525,5 +525,5 @@ struct adc_dev_s *stm32h5_adc_initialize(int intf, #endif #endif /* __ASSEMBLY__ */ -#endif /* CONFIG_STM32H5_ADC1 || CONFIG_STM32H5_ADC2*/ +#endif /* CONFIG_STM32_ADC1 || CONFIG_STM32_ADC2*/ #endif /* __ARCH_ARM_SRC_STM32H5_STM32_ADC_H */ diff --git a/arch/arm/src/stm32h5/stm32_dbgmcu.h b/arch/arm/src/stm32h5/stm32_dbgmcu.h index 48d61c970b47b..746fe869c2c25 100644 --- a/arch/arm/src/stm32h5/stm32_dbgmcu.h +++ b/arch/arm/src/stm32h5/stm32_dbgmcu.h @@ -31,7 +31,7 @@ #include "chip.h" -#if defined(CONFIG_STM32H5_STM32H5XXXX) +#if defined(CONFIG_STM32_STM32H5XXXX) # include "hardware/stm32_dbgmcu.h" #else # error "Unsupported STM32H5 chip" diff --git a/arch/arm/src/stm32h5/stm32_dma.c b/arch/arm/src/stm32h5/stm32_dma.c index 3f53a85a8dd9b..67465bdb296ac 100644 --- a/arch/arm/src/stm32h5/stm32_dma.c +++ b/arch/arm/src/stm32h5/stm32_dma.c @@ -118,7 +118,7 @@ static int gpdma_dmainterrupt(int irq, void *context, void *arg); * Private Data ****************************************************************************/ -#ifdef CONFIG_STM32H5_DMA1 +#ifdef CONFIG_STM32_DMA1 static struct gpdma_ch_s g_chan[] = { { @@ -150,7 +150,7 @@ static struct gpdma_ch_s g_chan[] = .base = STM32_DMA1_BASE + CH_BASE_OFFSET(3) }, #endif -#ifdef CONFIG_STM32H5_DMA2 +#ifdef CONFIG_STM32_DMA2 { .dma_instance = 2, .channel = 0, @@ -703,7 +703,7 @@ size_t stm32_dmaresidual(DMA_HANDLE handle) return (size_t)(br1 & GPDMA_CXBR1_BNDT_MASK); } -#ifdef CONFIG_STM32H5_DMACAPABLE +#ifdef CONFIG_STM32_DMACAPABLE /**************************************************************************** * Name: stm32_dmacapable * diff --git a/arch/arm/src/stm32h5/stm32_dma.h b/arch/arm/src/stm32h5/stm32_dma.h index 6c94150745748..a9b336d6f8144 100644 --- a/arch/arm/src/stm32h5/stm32_dma.h +++ b/arch/arm/src/stm32h5/stm32_dma.h @@ -39,9 +39,9 @@ # undef CONFIG_DEBUG_DMA_INFO #endif -#ifdef CONFIG_STM32H5_DMACAPABLE -# error "CONFIG_STM32H5_DMACAPABLE not yet implemented." -# undef CONFIG_STM32H5_DMACAPABLE +#ifdef CONFIG_STM32_DMACAPABLE +# error "CONFIG_STM32_DMACAPABLE not yet implemented." +# undef CONFIG_STM32_DMACAPABLE #endif /**************************************************************************** @@ -319,7 +319,7 @@ size_t stm32_dmaresidual(DMA_HANDLE handle); * ****************************************************************************/ -#ifdef CONFIG_STM32H5_DMACAPABLE +#ifdef CONFIG_STM32_DMACAPABLE bool stm32_dmacapable(DMA_HANDLE handle, struct stm32_gpdma_cfg_s *cfg); #else # define stm32_dmacapable(handle, cfg) (true) diff --git a/arch/arm/src/stm32h5/stm32_dts.c b/arch/arm/src/stm32h5/stm32_dts.c index efcf5da4795f5..b6d5067869fb5 100644 --- a/arch/arm/src/stm32h5/stm32_dts.c +++ b/arch/arm/src/stm32h5/stm32_dts.c @@ -59,7 +59,7 @@ static int stm32_dts_set_interval (struct sensor_lowerhalf_s *lower, struct file *filep, uint32_t *period_us); -#if CONFIG_STM32H5_DTS_TRIGGER == 0 +#if CONFIG_STM32_DTS_TRIGGER == 0 static ssize_t stm32_dts_fetch (struct sensor_lowerhalf_s *lower, struct file *filep, char *buffer, size_t buflen); @@ -75,7 +75,7 @@ static int stm32_dts_isr (int irq, void *context, void *arg); * Pre-processor Definitions ****************************************************************************/ -#if CONFIG_STM32H5_DTS_TRIGGER != 0 +#if CONFIG_STM32_DTS_TRIGGER != 0 # error "Hardware triggers not implemented. Need LP Timers first." #endif @@ -112,7 +112,7 @@ static const struct sensor_ops_s g_dts_ops = .activate = stm32_dts_activate, .set_interval = stm32_dts_set_interval, .batch = NULL, -#if CONFIG_STM32H5_DTS_TRIGGER == 0 +#if CONFIG_STM32_DTS_TRIGGER == 0 .fetch = stm32_dts_fetch, #else .fetch = NULL, @@ -230,7 +230,7 @@ static void dts_configure_cfgr1(void) { /* Compute PCLK prescaler <= 1MHz */ -#if !defined(CONFIG_STM32H5_DTS_REFCLK_LSE) +#if !defined(CONFIG_STM32_DTS_REFCLK_LSE) uint32_t div = (STM32_PCLK1_FREQUENCY + 1000000 - 1) / 1000000; if (div > 127) @@ -245,13 +245,13 @@ static void dts_configure_cfgr1(void) uint32_t cfgr1 = DTS_CFGR1_TS1_EN - | DTS_CFGR1_TS1_SMP_TIME(CONFIG_STM32H5_DTS_SMP_TIME) -#if !defined(CONFIG_STM32H5_DTS_REFCLK_LSE) + | DTS_CFGR1_TS1_SMP_TIME(CONFIG_STM32_DTS_SMP_TIME) +#if !defined(CONFIG_STM32_DTS_REFCLK_LSE) | DTS_CFGR1_HSREF_CLK_DIV_RATIO(div) #else | DTS_CFGR1_REFCLK_SEL #endif - | DTS_CFGR1_TS1_INTRIG(CONFIG_STM32H5_DTS_TRIGGER); + | DTS_CFGR1_TS1_INTRIG(CONFIG_STM32_DTS_TRIGGER); putreg32(cfgr1, STM32_DTS_CFGR1); } @@ -295,7 +295,7 @@ static void dts_get_cfg_data(void) { uint32_t cfgr1 = getreg32(STM32_DTS_CFGR1); -#if defined(CONFIG_STM32H5_DTS_REFCLK_LSE) +#if defined(CONFIG_STM32_DTS_REFCLK_LSE) g_dts_cfg.lse = true; #else g_dts_cfg.lse = false; @@ -324,23 +324,23 @@ static void dts_configure_interrupts(struct sensor_lowerhalf_s *lower) { uint32_t itenr = 0; -#ifdef CONFIG_STM32H5_DTS_ITEN_ITEF +#ifdef CONFIG_STM32_DTS_ITEN_ITEF itenr |= DTS_ITENR_ITEEN; #endif -#ifdef CONFIG_STM32H5_DTS_ITEN_ITLF +#ifdef CONFIG_STM32_DTS_ITEN_ITLF itenr |= DTS_ITENR_ITLEN; #endif -#ifdef CONFIG_STM32H5_DTS_ITEN_ITHF +#ifdef CONFIG_STM32_DTS_ITEN_ITHF itenr |= DTS_ITENR_ITHEN; #endif -#ifdef CONFIG_STM32H5_DTS_AITEN_AITEF +#ifdef CONFIG_STM32_DTS_AITEN_AITEF itenr |= DTS_ITENR_AITEEN; #endif -#ifdef CONFIG_STM32H5_DTS_AITEN_AITLF +#ifdef CONFIG_STM32_DTS_AITEN_AITLF itenr |= DTS_ITENR_AITLEN; #endif -#ifdef CONFIG_STM32H5_DTS_AITEN_AITHF +#ifdef CONFIG_STM32_DTS_AITEN_AITHF itenr |= DTS_ITENR_AITHEN; #endif @@ -392,7 +392,7 @@ static int stm32_dts_activate(struct sensor_lowerhalf_s *lower, return OK; } -#if CONFIG_STM32H5_DTS_TRIGGER == 0 +#if CONFIG_STM32_DTS_TRIGGER == 0 /**************************************************************************** * Name: stm32_dts_fetch * @@ -538,7 +538,7 @@ static int stm32_dts_isr(int irq, void *context, void *arg) * Name: stm32_dts_register ****************************************************************************/ -int stm32h5_dts_register(int devno) +int stm32_dts_register(int devno) { int ret; diff --git a/arch/arm/src/stm32h5/stm32_dts.h b/arch/arm/src/stm32h5/stm32_dts.h index 67e796699a992..560ef39cfdb83 100644 --- a/arch/arm/src/stm32h5/stm32_dts.h +++ b/arch/arm/src/stm32h5/stm32_dts.h @@ -65,7 +65,7 @@ extern "C" #define EXTERN extern #endif -int stm32h5_dts_register(int devno); +int stm32_dts_register(int devno); #undef EXTERN #if defined(__cplusplus) diff --git a/arch/arm/src/stm32h5/stm32_ethernet.c b/arch/arm/src/stm32h5/stm32_ethernet.c index 4dbcee14fb69b..0ef2f2eb4b9da 100644 --- a/arch/arm/src/stm32h5/stm32_ethernet.c +++ b/arch/arm/src/stm32h5/stm32_ethernet.c @@ -66,12 +66,12 @@ #include -/* STM32H5_NETHERNET determines the number of physical interfaces that can - * be supported by the hardware. CONFIG_STM32H5_ETHMAC will defined if +/* STM32_NETHERNET determines the number of physical interfaces that can + * be supported by the hardware. CONFIG_STM32_ETHMAC will defined if * any STM32H5 Ethernet support is enabled in the configuration. */ -#if STM32H5_NETHERNET > 0 && defined(CONFIG_STM32H5_ETHMAC) +#if STM32_NETHERNET > 0 && defined(CONFIG_STM32_ETHMAC) /**************************************************************************** * Pre-processor Definitions @@ -79,7 +79,7 @@ /* Configuration ************************************************************/ -#if STM32H5_NETHERNET > 1 +#if STM32_NETHERNET > 1 # error "Logic to support multiple Ethernet interfaces is incomplete" #endif @@ -93,85 +93,85 @@ /* Select work queue */ -# if defined(CONFIG_STM32H5_ETHMAC_HPWORK) +# if defined(CONFIG_STM32_ETHMAC_HPWORK) # define ETHWORK HPWORK -# elif defined(CONFIG_STM32H5_ETHMAC_LPWORK) +# elif defined(CONFIG_STM32_ETHMAC_LPWORK) # define ETHWORK LPWORK # else # define ETHWORK LPWORK # endif #endif -#ifndef CONFIG_STM32H5_PHYADDR -# error "CONFIG_STM32H5_PHYADDR must be defined in the NuttX configuration" +#ifndef CONFIG_STM32_PHYADDR +# error "CONFIG_STM32_PHYADDR must be defined in the NuttX configuration" #endif -#if !defined(CONFIG_STM32H5_MII) && !defined(CONFIG_STM32H5_RMII) -# warning "Neither CONFIG_STM32H5_MII nor CONFIG_STM32H5_RMII defined" +#if !defined(CONFIG_STM32_MII) && !defined(CONFIG_STM32_RMII) +# warning "Neither CONFIG_STM32_MII nor CONFIG_STM32_RMII defined" #endif -#if defined(CONFIG_STM32H5_MII) && defined(CONFIG_STM32H5_RMII) -# error "Both CONFIG_STM32H5_MII and CONFIG_STM32H5_RMII defined" +#if defined(CONFIG_STM32_MII) && defined(CONFIG_STM32_RMII) +# error "Both CONFIG_STM32_MII and CONFIG_STM32_RMII defined" #endif -#ifdef CONFIG_STM32H5_MII -# if !defined(CONFIG_STM32H5_MII_MCO1) && !defined(CONFIG_STM32H5_MII_MCO2) && \ - !defined(CONFIG_STM32H5_MII_EXTCLK) -# warning "Neither CONFIG_STM32H5_MII_MCO1, CONFIG_STM32H5_MII_MCO2, nor CONFIG_STM32H5_MII_EXTCLK defined" +#ifdef CONFIG_STM32_MII +# if !defined(CONFIG_STM32_MII_MCO1) && !defined(CONFIG_STM32_MII_MCO2) && \ + !defined(CONFIG_STM32_MII_EXTCLK) +# warning "Neither CONFIG_STM32_MII_MCO1, CONFIG_STM32_MII_MCO2, nor CONFIG_STM32_MII_EXTCLK defined" # endif -# if defined(CONFIG_STM32H5_MII_MCO1) && defined(CONFIG_STM32H5_MII_MCO2) -# error "Both CONFIG_STM32H5_MII_MCO1 and CONFIG_STM32H5_MII_MCO2 defined" +# if defined(CONFIG_STM32_MII_MCO1) && defined(CONFIG_STM32_MII_MCO2) +# error "Both CONFIG_STM32_MII_MCO1 and CONFIG_STM32_MII_MCO2 defined" # endif #endif -#ifdef CONFIG_STM32H5_RMII -# if !defined(CONFIG_STM32H5_RMII_MCO1) && !defined(CONFIG_STM32H5_RMII_MCO2) && \ - !defined(CONFIG_STM32H5_RMII_EXTCLK) -# warning "Neither CONFIG_STM32H5_RMII_MCO1, CONFIG_STM32H5_RMII_MCO2, nor CONFIG_STM32H5_RMII_EXTCLK defined" +#ifdef CONFIG_STM32_RMII +# if !defined(CONFIG_STM32_RMII_MCO1) && !defined(CONFIG_STM32_RMII_MCO2) && \ + !defined(CONFIG_STM32_RMII_EXTCLK) +# warning "Neither CONFIG_STM32_RMII_MCO1, CONFIG_STM32_RMII_MCO2, nor CONFIG_STM32_RMII_EXTCLK defined" # endif -# if defined(CONFIG_STM32H5_RMII_MCO1) && defined(CONFIG_STM32H5_RMII_MCO2) -# error "Both CONFIG_STM32H5_RMII_MCO1 and CONFIG_STM32H5_RMII_MCO2 defined" +# if defined(CONFIG_STM32_RMII_MCO1) && defined(CONFIG_STM32_RMII_MCO2) +# error "Both CONFIG_STM32_RMII_MCO1 and CONFIG_STM32_RMII_MCO2 defined" # endif #endif -#ifdef CONFIG_STM32H5_AUTONEG -# ifndef CONFIG_STM32H5_PHYSR -# error "CONFIG_STM32H5_PHYSR must be defined in the NuttX configuration" +#ifdef CONFIG_STM32_AUTONEG +# ifndef CONFIG_STM32_PHYSR +# error "CONFIG_STM32_PHYSR must be defined in the NuttX configuration" # endif -# ifdef CONFIG_STM32H5_PHYSR_ALTCONFIG -# ifndef CONFIG_STM32H5_PHYSR_ALTMODE -# error "CONFIG_STM32H5_PHYSR_ALTMODE must be defined in the NuttX configuration" +# ifdef CONFIG_STM32_PHYSR_ALTCONFIG +# ifndef CONFIG_STM32_PHYSR_ALTMODE +# error "CONFIG_STM32_PHYSR_ALTMODE must be defined in the NuttX configuration" # endif -# ifndef CONFIG_STM32H5_PHYSR_10HD -# error "CONFIG_STM32H5_PHYSR_10HD must be defined in the NuttX configuration" +# ifndef CONFIG_STM32_PHYSR_10HD +# error "CONFIG_STM32_PHYSR_10HD must be defined in the NuttX configuration" # endif -# ifndef CONFIG_STM32H5_PHYSR_100HD -# error "CONFIG_STM32H5_PHYSR_100HD must be defined in the NuttX configuration" +# ifndef CONFIG_STM32_PHYSR_100HD +# error "CONFIG_STM32_PHYSR_100HD must be defined in the NuttX configuration" # endif -# ifndef CONFIG_STM32H5_PHYSR_10FD -# error "CONFIG_STM32H5_PHYSR_10FD must be defined in the NuttX configuration" +# ifndef CONFIG_STM32_PHYSR_10FD +# error "CONFIG_STM32_PHYSR_10FD must be defined in the NuttX configuration" # endif -# ifndef CONFIG_STM32H5_PHYSR_100FD -# error "CONFIG_STM32H5_PHYSR_100FD must be defined in the NuttX configuration" +# ifndef CONFIG_STM32_PHYSR_100FD +# error "CONFIG_STM32_PHYSR_100FD must be defined in the NuttX configuration" # endif # else -# ifndef CONFIG_STM32H5_PHYSR_SPEED -# error "CONFIG_STM32H5_PHYSR_SPEED must be defined in the NuttX configuration" +# ifndef CONFIG_STM32_PHYSR_SPEED +# error "CONFIG_STM32_PHYSR_SPEED must be defined in the NuttX configuration" # endif -# ifndef CONFIG_STM32H5_PHYSR_100MBPS -# error "CONFIG_STM32H5_PHYSR_100MBPS must be defined in the NuttX configuration" +# ifndef CONFIG_STM32_PHYSR_100MBPS +# error "CONFIG_STM32_PHYSR_100MBPS must be defined in the NuttX configuration" # endif -# ifndef CONFIG_STM32H5_PHYSR_MODE -# error "CONFIG_STM32H5_PHYSR_MODE must be defined in the NuttX configuration" +# ifndef CONFIG_STM32_PHYSR_MODE +# error "CONFIG_STM32_PHYSR_MODE must be defined in the NuttX configuration" # endif -# ifndef CONFIG_STM32H5_PHYSR_FULLDUPLEX -# error "CONFIG_STM32H5_PHYSR_FULLDUPLEX must be defined in the NuttX configuration" +# ifndef CONFIG_STM32_PHYSR_FULLDUPLEX +# error "CONFIG_STM32_PHYSR_FULLDUPLEX must be defined in the NuttX configuration" # endif # endif #endif -#ifdef CONFIG_STM32H5_ETH_PTP -# warning "CONFIG_STM32H5_ETH_PTP is not yet supported" +#ifdef CONFIG_STM32_ETH_PTP +# warning "CONFIG_STM32_ETH_PTP is not yet supported" #endif /* Add 4 to the configured buffer size to account for the 2 byte checksum @@ -182,8 +182,8 @@ #define OPTIMAL_ETH_BUFSIZE ((CONFIG_NET_ETH_PKTSIZE + 4 + 15) & ~15) -#ifdef CONFIG_STM32H5_ETH_BUFSIZE -# define ETH_BUFSIZE CONFIG_STM32H5_ETH_BUFSIZE +#ifdef CONFIG_STM32_ETH_BUFSIZE +# define ETH_BUFSIZE CONFIG_STM32_ETH_BUFSIZE #else # define ETH_BUFSIZE OPTIMAL_ETH_BUFSIZE #endif @@ -200,16 +200,16 @@ # warning "You are using an incomplete/untested configuration" #endif -#ifndef CONFIG_STM32H5_ETH_NRXDESC -# define CONFIG_STM32H5_ETH_NRXDESC 8 +#ifndef CONFIG_STM32_ETH_NRXDESC +# define CONFIG_STM32_ETH_NRXDESC 8 #endif -#ifndef CONFIG_STM32H5_ETH_NTXDESC -# define CONFIG_STM32H5_ETH_NTXDESC 4 +#ifndef CONFIG_STM32_ETH_NTXDESC +# define CONFIG_STM32_ETH_NTXDESC 4 #endif /* We need at least one more free buffer than transmit buffers */ -#define STM32_ETH_NFREEBUFFERS (CONFIG_STM32H5_ETH_NTXDESC+1) +#define STM32_ETH_NFREEBUFFERS (CONFIG_STM32_ETH_NTXDESC+1) /* Buffers used for DMA access must begin on an address aligned with the * D-Cache line and must be an even multiple of the D-Cache line size. @@ -227,21 +227,21 @@ #define DESC_PADSIZE DMA_ALIGN_UP(DESC_SIZE) #define ALIGNED_BUFSIZE DMA_ALIGN_UP(ETH_BUFSIZE) -#define RXTABLE_SIZE (STM32H5_NETHERNET * CONFIG_STM32H5_ETH_NRXDESC) -#define TXTABLE_SIZE (STM32H5_NETHERNET * CONFIG_STM32H5_ETH_NTXDESC) +#define RXTABLE_SIZE (STM32_NETHERNET * CONFIG_STM32_ETH_NRXDESC) +#define TXTABLE_SIZE (STM32_NETHERNET * CONFIG_STM32_ETH_NTXDESC) -#define RXBUFFER_SIZE (CONFIG_STM32H5_ETH_NRXDESC * ALIGNED_BUFSIZE) -#define RXBUFFER_ALLOC (STM32H5_NETHERNET * RXBUFFER_SIZE) +#define RXBUFFER_SIZE (CONFIG_STM32_ETH_NRXDESC * ALIGNED_BUFSIZE) +#define RXBUFFER_ALLOC (STM32_NETHERNET * RXBUFFER_SIZE) #define TXBUFFER_SIZE (STM32_ETH_NFREEBUFFERS * ALIGNED_BUFSIZE) -#define TXBUFFER_ALLOC (STM32H5_NETHERNET * TXBUFFER_SIZE) +#define TXBUFFER_ALLOC (STM32_NETHERNET * TXBUFFER_SIZE) /* Extremely detailed register debug that you would normally never want * enabled. */ #ifndef CONFIG_DEBUG_NET_INFO -# undef CONFIG_STM32H5_ETHMAC_REGDEBUG +# undef CONFIG_STM32_ETHMAC_REGDEBUG #endif /* Clocking *****************************************************************/ @@ -332,7 +332,7 @@ * ETH_MACCR_ACS Automatic pad/CRC stripping 0 (disabled) * ETH_MACCR_DR Retry disable 1 (disabled) * ETH_MACCR_IPC IPv4 checksum offload - * Depends on CONFIG_STM32H5_ETH_HWCHECKSUM + * Depends on CONFIG_STM32_ETH_HWCHECKSUM * ETH_MACCR_LM Loopback mode 0 (disabled) * ETH_MACCR_DO Receive own disable 0 (enabled) * ETH_MACCR_DCRS Carrier sense disable 0 (enabled) @@ -347,7 +347,7 @@ * ETH_MACCR_FES Fast Ethernet speed Depends on priv->mbps100 */ -#ifdef CONFIG_STM32H5_ETH_HWCHECKSUM +#ifdef CONFIG_STM32_ETH_HWCHECKSUM # define MACCR_SET_BITS \ (ETH_MACCR_BL_10 | ETH_MACCR_DR | ETH_MACCR_IPC | ETH_MACCR_IPG(96)) #else @@ -653,7 +653,7 @@ aligned_data(ARMV8M_DCACHE_LINESIZE); /* These are the pre-allocated Ethernet device structures */ -static struct stm32_ethmac_s g_stm32ethmac[STM32H5_NETHERNET]; +static struct stm32_ethmac_s g_stm32ethmac[STM32_NETHERNET]; /**************************************************************************** * Private Function Prototypes @@ -661,7 +661,7 @@ static struct stm32_ethmac_s g_stm32ethmac[STM32H5_NETHERNET]; /* Register operations ******************************************************/ -#ifdef CONFIG_STM32H5_ETHMAC_REGDEBUG +#ifdef CONFIG_STM32_ETHMAC_REGDEBUG static uint32_t stm32_getreg(uint32_t addr); static void stm32_putreg(uint32_t val, uint32_t addr); static void stm32_checksetup(void); @@ -733,7 +733,7 @@ static void stm32_rxdescinit(struct stm32_ethmac_s *priv, union stm32_desc_u *rxtable, uint8_t *rxbuffer); /* PHY Initialization */ -#ifndef CONFIG_STM32H5_NO_PHY +#ifndef CONFIG_STM32_NO_PHY #if defined(CONFIG_NETDEV_PHY_IOCTL) && defined(CONFIG_ARCH_PHY_INTERRUPT) static int stm32_phyintenable(struct stm32_ethmac_s *priv); #endif @@ -745,17 +745,17 @@ static int stm32_phywrite(uint16_t phydevaddr, uint16_t phyregaddr, static inline int stm32_dm9161(struct stm32_ethmac_s *priv); #endif static int stm32_phyinit(struct stm32_ethmac_s *priv); -#ifdef CONFIG_STM32H5_ETHMAC_REGDEBUG +#ifdef CONFIG_STM32_ETHMAC_REGDEBUG static void stm32_phyregdump(void); #endif #endif /* MAC/DMA Initialization */ -#ifdef CONFIG_STM32H5_MII +#ifdef CONFIG_STM32_MII static inline void stm32_selectmii(void); #endif -#ifdef CONFIG_STM32H5_RMII +#ifdef CONFIG_STM32_RMII static inline void stm32_selectrmii(void); #endif static inline void stm32_ethgpioconfig(struct stm32_ethmac_s *priv); @@ -785,7 +785,7 @@ static int stm32_ethconfig(struct stm32_ethmac_s *priv); * ****************************************************************************/ -#ifdef CONFIG_STM32H5_ETHMAC_REGDEBUG +#ifdef CONFIG_STM32_ETHMAC_REGDEBUG static uint32_t stm32_getreg(uint32_t addr) { static uint32_t prevaddr = 0; @@ -857,7 +857,7 @@ static uint32_t stm32_getreg(uint32_t addr) * ****************************************************************************/ -#ifdef CONFIG_STM32H5_ETHMAC_REGDEBUG +#ifdef CONFIG_STM32_ETHMAC_REGDEBUG static void stm32_putreg(uint32_t val, uint32_t addr) { /* Show the register value being written */ @@ -884,7 +884,7 @@ static void stm32_putreg(uint32_t val, uint32_t addr) * ****************************************************************************/ -#ifdef CONFIG_STM32H5_ETHMAC_REGDEBUG +#ifdef CONFIG_STM32_ETHMAC_REGDEBUG static void stm32_checksetup(void) { } @@ -1026,10 +1026,10 @@ static struct eth_desc_s *stm32_get_next_txdesc(struct stm32_ethmac_s *priv, struct eth_desc_s * curr) { union stm32_desc_u *first = - &g_txtable[priv->intf * CONFIG_STM32H5_ETH_NTXDESC]; + &g_txtable[priv->intf * CONFIG_STM32_ETH_NTXDESC]; union stm32_desc_u *last = - &g_txtable[priv->intf * CONFIG_STM32H5_ETH_NTXDESC + - CONFIG_STM32H5_ETH_NTXDESC - 1]; + &g_txtable[priv->intf * CONFIG_STM32_ETH_NTXDESC + + CONFIG_STM32_ETH_NTXDESC - 1]; union stm32_desc_u *next = ((union stm32_desc_u *)curr) + 1; if (next > last) @@ -1113,7 +1113,7 @@ static int stm32_transmit(struct stm32_ethmac_s *priv) * pseudo-header checksum will be computed. */ -#ifdef CONFIG_STM32H5_ETH_HWCHECKSUM +#ifdef CONFIG_STM32_ETH_HWCHECKSUM txdesc->des3 = ETH_TDES3_RD_FD | ETH_TDES3_RD_CIC_ALL; #else txdesc->des3 = ETH_TDES3_RD_FD; @@ -1207,7 +1207,7 @@ static int stm32_transmit(struct stm32_ethmac_s *priv) * pseudo-header checksum will be computed. */ -#ifdef CONFIG_STM32H5_ETH_HWCHECKSUM +#ifdef CONFIG_STM32_ETH_HWCHECKSUM txdesc->des3 = (ETH_TDES3_RD_OWN | ETH_TDES3_RD_LD | ETH_TDES3_RD_FD | ETH_TDES3_RD_CIC_ALL); #else @@ -1259,7 +1259,7 @@ static int stm32_transmit(struct stm32_ethmac_s *priv) * stoppable transmit events. */ - if (priv->inflight >= CONFIG_STM32H5_ETH_NTXDESC) + if (priv->inflight >= CONFIG_STM32_ETH_NTXDESC) { stm32_disableint(priv, ETH_DMACIER_RIE); } @@ -1325,7 +1325,7 @@ static int stm32_txpoll(struct net_driver_s *dev) * In a race condition, ETH_TDES3_OWN may be cleared BUT still * not available because stm32_freeframe() has not yet run. If * stm32_freeframe() has run, the buffer1 pointer (tdes2) will be - * nullified (and inflight should be < CONFIG_STM32H5_ETH_NTXDESC). + * nullified (and inflight should be < CONFIG_STM32_ETH_NTXDESC). */ if ((priv->txhead->des3 & ETH_TDES3_RD_OWN) != 0 || @@ -1398,7 +1398,7 @@ static void stm32_dopoll(struct stm32_ethmac_s *priv) * In a race condition, ETH_TDES3_RD_OWN may be cleared BUT still * not available because stm32_freeframe() has not yet run. If * stm32_freeframe() has run, the buffer1 pointer (des0) will be - * nullified (and inflight should be < CONFIG_STM32H5_ETH_NTXDESC). + * nullified (and inflight should be < CONFIG_STM32_ETH_NTXDESC). */ if ((priv->txhead->des3 & ETH_TDES3_RD_OWN) == 0 && @@ -1524,10 +1524,10 @@ static struct eth_desc_s *stm32_get_next_rxdesc(struct stm32_ethmac_s *priv, struct eth_desc_s * curr) { union stm32_desc_u *first = - &g_rxtable[priv->intf * CONFIG_STM32H5_ETH_NRXDESC]; + &g_rxtable[priv->intf * CONFIG_STM32_ETH_NRXDESC]; union stm32_desc_u *last = - &g_rxtable[priv->intf * CONFIG_STM32H5_ETH_NRXDESC + - CONFIG_STM32H5_ETH_NRXDESC - 1]; + &g_rxtable[priv->intf * CONFIG_STM32_ETH_NRXDESC + + CONFIG_STM32_ETH_NRXDESC - 1]; union stm32_desc_u *next = ((union stm32_desc_u *)curr) + 1; if (next > last) @@ -1678,8 +1678,8 @@ static int stm32_recvframe(struct stm32_ethmac_s *priv) for (i = 0; (rxdesc->des3 & ETH_RDES3_WB_OWN) == 0 && - i < CONFIG_STM32H5_ETH_NRXDESC && - priv->inflight < CONFIG_STM32H5_ETH_NTXDESC; + i < CONFIG_STM32_ETH_NRXDESC && + priv->inflight < CONFIG_STM32_ETH_NTXDESC; i++) { /* Check if this is a normal descriptor */ @@ -1724,7 +1724,7 @@ static int stm32_recvframe(struct stm32_ethmac_s *priv) ninfo("rxhead: %p rxcurr: %p segments: %d\n", priv->rxhead, priv->rxcurr, priv->segments); -#ifdef CONFIG_STM32H5_ETH_HWCHECKSUM +#ifdef CONFIG_STM32_ETH_HWCHECKSUM /* Check if any errors are reported in the frame. * If hardware checksum is enabled, check if: * - RDES1 is valid @@ -2796,7 +2796,7 @@ static void stm32_txdescinit(struct stm32_ethmac_s *priv, /* Initialize each TX descriptor */ - for (i = 0; i < CONFIG_STM32H5_ETH_NTXDESC; i++) + for (i = 0; i < CONFIG_STM32_ETH_NTXDESC; i++) { txdesc = &txtable[i].desc; @@ -2832,7 +2832,7 @@ static void stm32_txdescinit(struct stm32_ethmac_s *priv, * properly but the DMACCATXDR advances to outside the descriptor ring */ - stm32_putreg(CONFIG_STM32H5_ETH_NTXDESC - 1, STM32_ETH_DMACTXRLR); + stm32_putreg(CONFIG_STM32_ETH_NTXDESC - 1, STM32_ETH_DMACTXRLR); /* Set Transmit Descriptor List Address Register */ @@ -2885,7 +2885,7 @@ static void stm32_rxdescinit(struct stm32_ethmac_s *priv, /* Initialize each RX descriptor */ - for (i = 0; i < CONFIG_STM32H5_ETH_NRXDESC; i++) + for (i = 0; i < CONFIG_STM32_ETH_NRXDESC; i++) { rxdesc = &rxtable[i].desc; @@ -2918,7 +2918,7 @@ static void stm32_rxdescinit(struct stm32_ethmac_s *priv, * properly but the DMACCARXDR advances to outside the descriptor ring */ - stm32_putreg(CONFIG_STM32H5_ETH_NRXDESC - 1, STM32_ETH_DMACRXRLR); + stm32_putreg(CONFIG_STM32_ETH_NRXDESC - 1, STM32_ETH_DMACRXRLR); /* Set Receive Descriptor List Address Register */ @@ -2926,7 +2926,7 @@ static void stm32_rxdescinit(struct stm32_ethmac_s *priv, /* Set Receive Descriptor Tail pointer Address */ - stm32_putreg((uint32_t)&rxtable[CONFIG_STM32H5_ETH_NRXDESC - 1].desc, + stm32_putreg((uint32_t)&rxtable[CONFIG_STM32_ETH_NRXDESC - 1].desc, STM32_ETH_DMACRXDTPR); } @@ -2962,7 +2962,7 @@ static void stm32_rxdescinit(struct stm32_ethmac_s *priv, #ifdef CONFIG_NETDEV_PHY_IOCTL static int stm32_ioctl(struct net_driver_s *dev, int cmd, unsigned long arg) { -#ifndef CONFIG_STM32H5_NO_PHY +#ifndef CONFIG_STM32_NO_PHY #ifdef CONFIG_ARCH_PHY_INTERRUPT struct stm32_ethmac_s *priv = (struct stm32_ethmac_s *)dev->d_private; #endif @@ -2992,7 +2992,7 @@ static int stm32_ioctl(struct net_driver_s *dev, int cmd, unsigned long arg) { struct mii_ioctl_data_s *req = (struct mii_ioctl_data_s *)((uintptr_t)arg); - req->phy_id = CONFIG_STM32H5_PHYADDR; + req->phy_id = CONFIG_STM32_PHYADDR; ret = OK; } break; @@ -3026,7 +3026,7 @@ static int stm32_ioctl(struct net_driver_s *dev, int cmd, unsigned long arg) } #endif /* CONFIG_NETDEV_PHY_IOCTL */ -#ifndef CONFIG_STM32H5_NO_PHY +#ifndef CONFIG_STM32_NO_PHY /**************************************************************************** * Function: stm32_phyintenable * @@ -3224,7 +3224,7 @@ static inline int stm32_dm9161(struct stm32_ethmac_s *priv) * indication that check if the DM9161 PHY CHIP is not ready. */ - ret = stm32_phyread(CONFIG_STM32H5_PHYADDR, MII_PHYID1, &phyval); + ret = stm32_phyread(CONFIG_STM32_PHYADDR, MII_PHYID1, &phyval); if (ret < 0) { nerr("ERROR: Failed to read the PHY ID1: %d\n", ret); @@ -3246,7 +3246,7 @@ static inline int stm32_dm9161(struct stm32_ethmac_s *priv) * Register 16 */ - ret = stm32_phyread(CONFIG_STM32H5_PHYADDR, 16, &phyval); + ret = stm32_phyread(CONFIG_STM32_PHYADDR, 16, &phyval); if (ret < 0) { nerr("ERROR: Failed to read the PHY Register 0x10: %d\n", ret); @@ -3280,7 +3280,7 @@ static inline int stm32_dm9161(struct stm32_ethmac_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32H5_ETHMAC_REGDEBUG +#ifdef CONFIG_STM32_ETHMAC_REGDEBUG static void stm32_phyregdump() { uint16_t phyval; @@ -3289,7 +3289,7 @@ static void stm32_phyregdump() for (i = 0; i < 0x20; i++) { - ret = stm32_phyread(CONFIG_STM32H5_PHYADDR, i, &phyval); + ret = stm32_phyread(CONFIG_STM32_PHYADDR, i, &phyval); if (ret < 0) { nerr("ERROR: Failed to read reg: 0%2x\n", i); @@ -3320,7 +3320,7 @@ static void stm32_phyregdump() static int stm32_phyinit(struct stm32_ethmac_s *priv) { -#ifdef CONFIG_STM32H5_AUTONEG +#ifdef CONFIG_STM32_AUTONEG volatile uint32_t timeout; #endif uint32_t regval; @@ -3342,7 +3342,7 @@ static int stm32_phyinit(struct stm32_ethmac_s *priv) /* Put the PHY in reset mode */ - ret = stm32_phywrite(CONFIG_STM32H5_PHYADDR, MII_MCR, MII_MCR_RESET, + ret = stm32_phywrite(CONFIG_STM32_PHYADDR, MII_MCR, MII_MCR_RESET, MII_MCR_RESET); if (ret < 0) { @@ -3355,7 +3355,7 @@ static int stm32_phyinit(struct stm32_ethmac_s *priv) { up_mdelay(10); to -= 10; - ret = stm32_phyread(CONFIG_STM32H5_PHYADDR, MII_MCR, &phyval); + ret = stm32_phyread(CONFIG_STM32_PHYADDR, MII_MCR, &phyval); } while (phyval & MII_MCR_RESET && to > 0); @@ -3369,7 +3369,7 @@ static int stm32_phyinit(struct stm32_ethmac_s *priv) ninfo("Phy reset in %d ms\n", PHY_RESET_DELAY - to); } -#ifdef CONFIG_STM32H5_ETHMAC_REGDEBUG +#ifdef CONFIG_STM32_ETHMAC_REGDEBUG stm32_phyregdump(); #endif @@ -3385,12 +3385,12 @@ static int stm32_phyinit(struct stm32_ethmac_s *priv) /* Perform auto-negotiation if so configured */ -#ifdef CONFIG_STM32H5_AUTONEG +#ifdef CONFIG_STM32_AUTONEG /* Wait for link status */ for (timeout = 0; timeout < PHY_RETRY_TIMEOUT; timeout++) { - ret = stm32_phyread(CONFIG_STM32H5_PHYADDR, MII_MSR, &phyval); + ret = stm32_phyread(CONFIG_STM32_PHYADDR, MII_MSR, &phyval); if (ret < 0) { nerr("ERROR: Failed to read the PHY MSR: %d\n", ret); @@ -3412,7 +3412,7 @@ static int stm32_phyinit(struct stm32_ethmac_s *priv) /* Enable auto-negotiation */ - ret = stm32_phywrite(CONFIG_STM32H5_PHYADDR, MII_MCR, MII_MCR_ANENABLE, + ret = stm32_phywrite(CONFIG_STM32_PHYADDR, MII_MCR, MII_MCR_ANENABLE, MII_MCR_ANENABLE); if (ret < 0) { @@ -3424,7 +3424,7 @@ static int stm32_phyinit(struct stm32_ethmac_s *priv) for (timeout = 0; timeout < PHY_RETRY_TIMEOUT; timeout++) { - ret = stm32_phyread(CONFIG_STM32H5_PHYADDR, MII_MSR, &phyval); + ret = stm32_phyread(CONFIG_STM32_PHYADDR, MII_MSR, &phyval); if (ret < 0) { nerr("ERROR: Failed to read the PHY MSR: %d\n", ret); @@ -3446,7 +3446,7 @@ static int stm32_phyinit(struct stm32_ethmac_s *priv) /* Read the result of the auto-negotiation from the PHY-specific register */ - ret = stm32_phyread(CONFIG_STM32H5_PHYADDR, CONFIG_STM32H5_PHYSR, &phyval); + ret = stm32_phyread(CONFIG_STM32_PHYADDR, CONFIG_STM32_PHYSR, &phyval); if (ret < 0) { nerr("ERROR: Failed to read PHY status register\n"); @@ -3455,38 +3455,38 @@ static int stm32_phyinit(struct stm32_ethmac_s *priv) /* Remember the selected speed and duplex modes */ - ninfo("PHYSR[%d]: %04x\n", CONFIG_STM32H5_PHYSR, phyval); + ninfo("PHYSR[%d]: %04x\n", CONFIG_STM32_PHYSR, phyval); /* Different PHYs present speed and mode information in different ways. IF - * This CONFIG_STM32H5_PHYSR_ALTCONFIG is selected, this indicates that + * This CONFIG_STM32_PHYSR_ALTCONFIG is selected, this indicates that * the PHY represents speed and mode information are combined, for * example, with separate bits for 10HD, 100HD, 10FD and 100FD. */ -#ifdef CONFIG_STM32H5_PHYSR_ALTCONFIG - switch (phyval & CONFIG_STM32H5_PHYSR_ALTMODE) +#ifdef CONFIG_STM32_PHYSR_ALTCONFIG + switch (phyval & CONFIG_STM32_PHYSR_ALTMODE) { default: nerr("ERROR: Unrecognized PHY status setting\n"); /* Falls through */ - case CONFIG_STM32H5_PHYSR_10HD: + case CONFIG_STM32_PHYSR_10HD: priv->fduplex = 0; priv->mbps100 = 0; break; - case CONFIG_STM32H5_PHYSR_100HD: + case CONFIG_STM32_PHYSR_100HD: priv->fduplex = 0; priv->mbps100 = 1; break; - case CONFIG_STM32H5_PHYSR_10FD: + case CONFIG_STM32_PHYSR_10FD: priv->fduplex = 1; priv->mbps100 = 0; break; - case CONFIG_STM32H5_PHYSR_100FD: + case CONFIG_STM32_PHYSR_100FD: priv->fduplex = 1; priv->mbps100 = 1; break; @@ -3499,13 +3499,13 @@ static int stm32_phyinit(struct stm32_ethmac_s *priv) */ #else - if ((phyval & CONFIG_STM32H5_PHYSR_MODE) == - CONFIG_STM32H5_PHYSR_FULLDUPLEX) + if ((phyval & CONFIG_STM32_PHYSR_MODE) == + CONFIG_STM32_PHYSR_FULLDUPLEX) { priv->fduplex = 1; } - if ((phyval & CONFIG_STM32H5_PHYSR_SPEED) == CONFIG_STM32H5_PHYSR_100MBPS) + if ((phyval & CONFIG_STM32_PHYSR_SPEED) == CONFIG_STM32_PHYSR_100MBPS) { priv->mbps100 = 1; } @@ -3514,14 +3514,14 @@ static int stm32_phyinit(struct stm32_ethmac_s *priv) #else /* Auto-negotiation not selected */ phyval = 0; -#ifdef CONFIG_STM32H5_ETHFD +#ifdef CONFIG_STM32_ETHFD phyval |= MII_MCR_FULLDPLX; #endif -#ifdef CONFIG_STM32H5_ETH100MBPS +#ifdef CONFIG_STM32_ETH100MBPS phyval |= MII_MCR_SPEED100; #endif - ret = stm32_phywrite(CONFIG_STM32H5_PHYADDR, MII_MCR, phyval, 0xffff); + ret = stm32_phywrite(CONFIG_STM32_PHYADDR, MII_MCR, phyval, 0xffff); if (ret < 0) { nerr("ERROR: Failed to write the PHY MCR: %d\n", ret); @@ -3532,10 +3532,10 @@ static int stm32_phyinit(struct stm32_ethmac_s *priv) /* Remember the selected speed and duplex modes */ -#ifdef CONFIG_STM32H5_ETHFD +#ifdef CONFIG_STM32_ETHFD priv->fduplex = 1; #endif -#ifdef CONFIG_STM32H5_ETH100MBPS +#ifdef CONFIG_STM32_ETH100MBPS priv->mbps100 = 1; #endif #endif @@ -3563,7 +3563,7 @@ static int stm32_phyinit(struct stm32_ethmac_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32H5_MII +#ifdef CONFIG_STM32_MII #pragma message "If TrustZone is enabled, MII will fail to select." static inline void stm32_selectmii(void) { @@ -3590,7 +3590,7 @@ static inline void stm32_selectmii(void) * ****************************************************************************/ -#ifdef CONFIG_STM32H5_RMII +#ifdef CONFIG_STM32_RMII #pragma message "If TrustZone is enabled, RMII will fail to select." static inline void stm32_selectrmii(void) { @@ -3623,17 +3623,17 @@ static inline void stm32_ethgpioconfig(struct stm32_ethmac_s *priv) { /* Configure GPIO pins to support Ethernet */ -#if defined(CONFIG_STM32H5_MII) || defined(CONFIG_STM32H5_RMII) +#if defined(CONFIG_STM32_MII) || defined(CONFIG_STM32_RMII) /* MDC and MDIO are common to both modes */ -# ifndef CONFIG_STM32H5_NO_PHY +# ifndef CONFIG_STM32_NO_PHY stm32_configgpio(GPIO_ETH_MDC); stm32_configgpio(GPIO_ETH_MDIO); # endif /* Set up the MII interface */ -# if defined(CONFIG_STM32H5_MII) +# if defined(CONFIG_STM32_MII) /* Select the MII interface */ @@ -3648,7 +3648,7 @@ static inline void stm32_ethgpioconfig(struct stm32_ethmac_s *priv) * PLLI2S clock (through a configurable prescaler) on PC9 pin." */ -# if defined(CONFIG_STM32H5_MII_MCO1) +# if defined(CONFIG_STM32_MII_MCO1) /* Configure MC01 to drive the PHY. Board logic must provide MC01 clocking * info. */ @@ -3656,7 +3656,7 @@ static inline void stm32_ethgpioconfig(struct stm32_ethmac_s *priv) stm32_configgpio(GPIO_MCO1); stm32_mco1config(BOARD_CFGR_MC01_SOURCE, BOARD_CFGR_MC01_DIVIDER); -# elif defined(CONFIG_STM32H5_MII_MCO2) +# elif defined(CONFIG_STM32_MII_MCO2) /* Configure MC02 to drive the PHY. Board logic must provide MC02 clocking * info. */ @@ -3664,7 +3664,7 @@ static inline void stm32_ethgpioconfig(struct stm32_ethmac_s *priv) stm32_configgpio(GPIO_MCO2); stm32_mco2config(BOARD_CFGR_MC02_SOURCE, BOARD_CFGR_MC02_DIVIDER); -# elif defined(CONFIG_STM32H5_MII_MCO) +# elif defined(CONFIG_STM32_MII_MCO) /* Setup MCO pin for alternative usage */ stm32_configgpio(GPIO_MCO); @@ -3695,7 +3695,7 @@ static inline void stm32_ethgpioconfig(struct stm32_ethmac_s *priv) /* Set up the RMII interface. */ -# elif defined(CONFIG_STM32H5_RMII) +# elif defined(CONFIG_STM32_RMII) /* Select the RMII interface */ @@ -3710,7 +3710,7 @@ static inline void stm32_ethgpioconfig(struct stm32_ethmac_s *priv) * PLLI2S clock (through a configurable prescaler) on PC9 pin." */ -# if defined(CONFIG_STM32H5_RMII_MCO1) +# if defined(CONFIG_STM32_RMII_MCO1) /* Configure MC01 to drive the PHY. Board logic must provide MC01 clocking * info. */ @@ -3718,7 +3718,7 @@ static inline void stm32_ethgpioconfig(struct stm32_ethmac_s *priv) stm32_configgpio(GPIO_MCO1); stm32_mco1config(BOARD_CFGR_MC01_SOURCE, BOARD_CFGR_MC01_DIVIDER); -# elif defined(CONFIG_STM32H5_RMII_MCO2) +# elif defined(CONFIG_STM32_RMII_MCO2) /* Configure MC02 to drive the PHY. Board logic must provide MC02 clocking * info. */ @@ -3726,7 +3726,7 @@ static inline void stm32_ethgpioconfig(struct stm32_ethmac_s *priv) stm32_configgpio(GPIO_MCO2); stm32_mco2config(BOARD_CFGR_MC02_SOURCE, BOARD_CFGR_MC02_DIVIDER); -# elif defined(CONFIG_STM32H5_RMII_MCO) +# elif defined(CONFIG_STM32_RMII_MCO) /* Setup MCO pin for alternative usage */ stm32_configgpio(GPIO_MCO); @@ -3749,7 +3749,7 @@ static inline void stm32_ethgpioconfig(struct stm32_ethmac_s *priv) # endif #endif -#ifdef CONFIG_STM32H5_ETH_PTP +#ifdef CONFIG_STM32_ETH_PTP /* Enable pulse-per-second (PPS) output signal */ stm32_configgpio(GPIO_ETH_PPS_OUT); @@ -4088,7 +4088,7 @@ static int stm32_ethconfig(struct stm32_ethmac_s *priv) * sequence in stm32_rcc.c. */ -#ifdef CONFIG_STM32H5_PHYINIT +#ifdef CONFIG_STM32_PHYINIT /* Perform any necessary, board-specific PHY initialization */ ret = stm32_phy_boardinitialize(0); @@ -4111,24 +4111,24 @@ static int stm32_ethconfig(struct stm32_ethmac_s *priv) /* Initialize TX Descriptors list */ stm32_txdescinit(priv, - &g_txtable[priv->intf * CONFIG_STM32H5_ETH_NTXDESC]); + &g_txtable[priv->intf * CONFIG_STM32_ETH_NTXDESC]); /* Initialize RX Descriptors list */ stm32_rxdescinit(priv, - &g_rxtable[priv->intf * CONFIG_STM32H5_ETH_NRXDESC], + &g_rxtable[priv->intf * CONFIG_STM32_ETH_NRXDESC], &g_rxbuffer[priv->intf * RXBUFFER_SIZE]); /* Initialize the PHY */ -#ifdef CONFIG_STM32H5_NO_PHY +#ifdef CONFIG_STM32_NO_PHY ninfo("MAC without PHY\n"); -#ifdef CONFIG_STM32H5_ETHFD +#ifdef CONFIG_STM32_ETHFD priv->fduplex = 1; #else priv->fduplex = 0; #endif -#ifdef CONFIG_STM32H5_ETH100MBPS +#ifdef CONFIG_STM32_ETH100MBPS priv->mbps100 = 1; #else priv->mbps100 = 0; @@ -4181,7 +4181,7 @@ static int stm32_ethconfig(struct stm32_ethmac_s *priv) * ****************************************************************************/ -#if STM32H5_NETHERNET > 1 || defined(CONFIG_NETDEV_LATEINIT) +#if STM32_NETHERNET > 1 || defined(CONFIG_NETDEV_LATEINIT) int stm32_ethinitialize(int intf) #else static inline int stm32_ethinitialize(int intf) @@ -4196,7 +4196,7 @@ static inline int stm32_ethinitialize(int intf) /* Get the interface structure associated with this interface number. */ - DEBUGASSERT(intf < STM32H5_NETHERNET); + DEBUGASSERT(intf < STM32_NETHERNET); priv = &g_stm32ethmac[intf]; /* Initialize the driver structure */ @@ -4242,7 +4242,7 @@ static inline int stm32_ethinitialize(int intf) return -EAGAIN; } -#ifdef CONFIG_STM32H5_PHYINIT +#ifdef CONFIG_STM32_PHYINIT /* Perform any necessary, board-specific PHY initialization */ ret = stm32_phy_boardinitialize(0); @@ -4268,7 +4268,7 @@ static inline int stm32_ethinitialize(int intf) * * Description: * This is the "standard" network initialization logic called from the - * low-level initialization logic in arm_initialize.c. If STM32H5_NETHERNET + * low-level initialization logic in arm_initialize.c. If STM32_NETHERNET * greater than one, then board specific logic will have to supply a * version of arm_netinitialize() that calls stm32_ethinitialize() with * the appropriate interface number. @@ -4283,11 +4283,11 @@ static inline int stm32_ethinitialize(int intf) * ****************************************************************************/ -#if STM32H5_NETHERNET == 1 && !defined(CONFIG_NETDEV_LATEINIT) +#if STM32_NETHERNET == 1 && !defined(CONFIG_NETDEV_LATEINIT) void arm_netinitialize(void) { stm32_ethinitialize(0); } #endif -#endif /* STM32H5_NETHERNET > 0 && CONFIG_STM32H5_ETHMAC */ +#endif /* STM32_NETHERNET > 0 && CONFIG_STM32_ETHMAC */ diff --git a/arch/arm/src/stm32h5/stm32_ethernet.h b/arch/arm/src/stm32h5/stm32_ethernet.h index 66107aa0181a4..284d011894d1e 100644 --- a/arch/arm/src/stm32h5/stm32_ethernet.h +++ b/arch/arm/src/stm32h5/stm32_ethernet.h @@ -29,7 +29,7 @@ #include "hardware/stm32_ethernet.h" -#if STM32H5_NETHERNET > 0 +#if STM32_NETHERNET > 0 #ifndef __ASSEMBLY__ /**************************************************************************** @@ -65,7 +65,7 @@ extern "C" * ****************************************************************************/ -#if STM32H5_NETHERNET > 1 || defined(CONFIG_NETDEV_LATEINIT) +#if STM32_NETHERNET > 1 || defined(CONFIG_NETDEV_LATEINIT) int stm32_ethinitialize(int intf); #endif @@ -75,7 +75,7 @@ int stm32_ethinitialize(int intf); * Description: * Some boards require specialized initialization of the PHY before it can * be used. This may include such things as configuring GPIOs, resetting - * the PHY, etc. If CONFIG_STM32H5_PHYINIT is defined in the configuration + * the PHY, etc. If CONFIG_STM32_PHYINIT is defined in the configuration * then the board specific logic must provide stm32_phyinitialize(); The * STM32 Ethernet driver will call this function one time before it first * uses the PHY. @@ -90,7 +90,7 @@ int stm32_ethinitialize(int intf); * ****************************************************************************/ -#ifdef CONFIG_STM32H5_PHYINIT +#ifdef CONFIG_STM32_PHYINIT int stm32_phy_boardinitialize(int intf); #endif @@ -100,5 +100,5 @@ int stm32_phy_boardinitialize(int intf); #endif #endif /* __ASSEMBLY__ */ -#endif /* STM32H5_NETHERNET > 0 */ +#endif /* STM32_NETHERNET > 0 */ #endif /* __ARCH_ARM_SRC_STM32H5_STM32_ETHERNET_H */ \ No newline at end of file diff --git a/arch/arm/src/stm32h5/stm32_fdcan.c b/arch/arm/src/stm32h5/stm32_fdcan.c index 622c809eafa38..639f0e7e1d921 100644 --- a/arch/arm/src/stm32h5/stm32_fdcan.c +++ b/arch/arm/src/stm32h5/stm32_fdcan.c @@ -75,7 +75,7 @@ # define STM32_CANRAM1_BASE (STM32_FDCAN_SRAM_BASE + 0x0000) # define STM32_CANRAM2_BASE (STM32_FDCAN_SRAM_BASE + 1*(FDCAN_MSGRAM_WORDS * 4)) -# ifdef CONFIG_STM32H5_FDCAN1 +# ifdef CONFIG_STM32_FDCAN1 # define FDCAN1_STDFILTER_SIZE (28) # define FDCAN1_EXTFILTER_SIZE (8) # define FDCAN1_RXFIFO0_SIZE (3) @@ -90,7 +90,7 @@ # define FDCAN1_TXEVENTFIFO_WORDS (6) # define FDCAN1_TXFIFIOQ_WORDS (54) # endif -# ifdef CONFIG_STM32H5_FDCAN2 +# ifdef CONFIG_STM32_FDCAN2 # define FDCAN2_STDFILTER_SIZE (28) # define FDCAN2_EXTFILTER_SIZE (8) # define FDCAN2_RXFIFO0_SIZE (3) @@ -108,18 +108,18 @@ /* FDCAN1 Configuration *****************************************************/ -#ifdef CONFIG_STM32H5_FDCAN1 +#ifdef CONFIG_STM32_FDCAN1 /* Bit timing */ -# ifndef CONFIG_STM32H5_FDCAN1_AUTO_BIT_TIMING +# ifndef CONFIG_STM32_FDCAN1_AUTO_BIT_TIMING -# define FDCAN1_NTSEG1 (CONFIG_STM32H5_FDCAN1_NTSEG1 - 1) -# define FDCAN1_NTSEG2 (CONFIG_STM32H5_FDCAN1_NTSEG2 - 1) +# define FDCAN1_NTSEG1 (CONFIG_STM32_FDCAN1_NTSEG1 - 1) +# define FDCAN1_NTSEG2 (CONFIG_STM32_FDCAN1_NTSEG2 - 1) # define FDCAN1_NBRP ((STM32_FDCANCLK_FREQUENCY / \ ((FDCAN1_NTSEG1 + FDCAN1_NTSEG2 + 3) * \ - CONFIG_STM32H5_FDCAN1_BITRATE)) - 1) -# define FDCAN1_NSJW (CONFIG_STM32H5_FDCAN1_NSJW - 1) + CONFIG_STM32_FDCAN1_BITRATE)) - 1) +# define FDCAN1_NSJW (CONFIG_STM32_FDCAN1_NSJW - 1) # if FDCAN1_NTSEG1 > FDCAN_NBTP_NTSEG1_MAX # error Invalid FDCAN1 NTSEG1 @@ -134,13 +134,13 @@ # error Invalid FDCAN1 NBRP # endif -# ifdef CONFIG_STM32H5_FDCAN1_FD_BRS -# define FDCAN1_DTSEG1 (CONFIG_STM32H5_FDCAN1_DTSEG1 - 1) -# define FDCAN1_DTSEG2 (CONFIG_STM32H5_FDCAN1_DTSEG2 - 1) +# ifdef CONFIG_STM32_FDCAN1_FD_BRS +# define FDCAN1_DTSEG1 (CONFIG_STM32_FDCAN1_DTSEG1 - 1) +# define FDCAN1_DTSEG2 (CONFIG_STM32_FDCAN1_DTSEG2 - 1) # define FDCAN1_DBRP ((STM32_FDCANCLK_FREQUENCY / \ ((FDCAN1_DTSEG1 + FDCAN1_DTSEG2 + 3) * \ - CONFIG_STM32H5_FDCAN1_DBITRATE)) - 1) -# define FDCAN1_DSJW (CONFIG_STM32H5_FDCAN1_DSJW - 1) + CONFIG_STM32_FDCAN1_DBITRATE)) - 1) +# define FDCAN1_DSJW (CONFIG_STM32_FDCAN1_DSJW - 1) # else # define FDCAN1_DTSEG1 1 # define FDCAN1_DTSEG2 1 @@ -174,22 +174,22 @@ # define FDCAN1_TXFIFOQ_INDEX (FDCAN1_TXEVENTFIFO_INDEX + FDCAN1_TXEVENTFIFO_WORDS) # define FDCAN1_MSGRAM_WORDS (FDCAN1_TXFIFOQ_INDEX + FDCAN1_TXFIFIOQ_WORDS) -#endif /* CONFIG_STM32H5_FDCAN1 */ +#endif /* CONFIG_STM32_FDCAN1 */ /* FDCAN2 Configuration *****************************************************/ -#ifdef CONFIG_STM32H5_FDCAN2 +#ifdef CONFIG_STM32_FDCAN2 /* Bit timing */ -# ifndef CONFIG_STM32H5_FDCAN2_AUTO_BIT_TIMING +# ifndef CONFIG_STM32_FDCAN2_AUTO_BIT_TIMING -# define FDCAN2_NTSEG1 (CONFIG_STM32H5_FDCAN2_NTSEG1 - 1) -# define FDCAN2_NTSEG2 (CONFIG_STM32H5_FDCAN2_NTSEG2 - 1) +# define FDCAN2_NTSEG1 (CONFIG_STM32_FDCAN2_NTSEG1 - 1) +# define FDCAN2_NTSEG2 (CONFIG_STM32_FDCAN2_NTSEG2 - 1) # define FDCAN2_NBRP (((STM32_FDCANCLK_FREQUENCY / \ ((FDCAN2_NTSEG1 + FDCAN2_NTSEG2 + 3) * \ - CONFIG_STM32H5_FDCAN2_BITRATE)) - 1)) -# define FDCAN2_NSJW (CONFIG_STM32H5_FDCAN2_NSJW - 1) + CONFIG_STM32_FDCAN2_BITRATE)) - 1)) +# define FDCAN2_NSJW (CONFIG_STM32_FDCAN2_NSJW - 1) # if FDCAN2_NTSEG1 > FDCAN_NBTP_NTSEG1_MAX # error Invalid FDCAN2 NTSEG1 @@ -204,13 +204,13 @@ # error Invalid FDCAN1 NBRP # endif -# ifdef CONFIG_STM32H5_FDCAN2_FD_BRS -# define FDCAN2_DTSEG1 (CONFIG_STM32H5_FDCAN2_DTSEG1 - 1) -# define FDCAN2_DTSEG2 (CONFIG_STM32H5_FDCAN2_DTSEG2 - 1) +# ifdef CONFIG_STM32_FDCAN2_FD_BRS +# define FDCAN2_DTSEG1 (CONFIG_STM32_FDCAN2_DTSEG1 - 1) +# define FDCAN2_DTSEG2 (CONFIG_STM32_FDCAN2_DTSEG2 - 1) # define FDCAN2_DBRP (((STM32_FDCANCLK_FREQUENCY / \ ((FDCAN2_DTSEG1 + FDCAN2_DTSEG2 + 3) * \ - CONFIG_STM32H5_FDCAN2_DBITRATE)) - 1)) -# define FDCAN2_DSJW (CONFIG_STM32H5_FDCAN2_DSJW - 1) + CONFIG_STM32_FDCAN2_DBITRATE)) - 1)) +# define FDCAN2_DSJW (CONFIG_STM32_FDCAN2_DSJW - 1) # else # define FDCAN2_DTSEG1 1 # define FDCAN2_DTSEG2 1 @@ -245,7 +245,7 @@ # define FDCAN2_TXFIFOQ_INDEX (FDCAN2_TXEVENTFIFO_INDEX + FDCAN2_TXEVENTFIFO_WORDS) # define FDCAN2_MSGRAM_WORDS (FDCAN2_TXFIFOQ_INDEX + FDCAN2_TXFIFIOQ_WORDS) -#endif /* CONFIG_STM32H5_FDCAN2 */ +#endif /* CONFIG_STM32_FDCAN2 */ /* Interrupts ***************************************************************/ @@ -325,13 +325,13 @@ /* Debug configurations that may be enabled just for testing FDCAN */ #ifndef CONFIG_DEBUG_CAN_INFO -# undef CONFIG_STM32H5_FDCAN_REGDEBUG +# undef CONFIG_STM32_FDCAN_REGDEBUG #endif -#undef STM32H5_FDCAN_LOOPBACK -#if defined(CONFIG_STM32H5_FDCAN1_LOOPBACK) || \ - defined(CONFIG_STM32H5_FDCAN2_LOOPBACK) -# define STM32H5_FDCAN_LOOPBACK 1 +#undef STM32_FDCAN_LOOPBACK +#if defined(CONFIG_STM32_FDCAN1_LOOPBACK) || \ + defined(CONFIG_STM32_FDCAN2_LOOPBACK) +# define STM32_FDCAN_LOOPBACK 1 #endif /**************************************************************************** @@ -403,7 +403,7 @@ struct stm32_config_s uint8_t rxfifo1esize; /* RX FIFO1 element size (words) */ uint8_t txeventesize; /* TXevent element size (words) */ uint8_t txbufferesize; /* TX buffer element size (words) */ -#ifdef STM32H5_FDCAN_LOOPBACK +#ifdef STM32_FDCAN_LOOPBACK bool loopback; /* True: Loopback mode */ #endif @@ -435,7 +435,7 @@ struct stm32_fdcan_s #endif uint32_t stdfilters[4]; /* Standard filter bit allocator. 4*32=128 */ -#ifdef CONFIG_STM32H5_FDCAN_REGDEBUG +#ifdef CONFIG_STM32_FDCAN_REGDEBUG uintptr_t regaddr; /* Last register address read */ uint32_t regval; /* Last value read from the register */ unsigned int count; /* Number of times that the value was read */ @@ -460,7 +460,7 @@ struct fdcan_bitseg static uint32_t fdcan_getreg(struct stm32_fdcan_s *priv, int offset); static void fdcan_putreg(struct stm32_fdcan_s *priv, int offset, uint32_t regval); -#ifdef CONFIG_STM32H5_FDCAN_REGDEBUG +#ifdef CONFIG_STM32_FDCAN_REGDEBUG static void fdcan_dumpregs(struct stm32_fdcan_s *priv, const char *msg); static void fdcan_dumprxregs(struct stm32_fdcan_s *priv, @@ -537,7 +537,7 @@ static const struct can_ops_s g_fdcanops = .co_txempty = fdcan_txempty, }; -#ifdef CONFIG_STM32H5_FDCAN1 +#ifdef CONFIG_STM32_FDCAN1 /* Message RAM allocation */ /* Constant configuration */ @@ -547,11 +547,11 @@ static const struct stm32_config_s g_fdcan1const = .rxpinset = GPIO_FDCAN1_RX, .txpinset = GPIO_FDCAN1_TX, .base = STM32_FDCAN1_BASE, - .baud = CONFIG_STM32H5_FDCAN1_BITRATE, -#if defined(CONFIG_STM32H5_FDCAN1_FD_BRS) - .data_baud = CONFIG_STM32H5_FDCAN1_DBITRATE, + .baud = CONFIG_STM32_FDCAN1_BITRATE, +#if defined(CONFIG_STM32_FDCAN1_FD_BRS) + .data_baud = CONFIG_STM32_FDCAN1_DBITRATE, #endif -#ifndef CONFIG_STM32H5_FDCAN1_AUTO_BIT_TIMING +#ifndef CONFIG_STM32_FDCAN1_AUTO_BIT_TIMING .nbtp = FDCAN_NBTP_NBRP(FDCAN1_NBRP) | FDCAN_NBTP_NTSEG1(FDCAN1_NTSEG1) | FDCAN_NBTP_NTSEG2(FDCAN1_NTSEG2) | @@ -564,14 +564,14 @@ static const struct stm32_config_s g_fdcan1const = .port = 1, .irq0 = STM32_IRQ_FDCAN1_IT0, .irq1 = STM32_IRQ_FDCAN1_IT1, -#if defined(CONFIG_STM32H5_FDCAN1_CLASSIC) +#if defined(CONFIG_STM32_FDCAN1_CLASSIC) .mode = FDCAN_CLASSIC_MODE, -#elif defined(CONFIG_STM32H5_FDCAN1_FD) +#elif defined(CONFIG_STM32_FDCAN1_FD) .mode = FDCAN_FD_MODE, #else .mode = FDCAN_FD_BRS_MODE, #endif -#if defined(CONFIG_STM32H5_FDCAN1_NONISO_FORMAT) +#if defined(CONFIG_STM32_FDCAN1_NONISO_FORMAT) .format = FDCAN_NONISO_BOSCH_V1_FORMAT, #else .format = FDCAN_ISO11898_1_FORMAT, @@ -587,7 +587,7 @@ static const struct stm32_config_s g_fdcan1const = .txeventesize = (FDCAN1_TXEVENTFIFO_WORDS / FDCAN1_TXEVENTFIFO_SIZE), .txbufferesize = (FDCAN1_TXFIFIOQ_WORDS / FDCAN1_TXFIFIOQ_SIZE), -#ifdef CONFIG_STM32H5_FDCAN1_LOOPBACK +#ifdef CONFIG_STM32_FDCAN1_LOOPBACK .loopback = true, #endif @@ -609,9 +609,9 @@ static const struct stm32_config_s g_fdcan1const = static struct stm32_fdcan_s g_fdcan1priv; static struct can_dev_s g_fdcan1dev; -#endif /* CONFIG_STM32H5_FDCAN1 */ +#endif /* CONFIG_STM32_FDCAN1 */ -#ifdef CONFIG_STM32H5_FDCAN2 +#ifdef CONFIG_STM32_FDCAN2 /* FDCAN2 message RAM allocation */ /* FDCAN2 constant configuration */ @@ -621,11 +621,11 @@ static const struct stm32_config_s g_fdcan2const = .rxpinset = GPIO_FDCAN2_RX, .txpinset = GPIO_FDCAN2_TX, .base = STM32_FDCAN2_BASE, - .baud = CONFIG_STM32H5_FDCAN2_BITRATE, -#if defined(CONFIG_STM32H5_FDCAN2_FD_BRS) - .data_baud = CONFIG_STM32H5_FDCAN2_DBITRATE, + .baud = CONFIG_STM32_FDCAN2_BITRATE, +#if defined(CONFIG_STM32_FDCAN2_FD_BRS) + .data_baud = CONFIG_STM32_FDCAN2_DBITRATE, #endif -#ifndef CONFIG_STM32H5_FDCAN2_AUTO_BIT_TIMING +#ifndef CONFIG_STM32_FDCAN2_AUTO_BIT_TIMING .nbtp = FDCAN_NBTP_NBRP(FDCAN2_NBRP) | FDCAN_NBTP_NTSEG1(FDCAN2_NTSEG1) | FDCAN_NBTP_NTSEG2(FDCAN2_NTSEG2) | @@ -638,14 +638,14 @@ static const struct stm32_config_s g_fdcan2const = .port = 2, .irq0 = STM32_IRQ_FDCAN2_IT0, .irq1 = STM32_IRQ_FDCAN2_IT1, -#if defined(CONFIG_STM32H5_FDCAN2_CLASSIC) +#if defined(CONFIG_STM32_FDCAN2_CLASSIC) .mode = FDCAN_CLASSIC_MODE, -#elif defined(CONFIG_STM32H5_FDCAN2_FD) +#elif defined(CONFIG_STM32_FDCAN2_FD) .mode = FDCAN_FD_MODE, #else .mode = FDCAN_FD_BRS_MODE, #endif -#if defined(CONFIG_STM32H5_FDCAN2_NONISO_FORMAT) +#if defined(CONFIG_STM32_FDCAN2_NONISO_FORMAT) .format = FDCAN_NONISO_BOSCH_V1_FORMAT, #else .format = FDCAN_ISO11898_1_FORMAT, @@ -661,7 +661,7 @@ static const struct stm32_config_s g_fdcan2const = .txeventesize = (FDCAN2_TXEVENTFIFO_WORDS / FDCAN2_TXEVENTFIFO_SIZE), .txbufferesize = (FDCAN2_TXFIFIOQ_WORDS / FDCAN2_TXFIFIOQ_SIZE), -#ifdef CONFIG_STM32H5_FDCAN2_LOOPBACK +#ifdef CONFIG_STM32_FDCAN2_LOOPBACK .loopback = true, #endif @@ -683,7 +683,7 @@ static const struct stm32_config_s g_fdcan2const = static struct stm32_fdcan_s g_fdcan2priv; static struct can_dev_s g_fdcan2dev; -#endif /* CONFIG_STM32H5_FDCAN2 */ +#endif /* CONFIG_STM32_FDCAN2 */ /**************************************************************************** * Private Functions @@ -703,7 +703,7 @@ static struct can_dev_s g_fdcan2dev; * ****************************************************************************/ -#ifdef CONFIG_STM32H5_FDCAN_REGDEBUG +#ifdef CONFIG_STM32_FDCAN_REGDEBUG static uint32_t fdcan_getreg(struct stm32_fdcan_s *priv, int offset) { const struct stm32_config_s *config = priv->config; @@ -783,7 +783,7 @@ static uint32_t fdcan_getreg(struct stm32_fdcan_s *priv, int offset) * ****************************************************************************/ -#ifdef CONFIG_STM32H5_FDCAN_REGDEBUG +#ifdef CONFIG_STM32_FDCAN_REGDEBUG static void fdcan_putreg(struct stm32_fdcan_s *priv, int offset, uint32_t regval) { @@ -823,7 +823,7 @@ static void fdcan_putreg(struct stm32_fdcan_s *priv, int offset, * ****************************************************************************/ -#ifdef CONFIG_STM32H5_FDCAN_REGDEBUG +#ifdef CONFIG_STM32_FDCAN_REGDEBUG static void fdcan_dumpregs(struct stm32_fdcan_s *priv, const char *msg) { @@ -869,7 +869,7 @@ static void fdcan_dumpregs(struct stm32_fdcan_s *priv, * ****************************************************************************/ -#ifdef CONFIG_STM32H5_FDCAN_REGDEBUG +#ifdef CONFIG_STM32_FDCAN_REGDEBUG static void fdcan_dumprxregs(struct stm32_fdcan_s *priv, const char *msg) { @@ -912,7 +912,7 @@ static void fdcan_dumprxregs(struct stm32_fdcan_s *priv, * ****************************************************************************/ -#ifdef CONFIG_STM32H5_FDCAN_REGDEBUG +#ifdef CONFIG_STM32_FDCAN_REGDEBUG static void fdcan_dumptxregs(struct stm32_fdcan_s *priv, const char *msg) { @@ -961,7 +961,7 @@ static void fdcan_dumptxregs(struct stm32_fdcan_s *priv, * ****************************************************************************/ -#ifdef CONFIG_STM32H5_FDCAN_REGDEBUG +#ifdef CONFIG_STM32_FDCAN_REGDEBUG static void fdcan_dumpramlayout(struct stm32_fdcan_s *priv) { const struct stm32_config_s *config = priv->config; @@ -2406,7 +2406,7 @@ static bool fdcan_txempty(struct can_dev_s *dev) { struct stm32_fdcan_s *priv = dev->cd_priv; uint32_t regval = 0; -#ifndef CONFIG_STM32H5_FDCAN_QUEUE_MODE +#ifndef CONFIG_STM32_FDCAN_QUEUE_MODE int tffl = 0; bool empty = false; #endif @@ -2426,7 +2426,7 @@ static bool fdcan_txempty(struct can_dev_s *dev) /* Tx FIFO Free Level */ -#ifndef CONFIG_STM32H5_FDCAN_QUEUE_MODE +#ifndef CONFIG_STM32_FDCAN_QUEUE_MODE tffl = (regval & FDCAN_TXFQS_TFFL_MASK) >> FDCAN_TXFQS_TFFL_SHIFT; empty = (tffl >= priv->config->ntxfifoq); return empty; @@ -3275,14 +3275,14 @@ static int fdcan_hw_initialize(struct stm32_fdcan_s *priv) /* Enable FIFO/Queue mode */ regval = fdcan_getreg(priv, STM32_FDCAN_TXBC_OFFSET); -#ifdef CONFIG_STM32H5_FDCAN_QUEUE_MODE +#ifdef CONFIG_STM32_FDCAN_QUEUE_MODE regval |= FDCAN_TXBC_TFQM; #else regval &= ~FDCAN_TXBC_TFQM; #endif fdcan_putreg(priv, STM32_FDCAN_TXBC_OFFSET, regval); -#ifdef STM32H5_FDCAN_LOOPBACK +#ifdef STM32_FDCAN_LOOPBACK /* Is loopback mode selected for this peripheral? */ if (config->loopback) @@ -3461,7 +3461,7 @@ int32_t fdcan_bittiming(struct fdcan_bitseg *timing) return 3; /* Solution not found */ } -#ifdef CONFIG_STM32H5_FDCAN_REGDEBUG +#ifdef CONFIG_STM32_FDCAN_REGDEBUG ninfo("[fdcan] CLK_FREQ %lu, target_bitrate %lu, prescaler %lu, bs1 %d" ", bs2 %d\n", CLK_FREQ, target_bitrate, prescaler_bs, bs1 - 1, bs2 - 1); @@ -3506,7 +3506,7 @@ struct can_dev_s *stm32_fdcaninitialize(int port) /* Select FDCAN peripheral to be initialized */ -#ifdef CONFIG_STM32H5_FDCAN1 +#ifdef CONFIG_STM32_FDCAN1 if (port == FDCAN1) { /* Select the FDCAN1 device structure */ @@ -3514,13 +3514,13 @@ struct can_dev_s *stm32_fdcaninitialize(int port) dev = &g_fdcan1dev; priv = &g_fdcan1priv; config = &g_fdcan1const; -#ifndef CONFIG_STM32H5_FDCAN1_AUTO_BIT_TIMING +#ifndef CONFIG_STM32_FDCAN1_AUTO_BIT_TIMING auto_bit_timing = false; #endif } else #endif -#ifdef CONFIG_STM32H5_FDCAN2 +#ifdef CONFIG_STM32_FDCAN2 if (port == FDCAN2) { /* Select the FDCAN2 device structure */ @@ -3528,7 +3528,7 @@ struct can_dev_s *stm32_fdcaninitialize(int port) dev = &g_fdcan2dev; priv = &g_fdcan2priv; config = &g_fdcan2const; -#ifndef CONFIG_STM32H5_FDCAN2_AUTO_BIT_TIMING +#ifndef CONFIG_STM32_FDCAN2_AUTO_BIT_TIMING auto_bit_timing = false; #endif } diff --git a/arch/arm/src/stm32h5/stm32_fdcan.h b/arch/arm/src/stm32h5/stm32_fdcan.h index 5f770fc7a8166..04207ad79856e 100644 --- a/arch/arm/src/stm32h5/stm32_fdcan.h +++ b/arch/arm/src/stm32h5/stm32_fdcan.h @@ -64,7 +64,7 @@ extern "C" * Public Function Prototypes ****************************************************************************/ -#ifdef CONFIG_STM32H5_FDCAN_CHARDRIVER +#ifdef CONFIG_STM32_FDCAN_CHARDRIVER /**************************************************************************** * Name: stm32_fdcaninitialize @@ -83,7 +83,7 @@ extern "C" struct can_dev_s *stm32_fdcaninitialize(int port); #endif -#ifdef CONFIG_STM32H5_FDCAN_SOCKET +#ifdef CONFIG_STM32_FDCAN_SOCKET /**************************************************************************** * Name: stm32_fdcansockinitialize diff --git a/arch/arm/src/stm32h5/stm32_flash.c b/arch/arm/src/stm32h5/stm32_flash.c index e9325741b6623..feac762f1654f 100644 --- a/arch/arm/src/stm32h5/stm32_flash.c +++ b/arch/arm/src/stm32h5/stm32_flash.c @@ -26,7 +26,7 @@ #include -#if defined(CONFIG_STM32H5_STM32H563XX) +#if defined(CONFIG_STM32_STM32H563XX) # include "stm32h563xx_flash.c" #else # error "Unsupported STM32 H5 chip" diff --git a/arch/arm/src/stm32h5/stm32_flash.h b/arch/arm/src/stm32h5/stm32_flash.h index bb0220a9215f9..6afaad7a1dcd3 100644 --- a/arch/arm/src/stm32h5/stm32_flash.h +++ b/arch/arm/src/stm32h5/stm32_flash.h @@ -45,16 +45,16 @@ extern "C" #define EXTERN extern #endif -void stm32h5_flash_getopt(uint32_t *opt1, uint32_t *opt2); +void stm32_flash_getopt(uint32_t *opt1, uint32_t *opt2); -int stm32h5_flash_optmodify(uint32_t clear1, uint32_t set1, +int stm32_flash_optmodify(uint32_t clear1, uint32_t set1, uint32_t clear2, uint32_t set2); -int stm32h5_flash_swapbanks(void); +int stm32_flash_swapbanks(void); -void stm32h5_flash_lock(void); +void stm32_flash_lock(void); -void stm32h5_flash_unlock(void); +void stm32_flash_unlock(void); #undef EXTERN #if defined(__cplusplus) diff --git a/arch/arm/src/stm32h5/stm32_gpio.c b/arch/arm/src/stm32h5/stm32_gpio.c index 7664d245c9e4f..334a5faf38ae4 100644 --- a/arch/arm/src/stm32h5/stm32_gpio.c +++ b/arch/arm/src/stm32h5/stm32_gpio.c @@ -52,30 +52,30 @@ static spinlock_t g_configgpio_lock = SP_UNLOCKED; /* Base addresses for each GPIO block */ -const uint32_t g_gpiobase[STM32H5_NPORTS] = +const uint32_t g_gpiobase[STM32_NPORTS] = { -#if STM32H5_NPORTS > 0 +#if STM32_NPORTS > 0 STM32_GPIOA_BASE, #endif -#if STM32H5_NPORTS > 1 +#if STM32_NPORTS > 1 STM32_GPIOB_BASE, #endif -#if STM32H5_NPORTS > 2 +#if STM32_NPORTS > 2 STM32_GPIOC_BASE, #endif -#if STM32H5_NPORTS > 3 +#if STM32_NPORTS > 3 STM32_GPIOD_BASE, #endif -#if STM32H5_NPORTS > 4 +#if STM32_NPORTS > 4 STM32_GPIOE_BASE, #endif -#if STM32H5_NPORTS > 5 +#if STM32_NPORTS > 5 STM32_GPIOF_BASE, #endif -#if STM32H5_NPORTS > 6 +#if STM32_NPORTS > 6 STM32_GPIOG_BASE, #endif -#if STM32H5_NPORTS > 7 +#if STM32_NPORTS > 7 STM32_GPIOH_BASE, #endif }; @@ -139,7 +139,7 @@ int stm32_configgpio(uint32_t cfgset) /* Verify that this hardware supports the select GPIO port */ port = (cfgset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; - if (port >= STM32H5_NPORTS) + if (port >= STM32_NPORTS) { return -EINVAL; } @@ -350,7 +350,7 @@ void stm32_gpiowrite(uint32_t pinset, bool value) unsigned int pin; port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; - if (port < STM32H5_NPORTS) + if (port < STM32_NPORTS) { /* Get the port base address */ @@ -390,7 +390,7 @@ bool stm32_gpioread(uint32_t pinset) unsigned int pin; port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; - if (port < STM32H5_NPORTS) + if (port < STM32_NPORTS) { /* Get the port base address */ diff --git a/arch/arm/src/stm32h5/stm32_gpio.h b/arch/arm/src/stm32h5/stm32_gpio.h index 9b3552cedc838..ec2caefa30533 100644 --- a/arch/arm/src/stm32h5/stm32_gpio.h +++ b/arch/arm/src/stm32h5/stm32_gpio.h @@ -39,7 +39,7 @@ #include "chip.h" -#if defined(CONFIG_STM32H5_STM32H5XXXX) +#if defined(CONFIG_STM32_STM32H5XXXX) # include "hardware/stm32_gpio.h" #else # error "Unsupported STM32H5 chip" @@ -242,7 +242,7 @@ extern "C" /* Base addresses for each GPIO block */ -EXTERN const uint32_t g_gpiobase[STM32H5_NPORTS]; +EXTERN const uint32_t g_gpiobase[STM32_NPORTS]; /**************************************************************************** * Public Function Prototypes diff --git a/arch/arm/src/stm32h5/stm32_hsi48.c b/arch/arm/src/stm32h5/stm32_hsi48.c index 7ad06b8491272..2825f722e9ec5 100644 --- a/arch/arm/src/stm32h5/stm32_hsi48.c +++ b/arch/arm/src/stm32h5/stm32_hsi48.c @@ -37,9 +37,9 @@ * Public Functions ****************************************************************************/ -#ifdef CONFIG_STM32H5_HAVE_HSI48 +#ifdef CONFIG_STM32_HAVE_HSI48 /**************************************************************************** - * Name: stm32h5_enable_hsi48 + * Name: stm32_enable_hsi48 * * Description: * The HSI48 @@ -65,7 +65,7 @@ * ****************************************************************************/ -void stm32h5_enable_hsi48(enum syncsrc_e syncsrc) +void stm32_enable_hsi48(enum syncsrc_e syncsrc) { uint32_t regval; @@ -134,7 +134,7 @@ void stm32h5_enable_hsi48(enum syncsrc_e syncsrc) } /**************************************************************************** - * Name: stm32h5_disable_hsi48 + * Name: stm32_disable_hsi48 * * Description: * Disable the HSI48 clock. @@ -147,7 +147,7 @@ void stm32h5_enable_hsi48(enum syncsrc_e syncsrc) * ****************************************************************************/ -void stm32h5_disable_hsi48(void) +void stm32_disable_hsi48(void) { uint32_t regval; @@ -168,4 +168,4 @@ void stm32h5_disable_hsi48(void) putreg32(regval, STM32_CRS_CR); } -#endif /* CONFIG_STM32H5_HAVE_HSI48 */ +#endif /* CONFIG_STM32_HAVE_HSI48 */ diff --git a/arch/arm/src/stm32h5/stm32_hsi48.h b/arch/arm/src/stm32h5/stm32_hsi48.h index 458a27f6aaa48..290bd4713f1c8 100644 --- a/arch/arm/src/stm32h5/stm32_hsi48.h +++ b/arch/arm/src/stm32h5/stm32_hsi48.h @@ -29,7 +29,7 @@ #include -#ifdef CONFIG_STM32H5_HAVE_HSI48 +#ifdef CONFIG_STM32_HAVE_HSI48 /**************************************************************************** * Public Types @@ -48,7 +48,7 @@ enum syncsrc_e ****************************************************************************/ /**************************************************************************** - * Name: stm32h5_enable_hsi48 + * Name: stm32_enable_hsi48 * * Description: * On STM32H5X3, STM32H596xx/4A6xx and STM32H5XR devices only, the HSI48 @@ -74,10 +74,10 @@ enum syncsrc_e * ****************************************************************************/ -void stm32h5_enable_hsi48(enum syncsrc_e syncsrc); +void stm32_enable_hsi48(enum syncsrc_e syncsrc); /**************************************************************************** - * Name: stm32h5_disable_hsi48 + * Name: stm32_disable_hsi48 * * Description: * Disable the HSI48 clock. @@ -90,7 +90,7 @@ void stm32h5_enable_hsi48(enum syncsrc_e syncsrc); * ****************************************************************************/ -void stm32h5_disable_hsi48(void); +void stm32_disable_hsi48(void); -#endif /* CONFIG_STM32H5_HAVE_HSI48 */ +#endif /* CONFIG_STM32_HAVE_HSI48 */ #endif /* __ARCH_ARM_SRC_STM32H5_STM32_HSI48_H */ diff --git a/arch/arm/src/stm32h5/stm32_i2c.c b/arch/arm/src/stm32h5/stm32_i2c.c index 7b43fa8ed93f5..ba1587d5587b9 100644 --- a/arch/arm/src/stm32h5/stm32_i2c.c +++ b/arch/arm/src/stm32h5/stm32_i2c.c @@ -158,28 +158,28 @@ * * One of: * - * CONFIG_STM32H5_STM32H5XXXXX + * CONFIG_STM32_STM32H5XXXXX * * and one or more interfaces: * - * CONFIG_STM32H5_I2C1 - * CONFIG_STM32H5_I2C2 - * CONFIG_STM32H5_I2C3 - * CONFIG_STM32H5_I2C4 + * CONFIG_STM32_I2C1 + * CONFIG_STM32_I2C2 + * CONFIG_STM32_I2C3 + * CONFIG_STM32_I2C4 * * To configure the ISR timeout using fixed values - * (CONFIG_STM32H5_I2C_DYNTIMEO=n): + * (CONFIG_STM32_I2C_DYNTIMEO=n): * - * CONFIG_STM32H5_I2CTIMEOSEC (Timeout in seconds) - * CONFIG_STM32H5_I2CTIMEOMS (Timeout in milliseconds) - * CONFIG_STM32H5_I2CTIMEOTICKS (Timeout in ticks) + * CONFIG_STM32_I2CTIMEOSEC (Timeout in seconds) + * CONFIG_STM32_I2CTIMEOMS (Timeout in milliseconds) + * CONFIG_STM32_I2CTIMEOTICKS (Timeout in ticks) * * To configure the ISR timeout using dynamic values - * (CONFIG_STM32H5_I2C_DYNTIMEO=y): + * (CONFIG_STM32_I2C_DYNTIMEO=y): * - * CONFIG_STM32H5_I2C_DYNTIMEO_USECPERBYTE + * CONFIG_STM32_I2C_DYNTIMEO_USECPERBYTE * (Timeout in microseconds per byte) - * CONFIG_STM32H5_I2C_DYNTIMEO_STARTSTOP + * CONFIG_STM32_I2C_DYNTIMEO_STARTSTOP * (Timeout for start/stop in msec) * * Debugging output enabled with: @@ -227,8 +227,8 @@ /* At least one I2C peripheral must be enabled */ -#if defined(CONFIG_STM32H5_I2C1) || defined(CONFIG_STM32H5_I2C2) || \ - defined(CONFIG_STM32H5_I2C3) || defined(CONFIG_STM32H5_I2C4) +#if defined(CONFIG_STM32_I2C1) || defined(CONFIG_STM32_I2C2) || \ + defined(CONFIG_STM32_I2C3) || defined(CONFIG_STM32_I2C4) /**************************************************************************** * Pre-processor Definitions @@ -246,25 +246,25 @@ /* Interrupt wait timeout in seconds and milliseconds */ -#if !defined(CONFIG_STM32H5_I2CTIMEOSEC) && !defined(CONFIG_STM32H5_I2CTIMEOMS) -# define CONFIG_STM32H5_I2CTIMEOSEC 0 -# define CONFIG_STM32H5_I2CTIMEOMS 500 /* Default is 500 milliseconds */ +#if !defined(CONFIG_STM32_I2CTIMEOSEC) && !defined(CONFIG_STM32_I2CTIMEOMS) +# define CONFIG_STM32_I2CTIMEOSEC 0 +# define CONFIG_STM32_I2CTIMEOMS 500 /* Default is 500 milliseconds */ # warning "Using Default 500 Ms Timeout" -#elif !defined(CONFIG_STM32H5_I2CTIMEOSEC) -# define CONFIG_STM32H5_I2CTIMEOSEC 0 /* User provided milliseconds */ -#elif !defined(CONFIG_STM32H5_I2CTIMEOMS) -# define CONFIG_STM32H5_I2CTIMEOMS 0 /* User provided seconds */ +#elif !defined(CONFIG_STM32_I2CTIMEOSEC) +# define CONFIG_STM32_I2CTIMEOSEC 0 /* User provided milliseconds */ +#elif !defined(CONFIG_STM32_I2CTIMEOMS) +# define CONFIG_STM32_I2CTIMEOMS 0 /* User provided seconds */ #endif /* Interrupt wait time timeout in system timer ticks */ -#ifndef CONFIG_STM32H5_I2CTIMEOTICKS -# define CONFIG_STM32H5_I2CTIMEOTICKS \ - (SEC2TICK(CONFIG_STM32H5_I2CTIMEOSEC) + MSEC2TICK(CONFIG_STM32H5_I2CTIMEOMS)) +#ifndef CONFIG_STM32_I2CTIMEOTICKS +# define CONFIG_STM32_I2CTIMEOTICKS \ + (SEC2TICK(CONFIG_STM32_I2CTIMEOSEC) + MSEC2TICK(CONFIG_STM32_I2CTIMEOMS)) #endif -#ifndef CONFIG_STM32H5_I2C_DYNTIMEO_STARTSTOP -# define CONFIG_STM32H5_I2C_DYNTIMEO_STARTSTOP TICK2USEC(CONFIG_STM32H5_I2CTIMEOTICKS) +#ifndef CONFIG_STM32_I2C_DYNTIMEO_STARTSTOP +# define CONFIG_STM32_I2C_DYNTIMEO_STARTSTOP TICK2USEC(CONFIG_STM32_I2CTIMEOTICKS) #endif /* Macros to convert a I2C pin to a GPIO output */ @@ -443,9 +443,9 @@ static inline void stm32_i2c_putreg32(struct stm32_i2c_priv_s *priv, static inline void stm32_i2c_modifyreg32(struct stm32_i2c_priv_s *priv, uint8_t offset, uint32_t clearbits, uint32_t setbits); -#ifdef CONFIG_STM32H5_I2C_DYNTIMEO +#ifdef CONFIG_STM32_I2C_DYNTIMEO static uint32_t stm32_i2c_toticks(int msgc, struct i2c_msg_s *msgs); -#endif /* CONFIG_STM32H5_I2C_DYNTIMEO */ +#endif /* CONFIG_STM32_I2C_DYNTIMEO */ static inline int stm32_i2c_sem_waitdone(struct stm32_i2c_priv_s *priv); static inline void stm32_i2c_sem_waitstop(struct stm32_i2c_priv_s *priv); #ifdef CONFIG_I2C_TRACE @@ -485,7 +485,7 @@ static int stm32_i2c_pm_prepare(struct pm_callback_s *cb, int domain, * Private Data ****************************************************************************/ -#ifdef CONFIG_STM32H5_I2C1 +#ifdef CONFIG_STM32_I2C1 static const struct stm32_i2c_config_s stm32_i2c1_config = { .base = STM32_I2C1_BASE, @@ -523,7 +523,7 @@ static struct stm32_i2c_priv_s stm32_i2c1_priv = }; #endif -#ifdef CONFIG_STM32H5_I2C2 +#ifdef CONFIG_STM32_I2C2 static const struct stm32_i2c_config_s stm32_i2c2_config = { .base = STM32_I2C2_BASE, @@ -561,7 +561,7 @@ static struct stm32_i2c_priv_s stm32_i2c2_priv = }; #endif -#ifdef CONFIG_STM32H5_I2C3 +#ifdef CONFIG_STM32_I2C3 static const struct stm32_i2c_config_s stm32_i2c3_config = { .base = STM32_I2C3_BASE, @@ -599,7 +599,7 @@ static struct stm32_i2c_priv_s stm32_i2c3_priv = }; #endif -#ifdef CONFIG_STM32H5_I2C4 +#ifdef CONFIG_STM32_I2C4 static const struct stm32_i2c_config_s stm32_i2c4_config = { .base = STM32_I2C4_BASE, @@ -731,7 +731,7 @@ static inline void stm32_i2c_modifyreg32(struct stm32_i2c_priv_s *priv, * ****************************************************************************/ -#ifdef CONFIG_STM32H5_I2C_DYNTIMEO +#ifdef CONFIG_STM32_I2C_DYNTIMEO static uint32_t stm32_i2c_toticks(int msgc, struct i2c_msg_s *msgs) { size_t bytecount = 0; @@ -748,7 +748,7 @@ static uint32_t stm32_i2c_toticks(int msgc, struct i2c_msg_s *msgs) * factor. */ - return USEC2TICK(CONFIG_STM32H5_I2C_DYNTIMEO_USECPERBYTE * bytecount); + return USEC2TICK(CONFIG_STM32_I2C_DYNTIMEO_USECPERBYTE * bytecount); } #endif @@ -804,12 +804,12 @@ static inline int stm32_i2c_sem_waitdone(struct stm32_i2c_priv_s *priv) { /* Wait until either the transfer is complete or the timeout expires */ -#ifdef CONFIG_STM32H5_I2C_DYNTIMEO +#ifdef CONFIG_STM32_I2C_DYNTIMEO ret = nxsem_tickwait_uninterruptible(&priv->sem_isr, stm32_i2c_toticks(priv->msgc, priv->msgv)); #else ret = nxsem_tickwait_uninterruptible(&priv->sem_isr, - CONFIG_STM32H5_I2CTIMEOTICKS); + CONFIG_STM32_I2CTIMEOTICKS); #endif if (ret < 0) { @@ -847,10 +847,10 @@ static inline int stm32_i2c_sem_waitdone(struct stm32_i2c_priv_s *priv) /* Get the timeout value */ -#ifdef CONFIG_STM32H5_I2C_DYNTIMEO +#ifdef CONFIG_STM32_I2C_DYNTIMEO timeout = stm32_i2c_toticks(priv->msgc, priv->msgv); #else - timeout = CONFIG_STM32H5_I2CTIMEOTICKS; + timeout = CONFIG_STM32_I2CTIMEOTICKS; #endif /* Signal the interrupt handler that we are waiting. NOTE: Interrupts @@ -988,10 +988,10 @@ static inline void stm32_i2c_sem_waitstop(struct stm32_i2c_priv_s *priv) /* Select a timeout */ -#ifdef CONFIG_STM32H5_I2C_DYNTIMEO - timeout = USEC2TICK(CONFIG_STM32H5_I2C_DYNTIMEO_STARTSTOP); +#ifdef CONFIG_STM32_I2C_DYNTIMEO + timeout = USEC2TICK(CONFIG_STM32_I2C_DYNTIMEO_STARTSTOP); #else - timeout = CONFIG_STM32H5_I2CTIMEOTICKS; + timeout = CONFIG_STM32_I2CTIMEOTICKS; #endif /* Wait as stop might still be in progress */ @@ -1283,82 +1283,82 @@ static void stm32_i2c_setclock(struct stm32_i2c_priv_s *priv, switch (priv->config->base) { -#ifdef CONFIG_STM32H5_I2C1 +#ifdef CONFIG_STM32_I2C1 case STM32_I2C1_BASE: -# if defined(CONFIG_STM32H5_I2C1_CLK_HSI) +# if defined(CONFIG_STM32_I2C1_CLK_HSI) i2c_ker_ck = STM32_HSI_FREQUENCY; -# elif defined(CONFIG_STM32H5_I2C1_CLK_CSI) +# elif defined(CONFIG_STM32_I2C1_CLK_CSI) i2c_ker_ck = STM32_CSI_FREQUENCY; -# elif defined(CONFIG_STM32H5_I2C1_CLK_PCLK1) +# elif defined(CONFIG_STM32_I2C1_CLK_PCLK1) i2c_ker_ck = STM32_PCLK1_FREQUENCY; # else i2c_ker_ck = STM32_PLL3R_FREQUENCY; # endif - anfoff = CONFIG_STM32H5_I2C1_ANFOFF; - dnf = CONFIG_STM32H5_I2C1_DNF; -# ifdef CONFIG_STM32H5_I2C1_RF_OVERRIDE - tr_max = CONFIG_STM32H5_I2C1_RISE; - tf_max = CONFIG_STM32H5_I2C1_FALL; + anfoff = CONFIG_STM32_I2C1_ANFOFF; + dnf = CONFIG_STM32_I2C1_DNF; +# ifdef CONFIG_STM32_I2C1_RF_OVERRIDE + tr_max = CONFIG_STM32_I2C1_RISE; + tf_max = CONFIG_STM32_I2C1_FALL; rf_override = true; # endif break; #endif -#ifdef CONFIG_STM32H5_I2C2 +#ifdef CONFIG_STM32_I2C2 case STM32_I2C2_BASE: -# if defined(CONFIG_STM32H5_I2C2_CLK_HSI) +# if defined(CONFIG_STM32_I2C2_CLK_HSI) i2c_ker_ck = STM32_HSI_FREQUENCY; -# elif defined(CONFIG_STM32H5_I2C2_CLK_CSI) +# elif defined(CONFIG_STM32_I2C2_CLK_CSI) i2c_ker_ck = STM32_CSI_FREQUENCY; -# elif defined(CONFIG_STM32H5_I2C2_CLK_PCLK1) +# elif defined(CONFIG_STM32_I2C2_CLK_PCLK1) i2c_ker_ck = STM32_PCLK1_FREQUENCY; # else i2c_ker_ck = STM32_PLL3R_FREQUENCY; # endif - anfoff = CONFIG_STM32H5_I2C2_ANFOFF; - dnf = CONFIG_STM32H5_I2C2_DNF; -# ifdef CONFIG_STM32H5_I2C2_RF_OVERRIDE - tr_max = CONFIG_STM32H5_I2C2_RISE; - tf_max = CONFIG_STM32H5_I2C2_FALL; + anfoff = CONFIG_STM32_I2C2_ANFOFF; + dnf = CONFIG_STM32_I2C2_DNF; +# ifdef CONFIG_STM32_I2C2_RF_OVERRIDE + tr_max = CONFIG_STM32_I2C2_RISE; + tf_max = CONFIG_STM32_I2C2_FALL; rf_override = true; # endif break; #endif -#ifdef CONFIG_STM32H5_I2C3 +#ifdef CONFIG_STM32_I2C3 case STM32_I2C3_BASE: -# if defined(CONFIG_STM32H5_I2C3_CLK_HSI) +# if defined(CONFIG_STM32_I2C3_CLK_HSI) i2c_ker_ck = STM32_HSI_FREQUENCY; -# elif defined(CONFIG_STM32H5_I2C3_CLK_CSI) +# elif defined(CONFIG_STM32_I2C3_CLK_CSI) i2c_ker_ck = STM32_CSI_FREQUENCY; -# elif defined(CONFIG_STM32H5_I2C3_CLK_PCLK3) +# elif defined(CONFIG_STM32_I2C3_CLK_PCLK3) i2c_ker_ck = STM32_PCLK3_FREQUENCY; # else i2c_ker_ck = STM32_PLL3R_FREQUENCY; # endif - anfoff = CONFIG_STM32H5_I2C3_ANFOFF; - dnf = CONFIG_STM32H5_I2C3_DNF; -# ifdef CONFIG_STM32H5_I2C3_RF_OVERRIDE - tr_max = CONFIG_STM32H5_I2C3_RISE; - tf_max = CONFIG_STM32H5_I2C3_FALL; + anfoff = CONFIG_STM32_I2C3_ANFOFF; + dnf = CONFIG_STM32_I2C3_DNF; +# ifdef CONFIG_STM32_I2C3_RF_OVERRIDE + tr_max = CONFIG_STM32_I2C3_RISE; + tf_max = CONFIG_STM32_I2C3_FALL; rf_override = true; # endif break; #endif -#ifdef CONFIG_STM32H5_I2C4 +#ifdef CONFIG_STM32_I2C4 case STM32_I2C4_BASE: -# if defined(CONFIG_STM32H5_I2C4_CLK_HSI) +# if defined(CONFIG_STM32_I2C4_CLK_HSI) i2c_ker_ck = STM32_HSI_FREQUENCY; -# elif defined(CONFIG_STM32H5_I2C4_CLK_CSI) +# elif defined(CONFIG_STM32_I2C4_CLK_CSI) i2c_ker_ck = STM32_CSI_FREQUENCY; -# elif defined(CONFIG_STM32H5_I2C4_CLK_PCLK3) +# elif defined(CONFIG_STM32_I2C4_CLK_PCLK3) i2c_ker_ck = STM32_PCLK3_FREQUENCY; # else i2c_ker_ck = STM32_PLL3R_FREQUENCY; # endif - anfoff = CONFIG_STM32H5_I2C4_ANFOFF; - dnf = CONFIG_STM32H5_I2C4_DNF; -# ifdef CONFIG_STM32H5_I2C4_RF_OVERRIDE - tr_max = CONFIG_STM32H5_I2C4_RISE; - tf_max = CONFIG_STM32H5_I2C4_FALL; + anfoff = CONFIG_STM32_I2C4_ANFOFF; + dnf = CONFIG_STM32_I2C4_DNF; +# ifdef CONFIG_STM32_I2C4_RF_OVERRIDE + tr_max = CONFIG_STM32_I2C4_RISE; + tf_max = CONFIG_STM32_I2C4_FALL; rf_override = true; # endif break; @@ -2387,17 +2387,17 @@ static int stm32_i2c_init(struct stm32_i2c_priv_s *priv) switch (priv->config->base) { -#ifdef CONFIG_STM32H5_I2C1 +#ifdef CONFIG_STM32_I2C1 case STM32_I2C1_BASE: -# if defined(CONFIG_STM32H5_I2C1_CLK_HSI) +# if defined(CONFIG_STM32_I2C1_CLK_HSI) modifyreg32(STM32_RCC_CCIPR4, RCC_CCIPR4_I2C1SEL_MASK, RCC_CCIPR4_I2C1SEL_HSIKERCK); -# elif defined(CONFIG_STM32H5_I2C1_CLK_CSI) +# elif defined(CONFIG_STM32_I2C1_CLK_CSI) modifyreg32(STM32_RCC_CCIPR4, RCC_CCIPR4_I2C1SEL_MASK, RCC_CCIPR4_I2C1SEL_CSIKERCK); -# elif defined(CONFIG_STM32H5_I2C1_CLK_PCLK1) +# elif defined(CONFIG_STM32_I2C1_CLK_PCLK1) modifyreg32(STM32_RCC_CCIPR4, RCC_CCIPR4_I2C1SEL_MASK, RCC_CCIPR4_I2C1SEL_RCCPCLK1); @@ -2408,17 +2408,17 @@ static int stm32_i2c_init(struct stm32_i2c_priv_s *priv) # endif break; #endif -#ifdef CONFIG_STM32H5_I2C2 +#ifdef CONFIG_STM32_I2C2 case STM32_I2C2_BASE: -# if defined(CONFIG_STM32H5_I2C2_CLK_HSI) +# if defined(CONFIG_STM32_I2C2_CLK_HSI) modifyreg32(STM32_RCC_CCIPR4, RCC_CCIPR4_I2C2SEL_MASK, RCC_CCIPR4_I2C2SEL_HSIKERCK); -# elif defined(CONFIG_STM32H5_I2C2_CLK_CSI) +# elif defined(CONFIG_STM32_I2C2_CLK_CSI) modifyreg32(STM32_RCC_CCIPR4, RCC_CCIPR4_I2C2SEL_MASK, RCC_CCIPR4_I2C2SEL_CSIKERCK); -# elif defined(CONFIG_STM32H5_I2C2_CLK_PCLK1) +# elif defined(CONFIG_STM32_I2C2_CLK_PCLK1) modifyreg32(STM32_RCC_CCIPR4, RCC_CCIPR4_I2C2SEL_MASK, RCC_CCIPR4_I2C2SEL_PCLK1); @@ -2429,17 +2429,17 @@ static int stm32_i2c_init(struct stm32_i2c_priv_s *priv) # endif break; #endif -#ifdef CONFIG_STM32H5_I2C3 +#ifdef CONFIG_STM32_I2C3 case STM32_I2C3_BASE: -# if defined(CONFIG_STM32H5_I2C3_CLK_HSI) +# if defined(CONFIG_STM32_I2C3_CLK_HSI) modifyreg32(STM32_RCC_CCIPR4, RCC_CCIPR4_I2C3SEL_MASK, RCC_CCIPR4_I2C3SEL_HSIKERCK); -# elif defined(CONFIG_STM32H5_I2C3_CLK_CSI) +# elif defined(CONFIG_STM32_I2C3_CLK_CSI) modifyreg32(STM32_RCC_CCIPR4, RCC_CCIPR4_I2C3SEL_MASK, RCC_CCIPR4_I2C3SEL_CSIKERCK); -# elif defined(CONFIG_STM32H5_I2C3_CLK_PCLK3) +# elif defined(CONFIG_STM32_I2C3_CLK_PCLK3) modifyreg32(STM32_RCC_CCIPR4, RCC_CCIPR4_I2C3SEL_MASK, RCC_CCIPR4_I2C3SEL_PCLK3); @@ -2450,17 +2450,17 @@ static int stm32_i2c_init(struct stm32_i2c_priv_s *priv) # endif break; #endif -#ifdef CONFIG_STM32H5_I2C4 +#ifdef CONFIG_STM32_I2C4 case STM32_I2C4_BASE: -# if defined(CONFIG_STM32H5_I2C4_CLK_HSI) +# if defined(CONFIG_STM32_I2C4_CLK_HSI) modifyreg32(STM32_RCC_CCIPR4, RCC_CCIPR4_I2C4SEL_MASK, RCC_CCIPR4_I2C4SEL_HSIKERCK); -# elif defined(CONFIG_STM32H5_I2C4_CLK_CSI) +# elif defined(CONFIG_STM32_I2C4_CLK_CSI) modifyreg32(STM32_RCC_CCIPR4, RCC_CCIPR4_I2C4SEL_MASK, RCC_CCIPR4_I2C4SEL_CSIKERCK); -# elif defined(CONFIG_STM32H5_I2C4_CLK_PCLK3) +# elif defined(CONFIG_STM32_I2C4_CLK_PCLK3) modifyreg32(STM32_RCC_CCIPR4, RCC_CCIPR4_I2C4SEL_MASK, RCC_CCIPR4_I2C4SEL_PCLK3); @@ -3016,22 +3016,22 @@ struct i2c_master_s *stm32_i2cbus_initialize(int port) switch (port) { -#ifdef CONFIG_STM32H5_I2C1 +#ifdef CONFIG_STM32_I2C1 case 1: priv = (struct stm32_i2c_priv_s *)&stm32_i2c1_priv; break; #endif -#ifdef CONFIG_STM32H5_I2C2 +#ifdef CONFIG_STM32_I2C2 case 2: priv = (struct stm32_i2c_priv_s *)&stm32_i2c2_priv; break; #endif -#ifdef CONFIG_STM32H5_I2C3 +#ifdef CONFIG_STM32_I2C3 case 3: priv = (struct stm32_i2c_priv_s *)&stm32_i2c3_priv; break; #endif -#ifdef CONFIG_STM32H5_I2C4 +#ifdef CONFIG_STM32_I2C4 case 4: priv = (struct stm32_i2c_priv_s *)&stm32_i2c4_priv; break; @@ -3117,5 +3117,5 @@ int stm32_i2cbus_uninitialize(struct i2c_master_s *dev) return OK; } -#endif /* CONFIG_STM32H5_I2C1 || CONFIG_STM32H5_I2C2 || \ - * CONFIG_STM32H5_I2C3 || CONFIG_STM32H5_I2C4 */ +#endif /* CONFIG_STM32_I2C1 || CONFIG_STM32_I2C2 || \ + * CONFIG_STM32_I2C3 || CONFIG_STM32_I2C4 */ diff --git a/arch/arm/src/stm32h5/stm32_i2c.h b/arch/arm/src/stm32h5/stm32_i2c.h index ceb6a7091cd61..87c3f6a1b027a 100644 --- a/arch/arm/src/stm32h5/stm32_i2c.h +++ b/arch/arm/src/stm32h5/stm32_i2c.h @@ -41,10 +41,10 @@ * seconds per byte value must be provided as well. */ -#ifdef CONFIG_STM32H5_I2C_DYNTIMEO -# if CONFIG_STM32H5_I2C_DYNTIMEO_USECPERBYTE < 1 -# warning "Ignoring CONFIG_STM32H5_I2C_DYNTIMEO because of CONFIG_STM32H5_I2C_DYNTIMEO_USECPERBYTE" -# undef CONFIG_STM32H5_I2C_DYNTIMEO +#ifdef CONFIG_STM32_I2C_DYNTIMEO +# if CONFIG_STM32_I2C_DYNTIMEO_USECPERBYTE < 1 +# warning "Ignoring CONFIG_STM32_I2C_DYNTIMEO because of CONFIG_STM32_I2C_DYNTIMEO_USECPERBYTE" +# undef CONFIG_STM32_I2C_DYNTIMEO # endif #endif diff --git a/arch/arm/src/stm32h5/stm32_icache.c b/arch/arm/src/stm32h5/stm32_icache.c index 8cd9c0483eec4..2aa578d6723c0 100644 --- a/arch/arm/src/stm32h5/stm32_icache.c +++ b/arch/arm/src/stm32h5/stm32_icache.c @@ -40,8 +40,8 @@ * Pre-processor Definitions ****************************************************************************/ -#define STM32H5_ICACHE_INTERRUPT (defined(CONFIG_STM32H5_ICACHE_INV_INT) ||\ - defined(CONFIG_STM32H5_ICACHE_ERR_INT)) +#define STM32_ICACHE_INTERRUPT (defined(CONFIG_STM32_ICACHE_INV_INT) ||\ + defined(CONFIG_STM32_ICACHE_ERR_INT)) /**************************************************************************** * Private Types @@ -82,51 +82,51 @@ static struct stm32_icache_s icache1 = .lock = SP_UNLOCKED, }; -#ifdef CONFIG_STM32H5_ICACHE_REGION0 +#ifdef CONFIG_STM32_ICACHE_REGION0 static struct stm32_icache_region region0 = { .num = 0, - .baseaddr = CONFIG_STM32H5_ICACHE_REGION0_BADDR, - .rsize = CONFIG_STM32H5_ICACHE_REGION0_RSIZE, - .remapaddr = CONFIG_STM32H5_ICACHE_REGION0_REMAPADDR, - .mstsel = CONFIG_STM32H5_ICACHE_REGION0_MSTSEL, - .hburst = CONFIG_STM32H5_ICACHE_REGION0_HBURST, + .baseaddr = CONFIG_STM32_ICACHE_REGION0_BADDR, + .rsize = CONFIG_STM32_ICACHE_REGION0_RSIZE, + .remapaddr = CONFIG_STM32_ICACHE_REGION0_REMAPADDR, + .mstsel = CONFIG_STM32_ICACHE_REGION0_MSTSEL, + .hburst = CONFIG_STM32_ICACHE_REGION0_HBURST, }; #endif -#ifdef CONFIG_STM32H5_ICACHE_REGION1 +#ifdef CONFIG_STM32_ICACHE_REGION1 static struct stm32_icache_region region1 = { .num = 1, - .baseaddr = CONFIG_STM32H5_ICACHE_REGION1_BADDR, - .rsize = CONFIG_STM32H5_ICACHE_REGION1_RSIZE, - .remapaddr = CONFIG_STM32H5_ICACHE_REGION1_REMAPADDR, - .mstsel = CONFIG_STM32H5_ICACHE_REGION1_MSTSEL, - .hburst = CONFIG_STM32H5_ICACHE_REGION1_HBURST, + .baseaddr = CONFIG_STM32_ICACHE_REGION1_BADDR, + .rsize = CONFIG_STM32_ICACHE_REGION1_RSIZE, + .remapaddr = CONFIG_STM32_ICACHE_REGION1_REMAPADDR, + .mstsel = CONFIG_STM32_ICACHE_REGION1_MSTSEL, + .hburst = CONFIG_STM32_ICACHE_REGION1_HBURST, }; #endif -#ifdef CONFIG_STM32H5_ICACHE_REGION2 +#ifdef CONFIG_STM32_ICACHE_REGION2 static struct stm32_icache_region region2 = { .num = 2, - .baseaddr = CONFIG_STM32H5_ICACHE_REGION2_BADDR, - .rsize = CONFIG_STM32H5_ICACHE_REGION2_RSIZE, - .remapaddr = CONFIG_STM32H5_ICACHE_REGION2_REMAPADDR, - .mstsel = CONFIG_STM32H5_ICACHE_REGION2_MSTSEL, - .hburst = CONFIG_STM32H5_ICACHE_REGION2_HBURST, + .baseaddr = CONFIG_STM32_ICACHE_REGION2_BADDR, + .rsize = CONFIG_STM32_ICACHE_REGION2_RSIZE, + .remapaddr = CONFIG_STM32_ICACHE_REGION2_REMAPADDR, + .mstsel = CONFIG_STM32_ICACHE_REGION2_MSTSEL, + .hburst = CONFIG_STM32_ICACHE_REGION2_HBURST, }; #endif -#ifdef CONFIG_STM32H5_ICACHE_REGION3 +#ifdef CONFIG_STM32_ICACHE_REGION3 static struct stm32_icache_region region3 = { .num = 3, - .baseaddr = CONFIG_STM32H5_ICACHE_REGION3_BADDR, - .rsize = CONFIG_STM32H5_ICACHE_REGION3_RSIZE, - .remapaddr = CONFIG_STM32H5_ICACHE_REGION3_REMAPADDR, - .mstsel = CONFIG_STM32H5_ICACHE_REGION3_MSTSEL, - .hburst = CONFIG_STM32H5_ICACHE_REGION3_HBURST, + .baseaddr = CONFIG_STM32_ICACHE_REGION3_BADDR, + .rsize = CONFIG_STM32_ICACHE_REGION3_RSIZE, + .remapaddr = CONFIG_STM32_ICACHE_REGION3_REMAPADDR, + .mstsel = CONFIG_STM32_ICACHE_REGION3_MSTSEL, + .hburst = CONFIG_STM32_ICACHE_REGION3_HBURST, }; #endif @@ -235,7 +235,7 @@ void stm32_icache_initialize(void) /* Set associativity */ -#ifdef CONFIG_STM32H5_ICACHE_DIRECT +#ifdef CONFIG_STM32_ICACHE_DIRECT regval = getreg32(STM32_ICACHE_CR); regval &= ~(ICACHE_CR_WAYSEL); putreg32(regval, STM32_ICACHE_CR); @@ -246,27 +246,27 @@ void stm32_icache_initialize(void) * Reset Monitors on Initialization */ -#ifdef CONFIG_STM32H5_ICACHE_MONITOR_EN +#ifdef CONFIG_STM32_ICACHE_MONITOR_EN stm32_icache_enable_monitors(); stm32_icache_reset_monitors(); #endif /* Set up region configuration registers */ -#ifdef CONFIG_STM32H5_ICACHE_REGION0 +#ifdef CONFIG_STM32_ICACHE_REGION0 stm32_icache_setup_region(region0); #endif -#ifdef CONFIG_STM32H5_ICACHE_REGION1 +#ifdef CONFIG_STM32_ICACHE_REGION1 stm32_icache_setup_region(region1); #endif -#ifdef CONFIG_STM32H5_ICACHE_REGION2 +#ifdef CONFIG_STM32_ICACHE_REGION2 stm32_icache_setup_region(region2); #endif -#ifdef CONFIG_STM32H5_ICACHE_REGION3 +#ifdef CONFIG_STM32_ICACHE_REGION3 stm32_icache_setup_region(region3); #endif -#if STM32H5_ICACHE_INTERRUPT +#if STM32_ICACHE_INTERRUPT /* Attach ISR */ int ret; @@ -278,10 +278,10 @@ void stm32_icache_initialize(void) if (ret == OK) { regval = 0; -# ifdef CONFIG_STM32H5_ICACHE_INV_INT +# ifdef CONFIG_STM32_ICACHE_INV_INT regval |= ICACHE_IER_BSYENDIE; # endif -# ifdef CONFIG_STM32H5_ICACHE_ERR_INT +# ifdef CONFIG_STM32_ICACHE_ERR_INT regval |= ICACHE_IER_ERRIE; # endif stm32_icache_set_ier(regval); @@ -358,7 +358,7 @@ void stm32_invalidate_icache(void) regval |= ICACHE_CR_CACHEINV; putreg32(regval, STM32_ICACHE_CR); -#if defined(CONFIG_STM32H5_ICACHE_INV_INT) +#if defined(CONFIG_STM32_ICACHE_INV_INT) stm32_icache_invf_interrupt(); #else stm32_icache_invf_poll(); diff --git a/arch/arm/src/stm32h5/stm32_idle.c b/arch/arm/src/stm32h5/stm32_idle.c index fdde8d81b1fa0..5cc08c4759b40 100644 --- a/arch/arm/src/stm32h5/stm32_idle.c +++ b/arch/arm/src/stm32h5/stm32_idle.c @@ -92,7 +92,7 @@ void up_idle(void) /* Sleep until an interrupt occurs to save power. */ -#if !(defined(CONFIG_DEBUG_SYMBOLS) && defined(CONFIG_STM32H5_DISABLE_IDLE_SLEEP_DURING_DEBUG)) +#if !(defined(CONFIG_DEBUG_SYMBOLS) && defined(CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG)) BEGIN_IDLE(); asm("WFI"); END_IDLE(); diff --git a/arch/arm/src/stm32h5/stm32_lowputc.c b/arch/arm/src/stm32h5/stm32_lowputc.c index 7de76e7300c85..16a0a6131663a 100644 --- a/arch/arm/src/stm32h5/stm32_lowputc.c +++ b/arch/arm/src/stm32h5/stm32_lowputc.c @@ -46,260 +46,260 @@ #ifdef HAVE_CONSOLE # if defined(CONFIG_LPUART1_SERIAL_CONSOLE) -# define STM32H5_CONSOLE_BASE STM32_LPUART1_BASE -# define STM32H5_APBCLOCK STM32_PCLK1_FREQUENCY -# define STM32H5_CONSOLE_APBREG STM32_RCC_APB3ENR -# define STM32H5_CONSOLE_APBEN RCC_APB3ENR_LPUART1EN -# define STM32H5_CONSOLE_BAUD CONFIG_LPUART1_BAUD -# define STM32H5_CONSOLE_BITS CONFIG_LPUART1_BITS -# define STM32H5_CONSOLE_PARITY CONFIG_LPUART1_PARITY -# define STM32H5_CONSOLE_2STOP CONFIG_LPUART1_2STOP -# define STM32H5_CONSOLE_TX GPIO_LPUART1_TX -# define STM32H5_CONSOLE_RX GPIO_LPUART1_RX +# define STM32_CONSOLE_BASE STM32_LPUART1_BASE +# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY +# define STM32_CONSOLE_APBREG STM32_RCC_APB3ENR +# define STM32_CONSOLE_APBEN RCC_APB3ENR_LPUART1EN +# define STM32_CONSOLE_BAUD CONFIG_LPUART1_BAUD +# define STM32_CONSOLE_BITS CONFIG_LPUART1_BITS +# define STM32_CONSOLE_PARITY CONFIG_LPUART1_PARITY +# define STM32_CONSOLE_2STOP CONFIG_LPUART1_2STOP +# define STM32_CONSOLE_TX GPIO_LPUART1_TX +# define STM32_CONSOLE_RX GPIO_LPUART1_RX # ifdef CONFIG_LPUART1_RS485 -# define STM32H5_CONSOLE_RS485_DIR GPIO_LPUART1_RS485_DIR +# define STM32_CONSOLE_RS485_DIR GPIO_LPUART1_RS485_DIR # if (CONFIG_LPUART1_RS485_DIR_POLARITY == 0) -# define STM32H5_CONSOLE_RS485_DIR_POLARITY false +# define STM32_CONSOLE_RS485_DIR_POLARITY false # else -# define STM32H5_CONSOLE_RS485_DIR_POLARITY true +# define STM32_CONSOLE_RS485_DIR_POLARITY true # endif # endif # elif defined(CONFIG_USART1_SERIAL_CONSOLE) -# define STM32H5_CONSOLE_BASE STM32_USART1_BASE -# define STM32H5_APBCLOCK STM32_PCLK2_FREQUENCY -# define STM32H5_CONSOLE_APBREG STM32_RCC_APB2ENR -# define STM32H5_CONSOLE_APBEN RCC_APB2ENR_USART1EN -# define STM32H5_CONSOLE_BAUD CONFIG_USART1_BAUD -# define STM32H5_CONSOLE_BITS CONFIG_USART1_BITS -# define STM32H5_CONSOLE_PARITY CONFIG_USART1_PARITY -# define STM32H5_CONSOLE_2STOP CONFIG_USART1_2STOP -# define STM32H5_CONSOLE_TX GPIO_USART1_TX -# define STM32H5_CONSOLE_RX GPIO_USART1_RX +# define STM32_CONSOLE_BASE STM32_USART1_BASE +# define STM32_APBCLOCK STM32_PCLK2_FREQUENCY +# define STM32_CONSOLE_APBREG STM32_RCC_APB2ENR +# define STM32_CONSOLE_APBEN RCC_APB2ENR_USART1EN +# define STM32_CONSOLE_BAUD CONFIG_USART1_BAUD +# define STM32_CONSOLE_BITS CONFIG_USART1_BITS +# define STM32_CONSOLE_PARITY CONFIG_USART1_PARITY +# define STM32_CONSOLE_2STOP CONFIG_USART1_2STOP +# define STM32_CONSOLE_TX GPIO_USART1_TX +# define STM32_CONSOLE_RX GPIO_USART1_RX # ifdef CONFIG_USART1_RS485 -# define STM32H5_CONSOLE_RS485_DIR GPIO_USART1_RS485_DIR +# define STM32_CONSOLE_RS485_DIR GPIO_USART1_RS485_DIR # if (CONFIG_USART1_RS485_DIR_POLARITY == 0) -# define STM32H5_CONSOLE_RS485_DIR_POLARITY false +# define STM32_CONSOLE_RS485_DIR_POLARITY false # else -# define STM32H5_CONSOLE_RS485_DIR_POLARITY true +# define STM32_CONSOLE_RS485_DIR_POLARITY true # endif # endif # elif defined(CONFIG_USART2_SERIAL_CONSOLE) -# define STM32H5_CONSOLE_BASE STM32_USART2_BASE -# define STM32H5_APBCLOCK STM32_PCLK1_FREQUENCY -# define STM32H5_CONSOLE_APBREG STM32_RCC_APB1LENR -# define STM32H5_CONSOLE_APBEN RCC_APB1LENR_USART2EN -# define STM32H5_CONSOLE_BAUD CONFIG_USART2_BAUD -# define STM32H5_CONSOLE_BITS CONFIG_USART2_BITS -# define STM32H5_CONSOLE_PARITY CONFIG_USART2_PARITY -# define STM32H5_CONSOLE_2STOP CONFIG_USART2_2STOP -# define STM32H5_CONSOLE_TX GPIO_USART2_TX -# define STM32H5_CONSOLE_RX GPIO_USART2_RX +# define STM32_CONSOLE_BASE STM32_USART2_BASE +# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY +# define STM32_CONSOLE_APBREG STM32_RCC_APB1LENR +# define STM32_CONSOLE_APBEN RCC_APB1LENR_USART2EN +# define STM32_CONSOLE_BAUD CONFIG_USART2_BAUD +# define STM32_CONSOLE_BITS CONFIG_USART2_BITS +# define STM32_CONSOLE_PARITY CONFIG_USART2_PARITY +# define STM32_CONSOLE_2STOP CONFIG_USART2_2STOP +# define STM32_CONSOLE_TX GPIO_USART2_TX +# define STM32_CONSOLE_RX GPIO_USART2_RX # ifdef CONFIG_USART2_RS485 -# define STM32H5_CONSOLE_RS485_DIR GPIO_USART2_RS485_DIR +# define STM32_CONSOLE_RS485_DIR GPIO_USART2_RS485_DIR # if (CONFIG_USART2_RS485_DIR_POLARITY == 0) -# define STM32H5_CONSOLE_RS485_DIR_POLARITY false +# define STM32_CONSOLE_RS485_DIR_POLARITY false # else -# define STM32H5_CONSOLE_RS485_DIR_POLARITY true +# define STM32_CONSOLE_RS485_DIR_POLARITY true # endif # endif # elif defined(CONFIG_USART3_SERIAL_CONSOLE) -# define STM32H5_CONSOLE_BASE STM32_USART3_BASE -# define STM32H5_APBCLOCK STM32_PCLK1_FREQUENCY -# define STM32H5_CONSOLE_APBREG STM32_RCC_APB1LENR -# define STM32H5_CONSOLE_APBEN RCC_APB1LENR_USART3EN -# define STM32H5_CONSOLE_BAUD CONFIG_USART3_BAUD -# define STM32H5_CONSOLE_BITS CONFIG_USART3_BITS -# define STM32H5_CONSOLE_PARITY CONFIG_USART3_PARITY -# define STM32H5_CONSOLE_2STOP CONFIG_USART3_2STOP -# define STM32H5_CONSOLE_TX GPIO_USART3_TX -# define STM32H5_CONSOLE_RX GPIO_USART3_RX +# define STM32_CONSOLE_BASE STM32_USART3_BASE +# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY +# define STM32_CONSOLE_APBREG STM32_RCC_APB1LENR +# define STM32_CONSOLE_APBEN RCC_APB1LENR_USART3EN +# define STM32_CONSOLE_BAUD CONFIG_USART3_BAUD +# define STM32_CONSOLE_BITS CONFIG_USART3_BITS +# define STM32_CONSOLE_PARITY CONFIG_USART3_PARITY +# define STM32_CONSOLE_2STOP CONFIG_USART3_2STOP +# define STM32_CONSOLE_TX GPIO_USART3_TX +# define STM32_CONSOLE_RX GPIO_USART3_RX # ifdef CONFIG_USART3_RS485 -# define STM32H5_CONSOLE_RS485_DIR GPIO_USART3_RS485_DIR +# define STM32_CONSOLE_RS485_DIR GPIO_USART3_RS485_DIR # if (CONFIG_USART3_RS485_DIR_POLARITY == 0) -# define STM32H5_CONSOLE_RS485_DIR_POLARITY false +# define STM32_CONSOLE_RS485_DIR_POLARITY false # else -# define STM32H5_CONSOLE_RS485_DIR_POLARITY true +# define STM32_CONSOLE_RS485_DIR_POLARITY true # endif # endif # elif defined(CONFIG_UART4_SERIAL_CONSOLE) -# define STM32H5_CONSOLE_BASE STM32_UART4_BASE -# define STM32H5_APBCLOCK STM32_PCLK1_FREQUENCY -# define STM32H5_CONSOLE_APBREG STM32_RCC_APB1LENR -# define STM32H5_CONSOLE_APBEN RCC_APB1LENR_UART4EN -# define STM32H5_CONSOLE_BAUD CONFIG_UART4_BAUD -# define STM32H5_CONSOLE_BITS CONFIG_UART4_BITS -# define STM32H5_CONSOLE_PARITY CONFIG_UART4_PARITY -# define STM32H5_CONSOLE_2STOP CONFIG_UART4_2STOP -# define STM32H5_CONSOLE_TX GPIO_UART4_TX -# define STM32H5_CONSOLE_RX GPIO_UART4_RX +# define STM32_CONSOLE_BASE STM32_UART4_BASE +# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY +# define STM32_CONSOLE_APBREG STM32_RCC_APB1LENR +# define STM32_CONSOLE_APBEN RCC_APB1LENR_UART4EN +# define STM32_CONSOLE_BAUD CONFIG_UART4_BAUD +# define STM32_CONSOLE_BITS CONFIG_UART4_BITS +# define STM32_CONSOLE_PARITY CONFIG_UART4_PARITY +# define STM32_CONSOLE_2STOP CONFIG_UART4_2STOP +# define STM32_CONSOLE_TX GPIO_UART4_TX +# define STM32_CONSOLE_RX GPIO_UART4_RX # ifdef CONFIG_UART4_RS485 -# define STM32H5_CONSOLE_RS485_DIR GPIO_UART4_RS485_DIR +# define STM32_CONSOLE_RS485_DIR GPIO_UART4_RS485_DIR # if (CONFIG_UART4_RS485_DIR_POLARITY == 0) -# define STM32H5_CONSOLE_RS485_DIR_POLARITY false +# define STM32_CONSOLE_RS485_DIR_POLARITY false # else -# define STM32H5_CONSOLE_RS485_DIR_POLARITY true +# define STM32_CONSOLE_RS485_DIR_POLARITY true # endif # endif # elif defined(CONFIG_UART5_SERIAL_CONSOLE) -# define STM32H5_CONSOLE_BASE STM32_UART5_BASE -# define STM32H5_APBCLOCK STM32_PCLK1_FREQUENCY -# define STM32H5_CONSOLE_APBREG STM32_RCC_APB1LENR -# define STM32H5_CONSOLE_APBEN RCC_APB1LENR_UART5EN -# define STM32H5_CONSOLE_BAUD CONFIG_UART5_BAUD -# define STM32H5_CONSOLE_BITS CONFIG_UART5_BITS -# define STM32H5_CONSOLE_PARITY CONFIG_UART5_PARITY -# define STM32H5_CONSOLE_2STOP CONFIG_UART5_2STOP -# define STM32H5_CONSOLE_TX GPIO_UART5_TX -# define STM32H5_CONSOLE_RX GPIO_UART5_RX +# define STM32_CONSOLE_BASE STM32_UART5_BASE +# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY +# define STM32_CONSOLE_APBREG STM32_RCC_APB1LENR +# define STM32_CONSOLE_APBEN RCC_APB1LENR_UART5EN +# define STM32_CONSOLE_BAUD CONFIG_UART5_BAUD +# define STM32_CONSOLE_BITS CONFIG_UART5_BITS +# define STM32_CONSOLE_PARITY CONFIG_UART5_PARITY +# define STM32_CONSOLE_2STOP CONFIG_UART5_2STOP +# define STM32_CONSOLE_TX GPIO_UART5_TX +# define STM32_CONSOLE_RX GPIO_UART5_RX # ifdef CONFIG_UART5_RS485 -# define STM32H5_CONSOLE_RS485_DIR GPIO_UART5_RS485_DIR +# define STM32_CONSOLE_RS485_DIR GPIO_UART5_RS485_DIR # if (CONFIG_UART5_RS485_DIR_POLARITY == 0) -# define STM32H5_CONSOLE_RS485_DIR_POLARITY false +# define STM32_CONSOLE_RS485_DIR_POLARITY false # else -# define STM32H5_CONSOLE_RS485_DIR_POLARITY true +# define STM32_CONSOLE_RS485_DIR_POLARITY true # endif # endif # elif defined(CONFIG_USART6_SERIAL_CONSOLE) -# define STM32H5_CONSOLE_BASE STM32_USART6_BASE -# define STM32H5_APBCLOCK STM32_PCLK1_FREQUENCY -# define STM32H5_CONSOLE_APBREG STM32_RCC_APB1LENR -# define STM32H5_CONSOLE_APBEN RCC_APB1LENR_USART6EN -# define STM32H5_CONSOLE_BAUD CONFIG_USART6_BAUD -# define STM32H5_CONSOLE_BITS CONFIG_USART6_BITS -# define STM32H5_CONSOLE_PARITY CONFIG_USART6_PARITY -# define STM32H5_CONSOLE_2STOP CONFIG_USART6_2STOP -# define STM32H5_CONSOLE_TX GPIO_USART6_TX -# define STM32H5_CONSOLE_RX GPIO_USART6_RX +# define STM32_CONSOLE_BASE STM32_USART6_BASE +# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY +# define STM32_CONSOLE_APBREG STM32_RCC_APB1LENR +# define STM32_CONSOLE_APBEN RCC_APB1LENR_USART6EN +# define STM32_CONSOLE_BAUD CONFIG_USART6_BAUD +# define STM32_CONSOLE_BITS CONFIG_USART6_BITS +# define STM32_CONSOLE_PARITY CONFIG_USART6_PARITY +# define STM32_CONSOLE_2STOP CONFIG_USART6_2STOP +# define STM32_CONSOLE_TX GPIO_USART6_TX +# define STM32_CONSOLE_RX GPIO_USART6_RX # ifdef CONFIG_USART6_RS485 -# define STM32H5_CONSOLE_RS485_DIR GPIO_USART6_RS485_DIR +# define STM32_CONSOLE_RS485_DIR GPIO_USART6_RS485_DIR # if (CONFIG_USART6_RS485_DIR_POLARITY == 0) -# define STM32H5_CONSOLE_RS485_DIR_POLARITY false +# define STM32_CONSOLE_RS485_DIR_POLARITY false # else -# define STM32H5_CONSOLE_RS485_DIR_POLARITY true +# define STM32_CONSOLE_RS485_DIR_POLARITY true # endif # endif # elif defined(CONFIG_UART7_SERIAL_CONSOLE) -# define STM32H5_CONSOLE_BASE STM32_UART7_BASE -# define STM32H5_APBCLOCK STM32_PCLK1_FREQUENCY -# define STM32H5_CONSOLE_APBREG STM32_RCC_APB1LENR -# define STM32H5_CONSOLE_APBEN RCC_APB1LENR_UART7EN -# define STM32H5_CONSOLE_BAUD CONFIG_UART7_BAUD -# define STM32H5_CONSOLE_BITS CONFIG_UART7_BITS -# define STM32H5_CONSOLE_PARITY CONFIG_UART7_PARITY -# define STM32H5_CONSOLE_2STOP CONFIG_UART7_2STOP -# define STM32H5_CONSOLE_TX GPIO_UART7_TX -# define STM32H5_CONSOLE_RX GPIO_UART7_RX +# define STM32_CONSOLE_BASE STM32_UART7_BASE +# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY +# define STM32_CONSOLE_APBREG STM32_RCC_APB1LENR +# define STM32_CONSOLE_APBEN RCC_APB1LENR_UART7EN +# define STM32_CONSOLE_BAUD CONFIG_UART7_BAUD +# define STM32_CONSOLE_BITS CONFIG_UART7_BITS +# define STM32_CONSOLE_PARITY CONFIG_UART7_PARITY +# define STM32_CONSOLE_2STOP CONFIG_UART7_2STOP +# define STM32_CONSOLE_TX GPIO_UART7_TX +# define STM32_CONSOLE_RX GPIO_UART7_RX # ifdef CONFIG_UART7_RS485 -# define STM32H5_CONSOLE_RS485_DIR GPIO_UART7_RS485_DIR +# define STM32_CONSOLE_RS485_DIR GPIO_UART7_RS485_DIR # if (CONFIG_UART7_RS485_DIR_POLARITY == 0) -# define STM32H5_CONSOLE_RS485_DIR_POLARITY false +# define STM32_CONSOLE_RS485_DIR_POLARITY false # else -# define STM32H5_CONSOLE_RS485_DIR_POLARITY true +# define STM32_CONSOLE_RS485_DIR_POLARITY true # endif # endif # elif defined(CONFIG_UART8_SERIAL_CONSOLE) -# define STM32H5_CONSOLE_BASE STM32_UART8_BASE -# define STM32H5_APBCLOCK STM32_PCLK1_FREQUENCY -# define STM32H5_CONSOLE_APBREG STM32_RCC_APB1LENR -# define STM32H5_CONSOLE_APBEN RCC_APB1LENR_UART8EN -# define STM32H5_CONSOLE_BAUD CONFIG_UART8_BAUD -# define STM32H5_CONSOLE_BITS CONFIG_UART8_BITS -# define STM32H5_CONSOLE_PARITY CONFIG_UART8_PARITY -# define STM32H5_CONSOLE_2STOP CONFIG_UART8_2STOP -# define STM32H5_CONSOLE_TX GPIO_UART8_TX -# define STM32H5_CONSOLE_RX GPIO_UART8_RX +# define STM32_CONSOLE_BASE STM32_UART8_BASE +# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY +# define STM32_CONSOLE_APBREG STM32_RCC_APB1LENR +# define STM32_CONSOLE_APBEN RCC_APB1LENR_UART8EN +# define STM32_CONSOLE_BAUD CONFIG_UART8_BAUD +# define STM32_CONSOLE_BITS CONFIG_UART8_BITS +# define STM32_CONSOLE_PARITY CONFIG_UART8_PARITY +# define STM32_CONSOLE_2STOP CONFIG_UART8_2STOP +# define STM32_CONSOLE_TX GPIO_UART8_TX +# define STM32_CONSOLE_RX GPIO_UART8_RX # ifdef CONFIG_UART8_RS485 -# define STM32H5_CONSOLE_RS485_DIR GPIO_UART8_RS485_DIR +# define STM32_CONSOLE_RS485_DIR GPIO_UART8_RS485_DIR # if (CONFIG_UART8_RS485_DIR_POLARITY == 0) -# define STM32H5_CONSOLE_RS485_DIR_POLARITY false +# define STM32_CONSOLE_RS485_DIR_POLARITY false # else -# define STM32H5_CONSOLE_RS485_DIR_POLARITY true +# define STM32_CONSOLE_RS485_DIR_POLARITY true # endif # endif # elif defined(CONFIG_UART9_SERIAL_CONSOLE) -# define STM32H5_CONSOLE_BASE STM32_UART9_BASE -# define STM32H5_APBCLOCK STM32_PCLK1_FREQUENCY -# define STM32H5_CONSOLE_APBREG STM32_RCC_APB1LENR -# define STM32H5_CONSOLE_APBEN RCC_APB1LENR_UART9EN -# define STM32H5_CONSOLE_BAUD CONFIG_UART9_BAUD -# define STM32H5_CONSOLE_BITS CONFIG_UART9_BITS -# define STM32H5_CONSOLE_PARITY CONFIG_UART9_PARITY -# define STM32H5_CONSOLE_2STOP CONFIG_UART9_2STOP -# define STM32H5_CONSOLE_TX GPIO_UART9_TX -# define STM32H5_CONSOLE_RX GPIO_UART9_RX +# define STM32_CONSOLE_BASE STM32_UART9_BASE +# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY +# define STM32_CONSOLE_APBREG STM32_RCC_APB1LENR +# define STM32_CONSOLE_APBEN RCC_APB1LENR_UART9EN +# define STM32_CONSOLE_BAUD CONFIG_UART9_BAUD +# define STM32_CONSOLE_BITS CONFIG_UART9_BITS +# define STM32_CONSOLE_PARITY CONFIG_UART9_PARITY +# define STM32_CONSOLE_2STOP CONFIG_UART9_2STOP +# define STM32_CONSOLE_TX GPIO_UART9_TX +# define STM32_CONSOLE_RX GPIO_UART9_RX # ifdef CONFIG_UART9_RS485 -# define STM32H5_CONSOLE_RS485_DIR GPIO_UART9_RS485_DIR +# define STM32_CONSOLE_RS485_DIR GPIO_UART9_RS485_DIR # if (CONFIG_UART9_RS485_DIR_POLARITY == 0) -# define STM32H5_CONSOLE_RS485_DIR_POLARITY false +# define STM32_CONSOLE_RS485_DIR_POLARITY false # else -# define STM32H5_CONSOLE_RS485_DIR_POLARITY true +# define STM32_CONSOLE_RS485_DIR_POLARITY true # endif # endif # elif defined(CONFIG_USART10_SERIAL_CONSOLE) -# define STM32H5_CONSOLE_BASE STM32_USART10_BASE -# define STM32H5_APBCLOCK STM32_PCLK1_FREQUENCY -# define STM32H5_CONSOLE_APBREG STM32_RCC_APB1LENR -# define STM32H5_CONSOLE_APBEN RCC_APB1LENR_USART10EN -# define STM32H5_CONSOLE_BAUD CONFIG_USART10_BAUD -# define STM32H5_CONSOLE_BITS CONFIG_USART10_BITS -# define STM32H5_CONSOLE_PARITY CONFIG_USART10_PARITY -# define STM32H5_CONSOLE_2STOP CONFIG_USART10_2STOP -# define STM32H5_CONSOLE_TX GPIO_USART10_TX -# define STM32H5_CONSOLE_RX GPIO_USART10_RX +# define STM32_CONSOLE_BASE STM32_USART10_BASE +# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY +# define STM32_CONSOLE_APBREG STM32_RCC_APB1LENR +# define STM32_CONSOLE_APBEN RCC_APB1LENR_USART10EN +# define STM32_CONSOLE_BAUD CONFIG_USART10_BAUD +# define STM32_CONSOLE_BITS CONFIG_USART10_BITS +# define STM32_CONSOLE_PARITY CONFIG_USART10_PARITY +# define STM32_CONSOLE_2STOP CONFIG_USART10_2STOP +# define STM32_CONSOLE_TX GPIO_USART10_TX +# define STM32_CONSOLE_RX GPIO_USART10_RX # ifdef CONFIG_USART10_RS485 -# define STM32H5_CONSOLE_RS485_DIR GPIO_USART10_RS485_DIR +# define STM32_CONSOLE_RS485_DIR GPIO_USART10_RS485_DIR # if (CONFIG_USART10_RS485_DIR_POLARITY == 0) -# define STM32H5_CONSOLE_RS485_DIR_POLARITY false +# define STM32_CONSOLE_RS485_DIR_POLARITY false # else -# define STM32H5_CONSOLE_RS485_DIR_POLARITY true +# define STM32_CONSOLE_RS485_DIR_POLARITY true # endif # endif # elif defined(CONFIG_USART11_SERIAL_CONSOLE) -# define STM32H5_CONSOLE_BASE STM32_USART11_BASE -# define STM32H5_APBCLOCK STM32_PCLK1_FREQUENCY -# define STM32H5_CONSOLE_APBREG STM32_RCC_APB1LENR -# define STM32H5_CONSOLE_APBEN RCC_APB1LENR_USART11EN -# define STM32H5_CONSOLE_BAUD CONFIG_USART11_BAUD -# define STM32H5_CONSOLE_BITS CONFIG_USART11_BITS -# define STM32H5_CONSOLE_PARITY CONFIG_USART11_PARITY -# define STM32H5_CONSOLE_2STOP CONFIG_USART11_2STOP -# define STM32H5_CONSOLE_TX GPIO_USART11_TX -# define STM32H5_CONSOLE_RX GPIO_USART11_RX +# define STM32_CONSOLE_BASE STM32_USART11_BASE +# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY +# define STM32_CONSOLE_APBREG STM32_RCC_APB1LENR +# define STM32_CONSOLE_APBEN RCC_APB1LENR_USART11EN +# define STM32_CONSOLE_BAUD CONFIG_USART11_BAUD +# define STM32_CONSOLE_BITS CONFIG_USART11_BITS +# define STM32_CONSOLE_PARITY CONFIG_USART11_PARITY +# define STM32_CONSOLE_2STOP CONFIG_USART11_2STOP +# define STM32_CONSOLE_TX GPIO_USART11_TX +# define STM32_CONSOLE_RX GPIO_USART11_RX # ifdef CONFIG_USART11_RS485 -# define STM32H5_CONSOLE_RS485_DIR GPIO_USART11_RS485_DIR +# define STM32_CONSOLE_RS485_DIR GPIO_USART11_RS485_DIR # if (CONFIG_USART11_RS485_DIR_POLARITY == 0) -# define STM32H5_CONSOLE_RS485_DIR_POLARITY false +# define STM32_CONSOLE_RS485_DIR_POLARITY false # else -# define STM32H5_CONSOLE_RS485_DIR_POLARITY true +# define STM32_CONSOLE_RS485_DIR_POLARITY true # endif # endif # elif defined(CONFIG_UART12_SERIAL_CONSOLE) -# define STM32H5_CONSOLE_BASE STM32_UART12_BASE -# define STM32H5_APBCLOCK STM32_PCLK1_FREQUENCY -# define STM32H5_CONSOLE_APBREG STM32_RCC_APB1LENR -# define STM32H5_CONSOLE_APBEN RCC_APB1LENR_UART12EN -# define STM32H5_CONSOLE_BAUD CONFIG_UART12_BAUD -# define STM32H5_CONSOLE_BITS CONFIG_UART12_BITS -# define STM32H5_CONSOLE_PARITY CONFIG_UART12_PARITY -# define STM32H5_CONSOLE_2STOP CONFIG_UART12_2STOP -# define STM32H5_CONSOLE_TX GPIO_UART12_TX -# define STM32H5_CONSOLE_RX GPIO_UART12_RX +# define STM32_CONSOLE_BASE STM32_UART12_BASE +# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY +# define STM32_CONSOLE_APBREG STM32_RCC_APB1LENR +# define STM32_CONSOLE_APBEN RCC_APB1LENR_UART12EN +# define STM32_CONSOLE_BAUD CONFIG_UART12_BAUD +# define STM32_CONSOLE_BITS CONFIG_UART12_BITS +# define STM32_CONSOLE_PARITY CONFIG_UART12_PARITY +# define STM32_CONSOLE_2STOP CONFIG_UART12_2STOP +# define STM32_CONSOLE_TX GPIO_UART12_TX +# define STM32_CONSOLE_RX GPIO_UART12_RX # ifdef CONFIG_UART12_RS485 -# define STM32H5_CONSOLE_RS485_DIR GPIO_UART12_RS485_DIR +# define STM32_CONSOLE_RS485_DIR GPIO_UART12_RS485_DIR # if (CONFIG_UART12_RS485_DIR_POLARITY == 0) -# define STM32H5_CONSOLE_RS485_DIR_POLARITY false +# define STM32_CONSOLE_RS485_DIR_POLARITY false # else -# define STM32H5_CONSOLE_RS485_DIR_POLARITY true +# define STM32_CONSOLE_RS485_DIR_POLARITY true # endif # endif # endif /* CR1 settings */ -# if STM32H5_CONSOLE_BITS == 9 +# if STM32_CONSOLE_BITS == 9 # define USART_CR1_M0_VALUE USART_CR1_M0 # define USART_CR1_M1_VALUE 0 -# elif STM32H5_CONSOLE_BITS == 7 +# elif STM32_CONSOLE_BITS == 7 # define USART_CR1_M0_VALUE 0 # define USART_CR1_M1_VALUE USART_CR1_M1 # else /* 8 bits */ @@ -307,15 +307,15 @@ # define USART_CR1_M1_VALUE 0 # endif -# if STM32H5_CONSOLE_PARITY == 1 /* odd parity */ +# if STM32_CONSOLE_PARITY == 1 /* odd parity */ # define USART_CR1_PARITY_VALUE (USART_CR1_PCE|USART_CR1_PS) -# elif STM32H5_CONSOLE_PARITY == 2 /* even parity */ +# elif STM32_CONSOLE_PARITY == 2 /* even parity */ # define USART_CR1_PARITY_VALUE USART_CR1_PCE # else /* no parity */ # define USART_CR1_PARITY_VALUE 0 # endif -# if STM32H5_CONSOLE_BASE == STM32_LPUART1_BASE +# if STM32_CONSOLE_BASE == STM32_LPUART1_BASE # define USART_CR1_CLRBITS \ (USART_CR1_UE | USART_CR1_UESM | USART_CR1_RE | USART_CR1_TE | USART_CR1_PS | \ USART_CR1_PCE | USART_CR1_WAKE | USART_CR1_M0 | USART_CR1_M1 | \ @@ -333,7 +333,7 @@ /* CR2 settings */ -# if STM32H5_CONSOLE_2STOP != 0 +# if STM32_CONSOLE_2STOP != 0 # define USART_CR2_STOP2_VALUE USART_CR2_STOP2 # else # define USART_CR2_STOP2_VALUE 0 @@ -362,7 +362,7 @@ # undef USE_OVER8 /* Calculate USART BAUD rate divider */ -# if STM32H5_CONSOLE_BASE == STM32_LPUART1_BASE +# if STM32_CONSOLE_BASE == STM32_LPUART1_BASE /* BRR = (256 * (APBCLOCK / Prescaler)) / (Baud rate) * With Prescaler == 16, BRR = (16 * APBCLOCK / (Baud rate) @@ -388,19 +388,19 @@ * UARTDIV = 2 * fCK / baud */ -# define STM32H5_USARTDIV8 \ - (((STM32H5_APBCLOCK << 1) + (STM32H5_CONSOLE_BAUD >> 1)) / STM32H5_CONSOLE_BAUD) -# define STM32H5_USARTDIV16 \ - ((STM32H5_APBCLOCK + (STM32H5_CONSOLE_BAUD >> 1)) / STM32H5_CONSOLE_BAUD) +# define STM32_USARTDIV8 \ + (((STM32_APBCLOCK << 1) + (STM32_CONSOLE_BAUD >> 1)) / STM32_CONSOLE_BAUD) +# define STM32_USARTDIV16 \ + ((STM32_APBCLOCK + (STM32_CONSOLE_BAUD >> 1)) / STM32_CONSOLE_BAUD) /* Use oversamply by 8 only if the divisor is small. But what is small? */ -# if STM32H5_USARTDIV8 > 2000 -# define STM32H5_BRR_VALUE STM32H5_USARTDIV16 +# if STM32_USARTDIV8 > 2000 +# define STM32_BRR_VALUE STM32_USARTDIV16 # else # define USE_OVER8 1 -# define STM32H5_BRR_VALUE \ - ((STM32H5_USARTDIV8 & 0xfff0) | ((STM32H5_USARTDIV8 & 0x000f) >> 1)) +# define STM32_BRR_VALUE \ + ((STM32_USARTDIV8 & 0xfff0) | ((STM32_USARTDIV8 & 0x000f) >> 1)) # endif # endif #endif /* HAVE_CONSOLE */ @@ -442,22 +442,22 @@ void arm_lowputc(char ch) #ifdef HAVE_CONSOLE /* Wait until the TX data register is empty */ - while ((getreg32(STM32H5_CONSOLE_BASE + STM32_USART_ISR_OFFSET) & + while ((getreg32(STM32_CONSOLE_BASE + STM32_USART_ISR_OFFSET) & USART_ISR_TXE) == 0); -#ifdef STM32H5_CONSOLE_RS485_DIR - stm32_gpiowrite(STM32H5_CONSOLE_RS485_DIR, - STM32H5_CONSOLE_RS485_DIR_POLARITY); +#ifdef STM32_CONSOLE_RS485_DIR + stm32_gpiowrite(STM32_CONSOLE_RS485_DIR, + STM32_CONSOLE_RS485_DIR_POLARITY); #endif /* Then send the character */ - putreg32((uint32_t)ch, STM32H5_CONSOLE_BASE + STM32_USART_TDR_OFFSET); + putreg32((uint32_t)ch, STM32_CONSOLE_BASE + STM32_USART_TDR_OFFSET); -#ifdef STM32H5_CONSOLE_RS485_DIR - while ((getreg32(STM32H5_CONSOLE_BASE + STM32_USART_ISR_OFFSET) & +#ifdef STM32_CONSOLE_RS485_DIR + while ((getreg32(STM32_CONSOLE_BASE + STM32_USART_ISR_OFFSET) & USART_ISR_TC) == 0); - stm32_gpiowrite(STM32H5_CONSOLE_RS485_DIR, - !STM32H5_CONSOLE_RS485_DIR_POLARITY); + stm32_gpiowrite(STM32_CONSOLE_RS485_DIR, + !STM32_CONSOLE_RS485_DIR_POLARITY); #endif #endif /* HAVE_CONSOLE */ @@ -483,7 +483,7 @@ void stm32_lowsetup(void) #if defined(HAVE_CONSOLE) /* Enable USART APB clock */ - modifyreg32(STM32H5_CONSOLE_APBREG, 0, STM32H5_CONSOLE_APBEN); + modifyreg32(STM32_CONSOLE_APBREG, 0, STM32_CONSOLE_APBEN); #endif /* Enable the console USART and configure GPIO pins needed for rx/tx. @@ -492,17 +492,17 @@ void stm32_lowsetup(void) * stm32_rcc.c */ -#ifdef STM32H5_CONSOLE_TX - stm32_configgpio(STM32H5_CONSOLE_TX); +#ifdef STM32_CONSOLE_TX + stm32_configgpio(STM32_CONSOLE_TX); #endif -#ifdef STM32H5_CONSOLE_RX - stm32_configgpio(STM32H5_CONSOLE_RX); +#ifdef STM32_CONSOLE_RX + stm32_configgpio(STM32_CONSOLE_RX); #endif -#ifdef STM32H5_CONSOLE_RS485_DIR - stm32_configgpio(STM32H5_CONSOLE_RS485_DIR); - stm32_gpiowrite(STM32H5_CONSOLE_RS485_DIR, - !STM32H5_CONSOLE_RS485_DIR_POLARITY); +#ifdef STM32_CONSOLE_RS485_DIR + stm32_configgpio(STM32_CONSOLE_RS485_DIR); + stm32_gpiowrite(STM32_CONSOLE_RS485_DIR, + !STM32_CONSOLE_RS485_DIR_POLARITY); #endif /* Enable and configure the selected console device */ @@ -510,42 +510,42 @@ void stm32_lowsetup(void) #if defined(HAVE_CONSOLE) && !defined(CONFIG_SUPPRESS_UART_CONFIG) /* Configure CR2 */ - cr = getreg32(STM32H5_CONSOLE_BASE + STM32_USART_CR2_OFFSET); + cr = getreg32(STM32_CONSOLE_BASE + STM32_USART_CR2_OFFSET); cr &= ~USART_CR2_CLRBITS; cr |= USART_CR2_SETBITS; - putreg32(cr, STM32H5_CONSOLE_BASE + STM32_USART_CR2_OFFSET); + putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR2_OFFSET); /* Configure CR1 */ - cr = getreg32(STM32H5_CONSOLE_BASE + STM32_USART_CR1_OFFSET); + cr = getreg32(STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET); cr &= ~USART_CR1_CLRBITS; cr |= USART_CR1_SETBITS; - putreg32(cr, STM32H5_CONSOLE_BASE + STM32_USART_CR1_OFFSET); + putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET); /* Configure CR3 */ - cr = getreg32(STM32H5_CONSOLE_BASE + STM32_USART_CR3_OFFSET); + cr = getreg32(STM32_CONSOLE_BASE + STM32_USART_CR3_OFFSET); cr &= ~USART_CR3_CLRBITS; cr |= USART_CR3_SETBITS; - putreg32(cr, STM32H5_CONSOLE_BASE + STM32_USART_CR3_OFFSET); + putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR3_OFFSET); /* Configure the USART Baud Rate */ - putreg32(STM32H5_BRR_VALUE, - STM32H5_CONSOLE_BASE + STM32_USART_BRR_OFFSET); + putreg32(STM32_BRR_VALUE, + STM32_CONSOLE_BASE + STM32_USART_BRR_OFFSET); /* Select oversampling by 8 */ - cr = getreg32(STM32H5_CONSOLE_BASE + STM32_USART_CR1_OFFSET); + cr = getreg32(STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET); #ifdef USE_OVER8 cr |= USART_CR1_OVER8; - putreg32(cr, STM32H5_CONSOLE_BASE + STM32_USART_CR1_OFFSET); + putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET); #endif /* Enable Rx, Tx, and the USART */ cr |= (USART_CR1_UE | USART_CR1_TE | USART_CR1_RE); - putreg32(cr, STM32H5_CONSOLE_BASE + STM32_USART_CR1_OFFSET); + putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET); #endif /* HAVE_CONSOLE && !CONFIG_SUPPRESS_UART_CONFIG */ #endif /* HAVE_UART */ diff --git a/arch/arm/src/stm32h5/stm32_lse.c b/arch/arm/src/stm32h5/stm32_lse.c index d5c0db5e0f12e..7bc65aa3a06a9 100644 --- a/arch/arm/src/stm32h5/stm32_lse.c +++ b/arch/arm/src/stm32h5/stm32_lse.c @@ -41,9 +41,9 @@ static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1, #define LSERDY_TIMEOUT (500 * CONFIG_BOARD_LOOPSPERMSEC) -#ifdef CONFIG_STM32H5_RTC_LSECLOCK_START_DRV_CAPABILITY -# if CONFIG_STM32H5_RTC_LSECLOCK_START_DRV_CAPABILITY < 0 || \ - CONFIG_STM32H5_RTC_LSECLOCK_START_DRV_CAPABILITY > 3 +#ifdef CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY +# if CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY < 0 || \ + CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY > 3 # error "Invalid LSE drive capability setting" # endif #endif @@ -52,7 +52,7 @@ static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1, * Private Data ****************************************************************************/ -#ifdef CONFIG_STM32H5_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY +#ifdef CONFIG_STM32_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY static const uint32_t drives[4] = { RCC_BDCR_LSEDRV_LOW, @@ -79,7 +79,7 @@ void stm32_rcc_enablelse(void) bool writable; uint32_t regval; volatile int32_t timeout; -#ifdef CONFIG_STM32H5_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY +#ifdef CONFIG_STM32_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY volatile int32_t drive = 0; #endif @@ -105,19 +105,19 @@ void stm32_rcc_enablelse(void) regval |= RCC_BDCR_LSEON; -#ifdef CONFIG_STM32H5_RTC_LSECLOCK_START_DRV_CAPABILITY +#ifdef CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY /* Set start-up drive capability for LSE oscillator. LSE must be OFF * to change drive strength. */ regval &= ~(RCC_BDCR_LSEDRV_MASK | RCC_BDCR_LSEON); - regval |= CONFIG_STM32H5_RTC_LSECLOCK_START_DRV_CAPABILITY << + regval |= CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY << RCC_BDCR_LSEDRV_SHIFT; putreg32(regval, STM32_RCC_BDCR); regval |= RCC_BDCR_LSEON; #endif -#ifdef CONFIG_STM32H5_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY +#ifdef CONFIG_STM32_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY do { regval &= ~(RCC_BDCR_LSEDRV_MASK | RCC_BDCR_LSEON); @@ -145,7 +145,7 @@ void stm32_rcc_enablelse(void) } } -#ifdef CONFIG_STM32H5_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY +#ifdef CONFIG_STM32_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY if (timeout != 0) { break; @@ -154,7 +154,7 @@ void stm32_rcc_enablelse(void) while (drive < sizeof(drives) / sizeof(drives[0])); #endif -#ifdef CONFIG_STM32H5_RTC_LSECLOCK_LOWER_RUN_DRV_CAPABILITY +#ifdef CONFIG_STM32_RTC_LSECLOCK_LOWER_RUN_DRV_CAPABILITY /* Set running drive capability for LSE oscillator. */ diff --git a/arch/arm/src/stm32h5/stm32_pulsecount.c b/arch/arm/src/stm32h5/stm32_pulsecount.c index 7bae9cc8cb7f2..d002444cd7a5a 100644 --- a/arch/arm/src/stm32h5/stm32_pulsecount.c +++ b/arch/arm/src/stm32h5/stm32_pulsecount.c @@ -182,10 +182,10 @@ static int pulsecount_configure(struct pulsecount_lowerhalf_s *dev); static int pulsecount_timer(struct pulsecount_lowerhalf_s *dev, const struct pulsecount_info_s *info); static int pulsecount_interrupt(struct pulsecount_lowerhalf_s *dev); -# ifdef CONFIG_STM32H5_TIM1_PULSECOUNT +# ifdef CONFIG_STM32_TIM1_PULSECOUNT static int pulsecount_tim1interrupt(int irq, void *context, void *arg); # endif -# ifdef CONFIG_STM32H5_TIM8_PULSECOUNT +# ifdef CONFIG_STM32_TIM8_PULSECOUNT static int pulsecount_tim8interrupt(int irq, void *context, void *arg); # endif static uint8_t pulsecount_count(uint32_t count); @@ -212,107 +212,107 @@ static int pulsecount_ioctl(struct pulsecount_lowerhalf_s *dev, * Private Data ****************************************************************************/ -#ifdef CONFIG_STM32H5_TIM1_PULSECOUNT +#ifdef CONFIG_STM32_TIM1_PULSECOUNT static struct stm32_tim_s g_pulsecount1dev = { .channel = { - .channel = CONFIG_STM32H5_TIM1_PULSECOUNT_CHANNEL, -#if CONFIG_STM32H5_TIM1_PULSECOUNT_CHANNEL == 1 + .channel = CONFIG_STM32_TIM1_PULSECOUNT_CHANNEL, +#if CONFIG_STM32_TIM1_PULSECOUNT_CHANNEL == 1 .out1 = { .in_use = 1, - .pol = CONFIG_STM32H5_TIM1_PULSECOUNT_POL, - .idle = CONFIG_STM32H5_TIM1_PULSECOUNT_IDLE, + .pol = CONFIG_STM32_TIM1_PULSECOUNT_POL, + .idle = CONFIG_STM32_TIM1_PULSECOUNT_IDLE, .pincfg = GPIO_TIM1_CH1OUT, }, -#elif CONFIG_STM32H5_TIM1_PULSECOUNT_CHANNEL == 2 +#elif CONFIG_STM32_TIM1_PULSECOUNT_CHANNEL == 2 .out1 = { .in_use = 1, - .pol = CONFIG_STM32H5_TIM1_PULSECOUNT_POL, - .idle = CONFIG_STM32H5_TIM1_PULSECOUNT_IDLE, + .pol = CONFIG_STM32_TIM1_PULSECOUNT_POL, + .idle = CONFIG_STM32_TIM1_PULSECOUNT_IDLE, .pincfg = GPIO_TIM1_CH2OUT, }, -#elif CONFIG_STM32H5_TIM1_PULSECOUNT_CHANNEL == 3 +#elif CONFIG_STM32_TIM1_PULSECOUNT_CHANNEL == 3 .out1 = { .in_use = 1, - .pol = CONFIG_STM32H5_TIM1_PULSECOUNT_POL, - .idle = CONFIG_STM32H5_TIM1_PULSECOUNT_IDLE, + .pol = CONFIG_STM32_TIM1_PULSECOUNT_POL, + .idle = CONFIG_STM32_TIM1_PULSECOUNT_IDLE, .pincfg = GPIO_TIM1_CH3OUT, }, -#elif CONFIG_STM32H5_TIM1_PULSECOUNT_CHANNEL == 4 +#elif CONFIG_STM32_TIM1_PULSECOUNT_CHANNEL == 4 .out1 = { .in_use = 1, - .pol = CONFIG_STM32H5_TIM1_PULSECOUNT_POL, - .idle = CONFIG_STM32H5_TIM1_PULSECOUNT_IDLE, + .pol = CONFIG_STM32_TIM1_PULSECOUNT_POL, + .idle = CONFIG_STM32_TIM1_PULSECOUNT_IDLE, .pincfg = GPIO_TIM1_CH4OUT, }, #endif }, .timid = 1, .timtype = TIMTYPE_TIM1, - .t_dts = CONFIG_STM32H5_TIM1_PULSECOUNT_TDTS, + .t_dts = CONFIG_STM32_TIM1_PULSECOUNT_TDTS, .irq = STM32_IRQ_TIM1_UP, .base = STM32_TIM1_BASE, .pclk = TIMCLK_TIM1, }; -#endif /* CONFIG_STM32H5_TIM1_PULSECOUNT */ +#endif /* CONFIG_STM32_TIM1_PULSECOUNT */ -#ifdef CONFIG_STM32H5_TIM8_PULSECOUNT +#ifdef CONFIG_STM32_TIM8_PULSECOUNT static struct stm32_tim_s g_pulsecount8dev = { .channel = { - .channel = CONFIG_STM32H5_TIM8_PULSECOUNT_CHANNEL, -#if CONFIG_STM32H5_TIM8_PULSECOUNT_CHANNEL == 1 + .channel = CONFIG_STM32_TIM8_PULSECOUNT_CHANNEL, +#if CONFIG_STM32_TIM8_PULSECOUNT_CHANNEL == 1 .out1 = { .in_use = 1, - .pol = CONFIG_STM32H5_TIM8_PULSECOUNT_POL, - .idle = CONFIG_STM32H5_TIM8_PULSECOUNT_IDLE, + .pol = CONFIG_STM32_TIM8_PULSECOUNT_POL, + .idle = CONFIG_STM32_TIM8_PULSECOUNT_IDLE, .pincfg = GPIO_TIM8_CH1OUT, }, -#elif CONFIG_STM32H5_TIM8_PULSECOUNT_CHANNEL == 2 +#elif CONFIG_STM32_TIM8_PULSECOUNT_CHANNEL == 2 .out1 = { .in_use = 1, - .pol = CONFIG_STM32H5_TIM8_PULSECOUNT_POL, - .idle = CONFIG_STM32H5_TIM8_PULSECOUNT_IDLE, + .pol = CONFIG_STM32_TIM8_PULSECOUNT_POL, + .idle = CONFIG_STM32_TIM8_PULSECOUNT_IDLE, .pincfg = GPIO_TIM8_CH2OUT, }, -#elif CONFIG_STM32H5_TIM8_PULSECOUNT_CHANNEL == 3 +#elif CONFIG_STM32_TIM8_PULSECOUNT_CHANNEL == 3 .out1 = { .in_use = 1, - .pol = CONFIG_STM32H5_TIM8_PULSECOUNT_POL, - .idle = CONFIG_STM32H5_TIM8_PULSECOUNT_IDLE, + .pol = CONFIG_STM32_TIM8_PULSECOUNT_POL, + .idle = CONFIG_STM32_TIM8_PULSECOUNT_IDLE, .pincfg = GPIO_TIM8_CH3OUT, }, -#elif CONFIG_STM32H5_TIM8_PULSECOUNT_CHANNEL == 4 +#elif CONFIG_STM32_TIM8_PULSECOUNT_CHANNEL == 4 .out1 = { .in_use = 1, - .pol = CONFIG_STM32H5_TIM8_PULSECOUNT_POL, - .idle = CONFIG_STM32H5_TIM8_PULSECOUNT_IDLE, + .pol = CONFIG_STM32_TIM8_PULSECOUNT_POL, + .idle = CONFIG_STM32_TIM8_PULSECOUNT_IDLE, .pincfg = GPIO_TIM8_CH4OUT, }, #endif }, .timid = 8, .timtype = TIMTYPE_TIM8, - .t_dts = CONFIG_STM32H5_TIM8_PULSECOUNT_TDTS, + .t_dts = CONFIG_STM32_TIM8_PULSECOUNT_TDTS, .irq = STM32_IRQ_TIM8_UP, .base = STM32_TIM8_BASE, .pclk = TIMCLK_TIM8, }; -#endif /* CONFIG_STM32H5_TIM8_PULSECOUNT */ +#endif /* CONFIG_STM32_TIM8_PULSECOUNT */ static const struct pulsecount_ops_s g_pulsecountops = { @@ -323,7 +323,7 @@ static const struct pulsecount_ops_s g_pulsecountops = .ioctl = pulsecount_ioctl, }; -#ifdef CONFIG_STM32H5_TIM1_PULSECOUNT +#ifdef CONFIG_STM32_TIM1_PULSECOUNT static struct stm32_pulsecount_s g_pulsecount1lower = { .ops = &g_pulsecountops, @@ -331,7 +331,7 @@ static struct stm32_pulsecount_s g_pulsecount1lower = }; #endif -#ifdef CONFIG_STM32H5_TIM8_PULSECOUNT +#ifdef CONFIG_STM32_TIM8_PULSECOUNT static struct stm32_pulsecount_s g_pulsecount8lower = { .ops = &g_pulsecountops, @@ -1321,21 +1321,21 @@ static int pulsecount_interrupt(struct pulsecount_lowerhalf_s *dev) * ****************************************************************************/ -#ifdef CONFIG_STM32H5_TIM1_PULSECOUNT +#ifdef CONFIG_STM32_TIM1_PULSECOUNT static int pulsecount_tim1interrupt(int irq, void *context, void *arg) { return pulsecount_interrupt((struct pulsecount_lowerhalf_s *) &g_pulsecount1dev); } -#endif /* CONFIG_STM32H5_TIM1_PULSECOUNT */ +#endif /* CONFIG_STM32_TIM1_PULSECOUNT */ -#ifdef CONFIG_STM32H5_TIM8_PULSECOUNT +#ifdef CONFIG_STM32_TIM8_PULSECOUNT static int pulsecount_tim8interrupt(int irq, void *context, void *arg) { return pulsecount_interrupt((struct pulsecount_lowerhalf_s *) &g_pulsecount8dev); } -#endif /* CONFIG_STM32H5_TIM8_PULSECOUNT */ +#endif /* CONFIG_STM32_TIM8_PULSECOUNT */ /**************************************************************************** * Name: pulsecount_count @@ -1408,7 +1408,7 @@ static int pulsecount_set_apb_clock(struct stm32_tim_s *priv, bool on) switch (priv->timid) { -#ifdef CONFIG_STM32H5_TIM1_PULSECOUNT +#ifdef CONFIG_STM32_TIM1_PULSECOUNT case 1: { regaddr = TIMRCCEN_TIM1; @@ -1417,7 +1417,7 @@ static int pulsecount_set_apb_clock(struct stm32_tim_s *priv, bool on) } #endif -#ifdef CONFIG_STM32H5_TIM8_PULSECOUNT +#ifdef CONFIG_STM32_TIM8_PULSECOUNT case 8: { regaddr = TIMRCCEN_TIM8; @@ -1600,7 +1600,7 @@ static int pulsecount_ll_stop(struct pulsecount_lowerhalf_s *dev) switch (priv->timid) { -#ifdef CONFIG_STM32H5_TIM1_PULSECOUNT +#ifdef CONFIG_STM32_TIM1_PULSECOUNT case 1: { regaddr = TIMRCCRST_TIM1; @@ -1609,7 +1609,7 @@ static int pulsecount_ll_stop(struct pulsecount_lowerhalf_s *dev) } #endif -#ifdef CONFIG_STM32H5_TIM8_PULSECOUNT +#ifdef CONFIG_STM32_TIM8_PULSECOUNT case 8: { regaddr = TIMRCCRST_TIM8; @@ -1761,7 +1761,7 @@ struct pulsecount_lowerhalf_s *stm32_pulsecountinitialize(int timer) switch (timer) { -#ifdef CONFIG_STM32H5_TIM1_PULSECOUNT +#ifdef CONFIG_STM32_TIM1_PULSECOUNT case 1: { lower = &g_pulsecount1lower; @@ -1771,7 +1771,7 @@ struct pulsecount_lowerhalf_s *stm32_pulsecountinitialize(int timer) } #endif -#ifdef CONFIG_STM32H5_TIM8_PULSECOUNT +#ifdef CONFIG_STM32_TIM8_PULSECOUNT case 8: { lower = &g_pulsecount8lower; diff --git a/arch/arm/src/stm32h5/stm32_pwm.c b/arch/arm/src/stm32h5/stm32_pwm.c index eadb42917b1a6..1caf1ddc04bb3 100644 --- a/arch/arm/src/stm32h5/stm32_pwm.c +++ b/arch/arm/src/stm32h5/stm32_pwm.c @@ -159,9 +159,9 @@ * supported capture/compare. */ -#if defined(CONFIG_STM32H5_TIM1_PWM) || defined(CONFIG_STM32H5_TIM8_PWM) || \ - defined(CONFIG_STM32H5_TIM15_PWM) || defined(CONFIG_STM32_TIM16_PWM) || \ - defined(CONFIG_STM32H5_TIM17_PWM) +#if defined(CONFIG_STM32_TIM1_PWM) || defined(CONFIG_STM32_TIM8_PWM) || \ + defined(CONFIG_STM32_TIM15_PWM) || defined(CONFIG_STM32_TIM16_PWM) || \ + defined(CONFIG_STM32_TIM17_PWM) # define HAVE_ADVTIM #else # undef HAVE_ADVTIM @@ -169,16 +169,16 @@ /* Synchronisation support */ -#ifdef CONFIG_STM32H5_PWM_TRGO +#ifdef CONFIG_STM32_PWM_TRGO # define HAVE_TRGO #endif /* Break support */ -#if defined(CONFIG_STM32H5_TIM1_BREAK1) || defined(CONFIG_STM32H5_TIM1_BREAK2) || \ - defined(CONFIG_STM32H5_TIM8_BREAK1) || defined(CONFIG_STM32H5_TIM8_BREAK2) || \ - defined(CONFIG_STM32H5_TIM15_BREAK1) || defined(CONFIG_STM32H5_TIM16_BREAK1) || \ - defined(CONFIG_STM32H5_TIM17_BREAK1) +#if defined(CONFIG_STM32_TIM1_BREAK1) || defined(CONFIG_STM32_TIM1_BREAK2) || \ + defined(CONFIG_STM32_TIM8_BREAK1) || defined(CONFIG_STM32_TIM8_BREAK2) || \ + defined(CONFIG_STM32_TIM15_BREAK1) || defined(CONFIG_STM32_TIM16_BREAK1) || \ + defined(CONFIG_STM32_TIM17_BREAK1) # defined HAVE_BREAK #endif @@ -241,7 +241,7 @@ struct stm32_pwmchan_s struct stm32_pwmtimer_s { const struct pwm_ops_s *ops; /* PWM operations */ -#ifdef CONFIG_STM32H5_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS const struct stm32_pwm_ops_s *llops; /* Low-level PWM ops */ #endif struct stm32_pwmchan_s *channels; /* Channels configuration */ @@ -314,10 +314,10 @@ static int pwm_break_dt_configure(struct stm32_pwmtimer_s *priv); static int pwm_sync_configure(struct stm32_pwmtimer_s *priv, uint8_t trgo); #endif -#if defined(HAVE_PWM_COMPLEMENTARY) && defined(CONFIG_STM32H5_PWM_LL_OPS) +#if defined(HAVE_PWM_COMPLEMENTARY) && defined(CONFIG_STM32_PWM_LL_OPS) static int pwm_deadtime_update(struct pwm_lowerhalf_s *dev, uint8_t dt); #endif -#ifdef CONFIG_STM32H5_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS static uint32_t pwm_ccr_get(struct pwm_lowerhalf_s *dev, uint8_t index); #endif @@ -354,7 +354,7 @@ static const struct pwm_ops_s g_pwmops = .ioctl = pwm_ioctl, }; -#ifdef CONFIG_STM32H5_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS static const struct stm32_pwm_ops_s g_llpwmops = { .configure = pwm_configure, @@ -377,138 +377,138 @@ static const struct stm32_pwm_ops_s g_llpwmops = }; #endif -#ifdef CONFIG_STM32H5_TIM1_PWM +#ifdef CONFIG_STM32_TIM1_PWM static struct stm32_pwmchan_s g_pwm1channels[] = { /* TIM1 has 4 channels, 4 complementary */ -#ifdef CONFIG_STM32H5_TIM1_CHANNEL1 +#ifdef CONFIG_STM32_TIM1_CHANNEL1 { .channel = 1, - .mode = CONFIG_STM32H5_TIM1_CH1MODE, + .mode = CONFIG_STM32_TIM1_CH1MODE, #ifdef HAVE_BREAK .brk = { -#ifdef CONFIG_STM32H5_TIM1_BREAK1 +#ifdef CONFIG_STM32_TIM1_BREAK1 .en1 = 1, - .pol1 = CONFIG_STM32H5_TIM1_BRK1POL, + .pol1 = CONFIG_STM32_TIM1_BRK1POL, #endif -#ifdef CONFIG_STM32H5_TIM1_BREAK2 +#ifdef CONFIG_STM32_TIM1_BREAK2 .en2 = 1, - .pol2 = CONFIG_STM32H5_TIM1_BRK2POL, - .flt2 = CONFIG_STM32H5_TIM1_BRK2FLT, + .pol2 = CONFIG_STM32_TIM1_BRK2POL, + .flt2 = CONFIG_STM32_TIM1_BRK2FLT, #endif }, #endif -#ifdef CONFIG_STM32H5_TIM1_CH1OUT +#ifdef CONFIG_STM32_TIM1_CH1OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H5_TIM1_CH1POL, - .idle = CONFIG_STM32H5_TIM1_CH1IDLE, + .pol = CONFIG_STM32_TIM1_CH1POL, + .idle = CONFIG_STM32_TIM1_CH1IDLE, .pincfg = PWM_TIM1_CH1CFG, }, #endif -#ifdef CONFIG_STM32H5_TIM1_CH1NOUT +#ifdef CONFIG_STM32_TIM1_CH1NOUT .out2 = { .in_use = 1, - .pol = CONFIG_STM32H5_TIM1_CH1NPOL, - .idle = CONFIG_STM32H5_TIM1_CH1NIDLE, + .pol = CONFIG_STM32_TIM1_CH1NPOL, + .idle = CONFIG_STM32_TIM1_CH1NIDLE, .pincfg = PWM_TIM1_CH1NCFG, } #endif }, #endif -#ifdef CONFIG_STM32H5_TIM1_CHANNEL2 +#ifdef CONFIG_STM32_TIM1_CHANNEL2 { .channel = 2, - .mode = CONFIG_STM32H5_TIM1_CH2MODE, -#ifdef CONFIG_STM32H5_TIM1_CH2OUT + .mode = CONFIG_STM32_TIM1_CH2MODE, +#ifdef CONFIG_STM32_TIM1_CH2OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H5_TIM1_CH2POL, - .idle = CONFIG_STM32H5_TIM1_CH2IDLE, + .pol = CONFIG_STM32_TIM1_CH2POL, + .idle = CONFIG_STM32_TIM1_CH2IDLE, .pincfg = PWM_TIM1_CH2CFG, }, #endif -#ifdef CONFIG_STM32H5_TIM1_CH2NOUT +#ifdef CONFIG_STM32_TIM1_CH2NOUT .out2 = { .in_use = 1, - .pol = CONFIG_STM32H5_TIM1_CH2NPOL, - .idle = CONFIG_STM32H5_TIM1_CH2NIDLE, + .pol = CONFIG_STM32_TIM1_CH2NPOL, + .idle = CONFIG_STM32_TIM1_CH2NIDLE, .pincfg = PWM_TIM1_CH2NCFG, } #endif }, #endif -#ifdef CONFIG_STM32H5_TIM1_CHANNEL3 +#ifdef CONFIG_STM32_TIM1_CHANNEL3 { .channel = 3, - .mode = CONFIG_STM32H5_TIM1_CH3MODE, -#ifdef CONFIG_STM32H5_TIM1_CH3OUT + .mode = CONFIG_STM32_TIM1_CH3MODE, +#ifdef CONFIG_STM32_TIM1_CH3OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H5_TIM1_CH3POL, - .idle = CONFIG_STM32H5_TIM1_CH3IDLE, + .pol = CONFIG_STM32_TIM1_CH3POL, + .idle = CONFIG_STM32_TIM1_CH3IDLE, .pincfg = PWM_TIM1_CH3CFG, }, #endif -#ifdef CONFIG_STM32H5_TIM1_CH3NOUT +#ifdef CONFIG_STM32_TIM1_CH3NOUT .out2 = { .in_use = 1, - .pol = CONFIG_STM32H5_TIM1_CH3NPOL, - .idle = CONFIG_STM32H5_TIM1_CH3NIDLE, + .pol = CONFIG_STM32_TIM1_CH3NPOL, + .idle = CONFIG_STM32_TIM1_CH3NIDLE, .pincfg = PWM_TIM1_CH3NCFG, } #endif }, #endif -#ifdef CONFIG_STM32H5_TIM1_CHANNEL4 +#ifdef CONFIG_STM32_TIM1_CHANNEL4 { .channel = 4, - .mode = CONFIG_STM32H5_TIM1_CH4MODE, -#ifdef CONFIG_STM32H5_TIM1_CH4OUT + .mode = CONFIG_STM32_TIM1_CH4MODE, +#ifdef CONFIG_STM32_TIM1_CH4OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H5_TIM1_CH4POL, - .idle = CONFIG_STM32H5_TIM1_CH4IDLE, + .pol = CONFIG_STM32_TIM1_CH4POL, + .idle = CONFIG_STM32_TIM1_CH4IDLE, .pincfg = PWM_TIM1_CH4CFG, } #endif }, #endif -#ifdef CONFIG_STM32H5_TIM1_CHANNEL5 +#ifdef CONFIG_STM32_TIM1_CHANNEL5 { .channel = 5, - .mode = CONFIG_STM32H5_TIM1_CH5MODE, -#ifdef CONFIG_STM32H5_TIM1_CH5OUT + .mode = CONFIG_STM32_TIM1_CH5MODE, +#ifdef CONFIG_STM32_TIM1_CH5OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H5_TIM1_CH5POL, - .idle = CONFIG_STM32H5_TIM1_CH5IDLE, + .pol = CONFIG_STM32_TIM1_CH5POL, + .idle = CONFIG_STM32_TIM1_CH5IDLE, .pincfg = 0, /* Not available externally */ } #endif }, #endif -#ifdef CONFIG_STM32H5_TIM1_CHANNEL6 +#ifdef CONFIG_STM32_TIM1_CHANNEL6 { .channel = 6, - .mode = CONFIG_STM32H5_TIM1_CH6MODE, -#ifdef CONFIG_STM32H5_TIM1_CH6OUT + .mode = CONFIG_STM32_TIM1_CH6MODE, +#ifdef CONFIG_STM32_TIM1_CH6OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H5_TIM1_CH6POL, - .idle = CONFIG_STM32H5_TIM1_CH6IDLE, + .pol = CONFIG_STM32_TIM1_CH6POL, + .idle = CONFIG_STM32_TIM1_CH6IDLE, .pincfg = 0, /* Not available externally */ } #endif @@ -519,18 +519,18 @@ static struct stm32_pwmchan_s g_pwm1channels[] = static struct stm32_pwmtimer_s g_pwm1dev = { .ops = &g_pwmops, -#ifdef CONFIG_STM32H5_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS .llops = &g_llpwmops, #endif .timid = 1, .chan_num = PWM_TIM1_NCHANNELS, .channels = g_pwm1channels, .timtype = TIMTYPE_TIM1, - .mode = CONFIG_STM32H5_TIM1_MODE, - .lock = CONFIG_STM32H5_TIM1_LOCK, - .t_dts = CONFIG_STM32H5_TIM1_TDTS, + .mode = CONFIG_STM32_TIM1_MODE, + .lock = CONFIG_STM32_TIM1_LOCK, + .t_dts = CONFIG_STM32_TIM1_TDTS, #ifdef HAVE_PWM_COMPLEMENTARY - .deadtime = CONFIG_STM32H5_TIM1_DEADTIME, + .deadtime = CONFIG_STM32_TIM1_DEADTIME, #endif #if defined(HAVE_TRGO) && defined(STM32_TIM1_TRGO) .trgo = STM32_TIM1_TRGO, @@ -538,72 +538,72 @@ static struct stm32_pwmtimer_s g_pwm1dev = .base = STM32_TIM1_BASE, .pclk = TIMCLK_TIM1, }; -#endif /* CONFIG_STM32H5_TIM1_PWM */ +#endif /* CONFIG_STM32_TIM1_PWM */ -#ifdef CONFIG_STM32H5_TIM2_PWM +#ifdef CONFIG_STM32_TIM2_PWM static struct stm32_pwmchan_s g_pwm2channels[] = { /* TIM2 has 4 channels */ -#ifdef CONFIG_STM32H5_TIM2_CHANNEL1 +#ifdef CONFIG_STM32_TIM2_CHANNEL1 { .channel = 1, - .mode = CONFIG_STM32H5_TIM2_CH1MODE, -#ifdef CONFIG_STM32H5_TIM2_CH1OUT + .mode = CONFIG_STM32_TIM2_CH1MODE, +#ifdef CONFIG_STM32_TIM2_CH1OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H5_TIM2_CH1POL, - .idle = CONFIG_STM32H5_TIM2_CH1IDLE, + .pol = CONFIG_STM32_TIM2_CH1POL, + .idle = CONFIG_STM32_TIM2_CH1IDLE, .pincfg = PWM_TIM2_CH1CFG, } #endif /* No complementary outputs */ }, #endif -#ifdef CONFIG_STM32H5_TIM2_CHANNEL2 +#ifdef CONFIG_STM32_TIM2_CHANNEL2 { .channel = 2, - .mode = CONFIG_STM32H5_TIM2_CH2MODE, -#ifdef CONFIG_STM32H5_TIM2_CH2OUT + .mode = CONFIG_STM32_TIM2_CH2MODE, +#ifdef CONFIG_STM32_TIM2_CH2OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H5_TIM2_CH2POL, - .idle = CONFIG_STM32H5_TIM2_CH2IDLE, + .pol = CONFIG_STM32_TIM2_CH2POL, + .idle = CONFIG_STM32_TIM2_CH2IDLE, .pincfg = PWM_TIM2_CH2CFG, } #endif /* No complementary outputs */ }, #endif -#ifdef CONFIG_STM32H5_TIM2_CHANNEL3 +#ifdef CONFIG_STM32_TIM2_CHANNEL3 { .channel = 3, - .mode = CONFIG_STM32H5_TIM2_CH3MODE, -#ifdef CONFIG_STM32H5_TIM2_CH3OUT + .mode = CONFIG_STM32_TIM2_CH3MODE, +#ifdef CONFIG_STM32_TIM2_CH3OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H5_TIM2_CH3POL, - .idle = CONFIG_STM32H5_TIM2_CH3IDLE, + .pol = CONFIG_STM32_TIM2_CH3POL, + .idle = CONFIG_STM32_TIM2_CH3IDLE, .pincfg = PWM_TIM2_CH3CFG, } #endif /* No complementary outputs */ }, #endif -#ifdef CONFIG_STM32H5_TIM2_CHANNEL4 +#ifdef CONFIG_STM32_TIM2_CHANNEL4 { .channel = 4, - .mode = CONFIG_STM32H5_TIM2_CH4MODE, -#ifdef CONFIG_STM32H5_TIM2_CH4OUT + .mode = CONFIG_STM32_TIM2_CH4MODE, +#ifdef CONFIG_STM32_TIM2_CH4OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H5_TIM2_CH4POL, - .idle = CONFIG_STM32H5_TIM2_CH4IDLE, + .pol = CONFIG_STM32_TIM2_CH4POL, + .idle = CONFIG_STM32_TIM2_CH4IDLE, .pincfg = PWM_TIM2_CH4CFG, } #endif @@ -615,14 +615,14 @@ static struct stm32_pwmchan_s g_pwm2channels[] = static struct stm32_pwmtimer_s g_pwm2dev = { .ops = &g_pwmops, -#ifdef CONFIG_STM32H5_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS .llops = &g_llpwmops, #endif .timid = 2, .chan_num = PWM_TIM2_NCHANNELS, .channels = g_pwm2channels, .timtype = TIMTYPE_TIM2, - .mode = CONFIG_STM32H5_TIM2_MODE, + .mode = CONFIG_STM32_TIM2_MODE, .lock = 0, /* No lock */ .t_dts = 0, /* No t_dts */ #ifdef HAVE_PWM_COMPLEMENTARY @@ -634,72 +634,72 @@ static struct stm32_pwmtimer_s g_pwm2dev = .base = STM32_TIM2_BASE, .pclk = TIMCLK_TIM2, }; -#endif /* CONFIG_STM32H5_TIM2_PWM */ +#endif /* CONFIG_STM32_TIM2_PWM */ -#ifdef CONFIG_STM32H5_TIM3_PWM +#ifdef CONFIG_STM32_TIM3_PWM static struct stm32_pwmchan_s g_pwm3channels[] = { /* TIM3 has 4 channels */ -#ifdef CONFIG_STM32H5_TIM3_CHANNEL1 +#ifdef CONFIG_STM32_TIM3_CHANNEL1 { .channel = 1, - .mode = CONFIG_STM32H5_TIM3_CH1MODE, -#ifdef CONFIG_STM32H5_TIM3_CH1OUT + .mode = CONFIG_STM32_TIM3_CH1MODE, +#ifdef CONFIG_STM32_TIM3_CH1OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H5_TIM3_CH1POL, - .idle = CONFIG_STM32H5_TIM3_CH1IDLE, + .pol = CONFIG_STM32_TIM3_CH1POL, + .idle = CONFIG_STM32_TIM3_CH1IDLE, .pincfg = PWM_TIM3_CH1CFG, } #endif /* No complementary outputs */ }, #endif -#ifdef CONFIG_STM32H5_TIM3_CHANNEL2 +#ifdef CONFIG_STM32_TIM3_CHANNEL2 { .channel = 2, - .mode = CONFIG_STM32H5_TIM3_CH2MODE, -#ifdef CONFIG_STM32H5_TIM3_CH2OUT + .mode = CONFIG_STM32_TIM3_CH2MODE, +#ifdef CONFIG_STM32_TIM3_CH2OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H5_TIM3_CH2POL, - .idle = CONFIG_STM32H5_TIM3_CH2IDLE, + .pol = CONFIG_STM32_TIM3_CH2POL, + .idle = CONFIG_STM32_TIM3_CH2IDLE, .pincfg = PWM_TIM3_CH2CFG, } #endif /* No complementary outputs */ }, #endif -#ifdef CONFIG_STM32H5_TIM3_CHANNEL3 +#ifdef CONFIG_STM32_TIM3_CHANNEL3 { .channel = 3, - .mode = CONFIG_STM32H5_TIM3_CH3MODE, -#ifdef CONFIG_STM32H5_TIM3_CH3OUT + .mode = CONFIG_STM32_TIM3_CH3MODE, +#ifdef CONFIG_STM32_TIM3_CH3OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H5_TIM3_CH3POL, - .idle = CONFIG_STM32H5_TIM3_CH3IDLE, + .pol = CONFIG_STM32_TIM3_CH3POL, + .idle = CONFIG_STM32_TIM3_CH3IDLE, .pincfg = PWM_TIM3_CH3CFG, } #endif /* No complementary outputs */ }, #endif -#ifdef CONFIG_STM32H5_TIM3_CHANNEL4 +#ifdef CONFIG_STM32_TIM3_CHANNEL4 { .channel = 4, - .mode = CONFIG_STM32H5_TIM3_CH4MODE, -#ifdef CONFIG_STM32H5_TIM3_CH4OUT + .mode = CONFIG_STM32_TIM3_CH4MODE, +#ifdef CONFIG_STM32_TIM3_CH4OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H5_TIM3_CH4POL, - .idle = CONFIG_STM32H5_TIM3_CH4IDLE, + .pol = CONFIG_STM32_TIM3_CH4POL, + .idle = CONFIG_STM32_TIM3_CH4IDLE, .pincfg = PWM_TIM3_CH4CFG, } #endif @@ -711,14 +711,14 @@ static struct stm32_pwmchan_s g_pwm3channels[] = static struct stm32_pwmtimer_s g_pwm3dev = { .ops = &g_pwmops, -#ifdef CONFIG_STM32H5_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS .llops = &g_llpwmops, #endif .timid = 3, .chan_num = PWM_TIM3_NCHANNELS, .channels = g_pwm3channels, .timtype = TIMTYPE_TIM3, - .mode = CONFIG_STM32H5_TIM3_MODE, + .mode = CONFIG_STM32_TIM3_MODE, .lock = 0, /* No lock */ .t_dts = 0, /* No t_dts */ #ifdef HAVE_PWM_COMPLEMENTARY @@ -730,72 +730,72 @@ static struct stm32_pwmtimer_s g_pwm3dev = .base = STM32_TIM3_BASE, .pclk = TIMCLK_TIM3, }; -#endif /* CONFIG_STM32H5_TIM3_PWM */ +#endif /* CONFIG_STM32_TIM3_PWM */ -#ifdef CONFIG_STM32H5_TIM4_PWM +#ifdef CONFIG_STM32_TIM4_PWM static struct stm32_pwmchan_s g_pwm4channels[] = { /* TIM4 has 4 channels */ -#ifdef CONFIG_STM32H5_TIM4_CHANNEL1 +#ifdef CONFIG_STM32_TIM4_CHANNEL1 { .channel = 1, - .mode = CONFIG_STM32H5_TIM4_CH1MODE, -#ifdef CONFIG_STM32H5_TIM4_CH1OUT + .mode = CONFIG_STM32_TIM4_CH1MODE, +#ifdef CONFIG_STM32_TIM4_CH1OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H5_TIM4_CH1POL, - .idle = CONFIG_STM32H5_TIM4_CH1IDLE, + .pol = CONFIG_STM32_TIM4_CH1POL, + .idle = CONFIG_STM32_TIM4_CH1IDLE, .pincfg = PWM_TIM4_CH1CFG, } #endif /* No complementary outputs */ }, #endif -#ifdef CONFIG_STM32H5_TIM4_CHANNEL2 +#ifdef CONFIG_STM32_TIM4_CHANNEL2 { .channel = 2, - .mode = CONFIG_STM32H5_TIM4_CH2MODE, -#ifdef CONFIG_STM32H5_TIM4_CH2OUT + .mode = CONFIG_STM32_TIM4_CH2MODE, +#ifdef CONFIG_STM32_TIM4_CH2OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H5_TIM4_CH2POL, - .idle = CONFIG_STM32H5_TIM4_CH2IDLE, + .pol = CONFIG_STM32_TIM4_CH2POL, + .idle = CONFIG_STM32_TIM4_CH2IDLE, .pincfg = PWM_TIM4_CH2CFG, } #endif /* No complementary outputs */ }, #endif -#ifdef CONFIG_STM32H5_TIM4_CHANNEL3 +#ifdef CONFIG_STM32_TIM4_CHANNEL3 { .channel = 3, - .mode = CONFIG_STM32H5_TIM4_CH3MODE, -#ifdef CONFIG_STM32H5_TIM4_CH3OUT + .mode = CONFIG_STM32_TIM4_CH3MODE, +#ifdef CONFIG_STM32_TIM4_CH3OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H5_TIM4_CH3POL, - .idle = CONFIG_STM32H5_TIM4_CH3IDLE, + .pol = CONFIG_STM32_TIM4_CH3POL, + .idle = CONFIG_STM32_TIM4_CH3IDLE, .pincfg = PWM_TIM4_CH3CFG, } #endif /* No complementary outputs */ }, #endif -#ifdef CONFIG_STM32H5_TIM4_CHANNEL4 +#ifdef CONFIG_STM32_TIM4_CHANNEL4 { .channel = 4, - .mode = CONFIG_STM32H5_TIM4_CH4MODE, -#ifdef CONFIG_STM32H5_TIM4_CH4OUT + .mode = CONFIG_STM32_TIM4_CH4MODE, +#ifdef CONFIG_STM32_TIM4_CH4OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H5_TIM4_CH4POL, - .idle = CONFIG_STM32H5_TIM4_CH4IDLE, + .pol = CONFIG_STM32_TIM4_CH4POL, + .idle = CONFIG_STM32_TIM4_CH4IDLE, .pincfg = PWM_TIM4_CH4CFG, } #endif @@ -807,14 +807,14 @@ static struct stm32_pwmchan_s g_pwm4channels[] = static struct stm32_pwmtimer_s g_pwm4dev = { .ops = &g_pwmops, -#ifdef CONFIG_STM32H5_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS .llops = &g_llpwmops, #endif .timid = 4, .chan_num = PWM_TIM4_NCHANNELS, .channels = g_pwm4channels, .timtype = TIMTYPE_TIM4, - .mode = CONFIG_STM32H5_TIM4_MODE, + .mode = CONFIG_STM32_TIM4_MODE, .lock = 0, /* No lock */ .t_dts = 0, /* No t_dts */ #ifdef HAVE_PWM_COMPLEMENTARY @@ -826,71 +826,71 @@ static struct stm32_pwmtimer_s g_pwm4dev = .base = STM32_TIM4_BASE, .pclk = TIMCLK_TIM4, }; -#endif /* CONFIG_STM32H5_TIM4_PWM */ +#endif /* CONFIG_STM32_TIM4_PWM */ -#ifdef CONFIG_STM32H5_TIM5_PWM +#ifdef CONFIG_STM32_TIM5_PWM static struct stm32_pwmchan_s g_pwm5channels[] = { /* TIM5 has 4 channels */ -#ifdef CONFIG_STM32H5_TIM5_CHANNEL1 +#ifdef CONFIG_STM32_TIM5_CHANNEL1 { .channel = 1, - .mode = CONFIG_STM32H5_TIM5_CH1MODE, -#ifdef CONFIG_STM32H5_TIM5_CH1OUT + .mode = CONFIG_STM32_TIM5_CH1MODE, +#ifdef CONFIG_STM32_TIM5_CH1OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H5_TIM5_CH1POL, - .idle = CONFIG_STM32H5_TIM5_CH1IDLE, + .pol = CONFIG_STM32_TIM5_CH1POL, + .idle = CONFIG_STM32_TIM5_CH1IDLE, .pincfg = PWM_TIM5_CH1CFG, } #endif /* No complementary outputs */ }, #endif -#ifdef CONFIG_STM32H5_TIM5_CHANNEL2 +#ifdef CONFIG_STM32_TIM5_CHANNEL2 { .channel = 2, - .mode = CONFIG_STM32H5_TIM5_CH2MODE, -#ifdef CONFIG_STM32H5_TIM5_CH2OUT + .mode = CONFIG_STM32_TIM5_CH2MODE, +#ifdef CONFIG_STM32_TIM5_CH2OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H5_TIM5_CH2POL, - .idle = CONFIG_STM32H5_TIM5_CH2IDLE, + .pol = CONFIG_STM32_TIM5_CH2POL, + .idle = CONFIG_STM32_TIM5_CH2IDLE, .pincfg = PWM_TIM5_CH2CFG, } #endif /* No complementary outputs */ }, #endif -#ifdef CONFIG_STM32H5_TIM5_CHANNEL3 +#ifdef CONFIG_STM32_TIM5_CHANNEL3 { .channel = 3, - .mode = CONFIG_STM32H5_TIM5_CH3MODE, -#ifdef CONFIG_STM32H5_TIM5_CH3OUT + .mode = CONFIG_STM32_TIM5_CH3MODE, +#ifdef CONFIG_STM32_TIM5_CH3OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H5_TIM5_CH3POL, - .idle = CONFIG_STM32H5_TIM5_CH3IDLE, + .pol = CONFIG_STM32_TIM5_CH3POL, + .idle = CONFIG_STM32_TIM5_CH3IDLE, .pincfg = PWM_TIM5_CH3CFG, } #endif }, #endif -#ifdef CONFIG_STM32H5_TIM5_CHANNEL4 +#ifdef CONFIG_STM32_TIM5_CHANNEL4 { .channel = 4, - .mode = CONFIG_STM32H5_TIM5_CH4MODE, -#ifdef CONFIG_STM32H5_TIM5_CH4OUT + .mode = CONFIG_STM32_TIM5_CH4MODE, +#ifdef CONFIG_STM32_TIM5_CH4OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H5_TIM5_CH4POL, - .idle = CONFIG_STM32H5_TIM5_CH4IDLE, + .pol = CONFIG_STM32_TIM5_CH4POL, + .idle = CONFIG_STM32_TIM5_CH4IDLE, .pincfg = PWM_TIM5_CH4CFG, } #endif @@ -901,14 +901,14 @@ static struct stm32_pwmchan_s g_pwm5channels[] = static struct stm32_pwmtimer_s g_pwm5dev = { .ops = &g_pwmops, -#ifdef CONFIG_STM32H5_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS .llops = &g_llpwmops, #endif .timid = 5, .chan_num = PWM_TIM5_NCHANNELS, .channels = g_pwm5channels, .timtype = TIMTYPE_TIM5, - .mode = CONFIG_STM32H5_TIM5_MODE, + .mode = CONFIG_STM32_TIM5_MODE, .lock = 0, /* No lock */ .t_dts = 0, /* No t_dts */ #ifdef HAVE_PWM_COMPLEMENTARY @@ -920,140 +920,140 @@ static struct stm32_pwmtimer_s g_pwm5dev = .base = STM32_TIM5_BASE, .pclk = TIMCLK_TIM5, }; -#endif /* CONFIG_STM32H5_TIM5_PWM */ +#endif /* CONFIG_STM32_TIM5_PWM */ -#ifdef CONFIG_STM32H5_TIM8_PWM +#ifdef CONFIG_STM32_TIM8_PWM static struct stm32_pwmchan_s g_pwm8channels[] = { /* TIM8 has 4 channels, 4 complementary */ -#ifdef CONFIG_STM32H5_TIM8_CHANNEL1 +#ifdef CONFIG_STM32_TIM8_CHANNEL1 { .channel = 1, - .mode = CONFIG_STM32H5_TIM8_CH1MODE, + .mode = CONFIG_STM32_TIM8_CH1MODE, #ifdef HAVE_BREAK .brk = { -#ifdef CONFIG_STM32H5_TIM8_BREAK1 +#ifdef CONFIG_STM32_TIM8_BREAK1 .en1 = 1, - .pol1 = CONFIG_STM32H5_TIM8_BRK1POL, + .pol1 = CONFIG_STM32_TIM8_BRK1POL, #endif -#ifdef CONFIG_STM32H5_TIM8_BREAK2 +#ifdef CONFIG_STM32_TIM8_BREAK2 .en2 = 1, - .pol2 = CONFIG_STM32H5_TIM8_BRK2POL, - .flt2 = CONFIG_STM32H5_TIM8_BRK2FLT, + .pol2 = CONFIG_STM32_TIM8_BRK2POL, + .flt2 = CONFIG_STM32_TIM8_BRK2FLT, #endif }, #endif -#ifdef CONFIG_STM32H5_TIM8_CH1OUT +#ifdef CONFIG_STM32_TIM8_CH1OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H5_TIM8_CH1POL, - .idle = CONFIG_STM32H5_TIM8_CH1IDLE, + .pol = CONFIG_STM32_TIM8_CH1POL, + .idle = CONFIG_STM32_TIM8_CH1IDLE, .pincfg = PWM_TIM8_CH1CFG, }, #endif -#ifdef CONFIG_STM32H5_TIM8_CH1NOUT +#ifdef CONFIG_STM32_TIM8_CH1NOUT .out2 = { .in_use = 1, - .pol = CONFIG_STM32H5_TIM8_CH1NPOL, - .idle = CONFIG_STM32H5_TIM8_CH1NIDLE, + .pol = CONFIG_STM32_TIM8_CH1NPOL, + .idle = CONFIG_STM32_TIM8_CH1NIDLE, .pincfg = PWM_TIM8_CH1NCFG, } #endif }, #endif -#ifdef CONFIG_STM32H5_TIM8_CHANNEL2 +#ifdef CONFIG_STM32_TIM8_CHANNEL2 { .channel = 2, - .mode = CONFIG_STM32H5_TIM8_CH2MODE, -#ifdef CONFIG_STM32H5_TIM8_CH2OUT + .mode = CONFIG_STM32_TIM8_CH2MODE, +#ifdef CONFIG_STM32_TIM8_CH2OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H5_TIM8_CH2POL, - .idle = CONFIG_STM32H5_TIM8_CH2IDLE, + .pol = CONFIG_STM32_TIM8_CH2POL, + .idle = CONFIG_STM32_TIM8_CH2IDLE, .pincfg = PWM_TIM8_CH2CFG, }, #endif -#ifdef CONFIG_STM32H5_TIM8_CH2NOUT +#ifdef CONFIG_STM32_TIM8_CH2NOUT .out2 = { .in_use = 1, - .pol = CONFIG_STM32H5_TIM8_CH2NPOL, - .idle = CONFIG_STM32H5_TIM8_CH2NIDLE, + .pol = CONFIG_STM32_TIM8_CH2NPOL, + .idle = CONFIG_STM32_TIM8_CH2NIDLE, .pincfg = PWM_TIM8_CH2NCFG, } #endif }, #endif -#ifdef CONFIG_STM32H5_TIM8_CHANNEL3 +#ifdef CONFIG_STM32_TIM8_CHANNEL3 { .channel = 3, - .mode = CONFIG_STM32H5_TIM8_CH3MODE, -#ifdef CONFIG_STM32H5_TIM8_CH3OUT + .mode = CONFIG_STM32_TIM8_CH3MODE, +#ifdef CONFIG_STM32_TIM8_CH3OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H5_TIM8_CH3POL, - .idle = CONFIG_STM32H5_TIM8_CH3IDLE, + .pol = CONFIG_STM32_TIM8_CH3POL, + .idle = CONFIG_STM32_TIM8_CH3IDLE, .pincfg = PWM_TIM8_CH3CFG, }, #endif -#ifdef CONFIG_STM32H5_TIM8_CH3NOUT +#ifdef CONFIG_STM32_TIM8_CH3NOUT .out2 = { .in_use = 1, - .pol = CONFIG_STM32H5_TIM8_CH3NPOL, - .idle = CONFIG_STM32H5_TIM8_CH3NIDLE, + .pol = CONFIG_STM32_TIM8_CH3NPOL, + .idle = CONFIG_STM32_TIM8_CH3NIDLE, .pincfg = PWM_TIM8_CH3NCFG, } #endif }, #endif -#ifdef CONFIG_STM32H5_TIM8_CHANNEL4 +#ifdef CONFIG_STM32_TIM8_CHANNEL4 { .channel = 4, - .mode = CONFIG_STM32H5_TIM8_CH4MODE, -#ifdef CONFIG_STM32H5_TIM8_CH4OUT + .mode = CONFIG_STM32_TIM8_CH4MODE, +#ifdef CONFIG_STM32_TIM8_CH4OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H5_TIM8_CH4POL, - .idle = CONFIG_STM32H5_TIM8_CH4IDLE, + .pol = CONFIG_STM32_TIM8_CH4POL, + .idle = CONFIG_STM32_TIM8_CH4IDLE, .pincfg = PWM_TIM8_CH4CFG, } #endif }, #endif -#ifdef CONFIG_STM32H5_TIM8_CHANNEL5 +#ifdef CONFIG_STM32_TIM8_CHANNEL5 { .channel = 5, - .mode = CONFIG_STM32H5_TIM8_CH5MODE, -#ifdef CONFIG_STM32H5_TIM8_CH5OUT + .mode = CONFIG_STM32_TIM8_CH5MODE, +#ifdef CONFIG_STM32_TIM8_CH5OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H5_TIM8_CH5POL, - .idle = CONFIG_STM32H5_TIM8_CH5IDLE, + .pol = CONFIG_STM32_TIM8_CH5POL, + .idle = CONFIG_STM32_TIM8_CH5IDLE, .pincfg = 0, /* Not available externally */ } #endif }, #endif -#ifdef CONFIG_STM32H5_TIM8_CHANNEL6 +#ifdef CONFIG_STM32_TIM8_CHANNEL6 { .channel = 6, - .mode = CONFIG_STM32H5_TIM8_CH6MODE, -#ifdef CONFIG_STM32H5_TIM8_CH6OUT + .mode = CONFIG_STM32_TIM8_CH6MODE, +#ifdef CONFIG_STM32_TIM8_CH6OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H5_TIM8_CH6POL, - .idle = CONFIG_STM32H5_TIM8_CH6IDLE, + .pol = CONFIG_STM32_TIM8_CH6POL, + .idle = CONFIG_STM32_TIM8_CH6IDLE, .pincfg = 0, /* Not available externally */ } #endif @@ -1064,18 +1064,18 @@ static struct stm32_pwmchan_s g_pwm8channels[] = static struct stm32_pwmtimer_s g_pwm8dev = { .ops = &g_pwmops, -#ifdef CONFIG_STM32H5_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS .llops = &g_llpwmops, #endif .timid = 8, .chan_num = PWM_TIM8_NCHANNELS, .channels = g_pwm8channels, .timtype = TIMTYPE_TIM8, - .mode = CONFIG_STM32H5_TIM8_MODE, - .lock = CONFIG_STM32H5_TIM8_LOCK, - .t_dts = CONFIG_STM32H5_TIM8_TDTS, + .mode = CONFIG_STM32_TIM8_MODE, + .lock = CONFIG_STM32_TIM8_LOCK, + .t_dts = CONFIG_STM32_TIM8_TDTS, #ifdef HAVE_PWM_COMPLEMENTARY - .deadtime = CONFIG_STM32H5_TIM8_DEADTIME, + .deadtime = CONFIG_STM32_TIM8_DEADTIME, #endif #if defined(HAVE_TRGO) && defined(STM32_TIM8_TRGO) .trgo = STM32_TIM8_TRGO, @@ -1083,40 +1083,40 @@ static struct stm32_pwmtimer_s g_pwm8dev = .base = STM32_TIM8_BASE, .pclk = TIMCLK_TIM8, }; -#endif /* CONFIG_STM32H5_TIM8_PWM */ +#endif /* CONFIG_STM32_TIM8_PWM */ -#ifdef CONFIG_STM32H5_TIM12_PWM +#ifdef CONFIG_STM32_TIM12_PWM static struct stm32_pwmchan_s g_pwm12channels[] = { /* TIM12 has 2 channels */ -#ifdef CONFIG_STM32H5_TIM12_CHANNEL1 +#ifdef CONFIG_STM32_TIM12_CHANNEL1 { .channel = 1, - .mode = CONFIG_STM32H5_TIM12_CH1MODE, -#ifdef CONFIG_STM32H5_TIM12_CH1OUT + .mode = CONFIG_STM32_TIM12_CH1MODE, +#ifdef CONFIG_STM32_TIM12_CH1OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H5_TIM12_CH1POL, - .idle = CONFIG_STM32H5_TIM12_CH1IDLE, + .pol = CONFIG_STM32_TIM12_CH1POL, + .idle = CONFIG_STM32_TIM12_CH1IDLE, .pincfg = PWM_TIM12_CH1CFG, } #endif /* No complementary outputs */ }, #endif -#ifdef CONFIG_STM32H5_TIM12_CHANNEL2 +#ifdef CONFIG_STM32_TIM12_CHANNEL2 { .channel = 2, - .mode = CONFIG_STM32H5_TIM12_CH2MODE, -#ifdef CONFIG_STM32H5_TIM12_CH2OUT + .mode = CONFIG_STM32_TIM12_CH2MODE, +#ifdef CONFIG_STM32_TIM12_CH2OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H5_TIM12_CH2POL, - .idle = CONFIG_STM32H5_TIM12_CH2IDLE, + .pol = CONFIG_STM32_TIM12_CH2POL, + .idle = CONFIG_STM32_TIM12_CH2IDLE, .pincfg = PWM_TIM12_CH2CFG, } #endif @@ -1128,7 +1128,7 @@ static struct stm32_pwmchan_s g_pwm12channels[] = static struct stm32_pwmtimer_s g_pwm12dev = { .ops = &g_pwmops, -#ifdef CONFIG_STM32H5_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS .llops = &g_llpwmops, #endif .timid = 12, @@ -1147,24 +1147,24 @@ static struct stm32_pwmtimer_s g_pwm12dev = .base = STM32_TIM12_BASE, .pclk = TIMCLK_TIM12, }; -#endif /* CONFIG_STM32H5_TIM12_PWM */ +#endif /* CONFIG_STM32_TIM12_PWM */ -#ifdef CONFIG_STM32H5_TIM13_PWM +#ifdef CONFIG_STM32_TIM13_PWM static struct stm32_pwmchan_s g_pwm13channels[] = { /* TIM13 has 1 channel */ -#ifdef CONFIG_STM32H5_TIM13_CHANNEL1 +#ifdef CONFIG_STM32_TIM13_CHANNEL1 { .channel = 1, - .mode = CONFIG_STM32H5_TIM13_CH1MODE, -#ifdef CONFIG_STM32H5_TIM13_CH1OUT + .mode = CONFIG_STM32_TIM13_CH1MODE, +#ifdef CONFIG_STM32_TIM13_CH1OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H5_TIM13_CH1POL, - .idle = CONFIG_STM32H5_TIM13_CH1IDLE, + .pol = CONFIG_STM32_TIM13_CH1POL, + .idle = CONFIG_STM32_TIM13_CH1IDLE, .pincfg = PWM_TIM13_CH1CFG, } #endif @@ -1176,7 +1176,7 @@ static struct stm32_pwmchan_s g_pwm13channels[] = static struct stm32_pwmtimer_s g_pwm13dev = { .ops = &g_pwmops, -#ifdef CONFIG_STM32H5_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS .llops = &g_llpwmops, #endif .timid = 13, @@ -1195,24 +1195,24 @@ static struct stm32_pwmtimer_s g_pwm13dev = .base = STM32_TIM13_BASE, .pclk = TIMCLK_TIM13, }; -#endif /* CONFIG_STM32H5_TIM13_PWM */ +#endif /* CONFIG_STM32_TIM13_PWM */ -#ifdef CONFIG_STM32H5_TIM14_PWM +#ifdef CONFIG_STM32_TIM14_PWM static struct stm32_pwmchan_s g_pwm14channels[] = { /* TIM14 has 1 channel */ -#ifdef CONFIG_STM32H5_TIM14_CHANNEL1 +#ifdef CONFIG_STM32_TIM14_CHANNEL1 { .channel = 1, - .mode = CONFIG_STM32H5_TIM14_CH1MODE, -#ifdef CONFIG_STM32H5_TIM14_CH1OUT + .mode = CONFIG_STM32_TIM14_CH1MODE, +#ifdef CONFIG_STM32_TIM14_CH1OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H5_TIM14_CH1POL, - .idle = CONFIG_STM32H5_TIM14_CH1IDLE, + .pol = CONFIG_STM32_TIM14_CH1POL, + .idle = CONFIG_STM32_TIM14_CH1IDLE, .pincfg = PWM_TIM14_CH1CFG, } #endif @@ -1224,7 +1224,7 @@ static struct stm32_pwmchan_s g_pwm14channels[] = static struct stm32_pwmtimer_s g_pwm14dev = { .ops = &g_pwmops, -#ifdef CONFIG_STM32H5_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS .llops = &g_llpwmops, #endif .timid = 14, @@ -1243,58 +1243,58 @@ static struct stm32_pwmtimer_s g_pwm14dev = .base = STM32_TIM14_BASE, .pclk = TIMCLK_TIM14, }; -#endif /* CONFIG_STM32H5_TIM14_PWM */ +#endif /* CONFIG_STM32_TIM14_PWM */ -#ifdef CONFIG_STM32H5_TIM15_PWM +#ifdef CONFIG_STM32_TIM15_PWM static struct stm32_pwmchan_s g_pwm15channels[] = { /* TIM15 has 2 channels, 1 complementary */ -#ifdef CONFIG_STM32H5_TIM15_CHANNEL1 +#ifdef CONFIG_STM32_TIM15_CHANNEL1 { .channel = 1, - .mode = CONFIG_STM32H5_TIM15_CH1MODE, + .mode = CONFIG_STM32_TIM15_CH1MODE, #ifdef HAVE_BREAK .brk = { -#ifdef CONFIG_STM32H5_TIM15_BREAK1 +#ifdef CONFIG_STM32_TIM15_BREAK1 .en1 = 1, - .pol1 = CONFIG_STM32H5_TIM15_BRK1POL, + .pol1 = CONFIG_STM32_TIM15_BRK1POL, #endif /* No BREAK2 */ }, #endif -#ifdef CONFIG_STM32H5_TIM15_CH1OUT +#ifdef CONFIG_STM32_TIM15_CH1OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H5_TIM15_CH1POL, - .idle = CONFIG_STM32H5_TIM15_CH1IDLE, + .pol = CONFIG_STM32_TIM15_CH1POL, + .idle = CONFIG_STM32_TIM15_CH1IDLE, .pincfg = PWM_TIM15_CH1CFG, }, #endif -#ifdef CONFIG_STM32H5_TIM15_CH1NOUT +#ifdef CONFIG_STM32_TIM15_CH1NOUT .out2 = { .in_use = 1, - .pol = CONFIG_STM32H5_TIM15_CH1NPOL, - .idle = CONFIG_STM32H5_TIM15_CH1NIDLE, + .pol = CONFIG_STM32_TIM15_CH1NPOL, + .idle = CONFIG_STM32_TIM15_CH1NIDLE, .pincfg = PWM_TIM15_CH2CFG, } #endif }, #endif -#ifdef CONFIG_STM32H5_TIM15_CHANNEL2 +#ifdef CONFIG_STM32_TIM15_CHANNEL2 { .channel = 2, - .mode = CONFIG_STM32H5_TIM15_CH2MODE, -#ifdef CONFIG_STM32H5_TIM12_CH2OUT + .mode = CONFIG_STM32_TIM15_CH2MODE, +#ifdef CONFIG_STM32_TIM12_CH2OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H5_TIM15_CH2POL, - .idle = CONFIG_STM32H5_TIM15_CH2IDLE, + .pol = CONFIG_STM32_TIM15_CH2POL, + .idle = CONFIG_STM32_TIM15_CH2IDLE, .pincfg = PWM_TIM15_CH2CFG, } #endif @@ -1306,7 +1306,7 @@ static struct stm32_pwmchan_s g_pwm15channels[] = static struct stm32_pwmtimer_s g_pwm15dev = { .ops = &g_pwmops, -#ifdef CONFIG_STM32H5_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS .llops = &g_llpwmops, #endif .timid = 15, @@ -1314,10 +1314,10 @@ static struct stm32_pwmtimer_s g_pwm15dev = .channels = g_pwm15channels, .timtype = TIMTYPE_TIM15, .mode = STM32_TIMMODE_COUNTUP, - .lock = CONFIG_STM32H5_TIM15_LOCK, - .t_dts = CONFIG_STM32H5_TIM15_TDTS, + .lock = CONFIG_STM32_TIM15_LOCK, + .t_dts = CONFIG_STM32_TIM15_TDTS, #ifdef HAVE_PWM_COMPLEMENTARY - .deadtime = CONFIG_STM32H5_TIM15_DEADTIME, + .deadtime = CONFIG_STM32_TIM15_DEADTIME, #endif #if defined(HAVE_TRGO) && defined(STM32_TIM15_TRGO) .trgo = STM32_TIM15_TRGO, @@ -1325,43 +1325,43 @@ static struct stm32_pwmtimer_s g_pwm15dev = .base = STM32_TIM15_BASE, .pclk = TIMCLK_TIM15, }; -#endif /* CONFIG_STM32H5_TIM15_PWM */ +#endif /* CONFIG_STM32_TIM15_PWM */ -#ifdef CONFIG_STM32H5_TIM16_PWM +#ifdef CONFIG_STM32_TIM16_PWM static struct stm32_pwmchan_s g_pwm16channels[] = { /* TIM16 has 1 channel, 1 complementary */ -#ifdef CONFIG_STM32H5_TIM16_CHANNEL1 +#ifdef CONFIG_STM32_TIM16_CHANNEL1 { .channel = 1, - .mode = CONFIG_STM32H5_TIM16_CH1MODE, + .mode = CONFIG_STM32_TIM16_CH1MODE, #ifdef HAVE_BREAK .brk = { -#ifdef CONFIG_STM32H5_TIM16_BREAK1 +#ifdef CONFIG_STM32_TIM16_BREAK1 .en1 = 1, - .pol1 = CONFIG_STM32H5_TIM16_BRK1POL, + .pol1 = CONFIG_STM32_TIM16_BRK1POL, #endif /* No BREAK2 */ }, #endif -#ifdef CONFIG_STM32H5_TIM16_CH1OUT +#ifdef CONFIG_STM32_TIM16_CH1OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H5_TIM16_CH1POL, - .idle = CONFIG_STM32H5_TIM16_CH1IDLE, + .pol = CONFIG_STM32_TIM16_CH1POL, + .idle = CONFIG_STM32_TIM16_CH1IDLE, .pincfg = PWM_TIM16_CH1CFG, }, #endif -#ifdef CONFIG_STM32H5_TIM16_CH1NOUT +#ifdef CONFIG_STM32_TIM16_CH1NOUT .out2 = { .in_use = 1, - .pol = CONFIG_STM32H5_TIM16_CH1NPOL, - .idle = CONFIG_STM32H5_TIM16_CH1NIDLE, + .pol = CONFIG_STM32_TIM16_CH1NPOL, + .idle = CONFIG_STM32_TIM16_CH1NIDLE, .pincfg = PWM_TIM16_CH2CFG, } #endif @@ -1372,7 +1372,7 @@ static struct stm32_pwmchan_s g_pwm16channels[] = static struct stm32_pwmtimer_s g_pwm16dev = { .ops = &g_pwmops, -#ifdef CONFIG_STM32H5_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS .llops = &g_llpwmops, #endif .timid = 16, @@ -1380,10 +1380,10 @@ static struct stm32_pwmtimer_s g_pwm16dev = .channels = g_pwm16channels, .timtype = TIMTYPE_TIM16, .mode = STM32_TIMMODE_COUNTUP, - .lock = CONFIG_STM32H5_TIM16_LOCK, - .t_dts = CONFIG_STM32H5_TIM16_TDTS, + .lock = CONFIG_STM32_TIM16_LOCK, + .t_dts = CONFIG_STM32_TIM16_TDTS, #ifdef HAVE_PWM_COMPLEMENTARY - .deadtime = CONFIG_STM32H5_TIM16_DEADTIME, + .deadtime = CONFIG_STM32_TIM16_DEADTIME, #endif #if defined(HAVE_TRGO) .trgo = 0, /* TRGO not supported for TIM16 */ @@ -1391,43 +1391,43 @@ static struct stm32_pwmtimer_s g_pwm16dev = .base = STM32_TIM16_BASE, .pclk = TIMCLK_TIM16, }; -#endif /* CONFIG_STM32H5_TIM16_PWM */ +#endif /* CONFIG_STM32_TIM16_PWM */ -#ifdef CONFIG_STM32H5_TIM17_PWM +#ifdef CONFIG_STM32_TIM17_PWM static struct stm32_pwmchan_s g_pwm17channels[] = { /* TIM17 has 1 channel, 1 complementary */ -#ifdef CONFIG_STM32H5_TIM17_CHANNEL1 +#ifdef CONFIG_STM32_TIM17_CHANNEL1 { .channel = 1, - .mode = CONFIG_STM32H5_TIM17_CH1MODE, + .mode = CONFIG_STM32_TIM17_CH1MODE, #ifdef HAVE_BREAK .brk = { -#ifdef CONFIG_STM32H5_TIM17_BREAK1 +#ifdef CONFIG_STM32_TIM17_BREAK1 .en1 = 1, - .pol1 = CONFIG_STM32H5_TIM17_BRK1POL, + .pol1 = CONFIG_STM32_TIM17_BRK1POL, #endif /* No BREAK2 */ }, #endif -#ifdef CONFIG_STM32H5_TIM17_CH1OUT +#ifdef CONFIG_STM32_TIM17_CH1OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H5_TIM17_CH1POL, - .idle = CONFIG_STM32H5_TIM17_CH1IDLE, + .pol = CONFIG_STM32_TIM17_CH1POL, + .idle = CONFIG_STM32_TIM17_CH1IDLE, .pincfg = PWM_TIM17_CH1CFG, }, #endif -#ifdef CONFIG_STM32H5_TIM17_CH1NOUT +#ifdef CONFIG_STM32_TIM17_CH1NOUT .out2 = { .in_use = 1, - .pol = CONFIG_STM32H5_TIM17_CH1NPOL, - .idle = CONFIG_STM32H5_TIM17_CH1NIDLE, + .pol = CONFIG_STM32_TIM17_CH1NPOL, + .idle = CONFIG_STM32_TIM17_CH1NIDLE, .pincfg = PWM_TIM17_CH2CFG, } #endif @@ -1438,7 +1438,7 @@ static struct stm32_pwmchan_s g_pwm17channels[] = static struct stm32_pwmtimer_s g_pwm17dev = { .ops = &g_pwmops, -#ifdef CONFIG_STM32H5_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS .llops = &g_llpwmops, #endif .timid = 17, @@ -1446,10 +1446,10 @@ static struct stm32_pwmtimer_s g_pwm17dev = .channels = g_pwm17channels, .timtype = TIMTYPE_TIM17, .mode = STM32_TIMMODE_COUNTUP, - .lock = CONFIG_STM32H5_TIM17_LOCK, - .t_dts = CONFIG_STM32H5_TIM17_TDTS, + .lock = CONFIG_STM32_TIM17_LOCK, + .t_dts = CONFIG_STM32_TIM17_TDTS, #ifdef HAVE_PWM_COMPLEMENTARY - .deadtime = CONFIG_STM32H5_TIM17_DEADTIME, + .deadtime = CONFIG_STM32_TIM17_DEADTIME, #endif #if defined(HAVE_TRGO) .trgo = 0, /* TRGO not supported for TIM17 */ @@ -1457,7 +1457,7 @@ static struct stm32_pwmtimer_s g_pwm17dev = .base = STM32_TIM17_BASE, .pclk = TIMCLK_TIM17, }; -#endif /* CONFIG_STM32H5_TIM17_PWM */ +#endif /* CONFIG_STM32_TIM17_PWM */ /* TODO: support for TIM19,20,21,22 */ @@ -1792,7 +1792,7 @@ static int pwm_ccr_update(struct pwm_lowerhalf_s *dev, uint8_t index, * Name: pwm_ccr_get ****************************************************************************/ -#ifdef CONFIG_STM32H5_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS static uint32_t pwm_ccr_get(struct pwm_lowerhalf_s *dev, uint8_t index) { struct stm32_pwmtimer_s *priv = (struct stm32_pwmtimer_s *)dev; @@ -1849,7 +1849,7 @@ static uint32_t pwm_ccr_get(struct pwm_lowerhalf_s *dev, uint8_t index) return pwm_getreg(priv, offset); } -#endif /* CONFIG_STM32H5_PWM_LL_OPS */ +#endif /* CONFIG_STM32_PWM_LL_OPS */ /**************************************************************************** * Name: pwm_arr_update @@ -2577,7 +2577,7 @@ static int pwm_outputs_enable(struct pwm_lowerhalf_s *dev, return OK; } -#if defined(HAVE_PWM_COMPLEMENTARY) && defined(CONFIG_STM32H5_PWM_LL_OPS) +#if defined(HAVE_PWM_COMPLEMENTARY) && defined(CONFIG_STM32_PWM_LL_OPS) /**************************************************************************** * Name: pwm_deadtime_update @@ -3130,7 +3130,7 @@ static int pwm_set_apb_clock(struct stm32_pwmtimer_s *priv, bool on) switch (priv->timid) { -#ifdef CONFIG_STM32H5_TIM1_PWM +#ifdef CONFIG_STM32_TIM1_PWM case 1: { regaddr = TIMRCCEN_TIM1; @@ -3139,7 +3139,7 @@ static int pwm_set_apb_clock(struct stm32_pwmtimer_s *priv, bool on) } #endif -#ifdef CONFIG_STM32H5_TIM2_PWM +#ifdef CONFIG_STM32_TIM2_PWM case 2: { regaddr = TIMRCCEN_TIM2; @@ -3148,7 +3148,7 @@ static int pwm_set_apb_clock(struct stm32_pwmtimer_s *priv, bool on) } #endif -#ifdef CONFIG_STM32H5_TIM3_PWM +#ifdef CONFIG_STM32_TIM3_PWM case 3: { regaddr = TIMRCCEN_TIM3; @@ -3157,7 +3157,7 @@ static int pwm_set_apb_clock(struct stm32_pwmtimer_s *priv, bool on) } #endif -#ifdef CONFIG_STM32H5_TIM4_PWM +#ifdef CONFIG_STM32_TIM4_PWM case 4: { regaddr = TIMRCCEN_TIM4; @@ -3166,7 +3166,7 @@ static int pwm_set_apb_clock(struct stm32_pwmtimer_s *priv, bool on) } #endif -#ifdef CONFIG_STM32H5_TIM5_PWM +#ifdef CONFIG_STM32_TIM5_PWM case 5: { regaddr = TIMRCCEN_TIM5; @@ -3175,7 +3175,7 @@ static int pwm_set_apb_clock(struct stm32_pwmtimer_s *priv, bool on) } #endif -#ifdef CONFIG_STM32H5_TIM8_PWM +#ifdef CONFIG_STM32_TIM8_PWM case 8: { regaddr = TIMRCCEN_TIM8; @@ -3184,7 +3184,7 @@ static int pwm_set_apb_clock(struct stm32_pwmtimer_s *priv, bool on) } #endif -#ifdef CONFIG_STM32H5_TIM12_PWM +#ifdef CONFIG_STM32_TIM12_PWM case 12: { regaddr = TIMRCCEN_TIM12; @@ -3193,7 +3193,7 @@ static int pwm_set_apb_clock(struct stm32_pwmtimer_s *priv, bool on) } #endif -#ifdef CONFIG_STM32H5_TIM13_PWM +#ifdef CONFIG_STM32_TIM13_PWM case 13: { regaddr = TIMRCCEN_TIM13; @@ -3202,7 +3202,7 @@ static int pwm_set_apb_clock(struct stm32_pwmtimer_s *priv, bool on) } #endif -#ifdef CONFIG_STM32H5_TIM14_PWM +#ifdef CONFIG_STM32_TIM14_PWM case 14: { regaddr = TIMRCCEN_TIM14; @@ -3211,7 +3211,7 @@ static int pwm_set_apb_clock(struct stm32_pwmtimer_s *priv, bool on) } #endif -#ifdef CONFIG_STM32H5_TIM15_PWM +#ifdef CONFIG_STM32_TIM15_PWM case 15: { regaddr = TIMRCCEN_TIM15; @@ -3220,7 +3220,7 @@ static int pwm_set_apb_clock(struct stm32_pwmtimer_s *priv, bool on) } #endif -#ifdef CONFIG_STM32H5_TIM16_PWM +#ifdef CONFIG_STM32_TIM16_PWM case 16: { regaddr = TIMRCCEN_TIM16; @@ -3229,7 +3229,7 @@ static int pwm_set_apb_clock(struct stm32_pwmtimer_s *priv, bool on) } #endif -#ifdef CONFIG_STM32H5_TIM17_PWM +#ifdef CONFIG_STM32_TIM17_PWM case 17: { regaddr = TIMRCCEN_TIM17; @@ -3527,7 +3527,7 @@ static int pwm_stop(struct pwm_lowerhalf_s *dev) switch (priv->timid) { -#ifdef CONFIG_STM32H5_TIM1_PWM +#ifdef CONFIG_STM32_TIM1_PWM case 1: { regaddr = TIMRCCRST_TIM1; @@ -3536,7 +3536,7 @@ static int pwm_stop(struct pwm_lowerhalf_s *dev) } #endif -#ifdef CONFIG_STM32H5_TIM2_PWM +#ifdef CONFIG_STM32_TIM2_PWM case 2: { regaddr = TIMRCCRST_TIM2; @@ -3545,7 +3545,7 @@ static int pwm_stop(struct pwm_lowerhalf_s *dev) } #endif -#ifdef CONFIG_STM32H5_TIM3_PWM +#ifdef CONFIG_STM32_TIM3_PWM case 3: { regaddr = TIMRCCRST_TIM3; @@ -3554,7 +3554,7 @@ static int pwm_stop(struct pwm_lowerhalf_s *dev) } #endif -#ifdef CONFIG_STM32H5_TIM4_PWM +#ifdef CONFIG_STM32_TIM4_PWM case 4: { regaddr = TIMRCCRST_TIM4; @@ -3563,7 +3563,7 @@ static int pwm_stop(struct pwm_lowerhalf_s *dev) } #endif -#ifdef CONFIG_STM32H5_TIM5_PWM +#ifdef CONFIG_STM32_TIM5_PWM case 5: { regaddr = TIMRCCRST_TIM5; @@ -3572,7 +3572,7 @@ static int pwm_stop(struct pwm_lowerhalf_s *dev) } #endif -#ifdef CONFIG_STM32H5_TIM8_PWM +#ifdef CONFIG_STM32_TIM8_PWM case 8: { regaddr = TIMRCCRST_TIM8; @@ -3581,7 +3581,7 @@ static int pwm_stop(struct pwm_lowerhalf_s *dev) } #endif -#ifdef CONFIG_STM32H5_TIM12_PWM +#ifdef CONFIG_STM32_TIM12_PWM case 12: { regaddr = TIMRCCRST_TIM12; @@ -3590,7 +3590,7 @@ static int pwm_stop(struct pwm_lowerhalf_s *dev) } #endif -#ifdef CONFIG_STM32H5_TIM13_PWM +#ifdef CONFIG_STM32_TIM13_PWM case 13: { regaddr = TIMRCCRST_TIM13; @@ -3599,7 +3599,7 @@ static int pwm_stop(struct pwm_lowerhalf_s *dev) } #endif -#ifdef CONFIG_STM32H5_TIM14_PWM +#ifdef CONFIG_STM32_TIM14_PWM case 14: { regaddr = TIMRCCRST_TIM14; @@ -3608,7 +3608,7 @@ static int pwm_stop(struct pwm_lowerhalf_s *dev) } #endif -#ifdef CONFIG_STM32H5_TIM15_PWM +#ifdef CONFIG_STM32_TIM15_PWM case 15: { regaddr = TIMRCCRST_TIM15; @@ -3617,7 +3617,7 @@ static int pwm_stop(struct pwm_lowerhalf_s *dev) } #endif -#ifdef CONFIG_STM32H5_TIM16_PWM +#ifdef CONFIG_STM32_TIM16_PWM case 16: { regaddr = TIMRCCRST_TIM16; @@ -3626,7 +3626,7 @@ static int pwm_stop(struct pwm_lowerhalf_s *dev) } #endif -#ifdef CONFIG_STM32H5_TIM17_PWM +#ifdef CONFIG_STM32_TIM17_PWM case 17: { regaddr = TIMRCCRST_TIM17; @@ -3743,7 +3743,7 @@ struct pwm_lowerhalf_s *stm32_pwminitialize(int timer) switch (timer) { -#ifdef CONFIG_STM32H5_TIM1_PWM +#ifdef CONFIG_STM32_TIM1_PWM case 1: { lower = &g_pwm1dev; @@ -3754,7 +3754,7 @@ struct pwm_lowerhalf_s *stm32_pwminitialize(int timer) } #endif -#ifdef CONFIG_STM32H5_TIM2_PWM +#ifdef CONFIG_STM32_TIM2_PWM case 2: { lower = &g_pwm2dev; @@ -3762,7 +3762,7 @@ struct pwm_lowerhalf_s *stm32_pwminitialize(int timer) } #endif -#ifdef CONFIG_STM32H5_TIM3_PWM +#ifdef CONFIG_STM32_TIM3_PWM case 3: { lower = &g_pwm3dev; @@ -3770,7 +3770,7 @@ struct pwm_lowerhalf_s *stm32_pwminitialize(int timer) } #endif -#ifdef CONFIG_STM32H5_TIM4_PWM +#ifdef CONFIG_STM32_TIM4_PWM case 4: { lower = &g_pwm4dev; @@ -3778,7 +3778,7 @@ struct pwm_lowerhalf_s *stm32_pwminitialize(int timer) } #endif -#ifdef CONFIG_STM32H5_TIM5_PWM +#ifdef CONFIG_STM32_TIM5_PWM case 5: { lower = &g_pwm5dev; @@ -3786,7 +3786,7 @@ struct pwm_lowerhalf_s *stm32_pwminitialize(int timer) } #endif -#ifdef CONFIG_STM32H5_TIM8_PWM +#ifdef CONFIG_STM32_TIM8_PWM case 8: { lower = &g_pwm8dev; @@ -3797,7 +3797,7 @@ struct pwm_lowerhalf_s *stm32_pwminitialize(int timer) } #endif -#ifdef CONFIG_STM32H5_TIM12_PWM +#ifdef CONFIG_STM32_TIM12_PWM case 12: { lower = &g_pwm12dev; @@ -3805,7 +3805,7 @@ struct pwm_lowerhalf_s *stm32_pwminitialize(int timer) } #endif -#ifdef CONFIG_STM32H5_TIM13_PWM +#ifdef CONFIG_STM32_TIM13_PWM case 13: { lower = &g_pwm13dev; @@ -3813,7 +3813,7 @@ struct pwm_lowerhalf_s *stm32_pwminitialize(int timer) } #endif -#ifdef CONFIG_STM32H5_TIM14_PWM +#ifdef CONFIG_STM32_TIM14_PWM case 14: { lower = &g_pwm14dev; @@ -3821,7 +3821,7 @@ struct pwm_lowerhalf_s *stm32_pwminitialize(int timer) } #endif -#ifdef CONFIG_STM32H5_TIM15_PWM +#ifdef CONFIG_STM32_TIM15_PWM case 15: { lower = &g_pwm15dev; @@ -3829,7 +3829,7 @@ struct pwm_lowerhalf_s *stm32_pwminitialize(int timer) } #endif -#ifdef CONFIG_STM32H5_TIM16_PWM +#ifdef CONFIG_STM32_TIM16_PWM case 16: { lower = &g_pwm16dev; @@ -3837,7 +3837,7 @@ struct pwm_lowerhalf_s *stm32_pwminitialize(int timer) } #endif -#ifdef CONFIG_STM32H5_TIM17_PWM +#ifdef CONFIG_STM32_TIM17_PWM case 17: { lower = &g_pwm17dev; diff --git a/arch/arm/src/stm32h5/stm32_pwm.h b/arch/arm/src/stm32h5/stm32_pwm.h index 149de56fec9cd..138d2ad573b13 100644 --- a/arch/arm/src/stm32h5/stm32_pwm.h +++ b/arch/arm/src/stm32h5/stm32_pwm.h @@ -39,7 +39,7 @@ #include "chip.h" -#ifdef CONFIG_STM32H5_PWM +#ifdef CONFIG_STM32_PWM # include # include "hardware/stm32_tim.h" #endif @@ -52,89 +52,89 @@ /* Timer devices may be used for different purposes. One special purpose is * to generate modulated outputs for such things as motor control. - * If CONFIG_STM32H5_TIMn is defined then the CONFIG_STM32H5_TIMn_PWM must + * If CONFIG_STM32_TIMn is defined then the CONFIG_STM32_TIMn_PWM must * also be defined to indicate that timer "n" is intended to be used for * pulsed output signal generation. */ -#ifndef CONFIG_STM32H5_TIM1 -# undef CONFIG_STM32H5_TIM1_PWM +#ifndef CONFIG_STM32_TIM1 +# undef CONFIG_STM32_TIM1_PWM #endif -#ifndef CONFIG_STM32H5_TIM2 -# undef CONFIG_STM32H5_TIM2_PWM +#ifndef CONFIG_STM32_TIM2 +# undef CONFIG_STM32_TIM2_PWM #endif -#ifndef CONFIG_STM32H5_TIM3 -# undef CONFIG_STM32H5_TIM3_PWM +#ifndef CONFIG_STM32_TIM3 +# undef CONFIG_STM32_TIM3_PWM #endif -#ifndef CONFIG_STM32H5_TIM4 -# undef CONFIG_STM32H5_TIM4_PWM +#ifndef CONFIG_STM32_TIM4 +# undef CONFIG_STM32_TIM4_PWM #endif -#ifndef CONFIG_STM32H5_TIM5 -# undef CONFIG_STM32H5_TIM5_PWM +#ifndef CONFIG_STM32_TIM5 +# undef CONFIG_STM32_TIM5_PWM #endif -#ifndef CONFIG_STM32H5_TIM8 -# undef CONFIG_STM32H5_TIM8_PWM +#ifndef CONFIG_STM32_TIM8 +# undef CONFIG_STM32_TIM8_PWM #endif -#ifndef CONFIG_STM32H5_TIM12 -# undef CONFIG_STM32H5_TIM12_PWM +#ifndef CONFIG_STM32_TIM12 +# undef CONFIG_STM32_TIM12_PWM #endif -#ifndef CONFIG_STM32H5_TIM13 -# undef CONFIG_STM32H5_TIM13_PWM +#ifndef CONFIG_STM32_TIM13 +# undef CONFIG_STM32_TIM13_PWM #endif -#ifndef CONFIG_STM32H5_TIM14 -# undef CONFIG_STM32H5_TIM14_PWM +#ifndef CONFIG_STM32_TIM14 +# undef CONFIG_STM32_TIM14_PWM #endif -#ifndef CONFIG_STM32H5_TIM15 -# undef CONFIG_STM32H5_TIM15_PWM +#ifndef CONFIG_STM32_TIM15 +# undef CONFIG_STM32_TIM15_PWM #endif -#ifndef CONFIG_STM32H5_TIM16 -# undef CONFIG_STM32H5_TIM16_PWM +#ifndef CONFIG_STM32_TIM16 +# undef CONFIG_STM32_TIM16_PWM #endif -#ifndef CONFIG_STM32H5_TIM17 -# undef CONFIG_STM32H5_TIM17_PWM +#ifndef CONFIG_STM32_TIM17 +# undef CONFIG_STM32_TIM17_PWM #endif /* The basic timers (timer 6 and 7) are not capable of generating output * pulses */ -#undef CONFIG_STM32H5_TIM6_PWM -#undef CONFIG_STM32H5_TIM7_PWM +#undef CONFIG_STM32_TIM6_PWM +#undef CONFIG_STM32_TIM7_PWM /* Check if PWM support for any channel is enabled. */ -#ifdef CONFIG_STM32H5_PWM +#ifdef CONFIG_STM32_PWM /* PWM driver channels configuration */ -#ifdef CONFIG_STM32H5_PWM_MULTICHAN +#ifdef CONFIG_STM32_PWM_MULTICHAN -#ifdef CONFIG_STM32H5_TIM1_CHANNEL1 +#ifdef CONFIG_STM32_TIM1_CHANNEL1 # define PWM_TIM1_CHANNEL1 1 #else # define PWM_TIM1_CHANNEL1 0 #endif -#ifdef CONFIG_STM32H5_TIM1_CHANNEL2 +#ifdef CONFIG_STM32_TIM1_CHANNEL2 # define PWM_TIM1_CHANNEL2 1 #else # define PWM_TIM1_CHANNEL2 0 #endif -#ifdef CONFIG_STM32H5_TIM1_CHANNEL3 +#ifdef CONFIG_STM32_TIM1_CHANNEL3 # define PWM_TIM1_CHANNEL3 1 #else # define PWM_TIM1_CHANNEL3 0 #endif -#ifdef CONFIG_STM32H5_TIM1_CHANNEL4 +#ifdef CONFIG_STM32_TIM1_CHANNEL4 # define PWM_TIM1_CHANNEL4 1 #else # define PWM_TIM1_CHANNEL4 0 #endif -#ifdef CONFIG_STM32H5_TIM1_CHANNEL5 +#ifdef CONFIG_STM32_TIM1_CHANNEL5 # define PWM_TIM1_CHANNEL5 1 #else # define PWM_TIM1_CHANNEL5 0 #endif -#ifdef CONFIG_STM32H5_TIM1_CHANNEL6 +#ifdef CONFIG_STM32_TIM1_CHANNEL6 # define PWM_TIM1_CHANNEL6 1 #else # define PWM_TIM1_CHANNEL6 0 @@ -143,22 +143,22 @@ PWM_TIM1_CHANNEL3 + PWM_TIM1_CHANNEL4 + \ PWM_TIM1_CHANNEL5 + PWM_TIM1_CHANNEL6) -#ifdef CONFIG_STM32H5_TIM2_CHANNEL1 +#ifdef CONFIG_STM32_TIM2_CHANNEL1 # define PWM_TIM2_CHANNEL1 1 #else # define PWM_TIM2_CHANNEL1 0 #endif -#ifdef CONFIG_STM32H5_TIM2_CHANNEL2 +#ifdef CONFIG_STM32_TIM2_CHANNEL2 # define PWM_TIM2_CHANNEL2 1 #else # define PWM_TIM2_CHANNEL2 0 #endif -#ifdef CONFIG_STM32H5_TIM2_CHANNEL3 +#ifdef CONFIG_STM32_TIM2_CHANNEL3 # define PWM_TIM2_CHANNEL3 1 #else # define PWM_TIM2_CHANNEL3 0 #endif -#ifdef CONFIG_STM32H5_TIM2_CHANNEL4 +#ifdef CONFIG_STM32_TIM2_CHANNEL4 # define PWM_TIM2_CHANNEL4 1 #else # define PWM_TIM2_CHANNEL4 0 @@ -166,22 +166,22 @@ #define PWM_TIM2_NCHANNELS (PWM_TIM2_CHANNEL1 + PWM_TIM2_CHANNEL2 + \ PWM_TIM2_CHANNEL3 + PWM_TIM2_CHANNEL4) -#ifdef CONFIG_STM32H5_TIM3_CHANNEL1 +#ifdef CONFIG_STM32_TIM3_CHANNEL1 # define PWM_TIM3_CHANNEL1 1 #else # define PWM_TIM3_CHANNEL1 0 #endif -#ifdef CONFIG_STM32H5_TIM3_CHANNEL2 +#ifdef CONFIG_STM32_TIM3_CHANNEL2 # define PWM_TIM3_CHANNEL2 1 #else # define PWM_TIM3_CHANNEL2 0 #endif -#ifdef CONFIG_STM32H5_TIM3_CHANNEL3 +#ifdef CONFIG_STM32_TIM3_CHANNEL3 # define PWM_TIM3_CHANNEL3 1 #else # define PWM_TIM3_CHANNEL3 0 #endif -#ifdef CONFIG_STM32H5_TIM3_CHANNEL4 +#ifdef CONFIG_STM32_TIM3_CHANNEL4 # define PWM_TIM3_CHANNEL4 1 #else # define PWM_TIM3_CHANNEL4 0 @@ -189,22 +189,22 @@ #define PWM_TIM3_NCHANNELS (PWM_TIM3_CHANNEL1 + PWM_TIM3_CHANNEL2 + \ PWM_TIM3_CHANNEL3 + PWM_TIM3_CHANNEL4) -#ifdef CONFIG_STM32H5_TIM4_CHANNEL1 +#ifdef CONFIG_STM32_TIM4_CHANNEL1 # define PWM_TIM4_CHANNEL1 1 #else # define PWM_TIM4_CHANNEL1 0 #endif -#ifdef CONFIG_STM32H5_TIM4_CHANNEL2 +#ifdef CONFIG_STM32_TIM4_CHANNEL2 # define PWM_TIM4_CHANNEL2 1 #else # define PWM_TIM4_CHANNEL2 0 #endif -#ifdef CONFIG_STM32H5_TIM4_CHANNEL3 +#ifdef CONFIG_STM32_TIM4_CHANNEL3 # define PWM_TIM4_CHANNEL3 1 #else # define PWM_TIM4_CHANNEL3 0 #endif -#ifdef CONFIG_STM32H5_TIM4_CHANNEL4 +#ifdef CONFIG_STM32_TIM4_CHANNEL4 # define PWM_TIM4_CHANNEL4 1 #else # define PWM_TIM4_CHANNEL4 0 @@ -212,22 +212,22 @@ #define PWM_TIM4_NCHANNELS (PWM_TIM4_CHANNEL1 + PWM_TIM4_CHANNEL2 + \ PWM_TIM4_CHANNEL3 + PWM_TIM4_CHANNEL4) -#ifdef CONFIG_STM32H5_TIM5_CHANNEL1 +#ifdef CONFIG_STM32_TIM5_CHANNEL1 # define PWM_TIM5_CHANNEL1 1 #else # define PWM_TIM5_CHANNEL1 0 #endif -#ifdef CONFIG_STM32H5_TIM5_CHANNEL2 +#ifdef CONFIG_STM32_TIM5_CHANNEL2 # define PWM_TIM5_CHANNEL2 1 #else # define PWM_TIM5_CHANNEL2 0 #endif -#ifdef CONFIG_STM32H5_TIM5_CHANNEL3 +#ifdef CONFIG_STM32_TIM5_CHANNEL3 # define PWM_TIM5_CHANNEL3 1 #else # define PWM_TIM5_CHANNEL3 0 #endif -#ifdef CONFIG_STM32H5_TIM5_CHANNEL4 +#ifdef CONFIG_STM32_TIM5_CHANNEL4 # define PWM_TIM5_CHANNEL4 1 #else # define PWM_TIM5_CHANNEL4 0 @@ -235,32 +235,32 @@ #define PWM_TIM5_NCHANNELS (PWM_TIM5_CHANNEL1 + PWM_TIM5_CHANNEL2 + \ PWM_TIM5_CHANNEL3 + PWM_TIM5_CHANNEL4) -#ifdef CONFIG_STM32H5_TIM8_CHANNEL1 +#ifdef CONFIG_STM32_TIM8_CHANNEL1 # define PWM_TIM8_CHANNEL1 1 #else # define PWM_TIM8_CHANNEL1 0 #endif -#ifdef CONFIG_STM32H5_TIM8_CHANNEL2 +#ifdef CONFIG_STM32_TIM8_CHANNEL2 # define PWM_TIM8_CHANNEL2 1 #else # define PWM_TIM8_CHANNEL2 0 #endif -#ifdef CONFIG_STM32H5_TIM8_CHANNEL3 +#ifdef CONFIG_STM32_TIM8_CHANNEL3 # define PWM_TIM8_CHANNEL3 1 #else # define PWM_TIM8_CHANNEL3 0 #endif -#ifdef CONFIG_STM32H5_TIM8_CHANNEL4 +#ifdef CONFIG_STM32_TIM8_CHANNEL4 # define PWM_TIM8_CHANNEL4 1 #else # define PWM_TIM8_CHANNEL4 0 #endif -#ifdef CONFIG_STM32H5_TIM8_CHANNEL5 +#ifdef CONFIG_STM32_TIM8_CHANNEL5 # define PWM_TIM8_CHANNEL5 1 #else # define PWM_TIM8_CHANNEL5 0 #endif -#ifdef CONFIG_STM32H5_TIM8_CHANNEL6 +#ifdef CONFIG_STM32_TIM8_CHANNEL6 # define PWM_TIM8_CHANNEL6 1 #else # define PWM_TIM8_CHANNEL6 0 @@ -269,64 +269,64 @@ PWM_TIM8_CHANNEL3 + PWM_TIM8_CHANNEL4 + \ PWM_TIM8_CHANNEL5 + PWM_TIM8_CHANNEL6) -#ifdef CONFIG_STM32H5_TIM12_CHANNEL1 +#ifdef CONFIG_STM32_TIM12_CHANNEL1 # define PWM_TIM12_CHANNEL1 1 #else # define PWM_TIM12_CHANNEL1 0 #endif -#ifdef CONFIG_STM32H5_TIM12_CHANNEL2 +#ifdef CONFIG_STM32_TIM12_CHANNEL2 # define PWM_TIM12_CHANNEL2 1 #else # define PWM_TIM12_CHANNEL2 0 #endif #define PWM_TIM12_NCHANNELS (PWM_TIM12_CHANNEL1 + PWM_TIM12_CHANNEL2) -#ifdef CONFIG_STM32H5_TIM13_CHANNEL1 +#ifdef CONFIG_STM32_TIM13_CHANNEL1 # define PWM_TIM13_CHANNEL1 1 #else # define PWM_TIM13_CHANNEL1 0 #endif #define PWM_TIM13_NCHANNELS (PWM_TIM13_CHANNEL1) -#ifdef CONFIG_STM32H5_TIM14_CHANNEL1 +#ifdef CONFIG_STM32_TIM14_CHANNEL1 # define PWM_TIM14_CHANNEL1 1 #else # define PWM_TIM14_CHANNEL1 0 #endif #define PWM_TIM14_NCHANNELS (PWM_TIM14_CHANNEL1) -#ifdef CONFIG_STM32H5_TIM15_CHANNEL1 +#ifdef CONFIG_STM32_TIM15_CHANNEL1 # define PWM_TIM15_CHANNEL1 1 #else # define PWM_TIM15_CHANNEL1 0 #endif -#ifdef CONFIG_STM32H5_TIM15_CHANNEL2 +#ifdef CONFIG_STM32_TIM15_CHANNEL2 # define PWM_TIM15_CHANNEL2 1 #else # define PWM_TIM15_CHANNEL2 0 #endif #define PWM_TIM15_NCHANNELS (PWM_TIM15_CHANNEL1 + PWM_TIM15_CHANNEL2) -#ifdef CONFIG_STM32H5_TIM16_CHANNEL1 +#ifdef CONFIG_STM32_TIM16_CHANNEL1 # define PWM_TIM16_CHANNEL1 1 #else # define PWM_TIM16_CHANNEL1 0 #endif #define PWM_TIM16_NCHANNELS PWM_TIM16_CHANNEL1 -#ifdef CONFIG_STM32H5_TIM17_CHANNEL1 +#ifdef CONFIG_STM32_TIM17_CHANNEL1 # define PWM_TIM17_CHANNEL1 1 #else # define PWM_TIM17_CHANNEL1 0 #endif #define PWM_TIM17_NCHANNELS PWM_TIM17_CHANNEL1 -#else /* !CONFIG_STM32H5_PWM_MULTICHAN */ +#else /* !CONFIG_STM32_PWM_MULTICHAN */ /* For each timer that is enabled for PWM usage, we need the following * additional configuration settings: * - * CONFIG_STM32H5_TIMx_CHANNEL - Specifies the timer output channel + * CONFIG_STM32_TIMx_CHANNEL - Specifies the timer output channel * {1,..,4} * PWM_TIMx_CHn - One of the values defined in chip/stm32*_pinmap.h. * In the case where there are multiple pin selections, the correct @@ -338,425 +338,425 @@ * is not supported by this driver: Only one output channel per timer. */ -#ifdef CONFIG_STM32H5_TIM1_PWM -# if !defined(CONFIG_STM32H5_TIM1_CHANNEL) -# error "CONFIG_STM32H5_TIM1_CHANNEL must be provided" -# elif CONFIG_STM32H5_TIM1_CHANNEL == 1 -# define CONFIG_STM32H5_TIM1_CHANNEL1 1 -# define CONFIG_STM32H5_TIM1_CH1MODE CONFIG_STM32H5_TIM1_CHMODE -# elif CONFIG_STM32H5_TIM1_CHANNEL == 2 -# define CONFIG_STM32H5_TIM1_CHANNEL2 1 -# define CONFIG_STM32H5_TIM1_CH2MODE CONFIG_STM32H5_TIM1_CHMODE -# elif CONFIG_STM32H5_TIM1_CHANNEL == 3 -# define CONFIG_STM32H5_TIM1_CHANNEL3 1 -# define CONFIG_STM32H5_TIM1_CH3MODE CONFIG_STM32H5_TIM1_CHMODE -# elif CONFIG_STM32H5_TIM1_CHANNEL == 4 -# define CONFIG_STM32H5_TIM1_CHANNEL4 1 -# define CONFIG_STM32H5_TIM1_CH4MODE CONFIG_STM32H5_TIM1_CHMODE +#ifdef CONFIG_STM32_TIM1_PWM +# if !defined(CONFIG_STM32_TIM1_CHANNEL) +# error "CONFIG_STM32_TIM1_CHANNEL must be provided" +# elif CONFIG_STM32_TIM1_CHANNEL == 1 +# define CONFIG_STM32_TIM1_CHANNEL1 1 +# define CONFIG_STM32_TIM1_CH1MODE CONFIG_STM32_TIM1_CHMODE +# elif CONFIG_STM32_TIM1_CHANNEL == 2 +# define CONFIG_STM32_TIM1_CHANNEL2 1 +# define CONFIG_STM32_TIM1_CH2MODE CONFIG_STM32_TIM1_CHMODE +# elif CONFIG_STM32_TIM1_CHANNEL == 3 +# define CONFIG_STM32_TIM1_CHANNEL3 1 +# define CONFIG_STM32_TIM1_CH3MODE CONFIG_STM32_TIM1_CHMODE +# elif CONFIG_STM32_TIM1_CHANNEL == 4 +# define CONFIG_STM32_TIM1_CHANNEL4 1 +# define CONFIG_STM32_TIM1_CH4MODE CONFIG_STM32_TIM1_CHMODE # else -# error "Unsupported value of CONFIG_STM32H5_TIM1_CHANNEL" +# error "Unsupported value of CONFIG_STM32_TIM1_CHANNEL" # endif # define PWM_TIM1_NCHANNELS 1 #endif -#ifdef CONFIG_STM32H5_TIM2_PWM -# if !defined(CONFIG_STM32H5_TIM2_CHANNEL) -# error "CONFIG_STM32H5_TIM2_CHANNEL must be provided" -# elif CONFIG_STM32H5_TIM2_CHANNEL == 1 -# define CONFIG_STM32H5_TIM2_CHANNEL1 1 -# define CONFIG_STM32H5_TIM2_CH1MODE CONFIG_STM32H5_TIM2_CHMODE -# elif CONFIG_STM32H5_TIM2_CHANNEL == 2 -# define CONFIG_STM32H5_TIM2_CHANNEL2 1 -# define CONFIG_STM32H5_TIM2_CH2MODE CONFIG_STM32H5_TIM2_CHMODE -# elif CONFIG_STM32H5_TIM2_CHANNEL == 3 -# define CONFIG_STM32H5_TIM2_CHANNEL3 1 -# define CONFIG_STM32H5_TIM2_CH3MODE CONFIG_STM32H5_TIM2_CHMODE -# elif CONFIG_STM32H5_TIM2_CHANNEL == 4 -# define CONFIG_STM32H5_TIM2_CHANNEL4 1 -# define CONFIG_STM32H5_TIM2_CH4MODE CONFIG_STM32H5_TIM2_CHMODE +#ifdef CONFIG_STM32_TIM2_PWM +# if !defined(CONFIG_STM32_TIM2_CHANNEL) +# error "CONFIG_STM32_TIM2_CHANNEL must be provided" +# elif CONFIG_STM32_TIM2_CHANNEL == 1 +# define CONFIG_STM32_TIM2_CHANNEL1 1 +# define CONFIG_STM32_TIM2_CH1MODE CONFIG_STM32_TIM2_CHMODE +# elif CONFIG_STM32_TIM2_CHANNEL == 2 +# define CONFIG_STM32_TIM2_CHANNEL2 1 +# define CONFIG_STM32_TIM2_CH2MODE CONFIG_STM32_TIM2_CHMODE +# elif CONFIG_STM32_TIM2_CHANNEL == 3 +# define CONFIG_STM32_TIM2_CHANNEL3 1 +# define CONFIG_STM32_TIM2_CH3MODE CONFIG_STM32_TIM2_CHMODE +# elif CONFIG_STM32_TIM2_CHANNEL == 4 +# define CONFIG_STM32_TIM2_CHANNEL4 1 +# define CONFIG_STM32_TIM2_CH4MODE CONFIG_STM32_TIM2_CHMODE # else -# error "Unsupported value of CONFIG_STM32H5_TIM2_CHANNEL" +# error "Unsupported value of CONFIG_STM32_TIM2_CHANNEL" # endif # define PWM_TIM2_NCHANNELS 1 #endif -#ifdef CONFIG_STM32H5_TIM3_PWM -# if !defined(CONFIG_STM32H5_TIM3_CHANNEL) -# error "CONFIG_STM32H5_TIM3_CHANNEL must be provided" -# elif CONFIG_STM32H5_TIM3_CHANNEL == 1 -# define CONFIG_STM32H5_TIM3_CHANNEL1 1 -# define CONFIG_STM32H5_TIM3_CH1MODE CONFIG_STM32H5_TIM3_CHMODE -# elif CONFIG_STM32H5_TIM3_CHANNEL == 2 -# define CONFIG_STM32H5_TIM3_CHANNEL2 1 -# define CONFIG_STM32H5_TIM3_CH2MODE CONFIG_STM32H5_TIM3_CHMODE -# elif CONFIG_STM32H5_TIM3_CHANNEL == 3 -# define CONFIG_STM32H5_TIM3_CHANNEL3 1 -# define CONFIG_STM32H5_TIM3_CH3MODE CONFIG_STM32H5_TIM3_CHMODE -# elif CONFIG_STM32H5_TIM3_CHANNEL == 4 -# define CONFIG_STM32H5_TIM3_CHANNEL4 1 -# define CONFIG_STM32H5_TIM3_CH4MODE CONFIG_STM32H5_TIM3_CHMODE +#ifdef CONFIG_STM32_TIM3_PWM +# if !defined(CONFIG_STM32_TIM3_CHANNEL) +# error "CONFIG_STM32_TIM3_CHANNEL must be provided" +# elif CONFIG_STM32_TIM3_CHANNEL == 1 +# define CONFIG_STM32_TIM3_CHANNEL1 1 +# define CONFIG_STM32_TIM3_CH1MODE CONFIG_STM32_TIM3_CHMODE +# elif CONFIG_STM32_TIM3_CHANNEL == 2 +# define CONFIG_STM32_TIM3_CHANNEL2 1 +# define CONFIG_STM32_TIM3_CH2MODE CONFIG_STM32_TIM3_CHMODE +# elif CONFIG_STM32_TIM3_CHANNEL == 3 +# define CONFIG_STM32_TIM3_CHANNEL3 1 +# define CONFIG_STM32_TIM3_CH3MODE CONFIG_STM32_TIM3_CHMODE +# elif CONFIG_STM32_TIM3_CHANNEL == 4 +# define CONFIG_STM32_TIM3_CHANNEL4 1 +# define CONFIG_STM32_TIM3_CH4MODE CONFIG_STM32_TIM3_CHMODE # else -# error "Unsupported value of CONFIG_STM32H5_TIM3_CHANNEL" +# error "Unsupported value of CONFIG_STM32_TIM3_CHANNEL" # endif # define PWM_TIM3_NCHANNELS 1 #endif -#ifdef CONFIG_STM32H5_TIM4_PWM -# if !defined(CONFIG_STM32H5_TIM4_CHANNEL) -# error "CONFIG_STM32H5_TIM4_CHANNEL must be provided" -# elif CONFIG_STM32H5_TIM4_CHANNEL == 1 -# define CONFIG_STM32H5_TIM4_CHANNEL1 1 -# define CONFIG_STM32H5_TIM4_CH1MODE CONFIG_STM32H5_TIM4_CHMODE -# elif CONFIG_STM32H5_TIM4_CHANNEL == 2 -# define CONFIG_STM32H5_TIM4_CHANNEL2 1 -# define CONFIG_STM32H5_TIM4_CH2MODE CONFIG_STM32H5_TIM4_CHMODE -# elif CONFIG_STM32H5_TIM4_CHANNEL == 3 -# define CONFIG_STM32H5_TIM4_CHANNEL3 1 -# define CONFIG_STM32H5_TIM4_CH3MODE CONFIG_STM32H5_TIM4_CHMODE -# elif CONFIG_STM32H5_TIM4_CHANNEL == 4 -# define CONFIG_STM32H5_TIM4_CHANNEL4 1 -# define CONFIG_STM32H5_TIM4_CH4MODE CONFIG_STM32H5_TIM4_CHMODE +#ifdef CONFIG_STM32_TIM4_PWM +# if !defined(CONFIG_STM32_TIM4_CHANNEL) +# error "CONFIG_STM32_TIM4_CHANNEL must be provided" +# elif CONFIG_STM32_TIM4_CHANNEL == 1 +# define CONFIG_STM32_TIM4_CHANNEL1 1 +# define CONFIG_STM32_TIM4_CH1MODE CONFIG_STM32_TIM4_CHMODE +# elif CONFIG_STM32_TIM4_CHANNEL == 2 +# define CONFIG_STM32_TIM4_CHANNEL2 1 +# define CONFIG_STM32_TIM4_CH2MODE CONFIG_STM32_TIM4_CHMODE +# elif CONFIG_STM32_TIM4_CHANNEL == 3 +# define CONFIG_STM32_TIM4_CHANNEL3 1 +# define CONFIG_STM32_TIM4_CH3MODE CONFIG_STM32_TIM4_CHMODE +# elif CONFIG_STM32_TIM4_CHANNEL == 4 +# define CONFIG_STM32_TIM4_CHANNEL4 1 +# define CONFIG_STM32_TIM4_CH4MODE CONFIG_STM32_TIM4_CHMODE # else -# error "Unsupported value of CONFIG_STM32H5_TIM4_CHANNEL" +# error "Unsupported value of CONFIG_STM32_TIM4_CHANNEL" # endif # define PWM_TIM4_NCHANNELS 1 #endif -#ifdef CONFIG_STM32H5_TIM5_PWM -# if !defined(CONFIG_STM32H5_TIM5_CHANNEL) -# error "CONFIG_STM32H5_TIM5_CHANNEL must be provided" -# elif CONFIG_STM32H5_TIM5_CHANNEL == 1 -# define CONFIG_STM32H5_TIM5_CHANNEL1 1 -# define CONFIG_STM32H5_TIM5_CH1MODE CONFIG_STM32H5_TIM5_CHMODE -# elif CONFIG_STM32H5_TIM5_CHANNEL == 2 -# define CONFIG_STM32H5_TIM5_CHANNEL2 1 -# define CONFIG_STM32H5_TIM5_CH2MODE CONFIG_STM32H5_TIM5_CHMODE -# elif CONFIG_STM32H5_TIM5_CHANNEL == 3 -# define CONFIG_STM32H5_TIM5_CHANNEL3 1 -# define CONFIG_STM32H5_TIM5_CH3MODE CONFIG_STM32H5_TIM5_CHMODE -# elif CONFIG_STM32H5_TIM5_CHANNEL == 4 -# define CONFIG_STM32H5_TIM5_CHANNEL4 1 -# define CONFIG_STM32H5_TIM5_CH4MODE CONFIG_STM32H5_TIM5_CHMODE +#ifdef CONFIG_STM32_TIM5_PWM +# if !defined(CONFIG_STM32_TIM5_CHANNEL) +# error "CONFIG_STM32_TIM5_CHANNEL must be provided" +# elif CONFIG_STM32_TIM5_CHANNEL == 1 +# define CONFIG_STM32_TIM5_CHANNEL1 1 +# define CONFIG_STM32_TIM5_CH1MODE CONFIG_STM32_TIM5_CHMODE +# elif CONFIG_STM32_TIM5_CHANNEL == 2 +# define CONFIG_STM32_TIM5_CHANNEL2 1 +# define CONFIG_STM32_TIM5_CH2MODE CONFIG_STM32_TIM5_CHMODE +# elif CONFIG_STM32_TIM5_CHANNEL == 3 +# define CONFIG_STM32_TIM5_CHANNEL3 1 +# define CONFIG_STM32_TIM5_CH3MODE CONFIG_STM32_TIM5_CHMODE +# elif CONFIG_STM32_TIM5_CHANNEL == 4 +# define CONFIG_STM32_TIM5_CHANNEL4 1 +# define CONFIG_STM32_TIM5_CH4MODE CONFIG_STM32_TIM5_CHMODE # else -# error "Unsupported value of CONFIG_STM32H5_TIM5_CHANNEL" +# error "Unsupported value of CONFIG_STM32_TIM5_CHANNEL" # endif # define PWM_TIM5_NCHANNELS 1 #endif -#ifdef CONFIG_STM32H5_TIM8_PWM -# if !defined(CONFIG_STM32H5_TIM8_CHANNEL) -# error "CONFIG_STM32H5_TIM8_CHANNEL must be provided" -# elif CONFIG_STM32H5_TIM8_CHANNEL == 1 -# define CONFIG_STM32H5_TIM8_CHANNEL1 1 -# define CONFIG_STM32H5_TIM8_CH1MODE CONFIG_STM32H5_TIM8_CHMODE -# elif CONFIG_STM32H5_TIM8_CHANNEL == 2 -# define CONFIG_STM32H5_TIM8_CHANNEL2 1 -# define CONFIG_STM32H5_TIM8_CH2MODE CONFIG_STM32H5_TIM8_CHMODE -# elif CONFIG_STM32H5_TIM8_CHANNEL == 3 -# define CONFIG_STM32H5_TIM8_CHANNEL3 1 -# define CONFIG_STM32H5_TIM8_CH3MODE CONFIG_STM32H5_TIM8_CHMODE -# elif CONFIG_STM32H5_TIM8_CHANNEL == 4 -# define CONFIG_STM32H5_TIM8_CHANNEL4 1 -# define CONFIG_STM32H5_TIM8_CH4MODE CONFIG_STM32H5_TIM8_CHMODE +#ifdef CONFIG_STM32_TIM8_PWM +# if !defined(CONFIG_STM32_TIM8_CHANNEL) +# error "CONFIG_STM32_TIM8_CHANNEL must be provided" +# elif CONFIG_STM32_TIM8_CHANNEL == 1 +# define CONFIG_STM32_TIM8_CHANNEL1 1 +# define CONFIG_STM32_TIM8_CH1MODE CONFIG_STM32_TIM8_CHMODE +# elif CONFIG_STM32_TIM8_CHANNEL == 2 +# define CONFIG_STM32_TIM8_CHANNEL2 1 +# define CONFIG_STM32_TIM8_CH2MODE CONFIG_STM32_TIM8_CHMODE +# elif CONFIG_STM32_TIM8_CHANNEL == 3 +# define CONFIG_STM32_TIM8_CHANNEL3 1 +# define CONFIG_STM32_TIM8_CH3MODE CONFIG_STM32_TIM8_CHMODE +# elif CONFIG_STM32_TIM8_CHANNEL == 4 +# define CONFIG_STM32_TIM8_CHANNEL4 1 +# define CONFIG_STM32_TIM8_CH4MODE CONFIG_STM32_TIM8_CHMODE # else -# error "Unsupported value of CONFIG_STM32H5_TIM8_CHANNEL" +# error "Unsupported value of CONFIG_STM32_TIM8_CHANNEL" # endif # define PWM_TIM8_NCHANNELS 1 #endif -#ifdef CONFIG_STM32H5_TIM12_PWM -# if !defined(CONFIG_STM32H5_TIM12_CHANNEL) -# error "CONFIG_STM32H5_TIM12_CHANNEL must be provided" -# elif CONFIG_STM32H5_TIM12_CHANNEL == 1 -# define CONFIG_STM32H5_TIM12_CHANNEL1 1 -# define CONFIG_STM32H5_TIM12_CH1MODE CONFIG_STM32H5_TIM12_CHMODE -# elif CONFIG_STM32H5_TIM12_CHANNEL == 2 -# define CONFIG_STM32H5_TIM12_CHANNEL2 1 -# define CONFIG_STM32H5_TIM12_CH2MODE CONFIG_STM32H5_TIM12_CHMODE +#ifdef CONFIG_STM32_TIM12_PWM +# if !defined(CONFIG_STM32_TIM12_CHANNEL) +# error "CONFIG_STM32_TIM12_CHANNEL must be provided" +# elif CONFIG_STM32_TIM12_CHANNEL == 1 +# define CONFIG_STM32_TIM12_CHANNEL1 1 +# define CONFIG_STM32_TIM12_CH1MODE CONFIG_STM32_TIM12_CHMODE +# elif CONFIG_STM32_TIM12_CHANNEL == 2 +# define CONFIG_STM32_TIM12_CHANNEL2 1 +# define CONFIG_STM32_TIM12_CH2MODE CONFIG_STM32_TIM12_CHMODE # else -# error "Unsupported value of CONFIG_STM32H5_TIM12_CHANNEL" +# error "Unsupported value of CONFIG_STM32_TIM12_CHANNEL" # endif # define PWM_TIM12_NCHANNELS 1 #endif -#ifdef CONFIG_STM32H5_TIM13_PWM -# if !defined(CONFIG_STM32H5_TIM13_CHANNEL) -# error "CONFIG_STM32H5_TIM13_CHANNEL must be provided" -# elif CONFIG_STM32H5_TIM13_CHANNEL == 1 -# define CONFIG_STM32H5_TIM13_CHANNEL1 1 -# define CONFIG_STM32H5_TIM13_CH1MODE CONFIG_STM32H5_TIM13_CHMODE +#ifdef CONFIG_STM32_TIM13_PWM +# if !defined(CONFIG_STM32_TIM13_CHANNEL) +# error "CONFIG_STM32_TIM13_CHANNEL must be provided" +# elif CONFIG_STM32_TIM13_CHANNEL == 1 +# define CONFIG_STM32_TIM13_CHANNEL1 1 +# define CONFIG_STM32_TIM13_CH1MODE CONFIG_STM32_TIM13_CHMODE # else -# error "Unsupported value of CONFIG_STM32H5_TIM13_CHANNEL" +# error "Unsupported value of CONFIG_STM32_TIM13_CHANNEL" # endif # define PWM_TIM13_NCHANNELS 1 #endif -#ifdef CONFIG_STM32H5_TIM14_PWM -# if !defined(CONFIG_STM32H5_TIM14_CHANNEL) -# error "CONFIG_STM32H5_TIM14_CHANNEL must be provided" -# elif CONFIG_STM32H5_TIM14_CHANNEL == 1 -# define CONFIG_STM32H5_TIM14_CHANNEL1 1 -# define CONFIG_STM32H5_TIM14_CH1MODE CONFIG_STM32H5_TIM14_CHMODE +#ifdef CONFIG_STM32_TIM14_PWM +# if !defined(CONFIG_STM32_TIM14_CHANNEL) +# error "CONFIG_STM32_TIM14_CHANNEL must be provided" +# elif CONFIG_STM32_TIM14_CHANNEL == 1 +# define CONFIG_STM32_TIM14_CHANNEL1 1 +# define CONFIG_STM32_TIM14_CH1MODE CONFIG_STM32_TIM14_CHMODE # else -# error "Unsupported value of CONFIG_STM32H5_TIM14_CHANNEL" +# error "Unsupported value of CONFIG_STM32_TIM14_CHANNEL" # endif # define PWM_TIM14_NCHANNELS 1 #endif -#ifdef CONFIG_STM32H5_TIM15_PWM -# if !defined(CONFIG_STM32H5_TIM15_CHANNEL) -# error "CONFIG_STM32H5_TIM15_CHANNEL must be provided" -# elif CONFIG_STM32H5_TIM15_CHANNEL == 1 -# define CONFIG_STM32H5_TIM15_CHANNEL1 1 -# define CONFIG_STM32H5_TIM15_CH1MODE CONFIG_STM32H5_TIM15_CHMODE -# elif CONFIG_STM32H5_TIM15_CHANNEL == 2 -# define CONFIG_STM32H5_TIM15_CHANNEL2 1 -# define CONFIG_STM32H5_TIM15_CH2MODE CONFIG_STM32H5_TIM15_CHMODE +#ifdef CONFIG_STM32_TIM15_PWM +# if !defined(CONFIG_STM32_TIM15_CHANNEL) +# error "CONFIG_STM32_TIM15_CHANNEL must be provided" +# elif CONFIG_STM32_TIM15_CHANNEL == 1 +# define CONFIG_STM32_TIM15_CHANNEL1 1 +# define CONFIG_STM32_TIM15_CH1MODE CONFIG_STM32_TIM15_CHMODE +# elif CONFIG_STM32_TIM15_CHANNEL == 2 +# define CONFIG_STM32_TIM15_CHANNEL2 1 +# define CONFIG_STM32_TIM15_CH2MODE CONFIG_STM32_TIM15_CHMODE # else -# error "Unsupported value of CONFIG_STM32H5_TIM15_CHANNEL" +# error "Unsupported value of CONFIG_STM32_TIM15_CHANNEL" # endif # define PWM_TIM15_NCHANNELS 1 #endif -#ifdef CONFIG_STM32H5_TIM16_PWM -# if !defined(CONFIG_STM32H5_TIM16_CHANNEL) -# error "CONFIG_STM32H5_TIM16_CHANNEL must be provided" -# elif CONFIG_STM32H5_TIM16_CHANNEL == 1 -# define CONFIG_STM32H5_TIM16_CHANNEL1 1 -# define CONFIG_STM32H5_TIM16_CH1MODE CONFIG_STM32H5_TIM16_CHMODE +#ifdef CONFIG_STM32_TIM16_PWM +# if !defined(CONFIG_STM32_TIM16_CHANNEL) +# error "CONFIG_STM32_TIM16_CHANNEL must be provided" +# elif CONFIG_STM32_TIM16_CHANNEL == 1 +# define CONFIG_STM32_TIM16_CHANNEL1 1 +# define CONFIG_STM32_TIM16_CH1MODE CONFIG_STM32_TIM16_CHMODE # else -# error "Unsupported value of CONFIG_STM32H5_TIM16_CHANNEL" +# error "Unsupported value of CONFIG_STM32_TIM16_CHANNEL" # endif # define PWM_TIM16_NCHANNELS 1 #endif -#ifdef CONFIG_STM32H5_TIM17_PWM -# if !defined(CONFIG_STM32H5_TIM17_CHANNEL) -# error "CONFIG_STM32H5_TIM17_CHANNEL must be provided" -# elif CONFIG_STM32H5_TIM17_CHANNEL == 1 -# define CONFIG_STM32H5_TIM17_CHANNEL1 1 -# define CONFIG_STM32H5_TIM17_CH1MODE CONFIG_STM32H5_TIM17_CHMODE +#ifdef CONFIG_STM32_TIM17_PWM +# if !defined(CONFIG_STM32_TIM17_CHANNEL) +# error "CONFIG_STM32_TIM17_CHANNEL must be provided" +# elif CONFIG_STM32_TIM17_CHANNEL == 1 +# define CONFIG_STM32_TIM17_CHANNEL1 1 +# define CONFIG_STM32_TIM17_CH1MODE CONFIG_STM32_TIM17_CHMODE # else -# error "Unsupported value of CONFIG_STM32H5_TIM17_CHANNEL" +# error "Unsupported value of CONFIG_STM32_TIM17_CHANNEL" # endif # define PWM_TIM17_NCHANNELS 1 #endif -#endif /* CONFIG_STM32H5_PWM_MULTICHAN */ +#endif /* CONFIG_STM32_PWM_MULTICHAN */ -#ifdef CONFIG_STM32H5_TIM1_CH1OUT +#ifdef CONFIG_STM32_TIM1_CH1OUT # define PWM_TIM1_CH1CFG GPIO_TIM1_CH1OUT #else # define PWM_TIM1_CH1CFG 0 #endif -#ifdef CONFIG_STM32H5_TIM1_CH1NOUT +#ifdef CONFIG_STM32_TIM1_CH1NOUT # define PWM_TIM1_CH1NCFG GPIO_TIM1_CH1NOUT #else # define PWM_TIM1_CH1NCFG 0 #endif -#ifdef CONFIG_STM32H5_TIM1_CH2OUT +#ifdef CONFIG_STM32_TIM1_CH2OUT # define PWM_TIM1_CH2CFG GPIO_TIM1_CH2OUT #else # define PWM_TIM1_CH2CFG 0 #endif -#ifdef CONFIG_STM32H5_TIM1_CH2NOUT +#ifdef CONFIG_STM32_TIM1_CH2NOUT # define PWM_TIM1_CH2NCFG GPIO_TIM1_CH2NOUT #else # define PWM_TIM1_CH2NCFG 0 #endif -#ifdef CONFIG_STM32H5_TIM1_CH3OUT +#ifdef CONFIG_STM32_TIM1_CH3OUT # define PWM_TIM1_CH3CFG GPIO_TIM1_CH3OUT #else # define PWM_TIM1_CH3CFG 0 #endif -#ifdef CONFIG_STM32H5_TIM1_CH3NOUT +#ifdef CONFIG_STM32_TIM1_CH3NOUT # define PWM_TIM1_CH3NCFG GPIO_TIM1_CH3NOUT #else # define PWM_TIM1_CH3NCFG 0 #endif -#ifdef CONFIG_STM32H5_TIM1_CH4OUT +#ifdef CONFIG_STM32_TIM1_CH4OUT # define PWM_TIM1_CH4CFG GPIO_TIM1_CH4OUT #else # define PWM_TIM1_CH4CFG 0 #endif -#ifdef CONFIG_STM32H5_TIM2_CH1OUT +#ifdef CONFIG_STM32_TIM2_CH1OUT # define PWM_TIM2_CH1CFG GPIO_TIM2_CH1OUT #else # define PWM_TIM2_CH1CFG 0 #endif -#ifdef CONFIG_STM32H5_TIM2_CH2OUT +#ifdef CONFIG_STM32_TIM2_CH2OUT # define PWM_TIM2_CH2CFG GPIO_TIM2_CH2OUT #else # define PWM_TIM2_CH2CFG 0 #endif -#ifdef CONFIG_STM32H5_TIM2_CH3OUT +#ifdef CONFIG_STM32_TIM2_CH3OUT # define PWM_TIM2_CH3CFG GPIO_TIM2_CH3OUT #else # define PWM_TIM2_CH3CFG 0 #endif -#ifdef CONFIG_STM32H5_TIM2_CH4OUT +#ifdef CONFIG_STM32_TIM2_CH4OUT # define PWM_TIM2_CH4CFG GPIO_TIM2_CH4OUT #else # define PWM_TIM2_CH4CFG 0 #endif -#ifdef CONFIG_STM32H5_TIM3_CH1OUT +#ifdef CONFIG_STM32_TIM3_CH1OUT # define PWM_TIM3_CH1CFG GPIO_TIM3_CH1OUT #else # define PWM_TIM3_CH1CFG 0 #endif -#ifdef CONFIG_STM32H5_TIM3_CH2OUT +#ifdef CONFIG_STM32_TIM3_CH2OUT # define PWM_TIM3_CH2CFG GPIO_TIM3_CH2OUT #else # define PWM_TIM3_CH2CFG 0 #endif -#ifdef CONFIG_STM32H5_TIM3_CH3OUT +#ifdef CONFIG_STM32_TIM3_CH3OUT # define PWM_TIM3_CH3CFG GPIO_TIM3_CH3OUT #else # define PWM_TIM3_CH3CFG 0 #endif -#ifdef CONFIG_STM32H5_TIM3_CH4OUT +#ifdef CONFIG_STM32_TIM3_CH4OUT # define PWM_TIM3_CH4CFG GPIO_TIM3_CH4OUT #else # define PWM_TIM3_CH4CFG 0 #endif -#ifdef CONFIG_STM32H5_TIM4_CH1OUT +#ifdef CONFIG_STM32_TIM4_CH1OUT # define PWM_TIM4_CH1CFG GPIO_TIM4_CH1OUT #else # define PWM_TIM4_CH1CFG 0 #endif -#ifdef CONFIG_STM32H5_TIM4_CH2OUT +#ifdef CONFIG_STM32_TIM4_CH2OUT # define PWM_TIM4_CH2CFG GPIO_TIM4_CH2OUT #else # define PWM_TIM4_CH2CFG 0 #endif -#ifdef CONFIG_STM32H5_TIM4_CH3OUT +#ifdef CONFIG_STM32_TIM4_CH3OUT # define PWM_TIM4_CH3CFG GPIO_TIM4_CH3OUT #else # define PWM_TIM4_CH3CFG 0 #endif -#ifdef CONFIG_STM32H5_TIM4_CH4OUT +#ifdef CONFIG_STM32_TIM4_CH4OUT # define PWM_TIM4_CH4CFG GPIO_TIM4_CH4OUT #else # define PWM_TIM4_CH4CFG 0 #endif -#ifdef CONFIG_STM32H5_TIM5_CH1OUT +#ifdef CONFIG_STM32_TIM5_CH1OUT # define PWM_TIM5_CH1CFG GPIO_TIM5_CH1OUT #else # define PWM_TIM5_CH1CFG 0 #endif -#ifdef CONFIG_STM32H5_TIM5_CH2OUT +#ifdef CONFIG_STM32_TIM5_CH2OUT # define PWM_TIM5_CH2CFG GPIO_TIM5_CH2OUT #else # define PWM_TIM5_CH2CFG 0 #endif -#ifdef CONFIG_STM32H5_TIM5_CH3OUT +#ifdef CONFIG_STM32_TIM5_CH3OUT # define PWM_TIM5_CH3CFG GPIO_TIM5_CH3OUT #else # define PWM_TIM5_CH3CFG 0 #endif -#ifdef CONFIG_STM32H5_TIM5_CH4OUT +#ifdef CONFIG_STM32_TIM5_CH4OUT # define PWM_TIM5_CH4CFG GPIO_TIM5_CH4OUT #else # define PWM_TIM5_CH4CFG 0 #endif -#ifdef CONFIG_STM32H5_TIM8_CH1OUT +#ifdef CONFIG_STM32_TIM8_CH1OUT # define PWM_TIM8_CH1CFG GPIO_TIM8_CH1OUT #else # define PWM_TIM8_CH1CFG 0 #endif -#ifdef CONFIG_STM32H5_TIM8_CH1NOUT +#ifdef CONFIG_STM32_TIM8_CH1NOUT # define PWM_TIM8_CH1NCFG GPIO_TIM8_CH1NOUT #else # define PWM_TIM8_CH1NCFG 0 #endif -#ifdef CONFIG_STM32H5_TIM8_CH2OUT +#ifdef CONFIG_STM32_TIM8_CH2OUT # define PWM_TIM8_CH2CFG GPIO_TIM8_CH2OUT #else # define PWM_TIM8_CH2CFG 0 #endif -#ifdef CONFIG_STM32H5_TIM8_CH2NOUT +#ifdef CONFIG_STM32_TIM8_CH2NOUT # define PWM_TIM8_CH2NCFG GPIO_TIM8_CH2NOUT #else # define PWM_TIM8_CH2NCFG 0 #endif -#ifdef CONFIG_STM32H5_TIM8_CH3OUT +#ifdef CONFIG_STM32_TIM8_CH3OUT # define PWM_TIM8_CH3CFG GPIO_TIM8_CH3OUT #else # define PWM_TIM8_CH3CFG 0 #endif -#ifdef CONFIG_STM32H5_TIM8_CH3NOUT +#ifdef CONFIG_STM32_TIM8_CH3NOUT # define PWM_TIM8_CH3NCFG GPIO_TIM8_CH3NOUT #else # define PWM_TIM8_CH3NCFG 0 #endif -#ifdef CONFIG_STM32H5_TIM8_CH4OUT +#ifdef CONFIG_STM32_TIM8_CH4OUT # define PWM_TIM8_CH4CFG GPIO_TIM8_CH4OUT #else # define PWM_TIM8_CH4CFG 0 #endif -#ifdef CONFIG_STM32H5_TIM12_CH1OUT +#ifdef CONFIG_STM32_TIM12_CH1OUT # define PWM_TIM12_CH1CFG GPIO_TIM12_CH1OUT #else # define PWM_TIM12_CH1CFG 0 #endif -#ifdef CONFIG_STM32H5_TIM12_CH2OUT +#ifdef CONFIG_STM32_TIM12_CH2OUT # define PWM_TIM12_CH2CFG GPIO_TIM12_CH2OUT #else # define PWM_TIM12_CH2CFG 0 #endif -#ifdef CONFIG_STM32H5_TIM13_CH1OUT +#ifdef CONFIG_STM32_TIM13_CH1OUT # define PWM_TIM13_CH1CFG GPIO_TIM13_CH1OUT #else # define PWM_TIM13_CH1CFG 0 #endif -#ifdef CONFIG_STM32H5_TIM14_CH1OUT +#ifdef CONFIG_STM32_TIM14_CH1OUT # define PWM_TIM14_CH1CFG GPIO_TIM14_CH1OUT #else # define PWM_TIM14_CH1CFG 0 #endif -#ifdef CONFIG_STM32H5_TIM15_CH1OUT +#ifdef CONFIG_STM32_TIM15_CH1OUT # define PWM_TIM15_CH1CFG GPIO_TIM15_CH1OUT #else # define PWM_TIM15_CH1CFG 0 #endif -#ifdef CONFIG_STM32H5_TIM15_CH1NOUT +#ifdef CONFIG_STM32_TIM15_CH1NOUT # define PWM_TIM15_CH1NCFG GPIO_TIM15_CH1NOUT #else # define PWM_TIM15_CH1NCFG 0 #endif -#ifdef CONFIG_STM32H5_TIM15_CH2OUT +#ifdef CONFIG_STM32_TIM15_CH2OUT # define PWM_TIM15_CH2CFG GPIO_TIM15_CH2OUT #else # define PWM_TIM15_CH2CFG 0 #endif -#ifdef CONFIG_STM32H5_TIM16_CH1OUT +#ifdef CONFIG_STM32_TIM16_CH1OUT # define PWM_TIM16_CH1CFG GPIO_TIM16_CH1OUT #else # define PWM_TIM16_CH1CFG 0 #endif -#ifdef CONFIG_STM32H5_TIM16_CH1NOUT +#ifdef CONFIG_STM32_TIM16_CH1NOUT # define PWM_TIM16_CH1NCFG GPIO_TIM16_CH1NOUT #else # define PWM_TIM16_CH1NCFG 0 #endif -#ifdef CONFIG_STM32H5_TIM17_CH1OUT +#ifdef CONFIG_STM32_TIM17_CH1OUT # define PWM_TIM17_CH1CFG GPIO_TIM17_CH1OUT #else # define PWM_TIM17_CH1CFG 0 #endif -#ifdef CONFIG_STM32H5_TIM17_CH1NOUT +#ifdef CONFIG_STM32_TIM17_CH1NOUT # define PWM_TIM17_CH1NCFG GPIO_TIM17_CH1NOUT #else # define PWM_TIM17_CH1NCFG 0 @@ -764,21 +764,21 @@ /* Complementary outputs support */ -#if defined(CONFIG_STM32H5_TIM1_CH1NOUT) || defined(CONFIG_STM32H5_TIM1_CH2NOUT) || \ - defined(CONFIG_STM32H5_TIM1_CH3NOUT) +#if defined(CONFIG_STM32_TIM1_CH1NOUT) || defined(CONFIG_STM32_TIM1_CH2NOUT) || \ + defined(CONFIG_STM32_TIM1_CH3NOUT) # define HAVE_TIM1_COMPLEMENTARY #endif -#if defined(CONFIG_STM32H5_TIM8_CH1NOUT) || defined(CONFIG_STM32H5_TIM8_CH2NOUT) || \ - defined(CONFIG_STM32H5_TIM8_CH3NOUT) +#if defined(CONFIG_STM32_TIM8_CH1NOUT) || defined(CONFIG_STM32_TIM8_CH2NOUT) || \ + defined(CONFIG_STM32_TIM8_CH3NOUT) # define HAVE_TIM8_COMPLEMENTARY #endif -#if defined(CONFIG_STM32H5_TIM15_CH1NOUT) +#if defined(CONFIG_STM32_TIM15_CH1NOUT) # define HAVE_TIM15_COMPLEMENTARY #endif -#if defined(CONFIG_STM32H5_TIM16_CH1NOUT) +#if defined(CONFIG_STM32_TIM16_CH1NOUT) # define HAVE_TIM16_COMPLEMENTARY #endif -#if defined(CONFIG_STM32H5_TIM17_CH1NOUT) +#if defined(CONFIG_STM32_TIM17_CH1NOUT) # define HAVE_TIM17_COMPLEMENTARY #endif #if defined(HAVE_TIM1_COMPLEMENTARY) || defined(HAVE_TIM8_COMPLEMENTARY) || \ @@ -789,7 +789,7 @@ /* Low-level ops helpers ****************************************************/ -#ifdef CONFIG_STM32H5_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS /* NOTE: * low-level ops accept pwm_lowerhalf_s as first argument, but llops access @@ -925,7 +925,7 @@ enum stm32_pwm_output_e #endif }; -#ifdef CONFIG_STM32H5_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS /* This structure provides the publicly visible representation of the * "lower-half" PWM driver structure. @@ -1011,7 +1011,7 @@ struct stm32_pwm_ops_s #endif }; -#endif /* CONFIG_STM32H5_PWM_LL_OPS */ +#endif /* CONFIG_STM32_PWM_LL_OPS */ /**************************************************************************** * Public Data @@ -1057,5 +1057,5 @@ struct pwm_lowerhalf_s *stm32_pwminitialize(int timer); #endif #endif /* __ASSEMBLY__ */ -#endif /* CONFIG_STM32H5_PWM */ +#endif /* CONFIG_STM32_PWM */ #endif /* __ARCH_ARM_SRC_STM32H5_STM32_PWM_H */ diff --git a/arch/arm/src/stm32h5/stm32_qspi.c b/arch/arm/src/stm32h5/stm32_qspi.c index 2a15d2d19d91d..fa0448187bd4c 100644 --- a/arch/arm/src/stm32h5/stm32_qspi.c +++ b/arch/arm/src/stm32h5/stm32_qspi.c @@ -55,11 +55,11 @@ #include "stm32_rcc.h" #include "hardware/stm32_qspi.h" -#ifdef CONFIG_STM32H5_QSPI_DMA +#ifdef CONFIG_STM32_QSPI_DMA #include "stm32_dma.h" #endif -#ifdef CONFIG_STM32H5_QSPI1 +#ifdef CONFIG_STM32_QSPI1 /**************************************************************************** * Pre-processor Definitions @@ -70,7 +70,7 @@ /* Check if QSPI debug is enabled */ #ifndef CONFIG_DEBUG_DMA -# undef CONFIG_STM32H5_QSPI_DMADEBUG +# undef CONFIG_STM32_QSPI_DMADEBUG #endif #define DMA_INITIAL 0 @@ -83,7 +83,7 @@ /* Can't have both interrupt-driven QSPI and DMA QSPI */ -#if defined(CONFIG_STM32H5_QSPI_INTERRUPTS) && defined(CONFIG_STM32H5_QSPI_DMA) +#if defined(CONFIG_STM32_QSPI_INTERRUPTS) && defined(CONFIG_STM32_QSPI_DMA) # error "Cannot enable both interrupt mode and DMA mode for QSPI" #endif @@ -95,7 +95,7 @@ GPIO_QSPI_IO1 GPIO_QSPI_IO2 GPIO_QSPI_IO3 GPIO_QSPI_SCK in your board.h #endif -#ifdef CONFIG_STM32H5_QSPI_DMA +#ifdef CONFIG_STM32_QSPI_DMA # ifdef DMAMAP_QUADSPI @@ -107,26 +107,26 @@ # define DMACHAN_QUADSPI DMAMAP_QUADSPI # endif -# if defined(CONFIG_STM32H5_QSPI_DMAPRIORITY_LOW) +# if defined(CONFIG_STM32_QSPI_DMAPRIORITY_LOW) # define QSPI_DMA_PRIO DMA_SCR_PRILO -# elif defined(CONFIG_STM32H5_QSPI_DMAPRIORITY_MEDIUM) +# elif defined(CONFIG_STM32_QSPI_DMAPRIORITY_MEDIUM) # define QSPI_DMA_PRIO DMA_SCR_PRIMED -# elif defined(CONFIG_STM32H5_QSPI_DMAPRIORITY_HIGH) +# elif defined(CONFIG_STM32_QSPI_DMAPRIORITY_HIGH) # define QSPI_DMA_PRIO DMA_SCR_PRIHI -# elif defined(CONFIG_STM32H5_QSPI_DMAPRIORITY_VERYHIGH) +# elif defined(CONFIG_STM32_QSPI_DMAPRIORITY_VERYHIGH) # define QSPI_DMA_PRIO DMA_SCR_PRIVERYHI # else # define QSPI_DMA_PRIO DMA_SCR_PRIMED # endif -#endif /* CONFIG_STM32H5_QSPI_DMA */ +#endif /* CONFIG_STM32_QSPI_DMA */ #ifndef STM32_SYSCLK_FREQUENCY # error your board.h needs to define the value of STM32_SYSCLK_FREQUENCY #endif -#if !defined(CONFIG_STM32H5_QSPI_FLASH_SIZE) || 0 == CONFIG_STM32H5_QSPI_FLASH_SIZE -# error you must specify a positive flash size via CONFIG_STM32H5_QSPI_FLASH_SIZE +#if !defined(CONFIG_STM32_QSPI_FLASH_SIZE) || 0 == CONFIG_STM32_QSPI_FLASH_SIZE +# error you must specify a positive flash size via CONFIG_STM32_QSPI_FLASH_SIZE #endif /* DMA timeout. The value is not critical; we just don't want the system to @@ -144,11 +144,11 @@ * QUADSPI clock defaults to HCLK. */ -#if defined(CONFIG_STM32H5_QSPI1) && !defined(STM32_RCC_CCIPR4_OCTOSPI1SEL) +#if defined(CONFIG_STM32_QSPI1) && !defined(STM32_RCC_CCIPR4_OCTOSPI1SEL) # error your board.h needs to define STM32_RCC_CCIPR4_OCTOSPI1SEL #endif -#if defined(CONFIG_STM32H5_QSPI1) && !defined(STM32_QSPI_FREQUENCY) +#if defined(CONFIG_STM32_QSPI1) && !defined(STM32_QSPI_FREQUENCY) # error your board.h needs to defined STM32_QSPI_FREQUENCY #else # define QSPI_CLK_FREQUENCY STM32_QSPI_FREQUENCY @@ -183,14 +183,14 @@ struct stm32_qspidev_s mutex_t lock; /* Assures mutually exclusive access to QSPI */ bool memmap; /* TRUE: Controller is in memory mapped mode */ -#ifdef CONFIG_STM32H5_QSPI_INTERRUPTS +#ifdef CONFIG_STM32_QSPI_INTERRUPTS xcpt_t handler; /* Interrupt handler */ uint8_t irq; /* Interrupt number */ sem_t op_sem; /* Block until complete */ struct qspi_xctnspec_s *xctn; /* context of transaction in progress */ #endif -#ifdef CONFIG_STM32H5_QSPI_DMA +#ifdef CONFIG_STM32_QSPI_DMA bool candma; /* DMA is supported */ sem_t dmawait; /* Used to wait for DMA completion */ int result; /* DMA result */ @@ -200,11 +200,11 @@ struct stm32_qspidev_s /* Debug stuff */ -#ifdef CONFIG_STM32H5_QSPI_DMADEBUG +#ifdef CONFIG_STM32_QSPI_DMADEBUG struct stm32_dmaregs_s dmaregs[DMA_NSAMPLES]; #endif -#ifdef CONFIG_STM32H5_QSPI_REGDEBUG +#ifdef CONFIG_STM32_QSPI_REGDEBUG bool wrlast; /* Last was a write */ uint32_t addresslast; /* Last address */ uint32_t valuelast; /* Last value */ @@ -240,7 +240,7 @@ struct qspi_xctnspec_s uint8_t isddr; /* true if 'double data rate' */ -#ifdef CONFIG_STM32H5_QSPI_INTERRUPTS +#ifdef CONFIG_STM32_QSPI_INTERRUPTS uint8_t function; /* functional mode; to distinguish a read or write */ int8_t disposition; /* how it all turned out */ uint32_t idxnow; /* index into databuffer of current byte in transfer */ @@ -253,7 +253,7 @@ struct qspi_xctnspec_s /* Helpers */ -#ifdef CONFIG_STM32H5_QSPI_REGDEBUG +#ifdef CONFIG_STM32_QSPI_REGDEBUG static bool qspi_checkreg(struct stm32_qspidev_s *priv, bool wr, uint32_t value, uint32_t address); #else @@ -280,16 +280,16 @@ static void qspi_dumpgpioconfig(const char *msg); /* Interrupts */ -#ifdef CONFIG_STM32H5_QSPI_INTERRUPTS +#ifdef CONFIG_STM32_QSPI_INTERRUPTS static int qspi0_interrupt(int irq, void *context, void *arg); #endif /* DMA support */ -#ifdef CONFIG_STM32H5_QSPI_DMA +#ifdef CONFIG_STM32_QSPI_DMA -# ifdef CONFIG_STM32H5_QSPI_DMADEBUG +# ifdef CONFIG_STM32_QSPI_DMADEBUG # define qspi_dma_sample(s,i) stm32_dmasample((s)->dmach, &(s)->dmaregs[i]) static void qspi_dma_sampleinit(struct stm32_qspidev_s *priv); static void qspi_dma_sampledone(struct stm32_qspidev_s *priv); @@ -299,8 +299,8 @@ static void qspi_dma_sampledone(struct stm32_qspidev_s *priv); # define qspi_dma_sampledone(s) # endif -# ifndef CONFIG_STM32H5_QSPI_DMATHRESHOLD -# define CONFIG_STM32H5_QSPI_DMATHRESHOLD 4 +# ifndef CONFIG_STM32_QSPI_DMATHRESHOLD +# define CONFIG_STM32_QSPI_DMATHRESHOLD 4 # endif #endif @@ -354,13 +354,13 @@ static struct stm32_qspidev_s g_qspi0dev = }, .base = STM32_OCTOSPI1_BASE, .lock = NXMUTEX_INITIALIZER, -#ifdef CONFIG_STM32H5_QSPI_INTERRUPTS +#ifdef CONFIG_STM32_QSPI_INTERRUPTS .handler = qspi0_interrupt, .irq = STM32_IRQ_OCTOSPI1, .op_sem = SEM_INITIALIZER(0), #endif .intf = 0, -#ifdef CONFIG_STM32H5_QSPI_DMA +#ifdef CONFIG_STM32_QSPI_DMA .candma = true, .dmawait = SEM_INITIALIZER(0), #endif @@ -386,7 +386,7 @@ static struct stm32_qspidev_s g_qspi0dev = * ****************************************************************************/ -#ifdef CONFIG_STM32H5_QSPI_REGDEBUG +#ifdef CONFIG_STM32_QSPI_REGDEBUG static bool qspi_checkreg(struct stm32_qspidev_s *priv, bool wr, uint32_t value, uint32_t address) { @@ -438,7 +438,7 @@ static inline uint32_t qspi_getreg(struct stm32_qspidev_s *priv, uint32_t address = priv->base + offset; uint32_t value = getreg32(address); -#ifdef CONFIG_STM32H5_QSPI_REGDEBUG +#ifdef CONFIG_STM32_QSPI_REGDEBUG if (qspi_checkreg(priv, false, value, address)) { spiinfo("%08" PRIx32 "->%08" PRIx32 "\n", address, value); @@ -461,7 +461,7 @@ static inline void qspi_putreg(struct stm32_qspidev_s *priv, { uint32_t address = priv->base + offset; -#ifdef CONFIG_STM32H5_QSPI_REGDEBUG +#ifdef CONFIG_STM32_QSPI_REGDEBUG if (qspi_checkreg(priv, true, value, address)) { spiinfo("%08" PRIx32 "<-%08" PRIx32 "\n", address, value); @@ -583,7 +583,7 @@ static void qspi_dumpgpioconfig(const char *msg) } #endif -#ifdef CONFIG_STM32H5_QSPI_DMADEBUG +#ifdef CONFIG_STM32_QSPI_DMADEBUG /**************************************************************************** * Name: qspi_dma_sampleinit * @@ -797,7 +797,7 @@ static int qspi_setupxctnfromcmd(struct qspi_xctnspec_s *xctn, xctn->isddr = 0; } -#if defined(CONFIG_STM32H5_QSPI_INTERRUPTS) +#if defined(CONFIG_STM32_QSPI_INTERRUPTS) xctn->function = QSPICMD_ISWRITE(cmdinfo->flags) ? CR_FMODE_INDWR : CR_FMODE_INDRD; xctn->disposition = - EIO; @@ -936,7 +936,7 @@ static int qspi_setupxctnfrommem(struct qspi_xctnspec_s *xctn, xctn->isddr = 0; -#if defined(CONFIG_STM32H5_QSPI_INTERRUPTS) +#if defined(CONFIG_STM32_QSPI_INTERRUPTS) xctn->function = QSPIMEM_ISWRITE(meminfo->flags) ? CR_FMODE_INDWR : CR_FMODE_INDRD; xctn->disposition = - EIO; @@ -1075,7 +1075,7 @@ static void qspi_ccrconfig(struct stm32_qspidev_s *priv, } } -#if defined(CONFIG_STM32H5_QSPI_INTERRUPTS) +#if defined(CONFIG_STM32_QSPI_INTERRUPTS) /**************************************************************************** * Name: qspi0_interrupt * @@ -1298,7 +1298,7 @@ static int qspi0_interrupt(int irq, void *context, void *arg) return OK; } -#elif defined(CONFIG_STM32H5_QSPI_DMA) +#elif defined(CONFIG_STM32_QSPI_DMA) /**************************************************************************** * Name: qspi_dma_timeout * @@ -1571,7 +1571,7 @@ static int qspi_memory_dma(struct stm32_qspidev_s *priv, } #endif -#if !defined(CONFIG_STM32H5_QSPI_INTERRUPTS) +#if !defined(CONFIG_STM32_QSPI_INTERRUPTS) /**************************************************************************** * Name: qspi_receive_blocking * @@ -2017,7 +2017,7 @@ static int qspi_command(struct qspi_dev_s *dev, QSPI_FCR_CTEF | QSPI_FCR_CTCF | QSPI_FCR_CSMF | QSPI_FCR_CTOF, STM32_QUADSPI_FCR_OFFSET); -#ifdef CONFIG_STM32H5_QSPI_INTERRUPTS +#ifdef CONFIG_STM32_QSPI_INTERRUPTS /* interrupt mode will need access to the transaction context */ priv->xctn = &xctn; @@ -2198,7 +2198,7 @@ static int qspi_memory(struct qspi_dev_s *dev, QSPI_FCR_CTEF | QSPI_FCR_CTCF | QSPI_FCR_CSMF | QSPI_FCR_CTOF, STM32_QUADSPI_FCR_OFFSET); -#ifdef CONFIG_STM32H5_QSPI_INTERRUPTS +#ifdef CONFIG_STM32_QSPI_INTERRUPTS /* interrupt mode will need access to the transaction context */ priv->xctn = &xctn; @@ -2257,11 +2257,11 @@ static int qspi_memory(struct qspi_dev_s *dev, ret = xctn.disposition; -#elif defined(CONFIG_STM32H5_QSPI_DMA) +#elif defined(CONFIG_STM32_QSPI_DMA) /* Can we perform DMA? Should we perform DMA? */ if (priv->candma && - meminfo->buflen > CONFIG_STM32H5_QSPI_DMATHRESHOLD && + meminfo->buflen > CONFIG_STM32_QSPI_DMATHRESHOLD && IS_ALIGNED((uintptr_t)meminfo->buffer, 4) && IS_ALIGNED(meminfo->buflen, 4)) { @@ -2423,18 +2423,18 @@ static int qspi_hw_initialize(struct stm32_qspidev_s *priv) regval &= ~(QSPI_CR_TEIE | QSPI_CR_TCIE | QSPI_CR_FTIE | QSPI_CR_SMIE | QSPI_CR_TOIE | QSPI_CR_MSEL | QSPI_CR_DMM); -#if defined(CONFIG_STM32H5_QSPI_MODE_BANK2) +#if defined(CONFIG_STM32_QSPI_MODE_BANK2) regval |= QSPI_CR_MSEL; #endif -#if defined(CONFIG_STM32H5_QSPI_MODE_DUAL) +#if defined(CONFIG_STM32_QSPI_MODE_DUAL) regval |= QSPI_CR_DMM; #endif /* Configure QSPI FIFO Threshold */ regval &= ~(QSPI_CR_FTHRES_MASK); - regval |= ((CONFIG_STM32H5_QSPI_FIFO_THESHOLD - 1) << + regval |= ((CONFIG_STM32_QSPI_FIFO_THESHOLD - 1) << QSPI_CR_FTHRES_SHIFT); qspi_putreg(priv, regval, STM32_QUADSPI_CR_OFFSET); @@ -2460,10 +2460,10 @@ static int qspi_hw_initialize(struct stm32_qspidev_s *priv) QSPI_DCR1_CSHT_MASK | QSPI_DCR1_DEVSIZE_MASK); - regval |= ((CONFIG_STM32H5_QSPI_CSHT - 1) << QSPI_DCR1_CSHT_SHIFT); - if (0 != CONFIG_STM32H5_QSPI_FLASH_SIZE) + regval |= ((CONFIG_STM32_QSPI_CSHT - 1) << QSPI_DCR1_CSHT_SHIFT); + if (0 != CONFIG_STM32_QSPI_FLASH_SIZE) { - unsigned int nsize = CONFIG_STM32H5_QSPI_FLASH_SIZE; + unsigned int nsize = CONFIG_STM32_QSPI_FLASH_SIZE; int nlog2size = 31; while ((nsize & 0x80000000) == 0) @@ -2569,7 +2569,7 @@ struct qspi_dev_s *stm32_qspi_initialize(int intf) { /* Now perform one time initialization. */ -#ifdef CONFIG_STM32H5_QSPI_DMA +#ifdef CONFIG_STM32_QSPI_DMA /* Pre-allocate DMA channels. */ if (priv->candma) @@ -2583,7 +2583,7 @@ struct qspi_dev_s *stm32_qspi_initialize(int intf) } #endif -#ifdef CONFIG_STM32H5_QSPI_INTERRUPTS +#ifdef CONFIG_STM32_QSPI_INTERRUPTS /* Attach the interrupt handler */ ret = irq_attach(priv->irq, priv->handler, NULL); @@ -2609,7 +2609,7 @@ struct qspi_dev_s *stm32_qspi_initialize(int intf) priv->initialized = true; priv->memmap = false; -#ifdef CONFIG_STM32H5_QSPI_INTERRUPTS +#ifdef CONFIG_STM32_QSPI_INTERRUPTS up_enable_irq(priv->irq); #endif } @@ -2617,12 +2617,12 @@ struct qspi_dev_s *stm32_qspi_initialize(int intf) return &priv->qspi; errout_with_irq: -#ifdef CONFIG_STM32H5_QSPI_INTERRUPTS +#ifdef CONFIG_STM32_QSPI_INTERRUPTS irq_detach(priv->irq); errout_with_dmach: #endif -#ifdef CONFIG_STM32H5_QSPI_DMA +#ifdef CONFIG_STM32_QSPI_DMA if (priv->dmach) { stm32_dmafree(priv->dmach); @@ -2688,7 +2688,7 @@ void stm32_qspi_enter_memorymapped(struct qspi_dev_s *dev, qspi_putreg(&g_qspi0dev, QSPI_FCR_CTOF, STM32_QUADSPI_FCR_OFFSET); -#ifdef CONFIG_STM32H5_QSPI_INTERRUPTS +#ifdef CONFIG_STM32_QSPI_INTERRUPTS /* Enable Timeout interrupt */ regval = qspi_getreg(priv, STM32_QUADSPI_CR_OFFSET); @@ -2707,7 +2707,7 @@ void stm32_qspi_enter_memorymapped(struct qspi_dev_s *dev, qspi_setupxctnfrommem(&xctn, meminfo); -#ifdef CONFIG_STM32H5_QSPI_INTERRUPTS +#ifdef CONFIG_STM32_QSPI_INTERRUPTS priv->xctn = NULL; #endif @@ -2753,4 +2753,4 @@ void stm32_qspi_exit_memorymapped(struct qspi_dev_s *dev) qspi_lock(dev, false); } -#endif /* CONFIG_STM32H5_QSPI */ +#endif /* CONFIG_STM32_QSPI */ diff --git a/arch/arm/src/stm32h5/stm32_qspi.h b/arch/arm/src/stm32h5/stm32_qspi.h index e052df4c1d7c3..91485bfa9ba0a 100644 --- a/arch/arm/src/stm32h5/stm32_qspi.h +++ b/arch/arm/src/stm32h5/stm32_qspi.h @@ -33,7 +33,7 @@ #include "chip.h" -#ifdef CONFIG_STM32H5_QSPI1 +#ifdef CONFIG_STM32_QSPI1 /**************************************************************************** * Pre-processor Definitions @@ -125,5 +125,5 @@ void stm32_qspi_exit_memorymapped(struct qspi_dev_s *dev); #endif #endif /* __ASSEMBLY__ */ -#endif /* CONFIG_STM32H5_QSPI */ +#endif /* CONFIG_STM32_QSPI */ #endif /* __ARCH_ARM_SRC_STM32H5_STM32_QSPI_H */ diff --git a/arch/arm/src/stm32h5/stm32_rcc.c b/arch/arm/src/stm32h5/stm32_rcc.c index e54cd1f2ce227..fa541ee24a138 100644 --- a/arch/arm/src/stm32h5/stm32_rcc.c +++ b/arch/arm/src/stm32h5/stm32_rcc.c @@ -55,9 +55,9 @@ static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1, #define LSERDY_TIMEOUT (500 * CONFIG_BOARD_LOOPSPERMSEC) -#ifdef CONFIG_STM32H5_RTC_LSECLOCK_START_DRV_CAPABILITY -# if CONFIG_STM32H5_RTC_LSECLOCK_START_DRV_CAPABILITY < 0 || \ - CONFIG_STM32H5_RTC_LSECLOCK_START_DRV_CAPABILITY > 3 +#ifdef CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY +# if CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY < 0 || \ + CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY > 3 # error "Invalid LSE drive capability setting" # endif #endif @@ -66,7 +66,7 @@ static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1, * Private Data ****************************************************************************/ -#ifdef CONFIG_STM32H5_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY +#ifdef CONFIG_STM32_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY static const uint32_t drives[4] = { RCC_BDCR_LSEDRV_LOW, @@ -101,7 +101,7 @@ static const uint32_t drives[4] = * ****************************************************************************/ -#if defined(CONFIG_STM32H5_PWR) && defined(CONFIG_STM32H5_RTC) +#if defined(CONFIG_STM32_PWR) && defined(CONFIG_STM32_RTC) static inline void rcc_resetbkp(void) { bool init_stat; @@ -111,14 +111,14 @@ static inline void rcc_resetbkp(void) init_stat = stm32h5_rtc_is_initialized(); if (!init_stat) { - uint32_t bkregs[STM32H5_RTC_BKCOUNT]; + uint32_t bkregs[STM32_RTC_BKCOUNT]; int i; /* Backup backup-registers before RTC reset. */ - for (i = 0; i < STM32H5_RTC_BKCOUNT; i++) + for (i = 0; i < STM32_RTC_BKCOUNT; i++) { - bkregs[i] = getreg32(STM32H5_RTC_BKR(i)); + bkregs[i] = getreg32(STM32_RTC_BKR(i)); } /* Enable write access to the backup domain (RTC registers, RTC @@ -136,14 +136,14 @@ static inline void rcc_resetbkp(void) /* Restore backup-registers, except RTC related. */ - for (i = 0; i < STM32H5_RTC_BKCOUNT; i++) + for (i = 0; i < STM32_RTC_BKCOUNT; i++) { - if (RTC_MAGIC_REG == STM32H5_RTC_BKR(i)) + if (RTC_MAGIC_REG == STM32_RTC_BKR(i)) { continue; } - putreg32(bkregs[i], STM32H5_RTC_BKR(i)); + putreg32(bkregs[i], STM32_RTC_BKR(i)); } stm32_pwr_enablebkp(false); @@ -166,7 +166,7 @@ static inline void rcc_resetbkp(void) * and enable peripheral clocking for all peripherals enabled in the NuttX * configuration file. * - * If CONFIG_ARCH_BOARD_STM32H5_CUSTOM_CLOCKCONFIG is defined, then + * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then * clocking will be enabled by an externally provided, board-specific * function called stm32_board_clockconfig(). * @@ -189,7 +189,7 @@ void stm32_clockconfig(void) rcc_resetbkp(); #endif -#if defined(CONFIG_ARCH_BOARD_STM32H5_CUSTOM_CLOCKCONFIG) +#if defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) /* Invoke Board Custom Clock Configuration */ @@ -223,7 +223,7 @@ void stm32_clockconfig(void) * stm32_clockconfig() * reset the currently enabled peripheral clocks. * - * If CONFIG_ARCH_BOARD_STM32H5_CUSTOM_CLOCKCONFIG is defined, then + * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then * clocking will be enabled by an externally provided, board-specific * function called stm32_board_clockconfig(). * @@ -238,7 +238,7 @@ void stm32_clockconfig(void) #ifdef CONFIG_PM void stm32_clockenable(void) { -#if defined(CONFIG_ARCH_BOARD_STM32H5_CUSTOM_CLOCKCONFIG) +#if defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) /* Invoke Board Custom Clock Configuration */ diff --git a/arch/arm/src/stm32h5/stm32_rcc.h b/arch/arm/src/stm32h5/stm32_rcc.h index 49ad30b7f13dc..8e0f56fb786af 100644 --- a/arch/arm/src/stm32h5/stm32_rcc.h +++ b/arch/arm/src/stm32h5/stm32_rcc.h @@ -32,7 +32,7 @@ #include "arm_internal.h" #include "chip.h" -#if defined(CONFIG_STM32H5_STM32H5XXXX) +#if defined(CONFIG_STM32_STM32H5XXXX) # include "hardware/stm32_rcc.h" #else # error "Unsupported STM32H5 chip" @@ -126,7 +126,7 @@ static inline void stm32_mco2config(uint32_t source) * and enable peripheral clocking for all periperipherals enabled in the * NuttX configuration file. * - * If CONFIG_ARCH_BOARD_STM32H5_CUSTOM_CLOCKCONFIG is defined, then + * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then * clocking will be enabled by an externally provided, board-specific * function called stm32_board_clockconfig(). * @@ -149,7 +149,7 @@ void stm32_clockconfig(void); * ****************************************************************************/ -#ifdef CONFIG_ARCH_BOARD_STM32H5_CUSTOM_CLOCKCONFIG +#ifdef CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG void stm32_board_clockconfig(void); #endif @@ -164,7 +164,7 @@ void stm32_board_clockconfig(void); * ****************************************************************************/ -#ifndef CONFIG_ARCH_BOARD_STM32H5_CUSTOM_CLOCKCONFIG +#ifndef CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG void stm32_stdclockconfig(void); #endif @@ -181,7 +181,7 @@ void stm32_stdclockconfig(void); * stm32_clockconfig(): It does not reset any devices, and it does not * reset the currently enabled peripheral clocks. * - * If CONFIG_ARCH_BOARD_STM32H5_CUSTOM_CLOCKCONFIG is defined, then + * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then * clocking will be enabled by an externally provided, board-specific * function called stm32_board_clockconfig(). * diff --git a/arch/arm/src/stm32h5/stm32_serial.c b/arch/arm/src/stm32h5/stm32_serial.c index 4d2e94ad5774e..708809add24fc 100644 --- a/arch/arm/src/stm32h5/stm32_serial.c +++ b/arch/arm/src/stm32h5/stm32_serial.c @@ -84,7 +84,7 @@ /* Verify that DMA has been enabled and the DMA channel has been defined. */ -#if !defined(CONFIG_STM32H5_DMA1) && !defined(CONFIG_STM32H5_DMA2) +#if !defined(CONFIG_STM32_DMA1) && !defined(CONFIG_STM32_DMA2) # error STM32H5 Serial DMA requires one of DMA1 or DMA2 to be enabled #endif @@ -110,19 +110,19 @@ * can be individually invalidated. */ -# if !defined(CONFIG_STM32H5_SERIAL_RXDMA_BUFFER_SIZE) || \ - CONFIG_STM32H5_SERIAL_RXDMA_BUFFER_SIZE == 0 +# if !defined(CONFIG_STM32_SERIAL_RXDMA_BUFFER_SIZE) || \ + CONFIG_STM32_SERIAL_RXDMA_BUFFER_SIZE == 0 # define RXDMA_BUFFER_SIZE 32 # else -# define RXDMA_BUFFER_SIZE ((CONFIG_STM32H5_SERIAL_RXDMA_BUFFER_SIZE + 31) & ~31) +# define RXDMA_BUFFER_SIZE ((CONFIG_STM32_SERIAL_RXDMA_BUFFER_SIZE + 31) & ~31) # endif #endif /* Power management definitions */ -#if defined(CONFIG_PM) && !defined(CONFIG_STM32H5_PM_SERIAL_ACTIVITY) -# define CONFIG_STM32H5_PM_SERIAL_ACTIVITY 10 +#if defined(CONFIG_PM) && !defined(CONFIG_STM32_PM_SERIAL_ACTIVITY) +# define CONFIG_STM32_PM_SERIAL_ACTIVITY 10 #endif /* USART Unconfigure bits */ @@ -142,7 +142,7 @@ * See stm32serial_restoreusartint where the masking is done. */ -#ifdef CONFIG_STM32H5_SERIALBRK_BSDCOMPAT +#ifdef CONFIG_STM32_SERIALBRK_BSDCOMPAT # define USART_CR1_IE_BREAK_INPROGRESS_SHFTS 15 # define USART_CR1_IE_BREAK_INPROGRESS (1 << USART_CR1_IE_BREAK_INPROGRESS_SHFTS) #endif @@ -331,7 +331,7 @@ static const struct uart_ops_s g_uart_dma_ops = /* I/O buffers */ -#ifdef CONFIG_STM32H5_LPUART1_SERIALDRIVER +#ifdef CONFIG_STM32_LPUART1_SERIALDRIVER static char g_lpuart1rxbuffer[CONFIG_LPUART1_RXBUFSIZE]; static char g_lpuart1txbuffer[CONFIG_LPUART1_TXBUFSIZE]; # ifdef CONFIG_LPUART1_RXDMA @@ -339,7 +339,7 @@ static char g_lpuart1rxfifo[RXDMA_BUFFER_SIZE]; # endif #endif -#ifdef CONFIG_STM32H5_USART1_SERIALDRIVER +#ifdef CONFIG_STM32_USART1_SERIALDRIVER static char g_usart1rxbuffer[CONFIG_USART1_RXBUFSIZE]; static char g_usart1txbuffer[CONFIG_USART1_TXBUFSIZE]; # ifdef CONFIG_USART1_RXDMA @@ -347,7 +347,7 @@ static char g_usart1rxfifo[RXDMA_BUFFER_SIZE]; # endif #endif -#ifdef CONFIG_STM32H5_USART2_SERIALDRIVER +#ifdef CONFIG_STM32_USART2_SERIALDRIVER static char g_usart2rxbuffer[CONFIG_USART2_RXBUFSIZE]; static char g_usart2txbuffer[CONFIG_USART2_TXBUFSIZE]; # ifdef CONFIG_USART2_RXDMA @@ -355,7 +355,7 @@ static char g_usart2rxfifo[RXDMA_BUFFER_SIZE]; # endif #endif -#ifdef CONFIG_STM32H5_USART3_SERIALDRIVER +#ifdef CONFIG_STM32_USART3_SERIALDRIVER static char g_usart3rxbuffer[CONFIG_USART3_RXBUFSIZE]; static char g_usart3txbuffer[CONFIG_USART3_TXBUFSIZE]; # ifdef CONFIG_USART3_RXDMA @@ -363,7 +363,7 @@ static char g_usart3rxfifo[RXDMA_BUFFER_SIZE]; # endif #endif -#ifdef CONFIG_STM32H5_UART4_SERIALDRIVER +#ifdef CONFIG_STM32_UART4_SERIALDRIVER static char g_uart4rxbuffer[CONFIG_UART4_RXBUFSIZE]; static char g_uart4txbuffer[CONFIG_UART4_TXBUFSIZE]; # ifdef CONFIG_UART4_RXDMA @@ -371,7 +371,7 @@ static char g_uart4rxfifo[RXDMA_BUFFER_SIZE]; # endif #endif -#ifdef CONFIG_STM32H5_UART5_SERIALDRIVER +#ifdef CONFIG_STM32_UART5_SERIALDRIVER static char g_uart5rxbuffer[CONFIG_UART5_RXBUFSIZE]; static char g_uart5txbuffer[CONFIG_UART5_TXBUFSIZE]; # ifdef CONFIG_UART5_RXDMA @@ -379,7 +379,7 @@ static char g_uart5rxfifo[RXDMA_BUFFER_SIZE]; # endif #endif -#ifdef CONFIG_STM32H5_USART6_SERIALDRIVER +#ifdef CONFIG_STM32_USART6_SERIALDRIVER static char g_usart6rxbuffer[CONFIG_USART6_RXBUFSIZE]; static char g_usart6txbuffer[CONFIG_USART6_TXBUFSIZE]; # ifdef CONFIG_USART6_RXDMA @@ -387,7 +387,7 @@ static char g_usart6rxfifo[RXDMA_BUFFER_SIZE]; # endif #endif -#ifdef CONFIG_STM32H7_UART7_SERIALDRIVER +#ifdef CONFIG_STM32_UART7_SERIALDRIVER static char g_uart7rxbuffer[CONFIG_UART7_RXBUFSIZE]; static char g_uart7txbuffer[CONFIG_UART7_TXBUFSIZE]; # ifdef CONFIG_UART7_RXDMA @@ -403,7 +403,7 @@ static char g_uart8rxfifo[RXDMA_BUFFER_SIZE]; # endif #endif -#ifdef CONFIG_STM32H5_USART10_SERIALDRIVER +#ifdef CONFIG_STM32_USART10_SERIALDRIVER static char g_usart10rxbuffer[CONFIG_USART10_RXBUFSIZE]; static char g_usart10txbuffer[CONFIG_USART10_TXBUFSIZE]; # ifdef CONFIG_USART10_RXDMA @@ -411,7 +411,7 @@ static char g_usart10rxfifo[RXDMA_BUFFER_SIZE]; # endif #endif -#ifdef CONFIG_STM32H5_USART11_SERIALDRIVER +#ifdef CONFIG_STM32_USART11_SERIALDRIVER static char g_usart11rxbuffer[CONFIG_USART11_RXBUFSIZE]; static char g_usart11txbuffer[CONFIG_USART11_TXBUFSIZE]; # ifdef CONFIG_USART11_RXDMA @@ -419,7 +419,7 @@ static char g_usart11rxfifo[RXDMA_BUFFER_SIZE]; # endif #endif -#ifdef CONFIG_STM32H12_UART12_SERIALDRIVER +#ifdef CONFIG_STM32_UART12_SERIALDRIVER static char g_uart12rxbuffer[CONFIG_UART12_RXBUFSIZE]; static char g_uart12txbuffer[CONFIG_UART12_TXBUFSIZE]; # ifdef CONFIG_UART12_RXDMA @@ -429,7 +429,7 @@ static char g_uart12rxfifo[RXDMA_BUFFER_SIZE]; /* This describes the state of the STM32 USART1 ports. */ -#ifdef CONFIG_STM32H5_LPUART1_SERIALDRIVER +#ifdef CONFIG_STM32_LPUART1_SERIALDRIVER static struct stm32_serial_s g_lpuart1priv = { .dev = @@ -504,7 +504,7 @@ static struct stm32_serial_s g_lpuart1priv = }; #endif -#ifdef CONFIG_STM32H5_USART1_SERIALDRIVER +#ifdef CONFIG_STM32_USART1_SERIALDRIVER static struct stm32_serial_s g_usart1priv = { .dev = @@ -581,7 +581,7 @@ static struct stm32_serial_s g_usart1priv = /* This describes the state of the STM32 USART2 port. */ -#ifdef CONFIG_STM32H5_USART2_SERIALDRIVER +#ifdef CONFIG_STM32_USART2_SERIALDRIVER static struct stm32_serial_s g_usart2priv = { .dev = @@ -658,7 +658,7 @@ static struct stm32_serial_s g_usart2priv = /* This describes the state of the STM32 USART3 port. */ -#ifdef CONFIG_STM32H5_USART3_SERIALDRIVER +#ifdef CONFIG_STM32_USART3_SERIALDRIVER static struct stm32_serial_s g_usart3priv = { .dev = @@ -735,7 +735,7 @@ static struct stm32_serial_s g_usart3priv = /* This describes the state of the STM32 UART4 port. */ -#ifdef CONFIG_STM32H5_UART4_SERIALDRIVER +#ifdef CONFIG_STM32_UART4_SERIALDRIVER static struct stm32_serial_s g_uart4priv = { .dev = @@ -812,7 +812,7 @@ static struct stm32_serial_s g_uart4priv = /* This describes the state of the STM32 UART5 port. */ -#ifdef CONFIG_STM32H5_UART5_SERIALDRIVER +#ifdef CONFIG_STM32_UART5_SERIALDRIVER static struct stm32_serial_s g_uart5priv = { .dev = @@ -889,7 +889,7 @@ static struct stm32_serial_s g_uart5priv = /* This describes the state of the STM32 USART6 port. */ -#ifdef CONFIG_STM32H5_USART6_SERIALDRIVER +#ifdef CONFIG_STM32_USART6_SERIALDRIVER static struct stm32_serial_s g_usart6priv = { .dev = @@ -966,7 +966,7 @@ static struct stm32_serial_s g_usart6priv = /* This describes the state of the STM32 UART7 port. */ -#ifdef CONFIG_STM32H5_UART7_SERIALDRIVER +#ifdef CONFIG_STM32_UART7_SERIALDRIVER static struct stm32_serial_s g_uart7priv = { .dev = @@ -1043,7 +1043,7 @@ static struct stm32_serial_s g_uart7priv = /* This describes the state of the STM32 UART8 port. */ -#ifdef CONFIG_STM32H5_UART8_SERIALDRIVER +#ifdef CONFIG_STM32_UART8_SERIALDRIVER static struct stm32_serial_s g_uart8priv = { .dev = @@ -1120,7 +1120,7 @@ static struct stm32_serial_s g_uart8priv = /* This describes the state of the STM32 UART9 port. */ -#ifdef CONFIG_STM32H5_UART9_SERIALDRIVER +#ifdef CONFIG_STM32_UART9_SERIALDRIVER static struct stm32_serial_s g_uart9priv = { .dev = @@ -1197,7 +1197,7 @@ static struct stm32_serial_s g_uart9priv = /* This describes the state of the STM32 USART10 port. */ -#ifdef CONFIG_STM32H5_USART10_SERIALDRIVER +#ifdef CONFIG_STM32_USART10_SERIALDRIVER static struct stm32_serial_s g_usart10priv = { .dev = @@ -1274,7 +1274,7 @@ static struct stm32_serial_s g_usart10priv = /* This describes the state of the STM32 USART11 port. */ -#ifdef CONFIG_STM32H5_USART11_SERIALDRIVER +#ifdef CONFIG_STM32_USART11_SERIALDRIVER static struct stm32_serial_s g_usart11priv = { .dev = @@ -1351,7 +1351,7 @@ static struct stm32_serial_s g_usart11priv = /* This describes the state of the STM32 UART12 port. */ -#ifdef CONFIG_STM32H5_UART12_SERIALDRIVER +#ifdef CONFIG_STM32_UART12_SERIALDRIVER static struct stm32_serial_s g_uart12priv = { .dev = @@ -1429,45 +1429,45 @@ static struct stm32_serial_s g_uart12priv = /* This table lets us iterate over the configured USARTs */ static struct stm32_serial_s * const - g_uart_devs[STM32H5_NLPUART + STM32H5_NUSART + STM32H5_NUART] = + g_uart_devs[STM32_NLPUART + STM32_NUSART + STM32_NUART] = { -#ifdef CONFIG_STM32H5_LPUART1_SERIALDRIVER +#ifdef CONFIG_STM32_LPUART1_SERIALDRIVER [0] = &g_lpuart1priv, #endif -#ifdef CONFIG_STM32H5_USART1_SERIALDRIVER +#ifdef CONFIG_STM32_USART1_SERIALDRIVER [1] = &g_usart1priv, #endif -#ifdef CONFIG_STM32H5_USART2_SERIALDRIVER +#ifdef CONFIG_STM32_USART2_SERIALDRIVER [2] = &g_usart2priv, #endif -#ifdef CONFIG_STM32H5_USART3_SERIALDRIVER +#ifdef CONFIG_STM32_USART3_SERIALDRIVER [3] = &g_usart3priv, #endif -#ifdef CONFIG_STM32H5_UART4_SERIALDRIVER +#ifdef CONFIG_STM32_UART4_SERIALDRIVER [4] = &g_uart4priv, #endif -#ifdef CONFIG_STM32H5_UART5_SERIALDRIVER +#ifdef CONFIG_STM32_UART5_SERIALDRIVER [5] = &g_uart5priv, #endif -#ifdef CONFIG_STM32H5_USART6_SERIALDRIVER +#ifdef CONFIG_STM32_USART6_SERIALDRIVER [6] = &g_usart6priv, #endif -#ifdef CONFIG_STM32H5_UART7_SERIALDRIVER +#ifdef CONFIG_STM32_UART7_SERIALDRIVER [7] = &g_uart7priv, #endif -#ifdef CONFIG_STM32H5_UART8_SERIALDRIVER +#ifdef CONFIG_STM32_UART8_SERIALDRIVER [8] = &g_uart8priv, #endif -#ifdef CONFIG_STM32H5_UART9_SERIALDRIVER +#ifdef CONFIG_STM32_UART9_SERIALDRIVER [9] = &g_uart9priv, #endif -#ifdef CONFIG_STM32H5_USART10_SERIALDRIVER +#ifdef CONFIG_STM32_USART10_SERIALDRIVER [10] = &g_usart10priv, #endif -#ifdef CONFIG_STM32H5_USART11_SERIALDRIVER +#ifdef CONFIG_STM32_USART11_SERIALDRIVER [11] = &g_usart11priv, #endif -#ifdef CONFIG_STM32H5_UART12_SERIALDRIVER +#ifdef CONFIG_STM32_UART12_SERIALDRIVER [12] = &g_uart12priv, #endif }; @@ -1652,7 +1652,7 @@ static void stm32serial_setformat(struct uart_dev_s *dev) /* This first implementation is for U[S]ARTs that support oversampling * by 8 in additional to the standard oversampling by 16. */ -#ifdef CONFIG_STM32H5_LPUART1 +#ifdef CONFIG_STM32_LPUART1 if (priv->islpuart == true) { /* LPUART BRR (19:00) = (256*apbclock_hz/baud_rate) */ @@ -1738,7 +1738,7 @@ static void stm32serial_setformat(struct uart_dev_s *dev) priv->baud; } else -#endif /* CONFIG_STM32H5_LPUART1 */ +#endif /* CONFIG_STM32_LPUART1 */ { uint32_t usartdiv8; @@ -1847,7 +1847,7 @@ static void stm32serial_setformat(struct uart_dev_s *dev) regval = stm32serial_getreg(priv, STM32_USART_CR3_OFFSET); regval &= ~(USART_CR3_CTSE | USART_CR3_RTSE); -#if defined(CONFIG_SERIAL_IFLOWCONTROL) && !defined(CONFIG_STM32H5_FLOWCONTROL_BROKEN) +#if defined(CONFIG_SERIAL_IFLOWCONTROL) && !defined(CONFIG_STM32_FLOWCONTROL_BROKEN) if (priv->iflow && (priv->rts_gpio != 0)) { regval |= USART_CR3_RTSE; @@ -2012,7 +2012,7 @@ static void stm32serial_pm_setsuspend(bool suspend) g_serialpm.serial_suspended = suspend; - for (n = 0; n < STM32H5_NLPUART + STM32H5_NUSART + STM32H5_NUART; n++) + for (n = 0; n < STM32_NLPUART + STM32_NUSART + STM32_NUART; n++) { struct stm32_serial_s *priv = g_uart_devs[n]; @@ -2051,80 +2051,80 @@ static void stm32serial_setapbclock(struct uart_dev_s *dev, bool on) { default: return; -#ifdef CONFIG_STM32H5_LPUART1_SERIALDRIVER +#ifdef CONFIG_STM32_LPUART1_SERIALDRIVER case STM32_LPUART1_BASE: rcc_en = RCC_APB3ENR_LPUART1EN ; regaddr = STM32_RCC_APB3ENR; break; #endif -#ifdef CONFIG_STM32H5_USART1_SERIALDRIVER +#ifdef CONFIG_STM32_USART1_SERIALDRIVER case STM32_USART1_BASE: rcc_en = RCC_APB2ENR_USART1EN ; regaddr = STM32_RCC_APB2ENR; break; #endif -#ifdef CONFIG_STM32H5_USART2_SERIALDRIVER +#ifdef CONFIG_STM32_USART2_SERIALDRIVER case STM32_USART2_BASE: rcc_en = RCC_APB1LENR_USART2EN; regaddr = STM32_RCC_APB1LENR; break; #endif -#ifdef CONFIG_STM32H5_USART3_SERIALDRIVER +#ifdef CONFIG_STM32_USART3_SERIALDRIVER case STM32_USART3_BASE: rcc_en = RCC_APB1LENR_USART3EN; regaddr = STM32_RCC_APB1LENR; break; #endif -#ifdef CONFIG_STM32H5_UART4_SERIALDRIVER +#ifdef CONFIG_STM32_UART4_SERIALDRIVER case STM32_UART4_BASE: rcc_en = RCC_APB1LENR_UART4EN; regaddr = STM32_RCC_APB1LENR; break; #endif -#ifdef CONFIG_STM32H5_UART5_SERIALDRIVER +#ifdef CONFIG_STM32_UART5_SERIALDRIVER case STM32_UART5_BASE: rcc_en = RCC_APB1LENR_UART5EN; regaddr = STM32_RCC_APB1LENR; break; #endif -#ifdef CONFIG_STM32H5_USART6_SERIALDRIVER +#ifdef CONFIG_STM32_USART6_SERIALDRIVER case STM32_USART6_BASE: rcc_en = RCC_APB1LENR_USART6EN; regaddr = STM32_RCC_APB1LENR; break; #endif -#ifdef CONFIG_STM32H5_UART7_SERIALDRIVER +#ifdef CONFIG_STM32_UART7_SERIALDRIVER case STM32_UART7_BASE: rcc_en = RCC_APB1LENR_UART7EN; regaddr = STM32_RCC_APB1LENR; break; #endif -#ifdef CONFIG_STM32H5_UART8_SERIALDRIVER +#ifdef CONFIG_STM32_UART8_SERIALDRIVER case STM32_UART8_BASE: rcc_en = RCC_APB1LENR_UART8EN; regaddr = STM32_RCC_APB1LENR; break; #endif -#ifdef CONFIG_STM32H5_UART9_SERIALDRIVER +#ifdef CONFIG_STM32_UART9_SERIALDRIVER case STM32_UART9_BASE: rcc_en = RCC_APB1HENR_UART9EN; regaddr = STM32_RCC_APB1HENR; break; #endif -#ifdef CONFIG_STM32H5_USART10_SERIALDRIVER +#ifdef CONFIG_STM32_USART10_SERIALDRIVER case STM32_USART10_BASE: rcc_en = RCC_APB1LENR_USART10EN; regaddr = STM32_RCC_APB1LENR; break; #endif -#ifdef CONFIG_STM32H5_USART11_SERIALDRIVER +#ifdef CONFIG_STM32_USART11_SERIALDRIVER case STM32_USART11_BASE: rcc_en = RCC_APB1LENR_USART11EN; regaddr = STM32_RCC_APB1LENR; break; #endif -#ifdef CONFIG_STM32H5_UART12_SERIALDRIVER +#ifdef CONFIG_STM32_UART12_SERIALDRIVER case STM32_UART12_BASE: rcc_en = RCC_APB1HENR_UART12EN; regaddr = STM32_RCC_APB1HENR; @@ -2193,7 +2193,7 @@ static int stm32serial_setup(struct uart_dev_s *dev) { uint32_t config = priv->rts_gpio; -#ifdef CONFIG_STM32H5_FLOWCONTROL_BROKEN +#ifdef CONFIG_STM32_FLOWCONTROL_BROKEN /* Instead of letting hw manage this pin, we will bitbang */ config = (config & ~GPIO_MODE_MASK) | GPIO_OUTPUT; @@ -2584,8 +2584,8 @@ static int stm32serial_interrupt(int irq, void *context, void *arg) /* Report serial activity to the power management logic */ -#if defined(CONFIG_PM) && CONFIG_STM32H5_PM_SERIAL_ACTIVITY > 0 - pm_activity(PM_IDLE_DOMAIN, CONFIG_STM32H5_PM_SERIAL_ACTIVITY); +#if defined(CONFIG_PM) && CONFIG_STM32_PM_SERIAL_ACTIVITY > 0 + pm_activity(PM_IDLE_DOMAIN, CONFIG_STM32_PM_SERIAL_ACTIVITY); #endif /* Loop until there are no characters to be transferred or, @@ -2834,7 +2834,7 @@ static int stm32serial_ioctl(struct file *filep, int cmd, break; #endif -#ifdef CONFIG_STM32H5_USART_SINGLEWIRE +#ifdef CONFIG_STM32_USART_SINGLEWIRE case TIOCSSINGLEWIRE: { uint32_t cr1; @@ -2912,7 +2912,7 @@ static int stm32serial_ioctl(struct file *filep, int cmd, break; #endif -#ifdef CONFIG_STM32H5_USART_INVERT +#ifdef CONFIG_STM32_USART_INVERT case TIOCSINVERT: { uint32_t cr1; @@ -2963,7 +2963,7 @@ static int stm32serial_ioctl(struct file *filep, int cmd, break; #endif -#ifdef CONFIG_STM32H5_USART_SWAP +#ifdef CONFIG_STM32_USART_SWAP case TIOCSSWAP: { uint32_t cr1; @@ -3100,8 +3100,8 @@ static int stm32serial_ioctl(struct file *filep, int cmd, break; #endif /* CONFIG_SERIAL_TERMIOS */ -#ifdef CONFIG_STM32H5_USART_BREAKS -# ifdef CONFIG_STM32H5_SERIALBRK_BSDCOMPAT +#ifdef CONFIG_STM32_USART_BREAKS +# ifdef CONFIG_STM32_SERIALBRK_BSDCOMPAT case TIOCSBRK: /* BSD compatibility: Turn break on, unconditionally */ { irqstate_t flags; @@ -3343,7 +3343,7 @@ static bool stm32serial_rxflowcontrol(struct uart_dev_s *dev, (struct stm32_serial_s *)dev->priv; #if defined(CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS) && \ - defined(CONFIG_STM32H5_FLOWCONTROL_BROKEN) + defined(CONFIG_STM32_FLOWCONTROL_BROKEN) if (priv->iflow && (priv->rts_gpio != 0)) { /* Assert/de-assert nRTS set it high resume/stop sending */ @@ -3699,7 +3699,7 @@ static void stm32serial_txint(struct uart_dev_s *dev, bool enable) } # endif -# ifdef CONFIG_STM32H5_SERIALBRK_BSDCOMPAT +# ifdef CONFIG_STM32_SERIALBRK_BSDCOMPAT if (priv->ie & USART_CR1_IE_BREAK_INPROGRESS) { leave_critical_section(flags); @@ -3930,7 +3930,7 @@ static int stm32serial_pmprepare(struct pm_callback_s *cb, int domain, * buffers. */ - for (n = 0; n < STM32H5_NLPUART + STM32H5_NUSART + STM32H5_NUART; n++) + for (n = 0; n < STM32_NLPUART + STM32_NUSART + STM32_NUART; n++) { struct stm32_serial_s *priv = g_uart_devs[n]; @@ -4000,7 +4000,7 @@ void arm_earlyserialinit(void) /* Disable all USART interrupts */ - for (i = 0; i < STM32H5_NLPUART + STM32H5_NUSART + STM32H5_NUART; i++) + for (i = 0; i < STM32_NLPUART + STM32_NUSART + STM32_NUART; i++) { if (g_uart_devs[i]) { @@ -4049,7 +4049,7 @@ void arm_serialinit(void) #if CONSOLE_UART > 0 uart_register("/dev/console", &g_uart_devs[CONSOLE_UART - 1]->dev); -#ifndef CONFIG_STM32H5_SERIAL_DISABLE_REORDERING +#ifndef CONFIG_STM32_SERIAL_DISABLE_REORDERING /* If not disabled, register the console UART to ttyS0 and exclude * it from initializing it further down */ @@ -4069,7 +4069,7 @@ void arm_serialinit(void) strlcpy(devname, "/dev/ttySx", sizeof(devname)); - for (i = 0; i < STM32H5_NLPUART + STM32H5_NUSART + STM32H5_NUART; i++) + for (i = 0; i < STM32_NLPUART + STM32_NUSART + STM32_NUART; i++) { /* Don't create a device for non-configured ports. */ @@ -4078,7 +4078,7 @@ void arm_serialinit(void) continue; } -#ifndef CONFIG_STM32H5_SERIAL_DISABLE_REORDERING +#ifndef CONFIG_STM32_SERIAL_DISABLE_REORDERING /* Don't create a device for the console - we did that above */ if (g_uart_devs[i]->dev.isconsole) diff --git a/arch/arm/src/stm32h5/stm32_spi.c b/arch/arm/src/stm32h5/stm32_spi.c index 3a66be2eb1d9c..42ce61211f7a9 100644 --- a/arch/arm/src/stm32h5/stm32_spi.c +++ b/arch/arm/src/stm32h5/stm32_spi.c @@ -72,19 +72,19 @@ #include "stm32_gpio.h" #include "stm32_spi.h" -#ifdef CONFIG_STM32H5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA #include "stm32_dma.h" #endif -#if defined(CONFIG_STM32H5_STM32H50XXX) +#if defined(CONFIG_STM32_STM32H50XXX) # define SPI_MAX_KER_CK 250000000 #else # define SPI_MAX_KER_CK 125000000 #endif -#if defined(CONFIG_STM32H5_SPI1) || defined(CONFIG_STM32H5_SPI2) || \ - defined(CONFIG_STM32H5_SPI3) || defined(CONFIG_STM32H5_SPI4) || \ - defined(CONFIG_STM32H5_SPI5) || defined(CONFIG_STM32H5_SPI6) +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || \ + defined(CONFIG_STM32_SPI3) || defined(CONFIG_STM32_SPI4) || \ + defined(CONFIG_STM32_SPI5) || defined(CONFIG_STM32_SPI6) /**************************************************************************** * Pre-processor Definitions @@ -94,18 +94,18 @@ /* SPI interrupts */ -#ifdef CONFIG_STM32H5_SPI_INTERRUPTS +#ifdef CONFIG_STM32_SPI_INTERRUPTS # error "Interrupt driven SPI not yet supported" #endif /* Can't have both interrupt driven SPI and SPI DMA */ -#if defined(CONFIG_STM32H5_SPI_INTERRUPTS) && defined(CONFIG_STM32H5_SPI_DMA) +#if defined(CONFIG_STM32_SPI_INTERRUPTS) && defined(CONFIG_STM32_SPI_DMA) # error "Cannot enable both interrupt mode and DMA mode for SPI" #endif /* SPI DMA priority */ -#ifdef CONFIG_STM32H5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA # if defined(CONFIG_SPI_DMAPRIO) # define SPI_DMA_PRIO CONFIG_SPI_DMAPRIO @@ -142,39 +142,39 @@ # define SPIDMA_BUF_ALIGN # endif -# if defined(CONFIG_STM32H5_SPI1_DMA_BUFFER) && \ - CONFIG_STM32H5_SPI1_DMA_BUFFER > 0 -# define SPI1_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32H5_SPI1_DMA_BUFFER) +# if defined(CONFIG_STM32_SPI1_DMA_BUFFER) && \ + CONFIG_STM32_SPI1_DMA_BUFFER > 0 +# define SPI1_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32_SPI1_DMA_BUFFER) # define SPI1_DMABUFSIZE_ALGN SPIDMA_BUF_ALIGN # endif -# if defined(CONFIG_STM32H5_SPI2_DMA_BUFFER) && \ - CONFIG_STM32H5_SPI2_DMA_BUFFER > 0 -# define SPI2_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32H5_SPI2_DMA_BUFFER) +# if defined(CONFIG_STM32_SPI2_DMA_BUFFER) && \ + CONFIG_STM32_SPI2_DMA_BUFFER > 0 +# define SPI2_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32_SPI2_DMA_BUFFER) # define SPI2_DMABUFSIZE_ALGN SPIDMA_BUF_ALIGN # endif -# if defined(CONFIG_STM32H5_SPI3_DMA_BUFFER) && \ - CONFIG_STM32H5_SPI3_DMA_BUFFER > 0 -# define SPI3_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32H5_SPI3_DMA_BUFFER) +# if defined(CONFIG_STM32_SPI3_DMA_BUFFER) && \ + CONFIG_STM32_SPI3_DMA_BUFFER > 0 +# define SPI3_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32_SPI3_DMA_BUFFER) # define SPI3_DMABUFSIZE_ALGN SPIDMA_BUF_ALIGN # endif -# if defined(CONFIG_STM32H5_SPI4_DMA_BUFFER) && \ - CONFIG_STM32H5_SPI4_DMA_BUFFER > 0 -# define SPI4_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32H5_SPI4_DMA_BUFFER) +# if defined(CONFIG_STM32_SPI4_DMA_BUFFER) && \ + CONFIG_STM32_SPI4_DMA_BUFFER > 0 +# define SPI4_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32_SPI4_DMA_BUFFER) # define SPI4_DMABUFSIZE_ALGN SPIDMA_BUF_ALIGN # endif -# if defined(CONFIG_STM32H5_SPI5_DMA_BUFFER) && \ - CONFIG_STM32H5_SPI5_DMA_BUFFER > 0 -# define SPI5_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32H5_SPI5_DMA_BUFFER) +# if defined(CONFIG_STM32_SPI5_DMA_BUFFER) && \ + CONFIG_STM32_SPI5_DMA_BUFFER > 0 +# define SPI5_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32_SPI5_DMA_BUFFER) # define SPI5_DMABUFSIZE_ALGN SPIDMA_BUF_ALIGN # endif -#if defined(CONFIG_STM32H5_SPI6_DMA_BUFFER) && \ - CONFIG_STM32H5_SPI6_DMA_BUFFER > 0 -# define SPI6_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32H5_SPI6_DMA_BUFFER) +#if defined(CONFIG_STM32_SPI6_DMA_BUFFER) && \ + CONFIG_STM32_SPI6_DMA_BUFFER > 0 +# define SPI6_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32_SPI6_DMA_BUFFER) # define SPI6_DMABUFSIZE_ALGN SPIDMA_BUF_ALIGN # endif @@ -182,7 +182,7 @@ /* Kernel clock configuration */ -#if defined(CONFIG_STM32H5_SPI1) +#if defined(CONFIG_STM32_SPI1) # ifndef STM32_SPI1_FREQUENCY # error Must define STM32_SPI1_FREQUENCY in board.h # else @@ -195,7 +195,7 @@ # endif #endif /* SPI1 */ -#if defined(CONFIG_STM32H5_SPI2) +#if defined(CONFIG_STM32_SPI2) # ifndef STM32_SPI2_FREQUENCY # error Must define STM32_SPI2_FREQUENCY in board.h # else @@ -208,7 +208,7 @@ # endif #endif /* SPI2 */ -#if defined(CONFIG_STM32H5_SPI3) +#if defined(CONFIG_STM32_SPI3) # ifndef STM32_SPI3_FREQUENCY # error Must define STM32_SPI3_FREQUENCY in board.h # else @@ -221,7 +221,7 @@ # endif #endif /* SPI3 */ -#if defined(CONFIG_STM32H5_SPI1) +#if defined(CONFIG_STM32_SPI1) # ifndef STM32_SPI1_FREQUENCY # error Must define STM32_SPI1_FREQUENCY in board.h # else @@ -234,7 +234,7 @@ # endif #endif /* SPI1 */ -#if defined(CONFIG_STM32H5_SPI5) +#if defined(CONFIG_STM32_SPI5) # ifndef STM32_SPI5_FREQUENCY # error Must define STM32_SPI5_FREQUENCY in board.h # else @@ -247,7 +247,7 @@ # endif #endif /* SPI5 */ -#if defined(CONFIG_STM32H5_SPI6) +#if defined(CONFIG_STM32_SPI6) # ifndef STM32_SPI6_FREQUENCY # error Must define STM32_SPI6_FREQUENCY in board.h # else @@ -278,7 +278,7 @@ struct stm32_spidev_s uint32_t spibase; /* SPIn base address */ uint32_t spiclock; /* Clocking for the SPI module */ uint8_t spiirq; /* SPI IRQ number */ -#ifdef CONFIG_STM32H5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA volatile uint8_t rxresult; /* Result of the RX DMA */ volatile uint8_t txresult; /* Result of the RX DMA */ #ifdef CONFIG_SPI_TRIGGER @@ -328,7 +328,7 @@ static inline void spi_dumpregs(struct stm32_spidev_s *priv); /* DMA support */ -#ifdef CONFIG_STM32H5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static int spi_dmarxwait(struct stm32_spidev_s *priv); static int spi_dmatxwait(struct stm32_spidev_s *priv); static inline void spi_dmarxwakeup(struct stm32_spidev_s *priv); @@ -394,7 +394,7 @@ static int spi_pm_prepare(struct pm_callback_s *cb, int domain, * Private Data ****************************************************************************/ -#ifdef CONFIG_STM32H5_SPI1 +#ifdef CONFIG_STM32_SPI1 static const struct spi_ops_s g_sp1iops = { .lock = spi_lock, @@ -443,7 +443,7 @@ static struct stm32_spidev_s g_spi1dev = .spibase = STM32_SPI1_BASE, .spiclock = STM32_SPI1_FREQUENCY, .spiirq = STM32_IRQ_SPI1, -#ifdef CONFIG_STM32H5_SPI1_DMA +#ifdef CONFIG_STM32_SPI1_DMA .rxch = DMAMAP_SPI1_RX, .txch = DMAMAP_SPI1_TX, # if defined(SPI1_DMABUFSIZE_ADJUSTED) @@ -458,15 +458,15 @@ static struct stm32_spidev_s g_spi1dev = #ifdef CONFIG_PM .pm_cb.prepare = spi_pm_prepare, #endif -#ifdef CONFIG_STM32H5_SPI1_COMMTYPE - .config = CONFIG_STM32H5_SPI1_COMMTYPE, +#ifdef CONFIG_STM32_SPI1_COMMTYPE + .config = CONFIG_STM32_SPI1_COMMTYPE, #else .config = FULL_DUPLEX, #endif }; -#endif /* CONFIG_STM32H5_SPI1 */ +#endif /* CONFIG_STM32_SPI1 */ -#ifdef CONFIG_STM32H5_SPI2 +#ifdef CONFIG_STM32_SPI2 static const struct spi_ops_s g_sp2iops = { .lock = spi_lock, @@ -515,7 +515,7 @@ static struct stm32_spidev_s g_spi2dev = .spibase = STM32_SPI2_BASE, .spiclock = STM32_SPI2_FREQUENCY, .spiirq = STM32_IRQ_SPI2, -#ifdef CONFIG_STM32H5_SPI2_DMA +#ifdef CONFIG_STM32_SPI2_DMA .rxch = DMAMAP_SPI2_RX, .txch = DMAMAP_SPI2_TX, # if defined(SPI2_DMABUFSIZE_ADJUSTED) @@ -530,15 +530,15 @@ static struct stm32_spidev_s g_spi2dev = #ifdef CONFIG_PM .pm_cb.prepare = spi_pm_prepare, #endif -#ifdef CONFIG_STM32H5_SPI2_COMMTYPE - .config = CONFIG_STM32H5_SPI2_COMMTYPE, +#ifdef CONFIG_STM32_SPI2_COMMTYPE + .config = CONFIG_STM32_SPI2_COMMTYPE, #else .config = FULL_DUPLEX, #endif }; -#endif /* CONFIG_STM32H5_SPI2 */ +#endif /* CONFIG_STM32_SPI2 */ -#ifdef CONFIG_STM32H5_SPI3 +#ifdef CONFIG_STM32_SPI3 static const struct spi_ops_s g_sp3iops = { .lock = spi_lock, @@ -587,7 +587,7 @@ static struct stm32_spidev_s g_spi3dev = .spibase = STM32_SPI3_BASE, .spiclock = STM32_SPI3_FREQUENCY, .spiirq = STM32_IRQ_SPI3, -#ifdef CONFIG_STM32H5_SPI3_DMA +#ifdef CONFIG_STM32_SPI3_DMA .rxch = DMAMAP_SPI3_RX, .txch = DMAMAP_SPI3_TX, # if defined(SPI3_DMABUFSIZE_ADJUSTED) @@ -602,15 +602,15 @@ static struct stm32_spidev_s g_spi3dev = #ifdef CONFIG_PM .pm_cb.prepare = spi_pm_prepare, #endif -#ifdef CONFIG_STM32H5_SPI3_COMMTYPE - .config = CONFIG_STM32H5_SPI3_COMMTYPE, +#ifdef CONFIG_STM32_SPI3_COMMTYPE + .config = CONFIG_STM32_SPI3_COMMTYPE, #else .config = FULL_DUPLEX, #endif }; -#endif /* CONFIG_STM32H5_SPI3 */ +#endif /* CONFIG_STM32_SPI3 */ -#ifdef CONFIG_STM32H5_SPI4 +#ifdef CONFIG_STM32_SPI4 static const struct spi_ops_s g_sp4iops = { .lock = spi_lock, @@ -659,7 +659,7 @@ static struct stm32_spidev_s g_spi4dev = .spibase = STM32_SPI4_BASE, .spiclock = STM32_SPI4_FREQUENCY, .spiirq = STM32_IRQ_SPI4, -#ifdef CONFIG_STM32H5_SPI4_DMA +#ifdef CONFIG_STM32_SPI4_DMA .rxch = DMAMAP_SPI4_RX, .txch = DMAMAP_SPI4_TX, # if defined(SPI4_DMABUFSIZE_ADJUSTED) @@ -674,15 +674,15 @@ static struct stm32_spidev_s g_spi4dev = #ifdef CONFIG_PM .pm_cb.prepare = spi_pm_prepare, #endif -#ifdef CONFIG_STM32H5_SPI4_COMMTYPE - .config = CONFIG_STM32H5_SPI4_COMMTYPE, +#ifdef CONFIG_STM32_SPI4_COMMTYPE + .config = CONFIG_STM32_SPI4_COMMTYPE, #else .config = FULL_DUPLEX, #endif }; -#endif /* CONFIG_STM32H5_SPI4 */ +#endif /* CONFIG_STM32_SPI4 */ -#ifdef CONFIG_STM32H5_SPI5 +#ifdef CONFIG_STM32_SPI5 static const struct spi_ops_s g_sp5iops = { .lock = spi_lock, @@ -731,7 +731,7 @@ static struct stm32_spidev_s g_spi5dev = .spibase = STM32_SPI5_BASE, .spiclock = STM32_SPI5_FREQUENCY, .spiirq = STM32_IRQ_SPI5, -#ifdef CONFIG_STM32H5_SPI5_DMA +#ifdef CONFIG_STM32_SPI5_DMA .rxch = DMAMAP_SPI5_RX, .txch = DMAMAP_SPI5_TX, # if defined(SPI5_DMABUFSIZE_ADJUSTED) @@ -746,15 +746,15 @@ static struct stm32_spidev_s g_spi5dev = #ifdef CONFIG_PM .pm_cb.prepare = spi_pm_prepare, #endif -#ifdef CONFIG_STM32H5_SPI5_COMMTYPE - .config = CONFIG_STM32H5_SPI5_COMMTYPE, +#ifdef CONFIG_STM32_SPI5_COMMTYPE + .config = CONFIG_STM32_SPI5_COMMTYPE, #else .config = FULL_DUPLEX, #endif }; -#endif /* CONFIG_STM32H5_SPI5 */ +#endif /* CONFIG_STM32_SPI5 */ -#ifdef CONFIG_STM32H5_SPI6 +#ifdef CONFIG_STM32_SPI6 static const struct spi_ops_s g_sp6iops = { .lock = spi_lock, @@ -804,7 +804,7 @@ static struct stm32_spidev_s g_spi6dev = .spibase = STM32_SPI6_BASE, .spiclock = STM32_SPI6_FREQUENCY, .spiirq = STM32_IRQ_SPI6, -#ifdef CONFIG_STM32H5_SPI6_DMA +#ifdef CONFIG_STM32_SPI6_DMA .rxch = DMAMAP_SPI6_RX, .txch = DMAMAP_SPI6_TX, # if defined(SPI6_DMABUFSIZE_ADJUSTED) @@ -819,13 +819,13 @@ static struct stm32_spidev_s g_spi6dev = #ifdef CONFIG_PM .pm_cb.prepare = spi_pm_prepare, #endif -#ifdef CONFIG_STM32H5_SPI6_COMMTYPE - .config = CONFIG_STM32H5_SPI6_COMMTYPE, +#ifdef CONFIG_STM32_SPI6_COMMTYPE + .config = CONFIG_STM32_SPI6_COMMTYPE, #else .config = FULL_DUPLEX, #endif }; -#endif /* CONFIG_STM32H5_SPI6 */ +#endif /* CONFIG_STM32_SPI6 */ /**************************************************************************** * Private Functions @@ -1147,7 +1147,7 @@ static int spi_interrupt(int irq, void *context, void *arg) spi_modifyreg(priv, STM32_SPI_IER_OFFSET, SPI_IER_EOTIE, 0); /* Set result and release wait semaphore */ -#ifdef CONFIG_STM32H5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA priv->txresult = 0x80; nxsem_post(&priv->txsem); #endif @@ -1164,7 +1164,7 @@ static int spi_interrupt(int irq, void *context, void *arg) * ****************************************************************************/ -#ifdef CONFIG_STM32H5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static int spi_dmarxwait(struct stm32_spidev_s *priv) { int ret; @@ -1204,7 +1204,7 @@ static int spi_dmarxwait(struct stm32_spidev_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32H5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static int spi_dmatxwait(struct stm32_spidev_s *priv) { int ret; @@ -1253,7 +1253,7 @@ static int spi_dmatxwait(struct stm32_spidev_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32H5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static inline void spi_dmarxwakeup(struct stm32_spidev_s *priv) { nxsem_post(&priv->rxsem); @@ -1268,7 +1268,7 @@ static inline void spi_dmarxwakeup(struct stm32_spidev_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32H5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_dmarxcallback(DMA_HANDLE handle, uint8_t isr, void *arg) { struct stm32_spidev_s *priv = (struct stm32_spidev_s *)arg; @@ -1288,7 +1288,7 @@ static void spi_dmarxcallback(DMA_HANDLE handle, uint8_t isr, void *arg) * ****************************************************************************/ -#ifdef CONFIG_STM32H5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_dmarxsetup(struct stm32_spidev_s *priv, void *rxbuffer, void *rxdummy, size_t nwords, stm32_dmacfg_t *dmacfg) @@ -1350,7 +1350,7 @@ static void spi_dmarxsetup(struct stm32_spidev_s *priv, * ****************************************************************************/ -#ifdef CONFIG_STM32H5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_dmatxsetup(struct stm32_spidev_s *priv, const void *txbuffer, const void *txdummy, size_t nwords, stm32_dmacfg_t *dmacfg) @@ -1410,7 +1410,7 @@ static void spi_dmatxsetup(struct stm32_spidev_s *priv, * ****************************************************************************/ -#ifdef CONFIG_STM32H5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_dmarxstart(struct stm32_spidev_s *priv) { /* Can't receive in tx only mode */ @@ -1434,7 +1434,7 @@ static void spi_dmarxstart(struct stm32_spidev_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32H5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_dmatxstart(struct stm32_spidev_s *priv) { /* Can't transmit in rx only mode */ @@ -1991,9 +1991,9 @@ static uint32_t spi_send(struct spi_dev_s *dev, uint32_t wd) * ****************************************************************************/ -#if !defined(CONFIG_STM32H5_SPI_DMA) || defined(CONFIG_STM32H5_DMACAPABLE) || \ - defined(CONFIG_STM32H5_SPI_DMATHRESHOLD) -#if !defined(CONFIG_STM32H5_SPI_DMA) +#if !defined(CONFIG_STM32_SPI_DMA) || defined(CONFIG_STM32_DMACAPABLE) || \ + defined(CONFIG_STM32_SPI_DMATHRESHOLD) +#if !defined(CONFIG_STM32_SPI_DMA) static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, void *rxbuffer, size_t nwords) #else @@ -2082,8 +2082,8 @@ static void spi_exchange_nodma(struct spi_dev_s *dev, } } -#endif /* !CONFIG_STM32H5_SPI_DMA || CONFIG_STM32H5_DMACAPABLE || - * CONFIG_STM32H5_SPI_DMATHRESHOLD +#endif /* !CONFIG_STM32_SPI_DMA || CONFIG_STM32_DMACAPABLE || + * CONFIG_STM32_SPI_DMATHRESHOLD */ /**************************************************************************** @@ -2107,7 +2107,7 @@ static void spi_exchange_nodma(struct spi_dev_s *dev, * ****************************************************************************/ -#ifdef CONFIG_STM32H5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, void *rxbuffer, size_t nwords) { @@ -2125,12 +2125,12 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, size_t nbytes = (priv->nbits > 8) ? nwords << 1 : nwords; -#ifdef CONFIG_STM32H5_SPI_DMATHRESHOLD +#ifdef CONFIG_STM32_SPI_DMATHRESHOLD /* If this is a small SPI transfer, then let spi_exchange_nodma() do the * work. */ - if (nbytes <= CONFIG_STM32H5_SPI_DMATHRESHOLD) + if (nbytes <= CONFIG_STM32_SPI_DMATHRESHOLD) { spi_exchange_nodma(dev, txbuffer, rxbuffer, nwords); return; @@ -2194,7 +2194,7 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, spi_dmatxsetup(priv, txbuffer, &txdummy, nwords, &txdmacfg); spi_dmarxsetup(priv, rxbuffer, (uint16_t *)rxdummy, nwords, &rxdmacfg); -#ifdef CONFIG_STM32H5_DMACAPABLE +#ifdef CONFIG_STM32_DMACAPABLE /* Test for DMA capability of only callers buffers, internal buffers are * guaranteed capable. @@ -2324,7 +2324,7 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, priv->trigarmed = false; #endif } -#endif /* CONFIG_STM32H5_SPI_DMA */ +#endif /* CONFIG_STM32_SPI_DMA */ /**************************************************************************** * Name: spi_trigger @@ -2345,7 +2345,7 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, #ifdef CONFIG_SPI_TRIGGER static int spi_trigger(struct spi_dev_s *dev) { -#ifdef CONFIG_STM32H5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev; if (!priv->trigarmed) @@ -2579,7 +2579,7 @@ static void spi_bus_initialize(struct stm32_spidev_s *priv) spi_putreg(priv, STM32_SPI_CRCPOLY_OFFSET, 7); -#ifdef CONFIG_STM32H5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA /* Get DMA channels. NOTE: stm32_dmachannel() will always assign the DMA * channel. If the channel is not available, then stm32_dmachannel() will * block and wait until the channel becomes available. WARNING: If you @@ -2661,7 +2661,7 @@ struct spi_dev_s *stm32_spibus_initialize(int bus) struct stm32_spidev_s *priv = NULL; irqstate_t flags = enter_critical_section(); -#ifdef CONFIG_STM32H5_SPI1 +#ifdef CONFIG_STM32_SPI1 if (bus == 1) { /* Select SPI1 */ @@ -2686,7 +2686,7 @@ struct spi_dev_s *stm32_spibus_initialize(int bus) } else #endif -#ifdef CONFIG_STM32H5_SPI2 +#ifdef CONFIG_STM32_SPI2 if (bus == 2) { /* Select SPI2 */ @@ -2711,7 +2711,7 @@ struct spi_dev_s *stm32_spibus_initialize(int bus) } else #endif -#ifdef CONFIG_STM32H5_SPI3 +#ifdef CONFIG_STM32_SPI3 if (bus == 3) { /* Select SPI3 */ @@ -2736,7 +2736,7 @@ struct spi_dev_s *stm32_spibus_initialize(int bus) } else #endif -#ifdef CONFIG_STM32H5_SPI4 +#ifdef CONFIG_STM32_SPI4 if (bus == 4) { /* Select SPI4 */ @@ -2761,7 +2761,7 @@ struct spi_dev_s *stm32_spibus_initialize(int bus) } else #endif -#ifdef CONFIG_STM32H5_SPI5 +#ifdef CONFIG_STM32_SPI5 if (bus == 5) { /* Select SPI5 */ @@ -2786,7 +2786,7 @@ struct spi_dev_s *stm32_spibus_initialize(int bus) } else #endif -#ifdef CONFIG_STM32H5_SPI6 +#ifdef CONFIG_STM32_SPI6 if (bus == 6) { /* Select SPI6 */ @@ -2819,6 +2819,6 @@ struct spi_dev_s *stm32_spibus_initialize(int bus) return (struct spi_dev_s *)priv; } -#endif /* CONFIG_STM32H5_SPI1 || CONFIG_STM32H5_SPI2 || CONFIG_STM32H5_SPI3 || - * CONFIG_STM32H5_SPI4 || CONFIG_STM32H5_SPI5 || CONFIG_STM32H5_SPI6 +#endif /* CONFIG_STM32_SPI1 || CONFIG_STM32_SPI2 || CONFIG_STM32_SPI3 || + * CONFIG_STM32_SPI4 || CONFIG_STM32_SPI5 || CONFIG_STM32_SPI6 */ diff --git a/arch/arm/src/stm32h5/stm32_spi.h b/arch/arm/src/stm32h5/stm32_spi.h index e1f25c88e4904..42f7ea39e5d2a 100644 --- a/arch/arm/src/stm32h5/stm32_spi.h +++ b/arch/arm/src/stm32h5/stm32_spi.h @@ -112,42 +112,42 @@ struct spi_slave_ctrlr_s *stm32_spi_slave_initialize(int bus); * ****************************************************************************/ -#ifdef CONFIG_STM32H5_SPI1 +#ifdef CONFIG_STM32_SPI1 void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, bool selected); uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid); int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); #endif -#ifdef CONFIG_STM32H5_SPI2 +#ifdef CONFIG_STM32_SPI2 void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid, bool selected); uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid); int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); #endif -#ifdef CONFIG_STM32H5_SPI3 +#ifdef CONFIG_STM32_SPI3 void stm32_spi3select(struct spi_dev_s *dev, uint32_t devid, bool selected); uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid); int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); #endif -#ifdef CONFIG_STM32H5_SPI4 +#ifdef CONFIG_STM32_SPI4 void stm32_spi4select(struct spi_dev_s *dev, uint32_t devid, bool selected); uint8_t stm32_spi4status(struct spi_dev_s *dev, uint32_t devid); int stm32_spi4cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); #endif -#ifdef CONFIG_STM32H5_SPI5 +#ifdef CONFIG_STM32_SPI5 void stm32_spi5select(struct spi_dev_s *dev, uint32_t devid, bool selected); uint8_t stm32_spi5status(struct spi_dev_s *dev, uint32_t devid); int stm32_spi5cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); #endif -#ifdef CONFIG_STM32H5_SPI6 +#ifdef CONFIG_STM32_SPI6 void stm32_spi6select(struct spi_dev_s *dev, uint32_t devid, bool selected); uint8_t stm32_spi6status(struct spi_dev_s *dev, uint32_t devid); @@ -175,32 +175,32 @@ int stm32_spi6cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); ****************************************************************************/ #ifdef CONFIG_SPI_CALLBACK -#ifdef CONFIG_STM32H5_SPI1 +#ifdef CONFIG_STM32_SPI1 int stm32_spi1register(struct spi_dev_s *dev, spi_mediachange_t callback, void *arg); #endif -#ifdef CONFIG_STM32H5_SPI2 +#ifdef CONFIG_STM32_SPI2 int stm32_spi2register(struct spi_dev_s *dev, spi_mediachange_t callback, void *arg); #endif -#ifdef CONFIG_STM32H5_SPI3 +#ifdef CONFIG_STM32_SPI3 int stm32_spi3register(struct spi_dev_s *dev, spi_mediachange_t callback, void *arg); #endif -#ifdef CONFIG_STM32H5_SPI4 +#ifdef CONFIG_STM32_SPI4 int stm32_spi4register(struct spi_dev_s *dev, spi_mediachange_t callback, void *arg); #endif -#ifdef CONFIG_STM32H5_SPI5 +#ifdef CONFIG_STM32_SPI5 int stm32_spi5register(struct spi_dev_s *dev, spi_mediachange_t callback, void *arg); #endif -#ifdef CONFIG_STM32H5_SPI6 +#ifdef CONFIG_STM32_SPI6 int stm32_spi6register(struct spi_dev_s *dev, spi_mediachange_t callback, void *arg); #endif diff --git a/arch/arm/src/stm32h5/stm32_start.c b/arch/arm/src/stm32h5/stm32_start.c index 812f82951edbb..62acdd78f69f7 100644 --- a/arch/arm/src/stm32h5/stm32_start.c +++ b/arch/arm/src/stm32h5/stm32_start.c @@ -83,10 +83,10 @@ */ #define SRAM2_START STM32_SRAM2_BASE -#define SRAM2_END (SRAM2_START + STM32H5_SRAM2_SIZE) +#define SRAM2_END (SRAM2_START + STM32_SRAM2_SIZE) #define SRAM3_START STM32_SRAM3_BASE -#define SRAM3_END (SRAM3_START + STM32H5_SRAM3_SIZE) +#define SRAM3_END (SRAM3_START + STM32_SRAM3_SIZE) #define HEAP_BASE ((uintptr_t)_ebss + CONFIG_IDLETHREAD_STACKSIZE) @@ -176,7 +176,7 @@ void __start(void) *dest++ = *src++; } -#ifdef CONFIG_STM32H5_SRAM2_INIT +#ifdef CONFIG_STM32_SRAM2_INIT /* NOTE: this is optional because this may be inappropriate, especially * if the memory is being used for it's battery backed purpose. In that * case, the first-time initialization needs to be performed by the board @@ -190,7 +190,7 @@ void __start(void) } #endif -#ifdef CONFIG_STM32H5_SRAM3_INIT +#ifdef CONFIG_STM32_SRAM3_INIT for (dest = (uint32_t *)SRAM3_START; dest < (uint32_t *)SRAM3_END; ) { *dest++ = 0; @@ -225,7 +225,7 @@ void __start(void) stm32_board_initialize(); showprogress('C'); -#ifdef CONFIG_STM32H5_ICACHE +#ifdef CONFIG_STM32_ICACHE stm32_enable_icache(); #endif showprogress('G'); diff --git a/arch/arm/src/stm32h5/stm32_tim.c b/arch/arm/src/stm32h5/stm32_tim.c index 0bb2b40fefe31..555afe3c72d74 100644 --- a/arch/arm/src/stm32h5/stm32_tim.c +++ b/arch/arm/src/stm32h5/stm32_tim.c @@ -53,96 +53,96 @@ * include: * * - To generate modulated outputs for such things as motor control. If - * CONFIG_STM32H5_TIMn is defined then the CONFIG_STM32H5_TIMn_PWM may + * CONFIG_STM32_TIMn is defined then the CONFIG_STM32_TIMn_PWM may * also be defined to indicate that the timer is intended to be used for * pulsed output modulation. * - * - To control periodic ADC input sampling. If CONFIG_STM32H5_TIMn is - * defined then CONFIG_STM32H5_TIMn_ADC may also be defined to indicate + * - To control periodic ADC input sampling. If CONFIG_STM32_TIMn is + * defined then CONFIG_STM32_TIMn_ADC may also be defined to indicate * that timer "n" is intended to be used for that purpose. * - * - To control periodic DAC outputs. If CONFIG_STM32H5_TIMn is defined - * then CONFIG_STM32H5_TIMn_DAC may also be defined to indicate that + * - To control periodic DAC outputs. If CONFIG_STM32_TIMn is defined + * then CONFIG_STM32_TIMn_DAC may also be defined to indicate that * timer "n" is intended to be used for that purpose. * - * - To use a Quadrature Encoder. If CONFIG_STM32H5_TIMn is defined then - * CONFIG_STM32H5_TIMn_QE may also be defined to indicate that timer "n" + * - To use a Quadrature Encoder. If CONFIG_STM32_TIMn is defined then + * CONFIG_STM32_TIMn_QE may also be defined to indicate that timer "n" * is intended to be used for that purpose. * * In any of these cases, the timer will not be used by this timer module. */ -#if defined(CONFIG_STM32H5_TIM1_PWM) || defined (CONFIG_STM32H5_TIM1_ADC) || \ - defined(CONFIG_STM32H5_TIM1_DAC) || defined(CONFIG_STM32H5_TIM1_QE) -# undef CONFIG_STM32H5_TIM1 +#if defined(CONFIG_STM32_TIM1_PWM) || defined (CONFIG_STM32_TIM1_ADC) || \ + defined(CONFIG_STM32_TIM1_DAC) || defined(CONFIG_STM32_TIM1_QE) +# undef CONFIG_STM32_TIM1 #endif -#if defined(CONFIG_STM32H5_TIM2_PWM) || defined (CONFIG_STM32H5_TIM2_ADC) || \ - defined(CONFIG_STM32H5_TIM2_DAC) || defined(CONFIG_STM32H5_TIM2_QE) -# undef CONFIG_STM32H5_TIM2 +#if defined(CONFIG_STM32_TIM2_PWM) || defined (CONFIG_STM32_TIM2_ADC) || \ + defined(CONFIG_STM32_TIM2_DAC) || defined(CONFIG_STM32_TIM2_QE) +# undef CONFIG_STM32_TIM2 #endif -#if defined(CONFIG_STM32H5_TIM3_PWM) || defined (CONFIG_STM32H5_TIM3_ADC) || \ - defined(CONFIG_STM32H5_TIM3_DAC) || defined(CONFIG_STM32H5_TIM3_QE) -# undef CONFIG_STM32H5_TIM3 +#if defined(CONFIG_STM32_TIM3_PWM) || defined (CONFIG_STM32_TIM3_ADC) || \ + defined(CONFIG_STM32_TIM3_DAC) || defined(CONFIG_STM32_TIM3_QE) +# undef CONFIG_STM32_TIM3 #endif -#if defined(CONFIG_STM32H5_TIM4_PWM) || defined (CONFIG_STM32H5_TIM4_ADC) || \ - defined(CONFIG_STM32H5_TIM4_DAC) || defined(CONFIG_STM32H5_TIM4_QE) -# undef CONFIG_STM32H5_TIM4 +#if defined(CONFIG_STM32_TIM4_PWM) || defined (CONFIG_STM32_TIM4_ADC) || \ + defined(CONFIG_STM32_TIM4_DAC) || defined(CONFIG_STM32_TIM4_QE) +# undef CONFIG_STM32_TIM4 #endif -#if defined(CONFIG_STM32H5_TIM5_PWM) || defined (CONFIG_STM32H5_TIM5_ADC) || \ - defined(CONFIG_STM32H5_TIM5_DAC) || defined(CONFIG_STM32H5_TIM5_QE) -# undef CONFIG_STM32H5_TIM5 +#if defined(CONFIG_STM32_TIM5_PWM) || defined (CONFIG_STM32_TIM5_ADC) || \ + defined(CONFIG_STM32_TIM5_DAC) || defined(CONFIG_STM32_TIM5_QE) +# undef CONFIG_STM32_TIM5 #endif -#if defined(CONFIG_STM32H5_TIM6_PWM) || defined (CONFIG_STM32H5_TIM6_ADC) || \ - defined(CONFIG_STM32H5_TIM6_DAC) || defined(CONFIG_STM32H5_TIM6_QE) -# undef CONFIG_STM32H5_TIM6 +#if defined(CONFIG_STM32_TIM6_PWM) || defined (CONFIG_STM32_TIM6_ADC) || \ + defined(CONFIG_STM32_TIM6_DAC) || defined(CONFIG_STM32_TIM6_QE) +# undef CONFIG_STM32_TIM6 #endif -#if defined(CONFIG_STM32H5_TIM7_PWM) || defined (CONFIG_STM32H5_TIM7_ADC) || \ - defined(CONFIG_STM32H5_TIM7_DAC) || defined(CONFIG_STM32H5_TIM7_QE) -# undef CONFIG_STM32H5_TIM7 +#if defined(CONFIG_STM32_TIM7_PWM) || defined (CONFIG_STM32_TIM7_ADC) || \ + defined(CONFIG_STM32_TIM7_DAC) || defined(CONFIG_STM32_TIM7_QE) +# undef CONFIG_STM32_TIM7 #endif -#if defined(CONFIG_STM32H5_TIM8_PWM) || defined (CONFIG_STM32H5_TIM8_ADC) || \ - defined(CONFIG_STM32H5_TIM8_DAC) || defined(CONFIG_STM32H5_TIM8_QE) -# undef CONFIG_STM32H5_TIM8 +#if defined(CONFIG_STM32_TIM8_PWM) || defined (CONFIG_STM32_TIM8_ADC) || \ + defined(CONFIG_STM32_TIM8_DAC) || defined(CONFIG_STM32_TIM8_QE) +# undef CONFIG_STM32_TIM8 #endif -#if defined(CONFIG_STM32H5_TIM12_PWM) || defined (CONFIG_STM32H5_TIM12_ADC) || \ - defined(CONFIG_STM32H5_TIM12_DAC) || defined(CONFIG_STM32H5_TIM12_QE) -# undef CONFIG_STM32H5_TIM12 +#if defined(CONFIG_STM32_TIM12_PWM) || defined (CONFIG_STM32_TIM12_ADC) || \ + defined(CONFIG_STM32_TIM12_DAC) || defined(CONFIG_STM32_TIM12_QE) +# undef CONFIG_STM32_TIM12 #endif -#if defined(CONFIG_STM32H5_TIM13_PWM) || defined (CONFIG_STM32H5_TIM13_ADC) || \ - defined(CONFIG_STM32H5_TIM13_DAC) || defined(CONFIG_STM32H5_TIM13_QE) -# undef CONFIG_STM32H5_TIM13 +#if defined(CONFIG_STM32_TIM13_PWM) || defined (CONFIG_STM32_TIM13_ADC) || \ + defined(CONFIG_STM32_TIM13_DAC) || defined(CONFIG_STM32_TIM13_QE) +# undef CONFIG_STM32_TIM13 #endif -#if defined(CONFIG_STM32H5_TIM14_PWM) || defined (CONFIG_STM32H5_TIM14_ADC) || \ - defined(CONFIG_STM32H5_TIM14_DAC) || defined(CONFIG_STM32H5_TIM14_QE) -# undef CONFIG_STM32H5_TIM14 +#if defined(CONFIG_STM32_TIM14_PWM) || defined (CONFIG_STM32_TIM14_ADC) || \ + defined(CONFIG_STM32_TIM14_DAC) || defined(CONFIG_STM32_TIM14_QE) +# undef CONFIG_STM32_TIM14 #endif -#if defined(CONFIG_STM32H5_TIM15_PWM) || defined (CONFIG_STM32H5_TIM15_ADC) || \ - defined(CONFIG_STM32H5_TIM15_DAC) || defined(CONFIG_STM32H5_TIM15_QE) -# undef CONFIG_STM32H5_TIM15 +#if defined(CONFIG_STM32_TIM15_PWM) || defined (CONFIG_STM32_TIM15_ADC) || \ + defined(CONFIG_STM32_TIM15_DAC) || defined(CONFIG_STM32_TIM15_QE) +# undef CONFIG_STM32_TIM15 #endif -#if defined(CONFIG_STM32H5_TIM16_PWM) || defined (CONFIG_STM32H5_TIM16_ADC) || \ - defined(CONFIG_STM32H5_TIM16_DAC) || defined(CONFIG_STM32H5_TIM16_QE) -# undef CONFIG_STM32H5_TIM16 +#if defined(CONFIG_STM32_TIM16_PWM) || defined (CONFIG_STM32_TIM16_ADC) || \ + defined(CONFIG_STM32_TIM16_DAC) || defined(CONFIG_STM32_TIM16_QE) +# undef CONFIG_STM32_TIM16 #endif -#if defined(CONFIG_STM32H5_TIM17_PWM) || defined (CONFIG_STM32H5_TIM17_ADC) || \ - defined(CONFIG_STM32H5_TIM17_DAC) || defined(CONFIG_STM32H5_TIM17_QE) -# undef CONFIG_STM32H5_TIM17 +#if defined(CONFIG_STM32_TIM17_PWM) || defined (CONFIG_STM32_TIM17_ADC) || \ + defined(CONFIG_STM32_TIM17_DAC) || defined(CONFIG_STM32_TIM17_QE) +# undef CONFIG_STM32_TIM17 #endif -#if defined(CONFIG_STM32H5_TIM1) +#if defined(CONFIG_STM32_TIM1) # if defined(GPIO_TIM1_CH1OUT) ||defined(GPIO_TIM1_CH2OUT)||\ defined(GPIO_TIM1_CH3OUT) ||defined(GPIO_TIM1_CH4OUT)||\ defined(GPIO_TIM1_CH5OUT) ||defined(GPIO_TIM1_CH6OUT) @@ -150,35 +150,35 @@ # endif #endif -#if defined(CONFIG_STM32H5_TIM2) +#if defined(CONFIG_STM32_TIM2) # if defined(GPIO_TIM2_CH1OUT) ||defined(GPIO_TIM2_CH2OUT)||\ defined(GPIO_TIM2_CH3OUT) ||defined(GPIO_TIM2_CH4OUT) # define HAVE_TIM2_GPIOCONFIG 1 # endif #endif -#if defined(CONFIG_STM32H5_TIM3) +#if defined(CONFIG_STM32_TIM3) # if defined(GPIO_TIM3_CH1OUT) ||defined(GPIO_TIM3_CH2OUT)||\ defined(GPIO_TIM3_CH3OUT) ||defined(GPIO_TIM3_CH4OUT) # define HAVE_TIM3_GPIOCONFIG 1 # endif #endif -#if defined(CONFIG_STM32H5_TIM4) +#if defined(CONFIG_STM32_TIM4) # if defined(GPIO_TIM4_CH1OUT) ||defined(GPIO_TIM4_CH2OUT)||\ defined(GPIO_TIM4_CH3OUT) ||defined(GPIO_TIM4_CH4OUT) # define HAVE_TIM4_GPIOCONFIG 1 # endif #endif -#if defined(CONFIG_STM32H5_TIM5) +#if defined(CONFIG_STM32_TIM5) # if defined(GPIO_TIM5_CH1OUT) ||defined(GPIO_TIM5_CH2OUT)||\ defined(GPIO_TIM5_CH3OUT) ||defined(GPIO_TIM5_CH4OUT) # define HAVE_TIM5_GPIOCONFIG 1 # endif #endif -#if defined(CONFIG_STM32H5_TIM8) +#if defined(CONFIG_STM32_TIM8) # if defined(GPIO_TIM8_CH1OUT) ||defined(GPIO_TIM8_CH2OUT)||\ defined(GPIO_TIM8_CH3OUT) ||defined(GPIO_TIM8_CH4OUT)||\ defined(GPIO_TIM8_CH5OUT) ||defined(GPIO_TIM8_CH6OUT) @@ -186,37 +186,37 @@ # endif #endif -#if defined(CONFIG_STM32H5_TIM12) +#if defined(CONFIG_STM32_TIM12) # if defined(GPIO_TIM12_CH1OUT) ||defined(GPIO_TIM12_CH2OUT) # define HAVE_TIM12_GPIOCONFIG 1 # endif #endif -#if defined(CONFIG_STM32H5_TIM13) +#if defined(CONFIG_STM32_TIM13) # if defined(GPIO_TIM13_CH1OUT) # define HAVE_TIM13_GPIOCONFIG 1 # endif #endif -#if defined(CONFIG_STM32H5_TIM14) +#if defined(CONFIG_STM32_TIM14) # if defined(GPIO_TIM14_CH1OUT) # define HAVE_TIM14_GPIOCONFIG 1 # endif #endif -#if defined(CONFIG_STM32H5_TIM15) +#if defined(CONFIG_STM32_TIM15) # if defined(GPIO_TIM15_CH1OUT) ||defined(GPIO_TIM15_CH2OUT) # define HAVE_TIM15_GPIOCONFIG 1 # endif #endif -#if defined(CONFIG_STM32H5_TIM16) +#if defined(CONFIG_STM32_TIM16) # if defined(GPIO_TIM16_CH1OUT) # define HAVE_TIM16_GPIOCONFIG 1 # endif #endif -#if defined(CONFIG_STM32H5_TIM17) +#if defined(CONFIG_STM32_TIM17) # if defined(GPIO_TIM17_CH1OUT) # define HAVE_TIM17_GPIOCONFIG 1 # endif @@ -226,13 +226,13 @@ * intended for some other purpose. */ -#if defined(CONFIG_STM32H5_TIM1) || defined(CONFIG_STM32H5_TIM2) || \ - defined(CONFIG_STM32H5_TIM3) || defined(CONFIG_STM32H5_TIM4) || \ - defined(CONFIG_STM32H5_TIM5) || defined(CONFIG_STM32H5_TIM6) || \ - defined(CONFIG_STM32H5_TIM7) || defined(CONFIG_STM32H5_TIM8) || \ - defined(CONFIG_STM32H5_TIM12) || defined(CONFIG_STM32H5_TIM13) || \ - defined(CONFIG_STM32H5_TIM14) || defined(CONFIG_STM32H5_TIM15) || \ - defined(CONFIG_STM32H5_TIM16) || defined(CONFIG_STM32H5_TIM17) +#if defined(CONFIG_STM32_TIM1) || defined(CONFIG_STM32_TIM2) || \ + defined(CONFIG_STM32_TIM3) || defined(CONFIG_STM32_TIM4) || \ + defined(CONFIG_STM32_TIM5) || defined(CONFIG_STM32_TIM6) || \ + defined(CONFIG_STM32_TIM7) || defined(CONFIG_STM32_TIM8) || \ + defined(CONFIG_STM32_TIM12) || defined(CONFIG_STM32_TIM13) || \ + defined(CONFIG_STM32_TIM14) || defined(CONFIG_STM32_TIM15) || \ + defined(CONFIG_STM32_TIM16) || defined(CONFIG_STM32_TIM17) /**************************************************************************** * Private Types @@ -307,7 +307,7 @@ static const struct stm32_tim_ops_s stm32_tim_ops = .checkint = &stm32_tim_checkint, }; -#ifdef CONFIG_STM32H5_TIM1 +#ifdef CONFIG_STM32_TIM1 struct stm32_tim_priv_s stm32_tim1_priv = { .ops = &stm32_tim_ops, @@ -315,7 +315,7 @@ struct stm32_tim_priv_s stm32_tim1_priv = .base = STM32_TIM1_BASE, }; #endif -#ifdef CONFIG_STM32H5_TIM2 +#ifdef CONFIG_STM32_TIM2 struct stm32_tim_priv_s stm32_tim2_priv = { .ops = &stm32_tim_ops, @@ -324,7 +324,7 @@ struct stm32_tim_priv_s stm32_tim2_priv = }; #endif -#ifdef CONFIG_STM32H5_TIM3 +#ifdef CONFIG_STM32_TIM3 struct stm32_tim_priv_s stm32_tim3_priv = { .ops = &stm32_tim_ops, @@ -333,7 +333,7 @@ struct stm32_tim_priv_s stm32_tim3_priv = }; #endif -#ifdef CONFIG_STM32H5_TIM4 +#ifdef CONFIG_STM32_TIM4 struct stm32_tim_priv_s stm32_tim4_priv = { .ops = &stm32_tim_ops, @@ -342,7 +342,7 @@ struct stm32_tim_priv_s stm32_tim4_priv = }; #endif -#ifdef CONFIG_STM32H5_TIM5 +#ifdef CONFIG_STM32_TIM5 struct stm32_tim_priv_s stm32_tim5_priv = { .ops = &stm32_tim_ops, @@ -351,7 +351,7 @@ struct stm32_tim_priv_s stm32_tim5_priv = }; #endif -#ifdef CONFIG_STM32H5_TIM6 +#ifdef CONFIG_STM32_TIM6 struct stm32_tim_priv_s stm32_tim6_priv = { .ops = &stm32_tim_ops, @@ -360,7 +360,7 @@ struct stm32_tim_priv_s stm32_tim6_priv = }; #endif -#ifdef CONFIG_STM32H5_TIM7 +#ifdef CONFIG_STM32_TIM7 struct stm32_tim_priv_s stm32_tim7_priv = { .ops = &stm32_tim_ops, @@ -369,7 +369,7 @@ struct stm32_tim_priv_s stm32_tim7_priv = }; #endif -#ifdef CONFIG_STM32H5_TIM8 +#ifdef CONFIG_STM32_TIM8 struct stm32_tim_priv_s stm32_tim8_priv = { .ops = &stm32_tim_ops, @@ -378,7 +378,7 @@ struct stm32_tim_priv_s stm32_tim8_priv = }; #endif -#ifdef CONFIG_STM32H5_TIM12 +#ifdef CONFIG_STM32_TIM12 struct stm32_tim_priv_s stm32_tim12_priv = { .ops = &stm32_tim_ops, @@ -387,7 +387,7 @@ struct stm32_tim_priv_s stm32_tim12_priv = }; #endif -#ifdef CONFIG_STM32H5_TIM13 +#ifdef CONFIG_STM32_TIM13 struct stm32_tim_priv_s stm32_tim13_priv = { .ops = &stm32_tim_ops, @@ -396,7 +396,7 @@ struct stm32_tim_priv_s stm32_tim13_priv = }; #endif -#ifdef CONFIG_STM32H5_TIM14 +#ifdef CONFIG_STM32_TIM14 struct stm32_tim_priv_s stm32_tim14_priv = { .ops = &stm32_tim_ops, @@ -405,7 +405,7 @@ struct stm32_tim_priv_s stm32_tim14_priv = }; #endif -#ifdef CONFIG_STM32H5_TIM15 +#ifdef CONFIG_STM32_TIM15 struct stm32_tim_priv_s stm32_tim15_priv = { .ops = &stm32_tim_ops, @@ -414,7 +414,7 @@ struct stm32_tim_priv_s stm32_tim15_priv = }; #endif -#ifdef CONFIG_STM32H5_TIM16 +#ifdef CONFIG_STM32_TIM16 struct stm32_tim_priv_s stm32_tim16_priv = { .ops = &stm32_tim_ops, @@ -423,7 +423,7 @@ struct stm32_tim_priv_s stm32_tim16_priv = }; #endif -#ifdef CONFIG_STM32H5_TIM17 +#ifdef CONFIG_STM32_TIM17 struct stm32_tim_priv_s stm32_tim17_priv = { .ops = &stm32_tim_ops, @@ -514,12 +514,12 @@ static int stm32_tim_getwidth(struct stm32_tim_dev_s *dev) switch (((struct stm32_tim_priv_s *)dev)->base) { -#if defined(CONFIG_STM32H5_TIM2) +#if defined(CONFIG_STM32_TIM2) case STM32_TIM2_BASE: return 32; #endif -#if defined(CONFIG_STM32H5_TIM5) +#if defined(CONFIG_STM32_TIM5) case STM32_TIM5_BASE: return 32; #endif @@ -621,72 +621,72 @@ static int stm32_tim_setclock(struct stm32_tim_dev_s *dev, uint32_t freq) switch (((struct stm32_tim_priv_s *)dev)->base) { -#ifdef CONFIG_STM32H5_TIM1 +#ifdef CONFIG_STM32_TIM1 case STM32_TIM1_BASE: freqin = STM32_APB2_TIM1_CLKIN; break; #endif -#ifdef CONFIG_STM32H5_TIM2 +#ifdef CONFIG_STM32_TIM2 case STM32_TIM2_BASE: freqin = STM32_APB1_TIM2_CLKIN; break; #endif -#ifdef CONFIG_STM32H5_TIM3 +#ifdef CONFIG_STM32_TIM3 case STM32_TIM3_BASE: freqin = STM32_APB1_TIM3_CLKIN; break; #endif -#ifdef CONFIG_STM32H5_TIM4 +#ifdef CONFIG_STM32_TIM4 case STM32_TIM4_BASE: freqin = STM32_APB1_TIM4_CLKIN; break; #endif -#ifdef CONFIG_STM32H5_TIM5 +#ifdef CONFIG_STM32_TIM5 case STM32_TIM5_BASE: freqin = STM32_APB1_TIM5_CLKIN; break; #endif -#ifdef CONFIG_STM32H5_TIM6 +#ifdef CONFIG_STM32_TIM6 case STM32_TIM6_BASE: freqin = STM32_APB1_TIM6_CLKIN; break; #endif -#ifdef CONFIG_STM32H5_TIM7 +#ifdef CONFIG_STM32_TIM7 case STM32_TIM7_BASE: freqin = STM32_APB1_TIM7_CLKIN; break; #endif -#ifdef CONFIG_STM32H5_TIM8 +#ifdef CONFIG_STM32_TIM8 case STM32_TIM8_BASE: freqin = STM32_APB2_TIM8_CLKIN; break; #endif -#ifdef CONFIG_STM32H5_TIM12 +#ifdef CONFIG_STM32_TIM12 case STM32_TIM12_BASE: freqin = STM32_APB1_TIM12_CLKIN; break; #endif -#ifdef CONFIG_STM32H5_TIM13 +#ifdef CONFIG_STM32_TIM13 case STM32_TIM13_BASE: freqin = STM32_APB1_TIM13_CLKIN; break; #endif -#ifdef CONFIG_STM32H5_TIM14 +#ifdef CONFIG_STM32_TIM14 case STM32_TIM14_BASE: freqin = STM32_APB1_TIM14_CLKIN; break; #endif -#ifdef CONFIG_STM32H5_TIM15 +#ifdef CONFIG_STM32_TIM15 case STM32_TIM15_BASE: freqin = STM32_APB2_TIM15_CLKIN; break; #endif -#ifdef CONFIG_STM32H5_TIM16 +#ifdef CONFIG_STM32_TIM16 case STM32_TIM16_BASE: freqin = STM32_APB2_TIM16_CLKIN; break; #endif -#ifdef CONFIG_STM32H5_TIM17 +#ifdef CONFIG_STM32_TIM17 case STM32_TIM17_BASE: freqin = STM32_APB2_TIM17_CLKIN; break; @@ -740,72 +740,72 @@ static int stm32_tim_setisr(struct stm32_tim_dev_s *dev, switch (((struct stm32_tim_priv_s *)dev)->base) { -#ifdef CONFIG_STM32H5_TIM1 +#ifdef CONFIG_STM32_TIM1 case STM32_TIM1_BASE: vectorno = STM32_IRQ_TIM1_UP; break; #endif -#ifdef CONFIG_STM32H5_TIM2 +#ifdef CONFIG_STM32_TIM2 case STM32_TIM2_BASE: vectorno = STM32_IRQ_TIM2; break; #endif -#ifdef CONFIG_STM32H5_TIM3 +#ifdef CONFIG_STM32_TIM3 case STM32_TIM3_BASE: vectorno = STM32_IRQ_TIM3; break; #endif -#ifdef CONFIG_STM32H5_TIM4 +#ifdef CONFIG_STM32_TIM4 case STM32_TIM4_BASE: vectorno = STM32_IRQ_TIM4; break; #endif -#ifdef CONFIG_STM32H5_TIM5 +#ifdef CONFIG_STM32_TIM5 case STM32_TIM5_BASE: vectorno = STM32_IRQ_TIM5; break; #endif -#ifdef CONFIG_STM32H5_TIM6 +#ifdef CONFIG_STM32_TIM6 case STM32_TIM6_BASE: vectorno = STM32_IRQ_TIM6; break; #endif -#ifdef CONFIG_STM32H5_TIM7 +#ifdef CONFIG_STM32_TIM7 case STM32_TIM7_BASE: vectorno = STM32_IRQ_TIM7; break; #endif -#ifdef CONFIG_STM32H5_TIM8 +#ifdef CONFIG_STM32_TIM8 case STM32_TIM8_BASE: vectorno = STM32_IRQ_TIM8_UP; break; #endif -#ifdef CONFIG_STM32H5_TIM12 +#ifdef CONFIG_STM32_TIM12 case STM32_TIM12_BASE: vectorno = STM32_IRQ_TIM12; break; #endif -#ifdef CONFIG_STM32H5_TIM13 +#ifdef CONFIG_STM32_TIM13 case STM32_TIM13_BASE: vectorno = STM32_IRQ_TIM13; break; #endif -#ifdef CONFIG_STM32H5_TIM14 +#ifdef CONFIG_STM32_TIM14 case STM32_TIM14_BASE: vectorno = STM32_IRQ_TIM14; break; #endif -#ifdef CONFIG_STM32H5_TIM15 +#ifdef CONFIG_STM32_TIM15 case STM32_TIM15_BASE: vectorno = STM32_IRQ_TIM15; break; #endif -#ifdef CONFIG_STM32H5_TIM16 +#ifdef CONFIG_STM32_TIM16 case STM32_TIM16_BASE: vectorno = STM32_IRQ_TIM16; break; #endif -#ifdef CONFIG_STM32H5_TIM17 +#ifdef CONFIG_STM32_TIM17 case STM32_TIM17_BASE: vectorno = STM32_IRQ_TIM17; break; @@ -1011,7 +1011,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, switch (((struct stm32_tim_priv_s *)dev)->base) { -#ifdef CONFIG_STM32H5_TIM1 +#ifdef CONFIG_STM32_TIM1 case STM32_TIM1_BASE: switch (channel) { @@ -1044,7 +1044,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32H5_TIM2 +#ifdef CONFIG_STM32_TIM2 case STM32_TIM2_BASE: switch (channel) { @@ -1073,7 +1073,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32H5_TIM3 +#ifdef CONFIG_STM32_TIM3 case STM32_TIM3_BASE: switch (channel) { @@ -1102,7 +1102,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32H5_TIM4 +#ifdef CONFIG_STM32_TIM4 case STM32_TIM4_BASE: switch (channel) { @@ -1131,7 +1131,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32H5_TIM5 +#ifdef CONFIG_STM32_TIM5 case STM32_TIM5_BASE: switch (channel) { @@ -1160,7 +1160,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32H5_TIM8 +#ifdef CONFIG_STM32_TIM8 case STM32_TIM8_BASE: switch (channel) { @@ -1194,7 +1194,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, break; #endif -#ifdef CONFIG_STM32H5_TIM12 +#ifdef CONFIG_STM32_TIM12 case STM32_TIM12_BASE: switch (channel) { @@ -1213,7 +1213,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32H5_TIM13 +#ifdef CONFIG_STM32_TIM13 case STM32_TIM13_BASE: switch (channel) { @@ -1227,7 +1227,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32H5_TIM14 +#ifdef CONFIG_STM32_TIM14 case STM32_TIM14_BASE: switch (channel) { @@ -1242,7 +1242,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, break; #endif -#ifdef CONFIG_STM32H5_TIM15 +#ifdef CONFIG_STM32_TIM15 case STM32_TIM15_BASE: switch (channel) { @@ -1261,7 +1261,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32H5_TIM16 +#ifdef CONFIG_STM32_TIM16 case STM32_TIM16_BASE: switch (channel) { @@ -1275,7 +1275,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32H5_TIM17 +#ifdef CONFIG_STM32_TIM17 case STM32_TIM17_BASE: switch (channel) { @@ -1359,85 +1359,85 @@ struct stm32_tim_dev_s *stm32_tim_init(int timer) switch (timer) { -#ifdef CONFIG_STM32H5_TIM1 +#ifdef CONFIG_STM32_TIM1 case 1: dev = (struct stm32_tim_dev_s *)&stm32_tim1_priv; modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM1EN); break; #endif -#ifdef CONFIG_STM32H5_TIM2 +#ifdef CONFIG_STM32_TIM2 case 2: dev = (struct stm32_tim_dev_s *)&stm32_tim2_priv; modifyreg32(STM32_RCC_APB1LENR, 0, RCC_APB1LENR_TIM2EN); break; #endif -#ifdef CONFIG_STM32H5_TIM3 +#ifdef CONFIG_STM32_TIM3 case 3: dev = (struct stm32_tim_dev_s *)&stm32_tim3_priv; modifyreg32(STM32_RCC_APB1LENR, 0, RCC_APB1LENR_TIM3EN); break; #endif -#ifdef CONFIG_STM32H5_TIM4 +#ifdef CONFIG_STM32_TIM4 case 4: dev = (struct stm32_tim_dev_s *)&stm32_tim4_priv; modifyreg32(STM32_RCC_APB1LENR, 0, RCC_APB1LENR_TIM4EN); break; #endif -#ifdef CONFIG_STM32H5_TIM5 +#ifdef CONFIG_STM32_TIM5 case 5: dev = (struct stm32_tim_dev_s *)&stm32_tim5_priv; modifyreg32(STM32_RCC_APB1LENR, 0, RCC_APB1LENR_TIM5EN); break; #endif -#ifdef CONFIG_STM32H5_TIM6 +#ifdef CONFIG_STM32_TIM6 case 6: dev = (struct stm32_tim_dev_s *)&stm32_tim6_priv; modifyreg32(STM32_RCC_APB1LENR, 0, RCC_APB1LENR_TIM6EN); break; #endif -#ifdef CONFIG_STM32H5_TIM7 +#ifdef CONFIG_STM32_TIM7 case 7: dev = (struct stm32_tim_dev_s *)&stm32_tim7_priv; modifyreg32(STM32_RCC_APB1LENR, 0, RCC_APB1LENR_TIM7EN); break; #endif -#ifdef CONFIG_STM32H5_TIM8 +#ifdef CONFIG_STM32_TIM8 case 8: dev = (struct stm32_tim_dev_s *)&stm32_tim8_priv; modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM8EN); break; #endif -#ifdef CONFIG_STM32H5_TIM12 +#ifdef CONFIG_STM32_TIM12 case 12: dev = (struct stm32_tim_dev_s *)&stm32_tim12_priv; modifyreg32(STM32_RCC_APB1LENR, 0, RCC_APB1LENR_TIM12EN); break; #endif -#ifdef CONFIG_STM32H5_TIM13 +#ifdef CONFIG_STM32_TIM13 case 13: dev = (struct stm32_tim_dev_s *)&stm32_tim13_priv; modifyreg32(STM32_RCC_APB1LENR, 0, RCC_APB1LENR_TIM13EN); break; #endif -#ifdef CONFIG_STM32H5_TIM14 +#ifdef CONFIG_STM32_TIM14 case 14: dev = (struct stm32_tim_dev_s *)&stm32_tim14_priv; modifyreg32(STM32_RCC_APB1LENR, 0, RCC_APB1LENR_TIM14EN); break; #endif -#ifdef CONFIG_STM32H5_TIM15 +#ifdef CONFIG_STM32_TIM15 case 15: dev = (struct stm32_tim_dev_s *)&stm32_tim15_priv; modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM15EN); break; #endif -#ifdef CONFIG_STM32H5_TIM16 +#ifdef CONFIG_STM32_TIM16 case 16: dev = (struct stm32_tim_dev_s *)&stm32_tim16_priv; modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM16EN); break; #endif -#ifdef CONFIG_STM32H5_TIM17 +#ifdef CONFIG_STM32_TIM17 case 17: dev = (struct stm32_tim_dev_s *)&stm32_tim17_priv; modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM17EN); @@ -1469,72 +1469,72 @@ int stm32_tim_deinit(struct stm32_tim_dev_s * dev) switch (((struct stm32_tim_priv_s *)dev)->base) { -#ifdef CONFIG_STM32H5_TIM1 +#ifdef CONFIG_STM32_TIM1 case STM32_TIM1_BASE: modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM1EN, 0); break; #endif -#ifdef CONFIG_STM32H5_TIM2 +#ifdef CONFIG_STM32_TIM2 case STM32_TIM2_BASE: modifyreg32(STM32_RCC_APB1LENR, RCC_APB1LENR_TIM2EN, 0); break; #endif -#ifdef CONFIG_STM32H5_TIM3 +#ifdef CONFIG_STM32_TIM3 case STM32_TIM3_BASE: modifyreg32(STM32_RCC_APB1LENR, RCC_APB1LENR_TIM3EN, 0); break; #endif -#ifdef CONFIG_STM32H5_TIM4 +#ifdef CONFIG_STM32_TIM4 case STM32_TIM4_BASE: modifyreg32(STM32_RCC_APB1LENR, RCC_APB1LENR_TIM4EN, 0); break; #endif -#ifdef CONFIG_STM32H5_TIM5 +#ifdef CONFIG_STM32_TIM5 case STM32_TIM5_BASE: modifyreg32(STM32_RCC_APB1LENR, RCC_APB1LENR_TIM5EN, 0); break; #endif -#ifdef CONFIG_STM32H5_TIM6 +#ifdef CONFIG_STM32_TIM6 case STM32_TIM6_BASE: modifyreg32(STM32_RCC_APB1LENR, RCC_APB1LENR_TIM6EN, 0); break; #endif -#ifdef CONFIG_STM32H5_TIM7 +#ifdef CONFIG_STM32_TIM7 case STM32_TIM7_BASE: modifyreg32(STM32_RCC_APB1LENR, RCC_APB1LENR_TIM7EN, 0); break; #endif -#ifdef CONFIG_STM32H5_TIM8 +#ifdef CONFIG_STM32_TIM8 case STM32_TIM8_BASE: modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM8EN, 0); break; #endif -#ifdef CONFIG_STM32H5_TIM12 +#ifdef CONFIG_STM32_TIM12 case STM32_TIM12_BASE: modifyreg32(STM32_RCC_APB1LENR, RCC_APB1LENR_TIM12EN, 0); break; #endif -#ifdef CONFIG_STM32H5_TIM13 +#ifdef CONFIG_STM32_TIM13 case STM32_TIM13_BASE: modifyreg32(STM32_RCC_APB1LENR, RCC_APB1LENR_TIM13EN, 0); break; #endif -#ifdef CONFIG_STM32H5_TIM14 +#ifdef CONFIG_STM32_TIM14 case STM32_TIM14_BASE: modifyreg32(STM32_RCC_APB1LENR, RCC_APB1LENR_TIM14EN, 0); break; #endif -#ifdef CONFIG_STM32H5_TIM15 +#ifdef CONFIG_STM32_TIM15 case STM32_TIM15_BASE: modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM15EN, 0); break; #endif -#ifdef CONFIG_STM32H5_TIM16 +#ifdef CONFIG_STM32_TIM16 case STM32_TIM16_BASE: modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM16EN, 0); break; #endif -#ifdef CONFIG_STM32H5_TIM17 +#ifdef CONFIG_STM32_TIM17 case STM32_TIM17_BASE: modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM17EN, 0); break; @@ -1550,4 +1550,4 @@ int stm32_tim_deinit(struct stm32_tim_dev_s * dev) return OK; } -#endif /* defined(CONFIG_STM32H5_TIM1 || ... || TIM17) */ +#endif /* defined(CONFIG_STM32_TIM1 || ... || TIM17) */ diff --git a/arch/arm/src/stm32h5/stm32_tim_lowerhalf.c b/arch/arm/src/stm32h5/stm32_tim_lowerhalf.c index b31f6771216e3..d0a77244157be 100644 --- a/arch/arm/src/stm32h5/stm32_tim_lowerhalf.c +++ b/arch/arm/src/stm32h5/stm32_tim_lowerhalf.c @@ -58,13 +58,13 @@ #include "stm32_tim.h" #if defined(CONFIG_TIMER) && \ - (defined(CONFIG_STM32H5_TIM1) || defined(CONFIG_STM32H5_TIM2) || \ - defined(CONFIG_STM32H5_TIM3) || defined(CONFIG_STM32H5_TIM4) || \ - defined(CONFIG_STM32H5_TIM5) || defined(CONFIG_STM32H5_TIM6) || \ - defined(CONFIG_STM32H5_TIM7) || defined(CONFIG_STM32H5_TIM8) || \ - defined(CONFIG_STM32H5_TIM12) || defined(CONFIG_STM32H5_TIM13) || \ - defined(CONFIG_STM32H5_TIM14) || defined(CONFIG_STM32H5_TIM15) || \ - defined(CONFIG_STM32H5_TIM16) || defined(CONFIG_STM32H5_TIM17)) + (defined(CONFIG_STM32_TIM1) || defined(CONFIG_STM32_TIM2) || \ + defined(CONFIG_STM32_TIM3) || defined(CONFIG_STM32_TIM4) || \ + defined(CONFIG_STM32_TIM5) || defined(CONFIG_STM32_TIM6) || \ + defined(CONFIG_STM32_TIM7) || defined(CONFIG_STM32_TIM8) || \ + defined(CONFIG_STM32_TIM12) || defined(CONFIG_STM32_TIM13) || \ + defined(CONFIG_STM32_TIM14) || defined(CONFIG_STM32_TIM15) || \ + defined(CONFIG_STM32_TIM16) || defined(CONFIG_STM32_TIM17)) /**************************************************************************** * Pre-processor Definitions @@ -135,7 +135,7 @@ static const struct timer_ops_s g_timer_ops = .ioctl = NULL, }; -#ifdef CONFIG_STM32H5_TIM1 +#ifdef CONFIG_STM32_TIM1 static struct stm32_lowerhalf_s g_tim1_lowerhalf = { .ops = &g_timer_ops, @@ -143,7 +143,7 @@ static struct stm32_lowerhalf_s g_tim1_lowerhalf = }; #endif -#ifdef CONFIG_STM32H5_TIM2 +#ifdef CONFIG_STM32_TIM2 static struct stm32_lowerhalf_s g_tim2_lowerhalf = { .ops = &g_timer_ops, @@ -151,7 +151,7 @@ static struct stm32_lowerhalf_s g_tim2_lowerhalf = }; #endif -#ifdef CONFIG_STM32H5_TIM3 +#ifdef CONFIG_STM32_TIM3 static struct stm32_lowerhalf_s g_tim3_lowerhalf = { .ops = &g_timer_ops, @@ -159,7 +159,7 @@ static struct stm32_lowerhalf_s g_tim3_lowerhalf = }; #endif -#ifdef CONFIG_STM32H5_TIM4 +#ifdef CONFIG_STM32_TIM4 static struct stm32_lowerhalf_s g_tim4_lowerhalf = { .ops = &g_timer_ops, @@ -167,7 +167,7 @@ static struct stm32_lowerhalf_s g_tim4_lowerhalf = }; #endif -#ifdef CONFIG_STM32H5_TIM5 +#ifdef CONFIG_STM32_TIM5 static struct stm32_lowerhalf_s g_tim5_lowerhalf = { .ops = &g_timer_ops, @@ -175,7 +175,7 @@ static struct stm32_lowerhalf_s g_tim5_lowerhalf = }; #endif -#ifdef CONFIG_STM32H5_TIM6 +#ifdef CONFIG_STM32_TIM6 static struct stm32_lowerhalf_s g_tim6_lowerhalf = { .ops = &g_timer_ops, @@ -183,7 +183,7 @@ static struct stm32_lowerhalf_s g_tim6_lowerhalf = }; #endif -#ifdef CONFIG_STM32H5_TIM7 +#ifdef CONFIG_STM32_TIM7 static struct stm32_lowerhalf_s g_tim7_lowerhalf = { .ops = &g_timer_ops, @@ -191,7 +191,7 @@ static struct stm32_lowerhalf_s g_tim7_lowerhalf = }; #endif -#ifdef CONFIG_STM32H5_TIM8 +#ifdef CONFIG_STM32_TIM8 static struct stm32_lowerhalf_s g_tim8_lowerhalf = { .ops = &g_timer_ops, @@ -199,7 +199,7 @@ static struct stm32_lowerhalf_s g_tim8_lowerhalf = }; #endif -#ifdef CONFIG_STM32H5_TIM12 +#ifdef CONFIG_STM32_TIM12 static struct stm32_lowerhalf_s g_tim12_lowerhalf = { .ops = &g_timer_ops, @@ -207,7 +207,7 @@ static struct stm32_lowerhalf_s g_tim12_lowerhalf = }; #endif -#ifdef CONFIG_STM32H5_TIM13 +#ifdef CONFIG_STM32_TIM13 static struct stm32_lowerhalf_s g_tim13_lowerhalf = { .ops = &g_timer_ops, @@ -215,7 +215,7 @@ static struct stm32_lowerhalf_s g_tim13_lowerhalf = }; #endif -#ifdef CONFIG_STM32H5_TIM14 +#ifdef CONFIG_STM32_TIM14 static struct stm32_lowerhalf_s g_tim14_lowerhalf = { .ops = &g_timer_ops, @@ -223,7 +223,7 @@ static struct stm32_lowerhalf_s g_tim14_lowerhalf = }; #endif -#ifdef CONFIG_STM32H5_TIM15 +#ifdef CONFIG_STM32_TIM15 static struct stm32_lowerhalf_s g_tim15_lowerhalf = { .ops = &g_timer_ops, @@ -231,7 +231,7 @@ static struct stm32_lowerhalf_s g_tim15_lowerhalf = }; #endif -#ifdef CONFIG_STM32H5_TIM16 +#ifdef CONFIG_STM32_TIM16 static struct stm32_lowerhalf_s g_tim16_lowerhalf = { .ops = &g_timer_ops, @@ -239,7 +239,7 @@ static struct stm32_lowerhalf_s g_tim16_lowerhalf = }; #endif -#ifdef CONFIG_STM32H5_TIM17 +#ifdef CONFIG_STM32_TIM17 static struct stm32_lowerhalf_s g_tim17_lowerhalf = { .ops = &g_timer_ops, @@ -473,75 +473,75 @@ int stm32_timer_initialize(const char *devpath, int timer) switch (timer) { -#ifdef CONFIG_STM32H5_TIM1 +#ifdef CONFIG_STM32_TIM1 case 1: lower = &g_tim1_lowerhalf; break; #endif -#ifdef CONFIG_STM32H5_TIM2 +#ifdef CONFIG_STM32_TIM2 case 2: lower = &g_tim2_lowerhalf; break; #endif -#ifdef CONFIG_STM32H5_TIM3 +#ifdef CONFIG_STM32_TIM3 case 3: lower = &g_tim3_lowerhalf; break; #endif -#ifdef CONFIG_STM32H5_TIM4 +#ifdef CONFIG_STM32_TIM4 case 4: lower = &g_tim4_lowerhalf; break; #endif -#ifdef CONFIG_STM32H5_TIM5 +#ifdef CONFIG_STM32_TIM5 case 5: lower = &g_tim5_lowerhalf; break; #endif -#ifdef CONFIG_STM32H5_TIM6 +#ifdef CONFIG_STM32_TIM6 case 6: lower = &g_tim6_lowerhalf; break; #endif -#ifdef CONFIG_STM32H5_TIM7 +#ifdef CONFIG_STM32_TIM7 case 7: lower = &g_tim7_lowerhalf; break; #endif -#ifdef CONFIG_STM32H5_TIM8 +#ifdef CONFIG_STM32_TIM8 case 8: lower = &g_tim8_lowerhalf; break; #endif -#ifdef CONFIG_STM32H5_TIM12 +#ifdef CONFIG_STM32_TIM12 case 12: lower = &g_tim12_lowerhalf; break; #endif -#ifdef CONFIG_STM32H5_TIM13 +#ifdef CONFIG_STM32_TIM13 case 13: lower = &g_tim13_lowerhalf; break; #endif -#ifdef CONFIG_STM32H5_TIM14 +#ifdef CONFIG_STM32_TIM14 case 14: lower = &g_tim14_lowerhalf; break; #endif -#ifdef CONFIG_STM32H5_TIM15 +#ifdef CONFIG_STM32_TIM15 case 15: lower = &g_tim15_lowerhalf; break; #endif -#ifdef CONFIG_STM32H5_TIM16 +#ifdef CONFIG_STM32_TIM16 case 16: lower = &g_tim16_lowerhalf; break; #endif -#ifdef CONFIG_STM32H5_TIM17 +#ifdef CONFIG_STM32_TIM17 case 17: lower = &g_tim17_lowerhalf; break; diff --git a/arch/arm/src/stm32h5/stm32_timerisr.c b/arch/arm/src/stm32h5/stm32_timerisr.c index 448f063b87f2f..d985e469cfc66 100644 --- a/arch/arm/src/stm32h5/stm32_timerisr.c +++ b/arch/arm/src/stm32h5/stm32_timerisr.c @@ -58,9 +58,9 @@ * And I don't know now to re-configure it yet */ -#undef CONFIG_STM32H5_SYSTICK_HCLKd8 +#undef CONFIG_STM32_SYSTICK_HCLKd8 -#ifdef CONFIG_STM32H5_SYSTICK_HCLKd8 +#ifdef CONFIG_STM32_SYSTICK_HCLKd8 # define SYSTICK_RELOAD ((STM32_HCLK_FREQUENCY / 8 / CLK_TCK) - 1) #else # define SYSTICK_RELOAD ((STM32_HCLK_FREQUENCY / CLK_TCK) - 1) @@ -123,7 +123,7 @@ void up_timer_initialize(void) #if 0 /* Does not work. Comes up with HCLK source and I can't change it */ regval = getreg32(NVIC_SYSTICK_CTRL); -#ifdef CONFIG_STM32H5_SYSTICK_HCLKd8 +#ifdef CONFIG_STM32_SYSTICK_HCLKd8 regval &= ~NVIC_SYSTICK_CTRL_CLKSOURCE; #else regval |= NVIC_SYSTICK_CTRL_CLKSOURCE; diff --git a/arch/arm/src/stm32h5/stm32_uart.h b/arch/arm/src/stm32h5/stm32_uart.h index 93914500e7668..04680b4789b82 100644 --- a/arch/arm/src/stm32h5/stm32_uart.h +++ b/arch/arm/src/stm32h5/stm32_uart.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_STC_STM32H5_STM32_UART_H -#define __ARCH_ARM_STC_STM32H5_STM32_UART_H +#ifndef __ARCH_ARM_SRC_STM32H5_STM32_UART_H +#define __ARCH_ARM_SRC_STM32H5_STM32_UART_H /**************************************************************************** * Included Files @@ -32,7 +32,7 @@ #include "chip.h" -#if defined(CONFIG_STM32H5_STM32H5XXXX) +#if defined(CONFIG_STM32_STM32H5XXXX) # include "hardware/stm32_uart.h" #else # error "Unsupported STM32H5 chip" @@ -46,116 +46,116 @@ * device. */ -#if !defined(CONFIG_STM32H5_HAVE_UART12) -# undef CONFIG_STM32H5_UART12 +#if !defined(CONFIG_STM32_HAVE_UART12) +# undef CONFIG_STM32_UART12 #endif -#if !defined(CONFIG_STM32H5_HAVE_USART11) -# undef CONFIG_STM32H5_USART11 +#if !defined(CONFIG_STM32_HAVE_USART11) +# undef CONFIG_STM32_USART11 #endif -#if !defined(CONFIG_STM32H5_HAVE_USART10) -# undef CONFIG_STM32H5_USART10 +#if !defined(CONFIG_STM32_HAVE_USART10) +# undef CONFIG_STM32_USART10 #endif -#if !defined(CONFIG_STM32H5_HAVE_UART9) -# undef CONFIG_STM32H5_UART9 +#if !defined(CONFIG_STM32_HAVE_UART9) +# undef CONFIG_STM32_UART9 #endif -#if !defined(CONFIG_STM32H5_HAVE_UART8) -# undef CONFIG_STM32H5_UART8 +#if !defined(CONFIG_STM32_HAVE_UART8) +# undef CONFIG_STM32_UART8 #endif -#if !defined(CONFIG_STM32H5_HAVE_UART7) -# undef CONFIG_STM32H5_UART7 +#if !defined(CONFIG_STM32_HAVE_UART7) +# undef CONFIG_STM32_UART7 #endif -#if !defined(CONFIG_STM32H5_HAVE_USART6) -# undef CONFIG_STM32H5_USART6 +#if !defined(CONFIG_STM32_HAVE_USART6) +# undef CONFIG_STM32_USART6 #endif -#if !defined(CONFIG_STM32H5_HAVE_UART5) -# undef CONFIG_STM32H5_UART5 +#if !defined(CONFIG_STM32_HAVE_UART5) +# undef CONFIG_STM32_UART5 #endif -#if !defined(CONFIG_STM32H5_HAVE_UART4) -# undef CONFIG_STM32H5_UART4 +#if !defined(CONFIG_STM32_HAVE_UART4) +# undef CONFIG_STM32_UART4 #endif -#if !defined(CONFIG_STM32H5_HAVE_USART3) -# undef CONFIG_STM32H5_USART3 +#if !defined(CONFIG_STM32_HAVE_USART3) +# undef CONFIG_STM32_USART3 #endif -#if !defined(CONFIG_STM32H5_HAVE_USART2) -# undef CONFIG_STM32H5_USART2 +#if !defined(CONFIG_STM32_HAVE_USART2) +# undef CONFIG_STM32_USART2 #endif -#if !defined(CONFIG_STM32H5_HAVE_USART1) -# undef CONFIG_STM32H5_USART1 +#if !defined(CONFIG_STM32_HAVE_USART1) +# undef CONFIG_STM32_USART1 #endif -#if !defined(CONFIG_STM32H5_HAVE_LPUART1) -# undef CONFIG_STM32H5_LPUART1 +#if !defined(CONFIG_STM32_HAVE_LPUART1) +# undef CONFIG_STM32_LPUART1 #endif /* Sanity checks */ -#if !defined(CONFIG_STM32H5_LPUART1) -# undef CONFIG_STM32H5_LPUART1_SERIALDRIVER -# undef CONFIG_STM32H5_LPUART1_1WIREDRIVER +#if !defined(CONFIG_STM32_LPUART1) +# undef CONFIG_STM32_LPUART1_SERIALDRIVER +# undef CONFIG_STM32_LPUART1_1WIREDRIVER #endif -#if !defined(CONFIG_STM32H5_USART1) -# undef CONFIG_STM32H5_USART1_SERIALDRIVER -# undef CONFIG_STM32H5_USART1_1WIREDRIVER +#if !defined(CONFIG_STM32_USART1) +# undef CONFIG_STM32_USART1_SERIALDRIVER +# undef CONFIG_STM32_USART1_1WIREDRIVER #endif -#if !defined(CONFIG_STM32H5_USART2) -# undef CONFIG_STM32H5_USART2_SERIALDRIVER -# undef CONFIG_STM32H5_USART2_1WIREDRIVER +#if !defined(CONFIG_STM32_USART2) +# undef CONFIG_STM32_USART2_SERIALDRIVER +# undef CONFIG_STM32_USART2_1WIREDRIVER #endif -#if !defined(CONFIG_STM32H5_USART3) -# undef CONFIG_STM32H5_USART3_SERIALDRIVER -# undef CONFIG_STM32H5_USART3_1WIREDRIVER +#if !defined(CONFIG_STM32_USART3) +# undef CONFIG_STM32_USART3_SERIALDRIVER +# undef CONFIG_STM32_USART3_1WIREDRIVER #endif -#if !defined(CONFIG_STM32H5_UART4) -# undef CONFIG_STM32H5_UART4_SERIALDRIVER -# undef CONFIG_STM32H5_UART4_1WIREDRIVER +#if !defined(CONFIG_STM32_UART4) +# undef CONFIG_STM32_UART4_SERIALDRIVER +# undef CONFIG_STM32_UART4_1WIREDRIVER #endif -#if !defined(CONFIG_STM32H5_UART5) -# undef CONFIG_STM32H5_UART5_SERIALDRIVER -# undef CONFIG_STM32H5_UART5_1WIREDRIVER +#if !defined(CONFIG_STM32_UART5) +# undef CONFIG_STM32_UART5_SERIALDRIVER +# undef CONFIG_STM32_UART5_1WIREDRIVER #endif -#if !defined(CONFIG_STM32H5_USART6) -# undef CONFIG_STM32H5_USART6_SERIALDRIVER -# undef CONFIG_STM32H5_USART6_1WIREDRIVER +#if !defined(CONFIG_STM32_USART6) +# undef CONFIG_STM32_USART6_SERIALDRIVER +# undef CONFIG_STM32_USART6_1WIREDRIVER #endif -#if !defined(CONFIG_STM32H5_UART7) -# undef CONFIG_STM32H5_UART7_SERIALDRIVER -# undef CONFIG_STM32H5_UART7_1WIREDRIVER +#if !defined(CONFIG_STM32_UART7) +# undef CONFIG_STM32_UART7_SERIALDRIVER +# undef CONFIG_STM32_UART7_1WIREDRIVER #endif -#if !defined(CONFIG_STM32H5_UART8) -# undef CONFIG_STM32H5_UART8_SERIALDRIVER -# undef CONFIG_STM32H5_UART8_1WIREDRIVER +#if !defined(CONFIG_STM32_UART8) +# undef CONFIG_STM32_UART8_SERIALDRIVER +# undef CONFIG_STM32_UART8_1WIREDRIVER #endif -#if !defined(CONFIG_STM32H5_UART9) -# undef CONFIG_STM32H5_UART9_SERIALDRIVER -# undef CONFIG_STM32H5_UART9_1WIREDRIVER +#if !defined(CONFIG_STM32_UART9) +# undef CONFIG_STM32_UART9_SERIALDRIVER +# undef CONFIG_STM32_UART9_1WIREDRIVER #endif -#if !defined(CONFIG_STM32H5_USART10) -# undef CONFIG_STM32H5_USART10_SERIALDRIVER -# undef CONFIG_STM32H5_USART10_1WIREDRIVER +#if !defined(CONFIG_STM32_USART10) +# undef CONFIG_STM32_USART10_SERIALDRIVER +# undef CONFIG_STM32_USART10_1WIREDRIVER #endif -#if !defined(CONFIG_STM32H5_USART11) -# undef CONFIG_STM32H5_USART11_SERIALDRIVER -# undef CONFIG_STM32H5_USART11_1WIREDRIVER +#if !defined(CONFIG_STM32_USART11) +# undef CONFIG_STM32_USART11_SERIALDRIVER +# undef CONFIG_STM32_USART11_1WIREDRIVER #endif -#if !defined(CONFIG_STM32H5_UART12) -# undef CONFIG_STM32H5_UART12_SERIALDRIVER -# undef CONFIG_STM32H5_UART12_1WIREDRIVER +#if !defined(CONFIG_STM32_UART12) +# undef CONFIG_STM32_UART12_SERIALDRIVER +# undef CONFIG_STM32_UART12_1WIREDRIVER #endif /* Is there a USART enabled? */ -#if defined(CONFIG_STM32H5_LPUART1) || defined(CONFIG_STM32H5_USART1) || \ - defined(CONFIG_STM32H5_USART2) || defined(CONFIG_STM32H5_USART3) || \ - defined(CONFIG_STM32H5_UART4) || defined(CONFIG_STM32H5_UART5) || \ - defined(CONFIG_STM32H5_USART6) || defined(CONFIG_STM32H5_UART7) || \ - defined(CONFIG_STM32H5_UART8) || defined(CONFIG_STM32H5_UART9) || \ - defined(CONFIG_STM32H5_USART10) || defined(CONFIG_STM32H5_USART11) || \ - defined(CONFIG_STM32H5_USART12) +#if defined(CONFIG_STM32_LPUART1) || defined(CONFIG_STM32_USART1) || \ + defined(CONFIG_STM32_USART2) || defined(CONFIG_STM32_USART3) || \ + defined(CONFIG_STM32_UART4) || defined(CONFIG_STM32_UART5) || \ + defined(CONFIG_STM32_USART6) || defined(CONFIG_STM32_UART7) || \ + defined(CONFIG_STM32_UART8) || defined(CONFIG_STM32_UART9) || \ + defined(CONFIG_STM32_USART10) || defined(CONFIG_STM32_USART11) || \ + defined(CONFIG_STM32_USART12) # define HAVE_UART 1 #endif /* Is there a serial console? */ -#if defined(CONFIG_LPUART1_SERIAL_CONSOLE) && defined(CONFIG_STM32H5_LPUART1_SERIALDRIVER) +#if defined(CONFIG_LPUART1_SERIAL_CONSOLE) && defined(CONFIG_STM32_LPUART1_SERIALDRIVER) # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE @@ -170,7 +170,7 @@ # undef CONFIG_UART12_SERIAL_CONSOLE # define CONSOLE_UART 1 # define HAVE_CONSOLE 1 -#elif defined(CONFIG_USART1_SERIAL_CONSOLE) && defined(CONFIG_STM32H5_USART1_SERIALDRIVER) +#elif defined(CONFIG_USART1_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART1_SERIALDRIVER) # undef CONFIG_LPUART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE @@ -185,7 +185,7 @@ # undef CONFIG_UART12_SERIAL_CONSOLE # define CONSOLE_UART 2 # define HAVE_CONSOLE 1 -#elif defined(CONFIG_USART2_SERIAL_CONSOLE) && defined(CONFIG_STM32H5_USART2_SERIALDRIVER) +#elif defined(CONFIG_USART2_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART2_SERIALDRIVER) # undef CONFIG_LPUART1_SERIAL_CONSOLE # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE @@ -200,7 +200,7 @@ # undef CONFIG_UART12_SERIAL_CONSOLE # define CONSOLE_UART 3 # define HAVE_CONSOLE 1 -#elif defined(CONFIG_USART3_SERIAL_CONSOLE) && defined(CONFIG_STM32H5_USART3_SERIALDRIVER) +#elif defined(CONFIG_USART3_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART3_SERIALDRIVER) # undef CONFIG_LPUART1_SERIAL_CONSOLE # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE @@ -215,7 +215,7 @@ # undef CONFIG_UART12_SERIAL_CONSOLE # define CONSOLE_UART 4 # define HAVE_CONSOLE 1 -#elif defined(CONFIG_UART4_SERIAL_CONSOLE) && defined(CONFIG_STM32H5_UART4_SERIALDRIVER) +#elif defined(CONFIG_UART4_SERIAL_CONSOLE) && defined(CONFIG_STM32_UART4_SERIALDRIVER) # undef CONFIG_LPUART1_SERIAL_CONSOLE # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE @@ -230,7 +230,7 @@ # undef CONFIG_UART12_SERIAL_CONSOLE # define CONSOLE_UART 5 # define HAVE_CONSOLE 1 -#elif defined(CONFIG_UART5_SERIAL_CONSOLE) && defined(CONFIG_STM32H5_UART5_SERIALDRIVER) +#elif defined(CONFIG_UART5_SERIAL_CONSOLE) && defined(CONFIG_STM32_UART5_SERIALDRIVER) # undef CONFIG_LPUART1_SERIAL_CONSOLE # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE @@ -245,7 +245,7 @@ # undef CONFIG_UART12_SERIAL_CONSOLE # define CONSOLE_UART 6 # define HAVE_CONSOLE 1 -#elif defined(CONFIG_USART6_SERIAL_CONSOLE) && defined(CONFIG_STM32H5_USART6_SERIALDRIVER) +#elif defined(CONFIG_USART6_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART6_SERIALDRIVER) # undef CONFIG_LPUART1_SERIAL_CONSOLE # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE @@ -260,7 +260,7 @@ # undef CONFIG_UART12_SERIAL_CONSOLE # define CONSOLE_UART 7 # define HAVE_CONSOLE 1 -#elif defined(CONFIG_UART7_SERIAL_CONSOLE) && defined(CONFIG_STM32H5_UART7_SERIALDRIVER) +#elif defined(CONFIG_UART7_SERIAL_CONSOLE) && defined(CONFIG_STM32_UART7_SERIALDRIVER) # undef CONFIG_LPUART1_SERIAL_CONSOLE # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE @@ -275,7 +275,7 @@ # undef CONFIG_UART12_SERIAL_CONSOLE # define CONSOLE_UART 8 # define HAVE_CONSOLE 1 -#elif defined(CONFIG_UART8_SERIAL_CONSOLE) && defined(CONFIG_STM32H5_UART8_SERIALDRIVER) +#elif defined(CONFIG_UART8_SERIAL_CONSOLE) && defined(CONFIG_STM32_UART8_SERIALDRIVER) # undef CONFIG_LPUART1_SERIAL_CONSOLE # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE @@ -290,7 +290,7 @@ # undef CONFIG_UART12_SERIAL_CONSOLE # define CONSOLE_UART 9 # define HAVE_CONSOLE 1 -#elif defined(CONFIG_UART9_SERIAL_CONSOLE) && defined(CONFIG_STM32H5_UART9_SERIALDRIVER) +#elif defined(CONFIG_UART9_SERIAL_CONSOLE) && defined(CONFIG_STM32_UART9_SERIALDRIVER) # undef CONFIG_LPUART1_SERIAL_CONSOLE # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE @@ -305,7 +305,7 @@ # undef CONFIG_UART12_SERIAL_CONSOLE # define CONSOLE_UART 10 # define HAVE_CONSOLE 1 -#elif defined(CONFIG_USART10_SERIAL_CONSOLE) && defined(CONFIG_STM32H5_USART10_SERIALDRIVER) +#elif defined(CONFIG_USART10_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART10_SERIALDRIVER) # undef CONFIG_LPUART1_SERIAL_CONSOLE # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE @@ -320,7 +320,7 @@ # undef CONFIG_UART12_SERIAL_CONSOLE # define CONSOLE_UART 11 # define HAVE_CONSOLE 1 -#elif defined(CONFIG_USART11_SERIAL_CONSOLE) && defined(CONFIG_STM32H5_USART11_SERIALDRIVER) +#elif defined(CONFIG_USART11_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART11_SERIALDRIVER) # undef CONFIG_LPUART1_SERIAL_CONSOLE # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE @@ -335,7 +335,7 @@ # undef CONFIG_UART12_SERIAL_CONSOLE # define CONSOLE_UART 12 # define HAVE_CONSOLE 1 -#elif defined(CONFIG_UART12_SERIAL_CONSOLE) && defined(CONFIG_STM32H5_UART12_SERIALDRIVER) +#elif defined(CONFIG_UART12_SERIAL_CONSOLE) && defined(CONFIG_STM32_UART12_SERIALDRIVER) # undef CONFIG_LPUART1_SERIAL_CONSOLE # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE @@ -381,55 +381,55 @@ /* Disable the DMA configuration on all unused USARTs */ -#ifndef CONFIG_STM32H5_LPUART1_SERIALDRIVER +#ifndef CONFIG_STM32_LPUART1_SERIALDRIVER # undef CONFIG_LPUART1_RXDMA #endif -#ifndef CONFIG_STM32H5_USART1_SERIALDRIVER +#ifndef CONFIG_STM32_USART1_SERIALDRIVER # undef CONFIG_USART1_RXDMA #endif -#ifndef CONFIG_STM32H5_USART2_SERIALDRIVER +#ifndef CONFIG_STM32_USART2_SERIALDRIVER # undef CONFIG_USART2_RXDMA #endif -#ifndef CONFIG_STM32H5_USART3_SERIALDRIVER +#ifndef CONFIG_STM32_USART3_SERIALDRIVER # undef CONFIG_USART3_RXDMA #endif -#ifndef CONFIG_STM32H5_UART4_SERIALDRIVER +#ifndef CONFIG_STM32_UART4_SERIALDRIVER # undef CONFIG_UART4_RXDMA #endif -#ifndef CONFIG_STM32H5_UART5_SERIALDRIVER +#ifndef CONFIG_STM32_UART5_SERIALDRIVER # undef CONFIG_UART5_RXDMA #endif -#ifndef CONFIG_STM32H5_USART6_SERIALDRIVER +#ifndef CONFIG_STM32_USART6_SERIALDRIVER # undef CONFIG_USART6_RXDMA #endif -#ifndef CONFIG_STM32H5_UART7_SERIALDRIVER +#ifndef CONFIG_STM32_UART7_SERIALDRIVER # undef CONFIG_UART7_RXDMA #endif -#ifndef CONFIG_STM32H5_UART8_SERIALDRIVER +#ifndef CONFIG_STM32_UART8_SERIALDRIVER # undef CONFIG_UART8_RXDMA #endif -#ifndef CONFIG_STM32H5_UART9_SERIALDRIVER +#ifndef CONFIG_STM32_UART9_SERIALDRIVER # undef CONFIG_UART9_RXDMA #endif -#ifndef CONFIG_STM32H5_USART10_SERIALDRIVER +#ifndef CONFIG_STM32_USART10_SERIALDRIVER # undef CONFIG_USART10_RXDMA #endif -#ifndef CONFIG_STM32H5_USART11_SERIALDRIVER +#ifndef CONFIG_STM32_USART11_SERIALDRIVER # undef CONFIG_USART11_RXDMA #endif -#ifndef CONFIG_STM32H5_UART12_SERIALDRIVER +#ifndef CONFIG_STM32_UART12_SERIALDRIVER # undef CONFIG_UART12_RXDMA #endif @@ -480,31 +480,31 @@ /* Is DMA used on all (enabled) USARTs */ #define SERIAL_HAVE_ONLY_DMA 1 -#if defined(CONFIG_STM32H5_LPUART1_SERIALDRIVER) && !defined(CONFIG_LPUART1_RXDMA) +#if defined(CONFIG_STM32_LPUART1_SERIALDRIVER) && !defined(CONFIG_LPUART1_RXDMA) # undef SERIAL_HAVE_ONLY_DMA -#elif defined(CONFIG_STM32H5_USART1_SERIALDRIVER) && !defined(CONFIG_USART1_RXDMA) +#elif defined(CONFIG_STM32_USART1_SERIALDRIVER) && !defined(CONFIG_USART1_RXDMA) # undef SERIAL_HAVE_ONLY_DMA -#elif defined(CONFIG_STM32H5_USART2_SERIALDRIVER) && !defined(CONFIG_USART2_RXDMA) +#elif defined(CONFIG_STM32_USART2_SERIALDRIVER) && !defined(CONFIG_USART2_RXDMA) # undef SERIAL_HAVE_ONLY_DMA -#elif defined(CONFIG_STM32H5_USART3_SERIALDRIVER) && !defined(CONFIG_USART3_RXDMA) +#elif defined(CONFIG_STM32_USART3_SERIALDRIVER) && !defined(CONFIG_USART3_RXDMA) # undef SERIAL_HAVE_ONLY_DMA -#elif defined(CONFIG_STM32H5_UART4_SERIALDRIVER) && !defined(CONFIG_UART4_RXDMA) +#elif defined(CONFIG_STM32_UART4_SERIALDRIVER) && !defined(CONFIG_UART4_RXDMA) # undef SERIAL_HAVE_ONLY_DMA -#elif defined(CONFIG_STM32H5_UART5_SERIALDRIVER) && !defined(CONFIG_UART5_RXDMA) +#elif defined(CONFIG_STM32_UART5_SERIALDRIVER) && !defined(CONFIG_UART5_RXDMA) # undef SERIAL_HAVE_ONLY_DMA -#elif defined(CONFIG_STM32H5_USART6_SERIALDRIVER) && !defined(CONFIG_USART6_RXDMA) +#elif defined(CONFIG_STM32_USART6_SERIALDRIVER) && !defined(CONFIG_USART6_RXDMA) # undef SERIAL_HAVE_ONLY_DMA -#elif defined(CONFIG_STM32H5_UART7_SERIALDRIVER) && !defined(CONFIG_UART7_RXDMA) +#elif defined(CONFIG_STM32_UART7_SERIALDRIVER) && !defined(CONFIG_UART7_RXDMA) # undef SERIAL_HAVE_ONLY_DMA -#elif defined(CONFIG_STM32H5_UART8_SERIALDRIVER) && !defined(CONFIG_UART8_RXDMA) +#elif defined(CONFIG_STM32_UART8_SERIALDRIVER) && !defined(CONFIG_UART8_RXDMA) # undef SERIAL_HAVE_ONLY_DMA -#elif defined(CONFIG_STM32H5_UART9_SERIALDRIVER) && !defined(CONFIG_UART9_RXDMA) +#elif defined(CONFIG_STM32_UART9_SERIALDRIVER) && !defined(CONFIG_UART9_RXDMA) # undef SERIAL_HAVE_ONLY_DMA -#elif defined(CONFIG_STM32H5_USART10_SERIALDRIVER) && !defined(CONFIG_USART10_RXDMA) +#elif defined(CONFIG_STM32_USART10_SERIALDRIVER) && !defined(CONFIG_USART10_RXDMA) # undef SERIAL_HAVE_ONLY_DMA -#elif defined(CONFIG_STM32H5_USART11_SERIALDRIVER) && !defined(CONFIG_USART11_RXDMA) +#elif defined(CONFIG_STM32_USART11_SERIALDRIVER) && !defined(CONFIG_USART11_RXDMA) # undef SERIAL_HAVE_ONLY_DMA -#elif defined(CONFIG_STM32H5_UART12_SERIALDRIVER) && !defined(CONFIG_UART12_RXDMA) +#elif defined(CONFIG_STM32_UART12_SERIALDRIVER) && !defined(CONFIG_UART12_RXDMA) # undef SERIAL_HAVE_ONLY_DMA #endif @@ -572,4 +572,4 @@ void stm32_serial_dma_poll(void); #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_STC_STM32H5_STM32_UART_H */ +#endif /* __ARCH_ARM_SRC_STM32H5_STM32_UART_H */ diff --git a/arch/arm/src/stm32h5/stm32_uid.c b/arch/arm/src/stm32h5/stm32_uid.c deleted file mode 100644 index bda001d2760b6..0000000000000 --- a/arch/arm/src/stm32h5/stm32_uid.c +++ /dev/null @@ -1,66 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32h5/stm32_uid.c - * - * Copyright (C) 2015 Marawan Ragab. All rights reserved. - * Authors: Marawan Ragab - * David Sidrane - * Modified for STM32H5 by Tyler Bennett - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "hardware/stm32_memorymap.h" - -#include "stm32_uid.h" - -#ifdef STM32_SYSMEM_UID - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -void stm32_get_uniqueid(uint8_t uniqueid[12]) -{ - int i; - uint32_t *uid = (uint32_t *) uniqueid; - - for (i = 0; i < 3; i++) - { - *uid = *((uint32_t *)(STM32_SYSMEM_UID) + i); - uid++; - } -} - -#endif /* STM32_SYSMEM_UID */ diff --git a/arch/arm/src/stm32h5/stm32_uid.h b/arch/arm/src/stm32h5/stm32_uid.h deleted file mode 100644 index d63e07e6c9087..0000000000000 --- a/arch/arm/src/stm32h5/stm32_uid.h +++ /dev/null @@ -1,53 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32h5/stm32_uid.h - * - * Copyright (C) 2015 Marawan Ragab. All rights reserved. - * Authors: Marawan Ragab - * David Sidrane - * Modified for STM32H5 by Tyler Bennett - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32H5_STM32_UID_H -#define __ARCH_ARM_SRC_STM32H5_STM32_UID_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -void stm32_get_uniqueid(uint8_t uniqueid[12]); - -#endif /* __ARCH_ARM_SRC_STM32H5_STM32_UID_H */ \ No newline at end of file diff --git a/arch/arm/src/stm32h5/stm32_usbdrdhost.c b/arch/arm/src/stm32h5/stm32_usbdrdhost.c index 46fb168b718d3..1333ef56ae551 100644 --- a/arch/arm/src/stm32h5/stm32_usbdrdhost.c +++ b/arch/arm/src/stm32h5/stm32_usbdrdhost.c @@ -62,7 +62,7 @@ #include "hardware/stm32h5xxx_pwr.h" #include "stm32_usbdrdhost.h" -#if defined(CONFIG_USBHOST) && defined(CONFIG_STM32H5_USBFS_HOST) +#if defined(CONFIG_USBHOST) && defined(CONFIG_STM32_USBFS_HOST) /**************************************************************************** * Pre-processor Definitions @@ -70,42 +70,42 @@ /* Configuration */ -#ifndef CONFIG_STM32H5_USBDRD_NCHANNELS -# define CONFIG_STM32H5_USBDRD_NCHANNELS 8 +#ifndef CONFIG_STM32_USBDRD_NCHANNELS +# define CONFIG_STM32_USBDRD_NCHANNELS 8 #endif -#ifndef CONFIG_STM32H5_USBDRD_DESCSIZE -# define CONFIG_STM32H5_USBDRD_DESCSIZE 128 +#ifndef CONFIG_STM32_USBDRD_DESCSIZE +# define CONFIG_STM32_USBDRD_DESCSIZE 128 #endif -#ifndef CONFIG_STM32H5_USBDRD_TRANSFER_TIMEOUT -# define CONFIG_STM32H5_USBDRD_TRANSFER_TIMEOUT 5000 +#ifndef CONFIG_STM32_USBDRD_TRANSFER_TIMEOUT +# define CONFIG_STM32_USBDRD_TRANSFER_TIMEOUT 5000 #endif /* Hardware definitions */ -#define STM32H5_NHOST_CHANNELS CONFIG_STM32H5_USBDRD_NCHANNELS -#define STM32H5_EP0_MAX_PACKET_SIZE 64 -#define STM32H5_RETRY_COUNT 3 /* Control transfer retries */ +#define STM32_NHOST_CHANNELS CONFIG_STM32_USBDRD_NCHANNELS +#define STM32_EP0_MAX_PACKET_SIZE 64 +#define STM32_RETRY_COUNT 3 /* Control transfer retries */ /* PMA Buffer allocation (fixed-size bitmap allocator) */ -#define STM32H5_PMA_BUFFER_SIZE 64 /* Fixed buffer size (bytes) */ -#define STM32H5_PMA_NBUFFERS 30 /* Total allocatable buffers */ -#define STM32H5_PMA_BUFFER_ALLSET 0x3fffffff /* All 30 buffers available */ -#define STM32H5_PMA_BUFFER_BIT(bn) (1U << (bn)) -#define STM32H5_PMA_BUFNO2ADDR(bn) (USB_DRD_PMA_START_ADDR + ((bn) * STM32H5_PMA_BUFFER_SIZE)) -#define STM32H5_PMA_BUFFER_NONE 0xFF /* Invalid buffer number */ +#define STM32_PMA_BUFFER_SIZE 64 /* Fixed buffer size (bytes) */ +#define STM32_PMA_NBUFFERS 30 /* Total allocatable buffers */ +#define STM32_PMA_BUFFER_ALLSET 0x3fffffff /* All 30 buffers available */ +#define STM32_PMA_BUFFER_BIT(bn) (1U << (bn)) +#define STM32_PMA_BUFNO2ADDR(bn) (USB_DRD_PMA_START_ADDR + ((bn) * STM32_PMA_BUFFER_SIZE)) +#define STM32_PMA_BUFFER_NONE 0xFF /* Invalid buffer number */ /* Delays */ -#define STM32H5_DATANAK_DELAY SEC2TICK(5) -#define STM32H5_RESET_DELAY 100 /* ms */ +#define STM32_DATANAK_DELAY SEC2TICK(5) +#define STM32_RESET_DELAY 100 /* ms */ /* USB DRD base addresses */ -#define STM32H5_USBDRD_BASE STM32_USB_FS_BASE -#define STM32H5_USBDRD_PMA_BASE STM32_USB_FS_RAM_BASE +#define STM32_USBDRD_BASE STM32_USB_FS_BASE +#define STM32_USBDRD_PMA_BASE STM32_USB_FS_RAM_BASE /* Register access helpers */ @@ -115,7 +115,7 @@ /* Channel register access */ -#define STM32H5_USB_CHEP(n) (STM32H5_USBDRD_BASE + ((n) << 2)) +#define STM32_USB_CHEP(n) (STM32_USBDRD_BASE + ((n) << 2)) /* Host channel data PID values */ @@ -227,7 +227,7 @@ struct stm32_usbhost_s /* Host channels */ - struct stm32_chan_s chan[STM32H5_NHOST_CHANNELS]; + struct stm32_chan_s chan[STM32_NHOST_CHANNELS]; /* PMA allocation */ @@ -416,7 +416,7 @@ static void stm32_pma_write(const uint8_t *buffer, uint16_t pmaaddr, uint32_t count; uint32_t remaining; - pdwval = (volatile uint32_t *)(STM32H5_USBDRD_PMA_BASE + pmaaddr); + pdwval = (volatile uint32_t *)(STM32_USBDRD_PMA_BASE + pmaaddr); count = nbytes >> 2; /* Number of 32-bit words */ remaining = nbytes & 0x03; /* Remaining bytes */ @@ -466,7 +466,7 @@ static void stm32_pma_read(uint8_t *buffer, uint16_t pmaaddr, UP_DSB(); - pdwval = (volatile uint32_t *)(STM32H5_USBDRD_PMA_BASE + pmaaddr); + pdwval = (volatile uint32_t *)(STM32_USBDRD_PMA_BASE + pmaaddr); count = nbytes >> 2; remaining = nbytes & 0x03; @@ -508,9 +508,9 @@ static int stm32_pma_alloc_buffer(struct stm32_usbhost_s *priv) flags = enter_critical_section(); - for (bufndx = 0; bufndx < STM32H5_PMA_NBUFFERS; bufndx++) + for (bufndx = 0; bufndx < STM32_PMA_NBUFFERS; bufndx++) { - uint32_t bit = STM32H5_PMA_BUFFER_BIT(bufndx); + uint32_t bit = STM32_PMA_BUFFER_BIT(bufndx); if ((priv->pma_bufavail & bit) != 0) { priv->pma_bufavail &= ~bit; /* Mark allocated */ @@ -524,12 +524,12 @@ static int stm32_pma_alloc_buffer(struct stm32_usbhost_s *priv) if (bufno >= 0) { uinfo("PMA buffer allocated: bufno=%d addr=0x%04x\n", - bufno, STM32H5_PMA_BUFNO2ADDR(bufno)); + bufno, STM32_PMA_BUFNO2ADDR(bufno)); } else { uerr("ERROR: PMA buffer allocation failed, all %d buffers in use\n", - STM32H5_PMA_NBUFFERS); + STM32_PMA_NBUFFERS); } return bufno; @@ -548,14 +548,14 @@ static void stm32_pma_free_buffer(struct stm32_usbhost_s *priv, { irqstate_t flags; - DEBUGASSERT(bufno < STM32H5_PMA_NBUFFERS); + DEBUGASSERT(bufno < STM32_PMA_NBUFFERS); flags = enter_critical_section(); - priv->pma_bufavail |= STM32H5_PMA_BUFFER_BIT(bufno); /* Mark available */ + priv->pma_bufavail |= STM32_PMA_BUFFER_BIT(bufno); /* Mark available */ leave_critical_section(flags); uinfo("PMA buffer freed: bufno=%d addr=0x%04x\n", - bufno, STM32H5_PMA_BUFNO2ADDR(bufno)); + bufno, STM32_PMA_BUFNO2ADDR(bufno)); } /**************************************************************************** @@ -570,7 +570,7 @@ static int stm32_chan_alloc(struct stm32_usbhost_s *priv) { int chidx; - for (chidx = 0; chidx < STM32H5_NHOST_CHANNELS; chidx++) + for (chidx = 0; chidx < STM32_NHOST_CHANNELS; chidx++) { if (!priv->chan[chidx].inuse) { @@ -582,7 +582,7 @@ static int stm32_chan_alloc(struct stm32_usbhost_s *priv) priv->chan[chidx].inuse = true; priv->chan[chidx].pmabufno = (uint8_t)bufno; - priv->chan[chidx].pmaaddr = STM32H5_PMA_BUFNO2ADDR(bufno); + priv->chan[chidx].pmaaddr = STM32_PMA_BUFNO2ADDR(bufno); uinfo("Channel allocated: chidx=%d\n", chidx); return chidx; } @@ -604,18 +604,18 @@ static inline void stm32_chan_free(struct stm32_usbhost_s *priv, { struct stm32_chan_s *chan; - DEBUGASSERT((unsigned)chidx < STM32H5_NHOST_CHANNELS); + DEBUGASSERT((unsigned)chidx < STM32_NHOST_CHANNELS); chan = &priv->chan[chidx]; /* Free PMA buffer if allocated */ - if (chan->pmabufno != STM32H5_PMA_BUFFER_NONE) + if (chan->pmabufno != STM32_PMA_BUFFER_NONE) { stm32_set_chep_rx_status(priv, chidx, USB_CHEP_RX_STRX_DIS); stm32_set_chep_tx_status(priv, chidx, USB_CHEP_TX_STTX_DIS); stm32_pma_free_buffer(priv, chan->pmabufno); - chan->pmabufno = STM32H5_PMA_BUFFER_NONE; + chan->pmabufno = STM32_PMA_BUFFER_NONE; chan->pmaaddr = 0; uinfo("Channel freed: chidx=%d\n", chidx); } @@ -639,7 +639,7 @@ static void stm32_set_chep_tx_status(struct stm32_usbhost_s *priv, /* Status changes work by toggling the DTOG bits */ - regval = stm32_getreg(STM32H5_USB_CHEP(priv->chan[chidx].chidx)) + regval = stm32_getreg(STM32_USB_CHEP(priv->chan[chidx].chidx)) & USB_CHEP_TX_DTOGMASK; if (status & USB_CHEP_TX_DTOG1) { @@ -651,7 +651,7 @@ static void stm32_set_chep_tx_status(struct stm32_usbhost_s *priv, regval ^= USB_CHEP_TX_DTOG2; } - stm32_putreg(STM32H5_USB_CHEP(priv->chan[chidx].chidx), + stm32_putreg(STM32_USB_CHEP(priv->chan[chidx].chidx), regval | USB_CHEP_VTRX | USB_CHEP_VTTX); } @@ -671,7 +671,7 @@ static void stm32_set_chep_rx_status(struct stm32_usbhost_s *priv, /* Status changes work by toggling the DTOG bits */ - regval = stm32_getreg(STM32H5_USB_CHEP(priv->chan[chidx].chidx)) + regval = stm32_getreg(STM32_USB_CHEP(priv->chan[chidx].chidx)) & USB_CHEP_RX_DTOGMASK; if (status & USB_CHEP_RX_DTOG1) { @@ -683,7 +683,7 @@ static void stm32_set_chep_rx_status(struct stm32_usbhost_s *priv, regval ^= USB_CHEP_RX_DTOG2; } - stm32_putreg(STM32H5_USB_CHEP(priv->chan[chidx].chidx), + stm32_putreg(STM32_USB_CHEP(priv->chan[chidx].chidx), regval | USB_CHEP_VTRX | USB_CHEP_VTTX); } @@ -701,7 +701,7 @@ static inline void stm32_chan_freeall(struct stm32_usbhost_s *priv) /* Free all host channels */ - for (chidx = 0; chidx < STM32H5_NHOST_CHANNELS; chidx++) + for (chidx = 0; chidx < STM32_NHOST_CHANNELS; chidx++) { if (priv->chan[chidx].inuse) { @@ -748,7 +748,7 @@ static void stm32_chan_configure(struct stm32_usbhost_s *priv, /* Read current register value and mask toggleable bits */ - regval = stm32_getreg(STM32H5_USB_CHEP(chidx)) & USB_CH_T_MASK; + regval = stm32_getreg(STM32_USB_CHEP(chidx)) & USB_CH_T_MASK; /* Set endpoint type */ @@ -772,7 +772,7 @@ static void stm32_chan_configure(struct stm32_usbhost_s *priv, /* Write the channel register with VT bits preserved */ - stm32_putreg(STM32H5_USB_CHEP(chidx), + stm32_putreg(STM32_USB_CHEP(chidx), regval | USB_CHEP_VTRX | USB_CHEP_VTTX); } @@ -944,7 +944,7 @@ static int stm32_ctrlchan_alloc(struct stm32_usbhost_s *priv, chan->eptype = USB_EP_ATTR_XFER_CONTROL; chan->funcaddr = funcaddr; chan->speed = speed; - chan->maxpacket = STM32H5_EP0_MAX_PACKET_SIZE; + chan->maxpacket = STM32_EP0_MAX_PACKET_SIZE; chan->indata1 = false; chan->outdata1 = false; @@ -956,7 +956,7 @@ static int stm32_ctrlchan_alloc(struct stm32_usbhost_s *priv, chan->eptype = USB_EP_ATTR_XFER_CONTROL; chan->funcaddr = funcaddr; chan->speed = speed; - chan->maxpacket = STM32H5_EP0_MAX_PACKET_SIZE; + chan->maxpacket = STM32_EP0_MAX_PACKET_SIZE; chan->indata1 = false; chan->outdata1 = false; @@ -1092,7 +1092,7 @@ static void stm32_transfer_start(struct stm32_usbhost_s *priv, bdval |= (nblocks << USB_PMA_RXBD_NUM_BLOCK_SHIFT); } - pbd = (volatile uint32_t *)(STM32H5_USBDRD_PMA_BASE + + pbd = (volatile uint32_t *)(STM32_USBDRD_PMA_BASE + USB_PMA_RXBD_OFFSET(chidx)); *pbd = bdval; @@ -1104,7 +1104,7 @@ static void stm32_transfer_start(struct stm32_usbhost_s *priv, /* Clear data toggle if starting new transfer */ - regval = stm32_getreg(STM32H5_USB_CHEP(chidx)); + regval = stm32_getreg(STM32_USB_CHEP(chidx)); if ((regval & USB_CHEP_DTOG_RX) != 0) { if (!chan->indata1) @@ -1113,7 +1113,7 @@ static void stm32_transfer_start(struct stm32_usbhost_s *priv, regval = (regval & USB_CHEP_REG_MASK) | USB_CHEP_VTRX | USB_CHEP_VTTX | USB_CHEP_DTOG_RX; - stm32_putreg(STM32H5_USB_CHEP(chidx), regval); + stm32_putreg(STM32_USB_CHEP(chidx), regval); } } else @@ -1124,7 +1124,7 @@ static void stm32_transfer_start(struct stm32_usbhost_s *priv, regval = (regval & USB_CHEP_REG_MASK) | USB_CHEP_VTRX | USB_CHEP_VTTX | USB_CHEP_DTOG_RX; - stm32_putreg(STM32H5_USB_CHEP(chidx), regval); + stm32_putreg(STM32_USB_CHEP(chidx), regval); } } @@ -1146,7 +1146,7 @@ static void stm32_transfer_start(struct stm32_usbhost_s *priv, bdval = chan->pmaaddr; /* chan->pmaaddr is already 4 byte aligned */ bdval |= ((uint32_t)len << USB_PMA_TXBD_COUNT_SHIFT); - pbd = (volatile uint32_t *)(STM32H5_USBDRD_PMA_BASE + + pbd = (volatile uint32_t *)(STM32_USBDRD_PMA_BASE + USB_PMA_TXBD_OFFSET(chidx)); *pbd = bdval; @@ -1154,8 +1154,8 @@ static void stm32_transfer_start(struct stm32_usbhost_s *priv, if (chan->pid == HC_PID_SETUP) { - regval = stm32_getreg(STM32H5_USB_CHEP(chidx)) & USB_CHEP_REG_MASK; - stm32_putreg(STM32H5_USB_CHEP(chidx), + regval = stm32_getreg(STM32_USB_CHEP(chidx)) & USB_CHEP_REG_MASK; + stm32_putreg(STM32_USB_CHEP(chidx), regval | USB_CHEP_SETUP | USB_CHEP_VTRX | USB_CHEP_VTTX); } @@ -1164,7 +1164,7 @@ static void stm32_transfer_start(struct stm32_usbhost_s *priv, * hardware auto-toggles after successful transmit) */ - regval = stm32_getreg(STM32H5_USB_CHEP(chidx)); + regval = stm32_getreg(STM32_USB_CHEP(chidx)); if ((regval & USB_CHEP_DTOG_TX) != 0) { if (!chan->outdata1) @@ -1173,7 +1173,7 @@ static void stm32_transfer_start(struct stm32_usbhost_s *priv, regval = (regval & USB_CHEP_REG_MASK) | USB_CHEP_VTRX | USB_CHEP_VTTX | USB_CHEP_DTOG_TX; - stm32_putreg(STM32H5_USB_CHEP(chidx), regval); + stm32_putreg(STM32_USB_CHEP(chidx), regval); } } else @@ -1184,7 +1184,7 @@ static void stm32_transfer_start(struct stm32_usbhost_s *priv, regval = (regval & USB_CHEP_REG_MASK) | USB_CHEP_VTRX | USB_CHEP_VTTX | USB_CHEP_DTOG_TX; - stm32_putreg(STM32H5_USB_CHEP(chidx), regval); + stm32_putreg(STM32_USB_CHEP(chidx), regval); } } @@ -1225,7 +1225,7 @@ static int stm32_ctrl_sendsetup(struct stm32_usbhost_s *priv, } stm32_transfer_start(priv, ep0->outndx); - return stm32_chan_wait(priv, chan, CONFIG_STM32H5_USBDRD_TRANSFER_TIMEOUT); + return stm32_chan_wait(priv, chan, CONFIG_STM32_USBDRD_TRANSFER_TIMEOUT); } /**************************************************************************** @@ -1257,7 +1257,7 @@ static int stm32_ctrl_senddata(struct stm32_usbhost_s *priv, } stm32_transfer_start(priv, ep0->outndx); - return stm32_chan_wait(priv, chan, CONFIG_STM32H5_USBDRD_TRANSFER_TIMEOUT); + return stm32_chan_wait(priv, chan, CONFIG_STM32_USBDRD_TRANSFER_TIMEOUT); } /**************************************************************************** @@ -1289,7 +1289,7 @@ static int stm32_ctrl_recvdata(struct stm32_usbhost_s *priv, } stm32_transfer_start(priv, ep0->inndx); - return stm32_chan_wait(priv, chan, CONFIG_STM32H5_USBDRD_TRANSFER_TIMEOUT); + return stm32_chan_wait(priv, chan, CONFIG_STM32_USBDRD_TRANSFER_TIMEOUT); } /**************************************************************************** @@ -1321,7 +1321,7 @@ static ssize_t stm32_in_transfer(struct stm32_usbhost_s *priv, stm32_transfer_start(priv, chidx); - ret = stm32_chan_wait(priv, chan, CONFIG_STM32H5_USBDRD_TRANSFER_TIMEOUT); + ret = stm32_chan_wait(priv, chan, CONFIG_STM32_USBDRD_TRANSFER_TIMEOUT); if (ret < 0) { return ret; @@ -1359,7 +1359,7 @@ static ssize_t stm32_out_transfer(struct stm32_usbhost_s *priv, stm32_transfer_start(priv, chidx); - ret = stm32_chan_wait(priv, chan, CONFIG_STM32H5_USBDRD_TRANSFER_TIMEOUT); + ret = stm32_chan_wait(priv, chan, CONFIG_STM32_USBDRD_TRANSFER_TIMEOUT); if (ret < 0) { return ret; @@ -1460,13 +1460,13 @@ static void stm32_gint_disconnected(struct stm32_usbhost_s *priv) static void stm32_hc_in_irq(struct stm32_usbhost_s *priv, int chidx) { struct stm32_chan_s *chan = &priv->chan[chidx]; - uint32_t chepval = stm32_getreg(STM32H5_USB_CHEP(chidx)); + uint32_t chepval = stm32_getreg(STM32_USB_CHEP(chidx)); uint32_t rx_status = chepval & USB_CHEP_RX_STRX_MASK; bool wakeup = false; if ((chepval & USB_CHEP_ERRRX) != 0) { - chepval = stm32_getreg(STM32H5_USB_CHEP(chidx)); + chepval = stm32_getreg(STM32_USB_CHEP(chidx)); uerr("ERRRX chidx=%d chepval=0x%08x rx_status=%d nak=%d\n", chidx, (unsigned int)chepval, (int)((chepval & USB_CHEP_RX_STRX_MASK) >> @@ -1479,7 +1479,7 @@ static void stm32_hc_in_irq(struct stm32_usbhost_s *priv, int chidx) chepval = (chepval & (0xffff7fff & USB_CHEP_REG_MASK) & ~USB_CHEP_ERRRX) | USB_CHEP_VTTX; - stm32_putreg(STM32H5_USB_CHEP(chidx), chepval); + stm32_putreg(STM32_USB_CHEP(chidx), chepval); chan->result = EIO; chan->chreason = CHREASON_TXERR; @@ -1500,7 +1500,7 @@ static void stm32_hc_in_irq(struct stm32_usbhost_s *priv, int chidx) uint16_t count; bool transfer_complete; - pbd = (volatile uint32_t *)(STM32H5_USBDRD_PMA_BASE + + pbd = (volatile uint32_t *)(STM32_USBDRD_PMA_BASE + USB_PMA_RXBD_OFFSET(chidx)); count = (*pbd >> USB_PMA_RXBD_COUNT_SHIFT) & 0x3ff; @@ -1546,10 +1546,10 @@ static void stm32_hc_in_irq(struct stm32_usbhost_s *priv, int chidx) * (toggle bit, write 1 keeps, write 0 clears) */ - chepval = stm32_getreg(STM32H5_USB_CHEP(chidx)); + chepval = stm32_getreg(STM32_USB_CHEP(chidx)); chepval = (chepval & (0xffff7fff & USB_CHEP_REG_MASK)) | USB_CHEP_VTTX; - stm32_putreg(STM32H5_USB_CHEP(chidx), chepval); + stm32_putreg(STM32_USB_CHEP(chidx), chepval); /* More data expected - reactivate channel for next packet */ @@ -1598,9 +1598,9 @@ static void stm32_hc_in_irq(struct stm32_usbhost_s *priv, int chidx) * (toggle bit, write 1 keeps, write 0 clears) */ - chepval = stm32_getreg(STM32H5_USB_CHEP(chidx)); + chepval = stm32_getreg(STM32_USB_CHEP(chidx)); chepval = (chepval & (0xffff7fff & USB_CHEP_REG_MASK)) | USB_CHEP_VTTX; - stm32_putreg(STM32H5_USB_CHEP(chidx), chepval); + stm32_putreg(STM32_USB_CHEP(chidx), chepval); if (wakeup) { @@ -1620,7 +1620,7 @@ static void stm32_hc_in_irq(struct stm32_usbhost_s *priv, int chidx) static void stm32_hc_out_irq(struct stm32_usbhost_s *priv, int chidx) { struct stm32_chan_s *chan = &priv->chan[chidx]; - uint32_t chepval = stm32_getreg(STM32H5_USB_CHEP(chidx)); + uint32_t chepval = stm32_getreg(STM32_USB_CHEP(chidx)); uint32_t tx_status = chepval & USB_CHEP_TX_STTX_MASK; bool wakeup = false; @@ -1630,10 +1630,10 @@ static void stm32_hc_out_irq(struct stm32_usbhost_s *priv, int chidx) * write 1 to VTRX/VTTX to preserve */ - chepval = stm32_getreg(STM32H5_USB_CHEP(chidx)); + chepval = stm32_getreg(STM32_USB_CHEP(chidx)); chepval = (chepval & USB_CHEP_REG_MASK & ~USB_CHEP_ERRTX) | USB_CHEP_VTRX | USB_CHEP_VTTX; - stm32_putreg(STM32H5_USB_CHEP(chidx), chepval); + stm32_putreg(STM32_USB_CHEP(chidx), chepval); chan->result = EIO; chan->chreason = CHREASON_TXERR; @@ -1699,10 +1699,10 @@ static void stm32_hc_out_irq(struct stm32_usbhost_s *priv, int chidx) if ((chepval & USB_CHEP_NAK) != 0) { - chepval = stm32_getreg(STM32H5_USB_CHEP(chidx)); + chepval = stm32_getreg(STM32_USB_CHEP(chidx)); chepval = (chepval & USB_CHEP_REG_MASK & ~USB_CHEP_NAK) | USB_CHEP_VTRX | USB_CHEP_VTTX; - stm32_putreg(STM32H5_USB_CHEP(chidx), chepval); + stm32_putreg(STM32_USB_CHEP(chidx), chepval); } if (!chan->waiter && !chan->callback) @@ -1728,9 +1728,9 @@ static void stm32_hc_out_irq(struct stm32_usbhost_s *priv, int chidx) /* Clear VTTX by writing 0 to it */ - chepval = stm32_getreg(STM32H5_USB_CHEP(chidx)); + chepval = stm32_getreg(STM32_USB_CHEP(chidx)); chepval = (chepval & (0xffffff7f & USB_CHEP_REG_MASK)) | USB_CHEP_VTRX; - stm32_putreg(STM32H5_USB_CHEP(chidx), chepval); + stm32_putreg(STM32_USB_CHEP(chidx), chepval); if (wakeup) { @@ -2132,11 +2132,11 @@ static int stm32_epfree(struct usbhost_driver_s *drvr, usbhost_ep_t ep) } /* A single channel is represent by an index in the range of 0 to - * STM32H5_NHOST_CHANNELS. Otherwise, the ep must be a pointer to + * STM32_NHOST_CHANNELS. Otherwise, the ep must be a pointer to * an allocated control endpoint structure. */ - if ((uintptr_t)ep < STM32H5_NHOST_CHANNELS) + if ((uintptr_t)ep < STM32_NHOST_CHANNELS) { /* Halt the channel and mark the channel available */ @@ -2176,14 +2176,14 @@ static int stm32_alloc(struct usbhost_driver_s *drvr, DEBUGASSERT(drvr && buffer && maxlen); - alloc = kmm_malloc(CONFIG_STM32H5_USBDRD_DESCSIZE); + alloc = kmm_malloc(CONFIG_STM32_USBDRD_DESCSIZE); if (!alloc) { return -ENOMEM; } *buffer = alloc; - *maxlen = CONFIG_STM32H5_USBDRD_DESCSIZE; + *maxlen = CONFIG_STM32_USBDRD_DESCSIZE; return OK; } @@ -2275,7 +2275,7 @@ static int stm32_ctrlin(struct usbhost_driver_s *drvr, usbhost_ep_t ep0, return ret; } - for (retries = 0; retries < STM32H5_RETRY_COUNT; retries++) + for (retries = 0; retries < STM32_RETRY_COUNT; retries++) { /* Send SETUP */ @@ -2351,7 +2351,7 @@ static int stm32_ctrlout(struct usbhost_driver_s *drvr, usbhost_ep_t ep0, return ret; } - for (retries = 0; retries < STM32H5_RETRY_COUNT; retries++) + for (retries = 0; retries < STM32_RETRY_COUNT; retries++) { /* Send SETUP */ @@ -2409,7 +2409,7 @@ static ssize_t stm32_transfer(struct usbhost_driver_s *drvr, ssize_t nbytes; int ret; - DEBUGASSERT(priv && buffer && chidx < STM32H5_NHOST_CHANNELS); + DEBUGASSERT(priv && buffer && chidx < STM32_NHOST_CHANNELS); ret = nxmutex_lock(&priv->lock); if (ret < 0) @@ -2461,7 +2461,7 @@ static int stm32_asynch(struct usbhost_driver_s *drvr, usbhost_ep_t ep, struct stm32_chan_s *chan; int ret; - DEBUGASSERT(priv && buffer && chidx < STM32H5_NHOST_CHANNELS); + DEBUGASSERT(priv && buffer && chidx < STM32_NHOST_CHANNELS); ret = nxmutex_lock(&priv->lock); if (ret < 0) @@ -2499,7 +2499,7 @@ static int stm32_cancel(struct usbhost_driver_s *drvr, usbhost_ep_t ep) struct stm32_chan_s *chan; irqstate_t flags; - DEBUGASSERT(priv && chidx < STM32H5_NHOST_CHANNELS); + DEBUGASSERT(priv && chidx < STM32_NHOST_CHANNELS); chan = &priv->chan[chidx]; @@ -2595,7 +2595,7 @@ static void stm32_portreset(struct stm32_usbhost_s *priv) /* Wait for reset */ - nxsched_usleep(STM32H5_RESET_DELAY * 1000); + nxsched_usleep(STM32_RESET_DELAY * 1000); /* Release reset */ @@ -2722,15 +2722,15 @@ static void stm32_sw_initialize(struct stm32_usbhost_s *priv) /* Initialize PMA allocation - all buffers available */ - priv->pma_bufavail = STM32H5_PMA_BUFFER_ALLSET; + priv->pma_bufavail = STM32_PMA_BUFFER_ALLSET; /* Initialize channels */ - for (i = 0; i < STM32H5_NHOST_CHANNELS; i++) + for (i = 0; i < STM32_NHOST_CHANNELS; i++) { priv->chan[i].chidx = i; priv->chan[i].inuse = false; - priv->chan[i].pmabufno = STM32H5_PMA_BUFFER_NONE; + priv->chan[i].pmabufno = STM32_PMA_BUFFER_NONE; nxsem_init(&priv->chan[i].waitsem, 0, 0); } } @@ -2829,7 +2829,7 @@ static int stm32_hw_initialize(struct stm32_usbhost_s *priv) /* Enable VBUS drive */ - stm32h5_usbhost_vbusdrive(0, true); + stm32_usbdrdhost_vbusdrive(0, true); uinfo("USB Host initialized\n"); @@ -2841,14 +2841,14 @@ static int stm32_hw_initialize(struct stm32_usbhost_s *priv) ****************************************************************************/ /**************************************************************************** - * Name: stm32h5_usbhost_initialize + * Name: stm32_usbdrdhost_initialize * * Description: * Initialize USB host controller * ****************************************************************************/ -struct usbhost_connection_s *stm32h5_usbhost_initialize(void) +struct usbhost_connection_s *stm32_usbdrdhost_initialize(void) { struct stm32_usbhost_s *priv = &g_usbhost; int ret; @@ -2872,7 +2872,7 @@ struct usbhost_connection_s *stm32h5_usbhost_initialize(void) } /**************************************************************************** - * Name: stm32_usbhost_vbusdrive + * Name: stm32_usbdrdhost_vbusdrive * * Description: * Control VBUS power @@ -2881,7 +2881,7 @@ struct usbhost_connection_s *stm32h5_usbhost_initialize(void) ****************************************************************************/ __attribute__((weak)) -void stm32_usbhost_vbusdrive(int port, bool enable) +void stm32_usbdrdhost_vbusdrive(int port, bool enable) { /* Default implementation - do nothing. * Board-specific code should override this to control VBUS power. @@ -2890,4 +2890,4 @@ void stm32_usbhost_vbusdrive(int port, bool enable) uinfo("VBUS drive port=%d enable=%d (default - no-op)\n", port, enable); } -#endif /* CONFIG_USBHOST && CONFIG_STM32H5_USBFS_HOST */ +#endif /* CONFIG_USBHOST && CONFIG_STM32_USBFS_HOST */ diff --git a/arch/arm/src/stm32h5/stm32_usbdrdhost.h b/arch/arm/src/stm32h5/stm32_usbdrdhost.h index f96b56e0cb7f7..a3f07b1be6793 100644 --- a/arch/arm/src/stm32h5/stm32_usbdrdhost.h +++ b/arch/arm/src/stm32h5/stm32_usbdrdhost.h @@ -39,20 +39,20 @@ /* Pre-requisites */ -#if !defined(CONFIG_STM32H5_USBFS_HOST) -# error "CONFIG_STM32H5_USBFS_HOST is required" +#if !defined(CONFIG_STM32_USBFS_HOST) +# error "CONFIG_STM32_USBFS_HOST is required" #endif /* USB DRD Host Driver Configuration */ -#ifndef CONFIG_STM32H5_USBDRD_NCHANNELS -# define CONFIG_STM32H5_USBDRD_NCHANNELS 8 +#ifndef CONFIG_STM32_USBDRD_NCHANNELS +# define CONFIG_STM32_USBDRD_NCHANNELS 8 #endif /* Default descriptor buffer size */ -#ifndef CONFIG_STM32H5_USBDRD_DESCSIZE -# define CONFIG_STM32H5_USBDRD_DESCSIZE 128 +#ifndef CONFIG_STM32_USBDRD_DESCSIZE +# define CONFIG_STM32_USBDRD_DESCSIZE 128 #endif /**************************************************************************** @@ -63,7 +63,7 @@ * to the board-level USB host logic. */ -struct stm32h5_usbhost_connection_s +struct stm32_usbhost_connection_s { /* Wait for device connection/disconnection */ @@ -90,7 +90,7 @@ extern "C" ****************************************************************************/ /**************************************************************************** - * Name: stm32h5_usbhost_initialize + * Name: stm32_usbdrdhost_initialize * * Description: * Initialize USB host controller hardware. @@ -108,10 +108,10 @@ extern "C" * ****************************************************************************/ -struct usbhost_connection_s *stm32h5_usbhost_initialize(void); +struct usbhost_connection_s *stm32_usbdrdhost_initialize(void); /**************************************************************************** - * Name: stm32h5_usbhost_vbusdrive + * Name: stm32_usbdrdhost_vbusdrive * * Description: * Enable/disable VBUS power to the connected USB device. @@ -133,7 +133,7 @@ struct usbhost_connection_s *stm32h5_usbhost_initialize(void); * ****************************************************************************/ -void stm32h5_usbhost_vbusdrive(int port, bool enable); +void stm32_usbdrdhost_vbusdrive(int port, bool enable); #undef EXTERN #if defined(__cplusplus) diff --git a/arch/arm/src/stm32h5/stm32_usbfs.c b/arch/arm/src/stm32h5/stm32_usbfs.c index 2b44b01426674..c4a69deb44128 100644 --- a/arch/arm/src/stm32h5/stm32_usbfs.c +++ b/arch/arm/src/stm32h5/stm32_usbfs.c @@ -49,7 +49,7 @@ #include "stm32_gpio.h" #include "stm32_usbfs.h" -#if defined(CONFIG_STM32H5_USBFS) +#if defined(CONFIG_STM32_USBFS) /**************************************************************************** * Pre-processor Definitions @@ -70,7 +70,7 @@ */ #ifndef CONFIG_DEBUG_USB_INFO -# undef CONFIG_STM32H5_USBFS_REGDEBUG +# undef CONFIG_STM32_USBFS_REGDEBUG #endif /* Initial interrupt mask: Reset + Suspend + Correct Transfer */ @@ -345,7 +345,7 @@ struct stm32_usbdev_s /* Register operations ******************************************************/ -#ifdef CONFIG_STM32H5_USBFS_REGDEBUG +#ifdef CONFIG_STM32_USBFS_REGDEBUG static uint32_t stm32_getreg(uint32_t addr); static void stm32_putreg(uint16_t val, uint32_t addr); static void stm32_checksetup(void); @@ -609,7 +609,7 @@ const struct trace_msg_t g_usb_trace_strings_deverror[] = * Name: stm32_getreg ****************************************************************************/ -#ifdef CONFIG_STM32H5_USBFS_REGDEBUG +#ifdef CONFIG_STM32_USBFS_REGDEBUG static uint32_t stm32_getreg(uint32_t addr) { static uint32_t prevaddr = 0; @@ -668,7 +668,7 @@ static uint32_t stm32_getreg(uint32_t addr) * Name: stm32_putreg ****************************************************************************/ -#ifdef CONFIG_STM32H5_USBFS_REGDEBUG +#ifdef CONFIG_STM32_USBFS_REGDEBUG static void stm32_putreg(uint32_t val, uint32_t addr) { /* Show the register value being written */ @@ -685,7 +685,7 @@ static void stm32_putreg(uint32_t val, uint32_t addr) * Name: stm32_dumpep ****************************************************************************/ -#ifdef CONFIG_STM32H5_USBFS_REGDEBUG +#ifdef CONFIG_STM32_USBFS_REGDEBUG static void stm32_dumpep(int epno) { uint32_t addr; @@ -723,7 +723,7 @@ static void stm32_dumpep(int epno) * Name: stm32_checksetup ****************************************************************************/ -#ifdef CONFIG_STM32H5_USBFS_REGDEBUG +#ifdef CONFIG_STM32_USBFS_REGDEBUG static void stm32_checksetup(void) { uint32_t cfgr = getreg32(STM32_RCC_CFGR); @@ -3950,4 +3950,4 @@ int usbdev_unregister(struct usbdevclass_driver_s *driver) return OK; } -#endif /* CONFIG_STM32H5_USBFS */ +#endif /* CONFIG_STM32_USBFS */ diff --git a/arch/arm/src/stm32h5/stm32h563xx_flash.c b/arch/arm/src/stm32h5/stm32h563xx_flash.c index 3b2aebdcaff4d..f1ca7d5d97af6 100644 --- a/arch/arm/src/stm32h5/stm32h563xx_flash.c +++ b/arch/arm/src/stm32h5/stm32h563xx_flash.c @@ -58,45 +58,45 @@ #define FLASH_BLOCK_SIZE _K(8) #define FLASH_PAGE_SIZE 16 -#if !defined(CONFIG_STM32H5_FLASH_OVERRIDE_DEFAULT) && \ - !defined(CONFIG_STM32H5_FLASH_OVERRIDE_B) && \ - !defined(CONFIG_STM32H5_FLASH_OVERRIDE_C) && \ - !defined(CONFIG_STM32H5_FLASH_OVERRIDE_E) && \ - !defined(CONFIG_STM32H5_FLASH_OVERRIDE_G) && \ - !defined(CONFIG_STM32H5_FLASH_OVERRIDE_I) && \ - !defined(CONFIG_STM32H5_FLASH_CONFIG_B) && \ - !defined(CONFIG_STM32H5_FLASH_CONFIG_C) && \ - !defined(CONFIG_STM32H5_FLASH_CONFIG_E) && \ - !defined(CONFIG_STM32H5_FLASH_CONFIG_G) && \ - !defined(CONFIG_STM32H5_FLASH_CONFIG_I) -# define CONFIG_STM32H5_FLASH_OVERRIDE_E +#if !defined(CONFIG_STM32_FLASH_OVERRIDE_DEFAULT) && \ + !defined(CONFIG_STM32_FLASH_OVERRIDE_B) && \ + !defined(CONFIG_STM32_FLASH_OVERRIDE_C) && \ + !defined(CONFIG_STM32_FLASH_OVERRIDE_E) && \ + !defined(CONFIG_STM32_FLASH_OVERRIDE_G) && \ + !defined(CONFIG_STM32_FLASH_OVERRIDE_I) && \ + !defined(CONFIG_STM32_FLASH_CONFIG_B) && \ + !defined(CONFIG_STM32_FLASH_CONFIG_C) && \ + !defined(CONFIG_STM32_FLASH_CONFIG_E) && \ + !defined(CONFIG_STM32_FLASH_CONFIG_G) && \ + !defined(CONFIG_STM32_FLASH_CONFIG_I) +# define CONFIG_STM32_FLASH_OVERRIDE_E # warning "Flash size not defined defaulting to 512KiB (E)" #endif /* Override of the Flash has been chosen */ -#if !defined(CONFIG_STM32H5_FLASH_OVERRIDE_DEFAULT) -# undef CONFIG_STM32H5_FLASH_CONFIG_C -# undef CONFIG_STM32H5_FLASH_CONFIG_E -# if defined(CONFIG_STM32H5_FLASH_OVERRIDE_C) -# define CONFIG_STM32H5_FLASH_CONFIG_C -# elif defined(CONFIG_STM32H5_FLASH_OVERRIDE_E) -# define CONFIG_STM32H5_FLASH_CONFIG_E +#if !defined(CONFIG_STM32_FLASH_OVERRIDE_DEFAULT) +# undef CONFIG_STM32_FLASH_CONFIG_C +# undef CONFIG_STM32_FLASH_CONFIG_E +# if defined(CONFIG_STM32_FLASH_OVERRIDE_C) +# define CONFIG_STM32_FLASH_CONFIG_C +# elif defined(CONFIG_STM32_FLASH_OVERRIDE_E) +# define CONFIG_STM32_FLASH_CONFIG_E # endif #endif -#if defined(CONFIG_STM32H5_FLASH_CONFIG_I) +#if defined(CONFIG_STM32_FLASH_CONFIG_I) # define H5_FLASH_BANK_NBLOCKS 128 -#elif defined(CONFIG_STM32H5_FLASH_CONFIG_G) +#elif defined(CONFIG_STM32_FLASH_CONFIG_G) # define H5_FLASH_BANK_NBLOCKS 64 -#elif defined(CONFIG_STM32H5_FLASH_CONFIG_E) +#elif defined(CONFIG_STM32_FLASH_CONFIG_E) # define H5_FLASH_BANK_NBLOCKS 32 -#elif defined(CONFIG_STM32H5_FLASH_CONFIG_C) +#elif defined(CONFIG_STM32_FLASH_CONFIG_C) # define H5_FLASH_BANK_NBLOCKS 16 -#elif defined(CONFIG_STM32H5_FLASH_CONFIG_B) +#elif defined(CONFIG_STM32_FLASH_CONFIG_B) # define H5_FLASH_BANK_NBLOCKS 8 #else -# warning "No valid STM32H5_FLASH_CONFIG_x defined." +# warning "No valid STM32_FLASH_CONFIG_x defined." #endif #define H5_FLASH_BANKSIZE (FLASH_BLOCK_SIZE * H5_FLASH_BANK_NBLOCKS) @@ -344,14 +344,14 @@ static void flash_lock_opt(void) ****************************************************************************/ /**************************************************************************** - * Name: stm32h5_flash_unlock + * Name: stm32_flash_unlock * * Description: * Unlock non-secure flash control * ****************************************************************************/ -void stm32h5_flash_unlock(void) +void stm32_flash_unlock(void) { nxmutex_lock(&g_lock); flash_unlock_nscr(); @@ -359,14 +359,14 @@ void stm32h5_flash_unlock(void) } /**************************************************************************** - * Name: stm32h5_flash_lock + * Name: stm32_flash_lock * * Description: * Lock non-secure flash control * ****************************************************************************/ -void stm32h5_flash_lock(void) +void stm32_flash_lock(void) { nxmutex_lock(&g_lock); flash_lock_nscr(); @@ -374,7 +374,7 @@ void stm32h5_flash_lock(void) } /**************************************************************************** - * Name: stm32h5_flash_getopt + * Name: stm32_flash_getopt * * Description: * Read the current flash option bytes from FLASH_OPTSR_CUR and @@ -386,14 +386,14 @@ void stm32h5_flash_lock(void) * ****************************************************************************/ -void stm32h5_flash_getopt(uint32_t *opt1, uint32_t *opt2) +void stm32_flash_getopt(uint32_t *opt1, uint32_t *opt2) { *opt1 = getreg32(STM32_FLASH_OPTSR_CUR); *opt2 = getreg32(STM32_FLASH_OPTSR2_CUR); } /**************************************************************************** - * Name: stm32h5_flash_optmodify + * Name: stm32_flash_optmodify * * Description: * Modifies the current flash option bytes, given bits to set and clear. @@ -412,7 +412,7 @@ void stm32h5_flash_getopt(uint32_t *opt1, uint32_t *opt2) * ****************************************************************************/ -int stm32h5_flash_optmodify(uint32_t clear1, uint32_t set1, +int stm32_flash_optmodify(uint32_t clear1, uint32_t set1, uint32_t clear2, uint32_t set2) { int ret; @@ -451,7 +451,7 @@ int stm32h5_flash_optmodify(uint32_t clear1, uint32_t set1, } /**************************************************************************** - * Name: stm32h5_flash_swapbanks + * Name: stm32_flash_swapbanks * * Description: * Swaps banks 1 and 2 in the processor's memory map. Takes effect @@ -464,7 +464,7 @@ int stm32h5_flash_optmodify(uint32_t clear1, uint32_t set1, * ****************************************************************************/ -int stm32h5_flash_swapbanks(void) +int stm32_flash_swapbanks(void) { uint32_t reg; bool was_locked; diff --git a/arch/arm/src/stm32h5/stm32h5xx_rcc.c b/arch/arm/src/stm32h5/stm32h5xx_rcc.c index 62f94162fbb88..033a384c188ba 100644 --- a/arch/arm/src/stm32h5/stm32h5xx_rcc.c +++ b/arch/arm/src/stm32h5/stm32h5xx_rcc.c @@ -58,19 +58,19 @@ static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1, /* HSE divisor to yield ~1MHz RTC clock */ -#define HSE_DIVISOR (STM32H5_HSE_FREQUENCY + 500000) / 1000000 +#define HSE_DIVISOR (STM32_HSE_FREQUENCY + 500000) / 1000000 /* Determine if board wants to use HSI48 as 48 MHz oscillator. */ -#if defined(CONFIG_STM32H5_HAVE_HSI48) && defined(STM32H5_USE_CLK48) -# if defined(STM32H5_CLKUSB_SEL) -# if (STM32H5_CLKUSB_SEL == RCC_CCIPR4_USBSEL_HSI48KERCK) -# define STM32H5_USE_HSI48 1 +#if defined(CONFIG_STM32_HAVE_HSI48) && defined(STM32_USE_CLK48) +# if defined(STM32_CLKUSB_SEL) +# if (STM32_CLKUSB_SEL == RCC_CCIPR4_USBSEL_HSI48KERCK) +# define STM32_USE_HSI48 1 # endif # endif -# if defined(STM32H5_CLKRNG_SEL) -# if (STM32H5_CLKRNG_SEL == RCC_CCIPR5_RNGSEL_HSI48KERCK) -# define STM32H5_USE_HSI48 1 +# if defined(STM32_CLKRNG_SEL) +# if (STM32_CLKRNG_SEL == RCC_CCIPR5_RNGSEL_HSI48KERCK) +# define STM32_USE_HSI48 1 # endif # endif #endif @@ -101,49 +101,49 @@ static inline void rcc_enableahb1(void) regval = getreg32(STM32_RCC_AHB1ENR); -#ifdef CONFIG_STM32H5_DMA1 +#ifdef CONFIG_STM32_DMA1 /* DMA 1 clock enable */ regval |= RCC_AHB1ENR_GPDMA1EN; #endif -#ifdef CONFIG_STM32H5_DMA2 +#ifdef CONFIG_STM32_DMA2 /* DMA 2 clock enable */ regval |= RCC_AHB1ENR_GPDMA2EN; #endif -#ifdef CONFIG_STM32H5_FLASHEN +#ifdef CONFIG_STM32_FLASHEN /* Flash memory interface clock enable */ regval |= RCC_AHB1ENR_FLASHEN; #endif -#ifdef CONFIG_STM32H5_CRC +#ifdef CONFIG_STM32_CRC /* CRC clock enable */ regval |= RCC_AHB1ENR_CRCEN; #endif -#ifdef CONFIG_STM32H5_CORDIC +#ifdef CONFIG_STM32_CORDIC /* CORDIC clock enable */ regval |= RCC_AHB1ENR_CORDICEN; #endif -#ifdef CONFIG_STM32H5_FMAC +#ifdef CONFIG_STM32_FMAC /* FMAC clock enable */ regval |= RCC_AHB1ENR_FMACEN; #endif -#ifdef CONFIG_STM32H5_RAMCFG +#ifdef CONFIG_STM32_RAMCFG /* RAMCFG clock enable */ regval |= RCC_AHB1ENR_RAMCFGEN; #endif -#ifdef CONFIG_STM32H5_ETHMAC +#ifdef CONFIG_STM32_ETHMAC /* ETH clock enable */ regval |= RCC_AHB1ENR_ETHEN; @@ -157,24 +157,24 @@ static inline void rcc_enableahb1(void) regval |= RCC_AHB1ENR_ETHRXEN; #endif -#ifdef CONFIG_STM32H5_TZSC1 +#ifdef CONFIG_STM32_TZSC1 regval |= RCC_AHB1ENR_TZSC1EN; #endif -#ifdef CONFIG_STM32H5_BKPRAM +#ifdef CONFIG_STM32_BKPRAM /* BKPRAM clock enable */ regval |= RCC_AHB1ENR_BKPRAMEN; #endif -#ifdef CONFIG_STM32H5_DCACHE +#ifdef CONFIG_STM32_DCACHE /* DCACHE clock enable */ regval |= RCC_AHB1ENR_DCACHEEN; #endif -#ifdef CONFIG_STM32H5_SRAM1 +#ifdef CONFIG_STM32_SRAM1 /* ETH clock enable */ regval |= RCC_AHB1ENR_SRAM1EN; @@ -203,91 +203,91 @@ static inline void rcc_enableahb2(void) /* Enable GPIOA, GPIOB, .... GPIOH */ -#if STM32H5_NPORTS > 0 +#if STM32_NPORTS > 0 regval |= (RCC_AHB2ENR_GPIOAEN -#if STM32H5_NPORTS > 1 +#if STM32_NPORTS > 1 | RCC_AHB2ENR_GPIOBEN #endif -#if STM32H5_NPORTS > 2 +#if STM32_NPORTS > 2 | RCC_AHB2ENR_GPIOCEN #endif -#if STM32H5_NPORTS > 3 +#if STM32_NPORTS > 3 | RCC_AHB2ENR_GPIODEN #endif -#if STM32H5_NPORTS > 4 +#if STM32_NPORTS > 4 | RCC_AHB2ENR_GPIOEEN #endif -#if STM32H5_NPORTS > 5 +#if STM32_NPORTS > 5 | RCC_AHB2ENR_GPIOFEN #endif -#if STM32H5_NPORTS > 6 +#if STM32_NPORTS > 6 | RCC_AHB2ENR_GPIOGEN #endif -#if STM32H5_NPORTS > 7 +#if STM32_NPORTS > 7 | RCC_AHB2ENR_GPIOHEN #endif -#if STM32H5_NPORTS > 7 +#if STM32_NPORTS > 7 | RCC_AHB2ENR_GPIOIEN #endif ); #endif -#if defined(CONFIG_STM32H5_ADC) +#if defined(CONFIG_STM32_ADC) /* ADC clock enable */ regval |= RCC_AHB2ENR_ADCEN; #endif -#ifdef CONFIG_STM32H5_DAC1 +#ifdef CONFIG_STM32_DAC1 /* DAC1 clock enable */ regval |= RCC_AHB2ENR_DAC1EN; #endif -#ifdef CONFIG_STM32H5_DCMI_PSSI +#ifdef CONFIG_STM32_DCMI_PSSI /* Digital Camera Interface clock enable */ regval |= RCC_AHB2ENR_DCMI_PSSIEN; #endif -#ifdef CONFIG_STM32H5_AES +#ifdef CONFIG_STM32_AES /* Cryptographic modules clock enable */ regval |= RCC_AHB2ENR_AESEN; #endif -#ifdef CONFIG_STM32H5_HASH +#ifdef CONFIG_STM32_HASH /* Hash module enable */ regval |= RCC_AHB2ENR_HASHEN #endif -#ifdef CONFIG_STM32H5_RNG +#ifdef CONFIG_STM32_RNG /* Random number generator clock enable */ regval |= RCC_AHB2ENR_RNGEN; #endif -#ifdef CONFIG_STM32H5_PKA +#ifdef CONFIG_STM32_PKA /* Public Key Accelerator clock enable */ regval |= RCC_AHB2ENR_PKAEN; #endif -#ifdef CONFIG_STM32H5_SAES +#ifdef CONFIG_STM32_SAES /* Secure AES coprocessor clock enable */ regval |= RCC_AHB2ENR_SAESEN; #endif -#ifdef CONFIG_STM32H5_SRAM2 +#ifdef CONFIG_STM32_SRAM2 /* SRAM2 clock enable */ regval |= RCC_AHB2ENR_SRAM2EN; #endif -#ifdef CONFIG_STM32H5_SRAM3 +#ifdef CONFIG_STM32_SRAM3 /* SRAM2 clock enable */ regval |= RCC_AHB2ENR_SRAM3EN; @@ -314,31 +314,31 @@ static inline void rcc_enableahb4(void) regval = getreg32(STM32_RCC_AHB4ENR); -#ifdef CONFIG_STM32H5_OTFDEC1EN +#ifdef CONFIG_STM32_OTFDEC1EN /* On-the-fly-decryption module clock enable */ regval |= RCC_AHB4ENR_OTFDEC1EN; #endif -#ifdef CONFIG_STM32H5_SDMMC1 +#ifdef CONFIG_STM32_SDMMC1 /* SDMMC1 clock enable */ regval |= RCC_AHB4ENR_SDMMC1EN; #endif -#ifdef CONFIG_STM32H5_SDMMC2 +#ifdef CONFIG_STM32_SDMMC2 /* SDMMC1 clock enable */ regval |= RCC_AHB4ENR_SDMMC2EN; #endif -#ifdef CONFIG_STM32H5_FMC +#ifdef CONFIG_STM32_FMC /* Flexible memory controller clock enable */ regval |= RCC_AHB4ENR_FMCEN; #endif -#ifdef CONFIG_STM32H5_OCTOSPI1 +#ifdef CONFIG_STM32_OCTOSPI1 /* OCTOSPI1 module clock enable */ regval |= RCC_AHB4ENR_OSPI1EN; @@ -365,62 +365,62 @@ static inline void rcc_enableapb1l(void) regval = getreg32(STM32_RCC_APB1LENR); -#ifdef CONFIG_STM32H5_SPI2 +#ifdef CONFIG_STM32_SPI2 /* Bit 14: SPI2 clock enable */ regval |= RCC_APB1LENR_SPI2EN; #endif -#ifdef CONFIG_STM32H5_SPI3 +#ifdef CONFIG_STM32_SPI3 /* Bit 15: SPI3 clock enable */ regval |= RCC_APB1LENR_SPI3EN; #endif -#ifdef CONFIG_STM32H5_USART2 +#ifdef CONFIG_STM32_USART2 /* Bit 17: USART2 clock enable */ regval |= RCC_APB1LENR_USART2EN; #endif -#ifdef CONFIG_STM32H5_USART3 +#ifdef CONFIG_STM32_USART3 /* Bit 18: USART3 clock enable */ regval |= RCC_APB1LENR_USART3EN; #endif -#ifdef CONFIG_STM32H5_UART4 +#ifdef CONFIG_STM32_UART4 /* Bit 19: UART4 clock enable */ regval |= RCC_APB1LENR_UART4EN; #endif -#ifdef CONFIG_STM32H5_UART5 +#ifdef CONFIG_STM32_UART5 /* Bit 20: UART5 clock enable */ regval |= RCC_APB1LENR_UART5EN; #endif -#ifdef CONFIG_STM32H5_I2C1 +#ifdef CONFIG_STM32_I2C1 /* Bit 21: I2C1 clock enable */ regval |= RCC_APB1LENR_I2C1EN; #endif -#ifdef CONFIG_STM32H5_I2C2 +#ifdef CONFIG_STM32_I2C2 /* Bit 22: I2C2 clock enable */ regval |= RCC_APB1LENR_I2C2EN; #endif -#ifdef CONFIG_STM32H5_I3C1 +#ifdef CONFIG_STM32_I3C1 /* Bit 23: I3C1 clock enable */ regval |= RCC_APB1LENR_I3C1EN; #endif -#ifdef STM32H5_USE_HSI48 - if (STM32H5_HSI48_SYNCSRC != SYNCSRC_NONE) +#ifdef STM32_USE_HSI48 + if (STM32_HSI48_SYNCSRC != SYNCSRC_NONE) { /* Bit 24: CRS clock enable */ @@ -428,37 +428,37 @@ static inline void rcc_enableapb1l(void) } #endif -#ifdef CONFIG_STM32H5_USART6 +#ifdef CONFIG_STM32_USART6 /* Bit 25: USART6 clock enable */ regval |= RCC_APB1LENR_USART6EN; #endif -#ifdef CONFIG_STM32H5_USART10 +#ifdef CONFIG_STM32_USART10 /* Bit 26: USART10 clock enable */ regval |= RCC_APB1LENR_USART10EN; #endif -#ifdef CONFIG_STM32H5_USART11 +#ifdef CONFIG_STM32_USART11 /* Bit 27: USART11 clock enable */ regval |= RCC_APB1LENR_USART11EN; #endif -#ifdef CONFIG_STM32H5_CEC +#ifdef CONFIG_STM32_CEC /* Bit 28: CEC clock enable */ regval |= RCC_APB1LENR_CECEN; #endif -#ifdef CONFIG_STM32H5_UART7 +#ifdef CONFIG_STM32_UART7 /* Bit 30: UART7 clock enable */ regval |= RCC_APB1LENR_UART7EN; #endif -#ifdef CONFIG_STM32H5_UART8 +#ifdef CONFIG_STM32_UART8 /* Bit 31: UART8 clock enable */ regval |= RCC_APB1LENR_UART8EN; @@ -485,37 +485,37 @@ static inline void rcc_enableapb1h(void) regval = getreg32(STM32_RCC_APB1HENR); -#ifdef CONFIG_STM32H5_UART9 +#ifdef CONFIG_STM32_UART9 /* Bit 0: UART9 clock enable */ regval |= RCC_APB1HENR_UART9EN; #endif -#ifdef CONFIG_STM32H5_UART12 +#ifdef CONFIG_STM32_UART12 /* Bit 1: UART12 clock enable */ regval |= RCC_APB1HENR_UART12EN; #endif -#ifdef CONFIG_STM32H5_DTS +#ifdef CONFIG_STM32_DTS /* Bit 3: DTS clock enable */ regval |= RCC_APB1HENR_DTSEN; #endif -#ifdef CONFIG_STM32H5_LPTIM2 +#ifdef CONFIG_STM32_LPTIM2 /* Bit 5: Low-power Timer 2 clock enable */ regval |= RCC_APB1HENR_LPTIM2EN; #endif -#ifdef CONFIG_STM32H5_FDCAN +#ifdef CONFIG_STM32_FDCAN /* Bit 9: FDCAN clock enable */ regval |= RCC_APB1HENR_FDCANEN; #endif -#ifdef CONFIG_STM32H5_UCPD1 +#ifdef CONFIG_STM32_UCPD1 /* Bit 23: UCPD1 clock enable */ regval |= RCC_APB1HENR_UCPD1EN; @@ -544,43 +544,43 @@ static inline void rcc_enableapb2(void) regval = getreg32(STM32_RCC_APB2ENR); -#ifdef CONFIG_STM32H5_SPI1 +#ifdef CONFIG_STM32_SPI1 /* SPI1 clock enable */ regval |= RCC_APB2ENR_SPI1EN; #endif -#ifdef CONFIG_STM32H5_USART1 +#ifdef CONFIG_STM32_USART1 /* USART1 clock enable */ regval |= RCC_APB2ENR_USART1EN; #endif -#ifdef CONFIG_STM32H5_SPI4 +#ifdef CONFIG_STM32_SPI4 /* SPI4 clock enable */ regval |= RCC_APB2ENR_SPI4EN; #endif -#ifdef CONFIG_STM32H5_SPI6 +#ifdef CONFIG_STM32_SPI6 /* SPI6 clock enable */ regval |= RCC_APB2ENR_SPI6EN; #endif -#ifdef CONFIG_STM32H5_SAI1 +#ifdef CONFIG_STM32_SAI1 /* SAI1 clock enable */ regval |= RCC_APB2ENR_SAI1EN; #endif -#ifdef CONFIG_STM32H5_SAI2 +#ifdef CONFIG_STM32_SAI2 /* SAI2 clock enable */ regval |= RCC_APB2ENR_SAI2EN; #endif -#if defined(CONFIG_STM32H5_USBFS) || defined(CONFIG_STM32H5_USBFS_HOST) +#if defined(CONFIG_STM32_USBFS) || defined(CONFIG_STM32_USBFS_HOST) /* USB clock enable */ regval |= RCC_APB2ENR_USBEN; @@ -607,79 +607,79 @@ static inline void rcc_enableapb3(void) regval = getreg32(STM32_RCC_APB3ENR); -#if defined(CONFIG_STM32H5_SBS) || defined(CONFIG_STM32H5_ETHMAC) +#if defined(CONFIG_STM32_SBS) || defined(CONFIG_STM32_ETHMAC) /* Bit 1: SBS clock enable */ regval |= RCC_APB3ENR_SBSEN; #endif -#ifdef CONFIG_STM32H5_SPI5 +#ifdef CONFIG_STM32_SPI5 /* Bit 5: SPI5 clock enable */ regval |= RCC_APB3ENR_SPI5EN; #endif -#ifdef CONFIG_STM32H5_LPUART1 +#ifdef CONFIG_STM32_LPUART1 /* Bit 6: LPUART1 clock enable */ regval |= RCC_APB3ENR_LPUART1EN; #endif -#ifdef CONFIG_STM32H5_I2C3 +#ifdef CONFIG_STM32_I2C3 /* Bit 7: I2C3 clock enable */ regval |= RCC_APB3ENR_I2C3EN; #endif -#ifdef CONFIG_STM32H5_I2C4 +#ifdef CONFIG_STM32_I2C4 /* Bit 8: I2C4 clock enable */ regval |= RCC_APB3ENR_I2C4EN; #endif -#ifdef CONFIG_STM32H5_I3C2 +#ifdef CONFIG_STM32_I3C2 /* Bit 9: I3C2 clock enable */ regval |= RCC_APB3ENR_I3C2EN; #endif -#ifdef CONFIG_STM32H5_LPTIM1 +#ifdef CONFIG_STM32_LPTIM1 /* Bit 11: LPTIM1 clock enable */ regval |= RCC_APB3ENR_LPTIM1EN; #endif -#ifdef CONFIG_STM32H5_LPTIM3 +#ifdef CONFIG_STM32_LPTIM3 /* Bit 12: LPTIM3 clock enable */ regval |= RCC_APB3ENR_LPTIM3EN; #endif -#ifdef CONFIG_STM32H5_LPTIM4 +#ifdef CONFIG_STM32_LPTIM4 /* Bit 13: LPTIM4 clock enable */ regval |= RCC_APB3ENR_LPTIM4EN; #endif -#ifdef CONFIG_STM32H5_LPTIM5 +#ifdef CONFIG_STM32_LPTIM5 /* Bit 14: LPTIM5 clock enable */ regval |= RCC_APB3ENR_LPTIM5EN; #endif -#ifdef CONFIG_STM32H5_LPTIM6 +#ifdef CONFIG_STM32_LPTIM6 /* Bit 15: LPTIM6 clock enable */ regval |= RCC_APB3ENR_LPTIM6EN; #endif -#ifdef CONFIG_STM32H5_VREF +#ifdef CONFIG_STM32_VREF /* Bit 20: VREF clock enable */ regval |= RCC_APB3ENR_VREFEN; #endif -#ifdef CONFIG_STM32H5_RTCAPB +#ifdef CONFIG_STM32_RTCAPB /* Bit 21: RTCABP clock enable */ regval |= RCC_APB3ENR_RTCAPBEN; @@ -842,10 +842,10 @@ void stm32_rcc_enableperipherals(void) rcc_enableapb2(); rcc_enableapb3(); -#ifdef STM32H5_USE_HSI48 +#ifdef STM32_USE_HSI48 /* Enable HSI48 clocking to support USB transfers or RNG */ - stm32h5_enable_hsi48(STM32H5_HSI48_SYNCSRC); + stm32_enable_hsi48(STM32_HSI48_SYNCSRC); #endif } @@ -859,7 +859,7 @@ void stm32_rcc_enableperipherals(void) * power clocking modes! ****************************************************************************/ -#ifndef CONFIG_ARCH_BOARD_STM32H5_CUSTOM_CLOCKCONFIG +#ifndef CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG void stm32_stdclockconfig(void) { uint32_t regval; @@ -995,7 +995,7 @@ void stm32_stdclockconfig(void) putreg32(regval, STM32_RCC_CFGR2); -#ifdef CONFIG_STM32H5_RTC_HSECLOCK +#ifdef CONFIG_STM32_RTC_HSECLOCK /* Set the RTC clock divisor */ regval = getreg32(STM32_RCC_CFGR1); @@ -1096,15 +1096,15 @@ void stm32_stdclockconfig(void) { } -#if defined(CONFIG_STM32H5_IWDG) || defined(CONFIG_STM32H5_RTC_LSICLOCK) || \ - defined(STM32H5_USE_LSCO_LSI) +#if defined(CONFIG_STM32_IWDG) || defined(CONFIG_STM32_RTC_LSICLOCK) || \ + defined(STM32_USE_LSCO_LSI) /* Low speed internal clock source LSI */ stm32_rcc_enablelsi(); #endif -#if defined(STM32_USE_LSE) || defined(STM32H5_USE_LSCO_LSE) +#if defined(STM32_USE_LSE) || defined(STM32_USE_LSCO_LSE) /* Low speed external clock source LSE */ stm32_rcc_enablelse(); @@ -1203,19 +1203,19 @@ void stm32_stdclockconfig(void) /* Configure USB source clock */ -#if defined(STM32H5_CLKUSB_SEL) +#if defined(STM32_CLKUSB_SEL) regval = getreg32(STM32_RCC_CCIPR4); regval &= ~RCC_CCIPR4_USBSEL_MASK; - regval |= STM32H5_CLKUSB_SEL; + regval |= STM32_CLKUSB_SEL; putreg32(regval, STM32_RCC_CCIPR4); #endif /* Configure RNG source clock */ -#if defined(STM32H5_CLKRNG_SEL) +#if defined(STM32_CLKRNG_SEL) regval = getreg32(STM32_RCC_CCIPR5); regval &= ~RCC_CCIPR5_RNGSEL_MASK; - regval |= STM32H5_CLKRNG_SEL; + regval |= STM32_CLKRNG_SEL; putreg32(regval, STM32_RCC_CCIPR5); #endif } diff --git a/arch/arm/src/stm32h7/CMakeLists.txt b/arch/arm/src/stm32h7/CMakeLists.txt index eb5a4218c2203..5f6e1f9800f86 100644 --- a/arch/arm/src/stm32h7/CMakeLists.txt +++ b/arch/arm/src/stm32h7/CMakeLists.txt @@ -32,10 +32,9 @@ list( stm32_start.c stm32_rcc.c stm32_lowputc.c - stm32_serial.c - stm32_uid.c) + stm32_serial.c) -if(CONFIG_STM32H7_PROGMEM) +if(CONFIG_STM32_PROGMEM) list(APPEND SRCS stm32_flash.c) endif() @@ -43,7 +42,7 @@ if(CONFIG_ARCH_STM32H7_DUALCORE) list(APPEND SRCS stm32_dualcore.c) endif() -if(CONFIG_STM32H7_HSEM) +if(CONFIG_STM32_HSEM) list(APPEND SRCS stm32_hsem.c) endif() @@ -57,7 +56,7 @@ else() list(APPEND SRCS stm32_timerisr.c) endif() -if(CONFIG_STM32H7_ONESHOT) +if(CONFIG_STM32_ONESHOT) list(APPEND SRCS stm32_oneshot.c stm32_oneshot_lowerhalf.c) endif() @@ -73,47 +72,51 @@ if(CONFIG_ARMV7M_DTCM) list(APPEND SRCS stm32_dtcm.c) endif() -if(CONFIG_STM32H7_ADC) +if(CONFIG_STM32_ADC) list(APPEND SRCS stm32_adc.c) endif() -if(CONFIG_STM32H7_FDCAN) +if(CONFIG_STM32_FDCAN) list(APPEND SRCS stm32_fdcan_sock.c) endif() -if(CONFIG_STM32H7_BBSRAM) +if(CONFIG_STM32_BBSRAM) list(APPEND SRCS stm32_bbsram.c) endif() -if(CONFIG_STM32H7_DMA) +if(CONFIG_STM32_DMA) list(APPEND SRCS stm32_dma.c) endif() -if(CONFIG_STM32H7_FMC) +if(CONFIG_STM32_FMC) list(APPEND SRCS stm32_fmc.c) endif() -if(CONFIG_STM32H7_IWDG OR CONFIG_STM32H7_RTC_LSICLOCK) +if(CONFIG_STM32_RNG) + list(APPEND SRCS stm32_rng.c) +endif() + +if(CONFIG_STM32_IWDG OR CONFIG_STM32_RTC_LSICLOCK) list(APPEND SRCS stm32_lsi.c) endif() -if(CONFIG_STM32H7_RTC_LSECLOCK) +if(CONFIG_STM32_RTC_LSECLOCK) list(APPEND SRCS stm32_lse.c) endif() -if(CONFIG_STM32H7_I2C) +if(CONFIG_STM32_I2C) list(APPEND SRCS stm32_i2c.c) endif() -if(CONFIG_STM32H7_PWR) +if(CONFIG_STM32_PWR) list(APPEND SRCS stm32_pwr.c) endif() -if(CONFIG_STM32H7_QUADSPI) +if(CONFIG_STM32_QSPI) list(APPEND SRCS stm32_qspi.c) endif() -if(CONFIG_STM32H7_RTC) +if(CONFIG_STM32_RTC) list(APPEND SRCS stm32_rtc.c) if(CONFIG_RTC_ALARM) list(APPEND SRCS stm32_exti_alarm.c) @@ -126,7 +129,7 @@ if(CONFIG_STM32H7_RTC) endif() endif() -if(CONFIG_STM32H7_SPI) +if(CONFIG_STM32_SPI) list(APPEND SRCS stm32_spi.c) endif() @@ -134,7 +137,7 @@ if(CONFIG_SPI_SLAVE) list(APPEND SRCS stm32_spi_slave.c) endif() -if(CONFIG_STM32H7_SDMMC) +if(CONFIG_STM32_SDMMC) list(APPEND SRCS stm32_sdmmc.c) endif() @@ -142,7 +145,7 @@ if(CONFIG_TIMER) list(APPEND SRCS stm32_tim_lowerhalf.c) endif() -if(CONFIG_STM32H7_TIMX_CAP) +if(CONFIG_STM32_TIMX_CAP) list(APPEND SRCS stm32_capture.c) endif() @@ -150,7 +153,7 @@ if(CONFIG_CAPTURE) list(APPEND SRCS stm32_capture_lowerhalf.c) endif() -if(CONFIG_STM32H7_LTDC) +if(CONFIG_STM32_LTDC) list(APPEND SRCS stm32_ltdc.c) endif() @@ -169,15 +172,15 @@ if(CONFIG_USBHOST) endif() endif() -if(CONFIG_STM32H7_TIM) +if(CONFIG_STM32_TIM) list(APPEND SRCS stm32_tim.c) endif() -if(CONFIG_STM32H7_LPTIM) +if(CONFIG_STM32_LPTIM) list(APPEND SRCS stm32_lptim.c) endif() -if(CONFIG_STM32H7_PWM) +if(CONFIG_STM32_PWM) list(APPEND SRCS stm32_pwm.c) endif() @@ -185,7 +188,7 @@ if(CONFIG_PULSECOUNT) list(APPEND SRCS stm32_pulsecount.c) endif() -if(CONFIG_STM32H7_ETHMAC) +if(CONFIG_STM32_ETHMAC) list(APPEND SRCS stm32_ethernet.c) endif() @@ -204,12 +207,22 @@ if(CONFIG_PM) endif() endif() -if(CONFIG_STM32H7_IWDG) +if(CONFIG_STM32_IWDG) list(APPEND SRCS stm32_iwdg.c) endif() -if(CONFIG_STM32H7_WWDG) +if(CONFIG_STM32_WWDG) list(APPEND SRCS stm32_wwdg.c) endif() +if(CONFIG_STM32_CRYP AND CONFIG_STM32_HAVE_IP_CRYPTO_H7) + list(APPEND SRCS stm32_aes.c) +endif() + +if(CONFIG_CRYPTO_CRYPTODEV_HARDWARE AND CONFIG_STM32_HAVE_IP_CRYPTO_H7) + list(APPEND SRCS stm32_crypto.c) +endif() + target_sources(arch PRIVATE ${SRCS}) + +add_subdirectory(${NUTTX_DIR}/arch/arm/src/common/stm32 stm32_common) diff --git a/arch/arm/src/stm32h7/Kconfig b/arch/arm/src/stm32h7/Kconfig index 4f1c6eaaa173f..17a8fc57014c3 100644 --- a/arch/arm/src/stm32h7/Kconfig +++ b/arch/arm/src/stm32h7/Kconfig @@ -7,6 +7,43 @@ if ARCH_CHIP_STM32H7 comment "STM32 H7 Configuration Options" +config STM32_H7_PERIPHERALS + bool + default ARCH_CHIP_STM32H7 + select STM32_HAVE_DMA1 + select STM32_HAVE_DMA2 + select STM32_HAVE_I2C1 + select STM32_HAVE_I2C2 + select STM32_HAVE_I2C3 + select STM32_HAVE_I2C4 + select STM32_HAVE_IOCOMPENSATION + select STM32_HAVE_LPTIM1 + select STM32_HAVE_OTGFS + select STM32_HAVE_RTC_SUBSECONDS + select STM32_HAVE_SDMMC1 + select STM32_HAVE_SDMMC2 + select STM32_HAVE_SPI1 + select STM32_HAVE_SPI2 + select STM32_HAVE_SPI3 + select STM32_HAVE_SYSCFG + select STM32_HAVE_UART4 + select STM32_HAVE_UART5 + select STM32_HAVE_UART7 + select STM32_HAVE_UART8 + select STM32_HAVE_USART1 + select STM32_HAVE_USART2 + select STM32_HAVE_USART3 + select STM32_HAVE_USART6 + select STM32_HAVE_HSEM + select STM32_HAVE_CSI + select STM32_HAVE_HSI48 + select STM32_HAVE_MDMA + select STM32_HAVE_BDMA + select STM32_HAVE_OTG_H7 + select STM32_HAVE_USART_RXFIFO_THRESHOLD + select STM32_HAVE_FDCAN_H7 + select STM32_HAVE_IP_WDG_M3M4_V1 + choice prompt "STM32 H7 Chip Selection" default ARCH_CHIP_STM32H743ZI @@ -14,34 +51,34 @@ choice config ARCH_CHIP_STM32H723VG bool "STM32H723VG" - select STM32H7_STM32H7X3XX - select STM32H7_STM32H72XXX_OR_STM32H73XXX - select STM32H7_FLASH_CONFIG_G + select STM32_STM32H7X3XX + select STM32_STM32H72XXX_OR_STM32H73XXX + select STM32_FLASH_CONFIG_G select STM32H7_IO_CONFIG_V - select STM32H7_HAVE_FDCAN1 - select STM32H7_HAVE_FDCAN2 - select STM32H7_HAVE_FDCAN3 + select STM32_HAVE_FDCAN1 + select STM32_HAVE_FDCAN2 + select STM32_HAVE_FDCAN3 ---help--- STM32 H7 Cortex M7, 1024 Kb FLASH, 564K Kb SRAM, LQFP144 config ARCH_CHIP_STM32H723ZG bool "STM32H723ZG" - select STM32H7_STM32H7X3XX - select STM32H7_STM32H72XXX_OR_STM32H73XXX - select STM32H7_FLASH_CONFIG_G + select STM32_STM32H7X3XX + select STM32_STM32H72XXX_OR_STM32H73XXX + select STM32_FLASH_CONFIG_G select STM32H7_IO_CONFIG_Z - select STM32H7_HAVE_FDCAN1 - select STM32H7_HAVE_FDCAN2 - select STM32H7_HAVE_FDCAN3 + select STM32_HAVE_FDCAN1 + select STM32_HAVE_FDCAN2 + select STM32_HAVE_FDCAN3 ---help--- STM32 H7 Cortex M7, 1024 Kb FLASH, 564K Kb SRAM, LQFP144 config ARCH_CHIP_STM32H743AG bool "STM32H743AG" - select STM32H7_STM32H7X3XX - select STM32H7_FLASH_CONFIG_G + select STM32_STM32H7X3XX + select STM32_FLASH_CONFIG_G select STM32H7_IO_CONFIG_A ---help--- STM32 H7 Cortex M7, 1024 Kb FLASH, 1024K Kb SRAM, @@ -49,8 +86,8 @@ config ARCH_CHIP_STM32H743AG config ARCH_CHIP_STM32H743AI bool "STM32H743AI" - select STM32H7_STM32H7X3XX - select STM32H7_FLASH_CONFIG_I + select STM32_STM32H7X3XX + select STM32_FLASH_CONFIG_I select STM32H7_IO_CONFIG_A ---help--- STM32 H7 Cortex M7, 2048 Kb FLASH, 1024K Kb SRAM, @@ -58,8 +95,8 @@ config ARCH_CHIP_STM32H743AI config ARCH_CHIP_STM32H743BG bool "STM32H743BG" - select STM32H7_STM32H7X3XX - select STM32H7_FLASH_CONFIG_G + select STM32_STM32H7X3XX + select STM32_FLASH_CONFIG_G select STM32H7_IO_CONFIG_B ---help--- STM32 H7 Cortex M7, 1024 Kb FLASH, 1024K Kb SRAM, @@ -67,8 +104,8 @@ config ARCH_CHIP_STM32H743BG config ARCH_CHIP_STM32H743BI bool "STM32H743BI" - select STM32H7_STM32H7X3XX - select STM32H7_FLASH_CONFIG_I + select STM32_STM32H7X3XX + select STM32_FLASH_CONFIG_I select STM32H7_IO_CONFIG_B ---help--- STM32 H7 Cortex M7, 2048 Kb FLASH, 1024K Kb SRAM, @@ -76,8 +113,8 @@ config ARCH_CHIP_STM32H743BI config ARCH_CHIP_STM32H743IG bool "STM32H743IG" - select STM32H7_STM32H7X3XX - select STM32H7_FLASH_CONFIG_G + select STM32_STM32H7X3XX + select STM32_FLASH_CONFIG_G select STM32H7_IO_CONFIG_I ---help--- STM32 H7 Cortex M7, 1024 Kb FLASH, 1024K Kb SRAM, @@ -85,8 +122,8 @@ config ARCH_CHIP_STM32H743IG config ARCH_CHIP_STM32H743II bool "STM32H743II" - select STM32H7_STM32H7X3XX - select STM32H7_FLASH_CONFIG_I + select STM32_STM32H7X3XX + select STM32_FLASH_CONFIG_I select STM32H7_IO_CONFIG_I ---help--- STM32 H7 Cortex M7, 2048 Kb FLASH, 1024K Kb SRAM, @@ -94,8 +131,8 @@ config ARCH_CHIP_STM32H743II config ARCH_CHIP_STM32H743VG bool "STM32H743VG" - select STM32H7_STM32H7X3XX - select STM32H7_FLASH_CONFIG_G + select STM32_STM32H7X3XX + select STM32_FLASH_CONFIG_G select STM32H7_IO_CONFIG_V ---help--- STM32 H7 Cortex M7, 1024 Kb FLASH, 1024K Kb SRAM, @@ -103,8 +140,8 @@ config ARCH_CHIP_STM32H743VG config ARCH_CHIP_STM32H743VI bool "STM32H743VI" - select STM32H7_STM32H7X3XX - select STM32H7_FLASH_CONFIG_I + select STM32_STM32H7X3XX + select STM32_FLASH_CONFIG_I select STM32H7_IO_CONFIG_V ---help--- STM32 H7 Cortex M7, 2048 Kb FLASH, 1024K Kb SRAM, @@ -112,8 +149,8 @@ config ARCH_CHIP_STM32H743VI config ARCH_CHIP_STM32H743XG bool "STM32H743XG" - select STM32H7_STM32H7X3XX - select STM32H7_FLASH_CONFIG_G + select STM32_STM32H7X3XX + select STM32_FLASH_CONFIG_G select STM32H7_IO_CONFIG_X ---help--- STM32 H7 Cortex M7, 1024 Kb FLASH, 1024K Kb SRAM, @@ -121,8 +158,8 @@ config ARCH_CHIP_STM32H743XG config ARCH_CHIP_STM32H743XI bool "STM32H743XI" - select STM32H7_STM32H7X3XX - select STM32H7_FLASH_CONFIG_I + select STM32_STM32H7X3XX + select STM32_FLASH_CONFIG_I select STM32H7_IO_CONFIG_X ---help--- STM32 H7 Cortex M7, 2048 Kb FLASH, 1024K Kb SRAM, @@ -130,8 +167,8 @@ config ARCH_CHIP_STM32H743XI config ARCH_CHIP_STM32H743ZG bool "STM32H743ZG" - select STM32H7_STM32H7X3XX - select STM32H7_FLASH_CONFIG_G + select STM32_STM32H7X3XX + select STM32_FLASH_CONFIG_G select STM32H7_IO_CONFIG_Z ---help--- STM32 H7 Cortex M7, 1024 Kb FLASH, 1024K Kb SRAM, @@ -139,8 +176,8 @@ config ARCH_CHIP_STM32H743ZG config ARCH_CHIP_STM32H743ZI bool "STM32H743ZI" - select STM32H7_STM32H7X3XX - select STM32H7_FLASH_CONFIG_I + select STM32_STM32H7X3XX + select STM32_FLASH_CONFIG_I select STM32H7_IO_CONFIG_Z ---help--- STM32 H7 Cortex M7, 2048 Kb FLASH, 1024K Kb SRAM, @@ -148,8 +185,8 @@ config ARCH_CHIP_STM32H743ZI config ARCH_CHIP_STM32H745BG bool "STM32H745BG" - select STM32H7_STM32H7X5XX - select STM32H7_FLASH_CONFIG_G + select STM32_STM32H7X5XX + select STM32_FLASH_CONFIG_G select STM32H7_IO_CONFIG_B ---help--- Dual core STM32 H7 Cortex M7+M4, 1024 Kb FLASH, 1024K Kb SRAM, @@ -157,8 +194,8 @@ config ARCH_CHIP_STM32H745BG config ARCH_CHIP_STM32H745BI bool "STM32H745BI" - select STM32H7_STM32H7X5XX - select STM32H7_FLASH_CONFIG_I + select STM32_STM32H7X5XX + select STM32_FLASH_CONFIG_I select STM32H7_IO_CONFIG_B ---help--- Dual core STM32 H7 Cortex M7+M4, 2048 Kb FLASH, 1024K Kb SRAM, @@ -166,8 +203,8 @@ config ARCH_CHIP_STM32H745BI config ARCH_CHIP_STM32H745IG bool "STM32H745IG" - select STM32H7_STM32H7X5XX - select STM32H7_FLASH_CONFIG_G + select STM32_STM32H7X5XX + select STM32_FLASH_CONFIG_G select STM32H7_IO_CONFIG_I ---help--- Dual core STM32 H7 Cortex M7+M4, 1024 Kb FLASH, 1024K Kb SRAM, @@ -175,8 +212,8 @@ config ARCH_CHIP_STM32H745IG config ARCH_CHIP_STM32H745II bool "STM32H745II" - select STM32H7_STM32H7X5XX - select STM32H7_FLASH_CONFIG_I + select STM32_STM32H7X5XX + select STM32_FLASH_CONFIG_I select STM32H7_IO_CONFIG_I ---help--- Dual core STM32 H7 Cortex M7+M4, 2048 Kb FLASH, 1024K Kb SRAM, @@ -184,8 +221,8 @@ config ARCH_CHIP_STM32H745II config ARCH_CHIP_STM32H745XG bool "STM32H745XG" - select STM32H7_STM32H7X5XX - select STM32H7_FLASH_CONFIG_G + select STM32_STM32H7X5XX + select STM32_FLASH_CONFIG_G select STM32H7_IO_CONFIG_X ---help--- Dual core STM32 H7 Cortex M7+M4, 1024 Kb FLASH, 1024K Kb SRAM, @@ -193,8 +230,8 @@ config ARCH_CHIP_STM32H745XG config ARCH_CHIP_STM32H745XI bool "STM32H745XI" - select STM32H7_STM32H7X5XX - select STM32H7_FLASH_CONFIG_I + select STM32_STM32H7X5XX + select STM32_FLASH_CONFIG_I select STM32H7_IO_CONFIG_X ---help--- Dual core STM32 H7 Cortex M7+M4, 2048 Kb FLASH, 1024K Kb SRAM, @@ -202,8 +239,8 @@ config ARCH_CHIP_STM32H745XI config ARCH_CHIP_STM32H745ZG bool "STM32H745ZG" - select STM32H7_STM32H7X5XX - select STM32H7_FLASH_CONFIG_G + select STM32_STM32H7X5XX + select STM32_FLASH_CONFIG_G select STM32H7_IO_CONFIG_Z ---help--- Dual core STM32 H7 Cortex M7+M4, 1024 Kb FLASH, 1024K Kb SRAM, @@ -211,8 +248,8 @@ config ARCH_CHIP_STM32H745ZG config ARCH_CHIP_STM32H745ZI bool "STM32H745ZI" - select STM32H7_STM32H7X5XX - select STM32H7_FLASH_CONFIG_I + select STM32_STM32H7X5XX + select STM32_FLASH_CONFIG_I select STM32H7_IO_CONFIG_Z ---help--- Dual core STM32 H7 Cortex M7+M4, 2048 Kb FLASH, 1024K Kb SRAM, @@ -220,165 +257,170 @@ config ARCH_CHIP_STM32H745ZI config ARCH_CHIP_STM32H747XI bool "STM32H747XI" - select STM32H7_STM32H7X7XX - select STM32H7_FLASH_CONFIG_I + select STM32_STM32H7X7XX + select STM32_FLASH_CONFIG_I select STM32H7_IO_CONFIG_X - select STM32H7_HAVE_SMPS + select STM32_HAVE_SMPS ---help--- Dual core STM32 H7 Cortex M7+M4, 2048 Kb FLASH, 1024K Kb SRAM TFBGA240 config ARCH_CHIP_STM32H750VB bool "STM32H750VB" - select STM32H7_STM32H7X0XX - select STM32H7_FLASH_CONFIG_B + select STM32_STM32H7X0XX + select STM32_FLASH_CONFIG_B select STM32H7_IO_CONFIG_V - select STM32H7_HAVE_CRYP + select STM32_HAVE_CRYP + select STM32_HAVE_IP_CRYPTO_H7 ---help--- STM32 H7 Cortex M7+M4, 128 Kb FLASH, 1024K Kb SRAM, with cryptographic accelerator, LQFP100 config ARCH_CHIP_STM32H750ZB bool "STM32H750ZB" - select STM32H7_STM32H7X0XX - select STM32H7_FLASH_CONFIG_B + select STM32_STM32H7X0XX + select STM32_FLASH_CONFIG_B select STM32H7_IO_CONFIG_Z - select STM32H7_HAVE_CRYP + select STM32_HAVE_CRYP + select STM32_HAVE_IP_CRYPTO_H7 ---help--- STM32 H7 Cortex M7+M4, 128 Kb FLASH, 1024K Kb SRAM, with cryptographic accelerator, LQFP144 config ARCH_CHIP_STM32H750IB bool "STM32H750IB" - select STM32H7_STM32H7X0XX - select STM32H7_FLASH_CONFIG_B + select STM32_STM32H7X0XX + select STM32_FLASH_CONFIG_B select STM32H7_IO_CONFIG_I - select STM32H7_HAVE_CRYP + select STM32_HAVE_CRYP + select STM32_HAVE_IP_CRYPTO_H7 ---help--- STM32 H7 Cortex M7+M4, 128 Kb FLASH, 1024K Kb SRAM, with cryptographic accelerator, LQFP176 or UFBGA176+25 config ARCH_CHIP_STM32H750XB bool "STM32H750XB" - select STM32H7_STM32H7X0XX - select STM32H7_FLASH_CONFIG_B + select STM32_STM32H7X0XX + select STM32_FLASH_CONFIG_B select STM32H7_IO_CONFIG_X - select STM32H7_HAVE_CRYP + select STM32_HAVE_CRYP + select STM32_HAVE_IP_CRYPTO_H7 ---help--- STM32 H7 Cortex M7+M4, 128 Kb FLASH, 1024K Kb SRAM, with cryptographic accelerator, TFBGA240+25 config ARCH_CHIP_STM32H753AI bool "STM32H753AI" - select STM32H7_STM32H7X3XX - select STM32H7_FLASH_CONFIG_I + select STM32_STM32H7X3XX + select STM32_FLASH_CONFIG_I select STM32H7_IO_CONFIG_A - select STM32H7_HAVE_CRYP + select STM32_HAVE_CRYP + select STM32_HAVE_IP_CRYPTO_H7 ---help--- STM32 H7 Cortex M7, 2048 Kb FLASH, 1024K Kb SRAM, with cryptographic accelerator, UFBGA169 config ARCH_CHIP_STM32H753BI bool "STM32H753BI" - select STM32H7_STM32H7X3XX - select STM32H7_FLASH_CONFIG_I + select STM32_STM32H7X3XX + select STM32_FLASH_CONFIG_I select STM32H7_IO_CONFIG_B - select STM32H7_HAVE_CRYP + select STM32_HAVE_CRYP + select STM32_HAVE_IP_CRYPTO_H7 ---help--- STM32 H7 Cortex M7, 2048 Kb FLASH, 1024K Kb SRAM, with cryptographic accelerator, LQFP208 config ARCH_CHIP_STM32H753II bool "STM32H753II" - select STM32H7_STM32H7X3XX - select STM32H7_FLASH_CONFIG_I + select STM32_STM32H7X3XX + select STM32_FLASH_CONFIG_I select STM32H7_IO_CONFIG_I - select STM32H7_HAVE_CRYP + select STM32_HAVE_CRYP + select STM32_HAVE_IP_CRYPTO_H7 ---help--- STM32 H7 Cortex M7, 2048 Kb FLASH, 1024K Kb SRAM, with cryptographic accelerator, LQFP176/UFBGA176 config ARCH_CHIP_STM32H753VI bool "STM32H753VI" - select STM32H7_STM32H7X3XX - select STM32H7_FLASH_CONFIG_I + select STM32_STM32H7X3XX + select STM32_FLASH_CONFIG_I select STM32H7_IO_CONFIG_V - select STM32H7_HAVE_CRYP + select STM32_HAVE_CRYP + select STM32_HAVE_IP_CRYPTO_H7 ---help--- STM32 H7 Cortex M7, 2048 Kb FLASH, 1024K Kb SRAM, with cryptographic accelerator, LQFP100/TFBGA100 config ARCH_CHIP_STM32H753XI bool "STM32H753XI" - select STM32H7_STM32H7X3XX - select STM32H7_FLASH_CONFIG_I + select STM32_STM32H7X3XX + select STM32_FLASH_CONFIG_I select STM32H7_IO_CONFIG_X - select STM32H7_HAVE_CRYP + select STM32_HAVE_CRYP + select STM32_HAVE_IP_CRYPTO_H7 ---help--- STM32 H7 Cortex M7, 2048 Kb FLASH, 1024K Kb SRAM, with cryptographic accelerator, TFBGA240 config ARCH_CHIP_STM32H753ZI bool "STM32H753ZI" - select STM32H7_STM32H7X3XX - select STM32H7_FLASH_CONFIG_I + select STM32_STM32H7X3XX + select STM32_FLASH_CONFIG_I select STM32H7_IO_CONFIG_Z - select STM32H7_HAVE_CRYP + select STM32_HAVE_CRYP + select STM32_HAVE_IP_CRYPTO_H7 ---help--- STM32 H7 Cortex M7, 2048 Kb FLASH, 1024K Kb SRAM, with cryptographic accelerator, LQFP144 config ARCH_CHIP_STM32H7B3LI bool "STM32H7B3LI" - select STM32H7_STM32H7B3XX - select STM32H7_FLASH_CONFIG_I + select STM32_STM32H7B3XX + select STM32_FLASH_CONFIG_I select STM32H7_IO_CONFIG_L - select STM32H7_HAVE_SMPS - select STM32H7_HAVE_CRYP + select STM32_HAVE_SMPS + select STM32_HAVE_CRYP + select STM32_HAVE_IP_CRYPTO_H7 ---help--- STM32 H7 Cortex M7, 2048 Kb FLASH, 1376 Kb SRAM, with cryptographic accelerator, TFBGA225 config ARCH_CHIP_STM32H755II bool "STM32H755II" - select STM32H7_STM32H7X5XX - select STM32H7_FLASH_CONFIG_I + select STM32_STM32H7X5XX + select STM32_FLASH_CONFIG_I select STM32H7_IO_CONFIG_I - select STM32H7_HAVE_FDCAN1 - select STM32H7_HAVE_FDCAN2 - select STM32H7_HAVE_CRYP + select STM32_HAVE_FDCAN1 + select STM32_HAVE_FDCAN2 + select STM32_HAVE_CRYP + select STM32_HAVE_IP_CRYPTO_H7 ---help--- STM32 H7 Cortex M7, 2048 Kb FLASH, 1024K Kb SRAM, with cryptographic accelerator, LQFP176/UFBGA176 config ARCH_CHIP_STM32H755XI bool "STM32H755XI" - select STM32H7_STM32H7X5XX - select STM32H7_FLASH_CONFIG_I + select STM32_STM32H7X5XX + select STM32_FLASH_CONFIG_I select STM32H7_IO_CONFIG_X - select STM32H7_HAVE_FDCAN1 - select STM32H7_HAVE_FDCAN2 - select STM32H7_HAVE_CRYP + select STM32_HAVE_FDCAN1 + select STM32_HAVE_FDCAN2 + select STM32_HAVE_CRYP + select STM32_HAVE_IP_CRYPTO_H7 ---help--- STM32 H7 Cortex M7, 2048 Kb FLASH, 1024K Kb SRAM, with cryptographic accelerator, TFBGA240 endchoice # STM32 H7 Chip Selection -config STM32H7_HAVE_SMPS - bool - default n - -config STM32H7_HAVE_PWR_DIRECT_SMPS_SUPPLY - bool - default n - -config STM32H7_PWR_DIRECT_SMPS_SUPPLY +config STM32_PWR_DIRECT_SMPS_SUPPLY bool "Use direct SMPS supply mode" - depends on STM32H7_HAVE_SMPS + depends on STM32_HAVE_SMPS default n -config STM32H7_PWR_EXTERNAL_SOURCE_SUPPLY +config STM32_PWR_EXTERNAL_SOURCE_SUPPLY bool "Use external source as power supply" default n ---help--- @@ -386,8 +428,8 @@ config STM32H7_PWR_EXTERNAL_SOURCE_SUPPLY choice prompt "STM32 H7 Power Supply Selection" - default STM32H7_PWR_DEFAULT_SUPPLY - depends on STM32H7_HAVE_SMPS && !STM32H7_HAVE_PWR_DIRECT_SMPS_SUPPLY + default STM32_PWR_DEFAULT_SUPPLY + depends on STM32_HAVE_SMPS && !STM32_HAVE_PWR_DIRECT_SMPS_SUPPLY ---help--- The STM32H7x5 and STM32H7x7 support power supply configurations for the VCORE core domain and an external supply, by configuring the SMPS step-down converter and voltage regulator. @@ -395,15 +437,15 @@ choice Currently the only supported modes are Direct SMPS supply and LDO supply. -config STM32H7_PWR_DEFAULT_SUPPLY +config STM32_PWR_DEFAULT_SUPPLY bool "Default" -config STM32H7_PWR_LDO_SUPPLY +config STM32_PWR_LDO_SUPPLY bool "Use LDO supply mode" endchoice # "STM32 H7 Power Supply Selection" -config STM32H7_PWR_IGNORE_ACTVOSRDY +config STM32_PWR_IGNORE_ACTVOSRDY bool "Ignore PWR_CSR1_ACTVOSRDY bit" default n ---help--- @@ -411,38 +453,45 @@ config STM32H7_PWR_IGNORE_ACTVOSRDY This is workaround for Renode simulation that doesn't implement this feature. config STM32H7_IO_CONFIG_A + # Package designator A bool default n config STM32H7_IO_CONFIG_B + # Package designator B bool default n config STM32H7_IO_CONFIG_I + # Package designator I bool default n config STM32H7_IO_CONFIG_L + # Package designator L bool default n config STM32H7_IO_CONFIG_V + # Package designator V bool default n config STM32H7_IO_CONFIG_X + # Package designator X bool default n config STM32H7_IO_CONFIG_Z + # Package designator Z bool default n config ARCH_STM32H7_DUALCORE bool default n - select STM32H7_HSEM if !STM32H7_CORTEXM4_DISABLED - select STM32H7_HAVE_CM4 + select STM32_HSEM if !STM32_CORTEXM4_DISABLED + select STM32_HAVE_CM4 choice prompt "STM32 H7 Core selection" @@ -463,141 +512,166 @@ config ARCH_CHIP_STM32H7_CORTEXM4 endchoice # STM32 H7 Core selection -config STM32H7_STM32H7X0XX +config STM32_STM32H7X0XX bool default n select ARCH_HAVE_FPU select ARCH_HAVE_DPFPU - select STM32H7_HAVE_LTDC - select STM32H7_HAVE_ETHERNET - select STM32H7_HAVE_FMC - select STM32H7_HAVE_GPIOF if !STM32H7_IO_CONFIG_V - select STM32H7_HAVE_GPIOG if !STM32H7_IO_CONFIG_V - select STM32H7_HAVE_SPI4 - select STM32H7_HAVE_SPI5 if !STM32H7_IO_CONFIG_V - select STM32H7_HAVE_SPI6 - select STM32H7_HAVE_RNG - -config STM32H7_STM32H7X3XX + select STM32_HAVE_FDCAN1 + select STM32_HAVE_FDCAN2 + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM3 + select STM32_HAVE_TIM4 + select STM32_HAVE_TIM5 + select STM32_HAVE_TIM6 + select STM32_HAVE_TIM7 + select STM32_HAVE_TIM8 + select STM32_HAVE_TIM12 + select STM32_HAVE_TIM13 + select STM32_HAVE_TIM14 + select STM32_HAVE_TIM15 + select STM32_HAVE_TIM16 + select STM32_HAVE_TIM17 + select STM32_HAVE_LTDC + select STM32_HAVE_ETHERNET + select STM32_HAVE_FMC + select STM32_HAVE_GPIOF if !STM32H7_IO_CONFIG_V + select STM32_HAVE_GPIOG if !STM32H7_IO_CONFIG_V + select STM32_HAVE_SPI4 + select STM32_HAVE_SPI5 if !STM32H7_IO_CONFIG_V + select STM32_HAVE_SPI6 + select STM32_HAVE_RNG + +config STM32_STM32H7X3XX bool default n select ARCH_HAVE_FPU select ARCH_HAVE_DPFPU - select STM32H7_HAVE_LTDC - select STM32H7_HAVE_ETHERNET - select STM32H7_HAVE_FMC - select STM32H7_HAVE_GPIOF if !STM32H7_IO_CONFIG_V - select STM32H7_HAVE_GPIOG if !STM32H7_IO_CONFIG_V - select STM32H7_HAVE_SPI4 - select STM32H7_HAVE_SPI5 if !STM32H7_IO_CONFIG_V - select STM32H7_HAVE_SPI6 - select STM32H7_HAVE_RNG - -config STM32H7_STM32H7B3XX + select STM32_HAVE_FDCAN1 + select STM32_HAVE_FDCAN2 + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM3 + select STM32_HAVE_TIM4 + select STM32_HAVE_TIM5 + select STM32_HAVE_TIM6 + select STM32_HAVE_TIM7 + select STM32_HAVE_TIM8 + select STM32_HAVE_TIM12 + select STM32_HAVE_TIM13 + select STM32_HAVE_TIM14 + select STM32_HAVE_TIM15 + select STM32_HAVE_TIM16 + select STM32_HAVE_TIM17 + select STM32_HAVE_LTDC + select STM32_HAVE_ETHERNET + select STM32_HAVE_FMC + select STM32_HAVE_GPIOF if !STM32H7_IO_CONFIG_V + select STM32_HAVE_GPIOG if !STM32H7_IO_CONFIG_V + select STM32_HAVE_SPI4 + select STM32_HAVE_SPI5 if !STM32H7_IO_CONFIG_V + select STM32_HAVE_SPI6 + select STM32_HAVE_RNG + +config STM32_STM32H7B3XX bool default n select ARCH_HAVE_FPU select ARCH_HAVE_DPFPU - select STM32H7_HAVE_ETHERNET - select STM32H7_HAVE_FMC - select STM32H7_HAVE_GPIOF if !STM32H7_IO_CONFIG_V - select STM32H7_HAVE_GPIOG if !STM32H7_IO_CONFIG_V - select STM32H7_HAVE_SPI4 - select STM32H7_HAVE_SPI5 if !STM32H7_IO_CONFIG_V - select STM32H7_HAVE_SPI6 - select STM32H7_HAVE_RNG - -config STM32H7_STM32H7X5XX + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM3 + select STM32_HAVE_TIM4 + select STM32_HAVE_TIM5 + select STM32_HAVE_TIM6 + select STM32_HAVE_TIM7 + select STM32_HAVE_TIM8 + select STM32_HAVE_TIM12 + select STM32_HAVE_TIM13 + select STM32_HAVE_TIM14 + select STM32_HAVE_TIM15 + select STM32_HAVE_TIM16 + select STM32_HAVE_TIM17 + select STM32_HAVE_ETHERNET + select STM32_HAVE_FMC + select STM32_HAVE_GPIOF if !STM32H7_IO_CONFIG_V + select STM32_HAVE_GPIOG if !STM32H7_IO_CONFIG_V + select STM32_HAVE_SPI4 + select STM32_HAVE_SPI5 if !STM32H7_IO_CONFIG_V + select STM32_HAVE_SPI6 + select STM32_HAVE_RNG + +config STM32_STM32H7X5XX bool default n select ARCH_STM32H7_DUALCORE select ARCH_HAVE_FPU select ARCH_HAVE_DPFPU - select STM32H7_HAVE_LTDC - select STM32H7_HAVE_ETHERNET - select STM32H7_HAVE_FMC - select STM32H7_HAVE_GPIOF if !STM32H7_IO_CONFIG_V - select STM32H7_HAVE_GPIOG if !STM32H7_IO_CONFIG_V - select STM32H7_HAVE_SPI4 - select STM32H7_HAVE_SPI5 if !STM32H7_IO_CONFIG_V - select STM32H7_HAVE_SPI6 - select STM32H7_HAVE_SMPS - select STM32H7_HAVE_RNG - -config STM32H7_STM32H7X7XX + select STM32_HAVE_FDCAN1 + select STM32_HAVE_FDCAN2 + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM3 + select STM32_HAVE_TIM4 + select STM32_HAVE_TIM5 + select STM32_HAVE_TIM6 + select STM32_HAVE_TIM7 + select STM32_HAVE_TIM8 + select STM32_HAVE_TIM12 + select STM32_HAVE_TIM13 + select STM32_HAVE_TIM14 + select STM32_HAVE_TIM15 + select STM32_HAVE_TIM16 + select STM32_HAVE_TIM17 + select STM32_HAVE_LTDC + select STM32_HAVE_ETHERNET + select STM32_HAVE_FMC + select STM32_HAVE_GPIOF if !STM32H7_IO_CONFIG_V + select STM32_HAVE_GPIOG if !STM32H7_IO_CONFIG_V + select STM32_HAVE_SPI4 + select STM32_HAVE_SPI5 if !STM32H7_IO_CONFIG_V + select STM32_HAVE_SPI6 + select STM32_HAVE_SMPS + select STM32_HAVE_RNG + +config STM32_STM32H7X7XX bool default n select ARCH_STM32H7_DUALCORE select ARCH_HAVE_FPU select ARCH_HAVE_DPFPU - select STM32H7_HAVE_LTDC - select STM32H7_HAVE_ETHERNET - select STM32H7_HAVE_FMC - select STM32H7_HAVE_GPIOF - select STM32H7_HAVE_GPIOG - select STM32H7_HAVE_SPI4 - select STM32H7_HAVE_SPI5 - select STM32H7_HAVE_SPI6 - select STM32H7_HAVE_RNG + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM3 + select STM32_HAVE_TIM4 + select STM32_HAVE_TIM5 + select STM32_HAVE_TIM6 + select STM32_HAVE_TIM7 + select STM32_HAVE_TIM8 + select STM32_HAVE_TIM12 + select STM32_HAVE_TIM13 + select STM32_HAVE_TIM14 + select STM32_HAVE_TIM15 + select STM32_HAVE_TIM16 + select STM32_HAVE_TIM17 + select STM32_HAVE_LTDC + select STM32_HAVE_ETHERNET + select STM32_HAVE_FMC + select STM32_HAVE_GPIOF + select STM32_HAVE_GPIOG + select STM32_HAVE_SPI4 + select STM32_HAVE_SPI5 + select STM32_HAVE_SPI6 + select STM32_HAVE_RNG # The reduced SRAM configuration STM32H72X and STM32H73X -config STM32H7_STM32H72XXX_OR_STM32H73XXX - bool - default n - -config STM32H7_FLASH_CONFIG_B - bool - default n - -config STM32H7_FLASH_CONFIG_G - bool - default n - -config STM32H7_FLASH_CONFIG_I +config STM32_STM32H72XXX_OR_STM32H73XXX bool default n -choice - prompt "Override Flash Size Designator" - depends on ARCH_CHIP_STM32H7 - default STM32H7_FLASH_OVERRIDE_DEFAULT - ---help--- - STM32H7 series parts numbering (sans the package type) ends with a - letter that designates the FLASH size. - - Designator Size in KiB - B 128 - G 1024 - I 2048 - - This configuration option defaults to using the configuration based - on that designator or the default smaller size if there is no last - character designator is present in the STM32 Chip Selection. - - Examples: - - If the STM32H743ZI is chosen, the Flash configuration would be - 'I', if a variant of the part is released in the future one - could simply select another designator here. - - If an STM32H7xxx Series parts is chosen the default Flash - configuration will be set herein and can be changed. - -config STM32H7_FLASH_OVERRIDE_DEFAULT - bool "Default" - -config STM32H7_FLASH_OVERRIDE_B - bool "B 128KiB" - -config STM32H7_FLASH_OVERRIDE_G - bool "G 1048KiB" -config STM32H7_FLASH_OVERRIDE_I - bool "I 2048KiB" - -endchoice # "Override Flash Size Designator" - -config STM32H7_FLASH_CR_PSIZE +config STM32_FLASH_CR_PSIZE int "Flash program size width" depends on ARCH_CHIP_STM32H7 default 3 @@ -611,7 +685,7 @@ config STM32H7_FLASH_CR_PSIZE 2: 32 bits 3: 64 bits (default) -config STM32H7_AXI_SRAM_CORRUPTION_WAR +config STM32_AXI_SRAM_CORRUPTION_WAR bool "Errata 2.2.9 Reading from AXI SRAM data read corruption Workaround" default y ---help--- @@ -631,47 +705,36 @@ if ARCH_STM32H7_DUALCORE if ARCH_CHIP_STM32H7_CORTEXM7 -config STM32H7_CORTEXM4_ENABLED +config STM32_CORTEXM4_ENABLED bool "Enable support for M4 core" default y -config STM32H7_CORTEXM7_BOOTM4 +config STM32_CORTEXM7_BOOTM4 bool "Boot M4 core" - select STM32H7_SYSCFG - default y if STM32H7_CORTEXM4_ENABLED + select STM32_SYSCFG + default y if STM32_CORTEXM4_ENABLED default n endif # ARCH_CHIP_STM32H7_CORTEXM7 -config STM32H7_CORTEXM7_FLASH_SIZE +config STM32_CORTEXM7_FLASH_SIZE int "Flash reserved for M7 core" - default 1048576 if STM32H7_CORTEXM4_ENABLED || ARCH_CHIP_STM32H7_CORTEXM4 + default 1048576 if STM32_CORTEXM4_ENABLED || ARCH_CHIP_STM32H7_CORTEXM4 default 2097152 -config STM32H7_CORTEXM7_SHMEM +config STM32_CORTEXM7_SHMEM bool select ARM_MPU if ARCH_CHIP_STM32H7_CORTEXM7 - default y if STM32H7_CORTEXM4_ENABLED || ARCH_CHIP_STM32H7_CORTEXM4 + default y if STM32_CORTEXM4_ENABLED || ARCH_CHIP_STM32H7_CORTEXM4 default n -config STM32H7_SHMEM_SRAM3 +config STM32_SHMEM_SRAM3 bool "Use SRAM3 as shared memory" - depends on STM32H7_CORTEXM7_SHMEM + depends on STM32_CORTEXM7_SHMEM default y endif # ARCH_STM32H7_DUALCORE -config STM32_HAVE_OTA_PARTITION - bool - default n - -config STM32H7_PROGMEM - bool "Flash progmem support" - default n - ---help--- - Add progmem support, start block and end block options are provided to - obtain an uniform flash memory mapping. - menu "Application Image Configuration" choice prompt "Application Image Format" @@ -711,5945 +774,22 @@ endchoice # Application Image Format endmenu # Application Image Configuration -menu "STM32H7 Peripheral Selection" - -# These "hidden" settings determine whether a peripheral option is available -# for the selected MCU - -config STM32H7_HAVE_CM4 - bool - default n - -config STM32H7_HAVE_LTDC - bool - default n - -config STM32H7_HAVE_ETHERNET - bool - default n - -config STM32H7_HAVE_PHY_POLLED - bool - default n - -config STM32H7_HAVE_FMC - bool - default n - -config STM32H7_HAVE_GPIOF - bool - default n - -config STM32H7_HAVE_GPIOG - bool - default n - -config STM32H7_HAVE_SPI4 - bool - default n - -config STM32H7_HAVE_SPI5 - bool - default n - -config STM32H7_HAVE_SPI6 - bool - default n - -config STM32H7_HAVE_FDCAN1 - bool - default n - -config STM32H7_HAVE_FDCAN2 - bool - default n - -config STM32H7_HAVE_FDCAN3 - bool - default n - -config STM32H7_HAVE_RNG - bool - default n - -config STM32H7_HAVE_CRYP - bool - default n - -# These "hidden" settings are the OR of individual peripheral selections -# indicating that the general capability is required. - -config STM32H7_ADC - bool - default n - -config STM32H7_FDCAN - bool - select NET_CAN_HAVE_ERRORS - select NET_CAN_HAVE_CANFD - select NET_CAN_EXTID - select NET_CAN_HAVE_TX_DEADLINE - default n - -config STM32H7_DAC - bool - default n - -config STM32H7_DMA - bool - default n - -config STM32H7_I2C - bool - default n - -config STM32H7_SAI - bool - default n - -config STM32H7_SDMMC - bool - default n - -config STM32H7_SPI - bool - default n - -config STM32H7_SPI_DMA - bool - default n - -config STM32H7_TIM - bool - default n - -config STM32H7_LPTIM - bool - default n - -config STM32H7_HSEM - bool "Hardware semaphore" - default n - -config STM32H7_RTC - bool "RTC" - default n - select RTC - -config STM32H7_CSI - bool "CSI Low-speed internal oscillator (4MHz)" - default n - -config STM32H7_HSI48 - bool "HSI48 High-speed 48MHz internal oscillator" - default n - -config STM32H7_PWR - bool "PWR" - default n - -config STM32H7_PWM - bool - default n - -config STM32H7_USART - bool - default n - -# These are the peripheral selections proper -config STM32H7_ADC1 - bool "ADC1" - default n - select STM32H7_ADC - -config STM32H7_ADC2 - bool "ADC2" - default n - select STM32H7_ADC - -config STM32H7_ADC3 - bool "ADC3" - default n - select STM32H7_ADC - -config STM32H7_RNG - bool "RNG" - default n - depends on STM32H7_HAVE_RNG - select ARCH_HAVE_RNG - -config STM32H7_CRC - bool "CRC" - default n - -config STM32H7_CRYP - bool "CRYP" - default n - depends on STM32H7_HAVE_CRYP - -config STM32H7_BKPSRAM - bool "Enable BKP RAM Domain" - select STM32H7_PWR - default n - -config STM32H7_DMA1 - bool "DMA1" - default n - select STM32H7_DMA - select ARCH_DMA - -config STM32H7_DMA2 - bool "DMA2" - default n - select STM32H7_DMA - select ARCH_DMA - -config STM32H7_MDMA - bool "MDMA" - default n - depends on EXPERIMENTAL - select STM32H7_DMA - select ARCH_DMA - -config STM32H7_BDMA - bool "BDMA" - default n - depends on EXPERIMENTAL - select STM32H7_DMA - select ARCH_DMA - -config STM32H7_ETHMAC - bool "Ethernet MAC" - default n - depends on STM32H7_HAVE_ETHERNET - select NETDEVICES - select ARCH_HAVE_PHY - select STM32H7_HAVE_PHY_POLLED - -config STM32H7_FMC - bool "FMC" - default n - depends on STM32H7_HAVE_FMC +config STM32_BYPASS_CLOCKCONFIG + bool "Bypass clock configuration" + depends on ARCH_STM32H7_DUALCORE + default n if ARCH_CHIP_STM32H7_CORTEXM7 + default y if ARCH_CHIP_STM32H7_CORTEXM4 ---help--- - Enable Flexible Memory Controller. - To correctly configure FMC for your hardware, you will have to define - a number of macros in your board.h file. See stm32_fmc.c for directions. - -config STM32H7_OTGFS - bool "OTG FS" - default n - select USBHOST_HAVE_ASYNCH if USBHOST - -config STM32H7_OTGHS - bool "OTG FS/HS" - default n - depends on EXPERIMENTAL - select USBHOST_HAVE_ASYNCH if USBHOST - -config STM32H7_OTG_SOFOUTPUT - bool "OTG SOF output" - default n - -config STM32H7_OTG_USBREGEN - bool "Enable USB voltage regulator" - default n - -config STM32H7_QUADSPI - bool "QuadSPI" - default n - -config STM32H7_USBDEV_REGDEBUG - bool "OTG USBDEV REGDEBUG" - default n - depends on USBDEV - -config STM32H7_USBHOST_REGDEBUG - bool "OTG USBHOST REGDEBUG" - default n - depends on USBHOST - -config STM32H7_USBHOST_PKTDUMP - bool "OTG USBHOST PKTDUMP" - default n - depends on USBHOST - -config STM32H7_SDMMC1 - bool "SDMMC1" - default n - select STM32H7_SDMMC - select ARCH_HAVE_SDIO - select ARCH_HAVE_SDIOWAIT_WRCOMPLETE - select ARCH_HAVE_SDIO_PREFLIGHT - select SDIO_BLOCKSETUP - -config STM32H7_SDMMC2 - bool "SDMMC2" - default n - select STM32H7_SDMMC - select ARCH_HAVE_SDIO - select ARCH_HAVE_SDIOWAIT_WRCOMPLETE - select ARCH_HAVE_SDIO_PREFLIGHT - select SDIO_BLOCKSETUP - -config STM32H7_IWDG - bool "IWDG" - default n - select WATCHDOG - -config STM32H7_WWDG - bool "WWDG" - default n - select WATCHDOG - -menu "STM32H7 FDCAN Selection" - -config STM32H7_FDCAN1 - bool "FDCAN1" - default n - select STM32H7_FDCAN - -config STM32H7_FDCAN2 - bool "FDCAN2" - default n - select STM32H7_FDCAN - -config STM32H7_FDCAN3 - bool "FDCAN3" - default n - select STM32H7_FDCAN - -endmenu # STM32H7 FDCAN Selection - -menu "STM32H7 I2C Selection" - -config STM32H7_I2C1 - bool "I2C1" - default n - select STM32H7_I2C - -config STM32H7_I2C2 - bool "I2C2" - default n - select STM32H7_I2C - -config STM32H7_I2C3 - bool "I2C3" - default n - select STM32H7_I2C - -config STM32H7_I2C4 - bool "I2C4" - default n - select STM32H7_I2C - -endmenu # STM32H7 I2C Selection + Bypass clock configuration. For dual core chips only one core + should configure clocks -config STM32H7_LTDC - bool "LTDC" +config STM32_SRAM4EXCLUDE + bool "Exclude SRAM4 from the heap" + default y if RPTUN default n - select FB - depends on STM32H7_HAVE_LTDC ---help--- - The STM32 LTDC is an LCD-TFT Display Controller available on - the STM32H7 devices. - It features a standard RGB888 parallel video interface (along - with HSYNC, VSYNC, etc.) for controlling TFT LCD displays. - In some STM32H7 devices the graphics signals can optionally - be output via DSI instead of the parallel interface: - See config options STM32H7_DSIHOST and STM32H7_LTDC_USE_DSI. - -menu "STM32H7 SPI Selection" - -config STM32H7_SPI1 - bool "SPI1" - default n - select SPI - select STM32H7_SPI - -config STM32H7_SPI2 - bool "SPI2" - default n - select SPI - select STM32H7_SPI - -config STM32H7_SPI3 - bool "SPI3" - default n - select SPI - select STM32H7_SPI - -config STM32H7_SPI4 - bool "SPI4" - default n - depends on STM32H7_HAVE_SPI4 - select SPI - select STM32H7_SPI - -config STM32H7_SPI5 - bool "SPI5" - default n - depends on STM32H7_HAVE_SPI5 - select SPI - select STM32H7_SPI - -config STM32H7_SPI6 - bool "SPI6" - default n - depends on STM32H7_HAVE_SPI6 - select SPI - select STM32H7_SPI - -endmenu # STM32H7 SPI Selection - -config STM32H7_SYSCFG - bool "SYSCFG" - default y - -menu "STM32H7 Timer Selection" - -config STM32H7_TIM1 - bool "TIM1" - default n - select STM32H7_TIM - -config STM32H7_TIM2 - bool "TIM2" - default n - select STM32H7_TIM - -config STM32H7_TIM3 - bool "TIM3" - default n - select STM32H7_TIM - -config STM32H7_TIM4 - bool "TIM4" - default n - select STM32H7_TIM - -config STM32H7_TIM5 - bool "TIM5" - default n - select STM32H7_TIM - -config STM32H7_TIM6 - bool "TIM6" - default n - select STM32H7_TIM - -config STM32H7_TIM7 - bool "TIM7" - default n - select STM32H7_TIM - -config STM32H7_TIM8 - bool "TIM8" - default n - select STM32H7_TIM - -config STM32H7_TIM12 - bool "TIM12" - default n - select STM32H7_TIM - -config STM32H7_TIM13 - bool "TIM13" - default n - select STM32H7_TIM - -config STM32H7_TIM14 - bool "TIM14" - default n - select STM32H7_TIM - -config STM32H7_TIM15 - bool "TIM15" - default n - select STM32H7_TIM - -config STM32H7_TIM16 - bool "TIM16" - default n - select STM32H7_TIM - -config STM32H7_TIM17 - bool "TIM17" - default n - select STM32H7_TIM - -endmenu # STM32H7 Timer Selection - -menu "STM32H7 Low-power Timer Selection" - -config STM32H7_LPTIM1 - bool "LPTIM1" - default n - select STM32H7_LPTIM - -config STM32H7_LPTIM2 - bool "LPTIM2" - default n - select STM32H7_LPTIM - -config STM32H7_LPTIM3 - bool "LPTIM3" - default n - select STM32H7_LPTIM - -config STM32H7_LPTIM4 - bool "LPTIM4" - default n - select STM32H7_LPTIM - -config STM32H7_LPTIM5 - bool "LPTIM5" - default n - select STM32H7_LPTIM - -endmenu # STM32H7 Low-power Timer Selection - -menu "STM32H7 U[S]ART Selection" - -config STM32H7_USART1 - bool "USART1" - default n - select USART1_SERIALDRIVER - select ARCH_HAVE_SERIAL_TERMIOS - select STM32H7_USART - -config STM32H7_USART2 - bool "USART2" - default n - select USART2_SERIALDRIVER - select ARCH_HAVE_SERIAL_TERMIOS - select STM32H7_USART - -config STM32H7_USART3 - bool "USART3" - default n - select ARCH_HAVE_SERIAL_TERMIOS - select USART3_SERIALDRIVER - select STM32H7_USART - -config STM32H7_UART4 - bool "UART4" - default n - select ARCH_HAVE_SERIAL_TERMIOS - select UART4_SERIALDRIVER - select STM32H7_USART - -config STM32H7_UART5 - bool "UART5" - default n - select ARCH_HAVE_SERIAL_TERMIOS - select UART5_SERIALDRIVER - select STM32H7_USART - -config STM32H7_USART6 - bool "USART6" - default n - select ARCH_HAVE_SERIAL_TERMIOS - select USART6_SERIALDRIVER - select STM32H7_USART - -config STM32H7_UART7 - bool "UART7" - default n - select ARCH_HAVE_SERIAL_TERMIOS - select UART7_SERIALDRIVER - select STM32H7_USART - -config STM32H7_UART8 - bool "UART8" - default n - select ARCH_HAVE_SERIAL_TERMIOS - select UART8_SERIALDRIVER - select STM32H7_USART - -endmenu # STM32H7 U[S]ART Selection -endmenu # STM32H7 Peripheral Selection - -config STM32H7_SYSCFG_IOCOMPENSATION - bool "SYSCFG I/O Compensation" - default n - select STM32H7_CSI - ---help--- - By default the I/O compensation cell is not used. However when the I/O - output buffer speed is configured in 50 MHz or 100 MHz mode, it is - recommended to use the compensation cell for slew rate control on I/O - tf(IO)out)/tr(IO)out commutation to reduce the I/O noise on power supply. - - The I/O compensation cell can be used only when the supply voltage ranges - from 2.4 to 3.6 V - -menu "OTG_HS Configuration" - depends on STM32H7_OTGHS - -config STM32H7_OTGHS_FS - bool "OTGHS in FS mode" - default n - -choice - prompt "ULPI Selection" - default STM32H7_OTGHS_NO_ULPI - -config STM32H7_OTGHS_NO_ULPI - bool "No External ULPI on board." - ---help--- - Select to indicate that there is no external ULPI PHY. This means the OTG_HS - peripheral must use the internal full-speed PHY and will be limited to - full-speed mode. - -config STM32H7_OTGHS_EXTERNAL_ULPI - bool "External ULPI" - ---help--- - Select to indicate the presence of an external ULPI PHY and use it. - -endchoice #"ULPI Selection" - -endmenu # OTG_HS Config - -menu "I2C Configuration" - depends on STM32H7_I2C - -config STM32H7_I2C_DYNTIMEO - bool "Use dynamic timeouts" - default n - depends on STM32H7_I2C - -config STM32H7_I2C_DYNTIMEO_USECPERBYTE - int "Timeout Microseconds per Byte" - default 500 - depends on STM32H7_I2C_DYNTIMEO - -config STM32H7_I2C_DYNTIMEO_STARTSTOP - int "Timeout for Start/Stop (Milliseconds)" - default 1000 - depends on STM32H7_I2C_DYNTIMEO - -config STM32H7_I2CTIMEOSEC - int "Timeout seconds" - default 0 - depends on STM32H7_I2C - -config STM32H7_I2CTIMEOMS - int "Timeout Milliseconds" - default 500 - depends on STM32H7_I2C && !STM32H7_I2C_DYNTIMEO - -config STM32H7_I2CTIMEOTICKS - int "Timeout for Done and Stop (ticks)" - default 500 - depends on STM32H7_I2C && !STM32H7_I2C_DYNTIMEO - -endmenu # "I2C Configuration" - -menu "OTG Configuration" - depends on STM32H7_OTGFS || STM32H7_OTGHS - -config OTG_ID_GPIO_DISABLE - bool "Disable the use of GPIO_OTG_ID pin." - default n - ---help--- - Disables/Enables the use of GPIO_OTG_ID pin. This allows non OTG use - cases to reuse this GPIO pin and ensure it is not set incorrectlty - during OS boot. - -choice - prompt "STM32H7 OTGFS role" - depends on STM32H7_OTGFS - default STM32H7_OTGFS_USBDEV if USBDEV - default STM32H7_OTGFS_HOST if !USBDEV && USBHOST - -config STM32H7_OTGFS_USBDEV - bool "OTGFS as USBDEV" - depends on USBDEV - -config STM32H7_OTGFS_HOST - bool "OTGFS as HOST" - depends on USBHOST - -endchoice # "STM32H7 OTGFS role" - -choice - prompt "STM32H7 OTGHS role (only USBDEV supported for now)" - depends on STM32H7_OTGHS - default STM32H7_OTGHS_USBDEV if USBDEV - -config STM32H7_OTGHS_USBDEV - bool "OTGHS as USBDEV" - depends on USBDEV - -endchoice # "STM32H7 OTGHS role" - -endmenu # OTG Configuration - -menu "SPI Configuration" - depends on STM32H7_SPI - -config STM32H7_SPI_INTERRUPTS - bool "Interrupt driver SPI" - default n - ---help--- - Select to enable interrupt driven SPI support. Non-interrupt-driven, - poll-waiting is recommended if the interrupt rate would be to high in - the interrupt driven case. - -config STM32H7_SPI_DMATHRESHOLD - int "SPI DMA threshold" - default 4 - depends on STM32H7_SPI_DMA - ---help--- - When SPI DMA is enabled, small DMA transfers will still be performed - by polling logic. But we need a threshold value to determine what - is small. - -config STM32H7_SPI1_DMA - bool "SPI1 DMA" - default n - depends on STM32H7_SPI1 && !STM32H7_SPI_INTERRUPT - select STM32H7_SPI_DMA - ---help--- - Use DMA to improve SPI1 transfer performance. Cannot be used with STM32H7_SPI_INTERRUPT - -config STM32H7_SPI1_DMA_BUFFER - int "SPI1 DMA buffer size" - default 0 - depends on STM32H7_SPI1_DMA - ---help--- - Add a properly aligned DMA buffer for RX and TX DMA for SPI1. - -config STM32H7_SPI1_COMMTYPE - int "SPI1 Operation mode" - default 0 - range 0 3 - depends on STM32H7_SPI1 - ---help--- - Select full-duplex (0), simplex tx (1), simplex rx (2) or half-duplex (3) - -config STM32H7_SPI2_DMA - bool "SPI2 DMA" - default n - depends on STM32H7_SPI2 && !STM32H7_SPI_INTERRUPT - select STM32H7_SPI_DMA - ---help--- - Use DMA to improve SPI2 transfer performance. Cannot be used with STM32H7_SPI_INTERRUPT - -config STM32H7_SPI2_DMA_BUFFER - int "SPI2 DMA buffer size" - default 0 - depends on STM32H7_SPI2_DMA - ---help--- - Add a properly aligned DMA buffer for RX and TX DMA for SPI2. - -config STM32H7_SPI2_COMMTYPE - int "SPI2 Operation mode" - default 0 - range 0 3 - depends on STM32H7_SPI2 - ---help--- - Select full-duplex (0), simplex tx (1), simplex rx (2) or half-duplex (3) - -config STM32H7_SPI3_DMA - bool "SPI3 DMA" - default n - depends on STM32H7_SPI3 && !STM32H7_SPI_INTERRUPT - select STM32H7_SPI_DMA - ---help--- - Use DMA to improve SPI3 transfer performance. Cannot be used with STM32H7_SPI_INTERRUPT - -config STM32H7_SPI3_DMA_BUFFER - int "SPI3 DMA buffer size" - default 0 - depends on STM32H7_SPI3_DMA - ---help--- - Add a properly aligned DMA buffer for RX and TX DMA for SPI3. - -config STM32H7_SPI3_COMMTYPE - int "SPI3 Operation mode" - default 0 - range 0 3 - depends on STM32H7_SPI3 - ---help--- - Select full-duplex (0), simplex tx (1), simplex rx (2) or half-duplex (3) - -config STM32H7_SPI4_DMA - bool "SPI4 DMA" - default n - depends on STM32H7_SPI4 && !STM32H7_SPI_INTERRUPT - select STM32H7_SPI_DMA - ---help--- - Use DMA to improve SPI4 transfer performance. Cannot be used with STM32H7_SPI_INTERRUPT - -config STM32H7_SPI4_DMA_BUFFER - int "SPI4 DMA buffer size" - default 0 - depends on STM32H7_SPI4_DMA - ---help--- - Add a properly aligned DMA buffer for RX and TX DMA for SPI4. - -config STM32H7_SPI4_COMMTYPE - int "SPI4 Operation mode" - default 0 - range 0 3 - depends on STM32H7_SPI4 - ---help--- - Select full-duplex (0), simplex tx (1), simplex rx (2) or half-duplex (3) - -config STM32H7_SPI5_DMA - bool "SPI5 DMA" - default n - depends on STM32H7_SPI5 && !STM32H7_SPI_INTERRUPT - select STM32H7_SPI_DMA - ---help--- - Use DMA to improve SPI5 transfer performance. Cannot be used with STM32H7_SPI_INTERRUPT - -config STM32H7_SPI5_DMA_BUFFER - int "SPI5 DMA buffer size" - default 0 - depends on STM32H7_SPI5_DMA - ---help--- - Add a properly aligned DMA buffer for RX and TX DMA for SPI5. - -config STM32H7_SPI5_COMMTYPE - int "SPI5 Operation mode" - default 0 - range 0 3 - depends on STM32H7_SPI5 - ---help--- - Select full-duplex (0), simplex tx (1), simplex rx (2) or half-duplex (3) - -config STM32H7_SPI6_DMA - bool "SPI6 DMA" - default n - depends on STM32H7_SPI6 && !STM32H7_SPI_INTERRUPT - select STM32H7_SPI_DMA - ---help--- - Use DMA to improve SPI6 transfer performance. Cannot be used with STM32H7_SPI_INTERRUPT - -config STM32H7_SPI6_DMA_BUFFER - int "SPI6 DMA buffer size" - default 0 - depends on STM32H7_SPI6_DMA - ---help--- - Add a properly aligned DMA buffer for RX and TX DMA for SPI6. - -config STM32H7_SPI6_COMMTYPE - int "SPI6 Operation mode" - default 0 - range 0 3 - depends on STM32H7_SPI6 - ---help--- - Select full-duplex (0), simplex tx (1), simplex rx (2) or half-duplex (3) - -endmenu # "SPI Configuration" - -menu "U[S]ART Configuration" - depends on STM32H7_USART - -if STM32H7_USART1 - -config USART1_RS485 - bool "RS-485 on USART1" - default n - ---help--- - Enable RS-485 interface on USART1. Your board config will have to - provide GPIO_USART1_RS485_DIR pin definition. - -config USART1_RS485_DIR_POLARITY - int "USART1 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on USART1_RS485 - ---help--- - Polarity of DIR pin for RS-485 on USART1. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config USART1_RXFIFO_THRES - int "USART1 Rx FIFO Threshold" - default 3 - range 0 5 - ---help--- - Select the Rx FIFO threshold: - - 0 -> 1/8 full - 1 -> 1/4 full - 2 -> 1/2 full - 3 -> 3/4 full - 4 -> 7/8 full - 5 -> Full - - Higher values mean lower interrupt rates and better CPU performance. - Lower values may be needed at high BAUD rates to prevent Rx data - overrun errors. - -endif # STM32H7_USART1 - -if STM32H7_USART2 - -config USART2_RS485 - bool "RS-485 on USART2" - default n - ---help--- - Enable RS-485 interface on USART2. Your board config will have to - provide GPIO_USART2_RS485_DIR pin definition. - -config USART2_RS485_DIR_POLARITY - int "USART2 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on USART2_RS485 - ---help--- - Polarity of DIR pin for RS-485 on USART2. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config USART2_RXFIFO_THRES - int "USART2 Rx FIFO Threshold" - default 3 - range 0 5 - ---help--- - Select the Rx FIFO threshold: - - 0 -> 1/8 full - 1 -> 1/4 full - 2 -> 1/2 full - 3 -> 3/4 full - 4 -> 7/8 full - 5 -> Full - - Higher values mean lower interrupt rates and better CPU performance. - Lower values may be needed at high BAUD rates to prevent Rx data - overrun errors. - -endif # STM32H7_USART2 - -if STM32H7_USART3 - -config USART3_RS485 - bool "RS-485 on USART3" - default n - ---help--- - Enable RS-485 interface on USART3. Your board config will have to - provide GPIO_USART3_RS485_DIR pin definition. - -config USART3_RS485_DIR_POLARITY - int "USART3 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on USART3_RS485 - ---help--- - Polarity of DIR pin for RS-485 on USART3. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config USART3_RXFIFO_THRES - int "USART3 Rx FIFO Threshold" - default 3 - range 0 5 - ---help--- - Select the Rx FIFO threshold: - - 0 -> 1/8 full - 1 -> 1/4 full - 2 -> 1/2 full - 3 -> 3/4 full - 4 -> 7/8 full - 5 -> Full - - Higher values mean lower interrupt rates and better CPU performance. - Lower values may be needed at high BAUD rates to prevent Rx data - overrun errors. - -endif # STM32H7_USART3 - -if STM32H7_UART4 - -config UART4_RS485 - bool "RS-485 on UART4" - default n - ---help--- - Enable RS-485 interface on UART4. Your board config will have to - provide GPIO_UART4_RS485_DIR pin definition. - -config UART4_RS485_DIR_POLARITY - int "UART4 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on UART4_RS485 - ---help--- - Polarity of DIR pin for RS-485 on UART4. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config UART4_RXFIFO_THRES - int "UART4 Rx FIFO Threshold" - default 3 - range 0 5 - ---help--- - Select the Rx FIFO threshold: - - 0 -> 1/8 full - 1 -> 1/4 full - 2 -> 1/2 full - 3 -> 3/4 full - 4 -> 7/8 full - 5 -> Full - - Higher values mean lower interrupt rates and better CPU performance. - Lower values may be needed at high BAUD rates to prevent Rx data - overrun errors. - -endif # STM32H7_UART4 - -if STM32H7_UART5 - -config UART5_RS485 - bool "RS-485 on UART5" - default n - ---help--- - Enable RS-485 interface on UART5. Your board config will have to - provide GPIO_UART5_RS485_DIR pin definition. - -config UART5_RS485_DIR_POLARITY - int "UART5 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on UART5_RS485 - ---help--- - Polarity of DIR pin for RS-485 on UART5. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config UART5_RXFIFO_THRES - int "UART5 Rx FIFO Threshold" - default 3 - range 0 5 - ---help--- - Select the Rx FIFO threshold: - - 0 -> 1/8 full - 1 -> 1/4 full - 2 -> 1/2 full - 3 -> 3/4 full - 4 -> 7/8 full - 5 -> Full - - Higher values mean lower interrupt rates and better CPU performance. - Lower values may be needed at high BAUD rates to prevent Rx data - overrun errors. - -endif # STM32H7_UART5 - -if STM32H7_USART6 - -config USART6_RS485 - bool "RS-485 on USART6" - default n - ---help--- - Enable RS-485 interface on USART6. Your board config will have to - provide GPIO_USART6_RS485_DIR pin definition. - -config USART6_RS485_DIR_POLARITY - int "USART6 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on USART6_RS485 - ---help--- - Polarity of DIR pin for RS-485 on USART6. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config USART6_RXFIFO_THRES - int "USART6 Rx FIFO Threshold" - default 3 - range 0 5 - ---help--- - Select the Rx FIFO threshold: - - 0 -> 1/8 full - 1 -> 1/4 full - 2 -> 1/2 full - 3 -> 3/4 full - 4 -> 7/8 full - 5 -> Full - - Higher values mean lower interrupt rates and better CPU performance. - Lower values may be needed at high BAUD rates to prevent Rx data - overrun errors. - -endif # STM32H7_USART - -if STM32H7_UART7 - -config UART7_RS485 - bool "RS-485 on UART7" - default n - ---help--- - Enable RS-485 interface on UART7. Your board config will have to - provide GPIO_UART7_RS485_DIR pin definition. - -config UART7_RS485_DIR_POLARITY - int "UART7 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on UART7_RS485 - ---help--- - Polarity of DIR pin for RS-485 on UART7. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config UART7_RXFIFO_THRES - int "UART7 Rx FIFO Threshold" - default 3 - range 0 5 - ---help--- - Select the Rx FIFO threshold: - - 0 -> 1/8 full - 1 -> 1/4 full - 2 -> 1/2 full - 3 -> 3/4 full - 4 -> 7/8 full - 5 -> Full - - Higher values mean lower interrupt rates and better CPU performance. - Lower values may be needed at high BAUD rates to prevent Rx data - overrun errors. - -endif # STM32H7_UART7 - -if STM32H7_UART8 - -config UART8_RS485 - bool "RS-485 on UART8" - default n - ---help--- - Enable RS-485 interface on UART8. Your board config will have to - provide GPIO_UART8_RS485_DIR pin definition. - -config UART8_RS485_DIR_POLARITY - int "UART8 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on UART8_RS485 - ---help--- - Polarity of DIR pin for RS-485 on UART8. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config UART8_RXFIFO_THRES - int "UART8 Rx FIFO Threshold" - default 3 - range 0 5 - ---help--- - Select the Rx FIFO threshold: - - 0 -> 1/8 full - 1 -> 1/4 full - 2 -> 1/2 full - 3 -> 3/4 full - 4 -> 7/8 full - 5 -> Full - - Higher values mean lower interrupt rates and better CPU performance. - Lower values may be needed at high BAUD rates to prevent Rx data - overrun errors. - -endif # STM32H7_UART8 - -config STM32H7_SERIAL_RXDMA_BUFFER_SIZE - int "Rx DMA buffer size" - default 32 - depends on USART1_RXDMA || USART2_RXDMA || USART3_RXDMA || UART4_RXDMA || UART5_RXDMA || USART6_RXDMA || UART7_RXDMA || UART8_RXDMA - ---help--- - The DMA buffer size when using RX DMA to emulate a FIFO. - - When streaming data, the generic serial layer will be called - every time the FIFO receives half this number of bytes. - - Value given here will be rounded up to next multiple of 32 bytes. - -config STM32H7_SERIAL_DISABLE_REORDERING - bool "Disable reordering of ttySx devices." - default n - ---help--- - NuttX per default reorders the serial ports (/dev/ttySx) so that the - console is always on /dev/ttyS0. If more than one UART is in use this - can, however, have the side-effect that all port mappings - (hardware USART1 -> /dev/ttyS0) change if the console is moved to another - UART. This is in particular relevant if a project uses the USB console - in some boards and a serial console in other boards, but does not - want the side effect of having all serial port names change when just - the console is moved from serial to USB. - -config STM32H7_FLOWCONTROL_BROKEN - bool "Use Software UART RTS flow control" - depends on SERIAL_IFLOWCONTROL_WATERMARKS - default n - ---help--- - Enable UART RTS flow control using Software. Because STM - Current STM32 have broken HW based RTS behavior (they assert - nRTS after every byte received) Enable this setting workaround - this issue by using software based management of RTS - -config STM32H7_USART_BREAKS - bool "Add TIOxSBRK to support sending Breaks" - default n - ---help--- - Add TIOCxBRK routines to send a line break per the STM32 manual, the - break will be a pulse based on the value M. This is not a BSD compatible - break. - -config STM32H7_SERIALBRK_BSDCOMPAT - bool "Use GPIO To send Break" - depends on STM32H7_USART_BREAKS - default n - ---help--- - Enable using GPIO on the TX pin to send a BSD compatible break: - TIOCSBRK will start the break and TIOCCBRK will end the break. - The current STM32H7 U[S]ARTS have no way to leave the break on - (TX=LOW) because software starts the break and then the hardware - automatically clears the break. This makes it difficult to send - a long break. - -config STM32H7_USART_SINGLEWIRE - bool "Single Wire Support" - default n - depends on STM32H7_USART - ---help--- - Enable single wire UART support. The option enables support for the - TIOCSSINGLEWIRE ioctl in the STM32H7 serial driver. - -config STM32H7_USART_INVERT - bool "Signal Invert Support" - default n - depends on STM32H7_USART - ---help--- - Enable signal inversion UART support. The option enables support for the - TIOCSINVERT ioctl in the STM32H7 serial driver. - -config STM32H7_USART_SWAP - bool "Swap RX/TX pins support" - default n - depends on STM32H7_USART - ---help--- - Enable RX/TX pin swapping support. The option enables support for the - TIOCSSWAP ioctl in the STM32H7 serial driver. - -if PM - -config STM32H7_PM_SERIAL_ACTIVITY - int "PM serial activity" - default 10 - ---help--- - PM activity reported to power management logic on every serial - interrupt. - -endif # PM -endmenu # U[S]ART Configuration - -menu "ADC Configuration" - depends on STM32H7_ADC - -config STM32H7_ADC_MAX_SAMPLES - int "The maximum number of channels that can be sampled" - default 16 - ---help--- - The maximum number of samples which can be handled without - overrun depends on various factors. This is the user's - responsibility to correctly select this value. - Since the interface to update the sampling time is available - for all supported devices, the user can change the default - values in the board initialization logic and avoid ADC overrun. - -config STM32H7_ADC1_DMA - bool "ADC1 DMA (not supported yet)" - depends on STM32H7_ADC1 && EXPERIMENTAL - default n - ---help--- - If DMA is selected, then the ADC may be configured to support - DMA transfer, which is necessary if multiple channels are read - or if very high trigger frequencies are used. - -config STM32H7_ADC1_DMA_BATCH - int "ADC1 DMA number of conversions" - depends on STM32H7_ADC1 && STM32H7_ADC1_DMA - default 1 - ---help--- - This option allows you to select the number of regular group conversions - that will trigger a DMA callback transerring data to the upper-half driver. - By default, this value is 1, which means that data is transferred after - each group conversion. - -config STM32H7_ADC2_DMA - bool "ADC2 DMA (not supported yet)" - depends on STM32H7_ADC2 && EXPERIMENTAL - default n - ---help--- - If DMA is selected, then the ADC may be configured to support - DMA transfer, which is necessary if multiple channels are read - or if very high trigger frequencies are used. - -config STM32H7_ADC2_DMA_BATCH - int "ADC2 DMA number of conversions" - depends on STM32H7_ADC2 && STM32H7_ADC2_DMA - default 1 - ---help--- - This option allows you to select the number of regular group conversions - that will trigger a DMA callback transerring data to the upper-half driver. - By default, this value is 1, which means that data is transferred after - each group conversion. - -config STM32H7_ADC3_DMA - bool "ADC3 DMA (not supported yet)" - depends on STM32H7_ADC3 && EXPERIMENTAL - default n - ---help--- - If DMA is selected, then the ADC may be configured to support - DMA transfer, which is necessary if multiple channels are read - or if very high trigger frequencies are used. - -config STM32H7_ADC3_DMA_BATCH - int "ADC3 DMA number of conversions" - depends on STM32H7_ADC3 && STM32H7_ADC3_DMA - default 1 - ---help--- - This option allows you to select the number of regular group conversions - that will trigger a DMA callback transerring data to the upper-half driver. - By default, this value is 1, which means that data is transferred after - each group conversion. - -endmenu # ADC Configuration - -menu "SD/MMC Configuration" - depends on STM32H7_SDMMC - -config STM32H7_SDMMC_XFRDEBUG - bool "SDMMC transfer debug" - depends on DEBUG_FS_INFO - default n - ---help--- - Enable special debug instrumentation analyze SDMMC data transfers. - This logic is as non-invasive as possible: It samples SDMMC - registers at key points in the data transfer and then dumps all of - the registers at the end of the transfer. If DEBUG_DMA is also - enabled, then DMA register will be collected as well. Requires also - DEBUG_FS and CONFIG_DEBUG_INFO. - -config STM32H7_SDMMC_IDMA - bool "Support IDMA data transfers" - default y - select SDIO_DMA - ---help--- - Support IDMA data transfers. - -menu "SDMMC1 Configuration" - depends on STM32H7_SDMMC1 - -config SDMMC1_WIDTH_D1_ONLY - bool "Use D1 only on SDMMC1" - default n - ---help--- - Select 1-bit transfer mode. Default: 4-bit transfer mode. - -config SDMMC1_SDIO_MODE - bool "SDIO Card Support" - default n - ---help--- - Build in additional support needed only for SDIO cards (vs. SD - memory cards) - -config SDMMC1_SDIO_PULLUP - bool "Enable internal Pull-Ups" - default n - ---help--- - If you are using an external SDCard module that does not have the - pull-up resistors for the SDIO interface (like the Gadgeteer SD Card - Module) then enable this option to activate the internal pull-up - resistors. - -endmenu # "SDMMC1 Configuration" - -menu "SDMMC2 Configuration" - depends on STM32H7_SDMMC2 - -config SDMMC2_WIDTH_D1_ONLY - bool "Use D1 only on SDMMC2" - default n - ---help--- - Select 1-bit transfer mode. Default: 4-bit transfer mode. - -config SDMMC2_SDIO_MODE - bool "SDIO Card Support" - default n - ---help--- - Build in additional support needed only for SDIO cards (vs. SD - memory cards) - -config SDMMC2_SDIO_PULLUP - bool "Enable internal Pull-Ups" - default n - ---help--- - If you are using an external SDCard module that does not have the - pull-up resistors for the SDIO interface (like the Gadgeteer SD Card - Module) then enable this option to activate the internal pull-up - resistors. - -endmenu # "SDMMC2 Configuration" -endmenu # "SD/MMC Configuration" - -if STM32H7_BKPSRAM - -config STM32H7_BBSRAM - bool "BBSRAM File Support" - default n - select ARM_MPU - -config STM32H7_BBSRAM_FILES - int "Max Files to support in BBSRAM" - default 4 - depends on STM32H7_BBSRAM - -config STM32H7_SAVE_CRASHDUMP - bool "Enable Saving Panic to BBSRAM" - default n - depends on STM32H7_BBSRAM - -endif # STM32H7_BKPSRAM - -config STM32H7_HAVE_RTC_SUBSECONDS - bool - select ARCH_HAVE_RTC_SUBSECONDS - default y - -menu "RTC Configuration" - depends on STM32H7_RTC - -config STM32H7_RTC_MAGIC_REG - int "BKP register" - default 0 - range 0 31 - ---help--- - The BKP register used to store/check the Magic value to determine if - RTC is already setup - -config STM32H7_RTC_MAGIC - hex "RTC Magic 1" - default 0xfacefeed - ---help--- - Value used as Magic to determine if the RTC is already setup - -config STM32H7_RTC_MAGIC_TIME_SET - hex "RTC Magic 2" - default 0xf00dface - ---help--- - Value used as Magic to determine if the RTC has been setup and has - time set - -choice - prompt "RTC clock source" - default STM32H7_RTC_LSECLOCK - -config STM32H7_RTC_HSECLOCK - bool "HSE clock" - ---help--- - Drive the RTC with the HSE clock, divided down to 1MHz. - -config STM32H7_RTC_LSECLOCK - bool "LSE clock" - ---help--- - Drive the RTC with the LSE clock - -config STM32H7_RTC_LSICLOCK - bool "LSI clock" - ---help--- - Drive the RTC with the LSI clock - -endchoice #"RTC clock source" - -if STM32H7_RTC_LSECLOCK - -config STM32H7_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY - bool "Automatically boost the LSE oscillator drive capability level until it starts-up" - default n - ---help--- - This will cycle through the correct* values from low to high. To - avoid damaging the crystal, we want to use the lowest setting that - gets the OSC running. See app note AN2867 - - 0 = Low drive capability (default) - 1 = Medium low drive capability - 2 = Medium high drive capability - 3 = High drive capability - - *It will take into account the revision of the silicon and use - the correct code points to achieve the drive strength. - See Errata ES0392 Rev 7 2.2.14 LSE oscillator driving capability - selection bits are swapped. - -config STM32H7_RTC_LSECLOCK_START_DRV_CAPABILITY - int "LSE oscillator drive capability level at LSE start-up" - default 0 - range 0 3 - depends on !STM32H7_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY - ---help--- - 0 = Low drive capability (default) - 1 = Medium low drive capability - 2 = Medium high drive capability - 3 = High drive capability - - It will take into account the revision of the silicon and use - the correct code points to achieve the drive strength. - See Errata ES0392 Rev 7 2.2.14 LSE oscillator driving capability - selection bits are swapped. - -config STM32H7_RTC_LSECLOCK_RUN_DRV_CAPABILITY - int "LSE oscillator drive capability level after LSE start-up" - default 0 - range 0 3 - depends on !STM32H7_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY - ---help--- - 0 = Low drive capability (default) - 1 = Medium low drive capability - 2 = Medium high drive capability - 3 = High drive capability - - It will take into account the revision of the silicon and use - the correct code points to achieve the drive strength. - See Errata ES0392 Rev 7 2.2.14 LSE oscillator driving capability - selection bits are swapped. - - WARNING this RUN setting does not appear to work! It appears - that the LSEDRV bits cannot be changed once the OSC is running. - -endif # STM32H7_RTC_LSECLOCK - -endmenu # RTC Configuration - -menu "QuadSPI Configuration" - depends on STM32H7_QUADSPI - -config STM32H7_QSPI_FLASH_SIZE - int "Size of attached serial flash, bytes" - default 16777216 - range 1 2147483648 - ---help--- - The STM32H7 QSPI peripheral requires the size of the Flash be specified - -config STM32H7_QSPI_FIFO_THESHOLD - int "Number of bytes before asserting FIFO threshold flag" - default 4 - range 1 16 - ---help--- - The STM32H7 QSPI peripheral requires that the FIFO threshold be specified - I would leave it at the default value of 4 unless you know what you are doing. - -config STM32H7_QSPI_CSHT - int "Number of cycles Chip Select must be inactive between transactions" - default 1 - range 1 8 - ---help--- - The STM32H7 QSPI peripheral requires that it be specified the minimum number - of AHB cycles that Chip Select be held inactive between transactions. - -choice - prompt "Transfer technique" - default STM32H7_QSPI_DMA - ---help--- - You can choose between using polling, interrupts, or DMA to transfer data - over the QSPI interface. - -config STM32H7_QSPI_POLLING - bool "Polling" - ---help--- - Use conventional register I/O with status polling to transfer data. - -config STM32H7_QSPI_INTERRUPTS - bool "Interrupts" - ---help--- - User interrupt driven I/O transfers. - -config STM32H7_QSPI_DMA - bool "DMA" - depends on STM32H7_DMA - ---help--- - Use DMA to improve QSPI transfer performance. - -endchoice # Transfer technique - -choice - prompt "Bank selection" - default STM32H7_QSPI_MODE_BANK1 - ---help--- - You can choose between using polling, interrupts, or DMA to transfer data - over the QSPI interface. - -config STM32H7_QSPI_MODE_BANK1 - bool "Bank 1" - -config STM32H7_QSPI_MODE_BANK2 - bool "Bank 2" - -config STM32H7_QSPI_MODE_DUAL - bool "Dual Bank" - -endchoice # Bank selection - -choice - prompt "DMA Priority" - default STM32H7_QSPI_DMAPRIORITY_MEDIUM - depends on STM32H7_DMA - ---help--- - The DMA controller supports priority levels. You are probably fine - with the default of 'medium' except for special cases. In the event - of contention between to channels at the same priority, the lower - numbered channel has hardware priority over the higher numbered one. - -config STM32H7_QSPI_DMAPRIORITY_VERYHIGH - bool "Very High priority" - depends on STM32H7_DMA - ---help--- - 'Highest' priority. - -config STM32H7_QSPI_DMAPRIORITY_HIGH - bool "High priority" - depends on STM32H7_DMA - ---help--- - 'High' priority. - -config STM32H7_QSPI_DMAPRIORITY_MEDIUM - bool "Medium priority" - depends on STM32H7_DMA - ---help--- - 'Medium' priority. - -config STM32H7_QSPI_DMAPRIORITY_LOW - bool "Low priority" - depends on STM32H7_DMA - ---help--- - 'Low' priority. - -endchoice # DMA Priority - -config STM32H7_QSPI_DMATHRESHOLD - int "QSPI DMA threshold" - default 4 - depends on STM32H7_QSPI_DMA - ---help--- - When QSPI DMA is enabled, small DMA transfers will still be performed - by polling logic. This value is the threshold below which transfers - will still be performed by conventional register status polling. - -config STM32H7_QSPI_DMADEBUG - bool "QSPI DMA transfer debug" - depends on STM32H7_QSPI_DMA && DEBUG_SPI && DEBUG_DMA - default n - ---help--- - Enable special debug instrumentation to analyze QSPI DMA data transfers. - This logic is as non-invasive as possible: It samples DMA - registers at key points in the data transfer and then dumps all of - the registers at the end of the transfer. - -config STM32H7_QSPI_REGDEBUG - bool "QSPI Register level debug" - depends on DEBUG_SPI_INFO - default n - ---help--- - Output detailed register-level QSPI device debug information. - Requires also CONFIG_DEBUG_SPI_INFO. - -endmenu # QuadSPI Configuration - -config STM32H7_BYPASS_CLOCKCONFIG - bool "Bypass clock configuration" - depends on ARCH_STM32H7_DUALCORE - default n if ARCH_CHIP_STM32H7_CORTEXM7 - default y if ARCH_CHIP_STM32H7_CORTEXM4 - ---help--- - Bypass clock configuration. For dual core chips only one core - should configure clocks - -config STM32H7_CUSTOM_CLOCKCONFIG - bool "Custom clock configuration" - default n - ---help--- - Enables special, board-specific STM32 clock configuration. - -config STM32H7_SRAM4EXCLUDE - bool "Exclude SRAM4 from the heap" - default y if RPTUN - default n - ---help--- - Exclude SRAM4 from the HEAP in order to use this 64 KB region - for other uses, such as DMA buffers, etc. - -config STM32H7_DTCMEXCLUDE - bool "Exclude DTCM SRAM from the heap" - default LIBC_ARCH_ELF - depends on ARMV7M_HAVE_DTCM - ---help--- - Exclude DTCM SRAM from the HEAP because it appears to be impossible - to execute ELF modules from DTCM RAM (REVISIT!). - -config STM32H7_DTCM_PROCFS - bool "DTCM SRAM PROCFS support" - default n - depends on ARMV7M_DTCM && FS_PROCFS - ---help--- - Select to build in support for /proc/dtcm. Reading from /proc/dtcm - will provide statistics about DTCM memory use similar to what you - would get from mallinfo() for the user heap. - -config STM32H7_DMACAPABLE - bool "Workaround non-DMA capable memory" - depends on ARCH_DMA - default n - ---help--- - This option enables the DMA interface stm32_dmacapable that can be - used to check if it is possible to do DMA from the selected address. - Drivers then may use this information to determine if they should - attempt the DMA or fall back to a different transfer method. - -config STM32H7_DMACAPABLE_ASSUME_CACHE_ALIGNED - bool "Do not disqualify DMA capability based on cache alignment" - depends on STM32H7_DMACAPABLE && ARMV7M_DCACHE && !ARMV7M_DCACHE_WRITETHROUGH - default n - ---help--- - This option configures the stm32_dmacapable to not disqualify - DMA operations on memory that is not dcache aligned based solely - on the starting address and byte count. - - Use this when ALL buffer extents are known to be aligned, but the - the count does not use the complete buffer. - -menu "Timer Configuration" - -if SCHED_TICKLESS - -config STM32H7_TICKLESS_TIMER - int "Tickless hardware timer" - default 2 - range 1 17 - ---help--- - If the Tickless OS feature is enabled, then one clock must be - assigned to provided the timer needed by the OS. - -config STM32H7_TICKLESS_CHANNEL - int "Tickless timer channel" - default 1 - range 1 4 - ---help--- - If the Tickless OS feature is enabled, the one clock must be - assigned to provided the free-running timer needed by the OS - and one channel on that clock is needed to handle intervals. - -endif # SCHED_TICKLESS - -config STM32H7_ONESHOT - bool "TIM one-shot wrapper" - default n - ---help--- - Enable a wrapper around the low level timer/counter functions to - support one-shot timer. - -config STM32H7_ONESHOT_MAXTIMERS - int "Maximum number of oneshot timers" - default 1 - range 1 8 - depends on STM32H7_ONESHOT - ---help--- - Determines the maximum number of oneshot timers that can be - supported. This setting pre-allocates some minimal support for each - of the timers and places an upper limit on the number of oneshot - timers that you can use. - -config STM32H7_PWM_LL_OPS - bool "PWM low-level operations" - default n - ---help--- - Enable low-level PWM ops. - -config STM32H7_TIM1_PWM - bool "TIM1 PWM" - default n - depends on STM32H7_TIM1 - select STM32H7_PWM - ---help--- - Reserve timer 1 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32H7_TIM1 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32H7_TIM1_PWM - -config STM32H7_TIM1_MODE - int "TIM1 Mode" - default 0 - range 0 4 - ---help--- - Specifies the timer mode. - -config STM32H7_TIM1_LOCK - int "TIM1 Lock Level Configuration" - default 0 - range 0 3 - ---help--- - Timer 1 lock level configuration - -config STM32H7_TIM1_TDTS - int "TIM1 t_DTS Division" - default 0 - range 0 2 - ---help--- - Timer 1 dead-time and sampling clock (t_DTS) division - -config STM32H7_TIM1_DEADTIME - int "TIM1 Initial Dead-time" - default 0 - range 0 255 - ---help--- - Timer 1 initial dead-time - -if STM32H7_PWM_MULTICHAN - -config STM32H7_TIM1_CHANNEL1 - bool "TIM1 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32H7_TIM1_CHANNEL1 - -config STM32H7_TIM1_CH1MODE - int "TIM1 Channel 1 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H7_TIM1_CH1OUT - bool "TIM1 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -config STM32H7_TIM1_CH1NOUT - bool "TIM1 Channel 1 Complementary Output" - default n - ---help--- - Enables channel 1 Complementary Output. - -endif # STM32H7_TIM1_CHANNEL1 - -config STM32H7_TIM1_CHANNEL2 - bool "TIM1 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32H7_TIM1_CHANNEL2 - -config STM32H7_TIM1_CH2MODE - int "TIM1 Channel 2 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H7_TIM1_CH2OUT - bool "TIM1 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -config STM32H7_TIM1_CH2NOUT - bool "TIM1 Channel 2 Complementary Output" - default n - ---help--- - Enables channel 2 Complementary Output. - -endif # STM32H7_TIM1_CHANNEL2 - -config STM32H7_TIM1_CHANNEL3 - bool "TIM1 Channel 3" - default n - ---help--- - Enables channel 3. - -if STM32H7_TIM1_CHANNEL3 - -config STM32H7_TIM1_CH3MODE - int "TIM1 Channel 3 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H7_TIM1_CH3OUT - bool "TIM1 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -config STM32H7_TIM1_CH3NOUT - bool "TIM1 Channel 3 Complementary Output" - default n - ---help--- - Enables channel 3 Complementary Output. - -endif # STM32H7_TIM1_CHANNEL3 - -config STM32H7_TIM1_CHANNEL4 - bool "TIM1 Channel 4" - default n - ---help--- - Enables channel 4. - -if STM32H7_TIM1_CHANNEL4 - -config STM32H7_TIM1_CH4MODE - int "TIM1 Channel 4 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H7_TIM1_CH4OUT - bool "TIM1 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32H7_TIM1_CHANNEL4 - -config STM32H7_TIM1_CHANNEL5 - bool "TIM1 Channel 5 (internal)" - default n - ---help--- - Enables channel 5 (not available externally) - -if STM32H7_TIM1_CHANNEL5 - -config STM32H7_TIM1_CH5MODE - int "TIM1 Channel 5 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H7_TIM1_CH5OUT - bool "TIM1 Channel 5 Output" - default n - ---help--- - Enables channel 5 output. - -endif # STM32H7_TIM1_CHANNEL5 - -config STM32H7_TIM1_CHANNEL6 - bool "TIM1 Channel 6 (internal)" - default n - ---help--- - Enables channel 6 (not available externally) - -if STM32H7_TIM1_CHANNEL6 - -config STM32H7_TIM1_CH6MODE - int "TIM1 Channel 6 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H7_TIM1_CH6OUT - bool "TIM1 Channel 6 Output" - default n - ---help--- - Enables channel 6 output. - -endif # STM32H7_TIM1_CHANNEL6 - -endif # STM32H7_PWM_MULTICHAN - -if !STM32H7_PWM_MULTICHAN - -config STM32H7_TIM1_CHANNEL - int "TIM1 PWM Output Channel" - default 1 - range 1 4 - ---help--- - If TIM1 is enabled for PWM usage, you also need specifies the timer output - channel {1,..,4} - -if STM32H7_TIM1_CHANNEL = 1 - -config STM32H7_TIM1_CH1OUT - bool "TIM1 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -config STM32H7_TIM1_CH1NOUT - bool "TIM1 Channel 1 Complementary Output" - default n - ---help--- - Enables channel 1 Complementary Output. - -endif # STM32H7_TIM1_CHANNEL = 1 - -if STM32H7_TIM1_CHANNEL = 2 - -config STM32H7_TIM1_CH2OUT - bool "TIM1 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -config STM32H7_TIM1_CH2NOUT - bool "TIM1 Channel 2 Complementary Output" - default n - ---help--- - Enables channel 2 Complementary Output. - -endif # STM32H7_TIM1_CHANNEL = 2 - -if STM32H7_TIM1_CHANNEL = 3 - -config STM32H7_TIM1_CH3OUT - bool "TIM1 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -config STM32H7_TIM1_CH3NOUT - bool "TIM1 Channel 3 Complementary Output" - default n - ---help--- - Enables channel 3 Complementary Output. - -endif # STM32H7_TIM1_CHANNEL = 3 - -if STM32H7_TIM1_CHANNEL = 4 - -config STM32H7_TIM1_CH4OUT - bool "TIM1 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32H7_TIM1_CHANNEL = 4 - -config STM32H7_TIM1_CHMODE - int "TIM1 Channel Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32H7_PWM_MULTICHAN - -endif # STM32H7_TIM1_PWM - -config STM32H7_TIM2_PWM - bool "TIM2 PWM" - default n - depends on STM32H7_TIM2 - select STM32H7_PWM - ---help--- - Reserve timer 2 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32H7_TIM2 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32H7_TIM2_PWM - -config STM32H7_TIM2_MODE - int "TIM2 Mode" - default 0 - range 0 4 - ---help--- - Specifies the timer mode. - -if STM32H7_PWM_MULTICHAN - -config STM32H7_TIM2_CHANNEL1 - bool "TIM2 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32H7_TIM2_CHANNEL1 - -config STM32H7_TIM2_CH1MODE - int "TIM2 Channel 1 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H7_TIM2_CH1OUT - bool "TIM2 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32H7_TIM2_CHANNEL1 - -config STM32H7_TIM2_CHANNEL2 - bool "TIM2 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32H7_TIM2_CHANNEL2 - -config STM32H7_TIM2_CH2MODE - int "TIM2 Channel 2 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H7_TIM2_CH2OUT - bool "TIM2 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32H7_TIM2_CHANNEL2 - -config STM32H7_TIM2_CHANNEL3 - bool "TIM2 Channel 3" - default n - ---help--- - Enables channel 3. - -if STM32H7_TIM2_CHANNEL3 - -config STM32H7_TIM2_CH3MODE - int "TIM2 Channel 3 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H7_TIM2_CH3OUT - bool "TIM2 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -endif # STM32H7_TIM2_CHANNEL3 - -config STM32H7_TIM2_CHANNEL4 - bool "TIM2 Channel 4" - default n - ---help--- - Enables channel 4. - -if STM32H7_TIM2_CHANNEL4 - -config STM32H7_TIM2_CH4MODE - int "TIM2 Channel 4 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H7_TIM2_CH4OUT - bool "TIM2 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32H7_TIM2_CHANNEL4 - -endif # STM32H7_PWM_MULTICHAN - -if !STM32H7_PWM_MULTICHAN - -config STM32H7_TIM2_CHANNEL - int "TIM2 PWM Output Channel" - default 1 - range 1 4 - ---help--- - If TIM2 is enabled for PWM usage, you also need specifies the timer output - channel {1,..,4} - -if STM32H7_TIM2_CHANNEL = 1 - -config STM32H7_TIM2_CH1OUT - bool "TIM2 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32H7_TIM2_CHANNEL = 1 - -if STM32H7_TIM2_CHANNEL = 2 - -config STM32H7_TIM2_CH2OUT - bool "TIM2 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32H7_TIM2_CHANNEL = 2 - -if STM32H7_TIM2_CHANNEL = 3 - -config STM32H7_TIM2_CH3OUT - bool "TIM2 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -endif # STM32H7_TIM2_CHANNEL = 3 - -if STM32H7_TIM2_CHANNEL = 4 - -config STM32H7_TIM2_CH4OUT - bool "TIM2 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32H7_TIM2_CHANNEL = 4 - -config STM32H7_TIM2_CHMODE - int "TIM2 Channel Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32H7_PWM_MULTICHAN - -endif # STM32H7_TIM2_PWM - -config STM32H7_TIM3_PWM - bool "TIM3 PWM" - default n - depends on STM32H7_TIM3 - select STM32H7_PWM - ---help--- - Reserve timer 3 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32H7_TIM3 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32H7_TIM3_PWM - -config STM32H7_TIM3_MODE - int "TIM3 Mode" - default 0 - range 0 4 - ---help--- - Specifies the timer mode. - -if STM32H7_PWM_MULTICHAN - -config STM32H7_TIM3_CHANNEL1 - bool "TIM3 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32H7_TIM3_CHANNEL1 - -config STM32H7_TIM3_CH1MODE - int "TIM3 Channel 1 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H7_TIM3_CH1OUT - bool "TIM3 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32H7_TIM3_CHANNEL1 - -config STM32H7_TIM3_CHANNEL2 - bool "TIM3 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32H7_TIM3_CHANNEL2 - -config STM32H7_TIM3_CH2MODE - int "TIM3 Channel 2 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H7_TIM3_CH2OUT - bool "TIM3 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32H7_TIM3_CHANNEL2 - -config STM32H7_TIM3_CHANNEL3 - bool "TIM3 Channel 3" - default n - ---help--- - Enables channel 3. - -if STM32H7_TIM3_CHANNEL3 - -config STM32H7_TIM3_CH3MODE - int "TIM3 Channel 3 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H7_TIM3_CH3OUT - bool "TIM3 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -endif # STM32H7_TIM3_CHANNEL3 - -config STM32H7_TIM3_CHANNEL4 - bool "TIM3 Channel 4" - default n - ---help--- - Enables channel 4. - -if STM32H7_TIM3_CHANNEL4 - -config STM32H7_TIM3_CH4MODE - int "TIM3 Channel 4 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H7_TIM3_CH4OUT - bool "TIM3 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32H7_TIM3_CHANNEL4 - -endif # STM32H7_PWM_MULTICHAN - -if !STM32H7_PWM_MULTICHAN - -config STM32H7_TIM3_CHANNEL - int "TIM3 PWM Output Channel" - default 1 - range 1 4 - ---help--- - If TIM3 is enabled for PWM usage, you also need specifies the timer output - channel {1,..,4} - -if STM32H7_TIM3_CHANNEL = 1 - -config STM32H7_TIM3_CH1OUT - bool "TIM3 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32H7_TIM3_CHANNEL = 1 - -if STM32H7_TIM3_CHANNEL = 2 - -config STM32H7_TIM3_CH2OUT - bool "TIM3 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32H7_TIM3_CHANNEL = 2 - -if STM32H7_TIM3_CHANNEL = 3 - -config STM32H7_TIM3_CH3OUT - bool "TIM3 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -endif # STM32H7_TIM3_CHANNEL = 3 - -if STM32H7_TIM3_CHANNEL = 4 - -config STM32H7_TIM3_CH4OUT - bool "TIM3 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32H7_TIM3_CHANNEL = 4 - -config STM32H7_TIM3_CHMODE - int "TIM3 Channel Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32H7_PWM_MULTICHAN - -endif # STM32H7_TIM3_PWM - -config STM32H7_TIM4_PWM - bool "TIM4 PWM" - default n - depends on STM32H7_TIM4 - select STM32H7_PWM - ---help--- - Reserve timer 4 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32H7_TIM4 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32H7_TIM4_PWM - -config STM32H7_TIM4_MODE - int "TIM4 Mode" - default 0 - range 0 4 - ---help--- - Specifies the timer mode. - -if STM32H7_PWM_MULTICHAN - -config STM32H7_TIM4_CHANNEL1 - bool "TIM4 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32H7_TIM4_CHANNEL1 - -config STM32H7_TIM4_CH1MODE - int "TIM4 Channel 1 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H7_TIM4_CH1OUT - bool "TIM4 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32H7_TIM4_CHANNEL1 - -config STM32H7_TIM4_CHANNEL2 - bool "TIM4 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32H7_TIM4_CHANNEL2 - -config STM32H7_TIM4_CH2MODE - int "TIM4 Channel 2 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H7_TIM4_CH2OUT - bool "TIM4 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32H7_TIM4_CHANNEL2 - -config STM32H7_TIM4_CHANNEL3 - bool "TIM4 Channel 3" - default n - ---help--- - Enables channel 3. - -if STM32H7_TIM4_CHANNEL3 - -config STM32H7_TIM4_CH3MODE - int "TIM4 Channel 3 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H7_TIM4_CH3OUT - bool "TIM4 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -endif # STM32H7_TIM4_CHANNEL3 - -config STM32H7_TIM4_CHANNEL4 - bool "TIM4 Channel 4" - default n - ---help--- - Enables channel 4. - -if STM32H7_TIM4_CHANNEL4 - -config STM32H7_TIM4_CH4MODE - int "TIM4 Channel 4 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H7_TIM4_CH4OUT - bool "TIM4 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32H7_TIM4_CHANNEL4 - -endif # STM32H7_PWM_MULTICHAN - -if !STM32H7_PWM_MULTICHAN - -config STM32H7_TIM4_CHANNEL - int "TIM4 PWM Output Channel" - default 1 - range 1 4 - ---help--- - If TIM4 is enabled for PWM usage, you also need specifies the timer output - channel {1,..,4} - -if STM32H7_TIM4_CHANNEL = 1 - -config STM32H7_TIM4_CH1OUT - bool "TIM4 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32H7_TIM4_CHANNEL = 1 - -if STM32H7_TIM4_CHANNEL = 2 - -config STM32H7_TIM4_CH2OUT - bool "TIM4 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32H7_TIM4_CHANNEL = 2 - -if STM32H7_TIM4_CHANNEL = 3 - -config STM32H7_TIM4_CH3OUT - bool "TIM4 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -endif # STM32H7_TIM4_CHANNEL = 3 - -if STM32H7_TIM4_CHANNEL = 4 - -config STM32H7_TIM4_CH4OUT - bool "TIM4 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32H7_TIM4_CHANNEL = 4 - -config STM32H7_TIM4_CHMODE - int "TIM4 Channel Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32H7_PWM_MULTICHAN - -endif # STM32H7_TIM4_PWM - -config STM32H7_TIM5_PWM - bool "TIM5 PWM" - default n - depends on STM32H7_TIM5 - select STM32H7_PWM - ---help--- - Reserve timer 5 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32H7_TIM5 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32H7_TIM5_PWM - -config STM32H7_TIM5_MODE - int "TIM5 Mode" - default 0 - range 0 4 - ---help--- - Specifies the timer mode. - -if STM32H7_PWM_MULTICHAN - -config STM32H7_TIM5_CHANNEL1 - bool "TIM5 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32H7_TIM5_CHANNEL1 - -config STM32H7_TIM5_CH1MODE - int "TIM5 Channel 1 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H7_TIM5_CH1OUT - bool "TIM5 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32H7_TIM5_CHANNEL1 - -config STM32H7_TIM5_CHANNEL2 - bool "TIM5 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32H7_TIM5_CHANNEL2 - -config STM32H7_TIM5_CH2MODE - int "TIM5 Channel 2 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H7_TIM5_CH2OUT - bool "TIM5 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32H7_TIM5_CHANNEL2 - -config STM32H7_TIM5_CHANNEL3 - bool "TIM5 Channel 3" - default n - ---help--- - Enables channel 3. - -if STM32H7_TIM5_CHANNEL3 - -config STM32H7_TIM5_CH3MODE - int "TIM5 Channel 3 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H7_TIM5_CH3OUT - bool "TIM5 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -endif # STM32H7_TIM5_CHANNEL3 - -config STM32H7_TIM5_CHANNEL4 - bool "TIM5 Channel 4" - default n - ---help--- - Enables channel 4. - -if STM32H7_TIM5_CHANNEL4 - -config STM32H7_TIM5_CH4MODE - int "TIM5 Channel 4 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H7_TIM5_CH4OUT - bool "TIM5 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32H7_TIM5_CHANNEL4 - -endif # STM32H7_PWM_MULTICHAN - -if !STM32H7_PWM_MULTICHAN - -config STM32H7_TIM5_CHANNEL - int "TIM5 PWM Output Channel" - default 1 - range 1 4 - ---help--- - If TIM5 is enabled for PWM usage, you also need specifies the timer output - channel {1,..,4} - -if STM32H7_TIM5_CHANNEL = 1 - -config STM32H7_TIM5_CH1OUT - bool "TIM5 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32H7_TIM5_CHANNEL = 1 - -if STM32H7_TIM5_CHANNEL = 2 - -config STM32H7_TIM5_CH2OUT - bool "TIM5 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32H7_TIM5_CHANNEL = 2 - -if STM32H7_TIM5_CHANNEL = 3 - -config STM32H7_TIM5_CH3OUT - bool "TIM5 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -endif # STM32H7_TIM5_CHANNEL = 3 - -if STM32H7_TIM5_CHANNEL = 4 - -config STM32H7_TIM5_CH4OUT - bool "TIM5 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32H7_TIM5_CHANNEL = 4 - -config STM32H7_TIM5_CHMODE - int "TIM5 Channel Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32H7_PWM_MULTICHAN - -endif # STM32H7_TIM5_PWM - -config STM32H7_TIM8_PWM - bool "TIM8 PWM" - default n - depends on STM32H7_TIM8 - select STM32H7_PWM - ---help--- - Reserve timer 8 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32H7_TIM8 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32H7_TIM8_PWM - -config STM32H7_TIM8_MODE - int "TIM8 Mode" - default 0 - range 0 4 - ---help--- - Specifies the timer mode. - -config STM32H7_TIM8_LOCK - int "TIM8 Lock Level Configuration" - default 0 - range 0 3 - ---help--- - Timer 8 lock level configuration - -config STM32H7_TIM8_DEADTIME - int "TIM8 Initial Dead-time" - default 0 - range 0 255 - ---help--- - Timer 8 initial dead-time - -config STM32H7_TIM8_TDTS - int "TIM8 t_DTS Division" - default 0 - range 0 2 - ---help--- - Timer 8 dead-time and sampling clock (t_DTS) division - -if STM32H7_PWM_MULTICHAN - -config STM32H7_TIM8_CHANNEL1 - bool "TIM8 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32H7_TIM8_CHANNEL1 - -config STM32H7_TIM8_CH1MODE - int "TIM8 Channel 1 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H7_TIM8_CH1OUT - bool "TIM8 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -config STM32H7_TIM8_CH1NOUT - bool "TIM8 Channel 1 Complementary Output" - default n - ---help--- - Enables channel 1 Complementary Output. - -endif # STM32H7_TIM8_CHANNEL1 - -config STM32H7_TIM8_CHANNEL2 - bool "TIM8 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32H7_TIM8_CHANNEL2 - -config STM32H7_TIM8_CH2MODE - int "TIM8 Channel 2 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H7_TIM8_CH2OUT - bool "TIM8 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -config STM32H7_TIM8_CH2NOUT - bool "TIM8 Channel 2 Complementary Output" - default n - ---help--- - Enables channel 2 Complementary Output. - -endif # STM32H7_TIM8_CHANNEL2 - -config STM32H7_TIM8_CHANNEL3 - bool "TIM8 Channel 3" - default n - ---help--- - Enables channel 3. - -if STM32H7_TIM8_CHANNEL3 - -config STM32H7_TIM8_CH3MODE - int "TIM8 Channel 3 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H7_TIM8_CH3OUT - bool "TIM8 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -config STM32H7_TIM8_CH3NOUT - bool "TIM8 Channel 3 Complementary Output" - default n - ---help--- - Enables channel 3 Complementary Output. - -endif # STM32H7_TIM8_CHANNEL3 - -config STM32H7_TIM8_CHANNEL4 - bool "TIM8 Channel 4" - default n - ---help--- - Enables channel 4. - -if STM32H7_TIM8_CHANNEL4 - -config STM32H7_TIM8_CH4MODE - int "TIM8 Channel 4 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H7_TIM8_CH4OUT - bool "TIM8 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32H7_TIM8_CHANNEL4 - -config STM32H7_TIM8_CHANNEL5 - bool "TIM8 Channel 5 (internal)" - default n - ---help--- - Enables channel 5 (not available externally) - -if STM32H7_TIM8_CHANNEL5 - -config STM32H7_TIM8_CH5MODE - int "TIM8 Channel 5 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H7_TIM8_CH5OUT - bool "TIM8 Channel 5 Output" - default n - ---help--- - Enables channel 5 output. - -endif # STM32H7_TIM8_CHANNEL5 - -config STM32H7_TIM8_CHANNEL6 - bool "TIM8 Channel 6 (internal)" - default n - ---help--- - Enables channel 6 (not available externally) - -if STM32H7_TIM8_CHANNEL6 - -config STM32H7_TIM8_CH6MODE - int "TIM8 Channel 6 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H7_TIM8_CH6OUT - bool "TIM8 Channel 6 Output" - default n - ---help--- - Enables channel 6 output. - -endif # STM32H7_TIM8_CHANNEL6 - -endif # STM32H7_PWM_MULTICHAN - -if !STM32H7_PWM_MULTICHAN - -config STM32H7_TIM8_CHANNEL - int "TIM8 PWM Output Channel" - default 1 - range 1 4 - ---help--- - If TIM8 is enabled for PWM usage, you also need specifies the timer output - channel {1,..,4} - -if STM32H7_TIM8_CHANNEL = 1 - -config STM32H7_TIM8_CH1OUT - bool "TIM8 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -config STM32H7_TIM8_CH1NOUT - bool "TIM8 Channel 1 Complementary Output" - default n - ---help--- - Enables channel 1 Complementary Output. - -endif # STM32H7_TIM8_CHANNEL = 1 - -if STM32H7_TIM8_CHANNEL = 2 - -config STM32H7_TIM8_CH2OUT - bool "TIM8 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -config STM32H7_TIM8_CH2NOUT - bool "TIM8 Channel 2 Complementary Output" - default n - ---help--- - Enables channel 2 Complementary Output. - -endif # STM32H7_TIM8_CHANNEL = 2 - -if STM32H7_TIM8_CHANNEL = 3 - -config STM32H7_TIM8_CH3OUT - bool "TIM8 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -config STM32H7_TIM8_CH3NOUT - bool "TIM8 Channel 3 Complementary Output" - default n - ---help--- - Enables channel 3 Complementary Output. - -endif # STM32H7_TIM8_CHANNEL = 3 - -if STM32H7_TIM8_CHANNEL = 4 - -config STM32H7_TIM8_CH4OUT - bool "TIM8 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32H7_TIM8_CHANNEL = 4 - -config STM32H7_TIM8_CHMODE - int "TIM8 Channel Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32H7_PWM_MULTICHAN - -endif # STM32H7_TIM8_PWM - -config STM32H7_TIM12_PWM - bool "TIM12 PWM" - default n - depends on STM32H7_TIM12 - select STM32H7_PWM - ---help--- - Reserve timer 12 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32H7_TIM12 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32H7_TIM12_PWM - -if STM32H7_PWM_MULTICHAN - -config STM32H7_TIM12_CHANNEL1 - bool "TIM12 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32H7_TIM12_CHANNEL1 - -config STM32H7_TIM12_CH1MODE - int "TIM12 Channel 1 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H7_TIM12_CH1OUT - bool "TIM12 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32H7_TIM12_CHANNEL1 - -config STM32H7_TIM12_CHANNEL2 - bool "TIM12 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32H7_TIM12_CHANNEL2 - -config STM32H7_TIM12_CH2MODE - int "TIM12 Channel 2 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H7_TIM12_CH2OUT - bool "TIM12 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32H7_TIM12_CHANNEL2 - -endif # STM32H7_PWM_MULTICHAN - -if !STM32H7_PWM_MULTICHAN - -config STM32H7_TIM12_CHANNEL - int "TIM12 PWM Output Channel" - default 1 - range 1 2 - ---help--- - If TIM12 is enabled for PWM usage, you also need specifies the timer output - channel {1,2} - -if STM32H7_TIM12_CHANNEL = 1 - -config STM32H7_TIM12_CH1OUT - bool "TIM12 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32H7_TIM12_CHANNEL = 1 - -if STM32H7_TIM12_CHANNEL = 2 - -config STM32H7_TIM12_CH2OUT - bool "TIM12 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32H7_TIM12_CHANNEL = 2 - -config STM32H7_TIM12_CHMODE - int "TIM12 Channel Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32H7_PWM_MULTICHAN - -endif # STM32H7_TIM12_PWM - -config STM32H7_TIM13_PWM - bool "TIM13 PWM" - default n - depends on STM32H7_TIM13 - select STM32H7_PWM - ---help--- - Reserve timer 13 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32H7_TIM13 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32H7_TIM13_PWM - -if STM32H7_PWM_MULTICHAN - -config STM32H7_TIM13_CHANNEL1 - bool "TIM13 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32H7_TIM13_CHANNEL1 - -config STM32H7_TIM13_CH1MODE - int "TIM13 Channel 1 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H7_TIM13_CH1OUT - bool "TIM13 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32H7_TIM13_CHANNEL1 - -endif # STM32H7_PWM_MULTICHAN - -if !STM32H7_PWM_MULTICHAN - -config STM32H7_TIM13_CHANNEL - int "TIM13 PWM Output Channel" - default 1 - range 1 1 - ---help--- - If TIM13 is enabled for PWM usage, you also need specifies the timer output - channel {1} - -if STM32H7_TIM13_CHANNEL = 1 - -config STM32H7_TIM13_CH1OUT - bool "TIM13 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32H7_TIM13_CHANNEL = 1 - -config STM32H7_TIM13_CHMODE - int "TIM13 Channel Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32H7_PWM_MULTICHAN - -endif # STM32H7_TIM13_PWM - -config STM32H7_TIM14_PWM - bool "TIM14 PWM" - default n - depends on STM32H7_TIM14 - select STM32H7_PWM - ---help--- - Reserve timer 14 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32H7_TIM14 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32H7_TIM14_PWM - -if STM32H7_PWM_MULTICHAN - -config STM32H7_TIM14_CHANNEL1 - bool "TIM14 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32H7_TIM14_CHANNEL1 - -config STM32H7_TIM14_CH1MODE - int "TIM14 Channel 1 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H7_TIM14_CH1OUT - bool "TIM14 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32H7_TIM14_CHANNEL1 - -endif # STM32H7_PWM_MULTICHAN - -if !STM32H7_PWM_MULTICHAN - -config STM32H7_TIM14_CHANNEL - int "TIM14 PWM Output Channel" - default 1 - range 1 1 - ---help--- - If TIM14 is enabled for PWM usage, you also need specifies the timer output - channel {1} - -if STM32H7_TIM14_CHANNEL = 1 - -config STM32H7_TIM14_CH1OUT - bool "TIM14 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32H7_TIM14_CHANNEL = 1 - -config STM32H7_TIM14_CHMODE - int "TIM14 Channel Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32H7_PWM_MULTICHAN - -endif # STM32H7_TIM14_PWM - -config STM32H7_TIM15_PWM - bool "TIM15 PWM" - default n - depends on STM32H7_TIM15 - select STM32H7_PWM - ---help--- - Reserve timer 15 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32H7_TIM15 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32H7_TIM15_PWM - -config STM32H7_TIM15_LOCK - int "TIM15 Lock Level Configuration" - default 0 - range 0 3 - ---help--- - Timer 15 lock level configuration - -config STM32H7_TIM15_TDTS - int "TIM15 t_DTS Division" - default 0 - range 0 2 - ---help--- - Timer 15 dead-time and sampling clock (t_DTS) division - -config STM32H7_TIM15_DEADTIME - int "TIM15 Initial Dead-time" - default 0 - range 0 255 - ---help--- - Timer 15 initial dead-time - -if STM32H7_PWM_MULTICHAN - -config STM32H7_TIM15_CHANNEL1 - bool "TIM15 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32H7_TIM15_CHANNEL1 - -config STM32H7_TIM15_CH1MODE - int "TIM15 Channel 1 Mode" - default 6 - range 0 9 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H7_TIM15_CH1OUT - bool "TIM15 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -config STM32H7_TIM15_CH1NOUT - bool "TIM15 Channel 1 Complementary Output" - default n - ---help--- - Enables channel 1 Complementary Output. - -endif # STM32H7_TIM15_CHANNEL1 - -config STM32H7_TIM15_CHANNEL2 - bool "TIM15 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32H7_TIM15_CHANNEL2 - -config STM32H7_TIM15_CH2MODE - int "TIM15 Channel 2 Mode" - default 6 - range 0 9 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H7_TIM15_CH2OUT - bool "TIM15 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32H7_TIM15_CHANNEL2 - -endif # STM32H7_PWM_MULTICHAN - -if !STM32H7_PWM_MULTICHAN - -config STM32H7_TIM15_CHANNEL - int "TIM15 PWM Output Channel" - default 1 - range 1 2 - ---help--- - If TIM15 is enabled for PWM usage, you also need specifies the timer output - channel {1,2} - -if STM32H7_TIM15_CHANNEL = 1 - -config STM32H7_TIM15_CH1OUT - bool "TIM15 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -config STM32H7_TIM15_CH1NOUT - bool "TIM15 Channel 1 Complementary Output" - default n - ---help--- - Enables channel 1 Complementary Output. - -endif # STM32H7_TIM15_CHANNEL = 1 - -if STM32H7_TIM15_CHANNEL = 2 - -config STM32H7_TIM15_CH2OUT - bool "TIM15 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -config STM32H7_TIM15_CH2NOUT - bool "TIM15 Channel 2 Complementary Output" - default n - ---help--- - Enables channel 2 Complementary Output. - -endif # STM32H7_TIM15_CHANNEL = 2 - -config STM32H7_TIM15_CHMODE - int "TIM15 Channel Mode" - default 6 - range 0 9 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32H7_PWM_MULTICHAN - -endif # STM32H7_TIM15_PWM - -config STM32H7_TIM16_PWM - bool "TIM16 PWM" - default n - depends on STM32H7_TIM16 - select STM32H7_PWM - ---help--- - Reserve timer 16 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32H7_TIM16 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32H7_TIM16_PWM - -config STM32H7_TIM16_LOCK - int "TIM16 Lock Level Configuration" - default 0 - range 0 3 - ---help--- - Timer 16 lock level configuration - -config STM32H7_TIM16_TDTS - int "TIM16 t_DTS division" - default 0 - range 0 2 - ---help--- - Timer 16 dead-time and sampling clock (t_DTS) division - -config STM32H7_TIM16_DEADTIME - int "TIM16 Initial Dead-time" - default 0 - range 0 255 - ---help--- - Timer 16 initial dead-time - -if STM32H7_PWM_MULTICHAN - -config STM32H7_TIM16_CHANNEL1 - bool "TIM16 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32H7_TIM16_CHANNEL1 - -config STM32H7_TIM16_CH1MODE - int "TIM16 Channel 1 Mode" - default 6 - range 0 7 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H7_TIM16_CH1OUT - bool "TIM16 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32H7_TIM16_CHANNEL1 - -endif # STM32H7_PWM_MULTICHAN - -if !STM32H7_PWM_MULTICHAN - -config STM32H7_TIM16_CHANNEL - int "TIM16 PWM Output Channel" - default 1 - range 1 1 - ---help--- - If TIM16 is enabled for PWM usage, you also need specifies the timer output - channel {1} - -if STM32H7_TIM16_CHANNEL = 1 - -config STM32H7_TIM16_CH1OUT - bool "TIM16 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32H7_TIM16_CHANNEL = 1 - -config STM32H7_TIM16_CHMODE - int "TIM16 Channel Mode" - default 6 - range 0 7 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32H7_PWM_MULTICHAN - -endif # STM32H7_TIM16_PWM - -config STM32H7_TIM17_PWM - bool "TIM17 PWM" - default n - depends on STM32H7_TIM17 - select STM32H7_PWM - ---help--- - Reserve timer 17 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32H7_TIM17 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32H7_TIM17_PWM - -config STM32H7_TIM17_LOCK - int "TIM17 Lock Level Configuration" - default 0 - range 0 3 - ---help--- - Timer 17 lock level configuration - -config STM32H7_TIM17_TDTS - int "TIM17 t_DTS Division" - default 0 - range 0 2 - ---help--- - Timer 17 dead-time and sampling clock (t_DTS) division - -config STM32H7_TIM17_DEADTIME - int "TIM17 Initial Dead-time" - default 0 - range 0 255 - ---help--- - Timer 17 initial dead-time - -if STM32H7_PWM_MULTICHAN - -config STM32H7_TIM17_CHANNEL1 - bool "TIM17 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32H7_TIM17_CHANNEL1 - -config STM32H7_TIM17_CH1MODE - int "TIM17 Channel 1 Mode" - default 6 - range 0 7 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H7_TIM17_CH1OUT - bool "TIM17 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32H7_TIM17_CHANNEL1 - -endif # STM32H7_PWM_MULTICHAN - -if !STM32H7_PWM_MULTICHAN - -config STM32H7_TIM17_CHANNEL - int "TIM17 PWM Output Channel" - default 1 - range 1 1 - ---help--- - If TIM17 is enabled for PWM usage, you also need specifies the timer output - channel {1} - -if STM32H7_TIM17_CHANNEL = 1 - -config STM32H7_TIM17_CH1OUT - bool "TIM17 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32H7_TIM17_CHANNEL = 1 - -config STM32H7_TIM17_CHMODE - int "TIM17 Channel Mode" - default 6 - range 0 7 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32H7_PWM_MULTICHAN - -endif # STM32H7_TIM17_PWM - -config STM32H7_PWM_MULTICHAN - bool "PWM Multiple Output Channels" - default n - depends on STM32H7_PWM - ---help--- - Specifies that the PWM driver supports multiple output - channels per timer. - -config STM32H7_PULSECOUNT - bool - default n - select ARCH_HAVE_PULSECOUNT - select PULSECOUNT - -config STM32H7_TIM1_PULSECOUNT - bool "TIM1 pulse count" - default n - depends on STM32H7_TIM1 - select STM32H7_PULSECOUNT - ---help--- - Reserve timer 1 for pulse count output. - -if STM32H7_TIM1_PULSECOUNT - -config STM32H7_TIM1_PULSECOUNT_TDTS - int "TIM1 pulse count clock division" - default 0 - range 0 2 - -config STM32H7_TIM1_PULSECOUNT_CHANNEL - int "TIM1 pulse count channel" - default 1 - range 1 4 - ---help--- - Specifies the timer channel {1,..,4}. - -config STM32H7_TIM1_PULSECOUNT_POL - int "TIM1 pulse count output polarity" - default 0 - range 0 1 - -config STM32H7_TIM1_PULSECOUNT_IDLE - int "TIM1 pulse count idle state" - default 0 - range 0 1 - -endif # STM32H7_TIM1_PULSECOUNT - -config STM32H7_TIM8_PULSECOUNT - bool "TIM8 pulse count" - default n - depends on STM32H7_TIM8 - select STM32H7_PULSECOUNT - ---help--- - Reserve timer 8 for pulse count output. - -if STM32H7_TIM8_PULSECOUNT - -config STM32H7_TIM8_PULSECOUNT_TDTS - int "TIM8 pulse count clock division" - default 0 - range 0 2 - -config STM32H7_TIM8_PULSECOUNT_CHANNEL - int "TIM8 pulse count channel" - default 1 - range 1 4 - ---help--- - Specifies the timer channel {1,..,4}. - -config STM32H7_TIM8_PULSECOUNT_POL - int "TIM8 pulse count output polarity" - default 0 - range 0 1 - -config STM32H7_TIM8_PULSECOUNT_IDLE - int "TIM8 pulse count idle state" - default 0 - range 0 1 - -endif # STM32H7_TIM8_PULSECOUNT -config STM32H7_TIM1_ADC - bool "TIM1 ADC" - default n - depends on STM32H7_TIM1 && STM32H7_ADC - ---help--- - Reserve timer 1 for use by an ADC - - Timer devices may be used for different purposes. If STM32H7_TIM1 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - -choice - prompt "Select ADC for use with TIM1" - default STM32H7_TIM1_ADC1 - depends on STM32H7_TIM1_ADC - -config STM32H7_TIM1_ADC1 - bool "Use TIM1 for ADC1" - depends on STM32H7_ADC1 - select STM32H7_HAVE_ADC1_TIMER - ---help--- - Reserve TIM1 to trigger ADC1 - -config STM32H7_TIM1_ADC2 - bool "Use TIM1 for ADC2" - depends on STM32H7_ADC2 - select STM32H7_HAVE_ADC2_TIMER - ---help--- - Reserve TIM1 to trigger ADC2 - -config STM32H7_TIM1_ADC3 - bool "Use TIM1 for ADC3" - depends on STM32H7_ADC3 - select STM32H7_HAVE_ADC3_TIMER - ---help--- - Reserve TIM1 to trigger ADC3 - -endchoice # Select ADC for use with TIM1 - -config STM32H7_TIM2_ADC - bool "TIM2 ADC" - default n - depends on STM32H7_TIM2 && STM32H7_ADC - ---help--- - Reserve timer 2 for use by an ADC - - Timer devices may be used for different purposes. If STM32H7_TIM2 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - -choice - prompt "Select ADC for use with TIM2" - default STM32H7_TIM2_ADC1 - depends on STM32H7_TIM2_ADC - -config STM32H7_TIM2_ADC1 - bool "Use TIM2 for ADC1" - depends on STM32H7_ADC1 - select STM32H7_HAVE_ADC1_TIMER - ---help--- - Reserve TIM2 to trigger ADC1 - -config STM32H7_TIM2_ADC2 - bool "Use TIM2 for ADC2" - depends on STM32H7_ADC2 - select STM32H7_HAVE_ADC2_TIMER - ---help--- - Reserve TIM2 to trigger ADC2 - -config STM32H7_TIM2_ADC3 - bool "Use TIM2 for ADC3" - depends on STM32H7_ADC3 - select STM32H7_HAVE_ADC3_TIMER - ---help--- - Reserve TIM2 to trigger ADC3 - -endchoice # Select ADC for use with TIM2 - -config STM32H7_TIM3_ADC - bool "TIM3 ADC" - default n - depends on STM32H7_TIM3 && STM32H7_ADC - ---help--- - Reserve timer 3 for use by an ADC - - Timer devices may be used for different purposes. If STM32H7_TIM3 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - -choice - prompt "Select ADC for use with TIM3" - default STM32H7_TIM3_ADC1 - depends on STM32H7_TIM3_ADC - -config STM32H7_TIM3_ADC1 - bool "Use TIM3 for ADC1" - depends on STM32H7_ADC1 - select STM32H7_HAVE_ADC1_TIMER - ---help--- - Reserve TIM3 to trigger ADC1 - -config STM32H7_TIM3_ADC2 - bool "Use TIM3 for ADC2" - depends on STM32H7_ADC2 - select STM32H7_HAVE_ADC2_TIMER - ---help--- - Reserve TIM3 to trigger ADC2 - -config STM32H7_TIM3_ADC3 - bool "Use TIM3 for ADC3" - depends on STM32H7_ADC3 - select STM32H7_HAVE_ADC3_TIMER - ---help--- - Reserve TIM3 to trigger ADC3 - -endchoice # Select ADC for use with TIM3 - -config STM32H7_TIM4_ADC - bool "TIM4 ADC" - default n - depends on STM32H7_TIM4 && STM32H7_ADC - ---help--- - Reserve timer 4 for use by ADC - - Timer devices may be used for different purposes. If STM32H7_TIM4 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - -choice - prompt "Select ADC for use with TIM4" - default STM32H7_TIM4_ADC1 - depends on STM32H7_TIM4_ADC - -config STM32H7_TIM4_ADC1 - bool "Use TIM4 for ADC1" - depends on STM32H7_ADC1 - select STM32H7_HAVE_ADC1_TIMER - ---help--- - Reserve TIM4 to trigger ADC1 - -config STM32H7_TIM4_ADC2 - bool "Use TIM4 for ADC2" - depends on STM32H7_ADC2 - select STM32H7_HAVE_ADC2_TIMER - ---help--- - Reserve TIM4 to trigger ADC2 - -config STM32H7_TIM4_ADC3 - bool "Use TIM4 for ADC3" - depends on STM32H7_ADC3 - select STM32H7_HAVE_ADC3_TIMER - ---help--- - Reserve TIM4 to trigger ADC3 - -endchoice # Select ADC for use with TIM4 - -config STM32H7_TIM6_ADC - bool "TIM6 ADC" - default n - depends on STM32H7_TIM6 && STM32H7_ADC - ---help--- - Reserve timer 6 for use by ADC - - Timer devices may be used for different purposes. If STM32H7_TIM6 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - -choice - prompt "Select ADC for use with TIM6" - default STM32H7_TIM6_ADC1 - depends on STM32H7_TIM6_ADC - -config STM32H7_TIM6_ADC1 - bool "Use TIM6 for ADC1" - depends on STM32H7_ADC1 - select STM32H7_HAVE_ADC1_TIMER - ---help--- - Reserve TIM6 to trigger ADC1 - -config STM32H7_TIM6_ADC2 - bool "Use TIM6 for ADC2" - depends on STM32H7_ADC2 - select STM32H7_HAVE_ADC2_TIMER - ---help--- - Reserve TIM6 to trigger ADC2 - -config STM32H7_TIM6_ADC3 - bool "Use TIM6 for ADC3" - depends on STM32H7_ADC3 - select STM32H7_HAVE_ADC3_TIMER - ---help--- - Reserve TIM6 to trigger ADC3 - -endchoice # Select ADC for use with TIM6 - -config STM32H7_TIM8_ADC - bool "TIM8 ADC" - default n - depends on STM32H7_TIM8 && STM32H7_ADC - ---help--- - Reserve timer 8 for use by ADC - - Timer devices may be used for different purposes. If STM32H7_TIM8 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - -choice - prompt "Select ADC for use with TIM8" - default STM32H7_TIM8_ADC1 - depends on STM32H7_TIM8_ADC - -config STM32H7_TIM8_ADC1 - bool "Use TIM8 for ADC1" - depends on STM32H7_ADC1 - select STM32H7_HAVE_ADC1_TIMER - ---help--- - Reserve TIM8 to trigger ADC1 - -config STM32H7_TIM8_ADC2 - bool "Use TIM8 for ADC2" - depends on STM32H7_ADC2 - select STM32H7_HAVE_ADC2_TIMER - ---help--- - Reserve TIM8 to trigger ADC2 - -config STM32H7_TIM8_ADC3 - bool "Use TIM8 for ADC3" - depends on STM32H7_ADC3 - select STM32H7_HAVE_ADC3_TIMER - ---help--- - Reserve TIM8 to trigger ADC3 - -endchoice # Select ADC for use with TIM8 - -config STM32H7_TIM15_ADC - bool "TIM15 ADC" - default n - depends on STM32H7_TIM15 && STM32H7_ADC - ---help--- - Reserve timer 15 for use by ADC - - Timer devices may be used for different purposes. If STM32H7_TIM15 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - -choice - prompt "Select ADC for use with TIM15" - default STM32H7_TIM15_ADC1 - depends on STM32H7_TIM15_ADC - -config STM32H7_TIM15_ADC1 - bool "Use TIM15 for ADC1" - depends on STM32H7_ADC1 - select STM32H7_HAVE_ADC1_TIMER - ---help--- - Reserve TIM15 to trigger ADC1 - -config STM32H7_TIM15_ADC2 - bool "Use TIM15 for ADC2" - depends on STM32H7_ADC2 - select STM32H7_HAVE_ADC2_TIMER - ---help--- - Reserve TIM15 to trigger ADC2 - -config STM32H7_TIM15_ADC3 - bool "Use TIM15 for ADC3" - depends on STM32H7_ADC3 - select STM32H7_HAVE_ADC3_TIMER - ---help--- - Reserve TIM15 to trigger ADC3 - -endchoice # Select ADC for use with TIM15 - -config STM32H7_HAVE_ADC1_TIMER - bool - -config STM32H7_HAVE_ADC2_TIMER - bool - -config STM32H7_HAVE_ADC3_TIMER - bool - -config STM32H7_ADC1_SAMPLE_FREQUENCY - int "ADC1 Sampling Frequency" - default 100 - depends on STM32H7_HAVE_ADC1_TIMER - ---help--- - ADC1 sampling frequency. Default: 100Hz - -config STM32H7_ADC1_TIMTRIG - int "ADC1 Timer Trigger" - default 0 - range 0 4 - depends on STM32H7_HAVE_ADC1_TIMER - ---help--- - Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO - -config STM32H7_ADC2_SAMPLE_FREQUENCY - int "ADC2 Sampling Frequency" - default 100 - depends on STM32H7_HAVE_ADC2_TIMER - ---help--- - ADC2 sampling frequency. Default: 100Hz - -config STM32H7_ADC2_TIMTRIG - int "ADC2 Timer Trigger" - default 0 - range 0 4 - depends on STM32H7_HAVE_ADC2_TIMER - ---help--- - Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO - -config STM32H7_ADC3_SAMPLE_FREQUENCY - int "ADC3 Sampling Frequency" - default 100 - depends on STM32H7_HAVE_ADC3_TIMER - ---help--- - ADC3 sampling frequency. Default: 100Hz - -config STM32H7_ADC3_TIMTRIG - int "ADC3 Timer Trigger" - default 0 - range 0 4 - depends on STM32H7_HAVE_ADC3_TIMER - ---help--- - Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO - -config STM32H7_TIMX_CAP - default n - bool "Helpers for Capture Drivers" - -config STM32H7_TIM1_CAP - bool "TIM1 Capture" - default n - select STM32H7_TIMX_CAP - depends on STM32H7_TIM1 - ---help--- - Reserve timer 1 for use by the capture driver. - -if STM32H7_TIM1_CAP - -config STM32H7_TIM1_CHANNEL - int "TIM1 Capture Input Channel" - default 1 - range 1 6 - ---help--- - Specifies the timer input channel {1..6} for TIM1. - -config STM32H7_TIM1_CLOCK - int "TIM1 capture frequency (Hz)" - default 100000 - ---help--- - This clock frequency determines the timer's counting rate. - -endif # STM32H7_TIM1_CAP - -config STM32H7_TIM8_CAP - bool "TIM8 Capture" - default n - select STM32H7_TIMX_CAP - depends on STM32H7_TIM8 - ---help--- - Reserve timer 8 for use by the capture driver. - -if STM32H7_TIM8_CAP - -config STM32H7_TIM8_CHANNEL - int "TIM8 Capture Input Channel" - default 1 - range 1 6 - ---help--- - Specifies the timer input channel {1..6} for TIM8. - -config STM32H7_TIM8_CLOCK - int "TIM8 capture frequency (Hz)" - default 100000 - ---help--- - This clock frequency determines the timer's counting rate. - -endif # STM32H7_TIM8_CAP - -# -# General-Purpose Timers (4 Channels) -# - -config STM32H7_TIM2_CAP - bool "TIM2 Capture" - default n - select STM32H7_TIMX_CAP - depends on STM32H7_TIM2 - ---help--- - Reserve timer 2 for use by the capture driver. - -if STM32H7_TIM2_CAP - -config STM32H7_TIM2_CHANNEL - int "TIM2 Capture Input Channel" - default 1 - range 1 4 - ---help--- - Specifies the timer input channel {1..4} for TIM2. - -config STM32H7_TIM2_CLOCK - int "TIM2 capture frequency (Hz)" - default 100000 - ---help--- - This clock frequency determines the timer's counting rate. - -endif # STM32H7_TIM2_CAP - -config STM32H7_TIM3_CAP - bool "TIM3 Capture" - default n - select STM32H7_TIMX_CAP - depends on STM32H7_TIM3 - ---help--- - Reserve timer 3 for use by the capture driver. - -if STM32H7_TIM3_CAP - -config STM32H7_TIM3_CHANNEL - int "TIM3 Capture Input Channel" - default 1 - range 1 4 - ---help--- - Specifies the timer input channel {1..4} for TIM3. - -config STM32H7_TIM3_CLOCK - int "TIM3 capture frequency (Hz)" - default 100000 - ---help--- - This clock frequency determines the timer's counting rate. - -endif # STM32H7_TIM3_CAP - -config STM32H7_TIM4_CAP - bool "TIM4 Capture" - default n - select STM32H7_TIMX_CAP - depends on STM32H7_TIM4 - ---help--- - Reserve timer 4 for use by the capture driver. - -if STM32H7_TIM4_CAP - -config STM32H7_TIM4_CHANNEL - int "TIM4 Capture Input Channel" - default 1 - range 1 4 - ---help--- - Specifies the timer input channel {1..4} for TIM4. - -config STM32H7_TIM4_CLOCK - int "TIM4 capture frequency (Hz)" - default 100000 - ---help--- - This clock frequency determines the timer's counting rate. - -endif # STM32H7_TIM4_CAP - -config STM32H7_TIM5_CAP - bool "TIM5 Capture" - default n - select STM32H7_TIMX_CAP - depends on STM32H7_TIM5 - ---help--- - Reserve timer 5 for use by the capture driver. - -if STM32H7_TIM5_CAP - -config STM32H7_TIM5_CHANNEL - int "TIM5 Capture Input Channel" - default 1 - range 1 4 - ---help--- - Specifies the timer input channel {1..4} for TIM5. - -config STM32H7_TIM5_CLOCK - int "TIM5 capture frequency (Hz)" - default 100000 - ---help--- - This clock frequency determines the timer's counting rate. - -endif # STM32H7_TIM5_CAP - -# -# General-Purpose Timers (2 Channels) -# - -config STM32H7_TIM12_CAP - bool "TIM12 Capture" - default n - select STM32H7_TIMX_CAP - depends on STM32H7_TIM12 - ---help--- - Reserve timer 12 for use by the capture driver. - -if STM32H7_TIM12_CAP - -config STM32H7_TIM12_CHANNEL - int "TIM12 Capture Input Channel" - default 1 - range 1 2 - ---help--- - Specifies the timer input channel {1..2} for TIM12. - -config STM32H7_TIM12_CLOCK - int "TIM12 capture frequency (Hz)" - default 100000 - ---help--- - This clock frequency determines the timer's counting rate. - -endif # STM32H7_TIM12_CAP - -config STM32H7_TIM15_CAP - bool "TIM15 Capture" - default n - select STM32H7_TIMX_CAP - depends on STM32H7_TIM15 - ---help--- - Reserve timer 15 for use by the capture driver. - -if STM32H7_TIM15_CAP - -config STM32H7_TIM15_CHANNEL - int "TIM15 Capture Input Channel" - default 1 - range 1 2 - ---help--- - Specifies the timer input channel {1..2} for TIM15. - -config STM32H7_TIM15_CLOCK - int "TIM15 capture frequency (Hz)" - default 100000 - ---help--- - This clock frequency determines the timer's counting rate. - -endif # STM32H7_TIM15_CAP - -# -# General-Purpose Timers (1 Channel) -# - -config STM32H7_TIM13_CAP - bool "TIM13 Capture" - default n - select STM32H7_TIMX_CAP - depends on STM32H7_TIM13 - ---help--- - Reserve timer 13 for use by the capture driver. - -if STM32H7_TIM13_CAP - -config STM32H7_TIM13_CHANNEL - int "TIM13 Capture Input Channel" - default 1 - range 1 1 - ---help--- - Specifies the timer input channel {1} for TIM13. - -config STM32H7_TIM13_CLOCK - int "TIM13 capture frequency (Hz)" - default 100000 - ---help--- - This clock frequency determines the timer's counting rate. - -endif # STM32H7_TIM13_CAP - -config STM32H7_TIM14_CAP - bool "TIM14 Capture" - default n - select STM32H7_TIMX_CAP - depends on STM32H7_TIM14 - ---help--- - Reserve timer 14 for use by the capture driver. - -if STM32H7_TIM14_CAP - -config STM32H7_TIM14_CHANNEL - int "TIM14 Capture Input Channel" - default 1 - range 1 1 - ---help--- - Specifies the timer input channel {1} for TIM14. - -config STM32H7_TIM14_CLOCK - int "TIM14 capture frequency (Hz)" - default 100000 - ---help--- - This clock frequency determines the timer's counting rate. - -endif # STM32H7_TIM14_CAP - -config STM32H7_TIM16_CAP - bool "TIM16 Capture" - default n - select STM32H7_TIMX_CAP - depends on STM32H7_TIM16 - ---help--- - Reserve timer 16 for use by the capture driver. - -if STM32H7_TIM16_CAP - -config STM32H7_TIM16_CHANNEL - int "TIM16 Capture Input Channel" - default 1 - range 1 1 - ---help--- - Specifies the timer input channel {1} for TIM16. - -config STM32H7_TIM16_CLOCK - int "TIM16 capture frequency (Hz)" - default 100000 - ---help--- - This clock frequency determines the timer's counting rate. - -endif # STM32H7_TIM16_CAP - -config STM32H7_TIM17_CAP - bool "TIM17 Capture" - default n - select STM32H7_TIMX_CAP - depends on STM32H7_TIM17 - ---help--- - Reserve timer 17 for use by the capture driver. - -if STM32H7_TIM17_CAP - -config STM32H7_TIM17_CHANNEL - int "TIM17 Capture Input Channel" - default 1 - range 1 1 - ---help--- - Specifies the timer input channel {1} for TIM17. - -config STM32H7_TIM17_CLOCK - int "TIM17 capture frequency (Hz)" - default 100000 - ---help--- - This clock frequency determines the timer's counting rate. - -endif # STM32H7_TIM17_CAP - -# -# Low-Power Timers -# - -config STM32H7_LPTIM1_CAP - bool "LPTIM1 Capture" - default n - select STM32H7_TIMX_CAP - depends on STM32H7_LPTIM1 - ---help--- - Reserve low-power timer 1 for use by the capture driver. - -if STM32H7_LPTIM1_CAP - -config STM32H7LPTIM1_CHANNEL - int "LPTIM1 Capture Input Channel" - default 1 - range 1 2 - ---help--- - Specifies the timer input channel {1,2} for LPTIM1. - -config STM32H7LPTIM1_CLOCK - int "LPTIM1 capture frequency (Hz)" - default 100000 - ---help--- - This clock frequency determines the timer's counting rate. - -endif # STM32H7_LPTIM1_CAP - -config STM32H7_LPTIM2_CAP - bool "LPTIM2 Capture" - default n - select STM32H7_TIMX_CAP - depends on STM32H7_LPTIM2 - ---help--- - Reserve low-power timer 2 for use by the capture driver. - -if STM32H7_LPTIM2_CAP - -config STM32H7LPTIM2_CHANNEL - int "LPTIM2 Capture Input Channel" - default 1 - range 1 2 - ---help--- - Specifies the timer input channel {1,2} for LPTIM2. - -config STM32H7LPTIM2_CLOCK - int "LPTIM2 capture frequency (Hz)" - default 100000 - ---help--- - This clock frequency determines the timer's counting rate. - -endif # STM32H7_LPTIM2_CAP - -config STM32H7_LPTIM3_CAP - bool "LPTIM3 Capture" - default n - select STM32H7_TIMX_CAP - depends on STM32H7_LPTIM3 - ---help--- - Reserve low-power timer 3 for use by the capture driver. - -if STM32H7_LPTIM3_CAP - -config STM32H7LPTIM3_CHANNEL - int "LPTIM3 Capture Input Channel" - default 1 - range 1 2 - ---help--- - Specifies the timer input channel {1,2} for LPTIM3. - -config STM32H7LPTIM3_CLOCK - int "LPTIM3 capture frequency (Hz)" - default 100000 - ---help--- - This clock frequency determines the timer's counting rate. - -endif # STM32H7_LPTIM3_CAP - -config STM32H7_LPTIM4_CAP - bool "LPTIM4 Capture" - default n - select STM32H7_TIMX_CAP - depends on STM32H7_LPTIM4 - ---help--- - Reserve low-power timer 4 for use by the capture driver. - -if STM32H7_LPTIM4_CAP - -config STM32H7LPTIM4_CHANNEL - int "LPTIM4 Capture Input Channel" - default 1 - range 1 2 - ---help--- - Specifies the timer input channel {1,2} for LPTIM4. - -config STM32H7LPTIM4_CLOCK - int "LPTIM4 capture frequency (Hz)" - default 100000 - ---help--- - This clock frequency determines the timer's counting rate. - -endif # STM32H7_LPTIM4_CAP - -config STM32H7_LPTIM5_CAP - bool "LPTIM5 Capture" - default n - select STM32H7_TIMX_CAP - depends on STM32H7_LPTIM5 - ---help--- - Reserve low-power timer 5 for use by the capture driver. - -if STM32H7_LPTIM5_CAP - -config STM32H7LPTIM5_CHANNEL - int "LPTIM5 Capture Input Channel" - default 1 - range 1 2 - ---help--- - Specifies the timer input channel {1,2} for LPTIM5. - -config STM32H7LPTIM5_CLOCK - int "LPTIM5 capture frequency (Hz)" - default 100000 - ---help--- - This clock frequency determines the timer's counting rate. - -endif # STM32H7_LPTIM5_CAP - -menu "STM32 TIMx Outputs Configuration" - -config STM32H7_TIM1_CH1POL - int "TIM1 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32H7_TIM1_CH1OUT - ---help--- - TIM1 Channel 1 output polarity - -config STM32H7_TIM1_CH1IDLE - int "TIM1 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32H7_TIM1_CH1OUT - ---help--- - TIM1 Channel 1 output IDLE - -config STM32H7_TIM1_CH1NPOL - int "TIM1 Channel 1 Complementary Output polarity" - default 0 - range 0 1 - depends on STM32H7_TIM1_CH1NOUT - ---help--- - TIM1 Channel 1 Complementary Output polarity - -config STM32H7_TIM1_CH1NIDLE - int "TIM1 Channel 1 Complementary Output IDLE" - default 0 - range 0 1 - depends on STM32H7_TIM1_CH1NOUT - ---help--- - TIM1 Channel 1 Complementary Output IDLE - -config STM32H7_TIM1_CH2POL - int "TIM1 Channel 2 Output polarity" - default 0 - range 0 1 - depends on STM32H7_TIM1_CH2OUT - ---help--- - TIM1 Channel 2 output polarity - -config STM32H7_TIM1_CH2IDLE - int "TIM1 Channel 2 Output IDLE" - default 0 - range 0 1 - depends on STM32H7_TIM1_CH2OUT - ---help--- - TIM1 Channel 2 output IDLE - -config STM32H7_TIM1_CH2NPOL - int "TIM1 Channel 2 Complementary Output polarity" - default 0 - range 0 1 - depends on STM32H7_TIM1_CH2NOUT - ---help--- - TIM1 Channel 2 Complementary Output polarity - -config STM32H7_TIM1_CH2NIDLE - int "TIM1 Channel 2 Complementary Output IDLE" - default 0 - range 0 1 - depends on STM32H7_TIM1_CH2NOUT - ---help--- - TIM1 Channel 2 Complementary Output IDLE - -config STM32H7_TIM1_CH3POL - int "TIM1 Channel 3 Output polarity" - default 0 - range 0 1 - depends on STM32H7_TIM1_CH3OUT - ---help--- - TIM1 Channel 3 output polarity - -config STM32H7_TIM1_CH3IDLE - int "TIM1 Channel 3 Output IDLE" - default 0 - range 0 1 - depends on STM32H7_TIM1_CH3OUT - ---help--- - TIM1 Channel 3 output IDLE - -config STM32H7_TIM1_CH3NPOL - int "TIM1 Channel 3 Complementary Output polarity" - default 0 - range 0 1 - depends on STM32H7_TIM1_CH3NOUT - ---help--- - TIM1 Channel 3 Complementary Output polarity - -config STM32H7_TIM1_CH3NIDLE - int "TIM1 Channel 3 Complementary Output IDLE" - default 0 - range 0 1 - depends on STM32H7_TIM1_CH3NOUT - ---help--- - TIM1 Channel 3 Complementary Output IDLE - -config STM32H7_TIM1_CH4POL - int "TIM1 Channel 4 Output polarity" - default 0 - range 0 1 - depends on STM32H7_TIM1_CH4OUT - ---help--- - TIM1 Channel 4 output polarity - -config STM32H7_TIM1_CH4IDLE - int "TIM1 Channel 4 Output IDLE" - default 0 - range 0 1 - depends on STM32H7_TIM1_CH4OUT - ---help--- - TIM1 Channel 4 output IDLE - -config STM32H7_TIM1_CH5POL - int "TIM1 Channel 5 Output polarity" - default 0 - range 0 1 - depends on STM32H7_TIM1_CH5OUT - ---help--- - TIM1 Channel 5 output polarity - -config STM32H7_TIM1_CH5IDLE - int "TIM1 Channel 5 Output IDLE" - default 0 - range 0 1 - depends on STM32H7_TIM1_CH5OUT - ---help--- - TIM1 Channel 5 output IDLE - -config STM32H7_TIM1_CH6POL - int "TIM1 Channel 6 Output polarity" - default 0 - range 0 1 - depends on STM32H7_TIM1_CH6OUT - ---help--- - TIM1 Channel 6 output polarity - -config STM32H7_TIM1_CH6IDLE - int "TIM1 Channel 6 Output IDLE" - default 0 - range 0 1 - depends on STM32H7_TIM1_CH6OUT - ---help--- - TIM1 Channel 6 output IDLE - -config STM32H7_TIM2_CH1POL - int "TIM2 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32H7_TIM2_CH1OUT - ---help--- - TIM2 Channel 1 output polarity - -config STM32H7_TIM2_CH1IDLE - int "TIM2 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32H7_TIM2_CH1OUT - ---help--- - TIM2 Channel 1 output IDLE - -config STM32H7_TIM2_CH2POL - int "TIM2 Channel 2 Output polarity" - default 0 - range 0 1 - depends on STM32H7_TIM2_CH2OUT - ---help--- - TIM2 Channel 2 output polarity - -config STM32H7_TIM2_CH2IDLE - int "TIM2 Channel 2 Output IDLE" - default 0 - range 0 1 - depends on STM32H7_TIM2_CH2OUT - ---help--- - TIM2 Channel 2 output IDLE - -config STM32H7_TIM2_CH3POL - int "TIM2 Channel 3 Output polarity" - default 0 - range 0 1 - depends on STM32H7_TIM2_CH3OUT - ---help--- - TIM2 Channel 3 output polarity - -config STM32H7_TIM2_CH3IDLE - int "TIM2 Channel 3 Output IDLE" - default 0 - range 0 1 - depends on STM32H7_TIM2_CH3OUT - ---help--- - TIM2 Channel 3 output IDLE - -config STM32H7_TIM2_CH4POL - int "TIM2 Channel 4 Output polarity" - default 0 - range 0 1 - depends on STM32H7_TIM2_CH4OUT - ---help--- - TIM2 Channel 4 output polarity - -config STM32H7_TIM2_CH4IDLE - int "TIM2 Channel 4 Output IDLE" - default 0 - range 0 1 - depends on STM32H7_TIM2_CH4OUT - ---help--- - TIM2 Channel 4 output IDLE - -config STM32H7_TIM3_CH1POL - int "TIM3 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32H7_TIM3_CH1OUT - ---help--- - TIM3 Channel 1 output polarity - -config STM32H7_TIM3_CH1IDLE - int "TIM3 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32H7_TIM3_CH1OUT - ---help--- - TIM3 Channel 1 output IDLE - -config STM32H7_TIM3_CH2POL - int "TIM3 Channel 2 Output polarity" - default 0 - range 0 1 - depends on STM32H7_TIM3_CH2OUT - ---help--- - TIM3 Channel 2 output polarity - -config STM32H7_TIM3_CH2IDLE - int "TIM3 Channel 2 Output IDLE" - default 0 - range 0 1 - depends on STM32H7_TIM3_CH2OUT - ---help--- - TIM3 Channel 2 output IDLE - -config STM32H7_TIM3_CH3POL - int "TIM3 Channel 3 Output polarity" - default 0 - range 0 1 - depends on STM32H7_TIM3_CH3OUT - ---help--- - TIM3 Channel 3 output polarity - -config STM32H7_TIM3_CH3IDLE - int "TIM3 Channel 3 Output IDLE" - default 0 - range 0 1 - depends on STM32H7_TIM3_CH3OUT - ---help--- - TIM3 Channel 3 output IDLE - -config STM32H7_TIM3_CH4POL - int "TIM3 Channel 4 Output polarity" - default 0 - range 0 1 - depends on STM32H7_TIM3_CH4OUT - ---help--- - TIM3 Channel 4 output polarity - -config STM32H7_TIM3_CH4IDLE - int "TIM3 Channel 4 Output IDLE" - default 0 - range 0 1 - depends on STM32H7_TIM3_CH4OUT - ---help--- - TIM3 Channel 4 output IDLE - -config STM32H7_TIM4_CH1POL - int "TIM4 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32H7_TIM4_CH1OUT - ---help--- - TIM4 Channel 1 output polarity - -config STM32H7_TIM4_CH1IDLE - int "TIM4 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32H7_TIM4_CH1OUT - ---help--- - TIM4 Channel 1 output IDLE - -config STM32H7_TIM4_CH2POL - int "TIM4 Channel 2 Output polarity" - default 0 - range 0 1 - depends on STM32H7_TIM4_CH2OUT - ---help--- - TIM4 Channel 2 output polarity - -config STM32H7_TIM4_CH2IDLE - int "TIM4 Channel 2 Output IDLE" - default 0 - range 0 1 - depends on STM32H7_TIM4_CH2OUT - ---help--- - TIM4 Channel 2 output IDLE - -config STM32H7_TIM4_CH3POL - int "TIM4 Channel 3 Output polarity" - default 0 - range 0 1 - depends on STM32H7_TIM4_CH3OUT - ---help--- - TIM4 Channel 3 output polarity - -config STM32H7_TIM4_CH3IDLE - int "TIM4 Channel 3 Output IDLE" - default 0 - range 0 1 - depends on STM32H7_TIM4_CH3OUT - ---help--- - TIM4 Channel 3 output IDLE - -config STM32H7_TIM4_CH4POL - int "TIM4 Channel 4 Output polarity" - default 0 - range 0 1 - depends on STM32H7_TIM4_CH4OUT - ---help--- - TIM4 Channel 4 output polarity - -config STM32H7_TIM4_CH4IDLE - int "TIM4 Channel 4 Output IDLE" - default 0 - range 0 1 - depends on STM32H7_TIM4_CH4OUT - ---help--- - TIM4 Channel 4 output IDLE - -config STM32H7_TIM5_CH1POL - int "TIM5 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32H7_TIM5_CH1OUT - ---help--- - TIM5 Channel 1 output polarity - -config STM32H7_TIM5_CH1IDLE - int "TIM5 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32H7_TIM5_CH1OUT - ---help--- - TIM5 Channel 1 output IDLE - -config STM32H7_TIM5_CH2POL - int "TIM5 Channel 2 Output polarity" - default 0 - range 0 1 - depends on STM32H7_TIM5_CH2OUT - ---help--- - TIM5 Channel 2 output polarity - -config STM32H7_TIM5_CH2IDLE - int "TIM5 Channel 2 Output IDLE" - default 0 - range 0 1 - depends on STM32H7_TIM5_CH2OUT - ---help--- - TIM5 Channel 2 output IDLE - -config STM32H7_TIM5_CH3POL - int "TIM5 Channel 3 Output polarity" - default 0 - range 0 1 - depends on STM32H7_TIM5_CH3OUT - ---help--- - TIM5 Channel 3 output polarity - -config STM32H7_TIM5_CH3IDLE - int "TIM5 Channel 3 Output IDLE" - default 0 - range 0 1 - depends on STM32H7_TIM5_CH3OUT - ---help--- - TIM5 Channel 3 output IDLE - -config STM32H7_TIM5_CH4POL - int "TIM5 Channel 4 Output polarity" - default 0 - range 0 1 - depends on STM32H7_TIM5_CH4OUT - ---help--- - TIM5 Channel 4 output polarity - -config STM32H7_TIM5_CH4IDLE - int "TIM5 Channel 4 Output IDLE" - default 0 - range 0 1 - depends on STM32H7_TIM5_CH4OUT - ---help--- - TIM5 Channel 4 output IDLE - -config STM32H7_TIM8_CH1POL - int "TIM8 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32H7_TIM8_CH1OUT - ---help--- - TIM8 Channel 1 output polarity - -config STM32H7_TIM8_CH1IDLE - int "TIM8 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32H7_TIM8_CH1OUT - ---help--- - TIM8 Channel 1 output IDLE - -config STM32H7_TIM8_CH1NPOL - int "TIM8 Channel 1 Complementary Output polarity" - default 0 - range 0 1 - depends on STM32H7_TIM8_CH1NOUT - ---help--- - TIM8 Channel 1 Complementary Output polarity - -config STM32H7_TIM8_CH1NIDLE - int "TIM8 Channel 1 Complementary Output IDLE" - default 0 - range 0 1 - depends on STM32H7_TIM8_CH1NOUT - ---help--- - TIM8 Channel 1 Complementary Output IDLE - -config STM32H7_TIM8_CH2POL - int "TIM8 Channel 2 Output polarity" - default 0 - range 0 1 - depends on STM32H7_TIM8_CH2OUT - ---help--- - TIM8 Channel 2 output polarity - -config STM32H7_TIM8_CH2IDLE - int "TIM8 Channel 2 Output IDLE" - default 0 - range 0 1 - depends on STM32H7_TIM8_CH2OUT - ---help--- - TIM8 Channel 2 output IDLE - -config STM32H7_TIM8_CH2NPOL - int "TIM8 Channel 2 Complementary Output polarity" - default 0 - range 0 1 - depends on STM32H7_TIM8_CH2NOUT - ---help--- - TIM8 Channel 2 Complementary Output polarity - -config STM32H7_TIM8_CH2NIDLE - int "TIM8 Channel 2 Complementary Output IDLE" - default 0 - range 0 1 - depends on STM32H7_TIM8_CH2NOUT - ---help--- - TIM8 Channel 2 Complementary Output IDLE - -config STM32H7_TIM8_CH3POL - int "TIM8 Channel 3 Output polarity" - default 0 - range 0 1 - depends on STM32H7_TIM8_CH3OUT - ---help--- - TIM8 Channel 3 output polarity - -config STM32H7_TIM8_CH3IDLE - int "TIM8 Channel 3 Output IDLE" - default 0 - range 0 1 - depends on STM32H7_TIM8_CH3OUT - ---help--- - TIM8 Channel 3 output IDLE - -config STM32H7_TIM8_CH3NPOL - int "TIM8 Channel 3 Complementary Output polarity" - default 0 - range 0 1 - depends on STM32H7_TIM8_CH3NOUT - ---help--- - TIM8 Channel 3 Complementary Output polarity - -config STM32H7_TIM8_CH3NIDLE - int "TIM8 Channel 3 Complementary Output IDLE" - default 0 - range 0 1 - depends on STM32H7_TIM8_CH3NOUT - ---help--- - TIM8 Channel 3 Complementary Output IDLE - -config STM32H7_TIM8_CH4POL - int "TIM8 Channel 4 Output polarity" - default 0 - range 0 1 - depends on STM32H7_TIM8_CH4OUT - ---help--- - TIM8 Channel 4 output polarity - -config STM32H7_TIM8_CH4IDLE - int "TIM8 Channel 4 Output IDLE" - default 0 - range 0 1 - depends on STM32H7_TIM8_CH4OUT - ---help--- - TIM8 Channel 4 output IDLE - -config STM32H7_TIM8_CH5POL - int "TIM8 Channel 5 Output polarity" - default 0 - range 0 1 - depends on STM32H7_TIM8_CH5OUT - ---help--- - TIM8 Channel 5 output polarity - -config STM32H7_TIM8_CH5IDLE - int "TIM8 Channel 5 Output IDLE" - default 0 - range 0 1 - depends on STM32H7_TIM8_CH5OUT - ---help--- - TIM8 Channel 5 output IDLE - -config STM32H7_TIM8_CH6POL - int "TIM8 Channel 6 Output polarity" - default 0 - range 0 1 - depends on STM32H7_TIM8_CH6OUT - ---help--- - TIM8 Channel 6 output polarity - -config STM32H7_TIM8_CH6IDLE - int "TIM8 Channel 6 Output IDLE" - default 0 - range 0 1 - depends on STM32H7_TIM8_CH6OUT - ---help--- - TIM8 Channel 6 output IDLE - -config STM32H7_TIM12_CH1POL - int "TIM12 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32H7_TIM12_CH1OUT - ---help--- - TIM12 Channel 1 output polarity - -config STM32H7_TIM12_CH1IDLE - int "TIM12 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32H7_TIM12_CH1OUT - ---help--- - TIM12 Channel 1 output IDLE - -config STM32H7_TIM12_CH2POL - int "TIM12 Channel 2 Output polarity" - default 0 - range 0 1 - depends on STM32H7_TIM12_CH2OUT - ---help--- - TIM12 Channel 2 output polarity - -config STM32H7_TIM12_CH2IDLE - int "TIM12 Channel 2 Output IDLE" - default 0 - range 0 1 - depends on STM32H7_TIM12_CH2OUT - ---help--- - TIM12 Channel 2 output IDLE - -config STM32H7_TIM13_CH1POL - int "TIM13 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32H7_TIM13_CH1OUT - ---help--- - TIM13 Channel 1 output polarity - -config STM32H7_TIM13_CH1IDLE - int "TIM13 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32H7_TIM13_CH1OUT - ---help--- - TIM13 Channel 1 output IDLE - -config STM32H7_TIM14_CH1POL - int "TIM14 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32H7_TIM14_CH1OUT - ---help--- - TIM14 Channel 1 output polarity - -config STM32H7_TIM14_CH1IDLE - int "TIM14 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32H7_TIM14_CH1OUT - ---help--- - TIM14 Channel 1 output IDLE - -config STM32H7_TIM15_CH1POL - int "TIM15 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32H7_TIM15_CH1OUT - ---help--- - TIM15 Channel 1 output polarity - -config STM32H7_TIM15_CH1IDLE - int "TIM15 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32H7_TIM15_CH1OUT - ---help--- - TIM15 Channel 1 output IDLE - -config STM32H7_TIM15_CH1NPOL - int "TIM15 Channel 1 Complementary Output polarity" - default 0 - range 0 1 - depends on STM32H7_TIM15_CH1NOUT - ---help--- - TIM15 Channel 1 Complementary Output polarity - -config STM32H7_TIM15_CH1NIDLE - int "TIM15 Channel 1 Complementary Output IDLE" - default 0 - range 0 1 - depends on STM32H7_TIM15_CH1NOUT - ---help--- - TIM15 Channel 1 Complementary Output IDLE - -config STM32H7_TIM15_CH2POL - int "TIM15 Channel 2 Output polarity" - default 0 - range 0 1 - depends on STM32H7_TIM15_CH2OUT - ---help--- - TIM15 Channel 2 output polarity - -config STM32H7_TIM15_CH2IDLE - int "TIM15 Channel 2 Output IDLE" - default 0 - range 0 1 - depends on STM32H7_TIM15_CH2OUT - ---help--- - TIM15 Channel 2 output IDLE - -config STM32H7_TIM15_CH2NPOL - int "TIM15 Channel 2 Complementary Output polarity" - default 0 - range 0 1 - depends on STM32H7_TIM15_CH2NOUT - ---help--- - TIM15 Channel 2 Complementary Output polarity - -config STM32H7_TIM15_CH2NIDLE - int "TIM15 Channel 2 Complementary Output IDLE" - default 0 - range 0 1 - depends on STM32H7_TIM15_CH2NOUT - ---help--- - TIM15 Channel 2 Complementary Output IDLE - -config STM32H7_TIM16_CH1POL - int "TIM16 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32H7_TIM16_CH1OUT - ---help--- - TIM16 Channel 1 output polarity - -config STM32H7_TIM16_CH1IDLE - int "TIM16 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32H7_TIM16_CH1OUT - ---help--- - TIM16 Channel 1 output IDLE - -config STM32H7_TIM17_CH1POL - int "TIM17 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32H7_TIM17_CH1OUT - ---help--- - TIM17 Channel 1 output polarity - -config STM32H7_TIM17_CH1IDLE - int "TIM17 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32H7_TIM17_CH1OUT - ---help--- - TIM17 Channel 1 output IDLE - -endmenu #STM32 TIMx Outputs Configuration - -endmenu # Timer Configuration - -menu "Ethernet MAC configuration" - depends on STM32H7_ETHMAC - -config STM32H7_PHYADDR - int "PHY address" - default 0 - ---help--- - The 5-bit address of the PHY on the board. Default: 1 - -config STM32H7_PHYINIT - bool "Board-specific PHY Initialization" - default n - ---help--- - Some boards require specialized initialization of the PHY before it can be used. - This may include such things as configuring GPIOs, resetting the PHY, etc. If - STM32H7_PHYINIT is defined in the configuration then the board specific logic must - provide stm32_phyinitialize(); The STM32 Ethernet driver will call this function - one time before it first uses the PHY. - -config STM32H7_PHY_POLLING - bool "Support network monitoring by polling the PHY" - default n - depends on STM32H7_HAVE_PHY_POLLED - select ARCH_PHY_POLLED - ---help--- - Some boards may not have an interrupt connected to the PHY. - This option allows the network monitor to be used by polling the - the PHY for status. - -config STM32H7_MII - bool "Use MII interface" - default n - ---help--- - Support Ethernet MII interface. - -choice - prompt "MII clock configuration" - default STM32H7_MII_EXTCLK - depends on STM32H7_MII - -config STM32H7_MII_MCO1 - bool "Use MC01 as MII clock" - ---help--- - Use MCO1 to clock the MII interface. - -config STM32H7_MII_MCO2 - bool "Use MC02 as MII clock" - ---help--- - Use MCO2 to clock the MII interface. - -config STM32H7_MII_EXTCLK - bool "External MII clock" - ---help--- - Clocking is provided by external logic. - -endchoice # MII clock configuration - -config STM32H7_AUTONEG - bool "Use autonegotiation" - default y - ---help--- - Use PHY autonegotiation to determine speed and mode - -config STM32H7_ETH_NRXDESC - int "Number of RX descriptors" - default 8 - ---help--- - Number of RX DMA descriptors to use. - -config STM32H7_ETH_NTXDESC - int "Number of TX descriptors" - default 4 - ---help--- - Number of TX DMA descriptors to use. - -config STM32H7_ETHFD - bool "Full duplex" - default n - depends on !STM32H7_AUTONEG - ---help--- - If STM32H7_AUTONEG is not defined, then this may be defined to select full duplex - mode. Default: half-duplex - -config STM32H7_ETH100MBPS - bool "100 Mbps" - default n - depends on !STM32H7_AUTONEG - ---help--- - If STM32H7_AUTONEG is not defined, then this may be defined to select 100 MBps - speed. Default: 10 Mbps - -config STM32H7_PHYSR - int "PHY Status Register Address (decimal)" - depends on STM32H7_AUTONEG - ---help--- - This must be provided if STM32H7_AUTONEG is defined. The PHY status register - address may diff from PHY to PHY. This configuration sets the address of - the PHY status register. - -config STM32H7_PHYSR_ALTCONFIG - bool "PHY Status Alternate Bit Layout" - default n - depends on STM32H7_AUTONEG - ---help--- - Different PHYs present speed and mode information in different ways. Some - will present separate information for speed and mode (this is the default). - Those PHYs, for example, may provide a 10/100 Mbps indication and a separate - full/half duplex indication. This options selects an alternative representation - where speed and mode information are combined. This might mean, for example, - separate bits for 10HD, 100HD, 10FD and 100FD. - -config STM32H7_PHYSR_SPEED - hex "PHY Speed Mask" - depends on STM32H7_AUTONEG && !STM32H7_PHYSR_ALTCONFIG - ---help--- - This must be provided if STM32H7_AUTONEG is defined. This provides bit mask - for isolating the 10 or 100MBps speed indication. - -config STM32H7_PHYSR_100MBPS - hex "PHY 100Mbps Speed Value" - depends on STM32H7_AUTONEG && !STM32H7_PHYSR_ALTCONFIG - ---help--- - This must be provided if STM32H7_AUTONEG is defined. This provides the value - of the speed bit(s) indicating 100MBps speed. - -config STM32H7_PHYSR_MODE - hex "PHY Mode Mask" - depends on STM32H7_AUTONEG && !STM32H7_PHYSR_ALTCONFIG - ---help--- - This must be provided if STM32H7_AUTONEG is defined. This provide bit mask - for isolating the full or half duplex mode bits. - -config STM32H7_PHYSR_FULLDUPLEX - hex "PHY Full Duplex Mode Value" - depends on STM32H7_AUTONEG && !STM32H7_PHYSR_ALTCONFIG - ---help--- - This must be provided if STM32H7_AUTONEG is defined. This provides the - value of the mode bits indicating full duplex mode. - -config STM32H7_PHYSR_ALTMODE - hex "PHY Mode Mask" - depends on STM32H7_AUTONEG && STM32H7_PHYSR_ALTCONFIG - ---help--- - This must be provided if STM32H7_AUTONEG is defined. This provide bit mask - for isolating the speed and full/half duplex mode bits. - -config STM32H7_PHYSR_10HD - hex "10MBase-T Half Duplex Value" - depends on STM32H7_AUTONEG && STM32H7_PHYSR_ALTCONFIG - ---help--- - This must be provided if STM32H7_AUTONEG is defined. This is the value - under the bit mask that represents the 10Mbps, half duplex setting. - -config STM32H7_PHYSR_100HD - hex "100Base-T Half Duplex Value" - depends on STM32H7_AUTONEG && STM32H7_PHYSR_ALTCONFIG - ---help--- - This must be provided if STM32H7_AUTONEG is defined. This is the value - under the bit mask that represents the 100Mbps, half duplex setting. - -config STM32H7_PHYSR_10FD - hex "10Base-T Full Duplex Value" - depends on STM32H7_AUTONEG && STM32H7_PHYSR_ALTCONFIG - ---help--- - This must be provided if STM32H7_AUTONEG is defined. This is the value - under the bit mask that represents the 10Mbps, full duplex setting. - -config STM32H7_PHYSR_100FD - hex "100Base-T Full Duplex Value" - depends on STM32H7_AUTONEG && STM32H7_PHYSR_ALTCONFIG - ---help--- - This must be provided if STM32H7_AUTONEG is defined. This is the value - under the bit mask that represents the 100Mbps, full duplex setting. - -config STM32H7_ETH_PTP - bool "Precision Time Protocol (PTP)" - default n - ---help--- - Precision Time Protocol (PTP). Not supported but some hooks are indicated - with this condition. - -config STM32H7_RMII - bool - default !STM32H7_MII - -choice - prompt "RMII clock configuration" - default STM32H7_RMII_EXTCLK - depends on STM32H7_RMII - -config STM32H7_RMII_MCO1 - bool "Use MC01 as RMII clock" - ---help--- - Use MCO1 to clock the RMII interface. - -config STM32H7_RMII_MCO2 - bool "Use MC02 as RMII clock" - ---help--- - Use MCO2 to clock the RMII interface. - -config STM32H7_RMII_EXTCLK - bool "External RMII clock" - ---help--- - Clocking is provided by external logic. - -endchoice # RMII clock configuration - -config STM32H7_ETHMAC_REGDEBUG - bool "Register-Level Debug" - default n - depends on DEBUG_NET_INFO - ---help--- - Enable very low-level register access debug. Depends on - CONFIG_DEBUG_FEATURES. - -config STM32H7_NO_PHY - bool "MAC has no PHY" - default n - -endmenu # Ethernet MAC configuration - -if STM32H7_LTDC - -menu "LTDC Configuration" - -config STM32H7_LTDC_USE_DSI - bool "Use DSI as display connection" - default n - depends on STM32H7_DSIHOST - ---help--- - Select this if your display is connected via DSI. - Deselect option if your display is connected via digital - RGB+HSYNC+VSYNC - -config STM32H7_LTDC_BACKLIGHT - bool "Backlight support" - default y - -config STM32H7_LTDC_DEFBACKLIGHT - hex "Default backlight level" - default 0xf0 - -config STM32H7_LTDC_BACKCOLOR - hex "Background color" - default 0x0 - ---help--- - This is the background color that will be used as the LTDC - background layer color. It is an RGB888 format value, - which gets written unmodified to register LTDC_BCCR. - -config STM32H7_LTDC_DITHER - bool "Dither support" - default n - -config STM32H7_LTDC_DITHER_RED - depends on STM32H7_LTDC_DITHER - int "Dither red width" - range 0 7 - default 2 - ---help--- - This is the dither red width. - -config STM32H7_LTDC_DITHER_GREEN - depends on STM32H7_LTDC_DITHER - int "Dither green width" - range 0 7 - default 2 - ---help--- - This is the dither green width. - -config STM32H7_LTDC_DITHER_BLUE - depends on STM32H7_LTDC_DITHER - int "Dither blue width" - range 0 7 - default 2 - ---help--- - This is the dither blue width. - -config STM32H7_LTDC_FB_BASE - hex "Framebuffer memory start address" - default 0 - ---help--- - If you are using the LTDC, then you must provide the address - of the start of the framebuffer. This address will typically - be in the SRAM or SDRAM memory region of the FMC. - -config STM32H7_LTDC_FB_SIZE - int "Framebuffer memory size (bytes)" - default 0 - ---help--- - Must be the whole size of the active LTDC layer. - -config STM32H7_LTDC_FB_DOUBLE_BUFFER - bool "Enable double buffering" - default n - ---help--- - Enable double buffering to allow updates to the framebuffer while the display is being refreshed. - This configuration requires two framebuffers: one active and one inactive. - When the display refreshes, the active and inactive framebuffers are swapped, - enabling smooth and flicker-free updates. - -config STM32H7_LTDC_L1_CHROMAKEYEN - bool "Enable chromakey support for layer 1" - default y - -config STM32H7_LTDC_L1_CHROMAKEY - hex "Layer L1 initial chroma key" - default 0x00000000 - -config STM32H7_LTDC_L1_COLOR - hex "Layer L1 default color" - default 0x00000000 - -choice - prompt "Layer 1 color format" - default STM32H7_LTDC_L1_RGB565 - -config STM32H7_LTDC_L1_L8 - bool "8 bpp L8 (8-bit CLUT)" - depends on STM32H7_FB_CMAP - -config STM32H7_LTDC_L1_AL44 - bool "8 bpp AL44 (4-bit alpha + 4-bit CLUT)" - depends on STM32H7_FB_CMAP - -config STM32H7_LTDC_L1_AL88 - bool "16 bpp AL88 (8-bit alpha + 8-bit CLUT)" - depends on STM32H7_FB_CMAP - -config STM32H7_LTDC_L1_RGB565 - bool "16 bpp RGB 565" - depends on !STM32H7_FB_CMAP - -config STM32H7_LTDC_L1_ARGB4444 - bool "16 bpp ARGB 4444" - depends on !STM32H7_FB_CMAP - -config STM32H7_LTDC_L1_ARGB1555 - bool "16 bpp ARGB 1555" - depends on !STM32H7_FB_CMAP - -config STM32H7_LTDC_L1_RGB888 - bool "24 bpp RGB 888" - depends on !STM32H7_FB_CMAP - -config STM32H7_LTDC_L1_ARGB8888 - bool "32 bpp ARGB 8888" - depends on !STM32H7_FB_CMAP - -endchoice # Layer 1 color format - -config STM32H7_LTDC_L2 - bool "Enable Layer 2 support" - default y - -if STM32H7_LTDC_L2 - -config STM32H7_LTDC_L2_COLOR - hex "Layer L2 default color" - default 0x00000000 - -config STM32H7_LTDC_L2_CHROMAKEYEN - bool "Enable chromakey support for layer 2" - default y - -config STM32H7_LTDC_L2_CHROMAKEY - hex "Layer L2 initial chroma key" - default 0x00000000 - -choice - prompt "Layer 2 (top layer) color format" - default STM32H7_LTDC_L2_RGB565 - -config STM32H7_LTDC_L2_L8 - depends on STM32H7_LTDC_L1_L8 - bool "8 bpp L8 (8-bit CLUT)" - -config STM32H7_LTDC_L2_AL44 - depends on STM32H7_LTDC_L1_AL44 - bool "8 bpp AL44 (4-bit alpha + 4-bit CLUT)" - -config STM32H7_LTDC_L2_AL88 - depends on STM32H7_LTDC_L1_AL88 - bool "16 bpp AL88 (8-bit alpha + 8-bit CLUT)" - -config STM32H7_LTDC_L2_RGB565 - depends on STM32H7_LTDC_L1_RGB565 - bool "16 bpp RGB 565" - -config STM32H7_LTDC_L2_ARGB4444 - depends on STM32H7_LTDC_L1_ARGB4444 - bool "16 bpp ARGB 4444" - -config STM32H7_LTDC_L2_ARGB1555 - depends on STM32H7_LTDC_L1_ARGB1555 - bool "16 bpp ARGB 1555" - -config STM32H7_LTDC_L2_RGB888 - depends on STM32H7_LTDC_L1_RGB888 - bool "24 bpp RGB 888" - -config STM32H7_LTDC_L2_ARGB8888 - depends on STM32H7_LTDC_L1_ARGB8888 - bool "32 bpp ARGB 8888" - -endchoice # Layer 2 color format - -endif # STM32H7_LTDC_L2 - -config STM32H7_FB_CMAP - bool "Color map support" - default y - select FB_CMAP - ---help--- - EnablingEnablescolor map support is necessary for ltdc L8 format. - -config STM32H7_FB_TRANSPARENCY - bool "Transparency color map support" - default y - depends on STM32H7_FB_CMAP - select FB_TRANSPARENCY - ---help--- - Enables transparency color map support is necessary for ltdc L8 format. - -config STM32H7_LTDC_REGDEBUG - bool "Enable LTDC register value debug messages" - default n - ---help--- - This gives additional messages for LTDC related register values. - Additionally, you have to select "Low-level LCD Debug Features" - to enable the debug messages. - -endmenu # LTDC Configuration - -endif # STM32H7_LTDC - -menu "QEncoder Driver" - depends on SENSORS_QENCODER - depends on STM32H7_TIM1 || STM32H7_TIM2 || STM32H7_TIM3 || STM32H7_TIM4 || STM32H7_TIM5 || STM32H7_TIM8 - -config STM32H7_TIM1_QE - bool "TIM1" - default n - depends on STM32H7_TIM1 - ---help--- - Reserve TIM1 for use by QEncoder. - -if STM32H7_TIM1_QE - -config STM32H7_TIM1_QEPSC - int "TIM1 pulse prescaler" - default 1 - ---help--- - This prescaler divides the number of recorded encoder pulses, - limiting the count rate at the expense of resolution. - -endif # STM32H7_TIM1_QE - -config STM32H7_TIM2_QE - bool "TIM2" - default n - depends on STM32H7_TIM2 - ---help--- - Reserve TIM2 for use by QEncoder. - -if STM32H7_TIM2_QE - -config STM32H7_TIM2_QEPSC - int "TIM2 pulse prescaler" - default 1 - ---help--- - This prescaler divides the number of recorded encoder pulses, - limiting the count rate at the expense of resolution. - -endif # STM32H7_TIM2_QE - -config STM32H7_TIM3_QE - bool "TIM3" - default n - depends on STM32H7_TIM3 - ---help--- - Reserve TIM3 for use by QEncoder. - -if STM32H7_TIM3_QE - -config STM32H7_TIM3_QEPSC - int "TIM3 pulse prescaler" - default 1 - ---help--- - This prescaler divides the number of recorded encoder pulses, - limiting the count rate at the expense of resolution. - -endif # STM32H7_TIM3_QE - -config STM32H7_TIM4_QE - bool "TIM4" - default n - depends on STM32H7_TIM4 - ---help--- - Reserve TIM4 for use by QEncoder. - -if STM32H7_TIM4_QE - -config STM32H7_TIM4_QEPSC - int "TIM4 pulse prescaler" - default 1 - ---help--- - This prescaler divides the number of recorded encoder pulses, - limiting the count rate at the expense of resolution. - -endif # STM32H7_TIM4_QE - -config STM32H7_TIM5_QE - bool "TIM5" - default n - depends on STM32H7_TIM5 - ---help--- - Reserve TIM5 for use by QEncoder. - -if STM32H7_TIM5_QE - -config STM32H7_TIM5_QEPSC - int "TIM5 pulse prescaler" - default 1 - ---help--- - This prescaler divides the number of recorded encoder pulses, - limiting the count rate at the expense of resolution. - -endif # STM32H7_TIM5_QE - -config STM32H7_TIM8_QE - bool "TIM8" - default n - depends on STM32H7_TIM8 - ---help--- - Reserve TIM8 for use by QEncoder. - -if STM32H7_TIM8_QE - -config STM32H7_TIM8_QEPSC - int "TIM8 pulse prescaler" - default 1 - ---help--- - This prescaler divides the number of recorded encoder pulses, - limiting the count rate at the expense of resolution. - -endif # STM32H7_TIM8_QE - -config STM32H7_QENCODER_FILTER - bool "Enable filtering on STM32 QEncoder input" - default y - -choice - depends on STM32H7_QENCODER_FILTER - prompt "Input channel sampling frequency" - default STM32H7_QENCODER_SAMPLE_FDTS_4 - -config STM32H7_QENCODER_SAMPLE_FDTS - bool "fDTS" - -config STM32H7_QENCODER_SAMPLE_CKINT - bool "fCK_INT" - -config STM32H7_QENCODER_SAMPLE_FDTS_2 - bool "fDTS/2" - -config STM32H7_QENCODER_SAMPLE_FDTS_4 - bool "fDTS/4" - -config STM32H7_QENCODER_SAMPLE_FDTS_8 - bool "fDTS/8" - -config STM32H7_QENCODER_SAMPLE_FDTS_16 - bool "fDTS/16" - -config STM32H7_QENCODER_SAMPLE_FDTS_32 - bool "fDTS/32" - -endchoice # Input channel sampling frequency - -choice - depends on STM32H7_QENCODER_FILTER - prompt "Input channel event count" - default STM32H7_QENCODER_SAMPLE_EVENT_6 - -config STM32H7_QENCODER_SAMPLE_EVENT_1 - depends on STM32H7_QENCODER_SAMPLE_FDTS - bool "1" - -config STM32H7_QENCODER_SAMPLE_EVENT_2 - depends on STM32H7_QENCODER_SAMPLE_CKINT - bool "2" - -config STM32H7_QENCODER_SAMPLE_EVENT_4 - depends on STM32H7_QENCODER_SAMPLE_CKINT - bool "4" - -config STM32H7_QENCODER_SAMPLE_EVENT_5 - depends on STM32H7_QENCODER_SAMPLE_FDTS_16 || STM32H7_QENCODER_SAMPLE_FDTS_32 - bool "5" - -config STM32H7_QENCODER_SAMPLE_EVENT_6 - depends on !STM32H7_QENCODER_SAMPLE_FDTS && !STM32H7_QENCODER_SAMPLE_CKINT - bool "6" - -config STM32H7_QENCODER_SAMPLE_EVENT_8 - depends on !STM32H7_QENCODER_SAMPLE_FDTS - bool "8" - -endchoice # Input channel event count - -endmenu # QEncoder Driver - -menu "FDCAN Driver Configuration" - depends on STM32H7_FDCAN1 || STM32H7_FDCAN2 || STM32H7_FDCAN3 - -menu "FDCAN1 Configuration" - depends on STM32H7_FDCAN1 - -config FDCAN1_BITRATE - int "CAN bitrate" - depends on !NET_CAN_CANFD - default 100000 - -config FDCAN1_ARBI_BITRATE - int "CAN FD Arbitration phase bitrate" - depends on NET_CAN_CANFD - default 100000 - -config FDCAN1_DATA_BITRATE - int "CAN FD Data phase bitrate" - depends on NET_CAN_CANFD - default 4000000 - -endmenu # STM32H7_FDCAN1 - -menu "FDCAN2 Configuration" - depends on STM32H7_FDCAN2 - -config FDCAN2_BITRATE - int "CAN bitrate" - depends on !NET_CAN_CANFD - default 100000 - -config FDCAN2_ARBI_BITRATE - int "CAN FD Arbitration phase bitrate" - depends on NET_CAN_CANFD - default 100000 - -config FDCAN2_DATA_BITRATE - int "CAN FD Data phase bitrate" - depends on NET_CAN_CANFD - default 4000000 - -endmenu # STM32H7_FDCAN2 - -menu "FDCAN3 Configuration" - depends on STM32H7_FDCAN3 - -config FDCAN3_BITRATE - int "CAN bitrate" - depends on !NET_CAN_CANFD - default 1000000 - -config FDCAN3_ARBI_BITRATE - int "CAN FD Arbitration phase bitrate" - depends on NET_CAN_CANFD - default 1000000 - -config FDCAN3_DATA_BITRATE - int "CAN FD Data phase bitrate" - depends on NET_CAN_CANFD - default 4000000 - -endmenu # STM32H7_FDCAN3 - -config STM32H7_FDCAN_REGDEBUG - bool "Enable register dump debugging" - depends on DEBUG_NET_INFO - default n - ---help--- - Output detailed register-level CAN device debug information. - Requires also CONFIG_DEBUG_CAN_INFO and CONFIG_DEBUG_NET_INFO. - -config STM32H7_FDCAN_LOOPBACK - bool "Enable FDCAN loopback mode" - default n - ---help--- - Enable the FDCAN local loopback mode for testing purposes. - Requires a further choice of internal or external loopback mode. - - TODO: Enable separately for FDCAN1 and FDCAN2 - -choice - prompt "FDCAN Loopback Mode" - depends on STM32H7_FDCAN_LOOPBACK - default STM32H7_FDCAN_LOOPBACK_INTERNAL - -config STM32H7_FDCAN_LOOPBACK_INTERNAL - bool "Internal loopback mode" - ---help--- - Enable internal loopback mode, where both Tx and Rx are - disconnected from the CAN bus. This can be used for a "Hot Selftest", - meaning the FDCAN can be used without affecting a running CAN bus. - - All transmitted frames are treated as received frames and processed - accordingly. - -config STM32H7_FDCAN_LOOPBACK_EXTERNAL - bool "External loopback mode" - ---help--- - Enable external loopback mode, where the Rx pin is disconnected from - the CAN bus but the Tx pin remains connected. - - All transmitted frames are treated as received frames and processed - accordingly. - -endchoice # FDCAN Loopback Mode - -choice - prompt "FDCAN WorkQueue Selection" - default STM32H7_FDCAN_LPWORK - -config STM32H7_FDCAN_LPWORK - bool "Use LP work queue" - ---help--- - Use the low-priority (LP) work queue for reception and transmission - of new frames and for processing of transmission timeouts. - -config STM32H7_FDCAN_HPWORK - bool "Use HP work queue" - ---help--- - Use the high-priority (HP) work queue for reception and transmission - of new frames and for processing of transmission timeouts. - -endchoice # FDCAN WorkQueue Selection - -endmenu # FDCAN Driver + Exclude SRAM4 from the HEAP in order to use this 64 KB region + for other uses, such as DMA buffers, etc. menu "Progmem MTD configuration" @@ -6665,7 +805,7 @@ config STM32_PROGMEM_OTA_PARTITION select MTD_BYTE_WRITE select MTD_PARTITION select MTD_PROGMEM - select STM32H7_PROGMEM + select STM32_PROGMEM ---help--- Initialize an MTD driver for the Flash, which will add an entry at /dev for application access from userspace. diff --git a/arch/arm/src/stm32h7/Make.defs b/arch/arm/src/stm32h7/Make.defs index 73f9b13979a72..298f6da5b5c62 100644 --- a/arch/arm/src/stm32h7/Make.defs +++ b/arch/arm/src/stm32h7/Make.defs @@ -26,8 +26,9 @@ # Common ARM and Cortex-M7 files include armv7-m/Make.defs +include common/stm32/Make.defs -ifeq ($(CONFIG_STM32H7_PROGMEM),y) +ifeq ($(CONFIG_STM32_PROGMEM),y) CHIP_CSRCS += stm32_flash.c endif @@ -35,7 +36,7 @@ ifeq ($(CONFIG_ARCH_STM32H7_DUALCORE),y) CHIP_CSRCS += stm32_dualcore.c endif -ifeq ($(CONFIG_STM32H7_HSEM),y) +ifeq ($(CONFIG_STM32_HSEM),y) CHIP_CSRCS += stm32_hsem.c endif @@ -47,7 +48,6 @@ endif CHIP_CSRCS += stm32_allocateheap.c stm32_exti_gpio.c stm32_gpio.c stm32_irq.c CHIP_CSRCS += stm32_start.c stm32_rcc.c stm32_lowputc.c stm32_serial.c -CHIP_CSRCS += stm32_uid.c ifeq ($(CONFIG_SCHED_TICKLESS),y) CHIP_CSRCS += stm32_tickless.c @@ -55,7 +55,7 @@ else CHIP_CSRCS += stm32_timerisr.c endif -ifeq ($(CONFIG_STM32H7_ONESHOT),y) +ifeq ($(CONFIG_STM32_ONESHOT),y) CHIP_CSRCS += stm32_oneshot.c stm32_oneshot_lowerhalf.c endif @@ -71,51 +71,51 @@ ifeq ($(CONFIG_ARMV7M_DTCM),y) CHIP_CSRCS += stm32_dtcm.c endif -ifeq ($(CONFIG_STM32H7_ADC),y) +ifeq ($(CONFIG_STM32_ADC),y) CHIP_CSRCS += stm32_adc.c endif -ifeq ($(CONFIG_STM32H7_FDCAN),y) +ifeq ($(CONFIG_STM32_FDCAN),y) CHIP_CSRCS += stm32_fdcan_sock.c endif -ifeq ($(CONFIG_STM32H7_RNG),y) +ifeq ($(CONFIG_STM32_RNG),y) CHIP_CSRCS += stm32_rng.c endif -ifeq ($(CONFIG_STM32H7_BBSRAM),y) +ifeq ($(CONFIG_STM32_BBSRAM),y) CHIP_CSRCS += stm32_bbsram.c endif -ifeq ($(CONFIG_STM32H7_DMA),y) +ifeq ($(CONFIG_STM32_DMA),y) CHIP_CSRCS += stm32_dma.c endif -ifeq ($(CONFIG_STM32H7_FMC),y) +ifeq ($(CONFIG_STM32_FMC),y) CHIP_CSRCS += stm32_fmc.c endif -ifeq ($(filter y,$(CONFIG_STM32H7_IWDG) $(CONFIG_STM32H7_RTC_LSICLOCK)),y) +ifeq ($(filter y,$(CONFIG_STM32_IWDG) $(CONFIG_STM32_RTC_LSICLOCK)),y) CHIP_CSRCS += stm32_lsi.c endif -ifeq ($(CONFIG_STM32H7_RTC_LSECLOCK),y) +ifeq ($(CONFIG_STM32_RTC_LSECLOCK),y) CHIP_CSRCS += stm32_lse.c endif -ifeq ($(CONFIG_STM32H7_I2C),y) +ifeq ($(CONFIG_STM32_I2C),y) CHIP_CSRCS += stm32_i2c.c endif -ifeq ($(CONFIG_STM32H7_PWR),y) +ifeq ($(CONFIG_STM32_PWR),y) CHIP_CSRCS += stm32_pwr.c endif -ifeq ($(CONFIG_STM32H7_QUADSPI),y) +ifeq ($(CONFIG_STM32_QSPI),y) CHIP_CSRCS += stm32_qspi.c endif -ifeq ($(CONFIG_STM32H7_RTC),y) +ifeq ($(CONFIG_STM32_RTC),y) CHIP_CSRCS += stm32_rtc.c ifeq ($(CONFIG_RTC_ALARM),y) CHIP_CSRCS += stm32_exti_alarm.c @@ -128,7 +128,7 @@ CHIP_CSRCS += stm32_rtc_lowerhalf.c endif endif -ifeq ($(CONFIG_STM32H7_SPI),y) +ifeq ($(CONFIG_STM32_SPI),y) CHIP_CSRCS += stm32_spi.c endif @@ -136,7 +136,7 @@ ifeq ($(CONFIG_SPI_SLAVE),y) CHIP_CSRCS += stm32_spi_slave.c endif -ifeq ($(CONFIG_STM32H7_SDMMC),y) +ifeq ($(CONFIG_STM32_SDMMC),y) CHIP_CSRCS += stm32_sdmmc.c endif @@ -144,7 +144,7 @@ ifeq ($(CONFIG_TIMER),y) CHIP_CSRCS += stm32_tim_lowerhalf.c endif -ifeq ($(CONFIG_STM32H7_TIMX_CAP),y) +ifeq ($(CONFIG_STM32_TIMX_CAP),y) CHIP_CSRCS += stm32_capture.c endif @@ -152,7 +152,7 @@ ifeq ($(CONFIG_CAPTURE),y) CHIP_CSRCS += stm32_capture_lowerhalf.c endif -ifeq ($(CONFIG_STM32H7_LTDC),y) +ifeq ($(CONFIG_STM32_LTDC),y) CHIP_CSRCS += stm32_ltdc.c endif @@ -171,23 +171,23 @@ endif endif endif -ifeq ($(CONFIG_STM32H7_TIM),y) +ifeq ($(CONFIG_STM32_TIM),y) CHIP_CSRCS += stm32_tim.c endif -ifeq ($(CONFIG_STM32H7_LPTIM),y) +ifeq ($(CONFIG_STM32_LPTIM),y) CHIP_CSRCS += stm32_lptim.c endif -ifeq ($(CONFIG_STM32H7_PWM),y) +ifeq ($(CONFIG_STM32_PWM),y) CHIP_CSRCS += stm32_pwm.c endif -ifeq ($(CONFIG_STM32H7_PULSECOUNT),y) +ifeq ($(CONFIG_STM32_PULSECOUNT),y) CHIP_CSRCS += stm32_pulsecount.c endif -ifeq ($(CONFIG_STM32H7_ETHMAC),y) +ifeq ($(CONFIG_STM32_ETHMAC),y) CHIP_CSRCS += stm32_ethernet.c endif @@ -206,22 +206,22 @@ CHIP_CSRCS += stm32_pminitialize.c endif endif -ifeq ($(CONFIG_STM32H7_IWDG),y) +ifeq ($(CONFIG_STM32_IWDG),y) CHIP_CSRCS += stm32_iwdg.c endif -ifeq ($(CONFIG_STM32H7_WWDG),y) +ifeq ($(CONFIG_STM32_WWDG),y) CHIP_CSRCS += stm32_wwdg.c endif -#ifeq ($(CONFIG_STM32H7_HASH),y) -#CHIP_CSRCS += stm32_hash.c -#endif - -ifeq ($(CONFIG_STM32H7_CRYP),y) +ifeq ($(CONFIG_STM32_CRYP),y) +ifeq ($(CONFIG_STM32_HAVE_IP_CRYPTO_H7),y) CHIP_CSRCS += stm32_aes.c endif +endif ifeq ($(CONFIG_CRYPTO_CRYPTODEV_HARDWARE),y) +ifeq ($(CONFIG_STM32_HAVE_IP_CRYPTO_H7),y) CHIP_CSRCS += stm32_crypto.c endif +endif diff --git a/arch/arm/src/stm32h7/hardware/stm32_dmamux.h b/arch/arm/src/stm32h7/hardware/stm32_dmamux.h index 74973a4004ac4..5ac1b4a0481f9 100644 --- a/arch/arm/src/stm32h7/hardware/stm32_dmamux.h +++ b/arch/arm/src/stm32h7/hardware/stm32_dmamux.h @@ -203,15 +203,15 @@ /* Import DMAMUX map */ -#if defined(CONFIG_STM32H7_STM32H7X0XX) +#if defined(CONFIG_STM32_STM32H7X0XX) # include "hardware/stm32h7x3xx_dmamux.h" -#elif defined(CONFIG_STM32H7_STM32H7X3XX) +#elif defined(CONFIG_STM32_STM32H7X3XX) # include "hardware/stm32h7x3xx_dmamux.h" -#elif defined(CONFIG_STM32H7_STM32H7B3XX) +#elif defined(CONFIG_STM32_STM32H7B3XX) # include "hardware/stm32h7x3xx_dmamux.h" -#elif defined(CONFIG_STM32H7_STM32H7X5XX) +#elif defined(CONFIG_STM32_STM32H7X5XX) # include "hardware/stm32h7x3xx_dmamux.h" -#elif defined(CONFIG_STM32H7_STM32H7X7XX) +#elif defined(CONFIG_STM32_STM32H7X7XX) # include "hardware/stm32h7x3xx_dmamux.h" #else # error "Unsupported STM32 H7 sub family" diff --git a/arch/arm/src/stm32h7/hardware/stm32_ethernet.h b/arch/arm/src/stm32h7/hardware/stm32_ethernet.h index f22c76cd15616..a65c24307614b 100644 --- a/arch/arm/src/stm32h7/hardware/stm32_ethernet.h +++ b/arch/arm/src/stm32h7/hardware/stm32_ethernet.h @@ -33,11 +33,11 @@ * families */ -#if defined(CONFIG_STM32H7_STM32H7X0XX) || \ - defined(CONFIG_STM32H7_STM32H7X3XX) || \ - defined(CONFIG_STM32H7_STM32H7B3XX) || \ - defined(CONFIG_STM32H7_STM32H7X5XX) || \ - defined(CONFIG_STM32H7_STM32H7X7XX) +#if defined(CONFIG_STM32_STM32H7X0XX) || \ + defined(CONFIG_STM32_STM32H7X3XX) || \ + defined(CONFIG_STM32_STM32H7B3XX) || \ + defined(CONFIG_STM32_STM32H7X5XX) || \ + defined(CONFIG_STM32_STM32H7X7XX) /**************************************************************************** * Pre-processor Definitions @@ -680,5 +680,5 @@ struct eth_desc_s ****************************************************************************/ #endif /* __ASSEMBLY__ */ -#endif /* CONFIG_STM32H7_STM32H7X3XX || CONFIG_STM32H7_STM32H7B3XX */ +#endif /* CONFIG_STM32_STM32H7X3XX || CONFIG_STM32_STM32H7B3XX */ #endif /* __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32_ETHERNET_H */ diff --git a/arch/arm/src/stm32h7/hardware/stm32_exti.h b/arch/arm/src/stm32h7/hardware/stm32_exti.h index e197f4b6c4279..bd5bf31c73e70 100644 --- a/arch/arm/src/stm32h7/hardware/stm32_exti.h +++ b/arch/arm/src/stm32h7/hardware/stm32_exti.h @@ -35,11 +35,11 @@ * families */ -#if defined(CONFIG_STM32H7_STM32H7X0XX) || \ - defined(CONFIG_STM32H7_STM32H7X3XX) || \ - defined(CONFIG_STM32H7_STM32H7B3XX) || \ - defined(CONFIG_STM32H7_STM32H7X5XX) || \ - defined(CONFIG_STM32H7_STM32H7X7XX) +#if defined(CONFIG_STM32_STM32H7X0XX) || \ + defined(CONFIG_STM32_STM32H7X3XX) || \ + defined(CONFIG_STM32_STM32H7B3XX) || \ + defined(CONFIG_STM32_STM32H7X5XX) || \ + defined(CONFIG_STM32_STM32H7X7XX) /**************************************************************************** * Pre-processor Definitions @@ -243,5 +243,5 @@ #define EXTI_EVENT_ETHWKUP 86 /* Ethernet wakeup */ #define EXTI_EVENT_HSECSS 87 /* HSECSS interrupt */ -#endif /* CONFIG_STM32H7_STM32H7X3XX || CONFIG_STM32H7_STM32H7X7XX || CONFIG_STM32H7_STM32H7B3XX */ +#endif /* CONFIG_STM32_STM32H7X3XX || CONFIG_STM32_STM32H7X7XX || CONFIG_STM32_STM32H7B3XX */ #endif /* __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32_EXTI_H */ diff --git a/arch/arm/src/stm32h7/hardware/stm32_flash.h b/arch/arm/src/stm32h7/hardware/stm32_flash.h index 399694f63f7f9..b24ccc58f7034 100644 --- a/arch/arm/src/stm32h7/hardware/stm32_flash.h +++ b/arch/arm/src/stm32h7/hardware/stm32_flash.h @@ -30,15 +30,15 @@ #include #include "chip.h" -#if defined(CONFIG_STM32H7_STM32H7X0XX) +#if defined(CONFIG_STM32_STM32H7X0XX) # include "hardware/stm32h7x3xx_flash.h" -#elif defined(CONFIG_STM32H7_STM32H7X3XX) +#elif defined(CONFIG_STM32_STM32H7X3XX) # include "hardware/stm32h7x3xx_flash.h" -#elif defined(CONFIG_STM32H7_STM32H7B3XX) +#elif defined(CONFIG_STM32_STM32H7B3XX) # include "hardware/stm32h7b3xx_flash.h" -#elif defined(CONFIG_STM32H7_STM32H7X5XX) +#elif defined(CONFIG_STM32_STM32H7X5XX) # include "hardware/stm32h7x3xx_flash.h" -#elif defined(CONFIG_STM32H7_STM32H7X7XX) +#elif defined(CONFIG_STM32_STM32H7X7XX) # include "hardware/stm32h7x3xx_flash.h" #else # error "Unsupported STM32 H7 part" diff --git a/arch/arm/src/stm32h7/hardware/stm32_gpio.h b/arch/arm/src/stm32h7/hardware/stm32_gpio.h index 83c989afaa2d0..68f682e41c96e 100644 --- a/arch/arm/src/stm32h7/hardware/stm32_gpio.h +++ b/arch/arm/src/stm32h7/hardware/stm32_gpio.h @@ -30,15 +30,15 @@ #include #include "chip.h" -#if defined(CONFIG_STM32H7_STM32H7X0XX) +#if defined(CONFIG_STM32_STM32H7X0XX) # include "hardware/stm32h7x3xx_gpio.h" -#elif defined(CONFIG_STM32H7_STM32H7X3XX) +#elif defined(CONFIG_STM32_STM32H7X3XX) # include "hardware/stm32h7x3xx_gpio.h" -#elif defined(CONFIG_STM32H7_STM32H7B3XX) +#elif defined(CONFIG_STM32_STM32H7B3XX) # include "hardware/stm32h7x3xx_gpio.h" -#elif defined(CONFIG_STM32H7_STM32H7X5XX) +#elif defined(CONFIG_STM32_STM32H7X5XX) # include "hardware/stm32h7x3xx_gpio.h" -#elif defined(CONFIG_STM32H7_STM32H7X7XX) +#elif defined(CONFIG_STM32_STM32H7X7XX) # include "hardware/stm32h7x3xx_gpio.h" #else # error "Unsupported STM32 H7 part" diff --git a/arch/arm/src/stm32h7/hardware/stm32_i2c.h b/arch/arm/src/stm32h7/hardware/stm32_i2c.h index 7b7efcd854908..e9b47c456897b 100644 --- a/arch/arm/src/stm32h7/hardware/stm32_i2c.h +++ b/arch/arm/src/stm32h7/hardware/stm32_i2c.h @@ -30,15 +30,15 @@ #include #include "chip.h" -#if defined(CONFIG_STM32H7_STM32H7X0XX) +#if defined(CONFIG_STM32_STM32H7X0XX) # include "hardware/stm32h7x3xx_i2c.h" -#elif defined(CONFIG_STM32H7_STM32H7X3XX) +#elif defined(CONFIG_STM32_STM32H7X3XX) # include "hardware/stm32h7x3xx_i2c.h" -#elif defined(CONFIG_STM32H7_STM32H7B3XX) +#elif defined(CONFIG_STM32_STM32H7B3XX) # include "hardware/stm32h7x3xx_i2c.h" -#elif defined(CONFIG_STM32H7_STM32H7X5XX) +#elif defined(CONFIG_STM32_STM32H7X5XX) # include "hardware/stm32h7x3xx_i2c.h" -#elif defined(CONFIG_STM32H7_STM32H7X7XX) +#elif defined(CONFIG_STM32_STM32H7X7XX) # include "hardware/stm32h7x3xx_i2c.h" #else # error "Unsupported STM32 H7 sub family" diff --git a/arch/arm/src/stm32h7/hardware/stm32_memorymap.h b/arch/arm/src/stm32h7/hardware/stm32_memorymap.h index 18c199495ab38..85b3d880ebd12 100644 --- a/arch/arm/src/stm32h7/hardware/stm32_memorymap.h +++ b/arch/arm/src/stm32h7/hardware/stm32_memorymap.h @@ -30,15 +30,15 @@ #include #include "chip.h" -#if defined(CONFIG_STM32H7_STM32H7X0XX) +#if defined(CONFIG_STM32_STM32H7X0XX) # include "hardware/stm32h7x3xx_memorymap.h" -#elif defined(CONFIG_STM32H7_STM32H7X3XX) +#elif defined(CONFIG_STM32_STM32H7X3XX) # include "hardware/stm32h7x3xx_memorymap.h" -#elif defined(CONFIG_STM32H7_STM32H7B3XX) +#elif defined(CONFIG_STM32_STM32H7B3XX) # include "hardware/stm32h7x3xx_memorymap.h" -#elif defined(CONFIG_STM32H7_STM32H7X5XX) +#elif defined(CONFIG_STM32_STM32H7X5XX) # include "hardware/stm32h7x3xx_memorymap.h" -#elif defined(CONFIG_STM32H7_STM32H7X7XX) +#elif defined(CONFIG_STM32_STM32H7X7XX) # include "hardware/stm32h7x3xx_memorymap.h" #else # error "Unsupported STM32 H7 memory map" diff --git a/arch/arm/src/stm32h7/hardware/stm32_pinmap.h b/arch/arm/src/stm32h7/hardware/stm32_pinmap.h index db27991f33da4..409bca7898397 100644 --- a/arch/arm/src/stm32h7/hardware/stm32_pinmap.h +++ b/arch/arm/src/stm32h7/hardware/stm32_pinmap.h @@ -30,15 +30,15 @@ #include #include "chip.h" -#if defined(CONFIG_STM32H7_STM32H7X0XX) +#if defined(CONFIG_STM32_STM32H7X0XX) # include "hardware/stm32h7x3xx_pinmap.h" -#elif defined(CONFIG_STM32H7_STM32H7X3XX) +#elif defined(CONFIG_STM32_STM32H7X3XX) # include "hardware/stm32h7x3xx_pinmap.h" -#elif defined(CONFIG_STM32H7_STM32H7B3XX) +#elif defined(CONFIG_STM32_STM32H7B3XX) # include "hardware/stm32h7x3xx_pinmap.h" -#elif defined(CONFIG_STM32H7_STM32H7X5XX) +#elif defined(CONFIG_STM32_STM32H7X5XX) # include "hardware/stm32h7x3xx_pinmap.h" -#elif defined(CONFIG_STM32H7_STM32H7X7XX) +#elif defined(CONFIG_STM32_STM32H7X7XX) # include "hardware/stm32h7x3xx_pinmap.h" #else # error "Unsupported STM32 H7 Pin map" diff --git a/arch/arm/src/stm32h7/hardware/stm32_pwr.h b/arch/arm/src/stm32h7/hardware/stm32_pwr.h index 88f257e9a5805..a3fe24507b801 100644 --- a/arch/arm/src/stm32h7/hardware/stm32_pwr.h +++ b/arch/arm/src/stm32h7/hardware/stm32_pwr.h @@ -30,15 +30,15 @@ #include #include "chip.h" -#if defined(CONFIG_STM32H7_STM32H7X0XX) +#if defined(CONFIG_STM32_STM32H7X0XX) # include "hardware/stm32h7x3xx_pwr.h" -#elif defined(CONFIG_STM32H7_STM32H7X3XX) +#elif defined(CONFIG_STM32_STM32H7X3XX) # include "hardware/stm32h7x3xx_pwr.h" -#elif defined(CONFIG_STM32H7_STM32H7B3XX) +#elif defined(CONFIG_STM32_STM32H7B3XX) # include "hardware/stm32h7x3xx_pwr.h" -#elif defined(CONFIG_STM32H7_STM32H7X5XX) +#elif defined(CONFIG_STM32_STM32H7X5XX) # include "hardware/stm32h7x3xx_pwr.h" -#elif defined(CONFIG_STM32H7_STM32H7X7XX) +#elif defined(CONFIG_STM32_STM32H7X7XX) # include "hardware/stm32h7x3xx_pwr.h" #else # error "Unsupported STM32 H7 part" diff --git a/arch/arm/src/stm32h7/hardware/stm32_qspi.h b/arch/arm/src/stm32h7/hardware/stm32_qspi.h index dcc4e882cdf55..a66957eac8941 100644 --- a/arch/arm/src/stm32h7/hardware/stm32_qspi.h +++ b/arch/arm/src/stm32h7/hardware/stm32_qspi.h @@ -38,8 +38,8 @@ /* General Characteristics **************************************************/ -#define STM32H7_QSPI_MINBITS 8 /* Minimum word width */ -#define STM32H7_QSPI_MAXBITS 32 /* Maximum word width */ +#define STM32_QSPI_MINBITS 8 /* Minimum word width */ +#define STM32_QSPI_MAXBITS 32 /* Maximum word width */ /* QSPI register offsets ****************************************************/ diff --git a/arch/arm/src/stm32h7/hardware/stm32_rcc.h b/arch/arm/src/stm32h7/hardware/stm32_rcc.h index 984f782d6129c..67ef3c5d180ed 100644 --- a/arch/arm/src/stm32h7/hardware/stm32_rcc.h +++ b/arch/arm/src/stm32h7/hardware/stm32_rcc.h @@ -30,15 +30,15 @@ #include #include "chip.h" -#if defined(CONFIG_STM32H7_STM32H7X0XX) +#if defined(CONFIG_STM32_STM32H7X0XX) # include "hardware/stm32h7x3xx_rcc.h" -#elif defined(CONFIG_STM32H7_STM32H7X3XX) +#elif defined(CONFIG_STM32_STM32H7X3XX) # include "hardware/stm32h7x3xx_rcc.h" -#elif defined(CONFIG_STM32H7_STM32H7B3XX) +#elif defined(CONFIG_STM32_STM32H7B3XX) # include "hardware/stm32h7x3xx_rcc.h" -#elif defined(CONFIG_STM32H7_STM32H7X5XX) +#elif defined(CONFIG_STM32_STM32H7X5XX) # include "hardware/stm32h7x3xx_rcc.h" -#elif defined(CONFIG_STM32H7_STM32H7X7XX) +#elif defined(CONFIG_STM32_STM32H7X7XX) # include "hardware/stm32h7x3xx_rcc.h" #else # error "Unsupported STM32 H7 part" diff --git a/arch/arm/src/stm32h7/hardware/stm32_sdmmc.h b/arch/arm/src/stm32h7/hardware/stm32_sdmmc.h index 28bcba80b9ae9..b5d9bd019441a 100644 --- a/arch/arm/src/stm32h7/hardware/stm32_sdmmc.h +++ b/arch/arm/src/stm32h7/hardware/stm32_sdmmc.h @@ -30,15 +30,15 @@ #include #include "chip.h" -#if defined(CONFIG_STM32H7_STM32H7X0XX) +#if defined(CONFIG_STM32_STM32H7X0XX) # include "stm32h7x3xx_sdmmc.h" -#elif defined(CONFIG_STM32H7_STM32H7X3XX) +#elif defined(CONFIG_STM32_STM32H7X3XX) # include "stm32h7x3xx_sdmmc.h" -#elif defined(CONFIG_STM32H7_STM32H7B3XX) +#elif defined(CONFIG_STM32_STM32H7B3XX) # include "stm32h7x3xx_sdmmc.h" -#elif defined(CONFIG_STM32H7_STM32H7X5XX) +#elif defined(CONFIG_STM32_STM32H7X5XX) # include "stm32h7x3xx_sdmmc.h" -#elif defined(CONFIG_STM32H7_STM32H7X7XX) +#elif defined(CONFIG_STM32_STM32H7X7XX) # include "stm32h7x3xx_sdmmc.h" #else # error "Unsupported STM32 H7 part" diff --git a/arch/arm/src/stm32h7/hardware/stm32_spi.h b/arch/arm/src/stm32h7/hardware/stm32_spi.h index 44bae2e58fa5e..f342cc3ea35bc 100644 --- a/arch/arm/src/stm32h7/hardware/stm32_spi.h +++ b/arch/arm/src/stm32h7/hardware/stm32_spi.h @@ -30,15 +30,15 @@ #include #include "chip.h" -#if defined(CONFIG_STM32H7_STM32H7X0XX) +#if defined(CONFIG_STM32_STM32H7X0XX) # include "hardware/stm32h7x3xx_spi.h" -#elif defined(CONFIG_STM32H7_STM32H7X3XX) +#elif defined(CONFIG_STM32_STM32H7X3XX) # include "hardware/stm32h7x3xx_spi.h" -#elif defined(CONFIG_STM32H7_STM32H7B3XX) +#elif defined(CONFIG_STM32_STM32H7B3XX) # include "hardware/stm32h7x3xx_spi.h" -#elif defined(CONFIG_STM32H7_STM32H7X5XX) +#elif defined(CONFIG_STM32_STM32H7X5XX) # include "hardware/stm32h7x3xx_spi.h" -#elif defined(CONFIG_STM32H7_STM32H7X7XX) +#elif defined(CONFIG_STM32_STM32H7X7XX) # include "hardware/stm32h7x3xx_spi.h" #else # error "Unsupported STM32 H7 sub family" diff --git a/arch/arm/src/stm32h7/hardware/stm32_syscfg.h b/arch/arm/src/stm32h7/hardware/stm32_syscfg.h index a48b13ff5d240..3403a0f6fd06d 100644 --- a/arch/arm/src/stm32h7/hardware/stm32_syscfg.h +++ b/arch/arm/src/stm32h7/hardware/stm32_syscfg.h @@ -30,15 +30,15 @@ #include #include "chip.h" -#if defined(CONFIG_STM32H7_STM32H7X0XX) +#if defined(CONFIG_STM32_STM32H7X0XX) # include "hardware/stm32h7x3xx_syscfg.h" -#elif defined(CONFIG_STM32H7_STM32H7X3XX) +#elif defined(CONFIG_STM32_STM32H7X3XX) # include "hardware/stm32h7x3xx_syscfg.h" -#elif defined(CONFIG_STM32H7_STM32H7B3XX) +#elif defined(CONFIG_STM32_STM32H7B3XX) # include "hardware/stm32h7x3xx_syscfg.h" -#elif defined(CONFIG_STM32H7_STM32H7X5XX) +#elif defined(CONFIG_STM32_STM32H7X5XX) # include "hardware/stm32h7x3xx_syscfg.h" -#elif defined(CONFIG_STM32H7_STM32H7X7XX) +#elif defined(CONFIG_STM32_STM32H7X7XX) # include "hardware/stm32h7x3xx_syscfg.h" #else # error "Unsupported STM32 H7 part" diff --git a/arch/arm/src/stm32h7/hardware/stm32_uart.h b/arch/arm/src/stm32h7/hardware/stm32_uart.h index 9bc1408a9b43c..0e6820748e30f 100644 --- a/arch/arm/src/stm32h7/hardware/stm32_uart.h +++ b/arch/arm/src/stm32h7/hardware/stm32_uart.h @@ -30,15 +30,15 @@ #include #include "chip.h" -#if defined(CONFIG_STM32H7_STM32H7X0XX) +#if defined(CONFIG_STM32_STM32H7X0XX) # include "hardware/stm32h7x3xx_uart.h" -#elif defined(CONFIG_STM32H7_STM32H7X3XX) +#elif defined(CONFIG_STM32_STM32H7X3XX) # include "hardware/stm32h7x3xx_uart.h" -#elif defined(CONFIG_STM32H7_STM32H7B3XX) +#elif defined(CONFIG_STM32_STM32H7B3XX) # include "hardware/stm32h7x3xx_uart.h" -#elif defined(CONFIG_STM32H7_STM32H7X5XX) +#elif defined(CONFIG_STM32_STM32H7X5XX) # include "hardware/stm32h7x3xx_uart.h" -#elif defined(CONFIG_STM32H7_STM32H7X7XX) +#elif defined(CONFIG_STM32_STM32H7X7XX) # include "hardware/stm32h7x3xx_uart.h" #else # error "Unsupported STM32 H7 memory map" diff --git a/arch/arm/src/stm32h7/hardware/stm32h7x3xx_gpio.h b/arch/arm/src/stm32h7/hardware/stm32h7x3xx_gpio.h index e052e88da4538..310899214c38f 100644 --- a/arch/arm/src/stm32h7/hardware/stm32h7x3xx_gpio.h +++ b/arch/arm/src/stm32h7/hardware/stm32h7x3xx_gpio.h @@ -30,11 +30,11 @@ #include #include -#if defined(CONFIG_STM32H7_STM32H7X0XX) || \ - defined(CONFIG_STM32H7_STM32H7X3XX) || \ - defined(CONFIG_STM32H7_STM32H7B3XX) || \ - defined(CONFIG_STM32H7_STM32H7X5XX) || \ - defined(CONFIG_STM32H7_STM32H7X7XX) +#if defined(CONFIG_STM32_STM32H7X0XX) || \ + defined(CONFIG_STM32_STM32H7X3XX) || \ + defined(CONFIG_STM32_STM32H7B3XX) || \ + defined(CONFIG_STM32_STM32H7X5XX) || \ + defined(CONFIG_STM32_STM32H7X7XX) /**************************************************************************** * Pre-processor Definitions @@ -55,7 +55,7 @@ /* Register Addresses *******************************************************/ -#if STM32H7_NGPIO > 0 +#if STM32_NGPIO > 0 # define STM32_GPIOA_MODER (STM32_GPIOA_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOA_OTYPER (STM32_GPIOA_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOA_OSPEED (STM32_GPIOA_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -68,7 +68,7 @@ # define STM32_GPIOA_AFRH (STM32_GPIOA_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32H7_NGPIO > 1 +#if STM32_NGPIO > 1 # define STM32_GPIOB_MODER (STM32_GPIOB_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOB_OTYPER (STM32_GPIOB_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOB_OSPEED (STM32_GPIOB_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -81,7 +81,7 @@ # define STM32_GPIOB_AFRH (STM32_GPIOB_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32H7_NGPIO > 2 +#if STM32_NGPIO > 2 # define STM32_GPIOC_MODER (STM32_GPIOC_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOC_OTYPER (STM32_GPIOC_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOC_OSPEED (STM32_GPIOC_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -94,7 +94,7 @@ # define STM32_GPIOC_AFRH (STM32_GPIOC_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32H7_NGPIO > 3 +#if STM32_NGPIO > 3 # define STM32_GPIOD_MODER (STM32_GPIOD_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOD_OTYPER (STM32_GPIOD_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOD_OSPEED (STM32_GPIOD_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -107,7 +107,7 @@ # define STM32_GPIOD_AFRH (STM32_GPIOD_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32H7_NGPIO > 4 +#if STM32_NGPIO > 4 # define STM32_GPIOE_MODER (STM32_GPIOE_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOE_OTYPER (STM32_GPIOE_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOE_OSPEED (STM32_GPIOE_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -120,7 +120,7 @@ # define STM32_GPIOE_AFRH (STM32_GPIOE_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if (STM32H7_NGPIO > 5) && (defined(CONFIG_STM32H7_HAVE_GPIOF)) +#if (STM32_NGPIO > 5) && (defined(CONFIG_STM32_HAVE_GPIOF)) # define STM32_GPIOF_MODER (STM32_GPIOF_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOF_OTYPER (STM32_GPIOF_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOF_OSPEED (STM32_GPIOF_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -133,7 +133,7 @@ # define STM32_GPIOF_AFRH (STM32_GPIOF_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if (STM32H7_NGPIO > 6) && (defined(CONFIG_STM32H7_HAVE_GPIOG)) +#if (STM32_NGPIO > 6) && (defined(CONFIG_STM32_HAVE_GPIOG)) # define STM32_GPIOG_MODER (STM32_GPIOG_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOG_OTYPER (STM32_GPIOG_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOG_OSPEED (STM32_GPIOG_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -146,7 +146,7 @@ # define STM32_GPIOG_AFRH (STM32_GPIOG_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32H7_NGPIO > 7 +#if STM32_NGPIO > 7 # define STM32_GPIOH_MODER (STM32_GPIOH_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOH_OTYPER (STM32_GPIOH_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOH_OSPEED (STM32_GPIOH_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -159,7 +159,7 @@ # define STM32_GPIOH_AFRH (STM32_GPIOH_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32H7_NGPIO > 8 +#if STM32_NGPIO > 8 # define STM32_GPIOI_MODER (STM32_GPIOI_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOI_OTYPER (STM32_GPIOI_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOI_OSPEED (STM32_GPIOI_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -172,7 +172,7 @@ # define STM32_GPIOI_AFRH (STM32_GPIOI_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32H7_NGPIO > 9 +#if STM32_NGPIO > 9 # define STM32_GPIOJ_MODER (STM32_GPIOJ_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOJ_OTYPER (STM32_GPIOJ_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOJ_OSPEED (STM32_GPIOJ_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -185,7 +185,7 @@ # define STM32_GPIOJ_AFRH (STM32_GPIOJ_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32H7_NGPIO > 10 +#if STM32_NGPIO > 10 # define STM32_GPIOK_MODER (STM32_GPIOK_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOK_OTYPER (STM32_GPIOK_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOK_OSPEED (STM32_GPIOK_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -390,5 +390,5 @@ #define GPIO_AFRH15_SHIFT (28) #define GPIO_AFRH15_MASK (15 << GPIO_AFRH15_SHIFT) -#endif /* CONFIG_STM32H7_STM32H7X3XX || CONFIG_STM32H7_STM32H7X7XX || CONFIG_STM32H7_STM32H7B3XX */ +#endif /* CONFIG_STM32_STM32H7X3XX || CONFIG_STM32_STM32H7X7XX || CONFIG_STM32_STM32H7B3XX */ #endif /* __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32H7X3XX_GPIO_H */ diff --git a/arch/arm/src/stm32h7/hardware/stm32h7x3xx_i2c.h b/arch/arm/src/stm32h7/hardware/stm32h7x3xx_i2c.h index bd2e35904070d..944b1f0ef2cd2 100644 --- a/arch/arm/src/stm32h7/hardware/stm32h7x3xx_i2c.h +++ b/arch/arm/src/stm32h7/hardware/stm32h7x3xx_i2c.h @@ -43,7 +43,7 @@ /* Register Addresses *******************************************************/ -#if STM32H7_NI2C > 0 +#if STM32_NI2C > 0 # define STM32_I2C1_CR1 (STM32_I2C1_BASE+STM32_I2C_CR1_OFFSET) # define STM32_I2C1_CR2 (STM32_I2C1_BASE+STM32_I2C_CR2_OFFSET) # define STM32_I2C1_OAR1 (STM32_I2C1_BASE+STM32_I2C_OAR1_OFFSET) @@ -57,7 +57,7 @@ # define STM32_I2C1_TXDR (STM32_I2C1_BASE+STM32_I2C_TXDR_OFFSET) #endif -#if STM32H7_NI2C > 1 +#if STM32_NI2C > 1 # define STM32_I2C2_CR1 (STM32_I2C2_BASE+STM32_I2C_CR1_OFFSET) # define STM32_I2C2_CR2 (STM32_I2C2_BASE+STM32_I2C_CR2_OFFSET) # define STM32_I2C2_OAR1 (STM32_I2C2_BASE+STM32_I2C_OAR1_OFFSET) @@ -71,7 +71,7 @@ # define STM32_I2C2_TXDR (STM32_I2C2_BASE+STM32_I2C_TXDR_OFFSET) #endif -#if STM32H7_NI2C > 2 +#if STM32_NI2C > 2 # define STM32_I2C3_CR1 (STM32_I2C3_BASE+STM32_I2C_CR1_OFFSET) # define STM32_I2C3_CR2 (STM32_I2C3_BASE+STM32_I2C_CR2_OFFSET) # define STM32_I2C3_OAR1 (STM32_I2C3_BASE+STM32_I2C_OAR1_OFFSET) @@ -85,7 +85,7 @@ # define STM32_I2C3_TXDR (STM32_I2C3_BASE+STM32_I2C_TXDR_OFFSET) #endif -#if STM32H7_NI2C > 3 +#if STM32_NI2C > 3 # define STM32_I2C4_CR1 (STM32_I2C4_BASE+STM32_I2C_CR1_OFFSET) # define STM32_I2C4_CR2 (STM32_I2C4_BASE+STM32_I2C_CR2_OFFSET) # define STM32_I2C4_OAR1 (STM32_I2C4_BASE+STM32_I2C_OAR1_OFFSET) diff --git a/arch/arm/src/stm32h7/hardware/stm32h7x3xx_memorymap.h b/arch/arm/src/stm32h7/hardware/stm32h7x3xx_memorymap.h index 215c7be0ed876..1e3737d13e3e0 100644 --- a/arch/arm/src/stm32h7/hardware/stm32h7x3xx_memorymap.h +++ b/arch/arm/src/stm32h7/hardware/stm32h7x3xx_memorymap.h @@ -65,7 +65,7 @@ #ifdef CONFIG_ARCH_CHIP_STM32H7_CORTEXM7 # define STM32_SRAM1_BASE 0x30000000 /* 0x30000000-0x30003fff: System SRAM1 */ -# ifdef CONFIG_STM32H7_STM32H72XXX_OR_STM32H73XXX +# ifdef CONFIG_STM32_STM32H72XXX_OR_STM32H73XXX # define STM32_SRAM2_BASE 0x30004000 /* 0x30004000-0x30007fff: System SRAM2 */ # else /* STM32H74XXX or STM32H75XXX with full SRAM configuration */ # define STM32_SRAM2_BASE 0x30020000 /* 0x30020000-0x3003ffff: System SRAM2 */ diff --git a/arch/arm/src/stm32h7/hardware/stm32h7x3xx_pinmap.h b/arch/arm/src/stm32h7/hardware/stm32h7x3xx_pinmap.h index 46b114c3e67d8..3974629f51694 100644 --- a/arch/arm/src/stm32h7/hardware/stm32h7x3xx_pinmap.h +++ b/arch/arm/src/stm32h7/hardware/stm32h7x3xx_pinmap.h @@ -31,11 +31,11 @@ #include "stm32_gpio.h" -#if defined(CONFIG_STM32H7_STM32H7X0XX) || \ - defined(CONFIG_STM32H7_STM32H7X3XX) || \ - defined(CONFIG_STM32H7_STM32H7B3XX) || \ - defined(CONFIG_STM32H7_STM32H7X5XX) || \ - defined(CONFIG_STM32H7_STM32H7X7XX) +#if defined(CONFIG_STM32_STM32H7X0XX) || \ + defined(CONFIG_STM32_STM32H7X3XX) || \ + defined(CONFIG_STM32_STM32H7B3XX) || \ + defined(CONFIG_STM32_STM32H7X5XX) || \ + defined(CONFIG_STM32_STM32H7X7XX) /**************************************************************************** * Pre-processor Definitions @@ -1538,5 +1538,5 @@ #define GPIO_UART8_TX_1 (GPIO_ALT|GPIO_AF8|GPIO_PUSHPULL|GPIO_PULLUP|GPIO_PORTE|GPIO_PIN1) #define GPIO_UART8_TX_2 (GPIO_ALT|GPIO_AF8|GPIO_PUSHPULL|GPIO_PULLUP|GPIO_PORTJ|GPIO_PIN8) -#endif /* CONFIG_STM32H7_STM32H7X0XX CONFIG_STM32H7_STM32H7X3XX || CONFIG_STM32H7_STM32H7X7XX || CONFIG_STM32H7_STM32H7B3XX */ +#endif /* CONFIG_STM32_STM32H7X0XX CONFIG_STM32_STM32H7X3XX || CONFIG_STM32_STM32H7X7XX || CONFIG_STM32_STM32H7B3XX */ #endif /* __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32H7X3XX_PINMAP_H */ diff --git a/arch/arm/src/stm32h7/hardware/stm32h7x3xx_pwr.h b/arch/arm/src/stm32h7/hardware/stm32h7x3xx_pwr.h index 977f1c4135021..6643ce2452f14 100644 --- a/arch/arm/src/stm32h7/hardware/stm32h7x3xx_pwr.h +++ b/arch/arm/src/stm32h7/hardware/stm32h7x3xx_pwr.h @@ -131,10 +131,10 @@ #define STM32_PWR_CR3_BYPASS (1 << 0) /* Bit 0: Power management unit bypass */ #define STM32_PWR_CR3_LDOEN (1 << 1) /* Bit 1: Low drop-out regulator enable */ -#ifndef CONFIG_STM32H7_HAVE_SMPS +#ifndef CONFIG_STM32_HAVE_SMPS # define STM32_PWR_CR3_SCUEN (1 << 2) /* Bit 2: Supply configuration update enable */ #endif -#ifdef CONFIG_STM32H7_HAVE_SMPS +#ifdef CONFIG_STM32_HAVE_SMPS # define STM32_PWR_CR3_SDEN (1 << 2) /* Bit 2: SMPS step-down converter enable */ # define STM32_PWR_CR3_SMPSEXTHP (1 << 3) /* Bit 3: SMPS step-down converter external power delivery selection */ # define STM32_PWR_CR3_SMPSLEVEL_SHIFT (4) /* BitS 4-5: SMPS step-down converter voltage output level selection */ diff --git a/arch/arm/src/stm32h7/hardware/stm32h7x3xx_rcc.h b/arch/arm/src/stm32h7/hardware/stm32h7x3xx_rcc.h index 8124fbd9c7b71..308dc30f621db 100644 --- a/arch/arm/src/stm32h7/hardware/stm32h7x3xx_rcc.h +++ b/arch/arm/src/stm32h7/hardware/stm32h7x3xx_rcc.h @@ -827,10 +827,10 @@ /* RCC Global Control register */ #define RCC_GCR_WW1RSC (1 << 0) /* Bit 0: WWDG1 reset scope control */ -#ifdef CONFIG_STM32H7_HAVE_CM4 +#ifdef CONFIG_STM32_HAVE_CM4 # define RCC_GCR_WW2RSC (1 << 1) /* Bit 1: WWDG2 reset scope control */ #endif -#ifdef CONFIG_STM32H7_HAVE_CM4 +#ifdef CONFIG_STM32_HAVE_CM4 # define RCC_GCR_BOOT_C1 (1 << 2) /* Bit 2: Allows CPU1 to boot */ # define RCC_GCR_BOOT_C2 (1 << 3) /* Bit 3: Allows CPU2 to boot */ #endif diff --git a/arch/arm/src/stm32h7/hardware/stm32h7x3xx_spi.h b/arch/arm/src/stm32h7/hardware/stm32h7x3xx_spi.h index 2e00669d7d456..2cfb71ca647a5 100644 --- a/arch/arm/src/stm32h7/hardware/stm32h7x3xx_spi.h +++ b/arch/arm/src/stm32h7/hardware/stm32h7x3xx_spi.h @@ -29,11 +29,11 @@ #include -#if defined(CONFIG_STM32H7_STM32H7X0XX) || \ - defined(CONFIG_STM32H7_STM32H7X3XX) || \ - defined(CONFIG_STM32H7_STM32H7B3XX) || \ - defined(CONFIG_STM32H7_STM32H7X5XX) || \ - defined(CONFIG_STM32H7_STM32H7X7XX) +#if defined(CONFIG_STM32_STM32H7X0XX) || \ + defined(CONFIG_STM32_STM32H7X3XX) || \ + defined(CONFIG_STM32_STM32H7B3XX) || \ + defined(CONFIG_STM32_STM32H7X5XX) || \ + defined(CONFIG_STM32_STM32H7X7XX) /**************************************************************************** * Pre-processor Definitions @@ -62,7 +62,7 @@ /* Register Addresses *******************************************************/ -#if STM32H7_NSPI > 0 +#if STM32_NSPI > 0 # define STM32_SPI1_CR1 (STM32_SPI1_BASE+STM32_SPI_CR1_OFFSET) # define STM32_SPI1_CR2 (STM32_SPI1_BASE+STM32_SPI_CR2_OFFSET) # define STM32_SPI1_CFG1 (STM32_SPI1_BASE+STM32_SPI_CFG1_OFFSET) @@ -79,7 +79,7 @@ # define STM32_SPI1_I2SCFGR (STM32_SPI1_BASE+STM32_SPI_I2SCFGR_OFFSET) #endif -#if STM32H7_NSPI > 1 +#if STM32_NSPI > 1 # define STM32_SPI2_CR1 (STM32_SPI2_BASE+STM32_SPI_CR1_OFFSET) # define STM32_SPI2_CR2 (STM32_SPI2_BASE+STM32_SPI_CR2_OFFSET) # define STM32_SPI2_CFG1 (STM32_SPI2_BASE+STM32_SPI_CFG1_OFFSET) @@ -96,7 +96,7 @@ # define STM32_SPI2_I2SCFGR (STM32_SPI2_BASE+STM32_SPI_I2SCFGR_OFFSET) #endif -#if STM32H7_NSPI > 2 +#if STM32_NSPI > 2 # define STM32_SPI3_CR1 (STM32_SPI3_BASE+STM32_SPI_CR1_OFFSET) # define STM32_SPI3_CR2 (STM32_SPI3_BASE+STM32_SPI_CR2_OFFSET) # define STM32_SPI3_CFG1 (STM32_SPI3_BASE+STM32_SPI_CFG1_OFFSET) @@ -113,7 +113,7 @@ # define STM32_SPI3_I2SCFGR (STM32_SPI3_BASE+STM32_SPI_I2SCFGR_OFFSET) #endif -#if STM32H7_NSPI > 3 +#if STM32_NSPI > 3 # define STM32_SPI4_CR1 (STM32_SPI4_BASE+STM32_SPI_CR1_OFFSET) # define STM32_SPI4_CR2 (STM32_SPI4_BASE+STM32_SPI_CR2_OFFSET) # define STM32_SPI4_CFG1 (STM32_SPI4_BASE+STM32_SPI_CFG1_OFFSET) @@ -130,7 +130,7 @@ # define STM32_SPI4_I2SCFGR (STM32_SPI4_BASE+STM32_SPI_I2SCFGR_OFFSET) #endif -#if STM32H7_NSPI > 4 +#if STM32_NSPI > 4 # define STM32_SPI5_CR1 (STM32_SPI5_BASE+STM32_SPI_CR1_OFFSET) # define STM32_SPI5_CR2 (STM32_SPI5_BASE+STM32_SPI_CR2_OFFSET) # define STM32_SPI5_CFG1 (STM32_SPI5_BASE+STM32_SPI_CFG1_OFFSET) @@ -147,7 +147,7 @@ # define STM32_SPI5_I2SCFGR (STM32_SPI5_BASE+STM32_SPI_I2SCFGR_OFFSET) #endif -#if STM32H7_NSPI > 5 +#if STM32_NSPI > 5 # define STM32_SPI6_CR1 (STM32_SPI6_BASE+STM32_SPI_CR1_OFFSET) # define STM32_SPI6_CR2 (STM32_SPI6_BASE+STM32_SPI_CR2_OFFSET) # define STM32_SPI6_CFG1 (STM32_SPI6_BASE+STM32_SPI_CFG1_OFFSET) @@ -466,5 +466,5 @@ /* TODO: SPI/I2S configuration register */ -#endif /* CONFIG_STM32H7_STM32H7X3XX || CONFIG_STM32H7_STM32H7B3XX */ +#endif /* CONFIG_STM32_STM32H7X3XX || CONFIG_STM32_STM32H7B3XX */ #endif /* __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32H7X3XX_SPI_H */ diff --git a/arch/arm/src/stm32h7/hardware/stm32h7x3xx_syscfg.h b/arch/arm/src/stm32h7/hardware/stm32h7x3xx_syscfg.h index e259beff596ff..e5c6fe8e3cedf 100644 --- a/arch/arm/src/stm32h7/hardware/stm32h7x3xx_syscfg.h +++ b/arch/arm/src/stm32h7/hardware/stm32h7x3xx_syscfg.h @@ -56,7 +56,7 @@ #define STM32_SYSCFG_UR_OFFSET(n) (0x0300 + ((n) << 2)) #define STM32_SYSCFG_UR0_OFFSET 0x0300 /* User register 0 */ -#ifdef CONFIG_STM32H7_HAVE_CM4 +#ifdef CONFIG_STM32_HAVE_CM4 # define STM32_SYSCFG_UR1_OFFSET 0x0304 /* User register 2 */ #endif #define STM32_SYSCFG_UR2_OFFSET 0x0308 /* User register 2 */ @@ -92,7 +92,7 @@ #define STM32_SYSCFG_PWRCR (STM32_SYSCFG_BASE + STM32_SYSCFG_PWRCR_OFFSET) #define STM32_SYSCFG_UR0 (STM32_SYSCFG_BASE + STM32_SYSCFG_UR0_OFFSET) -#ifdef CONFIG_STM32H7_HAVE_CM4 +#ifdef CONFIG_STM32_HAVE_CM4 # define STM32_SYSCFG_UR1 (STM32_SYSCFG_BASE + STM32_SYSCFG_UR1_OFFSET) #endif #define STM32_SYSCFG_UR2 (STM32_SYSCFG_BASE + STM32_SYSCFG_UR2_OFFSET) @@ -220,7 +220,7 @@ /* User register 1 */ -#ifdef CONFIG_STM32H7_HAVE_CM4 +#ifdef CONFIG_STM32_HAVE_CM4 # define SYSCFG_UR1_BCM4 (1 << 0) /* Bit 0: Boot Cortex-M4 */ # define SYSCFG_UR1_BCM7 (1 << 16) /* Bit 16: Boot Cortex-M7 */ #endif diff --git a/arch/arm/src/stm32h7/hardware/stm32h7x3xx_uart.h b/arch/arm/src/stm32h7/hardware/stm32h7x3xx_uart.h index e5785ef1c16eb..84a46958e43ae 100644 --- a/arch/arm/src/stm32h7/hardware/stm32h7x3xx_uart.h +++ b/arch/arm/src/stm32h7/hardware/stm32h7x3xx_uart.h @@ -31,11 +31,11 @@ #include "chip.h" #include "hardware/stm32_memorymap.h" -#if defined(CONFIG_STM32H7_STM32H7X0XX) || \ - defined(CONFIG_STM32H7_STM32H7X3XX) || \ - defined(CONFIG_STM32H7_STM32H7B3XX) || \ - defined(CONFIG_STM32H7_STM32H7X5XX) || \ - defined(CONFIG_STM32H7_STM32H7X7XX) +#if defined(CONFIG_STM32_STM32H7X0XX) || \ + defined(CONFIG_STM32_STM32H7X3XX) || \ + defined(CONFIG_STM32_STM32H7B3XX) || \ + defined(CONFIG_STM32_STM32H7X5XX) || \ + defined(CONFIG_STM32_STM32H7X7XX) /**************************************************************************** * Pre-processor Definitions @@ -58,7 +58,7 @@ /* Register Addresses *******************************************************/ -#if STM32H7_NUSART > 0 +#if STM32_NUSART > 0 # define STM32_USART1_CR1 (STM32_USART1_BASE + STM32_USART_CR1_OFFSET) # define STM32_USART1_CR2 (STM32_USART1_BASE + STM32_USART_CR2_OFFSET) # define STM32_USART1_CR3 (STM32_USART1_BASE + STM32_USART_CR3_OFFSET) @@ -74,7 +74,7 @@ # define STM32_USART1_PRESC (STM32_USART1_BASE + STM32_USART_PRESC_OFFSET) #endif -#if STM32H7_NUSART > 1 +#if STM32_NUSART > 1 # define STM32_USART2_CR1 (STM32_USART2_BASE + STM32_USART_CR1_OFFSET) # define STM32_USART2_CR2 (STM32_USART2_BASE + STM32_USART_CR2_OFFSET) # define STM32_USART2_CR3 (STM32_USART2_BASE + STM32_USART_CR3_OFFSET) @@ -90,7 +90,7 @@ # define STM32_USART2_PRESC (STM32_USART2_BASE + STM32_USART_PRESC_OFFSET) #endif -#if STM32H7_NUSART > 2 +#if STM32_NUSART > 2 # define STM32_USART3_CR1 (STM32_USART3_BASE + STM32_USART_CR1_OFFSET) # define STM32_USART3_CR2 (STM32_USART3_BASE + STM32_USART_CR2_OFFSET) # define STM32_USART3_CR3 (STM32_USART3_BASE + STM32_USART_CR3_OFFSET) @@ -106,7 +106,7 @@ # define STM32_USART3_PRESC (STM32_USART3_BASE + STM32_USART_PRESC_OFFSET) #endif -#if STM32H7_NUSART > 3 +#if STM32_NUSART > 3 # define STM32_USART6_CR1 (STM32_USART6_BASE + STM32_USART_CR1_OFFSET) # define STM32_USART6_CR2 (STM32_USART6_BASE + STM32_USART_CR2_OFFSET) # define STM32_USART6_CR3 (STM32_USART6_BASE + STM32_USART_CR3_OFFSET) @@ -122,7 +122,7 @@ # define STM32_USART6_PRESC (STM32_USART6_BASE + STM32_USART_PRESC_OFFSET) #endif -#if STM32H7_NUART > 0 +#if STM32_NUART > 0 # define STM32_UART4_CR1 (STM32_UART4_BASE + STM32_USART_CR1_OFFSET) # define STM32_UART4_CR2 (STM32_UART4_BASE + STM32_USART_CR2_OFFSET) # define STM32_UART4_CR3 (STM32_UART4_BASE + STM32_USART_CR3_OFFSET) @@ -137,7 +137,7 @@ # define STM32_UART4_TDR (STM32_UART4_BASE + STM32_USART_TDR_OFFSET) #endif -#if STM32H7_NUART > 1 +#if STM32_NUART > 1 # define STM32_UART5_CR1 (STM32_UART5_BASE + STM32_USART_CR1_OFFSET) # define STM32_UART5_CR2 (STM32_UART5_BASE + STM32_USART_CR2_OFFSET) # define STM32_UART5_CR3 (STM32_UART5_BASE + STM32_USART_CR3_OFFSET) @@ -152,7 +152,7 @@ # define STM32_UART5_TDR (STM32_UART5_BASE + STM32_USART_TDR_OFFSET) #endif -#if STM32H7_NUART > 2 +#if STM32_NUART > 2 # define STM32_UART7_CR1 (STM32_UART7_BASE + STM32_USART_CR1_OFFSET) # define STM32_UART7_CR2 (STM32_UART7_BASE + STM32_USART_CR2_OFFSET) # define STM32_UART7_CR3 (STM32_UART7_BASE + STM32_USART_CR3_OFFSET) @@ -167,7 +167,7 @@ # define STM32_UART7_TDR (STM32_UART7_BASE + STM32_USART_TDR_OFFSET) #endif -#if STM32H7_NUART > 3 +#if STM32_NUART > 3 # define STM32_UART8_CR1 (STM32_UART8_BASE + STM32_USART_CR1_OFFSET) # define STM32_UART8_CR2 (STM32_UART8_BASE + STM32_USART_CR2_OFFSET) # define STM32_UART8_CR3 (STM32_UART8_BASE + STM32_USART_CR3_OFFSET) @@ -415,5 +415,5 @@ # define USART_PRESC_DIV64 (9 << USART_PRESC_SHIFT) /* Input clock divided by 64 */ # define USART_PRESC_DIV128 (10 << USART_PRESC_SHIFT) /* Input clock divided by 128 */ # define USART_PRESC_DIV256 (11 << USART_PRESC_SHIFT) /* Input clock divided by 256 */ -#endif /* CONFIG_STM32H7_STM32H7X3XX || CONFIG_STM32H7_STM32H7X7XX || CONFIG_STM32H7_STM32H7B3XX */ +#endif /* CONFIG_STM32_STM32H7X3XX || CONFIG_STM32_STM32H7X7XX || CONFIG_STM32_STM32H7B3XX */ #endif /* __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32H7X3XX_UART_H */ diff --git a/arch/arm/src/stm32h7/stm32_adc.c b/arch/arm/src/stm32h7/stm32_adc.c index 720bfdeae3d24..529ba50aece58 100644 --- a/arch/arm/src/stm32h7/stm32_adc.c +++ b/arch/arm/src/stm32h7/stm32_adc.c @@ -77,8 +77,8 @@ /* Some ADC peripheral must be enabled */ -#if defined(CONFIG_STM32H7_ADC1) || defined(CONFIG_STM32H7_ADC2) || \ - defined(CONFIG_STM32H7_ADC3) +#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) || \ + defined(CONFIG_STM32_ADC3) /**************************************************************************** * Pre-processor Definitions @@ -92,9 +92,9 @@ /* ADC Channels/DMA *********************************************************/ #ifdef ADC_HAVE_DMA -# if !defined(CONFIG_STM32H7_DMA1) && !defined(CONFIG_STM32H7_DMA2) +# if !defined(CONFIG_STM32_DMA1) && !defined(CONFIG_STM32_DMA2) # /* REVISIT: check accordingly to which one is configured in board.h */ -# error "STM32H7 ADC DMA support requires CONFIG_STM32H7_DMA1 or CONFIG_STM32H7_DMA2" +# error "STM32H7 ADC DMA support requires CONFIG_STM32_DMA1 or CONFIG_STM32_DMA2" # endif #endif @@ -191,7 +191,7 @@ struct stm32_dev_s /* List of selected ADC channels to sample */ - uint8_t chanlist[CONFIG_STM32H7_ADC_MAX_SAMPLES]; + uint8_t chanlist[CONFIG_STM32_ADC_MAX_SAMPLES]; }; /**************************************************************************** @@ -254,10 +254,10 @@ static int adc_pm_prepare(struct pm_callback_s *cb, int domain, /* ADC Interrupt Handler */ static int adc_interrupt(struct adc_dev_s *dev, uint32_t regval); -#if defined(CONFIG_STM32H7_ADC1) || defined(CONFIG_STM32H7_ADC2) +#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) static int adc12_interrupt(int irq, void *context, void *arg); #endif -#if defined(CONFIG_STM32H7_ADC3) +#if defined(CONFIG_STM32_ADC3) static int adc3_interrupt(int irq, void *context, void *arg); #endif @@ -289,11 +289,11 @@ static const struct adc_ops_s g_adcops = /* ADC1 state */ -#ifdef CONFIG_STM32H7_ADC1 +#ifdef CONFIG_STM32_ADC1 #ifdef ADC1_HAVE_DMA -static uint16_t g_adc1_dmabuffer[CONFIG_STM32H7_ADC_MAX_SAMPLES * - CONFIG_STM32H7_ADC1_DMA_BATCH]; +static uint16_t g_adc1_dmabuffer[CONFIG_STM32_ADC_MAX_SAMPLES * + CONFIG_STM32_ADC1_DMA_BATCH]; #endif static struct stm32_dev_s g_adcpriv1 = @@ -305,19 +305,19 @@ static struct stm32_dev_s g_adcpriv1 = .mbase = STM32_ADC1_BASE, .initialized = false, #ifdef ADC1_HAVE_TIMER - .trigger = CONFIG_STM32H7_ADC1_TIMTRIG, + .trigger = CONFIG_STM32_ADC1_TIMTRIG, .tbase = ADC1_TIMER_BASE, .trcc_enr = ADC1_TIMER_RCC_ENR, .trcc_en = ADC1_TIMER_RCC_EN, .extsel = ADC1_EXTSEL_VALUE, .pclck = ADC1_TIMER_PCLK_FREQUENCY, - .freq = CONFIG_STM32H7_ADC1_SAMPLE_FREQUENCY, + .freq = CONFIG_STM32_ADC1_SAMPLE_FREQUENCY, #endif #ifdef ADC1_HAVE_DMA .dmachan = ADC1_DMA_CHAN, .hasdma = true, .r_dmabuffer = g_adc1_dmabuffer, - .dmabatch = CONFIG_STM32H7_ADC1_DMA_BATCH, + .dmabatch = CONFIG_STM32_ADC1_DMA_BATCH, #endif #ifdef ADC1_HAVE_DFSDM .hasdfsdm = true, @@ -339,11 +339,11 @@ static struct adc_dev_s g_adcdev1 = /* ADC2 state */ -#ifdef CONFIG_STM32H7_ADC2 +#ifdef CONFIG_STM32_ADC2 #ifdef ADC2_HAVE_DMA -static uint16_t g_adc2_dmabuffer[CONFIG_STM32H7_ADC_MAX_SAMPLES * - CONFIG_STM32H7_ADC2_DMA_BATCH]; +static uint16_t g_adc2_dmabuffer[CONFIG_STM32_ADC_MAX_SAMPLES * + CONFIG_STM32_ADC2_DMA_BATCH]; #endif static struct stm32_dev_s g_adcpriv2 = @@ -355,19 +355,19 @@ static struct stm32_dev_s g_adcpriv2 = .mbase = STM32_ADC1_BASE, .initialized = false, #ifdef ADC2_HAVE_TIMER - .trigger = CONFIG_STM32H7_ADC2_TIMTRIG, + .trigger = CONFIG_STM32_ADC2_TIMTRIG, .tbase = ADC2_TIMER_BASE, .trcc_enr = ADC2_TIMER_RCC_ENR, .trcc_en = ADC2_TIMER_RCC_EN, .extsel = ADC2_EXTSEL_VALUE, .pclck = ADC2_TIMER_PCLK_FREQUENCY, - .freq = CONFIG_STM32H7_ADC2_SAMPLE_FREQUENCY, + .freq = CONFIG_STM32_ADC2_SAMPLE_FREQUENCY, #endif #ifdef ADC2_HAVE_DMA .dmachan = ADC2_DMA_CHAN, .hasdma = true, .r_dmabuffer = g_adc2_dmabuffer, - .dmabatch = CONFIG_STM32H7_ADC2_DMA_BATCH, + .dmabatch = CONFIG_STM32_ADC2_DMA_BATCH, #endif #ifdef ADC2_HAVE_DFSDM .hasdfsdm = true, @@ -389,11 +389,11 @@ static struct adc_dev_s g_adcdev2 = /* ADC3 state */ -#ifdef CONFIG_STM32H7_ADC3 +#ifdef CONFIG_STM32_ADC3 #ifdef ADC3_HAVE_DMA -static uint16_t g_adc3_dmabuffer[CONFIG_STM32H7_ADC_MAX_SAMPLES * - CONFIG_STM32H7_ADC3_DMA_BATCH]; +static uint16_t g_adc3_dmabuffer[CONFIG_STM32_ADC_MAX_SAMPLES * + CONFIG_STM32_ADC3_DMA_BATCH]; #endif static struct stm32_dev_s g_adcpriv3 = @@ -405,19 +405,19 @@ static struct stm32_dev_s g_adcpriv3 = .mbase = STM32_ADC3_BASE, .initialized = false, #ifdef ADC3_HAVE_TIMER - .trigger = CONFIG_STM32H7_ADC3_TIMTRIG, + .trigger = CONFIG_STM32_ADC3_TIMTRIG, .tbase = ADC3_TIMER_BASE, .trcc_enr = ADC3_TIMER_RCC_ENR, .trcc_en = ADC3_TIMER_RCC_EN, .extsel = ADC3_EXTSEL_VALUE, .pclck = ADC3_TIMER_PCLK_FREQUENCY, - .freq = CONFIG_STM32H7_ADC3_SAMPLE_FREQUENCY, + .freq = CONFIG_STM32_ADC3_SAMPLE_FREQUENCY, #endif #ifdef ADC3_HAVE_DMA .dmachan = ADC3_DMA_CHAN, .hasdma = true, .r_dmabuffer = g_adc3_dmabuffer, - .dmabatch = CONFIG_STM32H7_ADC3_DMA_BATCH, + .dmabatch = CONFIG_STM32_ADC3_DMA_BATCH, #endif #ifdef ADC3_HAVE_DFSDM .hasdfsdm = true, @@ -1381,7 +1381,7 @@ static int adc_setup(struct adc_dev_s *dev) * ADC1 and ADC2 are enabled.) */ -#if defined(CONFIG_STM32H7_ADC1) && defined(CONFIG_STM32H7_ADC2) +#if defined(CONFIG_STM32_ADC1) && defined(CONFIG_STM32_ADC2) if ((dev == &g_adcdev1 && !((struct stm32_dev_s *)g_adcdev2.ad_priv)->initialized) || (dev == &g_adcdev2 && @@ -1880,7 +1880,7 @@ static int adc_set_ch(struct adc_dev_s *dev, uint8_t ch) priv->rnchannels = 1; } - DEBUGASSERT(priv->rnchannels <= CONFIG_STM32H7_ADC_MAX_SAMPLES); + DEBUGASSERT(priv->rnchannels <= CONFIG_STM32_ADC_MAX_SAMPLES); bits = adc_sqrbits(priv, ADC_SQR4_FIRST, ADC_SQR4_LAST, ADC_SQR4_SQ_OFFSET); @@ -2162,13 +2162,13 @@ static int adc_interrupt(struct adc_dev_s *dev, uint32_t adcisr) * ****************************************************************************/ -#if defined(CONFIG_STM32H7_ADC1) || defined(CONFIG_STM32H7_ADC2) +#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) static int adc12_interrupt(int irq, void *context, void *arg) { uint32_t regval; uint32_t pending; -#ifdef CONFIG_STM32H7_ADC1 +#ifdef CONFIG_STM32_ADC1 regval = getreg32(STM32_ADC1_ISR); pending = regval & ADC_INT_MASK; if (pending != 0) @@ -2177,7 +2177,7 @@ static int adc12_interrupt(int irq, void *context, void *arg) } #endif -#ifdef CONFIG_STM32H7_ADC2 +#ifdef CONFIG_STM32_ADC2 regval = getreg32(STM32_ADC2_ISR); pending = regval & ADC_INT_MASK; if (pending != 0) @@ -2202,7 +2202,7 @@ static int adc12_interrupt(int irq, void *context, void *arg) * ****************************************************************************/ -#ifdef CONFIG_STM32H7_ADC3 +#ifdef CONFIG_STM32_ADC3 static int adc3_interrupt(int irq, void *context, void *arg) { uint32_t regval; @@ -2276,7 +2276,7 @@ static void adc_dmaconvcallback(DMA_HANDLE handle, uint8_t isr, ****************************************************************************/ /**************************************************************************** - * Name: stm32h7_adc_initialize + * Name: stm32_adc_initialize * * Description: * Initialize the ADC. @@ -2301,7 +2301,7 @@ static void adc_dmaconvcallback(DMA_HANDLE handle, uint8_t isr, * ****************************************************************************/ -struct adc_dev_s *stm32h7_adc_initialize(int intf, +struct adc_dev_s *stm32_adc_initialize(int intf, const uint8_t *chanlist, int cchannels) { @@ -2312,19 +2312,19 @@ struct adc_dev_s *stm32h7_adc_initialize(int intf, switch (intf) { -#ifdef CONFIG_STM32H7_ADC1 +#ifdef CONFIG_STM32_ADC1 case 1: ainfo("ADC1 selected\n"); dev = &g_adcdev1; break; #endif -#ifdef CONFIG_STM32H7_ADC2 +#ifdef CONFIG_STM32_ADC2 case 2: ainfo("ADC2 selected\n"); dev = &g_adcdev2; break; #endif -#ifdef CONFIG_STM32H7_ADC3 +#ifdef CONFIG_STM32_ADC3 case 3: ainfo("ADC3 selected\n"); dev = &g_adcdev3; @@ -2340,10 +2340,10 @@ struct adc_dev_s *stm32h7_adc_initialize(int intf, priv = (struct stm32_dev_s *)dev->ad_priv; priv->cb = NULL; - DEBUGASSERT(cchannels <= CONFIG_STM32H7_ADC_MAX_SAMPLES); - if (cchannels > CONFIG_STM32H7_ADC_MAX_SAMPLES) + DEBUGASSERT(cchannels <= CONFIG_STM32_ADC_MAX_SAMPLES); + if (cchannels > CONFIG_STM32_ADC_MAX_SAMPLES) { - cchannels = CONFIG_STM32H7_ADC_MAX_SAMPLES; + cchannels = CONFIG_STM32_ADC_MAX_SAMPLES; } priv->cchannels = cchannels; @@ -2360,5 +2360,5 @@ struct adc_dev_s *stm32h7_adc_initialize(int intf, return dev; } -#endif /* CONFIG_STM32H7_ADC1 || CONFIG_STM32H7_ADC2 || CONFIG_STM32H7_ADC3 */ +#endif /* CONFIG_STM32_ADC1 || CONFIG_STM32_ADC2 || CONFIG_STM32_ADC3 */ #endif /* CONFIG_ADC */ diff --git a/arch/arm/src/stm32h7/stm32_adc.h b/arch/arm/src/stm32h7/stm32_adc.h index df7e5132e0590..a22ebb45e0cff 100644 --- a/arch/arm/src/stm32h7/stm32_adc.h +++ b/arch/arm/src/stm32h7/stm32_adc.h @@ -39,87 +39,87 @@ /* Configuration ************************************************************/ /* Timer devices may be used for different purposes. One special purpose is - * to control periodic ADC sampling. If CONFIG_STM32H7_TIMn is defined then - * CONFIG_STM32H7_TIMn_ADC must also be defined to indicate that timer "n" + * to control periodic ADC sampling. If CONFIG_STM32_TIMn is defined then + * CONFIG_STM32_TIMn_ADC must also be defined to indicate that timer "n" * is intended to be used for that purpose. Timers 1,2,3,6 and 15 may be * used on STM32H7X3, while STM32H7X6 adds support for timers 4 and 8 as * well. */ -#ifndef CONFIG_STM32H7_TIM1 -# undef CONFIG_STM32H7_TIM1_ADC -# undef CONFIG_STM32H7_TIM1_ADC1 -# undef CONFIG_STM32H7_TIM1_ADC2 -# undef CONFIG_STM32H7_TIM1_ADC3 +#ifndef CONFIG_STM32_TIM1 +# undef CONFIG_STM32_TIM1_ADC +# undef CONFIG_STM32_TIM1_ADC1 +# undef CONFIG_STM32_TIM1_ADC2 +# undef CONFIG_STM32_TIM1_ADC3 #endif -#ifndef CONFIG_STM32H7_TIM2 -# undef CONFIG_STM32H7_TIM2_ADC -# undef CONFIG_STM32H7_TIM2_ADC1 -# undef CONFIG_STM32H7_TIM2_ADC2 -# undef CONFIG_STM32H7_TIM2_ADC3 +#ifndef CONFIG_STM32_TIM2 +# undef CONFIG_STM32_TIM2_ADC +# undef CONFIG_STM32_TIM2_ADC1 +# undef CONFIG_STM32_TIM2_ADC2 +# undef CONFIG_STM32_TIM2_ADC3 #endif -#ifndef CONFIG_STM32H7_TIM3 -# undef CONFIG_STM32H7_TIM3_ADC -# undef CONFIG_STM32H7_TIM3_ADC1 -# undef CONFIG_STM32H7_TIM3_ADC2 -# undef CONFIG_STM32H7_TIM3_ADC3 +#ifndef CONFIG_STM32_TIM3 +# undef CONFIG_STM32_TIM3_ADC +# undef CONFIG_STM32_TIM3_ADC1 +# undef CONFIG_STM32_TIM3_ADC2 +# undef CONFIG_STM32_TIM3_ADC3 #endif -#ifndef CONFIG_STM32H7_TIM4 -# undef CONFIG_STM32H7_TIM4_ADC -# undef CONFIG_STM32H7_TIM4_ADC1 -# undef CONFIG_STM32H7_TIM4_ADC2 -# undef CONFIG_STM32H7_TIM4_ADC3 +#ifndef CONFIG_STM32_TIM4 +# undef CONFIG_STM32_TIM4_ADC +# undef CONFIG_STM32_TIM4_ADC1 +# undef CONFIG_STM32_TIM4_ADC2 +# undef CONFIG_STM32_TIM4_ADC3 #endif -#ifndef CONFIG_STM32H7_TIM6 -# undef CONFIG_STM32H7_TIM6_ADC -# undef CONFIG_STM32H7_TIM6_ADC1 -# undef CONFIG_STM32H7_TIM6_ADC2 -# undef CONFIG_STM32H7_TIM6_ADC3 +#ifndef CONFIG_STM32_TIM6 +# undef CONFIG_STM32_TIM6_ADC +# undef CONFIG_STM32_TIM6_ADC1 +# undef CONFIG_STM32_TIM6_ADC2 +# undef CONFIG_STM32_TIM6_ADC3 #endif -#ifndef CONFIG_STM32H7_TIM8 -# undef CONFIG_STM32H7_TIM8_ADC -# undef CONFIG_STM32H7_TIM8_ADC1 -# undef CONFIG_STM32H7_TIM8_ADC2 -# undef CONFIG_STM32H7_TIM8_ADC3 +#ifndef CONFIG_STM32_TIM8 +# undef CONFIG_STM32_TIM8_ADC +# undef CONFIG_STM32_TIM8_ADC1 +# undef CONFIG_STM32_TIM8_ADC2 +# undef CONFIG_STM32_TIM8_ADC3 #endif -#ifndef CONFIG_STM32H7_TIM15 -# undef CONFIG_STM32H7_TIM15_ADC -# undef CONFIG_STM32H7_TIM15_ADC1 -# undef CONFIG_STM32H7_TIM15_ADC2 -# undef CONFIG_STM32H7_TIM15_ADC3 +#ifndef CONFIG_STM32_TIM15 +# undef CONFIG_STM32_TIM15_ADC +# undef CONFIG_STM32_TIM15_ADC1 +# undef CONFIG_STM32_TIM15_ADC2 +# undef CONFIG_STM32_TIM15_ADC3 #endif -#if defined(CONFIG_STM32H7_ADC1) || defined(CONFIG_STM32H7_ADC2) || \ - defined(CONFIG_STM32H7_ADC3) +#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) || \ + defined(CONFIG_STM32_ADC3) /* ADC output to DFSDM support. Note that DFSDM and DMA are * mutually exclusive. */ #undef ADC_HAVE_DFSDM -#if defined(CONFIG_STM32H7_ADC1_OUTPUT_DFSDM) || \ - defined(CONFIG_STM32H7_ADC2_OUTPUT_DFSDM) || \ - defined(CONFIG_STM32H7_ADC3_OUTPUT_DFSDM) +#if defined(CONFIG_STM32_ADC1_OUTPUT_DFSDM) || \ + defined(CONFIG_STM32_ADC2_OUTPUT_DFSDM) || \ + defined(CONFIG_STM32_ADC3_OUTPUT_DFSDM) # define ADC_HAVE_DFSDM #endif -#if defined(CONFIG_STM32H7_ADC1_OUTPUT_DFSDM) +#if defined(CONFIG_STM32_ADC1_OUTPUT_DFSDM) # define ADC1_HAVE_DFSDM 1 -# undef CONFIG_STM32H7_ADC1_DMA +# undef CONFIG_STM32_ADC1_DMA #else # undef ADC1_HAVE_DFSDM #endif -#if defined(CONFIG_STM32H7_ADC2_OUTPUT_DFSDM) +#if defined(CONFIG_STM32_ADC2_OUTPUT_DFSDM) # define ADC2_HAVE_DFSDM 1 -# undef CONFIG_STM32H7_ADC2_DMA +# undef CONFIG_STM32_ADC2_DMA #else # undef ADC2_HAVE_DFSDM #endif -#if defined(CONFIG_STM32H7_ADC3_OUTPUT_DFSDM) +#if defined(CONFIG_STM32_ADC3_OUTPUT_DFSDM) # define ADC3_HAVE_DFSDM 1 -# undef CONFIG_STM32H7_ADC3_DMA +# undef CONFIG_STM32_ADC3_DMA #else # undef ADC3_HAVE_DFSDM #endif @@ -127,24 +127,24 @@ /* DMA support */ #undef ADC_HAVE_DMA -#if defined(CONFIG_STM32H7_ADC1_DMA) || defined(CONFIG_STM32H7_ADC2_DMA) || \ - defined(CONFIG_STM32H7_ADC3_DMA) +#if defined(CONFIG_STM32_ADC1_DMA) || defined(CONFIG_STM32_ADC2_DMA) || \ + defined(CONFIG_STM32_ADC3_DMA) # define ADC_HAVE_DMA 1 #endif -#ifdef CONFIG_STM32H7_ADC1_DMA +#ifdef CONFIG_STM32_ADC1_DMA # define ADC1_HAVE_DMA 1 #else # undef ADC1_HAVE_DMA #endif -#ifdef CONFIG_STM32H7_ADC2_DMA +#ifdef CONFIG_STM32_ADC2_DMA # define ADC2_HAVE_DMA 1 #else # undef ADC2_HAVE_DMA #endif -#ifdef CONFIG_STM32H7_ADC3_DMA +#ifdef CONFIG_STM32_ADC3_DMA # define ADC3_HAVE_DMA 1 #else # undef ADC3_HAVE_DMA @@ -154,43 +154,43 @@ * information about the timer. */ -#if defined(CONFIG_STM32H7_TIM1_ADC1) +#if defined(CONFIG_STM32_TIM1_ADC1) # define ADC1_HAVE_TIMER 1 # define ADC1_TIMER_BASE STM32_TIM1_BASE # define ADC1_TIMER_PCLK_FREQUENCY STM32_APB2_TIM1_CLKIN # define ADC1_TIMER_RCC_ENR STM32_RCC_APB2ENR # define ADC1_TIMER_RCC_EN RCC_APB2ENR_TIM1EN -#elif defined(CONFIG_STM32H7_TIM2_ADC1) +#elif defined(CONFIG_STM32_TIM2_ADC1) # define ADC1_HAVE_TIMER 1 # define ADC1_TIMER_BASE STM32_TIM2_BASE # define ADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM2_CLKIN # define ADC1_TIMER_RCC_ENR STM32_RCC_APB1LENR # define ADC1_TIMER_RCC_EN RCC_APB1LENR_TIM2EN -#elif defined(CONFIG_STM32H7_TIM3_ADC1) +#elif defined(CONFIG_STM32_TIM3_ADC1) # define ADC1_HAVE_TIMER 1 # define ADC1_TIMER_BASE STM32_TIM3_BASE # define ADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM3_CLKIN # define ADC1_TIMER_RCC_ENR STM32_RCC_APB1LENR # define ADC1_TIMER_RCC_EN RCC_APB1LENR_TIM3EN -#elif defined(CONFIG_STM32H7_TIM4_ADC1) +#elif defined(CONFIG_STM32_TIM4_ADC1) # define ADC1_HAVE_TIMER 1 # define ADC1_TIMER_BASE STM32_TIM4_BASE # define ADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM4_CLKIN # define ADC1_TIMER_RCC_ENR STM32_RCC_APB1LENR # define ADC1_TIMER_RCC_EN RCC_APB1LENR_TIM4EN -#elif defined(CONFIG_STM32H7_TIM6_ADC1) +#elif defined(CONFIG_STM32_TIM6_ADC1) # define ADC1_HAVE_TIMER 1 # define ADC1_TIMER_BASE STM32_TIM6_BASE # define ADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM6_CLKIN # define ADC1_TIMER_RCC_ENR STM32_RCC_APB1LENR # define ADC1_TIMER_RCC_EN RCC_APB1LENR_TIM6EN -#elif defined(CONFIG_STM32H7_TIM8_ADC1) +#elif defined(CONFIG_STM32_TIM8_ADC1) # define ADC1_HAVE_TIMER 1 # define ADC1_TIMER_BASE STM32_TIM8_BASE # define ADC1_TIMER_PCLK_FREQUENCY STM32_APB2_TIM8_CLKIN # define ADC1_TIMER_RCC_ENR STM32_RCC_APB2ENR # define ADC1_TIMER_RCC_EN RCC_APB2ENR_TIM8EN -#elif defined(CONFIG_STM32H7_TIM15_ADC1) +#elif defined(CONFIG_STM32_TIM15_ADC1) # define ADC1_HAVE_TIMER 1 # define ADC1_TIMER_BASE STM32_TIM15_BASE # define ADC1_TIMER_PCLK_FREQUENCY STM32_APB2_TIM15_CLKIN @@ -201,52 +201,52 @@ #endif #ifdef ADC1_HAVE_TIMER -# ifndef CONFIG_STM32H7_ADC1_SAMPLE_FREQUENCY -# error "CONFIG_STM32H7_ADC1_SAMPLE_FREQUENCY not defined" +# ifndef CONFIG_STM32_ADC1_SAMPLE_FREQUENCY +# error "CONFIG_STM32_ADC1_SAMPLE_FREQUENCY not defined" # endif -# ifndef CONFIG_STM32H7_ADC1_TIMTRIG -# error "CONFIG_STM32H7_ADC1_TIMTRIG not defined" +# ifndef CONFIG_STM32_ADC1_TIMTRIG +# error "CONFIG_STM32_ADC1_TIMTRIG not defined" # warning "Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO" # endif #endif -#if defined(CONFIG_STM32H7_TIM1_ADC2) +#if defined(CONFIG_STM32_TIM1_ADC2) # define ADC2_HAVE_TIMER 1 # define ADC2_TIMER_BASE STM32_TIM1_BASE # define ADC2_TIMER_PCLK_FREQUENCY STM32_APB2_TIM1_CLKIN # define ADC2_TIMER_RCC_ENR STM32_RCC_APB2ENR # define ADC2_TIMER_RCC_EN RCC_APB2ENR_TIM1EN -#elif defined(CONFIG_STM32H7_TIM2_ADC2) +#elif defined(CONFIG_STM32_TIM2_ADC2) # define ADC2_HAVE_TIMER 1 # define ADC2_TIMER_BASE STM32_TIM2_BASE # define ADC2_TIMER_PCLK_FREQUENCY STM32_APB1_TIM2_CLKIN # define ADC2_TIMER_RCC_ENR STM32_RCC_APB1LENR # define ADC2_TIMER_RCC_EN RCC_APB1LENR_TIM2EN -#elif defined(CONFIG_STM32H7_TIM3_ADC2) +#elif defined(CONFIG_STM32_TIM3_ADC2) # define ADC2_HAVE_TIMER 1 # define ADC2_TIMER_BASE STM32_TIM3_BASE # define ADC2_TIMER_PCLK_FREQUENCY STM32_APB1_TIM3_CLKIN # define ADC2_TIMER_RCC_ENR STM32_RCC_APB1LENR # define ADC2_TIMER_RCC_EN RCC_APB1LENR_TIM3EN -#elif defined(CONFIG_STM32H7_TIM4_ADC2) +#elif defined(CONFIG_STM32_TIM4_ADC2) # define ADC2_HAVE_TIMER 1 # define ADC2_TIMER_BASE STM32_TIM4_BASE # define ADC2_TIMER_PCLK_FREQUENCY STM32_APB1_TIM4_CLKIN # define ADC2_TIMER_RCC_ENR STM32_RCC_APB1LENR # define ADC2_TIMER_RCC_EN RCC_APB1LENR_TIM4EN -#elif defined(CONFIG_STM32H7_TIM6_ADC2) +#elif defined(CONFIG_STM32_TIM6_ADC2) # define ADC2_HAVE_TIMER 1 # define ADC2_TIMER_BASE STM32_TIM6_BASE # define ADC2_TIMER_PCLK_FREQUENCY STM32_APB1_TIM6_CLKIN # define ADC2_TIMER_RCC_ENR STM32_RCC_APB1LENR # define ADC2_TIMER_RCC_EN RCC_APB1LENR_TIM6EN -#elif defined(CONFIG_STM32H7_TIM8_ADC2) +#elif defined(CONFIG_STM32_TIM8_ADC2) # define ADC2_HAVE_TIMER 1 # define ADC2_TIMER_BASE STM32_TIM8_BASE # define ADC2_TIMER_PCLK_FREQUENCY STM32_APB2_TIM8_CLKIN # define ADC2_TIMER_RCC_ENR STM32_RCC_APB2ENR # define ADC2_TIMER_RCC_EN RCC_APB2ENR_TIM8EN -#elif defined(CONFIG_STM32H7_TIM15_ADC2) +#elif defined(CONFIG_STM32_TIM15_ADC2) # define ADC2_HAVE_TIMER 1 # define ADC2_TIMER_BASE STM32_TIM15_BASE # define ADC2_TIMER_PCLK_FREQUENCY STM32_APB2_TIM15_CLKIN @@ -257,52 +257,52 @@ #endif #ifdef ADC2_HAVE_TIMER -# ifndef CONFIG_STM32H7_ADC2_SAMPLE_FREQUENCY -# error "CONFIG_STM32H7_ADC2_SAMPLE_FREQUENCY not defined" +# ifndef CONFIG_STM32_ADC2_SAMPLE_FREQUENCY +# error "CONFIG_STM32_ADC2_SAMPLE_FREQUENCY not defined" # endif -# ifndef CONFIG_STM32H7_ADC2_TIMTRIG -# error "CONFIG_STM32H7_ADC2_TIMTRIG not defined" +# ifndef CONFIG_STM32_ADC2_TIMTRIG +# error "CONFIG_STM32_ADC2_TIMTRIG not defined" # warning "Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO" # endif #endif -#if defined(CONFIG_STM32H7_TIM1_ADC3) +#if defined(CONFIG_STM32_TIM1_ADC3) # define ADC3_HAVE_TIMER 1 # define ADC3_TIMER_BASE STM32_TIM1_BASE # define ADC3_TIMER_PCLK_FREQUENCY STM32_APB2_TIM1_CLKIN # define ADC3_TIMER_RCC_ENR STM32_RCC_APB2ENR # define ADC3_TIMER_RCC_EN RCC_APB2ENR_TIM1EN -#elif defined(CONFIG_STM32H7_TIM2_ADC3) +#elif defined(CONFIG_STM32_TIM2_ADC3) # define ADC3_HAVE_TIMER 1 # define ADC3_TIMER_BASE STM32_TIM2_BASE # define ADC3_TIMER_PCLK_FREQUENCY STM32_APB1_TIM2_CLKIN # define ADC3_TIMER_RCC_ENR STM32_RCC_APB1LENR # define ADC3_TIMER_RCC_EN RCC_APB1LENR_TIM2EN -#elif defined(CONFIG_STM32H7_TIM3_ADC3) +#elif defined(CONFIG_STM32_TIM3_ADC3) # define ADC3_HAVE_TIMER 1 # define ADC3_TIMER_BASE STM32_TIM3_BASE # define ADC3_TIMER_PCLK_FREQUENCY STM32_APB1_TIM3_CLKIN # define ADC3_TIMER_RCC_ENR STM32_RCC_APB1LENR # define ADC3_TIMER_RCC_EN RCC_APB1LENR_TIM3EN -#elif defined(CONFIG_STM32H7_TIM4_ADC3) +#elif defined(CONFIG_STM32_TIM4_ADC3) # define ADC3_HAVE_TIMER 1 # define ADC3_TIMER_BASE STM32_TIM4_BASE # define ADC3_TIMER_PCLK_FREQUENCY STM32_APB1_TIM4_CLKIN # define ADC3_TIMER_RCC_ENR STM32_RCC_APB1LENR # define ADC3_TIMER_RCC_EN RCC_APB1LENR_TIM4EN -#elif defined(CONFIG_STM32H7_TIM6_ADC3) +#elif defined(CONFIG_STM32_TIM6_ADC3) # define ADC3_HAVE_TIMER 1 # define ADC3_TIMER_BASE STM32_TIM6_BASE # define ADC3_TIMER_PCLK_FREQUENCY STM32_APB1_TIM6_CLKIN # define ADC3_TIMER_RCC_ENR STM32_RCC_APB1LENR # define ADC3_TIMER_RCC_EN RCC_APB1LENR_TIM6EN -#elif defined(CONFIG_STM32H7_TIM8_ADC3) +#elif defined(CONFIG_STM32_TIM8_ADC3) # define ADC3_HAVE_TIMER 1 # define ADC3_TIMER_BASE STM32_TIM8_BASE # define ADC3_TIMER_PCLK_FREQUENCY STM32_APB2_TIM8_CLKIN # define ADC3_TIMER_RCC_ENR STM32_RCC_APB2ENR # define ADC3_TIMER_RCC_EN RCC_APB2ENR_TIM8EN -#elif defined(CONFIG_STM32H7_TIM15_ADC3) +#elif defined(CONFIG_STM32_TIM15_ADC3) # define ADC3_HAVE_TIMER 1 # define ADC3_TIMER_BASE STM32_TIM15_BASE # define ADC3_TIMER_PCLK_FREQUENCY STM32_APB2_TIM15_CLKIN @@ -313,11 +313,11 @@ #endif #ifdef ADC3_HAVE_TIMER -# ifndef CONFIG_STM32H7_ADC3_SAMPLE_FREQUENCY -# error "CONFIG_STM32H7_ADC3_SAMPLE_FREQUENCY not defined" +# ifndef CONFIG_STM32_ADC3_SAMPLE_FREQUENCY +# error "CONFIG_STM32_ADC3_SAMPLE_FREQUENCY not defined" # endif -# ifndef CONFIG_STM32H7_ADC3_TIMTRIG -# error "CONFIG_STM32H7_ADC3_TIMTRIG not defined" +# ifndef CONFIG_STM32_ADC3_TIMTRIG +# error "CONFIG_STM32_ADC3_TIMTRIG not defined" # warning "Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO" # endif #endif @@ -455,315 +455,315 @@ #define ADC3_EXTSEL_T15CC4 ADC_CFGR_EXTSEL_T15CC4 #define ADC3_EXTSEL_T15TRGO ADC_CFGR_EXTSEL_T15TRGO -#if defined(CONFIG_STM32H7_TIM1_ADC1) -# if CONFIG_STM32H7_ADC1_TIMTRIG == 0 +#if defined(CONFIG_STM32_TIM1_ADC1) +# if CONFIG_STM32_ADC1_TIMTRIG == 0 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T1CC1 -# elif CONFIG_STM32H7_ADC1_TIMTRIG == 1 +# elif CONFIG_STM32_ADC1_TIMTRIG == 1 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T1CC2 -# elif CONFIG_STM32H7_ADC1_TIMTRIG == 2 +# elif CONFIG_STM32_ADC1_TIMTRIG == 2 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T1CC3 -# elif CONFIG_STM32H7_ADC1_TIMTRIG == 3 +# elif CONFIG_STM32_ADC1_TIMTRIG == 3 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T1CC4 -# elif CONFIG_STM32H7_ADC1_TIMTRIG == 4 +# elif CONFIG_STM32_ADC1_TIMTRIG == 4 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T1TRGO -# elif CONFIG_STM32H7_ADC1_TIMTRIG == 5 +# elif CONFIG_STM32_ADC1_TIMTRIG == 5 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T1TRGO2 # else -# error "CONFIG_STM32H7_ADC1_TIMTRIG is out of range" +# error "CONFIG_STM32_ADC1_TIMTRIG is out of range" # endif -#elif defined(CONFIG_STM32H7_TIM2_ADC1) -# if CONFIG_STM32H7_ADC1_TIMTRIG == 0 +#elif defined(CONFIG_STM32_TIM2_ADC1) +# if CONFIG_STM32_ADC1_TIMTRIG == 0 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T2CC1 -# elif CONFIG_STM32H7_ADC1_TIMTRIG == 1 +# elif CONFIG_STM32_ADC1_TIMTRIG == 1 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T2CC2 -# elif CONFIG_STM32H7_ADC1_TIMTRIG == 2 +# elif CONFIG_STM32_ADC1_TIMTRIG == 2 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T2CC3 -# elif CONFIG_STM32H7_ADC1_TIMTRIG == 3 +# elif CONFIG_STM32_ADC1_TIMTRIG == 3 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T2CC4 -# elif CONFIG_STM32H7_ADC1_TIMTRIG == 4 +# elif CONFIG_STM32_ADC1_TIMTRIG == 4 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T2TRGO # else -# error "CONFIG_STM32H7_ADC1_TIMTRIG is out of range" +# error "CONFIG_STM32_ADC1_TIMTRIG is out of range" # endif -#elif defined(CONFIG_STM32H7_TIM3_ADC1) -# if CONFIG_STM32H7_ADC1_TIMTRIG == 0 +#elif defined(CONFIG_STM32_TIM3_ADC1) +# if CONFIG_STM32_ADC1_TIMTRIG == 0 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T3CC1 -# elif CONFIG_STM32H7_ADC1_TIMTRIG == 1 +# elif CONFIG_STM32_ADC1_TIMTRIG == 1 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T3CC2 -# elif CONFIG_STM32H7_ADC1_TIMTRIG == 2 +# elif CONFIG_STM32_ADC1_TIMTRIG == 2 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T3CC3 -# elif CONFIG_STM32H7_ADC1_TIMTRIG == 3 +# elif CONFIG_STM32_ADC1_TIMTRIG == 3 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T3CC4 -# elif CONFIG_STM32H7_ADC1_TIMTRIG == 4 +# elif CONFIG_STM32_ADC1_TIMTRIG == 4 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T3TRGO # else -# error "CONFIG_STM32H7_ADC1_TIMTRIG is out of range" +# error "CONFIG_STM32_ADC1_TIMTRIG is out of range" # endif -#elif defined(CONFIG_STM32H7_TIM4_ADC1) -# if CONFIG_STM32H7_ADC1_TIMTRIG == 0 +#elif defined(CONFIG_STM32_TIM4_ADC1) +# if CONFIG_STM32_ADC1_TIMTRIG == 0 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T4CC1 -# elif CONFIG_STM32H7_ADC1_TIMTRIG == 1 +# elif CONFIG_STM32_ADC1_TIMTRIG == 1 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T4CC2 -# elif CONFIG_STM32H7_ADC1_TIMTRIG == 2 +# elif CONFIG_STM32_ADC1_TIMTRIG == 2 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T4CC3 -# elif CONFIG_STM32H7_ADC1_TIMTRIG == 3 +# elif CONFIG_STM32_ADC1_TIMTRIG == 3 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T4CC4 -# elif CONFIG_STM32H7_ADC1_TIMTRIG == 4 +# elif CONFIG_STM32_ADC1_TIMTRIG == 4 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T4TRGO # else -# error "CONFIG_STM32H7_ADC1_TIMTRIG is out of range" +# error "CONFIG_STM32_ADC1_TIMTRIG is out of range" # endif -#elif defined(CONFIG_STM32H7_TIM6_ADC1) -# if CONFIG_STM32H7_ADC1_TIMTRIG == 0 +#elif defined(CONFIG_STM32_TIM6_ADC1) +# if CONFIG_STM32_ADC1_TIMTRIG == 0 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T6CC1 -# elif CONFIG_STM32H7_ADC1_TIMTRIG == 1 +# elif CONFIG_STM32_ADC1_TIMTRIG == 1 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T6CC2 -# elif CONFIG_STM32H7_ADC1_TIMTRIG == 2 +# elif CONFIG_STM32_ADC1_TIMTRIG == 2 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T6CC3 -# elif CONFIG_STM32H7_ADC1_TIMTRIG == 3 +# elif CONFIG_STM32_ADC1_TIMTRIG == 3 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T6CC4 -# elif CONFIG_STM32H7_ADC1_TIMTRIG == 4 +# elif CONFIG_STM32_ADC1_TIMTRIG == 4 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T6TRGO # else -# error "CONFIG_STM32H7_ADC1_TIMTRIG is out of range" +# error "CONFIG_STM32_ADC1_TIMTRIG is out of range" # endif -#elif defined(CONFIG_STM32H7_TIM8_ADC1) -# if CONFIG_STM32H7_ADC1_TIMTRIG == 0 +#elif defined(CONFIG_STM32_TIM8_ADC1) +# if CONFIG_STM32_ADC1_TIMTRIG == 0 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T8CC1 -# elif CONFIG_STM32H7_ADC1_TIMTRIG == 1 +# elif CONFIG_STM32_ADC1_TIMTRIG == 1 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T8CC2 -# elif CONFIG_STM32H7_ADC1_TIMTRIG == 2 +# elif CONFIG_STM32_ADC1_TIMTRIG == 2 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T8CC3 -# elif CONFIG_STM32H7_ADC1_TIMTRIG == 3 +# elif CONFIG_STM32_ADC1_TIMTRIG == 3 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T8CC4 -# elif CONFIG_STM32H7_ADC1_TIMTRIG == 4 +# elif CONFIG_STM32_ADC1_TIMTRIG == 4 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T8TRGO -# elif CONFIG_STM32H7_ADC1_TIMTRIG == 5 +# elif CONFIG_STM32_ADC1_TIMTRIG == 5 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T8TRGO2 # else -# error "CONFIG_STM32H7_ADC1_TIMTRIG is out of range" +# error "CONFIG_STM32_ADC1_TIMTRIG is out of range" # endif -#elif defined(CONFIG_STM32H7_TIM15_ADC1) -# if CONFIG_STM32H7_ADC1_TIMTRIG == 0 +#elif defined(CONFIG_STM32_TIM15_ADC1) +# if CONFIG_STM32_ADC1_TIMTRIG == 0 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T15CC1 -# elif CONFIG_STM32H7_ADC1_TIMTRIG == 1 +# elif CONFIG_STM32_ADC1_TIMTRIG == 1 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T15CC2 -# elif CONFIG_STM32H7_ADC1_TIMTRIG == 2 +# elif CONFIG_STM32_ADC1_TIMTRIG == 2 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T15CC3 -# elif CONFIG_STM32H7_ADC1_TIMTRIG == 3 +# elif CONFIG_STM32_ADC1_TIMTRIG == 3 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T15CC4 -# elif CONFIG_STM32H7_ADC1_TIMTRIG == 4 +# elif CONFIG_STM32_ADC1_TIMTRIG == 4 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T15TRGO # else -# error "CONFIG_STM32H7_ADC1_TIMTRIG is out of range" +# error "CONFIG_STM32_ADC1_TIMTRIG is out of range" # endif #endif -#if defined(CONFIG_STM32H7_TIM1_ADC2) -# if CONFIG_STM32H7_ADC2_TIMTRIG == 0 +#if defined(CONFIG_STM32_TIM1_ADC2) +# if CONFIG_STM32_ADC2_TIMTRIG == 0 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T1CC1 -# elif CONFIG_STM32H7_ADC2_TIMTRIG == 1 +# elif CONFIG_STM32_ADC2_TIMTRIG == 1 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T1CC2 -# elif CONFIG_STM32H7_ADC2_TIMTRIG == 2 +# elif CONFIG_STM32_ADC2_TIMTRIG == 2 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T1CC3 -# elif CONFIG_STM32H7_ADC2_TIMTRIG == 3 +# elif CONFIG_STM32_ADC2_TIMTRIG == 3 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T1CC4 -# elif CONFIG_STM32H7_ADC2_TIMTRIG == 4 +# elif CONFIG_STM32_ADC2_TIMTRIG == 4 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T1TRGO -# elif CONFIG_STM32H7_ADC2_TIMTRIG == 5 +# elif CONFIG_STM32_ADC2_TIMTRIG == 5 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T1TRGO2 # else -# error "CONFIG_STM32H7_ADC2_TIMTRIG is out of range" +# error "CONFIG_STM32_ADC2_TIMTRIG is out of range" # endif -#elif defined(CONFIG_STM32H7_TIM2_ADC2) -# if CONFIG_STM32H7_ADC2_TIMTRIG == 0 +#elif defined(CONFIG_STM32_TIM2_ADC2) +# if CONFIG_STM32_ADC2_TIMTRIG == 0 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T2CC1 -# elif CONFIG_STM32H7_ADC2_TIMTRIG == 1 +# elif CONFIG_STM32_ADC2_TIMTRIG == 1 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T2CC2 -# elif CONFIG_STM32H7_ADC2_TIMTRIG == 2 +# elif CONFIG_STM32_ADC2_TIMTRIG == 2 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T2CC3 -# elif CONFIG_STM32H7_ADC2_TIMTRIG == 3 +# elif CONFIG_STM32_ADC2_TIMTRIG == 3 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T2CC4 -# elif CONFIG_STM32H7_ADC2_TIMTRIG == 4 +# elif CONFIG_STM32_ADC2_TIMTRIG == 4 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T2TRGO # else -# error "CONFIG_STM32H7_ADC2_TIMTRIG is out of range" +# error "CONFIG_STM32_ADC2_TIMTRIG is out of range" # endif -#elif defined(CONFIG_STM32H7_TIM3_ADC2) -# if CONFIG_STM32H7_ADC2_TIMTRIG == 0 +#elif defined(CONFIG_STM32_TIM3_ADC2) +# if CONFIG_STM32_ADC2_TIMTRIG == 0 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T3CC1 -# elif CONFIG_STM32H7_ADC2_TIMTRIG == 1 +# elif CONFIG_STM32_ADC2_TIMTRIG == 1 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T3CC2 -# elif CONFIG_STM32H7_ADC2_TIMTRIG == 2 +# elif CONFIG_STM32_ADC2_TIMTRIG == 2 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T3CC3 -# elif CONFIG_STM32H7_ADC2_TIMTRIG == 3 +# elif CONFIG_STM32_ADC2_TIMTRIG == 3 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T3CC4 -# elif CONFIG_STM32H7_ADC2_TIMTRIG == 4 +# elif CONFIG_STM32_ADC2_TIMTRIG == 4 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T3TRGO # else -# error "CONFIG_STM32H7_ADC2_TIMTRIG is out of range" +# error "CONFIG_STM32_ADC2_TIMTRIG is out of range" # endif -#elif defined(CONFIG_STM32H7_TIM4_ADC2) -# if CONFIG_STM32H7_ADC2_TIMTRIG == 0 +#elif defined(CONFIG_STM32_TIM4_ADC2) +# if CONFIG_STM32_ADC2_TIMTRIG == 0 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T4CC1 -# elif CONFIG_STM32H7_ADC2_TIMTRIG == 1 +# elif CONFIG_STM32_ADC2_TIMTRIG == 1 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T4CC2 -# elif CONFIG_STM32H7_ADC2_TIMTRIG == 2 +# elif CONFIG_STM32_ADC2_TIMTRIG == 2 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T4CC3 -# elif CONFIG_STM32H7_ADC2_TIMTRIG == 3 +# elif CONFIG_STM32_ADC2_TIMTRIG == 3 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T4CC4 -# elif CONFIG_STM32H7_ADC2_TIMTRIG == 4 +# elif CONFIG_STM32_ADC2_TIMTRIG == 4 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T4TRGO # else -# error "CONFIG_STM32H7_ADC2_TIMTRIG is out of range" +# error "CONFIG_STM32_ADC2_TIMTRIG is out of range" # endif -#elif defined(CONFIG_STM32H7_TIM6_ADC2) -# if CONFIG_STM32H7_ADC2_TIMTRIG == 0 +#elif defined(CONFIG_STM32_TIM6_ADC2) +# if CONFIG_STM32_ADC2_TIMTRIG == 0 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T6CC1 -# elif CONFIG_STM32H7_ADC2_TIMTRIG == 1 +# elif CONFIG_STM32_ADC2_TIMTRIG == 1 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T6CC2 -# elif CONFIG_STM32H7_ADC2_TIMTRIG == 2 +# elif CONFIG_STM32_ADC2_TIMTRIG == 2 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T6CC3 -# elif CONFIG_STM32H7_ADC2_TIMTRIG == 3 +# elif CONFIG_STM32_ADC2_TIMTRIG == 3 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T6CC4 -# elif CONFIG_STM32H7_ADC2_TIMTRIG == 4 +# elif CONFIG_STM32_ADC2_TIMTRIG == 4 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T6TRGO # else -# error "CONFIG_STM32H7_ADC2_TIMTRIG is out of range" +# error "CONFIG_STM32_ADC2_TIMTRIG is out of range" # endif -#elif defined(CONFIG_STM32H7_TIM8_ADC2) -# if CONFIG_STM32H7_ADC2_TIMTRIG == 0 +#elif defined(CONFIG_STM32_TIM8_ADC2) +# if CONFIG_STM32_ADC2_TIMTRIG == 0 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T8CC1 -# elif CONFIG_STM32H7_ADC2_TIMTRIG == 1 +# elif CONFIG_STM32_ADC2_TIMTRIG == 1 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T8CC2 -# elif CONFIG_STM32H7_ADC2_TIMTRIG == 2 +# elif CONFIG_STM32_ADC2_TIMTRIG == 2 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T8CC3 -# elif CONFIG_STM32H7_ADC2_TIMTRIG == 3 +# elif CONFIG_STM32_ADC2_TIMTRIG == 3 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T8CC4 -# elif CONFIG_STM32H7_ADC2_TIMTRIG == 4 +# elif CONFIG_STM32_ADC2_TIMTRIG == 4 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T8TRGO -# elif CONFIG_STM32H7_ADC2_TIMTRIG == 5 +# elif CONFIG_STM32_ADC2_TIMTRIG == 5 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T8TRGO2 # else -# error "CONFIG_STM32H7_ADC2_TIMTRIG is out of range" +# error "CONFIG_STM32_ADC2_TIMTRIG is out of range" # endif -#elif defined(CONFIG_STM32H7_TIM15_ADC2) -# if CONFIG_STM32H7_ADC2_TIMTRIG == 0 +#elif defined(CONFIG_STM32_TIM15_ADC2) +# if CONFIG_STM32_ADC2_TIMTRIG == 0 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T15CC1 -# elif CONFIG_STM32H7_ADC2_TIMTRIG == 1 +# elif CONFIG_STM32_ADC2_TIMTRIG == 1 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T15CC2 -# elif CONFIG_STM32H7_ADC2_TIMTRIG == 2 +# elif CONFIG_STM32_ADC2_TIMTRIG == 2 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T15CC3 -# elif CONFIG_STM32H7_ADC2_TIMTRIG == 3 +# elif CONFIG_STM32_ADC2_TIMTRIG == 3 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T15CC4 -# elif CONFIG_STM32H7_ADC2_TIMTRIG == 4 +# elif CONFIG_STM32_ADC2_TIMTRIG == 4 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T15TRGO # else -# error "CONFIG_STM32H7_ADC2_TIMTRIG is out of range" +# error "CONFIG_STM32_ADC2_TIMTRIG is out of range" # endif #endif -#if defined(CONFIG_STM32H7_TIM1_ADC3) -# if CONFIG_STM32H7_ADC3_TIMTRIG == 0 +#if defined(CONFIG_STM32_TIM1_ADC3) +# if CONFIG_STM32_ADC3_TIMTRIG == 0 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T1CC1 -# elif CONFIG_STM32H7_ADC3_TIMTRIG == 1 +# elif CONFIG_STM32_ADC3_TIMTRIG == 1 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T1CC2 -# elif CONFIG_STM32H7_ADC3_TIMTRIG == 2 +# elif CONFIG_STM32_ADC3_TIMTRIG == 2 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T1CC3 -# elif CONFIG_STM32H7_ADC3_TIMTRIG == 3 +# elif CONFIG_STM32_ADC3_TIMTRIG == 3 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T1CC4 -# elif CONFIG_STM32H7_ADC3_TIMTRIG == 4 +# elif CONFIG_STM32_ADC3_TIMTRIG == 4 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T1TRGO -# elif CONFIG_STM32H7_ADC3_TIMTRIG == 5 +# elif CONFIG_STM32_ADC3_TIMTRIG == 5 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T1TRGO2 # else -# error "CONFIG_STM32H7_ADC3_TIMTRIG is out of range" +# error "CONFIG_STM32_ADC3_TIMTRIG is out of range" # endif -#elif defined(CONFIG_STM32H7_TIM2_ADC3) -# if CONFIG_STM32H7_ADC3_TIMTRIG == 0 +#elif defined(CONFIG_STM32_TIM2_ADC3) +# if CONFIG_STM32_ADC3_TIMTRIG == 0 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T2CC1 -# elif CONFIG_STM32H7_ADC3_TIMTRIG == 1 +# elif CONFIG_STM32_ADC3_TIMTRIG == 1 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T2CC2 -# elif CONFIG_STM32H7_ADC3_TIMTRIG == 2 +# elif CONFIG_STM32_ADC3_TIMTRIG == 2 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T2CC3 -# elif CONFIG_STM32H7_ADC3_TIMTRIG == 3 +# elif CONFIG_STM32_ADC3_TIMTRIG == 3 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T2CC4 -# elif CONFIG_STM32H7_ADC3_TIMTRIG == 4 +# elif CONFIG_STM32_ADC3_TIMTRIG == 4 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T2TRGO # else -# error "CONFIG_STM32H7_ADC3_TIMTRIG is out of range" +# error "CONFIG_STM32_ADC3_TIMTRIG is out of range" # endif -#elif defined(CONFIG_STM32H7_TIM3_ADC3) -# if CONFIG_STM32H7_ADC3_TIMTRIG == 0 +#elif defined(CONFIG_STM32_TIM3_ADC3) +# if CONFIG_STM32_ADC3_TIMTRIG == 0 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T3CC1 -# elif CONFIG_STM32H7_ADC3_TIMTRIG == 1 +# elif CONFIG_STM32_ADC3_TIMTRIG == 1 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T3CC2 -# elif CONFIG_STM32H7_ADC3_TIMTRIG == 2 +# elif CONFIG_STM32_ADC3_TIMTRIG == 2 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T3CC3 -# elif CONFIG_STM32H7_ADC3_TIMTRIG == 3 +# elif CONFIG_STM32_ADC3_TIMTRIG == 3 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T3CC4 -# elif CONFIG_STM32H7_ADC3_TIMTRIG == 4 +# elif CONFIG_STM32_ADC3_TIMTRIG == 4 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T3TRGO # else -# error "CONFIG_STM32H7_ADC3_TIMTRIG is out of range" +# error "CONFIG_STM32_ADC3_TIMTRIG is out of range" # endif -#elif defined(CONFIG_STM32H7_TIM4_ADC3) -# if CONFIG_STM32H7_ADC3_TIMTRIG == 0 +#elif defined(CONFIG_STM32_TIM4_ADC3) +# if CONFIG_STM32_ADC3_TIMTRIG == 0 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T4CC1 -# elif CONFIG_STM32H7_ADC3_TIMTRIG == 1 +# elif CONFIG_STM32_ADC3_TIMTRIG == 1 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T4CC2 -# elif CONFIG_STM32H7_ADC3_TIMTRIG == 2 +# elif CONFIG_STM32_ADC3_TIMTRIG == 2 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T4CC3 -# elif CONFIG_STM32H7_ADC3_TIMTRIG == 3 +# elif CONFIG_STM32_ADC3_TIMTRIG == 3 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T4CC4 -# elif CONFIG_STM32H7_ADC3_TIMTRIG == 4 +# elif CONFIG_STM32_ADC3_TIMTRIG == 4 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T4TRGO # else -# error "CONFIG_STM32H7_ADC3_TIMTRIG is out of range" +# error "CONFIG_STM32_ADC3_TIMTRIG is out of range" # endif -#elif defined(CONFIG_STM32H7_TIM6_ADC3) -# if CONFIG_STM32H7_ADC3_TIMTRIG == 0 +#elif defined(CONFIG_STM32_TIM6_ADC3) +# if CONFIG_STM32_ADC3_TIMTRIG == 0 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T6CC1 -# elif CONFIG_STM32H7_ADC3_TIMTRIG == 1 +# elif CONFIG_STM32_ADC3_TIMTRIG == 1 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T6CC2 -# elif CONFIG_STM32H7_ADC3_TIMTRIG == 2 +# elif CONFIG_STM32_ADC3_TIMTRIG == 2 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T6CC3 -# elif CONFIG_STM32H7_ADC3_TIMTRIG == 3 +# elif CONFIG_STM32_ADC3_TIMTRIG == 3 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T6CC4 -# elif CONFIG_STM32H7_ADC3_TIMTRIG == 4 +# elif CONFIG_STM32_ADC3_TIMTRIG == 4 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T6TRGO # else -# error "CONFIG_STM32H7_ADC3_TIMTRIG is out of range" +# error "CONFIG_STM32_ADC3_TIMTRIG is out of range" # endif -#elif defined(CONFIG_STM32H7_TIM8_ADC3) -# if CONFIG_STM32H7_ADC3_TIMTRIG == 0 +#elif defined(CONFIG_STM32_TIM8_ADC3) +# if CONFIG_STM32_ADC3_TIMTRIG == 0 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T8CC1 -# elif CONFIG_STM32H7_ADC3_TIMTRIG == 1 +# elif CONFIG_STM32_ADC3_TIMTRIG == 1 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T8CC2 -# elif CONFIG_STM32H7_ADC3_TIMTRIG == 2 +# elif CONFIG_STM32_ADC3_TIMTRIG == 2 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T8CC3 -# elif CONFIG_STM32H7_ADC3_TIMTRIG == 3 +# elif CONFIG_STM32_ADC3_TIMTRIG == 3 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T8CC4 -# elif CONFIG_STM32H7_ADC3_TIMTRIG == 4 +# elif CONFIG_STM32_ADC3_TIMTRIG == 4 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T8TRGO -# elif CONFIG_STM32H7_ADC3_TIMTRIG == 5 +# elif CONFIG_STM32_ADC3_TIMTRIG == 5 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T8TRGO2 # else -# error "CONFIG_STM32H7_ADC3_TIMTRIG is out of range" +# error "CONFIG_STM32_ADC3_TIMTRIG is out of range" # endif -#elif defined(CONFIG_STM32H7_TIM15_ADC3) -# if CONFIG_STM32H7_ADC3_TIMTRIG == 0 +#elif defined(CONFIG_STM32_TIM15_ADC3) +# if CONFIG_STM32_ADC3_TIMTRIG == 0 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T15CC1 -# elif CONFIG_STM32H7_ADC3_TIMTRIG == 1 +# elif CONFIG_STM32_ADC3_TIMTRIG == 1 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T15CC2 -# elif CONFIG_STM32H7_ADC3_TIMTRIG == 2 +# elif CONFIG_STM32_ADC3_TIMTRIG == 2 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T15CC3 -# elif CONFIG_STM32H7_ADC3_TIMTRIG == 3 +# elif CONFIG_STM32_ADC3_TIMTRIG == 3 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T15CC4 -# elif CONFIG_STM32H7_ADC3_TIMTRIG == 4 +# elif CONFIG_STM32_ADC3_TIMTRIG == 4 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T15TRGO # else -# error "CONFIG_STM32H7_ADC3_TIMTRIG is out of range" +# error "CONFIG_STM32_ADC3_TIMTRIG is out of range" # endif #endif @@ -785,7 +785,7 @@ extern "C" #endif /**************************************************************************** - * Name: stm32h7_adc_initialize + * Name: stm32_adc_initialize * * Description: * Initialize the ADC. @@ -801,7 +801,7 @@ extern "C" ****************************************************************************/ struct adc_dev_s; -struct adc_dev_s *stm32h7_adc_initialize(int intf, +struct adc_dev_s *stm32_adc_initialize(int intf, const uint8_t *chanlist, int nchannels); #undef EXTERN @@ -810,5 +810,5 @@ struct adc_dev_s *stm32h7_adc_initialize(int intf, #endif #endif /* __ASSEMBLY__ */ -#endif /* CONFIG_STM32H7_ADC1 || CONFIG_STM32H7_ADC2 || CONFIG_STM32H7_ADC3 */ +#endif /* CONFIG_STM32_ADC1 || CONFIG_STM32_ADC2 || CONFIG_STM32_ADC3 */ #endif /* __ARCH_ARM_SRC_STM32H7_STM32_ADC_H */ diff --git a/arch/arm/src/stm32h7/stm32_aes.h b/arch/arm/src/stm32h7/stm32_aes.h index ad9595d946a50..207bcad7262d7 100644 --- a/arch/arm/src/stm32h7/stm32_aes.h +++ b/arch/arm/src/stm32h7/stm32_aes.h @@ -37,7 +37,7 @@ * variants include CRYP */ -#ifdef CONFIG_STM32H7_HAVE_CRYP +#ifdef CONFIG_STM32_HAVE_CRYP # include "hardware/stm32h7xxxx_cryp.h" #else # error "Unknown chip for AES" diff --git a/arch/arm/src/stm32h7/stm32_allocateheap.c b/arch/arm/src/stm32h7/stm32_allocateheap.c index cec7d503b3ba2..ab77f78604da4 100644 --- a/arch/arm/src/stm32h7/stm32_allocateheap.c +++ b/arch/arm/src/stm32h7/stm32_allocateheap.c @@ -57,7 +57,7 @@ ****************************************************************************/ #if defined(CONFIG_ARCH_CHIP_STM32H7_CORTEXM7) && \ - !defined(CONFIG_STM32H7_CORTEXM4_ENABLED) + !defined(CONFIG_STM32_CORTEXM4_ENABLED) /* Configuration for M7 core when M4 core support disabled */ @@ -84,7 +84,7 @@ * - Tightly Coupled Memory (TCM RAM), we can use Data TCM (DTCM) for system * heap. Note that DTCM has a number of limitations, for example DMA * transfers to/from DTCM are limited. - * Define CONFIG_STM32H7_DTCMEXCLUDE to exclude the DTCM from heap. + * Define CONFIG_STM32_DTCMEXCLUDE to exclude the DTCM from heap. * +1 to CONFIG_MM_REGIONS if you want to use DTCM. * * - External SDRAM can be connected to the FMC peripheral. Initialization @@ -111,18 +111,18 @@ /* Set the start and end of the SRAMs */ # define SRAM_START STM32_AXISRAM_BASE -# define SRAM_END (SRAM_START + STM32H7_SRAM_SIZE) +# define SRAM_END (SRAM_START + STM32_SRAM_SIZE) # define SRAM123_START STM32_SRAM123_BASE -# define SRAM123_END (SRAM123_START + STM32H7_SRAM123_SIZE) +# define SRAM123_END (SRAM123_START + STM32_SRAM123_SIZE) #elif defined(CONFIG_ARCH_CHIP_STM32H7_CORTEXM7) && \ - defined(CONFIG_STM32H7_CORTEXM4_ENABLED) + defined(CONFIG_STM32_CORTEXM4_ENABLED) /* Configuration for M7 core when M4 core support enabled */ # define SRAM_START STM32_AXISRAM_BASE -# define SRAM_END (SRAM_START + STM32H7_SRAM_SIZE) +# define SRAM_END (SRAM_START + STM32_SRAM_SIZE) /* Exclude SRAM123 */ @@ -134,16 +134,16 @@ /* Configuration for M4 core support enabled */ # define SRAM_START STM32_SRAM123_BASE -# define SRAM_END (SRAM_START + STM32H7_SRAM123_SIZE - \ - STM32H7_SRAM3_SIZE) +# define SRAM_END (SRAM_START + STM32_SRAM123_SIZE - \ + STM32_SRAM3_SIZE) #endif #undef HAVE_SRAM4 -#if !defined(CONFIG_STM32H7_SRAM4EXCLUDE) +#if !defined(CONFIG_STM32_SRAM4EXCLUDE) # define HAVE_SRAM4 1 # define SRAM4_START ((uint32_t)(STM32_SRAM4_BASE)) -# define SRAM4_END ((uint32_t)(SRAM4_START + STM32H7_SRAM4_SIZE)) +# define SRAM4_END ((uint32_t)(SRAM4_START + STM32_SRAM4_SIZE)) # define SRAM4_HEAP_START ((uint32_t)_sram4_heap_start) #endif @@ -158,7 +158,7 @@ /* DTCM to be excluded from the main heap. */ -#ifdef CONFIG_STM32H7_DTCMEXCLUDE +#ifdef CONFIG_STM32_DTCMEXCLUDE # undef HAVE_DTCM #endif @@ -410,7 +410,7 @@ void arm_addregion(void) } #endif -#ifdef CONFIG_STM32H7_FMC +#ifdef CONFIG_STM32_FMC stm32_fmc_init(); #endif diff --git a/arch/arm/src/stm32h7/stm32_bbsram.c b/arch/arm/src/stm32h7/stm32_bbsram.c index a4666960d318f..37dc0b741b2ff 100644 --- a/arch/arm/src/stm32h7/stm32_bbsram.c +++ b/arch/arm/src/stm32h7/stm32_bbsram.c @@ -50,14 +50,14 @@ #include "mpu.h" #include "stm32_pwr.h" -#ifdef CONFIG_STM32H7_BBSRAM +#ifdef CONFIG_STM32_BBSRAM /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ -#if !defined(CONFIG_STM32H7_BKPSRAM) -#error Driver Requires CONFIG_STM32H7_BKPSRAM to be enabled +#if !defined(CONFIG_STM32_BKPSRAM) +#error Driver Requires CONFIG_STM32_BKPSRAM to be enabled #endif #define MAX_OPENCNT (255) /* Limit of uint8_t */ @@ -151,7 +151,7 @@ static int stm32_bbsram_unlink(struct inode *inode); ****************************************************************************/ #if defined(CONFIG_BBSRAM_DEBUG) -static uint8_t debug[STM32H7_BBSRAM_SIZE]; +static uint8_t debug[STM32_BBSRAM_SIZE]; #endif static const struct file_operations g_stm32_bbsram_fops = @@ -168,7 +168,7 @@ static const struct file_operations g_stm32_bbsram_fops = #endif }; -static struct stm32_bbsram_s g_bbsram[CONFIG_STM32H7_BBSRAM_FILES]; +static struct stm32_bbsram_s g_bbsram[CONFIG_STM32_BBSRAM_FILES]; /**************************************************************************** * Private Functions @@ -591,7 +591,7 @@ static int stm32_bbsram_ioctl(struct file *filep, int cmd, DEBUGASSERT(inode->i_private); bbr = inode->i_private; - if (cmd == STM32H7_BBSRAM_GETDESC_IOCTL) + if (cmd == STM32_BBSRAM_GETDESC_IOCTL) { struct bbsramd_s *bbrr = (struct bbsramd_s *)((uintptr_t)arg); @@ -688,9 +688,9 @@ static int stm32_bbsram_probe(int *ent, struct stm32_bbsram_s pdev[]) * after reset due to the ECC behavior. */ - avail = STM32H7_BBSRAM_SIZE; + avail = STM32_BBSRAM_SIZE; - for (i = 0; (i < CONFIG_STM32H7_BBSRAM_FILES) && ent[i] && (avail > 0); + for (i = 0; (i < CONFIG_STM32_BBSRAM_FILES) && ent[i] && (avail > 0); i++) { /* Validate the actual allocations against what is in the BBSRAM */ @@ -793,9 +793,9 @@ int stm32_bbsraminitialize(char *devpath, int *sizes) */ # if defined(CONFIG_BUILD_PROTECTED) - mpu_peripheral(STM32_BBSRAM_BASE, STM32H7_BBSRAM_SIZE); + mpu_peripheral(STM32_BBSRAM_BASE, STM32_BBSRAM_SIZE); # else - mpu_user_peripheral(STM32_BBSRAM_BASE, STM32H7_BBSRAM_SIZE); + mpu_user_peripheral(STM32_BBSRAM_BASE, STM32_BBSRAM_SIZE); mpu_control(true, true, true); # endif #endif @@ -855,7 +855,7 @@ int stm32_bbsraminitialize(char *devpath, int *sizes) * ****************************************************************************/ -#if defined(CONFIG_STM32H7_SAVE_CRASHDUMP) +#if defined(CONFIG_STM32_SAVE_CRASHDUMP) int stm32_bbsram_savepanic(int fileno, uint8_t *context, int length) { struct bbsramfh_s *bbf; @@ -873,7 +873,7 @@ int stm32_bbsram_savepanic(int fileno, uint8_t *context, int length) { once = true; - DEBUGASSERT(fileno > 0 && fileno < CONFIG_STM32H7_BBSRAM_FILES); + DEBUGASSERT(fileno > 0 && fileno < CONFIG_STM32_BBSRAM_FILES); bbf = g_bbsram[fileno].bbf; diff --git a/arch/arm/src/stm32h7/stm32_bbsram.h b/arch/arm/src/stm32h7/stm32_bbsram.h index c9d41f73cc23f..23c01b59c8ba8 100644 --- a/arch/arm/src/stm32h7/stm32_bbsram.h +++ b/arch/arm/src/stm32h7/stm32_bbsram.h @@ -25,7 +25,7 @@ /**************************************************************************** * The purpose of this driver is to add battery backup file to the file - * system. There can be CONFIG_STM32H7_BBRSRAM_COUNT files defined. + * system. There can be CONFIG_STM32_BBRSRAM_COUNT files defined. * These files are of fixed size up to the maximum of the backing 4K SRAM. * * If CONFIG_SAVE_CRASHDUMP is defined The driver also supports a feature @@ -46,17 +46,17 @@ * Pre-processor Definitions ****************************************************************************/ -#define STM32H7_BBSRAM_SIZE 4096 +#define STM32_BBSRAM_SIZE 4096 -#if !defined(CONFIG_STM32H7_BBSRAM_FILES) -# define CONFIG_STM32H7_BBSRAM_FILES 4 +#if !defined(CONFIG_STM32_BBSRAM_FILES) +# define CONFIG_STM32_BBSRAM_FILES 4 #endif -/* REVISIT: What guarantees that STM32H7_BBSRAM_GETDESC_IOCTL has a unique +/* REVISIT: What guarantees that STM32_BBSRAM_GETDESC_IOCTL has a unique * value among all over _DIOC() values? */ -#define STM32H7_BBSRAM_GETDESC_IOCTL _DIOC(0x0010) /* Returns a bbsramd_s */ +#define STM32_BBSRAM_GETDESC_IOCTL _DIOC(0x0010) /* Returns a bbsramd_s */ /**************************************************************************** * Public Types @@ -107,8 +107,8 @@ extern "C" * the last entry should be 0 * A size of -1 will use all the remaining spaces * - * If the length of sizes is greater then CONFIG_STM32H7_BBSRAM_FILES - * CONFIG_STM32H7_BBSRAM_FILES will be returned. + * If the length of sizes is greater then CONFIG_STM32_BBSRAM_FILES + * CONFIG_STM32_BBSRAM_FILES will be returned. * * Returned Value: * Number of files created on success; Negated errno on failure. @@ -126,7 +126,7 @@ int stm32_bbsraminitialize(char *devpath, int *sizes); * Saves the panic context in a previously allocated BBSRAM file * * Parameters: -* fileno - the value returned by the ioctl STM32H7_BBSRAM_GETDESC_IOCTL +* fileno - the value returned by the ioctl STM32_BBSRAM_GETDESC_IOCTL * context - Pointer to a any array of bytes to save * length - The length of the data pointed to byt context * @@ -137,7 +137,7 @@ int stm32_bbsraminitialize(char *devpath, int *sizes); * *****************************************************************************/ -#if defined(CONFIG_STM32H7_SAVE_CRASHDUMP) +#if defined(CONFIG_STM32_SAVE_CRASHDUMP) int stm32_bbsram_savepanic(int fileno, uint8_t *context, int length); #endif diff --git a/arch/arm/src/stm32h7/stm32_capture.c b/arch/arm/src/stm32h7/stm32_capture.c index ec1c3e0dfd7d8..32ef41e9d9cac 100644 --- a/arch/arm/src/stm32h7/stm32_capture.c +++ b/arch/arm/src/stm32h7/stm32_capture.c @@ -49,7 +49,7 @@ /* Sanity checks ************************************************************/ -#if !defined(CONFIG_STM32H7_STM32H7X3XX) +#if !defined(CONFIG_STM32_STM32H7X3XX) # warning "This driver is for STM32H7X3XX devices" #endif @@ -59,7 +59,7 @@ * intended for some other purpose. */ -#if defined(CONFIG_STM32H7_TIMX_CAP) +#if defined(CONFIG_STM32_TIMX_CAP) /* Check if any channel is enabled. * This is done to simplify the logic below. @@ -102,25 +102,25 @@ /* Check if we have any advanced timers */ -#if defined(CONFIG_STM32H7_TIM1_CAP) || defined(CONFIG_STM32H7_TIM8_CAP) +#if defined(CONFIG_STM32_TIM1_CAP) || defined(CONFIG_STM32_TIM8_CAP) # define USE_ADVANCED_TIM 1 #endif /* Check if we have any general purpose timers */ -#if defined(CONFIG_STM32H7_TIM2_CAP) || defined(CONFIG_STM32H7_TIM3_CAP) || \ - defined(CONFIG_STM32H7_TIM4_CAP) || defined(CONFIG_STM32H7_TIM5_CAP) || \ - defined(CONFIG_STM32H7_TIM12_CAP) || defined(CONFIG_STM32H7_TIM13_CAP) || \ - defined(CONFIG_STM32H7_TIM14_CAP) || defined(CONFIG_STM32H7_TIM15_CAP) || \ - defined(CONFIG_STM32H7_TIM16_CAP) || defined(CONFIG_STM32H7_TIM17_CAP) +#if defined(CONFIG_STM32_TIM2_CAP) || defined(CONFIG_STM32_TIM3_CAP) || \ + defined(CONFIG_STM32_TIM4_CAP) || defined(CONFIG_STM32_TIM5_CAP) || \ + defined(CONFIG_STM32_TIM12_CAP) || defined(CONFIG_STM32_TIM13_CAP) || \ + defined(CONFIG_STM32_TIM14_CAP) || defined(CONFIG_STM32_TIM15_CAP) || \ + defined(CONFIG_STM32_TIM16_CAP) || defined(CONFIG_STM32_TIM17_CAP) # define USE_GENERAL_TIM 1 #endif /* Check if we have any low-power timers */ -#if defined(CONFIG_STM32H7_LPTIM1_CAP) || defined(CONFIG_STM32H7_LPTIM2_CAP) || \ - defined(CONFIG_STM32H7_LPTIM3_CAP) || defined(CONFIG_STM32H7_LPTIM4_CAP) || \ - defined(CONFIG_STM32H7_LPTIM5_CAP) +#if defined(CONFIG_STM32_LPTIM1_CAP) || defined(CONFIG_STM32_LPTIM2_CAP) || \ + defined(CONFIG_STM32_LPTIM3_CAP) || defined(CONFIG_STM32_LPTIM4_CAP) || \ + defined(CONFIG_STM32_LPTIM5_CAP) # define USE_LOWPOWER_TIM 1 #endif @@ -237,7 +237,7 @@ uint32_t stm32_cap_gpio(const struct stm32_cap_priv_s *priv, switch (priv->base) { -#ifdef CONFIG_STM32H7_TIM1_CAP +#ifdef CONFIG_STM32_TIM1_CAP case STM32_TIM1_BASE: switch (channel) { @@ -265,7 +265,7 @@ uint32_t stm32_cap_gpio(const struct stm32_cap_priv_s *priv, break; #endif -#ifdef CONFIG_STM32H7_TIM2_CAP +#ifdef CONFIG_STM32_TIM2_CAP case STM32_TIM2_BASE: switch (channel) { @@ -293,7 +293,7 @@ uint32_t stm32_cap_gpio(const struct stm32_cap_priv_s *priv, break; #endif -#ifdef CONFIG_STM32H7_TIM3_CAP +#ifdef CONFIG_STM32_TIM3_CAP case STM32_TIM3_BASE: switch (channel) { @@ -321,7 +321,7 @@ uint32_t stm32_cap_gpio(const struct stm32_cap_priv_s *priv, break; #endif -#ifdef CONFIG_STM32H7_TIM4_CAP +#ifdef CONFIG_STM32_TIM4_CAP case STM32_TIM4_BASE: switch (channel) { @@ -349,7 +349,7 @@ uint32_t stm32_cap_gpio(const struct stm32_cap_priv_s *priv, break; #endif -#ifdef CONFIG_STM32H7_TIM5_CAP +#ifdef CONFIG_STM32_TIM5_CAP case STM32_TIM5_BASE: switch (channel) { @@ -379,7 +379,7 @@ uint32_t stm32_cap_gpio(const struct stm32_cap_priv_s *priv, /* TIM6 and TIM7 cannot be used in capture */ -#ifdef CONFIG_STM32H7_TIM8_CAP +#ifdef CONFIG_STM32_TIM8_CAP case STM32_TIM8_BASE: switch (channel) { @@ -407,7 +407,7 @@ uint32_t stm32_cap_gpio(const struct stm32_cap_priv_s *priv, break; #endif -#ifdef CONFIG_STM32H7_TIM9_CAP +#ifdef CONFIG_STM32_TIM9_CAP case STM32_TIM9_BASE: switch (channel) { @@ -435,7 +435,7 @@ uint32_t stm32_cap_gpio(const struct stm32_cap_priv_s *priv, break; #endif -#ifdef CONFIG_STM32H7_TIM10_CAP +#ifdef CONFIG_STM32_TIM10_CAP case STM32_TIM10_BASE: switch (channel) { @@ -463,7 +463,7 @@ uint32_t stm32_cap_gpio(const struct stm32_cap_priv_s *priv, break; #endif -#ifdef CONFIG_STM32H7_TIM11_CAP +#ifdef CONFIG_STM32_TIM11_CAP case STM32_TIM11_BASE: switch (channel) { @@ -491,7 +491,7 @@ uint32_t stm32_cap_gpio(const struct stm32_cap_priv_s *priv, break; #endif -#ifdef CONFIG_STM32H7_TIM12_CAP +#ifdef CONFIG_STM32_TIM12_CAP case STM32_TIM12_BASE: switch (channel) { @@ -519,7 +519,7 @@ uint32_t stm32_cap_gpio(const struct stm32_cap_priv_s *priv, break; #endif -#ifdef CONFIG_STM32H7_TIM13_CAP +#ifdef CONFIG_STM32_TIM13_CAP case STM32_TIM13_BASE: switch (channel) { @@ -547,7 +547,7 @@ uint32_t stm32_cap_gpio(const struct stm32_cap_priv_s *priv, break; #endif -#ifdef CONFIG_STM32H7_TIM14_CAP +#ifdef CONFIG_STM32_TIM14_CAP case STM32_TIM14_BASE: switch (channel) { @@ -589,31 +589,31 @@ static inline int stm32_cap_set_rcc(const struct stm32_cap_priv_s *priv, { /* APB2 Timers */ -#ifdef CONFIG_STM32H7_TIM1_CAP +#ifdef CONFIG_STM32_TIM1_CAP case STM32_TIM1_BASE: offset = STM32_RCC_APB2ENR; mask = RCC_APB2ENR_TIM1EN; break; #endif -#ifdef CONFIG_STM32H7_TIM8_CAP +#ifdef CONFIG_STM32_TIM8_CAP case STM32_TIM8_BASE: offset = STM32_RCC_APB2ENR; mask = RCC_APB2ENR_TIM8EN; break; #endif -#ifdef CONFIG_STM32H7_TIM15_CAP +#ifdef CONFIG_STM32_TIM15_CAP case STM32_TIM15_BASE: offset = STM32_RCC_APB2ENR; mask = RCC_APB2ENR_TIM15EN; break; #endif -#ifdef CONFIG_STM32H7_TIM16_CAP +#ifdef CONFIG_STM32_TIM16_CAP case STM32_TIM16_BASE: offset = STM32_RCC_APB2ENR; mask = RCC_APB2ENR_TIM16EN; break; #endif -#ifdef CONFIG_STM32H7_TIM17_CAP +#ifdef CONFIG_STM32_TIM17_CAP case STM32_TIM17_BASE: offset = STM32_RCC_APB2ENR; mask = RCC_APB2ENR_TIM17EN; @@ -622,50 +622,50 @@ static inline int stm32_cap_set_rcc(const struct stm32_cap_priv_s *priv, /* APB1L Timers */ -#ifdef CONFIG_STM32H7_TIM2_CAP +#ifdef CONFIG_STM32_TIM2_CAP case STM32_TIM2_BASE: offset = STM32_RCC_APB1LENR; mask = RCC_APB1LENR_TIM2EN; break; #endif -#ifdef CONFIG_STM32H7_TIM3_CAP +#ifdef CONFIG_STM32_TIM3_CAP case STM32_TIM3_BASE: offset = STM32_RCC_APB1LENR; mask = RCC_APB1LENR_TIM3EN; break; #endif -#ifdef CONFIG_STM32H7_TIM4_CAP +#ifdef CONFIG_STM32_TIM4_CAP case STM32_TIM4_BASE: offset = STM32_RCC_APB1LENR; mask = RCC_APB1LENR_TIM4EN; break; #endif -#ifdef CONFIG_STM32H7_TIM5_CAP +#ifdef CONFIG_STM32_TIM5_CAP case STM32_TIM5_BASE: offset = STM32_RCC_APB1LENR; mask = RCC_APB1LENR_TIM5EN; break; #endif /* TIM6 and TIM7 cannot be used in capture */ -#ifdef CONFIG_STM32H7_TIM12_CAP +#ifdef CONFIG_STM32_TIM12_CAP case STM32_TIM12_BASE: offset = STM32_RCC_APB1LENR; mask = RCC_APB1LENR_TIM12EN; break; #endif -#ifdef CONFIG_STM32H7_TIM13_CAP +#ifdef CONFIG_STM32_TIM13_CAP case STM32_TIM13_BASE: offset = STM32_RCC_APB1LENR; mask = RCC_APB1LENR_TIM13EN; break; #endif -#ifdef CONFIG_STM32H7_TIM14_CAP +#ifdef CONFIG_STM32_TIM14_CAP case STM32_TIM14_BASE: offset = STM32_RCC_APB1LENR; mask = RCC_APB1LENR_TIM14EN; break; #endif -#ifdef CONFIG_STM32H7_LPTIM1_CAP +#ifdef CONFIG_STM32_LPTIM1_CAP case STM32_LPTIM1_BASE: offset = STM32_RCC_APB1LENR; mask = RCC_APB1LENR_LPTIM1EN; @@ -674,25 +674,25 @@ static inline int stm32_cap_set_rcc(const struct stm32_cap_priv_s *priv, /* APB4 Timers */ -#ifdef CONFIG_STM32H7_LPTIM2_CAP +#ifdef CONFIG_STM32_LPTIM2_CAP case STM32_LPTIM2_BASE: offset = STM32_RCC_APB4ENR; mask = RCC_APB4ENR_LPTIM2EN; break; #endif -#ifdef CONFIG_STM32H7_LPTIM3_CAP +#ifdef CONFIG_STM32_LPTIM3_CAP case STM32_LPTIM3_BASE: offset = STM32_RCC_APB4ENR; mask = RCC_APB4ENR_LPTIM3EN; break; #endif -#ifdef CONFIG_STM32H7_LPTIM4_CAP +#ifdef CONFIG_STM32_LPTIM4_CAP case STM32_LPTIM4_BASE: offset = STM32_RCC_APB4ENR; mask = RCC_APB4ENR_LPTIM4EN; break; #endif -#ifdef CONFIG_STM32H7_LPTIM5_CAP +#ifdef CONFIG_STM32_LPTIM5_CAP case STM32_LPTIM5_BASE: offset = STM32_RCC_APB4ENR; mask = RCC_APB4ENR_LPTIM5EN; @@ -744,62 +744,62 @@ static int stm32_cap_setclock(struct stm32_cap_dev_s *dev, switch (priv->base) { -#ifdef CONFIG_STM32H7_TIM1 +#ifdef CONFIG_STM32_TIM1 case STM32_TIM1_BASE: freqin = STM32_APB2_TIM1_CLKIN; break; #endif -#ifdef CONFIG_STM32H7_TIM2 +#ifdef CONFIG_STM32_TIM2 case STM32_TIM2_BASE: freqin = STM32_APB1_TIM2_CLKIN; break; #endif -#ifdef CONFIG_STM32H7_TIM3 +#ifdef CONFIG_STM32_TIM3 case STM32_TIM3_BASE: freqin = STM32_APB1_TIM3_CLKIN; break; #endif -#ifdef CONFIG_STM32H7_TIM4 +#ifdef CONFIG_STM32_TIM4 case STM32_TIM4_BASE: freqin = STM32_APB1_TIM4_CLKIN; break; #endif -#ifdef CONFIG_STM32H7_TIM5 +#ifdef CONFIG_STM32_TIM5 case STM32_TIM5_BASE: freqin = STM32_APB1_TIM5_CLKIN; break; #endif -#ifdef CONFIG_STM32H7_TIM8 +#ifdef CONFIG_STM32_TIM8 case STM32_TIM8_BASE: freqin = STM32_APB2_TIM8_CLKIN; break; #endif -#ifdef CONFIG_STM32H7_TIM9 +#ifdef CONFIG_STM32_TIM9 case STM32_TIM9_BASE: freqin = STM32_APB2_TIM9_CLKIN; break; #endif -#ifdef CONFIG_STM32H7_TIM10 +#ifdef CONFIG_STM32_TIM10 case STM32_TIM10_BASE: freqin = STM32_APB2_TIM10_CLKIN; break; #endif -#ifdef CONFIG_STM32H7_TIM11 +#ifdef CONFIG_STM32_TIM11 case STM32_TIM11_BASE: freqin = STM32_APB2_TIM11_CLKIN; break; #endif -#ifdef CONFIG_STM32H7_TIM12 +#ifdef CONFIG_STM32_TIM12 case STM32_TIM12_BASE: freqin = STM32_APB1_TIM12_CLKIN; break; #endif -#ifdef CONFIG_STM32H7_TIM13 +#ifdef CONFIG_STM32_TIM13 case STM32_TIM13_BASE: freqin = STM32_APB1_TIM13_CLKIN; break; #endif -#ifdef CONFIG_STM32H7_TIM14 +#ifdef CONFIG_STM32_TIM14 case STM32_TIM14_BASE: freqin = STM32_APB1_TIM14_CLKIN; break; @@ -1350,7 +1350,7 @@ struct stm32_cap_ops_s stm32_cap_ops = .getflags = &stm32_cap_getflags }; -#ifdef CONFIG_STM32H7_TIM1_CAP +#ifdef CONFIG_STM32_TIM1_CAP const struct stm32_cap_priv_s stm32_tim1_priv = { .ops = &stm32_cap_ops, @@ -1362,7 +1362,7 @@ const struct stm32_cap_priv_s stm32_tim1_priv = }; #endif -#ifdef CONFIG_STM32H7_TIM2_CAP +#ifdef CONFIG_STM32_TIM2_CAP const struct stm32_cap_priv_s stm32_tim2_priv = { .ops = &stm32_cap_ops, @@ -1374,7 +1374,7 @@ const struct stm32_cap_priv_s stm32_tim2_priv = }; #endif -#ifdef CONFIG_STM32H7_TIM3_CAP +#ifdef CONFIG_STM32_TIM3_CAP const struct stm32_cap_priv_s stm32_tim3_priv = { .ops = &stm32_cap_ops, @@ -1386,7 +1386,7 @@ const struct stm32_cap_priv_s stm32_tim3_priv = }; #endif -#ifdef CONFIG_STM32H7_TIM4_CAP +#ifdef CONFIG_STM32_TIM4_CAP const struct stm32_cap_priv_s stm32_tim4_priv = { .ops = &stm32_cap_ops, @@ -1398,7 +1398,7 @@ const struct stm32_cap_priv_s stm32_tim4_priv = }; #endif -#ifdef CONFIG_STM32H7_TIM5_CAP +#ifdef CONFIG_STM32_TIM5_CAP const struct stm32_cap_priv_s stm32_tim5_priv = { .ops = &stm32_cap_ops, @@ -1412,7 +1412,7 @@ const struct stm32_cap_priv_s stm32_tim5_priv = /* TIM6 and TIM7 cannot be used in capture */ -#ifdef CONFIG_STM32H7_TIM8_CAP +#ifdef CONFIG_STM32_TIM8_CAP const struct stm32_cap_priv_s stm32_tim8_priv = { .ops = &stm32_cap_ops, @@ -1424,7 +1424,7 @@ const struct stm32_cap_priv_s stm32_tim8_priv = }; #endif -#ifdef CONFIG_STM32H7_TIM9_CAP +#ifdef CONFIG_STM32_TIM9_CAP const struct stm32_cap_priv_s stm32_tim9_priv = { .ops = &stm32_cap_ops, @@ -1436,7 +1436,7 @@ const struct stm32_cap_priv_s stm32_tim9_priv = }; #endif -#ifdef CONFIG_STM32H7_TIM10_CAP +#ifdef CONFIG_STM32_TIM10_CAP const struct stm32_cap_priv_s stm32_tim10_priv = { .ops = &stm32_cap_ops, @@ -1448,7 +1448,7 @@ const struct stm32_cap_priv_s stm32_tim10_priv = }; #endif -#ifdef CONFIG_STM32H7_TIM11_CAP +#ifdef CONFIG_STM32_TIM11_CAP const struct stm32_cap_priv_s stm32_tim11_priv = { .ops = &stm32_cap_ops, @@ -1460,7 +1460,7 @@ const struct stm32_cap_priv_s stm32_tim11_priv = }; #endif -#ifdef CONFIG_STM32H7_TIM12_CAP +#ifdef CONFIG_STM32_TIM12_CAP const struct stm32_cap_priv_s stm32_tim12_priv = { .ops = &stm32_cap_ops, @@ -1472,7 +1472,7 @@ const struct stm32_cap_priv_s stm32_tim12_priv = }; #endif -#ifdef CONFIG_STM32H7_TIM13_CAP +#ifdef CONFIG_STM32_TIM13_CAP const struct stm32_cap_priv_s stm32_tim13_priv = { .ops = &stm32_cap_ops, @@ -1484,7 +1484,7 @@ const struct stm32_cap_priv_s stm32_tim13_priv = }; #endif -#ifdef CONFIG_STM32H7_TIM14_CAP +#ifdef CONFIG_STM32_TIM14_CAP const struct stm32_cap_priv_s stm32_tim14_priv = { .ops = &stm32_cap_ops, @@ -1496,7 +1496,7 @@ const struct stm32_cap_priv_s stm32_tim14_priv = }; #endif -#ifdef CONFIG_STM32H7_TIM15_CAP +#ifdef CONFIG_STM32_TIM15_CAP static const struct stm32_cap_priv_s stm32_tim15_priv = { .ops = &stm32_cap_ops, @@ -1508,7 +1508,7 @@ static const struct stm32_cap_priv_s stm32_tim15_priv = }; #endif -#ifdef CONFIG_STM32H7_TIM16_CAP +#ifdef CONFIG_STM32_TIM16_CAP static const struct stm32_cap_priv_s stm32_tim16_priv = { .ops = &stm32_cap_ops, @@ -1520,7 +1520,7 @@ static const struct stm32_cap_priv_s stm32_tim16_priv = }; #endif -#ifdef CONFIG_STM32H7_TIM17_CAP +#ifdef CONFIG_STM32_TIM17_CAP static const struct stm32_cap_priv_s stm32_tim17_priv = { .ops = &stm32_cap_ops, @@ -1536,54 +1536,54 @@ static inline const struct stm32_cap_priv_s * stm32_cap_get_priv(int timer) { switch (timer) { -#ifdef CONFIG_STM32H7_TIM1_CAP +#ifdef CONFIG_STM32_TIM1_CAP case 1: return &stm32_tim1_priv; #endif -#ifdef CONFIG_STM32H7_TIM2_CAP +#ifdef CONFIG_STM32_TIM2_CAP case 2: return &stm32_tim2_priv; #endif -#ifdef CONFIG_STM32H7_TIM3_CAP +#ifdef CONFIG_STM32_TIM3_CAP case 3: return &stm32_tim3_priv; #endif -#ifdef CONFIG_STM32H7_TIM4_CAP +#ifdef CONFIG_STM32_TIM4_CAP case 4: return &stm32_tim4_priv; #endif -#ifdef CONFIG_STM32H7_TIM5_CAP +#ifdef CONFIG_STM32_TIM5_CAP case 5: return &stm32_tim5_priv; #endif /* TIM6 and TIM7 cannot be used in capture */ -#ifdef CONFIG_STM32H7_TIM8_CAP +#ifdef CONFIG_STM32_TIM8_CAP case 8: return &stm32_tim8_priv; #endif -#ifdef CONFIG_STM32H7_TIM9_CAP +#ifdef CONFIG_STM32_TIM9_CAP case 9: return &stm32_tim9_priv; #endif -#ifdef CONFIG_STM32H7_TIM10_CAP +#ifdef CONFIG_STM32_TIM10_CAP case 10: return &stm32_tim10_priv; #endif -#ifdef CONFIG_STM32H7_TIM11_CAP +#ifdef CONFIG_STM32_TIM11_CAP case 11: return &stm32_tim11_priv; #endif -#ifdef CONFIG_STM32H7_TIM12_CAP +#ifdef CONFIG_STM32_TIM12_CAP case 12: return &stm32_tim12_priv; #endif -#ifdef CONFIG_STM32H7_TIM13_CAP +#ifdef CONFIG_STM32_TIM13_CAP case 13: return &stm32_tim13_priv; #endif -#ifdef CONFIG_STM32H7_TIM14_CAP +#ifdef CONFIG_STM32_TIM14_CAP case 14: return &stm32_tim14_priv; #endif @@ -1640,4 +1640,4 @@ int stm32_cap_deinit(struct stm32_cap_dev_s * dev) return OK; } -#endif /* defined(CONFIG_STM32H7_TIM1 || ... || TIM14) */ +#endif /* defined(CONFIG_STM32_TIM1 || ... || TIM14) */ diff --git a/arch/arm/src/stm32h7/stm32_capture_lowerhalf.c b/arch/arm/src/stm32h7/stm32_capture_lowerhalf.c index 6bdf846cfb081..79ee35e30224e 100644 --- a/arch/arm/src/stm32h7/stm32_capture_lowerhalf.c +++ b/arch/arm/src/stm32h7/stm32_capture_lowerhalf.c @@ -47,35 +47,35 @@ /* 32-Bit Timers ************************************************************/ -#define STM32H7_TIM2_RES 32 -#define STM32H7_TIM5_RES 32 +#define STM32_TIM2_RES 32 +#define STM32_TIM5_RES 32 /* 16-Bit Timers ************************************************************/ /* Advanced-Control Timers */ -#define STM32H7_TIM1_RES 16 -#define STM32H7_TIM8_RES 16 +#define STM32_TIM1_RES 16 +#define STM32_TIM8_RES 16 /* General-Purpose Timers */ -#define STM32H7_TIM3_RES 16 -#define STM32H7_TIM4_RES 16 -#define STM32H7_TIM12_RES 16 -#define STM32H7_TIM13_RES 16 -#define STM32H7_TIM14_RES 16 -#define STM32H7_TIM15_RES 16 -#define STM32H7_TIM16_RES 16 -#define STM32H7_TIM17_RES 16 +#define STM32_TIM3_RES 16 +#define STM32_TIM4_RES 16 +#define STM32_TIM12_RES 16 +#define STM32_TIM13_RES 16 +#define STM32_TIM14_RES 16 +#define STM32_TIM15_RES 16 +#define STM32_TIM16_RES 16 +#define STM32_TIM17_RES 16 /* Basic Timers */ -#define STM32H7_TIM6_RES 16 -#define STM32H7_TIM7_RES 16 +#define STM32_TIM6_RES 16 +#define STM32_TIM7_RES 16 /* Low-Power Timers */ -#define STM32H7_LPTIM1_RES 16 -#define STM32H7_LPTIM2_RES 16 -#define STM32H7_LPTIM3_RES 16 -#define STM32H7_LPTIM4_RES 16 -#define STM32H7_LPTIM5_RES 16 +#define STM32_LPTIM1_RES 16 +#define STM32_LPTIM2_RES 16 +#define STM32_LPTIM3_RES 16 +#define STM32_LPTIM4_RES 16 +#define STM32_LPTIM5_RES 16 /**************************************************************************** * Private Types @@ -125,123 +125,123 @@ static const struct cap_ops_s g_cap_ops = .getfreq = stm32_getfreq, }; -#ifdef CONFIG_STM32H7_TIM1_CAP +#ifdef CONFIG_STM32_TIM1_CAP static struct stm32_lowerhalf_s g_cap1_lowerhalf = { .ops = &g_cap_ops, - .resolution = STM32H7_TIM1_RES, - .channel = CONFIG_STM32H7_TIM1_CHANNEL, - .clock = CONFIG_STM32H7_TIM1_CLOCK, + .resolution = STM32_TIM1_RES, + .channel = CONFIG_STM32_TIM1_CHANNEL, + .clock = CONFIG_STM32_TIM1_CLOCK, }; #endif -#ifdef CONFIG_STM32H7_TIM2_CAP +#ifdef CONFIG_STM32_TIM2_CAP static struct stm32_lowerhalf_s g_cap2_lowerhalf = { .ops = &g_cap_ops, - .resolution = STM32H7_TIM2_RES, - .channel = CONFIG_STM32H7_TIM2_CHANNEL, - .clock = CONFIG_STM32H7_TIM2_CLOCK, + .resolution = STM32_TIM2_RES, + .channel = CONFIG_STM32_TIM2_CHANNEL, + .clock = CONFIG_STM32_TIM2_CLOCK, }; #endif -#ifdef CONFIG_STM32H7_TIM3_CAP +#ifdef CONFIG_STM32_TIM3_CAP static struct stm32_lowerhalf_s g_cap3_lowerhalf = { .ops = &g_cap_ops, - .resolution = STM32H7_TIM3_RES, - .channel = CONFIG_STM32H7_TIM3_CHANNEL, - .clock = CONFIG_STM32H7_TIM3_CLOCK, + .resolution = STM32_TIM3_RES, + .channel = CONFIG_STM32_TIM3_CHANNEL, + .clock = CONFIG_STM32_TIM3_CLOCK, }; #endif -#ifdef CONFIG_STM32H7_TIM4_CAP +#ifdef CONFIG_STM32_TIM4_CAP static struct stm32_lowerhalf_s g_cap4_lowerhalf = { .ops = &g_cap_ops, - .resolution = STM32H7_TIM4_RES, - .channel = CONFIG_STM32H7_TIM4_CHANNEL, - .clock = CONFIG_STM32H7_TIM4_CLOCK, + .resolution = STM32_TIM4_RES, + .channel = CONFIG_STM32_TIM4_CHANNEL, + .clock = CONFIG_STM32_TIM4_CLOCK, }; #endif -#ifdef CONFIG_STM32H7_TIM5_CAP +#ifdef CONFIG_STM32_TIM5_CAP static struct stm32_lowerhalf_s g_cap5_lowerhalf = { .ops = &g_cap_ops, - .resolution = STM32H7_TIM5_RES, - .channel = CONFIG_STM32H7_TIM5_CHANNEL, - .clock = CONFIG_STM32H7_TIM5_CLOCK, + .resolution = STM32_TIM5_RES, + .channel = CONFIG_STM32_TIM5_CHANNEL, + .clock = CONFIG_STM32_TIM5_CLOCK, }; #endif -#ifdef CONFIG_STM32H7_TIM8_CAP +#ifdef CONFIG_STM32_TIM8_CAP static struct stm32_lowerhalf_s g_cap8_lowerhalf = { .ops = &g_cap_ops, - .resolution = STM32H7_TIM8_RES, - .channel = CONFIG_STM32H7_TIM8_CHANNEL, - .clock = CONFIG_STM32H7_TIM8_CLOCK, + .resolution = STM32_TIM8_RES, + .channel = CONFIG_STM32_TIM8_CHANNEL, + .clock = CONFIG_STM32_TIM8_CLOCK, }; #endif -#ifdef CONFIG_STM32H7_TIM12_CAP +#ifdef CONFIG_STM32_TIM12_CAP static struct stm32_lowerhalf_s g_cap12_lowerhalf = { .ops = &g_cap_ops, - .resolution = STM32H7_TIM12_RES, - .channel = CONFIG_STM32H7_TIM12_CHANNEL, - .clock = CONFIG_STM32H7_TIM12_CLOCK, + .resolution = STM32_TIM12_RES, + .channel = CONFIG_STM32_TIM12_CHANNEL, + .clock = CONFIG_STM32_TIM12_CLOCK, }; #endif -#ifdef CONFIG_STM32H7_TIM13_CAP +#ifdef CONFIG_STM32_TIM13_CAP static struct stm32_lowerhalf_s g_cap13_lowerhalf = { .ops = &g_cap_ops, - .resolution = STM32H7_TIM13_RES, - .channel = CONFIG_STM32H7_TIM13_CHANNEL, - .clock = CONFIG_STM32H7_TIM13_CLOCK, + .resolution = STM32_TIM13_RES, + .channel = CONFIG_STM32_TIM13_CHANNEL, + .clock = CONFIG_STM32_TIM13_CLOCK, }; #endif -#ifdef CONFIG_STM32H7_TIM14_CAP +#ifdef CONFIG_STM32_TIM14_CAP static struct stm32_lowerhalf_s g_cap14_lowerhalf = { .ops = &g_cap_ops, - .resolution = STM32H7_TIM14_RES, - .channel = CONFIG_STM32H7_TIM14_CHANNEL, - .clock = CONFIG_STM32H7_TIM14_CLOCK, + .resolution = STM32_TIM14_RES, + .channel = CONFIG_STM32_TIM14_CHANNEL, + .clock = CONFIG_STM32_TIM14_CLOCK, }; #endif -#ifdef CONFIG_STM32H7_TIM15_CAP +#ifdef CONFIG_STM32_TIM15_CAP static struct stm32_lowerhalf_s g_cap15_lowerhalf = { .ops = &g_cap_ops, - .resolution = STM32H7_TIM15_RES, - .channel = CONFIG_STM32H7_TIM15_CHANNEL, - .clock = CONFIG_STM32H7_TIM15_CLOCK, + .resolution = STM32_TIM15_RES, + .channel = CONFIG_STM32_TIM15_CHANNEL, + .clock = CONFIG_STM32_TIM15_CLOCK, }; #endif -#ifdef CONFIG_STM32H7_TIM16_CAP +#ifdef CONFIG_STM32_TIM16_CAP static struct stm32_lowerhalf_s g_cap16_lowerhalf = { .ops = &g_cap_ops, - .resolution = STM32H7_TIM16_RES, - .channel = CONFIG_STM32H7_TIM16_CHANNEL, - .clock = CONFIG_STM32H7_TIM16_CLOCK, + .resolution = STM32_TIM16_RES, + .channel = CONFIG_STM32_TIM16_CHANNEL, + .clock = CONFIG_STM32_TIM16_CLOCK, }; #endif -#ifdef CONFIG_STM32H7_TIM17_CAP +#ifdef CONFIG_STM32_TIM17_CAP static struct stm32_lowerhalf_s g_cap17_lowerhalf = { .ops = &g_cap_ops, - .resolution = STM32H7_TIM17_RES, - .channel = CONFIG_STM32H7_TIM17_CHANNEL, - .clock = CONFIG_STM32H7_TIM17_CLOCK, + .resolution = STM32_TIM17_RES, + .channel = CONFIG_STM32_TIM17_CHANNEL, + .clock = CONFIG_STM32_TIM17_CLOCK, }; #endif @@ -504,62 +504,62 @@ struct cap_lowerhalf_s *stm32_cap_initialize(int timer) switch (timer) { -#ifdef CONFIG_STM32H7_TIM1_CAP +#ifdef CONFIG_STM32_TIM1_CAP case 1: lower = &g_cap1_lowerhalf; break; #endif -#ifdef CONFIG_STM32H7_TIM2_CAP +#ifdef CONFIG_STM32_TIM2_CAP case 2: lower = &g_cap2_lowerhalf; break; #endif -#ifdef CONFIG_STM32H7_TIM3_CAP +#ifdef CONFIG_STM32_TIM3_CAP case 3: lower = &g_cap3_lowerhalf; break; #endif -#ifdef CONFIG_STM32H7_TIM4_CAP +#ifdef CONFIG_STM32_TIM4_CAP case 4: lower = &g_cap4_lowerhalf; break; #endif -#ifdef CONFIG_STM32H7_TIM5_CAP +#ifdef CONFIG_STM32_TIM5_CAP case 5: lower = &g_cap5_lowerhalf; break; #endif -#ifdef CONFIG_STM32H7_TIM8_CAP +#ifdef CONFIG_STM32_TIM8_CAP case 8: lower = &g_cap8_lowerhalf; break; #endif -#ifdef CONFIG_STM32H7_TIM12_CAP +#ifdef CONFIG_STM32_TIM12_CAP case 12: lower = &g_cap12_lowerhalf; break; #endif -#ifdef CONFIG_STM32H7_TIM13_CAP +#ifdef CONFIG_STM32_TIM13_CAP case 13: lower = &g_cap13_lowerhalf; break; #endif -#ifdef CONFIG_STM32H7_TIM14_CAP +#ifdef CONFIG_STM32_TIM14_CAP case 14: lower = &g_cap14_lowerhalf; break; #endif -#ifdef CONFIG_STM32H7_TIM15_CAP +#ifdef CONFIG_STM32_TIM15_CAP case 15: lower = &g_cap15_lowerhalf; break; #endif -#ifdef CONFIG_STM32H7_TIM16_CAP +#ifdef CONFIG_STM32_TIM16_CAP case 16: lower = &g_cap16_lowerhalf; break; #endif -#ifdef CONFIG_STM32H7_TIM17_CAP +#ifdef CONFIG_STM32_TIM17_CAP case 17: lower = &g_cap17_lowerhalf; break; diff --git a/arch/arm/src/stm32h7/stm32_dma.c b/arch/arm/src/stm32h7/stm32_dma.c index adbecb87cea63..5ea0a3f87e783 100644 --- a/arch/arm/src/stm32h7/stm32_dma.c +++ b/arch/arm/src/stm32h7/stm32_dma.c @@ -51,22 +51,22 @@ #define DMAMUX_NUM 2 #define DMA_CONTROLLERS 4 -#ifdef CONFIG_STM32H7_MDMA +#ifdef CONFIG_STM32_MDMA # define MDMA_NCHAN 16 #else # define MDMA_NCHAN 0 #endif -#ifdef CONFIG_STM32H7_DMA1 +#ifdef CONFIG_STM32_DMA1 # define DMA1_NSTREAMS 8 #else # define DMA1_NSTREAMS 0 #endif -#ifdef CONFIG_STM32H7_DMA2 +#ifdef CONFIG_STM32_DMA2 # define DMA2_NSTREAMS 8 #else # define DMA2_NSTREAMS 0 #endif -#ifdef CONFIG_STM32H7_BDMA +#ifdef CONFIG_STM32_BDMA # define BDMA_NCHAN 8 #else # define BDMA_NCHAN 0 @@ -185,7 +185,7 @@ struct stm32_dma_ops_s * Private Functions ****************************************************************************/ -#ifdef CONFIG_STM32H7_MDMA +#ifdef CONFIG_STM32_MDMA static void stm32_mdma_disable(DMA_CHANNEL dmachan); static int stm32_mdma_interrupt(int irq, void *context, void *arg); static void stm32_mdma_setup(DMA_HANDLE handle, stm32_dmacfg_t *cfg); @@ -193,7 +193,7 @@ static void stm32_mdma_free(DMA_HANDLE handle); static void stm32_mdma_start(DMA_HANDLE handle, dma_callback_t callback, void *arg, bool half); static size_t stm32_mdma_residual(DMA_HANDLE handle); -#ifdef CONFIG_STM32H7_DMACAPABLE +#ifdef CONFIG_STM32_DMACAPABLE static bool stm32_mdma_capable(stm32_dmacfg_t *cfg); #endif #ifdef CONFIG_DEBUG_DMA_INFO @@ -201,7 +201,7 @@ static void stm32_mdma_dump(DMA_HANDLE handle, const char *msg); #endif #endif -#if defined(CONFIG_STM32H7_DMA1) || defined(CONFIG_STM32H7_DMA2) +#if defined(CONFIG_STM32_DMA1) || defined(CONFIG_STM32_DMA2) static void stm32_sdma_disable(DMA_CHANNEL dmachan); static int stm32_sdma_interrupt(int irq, void *context, void *arg); static void stm32_sdma_setup(DMA_HANDLE handle, stm32_dmacfg_t *cfg); @@ -209,7 +209,7 @@ static void stm32_sdma_free(DMA_HANDLE handle); static void stm32_sdma_start(DMA_HANDLE handle, dma_callback_t callback, void *arg, bool half); static size_t stm32_sdma_residual(DMA_HANDLE handle); -#ifdef CONFIG_STM32H7_DMACAPABLE +#ifdef CONFIG_STM32_DMACAPABLE static bool stm32_sdma_capable(stm32_dmacfg_t *cfg); #endif #ifdef CONFIG_DEBUG_DMA_INFO @@ -217,7 +217,7 @@ static void stm32_sdma_dump(DMA_HANDLE handle, const char *msg); #endif #endif -#ifdef CONFIG_STM32H7_BDMA +#ifdef CONFIG_STM32_BDMA static void stm32_bdma_disable(DMA_CHANNEL dmachan); static int stm32_bdma_interrupt(int irq, void *context, void *arg); static void stm32_bdma_setup(DMA_HANDLE handle, stm32_dmacfg_t *cfg); @@ -225,7 +225,7 @@ static void stm32_bdma_free(DMA_HANDLE handle); static void stm32_bdma_start(DMA_HANDLE handle, dma_callback_t callback, void *arg, bool half); static size_t stm32_bdma_residual(DMA_HANDLE handle); -#ifdef CONFIG_STM32H7_DMACAPABLE +#ifdef CONFIG_STM32_DMACAPABLE static bool stm32_bdma_capable(stm32_dmacfg_t *cfg); #endif #ifdef CONFIG_DEBUG_DMA_INFO @@ -265,7 +265,7 @@ static inline void dmachan_modifyreg32(DMA_CHANNEL dmachan, struct stm32_dma_ops_s g_dma_ops[DMA_CONTROLLERS] = { -#ifdef CONFIG_STM32H7_MDMA +#ifdef CONFIG_STM32_MDMA /* 0 - MDMA */ { @@ -275,7 +275,7 @@ struct stm32_dma_ops_s g_dma_ops[DMA_CONTROLLERS] = .dma_free = stm32_mdma_free, .dma_start = stm32_mdma_start, .dma_residual = stm32_mdma_residual, -#ifdef CONFIG_STM32H7_DMACAPABLE +#ifdef CONFIG_STM32_DMACAPABLE .dma_capable = stm32_mdma_capable, #endif #ifdef CONFIG_DEBUG_DMA_INFO @@ -288,7 +288,7 @@ struct stm32_dma_ops_s g_dma_ops[DMA_CONTROLLERS] = }, #endif -#ifdef CONFIG_STM32H7_DMA1 +#ifdef CONFIG_STM32_DMA1 /* 1 - DMA1 */ { @@ -298,7 +298,7 @@ struct stm32_dma_ops_s g_dma_ops[DMA_CONTROLLERS] = .dma_free = stm32_sdma_free, .dma_start = stm32_sdma_start, .dma_residual = stm32_sdma_residual, -#ifdef CONFIG_STM32H7_DMACAPABLE +#ifdef CONFIG_STM32_DMACAPABLE .dma_capable = stm32_sdma_capable, #endif #ifdef CONFIG_DEBUG_DMA_INFO @@ -311,7 +311,7 @@ struct stm32_dma_ops_s g_dma_ops[DMA_CONTROLLERS] = }, #endif -#ifdef CONFIG_STM32H7_DMA2 +#ifdef CONFIG_STM32_DMA2 /* 2 - DMA2 */ { @@ -321,7 +321,7 @@ struct stm32_dma_ops_s g_dma_ops[DMA_CONTROLLERS] = .dma_free = stm32_sdma_free, .dma_start = stm32_sdma_start, .dma_residual = stm32_sdma_residual, -#ifdef CONFIG_STM32H7_DMACAPABLE +#ifdef CONFIG_STM32_DMACAPABLE .dma_capable = stm32_sdma_capable, #endif #ifdef CONFIG_DEBUG_DMA_INFO @@ -334,7 +334,7 @@ struct stm32_dma_ops_s g_dma_ops[DMA_CONTROLLERS] = }, #endif -#ifdef CONFIG_STM32H7_BDMA +#ifdef CONFIG_STM32_BDMA /* 3 - BDMA */ { @@ -344,7 +344,7 @@ struct stm32_dma_ops_s g_dma_ops[DMA_CONTROLLERS] = .dma_free = stm32_bdma_free, .dma_start = stm32_bdma_start, .dma_residual = stm32_bdma_residual, -#ifdef CONFIG_STM32H7_DMACAPABLE +#ifdef CONFIG_STM32_DMACAPABLE .dma_capable = stm32_bdma_capable, #endif #ifdef CONFIG_DEBUG_DMA_INFO @@ -427,7 +427,7 @@ struct stm32_dma_s g_dma[DMA_NCHANNELS] = static struct stm32_dmach_s g_dmach[DMA_NCHANNELS] = { -#ifdef CONFIG_STM32H7_MDMA +#ifdef CONFIG_STM32_MDMA /* MDMA */ { @@ -559,7 +559,7 @@ static struct stm32_dmach_s g_dmach[DMA_NCHANNELS] = }, #endif -#ifdef CONFIG_STM32H7_DMA1 +#ifdef CONFIG_STM32_DMA1 /* DMA1 */ { @@ -627,7 +627,7 @@ static struct stm32_dmach_s g_dmach[DMA_NCHANNELS] = }, #endif -#ifdef CONFIG_STM32H7_DMA2 +#ifdef CONFIG_STM32_DMA2 /* DMA2 */ { @@ -695,7 +695,7 @@ static struct stm32_dmach_s g_dmach[DMA_NCHANNELS] = }, #endif -#ifdef CONFIG_STM32H7_BDMA +#ifdef CONFIG_STM32_BDMA /* BDMA */ { @@ -920,7 +920,7 @@ static void stm32_gdma_limits_get(uint8_t controller, uint8_t *first, * Master DMA functions ****************************************************************************/ -#ifdef CONFIG_STM32H7_MDMA +#ifdef CONFIG_STM32_MDMA /**************************************************************************** * Name: stm32_mdma_disable @@ -1028,7 +1028,7 @@ static size_t stm32_mdma_residual(DMA_HANDLE handle) * Name: stm32_mdma_capable ****************************************************************************/ -#ifdef CONFIG_STM32H7_DMACAPABLE +#ifdef CONFIG_STM32_DMACAPABLE static bool stm32_mdma_capable(stm32_dmacfg_t *cfg) { uint32_t transfer_size; @@ -1084,13 +1084,13 @@ static void stm32_mdma_dump(DMA_HANDLE handle, const char *msg) } #endif -#endif /* CONFIG_STM32H7_MDMA */ +#endif /* CONFIG_STM32_MDMA */ /**************************************************************************** * Standard DMA functions ****************************************************************************/ -#if defined(CONFIG_STM32H7_DMA1) || defined(CONFIG_STM32H7_DMA2) +#if defined(CONFIG_STM32_DMA1) || defined(CONFIG_STM32_DMA2) /**************************************************************************** * Name: stm32_sdma_disable @@ -1158,7 +1158,7 @@ static int stm32_sdma_interrupt(int irq, void *context, void *arg) /* Get the stream and the controller that generated the interrupt */ -#ifdef CONFIG_STM32H7_DMA1 +#ifdef CONFIG_STM32_DMA1 if (irq >= STM32_IRQ_DMA1S0 && irq <= STM32_IRQ_DMA1S6) { stream = irq - STM32_IRQ_DMA1S0; @@ -1171,7 +1171,7 @@ static int stm32_sdma_interrupt(int irq, void *context, void *arg) } else #endif -#ifdef CONFIG_STM32H7_DMA2 +#ifdef CONFIG_STM32_DMA2 if (irq >= STM32_IRQ_DMA2S0 && irq <= STM32_IRQ_DMA2S4) { stream = irq - STM32_IRQ_DMA2S0; @@ -1258,7 +1258,7 @@ static void stm32_sdma_setup(DMA_HANDLE handle, stm32_dmacfg_t *cfg) "scr: %08" PRIx32 "\n", cfg->paddr, cfg->maddr, cfg->ndata, cfg->cfg1); -#ifdef CONFIG_STM32H7_DMACAPABLE +#ifdef CONFIG_STM32_DMACAPABLE DEBUGASSERT(stm32_sdma_capable(cfg)); #endif @@ -1530,7 +1530,7 @@ static size_t stm32_sdma_residual(DMA_HANDLE handle) * Name: stm32_sdma_capable ****************************************************************************/ -#ifdef CONFIG_STM32H7_DMACAPABLE +#ifdef CONFIG_STM32_DMACAPABLE static bool stm32_sdma_capable(stm32_dmacfg_t *cfg) { uint32_t transfer_size; @@ -1604,7 +1604,7 @@ static bool stm32_sdma_capable(stm32_dmacfg_t *cfg) dmainfo("stm32_dmacapable: dcache unaligned " "maddr:0x%08" PRIx32 " mend:0x%08" PRIx32 "\n", cfg->maddr, mend); -#if !defined(CONFIG_STM32H7_DMACAPABLE_ASSUME_CACHE_ALIGNED) +#if !defined(CONFIG_STM32_DMACAPABLE_ASSUME_CACHE_ALIGNED) return false; #endif } @@ -1766,13 +1766,13 @@ static void stm32_sdma_dump(DMA_HANDLE handle, const char *msg) } #endif -#endif /* CONFIG_STM32H7_DMA1 || CONFIG_STM32H7_DMA2 */ +#endif /* CONFIG_STM32_DMA1 || CONFIG_STM32_DMA2 */ /**************************************************************************** * Basic DMA functions ****************************************************************************/ -#ifdef CONFIG_STM32H7_BDMA +#ifdef CONFIG_STM32_BDMA /**************************************************************************** * Name: stm32_bdma_channel_disable @@ -1898,7 +1898,7 @@ static void stm32_bdma_setup(DMA_HANDLE handle, stm32_dmacfg_t *cfg) "scr: %08" PRIx32 "\n", cfg->paddr, cfg->maddr, cfg->ndata, cfg->cfg1); -#ifdef CONFIG_STM32H7_DMACAPABLE +#ifdef CONFIG_STM32_DMACAPABLE DEBUGASSERT(stm32_bdma_capable(cfg)); #endif @@ -2106,7 +2106,7 @@ static size_t stm32_bdma_residual(DMA_HANDLE handle) * Name: stm32_bdma_capable ****************************************************************************/ -#ifdef CONFIG_STM32H7_DMACAPABLE +#ifdef CONFIG_STM32_DMACAPABLE static bool stm32_bdma_capable(stm32_dmacfg_t *cfg) { uint32_t transfer_size; @@ -2177,7 +2177,7 @@ static bool stm32_bdma_capable(stm32_dmacfg_t *cfg) dmainfo("stm32_dmacapable: dcache unaligned " "maddr:0x%08" PRIx32 " mend:0x%08" PRIx32 "\n", cfg->maddr, mend); -#if !defined(CONFIG_STM32H7_DMACAPABLE_ASSUME_CACHE_ALIGNED) +#if !defined(CONFIG_STM32_DMACAPABLE_ASSUME_CACHE_ALIGNED) return false; #endif } @@ -2253,7 +2253,7 @@ static void stm32_bdma_dump(DMA_HANDLE handle, const char *msg) } #endif -#endif /* CONFIG_STM32H7_BDMA */ +#endif /* CONFIG_STM32_BDMA */ /**************************************************************************** * Name: stm32_dmamux_dump @@ -2341,30 +2341,30 @@ void weak_function arm_dma_initialize(void) #ifdef CONFIG_ARCH_IRQPRIO switch (controller) { -#if defined(CONFIG_STM32H7_DMA1) || defined(CONFIG_STM32H7_DMA2) +#if defined(CONFIG_STM32_DMA1) || defined(CONFIG_STM32_DMA2) case DMA1: case DMA2: { up_prioritize_irq(dmachan->irq, CONFIG_DMA_PRI); break; } -#endif /* CONFIG_STM32H7_DMA1 && CONFIG_STM32H7_DMA2 */ +#endif /* CONFIG_STM32_DMA1 && CONFIG_STM32_DMA2 */ -#ifdef CONFIG_STM32H7_MDMA +#ifdef CONFIG_STM32_MDMA case MDMA: { up_prioritize_irq(dmachan->irq, CONFIG_MDMA_PRI); break; } -#endif /* CONFIG_STM32H7_MDMA */ +#endif /* CONFIG_STM32_MDMA */ -#ifdef CONFIG_STM32H7_BDMA +#ifdef CONFIG_STM32_BDMA case BDMA: { up_prioritize_irq(dmachan->irq, CONFIG_BDMA_PRI); break; } -#endif /* CONFIG_STM32H7_BDMA */ +#endif /* CONFIG_STM32_BDMA */ default: { @@ -2666,7 +2666,7 @@ size_t stm32_dmaresidual(DMA_HANDLE handle) * ****************************************************************************/ -#ifdef CONFIG_STM32H7_DMACAPABLE +#ifdef CONFIG_STM32_DMACAPABLE bool stm32_dmacapable(DMA_HANDLE handle, stm32_dmacfg_t *cfg) { DMA_CHANNEL dmachan = (DMA_CHANNEL)handle; diff --git a/arch/arm/src/stm32h7/stm32_dma.h b/arch/arm/src/stm32h7/stm32_dma.h index d8cfdc3524ed2..39b440be58eed 100644 --- a/arch/arm/src/stm32h7/stm32_dma.h +++ b/arch/arm/src/stm32h7/stm32_dma.h @@ -194,7 +194,7 @@ size_t stm32_dmaresidual(DMA_HANDLE handle); * Name: stm32_dmacapable ****************************************************************************/ -#ifdef CONFIG_STM32H7_DMACAPABLE +#ifdef CONFIG_STM32_DMACAPABLE bool stm32_dmacapable(DMA_HANDLE handle, stm32_dmacfg_t *cfg); #else # define stm32_dmacapable(handle, cfg) (true) diff --git a/arch/arm/src/stm32h7/stm32_dtcm.h b/arch/arm/src/stm32h7/stm32_dtcm.h index aba82326484b1..c55ded32e5700 100644 --- a/arch/arm/src/stm32h7/stm32_dtcm.h +++ b/arch/arm/src/stm32h7/stm32_dtcm.h @@ -50,7 +50,7 @@ * heap. */ -#ifndef CONFIG_STM32H7_DTCMEXCLUDE +#ifndef CONFIG_STM32_DTCMEXCLUDE # undef HAVE_DTCM_HEAP #endif diff --git a/arch/arm/src/stm32h7/stm32_dualcore.c b/arch/arm/src/stm32h7/stm32_dualcore.c index 5288a3f2206ec..d0b3d84148f95 100644 --- a/arch/arm/src/stm32h7/stm32_dualcore.c +++ b/arch/arm/src/stm32h7/stm32_dualcore.c @@ -52,7 +52,7 @@ ****************************************************************************/ #if (defined(CONFIG_ARCH_CHIP_STM32H7_CORTEXM7) && \ - defined(CONFIG_STM32H7_CORTEXM4_ENABLED)) || \ + defined(CONFIG_STM32_CORTEXM4_ENABLED)) || \ defined(CONFIG_ARCH_CHIP_STM32H7_CORTEXM4) /**************************************************************************** @@ -105,7 +105,7 @@ static void stm32_cpu2sem_wait(void) #endif #if defined(CONFIG_ARCH_CHIP_STM32H7_CORTEXM7) && \ - defined(CONFIG_STM32H7_CORTEXM4_ENABLED) + defined(CONFIG_STM32_CORTEXM4_ENABLED) /**************************************************************************** * Name: stm32_cm7_take_sem @@ -134,17 +134,17 @@ static void stm32_cpu2sem_take(void) ****************************************************************************/ #if defined(CONFIG_ARCH_CHIP_STM32H7_CORTEXM7) && \ - defined(CONFIG_STM32H7_CORTEXM4_ENABLED) + defined(CONFIG_STM32_CORTEXM4_ENABLED) /**************************************************************************** - * Name: stm32h7_start_cm4 + * Name: stm32_start_cm4 * * Description: * Start CM4 core * ****************************************************************************/ -void stm32h7_start_cm4(void) +void stm32_start_cm4(void) { uint32_t regval = 0; @@ -162,7 +162,7 @@ void stm32h7_start_cm4(void) stm32_cpu2sem_take(); } -#ifdef CONFIG_STM32H7_CORTEXM7_BOOTM4 +#ifdef CONFIG_STM32_CORTEXM7_BOOTM4 else { /* CM4 not started at boot - force CM4 boot */ @@ -177,14 +177,14 @@ void stm32h7_start_cm4(void) #ifdef CONFIG_ARCH_CHIP_STM32H7_CORTEXM4 /**************************************************************************** - * Name: stm32h7_waitfor_cm7 + * Name: stm32_waitfor_cm7 * * Description: * Wait for CM7 core initialization * ****************************************************************************/ -void stm32h7_waitfor_cm7(void) +void stm32_waitfor_cm7(void) { if (stm32_cm4_boot() == true) { diff --git a/arch/arm/src/stm32h7/stm32_dualcore.h b/arch/arm/src/stm32h7/stm32_dualcore.h index ab0524de3bf03..9a8973b6ccb0d 100644 --- a/arch/arm/src/stm32h7/stm32_dualcore.h +++ b/arch/arm/src/stm32h7/stm32_dualcore.h @@ -51,29 +51,29 @@ extern "C" #endif #if defined(CONFIG_ARCH_CHIP_STM32H7_CORTEXM7) && \ - defined(CONFIG_STM32H7_CORTEXM4_ENABLED) + defined(CONFIG_STM32_CORTEXM4_ENABLED) /**************************************************************************** - * Name: stm32h7_start_cm4 + * Name: stm32_start_cm4 * * Description: * Start CM4 core * ****************************************************************************/ -void stm32h7_start_cm4(void); +void stm32_start_cm4(void); #endif #ifdef CONFIG_ARCH_CHIP_STM32H7_CORTEXM4 /**************************************************************************** - * Name: stm32h7_waitfor_cm7 + * Name: stm32_waitfor_cm7 * * Description: * Wait for CM7 core initialization * ****************************************************************************/ -void stm32h7_waitfor_cm7(void); +void stm32_waitfor_cm7(void); #endif #undef EXTERN diff --git a/arch/arm/src/stm32h7/stm32_ethernet.c b/arch/arm/src/stm32h7/stm32_ethernet.c index 2787c840596ba..2ae195bf09bd5 100644 --- a/arch/arm/src/stm32h7/stm32_ethernet.c +++ b/arch/arm/src/stm32h7/stm32_ethernet.c @@ -68,12 +68,12 @@ #include -/* STM32H7_NETHERNET determines the number of physical interfaces that can - * be supported by the hardware. CONFIG_STM32H7_ETHMAC will defined if +/* STM32_NETHERNET determines the number of physical interfaces that can + * be supported by the hardware. CONFIG_STM32_ETHMAC will defined if * any STM32H7 Ethernet support is enabled in the configuration. */ -#if STM32H7_NETHERNET > 0 && defined(CONFIG_STM32H7_ETHMAC) +#if STM32_NETHERNET > 0 && defined(CONFIG_STM32_ETHMAC) /**************************************************************************** * Pre-processor Definitions @@ -81,7 +81,7 @@ /* Configuration ************************************************************/ -#if STM32H7_NETHERNET > 1 +#if STM32_NETHERNET > 1 # error "Logic to support multiple Ethernet interfaces is incomplete" #endif @@ -95,9 +95,9 @@ /* Select work queue */ -# if defined(CONFIG_STM32H7_ETHMAC_HPWORK) +# if defined(CONFIG_STM32_ETHMAC_HPWORK) # define ETHWORK HPWORK -# elif defined(CONFIG_STM32H7_ETHMAC_LPWORK) +# elif defined(CONFIG_STM32_ETHMAC_LPWORK) # define ETHWORK LPWORK # else # define ETHWORK LPWORK @@ -105,136 +105,136 @@ #endif #if defined(CONFIG_ETH0_PHY_AM79C874) -# define STM32H7_PHYID1 MII_PHYID1_AM79C874 -# define STM32H7_PHYID2 MII_PHYID2_AM79C874 +# define STM32_PHYID1 MII_PHYID1_AM79C874 +# define STM32_PHYID2 MII_PHYID2_AM79C874 #elif defined(CONFIG_ETH0_PHY_AR8031) -# define STM32H7_PHYID1 MII_PHYID1_AR8031 -# define STM32H7_PHYID2 MII_PHYID2_AR8031 +# define STM32_PHYID1 MII_PHYID1_AR8031 +# define STM32_PHYID2 MII_PHYID2_AR8031 #elif defined(CONFIG_ETH0_PHY_KS8721) -# define STM32H7_PHYID1 MII_PHYID1_KS8721 -# define STM32H7_PHYID2 MII_PHYID2_KS8721 +# define STM32_PHYID1 MII_PHYID1_KS8721 +# define STM32_PHYID2 MII_PHYID2_KS8721 #elif defined(CONFIG_ETH0_PHY_KSZ8041) -# define STM32H7_PHYID1 MII_PHYID1_KSZ8041 -# define STM32H7_PHYID2 MII_PHYID2_KSZ8041 +# define STM32_PHYID1 MII_PHYID1_KSZ8041 +# define STM32_PHYID2 MII_PHYID2_KSZ8041 #elif defined(CONFIG_ETH0_PHY_KSZ8051) -# define STM32H7_PHYID1 MII_PHYID1_KSZ8051 -# define STM32H7_PHYID2 MII_PHYID2_KSZ8051 +# define STM32_PHYID1 MII_PHYID1_KSZ8051 +# define STM32_PHYID2 MII_PHYID2_KSZ8051 #elif defined(CONFIG_ETH0_PHY_KSZ8061) -# define STM32H7_PHYID1 MII_PHYID1_KSZ8061 -# define STM32H7_PHYID2 MII_PHYID2_KSZ8061 +# define STM32_PHYID1 MII_PHYID1_KSZ8061 +# define STM32_PHYID2 MII_PHYID2_KSZ8061 #elif defined(CONFIG_ETH0_PHY_KSZ8081) -# define STM32H7_PHYID1 MII_PHYID1_KSZ8081 -# define STM32H7_PHYID2 MII_PHYID2_KSZ8081 +# define STM32_PHYID1 MII_PHYID1_KSZ8081 +# define STM32_PHYID2 MII_PHYID2_KSZ8081 #elif defined(CONFIG_ETH0_PHY_DP83848C) -# define STM32H7_PHYID1 MII_PHYID1_DP83848C -# define STM32H7_PHYID2 MII_PHYID2_DP83848C +# define STM32_PHYID1 MII_PHYID1_DP83848C +# define STM32_PHYID2 MII_PHYID2_DP83848C #elif defined(CONFIG_ETH0_PHY_DP83825I) -# define STM32H7_PHYID1 MII_PHYID1_DP83825I -# define STM32H7_PHYID2 MII_PHYID2_DP83825I +# define STM32_PHYID1 MII_PHYID1_DP83825I +# define STM32_PHYID2 MII_PHYID2_DP83825I #elif defined(CONFIG_ETH0_PHY_TJA1100) -# define STM32H7_PHYID1 MII_PHYID1_TJA1100 -# define STM32H7_PHYID2 MII_PHYID2_TJA1100 +# define STM32_PHYID1 MII_PHYID1_TJA1100 +# define STM32_PHYID2 MII_PHYID2_TJA1100 #elif defined(CONFIG_ETH0_PHY_TJA1101) -# define STM32H7_PHYID1 MII_PHYID1_TJA1101 -# define STM32H7_PHYID2 MII_PHYID2_TJA1101 +# define STM32_PHYID1 MII_PHYID1_TJA1101 +# define STM32_PHYID2 MII_PHYID2_TJA1101 #elif defined(CONFIG_ETH0_PHY_TJA1103) -# define STM32H7_PHYID1 MII_PHYID1_TJA1103 -# define STM32H7_PHYID2 MII_PHYID2_TJA1103 +# define STM32_PHYID1 MII_PHYID1_TJA1103 +# define STM32_PHYID2 MII_PHYID2_TJA1103 #elif defined(CONFIG_ETH0_PHY_LAN8720) -# define STM32H7_PHYID1 MII_PHYID1_LAN8720 -# define STM32H7_PHYID2 MII_PHYID2_LAN8720 +# define STM32_PHYID1 MII_PHYID1_LAN8720 +# define STM32_PHYID2 MII_PHYID2_LAN8720 #elif defined(CONFIG_ETH0_PHY_LAN8740) -# define STM32H7_PHYID1 MII_PHYID1_LAN8740 -# define STM32H7_PHYID2 MII_PHYID2_LAN8740 +# define STM32_PHYID1 MII_PHYID1_LAN8740 +# define STM32_PHYID2 MII_PHYID2_LAN8740 #elif defined(CONFIG_ETH0_PHY_LAN8740A) -# define STM32H7_PHYID1 MII_PHYID1_LAN8740A -# define STM32H7_PHYID2 MII_PHYID2_LAN8740A +# define STM32_PHYID1 MII_PHYID1_LAN8740A +# define STM32_PHYID2 MII_PHYID2_LAN8740A #elif defined(CONFIG_ETH0_PHY_LAN8742A) -# define STM32H7_PHYID1 MII_PHYID1_LAN8742A -# define STM32H7_PHYID2 MII_PHYID2_LAN8742A +# define STM32_PHYID1 MII_PHYID1_LAN8742A +# define STM32_PHYID2 MII_PHYID2_LAN8742A #elif defined(CONFIG_ETH0_PHY_DM9161) -# define STM32H7_PHYID1 MII_PHYID1_DM9161 -# define STM32H7_PHYID2 MII_PHYID2_DM9161 +# define STM32_PHYID1 MII_PHYID1_DM9161 +# define STM32_PHYID2 MII_PHYID2_DM9161 #elif defined(CONFIG_ETH0_PHY_YT8512) -# define STM32H7_PHYID1 MII_PHYID1_YT8512 -# define STM32H7_PHYID2 MII_PHYID2_YT8512 +# define STM32_PHYID1 MII_PHYID1_YT8512 +# define STM32_PHYID2 MII_PHYID2_YT8512 #else # warning "No PHY specified!" #endif -#ifndef CONFIG_STM32H7_PHYADDR -# error "CONFIG_STM32H7_PHYADDR must be defined in the NuttX configuration" +#ifndef CONFIG_STM32_PHYADDR +# error "CONFIG_STM32_PHYADDR must be defined in the NuttX configuration" #endif -#if !defined(CONFIG_STM32H7_MII) && !defined(CONFIG_STM32H7_RMII) -# warning "Neither CONFIG_STM32H7_MII nor CONFIG_STM32H7_RMII defined" +#if !defined(CONFIG_STM32_MII) && !defined(CONFIG_STM32_RMII) +# warning "Neither CONFIG_STM32_MII nor CONFIG_STM32_RMII defined" #endif -#if defined(CONFIG_STM32H7_MII) && defined(CONFIG_STM32H7_RMII) -# error "Both CONFIG_STM32H7_MII and CONFIG_STM32H7_RMII defined" +#if defined(CONFIG_STM32_MII) && defined(CONFIG_STM32_RMII) +# error "Both CONFIG_STM32_MII and CONFIG_STM32_RMII defined" #endif -#ifdef CONFIG_STM32H7_MII -# if !defined(CONFIG_STM32H7_MII_MCO1) && !defined(CONFIG_STM32H7_MII_MCO2) && \ - !defined(CONFIG_STM32H7_MII_EXTCLK) -# warning "Neither CONFIG_STM32H7_MII_MCO1, CONFIG_STM32H7_MII_MCO2, nor CONFIG_STM32H7_MII_EXTCLK defined" +#ifdef CONFIG_STM32_MII +# if !defined(CONFIG_STM32_MII_MCO1) && !defined(CONFIG_STM32_MII_MCO2) && \ + !defined(CONFIG_STM32_MII_EXTCLK) +# warning "Neither CONFIG_STM32_MII_MCO1, CONFIG_STM32_MII_MCO2, nor CONFIG_STM32_MII_EXTCLK defined" # endif -# if defined(CONFIG_STM32H7_MII_MCO1) && defined(CONFIG_STM32H7_MII_MCO2) -# error "Both CONFIG_STM32H7_MII_MCO1 and CONFIG_STM32H7_MII_MCO2 defined" +# if defined(CONFIG_STM32_MII_MCO1) && defined(CONFIG_STM32_MII_MCO2) +# error "Both CONFIG_STM32_MII_MCO1 and CONFIG_STM32_MII_MCO2 defined" # endif #endif -#ifdef CONFIG_STM32H7_RMII -# if !defined(CONFIG_STM32H7_RMII_MCO1) && !defined(CONFIG_STM32H7_RMII_MCO2) && \ - !defined(CONFIG_STM32H7_RMII_EXTCLK) -# warning "Neither CONFIG_STM32H7_RMII_MCO1, CONFIG_STM32H7_RMII_MCO2, nor CONFIG_STM32H7_RMII_EXTCLK defined" +#ifdef CONFIG_STM32_RMII +# if !defined(CONFIG_STM32_RMII_MCO1) && !defined(CONFIG_STM32_RMII_MCO2) && \ + !defined(CONFIG_STM32_RMII_EXTCLK) +# warning "Neither CONFIG_STM32_RMII_MCO1, CONFIG_STM32_RMII_MCO2, nor CONFIG_STM32_RMII_EXTCLK defined" # endif -# if defined(CONFIG_STM32H7_RMII_MCO1) && defined(CONFIG_STM32H7_RMII_MCO2) -# error "Both CONFIG_STM32H7_RMII_MCO1 and CONFIG_STM32H7_RMII_MCO2 defined" +# if defined(CONFIG_STM32_RMII_MCO1) && defined(CONFIG_STM32_RMII_MCO2) +# error "Both CONFIG_STM32_RMII_MCO1 and CONFIG_STM32_RMII_MCO2 defined" # endif #endif -#ifdef CONFIG_STM32H7_AUTONEG -# ifndef CONFIG_STM32H7_PHYSR -# error "CONFIG_STM32H7_PHYSR must be defined in the NuttX configuration" +#ifdef CONFIG_STM32_AUTONEG +# ifndef CONFIG_STM32_PHYSR +# error "CONFIG_STM32_PHYSR must be defined in the NuttX configuration" # endif -# ifdef CONFIG_STM32H7_PHYSR_ALTCONFIG -# ifndef CONFIG_STM32H7_PHYSR_ALTMODE -# error "CONFIG_STM32H7_PHYSR_ALTMODE must be defined in the NuttX configuration" +# ifdef CONFIG_STM32_PHYSR_ALTCONFIG +# ifndef CONFIG_STM32_PHYSR_ALTMODE +# error "CONFIG_STM32_PHYSR_ALTMODE must be defined in the NuttX configuration" # endif -# ifndef CONFIG_STM32H7_PHYSR_10HD -# error "CONFIG_STM32H7_PHYSR_10HD must be defined in the NuttX configuration" +# ifndef CONFIG_STM32_PHYSR_10HD +# error "CONFIG_STM32_PHYSR_10HD must be defined in the NuttX configuration" # endif -# ifndef CONFIG_STM32H7_PHYSR_100HD -# error "CONFIG_STM32H7_PHYSR_100HD must be defined in the NuttX configuration" +# ifndef CONFIG_STM32_PHYSR_100HD +# error "CONFIG_STM32_PHYSR_100HD must be defined in the NuttX configuration" # endif -# ifndef CONFIG_STM32H7_PHYSR_10FD -# error "CONFIG_STM32H7_PHYSR_10FD must be defined in the NuttX configuration" +# ifndef CONFIG_STM32_PHYSR_10FD +# error "CONFIG_STM32_PHYSR_10FD must be defined in the NuttX configuration" # endif -# ifndef CONFIG_STM32H7_PHYSR_100FD -# error "CONFIG_STM32H7_PHYSR_100FD must be defined in the NuttX configuration" +# ifndef CONFIG_STM32_PHYSR_100FD +# error "CONFIG_STM32_PHYSR_100FD must be defined in the NuttX configuration" # endif # else -# ifndef CONFIG_STM32H7_PHYSR_SPEED -# error "CONFIG_STM32H7_PHYSR_SPEED must be defined in the NuttX configuration" +# ifndef CONFIG_STM32_PHYSR_SPEED +# error "CONFIG_STM32_PHYSR_SPEED must be defined in the NuttX configuration" # endif -# ifndef CONFIG_STM32H7_PHYSR_100MBPS -# error "CONFIG_STM32H7_PHYSR_100MBPS must be defined in the NuttX configuration" +# ifndef CONFIG_STM32_PHYSR_100MBPS +# error "CONFIG_STM32_PHYSR_100MBPS must be defined in the NuttX configuration" # endif -# ifndef CONFIG_STM32H7_PHYSR_MODE -# error "CONFIG_STM32H7_PHYSR_MODE must be defined in the NuttX configuration" +# ifndef CONFIG_STM32_PHYSR_MODE +# error "CONFIG_STM32_PHYSR_MODE must be defined in the NuttX configuration" # endif -# ifndef CONFIG_STM32H7_PHYSR_FULLDUPLEX -# error "CONFIG_STM32H7_PHYSR_FULLDUPLEX must be defined in the NuttX configuration" +# ifndef CONFIG_STM32_PHYSR_FULLDUPLEX +# error "CONFIG_STM32_PHYSR_FULLDUPLEX must be defined in the NuttX configuration" # endif # endif #endif -#ifdef CONFIG_STM32H7_ETH_PTP -# warning "CONFIG_STM32H7_ETH_PTP is not yet supported" +#ifdef CONFIG_STM32_ETH_PTP +# warning "CONFIG_STM32_ETH_PTP is not yet supported" #endif -#undef CONFIG_STM32H7_ETH_HWCHECKSUM +#undef CONFIG_STM32_ETH_HWCHECKSUM /* Add 4 to the configured buffer size to account for the 2 byte checksum * memory needed at the end of the maximum size packet. Buffer sizes must @@ -244,8 +244,8 @@ #define OPTIMAL_ETH_BUFSIZE ((CONFIG_NET_ETH_PKTSIZE + 4 + 15) & ~15) -#ifdef CONFIG_STM32H7_ETH_BUFSIZE -# define ETH_BUFSIZE CONFIG_STM32H7_ETH_BUFSIZE +#ifdef CONFIG_STM32_ETH_BUFSIZE +# define ETH_BUFSIZE CONFIG_STM32_ETH_BUFSIZE #else # define ETH_BUFSIZE OPTIMAL_ETH_BUFSIZE #endif @@ -262,16 +262,16 @@ # warning "You are using an incomplete/untested configuration" #endif -#ifndef CONFIG_STM32H7_ETH_NRXDESC -# define CONFIG_STM32H7_ETH_NRXDESC 8 +#ifndef CONFIG_STM32_ETH_NRXDESC +# define CONFIG_STM32_ETH_NRXDESC 8 #endif -#ifndef CONFIG_STM32H7_ETH_NTXDESC -# define CONFIG_STM32H7_ETH_NTXDESC 4 +#ifndef CONFIG_STM32_ETH_NTXDESC +# define CONFIG_STM32_ETH_NTXDESC 4 #endif /* We need at least one more free buffer than transmit buffers */ -#define STM32_ETH_NFREEBUFFERS (CONFIG_STM32H7_ETH_NTXDESC+1) +#define STM32_ETH_NFREEBUFFERS (CONFIG_STM32_ETH_NTXDESC+1) /* Buffers used for DMA access must begin on an address aligned with the * D-Cache line and must be an even multiple of the D-Cache line size. @@ -289,21 +289,21 @@ #define DESC_PADSIZE DMA_ALIGN_UP(DESC_SIZE) #define ALIGNED_BUFSIZE DMA_ALIGN_UP(ETH_BUFSIZE) -#define RXTABLE_SIZE (STM32H7_NETHERNET * CONFIG_STM32H7_ETH_NRXDESC) -#define TXTABLE_SIZE (STM32H7_NETHERNET * CONFIG_STM32H7_ETH_NTXDESC) +#define RXTABLE_SIZE (STM32_NETHERNET * CONFIG_STM32_ETH_NRXDESC) +#define TXTABLE_SIZE (STM32_NETHERNET * CONFIG_STM32_ETH_NTXDESC) -#define RXBUFFER_SIZE (CONFIG_STM32H7_ETH_NRXDESC * ALIGNED_BUFSIZE) -#define RXBUFFER_ALLOC (STM32H7_NETHERNET * RXBUFFER_SIZE) +#define RXBUFFER_SIZE (CONFIG_STM32_ETH_NRXDESC * ALIGNED_BUFSIZE) +#define RXBUFFER_ALLOC (STM32_NETHERNET * RXBUFFER_SIZE) #define TXBUFFER_SIZE (STM32_ETH_NFREEBUFFERS * ALIGNED_BUFSIZE) -#define TXBUFFER_ALLOC (STM32H7_NETHERNET * TXBUFFER_SIZE) +#define TXBUFFER_ALLOC (STM32_NETHERNET * TXBUFFER_SIZE) /* Extremely detailed register debug that you would normally never want * enabled. */ #ifndef CONFIG_DEBUG_NET_INFO -# undef CONFIG_STM32H7_ETHMAC_REGDEBUG +# undef CONFIG_STM32_ETHMAC_REGDEBUG #endif /* Clocking *****************************************************************/ @@ -394,7 +394,7 @@ * ETH_MACCR_ACS Automatic pad/CRC stripping 0 (disabled) * ETH_MACCR_DR Retry disable 1 (disabled) * ETH_MACCR_IPC IPv4 checksum offload - * Depends on CONFIG_STM32H7_ETH_HWCHECKSUM + * Depends on CONFIG_STM32_ETH_HWCHECKSUM * ETH_MACCR_LM Loopback mode 0 (disabled) * ETH_MACCR_DO Receive own disable 0 (enabled) * ETH_MACCR_DCRS Carrier sense disable 0 (enabled) @@ -409,7 +409,7 @@ * ETH_MACCR_FES Fast Ethernet speed Depends on priv->mbps100 */ -#ifdef CONFIG_STM32H7_ETH_HWCHECKSUM +#ifdef CONFIG_STM32_ETH_HWCHECKSUM # define MACCR_SET_BITS \ (ETH_MACCR_BL_10 | ETH_MACCR_DR | ETH_MACCR_IPC | ETH_MACCR_IPG(96)) #else @@ -558,10 +558,10 @@ #define MTLRXQOMR_SET_MASK \ ((0x7 << ETH_MTLRXQOMR_RQS_SHIFT) | ETH_MTLRXQOMR_RTC_64) -#ifdef CONFIG_STM32H7_ETH_HWCHECKSUM +#ifdef CONFIG_STM32_ETH_HWCHECKSUM /* TODO */ -# error CONFIG_STM32H7_ETH_HWCHECKSUM not supported +# error CONFIG_STM32_ETH_HWCHECKSUM not supported #endif /* Clear the DMAMR bits that will be setup during MAC initialization (or that @@ -723,7 +723,7 @@ aligned_data(ARMV7M_DCACHE_LINESIZE); /* These are the pre-allocated Ethernet device structures */ -static struct stm32_ethmac_s g_stm32ethmac[STM32H7_NETHERNET]; +static struct stm32_ethmac_s g_stm32ethmac[STM32_NETHERNET]; /**************************************************************************** * Private Function Prototypes @@ -731,7 +731,7 @@ static struct stm32_ethmac_s g_stm32ethmac[STM32H7_NETHERNET]; /* Register operations ******************************************************/ -#ifdef CONFIG_STM32H7_ETHMAC_REGDEBUG +#ifdef CONFIG_STM32_ETHMAC_REGDEBUG static uint32_t stm32_getreg(uint32_t addr); static void stm32_putreg(uint32_t val, uint32_t addr); static void stm32_checksetup(void); @@ -803,7 +803,7 @@ static void stm32_rxdescinit(struct stm32_ethmac_s *priv, union stm32_desc_u *rxtable, uint8_t *rxbuffer); /* PHY Initialization */ -#ifndef CONFIG_STM32H7_NO_PHY +#ifndef CONFIG_STM32_NO_PHY #if defined(CONFIG_NETDEV_PHY_IOCTL) && defined(CONFIG_ARCH_PHY_INTERRUPT) static int stm32_phyintenable(struct stm32_ethmac_s *priv); #endif @@ -812,17 +812,17 @@ static int stm32_phyintenable(struct stm32_ethmac_s *priv); static inline int stm32_dm9161(struct stm32_ethmac_s *priv); #endif static int stm32_phyinit(struct stm32_ethmac_s *priv); -#ifdef CONFIG_STM32H7_ETHMAC_REGDEBUG +#ifdef CONFIG_STM32_ETHMAC_REGDEBUG static void stm32_phyregdump(struct stm32_ethmac_s *priv); #endif #endif /* MAC/DMA Initialization */ -#ifdef CONFIG_STM32H7_MII +#ifdef CONFIG_STM32_MII static inline void stm32_selectmii(void); #endif -#ifdef CONFIG_STM32H7_RMII +#ifdef CONFIG_STM32_RMII static inline void stm32_selectrmii(void); #endif static inline void stm32_ethgpioconfig(struct stm32_ethmac_s *priv); @@ -852,7 +852,7 @@ static int stm32_ethconfig(struct stm32_ethmac_s *priv); * ****************************************************************************/ -#ifdef CONFIG_STM32H7_ETHMAC_REGDEBUG +#ifdef CONFIG_STM32_ETHMAC_REGDEBUG static uint32_t stm32_getreg(uint32_t addr) { static uint32_t prevaddr = 0; @@ -924,7 +924,7 @@ static uint32_t stm32_getreg(uint32_t addr) * ****************************************************************************/ -#ifdef CONFIG_STM32H7_ETHMAC_REGDEBUG +#ifdef CONFIG_STM32_ETHMAC_REGDEBUG static void stm32_putreg(uint32_t val, uint32_t addr) { /* Show the register value being written */ @@ -951,7 +951,7 @@ static void stm32_putreg(uint32_t val, uint32_t addr) * ****************************************************************************/ -#ifdef CONFIG_STM32H7_ETHMAC_REGDEBUG +#ifdef CONFIG_STM32_ETHMAC_REGDEBUG static void stm32_checksetup(void) { } @@ -1093,10 +1093,10 @@ static struct eth_desc_s *stm32_get_next_txdesc(struct stm32_ethmac_s *priv, struct eth_desc_s * curr) { union stm32_desc_u *first = - &g_txtable[priv->intf * CONFIG_STM32H7_ETH_NTXDESC]; + &g_txtable[priv->intf * CONFIG_STM32_ETH_NTXDESC]; union stm32_desc_u *last = - &g_txtable[priv->intf * CONFIG_STM32H7_ETH_NTXDESC + - CONFIG_STM32H7_ETH_NTXDESC - 1]; + &g_txtable[priv->intf * CONFIG_STM32_ETH_NTXDESC + + CONFIG_STM32_ETH_NTXDESC - 1]; union stm32_desc_u *next = ((union stm32_desc_u *)curr) + 1; if (next > last) @@ -1313,7 +1313,7 @@ static int stm32_transmit(struct stm32_ethmac_s *priv) * stoppable transmit events. */ - if (priv->inflight >= CONFIG_STM32H7_ETH_NTXDESC) + if (priv->inflight >= CONFIG_STM32_ETH_NTXDESC) { stm32_disableint(priv, ETH_DMACIER_RIE); } @@ -1379,7 +1379,7 @@ static int stm32_txpoll(struct net_driver_s *dev) * In a race condition, ETH_TDES3_OWN may be cleared BUT still * not available because stm32_freeframe() has not yet run. If * stm32_freeframe() has run, the buffer1 pointer (tdes2) will be - * nullified (and inflight should be < CONFIG_STM32H7_ETH_NTXDESC). + * nullified (and inflight should be < CONFIG_STM32_ETH_NTXDESC). */ if ((priv->txhead->des3 & ETH_TDES3_RD_OWN) != 0 || @@ -1452,7 +1452,7 @@ static void stm32_dopoll(struct stm32_ethmac_s *priv) * In a race condition, ETH_TDES3_RD_OWN may be cleared BUT still * not available because stm32_freeframe() has not yet run. If * stm32_freeframe() has run, the buffer1 pointer (des0) will be - * nullified (and inflight should be < CONFIG_STM32H7_ETH_NTXDESC). + * nullified (and inflight should be < CONFIG_STM32_ETH_NTXDESC). */ if ((priv->txhead->des3 & ETH_TDES3_RD_OWN) == 0 && @@ -1578,10 +1578,10 @@ static struct eth_desc_s *stm32_get_next_rxdesc(struct stm32_ethmac_s *priv, struct eth_desc_s * curr) { union stm32_desc_u *first = - &g_rxtable[priv->intf * CONFIG_STM32H7_ETH_NRXDESC]; + &g_rxtable[priv->intf * CONFIG_STM32_ETH_NRXDESC]; union stm32_desc_u *last = - &g_rxtable[priv->intf * CONFIG_STM32H7_ETH_NRXDESC + - CONFIG_STM32H7_ETH_NRXDESC - 1]; + &g_rxtable[priv->intf * CONFIG_STM32_ETH_NRXDESC + + CONFIG_STM32_ETH_NRXDESC - 1]; union stm32_desc_u *next = ((union stm32_desc_u *)curr) + 1; if (next > last) @@ -1732,8 +1732,8 @@ static int stm32_recvframe(struct stm32_ethmac_s *priv) for (i = 0; (rxdesc->des3 & ETH_RDES3_WB_OWN) == 0 && - i < CONFIG_STM32H7_ETH_NRXDESC && - priv->inflight < CONFIG_STM32H7_ETH_NTXDESC; + i < CONFIG_STM32_ETH_NRXDESC && + priv->inflight < CONFIG_STM32_ETH_NTXDESC; i++) { /* Check if this is a normal descriptor */ @@ -2831,7 +2831,7 @@ static void stm32_txdescinit(struct stm32_ethmac_s *priv, /* Initialize each TX descriptor */ - for (i = 0; i < CONFIG_STM32H7_ETH_NTXDESC; i++) + for (i = 0; i < CONFIG_STM32_ETH_NTXDESC; i++) { txdesc = &txtable[i].desc; @@ -2867,7 +2867,7 @@ static void stm32_txdescinit(struct stm32_ethmac_s *priv, * properly but the DMACCATXDR advances to outside the descriptor ring */ - stm32_putreg(CONFIG_STM32H7_ETH_NTXDESC - 1, STM32_ETH_DMACTXRLR); + stm32_putreg(CONFIG_STM32_ETH_NTXDESC - 1, STM32_ETH_DMACTXRLR); /* Set Transmit Descriptor List Address Register */ @@ -2920,7 +2920,7 @@ static void stm32_rxdescinit(struct stm32_ethmac_s *priv, /* Initialize each RX descriptor */ - for (i = 0; i < CONFIG_STM32H7_ETH_NRXDESC; i++) + for (i = 0; i < CONFIG_STM32_ETH_NRXDESC; i++) { rxdesc = &rxtable[i].desc; @@ -2953,7 +2953,7 @@ static void stm32_rxdescinit(struct stm32_ethmac_s *priv, * properly but the DMACCARXDR advances to outside the descriptor ring */ - stm32_putreg(CONFIG_STM32H7_ETH_NRXDESC - 1, STM32_ETH_DMACRXRLR); + stm32_putreg(CONFIG_STM32_ETH_NRXDESC - 1, STM32_ETH_DMACRXRLR); /* Set Receive Descriptor List Address Register */ @@ -2961,7 +2961,7 @@ static void stm32_rxdescinit(struct stm32_ethmac_s *priv, /* Set Receive Descriptor Tail pointer Address */ - stm32_putreg((uint32_t)&rxtable[CONFIG_STM32H7_ETH_NRXDESC - 1].desc, + stm32_putreg((uint32_t)&rxtable[CONFIG_STM32_ETH_NRXDESC - 1].desc, STM32_ETH_DMACRXDTPR); } @@ -2997,7 +2997,7 @@ static void stm32_rxdescinit(struct stm32_ethmac_s *priv, #ifdef CONFIG_NETDEV_PHY_IOCTL static int stm32_ioctl(struct net_driver_s *dev, int cmd, unsigned long arg) { -#ifndef CONFIG_STM32H7_NO_PHY +#ifndef CONFIG_STM32_NO_PHY #ifdef CONFIG_ARCH_PHY_INTERRUPT struct stm32_ethmac_s *priv = (struct stm32_ethmac_s *)dev->d_private; #endif @@ -3027,7 +3027,7 @@ static int stm32_ioctl(struct net_driver_s *dev, int cmd, unsigned long arg) { struct mii_ioctl_data_s *req = (struct mii_ioctl_data_s *)((uintptr_t)arg); - req->phy_id = CONFIG_STM32H7_PHYADDR; + req->phy_id = CONFIG_STM32_PHYADDR; ret = OK; } break; @@ -3062,7 +3062,7 @@ static int stm32_ioctl(struct net_driver_s *dev, int cmd, unsigned long arg) } #endif /* CONFIG_NETDEV_PHY_IOCTL */ -#ifndef CONFIG_STM32H7_NO_PHY +#ifndef CONFIG_STM32_NO_PHY /**************************************************************************** * Function: stm32_phyintenable * @@ -3119,7 +3119,7 @@ static inline int stm32_dm9161(struct stm32_ethmac_s *priv) */ ret = mdio_read(priv->mdio, - CONFIG_STM32H7_PHYADDR, MII_PHYID1, &phyval); + CONFIG_STM32_PHYADDR, MII_PHYID1, &phyval); if (ret < 0) { nerr("ERROR: Failed to read the PHY ID1: %d\n", ret); @@ -3142,7 +3142,7 @@ static inline int stm32_dm9161(struct stm32_ethmac_s *priv) */ ret = mdio_read(priv->mdio, - CONFIG_STM32H7_PHYADDR, 16, &phyval); + CONFIG_STM32_PHYADDR, 16, &phyval); if (ret < 0) { nerr("ERROR: Failed to read the PHY Register 0x10: %d\n", ret); @@ -3176,7 +3176,7 @@ static inline int stm32_dm9161(struct stm32_ethmac_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32H7_ETHMAC_REGDEBUG +#ifdef CONFIG_STM32_ETHMAC_REGDEBUG static void stm32_phyregdump(struct stm32_ethmac_s *priv) { uint16_t phyval; @@ -3186,7 +3186,7 @@ static void stm32_phyregdump(struct stm32_ethmac_s *priv) for (i = 0; i < 0x20; i++) { ret = mdio_read(priv->mdio, - CONFIG_STM32H7_PHYADDR, i, &phyval); + CONFIG_STM32_PHYADDR, i, &phyval); if (ret < 0) { nerr("ERROR: Failed to read reg: 0%2x\n", i); @@ -3217,7 +3217,7 @@ static void stm32_phyregdump(struct stm32_ethmac_s *priv) static int stm32_phyinit(struct stm32_ethmac_s *priv) { -#ifdef CONFIG_STM32H7_AUTONEG +#ifdef CONFIG_STM32_AUTONEG volatile uint32_t timeout; #endif uint32_t regval; @@ -3240,7 +3240,7 @@ static int stm32_phyinit(struct stm32_ethmac_s *priv) /* Put the PHY in reset mode */ ret = mdio_write(priv->mdio, - CONFIG_STM32H7_PHYADDR, MII_MCR, MII_MCR_RESET); + CONFIG_STM32_PHYADDR, MII_MCR, MII_MCR_RESET); if (ret < 0) { nerr("ERROR: Failed to reset the PHY: %d\n", ret); @@ -3254,7 +3254,7 @@ static int stm32_phyinit(struct stm32_ethmac_s *priv) to -= 10; phyval = 0xffff; ret = mdio_read(priv->mdio, - CONFIG_STM32H7_PHYADDR, MII_MCR, &phyval); + CONFIG_STM32_PHYADDR, MII_MCR, &phyval); ninfo("MII_MCR: phyval: %u ret: %d\n", phyval, ret); } @@ -3271,7 +3271,7 @@ static int stm32_phyinit(struct stm32_ethmac_s *priv) } ret = mdio_read(priv->mdio, - CONFIG_STM32H7_PHYADDR, MII_PHYID1, &phyval); + CONFIG_STM32_PHYADDR, MII_PHYID1, &phyval); if (ret < 0) { @@ -3279,17 +3279,17 @@ static int stm32_phyinit(struct stm32_ethmac_s *priv) return ret; } - if (phyval != STM32H7_PHYID1) + if (phyval != STM32_PHYID1) { nerr("ERROR: Incorrect PHYID1: %u expected: %u\n", - phyval, STM32H7_PHYID1); + phyval, STM32_PHYID1); return -ENXIO; } ninfo("MII_PHYID1: phyval: %u ret: %d\n", phyval, ret); ret = mdio_read(priv->mdio, - CONFIG_STM32H7_PHYADDR, MII_PHYID2, &phyval); + CONFIG_STM32_PHYADDR, MII_PHYID2, &phyval); if (ret < 0) { @@ -3297,16 +3297,16 @@ static int stm32_phyinit(struct stm32_ethmac_s *priv) return ret; } - if ((phyval & 0xfff0) != (STM32H7_PHYID2 & 0xfff0)) + if ((phyval & 0xfff0) != (STM32_PHYID2 & 0xfff0)) { nerr("ERROR: Incorrect PHYID2: %u expected: %u\n", - phyval, STM32H7_PHYID2); + phyval, STM32_PHYID2); return -ENXIO; } ninfo("MII_PHYID2: phyval: %u ret: %d\n", phyval, ret); -#ifdef CONFIG_STM32H7_ETHMAC_REGDEBUG +#ifdef CONFIG_STM32_ETHMAC_REGDEBUG stm32_phyregdump(priv); #endif @@ -3322,13 +3322,13 @@ static int stm32_phyinit(struct stm32_ethmac_s *priv) /* Perform auto-negotiation if so configured */ -#ifdef CONFIG_STM32H7_AUTONEG +#ifdef CONFIG_STM32_AUTONEG /* Wait for link status */ for (timeout = 0; timeout < PHY_RETRY_TIMEOUT; timeout++) { ret = mdio_read(priv->mdio, - CONFIG_STM32H7_PHYADDR, MII_MSR, &phyval); + CONFIG_STM32_PHYADDR, MII_MSR, &phyval); if (ret < 0) { nerr("ERROR: Failed to read the PHY MSR: %d\n", ret); @@ -3352,7 +3352,7 @@ static int stm32_phyinit(struct stm32_ethmac_s *priv) /* Enable auto-negotiation */ ret = mdio_write(priv->mdio, - CONFIG_STM32H7_PHYADDR, MII_MCR, MII_MCR_ANENABLE); + CONFIG_STM32_PHYADDR, MII_MCR, MII_MCR_ANENABLE); if (ret < 0) { nerr("ERROR: Failed to enable auto-negotiation: %d\n", ret); @@ -3364,7 +3364,7 @@ static int stm32_phyinit(struct stm32_ethmac_s *priv) for (timeout = 0; timeout < PHY_RETRY_TIMEOUT; timeout++) { ret = mdio_read(priv->mdio, - CONFIG_STM32H7_PHYADDR, MII_MSR, &phyval); + CONFIG_STM32_PHYADDR, MII_MSR, &phyval); if (ret < 0) { nerr("ERROR: Failed to read the PHY MSR: %d\n", ret); @@ -3387,7 +3387,7 @@ static int stm32_phyinit(struct stm32_ethmac_s *priv) /* Read the result of the auto-negotiation from the PHY-specific register */ ret = mdio_read(priv->mdio, - CONFIG_STM32H7_PHYADDR, CONFIG_STM32H7_PHYSR, &phyval); + CONFIG_STM32_PHYADDR, CONFIG_STM32_PHYSR, &phyval); if (ret < 0) { nerr("ERROR: Failed to read PHY status register\n"); @@ -3396,38 +3396,38 @@ static int stm32_phyinit(struct stm32_ethmac_s *priv) /* Remember the selected speed and duplex modes */ - ninfo("PHYSR[%d]: %04x\n", CONFIG_STM32H7_PHYSR, phyval); + ninfo("PHYSR[%d]: %04x\n", CONFIG_STM32_PHYSR, phyval); /* Different PHYs present speed and mode information in different ways. IF - * This CONFIG_STM32H7_PHYSR_ALTCONFIG is selected, this indicates that + * This CONFIG_STM32_PHYSR_ALTCONFIG is selected, this indicates that * the PHY represents speed and mode information are combined, for * example, with separate bits for 10HD, 100HD, 10FD and 100FD. */ -#ifdef CONFIG_STM32H7_PHYSR_ALTCONFIG - switch (phyval & CONFIG_STM32H7_PHYSR_ALTMODE) +#ifdef CONFIG_STM32_PHYSR_ALTCONFIG + switch (phyval & CONFIG_STM32_PHYSR_ALTMODE) { default: nerr("ERROR: Unrecognized PHY status setting\n"); /* Falls through */ - case CONFIG_STM32H7_PHYSR_10HD: + case CONFIG_STM32_PHYSR_10HD: priv->fduplex = 0; priv->mbps100 = 0; break; - case CONFIG_STM32H7_PHYSR_100HD: + case CONFIG_STM32_PHYSR_100HD: priv->fduplex = 0; priv->mbps100 = 1; break; - case CONFIG_STM32H7_PHYSR_10FD: + case CONFIG_STM32_PHYSR_10FD: priv->fduplex = 1; priv->mbps100 = 0; break; - case CONFIG_STM32H7_PHYSR_100FD: + case CONFIG_STM32_PHYSR_100FD: priv->fduplex = 1; priv->mbps100 = 1; break; @@ -3440,13 +3440,13 @@ static int stm32_phyinit(struct stm32_ethmac_s *priv) */ #else - if ((phyval & CONFIG_STM32H7_PHYSR_MODE) == - CONFIG_STM32H7_PHYSR_FULLDUPLEX) + if ((phyval & CONFIG_STM32_PHYSR_MODE) == + CONFIG_STM32_PHYSR_FULLDUPLEX) { priv->fduplex = 1; } - if ((phyval & CONFIG_STM32H7_PHYSR_SPEED) == CONFIG_STM32H7_PHYSR_100MBPS) + if ((phyval & CONFIG_STM32_PHYSR_SPEED) == CONFIG_STM32_PHYSR_100MBPS) { priv->mbps100 = 1; } @@ -3455,14 +3455,14 @@ static int stm32_phyinit(struct stm32_ethmac_s *priv) #else /* Auto-negotiation not selected */ phyval = 0; -#ifdef CONFIG_STM32H7_ETHFD +#ifdef CONFIG_STM32_ETHFD phyval |= MII_MCR_FULLDPLX; #endif -#ifdef CONFIG_STM32H7_ETH100MBPS +#ifdef CONFIG_STM32_ETH100MBPS phyval |= MII_MCR_SPEED100; #endif - ret = stm32_phywrite(CONFIG_STM32H7_PHYADDR, MII_MCR, phyval, 0xffff); + ret = stm32_phywrite(CONFIG_STM32_PHYADDR, MII_MCR, phyval, 0xffff); if (ret < 0) { nerr("ERROR: Failed to write the PHY MCR: %d\n", ret); @@ -3473,10 +3473,10 @@ static int stm32_phyinit(struct stm32_ethmac_s *priv) /* Remember the selected speed and duplex modes */ -#ifdef CONFIG_STM32H7_ETHFD +#ifdef CONFIG_STM32_ETHFD priv->fduplex = 1; #endif -#ifdef CONFIG_STM32H7_ETH100MBPS +#ifdef CONFIG_STM32_ETH100MBPS priv->mbps100 = 1; #endif #endif @@ -3504,7 +3504,7 @@ static int stm32_phyinit(struct stm32_ethmac_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32H7_MII +#ifdef CONFIG_STM32_MII static inline void stm32_selectmii(void) { uint32_t regval; @@ -3530,7 +3530,7 @@ static inline void stm32_selectmii(void) * ****************************************************************************/ -#ifdef CONFIG_STM32H7_RMII +#ifdef CONFIG_STM32_RMII static inline void stm32_selectrmii(void) { uint32_t regval; @@ -3562,17 +3562,17 @@ static inline void stm32_ethgpioconfig(struct stm32_ethmac_s *priv) { /* Configure GPIO pins to support Ethernet */ -#if defined(CONFIG_STM32H7_MII) || defined(CONFIG_STM32H7_RMII) +#if defined(CONFIG_STM32_MII) || defined(CONFIG_STM32_RMII) /* MDC and MDIO are common to both modes */ -# ifndef CONFIG_STM32H7_NO_PHY +# ifndef CONFIG_STM32_NO_PHY stm32_configgpio(GPIO_ETH_MDC); stm32_configgpio(GPIO_ETH_MDIO); # endif /* Set up the MII interface */ -# if defined(CONFIG_STM32H7_MII) +# if defined(CONFIG_STM32_MII) /* Select the MII interface */ @@ -3587,7 +3587,7 @@ static inline void stm32_ethgpioconfig(struct stm32_ethmac_s *priv) * PLLI2S clock (through a configurable prescaler) on PC9 pin." */ -# if defined(CONFIG_STM32H7_MII_MCO1) +# if defined(CONFIG_STM32_MII_MCO1) /* Configure MC01 to drive the PHY. Board logic must provide MC01 clocking * info. */ @@ -3595,7 +3595,7 @@ static inline void stm32_ethgpioconfig(struct stm32_ethmac_s *priv) stm32_configgpio(GPIO_MCO1); stm32_mco1config(BOARD_CFGR_MC01_SOURCE, BOARD_CFGR_MC01_DIVIDER); -# elif defined(CONFIG_STM32H7_MII_MCO2) +# elif defined(CONFIG_STM32_MII_MCO2) /* Configure MC02 to drive the PHY. Board logic must provide MC02 clocking * info. */ @@ -3603,7 +3603,7 @@ static inline void stm32_ethgpioconfig(struct stm32_ethmac_s *priv) stm32_configgpio(GPIO_MCO2); stm32_mco2config(BOARD_CFGR_MC02_SOURCE, BOARD_CFGR_MC02_DIVIDER); -# elif defined(CONFIG_STM32H7_MII_MCO) +# elif defined(CONFIG_STM32_MII_MCO) /* Setup MCO pin for alternative usage */ stm32_configgpio(GPIO_MCO); @@ -3634,7 +3634,7 @@ static inline void stm32_ethgpioconfig(struct stm32_ethmac_s *priv) /* Set up the RMII interface. */ -# elif defined(CONFIG_STM32H7_RMII) +# elif defined(CONFIG_STM32_RMII) /* Select the RMII interface */ @@ -3649,7 +3649,7 @@ static inline void stm32_ethgpioconfig(struct stm32_ethmac_s *priv) * PLLI2S clock (through a configurable prescaler) on PC9 pin." */ -# if defined(CONFIG_STM32H7_RMII_MCO1) +# if defined(CONFIG_STM32_RMII_MCO1) /* Configure MC01 to drive the PHY. Board logic must provide MC01 clocking * info. */ @@ -3657,7 +3657,7 @@ static inline void stm32_ethgpioconfig(struct stm32_ethmac_s *priv) stm32_configgpio(GPIO_MCO1); stm32_mco1config(BOARD_CFGR_MC01_SOURCE, BOARD_CFGR_MC01_DIVIDER); -# elif defined(CONFIG_STM32H7_RMII_MCO2) +# elif defined(CONFIG_STM32_RMII_MCO2) /* Configure MC02 to drive the PHY. Board logic must provide MC02 clocking * info. */ @@ -3665,7 +3665,7 @@ static inline void stm32_ethgpioconfig(struct stm32_ethmac_s *priv) stm32_configgpio(GPIO_MCO2); stm32_mco2config(BOARD_CFGR_MC02_SOURCE, BOARD_CFGR_MC02_DIVIDER); -# elif defined(CONFIG_STM32H7_RMII_MCO) +# elif defined(CONFIG_STM32_RMII_MCO) /* Setup MCO pin for alternative usage */ stm32_configgpio(GPIO_MCO); @@ -3688,7 +3688,7 @@ static inline void stm32_ethgpioconfig(struct stm32_ethmac_s *priv) # endif #endif -#ifdef CONFIG_STM32H7_ETH_PTP +#ifdef CONFIG_STM32_ETH_PTP /* Enable pulse-per-second (PPS) output signal */ stm32_configgpio(GPIO_ETH_PPS_OUT); @@ -4027,7 +4027,7 @@ static int stm32_ethconfig(struct stm32_ethmac_s *priv) * sequence in stm32_rcc.c. */ -#ifdef CONFIG_STM32H7_PHYINIT +#ifdef CONFIG_STM32_PHYINIT /* Perform any necessary, board-specific PHY initialization */ ret = stm32_phy_boardinitialize(0); @@ -4050,24 +4050,24 @@ static int stm32_ethconfig(struct stm32_ethmac_s *priv) /* Initialize TX Descriptors list */ stm32_txdescinit(priv, - &g_txtable[priv->intf * CONFIG_STM32H7_ETH_NTXDESC]); + &g_txtable[priv->intf * CONFIG_STM32_ETH_NTXDESC]); /* Initialize RX Descriptors list */ stm32_rxdescinit(priv, - &g_rxtable[priv->intf * CONFIG_STM32H7_ETH_NRXDESC], + &g_rxtable[priv->intf * CONFIG_STM32_ETH_NRXDESC], &g_rxbuffer[priv->intf * RXBUFFER_SIZE]); /* Initialize the PHY */ -#ifdef CONFIG_STM32H7_NO_PHY +#ifdef CONFIG_STM32_NO_PHY ninfo("MAC without PHY\n"); -#ifdef CONFIG_STM32H7_ETHFD +#ifdef CONFIG_STM32_ETHFD priv->fduplex = 1; #else priv->fduplex = 0; #endif -#ifdef CONFIG_STM32H7_ETH100MBPS +#ifdef CONFIG_STM32_ETH100MBPS priv->mbps100 = 1; #else priv->mbps100 = 0; @@ -4120,7 +4120,7 @@ static int stm32_ethconfig(struct stm32_ethmac_s *priv) * ****************************************************************************/ -#if STM32H7_NETHERNET > 1 || defined(CONFIG_NETDEV_LATEINIT) +#if STM32_NETHERNET > 1 || defined(CONFIG_NETDEV_LATEINIT) int stm32_ethinitialize(int intf) #else static inline int stm32_ethinitialize(int intf) @@ -4135,7 +4135,7 @@ static inline int stm32_ethinitialize(int intf) /* Get the interface structure associated with this interface number. */ - DEBUGASSERT(intf < STM32H7_NETHERNET); + DEBUGASSERT(intf < STM32_NETHERNET); priv = &g_stm32ethmac[intf]; /* Initialize the driver structure */ @@ -4190,7 +4190,7 @@ static inline int stm32_ethinitialize(int intf) return -EAGAIN; } -#ifdef CONFIG_STM32H7_PHYINIT +#ifdef CONFIG_STM32_PHYINIT /* Perform any necessary, board-specific PHY initialization */ ret = stm32_phy_boardinitialize(0); @@ -4216,7 +4216,7 @@ static inline int stm32_ethinitialize(int intf) * * Description: * This is the "standard" network initialization logic called from the - * low-level initialization logic in arm_initialize.c. If STM32H7_NETHERNET + * low-level initialization logic in arm_initialize.c. If STM32_NETHERNET * greater than one, then board specific logic will have to supply a * version of arm_netinitialize() that calls stm32_ethinitialize() with * the appropriate interface number. @@ -4231,11 +4231,11 @@ static inline int stm32_ethinitialize(int intf) * ****************************************************************************/ -#if STM32H7_NETHERNET == 1 && !defined(CONFIG_NETDEV_LATEINIT) +#if STM32_NETHERNET == 1 && !defined(CONFIG_NETDEV_LATEINIT) void arm_netinitialize(void) { stm32_ethinitialize(0); } #endif -#endif /* STM32H7_NETHERNET > 0 && CONFIG_STM32H7_ETHMAC */ +#endif /* STM32_NETHERNET > 0 && CONFIG_STM32_ETHMAC */ diff --git a/arch/arm/src/stm32h7/stm32_ethernet.h b/arch/arm/src/stm32h7/stm32_ethernet.h index 6f7026bacacad..347beebab6677 100644 --- a/arch/arm/src/stm32h7/stm32_ethernet.h +++ b/arch/arm/src/stm32h7/stm32_ethernet.h @@ -31,7 +31,7 @@ #include "hardware/stm32_ethernet.h" -#if STM32H7_NETHERNET > 0 +#if STM32_NETHERNET > 0 #ifndef __ASSEMBLY__ /**************************************************************************** @@ -67,7 +67,7 @@ extern "C" * ****************************************************************************/ -#if STM32H7_NETHERNET > 1 || defined(CONFIG_NETDEV_LATEINIT) +#if STM32_NETHERNET > 1 || defined(CONFIG_NETDEV_LATEINIT) int stm32_ethinitialize(int intf); #endif @@ -77,7 +77,7 @@ int stm32_ethinitialize(int intf); * Description: * Some boards require specialized initialization of the PHY before it can * be used. This may include such things as configuring GPIOs, resetting - * the PHY, etc. If CONFIG_STM32H7_PHYINIT is defined in the configuration + * the PHY, etc. If CONFIG_STM32_PHYINIT is defined in the configuration * then the board specific logic must provide stm32_phyinitialize(); The * STM32 Ethernet driver will call this function one time before it first * uses the PHY. @@ -92,7 +92,7 @@ int stm32_ethinitialize(int intf); * ****************************************************************************/ -#ifdef CONFIG_STM32H7_PHYINIT +#ifdef CONFIG_STM32_PHYINIT int stm32_phy_boardinitialize(int intf); #endif @@ -102,5 +102,5 @@ int stm32_phy_boardinitialize(int intf); #endif #endif /* __ASSEMBLY__ */ -#endif /* STM32H7_NETHERNET > 0 */ +#endif /* STM32_NETHERNET > 0 */ #endif /* __ARCH_ARM_SRC_STM32H7_STM32_ETHERNET_H */ diff --git a/arch/arm/src/stm32h7/stm32_exti_gpio.c b/arch/arm/src/stm32h7/stm32_exti_gpio.c index 4b27006a665d3..74c8e812fc432 100644 --- a/arch/arm/src/stm32h7/stm32_exti_gpio.c +++ b/arch/arm/src/stm32h7/stm32_exti_gpio.c @@ -44,11 +44,11 @@ * families */ -#if defined(CONFIG_STM32H7_STM32H7X0XX) || \ - defined(CONFIG_STM32H7_STM32H7X3XX) || \ - defined(CONFIG_STM32H7_STM32H7B3XX) || \ - defined(CONFIG_STM32H7_STM32H7X5XX) || \ - defined(CONFIG_STM32H7_STM32H7X7XX) +#if defined(CONFIG_STM32_STM32H7X0XX) || \ + defined(CONFIG_STM32_STM32H7X3XX) || \ + defined(CONFIG_STM32_STM32H7B3XX) || \ + defined(CONFIG_STM32_STM32H7X5XX) || \ + defined(CONFIG_STM32_STM32H7X7XX) /**************************************************************************** * Private Types @@ -378,4 +378,4 @@ int stm32_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, return OK; } -#endif /* CONFIG_STM32H7_STM32H7X3XX || CONFIG_STM32H7_STM32H7X7XX || CONFIG_STM32H7_STM32H7B3XX */ +#endif /* CONFIG_STM32_STM32H7X3XX || CONFIG_STM32_STM32H7X7XX || CONFIG_STM32_STM32H7B3XX */ diff --git a/arch/arm/src/stm32h7/stm32_fdcan_sock.c b/arch/arm/src/stm32h7/stm32_fdcan_sock.c index 459f0204a8b90..15eecf55a7ec6 100644 --- a/arch/arm/src/stm32h7/stm32_fdcan_sock.c +++ b/arch/arm/src/stm32h7/stm32_fdcan_sock.c @@ -90,9 +90,9 @@ * critical Rx/Tx transactions on the CAN bus. */ -# if defined(CONFIG_STM32H7_FDCAN_HPWORK) +# if defined(CONFIG_STM32_FDCAN_HPWORK) # define CANWORK HPWORK -# elif defined(CONFIG_STM32H7_FDCAN_LPWORK) +# elif defined(CONFIG_STM32_FDCAN_LPWORK) # define CANWORK LPWORK # else # define CANWORK LPWORK @@ -326,7 +326,7 @@ struct fdcan_message_ram /* FDCAN device structures **************************************************/ -#ifdef CONFIG_STM32H7_FDCAN1 +#ifdef CONFIG_STM32_FDCAN1 static const struct fdcan_config_s stm32_fdcan0_config = { .tx_pin = GPIO_CAN1_TX, @@ -339,7 +339,7 @@ static const struct fdcan_config_s stm32_fdcan0_config = }; #endif -#ifdef CONFIG_STM32H7_FDCAN2 +#ifdef CONFIG_STM32_FDCAN2 static const struct fdcan_config_s stm32_fdcan1_config = { .tx_pin = GPIO_CAN2_TX, @@ -352,7 +352,7 @@ static const struct fdcan_config_s stm32_fdcan1_config = }; #endif -#ifdef CONFIG_STM32H7_FDCAN3 +#ifdef CONFIG_STM32_FDCAN3 static const struct fdcan_config_s stm32_fdcan2_config = { .tx_pin = GPIO_CAN3_TX, @@ -411,15 +411,15 @@ struct fdcan_driver_s * Private Data ****************************************************************************/ -#ifdef CONFIG_STM32H7_FDCAN1 +#ifdef CONFIG_STM32_FDCAN1 static struct fdcan_driver_s g_fdcan0; #endif -#ifdef CONFIG_STM32H7_FDCAN2 +#ifdef CONFIG_STM32_FDCAN2 static struct fdcan_driver_s g_fdcan1; #endif -#ifdef CONFIG_STM32H7_FDCAN3 +#ifdef CONFIG_STM32_FDCAN3 static struct fdcan_driver_s g_fdcan2; #endif @@ -437,7 +437,7 @@ static int fdcan_txpoll(struct net_driver_s *dev); /* Helper functions */ -#ifdef CONFIG_STM32H7_FDCAN_REGDEBUG +#ifdef CONFIG_STM32_FDCAN_REGDEBUG static void fdcan_dumpregs(struct fdcan_driver_s *priv); #endif @@ -511,7 +511,7 @@ static void fdcan_errint(struct fdcan_driver_s *priv, bool enable); * Dump common register values to the console for debugging purposes. ****************************************************************************/ -#ifdef CONFIG_STM32H7_FDCAN_REGDEBUG +#ifdef CONFIG_STM32_FDCAN_REGDEBUG static void fdcan_dumpregs(struct fdcan_driver_s *priv) { printf("-------------- FDCAN Reg Dump ----------------\n"); @@ -685,7 +685,7 @@ int32_t fdcan_bittiming(struct fdcan_bitseg *timing) return 3; /* Solution not found */ } -#ifdef CONFIG_STM32H7_FDCAN_REGDEBUG +#ifdef CONFIG_STM32_FDCAN_REGDEBUG ninfo("[fdcan] CLK_FREQ %lu, target_bitrate %lu, prescaler %lu, bs1 %d" ", bs2 %d\n", CLK_FREQ, target_bitrate, prescaler_bs, bs1 - 1, bs2 - 1); @@ -1803,7 +1803,7 @@ static int fdcan_ifup(struct net_driver_s *dev) fdcan_setinit(priv->base, 0); -#ifdef CONFIG_STM32H7_FDCAN_REGDEBUG +#ifdef CONFIG_STM32_FDCAN_REGDEBUG fdcan_dumpregs(priv); #endif @@ -2092,7 +2092,7 @@ int fdcan_initialize(struct fdcan_driver_s *priv) return -EIO; } -#ifdef CONFIG_STM32H7_FDCAN_REGDEBUG +#ifdef CONFIG_STM32_FDCAN_REGDEBUG const struct fdcan_bitseg *tim = &priv->arbi_timing; ninfo("[fdcan][arbi] Timings: presc=%u sjw=%u bs1=%u bs2=%u\r\n", tim->prescaler, tim->sjw, tim->bs1, tim->bs2); @@ -2116,7 +2116,7 @@ int fdcan_initialize(struct fdcan_driver_s *priv) return -EIO; } -#ifdef CONFIG_STM32H7_FDCAN_REGDEBUG +#ifdef CONFIG_STM32_FDCAN_REGDEBUG tim = &priv->data_timing; ninfo("[fdcan][data] Timings: presc=%u sjw=%u bs1=%u bs2=%u\r\n", tim->prescaler, tim->sjw, tim->bs1, tim->bs2); @@ -2136,14 +2136,14 @@ int fdcan_initialize(struct fdcan_driver_s *priv) /* Operation Configuration */ -#ifdef CONFIG_STM32H7_FDCAN_LOOPBACK +#ifdef CONFIG_STM32_FDCAN_LOOPBACK /* Enable External Loopback Mode (Rx pin disconnected) (RM0433 pg 2494) */ modifyreg32(priv->base + STM32_FDCAN_CCCR_OFFSET, 0, FDCAN_CCCR_TEST); modifyreg32(priv->base + STM32_FDCAN_TEST_OFFSET, 0, FDCAN_TEST_LBCK); #endif -#ifdef CONFIG_STM32H7_FDCAN_LOOPBACK_INTERNAL +#ifdef CONFIG_STM32_FDCAN_LOOPBACK_INTERNAL /* Enable Bus Monitoring / Restricted Op Mode (RM0433 pg 2492, 2494) */ modifyreg32(priv->base + STM32_FDCAN_CCCR_OFFSET, 0, FDCAN_CCCR_MON); @@ -2331,7 +2331,7 @@ int fdcan_initialize(struct fdcan_driver_s *priv) regval &= ~FDCAN_GFC_ANFE; /* Accept non-matching extid frames into FIFO0 */ putreg32(regval, priv->base + STM32_FDCAN_GFC_OFFSET); -#ifdef CONFIG_STM32H7_FDCAN_REGDEBUG +#ifdef CONFIG_STM32_FDCAN_REGDEBUG fdcan_dumpregs(priv); #endif @@ -2339,7 +2339,7 @@ int fdcan_initialize(struct fdcan_driver_s *priv) fdcan_setinit(priv->base, 0); -#ifdef CONFIG_STM32H7_FDCAN_REGDEBUG +#ifdef CONFIG_STM32_FDCAN_REGDEBUG fdcan_dumpregs(priv); #endif @@ -2395,7 +2395,7 @@ static void fdcan_reset(struct fdcan_driver_s *priv) { for (uint32_t i = 0; i < NUM_RX_FIFO0; i++) { - #ifdef CONFIG_STM32H7_FDCAN_REGDEBUG + #ifdef CONFIG_STM32_FDCAN_REGDEBUG ninfo("[fdcan] MB RX %i %p\r\n", i, &priv->rx[i]); #endif priv->rx[i].header.w1 = 0x0; @@ -2411,7 +2411,7 @@ static void fdcan_reset(struct fdcan_driver_s *priv) { for (uint32_t i = 0; i < NUM_TX_FIFO; i++) { - #ifdef CONFIG_STM32H7_FDCAN_REGDEBUG + #ifdef CONFIG_STM32_FDCAN_REGDEBUG ninfo("[fdcan] MB TX %i %p\r\n", i, &priv->tx[i]); #endif priv->tx[i].header.w1 = 0x0; @@ -2458,7 +2458,7 @@ int stm32_fdcansockinitialize(int intf) switch (intf) { -#ifdef CONFIG_STM32H7_FDCAN1 +#ifdef CONFIG_STM32_FDCAN1 case 0: priv = &g_fdcan0; memset(priv, 0, sizeof(struct fdcan_driver_s)); @@ -2477,7 +2477,7 @@ int stm32_fdcansockinitialize(int intf) break; #endif -#ifdef CONFIG_STM32H7_FDCAN2 +#ifdef CONFIG_STM32_FDCAN2 case 1: priv = &g_fdcan1; memset(priv, 0, sizeof(struct fdcan_driver_s)); @@ -2496,7 +2496,7 @@ int stm32_fdcansockinitialize(int intf) break; #endif -#ifdef CONFIG_STM32H7_FDCAN3 +#ifdef CONFIG_STM32_FDCAN3 case 2: priv = &g_fdcan2; memset(priv, 0, sizeof(struct fdcan_driver_s)); @@ -2579,7 +2579,7 @@ int stm32_fdcansockinitialize(int intf) netdev_register(&priv->dev, NET_LL_CAN); -#ifdef CONFIG_STM32H7_FDCAN_REGDEBUG +#ifdef CONFIG_STM32_FDCAN_REGDEBUG fdcan_dumpregs(priv); #endif @@ -2600,15 +2600,15 @@ int stm32_fdcansockinitialize(int intf) #if !defined(CONFIG_NETDEV_LATEINIT) void arm_netinitialize(void) { -#ifdef CONFIG_STM32H7_FDCAN1 +#ifdef CONFIG_STM32_FDCAN1 stm32_fdcansockinitialize(0); #endif -#ifdef CONFIG_STM32H7_FDCAN2 +#ifdef CONFIG_STM32_FDCAN2 stm32_fdcansockinitialize(1); #endif -#ifdef CONFIG_STM32H7_FDCAN3 +#ifdef CONFIG_STM32_FDCAN3 stm32_fdcansockinitialize(2); #endif } diff --git a/arch/arm/src/stm32h7/stm32_fdcan_sock.h b/arch/arm/src/stm32h7/stm32_fdcan_sock.h index 0c92ea109aebd..f5f66c31090de 100644 --- a/arch/arm/src/stm32h7/stm32_fdcan_sock.h +++ b/arch/arm/src/stm32h7/stm32_fdcan_sock.h @@ -31,7 +31,7 @@ #include "hardware/stm32_fdcan.h" -#ifdef CONFIG_STM32H7_FDCAN +#ifdef CONFIG_STM32_FDCAN /**************************************************************************** * Pre-processor Definitions @@ -105,5 +105,5 @@ int stm32_fdcansockinitialize(int intf); #endif #endif /* __ASSEMBLY__ */ -#endif /* CONFIG_STM32H7_FDCAN */ +#endif /* CONFIG_STM32_FDCAN */ #endif /* __ARCH_ARM_SRC_STM32H7_STM32_FDCAN_SOCK_H */ diff --git a/arch/arm/src/stm32h7/stm32_flash.c b/arch/arm/src/stm32h7/stm32_flash.c index 3a963bbc22bd4..c9afb10a3626d 100644 --- a/arch/arm/src/stm32h7/stm32_flash.c +++ b/arch/arm/src/stm32h7/stm32_flash.c @@ -26,15 +26,15 @@ #include -#if defined(CONFIG_STM32H7_STM32H7X0XX) +#if defined(CONFIG_STM32_STM32H7X0XX) # include "stm32h743xx_flash.c" -#elif defined(CONFIG_STM32H7_STM32H7X3XX) +#elif defined(CONFIG_STM32_STM32H7X3XX) # include "stm32h743xx_flash.c" -#elif defined(CONFIG_STM32H7_STM32H7B3XX) +#elif defined(CONFIG_STM32_STM32H7B3XX) # include "stm32h7b3xx_flash.c" -#elif defined(CONFIG_STM32H7_STM32H7X5XX) +#elif defined(CONFIG_STM32_STM32H7X5XX) # include "stm32h743xx_flash.c" -#elif defined(CONFIG_STM32H7_STM32H7X7XX) +#elif defined(CONFIG_STM32_STM32H7X7XX) # include "stm32h743xx_flash.c" #else # error "Unsupported STM32 H7 chip" diff --git a/arch/arm/src/stm32h7/stm32_flash.h b/arch/arm/src/stm32h7/stm32_flash.h index 39481210ddad1..cdd73d3b31ddc 100644 --- a/arch/arm/src/stm32h7/stm32_flash.h +++ b/arch/arm/src/stm32h7/stm32_flash.h @@ -48,27 +48,27 @@ extern "C" #endif /**************************************************************************** - * Name: stm32h7_flash_getopt + * Name: stm32_flash_getopt * * Description: * Returns the current flash option bytes from the FLASH_OPTSR_CR register. * ****************************************************************************/ -uint32_t stm32h7_flash_getopt(void); +uint32_t stm32_flash_getopt(void); /**************************************************************************** - * Name: stm32h7_flash_optmodify + * Name: stm32_flash_optmodify * * Description: * Modifies the current flash option bytes, given bits to set and clear. * ****************************************************************************/ -void stm32h7_flash_optmodify(uint32_t clear, uint32_t set); +void stm32_flash_optmodify(uint32_t clear, uint32_t set); /**************************************************************************** - * Name: stm32h7_flash_swapbanks + * Name: stm32_flash_swapbanks * * Description: * Swaps banks 1 and 2 in the processor's memory map. Takes effect @@ -76,37 +76,37 @@ void stm32h7_flash_optmodify(uint32_t clear, uint32_t set); * ****************************************************************************/ -void stm32h7_flash_swapbanks(void); +void stm32_flash_swapbanks(void); /**************************************************************************** - * Name: stm32h7_flash_lock + * Name: stm32_flash_lock * * Description: * Locks a bank * ****************************************************************************/ -int stm32h7_flash_lock(void); +int stm32_flash_lock(void); /**************************************************************************** - * Name: stm32h7_flash_unlock + * Name: stm32_flash_unlock * * Description: * Unlocks a bank * ****************************************************************************/ -int stm32h7_flash_unlock(void); +int stm32_flash_unlock(void); /**************************************************************************** - * Name: stm32h7_flash_writeprotect + * Name: stm32_flash_writeprotect * * Description: * Enable or disable the write protection of a flash sector. * ****************************************************************************/ -int stm32h7_flash_writeprotect(size_t page, bool enabled); +int stm32_flash_writeprotect(size_t page, bool enabled); #undef EXTERN #if defined(__cplusplus) diff --git a/arch/arm/src/stm32h7/stm32_fmc.c b/arch/arm/src/stm32h7/stm32_fmc.c index 841f2e6452567..1b790354b1801 100644 --- a/arch/arm/src/stm32h7/stm32_fmc.c +++ b/arch/arm/src/stm32h7/stm32_fmc.c @@ -26,7 +26,7 @@ #include -#if defined(CONFIG_STM32H7_FMC) +#if defined(CONFIG_STM32_FMC) #include "stm32.h" @@ -41,7 +41,7 @@ /**************************************************************************** * To use FMC, you must first enable it in configuration: * - * CONFIG_STM32H7_FMC=y + * CONFIG_STM32_FMC=y * * FMC is statically configured at startup. Its configuration is adjusted * using BOARD_XXX macros described below, which should be declared @@ -549,4 +549,4 @@ void stm32_fmc_sdram_command(uint32_t cmd) putreg32(cmd, STM32_FMC_SDCMR); } -#endif /* CONFIG_STM32H7_FMC */ +#endif /* CONFIG_STM32_FMC */ diff --git a/arch/arm/src/stm32h7/stm32_gpio.c b/arch/arm/src/stm32h7/stm32_gpio.c index 8f59ef8b8a8c9..77bcccbc4ea66 100644 --- a/arch/arm/src/stm32h7/stm32_gpio.c +++ b/arch/arm/src/stm32h7/stm32_gpio.c @@ -44,11 +44,11 @@ * families */ -#if defined(CONFIG_STM32H7_STM32H7X0XX) || \ - defined(CONFIG_STM32H7_STM32H7X3XX) || \ - defined(CONFIG_STM32H7_STM32H7B3XX) || \ - defined(CONFIG_STM32H7_STM32H7X5XX) || \ - defined(CONFIG_STM32H7_STM32H7X7XX) +#if defined(CONFIG_STM32_STM32H7X0XX) || \ + defined(CONFIG_STM32_STM32H7X3XX) || \ + defined(CONFIG_STM32_STM32H7B3XX) || \ + defined(CONFIG_STM32_STM32H7X5XX) || \ + defined(CONFIG_STM32_STM32H7X7XX) /**************************************************************************** * Private Data @@ -62,47 +62,47 @@ static spinlock_t g_configgpio_lock = SP_UNLOCKED; /* Base addresses for each GPIO block */ -const uint32_t g_gpiobase[STM32H7_NGPIO] = +const uint32_t g_gpiobase[STM32_NGPIO] = { -#if STM32H7_NGPIO > 0 +#if STM32_NGPIO > 0 STM32_GPIOA_BASE, #endif -#if STM32H7_NGPIO > 1 +#if STM32_NGPIO > 1 STM32_GPIOB_BASE, #endif -#if STM32H7_NGPIO > 2 +#if STM32_NGPIO > 2 STM32_GPIOC_BASE, #endif -#if STM32H7_NGPIO > 3 +#if STM32_NGPIO > 3 STM32_GPIOD_BASE, #endif -#if STM32H7_NGPIO > 4 +#if STM32_NGPIO > 4 STM32_GPIOE_BASE, #endif -#if STM32H7_NGPIO > 5 -# if defined(CONFIG_STM32H7_HAVE_GPIOF) +#if STM32_NGPIO > 5 +# if defined(CONFIG_STM32_HAVE_GPIOF) STM32_GPIOF_BASE, # else 0, # endif #endif -#if STM32H7_NGPIO > 6 -# if defined(CONFIG_STM32H7_HAVE_GPIOG) +#if STM32_NGPIO > 6 +# if defined(CONFIG_STM32_HAVE_GPIOG) STM32_GPIOG_BASE, # else 0, # endif #endif -#if STM32H7_NGPIO > 7 +#if STM32_NGPIO > 7 STM32_GPIOH_BASE, #endif -#if STM32H7_NGPIO > 8 +#if STM32_NGPIO > 8 STM32_GPIOI_BASE, #endif -#if STM32H7_NGPIO > 9 +#if STM32_NGPIO > 9 STM32_GPIOJ_BASE, #endif -#if STM32H7_NGPIO > 10 +#if STM32_NGPIO > 10 STM32_GPIOK_BASE, #endif }; @@ -163,7 +163,7 @@ int stm32_configgpio(uint32_t cfgset) /* Verify that this hardware supports the select GPIO port */ port = (cfgset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; - if (port >= STM32H7_NGPIO) + if (port >= STM32_NGPIO) { return -EINVAL; } @@ -443,7 +443,7 @@ void stm32_gpiowrite(uint32_t pinset, bool value) unsigned int pin; port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; - if (port < STM32H7_NGPIO) + if (port < STM32_NGPIO) { /* Get the port base address */ @@ -485,7 +485,7 @@ bool stm32_gpioread(uint32_t pinset) unsigned int pin; port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; - if (port < STM32H7_NGPIO) + if (port < STM32_NGPIO) { /* Get the port base address */ @@ -526,7 +526,7 @@ bool stm32_gpioread(uint32_t pinset) * ****************************************************************************/ -#ifdef CONFIG_STM32H7_SYSCFG_IOCOMPENSATION +#ifdef CONFIG_STM32_SYSCFG_IOCOMPENSATION void stm32_iocompensation(void) { /* Enable I/O Compensation. Writing '1' to the CMPCR power-down bit @@ -543,4 +543,4 @@ void stm32_iocompensation(void) } #endif -#endif /* CONFIG_STM32H7_STM32H7X3XX || CONFIG_STM32H7_STM32H7X7XX || CONFIG_STM32H7_STM32H7B3XX */ +#endif /* CONFIG_STM32_STM32H7X3XX || CONFIG_STM32_STM32H7X7XX || CONFIG_STM32_STM32H7B3XX */ diff --git a/arch/arm/src/stm32h7/stm32_gpio.h b/arch/arm/src/stm32h7/stm32_gpio.h index 02a644c3290bf..18ce28cc321ea 100644 --- a/arch/arm/src/stm32h7/stm32_gpio.h +++ b/arch/arm/src/stm32h7/stm32_gpio.h @@ -184,37 +184,37 @@ #define GPIO_PORT_SHIFT (4) /* Bit 4-7: Port number */ #define GPIO_PORT_MASK (15 << GPIO_PORT_SHIFT) -#if STM32H7_NGPIO > 0 +#if STM32_NGPIO > 0 # define GPIO_PORTA (0 << GPIO_PORT_SHIFT) /* GPIOA */ #endif -#if STM32H7_NGPIO > 1 +#if STM32_NGPIO > 1 # define GPIO_PORTB (1 << GPIO_PORT_SHIFT) /* GPIOB */ #endif -#if STM32H7_NGPIO > 2 +#if STM32_NGPIO > 2 # define GPIO_PORTC (2 << GPIO_PORT_SHIFT) /* GPIOC */ #endif -#if STM32H7_NGPIO > 3 +#if STM32_NGPIO > 3 # define GPIO_PORTD (3 << GPIO_PORT_SHIFT) /* GPIOD */ #endif -#if STM32H7_NGPIO > 4 +#if STM32_NGPIO > 4 # define GPIO_PORTE (4 << GPIO_PORT_SHIFT) /* GPIOE */ #endif -#if (STM32H7_NGPIO > 5) && (defined(CONFIG_STM32H7_HAVE_GPIOF)) +#if (STM32_NGPIO > 5) && (defined(CONFIG_STM32_HAVE_GPIOF)) # define GPIO_PORTF (5 << GPIO_PORT_SHIFT) /* GPIOF */ #endif -#if (STM32H7_NGPIO > 6) && (defined(CONFIG_STM32H7_HAVE_GPIOG)) +#if (STM32_NGPIO > 6) && (defined(CONFIG_STM32_HAVE_GPIOG)) # define GPIO_PORTG (6 << GPIO_PORT_SHIFT) /* GPIOG */ #endif -#if STM32H7_NGPIO > 7 +#if STM32_NGPIO > 7 # define GPIO_PORTH (7 << GPIO_PORT_SHIFT) /* GPIOH */ #endif -#if STM32H7_NGPIO > 8 +#if STM32_NGPIO > 8 # define GPIO_PORTI (8 << GPIO_PORT_SHIFT) /* GPIOI */ #endif -#if STM32H7_NGPIO > 9 +#if STM32_NGPIO > 9 # define GPIO_PORTJ (9 << GPIO_PORT_SHIFT) /* GPIOJ */ #endif -#if STM32H7_NGPIO > 10 +#if STM32_NGPIO > 10 # define GPIO_PORTK (10 << GPIO_PORT_SHIFT) /* GPIOK */ #endif @@ -262,7 +262,7 @@ extern "C" /* Base addresses for each GPIO block */ -EXTERN const uint32_t g_gpiobase[STM32H7_NGPIO]; +EXTERN const uint32_t g_gpiobase[STM32_NGPIO]; /**************************************************************************** * Public Function Prototypes @@ -350,7 +350,7 @@ bool stm32_gpioread(uint32_t pinset); * ****************************************************************************/ -#ifdef CONFIG_STM32H7_SYSCFG_IOCOMPENSATION +#ifdef CONFIG_STM32_SYSCFG_IOCOMPENSATION void stm32_iocompensation(void); #endif diff --git a/arch/arm/src/stm32h7/stm32_i2c.c b/arch/arm/src/stm32h7/stm32_i2c.c index 9b7cdc9df2f87..e01dd136a21bc 100644 --- a/arch/arm/src/stm32h7/stm32_i2c.c +++ b/arch/arm/src/stm32h7/stm32_i2c.c @@ -156,28 +156,28 @@ * * One of: * - * CONFIG_STM32H7_STM32H7X3XX + * CONFIG_STM32_STM32H7X3XX * * and one or more interfaces: * - * CONFIG_STM32H7_I2C1 - * CONFIG_STM32H7_I2C2 - * CONFIG_STM32H7_I2C3 - * CONFIG_STM32H7_I2C4 + * CONFIG_STM32_I2C1 + * CONFIG_STM32_I2C2 + * CONFIG_STM32_I2C3 + * CONFIG_STM32_I2C4 * * To configure the ISR timeout using fixed values - * (CONFIG_STM32H7_I2C_DYNTIMEO=n): + * (CONFIG_STM32_I2C_DYNTIMEO=n): * - * CONFIG_STM32H7_I2CTIMEOSEC (Timeout in seconds) - * CONFIG_STM32H7_I2CTIMEOMS (Timeout in milliseconds) - * CONFIG_STM32H7_I2CTIMEOTICKS (Timeout in ticks) + * CONFIG_STM32_I2CTIMEOSEC (Timeout in seconds) + * CONFIG_STM32_I2CTIMEOMS (Timeout in milliseconds) + * CONFIG_STM32_I2CTIMEOTICKS (Timeout in ticks) * * To configure the ISR timeout using dynamic values - * (CONFIG_STM32H7_I2C_DYNTIMEO=y): + * (CONFIG_STM32_I2C_DYNTIMEO=y): * - * CONFIG_STM32H7_I2C_DYNTIMEO_USECPERBYTE + * CONFIG_STM32_I2C_DYNTIMEO_USECPERBYTE * (Timeout in microseconds per byte) - * CONFIG_STM32H7_I2C_DYNTIMEO_STARTSTOP + * CONFIG_STM32_I2C_DYNTIMEO_STARTSTOP * (Timeout for start/stop in msec) * * Debugging output enabled with: @@ -225,8 +225,8 @@ /* At least one I2C peripheral must be enabled */ -#if defined(CONFIG_STM32H7_I2C1) || defined(CONFIG_STM32H7_I2C2) || \ - defined(CONFIG_STM32H7_I2C3) || defined(CONFIG_STM32H7_I2C4) +#if defined(CONFIG_STM32_I2C1) || defined(CONFIG_STM32_I2C2) || \ + defined(CONFIG_STM32_I2C3) || defined(CONFIG_STM32_I2C4) /**************************************************************************** * Pre-processor Definitions @@ -234,14 +234,14 @@ #undef INVALID_CLOCK_SOURCE -#if defined(CONFIG_STM32H7_I2C1) || defined(CONFIG_STM32H7_I2C2) || \ - defined(CONFIG_STM32H7_I2C3) +#if defined(CONFIG_STM32_I2C1) || defined(CONFIG_STM32_I2C2) || \ + defined(CONFIG_STM32_I2C3) # if STM32_RCC_D2CCIP2R_I2C123SRC != RCC_D2CCIP2R_I2C123SEL_HSI # warning "Clock Source STM32_RCC_D2CCIP2R_I2C123SRC must be HSI" # define INVALID_CLOCK_SOURCE # endif #endif -#ifdef CONFIG_STM32H7_I2C4 +#ifdef CONFIG_STM32_I2C4 # if STM32_RCC_D3CCIPR_I2C4SRC != RCC_D3CCIPR_I2C4SEL_HSI # warning "Clock Source STM32_RCC_D3CCIPR_I2C4SRC must be HSI" # define INVALID_CLOCK_SOURCE @@ -258,25 +258,25 @@ /* Interrupt wait timeout in seconds and milliseconds */ -#if !defined(CONFIG_STM32H7_I2CTIMEOSEC) && !defined(CONFIG_STM32H7_I2CTIMEOMS) -# define CONFIG_STM32H7_I2CTIMEOSEC 0 -# define CONFIG_STM32H7_I2CTIMEOMS 500 /* Default is 500 milliseconds */ +#if !defined(CONFIG_STM32_I2CTIMEOSEC) && !defined(CONFIG_STM32_I2CTIMEOMS) +# define CONFIG_STM32_I2CTIMEOSEC 0 +# define CONFIG_STM32_I2CTIMEOMS 500 /* Default is 500 milliseconds */ # warning "Using Default 500 Ms Timeout" -#elif !defined(CONFIG_STM32H7_I2CTIMEOSEC) -# define CONFIG_STM32H7_I2CTIMEOSEC 0 /* User provided milliseconds */ -#elif !defined(CONFIG_STM32H7_I2CTIMEOMS) -# define CONFIG_STM32H7_I2CTIMEOMS 0 /* User provided seconds */ +#elif !defined(CONFIG_STM32_I2CTIMEOSEC) +# define CONFIG_STM32_I2CTIMEOSEC 0 /* User provided milliseconds */ +#elif !defined(CONFIG_STM32_I2CTIMEOMS) +# define CONFIG_STM32_I2CTIMEOMS 0 /* User provided seconds */ #endif /* Interrupt wait time timeout in system timer ticks */ -#ifndef CONFIG_STM32H7_I2CTIMEOTICKS -# define CONFIG_STM32H7_I2CTIMEOTICKS \ - (SEC2TICK(CONFIG_STM32H7_I2CTIMEOSEC) + MSEC2TICK(CONFIG_STM32H7_I2CTIMEOMS)) +#ifndef CONFIG_STM32_I2CTIMEOTICKS +# define CONFIG_STM32_I2CTIMEOTICKS \ + (SEC2TICK(CONFIG_STM32_I2CTIMEOSEC) + MSEC2TICK(CONFIG_STM32_I2CTIMEOMS)) #endif -#ifndef CONFIG_STM32H7_I2C_DYNTIMEO_STARTSTOP -# define CONFIG_STM32H7_I2C_DYNTIMEO_STARTSTOP TICK2USEC(CONFIG_STM32H7_I2CTIMEOTICKS) +#ifndef CONFIG_STM32_I2C_DYNTIMEO_STARTSTOP +# define CONFIG_STM32_I2C_DYNTIMEO_STARTSTOP TICK2USEC(CONFIG_STM32_I2CTIMEOTICKS) #endif /* Macros to convert a I2C pin to a GPIO output */ @@ -446,9 +446,9 @@ static inline void stm32_i2c_putreg32(struct stm32_i2c_priv_s *priv, static inline void stm32_i2c_modifyreg32(struct stm32_i2c_priv_s *priv, uint8_t offset, uint32_t clearbits, uint32_t setbits); -#ifdef CONFIG_STM32H7_I2C_DYNTIMEO +#ifdef CONFIG_STM32_I2C_DYNTIMEO static uint32_t stm32_i2c_toticks(int msgc, struct i2c_msg_s *msgs); -#endif /* CONFIG_STM32H7_I2C_DYNTIMEO */ +#endif /* CONFIG_STM32_I2C_DYNTIMEO */ static inline int stm32_i2c_sem_waitdone(struct stm32_i2c_priv_s *priv); static inline void stm32_i2c_sem_waitstop(struct stm32_i2c_priv_s *priv); #ifdef CONFIG_I2C_TRACE @@ -488,7 +488,7 @@ static int stm32_i2c_pm_prepare(struct pm_callback_s *cb, int domain, * Private Data ****************************************************************************/ -#ifdef CONFIG_STM32H7_I2C1 +#ifdef CONFIG_STM32_I2C1 static const struct stm32_i2c_config_s stm32_i2c1_config = { .base = STM32_I2C1_BASE, @@ -524,7 +524,7 @@ static struct stm32_i2c_priv_s stm32_i2c1_priv = }; #endif -#ifdef CONFIG_STM32H7_I2C2 +#ifdef CONFIG_STM32_I2C2 static const struct stm32_i2c_config_s stm32_i2c2_config = { .base = STM32_I2C2_BASE, @@ -560,7 +560,7 @@ static struct stm32_i2c_priv_s stm32_i2c2_priv = }; #endif -#ifdef CONFIG_STM32H7_I2C3 +#ifdef CONFIG_STM32_I2C3 static const struct stm32_i2c_config_s stm32_i2c3_config = { .base = STM32_I2C3_BASE, @@ -596,7 +596,7 @@ static struct stm32_i2c_priv_s stm32_i2c3_priv = }; #endif -#ifdef CONFIG_STM32H7_I2C4 +#ifdef CONFIG_STM32_I2C4 static const struct stm32_i2c_config_s stm32_i2c4_config = { .base = STM32_I2C4_BASE, @@ -726,7 +726,7 @@ static inline void stm32_i2c_modifyreg32(struct stm32_i2c_priv_s *priv, * ****************************************************************************/ -#ifdef CONFIG_STM32H7_I2C_DYNTIMEO +#ifdef CONFIG_STM32_I2C_DYNTIMEO static uint32_t stm32_i2c_toticks(int msgc, struct i2c_msg_s *msgs) { size_t bytecount = 0; @@ -743,7 +743,7 @@ static uint32_t stm32_i2c_toticks(int msgc, struct i2c_msg_s *msgs) * factor. */ - return USEC2TICK(CONFIG_STM32H7_I2C_DYNTIMEO_USECPERBYTE * bytecount); + return USEC2TICK(CONFIG_STM32_I2C_DYNTIMEO_USECPERBYTE * bytecount); } #endif @@ -799,12 +799,12 @@ static inline int stm32_i2c_sem_waitdone(struct stm32_i2c_priv_s *priv) { /* Wait until either the transfer is complete or the timeout expires */ -#ifdef CONFIG_STM32H7_I2C_DYNTIMEO +#ifdef CONFIG_STM32_I2C_DYNTIMEO ret = nxsem_tickwait_uninterruptible(&priv->sem_isr, stm32_i2c_toticks(priv->msgc, priv->msgv)); #else ret = nxsem_tickwait_uninterruptible(&priv->sem_isr, - CONFIG_STM32H7_I2CTIMEOTICKS); + CONFIG_STM32_I2CTIMEOTICKS); #endif if (ret < 0) { @@ -842,10 +842,10 @@ static inline int stm32_i2c_sem_waitdone(struct stm32_i2c_priv_s *priv) /* Get the timeout value */ -#ifdef CONFIG_STM32H7_I2C_DYNTIMEO +#ifdef CONFIG_STM32_I2C_DYNTIMEO timeout = stm32_i2c_toticks(priv->msgc, priv->msgv); #else - timeout = CONFIG_STM32H7_I2CTIMEOTICKS; + timeout = CONFIG_STM32_I2CTIMEOTICKS; #endif /* Signal the interrupt handler that we are waiting. NOTE: Interrupts @@ -983,10 +983,10 @@ static inline void stm32_i2c_sem_waitstop(struct stm32_i2c_priv_s *priv) /* Select a timeout */ -#ifdef CONFIG_STM32H7_I2C_DYNTIMEO - timeout = USEC2TICK(CONFIG_STM32H7_I2C_DYNTIMEO_STARTSTOP); +#ifdef CONFIG_STM32_I2C_DYNTIMEO + timeout = USEC2TICK(CONFIG_STM32_I2C_DYNTIMEO_STARTSTOP); #else - timeout = CONFIG_STM32H7_I2CTIMEOTICKS; + timeout = CONFIG_STM32_I2CTIMEOTICKS; #endif /* Wait as stop might still be in progress */ @@ -2715,22 +2715,22 @@ struct i2c_master_s *stm32_i2cbus_initialize(int port) switch (port) { -#ifdef CONFIG_STM32H7_I2C1 +#ifdef CONFIG_STM32_I2C1 case 1: priv = (struct stm32_i2c_priv_s *)&stm32_i2c1_priv; break; #endif -#ifdef CONFIG_STM32H7_I2C2 +#ifdef CONFIG_STM32_I2C2 case 2: priv = (struct stm32_i2c_priv_s *)&stm32_i2c2_priv; break; #endif -#ifdef CONFIG_STM32H7_I2C3 +#ifdef CONFIG_STM32_I2C3 case 3: priv = (struct stm32_i2c_priv_s *)&stm32_i2c3_priv; break; #endif -#ifdef CONFIG_STM32H7_I2C4 +#ifdef CONFIG_STM32_I2C4 case 4: priv = (struct stm32_i2c_priv_s *)&stm32_i2c4_priv; break; @@ -2816,5 +2816,5 @@ int stm32_i2cbus_uninitialize(struct i2c_master_s *dev) return OK; } -#endif /* CONFIG_STM32H7_I2C1 || CONFIG_STM32H7_I2C2 || \ - * CONFIG_STM32H7_I2C3 || CONFIG_STM32H7_I2C4 */ +#endif /* CONFIG_STM32_I2C1 || CONFIG_STM32_I2C2 || \ + * CONFIG_STM32_I2C3 || CONFIG_STM32_I2C4 */ diff --git a/arch/arm/src/stm32h7/stm32_i2c.h b/arch/arm/src/stm32h7/stm32_i2c.h index ae507efe60351..78dc96b1ba537 100644 --- a/arch/arm/src/stm32h7/stm32_i2c.h +++ b/arch/arm/src/stm32h7/stm32_i2c.h @@ -41,10 +41,10 @@ * seconds per byte value must be provided as well. */ -#ifdef CONFIG_STM32H7_I2C_DYNTIMEO -# if CONFIG_STM32H7_I2C_DYNTIMEO_USECPERBYTE < 1 -# warning "Ignoring CONFIG_STM32H7_I2C_DYNTIMEO because of CONFIG_STM32H7_I2C_DYNTIMEO_USECPERBYTE" -# undef CONFIG_STM32H7_I2C_DYNTIMEO +#ifdef CONFIG_STM32_I2C_DYNTIMEO +# if CONFIG_STM32_I2C_DYNTIMEO_USECPERBYTE < 1 +# warning "Ignoring CONFIG_STM32_I2C_DYNTIMEO because of CONFIG_STM32_I2C_DYNTIMEO_USECPERBYTE" +# undef CONFIG_STM32_I2C_DYNTIMEO # endif #endif diff --git a/arch/arm/src/stm32h7/stm32_irq.c b/arch/arm/src/stm32h7/stm32_irq.c index 2bcf4b9cc7e68..37da642357f29 100644 --- a/arch/arm/src/stm32h7/stm32_irq.c +++ b/arch/arm/src/stm32h7/stm32_irq.c @@ -40,7 +40,7 @@ #include "ram_vectors.h" #include "arm_internal.h" -#ifdef CONFIG_STM32H7_GPIO_IRQ +#ifdef CONFIG_STM32_GPIO_IRQ # include "stm32_gpio.h" #endif @@ -404,7 +404,7 @@ void up_irqinitialize(void) * GPIO pins. */ -#ifdef CONFIG_STM32H7_GPIO_IRQ +#ifdef CONFIG_STM32_GPIO_IRQ stm32_gpioirqinitialize(); #endif @@ -448,7 +448,7 @@ void up_disable_irq(int irq) putreg32(regval, regaddr); } } -#ifdef CONFIG_STM32H7_GPIO_IRQ +#ifdef CONFIG_STM32_GPIO_IRQ else { /* Maybe it is a (derived) GPIO IRQ */ @@ -495,7 +495,7 @@ void up_enable_irq(int irq) putreg32(regval, regaddr); } } -#ifdef CONFIG_STM32H7_GPIO_IRQ +#ifdef CONFIG_STM32_GPIO_IRQ else { /* Maybe it is a (derived) GPIO IRQ */ diff --git a/arch/arm/src/stm32h7/stm32_iwdg.c b/arch/arm/src/stm32h7/stm32_iwdg.c index 13150c3943150..299b40ae68e4a 100644 --- a/arch/arm/src/stm32h7/stm32_iwdg.c +++ b/arch/arm/src/stm32h7/stm32_iwdg.c @@ -41,7 +41,7 @@ #include "stm32_rcc.h" #include "stm32_wdg.h" -#if defined(CONFIG_WATCHDOG) && defined(CONFIG_STM32H7_IWDG) +#if defined(CONFIG_WATCHDOG) && defined(CONFIG_STM32_IWDG) /**************************************************************************** * Pre-processor Definitions @@ -69,12 +69,12 @@ /* Configuration ************************************************************/ -#ifndef CONFIG_STM32H7_IWDG_DEFTIMOUT -# define CONFIG_STM32H7_IWDG_DEFTIMOUT IWDG_MAXTIMEOUT +#ifndef CONFIG_STM32_IWDG_DEFTIMOUT +# define CONFIG_STM32_IWDG_DEFTIMOUT IWDG_MAXTIMEOUT #endif #ifndef CONFIG_DEBUG_WATCHDOG_INFO -# undef CONFIG_STM32H7_IWDG_REGDEBUG +# undef CONFIG_STM32_IWDG_REGDEBUG #endif /* REVISIT: It appears that you can only setup the prescaler and reload @@ -83,19 +83,19 @@ * is started, then refuse any further attempts to change timeout. */ -#define CONFIG_STM32H7_IWDG_ONETIMESETUP 1 +#define CONFIG_STM32_IWDG_ONETIMESETUP 1 /* REVISIT: Another possibility is that we CAN change the prescaler and * reload values after starting the timer. This option is untested but the * implementation place conditioned on the following: */ -#undef CONFIG_STM32H7_IWDG_DEFERREDSETUP +#undef CONFIG_STM32_IWDG_DEFERREDSETUP /* But you can only try one at a time */ -#if defined(CONFIG_STM32H7_IWDG_ONETIMESETUP) && defined(CONFIG_STM32H7_IWDG_DEFERREDSETUP) -# error "Both CONFIG_STM32H7_IWDG_ONETIMESETUP and CONFIG_STM32H7_IWDG_DEFERREDSETUP are defined" +#if defined(CONFIG_STM32_IWDG_ONETIMESETUP) && defined(CONFIG_STM32_IWDG_DEFERREDSETUP) +# error "Both CONFIG_STM32_IWDG_ONETIMESETUP and CONFIG_STM32_IWDG_DEFERREDSETUP are defined" #endif /**************************************************************************** @@ -124,7 +124,7 @@ struct stm32_lowerhalf_s /* Register operations ******************************************************/ -#ifdef CONFIG_STM32H7_IWDG_REGDEBUG +#ifdef CONFIG_STM32_IWDG_REGDEBUG static uint16_t stm32_getreg(uint32_t addr); static void stm32_putreg(uint16_t val, uint32_t addr); #else @@ -177,7 +177,7 @@ static struct stm32_lowerhalf_s g_wdgdev; * ****************************************************************************/ -#ifdef CONFIG_STM32H7_IWDG_REGDEBUG +#ifdef CONFIG_STM32_IWDG_REGDEBUG static uint16_t stm32_getreg(uint32_t addr) { static uint32_t prevaddr = 0; @@ -240,7 +240,7 @@ static uint16_t stm32_getreg(uint32_t addr) * ****************************************************************************/ -#ifdef CONFIG_STM32H7_IWDG_REGDEBUG +#ifdef CONFIG_STM32_IWDG_REGDEBUG static void stm32_putreg(uint16_t val, uint32_t addr) { /* Show the register value being written */ @@ -280,7 +280,7 @@ static inline void stm32_setprescaler(struct stm32_lowerhalf_s *priv) * be necessary. */ -#ifndef CONFIG_STM32H7_IWDG_ONETIMESETUP +#ifndef CONFIG_STM32_IWDG_ONETIMESETUP while ((stm32_getreg(STM32_IWDG_SR) & (IWDG_SR_PVU | IWDG_SR_RVU)) != 0); #endif @@ -335,7 +335,7 @@ static int stm32_start(struct watchdog_lowerhalf_s *lower) * starting the watchdog timer. */ -#if defined(CONFIG_STM32H7_IWDG_ONETIMESETUP) || defined(CONFIG_STM32H7_IWDG_DEFERREDSETUP) +#if defined(CONFIG_STM32_IWDG_ONETIMESETUP) || defined(CONFIG_STM32_IWDG_DEFERREDSETUP) stm32_setprescaler(priv); #endif @@ -512,7 +512,7 @@ static int stm32_settimeout(struct watchdog_lowerhalf_s *lower, * to zero. */ -#ifdef CONFIG_STM32H7_IWDG_ONETIMESETUP +#ifdef CONFIG_STM32_IWDG_ONETIMESETUP if (priv->started) { wdwarn("WARNING: Timer is already started\n"); @@ -597,12 +597,12 @@ static int stm32_settimeout(struct watchdog_lowerhalf_s *lower, * to zero. */ -#ifndef CONFIG_STM32H7_IWDG_ONETIMESETUP - /* If CONFIG_STM32H7_IWDG_DEFERREDSETUP is selected, then perform the +#ifndef CONFIG_STM32_IWDG_ONETIMESETUP + /* If CONFIG_STM32_IWDG_DEFERREDSETUP is selected, then perform the * register configuration only if the timer has been started. */ -#ifdef CONFIG_STM32H7_IWDG_DEFERREDSETUP +#ifdef CONFIG_STM32_IWDG_DEFERREDSETUP if (priv->started) #endif { @@ -670,7 +670,7 @@ void stm32_iwdginitialize(const char *devpath, uint32_t lsifreq) */ stm32_settimeout((struct watchdog_lowerhalf_s *)priv, - CONFIG_STM32H7_IWDG_DEFTIMOUT); + CONFIG_STM32_IWDG_DEFTIMOUT); /* Register the watchdog driver as /dev/watchdog0 */ @@ -681,9 +681,9 @@ void stm32_iwdginitialize(const char *devpath, uint32_t lsifreq) * on DBG_IWDG_STOP configuration bit in DBG module. */ -#if defined(CONFIG_STM32H7_JTAG_FULL_ENABLE) || \ - defined(CONFIG_STM32H7_JTAG_NOJNTRST_ENABLE) || \ - defined(CONFIG_STM32H7_JTAG_SW_ENABLE) +#if defined(CONFIG_STM32_JTAG_FULL_ENABLE) || \ + defined(CONFIG_STM32_JTAG_NOJNTRST_ENABLE) || \ + defined(CONFIG_STM32_JTAG_SW_ENABLE) { uint32_t cr = getreg32(STM32_DBGMCU_APB4_FZ1); cr |= DBGMCU_APB4_WDGLSD1; @@ -692,4 +692,4 @@ void stm32_iwdginitialize(const char *devpath, uint32_t lsifreq) #endif } -#endif /* CONFIG_WATCHDOG && CONFIG_STM32H7_IWDG */ +#endif /* CONFIG_WATCHDOG && CONFIG_STM32_IWDG */ diff --git a/arch/arm/src/stm32h7/stm32_lptim.c b/arch/arm/src/stm32h7/stm32_lptim.c index daa7bc8029f3f..958243f7631c5 100644 --- a/arch/arm/src/stm32h7/stm32_lptim.c +++ b/arch/arm/src/stm32h7/stm32_lptim.c @@ -43,9 +43,9 @@ #include "stm32_gpio.h" #include "stm32_lptim.h" -#if defined(CONFIG_STM32H7_LPTIM1) || defined(CONFIG_STM32H7_LPTIM2) || \ - defined(CONFIG_STM32H7_LPTIM3) || defined(CONFIG_STM32H7_LPTIM4) || \ - defined(CONFIG_STM32H7_LPTIM5) +#if defined(CONFIG_STM32_LPTIM1) || defined(CONFIG_STM32_LPTIM2) || \ + defined(CONFIG_STM32_LPTIM3) || defined(CONFIG_STM32_LPTIM4) || \ + defined(CONFIG_STM32_LPTIM5) /**************************************************************************** * Private Function prototypes @@ -103,35 +103,35 @@ static const struct stm32_lptim_ops_s stm32_lptim_ops = .ackint = &stm32_lptim_ackint }; -#ifdef CONFIG_STM32H7_LPTIM1 +#ifdef CONFIG_STM32_LPTIM1 struct stm32_lptim_dev_s stm32_lptim1_priv = { .ops = &stm32_lptim_ops, .base = STM32_LPTIM1_BASE, }; #endif -#ifdef CONFIG_STM32H7_LPTIM2 +#ifdef CONFIG_STM32_LPTIM2 struct stm32_lptim_dev_s stm32_lptim2_priv = { .ops = &stm32_lptim_ops, .base = STM32_LPTIM2_BASE, }; #endif -#ifdef CONFIG_STM32H7_LPTIM3 +#ifdef CONFIG_STM32_LPTIM3 struct stm32_lptim_dev_s stm32_lptim3_priv = { .ops = &stm32_lptim_ops, .base = STM32_LPTIM3_BASE, }; #endif -#ifdef CONFIG_STM32H7_LPTIM4 +#ifdef CONFIG_STM32_LPTIM4 struct stm32_lptim_dev_s stm32_lptim4_priv = { .ops = &stm32_lptim_ops, .base = STM32_LPTIM4_BASE, }; #endif -#ifdef CONFIG_STM32H7_LPTIM5 +#ifdef CONFIG_STM32_LPTIM5 struct stm32_lptim_dev_s stm32_lptim5_priv = { .ops = &stm32_lptim_ops, @@ -205,7 +205,7 @@ static int stm32_lptim_setinput(struct stm32_lptim_dev_s *dev, { switch (dev->base) { -#if defined(CONFIG_STM32H7_LPTIM1) || defined(CONFIG_STM32H7_LPTIM2) +#if defined(CONFIG_STM32_LPTIM1) || defined(CONFIG_STM32_LPTIM2) case STM32_LPTIM1_BASE: case STM32_LPTIM2_BASE: if (input == 0) @@ -221,7 +221,7 @@ static int stm32_lptim_setinput(struct stm32_lptim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32H7_LPTIM3 +#ifdef CONFIG_STM32_LPTIM3 case STM32_LPTIM3_BASE: modifyreg32(dev->base + STM32_LPTIM_CFGR2_OFFSET, LPTIM_CFGR2_IN1SEL_MASK, mux); @@ -301,27 +301,27 @@ static int stm32_lptim_setisr(struct stm32_lptim_dev_s *dev, switch (dev->base) { -#ifdef CONFIG_STM32H7_LPTIM1 +#ifdef CONFIG_STM32_LPTIM1 case STM32_LPTIM1_BASE: vectorno = STM32_IRQ_LPTIM1; break; #endif -#ifdef CONFIG_STM32H7_LPTIM2 +#ifdef CONFIG_STM32_LPTIM2 case STM32_LPTIM2_BASE: vectorno = STM32_IRQ_LPTIM2; break; #endif -#ifdef CONFIG_STM32H7_LPTIM3 +#ifdef CONFIG_STM32_LPTIM3 case STM32_LPTIM3_BASE: vectorno = STM32_IRQ_LPTIM3; break; #endif -#ifdef CONFIG_STM32H7_LPTIM4 +#ifdef CONFIG_STM32_LPTIM4 case STM32_LPTIM4_BASE: vectorno = STM32_IRQ_LPTIM4; break; #endif -#ifdef CONFIG_STM32H7_LPTIM5 +#ifdef CONFIG_STM32_LPTIM5 case STM32_LPTIM5_BASE: vectorno = STM32_IRQ_LPTIM5; break; @@ -391,31 +391,31 @@ struct stm32_lptim_dev_s *stm32_lptim_init(int lptimer) switch (lptimer) { -#ifdef CONFIG_STM32H7_LPTIM1 +#ifdef CONFIG_STM32_LPTIM1 case 1: dev = &stm32_lptim1_priv; modifyreg32(STM32_RCC_APB1LENR, 0, RCC_APB1LENR_LPTIM1EN); break; #endif -#ifdef CONFIG_STM32H7_LPTIM2 +#ifdef CONFIG_STM32_LPTIM2 case 2: dev = &stm32_lptim2_priv; modifyreg32(STM32_RCC_APB4ENR, 0, RCC_APB4ENR_LPTIM2EN); break; #endif -#ifdef CONFIG_STM32H7_LPTIM3 +#ifdef CONFIG_STM32_LPTIM3 case 3: dev = &stm32_lptim3_priv; modifyreg32(STM32_RCC_APB4ENR, 0, RCC_APB4ENR_LPTIM3EN); break; #endif -#ifdef CONFIG_STM32H7_LPTIM4 +#ifdef CONFIG_STM32_LPTIM4 case 4: dev = &stm32_lptim4_priv; modifyreg32(STM32_RCC_APB4ENR, 0, RCC_APB4ENR_LPTIM4EN); break; #endif -#ifdef CONFIG_STM32H7_LPTIM5 +#ifdef CONFIG_STM32_LPTIM5 case 5: dev = &stm32_lptim5_priv; modifyreg32(STM32_RCC_APB4ENR, 0, RCC_APB4ENR_LPTIM5EN); @@ -436,27 +436,27 @@ int stm32_lptim_deinit(struct stm32_lptim_dev_s * dev) switch (dev->base) { -#ifdef CONFIG_STM32H7_LPTIM1 +#ifdef CONFIG_STM32_LPTIM1 case STM32_LPTIM1_BASE: modifyreg32(STM32_RCC_APB1LLPENR, RCC_APB1LENR_LPTIM1EN, 0); break; #endif -#ifdef CONFIG_STM32H7_LPTIM2 +#ifdef CONFIG_STM32_LPTIM2 case STM32_LPTIM2_BASE: modifyreg32(STM32_RCC_APB4LPENR, RCC_APB4ENR_LPTIM2EN, 0); break; #endif -#ifdef CONFIG_STM32H7_LPTIM3 +#ifdef CONFIG_STM32_LPTIM3 case STM32_LPTIM3_BASE: modifyreg32(STM32_RCC_APB4LPENR, RCC_APB4ENR_LPTIM3EN, 0); break; #endif -#ifdef CONFIG_STM32H7_LPTIM4 +#ifdef CONFIG_STM32_LPTIM4 case STM32_LPTIM4_BASE: modifyreg32(STM32_RCC_APB4LPENR, RCC_APB4ENR_LPTIM4EN, 0); break; #endif -#ifdef CONFIG_STM32H7_LPTIM5 +#ifdef CONFIG_STM32_LPTIM5 case STM32_LPTIM5_BASE: modifyreg32(STM32_RCC_APB4LPENR, RCC_APB4ENR_LPTIM5EN, 0); break; @@ -468,4 +468,4 @@ int stm32_lptim_deinit(struct stm32_lptim_dev_s * dev) return OK; } -#endif /* defined(CONFIG_STM32H7_LPTIM1 || ... || CONFIG_STM32H7_LPTIM5) */ +#endif /* defined(CONFIG_STM32_LPTIM1 || ... || CONFIG_STM32_LPTIM5) */ diff --git a/arch/arm/src/stm32h7/stm32_lse.c b/arch/arm/src/stm32h7/stm32_lse.c index e55b9936798be..0fdfaf611c744 100644 --- a/arch/arm/src/stm32h7/stm32_lse.c +++ b/arch/arm/src/stm32h7/stm32_lse.c @@ -42,16 +42,16 @@ static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1, #define LSERDY_TIMEOUT (500 * CONFIG_BOARD_LOOPSPERMSEC) -#ifdef CONFIG_STM32H7_RTC_LSECLOCK_START_DRV_CAPABILITY -# if CONFIG_STM32H7_RTC_LSECLOCK_START_DRV_CAPABILITY < 0 || \ - CONFIG_STM32H7_RTC_LSECLOCK_START_DRV_CAPABILITY > 3 +#ifdef CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY +# if CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY < 0 || \ + CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY > 3 # error "Invalid LSE drive capability setting" # endif #endif -#ifdef CONFIG_STM32H7_RTC_LSECLOCK_RUN_DRV_CAPABILITY -# if CONFIG_STM32H7_RTC_LSECLOCK_RUN_DRV_CAPABILITY < 0 || \ - CONFIG_STM32H7_RTC_LSECLOCK_RUN_DRV_CAPABILITY > 3 +#ifdef CONFIG_STM32_RTC_LSECLOCK_RUN_DRV_CAPABILITY +# if CONFIG_STM32_RTC_LSECLOCK_RUN_DRV_CAPABILITY < 0 || \ + CONFIG_STM32_RTC_LSECLOCK_RUN_DRV_CAPABILITY > 3 # error "Invalid LSE drive capability setting" # endif #endif @@ -96,7 +96,7 @@ void stm32_rcc_enablelse(void) { uint32_t regval; volatile int32_t timeout; -#ifdef CONFIG_STM32H7_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY +#ifdef CONFIG_STM32_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY volatile int32_t drive = 0; #endif const uint32_t *drives = drives_rev_y; @@ -131,18 +131,18 @@ void stm32_rcc_enablelse(void) regval |= RCC_BDCR_LSEON; -#ifdef CONFIG_STM32H7_RTC_LSECLOCK_START_DRV_CAPABILITY +#ifdef CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY /* Set start-up drive capability for LSE oscillator. With the * enable off */ regval &= ~(RCC_BDCR_LSEDRV_MASK | RCC_BDCR_LSEON); - regval |= drives[CONFIG_STM32H7_RTC_LSECLOCK_START_DRV_CAPABILITY]; + regval |= drives[CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY]; putreg32(regval, STM32_RCC_BDCR); regval |= RCC_BDCR_LSEON; #endif -#ifdef CONFIG_STM32H7_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY +#ifdef CONFIG_STM32_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY do { regval &= ~(RCC_BDCR_LSEDRV_MASK | RCC_BDCR_LSEON); @@ -170,7 +170,7 @@ void stm32_rcc_enablelse(void) } } -#ifdef CONFIG_STM32H7_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY +#ifdef CONFIG_STM32_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY if (timeout != 0) { break; @@ -179,13 +179,13 @@ void stm32_rcc_enablelse(void) while (drive < sizeof(drives_rev_y) / sizeof(drives_rev_y[0])); #endif -#if defined(CONFIG_STM32H7_RTC_LSECLOCK_RUN_DRV_CAPABILITY) && \ - CONFIG_STM32H7_RTC_LSECLOCK_START_DRV_CAPABILITY != \ - CONFIG_STM32H7_RTC_LSECLOCK_RUN_DRV_CAPABILITY +#if defined(CONFIG_STM32_RTC_LSECLOCK_RUN_DRV_CAPABILITY) && \ + CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY != \ + CONFIG_STM32_RTC_LSECLOCK_RUN_DRV_CAPABILITY /* Set running drive capability for LSE oscillator. */ regval &= ~RCC_BDCR_LSEDRV_MASK; - regval |= drives[CONFIG_STM32H7_RTC_LSECLOCK_RUN_DRV_CAPABILITY]; + regval |= drives[CONFIG_STM32_RTC_LSECLOCK_RUN_DRV_CAPABILITY]; putreg32(regval, STM32_RCC_BDCR); #endif diff --git a/arch/arm/src/stm32h7/stm32_ltdc.c b/arch/arm/src/stm32h7/stm32_ltdc.c index 79f6ac0f0de04..3f0578227a0eb 100644 --- a/arch/arm/src/stm32h7/stm32_ltdc.c +++ b/arch/arm/src/stm32h7/stm32_ltdc.c @@ -127,8 +127,8 @@ /* Configuration ************************************************************/ -#ifndef CONFIG_STM32H7_LTDC_DEFBACKLIGHT -# define CONFIG_STM32H7_LTDC_DEFBACKLIGHT 0xf0 +#ifndef CONFIG_STM32_LTDC_DEFBACKLIGHT +# define CONFIG_STM32_LTDC_DEFBACKLIGHT 0xf0 #endif #define STM32_LTDC_BACKLIGHT_OFF 0x00 @@ -136,23 +136,23 @@ /* Layer 1 format */ -#if defined(CONFIG_STM32H7_LTDC_L1_L8) +#if defined(CONFIG_STM32_LTDC_L1_L8) # define STM32_LTDC_L1_BPP 8 # define STM32_LTDC_L1_COLOR_FMT FB_FMT_RGB8 # define STM32_LTDC_L1PFCR_PF LTDC_LXPFCR_PF(LTDC_PF_L8) # define STM32_LTDC_L1_DMA2D_PF DMA2D_PF_L8 # define STM32_LTDC_L1CMAP -#elif defined(CONFIG_STM32H7_LTDC_L1_RGB565) +#elif defined(CONFIG_STM32_LTDC_L1_RGB565) # define STM32_LTDC_L1_BPP 16 # define STM32_LTDC_L1_COLOR_FMT FB_FMT_RGB16_565 # define STM32_LTDC_L1PFCR_PF LTDC_LXPFCR_PF(LTDC_PF_RGB565) # define STM32_LTDC_L1_DMA2D_PF DMA2D_PF_RGB565 -#elif defined(CONFIG_STM32H7_LTDC_L1_RGB888) +#elif defined(CONFIG_STM32_LTDC_L1_RGB888) # define STM32_LTDC_L1_BPP 24 # define STM32_LTDC_L1_COLOR_FMT FB_FMT_RGB24 # define STM32_LTDC_L1PFCR_PF LTDC_LXPFCR_PF(LTDC_PF_RGB888) # define STM32_LTDC_L1_DMA2D_PF DMA2D_PF_RGB888 -#elif defined(CONFIG_STM32H7_LTDC_L1_ARGB8888) +#elif defined(CONFIG_STM32_LTDC_L1_ARGB8888) # define STM32_LTDC_L1_BPP 32 # define STM32_LTDC_L1_COLOR_FMT FB_FMT_RGB32 # define STM32_LTDC_L1PFCR_PF LTDC_LXPFCR_PF(LTDC_PF_ARGB8888) @@ -163,24 +163,24 @@ /* Layer 2 format */ -#ifdef CONFIG_STM32H7_LTDC_L2 -# if defined(CONFIG_STM32H7_LTDC_L2_L8) +#ifdef CONFIG_STM32_LTDC_L2 +# if defined(CONFIG_STM32_LTDC_L2_L8) # define STM32_LTDC_L2_BPP 8 # define STM32_LTDC_L2_COLOR_FMT FB_FMT_RGB8 # define STM32_LTDC_L2PFCR_PF LTDC_LXPFCR_PF(LTDC_PF_L8) # define STM32_LTDC_L2_DMA2D_PF DMA2D_PF_L8 # define STM32_LTDC_L2CMAP -# elif defined(CONFIG_STM32H7_LTDC_L2_RGB565) +# elif defined(CONFIG_STM32_LTDC_L2_RGB565) # define STM32_LTDC_L2_BPP 16 # define STM32_LTDC_L2_COLOR_FMT FB_FMT_RGB16_565 # define STM32_LTDC_L2PFCR_PF LTDC_LXPFCR_PF(LTDC_PF_RGB565) # define STM32_LTDC_L2_DMA2D_PF DMA2D_PF_RGB565 -# elif defined(CONFIG_STM32H7_LTDC_L2_RGB888) +# elif defined(CONFIG_STM32_LTDC_L2_RGB888) # define STM32_LTDC_L2_BPP 24 # define STM32_LTDC_L2_COLOR_FMT FB_FMT_RGB24 # define STM32_LTDC_L2PFCR_PF LTDC_LXPFCR_PF(LTDC_PF_RGB888) # define STM32_LTDC_L2_DMA2D_PF DMA2D_PF_RGB888 -# elif defined(CONFIG_STM32H7_LTDC_L2_ARGB8888) +# elif defined(CONFIG_STM32_LTDC_L2_ARGB8888) # define STM32_LTDC_L2_BPP 32 # define STM32_LTDC_L2_COLOR_FMT FB_FMT_RGB32 # define STM32_LTDC_L2PFCR_PF LTDC_LXPFCR_PF(LTDC_PF_ARGB8888) @@ -188,7 +188,7 @@ # else # error "LTDC pixel format not supported" # endif -#endif /* CONFIG_STM32H7_LTDC_L2 */ +#endif /* CONFIG_STM32_LTDC_L2 */ /* Framebuffer sizes in bytes */ @@ -208,43 +208,43 @@ #define STM32_LTDC_LX_BYPP(n) ((n) / 8) -#if defined(CONFIG_STM32H7_LTDC_FB_DOUBLE_BUFFER) +#if defined(CONFIG_STM32_LTDC_FB_DOUBLE_BUFFER) #define STM32_LTDC_L1_FBSIZE (STM32_LTDC_L1_STRIDE * STM32_LTDC_HEIGHT * 2) #else #define STM32_LTDC_L1_FBSIZE (STM32_LTDC_L1_STRIDE * STM32_LTDC_HEIGHT) #endif -#ifdef CONFIG_STM32H7_LTDC_L2 -# ifndef CONFIG_STM32H7_LTDC_L2_WIDTH -# define CONFIG_STM32H7_LTDC_L2_WIDTH STM32_LTDC_WIDTH +#ifdef CONFIG_STM32_LTDC_L2 +# ifndef CONFIG_STM32_LTDC_L2_WIDTH +# define CONFIG_STM32_LTDC_L2_WIDTH STM32_LTDC_WIDTH # endif -# if CONFIG_STM32H7_LTDC_L2_WIDTH > STM32_LTDC_WIDTH +# if CONFIG_STM32_LTDC_L2_WIDTH > STM32_LTDC_WIDTH # error Width of Layer 2 exceeds the width of the display # endif -# ifndef CONFIG_STM32H7_LTDC_L2_HEIGHT -# define CONFIG_STM32H7_LTDC_L2_HEIGHT STM32_LTDC_HEIGHT +# ifndef CONFIG_STM32_LTDC_L2_HEIGHT +# define CONFIG_STM32_LTDC_L2_HEIGHT STM32_LTDC_HEIGHT # endif -# if CONFIG_STM32H7_LTDC_L2_HEIGHT > STM32_LTDC_HEIGHT +# if CONFIG_STM32_LTDC_L2_HEIGHT > STM32_LTDC_HEIGHT # error Height of Layer 2 exceeds the height of the display # endif # if STM32_LTDC_L2_BPP == 8 -# define STM32_LTDC_L2_STRIDE (CONFIG_STM32H7_LTDC_L2_WIDTH) +# define STM32_LTDC_L2_STRIDE (CONFIG_STM32_LTDC_L2_WIDTH) # elif STM32_LTDC_L2_BPP == 16 -# define STM32_LTDC_L2_STRIDE ((CONFIG_STM32H7_LTDC_L2_WIDTH * 16 + 7) / 8) +# define STM32_LTDC_L2_STRIDE ((CONFIG_STM32_LTDC_L2_WIDTH * 16 + 7) / 8) # elif STM32_LTDC_L2_BPP == 24 -# define STM32_LTDC_L2_STRIDE ((CONFIG_STM32H7_LTDC_L2_WIDTH * 24 + 7) / 8) +# define STM32_LTDC_L2_STRIDE ((CONFIG_STM32_LTDC_L2_WIDTH * 24 + 7) / 8) # elif STM32_LTDC_L2_BPP == 32 -# define STM32_LTDC_L2_STRIDE ((CONFIG_STM32H7_LTDC_L2_WIDTH * 32 + 7) / 8) +# define STM32_LTDC_L2_STRIDE ((CONFIG_STM32_LTDC_L2_WIDTH * 32 + 7) / 8) # else # error Undefined or unrecognized base resolution # endif # define STM32_LTDC_L2_FBSIZE (STM32_LTDC_L2_STRIDE * \ - CONFIG_STM32H7_LTDC_L2_HEIGHT) + CONFIG_STM32_LTDC_L2_HEIGHT) #else # define STM32_LTDC_L2_FBSIZE (0) @@ -258,7 +258,7 @@ /* Debug option */ -#ifdef CONFIG_STM32H7_LTDC_REGDEBUG +#ifdef CONFIG_STM32_LTDC_REGDEBUG # define regerr lcderr # define reginfo lcdinfo #else @@ -273,10 +273,10 @@ * against wild framebuffer writes. */ -#define STM32_LTDC_BUFFER_SIZE CONFIG_STM32H7_LTDC_FB_SIZE +#define STM32_LTDC_BUFFER_SIZE CONFIG_STM32_LTDC_FB_SIZE #define STM32_LTDC_BUFFER_FREE (STM32_LTDC_BUFFER_SIZE - \ STM32_LTDC_TOTAL_FBSIZE) -#define STM32_LTDC_BUFFER_START (CONFIG_STM32H7_LTDC_FB_BASE + \ +#define STM32_LTDC_BUFFER_START (CONFIG_STM32_LTDC_FB_BASE + \ STM32_LTDC_BUFFER_FREE/2) #if STM32_LTDC_BUFFER_FREE < 0 @@ -289,7 +289,7 @@ #define STM32_LTDC_ENDBUF_L1 (STM32_LTDC_BUFFER_L1 + \ STM32_LTDC_L1_FBSIZE) -#ifdef CONFIG_STM32H7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 # define STM32_LTDC_BUFFER_L2 STM32_LTDC_ENDBUF_L1 # define STM32_LTDC_ENDBUF_L2 (STM32_LTDC_BUFFER_L2 + \ STM32_LTDC_L2_FBSIZE) @@ -299,7 +299,7 @@ /* LTDC layer */ -#ifdef CONFIG_STM32H7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 # define LTDC_NLAYERS 2 #else # define LTDC_NLAYERS 1 @@ -307,27 +307,27 @@ /* DMA2D layer */ -#ifdef CONFIG_STM32H7_DMA2D -# define DMA2D_NLAYERS CONFIG_STM32H7_DMA2D_NLAYERS +#ifdef CONFIG_STM32_DMA2D +# define DMA2D_NLAYERS CONFIG_STM32_DMA2D_NLAYERS # if DMA2D_NLAYERS < 1 # error "DMA2D must at least support 1 overlay" # endif -#define STM32_DMA2D_WIDTH CONFIG_STM32H7_DMA2D_LAYER_PPLINE +#define STM32_DMA2D_WIDTH CONFIG_STM32_DMA2D_LAYER_PPLINE -# if defined(CONFIG_STM32H7_DMA2D_L8) +# if defined(CONFIG_STM32_DMA2D_L8) # define STM32_DMA2D_STRIDE (STM32_DMA2D_WIDTH) # define STM32_DMA2D_BPP 8 # define STM32_DMA2D_COLOR_FMT DMA2D_PF_L8 -# elif defined(CONFIG_STM32H7_DMA2D_RGB565) +# elif defined(CONFIG_STM32_DMA2D_RGB565) # define STM32_DMA2D_STRIDE ((STM32_DMA2D_WIDTH * 16 + 7) / 8) # define STM32_DMA2D_BPP 16 # define STM32_DMA2D_COLOR_FMT DMA2D_PF_RGB565 -# elif defined(CONFIG_STM32H7_DMA2D_RGB888) +# elif defined(CONFIG_STM32_DMA2D_RGB888) # define STM32_DMA2D_STRIDE ((STM32_DMA2D_WIDTH * 24 + 7) / 8) # define STM32_DMA2D_BPP 24 # define STM32_DMA2D_COLOR_FMT DMA2D_PF_RGB888 -# elif defined(CONFIG_STM32H7_DMA2D_ARGB8888) +# elif defined(CONFIG_STM32_DMA2D_ARGB8888) # define STM32_DMA2D_STRIDE ((STM32_DMA2D_WIDTH * 32 + 7) / 8) # define STM32_DMA2D_BPP 32 # define STM32_DMA2D_COLOR_FMT DMA2D_PF_ARGB8888 @@ -335,63 +335,63 @@ # error "DMA2D pixel format not supported" # endif -# ifdef CONFIG_STM32H7_DMA2D_LAYER_SHARED -# define STM32_DMA2D_FBSIZE CONFIG_STM32H7_DMA2D_FB_SIZE +# ifdef CONFIG_STM32_DMA2D_LAYER_SHARED +# define STM32_DMA2D_FBSIZE CONFIG_STM32_DMA2D_FB_SIZE # define STM32_DMA2D_LAYER_SIZE 0 # else -# define STM32_DMA2D_FBSIZE CONFIG_STM32H7_DMA2D_FB_SIZE / DMA2D_NLAYERS +# define STM32_DMA2D_FBSIZE CONFIG_STM32_DMA2D_FB_SIZE / DMA2D_NLAYERS # define STM32_DMA2D_LAYER_SIZE STM32_DMA2D_FBSIZE -# if STM32_DMA2D_FBSIZE * DMA2D_NLAYERS > CONFIG_STM32H7_DMA2D_FB_SIZE +# if STM32_DMA2D_FBSIZE * DMA2D_NLAYERS > CONFIG_STM32_DMA2D_FB_SIZE # error "DMA2D framebuffer size to small for configured number of overlays" # endif -# endif /* CONFIG_STM32H7_DMA2D_LAYER_SHARED */ +# endif /* CONFIG_STM32_DMA2D_LAYER_SHARED */ # define STM32_DMA2D_HEIGHT STM32_DMA2D_FBSIZE / STM32_DMA2D_STRIDE -# define STM32_DMA2D_BUFFER_START CONFIG_STM32H7_DMA2D_FB_BASE +# define STM32_DMA2D_BUFFER_START CONFIG_STM32_DMA2D_FB_BASE #else # define DMA2D_NLAYERS 0 -#endif /* CONFIG_STM32H7_DMA2D */ +#endif /* CONFIG_STM32_DMA2D */ #define LTDC_NOVERLAYS LTDC_NLAYERS + DMA2D_NLAYERS /* Dithering */ -#ifndef CONFIG_STM32H7_LTDC_DITHER_RED +#ifndef CONFIG_STM32_LTDC_DITHER_RED # define STM32_LTDC_DITHER_RED 0 #else -# define STM32_LTDC_DITHER_RED CONFIG_STM32H7_LTDC_DITHER_RED +# define STM32_LTDC_DITHER_RED CONFIG_STM32_LTDC_DITHER_RED #endif -#ifndef CONFIG_STM32H7_LTDC_DITHER_GREEN +#ifndef CONFIG_STM32_LTDC_DITHER_GREEN # define STM32_LTDC_DITHER_GREEN 0 #else -# define STM32_LTDC_DITHER_GREEN CONFIG_STM32H7_LTDC_DITHER_GREEN +# define STM32_LTDC_DITHER_GREEN CONFIG_STM32_LTDC_DITHER_GREEN #endif -#ifndef CONFIG_STM32H7_LTDC_DITHER_BLUE +#ifndef CONFIG_STM32_LTDC_DITHER_BLUE # define STM32_LTDC_DITHER_BLUE 0 #else -# define STM32_LTDC_DITHER_BLUE CONFIG_STM32H7_LTDC_DITHER_BLUE +# define STM32_LTDC_DITHER_BLUE CONFIG_STM32_LTDC_DITHER_BLUE #endif /* Background color */ -#ifndef CONFIG_STM32H7_LTDC_BACKCOLOR +#ifndef CONFIG_STM32_LTDC_BACKCOLOR # define STM32_LTDC_BACKCOLOR 0 #else -# define STM32_LTDC_BACKCOLOR CONFIG_STM32H7_LTDC_BACKCOLOR +# define STM32_LTDC_BACKCOLOR CONFIG_STM32_LTDC_BACKCOLOR #endif /* Layer default color */ -#ifdef CONFIG_STM32H7_LTDC_L1_COLOR -# define STM32_LTDC_L1_COLOR CONFIG_STM32H7_LTDC_L1_COLOR +#ifdef CONFIG_STM32_LTDC_L1_COLOR +# define STM32_LTDC_L1_COLOR CONFIG_STM32_LTDC_L1_COLOR #else # define STM32_LTDC_L1_COLOR 0x000000 #endif -#ifdef CONFIG_STM32H7_LTDC_L2 -# ifdef CONFIG_STM32H7_LTDC_L2_COLOR -# define STM32_LTDC_L2_COLOR CONFIG_STM32H7_LTDC_L2_COLOR +#ifdef CONFIG_STM32_LTDC_L2 +# ifdef CONFIG_STM32_LTDC_L2_COLOR +# define STM32_LTDC_L2_COLOR CONFIG_STM32_LTDC_L2_COLOR # else # define STM32_LTDC_L2_COLOR 0x000000 # endif @@ -425,28 +425,28 @@ /* Check pixel format support by DMA2D driver */ -#ifdef CONFIG_STM32H7_DMA2D -# if defined(CONFIG_STM32H7_LTDC_L1_L8) || \ - defined(CONFIG_STM32H7_LTDC_L2_L8) -# if !defined(CONFIG_STM32H7_DMA2D_L8) +#ifdef CONFIG_STM32_DMA2D +# if defined(CONFIG_STM32_LTDC_L1_L8) || \ + defined(CONFIG_STM32_LTDC_L2_L8) +# if !defined(CONFIG_STM32_DMA2D_L8) # error "DMA2D must support FB_FMT_RGB8 pixel format" # endif # endif -# if defined(CONFIG_STM32H7_LTDC_L1_RGB565) || \ - defined(CONFIG_STM32H7_LTDC_L2_RGB565) -# if !defined(CONFIG_STM32H7_DMA2D_RGB565) +# if defined(CONFIG_STM32_LTDC_L1_RGB565) || \ + defined(CONFIG_STM32_LTDC_L2_RGB565) +# if !defined(CONFIG_STM32_DMA2D_RGB565) # error "DMA2D must support FB_FMT_RGB16_565 pixel format" # endif # endif -# if defined(CONFIG_STM32H7_LTDC_L1_RGB888) || \ - defined(CONFIG_STM32H7_LTDC_L2_RGB888) -# if !defined(CONFIG_STM32H7_DMA2D_RGB888) +# if defined(CONFIG_STM32_LTDC_L1_RGB888) || \ + defined(CONFIG_STM32_LTDC_L2_RGB888) +# if !defined(CONFIG_STM32_DMA2D_RGB888) # error "DMA2D must support FB_FMT_RGB24 pixel format" # endif # endif -# if defined(CONFIG_STM32H7_LTDC_L1_ARGB8888) || \ - defined(CONFIG_STM32H7_LTDC_L2_ARGB8888) -# if !defined(CONFIG_STM32H7_DMA2D_ARGB8888) +# if defined(CONFIG_STM32_LTDC_L1_ARGB8888) || \ + defined(CONFIG_STM32_LTDC_L2_ARGB8888) +# if !defined(CONFIG_STM32_DMA2D_ARGB8888) # error "DMA2D must support FB_FMT_RGB32 pixel format" # endif # endif @@ -454,12 +454,12 @@ /* Calculate the size of the layers clut table */ -#ifdef CONFIG_STM32H7_FB_CMAP -# if defined(CONFIG_STM32H7_DMA2D) && !defined(CONFIG_STM32H7_DMA2D_L8) +#ifdef CONFIG_STM32_FB_CMAP +# if defined(CONFIG_STM32_DMA2D) && !defined(CONFIG_STM32_DMA2D_L8) # error "DMA2D must also support L8 CLUT pixel format if supported by LTDC" # endif # ifdef STM32_LTDC_L1CMAP -# ifdef CONFIG_STM32H7_FB_TRANSPARENCY +# ifdef CONFIG_STM32_FB_TRANSPARENCY # define STM32_LAYER_CLUT_SIZE STM32_LTDC_NCLUT * sizeof(uint32_t) # else # define STM32_LAYER_CLUT_SIZE STM32_LTDC_NCLUT * 3 * sizeof(uint8_t) @@ -467,7 +467,7 @@ # endif # ifdef STM32_LTDC_L2CMAP # undef STM32_LAYER_CLUT_SIZE -# ifdef CONFIG_STM32H7_FB_TRANSPARENCY +# ifdef CONFIG_STM32_FB_TRANSPARENCY # define STM32_LAYER_CLUT_SIZE STM32_LTDC_NCLUT * sizeof(uint32_t) * 2 # else # define STM32_LAYER_CLUT_SIZE STM32_LTDC_NCLUT * 3 * sizeof(uint8_t) * 2 @@ -475,7 +475,7 @@ # endif #endif -#ifndef CONFIG_STM32H7_FB_CMAP +#ifndef CONFIG_STM32_FB_CMAP # if defined(STM32_LTDC_L1CMAP) || defined(STM32_LTDC_L2CMAP) # undef STM32_LTDC_L1CMAP # undef STM32_LTDC_L2CMAP @@ -512,9 +512,9 @@ /* Acceleration support for LTDC overlays */ -#ifdef CONFIG_STM32H7_LTDC_L1_CHROMAKEYEN +#ifdef CONFIG_STM32_LTDC_L1_CHROMAKEYEN # define STM32_LTDC_L1_CHROMAEN true -# define STM32_LTDC_L1_CHROMAKEY CONFIG_STM32H7_LTDC_L1_CHROMAKEY +# define STM32_LTDC_L1_CHROMAKEY CONFIG_STM32_LTDC_L1_CHROMAKEY # define LTDC_LTDC_ACCL_L1 FB_ACCL_TRANSP | FB_ACCL_CHROMA #else # define STM32_LTDC_L1_CHROMAEN false @@ -522,9 +522,9 @@ # define LTDC_LTDC_ACCL_L1 FB_ACCL_TRANSP #endif -#ifdef CONFIG_STM32H7_LTDC_L2_CHROMAKEYEN +#ifdef CONFIG_STM32_LTDC_L2_CHROMAKEYEN # define STM32_LTDC_L2_CHROMAEN true -# define STM32_LTDC_L2_CHROMAKEY CONFIG_STM32H7_LTDC_L2_CHROMAKEY +# define STM32_LTDC_L2_CHROMAKEY CONFIG_STM32_LTDC_L2_CHROMAKEY # define LTDC_LTDC_ACCL_L2 FB_ACCL_TRANSP | FB_ACCL_CHROMA #else # define STM32_LTDC_L2_CHROMAEN false @@ -532,34 +532,34 @@ # define LTDC_LTDC_ACCL_L2 FB_ACCL_TRANSP #endif -#ifdef CONFIG_STM32H7_DMA2D +#ifdef CONFIG_STM32_DMA2D # ifdef CONFIG_FB_OVERLAY_BLIT -# ifdef CONFIG_STM32H7_FB_CMAP +# ifdef CONFIG_STM32_FB_CMAP # define LTDC_BLIT_ACCL FB_ACCL_BLIT # else # define LTDC_BLIT_ACCL FB_ACCL_BLIT | FB_ACCL_BLEND -# endif /* CONFIG_STM32H7_FB_CMAP */ +# endif /* CONFIG_STM32_FB_CMAP */ # else # define LTDC_BLIT_ACCL 0 # endif /* CONFIG_FB_OVERLAY_BLIT */ -# ifdef CONFIG_STM32H7_FB_CMAP +# ifdef CONFIG_STM32_FB_CMAP # define LTDC_DMA2D_ACCL LTDC_BLIT_ACCL # else # define LTDC_DMA2D_ACCL FB_ACCL_COLOR | LTDC_BLIT_ACCL -# endif /* CONFIG_STM32H7_FB_CMAP */ +# endif /* CONFIG_STM32_FB_CMAP */ #else # define LTDC_DMA2D_ACCL 0 -#endif /* CONFIG_STM32H7_DMA2D */ +#endif /* CONFIG_STM32_DMA2D */ #define LTDC_L1_ACCL LTDC_LTDC_ACCL_L1 | LTDC_DMA2D_ACCL -#ifdef CONFIG_STM32H7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 # define LTDC_L2_ACCL LTDC_LTDC_ACCL_L2 | LTDC_DMA2D_ACCL #endif /* Acceleration support for DMA2D overlays */ -#ifdef CONFIG_STM32H7_FB_CMAP +#ifdef CONFIG_STM32_FB_CMAP # ifdef CONFIG_FB_OVERLAY_BLIT # define DMA2D_ACCL FB_ACCL_BLIT | FB_ACCL_AREA # else @@ -585,7 +585,7 @@ /* Color normalization */ -#if defined(CONFIG_STM32H7_LTDC_L1_RGB565) +#if defined(CONFIG_STM32_LTDC_L1_RGB565) # define RGB888_R(x) (((((x) >> 11) & 0x1f) * 527 + 23) >> 6) # define RGB888_G(x) (((((x) >> 5) & 0x3f) * 259 + 33) >> 6) # define RGB888_B(x) ((((x) & 0x1f) * 527 + 23) >> 6) @@ -618,7 +618,7 @@ struct stm32_ltdc_s struct fb_overlayinfo_s oinfo; /* Overlay info */ #endif -#ifdef CONFIG_STM32H7_DMA2D +#ifdef CONFIG_STM32_DMA2D struct stm32_dma2d_overlay_s dma2dinfo; /* Overlay info for DMA2D */ #endif @@ -643,7 +643,7 @@ struct stm32_ltdcdev_s /* Cmap information */ -#ifdef CONFIG_STM32H7_FB_CMAP +#ifdef CONFIG_STM32_FB_CMAP struct fb_cmap_s cmap; #endif @@ -651,7 +651,7 @@ struct stm32_ltdcdev_s struct stm32_ltdc_s layer[LTDC_NOVERLAYS]; -#ifdef CONFIG_STM32H7_DMA2D +#ifdef CONFIG_STM32_DMA2D /* Interface to the dma2d controller */ struct dma2d_layer_s *dma2d; @@ -699,7 +699,7 @@ static void stm32_ltdc_lchromakeyenable(struct stm32_ltdc_s *layer, bool enable); static void stm32_ltdc_linit(uint8_t lid); -#ifdef CONFIG_STM32H7_DMA2D +#ifdef CONFIG_STM32_DMA2D static void stm32_ltdc_dma2dlinit(void); # ifdef CONFIG_FB_OVERLAY_BLIT @@ -708,7 +708,7 @@ static bool stm32_ltdc_lvalidate(const struct stm32_ltdc_s *layer, # endif #endif -#ifdef CONFIG_STM32H7_FB_CMAP +#ifdef CONFIG_STM32_FB_CMAP static void stm32_ltdc_lputclut(struct stm32_ltdc_s *layer, const struct fb_cmap_s *cmap); static void stm32_ltdc_lgetclut(struct stm32_ltdc_s *layer, @@ -731,7 +731,7 @@ static int stm32_getplaneinfo(struct fb_vtable_s *vtable, * mapping */ -#ifdef CONFIG_STM32H7_FB_CMAP +#ifdef CONFIG_STM32_FB_CMAP static int stm32_getcmap(struct fb_vtable_s *vtable, struct fb_cmap_s *cmap); static int stm32_putcmap(struct fb_vtable_s *vtable, @@ -746,7 +746,7 @@ static int stm32_putcmap(struct fb_vtable_s *vtable, static int stm32_waitforvsync(struct fb_vtable_s *vtable); #endif -#if defined(CONFIG_STM32H7_LTDC_FB_DOUBLE_BUFFER) +#if defined(CONFIG_STM32_LTDC_FB_DOUBLE_BUFFER) static int stm32_pandisplay(struct fb_vtable_s *vtable, struct fb_planeinfo_s *pinfo); #endif @@ -806,16 +806,16 @@ static const uint32_t g_ltdcpins[] = #define STM32_LTDC_NPINCONFIGS (sizeof(g_ltdcpins) / sizeof(uint32_t)) -#ifdef CONFIG_STM32H7_FB_CMAP +#ifdef CONFIG_STM32_FB_CMAP /* The layers clut table entries */ static uint8_t g_redclut[STM32_LTDC_NCLUT]; static uint8_t g_greenclut[STM32_LTDC_NCLUT]; static uint8_t g_blueclut[STM32_LTDC_NCLUT]; -# ifdef CONFIG_STM32H7_FB_TRANSPARENCY +# ifdef CONFIG_STM32_FB_TRANSPARENCY static uint8_t g_transpclut[STM32_LTDC_NCLUT]; # endif -#endif /* CONFIG_STM32H7_FB_CMAP */ +#endif /* CONFIG_STM32_FB_CMAP */ /* The LTDC semaphore that enforces mutually exclusive access */ @@ -847,12 +847,12 @@ static struct stm32_ltdcdev_s g_vtable = .waitforvsync = stm32_waitforvsync #endif -#if defined(CONFIG_STM32H7_LTDC_FB_DOUBLE_BUFFER) +#if defined(CONFIG_STM32_LTDC_FB_DOUBLE_BUFFER) , .pandisplay = stm32_pandisplay #endif -#ifdef CONFIG_STM32H7_FB_CMAP +#ifdef CONFIG_STM32_FB_CMAP , .getcmap = stm32_getcmap, .putcmap = stm32_putcmap @@ -873,7 +873,7 @@ static struct stm32_ltdcdev_s g_vtable = # endif #endif /* CONFIG_FB_OVERLAY */ }, -#ifdef CONFIG_STM32H7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 .pinfo = { .fbmem = (uint8_t *)STM32_LTDC_BUFFER_L2, @@ -901,7 +901,7 @@ static struct stm32_ltdcdev_s g_vtable = .display = 0, .bpp = STM32_LTDC_L1_BPP, .xres_virtual = STM32_LTDC_WIDTH, -#if defined(CONFIG_STM32H7_LTDC_FB_DOUBLE_BUFFER) +#if defined(CONFIG_STM32_LTDC_FB_DOUBLE_BUFFER) .yres_virtual = STM32_LTDC_HEIGHT * 2, #else .yres_virtual = STM32_LTDC_HEIGHT, @@ -919,9 +919,9 @@ static struct stm32_ltdcdev_s g_vtable = .noverlays = LTDC_NOVERLAYS # endif } -#endif /* CONFIG_STM32H7_LTDC_L2 */ +#endif /* CONFIG_STM32_LTDC_L2 */ , -#ifdef CONFIG_STM32H7_FB_CMAP +#ifdef CONFIG_STM32_FB_CMAP .cmap = { .first = 0, @@ -929,7 +929,7 @@ static struct stm32_ltdcdev_s g_vtable = .red = g_redclut, .green = g_greenclut, .blue = g_blueclut, -# ifdef CONFIG_STM32H7_FB_TRANSPARENCY +# ifdef CONFIG_STM32_FB_TRANSPARENCY .transp = g_transpclut # endif } @@ -965,7 +965,7 @@ static struct stm32_ltdcdev_s g_vtable = }, #endif -#ifdef CONFIG_STM32H7_DMA2D +#ifdef CONFIG_STM32_DMA2D .dma2dinfo = { .fmt = STM32_LTDC_L1_DMA2D_PF, @@ -977,7 +977,7 @@ static struct stm32_ltdcdev_s g_vtable = #endif .lock = &g_lock } -#ifdef CONFIG_STM32H7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 , .layer[LTDC_LAYER_L2] = { @@ -1009,7 +1009,7 @@ static struct stm32_ltdcdev_s g_vtable = }, #endif -#ifdef CONFIG_STM32H7_DMA2D +#ifdef CONFIG_STM32_DMA2D .dma2dinfo = { .fmt = STM32_LTDC_L2_DMA2D_PF, @@ -1031,7 +1031,7 @@ static struct stm32_ltdcdev_s g_vtable = static const uint32_t stm32_width_layer_t[LTDC_NLAYERS] = { STM32_LTDC_WIDTH -#ifdef CONFIG_STM32H7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 , STM32_LTDC_WIDTH #endif }; @@ -1041,7 +1041,7 @@ static const uint32_t stm32_width_layer_t[LTDC_NLAYERS] = static const uint32_t stm32_height_layer_t[LTDC_NLAYERS] = { STM32_LTDC_HEIGHT -#ifdef CONFIG_STM32H7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 , STM32_LTDC_HEIGHT #endif }; @@ -1051,7 +1051,7 @@ static const uint32_t stm32_height_layer_t[LTDC_NLAYERS] = static const uint32_t stm32_stride_layer_t[LTDC_NLAYERS] = { STM32_LTDC_L1_STRIDE -#ifdef CONFIG_STM32H7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 , STM32_LTDC_L2_STRIDE #endif }; @@ -1061,7 +1061,7 @@ static const uint32_t stm32_stride_layer_t[LTDC_NLAYERS] = static const uint32_t stm32_bpp_layer_t[LTDC_NLAYERS] = { STM32_LTDC_L1_BPP -#ifdef CONFIG_STM32H7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 , STM32_LTDC_L2_BPP #endif }; @@ -1071,7 +1071,7 @@ static const uint32_t stm32_bpp_layer_t[LTDC_NLAYERS] = static const uint32_t stm32_fblen_layer_t[LTDC_NLAYERS] = { STM32_LTDC_L1_FBSIZE -#ifdef CONFIG_STM32H7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 , STM32_LTDC_L2_FBSIZE #endif }; @@ -1081,7 +1081,7 @@ static const uint32_t stm32_fblen_layer_t[LTDC_NLAYERS] = static const uint32_t stm32_fbmem_layer_t[LTDC_NLAYERS] = { STM32_LTDC_BUFFER_L1 -#ifdef CONFIG_STM32H7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 , STM32_LTDC_BUFFER_L2 #endif }; @@ -1091,7 +1091,7 @@ static const uint32_t stm32_fbmem_layer_t[LTDC_NLAYERS] = static const uint32_t stm32_defaultcolor_layer_t[LTDC_NLAYERS] = { STM32_LTDC_L1_COLOR -#ifdef CONFIG_STM32H7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 , STM32_LTDC_L2_COLOR #endif }; @@ -1101,7 +1101,7 @@ static const uint32_t stm32_defaultcolor_layer_t[LTDC_NLAYERS] = static const uint32_t stm32_chromakey_layer_t[LTDC_NLAYERS] = { STM32_LTDC_L1_CHROMAKEY -#ifdef CONFIG_STM32H7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 , STM32_LTDC_L2_CHROMAKEY #endif }; @@ -1111,7 +1111,7 @@ static const uint32_t stm32_chromakey_layer_t[LTDC_NLAYERS] = static const bool stm32_chromakeyen_layer_t[LTDC_NLAYERS] = { STM32_LTDC_L1_CHROMAEN -#ifdef CONFIG_STM32H7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 , STM32_LTDC_L2_CHROMAEN #endif }; @@ -1121,7 +1121,7 @@ static const bool stm32_chromakeyen_layer_t[LTDC_NLAYERS] = static const uint32_t stm32_fmt_layer_t[LTDC_NLAYERS] = { STM32_LTDC_L1PFCR_PF -#ifdef CONFIG_STM32H7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 , STM32_LTDC_L2PFCR_PF #endif }; @@ -1133,7 +1133,7 @@ static const uint32_t stm32_fmt_layer_t[LTDC_NLAYERS] = static const uintptr_t stm32_cr_layer_t[LTDC_NLAYERS] = { STM32_LTDC_L1CR -#ifdef CONFIG_STM32H7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 , STM32_LTDC_L2CR #endif }; @@ -1143,7 +1143,7 @@ static const uintptr_t stm32_cr_layer_t[LTDC_NLAYERS] = static const uintptr_t stm32_whpcr_layer_t[LTDC_NLAYERS] = { STM32_LTDC_L1WHPCR -#ifdef CONFIG_STM32H7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 , STM32_LTDC_L2WHPCR #endif }; @@ -1153,7 +1153,7 @@ static const uintptr_t stm32_whpcr_layer_t[LTDC_NLAYERS] = static const uintptr_t stm32_wvpcr_layer_t[LTDC_NLAYERS] = { STM32_LTDC_L1WVPCR -#ifdef CONFIG_STM32H7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 , STM32_LTDC_L2WVPCR #endif }; @@ -1163,7 +1163,7 @@ static const uintptr_t stm32_wvpcr_layer_t[LTDC_NLAYERS] = static const uintptr_t stm32_pfcr_layer_t[LTDC_NLAYERS] = { STM32_LTDC_L1PFCR -#ifdef CONFIG_STM32H7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 , STM32_LTDC_L2PFCR #endif }; @@ -1173,7 +1173,7 @@ static const uintptr_t stm32_pfcr_layer_t[LTDC_NLAYERS] = static const uintptr_t stm32_dccr_layer_t[LTDC_NLAYERS] = { STM32_LTDC_L1DCCR -#ifdef CONFIG_STM32H7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 , STM32_LTDC_L2DCCR #endif }; @@ -1183,7 +1183,7 @@ static const uintptr_t stm32_dccr_layer_t[LTDC_NLAYERS] = static const uintptr_t stm32_ckcr_layer_t[LTDC_NLAYERS] = { STM32_LTDC_L1CKCR -#ifdef CONFIG_STM32H7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 , STM32_LTDC_L2CKCR #endif }; @@ -1193,7 +1193,7 @@ static const uintptr_t stm32_ckcr_layer_t[LTDC_NLAYERS] = static const uintptr_t stm32_cacr_layer_t[LTDC_NLAYERS] = { STM32_LTDC_L1CACR -#ifdef CONFIG_STM32H7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 , STM32_LTDC_L2CACR #endif }; @@ -1203,7 +1203,7 @@ static const uintptr_t stm32_cacr_layer_t[LTDC_NLAYERS] = static const uintptr_t stm32_bfcr_layer_t[LTDC_NLAYERS] = { STM32_LTDC_L1BFCR -#ifdef CONFIG_STM32H7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 , STM32_LTDC_L2BFCR #endif }; @@ -1213,7 +1213,7 @@ static const uintptr_t stm32_bfcr_layer_t[LTDC_NLAYERS] = static const uintptr_t stm32_cfbar_layer_t[LTDC_NLAYERS] = { STM32_LTDC_L1CFBAR -#ifdef CONFIG_STM32H7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 , STM32_LTDC_L2CFBAR #endif }; @@ -1223,7 +1223,7 @@ static const uintptr_t stm32_cfbar_layer_t[LTDC_NLAYERS] = static const uintptr_t stm32_cfblr_layer_t[LTDC_NLAYERS] = { STM32_LTDC_L1CFBLR -#ifdef CONFIG_STM32H7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 , STM32_LTDC_L2CFBLR #endif }; @@ -1233,22 +1233,22 @@ static const uintptr_t stm32_cfblr_layer_t[LTDC_NLAYERS] = static const uintptr_t stm32_cfblnr_layer_t[LTDC_NLAYERS] = { STM32_LTDC_L1CFBLNR -#ifdef CONFIG_STM32H7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 , STM32_LTDC_L2CFBLNR #endif }; /* LTDC_LxCLUTWR */ -#ifdef CONFIG_STM32H7_FB_CMAP +#ifdef CONFIG_STM32_FB_CMAP static const uintptr_t stm32_clutwr_layer_t[LTDC_NLAYERS] = { STM32_LTDC_L1CLUTWR -# ifdef CONFIG_STM32H7_LTDC_L2 +# ifdef CONFIG_STM32_LTDC_L2 , STM32_LTDC_L2CLUTWR # endif }; -#endif /* CONFIG_STM32H7_FB_CMAP */ +#endif /* CONFIG_STM32_FB_CMAP */ /* The initialized state of the driver */ @@ -1501,7 +1501,7 @@ static int stm32_ltdcirq(int irq, void *context, void *arg) putreg32(LTDC_ICR_CRRIF, STM32_LTDC_ICR); priv->error = OK; -#if defined(CONFIG_STM32H7_LTDC_FB_DOUBLE_BUFFER) +#if defined(CONFIG_STM32_LTDC_FB_DOUBLE_BUFFER) fb_remove_paninfo(&g_vtable.vtable, FB_NO_OVERLAY); #endif } @@ -1681,7 +1681,7 @@ static void stm32_ltdc_globalconfig(void) /* Configure dither */ stm32_ltdc_dither( -#ifdef CONFIG_STM32H7_LTDC_DITHER +#ifdef CONFIG_STM32_LTDC_DITHER true, #else false, @@ -1953,7 +1953,7 @@ static void stm32_ltdc_lchromakey(struct stm32_ltdc_s *layer, /* Set chromakey */ -#ifdef CONFIG_STM32H7_FB_CMAP +#ifdef CONFIG_STM32_FB_CMAP uint8_t r = g_vtable.cmap.red[chroma]; uint8_t g = g_vtable.cmap.green[chroma]; uint8_t b = g_vtable.cmap.blue[chroma]; @@ -2023,7 +2023,7 @@ static void stm32_ltdc_lchromakeyenable(struct stm32_ltdc_s *layer, * ****************************************************************************/ -#ifdef CONFIG_STM32H7_FB_CMAP +#ifdef CONFIG_STM32_FB_CMAP static void stm32_ltdc_lclutenable(struct stm32_ltdc_s *layer, bool enable) { uint32_t regval; @@ -2127,7 +2127,7 @@ static void stm32_ltdc_lgetclut(struct stm32_ltdc_s *layer, for (n = cmap->first; n < cmap->len && n < STM32_LTDC_NCLUT; n++) { -# ifdef CONFIG_STM32H7_FB_TRANSPARENCY +# ifdef CONFIG_STM32_FB_TRANSPARENCY cmap->transp[n] = priv_cmap->transp[n]; # endif cmap->red[n] = priv_cmap->red[n]; @@ -2136,7 +2136,7 @@ static void stm32_ltdc_lgetclut(struct stm32_ltdc_s *layer, reginfo("color = %d, transp=%02x, red=%02x, green=%02x, blue=%02x\n", n, -# ifdef CONFIG_STM32H7_FB_TRANSPARENCY +# ifdef CONFIG_STM32_FB_TRANSPARENCY cmap->transp[n], # endif cmap->red[n], @@ -2144,7 +2144,7 @@ static void stm32_ltdc_lgetclut(struct stm32_ltdc_s *layer, cmap->blue[n]); } } -#endif /* CONFIG_STM32H7_FB_CMAP */ +#endif /* CONFIG_STM32_FB_CMAP */ /**************************************************************************** * Name: stm32_ltdc_lclear @@ -2176,7 +2176,7 @@ static void stm32_ltdc_lclear(uint8_t overlayno) * ****************************************************************************/ -#if defined(CONFIG_STM32H7_DMA2D) && defined(CONFIG_FB_OVERLAY_BLIT) +#if defined(CONFIG_STM32_DMA2D) && defined(CONFIG_FB_OVERLAY_BLIT) static bool stm32_ltdc_lvalidate(const struct stm32_ltdc_s *layer, const struct fb_area_s *area) { @@ -2187,7 +2187,7 @@ static bool stm32_ltdc_lvalidate(const struct stm32_ltdc_s *layer, return (offset <= layer->oinfo.fblen && area->w > 0 && area->h > 0); } -#endif /* defined(CONFIG_STM32H7_DMA2D) && defined(CONFIG_FB_OVERLAY_BLIT) */ +#endif /* defined(CONFIG_STM32_DMA2D) && defined(CONFIG_FB_OVERLAY_BLIT) */ /**************************************************************************** * Name: stm32_ltdc_linit @@ -2247,7 +2247,7 @@ static void stm32_ltdc_linit(uint8_t overlay) stm32_ltdc_lchromakeyenable(layer, stm32_chromakeyen_layer_t[overlay]); -#ifdef CONFIG_STM32H7_FB_CMAP +#ifdef CONFIG_STM32_FB_CMAP /* Disable clut by default */ if (dev->vinfo.fmt == FB_FMT_RGB8) @@ -2287,7 +2287,7 @@ static void stm32_ltdc_linit(uint8_t overlay) * ****************************************************************************/ -#ifdef CONFIG_STM32H7_DMA2D +#ifdef CONFIG_STM32_DMA2D static void stm32_ltdc_dma2dlinit(void) { int n; @@ -2323,7 +2323,7 @@ static void stm32_ltdc_dma2dlinit(void) layer->dma2dinfo.oinfo = &layer->oinfo; } } -#endif /* CONFIG_STM32H7_DMA2D */ +#endif /* CONFIG_STM32_DMA2D */ /**************************************************************************** * Public Functions @@ -2410,7 +2410,7 @@ static int stm32_getplaneinfo(struct fb_vtable_s *vtable, int planeno, * ****************************************************************************/ -#ifdef CONFIG_STM32H7_FB_CMAP +#ifdef CONFIG_STM32_FB_CMAP static int stm32_getcmap(struct fb_vtable_s *vtable, struct fb_cmap_s *cmap) { @@ -2440,7 +2440,7 @@ static int stm32_getcmap(struct fb_vtable_s *vtable, */ struct stm32_ltdc_s *layer; -# ifdef CONFIG_STM32H7_LTDC_L2 +# ifdef CONFIG_STM32_LTDC_L2 layer = &priv->layer[LTDC_LAYER_L2]; # else layer = &priv->layer[LTDC_LAYER_L1]; @@ -2510,7 +2510,7 @@ static int stm32_putcmap(struct fb_vtable_s *vtable, priv_cmap->red[n] = cmap->red[n]; priv_cmap->green[n] = cmap->green[n]; priv_cmap->blue[n] = cmap->blue[n]; -# ifdef CONFIG_STM32H7_FB_TRANSPARENCY +# ifdef CONFIG_STM32_FB_TRANSPARENCY /* Not supported by LTDC */ priv_cmap->transp[n] = cmap->transp[n]; @@ -2530,7 +2530,7 @@ static int stm32_putcmap(struct fb_vtable_s *vtable, stm32_ltdc_lputclut(layer, priv_cmap); } -# ifdef CONFIG_STM32H7_DMA2D +# ifdef CONFIG_STM32_DMA2D /* Update dma2d cmap */ priv->dma2d->setclut(cmap); @@ -2542,7 +2542,7 @@ static int stm32_putcmap(struct fb_vtable_s *vtable, return ret; } -#endif /* CONFIG_STM32H7_FB_CMAP */ +#endif /* CONFIG_STM32_FB_CMAP */ /**************************************************************************** * Name: stm32_ioctl_waitforvsync @@ -2570,7 +2570,7 @@ static int stm32_waitforvsync(struct fb_vtable_s *vtable) * Description: * Entrypoint ioctl FBIOPAN_DISPLAY ****************************************************************************/ -#if defined(CONFIG_STM32H7_LTDC_FB_DOUBLE_BUFFER) +#if defined(CONFIG_STM32_LTDC_FB_DOUBLE_BUFFER) static int stm32_pandisplay(struct fb_vtable_s *vtable, struct fb_planeinfo_s *pinfo) { @@ -2647,7 +2647,7 @@ static int stm32_settransp(struct fb_vtable_s *vtable, layer->oinfo.transp.transp = oinfo->transp.transp; layer->oinfo.transp.transp_mode = oinfo->transp.transp_mode; -# ifdef CONFIG_STM32H7_DMA2D +# ifdef CONFIG_STM32_DMA2D if (layer->oinfo.transp.transp_mode == 0) { layer->dma2dinfo.transp_mode = STM32_DMA2D_PFCCR_AM_CONST; @@ -2694,14 +2694,14 @@ static int stm32_setchromakey(struct fb_vtable_s *vtable, int ret; struct stm32_ltdc_s *layer = &priv->layer[oinfo->overlay]; -# ifndef CONFIG_STM32H7_LTDC_L1_CHROMAKEY +# ifndef CONFIG_STM32_LTDC_L1_CHROMAKEY if (oinfo->overlay == LTDC_LAYER_L1) { return -ENOSYS; } # endif -# ifndef CONFIG_STM32H7_LTDC_L2_CHROMAKEY +# ifndef CONFIG_STM32_LTDC_L2_CHROMAKEY if (oinfo->overlay == LTDC_LAYER_L2) { return -ENOSYS; @@ -2709,7 +2709,7 @@ static int stm32_setchromakey(struct fb_vtable_s *vtable, # endif nxsem_wait(layer->lock); -# ifdef CONFIG_STM32H7_FB_CMAP +# ifdef CONFIG_STM32_FB_CMAP if (oinfo->chromakey >= g_vtable.cmap.len) { lcderr("ERROR: Clut index %d is out of range\n", oinfo->chromakey); @@ -2729,7 +2729,7 @@ static int stm32_setchromakey(struct fb_vtable_s *vtable, nxsem_post(layer->lock); return ret; } -# ifdef CONFIG_STM32H7_DMA2D +# ifdef CONFIG_STM32_DMA2D else if (oinfo->overlay < LTDC_NOVERLAYS) { /* Chromakey not supported by DMA2D */ @@ -2757,7 +2757,7 @@ static int stm32_setcolor(struct fb_vtable_s *vtable, if (oinfo->overlay < LTDC_NOVERLAYS) { -# ifdef CONFIG_STM32H7_DMA2D +# ifdef CONFIG_STM32_DMA2D /* Set color within the active overlay is not supported by LTDC. So use * DMA2D controller instead when configured. @@ -2817,7 +2817,7 @@ static int stm32_setblank(struct fb_vtable_s *vtable, return OK; } -# ifdef CONFIG_STM32H7_DMA2D +# ifdef CONFIG_STM32_DMA2D else if (oinfo->overlay < LTDC_NOVERLAYS) { /* DMA2D overlays are non visible */ @@ -2851,7 +2851,7 @@ static int stm32_setarea(struct fb_vtable_s *vtable, return -ENOSYS; } -# ifdef CONFIG_STM32H7_DMA2D +# ifdef CONFIG_STM32_DMA2D if (oinfo->overlay < LTDC_NOVERLAYS) { struct stm32_ltdcdev_s *priv = (struct stm32_ltdcdev_s *)vtable; @@ -2885,7 +2885,7 @@ static int stm32_blit(struct fb_vtable_s *vtable, if (blit->dest.overlay < LTDC_NOVERLAYS && blit->src.overlay < LTDC_NOVERLAYS) { -# ifdef CONFIG_STM32H7_DMA2D +# ifdef CONFIG_STM32_DMA2D int ret; struct fb_area_s sarea; const struct fb_area_s *darea = &blit->dest.area; @@ -2944,7 +2944,7 @@ static int stm32_blend(struct fb_vtable_s *vtable, blend->foreground.overlay < LTDC_NOVERLAYS && blend->background.overlay < LTDC_NOVERLAYS) { -# ifdef CONFIG_STM32H7_DMA2D +# ifdef CONFIG_STM32_DMA2D int ret; struct fb_area_s barea; const struct fb_area_s *darea = &blend->dest.area; @@ -3055,7 +3055,7 @@ int stm32_ltdcinitialize(void) lcdinfo("Configure global register\n"); stm32_ltdc_globalconfig(); -#ifdef CONFIG_STM32H7_DMA2D +#ifdef CONFIG_STM32_DMA2D /* Initialize the dma2d controller */ ret = stm32_dma2dinitialize(); @@ -3071,31 +3071,31 @@ int stm32_ltdcinitialize(void) DEBUGASSERT(g_vtable.dma2d != NULL); #endif -#ifdef CONFIG_STM32H7_FB_CMAP +#ifdef CONFIG_STM32_FB_CMAP /* Cleanup clut */ memset(&g_redclut, 0, STM32_LTDC_NCLUT); memset(&g_blueclut, 0, STM32_LTDC_NCLUT); memset(&g_greenclut, 0, STM32_LTDC_NCLUT); -# ifdef CONFIG_STM32H7_FB_TRANSPARENCY +# ifdef CONFIG_STM32_FB_TRANSPARENCY memset(&g_transpclut, 0, STM32_LTDC_NCLUT); # endif -#endif /* CONFIG_STM32H7_FB_CMAP */ +#endif /* CONFIG_STM32_FB_CMAP */ /* Initialize ltdc layer */ lcdinfo("Initialize ltdc layer\n"); stm32_ltdc_linit(LTDC_LAYER_L1); -#ifdef CONFIG_STM32H7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 stm32_ltdc_linit(LTDC_LAYER_L2); #endif -#ifdef CONFIG_STM32H7_DMA2D +#ifdef CONFIG_STM32_DMA2D stm32_ltdc_dma2dlinit(); #endif /* Enable the backlight */ -#ifdef CONFIG_STM32H7_LCD_BACKLIGHT +#ifdef CONFIG_STM32_LCD_BACKLIGHT stm32_backlight(true); #endif @@ -3181,10 +3181,10 @@ void stm32_ltdcuninitialize(void) * ****************************************************************************/ -#ifdef CONFIG_STM32H7_LCD_BACKLIGHT +#ifdef CONFIG_STM32_LCD_BACKLIGHT void stm32_backlight(bool blon) { - /* Set default backlight level CONFIG_STM32H7_LTDC_DEFBACKLIGHT */ + /* Set default backlight level CONFIG_STM32_LTDC_DEFBACKLIGHT */ lcderr("ERROR: Not supported\n"); } diff --git a/arch/arm/src/stm32h7/stm32_ltdc.h b/arch/arm/src/stm32h7/stm32_ltdc.h index 53a73da7d08bb..cd95f6da700f8 100644 --- a/arch/arm/src/stm32h7/stm32_ltdc.h +++ b/arch/arm/src/stm32h7/stm32_ltdc.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F7_STM32_LTDC_H -#define __ARCH_ARM_SRC_STM32F7_STM32_LTDC_H +#ifndef __ARCH_ARM_SRC_STM32H7_STM32_LTDC_H +#define __ARCH_ARM_SRC_STM32H7_STM32_LTDC_H /**************************************************************************** * Included Files @@ -91,12 +91,12 @@ struct fb_vtable_s *stm32_ltdcgetvplane(int vplane); * Name: stm32_lcd_backlight * * Description: - * If CONFIG_STM32F7_LCD_BACKLIGHT is defined, then the board-specific + * If CONFIG_STM32_LCD_BACKLIGHT is defined, then the board-specific * logic must provide this interface to turn the backlight on and off. * ****************************************************************************/ -#ifdef CONFIG_STM32F7_LCD_BACKLIGHT +#ifdef CONFIG_STM32_LCD_BACKLIGHT void stm32_backlight(bool blon); #endif -#endif /* __ARCH_ARM_SRC_STM32F7_STM32_LTDC_H */ +#endif /* __ARCH_ARM_SRC_STM32H7_STM32_LTDC_H */ diff --git a/arch/arm/src/stm32h7/stm32_mdio.c b/arch/arm/src/stm32h7/stm32_mdio.c index d524b27ce1f6e..412aedcb915d5 100644 --- a/arch/arm/src/stm32h7/stm32_mdio.c +++ b/arch/arm/src/stm32h7/stm32_mdio.c @@ -30,7 +30,7 @@ * Pre-processor Definitions ****************************************************************************/ -#ifdef CONFIG_STM32H7_ETHMAC_REGDEBUG +#ifdef CONFIG_STM32_ETHMAC_REGDEBUG static uint32_t stm32_getreg(uint32_t addr); static void stm32_putreg(uint32_t val, uint32_t addr); static void stm32_checksetup(void); diff --git a/arch/arm/src/stm32h7/stm32_mpuinit.c b/arch/arm/src/stm32h7/stm32_mpuinit.c index 91d78295bb85c..a141895b21020 100644 --- a/arch/arm/src/stm32h7/stm32_mpuinit.c +++ b/arch/arm/src/stm32h7/stm32_mpuinit.c @@ -44,9 +44,9 @@ ****************************************************************************/ #ifdef CONFIG_RPTUN -# ifdef CONFIG_STM32H7_SHMEM_SRAM3 +# ifdef CONFIG_STM32_SHMEM_SRAM3 # define STM32_SHMEM_BASE STM32_SRAM3_BASE -# define STM32_SHMEM_SIZE STM32H7_SRAM3_SIZE +# define STM32_SHMEM_SIZE STM32_SRAM3_SIZE # else # error missing shmem MPU configuration # endif diff --git a/arch/arm/src/stm32h7/stm32_oneshot.c b/arch/arm/src/stm32h7/stm32_oneshot.c index 078d6efe50236..e1fc56718ec77 100644 --- a/arch/arm/src/stm32h7/stm32_oneshot.c +++ b/arch/arm/src/stm32h7/stm32_oneshot.c @@ -39,7 +39,7 @@ #include "stm32_oneshot.h" -#ifdef CONFIG_STM32H7_ONESHOT +#ifdef CONFIG_STM32_ONESHOT /**************************************************************************** * Private Function Prototypes @@ -51,7 +51,7 @@ static int stm32_oneshot_handler(int irg_num, void * context, void *arg); * Private Data ****************************************************************************/ -static struct stm32_oneshot_s *g_oneshot[CONFIG_STM32H7_ONESHOT_MAXTIMERS]; +static struct stm32_oneshot_s *g_oneshot[CONFIG_STM32_ONESHOT_MAXTIMERS]; /**************************************************************************** * Private Functions @@ -117,19 +117,19 @@ static int stm32_oneshot_handler(int irg_num, void * context, void *arg) * * Returned Value: * Returns zero (OK) on success. This can only fail if the number of - * timers exceeds CONFIG_STM32H7_ONESHOT_MAXTIMERS. + * timers exceeds CONFIG_STM32_ONESHOT_MAXTIMERS. * ****************************************************************************/ static inline int stm32_allocate_handler(struct stm32_oneshot_s *oneshot) { -#if CONFIG_STM32H7_ONESHOT_MAXTIMERS > 1 +#if CONFIG_STM32_ONESHOT_MAXTIMERS > 1 int ret = -EBUSY; int i; /* Search for an unused handler */ - for (i = 0; i < CONFIG_STM32H7_ONESHOT_MAXTIMERS; i++) + for (i = 0; i < CONFIG_STM32_ONESHOT_MAXTIMERS; i++) { /* Is this handler available? */ @@ -401,4 +401,4 @@ int stm32_oneshot_cancel(struct stm32_oneshot_s *oneshot, return OK; } -#endif /* CONFIG_STM32H7_ONESHOT */ +#endif /* CONFIG_STM32_ONESHOT */ diff --git a/arch/arm/src/stm32h7/stm32_oneshot.h b/arch/arm/src/stm32h7/stm32_oneshot.h index 412f901e16b4b..f16523985ff1f 100644 --- a/arch/arm/src/stm32h7/stm32_oneshot.h +++ b/arch/arm/src/stm32h7/stm32_oneshot.h @@ -36,22 +36,22 @@ #include "stm32_tim.h" -#ifdef CONFIG_STM32H7_ONESHOT +#ifdef CONFIG_STM32_ONESHOT /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ -#if !defined(CONFIG_STM32H7_ONESHOT_MAXTIMERS) || \ - CONFIG_STM32H7_ONESHOT_MAXTIMERS < 1 -# undef CONFIG_STM32H7_ONESHOT_MAXTIMERS -# define CONFIG_STM32H7_ONESHOT_MAXTIMERS 1 +#if !defined(CONFIG_STM32_ONESHOT_MAXTIMERS) || \ + CONFIG_STM32_ONESHOT_MAXTIMERS < 1 +# undef CONFIG_STM32_ONESHOT_MAXTIMERS +# define CONFIG_STM32_ONESHOT_MAXTIMERS 1 #endif -#if CONFIG_STM32H7_ONESHOT_MAXTIMERS > 8 +#if CONFIG_STM32_ONESHOT_MAXTIMERS > 8 # warning Additional logic required to handle more than 8 timers -# undef CONFIG_STM32H7_ONESHOT_MAXTIMERS -# define CONFIG_STM32H7_ONESHOT_MAXTIMERS 8 +# undef CONFIG_STM32_ONESHOT_MAXTIMERS +# define CONFIG_STM32_ONESHOT_MAXTIMERS 8 #endif /**************************************************************************** @@ -75,7 +75,7 @@ typedef void (*oneshot_handler_t)(void *arg); struct stm32_oneshot_s { uint8_t chan; /* The timer/counter in use */ -#if CONFIG_STM32H7_ONESHOT_MAXTIMERS > 1 +#if CONFIG_STM32_ONESHOT_MAXTIMERS > 1 uint8_t cbndx; /* Timer callback handler index */ #endif volatile bool running; /* True: the timer is running */ @@ -193,5 +193,5 @@ int stm32_oneshot_cancel(struct stm32_oneshot_s *oneshot, } #endif -#endif /* CONFIG_STM32H7_ONESHOT */ +#endif /* CONFIG_STM32_ONESHOT */ #endif /* __ARCH_ARM_SRC_STM32H7_STM32_ONESHOT_H */ diff --git a/arch/arm/src/stm32h7/stm32_otg.h b/arch/arm/src/stm32h7/stm32_otg.h index 131be78c428de..a847ccf74c0eb 100644 --- a/arch/arm/src/stm32h7/stm32_otg.h +++ b/arch/arm/src/stm32h7/stm32_otg.h @@ -37,21 +37,21 @@ #include "stm32_rcc.h" #include "hardware/stm32_otg.h" -#if defined(CONFIG_STM32H7_OTGFS) || defined(CONFIG_STM32H7_OTGHS) +#if defined(CONFIG_STM32_OTGFS) || defined(CONFIG_STM32_OTGHS) #if (STM32_RCC_D2CCIP2R_USBSRC == RCC_D2CCIP2R_USBSEL_HSI48) && \ - !defined(CONFIG_STM32H7_HSI48) + !defined(CONFIG_STM32_HSI48) # error board.h selected HSI48 as USB clock source, but HSI48 is not \ - enabled. Enable STM32H7_HSI48 + enabled. Enable STM32_HSI48 #endif -#if defined(CONFIG_STM32H7_OTGHS) && !defined(CONFIG_STM32H7_OTGHS_FS) && \ - defined(CONFIG_STM32H7_OTGHS_NO_ULPI) +#if defined(CONFIG_STM32_OTGHS) && !defined(CONFIG_STM32_OTGHS_FS) && \ + defined(CONFIG_STM32_OTGHS_NO_ULPI) # error OTG HS selected but no ULPI enabled #endif -#if defined(CONFIG_STM32H7_OTGHS_EXTERNAL_ULPI) && \ - !defined(CONFIG_STM32H7_SYSCFG_IOCOMPENSATION) +#if defined(CONFIG_STM32_OTGHS_EXTERNAL_ULPI) && \ + !defined(CONFIG_STM32_SYSCFG_IOCOMPENSATION) # error External ULPI needs IOCOMPENSATION enabled #endif @@ -126,7 +126,7 @@ struct usbhost_connection_s *stm32_otgfshost_initialize(int controller); struct usbdev_s; void stm32_usbsuspend(struct usbdev_s *dev, bool resume); -#ifdef CONFIG_STM32H7_OTGHS_EXTERNAL_ULPI +#ifdef CONFIG_STM32_OTGHS_EXTERNAL_ULPI /**************************************************************************** * Name: stm32_usbulpireset * @@ -145,5 +145,5 @@ void stm32_usbulpireset(struct usbdev_s *dev); #endif #endif /* __ASSEMBLY__ */ -#endif /* CONFIG_STM32H7_OTGFS */ +#endif /* CONFIG_STM32_OTGFS */ #endif /* __ARCH_ARM_SRC_STM32H7_STM32_OTG_H */ diff --git a/arch/arm/src/stm32h7/stm32_otgdev.c b/arch/arm/src/stm32h7/stm32_otgdev.c index 22e1774b527f7..d185b987a03fc 100644 --- a/arch/arm/src/stm32h7/stm32_otgdev.c +++ b/arch/arm/src/stm32h7/stm32_otgdev.c @@ -53,8 +53,8 @@ #include "stm32_otg.h" #include "arm_internal.h" -#if defined(CONFIG_USBDEV) && (defined(CONFIG_STM32H7_OTGFS) || \ - defined(CONFIG_STM32H7_OTGHS)) +#if defined(CONFIG_USBDEV) && (defined(CONFIG_STM32_OTGFS) || \ + defined(CONFIG_STM32_OTGHS)) /**************************************************************************** * Pre-processor Definitions @@ -62,7 +62,7 @@ /* OTG device selection *****************************************************/ -#if defined(CONFIG_STM32H7_OTGFS_USBDEV) +#if defined(CONFIG_STM32_OTGFS_USBDEV) # define STM32_IRQ_OTG STM32_IRQ_OTGFS # define STM32_OTG_BASE STM32_OTGFS_BASE # define GPIO_OTG_DM GPIO_OTGFS_DM @@ -70,7 +70,7 @@ # define GPIO_OTG_ID GPIO_OTGFS_ID # define GPIO_OTG_SOF GPIO_OTGFS_SOF # define STM32_OTG_FIFO_SIZE 4096 -#elif defined(CONFIG_STM32H7_OTGHS_USBDEV) +#elif defined(CONFIG_STM32_OTGHS_USBDEV) # define STM32_IRQ_OTG STM32_IRQ_OTGHS # define STM32_OTG_BASE STM32_OTGHS_BASE # define GPIO_OTG_DM GPIO_OTGHS_DM @@ -82,7 +82,7 @@ # error Not selected USBDEV peripheral #endif -#if defined(CONFIG_STM32H7_OTGFS_USBDEV) && defined(CONFIG_STM32H7_OTGHS_USBDEV) +#if defined(CONFIG_STM32_OTGFS_USBDEV) && defined(CONFIG_STM32_OTGHS_USBDEV) # error Only one USBDEV role supported #endif @@ -552,7 +552,7 @@ struct stm32_usbdev_s /* Register operations ******************************************************/ -#if defined(CONFIG_STM32H7_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES) +#if defined(CONFIG_STM32_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES) static uint32_t stm32_getreg(uint32_t addr); static void stm32_putreg(uint32_t val, uint32_t addr); #else @@ -879,7 +879,7 @@ const struct trace_msg_t g_usb_trace_strings_intdecode[] = * ****************************************************************************/ -#if defined(CONFIG_STM32H7_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES) +#if defined(CONFIG_STM32_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES) static uint32_t stm32_getreg(uint32_t addr) { static uint32_t prevaddr = 0; @@ -942,7 +942,7 @@ static uint32_t stm32_getreg(uint32_t addr) * ****************************************************************************/ -#if defined(CONFIG_STM32H7_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES) +#if defined(CONFIG_STM32_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES) static void stm32_putreg(uint32_t val, uint32_t addr) { /* Show the register value being written */ @@ -2138,8 +2138,8 @@ static void stm32_usbreset(struct stm32_usbdev_s *priv) stm32_setaddress(priv, 0); priv->devstate = DEVSTATE_DEFAULT; -#if defined(CONFIG_STM32H7_OTGHS_USBDEV) && \ - defined(CONFIG_STM32H7_OTGHS_EXTERNAL_ULPI) +#if defined(CONFIG_STM32_OTGHS_USBDEV) && \ + defined(CONFIG_STM32_OTGHS_EXTERNAL_ULPI) priv->usbdev.speed = USB_SPEED_HIGH; #else priv->usbdev.speed = USB_SPEED_FULL; @@ -3447,7 +3447,7 @@ static inline void stm32_enuminterrupt(struct stm32_usbdev_s *priv) regval = stm32_getreg(STM32_OTG_GUSBCFG); regval &= ~OTG_GUSBCFG_TRDT_MASK; -#ifdef CONFIG_STM32H7_OTGHS +#ifdef CONFIG_STM32_OTGHS regval |= OTG_GUSBCFG_TRDT(9); #else regval |= OTG_GUSBCFG_TRDT(6); @@ -5289,9 +5289,9 @@ static void stm32_hwinitialize(struct stm32_usbdev_s *priv) stm32_putreg(OTG_GAHBCFG_TXFELVL, STM32_OTG_GAHBCFG); -#if (defined(CONFIG_STM32H7_OTGHS_USBDEV) && \ - defined(CONFIG_STM32H7_OTGHS_NO_ULPI)) || \ - defined(CONFIG_STM32H7_OTGFS_USBDEV) +#if (defined(CONFIG_STM32_OTGHS_USBDEV) && \ + defined(CONFIG_STM32_OTGHS_NO_ULPI)) || \ + defined(CONFIG_STM32_OTGFS_USBDEV) /* Full speed serial transceiver select */ regval = stm32_getreg(STM32_OTG_GUSBCFG); @@ -5299,9 +5299,9 @@ static void stm32_hwinitialize(struct stm32_usbdev_s *priv) stm32_putreg(regval, STM32_OTG_GUSBCFG); #endif -#if defined(CONFIG_STM32H7_OTGHS_USBDEV) && \ - defined(CONFIG_STM32H7_OTGHS_FS) && \ - defined(CONFIG_STM32H7_OTGHS_EXTERNAL_ULPI) +#if defined(CONFIG_STM32_OTGHS_USBDEV) && \ + defined(CONFIG_STM32_OTGHS_FS) && \ + defined(CONFIG_STM32_OTGHS_EXTERNAL_ULPI) /* ULPI Full speed mode */ regval = stm32_getreg(STM32_OTG_GUSBCFG); @@ -5343,9 +5343,9 @@ static void stm32_hwinitialize(struct stm32_usbdev_s *priv) regval = stm32_getreg(STM32_OTG_GCCFG); -#if (defined(CONFIG_STM32H7_OTGHS_USBDEV) && \ - defined(CONFIG_STM32H7_OTGHS_NO_ULPI)) || \ - defined(CONFIG_STM32H7_OTGFS_USBDEV) +#if (defined(CONFIG_STM32_OTGHS_USBDEV) && \ + defined(CONFIG_STM32_OTGHS_NO_ULPI)) || \ + defined(CONFIG_STM32_OTGFS_USBDEV) /* Enable USB FS transceiver */ regval |= OTG_GCCFG_PWRDWN; @@ -5360,8 +5360,8 @@ static void stm32_hwinitialize(struct stm32_usbdev_s *priv) stm32_putreg(regval, STM32_OTG_GCCFG); up_mdelay(20); -#if defined(CONFIG_STM32H7_OTGHS_USBDEV) && \ - defined(CONFIG_STM32H7_OTGHS_EXTERNAL_ULPI) +#if defined(CONFIG_STM32_OTGHS_USBDEV) && \ + defined(CONFIG_STM32_OTGHS_EXTERNAL_ULPI) /* Enable delay to default timing, necessary for some ULPI PHYs such * as such as USB334x */ @@ -5404,10 +5404,10 @@ static void stm32_hwinitialize(struct stm32_usbdev_s *priv) regval = stm32_getreg(STM32_OTG_DCFG); regval &= ~OTG_DCFG_DSPD_MASK; -#if defined(CONFIG_STM32H7_OTGHS_USBDEV) && \ - defined(CONFIG_STM32H7_OTGHS_FS) +#if defined(CONFIG_STM32_OTGHS_USBDEV) && \ + defined(CONFIG_STM32_OTGHS_FS) regval |= OTG_DCFG_DSPD_FSHS; -#elif defined(CONFIG_STM32H7_OTGHS_USBDEV) +#elif defined(CONFIG_STM32_OTGHS_USBDEV) regval |= OTG_DCFG_DSPD_HS; #else regval |= OTG_DCFG_DSPD_FS; @@ -5550,8 +5550,8 @@ static void stm32_hwinitialize(struct stm32_usbdev_s *priv) regval &= OTG_GINT_RESERVED; stm32_putreg(regval | OTG_GINT_RC_W1, STM32_OTG_GINTSTS); -#if defined(CONFIG_STM32H7_OTGHS_USBDEV) && \ - defined(CONFIG_STM32H7_OTGHS_NO_ULPI) +#if defined(CONFIG_STM32_OTGHS_USBDEV) && \ + defined(CONFIG_STM32_OTGHS_NO_ULPI) /* Disable the ULPI Clock enable in RCC AHB1 Register. This must * be done because if both the ULPI and the FS PHY clock enable bits * are set at the same time, the ARM never awakens from WFI due to @@ -5636,7 +5636,7 @@ void arm_usbinitialize(void) /* Enable USB regulator if configured */ -#ifdef CONFIG_STM32H7_OTG_USBREGEN +#ifdef CONFIG_STM32_OTG_USBREGEN regval |= STM32_PWR_CR3_USBREGEN; #else regval &= ~STM32_PWR_CR3_USBREGEN; @@ -5660,8 +5660,8 @@ void arm_usbinitialize(void) * current detection. */ -#if !(defined(CONFIG_STM32H7_OTGHS_USBDEV) && \ - defined(CONFIG_STM32H7_OTGHS_EXTERNAL_ULPI)) +#if !(defined(CONFIG_STM32_OTGHS_USBDEV) && \ + defined(CONFIG_STM32_OTGHS_EXTERNAL_ULPI)) /* Configure OTG alternate function pins */ stm32_configgpio(GPIO_OTG_DM); @@ -5674,7 +5674,7 @@ void arm_usbinitialize(void) /* SOF output pin configuration is configurable. */ -# ifdef CONFIG_STM32H7_OTG_SOFOUTPUT +# ifdef CONFIG_STM32_OTG_SOFOUTPUT stm32_configgpio(GPIO_OTG_SOF); # endif @@ -5866,7 +5866,7 @@ int usbdev_register(struct usbdevclass_driver_s *driver) stm32_pullup(&priv->usbdev, true); -#if defined(CONFIG_STM32H7_OTGHS_EXTERNAL_ULPI) +#if defined(CONFIG_STM32_OTGHS_EXTERNAL_ULPI) priv->usbdev.speed = USB_SPEED_HIGH; #else priv->usbdev.speed = USB_SPEED_FULL; @@ -5938,4 +5938,4 @@ int usbdev_unregister(struct usbdevclass_driver_s *driver) return OK; } -#endif /* CONFIG_USBDEV && CONFIG_STM32H7_OTGDEV */ +#endif /* CONFIG_USBDEV && CONFIG_STM32_OTGDEV */ diff --git a/arch/arm/src/stm32h7/stm32_otghost.c b/arch/arm/src/stm32h7/stm32_otghost.c index 095f220418301..a192ab25ea6da 100644 --- a/arch/arm/src/stm32h7/stm32_otghost.c +++ b/arch/arm/src/stm32h7/stm32_otghost.c @@ -60,7 +60,7 @@ #include "stm32_otg.h" #include "stm32_usbhost.h" -#if defined(CONFIG_USBHOST) && defined(CONFIG_STM32H7_OTGFS) +#if defined(CONFIG_USBHOST) && defined(CONFIG_STM32_OTGFS) /**************************************************************************** * Pre-processor Definitions @@ -68,7 +68,7 @@ /* OTG host selection *******************************************************/ -#if defined(CONFIG_STM32H7_OTGFS_HOST) +#if defined(CONFIG_STM32_OTGFS_HOST) # define STM32_IRQ_OTG STM32_IRQ_OTGFS # define STM32_OTG_BASE STM32_OTGFS_BASE # define GPIO_OTG_DM GPIO_OTGFS_DM @@ -76,7 +76,7 @@ # define GPIO_OTG_ID GPIO_OTGFS_ID # define GPIO_OTG_SOF GPIO_OTGFS_SOF # define STM32_OTG_FIFO_SIZE 4096 -#elif defined(CONFIG_STM32H7_OTGHS_HOST) +#elif defined(CONFIG_STM32_OTGHS_HOST) # error OTGHS HOST role not supported yet # define STM32_IRQ_OTG STM32_IRQ_OTGHS # define STM32_OTG_BASE STM32_OTGHS_BASE @@ -89,7 +89,7 @@ # error Not selected USBDEV peripheral #endif -#if defined(CONFIG_STM32H7_OTGFS_HOST) && defined(CONFIG_STM32H7_OTGHS_HOST) +#if defined(CONFIG_STM32_OTGFS_HOST) && defined(CONFIG_STM32_OTGHS_HOST) # error Only one HOST role supported #endif @@ -100,61 +100,61 @@ * Pre-requisites * * CONFIG_USBHOST - Enable general USB host support - * CONFIG_STM32H7_OTGFS - Enable the STM32 USB OTG FS block - * CONFIG_STM32H7_SYSCFG - Needed + * CONFIG_STM32_OTGFS - Enable the STM32 USB OTG FS block + * CONFIG_STM32_SYSCFG - Needed * * Options: * - * CONFIG_STM32H7_OTG_RXFIFO_SIZE - Size of the RX FIFO in 32-bit words. + * CONFIG_STM32_OTG_RXFIFO_SIZE - Size of the RX FIFO in 32-bit words. * Default 128 (512 bytes) - * CONFIG_STM32H7_OTG_NPTXFIFO_SIZE - Size of the non-periodic Tx FIFO + * CONFIG_STM32_OTG_NPTXFIFO_SIZE - Size of the non-periodic Tx FIFO * in 32-bit words. Default 96 (384 bytes) - * CONFIG_STM32H7_OTG_PTXFIFO_SIZE - Size of the periodic Tx FIFO in 32-bit + * CONFIG_STM32_OTG_PTXFIFO_SIZE - Size of the periodic Tx FIFO in 32-bit * words. Default 96 (384 bytes) - * CONFIG_STM32H7_OTG_DESCSIZE - Maximum size of a descriptor. Default: 128 - * CONFIG_STM32H7_OTG_SOFINTR - Enable SOF interrupts. Why would you ever + * CONFIG_STM32_OTG_DESCSIZE - Maximum size of a descriptor. Default: 128 + * CONFIG_STM32_OTG_SOFINTR - Enable SOF interrupts. Why would you ever * want to do that? - * CONFIG_STM32H7_USBHOST_REGDEBUG - Enable very low-level register access + * CONFIG_STM32_USBHOST_REGDEBUG - Enable very low-level register access * debug. Depends on CONFIG_DEBUG_FEATURES. - * CONFIG_STM32H7_USBHOST_PKTDUMP - Dump all incoming and outgoing USB + * CONFIG_STM32_USBHOST_PKTDUMP - Dump all incoming and outgoing USB * packets. Depends on CONFIG_DEBUG_FEATURES. */ /* Pre-requisites (partial) */ -#ifndef CONFIG_STM32H7_SYSCFG -# error "CONFIG_STM32H7_SYSCFG is required" +#ifndef CONFIG_STM32_SYSCFG +# error "CONFIG_STM32_SYSCFG is required" #endif /* Default RxFIFO size */ -#ifndef CONFIG_STM32H7_OTG_RXFIFO_SIZE -# define CONFIG_STM32H7_OTG_RXFIFO_SIZE 128 +#ifndef CONFIG_STM32_OTG_RXFIFO_SIZE +# define CONFIG_STM32_OTG_RXFIFO_SIZE 128 #endif /* Default host non-periodic Tx FIFO size */ -#ifndef CONFIG_STM32H7_OTG_NPTXFIFO_SIZE -# define CONFIG_STM32H7_OTG_NPTXFIFO_SIZE 96 +#ifndef CONFIG_STM32_OTG_NPTXFIFO_SIZE +# define CONFIG_STM32_OTG_NPTXFIFO_SIZE 96 #endif /* Default host periodic Tx fifo size register */ -#ifndef CONFIG_STM32H7_OTG_PTXFIFO_SIZE -# define CONFIG_STM32H7_OTG_PTXFIFO_SIZE 96 +#ifndef CONFIG_STM32_OTG_PTXFIFO_SIZE +# define CONFIG_STM32_OTG_PTXFIFO_SIZE 96 #endif /* Maximum size of a descriptor */ -#ifndef CONFIG_STM32H7_OTG_DESCSIZE -# define CONFIG_STM32H7_OTG_DESCSIZE 128 +#ifndef CONFIG_STM32_OTG_DESCSIZE +# define CONFIG_STM32_OTG_DESCSIZE 128 #endif /* Register/packet debug depends on CONFIG_DEBUG_FEATURES */ #ifndef CONFIG_DEBUG_FEATURES -# undef CONFIG_STM32H7_USBHOST_REGDEBUG -# undef CONFIG_STM32H7_USBHOST_PKTDUMP +# undef CONFIG_STM32_USBHOST_REGDEBUG +# undef CONFIG_STM32_USBHOST_PKTDUMP #endif /* HCD Setup ****************************************************************/ @@ -299,7 +299,7 @@ struct stm32_usbhost_s /* Register operations ******************************************************/ -#ifdef CONFIG_STM32H7_USBHOST_REGDEBUG +#ifdef CONFIG_STM32_USBHOST_REGDEBUG static void stm32_printreg(uint32_t addr, uint32_t val, bool iswrite); static void stm32_checkreg(uint32_t addr, uint32_t val, bool iswrite); static uint32_t stm32_getreg(uint32_t addr); @@ -312,7 +312,7 @@ static void stm32_putreg(uint32_t addr, uint32_t value); static inline void stm32_modifyreg(uint32_t addr, uint32_t clrbits, uint32_t setbits); -#ifdef CONFIG_STM32H7_USBHOST_PKTDUMP +#ifdef CONFIG_STM32_USBHOST_PKTDUMP # define stm32_pktdump(m,b,n) lib_dumpbuffer(m,b,n) #else # define stm32_pktdump(m,b,n) @@ -407,7 +407,7 @@ static void stm32_gint_disconnected(struct stm32_usbhost_s *priv); /* Second level interrupt handlers */ -#ifdef CONFIG_STM32H7_OTG_SOFINTR +#ifdef CONFIG_STM32_OTG_SOFINTR static inline void stm32_gint_sofisr(struct stm32_usbhost_s *priv); #endif static inline void stm32_gint_rxflvlisr(struct stm32_usbhost_s *priv); @@ -523,7 +523,7 @@ static struct usbhost_connection_s g_usbconn = * ****************************************************************************/ -#ifdef CONFIG_STM32H7_USBHOST_REGDEBUG +#ifdef CONFIG_STM32_USBHOST_REGDEBUG static void stm32_printreg(uint32_t addr, uint32_t val, bool iswrite) { uinfo("%08" PRIx32 "%s%08" PRIx32 "\n", addr, iswrite ? "<-" : "->", val); @@ -538,7 +538,7 @@ static void stm32_printreg(uint32_t addr, uint32_t val, bool iswrite) * ****************************************************************************/ -#ifdef CONFIG_STM32H7_USBHOST_REGDEBUG +#ifdef CONFIG_STM32_USBHOST_REGDEBUG static void stm32_checkreg(uint32_t addr, uint32_t val, bool iswrite) { static uint32_t prevaddr = 0; @@ -602,7 +602,7 @@ static void stm32_checkreg(uint32_t addr, uint32_t val, bool iswrite) * ****************************************************************************/ -#ifdef CONFIG_STM32H7_USBHOST_REGDEBUG +#ifdef CONFIG_STM32_USBHOST_REGDEBUG static uint32_t stm32_getreg(uint32_t addr) { /* Read the value from the register */ @@ -624,7 +624,7 @@ static uint32_t stm32_getreg(uint32_t addr) * ****************************************************************************/ -#ifdef CONFIG_STM32H7_USBHOST_REGDEBUG +#ifdef CONFIG_STM32_USBHOST_REGDEBUG static void stm32_putreg(uint32_t addr, uint32_t val) { /* Check if we need to print this value */ @@ -3013,7 +3013,7 @@ static void stm32_gint_disconnected(struct stm32_usbhost_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32H7_OTG_SOFINTR +#ifdef CONFIG_STM32_OTG_SOFINTR static inline void stm32_gint_sofisr(struct stm32_usbhost_s *priv) { /* Handle SOF interrupt */ @@ -3581,7 +3581,7 @@ static int stm32_gint_isr(int irq, void *context, void *arg) /* Handle the start of frame interrupt */ -#ifdef CONFIG_STM32H7_OTG_SOFINTR +#ifdef CONFIG_STM32_OTG_SOFINTR if ((pending & OTG_GINT_SOF) != 0) { usbhost_vtrace1(OTG_VTRACE1_GINT_SOF, 0); @@ -3747,7 +3747,7 @@ static inline void stm32_hostinit_enable(void) * OTG_GINT_DISC : Disconnect detected interrupt */ -#ifdef CONFIG_STM32H7_OTG_SOFINTR +#ifdef CONFIG_STM32_OTG_SOFINTR regval |= (OTG_GINT_SOF | OTG_GINT_RXFLVL | OTG_GINT_IISOOXFR | OTG_GINT_HPRT | OTG_GINT_HC | OTG_GINT_DISC); #else @@ -4274,7 +4274,7 @@ static int stm32_alloc(struct usbhost_driver_s *drvr, /* There is no special memory requirement for the STM32. */ - alloc = kmm_malloc(CONFIG_STM32H7_OTG_DESCSIZE); + alloc = kmm_malloc(CONFIG_STM32_OTG_DESCSIZE); if (!alloc) { return -ENOMEM; @@ -4283,7 +4283,7 @@ static int stm32_alloc(struct usbhost_driver_s *drvr, /* Return the allocated address and size of the descriptor buffer */ *buffer = alloc; - *maxlen = CONFIG_STM32H7_OTG_DESCSIZE; + *maxlen = CONFIG_STM32_OTG_DESCSIZE; return OK; } @@ -5150,21 +5150,21 @@ static void stm32_host_initialize(struct stm32_usbhost_s *priv) /* Configure Rx FIFO size (GRXFSIZ) */ - stm32_putreg(STM32_OTG_GRXFSIZ, CONFIG_STM32H7_OTG_RXFIFO_SIZE); - offset = CONFIG_STM32H7_OTG_RXFIFO_SIZE; + stm32_putreg(STM32_OTG_GRXFSIZ, CONFIG_STM32_OTG_RXFIFO_SIZE); + offset = CONFIG_STM32_OTG_RXFIFO_SIZE; /* Setup the host non-periodic Tx FIFO size (HNPTXFSIZ) */ regval = (offset | - (CONFIG_STM32H7_OTG_NPTXFIFO_SIZE << + (CONFIG_STM32_OTG_NPTXFIFO_SIZE << OTG_HNPTXFSIZ_NPTXFD_SHIFT)); stm32_putreg(STM32_OTG_HNPTXFSIZ, regval); - offset += CONFIG_STM32H7_OTG_NPTXFIFO_SIZE; + offset += CONFIG_STM32_OTG_NPTXFIFO_SIZE; /* Set up the host periodic Tx fifo size register (HPTXFSIZ) */ regval = (offset | - (CONFIG_STM32H7_OTG_PTXFIFO_SIZE << + (CONFIG_STM32_OTG_PTXFIFO_SIZE << OTG_HPTXFSIZ_PTXFD_SHIFT)); stm32_putreg(STM32_OTG_HPTXFSIZ, regval); @@ -5414,7 +5414,7 @@ struct usbhost_connection_s *stm32_otgfshost_initialize(int controller) /* Enable USB regulator if configured */ -#ifdef CONFIG_STM32H7_OTG_USBREGEN +#ifdef CONFIG_STM32_OTG_USBREGEN regval |= STM32_PWR_CR3_USBREGEN; #else regval &= ~STM32_PWR_CR3_USBREGEN; @@ -5458,7 +5458,7 @@ struct usbhost_connection_s *stm32_otgfshost_initialize(int controller) /* SOF output pin configuration is configurable */ -#ifdef CONFIG_STM32H7_OTG_SOFOUTPUT +#ifdef CONFIG_STM32_OTG_SOFOUTPUT stm32_configgpio(GPIO_OTG_SOF); #endif @@ -5484,4 +5484,4 @@ struct usbhost_connection_s *stm32_otgfshost_initialize(int controller) return &g_usbconn; } -#endif /* CONFIG_USBHOST && CONFIG_STM32H7_OTGFS */ +#endif /* CONFIG_USBHOST && CONFIG_STM32_OTGFS */ diff --git a/arch/arm/src/stm32h7/stm32_pulsecount.c b/arch/arm/src/stm32h7/stm32_pulsecount.c index f0a5189aba06b..b963fbf02cd4c 100644 --- a/arch/arm/src/stm32h7/stm32_pulsecount.c +++ b/arch/arm/src/stm32h7/stm32_pulsecount.c @@ -83,7 +83,7 @@ /* Advanced timer support */ -# if defined(CONFIG_STM32H7_TIM1_PULSECOUNT) || defined(CONFIG_STM32H7_TIM8_PULSECOUNT) +# if defined(CONFIG_STM32_TIM1_PULSECOUNT) || defined(CONFIG_STM32_TIM8_PULSECOUNT) # endif /* Synchronisation support */ @@ -191,10 +191,10 @@ static int pulsecount_configure(struct pulsecount_lowerhalf_s *dev); static int pulsecount_timer(struct pulsecount_lowerhalf_s *dev, const struct pulsecount_info_s *info); static int pulsecount_interrupt(struct pulsecount_lowerhalf_s *dev); -# ifdef CONFIG_STM32H7_TIM1_PULSECOUNT +# ifdef CONFIG_STM32_TIM1_PULSECOUNT static int pulsecount_tim1interrupt(int irq, void *context, void *arg); # endif -# ifdef CONFIG_STM32H7_TIM8_PULSECOUNT +# ifdef CONFIG_STM32_TIM8_PULSECOUNT static int pulsecount_tim8interrupt(int irq, void *context, void *arg); # endif static uint8_t pulsecount_count(uint32_t count); @@ -221,107 +221,107 @@ static int pulsecount_ioctl(struct pulsecount_lowerhalf_s *dev, * Private Data ****************************************************************************/ -#ifdef CONFIG_STM32H7_TIM1_PULSECOUNT +#ifdef CONFIG_STM32_TIM1_PULSECOUNT static struct stm32_tim_s g_pulsecount1dev = { .channel = { - .channel = CONFIG_STM32H7_TIM1_PULSECOUNT_CHANNEL, -#if CONFIG_STM32H7_TIM1_PULSECOUNT_CHANNEL == 1 + .channel = CONFIG_STM32_TIM1_PULSECOUNT_CHANNEL, +#if CONFIG_STM32_TIM1_PULSECOUNT_CHANNEL == 1 .out1 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM1_PULSECOUNT_POL, - .idle = CONFIG_STM32H7_TIM1_PULSECOUNT_IDLE, + .pol = CONFIG_STM32_TIM1_PULSECOUNT_POL, + .idle = CONFIG_STM32_TIM1_PULSECOUNT_IDLE, .pincfg = GPIO_TIM1_CH1OUT, }, -#elif CONFIG_STM32H7_TIM1_PULSECOUNT_CHANNEL == 2 +#elif CONFIG_STM32_TIM1_PULSECOUNT_CHANNEL == 2 .out1 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM1_PULSECOUNT_POL, - .idle = CONFIG_STM32H7_TIM1_PULSECOUNT_IDLE, + .pol = CONFIG_STM32_TIM1_PULSECOUNT_POL, + .idle = CONFIG_STM32_TIM1_PULSECOUNT_IDLE, .pincfg = GPIO_TIM1_CH2OUT, }, -#elif CONFIG_STM32H7_TIM1_PULSECOUNT_CHANNEL == 3 +#elif CONFIG_STM32_TIM1_PULSECOUNT_CHANNEL == 3 .out1 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM1_PULSECOUNT_POL, - .idle = CONFIG_STM32H7_TIM1_PULSECOUNT_IDLE, + .pol = CONFIG_STM32_TIM1_PULSECOUNT_POL, + .idle = CONFIG_STM32_TIM1_PULSECOUNT_IDLE, .pincfg = GPIO_TIM1_CH3OUT, }, -#elif CONFIG_STM32H7_TIM1_PULSECOUNT_CHANNEL == 4 +#elif CONFIG_STM32_TIM1_PULSECOUNT_CHANNEL == 4 .out1 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM1_PULSECOUNT_POL, - .idle = CONFIG_STM32H7_TIM1_PULSECOUNT_IDLE, + .pol = CONFIG_STM32_TIM1_PULSECOUNT_POL, + .idle = CONFIG_STM32_TIM1_PULSECOUNT_IDLE, .pincfg = GPIO_TIM1_CH4OUT, }, #endif }, .timid = 1, .timtype = TIMTYPE_TIM1, - .t_dts = CONFIG_STM32H7_TIM1_PULSECOUNT_TDTS, + .t_dts = CONFIG_STM32_TIM1_PULSECOUNT_TDTS, .irq = STM32_IRQ_TIM1UP, .base = STM32_TIM1_BASE, .pclk = TIMCLK_TIM1, }; -#endif /* CONFIG_STM32H7_TIM1_PULSECOUNT */ +#endif /* CONFIG_STM32_TIM1_PULSECOUNT */ -#ifdef CONFIG_STM32H7_TIM8_PULSECOUNT +#ifdef CONFIG_STM32_TIM8_PULSECOUNT static struct stm32_tim_s g_pulsecount8dev = { .channel = { - .channel = CONFIG_STM32H7_TIM8_PULSECOUNT_CHANNEL, -#if CONFIG_STM32H7_TIM8_PULSECOUNT_CHANNEL == 1 + .channel = CONFIG_STM32_TIM8_PULSECOUNT_CHANNEL, +#if CONFIG_STM32_TIM8_PULSECOUNT_CHANNEL == 1 .out1 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM8_PULSECOUNT_POL, - .idle = CONFIG_STM32H7_TIM8_PULSECOUNT_IDLE, + .pol = CONFIG_STM32_TIM8_PULSECOUNT_POL, + .idle = CONFIG_STM32_TIM8_PULSECOUNT_IDLE, .pincfg = GPIO_TIM8_CH1OUT, }, -#elif CONFIG_STM32H7_TIM8_PULSECOUNT_CHANNEL == 2 +#elif CONFIG_STM32_TIM8_PULSECOUNT_CHANNEL == 2 .out1 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM8_PULSECOUNT_POL, - .idle = CONFIG_STM32H7_TIM8_PULSECOUNT_IDLE, + .pol = CONFIG_STM32_TIM8_PULSECOUNT_POL, + .idle = CONFIG_STM32_TIM8_PULSECOUNT_IDLE, .pincfg = GPIO_TIM8_CH2OUT, }, -#elif CONFIG_STM32H7_TIM8_PULSECOUNT_CHANNEL == 3 +#elif CONFIG_STM32_TIM8_PULSECOUNT_CHANNEL == 3 .out1 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM8_PULSECOUNT_POL, - .idle = CONFIG_STM32H7_TIM8_PULSECOUNT_IDLE, + .pol = CONFIG_STM32_TIM8_PULSECOUNT_POL, + .idle = CONFIG_STM32_TIM8_PULSECOUNT_IDLE, .pincfg = GPIO_TIM8_CH3OUT, }, -#elif CONFIG_STM32H7_TIM8_PULSECOUNT_CHANNEL == 4 +#elif CONFIG_STM32_TIM8_PULSECOUNT_CHANNEL == 4 .out1 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM8_PULSECOUNT_POL, - .idle = CONFIG_STM32H7_TIM8_PULSECOUNT_IDLE, + .pol = CONFIG_STM32_TIM8_PULSECOUNT_POL, + .idle = CONFIG_STM32_TIM8_PULSECOUNT_IDLE, .pincfg = GPIO_TIM8_CH4OUT, }, #endif }, .timid = 8, .timtype = TIMTYPE_TIM8, - .t_dts = CONFIG_STM32H7_TIM8_PULSECOUNT_TDTS, + .t_dts = CONFIG_STM32_TIM8_PULSECOUNT_TDTS, .irq = STM32_IRQ_TIM8UP, .base = STM32_TIM8_BASE, .pclk = TIMCLK_TIM8, }; -#endif /* CONFIG_STM32H7_TIM8_PULSECOUNT */ +#endif /* CONFIG_STM32_TIM8_PULSECOUNT */ static const struct pulsecount_ops_s g_pulsecountops = { @@ -332,7 +332,7 @@ static const struct pulsecount_ops_s g_pulsecountops = .ioctl = pulsecount_ioctl, }; -#ifdef CONFIG_STM32H7_TIM1_PULSECOUNT +#ifdef CONFIG_STM32_TIM1_PULSECOUNT static struct stm32_pulsecount_s g_pulsecount1lower = { .ops = &g_pulsecountops, @@ -340,7 +340,7 @@ static struct stm32_pulsecount_s g_pulsecount1lower = }; #endif -#ifdef CONFIG_STM32H7_TIM8_PULSECOUNT +#ifdef CONFIG_STM32_TIM8_PULSECOUNT static struct stm32_pulsecount_s g_pulsecount8lower = { .ops = &g_pulsecountops, @@ -1332,21 +1332,21 @@ static int pulsecount_interrupt(struct pulsecount_lowerhalf_s *dev) * ****************************************************************************/ -#ifdef CONFIG_STM32H7_TIM1_PULSECOUNT +#ifdef CONFIG_STM32_TIM1_PULSECOUNT static int pulsecount_tim1interrupt(int irq, void *context, void *arg) { return pulsecount_interrupt((struct pulsecount_lowerhalf_s *) &g_pulsecount1dev); } -#endif /* CONFIG_STM32H7_TIM1_PULSECOUNT */ +#endif /* CONFIG_STM32_TIM1_PULSECOUNT */ -#ifdef CONFIG_STM32H7_TIM8_PULSECOUNT +#ifdef CONFIG_STM32_TIM8_PULSECOUNT static int pulsecount_tim8interrupt(int irq, void *context, void *arg) { return pulsecount_interrupt((struct pulsecount_lowerhalf_s *) &g_pulsecount8dev); } -#endif /* CONFIG_STM32H7_TIM8_PULSECOUNT */ +#endif /* CONFIG_STM32_TIM8_PULSECOUNT */ /**************************************************************************** * Name: pulsecount_count @@ -1419,7 +1419,7 @@ static int pulsecount_set_apb_clock(struct stm32_tim_s *priv, bool on) switch (priv->timid) { -#ifdef CONFIG_STM32H7_TIM1_PULSECOUNT +#ifdef CONFIG_STM32_TIM1_PULSECOUNT case 1: { regaddr = TIMRCCEN_TIM1; @@ -1428,7 +1428,7 @@ static int pulsecount_set_apb_clock(struct stm32_tim_s *priv, bool on) } #endif -#ifdef CONFIG_STM32H7_TIM8_PULSECOUNT +#ifdef CONFIG_STM32_TIM8_PULSECOUNT case 8: { regaddr = TIMRCCEN_TIM8; @@ -1611,7 +1611,7 @@ static int pulsecount_ll_stop(struct pulsecount_lowerhalf_s *dev) switch (priv->timid) { -#ifdef CONFIG_STM32H7_TIM1_PULSECOUNT +#ifdef CONFIG_STM32_TIM1_PULSECOUNT case 1: { regaddr = TIMRCCRST_TIM1; @@ -1620,7 +1620,7 @@ static int pulsecount_ll_stop(struct pulsecount_lowerhalf_s *dev) } #endif -#ifdef CONFIG_STM32H7_TIM8_PULSECOUNT +#ifdef CONFIG_STM32_TIM8_PULSECOUNT case 8: { regaddr = TIMRCCRST_TIM8; @@ -1782,7 +1782,7 @@ struct pulsecount_lowerhalf_s *stm32_pulsecountinitialize(int timer) switch (timer) { -#ifdef CONFIG_STM32H7_TIM1_PULSECOUNT +#ifdef CONFIG_STM32_TIM1_PULSECOUNT case 1: { lower = &g_pulsecount1lower; @@ -1792,7 +1792,7 @@ struct pulsecount_lowerhalf_s *stm32_pulsecountinitialize(int timer) } #endif -#ifdef CONFIG_STM32H7_TIM8_PULSECOUNT +#ifdef CONFIG_STM32_TIM8_PULSECOUNT case 8: { lower = &g_pulsecount8lower; diff --git a/arch/arm/src/stm32h7/stm32_pwm.c b/arch/arm/src/stm32h7/stm32_pwm.c index d2dc3b4f06e8d..70b434b741b99 100644 --- a/arch/arm/src/stm32h7/stm32_pwm.c +++ b/arch/arm/src/stm32h7/stm32_pwm.c @@ -49,7 +49,7 @@ * 2. STM32 TIMER IP version 2 - F3 (no F37x), F7, H7, L4, L4+ */ -#ifdef CONFIG_STM32H7_PWM +#ifdef CONFIG_STM32_PWM /**************************************************************************** * Pre-processor Definitions @@ -171,16 +171,16 @@ /* Synchronisation support */ -#ifdef CONFIG_STM32H7_PWM_TRGO +#ifdef CONFIG_STM32_PWM_TRGO # define HAVE_TRGO #endif /* Break support */ -#if defined(CONFIG_STM32H7_TIM1_BREAK1) || defined(CONFIG_STM32H7_TIM1_BREAK2) || \ - defined(CONFIG_STM32H7_TIM8_BREAK1) || defined(CONFIG_STM32H7_TIM8_BREAK2) || \ - defined(CONFIG_STM32H7_TIM15_BREAK1) || defined(CONFIG_STM32H7_TIM16_BREAK1) || \ - defined(CONFIG_STM32H7_TIM17_BREAK1) +#if defined(CONFIG_STM32_TIM1_BREAK1) || defined(CONFIG_STM32_TIM1_BREAK2) || \ + defined(CONFIG_STM32_TIM8_BREAK1) || defined(CONFIG_STM32_TIM8_BREAK2) || \ + defined(CONFIG_STM32_TIM15_BREAK1) || defined(CONFIG_STM32_TIM16_BREAK1) || \ + defined(CONFIG_STM32_TIM17_BREAK1) # defined HAVE_BREAK #endif @@ -243,7 +243,7 @@ struct stm32_pwmchan_s struct stm32_pwmtimer_s { const struct pwm_ops_s *ops; /* PWM operations */ -#ifdef CONFIG_STM32H7_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS const struct stm32_pwm_ops_s *llops; /* Low-level PWM ops */ #endif struct stm32_pwmchan_s *channels; /* Channels configuration */ @@ -316,10 +316,10 @@ static int pwm_break_dt_configure(struct stm32_pwmtimer_s *priv); static int pwm_sync_configure(struct stm32_pwmtimer_s *priv, uint8_t trgo); #endif -#if defined(HAVE_PWM_COMPLEMENTARY) && defined(CONFIG_STM32H7_PWM_LL_OPS) +#if defined(HAVE_PWM_COMPLEMENTARY) && defined(CONFIG_STM32_PWM_LL_OPS) static int pwm_deadtime_update(struct pwm_lowerhalf_s *dev, uint8_t dt); #endif -#ifdef CONFIG_STM32H7_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS static uint32_t pwm_ccr_get(struct pwm_lowerhalf_s *dev, uint8_t index); #endif @@ -356,7 +356,7 @@ static const struct pwm_ops_s g_pwmops = .ioctl = pwm_ioctl, }; -#ifdef CONFIG_STM32H7_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS static const struct stm32_pwm_ops_s g_llpwmops = { .configure = pwm_configure, @@ -379,138 +379,138 @@ static const struct stm32_pwm_ops_s g_llpwmops = }; #endif -#ifdef CONFIG_STM32H7_TIM1_PWM +#ifdef CONFIG_STM32_TIM1_PWM static struct stm32_pwmchan_s g_pwm1channels[] = { /* TIM1 has 4 channels, 4 complementary */ -#ifdef CONFIG_STM32H7_TIM1_CHANNEL1 +#ifdef CONFIG_STM32_TIM1_CHANNEL1 { .channel = 1, - .mode = CONFIG_STM32H7_TIM1_CH1MODE, + .mode = CONFIG_STM32_TIM1_CH1MODE, #ifdef HAVE_BREAK .brk = { -#ifdef CONFIG_STM32H7_TIM1_BREAK1 +#ifdef CONFIG_STM32_TIM1_BREAK1 .en1 = 1, - .pol1 = CONFIG_STM32H7_TIM1_BRK1POL, + .pol1 = CONFIG_STM32_TIM1_BRK1POL, #endif -#ifdef CONFIG_STM32H7_TIM1_BREAK2 +#ifdef CONFIG_STM32_TIM1_BREAK2 .en2 = 1, - .pol2 = CONFIG_STM32H7_TIM1_BRK2POL, - .flt2 = CONFIG_STM32H7_TIM1_BRK2FLT, + .pol2 = CONFIG_STM32_TIM1_BRK2POL, + .flt2 = CONFIG_STM32_TIM1_BRK2FLT, #endif }, #endif -#ifdef CONFIG_STM32H7_TIM1_CH1OUT +#ifdef CONFIG_STM32_TIM1_CH1OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM1_CH1POL, - .idle = CONFIG_STM32H7_TIM1_CH1IDLE, + .pol = CONFIG_STM32_TIM1_CH1POL, + .idle = CONFIG_STM32_TIM1_CH1IDLE, .pincfg = PWM_TIM1_CH1CFG, }, #endif -#ifdef CONFIG_STM32H7_TIM1_CH1NOUT +#ifdef CONFIG_STM32_TIM1_CH1NOUT .out2 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM1_CH1NPOL, - .idle = CONFIG_STM32H7_TIM1_CH1NIDLE, + .pol = CONFIG_STM32_TIM1_CH1NPOL, + .idle = CONFIG_STM32_TIM1_CH1NIDLE, .pincfg = PWM_TIM1_CH1NCFG, } #endif }, #endif -#ifdef CONFIG_STM32H7_TIM1_CHANNEL2 +#ifdef CONFIG_STM32_TIM1_CHANNEL2 { .channel = 2, - .mode = CONFIG_STM32H7_TIM1_CH2MODE, -#ifdef CONFIG_STM32H7_TIM1_CH2OUT + .mode = CONFIG_STM32_TIM1_CH2MODE, +#ifdef CONFIG_STM32_TIM1_CH2OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM1_CH2POL, - .idle = CONFIG_STM32H7_TIM1_CH2IDLE, + .pol = CONFIG_STM32_TIM1_CH2POL, + .idle = CONFIG_STM32_TIM1_CH2IDLE, .pincfg = PWM_TIM1_CH2CFG, }, #endif -#ifdef CONFIG_STM32H7_TIM1_CH2NOUT +#ifdef CONFIG_STM32_TIM1_CH2NOUT .out2 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM1_CH2NPOL, - .idle = CONFIG_STM32H7_TIM1_CH2NIDLE, + .pol = CONFIG_STM32_TIM1_CH2NPOL, + .idle = CONFIG_STM32_TIM1_CH2NIDLE, .pincfg = PWM_TIM1_CH2NCFG, } #endif }, #endif -#ifdef CONFIG_STM32H7_TIM1_CHANNEL3 +#ifdef CONFIG_STM32_TIM1_CHANNEL3 { .channel = 3, - .mode = CONFIG_STM32H7_TIM1_CH3MODE, -#ifdef CONFIG_STM32H7_TIM1_CH3OUT + .mode = CONFIG_STM32_TIM1_CH3MODE, +#ifdef CONFIG_STM32_TIM1_CH3OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM1_CH3POL, - .idle = CONFIG_STM32H7_TIM1_CH3IDLE, + .pol = CONFIG_STM32_TIM1_CH3POL, + .idle = CONFIG_STM32_TIM1_CH3IDLE, .pincfg = PWM_TIM1_CH3CFG, }, #endif -#ifdef CONFIG_STM32H7_TIM1_CH3NOUT +#ifdef CONFIG_STM32_TIM1_CH3NOUT .out2 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM1_CH3NPOL, - .idle = CONFIG_STM32H7_TIM1_CH3NIDLE, + .pol = CONFIG_STM32_TIM1_CH3NPOL, + .idle = CONFIG_STM32_TIM1_CH3NIDLE, .pincfg = PWM_TIM1_CH3NCFG, } #endif }, #endif -#ifdef CONFIG_STM32H7_TIM1_CHANNEL4 +#ifdef CONFIG_STM32_TIM1_CHANNEL4 { .channel = 4, - .mode = CONFIG_STM32H7_TIM1_CH4MODE, -#ifdef CONFIG_STM32H7_TIM1_CH4OUT + .mode = CONFIG_STM32_TIM1_CH4MODE, +#ifdef CONFIG_STM32_TIM1_CH4OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM1_CH4POL, - .idle = CONFIG_STM32H7_TIM1_CH4IDLE, + .pol = CONFIG_STM32_TIM1_CH4POL, + .idle = CONFIG_STM32_TIM1_CH4IDLE, .pincfg = PWM_TIM1_CH4CFG, } #endif }, #endif -#ifdef CONFIG_STM32H7_TIM1_CHANNEL5 +#ifdef CONFIG_STM32_TIM1_CHANNEL5 { .channel = 5, - .mode = CONFIG_STM32H7_TIM1_CH5MODE, -#ifdef CONFIG_STM32H7_TIM1_CH5OUT + .mode = CONFIG_STM32_TIM1_CH5MODE, +#ifdef CONFIG_STM32_TIM1_CH5OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM1_CH5POL, - .idle = CONFIG_STM32H7_TIM1_CH5IDLE, + .pol = CONFIG_STM32_TIM1_CH5POL, + .idle = CONFIG_STM32_TIM1_CH5IDLE, .pincfg = 0, /* Not available externally */ } #endif }, #endif -#ifdef CONFIG_STM32H7_TIM1_CHANNEL6 +#ifdef CONFIG_STM32_TIM1_CHANNEL6 { .channel = 6, - .mode = CONFIG_STM32H7_TIM1_CH6MODE, -#ifdef CONFIG_STM32H7_TIM1_CH6OUT + .mode = CONFIG_STM32_TIM1_CH6MODE, +#ifdef CONFIG_STM32_TIM1_CH6OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM1_CH6POL, - .idle = CONFIG_STM32H7_TIM1_CH6IDLE, + .pol = CONFIG_STM32_TIM1_CH6POL, + .idle = CONFIG_STM32_TIM1_CH6IDLE, .pincfg = 0, /* Not available externally */ } #endif @@ -521,18 +521,18 @@ static struct stm32_pwmchan_s g_pwm1channels[] = static struct stm32_pwmtimer_s g_pwm1dev = { .ops = &g_pwmops, -#ifdef CONFIG_STM32H7_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS .llops = &g_llpwmops, #endif .timid = 1, .chan_num = PWM_TIM1_NCHANNELS, .channels = g_pwm1channels, .timtype = TIMTYPE_TIM1, - .mode = CONFIG_STM32H7_TIM1_MODE, - .lock = CONFIG_STM32H7_TIM1_LOCK, - .t_dts = CONFIG_STM32H7_TIM1_TDTS, + .mode = CONFIG_STM32_TIM1_MODE, + .lock = CONFIG_STM32_TIM1_LOCK, + .t_dts = CONFIG_STM32_TIM1_TDTS, #ifdef HAVE_PWM_COMPLEMENTARY - .deadtime = CONFIG_STM32H7_TIM1_DEADTIME, + .deadtime = CONFIG_STM32_TIM1_DEADTIME, #endif #if defined(HAVE_TRGO) && defined(STM32_TIM1_TRGO) .trgo = STM32_TIM1_TRGO, @@ -540,72 +540,72 @@ static struct stm32_pwmtimer_s g_pwm1dev = .base = STM32_TIM1_BASE, .pclk = TIMCLK_TIM1, }; -#endif /* CONFIG_STM32H7_TIM1_PWM */ +#endif /* CONFIG_STM32_TIM1_PWM */ -#ifdef CONFIG_STM32H7_TIM2_PWM +#ifdef CONFIG_STM32_TIM2_PWM static struct stm32_pwmchan_s g_pwm2channels[] = { /* TIM2 has 4 channels */ -#ifdef CONFIG_STM32H7_TIM2_CHANNEL1 +#ifdef CONFIG_STM32_TIM2_CHANNEL1 { .channel = 1, - .mode = CONFIG_STM32H7_TIM2_CH1MODE, -#ifdef CONFIG_STM32H7_TIM2_CH1OUT + .mode = CONFIG_STM32_TIM2_CH1MODE, +#ifdef CONFIG_STM32_TIM2_CH1OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM2_CH1POL, - .idle = CONFIG_STM32H7_TIM2_CH1IDLE, + .pol = CONFIG_STM32_TIM2_CH1POL, + .idle = CONFIG_STM32_TIM2_CH1IDLE, .pincfg = PWM_TIM2_CH1CFG, } #endif /* No complementary outputs */ }, #endif -#ifdef CONFIG_STM32H7_TIM2_CHANNEL2 +#ifdef CONFIG_STM32_TIM2_CHANNEL2 { .channel = 2, - .mode = CONFIG_STM32H7_TIM2_CH2MODE, -#ifdef CONFIG_STM32H7_TIM2_CH2OUT + .mode = CONFIG_STM32_TIM2_CH2MODE, +#ifdef CONFIG_STM32_TIM2_CH2OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM2_CH2POL, - .idle = CONFIG_STM32H7_TIM2_CH2IDLE, + .pol = CONFIG_STM32_TIM2_CH2POL, + .idle = CONFIG_STM32_TIM2_CH2IDLE, .pincfg = PWM_TIM2_CH2CFG, } #endif /* No complementary outputs */ }, #endif -#ifdef CONFIG_STM32H7_TIM2_CHANNEL3 +#ifdef CONFIG_STM32_TIM2_CHANNEL3 { .channel = 3, - .mode = CONFIG_STM32H7_TIM2_CH3MODE, -#ifdef CONFIG_STM32H7_TIM2_CH3OUT + .mode = CONFIG_STM32_TIM2_CH3MODE, +#ifdef CONFIG_STM32_TIM2_CH3OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM2_CH3POL, - .idle = CONFIG_STM32H7_TIM2_CH3IDLE, + .pol = CONFIG_STM32_TIM2_CH3POL, + .idle = CONFIG_STM32_TIM2_CH3IDLE, .pincfg = PWM_TIM2_CH3CFG, } #endif /* No complementary outputs */ }, #endif -#ifdef CONFIG_STM32H7_TIM2_CHANNEL4 +#ifdef CONFIG_STM32_TIM2_CHANNEL4 { .channel = 4, - .mode = CONFIG_STM32H7_TIM2_CH4MODE, -#ifdef CONFIG_STM32H7_TIM2_CH4OUT + .mode = CONFIG_STM32_TIM2_CH4MODE, +#ifdef CONFIG_STM32_TIM2_CH4OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM2_CH4POL, - .idle = CONFIG_STM32H7_TIM2_CH4IDLE, + .pol = CONFIG_STM32_TIM2_CH4POL, + .idle = CONFIG_STM32_TIM2_CH4IDLE, .pincfg = PWM_TIM2_CH4CFG, } #endif @@ -617,14 +617,14 @@ static struct stm32_pwmchan_s g_pwm2channels[] = static struct stm32_pwmtimer_s g_pwm2dev = { .ops = &g_pwmops, -#ifdef CONFIG_STM32H7_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS .llops = &g_llpwmops, #endif .timid = 2, .chan_num = PWM_TIM2_NCHANNELS, .channels = g_pwm2channels, .timtype = TIMTYPE_TIM2, - .mode = CONFIG_STM32H7_TIM2_MODE, + .mode = CONFIG_STM32_TIM2_MODE, .lock = 0, /* No lock */ .t_dts = 0, /* No t_dts */ #ifdef HAVE_PWM_COMPLEMENTARY @@ -636,72 +636,72 @@ static struct stm32_pwmtimer_s g_pwm2dev = .base = STM32_TIM2_BASE, .pclk = TIMCLK_TIM2, }; -#endif /* CONFIG_STM32H7_TIM2_PWM */ +#endif /* CONFIG_STM32_TIM2_PWM */ -#ifdef CONFIG_STM32H7_TIM3_PWM +#ifdef CONFIG_STM32_TIM3_PWM static struct stm32_pwmchan_s g_pwm3channels[] = { /* TIM3 has 4 channels */ -#ifdef CONFIG_STM32H7_TIM3_CHANNEL1 +#ifdef CONFIG_STM32_TIM3_CHANNEL1 { .channel = 1, - .mode = CONFIG_STM32H7_TIM3_CH1MODE, -#ifdef CONFIG_STM32H7_TIM3_CH1OUT + .mode = CONFIG_STM32_TIM3_CH1MODE, +#ifdef CONFIG_STM32_TIM3_CH1OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM3_CH1POL, - .idle = CONFIG_STM32H7_TIM3_CH1IDLE, + .pol = CONFIG_STM32_TIM3_CH1POL, + .idle = CONFIG_STM32_TIM3_CH1IDLE, .pincfg = PWM_TIM3_CH1CFG, } #endif /* No complementary outputs */ }, #endif -#ifdef CONFIG_STM32H7_TIM3_CHANNEL2 +#ifdef CONFIG_STM32_TIM3_CHANNEL2 { .channel = 2, - .mode = CONFIG_STM32H7_TIM3_CH2MODE, -#ifdef CONFIG_STM32H7_TIM3_CH2OUT + .mode = CONFIG_STM32_TIM3_CH2MODE, +#ifdef CONFIG_STM32_TIM3_CH2OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM3_CH2POL, - .idle = CONFIG_STM32H7_TIM3_CH2IDLE, + .pol = CONFIG_STM32_TIM3_CH2POL, + .idle = CONFIG_STM32_TIM3_CH2IDLE, .pincfg = PWM_TIM3_CH2CFG, } #endif /* No complementary outputs */ }, #endif -#ifdef CONFIG_STM32H7_TIM3_CHANNEL3 +#ifdef CONFIG_STM32_TIM3_CHANNEL3 { .channel = 3, - .mode = CONFIG_STM32H7_TIM3_CH3MODE, -#ifdef CONFIG_STM32H7_TIM3_CH3OUT + .mode = CONFIG_STM32_TIM3_CH3MODE, +#ifdef CONFIG_STM32_TIM3_CH3OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM3_CH3POL, - .idle = CONFIG_STM32H7_TIM3_CH3IDLE, + .pol = CONFIG_STM32_TIM3_CH3POL, + .idle = CONFIG_STM32_TIM3_CH3IDLE, .pincfg = PWM_TIM3_CH3CFG, } #endif /* No complementary outputs */ }, #endif -#ifdef CONFIG_STM32H7_TIM3_CHANNEL4 +#ifdef CONFIG_STM32_TIM3_CHANNEL4 { .channel = 4, - .mode = CONFIG_STM32H7_TIM3_CH4MODE, -#ifdef CONFIG_STM32H7_TIM3_CH4OUT + .mode = CONFIG_STM32_TIM3_CH4MODE, +#ifdef CONFIG_STM32_TIM3_CH4OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM3_CH4POL, - .idle = CONFIG_STM32H7_TIM3_CH4IDLE, + .pol = CONFIG_STM32_TIM3_CH4POL, + .idle = CONFIG_STM32_TIM3_CH4IDLE, .pincfg = PWM_TIM3_CH4CFG, } #endif @@ -713,14 +713,14 @@ static struct stm32_pwmchan_s g_pwm3channels[] = static struct stm32_pwmtimer_s g_pwm3dev = { .ops = &g_pwmops, -#ifdef CONFIG_STM32H7_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS .llops = &g_llpwmops, #endif .timid = 3, .chan_num = PWM_TIM3_NCHANNELS, .channels = g_pwm3channels, .timtype = TIMTYPE_TIM3, - .mode = CONFIG_STM32H7_TIM3_MODE, + .mode = CONFIG_STM32_TIM3_MODE, .lock = 0, /* No lock */ .t_dts = 0, /* No t_dts */ #ifdef HAVE_PWM_COMPLEMENTARY @@ -732,72 +732,72 @@ static struct stm32_pwmtimer_s g_pwm3dev = .base = STM32_TIM3_BASE, .pclk = TIMCLK_TIM3, }; -#endif /* CONFIG_STM32H7_TIM3_PWM */ +#endif /* CONFIG_STM32_TIM3_PWM */ -#ifdef CONFIG_STM32H7_TIM4_PWM +#ifdef CONFIG_STM32_TIM4_PWM static struct stm32_pwmchan_s g_pwm4channels[] = { /* TIM4 has 4 channels */ -#ifdef CONFIG_STM32H7_TIM4_CHANNEL1 +#ifdef CONFIG_STM32_TIM4_CHANNEL1 { .channel = 1, - .mode = CONFIG_STM32H7_TIM4_CH1MODE, -#ifdef CONFIG_STM32H7_TIM4_CH1OUT + .mode = CONFIG_STM32_TIM4_CH1MODE, +#ifdef CONFIG_STM32_TIM4_CH1OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM4_CH1POL, - .idle = CONFIG_STM32H7_TIM4_CH1IDLE, + .pol = CONFIG_STM32_TIM4_CH1POL, + .idle = CONFIG_STM32_TIM4_CH1IDLE, .pincfg = PWM_TIM4_CH1CFG, } #endif /* No complementary outputs */ }, #endif -#ifdef CONFIG_STM32H7_TIM4_CHANNEL2 +#ifdef CONFIG_STM32_TIM4_CHANNEL2 { .channel = 2, - .mode = CONFIG_STM32H7_TIM4_CH2MODE, -#ifdef CONFIG_STM32H7_TIM4_CH2OUT + .mode = CONFIG_STM32_TIM4_CH2MODE, +#ifdef CONFIG_STM32_TIM4_CH2OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM4_CH2POL, - .idle = CONFIG_STM32H7_TIM4_CH2IDLE, + .pol = CONFIG_STM32_TIM4_CH2POL, + .idle = CONFIG_STM32_TIM4_CH2IDLE, .pincfg = PWM_TIM4_CH2CFG, } #endif /* No complementary outputs */ }, #endif -#ifdef CONFIG_STM32H7_TIM4_CHANNEL3 +#ifdef CONFIG_STM32_TIM4_CHANNEL3 { .channel = 3, - .mode = CONFIG_STM32H7_TIM4_CH3MODE, -#ifdef CONFIG_STM32H7_TIM4_CH3OUT + .mode = CONFIG_STM32_TIM4_CH3MODE, +#ifdef CONFIG_STM32_TIM4_CH3OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM4_CH3POL, - .idle = CONFIG_STM32H7_TIM4_CH3IDLE, + .pol = CONFIG_STM32_TIM4_CH3POL, + .idle = CONFIG_STM32_TIM4_CH3IDLE, .pincfg = PWM_TIM4_CH3CFG, } #endif /* No complementary outputs */ }, #endif -#ifdef CONFIG_STM32H7_TIM4_CHANNEL4 +#ifdef CONFIG_STM32_TIM4_CHANNEL4 { .channel = 4, - .mode = CONFIG_STM32H7_TIM4_CH4MODE, -#ifdef CONFIG_STM32H7_TIM4_CH4OUT + .mode = CONFIG_STM32_TIM4_CH4MODE, +#ifdef CONFIG_STM32_TIM4_CH4OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM4_CH4POL, - .idle = CONFIG_STM32H7_TIM4_CH4IDLE, + .pol = CONFIG_STM32_TIM4_CH4POL, + .idle = CONFIG_STM32_TIM4_CH4IDLE, .pincfg = PWM_TIM4_CH4CFG, } #endif @@ -809,14 +809,14 @@ static struct stm32_pwmchan_s g_pwm4channels[] = static struct stm32_pwmtimer_s g_pwm4dev = { .ops = &g_pwmops, -#ifdef CONFIG_STM32H7_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS .llops = &g_llpwmops, #endif .timid = 4, .chan_num = PWM_TIM4_NCHANNELS, .channels = g_pwm4channels, .timtype = TIMTYPE_TIM4, - .mode = CONFIG_STM32H7_TIM4_MODE, + .mode = CONFIG_STM32_TIM4_MODE, .lock = 0, /* No lock */ .t_dts = 0, /* No t_dts */ #ifdef HAVE_PWM_COMPLEMENTARY @@ -828,71 +828,71 @@ static struct stm32_pwmtimer_s g_pwm4dev = .base = STM32_TIM4_BASE, .pclk = TIMCLK_TIM4, }; -#endif /* CONFIG_STM32H7_TIM4_PWM */ +#endif /* CONFIG_STM32_TIM4_PWM */ -#ifdef CONFIG_STM32H7_TIM5_PWM +#ifdef CONFIG_STM32_TIM5_PWM static struct stm32_pwmchan_s g_pwm5channels[] = { /* TIM5 has 4 channels */ -#ifdef CONFIG_STM32H7_TIM5_CHANNEL1 +#ifdef CONFIG_STM32_TIM5_CHANNEL1 { .channel = 1, - .mode = CONFIG_STM32H7_TIM5_CH1MODE, -#ifdef CONFIG_STM32H7_TIM5_CH1OUT + .mode = CONFIG_STM32_TIM5_CH1MODE, +#ifdef CONFIG_STM32_TIM5_CH1OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM5_CH1POL, - .idle = CONFIG_STM32H7_TIM5_CH1IDLE, + .pol = CONFIG_STM32_TIM5_CH1POL, + .idle = CONFIG_STM32_TIM5_CH1IDLE, .pincfg = PWM_TIM5_CH1CFG, } #endif /* No complementary outputs */ }, #endif -#ifdef CONFIG_STM32H7_TIM5_CHANNEL2 +#ifdef CONFIG_STM32_TIM5_CHANNEL2 { .channel = 2, - .mode = CONFIG_STM32H7_TIM5_CH2MODE, -#ifdef CONFIG_STM32H7_TIM5_CH2OUT + .mode = CONFIG_STM32_TIM5_CH2MODE, +#ifdef CONFIG_STM32_TIM5_CH2OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM5_CH2POL, - .idle = CONFIG_STM32H7_TIM5_CH2IDLE, + .pol = CONFIG_STM32_TIM5_CH2POL, + .idle = CONFIG_STM32_TIM5_CH2IDLE, .pincfg = PWM_TIM5_CH2CFG, } #endif /* No complementary outputs */ }, #endif -#ifdef CONFIG_STM32H7_TIM5_CHANNEL3 +#ifdef CONFIG_STM32_TIM5_CHANNEL3 { .channel = 3, - .mode = CONFIG_STM32H7_TIM5_CH3MODE, -#ifdef CONFIG_STM32H7_TIM5_CH3OUT + .mode = CONFIG_STM32_TIM5_CH3MODE, +#ifdef CONFIG_STM32_TIM5_CH3OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM5_CH3POL, - .idle = CONFIG_STM32H7_TIM5_CH3IDLE, + .pol = CONFIG_STM32_TIM5_CH3POL, + .idle = CONFIG_STM32_TIM5_CH3IDLE, .pincfg = PWM_TIM5_CH3CFG, } #endif }, #endif -#ifdef CONFIG_STM32H7_TIM5_CHANNEL4 +#ifdef CONFIG_STM32_TIM5_CHANNEL4 { .channel = 4, - .mode = CONFIG_STM32H7_TIM5_CH4MODE, -#ifdef CONFIG_STM32H7_TIM5_CH4OUT + .mode = CONFIG_STM32_TIM5_CH4MODE, +#ifdef CONFIG_STM32_TIM5_CH4OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM5_CH4POL, - .idle = CONFIG_STM32H7_TIM5_CH4IDLE, + .pol = CONFIG_STM32_TIM5_CH4POL, + .idle = CONFIG_STM32_TIM5_CH4IDLE, .pincfg = PWM_TIM5_CH4CFG, } #endif @@ -903,14 +903,14 @@ static struct stm32_pwmchan_s g_pwm5channels[] = static struct stm32_pwmtimer_s g_pwm5dev = { .ops = &g_pwmops, -#ifdef CONFIG_STM32H7_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS .llops = &g_llpwmops, #endif .timid = 5, .chan_num = PWM_TIM5_NCHANNELS, .channels = g_pwm5channels, .timtype = TIMTYPE_TIM5, - .mode = CONFIG_STM32H7_TIM5_MODE, + .mode = CONFIG_STM32_TIM5_MODE, .lock = 0, /* No lock */ .t_dts = 0, /* No t_dts */ #ifdef HAVE_PWM_COMPLEMENTARY @@ -922,140 +922,140 @@ static struct stm32_pwmtimer_s g_pwm5dev = .base = STM32_TIM5_BASE, .pclk = TIMCLK_TIM5, }; -#endif /* CONFIG_STM32H7_TIM5_PWM */ +#endif /* CONFIG_STM32_TIM5_PWM */ -#ifdef CONFIG_STM32H7_TIM8_PWM +#ifdef CONFIG_STM32_TIM8_PWM static struct stm32_pwmchan_s g_pwm8channels[] = { /* TIM8 has 4 channels, 4 complementary */ -#ifdef CONFIG_STM32H7_TIM8_CHANNEL1 +#ifdef CONFIG_STM32_TIM8_CHANNEL1 { .channel = 1, - .mode = CONFIG_STM32H7_TIM8_CH1MODE, + .mode = CONFIG_STM32_TIM8_CH1MODE, #ifdef HAVE_BREAK .brk = { -#ifdef CONFIG_STM32H7_TIM8_BREAK1 +#ifdef CONFIG_STM32_TIM8_BREAK1 .en1 = 1, - .pol1 = CONFIG_STM32H7_TIM8_BRK1POL, + .pol1 = CONFIG_STM32_TIM8_BRK1POL, #endif -#ifdef CONFIG_STM32H7_TIM8_BREAK2 +#ifdef CONFIG_STM32_TIM8_BREAK2 .en2 = 1, - .pol2 = CONFIG_STM32H7_TIM8_BRK2POL, - .flt2 = CONFIG_STM32H7_TIM8_BRK2FLT, + .pol2 = CONFIG_STM32_TIM8_BRK2POL, + .flt2 = CONFIG_STM32_TIM8_BRK2FLT, #endif }, #endif -#ifdef CONFIG_STM32H7_TIM8_CH1OUT +#ifdef CONFIG_STM32_TIM8_CH1OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM8_CH1POL, - .idle = CONFIG_STM32H7_TIM8_CH1IDLE, + .pol = CONFIG_STM32_TIM8_CH1POL, + .idle = CONFIG_STM32_TIM8_CH1IDLE, .pincfg = PWM_TIM8_CH1CFG, }, #endif -#ifdef CONFIG_STM32H7_TIM8_CH1NOUT +#ifdef CONFIG_STM32_TIM8_CH1NOUT .out2 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM8_CH1NPOL, - .idle = CONFIG_STM32H7_TIM8_CH1NIDLE, + .pol = CONFIG_STM32_TIM8_CH1NPOL, + .idle = CONFIG_STM32_TIM8_CH1NIDLE, .pincfg = PWM_TIM8_CH1NCFG, } #endif }, #endif -#ifdef CONFIG_STM32H7_TIM8_CHANNEL2 +#ifdef CONFIG_STM32_TIM8_CHANNEL2 { .channel = 2, - .mode = CONFIG_STM32H7_TIM8_CH2MODE, -#ifdef CONFIG_STM32H7_TIM8_CH2OUT + .mode = CONFIG_STM32_TIM8_CH2MODE, +#ifdef CONFIG_STM32_TIM8_CH2OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM8_CH2POL, - .idle = CONFIG_STM32H7_TIM8_CH2IDLE, + .pol = CONFIG_STM32_TIM8_CH2POL, + .idle = CONFIG_STM32_TIM8_CH2IDLE, .pincfg = PWM_TIM8_CH2CFG, }, #endif -#ifdef CONFIG_STM32H7_TIM8_CH2NOUT +#ifdef CONFIG_STM32_TIM8_CH2NOUT .out2 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM8_CH2NPOL, - .idle = CONFIG_STM32H7_TIM8_CH2NIDLE, + .pol = CONFIG_STM32_TIM8_CH2NPOL, + .idle = CONFIG_STM32_TIM8_CH2NIDLE, .pincfg = PWM_TIM8_CH2NCFG, } #endif }, #endif -#ifdef CONFIG_STM32H7_TIM8_CHANNEL3 +#ifdef CONFIG_STM32_TIM8_CHANNEL3 { .channel = 3, - .mode = CONFIG_STM32H7_TIM8_CH3MODE, -#ifdef CONFIG_STM32H7_TIM8_CH3OUT + .mode = CONFIG_STM32_TIM8_CH3MODE, +#ifdef CONFIG_STM32_TIM8_CH3OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM8_CH3POL, - .idle = CONFIG_STM32H7_TIM8_CH3IDLE, + .pol = CONFIG_STM32_TIM8_CH3POL, + .idle = CONFIG_STM32_TIM8_CH3IDLE, .pincfg = PWM_TIM8_CH3CFG, }, #endif -#ifdef CONFIG_STM32H7_TIM8_CH3NOUT +#ifdef CONFIG_STM32_TIM8_CH3NOUT .out2 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM8_CH3NPOL, - .idle = CONFIG_STM32H7_TIM8_CH3NIDLE, + .pol = CONFIG_STM32_TIM8_CH3NPOL, + .idle = CONFIG_STM32_TIM8_CH3NIDLE, .pincfg = PWM_TIM8_CH3NCFG, } #endif }, #endif -#ifdef CONFIG_STM32H7_TIM8_CHANNEL4 +#ifdef CONFIG_STM32_TIM8_CHANNEL4 { .channel = 4, - .mode = CONFIG_STM32H7_TIM8_CH4MODE, -#ifdef CONFIG_STM32H7_TIM8_CH4OUT + .mode = CONFIG_STM32_TIM8_CH4MODE, +#ifdef CONFIG_STM32_TIM8_CH4OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM8_CH4POL, - .idle = CONFIG_STM32H7_TIM8_CH4IDLE, + .pol = CONFIG_STM32_TIM8_CH4POL, + .idle = CONFIG_STM32_TIM8_CH4IDLE, .pincfg = PWM_TIM8_CH4CFG, } #endif }, #endif -#ifdef CONFIG_STM32H7_TIM8_CHANNEL5 +#ifdef CONFIG_STM32_TIM8_CHANNEL5 { .channel = 5, - .mode = CONFIG_STM32H7_TIM8_CH5MODE, -#ifdef CONFIG_STM32H7_TIM8_CH5OUT + .mode = CONFIG_STM32_TIM8_CH5MODE, +#ifdef CONFIG_STM32_TIM8_CH5OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM8_CH5POL, - .idle = CONFIG_STM32H7_TIM8_CH5IDLE, + .pol = CONFIG_STM32_TIM8_CH5POL, + .idle = CONFIG_STM32_TIM8_CH5IDLE, .pincfg = 0, /* Not available externally */ } #endif }, #endif -#ifdef CONFIG_STM32H7_TIM8_CHANNEL6 +#ifdef CONFIG_STM32_TIM8_CHANNEL6 { .channel = 6, - .mode = CONFIG_STM32H7_TIM8_CH6MODE, -#ifdef CONFIG_STM32H7_TIM8_CH6OUT + .mode = CONFIG_STM32_TIM8_CH6MODE, +#ifdef CONFIG_STM32_TIM8_CH6OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM8_CH6POL, - .idle = CONFIG_STM32H7_TIM8_CH6IDLE, + .pol = CONFIG_STM32_TIM8_CH6POL, + .idle = CONFIG_STM32_TIM8_CH6IDLE, .pincfg = 0, /* Not available externally */ } #endif @@ -1066,18 +1066,18 @@ static struct stm32_pwmchan_s g_pwm8channels[] = static struct stm32_pwmtimer_s g_pwm8dev = { .ops = &g_pwmops, -#ifdef CONFIG_STM32H7_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS .llops = &g_llpwmops, #endif .timid = 8, .chan_num = PWM_TIM8_NCHANNELS, .channels = g_pwm8channels, .timtype = TIMTYPE_TIM8, - .mode = CONFIG_STM32H7_TIM8_MODE, - .lock = CONFIG_STM32H7_TIM8_LOCK, - .t_dts = CONFIG_STM32H7_TIM8_TDTS, + .mode = CONFIG_STM32_TIM8_MODE, + .lock = CONFIG_STM32_TIM8_LOCK, + .t_dts = CONFIG_STM32_TIM8_TDTS, #ifdef HAVE_PWM_COMPLEMENTARY - .deadtime = CONFIG_STM32H7_TIM8_DEADTIME, + .deadtime = CONFIG_STM32_TIM8_DEADTIME, #endif #if defined(HAVE_TRGO) && defined(STM32_TIM8_TRGO) .trgo = STM32_TIM8_TRGO, @@ -1085,40 +1085,40 @@ static struct stm32_pwmtimer_s g_pwm8dev = .base = STM32_TIM8_BASE, .pclk = TIMCLK_TIM8, }; -#endif /* CONFIG_STM32H7_TIM8_PWM */ +#endif /* CONFIG_STM32_TIM8_PWM */ -#ifdef CONFIG_STM32H7_TIM12_PWM +#ifdef CONFIG_STM32_TIM12_PWM static struct stm32_pwmchan_s g_pwm12channels[] = { /* TIM12 has 2 channels */ -#ifdef CONFIG_STM32H7_TIM12_CHANNEL1 +#ifdef CONFIG_STM32_TIM12_CHANNEL1 { .channel = 1, - .mode = CONFIG_STM32H7_TIM12_CH1MODE, -#ifdef CONFIG_STM32H7_TIM12_CH1OUT + .mode = CONFIG_STM32_TIM12_CH1MODE, +#ifdef CONFIG_STM32_TIM12_CH1OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM12_CH1POL, - .idle = CONFIG_STM32H7_TIM12_CH1IDLE, + .pol = CONFIG_STM32_TIM12_CH1POL, + .idle = CONFIG_STM32_TIM12_CH1IDLE, .pincfg = PWM_TIM12_CH1CFG, } #endif /* No complementary outputs */ }, #endif -#ifdef CONFIG_STM32H7_TIM12_CHANNEL2 +#ifdef CONFIG_STM32_TIM12_CHANNEL2 { .channel = 2, - .mode = CONFIG_STM32H7_TIM12_CH2MODE, -#ifdef CONFIG_STM32H7_TIM12_CH2OUT + .mode = CONFIG_STM32_TIM12_CH2MODE, +#ifdef CONFIG_STM32_TIM12_CH2OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM12_CH2POL, - .idle = CONFIG_STM32H7_TIM12_CH2IDLE, + .pol = CONFIG_STM32_TIM12_CH2POL, + .idle = CONFIG_STM32_TIM12_CH2IDLE, .pincfg = PWM_TIM12_CH2CFG, } #endif @@ -1130,7 +1130,7 @@ static struct stm32_pwmchan_s g_pwm12channels[] = static struct stm32_pwmtimer_s g_pwm12dev = { .ops = &g_pwmops, -#ifdef CONFIG_STM32H7_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS .llops = &g_llpwmops, #endif .timid = 12, @@ -1149,24 +1149,24 @@ static struct stm32_pwmtimer_s g_pwm12dev = .base = STM32_TIM12_BASE, .pclk = TIMCLK_TIM12, }; -#endif /* CONFIG_STM32H7_TIM12_PWM */ +#endif /* CONFIG_STM32_TIM12_PWM */ -#ifdef CONFIG_STM32H7_TIM13_PWM +#ifdef CONFIG_STM32_TIM13_PWM static struct stm32_pwmchan_s g_pwm13channels[] = { /* TIM13 has 1 channel */ -#ifdef CONFIG_STM32H7_TIM13_CHANNEL1 +#ifdef CONFIG_STM32_TIM13_CHANNEL1 { .channel = 1, - .mode = CONFIG_STM32H7_TIM13_CH1MODE, -#ifdef CONFIG_STM32H7_TIM13_CH1OUT + .mode = CONFIG_STM32_TIM13_CH1MODE, +#ifdef CONFIG_STM32_TIM13_CH1OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM13_CH1POL, - .idle = CONFIG_STM32H7_TIM13_CH1IDLE, + .pol = CONFIG_STM32_TIM13_CH1POL, + .idle = CONFIG_STM32_TIM13_CH1IDLE, .pincfg = PWM_TIM13_CH1CFG, } #endif @@ -1178,7 +1178,7 @@ static struct stm32_pwmchan_s g_pwm13channels[] = static struct stm32_pwmtimer_s g_pwm13dev = { .ops = &g_pwmops, -#ifdef CONFIG_STM32H7_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS .llops = &g_llpwmops, #endif .timid = 13, @@ -1197,24 +1197,24 @@ static struct stm32_pwmtimer_s g_pwm13dev = .base = STM32_TIM13_BASE, .pclk = TIMCLK_TIM13, }; -#endif /* CONFIG_STM32H7_TIM13_PWM */ +#endif /* CONFIG_STM32_TIM13_PWM */ -#ifdef CONFIG_STM32H7_TIM14_PWM +#ifdef CONFIG_STM32_TIM14_PWM static struct stm32_pwmchan_s g_pwm14channels[] = { /* TIM14 has 1 channel */ -#ifdef CONFIG_STM32H7_TIM14_CHANNEL1 +#ifdef CONFIG_STM32_TIM14_CHANNEL1 { .channel = 1, - .mode = CONFIG_STM32H7_TIM14_CH1MODE, -#ifdef CONFIG_STM32H7_TIM14_CH1OUT + .mode = CONFIG_STM32_TIM14_CH1MODE, +#ifdef CONFIG_STM32_TIM14_CH1OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM14_CH1POL, - .idle = CONFIG_STM32H7_TIM14_CH1IDLE, + .pol = CONFIG_STM32_TIM14_CH1POL, + .idle = CONFIG_STM32_TIM14_CH1IDLE, .pincfg = PWM_TIM14_CH1CFG, } #endif @@ -1226,7 +1226,7 @@ static struct stm32_pwmchan_s g_pwm14channels[] = static struct stm32_pwmtimer_s g_pwm14dev = { .ops = &g_pwmops, -#ifdef CONFIG_STM32H7_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS .llops = &g_llpwmops, #endif .timid = 14, @@ -1245,58 +1245,58 @@ static struct stm32_pwmtimer_s g_pwm14dev = .base = STM32_TIM14_BASE, .pclk = TIMCLK_TIM14, }; -#endif /* CONFIG_STM32H7_TIM14_PWM */ +#endif /* CONFIG_STM32_TIM14_PWM */ -#ifdef CONFIG_STM32H7_TIM15_PWM +#ifdef CONFIG_STM32_TIM15_PWM static struct stm32_pwmchan_s g_pwm15channels[] = { /* TIM15 has 2 channels, 1 complementary */ -#ifdef CONFIG_STM32H7_TIM15_CHANNEL1 +#ifdef CONFIG_STM32_TIM15_CHANNEL1 { .channel = 1, - .mode = CONFIG_STM32H7_TIM15_CH1MODE, + .mode = CONFIG_STM32_TIM15_CH1MODE, #ifdef HAVE_BREAK .brk = { -#ifdef CONFIG_STM32H7_TIM15_BREAK1 +#ifdef CONFIG_STM32_TIM15_BREAK1 .en1 = 1, - .pol1 = CONFIG_STM32H7_TIM15_BRK1POL, + .pol1 = CONFIG_STM32_TIM15_BRK1POL, #endif /* No BREAK2 */ }, #endif -#ifdef CONFIG_STM32H7_TIM15_CH1OUT +#ifdef CONFIG_STM32_TIM15_CH1OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM15_CH1POL, - .idle = CONFIG_STM32H7_TIM15_CH1IDLE, + .pol = CONFIG_STM32_TIM15_CH1POL, + .idle = CONFIG_STM32_TIM15_CH1IDLE, .pincfg = PWM_TIM15_CH1CFG, }, #endif -#ifdef CONFIG_STM32H7_TIM15_CH1NOUT +#ifdef CONFIG_STM32_TIM15_CH1NOUT .out2 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM15_CH1NPOL, - .idle = CONFIG_STM32H7_TIM15_CH1NIDLE, + .pol = CONFIG_STM32_TIM15_CH1NPOL, + .idle = CONFIG_STM32_TIM15_CH1NIDLE, .pincfg = PWM_TIM15_CH2CFG, } #endif }, #endif -#ifdef CONFIG_STM32H7_TIM15_CHANNEL2 +#ifdef CONFIG_STM32_TIM15_CHANNEL2 { .channel = 2, - .mode = CONFIG_STM32H7_TIM15_CH2MODE, -#ifdef CONFIG_STM32H7_TIM12_CH2OUT + .mode = CONFIG_STM32_TIM15_CH2MODE, +#ifdef CONFIG_STM32_TIM12_CH2OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM15_CH2POL, - .idle = CONFIG_STM32H7_TIM15_CH2IDLE, + .pol = CONFIG_STM32_TIM15_CH2POL, + .idle = CONFIG_STM32_TIM15_CH2IDLE, .pincfg = PWM_TIM15_CH2CFG, } #endif @@ -1308,7 +1308,7 @@ static struct stm32_pwmchan_s g_pwm15channels[] = static struct stm32_pwmtimer_s g_pwm15dev = { .ops = &g_pwmops, -#ifdef CONFIG_STM32H7_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS .llops = &g_llpwmops, #endif .timid = 15, @@ -1316,10 +1316,10 @@ static struct stm32_pwmtimer_s g_pwm15dev = .channels = g_pwm15channels, .timtype = TIMTYPE_TIM15, .mode = STM32_TIMMODE_COUNTUP, - .lock = CONFIG_STM32H7_TIM15_LOCK, - .t_dts = CONFIG_STM32H7_TIM15_TDTS, + .lock = CONFIG_STM32_TIM15_LOCK, + .t_dts = CONFIG_STM32_TIM15_TDTS, #ifdef HAVE_PWM_COMPLEMENTARY - .deadtime = CONFIG_STM32H7_TIM15_DEADTIME, + .deadtime = CONFIG_STM32_TIM15_DEADTIME, #endif #if defined(HAVE_TRGO) && defined(STM32_TIM15_TRGO) .trgo = STM32_TIM15_TRGO, @@ -1327,43 +1327,43 @@ static struct stm32_pwmtimer_s g_pwm15dev = .base = STM32_TIM15_BASE, .pclk = TIMCLK_TIM15, }; -#endif /* CONFIG_STM32H7_TIM15_PWM */ +#endif /* CONFIG_STM32_TIM15_PWM */ -#ifdef CONFIG_STM32H7_TIM16_PWM +#ifdef CONFIG_STM32_TIM16_PWM static struct stm32_pwmchan_s g_pwm16channels[] = { /* TIM16 has 1 channel, 1 complementary */ -#ifdef CONFIG_STM32H7_TIM16_CHANNEL1 +#ifdef CONFIG_STM32_TIM16_CHANNEL1 { .channel = 1, - .mode = CONFIG_STM32H7_TIM16_CH1MODE, + .mode = CONFIG_STM32_TIM16_CH1MODE, #ifdef HAVE_BREAK .brk = { -#ifdef CONFIG_STM32H7_TIM16_BREAK1 +#ifdef CONFIG_STM32_TIM16_BREAK1 .en1 = 1, - .pol1 = CONFIG_STM32H7_TIM16_BRK1POL, + .pol1 = CONFIG_STM32_TIM16_BRK1POL, #endif /* No BREAK2 */ }, #endif -#ifdef CONFIG_STM32H7_TIM16_CH1OUT +#ifdef CONFIG_STM32_TIM16_CH1OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM16_CH1POL, - .idle = CONFIG_STM32H7_TIM16_CH1IDLE, + .pol = CONFIG_STM32_TIM16_CH1POL, + .idle = CONFIG_STM32_TIM16_CH1IDLE, .pincfg = PWM_TIM16_CH1CFG, }, #endif -#ifdef CONFIG_STM32H7_TIM16_CH1NOUT +#ifdef CONFIG_STM32_TIM16_CH1NOUT .out2 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM16_CH1NPOL, - .idle = CONFIG_STM32H7_TIM16_CH1NIDLE, + .pol = CONFIG_STM32_TIM16_CH1NPOL, + .idle = CONFIG_STM32_TIM16_CH1NIDLE, .pincfg = PWM_TIM16_CH2CFG, } #endif @@ -1374,7 +1374,7 @@ static struct stm32_pwmchan_s g_pwm16channels[] = static struct stm32_pwmtimer_s g_pwm16dev = { .ops = &g_pwmops, -#ifdef CONFIG_STM32H7_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS .llops = &g_llpwmops, #endif .timid = 16, @@ -1382,10 +1382,10 @@ static struct stm32_pwmtimer_s g_pwm16dev = .channels = g_pwm16channels, .timtype = TIMTYPE_TIM16, .mode = STM32_TIMMODE_COUNTUP, - .lock = CONFIG_STM32H7_TIM16_LOCK, - .t_dts = CONFIG_STM32H7_TIM16_TDTS, + .lock = CONFIG_STM32_TIM16_LOCK, + .t_dts = CONFIG_STM32_TIM16_TDTS, #ifdef HAVE_PWM_COMPLEMENTARY - .deadtime = CONFIG_STM32H7_TIM16_DEADTIME, + .deadtime = CONFIG_STM32_TIM16_DEADTIME, #endif #if defined(HAVE_TRGO) .trgo = 0, /* TRGO not supported for TIM16 */ @@ -1393,43 +1393,43 @@ static struct stm32_pwmtimer_s g_pwm16dev = .base = STM32_TIM16_BASE, .pclk = TIMCLK_TIM16, }; -#endif /* CONFIG_STM32H7_TIM16_PWM */ +#endif /* CONFIG_STM32_TIM16_PWM */ -#ifdef CONFIG_STM32H7_TIM17_PWM +#ifdef CONFIG_STM32_TIM17_PWM static struct stm32_pwmchan_s g_pwm17channels[] = { /* TIM17 has 1 channel, 1 complementary */ -#ifdef CONFIG_STM32H7_TIM17_CHANNEL1 +#ifdef CONFIG_STM32_TIM17_CHANNEL1 { .channel = 1, - .mode = CONFIG_STM32H7_TIM17_CH1MODE, + .mode = CONFIG_STM32_TIM17_CH1MODE, #ifdef HAVE_BREAK .brk = { -#ifdef CONFIG_STM32H7_TIM17_BREAK1 +#ifdef CONFIG_STM32_TIM17_BREAK1 .en1 = 1, - .pol1 = CONFIG_STM32H7_TIM17_BRK1POL, + .pol1 = CONFIG_STM32_TIM17_BRK1POL, #endif /* No BREAK2 */ }, #endif -#ifdef CONFIG_STM32H7_TIM17_CH1OUT +#ifdef CONFIG_STM32_TIM17_CH1OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM17_CH1POL, - .idle = CONFIG_STM32H7_TIM17_CH1IDLE, + .pol = CONFIG_STM32_TIM17_CH1POL, + .idle = CONFIG_STM32_TIM17_CH1IDLE, .pincfg = PWM_TIM17_CH1CFG, }, #endif -#ifdef CONFIG_STM32H7_TIM17_CH1NOUT +#ifdef CONFIG_STM32_TIM17_CH1NOUT .out2 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM17_CH1NPOL, - .idle = CONFIG_STM32H7_TIM17_CH1NIDLE, + .pol = CONFIG_STM32_TIM17_CH1NPOL, + .idle = CONFIG_STM32_TIM17_CH1NIDLE, .pincfg = PWM_TIM17_CH2CFG, } #endif @@ -1440,7 +1440,7 @@ static struct stm32_pwmchan_s g_pwm17channels[] = static struct stm32_pwmtimer_s g_pwm17dev = { .ops = &g_pwmops, -#ifdef CONFIG_STM32H7_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS .llops = &g_llpwmops, #endif .timid = 17, @@ -1448,10 +1448,10 @@ static struct stm32_pwmtimer_s g_pwm17dev = .channels = g_pwm17channels, .timtype = TIMTYPE_TIM17, .mode = STM32_TIMMODE_COUNTUP, - .lock = CONFIG_STM32H7_TIM17_LOCK, - .t_dts = CONFIG_STM32H7_TIM17_TDTS, + .lock = CONFIG_STM32_TIM17_LOCK, + .t_dts = CONFIG_STM32_TIM17_TDTS, #ifdef HAVE_PWM_COMPLEMENTARY - .deadtime = CONFIG_STM32H7_TIM17_DEADTIME, + .deadtime = CONFIG_STM32_TIM17_DEADTIME, #endif #if defined(HAVE_TRGO) .trgo = 0, /* TRGO not supported for TIM17 */ @@ -1459,7 +1459,7 @@ static struct stm32_pwmtimer_s g_pwm17dev = .base = STM32_TIM17_BASE, .pclk = TIMCLK_TIM17, }; -#endif /* CONFIG_STM32H7_TIM17_PWM */ +#endif /* CONFIG_STM32_TIM17_PWM */ /* TODO: support for TIM19,20,21,22 */ @@ -1796,7 +1796,7 @@ static int pwm_ccr_update(struct pwm_lowerhalf_s *dev, uint8_t index, * Name: pwm_ccr_get ****************************************************************************/ -#ifdef CONFIG_STM32H7_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS static uint32_t pwm_ccr_get(struct pwm_lowerhalf_s *dev, uint8_t index) { struct stm32_pwmtimer_s *priv = (struct stm32_pwmtimer_s *)dev; @@ -1853,7 +1853,7 @@ static uint32_t pwm_ccr_get(struct pwm_lowerhalf_s *dev, uint8_t index) return pwm_getreg(priv, offset); } -#endif /* CONFIG_STM32H7_PWM_LL_OPS */ +#endif /* CONFIG_STM32_PWM_LL_OPS */ /**************************************************************************** * Name: pwm_arr_update @@ -2581,7 +2581,7 @@ static int pwm_outputs_enable(struct pwm_lowerhalf_s *dev, return OK; } -#if defined(HAVE_PWM_COMPLEMENTARY) && defined(CONFIG_STM32H7_PWM_LL_OPS) +#if defined(HAVE_PWM_COMPLEMENTARY) && defined(CONFIG_STM32_PWM_LL_OPS) /**************************************************************************** * Name: pwm_deadtime_update @@ -3134,7 +3134,7 @@ static int pwm_set_apb_clock(struct stm32_pwmtimer_s *priv, bool on) switch (priv->timid) { -#ifdef CONFIG_STM32H7_TIM1_PWM +#ifdef CONFIG_STM32_TIM1_PWM case 1: { regaddr = TIMRCCEN_TIM1; @@ -3143,7 +3143,7 @@ static int pwm_set_apb_clock(struct stm32_pwmtimer_s *priv, bool on) } #endif -#ifdef CONFIG_STM32H7_TIM2_PWM +#ifdef CONFIG_STM32_TIM2_PWM case 2: { regaddr = TIMRCCEN_TIM2; @@ -3152,7 +3152,7 @@ static int pwm_set_apb_clock(struct stm32_pwmtimer_s *priv, bool on) } #endif -#ifdef CONFIG_STM32H7_TIM3_PWM +#ifdef CONFIG_STM32_TIM3_PWM case 3: { regaddr = TIMRCCEN_TIM3; @@ -3161,7 +3161,7 @@ static int pwm_set_apb_clock(struct stm32_pwmtimer_s *priv, bool on) } #endif -#ifdef CONFIG_STM32H7_TIM4_PWM +#ifdef CONFIG_STM32_TIM4_PWM case 4: { regaddr = TIMRCCEN_TIM4; @@ -3170,7 +3170,7 @@ static int pwm_set_apb_clock(struct stm32_pwmtimer_s *priv, bool on) } #endif -#ifdef CONFIG_STM32H7_TIM5_PWM +#ifdef CONFIG_STM32_TIM5_PWM case 5: { regaddr = TIMRCCEN_TIM5; @@ -3179,7 +3179,7 @@ static int pwm_set_apb_clock(struct stm32_pwmtimer_s *priv, bool on) } #endif -#ifdef CONFIG_STM32H7_TIM8_PWM +#ifdef CONFIG_STM32_TIM8_PWM case 8: { regaddr = TIMRCCEN_TIM8; @@ -3188,7 +3188,7 @@ static int pwm_set_apb_clock(struct stm32_pwmtimer_s *priv, bool on) } #endif -#ifdef CONFIG_STM32H7_TIM12_PWM +#ifdef CONFIG_STM32_TIM12_PWM case 12: { regaddr = TIMRCCEN_TIM12; @@ -3197,7 +3197,7 @@ static int pwm_set_apb_clock(struct stm32_pwmtimer_s *priv, bool on) } #endif -#ifdef CONFIG_STM32H7_TIM13_PWM +#ifdef CONFIG_STM32_TIM13_PWM case 13: { regaddr = TIMRCCEN_TIM13; @@ -3206,7 +3206,7 @@ static int pwm_set_apb_clock(struct stm32_pwmtimer_s *priv, bool on) } #endif -#ifdef CONFIG_STM32H7_TIM14_PWM +#ifdef CONFIG_STM32_TIM14_PWM case 14: { regaddr = TIMRCCEN_TIM14; @@ -3215,7 +3215,7 @@ static int pwm_set_apb_clock(struct stm32_pwmtimer_s *priv, bool on) } #endif -#ifdef CONFIG_STM32H7_TIM15_PWM +#ifdef CONFIG_STM32_TIM15_PWM case 15: { regaddr = TIMRCCEN_TIM15; @@ -3224,7 +3224,7 @@ static int pwm_set_apb_clock(struct stm32_pwmtimer_s *priv, bool on) } #endif -#ifdef CONFIG_STM32H7_TIM16_PWM +#ifdef CONFIG_STM32_TIM16_PWM case 16: { regaddr = TIMRCCEN_TIM16; @@ -3233,7 +3233,7 @@ static int pwm_set_apb_clock(struct stm32_pwmtimer_s *priv, bool on) } #endif -#ifdef CONFIG_STM32H7_TIM17_PWM +#ifdef CONFIG_STM32_TIM17_PWM case 17: { regaddr = TIMRCCEN_TIM17; @@ -3531,7 +3531,7 @@ static int pwm_stop(struct pwm_lowerhalf_s *dev) switch (priv->timid) { -#ifdef CONFIG_STM32H7_TIM1_PWM +#ifdef CONFIG_STM32_TIM1_PWM case 1: { regaddr = TIMRCCRST_TIM1; @@ -3540,7 +3540,7 @@ static int pwm_stop(struct pwm_lowerhalf_s *dev) } #endif -#ifdef CONFIG_STM32H7_TIM2_PWM +#ifdef CONFIG_STM32_TIM2_PWM case 2: { regaddr = TIMRCCRST_TIM2; @@ -3549,7 +3549,7 @@ static int pwm_stop(struct pwm_lowerhalf_s *dev) } #endif -#ifdef CONFIG_STM32H7_TIM3_PWM +#ifdef CONFIG_STM32_TIM3_PWM case 3: { regaddr = TIMRCCRST_TIM3; @@ -3558,7 +3558,7 @@ static int pwm_stop(struct pwm_lowerhalf_s *dev) } #endif -#ifdef CONFIG_STM32H7_TIM4_PWM +#ifdef CONFIG_STM32_TIM4_PWM case 4: { regaddr = TIMRCCRST_TIM4; @@ -3567,7 +3567,7 @@ static int pwm_stop(struct pwm_lowerhalf_s *dev) } #endif -#ifdef CONFIG_STM32H7_TIM5_PWM +#ifdef CONFIG_STM32_TIM5_PWM case 5: { regaddr = TIMRCCRST_TIM5; @@ -3576,7 +3576,7 @@ static int pwm_stop(struct pwm_lowerhalf_s *dev) } #endif -#ifdef CONFIG_STM32H7_TIM8_PWM +#ifdef CONFIG_STM32_TIM8_PWM case 8: { regaddr = TIMRCCRST_TIM8; @@ -3585,7 +3585,7 @@ static int pwm_stop(struct pwm_lowerhalf_s *dev) } #endif -#ifdef CONFIG_STM32H7_TIM12_PWM +#ifdef CONFIG_STM32_TIM12_PWM case 12: { regaddr = TIMRCCRST_TIM12; @@ -3594,7 +3594,7 @@ static int pwm_stop(struct pwm_lowerhalf_s *dev) } #endif -#ifdef CONFIG_STM32H7_TIM13_PWM +#ifdef CONFIG_STM32_TIM13_PWM case 13: { regaddr = TIMRCCRST_TIM13; @@ -3603,7 +3603,7 @@ static int pwm_stop(struct pwm_lowerhalf_s *dev) } #endif -#ifdef CONFIG_STM32H7_TIM14_PWM +#ifdef CONFIG_STM32_TIM14_PWM case 14: { regaddr = TIMRCCRST_TIM14; @@ -3612,7 +3612,7 @@ static int pwm_stop(struct pwm_lowerhalf_s *dev) } #endif -#ifdef CONFIG_STM32H7_TIM15_PWM +#ifdef CONFIG_STM32_TIM15_PWM case 15: { regaddr = TIMRCCRST_TIM15; @@ -3621,7 +3621,7 @@ static int pwm_stop(struct pwm_lowerhalf_s *dev) } #endif -#ifdef CONFIG_STM32H7_TIM16_PWM +#ifdef CONFIG_STM32_TIM16_PWM case 16: { regaddr = TIMRCCRST_TIM16; @@ -3630,7 +3630,7 @@ static int pwm_stop(struct pwm_lowerhalf_s *dev) } #endif -#ifdef CONFIG_STM32H7_TIM17_PWM +#ifdef CONFIG_STM32_TIM17_PWM case 17: { regaddr = TIMRCCRST_TIM17; @@ -3747,7 +3747,7 @@ struct pwm_lowerhalf_s *stm32_pwminitialize(int timer) switch (timer) { -#ifdef CONFIG_STM32H7_TIM1_PWM +#ifdef CONFIG_STM32_TIM1_PWM case 1: { lower = &g_pwm1dev; @@ -3758,7 +3758,7 @@ struct pwm_lowerhalf_s *stm32_pwminitialize(int timer) } #endif -#ifdef CONFIG_STM32H7_TIM2_PWM +#ifdef CONFIG_STM32_TIM2_PWM case 2: { lower = &g_pwm2dev; @@ -3766,7 +3766,7 @@ struct pwm_lowerhalf_s *stm32_pwminitialize(int timer) } #endif -#ifdef CONFIG_STM32H7_TIM3_PWM +#ifdef CONFIG_STM32_TIM3_PWM case 3: { lower = &g_pwm3dev; @@ -3774,7 +3774,7 @@ struct pwm_lowerhalf_s *stm32_pwminitialize(int timer) } #endif -#ifdef CONFIG_STM32H7_TIM4_PWM +#ifdef CONFIG_STM32_TIM4_PWM case 4: { lower = &g_pwm4dev; @@ -3782,7 +3782,7 @@ struct pwm_lowerhalf_s *stm32_pwminitialize(int timer) } #endif -#ifdef CONFIG_STM32H7_TIM5_PWM +#ifdef CONFIG_STM32_TIM5_PWM case 5: { lower = &g_pwm5dev; @@ -3790,7 +3790,7 @@ struct pwm_lowerhalf_s *stm32_pwminitialize(int timer) } #endif -#ifdef CONFIG_STM32H7_TIM8_PWM +#ifdef CONFIG_STM32_TIM8_PWM case 8: { lower = &g_pwm8dev; @@ -3801,7 +3801,7 @@ struct pwm_lowerhalf_s *stm32_pwminitialize(int timer) } #endif -#ifdef CONFIG_STM32H7_TIM12_PWM +#ifdef CONFIG_STM32_TIM12_PWM case 12: { lower = &g_pwm12dev; @@ -3809,7 +3809,7 @@ struct pwm_lowerhalf_s *stm32_pwminitialize(int timer) } #endif -#ifdef CONFIG_STM32H7_TIM13_PWM +#ifdef CONFIG_STM32_TIM13_PWM case 13: { lower = &g_pwm13dev; @@ -3817,7 +3817,7 @@ struct pwm_lowerhalf_s *stm32_pwminitialize(int timer) } #endif -#ifdef CONFIG_STM32H7_TIM14_PWM +#ifdef CONFIG_STM32_TIM14_PWM case 14: { lower = &g_pwm14dev; @@ -3825,7 +3825,7 @@ struct pwm_lowerhalf_s *stm32_pwminitialize(int timer) } #endif -#ifdef CONFIG_STM32H7_TIM15_PWM +#ifdef CONFIG_STM32_TIM15_PWM case 15: { lower = &g_pwm15dev; @@ -3833,7 +3833,7 @@ struct pwm_lowerhalf_s *stm32_pwminitialize(int timer) } #endif -#ifdef CONFIG_STM32H7_TIM16_PWM +#ifdef CONFIG_STM32_TIM16_PWM case 16: { lower = &g_pwm16dev; @@ -3841,7 +3841,7 @@ struct pwm_lowerhalf_s *stm32_pwminitialize(int timer) } #endif -#ifdef CONFIG_STM32H7_TIM17_PWM +#ifdef CONFIG_STM32_TIM17_PWM case 17: { lower = &g_pwm17dev; @@ -3861,4 +3861,4 @@ struct pwm_lowerhalf_s *stm32_pwminitialize(int timer) return (struct pwm_lowerhalf_s *)lower; } -#endif /* CONFIG_STM32H7_PWM */ +#endif /* CONFIG_STM32_PWM */ diff --git a/arch/arm/src/stm32h7/stm32_pwm.h b/arch/arm/src/stm32h7/stm32_pwm.h index bc6002af3bf19..de9b791109a56 100644 --- a/arch/arm/src/stm32h7/stm32_pwm.h +++ b/arch/arm/src/stm32h7/stm32_pwm.h @@ -39,7 +39,7 @@ #include "chip.h" -#ifdef CONFIG_STM32H7_PWM +#ifdef CONFIG_STM32_PWM # include # include "hardware/stm32_tim.h" #endif @@ -52,89 +52,89 @@ /* Timer devices may be used for different purposes. One special purpose is * to generate modulated outputs for such things as motor control. - * If CONFIG_STM32H7_TIMn is defined then the CONFIG_STM32H7_TIMn_PWM must + * If CONFIG_STM32_TIMn is defined then the CONFIG_STM32_TIMn_PWM must * also be defined to indicate that timer "n" is intended to be used for * pulsed output signal generation. */ -#ifndef CONFIG_STM32H7_TIM1 -# undef CONFIG_STM32H7_TIM1_PWM +#ifndef CONFIG_STM32_TIM1 +# undef CONFIG_STM32_TIM1_PWM #endif -#ifndef CONFIG_STM32H7_TIM2 -# undef CONFIG_STM32H7_TIM2_PWM +#ifndef CONFIG_STM32_TIM2 +# undef CONFIG_STM32_TIM2_PWM #endif -#ifndef CONFIG_STM32H7_TIM3 -# undef CONFIG_STM32H7_TIM3_PWM +#ifndef CONFIG_STM32_TIM3 +# undef CONFIG_STM32_TIM3_PWM #endif -#ifndef CONFIG_STM32H7_TIM4 -# undef CONFIG_STM32H7_TIM4_PWM +#ifndef CONFIG_STM32_TIM4 +# undef CONFIG_STM32_TIM4_PWM #endif -#ifndef CONFIG_STM32H7_TIM5 -# undef CONFIG_STM32H7_TIM5_PWM +#ifndef CONFIG_STM32_TIM5 +# undef CONFIG_STM32_TIM5_PWM #endif -#ifndef CONFIG_STM32H7_TIM8 -# undef CONFIG_STM32H7_TIM8_PWM +#ifndef CONFIG_STM32_TIM8 +# undef CONFIG_STM32_TIM8_PWM #endif -#ifndef CONFIG_STM32H7_TIM12 -# undef CONFIG_STM32H7_TIM12_PWM +#ifndef CONFIG_STM32_TIM12 +# undef CONFIG_STM32_TIM12_PWM #endif -#ifndef CONFIG_STM32H7_TIM13 -# undef CONFIG_STM32H7_TIM13_PWM +#ifndef CONFIG_STM32_TIM13 +# undef CONFIG_STM32_TIM13_PWM #endif -#ifndef CONFIG_STM32H7_TIM14 -# undef CONFIG_STM32H7_TIM14_PWM +#ifndef CONFIG_STM32_TIM14 +# undef CONFIG_STM32_TIM14_PWM #endif -#ifndef CONFIG_STM32H7_TIM15 -# undef CONFIG_STM32H7_TIM15_PWM +#ifndef CONFIG_STM32_TIM15 +# undef CONFIG_STM32_TIM15_PWM #endif -#ifndef CONFIG_STM32H7_TIM16 -# undef CONFIG_STM32H7_TIM16_PWM +#ifndef CONFIG_STM32_TIM16 +# undef CONFIG_STM32_TIM16_PWM #endif -#ifndef CONFIG_STM32H7_TIM17 -# undef CONFIG_STM32H7_TIM17_PWM +#ifndef CONFIG_STM32_TIM17 +# undef CONFIG_STM32_TIM17_PWM #endif /* The basic timers (timer 6 and 7) are not capable of generating output * pulses */ -#undef CONFIG_STM32H7_TIM6_PWM -#undef CONFIG_STM32H7_TIM7_PWM +#undef CONFIG_STM32_TIM6_PWM +#undef CONFIG_STM32_TIM7_PWM /* Check if PWM support for any channel is enabled. */ -#ifdef CONFIG_STM32H7_PWM +#ifdef CONFIG_STM32_PWM /* PWM driver channels configuration */ -#ifdef CONFIG_STM32H7_PWM_MULTICHAN +#ifdef CONFIG_STM32_PWM_MULTICHAN -#ifdef CONFIG_STM32H7_TIM1_CHANNEL1 +#ifdef CONFIG_STM32_TIM1_CHANNEL1 # define PWM_TIM1_CHANNEL1 1 #else # define PWM_TIM1_CHANNEL1 0 #endif -#ifdef CONFIG_STM32H7_TIM1_CHANNEL2 +#ifdef CONFIG_STM32_TIM1_CHANNEL2 # define PWM_TIM1_CHANNEL2 1 #else # define PWM_TIM1_CHANNEL2 0 #endif -#ifdef CONFIG_STM32H7_TIM1_CHANNEL3 +#ifdef CONFIG_STM32_TIM1_CHANNEL3 # define PWM_TIM1_CHANNEL3 1 #else # define PWM_TIM1_CHANNEL3 0 #endif -#ifdef CONFIG_STM32H7_TIM1_CHANNEL4 +#ifdef CONFIG_STM32_TIM1_CHANNEL4 # define PWM_TIM1_CHANNEL4 1 #else # define PWM_TIM1_CHANNEL4 0 #endif -#ifdef CONFIG_STM32H7_TIM1_CHANNEL5 +#ifdef CONFIG_STM32_TIM1_CHANNEL5 # define PWM_TIM1_CHANNEL5 1 #else # define PWM_TIM1_CHANNEL5 0 #endif -#ifdef CONFIG_STM32H7_TIM1_CHANNEL6 +#ifdef CONFIG_STM32_TIM1_CHANNEL6 # define PWM_TIM1_CHANNEL6 1 #else # define PWM_TIM1_CHANNEL6 0 @@ -143,22 +143,22 @@ PWM_TIM1_CHANNEL3 + PWM_TIM1_CHANNEL4 + \ PWM_TIM1_CHANNEL5 + PWM_TIM1_CHANNEL6) -#ifdef CONFIG_STM32H7_TIM2_CHANNEL1 +#ifdef CONFIG_STM32_TIM2_CHANNEL1 # define PWM_TIM2_CHANNEL1 1 #else # define PWM_TIM2_CHANNEL1 0 #endif -#ifdef CONFIG_STM32H7_TIM2_CHANNEL2 +#ifdef CONFIG_STM32_TIM2_CHANNEL2 # define PWM_TIM2_CHANNEL2 1 #else # define PWM_TIM2_CHANNEL2 0 #endif -#ifdef CONFIG_STM32H7_TIM2_CHANNEL3 +#ifdef CONFIG_STM32_TIM2_CHANNEL3 # define PWM_TIM2_CHANNEL3 1 #else # define PWM_TIM2_CHANNEL3 0 #endif -#ifdef CONFIG_STM32H7_TIM2_CHANNEL4 +#ifdef CONFIG_STM32_TIM2_CHANNEL4 # define PWM_TIM2_CHANNEL4 1 #else # define PWM_TIM2_CHANNEL4 0 @@ -166,22 +166,22 @@ #define PWM_TIM2_NCHANNELS (PWM_TIM2_CHANNEL1 + PWM_TIM2_CHANNEL2 + \ PWM_TIM2_CHANNEL3 + PWM_TIM2_CHANNEL4) -#ifdef CONFIG_STM32H7_TIM3_CHANNEL1 +#ifdef CONFIG_STM32_TIM3_CHANNEL1 # define PWM_TIM3_CHANNEL1 1 #else # define PWM_TIM3_CHANNEL1 0 #endif -#ifdef CONFIG_STM32H7_TIM3_CHANNEL2 +#ifdef CONFIG_STM32_TIM3_CHANNEL2 # define PWM_TIM3_CHANNEL2 1 #else # define PWM_TIM3_CHANNEL2 0 #endif -#ifdef CONFIG_STM32H7_TIM3_CHANNEL3 +#ifdef CONFIG_STM32_TIM3_CHANNEL3 # define PWM_TIM3_CHANNEL3 1 #else # define PWM_TIM3_CHANNEL3 0 #endif -#ifdef CONFIG_STM32H7_TIM3_CHANNEL4 +#ifdef CONFIG_STM32_TIM3_CHANNEL4 # define PWM_TIM3_CHANNEL4 1 #else # define PWM_TIM3_CHANNEL4 0 @@ -189,22 +189,22 @@ #define PWM_TIM3_NCHANNELS (PWM_TIM3_CHANNEL1 + PWM_TIM3_CHANNEL2 + \ PWM_TIM3_CHANNEL3 + PWM_TIM3_CHANNEL4) -#ifdef CONFIG_STM32H7_TIM4_CHANNEL1 +#ifdef CONFIG_STM32_TIM4_CHANNEL1 # define PWM_TIM4_CHANNEL1 1 #else # define PWM_TIM4_CHANNEL1 0 #endif -#ifdef CONFIG_STM32H7_TIM4_CHANNEL2 +#ifdef CONFIG_STM32_TIM4_CHANNEL2 # define PWM_TIM4_CHANNEL2 1 #else # define PWM_TIM4_CHANNEL2 0 #endif -#ifdef CONFIG_STM32H7_TIM4_CHANNEL3 +#ifdef CONFIG_STM32_TIM4_CHANNEL3 # define PWM_TIM4_CHANNEL3 1 #else # define PWM_TIM4_CHANNEL3 0 #endif -#ifdef CONFIG_STM32H7_TIM4_CHANNEL4 +#ifdef CONFIG_STM32_TIM4_CHANNEL4 # define PWM_TIM4_CHANNEL4 1 #else # define PWM_TIM4_CHANNEL4 0 @@ -212,22 +212,22 @@ #define PWM_TIM4_NCHANNELS (PWM_TIM4_CHANNEL1 + PWM_TIM4_CHANNEL2 + \ PWM_TIM4_CHANNEL3 + PWM_TIM4_CHANNEL4) -#ifdef CONFIG_STM32H7_TIM5_CHANNEL1 +#ifdef CONFIG_STM32_TIM5_CHANNEL1 # define PWM_TIM5_CHANNEL1 1 #else # define PWM_TIM5_CHANNEL1 0 #endif -#ifdef CONFIG_STM32H7_TIM5_CHANNEL2 +#ifdef CONFIG_STM32_TIM5_CHANNEL2 # define PWM_TIM5_CHANNEL2 1 #else # define PWM_TIM5_CHANNEL2 0 #endif -#ifdef CONFIG_STM32H7_TIM5_CHANNEL3 +#ifdef CONFIG_STM32_TIM5_CHANNEL3 # define PWM_TIM5_CHANNEL3 1 #else # define PWM_TIM5_CHANNEL3 0 #endif -#ifdef CONFIG_STM32H7_TIM5_CHANNEL4 +#ifdef CONFIG_STM32_TIM5_CHANNEL4 # define PWM_TIM5_CHANNEL4 1 #else # define PWM_TIM5_CHANNEL4 0 @@ -235,32 +235,32 @@ #define PWM_TIM5_NCHANNELS (PWM_TIM5_CHANNEL1 + PWM_TIM5_CHANNEL2 + \ PWM_TIM5_CHANNEL3 + PWM_TIM5_CHANNEL4) -#ifdef CONFIG_STM32H7_TIM8_CHANNEL1 +#ifdef CONFIG_STM32_TIM8_CHANNEL1 # define PWM_TIM8_CHANNEL1 1 #else # define PWM_TIM8_CHANNEL1 0 #endif -#ifdef CONFIG_STM32H7_TIM8_CHANNEL2 +#ifdef CONFIG_STM32_TIM8_CHANNEL2 # define PWM_TIM8_CHANNEL2 1 #else # define PWM_TIM8_CHANNEL2 0 #endif -#ifdef CONFIG_STM32H7_TIM8_CHANNEL3 +#ifdef CONFIG_STM32_TIM8_CHANNEL3 # define PWM_TIM8_CHANNEL3 1 #else # define PWM_TIM8_CHANNEL3 0 #endif -#ifdef CONFIG_STM32H7_TIM8_CHANNEL4 +#ifdef CONFIG_STM32_TIM8_CHANNEL4 # define PWM_TIM8_CHANNEL4 1 #else # define PWM_TIM8_CHANNEL4 0 #endif -#ifdef CONFIG_STM32H7_TIM8_CHANNEL5 +#ifdef CONFIG_STM32_TIM8_CHANNEL5 # define PWM_TIM8_CHANNEL5 1 #else # define PWM_TIM8_CHANNEL5 0 #endif -#ifdef CONFIG_STM32H7_TIM8_CHANNEL6 +#ifdef CONFIG_STM32_TIM8_CHANNEL6 # define PWM_TIM8_CHANNEL6 1 #else # define PWM_TIM8_CHANNEL6 0 @@ -269,64 +269,64 @@ PWM_TIM8_CHANNEL3 + PWM_TIM8_CHANNEL4 + \ PWM_TIM8_CHANNEL5 + PWM_TIM8_CHANNEL6) -#ifdef CONFIG_STM32H7_TIM12_CHANNEL1 +#ifdef CONFIG_STM32_TIM12_CHANNEL1 # define PWM_TIM12_CHANNEL1 1 #else # define PWM_TIM12_CHANNEL1 0 #endif -#ifdef CONFIG_STM32H7_TIM12_CHANNEL2 +#ifdef CONFIG_STM32_TIM12_CHANNEL2 # define PWM_TIM12_CHANNEL2 1 #else # define PWM_TIM12_CHANNEL2 0 #endif #define PWM_TIM12_NCHANNELS (PWM_TIM12_CHANNEL1 + PWM_TIM12_CHANNEL2) -#ifdef CONFIG_STM32H7_TIM13_CHANNEL1 +#ifdef CONFIG_STM32_TIM13_CHANNEL1 # define PWM_TIM13_CHANNEL1 1 #else # define PWM_TIM13_CHANNEL1 0 #endif #define PWM_TIM13_NCHANNELS (PWM_TIM13_CHANNEL1) -#ifdef CONFIG_STM32H7_TIM14_CHANNEL1 +#ifdef CONFIG_STM32_TIM14_CHANNEL1 # define PWM_TIM14_CHANNEL1 1 #else # define PWM_TIM14_CHANNEL1 0 #endif #define PWM_TIM14_NCHANNELS (PWM_TIM14_CHANNEL1) -#ifdef CONFIG_STM32H7_TIM15_CHANNEL1 +#ifdef CONFIG_STM32_TIM15_CHANNEL1 # define PWM_TIM15_CHANNEL1 1 #else # define PWM_TIM15_CHANNEL1 0 #endif -#ifdef CONFIG_STM32H7_TIM15_CHANNEL2 +#ifdef CONFIG_STM32_TIM15_CHANNEL2 # define PWM_TIM15_CHANNEL2 1 #else # define PWM_TIM15_CHANNEL2 0 #endif #define PWM_TIM15_NCHANNELS (PWM_TIM15_CHANNEL1 + PWM_TIM15_CHANNEL2) -#ifdef CONFIG_STM32H7_TIM16_CHANNEL1 +#ifdef CONFIG_STM32_TIM16_CHANNEL1 # define PWM_TIM16_CHANNEL1 1 #else # define PWM_TIM16_CHANNEL1 0 #endif #define PWM_TIM16_NCHANNELS PWM_TIM16_CHANNEL1 -#ifdef CONFIG_STM32H7_TIM17_CHANNEL1 +#ifdef CONFIG_STM32_TIM17_CHANNEL1 # define PWM_TIM17_CHANNEL1 1 #else # define PWM_TIM17_CHANNEL1 0 #endif #define PWM_TIM17_NCHANNELS PWM_TIM17_CHANNEL1 -#else /* !CONFIG_STM32H7_PWM_MULTICHAN */ +#else /* !CONFIG_STM32_PWM_MULTICHAN */ /* For each timer that is enabled for PWM usage, we need the following * additional configuration settings: * - * CONFIG_STM32H7_TIMx_CHANNEL - Specifies the timer output channel + * CONFIG_STM32_TIMx_CHANNEL - Specifies the timer output channel * {1,..,4} * PWM_TIMx_CHn - One of the values defined in chip/stm32*_pinmap.h. * In the case where there are multiple pin selections, the correct @@ -338,425 +338,425 @@ * is not supported by this driver: Only one output channel per timer. */ -#ifdef CONFIG_STM32H7_TIM1_PWM -# if !defined(CONFIG_STM32H7_TIM1_CHANNEL) -# error "CONFIG_STM32H7_TIM1_CHANNEL must be provided" -# elif CONFIG_STM32H7_TIM1_CHANNEL == 1 -# define CONFIG_STM32H7_TIM1_CHANNEL1 1 -# define CONFIG_STM32H7_TIM1_CH1MODE CONFIG_STM32H7_TIM1_CHMODE -# elif CONFIG_STM32H7_TIM1_CHANNEL == 2 -# define CONFIG_STM32H7_TIM1_CHANNEL2 1 -# define CONFIG_STM32H7_TIM1_CH2MODE CONFIG_STM32H7_TIM1_CHMODE -# elif CONFIG_STM32H7_TIM1_CHANNEL == 3 -# define CONFIG_STM32H7_TIM1_CHANNEL3 1 -# define CONFIG_STM32H7_TIM1_CH3MODE CONFIG_STM32H7_TIM1_CHMODE -# elif CONFIG_STM32H7_TIM1_CHANNEL == 4 -# define CONFIG_STM32H7_TIM1_CHANNEL4 1 -# define CONFIG_STM32H7_TIM1_CH4MODE CONFIG_STM32H7_TIM1_CHMODE +#ifdef CONFIG_STM32_TIM1_PWM +# if !defined(CONFIG_STM32_TIM1_CHANNEL) +# error "CONFIG_STM32_TIM1_CHANNEL must be provided" +# elif CONFIG_STM32_TIM1_CHANNEL == 1 +# define CONFIG_STM32_TIM1_CHANNEL1 1 +# define CONFIG_STM32_TIM1_CH1MODE CONFIG_STM32_TIM1_CHMODE +# elif CONFIG_STM32_TIM1_CHANNEL == 2 +# define CONFIG_STM32_TIM1_CHANNEL2 1 +# define CONFIG_STM32_TIM1_CH2MODE CONFIG_STM32_TIM1_CHMODE +# elif CONFIG_STM32_TIM1_CHANNEL == 3 +# define CONFIG_STM32_TIM1_CHANNEL3 1 +# define CONFIG_STM32_TIM1_CH3MODE CONFIG_STM32_TIM1_CHMODE +# elif CONFIG_STM32_TIM1_CHANNEL == 4 +# define CONFIG_STM32_TIM1_CHANNEL4 1 +# define CONFIG_STM32_TIM1_CH4MODE CONFIG_STM32_TIM1_CHMODE # else -# error "Unsupported value of CONFIG_STM32H7_TIM1_CHANNEL" +# error "Unsupported value of CONFIG_STM32_TIM1_CHANNEL" # endif # define PWM_TIM1_NCHANNELS 1 #endif -#ifdef CONFIG_STM32H7_TIM2_PWM -# if !defined(CONFIG_STM32H7_TIM2_CHANNEL) -# error "CONFIG_STM32H7_TIM2_CHANNEL must be provided" -# elif CONFIG_STM32H7_TIM2_CHANNEL == 1 -# define CONFIG_STM32H7_TIM2_CHANNEL1 1 -# define CONFIG_STM32H7_TIM2_CH1MODE CONFIG_STM32H7_TIM2_CHMODE -# elif CONFIG_STM32H7_TIM2_CHANNEL == 2 -# define CONFIG_STM32H7_TIM2_CHANNEL2 1 -# define CONFIG_STM32H7_TIM2_CH2MODE CONFIG_STM32H7_TIM2_CHMODE -# elif CONFIG_STM32H7_TIM2_CHANNEL == 3 -# define CONFIG_STM32H7_TIM2_CHANNEL3 1 -# define CONFIG_STM32H7_TIM2_CH3MODE CONFIG_STM32H7_TIM2_CHMODE -# elif CONFIG_STM32H7_TIM2_CHANNEL == 4 -# define CONFIG_STM32H7_TIM2_CHANNEL4 1 -# define CONFIG_STM32H7_TIM2_CH4MODE CONFIG_STM32H7_TIM2_CHMODE +#ifdef CONFIG_STM32_TIM2_PWM +# if !defined(CONFIG_STM32_TIM2_CHANNEL) +# error "CONFIG_STM32_TIM2_CHANNEL must be provided" +# elif CONFIG_STM32_TIM2_CHANNEL == 1 +# define CONFIG_STM32_TIM2_CHANNEL1 1 +# define CONFIG_STM32_TIM2_CH1MODE CONFIG_STM32_TIM2_CHMODE +# elif CONFIG_STM32_TIM2_CHANNEL == 2 +# define CONFIG_STM32_TIM2_CHANNEL2 1 +# define CONFIG_STM32_TIM2_CH2MODE CONFIG_STM32_TIM2_CHMODE +# elif CONFIG_STM32_TIM2_CHANNEL == 3 +# define CONFIG_STM32_TIM2_CHANNEL3 1 +# define CONFIG_STM32_TIM2_CH3MODE CONFIG_STM32_TIM2_CHMODE +# elif CONFIG_STM32_TIM2_CHANNEL == 4 +# define CONFIG_STM32_TIM2_CHANNEL4 1 +# define CONFIG_STM32_TIM2_CH4MODE CONFIG_STM32_TIM2_CHMODE # else -# error "Unsupported value of CONFIG_STM32H7_TIM2_CHANNEL" +# error "Unsupported value of CONFIG_STM32_TIM2_CHANNEL" # endif # define PWM_TIM2_NCHANNELS 1 #endif -#ifdef CONFIG_STM32H7_TIM3_PWM -# if !defined(CONFIG_STM32H7_TIM3_CHANNEL) -# error "CONFIG_STM32H7_TIM3_CHANNEL must be provided" -# elif CONFIG_STM32H7_TIM3_CHANNEL == 1 -# define CONFIG_STM32H7_TIM3_CHANNEL1 1 -# define CONFIG_STM32H7_TIM3_CH1MODE CONFIG_STM32H7_TIM3_CHMODE -# elif CONFIG_STM32H7_TIM3_CHANNEL == 2 -# define CONFIG_STM32H7_TIM3_CHANNEL2 1 -# define CONFIG_STM32H7_TIM3_CH2MODE CONFIG_STM32H7_TIM3_CHMODE -# elif CONFIG_STM32H7_TIM3_CHANNEL == 3 -# define CONFIG_STM32H7_TIM3_CHANNEL3 1 -# define CONFIG_STM32H7_TIM3_CH3MODE CONFIG_STM32H7_TIM3_CHMODE -# elif CONFIG_STM32H7_TIM3_CHANNEL == 4 -# define CONFIG_STM32H7_TIM3_CHANNEL4 1 -# define CONFIG_STM32H7_TIM3_CH4MODE CONFIG_STM32H7_TIM3_CHMODE +#ifdef CONFIG_STM32_TIM3_PWM +# if !defined(CONFIG_STM32_TIM3_CHANNEL) +# error "CONFIG_STM32_TIM3_CHANNEL must be provided" +# elif CONFIG_STM32_TIM3_CHANNEL == 1 +# define CONFIG_STM32_TIM3_CHANNEL1 1 +# define CONFIG_STM32_TIM3_CH1MODE CONFIG_STM32_TIM3_CHMODE +# elif CONFIG_STM32_TIM3_CHANNEL == 2 +# define CONFIG_STM32_TIM3_CHANNEL2 1 +# define CONFIG_STM32_TIM3_CH2MODE CONFIG_STM32_TIM3_CHMODE +# elif CONFIG_STM32_TIM3_CHANNEL == 3 +# define CONFIG_STM32_TIM3_CHANNEL3 1 +# define CONFIG_STM32_TIM3_CH3MODE CONFIG_STM32_TIM3_CHMODE +# elif CONFIG_STM32_TIM3_CHANNEL == 4 +# define CONFIG_STM32_TIM3_CHANNEL4 1 +# define CONFIG_STM32_TIM3_CH4MODE CONFIG_STM32_TIM3_CHMODE # else -# error "Unsupported value of CONFIG_STM32H7_TIM3_CHANNEL" +# error "Unsupported value of CONFIG_STM32_TIM3_CHANNEL" # endif # define PWM_TIM3_NCHANNELS 1 #endif -#ifdef CONFIG_STM32H7_TIM4_PWM -# if !defined(CONFIG_STM32H7_TIM4_CHANNEL) -# error "CONFIG_STM32H7_TIM4_CHANNEL must be provided" -# elif CONFIG_STM32H7_TIM4_CHANNEL == 1 -# define CONFIG_STM32H7_TIM4_CHANNEL1 1 -# define CONFIG_STM32H7_TIM4_CH1MODE CONFIG_STM32H7_TIM4_CHMODE -# elif CONFIG_STM32H7_TIM4_CHANNEL == 2 -# define CONFIG_STM32H7_TIM4_CHANNEL2 1 -# define CONFIG_STM32H7_TIM4_CH2MODE CONFIG_STM32H7_TIM4_CHMODE -# elif CONFIG_STM32H7_TIM4_CHANNEL == 3 -# define CONFIG_STM32H7_TIM4_CHANNEL3 1 -# define CONFIG_STM32H7_TIM4_CH3MODE CONFIG_STM32H7_TIM4_CHMODE -# elif CONFIG_STM32H7_TIM4_CHANNEL == 4 -# define CONFIG_STM32H7_TIM4_CHANNEL4 1 -# define CONFIG_STM32H7_TIM4_CH4MODE CONFIG_STM32H7_TIM4_CHMODE +#ifdef CONFIG_STM32_TIM4_PWM +# if !defined(CONFIG_STM32_TIM4_CHANNEL) +# error "CONFIG_STM32_TIM4_CHANNEL must be provided" +# elif CONFIG_STM32_TIM4_CHANNEL == 1 +# define CONFIG_STM32_TIM4_CHANNEL1 1 +# define CONFIG_STM32_TIM4_CH1MODE CONFIG_STM32_TIM4_CHMODE +# elif CONFIG_STM32_TIM4_CHANNEL == 2 +# define CONFIG_STM32_TIM4_CHANNEL2 1 +# define CONFIG_STM32_TIM4_CH2MODE CONFIG_STM32_TIM4_CHMODE +# elif CONFIG_STM32_TIM4_CHANNEL == 3 +# define CONFIG_STM32_TIM4_CHANNEL3 1 +# define CONFIG_STM32_TIM4_CH3MODE CONFIG_STM32_TIM4_CHMODE +# elif CONFIG_STM32_TIM4_CHANNEL == 4 +# define CONFIG_STM32_TIM4_CHANNEL4 1 +# define CONFIG_STM32_TIM4_CH4MODE CONFIG_STM32_TIM4_CHMODE # else -# error "Unsupported value of CONFIG_STM32H7_TIM4_CHANNEL" +# error "Unsupported value of CONFIG_STM32_TIM4_CHANNEL" # endif # define PWM_TIM4_NCHANNELS 1 #endif -#ifdef CONFIG_STM32H7_TIM5_PWM -# if !defined(CONFIG_STM32H7_TIM5_CHANNEL) -# error "CONFIG_STM32H7_TIM5_CHANNEL must be provided" -# elif CONFIG_STM32H7_TIM5_CHANNEL == 1 -# define CONFIG_STM32H7_TIM5_CHANNEL1 1 -# define CONFIG_STM32H7_TIM5_CH1MODE CONFIG_STM32H7_TIM5_CHMODE -# elif CONFIG_STM32H7_TIM5_CHANNEL == 2 -# define CONFIG_STM32H7_TIM5_CHANNEL2 1 -# define CONFIG_STM32H7_TIM5_CH2MODE CONFIG_STM32H7_TIM5_CHMODE -# elif CONFIG_STM32H7_TIM5_CHANNEL == 3 -# define CONFIG_STM32H7_TIM5_CHANNEL3 1 -# define CONFIG_STM32H7_TIM5_CH3MODE CONFIG_STM32H7_TIM5_CHMODE -# elif CONFIG_STM32H7_TIM5_CHANNEL == 4 -# define CONFIG_STM32H7_TIM5_CHANNEL4 1 -# define CONFIG_STM32H7_TIM5_CH4MODE CONFIG_STM32H7_TIM5_CHMODE +#ifdef CONFIG_STM32_TIM5_PWM +# if !defined(CONFIG_STM32_TIM5_CHANNEL) +# error "CONFIG_STM32_TIM5_CHANNEL must be provided" +# elif CONFIG_STM32_TIM5_CHANNEL == 1 +# define CONFIG_STM32_TIM5_CHANNEL1 1 +# define CONFIG_STM32_TIM5_CH1MODE CONFIG_STM32_TIM5_CHMODE +# elif CONFIG_STM32_TIM5_CHANNEL == 2 +# define CONFIG_STM32_TIM5_CHANNEL2 1 +# define CONFIG_STM32_TIM5_CH2MODE CONFIG_STM32_TIM5_CHMODE +# elif CONFIG_STM32_TIM5_CHANNEL == 3 +# define CONFIG_STM32_TIM5_CHANNEL3 1 +# define CONFIG_STM32_TIM5_CH3MODE CONFIG_STM32_TIM5_CHMODE +# elif CONFIG_STM32_TIM5_CHANNEL == 4 +# define CONFIG_STM32_TIM5_CHANNEL4 1 +# define CONFIG_STM32_TIM5_CH4MODE CONFIG_STM32_TIM5_CHMODE # else -# error "Unsupported value of CONFIG_STM32H7_TIM5_CHANNEL" +# error "Unsupported value of CONFIG_STM32_TIM5_CHANNEL" # endif # define PWM_TIM5_NCHANNELS 1 #endif -#ifdef CONFIG_STM32H7_TIM8_PWM -# if !defined(CONFIG_STM32H7_TIM8_CHANNEL) -# error "CONFIG_STM32H7_TIM8_CHANNEL must be provided" -# elif CONFIG_STM32H7_TIM8_CHANNEL == 1 -# define CONFIG_STM32H7_TIM8_CHANNEL1 1 -# define CONFIG_STM32H7_TIM8_CH1MODE CONFIG_STM32H7_TIM8_CHMODE -# elif CONFIG_STM32H7_TIM8_CHANNEL == 2 -# define CONFIG_STM32H7_TIM8_CHANNEL2 1 -# define CONFIG_STM32H7_TIM8_CH2MODE CONFIG_STM32H7_TIM8_CHMODE -# elif CONFIG_STM32H7_TIM8_CHANNEL == 3 -# define CONFIG_STM32H7_TIM8_CHANNEL3 1 -# define CONFIG_STM32H7_TIM8_CH3MODE CONFIG_STM32H7_TIM8_CHMODE -# elif CONFIG_STM32H7_TIM8_CHANNEL == 4 -# define CONFIG_STM32H7_TIM8_CHANNEL4 1 -# define CONFIG_STM32H7_TIM8_CH4MODE CONFIG_STM32H7_TIM8_CHMODE +#ifdef CONFIG_STM32_TIM8_PWM +# if !defined(CONFIG_STM32_TIM8_CHANNEL) +# error "CONFIG_STM32_TIM8_CHANNEL must be provided" +# elif CONFIG_STM32_TIM8_CHANNEL == 1 +# define CONFIG_STM32_TIM8_CHANNEL1 1 +# define CONFIG_STM32_TIM8_CH1MODE CONFIG_STM32_TIM8_CHMODE +# elif CONFIG_STM32_TIM8_CHANNEL == 2 +# define CONFIG_STM32_TIM8_CHANNEL2 1 +# define CONFIG_STM32_TIM8_CH2MODE CONFIG_STM32_TIM8_CHMODE +# elif CONFIG_STM32_TIM8_CHANNEL == 3 +# define CONFIG_STM32_TIM8_CHANNEL3 1 +# define CONFIG_STM32_TIM8_CH3MODE CONFIG_STM32_TIM8_CHMODE +# elif CONFIG_STM32_TIM8_CHANNEL == 4 +# define CONFIG_STM32_TIM8_CHANNEL4 1 +# define CONFIG_STM32_TIM8_CH4MODE CONFIG_STM32_TIM8_CHMODE # else -# error "Unsupported value of CONFIG_STM32H7_TIM8_CHANNEL" +# error "Unsupported value of CONFIG_STM32_TIM8_CHANNEL" # endif # define PWM_TIM8_NCHANNELS 1 #endif -#ifdef CONFIG_STM32H7_TIM12_PWM -# if !defined(CONFIG_STM32H7_TIM12_CHANNEL) -# error "CONFIG_STM32H7_TIM12_CHANNEL must be provided" -# elif CONFIG_STM32H7_TIM12_CHANNEL == 1 -# define CONFIG_STM32H7_TIM12_CHANNEL1 1 -# define CONFIG_STM32H7_TIM12_CH1MODE CONFIG_STM32H7_TIM12_CHMODE -# elif CONFIG_STM32H7_TIM12_CHANNEL == 2 -# define CONFIG_STM32H7_TIM12_CHANNEL2 1 -# define CONFIG_STM32H7_TIM12_CH2MODE CONFIG_STM32H7_TIM12_CHMODE +#ifdef CONFIG_STM32_TIM12_PWM +# if !defined(CONFIG_STM32_TIM12_CHANNEL) +# error "CONFIG_STM32_TIM12_CHANNEL must be provided" +# elif CONFIG_STM32_TIM12_CHANNEL == 1 +# define CONFIG_STM32_TIM12_CHANNEL1 1 +# define CONFIG_STM32_TIM12_CH1MODE CONFIG_STM32_TIM12_CHMODE +# elif CONFIG_STM32_TIM12_CHANNEL == 2 +# define CONFIG_STM32_TIM12_CHANNEL2 1 +# define CONFIG_STM32_TIM12_CH2MODE CONFIG_STM32_TIM12_CHMODE # else -# error "Unsupported value of CONFIG_STM32H7_TIM12_CHANNEL" +# error "Unsupported value of CONFIG_STM32_TIM12_CHANNEL" # endif # define PWM_TIM12_NCHANNELS 1 #endif -#ifdef CONFIG_STM32H7_TIM13_PWM -# if !defined(CONFIG_STM32H7_TIM13_CHANNEL) -# error "CONFIG_STM32H7_TIM13_CHANNEL must be provided" -# elif CONFIG_STM32H7_TIM13_CHANNEL == 1 -# define CONFIG_STM32H7_TIM13_CHANNEL1 1 -# define CONFIG_STM32H7_TIM13_CH1MODE CONFIG_STM32H7_TIM13_CHMODE +#ifdef CONFIG_STM32_TIM13_PWM +# if !defined(CONFIG_STM32_TIM13_CHANNEL) +# error "CONFIG_STM32_TIM13_CHANNEL must be provided" +# elif CONFIG_STM32_TIM13_CHANNEL == 1 +# define CONFIG_STM32_TIM13_CHANNEL1 1 +# define CONFIG_STM32_TIM13_CH1MODE CONFIG_STM32_TIM13_CHMODE # else -# error "Unsupported value of CONFIG_STM32H7_TIM13_CHANNEL" +# error "Unsupported value of CONFIG_STM32_TIM13_CHANNEL" # endif # define PWM_TIM13_NCHANNELS 1 #endif -#ifdef CONFIG_STM32H7_TIM14_PWM -# if !defined(CONFIG_STM32H7_TIM14_CHANNEL) -# error "CONFIG_STM32H7_TIM14_CHANNEL must be provided" -# elif CONFIG_STM32H7_TIM14_CHANNEL == 1 -# define CONFIG_STM32H7_TIM14_CHANNEL1 1 -# define CONFIG_STM32H7_TIM14_CH1MODE CONFIG_STM32H7_TIM14_CHMODE +#ifdef CONFIG_STM32_TIM14_PWM +# if !defined(CONFIG_STM32_TIM14_CHANNEL) +# error "CONFIG_STM32_TIM14_CHANNEL must be provided" +# elif CONFIG_STM32_TIM14_CHANNEL == 1 +# define CONFIG_STM32_TIM14_CHANNEL1 1 +# define CONFIG_STM32_TIM14_CH1MODE CONFIG_STM32_TIM14_CHMODE # else -# error "Unsupported value of CONFIG_STM32H7_TIM14_CHANNEL" +# error "Unsupported value of CONFIG_STM32_TIM14_CHANNEL" # endif # define PWM_TIM14_NCHANNELS 1 #endif -#ifdef CONFIG_STM32H7_TIM15_PWM -# if !defined(CONFIG_STM32H7_TIM15_CHANNEL) -# error "CONFIG_STM32H7_TIM15_CHANNEL must be provided" -# elif CONFIG_STM32H7_TIM15_CHANNEL == 1 -# define CONFIG_STM32H7_TIM15_CHANNEL1 1 -# define CONFIG_STM32H7_TIM15_CH1MODE CONFIG_STM32H7_TIM15_CHMODE -# elif CONFIG_STM32H7_TIM15_CHANNEL == 2 -# define CONFIG_STM32H7_TIM15_CHANNEL2 1 -# define CONFIG_STM32H7_TIM15_CH2MODE CONFIG_STM32H7_TIM15_CHMODE +#ifdef CONFIG_STM32_TIM15_PWM +# if !defined(CONFIG_STM32_TIM15_CHANNEL) +# error "CONFIG_STM32_TIM15_CHANNEL must be provided" +# elif CONFIG_STM32_TIM15_CHANNEL == 1 +# define CONFIG_STM32_TIM15_CHANNEL1 1 +# define CONFIG_STM32_TIM15_CH1MODE CONFIG_STM32_TIM15_CHMODE +# elif CONFIG_STM32_TIM15_CHANNEL == 2 +# define CONFIG_STM32_TIM15_CHANNEL2 1 +# define CONFIG_STM32_TIM15_CH2MODE CONFIG_STM32_TIM15_CHMODE # else -# error "Unsupported value of CONFIG_STM32H7_TIM15_CHANNEL" +# error "Unsupported value of CONFIG_STM32_TIM15_CHANNEL" # endif # define PWM_TIM15_NCHANNELS 1 #endif -#ifdef CONFIG_STM32H7_TIM16_PWM -# if !defined(CONFIG_STM32H7_TIM16_CHANNEL) -# error "CONFIG_STM32H7_TIM16_CHANNEL must be provided" -# elif CONFIG_STM32H7_TIM16_CHANNEL == 1 -# define CONFIG_STM32H7_TIM16_CHANNEL1 1 -# define CONFIG_STM32H7_TIM16_CH1MODE CONFIG_STM32H7_TIM16_CHMODE +#ifdef CONFIG_STM32_TIM16_PWM +# if !defined(CONFIG_STM32_TIM16_CHANNEL) +# error "CONFIG_STM32_TIM16_CHANNEL must be provided" +# elif CONFIG_STM32_TIM16_CHANNEL == 1 +# define CONFIG_STM32_TIM16_CHANNEL1 1 +# define CONFIG_STM32_TIM16_CH1MODE CONFIG_STM32_TIM16_CHMODE # else -# error "Unsupported value of CONFIG_STM32H7_TIM16_CHANNEL" +# error "Unsupported value of CONFIG_STM32_TIM16_CHANNEL" # endif # define PWM_TIM16_NCHANNELS 1 #endif -#ifdef CONFIG_STM32H7_TIM17_PWM -# if !defined(CONFIG_STM32H7_TIM17_CHANNEL) -# error "CONFIG_STM32H7_TIM17_CHANNEL must be provided" -# elif CONFIG_STM32H7_TIM17_CHANNEL == 1 -# define CONFIG_STM32H7_TIM17_CHANNEL1 1 -# define CONFIG_STM32H7_TIM17_CH1MODE CONFIG_STM32H7_TIM17_CHMODE +#ifdef CONFIG_STM32_TIM17_PWM +# if !defined(CONFIG_STM32_TIM17_CHANNEL) +# error "CONFIG_STM32_TIM17_CHANNEL must be provided" +# elif CONFIG_STM32_TIM17_CHANNEL == 1 +# define CONFIG_STM32_TIM17_CHANNEL1 1 +# define CONFIG_STM32_TIM17_CH1MODE CONFIG_STM32_TIM17_CHMODE # else -# error "Unsupported value of CONFIG_STM32H7_TIM17_CHANNEL" +# error "Unsupported value of CONFIG_STM32_TIM17_CHANNEL" # endif # define PWM_TIM17_NCHANNELS 1 #endif -#endif /* CONFIG_STM32H7_PWM_MULTICHAN */ +#endif /* CONFIG_STM32_PWM_MULTICHAN */ -#ifdef CONFIG_STM32H7_TIM1_CH1OUT +#ifdef CONFIG_STM32_TIM1_CH1OUT # define PWM_TIM1_CH1CFG GPIO_TIM1_CH1OUT #else # define PWM_TIM1_CH1CFG 0 #endif -#ifdef CONFIG_STM32H7_TIM1_CH1NOUT +#ifdef CONFIG_STM32_TIM1_CH1NOUT # define PWM_TIM1_CH1NCFG GPIO_TIM1_CH1NOUT #else # define PWM_TIM1_CH1NCFG 0 #endif -#ifdef CONFIG_STM32H7_TIM1_CH2OUT +#ifdef CONFIG_STM32_TIM1_CH2OUT # define PWM_TIM1_CH2CFG GPIO_TIM1_CH2OUT #else # define PWM_TIM1_CH2CFG 0 #endif -#ifdef CONFIG_STM32H7_TIM1_CH2NOUT +#ifdef CONFIG_STM32_TIM1_CH2NOUT # define PWM_TIM1_CH2NCFG GPIO_TIM1_CH2NOUT #else # define PWM_TIM1_CH2NCFG 0 #endif -#ifdef CONFIG_STM32H7_TIM1_CH3OUT +#ifdef CONFIG_STM32_TIM1_CH3OUT # define PWM_TIM1_CH3CFG GPIO_TIM1_CH3OUT #else # define PWM_TIM1_CH3CFG 0 #endif -#ifdef CONFIG_STM32H7_TIM1_CH3NOUT +#ifdef CONFIG_STM32_TIM1_CH3NOUT # define PWM_TIM1_CH3NCFG GPIO_TIM1_CH3NOUT #else # define PWM_TIM1_CH3NCFG 0 #endif -#ifdef CONFIG_STM32H7_TIM1_CH4OUT +#ifdef CONFIG_STM32_TIM1_CH4OUT # define PWM_TIM1_CH4CFG GPIO_TIM1_CH4OUT #else # define PWM_TIM1_CH4CFG 0 #endif -#ifdef CONFIG_STM32H7_TIM2_CH1OUT +#ifdef CONFIG_STM32_TIM2_CH1OUT # define PWM_TIM2_CH1CFG GPIO_TIM2_CH1OUT #else # define PWM_TIM2_CH1CFG 0 #endif -#ifdef CONFIG_STM32H7_TIM2_CH2OUT +#ifdef CONFIG_STM32_TIM2_CH2OUT # define PWM_TIM2_CH2CFG GPIO_TIM2_CH2OUT #else # define PWM_TIM2_CH2CFG 0 #endif -#ifdef CONFIG_STM32H7_TIM2_CH3OUT +#ifdef CONFIG_STM32_TIM2_CH3OUT # define PWM_TIM2_CH3CFG GPIO_TIM2_CH3OUT #else # define PWM_TIM2_CH3CFG 0 #endif -#ifdef CONFIG_STM32H7_TIM2_CH4OUT +#ifdef CONFIG_STM32_TIM2_CH4OUT # define PWM_TIM2_CH4CFG GPIO_TIM2_CH4OUT #else # define PWM_TIM2_CH4CFG 0 #endif -#ifdef CONFIG_STM32H7_TIM3_CH1OUT +#ifdef CONFIG_STM32_TIM3_CH1OUT # define PWM_TIM3_CH1CFG GPIO_TIM3_CH1OUT #else # define PWM_TIM3_CH1CFG 0 #endif -#ifdef CONFIG_STM32H7_TIM3_CH2OUT +#ifdef CONFIG_STM32_TIM3_CH2OUT # define PWM_TIM3_CH2CFG GPIO_TIM3_CH2OUT #else # define PWM_TIM3_CH2CFG 0 #endif -#ifdef CONFIG_STM32H7_TIM3_CH3OUT +#ifdef CONFIG_STM32_TIM3_CH3OUT # define PWM_TIM3_CH3CFG GPIO_TIM3_CH3OUT #else # define PWM_TIM3_CH3CFG 0 #endif -#ifdef CONFIG_STM32H7_TIM3_CH4OUT +#ifdef CONFIG_STM32_TIM3_CH4OUT # define PWM_TIM3_CH4CFG GPIO_TIM3_CH4OUT #else # define PWM_TIM3_CH4CFG 0 #endif -#ifdef CONFIG_STM32H7_TIM4_CH1OUT +#ifdef CONFIG_STM32_TIM4_CH1OUT # define PWM_TIM4_CH1CFG GPIO_TIM4_CH1OUT #else # define PWM_TIM4_CH1CFG 0 #endif -#ifdef CONFIG_STM32H7_TIM4_CH2OUT +#ifdef CONFIG_STM32_TIM4_CH2OUT # define PWM_TIM4_CH2CFG GPIO_TIM4_CH2OUT #else # define PWM_TIM4_CH2CFG 0 #endif -#ifdef CONFIG_STM32H7_TIM4_CH3OUT +#ifdef CONFIG_STM32_TIM4_CH3OUT # define PWM_TIM4_CH3CFG GPIO_TIM4_CH3OUT #else # define PWM_TIM4_CH3CFG 0 #endif -#ifdef CONFIG_STM32H7_TIM4_CH4OUT +#ifdef CONFIG_STM32_TIM4_CH4OUT # define PWM_TIM4_CH4CFG GPIO_TIM4_CH4OUT #else # define PWM_TIM4_CH4CFG 0 #endif -#ifdef CONFIG_STM32H7_TIM5_CH1OUT +#ifdef CONFIG_STM32_TIM5_CH1OUT # define PWM_TIM5_CH1CFG GPIO_TIM5_CH1OUT #else # define PWM_TIM5_CH1CFG 0 #endif -#ifdef CONFIG_STM32H7_TIM5_CH2OUT +#ifdef CONFIG_STM32_TIM5_CH2OUT # define PWM_TIM5_CH2CFG GPIO_TIM5_CH2OUT #else # define PWM_TIM5_CH2CFG 0 #endif -#ifdef CONFIG_STM32H7_TIM5_CH3OUT +#ifdef CONFIG_STM32_TIM5_CH3OUT # define PWM_TIM5_CH3CFG GPIO_TIM5_CH3OUT #else # define PWM_TIM5_CH3CFG 0 #endif -#ifdef CONFIG_STM32H7_TIM5_CH4OUT +#ifdef CONFIG_STM32_TIM5_CH4OUT # define PWM_TIM5_CH4CFG GPIO_TIM5_CH4OUT #else # define PWM_TIM5_CH4CFG 0 #endif -#ifdef CONFIG_STM32H7_TIM8_CH1OUT +#ifdef CONFIG_STM32_TIM8_CH1OUT # define PWM_TIM8_CH1CFG GPIO_TIM8_CH1OUT #else # define PWM_TIM8_CH1CFG 0 #endif -#ifdef CONFIG_STM32H7_TIM8_CH1NOUT +#ifdef CONFIG_STM32_TIM8_CH1NOUT # define PWM_TIM8_CH1NCFG GPIO_TIM8_CH1NOUT #else # define PWM_TIM8_CH1NCFG 0 #endif -#ifdef CONFIG_STM32H7_TIM8_CH2OUT +#ifdef CONFIG_STM32_TIM8_CH2OUT # define PWM_TIM8_CH2CFG GPIO_TIM8_CH2OUT #else # define PWM_TIM8_CH2CFG 0 #endif -#ifdef CONFIG_STM32H7_TIM8_CH2NOUT +#ifdef CONFIG_STM32_TIM8_CH2NOUT # define PWM_TIM8_CH2NCFG GPIO_TIM8_CH2NOUT #else # define PWM_TIM8_CH2NCFG 0 #endif -#ifdef CONFIG_STM32H7_TIM8_CH3OUT +#ifdef CONFIG_STM32_TIM8_CH3OUT # define PWM_TIM8_CH3CFG GPIO_TIM8_CH3OUT #else # define PWM_TIM8_CH3CFG 0 #endif -#ifdef CONFIG_STM32H7_TIM8_CH3NOUT +#ifdef CONFIG_STM32_TIM8_CH3NOUT # define PWM_TIM8_CH3NCFG GPIO_TIM8_CH3NOUT #else # define PWM_TIM8_CH3NCFG 0 #endif -#ifdef CONFIG_STM32H7_TIM8_CH4OUT +#ifdef CONFIG_STM32_TIM8_CH4OUT # define PWM_TIM8_CH4CFG GPIO_TIM8_CH4OUT #else # define PWM_TIM8_CH4CFG 0 #endif -#ifdef CONFIG_STM32H7_TIM12_CH1OUT +#ifdef CONFIG_STM32_TIM12_CH1OUT # define PWM_TIM12_CH1CFG GPIO_TIM12_CH1OUT #else # define PWM_TIM12_CH1CFG 0 #endif -#ifdef CONFIG_STM32H7_TIM12_CH2OUT +#ifdef CONFIG_STM32_TIM12_CH2OUT # define PWM_TIM12_CH2CFG GPIO_TIM12_CH2OUT #else # define PWM_TIM12_CH2CFG 0 #endif -#ifdef CONFIG_STM32H7_TIM13_CH1OUT +#ifdef CONFIG_STM32_TIM13_CH1OUT # define PWM_TIM13_CH1CFG GPIO_TIM13_CH1OUT #else # define PWM_TIM13_CH1CFG 0 #endif -#ifdef CONFIG_STM32H7_TIM14_CH1OUT +#ifdef CONFIG_STM32_TIM14_CH1OUT # define PWM_TIM14_CH1CFG GPIO_TIM14_CH1OUT #else # define PWM_TIM14_CH1CFG 0 #endif -#ifdef CONFIG_STM32H7_TIM15_CH1OUT +#ifdef CONFIG_STM32_TIM15_CH1OUT # define PWM_TIM15_CH1CFG GPIO_TIM15_CH1OUT #else # define PWM_TIM15_CH1CFG 0 #endif -#ifdef CONFIG_STM32H7_TIM15_CH1NOUT +#ifdef CONFIG_STM32_TIM15_CH1NOUT # define PWM_TIM15_CH1NCFG GPIO_TIM15_CH1NOUT #else # define PWM_TIM15_CH1NCFG 0 #endif -#ifdef CONFIG_STM32H7_TIM15_CH2OUT +#ifdef CONFIG_STM32_TIM15_CH2OUT # define PWM_TIM15_CH2CFG GPIO_TIM15_CH2OUT #else # define PWM_TIM15_CH2CFG 0 #endif -#ifdef CONFIG_STM32H7_TIM16_CH1OUT +#ifdef CONFIG_STM32_TIM16_CH1OUT # define PWM_TIM16_CH1CFG GPIO_TIM16_CH1OUT #else # define PWM_TIM16_CH1CFG 0 #endif -#ifdef CONFIG_STM32H7_TIM16_CH1NOUT +#ifdef CONFIG_STM32_TIM16_CH1NOUT # define PWM_TIM16_CH1NCFG GPIO_TIM16_CH1NOUT #else # define PWM_TIM16_CH1NCFG 0 #endif -#ifdef CONFIG_STM32H7_TIM17_CH1OUT +#ifdef CONFIG_STM32_TIM17_CH1OUT # define PWM_TIM17_CH1CFG GPIO_TIM17_CH1OUT #else # define PWM_TIM17_CH1CFG 0 #endif -#ifdef CONFIG_STM32H7_TIM17_CH1NOUT +#ifdef CONFIG_STM32_TIM17_CH1NOUT # define PWM_TIM17_CH1NCFG GPIO_TIM17_CH1NOUT #else # define PWM_TIM17_CH1NCFG 0 @@ -764,21 +764,21 @@ /* Complementary outputs support */ -#if defined(CONFIG_STM32H7_TIM1_CH1NOUT) || defined(CONFIG_STM32H7_TIM1_CH2NOUT) || \ - defined(CONFIG_STM32H7_TIM1_CH3NOUT) +#if defined(CONFIG_STM32_TIM1_CH1NOUT) || defined(CONFIG_STM32_TIM1_CH2NOUT) || \ + defined(CONFIG_STM32_TIM1_CH3NOUT) # define HAVE_TIM1_COMPLEMENTARY #endif -#if defined(CONFIG_STM32H7_TIM8_CH1NOUT) || defined(CONFIG_STM32H7_TIM8_CH2NOUT) || \ - defined(CONFIG_STM32H7_TIM8_CH3NOUT) +#if defined(CONFIG_STM32_TIM8_CH1NOUT) || defined(CONFIG_STM32_TIM8_CH2NOUT) || \ + defined(CONFIG_STM32_TIM8_CH3NOUT) # define HAVE_TIM8_COMPLEMENTARY #endif -#if defined(CONFIG_STM32H7_TIM15_CH1NOUT) +#if defined(CONFIG_STM32_TIM15_CH1NOUT) # define HAVE_TIM15_COMPLEMENTARY #endif -#if defined(CONFIG_STM32H7_TIM16_CH1NOUT) +#if defined(CONFIG_STM32_TIM16_CH1NOUT) # define HAVE_TIM16_COMPLEMENTARY #endif -#if defined(CONFIG_STM32H7_TIM17_CH1NOUT) +#if defined(CONFIG_STM32_TIM17_CH1NOUT) # define HAVE_TIM17_COMPLEMENTARY #endif #if defined(HAVE_TIM1_COMPLEMENTARY) || defined(HAVE_TIM8_COMPLEMENTARY) || \ @@ -789,7 +789,7 @@ /* Low-level ops helpers ****************************************************/ -#ifdef CONFIG_STM32H7_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS /* NOTE: * low-level ops accept pwm_lowerhalf_s as first argument, but llops access @@ -925,7 +925,7 @@ enum stm32_pwm_output_e #endif }; -#ifdef CONFIG_STM32H7_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS /* This structure provides the publicly visible representation of the * "lower-half" PWM driver structure. @@ -1011,7 +1011,7 @@ struct stm32_pwm_ops_s #endif }; -#endif /* CONFIG_STM32H7_PWM_LL_OPS */ +#endif /* CONFIG_STM32_PWM_LL_OPS */ /**************************************************************************** * Public Data @@ -1057,5 +1057,5 @@ struct pwm_lowerhalf_s *stm32_pwminitialize(int timer); #endif #endif /* __ASSEMBLY__ */ -#endif /* CONFIG_STM32H7_PWM */ +#endif /* CONFIG_STM32_PWM */ #endif /* __ARCH_ARM_SRC_STM32H7_STM32_PWM_H */ diff --git a/arch/arm/src/stm32h7/stm32_pwr.c b/arch/arm/src/stm32h7/stm32_pwr.c index c1d97009676e4..287ca4b42ea5c 100644 --- a/arch/arm/src/stm32h7/stm32_pwr.c +++ b/arch/arm/src/stm32h7/stm32_pwr.c @@ -37,7 +37,7 @@ #include "stm32_pwr.h" #include "stm32_gpio.h" -#if defined(CONFIG_STM32H7_PWR) +#if defined(CONFIG_STM32_PWR) #define BREG_WAIT_USTIMEOUT 1000 /* uS to wait for regulator to come ready */ diff --git a/arch/arm/src/stm32h7/stm32_qencoder.c b/arch/arm/src/stm32h7/stm32_qencoder.c index 406ec36796b64..d3d29deb35cb7 100644 --- a/arch/arm/src/stm32h7/stm32_qencoder.c +++ b/arch/arm/src/stm32h7/stm32_qencoder.c @@ -60,14 +60,14 @@ /* If TIM2 or TIM5 are enabled, then we have 32-bit timers */ -#if defined(CONFIG_STM32H7_TIM2_QE) || defined(CONFIG_STM32H7_TIM5_QE) +#if defined(CONFIG_STM32_TIM2_QE) || defined(CONFIG_STM32_TIM5_QE) # define HAVE_32BIT_TIMERS 1 #endif /* If TIM1,3,4, or 8 are enabled, then we have 16-bit timers */ -#if defined(CONFIG_STM32H7_TIM1_QE) || defined(CONFIG_STM32H7_TIM3_QE) || \ - defined(CONFIG_STM32H7_TIM4_QE) || defined(CONFIG_STM32H7_TIM8_QE) +#if defined(CONFIG_STM32_TIM1_QE) || defined(CONFIG_STM32_TIM3_QE) || \ + defined(CONFIG_STM32_TIM4_QE) || defined(CONFIG_STM32_TIM8_QE) # define HAVE_16BIT_TIMERS 1 #endif @@ -89,51 +89,51 @@ /* Input filter *************************************************************/ -#ifdef CONFIG_STM32H7_QENCODER_FILTER -# if defined(CONFIG_STM32H7_QENCODER_SAMPLE_FDTS) -# if defined(CONFIG_STM32H7_QENCODER_SAMPLE_EVENT_1) +#ifdef CONFIG_STM32_QENCODER_FILTER +# if defined(CONFIG_STM32_QENCODER_SAMPLE_FDTS) +# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_1) # define STM32_QENCODER_ICF GTIM_CCMR_ICF_NOFILT # endif -# elif defined(CONFIG_STM32H7_QENCODER_SAMPLE_CKINT) -# if defined(CONFIG_STM32H7_QENCODER_SAMPLE_EVENT_2) +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_CKINT) +# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_2) # define STM32_QENCODER_ICF GTIM_CCMR_ICF_FCKINT2 -# elif defined(CONFIG_STM32H7_QENCODER_SAMPLE_EVENT_4) +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_4) # define STM32_QENCODER_ICF GTIM_CCMR_ICF_FCKINT4 -# elif defined(CONFIG_STM32H7_QENCODER_SAMPLE_EVENT_8) +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_8) # define STM32_QENCODER_ICF GTIM_CCMR_ICF_FCKINT8 # endif -# elif defined(CONFIG_STM32H7_QENCODER_SAMPLE_FDTS_2) -# if defined(CONFIG_STM32H7_QENCODER_SAMPLE_EVENT_6) +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_FDTS_2) +# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_6) # define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd26 -# elif defined(CONFIG_STM32H7_QENCODER_SAMPLE_EVENT_8) +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_8) # define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd28 # endif -# elif defined(CONFIG_STM32H7_QENCODER_SAMPLE_FDTS_4) -# if defined(CONFIG_STM32H7_QENCODER_SAMPLE_EVENT_6) +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_FDTS_4) +# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_6) # define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd46 -# elif defined(CONFIG_STM32H7_QENCODER_SAMPLE_EVENT_8) +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_8) # define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd48 # endif -# elif defined(CONFIG_STM32H7_QENCODER_SAMPLE_FDTS_8) -# if defined(CONFIG_STM32H7_QENCODER_SAMPLE_EVENT_6) +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_FDTS_8) +# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_6) # define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd86 -# elif defined(CONFIG_STM32H7_QENCODER_SAMPLE_EVENT_8) +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_8) # define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd88 # endif -# elif defined(CONFIG_STM32H7_QENCODER_SAMPLE_FDTS_16) -# if defined(CONFIG_STM32H7_QENCODER_SAMPLE_EVENT_5) +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_FDTS_16) +# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_5) # define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd165 -# elif defined(CONFIG_STM32H7_QENCODER_SAMPLE_EVENT_6) +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_6) # define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd166 -# elif defined(CONFIG_STM32H7_QENCODER_SAMPLE_EVENT_8) +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_8) # define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd168 # endif -# elif defined(CONFIG_STM32H7_QENCODER_SAMPLE_FDTS_32) -# if defined(CONFIG_STM32H7_QENCODER_SAMPLE_EVENT_5) +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_FDTS_32) +# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_5) # define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd325 -# elif defined(CONFIG_STM32H7_QENCODER_SAMPLE_EVENT_6) +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_6) # define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd326 -# elif defined(CONFIG_STM32H7_QENCODER_SAMPLE_EVENT_8) +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_8) # define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd328 # endif # endif @@ -276,7 +276,7 @@ static const struct qe_ops_s g_qecallbacks = /* Per-timer state structures */ -#ifdef CONFIG_STM32H7_TIM1_QE +#ifdef CONFIG_STM32_TIM1_QE static const struct stm32_qeconfig_s g_tim1config = { .timid = 1, @@ -287,7 +287,7 @@ static const struct stm32_qeconfig_s g_tim1config = .regaddr = STM32_RCC_APB2ENR, .enable = RCC_APB2ENR_TIM1EN, .base = STM32_TIM1_BASE, - .psc = CONFIG_STM32H7_TIM1_QEPSC, + .psc = CONFIG_STM32_TIM1_QEPSC, .ti1cfg = GPIO_TIM1_CH1IN, .ti2cfg = GPIO_TIM1_CH2IN, }; @@ -302,7 +302,7 @@ static struct stm32_lowerhalf_s g_tim1lower = #endif -#ifdef CONFIG_STM32H7_TIM2_QE +#ifdef CONFIG_STM32_TIM2_QE static const struct stm32_qeconfig_s g_tim2config = { .timid = 2, @@ -313,7 +313,7 @@ static const struct stm32_qeconfig_s g_tim2config = .regaddr = STM32_RCC_APB1LENR, .enable = RCC_APB1LENR_TIM2EN, .base = STM32_TIM2_BASE, - .psc = CONFIG_STM32H7_TIM2_QEPSC, + .psc = CONFIG_STM32_TIM2_QEPSC, .ti1cfg = GPIO_TIM2_CH1IN, .ti2cfg = GPIO_TIM2_CH2IN, }; @@ -328,7 +328,7 @@ static struct stm32_lowerhalf_s g_tim2lower = #endif -#ifdef CONFIG_STM32H7_TIM3_QE +#ifdef CONFIG_STM32_TIM3_QE static const struct stm32_qeconfig_s g_tim3config = { .timid = 3, @@ -339,7 +339,7 @@ static const struct stm32_qeconfig_s g_tim3config = .regaddr = STM32_RCC_APB1LENR, .enable = RCC_APB1LENR_TIM3EN, .base = STM32_TIM3_BASE, - .psc = CONFIG_STM32H7_TIM3_QEPSC, + .psc = CONFIG_STM32_TIM3_QEPSC, .ti1cfg = GPIO_TIM3_CH1IN, .ti2cfg = GPIO_TIM3_CH2IN, }; @@ -354,7 +354,7 @@ static struct stm32_lowerhalf_s g_tim3lower = #endif -#ifdef CONFIG_STM32H7_TIM4_QE +#ifdef CONFIG_STM32_TIM4_QE static const struct stm32_qeconfig_s g_tim4config = { .timid = 4, @@ -365,7 +365,7 @@ static const struct stm32_qeconfig_s g_tim4config = .regaddr = STM32_RCC_APB1LENR, .enable = RCC_APB1LENR_TIM4EN, .base = STM32_TIM4_BASE, - .psc = CONFIG_STM32H7_TIM4_QEPSC, + .psc = CONFIG_STM32_TIM4_QEPSC, .ti1cfg = GPIO_TIM4_CH1IN, .ti2cfg = GPIO_TIM4_CH2IN, }; @@ -380,7 +380,7 @@ static struct stm32_lowerhalf_s g_tim4lower = #endif -#ifdef CONFIG_STM32H7_TIM5_QE +#ifdef CONFIG_STM32_TIM5_QE static const struct stm32_qeconfig_s g_tim5config = { .timid = 5, @@ -391,7 +391,7 @@ static const struct stm32_qeconfig_s g_tim5config = .regaddr = STM32_RCC_APB1LENR, .enable = RCC_APB1LENR_TIM5EN, .base = STM32_TIM5_BASE, - .psc = CONFIG_STM32H7_TIM5_QEPSC, + .psc = CONFIG_STM32_TIM5_QEPSC, .ti1cfg = GPIO_TIM5_CH1IN, .ti2cfg = GPIO_TIM5_CH2IN, }; @@ -406,7 +406,7 @@ static struct stm32_lowerhalf_s g_tim5lower = #endif -#ifdef CONFIG_STM32H7_TIM8_QE +#ifdef CONFIG_STM32_TIM8_QE static const struct stm32_qeconfig_s g_tim8config = { .timid = 8, @@ -417,7 +417,7 @@ static const struct stm32_qeconfig_s g_tim8config = .regaddr = STM32_RCC_APB2ENR, .enable = RCC_APB2ENR_TIM8EN, .base = STM32_TIM8_BASE, - .psc = CONFIG_STM32H7_TIM8_QEPSC, + .psc = CONFIG_STM32_TIM8_QEPSC, .ti1cfg = GPIO_TIM8_CH1IN, .ti2cfg = GPIO_TIM8_CH2IN, }; @@ -562,7 +562,7 @@ static void stm32_dumpregs(struct stm32_lowerhalf_s *priv, stm32_getreg16(priv, STM32_GTIM_CCR2_OFFSET), stm32_getreg16(priv, STM32_GTIM_CCR3_OFFSET), stm32_getreg16(priv, STM32_GTIM_CCR4_OFFSET)); -#if defined(CONFIG_STM32H7_TIM1_QE) || defined(CONFIG_STM32H7_TIM8_QE) +#if defined(CONFIG_STM32_TIM1_QE) || defined(CONFIG_STM32_TIM8_QE) if (priv->config->timid == 1 || priv->config->timid == 8) { sninfo(" RCR: %04x BDTR: %04x DCR: %04x DMAR: %04x\n", @@ -593,27 +593,27 @@ static struct stm32_lowerhalf_s *stm32_tim2lower(int tim) { switch (tim) { -#ifdef CONFIG_STM32H7_TIM1_QE +#ifdef CONFIG_STM32_TIM1_QE case 1: return &g_tim1lower; #endif -#ifdef CONFIG_STM32H7_TIM2_QE +#ifdef CONFIG_STM32_TIM2_QE case 2: return &g_tim2lower; #endif -#ifdef CONFIG_STM32H7_TIM3_QE +#ifdef CONFIG_STM32_TIM3_QE case 3: return &g_tim3lower; #endif -#ifdef CONFIG_STM32H7_TIM4_QE +#ifdef CONFIG_STM32_TIM4_QE case 4: return &g_tim4lower; #endif -#ifdef CONFIG_STM32H7_TIM5_QE +#ifdef CONFIG_STM32_TIM5_QE case 5: return &g_tim5lower; #endif -#ifdef CONFIG_STM32H7_TIM8_QE +#ifdef CONFIG_STM32_TIM8_QE case 8: return &g_tim8lower; #endif @@ -733,7 +733,7 @@ static int stm32_setup(struct qe_lowerhalf_s *lower) stm32_putreg16(priv, STM32_GTIM_PSC_OFFSET, (uint16_t)priv->config->psc); -#if defined(CONFIG_STM32H7_TIM1_QE) || defined(CONFIG_STM32H7_TIM8_QE) +#if defined(CONFIG_STM32_TIM1_QE) || defined(CONFIG_STM32_TIM8_QE) if (priv->config->timid == 1 || priv->config->timid == 8) { /* Clear the Repetition Counter value */ @@ -944,37 +944,37 @@ static int stm32_shutdown(struct qe_lowerhalf_s *lower) switch (priv->config->timid) { -#ifdef CONFIG_STM32H7_TIM1_QE +#ifdef CONFIG_STM32_TIM1_QE case 1: regaddr = STM32_RCC_APB2RSTR; resetbit = RCC_APB2RSTR_TIM1RST; break; #endif -#ifdef CONFIG_STM32H7_TIM2_QE +#ifdef CONFIG_STM32_TIM2_QE case 2: regaddr = STM32_RCC_APB1LRSTR; resetbit = RCC_APB1LRSTR_TIM2RST; break; #endif -#ifdef CONFIG_STM32H7_TIM3_QE +#ifdef CONFIG_STM32_TIM3_QE case 3: regaddr = STM32_RCC_APB1LRSTR; resetbit = RCC_APB1LRSTR_TIM3RST; break; #endif -#ifdef CONFIG_STM32H7_TIM4_QE +#ifdef CONFIG_STM32_TIM4_QE case 4: regaddr = STM32_RCC_APB1LRSTR; resetbit = RCC_APB1LRSTR_TIM4RST; break; #endif -#ifdef CONFIG_STM32H7_TIM5_QE +#ifdef CONFIG_STM32_TIM5_QE case 5: regaddr = STM32_RCC_APB1LRSTR; resetbit = RCC_APB1LRSTR_TIM5RST; break; #endif -#ifdef CONFIG_STM32H7_TIM8_QE +#ifdef CONFIG_STM32_TIM8_QE case 8: regaddr = STM32_RCC_APB2RSTR; resetbit = RCC_APB2RSTR_TIM8RST; diff --git a/arch/arm/src/stm32h7/stm32_qencoder.h b/arch/arm/src/stm32h7/stm32_qencoder.h index a8b93505d59b6..6ad6f0f392eb3 100644 --- a/arch/arm/src/stm32h7/stm32_qencoder.h +++ b/arch/arm/src/stm32h7/stm32_qencoder.h @@ -38,42 +38,42 @@ ****************************************************************************/ /* Timer devices may be used for different purposes. One special purpose is - * as a quadrature encoder input device. If CONFIG_STM32H7_TIMn is defined - * then the CONFIG_STM32H7_TIMn_QE must also be defined to indicate that + * as a quadrature encoder input device. If CONFIG_STM32_TIMn is defined + * then the CONFIG_STM32_TIMn_QE must also be defined to indicate that * timer "n" is intended to be used for as a quadrature encoder. */ -#ifndef CONFIG_STM32H7_TIM1 -# undef CONFIG_STM32H7_TIM1_QE +#ifndef CONFIG_STM32_TIM1 +# undef CONFIG_STM32_TIM1_QE #endif -#ifndef CONFIG_STM32H7_TIM2 -# undef CONFIG_STM32H7_TIM2_QE +#ifndef CONFIG_STM32_TIM2 +# undef CONFIG_STM32_TIM2_QE #endif -#ifndef CONFIG_STM32H7_TIM3 -# undef CONFIG_STM32H7_TIM3_QE +#ifndef CONFIG_STM32_TIM3 +# undef CONFIG_STM32_TIM3_QE #endif -#ifndef CONFIG_STM32H7_TIM4 -# undef CONFIG_STM32H7_TIM4_QE +#ifndef CONFIG_STM32_TIM4 +# undef CONFIG_STM32_TIM4_QE #endif -#ifndef CONFIG_STM32H7_TIM5 -# undef CONFIG_STM32H7_TIM5_QE +#ifndef CONFIG_STM32_TIM5 +# undef CONFIG_STM32_TIM5_QE #endif -#ifndef CONFIG_STM32H7_TIM8 -# undef CONFIG_STM32H7_TIM8_QE +#ifndef CONFIG_STM32_TIM8 +# undef CONFIG_STM32_TIM8_QE #endif /* Only timers 2-5, and 1 & 8 can be used as a quadrature encoder * (at least for the STM32 H7) */ -#undef CONFIG_STM32H7_TIM6_QE -#undef CONFIG_STM32H7_TIM7_QE -#undef CONFIG_STM32H7_TIM9_QE -#undef CONFIG_STM32H7_TIM10_QE -#undef CONFIG_STM32H7_TIM11_QE -#undef CONFIG_STM32H7_TIM12_QE -#undef CONFIG_STM32H7_TIM13_QE -#undef CONFIG_STM32H7_TIM14_QE +#undef CONFIG_STM32_TIM6_QE +#undef CONFIG_STM32_TIM7_QE +#undef CONFIG_STM32_TIM9_QE +#undef CONFIG_STM32_TIM10_QE +#undef CONFIG_STM32_TIM11_QE +#undef CONFIG_STM32_TIM12_QE +#undef CONFIG_STM32_TIM13_QE +#undef CONFIG_STM32_TIM14_QE /**************************************************************************** * Included Files diff --git a/arch/arm/src/stm32h7/stm32_qspi.c b/arch/arm/src/stm32h7/stm32_qspi.c index bb985448e65ef..9de983152154c 100644 --- a/arch/arm/src/stm32h7/stm32_qspi.c +++ b/arch/arm/src/stm32h7/stm32_qspi.c @@ -57,7 +57,7 @@ #include "stm32_rcc.h" #include "hardware/stm32_qspi.h" -#ifdef CONFIG_STM32H7_QUADSPI +#ifdef CONFIG_STM32_QSPI /**************************************************************************** * Pre-processor Definitions @@ -68,7 +68,7 @@ /* Check if QSPI debug is enabled */ #ifndef CONFIG_DEBUG_DMA -# undef CONFIG_STM32H7_QSPI_DMADEBUG +# undef CONFIG_STM32_QSPI_DMADEBUG #endif #define DMA_INITIAL 0 @@ -81,7 +81,7 @@ /* Can't have both interrupt-driven QSPI and DMA QSPI */ -#if defined(CONFIG_STM32H7_QSPI_INTERRUPTS) && defined(CONFIG_STM32H7_QSPI_DMA) +#if defined(CONFIG_STM32_QSPI_INTERRUPTS) && defined(CONFIG_STM32_QSPI_DMA) # error "Cannot enable both interrupt mode and DMA mode for QSPI" #endif @@ -93,7 +93,7 @@ GPIO_QSPI_IO1 GPIO_QSPI_IO2 GPIO_QSPI_IO3 GPIO_QSPI_SCK in your board.h #endif -#ifdef CONFIG_STM32H7_QSPI_DMA +#ifdef CONFIG_STM32_QSPI_DMA # ifdef DMAMAP_QUADSPI @@ -105,26 +105,26 @@ # define DMACHAN_QUADSPI DMAMAP_QUADSPI # endif -# if defined(CONFIG_STM32H7_QSPI_DMAPRIORITY_LOW) +# if defined(CONFIG_STM32_QSPI_DMAPRIORITY_LOW) # define QSPI_DMA_PRIO DMA_SCR_PRILO -# elif defined(CONFIG_STM32H7_QSPI_DMAPRIORITY_MEDIUM) +# elif defined(CONFIG_STM32_QSPI_DMAPRIORITY_MEDIUM) # define QSPI_DMA_PRIO DMA_SCR_PRIMED -# elif defined(CONFIG_STM32H7_QSPI_DMAPRIORITY_HIGH) +# elif defined(CONFIG_STM32_QSPI_DMAPRIORITY_HIGH) # define QSPI_DMA_PRIO DMA_SCR_PRIHI -# elif defined(CONFIG_STM32H7_QSPI_DMAPRIORITY_VERYHIGH) +# elif defined(CONFIG_STM32_QSPI_DMAPRIORITY_VERYHIGH) # define QSPI_DMA_PRIO DMA_SCR_PRIVERYHI # else # define QSPI_DMA_PRIO DMA_SCR_PRIMED # endif -#endif /* CONFIG_STM32H7_QSPI_DMA */ +#endif /* CONFIG_STM32_QSPI_DMA */ #ifndef STM32_SYSCLK_FREQUENCY # error your board.h needs to define the value of STM32_SYSCLK_FREQUENCY #endif -#if !defined(CONFIG_STM32H7_QSPI_FLASH_SIZE) || 0 == CONFIG_STM32H7_QSPI_FLASH_SIZE -# error you must specify a positive flash size via CONFIG_STM32H7_QSPI_FLASH_SIZE +#if !defined(CONFIG_STM32_QSPI_FLASH_SIZE) || 0 == CONFIG_STM32_QSPI_FLASH_SIZE +# error you must specify a positive flash size via CONFIG_STM32_QSPI_FLASH_SIZE #endif /* DMA timeout. The value is not critical; we just don't want the system to @@ -189,14 +189,14 @@ struct stm32h7_qspidev_s mutex_t lock; /* Assures mutually exclusive access to QSPI */ bool memmap; /* TRUE: Controller is in memory mapped mode */ -#ifdef CONFIG_STM32H7_QSPI_INTERRUPTS +#ifdef CONFIG_STM32_QSPI_INTERRUPTS xcpt_t handler; /* Interrupt handler */ uint8_t irq; /* Interrupt number */ sem_t op_sem; /* Block until complete */ struct qspi_xctnspec_s *xctn; /* context of transaction in progress */ #endif -#ifdef CONFIG_STM32H7_QSPI_DMA +#ifdef CONFIG_STM32_QSPI_DMA bool candma; /* DMA is supported */ sem_t dmawait; /* Used to wait for DMA completion */ int result; /* DMA result */ @@ -206,11 +206,11 @@ struct stm32h7_qspidev_s /* Debug stuff */ -#ifdef CONFIG_STM32H7_QSPI_DMADEBUG +#ifdef CONFIG_STM32_QSPI_DMADEBUG struct stm32h7_dmaregs_s dmaregs[DMA_NSAMPLES]; #endif -#ifdef CONFIG_STM32H7_QSPI_REGDEBUG +#ifdef CONFIG_STM32_QSPI_REGDEBUG bool wrlast; /* Last was a write */ uint32_t addresslast; /* Last address */ uint32_t valuelast; /* Last value */ @@ -247,7 +247,7 @@ struct qspi_xctnspec_s uint8_t isddr; /* true if 'double data rate' */ uint8_t issioo; /* true if 'send instruction only once' mode */ -#ifdef CONFIG_STM32H7_QSPI_INTERRUPTS +#ifdef CONFIG_STM32_QSPI_INTERRUPTS uint8_t function; /* functional mode; to distinguish a read or write */ int8_t disposition; /* how it all turned out */ uint32_t idxnow; /* index into databuffer of current byte in transfer */ @@ -260,7 +260,7 @@ struct qspi_xctnspec_s /* Helpers */ -#ifdef CONFIG_STM32H7_QSPI_REGDEBUG +#ifdef CONFIG_STM32_QSPI_REGDEBUG static bool qspi_checkreg(struct stm32h7_qspidev_s *priv, bool wr, uint32_t value, uint32_t address); #else @@ -287,16 +287,16 @@ static void qspi_dumpgpioconfig(const char *msg); /* Interrupts */ -#ifdef CONFIG_STM32H7_QSPI_INTERRUPTS +#ifdef CONFIG_STM32_QSPI_INTERRUPTS static int qspi0_interrupt(int irq, void *context, void *arg); #endif /* DMA support */ -#ifdef CONFIG_STM32H7_QSPI_DMA +#ifdef CONFIG_STM32_QSPI_DMA -# ifdef CONFIG_STM32H7_QSPI_DMADEBUG +# ifdef CONFIG_STM32_QSPI_DMADEBUG # define qspi_dma_sample(s,i) stm32h7_dmasample((s)->dmach, &(s)->dmaregs[i]) static void qspi_dma_sampleinit(struct stm32h7_qspidev_s *priv); static void qspi_dma_sampledone(struct stm32h7_qspidev_s *priv); @@ -306,8 +306,8 @@ static void qspi_dma_sampledone(struct stm32h7_qspidev_s *priv); # define qspi_dma_sampledone(s) # endif -# ifndef CONFIG_STM32H7_QSPI_DMATHRESHOLD -# define CONFIG_STM32H7_QSPI_DMATHRESHOLD 4 +# ifndef CONFIG_STM32_QSPI_DMATHRESHOLD +# define CONFIG_STM32_QSPI_DMATHRESHOLD 4 # endif #endif @@ -361,13 +361,13 @@ static struct stm32h7_qspidev_s g_qspi0dev = }, .base = STM32_QUADSPI_BASE, .lock = NXMUTEX_INITIALIZER, -#ifdef CONFIG_STM32H7_QSPI_INTERRUPTS +#ifdef CONFIG_STM32_QSPI_INTERRUPTS .handler = qspi0_interrupt, .irq = STM32_IRQ_QUADSPI, .op_sem = SEM_INITIALIZER(0), #endif .intf = 0, -#ifdef CONFIG_STM32H7_QSPI_DMA +#ifdef CONFIG_STM32_QSPI_DMA .candma = true, .dmawait = SEM_INITIALIZER(0), #endif @@ -393,7 +393,7 @@ static struct stm32h7_qspidev_s g_qspi0dev = * ****************************************************************************/ -#ifdef CONFIG_STM32H7_QSPI_REGDEBUG +#ifdef CONFIG_STM32_QSPI_REGDEBUG static bool qspi_checkreg(struct stm32h7_qspidev_s *priv, bool wr, uint32_t value, uint32_t address) { @@ -445,7 +445,7 @@ static inline uint32_t qspi_getreg(struct stm32h7_qspidev_s *priv, uint32_t address = priv->base + offset; uint32_t value = getreg32(address); -#ifdef CONFIG_STM32H7_QSPI_REGDEBUG +#ifdef CONFIG_STM32_QSPI_REGDEBUG if (qspi_checkreg(priv, false, value, address)) { spiinfo("%08" PRIx32 "->%08" PRIx32 "\n", address, value); @@ -468,7 +468,7 @@ static inline void qspi_putreg(struct stm32h7_qspidev_s *priv, { uint32_t address = priv->base + offset; -#ifdef CONFIG_STM32H7_QSPI_REGDEBUG +#ifdef CONFIG_STM32_QSPI_REGDEBUG if (qspi_checkreg(priv, true, value, address)) { spiinfo("%08" PRIx32 "<-%08" PRIx32 "\n", address, value); @@ -649,7 +649,7 @@ static void qspi_dumpgpioconfig(const char *msg) } #endif -#ifdef CONFIG_STM32H7_QSPI_DMADEBUG +#ifdef CONFIG_STM32_QSPI_DMADEBUG /**************************************************************************** * Name: qspi_dma_sampleinit * @@ -867,7 +867,7 @@ static int qspi_setupxctnfromcmd(struct qspi_xctnspec_s *xctn, xctn->isddr = 0; } -#if defined(CONFIG_STM32H7_QSPI_INTERRUPTS) +#if defined(CONFIG_STM32_QSPI_INTERRUPTS) xctn->function = QSPICMD_ISWRITE(cmdinfo->flags) ? CCR_FMODE_INDWR : CCR_FMODE_INDRD; xctn->disposition = - EIO; @@ -1010,7 +1010,7 @@ static int qspi_setupxctnfrommem(struct qspi_xctnspec_s *xctn, xctn->isddr = 0; -#if defined(CONFIG_STM32H7_QSPI_INTERRUPTS) +#if defined(CONFIG_STM32_QSPI_INTERRUPTS) xctn->function = QSPIMEM_ISWRITE(meminfo->flags) ? CCR_FMODE_INDWR : CCR_FMODE_INDRD; xctn->disposition = - EIO; @@ -1135,7 +1135,7 @@ static void qspi_ccrconfig(struct stm32h7_qspidev_s *priv, } } -#if defined(CONFIG_STM32H7_QSPI_INTERRUPTS) +#if defined(CONFIG_STM32_QSPI_INTERRUPTS) /**************************************************************************** * Name: qspi0_interrupt * @@ -1358,7 +1358,7 @@ static int qspi0_interrupt(int irq, void *context, void *arg) return OK; } -#elif defined(CONFIG_STM32H7_QSPI_DMA) +#elif defined(CONFIG_STM32_QSPI_DMA) /**************************************************************************** * Name: qspi_dma_timeout * @@ -1631,7 +1631,7 @@ static int qspi_memory_dma(struct stm32h7_qspidev_s *priv, } #endif -#if !defined(CONFIG_STM32H7_QSPI_INTERRUPTS) +#if !defined(CONFIG_STM32_QSPI_INTERRUPTS) /**************************************************************************** * Name: qspi_receive_blocking * @@ -2065,7 +2065,7 @@ static int qspi_command(struct qspi_dev_s *dev, QSPI_FCR_CTEF | QSPI_FCR_CTCF | QSPI_FCR_CSMF | QSPI_FCR_CTOF, STM32_QUADSPI_FCR_OFFSET); -#ifdef CONFIG_STM32H7_QSPI_INTERRUPTS +#ifdef CONFIG_STM32_QSPI_INTERRUPTS /* interrupt mode will need access to the transaction context */ priv->xctn = &xctn; @@ -2246,7 +2246,7 @@ static int qspi_memory(struct qspi_dev_s *dev, QSPI_FCR_CTEF | QSPI_FCR_CTCF | QSPI_FCR_CSMF | QSPI_FCR_CTOF, STM32_QUADSPI_FCR_OFFSET); -#ifdef CONFIG_STM32H7_QSPI_INTERRUPTS +#ifdef CONFIG_STM32_QSPI_INTERRUPTS /* interrupt mode will need access to the transaction context */ priv->xctn = &xctn; @@ -2307,11 +2307,11 @@ static int qspi_memory(struct qspi_dev_s *dev, ret = xctn.disposition; -#elif defined(CONFIG_STM32H7_QSPI_DMA) +#elif defined(CONFIG_STM32_QSPI_DMA) /* Can we perform DMA? Should we perform DMA? */ if (priv->candma && - meminfo->buflen > CONFIG_STM32H7_QSPI_DMATHRESHOLD && + meminfo->buflen > CONFIG_STM32_QSPI_DMATHRESHOLD && IS_ALIGNED((uintptr_t)meminfo->buffer, 4) && IS_ALIGNED(meminfo->buflen, 4)) { @@ -2473,18 +2473,18 @@ static int qspi_hw_initialize(struct stm32h7_qspidev_s *priv) regval &= ~(QSPI_CR_TEIE | QSPI_CR_TCIE | QSPI_CR_FTIE | QSPI_CR_SMIE | QSPI_CR_TOIE | QSPI_CR_FSEL | QSPI_CR_DFM); -#if defined(CONFIG_STM32H7_QSPI_MODE_BANK2) +#if defined(CONFIG_STM32_QSPI_MODE_BANK2) regval |= QSPI_CR_FSEL; #endif -#if defined(CONFIG_STM32H7_QSPI_MODE_DUAL) +#if defined(CONFIG_STM32_QSPI_MODE_DUAL) regval |= QSPI_CR_DFM; #endif /* Configure QSPI FIFO Threshold */ regval &= ~(QSPI_CR_FTHRES_MASK); - regval |= ((CONFIG_STM32H7_QSPI_FIFO_THESHOLD - 1) << + regval |= ((CONFIG_STM32_QSPI_FIFO_THESHOLD - 1) << QSPI_CR_FTHRES_SHIFT); qspi_putreg(priv, regval, STM32_QUADSPI_CR_OFFSET); @@ -2505,10 +2505,10 @@ static int qspi_hw_initialize(struct stm32h7_qspidev_s *priv) regval = qspi_getreg(priv, STM32_QUADSPI_DCR_OFFSET); regval &= ~(QSPI_DCR_CKMODE | QSPI_DCR_CSHT_MASK | QSPI_DCR_FSIZE_MASK); regval |= (0x00); - regval |= ((CONFIG_STM32H7_QSPI_CSHT - 1) << QSPI_DCR_CSHT_SHIFT); - if (0 != CONFIG_STM32H7_QSPI_FLASH_SIZE) + regval |= ((CONFIG_STM32_QSPI_CSHT - 1) << QSPI_DCR_CSHT_SHIFT); + if (0 != CONFIG_STM32_QSPI_FLASH_SIZE) { - unsigned int nsize = CONFIG_STM32H7_QSPI_FLASH_SIZE; + unsigned int nsize = CONFIG_STM32_QSPI_FLASH_SIZE; int nlog2size = 31; while ((nsize & 0x80000000) == 0) @@ -2543,7 +2543,7 @@ static int qspi_hw_initialize(struct stm32h7_qspidev_s *priv) ****************************************************************************/ /**************************************************************************** - * Name: stm32h7_qspi_initialize + * Name: stm32_qspi_initialize * * Description: * Initialize the selected QSPI port in master mode @@ -2556,7 +2556,7 @@ static int qspi_hw_initialize(struct stm32h7_qspidev_s *priv) * ****************************************************************************/ -struct qspi_dev_s *stm32h7_qspi_initialize(int intf) +struct qspi_dev_s *stm32_qspi_initialize(int intf) { struct stm32h7_qspidev_s *priv; uint32_t regval; @@ -2618,7 +2618,7 @@ struct qspi_dev_s *stm32h7_qspi_initialize(int intf) { /* Now perform one time initialization. */ -#ifdef CONFIG_STM32H7_QSPI_DMA +#ifdef CONFIG_STM32_QSPI_DMA /* Pre-allocate DMA channels. */ if (priv->candma) @@ -2632,7 +2632,7 @@ struct qspi_dev_s *stm32h7_qspi_initialize(int intf) } #endif -#ifdef CONFIG_STM32H7_QSPI_INTERRUPTS +#ifdef CONFIG_STM32_QSPI_INTERRUPTS /* Attach the interrupt handler */ ret = irq_attach(priv->irq, priv->handler, NULL); @@ -2658,7 +2658,7 @@ struct qspi_dev_s *stm32h7_qspi_initialize(int intf) priv->initialized = true; priv->memmap = false; -#ifdef CONFIG_STM32H7_QSPI_INTERRUPTS +#ifdef CONFIG_STM32_QSPI_INTERRUPTS up_enable_irq(priv->irq); #endif } @@ -2666,12 +2666,12 @@ struct qspi_dev_s *stm32h7_qspi_initialize(int intf) return &priv->qspi; errout_with_irq: -#ifdef CONFIG_STM32H7_QSPI_INTERRUPTS +#ifdef CONFIG_STM32_QSPI_INTERRUPTS irq_detach(priv->irq); errout_with_dmach: #endif -#ifdef CONFIG_STM32H7_QSPI_DMA +#ifdef CONFIG_STM32_QSPI_DMA if (priv->dmach) { stm32_dmafree(priv->dmach); @@ -2683,7 +2683,7 @@ struct qspi_dev_s *stm32h7_qspi_initialize(int intf) } /**************************************************************************** - * Name: stm32h7_qspi_enter_memorymapped + * Name: stm32_qspi_enter_memorymapped * * Description: * Put the QSPI device into memory mapped mode @@ -2697,7 +2697,7 @@ struct qspi_dev_s *stm32h7_qspi_initialize(int intf) * ****************************************************************************/ -void stm32h7_qspi_enter_memorymapped(struct qspi_dev_s *dev, +void stm32_qspi_enter_memorymapped(struct qspi_dev_s *dev, const struct qspi_meminfo_s *meminfo, uint32_t lpto) { @@ -2737,7 +2737,7 @@ void stm32h7_qspi_enter_memorymapped(struct qspi_dev_s *dev, qspi_putreg(&g_qspi0dev, QSPI_FCR_CTOF, STM32_QUADSPI_FCR_OFFSET); -#ifdef CONFIG_STM32H7_QSPI_INTERRUPTS +#ifdef CONFIG_STM32_QSPI_INTERRUPTS /* Enable Timeout interrupt */ regval = qspi_getreg(priv, STM32_QUADSPI_CR_OFFSET); @@ -2756,7 +2756,7 @@ void stm32h7_qspi_enter_memorymapped(struct qspi_dev_s *dev, qspi_setupxctnfrommem(&xctn, meminfo); -#ifdef CONFIG_STM32H7_QSPI_INTERRUPTS +#ifdef CONFIG_STM32_QSPI_INTERRUPTS priv->xctn = NULL; #endif @@ -2775,7 +2775,7 @@ void stm32h7_qspi_enter_memorymapped(struct qspi_dev_s *dev, } /**************************************************************************** - * Name: stm32h7_qspi_exit_memorymapped + * Name: stm32_qspi_exit_memorymapped * * Description: * Take the QSPI device out of memory mapped mode @@ -2788,7 +2788,7 @@ void stm32h7_qspi_enter_memorymapped(struct qspi_dev_s *dev, * ****************************************************************************/ -void stm32h7_qspi_exit_memorymapped(struct qspi_dev_s *dev) +void stm32_qspi_exit_memorymapped(struct qspi_dev_s *dev) { struct stm32h7_qspidev_s *priv = (struct stm32h7_qspidev_s *)dev; @@ -2802,4 +2802,4 @@ void stm32h7_qspi_exit_memorymapped(struct qspi_dev_s *dev) qspi_lock(dev, false); } -#endif /* CONFIG_STM32H7_QSPI */ +#endif /* CONFIG_STM32_QSPI */ diff --git a/arch/arm/src/stm32h7/stm32_qspi.h b/arch/arm/src/stm32h7/stm32_qspi.h index 93f03807023dd..5d7fc92ab8a5e 100644 --- a/arch/arm/src/stm32h7/stm32_qspi.h +++ b/arch/arm/src/stm32h7/stm32_qspi.h @@ -35,7 +35,7 @@ #include "chip.h" -#ifdef CONFIG_STM32H7_QUADSPI +#ifdef CONFIG_STM32_QSPI /**************************************************************************** * Pre-processor Definitions @@ -83,7 +83,7 @@ extern "C" ****************************************************************************/ struct qspi_dev_s; -struct qspi_dev_s *stm32h7_qspi_initialize(int intf); +struct qspi_dev_s *stm32_qspi_initialize(int intf); /**************************************************************************** * Name: stm32l4_qspi_enter_memorymapped @@ -101,7 +101,7 @@ struct qspi_dev_s *stm32h7_qspi_initialize(int intf); * ****************************************************************************/ -void stm32h7_qspi_enter_memorymapped(struct qspi_dev_s *dev, +void stm32_qspi_enter_memorymapped(struct qspi_dev_s *dev, const struct qspi_meminfo_s *meminfo, uint32_t lpto); @@ -119,7 +119,7 @@ void stm32h7_qspi_enter_memorymapped(struct qspi_dev_s *dev, * ****************************************************************************/ -void stm32h7_qspi_exit_memorymapped(struct qspi_dev_s *dev); +void stm32_qspi_exit_memorymapped(struct qspi_dev_s *dev); #undef EXTERN #if defined(__cplusplus) @@ -127,5 +127,5 @@ void stm32h7_qspi_exit_memorymapped(struct qspi_dev_s *dev); #endif #endif /* __ASSEMBLY__ */ -#endif /* CONFIG_STM32H7_QSPI */ +#endif /* CONFIG_STM32_QSPI */ #endif /* __ARCH_ARM_SRC_STM32H7_STM32_QSPI_H */ diff --git a/arch/arm/src/stm32h7/stm32_rcc.c b/arch/arm/src/stm32h7/stm32_rcc.c index 668be18c4dd26..dcb7abdbe985e 100644 --- a/arch/arm/src/stm32h7/stm32_rcc.c +++ b/arch/arm/src/stm32h7/stm32_rcc.c @@ -59,15 +59,15 @@ static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1, /* Include chip-specific clocking initialization logic */ -#if defined(CONFIG_STM32H7_STM32H7X0XX) +#if defined(CONFIG_STM32_STM32H7X0XX) # include "stm32h7x3xx_rcc.c" -#elif defined(CONFIG_STM32H7_STM32H7X3XX) +#elif defined(CONFIG_STM32_STM32H7X3XX) # include "stm32h7x3xx_rcc.c" -#elif defined(CONFIG_STM32H7_STM32H7B3XX) +#elif defined(CONFIG_STM32_STM32H7B3XX) # include "stm32h7x3xx_rcc.c" -#elif defined(CONFIG_STM32H7_STM32H7X5XX) +#elif defined(CONFIG_STM32_STM32H7X5XX) # include "stm32h7x3xx_rcc.c" -#elif defined(CONFIG_STM32H7_STM32H7X7XX) +#elif defined(CONFIG_STM32_STM32H7X7XX) # include "stm32h7x7xx_rcc.c" #else # error "Unsupported STM32 H7 chip" @@ -86,9 +86,9 @@ static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1, * and enable peripheral clocking for all peripherals enabled in the NuttX * configuration file. * - * If CONFIG_STM32H7_CUSTOM_CLOCKCONFIG is defined, then clocking will be - * enabled by an externally provided, board-specific function called - * stm32_board_clockconfig(). + * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then clocking + * will be enabled by an externally provided, board-specific function + * called stm32_board_clockconfig(). * * Input Parameters: * None @@ -100,19 +100,19 @@ static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1, void stm32_clockconfig(void) { -#ifndef CONFIG_STM32H7_BYPASS_CLOCKCONFIG +#ifndef CONFIG_STM32_BYPASS_CLOCKCONFIG /* Make sure that we are starting in the reset state */ rcc_reset(); -# if defined(CONFIG_STM32H7_PWR) +# if defined(CONFIG_STM32_PWR) /* Insure the bkp is initialized */ stm32_pwr_initbkp(false); # endif -# if defined(CONFIG_STM32H7_CUSTOM_CLOCKCONFIG) +# if defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) /* Invoke Board Custom Clock Configuration */ @@ -127,13 +127,13 @@ void stm32_clockconfig(void) stm32_stdclockconfig(); # endif -#endif /* !CONFIG_STM32H7_BYPASS_CLOCKCONFIG */ +#endif /* !CONFIG_STM32_BYPASS_CLOCKCONFIG */ /* Enable peripheral clocking */ rcc_enableperipherals(); -#ifdef CONFIG_STM32H7_SYSCFG_IOCOMPENSATION +#ifdef CONFIG_STM32_SYSCFG_IOCOMPENSATION /* Enable I/O Compensation */ stm32_iocompensation(); @@ -153,9 +153,9 @@ void stm32_clockconfig(void) * stm32_clockconfig(): It does not reset any devices, and it does not * reset the currently enabled peripheral clocks. * - * If CONFIG_STM32H7_CUSTOM_CLOCKCONFIG is defined, then clocking will be - * enabled by an externally provided, board-specific function called - * stm32_board_clockconfig(). + * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then clocking + * will be enabled by an externally provided, board-specific function + * called stm32_board_clockconfig(). * * Input Parameters: * None @@ -168,7 +168,7 @@ void stm32_clockconfig(void) #ifdef CONFIG_PM void stm32_clockenable(void) { -#if defined(CONFIG_STM32H7_CUSTOM_CLOCKCONFIG) +#if defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) /* Invoke Board Custom Clock Configuration */ diff --git a/arch/arm/src/stm32h7/stm32_rcc.h b/arch/arm/src/stm32h7/stm32_rcc.h index 786bb7064db3e..8dfaf0eb65400 100644 --- a/arch/arm/src/stm32h7/stm32_rcc.h +++ b/arch/arm/src/stm32h7/stm32_rcc.h @@ -124,9 +124,9 @@ static inline void stm32_mco2config(uint32_t source, uint32_t div) * and enable peripheral clocking for all peripherals enabled in the NuttX * configuration file. * - * If CONFIG_STM32H7_CUSTOM_CLOCKCONFIG is defined, then clocking will be - * enabled by an externally provided, board-specific function called - * stm32_board_clockconfig(). + * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then clocking + * will be enabled by an externally provided, board-specific function + * called stm32_board_clockconfig(). * * Input Parameters: * None @@ -157,7 +157,7 @@ void stm32_stdclockconfig(void); * ****************************************************************************/ -#ifdef CONFIG_STM32H7_CUSTOM_CLOCKCONFIG +#ifdef CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG void stm32_board_clockconfig(void); #endif @@ -174,9 +174,9 @@ void stm32_board_clockconfig(void); * stm32_clockconfig(): It does not reset any devices, and it does not * reset the currently enabled peripheral clocks. * - * If CONFIG_STM32H7_CUSTOM_CLOCKCONFIG is defined, then clocking will be - * enabled by an externally provided, board-specific function called - * stm32_board_clockconfig(). + * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then clocking + * will be enabled by an externally provided, board-specific function + * called stm32_board_clockconfig(). * * Input Parameters: * None diff --git a/arch/arm/src/stm32h7/stm32_rng.c b/arch/arm/src/stm32h7/stm32_rng.c index 0e6e67df1c5ae..df53d7f73436d 100644 --- a/arch/arm/src/stm32h7/stm32_rng.c +++ b/arch/arm/src/stm32h7/stm32_rng.c @@ -41,7 +41,7 @@ #include "hardware/stm32_rng.h" #include "arm_internal.h" -#if defined(CONFIG_STM32H7_RNG) +#if defined(CONFIG_STM32_RNG) #if defined(CONFIG_DEV_RANDOM) || defined(CONFIG_DEV_URANDOM_ARCH) /**************************************************************************** @@ -311,4 +311,4 @@ void devurandom_register(void) #endif #endif /* CONFIG_DEV_RANDOM || CONFIG_DEV_URANDOM_ARCH */ -#endif /* CONFIG_STM32H7_RNG */ +#endif /* CONFIG_STM32_RNG */ diff --git a/arch/arm/src/stm32h7/stm32_rptun.c b/arch/arm/src/stm32h7/stm32_rptun.c index 648af00143d79..c46354c4569e0 100644 --- a/arch/arm/src/stm32h7/stm32_rptun.c +++ b/arch/arm/src/stm32h7/stm32_rptun.c @@ -60,7 +60,7 @@ #define VRING_NR (8) /* Number of descriptors */ #define VRING_SIZE (512) /* Size of one descriptor */ -#ifdef CONFIG_STM32H7_SHMEM_SRAM3 +#ifdef CONFIG_STM32_SHMEM_SRAM3 /* Use 32kB of the SRAM3 as a shared memory */ # define VRING_SHMEM STM32_SRAM3_BASE diff --git a/arch/arm/src/stm32h7/stm32_rtc.c b/arch/arm/src/stm32h7/stm32_rtc.c index ed25043062d6e..4bfbe237a917e 100644 --- a/arch/arm/src/stm32h7/stm32_rtc.c +++ b/arch/arm/src/stm32h7/stm32_rtc.c @@ -44,7 +44,7 @@ #include -#ifdef CONFIG_STM32H7_RTC +#ifdef CONFIG_STM32_RTC /**************************************************************************** * Pre-processor Definitions @@ -65,17 +65,17 @@ # error "CONFIG_RTC_HIRES must NOT be set with this driver" #endif -#ifndef CONFIG_STM32H7_PWR -# error "CONFIG_STM32H7_PWR must selected to use this driver" +#ifndef CONFIG_STM32_PWR +# error "CONFIG_STM32_PWR must selected to use this driver" #endif /* Constants ****************************************************************/ -#if defined(CONFIG_STM32H7_RTC_HSECLOCK) +#if defined(CONFIG_STM32_RTC_HSECLOCK) # define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_HSE -#elif defined(CONFIG_STM32H7_RTC_LSICLOCK) +#elif defined(CONFIG_STM32_RTC_LSICLOCK) # define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_LSI -#elif defined(CONFIG_STM32H7_RTC_LSECLOCK) +#elif defined(CONFIG_STM32_RTC_LSECLOCK) # define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_LSE #else # warning "RCC_BDCR_RTCSEL_NOCLK has been selected - RTC will not count" @@ -491,7 +491,7 @@ static int rtc_setup(void) /* Configure RTC pre-scaler with the required values */ -#ifdef CONFIG_STM32H7_RTC_HSECLOCK +#ifdef CONFIG_STM32_RTC_HSECLOCK /* STMicro app note AN4759 suggests using 7999 and 124 to * get exactly 1MHz when using the RTC at 8MHz. */ @@ -940,17 +940,17 @@ int up_rtc_initialize(void) * external high rate clock */ -#ifdef CONFIG_STM32H7_RTC_HSECLOCK +#ifdef CONFIG_STM32_RTC_HSECLOCK /* Use the HSE clock as the input to the RTC block */ rtc_dumpregs("On reset HSE"); -#elif defined(CONFIG_STM32H7_RTC_LSICLOCK) +#elif defined(CONFIG_STM32_RTC_LSICLOCK) /* Use the LSI clock as the input to the RTC block */ rtc_dumpregs("On reset LSI"); -#elif defined(CONFIG_STM32H7_RTC_LSECLOCK) +#elif defined(CONFIG_STM32_RTC_LSECLOCK) /* Use the LSE clock as the input to the RTC block */ rtc_dumpregs("On reset LSE"); @@ -1102,7 +1102,7 @@ int up_rtc_initialize(void) * ****************************************************************************/ -#ifdef CONFIG_STM32H7_HAVE_RTC_SUBSECONDS +#ifdef CONFIG_STM32_HAVE_RTC_SUBSECONDS int stm32_rtc_getdatetime_with_subseconds(struct tm *tp, long *nsec) #else int up_rtc_getdatetime(struct tm *tp) @@ -1111,7 +1111,7 @@ int up_rtc_getdatetime(struct tm *tp) uint32_t dr; uint32_t tr; uint32_t tmp; -#ifdef CONFIG_STM32H7_HAVE_RTC_SUBSECONDS +#ifdef CONFIG_STM32_HAVE_RTC_SUBSECONDS uint32_t ssr; uint32_t prediv_s; uint32_t usecs; @@ -1129,7 +1129,7 @@ int up_rtc_getdatetime(struct tm *tp) { dr = getreg32(STM32_RTC_DR); tr = getreg32(STM32_RTC_TR); -#ifdef CONFIG_STM32H7_HAVE_RTC_SUBSECONDS +#ifdef CONFIG_STM32_HAVE_RTC_SUBSECONDS ssr = getreg32(STM32_RTC_SSR); tmp = getreg32(STM32_RTC_TR); if (tmp != tr) @@ -1186,7 +1186,7 @@ int up_rtc_getdatetime(struct tm *tp) clock_daysbeforemonth(tp->tm_mon, clock_isleapyear(tp->tm_year + 1900)); tp->tm_isdst = 0; -#ifdef CONFIG_STM32H7_HAVE_RTC_SUBSECONDS +#ifdef CONFIG_STM32_HAVE_RTC_SUBSECONDS /* Return RTC sub-seconds if a non-NULL value * of nsec has been provided to receive the sub-second value. */ @@ -1207,7 +1207,7 @@ int up_rtc_getdatetime(struct tm *tp) } rtc_dumptime((const struct tm *)tp, &usecs, "Returning"); -#else /* CONFIG_STM32H7_HAVE_RTC_SUBSECONDS */ +#else /* CONFIG_STM32_HAVE_RTC_SUBSECONDS */ rtc_dumptime((const struct tm *)tp, NULL, "Returning"); #endif @@ -1237,7 +1237,7 @@ int up_rtc_getdatetime(struct tm *tp) * ****************************************************************************/ -#ifdef CONFIG_STM32H7_HAVE_RTC_SUBSECONDS +#ifdef CONFIG_STM32_HAVE_RTC_SUBSECONDS int up_rtc_getdatetime(struct tm *tp) { return stm32_rtc_getdatetime_with_subseconds(tp, NULL); @@ -1270,8 +1270,8 @@ int up_rtc_getdatetime(struct tm *tp) ****************************************************************************/ #ifdef CONFIG_ARCH_HAVE_RTC_SUBSECONDS -# ifndef CONFIG_STM32H7_HAVE_RTC_SUBSECONDS -# error "Invalid config, enable CONFIG_STM32H7_HAVE_RTC_SUBSECONDS." +# ifndef CONFIG_STM32_HAVE_RTC_SUBSECONDS +# error "Invalid config, enable CONFIG_STM32_HAVE_RTC_SUBSECONDS." # endif int up_rtc_getdatetime_with_subseconds(struct tm *tp, long *nsec) { @@ -1775,11 +1775,11 @@ int stm32_rtc_setperiodic(const struct timespec *period, uint32_t secs; uint32_t millisecs; -#if defined(CONFIG_STM32H7_RTC_HSECLOCK) +#if defined(CONFIG_STM32_RTC_HSECLOCK) # error "Periodic wakeup not available for HSE" -#elif defined(CONFIG_STM32H7_RTC_LSICLOCK) +#elif defined(CONFIG_STM32_RTC_LSICLOCK) # error "Periodic wakeup not available for LSI (and it is too inaccurate!)" -#elif defined(CONFIG_STM32H7_RTC_LSECLOCK) +#elif defined(CONFIG_STM32_RTC_LSECLOCK) const uint32_t rtc_div16_max_msecs = 16 * 1000 * 0xffffu / STM32_LSE_FREQUENCY; #else @@ -1950,4 +1950,4 @@ int stm32_rtc_cancelperiodic(void) } #endif -#endif /* CONFIG_STM32H7_RTC */ +#endif /* CONFIG_STM32_RTC */ diff --git a/arch/arm/src/stm32h7/stm32_rtc.h b/arch/arm/src/stm32h7/stm32_rtc.h index e3b3f69096c21..82290558797f4 100644 --- a/arch/arm/src/stm32h7/stm32_rtc.h +++ b/arch/arm/src/stm32h7/stm32_rtc.h @@ -46,21 +46,21 @@ #define STM32_RTC_PRESCALER_SECOND 32767 /* Default prescaler to get a second base */ #define STM32_RTC_PRESCALER_MIN 1 /* Maximum speed of 16384 Hz */ -#if !defined(CONFIG_STM32H7_RTC_MAGIC) -# define CONFIG_STM32H7_RTC_MAGIC (0xfacefeed) +#if !defined(CONFIG_STM32_RTC_MAGIC) +# define CONFIG_STM32_RTC_MAGIC (0xfacefeed) #endif -#if !defined(CONFIG_STM32H7_RTC_MAGIC_TIME_SET) -# define CONFIG_STM32H7_RTC_MAGIC_TIME_SET (0xf00dface) +#if !defined(CONFIG_STM32_RTC_MAGIC_TIME_SET) +# define CONFIG_STM32_RTC_MAGIC_TIME_SET (0xf00dface) #endif -#if !defined(CONFIG_STM32H7_RTC_MAGIC_REG) -# define CONFIG_STM32H7_RTC_MAGIC_REG (0) +#if !defined(CONFIG_STM32_RTC_MAGIC_REG) +# define CONFIG_STM32_RTC_MAGIC_REG (0) #endif -#define RTC_MAGIC CONFIG_STM32H7_RTC_MAGIC -#define RTC_MAGIC_TIME_SET CONFIG_STM32H7_RTC_MAGIC_TIME_SET -#define RTC_MAGIC_REG STM32_RTC_BKR(CONFIG_STM32H7_RTC_MAGIC_REG) +#define RTC_MAGIC CONFIG_STM32_RTC_MAGIC +#define RTC_MAGIC_TIME_SET CONFIG_STM32_RTC_MAGIC_TIME_SET +#define RTC_MAGIC_REG STM32_RTC_BKR(CONFIG_STM32_RTC_MAGIC_REG) /**************************************************************************** * Public Types @@ -106,7 +106,7 @@ extern "C" * ****************************************************************************/ -#ifdef CONFIG_STM32H7_HAVE_RTC_SUBSECONDS +#ifdef CONFIG_STM32_HAVE_RTC_SUBSECONDS int stm32_rtc_getdatetime_with_subseconds(struct tm *tp, long *nsec); #endif diff --git a/arch/arm/src/stm32h7/stm32_sdmmc.c b/arch/arm/src/stm32h7/stm32_sdmmc.c index 414e6c5dbdda7..2aca3035cd277 100644 --- a/arch/arm/src/stm32h7/stm32_sdmmc.c +++ b/arch/arm/src/stm32h7/stm32_sdmmc.c @@ -56,7 +56,7 @@ #include "stm32_rcc.h" #include "stm32_sdmmc.h" -#if defined(CONFIG_STM32H7_SDMMC1) || defined(CONFIG_STM32H7_SDMMC2) +#if defined(CONFIG_STM32_SDMMC1) || defined(CONFIG_STM32_SDMMC2) /**************************************************************************** * Pre-processor Definitions @@ -101,14 +101,14 @@ * CONFIG_SDIO_MUXBUS - Setting this configuration enables some locking * APIs to manage concurrent accesses on the SDMMC bus. This is not * needed for the simple case of a single SD card, for example. - * CONFIG_STM32H7_SDMMC_IDMA - Enable SDMMC IDMA. + * CONFIG_STM32_SDMMC_IDMA - Enable SDMMC IDMA. * DMA support for SDMMC. If disabled, the SDMMC will work in * interrupt mode and still use the IDMA to a local buffer for data * lengths less the 32 bytes due to the FIFO limitations. * CONFIG_SDMMC1/2_WIDTH_D1_ONLY - This may be selected to force the driver * operate with only a single data line (the default is to use all * 4 SD data lines). - * CONFIG_STM32H7_SDMMC_XFRDEBUG - Enables some very low-level debug + * CONFIG_STM32_SDMMC_XFRDEBUG - Enables some very low-level debug * output This also requires CONFIG_DEBUG_FS and CONFIG_DEBUG_INFO * CONFIG_SDMMC1/2_SDIO_MODE * Build ins additional support needed only for SDIO cards (vs. SD memory @@ -125,19 +125,19 @@ * hence, if only SDMMC2 is defined it will be slot 0. */ -#if !defined(CONFIG_STM32H7_SDMMC1) +#if !defined(CONFIG_STM32_SDMMC1) # define SDMMC2_SLOT 0 #else # define SDMMC2_SLOT 1 #endif -#if !defined(CONFIG_STM32H7_SDMMC_IDMA) +#if !defined(CONFIG_STM32_SDMMC_IDMA) # warning "Large Non-DMA transfer may result in RX overrun failures" -#elif defined(CONFIG_STM32H7_SDMMC1) +#elif defined(CONFIG_STM32_SDMMC1) # define SRAM123_START STM32_SRAM123_BASE -# define SRAM123_END (SRAM123_START + STM32H7_SRAM123_SIZE) +# define SRAM123_END (SRAM123_START + STM32_SRAM123_SIZE) # define SRAM4_START STM32_SRAM4_BASE -# define SRAM4_END (SRAM4_START + STM32H7_SRAM4_SIZE) +# define SRAM4_END (SRAM4_START + STM32_SRAM4_SIZE) #endif #if !defined(CONFIG_SCHED_WORKQUEUE) || !defined(CONFIG_SCHED_HPWORK) @@ -150,7 +150,7 @@ #endif #if !defined(CONFIG_DEBUG_FS) || !defined(CONFIG_DEBUG_FEATURES) -# undef CONFIG_STM32H7_SDMMC_XFRDEBUG +# undef CONFIG_STM32_SDMMC_XFRDEBUG #endif #ifdef CONFIG_SDMMC1_SDIO_PULLUP @@ -316,7 +316,7 @@ /* Register logging support */ -#if defined(CONFIG_STM32H7_SDMMC_XFRDEBUG) +#if defined(CONFIG_STM32_SDMMC_XFRDEBUG) # define SAMPLENDX_BEFORE_SETUP 0 # define SAMPLENDX_AFTER_SETUP 1 # define SAMPLENDX_END_TRANSFER 2 @@ -381,7 +381,7 @@ struct stm32_dev_s uint32_t blocksize; /* Current block size */ uint32_t receivecnt; /* Real count to receive */ -#if !defined(CONFIG_STM32H7_SDMMC_IDMA) +#if !defined(CONFIG_STM32_SDMMC_IDMA) struct work_s cbfifo; /* Monitor for Lame FIFO */ #endif uint8_t rxfifo[FIFO_SIZE_IN_BYTES] /* To offload with IDMA and support un-alinged buffers */ @@ -389,7 +389,7 @@ struct stm32_dev_s bool unaligned_rx; /* read buffer is not cache-line or 32 bit aligned */ /* Input dma buffer for unaligned transfers */ -#if defined(CONFIG_STM32H7_SDMMC_IDMA) +#if defined(CONFIG_STM32_SDMMC_IDMA) uint8_t sdmmc_rxbuffer[SDMMC_MAX_BLOCK_SIZE] aligned_data(ARMV7M_DCACHE_LINESIZE); #endif @@ -397,7 +397,7 @@ struct stm32_dev_s /* Register logging support */ -#if defined(CONFIG_STM32H7_SDMMC_XFRDEBUG) +#if defined(CONFIG_STM32_SDMMC_XFRDEBUG) struct stm32_sdioregs_s { uint8_t power; @@ -434,7 +434,7 @@ static void stm32_setpwrctrl(struct stm32_dev_s *priv, uint32_t pwrctrl); /* Debug Helpers ************************************************************/ -#if defined(CONFIG_STM32H7_SDMMC_XFRDEBUG) +#if defined(CONFIG_STM32_SDMMC_XFRDEBUG) static void stm32_sampleinit(void); static void stm32_sdiosample(struct stm32_dev_s *priv, struct stm32_sdioregs_s *regs); @@ -456,7 +456,7 @@ static uint8_t stm32_log2(uint16_t value); static void stm32_dataconfig(struct stm32_dev_s *priv, uint32_t timeout, uint32_t dlen, bool receive); static void stm32_datadisable(struct stm32_dev_s *priv); -#ifndef CONFIG_STM32H7_SDMMC_IDMA +#ifndef CONFIG_STM32_SDMMC_IDMA static void stm32_sendfifo(struct stm32_dev_s *priv); static void stm32_recvfifo(struct stm32_dev_s *priv); #else @@ -499,7 +499,7 @@ static int stm32_sendcmd(struct sdio_dev_s *dev, uint32_t cmd, uint32_t arg); static void stm32_blocksetup(struct sdio_dev_s *dev, unsigned int blocksize, unsigned int nblocks); -#ifndef CONFIG_STM32H7_SDMMC_IDMA +#ifndef CONFIG_STM32_SDMMC_IDMA static int stm32_recvsetup(struct sdio_dev_s *dev, uint8_t *buffer, size_t nbytes); static int stm32_sendsetup(struct sdio_dev_s *dev, @@ -527,7 +527,7 @@ static int stm32_registercallback(struct sdio_dev_s *dev, /* DMA */ -#if defined(CONFIG_STM32H7_SDMMC_IDMA) +#if defined(CONFIG_STM32_SDMMC_IDMA) # if defined(CONFIG_ARCH_HAVE_SDIO_PREFLIGHT) static int stm32_dmapreflight(struct sdio_dev_s *dev, const uint8_t *buffer, size_t buflen); @@ -546,7 +546,7 @@ static void stm32_default(struct stm32_dev_s *priv); /**************************************************************************** * Private Data ****************************************************************************/ -#if defined(CONFIG_STM32H7_SDMMC1) +#if defined(CONFIG_STM32_SDMMC1) struct stm32_dev_s g_sdmmcdev1 = { .dev = @@ -562,7 +562,7 @@ struct stm32_dev_s g_sdmmcdev1 = .attach = stm32_attach, .sendcmd = stm32_sendcmd, .blocksetup = stm32_blocksetup, -#if defined(CONFIG_STM32H7_SDMMC_IDMA) +#if defined(CONFIG_STM32_SDMMC_IDMA) .recvsetup = stm32_dmarecvsetup, .sendsetup = stm32_dmasendsetup, #else @@ -582,7 +582,7 @@ struct stm32_dev_s g_sdmmcdev1 = .eventwait = stm32_eventwait, .callbackenable = stm32_callbackenable, .registercallback = stm32_registercallback, -#if defined(CONFIG_STM32H7_SDMMC_IDMA) +#if defined(CONFIG_STM32_SDMMC_IDMA) # if defined(CONFIG_ARCH_HAVE_SDIO_PREFLIGHT) .dmapreflight = stm32_dmapreflight, # endif @@ -601,7 +601,7 @@ struct stm32_dev_s g_sdmmcdev1 = #endif }; #endif -#if defined(CONFIG_STM32H7_SDMMC2) +#if defined(CONFIG_STM32_SDMMC2) struct stm32_dev_s g_sdmmcdev2 = { .dev = @@ -617,7 +617,7 @@ struct stm32_dev_s g_sdmmcdev2 = .attach = stm32_attach, .sendcmd = stm32_sendcmd, .blocksetup = stm32_blocksetup, -#if defined(CONFIG_STM32H7_SDMMC_IDMA) +#if defined(CONFIG_STM32_SDMMC_IDMA) .recvsetup = stm32_dmarecvsetup, .sendsetup = stm32_dmasendsetup, #else @@ -637,7 +637,7 @@ struct stm32_dev_s g_sdmmcdev2 = .eventwait = stm32_eventwait, .callbackenable = stm32_callbackenable, .registercallback = stm32_registercallback, -#if defined(CONFIG_STM32H7_SDMMC_IDMA) +#if defined(CONFIG_STM32_SDMMC_IDMA) # if defined(CONFIG_ARCH_HAVE_SDIO_PREFLIGHT) .dmapreflight = stm32_dmapreflight, # endif @@ -658,7 +658,7 @@ struct stm32_dev_s g_sdmmcdev2 = #endif /* Register logging support */ -#if defined(CONFIG_STM32H7_SDMMC_XFRDEBUG) +#if defined(CONFIG_STM32_SDMMC_XFRDEBUG) static struct stm32_sampleregs_s g_sampleregs[DEBUG_NSAMPLES]; #endif @@ -899,7 +899,7 @@ static void stm32_setpwrctrl(struct stm32_dev_s *priv, uint32_t pwrctrl) * ****************************************************************************/ -#if defined(CONFIG_STM32H7_SDMMC_XFRDEBUG) +#if defined(CONFIG_STM32_SDMMC_XFRDEBUG) static void stm32_sampleinit(void) { memset(g_sampleregs, 0xff, DEBUG_NSAMPLES * @@ -915,7 +915,7 @@ static void stm32_sampleinit(void) * ****************************************************************************/ -#if defined(CONFIG_STM32H7_SDMMC_XFRDEBUG) +#if defined(CONFIG_STM32_SDMMC_XFRDEBUG) static void stm32_sdiosample(struct stm32_dev_s *priv, struct stm32_sdioregs_s *regs) { @@ -938,7 +938,7 @@ static void stm32_sdiosample(struct stm32_dev_s *priv, * ****************************************************************************/ -#if defined(CONFIG_STM32H7_SDMMC_XFRDEBUG) +#if defined(CONFIG_STM32_SDMMC_XFRDEBUG) static void stm32_sample(struct stm32_dev_s *priv, int index) { struct stm32_sampleregs_s *regs = &g_sampleregs[index]; @@ -954,7 +954,7 @@ static void stm32_sample(struct stm32_dev_s *priv, int index) * ****************************************************************************/ -#if defined(CONFIG_STM32H7_SDMMC_XFRDEBUG) +#if defined(CONFIG_STM32_SDMMC_XFRDEBUG) static void stm32_sdiodump(struct stm32_sdioregs_s *regs, const char *msg) { mcinfo("SDIO Registers: %s\n", msg); @@ -985,7 +985,7 @@ static void stm32_sdiodump(struct stm32_sdioregs_s *regs, const char *msg) * ****************************************************************************/ -#if defined(CONFIG_STM32H7_SDMMC_XFRDEBUG) +#if defined(CONFIG_STM32_SDMMC_XFRDEBUG) static void stm32_dumpsample(struct stm32_dev_s *priv, struct stm32_sampleregs_s *regs, const char *msg) @@ -1002,7 +1002,7 @@ static void stm32_dumpsample(struct stm32_dev_s *priv, * ****************************************************************************/ -#if defined(CONFIG_STM32H7_SDMMC_XFRDEBUG) +#if defined(CONFIG_STM32_SDMMC_XFRDEBUG) static void stm32_dumpsamples(struct stm32_dev_s *priv) { stm32_dumpsample(priv, &g_sampleregs[SAMPLENDX_BEFORE_SETUP], @@ -1104,7 +1104,7 @@ static void stm32_dataconfig(struct stm32_dev_s *priv, uint32_t timeout, { DEBUGASSERT((dlen % priv->blocksize) == 0); -#if defined(CONFIG_STM32H7_SDMMC_IDMA) +#if defined(CONFIG_STM32_SDMMC_IDMA) /* If this is an unaligned receive, then receive one block at a * time to the internal buffer */ @@ -1202,7 +1202,7 @@ static void stm32_datadisable(struct stm32_dev_s *priv) * ****************************************************************************/ -#if !defined(CONFIG_STM32H7_SDMMC_IDMA) +#if !defined(CONFIG_STM32_SDMMC_IDMA) static void stm32_sendfifo(struct stm32_dev_s *priv) { union @@ -1267,7 +1267,7 @@ static void stm32_sendfifo(struct stm32_dev_s *priv) * ****************************************************************************/ -#if !defined(CONFIG_STM32H7_SDMMC_IDMA) +#if !defined(CONFIG_STM32_SDMMC_IDMA) static void stm32_recvfifo(struct stm32_dev_s *priv) { union @@ -1328,7 +1328,7 @@ static void stm32_recvfifo(struct stm32_dev_s *priv) * ****************************************************************************/ -#if defined (CONFIG_STM32H7_SDMMC_IDMA) +#if defined (CONFIG_STM32_SDMMC_IDMA) static void stm32_recvdma(struct stm32_dev_s *priv) { uint32_t dctrl; @@ -1547,7 +1547,7 @@ static void stm32_endtransfer(struct stm32_dev_s *priv, * ****************************************************************************/ -#if !defined(CONFIG_STM32H7_SDMMC_IDMA) +#if !defined(CONFIG_STM32_SDMMC_IDMA) static void stm32_sdmmc_fifo_monitor(void *arg) { struct stm32_dev_s *priv = (struct stm32_dev_s *)arg; @@ -1643,7 +1643,7 @@ static int stm32_sdmmc_interrupt(int irq, void *context, void *arg) pending = enabled & priv->xfrmask; if (pending != 0) { -#ifndef CONFIG_STM32H7_SDMMC_IDMA +#ifndef CONFIG_STM32_SDMMC_IDMA /* Is the RX FIFO half full or more? Is so then we must be * processing a receive transaction. */ @@ -1689,7 +1689,7 @@ static int stm32_sdmmc_interrupt(int irq, void *context, void *arg) * half-full interrupt will be received. */ -#ifndef CONFIG_STM32H7_SDMMC_IDMA +#ifndef CONFIG_STM32_SDMMC_IDMA /* If the transfer would not trigger fifo half full * we used IDMA to manage the lame fifo @@ -1909,7 +1909,7 @@ static void stm32_reset(struct sdio_dev_s *dev) flags = enter_critical_section(); -#if defined(CONFIG_STM32H7_SDMMC1) +#if defined(CONFIG_STM32_SDMMC1) if (priv->base == STM32_SDMMC1_BASE) { regaddress = STM32_RCC_AHB3RSTR; @@ -1917,7 +1917,7 @@ static void stm32_reset(struct sdio_dev_s *dev) } #endif -#if defined CONFIG_STM32H7_SDMMC2 +#if defined CONFIG_STM32_SDMMC2 if (priv->base == STM32_SDMMC2_BASE) { regaddress = STM32_RCC_AHB2RSTR; @@ -1998,7 +1998,7 @@ static sdio_capset_t stm32_capabilities(struct sdio_dev_s *dev) caps |= SDIO_CAPS_DMABEFOREWRITE; -#if defined(CONFIG_STM32H7_SDMMC_IDMA) +#if defined(CONFIG_STM32_SDMMC_IDMA) caps |= SDIO_CAPS_DMASUPPORTED; #endif @@ -2305,7 +2305,7 @@ static void stm32_blocksetup(struct sdio_dev_s *dev, * ****************************************************************************/ -#ifndef CONFIG_STM32H7_SDMMC_IDMA +#ifndef CONFIG_STM32_SDMMC_IDMA static int stm32_recvsetup(struct sdio_dev_s *dev, uint8_t *buffer, size_t nbytes) { @@ -2381,7 +2381,7 @@ static int stm32_recvsetup(struct sdio_dev_s *dev, uint8_t *buffer, * ****************************************************************************/ -#ifndef CONFIG_STM32H7_SDMMC_IDMA +#ifndef CONFIG_STM32_SDMMC_IDMA static int stm32_sendsetup(struct sdio_dev_s *dev, const uint8_t *buffer, size_t nbytes) { @@ -3065,7 +3065,7 @@ static int stm32_registercallback(struct sdio_dev_s *dev, * OK on success; a negated errno on failure ****************************************************************************/ -#if defined(CONFIG_STM32H7_SDMMC_IDMA) && defined(CONFIG_ARCH_HAVE_SDIO_PREFLIGHT) +#if defined(CONFIG_STM32_SDMMC_IDMA) && defined(CONFIG_ARCH_HAVE_SDIO_PREFLIGHT) static int stm32_dmapreflight(struct sdio_dev_s *dev, const uint8_t *buffer, size_t buflen) { @@ -3074,7 +3074,7 @@ static int stm32_dmapreflight(struct sdio_dev_s *dev, /* IDMA must be possible to the buffer */ -#if defined(CONFIG_STM32H7_SDMMC1) +#if defined(CONFIG_STM32_SDMMC1) if (priv->base == STM32_SDMMC1_BASE) { /* For SDMMC1, IDMA cannot access SRAM123 or SRAM4. */ @@ -3134,7 +3134,7 @@ static int stm32_dmapreflight(struct sdio_dev_s *dev, * ****************************************************************************/ -#if defined(CONFIG_STM32H7_SDMMC_IDMA) +#if defined(CONFIG_STM32_SDMMC_IDMA) static int stm32_dmarecvsetup(struct sdio_dev_s *dev, uint8_t *buffer, size_t buflen) { @@ -3239,7 +3239,7 @@ static int stm32_dmarecvsetup(struct sdio_dev_s *dev, * ****************************************************************************/ -#if defined(CONFIG_STM32H7_SDMMC_IDMA) +#if defined(CONFIG_STM32_SDMMC_IDMA) static int stm32_dmasendsetup(struct sdio_dev_s *dev, const uint8_t *buffer, size_t buflen) { @@ -3423,7 +3423,7 @@ struct sdio_dev_s *sdio_initialize(int slotno) { struct stm32_dev_s *priv = NULL; -#if defined(CONFIG_STM32H7_SDMMC1) +#if defined(CONFIG_STM32_SDMMC1) if (slotno == 0) { /* Select SDMMC 1 */ @@ -3456,7 +3456,7 @@ struct sdio_dev_s *sdio_initialize(int slotno) } else #endif -#if defined(CONFIG_STM32H7_SDMMC2) +#if defined(CONFIG_STM32_SDMMC2) if (slotno == SDMMC2_SLOT) { /* Select SDMMC 2 */ @@ -3629,4 +3629,4 @@ void sdio_set_sdio_card_isr(struct sdio_dev_s *dev, } #endif -#endif /* CONFIG_STM32H7_SDMMC1 || CONFIG_STM32H7_SDMMC2 */ +#endif /* CONFIG_STM32_SDMMC1 || CONFIG_STM32_SDMMC2 */ diff --git a/arch/arm/src/stm32h7/stm32_serial.c b/arch/arm/src/stm32h7/stm32_serial.c index 7860667a24507..cf668117e809e 100644 --- a/arch/arm/src/stm32h7/stm32_serial.c +++ b/arch/arm/src/stm32h7/stm32_serial.c @@ -65,7 +65,7 @@ /* Total number of possible serial devices */ -#define STM32_NSERIAL (STM32H7_NUSART + STM32H7_NUART) +#define STM32_NSERIAL (STM32_NUSART + STM32_NUART) /* DMA configuration */ @@ -81,11 +81,11 @@ # if !defined(DMAMAP_USART1_RX) # error "USART1 DMA map not defined (DMAMAP_USART1_RX)" # endif -# if DMAMAP_USART1_RX == DMAMAP_DMA12_USART1RX_0 && !defined(CONFIG_STM32H7_DMA1) -# error STM32 USART1 using DMAMAP_DMA12_USART1RX_0 for receive DMA requires CONFIG_STM32H7_DMA1 +# if DMAMAP_USART1_RX == DMAMAP_DMA12_USART1RX_0 && !defined(CONFIG_STM32_DMA1) +# error STM32 USART1 using DMAMAP_DMA12_USART1RX_0 for receive DMA requires CONFIG_STM32_DMA1 # endif -# if DMAMAP_USART1_RX == DMAMAP_DMA12_USART1RX_1 && !defined(CONFIG_STM32H7_DMA2) -# error STM32 USART1 using DMAMAP_DMA12_USART1RX_1 for receive DMA requires CONFIG_STM32H7_DMA2 +# if DMAMAP_USART1_RX == DMAMAP_DMA12_USART1RX_1 && !defined(CONFIG_STM32_DMA2) +# error STM32 USART1 using DMAMAP_DMA12_USART1RX_1 for receive DMA requires CONFIG_STM32_DMA2 # endif # endif @@ -93,11 +93,11 @@ # if !defined(DMAMAP_USART2_RX) # error "USART2 DMA map not defined (DMAMAP_USART2_RX)" # endif -# if DMAMAP_USART2_RX == DMAMAP_DMA12_USART2RX_0 && !defined(CONFIG_STM32H7_DMA1) -# error STM32 USART2 using DMAMAP_DMA12_USART2RX_0 for receive DMA requires CONFIG_STM32H7_DMA1 +# if DMAMAP_USART2_RX == DMAMAP_DMA12_USART2RX_0 && !defined(CONFIG_STM32_DMA1) +# error STM32 USART2 using DMAMAP_DMA12_USART2RX_0 for receive DMA requires CONFIG_STM32_DMA1 # endif -# if DMAMAP_USART2_RX == DMAMAP_DMA12_USART2RX_1 && !defined(CONFIG_STM32H7_DMA2) -# error STM32 USART2 using DMAMAP_DMA12_USART2RX_1 for receive DMA requires CONFIG_STM32H7_DMA2 +# if DMAMAP_USART2_RX == DMAMAP_DMA12_USART2RX_1 && !defined(CONFIG_STM32_DMA2) +# error STM32 USART2 using DMAMAP_DMA12_USART2RX_1 for receive DMA requires CONFIG_STM32_DMA2 # endif # endif @@ -105,11 +105,11 @@ # if !defined(DMAMAP_USART3_RX) # error "USART3 DMA map not defined (DMAMAP_USART3_RX)" # endif -# if DMAMAP_USART3_RX == DMAMAP_DMA12_USART3RX_0 && !defined(CONFIG_STM32H7_DMA1) -# error STM32 USART3 using DMAMAP_DMA12_USART3RX_0 for receive DMA requires CONFIG_STM32H7_DMA1 +# if DMAMAP_USART3_RX == DMAMAP_DMA12_USART3RX_0 && !defined(CONFIG_STM32_DMA1) +# error STM32 USART3 using DMAMAP_DMA12_USART3RX_0 for receive DMA requires CONFIG_STM32_DMA1 # endif -# if DMAMAP_USART3_RX == DMAMAP_DMA12_USART3RX_1 && !defined(CONFIG_STM32H7_DMA2) -# error STM32 USART3 using DMAMAP_DMA12_USART3RX_1 for receive DMA requires CONFIG_STM32H7_DMA2 +# if DMAMAP_USART3_RX == DMAMAP_DMA12_USART3RX_1 && !defined(CONFIG_STM32_DMA2) +# error STM32 USART3 using DMAMAP_DMA12_USART3RX_1 for receive DMA requires CONFIG_STM32_DMA2 # endif # endif @@ -117,11 +117,11 @@ # if !defined(DMAMAP_UART4_RX) # error "UART4 DMA map not defined (DMAMAP_UART4_RX)" # endif -# if DMAMAP_UART4_RX == DMAMAP_DMA12_UART4RX_0 && !defined(CONFIG_STM32H7_DMA1) -# error STM32 UART4 using DMAMAP_DMA12_UART4RX_0 for receive DMA requires CONFIG_STM32H7_DMA1 +# if DMAMAP_UART4_RX == DMAMAP_DMA12_UART4RX_0 && !defined(CONFIG_STM32_DMA1) +# error STM32 UART4 using DMAMAP_DMA12_UART4RX_0 for receive DMA requires CONFIG_STM32_DMA1 # endif -# if DMAMAP_UART4_RX == DMAMAP_DMA12_UART4RX_1 && !defined(CONFIG_STM32H7_DMA2) -# error STM32 UART4 using DMAMAP_DMA12_UART4RX_1 for receive DMA requires CONFIG_STM32H7_DMA2 +# if DMAMAP_UART4_RX == DMAMAP_DMA12_UART4RX_1 && !defined(CONFIG_STM32_DMA2) +# error STM32 UART4 using DMAMAP_DMA12_UART4RX_1 for receive DMA requires CONFIG_STM32_DMA2 # endif # endif @@ -129,11 +129,11 @@ # if !defined(DMAMAP_UART5_RX) # error "UART5 DMA map not defined (DMAMAP_UART5_RX)" # endif -# if DMAMAP_UART5_RX == DMAMAP_DMA12_UART5RX_0 && !defined(CONFIG_STM32H7_DMA1) -# error STM32 UART5 using DMAMAP_DMA12_UART5RX_0 for receive DMA requires CONFIG_STM32H7_DMA1 +# if DMAMAP_UART5_RX == DMAMAP_DMA12_UART5RX_0 && !defined(CONFIG_STM32_DMA1) +# error STM32 UART5 using DMAMAP_DMA12_UART5RX_0 for receive DMA requires CONFIG_STM32_DMA1 # endif -# if DMAMAP_UART5_RX == DMAMAP_DMA12_UART5RX_1 && !defined(CONFIG_STM32H7_DMA2) -# error STM32 UART5 using DMAMAP_DMA12_UART5RX_1 for receive DMA requires CONFIG_STM32H7_DMA2 +# if DMAMAP_UART5_RX == DMAMAP_DMA12_UART5RX_1 && !defined(CONFIG_STM32_DMA2) +# error STM32 UART5 using DMAMAP_DMA12_UART5RX_1 for receive DMA requires CONFIG_STM32_DMA2 # endif # endif @@ -141,11 +141,11 @@ # if !defined(DMAMAP_USART6_RX) # error "USART6 DMA map not defined (DMAMAP_USART6_RX)" # endif -# if DMAMAP_USART6_RX == DMAMAP_DMA12_USART6RX_0 && !defined(CONFIG_STM32H7_DMA1) -# error STM32 USART6 using DMAMAP_DMA12_USART6RX_0 for receive DMA requires CONFIG_STM32H7_DMA1 +# if DMAMAP_USART6_RX == DMAMAP_DMA12_USART6RX_0 && !defined(CONFIG_STM32_DMA1) +# error STM32 USART6 using DMAMAP_DMA12_USART6RX_0 for receive DMA requires CONFIG_STM32_DMA1 # endif -# if DMAMAP_USART6_RX == DMAMAP_DMA12_USART6RX_1 && !defined(CONFIG_STM32H7_DMA2) -# error STM32 USART6 using DMAMAP_DMA12_USART6RX_1 for receive DMA requires CONFIG_STM32H7_DMA2 +# if DMAMAP_USART6_RX == DMAMAP_DMA12_USART6RX_1 && !defined(CONFIG_STM32_DMA2) +# error STM32 USART6 using DMAMAP_DMA12_USART6RX_1 for receive DMA requires CONFIG_STM32_DMA2 # endif # endif @@ -153,11 +153,11 @@ # if !defined(DMAMAP_UART7_RX) # error "UART7 DMA map not defined (DMAMAP_UART7_RX)" # endif -# if DMAMAP_UART7_RX == DMAMAP_DMA12_UART7RX_0 && !defined(CONFIG_STM32H7_DMA1) -# error STM32 UART7 using DMAMAP_DMA12_UART7RX_0 for receive DMA requires CONFIG_STM32H7_DMA1 +# if DMAMAP_UART7_RX == DMAMAP_DMA12_UART7RX_0 && !defined(CONFIG_STM32_DMA1) +# error STM32 UART7 using DMAMAP_DMA12_UART7RX_0 for receive DMA requires CONFIG_STM32_DMA1 # endif -# if DMAMAP_UART7_RX == DMAMAP_DMA12_UART7RX_1 && !defined(CONFIG_STM32H7_DMA2) -# error STM32 UART7 using DMAMAP_DMA12_UART7RX_1 for receive DMA requires CONFIG_STM32H7_DMA2 +# if DMAMAP_UART7_RX == DMAMAP_DMA12_UART7RX_1 && !defined(CONFIG_STM32_DMA2) +# error STM32 UART7 using DMAMAP_DMA12_UART7RX_1 for receive DMA requires CONFIG_STM32_DMA2 # endif # endif @@ -165,11 +165,11 @@ # if !defined(DMAMAP_UART8_RX) # error "UART8 DMA map not defined (DMAMAP_UART8_RX)" # endif -# if DMAMAP_UART8_RX == DMAMAP_DMA12_UART8RX_0 && !defined(CONFIG_STM32H7_DMA1) -# error STM32 UART8 using DMAMAP_DMA12_UART8RX_0 for receive DMA requires CONFIG_STM32H7_DMA1 +# if DMAMAP_UART8_RX == DMAMAP_DMA12_UART8RX_0 && !defined(CONFIG_STM32_DMA1) +# error STM32 UART8 using DMAMAP_DMA12_UART8RX_0 for receive DMA requires CONFIG_STM32_DMA1 # endif -# if DMAMAP_UART8_RX == DMAMAP_DMA12_UART8RX_1 && !defined(CONFIG_STM32H7_DMA2) -# error STM32 UART8 using DMAMAP_DMA12_UART8RX_1 for receive DMA requires CONFIG_STM32H7_DMA2 +# if DMAMAP_UART8_RX == DMAMAP_DMA12_UART8RX_1 && !defined(CONFIG_STM32_DMA2) +# error STM32 UART8 using DMAMAP_DMA12_UART8RX_1 for receive DMA requires CONFIG_STM32_DMA2 # endif # endif @@ -205,14 +205,14 @@ # define ARMV7M_DCACHE_LINESIZE 32 # endif -# if !defined(CONFIG_STM32H7_SERIAL_RXDMA_BUFFER_SIZE) || \ - (CONFIG_STM32H7_SERIAL_RXDMA_BUFFER_SIZE < ARMV7M_DCACHE_LINESIZE) -# undef CONFIG_STM32H7_SERIAL_RXDMA_BUFFER_SIZE -# define CONFIG_STM32H7_SERIAL_RXDMA_BUFFER_SIZE ARMV7M_DCACHE_LINESIZE +# if !defined(CONFIG_STM32_SERIAL_RXDMA_BUFFER_SIZE) || \ + (CONFIG_STM32_SERIAL_RXDMA_BUFFER_SIZE < ARMV7M_DCACHE_LINESIZE) +# undef CONFIG_STM32_SERIAL_RXDMA_BUFFER_SIZE +# define CONFIG_STM32_SERIAL_RXDMA_BUFFER_SIZE ARMV7M_DCACHE_LINESIZE # endif # define RXDMA_BUFFER_MASK (ARMV7M_DCACHE_LINESIZE - 1) -# define RXDMA_BUFFER_SIZE ((CONFIG_STM32H7_SERIAL_RXDMA_BUFFER_SIZE \ +# define RXDMA_BUFFER_SIZE ((CONFIG_STM32_SERIAL_RXDMA_BUFFER_SIZE \ + RXDMA_BUFFER_MASK) & ~RXDMA_BUFFER_MASK) /* DMA priority */ @@ -247,11 +247,11 @@ # if !defined(DMAMAP_USART1_TX) # error "USART1 DMA map not defined (DMAMAP_USART1_TX)" # endif -# if DMAMAP_USART1_TX == DMAMAP_DMA12_USART1TX_0 && !defined(CONFIG_STM32H7_DMA1) -# error STM32 USART1 using DMAMAP_DMA12_USART1TX_0 for transmit DMA requires CONFIG_STM32H7_DMA1 +# if DMAMAP_USART1_TX == DMAMAP_DMA12_USART1TX_0 && !defined(CONFIG_STM32_DMA1) +# error STM32 USART1 using DMAMAP_DMA12_USART1TX_0 for transmit DMA requires CONFIG_STM32_DMA1 # endif -# if DMAMAP_USART1_TX == DMAMAP_DMA12_USART1TX_1 && !defined(CONFIG_STM32H7_DMA2) -# error STM32 USART1 using DMAMAP_DMA12_USART1TX_1 for transmit DMA requires CONFIG_STM32H7_DMA2 +# if DMAMAP_USART1_TX == DMAMAP_DMA12_USART1TX_1 && !defined(CONFIG_STM32_DMA2) +# error STM32 USART1 using DMAMAP_DMA12_USART1TX_1 for transmit DMA requires CONFIG_STM32_DMA2 # endif # endif @@ -259,11 +259,11 @@ # if !defined(DMAMAP_USART2_TX) # error "USART2 DMA map not defined (DMAMAP_USART2_TX)" # endif -# if DMAMAP_USART2_TX == DMAMAP_DMA12_USART2TX_0 && !defined(CONFIG_STM32H7_DMA1) -# error STM32 USART2 using DMAMAP_DMA12_USART2TX_0 for transmit DMA requires CONFIG_STM32H7_DMA1 +# if DMAMAP_USART2_TX == DMAMAP_DMA12_USART2TX_0 && !defined(CONFIG_STM32_DMA1) +# error STM32 USART2 using DMAMAP_DMA12_USART2TX_0 for transmit DMA requires CONFIG_STM32_DMA1 # endif -# if DMAMAP_USART2_TX == DMAMAP_DMA12_USART2TX_1 && !defined(CONFIG_STM32H7_DMA2) -# error STM32 USART2 using DMAMAP_DMA12_USART2TX_1 for transmit DMA requires CONFIG_STM32H7_DMA2 +# if DMAMAP_USART2_TX == DMAMAP_DMA12_USART2TX_1 && !defined(CONFIG_STM32_DMA2) +# error STM32 USART2 using DMAMAP_DMA12_USART2TX_1 for transmit DMA requires CONFIG_STM32_DMA2 # endif # endif @@ -271,11 +271,11 @@ # if !defined(DMAMAP_USART3_TX) # error "USART3 DMA map not defined (DMAMAP_USART3_TX)" # endif -# if DMAMAP_USART3_TX == DMAMAP_DMA12_USART3TX_0 && !defined(CONFIG_STM32H7_DMA1) -# error STM32 USART3 using DMAMAP_DMA12_USART3TX_0 for transmit DMA requires CONFIG_STM32H7_DMA1 +# if DMAMAP_USART3_TX == DMAMAP_DMA12_USART3TX_0 && !defined(CONFIG_STM32_DMA1) +# error STM32 USART3 using DMAMAP_DMA12_USART3TX_0 for transmit DMA requires CONFIG_STM32_DMA1 # endif -# if DMAMAP_USART3_TX == DMAMAP_DMA12_USART3TX_1 && !defined(CONFIG_STM32H7_DMA2) -# error STM32 USART3 using DMAMAP_DMA12_USART3TX_1 for transmit DMA requires CONFIG_STM32H7_DMA2 +# if DMAMAP_USART3_TX == DMAMAP_DMA12_USART3TX_1 && !defined(CONFIG_STM32_DMA2) +# error STM32 USART3 using DMAMAP_DMA12_USART3TX_1 for transmit DMA requires CONFIG_STM32_DMA2 # endif # endif @@ -283,11 +283,11 @@ # if !defined(DMAMAP_UART4_TX) # error "UART4 DMA map not defined (DMAMAP_UART4_TX)" # endif -# if DMAMAP_UART4_TX == DMAMAP_DMA12_UART4TX_0 && !defined(CONFIG_STM32H7_DMA1) -# error STM32 UART4 using DMAMAP_DMA12_UART4TX_0 for transmit DMA requires CONFIG_STM32H7_DMA1 +# if DMAMAP_UART4_TX == DMAMAP_DMA12_UART4TX_0 && !defined(CONFIG_STM32_DMA1) +# error STM32 UART4 using DMAMAP_DMA12_UART4TX_0 for transmit DMA requires CONFIG_STM32_DMA1 # endif -# if DMAMAP_UART4_TX == DMAMAP_DMA12_UART4TX_1 && !defined(CONFIG_STM32H7_DMA2) -# error STM32 UART4 using DMAMAP_DMA12_UART4TX_1 for transmit DMA requires CONFIG_STM32H7_DMA2 +# if DMAMAP_UART4_TX == DMAMAP_DMA12_UART4TX_1 && !defined(CONFIG_STM32_DMA2) +# error STM32 UART4 using DMAMAP_DMA12_UART4TX_1 for transmit DMA requires CONFIG_STM32_DMA2 # endif # endif @@ -295,11 +295,11 @@ # if !defined(DMAMAP_UART5_TX) # error "UART5 DMA map not defined (DMAMAP_UART5_TX)" # endif -# if DMAMAP_UART5_TX == DMAMAP_DMA12_UART5TX_0 && !defined(CONFIG_STM32H7_DMA1) -# error STM32 UART5 using DMAMAP_DMA12_UART5TX_0 for transmit DMA requires CONFIG_STM32H7_DMA1 +# if DMAMAP_UART5_TX == DMAMAP_DMA12_UART5TX_0 && !defined(CONFIG_STM32_DMA1) +# error STM32 UART5 using DMAMAP_DMA12_UART5TX_0 for transmit DMA requires CONFIG_STM32_DMA1 # endif -# if DMAMAP_UART5_TX == DMAMAP_DMA12_UART5TX_1 && !defined(CONFIG_STM32H7_DMA2) -# error STM32 UART5 using DMAMAP_DMA12_UART5TX_1 for transmit DMA requires CONFIG_STM32H7_DMA2 +# if DMAMAP_UART5_TX == DMAMAP_DMA12_UART5TX_1 && !defined(CONFIG_STM32_DMA2) +# error STM32 UART5 using DMAMAP_DMA12_UART5TX_1 for transmit DMA requires CONFIG_STM32_DMA2 # endif # endif @@ -307,11 +307,11 @@ # if !defined(DMAMAP_USART6_TX) # error "USART6 DMA map not defined (DMAMAP_USART6_TX)" # endif -# if DMAMAP_USART6_TX == DMAMAP_DMA12_USART6TX_0 && !defined(CONFIG_STM32H7_DMA1) -# error STM32 USART6 using DMAMAP_DMA12_USART6TX_0 for transmit DMA requires CONFIG_STM32H7_DMA1 +# if DMAMAP_USART6_TX == DMAMAP_DMA12_USART6TX_0 && !defined(CONFIG_STM32_DMA1) +# error STM32 USART6 using DMAMAP_DMA12_USART6TX_0 for transmit DMA requires CONFIG_STM32_DMA1 # endif -# if DMAMAP_USART6_TX == DMAMAP_DMA12_USART6TX_1 && !defined(CONFIG_STM32H7_DMA2) -# error STM32 USART6 using DMAMAP_DMA12_USART6TX_1 for transmit DMA requires CONFIG_STM32H7_DMA2 +# if DMAMAP_USART6_TX == DMAMAP_DMA12_USART6TX_1 && !defined(CONFIG_STM32_DMA2) +# error STM32 USART6 using DMAMAP_DMA12_USART6TX_1 for transmit DMA requires CONFIG_STM32_DMA2 # endif # endif @@ -319,11 +319,11 @@ # if !defined(DMAMAP_UART7_TX) # error "UART7 DMA map not defined (DMAMAP_UART7_TX)" # endif -# if DMAMAP_UART7_TX == DMAMAP_DMA12_UART7TX_0 && !defined(CONFIG_STM32H7_DMA1) -# error STM32 UART7 using DMAMAP_DMA12_UART7TX_0 for transmit DMA requires CONFIG_STM32H7_DMA1 +# if DMAMAP_UART7_TX == DMAMAP_DMA12_UART7TX_0 && !defined(CONFIG_STM32_DMA1) +# error STM32 UART7 using DMAMAP_DMA12_UART7TX_0 for transmit DMA requires CONFIG_STM32_DMA1 # endif -# if DMAMAP_UART7_TX == DMAMAP_DMA12_UART7TX_1 && !defined(CONFIG_STM32H7_DMA2) -# error STM32 UART7 using DMAMAP_DMA12_UART7TX_1 for transmit DMA requires CONFIG_STM32H7_DMA2 +# if DMAMAP_UART7_TX == DMAMAP_DMA12_UART7TX_1 && !defined(CONFIG_STM32_DMA2) +# error STM32 UART7 using DMAMAP_DMA12_UART7TX_1 for transmit DMA requires CONFIG_STM32_DMA2 # endif # endif @@ -331,11 +331,11 @@ # if !defined(DMAMAP_UART8_TX) # error "UART8 DMA map not defined (DMAMAP_UART8_TX)" # endif -# if DMAMAP_UART8_TX == DMAMAP_DMA12_UART8TX_0 && !defined(CONFIG_STM32H7_DMA1) -# error STM32 UART8 using DMAMAP_DMA12_UART8TX_0 for transmit DMA requires CONFIG_STM32H7_DMA1 +# if DMAMAP_UART8_TX == DMAMAP_DMA12_UART8TX_0 && !defined(CONFIG_STM32_DMA1) +# error STM32 UART8 using DMAMAP_DMA12_UART8TX_0 for transmit DMA requires CONFIG_STM32_DMA1 # endif -# if DMAMAP_UART8_TX == DMAMAP_DMA12_UART8TX_1 && !defined(CONFIG_STM32H7_DMA2) -# error STM32 UART8 using DMAMAP_DMA12_UART8TX_1 for transmit DMA requires CONFIG_STM32H7_DMA2 +# if DMAMAP_UART8_TX == DMAMAP_DMA12_UART8TX_1 && !defined(CONFIG_STM32_DMA2) +# error STM32 UART8 using DMAMAP_DMA12_UART8TX_1 for transmit DMA requires CONFIG_STM32_DMA2 # endif # endif #endif @@ -371,7 +371,7 @@ #endif #define TXDMA_BUFFER_MASK (ARMV7M_DCACHE_LINESIZE - 1) -#define TXDMA_BUFFER_SIZE ((CONFIG_STM32H7_SERIAL_RXDMA_BUFFER_SIZE \ +#define TXDMA_BUFFER_SIZE ((CONFIG_STM32_SERIAL_RXDMA_BUFFER_SIZE \ + RXDMA_BUFFER_MASK) & ~RXDMA_BUFFER_MASK) /* If built with CONFIG_ARMV7M_DCACHE Buffers need to be aligned and @@ -475,8 +475,8 @@ /* Power management definitions */ -#if defined(CONFIG_PM) && !defined(CONFIG_STM32H7_PM_SERIAL_ACTIVITY) -# define CONFIG_STM32H7_PM_SERIAL_ACTIVITY 10 +#if defined(CONFIG_PM) && !defined(CONFIG_STM32_PM_SERIAL_ACTIVITY) +# define CONFIG_STM32_PM_SERIAL_ACTIVITY 10 #endif #if defined(CONFIG_PM) # warning stm32h7 serial power managemnt was taken from stm32f7 and is untested! @@ -501,7 +501,7 @@ * See up_restoreusartint where the masking is done. */ -#ifdef CONFIG_STM32H7_SERIALBRK_BSDCOMPAT +#ifdef CONFIG_STM32_SERIALBRK_BSDCOMPAT # define USART_CR1_IE_BREAK_INPROGRESS_SHFTS 15 # define USART_CR1_IE_BREAK_INPROGRESS (1 << USART_CR1_IE_BREAK_INPROGRESS_SHFTS) #endif @@ -511,13 +511,13 @@ /* Warnings for potentially unsafe configuration combinations. */ -#if defined(CONFIG_STM32H7_FLOWCONTROL_BROKEN) && \ +#if defined(CONFIG_STM32_FLOWCONTROL_BROKEN) && \ !defined(CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS) -# error "CONFIG_STM32H7_FLOWCONTROL_BROKEN requires \ +# error "CONFIG_STM32_FLOWCONTROL_BROKEN requires \ CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS to be enabled." #endif -#ifndef CONFIG_STM32H7_FLOWCONTROL_BROKEN +#ifndef CONFIG_STM32_FLOWCONTROL_BROKEN /* Combination of RXDMA + IFLOWCONTROL does not work as one might expect. * Since RXDMA uses circular DMA-buffer, DMA will always keep reading new * data from USART peripheral even if DMA buffer underruns. Thus this @@ -560,7 +560,7 @@ # warning "RXDMA and IFLOWCONTROL both enabled for UART8. \ This combination can lead to data loss." # endif -#endif /* CONFIG_STM32H7_FLOWCONTROL_BROKEN */ +#endif /* CONFIG_STM32_FLOWCONTROL_BROKEN */ /**************************************************************************** * Private Types @@ -868,49 +868,49 @@ static char g_uart8rxfifo[RXDMA_BUFFER_SIZE] /* Receive/Transmit buffers */ -#ifdef CONFIG_STM32H7_USART1 +#ifdef CONFIG_STM32_USART1 static char g_usart1rxbuffer[CONFIG_USART1_RXBUFSIZE]; static char g_usart1txbuffer[USART1_TXBUFSIZE_ADJUSTED] \ USART1_TXBUFSIZE_ALGN; #endif -#ifdef CONFIG_STM32H7_USART2 +#ifdef CONFIG_STM32_USART2 static char g_usart2rxbuffer[CONFIG_USART2_RXBUFSIZE]; static char g_usart2txbuffer[USART2_TXBUFSIZE_ADJUSTED] \ USART2_TXBUFSIZE_ALGN; #endif -#ifdef CONFIG_STM32H7_USART3 +#ifdef CONFIG_STM32_USART3 static char g_usart3rxbuffer[CONFIG_USART3_RXBUFSIZE]; static char g_usart3txbuffer[USART3_TXBUFSIZE_ADJUSTED] \ USART3_TXBUFSIZE_ALGN; #endif -#ifdef CONFIG_STM32H7_UART4 +#ifdef CONFIG_STM32_UART4 static char g_uart4rxbuffer[CONFIG_UART4_RXBUFSIZE]; static char g_uart4txbuffer[UART4_TXBUFSIZE_ADJUSTED] \ UART4_TXBUFSIZE_ALGN; #endif -#ifdef CONFIG_STM32H7_UART5 +#ifdef CONFIG_STM32_UART5 static char g_uart5rxbuffer[CONFIG_UART5_RXBUFSIZE]; static char g_uart5txbuffer[UART5_TXBUFSIZE_ADJUSTED] \ UART5_TXBUFSIZE_ALGN; #endif -#ifdef CONFIG_STM32H7_USART6 +#ifdef CONFIG_STM32_USART6 static char g_usart6rxbuffer[CONFIG_USART6_RXBUFSIZE]; static char g_usart6txbuffer[USART6_TXBUFSIZE_ADJUSTED] \ USART6_TXBUFSIZE_ALGN; #endif -#ifdef CONFIG_STM32H7_UART7 +#ifdef CONFIG_STM32_UART7 static char g_uart7rxbuffer[CONFIG_UART7_RXBUFSIZE]; static char g_uart7txbuffer[UART7_TXBUFSIZE_ADJUSTED] \ UART7_TXBUFSIZE_ALGN; #endif -#ifdef CONFIG_STM32H7_UART8 +#ifdef CONFIG_STM32_UART8 static char g_uart8rxbuffer[CONFIG_UART8_RXBUFSIZE]; static char g_uart8txbuffer[UART8_TXBUFSIZE_ADJUSTED] \ UART8_TXBUFSIZE_ALGN; @@ -918,7 +918,7 @@ static char g_uart8txbuffer[UART8_TXBUFSIZE_ADJUSTED] \ /* This describes the state of the STM32 USART1 ports. */ -#ifdef CONFIG_STM32H7_USART1 +#ifdef CONFIG_STM32_USART1 static struct up_dev_s g_usart1priv = { .dev = @@ -988,7 +988,7 @@ static struct up_dev_s g_usart1priv = /* This describes the state of the STM32 USART2 port. */ -#ifdef CONFIG_STM32H7_USART2 +#ifdef CONFIG_STM32_USART2 static struct up_dev_s g_usart2priv = { .dev = @@ -1058,7 +1058,7 @@ static struct up_dev_s g_usart2priv = /* This describes the state of the STM32 USART3 port. */ -#ifdef CONFIG_STM32H7_USART3 +#ifdef CONFIG_STM32_USART3 static struct up_dev_s g_usart3priv = { .dev = @@ -1128,7 +1128,7 @@ static struct up_dev_s g_usart3priv = /* This describes the state of the STM32 UART4 port. */ -#ifdef CONFIG_STM32H7_UART4 +#ifdef CONFIG_STM32_UART4 static struct up_dev_s g_uart4priv = { .dev = @@ -1198,7 +1198,7 @@ static struct up_dev_s g_uart4priv = /* This describes the state of the STM32 UART5 port. */ -#ifdef CONFIG_STM32H7_UART5 +#ifdef CONFIG_STM32_UART5 static struct up_dev_s g_uart5priv = { .dev = @@ -1268,7 +1268,7 @@ static struct up_dev_s g_uart5priv = /* This describes the state of the STM32 USART6 port. */ -#ifdef CONFIG_STM32H7_USART6 +#ifdef CONFIG_STM32_USART6 static struct up_dev_s g_usart6priv = { .dev = @@ -1338,7 +1338,7 @@ static struct up_dev_s g_usart6priv = /* This describes the state of the STM32 UART7 port. */ -#ifdef CONFIG_STM32H7_UART7 +#ifdef CONFIG_STM32_UART7 static struct up_dev_s g_uart7priv = { .dev = @@ -1408,7 +1408,7 @@ static struct up_dev_s g_uart7priv = /* This describes the state of the STM32 UART8 port. */ -#ifdef CONFIG_STM32H7_UART8 +#ifdef CONFIG_STM32_UART8 static struct up_dev_s g_uart8priv = { .dev = @@ -1480,28 +1480,28 @@ static struct up_dev_s g_uart8priv = static struct up_dev_s * const g_uart_devs[STM32_NSERIAL] = { -#ifdef CONFIG_STM32H7_USART1 +#ifdef CONFIG_STM32_USART1 [0] = &g_usart1priv, #endif -#ifdef CONFIG_STM32H7_USART2 +#ifdef CONFIG_STM32_USART2 [1] = &g_usart2priv, #endif -#ifdef CONFIG_STM32H7_USART3 +#ifdef CONFIG_STM32_USART3 [2] = &g_usart3priv, #endif -#ifdef CONFIG_STM32H7_UART4 +#ifdef CONFIG_STM32_UART4 [3] = &g_uart4priv, #endif -#ifdef CONFIG_STM32H7_UART5 +#ifdef CONFIG_STM32_UART5 [4] = &g_uart5priv, #endif -#ifdef CONFIG_STM32H7_USART6 +#ifdef CONFIG_STM32_USART6 [5] = &g_usart6priv, #endif -#ifdef CONFIG_STM32H7_UART7 +#ifdef CONFIG_STM32_UART7 [6] = &g_uart7priv, #endif -#ifdef CONFIG_STM32H7_UART8 +#ifdef CONFIG_STM32_UART8 [7] = &g_uart8priv, #endif }; @@ -1797,7 +1797,7 @@ static void up_set_format(struct uart_dev_s *dev) regval &= ~(USART_CR3_CTSE | USART_CR3_RTSE); #if defined(CONFIG_SERIAL_IFLOWCONTROL) && \ - !defined(CONFIG_STM32H7_FLOWCONTROL_BROKEN) + !defined(CONFIG_STM32_FLOWCONTROL_BROKEN) if (priv->iflow && (priv->rts_gpio != 0)) { regval |= USART_CR3_RTSE; @@ -1952,7 +1952,7 @@ static void up_pm_setsuspend(bool suspend) g_serialpm.serial_suspended = suspend; - for (n = 0; n < STM32H7_NUSART + STM32H7_NUART; n++) + for (n = 0; n < STM32_NUSART + STM32_NUART; n++) { struct up_dev_s *priv = g_uart_devs[n]; @@ -1990,49 +1990,49 @@ static void up_set_apb_clock(struct uart_dev_s *dev, bool on) { default: return; -#ifdef CONFIG_STM32H7_USART1 +#ifdef CONFIG_STM32_USART1 case STM32_USART1_BASE: rcc_en = RCC_APB2ENR_USART1EN; regaddr = STM32_RCC_APB2ENR; break; #endif -#ifdef CONFIG_STM32H7_USART2 +#ifdef CONFIG_STM32_USART2 case STM32_USART2_BASE: rcc_en = RCC_APB1LENR_USART2EN; regaddr = STM32_RCC_APB1LENR; break; #endif -#ifdef CONFIG_STM32H7_USART3 +#ifdef CONFIG_STM32_USART3 case STM32_USART3_BASE: rcc_en = RCC_APB1LENR_USART3EN; regaddr = STM32_RCC_APB1LENR; break; #endif -#ifdef CONFIG_STM32H7_UART4 +#ifdef CONFIG_STM32_UART4 case STM32_UART4_BASE: rcc_en = RCC_APB1LENR_UART4EN; regaddr = STM32_RCC_APB1LENR; break; #endif -#ifdef CONFIG_STM32H7_UART5 +#ifdef CONFIG_STM32_UART5 case STM32_UART5_BASE: rcc_en = RCC_APB1LENR_UART5EN; regaddr = STM32_RCC_APB1LENR; break; #endif -#ifdef CONFIG_STM32H7_USART6 +#ifdef CONFIG_STM32_USART6 case STM32_USART6_BASE: rcc_en = RCC_APB2ENR_USART6EN; regaddr = STM32_RCC_APB2ENR; break; #endif -#ifdef CONFIG_STM32H7_UART7 +#ifdef CONFIG_STM32_UART7 case STM32_UART7_BASE: rcc_en = RCC_APB1LENR_UART7EN; regaddr = STM32_RCC_APB1LENR; break; #endif -#ifdef CONFIG_STM32H7_UART8 +#ifdef CONFIG_STM32_UART8 case STM32_UART8_BASE: rcc_en = RCC_APB1LENR_UART8EN; regaddr = STM32_RCC_APB1LENR; @@ -2104,7 +2104,7 @@ static int up_setup(struct uart_dev_s *dev) { uint32_t config = priv->rts_gpio; -#ifdef CONFIG_STM32H7_FLOWCONTROL_BROKEN +#ifdef CONFIG_STM32_FLOWCONTROL_BROKEN /* Instead of letting hw manage this pin, we will bitbang */ config = (config & ~GPIO_MODE_MASK) | GPIO_OUTPUT; @@ -2477,8 +2477,8 @@ static int up_interrupt(int irq, void *context, void *arg) /* Report serial activity to the power management logic */ -#if defined(CONFIG_PM) && CONFIG_STM32H7_PM_SERIAL_ACTIVITY > 0 - pm_activity(PM_IDLE_DOMAIN, CONFIG_STM32H7_PM_SERIAL_ACTIVITY); +#if defined(CONFIG_PM) && CONFIG_STM32_PM_SERIAL_ACTIVITY > 0 + pm_activity(PM_IDLE_DOMAIN, CONFIG_STM32_PM_SERIAL_ACTIVITY); #endif /* Get the masked USART status word. */ @@ -2592,14 +2592,14 @@ static int up_interrupt(int irq, void *context, void *arg) static int up_ioctl(struct file *filep, int cmd, unsigned long arg) { #if defined(CONFIG_SERIAL_TERMIOS) || defined(CONFIG_SERIAL_TIOCSERGSTRUCT) \ - || defined(CONFIG_STM32H7_USART_SINGLEWIRE) \ - || defined(CONFIG_STM32H7_SERIALBRK_BSDCOMPAT) + || defined(CONFIG_STM32_USART_SINGLEWIRE) \ + || defined(CONFIG_STM32_SERIALBRK_BSDCOMPAT) struct inode *inode = filep->f_inode; struct uart_dev_s *dev = inode->i_private; #endif #if defined(CONFIG_SERIAL_TERMIOS) \ - || defined(CONFIG_STM32H7_USART_SINGLEWIRE) \ - || defined(CONFIG_STM32H7_SERIALBRK_BSDCOMPAT) + || defined(CONFIG_STM32_USART_SINGLEWIRE) \ + || defined(CONFIG_STM32_SERIALBRK_BSDCOMPAT) struct up_dev_s *priv = (struct up_dev_s *)dev->priv; #endif int ret = OK; @@ -2622,7 +2622,7 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg) break; #endif -#ifdef CONFIG_STM32H7_USART_SINGLEWIRE +#ifdef CONFIG_STM32_USART_SINGLEWIRE case TIOCSSINGLEWIRE: { uint32_t cr1; @@ -2689,7 +2689,7 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg) break; #endif -#ifdef CONFIG_STM32H7_USART_INVERT +#ifdef CONFIG_STM32_USART_INVERT case TIOCSINVERT: { uint32_t cr1; @@ -2740,7 +2740,7 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg) break; #endif -#ifdef CONFIG_STM32H7_USART_SWAP +#ifdef CONFIG_STM32_USART_SWAP case TIOCSSWAP: { uint32_t cr1; @@ -2877,8 +2877,8 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg) break; #endif /* CONFIG_SERIAL_TERMIOS */ -#ifdef CONFIG_STM32H7_USART_BREAKS -# ifdef CONFIG_STM32H7_SERIALBRK_BSDCOMPAT +#ifdef CONFIG_STM32_USART_BREAKS +# ifdef CONFIG_STM32_SERIALBRK_BSDCOMPAT case TIOCSBRK: /* BSD compatibility: Turn break on, unconditionally */ { irqstate_t flags; @@ -3088,7 +3088,7 @@ static bool up_rxflowcontrol(struct uart_dev_s *dev, struct up_dev_s *priv = (struct up_dev_s *)dev->priv; #if defined(CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS) && \ - defined(CONFIG_STM32H7_FLOWCONTROL_BROKEN) + defined(CONFIG_STM32_FLOWCONTROL_BROKEN) if (priv->iflow && (priv->rts_gpio != 0)) { /* Assert/de-assert nRTS set it high resume/stop sending */ @@ -3761,7 +3761,7 @@ static int up_pm_prepare(struct pm_callback_s *cb, int domain, * buffers. */ - for (n = 0; n < STM32H7_NUSART + STM32H7_NUART; n++) + for (n = 0; n < STM32_NUSART + STM32_NUART; n++) { struct up_dev_s *priv = g_uart_devs[n]; @@ -3911,7 +3911,7 @@ void arm_serialinit(void) #if CONSOLE_UART > 0 uart_register("/dev/console", &g_uart_devs[CONSOLE_UART - 1]->dev); -#ifndef CONFIG_STM32H7_SERIAL_DISABLE_REORDERING +#ifndef CONFIG_STM32_SERIAL_DISABLE_REORDERING /* If not disabled, register the console UART to ttyS0 and exclude * it from initializing it further down */ @@ -3940,7 +3940,7 @@ void arm_serialinit(void) continue; } -#ifndef CONFIG_STM32H7_SERIAL_DISABLE_REORDERING +#ifndef CONFIG_STM32_SERIAL_DISABLE_REORDERING /* Don't create a device for the console - we did that above */ if (g_uart_devs[i]->dev.isconsole) diff --git a/arch/arm/src/stm32h7/stm32_spi.c b/arch/arm/src/stm32h7/stm32_spi.c index 329abb73f25ad..7ca1e8103082b 100644 --- a/arch/arm/src/stm32h7/stm32_spi.c +++ b/arch/arm/src/stm32h7/stm32_spi.c @@ -75,9 +75,9 @@ #include "stm32_spi.h" #include "stm32_dma.h" -#if defined(CONFIG_STM32H7_SPI1) || defined(CONFIG_STM32H7_SPI2) || \ - defined(CONFIG_STM32H7_SPI3) || defined(CONFIG_STM32H7_SPI4) || \ - defined(CONFIG_STM32H7_SPI5) || defined(CONFIG_STM32H7_SPI6) +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || \ + defined(CONFIG_STM32_SPI3) || defined(CONFIG_STM32_SPI4) || \ + defined(CONFIG_STM32_SPI5) || defined(CONFIG_STM32_SPI6) /**************************************************************************** * Pre-processor Definitions @@ -87,19 +87,19 @@ /* SPI interrupts */ -#ifdef CONFIG_STM32H7_SPI_INTERRUPTS +#ifdef CONFIG_STM32_SPI_INTERRUPTS # error "Interrupt driven SPI not yet supported" #endif /* Can't have both interrupt driven SPI and SPI DMA */ -#if defined(CONFIG_STM32H7_SPI_INTERRUPTS) && defined(CONFIG_STM32H7_SPI_DMA) +#if defined(CONFIG_STM32_SPI_INTERRUPTS) && defined(CONFIG_STM32_SPI_DMA) # error "Cannot enable both interrupt mode and DMA mode for SPI" #endif /* SPI DMA priority */ -#ifdef CONFIG_STM32H7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA # if defined(CONFIG_SPI_DMAPRIO) # define SPI_DMA_PRIO CONFIG_SPI_DMAPRIO @@ -137,39 +137,39 @@ # define SPIDMA_BUF_ALIGN # endif -# if defined(CONFIG_STM32H7_SPI1_DMA_BUFFER) && \ - CONFIG_STM32H7_SPI1_DMA_BUFFER > 0 -# define SPI1_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32H7_SPI1_DMA_BUFFER) +# if defined(CONFIG_STM32_SPI1_DMA_BUFFER) && \ + CONFIG_STM32_SPI1_DMA_BUFFER > 0 +# define SPI1_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32_SPI1_DMA_BUFFER) # define SPI1_DMABUFSIZE_ALGN SPIDMA_BUF_ALIGN # endif -# if defined(CONFIG_STM32H7_SPI2_DMA_BUFFER) && \ - CONFIG_STM32H7_SPI2_DMA_BUFFER > 0 -# define SPI2_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32H7_SPI2_DMA_BUFFER) +# if defined(CONFIG_STM32_SPI2_DMA_BUFFER) && \ + CONFIG_STM32_SPI2_DMA_BUFFER > 0 +# define SPI2_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32_SPI2_DMA_BUFFER) # define SPI2_DMABUFSIZE_ALGN SPIDMA_BUF_ALIGN # endif -# if defined(CONFIG_STM32H7_SPI3_DMA_BUFFER) && \ - CONFIG_STM32H7_SPI3_DMA_BUFFER > 0 -# define SPI3_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32H7_SPI3_DMA_BUFFER) +# if defined(CONFIG_STM32_SPI3_DMA_BUFFER) && \ + CONFIG_STM32_SPI3_DMA_BUFFER > 0 +# define SPI3_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32_SPI3_DMA_BUFFER) # define SPI3_DMABUFSIZE_ALGN SPIDMA_BUF_ALIGN # endif -# if defined(CONFIG_STM32H7_SPI4_DMA_BUFFER) && \ - CONFIG_STM32H7_SPI4_DMA_BUFFER > 0 -# define SPI4_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32H7_SPI4_DMA_BUFFER) +# if defined(CONFIG_STM32_SPI4_DMA_BUFFER) && \ + CONFIG_STM32_SPI4_DMA_BUFFER > 0 +# define SPI4_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32_SPI4_DMA_BUFFER) # define SPI4_DMABUFSIZE_ALGN SPIDMA_BUF_ALIGN # endif -# if defined(CONFIG_STM32H7_SPI5_DMA_BUFFER) && \ - CONFIG_STM32H7_SPI5_DMA_BUFFER > 0 -# define SPI5_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32H7_SPI5_DMA_BUFFER) +# if defined(CONFIG_STM32_SPI5_DMA_BUFFER) && \ + CONFIG_STM32_SPI5_DMA_BUFFER > 0 +# define SPI5_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32_SPI5_DMA_BUFFER) # define SPI5_DMABUFSIZE_ALGN SPIDMA_BUF_ALIGN # endif -#if defined(CONFIG_STM32H7_SPI6_DMA_BUFFER) && \ - CONFIG_STM32H7_SPI6_DMA_BUFFER > 0 -# define SPI6_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32H7_SPI6_DMA_BUFFER) +#if defined(CONFIG_STM32_SPI6_DMA_BUFFER) && \ + CONFIG_STM32_SPI6_DMA_BUFFER > 0 +# define SPI6_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32_SPI6_DMA_BUFFER) # define SPI6_DMABUFSIZE_ALGN SPIDMA_BUF_ALIGN # endif @@ -180,8 +180,8 @@ * - support for all kernel clock configuration */ -#if defined(CONFIG_STM32H7_SPI1) || defined(CONFIG_STM32H7_SPI2) || \ - defined(CONFIG_STM32H7_SPI3) +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || \ + defined(CONFIG_STM32_SPI3) # if STM32_RCC_D2CCIP1R_SPI123SRC == RCC_D2CCIP1R_SPI123SEL_PLL1 # define SPI123_KERNEL_CLOCK_FREQ STM32_PLL1Q_FREQUENCY # elif STM32_RCC_D2CCIP1R_SPI123SRC == RCC_D2CCIP1R_SPI123SEL_PLL2 @@ -194,7 +194,7 @@ # endif #endif /* SPI123 */ -#if defined(CONFIG_STM32H7_SPI4) || defined(CONFIG_STM32H7_SPI5) +#if defined(CONFIG_STM32_SPI4) || defined(CONFIG_STM32_SPI5) # if STM32_RCC_D2CCIP1R_SPI45SRC == RCC_D2CCIP1R_SPI45SEL_APB # define SPI45_KERNEL_CLOCK_FREQ STM32_PCLK2_FREQUENCY # elif STM32_RCC_D2CCIP1R_SPI45SRC == RCC_D2CCIP1R_SPI45SEL_PLL2 @@ -207,7 +207,7 @@ # endif #endif /* SPI45 */ -#if defined(CONFIG_STM32H7_SPI6) +#if defined(CONFIG_STM32_SPI6) # if STM32_RCC_D3CCIPR_SPI6SRC == RCC_D3CCIPR_SPI6SEL_PCLK4 # define SPI6_KERNEL_CLOCK_FREQ STM32_PCLK4_FREQUENCY # elif STM32_RCC_D3CCIPR_SPI6SRC == RCC_D3CCIPR_SPI6SEL_PLL2 @@ -238,7 +238,7 @@ struct stm32_spidev_s uint32_t spibase; /* SPIn base address */ uint32_t spiclock; /* Clocking for the SPI module */ uint8_t spiirq; /* SPI IRQ number */ -#ifdef CONFIG_STM32H7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA volatile uint8_t rxresult; /* Result of the RX DMA */ volatile uint8_t txresult; /* Result of the RX DMA */ #ifdef CONFIG_SPI_TRIGGER @@ -288,7 +288,7 @@ static inline void spi_dumpregs(struct stm32_spidev_s *priv); /* DMA support */ -#ifdef CONFIG_STM32H7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static int spi_dmarxwait(struct stm32_spidev_s *priv); static int spi_dmatxwait(struct stm32_spidev_s *priv); static inline void spi_dmarxwakeup(struct stm32_spidev_s *priv); @@ -354,7 +354,7 @@ static int spi_pm_prepare(struct pm_callback_s *cb, int domain, * Private Data ****************************************************************************/ -#ifdef CONFIG_STM32H7_SPI1 +#ifdef CONFIG_STM32_SPI1 static const struct spi_ops_s g_sp1iops = { .lock = spi_lock, @@ -403,7 +403,7 @@ static struct stm32_spidev_s g_spi1dev = .spibase = STM32_SPI1_BASE, .spiclock = SPI123_KERNEL_CLOCK_FREQ, .spiirq = STM32_IRQ_SPI1, -#ifdef CONFIG_STM32H7_SPI1_DMA +#ifdef CONFIG_STM32_SPI1_DMA .rxch = DMAMAP_SPI1_RX, .txch = DMAMAP_SPI1_TX, # if defined(SPI1_DMABUFSIZE_ADJUSTED) @@ -418,15 +418,15 @@ static struct stm32_spidev_s g_spi1dev = #ifdef CONFIG_PM .pm_cb.prepare = spi_pm_prepare, #endif -#ifdef CONFIG_STM32H7_SPI1_COMMTYPE - .config = CONFIG_STM32H7_SPI1_COMMTYPE, +#ifdef CONFIG_STM32_SPI1_COMMTYPE + .config = CONFIG_STM32_SPI1_COMMTYPE, #else .config = FULL_DUPLEX, #endif }; -#endif /* CONFIG_STM32H7_SPI1 */ +#endif /* CONFIG_STM32_SPI1 */ -#ifdef CONFIG_STM32H7_SPI2 +#ifdef CONFIG_STM32_SPI2 static const struct spi_ops_s g_sp2iops = { .lock = spi_lock, @@ -475,7 +475,7 @@ static struct stm32_spidev_s g_spi2dev = .spibase = STM32_SPI2_BASE, .spiclock = SPI123_KERNEL_CLOCK_FREQ, .spiirq = STM32_IRQ_SPI2, -#ifdef CONFIG_STM32H7_SPI2_DMA +#ifdef CONFIG_STM32_SPI2_DMA .rxch = DMAMAP_SPI2_RX, .txch = DMAMAP_SPI2_TX, # if defined(SPI2_DMABUFSIZE_ADJUSTED) @@ -490,15 +490,15 @@ static struct stm32_spidev_s g_spi2dev = #ifdef CONFIG_PM .pm_cb.prepare = spi_pm_prepare, #endif -#ifdef CONFIG_STM32H7_SPI2_COMMTYPE - .config = CONFIG_STM32H7_SPI2_COMMTYPE, +#ifdef CONFIG_STM32_SPI2_COMMTYPE + .config = CONFIG_STM32_SPI2_COMMTYPE, #else .config = FULL_DUPLEX, #endif }; -#endif /* CONFIG_STM32H7_SPI2 */ +#endif /* CONFIG_STM32_SPI2 */ -#ifdef CONFIG_STM32H7_SPI3 +#ifdef CONFIG_STM32_SPI3 static const struct spi_ops_s g_sp3iops = { .lock = spi_lock, @@ -547,7 +547,7 @@ static struct stm32_spidev_s g_spi3dev = .spibase = STM32_SPI3_BASE, .spiclock = SPI123_KERNEL_CLOCK_FREQ, .spiirq = STM32_IRQ_SPI3, -#ifdef CONFIG_STM32H7_SPI3_DMA +#ifdef CONFIG_STM32_SPI3_DMA .rxch = DMAMAP_SPI3_RX, .txch = DMAMAP_SPI3_TX, # if defined(SPI3_DMABUFSIZE_ADJUSTED) @@ -562,15 +562,15 @@ static struct stm32_spidev_s g_spi3dev = #ifdef CONFIG_PM .pm_cb.prepare = spi_pm_prepare, #endif -#ifdef CONFIG_STM32H7_SPI3_COMMTYPE - .config = CONFIG_STM32H7_SPI3_COMMTYPE, +#ifdef CONFIG_STM32_SPI3_COMMTYPE + .config = CONFIG_STM32_SPI3_COMMTYPE, #else .config = FULL_DUPLEX, #endif }; -#endif /* CONFIG_STM32H7_SPI3 */ +#endif /* CONFIG_STM32_SPI3 */ -#ifdef CONFIG_STM32H7_SPI4 +#ifdef CONFIG_STM32_SPI4 static const struct spi_ops_s g_sp4iops = { .lock = spi_lock, @@ -619,7 +619,7 @@ static struct stm32_spidev_s g_spi4dev = .spibase = STM32_SPI4_BASE, .spiclock = SPI45_KERNEL_CLOCK_FREQ, .spiirq = STM32_IRQ_SPI4, -#ifdef CONFIG_STM32H7_SPI4_DMA +#ifdef CONFIG_STM32_SPI4_DMA .rxch = DMAMAP_SPI4_RX, .txch = DMAMAP_SPI4_TX, # if defined(SPI4_DMABUFSIZE_ADJUSTED) @@ -634,15 +634,15 @@ static struct stm32_spidev_s g_spi4dev = #ifdef CONFIG_PM .pm_cb.prepare = spi_pm_prepare, #endif -#ifdef CONFIG_STM32H7_SPI4_COMMTYPE - .config = CONFIG_STM32H7_SPI4_COMMTYPE, +#ifdef CONFIG_STM32_SPI4_COMMTYPE + .config = CONFIG_STM32_SPI4_COMMTYPE, #else .config = FULL_DUPLEX, #endif }; -#endif /* CONFIG_STM32H7_SPI4 */ +#endif /* CONFIG_STM32_SPI4 */ -#ifdef CONFIG_STM32H7_SPI5 +#ifdef CONFIG_STM32_SPI5 static const struct spi_ops_s g_sp5iops = { .lock = spi_lock, @@ -691,7 +691,7 @@ static struct stm32_spidev_s g_spi5dev = .spibase = STM32_SPI5_BASE, .spiclock = SPI45_KERNEL_CLOCK_FREQ, .spiirq = STM32_IRQ_SPI5, -#ifdef CONFIG_STM32H7_SPI5_DMA +#ifdef CONFIG_STM32_SPI5_DMA .rxch = DMAMAP_SPI5_RX, .txch = DMAMAP_SPI5_TX, # if defined(SPI5_DMABUFSIZE_ADJUSTED) @@ -706,15 +706,15 @@ static struct stm32_spidev_s g_spi5dev = #ifdef CONFIG_PM .pm_cb.prepare = spi_pm_prepare, #endif -#ifdef CONFIG_STM32H7_SPI5_COMMTYPE - .config = CONFIG_STM32H7_SPI5_COMMTYPE, +#ifdef CONFIG_STM32_SPI5_COMMTYPE + .config = CONFIG_STM32_SPI5_COMMTYPE, #else .config = FULL_DUPLEX, #endif }; -#endif /* CONFIG_STM32H7_SPI5 */ +#endif /* CONFIG_STM32_SPI5 */ -#ifdef CONFIG_STM32H7_SPI6 +#ifdef CONFIG_STM32_SPI6 static const struct spi_ops_s g_sp6iops = { .lock = spi_lock, @@ -764,7 +764,7 @@ static struct stm32_spidev_s g_spi6dev = .spibase = STM32_SPI6_BASE, .spiclock = SPI6_KERNEL_CLOCK_FREQ, .spiirq = STM32_IRQ_SPI6, -#ifdef CONFIG_STM32H7_SPI6_DMA +#ifdef CONFIG_STM32_SPI6_DMA .rxch = DMAMAP_SPI6_RX, .txch = DMAMAP_SPI6_TX, # if defined(SPI6_DMABUFSIZE_ADJUSTED) @@ -779,13 +779,13 @@ static struct stm32_spidev_s g_spi6dev = #ifdef CONFIG_PM .pm_cb.prepare = spi_pm_prepare, #endif -#ifdef CONFIG_STM32H7_SPI6_COMMTYPE - .config = CONFIG_STM32H7_SPI6_COMMTYPE, +#ifdef CONFIG_STM32_SPI6_COMMTYPE + .config = CONFIG_STM32_SPI6_COMMTYPE, #else .config = FULL_DUPLEX, #endif }; -#endif /* CONFIG_STM32H7_SPI6 */ +#endif /* CONFIG_STM32_SPI6 */ /**************************************************************************** * Private Functions @@ -1107,7 +1107,7 @@ static int spi_interrupt(int irq, void *context, void *arg) spi_modifyreg(priv, STM32_SPI_IER_OFFSET, SPI_IER_EOTIE, 0); /* Set result and release wait semaphore */ -#ifdef CONFIG_STM32H7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA priv->txresult = 0x80; nxsem_post(&priv->txsem); #endif @@ -1124,7 +1124,7 @@ static int spi_interrupt(int irq, void *context, void *arg) * ****************************************************************************/ -#ifdef CONFIG_STM32H7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static int spi_dmarxwait(struct stm32_spidev_s *priv) { int ret; @@ -1164,7 +1164,7 @@ static int spi_dmarxwait(struct stm32_spidev_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32H7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static int spi_dmatxwait(struct stm32_spidev_s *priv) { int ret; @@ -1213,7 +1213,7 @@ static int spi_dmatxwait(struct stm32_spidev_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32H7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static inline void spi_dmarxwakeup(struct stm32_spidev_s *priv) { nxsem_post(&priv->rxsem); @@ -1228,7 +1228,7 @@ static inline void spi_dmarxwakeup(struct stm32_spidev_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32H7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_dmarxcallback(DMA_HANDLE handle, uint8_t isr, void *arg) { struct stm32_spidev_s *priv = (struct stm32_spidev_s *)arg; @@ -1248,7 +1248,7 @@ static void spi_dmarxcallback(DMA_HANDLE handle, uint8_t isr, void *arg) * ****************************************************************************/ -#ifdef CONFIG_STM32H7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_dmarxsetup(struct stm32_spidev_s *priv, void *rxbuffer, void *rxdummy, size_t nwords, stm32_dmacfg_t *dmacfg) @@ -1310,7 +1310,7 @@ static void spi_dmarxsetup(struct stm32_spidev_s *priv, * ****************************************************************************/ -#ifdef CONFIG_STM32H7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_dmatxsetup(struct stm32_spidev_s *priv, const void *txbuffer, const void *txdummy, size_t nwords, stm32_dmacfg_t *dmacfg) @@ -1370,7 +1370,7 @@ static void spi_dmatxsetup(struct stm32_spidev_s *priv, * ****************************************************************************/ -#ifdef CONFIG_STM32H7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_dmarxstart(struct stm32_spidev_s *priv) { /* Can't receive in tx only mode */ @@ -1394,7 +1394,7 @@ static void spi_dmarxstart(struct stm32_spidev_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32H7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_dmatxstart(struct stm32_spidev_s *priv) { /* Can't transmit in rx only mode */ @@ -1929,9 +1929,9 @@ static uint32_t spi_send(struct spi_dev_s *dev, uint32_t wd) * ****************************************************************************/ -#if !defined(CONFIG_STM32H7_SPI_DMA) || defined(CONFIG_STM32H7_DMACAPABLE) || \ - defined(CONFIG_STM32H7_SPI_DMATHRESHOLD) -#if !defined(CONFIG_STM32H7_SPI_DMA) +#if !defined(CONFIG_STM32_SPI_DMA) || defined(CONFIG_STM32_DMACAPABLE) || \ + defined(CONFIG_STM32_SPI_DMATHRESHOLD) +#if !defined(CONFIG_STM32_SPI_DMA) static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, void *rxbuffer, size_t nwords) #else @@ -2020,8 +2020,8 @@ static void spi_exchange_nodma(struct spi_dev_s *dev, } } -#endif /* !CONFIG_STM32H7_SPI_DMA || CONFIG_STM32H7_DMACAPABLE || - * CONFIG_STM32H7_SPI_DMATHRESHOLD +#endif /* !CONFIG_STM32_SPI_DMA || CONFIG_STM32_DMACAPABLE || + * CONFIG_STM32_SPI_DMATHRESHOLD */ /**************************************************************************** @@ -2045,7 +2045,7 @@ static void spi_exchange_nodma(struct spi_dev_s *dev, * ****************************************************************************/ -#ifdef CONFIG_STM32H7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, void *rxbuffer, size_t nwords) { @@ -2063,12 +2063,12 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, size_t nbytes = (priv->nbits > 8) ? nwords << 1 : nwords; -#ifdef CONFIG_STM32H7_SPI_DMATHRESHOLD +#ifdef CONFIG_STM32_SPI_DMATHRESHOLD /* If this is a small SPI transfer, then let spi_exchange_nodma() do the * work. */ - if (nbytes <= CONFIG_STM32H7_SPI_DMATHRESHOLD) + if (nbytes <= CONFIG_STM32_SPI_DMATHRESHOLD) { spi_exchange_nodma(dev, txbuffer, rxbuffer, nwords); return; @@ -2132,7 +2132,7 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, spi_dmatxsetup(priv, txbuffer, &txdummy, nwords, &txdmacfg); spi_dmarxsetup(priv, rxbuffer, (uint16_t *)rxdummy, nwords, &rxdmacfg); -#ifdef CONFIG_STM32H7_DMACAPABLE +#ifdef CONFIG_STM32_DMACAPABLE /* Test for DMA capability of only callers buffers, internal buffers are * guaranteed capable. @@ -2264,7 +2264,7 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, priv->trigarmed = false; #endif } -#endif /* CONFIG_STM32H7_SPI_DMA */ +#endif /* CONFIG_STM32_SPI_DMA */ /**************************************************************************** * Name: spi_trigger @@ -2285,7 +2285,7 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, #ifdef CONFIG_SPI_TRIGGER static int spi_trigger(struct spi_dev_s *dev) { -#ifdef CONFIG_STM32H7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev; if (!priv->trigarmed) @@ -2519,7 +2519,7 @@ static void spi_bus_initialize(struct stm32_spidev_s *priv) spi_putreg(priv, STM32_SPI_CRCPOLY_OFFSET, 7); -#ifdef CONFIG_STM32H7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA /* Get DMA channels. NOTE: stm32_dmachannel() will always assign the DMA * channel. If the channel is not available, then stm32_dmachannel() will * block and wait until the channel becomes available. WARNING: If you @@ -2601,7 +2601,7 @@ struct spi_dev_s *stm32_spibus_initialize(int bus) struct stm32_spidev_s *priv = NULL; irqstate_t flags = enter_critical_section(); -#ifdef CONFIG_STM32H7_SPI1 +#ifdef CONFIG_STM32_SPI1 if (bus == 1) { /* Select SPI1 */ @@ -2626,7 +2626,7 @@ struct spi_dev_s *stm32_spibus_initialize(int bus) } else #endif -#ifdef CONFIG_STM32H7_SPI2 +#ifdef CONFIG_STM32_SPI2 if (bus == 2) { /* Select SPI2 */ @@ -2651,7 +2651,7 @@ struct spi_dev_s *stm32_spibus_initialize(int bus) } else #endif -#ifdef CONFIG_STM32H7_SPI3 +#ifdef CONFIG_STM32_SPI3 if (bus == 3) { /* Select SPI3 */ @@ -2676,7 +2676,7 @@ struct spi_dev_s *stm32_spibus_initialize(int bus) } else #endif -#ifdef CONFIG_STM32H7_SPI4 +#ifdef CONFIG_STM32_SPI4 if (bus == 4) { /* Select SPI4 */ @@ -2701,7 +2701,7 @@ struct spi_dev_s *stm32_spibus_initialize(int bus) } else #endif -#ifdef CONFIG_STM32H7_SPI5 +#ifdef CONFIG_STM32_SPI5 if (bus == 5) { /* Select SPI5 */ @@ -2726,7 +2726,7 @@ struct spi_dev_s *stm32_spibus_initialize(int bus) } else #endif -#ifdef CONFIG_STM32H7_SPI6 +#ifdef CONFIG_STM32_SPI6 if (bus == 6) { /* Select SPI6 */ @@ -2759,6 +2759,6 @@ struct spi_dev_s *stm32_spibus_initialize(int bus) return (struct spi_dev_s *)priv; } -#endif /* CONFIG_STM32H7_SPI1 || CONFIG_STM32H7_SPI2 || CONFIG_STM32H7_SPI3 || - * CONFIG_STM32H7_SPI4 || CONFIG_STM32H7_SPI5 || CONFIG_STM32H7_SPI6 +#endif /* CONFIG_STM32_SPI1 || CONFIG_STM32_SPI2 || CONFIG_STM32_SPI3 || + * CONFIG_STM32_SPI4 || CONFIG_STM32_SPI5 || CONFIG_STM32_SPI6 */ diff --git a/arch/arm/src/stm32h7/stm32_spi.h b/arch/arm/src/stm32h7/stm32_spi.h index a9b0532e0757e..663a2eac486db 100644 --- a/arch/arm/src/stm32h7/stm32_spi.h +++ b/arch/arm/src/stm32h7/stm32_spi.h @@ -114,42 +114,42 @@ struct spi_slave_ctrlr_s *stm32_spi_slave_initialize(int bus); * ****************************************************************************/ -#ifdef CONFIG_STM32H7_SPI1 +#ifdef CONFIG_STM32_SPI1 void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, bool selected); uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid); int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); #endif -#ifdef CONFIG_STM32H7_SPI2 +#ifdef CONFIG_STM32_SPI2 void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid, bool selected); uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid); int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); #endif -#ifdef CONFIG_STM32H7_SPI3 +#ifdef CONFIG_STM32_SPI3 void stm32_spi3select(struct spi_dev_s *dev, uint32_t devid, bool selected); uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid); int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); #endif -#ifdef CONFIG_STM32H7_SPI4 +#ifdef CONFIG_STM32_SPI4 void stm32_spi4select(struct spi_dev_s *dev, uint32_t devid, bool selected); uint8_t stm32_spi4status(struct spi_dev_s *dev, uint32_t devid); int stm32_spi4cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); #endif -#ifdef CONFIG_STM32H7_SPI5 +#ifdef CONFIG_STM32_SPI5 void stm32_spi5select(struct spi_dev_s *dev, uint32_t devid, bool selected); uint8_t stm32_spi5status(struct spi_dev_s *dev, uint32_t devid); int stm32_spi5cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); #endif -#ifdef CONFIG_STM32H7_SPI6 +#ifdef CONFIG_STM32_SPI6 void stm32_spi6select(struct spi_dev_s *dev, uint32_t devid, bool selected); uint8_t stm32_spi6status(struct spi_dev_s *dev, uint32_t devid); @@ -177,32 +177,32 @@ int stm32_spi6cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); ****************************************************************************/ #ifdef CONFIG_SPI_CALLBACK -#ifdef CONFIG_STM32H7_SPI1 +#ifdef CONFIG_STM32_SPI1 int stm32_spi1register(struct spi_dev_s *dev, spi_mediachange_t callback, void *arg); #endif -#ifdef CONFIG_STM32H7_SPI2 +#ifdef CONFIG_STM32_SPI2 int stm32_spi2register(struct spi_dev_s *dev, spi_mediachange_t callback, void *arg); #endif -#ifdef CONFIG_STM32H7_SPI3 +#ifdef CONFIG_STM32_SPI3 int stm32_spi3register(struct spi_dev_s *dev, spi_mediachange_t callback, void *arg); #endif -#ifdef CONFIG_STM32H7_SPI4 +#ifdef CONFIG_STM32_SPI4 int stm32_spi4register(struct spi_dev_s *dev, spi_mediachange_t callback, void *arg); #endif -#ifdef CONFIG_STM32H7_SPI5 +#ifdef CONFIG_STM32_SPI5 int stm32_spi5register(struct spi_dev_s *dev, spi_mediachange_t callback, void *arg); #endif -#ifdef CONFIG_STM32H7_SPI6 +#ifdef CONFIG_STM32_SPI6 int stm32_spi6register(struct spi_dev_s *dev, spi_mediachange_t callback, void *arg); #endif diff --git a/arch/arm/src/stm32h7/stm32_spi_slave.c b/arch/arm/src/stm32h7/stm32_spi_slave.c index efa9fc5641162..1231ffb3c11e0 100644 --- a/arch/arm/src/stm32h7/stm32_spi_slave.c +++ b/arch/arm/src/stm32h7/stm32_spi_slave.c @@ -52,12 +52,12 @@ #include "stm32_spi.h" #include "stm32_dma.h" -#if defined(CONFIG_STM32H7_SPI1_SLAVE) || \ - defined(CONFIG_STM32H7_SPI2_SLAVE) || \ - defined(CONFIG_STM32H7_SPI3_SLAVE) || \ - defined(CONFIG_STM32H7_SPI4_SLAVE) || \ - defined(CONFIG_STM32H7_SPI5_SLAVE) || \ - defined(CONFIG_STM32H7_SPI6_SLAVE) +#if defined(CONFIG_STM32_SPI1_SLAVE) || \ + defined(CONFIG_STM32_SPI2_SLAVE) || \ + defined(CONFIG_STM32_SPI3_SLAVE) || \ + defined(CONFIG_STM32_SPI4_SLAVE) || \ + defined(CONFIG_STM32_SPI5_SLAVE) || \ + defined(CONFIG_STM32_SPI6_SLAVE) /**************************************************************************** * Pre-processor Definitions @@ -67,19 +67,19 @@ /* SPI interrupts */ -#ifdef CONFIG_STM32H7_SPI_INTERRUPTS +#ifdef CONFIG_STM32_SPI_INTERRUPTS # error "Interrupt driven SPI not yet supported" #endif /* Can't have both interrupt driven SPI and SPI DMA */ -#if defined(CONFIG_STM32H7_SPI_INTERRUPTS) && defined(CONFIG_STM32H7_SPI_DMA) +#if defined(CONFIG_STM32_SPI_INTERRUPTS) && defined(CONFIG_STM32_SPI_DMA) # error "Cannot enable both interrupt mode and DMA mode for SPI" #endif /* SPI DMA priority */ -#ifdef CONFIG_STM32H7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA # if defined(CONFIG_SPI_DMAPRIO) # define SPI_DMA_PRIO CONFIG_SPI_DMAPRIO @@ -113,8 +113,8 @@ * - support for all kernel clock configuration */ -#if defined(CONFIG_STM32H7_SPI1_SLAVE) || defined(CONFIG_STM32H7_SPI2_SLAVE) || \ - defined(CONFIG_STM32H7_SPI3_SLAVE) +#if defined(CONFIG_STM32_SPI1_SLAVE) || defined(CONFIG_STM32_SPI2_SLAVE) || \ + defined(CONFIG_STM32_SPI3_SLAVE) # if STM32_RCC_D2CCIP1R_SPI123SRC == RCC_D2CCIP1R_SPI123SEL_PLL1 # define SPI123_KERNEL_CLOCK_FREQ STM32_PLL1Q_FREQUENCY # else @@ -125,7 +125,7 @@ # endif #endif /* SPI123 */ -#if defined(CONFIG_STM32H7_SPI4_SLAVE) || defined(CONFIG_STM32H7_SPI5_SLAVE) +#if defined(CONFIG_STM32_SPI4_SLAVE) || defined(CONFIG_STM32_SPI5_SLAVE) # if STM32_RCC_D2CCIP1R_SPI45SRC == RCC_D2CCIP1R_SPI45SEL_APB # define SPI45_KERNEL_CLOCK_FREQ STM32_PCLK2_FREQUENCY # else @@ -136,7 +136,7 @@ # endif #endif /* SPI45 */ -#if defined(CONFIG_STM32H7_SPI6_SLAVE) +#if defined(CONFIG_STM32_SPI6_SLAVE) # if STM32_RCC_D3CCIPR_SPI6SRC == RCC_D3CCIPR_SPI6SEL_PCLK4 # define SPI6_KERNEL_CLOCK_FREQ STM32_PCLK4_FREQUENCY # else @@ -147,9 +147,9 @@ # endif #endif /* SPI6 */ -#if defined (CONFIG_STM32H7_SPI_SLAVE_QSIZE) -# if CONFIG_STM32H7_SPI_SLAVE_QSIZE > 65535 -# error CONFIG_STM32H7_SPI_SLAVE_QSIZE too large +#if defined (CONFIG_STM32_SPI_SLAVE_QSIZE) +# if CONFIG_STM32_SPI_SLAVE_QSIZE > 65535 +# error CONFIG_STM32_SPI_SLAVE_QSIZE too large # endif #endif @@ -157,7 +157,7 @@ * support is in place */ -#if defined (CONFIG_STM32H7_SPI6_SLAVE) +#if defined (CONFIG_STM32_SPI6_SLAVE) # error SPI6 slave not supported yet #endif @@ -187,7 +187,7 @@ struct stm32_spidev_s uint32_t spiclock; /* Clocking for the SPI module */ uint8_t irq; /* SPI IRQ number */ uint32_t nss_pin; /* Chip select pin configuration */ -#ifdef CONFIG_STM32H7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA volatile uint8_t rxresult; /* Result of the RX DMA */ volatile uint8_t txresult; /* Result of the TX DMA */ uint32_t rxch; /* The RX DMA channel number */ @@ -221,7 +221,7 @@ struct stm32_spidev_s /* Input queue */ uint16_t ihead; /* Location of next unread value */ -#ifndef CONFIG_STM32H7_SPI_DMA +#ifndef CONFIG_STM32_SPI_DMA uint16_t itail; /* Index of next free memory pointer */ #endif uint8_t *inq; @@ -250,7 +250,7 @@ static inline void spi_dumpregs(struct stm32_spidev_s *priv); /* DMA support */ -#ifdef CONFIG_STM32H7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_dmarxcallback(DMA_HANDLE handle, uint8_t isr, void *arg); static void spi_dmatxcallback(DMA_HANDLE handle, uint8_t isr, @@ -311,7 +311,7 @@ static const struct spi_slave_ctrlrops_s g_ctrlr_ops = #define SPI_SLAVE_OUTQ(x) spi##x##_outq #define SPI_SLAVE_INQ(x) spi##x##_inq -#ifdef CONFIG_STM32H7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA #define SPI_SLAVE_INIT_DMA(x) \ .rxch = DMAMAP_SPI##x##_RX, \ .txch = DMAMAP_SPI##x##_TX, \ @@ -340,78 +340,78 @@ static const struct spi_slave_ctrlrops_s g_ctrlr_ops = .initialized = false, \ .lock = NXMUTEX_INITIALIZER, \ SPI_SLAVE_INIT_PM_PREPARE \ - .config = CONFIG_STM32H7_SPI##x##_COMMTYPE, \ + .config = CONFIG_STM32_SPI##x##_COMMTYPE, \ } -#ifdef CONFIG_STM32H7_SPI1_SLAVE +#ifdef CONFIG_STM32_SPI1_SLAVE static -uint8_t SPI_SLAVE_OUTQ(1)[DMA_ALIGN_UP(CONFIG_STM32H7_SPI_SLAVE_QSIZE)] +uint8_t SPI_SLAVE_OUTQ(1)[DMA_ALIGN_UP(CONFIG_STM32_SPI_SLAVE_QSIZE)] aligned_data(ARMV7M_DCACHE_LINESIZE); static -uint8_t SPI_SLAVE_INQ(1)[DMA_ALIGN_UP(CONFIG_STM32H7_SPI_SLAVE_QSIZE)] +uint8_t SPI_SLAVE_INQ(1)[DMA_ALIGN_UP(CONFIG_STM32_SPI_SLAVE_QSIZE)] aligned_data(ARMV7M_DCACHE_LINESIZE); static struct stm32_spidev_s g_spi1ctrlr = SPI_SLAVE_INIT(1); #endif -#ifdef CONFIG_STM32H7_SPI2_SLAVE +#ifdef CONFIG_STM32_SPI2_SLAVE static -uint8_t SPI_SLAVE_OUTQ(2)[DMA_ALIGN_UP(CONFIG_STM32H7_SPI_SLAVE_QSIZE)] +uint8_t SPI_SLAVE_OUTQ(2)[DMA_ALIGN_UP(CONFIG_STM32_SPI_SLAVE_QSIZE)] aligned_data(ARMV7M_DCACHE_LINESIZE); static -uint8_t SPI_SLAVE_INQ(2)[DMA_ALIGN_UP(CONFIG_STM32H7_SPI_SLAVE_QSIZE)] +uint8_t SPI_SLAVE_INQ(2)[DMA_ALIGN_UP(CONFIG_STM32_SPI_SLAVE_QSIZE)] aligned_data(ARMV7M_DCACHE_LINESIZE); static struct stm32_spidev_s g_spi2ctrlr = SPI_SLAVE_INIT(2); #endif -#ifdef CONFIG_STM32H7_SPI3_SLAVE +#ifdef CONFIG_STM32_SPI3_SLAVE static -uint8_t SPI_SLAVE_OUTQ(3)[DMA_ALIGN_UP(CONFIG_STM32H7_SPI_SLAVE_QSIZE)] +uint8_t SPI_SLAVE_OUTQ(3)[DMA_ALIGN_UP(CONFIG_STM32_SPI_SLAVE_QSIZE)] aligned_data(ARMV7M_DCACHE_LINESIZE); static -uint8_t SPI_SLAVE_INQ(3)[DMA_ALIGN_UP(CONFIG_STM32H7_SPI_SLAVE_QSIZE)] +uint8_t SPI_SLAVE_INQ(3)[DMA_ALIGN_UP(CONFIG_STM32_SPI_SLAVE_QSIZE)] aligned_data(ARMV7M_DCACHE_LINESIZE); static struct stm32_spidev_s g_spi3ctrlr = SPI_SLAVE_INIT(3); #endif -#ifdef CONFIG_STM32H7_SPI4_SLAVE +#ifdef CONFIG_STM32_SPI4_SLAVE static -uint8_t SPI_SLAVE_OUTQ(4)[DMA_ALIGN_UP(CONFIG_STM32H7_SPI_SLAVE_QSIZE)] +uint8_t SPI_SLAVE_OUTQ(4)[DMA_ALIGN_UP(CONFIG_STM32_SPI_SLAVE_QSIZE)] aligned_data(ARMV7M_DCACHE_LINESIZE); static -uint8_t SPI_SLAVE_INQ(4)[DMA_ALIGN_UP(CONFIG_STM32H7_SPI_SLAVE_QSIZE)] +uint8_t SPI_SLAVE_INQ(4)[DMA_ALIGN_UP(CONFIG_STM32_SPI_SLAVE_QSIZE)] aligned_data(ARMV7M_DCACHE_LINESIZE); static struct stm32_spidev_s g_spi4ctrlr = SPI_SLAVE_INIT(4); #endif -#ifdef CONFIG_STM32H7_SPI5_SLAVE +#ifdef CONFIG_STM32_SPI5_SLAVE static -uint8_t SPI_SLAVE_OUTQ(5)[DMA_ALIGN_UP(CONFIG_STM32H7_SPI_SLAVE_QSIZE)] +uint8_t SPI_SLAVE_OUTQ(5)[DMA_ALIGN_UP(CONFIG_STM32_SPI_SLAVE_QSIZE)] aligned_data(ARMV7M_DCACHE_LINESIZE); static -uint8_t SPI_SLAVE_INQ(5)[DMA_ALIGN_UP(CONFIG_STM32H7_SPI_SLAVE_QSIZE)] +uint8_t SPI_SLAVE_INQ(5)[DMA_ALIGN_UP(CONFIG_STM32_SPI_SLAVE_QSIZE)] aligned_data(ARMV7M_DCACHE_LINESIZE); static struct stm32_spidev_s g_spi5ctrlr = SPI_SLAVE_INIT(5); #endif -#ifdef CONFIG_STM32H7_SPI6_SLAVE +#ifdef CONFIG_STM32_SPI6_SLAVE /* TODO: these needs to be located in SRAM3 for SPI6 */ static -uint8_t SPI_SLAVE_OUTQ(6)[DMA_ALIGN_UP(CONFIG_STM32H7_SPI_SLAVE_QSIZE)] +uint8_t SPI_SLAVE_OUTQ(6)[DMA_ALIGN_UP(CONFIG_STM32_SPI_SLAVE_QSIZE)] aligned_data(ARMV7M_DCACHE_LINESIZE); static -uint8_t SPI_SLAVE_INQ(6)[DMA_ALIGN_UP(CONFIG_STM32H7_SPI_SLAVE_QSIZE)] +uint8_t SPI_SLAVE_INQ(6)[DMA_ALIGN_UP(CONFIG_STM32_SPI_SLAVE_QSIZE)] aligned_data(ARMV7M_DCACHE_LINESIZE); static struct stm32_spidev_s g_spi6ctrlr = SPI_SLAVE_INIT(6); @@ -706,7 +706,7 @@ static inline bool spi_9to16bitmode(struct stm32_spidev_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32H7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_dmarxcallback(DMA_HANDLE handle, uint8_t isr, void *arg) { struct stm32_spidev_s *priv = (struct stm32_spidev_s *)arg; @@ -726,7 +726,7 @@ static void spi_dmarxcallback(DMA_HANDLE handle, uint8_t isr, void *arg) * ****************************************************************************/ -#ifdef CONFIG_STM32H7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_dmatxcallback(DMA_HANDLE handle, uint8_t isr, void *arg) { struct stm32_spidev_s *priv = (struct stm32_spidev_s *)arg; @@ -746,7 +746,7 @@ static void spi_dmatxcallback(DMA_HANDLE handle, uint8_t isr, void *arg) * ****************************************************************************/ -#ifdef CONFIG_STM32H7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_dmarxsetup(struct stm32_spidev_s *priv, size_t nwords) { stm32_dmacfg_t dmacfg; @@ -779,7 +779,7 @@ static void spi_dmarxsetup(struct stm32_spidev_s *priv, size_t nwords) dmacfg.paddr = priv->spibase + STM32_SPI_RXDR_OFFSET; dmacfg.maddr = (uint32_t)priv->inq; - dmacfg.ndata = CONFIG_STM32H7_SPI_SLAVE_QSIZE; + dmacfg.ndata = CONFIG_STM32_SPI_SLAVE_QSIZE; dmacfg.cfg1 = priv->rxccr; dmacfg.cfg2 = 0; @@ -795,7 +795,7 @@ static void spi_dmarxsetup(struct stm32_spidev_s *priv, size_t nwords) * ****************************************************************************/ -#ifdef CONFIG_STM32H7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_dmatxsetup(struct stm32_spidev_s *priv, size_t nwords) { /* TODO: set up dma to transfer out the new data from priv->outq, @@ -850,7 +850,7 @@ static void spi_dmatxsetup(struct stm32_spidev_s *priv, size_t nwords) * ****************************************************************************/ -#ifdef CONFIG_STM32H7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_dmarxstart(struct stm32_spidev_s *priv) { /* Can't receive in tx only mode */ @@ -875,7 +875,7 @@ static void spi_dmarxstart(struct stm32_spidev_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32H7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_dmatxstart(struct stm32_spidev_s *priv) { /* Can't transmit in rx only mode */ @@ -1129,7 +1129,7 @@ static void spi_bind(struct spi_slave_ctrlr_s *ctrlr, /* invalidate the whole rx buffer */ up_flush_dcache((uintptr_t)priv->inq, - (uintptr_t)priv->inq + CONFIG_STM32H7_SPI_SLAVE_QSIZE); + (uintptr_t)priv->inq + CONFIG_STM32_SPI_SLAVE_QSIZE); /* Bind the SPI slave device interface instance to the SPI slave * controller interface. @@ -1223,7 +1223,7 @@ static int spi_nssinterrupt(int irq, void *context, void *arg) spi_enable(priv, false); -#ifdef CONFIG_STM32H7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA /* Setup DMAs */ @@ -1363,7 +1363,7 @@ static void spi_qflush(struct spi_slave_ctrlr_s *ctrlr) DEBUGASSERT(priv != NULL && priv->dev != NULL); -#ifdef CONFIG_STM32H7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA if (!priv->dmarunning) { return; @@ -1377,9 +1377,9 @@ static void spi_qflush(struct spi_slave_ctrlr_s *ctrlr) /* Flush the input buffers */ -#ifdef CONFIG_STM32H7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA priv->ihead = - CONFIG_STM32H7_SPI_SLAVE_QSIZE - stm32_dmaresidual(priv->rxdma); + CONFIG_STM32_SPI_SLAVE_QSIZE - stm32_dmaresidual(priv->rxdma); #else priv->ihead = 0; priv->itail = 0; @@ -1415,11 +1415,11 @@ static inline int spi_rx_buffer_free(uint8_t *ptr, int start, int end) * returns garbage */ - if (end >= CONFIG_STM32H7_SPI_SLAVE_QSIZE) + if (end >= CONFIG_STM32_SPI_SLAVE_QSIZE) { end = 0; up_invalidate_dcache((uintptr_t)&ptr[start], - (uintptr_t)&ptr[CONFIG_STM32H7_SPI_SLAVE_QSIZE]); + (uintptr_t)&ptr[CONFIG_STM32_SPI_SLAVE_QSIZE]); } else { @@ -1452,9 +1452,9 @@ static size_t spi_qpoll(struct spi_slave_ctrlr_s *ctrlr) uint16_t bytes_left; DEBUGASSERT(priv != NULL && priv->dev != NULL); - DEBUGASSERT(priv->ihead < CONFIG_STM32H7_SPI_SLAVE_QSIZE); + DEBUGASSERT(priv->ihead < CONFIG_STM32_SPI_SLAVE_QSIZE); -#ifdef CONFIG_STM32H7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA if (!priv->dmarunning) { return 0; @@ -1465,8 +1465,8 @@ static size_t spi_qpoll(struct spi_slave_ctrlr_s *ctrlr) spi_lock(ctrlr, true); -#ifdef CONFIG_STM32H7_SPI_DMA - itail = CONFIG_STM32H7_SPI_SLAVE_QSIZE - stm32_dmaresidual(priv->rxdma); +#ifdef CONFIG_STM32_SPI_DMA + itail = CONFIG_STM32_SPI_SLAVE_QSIZE - stm32_dmaresidual(priv->rxdma); #else #error Support only simplex mode rx with dma #endif @@ -1480,7 +1480,7 @@ static size_t spi_qpoll(struct spi_slave_ctrlr_s *ctrlr) priv->ihead += SPIS_DEV_RECEIVE(priv->dev, (const uint16_t *)&priv->inq[ihead], - CONFIG_STM32H7_SPI_SLAVE_QSIZE - + CONFIG_STM32_SPI_SLAVE_QSIZE - ihead); /* Invalidate dcache and wrap around the priv->ihead */ @@ -1505,7 +1505,7 @@ static size_t spi_qpoll(struct spi_slave_ctrlr_s *ctrlr) /* Calculate the number of bytes left in the buffer */ bytes_left = itail < priv->ihead - ? CONFIG_STM32H7_SPI_SLAVE_QSIZE - priv->ihead + itail + ? CONFIG_STM32_SPI_SLAVE_QSIZE - priv->ihead + itail : itail - priv->ihead; spi_lock(ctrlr, false); @@ -1657,7 +1657,7 @@ static void spi_slave_initialize(struct stm32_spidev_s *priv) spi_putreg(priv, STM32_SPI_CRCPOLY_OFFSET, 7); -#ifdef CONFIG_STM32H7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA /* DMA will be started in the interrupt handler, synchronized to the master * nss */ @@ -1735,7 +1735,7 @@ struct spi_slave_ctrlr_s *stm32_spi_slave_initialize(int bus) struct stm32_spidev_s *priv = NULL; irqstate_t flags = enter_critical_section(); -#ifdef CONFIG_STM32H7_SPI1_SLAVE +#ifdef CONFIG_STM32_SPI1_SLAVE if (bus == 1) { SPI_SLAVE_INIT_BUS(1); @@ -1743,7 +1743,7 @@ struct spi_slave_ctrlr_s *stm32_spi_slave_initialize(int bus) else #endif -#ifdef CONFIG_STM32H7_SPI2_SLAVE +#ifdef CONFIG_STM32_SPI2_SLAVE if (bus == 2) { SPI_SLAVE_INIT_BUS(2); @@ -1751,7 +1751,7 @@ struct spi_slave_ctrlr_s *stm32_spi_slave_initialize(int bus) else #endif -#ifdef CONFIG_STM32H7_SPI3_SLAVE +#ifdef CONFIG_STM32_SPI3_SLAVE if (bus == 3) { SPI_SLAVE_INIT_BUS(3); @@ -1759,7 +1759,7 @@ struct spi_slave_ctrlr_s *stm32_spi_slave_initialize(int bus) else #endif -#ifdef CONFIG_STM32H7_SPI4_SLAVE +#ifdef CONFIG_STM32_SPI4_SLAVE if (bus == 4) { SPI_SLAVE_INIT_BUS(4); @@ -1767,7 +1767,7 @@ struct spi_slave_ctrlr_s *stm32_spi_slave_initialize(int bus) else #endif -#ifdef CONFIG_STM32H7_SPI5_SLAVE +#ifdef CONFIG_STM32_SPI5_SLAVE if (bus == 5) { SPI_SLAVE_INIT_BUS(5); @@ -1775,7 +1775,7 @@ struct spi_slave_ctrlr_s *stm32_spi_slave_initialize(int bus) else #endif -#ifdef CONFIG_STM32H7_SPI6_SLAVE +#ifdef CONFIG_STM32_SPI6_SLAVE if (bus == 6) { SPI_SLAVE_INIT_BUS(6); @@ -1796,4 +1796,4 @@ struct spi_slave_ctrlr_s *stm32_spi_slave_initialize(int bus) return (struct spi_slave_ctrlr_s *)priv; } -#endif /* CONFIG_STM32H7_SPI1..6_SLAVE */ +#endif /* CONFIG_STM32_SPI1..6_SLAVE */ diff --git a/arch/arm/src/stm32h7/stm32_start.c b/arch/arm/src/stm32h7/stm32_start.c index 88d53cf8bb778..fa55412dc064b 100644 --- a/arch/arm/src/stm32h7/stm32_start.c +++ b/arch/arm/src/stm32h7/stm32_start.c @@ -195,7 +195,7 @@ void __start(void) #ifdef CONFIG_ARCH_CHIP_STM32H7_CORTEXM4 /* Wait for CM7 initialization done */ - stm32h7_waitfor_cm7(); + stm32_waitfor_cm7(); #endif /* If enabled reset the MPU */ @@ -305,11 +305,11 @@ void __start(void) #if defined(CONFIG_ARCH_STM32H7_DUALCORE) && \ defined(CONFIG_ARCH_CHIP_STM32H7_CORTEXM7) && \ - defined(CONFIG_STM32H7_CORTEXM4_ENABLED) + defined(CONFIG_STM32_CORTEXM4_ENABLED) /* Start CM4 core after clock configuration is done */ - stm32h7_start_cm4(); + stm32_start_cm4(); #endif nx_start(); diff --git a/arch/arm/src/stm32h7/stm32_tickless.c b/arch/arm/src/stm32h7/stm32_tickless.c index 1de1d5abf738a..7fb140248cb55 100644 --- a/arch/arm/src/stm32h7/stm32_tickless.c +++ b/arch/arm/src/stm32h7/stm32_tickless.c @@ -89,23 +89,23 @@ #undef HAVE_32BIT_TICKLESS -#if (CONFIG_STM32H7_TICKLESS_TIMER == 2) || \ - (CONFIG_STM32H7_TICKLESS_TIMER == 5) +#if (CONFIG_STM32_TICKLESS_TIMER == 2) || \ + (CONFIG_STM32_TICKLESS_TIMER == 5) #define HAVE_32BIT_TICKLESS 1 #endif -#if (CONFIG_STM32H7_TICKLESS_TIMER == 6) || \ - (CONFIG_STM32H7_TICKLESS_TIMER == 7) +#if (CONFIG_STM32_TICKLESS_TIMER == 6) || \ + (CONFIG_STM32_TICKLESS_TIMER == 7) # error Basic timers not supported by the tickless driver #endif -#if CONFIG_STM32H7_TICKLESS_CHANNEL == 1 +#if CONFIG_STM32_TICKLESS_CHANNEL == 1 #define DIER_CAPT_IE GTIM_DIER_CC1IE -#elif CONFIG_STM32H7_TICKLESS_CHANNEL == 2 +#elif CONFIG_STM32_TICKLESS_CHANNEL == 2 #define DIER_CAPT_IE GTIM_DIER_CC2IE -#elif CONFIG_STM32H7_TICKLESS_CHANNEL == 3 +#elif CONFIG_STM32_TICKLESS_CHANNEL == 3 #define DIER_CAPT_IE GTIM_DIER_CC3IE -#elif CONFIG_STM32H7_TICKLESS_CHANNEL == 4 +#elif CONFIG_STM32_TICKLESS_CHANNEL == 4 #define DIER_CAPT_IE GTIM_DIER_CC4IE #endif @@ -413,50 +413,50 @@ static uint64_t stm32_get_counter(void) void up_timer_initialize(void) { - switch (CONFIG_STM32H7_TICKLESS_TIMER) + switch (CONFIG_STM32_TICKLESS_TIMER) { -#ifdef CONFIG_STM32H7_TIM1 +#ifdef CONFIG_STM32_TIM1 case 1: g_tickless.base = STM32_TIM1_BASE; modifyreg32(STM32_DBGMCU_APB2FZ1, 0, DBGMCU_APB2Z1_TIM1STOP); break; #endif -#ifdef CONFIG_STM32H7_TIM2 +#ifdef CONFIG_STM32_TIM2 case 2: g_tickless.base = STM32_TIM2_BASE; modifyreg32(STM32_DBGMCU_APB1LFZ1, 0, DBGMCU_APB1L_TIM2STOP); break; #endif -#ifdef CONFIG_STM32H7_TIM3 +#ifdef CONFIG_STM32_TIM3 case 3: g_tickless.base = STM32_TIM3_BASE; modifyreg32(STM32_DBGMCU_APB1LFZ1, 0, DBGMCU_APB1L_TIM3STOP); break; #endif -#ifdef CONFIG_STM32H7_TIM4 +#ifdef CONFIG_STM32_TIM4 case 4: g_tickless.base = STM32_TIM4_BASE; modifyreg32(STM32_DBGMCU_APB1LFZ1, 0, DBGMCU_APB1L_TIM4STOP); break; #endif -#ifdef CONFIG_STM32H7_TIM5 +#ifdef CONFIG_STM32_TIM5 case 5: g_tickless.base = STM32_TIM5_BASE; modifyreg32(STM32_DBGMCU_APB1LFZ1, 0, DBGMCU_APB1L_TIM5STOP); break; #endif -#ifdef CONFIG_STM32H7_TIM8 +#ifdef CONFIG_STM32_TIM8 case 8: g_tickless.base = STM32_TIM8_BASE; modifyreg32(STM32_DBGMCU_APB2FZ1, 0, DBGMCU_APB2Z1_TIM8STOP); break; #endif -#ifdef CONFIG_STM32H7_TIM9 +#ifdef CONFIG_STM32_TIM9 case 9: g_tickless.base = STM32_TIM9_BASE; @@ -464,7 +464,7 @@ void up_timer_initialize(void) break; #endif -#ifdef CONFIG_STM32H7_TIM10 +#ifdef CONFIG_STM32_TIM10 case 10: g_tickless.base = STM32_TIM10_BASE; @@ -473,7 +473,7 @@ void up_timer_initialize(void) break; #endif -#ifdef CONFIG_STM32H7_TIM11 +#ifdef CONFIG_STM32_TIM11 case 11: g_tickless.base = STM32_TIM11_BASE; @@ -481,40 +481,40 @@ void up_timer_initialize(void) break; #endif -#ifdef CONFIG_STM32H7_TIM12 +#ifdef CONFIG_STM32_TIM12 case 12: g_tickless.base = STM32_TIM12_BASE; modifyreg32(STM32_DBGMCU_APB1LFZ1, 0, DBGMCU_APB1L_TIM12STOP); break; #endif -#ifdef CONFIG_STM32H7_TIM13 +#ifdef CONFIG_STM32_TIM13 case 13: g_tickless.base = STM32_TIM13_BASE; modifyreg32(STM32_DBGMCU_APB1LFZ1, 0, DBGMCU_APB1L_TIM13STOP); break; #endif -#ifdef CONFIG_STM32H7_TIM14 +#ifdef CONFIG_STM32_TIM14 case 14: g_tickless.base = STM32_TIM14_BASE; modifyreg32(STM32_DBGMCU_APB1LFZ1, 0, DBGMCU_APB1L_TIM14STOP); break; #endif -#ifdef CONFIG_STM32H7_TIM15 +#ifdef CONFIG_STM32_TIM15 case 15: g_tickless.base = STM32_TIM15_BASE; modifyreg32(STM32_DBGMCU_APB2FZ1, 0, DBGMCU_APB2Z1_TIM15STOP); break; #endif -#ifdef CONFIG_STM32H7_TIM16 +#ifdef CONFIG_STM32_TIM16 case 16: g_tickless.base = STM32_TIM16_BASE; modifyreg32(STM32_DBGMCU_APB2FZ1, 0, DBGMCU_APB2Z1_TIM16STOP); break; #endif -#ifdef CONFIG_STM32H7_TIM17 +#ifdef CONFIG_STM32_TIM17 case 17: g_tickless.base = STM32_TIM17_BASE; modifyreg32(STM32_DBGMCU_APB2FZ1, 0, DBGMCU_APB2Z1_TIM17STOP); @@ -528,8 +528,8 @@ void up_timer_initialize(void) /* Get the TC frequency that corresponds to the requested resolution */ g_tickless.frequency = USEC_PER_SEC / (uint32_t)CONFIG_USEC_PER_TICK; - g_tickless.timer = CONFIG_STM32H7_TICKLESS_TIMER; - g_tickless.channel = CONFIG_STM32H7_TICKLESS_CHANNEL; + g_tickless.timer = CONFIG_STM32_TICKLESS_TIMER; + g_tickless.channel = CONFIG_STM32_TICKLESS_CHANNEL; g_tickless.pending = false; g_tickless.period = 0; g_tickless.overflow = 0; @@ -1001,10 +1001,10 @@ int up_alarm_start(const struct timespec *ts) flags = enter_critical_section(); - STM32_TIM_SETCOMPARE(g_tickless.tch, CONFIG_STM32H7_TICKLESS_CHANNEL, tm); + STM32_TIM_SETCOMPARE(g_tickless.tch, CONFIG_STM32_TICKLESS_CHANNEL, tm); stm32_tickless_ackint(g_tickless.channel); - stm32_tickless_enableint(CONFIG_STM32H7_TICKLESS_CHANNEL); + stm32_tickless_enableint(CONFIG_STM32_TICKLESS_CHANNEL); g_tickless.pending = true; @@ -1021,7 +1021,7 @@ int up_alarm_start(const struct timespec *ts) while (tm <= stm32_get_counter()) { tm = stm32_get_counter() + offset++; - STM32_TIM_SETCOMPARE(g_tickless.tch, CONFIG_STM32H7_TICKLESS_CHANNEL, + STM32_TIM_SETCOMPARE(g_tickless.tch, CONFIG_STM32_TICKLESS_CHANNEL, tm); } @@ -1042,7 +1042,7 @@ int up_alarm_cancel(struct timespec *ts) ts->tv_sec = nsecs / NSEC_PER_SEC; ts->tv_nsec = nsecs - ts->tv_sec * NSEC_PER_SEC; - stm32_tickless_disableint(CONFIG_STM32H7_TICKLESS_CHANNEL); + stm32_tickless_disableint(CONFIG_STM32_TICKLESS_CHANNEL); return 0; } diff --git a/arch/arm/src/stm32h7/stm32_tim.c b/arch/arm/src/stm32h7/stm32_tim.c index 4b04b9a9f24f2..4fe8974731987 100644 --- a/arch/arm/src/stm32h7/stm32_tim.c +++ b/arch/arm/src/stm32h7/stm32_tim.c @@ -53,96 +53,96 @@ * include: * * - To generate modulated outputs for such things as motor control. If - * CONFIG_STM32H7_TIMn is defined then the CONFIG_STM32H7_TIMn_PWM may + * CONFIG_STM32_TIMn is defined then the CONFIG_STM32_TIMn_PWM may * also be defined to indicate that the timer is intended to be used for * pulsed output modulation. * - * - To control periodic ADC input sampling. If CONFIG_STM32H7_TIMn is - * defined then CONFIG_STM32H7_TIMn_ADC may also be defined to indicate + * - To control periodic ADC input sampling. If CONFIG_STM32_TIMn is + * defined then CONFIG_STM32_TIMn_ADC may also be defined to indicate * that timer "n" is intended to be used for that purpose. * - * - To control periodic DAC outputs. If CONFIG_STM32H7_TIMn is defined - * then CONFIG_STM32H7_TIMn_DAC may also be defined to indicate that + * - To control periodic DAC outputs. If CONFIG_STM32_TIMn is defined + * then CONFIG_STM32_TIMn_DAC may also be defined to indicate that * timer "n" is intended to be used for that purpose. * - * - To use a Quadrature Encoder. If CONFIG_STM32H7_TIMn is defined then - * CONFIG_STM32H7_TIMn_QE may also be defined to indicate that timer "n" + * - To use a Quadrature Encoder. If CONFIG_STM32_TIMn is defined then + * CONFIG_STM32_TIMn_QE may also be defined to indicate that timer "n" * is intended to be used for that purpose. * * In any of these cases, the timer will not be used by this timer module. */ -#if defined(CONFIG_STM32H7_TIM1_PWM) || defined (CONFIG_STM32H7_TIM1_ADC) || \ - defined(CONFIG_STM32H7_TIM1_DAC) || defined(CONFIG_STM32H7_TIM1_QE) -# undef CONFIG_STM32H7_TIM1 +#if defined(CONFIG_STM32_TIM1_PWM) || defined (CONFIG_STM32_TIM1_ADC) || \ + defined(CONFIG_STM32_TIM1_DAC) || defined(CONFIG_STM32_TIM1_QE) +# undef CONFIG_STM32_TIM1 #endif -#if defined(CONFIG_STM32H7_TIM2_PWM) || defined (CONFIG_STM32H7_TIM2_ADC) || \ - defined(CONFIG_STM32H7_TIM2_DAC) || defined(CONFIG_STM32H7_TIM2_QE) -# undef CONFIG_STM32H7_TIM2 +#if defined(CONFIG_STM32_TIM2_PWM) || defined (CONFIG_STM32_TIM2_ADC) || \ + defined(CONFIG_STM32_TIM2_DAC) || defined(CONFIG_STM32_TIM2_QE) +# undef CONFIG_STM32_TIM2 #endif -#if defined(CONFIG_STM32H7_TIM3_PWM) || defined (CONFIG_STM32H7_TIM3_ADC) || \ - defined(CONFIG_STM32H7_TIM3_DAC) || defined(CONFIG_STM32H7_TIM3_QE) -# undef CONFIG_STM32H7_TIM3 +#if defined(CONFIG_STM32_TIM3_PWM) || defined (CONFIG_STM32_TIM3_ADC) || \ + defined(CONFIG_STM32_TIM3_DAC) || defined(CONFIG_STM32_TIM3_QE) +# undef CONFIG_STM32_TIM3 #endif -#if defined(CONFIG_STM32H7_TIM4_PWM) || defined (CONFIG_STM32H7_TIM4_ADC) || \ - defined(CONFIG_STM32H7_TIM4_DAC) || defined(CONFIG_STM32H7_TIM4_QE) -# undef CONFIG_STM32H7_TIM4 +#if defined(CONFIG_STM32_TIM4_PWM) || defined (CONFIG_STM32_TIM4_ADC) || \ + defined(CONFIG_STM32_TIM4_DAC) || defined(CONFIG_STM32_TIM4_QE) +# undef CONFIG_STM32_TIM4 #endif -#if defined(CONFIG_STM32H7_TIM5_PWM) || defined (CONFIG_STM32H7_TIM5_ADC) || \ - defined(CONFIG_STM32H7_TIM5_DAC) || defined(CONFIG_STM32H7_TIM5_QE) -# undef CONFIG_STM32H7_TIM5 +#if defined(CONFIG_STM32_TIM5_PWM) || defined (CONFIG_STM32_TIM5_ADC) || \ + defined(CONFIG_STM32_TIM5_DAC) || defined(CONFIG_STM32_TIM5_QE) +# undef CONFIG_STM32_TIM5 #endif -#if defined(CONFIG_STM32H7_TIM6_PWM) || defined (CONFIG_STM32H7_TIM6_ADC) || \ - defined(CONFIG_STM32H7_TIM6_DAC) || defined(CONFIG_STM32H7_TIM6_QE) -# undef CONFIG_STM32H7_TIM6 +#if defined(CONFIG_STM32_TIM6_PWM) || defined (CONFIG_STM32_TIM6_ADC) || \ + defined(CONFIG_STM32_TIM6_DAC) || defined(CONFIG_STM32_TIM6_QE) +# undef CONFIG_STM32_TIM6 #endif -#if defined(CONFIG_STM32H7_TIM7_PWM) || defined (CONFIG_STM32H7_TIM7_ADC) || \ - defined(CONFIG_STM32H7_TIM7_DAC) || defined(CONFIG_STM32H7_TIM7_QE) -# undef CONFIG_STM32H7_TIM7 +#if defined(CONFIG_STM32_TIM7_PWM) || defined (CONFIG_STM32_TIM7_ADC) || \ + defined(CONFIG_STM32_TIM7_DAC) || defined(CONFIG_STM32_TIM7_QE) +# undef CONFIG_STM32_TIM7 #endif -#if defined(CONFIG_STM32H7_TIM8_PWM) || defined (CONFIG_STM32H7_TIM8_ADC) || \ - defined(CONFIG_STM32H7_TIM8_DAC) || defined(CONFIG_STM32H7_TIM8_QE) -# undef CONFIG_STM32H7_TIM8 +#if defined(CONFIG_STM32_TIM8_PWM) || defined (CONFIG_STM32_TIM8_ADC) || \ + defined(CONFIG_STM32_TIM8_DAC) || defined(CONFIG_STM32_TIM8_QE) +# undef CONFIG_STM32_TIM8 #endif -#if defined(CONFIG_STM32H7_TIM12_PWM) || defined (CONFIG_STM32H7_TIM12_ADC) || \ - defined(CONFIG_STM32H7_TIM12_DAC) || defined(CONFIG_STM32H7_TIM12_QE) -# undef CONFIG_STM32H7_TIM12 +#if defined(CONFIG_STM32_TIM12_PWM) || defined (CONFIG_STM32_TIM12_ADC) || \ + defined(CONFIG_STM32_TIM12_DAC) || defined(CONFIG_STM32_TIM12_QE) +# undef CONFIG_STM32_TIM12 #endif -#if defined(CONFIG_STM32H7_TIM13_PWM) || defined (CONFIG_STM32H7_TIM13_ADC) || \ - defined(CONFIG_STM32H7_TIM13_DAC) || defined(CONFIG_STM32H7_TIM13_QE) -# undef CONFIG_STM32H7_TIM13 +#if defined(CONFIG_STM32_TIM13_PWM) || defined (CONFIG_STM32_TIM13_ADC) || \ + defined(CONFIG_STM32_TIM13_DAC) || defined(CONFIG_STM32_TIM13_QE) +# undef CONFIG_STM32_TIM13 #endif -#if defined(CONFIG_STM32H7_TIM14_PWM) || defined (CONFIG_STM32H7_TIM14_ADC) || \ - defined(CONFIG_STM32H7_TIM14_DAC) || defined(CONFIG_STM32H7_TIM14_QE) -# undef CONFIG_STM32H7_TIM14 +#if defined(CONFIG_STM32_TIM14_PWM) || defined (CONFIG_STM32_TIM14_ADC) || \ + defined(CONFIG_STM32_TIM14_DAC) || defined(CONFIG_STM32_TIM14_QE) +# undef CONFIG_STM32_TIM14 #endif -#if defined(CONFIG_STM32H7_TIM15_PWM) || defined (CONFIG_STM32H7_TIM15_ADC) || \ - defined(CONFIG_STM32H7_TIM15_DAC) || defined(CONFIG_STM32H7_TIM15_QE) -# undef CONFIG_STM32H7_TIM15 +#if defined(CONFIG_STM32_TIM15_PWM) || defined (CONFIG_STM32_TIM15_ADC) || \ + defined(CONFIG_STM32_TIM15_DAC) || defined(CONFIG_STM32_TIM15_QE) +# undef CONFIG_STM32_TIM15 #endif -#if defined(CONFIG_STM32H7_TIM16_PWM) || defined (CONFIG_STM32H7_TIM16_ADC) || \ - defined(CONFIG_STM32H7_TIM16_DAC) || defined(CONFIG_STM32H7_TIM16_QE) -# undef CONFIG_STM32H7_TIM16 +#if defined(CONFIG_STM32_TIM16_PWM) || defined (CONFIG_STM32_TIM16_ADC) || \ + defined(CONFIG_STM32_TIM16_DAC) || defined(CONFIG_STM32_TIM16_QE) +# undef CONFIG_STM32_TIM16 #endif -#if defined(CONFIG_STM32H7_TIM17_PWM) || defined (CONFIG_STM32H7_TIM17_ADC) || \ - defined(CONFIG_STM32H7_TIM17_DAC) || defined(CONFIG_STM32H7_TIM17_QE) -# undef CONFIG_STM32H7_TIM17 +#if defined(CONFIG_STM32_TIM17_PWM) || defined (CONFIG_STM32_TIM17_ADC) || \ + defined(CONFIG_STM32_TIM17_DAC) || defined(CONFIG_STM32_TIM17_QE) +# undef CONFIG_STM32_TIM17 #endif -#if defined(CONFIG_STM32H7_TIM1) +#if defined(CONFIG_STM32_TIM1) # if defined(GPIO_TIM1_CH1OUT) ||defined(GPIO_TIM1_CH2OUT)||\ defined(GPIO_TIM1_CH3OUT) ||defined(GPIO_TIM1_CH4OUT)||\ defined(GPIO_TIM1_CH5OUT) ||defined(GPIO_TIM1_CH6OUT) @@ -150,35 +150,35 @@ # endif #endif -#if defined(CONFIG_STM32H7_TIM2) +#if defined(CONFIG_STM32_TIM2) # if defined(GPIO_TIM2_CH1OUT) ||defined(GPIO_TIM2_CH2OUT)||\ defined(GPIO_TIM2_CH3OUT) ||defined(GPIO_TIM2_CH4OUT) # define HAVE_TIM2_GPIOCONFIG 1 # endif #endif -#if defined(CONFIG_STM32H7_TIM3) +#if defined(CONFIG_STM32_TIM3) # if defined(GPIO_TIM3_CH1OUT) ||defined(GPIO_TIM3_CH2OUT)||\ defined(GPIO_TIM3_CH3OUT) ||defined(GPIO_TIM3_CH4OUT) # define HAVE_TIM3_GPIOCONFIG 1 # endif #endif -#if defined(CONFIG_STM32H7_TIM4) +#if defined(CONFIG_STM32_TIM4) # if defined(GPIO_TIM4_CH1OUT) ||defined(GPIO_TIM4_CH2OUT)||\ defined(GPIO_TIM4_CH3OUT) ||defined(GPIO_TIM4_CH4OUT) # define HAVE_TIM4_GPIOCONFIG 1 # endif #endif -#if defined(CONFIG_STM32H7_TIM5) +#if defined(CONFIG_STM32_TIM5) # if defined(GPIO_TIM5_CH1OUT) ||defined(GPIO_TIM5_CH2OUT)||\ defined(GPIO_TIM5_CH3OUT) ||defined(GPIO_TIM5_CH4OUT) # define HAVE_TIM5_GPIOCONFIG 1 # endif #endif -#if defined(CONFIG_STM32H7_TIM8) +#if defined(CONFIG_STM32_TIM8) # if defined(GPIO_TIM8_CH1OUT) ||defined(GPIO_TIM8_CH2OUT)||\ defined(GPIO_TIM8_CH3OUT) ||defined(GPIO_TIM8_CH4OUT)||\ defined(GPIO_TIM8_CH5OUT) ||defined(GPIO_TIM8_CH6OUT) @@ -186,37 +186,37 @@ # endif #endif -#if defined(CONFIG_STM32H7_TIM12) +#if defined(CONFIG_STM32_TIM12) # if defined(GPIO_TIM12_CH1OUT) ||defined(GPIO_TIM12_CH2OUT) # define HAVE_TIM12_GPIOCONFIG 1 # endif #endif -#if defined(CONFIG_STM32H7_TIM13) +#if defined(CONFIG_STM32_TIM13) # if defined(GPIO_TIM13_CH1OUT) # define HAVE_TIM13_GPIOCONFIG 1 # endif #endif -#if defined(CONFIG_STM32H7_TIM14) +#if defined(CONFIG_STM32_TIM14) # if defined(GPIO_TIM14_CH1OUT) # define HAVE_TIM14_GPIOCONFIG 1 # endif #endif -#if defined(CONFIG_STM32H7_TIM15) +#if defined(CONFIG_STM32_TIM15) # if defined(GPIO_TIM15_CH1OUT) ||defined(GPIO_TIM15_CH2OUT) # define HAVE_TIM15_GPIOCONFIG 1 # endif #endif -#if defined(CONFIG_STM32H7_TIM16) +#if defined(CONFIG_STM32_TIM16) # if defined(GPIO_TIM16_CH1OUT) # define HAVE_TIM16_GPIOCONFIG 1 # endif #endif -#if defined(CONFIG_STM32H7_TIM17) +#if defined(CONFIG_STM32_TIM17) # if defined(GPIO_TIM17_CH1OUT) # define HAVE_TIM17_GPIOCONFIG 1 # endif @@ -226,13 +226,13 @@ * intended for some other purpose. */ -#if defined(CONFIG_STM32H7_TIM1) || defined(CONFIG_STM32H7_TIM2) || \ - defined(CONFIG_STM32H7_TIM3) || defined(CONFIG_STM32H7_TIM4) || \ - defined(CONFIG_STM32H7_TIM5) || defined(CONFIG_STM32H7_TIM6) || \ - defined(CONFIG_STM32H7_TIM7) || defined(CONFIG_STM32H7_TIM8) || \ - defined(CONFIG_STM32H7_TIM12) || defined(CONFIG_STM32H7_TIM13) || \ - defined(CONFIG_STM32H7_TIM14) || defined(CONFIG_STM32H7_TIM15) || \ - defined(CONFIG_STM32H7_TIM16) || defined(CONFIG_STM32H7_TIM17) +#if defined(CONFIG_STM32_TIM1) || defined(CONFIG_STM32_TIM2) || \ + defined(CONFIG_STM32_TIM3) || defined(CONFIG_STM32_TIM4) || \ + defined(CONFIG_STM32_TIM5) || defined(CONFIG_STM32_TIM6) || \ + defined(CONFIG_STM32_TIM7) || defined(CONFIG_STM32_TIM8) || \ + defined(CONFIG_STM32_TIM12) || defined(CONFIG_STM32_TIM13) || \ + defined(CONFIG_STM32_TIM14) || defined(CONFIG_STM32_TIM15) || \ + defined(CONFIG_STM32_TIM16) || defined(CONFIG_STM32_TIM17) /**************************************************************************** * Private Types @@ -312,7 +312,7 @@ static const struct stm32_tim_ops_s stm32_tim_ops = .checkint = &stm32_tim_checkint, }; -#ifdef CONFIG_STM32H7_TIM1 +#ifdef CONFIG_STM32_TIM1 struct stm32_tim_priv_s stm32_tim1_priv = { .ops = &stm32_tim_ops, @@ -320,7 +320,7 @@ struct stm32_tim_priv_s stm32_tim1_priv = .base = STM32_TIM1_BASE, }; #endif -#ifdef CONFIG_STM32H7_TIM2 +#ifdef CONFIG_STM32_TIM2 struct stm32_tim_priv_s stm32_tim2_priv = { .ops = &stm32_tim_ops, @@ -329,7 +329,7 @@ struct stm32_tim_priv_s stm32_tim2_priv = }; #endif -#ifdef CONFIG_STM32H7_TIM3 +#ifdef CONFIG_STM32_TIM3 struct stm32_tim_priv_s stm32_tim3_priv = { .ops = &stm32_tim_ops, @@ -338,7 +338,7 @@ struct stm32_tim_priv_s stm32_tim3_priv = }; #endif -#ifdef CONFIG_STM32H7_TIM4 +#ifdef CONFIG_STM32_TIM4 struct stm32_tim_priv_s stm32_tim4_priv = { .ops = &stm32_tim_ops, @@ -347,7 +347,7 @@ struct stm32_tim_priv_s stm32_tim4_priv = }; #endif -#ifdef CONFIG_STM32H7_TIM5 +#ifdef CONFIG_STM32_TIM5 struct stm32_tim_priv_s stm32_tim5_priv = { .ops = &stm32_tim_ops, @@ -356,7 +356,7 @@ struct stm32_tim_priv_s stm32_tim5_priv = }; #endif -#ifdef CONFIG_STM32H7_TIM6 +#ifdef CONFIG_STM32_TIM6 struct stm32_tim_priv_s stm32_tim6_priv = { .ops = &stm32_tim_ops, @@ -365,7 +365,7 @@ struct stm32_tim_priv_s stm32_tim6_priv = }; #endif -#ifdef CONFIG_STM32H7_TIM7 +#ifdef CONFIG_STM32_TIM7 struct stm32_tim_priv_s stm32_tim7_priv = { .ops = &stm32_tim_ops, @@ -374,7 +374,7 @@ struct stm32_tim_priv_s stm32_tim7_priv = }; #endif -#ifdef CONFIG_STM32H7_TIM8 +#ifdef CONFIG_STM32_TIM8 struct stm32_tim_priv_s stm32_tim8_priv = { .ops = &stm32_tim_ops, @@ -383,7 +383,7 @@ struct stm32_tim_priv_s stm32_tim8_priv = }; #endif -#ifdef CONFIG_STM32H7_TIM12 +#ifdef CONFIG_STM32_TIM12 struct stm32_tim_priv_s stm32_tim12_priv = { .ops = &stm32_tim_ops, @@ -392,7 +392,7 @@ struct stm32_tim_priv_s stm32_tim12_priv = }; #endif -#ifdef CONFIG_STM32H7_TIM13 +#ifdef CONFIG_STM32_TIM13 struct stm32_tim_priv_s stm32_tim13_priv = { .ops = &stm32_tim_ops, @@ -401,7 +401,7 @@ struct stm32_tim_priv_s stm32_tim13_priv = }; #endif -#ifdef CONFIG_STM32H7_TIM14 +#ifdef CONFIG_STM32_TIM14 struct stm32_tim_priv_s stm32_tim14_priv = { .ops = &stm32_tim_ops, @@ -410,7 +410,7 @@ struct stm32_tim_priv_s stm32_tim14_priv = }; #endif -#ifdef CONFIG_STM32H7_TIM15 +#ifdef CONFIG_STM32_TIM15 struct stm32_tim_priv_s stm32_tim15_priv = { .ops = &stm32_tim_ops, @@ -419,7 +419,7 @@ struct stm32_tim_priv_s stm32_tim15_priv = }; #endif -#ifdef CONFIG_STM32H7_TIM16 +#ifdef CONFIG_STM32_TIM16 struct stm32_tim_priv_s stm32_tim16_priv = { .ops = &stm32_tim_ops, @@ -428,7 +428,7 @@ struct stm32_tim_priv_s stm32_tim16_priv = }; #endif -#ifdef CONFIG_STM32H7_TIM17 +#ifdef CONFIG_STM32_TIM17 struct stm32_tim_priv_s stm32_tim17_priv = { .ops = &stm32_tim_ops, @@ -519,12 +519,12 @@ static int stm32_tim_getwidth(struct stm32_tim_dev_s *dev) switch (((struct stm32_tim_priv_s *)dev)->base) { -#if defined(CONFIG_STM32H7_TIM2) +#if defined(CONFIG_STM32_TIM2) case STM32_TIM2_BASE: return 32; #endif -#if defined(CONFIG_STM32H7_TIM5) +#if defined(CONFIG_STM32_TIM5) case STM32_TIM5_BASE: return 32; #endif @@ -626,72 +626,72 @@ static int stm32_tim_setclock(struct stm32_tim_dev_s *dev, uint32_t freq) switch (((struct stm32_tim_priv_s *)dev)->base) { -#ifdef CONFIG_STM32H7_TIM1 +#ifdef CONFIG_STM32_TIM1 case STM32_TIM1_BASE: freqin = STM32_APB2_TIM1_CLKIN; break; #endif -#ifdef CONFIG_STM32H7_TIM2 +#ifdef CONFIG_STM32_TIM2 case STM32_TIM2_BASE: freqin = STM32_APB1_TIM2_CLKIN; break; #endif -#ifdef CONFIG_STM32H7_TIM3 +#ifdef CONFIG_STM32_TIM3 case STM32_TIM3_BASE: freqin = STM32_APB1_TIM3_CLKIN; break; #endif -#ifdef CONFIG_STM32H7_TIM4 +#ifdef CONFIG_STM32_TIM4 case STM32_TIM4_BASE: freqin = STM32_APB1_TIM4_CLKIN; break; #endif -#ifdef CONFIG_STM32H7_TIM5 +#ifdef CONFIG_STM32_TIM5 case STM32_TIM5_BASE: freqin = STM32_APB1_TIM5_CLKIN; break; #endif -#ifdef CONFIG_STM32H7_TIM6 +#ifdef CONFIG_STM32_TIM6 case STM32_TIM6_BASE: freqin = STM32_APB1_TIM6_CLKIN; break; #endif -#ifdef CONFIG_STM32H7_TIM7 +#ifdef CONFIG_STM32_TIM7 case STM32_TIM7_BASE: freqin = STM32_APB1_TIM7_CLKIN; break; #endif -#ifdef CONFIG_STM32H7_TIM8 +#ifdef CONFIG_STM32_TIM8 case STM32_TIM8_BASE: freqin = STM32_APB2_TIM8_CLKIN; break; #endif -#ifdef CONFIG_STM32H7_TIM12 +#ifdef CONFIG_STM32_TIM12 case STM32_TIM12_BASE: freqin = STM32_APB1_TIM12_CLKIN; break; #endif -#ifdef CONFIG_STM32H7_TIM13 +#ifdef CONFIG_STM32_TIM13 case STM32_TIM13_BASE: freqin = STM32_APB1_TIM13_CLKIN; break; #endif -#ifdef CONFIG_STM32H7_TIM14 +#ifdef CONFIG_STM32_TIM14 case STM32_TIM14_BASE: freqin = STM32_APB1_TIM14_CLKIN; break; #endif -#ifdef CONFIG_STM32H7_TIM15 +#ifdef CONFIG_STM32_TIM15 case STM32_TIM15_BASE: freqin = STM32_APB2_TIM15_CLKIN; break; #endif -#ifdef CONFIG_STM32H7_TIM16 +#ifdef CONFIG_STM32_TIM16 case STM32_TIM16_BASE: freqin = STM32_APB2_TIM16_CLKIN; break; #endif -#ifdef CONFIG_STM32H7_TIM17 +#ifdef CONFIG_STM32_TIM17 case STM32_TIM17_BASE: freqin = STM32_APB2_TIM17_CLKIN; break; @@ -745,72 +745,72 @@ static int stm32_tim_setisr(struct stm32_tim_dev_s *dev, switch (((struct stm32_tim_priv_s *)dev)->base) { -#ifdef CONFIG_STM32H7_TIM1 +#ifdef CONFIG_STM32_TIM1 case STM32_TIM1_BASE: vectorno = STM32_IRQ_TIM1UP; break; #endif -#ifdef CONFIG_STM32H7_TIM2 +#ifdef CONFIG_STM32_TIM2 case STM32_TIM2_BASE: vectorno = STM32_IRQ_TIM2; break; #endif -#ifdef CONFIG_STM32H7_TIM3 +#ifdef CONFIG_STM32_TIM3 case STM32_TIM3_BASE: vectorno = STM32_IRQ_TIM3; break; #endif -#ifdef CONFIG_STM32H7_TIM4 +#ifdef CONFIG_STM32_TIM4 case STM32_TIM4_BASE: vectorno = STM32_IRQ_TIM4; break; #endif -#ifdef CONFIG_STM32H7_TIM5 +#ifdef CONFIG_STM32_TIM5 case STM32_TIM5_BASE: vectorno = STM32_IRQ_TIM5; break; #endif -#ifdef CONFIG_STM32H7_TIM6 +#ifdef CONFIG_STM32_TIM6 case STM32_TIM6_BASE: vectorno = STM32_IRQ_TIM6; break; #endif -#ifdef CONFIG_STM32H7_TIM7 +#ifdef CONFIG_STM32_TIM7 case STM32_TIM7_BASE: vectorno = STM32_IRQ_TIM7; break; #endif -#ifdef CONFIG_STM32H7_TIM8 +#ifdef CONFIG_STM32_TIM8 case STM32_TIM8_BASE: vectorno = STM32_IRQ_TIM8UP; break; #endif -#ifdef CONFIG_STM32H7_TIM12 +#ifdef CONFIG_STM32_TIM12 case STM32_TIM12_BASE: vectorno = STM32_IRQ_TIM12; break; #endif -#ifdef CONFIG_STM32H7_TIM13 +#ifdef CONFIG_STM32_TIM13 case STM32_TIM13_BASE: vectorno = STM32_IRQ_TIM13; break; #endif -#ifdef CONFIG_STM32H7_TIM14 +#ifdef CONFIG_STM32_TIM14 case STM32_TIM14_BASE: vectorno = STM32_IRQ_TIM14; break; #endif -#ifdef CONFIG_STM32H7_TIM15 +#ifdef CONFIG_STM32_TIM15 case STM32_TIM15_BASE: vectorno = STM32_IRQ_TIM15; break; #endif -#ifdef CONFIG_STM32H7_TIM16 +#ifdef CONFIG_STM32_TIM16 case STM32_TIM16_BASE: vectorno = STM32_IRQ_TIM16; break; #endif -#ifdef CONFIG_STM32H7_TIM17 +#ifdef CONFIG_STM32_TIM17 case STM32_TIM17_BASE: vectorno = STM32_IRQ_TIM17; break; @@ -1016,7 +1016,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, switch (((struct stm32_tim_priv_s *)dev)->base) { -#ifdef CONFIG_STM32H7_TIM1 +#ifdef CONFIG_STM32_TIM1 case STM32_TIM1_BASE: switch (channel) { @@ -1049,7 +1049,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32H7_TIM2 +#ifdef CONFIG_STM32_TIM2 case STM32_TIM2_BASE: switch (channel) { @@ -1078,7 +1078,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32H7_TIM3 +#ifdef CONFIG_STM32_TIM3 case STM32_TIM3_BASE: switch (channel) { @@ -1107,7 +1107,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32H7_TIM4 +#ifdef CONFIG_STM32_TIM4 case STM32_TIM4_BASE: switch (channel) { @@ -1136,7 +1136,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32H7_TIM5 +#ifdef CONFIG_STM32_TIM5 case STM32_TIM5_BASE: switch (channel) { @@ -1165,7 +1165,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32H7_TIM8 +#ifdef CONFIG_STM32_TIM8 case STM32_TIM8_BASE: switch (channel) { @@ -1199,7 +1199,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, break; #endif -#ifdef CONFIG_STM32H7_TIM12 +#ifdef CONFIG_STM32_TIM12 case STM32_TIM12_BASE: switch (channel) { @@ -1218,7 +1218,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32H7_TIM13 +#ifdef CONFIG_STM32_TIM13 case STM32_TIM13_BASE: switch (channel) { @@ -1232,7 +1232,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32H7_TIM14 +#ifdef CONFIG_STM32_TIM14 case STM32_TIM14_BASE: switch (channel) { @@ -1247,7 +1247,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, break; #endif -#ifdef CONFIG_STM32H7_TIM15 +#ifdef CONFIG_STM32_TIM15 case STM32_TIM15_BASE: switch (channel) { @@ -1266,7 +1266,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32H7_TIM16 +#ifdef CONFIG_STM32_TIM16 case STM32_TIM16_BASE: switch (channel) { @@ -1280,7 +1280,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32H7_TIM17 +#ifdef CONFIG_STM32_TIM17 case STM32_TIM17_BASE: switch (channel) { @@ -1364,85 +1364,85 @@ struct stm32_tim_dev_s *stm32_tim_init(int timer) switch (timer) { -#ifdef CONFIG_STM32H7_TIM1 +#ifdef CONFIG_STM32_TIM1 case 1: dev = (struct stm32_tim_dev_s *)&stm32_tim1_priv; modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM1EN); break; #endif -#ifdef CONFIG_STM32H7_TIM2 +#ifdef CONFIG_STM32_TIM2 case 2: dev = (struct stm32_tim_dev_s *)&stm32_tim2_priv; modifyreg32(STM32_RCC_APB1LENR, 0, RCC_APB1LENR_TIM2EN); break; #endif -#ifdef CONFIG_STM32H7_TIM3 +#ifdef CONFIG_STM32_TIM3 case 3: dev = (struct stm32_tim_dev_s *)&stm32_tim3_priv; modifyreg32(STM32_RCC_APB1LENR, 0, RCC_APB1LENR_TIM3EN); break; #endif -#ifdef CONFIG_STM32H7_TIM4 +#ifdef CONFIG_STM32_TIM4 case 4: dev = (struct stm32_tim_dev_s *)&stm32_tim4_priv; modifyreg32(STM32_RCC_APB1LENR, 0, RCC_APB1LENR_TIM4EN); break; #endif -#ifdef CONFIG_STM32H7_TIM5 +#ifdef CONFIG_STM32_TIM5 case 5: dev = (struct stm32_tim_dev_s *)&stm32_tim5_priv; modifyreg32(STM32_RCC_APB1LENR, 0, RCC_APB1LENR_TIM5EN); break; #endif -#ifdef CONFIG_STM32H7_TIM6 +#ifdef CONFIG_STM32_TIM6 case 6: dev = (struct stm32_tim_dev_s *)&stm32_tim6_priv; modifyreg32(STM32_RCC_APB1LENR, 0, RCC_APB1LENR_TIM6EN); break; #endif -#ifdef CONFIG_STM32H7_TIM7 +#ifdef CONFIG_STM32_TIM7 case 7: dev = (struct stm32_tim_dev_s *)&stm32_tim7_priv; modifyreg32(STM32_RCC_APB1LENR, 0, RCC_APB1LENR_TIM7EN); break; #endif -#ifdef CONFIG_STM32H7_TIM8 +#ifdef CONFIG_STM32_TIM8 case 8: dev = (struct stm32_tim_dev_s *)&stm32_tim8_priv; modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM8EN); break; #endif -#ifdef CONFIG_STM32H7_TIM12 +#ifdef CONFIG_STM32_TIM12 case 12: dev = (struct stm32_tim_dev_s *)&stm32_tim12_priv; modifyreg32(STM32_RCC_APB1LENR, 0, RCC_APB1LENR_TIM12EN); break; #endif -#ifdef CONFIG_STM32H7_TIM13 +#ifdef CONFIG_STM32_TIM13 case 13: dev = (struct stm32_tim_dev_s *)&stm32_tim13_priv; modifyreg32(STM32_RCC_APB1LENR, 0, RCC_APB1LENR_TIM13EN); break; #endif -#ifdef CONFIG_STM32H7_TIM14 +#ifdef CONFIG_STM32_TIM14 case 14: dev = (struct stm32_tim_dev_s *)&stm32_tim14_priv; modifyreg32(STM32_RCC_APB1LENR, 0, RCC_APB1LENR_TIM14EN); break; #endif -#ifdef CONFIG_STM32H7_TIM15 +#ifdef CONFIG_STM32_TIM15 case 15: dev = (struct stm32_tim_dev_s *)&stm32_tim15_priv; modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM15EN); break; #endif -#ifdef CONFIG_STM32H7_TIM16 +#ifdef CONFIG_STM32_TIM16 case 16: dev = (struct stm32_tim_dev_s *)&stm32_tim16_priv; modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM16EN); break; #endif -#ifdef CONFIG_STM32H7_TIM17 +#ifdef CONFIG_STM32_TIM17 case 17: dev = (struct stm32_tim_dev_s *)&stm32_tim17_priv; modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM17EN); @@ -1474,72 +1474,72 @@ int stm32_tim_deinit(struct stm32_tim_dev_s * dev) switch (((struct stm32_tim_priv_s *)dev)->base) { -#ifdef CONFIG_STM32H7_TIM1 +#ifdef CONFIG_STM32_TIM1 case STM32_TIM1_BASE: modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM1EN, 0); break; #endif -#ifdef CONFIG_STM32H7_TIM2 +#ifdef CONFIG_STM32_TIM2 case STM32_TIM2_BASE: modifyreg32(STM32_RCC_APB1LENR, RCC_APB1LENR_TIM2EN, 0); break; #endif -#ifdef CONFIG_STM32H7_TIM3 +#ifdef CONFIG_STM32_TIM3 case STM32_TIM3_BASE: modifyreg32(STM32_RCC_APB1LENR, RCC_APB1LENR_TIM3EN, 0); break; #endif -#ifdef CONFIG_STM32H7_TIM4 +#ifdef CONFIG_STM32_TIM4 case STM32_TIM4_BASE: modifyreg32(STM32_RCC_APB1LENR, RCC_APB1LENR_TIM4EN, 0); break; #endif -#ifdef CONFIG_STM32H7_TIM5 +#ifdef CONFIG_STM32_TIM5 case STM32_TIM5_BASE: modifyreg32(STM32_RCC_APB1LENR, RCC_APB1LENR_TIM5EN, 0); break; #endif -#ifdef CONFIG_STM32H7_TIM6 +#ifdef CONFIG_STM32_TIM6 case STM32_TIM6_BASE: modifyreg32(STM32_RCC_APB1LENR, RCC_APB1LENR_TIM6EN, 0); break; #endif -#ifdef CONFIG_STM32H7_TIM7 +#ifdef CONFIG_STM32_TIM7 case STM32_TIM7_BASE: modifyreg32(STM32_RCC_APB1LENR, RCC_APB1LENR_TIM7EN, 0); break; #endif -#ifdef CONFIG_STM32H7_TIM8 +#ifdef CONFIG_STM32_TIM8 case STM32_TIM8_BASE: modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM8EN, 0); break; #endif -#ifdef CONFIG_STM32H7_TIM12 +#ifdef CONFIG_STM32_TIM12 case STM32_TIM12_BASE: modifyreg32(STM32_RCC_APB1LENR, RCC_APB1LENR_TIM12EN, 0); break; #endif -#ifdef CONFIG_STM32H7_TIM13 +#ifdef CONFIG_STM32_TIM13 case STM32_TIM13_BASE: modifyreg32(STM32_RCC_APB1LENR, RCC_APB1LENR_TIM13EN, 0); break; #endif -#ifdef CONFIG_STM32H7_TIM14 +#ifdef CONFIG_STM32_TIM14 case STM32_TIM14_BASE: modifyreg32(STM32_RCC_APB1LENR, RCC_APB1LENR_TIM14EN, 0); break; #endif -#ifdef CONFIG_STM32H7_TIM15 +#ifdef CONFIG_STM32_TIM15 case STM32_TIM15_BASE: modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM15EN, 0); break; #endif -#ifdef CONFIG_STM32H7_TIM16 +#ifdef CONFIG_STM32_TIM16 case STM32_TIM16_BASE: modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM16EN, 0); break; #endif -#ifdef CONFIG_STM32H7_TIM17 +#ifdef CONFIG_STM32_TIM17 case STM32_TIM17_BASE: modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM17EN, 0); break; @@ -1555,4 +1555,4 @@ int stm32_tim_deinit(struct stm32_tim_dev_s * dev) return OK; } -#endif /* defined(CONFIG_STM32H7_TIM1 || ... || TIM17) */ +#endif /* defined(CONFIG_STM32_TIM1 || ... || TIM17) */ diff --git a/arch/arm/src/stm32h7/stm32_tim_lowerhalf.c b/arch/arm/src/stm32h7/stm32_tim_lowerhalf.c index 895e54e7a2f9a..cc5e18737e5a7 100644 --- a/arch/arm/src/stm32h7/stm32_tim_lowerhalf.c +++ b/arch/arm/src/stm32h7/stm32_tim_lowerhalf.c @@ -58,13 +58,13 @@ #include "stm32_tim.h" #if defined(CONFIG_TIMER) && \ - (defined(CONFIG_STM32H7_TIM1) || defined(CONFIG_STM32H7_TIM2) || \ - defined(CONFIG_STM32H7_TIM3) || defined(CONFIG_STM32H7_TIM4) || \ - defined(CONFIG_STM32H7_TIM5) || defined(CONFIG_STM32H7_TIM6) || \ - defined(CONFIG_STM32H7_TIM7) || defined(CONFIG_STM32H7_TIM8) || \ - defined(CONFIG_STM32H7_TIM9) || defined(CONFIG_STM32H7_TIM10) || \ - defined(CONFIG_STM32H7_TIM11) || defined(CONFIG_STM32H7_TIM12) || \ - defined(CONFIG_STM32H7_TIM13) || defined(CONFIG_STM32H7_TIM14)) + (defined(CONFIG_STM32_TIM1) || defined(CONFIG_STM32_TIM2) || \ + defined(CONFIG_STM32_TIM3) || defined(CONFIG_STM32_TIM4) || \ + defined(CONFIG_STM32_TIM5) || defined(CONFIG_STM32_TIM6) || \ + defined(CONFIG_STM32_TIM7) || defined(CONFIG_STM32_TIM8) || \ + defined(CONFIG_STM32_TIM9) || defined(CONFIG_STM32_TIM10) || \ + defined(CONFIG_STM32_TIM11) || defined(CONFIG_STM32_TIM12) || \ + defined(CONFIG_STM32_TIM13) || defined(CONFIG_STM32_TIM14)) /**************************************************************************** * Pre-processor Definitions @@ -135,7 +135,7 @@ static const struct timer_ops_s g_timer_ops = .ioctl = NULL, }; -#ifdef CONFIG_STM32H7_TIM1 +#ifdef CONFIG_STM32_TIM1 static struct stm32_lowerhalf_s g_tim1_lowerhalf = { .ops = &g_timer_ops, @@ -143,7 +143,7 @@ static struct stm32_lowerhalf_s g_tim1_lowerhalf = }; #endif -#ifdef CONFIG_STM32H7_TIM2 +#ifdef CONFIG_STM32_TIM2 static struct stm32_lowerhalf_s g_tim2_lowerhalf = { .ops = &g_timer_ops, @@ -151,7 +151,7 @@ static struct stm32_lowerhalf_s g_tim2_lowerhalf = }; #endif -#ifdef CONFIG_STM32H7_TIM3 +#ifdef CONFIG_STM32_TIM3 static struct stm32_lowerhalf_s g_tim3_lowerhalf = { .ops = &g_timer_ops, @@ -159,7 +159,7 @@ static struct stm32_lowerhalf_s g_tim3_lowerhalf = }; #endif -#ifdef CONFIG_STM32H7_TIM4 +#ifdef CONFIG_STM32_TIM4 static struct stm32_lowerhalf_s g_tim4_lowerhalf = { .ops = &g_timer_ops, @@ -167,7 +167,7 @@ static struct stm32_lowerhalf_s g_tim4_lowerhalf = }; #endif -#ifdef CONFIG_STM32H7_TIM5 +#ifdef CONFIG_STM32_TIM5 static struct stm32_lowerhalf_s g_tim5_lowerhalf = { .ops = &g_timer_ops, @@ -175,7 +175,7 @@ static struct stm32_lowerhalf_s g_tim5_lowerhalf = }; #endif -#ifdef CONFIG_STM32H7_TIM6 +#ifdef CONFIG_STM32_TIM6 static struct stm32_lowerhalf_s g_tim6_lowerhalf = { .ops = &g_timer_ops, @@ -183,7 +183,7 @@ static struct stm32_lowerhalf_s g_tim6_lowerhalf = }; #endif -#ifdef CONFIG_STM32H7_TIM7 +#ifdef CONFIG_STM32_TIM7 static struct stm32_lowerhalf_s g_tim7_lowerhalf = { .ops = &g_timer_ops, @@ -191,7 +191,7 @@ static struct stm32_lowerhalf_s g_tim7_lowerhalf = }; #endif -#ifdef CONFIG_STM32H7_TIM8 +#ifdef CONFIG_STM32_TIM8 static struct stm32_lowerhalf_s g_tim8_lowerhalf = { .ops = &g_timer_ops, @@ -199,7 +199,7 @@ static struct stm32_lowerhalf_s g_tim8_lowerhalf = }; #endif -#ifdef CONFIG_STM32H7_TIM9 +#ifdef CONFIG_STM32_TIM9 static struct stm32_lowerhalf_s g_tim9_lowerhalf = { .ops = &g_timer_ops, @@ -207,7 +207,7 @@ static struct stm32_lowerhalf_s g_tim9_lowerhalf = }; #endif -#ifdef CONFIG_STM32H7_TIM10 +#ifdef CONFIG_STM32_TIM10 static struct stm32_lowerhalf_s g_tim10_lowerhalf = { .ops = &g_timer_ops, @@ -215,7 +215,7 @@ static struct stm32_lowerhalf_s g_tim10_lowerhalf = }; #endif -#ifdef CONFIG_STM32H7_TIM11 +#ifdef CONFIG_STM32_TIM11 static struct stm32_lowerhalf_s g_tim11_lowerhalf = { .ops = &g_timer_ops, @@ -223,7 +223,7 @@ static struct stm32_lowerhalf_s g_tim11_lowerhalf = }; #endif -#ifdef CONFIG_STM32H7_TIM12 +#ifdef CONFIG_STM32_TIM12 static struct stm32_lowerhalf_s g_tim12_lowerhalf = { .ops = &g_timer_ops, @@ -231,7 +231,7 @@ static struct stm32_lowerhalf_s g_tim12_lowerhalf = }; #endif -#ifdef CONFIG_STM32H7_TIM13 +#ifdef CONFIG_STM32_TIM13 static struct stm32_lowerhalf_s g_tim13_lowerhalf = { .ops = &g_timer_ops, @@ -239,7 +239,7 @@ static struct stm32_lowerhalf_s g_tim13_lowerhalf = }; #endif -#ifdef CONFIG_STM32H7_TIM14 +#ifdef CONFIG_STM32_TIM14 static struct stm32_lowerhalf_s g_tim14_lowerhalf = { .ops = &g_timer_ops, @@ -473,72 +473,72 @@ int stm32_timer_initialize(const char *devpath, int timer) switch (timer) { -#ifdef CONFIG_STM32H7_TIM1 +#ifdef CONFIG_STM32_TIM1 case 1: lower = &g_tim1_lowerhalf; break; #endif -#ifdef CONFIG_STM32H7_TIM2 +#ifdef CONFIG_STM32_TIM2 case 2: lower = &g_tim2_lowerhalf; break; #endif -#ifdef CONFIG_STM32H7_TIM3 +#ifdef CONFIG_STM32_TIM3 case 3: lower = &g_tim3_lowerhalf; break; #endif -#ifdef CONFIG_STM32H7_TIM4 +#ifdef CONFIG_STM32_TIM4 case 4: lower = &g_tim4_lowerhalf; break; #endif -#ifdef CONFIG_STM32H7_TIM5 +#ifdef CONFIG_STM32_TIM5 case 5: lower = &g_tim5_lowerhalf; break; #endif -#ifdef CONFIG_STM32H7_TIM6 +#ifdef CONFIG_STM32_TIM6 case 6: lower = &g_tim6_lowerhalf; break; #endif -#ifdef CONFIG_STM32H7_TIM7 +#ifdef CONFIG_STM32_TIM7 case 7: lower = &g_tim7_lowerhalf; break; #endif -#ifdef CONFIG_STM32H7_TIM8 +#ifdef CONFIG_STM32_TIM8 case 8: lower = &g_tim8_lowerhalf; break; #endif -#ifdef CONFIG_STM32H7_TIM9 +#ifdef CONFIG_STM32_TIM9 case 9: lower = &g_tim9_lowerhalf; break; #endif -#ifdef CONFIG_STM32H7_TIM10 +#ifdef CONFIG_STM32_TIM10 case 10: lower = &g_tim10_lowerhalf; break; #endif -#ifdef CONFIG_STM32H7_TIM11 +#ifdef CONFIG_STM32_TIM11 case 11: lower = &g_tim11_lowerhalf; break; #endif -#ifdef CONFIG_STM32H7_TIM12 +#ifdef CONFIG_STM32_TIM12 case 12: lower = &g_tim12_lowerhalf; break; #endif -#ifdef CONFIG_STM32H7_TIM13 +#ifdef CONFIG_STM32_TIM13 case 13: lower = &g_tim13_lowerhalf; break; #endif -#ifdef CONFIG_STM32H7_TIM14 +#ifdef CONFIG_STM32_TIM14 case 14: lower = &g_tim14_lowerhalf; break; diff --git a/arch/arm/src/stm32h7/stm32_timerisr.c b/arch/arm/src/stm32h7/stm32_timerisr.c index b2f37b5f58043..e5bd4cf05153c 100644 --- a/arch/arm/src/stm32h7/stm32_timerisr.c +++ b/arch/arm/src/stm32h7/stm32_timerisr.c @@ -66,14 +66,14 @@ * 224-1). */ -#undef CONFIG_STM32H7_SYSTICK_HCLKd8 +#undef CONFIG_STM32_SYSTICK_HCLKd8 /* REVISIT: * It looks like SYSTICK for H7 is always clocked from CPUCLK and doesn't * depend on the SYSTICK_CTRL_CLKSOURCE bit settings. */ -#ifdef CONFIG_STM32H7_SYSTICK_HCLKd8 +#ifdef CONFIG_STM32_SYSTICK_HCLKd8 # define STM32_SYSTICK_CLOCK (STM32_HCLK_FREQUENCY / 8) #else # define STM32_SYSTICK_CLOCK (STM32_CPUCLK_FREQUENCY) @@ -155,7 +155,7 @@ void up_timer_initialize(void) */ regval = (NVIC_SYSTICK_CTRL_TICKINT | NVIC_SYSTICK_CTRL_ENABLE); -#ifndef CONFIG_STM32H7_SYSTICK_HCLKd8 +#ifndef CONFIG_STM32_SYSTICK_HCLKd8 regval |= NVIC_SYSTICK_CTRL_CLKSOURCE; #else regval &= ~NVIC_SYSTICK_CTRL_CLKSOURCE; diff --git a/arch/arm/src/stm32h7/stm32_uart.h b/arch/arm/src/stm32h7/stm32_uart.h index 92234cb4c4556..8748d83c3430a 100644 --- a/arch/arm/src/stm32h7/stm32_uart.h +++ b/arch/arm/src/stm32h7/stm32_uart.h @@ -40,44 +40,44 @@ * device. */ -#if STM32H7_NUART < 4 -# undef CONFIG_STM32H7_UART8 +#if STM32_NUART < 4 +# undef CONFIG_STM32_UART8 #endif -#if STM32H7_NUART < 3 -# undef CONFIG_STM32H7_UART7 +#if STM32_NUART < 3 +# undef CONFIG_STM32_UART7 #endif -#if STM32H7_NUART < 2 -# undef CONFIG_STM32H7_UART5 +#if STM32_NUART < 2 +# undef CONFIG_STM32_UART5 #endif -#if STM32H7_NUART < 1 -# undef CONFIG_STM32H7_UART4 +#if STM32_NUART < 1 +# undef CONFIG_STM32_UART4 #endif -#if STM32H7_NUSART < 4 -# undef CONFIG_STM32H7_USART6 +#if STM32_NUSART < 4 +# undef CONFIG_STM32_USART6 #endif -#if STM32H7_NUSART < 3 -# undef CONFIG_STM32H7_USART3 +#if STM32_NUSART < 3 +# undef CONFIG_STM32_USART3 #endif -#if STM32H7_NUSART < 2 -# undef CONFIG_STM32H7_USART2 +#if STM32_NUSART < 2 +# undef CONFIG_STM32_USART2 #endif -#if STM32H7_NUSART < 1 -# undef CONFIG_STM32H7_USART1 +#if STM32_NUSART < 1 +# undef CONFIG_STM32_USART1 #endif /* Is there a USART enabled? */ -#if defined(CONFIG_STM32H7_USART1) || defined(CONFIG_STM32H7_USART2) || \ - defined(CONFIG_STM32H7_USART3) || defined(CONFIG_STM32H7_UART4) || \ - defined(CONFIG_STM32H7_UART5) || defined(CONFIG_STM32H7_USART6) || \ - defined(CONFIG_STM32H7_UART7) || defined(CONFIG_STM32H7_UART8) +#if defined(CONFIG_STM32_USART1) || defined(CONFIG_STM32_USART2) || \ + defined(CONFIG_STM32_USART3) || defined(CONFIG_STM32_UART4) || \ + defined(CONFIG_STM32_UART5) || defined(CONFIG_STM32_USART6) || \ + defined(CONFIG_STM32_UART7) || defined(CONFIG_STM32_UART8) # define HAVE_UART 1 #endif /* Is there a serial console? */ -#if defined(CONFIG_USART1_SERIAL_CONSOLE) && defined(CONFIG_STM32H7_USART1) +#if defined(CONFIG_USART1_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART1) # undef CONFIG_USART2_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE # undef CONFIG_UART4_SERIAL_CONSOLE @@ -87,7 +87,7 @@ # undef CONFIG_UART8_SERIAL_CONSOLE # define CONSOLE_UART 1 # define HAVE_CONSOLE 1 -#elif defined(CONFIG_USART2_SERIAL_CONSOLE) && defined(CONFIG_STM32H7_USART2) +#elif defined(CONFIG_USART2_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART2) # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE # undef CONFIG_UART4_SERIAL_CONSOLE @@ -97,7 +97,7 @@ # undef CONFIG_UART8_SERIAL_CONSOLE # define CONSOLE_UART 2 # define HAVE_CONSOLE 1 -#elif defined(CONFIG_USART3_SERIAL_CONSOLE) && defined(CONFIG_STM32H7_USART3) +#elif defined(CONFIG_USART3_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART3) # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # undef CONFIG_UART4_SERIAL_CONSOLE @@ -107,7 +107,7 @@ # undef CONFIG_UART8_SERIAL_CONSOLE # define CONSOLE_UART 3 # define HAVE_CONSOLE 1 -#elif defined(CONFIG_UART4_SERIAL_CONSOLE) && defined(CONFIG_STM32H7_UART4) +#elif defined(CONFIG_UART4_SERIAL_CONSOLE) && defined(CONFIG_STM32_UART4) # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE @@ -117,7 +117,7 @@ # undef CONFIG_UART8_SERIAL_CONSOLE # define CONSOLE_UART 4 # define HAVE_CONSOLE 1 -#elif defined(CONFIG_UART5_SERIAL_CONSOLE) && defined(CONFIG_STM32H7_UART5) +#elif defined(CONFIG_UART5_SERIAL_CONSOLE) && defined(CONFIG_STM32_UART5) # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE @@ -127,7 +127,7 @@ # undef CONFIG_UART8_SERIAL_CONSOLE # define CONSOLE_UART 5 # define HAVE_CONSOLE 1 -#elif defined(CONFIG_USART6_SERIAL_CONSOLE) && defined(CONFIG_STM32H7_USART6) +#elif defined(CONFIG_USART6_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART6) # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE @@ -137,7 +137,7 @@ # undef CONFIG_UART8_SERIAL_CONSOLE # define CONSOLE_UART 6 # define HAVE_CONSOLE 1 -#elif defined(CONFIG_UART7_SERIAL_CONSOLE) && defined(CONFIG_STM32H7_UART7) +#elif defined(CONFIG_UART7_SERIAL_CONSOLE) && defined(CONFIG_STM32_UART7) # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE @@ -147,7 +147,7 @@ # undef CONFIG_UART8_SERIAL_CONSOLE # define CONSOLE_UART 7 # define HAVE_CONSOLE 1 -#elif defined(CONFIG_UART8_SERIAL_CONSOLE) && defined(CONFIG_STM32H7_UART8) +#elif defined(CONFIG_UART8_SERIAL_CONSOLE) && defined(CONFIG_STM32_UART8) # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE @@ -296,42 +296,42 @@ /* Is RX DMA used on all (enabled) USARTs */ #define SERIAL_HAVE_ONLY_RXDMA 1 -#if defined(CONFIG_STM32H7_USART1) && !defined(CONFIG_USART1_RXDMA) +#if defined(CONFIG_STM32_USART1) && !defined(CONFIG_USART1_RXDMA) # undef SERIAL_HAVE_ONLY_RXDMA -#elif defined(CONFIG_STM32H7_USART2) && !defined(CONFIG_USART2_RXDMA) +#elif defined(CONFIG_STM32_USART2) && !defined(CONFIG_USART2_RXDMA) # undef SERIAL_HAVE_ONLY_RXDMA -#elif defined(CONFIG_STM32H7_USART3) && !defined(CONFIG_USART3_RXDMA) +#elif defined(CONFIG_STM32_USART3) && !defined(CONFIG_USART3_RXDMA) # undef SERIAL_HAVE_ONLY_RXDMA -#elif defined(CONFIG_STM32H7_UART4) && !defined(CONFIG_UART4_RXDMA) +#elif defined(CONFIG_STM32_UART4) && !defined(CONFIG_UART4_RXDMA) # undef SERIAL_HAVE_ONLY_RXDMA -#elif defined(CONFIG_STM32H7_UART5) && !defined(CONFIG_UART5_RXDMA) +#elif defined(CONFIG_STM32_UART5) && !defined(CONFIG_UART5_RXDMA) # undef SERIAL_HAVE_ONLY_RXDMA -#elif defined(CONFIG_STM32H7_USART6) && !defined(CONFIG_USART6_RXDMA) +#elif defined(CONFIG_STM32_USART6) && !defined(CONFIG_USART6_RXDMA) # undef SERIAL_HAVE_ONLY_RXDMA -#elif defined(CONFIG_STM32H7_UART7) && !defined(CONFIG_UART7_RXDMA) +#elif defined(CONFIG_STM32_UART7) && !defined(CONFIG_UART7_RXDMA) # undef SERIAL_HAVE_ONLY_RXDMA -#elif defined(CONFIG_STM32H7_UART8) && !defined(CONFIG_UART8_RXDMA) +#elif defined(CONFIG_STM32_UART8) && !defined(CONFIG_UART8_RXDMA) # undef SERIAL_HAVE_ONLY_RXDMA #endif /* Is TX DMA used on all (enabled) USARTs */ #define SERIAL_HAVE_ONLY_TXDMA 1 -#if defined(CONFIG_STM32H7_USART1) && !defined(CONFIG_USART1_TXDMA) +#if defined(CONFIG_STM32_USART1) && !defined(CONFIG_USART1_TXDMA) # undef SERIAL_HAVE_ONLY_TXDMA -#elif defined(CONFIG_STM32H7_USART2) && !defined(CONFIG_USART2_TXDMA) +#elif defined(CONFIG_STM32_USART2) && !defined(CONFIG_USART2_TXDMA) # undef SERIAL_HAVE_ONLY_TXDMA -#elif defined(CONFIG_STM32H7_USART3) && !defined(CONFIG_USART3_TXDMA) +#elif defined(CONFIG_STM32_USART3) && !defined(CONFIG_USART3_TXDMA) # undef SERIAL_HAVE_ONLY_TXDMA -#elif defined(CONFIG_STM32H7_UART4) && !defined(CONFIG_UART4_TXDMA) +#elif defined(CONFIG_STM32_UART4) && !defined(CONFIG_UART4_TXDMA) # undef SERIAL_HAVE_ONLY_TXDMA -#elif defined(CONFIG_STM32H7_UART5) && !defined(CONFIG_UART5_TXDMA) +#elif defined(CONFIG_STM32_UART5) && !defined(CONFIG_UART5_TXDMA) # undef SERIAL_HAVE_ONLY_TXDMA -#elif defined(CONFIG_STM32H7_USART6) && !defined(CONFIG_USART6_TXDMA) +#elif defined(CONFIG_STM32_USART6) && !defined(CONFIG_USART6_TXDMA) # undef SERIAL_HAVE_ONLY_TXDMA -#elif defined(CONFIG_STM32H7_UART7) && !defined(CONFIG_UART7_TXDMA) +#elif defined(CONFIG_STM32_UART7) && !defined(CONFIG_UART7_TXDMA) # undef SERIAL_HAVE_ONLY_TXDMA -#elif defined(CONFIG_STM32H7_UART8) && !defined(CONFIG_UART8_TXDMA) +#elif defined(CONFIG_STM32_UART8) && !defined(CONFIG_UART8_TXDMA) # undef SERIAL_HAVE_ONLY_TXDMA #endif @@ -343,28 +343,28 @@ /* No DMA ops */ #undef SERIAL_HAVE_NODMA_OPS -#if defined(CONFIG_STM32H7_USART1) && !defined(CONFIG_USART1_RXDMA) && \ +#if defined(CONFIG_STM32_USART1) && !defined(CONFIG_USART1_RXDMA) && \ !defined(CONFIG_USART1_TXDMA) # define SERIAL_HAVE_NODMA_OPS -#elif defined(CONFIG_STM32H7_USART2) && !defined(CONFIG_USART2_RXDMA) && \ +#elif defined(CONFIG_STM32_USART2) && !defined(CONFIG_USART2_RXDMA) && \ !defined(CONFIG_USART2_TXDMA) # define SERIAL_HAVE_NODMA_OPS -#elif defined(CONFIG_STM32H7_USART3) && !defined(CONFIG_USART3_RXDMA) && \ +#elif defined(CONFIG_STM32_USART3) && !defined(CONFIG_USART3_RXDMA) && \ !defined(CONFIG_USART3_TXDMA) # define SERIAL_HAVE_NODMA_OPS -#elif defined(CONFIG_STM32H7_UART4) && !defined(CONFIG_UART4_RXDMA) && \ +#elif defined(CONFIG_STM32_UART4) && !defined(CONFIG_UART4_RXDMA) && \ !defined(CONFIG_UART4_TXDMA) # define SERIAL_HAVE_NODMA_OPS -#elif defined(CONFIG_STM32H7_UART5) && !defined(CONFIG_UART5_RXDMA) && \ +#elif defined(CONFIG_STM32_UART5) && !defined(CONFIG_UART5_RXDMA) && \ !defined(CONFIG_UART5_TXDMA) # define SERIAL_HAVE_NODMA_OPS -#elif defined(CONFIG_STM32H7_USART6) && !defined(CONFIG_USART6_RXDMA) && \ +#elif defined(CONFIG_STM32_USART6) && !defined(CONFIG_USART6_RXDMA) && \ !defined(CONFIG_USART6_TXDMA) # define SERIAL_HAVE_NODMA_OPS -#elif defined(CONFIG_STM32H7_UART7) && !defined(CONFIG_UART7_RXDMA) && \ +#elif defined(CONFIG_STM32_UART7) && !defined(CONFIG_UART7_RXDMA) && \ !defined(CONFIG_UART7_TXDMA) # define SERIAL_HAVE_NODMA_OPS -#elif defined(CONFIG_STM32H7_UART8) && !defined(CONFIG_UART8_RXDMA) && \ +#elif defined(CONFIG_STM32_UART8) && !defined(CONFIG_UART8_RXDMA) && \ !defined(CONFIG_UART8_TXDMA) # define SERIAL_HAVE_NODMA_OPS #endif diff --git a/arch/arm/src/stm32h7/stm32_uid.c b/arch/arm/src/stm32h7/stm32_uid.c deleted file mode 100644 index a69edbe3898d4..0000000000000 --- a/arch/arm/src/stm32h7/stm32_uid.c +++ /dev/null @@ -1,64 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32h7/stm32_uid.c - * - * SPDX-License-Identifier: BSD-3-Clause - * SPDX-FileCopyrightText: 2015 Marawan Ragab. All rights reserved. - * SPDX-FileContributor: Marawan Ragab - * SPDX-FileContributor: David Sidrane - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "hardware/stm32_memorymap.h" - -#include "stm32_uid.h" - -#ifdef STM32_SYSMEM_UID - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -void stm32_get_uniqueid(uint8_t uniqueid[12]) -{ - int i; - - for (i = 0; i < 12; i++) - { - uniqueid[i] = *((uint8_t *)(STM32_SYSMEM_UID) + i); - } -} - -#endif /* STM32_SYSMEM_UID */ diff --git a/arch/arm/src/stm32h7/stm32_uid.h b/arch/arm/src/stm32h7/stm32_uid.h deleted file mode 100644 index 4946a910bed97..0000000000000 --- a/arch/arm/src/stm32h7/stm32_uid.h +++ /dev/null @@ -1,53 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32h7/stm32_uid.h - * - * SPDX-License-Identifier: BSD-3-Clause - * SPDX-FileCopyrightText: 2015 Marawan Ragab. All rights reserved. - * SPDX-FileContributor: Marawan Ragab - * SPDX-FileContributor: David Sidrane - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32H7_STM32_UID_H -#define __ARCH_ARM_SRC_STM32H7_STM32_UID_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -void stm32_get_uniqueid(uint8_t uniqueid[12]); - -#endif /* __ARCH_ARM_SRC_STM32H7_STM32_UID_H */ diff --git a/arch/arm/src/stm32h7/stm32_usbhost.h b/arch/arm/src/stm32h7/stm32_usbhost.h index 031b66ad22906..065e980ffcbbd 100644 --- a/arch/arm/src/stm32h7/stm32_usbhost.h +++ b/arch/arm/src/stm32h7/stm32_usbhost.h @@ -28,23 +28,23 @@ * Pre-requisites * * CONFIG_USBHOST - Enable general USB host support - * CONFIG_STM32H7_OTGFS - Enable the STM32 USB OTG FS block + * CONFIG_STM32_OTGFS - Enable the STM32 USB OTG FS block * or - * CONFIG_STM32H7_OTGHS - Enable the STM32 USB OTG HS block - * CONFIG_STM32H7_SYSCFG - Needed + * CONFIG_STM32_OTGHS - Enable the STM32 USB OTG HS block + * CONFIG_STM32_SYSCFG - Needed * * Options: * - * CONFIG_STM32H7_OTG_RXFIFO_SIZE - Size of the RX FIFO in 32-bit words. + * CONFIG_STM32_OTG_RXFIFO_SIZE - Size of the RX FIFO in 32-bit words. * Default 128 (512 bytes) - * CONFIG_STM32H7_OTG_NPTXFIFO_SIZE - Size of the non-periodic Tx FIFO + * CONFIG_STM32_OTG_NPTXFIFO_SIZE - Size of the non-periodic Tx FIFO * in 32-bit words. Default 96 (384 bytes) - * CONFIG_STM32H7_OTG_PTXFIFO_SIZE - Size of the periodic Tx FIFO in 32-bit + * CONFIG_STM32_OTG_PTXFIFO_SIZE - Size of the periodic Tx FIFO in 32-bit * words. Default 96 (384 bytes) - * CONFIG_STM32H7_OTG_SOFINTR - Enable SOF interrupts. Why would you ever + * CONFIG_STM32_OTG_SOFINTR - Enable SOF interrupts. Why would you ever * want to do that? * - * CONFIG_STM32H7_USBHOST_REGDEBUG - Enable very low-level register access + * CONFIG_STM32_USBHOST_REGDEBUG - Enable very low-level register access * debug. Depends on CONFIG_DEBUG_FEATURES. */ @@ -58,7 +58,7 @@ #include #include -#if (defined(CONFIG_STM32H7_OTGFS) || defined(CONFIG_STM32H7_OTGHS)) && \ +#if (defined(CONFIG_STM32_OTGFS) || defined(CONFIG_STM32_OTGHS)) && \ defined(CONFIG_USBHOST) #ifdef HAVE_USBHOST_TRACE @@ -190,5 +190,5 @@ void stm32_usbhost_vbusdrive(int iface, bool enable); #endif #endif /* __ASSEMBLY__ */ -#endif /* (CONFIG_STM32H7_OTGFS || CONFIG_STM32H7_OTGHS) && CONFIG_USBHOST */ +#endif /* (CONFIG_STM32_OTGFS || CONFIG_STM32_OTGHS) && CONFIG_USBHOST */ #endif /* __ARCH_ARM_SRC_STM32H7_STM32_USBHOST_H */ diff --git a/arch/arm/src/stm32h7/stm32_wdg.h b/arch/arm/src/stm32h7/stm32_wdg.h index f869669264aea..f5f5183766126 100644 --- a/arch/arm/src/stm32h7/stm32_wdg.h +++ b/arch/arm/src/stm32h7/stm32_wdg.h @@ -71,7 +71,7 @@ extern "C" * ****************************************************************************/ -#ifdef CONFIG_STM32H7_IWDG +#ifdef CONFIG_STM32_IWDG void stm32_iwdginitialize(const char *devpath, uint32_t lsifreq); #endif @@ -92,7 +92,7 @@ void stm32_iwdginitialize(const char *devpath, uint32_t lsifreq); * ****************************************************************************/ -#ifdef CONFIG_STM32H7_WWDG +#ifdef CONFIG_STM32_WWDG void stm32_wwdginitialize(const char *devpath); #endif diff --git a/arch/arm/src/stm32h7/stm32_wwdg.c b/arch/arm/src/stm32h7/stm32_wwdg.c index 4e96d10a3d3c2..7f254cf0c2166 100644 --- a/arch/arm/src/stm32h7/stm32_wwdg.c +++ b/arch/arm/src/stm32h7/stm32_wwdg.c @@ -39,7 +39,7 @@ #include "arm_internal.h" #include "stm32_wdg.h" -#if defined(CONFIG_WATCHDOG) && defined(CONFIG_STM32H7_WWDG) +#if defined(CONFIG_WATCHDOG) && defined(CONFIG_STM32_WWDG) /**************************************************************************** * Pre-processor Definitions @@ -66,12 +66,12 @@ /* Configuration ************************************************************/ -#ifndef CONFIG_STM32H7_WWDG_DEFTIMOUT -# define CONFIG_STM32H7_WWDG_DEFTIMOUT WWDG_MAXTIMEOUT +#ifndef CONFIG_STM32_WWDG_DEFTIMOUT +# define CONFIG_STM32_WWDG_DEFTIMOUT WWDG_MAXTIMEOUT #endif #ifndef CONFIG_DEBUG_WATCHDOG_INFO -# undef CONFIG_STM32H7_WWDG_REGDEBUG +# undef CONFIG_STM32_WWDG_REGDEBUG #endif /**************************************************************************** @@ -100,7 +100,7 @@ struct stm32_lowerhalf_s /* Register operations ******************************************************/ -#ifdef CONFIG_STM32H7_WWDG_REGDEBUG +#ifdef CONFIG_STM32_WWDG_REGDEBUG static uint16_t stm32_getreg(uint32_t addr); static void stm32_putreg(uint16_t val, uint32_t addr); #else @@ -161,7 +161,7 @@ static struct stm32_lowerhalf_s g_wdgdev; * ****************************************************************************/ -#ifdef CONFIG_STM32H7_WWDG_REGDEBUG +#ifdef CONFIG_STM32_WWDG_REGDEBUG static uint16_t stm32_getreg(uint32_t addr) { static uint32_t prevaddr = 0; @@ -224,7 +224,7 @@ static uint16_t stm32_getreg(uint32_t addr) * ****************************************************************************/ -#ifdef CONFIG_STM32H7_WWDG_REGDEBUG +#ifdef CONFIG_STM32_WWDG_REGDEBUG static void stm32_putreg(uint16_t val, uint32_t addr) { /* Show the register value being written */ @@ -772,7 +772,7 @@ void stm32_wwdginitialize(const char *devpath) */ stm32_settimeout((struct watchdog_lowerhalf_s *)priv, - CONFIG_STM32H7_WWDG_DEFTIMOUT); + CONFIG_STM32_WWDG_DEFTIMOUT); /* Register the watchdog driver as /dev/watchdog0 */ @@ -783,9 +783,9 @@ void stm32_wwdginitialize(const char *devpath) * on the WWDG1 STOP configuration bit in DBG module. */ -#if defined(CONFIG_STM32H7_JTAG_FULL_ENABLE) || \ - defined(CONFIG_STM32H7_JTAG_NOJNTRST_ENABLE) || \ - defined(CONFIG_STM32H7_JTAG_SW_ENABLE) +#if defined(CONFIG_STM32_JTAG_FULL_ENABLE) || \ + defined(CONFIG_STM32_JTAG_NOJNTRST_ENABLE) || \ + defined(CONFIG_STM32_JTAG_SW_ENABLE) { uint32_t cr = getreg32(STM32_DBGMCU_APB3_FZ1); cr |= DBGMCU_APB3_WWDG1STOP; @@ -794,4 +794,4 @@ void stm32_wwdginitialize(const char *devpath) #endif } -#endif /* CONFIG_WATCHDOG && CONFIG_STM32H7_WWDG */ +#endif /* CONFIG_WATCHDOG && CONFIG_STM32_WWDG */ diff --git a/arch/arm/src/stm32h7/stm32h743xx_flash.c b/arch/arm/src/stm32h7/stm32h743xx_flash.c index 1d68c42c78622..292fa63d5da02 100644 --- a/arch/arm/src/stm32h7/stm32h743xx_flash.c +++ b/arch/arm/src/stm32h7/stm32h743xx_flash.c @@ -69,10 +69,10 @@ /* Flash size is known from the chip selection: * - * When CONFIG_STM32H7_FLASH_OVERRIDE_DEFAULT is set the - * CONFIG_STM32H7_FLASH_CONFIG_x selects the default FLASH size based on + * When CONFIG_STM32_FLASH_OVERRIDE_DEFAULT is set the + * CONFIG_STM32_FLASH_CONFIG_x selects the default FLASH size based on * the chip part number. This value can be overridden with - * CONFIG_STM32H7_FLASH_OVERRIDE_x + * CONFIG_STM32_FLASH_OVERRIDE_x * * Parts STM32H74xxE have 512Kb of FLASH * Parts STM32H74xxG have 1024Kb of FLASH @@ -85,49 +85,49 @@ #define FLASH_SECTOR_SIZE _K(128) #define FLASH_PAGE_SIZE 32 -#if !defined(CONFIG_STM32H7_FLASH_OVERRIDE_DEFAULT) && \ - !defined(CONFIG_STM32H7_FLASH_OVERRIDE_B) && \ - !defined(CONFIG_STM32H7_FLASH_OVERRIDE_G) && \ - !defined(CONFIG_STM32H7_FLASH_OVERRIDE_I) && \ - !defined(CONFIG_STM32H7_FLASH_CONFIG_B) && \ - !defined(CONFIG_STM32H7_FLASH_CONFIG_G) && \ - !defined(CONFIG_STM32H7_FLASH_CONFIG_I) -# define CONFIG_STM32H7_FLASH_OVERRIDE_B +#if !defined(CONFIG_STM32_FLASH_OVERRIDE_DEFAULT) && \ + !defined(CONFIG_STM32_FLASH_OVERRIDE_B) && \ + !defined(CONFIG_STM32_FLASH_OVERRIDE_G) && \ + !defined(CONFIG_STM32_FLASH_OVERRIDE_I) && \ + !defined(CONFIG_STM32_FLASH_CONFIG_B) && \ + !defined(CONFIG_STM32_FLASH_CONFIG_G) && \ + !defined(CONFIG_STM32_FLASH_CONFIG_I) +# define CONFIG_STM32_FLASH_OVERRIDE_B # warning "Flash size not defined defaulting to 128KiB (B)" #endif -#if !defined(CONFIG_STM32H7_FLASH_OVERRIDE_DEFAULT) +#if !defined(CONFIG_STM32_FLASH_OVERRIDE_DEFAULT) -# undef CONFIG_STM32H7_FLASH_CONFIG_B -# undef CONFIG_STM32H7_FLASH_CONFIG_G -# undef CONFIG_STM32H7_FLASH_CONFIG_I +# undef CONFIG_STM32_FLASH_CONFIG_B +# undef CONFIG_STM32_FLASH_CONFIG_G +# undef CONFIG_STM32_FLASH_CONFIG_I -# if defined(CONFIG_STM32H7_FLASH_OVERRIDE_B) +# if defined(CONFIG_STM32_FLASH_OVERRIDE_B) -# define CONFIG_STM32H7_FLASH_CONFIG_B +# define CONFIG_STM32_FLASH_CONFIG_B -# elif defined(CONFIG_STM32H7_FLASH_OVERRIDE_G) +# elif defined(CONFIG_STM32_FLASH_OVERRIDE_G) -# define CONFIG_STM32H7_FLASH_CONFIG_G +# define CONFIG_STM32_FLASH_CONFIG_G -# elif defined(CONFIG_STM32H7_FLASH_OVERRIDE_I) +# elif defined(CONFIG_STM32_FLASH_OVERRIDE_I) -# define CONFIG_STM32H7_FLASH_CONFIG_I +# define CONFIG_STM32_FLASH_CONFIG_I # endif #endif -#if defined(CONFIG_STM32H7_FLASH_CONFIG_B) +#if defined(CONFIG_STM32_FLASH_CONFIG_B) # define STM32_FLASH_NBLOCKS 1 # define STM32_FLASH_SIZE _K(1 * 128) -#elif defined(CONFIG_STM32H7_FLASH_CONFIG_G) +#elif defined(CONFIG_STM32_FLASH_CONFIG_G) # define STM32_FLASH_NBLOCKS 8 # define STM32_FLASH_SIZE _K(8 * 128) -#elif defined(CONFIG_STM32H7_FLASH_CONFIG_I) +#elif defined(CONFIG_STM32_FLASH_CONFIG_I) # define STM32_FLASH_NBLOCKS 16 # define STM32_FLASH_SIZE _K(16 * 128) @@ -135,10 +135,10 @@ #endif -#ifndef CONFIG_STM32H7_FLASH_CR_PSIZE +#ifndef CONFIG_STM32_FLASH_CR_PSIZE #define FLASH_CR_PSIZE FLASH_CR_PSIZE_X64 #else -#define FLASH_CR_PSIZE (CONFIG_STM32H7_FLASH_CR_PSIZE << FLASH_CR_PSIZE_SHIFT) +#define FLASH_CR_PSIZE (CONFIG_STM32_FLASH_CR_PSIZE << FLASH_CR_PSIZE_SHIFT) #endif #define FLASH_KEY1 0x45670123 @@ -508,14 +508,14 @@ static void stm32h7_save_flashopt(struct stm32h7_flash_priv_s *priv) ****************************************************************************/ /**************************************************************************** - * Name: stm32h7_flash_unlock + * Name: stm32_flash_unlock * * Description: * Unlocks a bank * ****************************************************************************/ -int stm32h7_flash_unlock(size_t addr) +int stm32_flash_unlock(size_t addr) { int ret = -ENODEV; struct stm32h7_flash_priv_s *priv = stm32h7_flash_bank(addr); @@ -536,14 +536,14 @@ int stm32h7_flash_unlock(size_t addr) } /**************************************************************************** - * Name: stm32h7_flash_lock + * Name: stm32_flash_lock * * Description: * Locks a bank * ****************************************************************************/ -int stm32h7_flash_lock(size_t addr) +int stm32_flash_lock(size_t addr) { int ret = -ENODEV; struct stm32h7_flash_priv_s *priv = stm32h7_flash_bank(addr); @@ -564,14 +564,14 @@ int stm32h7_flash_lock(size_t addr) } /**************************************************************************** - * Name: stm32h7_flash_writeprotect + * Name: stm32_flash_writeprotect * * Description: * Enable or disable the write protection of a flash sector. * ****************************************************************************/ -int stm32h7_flash_writeprotect(size_t block, bool enabled) +int stm32_flash_writeprotect(size_t block, bool enabled) { struct stm32h7_flash_priv_s *priv; uint32_t setbits = 0; @@ -605,14 +605,14 @@ int stm32h7_flash_writeprotect(size_t block, bool enabled) } /**************************************************************************** - * Name: stm32h7_flash_getopt + * Name: stm32_flash_getopt * * Description: * Returns the current flash option bytes from the FLASH_OPTSR_CR register. * ****************************************************************************/ -uint32_t stm32h7_flash_getopt(void) +uint32_t stm32_flash_getopt(void) { struct stm32h7_flash_priv_s *priv; priv = stm32h7_flash_bank(STM32_FLASH_BANK1); @@ -625,14 +625,14 @@ uint32_t stm32h7_flash_getopt(void) } /**************************************************************************** - * Name: stm32h7_flash_optmodify + * Name: stm32_flash_optmodify * * Description: * Modifies the current flash option bytes, given bits to set and clear. * ****************************************************************************/ -void stm32h7_flash_optmodify(uint32_t clear, uint32_t set) +void stm32_flash_optmodify(uint32_t clear, uint32_t set) { struct stm32h7_flash_priv_s *priv; bool was_locked; @@ -652,7 +652,7 @@ void stm32h7_flash_optmodify(uint32_t clear, uint32_t set) } /**************************************************************************** - * Name: stm32h7_flash_swapbanks + * Name: stm32_flash_swapbanks * * Description: * Swaps banks 1 and 2 in the processor's memory map. Takes effect @@ -660,16 +660,16 @@ void stm32h7_flash_optmodify(uint32_t clear, uint32_t set) * ****************************************************************************/ -void stm32h7_flash_swapbanks(void) +void stm32_flash_swapbanks(void) { - uint32_t opts = stm32h7_flash_getopt(); + uint32_t opts = stm32_flash_getopt(); if (opts & FLASH_OPTCR_SWAPBANK) { - stm32h7_flash_optmodify(FLASH_OPTCR_SWAPBANK, 0); + stm32_flash_optmodify(FLASH_OPTCR_SWAPBANK, 0); } else { - stm32h7_flash_optmodify(0, FLASH_OPTCR_SWAPBANK); + stm32_flash_optmodify(0, FLASH_OPTCR_SWAPBANK); } } diff --git a/arch/arm/src/stm32h7/stm32h7b3xx_flash.c b/arch/arm/src/stm32h7/stm32h7b3xx_flash.c index c76b4e307a3bb..2a3756d9f534c 100644 --- a/arch/arm/src/stm32h7/stm32h7b3xx_flash.c +++ b/arch/arm/src/stm32h7/stm32h7b3xx_flash.c @@ -69,10 +69,10 @@ /* Flash size is known from the chip selection: * - * When CONFIG_STM32H7_FLASH_OVERRIDE_DEFAULT is set the - * CONFIG_STM32H7_FLASH_CONFIG_x selects the default FLASH size based on + * When CONFIG_STM32_FLASH_OVERRIDE_DEFAULT is set the + * CONFIG_STM32_FLASH_CONFIG_x selects the default FLASH size based on * the chip part number. This value can be overridden with - * CONFIG_STM32H7_FLASH_OVERRIDE_x + * CONFIG_STM32_FLASH_OVERRIDE_x * * Parts STM32H7x3xG have 1024Kb of FLASH * Parts STM32H7x3xI have 2048Kb of FLASH @@ -86,38 +86,38 @@ #define FLASH_PAGE_SIZE 16 -#if !defined(CONFIG_STM32H7_FLASH_OVERRIDE_DEFAULT) && \ - !defined(CONFIG_STM32H7_FLASH_OVERRIDE_G) && \ - !defined(CONFIG_STM32H7_FLASH_OVERRIDE_I) && \ - !defined(CONFIG_STM32H7_FLASH_CONFIG_G) && \ - !defined(CONFIG_STM32H7_FLASH_CONFIG_I) -# define CONFIG_STM32H7_FLASH_OVERRIDE_G +#if !defined(CONFIG_STM32_FLASH_OVERRIDE_DEFAULT) && \ + !defined(CONFIG_STM32_FLASH_OVERRIDE_G) && \ + !defined(CONFIG_STM32_FLASH_OVERRIDE_I) && \ + !defined(CONFIG_STM32_FLASH_CONFIG_G) && \ + !defined(CONFIG_STM32_FLASH_CONFIG_I) +# define CONFIG_STM32_FLASH_OVERRIDE_G # warning "Flash size not defined defaulting to 1024KiB (G)" #endif -#if !defined(CONFIG_STM32H7_FLASH_OVERRIDE_DEFAULT) +#if !defined(CONFIG_STM32_FLASH_OVERRIDE_DEFAULT) -# undef CONFIG_STM32H7_FLASH_CONFIG_B -# undef CONFIG_STM32H7_FLASH_CONFIG_G -# undef CONFIG_STM32H7_FLASH_CONFIG_I +# undef CONFIG_STM32_FLASH_CONFIG_B +# undef CONFIG_STM32_FLASH_CONFIG_G +# undef CONFIG_STM32_FLASH_CONFIG_I -# if defined(CONFIG_STM32H7_FLASH_OVERRIDE_G) +# if defined(CONFIG_STM32_FLASH_OVERRIDE_G) -# define CONFIG_STM32H7_FLASH_CONFIG_G +# define CONFIG_STM32_FLASH_CONFIG_G -# elif defined(CONFIG_STM32H7_FLASH_OVERRIDE_I) +# elif defined(CONFIG_STM32_FLASH_OVERRIDE_I) -# define CONFIG_STM32H7_FLASH_CONFIG_I +# define CONFIG_STM32_FLASH_CONFIG_I # endif #endif -#if defined(CONFIG_STM32H7_FLASH_CONFIG_G) +#if defined(CONFIG_STM32_FLASH_CONFIG_G) # define STM32_FLASH_NBLOCKS 128 # define STM32_FLASH_SIZE _K(128 * 8) -#elif defined(CONFIG_STM32H7_FLASH_CONFIG_I) +#elif defined(CONFIG_STM32_FLASH_CONFIG_I) # define STM32_FLASH_NBLOCKS 256 # define STM32_FLASH_SIZE _K(256 * 8) @@ -478,14 +478,14 @@ static void stm32h7_save_flashopt(struct stm32h7_flash_priv_s *priv) ****************************************************************************/ /**************************************************************************** - * Name: stm32h7_flash_unlock + * Name: stm32_flash_unlock * * Description: * Unlocks a bank * ****************************************************************************/ -int stm32h7_flash_unlock(size_t addr) +int stm32_flash_unlock(size_t addr) { int ret = -ENODEV; struct stm32h7_flash_priv_s *priv = stm32h7_flash_bank(addr); @@ -506,14 +506,14 @@ int stm32h7_flash_unlock(size_t addr) } /**************************************************************************** - * Name: stm32h7_flash_lock + * Name: stm32_flash_lock * * Description: * Locks a bank * ****************************************************************************/ -int stm32h7_flash_lock(size_t addr) +int stm32_flash_lock(size_t addr) { int ret = -ENODEV; struct stm32h7_flash_priv_s *priv = stm32h7_flash_bank(addr); @@ -534,14 +534,14 @@ int stm32h7_flash_lock(size_t addr) } /**************************************************************************** - * Name: stm32h7_flash_writeprotect + * Name: stm32_flash_writeprotect * * Description: * Enable or disable the write protection of a flash sector. * ****************************************************************************/ -int stm32h7_flash_writeprotect(size_t block, bool enabled) +int stm32_flash_writeprotect(size_t block, bool enabled) { struct stm32h7_flash_priv_s *priv; uint32_t setbits = 0; @@ -575,14 +575,14 @@ int stm32h7_flash_writeprotect(size_t block, bool enabled) } /**************************************************************************** - * Name: stm32h7_flash_getopt + * Name: stm32_flash_getopt * * Description: * Returns the current flash option bytes from the FLASH_OPTSR_CR register. * ****************************************************************************/ -uint32_t stm32h7_flash_getopt(void) +uint32_t stm32_flash_getopt(void) { struct stm32h7_flash_priv_s *priv; priv = stm32h7_flash_bank(STM32_FLASH_BANK1); @@ -595,14 +595,14 @@ uint32_t stm32h7_flash_getopt(void) } /**************************************************************************** - * Name: stm32h7_flash_optmodify + * Name: stm32_flash_optmodify * * Description: * Modifies the current flash option bytes, given bits to set and clear. * ****************************************************************************/ -void stm32h7_flash_optmodify(uint32_t clear, uint32_t set) +void stm32_flash_optmodify(uint32_t clear, uint32_t set) { struct stm32h7_flash_priv_s *priv; bool was_locked; @@ -622,7 +622,7 @@ void stm32h7_flash_optmodify(uint32_t clear, uint32_t set) } /**************************************************************************** - * Name: stm32h7_flash_swapbanks + * Name: stm32_flash_swapbanks * * Description: * Swaps banks 1 and 2 in the processor's memory map. Takes effect @@ -630,16 +630,16 @@ void stm32h7_flash_optmodify(uint32_t clear, uint32_t set) * ****************************************************************************/ -void stm32h7_flash_swapbanks(void) +void stm32_flash_swapbanks(void) { - uint32_t opts = stm32h7_flash_getopt(); + uint32_t opts = stm32_flash_getopt(); if (opts & FLASH_OPTCR_SWAPBANK) { - stm32h7_flash_optmodify(FLASH_OPTCR_SWAPBANK, 0); + stm32_flash_optmodify(FLASH_OPTCR_SWAPBANK, 0); } else { - stm32h7_flash_optmodify(0, FLASH_OPTCR_SWAPBANK); + stm32_flash_optmodify(0, FLASH_OPTCR_SWAPBANK); } } diff --git a/arch/arm/src/stm32h7/stm32h7x3xx_rcc.c b/arch/arm/src/stm32h7/stm32h7x3xx_rcc.c index a1ce272975bf0..c65bc2feeda73 100644 --- a/arch/arm/src/stm32h7/stm32h7x3xx_rcc.c +++ b/arch/arm/src/stm32h7/stm32h7x3xx_rcc.c @@ -146,23 +146,23 @@ static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1, * When the Soc does not supports SMPS we support only the LDO supply. */ -#ifdef CONFIG_STM32H7_HAVE_SMPS +#ifdef CONFIG_STM32_HAVE_SMPS # define STM32_PWR_CR3_MASK ~(STM32_PWR_CR3_BYPASS | \ STM32_PWR_CR3_LDOEN | \ STM32_PWR_CR3_SDEN | \ STM32_PWR_CR3_SMPSEXTHP | \ STM32_PWR_CR3_SMPSLEVEL_MASK) -# if defined(CONFIG_STM32H7_PWR_DIRECT_SMPS_SUPPLY) +# if defined(CONFIG_STM32_PWR_DIRECT_SMPS_SUPPLY) # define STM32_PWR_CR3_SELECTION STM32_PWR_CR3_SDEN -# elif defined(CONFIG_STM32H7_PWR_EXTERNAL_SOURCE_SUPPLY) +# elif defined(CONFIG_STM32_PWR_EXTERNAL_SOURCE_SUPPLY) # define STM32_PWR_CR3_SELECTION STM32_PWR_CR3_BYPASS # else # define STM32_PWR_CR3_SELECTION STM32_PWR_CR3_LDOEN # endif #else # define STM32_PWR_CR3_MASK 0xffffffff -# if defined(CONFIG_STM32H7_PWR_EXTERNAL_SOURCE_SUPPLY) +# if defined(CONFIG_STM32_PWR_EXTERNAL_SOURCE_SUPPLY) # define STM32_PWR_CR3_SELECTION (STM32_PWR_CR3_BYPASS | STM32_PWR_CR3_SCUEN) # else # define STM32_PWR_CR3_SELECTION (STM32_PWR_CR3_LDOEN | STM32_PWR_CR3_SCUEN) @@ -192,7 +192,7 @@ static inline void rcc_reset(void) regval |= RCC_CR_HSION; putreg32(regval, STM32_RCC_CR); -#if defined(CONFIG_STM32H7_AXI_SRAM_CORRUPTION_WAR) +#if defined(CONFIG_STM32_AXI_SRAM_CORRUPTION_WAR) /* Errata 2.2.9 Enable workaround for Reading from AXI SRAM may lead to * data read corruption. See ES0392 Rev 6. */ @@ -250,32 +250,32 @@ static inline void rcc_enableahb1(void) */ regval = getreg32(STM32_RCC_AHB1ENR); -#if defined(CONFIG_STM32H7_ADC1) || defined(CONFIG_STM32H7_ADC2) +#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) /* ADC1 & 2 clock enable */ regval |= RCC_AHB1ENR_ADC12EN; #endif -#ifdef CONFIG_STM32H7_DMA1 +#ifdef CONFIG_STM32_DMA1 /* DMA 1 clock enable */ regval |= RCC_AHB1ENR_DMA1EN; #endif -#ifdef CONFIG_STM32H7_DMA2 +#ifdef CONFIG_STM32_DMA2 /* DMA 2 clock enable */ regval |= RCC_AHB1ENR_DMA2EN; #endif -#ifdef CONFIG_STM32H7_OTGFS +#ifdef CONFIG_STM32_OTGFS /* USB OTG FS clock enable */ regval |= RCC_AHB1ENR_OTGFSEN; #endif -#ifdef CONFIG_STM32H7_OTGHS -# ifndef CONFIG_STM32H7_OTGHS_EXTERNAL_ULPI +#ifdef CONFIG_STM32_OTGHS +# ifndef CONFIG_STM32_OTGHS_EXTERNAL_ULPI /* Enable only clocking for USB OTG HS */ regval |= RCC_AHB1ENR_OTGHSEN; @@ -286,7 +286,7 @@ static inline void rcc_enableahb1(void) # endif #endif -#ifdef CONFIG_STM32H7_ETHMAC +#ifdef CONFIG_STM32_ETHMAC /* Enable ethernet clocks */ regval |= (RCC_AHB1ENR_ETH1MACEN | RCC_AHB1ENR_ETH1TXEN | @@ -314,19 +314,19 @@ static inline void rcc_enableahb2(void) regval = getreg32(STM32_RCC_AHB2ENR); -#ifdef CONFIG_STM32H7_SDMMC2 +#ifdef CONFIG_STM32_SDMMC2 /* SDMMC2 clock enable */ regval |= RCC_AHB2ENR_SDMMC2EN; #endif -#ifdef CONFIG_STM32H7_RNG +#ifdef CONFIG_STM32_RNG /* Random number generator clock enable */ regval |= RCC_AHB2ENR_RNGEN; #endif -#ifdef CONFIG_STM32H7_CRYP +#ifdef CONFIG_STM32_CRYP /* Cryptographic clock enable */ regval |= RCC_AHB2ENR_CRYPTEN; @@ -353,25 +353,25 @@ static inline void rcc_enableahb3(void) regval = getreg32(STM32_RCC_AHB3ENR); -#ifdef CONFIG_STM32H7_MDMA +#ifdef CONFIG_STM32_MDMA /* MDMA clock enable */ regval |= RCC_AHB3ENR_MDMAEN; #endif -#ifdef CONFIG_STM32H7_SDMMC1 +#ifdef CONFIG_STM32_SDMMC1 /* SDMMC clock enable */ regval |= RCC_AHB3ENR_SDMMC1EN; #endif -#ifdef CONFIG_STM32H7_FMC +#ifdef CONFIG_STM32_FMC /* Flexible static memory controller module clock enable */ regval |= RCC_AHB3ENR_FMCEN; #endif -#if defined(CONFIG_STM32H7_LTDC) && defined(CONFIG_STM32H7_DMA2D) +#if defined(CONFIG_STM32_LTDC) && defined(CONFIG_STM32_DMA2D) /* Enable DMA2D */ regval |= RCC_AHB3ENR_DMA2DEN; @@ -400,7 +400,7 @@ static inline void rcc_enableahb4(void) regval = getreg32(STM32_RCC_AHB4ENR); -#ifdef CONFIG_STM32H7_ADC3 +#ifdef CONFIG_STM32_ADC3 /* ADC3 clock enable */ regval |= RCC_AHB4ENR_ADC3EN; @@ -408,60 +408,60 @@ static inline void rcc_enableahb4(void) /* Enable GPIO, GPIOB, ... GPIOK */ -#if STM32H7_NGPIO > 0 +#if STM32_NGPIO > 0 regval |= (RCC_AHB4ENR_GPIOAEN -#if STM32H7_NGPIO > 1 +#if STM32_NGPIO > 1 | RCC_AHB4ENR_GPIOBEN #endif -#if STM32H7_NGPIO > 2 +#if STM32_NGPIO > 2 | RCC_AHB4ENR_GPIOCEN #endif -#if STM32H7_NGPIO > 3 +#if STM32_NGPIO > 3 | RCC_AHB4ENR_GPIODEN #endif -#if STM32H7_NGPIO > 4 +#if STM32_NGPIO > 4 | RCC_AHB4ENR_GPIOEEN #endif -#if (STM32H7_NGPIO > 5) && (defined(CONFIG_STM32H7_HAVE_GPIOF)) +#if (STM32_NGPIO > 5) && (defined(CONFIG_STM32_HAVE_GPIOF)) | RCC_AHB4ENR_GPIOFEN #endif -#if (STM32H7_NGPIO > 6) && (defined(CONFIG_STM32H7_HAVE_GPIOG)) +#if (STM32_NGPIO > 6) && (defined(CONFIG_STM32_HAVE_GPIOG)) | RCC_AHB4ENR_GPIOGEN #endif -#if STM32H7_NGPIO > 7 +#if STM32_NGPIO > 7 | RCC_AHB4ENR_GPIOHEN #endif -#if STM32H7_NGPIO > 8 +#if STM32_NGPIO > 8 | RCC_AHB4ENR_GPIOIEN #endif -#if STM32H7_NGPIO > 9 +#if STM32_NGPIO > 9 | RCC_AHB4ENR_GPIOJEN #endif -#if STM32H7_NGPIO > 10 +#if STM32_NGPIO > 10 | RCC_AHB4ENR_GPIOKEN #endif ); #endif -#ifdef CONFIG_STM32H7_BDMA +#ifdef CONFIG_STM32_BDMA /* BDMA clock enable */ regval |= RCC_AHB4ENR_BDMAEN; #endif -#ifdef CONFIG_STM32H7_CRC +#ifdef CONFIG_STM32_CRC /* CRC clock enable */ regval |= RCC_AHB4ENR_CRCEN; #endif -#ifdef CONFIG_STM32H7_BKPSRAM +#ifdef CONFIG_STM32_BKPSRAM /* Backup SRAM clock enable */ regval |= RCC_AHB4ENR_BKPSRAMEN; #endif -#ifdef CONFIG_STM32H7_HSEM +#ifdef CONFIG_STM32_HSEM /* HSEM clock enable */ regval |= RCC_AHB4ENR_HSEMEN; @@ -488,31 +488,31 @@ static inline void rcc_enableapb1(void) regval = getreg32(STM32_RCC_APB1LENR); -#ifdef CONFIG_STM32H7_SPI2 +#ifdef CONFIG_STM32_SPI2 /* SPI2 clock enable */ regval |= RCC_APB1LENR_SPI2EN; #endif -#ifdef CONFIG_STM32H7_SPI3 +#ifdef CONFIG_STM32_SPI3 /* SPI3 clock enable */ regval |= RCC_APB1LENR_SPI3EN; #endif -#ifdef CONFIG_STM32H7_I2C1 +#ifdef CONFIG_STM32_I2C1 /* I2C1 clock enable */ regval |= RCC_APB1LENR_I2C1EN; #endif -#ifdef CONFIG_STM32H7_I2C2 +#ifdef CONFIG_STM32_I2C2 /* I2C2 clock enable */ regval |= RCC_APB1LENR_I2C2EN; #endif -#ifdef CONFIG_STM32H7_I2C3 +#ifdef CONFIG_STM32_I2C3 /* I2C3 clock enable */ regval |= RCC_APB1LENR_I2C3EN; @@ -522,7 +522,7 @@ static inline void rcc_enableapb1(void) regval = getreg32(STM32_RCC_APB1HENR); -#ifdef CONFIG_STM32H7_FDCAN +#ifdef CONFIG_STM32_FDCAN /* FDCAN clock enable */ regval |= RCC_APB1HENR_FDCANEN; @@ -549,31 +549,31 @@ static inline void rcc_enableapb2(void) regval = getreg32(STM32_RCC_APB2ENR); -#ifdef CONFIG_STM32H7_SPI1 +#ifdef CONFIG_STM32_SPI1 /* SPI1 clock enable */ regval |= RCC_APB2ENR_SPI1EN; #endif -#ifdef CONFIG_STM32H7_SPI4 +#ifdef CONFIG_STM32_SPI4 /* SPI4 clock enable */ regval |= RCC_APB2ENR_SPI4EN; #endif -#ifdef CONFIG_STM32H7_SPI5 +#ifdef CONFIG_STM32_SPI5 /* SPI5 clock enable */ regval |= RCC_APB2ENR_SPI5EN; #endif -#ifdef CONFIG_STM32H7_USART1 +#ifdef CONFIG_STM32_USART1 /* USART1 clock enable */ regval |= RCC_APB2ENR_USART1EN; #endif -#ifdef CONFIG_STM32H7_USART6 +#ifdef CONFIG_STM32_USART6 /* USART6 clock enable */ regval |= RCC_APB2ENR_USART6EN; @@ -600,13 +600,13 @@ static inline void rcc_enableapb3(void) regval = getreg32(STM32_RCC_APB3ENR); -#ifdef CONFIG_STM32H7_LTDC +#ifdef CONFIG_STM32_LTDC /* LTDC clock enable */ regval |= RCC_APB3ENR_LTDCEN; #endif -#ifdef CONFIG_STM32H7_WWDG +#ifdef CONFIG_STM32_WWDG /* RM0433 Rev 8 * Reference manual - STM32H742, STM32H743/753 and STM32H750 Value line @@ -651,19 +651,19 @@ static inline void rcc_enableapb4(void) regval = getreg32(STM32_RCC_APB4ENR); -#ifdef CONFIG_STM32H7_SYSCFG +#ifdef CONFIG_STM32_SYSCFG /* System configuration controller clock enable */ regval |= RCC_APB4ENR_SYSCFGEN; #endif -#ifdef CONFIG_STM32H7_I2C4 +#ifdef CONFIG_STM32_I2C4 /* I2C4 clock enable */ regval |= RCC_APB4ENR_I2C4EN; #endif -#ifdef CONFIG_STM32H7_SPI6 +#ifdef CONFIG_STM32_SPI6 /* SPI6 clock enable */ regval |= RCC_APB4ENR_SPI6EN; @@ -762,7 +762,7 @@ void stm32_stdclockconfig(void) } #endif -#ifdef CONFIG_STM32H7_HSI48 +#ifdef CONFIG_STM32_HSI48 /* Enable HSI48 */ regval = getreg32(STM32_RCC_CR); @@ -776,7 +776,7 @@ void stm32_stdclockconfig(void) } #endif -#ifdef CONFIG_STM32H7_CSI +#ifdef CONFIG_STM32_CSI /* Enable CSI */ regval = getreg32(STM32_RCC_CR); @@ -832,7 +832,7 @@ void stm32_stdclockconfig(void) regval |= STM32_RCC_D3CFGR_D3PPRE; putreg32(regval, STM32_RCC_D3CFGR); -#ifdef CONFIG_STM32H7_RTC_HSECLOCK +#ifdef CONFIG_STM32_RTC_HSECLOCK /* Set the RTC clock divisor */ regval = getreg32(STM32_RCC_CFGR); @@ -963,7 +963,7 @@ void stm32_stdclockconfig(void) { } -#ifndef CONFIG_STM32H7_PWR_IGNORE_ACTVOSRDY +#ifndef CONFIG_STM32_PWR_IGNORE_ACTVOSRDY /* See Reference manual Section 5.4.1, System supply startup */ while ((getreg32(STM32_PWR_CSR1) & PWR_CSR1_ACTVOSRDY) == 0) @@ -1105,13 +1105,13 @@ void stm32_stdclockconfig(void) putreg32(regval, STM32_RCC_D2CCIP1R); #endif -#if defined(CONFIG_STM32H7_IWDG) || defined(CONFIG_STM32H7_RTC_LSICLOCK) +#if defined(CONFIG_STM32_IWDG) || defined(CONFIG_STM32_RTC_LSICLOCK) /* Low speed internal clock source LSI */ stm32_rcc_enablelsi(); #endif -#if defined(CONFIG_STM32H7_RTC_LSECLOCK) +#if defined(CONFIG_STM32_RTC_LSECLOCK) /* Low speed external clock source LSE * * TODO: There is another case where the LSE needs to diff --git a/arch/arm/src/stm32h7/stm32h7x7xx_rcc.c b/arch/arm/src/stm32h7/stm32h7x7xx_rcc.c index 2a03208623676..526dc538e4a9a 100644 --- a/arch/arm/src/stm32h7/stm32h7x7xx_rcc.c +++ b/arch/arm/src/stm32h7/stm32h7x7xx_rcc.c @@ -139,7 +139,7 @@ static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1, * When the Soc does not supports SMPS we support only the LDO supply. */ -#ifdef CONFIG_STM32H7_HAVE_SMPS +#ifdef CONFIG_STM32_HAVE_SMPS # define STM32_PWR_CR3_MASK ~(STM32_PWR_CR3_BYPASS | \ STM32_PWR_CR3_LDOEN | \ STM32_PWR_CR3_SDEN | \ @@ -179,7 +179,7 @@ static inline void rcc_reset(void) regval |= RCC_CR_HSION; putreg32(regval, STM32_RCC_CR); -#if defined(CONFIG_STM32H7_AXI_SRAM_CORRUPTION_WAR) +#if defined(CONFIG_STM32_AXI_SRAM_CORRUPTION_WAR) /* Errata 2.2.9 Enable workaround for Reading from AXI SRAM may lead to * data read corruption. See ES0392 Rev 6. */ @@ -237,32 +237,32 @@ static inline void rcc_enableahb1(void) */ regval = getreg32(STM32_RCC_AHB1ENR); -#if defined(CONFIG_STM32H7_ADC1) || defined(CONFIG_STM32H7_ADC2) +#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) /* ADC1 & 2 clock enable */ regval |= RCC_AHB1ENR_ADC12EN; #endif -#ifdef CONFIG_STM32H7_DMA1 +#ifdef CONFIG_STM32_DMA1 /* DMA 1 clock enable */ regval |= RCC_AHB1ENR_DMA1EN; #endif -#ifdef CONFIG_STM32H7_DMA2 +#ifdef CONFIG_STM32_DMA2 /* DMA 2 clock enable */ regval |= RCC_AHB1ENR_DMA2EN; #endif -#ifdef CONFIG_STM32H7_OTGFS +#ifdef CONFIG_STM32_OTGFS /* USB OTG FS clock enable */ regval |= RCC_AHB1ENR_OTGFSEN; #endif -#ifdef CONFIG_STM32H7_OTGHS -# if defined(CONFIG_STM32H7_OTGHS_EXTERNAL_ULPI) +#ifdef CONFIG_STM32_OTGHS +# if defined(CONFIG_STM32_OTGHS_EXTERNAL_ULPI) /* Enable clocking for USB OTG HS and external PHY */ regval |= (RCC_AHB1ENR_OTGHSEN | RCC_AHB1ENR_OTGHSULPIEN); @@ -273,7 +273,7 @@ static inline void rcc_enableahb1(void) #endif #endif -#ifdef CONFIG_STM32H7_ETHMAC +#ifdef CONFIG_STM32_ETHMAC /* Enable ethernet clocks */ regval |= (RCC_AHB1ENR_ETH1MACEN | RCC_AHB1ENR_ETH1TXEN | @@ -301,13 +301,13 @@ static inline void rcc_enableahb2(void) regval = getreg32(STM32_RCC_AHB2ENR); -#ifdef CONFIG_STM32H7_SDMMC2 +#ifdef CONFIG_STM32_SDMMC2 /* SDMMC2 clock enable */ regval |= RCC_AHB2ENR_SDMMC2EN; #endif -#ifdef CONFIG_STM32H7_RNG +#ifdef CONFIG_STM32_RNG /* Random number generator clock enable */ regval |= RCC_AHB2ENR_RNGEN; @@ -334,19 +334,19 @@ static inline void rcc_enableahb3(void) regval = getreg32(STM32_RCC_AHB3ENR); -#ifdef CONFIG_STM32H7_MDMA +#ifdef CONFIG_STM32_MDMA /* MDMA clock enable */ regval |= RCC_AHB3ENR_MDMAEN; #endif -#ifdef CONFIG_STM32H7_SDMMC1 +#ifdef CONFIG_STM32_SDMMC1 /* SDMMC clock enable */ regval |= RCC_AHB3ENR_SDMMC1EN; #endif -#ifdef CONFIG_STM32H7_FMC +#ifdef CONFIG_STM32_FMC /* Flexible static memory controller module clock enable */ regval |= RCC_AHB3ENR_FMCEN; @@ -375,7 +375,7 @@ static inline void rcc_enableahb4(void) regval = getreg32(STM32_RCC_AHB4ENR); -#ifdef CONFIG_STM32H7_ADC3 +#ifdef CONFIG_STM32_ADC3 /* ADC3 clock enable */ regval |= RCC_AHB4ENR_ADC3EN; @@ -383,54 +383,54 @@ static inline void rcc_enableahb4(void) /* Enable GPIO, GPIOB, ... GPIOK */ -#if STM32H7_NGPIO > 0 +#if STM32_NGPIO > 0 regval |= (RCC_AHB4ENR_GPIOAEN -#if STM32H7_NGPIO > 1 +#if STM32_NGPIO > 1 | RCC_AHB4ENR_GPIOBEN #endif -#if STM32H7_NGPIO > 2 +#if STM32_NGPIO > 2 | RCC_AHB4ENR_GPIOCEN #endif -#if STM32H7_NGPIO > 3 +#if STM32_NGPIO > 3 | RCC_AHB4ENR_GPIODEN #endif -#if STM32H7_NGPIO > 4 +#if STM32_NGPIO > 4 | RCC_AHB4ENR_GPIOEEN #endif -#if (STM32H7_NGPIO > 5) && (defined(CONFIG_STM32H7_HAVE_GPIOF)) +#if (STM32_NGPIO > 5) && (defined(CONFIG_STM32_HAVE_GPIOF)) | RCC_AHB4ENR_GPIOFEN #endif -#if (STM32H7_NGPIO > 6) && (defined(CONFIG_STM32H7_HAVE_GPIOG)) +#if (STM32_NGPIO > 6) && (defined(CONFIG_STM32_HAVE_GPIOG)) | RCC_AHB4ENR_GPIOGEN #endif -#if STM32H7_NGPIO > 7 +#if STM32_NGPIO > 7 | RCC_AHB4ENR_GPIOHEN #endif -#if STM32H7_NGPIO > 8 +#if STM32_NGPIO > 8 | RCC_AHB4ENR_GPIOIEN #endif -#if STM32H7_NGPIO > 9 +#if STM32_NGPIO > 9 | RCC_AHB4ENR_GPIOJEN #endif -#if STM32H7_NGPIO > 10 +#if STM32_NGPIO > 10 | RCC_AHB4ENR_GPIOKEN #endif ); #endif -#ifdef CONFIG_STM32H7_BDMA +#ifdef CONFIG_STM32_BDMA /* BDMA clock enable */ regval |= RCC_AHB4ENR_BDMAEN; #endif -#ifdef CONFIG_STM32H7_CRC +#ifdef CONFIG_STM32_CRC /* CRC clock enable */ regval |= RCC_AHB4ENR_CRCEN; #endif -#ifdef CONFIG_STM32H7_BKPSRAM +#ifdef CONFIG_STM32_BKPSRAM /* Backup SRAM clock enable */ regval |= RCC_AHB4ENR_BKPSRAMEN; @@ -457,31 +457,31 @@ static inline void rcc_enableapb1(void) regval = getreg32(STM32_RCC_APB1LENR); -#ifdef CONFIG_STM32H7_SPI2 +#ifdef CONFIG_STM32_SPI2 /* SPI2 clock enable */ regval |= RCC_APB1LENR_SPI2EN; #endif -#ifdef CONFIG_STM32H7_SPI3 +#ifdef CONFIG_STM32_SPI3 /* SPI3 clock enable */ regval |= RCC_APB1LENR_SPI3EN; #endif -#ifdef CONFIG_STM32H7_I2C1 +#ifdef CONFIG_STM32_I2C1 /* I2C1 clock enable */ regval |= RCC_APB1LENR_I2C1EN; #endif -#ifdef CONFIG_STM32H7_I2C2 +#ifdef CONFIG_STM32_I2C2 /* I2C2 clock enable */ regval |= RCC_APB1LENR_I2C2EN; #endif -#ifdef CONFIG_STM32H7_I2C3 +#ifdef CONFIG_STM32_I2C3 /* I2C3 clock enable */ regval |= RCC_APB1LENR_I2C3EN; @@ -516,31 +516,31 @@ static inline void rcc_enableapb2(void) regval = getreg32(STM32_RCC_APB2ENR); -#ifdef CONFIG_STM32H7_SPI1 +#ifdef CONFIG_STM32_SPI1 /* SPI1 clock enable */ regval |= RCC_APB2ENR_SPI1EN; #endif -#ifdef CONFIG_STM32H7_SPI4 +#ifdef CONFIG_STM32_SPI4 /* SPI4 clock enable */ regval |= RCC_APB2ENR_SPI4EN; #endif -#ifdef CONFIG_STM32H7_SPI5 +#ifdef CONFIG_STM32_SPI5 /* SPI5 clock enable */ regval |= RCC_APB2ENR_SPI5EN; #endif -#ifdef CONFIG_STM32H7_USART1 +#ifdef CONFIG_STM32_USART1 /* USART1 clock enable */ regval |= RCC_APB2ENR_USART1EN; #endif -#ifdef CONFIG_STM32H7_USART6 +#ifdef CONFIG_STM32_USART6 /* USART6 clock enable */ regval |= RCC_APB2ENR_USART6EN; @@ -590,19 +590,19 @@ static inline void rcc_enableapb4(void) regval = getreg32(STM32_RCC_APB4ENR); -#ifdef CONFIG_STM32H7_SYSCFG +#ifdef CONFIG_STM32_SYSCFG /* System configuration controller clock enable */ regval |= RCC_APB4ENR_SYSCFGEN; #endif -#ifdef CONFIG_STM32H7_I2C4 +#ifdef CONFIG_STM32_I2C4 /* I2C4 clock enable */ regval |= RCC_APB4ENR_I2C4EN; #endif -#ifdef CONFIG_STM32H7_SPI6 +#ifdef CONFIG_STM32_SPI6 /* SPI6 clock enable */ regval |= RCC_APB4ENR_SPI6EN; @@ -696,7 +696,7 @@ void stm32_stdclockconfig(void) } #endif -#ifdef CONFIG_STM32H7_HSI48 +#ifdef CONFIG_STM32_HSI48 /* Enable HSI48 */ regval = getreg32(STM32_RCC_CR); @@ -710,7 +710,7 @@ void stm32_stdclockconfig(void) } #endif -#ifdef CONFIG_STM32H7_CSI +#ifdef CONFIG_STM32_CSI /* Enable CSI */ regval = getreg32(STM32_RCC_CR); @@ -766,7 +766,7 @@ void stm32_stdclockconfig(void) regval |= STM32_RCC_D3CFGR_D3PPRE; putreg32(regval, STM32_RCC_D3CFGR); -#ifdef CONFIG_STM32H7_RTC_HSECLOCK +#ifdef CONFIG_STM32_RTC_HSECLOCK /* Set the RTC clock divisor */ regval = getreg32(STM32_RCC_CFGR); @@ -897,7 +897,7 @@ void stm32_stdclockconfig(void) { } -#ifndef CONFIG_STM32H7_PWR_IGNORE_ACTVOSRDY +#ifndef CONFIG_STM32_PWR_IGNORE_ACTVOSRDY /* See Reference manual Section 5.4.1, System supply startup */ while ((getreg32(STM32_PWR_CSR1) & PWR_CSR1_ACTVOSRDY) == 0) @@ -1038,13 +1038,13 @@ void stm32_stdclockconfig(void) putreg32(regval, STM32_RCC_D2CCIP1R); #endif -#if defined(CONFIG_STM32H7_IWDG) || defined(CONFIG_STM32H7_RTC_LSICLOCK) +#if defined(CONFIG_STM32_IWDG) || defined(CONFIG_STM32_RTC_LSICLOCK) /* Low speed internal clock source LSI */ stm32_rcc_enablelsi(); #endif -#if defined(CONFIG_STM32H7_RTC_LSECLOCK) +#if defined(CONFIG_STM32_RTC_LSECLOCK) /* Low speed external clock source LSE * * TODO: There is another case where the LSE needs to diff --git a/arch/arm/src/stm32l0/CMakeLists.txt b/arch/arm/src/stm32l0/CMakeLists.txt new file mode 100644 index 0000000000000..0b2c640ff2d8f --- /dev/null +++ b/arch/arm/src/stm32l0/CMakeLists.txt @@ -0,0 +1,32 @@ +# ############################################################################## +# arch/arm/src/stm32l0/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(SRCS) + +list(APPEND SRCS stm32_rcc.c) + +if(CONFIG_BUILD_PROTECTED) + list(APPEND SRCS stm32_userspace.c) +endif() + +target_sources(arch PRIVATE ${SRCS}) +add_subdirectory(${NUTTX_DIR}/arch/arm/src/common/stm32 stm32_common) diff --git a/arch/arm/src/stm32l0/Kconfig b/arch/arm/src/stm32l0/Kconfig new file mode 100644 index 0000000000000..db1311b2b7d14 --- /dev/null +++ b/arch/arm/src/stm32l0/Kconfig @@ -0,0 +1,268 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# +comment "STM32 L0 configuration" + +if ARCH_CHIP_STM32L0 + +choice + prompt "ST STM32L0 Chip Selection" + default ARCH_CHIP_STM32L073RZ + depends on ARCH_CHIP_STM32L0 + +config ARCH_CHIP_STM32L053C8 + bool "STM32L053C8" + select ARCH_CHIP_STM32L053XX + depends on ARCH_CHIP_STM32L0 + +config ARCH_CHIP_STM32L053R8 + bool "STM32L053R8" + select ARCH_CHIP_STM32L053XX + depends on ARCH_CHIP_STM32L0 + +config ARCH_CHIP_STM32L071K8 + bool "STM32L071K8" + select ARCH_CHIP_STM32L071XX + depends on ARCH_CHIP_STM32L0 + +config ARCH_CHIP_STM32L071KB + bool "STM32L071KB" + select ARCH_CHIP_STM32L071XX + depends on ARCH_CHIP_STM32L0 + +config ARCH_CHIP_STM32L071KZ + bool "STM32L071KZ" + select ARCH_CHIP_STM32L071XX + depends on ARCH_CHIP_STM32L0 + +config ARCH_CHIP_STM32L071C8 + bool "STM32L071C8" + select ARCH_CHIP_STM32L071XX + select STM32_HAVE_USART5 + select STM32_HAVE_SPI2 + select STM32_HAVE_I2C3 + depends on ARCH_CHIP_STM32L0 + +config ARCH_CHIP_STM32L071CB + bool "STM32L071CB" + select ARCH_CHIP_STM32L071XX + select STM32_HAVE_USART5 + select STM32_HAVE_SPI2 + select STM32_HAVE_I2C3 + depends on ARCH_CHIP_STM32L0 + +config ARCH_CHIP_STM32L071CZ + bool "STM32L071CZ" + select ARCH_CHIP_STM32L071XX + select STM32_HAVE_USART5 + select STM32_HAVE_SPI2 + select STM32_HAVE_I2C3 + depends on ARCH_CHIP_STM32L0 + +config ARCH_CHIP_STM32L071V8 + bool "STM32L071V8" + select ARCH_CHIP_STM32L071XX + select STM32_HAVE_USART5 + select STM32_HAVE_SPI2 + select STM32_HAVE_I2C3 + depends on ARCH_CHIP_STM32L0 + +config ARCH_CHIP_STM32L071VB + bool "STM32L071VB" + select ARCH_CHIP_STM32L071XX + select STM32_HAVE_USART5 + select STM32_HAVE_SPI2 + select STM32_HAVE_I2C3 + depends on ARCH_CHIP_STM32L0 + +config ARCH_CHIP_STM32L071VZ + bool "STM32L071VZ" + select ARCH_CHIP_STM32L071XX + select STM32_HAVE_USART5 + select STM32_HAVE_SPI2 + select STM32_HAVE_I2C3 + depends on ARCH_CHIP_STM32L0 + +config ARCH_CHIP_STM32L071RB + bool "STM32L071RB" + select ARCH_CHIP_STM32L071XX + select STM32_HAVE_USART5 + select STM32_HAVE_SPI2 + select STM32_HAVE_I2C3 + depends on ARCH_CHIP_STM32L0 + +config ARCH_CHIP_STM32L071RZ + bool "STM32L071RZ" + select ARCH_CHIP_STM32L071XX + select STM32_HAVE_USART5 + select STM32_HAVE_SPI2 + select STM32_HAVE_I2C3 + depends on ARCH_CHIP_STM32L0 + +config ARCH_CHIP_STM32L072V8 + bool "STM32L072V8" + select ARCH_CHIP_STM32L072XX + select STM32_HAVE_SPI2 + select STM32_HAVE_I2C3 + depends on ARCH_CHIP_STM32L0 + +config ARCH_CHIP_STM32L072VB + bool "STM32L072VB" + select ARCH_CHIP_STM32L072XX + select STM32_HAVE_SPI2 + select STM32_HAVE_I2C3 + depends on ARCH_CHIP_STM32L0 + +config ARCH_CHIP_STM32L072VZ + bool "STM32L072VZ" + select ARCH_CHIP_STM32L072XX + select STM32_HAVE_SPI2 + select STM32_HAVE_I2C3 + depends on ARCH_CHIP_STM32L0 + +config ARCH_CHIP_STM32L072KB + bool "STM32L072KB" + select ARCH_CHIP_STM32L072XX + depends on ARCH_CHIP_STM32L0 + +config ARCH_CHIP_STM32L072KZ + bool "STM32L072KZ" + select ARCH_CHIP_STM32L072XX + depends on ARCH_CHIP_STM32L0 + +config ARCH_CHIP_STM32L072CB + bool "STM32L072CB" + select ARCH_CHIP_STM32L072XX + select STM32_HAVE_SPI2 + select STM32_HAVE_I2C3 + depends on ARCH_CHIP_STM32L0 + +config ARCH_CHIP_STM32L072CZ + bool "STM32L072CZ" + select ARCH_CHIP_STM32L072XX + select STM32_HAVE_SPI2 + select STM32_HAVE_I2C3 + depends on ARCH_CHIP_STM32L0 + +config ARCH_CHIP_STM32L072RB + bool "STM32L072RB" + select ARCH_CHIP_STM32L072XX + select STM32_HAVE_SPI2 + select STM32_HAVE_I2C3 + depends on ARCH_CHIP_STM32L0 + +config ARCH_CHIP_STM32L072RZ + bool "STM32L072RZ" + select ARCH_CHIP_STM32L072XX + select STM32_HAVE_SPI2 + select STM32_HAVE_I2C3 + depends on ARCH_CHIP_STM32L0 + +config ARCH_CHIP_STM32L073V8 + bool "STM32L073V8" + select ARCH_CHIP_STM32L073XX + depends on ARCH_CHIP_STM32L0 + +config ARCH_CHIP_STM32L073VB + bool "STM32L073VB" + select ARCH_CHIP_STM32L073XX + depends on ARCH_CHIP_STM32L0 + +config ARCH_CHIP_STM32L073VZ + bool "STM32L073VZ" + select ARCH_CHIP_STM32L073XX + depends on ARCH_CHIP_STM32L0 + +config ARCH_CHIP_STM32L073CB + bool "STM32L073CB" + select ARCH_CHIP_STM32L073XX + depends on ARCH_CHIP_STM32L0 + +config ARCH_CHIP_STM32L073CZ + bool "STM32L073CZ" + select ARCH_CHIP_STM32L073XX + depends on ARCH_CHIP_STM32L0 + +config ARCH_CHIP_STM32L073RB + bool "STM32L073RB" + select ARCH_CHIP_STM32L073XX + depends on ARCH_CHIP_STM32L0 + +config ARCH_CHIP_STM32L073RZ + bool "STM32L073RZ" + select ARCH_CHIP_STM32L073XX + depends on ARCH_CHIP_STM32L0 + +endchoice + +endif + +config STM32_STM32L0 + bool + default n + select STM32_HAVE_DMA1 + select STM32_HAVE_I2C1 + select STM32_HAVE_SPI1 + select STM32_HAVE_USART1 + select STM32_HAVE_USART2 + select STM32_ENERGYLITE + select STM32_HAVE_LCD + select STM32_HAVE_VREFINT + select STM32_HAVE_IP_ADC_M0_V1 + select STM32_HAVE_IP_AES_M0_V1 if STM32_HAVE_AES + select STM32_HAVE_IP_COMP_M0_V1 if STM32_HAVE_COMP + select STM32_HAVE_IP_DAC_M0_V1 if STM32_HAVE_DAC1 + select STM32_HAVE_IP_DBGMCU_M0_V1 + select STM32_HAVE_IP_DMA_V1 + select STM32_HAVE_IP_DMA_V1_7CH + select STM32_HAVE_IP_EXTI_V1 + select STM32_HAVE_IP_FLASH_M0_V1 + select STM32_HAVE_IP_GPIO_M0_V1 + select STM32_HAVE_IP_I2C_M0_V1 + select STM32_HAVE_IP_PWR_M0_V1 + select STM32_HAVE_IP_SPI_V1 + select STM32_HAVE_IP_TIMERS_M0_V1 + select STM32_HAVE_IP_USART_V3 + select STM32_HAVE_IP_WDG_M0_V1 + select STM32_HAVE_IP_RNG_M0_V1 if STM32_HAVE_RNG + select STM32_HAVE_IP_RTCC_M0_V1 + select STM32_HAVE_IP_USBDEV_M0_V1 if STM32_HAVE_USBDEV + select STM32_HAVE_IP_HSI48_M0_V1 if STM32_HAVE_HSI48 + +config ARCH_CHIP_STM32L053XX + bool + select STM32_STM32L0 + +config ARCH_CHIP_STM32L071XX + bool + select STM32_STM32L0 + select STM32_HAVE_RNG + select STM32_HAVE_HSI48 + select STM32_HAVE_USART4 + +config ARCH_CHIP_STM32L072XX + bool + select STM32_STM32L0 + select STM32_HAVE_RNG + select STM32_HAVE_HSI48 + select STM32_HAVE_USART4 + select STM32_HAVE_USART5 + select STM32_HAVE_I2C2 + select STM32_HAVE_USBDEV + +config ARCH_CHIP_STM32L073XX + bool + select STM32_STM32L0 + select STM32_HAVE_RNG + select STM32_HAVE_HSI48 + select STM32_HAVE_USART4 + select STM32_HAVE_USART5 + select STM32_HAVE_SPI2 + select STM32_HAVE_I2C2 + select STM32_HAVE_I2C3 + select STM32_HAVE_USBDEV + +config STM32_FLASH_OVERRIDE + bool "Override Flash Designator" + default n diff --git a/arch/arm/src/stm32l0/Make.defs b/arch/arm/src/stm32l0/Make.defs new file mode 100644 index 0000000000000..41ee69999f4cf --- /dev/null +++ b/arch/arm/src/stm32l0/Make.defs @@ -0,0 +1,31 @@ +############################################################################ +# arch/arm/src/stm32l0/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include armv6-m/Make.defs + +CHIP_CSRCS = stm32_rcc.c + +ifeq ($(CONFIG_BUILD_PROTECTED),y) +CHIP_CSRCS += stm32_userspace.c +endif + +include common/stm32/Make.defs diff --git a/arch/arm/src/stm32l0/chip.h b/arch/arm/src/stm32l0/chip.h new file mode 100644 index 0000000000000..f5e1ecde93eae --- /dev/null +++ b/arch/arm/src/stm32l0/chip.h @@ -0,0 +1,44 @@ +/**************************************************************************** + * arch/arm/src/stm32l0/chip.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32L0_CHIP_H +#define __ARCH_ARM_SRC_STM32L0_CHIP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include "nvic.h" + +/* Include the chip capabilities file */ + +#include + +/* Include the memory map file. + * Other chip hardware files should then include this file for the proper + * setup. + */ + +#include "hardware/stm32_memorymap.h" + +#endif /* __ARCH_ARM_SRC_STM32L0_CHIP_H */ diff --git a/arch/arm/src/stm32l0/hardware/stm32_memorymap.h b/arch/arm/src/stm32l0/hardware/stm32_memorymap.h new file mode 100644 index 0000000000000..44f335487ab12 --- /dev/null +++ b/arch/arm/src/stm32l0/hardware/stm32_memorymap.h @@ -0,0 +1,17 @@ +/**************************************************************************** + * arch/arm/src/stm32l0/hardware/stm32_memorymap.h + * + * SPDX-License-Identifier: Apache-2.0 + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32L0_HARDWARE_STM32_MEMORYMAP_H +#define __ARCH_ARM_SRC_STM32L0_HARDWARE_STM32_MEMORYMAP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "hardware/stm32l0_memorymap.h" + +#endif /* __ARCH_ARM_SRC_STM32L0_HARDWARE_STM32_MEMORYMAP_H */ diff --git a/arch/arm/src/stm32l0/hardware/stm32_pinmap.h b/arch/arm/src/stm32l0/hardware/stm32_pinmap.h new file mode 100644 index 0000000000000..680c386947b24 --- /dev/null +++ b/arch/arm/src/stm32l0/hardware/stm32_pinmap.h @@ -0,0 +1,17 @@ +/**************************************************************************** + * arch/arm/src/stm32l0/hardware/stm32_pinmap.h + * + * SPDX-License-Identifier: Apache-2.0 + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32L0_HARDWARE_STM32_PINMAP_H +#define __ARCH_ARM_SRC_STM32L0_HARDWARE_STM32_PINMAP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "hardware/stm32l0_pinmap.h" + +#endif /* __ARCH_ARM_SRC_STM32L0_HARDWARE_STM32_PINMAP_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32l0_exti.h b/arch/arm/src/stm32l0/hardware/stm32l0_exti.h similarity index 96% rename from arch/arm/src/stm32f0l0g0/hardware/stm32l0_exti.h rename to arch/arm/src/stm32l0/hardware/stm32l0_exti.h index 4f246ccd8f734..dea6972eae5a4 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32l0_exti.h +++ b/arch/arm/src/stm32l0/hardware/stm32l0_exti.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32l0_exti.h + * arch/arm/src/stm32l0/hardware/stm32l0_exti.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32L0_EXTI_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32L0_EXTI_H +#ifndef __ARCH_ARM_SRC_STM32L0_HARDWARE_STM32L0_EXTI_H +#define __ARCH_ARM_SRC_STM32L0_HARDWARE_STM32L0_EXTI_H /**************************************************************************** * Included Files @@ -116,4 +116,4 @@ #define EXTI_PR_SHIFT (0) /* Bits 0-X: Pending bit for all lines */ #define EXTI_PR_MASK STM32_EXTI_MASK -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32L0_EXTI_H */ +#endif /* __ARCH_ARM_SRC_STM32L0_HARDWARE_STM32L0_EXTI_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32l0_flash.h b/arch/arm/src/stm32l0/hardware/stm32l0_flash.h similarity index 95% rename from arch/arm/src/stm32f0l0g0/hardware/stm32l0_flash.h rename to arch/arm/src/stm32l0/hardware/stm32l0_flash.h index 489d8588f185b..2f22a50f7f8e0 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32l0_flash.h +++ b/arch/arm/src/stm32l0/hardware/stm32l0_flash.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32l0_flash.h + * arch/arm/src/stm32l0/hardware/stm32l0_flash.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32L0_FLASH_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32L0_FLASH_H +#ifndef __ARCH_ARM_SRC_STM32L0_HARDWARE_STM32L0_FLASH_H +#define __ARCH_ARM_SRC_STM32L0_HARDWARE_STM32L0_FLASH_H /**************************************************************************** * Included Files @@ -102,4 +102,4 @@ #define FLASH_SR_OPTVERRUSR (1 << 12) /* Bit 12: Option UserValidity Error */ #define FLASH_SR_RDERR (1 << 13) /* Bit 13: Read protected error */ -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32L0_FLASH_H */ +#endif /* __ARCH_ARM_SRC_STM32L0_HARDWARE_STM32L0_FLASH_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32l0_memorymap.h b/arch/arm/src/stm32l0/hardware/stm32l0_memorymap.h similarity index 96% rename from arch/arm/src/stm32f0l0g0/hardware/stm32l0_memorymap.h rename to arch/arm/src/stm32l0/hardware/stm32l0_memorymap.h index 30da782402d28..dfdb2b3c4bcc3 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32l0_memorymap.h +++ b/arch/arm/src/stm32l0/hardware/stm32l0_memorymap.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32l0_memorymap.h + * arch/arm/src/stm32l0/hardware/stm32l0_memorymap.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32L0_MEMORYMAP_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32L0_MEMORYMAP_H +#ifndef __ARCH_ARM_SRC_STM32L0_HARDWARE_STM32L0_MEMORYMAP_H +#define __ARCH_ARM_SRC_STM32L0_HARDWARE_STM32L0_MEMORYMAP_H /**************************************************************************** * Pre-processor Definitions @@ -118,4 +118,4 @@ #define STM32_SYSMEM_UID 0x1ff80050 /* The 96-bit unique device identifier */ -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32L0_MEMORYMAP_H */ +#endif /* __ARCH_ARM_SRC_STM32L0_HARDWARE_STM32L0_MEMORYMAP_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32l0_pinmap.h b/arch/arm/src/stm32l0/hardware/stm32l0_pinmap.h similarity index 98% rename from arch/arm/src/stm32f0l0g0/hardware/stm32l0_pinmap.h rename to arch/arm/src/stm32l0/hardware/stm32l0_pinmap.h index a47d0df7245ac..9e18b9be9abe4 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32l0_pinmap.h +++ b/arch/arm/src/stm32l0/hardware/stm32l0_pinmap.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32l0_pinmap.h + * arch/arm/src/stm32l0/hardware/stm32l0_pinmap.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32L0_PINMAP_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32L0_PINMAP_H +#ifndef __ARCH_ARM_SRC_STM32L0_HARDWARE_STM32L0_PINMAP_H +#define __ARCH_ARM_SRC_STM32L0_HARDWARE_STM32L0_PINMAP_H /**************************************************************************** * Included Files @@ -326,4 +326,4 @@ /* TODO: LPUART */ -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32L0_PINMAP_H */ +#endif /* __ARCH_ARM_SRC_STM32L0_HARDWARE_STM32L0_PINMAP_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32l0_pwr.h b/arch/arm/src/stm32l0/hardware/stm32l0_pwr.h similarity index 95% rename from arch/arm/src/stm32f0l0g0/hardware/stm32l0_pwr.h rename to arch/arm/src/stm32l0/hardware/stm32l0_pwr.h index b5c00fa05e000..9f98c41d29467 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32l0_pwr.h +++ b/arch/arm/src/stm32l0/hardware/stm32l0_pwr.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32l0_pwr.h + * arch/arm/src/stm32l0/hardware/stm32l0_pwr.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32L0_PWR_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32L0_PWR_H +#ifndef __ARCH_ARM_SRC_STM32L0_HARDWARE_STM32L0_PWR_H +#define __ARCH_ARM_SRC_STM32L0_HARDWARE_STM32L0_PWR_H /**************************************************************************** * Included Files @@ -91,4 +91,4 @@ #define PWR_CSR_EWUP2 (1 << 9) /* Bit 9: Enable WKUP2 pin */ #define PWR_CSR_EWUP3 (1 << 10) /* Bit 10: Enable WKUP3 pin */ -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32L0_PWR_H */ +#endif /* __ARCH_ARM_SRC_STM32L0_HARDWARE_STM32L0_PWR_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32l0_rcc.h b/arch/arm/src/stm32l0/hardware/stm32l0_rcc.h similarity index 99% rename from arch/arm/src/stm32f0l0g0/hardware/stm32l0_rcc.h rename to arch/arm/src/stm32l0/hardware/stm32l0_rcc.h index 42a19e5010088..1b924ce687016 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32l0_rcc.h +++ b/arch/arm/src/stm32l0/hardware/stm32l0_rcc.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32l0_rcc.h + * arch/arm/src/stm32l0/hardware/stm32l0_rcc.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32L0_RCC_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32L0_RCC_H +#ifndef __ARCH_ARM_SRC_STM32L0_HARDWARE_STM32L0_RCC_H +#define __ARCH_ARM_SRC_STM32L0_HARDWARE_STM32L0_RCC_H /**************************************************************************** * Pre-processor Definitions @@ -538,4 +538,4 @@ #define RCC_CSR_WWDGRSTF (1 << 30) /* Bit 30: WWDG reset flag */ #define RCC_CSR_LPWRRSTF (1 << 31) /* Bit 31: Low-power reset flag */ -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32L0_RCC_H */ +#endif /* __ARCH_ARM_SRC_STM32L0_HARDWARE_STM32L0_RCC_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32l0_syscfg.h b/arch/arm/src/stm32l0/hardware/stm32l0_syscfg.h similarity index 97% rename from arch/arm/src/stm32f0l0g0/hardware/stm32l0_syscfg.h rename to arch/arm/src/stm32l0/hardware/stm32l0_syscfg.h index 85d28dc0ce9c5..e3dd1bf71592b 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32l0_syscfg.h +++ b/arch/arm/src/stm32l0/hardware/stm32l0_syscfg.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32l0_syscfg.h + * arch/arm/src/stm32l0/hardware/stm32l0_syscfg.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32L0_SYSCFG_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32L0_SYSCFG_H +#ifndef __ARCH_ARM_SRC_STM32L0_HARDWARE_STM32L0_SYSCFG_H +#define __ARCH_ARM_SRC_STM32L0_HARDWARE_STM32L0_SYSCFG_H /**************************************************************************** * Included Files @@ -132,4 +132,4 @@ #define SYSCFG_EXTICR4_EXTI15_SHIFT (12) /* Bits 12-15: EXTI 15 configuration */ #define SYSCFG_EXTICR4_EXTI15_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR4_EXTI15_SHIFT) -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32L0_SYSCFG_H */ +#endif /* __ARCH_ARM_SRC_STM32L0_HARDWARE_STM32L0_SYSCFG_H */ diff --git a/arch/arm/src/stm32l0/stm32.h b/arch/arm/src/stm32l0/stm32.h new file mode 100644 index 0000000000000..cdcdb2d4aa714 --- /dev/null +++ b/arch/arm/src/stm32l0/stm32.h @@ -0,0 +1,54 @@ +/**************************************************************************** + * arch/arm/src/stm32l0/stm32.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32L0_STM32_H +#define __ARCH_ARM_SRC_STM32L0_STM32_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include +#include + +#include "arm_internal.h" + +/* Peripherals **************************************************************/ + +#include "chip.h" +#include "stm32_dma.h" +#include "stm32_gpio.h" +#include "stm32_i2c.h" +#include "stm32_pwr.h" +#include "stm32_rcc.h" +#include "stm32_spi.h" +#include "stm32_uart.h" +#include "stm32_lowputc.h" +#include "stm32_adc.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#endif /* __ARCH_ARM_SRC_STM32L0_STM32_H */ diff --git a/arch/arm/src/stm32l0/stm32_rcc.c b/arch/arm/src/stm32l0/stm32_rcc.c new file mode 100644 index 0000000000000..a41366fdfeb08 --- /dev/null +++ b/arch/arm/src/stm32l0/stm32_rcc.c @@ -0,0 +1,220 @@ +/**************************************************************************** + * arch/arm/src/stm32l0/stm32_rcc.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include + +#include "arm_internal.h" +#include "hardware/stm32_flash.h" +#include "stm32_rcc.h" +#include "stm32_hsi48_m0_v1.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifdef CONFIG_STM32_RNG +# ifndef STM32_USE_CLK48 +# error RNG requires CLK48 enabled +# endif +#endif + +#ifdef CONFIG_STM32_USB +# ifndef STM32_USE_CLK48 +# error USB requires CLK48 enabled +# endif +#endif + +static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1, + "Configure BOARD_LOOPSPERMSEC to non-default value."); + +/* Allow up to 100 milliseconds for the high speed clock to become ready. + * that is a very long delay, but if the clock does not become ready we are + * hosed anyway. + */ + +#define HSERDY_TIMEOUT (100 * CONFIG_BOARD_LOOPSPERMSEC) + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/* Include chip-specific clocking initialization logic */ + +#include "stm32l0_rcc.c" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: rcc_resetbkp + * + * Description: + * The RTC needs to reset the Backup Domain to change RTCSEL and resetting + * the Backup Domain renders to disabling the LSE as consequence. + * In order to avoid resetting the Backup Domain when we already configured + * LSE we will reset the Backup Domain early (here). + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +#if defined(CONFIG_STM32_RTC) && defined(CONFIG_STM32_PWR) +static inline void rcc_resetbkp(void) +{ + uint32_t regval; + + /* Check if the RTC is already configured */ + + stm32_pwr_initbkp(false); + + regval = getreg32(RTC_MAGIC_REG); + if (regval != RTC_MAGIC && regval != RTC_MAGIC_TIME_SET) + { + stm32_pwr_enablebkp(true); + + /* We might be changing RTCSEL - to ensure such changes work, we must + * reset the backup domain (having backed up the RTC_MAGIC token) + */ + + modifyreg32(STM32_RCC_BDCR, 0, RCC_BDCR_BDRST); + modifyreg32(STM32_RCC_BDCR, RCC_BDCR_BDRST, 0); + + stm32_pwr_enablebkp(false); + } +} +#else +# define rcc_resetbkp() +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_clockconfig + * + * Description: + * Called to establish the clock settings based on the values in board.h. + * This function (by default) will reset most everything, enable the PLL, + * and enable peripheral clocking for all peripherals enabled in the NuttX + * configuration file. + * + * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then + * clocking will be enabled by an externally provided, board-specific + * function called stm32_board_clockconfig(). + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void stm32_clockconfig(void) +{ + /* Make sure that we are starting in the reset state */ + + rcc_reset(); + + /* Reset backup domain if appropriate */ + + rcc_resetbkp(); + +#if defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) + /* Invoke Board Custom Clock Configuration */ + + stm32_board_clockconfig(); + +#else + /* Invoke standard, fixed clock configuration based on definitions + * in board.h + */ + + stm32_stdclockconfig(); + +#endif + + /* Enable peripheral clocking */ + + rcc_enableperipherals(); +} + +/**************************************************************************** + * Name: stm32_clockenable + * + * Description: + * Re-enable the clock and restore the clock settings based on settings in + * board.h. This function is only available to support low-power modes of + * operation: When re-awakening from deep-sleep modes, it is necessary to + * re-enable/re-start the PLL + * + * This functional performs a subset of the operations performed by + * stm32_clockconfig(): It does not reset any devices, and it does not + * reset the currently enabled peripheral clocks. + * + * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then + * clocking will be enabled by an externally provided, board-specific + * function called stm32_board_clockconfig(). + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_PM +void stm32_clockenable(void) +{ +#if defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) + /* Invoke Board Custom Clock Configuration */ + + stm32_board_clockconfig(); + +#else + /* Invoke standard, fixed clock configuration based on definitions + * in board.h + */ + + stm32_stdclockconfig(); + +#endif +} +#endif diff --git a/arch/arm/src/stm32f0l0g0/stm32l0_rcc.c b/arch/arm/src/stm32l0/stm32l0_rcc.c similarity index 92% rename from arch/arm/src/stm32f0l0g0/stm32l0_rcc.c rename to arch/arm/src/stm32l0/stm32l0_rcc.c index 558ee7a23287c..79359bb30bf61 100644 --- a/arch/arm/src/stm32f0l0g0/stm32l0_rcc.c +++ b/arch/arm/src/stm32l0/stm32l0_rcc.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32l0_rcc.c + * arch/arm/src/stm32l0/stm32l0_rcc.c * * SPDX-License-Identifier: Apache-2.0 * @@ -51,10 +51,10 @@ static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1, /* Determine if board wants to use HSI48 as 48 MHz oscillator. */ -#if defined(CONFIG_STM32F0L0G0_HAVE_HSI48) && defined(STM32_USE_CLK48) +#if defined(CONFIG_STM32_HAVE_HSI48) && defined(STM32_USE_CLK48) # if STM32_CLK48_SEL == RCC_CCIPR_CLK48SEL_HSI48 # define STM32_USE_HSI48 -# ifndef CONFIG_STM32F0L0G0_VREFINT +# ifndef CONFIG_STM32_VREFINT # error VREFINT must be enabled if HSI48 used # endif # endif @@ -133,31 +133,31 @@ static inline void rcc_enableahb(void) regval = getreg32(STM32_RCC_AHBENR); -#ifdef CONFIG_STM32F0L0G0_DMA1 +#ifdef CONFIG_STM32_DMA1 /* DMA 1 clock enable */ regval |= RCC_AHBENR_DMA1EN; #endif -#ifdef CONFIG_STM32F0L0G0_MIF +#ifdef CONFIG_STM32_MIF /* Memory interface clock enable */ regval |= RCC_AHBENR_MIFEN; #endif -#ifdef CONFIG_STM32F0L0G0_CRC +#ifdef CONFIG_STM32_CRC /* CRC clock enable */ regval |= RCC_AHBENR_CRCEN; #endif -#ifdef CONFIG_STM32F0L0G0_TSC +#ifdef CONFIG_STM32_TSC /* TSC clock enable */ regval |= RCC_AHBENR_TSCEN; #endif -#ifdef CONFIG_STM32F0L0G0_RNG +#ifdef CONFIG_STM32_RNG /* Random number generator clock enable */ regval |= RCC_AHBENR_RNGEN; @@ -184,115 +184,115 @@ static inline void rcc_enableapb1(void) regval = getreg32(STM32_RCC_APB1ENR); -#ifdef CONFIG_STM32F0L0G0_TIM2 +#ifdef CONFIG_STM32_TIM2 /* Timer 2 clock enable */ regval |= RCC_APB1ENR_TIM2EN; #endif -#ifdef CONFIG_STM32F0L0G0_TIM3 +#ifdef CONFIG_STM32_TIM3 /* Timer 3 clock enable */ regval |= RCC_APB1ENR_TIM3EN; #endif -#ifdef CONFIG_STM32F0L0G0_TIM6 +#ifdef CONFIG_STM32_TIM6 /* Timer 6 clock enable */ regval |= RCC_APB1ENR_TIM6EN; #endif -#ifdef CONFIG_STM32F0L0G0_TIM7 +#ifdef CONFIG_STM32_TIM7 /* Timer 7 clock enable */ regval |= RCC_APB1ENR_TIM7EN; #endif -#ifdef CONFIG_STM32F0L0G0_LCD +#ifdef CONFIG_STM32_LCD /* LCD clock enable */ regval |= RCC_APB1ENR_LCDEN; #endif -#ifdef CONFIG_STM32F0L0G0_WWDG +#ifdef CONFIG_STM32_WWDG /* Window Watchdog clock enable */ regval |= RCC_APB1ENR_WWDGEN; #endif -#ifdef CONFIG_STM32F0L0G0_SPI2 +#ifdef CONFIG_STM32_SPI2 /* SPI 2 clock enable */ regval |= RCC_APB1ENR_SPI2EN; #endif -#ifdef CONFIG_STM32F0L0G0_USART2 +#ifdef CONFIG_STM32_USART2 /* USART 2 clock enable */ regval |= RCC_APB1ENR_USART2EN; #endif -#ifdef CONFIG_STM32F0L0G0_USART3 +#ifdef CONFIG_STM32_USART3 /* USART 3 clock enable */ regval |= RCC_APB1ENR_USART3EN; #endif -#ifdef CONFIG_STM32F0L0G0_USART4 +#ifdef CONFIG_STM32_USART4 /* USART 4 clock enable */ regval |= RCC_APB1ENR_USART4EN; #endif -#ifdef CONFIG_STM32F0L0G0_USART5 +#ifdef CONFIG_STM32_USART5 /* USART 5 clock enable */ regval |= RCC_APB1ENR_USART5EN; #endif -#ifdef CONFIG_STM32F0L0G0_I2C1 +#ifdef CONFIG_STM32_I2C1 /* I2C 1 clock enable */ regval |= RCC_APB1ENR_I2C1EN; #endif -#ifdef CONFIG_STM32F0L0G0_I2C2 +#ifdef CONFIG_STM32_I2C2 /* I2C 2 clock enable */ regval |= RCC_APB1ENR_I2C2EN; #endif -#ifdef CONFIG_STM32F0L0G0_USB +#ifdef CONFIG_STM32_USB /* USB clock enable */ regval |= RCC_APB1ENR_USBEN; #endif -#ifdef CONFIG_STM32F0L0G0_CRS +#ifdef CONFIG_STM32_CRS /* Clock recovery system clock enable */ regval |= RCC_APB1ENR_CRSEN; #endif -#ifdef CONFIG_STM32F0L0G0_PWR +#ifdef CONFIG_STM32_PWR /* Power interface clock enable */ regval |= RCC_APB1ENR_PWREN; #endif -#ifdef CONFIG_STM32F0L0G0_DAC1 +#ifdef CONFIG_STM32_DAC1 /* DAC 1 interface clock enable */ regval |= RCC_APB1ENR_DAC1EN; #endif -#ifdef CONFIG_STM32F0L0G0_I2C3 +#ifdef CONFIG_STM32_I2C3 /* I2C 3 clock enable */ regval |= RCC_APB1ENR_I2C4EN; #endif -#ifdef CONFIG_STM32F0L0G0_LPTIM1 +#ifdef CONFIG_STM32_LPTIM1 /* LPTIM1 clock enable */ regval |= RCC_APB1ENR_LPTIM1EN; @@ -319,37 +319,37 @@ static inline void rcc_enableapb2(void) regval = getreg32(STM32_RCC_APB2ENR); -#ifdef CONFIG_STM32F0L0G0_SYSCFG +#ifdef CONFIG_STM32_SYSCFG /* SYSCFG clock */ regval |= RCC_APB2ENR_SYSCFGEN; #endif -#ifdef CONFIG_STM32F0L0G0_TIM21 +#ifdef CONFIG_STM32_TIM21 /* TIM21 Timer clock enable */ regval |= RCC_APB2ENR_TIM21EN; #endif -#ifdef CONFIG_STM32F0L0G0_TIM22 +#ifdef CONFIG_STM32_TIM22 /* TIM22 Timer clock enable */ regval |= RCC_APB2ENR_TIM10EN; #endif -#ifdef CONFIG_STM32F0L0G0_ADC1 +#ifdef CONFIG_STM32_ADC1 /* ADC 1 clock enable */ regval |= RCC_APB2ENR_ADC1EN; #endif -#ifdef CONFIG_STM32F0L0G0_SPI1 +#ifdef CONFIG_STM32_SPI1 /* SPI 1 clock enable */ regval |= RCC_APB2ENR_SPI1EN; #endif -#ifdef CONFIG_STM32F0L0G0_USART1 +#ifdef CONFIG_STM32_USART1 /* USART1 clock enable */ regval |= RCC_APB2ENR_USART1EN; @@ -448,11 +448,11 @@ static inline bool stm32_rcc_enablehse(void) * ****************************************************************************/ -#ifndef CONFIG_ARCH_BOARD_STM32F0G0L0_CUSTOM_CLOCKCONFIG +#ifndef CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG static void stm32_stdclockconfig(void) { uint32_t regval; -#if defined(CONFIG_STM32F0L0G0_RTC_HSECLOCK) || defined(CONFIG_LCD_HSECLOCK) +#if defined(CONFIG_STM32_RTC_HSECLOCK) || defined(CONFIG_LCD_HSECLOCK) uint16_t pwrcr; #endif uint32_t pwr_vos; @@ -504,7 +504,7 @@ static void stm32_stdclockconfig(void) stm32_pwr_setvos(pwr_vos); -#if defined(CONFIG_STM32F0L0G0_RTC_HSECLOCK) || defined(CONFIG_LCD_HSECLOCK) +#if defined(CONFIG_STM32_RTC_HSECLOCK) || defined(CONFIG_LCD_HSECLOCK) /* If RTC / LCD selects HSE as clock source, the RTC prescaler * needs to be set before HSEON bit is set. */ @@ -683,8 +683,8 @@ static void stm32_stdclockconfig(void) while ((getreg32(STM32_RCC_CFGR) & RCC_CFGR_SWS_MASK) != STM32_SYSCLK_SWS); -#if defined(CONFIG_STM32F0L0G0_IWDG) || \ - defined(CONFIG_STM32F0L0G0_RTC_LSICLOCK) || defined(CONFIG_LCD_LSICLOCK) +#if defined(CONFIG_STM32_IWDG) || \ + defined(CONFIG_STM32_RTC_LSICLOCK) || defined(CONFIG_LCD_LSICLOCK) /* Low speed internal clock source LSI * * TODO: There is another case where the LSI needs to @@ -695,7 +695,7 @@ static void stm32_stdclockconfig(void) #endif -#if defined(CONFIG_STM32F0L0G0_RTC_LSECLOCK) || defined(CONFIG_LCD_LSECLOCK) +#if defined(CONFIG_STM32_RTC_LSECLOCK) || defined(CONFIG_LCD_LSECLOCK) /* Low speed external clock source LSE * * TODO: There is another case where the LSE needs to @@ -722,7 +722,7 @@ static void stm32_stdclockconfig(void) * ****************************************************************************/ -#ifdef CONFIG_STM32F0L0G0_VREFINT +#ifdef CONFIG_STM32_VREFINT static void vrefint_enable(void) { uint32_t regval = 0; @@ -759,7 +759,7 @@ static inline void rcc_enableperipherals(void) rcc_enableahb(); rcc_enableapb2(); rcc_enableapb1(); -#ifdef CONFIG_STM32F0L0G0_VREFINT +#ifdef CONFIG_STM32_VREFINT vrefint_enable(); #endif diff --git a/arch/arm/src/stm32l1/CMakeLists.txt b/arch/arm/src/stm32l1/CMakeLists.txt new file mode 100644 index 0000000000000..1067ff1910153 --- /dev/null +++ b/arch/arm/src/stm32l1/CMakeLists.txt @@ -0,0 +1,28 @@ +# ############################################################################## +# arch/arm/src/stm32l1/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(SRCS) + +list(APPEND SRCS stm32_rcc.c) + +target_sources(arch PRIVATE ${SRCS}) +add_subdirectory(${NUTTX_DIR}/arch/arm/src/common/stm32 stm32_common) diff --git a/arch/arm/src/stm32l1/Kconfig b/arch/arm/src/stm32l1/Kconfig new file mode 100644 index 0000000000000..1fdceba40c2bd --- /dev/null +++ b/arch/arm/src/stm32l1/Kconfig @@ -0,0 +1,352 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# +comment "STM32 L1 configuration" + +if ARCH_CHIP_STM32L1 + +choice + prompt "STM32L1 Chip Selection" + depends on ARCH_CHIP_STM32L1 + +config ARCH_CHIP_STM32L151C6 + bool "STM32L151C6" + select STM32_STM32L15XX + select STM32L1_LOWDENSITY + ---help--- + STM32L 48-pin EnergyLite, 32KB FLASH, 10KB SRAM, 4KB EEPROM + +config ARCH_CHIP_STM32L151C8 + bool "STM32L151C8" + select STM32_STM32L15XX + select STM32L1_LOWDENSITY + ---help--- + STM32L 48-pin EnergyLite, 64KB FLASH, 10KB SRAM, 4KB EEPROM + +config ARCH_CHIP_STM32L151CB + bool "STM32L151CB" + select STM32_STM32L15XX + select STM32L1_LOWDENSITY + ---help--- + STM32L 48-pin EnergyLite, 128KB FLASH, 16KB SRAM, 4KB EEPROM + +config ARCH_CHIP_STM32L151R6 + bool "STM32L151R6" + select STM32_STM32L15XX + select STM32L1_LOWDENSITY + ---help--- + STM32L 64-pin EnergyLite, 32KB FLASH, 10KB SRAM, 4KB EEPROM + +config ARCH_CHIP_STM32L151R8 + bool "STM32L151R8" + select STM32_STM32L15XX + select STM32L1_LOWDENSITY + ---help--- + STM32L 64-pin EnergyLite, 64KB FLASH, 10KB SRAM, 4KB EEPROM + +config ARCH_CHIP_STM32L151RB + bool "STM32L151RB" + select STM32_STM32L15XX + select STM32L1_LOWDENSITY + ---help--- + STM32L 64-pin EnergyLite, 128KB FLASH, 16KB SRAM, 4KB EEPROM + +config ARCH_CHIP_STM32L151V6 + bool "STM32L151V6" + select STM32_STM32L15XX + select STM32L1_LOWDENSITY + ---help--- + STM32L 100-pin EnergyLite, 32KB FLASH, 10KB SRAM, 4KB EEPROM + +config ARCH_CHIP_STM32L151V8 + bool "STM32L151V8" + select STM32_STM32L15XX + select STM32L1_LOWDENSITY + ---help--- + STM32L 100-pin EnergyLite, 64KB FLASH, 10KB SRAM, 4KB EEPROM + +config ARCH_CHIP_STM32L151VB + bool "STM32L151VB" + select STM32_STM32L15XX + select STM32L1_LOWDENSITY + ---help--- + STM32L 100-pin EnergyLite, 128KB FLASH, 16KB SRAM, 4KB EEPROM + +config ARCH_CHIP_STM32L152C6 + bool "STM32L152C6" + select STM32_STM32L15XX + select STM32L1_LOWDENSITY + ---help--- + STM32L 48-pin EnergyLite, 32KB FLASH, 10KB SRAM, 4KB EEPROM with + 4x18 LCD interface + +config ARCH_CHIP_STM32L152C8 + bool "STM32L152C8" + select STM32_STM32L15XX + select STM32L1_LOWDENSITY + ---help--- + STM32L 48-pin EnergyLite, 64KB FLASH, 10KB SRAM, 4KB EEPROM with + 4x18 LCD interface + +config ARCH_CHIP_STM32L152CB + bool "STM32L152CB" + select STM32_STM32L15XX + select STM32L1_LOWDENSITY + ---help--- + STM32L 48-pin EnergyLite, 128KB FLASH, 16KB SRAM, 4KB EEPROM with + 4x18 LCD interface + +config ARCH_CHIP_STM32L152R6 + bool "STM32L152R6" + select STM32_STM32L15XX + select STM32L1_LOWDENSITY + ---help--- + STM32L 64-pin EnergyLite, 32KB FLASH, 10KB SRAM, 4KB EEPROM with + 4x32/8x28 LCD interface + +config ARCH_CHIP_STM32L152R8 + bool "STM32L152R8" + select STM32_STM32L15XX + select STM32L1_LOWDENSITY + ---help--- + STM32L 64-pin EnergyLite, 64KB FLASH, 10KB SRAM, 4KB EEPROM with + 4x32/8x28 LCD interface + +config ARCH_CHIP_STM32L152RB + bool "STM32L152RB" + select STM32_STM32L15XX + select STM32L1_LOWDENSITY + ---help--- + STM32L 64-pin EnergyLite, 128KB FLASH, 16KB SRAM, 4KB EEPROM with + 4x32/8x28 LCD interface + +config ARCH_CHIP_STM32L152V6 + bool "STM32L152V6" + select STM32_STM32L15XX + select STM32L1_LOWDENSITY + ---help--- + STM32L 100-pin EnergyLite, 32KB FLASH, 10KB SRAM, 4KB EEPROM with + 4x44/8x40 LCD interface + +config ARCH_CHIP_STM32L152V8 + bool "STM32L152V8" + select STM32_STM32L15XX + select STM32L1_LOWDENSITY + ---help--- + STM32L 100-pin EnergyLite, 64KB FLASH, 10KB SRAM, 4KB EEPROM with + 4x44/8x40 LCD interface + +config ARCH_CHIP_STM32L152VB + bool "STM32L152VB" + select STM32_STM32L15XX + select STM32L1_LOWDENSITY + ---help--- + STM32L 100-pin EnergyLite, 128KB FLASH, 16KB SRAM, 4KB EEPROM with + 4x44/8x40 LCD interface + +config ARCH_CHIP_STM32L152CC + bool "STM32L152CC" + select STM32_STM32L15XX + select STM32L1_MEDIUMPLUSDENSITY + ---help--- + STM32L 48-pin EnergyLite, 256KB FLASH, 32KB SRAM, 8KB EEPROM with + 4x18 LCD interface + +config ARCH_CHIP_STM32L152RC + bool "STM32L152RC" + select STM32_STM32L15XX + select STM32L1_MEDIUMPLUSDENSITY + ---help--- + STM32L 64-pin EnergyLite, 256KB FLASH, 32KB SRAM, 8KB EEPROM with + 4x32/8x28 LCD interface + +config ARCH_CHIP_STM32L152VC + bool "STM32L152VC" + select STM32_STM32L15XX + select STM32L1_MEDIUMPLUSDENSITY + ---help--- + STM32L 100-pin EnergyLite, 256KB FLASH, 32KB SRAM, 8KB EEPROM with + 4x44/8x40 LCD interface + +config ARCH_CHIP_STM32L151RE + bool "STM32L151RE" + select STM32_STM32L15XX + select STM32L1_HIGHDENSITY + +config ARCH_CHIP_STM32L152RE + bool "STM32L152RE" + select STM32_STM32L15XX + select STM32L1_HIGHDENSITY + +config ARCH_CHIP_STM32L151VE + bool "STM32L151VE" + select STM32_STM32L15XX + select STM32L1_HIGHDENSITY + +config ARCH_CHIP_STM32L152VE + bool "STM32L152VE" + select STM32_STM32L15XX + select STM32L1_HIGHDENSITY + +config ARCH_CHIP_STM32L151QE + bool "STM32L151QE" + select STM32_STM32L15XX + select STM32L1_HIGHDENSITY + +config ARCH_CHIP_STM32L152QE + bool "STM32L152QE" + select STM32_STM32L15XX + select STM32L1_HIGHDENSITY + +config ARCH_CHIP_STM32L151ZE + bool "STM32L151ZE" + select STM32_STM32L15XX + select STM32L1_HIGHDENSITY + +config ARCH_CHIP_STM32L152ZE + bool "STM32L152ZE" + select STM32_STM32L15XX + select STM32L1_HIGHDENSITY + +config ARCH_CHIP_STM32L162ZD + bool "STM32L162ZD" + select STM32_STM32L15XX + select STM32L1_HIGHDENSITY + select STM32_HAVE_AES + ---help--- + STM32L 144-pin EnergyLite, 384KB FLASH, 48KB SRAM, 12KB EEPROM with + 4x44/8x40 LCD interface + +config ARCH_CHIP_STM32L162VE + bool "STM32L162VE" + select STM32_STM32L15XX + select STM32L1_HIGHDENSITY + select STM32_HAVE_AES + ---help--- + STM32L 100-pin EnergyLite, 512KB FLASH, 80KB SRAM, 16KB EEPROM with + 4x44/8x40 LCD interface + +endchoice + +endif + +config STM32_STM32L15XX + bool + default n + select STM32_HAVE_DMA1 + select STM32_HAVE_COMP + select STM32_HAVE_DMA2 + select ARCH_CORTEXM3 + select STM32_ENERGYLITE + select STM32_HAVE_I2C1 + select STM32_HAVE_LCD + select STM32_HAVE_SPI1 + select STM32_HAVE_SYSCFG + select STM32_HAVE_USART1 + select STM32_HAVE_USART2 + select STM32_HAVE_USBDEV + select STM32_HAVE_DAC1 + select STM32_HAVE_I2C2 + select STM32_HAVE_SPI2 + select STM32_HAVE_SPI3 + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM3 + select STM32_HAVE_TIM4 + select STM32_HAVE_TIM9 + select STM32_HAVE_TIM10 + select STM32_HAVE_TIM11 + select STM32_HAVE_ADC2 + select STM32_HAVE_USART3 + select STM32_HAVE_RTC_SUBSECONDS if !STM32L1_LOWDENSITY + select STM32_HAVE_IP_AES_M3M4_V1 if STM32_HAVE_AES + select STM32_HAVE_IP_BBSRAM_M3M4_V1 + select STM32_HAVE_IP_BKP_M3M4_V1 + select STM32_HAVE_IP_CAN_BXCAN_M3M4_V1 + select STM32_HAVE_IP_CCM_M3M4_V1 if STM32_HAVE_CCM + select STM32_HAVE_IP_CRYPTO_M3M4_V1 + select STM32_HAVE_IP_DBGMCU_M3M4_V2 + select STM32_HAVE_IP_ADC_M3M4_V1 + select STM32_HAVE_COMMON_FOC + select STM32_HAVE_IP_DCMI_V1 + select STM32_HAVE_IP_DAC_M3M4_V1 + select STM32_HAVE_IP_DFUMODE_M3M4_V1 + select STM32_HAVE_IP_DMA_V1 + select STM32_HAVE_IP_DMA_V1_8CH + select STM32_HAVE_IP_EXTI_V1 + select STM32_HAVE_IP_ETHMAC_M3M4_V1 if STM32_HAVE_ETHMAC + select STM32_HAVE_IP_FLASH_M3M4_V1 + select STM32_HAVE_IP_FLASH_M3M4_L1 + select STM32_HAVE_IP_FMC_M3M4_V1 if STM32_HAVE_FMC + select STM32_HAVE_IP_FREERUN_M3M4_V1 + select STM32_HAVE_IP_FSMC_M3M4_V1 if STM32_HAVE_FSMC + select STM32_HAVE_IP_GPIO_M3M4_V1 + select STM32_HAVE_IP_HRTIM_M3M4_V1 if STM32_HAVE_HRTIM1 + select STM32_HAVE_IP_I2C_M3M4_V1 + select STM32_HAVE_IP_I2S_M3M4_V1 + select STM32_HAVE_IP_ONESHOT_M3M4_V1 + select STM32_HAVE_IP_PWR_M3M4_V1 + select STM32_HAVE_IP_RTC_M3M4_V1 + select STM32_HAVE_IP_RTCC_M3M4_L1 if !STM32_HAVE_RTC_COUNTER + select STM32_HAVE_IP_SDIO_M3M4_V1 + select STM32_HAVE_IP_SPI_V1 + select STM32_HAVE_IP_SYSCFG_M3M4_V1 + select STM32_HAVE_IP_TIMERS_M3M4_V1 + select STM32_HAVE_IP_USART_V2 + select STM32_HAVE_IP_USBDEV_M3M4_V1 if STM32_HAVE_USBDEV + select STM32_HAVE_IP_USBFS_M3M4_V1 if STM32_HAVE_USBFS + select STM32_HAVE_IP_OTGFS_M3M4_V1 if STM32_HAVE_OTGFS + select STM32_HAVE_IP_WDG_M3M4_V1 + + +config STM32L1_MEDIUMPLUSDENSITY + bool + default n + +config STM32L1_HIGHDENSITY + bool + default n + select STM32_HAVE_FSMC + select STM32_HAVE_USART3 + select STM32_HAVE_UART4 + select STM32_HAVE_UART5 + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM5 + select STM32_HAVE_TIM6 + select STM32_HAVE_TIM7 + select STM32_HAVE_TIM8 + select STM32_HAVE_ADC2 + select STM32_HAVE_ADC3 + select STM32_HAVE_CAN1 + +config STM32L1_MEDIUMDENSITY + bool + default n + select STM32_HAVE_USART3 + select STM32_HAVE_UART4 + select STM32_HAVE_UART5 + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM5 + select STM32_HAVE_TIM6 + select STM32_HAVE_TIM7 + select STM32_HAVE_TIM8 + select STM32_HAVE_ADC2 + select STM32_HAVE_ADC3 + select STM32_HAVE_CAN1 + +config STM32L1_LOWDENSITY + bool + default n + select STM32_HAVE_USART3 + select STM32_HAVE_UART4 + select STM32_HAVE_UART5 + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM5 + select STM32_HAVE_TIM6 + select STM32_HAVE_TIM7 + select STM32_HAVE_TIM8 + select STM32_HAVE_ADC2 + select STM32_HAVE_CAN1 diff --git a/arch/arm/src/stm32l1/Make.defs b/arch/arm/src/stm32l1/Make.defs new file mode 100644 index 0000000000000..f0e835622db56 --- /dev/null +++ b/arch/arm/src/stm32l1/Make.defs @@ -0,0 +1,27 @@ +############################################################################ +# arch/arm/src/stm32l1/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include armv7-m/Make.defs + +CHIP_CSRCS = stm32_rcc.c + +include common/stm32/Make.defs diff --git a/arch/arm/src/stm32l1/chip.h b/arch/arm/src/stm32l1/chip.h new file mode 100644 index 0000000000000..b0857c705039f --- /dev/null +++ b/arch/arm/src/stm32l1/chip.h @@ -0,0 +1,59 @@ +/**************************************************************************** + * arch/arm/src/stm32l1/chip.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32L1_CHIP_H +#define __ARCH_ARM_SRC_STM32L1_CHIP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/* Include the chip capabilities file */ + +#include + +/* Include the chip interrupt definition file */ + +#include + +/* Include the chip memory map */ + +#include "hardware/stm32_memorymap.h" + +/* Include the chip pinmap */ + +#include "hardware/stm32_pinmap.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Provide the required number of peripheral interrupt vector + * definitions as * well. The definition STM32_IRQ_NEXTINTS simply comes + * from the chip-specific * IRQ header file included by arch/stm32/irq.h. + */ + +#define ARMV7M_PERIPHERAL_INTERRUPTS STM32_IRQ_NEXTINTS + +#endif /* __ARCH_ARM_SRC_STM32L1_CHIP_H */ diff --git a/arch/arm/src/stm32l1/hardware/stm32_memorymap.h b/arch/arm/src/stm32l1/hardware/stm32_memorymap.h new file mode 100644 index 0000000000000..bbe24f67a2ca6 --- /dev/null +++ b/arch/arm/src/stm32l1/hardware/stm32_memorymap.h @@ -0,0 +1,17 @@ +/**************************************************************************** + * arch/arm/src/stm32l1/hardware/stm32_memorymap.h + * + * SPDX-License-Identifier: Apache-2.0 + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32L1_HARDWARE_STM32_MEMORYMAP_H +#define __ARCH_ARM_SRC_STM32L1_HARDWARE_STM32_MEMORYMAP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "hardware/stm32l15xxx_memorymap.h" + +#endif /* __ARCH_ARM_SRC_STM32L1_HARDWARE_STM32_MEMORYMAP_H */ diff --git a/arch/arm/src/stm32l1/hardware/stm32_pinmap.h b/arch/arm/src/stm32l1/hardware/stm32_pinmap.h new file mode 100644 index 0000000000000..9bbf21f22811c --- /dev/null +++ b/arch/arm/src/stm32l1/hardware/stm32_pinmap.h @@ -0,0 +1,17 @@ +/**************************************************************************** + * arch/arm/src/stm32l1/hardware/stm32_pinmap.h + * + * SPDX-License-Identifier: Apache-2.0 + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32L1_HARDWARE_STM32_PINMAP_H +#define __ARCH_ARM_SRC_STM32L1_HARDWARE_STM32_PINMAP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "hardware/stm32l15xxx_pinmap.h" + +#endif /* __ARCH_ARM_SRC_STM32L1_HARDWARE_STM32_PINMAP_H */ diff --git a/arch/arm/src/stm32/hardware/stm32l15xxx_aes.h b/arch/arm/src/stm32l1/hardware/stm32l15xxx_aes.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32l15xxx_aes.h rename to arch/arm/src/stm32l1/hardware/stm32l15xxx_aes.h index c68fbc44d66e0..101ad5e19c4be 100644 --- a/arch/arm/src/stm32/hardware/stm32l15xxx_aes.h +++ b/arch/arm/src/stm32l1/hardware/stm32l15xxx_aes.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32l15xxx_aes.h + * arch/arm/src/stm32l1/hardware/stm32l15xxx_aes.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/hardware/stm32l15xxx_gpio.h b/arch/arm/src/stm32l1/hardware/stm32l15xxx_gpio.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32l15xxx_gpio.h rename to arch/arm/src/stm32l1/hardware/stm32l15xxx_gpio.h index 49dd7919b2268..903605e60af5e 100644 --- a/arch/arm/src/stm32/hardware/stm32l15xxx_gpio.h +++ b/arch/arm/src/stm32l1/hardware/stm32l15xxx_gpio.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32l15xxx_gpio.h + * arch/arm/src/stm32l1/hardware/stm32l15xxx_gpio.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/hardware/stm32l15xxx_memorymap.h b/arch/arm/src/stm32l1/hardware/stm32l15xxx_memorymap.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32l15xxx_memorymap.h rename to arch/arm/src/stm32l1/hardware/stm32l15xxx_memorymap.h index b1c2ba9ce8339..4a59b4c86caac 100644 --- a/arch/arm/src/stm32/hardware/stm32l15xxx_memorymap.h +++ b/arch/arm/src/stm32l1/hardware/stm32l15xxx_memorymap.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32l15xxx_memorymap.h + * arch/arm/src/stm32l1/hardware/stm32l15xxx_memorymap.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/hardware/stm32l15xxx_pinmap.h b/arch/arm/src/stm32l1/hardware/stm32l15xxx_pinmap.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32l15xxx_pinmap.h rename to arch/arm/src/stm32l1/hardware/stm32l15xxx_pinmap.h index 9211c8c64bec7..75294a51a742c 100644 --- a/arch/arm/src/stm32/hardware/stm32l15xxx_pinmap.h +++ b/arch/arm/src/stm32l1/hardware/stm32l15xxx_pinmap.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32l15xxx_pinmap.h + * arch/arm/src/stm32l1/hardware/stm32l15xxx_pinmap.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/hardware/stm32l15xxx_rcc.h b/arch/arm/src/stm32l1/hardware/stm32l15xxx_rcc.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32l15xxx_rcc.h rename to arch/arm/src/stm32l1/hardware/stm32l15xxx_rcc.h index 0217a9a79d948..c557971f1a356 100644 --- a/arch/arm/src/stm32/hardware/stm32l15xxx_rcc.h +++ b/arch/arm/src/stm32l1/hardware/stm32l15xxx_rcc.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32l15xxx_rcc.h + * arch/arm/src/stm32l1/hardware/stm32l15xxx_rcc.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/hardware/stm32l15xxx_syscfg.h b/arch/arm/src/stm32l1/hardware/stm32l15xxx_syscfg.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32l15xxx_syscfg.h rename to arch/arm/src/stm32l1/hardware/stm32l15xxx_syscfg.h index 3e6dfa2ddbe24..9cba220f8c207 100644 --- a/arch/arm/src/stm32/hardware/stm32l15xxx_syscfg.h +++ b/arch/arm/src/stm32l1/hardware/stm32l15xxx_syscfg.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32l15xxx_syscfg.h + * arch/arm/src/stm32l1/hardware/stm32l15xxx_syscfg.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32l1/stm32.h b/arch/arm/src/stm32l1/stm32.h new file mode 100644 index 0000000000000..2aed55b33cac0 --- /dev/null +++ b/arch/arm/src/stm32l1/stm32.h @@ -0,0 +1,69 @@ +/**************************************************************************** + * arch/arm/src/stm32l1/stm32.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32_STM32_H +#define __ARCH_ARM_SRC_STM32_STM32_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include +#include + +#include "arm_internal.h" + +/* Peripherals **************************************************************/ + +#include "chip.h" +#include "stm32_adc.h" +#include "stm32_can.h" +#include "stm32_comp.h" +#include "stm32_dbgmcu.h" +#include "stm32_dma.h" +#include "stm32_dac_m3m4_v1.h" +#include "stm32_exti.h" +#include "stm32_flash.h" +#include "stm32_fmc_m3m4_v1.h" +#include "stm32_fsmc_m3m4_v1.h" +#include "stm32_gpio.h" +#include "stm32_i2c.h" +#include "stm32_ltdc_m3m4_v1.h" +#include "stm32_opamp_m3m4_v1.h" +#include "stm32_pwr.h" +#include "stm32_rcc.h" +#include "stm32_rtc.h" +#include "stm32_sdio_m3m4_v1.h" +#include "stm32_spi.h" +#include "stm32_i2s.h" +#include "stm32_tim.h" +#include "stm32_uart.h" +#if defined(CONFIG_USBDEV) && defined(CONFIG_STM32_USB) +# include "stm32_usbdev.h" +#endif +#include "stm32_wdg.h" +#include "stm32_lowputc.h" +#include "stm32_eth_m3m4_v1.h" + +#endif /* __ARCH_ARM_SRC_STM32_STM32_H */ diff --git a/arch/arm/src/stm32l1/stm32_rcc.c b/arch/arm/src/stm32l1/stm32_rcc.c new file mode 100644 index 0000000000000..044d6aea475dd --- /dev/null +++ b/arch/arm/src/stm32l1/stm32_rcc.c @@ -0,0 +1,234 @@ +/**************************************************************************** + * arch/arm/src/stm32l1/stm32_rcc.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include + +#include "arm_internal.h" +#include "chip.h" +#include "stm32_gpio.h" +#include "stm32_rcc.h" +#include "stm32_rtc.h" +#include "stm32_flash.h" +#include "stm32.h" +#include "stm32_waste.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1, + "Configure BOARD_LOOPSPERMSEC to non-default value."); + +/* Allow up to 100 milliseconds for the high speed clock to become ready. + * that is a very long delay, but if the clock does not become ready we are + * hosed anyway. + */ + +#define HSERDY_TIMEOUT (100 * CONFIG_BOARD_LOOPSPERMSEC) + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/* Include chip-specific clocking initialization logic */ + +#include "stm32l15xxx_rcc.c" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#if defined(CONFIG_STM32_STM32L15XX) +# define STM32_RCC_XXX STM32_RCC_CSR +# define RCC_XXX_YYYRST RCC_CSR_RTCRST +#else +# define STM32_RCC_XXX STM32_RCC_BDCR +# define RCC_XXX_YYYRST RCC_BDCR_BDRST +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: rcc_resetbkp + * + * Description: + * The RTC needs to reset the Backup Domain to change RTCSEL and resetting + * the Backup Domain renders to disabling the LSE as consequence. + * In order to avoid resetting the Backup Domain when we already + * configured LSE we will reset the Backup Domain early (here). + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +#if defined(CONFIG_STM32_RTC) && defined(CONFIG_STM32_PWR) && !defined(CONFIG_STM32_STM32F10XX) +static inline void rcc_resetbkp(void) +{ + uint32_t regval; + + /* Check if the RTC is already configured */ + + stm32_pwr_initbkp(false); + + regval = getreg32(RTC_MAGIC_REG); + if (regval != RTC_MAGIC && regval != RTC_MAGIC_TIME_SET) + { + stm32_pwr_enablebkp(true); + + /* We might be changing RTCSEL - to ensure such changes work, we must + * reset the backup domain (having backed up the RTC_MAGIC token) + */ + + modifyreg32(STM32_RCC_XXX, 0, RCC_XXX_YYYRST); + modifyreg32(STM32_RCC_XXX, RCC_XXX_YYYRST, 0); + + stm32_pwr_enablebkp(false); + } +} +#else +# define rcc_resetbkp() +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_clockconfig + * + * Description: + * Called to establish the clock settings based on the values in board.h. + * This function (by default) will reset most everything, enable the PLL, + * and enable peripheral clocking for all peripherals enabled in the NuttX + * configuration file. + * + * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then clocking + * will be enabled by an externally provided, board-specific function + * called stm32_board_clockconfig(). + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void stm32_clockconfig(void) +{ + /* Make sure that we are starting in the reset state */ + + rcc_reset(); + + /* Reset backup domain if appropriate */ + + rcc_resetbkp(); + +#if defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) + + /* Invoke Board Custom Clock Configuration */ + + stm32_board_clockconfig(); + +#else + + /* Invoke standard, fixed clock configuration based on definitions + * in board.h + */ + + stm32_stdclockconfig(); + +#endif + + /* Enable peripheral clocking */ + + rcc_enableperipherals(); + +#ifdef CONFIG_STM32_SYSCFG_IOCOMPENSATION + /* Enable I/O Compensation */ + + stm32_iocompensation(); +#endif +} + +/**************************************************************************** + * Name: stm32_clockenable + * + * Description: + * Re-enable the clock and restore the clock settings based on settings + * in board.h. This function is only available to support low-power + * modes of operation: When re-awakening from deep-sleep modes, it is + * necessary to re-enable/re-start the PLL + * + * This functional performs a subset of the operations performed by + * stm32_clockconfig(): It does not reset any devices, and it does not + * reset the currently enabled peripheral clocks. + * + * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then clocking + * will be enabled by an externally provided, board-specific function + * called stm32_board_clockconfig(). + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_PM +void stm32_clockenable(void) +{ +#if defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) + + /* Invoke Board Custom Clock Configuration */ + + stm32_board_clockconfig(); + +#else + + /* Invoke standard, fixed clock configuration based on definitions + * in board.h + */ + + stm32_stdclockconfig(); + +#endif +} +#endif diff --git a/arch/arm/src/stm32/stm32l15xxx_alarm.h b/arch/arm/src/stm32l1/stm32l15xxx_alarm.h similarity index 99% rename from arch/arm/src/stm32/stm32l15xxx_alarm.h rename to arch/arm/src/stm32l1/stm32l15xxx_alarm.h index 52267bf83c0b8..1d5e789cec91c 100644 --- a/arch/arm/src/stm32/stm32l15xxx_alarm.h +++ b/arch/arm/src/stm32l1/stm32l15xxx_alarm.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32l15xxx_alarm.h + * arch/arm/src/stm32l1/stm32l15xxx_alarm.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/stm32l15xxx_rcc.c b/arch/arm/src/stm32l1/stm32l15xxx_rcc.c similarity index 99% rename from arch/arm/src/stm32/stm32l15xxx_rcc.c rename to arch/arm/src/stm32l1/stm32l15xxx_rcc.c index 043e46beca372..f7f08c0f656ba 100644 --- a/arch/arm/src/stm32/stm32l15xxx_rcc.c +++ b/arch/arm/src/stm32l1/stm32l15xxx_rcc.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32l15xxx_rcc.c + * arch/arm/src/stm32l1/stm32l15xxx_rcc.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32l4/CMakeLists.txt b/arch/arm/src/stm32l4/CMakeLists.txt index 040c98142bcd8..9ea2ec8809a94 100644 --- a/arch/arm/src/stm32l4/CMakeLists.txt +++ b/arch/arm/src/stm32l4/CMakeLists.txt @@ -33,8 +33,6 @@ list( stm32l4_rcc.c stm32l4_serial.c stm32l4_start.c - stm32l4_waste.c - stm32l4_uid.c stm32l4_spi.c stm32l4_i2c.c stm32l4_lse.c @@ -58,11 +56,11 @@ else() list(APPEND SRCS stm32l4_tickless.c) endif() -if(CONFIG_STM32L4_ONESHOT) +if(CONFIG_STM32_ONESHOT) list(APPEND SRCS stm32l4_oneshot.c stm32l4_oneshot_lowerhalf.c) endif() -if(CONFIG_STM32L4_FREERUN) +if(CONFIG_STM32_FREERUN) list(APPEND SRCS stm32l4_freerun.c) endif() @@ -70,37 +68,37 @@ if(CONFIG_BUILD_PROTECTED) list(APPEND SRCS stm32l4_userspace.c stm32l4_mpuinit.c) endif() -if(CONFIG_STM32L4_HAVE_HSI48) +if(CONFIG_STM32_HAVE_HSI48) list(APPEND SRCS stm32l4_hsi48.c) endif() -if(CONFIG_STM32L4_ADC) +if(CONFIG_STM32_ADC) list(APPEND SRCS stm32l4_adc.c) endif() -if(CONFIG_STM32L4_DAC) +if(CONFIG_STM32_DAC) list(APPEND SRCS stm32l4_dac.c) endif() -if(CONFIG_STM32L4_DFSDM) +if(CONFIG_STM32_DFSDM) list(APPEND SRCS stm32l4_dfsdm.c) endif() -if(CONFIG_STM32L4_DMA) +if(CONFIG_STM32_DMA) list(APPEND SRCS stm32l4_dma.c) endif() if(CONFIG_USBDEV) - if(CONFIG_STM32L4_USBFS) + if(CONFIG_STM32_USBFS) list(APPEND SRCS stm32l4_usbdev.c) endif() - if(CONFIG_STM32L4_OTGFS) + if(CONFIG_STM32_OTGFS) list(APPEND SRCS stm32l4_otgfsdev.c) endif() endif() if(CONFIG_USBHOST) - if(CONFIG_STM32L4_OTGFS) + if(CONFIG_STM32_OTGFS) list(APPEND SRCS stm32l4_otgfshost.c) endif() endif() @@ -124,11 +122,11 @@ if(CONFIG_PM) endif() endif() -if(CONFIG_STM32L4_PWR) +if(CONFIG_STM32_PWR) list(APPEND SRCS stm32l4_exti_pwr.c) endif() -if(CONFIG_STM32L4_RTC) +if(CONFIG_STM32_RTC) if(CONFIG_RTC_ALARM) list(APPEND SRCS stm32l4_exti_alarm.c) endif() @@ -144,23 +142,23 @@ if(CONFIG_DEBUG_FEATURES) list(APPEND SRCS stm32l4_dumpgpio.c) endif() -if(CONFIG_STM32L4_COMP) +if(CONFIG_STM32_COMP) list(APPEND SRCS stm32l4_comp.c stm32l4_exti_comp.c) endif() -if(CONFIG_STM32L4_RNG) +if(CONFIG_STM32_RNG) list(APPEND SRCS stm32l4_rng.c) endif() -if(CONFIG_STM32L4_SAI) +if(CONFIG_STM32_SAI) list(APPEND SRCS stm32l4_sai.c) endif() -if(CONFIG_STM32L4_LPTIM) +if(CONFIG_STM32_LPTIM) list(APPEND SRCS stm32l4_lptim.c) endif() -if(CONFIG_STM32L4_PWM) +if(CONFIG_STM32_PWM) list(APPEND SRCS stm32l4_pwm.c) endif() @@ -172,28 +170,30 @@ if(CONFIG_SENSORS_QENCODER) list(APPEND SRCS stm32l4_qencoder.c) endif() -if(CONFIG_STM32L4_QSPI) +if(CONFIG_STM32_QSPI) list(APPEND SRCS stm32l4_qspi.c) endif() -if(CONFIG_STM32L4_CAN) +if(CONFIG_STM32_CAN) list(APPEND SRCS stm32l4_can.c) endif() -if(CONFIG_STM32L4_FIREWALL) +if(CONFIG_STM32_FIREWALL) list(APPEND SRCS stm32l4_firewall.c) endif() -if(CONFIG_STM32L4_IWDG) +if(CONFIG_STM32_IWDG) list(APPEND SRCS stm32l4_iwdg.c) endif() -if(CONFIG_STM32L4_SDMMC1) +if(CONFIG_STM32_SDMMC1) list(APPEND SRCS stm32l4_sdmmc.c) endif() -if(CONFIG_STM32L4_1WIREDRIVER) +if(CONFIG_STM32_1WIREDRIVER) list(APPEND SRCS stm32l4_1wire.c) endif() target_sources(arch PRIVATE ${SRCS}) + +add_subdirectory(${NUTTX_DIR}/arch/arm/src/common/stm32 stm32_common) diff --git a/arch/arm/src/stm32l4/Kconfig b/arch/arm/src/stm32l4/Kconfig index b6d2bb1fb804c..8c7e33356dac8 100644 --- a/arch/arm/src/stm32l4/Kconfig +++ b/arch/arm/src/stm32l4/Kconfig @@ -7,6 +7,31 @@ if ARCH_CHIP_STM32L4 comment "STM32L4 Configuration Options" +config STM32_L4_PERIPHERALS + bool + default ARCH_CHIP_STM32L4 + select STM32_HAVE_DAC1 + select STM32_HAVE_DMA1 + select STM32_HAVE_DMA2 + select STM32_HAVE_I2C1 + select STM32_HAVE_I2C2 if !(STM32_STM32L432XX || STM32_STM32L442XX) + select STM32_HAVE_I2C3 + select STM32_HAVE_LPTIM1 + select STM32_HAVE_RNG + select STM32_HAVE_RTC_SUBSECONDS + select STM32_HAVE_SPI1 + select STM32_HAVE_SPI2 if !(STM32_STM32L432XX || STM32_STM32L442XX) + select STM32_HAVE_SPI3 + select STM32_HAVE_SYSCFG + select STM32_HAVE_TSC + select STM32_HAVE_SWPMI + select STM32_HAVE_FIREWALL + select STM32_HAVE_LPTIM_CHANNEL + select STM32_HAVE_TIM_ADC_CHANNEL + select STM32_HAVE_ADC_L4 + select STM32_HAVE_DAC_LL_OPS + select STM32_HAVE_IP_WDG_M3M4_V1 + choice prompt "STM32 L4 Chip Selection" default ARCH_CHIP_STM32L476RG @@ -14,544 +39,544 @@ choice config ARCH_CHIP_STM32L412KB bool "STM32L412KB" - select STM32L4_STM32L412XX - select STM32L4_FLASH_CONFIG_B + select STM32_STM32L412XX + select STM32_FLASH_CONFIG_B select STM32L4_IO_CONFIG_K ---help--- STM32 L4 Cortex M4, 128 Kb FLASH, 40 Kb SRAM config ARCH_CHIP_STM32L432KB bool "STM32L432KB" - select STM32L4_STM32L432XX - select STM32L4_FLASH_CONFIG_B + select STM32_STM32L432XX + select STM32_FLASH_CONFIG_B select STM32L4_IO_CONFIG_K ---help--- STM32 L4 Cortex M4, 128 Kb FLASH, 64 Kb SRAM config ARCH_CHIP_STM32L432KC bool "STM32L432KC" - select STM32L4_STM32L432XX - select STM32L4_FLASH_CONFIG_C + select STM32_STM32L432XX + select STM32_FLASH_CONFIG_C select STM32L4_IO_CONFIG_K ---help--- STM32 L4 Cortex M4, 256 Kb FLASH, 64 Kb SRAM config ARCH_CHIP_STM32L433CB bool "STM32L433CB" - select STM32L4_STM32L433XX - select STM32L4_FLASH_CONFIG_B + select STM32_STM32L433XX + select STM32_FLASH_CONFIG_B select STM32L4_IO_CONFIG_C ---help--- STM32 L4 Cortex M4, 128 Kb FLASH, 64 Kb SRAM config ARCH_CHIP_STM32L433CC bool "STM32L433CC" - select STM32L4_STM32L433XX - select STM32L4_FLASH_CONFIG_C + select STM32_STM32L433XX + select STM32_FLASH_CONFIG_C select STM32L4_IO_CONFIG_C ---help--- STM32 L4 Cortex M4, 256 Kb FLASH, 64 Kb SRAM config ARCH_CHIP_STM32L433RB bool "STM32L433RB" - select STM32L4_STM32L433XX - select STM32L4_FLASH_CONFIG_B + select STM32_STM32L433XX + select STM32_FLASH_CONFIG_B select STM32L4_IO_CONFIG_R ---help--- STM32 L4 Cortex M4, 128 Kb FLASH, 64 Kb SRAM config ARCH_CHIP_STM32L433RC bool "STM32L433RC" - select STM32L4_STM32L433XX - select STM32L4_FLASH_CONFIG_C + select STM32_STM32L433XX + select STM32_FLASH_CONFIG_C select STM32L4_IO_CONFIG_R ---help--- STM32 L4 Cortex M4, 256 Kb FLASH, 64 Kb SRAM config ARCH_CHIP_STM32L433VC bool "STM32L433VC" - select STM32L4_STM32L433XX - select STM32L4_FLASH_CONFIG_C + select STM32_STM32L433XX + select STM32_FLASH_CONFIG_C select STM32L4_IO_CONFIG_V ---help--- STM32 L4 Cortex M4, 256 Kb FLASH, 64 Kb SRAM config ARCH_CHIP_STM32L442KC bool "STM32L442KC" - select STM32L4_STM32L442XX - select STM32L4_FLASH_CONFIG_C + select STM32_STM32L442XX + select STM32_FLASH_CONFIG_C select STM32L4_IO_CONFIG_K ---help--- STM32 L4 Cortex M4, AES, 256 Kb FLASH, 64 Kb SRAM config ARCH_CHIP_STM32L443CC bool "STM32L443CC" - select STM32L4_STM32L443XX - select STM32L4_FLASH_CONFIG_C + select STM32_STM32L443XX + select STM32_FLASH_CONFIG_C select STM32L4_IO_CONFIG_C ---help--- STM32 L4 Cortex M4, AES, 256 Kb FLASH, 64 Kb SRAM config ARCH_CHIP_STM32L443RC bool "STM32L443RC" - select STM32L4_STM32L443XX - select STM32L4_FLASH_CONFIG_C + select STM32_STM32L443XX + select STM32_FLASH_CONFIG_C select STM32L4_IO_CONFIG_R ---help--- STM32 L4 Cortex M4, AES, 256 Kb FLASH, 64 Kb SRAM config ARCH_CHIP_STM32L443VC bool "STM32L443VC" - select STM32L4_STM32L443XX - select STM32L4_FLASH_CONFIG_C + select STM32_STM32L443XX + select STM32_FLASH_CONFIG_C select STM32L4_IO_CONFIG_V ---help--- STM32 L4 Cortex M4, AES, 256 Kb FLASH, 64 Kb SRAM config ARCH_CHIP_STM32L451CC bool "STM32L451CC" - select STM32L4_STM32L451XX - select STM32L4_FLASH_CONFIG_C + select STM32_STM32L451XX + select STM32_FLASH_CONFIG_C select STM32L4_IO_CONFIG_C ---help--- STM32 L4 Cortex M4, 256 Kb FLASH, 128+32 Kb SRAM config ARCH_CHIP_STM32L451CE bool "STM32L451CE" - select STM32L4_STM32L451XX - select STM32L4_FLASH_CONFIG_E + select STM32_STM32L451XX + select STM32_FLASH_CONFIG_E select STM32L4_IO_CONFIG_C ---help--- STM32 L4 Cortex M4, 512 Kb FLASH, 128+32 Kb SRAM config ARCH_CHIP_STM32L451RC bool "STM32L451RC" - select STM32L4_STM32L451XX - select STM32L4_FLASH_CONFIG_C + select STM32_STM32L451XX + select STM32_FLASH_CONFIG_C select STM32L4_IO_CONFIG_R ---help--- STM32 L4 Cortex M4, 256 Kb FLASH, 128+32 Kb SRAM config ARCH_CHIP_STM32L451RE bool "STM32L451RE" - select STM32L4_STM32L451XX - select STM32L4_FLASH_CONFIG_E + select STM32_STM32L451XX + select STM32_FLASH_CONFIG_E select STM32L4_IO_CONFIG_R ---help--- STM32 L4 Cortex M4, 512 Kb FLASH, 128+32 Kb SRAM config ARCH_CHIP_STM32L451VC bool "STM32L451VC" - select STM32L4_STM32L451XX - select STM32L4_FLASH_CONFIG_C + select STM32_STM32L451XX + select STM32_FLASH_CONFIG_C select STM32L4_IO_CONFIG_V ---help--- STM32 L4 Cortex M4, 256 Kb FLASH, 128+32 Kb SRAM config ARCH_CHIP_STM32L451VE bool "STM32L451VE" - select STM32L4_STM32L451XX - select STM32L4_FLASH_CONFIG_E + select STM32_STM32L451XX + select STM32_FLASH_CONFIG_E select STM32L4_IO_CONFIG_V ---help--- STM32 L4 Cortex M4, 512 Kb FLASH, 128+32 Kb SRAM config ARCH_CHIP_STM32L452CC bool "STM32L452CC" - select STM32L4_STM32L452XX - select STM32L4_FLASH_CONFIG_C + select STM32_STM32L452XX + select STM32_FLASH_CONFIG_C select STM32L4_IO_CONFIG_C ---help--- STM32 L4 Cortex M4, 256 Kb FLASH, 128+32 Kb SRAM config ARCH_CHIP_STM32L452CE bool "STM32L452CE" - select STM32L4_STM32L452XX - select STM32L4_FLASH_CONFIG_E + select STM32_STM32L452XX + select STM32_FLASH_CONFIG_E select STM32L4_IO_CONFIG_C ---help--- STM32 L4 Cortex M4, 512 Kb FLASH, 128+32 Kb SRAM config ARCH_CHIP_STM32L452RC bool "STM32L452RC" - select STM32L4_STM32L452XX - select STM32L4_FLASH_CONFIG_C + select STM32_STM32L452XX + select STM32_FLASH_CONFIG_C select STM32L4_IO_CONFIG_R ---help--- STM32 L4 Cortex M4, 256 Kb FLASH, 128+32 Kb SRAM config ARCH_CHIP_STM32L452RE bool "STM32L452RE" - select STM32L4_STM32L452XX - select STM32L4_FLASH_CONFIG_E + select STM32_STM32L452XX + select STM32_FLASH_CONFIG_E select STM32L4_IO_CONFIG_R ---help--- STM32 L4 Cortex M4, 512 Kb FLASH, 128+32 Kb SRAM config ARCH_CHIP_STM32L452VC bool "STM32L452VC" - select STM32L4_STM32L452XX - select STM32L4_FLASH_CONFIG_C + select STM32_STM32L452XX + select STM32_FLASH_CONFIG_C select STM32L4_IO_CONFIG_V ---help--- STM32 L4 Cortex M4, 256 Kb FLASH, 128+32 Kb SRAM config ARCH_CHIP_STM32L452VE bool "STM32L452VE" - select STM32L4_STM32L452XX - select STM32L4_FLASH_CONFIG_E + select STM32_STM32L452XX + select STM32_FLASH_CONFIG_E select STM32L4_IO_CONFIG_V ---help--- STM32 L4 Cortex M4, 512 Kb FLASH, 128+32 Kb SRAM config ARCH_CHIP_STM32L462CE bool "STM32L462CE" - select STM32L4_STM32L462XX - select STM32L4_FLASH_CONFIG_E + select STM32_STM32L462XX + select STM32_FLASH_CONFIG_E select STM32L4_IO_CONFIG_C ---help--- STM32 L4 Cortex M4, USB FS, AES, 512 Kb FLASH, 128+32 Kb SRAM config ARCH_CHIP_STM32L462RE bool "STM32L462RE" - select STM32L4_STM32L462XX - select STM32L4_FLASH_CONFIG_E + select STM32_STM32L462XX + select STM32_FLASH_CONFIG_E select STM32L4_IO_CONFIG_R ---help--- STM32 L4 Cortex M4, USB FS, AES, 512 Kb FLASH, 128+32 Kb SRAM config ARCH_CHIP_STM32L462VE bool "STM32L462VE" - select STM32L4_STM32L462XX - select STM32L4_FLASH_CONFIG_E + select STM32_STM32L462XX + select STM32_FLASH_CONFIG_E select STM32L4_IO_CONFIG_V ---help--- STM32 L4 Cortex M4, USB FS, AES, 512 Kb FLASH, 128+32 Kb SRAM config ARCH_CHIP_STM32L475RG bool "STM32L475RG" - select STM32L4_STM32L475XX - select STM32L4_FLASH_CONFIG_G + select STM32_STM32L475XX + select STM32_FLASH_CONFIG_G select STM32L4_IO_CONFIG_R ---help--- STM32 L4 Cortex M4, 1024Kb FLASH, 96+32 Kb SRAM, LQFP100 config ARCH_CHIP_STM32L475RE bool "STM32L475RE" - select STM32L4_STM32L475XX - select STM32L4_FLASH_CONFIG_E + select STM32_STM32L475XX + select STM32_FLASH_CONFIG_E select STM32L4_IO_CONFIG_R ---help--- STM32 L4 Cortex M4, 512Kb FLASH, 96+32 Kb SRAM, LQFP100 config ARCH_CHIP_STM32L475RC bool "STM32L475RC" - select STM32L4_STM32L475XX - select STM32L4_FLASH_CONFIG_E + select STM32_STM32L475XX + select STM32_FLASH_CONFIG_E select STM32L4_IO_CONFIG_R ---help--- STM32 L4 Cortex M4, 256Kb FLASH, 96+32 Kb SRAM, LQFP100 config ARCH_CHIP_STM32L475VG bool "STM32L475VG" - select STM32L4_STM32L475XX - select STM32L4_FLASH_CONFIG_G + select STM32_STM32L475XX + select STM32_FLASH_CONFIG_G select STM32L4_IO_CONFIG_R ---help--- STM32 L4 Cortex M4, 1024Kb FLASH, 96+32 Kb SRAM, LQFP64 config ARCH_CHIP_STM32L475VE bool "STM32L475VE" - select STM32L4_STM32L475XX - select STM32L4_FLASH_CONFIG_E + select STM32_STM32L475XX + select STM32_FLASH_CONFIG_E select STM32L4_IO_CONFIG_R ---help--- STM32 L4 Cortex M4, 512Kb FLASH, 96+32 Kb SRAM, LQFP64 config ARCH_CHIP_STM32L475VC bool "STM32L475VC" - select STM32L4_STM32L475XX - select STM32L4_FLASH_CONFIG_E + select STM32_STM32L475XX + select STM32_FLASH_CONFIG_E select STM32L4_IO_CONFIG_R ---help--- STM32 L4 Cortex M4, 256Kb FLASH, 96+32 Kb SRAM, LQFP64 config ARCH_CHIP_STM32L476JG bool "STM32L476JG" - select STM32L4_STM32L476XX - select STM32L4_FLASH_CONFIG_G + select STM32_STM32L476XX + select STM32_FLASH_CONFIG_G select STM32L4_IO_CONFIG_J ---help--- STM32 L4 Cortex M4, 1024Kb FLASH, 96+32 Kb SRAM config ARCH_CHIP_STM32L476JE bool "STM32L476JE" - select STM32L4_STM32L476XX - select STM32L4_FLASH_CONFIG_E + select STM32_STM32L476XX + select STM32_FLASH_CONFIG_E select STM32L4_IO_CONFIG_J ---help--- STM32 L4 Cortex M4, 512Kb FLASH, 96+32 Kb SRAM config ARCH_CHIP_STM32L476RG bool "STM32L476RG" - select STM32L4_STM32L476XX - select STM32L4_FLASH_CONFIG_G + select STM32_STM32L476XX + select STM32_FLASH_CONFIG_G select STM32L4_IO_CONFIG_R ---help--- STM32 L4 Cortex M4, 1024Kb FLASH, 96+32 Kb SRAM config ARCH_CHIP_STM32L476RE bool "STM32L476RE" - select STM32L4_STM32L476XX - select STM32L4_FLASH_CONFIG_E + select STM32_STM32L476XX + select STM32_FLASH_CONFIG_E select STM32L4_IO_CONFIG_R ---help--- STM32 L4 Cortex M4, 512Kb FLASH, 96+32 Kb SRAM config ARCH_CHIP_STM32L486RG bool "STM32L486RG" - select STM32L4_STM32L486XX - select STM32L4_FLASH_CONFIG_G + select STM32_STM32L486XX + select STM32_FLASH_CONFIG_G select STM32L4_IO_CONFIG_R ---help--- STM32 L4 Cortex M4, AES, 1024Kb FLASH, 96+32 Kb SRAM config ARCH_CHIP_STM32L486JG bool "STM32L486JG" - select STM32L4_STM32L486XX - select STM32L4_FLASH_CONFIG_G + select STM32_STM32L486XX + select STM32_FLASH_CONFIG_G select STM32L4_IO_CONFIG_J ---help--- STM32 L4 Cortex M4, AES, 1024Kb FLASH, 96+32 Kb SRAM config ARCH_CHIP_STM32L486VG bool "STM32L486VG" - select STM32L4_STM32L486XX - select STM32L4_FLASH_CONFIG_G + select STM32_STM32L486XX + select STM32_FLASH_CONFIG_G select STM32L4_IO_CONFIG_V ---help--- STM32 L4 Cortex M4, AES, 1024Kb FLASH, 96+32 Kb SRAM config ARCH_CHIP_STM32L486QG bool "STM32L486QG" - select STM32L4_STM32L486XX - select STM32L4_FLASH_CONFIG_G + select STM32_STM32L486XX + select STM32_FLASH_CONFIG_G select STM32L4_IO_CONFIG_Q ---help--- STM32 L4 Cortex M4, AES, 1024Kb FLASH, 96+32 Kb SRAM config ARCH_CHIP_STM32L486ZG bool "STM32L486ZG" - select STM32L4_STM32L486XX - select STM32L4_FLASH_CONFIG_G + select STM32_STM32L486XX + select STM32_FLASH_CONFIG_G select STM32L4_IO_CONFIG_Z ---help--- STM32 L4 Cortex M4, AES, 1024Kb FLASH, 96+32 Kb SRAM config ARCH_CHIP_STM32L496RE bool "STM32L496RE" - select STM32L4_STM32L496XX - select STM32L4_FLASH_CONFIG_E + select STM32_STM32L496XX + select STM32_FLASH_CONFIG_E select STM32L4_IO_CONFIG_R ---help--- STM32 L4 Cortex M4, 512Kb FLASH, 320 Kb SRAM config ARCH_CHIP_STM32L496RG bool "STM32L496RG" - select STM32L4_STM32L496XX - select STM32L4_FLASH_CONFIG_G + select STM32_STM32L496XX + select STM32_FLASH_CONFIG_G select STM32L4_IO_CONFIG_R ---help--- STM32 L4 Cortex M4, 1024Kb FLASH, 320 Kb SRAM config ARCH_CHIP_STM32L496VE bool "STM32L496VE" - select STM32L4_STM32L496XX - select STM32L4_FLASH_CONFIG_E + select STM32_STM32L496XX + select STM32_FLASH_CONFIG_E select STM32L4_IO_CONFIG_V ---help--- STM32 L4 Cortex M4, 512Kb FLASH, 320 Kb SRAM config ARCH_CHIP_STM32L496VG bool "STM32L496VG" - select STM32L4_STM32L496XX - select STM32L4_FLASH_CONFIG_G + select STM32_STM32L496XX + select STM32_FLASH_CONFIG_G select STM32L4_IO_CONFIG_V ---help--- STM32 L4 Cortex M4, 1024Kb FLASH, 320 Kb SRAM config ARCH_CHIP_STM32L496ZE bool "STM32L496ZE" - select STM32L4_STM32L496XX - select STM32L4_FLASH_CONFIG_E + select STM32_STM32L496XX + select STM32_FLASH_CONFIG_E select STM32L4_IO_CONFIG_Z ---help--- STM32 L4 Cortex M4, 512Kb FLASH, 320 Kb SRAM config ARCH_CHIP_STM32L496ZG bool "STM32L496ZG" - select STM32L4_STM32L496XX - select STM32L4_FLASH_CONFIG_G + select STM32_STM32L496XX + select STM32_FLASH_CONFIG_G select STM32L4_IO_CONFIG_Z ---help--- STM32 L4 Cortex M4, 1024Kb FLASH, 320 Kb SRAM config ARCH_CHIP_STM32L496AG bool "STM32L496AG" - select STM32L4_STM32L496XX - select STM32L4_FLASH_CONFIG_G + select STM32_STM32L496XX + select STM32_FLASH_CONFIG_G select STM32L4_IO_CONFIG_A ---help--- STM32 L4 Cortex M4, 1024Kb FLASH, 320 Kb SRAM config ARCH_CHIP_STM32L4A6RG bool "STM32L4A6RG" - select STM32L4_STM32L4A6XX - select STM32L4_FLASH_CONFIG_G + select STM32_STM32L4A6XX + select STM32_FLASH_CONFIG_G select STM32L4_IO_CONFIG_R ---help--- STM32 L4 Cortex M4, AES, HASH, 1024Kb FLASH, 320 Kb SRAM config ARCH_CHIP_STM32L4A6VG bool "STM32L4A6VG" - select STM32L4_STM32L4A6XX - select STM32L4_FLASH_CONFIG_G + select STM32_STM32L4A6XX + select STM32_FLASH_CONFIG_G select STM32L4_IO_CONFIG_V ---help--- STM32 L4 Cortex M4, AES, HASH, 1024Kb FLASH, 320 Kb SRAM config ARCH_CHIP_STM32L4A6QG bool "STM32L4A6QG" - select STM32L4_STM32L4A6XX - select STM32L4_FLASH_CONFIG_G + select STM32_STM32L4A6XX + select STM32_FLASH_CONFIG_G select STM32L4_IO_CONFIG_Q ---help--- STM32 L4 Cortex M4, AES, HASH, 1024Kb FLASH, 320 Kb SRAM config ARCH_CHIP_STM32L4A6ZG bool "STM32L4A6ZG" - select STM32L4_STM32L4A6XX - select STM32L4_FLASH_CONFIG_G + select STM32_STM32L4A6XX + select STM32_FLASH_CONFIG_G select STM32L4_IO_CONFIG_Z ---help--- STM32 L4 Cortex M4, AES, HASH, 1024Kb FLASH, 320 Kb SRAM config ARCH_CHIP_STM32L4A6AG bool "STM32L4A6AG" - select STM32L4_STM32L4A6XX - select STM32L4_FLASH_CONFIG_G + select STM32_STM32L4A6XX + select STM32_FLASH_CONFIG_G select STM32L4_IO_CONFIG_A ---help--- STM32 L4 Cortex M4, AES, HASH, 1024Kb FLASH, 320 Kb SRAM config ARCH_CHIP_STM32L4R5VG bool "STM32L4R5VG" - select STM32L4_STM32L4R5XX - select STM32L4_FLASH_CONFIG_G + select STM32_STM32L4R5XX + select STM32_FLASH_CONFIG_G select STM32L4_IO_CONFIG_V ---help--- STM32 L4+ Cortex M4, 1024Kb FLASH, 640 Kb SRAM config ARCH_CHIP_STM32L4R5QG bool "STM32L4R5QG" - select STM32L4_STM32L4R5XX - select STM32L4_FLASH_CONFIG_G + select STM32_STM32L4R5XX + select STM32_FLASH_CONFIG_G select STM32L4_IO_CONFIG_Q ---help--- STM32 L4+ Cortex M4, 1024Kb FLASH, 640 Kb SRAM config ARCH_CHIP_STM32L4R5ZG bool "STM32L4R5ZG" - select STM32L4_STM32L4R5XX - select STM32L4_FLASH_CONFIG_G + select STM32_STM32L4R5XX + select STM32_FLASH_CONFIG_G select STM32L4_IO_CONFIG_Z ---help--- STM32 L4+ Cortex M4, 1024Kb FLASH, 640 Kb SRAM config ARCH_CHIP_STM32L4R5AG bool "STM32L4R5AG" - select STM32L4_STM32L4R5XX - select STM32L4_FLASH_CONFIG_G + select STM32_STM32L4R5XX + select STM32_FLASH_CONFIG_G select STM32L4_IO_CONFIG_A ---help--- STM32 L4+ Cortex M4, 1024Kb FLASH, 640 Kb SRAM config ARCH_CHIP_STM32L4R5VI bool "STM32L4R5VI" - select STM32L4_STM32L4R5XX - select STM32L4_FLASH_CONFIG_I + select STM32_STM32L4R5XX + select STM32_FLASH_CONFIG_I select STM32L4_IO_CONFIG_V ---help--- STM32 L4+ Cortex M4, 2048Kb FLASH, 640 Kb SRAM config ARCH_CHIP_STM32L4R5QI bool "STM32L4R5QI" - select STM32L4_STM32L4R5XX - select STM32L4_FLASH_CONFIG_I + select STM32_STM32L4R5XX + select STM32_FLASH_CONFIG_I select STM32L4_IO_CONFIG_Q ---help--- STM32 L4+ Cortex M4, 2048Kb FLASH, 640 Kb SRAM config ARCH_CHIP_STM32L4R5ZI bool "STM32L4R5ZI" - select STM32L4_STM32L4R5XX - select STM32L4_FLASH_CONFIG_I + select STM32_STM32L4R5XX + select STM32_FLASH_CONFIG_I select STM32L4_IO_CONFIG_Z ---help--- STM32 L4+ Cortex M4, 2048Kb FLASH, 640 Kb SRAM config ARCH_CHIP_STM32L4R5AI bool "STM32L4R5AI" - select STM32L4_STM32L4R5XX - select STM32L4_FLASH_CONFIG_I + select STM32_STM32L4R5XX + select STM32_FLASH_CONFIG_I select STM32L4_IO_CONFIG_A ---help--- STM32 L4+ Cortex M4, 2048Kb FLASH, 640 Kb SRAM config ARCH_CHIP_STM32L4R9VG bool "STM32L4R9VG" - select STM32L4_STM32L4R9XX - select STM32L4_FLASH_CONFIG_G + select STM32_STM32L4R9XX + select STM32_FLASH_CONFIG_G select STM32L4_IO_CONFIG_V ---help--- STM32 L4+ Cortex M4, 1024Kb FLASH, 640 Kb SRAM config ARCH_CHIP_STM32L4R9ZG bool "STM32L4R9ZG" - select STM32L4_STM32L4R9XX - select STM32L4_FLASH_CONFIG_G + select STM32_STM32L4R9XX + select STM32_FLASH_CONFIG_G select STM32L4_IO_CONFIG_Z ---help--- STM32 L4+ Cortex M4, 1024Kb FLASH, 640 Kb SRAM config ARCH_CHIP_STM32L4R9AG bool "STM32L4R9AG" - select STM32L4_STM32L4R9XX - select STM32L4_FLASH_CONFIG_G + select STM32_STM32L4R9XX + select STM32_FLASH_CONFIG_G select STM32L4_IO_CONFIG_A ---help--- STM32 L4+ Cortex M4, 1024Kb FLASH, 640 Kb SRAM config ARCH_CHIP_STM32L4R9VI bool "STM32L4R9VI" - select STM32L4_STM32L4R9XX - select STM32L4_FLASH_CONFIG_I + select STM32_STM32L4R9XX + select STM32_FLASH_CONFIG_I select STM32L4_IO_CONFIG_V ---help--- STM32 L4+ Cortex M4, 2048Kb FLASH, 640 Kb SRAM config ARCH_CHIP_STM32L4R9ZI bool "STM32L4R9ZI" - select STM32L4_STM32L4R9XX - select STM32L4_FLASH_CONFIG_I + select STM32_STM32L4R9XX + select STM32_FLASH_CONFIG_I select STM32L4_IO_CONFIG_Z ---help--- STM32 L4+ Cortex M4, 2048Kb FLASH, 640 Kb SRAM config ARCH_CHIP_STM32L4R9AI bool "STM32L4R9AI" - select STM32L4_STM32L4R9XX - select STM32L4_FLASH_CONFIG_I + select STM32_STM32L4R9XX + select STM32_FLASH_CONFIG_I select STM32L4_IO_CONFIG_A ---help--- STM32 L4+ Cortex M4, 2048Kb FLASH, 640 Kb SRAM @@ -560,5924 +585,401 @@ endchoice # STM32 L4 Chip Selection # Chip product lines -config STM32L4_STM32L4X1 +config STM32_STM32L4X1 # STM32L4x1 Access Lines # # Avoid using this config as it is basically same subfamily - # as STM32L4_STM32L4X3 (documented in RM0394). + # as STM32_STM32L4X3 (documented in RM0394). # # Note: This is _not_ for STM32L471xx (documented in RM0392). bool default n - select STM32L4_STM32L4X3 + select STM32_STM32L4X3 -config STM32L4_STM32L4X2 +config STM32_STM32L4X2 # STM32L4x2 USB Device Lines # # Avoid using this config as it is basically same subfamily - # as STM32L4_STM32L4X3 (documented in RM0394). + # as STM32_STM32L4X3 (documented in RM0394). bool default n - select STM32L4_STM32L4X3 - select STM32L4_HAVE_USBFS + select STM32_STM32L4X3 + select STM32_HAVE_USBFS -config STM32L4_STM32L4X3 +config STM32_STM32L4X3 # STM32L4 devices documented in RM0394, regardless of what ST's # marketing calls them. bool default n select ARCH_HAVE_FPU - select STM32L4_HAVE_LPUART1 - select STM32L4_HAVE_USART1 - select STM32L4_HAVE_USART2 - select STM32L4_HAVE_USART3 if !(STM32L4_STM32L432XX || STM32L4_STM32L442XX) - select STM32L4_HAVE_LPTIM1 - select STM32L4_HAVE_LPTIM2 - select STM32L4_HAVE_COMP - select STM32L4_HAVE_SAI1 - select STM32L4_HAVE_LCD if !(STM32L4_STM32L4X1 || STM32L4_STM32L4X2) - select STM32L4_HAVE_HSI48 - -config STM32L4_STM32L4X5 + select STM32_HAVE_CAN1 + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM6 + select STM32_HAVE_TIM15 + select STM32_HAVE_TIM16 + select STM32_HAVE_LPUART1 + select STM32_HAVE_USART1 + select STM32_HAVE_USART2 + select STM32_HAVE_USART3 if !(STM32_STM32L432XX || STM32_STM32L442XX) + select STM32_HAVE_LPTIM1 + select STM32_HAVE_LPTIM2 + select STM32_HAVE_COMP + select STM32_HAVE_SAI1 + select STM32_HAVE_LCD if !(STM32_STM32L4X1 || STM32_STM32L4X2) + select STM32_HAVE_HSI48 + +config STM32_STM32L4X5 # STM32L4 USB OTG Lines (documented in RM0351) bool default n select ARCH_HAVE_FPU - select STM32L4_HAVE_LPUART1 - select STM32L4_HAVE_USART1 - select STM32L4_HAVE_USART2 - select STM32L4_HAVE_USART3 - select STM32L4_HAVE_UART4 - select STM32L4_HAVE_UART5 - select STM32L4_HAVE_ADC2 - select STM32L4_HAVE_ADC3 - select STM32L4_HAVE_DAC2 - select STM32L4_HAVE_FSMC - select STM32L4_HAVE_TIM3 - select STM32L4_HAVE_TIM4 - select STM32L4_HAVE_TIM5 - select STM32L4_HAVE_TIM7 - select STM32L4_HAVE_TIM8 - select STM32L4_HAVE_TIM17 - select STM32L4_HAVE_LPTIM1 - select STM32L4_HAVE_LPTIM2 - select STM32L4_HAVE_COMP - select STM32L4_HAVE_SAI1 - select STM32L4_HAVE_SAI2 - select STM32L4_HAVE_SDMMC1 - select STM32L4_HAVE_OTGFS - select STM32L4_HAVE_DFSDM1 - select STM32L4_HAVE_QSPI - -config STM32L4_STM32L4X6 + select STM32_HAVE_CAN1 + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM6 + select STM32_HAVE_TIM15 + select STM32_HAVE_TIM16 + select STM32_HAVE_LPUART1 + select STM32_HAVE_USART1 + select STM32_HAVE_USART2 + select STM32_HAVE_USART3 + select STM32_HAVE_UART4 + select STM32_HAVE_UART5 + select STM32_HAVE_ADC2 + select STM32_HAVE_ADC3 + select STM32_HAVE_DAC2 + select STM32_HAVE_FSMC + select STM32_HAVE_TIM3 + select STM32_HAVE_TIM4 + select STM32_HAVE_TIM5 + select STM32_HAVE_TIM7 + select STM32_HAVE_TIM8 + select STM32_HAVE_TIM17 + select STM32_HAVE_LPTIM1 + select STM32_HAVE_LPTIM2 + select STM32_HAVE_COMP + select STM32_HAVE_SAI1 + select STM32_HAVE_SAI2 + select STM32_HAVE_SDMMC1 + select STM32_HAVE_OTGFS + select STM32_HAVE_DFSDM1 + select STM32_HAVE_QSPI + +config STM32_STM32L4X6 # STM32L4x6 (documented in RM0351) bool default n select ARCH_HAVE_FPU - select STM32L4_HAVE_LPUART1 - select STM32L4_HAVE_USART1 - select STM32L4_HAVE_USART2 - select STM32L4_HAVE_USART3 - select STM32L4_HAVE_UART4 - select STM32L4_HAVE_UART5 - select STM32L4_HAVE_ADC2 - select STM32L4_HAVE_ADC3 - select STM32L4_HAVE_DAC2 - select STM32L4_HAVE_FSMC - select STM32L4_HAVE_TIM3 - select STM32L4_HAVE_TIM4 - select STM32L4_HAVE_TIM5 - select STM32L4_HAVE_TIM7 - select STM32L4_HAVE_TIM8 - select STM32L4_HAVE_TIM17 - select STM32L4_HAVE_LPTIM1 - select STM32L4_HAVE_LPTIM2 - select STM32L4_HAVE_COMP - select STM32L4_HAVE_SAI1 - select STM32L4_HAVE_SAI2 - select STM32L4_HAVE_SDMMC1 - select STM32L4_HAVE_OTGFS - select STM32L4_HAVE_LCD - select STM32L4_HAVE_QSPI - -config STM32L4_STM32L4XR + select STM32_HAVE_CAN1 + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM6 + select STM32_HAVE_TIM15 + select STM32_HAVE_TIM16 + select STM32_HAVE_LPUART1 + select STM32_HAVE_USART1 + select STM32_HAVE_USART2 + select STM32_HAVE_USART3 + select STM32_HAVE_UART4 + select STM32_HAVE_UART5 + select STM32_HAVE_ADC2 + select STM32_HAVE_ADC3 + select STM32_HAVE_DAC2 + select STM32_HAVE_FSMC + select STM32_HAVE_TIM3 + select STM32_HAVE_TIM4 + select STM32_HAVE_TIM5 + select STM32_HAVE_TIM7 + select STM32_HAVE_TIM8 + select STM32_HAVE_TIM17 + select STM32_HAVE_LPTIM1 + select STM32_HAVE_LPTIM2 + select STM32_HAVE_COMP + select STM32_HAVE_SAI1 + select STM32_HAVE_SAI2 + select STM32_HAVE_SDMMC1 + select STM32_HAVE_OTGFS + select STM32_HAVE_LCD + select STM32_HAVE_QSPI + +config STM32_STM32L4XR # STM32L4+ (documented in RM0432) bool default n select ARCH_HAVE_FPU - select STM32L4_HAVE_LPUART1 - select STM32L4_HAVE_USART1 - select STM32L4_HAVE_USART2 - select STM32L4_HAVE_USART3 - select STM32L4_HAVE_UART4 - select STM32L4_HAVE_UART5 - select STM32L4_HAVE_DAC2 - select STM32L4_HAVE_FSMC - select STM32L4_HAVE_TIM3 - select STM32L4_HAVE_TIM4 - select STM32L4_HAVE_TIM5 - select STM32L4_HAVE_TIM7 - select STM32L4_HAVE_TIM8 - select STM32L4_HAVE_TIM17 - select STM32L4_HAVE_LPTIM1 - select STM32L4_HAVE_LPTIM2 - select STM32L4_HAVE_COMP - select STM32L4_HAVE_SAI1 - select STM32L4_HAVE_SAI2 - select STM32L4_HAVE_SDMMC1 - select STM32L4_HAVE_OTGFS - select STM32L4_HAVE_I2C4 - select STM32L4_HAVE_DCMI - select STM32L4_HAVE_DFSDM1 - select STM32L4_HAVE_HSI48 - select STM32L4_HAVE_DMAMUX + select STM32_HAVE_CAN1 + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM6 + select STM32_HAVE_TIM15 + select STM32_HAVE_TIM16 + select STM32_HAVE_LPUART1 + select STM32_HAVE_USART1 + select STM32_HAVE_USART2 + select STM32_HAVE_USART3 + select STM32_HAVE_UART4 + select STM32_HAVE_UART5 + select STM32_HAVE_DAC2 + select STM32_HAVE_FSMC + select STM32_HAVE_TIM3 + select STM32_HAVE_TIM4 + select STM32_HAVE_TIM5 + select STM32_HAVE_TIM7 + select STM32_HAVE_TIM8 + select STM32_HAVE_TIM17 + select STM32_HAVE_LPTIM1 + select STM32_HAVE_LPTIM2 + select STM32_HAVE_COMP + select STM32_HAVE_SAI1 + select STM32_HAVE_SAI2 + select STM32_HAVE_SDMMC1 + select STM32_HAVE_OTGFS + select STM32_HAVE_I2C4 + select STM32_HAVE_DCMI + select STM32_HAVE_DFSDM1 + select STM32_HAVE_HSI48 + select STM32_HAVE_DMAMUX # Chip subfamilies: -config STM32L4_STM32L412XX +config STM32_STM32L412XX bool default n - select STM32L4_STM32L4X2 - select STM32L4_HAVE_ADC2 + select STM32_STM32L4X2 + select STM32_HAVE_ADC2 -config STM32L4_STM32L422XX +config STM32_STM32L422XX bool default n - select STM32L4_STM32L4X2 - select STM32L4_HAVE_ADC2 - select STM32L4_HAVE_AES + select STM32_STM32L4X2 + select STM32_HAVE_ADC2 + select STM32_HAVE_AES + select STM32_HAVE_IP_AES_M3M4_V1 -config STM32L4_STM32L431XX +config STM32_STM32L431XX bool default n - select STM32L4_STM32L4X1 - select STM32L4_HAVE_DAC2 - select STM32L4_HAVE_TIM7 - select STM32L4_HAVE_SDMMC1 if (STM32L4_IO_CONFIG_V || STM32L4_IO_CONFIG_R) + select STM32_STM32L4X1 + select STM32_HAVE_DAC2 + select STM32_HAVE_TIM7 + select STM32_HAVE_SDMMC1 if (STM32L4_IO_CONFIG_V || STM32L4_IO_CONFIG_R) -config STM32L4_STM32L432XX +config STM32_STM32L432XX bool default n - select STM32L4_STM32L4X2 - select STM32L4_HAVE_DAC2 - select STM32L4_HAVE_TIM7 + select STM32_STM32L4X2 + select STM32_HAVE_DAC2 + select STM32_HAVE_TIM7 -config STM32L4_STM32L433XX +config STM32_STM32L433XX bool default n - select STM32L4_STM32L4X3 - select STM32L4_HAVE_DAC2 - select STM32L4_HAVE_TIM7 + select STM32_STM32L4X3 + select STM32_HAVE_DAC2 + select STM32_HAVE_TIM7 -config STM32L4_STM32L442XX +config STM32_STM32L442XX bool default n - select STM32L4_STM32L4X2 - select STM32L4_HAVE_DAC2 - select STM32L4_HAVE_TIM7 - select STM32L4_HAVE_AES + select STM32_STM32L4X2 + select STM32_HAVE_DAC2 + select STM32_HAVE_TIM7 + select STM32_HAVE_AES + select STM32_HAVE_IP_AES_M3M4_V1 -config STM32L4_STM32L443XX +config STM32_STM32L443XX bool default n - select STM32L4_STM32L4X3 - select STM32L4_HAVE_DAC2 - select STM32L4_HAVE_TIM7 - select STM32L4_HAVE_SDMMC1 - select STM32L4_HAVE_AES + select STM32_STM32L4X3 + select STM32_HAVE_DAC2 + select STM32_HAVE_TIM7 + select STM32_HAVE_SDMMC1 + select STM32_HAVE_AES + select STM32_HAVE_IP_AES_M3M4_V1 -config STM32L4_STM32L451XX +config STM32_STM32L451XX bool default n - select STM32L4_STM32L4X1 - select STM32L4_HAVE_UART4 - select STM32L4_HAVE_TIM3 - select STM32L4_HAVE_I2C4 - select STM32L4_HAVE_SDMMC1 if !STM32L4_IO_CONFIG_C - select STM32L4_HAVE_DFSDM1 + select STM32_STM32L4X1 + select STM32_HAVE_UART4 + select STM32_HAVE_TIM3 + select STM32_HAVE_I2C4 + select STM32_HAVE_SDMMC1 if !STM32L4_IO_CONFIG_C + select STM32_HAVE_DFSDM1 -config STM32L4_STM32L452XX +config STM32_STM32L452XX bool default n - select STM32L4_STM32L4X2 - select STM32L4_HAVE_UART4 - select STM32L4_HAVE_TIM3 - select STM32L4_HAVE_I2C4 - select STM32L4_HAVE_SDMMC1 - select STM32L4_HAVE_DFSDM1 + select STM32_STM32L4X2 + select STM32_HAVE_UART4 + select STM32_HAVE_TIM3 + select STM32_HAVE_I2C4 + select STM32_HAVE_SDMMC1 + select STM32_HAVE_DFSDM1 -config STM32L4_STM32L462XX +config STM32_STM32L462XX bool default n - select STM32L4_STM32L4X2 - select STM32L4_HAVE_UART4 - select STM32L4_HAVE_TIM3 - select STM32L4_HAVE_I2C4 - select STM32L4_HAVE_SDMMC1 - select STM32L4_HAVE_DFSDM1 - select STM32L4_HAVE_AES + select STM32_STM32L4X2 + select STM32_HAVE_UART4 + select STM32_HAVE_TIM3 + select STM32_HAVE_I2C4 + select STM32_HAVE_SDMMC1 + select STM32_HAVE_DFSDM1 + select STM32_HAVE_AES + select STM32_HAVE_IP_AES_M3M4_V1 -config STM32L4_STM32L471XX +config STM32_STM32L471XX bool default n + select STM32_HAVE_CAN1 + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM6 + select STM32_HAVE_TIM15 + select STM32_HAVE_TIM16 # TODO -config STM32L4_STM32L475XX - bool - default n - select STM32L4_STM32L4X5 - -config STM32L4_STM32L476XX - bool - default n - select STM32L4_STM32L4X6 - -config STM32L4_STM32L486XX - bool - default n - select STM32L4_STM32L4X6 - select STM32L4_HAVE_AES - -config STM32L4_STM32L496XX - bool - default n - select STM32L4_STM32L4X6 - select STM32L4_HAVE_I2C4 - select STM32L4_HAVE_CAN2 - select STM32L4_HAVE_DCMI - select STM32L4_HAVE_DMA2D - select STM32L4_HAVE_DFSDM1 - select STM32L4_HAVE_HSI48 - -config STM32L4_STM32L4A6XX +config STM32_STM32L475XX bool default n - select STM32L4_STM32L496XX - select STM32L4_HAVE_AES - select STM32L4_HAVE_HASH + select STM32_STM32L4X5 -config STM32L4_STM32L4R5XX +config STM32_STM32L476XX bool default n - select STM32L4_STM32L4XR + select STM32_STM32L4X6 -config STM32L4_STM32L4S5XX +config STM32_STM32L486XX bool default n - select STM32L4_STM32L4XR - select STM32L4_HAVE_AES - select STM32L4_HAVE_HASH + select STM32_STM32L4X6 + select STM32_HAVE_AES + select STM32_HAVE_IP_AES_M3M4_V1 -config STM32L4_STM32L4R7XX +config STM32_STM32L496XX bool default n - select STM32L4_STM32L4XR - select STM32L4_HAVE_DMA2D + select STM32_STM32L4X6 + select STM32_HAVE_I2C4 + select STM32_HAVE_CAN2 + select STM32_HAVE_DCMI + select STM32_HAVE_DMA2D + select STM32_HAVE_IP_DMA2D_M3M4_V1 + select STM32_HAVE_DFSDM1 + select STM32_HAVE_HSI48 -config STM32L4_STM32L4S7XX +config STM32_STM32L4A6XX bool default n - select STM32L4_STM32L4XR - select STM32L4_HAVE_DMA2D - select STM32L4_HAVE_AES - select STM32L4_HAVE_HASH + select STM32_STM32L496XX + select STM32_HAVE_AES + select STM32_HAVE_HASH + select STM32_HAVE_IP_AES_M3M4_V1 -config STM32L4_STM32L4R9XX +config STM32_STM32L4R5XX bool default n - select STM32L4_STM32L4XR - select STM32L4_HAVE_DMA2D - select STM32L4_HAVE_LTDC - -config STM32L4_STM32L4S9XX - bool - default n - select STM32L4_STM32L4XR - select STM32L4_HAVE_DMA2D - select STM32L4_HAVE_LTDC - select STM32L4_HAVE_AES - select STM32L4_HAVE_HASH - -choice - prompt "Override Flash Size Designator" - depends on ARCH_CHIP_STM32L4 - default STM32L4_FLASH_OVERRIDE_DEFAULT - ---help--- - STM32L4 series parts numbering (sans the package type) ends with a letter - that designates the FLASH size. - - Designator Size in KiB - 8 64 - B 128 - C 256 - E 512 - G 1024 - I 2048 - - This configuration option defaults to using the configuration based on that designator - or the default smaller size if there is no last character designator is present in the - STM32 Chip Selection. - - Examples: - If the STM32L476VE is chosen, the Flash configuration would be 'E', if a variant of - the part with a 1024 KiB Flash is released in the future one could simply select - the 'G' designator here. - - If an STM32L4xxx Series parts is chosen the default Flash configuration will be set - herein and can be changed. - -config STM32L4_FLASH_OVERRIDE_DEFAULT - bool "Default" - -config STM32L4_FLASH_OVERRIDE_8 - bool "8 64 KB" - -config STM32L4_FLASH_OVERRIDE_B - bool "B 128 KB" - -config STM32L4_FLASH_OVERRIDE_C - bool "C 256 KB" - -config STM32L4_FLASH_OVERRIDE_E - bool "E 512 KB" + select STM32_STM32L4XR -config STM32L4_FLASH_OVERRIDE_G - bool "G 1024 KB" - -config STM32L4_FLASH_OVERRIDE_I - bool "I 2048 KB" - -endchoice # "Override Flash Size Designator" - -# Flash configurations - -config STM32L4_FLASH_CONFIG_8 +config STM32_STM32L4S5XX bool default n - depends on STM32L4_STM32L412XX + select STM32_STM32L4XR + select STM32_HAVE_AES + select STM32_HAVE_HASH + select STM32_HAVE_IP_AES_M3M4_V1 -config STM32L4_FLASH_CONFIG_B +config STM32_STM32L4R7XX bool default n - depends on STM32L4_STM32L4X1 || STM32L4_STM32L4X3 + select STM32_STM32L4XR + select STM32_HAVE_DMA2D + select STM32_HAVE_IP_DMA2D_M3M4_V1 -config STM32L4_FLASH_CONFIG_C +config STM32_STM32L4S7XX bool default n - depends on !STM32L4_STM32L496XX + select STM32_STM32L4XR + select STM32_HAVE_DMA2D + select STM32_HAVE_IP_DMA2D_M3M4_V1 + select STM32_HAVE_AES + select STM32_HAVE_HASH + select STM32_HAVE_IP_AES_M3M4_V1 -config STM32L4_FLASH_CONFIG_E +config STM32_STM32L4R9XX bool default n + select STM32_STM32L4XR + select STM32_HAVE_DMA2D + select STM32_HAVE_IP_DMA2D_M3M4_V1 + select STM32_HAVE_LTDC -config STM32L4_FLASH_CONFIG_G +config STM32_STM32L4S9XX bool default n - depends on STM32L4_STM32L4X5 || STM32L4_STM32L4X6 + select STM32_STM32L4XR + select STM32_HAVE_DMA2D + select STM32_HAVE_IP_DMA2D_M3M4_V1 + select STM32_HAVE_LTDC + select STM32_HAVE_AES + select STM32_HAVE_HASH + select STM32_HAVE_IP_AES_M3M4_V1 -config STM32L4_FLASH_CONFIG_I - bool - default n - depends on STM32L4_STM32L4XR # Pin/package configurations config STM32L4_IO_CONFIG_K + # Package designator K bool default n config STM32L4_IO_CONFIG_T + # Package designator T bool default n config STM32L4_IO_CONFIG_C + # Package designator C bool default n config STM32L4_IO_CONFIG_R + # Package designator R bool default n config STM32L4_IO_CONFIG_J + # Package designator J bool default n config STM32L4_IO_CONFIG_M + # Package designator M bool default n config STM32L4_IO_CONFIG_V + # Package designator V bool default n config STM32L4_IO_CONFIG_Q + # Package designator Q bool default n config STM32L4_IO_CONFIG_Z + # Package designator Z bool default n config STM32L4_IO_CONFIG_A + # Package designator A bool default n comment "STM32L4 SRAM2 and SRAM3 Options" -config STM32L4_SRAM2_HEAP - bool "SRAM2 is used for heap" - default n - select STM32L4_SRAM2_INIT - ---help--- - The STM32L4 SRAM2 region has special properties (power, protection, parity) - which may be used by the application for special purposes. But if these - special properties are not needed, it may be instead added to the heap for - use by malloc(). - NOTE: you must also select an appropriate number of memory regions in the - 'Memory Management' section. - -config STM32L4_SRAM2_INIT - bool "SRAM2 is initialized to zero" - default n - ---help--- - The STM32L4 SRAM2 region has parity checking. However, when the system - powers on, the memory is in an unknown state, and reads from uninitialized - memory can trigger parity faults from the random data. This can be - avoided by first writing to all locations to force the parity into a valid - state. - However, if the SRAM2 is being used for it's battery-backed capability, - this may be undesirable (because it will destroy the contents). In that - case, the board should handle the initialization itself at the appropriate - time. - -config STM32L4_SRAM3_HEAP - bool "SRAM3 is used for heap" - depends on STM32L4_STM32L4XR - default y - ---help--- - Add the STM32L4 SRAM3 to the heap for use by malloc(). - NOTE: you must also select an appropriate number of memory regions in the - 'Memory Management' section. - -comment "STM32L4 Peripherals" - -menu "STM32L4 Peripheral Support" - -# These "hidden" settings determine whether a peripheral option is available -# for the selected MCU - -config STM32L4_HAVE_ADC2 - bool - default n - -config STM32L4_HAVE_ADC3 - bool - default n - -config STM32L4_HAVE_AES - bool - default n - -config STM32L4_HAVE_CAN2 - bool - default n - -config STM32L4_HAVE_COMP - bool - default n - -config STM32L4_HAVE_DAC2 - bool - default n - -config STM32L4_HAVE_DCMI - bool - default n - -config STM32L4_HAVE_DFSDM1 - bool - default n - -config STM32L4_HAVE_DMA2D - bool - default n - -config STM32L4_HAVE_DMAMUX - bool - default n - -config STM32L4_HAVE_FSMC - bool - default n - -config STM32L4_HAVE_HASH - bool - default n - -config STM32L4_HAVE_HSI48 - bool - default n - -config STM32L4_HAVE_I2C4 - bool - default n - -config STM32L4_HAVE_LCD - bool - default n - -config STM32L4_HAVE_LTDC - bool - default n - -config STM32L4_HAVE_LPTIM1 - bool - default n - -config STM32L4_HAVE_LPTIM2 - bool - default n - -config STM32L4_HAVE_OTGFS - bool - default n - -config STM32L4_HAVE_USBFS - bool - default n - -config STM32L4_HAVE_SAI1 - bool - default n - -config STM32L4_HAVE_SAI2 - bool - default n - -config STM32L4_RTC - bool "RTC" - default n - select RTC - -config STM32L4_HAVE_SDMMC1 - bool - default n - -config STM32L4_HAVE_TIM3 - bool - default n - -config STM32L4_HAVE_TIM4 - bool - default n - -config STM32L4_HAVE_TIM5 - bool - default n - -config STM32L4_HAVE_TIM7 - bool - default n - -config STM32L4_HAVE_TIM8 - bool - default n - -config STM32L4_HAVE_TIM17 - bool - default n - -config STM32L4_HAVE_LPUART1 - bool - default n - -config STM32L4_HAVE_USART1 - bool - default n - -config STM32L4_HAVE_USART2 - bool - default n - -config STM32L4_HAVE_USART3 - bool - default n - -config STM32L4_HAVE_UART4 - bool - default n - -config STM32L4_HAVE_UART5 - bool - default n - -config STM32L4_HAVE_QSPI - bool - default n - -# These "hidden" settings are the OR of individual peripheral selections -# indicating that the general capability is required. - -config STM32L4_ADC - bool - default n - -config STM32L4_CAN - bool - default n - -config STM32L4_DAC - bool - default n - -config STM32L4_DFSDM - bool - default n - -config STM32L4_DMAMUX - bool - default n - depends on STM32L4_HAVE_DMAMUX - -config STM32L4_DMA - bool - default n - select STM32L4_DMAMUX if STM32L4_HAVE_DMAMUX - -config STM32L4_I2C - bool - default n - -config STM32L4_SAI - bool - default n - -config STM32L4_SPI - bool - default n - -config STM32L4_PWM - bool - default n - -config STM32L4_USART - bool - default n - -config STM32L4_LPTIM - bool - default n - -config STM32L4_SDMMC - bool - default n - -# These are the peripheral selections proper - -comment "AHB1 Peripherals" - -config STM32L4_DMAMUX1 - bool "DMAMUX1" - default n - depends on STM32L4_HAVE_DMAMUX - select STM32L4_DMAMUX - -config STM32L4_DMA1 - bool "DMA1" - default n - select STM32L4_DMA - select ARCH_DMA - select STM32L4_DMAMUX1 if STM32L4_HAVE_DMAMUX - -config STM32L4_DMA2 - bool "DMA2" - default n - select STM32L4_DMA - select ARCH_DMA - select STM32L4_DMAMUX1 if STM32L4_HAVE_DMAMUX - -config STM32L4_CRC - bool "CRC" - default n - -config STM32L4_TSC - bool "TSC" - default n - -comment "AHB2 Peripherals" - -config STM32L4_OTGFS - bool "OTG FS" - default n - select USBHOST_HAVE_ASYNCH if USBHOST - depends on STM32L4_HAVE_OTGFS - -config STM32L4_ADC1 - bool "ADC1" - default n - select STM32L4_ADC - -config STM32L4_ADC2 - bool "ADC2" - default n - select STM32L4_ADC - depends on STM32L4_HAVE_ADC2 - -config STM32L4_ADC3 - bool "ADC3" - default n - select STM32L4_ADC - depends on STM32L4_HAVE_ADC3 - -config STM32L4_AES - bool "AES" - default n - depends on STM32L4_HAVE_AES - -config STM32L4_DCMI - bool "DCMI" - default n - depends on STM32L4_HAVE_DCMI - -config STM32L4_DMA2D - bool "DMA2D" - default n - depends on STM32L4_HAVE_DMA2D - -config STM32L4_HASH - bool "HASH" - default n - depends on STM32L4_HAVE_HASH - -config STM32L4_RNG - bool "RNG" - default n - select ARCH_HAVE_RNG - -comment "AHB3 Peripherals" - -config STM32L4_FSMC - bool "FSMC" - default n - depends on STM32L4_HAVE_FSMC - -config STM32L4_QSPI - bool "QuadSPI" - default n - depends on STM32L4_HAVE_QSPI - ---help--- - The STM32L4 QSPI block is intended to support one serial NOR flash device - -if STM32L4_QSPI - -config STM32L4_QSPI_FLASH_SIZE - int "Size of attached serial flash, bytes" - default 16777216 - range 1 2147483647 - ---help--- - The STM32L4 QSPI peripheral requires the size of the Flash be specified - -config STM32L4_QSPI_FIFO_THESHOLD - int "Number of bytes before asserting FIFO threshold flag" - default 4 - range 1 16 - ---help--- - The STM32L4 QSPI peripheral requires that the FIFO threshold be specified - I would leave it at the default value of 4 unless you know what you are doing. - -config STM32L4_QSPI_CSHT - int "Number of cycles Chip Select must be inactive between transactions" - default 1 - range 1 8 - ---help--- - The STM32L4 QSPI peripheral requires that it be specified the minimum number - of AHB cycles that Chip Select be held inactive between transactions. - -choice - prompt "Transfer technique" - default STM32L4_QSPI_DMA - ---help--- - You can choose between using polling, interrupts, or DMA to transfer data - over the QSPI interface. - -config STM32L4_QSPI_POLLING - bool "Polling" - ---help--- - Use conventional register I/O with status polling to transfer data. - -config STM32L4_QSPI_INTERRUPTS - bool "Interrupts" - ---help--- - User interrupt driven I/O transfers. - -config STM32L4_QSPI_DMA - bool "DMA" - depends on STM32L4_DMA - ---help--- - Use DMA to improve QSPI transfer performance. - -endchoice - -choice - prompt "DMA Channel" - default STM32L4_QSPI_DMA_CHAN_1_5 - depends on STM32L4_DMA - ---help--- - You can choose between two DMA channels for use with QSPI: - either DMA1 channel 5, or DMA2 channel 7. - If you only see one choice here, it is probably because - you have not also enabled the associated DMA controller. - -config STM32L4_QSPI_DMA_CHAN_1_5 - bool "DMA1 Channel 5" - depends on STM32L4_DMA1 && !STM32L4_DMAMUX - ---help--- - Use DMA1 channel 5 for QSPI. - -config STM32L4_QSPI_DMA_CHAN_2_7 - bool "DMA2 Channel 7" - depends on STM32L4_DMA2 && !STM32L4_DMAMUX - ---help--- - Use DMA2 channel 7 for QSPI. - -endchoice - -choice - prompt "DMA Priority" - default STM32L4_QSPI_DMAPRIORITY_MEDIUM - depends on STM32L4_DMA - ---help--- - The DMA controller supports priority levels. You are probably fine - with the default of 'medium' except for special cases. In the event - of contention between to channels at the same priority, the lower - numbered channel has hardware priority over the higher numbered one. - -config STM32L4_QSPI_DMAPRIORITY_VERYHIGH - bool "Very High priority" - depends on STM32L4_DMA - ---help--- - 'Highest' priority. - -config STM32L4_QSPI_DMAPRIORITY_HIGH - bool "High priority" - depends on STM32L4_DMA - ---help--- - 'High' priority. - -config STM32L4_QSPI_DMAPRIORITY_MEDIUM - bool "Medium priority" - depends on STM32L4_DMA - ---help--- - 'Medium' priority. - -config STM32L4_QSPI_DMAPRIORITY_LOW - bool "Low priority" - depends on STM32L4_DMA - ---help--- - 'Low' priority. - -endchoice - -config STM32L4_QSPI_DMATHRESHOLD - int "QSPI DMA threshold" - default 4 - depends on STM32L4_QSPI_DMA - ---help--- - When QSPI DMA is enabled, small DMA transfers will still be performed - by polling logic. This value is the threshold below which transfers - will still be performed by conventional register status polling. - -config STM32L4_QSPI_DMADEBUG - bool "QSPI DMA transfer debug" - depends on STM32L4_QSPI_DMA && DEBUG_SPI && DEBUG_DMA - default n - ---help--- - Enable special debug instrumentation to analyze QSPI DMA data transfers. - This logic is as non-invasive as possible: It samples DMA - registers at key points in the data transfer and then dumps all of - the registers at the end of the transfer. - -config STM32L4_QSPI_REGDEBUG - bool "QSPI Register level debug" - depends on DEBUG_SPI_INFO - default n - ---help--- - Output detailed register-level QSPI device debug information. - Requires also CONFIG_DEBUG_SPI_INFO. - -endif - -comment "APB1 Peripherals" - -config STM32L4_PWR - bool "PWR" - default n - -config STM32L4_TIM2 - bool "TIM2" - default n - -config STM32L4_TIM3 - bool "TIM3" - default n - depends on STM32L4_HAVE_TIM3 - -config STM32L4_TIM4 - bool "TIM4" - default n - depends on STM32L4_HAVE_TIM4 - -config STM32L4_TIM5 - bool "TIM5" - default n - depends on STM32L4_HAVE_TIM5 - -config STM32L4_TIM6 - bool "TIM6" - default n - -config STM32L4_TIM7 - bool "TIM7" - default n - depends on STM32L4_HAVE_TIM7 - -config STM32L4_LCD - bool "LCD" - default n - depends on STM32L4_HAVE_LCD - -config STM32L4_SPI2 - bool "SPI2" - default n - depends on !(STM32L4_STM32L432XX || STM32L4_STM32L442XX) - select SPI - select STM32L4_SPI - -config STM32L4_SPI3 - bool "SPI3" - default n - select SPI - select STM32L4_SPI - -config STM32L4_LPUART1 - bool "LPUART1" - default n - depends on STM32L4_HAVE_LPUART1 - select ARCH_HAVE_SERIAL_TERMIOS - select STM32L4_USART - -config STM32L4_USART2 - bool "USART2" - default n - depends on STM32L4_HAVE_USART2 - select ARCH_HAVE_SERIAL_TERMIOS - select STM32L4_USART - -config STM32L4_USART3 - bool "USART3" - default n - depends on STM32L4_HAVE_USART3 - select ARCH_HAVE_SERIAL_TERMIOS - select STM32L4_USART - -config STM32L4_UART4 - bool "UART4" - default n - depends on STM32L4_HAVE_UART4 - select ARCH_HAVE_SERIAL_TERMIOS - select STM32L4_USART - -config STM32L4_UART5 - bool "UART5" - default n - depends on STM32L4_HAVE_UART5 - select ARCH_HAVE_SERIAL_TERMIOS - select STM32L4_USART - -config STM32L4_I2C1 - bool "I2C1" - default n - select STM32L4_I2C - -config STM32L4_I2C2 - bool "I2C2" - default n - depends on !(STM32L4_STM32L432XX || STM32L4_STM32L442XX) - select STM32L4_I2C - -config STM32L4_I2C3 - bool "I2C3" - default n - select STM32L4_I2C - -config STM32L4_I2C4 - bool "I2C4" - default n - select STM32L4_I2C - depends on STM32L4_HAVE_I2C4 - -config STM32L4_CAN1 - bool "CAN1" - default n - select CAN - select STM32L4_CAN - -config STM32L4_CAN2 - bool "CAN2" - default n - select CAN - select STM32L4_CAN - depends on STM32L4_HAVE_CAN2 - -config STM32L4_DAC1 - bool "DAC1" - default n - select STM32L4_DAC - -config STM32L4_DAC2 - bool "DAC2" - default n - select STM32L4_DAC - depends on STM32L4_HAVE_DAC2 - -config STM32L4_OPAMP - bool "OPAMP" - default n - -config STM32L4_LPTIM1 - bool "LPTIM1" - default n - select STM32L4_LPTIM - depends on STM32L4_HAVE_LPTIM1 - -config STM32L4_LPUART1 - bool "LPUART1" - default n - select LPUART1_SERIALDRIVER - select ARCH_HAVE_SERIAL_TERMIOS - select ARCH_HAVE_LPUART1 - -config STM32L4_SWPMI - bool "SWPMI" - default n - -config STM32L4_LPTIM2 - bool "LPTIM2" - default n - select STM32L4_LPTIM - depends on STM32L4_HAVE_LPTIM2 - -config STM32L4_USBFS - bool "USB FS" - default n - depends on STM32L4_HAVE_USBFS - select USBDEV - -comment "APB2 Peripherals" - -config STM32L4_SYSCFG - bool "SYSCFG" - default y - -config STM32L4_FIREWALL - bool "FIREWALL" - default y - depends on STM32L4_SYSCFG - -config STM32L4_SDMMC1 - bool "SDMMC1" - default n - select ARCH_HAVE_SDIO - select SCHED_HPWORK - select STM32L4_SAI1PLL - select STM32L4_SDMMC - select ARCH_HAVE_SDIOWAIT_WRCOMPLETE - select ARCH_HAVE_SDIO_PREFLIGHT - depends on STM32L4_HAVE_SDMMC1 - -config STM32L4_TIM1 - bool "TIM1" - default n - -config STM32L4_SPI1 - bool "SPI1" - default n - select SPI - select STM32L4_SPI - -config STM32L4_TIM8 - bool "TIM8" - default n - depends on STM32L4_HAVE_TIM8 - -config STM32L4_USART1 - bool "USART1" - default n - depends on STM32L4_HAVE_USART1 - select ARCH_HAVE_SERIAL_TERMIOS - select STM32L4_USART - -config STM32L4_TIM15 - bool "TIM15" - default n - -config STM32L4_TIM16 - bool "TIM16" - default n - -config STM32L4_TIM17 - bool "TIM17" - default n - depends on STM32L4_HAVE_TIM17 - -config STM32L4_COMP - bool "COMP" - default n - select COMP - depends on STM32L4_HAVE_COMP - -config STM32L4_SAI1 - bool "SAI1" - default n - depends on STM32L4_HAVE_SAI1 - -config STM32L4_SAI1_A - bool "SAI1 Block A" - default n - select AUDIO - select I2S - select SCHED_HPWORK - select STM32L4_SAI - depends on STM32L4_SAI1 - -config STM32L4_SAI1_B - bool "SAI1 Block B" - default n - select AUDIO - select I2S - select SCHED_HPWORK - select STM32L4_SAI - depends on STM32L4_SAI1 - -config STM32L4_SAI2 - bool "SAI2" - default n - depends on STM32L4_HAVE_SAI2 - -config STM32L4_SAI2_A - bool "SAI2 Block A" - default n - select AUDIO - select I2S - select SCHED_HPWORK - select STM32L4_SAI - depends on STM32L4_SAI2 - -config STM32L4_SAI2_B - bool "SAI2 Block B" - default n - select AUDIO - select I2S - select SCHED_HPWORK - select STM32L4_SAI - depends on STM32L4_SAI2 - -config STM32L4_DFSDM1 - bool "DFSDM1" - default n - depends on STM32L4_HAVE_DFSDM1 - -comment "Other Peripherals" - -config STM32L4_BKPSRAM - bool "Enable BKP RAM Domain" - default n - -config STM32L4_IWDG - bool "IWDG" - default n - select WATCHDOG - -config STM32L4_WWDG - bool "WWDG" - default n - select WATCHDOG - -endmenu - -config STM32L4_SAI1PLL - bool "SAI1PLL" - default n - ---help--- - The STM32L4 has a separate PLL for the SAI1 block. - Set this true and provide configuration parameters in - board.h to use this PLL. - -config STM32L4_SAI2PLL - bool "SAI2PLL" - default n - depends on STM32L4_HAVE_SAI2 - ---help--- - The STM32L4 has a separate PLL for the SAI2 block. - Set this true and provide configuration parameters in - board.h to use this PLL. - -config STM32L4_FLASH_PREFETCH - bool "Enable FLASH Pre-fetch" - default y - ---help--- - Enable FLASH prefetch - -config STM32L4_FLASH_WORKAROUND_DATA_CACHE_CORRUPTION_ON_RWW - bool "Workaround for FLASH data cache corruption" - default n - depends on STM32L4_STM32L4X5 || STM32L4_STM32L4X6 || STM32L4_STM32L4XR - ---help--- - Enable the workaround to fix flash data cache corruption when reading - from one flash bank while writing on other flash bank. See your STM32 - errata to check if your STM32 is affected by this problem. - -choice - prompt "JTAG Configuration" - default STM32L4_JTAG_DISABLE - ---help--- - JTAG Enable settings (by default JTAG-DP and SW-DP are disabled) - -config STM32L4_JTAG_DISABLE - bool "Disable all JTAG clocking" - -config STM32L4_JTAG_FULL_ENABLE - bool "Enable full SWJ (JTAG-DP + SW-DP)" - -config STM32L4_JTAG_NOJNTRST_ENABLE - bool "Enable full SWJ (JTAG-DP + SW-DP) but without JNTRST" - -config STM32L4_JTAG_SW_ENABLE - bool "Set JTAG-DP disabled and SW-DP enabled" - -endchoice - -config STM32L4_DISABLE_IDLE_SLEEP_DURING_DEBUG - bool "Disable IDLE Sleep (WFI) in debug mode" - default n - ---help--- - In debug configuration, disables the WFI instruction in the IDLE loop - to prevent the JTAG from disconnecting. With some JTAG debuggers, such - as the ST-LINK2 with OpenOCD, if the ARM is put to sleep via the WFI - instruction, the debugger will disconnect, terminating the debug session. - -config ARCH_BOARD_STM32L4_CUSTOM_CLOCKCONFIG - bool "Custom clock configuration" - default n - ---help--- - Enables special, board-specific STM32 clock configuration. - -config STM32L4_HAVE_RTC_SUBSECONDS - bool - select ARCH_HAVE_RTC_SUBSECONDS - default y - -menu "RTC Configuration" - depends on STM32L4_RTC - -config STM32L4_RTC_MAGIC_REG - int "BKP register" - default 0 - range 0 31 - ---help--- - The BKP register used to store/check the Magic value to determine if - RTC is already setup - -config STM32L4_RTC_MAGIC - hex "RTC Magic 1" - default 0xfacefeed - ---help--- - Value used as Magic to determine if the RTC is already setup - -config STM32L4_RTC_MAGIC_TIME_SET - hex "RTC Magic 2" - default 0xf00dface - ---help--- - Value used as Magic to determine if the RTC has been setup and has - time set - -choice - prompt "RTC clock source" - default STM32L4_RTC_LSECLOCK - depends on STM32L4_RTC - -config STM32L4_RTC_LSECLOCK - bool "LSE clock" - ---help--- - Drive the RTC with the LSE clock - -config STM32L4_RTC_LSICLOCK - bool "LSI clock" - ---help--- - Drive the RTC with the LSI clock - -config STM32L4_RTC_HSECLOCK - bool "HSE clock" - ---help--- - Drive the RTC with the HSE clock, divided down to 1MHz. - -endchoice - -if STM32L4_RTC_LSECLOCK - -config STM32L4_RTC_LSECLOCK_START_DRV_CAPABILITY - int "LSE oscillator drive capability level at LSE start-up" - default 0 - range 0 3 - ---help--- - 0 = Low drive capability (default) - 1 = Medium low drive capability - 2 = Medium high drive capability - 3 = High drive capability - -config STM32L4_RTC_LSECLOCK_RUN_DRV_CAPABILITY - int "LSE oscillator drive capability level after LSE start-up" - default 0 - range 0 3 - ---help--- - 0 = Low drive capability (default) - 1 = Medium low drive capability - 2 = Medium high drive capability - 3 = High drive capability - -endif # STM32L4_RTC_LSECLOCK - -endmenu # RTC Configuration - -menu "Timer Configuration" - -if SCHED_TICKLESS - -config STM32L4_ONESHOT - bool - default y - -config STM32L4_FREERUN - bool - default y - -config STM32L4_TICKLESS_ONESHOT - int "Tickless one-shot timer channel" - default 2 - range 1 8 - depends on STM32L4_ONESHOT - ---help--- - If the Tickless OS feature is enabled, then one clock must be - assigned to provide the one-shot timer needed by the OS. - -config STM32L4_TICKLESS_FREERUN - int "Tickless free-running timer channel" - default 5 - range 1 8 - depends on STM32L4_FREERUN - ---help--- - If the Tickless OS feature is enabled, then one clock must be - assigned to provide the free-running timer needed by the OS. - -endif # SCHED_TICKLESS - -if !SCHED_TICKLESS - -config STM32L4_ONESHOT - bool "TIM one-shot wrapper" - default n - ---help--- - Enable a wrapper around the low level timer/counter functions to - support one-shot timer. - -config STM32L4_FREERUN - bool "TIM free-running wrapper" - default n - ---help--- - Enable a wrapper around the low level timer/counter functions to - support a free-running timer. - -endif # !SCHED_TICKLESS - -config STM32L4_ONESHOT_MAXTIMERS - int "Maximum number of oneshot timers" - default 1 - range 1 8 - depends on STM32L4_ONESHOT - ---help--- - Determines the maximum number of oneshot timers that can be - supported. This setting pre-allocates some minimal support for each - of the timers and places an upper limit on the number of oneshot - timers that you can use. - -config STM32L4_LPTIM1_PWM - bool "LPTIM1 PWM" - default n - depends on STM32L4_LPTIM1 - select PWM - ---help--- - Reserve low-power timer 1 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32L4_LPTIM1 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32L4_LPTIM1_PWM - -choice - prompt "LPTIM1 clock source" - default STM32L4_LPTIM1_CLK_APB1 - -config STM32L4_LPTIM1_CLK_APB1 - bool "Clock LPTIM1 from APB1" - -config STM32L4_LPTIM1_CLK_LSE - bool "Clock LPTIM1 from LSE" - -config STM32L4_LPTIM1_CLK_LSI - bool "Clock LPTIM1 from LSI" - -config STM32L4_LPTIM1_CLK_HSI - bool "Clock LPTIM1 from HSI" -endchoice - -endif # STM32L4_LPTIM1_PWM - -config STM32L4_LPTIM2_PWM - bool "LPTIM2 PWM" - default n - depends on STM32L4_LPTIM2 - select PWM - ---help--- - Reserve low-power timer 2 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32L4_LPTIM2 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32L4_LPTIM2_PWM - -choice - prompt "LPTIM2 clock source" - default STM32L4_LPTIM2_CLK_APB1 - -config STM32L4_LPTIM2_CLK_APB1 - bool "Clock LPTIM2 from APB1" - -config STM32L4_LPTIM2_CLK_LSE - bool "Clock LPTIM2 from LSE" - -config STM32L4_LPTIM2_CLK_LSI - bool "Clock LPTIM2 from LSI" - -config STM32L4_LPTIM2_CLK_HSI - bool "Clock LPTIM2 from HSI" -endchoice - -endif # STM32L4_LPTIM2_PWM - -config STM32L4_PWM_LL_OPS - bool "PWM low-level operations" - default n - ---help--- - Enable low-level PWM ops. - -config STM32L4_TIM1_PWM - bool "TIM1 PWM" - default n - depends on STM32L4_TIM1 - select STM32L4_PWM - ---help--- - Reserve timer 1 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32L4_TIM1 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32L4_TIM1_PWM - -config STM32L4_TIM1_MODE - int "TIM1 Mode" - default 0 - range 0 4 - ---help--- - Specifies the timer mode. - -config STM32L4_TIM1_LOCK - int "TIM1 Lock Level Configuration" - default 0 - range 0 3 - ---help--- - Timer 1 lock level configuration - -config STM32L4_TIM1_TDTS - int "TIM1 t_DTS Division" - default 0 - range 0 2 - ---help--- - Timer 1 dead-time and sampling clock (t_DTS) division - -config STM32L4_TIM1_DEADTIME - int "TIM1 Initial Dead-time" - default 0 - range 0 255 - ---help--- - Timer 1 initial dead-time - -if STM32L4_PWM_MULTICHAN - -config STM32L4_TIM1_CHANNEL1 - bool "TIM1 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32L4_TIM1_CHANNEL1 - -config STM32L4_TIM1_CH1MODE - int "TIM1 Channel 1 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32l4_pwm_chanmode_e in stm32l4_pwm.h. - -config STM32L4_TIM1_CH1OUT - bool "TIM1 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -config STM32L4_TIM1_CH1NOUT - bool "TIM1 Channel 1 Complementary Output" - default n - depends on STM32L4_TIM1_CH1OUT - ---help--- - Enables channel 1 complementary output. - -endif # STM32L4_TIM1_CHANNEL1 - -config STM32L4_TIM1_CHANNEL2 - bool "TIM1 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32L4_TIM1_CHANNEL2 - -config STM32L4_TIM1_CH2MODE - int "TIM1 Channel 2 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32l4_pwm_chanmode_e in stm32l4_pwm.h. - -config STM32L4_TIM1_CH2OUT - bool "TIM1 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -config STM32L4_TIM1_CH2NOUT - bool "TIM1 Channel 2 Complemenrary Output" - default n - depends on STM32L4_TIM1_CH2OUT - ---help--- - Enables channel 2 complementary output. - -endif # STM32L4_TIM1_CHANNEL2 - -config STM32L4_TIM1_CHANNEL3 - bool "TIM1 Channel 3" - default n - ---help--- - Enables channel 3. - -if STM32L4_TIM1_CHANNEL3 - -config STM32L4_TIM1_CH3MODE - int "TIM1 Channel 3 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32l4_pwm_chanmode_e in stm32l4_pwm.h. - -config STM32L4_TIM1_CH3OUT - bool "TIM1 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -config STM32L4_TIM1_CH3NOUT - bool "TIM1 Channel 3 Complementary Output" - default n - depends on STM32L4_TIM1_CH3OUT - ---help--- - Enables channel 3 complementary output. - -endif # STM32L4_TIM1_CHANNEL3 - -config STM32L4_TIM1_CHANNEL4 - bool "TIM1 Channel 4" - default n - ---help--- - Enables channel 4. - -if STM32L4_TIM1_CHANNEL4 - -config STM32L4_TIM1_CH4MODE - int "TIM1 Channel 4 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32l4_pwm_chanmode_e in stm32l4_pwm.h. - -config STM32L4_TIM1_CH4OUT - bool "TIM1 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32L4_TIM1_CHANNEL4 - -endif # STM32L4_PWM_MULTICHAN - -if !STM32L4_PWM_MULTICHAN - -config STM32L4_TIM1_CHANNEL - int "TIM1 PWM Output Channel" - default 1 - range 1 4 - ---help--- - If TIM1 is enabled for PWM usage, you also need specifies the timer output - channel {1,..,4} - -if STM32L4_TIM1_CHANNEL = 1 - -config STM32L4_TIM1_CH1OUT - bool "TIM1 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -config STM32L4_TIM1_CH1NOUT - bool "TIM1 Channel 1 Complementary Output" - default n - ---help--- - Enables channel 1 Complementary Output. - -endif # STM32L4_TIM1_CHANNEL = 1 - -if STM32L4_TIM1_CHANNEL = 2 - -config STM32L4_TIM1_CH2OUT - bool "TIM1 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -config STM32L4_TIM1_CH2NOUT - bool "TIM1 Channel 2 Complementary Output" - default n - ---help--- - Enables channel 2 Complementary Output. - -endif # STM32L4_TIM1_CHANNEL = 2 - -if STM32L4_TIM1_CHANNEL = 3 - -config STM32L4_TIM1_CH3OUT - bool "TIM1 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -config STM32L4_TIM1_CH3NOUT - bool "TIM1 Channel 3 Complementary Output" - default n - ---help--- - Enables channel 3 Complementary Output. - -endif # STM32L4_TIM1_CHANNEL = 3 - -if STM32L4_TIM1_CHANNEL = 4 - -config STM32L4_TIM1_CH4OUT - bool "TIM1 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32L4_TIM1_CHANNEL = 4 - -config STM32L4_TIM1_CHMODE - int "TIM1 Channel Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32l4_pwm_chanmode_e in stm32l4_pwm.h. - -endif # !STM32L4_PWM_MULTICHAN - -endif # STM32L4_TIM1_PWM - -config STM32L4_TIM2_PWM - bool "TIM2 PWM" - default n - depends on STM32L4_TIM2 - select STM32L4_PWM - ---help--- - Reserve timer 2 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32L4_TIM2 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32L4_TIM2_PWM - -config STM32L4_TIM2_MODE - int "TIM2 Mode" - default 0 - range 0 4 - ---help--- - Specifies the timer mode. - -if STM32L4_PWM_MULTICHAN - -config STM32L4_TIM2_CHANNEL1 - bool "TIM2 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32L4_TIM2_CHANNEL1 - -config STM32L4_TIM2_CH1MODE - int "TIM2 Channel 1 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32l4_pwm_chanmode_e in stm32l4_pwm.h. - -config STM32L4_TIM2_CH1OUT - bool "TIM2 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32L4_TIM2_CHANNEL1 - -config STM32L4_TIM2_CHANNEL2 - bool "TIM2 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32L4_TIM2_CHANNEL2 - -config STM32L4_TIM2_CH2MODE - int "TIM2 Channel 2 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32l4_pwm_chanmode_e in stm32l4_pwm.h. - -config STM32L4_TIM2_CH2OUT - bool "TIM2 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32L4_TIM2_CHANNEL2 - -config STM32L4_TIM2_CHANNEL3 - bool "TIM2 Channel 3" - default n - ---help--- - Enables channel 3. - -if STM32L4_TIM2_CHANNEL3 - -config STM32L4_TIM2_CH3MODE - int "TIM2 Channel 3 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32l4_pwm_chanmode_e in stm32l4_pwm.h. - -config STM32L4_TIM2_CH3OUT - bool "TIM2 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -endif # STM32L4_TIM2_CHANNEL3 - -config STM32L4_TIM2_CHANNEL4 - bool "TIM2 Channel 4" - default n - ---help--- - Enables channel 4. - -if STM32L4_TIM2_CHANNEL4 - -config STM32L4_TIM2_CH4MODE - int "TIM2 Channel 4 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32l4_pwm_chanmode_e in stm32l4_pwm.h. - -config STM32L4_TIM2_CH4OUT - bool "TIM2 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32L4_TIM2_CHANNEL4 - -endif # STM32L4_PWM_MULTICHAN - -if !STM32L4_PWM_MULTICHAN - -config STM32L4_TIM2_CHANNEL - int "TIM2 PWM Output Channel" - default 1 - range 1 4 - ---help--- - If TIM2 is enabled for PWM usage, you also need specifies the timer output - channel {1,..,4} - -if STM32L4_TIM2_CHANNEL = 1 - -config STM32L4_TIM2_CH1OUT - bool "TIM2 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32L4_TIM2_CHANNEL = 1 - -if STM32L4_TIM2_CHANNEL = 2 - -config STM32L4_TIM2_CH2OUT - bool "TIM2 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32L4_TIM2_CHANNEL = 2 - -if STM32L4_TIM2_CHANNEL = 3 - -config STM32L4_TIM2_CH3OUT - bool "TIM2 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -endif # STM32L4_TIM2_CHANNEL = 3 - -if STM32L4_TIM2_CHANNEL = 4 - -config STM32L4_TIM2_CH4OUT - bool "TIM2 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32L4_TIM2_CHANNEL = 4 - -config STM32L4_TIM2_CHMODE - int "TIM2 Channel Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32l4_pwm_chanmode_e in stm32l4_pwm.h. - -endif # !STM32L4_PWM_MULTICHAN - -endif # STM32L4_TIM2_PWM - -config STM32L4_TIM3_PWM - bool "TIM3 PWM" - default n - depends on STM32L4_TIM3 - select STM32L4_PWM - ---help--- - Reserve timer 3 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32L4_TIM3 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32L4_TIM3_PWM - -config STM32L4_TIM3_MODE - int "TIM3 Mode" - default 0 - range 0 4 - ---help--- - Specifies the timer mode. - -if STM32L4_PWM_MULTICHAN - -config STM32L4_TIM3_CHANNEL1 - bool "TIM3 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32L4_TIM3_CHANNEL1 - -config STM32L4_TIM3_CH1MODE - int "TIM3 Channel 1 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32l4_pwm_chanmode_e in stm32l4_pwm.h. - -config STM32L4_TIM3_CH1OUT - bool "TIM3 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32L4_TIM3_CHANNEL1 - -config STM32L4_TIM3_CHANNEL2 - bool "TIM3 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32L4_TIM3_CHANNEL2 - -config STM32L4_TIM3_CH2MODE - int "TIM3 Channel 2 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32l4_pwm_chanmode_e in stm32l4_pwm.h. - -config STM32L4_TIM3_CH2OUT - bool "TIM3 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32L4_TIM3_CHANNEL2 - -config STM32L4_TIM3_CHANNEL3 - bool "TIM3 Channel 3" - default n - ---help--- - Enables channel 3. - -if STM32L4_TIM3_CHANNEL3 - -config STM32L4_TIM3_CH3MODE - int "TIM3 Channel 3 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32l4_pwm_chanmode_e in stm32l4_pwm.h. - -config STM32L4_TIM3_CH3OUT - bool "TIM3 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -endif # STM32L4_TIM3_CHANNEL3 - -config STM32L4_TIM3_CHANNEL4 - bool "TIM3 Channel 4" - default n - ---help--- - Enables channel 4. - -if STM32L4_TIM3_CHANNEL4 - -config STM32L4_TIM3_CH4MODE - int "TIM3 Channel 4 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32l4_pwm_chanmode_e in stm32l4_pwm.h. - -config STM32L4_TIM3_CH4OUT - bool "TIM3 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32L4_TIM3_CHANNEL4 - -endif # STM32L4_PWM_MULTICHAN - -if !STM32L4_PWM_MULTICHAN - -config STM32L4_TIM3_CHANNEL - int "TIM3 PWM Output Channel" - default 1 - range 1 4 - ---help--- - If TIM3 is enabled for PWM usage, you also need specifies the timer output - channel {1,..,4} - -if STM32L4_TIM3_CHANNEL = 1 - -config STM32L4_TIM3_CH1OUT - bool "TIM3 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32L4_TIM3_CHANNEL = 1 - -if STM32L4_TIM3_CHANNEL = 2 - -config STM32L4_TIM3_CH2OUT - bool "TIM3 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32L4_TIM3_CHANNEL = 2 - -if STM32L4_TIM3_CHANNEL = 3 - -config STM32L4_TIM3_CH3OUT - bool "TIM3 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -endif # STM32L4_TIM3_CHANNEL = 3 - -if STM32L4_TIM3_CHANNEL = 4 - -config STM32L4_TIM3_CH4OUT - bool "TIM3 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32L4_TIM3_CHANNEL = 4 - -config STM32L4_TIM3_CHMODE - int "TIM3 Channel Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32l4_pwm_chanmode_e in stm32l4_pwm.h. - -endif # !STM32L4_PWM_MULTICHAN - -endif # STM32L4_TIM3_PWM - -config STM32L4_TIM4_PWM - bool "TIM4 PWM" - default n - depends on STM32L4_TIM4 - select STM32L4_PWM - ---help--- - Reserve timer 4 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32L4_TIM4 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32L4_TIM4_PWM - -config STM32L4_TIM4_MODE - int "TIM4 Mode" - default 0 - range 0 4 - ---help--- - Specifies the timer mode. - -if STM32L4_PWM_MULTICHAN - -config STM32L4_TIM4_CHANNEL1 - bool "TIM4 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32L4_TIM4_CHANNEL1 - -config STM32L4_TIM4_CH1MODE - int "TIM4 Channel 1 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32l4_pwm_chanmode_e in stm32l4_pwm.h. - -config STM32L4_TIM4_CH1OUT - bool "TIM4 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32L4_TIM4_CHANNEL1 - -config STM32L4_TIM4_CHANNEL2 - bool "TIM4 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32L4_TIM4_CHANNEL2 - -config STM32L4_TIM4_CH2MODE - int "TIM4 Channel 2 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32l4_pwm_chanmode_e in stm32l4_pwm.h. - -config STM32L4_TIM4_CH2OUT - bool "TIM4 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32L4_TIM4_CHANNEL2 - -config STM32L4_TIM4_CHANNEL3 - bool "TIM4 Channel 3" - default n - ---help--- - Enables channel 3. - -if STM32L4_TIM4_CHANNEL3 - -config STM32L4_TIM4_CH3MODE - int "TIM4 Channel 3 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32l4_pwm_chanmode_e in stm32l4_pwm.h. - -config STM32L4_TIM4_CH3OUT - bool "TIM4 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -endif # STM32L4_TIM4_CHANNEL3 - -config STM32L4_TIM4_CHANNEL4 - bool "TIM4 Channel 4" - default n - ---help--- - Enables channel 4. - -if STM32L4_TIM4_CHANNEL4 - -config STM32L4_TIM4_CH4MODE - int "TIM4 Channel 4 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32l4_pwm_chanmode_e in stm32l4_pwm.h. - -config STM32L4_TIM4_CH4OUT - bool "TIM4 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32L4_TIM4_CHANNEL4 - -endif # STM32L4_PWM_MULTICHAN - -if !STM32L4_PWM_MULTICHAN - -config STM32L4_TIM4_CHANNEL - int "TIM4 PWM Output Channel" - default 1 - range 1 4 - ---help--- - If TIM4 is enabled for PWM usage, you also need specifies the timer output - channel {1,..,4} - -if STM32L4_TIM4_CHANNEL = 1 - -config STM32L4_TIM4_CH1OUT - bool "TIM4 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32L4_TIM4_CHANNEL = 1 - -if STM32L4_TIM4_CHANNEL = 2 - -config STM32L4_TIM4_CH2OUT - bool "TIM4 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32L4_TIM4_CHANNEL = 2 - -if STM32L4_TIM4_CHANNEL = 3 - -config STM32L4_TIM4_CH3OUT - bool "TIM4 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -endif # STM32L4_TIM4_CHANNEL = 3 - -if STM32L4_TIM4_CHANNEL = 4 - -config STM32L4_TIM4_CH4OUT - bool "TIM4 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32L4_TIM4_CHANNEL = 4 - -config STM32L4_TIM4_CHMODE - int "TIM4 Channel Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32l4_pwm_chanmode_e in stm32l4_pwm.h. - -endif # !STM32L4_PWM_MULTICHAN - -endif # STM32L4_TIM4_PWM - -config STM32L4_TIM5_PWM - bool "TIM5 PWM" - default n - depends on STM32L4_TIM5 - select STM32L4_PWM - ---help--- - Reserve timer 5 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32L4_TIM5 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32L4_TIM5_PWM - -config STM32L4_TIM5_MODE - int "TIM5 Mode" - default 0 - range 0 4 - ---help--- - Specifies the timer mode. - -if STM32L4_PWM_MULTICHAN - -config STM32L4_TIM5_CHANNEL1 - bool "TIM5 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32L4_TIM5_CHANNEL1 - -config STM32L4_TIM5_CH1MODE - int "TIM5 Channel 1 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32l4_pwm_chanmode_e in stm32l4_pwm.h. - -config STM32L4_TIM5_CH1OUT - bool "TIM5 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32L4_TIM5_CHANNEL1 - -config STM32L4_TIM5_CHANNEL2 - bool "TIM5 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32L4_TIM5_CHANNEL2 - -config STM32L4_TIM5_CH2MODE - int "TIM5 Channel 2 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32l4_pwm_chanmode_e in stm32l4_pwm.h. - -config STM32L4_TIM5_CH2OUT - bool "TIM5 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32L4_TIM5_CHANNEL2 - -config STM32L4_TIM5_CHANNEL3 - bool "TIM5 Channel 3" - default n - ---help--- - Enables channel 3. - -if STM32L4_TIM5_CHANNEL3 - -config STM32L4_TIM5_CH3MODE - int "TIM5 Channel 3 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32l4_pwm_chanmode_e in stm32l4_pwm.h. - -config STM32L4_TIM5_CH3OUT - bool "TIM5 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -endif # STM32L4_TIM5_CHANNEL3 - -config STM32L4_TIM5_CHANNEL4 - bool "TIM5 Channel 4" - default n - ---help--- - Enables channel 4. - -if STM32L4_TIM5_CHANNEL4 - -config STM32L4_TIM5_CH4MODE - int "TIM5 Channel 4 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32l4_pwm_chanmode_e in stm32l4_pwm.h. - -config STM32L4_TIM5_CH4OUT - bool "TIM5 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32L4_TIM5_CHANNEL4 - -endif # STM32L4_PWM_MULTICHAN - -if !STM32L4_PWM_MULTICHAN - -config STM32L4_TIM5_CHANNEL - int "TIM5 PWM Output Channel" - default 1 - range 1 4 - ---help--- - If TIM5 is enabled for PWM usage, you also need specifies the timer output - channel {1,..,4} - -if STM32L4_TIM5_CHANNEL = 1 - -config STM32L4_TIM5_CH1OUT - bool "TIM5 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32L4_TIM5_CHANNEL = 1 - -if STM32L4_TIM5_CHANNEL = 2 - -config STM32L4_TIM5_CH2OUT - bool "TIM5 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32L4_TIM5_CHANNEL = 2 - -if STM32L4_TIM5_CHANNEL = 3 - -config STM32L4_TIM5_CH3OUT - bool "TIM5 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -endif # STM32L4_TIM5_CHANNEL = 3 - -if STM32L4_TIM5_CHANNEL = 4 - -config STM32L4_TIM5_CH4OUT - bool "TIM5 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32L4_TIM5_CHANNEL = 4 - -config STM32L4_TIM5_CHMODE - int "TIM5 Channel Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32l4_pwm_chanmode_e in stm32l4_pwm.h. - -endif # !STM32L4_PWM_MULTICHAN - -endif # STM32L4_TIM5_PWM - -config STM32L4_TIM8_PWM - bool "TIM8 PWM" - default n - depends on STM32L4_TIM8 - select STM32L4_PWM - ---help--- - Reserve timer 8 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32L4_TIM8 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32L4_TIM8_PWM - -config STM32L4_TIM8_MODE - int "TIM8 Mode" - default 0 - range 0 4 - ---help--- - Specifies the timer mode. - -config STM32L4_TIM8_LOCK - int "TIM1 Lock Level Configuration" - default 0 - range 0 3 - ---help--- - Timer 8 lock level configuration - -config STM32L4_TIM8_TDTS - int "TIM8 t_DTS Division" - default 0 - range 0 2 - ---help--- - Timer 8 dead-time and sampling clock (t_DTS) division - -config STM32L4_TIM8_DEADTIME - int "TIM8 Initial Dead-time" - default 0 - range 0 255 - ---help--- - Timer 8 initial dead-time - -if STM32L4_PWM_MULTICHAN - -config STM32L4_TIM8_CHANNEL1 - bool "TIM8 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32L4_TIM8_CHANNEL1 - -config STM32L4_TIM8_CH1MODE - int "TIM8 Channel 1 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32l4_pwm_chanmode_e in stm32l4_pwm.h. - -config STM32L4_TIM8_CH1OUT - bool "TIM8 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -config STM32L4_TIM8_CH1NOUT - bool "TIM8 Channel 1 Complementary Output" - default n - depends on STM32L4_TIM8_CH1OUT - ---help--- - Enables channel 1 complementary output. - -endif # STM32L4_TIM8_CHANNEL1 - -config STM32L4_TIM8_CHANNEL2 - bool "TIM8 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32L4_TIM8_CHANNEL2 - -config STM32L4_TIM8_CH2MODE - int "TIM8 Channel 2 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32l4_pwm_chanmode_e in stm32l4_pwm.h. - -config STM32L4_TIM8_CH2OUT - bool "TIM8 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -config STM32L4_TIM8_CH2NOUT - bool "TIM8 Channel 2 Complementary Output" - default n - depends on STM32L4_TIM8_CH2OUT - ---help--- - Enables channel 2 complementary output. - -endif # STM32L4_TIM8_CHANNEL2 - -config STM32L4_TIM8_CHANNEL3 - bool "TIM8 Channel 3" - default n - ---help--- - Enables channel 3. - -if STM32L4_TIM8_CHANNEL3 - -config STM32L4_TIM8_CH3MODE - int "TIM8 Channel 3 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32l4_pwm_chanmode_e in stm32l4_pwm.h. - -config STM32L4_TIM8_CH3OUT - bool "TIM8 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -config STM32L4_TIM8_CH3NOUT - bool "TIM8 Channel 3 Complementary Output" - default n - depends on STM32L4_TIM8_CH3OUT - ---help--- - Enables channel 3 complementary output. - -endif # STM32L4_TIM8_CHANNEL3 - -config STM32L4_TIM8_CHANNEL4 - bool "TIM8 Channel 4" - default n - ---help--- - Enables channel 4. - -if STM32L4_TIM8_CHANNEL4 - -config STM32L4_TIM8_CH4MODE - int "TIM8 Channel 4 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32l4_pwm_chanmode_e in stm32l4_pwm.h. - -config STM32L4_TIM8_CH4OUT - bool "TIM8 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32L4_TIM8_CHANNEL4 - -endif # STM32L4_PWM_MULTICHAN - -if !STM32L4_PWM_MULTICHAN - -config STM32L4_TIM8_CHANNEL - int "TIM8 PWM Output Channel" - default 1 - range 1 4 - ---help--- - If TIM8 is enabled for PWM usage, you also need specifies the timer output - channel {1,..,4} - -if STM32L4_TIM8_CHANNEL = 1 - -config STM32L4_TIM8_CH1OUT - bool "TIM8 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -config STM32L4_TIM8_CH1NOUT - bool "TIM8 Channel 1 Complementary Output" - default n - ---help--- - Enables channel 1 Complementary Output. - -endif # STM32L4_TIM8_CHANNEL = 1 - -if STM32L4_TIM8_CHANNEL = 2 - -config STM32L4_TIM8_CH2OUT - bool "TIM8 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -config STM32L4_TIM8_CH2NOUT - bool "TIM8 Channel 2 Complementary Output" - default n - ---help--- - Enables channel 2 Complementary Output. - -endif # STM32L4_TIM8_CHANNEL = 2 - -if STM32L4_TIM8_CHANNEL = 3 - -config STM32L4_TIM8_CH3OUT - bool "TIM8 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -config STM32L4_TIM8_CH3NOUT - bool "TIM8 Channel 3 Complementary Output" - default n - ---help--- - Enables channel 3 Complementary Output. - -endif # STM32L4_TIM8_CHANNEL = 3 - -if STM32L4_TIM8_CHANNEL = 4 - -config STM32L4_TIM8_CH4OUT - bool "TIM8 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32L4_TIM8_CHANNEL = 4 - -config STM32L4_TIM8_CHMODE - int "TIM8 Channel Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32l4_pwm_chanmode_e in stm32l4_pwm.h. - -endif # !STM32L4_PWM_MULTICHAN - -endif # STM32L4_TIM8_PWM - -config STM32L4_TIM15_PWM - bool "TIM15 PWM" - default n - depends on STM32L4_TIM15 - select STM32L4_PWM - ---help--- - Reserve timer 15 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32L4_TIM15 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32L4_TIM15_PWM - -config STM32L4_TIM15_LOCK - int "TIM15 Lock Level Configuration" - default 0 - range 0 3 - ---help--- - Timer 15 lock level configuration - -config STM32L4_TIM15_TDTS - int "TIM15 t_DTS Division" - default 0 - range 0 2 - ---help--- - Timer 15 dead-time and sampling clock (t_DTS) division - -config STM32L4_TIM15_DEADTIME - int "TIM15 Initial Dead-time" - default 0 - range 0 255 - ---help--- - Timer 15 initial dead-time - -if STM32L4_PWM_MULTICHAN - -config STM32L4_TIM15_CHANNEL1 - bool "TIM15 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32L4_TIM15_CHANNEL1 - -config STM32L4_TIM15_CH1MODE - int "TIM15 Channel 1 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32l4_pwm_chanmode_e in stm32l4_pwm.h. - -config STM32L4_TIM15_CH1OUT - bool "TIM15 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -config STM32L4_TIM15_CH1NOUT - bool "TIM15 Channel 1 Complementary Output" - default n - depends on STM32L4_TIM15_CH1OUT - ---help--- - Enables channel 1 complementary output. - -endif # STM32L4_TIM15_CHANNEL1 - -config STM32L4_TIM15_CHANNEL2 - bool "TIM15 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32L4_TIM15_CHANNEL2 - -config STM32L4_TIM15_CH2MODE - int "TIM15 Channel 2 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32l4_pwm_chanmode_e in stm32l4_pwm.h. - -config STM32L4_TIM15_CH2OUT - bool "TIM15 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32L4_TIM15_CHANNEL2 - -endif # STM32L4_PWM_MULTICHAN - -if !STM32L4_PWM_MULTICHAN - -config STM32L4_TIM15_CHANNEL - int "TIM15 PWM Output Channel" - default 1 - range 1 2 - ---help--- - If TIM15 is enabled for PWM usage, you also need specifies the timer output - channel {1,2} - -if STM32L4_TIM15_CHANNEL = 1 - -config STM32L4_TIM15_CH1OUT - bool "TIM15 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -config STM32L4_TIM15_CH1NOUT - bool "TIM15 Channel 1 Complementary Output" - default n - ---help--- - Enables channel 1 Complementary Output. - -endif # STM32L4_TIM15_CHANNEL = 1 - -if STM32L4_TIM15_CHANNEL = 2 - -config STM32L4_TIM15_CH2OUT - bool "TIM15 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -config STM32L4_TIM15_CH2NOUT - bool "TIM15 Channel 2 Complementary Output" - default n - ---help--- - Enables channel 2 Complementary Output. - -endif # STM32L4_TIM15_CHANNEL = 2 - -config STM32L4_TIM15_CHMODE - int "TIM15 Channel Mode" - default 6 - range 0 9 - ---help--- - Specifies the channel mode. See enum stm32l4_pwm_chanmode_e in stm32l4_pwm.h. - -endif # !STM32L4_PWM_MULTICHAN - -endif # STM32L4_TIM15_PWM - -config STM32L4_TIM16_PWM - bool "TIM16 PWM" - default n - depends on STM32L4_TIM16 - select STM32L4_PWM - ---help--- - Reserve timer 16 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32L4_TIM16 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32L4_TIM16_PWM - -config STM32L4_TIM16_LOCK - int "TIM16 Lock Level Configuration" - default 0 - range 0 3 - ---help--- - Timer 16 lock level configuration - -config STM32L4_TIM16_TDTS - int "TIM16 t_DTS Division" - default 0 - range 0 2 - ---help--- - Timer 16 dead-time and sampling clock (t_DTS) division - -config STM32L4_TIM16_DEADTIME - int "TIM16 Initial Dead-time" - default 0 - range 0 255 - ---help--- - Timer 16 initial dead-time - -if STM32L4_PWM_MULTICHAN - -config STM32L4_TIM16_CHANNEL1 - bool "TIM16 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32L4_TIM16_CHANNEL1 - -config STM32L4_TIM16_CH1MODE - int "TIM16 Channel 1 Mode" - default 6 - range 0 7 - ---help--- - Specifies the channel mode. See enum stm32l4_pwm_chanmode_e in stm32l4_pwm.h. - -config STM32L4_TIM16_CH1OUT - bool "TIM16 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -config STM32L4_TIM16_CH1NOUT - bool "TIM16 Channel 1 Complementary Output" - default n - depends on STM32L4_TIM16_CH1OUT - ---help--- - Enables channel 1 complementary output. - -endif # STM32L4_TIM16_CHANNEL1 - -endif # STM32L4_PWM_MULTICHAN - -if !STM32L4_PWM_MULTICHAN - -config STM32L4_TIM16_CHANNEL - int "TIM16 PWM Output Channel" - default 1 - range 1 1 - ---help--- - If TIM16 is enabled for PWM usage, you also need specifies the timer output - channel {1} - -if STM32L4_TIM16_CHANNEL = 1 - -config STM32L4_TIM16_CH1OUT - bool "TIM16 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32L4_TIM16_CHANNEL = 1 - -config STM32L4_TIM16_CHMODE - int "TIM16 Channel Mode" - default 6 - range 0 7 - ---help--- - Specifies the channel mode. See enum stm32l4_pwm_chanmode_e in stm32l4_pwm.h. - -endif # !STM32L4_PWM_MULTICHAN - -endif # STM32L4_TIM16_PWM - -config STM32L4_TIM17_PWM - bool "TIM17 PWM" - default n - depends on STM32L4_TIM17 - select STM32L4_PWM - ---help--- - Reserve timer 17 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32L4_TIM17 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32L4_TIM17_PWM - -config STM32L4_TIM17_LOCK - int "TIM17 Lock Level Configuration" - default 0 - range 0 3 - ---help--- - Timer 17 lock level configuration - -config STM32L4_TIM17_TDTS - int "TIM17 t_DTS Division" - default 0 - range 0 2 - ---help--- - Timer 17 dead-time and sampling clock (t_DTS) division - -config STM32L4_TIM17_DEADTIME - int "TIM17 Initial Dead-time" - default 0 - range 0 255 - ---help--- - Timer 17 initial dead-time - -if STM32L4_PWM_MULTICHAN - -config STM32L4_TIM17_CHANNEL1 - bool "TIM17 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32L4_TIM17_CHANNEL1 - -config STM32L4_TIM17_CH1MODE - int "TIM17 Channel 1 Mode" - default 6 - range 0 7 - ---help--- - Specifies the channel mode. See enum stm32l4_pwm_chanmode_e in stm32l4_pwm.h. - -config STM32L4_TIM17_CH1OUT - bool "TIM17 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -config STM32L4_TIM17_CH1NOUT - bool "TIM17 Channel 1 Complementary Output" - default n - depends on STM32L4_TIM17_CH1OUT - ---help--- - Enables channel 1 complementary output. - -endif # STM32L4_TIM17_CHANNEL1 - -endif # STM32L4_PWM_MULTICHAN - -if !STM32L4_PWM_MULTICHAN - -config STM32L4_TIM17_CHANNEL - int "TIM17 PWM Output Channel" - default 1 - range 1 1 - ---help--- - If TIM17 is enabled for PWM usage, you also need specifies the timer output - channel {1} - -if STM32_TIM17_CHANNEL = 1 - -config STM32L4_TIM17_CH1OUT - bool "TIM17 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32L4_TIM17_CHANNEL = 1 - -config STM32L4_TIM17_CHMODE - int "TIM17 Channel Mode" - default 6 - range 0 7 - ---help--- - Specifies the channel mode. See enum stm32l4_pwm_chanmode_e in stm32l4_pwm.h. - -endif # !STM32L4_PWM_MULTICHAN - -endif # STM32L4_TIM17_PWM - -if STM32L4_LPTIM1_PWM - -if STM32L4_PWM_MULTICHAN - -config STM32L4_LPTIM1_CHANNEL1 - bool "LPTIM1 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32L4_LPTIM1_CHANNEL1 - -config STM32L4_LPTIM1_CH1OUT - bool "LPTIM1 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -config STM32L4_LPTIM1_CH1NOUT - bool "LPTIM1 Channel 1 Complementary Output" - default n - depends on STM32L4_LPTIM1_CH1OUT - ---help--- - Enables channel 1 complementary output. - -endif # STM32L4_LPTIM1_CHANNEL1 - -endif # STM32L4_PWM_MULTICHAN - -if !STM32L4_PWM_MULTICHAN - -config STM32L4_LPTIM1_CHANNEL - int "LPTIM1 PWM Output Channel" - default 1 - range 1 1 - ---help--- - If LPTIM1 is enabled for PWM usage, you also need specifies the timer output - channel {1} - -if STM32L4_LPTIM1_CHANNEL = 1 - -config STM32L4_LPTIM1_CH1OUT - bool "LPTIM1 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -config STM32L4_LPTIM1_CH1NOUT - bool "LPTIM1 Channel 1 Complementary Output" - default n - ---help--- - Enables channel 1 Complementary Output. - -endif # STM32L4_LPTIM1_CHANNEL = 1 - -endif # !STM32L4_PWM_MULTICHAN - -endif # STM32L4_LPTIM1_PWM - -if STM32L4_LPTIM2_PWM - -if STM32L4_PWM_MULTICHAN - -config STM32L4_LPTIM2_CHANNEL1 - bool "LPTIM2 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32L4_LPTIM2_CHANNEL1 - -config STM32L4_LPTIM2_CH1OUT - bool "LPTIM2 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -config STM32L4_LPTIM2_CH1NOUT - bool "LPTIM2 Channel 1 Complementary Output" - default n - depends on STM32L4_LPTIM2_CH1OUT - ---help--- - Enables channel 1 complementary output. - -endif # STM32L4_LPTIM2_CHANNEL1 - -endif # STM32L4_PWM_MULTICHAN - -if !STM32L4_PWM_MULTICHAN - -config STM32L4_LPTIM2_CHANNEL - int "LPTIM2 PWM Output Channel" - default 1 - range 1 1 - ---help--- - If LPTIM2 is enabled for PWM usage, you also need specifies the timer output - channel {1} - -if STM32L4_LPTIM2_CHANNEL = 1 - -config STM32L4_LPTIM2_CH1OUT - bool "LPTIM2 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -config STM32L4_LPTIM2_CH1NOUT - bool "LPTIM2 Channel 1 Complementary Output" - default n - ---help--- - Enables channel 1 Complementary Output. - -endif # STM32L4_LPTIM2_CHANNEL = 1 - -endif # !STM32L4_PWM_MULTICHAN - -endif # STM32L4_LPTIM2_PWM - -config STM32L4_PWM_MULTICHAN - bool "PWM Multiple Output Channels" - default n - depends on STM32L4_PWM - ---help--- - Specifies that the PWM driver supports multiple output - channels per timer. - -config STM32L4_PULSECOUNT - bool - default n - select ARCH_HAVE_PULSECOUNT - select PULSECOUNT - -config STM32L4_TIM1_PULSECOUNT - bool "TIM1 pulse count" - default n - depends on STM32L4_TIM1 - select STM32L4_PULSECOUNT - ---help--- - Reserve timer 1 for pulse count output. - -if STM32L4_TIM1_PULSECOUNT - -config STM32L4_TIM1_PULSECOUNT_TDTS - int "TIM1 pulse count clock division" - default 0 - range 0 2 - -config STM32L4_TIM1_PULSECOUNT_CHANNEL - int "TIM1 pulse count channel" - default 1 - range 1 4 - ---help--- - Specifies the timer channel {1,..,4}. - -config STM32L4_TIM1_PULSECOUNT_POL - int "TIM1 pulse count output polarity" - default 0 - range 0 1 - -config STM32L4_TIM1_PULSECOUNT_IDLE - int "TIM1 pulse count idle state" - default 0 - range 0 1 - -endif # STM32L4_TIM1_PULSECOUNT - -config STM32L4_TIM8_PULSECOUNT - bool "TIM8 pulse count" - default n - depends on STM32L4_TIM8 - select STM32L4_PULSECOUNT - ---help--- - Reserve timer 8 for pulse count output. - -if STM32L4_TIM8_PULSECOUNT - -config STM32L4_TIM8_PULSECOUNT_TDTS - int "TIM8 pulse count clock division" - default 0 - range 0 2 - -config STM32L4_TIM8_PULSECOUNT_CHANNEL - int "TIM8 pulse count channel" - default 1 - range 1 4 - ---help--- - Specifies the timer channel {1,..,4}. - -config STM32L4_TIM8_PULSECOUNT_POL - int "TIM8 pulse count output polarity" - default 0 - range 0 1 - -config STM32L4_TIM8_PULSECOUNT_IDLE - int "TIM8 pulse count idle state" - default 0 - range 0 1 - -endif # STM32L4_TIM8_PULSECOUNT -config STM32L4_TIM1_ADC - bool "TIM1 ADC" - default n - depends on STM32L4_TIM1 && STM32L4_ADC - ---help--- - Reserve timer 1 for use by ADC - - Timer devices may be used for different purposes. If STM32L4_TIM1 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - -choice - prompt "Select ADC to trigger" - default STM32L4_TIM1_ADC1 - depends on STM32L4_TIM1_ADC - -config STM32L4_TIM1_ADC1 - bool "TIM1 trigger ADC1" - depends on STM32L4_ADC1 - select STM32L4_HAVE_ADC1_TIMER - ---help--- - Reserve TIM1 to trigger ADC1 - -config STM32L4_TIM1_ADC2 - bool "TIM1 trigger ADC2" - depends on STM32L4_ADC2 - select STM32L4_HAVE_ADC2_TIMER - ---help--- - Reserve TIM1 to trigger ADC2 - -config STM32L4_TIM1_ADC3 - bool "TIM1 trigger ADC3" - depends on STM32L4_ADC3 - select STM32L4_HAVE_ADC3_TIMER - ---help--- - Reserve TIM1 to trigger ADC3 - -endchoice - -config STM32L4_TIM1_ADC_CHAN - int "TIM1 channel" - default 1 - range 1 4 - depends on STM32L4_TIM1_ADC - ---help--- - Values 1:CC1 2:CC2 3:CC3 4:CC4 - -config STM32L4_TIM2_ADC - bool "TIM2 ADC" - default n - depends on STM32L4_TIM2 && STM32L4_ADC - ---help--- - Reserve timer 2 for use by ADC - - Timer devices may be used for different purposes. If STM32L4_TIM2 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - -choice - prompt "Select ADC to trigger" - default STM32L4_TIM2_ADC1 - depends on STM32L4_TIM2_ADC - -config STM32L4_TIM2_ADC1 - bool "TIM2 trigger ADC1" - depends on STM32L4_ADC1 - select STM32L4_HAVE_ADC1_TIMER - ---help--- - Reserve TIM2 to trigger ADC1 - -config STM32L4_TIM2_ADC2 - bool "TIM2 trigger ADC2" - depends on STM32L4_ADC2 - select STM32L4_HAVE_ADC2_TIMER - ---help--- - Reserve TIM2 to trigger ADC2 - -config STM32L4_TIM2_ADC3 - bool "TIM2 trigger ADC3" - depends on STM32L4_ADC3 - select STM32L4_HAVE_ADC3_TIMER - ---help--- - Reserve TIM2 to trigger ADC3 - -endchoice - -config STM32L4_TIM2_ADC_CHAN - int "TIM2 channel" - default 1 - range 1 4 - depends on STM32L4_TIM2_ADC - ---help--- - Values 1:CC1 2:CC2 3:CC3 4:CC4 - -config STM32L4_TIM3_ADC - bool "TIM3 ADC" - default n - depends on STM32L4_TIM3 && STM32L4_ADC - ---help--- - Reserve timer 3 for use by ADC - - Timer devices may be used for different purposes. If STM32L4_TIM3 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - -choice - prompt "Select ADC to trigger" - default STM32L4_TIM3_ADC1 - depends on STM32L4_TIM3_ADC - -config STM32L4_TIM3_ADC1 - bool "TIM3 trigger ADC1" - depends on STM32L4_ADC1 - select STM32L4_HAVE_ADC1_TIMER - ---help--- - Reserve TIM3 to trigger ADC1 - -config STM32L4_TIM3_ADC2 - bool "TIM3 trigger ADC2" - depends on STM32L4_ADC2 - select STM32L4_HAVE_ADC2_TIMER - ---help--- - Reserve TIM3 to trigger ADC2 - -config STM32L4_TIM3_ADC3 - bool "TIM3 trigger ADC3" - depends on STM32L4_ADC3 - select STM32L4_HAVE_ADC3_TIMER - ---help--- - Reserve TIM3 to trigger ADC3 - -endchoice - -config STM32L4_TIM3_ADC_CHAN - int "TIM3 channel" - default 1 - range 1 4 - depends on STM32L4_TIM3_ADC - ---help--- - Values 1:CC2 2:CC2 3:CC3 4:CC4 - -config STM32L4_TIM4_ADC - bool "TIM4 ADC" - default n - depends on STM32L4_TIM4 && STM32L4_ADC - ---help--- - Reserve timer 4 for use by ADC - - Timer devices may be used for different purposes. If STM32L4_TIM4 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - -choice - prompt "Select ADC to trigger" - default STM32L4_TIM4_ADC1 - depends on STM32L4_TIM4_ADC - -config STM32L4_TIM4_ADC1 - bool "TIM4 trigger ADC1" - depends on STM32L4_ADC1 - select STM32L4_HAVE_ADC1_TIMER - ---help--- - Reserve TIM4 to trigger ADC1 - -config STM32L4_TIM4_ADC2 - bool "TIM4 trigger ADC2" - depends on STM32L4_ADC2 - select STM32L4_HAVE_ADC2_TIMER - ---help--- - Reserve TIM4 to trigger ADC2 - -config STM32L4_TIM4_ADC3 - bool "TIM4 trigger ADC3" - depends on STM32L4_ADC3 - select STM32L4_HAVE_ADC3_TIMER - ---help--- - Reserve TIM4 to trigger ADC3 - -endchoice - -config STM32L4_TIM4_ADC_CHAN - int "TIM4 channel" - default 1 - range 1 4 - depends on STM32L4_TIM4_ADC - ---help--- - Values 1:CC2 2:CC2 3:CC3 4:CC4 - -config STM32L4_TIM6_ADC - bool "TIM6 ADC" - default n - depends on STM32L4_TIM6 && STM32L4_ADC - ---help--- - Reserve timer 6 for use by ADC - - Timer devices may be used for different purposes. If STM32L4_TIM6 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - -choice - prompt "Select ADC to trigger" - default STM32L4_TIM6_ADC1 - depends on STM32L4_TIM6_ADC - -config STM32L4_TIM6_ADC1 - bool "TIM6 trigger ADC1" - depends on STM32L4_ADC1 - select STM32L4_HAVE_ADC1_TIMER - ---help--- - Reserve TIM6 to trigger ADC1 - -config STM32L4_TIM6_ADC2 - bool "TIM6 trigger ADC2" - depends on STM32L4_ADC2 - select STM32L4_HAVE_ADC2_TIMER - ---help--- - Reserve TIM6 to trigger ADC2 - -config STM32L4_TIM6_ADC3 - bool "TIM6 trigger ADC3" - depends on STM32L4_ADC3 - select STM32L4_HAVE_ADC3_TIMER - ---help--- - Reserve TIM6 to trigger ADC3 - -endchoice - -config STM32L4_TIM6_ADC_CHAN - int "TIM6 channel" - default 1 - range 1 4 - depends on STM32L4_TIM6_ADC - ---help--- - Values 1:CC2 2:CC2 3:CC3 4:CC4 - -config STM32L4_TIM8_ADC - bool "TIM8 ADC" - default n - depends on STM32L4_TIM8 && STM32L4_ADC - ---help--- - Reserve timer 8 for use by ADC - - Timer devices may be used for different purposes. If STM32L4_TIM8 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - -choice - prompt "Select ADC to trigger" - default STM32L4_TIM8_ADC1 - depends on STM32L4_TIM8_ADC - -config STM32L4_TIM8_ADC1 - bool "TIM8 trigger ADC1" - depends on STM32L4_ADC1 - select STM32L4_HAVE_ADC1_TIMER - ---help--- - Reserve TIM8 to trigger ADC1 - -config STM32L4_TIM8_ADC2 - bool "TIM8 trigger ADC2" - depends on STM32L4_ADC2 - select STM32L4_HAVE_ADC2_TIMER - ---help--- - Reserve TIM8 to trigger ADC2 - -config STM32L4_TIM8_ADC3 - bool "TIM8 trigger ADC3" - depends on STM32L4_ADC3 - select STM32L4_HAVE_ADC3_TIMER - ---help--- - Reserve TIM8 to trigger ADC3 - -endchoice - -config STM32L4_TIM8_ADC_CHAN - int "TIM8 channel" - default 1 - range 1 4 - depends on STM32L4_TIM8_ADC - ---help--- - Values 1:CC2 2:CC2 3:CC3 4:CC4 - -config STM32L4_TIM15_ADC - bool "TIM15 ADC" - default n - depends on STM32L4_TIM15 && STM32L4_ADC - ---help--- - Reserve timer 15 for use by ADC - - Timer devices may be used for different purposes. If STM32L4_TIM15 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - -choice - prompt "Select ADC to trigger" - default STM32L4_TIM15_ADC1 - depends on STM32L4_TIM15_ADC - -config STM32L4_TIM15_ADC1 - bool "TIM15 trigger ADC1" - depends on STM32L4_ADC1 - select STM32L4_HAVE_ADC1_TIMER - ---help--- - Reserve TIM15 to trigger ADC1 - -config STM32L4_TIM15_ADC2 - bool "TIM15 trigger ADC2" - depends on STM32L4_ADC2 - select STM32L4_HAVE_ADC2_TIMER - ---help--- - Reserve TIM15 to trigger ADC2 - -config STM32L4_TIM15_ADC3 - bool "TIM15 trigger ADC3" - depends on STM32L4_ADC3 - select STM32L4_HAVE_ADC3_TIMER - ---help--- - Reserve TIM15 to trigger ADC3 - -endchoice - -config STM32L4_TIM15_ADC_CHAN - int "TIM15 channel" - default 1 - range 1 4 - depends on STM32L4_TIM15_ADC - ---help--- - Values 1:CC2 2:CC2 3:CC3 4:CC4 - -config STM32L4_HAVE_ADC1_TIMER - bool - -config STM32L4_HAVE_ADC2_TIMER - bool - -config STM32L4_HAVE_ADC3_TIMER - bool - -config STM32L4_ADC1_SAMPLE_FREQUENCY - int "ADC1 Sampling Frequency" - default 100 - depends on STM32L4_HAVE_ADC1_TIMER - ---help--- - ADC1 sampling frequency. Default: 100Hz - -config STM32L4_ADC2_SAMPLE_FREQUENCY - int "ADC2 Sampling Frequency" - default 100 - depends on STM32L4_HAVE_ADC2_TIMER - ---help--- - ADC2 sampling frequency. Default: 100Hz - -config STM32L4_ADC3_SAMPLE_FREQUENCY - int "ADC3 Sampling Frequency" - default 100 - depends on STM32L4_HAVE_ADC3_TIMER - ---help--- - ADC3 sampling frequency. Default: 100Hz - -config STM32L4_TIM1_DAC - bool "TIM1 DAC" - default n - depends on STM32L4_TIM1 && STM32L4_DAC - ---help--- - Reserve timer 1 for use by DAC - - Timer devices may be used for different purposes. If STM32L4_TIM1 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -choice - prompt "Select TIM1 DAC channel" - default STM32L4_TIM1_DAC1 - depends on STM32L4_TIM1_DAC - -config STM32L4_TIM1_DAC1 - bool "TIM1 DAC channel 1" - ---help--- - Reserve TIM1 to trigger DAC1 - -config STM32L4_TIM1_DAC2 - bool "TIM1 DAC channel 2" - ---help--- - Reserve TIM1 to trigger DAC2 - -endchoice - -config STM32L4_TIM2_DAC - bool "TIM2 DAC" - default n - depends on STM32L4_TIM2 && STM32L4_DAC - ---help--- - Reserve timer 2 for use by DAC - - Timer devices may be used for different purposes. If STM32L4_TIM2 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -choice - prompt "Select TIM2 DAC channel" - default STM32L4_TIM2_DAC1 - depends on STM32L4_TIM2_DAC - -config STM32L4_TIM2_DAC1 - bool "TIM2 DAC channel 1" - ---help--- - Reserve TIM2 to trigger DAC1 - -config STM32L4_TIM2_DAC2 - bool "TIM2 DAC channel 2" - ---help--- - Reserve TIM2 to trigger DAC2 - -endchoice - -config STM32L4_TIM3_DAC - bool "TIM3 DAC" - default n - depends on STM32L4_TIM3 && STM32L4_DAC - ---help--- - Reserve timer 3 for use by DAC - - Timer devices may be used for different purposes. If STM32L4_TIM3 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -choice - prompt "Select TIM3 DAC channel" - default STM32L4_TIM3_DAC1 - depends on STM32L4_TIM3_DAC - -config STM32L4_TIM3_DAC1 - bool "TIM3 DAC channel 1" - ---help--- - Reserve TIM3 to trigger DAC1 - -config STM32L4_TIM3_DAC2 - bool "TIM3 DAC channel 2" - ---help--- - Reserve TIM3 to trigger DAC2 - -endchoice - -config STM32L4_TIM4_DAC - bool "TIM4 DAC" - default n - depends on STM32L4_TIM4 && STM32L4_DAC - ---help--- - Reserve timer 4 for use by DAC - - Timer devices may be used for different purposes. If STM32L4_TIM4 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -choice - prompt "Select TIM4 DAC channel" - default STM32L4_TIM4_DAC1 - depends on STM32L4_TIM4_DAC - -config STM32L4_TIM4_DAC1 - bool "TIM4 DAC channel 1" - ---help--- - Reserve TIM4 to trigger DAC1 - -config STM32L4_TIM4_DAC2 - bool "TIM4 DAC channel 2" - ---help--- - Reserve TIM4 to trigger DAC2 - -endchoice - -config STM32L4_TIM5_DAC - bool "TIM5 DAC" - default n - depends on STM32L4_TIM5 && STM32L4_DAC - ---help--- - Reserve timer 5 for use by DAC - - Timer devices may be used for different purposes. If STM32L4_TIM5 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -choice - prompt "Select TIM5 DAC channel" - default STM32L4_TIM5_DAC1 - depends on STM32L4_TIM5_DAC - -config STM32L4_TIM5_DAC1 - bool "TIM5 DAC channel 1" - ---help--- - Reserve TIM5 to trigger DAC1 - -config STM32L4_TIM5_DAC2 - bool "TIM5 DAC channel 2" - ---help--- - Reserve TIM5 to trigger DAC2 - -endchoice - -config STM32L4_TIM6_DAC - bool "TIM6 DAC" - default n - depends on STM32L4_TIM6 && STM32L4_DAC - ---help--- - Reserve timer 6 for use by DAC - - Timer devices may be used for different purposes. If STM32L4_TIM6 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -choice - prompt "Select TIM6 DAC channel" - default STM32L4_TIM6_DAC1 - depends on STM32L4_TIM6_DAC - -config STM32L4_TIM6_DAC1 - bool "TIM6 DAC channel 1" - ---help--- - Reserve TIM6 to trigger DAC1 - -config STM32L4_TIM6_DAC2 - bool "TIM6 DAC channel 2" - ---help--- - Reserve TIM6 to trigger DAC2 - -endchoice - -config STM32L4_TIM7_DAC - bool "TIM7 DAC" - default n - depends on STM32L4_TIM7 && STM32L4_DAC - ---help--- - Reserve timer 7 for use by DAC - - Timer devices may be used for different purposes. If STM32L4_TIM7 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -choice - prompt "Select TIM7 DAC channel" - default STM32L4_TIM7_DAC1 - depends on STM32L4_TIM7_DAC - -config STM32L4_TIM7_DAC1 - bool "TIM7 DAC channel 1" - ---help--- - Reserve TIM7 to trigger DAC1 - -config STM32L4_TIM7_DAC2 - bool "TIM7 DAC channel 2" - ---help--- - Reserve TIM7 to trigger DAC2 - -endchoice - -config STM32L4_TIM8_DAC - bool "TIM8 DAC" - default n - depends on STM32L4_TIM8 && STM32L4_DAC - ---help--- - Reserve timer 8 for use by DAC - - Timer devices may be used for different purposes. If STM32L4_TIM8 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -choice - prompt "Select TIM8 DAC channel" - default STM32L4_TIM8_DAC1 - depends on STM32L4_TIM8_DAC - -config STM32L4_TIM8_DAC1 - bool "TIM8 DAC channel 1" - ---help--- - Reserve TIM8 to trigger DAC1 - -config STM32L4_TIM8_DAC2 - bool "TIM8 DAC channel 2" - ---help--- - Reserve TIM8 to trigger DAC2 - -endchoice - -config STM32L4_TIM1_CAP - bool "TIM1 Capture" - default n - depends on STM32L4_HAVE_TIM1 - ---help--- - Reserve timer 1 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -config STM32L4_TIM2_CAP - bool "TIM2 Capture" - default n - depends on STM32L4_HAVE_TIM2 - ---help--- - Reserve timer 2 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -config STM32L4_TIM3_CAP - bool "TIM3 Capture" - default n - depends on STM32L4_HAVE_TIM3 - ---help--- - Reserve timer 3 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -config STM32L4_TIM4_CAP - bool "TIM4 Capture" - default n - depends on STM32L4_HAVE_TIM4 - ---help--- - Reserve timer 4 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -config STM32L4_TIM5_CAP - bool "TIM5 Capture" - default n - depends on STM32L4_HAVE_TIM5 - ---help--- - Reserve timer 5 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -config STM32L4_TIM8_CAP - bool "TIM8 Capture" - default n - depends on STM32L4_HAVE_TIM8 - ---help--- - Reserve timer 8 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -menu "STM32L4 TIMx Outputs Configuration" - -config STM32L4_TIM1_CH1POL - int "TIM1 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32L4_TIM1_CH1OUT - ---help--- - TIM1 Channel 1 output polarity - -config STM32L4_TIM1_CH1IDLE - int "TIM1 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32L4_TIM1_CH1OUT - ---help--- - TIM1 Channel 1 output IDLE - -config STM32L4_TIM1_CH1NPOL - int "TIM1 Channel 1 Complementary Output polarity" - default 0 - range 0 1 - depends on STM32L4_TIM1_CH1NOUT - ---help--- - TIM1 Channel 1 Complementary Output polarity - -config STM32L4_TIM1_CH1NIDLE - int "TIM1 Channel 1 Complementary Output IDLE" - default 0 - range 0 1 - depends on STM32L4_TIM1_CH1NOUT - ---help--- - TIM1 Channel 1 Complementary Output IDLE - -config STM32L4_TIM1_CH2POL - int "TIM1 Channel 2 Output polarity" - default 0 - range 0 1 - depends on STM32L4_TIM1_CH2OUT - ---help--- - TIM1 Channel 2 output polarity - -config STM32L4_TIM1_CH2IDLE - int "TIM1 Channel 2 Output IDLE" - default 0 - range 0 1 - depends on STM32L4_TIM1_CH2OUT - ---help--- - TIM1 Channel 2 output IDLE - -config STM32L4_TIM1_CH2NPOL - int "TIM1 Channel 2 Complementary Output polarity" - default 0 - range 0 1 - depends on STM32L4_TIM1_CH2NOUT - ---help--- - TIM1 Channel 2 Complementary Output polarity - -config STM32L4_TIM1_CH2NIDLE - int "TIM1 Channel 2 Complementary Output IDLE" - default 0 - range 0 1 - depends on STM32L4_TIM1_CH2NOUT - ---help--- - TIM1 Channel 2 Complementary Output IDLE - -config STM32L4_TIM1_CH3POL - int "TIM1 Channel 3 Output polarity" - default 0 - range 0 1 - depends on STM32L4_TIM1_CH3OUT - ---help--- - TIM1 Channel 3 output polarity - -config STM32L4_TIM1_CH3IDLE - int "TIM1 Channel 3 Output IDLE" - default 0 - range 0 1 - depends on STM32L4_TIM1_CH3OUT - ---help--- - TIM1 Channel 3 output IDLE - -config STM32L4_TIM1_CH3NPOL - int "TIM1 Channel 3 Complementary Output polarity" - default 0 - range 0 1 - depends on STM32L4_TIM1_CH3NOUT - ---help--- - TIM1 Channel 3 Complementary Output polarity - -config STM32L4_TIM1_CH3NIDLE - int "TIM1 Channel 3 Complementary Output IDLE" - default 0 - range 0 1 - depends on STM32L4_TIM1_CH3NOUT - ---help--- - TIM1 Channel 3 Complementary Output IDLE - -config STM32L4_TIM1_CH4POL - int "TIM1 Channel 4 Output polarity" - default 0 - range 0 1 - depends on STM32L4_TIM1_CH4OUT - ---help--- - TIM1 Channel 4 output polarity - -config STM32L4_TIM1_CH4IDLE - int "TIM1 Channel 4 Output IDLE" - default 0 - range 0 1 - depends on STM32L4_TIM1_CH4OUT - ---help--- - TIM1 Channel 4 output IDLE - -config STM32L4_TIM1_CH5POL - int "TIM1 Channel 5 Output polarity" - default 0 - range 0 1 - depends on STM32L4_TIM1_CH5OUT - ---help--- - TIM1 Channel 5 output polarity - -config STM32L4_TIM1_CH5IDLE - int "TIM1 Channel 5 Output IDLE" - default 0 - range 0 1 - depends on STM32L4_TIM1_CH5OUT - ---help--- - TIM1 Channel 5 output IDLE - -config STM32L4_TIM1_CH6POL - int "TIM1 Channel 6 Output polarity" - default 0 - range 0 1 - depends on STM32L4_TIM1_CH6OUT - ---help--- - TIM1 Channel 6 output polarity - -config STM32L4_TIM1_CH6IDLE - int "TIM1 Channel 6 Output IDLE" - default 0 - range 0 1 - depends on STM32L4_TIM1_CH6OUT - ---help--- - TIM1 Channel 6 output IDLE - -config STM32L4_TIM2_CH1POL - int "TIM2 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32L4_TIM2_CH1OUT - ---help--- - TIM2 Channel 1 output polarity - -config STM32L4_TIM2_CH1IDLE - int "TIM2 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32L4_TIM2_CH1OUT - ---help--- - TIM2 Channel 1 output IDLE - -config STM32L4_TIM2_CH2POL - int "TIM2 Channel 2 Output polarity" - default 0 - range 0 1 - depends on STM32L4_TIM2_CH2OUT - ---help--- - TIM2 Channel 2 output polarity - -config STM32L4_TIM2_CH2IDLE - int "TIM2 Channel 2 Output IDLE" - default 0 - range 0 1 - depends on STM32L4_TIM2_CH2OUT - ---help--- - TIM2 Channel 2 output IDLE - -config STM32L4_TIM2_CH3POL - int "TIM2 Channel 3 Output polarity" - default 0 - range 0 1 - depends on STM32L4_TIM2_CH3OUT - ---help--- - TIM2 Channel 3 output polarity - -config STM32L4_TIM2_CH3IDLE - int "TIM2 Channel 3 Output IDLE" - default 0 - range 0 1 - depends on STM32L4_TIM2_CH3OUT - ---help--- - TIM2 Channel 3 output IDLE - -config STM32L4_TIM2_CH4POL - int "TIM2 Channel 4 Output polarity" - default 0 - range 0 1 - depends on STM32L4_TIM2_CH4OUT - ---help--- - TIM2 Channel 4 output polarity - -config STM32L4_TIM2_CH4IDLE - int "TIM2 Channel 4 Output IDLE" - default 0 - range 0 1 - depends on STM32L4_TIM2_CH4OUT - ---help--- - TIM2 Channel 4 output IDLE - -config STM32L4_TIM3_CH1POL - int "TIM3 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32L4_TIM3_CH1OUT - ---help--- - TIM3 Channel 1 output polarity - -config STM32L4_TIM3_CH1IDLE - int "TIM3 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32L4_TIM3_CH1OUT - ---help--- - TIM3 Channel 1 output IDLE - -config STM32L4_TIM3_CH2POL - int "TIM3 Channel 2 Output polarity" - default 0 - range 0 1 - depends on STM32L4_TIM3_CH2OUT - ---help--- - TIM3 Channel 2 output polarity - -config STM32L4_TIM3_CH2IDLE - int "TIM3 Channel 2 Output IDLE" - default 0 - range 0 1 - depends on STM32L4_TIM3_CH2OUT - ---help--- - TIM3 Channel 2 output IDLE - -config STM32L4_TIM3_CH3POL - int "TIM3 Channel 3 Output polarity" - default 0 - range 0 1 - depends on STM32L4_TIM3_CH3OUT - ---help--- - TIM3 Channel 3 output polarity - -config STM32L4_TIM3_CH3IDLE - int "TIM3 Channel 3 Output IDLE" - default 0 - range 0 1 - depends on STM32L4_TIM3_CH3OUT - ---help--- - TIM3 Channel 3 output IDLE - -config STM32L4_TIM3_CH4POL - int "TIM3 Channel 4 Output polarity" - default 0 - range 0 1 - depends on STM32L4_TIM3_CH4OUT - ---help--- - TIM3 Channel 4 output polarity - -config STM32L4_TIM3_CH4IDLE - int "TIM3 Channel 4 Output IDLE" - default 0 - range 0 1 - depends on STM32L4_TIM3_CH4OUT - ---help--- - TIM3 Channel 4 output IDLE - -config STM32L4_TIM4_CH1POL - int "TIM4 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32L4_TIM4_CH1OUT - ---help--- - TIM4 Channel 1 output polarity - -config STM32L4_TIM4_CH1IDLE - int "TIM4 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32L4_TIM4_CH1OUT - ---help--- - TIM4 Channel 1 output IDLE - -config STM32L4_TIM4_CH2POL - int "TIM4 Channel 2 Output polarity" - default 0 - range 0 1 - depends on STM32L4_TIM4_CH2OUT - ---help--- - TIM4 Channel 2 output polarity - -config STM32L4_TIM4_CH2IDLE - int "TIM4 Channel 2 Output IDLE" - default 0 - range 0 1 - depends on STM32L4_TIM4_CH2OUT - ---help--- - TIM4 Channel 2 output IDLE - -config STM32L4_TIM4_CH3POL - int "TIM4 Channel 3 Output polarity" - default 0 - range 0 1 - depends on STM32L4_TIM4_CH3OUT - ---help--- - TIM4 Channel 3 output polarity - -config STM32L4_TIM4_CH3IDLE - int "TIM4 Channel 3 Output IDLE" - default 0 - range 0 1 - depends on STM32L4_TIM4_CH3OUT - ---help--- - TIM4 Channel 3 output IDLE - -config STM32L4_TIM4_CH4POL - int "TIM4 Channel 4 Output polarity" - default 0 - range 0 1 - depends on STM32L4_TIM4_CH4OUT - ---help--- - TIM4 Channel 4 output polarity - -config STM32L4_TIM4_CH4IDLE - int "TIM4 Channel 4 Output IDLE" - default 0 - range 0 1 - depends on STM32L4_TIM4_CH4OUT - ---help--- - TIM4 Channel 4 output IDLE - -config STM32L4_TIM5_CH1POL - int "TIM5 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32L4_TIM5_CH1OUT - ---help--- - TIM5 Channel 1 output polarity - -config STM32L4_TIM5_CH1IDLE - int "TIM5 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32L4_TIM5_CH1OUT - ---help--- - TIM5 Channel 1 output IDLE - -config STM32L4_TIM5_CH2POL - int "TIM5 Channel 2 Output polarity" - default 0 - range 0 1 - depends on STM32L4_TIM5_CH2OUT - ---help--- - TIM5 Channel 2 output polarity - -config STM32L4_TIM5_CH2IDLE - int "TIM5 Channel 2 Output IDLE" - default 0 - range 0 1 - depends on STM32L4_TIM5_CH2OUT - ---help--- - TIM5 Channel 2 output IDLE - -config STM32L4_TIM5_CH3POL - int "TIM5 Channel 3 Output polarity" - default 0 - range 0 1 - depends on STM32L4_TIM5_CH3OUT - ---help--- - TIM5 Channel 3 output polarity - -config STM32L4_TIM5_CH3IDLE - int "TIM5 Channel 3 Output IDLE" - default 0 - range 0 1 - depends on STM32L4_TIM5_CH3OUT - ---help--- - TIM5 Channel 3 output IDLE - -config STM32L4_TIM5_CH4POL - int "TIM5 Channel 4 Output polarity" - default 0 - range 0 1 - depends on STM32L4_TIM5_CH4OUT - ---help--- - TIM5 Channel 4 output polarity - -config STM32L4_TIM5_CH4IDLE - int "TIM5 Channel 4 Output IDLE" - default 0 - range 0 1 - depends on STM32L4_TIM5_CH4OUT - ---help--- - TIM5 Channel 4 output IDLE - -config STM32L4_TIM8_CH1POL - int "TIM8 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32L4_TIM8_CH1OUT - ---help--- - TIM8 Channel 1 output polarity - -config STM32L4_TIM8_CH1IDLE - int "TIM8 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32L4_TIM8_CH1OUT - ---help--- - TIM8 Channel 1 output IDLE - -config STM32L4_TIM8_CH1NPOL - int "TIM8 Channel 1 Complementary Output polarity" - default 0 - range 0 1 - depends on STM32L4_TIM8_CH1NOUT - ---help--- - TIM8 Channel 1 Complementary Output polarity - -config STM32L4_TIM8_CH1NIDLE - int "TIM8 Channel 1 Complementary Output IDLE" - default 0 - range 0 1 - depends on STM32L4_TIM8_CH1NOUT - ---help--- - TIM8 Channel 1 Complementary Output IDLE - -config STM32L4_TIM8_CH2POL - int "TIM8 Channel 2 Output polarity" - default 0 - range 0 1 - depends on STM32L4_TIM8_CH2OUT - ---help--- - TIM8 Channel 2 output polarity - -config STM32L4_TIM8_CH2IDLE - int "TIM8 Channel 2 Output IDLE" - default 0 - range 0 1 - depends on STM32L4_TIM8_CH2OUT - ---help--- - TIM8 Channel 2 output IDLE - -config STM32L4_TIM8_CH2NPOL - int "TIM8 Channel 2 Complementary Output polarity" - default 0 - range 0 1 - depends on STM32L4_TIM8_CH2NOUT - ---help--- - TIM8 Channel 2 Complementary Output polarity - -config STM32L4_TIM8_CH2NIDLE - int "TIM8 Channel 2 Complementary Output IDLE" - default 0 - range 0 1 - depends on STM32L4_TIM8_CH2NOUT - ---help--- - TIM8 Channel 2 Complementary Output IDLE - -config STM32L4_TIM8_CH3POL - int "TIM8 Channel 3 Output polarity" - default 0 - range 0 1 - depends on STM32L4_TIM8_CH3OUT - ---help--- - TIM8 Channel 3 output polarity - -config STM32L4_TIM8_CH3IDLE - int "TIM8 Channel 3 Output IDLE" - default 0 - range 0 1 - depends on STM32L4_TIM8_CH3OUT - ---help--- - TIM8 Channel 3 output IDLE - -config STM32L4_TIM8_CH3NPOL - int "TIM8 Channel 3 Complementary Output polarity" - default 0 - range 0 1 - depends on STM32L4_TIM8_CH3NOUT - ---help--- - TIM8 Channel 3 Complementary Output polarity - -config STM32L4_TIM8_CH3NIDLE - int "TIM8 Channel 3 Complementary Output IDLE" - default 0 - range 0 1 - depends on STM32L4_TIM8_CH3NOUT - ---help--- - TIM8 Channel 3 Complementary Output IDLE - -config STM32L4_TIM8_CH4POL - int "TIM8 Channel 4 Output polarity" - default 0 - range 0 1 - depends on STM32L4_TIM8_CH4OUT - ---help--- - TIM8 Channel 4 output polarity - -config STM32L4_TIM8_CH4IDLE - int "TIM8 Channel 4 Output IDLE" - default 0 - range 0 1 - depends on STM32L4_TIM8_CH4OUT - ---help--- - TIM8 Channel 4 output IDLE - -config STM32L4_TIM8_CH5POL - int "TIM8 Channel 5 Output polarity" - default 0 - range 0 1 - depends on STM32L4_TIM8_CH5OUT - ---help--- - TIM8 Channel 5 output polarity - -config STM32L4_TIM8_CH5IDLE - int "TIM8 Channel 5 Output IDLE" - default 0 - range 0 1 - depends on STM32L4_TIM8_CH5OUT - ---help--- - TIM8 Channel 5 output IDLE - -config STM32L4_TIM8_CH6POL - int "TIM8 Channel 6 Output polarity" - default 0 - range 0 1 - depends on STM32L4_TIM8_CH6OUT - ---help--- - TIM8 Channel 6 output polarity - -config STM32L4_TIM8_CH6IDLE - int "TIM8 Channel 6 Output IDLE" - default 0 - range 0 1 - depends on STM32L4_TIM8_CH6OUT - ---help--- - TIM8 Channel 6 output IDLE - -config STM32L4_TIM9_CH1POL - int "TIM9 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32L4_TIM9_CH1OUT - ---help--- - TIM9 Channel 1 output polarity - -config STM32L4_TIM9_CH1IDLE - int "TIM9 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32L4_TIM9_CH1OUT - ---help--- - TIM9 Channel 1 output IDLE - -config STM32L4_TIM9_CH2POL - int "TIM9 Channel 2 Output polarity" - default 0 - range 0 1 - depends on STM32L4_TIM9_CH2OUT - ---help--- - TIM9 Channel 2 output polarity - -config STM32L4_TIM9_CH2IDLE - int "TIM9 Channel 2 Output IDLE" - default 0 - range 0 1 - depends on STM32L4_TIM9_CH2OUT - ---help--- - TIM9 Channel 2 output IDLE - -config STM32L4_TIM10_CH1POL - int "TIM10 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32L4_TIM10_CH1OUT - ---help--- - TIM10 Channel 1 output polarity - -config STM32L4_TIM10_CH1IDLE - int "TIM10 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32L4_TIM10_CH1OUT - ---help--- - TIM10 Channel 1 output IDLE - -config STM32L4_TIM11_CH1POL - int "TIM11 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32L4_TIM11_CH1OUT - ---help--- - TIM11 Channel 1 output polarity - -config STM32L4_TIM11_CH1IDLE - int "TIM11 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32L4_TIM11_CH1OUT - ---help--- - TIM11 Channel 1 output IDLE - -config STM32L4_TIM12_CH1POL - int "TIM12 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32L4_TIM12_CH1OUT - ---help--- - TIM12 Channel 1 output polarity - -config STM32L4_TIM12_CH1IDLE - int "TIM12 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32L4_TIM12_CH1OUT - ---help--- - TIM12 Channel 1 output IDLE - -config STM32L4_TIM12_CH2POL - int "TIM12 Channel 2 Output polarity" - default 0 - range 0 1 - depends on STM32L4_TIM12_CH2OUT - ---help--- - TIM12 Channel 2 output polarity - -config STM32L4_TIM12_CH2IDLE - int "TIM12 Channel 2 Output IDLE" - default 0 - range 0 1 - depends on STM32L4_TIM12_CH2OUT - ---help--- - TIM12 Channel 2 output IDLE - -config STM32L4_TIM13_CH1POL - int "TIM13 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32L4_TIM13_CH1OUT - ---help--- - TIM13 Channel 1 output polarity - -config STM32L4_TIM13_CH1IDLE - int "TIM13 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32L4_TIM13_CH1OUT - ---help--- - TIM13 Channel 1 output IDLE - -config STM32L4_TIM14_CH1POL - int "TIM14 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32L4_TIM14_CH1OUT - ---help--- - TIM14 Channel 1 output polarity - -config STM32L4_TIM14_CH1IDLE - int "TIM14 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32L4_TIM14_CH1OUT - ---help--- - TIM14 Channel 1 output IDLE - -config STM32L4_TIM15_CH1POL - int "TIM15 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32L4_TIM15_CH1OUT - ---help--- - TIM15 Channel 1 output polarity - -config STM32L4_TIM15_CH1IDLE - int "TIM15 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32L4_TIM15_CH1OUT - ---help--- - TIM15 Channel 1 output IDLE - -config STM32L4_TIM15_CH1NPOL - int "TIM15 Channel 1 Complementary Output polarity" - default 0 - range 0 1 - depends on STM32L4_TIM15_CH1NOUT - ---help--- - TIM15 Channel 1 Complementary Output polarity - -config STM32L4_TIM15_CH1NIDLE - int "TIM15 Channel 1 Complementary Output IDLE" - default 0 - range 0 1 - depends on STM32L4_TIM15_CH1NOUT - ---help--- - TIM15 Channel 1 Complementary Output IDLE - -config STM32L4_TIM15_CH2POL - int "TIM15 Channel 2 Output polarity" - default 0 - range 0 1 - depends on STM32L4_TIM15_CH2OUT - ---help--- - TIM15 Channel 2 output polarity - -config STM32L4_TIM15_CH2IDLE - int "TIM15 Channel 2 Output IDLE" - default 0 - range 0 1 - depends on STM32L4_TIM15_CH2OUT - ---help--- - TIM15 Channel 2 output IDLE - -config STM32L4_TIM15_CH2NPOL - int "TIM15 Channel 2 Complementary Output polarity" - default 0 - range 0 1 - depends on STM32L4_TIM15_CH2NOUT - ---help--- - TIM15 Channel 2 Complementary Output polarity - -config STM32L4_TIM15_CH2NIDLE - int "TIM15 Channel 2 Complementary Output IDLE" - default 0 - range 0 1 - depends on STM32L4_TIM15_CH2NOUT - ---help--- - TIM15 Channel 2 Complementary Output IDLE - -config STM32L4_TIM16_CH1POL - int "TIM16 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32L4_TIM16_CH1OUT - ---help--- - TIM16 Channel 1 output polarity - -config STM32L4_TIM16_CH1IDLE - int "TIM16 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32L4_TIM16_CH1OUT - ---help--- - TIM16 Channel 1 output IDLE - -config STM32L4_TIM17_CH1POL - int "TIM17 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32L4_TIM17_CH1OUT - ---help--- - TIM17 Channel 1 output polarity - -config STM32L4_TIM17_CH1IDLE - int "TIM17 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32L4_TIM17_CH1OUT - ---help--- - TIM17 Channel 1 output IDLE - -endmenu #STM32L4 TIMx Outputs Configuration - -endmenu # Timer Configuration - -menu "ADC Configuration" - depends on STM32L4_ADC - -config STM32L4_ADC_MAX_SAMPLES - int "The maximum number of channels that can be sampled" - default 16 - ---help--- - The maximum number of samples which can be handled without - overrun depends on various factors. This is the user's - responsibility to correctly select this value. - Since the interface to update the sampling time is available - for all supported devices, the user can change the default - values in the board initialization logic and avoid ADC overrun. - -config STM32L4_ADC_NO_STARTUP_CONV - bool "Do not start conversion when opening ADC device" - default n - ---help--- - Do not start conversion when opening ADC device. - -config STM32L4_ADC_NOIRQ - bool "Do not use default ADC interrupts" - default n - ---help--- - Do not use default ADC interrupts handlers. - -config STM32L4_ADC_SMPR - int "ADC sample time" - default 0 - range 0 7 - ---help--- - ADC sample time - 0 - 2.5 ADC clock cycles - 1 - 6.5 ADC clock cycles - 2 - 12.5 ADC clock cycles - 3 - 24.5 ADC clock cycles - 4 - 47.5 ADC clock cycles - 5 - 92.5 ADC clock cycles - 6 - 247.5 ADC clock cycles - 7 - 640.5 ADC clock cycles - -config STM32L4_ADC_LL_OPS - bool "ADC low-level operations" - default n - ---help--- - Enable low-level ADC ops. - -config STM32L4_ADC1_RESOLUTION - int "ADC1 resolution" - depends on STM32L4_ADC1 - default 0 - range 0 3 - ---help--- - ADC1 resolution. 0 - 12 bit, 1 - 10 bit, 2 - 8 bit, 3 - 6 bit - -config STM32L4_ADC2_RESOLUTION - int "ADC2 resolution" - depends on STM32L4_ADC2 - default 0 - range 0 3 - ---help--- - ADC2 resolution. 0 - 12 bit, 1 - 10 bit, 2 - 8 bit, 3 - 6 bit - -config STM32L4_ADC3_RESOLUTION - int "ADC3 resolution" - depends on STM32L4_ADC3 - default 0 - range 0 3 - ---help--- - ADC3 resolution. 0 - 12 bit, 1 - 10 bit, 2 - 8 bit, 3 - 6 bit - -config STM32L4_ADC1_DMA - bool "ADC1 DMA" - depends on STM32L4_ADC1 - default n - ---help--- - If DMA is selected, then the ADC may be configured to support - DMA transfer, which is necessary if multiple channels are read - or if very high trigger frequencies are used. - -config STM32L4_ADC1_DMA_CFG - int "ADC1 DMA configuration" - depends on STM32L4_ADC1_DMA - range 0 1 - default 1 - ---help--- - 0 - ADC1 DMA in One Shot Mode, 1 - ADC1 DMA in Circular Mode - -config STM32L4_ADC1_DMA_BATCH - int "ADC1 DMA number of conversions" - depends on STM32L4_ADC1 && STM32L4_ADC1_DMA - default 1 - ---help--- - This option allows you to select the number of regular group conversions - that will trigger a DMA callback transerring data to the upper-half driver. - By default, this value is 1, which means that data is transferred after - each group conversion. - -config STM32L4_ADC2_DMA - bool "ADC2 DMA" - depends on STM32L4_ADC2 - default n - ---help--- - If DMA is selected, then the ADC may be configured to support - DMA transfer, which is necessary if multiple channels are read - or if very high trigger frequencies are used. - -config STM32L4_ADC2_DMA_CFG - int "ADC2 DMA configuration" - depends on STM32L4_ADC2_DMA - range 0 1 - default 1 - ---help--- - 0 - ADC2 DMA in One Shot Mode, 1 - ADC2 DMA in Circular Mode - -config STM32L4_ADC2_DMA_BATCH - int "ADC2 DMA number of conversions" - depends on STM32L4_ADC2 && STM32L4_ADC2_DMA - default 1 - ---help--- - This option allows you to select the number of regular group conversions - that will trigger a DMA callback transerring data to the upper-half driver. - By default, this value is 1, which means that data is transferred after - each group conversion. - -config STM32L4_ADC3_DMA - bool "ADC3 DMA" - depends on STM32L4_ADC3 - default n - ---help--- - If DMA is selected, then the ADC may be configured to support - DMA transfer, which is necessary if multiple channels are read - or if very high trigger frequencies are used. - -config STM32L4_ADC3_DMA_CFG - int "ADC3 DMA configuration" - depends on STM32L4_ADC3_DMA - range 0 1 - default 1 - ---help--- - 0 - ADC3 DMA in One Shot Mode, 1 - ADC3 DMA in Circular Mode - -config STM32L4_ADC3_DMA_BATCH - int "ADC2 DMA number of conversions" - depends on STM32L4_ADC3 && STM32L4_ADC3_DMA - default 1 - ---help--- - This option allows you to select the number of regular group conversions - that will trigger a DMA callback transerring data to the upper-half driver. - By default, this value is 1, which means that data is transferred after - each group conversion. - -config STM32L4_ADC1_INJ_CHAN - int "ADC1 configured injected channels" - depends on STM32L4_ADC1 - range 0 4 - default 0 - ---help--- - Number of configured ADC1 injected channels. - -config STM32L4_ADC2_INJ_CHAN - int "ADC2 configured injected channels" - depends on STM32L4_ADC2 - range 0 4 - default 0 - ---help--- - Number of configured ADC2 injected channels. - -config STM32L4_ADC3_INJ_CHAN - int "ADC3 configured injected channels" - depends on STM32L4_ADC3 - range 0 4 - default 0 - ---help--- - Number of configured ADC3 injected channels. - -config STM32L4_ADC1_OUTPUT_DFSDM - bool "ADC1 output to DFSDM" - depends on STM32L4_ADC1 && STM32L4_DFSDM1 && (STM32L4_STM32L496XX || STM32L4_STM32L4XR) - default n - ---help--- - Route ADC1 output directly to DFSDM parallel inputs. - -config STM32L4_ADC2_OUTPUT_DFSDM - bool "ADC2 output to DFSDM" - depends on STM32L4_ADC2 && STM32L4_DFSDM1 && STM32L4_STM32L496XX - default n - ---help--- - Route ADC2 output directly to DFSDM parallel inputs. - -config STM32L4_ADC3_OUTPUT_DFSDM - bool "ADC3 output to DFSDM" - depends on STM32L4_ADC3 && STM32L4_DFSDM1 && STM32L4_STM32L496XX - default n - ---help--- - Route ADC3 output directly to DFSDM parallel inputs. - -menu "STM32L4 ADCx triggering Configuration" - -config STM32L4_ADC1_EXTTRIG - int "ADC1 External trigger configuration for regular channels" - default 0 - range 0 4 - depends on STM32L4_ADC1 - ---help--- - Values 0: Hardware trigger detection disabled - 1: Hardware trigger detection on the rising edge - 2: Hardware trigger detection on the falling edge - 3: Hardware trigger detection on the rising and falling edges - -if STM32L4_ADC1_EXTTRIG > 0 - -config STM32L4_ADC1_EXTSEL - int "ADC1 External trigger selection for regular group" - default 0 - range 0 15 - depends on STM32L4_ADC1 - ---help--- - Select the external event used to trigger the start of conversion of - a regular group. See Reference Manual for more information. - -endif - -config STM32L4_ADC2_EXTTRIG - int "ADC2 External trigger configuration for regular channels" - default 0 - range 0 4 - depends on STM32L4_ADC2 - ---help--- - Values 0: Hardware trigger detection disabled - 1: Hardware trigger detection on the rising edge - 2: Hardware trigger detection on the falling edge - 3: Hardware trigger detection on the rising and falling edges - -if STM32L4_ADC2_EXTTRIG > 0 - -config STM32L4_ADC2_EXTSEL - int "ADC2 External trigger selection for regular group" - default 0 - range 0 15 - depends on STM32L4_ADC2 - ---help--- - Select the external event used to trigger the start of conversion of - a regular group. See Reference Manual for more information. - -endif - -config STM32L4_ADC3_EXTTRIG - int "ADC3 External trigger configuration for regular channels" - default 0 - range 0 4 - depends on STM32L4_ADC3 - ---help--- - Values 0: Hardware trigger detection disabled - 1: Hardware trigger detection on the rising edge - 2: Hardware trigger detection on the falling edge - 3: Hardware trigger detection on the rising and falling edges - -if STM32L4_ADC3_EXTTRIG > 0 - -config STM32L4_ADC3_EXTSEL - int "ADC3 External trigger selection for regular group" - default 0 - range 0 15 - depends on STM32L4_ADC3 - ---help--- - Select the external event used to trigger the start of conversion of - a regular group. See Reference Manual for more information. - -endif - -if STM32L4_ADC1_INJ_CHAN > 0 - -config STM32L4_ADC1_JEXTTRIG - int "ADC1 External Trigger Enable and Polarity Selection for injected channels" - default 0 - range 0 4 - depends on STM32L4_ADC1 - ---help--- - Values 0: Hardware and software trigger detection disabled, JQDIS=0 - (queue enabled) - 0: Hardware trigger detection disabled, JQDIS=1 (queue disabled) - 1: Hardware trigger detection on the rising edge - 2: Hardware trigger detection on the falling edge - 3: Hardware trigger detection on the rising and falling edges - -if STM32L4_ADC1_JEXTTRIG > 0 - -config STM32L4_ADC1_JEXTSEL - int "ADC1 External Trigger Selection for injected group" - default 0 - range 0 15 - depends on STM32L4_ADC1 - ---help--- - Select the external event used to trigger the start of conversion of an - injected group - -endif - -endif - -if STM32L4_ADC2_INJ_CHAN > 0 - -config STM32L4_ADC2_JEXTTRIG - int "ADC2 External Trigger Enable and Polarity Selection for injected channels" - default 0 - range 0 4 - depends on STM32L4_ADC2 - ---help--- - Values 0: Hardware and software trigger detection disabled, JQDIS=0 - (queue enabled) - 0: Hardware trigger detection disabled, JQDIS=1 (queue disabled) - 1: Hardware trigger detection on the rising edge - 2: Hardware trigger detection on the falling edge - 3: Hardware trigger detection on the rising and falling edges - -if STM32L4_ADC2_JEXTTRIG > 0 - -config STM32L4_ADC2_JEXTSEL - int "ADC2 External Trigger Selection for injected group" - default 0 - range 0 5 - depends on STM32L4_ADC2 - ---help--- - Select the external event used to trigger the start of conversion of an - injected group - -endif - -endif - -if STM32L4_ADC3_INJ_CHAN > 0 - -config STM32L4_ADC3_JEXTTRIG - int "ADC3 External Trigger Enable and Polarity Selection for injected channels" - default 0 - range 0 4 - depends on STM32L4_ADC3 - ---help--- - Values 0: Hardware and software trigger detection disabled, JQDIS=0 - (queue enabled) - 0: Hardware trigger detection disabled, JQDIS=1 (queue disabled) - 1: Hardware trigger detection on the rising edge - 2: Hardware trigger detection on the falling edge - 3: Hardware trigger detection on the rising and falling edges - -if STM32L4_ADC3_JEXTTRIG > 0 - -config STM32L4_ADC3_JEXTSEL - int "ADC3 External Trigger Selection for injected group" - default 0 - range 0 5 - depends on STM32L4_ADC3 - ---help--- - Select the external event used to trigger the start of conversion of an - injected group - -endif - -endif - -endmenu #STM32L4 ADCx triggering Configuration - -endmenu - -menu "DAC Configuration" - depends on STM32L4_DAC - -config STM32L4_DAC1_DMA - bool "DAC1 DMA" - depends on STM32L4_DAC1 - default n - ---help--- - If DMA is selected, then a timer and output frequency must also be - provided to support the DMA transfer. The DMA transfer could be - supported by an EXTI trigger, but this feature is not currently - supported by the driver. - -if STM32L4_DAC1_DMA - -config STM32L4_DAC1_TIMER - int "DAC1 timer" - range 2 8 - -config STM32L4_DAC1_TIMER_FREQUENCY - int "DAC1 timer frequency" - default 100 - ---help--- - DAC1 output frequency. Default: 100Hz - -config STM32L4_DAC1_DMA_BUFFER_SIZE - int "DAC1 DMA buffer size" - default 1 - -endif - -config STM32L4_DAC1_OUTPUT_ADC - bool "DAC1 output to ADC" - depends on STM32L4_DAC1 - default n - ---help--- - Route DAC1 output to ADC input instead of external pin. - -config STM32L4_DAC2_DMA - bool "DAC2 DMA" - depends on STM32L4_DAC2 - default n - ---help--- - If DMA is selected, then a timer and output frequency must also be - provided to support the DMA transfer. The DMA transfer could be - supported by an EXTI trigger, but this feature is not currently - supported by the driver. - -if STM32L4_DAC2_DMA - -config STM32L4_DAC2_TIMER - int "DAC2 timer" - default 0 - range 2 8 - -config STM32L4_DAC2_TIMER_FREQUENCY - int "DAC2 timer frequency" - default 100 - ---help--- - DAC2 output frequency. Default: 100Hz - -config STM32L4_DAC2_DMA_BUFFER_SIZE - int "DAC2 DMA buffer size" - default 1 - -endif - -config STM32L4_DAC2_OUTPUT_ADC - bool "DAC2 output to ADC" - depends on STM32L4_DAC2 - default n - ---help--- - Route DAC2 output to ADC input instead of external pin. - -config STM32L4_DAC_LL_OPS - bool "DAC low-level operations" - default n - ---help--- - Enable low-level DAC ops. - -endmenu - -menu "DFSDM Configuration" - depends on STM32L4_DFSDM1 - -config STM32L4_DFSDM1_FLT0 - bool "DFSDM1 Filter 0" - default n - select STM32L4_DFSDM - -config STM32L4_DFSDM1_FLT1 - bool "DFSDM1 Filter 1" - default n - select STM32L4_DFSDM - -config STM32L4_DFSDM1_FLT2 - bool "DFSDM1 Filter 2" - default n - depends on !STM32L4_STM32L4X3 - select STM32L4_DFSDM - -config STM32L4_DFSDM1_FLT3 - bool "DFSDM1 Filter 3" - default n - depends on !STM32L4_STM32L4X3 - select STM32L4_DFSDM - -config STM32L4_DFSDM1_DMA - bool "DFSDM1 DMA" - depends on STM32L4_DFSDM - default n - ---help--- - If DMA is selected, then the DFSDM may be configured to support - DMA transfer, which is necessary if multiple channels are read - or if very high trigger frequencies are used. - -endmenu - -config STM32L4_SERIALDRIVER - bool - -config STM32L4_1WIREDRIVER - bool - -menu "[LP]U[S]ART Configuration" - depends on STM32L4_USART - -choice - prompt "LPUART1 Driver Configuration" - default STM32L4_LPUART1_SERIALDRIVER - depends on STM32L4_LPUART1 - -config STM32L4_LPUART1_SERIALDRIVER - bool "Standard serial driver" - select LPUART1_SERIALDRIVER - select STM32L4_SERIALDRIVER - -config STM32L4_LPUART1_1WIREDRIVER - bool "1-Wire driver" - select STM32L4_1WIREDRIVER - -endchoice # LPUART1 Driver Configuration - -if LPUART1_SERIALDRIVER - -config LPUART1_RS485 - bool "RS-485 on LPUART1" - default n - depends on STM32L4_LPUART1 - ---help--- - Enable RS-485 interface on LPUART1. Your board config will have to - provide GPIO_LPUART1_RS485_DIR pin definition. Currently it cannot be - used with LPUART1_RXDMA. - -config LPUART1_RS485_DIR_POLARITY - int "LPUART1 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on LPUART1_RS485 - ---help--- - Polarity of DIR pin for RS-485 on LPUART1. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config LPUART1_RXDMA - bool "LPUART1 Rx DMA" - default n - depends on STM32L4_LPUART1 && (STM32L4_DMA1 || STM32L4_DMA2 || STM32L4_DMAMUX) - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -endif # LPUART1_SERIALDRIVER - -choice - prompt "USART1 Driver Configuration" - default STM32L4_USART1_SERIALDRIVER - depends on STM32L4_USART1 - -config STM32L4_USART1_SERIALDRIVER - bool "Standard serial driver" - select USART1_SERIALDRIVER - select STM32L4_SERIALDRIVER - -config STM32L4_USART1_1WIREDRIVER - bool "1-Wire driver" - select STM32L4_1WIREDRIVER - -endchoice # USART1 Driver Configuration - -if USART1_SERIALDRIVER - -config USART1_RS485 - bool "RS-485 on USART1" - default n - depends on STM32L4_USART1 - ---help--- - Enable RS-485 interface on USART1. Your board config will have to - provide GPIO_USART1_RS485_DIR pin definition. Currently it cannot be - used with USART1_RXDMA. - -config USART1_RS485_DIR_POLARITY - int "USART1 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on USART1_RS485 - ---help--- - Polarity of DIR pin for RS-485 on USART1. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config USART1_RXDMA - bool "USART1 Rx DMA" - default n - depends on STM32L4_USART1 && (STM32L4_DMA1 || STM32L4_DMA2 || STM32L4_DMAMUX) - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -endif # USART1_SERIALDRIVER - -choice - prompt "USART2 Driver Configuration" - default STM32L4_USART2_SERIALDRIVER - depends on STM32L4_USART2 - -config STM32L4_USART2_SERIALDRIVER - bool "Standard serial driver" - select USART2_SERIALDRIVER - select STM32L4_SERIALDRIVER - -config STM32L4_USART2_1WIREDRIVER - bool "1-Wire driver" - select STM32L4_1WIREDRIVER - -endchoice # USART2 Driver Configuration - -if USART2_SERIALDRIVER - -config USART2_RS485 - bool "RS-485 on USART2" - default n - depends on STM32L4_USART2 - ---help--- - Enable RS-485 interface on USART2. Your board config will have to - provide GPIO_USART2_RS485_DIR pin definition. Currently it cannot be - used with USART2_RXDMA. - -config USART2_RS485_DIR_POLARITY - int "USART2 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on USART2_RS485 - ---help--- - Polarity of DIR pin for RS-485 on USART2. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config USART2_RXDMA - bool "USART2 Rx DMA" - default n - depends on STM32L4_USART2 && (STM32L4_DMA1 || STM32L4_DMAMUX) - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -endif # USART2_SERIALDRIVER - -choice - prompt "USART3 Driver Configuration" - default STM32L4_USART3_SERIALDRIVER - depends on STM32L4_USART3 - -config STM32L4_USART3_SERIALDRIVER - bool "Standard serial driver" - select USART3_SERIALDRIVER - select STM32L4_SERIALDRIVER - -config STM32L4_USART3_1WIREDRIVER - bool "1-Wire driver" - select STM32L4_1WIREDRIVER - -endchoice # USART3 Driver Configuration - -if USART3_SERIALDRIVER - -config USART3_RS485 - bool "RS-485 on USART3" - default n - depends on STM32L4_USART3 - ---help--- - Enable RS-485 interface on USART3. Your board config will have to - provide GPIO_USART3_RS485_DIR pin definition. Currently it cannot be - used with USART3_RXDMA. - -config USART3_RS485_DIR_POLARITY - int "USART3 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on USART3_RS485 - ---help--- - Polarity of DIR pin for RS-485 on USART3. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config USART3_RXDMA - bool "USART3 Rx DMA" - default n - depends on STM32L4_USART3 && (STM32L4_DMA1 || STM32L4_DMAMUX) - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -endif # USART3_SERIALDRIVER - -choice - prompt "UART4 Driver Configuration" - default STM32L4_UART4_SERIALDRIVER - depends on STM32L4_UART4 - -config STM32L4_UART4_SERIALDRIVER - bool "Standard serial driver" - select UART4_SERIALDRIVER - select STM32L4_SERIALDRIVER - -config STM32L4_UART4_1WIREDRIVER - bool "1-Wire driver" - select STM32L4_1WIREDRIVER - -endchoice # UART4 Driver Configuration - -if UART4_SERIALDRIVER - -config UART4_RS485 - bool "RS-485 on UART4" - default n - depends on STM32L4_UART4 - ---help--- - Enable RS-485 interface on UART4. Your board config will have to - provide GPIO_UART4_RS485_DIR pin definition. Currently it cannot be - used with UART4_RXDMA. - -config UART4_RS485_DIR_POLARITY - int "UART4 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on UART4_RS485 - ---help--- - Polarity of DIR pin for RS-485 on UART4. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config UART4_RXDMA - bool "UART4 Rx DMA" - default n - depends on STM32L4_UART4 && (STM32L4_DMA2 || STM32L4_DMAMUX) - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -endif # UART4_SERIALDRIVER - -choice - prompt "UART5 Driver Configuration" - default STM32L4_UART5_SERIALDRIVER - depends on STM32L4_UART5 - -config STM32L4_UART5_SERIALDRIVER - bool "Standard serial driver" - select UART5_SERIALDRIVER - select STM32L4_SERIALDRIVER - -config STM32L4_UART5_1WIREDRIVER - bool "1-Wire driver" - select STM32L4_1WIREDRIVER - -endchoice # UART5 Driver Configuration - -if UART5_SERIALDRIVER - -config UART5_RS485 - bool "RS-485 on UART5" - default n - depends on STM32L4_UART5 - ---help--- - Enable RS-485 interface on UART5. Your board config will have to - provide GPIO_UART5_RS485_DIR pin definition. Currently it cannot be - used with UART5_RXDMA. - -config UART5_RS485_DIR_POLARITY - int "UART5 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on UART5_RS485 - ---help--- - Polarity of DIR pin for RS-485 on UART5. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config UART5_RXDMA - bool "UART5 Rx DMA" - default n - depends on STM32L4_UART5 && (STM32L4_DMA2 || STM32L4_DMAMUX) - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -endif # UART5_SERIALDRIVER - -if STM32L4_SERIALDRIVER - -comment "Serial Driver Configuration" - -config STM32L4_SERIAL_RXDMA_BUFFER_SIZE - int "Rx DMA buffer size" - default 32 - depends on USART1_RXDMA || USART2_RXDMA || USART3_RXDMA || UART4_RXDMA || UART5_RXDMA - ---help--- - The DMA buffer size when using RX DMA to emulate a FIFO. - - When streaming data, the generic serial layer will be called - every time the FIFO receives half this number of bytes. - - Value given here will be rounded up to next multiple of 32 bytes. - -config STM32L4_SERIAL_DISABLE_REORDERING - bool "Disable reordering of ttySx devices." - depends on STM32L4_USART1 || STM32L4_USART2 || STM32L4_USART3 || STM32L4_UART4 || STM32L4_UART5 - default n - ---help--- - NuttX per default reorders the serial ports (/dev/ttySx) so that the - console is always on /dev/ttyS0. If more than one UART is in use this - can, however, have the side-effect that all port mappings - (hardware USART1 -> /dev/ttyS0) change if the console is moved to another - UART. This is in particular relevant if a project uses the USB console - in some boards and a serial console in other boards, but does not - want the side effect of having all serial port names change when just - the console is moved from serial to USB. - -config STM32L4_FLOWCONTROL_BROKEN - bool "Use Software UART RTS flow control" - depends on STM32L4_USART - default n - ---help--- - Enable UART RTS flow control using Software. Because STM - Current STM32 have broken HW based RTS behavior (they assert - nRTS after every byte received) Enable this setting workaround - this issue by using software based management of RTS - -config STM32L4_USART_BREAKS - bool "Add TIOxSBRK to support sending Breaks" - depends on STM32L4_USART - default n - ---help--- - Add TIOCxBRK routines to send a line break per the STM32 manual, the - break will be a pulse based on the value M. This is not a BSD compatible - break. - -config STM32L4_SERIALBRK_BSDCOMPAT - bool "Use GPIO To send Break" - depends on STM32L4_USART && STM32L4_USART_BREAKS - default n - ---help--- - Enable using GPIO on the TX pin to send a BSD compatible break: - TIOCSBRK will start the break and TIOCCBRK will end the break. - The current STM32L4 U[S]ARTS have no way to leave the break on - (TX=LOW) because software starts the break and then the hardware - automatically clears the break. This makes it difficult to send - a long break. - -config STM32L4_USART_SINGLEWIRE - bool "Single Wire Support" - default n - depends on STM32L4_USART - ---help--- - Enable single wire UART support. The option enables support for the - TIOCSSINGLEWIRE ioctl in the STM32L4 serial driver. - -config STM32L4_USART_INVERT - bool "Signal Invert Support" - default n - depends on STM32L4_USART - ---help--- - Enable signal inversion UART support. The option enables support for the - TIOCSINVERT ioctl in the STM32L4 serial driver. - -config STM32L4_USART_SWAP - bool "Swap RX/TX pins support" - default n - depends on STM32L4_USART - ---help--- - Enable RX/TX pin swapping support. The option enables support for the - TIOCSSWAP ioctl in the STM32L4 serial driver. - -if PM - -config STM32L4_PM_SERIAL_ACTIVITY - int "PM serial activity" - default 10 - ---help--- - PM activity reported to power management logic on every serial - interrupt. - -endif -endif # STM32L4_SERIALDRIVER - -endmenu # U[S]ART Configuration - -menu "SPI Configuration" - depends on STM32L4_SPI - -config STM32L4_SPI_INTERRUPTS - bool "Interrupt driver SPI" - default n - ---help--- - Select to enable interrupt driven SPI support. Non-interrupt-driven, - poll-waiting is recommended if the interrupt rate would be to high in - the interrupt driven case. - -config STM32L4_SPI_DMA - bool "SPI DMA" - default n - ---help--- - Use DMA to improve SPI transfer performance. Cannot be used with STM32L4_SPI_INTERRUPT. - -endmenu - -menu "I2C Configuration" - depends on STM32L4_I2C - -config STM32L4_I2C_DYNTIMEO - bool "Use dynamic timeouts" - default n - depends on STM32L4_I2C - -config STM32L4_I2C_DYNTIMEO_USECPERBYTE - int "Timeout Microseconds per Byte" - default 500 - depends on STM32L4_I2C_DYNTIMEO - -config STM32L4_I2C_DYNTIMEO_STARTSTOP - int "Timeout for Start/Stop (Milliseconds)" - default 1000 - depends on STM32L4_I2C_DYNTIMEO - -config STM32L4_I2CTIMEOSEC - int "Timeout seconds" - default 0 - depends on STM32L4_I2C - -config STM32L4_I2CTIMEOMS - int "Timeout Milliseconds" - default 500 - depends on STM32L4_I2C && !STM32L4_I2C_DYNTIMEO - -config STM32L4_I2CTIMEOTICKS - int "Timeout for Done and Stop (ticks)" - default 500 - depends on STM32L4_I2C && !STM32L4_I2C_DYNTIMEO - -endmenu - -menu "SD/MMC Configuration" - depends on STM32L4_SDMMC - -config STM32L4_SDMMC_XFRDEBUG - bool "SDMMC transfer debug" - depends on DEBUG_FS_INFO - default n - ---help--- - Enable special debug instrumentation analyze SDMMC data transfers. - This logic is as non-invasive as possible: It samples SDMMC - registers at key points in the data transfer and then dumps all of - the registers at the end of the transfer. If DEBUG_DMA is also - enabled, then DMA register will be collected as well. Requires also - DEBUG_FS and CONFIG_DEBUG_INFO. - -config STM32L4_SDMMC_DMA - bool "Support DMA data transfers" - default n - select SDIO_DMA - depends on STM32L4_DMA - ---help--- - Support DMA data transfers. - -menu "SDMMC1 Configuration" - depends on STM32L4_SDMMC1 - -config STM32L4_SDMMC1_DMAPRIO - hex "SDMMC1 DMA priority" - default 0x00001000 - ---help--- - Select SDMMC1 DMA priority. - - Options are: 0x00000000 low, 0x00001000 medium, - 0x00002000 high, 0x00003000 very high. Default: medium. - -config SDMMC1_WIDTH_D1_ONLY - bool "Use D1 only on SDMMC1" - default n - ---help--- - Select 1-bit transfer mode. Default: 4-bit transfer mode. - -endmenu # SDMMC1 Configuration -endmenu # SD/MMC Configuration - -menu "CAN driver configuration" - depends on STM32L4_CAN1 || STM32L4_CAN2 - -config STM32L4_CAN1_BAUD - int "CAN1 BAUD" - default 250000 - depends on STM32L4_CAN1 - ---help--- - CAN1 BAUD rate. Required if CONFIG_STM32L4_CAN1 is defined. - -config STM32L4_CAN2_BAUD - int "CAN2 BAUD" - default 250000 - depends on STM32L4_CAN2 - ---help--- - CAN2 BAUD rate. Required if CONFIG_STM32L4_CAN2 is defined. - -config STM32L4_CAN_TSEG1 - int "TSEG1 quanta" - default 6 - ---help--- - The number of CAN time quanta in segment 1. Default: 6 - -config STM32L4_CAN_TSEG2 - int "TSEG2 quanta" - default 7 - ---help--- - The number of CAN time quanta in segment 2. Default: 7 - -config STM32L4_CAN_REGDEBUG - bool "CAN Register level debug" - depends on DEBUG_CAN_INFO - default n - ---help--- - Output detailed register-level CAN device debug information. - Requires also CONFIG_DEBUG_CAN_INFO. - -endmenu - -menu "QEncoder Driver" - depends on SENSORS_QENCODER - depends on STM32L4_TIM1 || STM32L4_TIM2 || STM32L4_TIM3 || STM32L4_TIM4 || STM32L4_TIM5 || STM32L4_TIM8 - -config STM32L4_TIM1_QE - bool "TIM1" - default n - depends on STM32L4_TIM1 - ---help--- - Reserve TIM1 for use by QEncoder. - -if STM32L4_TIM1_QE - -config STM32L4_TIM1_QEPSC - int "TIM1 pulse prescaler" - default 1 - ---help--- - This prescaler divides the number of recorded encoder pulses, limiting the count rate at the expense of resolution. - -endif - -config STM32L4_TIM2_QE - bool "TIM2" - default n - depends on STM32L4_TIM2 - ---help--- - Reserve TIM2 for use by QEncoder. - -if STM32L4_TIM2_QE - -config STM32L4_TIM2_QEPSC - int "TIM2 pulse prescaler" - default 1 - ---help--- - This prescaler divides the number of recorded encoder pulses, limiting the count rate at the expense of resolution. - -endif - -config STM32L4_TIM3_QE - bool "TIM3" - default n - depends on STM32L4_TIM3 - ---help--- - Reserve TIM3 for use by QEncoder. - -if STM32L4_TIM3_QE - -config STM32L4_TIM3_QEPSC - int "TIM3 pulse prescaler" - default 1 - ---help--- - This prescaler divides the number of recorded encoder pulses, limiting the count rate at the expense of resolution. - -endif - -config STM32L4_TIM4_QE - bool "TIM4" - default n - depends on STM32L4_TIM4 - ---help--- - Reserve TIM4 for use by QEncoder. - -if STM32L4_TIM4_QE - -config STM32L4_TIM4_QEPSC - int "TIM4 pulse prescaler" - default 1 - ---help--- - This prescaler divides the number of recorded encoder pulses, limiting the count rate at the expense of resolution. - -endif - -config STM32L4_TIM5_QE - bool "TIM5" - default n - depends on STM32L4_TIM5 - ---help--- - Reserve TIM5 for use by QEncoder. - -if STM32L4_TIM5_QE - -config STM32L4_TIM5_QEPSC - int "TIM5 pulse prescaler" - default 1 - ---help--- - This prescaler divides the number of recorded encoder pulses, limiting the count rate at the expense of resolution. - -endif - -config STM32L4_TIM8_QE - bool "TIM8" - default n - depends on STM32L4_TIM8 - ---help--- - Reserve TIM8 for use by QEncoder. - -if STM32L4_TIM8_QE - -config STM32L4_TIM8_QEPSC - int "TIM8 pulse prescaler" - default 1 - ---help--- - This prescaler divides the number of recorded encoder pulses, limiting the count rate at the expense of resolution. - -endif - -config STM32L4_QENCODER_FILTER - bool "Enable filtering on STM32 QEncoder input" - default y - -choice - depends on STM32L4_QENCODER_FILTER - prompt "Input channel sampling frequency" - default STM32L4_QENCODER_SAMPLE_FDTS_4 - -config STM32L4_QENCODER_SAMPLE_FDTS - bool "fDTS" - -config STM32L4_QENCODER_SAMPLE_CKINT - bool "fCK_INT" - -config STM32L4_QENCODER_SAMPLE_FDTS_2 - bool "fDTS/2" - -config STM32L4_QENCODER_SAMPLE_FDTS_4 - bool "fDTS/4" - -config STM32L4_QENCODER_SAMPLE_FDTS_8 - bool "fDTS/8" - -config STM32L4_QENCODER_SAMPLE_FDTS_16 - bool "fDTS/16" - -config STM32L4_QENCODER_SAMPLE_FDTS_32 - bool "fDTS/32" - -endchoice - -choice - depends on STM32L4_QENCODER_FILTER - prompt "Input channel event count" - default STM32L4_QENCODER_SAMPLE_EVENT_6 - -config STM32L4_QENCODER_SAMPLE_EVENT_1 - depends on STM32L4_QENCODER_SAMPLE_FDTS - bool "1" - -config STM32L4_QENCODER_SAMPLE_EVENT_2 - depends on STM32L4_QENCODER_SAMPLE_CKINT - bool "2" - -config STM32L4_QENCODER_SAMPLE_EVENT_4 - depends on STM32L4_QENCODER_SAMPLE_CKINT - bool "4" - -config STM32L4_QENCODER_SAMPLE_EVENT_5 - depends on STM32L4_QENCODER_SAMPLE_FDTS_16 || STM32L4_QENCODER_SAMPLE_FDTS_32 - bool "5" - -config STM32L4_QENCODER_SAMPLE_EVENT_6 - depends on !STM32L4_QENCODER_SAMPLE_FDTS && !STM32L4_QENCODER_SAMPLE_CKINT - bool "6" - -config STM32L4_QENCODER_SAMPLE_EVENT_8 - depends on !STM32L4_QENCODER_SAMPLE_FDTS - bool "8" - -endchoice - -endmenu - -menu "SAI Configuration" - depends on STM32L4_SAI - -choice - prompt "Operation mode" - default STM32L4_SAI_DMA - ---help--- - Select the operation mode the SAI driver should use. - -config STM32L4_SAI_POLLING - bool "Polling" - ---help--- - The SAI registers are polled for events. - -config STM32L4_SAI_INTERRUPTS - bool "Interrupt" - ---help--- - Select to enable interrupt driven SAI support. - -config STM32L4_SAI_DMA - bool "DMA" - ---help--- - Use DMA to improve SAI transfer performance. - -endchoice # Operation mode - -choice - prompt "SAI1 synchronization enable" - default STM32L4_SAI1_BOTH_ASYNC - depends on STM32L4_SAI1_A && STM32L4_SAI1_B - ---help--- - Select the synchronization mode of the SAI sub-blocks - -config STM32L4_SAI1_BOTH_ASYNC - bool "Both asynchronous" - -config STM32L4_SAI1_A_SYNC_WITH_B - bool "Block A is synchronous with Block B" - -config STM32L4_SAI1_B_SYNC_WITH_A - bool "Block B is synchronous with Block A" - -endchoice # SAI1 synchronization enable - -choice - prompt "SAI2 synchronization enable" - default STM32L4_SAI2_BOTH_ASYNC - depends on STM32L4_SAI2_A && STM32L4_SAI2_B - ---help--- - Select the synchronization mode of the SAI sub-blocks - -config STM32L4_SAI2_BOTH_ASYNC - bool "Both asynchronous" - -config STM32L4_SAI2_A_SYNC_WITH_B - bool "Block A is synchronous with Block B" - -config STM32L4_SAI2_B_SYNC_WITH_A - bool "Block B is synchronous with Block A" - -endchoice # SAI2 synchronization enable - -endmenu - endif # ARCH_CHIP_STM32L4 diff --git a/arch/arm/src/stm32l4/Make.defs b/arch/arm/src/stm32l4/Make.defs index 3d981681ff023..8149af37b753f 100644 --- a/arch/arm/src/stm32l4/Make.defs +++ b/arch/arm/src/stm32l4/Make.defs @@ -26,12 +26,13 @@ # Common ARM and Cortex-M4 files (copied from stm32/Make.defs) include armv7-m/Make.defs +include common/stm32/Make.defs # Required STM32L4 files -CHIP_CSRCS = stm32l4_allocateheap.c stm32l4_exti_gpio.c stm32l4_gpio.c +CHIP_CSRCS += stm32l4_allocateheap.c stm32l4_exti_gpio.c stm32l4_gpio.c CHIP_CSRCS += stm32l4_irq.c stm32l4_lowputc.c stm32l4_rcc.c -CHIP_CSRCS += stm32l4_serial.c stm32l4_start.c stm32l4_waste.c stm32l4_uid.c +CHIP_CSRCS += stm32l4_serial.c stm32l4_start.c CHIP_CSRCS += stm32l4_spi.c stm32l4_i2c.c stm32l4_lse.c stm32l4_lsi.c CHIP_CSRCS += stm32l4_pwr.c stm32l4_tim.c stm32l4_flash.c CHIP_CSRCS += stm32l4_dfumode.c @@ -50,11 +51,11 @@ else CHIP_CSRCS += stm32l4_tickless.c endif -ifeq ($(CONFIG_STM32L4_ONESHOT),y) +ifeq ($(CONFIG_STM32_ONESHOT),y) CHIP_CSRCS += stm32l4_oneshot.c stm32l4_oneshot_lowerhalf.c endif -ifeq ($(CONFIG_STM32L4_FREERUN),y) +ifeq ($(CONFIG_STM32_FREERUN),y) CHIP_CSRCS += stm32l4_freerun.c endif @@ -62,37 +63,37 @@ ifeq ($(CONFIG_BUILD_PROTECTED),y) CHIP_CSRCS += stm32l4_userspace.c stm32l4_mpuinit.c endif -ifeq ($(CONFIG_STM32L4_HAVE_HSI48),y) +ifeq ($(CONFIG_STM32_HAVE_HSI48),y) CHIP_CSRCS += stm32l4_hsi48.c endif -ifeq ($(CONFIG_STM32L4_ADC),y) +ifeq ($(CONFIG_STM32_ADC),y) CHIP_CSRCS += stm32l4_adc.c endif -ifeq ($(CONFIG_STM32L4_DAC),y) +ifeq ($(CONFIG_STM32_DAC),y) CHIP_CSRCS += stm32l4_dac.c endif -ifeq ($(CONFIG_STM32L4_DFSDM),y) +ifeq ($(CONFIG_STM32_DFSDM),y) CHIP_CSRCS += stm32l4_dfsdm.c endif -ifeq ($(CONFIG_STM32L4_DMA),y) +ifeq ($(CONFIG_STM32_DMA),y) CHIP_CSRCS += stm32l4_dma.c endif ifeq ($(CONFIG_USBDEV),y) -ifeq ($(CONFIG_STM32L4_USBFS),y) +ifeq ($(CONFIG_STM32_USBFS),y) CHIP_CSRCS += stm32l4_usbdev.c endif -ifeq ($(CONFIG_STM32L4_OTGFS),y) +ifeq ($(CONFIG_STM32_OTGFS),y) CHIP_CSRCS += stm32l4_otgfsdev.c endif endif ifeq ($(CONFIG_USBHOST),y) -ifeq ($(CONFIG_STM32L4_OTGFS),y) +ifeq ($(CONFIG_STM32_OTGFS),y) CHIP_CSRCS += stm32l4_otgfshost.c endif endif @@ -116,11 +117,11 @@ CHIP_CSRCS += stm32l4_pminitialize.c endif endif -ifeq ($(CONFIG_STM32L4_PWR),y) +ifeq ($(CONFIG_STM32_PWR),y) CHIP_CSRCS += stm32l4_exti_pwr.c endif -ifeq ($(CONFIG_STM32L4_RTC),y) +ifeq ($(CONFIG_STM32_RTC),y) ifeq ($(CONFIG_RTC_ALARM),y) CHIP_CSRCS += stm32l4_exti_alarm.c endif @@ -137,27 +138,27 @@ ifeq ($(CONFIG_DEBUG_FEATURES),y) CHIP_CSRCS += stm32l4_dumpgpio.c endif -ifeq ($(CONFIG_STM32L4_COMP),y) +ifeq ($(CONFIG_STM32_COMP),y) CHIP_CSRCS += stm32l4_comp.c stm32l4_exti_comp.c endif -ifeq ($(CONFIG_STM32L4_RNG),y) +ifeq ($(CONFIG_STM32_RNG),y) CHIP_CSRCS += stm32l4_rng.c endif -ifeq ($(CONFIG_STM32L4_SAI),y) +ifeq ($(CONFIG_STM32_SAI),y) CHIP_CSRCS += stm32l4_sai.c endif -ifeq ($(CONFIG_STM32L4_LPTIM),y) +ifeq ($(CONFIG_STM32_LPTIM),y) CHIP_CSRCS += stm32l4_lptim.c endif -ifeq ($(CONFIG_STM32L4_PWM),y) +ifeq ($(CONFIG_STM32_PWM),y) CHIP_CSRCS += stm32l4_pwm.c endif -ifeq ($(CONFIG_STM32L4_PULSECOUNT),y) +ifeq ($(CONFIG_STM32_PULSECOUNT),y) CHIP_CSRCS += stm32l4_pulsecount.c endif @@ -165,26 +166,26 @@ ifeq ($(CONFIG_SENSORS_QENCODER),y) CHIP_CSRCS += stm32l4_qencoder.c endif -ifeq ($(CONFIG_STM32L4_QSPI),y) +ifeq ($(CONFIG_STM32_QSPI),y) CHIP_CSRCS += stm32l4_qspi.c endif -ifeq ($(CONFIG_STM32L4_CAN),y) +ifeq ($(CONFIG_STM32_CAN),y) CHIP_CSRCS += stm32l4_can.c endif -ifeq ($(CONFIG_STM32L4_FIREWALL),y) +ifeq ($(CONFIG_STM32_FIREWALL),y) CHIP_CSRCS += stm32l4_firewall.c endif -ifeq ($(CONFIG_STM32L4_IWDG),y) +ifeq ($(CONFIG_STM32_IWDG),y) CHIP_CSRCS += stm32l4_iwdg.c endif -ifeq ($(CONFIG_STM32L4_SDMMC1),y) +ifeq ($(CONFIG_STM32_SDMMC1),y) CHIP_CSRCS += stm32l4_sdmmc.c endif -ifeq ($(CONFIG_STM32L4_1WIREDRIVER),y) +ifeq ($(CONFIG_STM32_1WIREDRIVER),y) CHIP_CSRCS += stm32l4_1wire.c endif diff --git a/arch/arm/src/stm32l4/chip.h b/arch/arm/src/stm32l4/chip.h index fb3a0d2202743..b1b27fca0dc7c 100644 --- a/arch/arm/src/stm32l4/chip.h +++ b/arch/arm/src/stm32l4/chip.h @@ -49,7 +49,7 @@ * arch/stm32l4/chip.h header file. */ -#define ARMV7M_PERIPHERAL_INTERRUPTS STM32L4_IRQ_NEXTINTS +#define ARMV7M_PERIPHERAL_INTERRUPTS STM32_IRQ_NEXTINTS /* Cache line sizes (in bytes) for the STM32L4 */ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4_adc.h b/arch/arm/src/stm32l4/hardware/stm32l4_adc.h index c78b9f598df27..edd726b262648 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4_adc.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4_adc.h @@ -41,136 +41,136 @@ * offset 0x0100 for slave. */ -#define STM32L4_ADC_ISR_OFFSET 0x0000 /* ADC interrupt and status register */ -#define STM32L4_ADC_IER_OFFSET 0x0004 /* ADC interrupt enable register */ -#define STM32L4_ADC_CR_OFFSET 0x0008 /* ADC control register */ -#define STM32L4_ADC_CFGR_OFFSET 0x000c /* ADC configuration register */ -#define STM32L4_ADC_CFGR2_OFFSET 0x0010 /* ADC configuration register 2 */ -#define STM32L4_ADC_SMPR1_OFFSET 0x0014 /* ADC sample time register 1 */ -#define STM32L4_ADC_SMPR2_OFFSET 0x0018 /* ADC sample time register 2 */ -#define STM32L4_ADC_TR1_OFFSET 0x0020 /* ADC watchdog threshold register 1 */ -#define STM32L4_ADC_TR2_OFFSET 0x0024 /* ADC watchdog threshold register 2 */ -#define STM32L4_ADC_TR3_OFFSET 0x0028 /* ADC watchdog threshold register 3 */ -#define STM32L4_ADC_SQR1_OFFSET 0x0030 /* ADC regular sequence register 1 */ -#define STM32L4_ADC_SQR2_OFFSET 0x0034 /* ADC regular sequence register 2 */ -#define STM32L4_ADC_SQR3_OFFSET 0x0038 /* ADC regular sequence register 3 */ -#define STM32L4_ADC_SQR4_OFFSET 0x003c /* ADC regular sequence register 4 */ -#define STM32L4_ADC_DR_OFFSET 0x0040 /* ADC regular data register */ -#define STM32L4_ADC_JSQR_OFFSET 0x004c /* ADC injected sequence register */ -#define STM32L4_ADC_OFR1_OFFSET 0x0060 /* ADC offset register 1 */ -#define STM32L4_ADC_OFR2_OFFSET 0x0064 /* ADC offset register 2 */ -#define STM32L4_ADC_OFR3_OFFSET 0x0068 /* ADC offset register 3 */ -#define STM32L4_ADC_OFR4_OFFSET 0x006c /* ADC offset register 4 */ -#define STM32L4_ADC_JDR1_OFFSET 0x0080 /* ADC injected data register 1 */ -#define STM32L4_ADC_JDR2_OFFSET 0x0084 /* ADC injected data register 2 */ -#define STM32L4_ADC_JDR3_OFFSET 0x0088 /* ADC injected data register 3 */ -#define STM32L4_ADC_JDR4_OFFSET 0x008c /* ADC injected data register 4 */ -#define STM32L4_ADC_AWD2CR_OFFSET 0x00a0 /* ADC analog watchdog 2 configuration register */ -#define STM32L4_ADC_AWD3CR_OFFSET 0x00a4 /* ADC analog watchdog 3 configuration register */ -#define STM32L4_ADC_DIFSEL_OFFSET 0x00b0 /* ADC differential mode selection register 2 */ -#define STM32L4_ADC_CALFACT_OFFSET 0x00b4 /* ADC calibration factors */ +#define STM32_ADC_ISR_OFFSET 0x0000 /* ADC interrupt and status register */ +#define STM32_ADC_IER_OFFSET 0x0004 /* ADC interrupt enable register */ +#define STM32_ADC_CR_OFFSET 0x0008 /* ADC control register */ +#define STM32_ADC_CFGR_OFFSET 0x000c /* ADC configuration register */ +#define STM32_ADC_CFGR2_OFFSET 0x0010 /* ADC configuration register 2 */ +#define STM32_ADC_SMPR1_OFFSET 0x0014 /* ADC sample time register 1 */ +#define STM32_ADC_SMPR2_OFFSET 0x0018 /* ADC sample time register 2 */ +#define STM32_ADC_TR1_OFFSET 0x0020 /* ADC watchdog threshold register 1 */ +#define STM32_ADC_TR2_OFFSET 0x0024 /* ADC watchdog threshold register 2 */ +#define STM32_ADC_TR3_OFFSET 0x0028 /* ADC watchdog threshold register 3 */ +#define STM32_ADC_SQR1_OFFSET 0x0030 /* ADC regular sequence register 1 */ +#define STM32_ADC_SQR2_OFFSET 0x0034 /* ADC regular sequence register 2 */ +#define STM32_ADC_SQR3_OFFSET 0x0038 /* ADC regular sequence register 3 */ +#define STM32_ADC_SQR4_OFFSET 0x003c /* ADC regular sequence register 4 */ +#define STM32_ADC_DR_OFFSET 0x0040 /* ADC regular data register */ +#define STM32_ADC_JSQR_OFFSET 0x004c /* ADC injected sequence register */ +#define STM32_ADC_OFR1_OFFSET 0x0060 /* ADC offset register 1 */ +#define STM32_ADC_OFR2_OFFSET 0x0064 /* ADC offset register 2 */ +#define STM32_ADC_OFR3_OFFSET 0x0068 /* ADC offset register 3 */ +#define STM32_ADC_OFR4_OFFSET 0x006c /* ADC offset register 4 */ +#define STM32_ADC_JDR1_OFFSET 0x0080 /* ADC injected data register 1 */ +#define STM32_ADC_JDR2_OFFSET 0x0084 /* ADC injected data register 2 */ +#define STM32_ADC_JDR3_OFFSET 0x0088 /* ADC injected data register 3 */ +#define STM32_ADC_JDR4_OFFSET 0x008c /* ADC injected data register 4 */ +#define STM32_ADC_AWD2CR_OFFSET 0x00a0 /* ADC analog watchdog 2 configuration register */ +#define STM32_ADC_AWD3CR_OFFSET 0x00a4 /* ADC analog watchdog 3 configuration register */ +#define STM32_ADC_DIFSEL_OFFSET 0x00b0 /* ADC differential mode selection register 2 */ +#define STM32_ADC_CALFACT_OFFSET 0x00b4 /* ADC calibration factors */ /* Master and Slave ADC Common Registers */ -#define STM32L4_ADC_CSR_OFFSET 0x0000 /* Common status register */ -#define STM32L4_ADC_CCR_OFFSET 0x0008 /* Common control register */ -#ifndef CONFIG_STM32L4_STM32L4X3 -# define STM32L4_ADC_CDR_OFFSET 0x000c /* Common regular data register for dual mode */ +#define STM32_ADC_CSR_OFFSET 0x0000 /* Common status register */ +#define STM32_ADC_CCR_OFFSET 0x0008 /* Common control register */ +#ifndef CONFIG_STM32_STM32L4X3 +# define STM32_ADC_CDR_OFFSET 0x000c /* Common regular data register for dual mode */ #endif /* Register Addresses *******************************************************/ -#define STM32L4_ADC1_ISR (STM32L4_ADC1_BASE+STM32L4_ADC_ISR_OFFSET) -#define STM32L4_ADC1_IER (STM32L4_ADC1_BASE+STM32L4_ADC_IER_OFFSET) -#define STM32L4_ADC1_CR (STM32L4_ADC1_BASE+STM32L4_ADC_CR_OFFSET) -#define STM32L4_ADC1_CFGR (STM32L4_ADC1_BASE+STM32L4_ADC_CFGR_OFFSET) -#define STM32L4_ADC1_CFGR2 (STM32L4_ADC1_BASE+STM32L4_ADC_CFGR2_OFFSET) -#define STM32L4_ADC1_SMPR1 (STM32L4_ADC1_BASE+STM32L4_ADC_SMPR1_OFFSET) -#define STM32L4_ADC1_SMPR2 (STM32L4_ADC1_BASE+STM32L4_ADC_SMPR2_OFFSET) -#define STM32L4_ADC1_TR1 (STM32L4_ADC1_BASE+STM32L4_ADC_TR1_OFFSET) -#define STM32L4_ADC1_TR2 (STM32L4_ADC1_BASE+STM32L4_ADC_TR2_OFFSET) -#define STM32L4_ADC1_TR3 (STM32L4_ADC1_BASE+STM32L4_ADC_TR3_OFFSET) -#define STM32L4_ADC1_SQR1 (STM32L4_ADC1_BASE+STM32L4_ADC_SQR1_OFFSET) -#define STM32L4_ADC1_SQR2 (STM32L4_ADC1_BASE+STM32L4_ADC_SQR2_OFFSET) -#define STM32L4_ADC1_SQR3 (STM32L4_ADC1_BASE+STM32L4_ADC_SQR3_OFFSET) -#define STM32L4_ADC1_SQR4 (STM32L4_ADC1_BASE+STM32L4_ADC_SQR4_OFFSET) -#define STM32L4_ADC1_DR (STM32L4_ADC1_BASE+STM32L4_ADC_DR_OFFSET) -#define STM32L4_ADC1_JSQR (STM32L4_ADC1_BASE+STM32L4_ADC_JSQR_OFFSET) -#define STM32L4_ADC1_OFR1 (STM32L4_ADC1_BASE+STM32L4_ADC_OFR1_OFFSET) -#define STM32L4_ADC1_OFR2 (STM32L4_ADC1_BASE+STM32L4_ADC_OFR2_OFFSET) -#define STM32L4_ADC1_OFR3 (STM32L4_ADC1_BASE+STM32L4_ADC_OFR3_OFFSET) -#define STM32L4_ADC1_OFR4 (STM32L4_ADC1_BASE+STM32L4_ADC_OFR4_OFFSET) -#define STM32L4_ADC1_JDR1 (STM32L4_ADC1_BASE+STM32L4_ADC_JDR1_OFFSET) -#define STM32L4_ADC1_JDR2 (STM32L4_ADC1_BASE+STM32L4_ADC_JDR2_OFFSET) -#define STM32L4_ADC1_JDR3 (STM32L4_ADC1_BASE+STM32L4_ADC_JDR3_OFFSET) -#define STM32L4_ADC1_JDR4 (STM32L4_ADC1_BASE+STM32L4_ADC_JDR4_OFFSET) -#define STM32L4_ADC1_AWD2CR (STM32L4_ADC1_BASE+STM32L4_ADC_AWD2CR_OFFSET) -#define STM32L4_ADC1_AWD3CR (STM32L4_ADC1_BASE+STM32L4_ADC_AWD3CR_OFFSET) -#define STM32L4_ADC1_DIFSEL (STM32L4_ADC1_BASE+STM32L4_ADC_DIFSEL_OFFSET) -#define STM32L4_ADC1_CALFACT (STM32L4_ADC1_BASE+STM32L4_ADC_CALFACT_OFFSET) - -#define STM32L4_ADC2_ISR (STM32L4_ADC2_BASE+STM32L4_ADC_ISR_OFFSET) -#define STM32L4_ADC2_IER (STM32L4_ADC2_BASE+STM32L4_ADC_IER_OFFSET) -#define STM32L4_ADC2_CR (STM32L4_ADC2_BASE+STM32L4_ADC_CR_OFFSET) -#define STM32L4_ADC2_CFGR (STM32L4_ADC2_BASE+STM32L4_ADC_CFGR_OFFSET) -#define STM32L4_ADC2_CFGR2 (STM32L4_ADC2_BASE+STM32L4_ADC_CFGR2_OFFSET) -#define STM32L4_ADC2_SMPR1 (STM32L4_ADC2_BASE+STM32L4_ADC_SMPR1_OFFSET) -#define STM32L4_ADC2_SMPR2 (STM32L4_ADC2_BASE+STM32L4_ADC_SMPR2_OFFSET) -#define STM32L4_ADC2_TR1 (STM32L4_ADC2_BASE+STM32L4_ADC_TR1_OFFSET) -#define STM32L4_ADC2_TR2 (STM32L4_ADC2_BASE+STM32L4_ADC_TR2_OFFSET) -#define STM32L4_ADC2_TR3 (STM32L4_ADC2_BASE+STM32L4_ADC_TR3_OFFSET) -#define STM32L4_ADC2_SQR1 (STM32L4_ADC2_BASE+STM32L4_ADC_SQR1_OFFSET) -#define STM32L4_ADC2_SQR2 (STM32L4_ADC2_BASE+STM32L4_ADC_SQR2_OFFSET) -#define STM32L4_ADC2_SQR3 (STM32L4_ADC2_BASE+STM32L4_ADC_SQR3_OFFSET) -#define STM32L4_ADC2_SQR4 (STM32L4_ADC2_BASE+STM32L4_ADC_SQR4_OFFSET) -#define STM32L4_ADC2_DR (STM32L4_ADC2_BASE+STM32L4_ADC_DR_OFFSET) -#define STM32L4_ADC2_JSQR (STM32L4_ADC2_BASE+STM32L4_ADC_JSQR_OFFSET) -#define STM32L4_ADC2_OFR1 (STM32L4_ADC2_BASE+STM32L4_ADC_OFR1_OFFSET) -#define STM32L4_ADC2_OFR2 (STM32L4_ADC2_BASE+STM32L4_ADC_OFR2_OFFSET) -#define STM32L4_ADC2_OFR3 (STM32L4_ADC2_BASE+STM32L4_ADC_OFR3_OFFSET) -#define STM32L4_ADC2_OFR4 (STM32L4_ADC2_BASE+STM32L4_ADC_OFR4_OFFSET) -#define STM32L4_ADC2_JDR1 (STM32L4_ADC2_BASE+STM32L4_ADC_JDR1_OFFSET) -#define STM32L4_ADC2_JDR2 (STM32L4_ADC2_BASE+STM32L4_ADC_JDR2_OFFSET) -#define STM32L4_ADC2_JDR3 (STM32L4_ADC2_BASE+STM32L4_ADC_JDR3_OFFSET) -#define STM32L4_ADC2_JDR4 (STM32L4_ADC2_BASE+STM32L4_ADC_JDR4_OFFSET) -#define STM32L4_ADC2_AWD2CR (STM32L4_ADC2_BASE+STM32L4_ADC_AWD2CR_OFFSET) -#define STM32L4_ADC2_AWD3CR (STM32L4_ADC2_BASE+STM32L4_ADC_AWD3CR_OFFSET) -#define STM32L4_ADC2_DIFSEL (STM32L4_ADC2_BASE+STM32L4_ADC_DIFSEL_OFFSET) -#define STM32L4_ADC2_CALFACT (STM32L4_ADC2_BASE+STM32L4_ADC_CALFACT_OFFSET) - -#define STM32L4_ADC3_ISR (STM32L4_ADC3_BASE+STM32L4_ADC_ISR_OFFSET) -#define STM32L4_ADC3_IER (STM32L4_ADC3_BASE+STM32L4_ADC_IER_OFFSET) -#define STM32L4_ADC3_CR (STM32L4_ADC3_BASE+STM32L4_ADC_CR_OFFSET) -#define STM32L4_ADC3_CFGR (STM32L4_ADC3_BASE+STM32L4_ADC_CFGR_OFFSET) -#define STM32L4_ADC3_CFGR2 (STM32L4_ADC3_BASE+STM32L4_ADC_CFGR2_OFFSET) -#define STM32L4_ADC3_SMPR1 (STM32L4_ADC3_BASE+STM32L4_ADC_SMPR1_OFFSET) -#define STM32L4_ADC3_SMPR2 (STM32L4_ADC3_BASE+STM32L4_ADC_SMPR2_OFFSET) -#define STM32L4_ADC3_TR1 (STM32L4_ADC3_BASE+STM32L4_ADC_TR1_OFFSET) -#define STM32L4_ADC3_TR2 (STM32L4_ADC3_BASE+STM32L4_ADC_TR2_OFFSET) -#define STM32L4_ADC3_TR3 (STM32L4_ADC3_BASE+STM32L4_ADC_TR3_OFFSET) -#define STM32L4_ADC3_SQR1 (STM32L4_ADC3_BASE+STM32L4_ADC_SQR1_OFFSET) -#define STM32L4_ADC3_SQR2 (STM32L4_ADC3_BASE+STM32L4_ADC_SQR2_OFFSET) -#define STM32L4_ADC3_SQR3 (STM32L4_ADC3_BASE+STM32L4_ADC_SQR3_OFFSET) -#define STM32L4_ADC3_SQR4 (STM32L4_ADC3_BASE+STM32L4_ADC_SQR4_OFFSET) -#define STM32L4_ADC3_DR (STM32L4_ADC3_BASE+STM32L4_ADC_DR_OFFSET) -#define STM32L4_ADC3_JSQR (STM32L4_ADC3_BASE+STM32L4_ADC_JSQR_OFFSET) -#define STM32L4_ADC3_OFR1 (STM32L4_ADC3_BASE+STM32L4_ADC_OFR1_OFFSET) -#define STM32L4_ADC3_OFR2 (STM32L4_ADC3_BASE+STM32L4_ADC_OFR2_OFFSET) -#define STM32L4_ADC3_OFR3 (STM32L4_ADC3_BASE+STM32L4_ADC_OFR3_OFFSET) -#define STM32L4_ADC3_OFR4 (STM32L4_ADC3_BASE+STM32L4_ADC_OFR4_OFFSET) -#define STM32L4_ADC3_JDR1 (STM32L4_ADC3_BASE+STM32L4_ADC_JDR1_OFFSET) -#define STM32L4_ADC3_JDR2 (STM32L4_ADC3_BASE+STM32L4_ADC_JDR2_OFFSET) -#define STM32L4_ADC3_JDR3 (STM32L4_ADC3_BASE+STM32L4_ADC_JDR3_OFFSET) -#define STM32L4_ADC3_JDR4 (STM32L4_ADC3_BASE+STM32L4_ADC_JDR4_OFFSET) -#define STM32L4_ADC3_AWD2CR (STM32L4_ADC3_BASE+STM32L4_ADC_AWD2CR_OFFSET) -#define STM32L4_ADC3_AWD3CR (STM32L4_ADC3_BASE+STM32L4_ADC_AWD3CR_OFFSET) -#define STM32L4_ADC3_DIFSEL (STM32L4_ADC3_BASE+STM32L4_ADC_DIFSEL_OFFSET) -#define STM32L4_ADC3_CALFACT (STM32L4_ADC3_BASE+STM32L4_ADC_CALFACT_OFFSET) - -#define STM32L4_ADC_CSR (STM32L4_ADCCMN_BASE+STM32L4_ADC_CSR_OFFSET) -#define STM32L4_ADC_CCR (STM32L4_ADCCMN_BASE+STM32L4_ADC_CCR_OFFSET) -#ifndef CONFIG_STM32L4_STM32L4X3 -# define STM32L4_ADC_CDR (STM32L4_ADCCMN_BASE+STM32L4_ADC_CDR_OFFSET) +#define STM32_ADC1_ISR (STM32_ADC1_BASE+STM32_ADC_ISR_OFFSET) +#define STM32_ADC1_IER (STM32_ADC1_BASE+STM32_ADC_IER_OFFSET) +#define STM32_ADC1_CR (STM32_ADC1_BASE+STM32_ADC_CR_OFFSET) +#define STM32_ADC1_CFGR (STM32_ADC1_BASE+STM32_ADC_CFGR_OFFSET) +#define STM32_ADC1_CFGR2 (STM32_ADC1_BASE+STM32_ADC_CFGR2_OFFSET) +#define STM32_ADC1_SMPR1 (STM32_ADC1_BASE+STM32_ADC_SMPR1_OFFSET) +#define STM32_ADC1_SMPR2 (STM32_ADC1_BASE+STM32_ADC_SMPR2_OFFSET) +#define STM32_ADC1_TR1 (STM32_ADC1_BASE+STM32_ADC_TR1_OFFSET) +#define STM32_ADC1_TR2 (STM32_ADC1_BASE+STM32_ADC_TR2_OFFSET) +#define STM32_ADC1_TR3 (STM32_ADC1_BASE+STM32_ADC_TR3_OFFSET) +#define STM32_ADC1_SQR1 (STM32_ADC1_BASE+STM32_ADC_SQR1_OFFSET) +#define STM32_ADC1_SQR2 (STM32_ADC1_BASE+STM32_ADC_SQR2_OFFSET) +#define STM32_ADC1_SQR3 (STM32_ADC1_BASE+STM32_ADC_SQR3_OFFSET) +#define STM32_ADC1_SQR4 (STM32_ADC1_BASE+STM32_ADC_SQR4_OFFSET) +#define STM32_ADC1_DR (STM32_ADC1_BASE+STM32_ADC_DR_OFFSET) +#define STM32_ADC1_JSQR (STM32_ADC1_BASE+STM32_ADC_JSQR_OFFSET) +#define STM32_ADC1_OFR1 (STM32_ADC1_BASE+STM32_ADC_OFR1_OFFSET) +#define STM32_ADC1_OFR2 (STM32_ADC1_BASE+STM32_ADC_OFR2_OFFSET) +#define STM32_ADC1_OFR3 (STM32_ADC1_BASE+STM32_ADC_OFR3_OFFSET) +#define STM32_ADC1_OFR4 (STM32_ADC1_BASE+STM32_ADC_OFR4_OFFSET) +#define STM32_ADC1_JDR1 (STM32_ADC1_BASE+STM32_ADC_JDR1_OFFSET) +#define STM32_ADC1_JDR2 (STM32_ADC1_BASE+STM32_ADC_JDR2_OFFSET) +#define STM32_ADC1_JDR3 (STM32_ADC1_BASE+STM32_ADC_JDR3_OFFSET) +#define STM32_ADC1_JDR4 (STM32_ADC1_BASE+STM32_ADC_JDR4_OFFSET) +#define STM32_ADC1_AWD2CR (STM32_ADC1_BASE+STM32_ADC_AWD2CR_OFFSET) +#define STM32_ADC1_AWD3CR (STM32_ADC1_BASE+STM32_ADC_AWD3CR_OFFSET) +#define STM32_ADC1_DIFSEL (STM32_ADC1_BASE+STM32_ADC_DIFSEL_OFFSET) +#define STM32_ADC1_CALFACT (STM32_ADC1_BASE+STM32_ADC_CALFACT_OFFSET) + +#define STM32_ADC2_ISR (STM32_ADC2_BASE+STM32_ADC_ISR_OFFSET) +#define STM32_ADC2_IER (STM32_ADC2_BASE+STM32_ADC_IER_OFFSET) +#define STM32_ADC2_CR (STM32_ADC2_BASE+STM32_ADC_CR_OFFSET) +#define STM32_ADC2_CFGR (STM32_ADC2_BASE+STM32_ADC_CFGR_OFFSET) +#define STM32_ADC2_CFGR2 (STM32_ADC2_BASE+STM32_ADC_CFGR2_OFFSET) +#define STM32_ADC2_SMPR1 (STM32_ADC2_BASE+STM32_ADC_SMPR1_OFFSET) +#define STM32_ADC2_SMPR2 (STM32_ADC2_BASE+STM32_ADC_SMPR2_OFFSET) +#define STM32_ADC2_TR1 (STM32_ADC2_BASE+STM32_ADC_TR1_OFFSET) +#define STM32_ADC2_TR2 (STM32_ADC2_BASE+STM32_ADC_TR2_OFFSET) +#define STM32_ADC2_TR3 (STM32_ADC2_BASE+STM32_ADC_TR3_OFFSET) +#define STM32_ADC2_SQR1 (STM32_ADC2_BASE+STM32_ADC_SQR1_OFFSET) +#define STM32_ADC2_SQR2 (STM32_ADC2_BASE+STM32_ADC_SQR2_OFFSET) +#define STM32_ADC2_SQR3 (STM32_ADC2_BASE+STM32_ADC_SQR3_OFFSET) +#define STM32_ADC2_SQR4 (STM32_ADC2_BASE+STM32_ADC_SQR4_OFFSET) +#define STM32_ADC2_DR (STM32_ADC2_BASE+STM32_ADC_DR_OFFSET) +#define STM32_ADC2_JSQR (STM32_ADC2_BASE+STM32_ADC_JSQR_OFFSET) +#define STM32_ADC2_OFR1 (STM32_ADC2_BASE+STM32_ADC_OFR1_OFFSET) +#define STM32_ADC2_OFR2 (STM32_ADC2_BASE+STM32_ADC_OFR2_OFFSET) +#define STM32_ADC2_OFR3 (STM32_ADC2_BASE+STM32_ADC_OFR3_OFFSET) +#define STM32_ADC2_OFR4 (STM32_ADC2_BASE+STM32_ADC_OFR4_OFFSET) +#define STM32_ADC2_JDR1 (STM32_ADC2_BASE+STM32_ADC_JDR1_OFFSET) +#define STM32_ADC2_JDR2 (STM32_ADC2_BASE+STM32_ADC_JDR2_OFFSET) +#define STM32_ADC2_JDR3 (STM32_ADC2_BASE+STM32_ADC_JDR3_OFFSET) +#define STM32_ADC2_JDR4 (STM32_ADC2_BASE+STM32_ADC_JDR4_OFFSET) +#define STM32_ADC2_AWD2CR (STM32_ADC2_BASE+STM32_ADC_AWD2CR_OFFSET) +#define STM32_ADC2_AWD3CR (STM32_ADC2_BASE+STM32_ADC_AWD3CR_OFFSET) +#define STM32_ADC2_DIFSEL (STM32_ADC2_BASE+STM32_ADC_DIFSEL_OFFSET) +#define STM32_ADC2_CALFACT (STM32_ADC2_BASE+STM32_ADC_CALFACT_OFFSET) + +#define STM32_ADC3_ISR (STM32_ADC3_BASE+STM32_ADC_ISR_OFFSET) +#define STM32_ADC3_IER (STM32_ADC3_BASE+STM32_ADC_IER_OFFSET) +#define STM32_ADC3_CR (STM32_ADC3_BASE+STM32_ADC_CR_OFFSET) +#define STM32_ADC3_CFGR (STM32_ADC3_BASE+STM32_ADC_CFGR_OFFSET) +#define STM32_ADC3_CFGR2 (STM32_ADC3_BASE+STM32_ADC_CFGR2_OFFSET) +#define STM32_ADC3_SMPR1 (STM32_ADC3_BASE+STM32_ADC_SMPR1_OFFSET) +#define STM32_ADC3_SMPR2 (STM32_ADC3_BASE+STM32_ADC_SMPR2_OFFSET) +#define STM32_ADC3_TR1 (STM32_ADC3_BASE+STM32_ADC_TR1_OFFSET) +#define STM32_ADC3_TR2 (STM32_ADC3_BASE+STM32_ADC_TR2_OFFSET) +#define STM32_ADC3_TR3 (STM32_ADC3_BASE+STM32_ADC_TR3_OFFSET) +#define STM32_ADC3_SQR1 (STM32_ADC3_BASE+STM32_ADC_SQR1_OFFSET) +#define STM32_ADC3_SQR2 (STM32_ADC3_BASE+STM32_ADC_SQR2_OFFSET) +#define STM32_ADC3_SQR3 (STM32_ADC3_BASE+STM32_ADC_SQR3_OFFSET) +#define STM32_ADC3_SQR4 (STM32_ADC3_BASE+STM32_ADC_SQR4_OFFSET) +#define STM32_ADC3_DR (STM32_ADC3_BASE+STM32_ADC_DR_OFFSET) +#define STM32_ADC3_JSQR (STM32_ADC3_BASE+STM32_ADC_JSQR_OFFSET) +#define STM32_ADC3_OFR1 (STM32_ADC3_BASE+STM32_ADC_OFR1_OFFSET) +#define STM32_ADC3_OFR2 (STM32_ADC3_BASE+STM32_ADC_OFR2_OFFSET) +#define STM32_ADC3_OFR3 (STM32_ADC3_BASE+STM32_ADC_OFR3_OFFSET) +#define STM32_ADC3_OFR4 (STM32_ADC3_BASE+STM32_ADC_OFR4_OFFSET) +#define STM32_ADC3_JDR1 (STM32_ADC3_BASE+STM32_ADC_JDR1_OFFSET) +#define STM32_ADC3_JDR2 (STM32_ADC3_BASE+STM32_ADC_JDR2_OFFSET) +#define STM32_ADC3_JDR3 (STM32_ADC3_BASE+STM32_ADC_JDR3_OFFSET) +#define STM32_ADC3_JDR4 (STM32_ADC3_BASE+STM32_ADC_JDR4_OFFSET) +#define STM32_ADC3_AWD2CR (STM32_ADC3_BASE+STM32_ADC_AWD2CR_OFFSET) +#define STM32_ADC3_AWD3CR (STM32_ADC3_BASE+STM32_ADC_AWD3CR_OFFSET) +#define STM32_ADC3_DIFSEL (STM32_ADC3_BASE+STM32_ADC_DIFSEL_OFFSET) +#define STM32_ADC3_CALFACT (STM32_ADC3_BASE+STM32_ADC_CALFACT_OFFSET) + +#define STM32_ADC_CSR (STM32_ADCCMN_BASE+STM32_ADC_CSR_OFFSET) +#define STM32_ADC_CCR (STM32_ADCCMN_BASE+STM32_ADC_CCR_OFFSET) +#ifndef CONFIG_STM32_STM32L4X3 +# define STM32_ADC_CDR (STM32_ADCCMN_BASE+STM32_ADC_CDR_OFFSET) #endif /* Register Bitfield Definitions ********************************************/ @@ -226,23 +226,23 @@ # define ADC_CFGR_EXTSEL_T1CC3 (0x02 << ADC_CFGR_EXTSEL_SHIFT) /* 0010: Timer 1 CC3 event */ # define ADC_CFGR_EXTSEL_T2CC4 (0x03 << ADC_CFGR_EXTSEL_SHIFT) /* 0011: Timer 2 CC4 event */ # define ADC_CFGR_EXTSEL_T3TRGO (0x04 << ADC_CFGR_EXTSEL_SHIFT) /* 0100: Timer 3 TRGO event */ -# if !defined(CONFIG_STM32L4_STM32L4X3) +# if !defined(CONFIG_STM32_STM32L4X3) # define ADC_CFGR_EXTSEL_T4CC4 (0x05 << ADC_CFGR_EXTSEL_SHIFT) /* 0101: Timer 4 CC4 event */ # endif # define ADC_CFGR_EXTSEL_EXTI11 (0x06 << ADC_CFGR_EXTSEL_SHIFT) /* 0110: EXTI line 11 */ -# if !defined(CONFIG_STM32L4_STM32L4X3) +# if !defined(CONFIG_STM32_STM32L4X3) # define ADC_CFGR_EXTSEL_T8TRGO (0x07 << ADC_CFGR_EXTSEL_SHIFT) /* 0111: Timer 8 TRGO event */ # define ADC_CFGR_EXTSEL_T8TRGO2 (0x08 << ADC_CFGR_EXTSEL_SHIFT) /* 1000: Timer 8 TRGO2 event */ # endif # define ADC_CFGR_EXTSEL_T1TRGO (0x09 << ADC_CFGR_EXTSEL_SHIFT) /* 1001: Timer 1 TRGO event */ # define ADC_CFGR_EXTSEL_T1TRGO2 (0x0a << ADC_CFGR_EXTSEL_SHIFT) /* 1010: Timer 1 TRGO2 event */ # define ADC_CFGR_EXTSEL_T2TRGO (0x0b << ADC_CFGR_EXTSEL_SHIFT) /* 1011: Timer 2 TRGO event */ -# if !defined(CONFIG_STM32L4_STM32L4X3) +# if !defined(CONFIG_STM32_STM32L4X3) # define ADC_CFGR_EXTSEL_T4TRGO (0x0c << ADC_CFGR_EXTSEL_SHIFT) /* 1100: Timer 4 TRGO event */ # endif # define ADC_CFGR_EXTSEL_T6TRGO (0x0d << ADC_CFGR_EXTSEL_SHIFT) /* 1101: Timer 6 TRGO event */ # define ADC_CFGR_EXTSEL_T15TRGO (0x0e << ADC_CFGR_EXTSEL_SHIFT) /* 1110: Timer 15 TRGO event */ -# if !defined(CONFIG_STM32L4_STM32L4X3) +# if !defined(CONFIG_STM32_STM32L4X3) # define ADC_CFGR_EXTSEL_T3CC4 (0x0f << ADC_CFGR_EXTSEL_SHIFT) /* 1111: Timer 3 CC4 event */ # endif #define ADC_CFGR_EXTEN_SHIFT (10) /* Bits 10-11: External trigger/polarity selection regular channels */ @@ -286,10 +286,12 @@ # define ADC_CFGR2_OVSR_64X (5 << ADC_CFGR2_OVSR_SHIFT) /* 64X oversampling */ # define ADC_CFGR2_OVSR_128X (6 << ADC_CFGR2_OVSR_SHIFT) /* 128X oversampling */ # define ADC_CFGR2_OVSR_256X (7 << ADC_CFGR2_OVSR_SHIFT) /* 256X oversampling */ + #define ADC_CFGR2_OVSS_SHIFT (5) /* Bits 5-8: Oversampling shift */ #define ADC_CFGR2_OVSS_MASK (0xf << ADC_CFGR2_OVSS_SHIFT) # define ADC_CFGR2_OVSS(value) ((value) << ADC_CFGR2_OVSS_SHIFT) - /* Value = 0..8 */ + /* Value = 0..8 */ + #define ADC_CFGR2_TROVS (1 << 9) /* Bit 9: Triggered Regular Oversampling */ #define ADC_CFGR2_ROVSM (1 << 10) /* Bit 10: Regular Oversampling mode */ @@ -539,7 +541,7 @@ #define ADC_CSR_AWD3_MST (1 << 9) /* Bit 9: Analog watchdog 3 flag (master ADC) */ #define ADC_CSR_JQOVF_MST (1 << 10) /* Bit 10: Injected Context Queue Overflow flag (master ADC) */ -#ifndef CONFIG_STM32L4_STM32L4X3 +#ifndef CONFIG_STM32_STM32L4X3 # define ADC_CSR_ADRDY_SLV (1 << 16) /* Bit 16: Slave ADC ready */ # define ADC_CSR_EOSMP_SLV (1 << 17) /* Bit 17: End of Sampling phase flag (slave ADC) */ # define ADC_CSR_EOC_SLV (1 << 18) /* Bit 18: End of regular conversion (slave ADC) */ @@ -555,7 +557,7 @@ /* Common control register */ -#ifndef CONFIG_STM32L4_STM32L4X3 +#ifndef CONFIG_STM32_STM32L4X3 # define ADC_CCR_DUAL_SHIFT (0) /* Bits 0-4: Dual ADC mode selection */ # define ADC_CCR_DUAL_MASK (31 << ADC_CCR_DUAL_SHIFT) # define ADC_CCR_DUAL_IND (0 << ADC_CCR_DUAL_SHIFT) /* Independent mode */ @@ -603,7 +605,7 @@ /* Common regular data register for dual mode */ -#ifndef CONFIG_STM32L4_STM32L4X3 +#ifndef CONFIG_STM32_STM32L4X3 # define ADC_CDR_RDATA_MST_SHIFT (0) /* Bits 0-15: Regular data of the master ADC */ # define ADC_CDR_RDATA_MST_MASK (0xffff << ADC_CDR_RDATA_MST_SHIFT) # define ADC_CDR_RDATA_SLV_SHIFT (16) /* Bits 16-31: Regular data of the slave ADC */ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4_can.h b/arch/arm/src/stm32l4/hardware/stm32l4_can.h index ac0338cd867f9..b79de2c9eaf0b 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4_can.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4_can.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_CAN_H -#define __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_CAN_H +#ifndef __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32_CAN_H +#define __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32_CAN_H /**************************************************************************** * Included Files @@ -54,61 +54,61 @@ /* CAN control and status registers */ -#define STM32L4_CAN_MCR_OFFSET 0x0000 /* CAN master control register */ -#define STM32L4_CAN_MSR_OFFSET 0x0004 /* CAN master status register */ -#define STM32L4_CAN_TSR_OFFSET 0x0008 /* CAN transmit status register */ -#define STM32L4_CAN_RFR_OFFSET(m) (0x000c + ((m) << 2)) -#define STM32L4_CAN_RF0R_OFFSET 0x000c /* CAN receive FIFO 0 register */ -#define STM32L4_CAN_RF1R_OFFSET 0x0010 /* CAN receive FIFO 1 register */ -#define STM32L4_CAN_IER_OFFSET 0x0014 /* CAN interrupt enable register */ -#define STM32L4_CAN_ESR_OFFSET 0x0018 /* CAN error status register */ -#define STM32L4_CAN_BTR_OFFSET 0x001c /* CAN bit timing register */ +#define STM32_CAN_MCR_OFFSET 0x0000 /* CAN master control register */ +#define STM32_CAN_MSR_OFFSET 0x0004 /* CAN master status register */ +#define STM32_CAN_TSR_OFFSET 0x0008 /* CAN transmit status register */ +#define STM32_CAN_RFR_OFFSET(m) (0x000c + ((m) << 2)) +#define STM32_CAN_RF0R_OFFSET 0x000c /* CAN receive FIFO 0 register */ +#define STM32_CAN_RF1R_OFFSET 0x0010 /* CAN receive FIFO 1 register */ +#define STM32_CAN_IER_OFFSET 0x0014 /* CAN interrupt enable register */ +#define STM32_CAN_ESR_OFFSET 0x0018 /* CAN error status register */ +#define STM32_CAN_BTR_OFFSET 0x001c /* CAN bit timing register */ /* CAN mailbox registers (3 TX and 2 RX) */ -#define STM32L4_CAN_TIR_OFFSET(m) (0x0180 + ((m) << 4)) -#define STM32L4_CAN_TI0R_OFFSET 0x0180 /* TX mailbox identifier register 0 */ -#define STM32L4_CAN_TI1R_OFFSET 0x0190 /* TX mailbox identifier register 1 */ -#define STM32L4_CAN_TI2R_OFFSET 0x01a0 /* TX mailbox identifier register 2 */ +#define STM32_CAN_TIR_OFFSET(m) (0x0180 + ((m) << 4)) +#define STM32_CAN_TI0R_OFFSET 0x0180 /* TX mailbox identifier register 0 */ +#define STM32_CAN_TI1R_OFFSET 0x0190 /* TX mailbox identifier register 1 */ +#define STM32_CAN_TI2R_OFFSET 0x01a0 /* TX mailbox identifier register 2 */ -#define STM32L4_CAN_TDTR_OFFSET(m) (0x0184 + ((m) << 4)) -#define STM32L4_CAN_TDT0R_OFFSET 0x0184 /* Mailbox data length control and time stamp register 0 */ -#define STM32L4_CAN_TDT1R_OFFSET 0x0194 /* Mailbox data length control and time stamp register 1 */ -#define STM32L4_CAN_TDT2R_OFFSET 0x01a4 /* Mailbox data length control and time stamp register 2 */ +#define STM32_CAN_TDTR_OFFSET(m) (0x0184 + ((m) << 4)) +#define STM32_CAN_TDT0R_OFFSET 0x0184 /* Mailbox data length control and time stamp register 0 */ +#define STM32_CAN_TDT1R_OFFSET 0x0194 /* Mailbox data length control and time stamp register 1 */ +#define STM32_CAN_TDT2R_OFFSET 0x01a4 /* Mailbox data length control and time stamp register 2 */ -#define STM32L4_CAN_TDLR_OFFSET(m) (0x0188 + ((m) << 4)) -#define STM32L4_CAN_TDL0R_OFFSET 0x0188 /* Mailbox data low register 0 */ -#define STM32L4_CAN_TDL1R_OFFSET 0x0198 /* Mailbox data low register 1 */ -#define STM32L4_CAN_TDL2R_OFFSET 0x01a8 /* Mailbox data low register 2 */ +#define STM32_CAN_TDLR_OFFSET(m) (0x0188 + ((m) << 4)) +#define STM32_CAN_TDL0R_OFFSET 0x0188 /* Mailbox data low register 0 */ +#define STM32_CAN_TDL1R_OFFSET 0x0198 /* Mailbox data low register 1 */ +#define STM32_CAN_TDL2R_OFFSET 0x01a8 /* Mailbox data low register 2 */ -#define STM32L4_CAN_TDHR_OFFSET(m) (0x018c + ((m) << 4)) -#define STM32L4_CAN_TDH0R_OFFSET 0x018c /* Mailbox data high register 0 */ -#define STM32L4_CAN_TDH1R_OFFSET 0x019c /* Mailbox data high register 1 */ -#define STM32L4_CAN_TDH2R_OFFSET 0x01ac /* Mailbox data high register 2 */ +#define STM32_CAN_TDHR_OFFSET(m) (0x018c + ((m) << 4)) +#define STM32_CAN_TDH0R_OFFSET 0x018c /* Mailbox data high register 0 */ +#define STM32_CAN_TDH1R_OFFSET 0x019c /* Mailbox data high register 1 */ +#define STM32_CAN_TDH2R_OFFSET 0x01ac /* Mailbox data high register 2 */ -#define STM32L4_CAN_RIR_OFFSET(m) (0x01b0 + ((m) << 4)) -#define STM32L4_CAN_RI0R_OFFSET 0x01b0 /* Rx FIFO mailbox identifier register 0 */ -#define STM32L4_CAN_RI1R_OFFSET 0x01c0 /* Rx FIFO mailbox identifier register 1 */ +#define STM32_CAN_RIR_OFFSET(m) (0x01b0 + ((m) << 4)) +#define STM32_CAN_RI0R_OFFSET 0x01b0 /* Rx FIFO mailbox identifier register 0 */ +#define STM32_CAN_RI1R_OFFSET 0x01c0 /* Rx FIFO mailbox identifier register 1 */ -#define STM32L4_CAN_RDTR_OFFSET(m) (0x01b4 + ((m) << 4)) -#define STM32L4_CAN_RDT0R_OFFSET 0x01b4 /* Rx FIFO mailbox data length control and time stamp register 0 */ -#define STM32L4_CAN_RDT1R_OFFSET 0x01c4 /* Rx FIFO mailbox data length control and time stamp register 1 */ +#define STM32_CAN_RDTR_OFFSET(m) (0x01b4 + ((m) << 4)) +#define STM32_CAN_RDT0R_OFFSET 0x01b4 /* Rx FIFO mailbox data length control and time stamp register 0 */ +#define STM32_CAN_RDT1R_OFFSET 0x01c4 /* Rx FIFO mailbox data length control and time stamp register 1 */ -#define STM32L4_CAN_RDLR_OFFSET(m) (0x01b8 + ((m) << 4)) -#define STM32L4_CAN_RDL0R_OFFSET 0x01b8 /* Receive FIFO mailbox data low register 0 */ -#define STM32L4_CAN_RDL1R_OFFSET 0x01c8 /* Receive FIFO mailbox data low register 1 */ +#define STM32_CAN_RDLR_OFFSET(m) (0x01b8 + ((m) << 4)) +#define STM32_CAN_RDL0R_OFFSET 0x01b8 /* Receive FIFO mailbox data low register 0 */ +#define STM32_CAN_RDL1R_OFFSET 0x01c8 /* Receive FIFO mailbox data low register 1 */ -#define STM32L4_CAN_RDHR_OFFSET(m) (0x01bc + ((m) << 4)) -#define STM32L4_CAN_RDH0R_OFFSET 0x01bc /* Receive FIFO mailbox data high register 0 */ -#define STM32L4_CAN_RDH1R_OFFSET 0x01cc /* Receive FIFO mailbox data high register 1 */ +#define STM32_CAN_RDHR_OFFSET(m) (0x01bc + ((m) << 4)) +#define STM32_CAN_RDH0R_OFFSET 0x01bc /* Receive FIFO mailbox data high register 0 */ +#define STM32_CAN_RDH1R_OFFSET 0x01cc /* Receive FIFO mailbox data high register 1 */ /* CAN filter registers */ -#define STM32L4_CAN_FMR_OFFSET 0x0200 /* CAN filter master register */ -#define STM32L4_CAN_FM1R_OFFSET 0x0204 /* CAN filter mode register */ -#define STM32L4_CAN_FS1R_OFFSET 0x020c /* CAN filter scale register */ -#define STM32L4_CAN_FFA1R_OFFSET 0x0214 /* CAN filter FIFO assignment register */ -#define STM32L4_CAN_FA1R_OFFSET 0x021c /* CAN filter activation register */ +#define STM32_CAN_FMR_OFFSET 0x0200 /* CAN filter master register */ +#define STM32_CAN_FM1R_OFFSET 0x0204 /* CAN filter mode register */ +#define STM32_CAN_FS1R_OFFSET 0x020c /* CAN filter scale register */ +#define STM32_CAN_FFA1R_OFFSET 0x0214 /* CAN filter FIFO assignment register */ +#define STM32_CAN_FA1R_OFFSET 0x021c /* CAN filter activation register */ /* There are 14 filter banks on the device. Each filter bank is * composed of two 32-bit registers, CAN_FiR: @@ -119,63 +119,63 @@ * ... */ -#define STM32L4_CAN_FIR_OFFSET(f,i) (0x240+((f)<<3)+(((i)-1)<<2)) +#define STM32_CAN_FIR_OFFSET(f,i) (0x240+((f)<<3)+(((i)-1)<<2)) /* Register Addresses *******************************************************/ -#if STM32L4_NCAN > 0 -# define STM32L4_CAN1_MCR (STM32L4_CAN1_BASE+STM32L4_CAN_MCR_OFFSET) -# define STM32L4_CAN1_MSR (STM32L4_CAN1_BASE+STM32L4_CAN_MSR_OFFSET) -# define STM32L4_CAN1_TSR (STM32L4_CAN1_BASE+STM32L4_CAN_TSR_OFFSET) -# define STM32L4_CAN1_RFR(m) (STM32L4_CAN1_BASE+STM32L4_CAN_RFR_OFFSET(m)) -# define STM32L4_CAN1_RF0R (STM32L4_CAN1_BASE+STM32L4_CAN_RF0R_OFFSET) -# define STM32L4_CAN1_RF1R (STM32L4_CAN1_BASE+STM32L4_CAN_RF1R_OFFSET) -# define STM32L4_CAN1_IER (STM32L4_CAN1_BASE+STM32L4_CAN_IER_OFFSET) -# define STM32L4_CAN1_ESR (STM32L4_CAN1_BASE+STM32L4_CAN_ESR_OFFSET) -# define STM32L4_CAN1_BTR (STM32L4_CAN1_BASE+STM32L4_CAN_BTR_OFFSET) - -# define STM32L4_CAN1_TIR(m) (STM32L4_CAN1_BASE+STM32L4_CAN_TIR_OFFSET(m)) -# define STM32L4_CAN1_TI0R (STM32L4_CAN1_BASE+STM32L4_CAN_TI0R_OFFSET) -# define STM32L4_CAN1_TI1R (STM32L4_CAN1_BASE+STM32L4_CAN_TI1R_OFFSET) -# define STM32L4_CAN1_TI2R (STM32L4_CAN1_BASE+STM32L4_CAN_TI2R_OFFSET) - -# define STM32L4_CAN1_TDTR(m) (STM32L4_CAN1_BASE+STM32L4_CAN_TDTR_OFFSET(m)) -# define STM32L4_CAN1_TDT0R (STM32L4_CAN1_BASE+STM32L4_CAN_TDT0R_OFFSET) -# define STM32L4_CAN1_TDT1R (STM32L4_CAN1_BASE+STM32L4_CAN_TDT1R_OFFSET) -# define STM32L4_CAN1_TDT2R (STM32L4_CAN1_BASE+STM32L4_CAN_TDT2R_OFFSET) - -# define STM32L4_CAN1_TDLR(m) (STM32L4_CAN1_BASE+STM32L4_CAN_TDLR_OFFSET(m)) -# define STM32L4_CAN1_TDL0R (STM32L4_CAN1_BASE+STM32L4_CAN_TDL0R_OFFSET) -# define STM32L4_CAN1_TDL1R (STM32L4_CAN1_BASE+STM32L4_CAN_TDL1R_OFFSET) -# define STM32L4_CAN1_TDL2R (STM32L4_CAN1_BASE+STM32L4_CAN_TDL2R_OFFSET) - -# define STM32L4_CAN1_TDHR(m) (STM32L4_CAN1_BASE+STM32L4_CAN_TDHR_OFFSET(m)) -# define STM32L4_CAN1_TDH0R (STM32L4_CAN1_BASE+STM32L4_CAN_TDH0R_OFFSET) -# define STM32L4_CAN1_TDH1R (STM32L4_CAN1_BASE+STM32L4_CAN_TDH1R_OFFSET) -# define STM32L4_CAN1_TDH2R (STM32L4_CAN1_BASE+STM32L4_CAN_TDH2R_OFFSET) - -# define STM32L4_CAN1_RIR(m) (STM32L4_CAN1_BASE+STM32L4_CAN_RIR_OFFSET(m)) -# define STM32L4_CAN1_RI0R (STM32L4_CAN1_BASE+STM32L4_CAN_RI0R_OFFSET) -# define STM32L4_CAN1_RI1R (STM32L4_CAN1_BASE+STM32L4_CAN_RI1R_OFFSET) - -# define STM32L4_CAN1_RDTR(m) (STM32L4_CAN1_BASE+STM32L4_CAN_RDTR_OFFSET(m)) -# define STM32L4_CAN1_RDT0R (STM32L4_CAN1_BASE+STM32L4_CAN_RDT0R_OFFSET) -# define STM32L4_CAN1_RDT1R (STM32L4_CAN1_BASE+STM32L4_CAN_RDT1R_OFFSET) - -# define STM32L4_CAN1_RDLR(m) (STM32L4_CAN1_BASE+STM32L4_CAN_RDLR_OFFSET(m)) -# define STM32L4_CAN1_RDL0R (STM32L4_CAN1_BASE+STM32L4_CAN_RDL0R_OFFSET) -# define STM32L4_CAN1_RDL1R (STM32L4_CAN1_BASE+STM32L4_CAN_RDL1R_OFFSET) - -# define STM32L4_CAN1_RDHR(m) (STM32L4_CAN1_BASE+STM32L4_CAN_RDHR_OFFSET(m)) -# define STM32L4_CAN1_RDH0R (STM32L4_CAN1_BASE+STM32L4_CAN_RDH0R_OFFSET) -# define STM32L4_CAN1_RDH1R (STM32L4_CAN1_BASE+STM32L4_CAN_RDH1R_OFFSET) - -# define STM32L4_CAN1_FMR (STM32L4_CAN1_BASE+STM32L4_CAN_FMR_OFFSET) -# define STM32L4_CAN1_FM1R (STM32L4_CAN1_BASE+STM32L4_CAN_FM1R_OFFSET) -# define STM32L4_CAN1_FS1R (STM32L4_CAN1_BASE+STM32L4_CAN_FS1R_OFFSET) -# define STM32L4_CAN1_FFA1R (STM32L4_CAN1_BASE+STM32L4_CAN_FFA1R_OFFSET) -# define STM32L4_CAN1_FA1R (STM32L4_CAN1_BASE+STM32L4_CAN_FA1R_OFFSET) -# define STM32L4_CAN1_FIR(b,i) (STM32L4_CAN1_BASE+STM32L4_CAN_FIR_OFFSET(b,i)) +#if STM32_NCAN > 0 +# define STM32_CAN1_MCR (STM32_CAN1_BASE+STM32_CAN_MCR_OFFSET) +# define STM32_CAN1_MSR (STM32_CAN1_BASE+STM32_CAN_MSR_OFFSET) +# define STM32_CAN1_TSR (STM32_CAN1_BASE+STM32_CAN_TSR_OFFSET) +# define STM32_CAN1_RFR(m) (STM32_CAN1_BASE+STM32_CAN_RFR_OFFSET(m)) +# define STM32_CAN1_RF0R (STM32_CAN1_BASE+STM32_CAN_RF0R_OFFSET) +# define STM32_CAN1_RF1R (STM32_CAN1_BASE+STM32_CAN_RF1R_OFFSET) +# define STM32_CAN1_IER (STM32_CAN1_BASE+STM32_CAN_IER_OFFSET) +# define STM32_CAN1_ESR (STM32_CAN1_BASE+STM32_CAN_ESR_OFFSET) +# define STM32_CAN1_BTR (STM32_CAN1_BASE+STM32_CAN_BTR_OFFSET) + +# define STM32_CAN1_TIR(m) (STM32_CAN1_BASE+STM32_CAN_TIR_OFFSET(m)) +# define STM32_CAN1_TI0R (STM32_CAN1_BASE+STM32_CAN_TI0R_OFFSET) +# define STM32_CAN1_TI1R (STM32_CAN1_BASE+STM32_CAN_TI1R_OFFSET) +# define STM32_CAN1_TI2R (STM32_CAN1_BASE+STM32_CAN_TI2R_OFFSET) + +# define STM32_CAN1_TDTR(m) (STM32_CAN1_BASE+STM32_CAN_TDTR_OFFSET(m)) +# define STM32_CAN1_TDT0R (STM32_CAN1_BASE+STM32_CAN_TDT0R_OFFSET) +# define STM32_CAN1_TDT1R (STM32_CAN1_BASE+STM32_CAN_TDT1R_OFFSET) +# define STM32_CAN1_TDT2R (STM32_CAN1_BASE+STM32_CAN_TDT2R_OFFSET) + +# define STM32_CAN1_TDLR(m) (STM32_CAN1_BASE+STM32_CAN_TDLR_OFFSET(m)) +# define STM32_CAN1_TDL0R (STM32_CAN1_BASE+STM32_CAN_TDL0R_OFFSET) +# define STM32_CAN1_TDL1R (STM32_CAN1_BASE+STM32_CAN_TDL1R_OFFSET) +# define STM32_CAN1_TDL2R (STM32_CAN1_BASE+STM32_CAN_TDL2R_OFFSET) + +# define STM32_CAN1_TDHR(m) (STM32_CAN1_BASE+STM32_CAN_TDHR_OFFSET(m)) +# define STM32_CAN1_TDH0R (STM32_CAN1_BASE+STM32_CAN_TDH0R_OFFSET) +# define STM32_CAN1_TDH1R (STM32_CAN1_BASE+STM32_CAN_TDH1R_OFFSET) +# define STM32_CAN1_TDH2R (STM32_CAN1_BASE+STM32_CAN_TDH2R_OFFSET) + +# define STM32_CAN1_RIR(m) (STM32_CAN1_BASE+STM32_CAN_RIR_OFFSET(m)) +# define STM32_CAN1_RI0R (STM32_CAN1_BASE+STM32_CAN_RI0R_OFFSET) +# define STM32_CAN1_RI1R (STM32_CAN1_BASE+STM32_CAN_RI1R_OFFSET) + +# define STM32_CAN1_RDTR(m) (STM32_CAN1_BASE+STM32_CAN_RDTR_OFFSET(m)) +# define STM32_CAN1_RDT0R (STM32_CAN1_BASE+STM32_CAN_RDT0R_OFFSET) +# define STM32_CAN1_RDT1R (STM32_CAN1_BASE+STM32_CAN_RDT1R_OFFSET) + +# define STM32_CAN1_RDLR(m) (STM32_CAN1_BASE+STM32_CAN_RDLR_OFFSET(m)) +# define STM32_CAN1_RDL0R (STM32_CAN1_BASE+STM32_CAN_RDL0R_OFFSET) +# define STM32_CAN1_RDL1R (STM32_CAN1_BASE+STM32_CAN_RDL1R_OFFSET) + +# define STM32_CAN1_RDHR(m) (STM32_CAN1_BASE+STM32_CAN_RDHR_OFFSET(m)) +# define STM32_CAN1_RDH0R (STM32_CAN1_BASE+STM32_CAN_RDH0R_OFFSET) +# define STM32_CAN1_RDH1R (STM32_CAN1_BASE+STM32_CAN_RDH1R_OFFSET) + +# define STM32_CAN1_FMR (STM32_CAN1_BASE+STM32_CAN_FMR_OFFSET) +# define STM32_CAN1_FM1R (STM32_CAN1_BASE+STM32_CAN_FM1R_OFFSET) +# define STM32_CAN1_FS1R (STM32_CAN1_BASE+STM32_CAN_FS1R_OFFSET) +# define STM32_CAN1_FFA1R (STM32_CAN1_BASE+STM32_CAN_FFA1R_OFFSET) +# define STM32_CAN1_FA1R (STM32_CAN1_BASE+STM32_CAN_FA1R_OFFSET) +# define STM32_CAN1_FIR(b,i) (STM32_CAN1_BASE+STM32_CAN_FIR_OFFSET(b,i)) #endif /* Register Bitfield Definitions ********************************************/ @@ -410,4 +410,4 @@ * Public Functions Prototypes ****************************************************************************/ -#endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_CAN_H */ +#endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32_CAN_H */ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4_comp.h b/arch/arm/src/stm32l4/hardware/stm32l4_comp.h index 4c9694ab78d14..f626c0dfb5ef4 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4_comp.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4_comp.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_COMP_H -#define __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_COMP_H +#ifndef __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32_COMP_H +#define __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32_COMP_H /**************************************************************************** * Pre-processor Definitions @@ -29,15 +29,15 @@ /* Register Offsets *********************************************************/ -#define STM32L4_COMP_CSR_OFFSET(n) (((n)-1) << 2) -#define STM32L4_COMP1_CSR_OFFSET 0x0000 /* Comparator 1 control and status register */ -#define STM32L4_COMP2_CSR_OFFSET 0x0004 /* Comparator 2 control and status register */ +#define STM32_COMP_CSR_OFFSET(n) (((n)-1) << 2) +#define STM32_COMP1_CSR_OFFSET 0x0000 /* Comparator 1 control and status register */ +#define STM32_COMP2_CSR_OFFSET 0x0004 /* Comparator 2 control and status register */ /* Register Addresses *******************************************************/ -#define STM32L4_COMP_CSR(n) (STM32L4_COMP_BASE+STM32L4_COMP_CSR_OFFSET(n)) -#define STM32L4_COMP1_CSR (STM32L4_COMP_BASE+STM32L4_COMP1_CSR_OFFSET) -#define STM32L4_COMP2_CSR (STM32L4_COMP_BASE+STM32L4_COMP2_CSR_OFFSET) +#define STM32_COMP_CSR(n) (STM32_COMP_BASE+STM32_COMP_CSR_OFFSET(n)) +#define STM32_COMP1_CSR (STM32_COMP_BASE+STM32_COMP1_CSR_OFFSET) +#define STM32_COMP2_CSR (STM32_COMP_BASE+STM32_COMP2_CSR_OFFSET) /* Register Bitfield Definitions ********************************************/ @@ -58,7 +58,7 @@ # define COMP_CSR_INMSEL_DAC1 (4 << COMP_CSR_INMSEL_SHIFT) /* DAC Channel1 */ # define COMP_CSR_INMSEL_DAC2 (5 << COMP_CSR_INMSEL_SHIFT) /* DAC Channel2 */ # define COMP_CSR_INMSEL_PIN1 (6 << COMP_CSR_INMSEL_SHIFT) /* Input minus pin 1: COMP1=PB1; COMP2=PB3 */ -#if defined(CONFIG_STM32L4_STM32L4X3) +#if defined(CONFIG_STM32_STM32L4X3) # define COMP_CSR_INMSEL_INMESEL (7 << COMP_CSR_INMSEL_SHIFT) /* Input minus pin 2: Selected by INMESEL */ #else # define COMP_CSR_INMSEL_PIN2 (7 << COMP_CSR_INMSEL_SHIFT) /* Input minus pin 2: COMP1=PC4; COMP2=PB7 */ @@ -68,7 +68,7 @@ #define COMP_CSR_INPSEL_MASK (3 << COMP_CSR_INPSEL_SHIFT) # define COMP_CSR_INPSEL_PIN1 (0 << COMP_CSR_INPSEL_SHIFT) /* Input plus pin 1: COMP1=PC5; COMP2=PB4 */ # define COMP_CSR_INPSEL_PIN2 (1 << COMP_CSR_INPSEL_SHIFT) /* Input plus pin 2: COMP1=PB2; COMP2=PB6 */ -#if defined(CONFIG_STM32L4_STM32L4X3) +#if defined(CONFIG_STM32_STM32L4X3) # define COMP_CSR_INPSEL_PIN3 (2 << COMP_CSR_INPSEL_SHIFT) /* Input plus pin 3: COMP1=PA1; COMP2=PA3 */ #endif @@ -101,7 +101,7 @@ #define COMP_CSR_BRGEN (1 << 22) /* Bit 22: Scaler bridge enable */ #define COMP_CSR_SCALEN (1 << 23) /* Bit 23: Voltage scaler enable bit */ /* Bit 24: Reserved */ -#if defined(CONFIG_STM32L4_STM32L4X3) +#if defined(CONFIG_STM32_STM32L4X3) # define COMP_CSR_INMESEL_SHIFT (25) /* Bits 25-26: Input minus extended selection bits */ # define COMP_CSR_INMESEL_MASK (3 << COMP_CSR_INMESEL_SHIFT) # define COMP_CSR_INMESEL_PIN2 (0 << COMP_CSR_INMESEL_SHIFT) /* Input minus pin 2: COMP1=PC4; COMP2=PB7 */ @@ -109,10 +109,12 @@ # define COMP_CSR_INMESEL_PIN4 (2 << COMP_CSR_INMESEL_SHIFT) /* Input minus pin 4: COMP1=PA4; COMP2=PA4 */ # define COMP_CSR_INMESEL_PIN5 (3 << COMP_CSR_INMESEL_SHIFT) /* Input minus pin 5: COMP1=PA5; COMP2=PA5 */ #endif - /* Bits 27-29: Reserved */ + +/* Bits 27-29: Reserved */ + #define COMP_CSR_VALUE (1 << 30) /* Bit 30: Comparator output status bit */ #define COMP_CSR_LOCK_MASK (1 << 31) /* Bit 31: CSR register lock bit */ # define COMP_CSR_LOCK_RW (0) # define COMP_CSR_LOCK_RO COMP_CSR_LOCK_MASK -#endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_COMP_H */ +#endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32_COMP_H */ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4_crs.h b/arch/arm/src/stm32l4/hardware/stm32l4_crs.h index 5ff70d77eaabc..38a33c17a4a7b 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4_crs.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4_crs.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_CRS_H -#define __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_CRS_H +#ifndef __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32_CRS_H +#define __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32_CRS_H /**************************************************************************** * Pre-processor Definitions @@ -29,17 +29,17 @@ /* Register Offsets *********************************************************/ -#define STM32L4_CRS_CR_OFFSET 0x0000 /* CRS control register */ -#define STM32L4_CRS_CFGR_OFFSET 0x0004 /* CRS configuration register */ -#define STM32L4_CRS_ISR_OFFSET 0x0008 /* CRS interrupt and status register */ -#define STM32L4_CRS_ICR_OFFSET 0x000c /* CRS interrupt flag clear register */ +#define STM32_CRS_CR_OFFSET 0x0000 /* CRS control register */ +#define STM32_CRS_CFGR_OFFSET 0x0004 /* CRS configuration register */ +#define STM32_CRS_ISR_OFFSET 0x0008 /* CRS interrupt and status register */ +#define STM32_CRS_ICR_OFFSET 0x000c /* CRS interrupt flag clear register */ /* Register Addresses *******************************************************/ -#define STM32L4_CRS_CR (STM32L4_CRS_BASE + STM32L4_CRS_CR_OFFSET) -#define STM32L4_CRS_CFGR (STM32L4_CRS_BASE + STM32L4_CRS_CFGR_OFFSET) -#define STM32L4_CRS_ISR (STM32L4_CRS_BASE + STM32L4_CRS_ISR_OFFSET) -#define STM32L4_CRS_ICR (STM32L4_CRS_BASE + STM32L4_CRS_ICR_OFFSET) +#define STM32_CRS_CR (STM32_CRS_BASE + STM32_CRS_CR_OFFSET) +#define STM32_CRS_CFGR (STM32_CRS_BASE + STM32_CRS_CFGR_OFFSET) +#define STM32_CRS_ISR (STM32_CRS_BASE + STM32_CRS_ISR_OFFSET) +#define STM32_CRS_ICR (STM32_CRS_BASE + STM32_CRS_ICR_OFFSET) /* Register Bitfield Definitions ********************************************/ @@ -100,4 +100,4 @@ #define CRS_ICR_ERRC (1 << 2) /* Bit 2: Error clear flag */ #define CRS_ICR_ESYNCC (1 << 3) /* Bit 3: Expected SYNC clear flag */ -#endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_CRS_H */ +#endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32_CRS_H */ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4_dac.h b/arch/arm/src/stm32l4/hardware/stm32l4_dac.h index d8d613212dae1..02030bcd91ae2 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4_dac.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4_dac.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_DAC_H -#define __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_DAC_H +#ifndef __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32_DAC_H +#define __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32_DAC_H /**************************************************************************** * Included Files @@ -36,51 +36,51 @@ /* Register Offsets *********************************************************/ -#define STM32L4_DAC_CR_OFFSET 0x0000 /* DAC control register */ -#define STM32L4_DAC_SWTRIGR_OFFSET 0x0004 /* DAC software trigger register */ -#define STM32L4_DAC_DHR12R1_OFFSET 0x0008 /* DAC channel 1 12-bit right-aligned data holding register */ -#define STM32L4_DAC_DHR12L1_OFFSET 0x000c /* DAC channel 1 12-bit left aligned data holding register */ -#define STM32L4_DAC_DHR8R1_OFFSET 0x0010 /* DAC channel 1 8-bit right aligned data holding register */ -#define STM32L4_DAC_DHR12R2_OFFSET 0x0014 /* DAC channel 2 12-bit right aligned data holding register */ -#define STM32L4_DAC_DHR12L2_OFFSET 0x0018 /* DAC channel 2 12-bit left aligned data holding register */ -#define STM32L4_DAC_DHR8R2_OFFSET 0x001c /* DAC channel 2 8-bit right-aligned data holding register */ -#define STM32L4_DAC_DHR12RD_OFFSET 0x0020 /* Dual DAC 12-bit right-aligned data holding register */ -#define STM32L4_DAC_DHR12LD_OFFSET 0x0024 /* DUAL DAC 12-bit left aligned data holding register */ -#define STM32L4_DAC_DHR8RD_OFFSET 0x0028 /* DUAL DAC 8-bit right aligned data holding register */ -#define STM32L4_DAC_DOR1_OFFSET 0x002c /* DAC channel 1 data output register */ -#define STM32L4_DAC_DOR2_OFFSET 0x0030 /* DAC channel 2 data output register */ -#define STM32L4_DAC_SR_OFFSET 0x0034 /* DAC status register */ +#define STM32_DAC_CR_OFFSET 0x0000 /* DAC control register */ +#define STM32_DAC_SWTRIGR_OFFSET 0x0004 /* DAC software trigger register */ +#define STM32_DAC_DHR12R1_OFFSET 0x0008 /* DAC channel 1 12-bit right-aligned data holding register */ +#define STM32_DAC_DHR12L1_OFFSET 0x000c /* DAC channel 1 12-bit left aligned data holding register */ +#define STM32_DAC_DHR8R1_OFFSET 0x0010 /* DAC channel 1 8-bit right aligned data holding register */ +#define STM32_DAC_DHR12R2_OFFSET 0x0014 /* DAC channel 2 12-bit right aligned data holding register */ +#define STM32_DAC_DHR12L2_OFFSET 0x0018 /* DAC channel 2 12-bit left aligned data holding register */ +#define STM32_DAC_DHR8R2_OFFSET 0x001c /* DAC channel 2 8-bit right-aligned data holding register */ +#define STM32_DAC_DHR12RD_OFFSET 0x0020 /* Dual DAC 12-bit right-aligned data holding register */ +#define STM32_DAC_DHR12LD_OFFSET 0x0024 /* DUAL DAC 12-bit left aligned data holding register */ +#define STM32_DAC_DHR8RD_OFFSET 0x0028 /* DUAL DAC 8-bit right aligned data holding register */ +#define STM32_DAC_DOR1_OFFSET 0x002c /* DAC channel 1 data output register */ +#define STM32_DAC_DOR2_OFFSET 0x0030 /* DAC channel 2 data output register */ +#define STM32_DAC_SR_OFFSET 0x0034 /* DAC status register */ /* New registers not in STM32L1: */ -#define STM32L4_DAC_CCR_OFFSET 0x0038 /* DAC calibration control register */ -#define STM32L4_DAC_MCR_OFFSET 0x003c /* DAC mode control register */ -#define STM32L4_DAC_SHSR1_OFFSET 0x0040 /* DAC Sample and Hold sample time register 1 */ -#define STM32L4_DAC_SHSR2_OFFSET 0x0044 /* DAC Sample and Hold sample time register 2 */ -#define STM32L4_DAC_SHHR_OFFSET 0x0048 /* DAC Sample and Hold hold time register */ -#define STM32L4_DAC_SHRR_OFFSET 0x004c /* DAC Sample and Hold refresh time register */ +#define STM32_DAC_CCR_OFFSET 0x0038 /* DAC calibration control register */ +#define STM32_DAC_MCR_OFFSET 0x003c /* DAC mode control register */ +#define STM32_DAC_SHSR1_OFFSET 0x0040 /* DAC Sample and Hold sample time register 1 */ +#define STM32_DAC_SHSR2_OFFSET 0x0044 /* DAC Sample and Hold sample time register 2 */ +#define STM32_DAC_SHHR_OFFSET 0x0048 /* DAC Sample and Hold hold time register */ +#define STM32_DAC_SHRR_OFFSET 0x004c /* DAC Sample and Hold refresh time register */ /* Register Addresses *******************************************************/ -#define STM32L4_DAC_CR (STM32L4_DAC_BASE+STM32L4_DAC_CR_OFFSET) -#define STM32L4_DAC_SWTRIGR (STM32L4_DAC_BASE+STM32L4_DAC_SWTRIGR_OFFSET) -#define STM32L4_DAC_DHR12R1 (STM32L4_DAC_BASE+STM32L4_DAC_DHR12R1_OFFSET) -#define STM32L4_DAC_DHR12L1 (STM32L4_DAC_BASE+STM32L4_DAC_DHR12L1_OFFSET) -#define STM32L4_DAC_DHR8R1 (STM32L4_DAC_BASE+STM32L4_DAC_DHR8R1_OFFSET) -#define STM32L4_DAC_DHR12R2 (STM32L4_DAC_BASE+STM32L4_DAC_DHR12R2_OFFSET) -#define STM32L4_DAC_DHR12L2 (STM32L4_DAC_BASE+STM32L4_DAC_DHR12L2_OFFSET) -#define STM32L4_DAC_DHR8R2 (STM32L4_DAC_BASE+STM32L4_DAC_DHR8R2_OFFSET) -#define STM32L4_DAC_DHR12RD (STM32L4_DAC_BASE+STM32L4_DAC_DHR12RD_OFFSET) -#define STM32L4_DAC_DHR12LD (STM32L4_DAC_BASE+STM32L4_DAC_DHR12LD_OFFSET) -#define STM32L4_DAC_DHR8RD (STM32L4_DAC_BASE+STM32L4_DAC_DHR8RD_OFFSET) -#define STM32L4_DAC_DOR1 (STM32L4_DAC_BASE+STM32L4_DAC_DOR1_OFFSET) -#define STM32L4_DAC_DOR2 (STM32L4_DAC_BASE+STM32L4_DAC_DOR2_OFFSET) -#define STM32L4_DAC_SR (STM32L4_DAC_BASE+STM32L4_DAC_SR_OFFSET) -#define STM32L4_DAC_CCR (STM32L4_DAC_BASE+STM32L4_DAC_CCR_OFFSET) -#define STM32L4_DAC_MCR (STM32L4_DAC_BASE+STM32L4_DAC_MCR_OFFSET) -#define STM32L4_DAC_SHSR1 (STM32L4_DAC_BASE+STM32L4_DAC_SHSR1_OFFSET) -#define STM32L4_DAC_SHSR2 (STM32L4_DAC_BASE+STM32L4_DAC_SHSR2_OFFSET) -#define STM32L4_DAC_SHHR (STM32L4_DAC_BASE+STM32L4_DAC_SHHR_OFFSET) -#define STM32L4_DAC_SHRR (STM32L4_DAC_BASE+STM32L4_DAC_SHRR_OFFSET) +#define STM32_DAC_CR (STM32_DAC_BASE+STM32_DAC_CR_OFFSET) +#define STM32_DAC_SWTRIGR (STM32_DAC_BASE+STM32_DAC_SWTRIGR_OFFSET) +#define STM32_DAC_DHR12R1 (STM32_DAC_BASE+STM32_DAC_DHR12R1_OFFSET) +#define STM32_DAC_DHR12L1 (STM32_DAC_BASE+STM32_DAC_DHR12L1_OFFSET) +#define STM32_DAC_DHR8R1 (STM32_DAC_BASE+STM32_DAC_DHR8R1_OFFSET) +#define STM32_DAC_DHR12R2 (STM32_DAC_BASE+STM32_DAC_DHR12R2_OFFSET) +#define STM32_DAC_DHR12L2 (STM32_DAC_BASE+STM32_DAC_DHR12L2_OFFSET) +#define STM32_DAC_DHR8R2 (STM32_DAC_BASE+STM32_DAC_DHR8R2_OFFSET) +#define STM32_DAC_DHR12RD (STM32_DAC_BASE+STM32_DAC_DHR12RD_OFFSET) +#define STM32_DAC_DHR12LD (STM32_DAC_BASE+STM32_DAC_DHR12LD_OFFSET) +#define STM32_DAC_DHR8RD (STM32_DAC_BASE+STM32_DAC_DHR8RD_OFFSET) +#define STM32_DAC_DOR1 (STM32_DAC_BASE+STM32_DAC_DOR1_OFFSET) +#define STM32_DAC_DOR2 (STM32_DAC_BASE+STM32_DAC_DOR2_OFFSET) +#define STM32_DAC_SR (STM32_DAC_BASE+STM32_DAC_SR_OFFSET) +#define STM32_DAC_CCR (STM32_DAC_BASE+STM32_DAC_CCR_OFFSET) +#define STM32_DAC_MCR (STM32_DAC_BASE+STM32_DAC_MCR_OFFSET) +#define STM32_DAC_SHSR1 (STM32_DAC_BASE+STM32_DAC_SHSR1_OFFSET) +#define STM32_DAC_SHSR2 (STM32_DAC_BASE+STM32_DAC_SHSR2_OFFSET) +#define STM32_DAC_SHHR (STM32_DAC_BASE+STM32_DAC_SHHR_OFFSET) +#define STM32_DAC_SHRR (STM32_DAC_BASE+STM32_DAC_SHRR_OFFSET) /* Register Bitfield Definitions ********************************************/ @@ -336,4 +336,4 @@ #define DAC_SHRR_TREFRESH2_SHIFT (16) /* Bits 16-23: DAC channel 2 refresh time */ #define DAC_SHRR_TREFRESH2_MASK (0xff << DAC_SHRR_TREFRESH2_SHIFT) -#endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_DAC_H */ +#endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32_DAC_H */ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4_dfsdm.h b/arch/arm/src/stm32l4/hardware/stm32l4_dfsdm.h index 85546d55bc89a..e64073321a201 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4_dfsdm.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4_dfsdm.h @@ -41,134 +41,134 @@ /* DFSDM channel y registers (y=0..7 or y=0..3 on STM32L4X3) */ -#define STM32L4_DFSDM_CHCFGR1_OFFSET(y) (0x00 + 0x20 * (y)) - -#define STM32L4_DFSDM_CH0CFGR1_OFFSET 0x0000 /* DFSDM channel configuration 0 register */ -#define STM32L4_DFSDM_CH1CFGR1_OFFSET 0x0020 /* DFSDM channel configuration 1 register */ -#define STM32L4_DFSDM_CH2CFGR1_OFFSET 0x0040 /* DFSDM channel configuration 2 register */ -#define STM32L4_DFSDM_CH3CFGR1_OFFSET 0x0060 /* DFSDM channel configuration 3 register */ -#ifndef CONFIG_STM32L4_STM32L4X3 -# define STM32L4_DFSDM_CH4CFGR1_OFFSET 0x0080 /* DFSDM channel configuration 4 register */ -# define STM32L4_DFSDM_CH5CFGR1_OFFSET 0x00a0 /* DFSDM channel configuration 5 register */ -# define STM32L4_DFSDM_CH6CFGR1_OFFSET 0x00c0 /* DFSDM channel configuration 6 register */ -# define STM32L4_DFSDM_CH7CFGR1_OFFSET 0x00e0 /* DFSDM channel configuration 7 register */ +#define STM32_DFSDM_CHCFGR1_OFFSET(y) (0x00 + 0x20 * (y)) + +#define STM32_DFSDM_CH0CFGR1_OFFSET 0x0000 /* DFSDM channel configuration 0 register */ +#define STM32_DFSDM_CH1CFGR1_OFFSET 0x0020 /* DFSDM channel configuration 1 register */ +#define STM32_DFSDM_CH2CFGR1_OFFSET 0x0040 /* DFSDM channel configuration 2 register */ +#define STM32_DFSDM_CH3CFGR1_OFFSET 0x0060 /* DFSDM channel configuration 3 register */ +#ifndef CONFIG_STM32_STM32L4X3 +# define STM32_DFSDM_CH4CFGR1_OFFSET 0x0080 /* DFSDM channel configuration 4 register */ +# define STM32_DFSDM_CH5CFGR1_OFFSET 0x00a0 /* DFSDM channel configuration 5 register */ +# define STM32_DFSDM_CH6CFGR1_OFFSET 0x00c0 /* DFSDM channel configuration 6 register */ +# define STM32_DFSDM_CH7CFGR1_OFFSET 0x00e0 /* DFSDM channel configuration 7 register */ #endif -#define STM32L4_DFSDM_CHCFGR2_OFFSET(y) (0x04 + 0x20 * (y)) - -#define STM32L4_DFSDM_CH0CFGR2_OFFSET 0x0004 /* DFSDM channel configuration 0 register 2 */ -#define STM32L4_DFSDM_CH1CFGR2_OFFSET 0x0024 /* DFSDM channel configuration 1 register 2 */ -#define STM32L4_DFSDM_CH2CFGR2_OFFSET 0x0044 /* DFSDM channel configuration 2 register 2 */ -#define STM32L4_DFSDM_CH3CFGR2_OFFSET 0x0064 /* DFSDM channel configuration 3 register 2 */ -#ifndef CONFIG_STM32L4_STM32L4X3 -# define STM32L4_DFSDM_CH4CFGR2_OFFSET 0x0084 /* DFSDM channel configuration 4 register 2 */ -# define STM32L4_DFSDM_CH5CFGR2_OFFSET 0x00a4 /* DFSDM channel configuration 5 register 2 */ -# define STM32L4_DFSDM_CH6CFGR2_OFFSET 0x00c4 /* DFSDM channel configuration 6 register 2 */ -# define STM32L4_DFSDM_CH7CFGR2_OFFSET 0x00e4 /* DFSDM channel configuration 7 register 2 */ +#define STM32_DFSDM_CHCFGR2_OFFSET(y) (0x04 + 0x20 * (y)) + +#define STM32_DFSDM_CH0CFGR2_OFFSET 0x0004 /* DFSDM channel configuration 0 register 2 */ +#define STM32_DFSDM_CH1CFGR2_OFFSET 0x0024 /* DFSDM channel configuration 1 register 2 */ +#define STM32_DFSDM_CH2CFGR2_OFFSET 0x0044 /* DFSDM channel configuration 2 register 2 */ +#define STM32_DFSDM_CH3CFGR2_OFFSET 0x0064 /* DFSDM channel configuration 3 register 2 */ +#ifndef CONFIG_STM32_STM32L4X3 +# define STM32_DFSDM_CH4CFGR2_OFFSET 0x0084 /* DFSDM channel configuration 4 register 2 */ +# define STM32_DFSDM_CH5CFGR2_OFFSET 0x00a4 /* DFSDM channel configuration 5 register 2 */ +# define STM32_DFSDM_CH6CFGR2_OFFSET 0x00c4 /* DFSDM channel configuration 6 register 2 */ +# define STM32_DFSDM_CH7CFGR2_OFFSET 0x00e4 /* DFSDM channel configuration 7 register 2 */ #endif -#define STM32L4_DFSDM_CHAWSCDR_OFFSET(y) (0x08 + 0x20 * (y)) - -#define STM32L4_DFSDM_CH0AWSCDR_OFFSET 0x0008 /* DFSDM channel 0 analog watchdog and short-circuit detector register */ -#define STM32L4_DFSDM_CH1AWSCDR_OFFSET 0x0028 /* DFSDM channel 1 analog watchdog and short-circuit detector register */ -#define STM32L4_DFSDM_CH2AWSCDR_OFFSET 0x0048 /* DFSDM channel 2 analog watchdog and short-circuit detector register */ -#define STM32L4_DFSDM_CH3AWSCDR_OFFSET 0x0068 /* DFSDM channel 3 analog watchdog and short-circuit detector register */ -#ifndef CONFIG_STM32L4_STM32L4X3 -# define STM32L4_DFSDM_CH4AWSCDR_OFFSET 0x0088 /* DFSDM channel 4 analog watchdog and short-circuit detector register */ -# define STM32L4_DFSDM_CH5AWSCDR_OFFSET 0x00a8 /* DFSDM channel 5 analog watchdog and short-circuit detector register */ -# define STM32L4_DFSDM_CH6AWSCDR_OFFSET 0x00c8 /* DFSDM channel 6 analog watchdog and short-circuit detector register */ -# define STM32L4_DFSDM_CH7AWSCDR_OFFSET 0x00e8 /* DFSDM channel 7 analog watchdog and short-circuit detector register */ +#define STM32_DFSDM_CHAWSCDR_OFFSET(y) (0x08 + 0x20 * (y)) + +#define STM32_DFSDM_CH0AWSCDR_OFFSET 0x0008 /* DFSDM channel 0 analog watchdog and short-circuit detector register */ +#define STM32_DFSDM_CH1AWSCDR_OFFSET 0x0028 /* DFSDM channel 1 analog watchdog and short-circuit detector register */ +#define STM32_DFSDM_CH2AWSCDR_OFFSET 0x0048 /* DFSDM channel 2 analog watchdog and short-circuit detector register */ +#define STM32_DFSDM_CH3AWSCDR_OFFSET 0x0068 /* DFSDM channel 3 analog watchdog and short-circuit detector register */ +#ifndef CONFIG_STM32_STM32L4X3 +# define STM32_DFSDM_CH4AWSCDR_OFFSET 0x0088 /* DFSDM channel 4 analog watchdog and short-circuit detector register */ +# define STM32_DFSDM_CH5AWSCDR_OFFSET 0x00a8 /* DFSDM channel 5 analog watchdog and short-circuit detector register */ +# define STM32_DFSDM_CH6AWSCDR_OFFSET 0x00c8 /* DFSDM channel 6 analog watchdog and short-circuit detector register */ +# define STM32_DFSDM_CH7AWSCDR_OFFSET 0x00e8 /* DFSDM channel 7 analog watchdog and short-circuit detector register */ #endif -#define STM32L4_DFSDM_CHWDATR_OFFSET(y) (0x0c + 0x20 * (y)) - -#define STM32L4_DFSDM_CH0WDATR_OFFSET 0x000c /* DFSDM channel 0 watchdog filter data register */ -#define STM32L4_DFSDM_CH1WDATR_OFFSET 0x002c /* DFSDM channel 1 watchdog filter data register */ -#define STM32L4_DFSDM_CH2WDATR_OFFSET 0x004c /* DFSDM channel 2 watchdog filter data register */ -#define STM32L4_DFSDM_CH3WDATR_OFFSET 0x006c /* DFSDM channel 3 watchdog filter data register */ -#ifndef CONFIG_STM32L4_STM32L4X3 -# define STM32L4_DFSDM_CH4WDATR_OFFSET 0x008c /* DFSDM channel 4 watchdog filter data register */ -# define STM32L4_DFSDM_CH5WDATR_OFFSET 0x00ac /* DFSDM channel 5 watchdog filter data register */ -# define STM32L4_DFSDM_CH6WDATR_OFFSET 0x00cc /* DFSDM channel 6 watchdog filter data register */ -# define STM32L4_DFSDM_CH7WDATR_OFFSET 0x00ec /* DFSDM channel 7 watchdog filter data register */ +#define STM32_DFSDM_CHWDATR_OFFSET(y) (0x0c + 0x20 * (y)) + +#define STM32_DFSDM_CH0WDATR_OFFSET 0x000c /* DFSDM channel 0 watchdog filter data register */ +#define STM32_DFSDM_CH1WDATR_OFFSET 0x002c /* DFSDM channel 1 watchdog filter data register */ +#define STM32_DFSDM_CH2WDATR_OFFSET 0x004c /* DFSDM channel 2 watchdog filter data register */ +#define STM32_DFSDM_CH3WDATR_OFFSET 0x006c /* DFSDM channel 3 watchdog filter data register */ +#ifndef CONFIG_STM32_STM32L4X3 +# define STM32_DFSDM_CH4WDATR_OFFSET 0x008c /* DFSDM channel 4 watchdog filter data register */ +# define STM32_DFSDM_CH5WDATR_OFFSET 0x00ac /* DFSDM channel 5 watchdog filter data register */ +# define STM32_DFSDM_CH6WDATR_OFFSET 0x00cc /* DFSDM channel 6 watchdog filter data register */ +# define STM32_DFSDM_CH7WDATR_OFFSET 0x00ec /* DFSDM channel 7 watchdog filter data register */ #endif -#define STM32L4_DFSDM_CHDATINR_OFFSET(ch) (0x10 + 0x20 * (ch)) /* DFSDM channel data input register */ - -#define STM32L4_DFSDM_CH0DATINR_OFFSET 0x0010 /* DFSDM channel 0 data input register */ -#define STM32L4_DFSDM_CH1DATINR_OFFSET 0x0030 /* DFSDM channel 1 data input register */ -#define STM32L4_DFSDM_CH2DATINR_OFFSET 0x0050 /* DFSDM channel 2 data input register */ -#define STM32L4_DFSDM_CH3DATINR_OFFSET 0x0070 /* DFSDM channel 3 data input register */ -#ifndef CONFIG_STM32L4_STM32L4X3 -# define STM32L4_DFSDM_CH4DATINR_OFFSET 0x0090 /* DFSDM channel 4 data input register */ -# define STM32L4_DFSDM_CH5DATINR_OFFSET 0x00b0 /* DFSDM channel 5 data input register */ -# define STM32L4_DFSDM_CH6DATINR_OFFSET 0x00d0 /* DFSDM channel 6 data input register */ -# define STM32L4_DFSDM_CH7DATINR_OFFSET 0x00f0 /* DFSDM channel 7 data input register */ +#define STM32_DFSDM_CHDATINR_OFFSET(ch) (0x10 + 0x20 * (ch)) /* DFSDM channel data input register */ + +#define STM32_DFSDM_CH0DATINR_OFFSET 0x0010 /* DFSDM channel 0 data input register */ +#define STM32_DFSDM_CH1DATINR_OFFSET 0x0030 /* DFSDM channel 1 data input register */ +#define STM32_DFSDM_CH2DATINR_OFFSET 0x0050 /* DFSDM channel 2 data input register */ +#define STM32_DFSDM_CH3DATINR_OFFSET 0x0070 /* DFSDM channel 3 data input register */ +#ifndef CONFIG_STM32_STM32L4X3 +# define STM32_DFSDM_CH4DATINR_OFFSET 0x0090 /* DFSDM channel 4 data input register */ +# define STM32_DFSDM_CH5DATINR_OFFSET 0x00b0 /* DFSDM channel 5 data input register */ +# define STM32_DFSDM_CH6DATINR_OFFSET 0x00d0 /* DFSDM channel 6 data input register */ +# define STM32_DFSDM_CH7DATINR_OFFSET 0x00f0 /* DFSDM channel 7 data input register */ #endif -#ifdef CONFIG_STM32L4_STM32L4XR -# define STM32L4_DFSDM_CHDLYR_OFFSET(ch) (0x14 + 0x20 * (ch)) /* DFSDM channel delay register */ - -# define STM32L4_DFSDM_CH0DLYR_OFFSET 0x0014 /* DFSDM channel 0 delay register */ -# define STM32L4_DFSDM_CH1DLYR_OFFSET 0x0034 /* DFSDM channel 1 delay register */ -# define STM32L4_DFSDM_CH2DLYR_OFFSET 0x0054 /* DFSDM channel 2 delay register */ -# define STM32L4_DFSDM_CH3DLYR_OFFSET 0x0074 /* DFSDM channel 3 delay register */ -# define STM32L4_DFSDM_CH4DLYR_OFFSET 0x0094 /* DFSDM channel 4 delay register */ -# define STM32L4_DFSDM_CH5DLYR_OFFSET 0x00b4 /* DFSDM channel 5 delay register */ -# define STM32L4_DFSDM_CH6DLYR_OFFSET 0x00d4 /* DFSDM channel 6 delay register */ -# define STM32L4_DFSDM_CH7DLYR_OFFSET 0x00f4 /* DFSDM channel 7 delay register */ +#ifdef CONFIG_STM32_STM32L4XR +# define STM32_DFSDM_CHDLYR_OFFSET(ch) (0x14 + 0x20 * (ch)) /* DFSDM channel delay register */ + +# define STM32_DFSDM_CH0DLYR_OFFSET 0x0014 /* DFSDM channel 0 delay register */ +# define STM32_DFSDM_CH1DLYR_OFFSET 0x0034 /* DFSDM channel 1 delay register */ +# define STM32_DFSDM_CH2DLYR_OFFSET 0x0054 /* DFSDM channel 2 delay register */ +# define STM32_DFSDM_CH3DLYR_OFFSET 0x0074 /* DFSDM channel 3 delay register */ +# define STM32_DFSDM_CH4DLYR_OFFSET 0x0094 /* DFSDM channel 4 delay register */ +# define STM32_DFSDM_CH5DLYR_OFFSET 0x00b4 /* DFSDM channel 5 delay register */ +# define STM32_DFSDM_CH6DLYR_OFFSET 0x00d4 /* DFSDM channel 6 delay register */ +# define STM32_DFSDM_CH7DLYR_OFFSET 0x00f4 /* DFSDM channel 7 delay register */ #endif /* DFSDM filter x module registers (x=0..3 or x=0..1 on STM32L4X3) */ -#define STM32L4_DFSDM_FLTCR1_OFFSET(x) (0x100 + 0x80 * (x)) /* DFSDM control register 1 */ -#define STM32L4_DFSDM_FLTCR2_OFFSET(x) (0x104 + 0x80 * (x)) /* DFSDM control register 2 */ -#define STM32L4_DFSDM_FLTISR_OFFSET(x) (0x108 + 0x80 * (x)) /* DFSDM interrupt and status register */ -#define STM32L4_DFSDM_FLTICR_OFFSET(x) (0x10c + 0x80 * (x)) /* DFSDM interrupt flag clear register */ -#define STM32L4_DFSDM_FLTJCHGR_OFFSET(x) (0x110 + 0x80 * (x)) /* DFSDM injected channel group selection register */ -#define STM32L4_DFSDM_FLTFCR_OFFSET(x) (0x114 + 0x80 * (x)) /* DFSDM filter control register */ -#define STM32L4_DFSDM_FLTJDATAR_OFFSET(x) (0x118 + 0x80 * (x)) /* DFSDM data register for injected group */ -#define STM32L4_DFSDM_FLTRDATAR_OFFSET(x) (0x11c + 0x80 * (x)) /* DFSDM data register for the regular channel */ -#define STM32L4_DFSDM_FLTAWHTR_OFFSET(x) (0x120 + 0x80 * (x)) /* DFSDM analog watchdog high threshold register */ -#define STM32L4_DFSDM_FLTAWLTR_OFFSET(x) (0x124 + 0x80 * (x)) /* DFSDM analog watchdog low threshold register */ -#define STM32L4_DFSDM_FLTAWSR_OFFSET(x) (0x128 + 0x80 * (x)) /* DFSDM analog watchdog status register */ -#define STM32L4_DFSDM_FLTAWCFR_OFFSET(x) (0x12c + 0x80 * (x)) /* DFSDM analog watchdog clear flag register */ -#define STM32L4_DFSDM_FLTEXMAX_OFFSET(x) (0x130 + 0x80 * (x)) /* DFSDM Extremes detector maximum register */ -#define STM32L4_DFSDM_FLTEXMIN_OFFSET(x) (0x134 + 0x80 * (x)) /* DFSDM Extremes detector minimum register */ -#define STM32L4_DFSDM_FLTCNVTIMR_OFFSET(x) (0x138 + 0x80 * (x)) /* DFSDM conversion timer register */ +#define STM32_DFSDM_FLTCR1_OFFSET(x) (0x100 + 0x80 * (x)) /* DFSDM control register 1 */ +#define STM32_DFSDM_FLTCR2_OFFSET(x) (0x104 + 0x80 * (x)) /* DFSDM control register 2 */ +#define STM32_DFSDM_FLTISR_OFFSET(x) (0x108 + 0x80 * (x)) /* DFSDM interrupt and status register */ +#define STM32_DFSDM_FLTICR_OFFSET(x) (0x10c + 0x80 * (x)) /* DFSDM interrupt flag clear register */ +#define STM32_DFSDM_FLTJCHGR_OFFSET(x) (0x110 + 0x80 * (x)) /* DFSDM injected channel group selection register */ +#define STM32_DFSDM_FLTFCR_OFFSET(x) (0x114 + 0x80 * (x)) /* DFSDM filter control register */ +#define STM32_DFSDM_FLTJDATAR_OFFSET(x) (0x118 + 0x80 * (x)) /* DFSDM data register for injected group */ +#define STM32_DFSDM_FLTRDATAR_OFFSET(x) (0x11c + 0x80 * (x)) /* DFSDM data register for the regular channel */ +#define STM32_DFSDM_FLTAWHTR_OFFSET(x) (0x120 + 0x80 * (x)) /* DFSDM analog watchdog high threshold register */ +#define STM32_DFSDM_FLTAWLTR_OFFSET(x) (0x124 + 0x80 * (x)) /* DFSDM analog watchdog low threshold register */ +#define STM32_DFSDM_FLTAWSR_OFFSET(x) (0x128 + 0x80 * (x)) /* DFSDM analog watchdog status register */ +#define STM32_DFSDM_FLTAWCFR_OFFSET(x) (0x12c + 0x80 * (x)) /* DFSDM analog watchdog clear flag register */ +#define STM32_DFSDM_FLTEXMAX_OFFSET(x) (0x130 + 0x80 * (x)) /* DFSDM Extremes detector maximum register */ +#define STM32_DFSDM_FLTEXMIN_OFFSET(x) (0x134 + 0x80 * (x)) /* DFSDM Extremes detector minimum register */ +#define STM32_DFSDM_FLTCNVTIMR_OFFSET(x) (0x138 + 0x80 * (x)) /* DFSDM conversion timer register */ /* Register Addresses *******************************************************/ /* DFSDM channel y registers (y=0..7 or y=0..3 on STM32L4X3) */ -#define STM32L4_DFSDM_CHCFGR1(y) (STM32L4_DFSDM_BASE + STM32L4_DFSDM_CHCFGR1_OFFSET(y)) -#define STM32L4_DFSDM_CH0CFGR1 (STM32L4_DFSDM_BASE + STM32L4_DFSDM_CH0CFGR1_OFFSET) +#define STM32_DFSDM_CHCFGR1(y) (STM32_DFSDM_BASE + STM32_DFSDM_CHCFGR1_OFFSET(y)) +#define STM32_DFSDM_CH0CFGR1 (STM32_DFSDM_BASE + STM32_DFSDM_CH0CFGR1_OFFSET) -#define STM32L4_DFSDM_CHCFGR2(y) (STM32L4_DFSDM_BASE + STM32L4_DFSDM_CHCFGR2_OFFSET(y)) -#define STM32L4_DFSDM_CHAWSCDR(y) (STM32L4_DFSDM_BASE + STM32L4_DFSDM_CHAWSCDR_OFFSET(y)) -#define STM32L4_DFSDM_CHWDATR(y) (STM32L4_DFSDM_BASE + STM32L4_DFSDM_CHWDATR_OFFSET(y) -#define STM32L4_DFSDM_CHDATINR(y) (STM32L4_DFSDM_BASE + STM32L4_DFSDM_CHDATINR_OFFSET(y)) -#ifdef CONFIG_STM32L4_STM32L4XR -# define STM32L4_DFSDM_CHDLYR(y) (STM32L4_DFSDM_BASE + STM32L4_DFSDM_CHDLYR_OFFSET(y)) +#define STM32_DFSDM_CHCFGR2(y) (STM32_DFSDM_BASE + STM32_DFSDM_CHCFGR2_OFFSET(y)) +#define STM32_DFSDM_CHAWSCDR(y) (STM32_DFSDM_BASE + STM32_DFSDM_CHAWSCDR_OFFSET(y)) +#define STM32_DFSDM_CHWDATR(y) (STM32_DFSDM_BASE + STM32_DFSDM_CHWDATR_OFFSET(y) +#define STM32_DFSDM_CHDATINR(y) (STM32_DFSDM_BASE + STM32_DFSDM_CHDATINR_OFFSET(y)) +#ifdef CONFIG_STM32_STM32L4XR +# define STM32_DFSDM_CHDLYR(y) (STM32_DFSDM_BASE + STM32_DFSDM_CHDLYR_OFFSET(y)) #endif /* DFSDM filter x module registers (x=0..3 or x=0..1 on STM32L4X3) */ -#define STM32L4_DFSDM_FLTCR1(x) (STM32L4_DFSDM_BASE + STM32L4_DFSDM_FLTCR1_OFFSET(x)) -#define STM32L4_DFSDM_FLTCR2(x) (STM32L4_DFSDM_BASE + STM32L4_DFSDM_FLTCR2_OFFSET(x)) -#define STM32L4_DFSDM_FLTISR(x) (STM32L4_DFSDM_BASE + STM32L4_DFSDM_FLTISR_OFFSET(x)) -#define STM32L4_DFSDM_FLTICR(x) (STM32L4_DFSDM_BASE + STM32L4_DFSDM_FLTICR_OFFSET(x)) -#define STM32L4_DFSDM_FLTJCHGR(x) (STM32L4_DFSDM_BASE + STM32L4_DFSDM_FLTJCHGR_OFFSET(x)) -#define STM32L4_DFSDM_FLTFCR(x) (STM32L4_DFSDM_BASE + STM32L4_DFSDM_FLTFCR_OFFSET(x)) -#define STM32L4_DFSDM_FLTJDATAR(x) (STM32L4_DFSDM_BASE + STM32L4_DFSDM_FLTJDATAR_OFFSET(x)) -#define STM32L4_DFSDM_FLTRDATAR(x) (STM32L4_DFSDM_BASE + STM32L4_DFSDM_FLTRDATAR_OFFSET(x)) -#define STM32L4_DFSDM_FLTAWHTR(x) (STM32L4_DFSDM_BASE + STM32L4_DFSDM_FLTAWHTR_OFFSET(x)) -#define STM32L4_DFSDM_FLTAWLTR(x) (STM32L4_DFSDM_BASE + STM32L4_DFSDM_FLTAWLTR_OFFSET(x)) -#define STM32L4_DFSDM_FLTAWSR(x) (STM32L4_DFSDM_BASE + STM32L4_DFSDM_FLTAWSR_OFFSET(x)) -#define STM32L4_DFSDM_FLTAWCFR(x) (STM32L4_DFSDM_BASE + STM32L4_DFSDM_FLTAWCFR_OFFSET(x)) -#define STM32L4_DFSDM_FLTEXMAX(x) (STM32L4_DFSDM_BASE + STM32L4_DFSDM_FLTEXMAX_OFFSET(x)) -#define STM32L4_DFSDM_FLTEXMIN(x) (STM32L4_DFSDM_BASE + STM32L4_DFSDM_FLTEXMIN_OFFSET(x)) -#define STM32L4_DFSDM_FLTCNVTIMR(x) (STM32L4_DFSDM_BASE + STM32L4_DFSDM_FLTCNVTIMR_OFFSET(x)) +#define STM32_DFSDM_FLTCR1(x) (STM32_DFSDM_BASE + STM32_DFSDM_FLTCR1_OFFSET(x)) +#define STM32_DFSDM_FLTCR2(x) (STM32_DFSDM_BASE + STM32_DFSDM_FLTCR2_OFFSET(x)) +#define STM32_DFSDM_FLTISR(x) (STM32_DFSDM_BASE + STM32_DFSDM_FLTISR_OFFSET(x)) +#define STM32_DFSDM_FLTICR(x) (STM32_DFSDM_BASE + STM32_DFSDM_FLTICR_OFFSET(x)) +#define STM32_DFSDM_FLTJCHGR(x) (STM32_DFSDM_BASE + STM32_DFSDM_FLTJCHGR_OFFSET(x)) +#define STM32_DFSDM_FLTFCR(x) (STM32_DFSDM_BASE + STM32_DFSDM_FLTFCR_OFFSET(x)) +#define STM32_DFSDM_FLTJDATAR(x) (STM32_DFSDM_BASE + STM32_DFSDM_FLTJDATAR_OFFSET(x)) +#define STM32_DFSDM_FLTRDATAR(x) (STM32_DFSDM_BASE + STM32_DFSDM_FLTRDATAR_OFFSET(x)) +#define STM32_DFSDM_FLTAWHTR(x) (STM32_DFSDM_BASE + STM32_DFSDM_FLTAWHTR_OFFSET(x)) +#define STM32_DFSDM_FLTAWLTR(x) (STM32_DFSDM_BASE + STM32_DFSDM_FLTAWLTR_OFFSET(x)) +#define STM32_DFSDM_FLTAWSR(x) (STM32_DFSDM_BASE + STM32_DFSDM_FLTAWSR_OFFSET(x)) +#define STM32_DFSDM_FLTAWCFR(x) (STM32_DFSDM_BASE + STM32_DFSDM_FLTAWCFR_OFFSET(x)) +#define STM32_DFSDM_FLTEXMAX(x) (STM32_DFSDM_BASE + STM32_DFSDM_FLTEXMAX_OFFSET(x)) +#define STM32_DFSDM_FLTEXMIN(x) (STM32_DFSDM_BASE + STM32_DFSDM_FLTEXMIN_OFFSET(x)) +#define STM32_DFSDM_FLTCNVTIMR(x) (STM32_DFSDM_BASE + STM32_DFSDM_FLTCNVTIMR_OFFSET(x)) /* Register Bitfield Definitions ********************************************/ @@ -289,17 +289,17 @@ # define DFSDM_FLTCR1_JEXTSEL_T1TRGO (0x00 << DFSDM_FLTCR1_JEXTSEL_SHIFT) /* 0000: Timer 1 TRGO event */ # define DFSDM_FLTCR1_JEXTSEL_T1TRGO2 (0x01 << DFSDM_FLTCR1_JEXTSEL_SHIFT) /* 0001: Timer 1 TRGO2 event */ -# if !defined(CONFIG_STM32L4_STM32L4X3) +# if !defined(CONFIG_STM32_STM32L4X3) # define DFSDM_FLTCR1_JEXTSEL_T8TRGO (0x02 << DFSDM_FLTCR1_JEXTSEL_SHIFT) /* 0010: Timer 8 TRGO event */ # else # define DFSDM_FLTCR1_JEXTSEL_T3TRGO (0x02 << DFSDM_FLTCR1_JEXTSEL_SHIFT) /* 0010: Timer 3 TRGO event */ # endif -# if !defined(CONFIG_STM32L4_STM32L4X3) +# if !defined(CONFIG_STM32_STM32L4X3) # define DFSDM_FLTCR1_JEXTSEL_T8TRGO2 (0x03 << DFSDM_FLTCR1_JEXTSEL_SHIFT) /* 0011: Timer 8 TRGO2 event */ # else # define DFSDM_FLTCR1_JEXTSEL_T16CC1 (0x03 << DFSDM_FLTCR1_JEXTSEL_SHIFT) /* 0011: Timer 16 CC1 (or OC1) event */ # endif -# if !defined(CONFIG_STM32L4_STM32L4X3) +# if !defined(CONFIG_STM32_STM32L4X3) # define DFSDM_FLTCR1_JEXTSEL_T4TRGO (0x04 << DFSDM_FLTCR1_JEXTSEL_SHIFT) /* 0100: Timer 4 TRGO event */ # endif # define DFSDM_FLTCR1_JEXTSEL_T6TRGO (0x05 << DFSDM_FLTCR1_JEXTSEL_SHIFT) /* 0101: Timer 6 TRGO event */ @@ -413,8 +413,8 @@ /* DFSDM data register for the regular channel (DFSDM_FLTxRDATAR) */ -#if defined(CONFIG_STM32L4_STM32L4X3) || defined(CONFIG_STM32L4_STM32L496XX) || \ - defined(CONFIG_STM32L4_STM32L4XR) +#if defined(CONFIG_STM32_STM32L4X3) || defined(CONFIG_STM32_STM32L496XX) || \ + defined(CONFIG_STM32_STM32L4XR) # define DFSDM_FLTRDATAR_RDATACH_SHIFT (0) /* Bits 0-3: channel most recently converted */ # define DFSDM_FLTRDATAR_RDATACH_MASK (7 << DFSDM_FLTRDATAR_RDATACH_SHIFT) #endif diff --git a/arch/arm/src/stm32l4/hardware/stm32l4_exti.h b/arch/arm/src/stm32l4/hardware/stm32l4_exti.h index f6295dc9c42fd..a7585f24b27c4 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4_exti.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4_exti.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_EXTI_H -#define __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_EXTI_H +#ifndef __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32_EXTI_H +#define __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32_EXTI_H /**************************************************************************** * Included Files @@ -34,44 +34,44 @@ * Pre-processor Definitions ****************************************************************************/ -#define STM32L4_NEXTI1 31 -#define STM32L4_EXTI1_MASK 0xffffffff -#define STM32L4_NEXTI2 9 -#define STM32L4_EXTI2_MASK 0x000001ff +#define STM32_NEXTI1 31 +#define STM32_EXTI1_MASK 0xffffffff +#define STM32_NEXTI2 9 +#define STM32_EXTI2_MASK 0x000001ff -#define STM32L4_EXTI1_BIT(n) (1 << (n)) -#define STM32L4_EXTI2_BIT(n) (1 << (n)) +#define STM32_EXTI1_BIT(n) (1 << (n)) +#define STM32_EXTI2_BIT(n) (1 << (n)) /* Register Offsets *********************************************************/ -#define STM32L4_EXTI1_OFFSET 0x0000 /* Offset to EXTI1 registers */ -#define STM32L4_EXTI2_OFFSET 0x0020 /* Offset to EXTI2 registers */ +#define STM32_EXTI1_OFFSET 0x0000 /* Offset to EXTI1 registers */ +#define STM32_EXTI2_OFFSET 0x0020 /* Offset to EXTI2 registers */ -#define STM32L4_EXTI_IMR_OFFSET 0x0000 /* Interrupt mask register */ -#define STM32L4_EXTI_EMR_OFFSET 0x0004 /* Event mask register */ -#define STM32L4_EXTI_RTSR_OFFSET 0x0008 /* Rising Trigger selection register */ -#define STM32L4_EXTI_FTSR_OFFSET 0x000c /* Falling Trigger selection register */ -#define STM32L4_EXTI_SWIER_OFFSET 0x0010 /* Software interrupt event register */ -#define STM32L4_EXTI_PR_OFFSET 0x0014 /* Pending register */ +#define STM32_EXTI_IMR_OFFSET 0x0000 /* Interrupt mask register */ +#define STM32_EXTI_EMR_OFFSET 0x0004 /* Event mask register */ +#define STM32_EXTI_RTSR_OFFSET 0x0008 /* Rising Trigger selection register */ +#define STM32_EXTI_FTSR_OFFSET 0x000c /* Falling Trigger selection register */ +#define STM32_EXTI_SWIER_OFFSET 0x0010 /* Software interrupt event register */ +#define STM32_EXTI_PR_OFFSET 0x0014 /* Pending register */ /* Register Addresses *******************************************************/ -#define STM32L4_EXTI1_BASE (STM32L4_EXTI_BASE+STM32L4_EXTI1_OFFSET) -#define STM32L4_EXTI2_BASE (STM32L4_EXTI_BASE+STM32L4_EXTI2_OFFSET) +#define STM32_EXTI1_BASE (STM32_EXTI_BASE+STM32_EXTI1_OFFSET) +#define STM32_EXTI2_BASE (STM32_EXTI_BASE+STM32_EXTI2_OFFSET) -#define STM32L4_EXTI1_IMR (STM32L4_EXTI1_BASE+STM32L4_EXTI_IMR_OFFSET) -#define STM32L4_EXTI1_EMR (STM32L4_EXTI1_BASE+STM32L4_EXTI_EMR_OFFSET) -#define STM32L4_EXTI1_RTSR (STM32L4_EXTI1_BASE+STM32L4_EXTI_RTSR_OFFSET) -#define STM32L4_EXTI1_FTSR (STM32L4_EXTI1_BASE+STM32L4_EXTI_FTSR_OFFSET) -#define STM32L4_EXTI1_SWIER (STM32L4_EXTI1_BASE+STM32L4_EXTI_SWIER_OFFSET) -#define STM32L4_EXTI1_PR (STM32L4_EXTI1_BASE+STM32L4_EXTI_PR_OFFSET) +#define STM32_EXTI1_IMR (STM32_EXTI1_BASE+STM32_EXTI_IMR_OFFSET) +#define STM32_EXTI1_EMR (STM32_EXTI1_BASE+STM32_EXTI_EMR_OFFSET) +#define STM32_EXTI1_RTSR (STM32_EXTI1_BASE+STM32_EXTI_RTSR_OFFSET) +#define STM32_EXTI1_FTSR (STM32_EXTI1_BASE+STM32_EXTI_FTSR_OFFSET) +#define STM32_EXTI1_SWIER (STM32_EXTI1_BASE+STM32_EXTI_SWIER_OFFSET) +#define STM32_EXTI1_PR (STM32_EXTI1_BASE+STM32_EXTI_PR_OFFSET) -#define STM32L4_EXTI2_IMR (STM32L4_EXTI2_BASE+STM32L4_EXTI_IMR_OFFSET) -#define STM32L4_EXTI2_EMR (STM32L4_EXTI2_BASE+STM32L4_EXTI_EMR_OFFSET) -#define STM32L4_EXTI2_RTSR (STM32L4_EXTI2_BASE+STM32L4_EXTI_RTSR_OFFSET) -#define STM32L4_EXTI2_FTSR (STM32L4_EXTI2_BASE+STM32L4_EXTI_FTSR_OFFSET) -#define STM32L4_EXTI2_SWIER (STM32L4_EXTI2_BASE+STM32L4_EXTI_SWIER_OFFSET) -#define STM32L4_EXTI2_PR (STM32L4_EXTI2_BASE+STM32L4_EXTI_PR_OFFSET) +#define STM32_EXTI2_IMR (STM32_EXTI2_BASE+STM32_EXTI_IMR_OFFSET) +#define STM32_EXTI2_EMR (STM32_EXTI2_BASE+STM32_EXTI_EMR_OFFSET) +#define STM32_EXTI2_RTSR (STM32_EXTI2_BASE+STM32_EXTI_RTSR_OFFSET) +#define STM32_EXTI2_FTSR (STM32_EXTI2_BASE+STM32_EXTI_FTSR_OFFSET) +#define STM32_EXTI2_SWIER (STM32_EXTI2_BASE+STM32_EXTI_SWIER_OFFSET) +#define STM32_EXTI2_PR (STM32_EXTI2_BASE+STM32_EXTI_PR_OFFSET) /* Register Bitfield Definitions ********************************************/ @@ -105,62 +105,62 @@ /* Interrupt mask register */ -#define EXTI_IMR1_BIT(n) STM32L4_EXTI1_BIT(n) /* 1=Interrupt request from line x is not masked */ +#define EXTI_IMR1_BIT(n) STM32_EXTI1_BIT(n) /* 1=Interrupt request from line x is not masked */ #define EXTI_IMR1_SHIFT (0) /* Bits 0-X: Interrupt Mask for all lines */ -#define EXTI_IMR1_MASK STM32L4_EXTI1_MASK +#define EXTI_IMR1_MASK STM32_EXTI1_MASK -#define EXTI_IMR2_BIT(n) STM32L4_EXTI2_BIT(n) /* 1=Interrupt request from line x is not masked */ +#define EXTI_IMR2_BIT(n) STM32_EXTI2_BIT(n) /* 1=Interrupt request from line x is not masked */ #define EXTI_IMR2_SHIFT (0) /* Bits 0-X: Interrupt Mask for all lines */ -#define EXTI_IMR2_MASK STM32L4_EXTI2_MASK +#define EXTI_IMR2_MASK STM32_EXTI2_MASK /* Event mask register */ -#define EXTI_EMR1_BIT(n) STM32L4_EXTI1_BIT(n) /* 1=Event request from line x is not mask */ +#define EXTI_EMR1_BIT(n) STM32_EXTI1_BIT(n) /* 1=Event request from line x is not mask */ #define EXTI_EMR1_SHIFT (0) /* Bits Bits 0-X: Event Mask for all lines */ -#define EXTI_EMR1_MASK STM32L4_EXTI1_MASK +#define EXTI_EMR1_MASK STM32_EXTI1_MASK -#define EXTI_EMR2_BIT(n) STM32L4_EXTI2_BIT(n) /* 1=Event request from line x is not mask */ +#define EXTI_EMR2_BIT(n) STM32_EXTI2_BIT(n) /* 1=Event request from line x is not mask */ #define EXTI_EMR2_SHIFT (0) /* Bits Bits 0-X: Event Mask for all lines */ -#define EXTI_EMR2_MASK STM32L4_EXTI2_MASK +#define EXTI_EMR2_MASK STM32_EXTI2_MASK /* Rising Trigger selection register */ -#define EXTI_RTSR1_BIT(n) STM32L4_EXTI1_BIT(n) /* 1=Rising trigger enabled (for Event and Interrupt) for input line */ +#define EXTI_RTSR1_BIT(n) STM32_EXTI1_BIT(n) /* 1=Rising trigger enabled (for Event and Interrupt) for input line */ #define EXTI_RTSR1_SHIFT (0) /* Bits 0-X: Rising trigger event configuration bit for all lines */ -#define EXTI_RTSR1_MASK STM32L4_EXTI1_MASK +#define EXTI_RTSR1_MASK STM32_EXTI1_MASK -#define EXTI_RTSR2_BIT(n) STM32L4_EXTI2_BIT(n) /* 1=Rising trigger enabled (for Event and Interrupt) for input line */ +#define EXTI_RTSR2_BIT(n) STM32_EXTI2_BIT(n) /* 1=Rising trigger enabled (for Event and Interrupt) for input line */ #define EXTI_RTSR2_SHIFT (0) /* Bits 0-X: Rising trigger event configuration bit for all lines */ -#define EXTI_RTSR2_MASK STM32L4_EXTI2_MASK +#define EXTI_RTSR2_MASK STM32_EXTI2_MASK /* Falling Trigger selection register */ -#define EXTI_FTSR1_BIT(n) STM32L4_EXTI1_BIT(n) /* 1=Falling trigger enabled (for Event and Interrupt) for input line */ -#define EXTI_FTSR1_SHIFT (0) /* Bits 0-X: Falling trigger event configuration bitfor all lines */ -#define EXTI_FTSR1_MASK STM32L4_EXTI1_MASK +#define EXTI_FTSR1_BIT(n) STM32_EXTI1_BIT(n) /* 1=Falling trigger enabled (for Event and Interrupt) for input line */ +#define EXTI_FTSR1_SHIFT (0) /* Bits 0-X: Falling trigger event configuration bitfor all lines */ +#define EXTI_FTSR1_MASK STM32_EXTI1_MASK -#define EXTI_FTSR2_BIT(n) STM32L4_EXTI2_BIT(n) /* 1=Falling trigger enabled (for Event and Interrupt) for input line */ -#define EXTI_FTSR2_SHIFT (0) /* Bits 0-X: Falling trigger event configuration bitfor all lines */ -#define EXTI_FTSR2_MASK STM32L4_EXTI2_MASK +#define EXTI_FTSR2_BIT(n) STM32_EXTI2_BIT(n) /* 1=Falling trigger enabled (for Event and Interrupt) for input line */ +#define EXTI_FTSR2_SHIFT (0) /* Bits 0-X: Falling trigger event configuration bitfor all lines */ +#define EXTI_FTSR2_MASK STM32_EXTI2_MASK /* Software interrupt event register */ -#define EXTI_SWIER1_BIT(n) STM32L4_EXTI1_BIT(n) /* 1=Sets the corresponding pending bit in EXTI_PR */ -#define EXTI_SWIER1_SHIFT (0) /* Bits 0-X: Software Interrupt for all lines */ -#define EXTI_SWIER1_MASK STM32L4_EXTI1_MASK +#define EXTI_SWIER1_BIT(n) STM32_EXTI1_BIT(n) /* 1=Sets the corresponding pending bit in EXTI_PR */ +#define EXTI_SWIER1_SHIFT (0) /* Bits 0-X: Software Interrupt for all lines */ +#define EXTI_SWIER1_MASK STM32_EXTI1_MASK -#define EXTI_SWIER2_BIT(n) STM32L4_EXTI2_BIT(n) /* 1=Sets the corresponding pending bit in EXTI_PR */ -#define EXTI_SWIER2_SHIFT (0) /* Bits 0-X: Software Interrupt for all lines */ -#define EXTI_SWIER2_MASK STM32L4_EXTI2_MASK +#define EXTI_SWIER2_BIT(n) STM32_EXTI2_BIT(n) /* 1=Sets the corresponding pending bit in EXTI_PR */ +#define EXTI_SWIER2_SHIFT (0) /* Bits 0-X: Software Interrupt for all lines */ +#define EXTI_SWIER2_MASK STM32_EXTI2_MASK /* Pending register */ -#define EXTI_PR1_BIT(n) STM32L4_EXTI1_BIT(n) /* 1=Selected trigger request occurred */ -#define EXTI_PR1_SHIFT (0) /* Bits 0-X: Pending bit for all lines */ -#define EXTI_PR1_MASK STM32L4_EXTI1_MASK +#define EXTI_PR1_BIT(n) STM32_EXTI1_BIT(n) /* 1=Selected trigger request occurred */ +#define EXTI_PR1_SHIFT (0) /* Bits 0-X: Pending bit for all lines */ +#define EXTI_PR1_MASK STM32_EXTI1_MASK -#define EXTI_PR2_BIT(n) STM32L4_EXTI2_BIT(n) /* 1=Selected trigger request occurred */ -#define EXTI_PR2_SHIFT (0) /* Bits 0-X: Pending bit for all lines */ -#define EXTI_PR2_MASK STM32L4_EXTI2_MASK +#define EXTI_PR2_BIT(n) STM32_EXTI2_BIT(n) /* 1=Selected trigger request occurred */ +#define EXTI_PR2_SHIFT (0) /* Bits 0-X: Pending bit for all lines */ +#define EXTI_PR2_MASK STM32_EXTI2_MASK -#endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_EXTI_H */ +#endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32_EXTI_H */ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4_flash.h b/arch/arm/src/stm32l4/hardware/stm32l4_flash.h index 8af1c073dc256..7a14fe18fb8dc 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4_flash.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4_flash.h @@ -35,10 +35,10 @@ /* Flash size is known from the chip selection: * - * When CONFIG_STM32L4_FLASH_OVERRIDE_DEFAULT is set the - * CONFIG_STM32L4_FLASH_CONFIG_x selects the default FLASH size based + * When CONFIG_STM32_FLASH_OVERRIDE_DEFAULT is set the + * CONFIG_STM32_FLASH_CONFIG_x selects the default FLASH size based * on the chip part number. This value can be overridden with - * CONFIG_STM32L4_FLASH_OVERRIDE_x. For example: + * CONFIG_STM32_FLASH_OVERRIDE_x. For example: * * Parts STM32L4xxE have 512Kb of FLASH * Parts STM32L4xxG have 1024Kb of FLASH @@ -47,10 +47,10 @@ * The STM32L4x5/STM32L4x6 devices have two banks, but on 512 and 256 Kb * devices an option byte is available to map all pages to the first bank. * - * The STM32L43x/44x/45x/46x chips (CONFIG_STM32L4_STM32L4X3) have a + * The STM32L43x/44x/45x/46x chips (CONFIG_STM32_STM32L4X3) have a * single bank only. * - * STM32L4+ devices (CONFIG_STM32L4_STM32L4XR) have single and dual bank + * STM32L4+ devices (CONFIG_STM32_STM32L4XR) have single and dual bank * operating modes. * * The STM32L4R/Sxx devices have 1 Mb or 2 Mb of flash @@ -69,123 +69,123 @@ #define _K(x) ((x)*1024) -#if !defined(CONFIG_STM32L4_FLASH_OVERRIDE_DEFAULT) && \ - !defined(CONFIG_STM32L4_FLASH_OVERRIDE_8) && \ - !defined(CONFIG_STM32L4_FLASH_OVERRIDE_B) && \ - !defined(CONFIG_STM32L4_FLASH_OVERRIDE_C) && \ - !defined(CONFIG_STM32L4_FLASH_OVERRIDE_E) && \ - !defined(CONFIG_STM32L4_FLASH_OVERRIDE_G) && \ - !defined(CONFIG_STM32L4_FLASH_OVERRIDE_I) && \ - !defined(CONFIG_STM32L4_FLASH_CONFIG_8) && \ - !defined(CONFIG_STM32L4_FLASH_CONFIG_B) && \ - !defined(CONFIG_STM32L4_FLASH_CONFIG_C) && \ - !defined(CONFIG_STM32L4_FLASH_CONFIG_E) && \ - !defined(CONFIG_STM32L4_FLASH_CONFIG_G) && \ - !defined(CONFIG_STM32L4_FLASH_CONFIG_I) -# define CONFIG_STM32L4_FLASH_OVERRIDE_E +#if !defined(CONFIG_STM32_FLASH_OVERRIDE_DEFAULT) && \ + !defined(CONFIG_STM32_FLASH_OVERRIDE_8) && \ + !defined(CONFIG_STM32_FLASH_OVERRIDE_B) && \ + !defined(CONFIG_STM32_FLASH_OVERRIDE_C) && \ + !defined(CONFIG_STM32_FLASH_OVERRIDE_E) && \ + !defined(CONFIG_STM32_FLASH_OVERRIDE_G) && \ + !defined(CONFIG_STM32_FLASH_OVERRIDE_I) && \ + !defined(CONFIG_STM32_FLASH_CONFIG_8) && \ + !defined(CONFIG_STM32_FLASH_CONFIG_B) && \ + !defined(CONFIG_STM32_FLASH_CONFIG_C) && \ + !defined(CONFIG_STM32_FLASH_CONFIG_E) && \ + !defined(CONFIG_STM32_FLASH_CONFIG_G) && \ + !defined(CONFIG_STM32_FLASH_CONFIG_I) +# define CONFIG_STM32_FLASH_OVERRIDE_E # warning "Flash size not defined defaulting to 512KiB (E)" #endif /* Override of the Flash has been chosen */ -#if !defined(CONFIG_STM32L4_FLASH_OVERRIDE_DEFAULT) -# undef CONFIG_STM32L4_FLASH_CONFIG_8 -# undef CONFIG_STM32L4_FLASH_CONFIG_B -# undef CONFIG_STM32L4_FLASH_CONFIG_C -# undef CONFIG_STM32L4_FLASH_CONFIG_E -# undef CONFIG_STM32L4_FLASH_CONFIG_G -# undef CONFIG_STM32L4_FLASH_CONFIG_I -# if defined(CONFIG_STM32L4_FLASH_OVERRIDE_8) -# define CONFIG_STM32L4_FLASH_CONFIG_8 -# elif defined(CONFIG_STM32L4_FLASH_OVERRIDE_B) -# define CONFIG_STM32L4_FLASH_CONFIG_B -# elif defined(CONFIG_STM32L4_FLASH_OVERRIDE_C) -# define CONFIG_STM32L4_FLASH_CONFIG_C -# elif defined(CONFIG_STM32L4_FLASH_OVERRIDE_E) -# define CONFIG_STM32L4_FLASH_CONFIG_E -# elif defined(CONFIG_STM32L4_FLASH_OVERRIDE_G) -# define CONFIG_STM32L4_FLASH_CONFIG_G -# elif defined(CONFIG_STM32L4_FLASH_OVERRIDE_I) -# define CONFIG_STM32L4_FLASH_CONFIG_I +#if !defined(CONFIG_STM32_FLASH_OVERRIDE_DEFAULT) +# undef CONFIG_STM32_FLASH_CONFIG_8 +# undef CONFIG_STM32_FLASH_CONFIG_B +# undef CONFIG_STM32_FLASH_CONFIG_C +# undef CONFIG_STM32_FLASH_CONFIG_E +# undef CONFIG_STM32_FLASH_CONFIG_G +# undef CONFIG_STM32_FLASH_CONFIG_I +# if defined(CONFIG_STM32_FLASH_OVERRIDE_8) +# define CONFIG_STM32_FLASH_CONFIG_8 +# elif defined(CONFIG_STM32_FLASH_OVERRIDE_B) +# define CONFIG_STM32_FLASH_CONFIG_B +# elif defined(CONFIG_STM32_FLASH_OVERRIDE_C) +# define CONFIG_STM32_FLASH_CONFIG_C +# elif defined(CONFIG_STM32_FLASH_OVERRIDE_E) +# define CONFIG_STM32_FLASH_CONFIG_E +# elif defined(CONFIG_STM32_FLASH_OVERRIDE_G) +# define CONFIG_STM32_FLASH_CONFIG_G +# elif defined(CONFIG_STM32_FLASH_OVERRIDE_I) +# define CONFIG_STM32_FLASH_CONFIG_I # endif #endif /* Define the valid configuration */ -#if defined(CONFIG_STM32L4_FLASH_CONFIG_8) /* 64 kB */ -# define STM32L4_FLASH_NPAGES 32 -# define STM32L4_FLASH_PAGESIZE 2048 -#elif defined(CONFIG_STM32L4_FLASH_CONFIG_B) /* 128 kB */ -# define STM32L4_FLASH_NPAGES 64 -# define STM32L4_FLASH_PAGESIZE 2048 -#elif defined(CONFIG_STM32L4_FLASH_CONFIG_C) /* 256 kB */ -# define STM32L4_FLASH_NPAGES 128 -# define STM32L4_FLASH_PAGESIZE 2048 -#elif defined(CONFIG_STM32L4_FLASH_CONFIG_E) /* 512 kB */ -# define STM32L4_FLASH_NPAGES 256 -# define STM32L4_FLASH_PAGESIZE 2048 -#elif defined(CONFIG_STM32L4_FLASH_CONFIG_G) /* 1 MB */ -# define STM32L4_FLASH_NPAGES 512 -# define STM32L4_FLASH_PAGESIZE 2048 -#elif defined(CONFIG_STM32L4_FLASH_CONFIG_I) /* 2 MB, STM32L4+ only */ -# define STM32L4_FLASH_NPAGES 512 -# define STM32L4_FLASH_PAGESIZE 4096 +#if defined(CONFIG_STM32_FLASH_CONFIG_8) /* 64 kB */ +# define STM32_FLASH_NPAGES 32 +# define STM32_FLASH_PAGESIZE 2048 +#elif defined(CONFIG_STM32_FLASH_CONFIG_B) /* 128 kB */ +# define STM32_FLASH_NPAGES 64 +# define STM32_FLASH_PAGESIZE 2048 +#elif defined(CONFIG_STM32_FLASH_CONFIG_C) /* 256 kB */ +# define STM32_FLASH_NPAGES 128 +# define STM32_FLASH_PAGESIZE 2048 +#elif defined(CONFIG_STM32_FLASH_CONFIG_E) /* 512 kB */ +# define STM32_FLASH_NPAGES 256 +# define STM32_FLASH_PAGESIZE 2048 +#elif defined(CONFIG_STM32_FLASH_CONFIG_G) /* 1 MB */ +# define STM32_FLASH_NPAGES 512 +# define STM32_FLASH_PAGESIZE 2048 +#elif defined(CONFIG_STM32_FLASH_CONFIG_I) /* 2 MB, STM32L4+ only */ +# define STM32_FLASH_NPAGES 512 +# define STM32_FLASH_PAGESIZE 4096 #else # error "unknown flash configuration!" #endif -#ifdef STM32L4_FLASH_PAGESIZE -# define STM32L4_FLASH_SIZE (STM32L4_FLASH_NPAGES * STM32L4_FLASH_PAGESIZE) +#ifdef STM32_FLASH_PAGESIZE +# define STM32_FLASH_SIZE (STM32_FLASH_NPAGES * STM32_FLASH_PAGESIZE) #endif /* Register Offsets *********************************************************/ -#define STM32L4_FLASH_ACR_OFFSET 0x0000 -#define STM32L4_FLASH_PDKEYR_OFFSET 0x0004 -#define STM32L4_FLASH_KEYR_OFFSET 0x0008 -#define STM32L4_FLASH_OPTKEYR_OFFSET 0x000c -#define STM32L4_FLASH_SR_OFFSET 0x0010 -#define STM32L4_FLASH_CR_OFFSET 0x0014 -#define STM32L4_FLASH_ECCR_OFFSET 0x0018 -#define STM32L4_FLASH_OPTR_OFFSET 0x0020 -#define STM32L4_FLASH_PCROP1SR_OFFSET 0x0024 -#define STM32L4_FLASH_PCROP1ER_OFFSET 0x0028 -#define STM32L4_FLASH_WRP1AR_OFFSET 0x002c -#define STM32L4_FLASH_WRP1BR_OFFSET 0x0030 -#if defined(CONFIG_STM32L4_STM32L4X5) || defined(CONFIG_STM32L4_STM32L4X6) || \ - defined(CONFIG_STM32L4_STM32L4XR) -# define STM32L4_FLASH_PCROP2SR_OFFSET 0x0044 -# define STM32L4_FLASH_PCROP2ER_OFFSET 0x0048 -# define STM32L4_FLASH_WRP2AR_OFFSET 0x004c -# define STM32L4_FLASH_WRP2BR_OFFSET 0x0050 +#define STM32_FLASH_ACR_OFFSET 0x0000 +#define STM32_FLASH_PDKEYR_OFFSET 0x0004 +#define STM32_FLASH_KEYR_OFFSET 0x0008 +#define STM32_FLASH_OPTKEYR_OFFSET 0x000c +#define STM32_FLASH_SR_OFFSET 0x0010 +#define STM32_FLASH_CR_OFFSET 0x0014 +#define STM32_FLASH_ECCR_OFFSET 0x0018 +#define STM32_FLASH_OPTR_OFFSET 0x0020 +#define STM32_FLASH_PCROP1SR_OFFSET 0x0024 +#define STM32_FLASH_PCROP1ER_OFFSET 0x0028 +#define STM32_FLASH_WRP1AR_OFFSET 0x002c +#define STM32_FLASH_WRP1BR_OFFSET 0x0030 +#if defined(CONFIG_STM32_STM32L4X5) || defined(CONFIG_STM32_STM32L4X6) || \ + defined(CONFIG_STM32_STM32L4XR) +# define STM32_FLASH_PCROP2SR_OFFSET 0x0044 +# define STM32_FLASH_PCROP2ER_OFFSET 0x0048 +# define STM32_FLASH_WRP2AR_OFFSET 0x004c +# define STM32_FLASH_WRP2BR_OFFSET 0x0050 #endif -#if defined(CONFIG_STM32L4_STM32L4XR) -# define STM32L4_FLASH_CFGR_OFFSET 0x0130 +#if defined(CONFIG_STM32_STM32L4XR) +# define STM32_FLASH_CFGR_OFFSET 0x0130 #endif /* Register Addresses *******************************************************/ -#define STM32L4_FLASH_ACR (STM32L4_FLASHIF_BASE+STM32L4_FLASH_ACR_OFFSET) -#define STM32L4_FLASH_PDKEYR (STM32L4_FLASHIF_BASE+STM32L4_FLASH_PDKEYR_OFFSET) -#define STM32L4_FLASH_KEYR (STM32L4_FLASHIF_BASE+STM32L4_FLASH_KEYR_OFFSET) -#define STM32L4_FLASH_OPTKEYR (STM32L4_FLASHIF_BASE+STM32L4_FLASH_OPTKEYR_OFFSET) -#define STM32L4_FLASH_SR (STM32L4_FLASHIF_BASE+STM32L4_FLASH_SR_OFFSET) -#define STM32L4_FLASH_CR (STM32L4_FLASHIF_BASE+STM32L4_FLASH_CR_OFFSET) -#define STM32L4_FLASH_ECCR (STM32L4_FLASHIF_BASE+STM32L4_FLASH_ECCR_OFFSET) -#define STM32L4_FLASH_OPTR (STM32L4_FLASHIF_BASE+STM32L4_FLASH_OPTR_OFFSET) -#define STM32L4_FLASH_PCROP1SR (STM32L4_FLASHIF_BASE+STM32L4_FLASH_PCROP1SR_OFFSET) -#define STM32L4_FLASH_PCROP1ER (STM32L4_FLASHIF_BASE+STM32L4_FLASH_PCROP1ER_OFFSET) -#define STM32L4_FLASH_WRP1AR (STM32L4_FLASHIF_BASE+STM32L4_FLASH_WRP1AR_OFFSET) -#define STM32L4_FLASH_WRP1BR (STM32L4_FLASHIF_BASE+STM32L4_FLASH_WRP1BR_OFFSET) -#if defined(CONFIG_STM32L4_STM32L4X5) || defined(CONFIG_STM32L4_STM32L4X6) || \ - defined(CONFIG_STM32L4_STM32L4XR) -# define STM32L4_FLASH_PCROP2SR (STM32L4_FLASHIF_BASE+STM32L4_FLASH_PCROP2SR_OFFSET) -# define STM32L4_FLASH_PCROP2ER (STM32L4_FLASHIF_BASE+STM32L4_FLASH_PCROP2ER_OFFSET) -# define STM32L4_FLASH_WRP2AR (STM32L4_FLASHIF_BASE+STM32L4_FLASH_WRP2AR_OFFSET) -# define STM32L4_FLASH_WRP2BR (STM32L4_FLASHIF_BASE+STM32L4_FLASH_WRP2BR_OFFSET) +#define STM32_FLASH_ACR (STM32_FLASHIF_BASE+STM32_FLASH_ACR_OFFSET) +#define STM32_FLASH_PDKEYR (STM32_FLASHIF_BASE+STM32_FLASH_PDKEYR_OFFSET) +#define STM32_FLASH_KEYR (STM32_FLASHIF_BASE+STM32_FLASH_KEYR_OFFSET) +#define STM32_FLASH_OPTKEYR (STM32_FLASHIF_BASE+STM32_FLASH_OPTKEYR_OFFSET) +#define STM32_FLASH_SR (STM32_FLASHIF_BASE+STM32_FLASH_SR_OFFSET) +#define STM32_FLASH_CR (STM32_FLASHIF_BASE+STM32_FLASH_CR_OFFSET) +#define STM32_FLASH_ECCR (STM32_FLASHIF_BASE+STM32_FLASH_ECCR_OFFSET) +#define STM32_FLASH_OPTR (STM32_FLASHIF_BASE+STM32_FLASH_OPTR_OFFSET) +#define STM32_FLASH_PCROP1SR (STM32_FLASHIF_BASE+STM32_FLASH_PCROP1SR_OFFSET) +#define STM32_FLASH_PCROP1ER (STM32_FLASHIF_BASE+STM32_FLASH_PCROP1ER_OFFSET) +#define STM32_FLASH_WRP1AR (STM32_FLASHIF_BASE+STM32_FLASH_WRP1AR_OFFSET) +#define STM32_FLASH_WRP1BR (STM32_FLASHIF_BASE+STM32_FLASH_WRP1BR_OFFSET) +#if defined(CONFIG_STM32_STM32L4X5) || defined(CONFIG_STM32_STM32L4X6) || \ + defined(CONFIG_STM32_STM32L4XR) +# define STM32_FLASH_PCROP2SR (STM32_FLASHIF_BASE+STM32_FLASH_PCROP2SR_OFFSET) +# define STM32_FLASH_PCROP2ER (STM32_FLASHIF_BASE+STM32_FLASH_PCROP2ER_OFFSET) +# define STM32_FLASH_WRP2AR (STM32_FLASHIF_BASE+STM32_FLASH_WRP2AR_OFFSET) +# define STM32_FLASH_WRP2BR (STM32_FLASHIF_BASE+STM32_FLASH_WRP2BR_OFFSET) #endif -#if defined(CONFIG_STM32L4_STM32L4XR) -# define STM32L4_FLASH_CFGR (STM32L4_FLASHIF_BASE+STM32L4_FLASH_CFGR_OFFSET) +#if defined(CONFIG_STM32_STM32L4XR) +# define STM32_FLASH_CFGR (STM32_FLASHIF_BASE+STM32_FLASH_CFGR_OFFSET) #endif /* Register Bitfield Definitions ********************************************/ @@ -224,7 +224,7 @@ #define FLASH_SR_RDERR (1 << 14) /* Bit 14: PCROP read error */ #define FLASH_SR_OPTVERR (1 << 15) /* Bit 15: Option validity error */ #define FLASH_SR_BSY (1 << 16) /* Bit 16: Busy */ -#if defined(CONFIG_STM32L4_STM32L4X3) || defined(CONFIG_STM32L4_STM32L4XR) +#if defined(CONFIG_STM32_STM32L4X3) || defined(CONFIG_STM32_STM32L4XR) # define FLASH_SR_PEMPTY (1 << 17) /* Bit 17: Program empty */ #endif @@ -238,8 +238,8 @@ #define FLASH_CR_PNB_MASK (0xFF << FLASH_CR_PNB_SHIFT) #define FLASH_CR_PNB(n) ((n) << FLASH_CR_PNB_SHIFT) /* Page n (if BKER=0) or n+256 (if BKER=1), n=0..255 */ -#if defined(CONFIG_STM32L4_STM32L4X5) || defined(CONFIG_STM32L4_STM32L4X6) || \ - defined(CONFIG_STM32L4_STM32L4XR) +#if defined(CONFIG_STM32_STM32L4X5) || defined(CONFIG_STM32_STM32L4X6) || \ + defined(CONFIG_STM32_STM32L4XR) # define FLASH_CR_BKER (1 << 11) /* Bit 11: Page number MSB (Bank selection) */ # define FLASH_CR_MER2 (1 << 15) /* Bit 15: Mass Erase Bank 2 */ #endif @@ -257,8 +257,8 @@ #define FLASH_ECCR_ADDR_ECC_SHIFT (0) /* Bits 0-18: ECC fail address */ #define FLASH_ECCR_ADDR_ECC_MASK (0x07ffff << FLASH_ECCR_ADDR_ECC_SHIFT) -#if defined(CONFIG_STM32L4_STM32L4X5) || defined(CONFIG_STM32L4_STM32L4X6) || \ - defined(CONFIG_STM32L4_STM32L4XR) +#if defined(CONFIG_STM32_STM32L4X5) || defined(CONFIG_STM32_STM32L4X6) || \ + defined(CONFIG_STM32_STM32L4XR) # define FLASH_ECCR_BK_ECC (1 << 19) /* Bit 19: ECC fail bank */ #endif #define FLASH_ECCR_SYSF_ECC (1 << 20) /* Bit 20: System Flash ECC fail */ @@ -275,19 +275,19 @@ #define FLASH_OPTCR_IWDG_STOP (1 << 17) /* Bit 17: Independent watchdog counter freeze in Stop mode */ #define FLASH_OPTCR_IWDG_STDBY (1 << 18) /* Bit 18: Independent watchdog counter freeze in Standby mode*/ #define FLASH_OPTCR_WWDG_SW (1 << 19) /* Bit 19: Window watchdog selection */ -#if defined(CONFIG_STM32L4_STM32L4X5) || defined(CONFIG_STM32L4_STM32L4X6) || \ - defined(CONFIG_STM32L4_STM32L4XR) +#if defined(CONFIG_STM32_STM32L4X5) || defined(CONFIG_STM32_STM32L4X6) || \ + defined(CONFIG_STM32_STM32L4XR) # define FLASH_OPTCR_BFB2 (1 << 20) /* Bit 20: Dual bank boot */ # define FLASH_OPTCR_DUALBANK (1 << 21) /* Bit 21: Dual bank enable */ #endif -#if defined(CONFIG_STM32L4_STM32L4XR) +#if defined(CONFIG_STM32_STM32L4XR) # define FLASH_OPTCR_DBANK (1 << 22) /* Bit 22: Dual bank mode for 2MB devices */ #endif #define FLASH_OPTCR_NBOOT1 (1 << 23) /* Bit 23: Boot configuration */ #define FLASH_OPTCR_SRAM2_PE (1 << 24) /* Bit 24: SRAM2 parity check enable */ #define FLASH_OPTCR_SRAM2_RST (1 << 25) /* Bit 25: SRAM2 Erase when system reset */ -#if defined(CONFIG_STM32L4_STM32L4X3) || defined(CONFIG_STM32L4_STM32L496XX) || \ - defined(CONFIG_STM32L4_STM32L4XR) +#if defined(CONFIG_STM32_STM32L4X3) || defined(CONFIG_STM32_STM32L496XX) || \ + defined(CONFIG_STM32_STM32L4XR) # define FLASH_OPTCR_NSWBOOT0 (1 << 26) /* Bit 26: Software BOOT0 */ # define FLASH_OPTCR_NBOOT0 (1 << 27) /* Bit 27: nBOOT0 option bit */ #endif @@ -307,7 +307,7 @@ /* Flash Configuration Register (CFGR) */ -#if defined(CONFIG_STM32L4_STM32L4XR) +#if defined(CONFIG_STM32_STM32L4XR) # define FLASH_CFGR_LVEN (1 << 0) /* Bit 0: Low voltage enable */ #endif diff --git a/arch/arm/src/stm32l4/hardware/stm32l4_gpio.h b/arch/arm/src/stm32l4/hardware/stm32l4_gpio.h index 8938d7d983c51..ca1b423d48d16 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4_gpio.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4_gpio.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_GPIO_H -#define __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_GPIO_H +#ifndef __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32_GPIO_H +#define __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32_GPIO_H /**************************************************************************** * Included Files @@ -36,154 +36,154 @@ /* Register Offsets *********************************************************/ -#define STM32L4_GPIO_MODER_OFFSET 0x0000 /* GPIO port mode register */ -#define STM32L4_GPIO_OTYPER_OFFSET 0x0004 /* GPIO port output type register */ -#define STM32L4_GPIO_OSPEED_OFFSET 0x0008 /* GPIO port output speed register */ -#define STM32L4_GPIO_PUPDR_OFFSET 0x000c /* GPIO port pull-up/pull-down register */ -#define STM32L4_GPIO_IDR_OFFSET 0x0010 /* GPIO port input data register */ -#define STM32L4_GPIO_ODR_OFFSET 0x0014 /* GPIO port output data register */ -#define STM32L4_GPIO_BSRR_OFFSET 0x0018 /* GPIO port bit set/reset register */ -#define STM32L4_GPIO_LCKR_OFFSET 0x001c /* GPIO port configuration lock register */ -#define STM32L4_GPIO_AFRL_OFFSET 0x0020 /* GPIO alternate function low register */ -#define STM32L4_GPIO_AFRH_OFFSET 0x0024 /* GPIO alternate function high register */ -#define STM32L4_GPIO_BRR_OFFSET 0x0028 /* GPIO port bit reset register */ -#define STM32L4_GPIO_ASCR_OFFSET 0x002c /* GPIO port analog switch control register */ +#define STM32_GPIO_MODER_OFFSET 0x0000 /* GPIO port mode register */ +#define STM32_GPIO_OTYPER_OFFSET 0x0004 /* GPIO port output type register */ +#define STM32_GPIO_OSPEED_OFFSET 0x0008 /* GPIO port output speed register */ +#define STM32_GPIO_PUPDR_OFFSET 0x000c /* GPIO port pull-up/pull-down register */ +#define STM32_GPIO_IDR_OFFSET 0x0010 /* GPIO port input data register */ +#define STM32_GPIO_ODR_OFFSET 0x0014 /* GPIO port output data register */ +#define STM32_GPIO_BSRR_OFFSET 0x0018 /* GPIO port bit set/reset register */ +#define STM32_GPIO_LCKR_OFFSET 0x001c /* GPIO port configuration lock register */ +#define STM32_GPIO_AFRL_OFFSET 0x0020 /* GPIO alternate function low register */ +#define STM32_GPIO_AFRH_OFFSET 0x0024 /* GPIO alternate function high register */ +#define STM32_GPIO_BRR_OFFSET 0x0028 /* GPIO port bit reset register */ +#define STM32_GPIO_ASCR_OFFSET 0x002c /* GPIO port analog switch control register */ /* Register Addresses *******************************************************/ -#if STM32L4_NPORTS > 0 -# define STM32L4_GPIOA_MODER (STM32L4_GPIOA_BASE+STM32L4_GPIO_MODER_OFFSET) -# define STM32L4_GPIOA_OTYPER (STM32L4_GPIOA_BASE+STM32L4_GPIO_OTYPER_OFFSET) -# define STM32L4_GPIOA_OSPEED (STM32L4_GPIOA_BASE+STM32L4_GPIO_OSPEED_OFFSET) -# define STM32L4_GPIOA_PUPDR (STM32L4_GPIOA_BASE+STM32L4_GPIO_PUPDR_OFFSET) -# define STM32L4_GPIOA_IDR (STM32L4_GPIOA_BASE+STM32L4_GPIO_IDR_OFFSET) -# define STM32L4_GPIOA_ODR (STM32L4_GPIOA_BASE+STM32L4_GPIO_ODR_OFFSET) -# define STM32L4_GPIOA_BSRR (STM32L4_GPIOA_BASE+STM32L4_GPIO_BSRR_OFFSET) -# define STM32L4_GPIOA_LCKR (STM32L4_GPIOA_BASE+STM32L4_GPIO_LCKR_OFFSET) -# define STM32L4_GPIOA_AFRL (STM32L4_GPIOA_BASE+STM32L4_GPIO_AFRL_OFFSET) -# define STM32L4_GPIOA_AFRH (STM32L4_GPIOA_BASE+STM32L4_GPIO_AFRH_OFFSET) -# define STM32L4_GPIOA_BRR (STM32L4_GPIOA_BASE+STM32L4_GPIO_BRR_OFFSET) -# define STM32L4_GPIOA_ASCR (STM32L4_GPIOA_BASE+STM32L4_GPIO_ASCR_OFFSET) +#if STM32_NPORTS > 0 +# define STM32_GPIOA_MODER (STM32_GPIOA_BASE+STM32_GPIO_MODER_OFFSET) +# define STM32_GPIOA_OTYPER (STM32_GPIOA_BASE+STM32_GPIO_OTYPER_OFFSET) +# define STM32_GPIOA_OSPEED (STM32_GPIOA_BASE+STM32_GPIO_OSPEED_OFFSET) +# define STM32_GPIOA_PUPDR (STM32_GPIOA_BASE+STM32_GPIO_PUPDR_OFFSET) +# define STM32_GPIOA_IDR (STM32_GPIOA_BASE+STM32_GPIO_IDR_OFFSET) +# define STM32_GPIOA_ODR (STM32_GPIOA_BASE+STM32_GPIO_ODR_OFFSET) +# define STM32_GPIOA_BSRR (STM32_GPIOA_BASE+STM32_GPIO_BSRR_OFFSET) +# define STM32_GPIOA_LCKR (STM32_GPIOA_BASE+STM32_GPIO_LCKR_OFFSET) +# define STM32_GPIOA_AFRL (STM32_GPIOA_BASE+STM32_GPIO_AFRL_OFFSET) +# define STM32_GPIOA_AFRH (STM32_GPIOA_BASE+STM32_GPIO_AFRH_OFFSET) +# define STM32_GPIOA_BRR (STM32_GPIOA_BASE+STM32_GPIO_BRR_OFFSET) +# define STM32_GPIOA_ASCR (STM32_GPIOA_BASE+STM32_GPIO_ASCR_OFFSET) #endif -#if STM32L4_NPORTS > 1 -# define STM32L4_GPIOB_MODER (STM32L4_GPIOB_BASE+STM32L4_GPIO_MODER_OFFSET) -# define STM32L4_GPIOB_OTYPER (STM32L4_GPIOB_BASE+STM32L4_GPIO_OTYPER_OFFSET) -# define STM32L4_GPIOB_OSPEED (STM32L4_GPIOB_BASE+STM32L4_GPIO_OSPEED_OFFSET) -# define STM32L4_GPIOB_PUPDR (STM32L4_GPIOB_BASE+STM32L4_GPIO_PUPDR_OFFSET) -# define STM32L4_GPIOB_IDR (STM32L4_GPIOB_BASE+STM32L4_GPIO_IDR_OFFSET) -# define STM32L4_GPIOB_ODR (STM32L4_GPIOB_BASE+STM32L4_GPIO_ODR_OFFSET) -# define STM32L4_GPIOB_BSRR (STM32L4_GPIOB_BASE+STM32L4_GPIO_BSRR_OFFSET) -# define STM32L4_GPIOB_LCKR (STM32L4_GPIOB_BASE+STM32L4_GPIO_LCKR_OFFSET) -# define STM32L4_GPIOB_AFRL (STM32L4_GPIOB_BASE+STM32L4_GPIO_AFRL_OFFSET) -# define STM32L4_GPIOB_AFRH (STM32L4_GPIOB_BASE+STM32L4_GPIO_AFRH_OFFSET) -# define STM32L4_GPIOB_BRR (STM32L4_GPIOB_BASE+STM32L4_GPIO_BRR_OFFSET) -# define STM32L4_GPIOB_ASCR (STM32L4_GPIOB_BASE+STM32L4_GPIO_ASCR_OFFSET) +#if STM32_NPORTS > 1 +# define STM32_GPIOB_MODER (STM32_GPIOB_BASE+STM32_GPIO_MODER_OFFSET) +# define STM32_GPIOB_OTYPER (STM32_GPIOB_BASE+STM32_GPIO_OTYPER_OFFSET) +# define STM32_GPIOB_OSPEED (STM32_GPIOB_BASE+STM32_GPIO_OSPEED_OFFSET) +# define STM32_GPIOB_PUPDR (STM32_GPIOB_BASE+STM32_GPIO_PUPDR_OFFSET) +# define STM32_GPIOB_IDR (STM32_GPIOB_BASE+STM32_GPIO_IDR_OFFSET) +# define STM32_GPIOB_ODR (STM32_GPIOB_BASE+STM32_GPIO_ODR_OFFSET) +# define STM32_GPIOB_BSRR (STM32_GPIOB_BASE+STM32_GPIO_BSRR_OFFSET) +# define STM32_GPIOB_LCKR (STM32_GPIOB_BASE+STM32_GPIO_LCKR_OFFSET) +# define STM32_GPIOB_AFRL (STM32_GPIOB_BASE+STM32_GPIO_AFRL_OFFSET) +# define STM32_GPIOB_AFRH (STM32_GPIOB_BASE+STM32_GPIO_AFRH_OFFSET) +# define STM32_GPIOB_BRR (STM32_GPIOB_BASE+STM32_GPIO_BRR_OFFSET) +# define STM32_GPIOB_ASCR (STM32_GPIOB_BASE+STM32_GPIO_ASCR_OFFSET) #endif -#if STM32L4_NPORTS > 2 -# define STM32L4_GPIOC_MODER (STM32L4_GPIOC_BASE+STM32L4_GPIO_MODER_OFFSET) -# define STM32L4_GPIOC_OTYPER (STM32L4_GPIOC_BASE+STM32L4_GPIO_OTYPER_OFFSET) -# define STM32L4_GPIOC_OSPEED (STM32L4_GPIOC_BASE+STM32L4_GPIO_OSPEED_OFFSET) -# define STM32L4_GPIOC_PUPDR (STM32L4_GPIOC_BASE+STM32L4_GPIO_PUPDR_OFFSET) -# define STM32L4_GPIOC_IDR (STM32L4_GPIOC_BASE+STM32L4_GPIO_IDR_OFFSET) -# define STM32L4_GPIOC_ODR (STM32L4_GPIOC_BASE+STM32L4_GPIO_ODR_OFFSET) -# define STM32L4_GPIOC_BSRR (STM32L4_GPIOC_BASE+STM32L4_GPIO_BSRR_OFFSET) -# define STM32L4_GPIOC_LCKR (STM32L4_GPIOC_BASE+STM32L4_GPIO_LCKR_OFFSET) -# define STM32L4_GPIOC_AFRL (STM32L4_GPIOC_BASE+STM32L4_GPIO_AFRL_OFFSET) -# define STM32L4_GPIOC_AFRH (STM32L4_GPIOC_BASE+STM32L4_GPIO_AFRH_OFFSET) -# define STM32L4_GPIOC_BRR (STM32L4_GPIOC_BASE+STM32L4_GPIO_BRR_OFFSET) -# define STM32L4_GPIOC_ASCR (STM32L4_GPIOC_BASE+STM32L4_GPIO_ASCR_OFFSET) +#if STM32_NPORTS > 2 +# define STM32_GPIOC_MODER (STM32_GPIOC_BASE+STM32_GPIO_MODER_OFFSET) +# define STM32_GPIOC_OTYPER (STM32_GPIOC_BASE+STM32_GPIO_OTYPER_OFFSET) +# define STM32_GPIOC_OSPEED (STM32_GPIOC_BASE+STM32_GPIO_OSPEED_OFFSET) +# define STM32_GPIOC_PUPDR (STM32_GPIOC_BASE+STM32_GPIO_PUPDR_OFFSET) +# define STM32_GPIOC_IDR (STM32_GPIOC_BASE+STM32_GPIO_IDR_OFFSET) +# define STM32_GPIOC_ODR (STM32_GPIOC_BASE+STM32_GPIO_ODR_OFFSET) +# define STM32_GPIOC_BSRR (STM32_GPIOC_BASE+STM32_GPIO_BSRR_OFFSET) +# define STM32_GPIOC_LCKR (STM32_GPIOC_BASE+STM32_GPIO_LCKR_OFFSET) +# define STM32_GPIOC_AFRL (STM32_GPIOC_BASE+STM32_GPIO_AFRL_OFFSET) +# define STM32_GPIOC_AFRH (STM32_GPIOC_BASE+STM32_GPIO_AFRH_OFFSET) +# define STM32_GPIOC_BRR (STM32_GPIOC_BASE+STM32_GPIO_BRR_OFFSET) +# define STM32_GPIOC_ASCR (STM32_GPIOC_BASE+STM32_GPIO_ASCR_OFFSET) #endif -#if STM32L4_NPORTS > 3 -# define STM32L4_GPIOD_MODER (STM32L4_GPIOD_BASE+STM32L4_GPIO_MODER_OFFSET) -# define STM32L4_GPIOD_OTYPER (STM32L4_GPIOD_BASE+STM32L4_GPIO_OTYPER_OFFSET) -# define STM32L4_GPIOD_OSPEED (STM32L4_GPIOD_BASE+STM32L4_GPIO_OSPEED_OFFSET) -# define STM32L4_GPIOD_PUPDR (STM32L4_GPIOD_BASE+STM32L4_GPIO_PUPDR_OFFSET) -# define STM32L4_GPIOD_IDR (STM32L4_GPIOD_BASE+STM32L4_GPIO_IDR_OFFSET) -# define STM32L4_GPIOD_ODR (STM32L4_GPIOD_BASE+STM32L4_GPIO_ODR_OFFSET) -# define STM32L4_GPIOD_BSRR (STM32L4_GPIOD_BASE+STM32L4_GPIO_BSRR_OFFSET) -# define STM32L4_GPIOD_LCKR (STM32L4_GPIOD_BASE+STM32L4_GPIO_LCKR_OFFSET) -# define STM32L4_GPIOD_AFRL (STM32L4_GPIOD_BASE+STM32L4_GPIO_AFRL_OFFSET) -# define STM32L4_GPIOD_AFRH (STM32L4_GPIOD_BASE+STM32L4_GPIO_AFRH_OFFSET) -# define STM32L4_GPIOD_BRR (STM32L4_GPIOD_BASE+STM32L4_GPIO_BRR_OFFSET) -# define STM32L4_GPIOD_ASCR (STM32L4_GPIOD_BASE+STM32L4_GPIO_ASCR_OFFSET) +#if STM32_NPORTS > 3 +# define STM32_GPIOD_MODER (STM32_GPIOD_BASE+STM32_GPIO_MODER_OFFSET) +# define STM32_GPIOD_OTYPER (STM32_GPIOD_BASE+STM32_GPIO_OTYPER_OFFSET) +# define STM32_GPIOD_OSPEED (STM32_GPIOD_BASE+STM32_GPIO_OSPEED_OFFSET) +# define STM32_GPIOD_PUPDR (STM32_GPIOD_BASE+STM32_GPIO_PUPDR_OFFSET) +# define STM32_GPIOD_IDR (STM32_GPIOD_BASE+STM32_GPIO_IDR_OFFSET) +# define STM32_GPIOD_ODR (STM32_GPIOD_BASE+STM32_GPIO_ODR_OFFSET) +# define STM32_GPIOD_BSRR (STM32_GPIOD_BASE+STM32_GPIO_BSRR_OFFSET) +# define STM32_GPIOD_LCKR (STM32_GPIOD_BASE+STM32_GPIO_LCKR_OFFSET) +# define STM32_GPIOD_AFRL (STM32_GPIOD_BASE+STM32_GPIO_AFRL_OFFSET) +# define STM32_GPIOD_AFRH (STM32_GPIOD_BASE+STM32_GPIO_AFRH_OFFSET) +# define STM32_GPIOD_BRR (STM32_GPIOD_BASE+STM32_GPIO_BRR_OFFSET) +# define STM32_GPIOD_ASCR (STM32_GPIOD_BASE+STM32_GPIO_ASCR_OFFSET) #endif -#if STM32L4_NPORTS > 4 -# define STM32L4_GPIOE_MODER (STM32L4_GPIOE_BASE+STM32L4_GPIO_MODER_OFFSET) -# define STM32L4_GPIOE_OTYPER (STM32L4_GPIOE_BASE+STM32L4_GPIO_OTYPER_OFFSET) -# define STM32L4_GPIOE_OSPEED (STM32L4_GPIOE_BASE+STM32L4_GPIO_OSPEED_OFFSET) -# define STM32L4_GPIOE_PUPDR (STM32L4_GPIOE_BASE+STM32L4_GPIO_PUPDR_OFFSET) -# define STM32L4_GPIOE_IDR (STM32L4_GPIOE_BASE+STM32L4_GPIO_IDR_OFFSET) -# define STM32L4_GPIOE_ODR (STM32L4_GPIOE_BASE+STM32L4_GPIO_ODR_OFFSET) -# define STM32L4_GPIOE_BSRR (STM32L4_GPIOE_BASE+STM32L4_GPIO_BSRR_OFFSET) -# define STM32L4_GPIOE_LCKR (STM32L4_GPIOE_BASE+STM32L4_GPIO_LCKR_OFFSET) -# define STM32L4_GPIOE_AFRL (STM32L4_GPIOE_BASE+STM32L4_GPIO_AFRL_OFFSET) -# define STM32L4_GPIOE_AFRH (STM32L4_GPIOE_BASE+STM32L4_GPIO_AFRH_OFFSET) -# define STM32L4_GPIOE_BRR (STM32L4_GPIOE_BASE+STM32L4_GPIO_BRR_OFFSET) -# define STM32L4_GPIOE_ASCR (STM32L4_GPIOE_BASE+STM32L4_GPIO_ASCR_OFFSET) +#if STM32_NPORTS > 4 +# define STM32_GPIOE_MODER (STM32_GPIOE_BASE+STM32_GPIO_MODER_OFFSET) +# define STM32_GPIOE_OTYPER (STM32_GPIOE_BASE+STM32_GPIO_OTYPER_OFFSET) +# define STM32_GPIOE_OSPEED (STM32_GPIOE_BASE+STM32_GPIO_OSPEED_OFFSET) +# define STM32_GPIOE_PUPDR (STM32_GPIOE_BASE+STM32_GPIO_PUPDR_OFFSET) +# define STM32_GPIOE_IDR (STM32_GPIOE_BASE+STM32_GPIO_IDR_OFFSET) +# define STM32_GPIOE_ODR (STM32_GPIOE_BASE+STM32_GPIO_ODR_OFFSET) +# define STM32_GPIOE_BSRR (STM32_GPIOE_BASE+STM32_GPIO_BSRR_OFFSET) +# define STM32_GPIOE_LCKR (STM32_GPIOE_BASE+STM32_GPIO_LCKR_OFFSET) +# define STM32_GPIOE_AFRL (STM32_GPIOE_BASE+STM32_GPIO_AFRL_OFFSET) +# define STM32_GPIOE_AFRH (STM32_GPIOE_BASE+STM32_GPIO_AFRH_OFFSET) +# define STM32_GPIOE_BRR (STM32_GPIOE_BASE+STM32_GPIO_BRR_OFFSET) +# define STM32_GPIOE_ASCR (STM32_GPIOE_BASE+STM32_GPIO_ASCR_OFFSET) #endif -#if STM32L4_NPORTS > 5 -# define STM32L4_GPIOF_MODER (STM32L4_GPIOF_BASE+STM32L4_GPIO_MODER_OFFSET) -# define STM32L4_GPIOF_OTYPER (STM32L4_GPIOF_BASE+STM32L4_GPIO_OTYPER_OFFSET) -# define STM32L4_GPIOF_OSPEED (STM32L4_GPIOF_BASE+STM32L4_GPIO_OSPEED_OFFSET) -# define STM32L4_GPIOF_PUPDR (STM32L4_GPIOF_BASE+STM32L4_GPIO_PUPDR_OFFSET) -# define STM32L4_GPIOF_IDR (STM32L4_GPIOF_BASE+STM32L4_GPIO_IDR_OFFSET) -# define STM32L4_GPIOF_ODR (STM32L4_GPIOF_BASE+STM32L4_GPIO_ODR_OFFSET) -# define STM32L4_GPIOF_BSRR (STM32L4_GPIOF_BASE+STM32L4_GPIO_BSRR_OFFSET) -# define STM32L4_GPIOF_LCKR (STM32L4_GPIOF_BASE+STM32L4_GPIO_LCKR_OFFSET) -# define STM32L4_GPIOF_AFRL (STM32L4_GPIOF_BASE+STM32L4_GPIO_AFRL_OFFSET) -# define STM32L4_GPIOF_AFRH (STM32L4_GPIOF_BASE+STM32L4_GPIO_AFRH_OFFSET) -# define STM32L4_GPIOF_BRR (STM32L4_GPIOF_BASE+STM32L4_GPIO_BRR_OFFSET) -# define STM32L4_GPIOF_ASCR (STM32L4_GPIOF_BASE+STM32L4_GPIO_ASCR_OFFSET) +#if STM32_NPORTS > 5 +# define STM32_GPIOF_MODER (STM32_GPIOF_BASE+STM32_GPIO_MODER_OFFSET) +# define STM32_GPIOF_OTYPER (STM32_GPIOF_BASE+STM32_GPIO_OTYPER_OFFSET) +# define STM32_GPIOF_OSPEED (STM32_GPIOF_BASE+STM32_GPIO_OSPEED_OFFSET) +# define STM32_GPIOF_PUPDR (STM32_GPIOF_BASE+STM32_GPIO_PUPDR_OFFSET) +# define STM32_GPIOF_IDR (STM32_GPIOF_BASE+STM32_GPIO_IDR_OFFSET) +# define STM32_GPIOF_ODR (STM32_GPIOF_BASE+STM32_GPIO_ODR_OFFSET) +# define STM32_GPIOF_BSRR (STM32_GPIOF_BASE+STM32_GPIO_BSRR_OFFSET) +# define STM32_GPIOF_LCKR (STM32_GPIOF_BASE+STM32_GPIO_LCKR_OFFSET) +# define STM32_GPIOF_AFRL (STM32_GPIOF_BASE+STM32_GPIO_AFRL_OFFSET) +# define STM32_GPIOF_AFRH (STM32_GPIOF_BASE+STM32_GPIO_AFRH_OFFSET) +# define STM32_GPIOF_BRR (STM32_GPIOF_BASE+STM32_GPIO_BRR_OFFSET) +# define STM32_GPIOF_ASCR (STM32_GPIOF_BASE+STM32_GPIO_ASCR_OFFSET) #endif -#if STM32L4_NPORTS > 6 -# define STM32L4_GPIOG_MODER (STM32L4_GPIOG_BASE+STM32L4_GPIO_MODER_OFFSET) -# define STM32L4_GPIOG_OTYPER (STM32L4_GPIOG_BASE+STM32L4_GPIO_OTYPER_OFFSET) -# define STM32L4_GPIOG_OSPEED (STM32L4_GPIOG_BASE+STM32L4_GPIO_OSPEED_OFFSET) -# define STM32L4_GPIOG_PUPDR (STM32L4_GPIOG_BASE+STM32L4_GPIO_PUPDR_OFFSET) -# define STM32L4_GPIOG_IDR (STM32L4_GPIOG_BASE+STM32L4_GPIO_IDR_OFFSET) -# define STM32L4_GPIOG_ODR (STM32L4_GPIOG_BASE+STM32L4_GPIO_ODR_OFFSET) -# define STM32L4_GPIOG_BSRR (STM32L4_GPIOG_BASE+STM32L4_GPIO_BSRR_OFFSET) -# define STM32L4_GPIOG_LCKR (STM32L4_GPIOG_BASE+STM32L4_GPIO_LCKR_OFFSET) -# define STM32L4_GPIOG_AFRL (STM32L4_GPIOG_BASE+STM32L4_GPIO_AFRL_OFFSET) -# define STM32L4_GPIOG_AFRH (STM32L4_GPIOG_BASE+STM32L4_GPIO_AFRH_OFFSET) -# define STM32L4_GPIOG_BRR (STM32L4_GPIOG_BASE+STM32L4_GPIO_BRR_OFFSET) -# define STM32L4_GPIOG_ASCR (STM32L4_GPIOG_BASE+STM32L4_GPIO_ASCR_OFFSET) +#if STM32_NPORTS > 6 +# define STM32_GPIOG_MODER (STM32_GPIOG_BASE+STM32_GPIO_MODER_OFFSET) +# define STM32_GPIOG_OTYPER (STM32_GPIOG_BASE+STM32_GPIO_OTYPER_OFFSET) +# define STM32_GPIOG_OSPEED (STM32_GPIOG_BASE+STM32_GPIO_OSPEED_OFFSET) +# define STM32_GPIOG_PUPDR (STM32_GPIOG_BASE+STM32_GPIO_PUPDR_OFFSET) +# define STM32_GPIOG_IDR (STM32_GPIOG_BASE+STM32_GPIO_IDR_OFFSET) +# define STM32_GPIOG_ODR (STM32_GPIOG_BASE+STM32_GPIO_ODR_OFFSET) +# define STM32_GPIOG_BSRR (STM32_GPIOG_BASE+STM32_GPIO_BSRR_OFFSET) +# define STM32_GPIOG_LCKR (STM32_GPIOG_BASE+STM32_GPIO_LCKR_OFFSET) +# define STM32_GPIOG_AFRL (STM32_GPIOG_BASE+STM32_GPIO_AFRL_OFFSET) +# define STM32_GPIOG_AFRH (STM32_GPIOG_BASE+STM32_GPIO_AFRH_OFFSET) +# define STM32_GPIOG_BRR (STM32_GPIOG_BASE+STM32_GPIO_BRR_OFFSET) +# define STM32_GPIOG_ASCR (STM32_GPIOG_BASE+STM32_GPIO_ASCR_OFFSET) #endif -#if STM32L4_NPORTS > 7 -# define STM32L4_GPIOH_MODER (STM32L4_GPIOH_BASE+STM32L4_GPIO_MODER_OFFSET) -# define STM32L4_GPIOH_OTYPER (STM32L4_GPIOH_BASE+STM32L4_GPIO_OTYPER_OFFSET) -# define STM32L4_GPIOH_OSPEED (STM32L4_GPIOH_BASE+STM32L4_GPIO_OSPEED_OFFSET) -# define STM32L4_GPIOH_PUPDR (STM32L4_GPIOH_BASE+STM32L4_GPIO_PUPDR_OFFSET) -# define STM32L4_GPIOH_IDR (STM32L4_GPIOH_BASE+STM32L4_GPIO_IDR_OFFSET) -# define STM32L4_GPIOH_ODR (STM32L4_GPIOH_BASE+STM32L4_GPIO_ODR_OFFSET) -# define STM32L4_GPIOH_BSRR (STM32L4_GPIOH_BASE+STM32L4_GPIO_BSRR_OFFSET) -# define STM32L4_GPIOH_LCKR (STM32L4_GPIOH_BASE+STM32L4_GPIO_LCKR_OFFSET) -# define STM32L4_GPIOH_AFRL (STM32L4_GPIOH_BASE+STM32L4_GPIO_AFRL_OFFSET) -# define STM32L4_GPIOH_AFRH (STM32L4_GPIOH_BASE+STM32L4_GPIO_AFRH_OFFSET) -# define STM32L4_GPIOH_BRR (STM32L4_GPIOH_BASE+STM32L4_GPIO_BRR_OFFSET) -# define STM32L4_GPIOH_ASCR (STM32L4_GPIOH_BASE+STM32L4_GPIO_ASCR_OFFSET) +#if STM32_NPORTS > 7 +# define STM32_GPIOH_MODER (STM32_GPIOH_BASE+STM32_GPIO_MODER_OFFSET) +# define STM32_GPIOH_OTYPER (STM32_GPIOH_BASE+STM32_GPIO_OTYPER_OFFSET) +# define STM32_GPIOH_OSPEED (STM32_GPIOH_BASE+STM32_GPIO_OSPEED_OFFSET) +# define STM32_GPIOH_PUPDR (STM32_GPIOH_BASE+STM32_GPIO_PUPDR_OFFSET) +# define STM32_GPIOH_IDR (STM32_GPIOH_BASE+STM32_GPIO_IDR_OFFSET) +# define STM32_GPIOH_ODR (STM32_GPIOH_BASE+STM32_GPIO_ODR_OFFSET) +# define STM32_GPIOH_BSRR (STM32_GPIOH_BASE+STM32_GPIO_BSRR_OFFSET) +# define STM32_GPIOH_LCKR (STM32_GPIOH_BASE+STM32_GPIO_LCKR_OFFSET) +# define STM32_GPIOH_AFRL (STM32_GPIOH_BASE+STM32_GPIO_AFRL_OFFSET) +# define STM32_GPIOH_AFRH (STM32_GPIOH_BASE+STM32_GPIO_AFRH_OFFSET) +# define STM32_GPIOH_BRR (STM32_GPIOH_BASE+STM32_GPIO_BRR_OFFSET) +# define STM32_GPIOH_ASCR (STM32_GPIOH_BASE+STM32_GPIO_ASCR_OFFSET) #endif -#if STM32L4_NPORTS > 8 -# define STM32L4_GPIOI_MODER (STM32L4_GPIOI_BASE+STM32L4_GPIO_MODER_OFFSET) -# define STM32L4_GPIOI_OTYPER (STM32L4_GPIOI_BASE+STM32L4_GPIO_OTYPER_OFFSET) -# define STM32L4_GPIOI_OSPEED (STM32L4_GPIOI_BASE+STM32L4_GPIO_OSPEED_OFFSET) -# define STM32L4_GPIOI_PUPDR (STM32L4_GPIOI_BASE+STM32L4_GPIO_PUPDR_OFFSET) -# define STM32L4_GPIOI_IDR (STM32L4_GPIOI_BASE+STM32L4_GPIO_IDR_OFFSET) -# define STM32L4_GPIOI_ODR (STM32L4_GPIOI_BASE+STM32L4_GPIO_ODR_OFFSET) -# define STM32L4_GPIOI_BSRR (STM32L4_GPIOI_BASE+STM32L4_GPIO_BSRR_OFFSET) -# define STM32L4_GPIOI_LCKR (STM32L4_GPIOI_BASE+STM32L4_GPIO_LCKR_OFFSET) -# define STM32L4_GPIOI_AFRL (STM32L4_GPIOI_BASE+STM32L4_GPIO_AFRL_OFFSET) -# define STM32L4_GPIOI_AFRH (STM32L4_GPIOI_BASE+STM32L4_GPIO_AFRH_OFFSET) -# define STM32L4_GPIOI_BRR (STM32L4_GPIOI_BASE+STM32L4_GPIO_BRR_OFFSET) -# define STM32L4_GPIOI_ASCR (STM32L4_GPIOI_BASE+STM32L4_GPIO_ASCR_OFFSET) +#if STM32_NPORTS > 8 +# define STM32_GPIOI_MODER (STM32_GPIOI_BASE+STM32_GPIO_MODER_OFFSET) +# define STM32_GPIOI_OTYPER (STM32_GPIOI_BASE+STM32_GPIO_OTYPER_OFFSET) +# define STM32_GPIOI_OSPEED (STM32_GPIOI_BASE+STM32_GPIO_OSPEED_OFFSET) +# define STM32_GPIOI_PUPDR (STM32_GPIOI_BASE+STM32_GPIO_PUPDR_OFFSET) +# define STM32_GPIOI_IDR (STM32_GPIOI_BASE+STM32_GPIO_IDR_OFFSET) +# define STM32_GPIOI_ODR (STM32_GPIOI_BASE+STM32_GPIO_ODR_OFFSET) +# define STM32_GPIOI_BSRR (STM32_GPIOI_BASE+STM32_GPIO_BSRR_OFFSET) +# define STM32_GPIOI_LCKR (STM32_GPIOI_BASE+STM32_GPIO_LCKR_OFFSET) +# define STM32_GPIOI_AFRL (STM32_GPIOI_BASE+STM32_GPIO_AFRL_OFFSET) +# define STM32_GPIOI_AFRH (STM32_GPIOI_BASE+STM32_GPIO_AFRH_OFFSET) +# define STM32_GPIOI_BRR (STM32_GPIOI_BASE+STM32_GPIO_BRR_OFFSET) +# define STM32_GPIOI_ASCR (STM32_GPIOI_BASE+STM32_GPIO_ASCR_OFFSET) #endif /* Register Bitfield Definitions ********************************************/ @@ -382,4 +382,4 @@ #define GPIO_ASCR(n) (1 << (n)) -#endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_GPIO_H */ +#endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32_GPIO_H */ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4_i2c.h b/arch/arm/src/stm32l4/hardware/stm32l4_i2c.h index 9ec04ef430a84..0b8bb0a43c7bb 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4_i2c.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4_i2c.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_I2C_H -#define __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_I2C_H +#ifndef __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32_I2C_H +#define __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32_I2C_H /**************************************************************************** * Pre-processor Definitions @@ -29,74 +29,74 @@ /* Register Offsets *********************************************************/ -#define STM32L4_I2C_CR1_OFFSET 0x0000 /* Control register 1 (32-bit) */ -#define STM32L4_I2C_CR2_OFFSET 0x0004 /* Control register 2 (32-bit) */ -#define STM32L4_I2C_OAR1_OFFSET 0x0008 /* Own address register 1 (16-bit) */ -#define STM32L4_I2C_OAR2_OFFSET 0x000c /* Own address register 2 (16-bit) */ -#define STM32L4_I2C_TIMINGR_OFFSET 0x0010 /* Timing register */ -#define STM32L4_I2C_TIMEOUTR_OFFSET 0x0014 /* Timeout register */ -#define STM32L4_I2C_ISR_OFFSET 0x0018 /* Interrupt and Status register */ -#define STM32L4_I2C_ICR_OFFSET 0x001c /* Interrupt clear register */ -#define STM32L4_I2C_PECR_OFFSET 0x0020 /* Packet error checking register */ -#define STM32L4_I2C_RXDR_OFFSET 0x0024 /* Receive data register */ -#define STM32L4_I2C_TXDR_OFFSET 0x0028 /* Transmit data register */ +#define STM32_I2C_CR1_OFFSET 0x0000 /* Control register 1 (32-bit) */ +#define STM32_I2C_CR2_OFFSET 0x0004 /* Control register 2 (32-bit) */ +#define STM32_I2C_OAR1_OFFSET 0x0008 /* Own address register 1 (16-bit) */ +#define STM32_I2C_OAR2_OFFSET 0x000c /* Own address register 2 (16-bit) */ +#define STM32_I2C_TIMINGR_OFFSET 0x0010 /* Timing register */ +#define STM32_I2C_TIMEOUTR_OFFSET 0x0014 /* Timeout register */ +#define STM32_I2C_ISR_OFFSET 0x0018 /* Interrupt and Status register */ +#define STM32_I2C_ICR_OFFSET 0x001c /* Interrupt clear register */ +#define STM32_I2C_PECR_OFFSET 0x0020 /* Packet error checking register */ +#define STM32_I2C_RXDR_OFFSET 0x0024 /* Receive data register */ +#define STM32_I2C_TXDR_OFFSET 0x0028 /* Transmit data register */ /* Register Addresses *******************************************************/ -#if STM32L4_NI2C > 0 -# define STM32L4_I2C1_CR1 (STM32L4_I2C1_BASE+STM32L4_I2C_CR1_OFFSET) -# define STM32L4_I2C1_CR2 (STM32L4_I2C1_BASE+STM32L4_I2C_CR2_OFFSET) -# define STM32L4_I2C1_OAR1 (STM32L4_I2C1_BASE+STM32L4_I2C_OAR1_OFFSET) -# define STM32L4_I2C1_OAR2 (STM32L4_I2C1_BASE+STM32L4_I2C_OAR2_OFFSET) -# define STM32L4_I2C1_TIMINGR (STM32L4_I2C1_BASE+STM32L4_I2C_TIMINGR_OFFSET) -# define STM32L4_I2C1_TIMEOUTR (STM32L4_I2C1_BASE+STM32L4_I2C_TIMEOUTR_OFFSET) -# define STM32L4_I2C1_ISR (STM32L4_I2C1_BASE+STM32L4_I2C_ISR_OFFSET) -# define STM32L4_I2C1_ICR (STM32L4_I2C1_BASE+STM32L4_I2C_ICR_OFFSET) -# define STM32L4_I2C1_PECR (STM32L4_I2C1_BASE+STM32L4_I2C_PECR_OFFSET) -# define STM32L4_I2C1_RXDR (STM32L4_I2C1_BASE+STM32L4_I2C_RXDR_OFFSET) -# define STM32L4_I2C1_TXDR (STM32L4_I2C1_BASE+STM32L4_I2C_TXDR_OFFSET) +#if STM32_NI2C > 0 +# define STM32_I2C1_CR1 (STM32_I2C1_BASE+STM32_I2C_CR1_OFFSET) +# define STM32_I2C1_CR2 (STM32_I2C1_BASE+STM32_I2C_CR2_OFFSET) +# define STM32_I2C1_OAR1 (STM32_I2C1_BASE+STM32_I2C_OAR1_OFFSET) +# define STM32_I2C1_OAR2 (STM32_I2C1_BASE+STM32_I2C_OAR2_OFFSET) +# define STM32_I2C1_TIMINGR (STM32_I2C1_BASE+STM32_I2C_TIMINGR_OFFSET) +# define STM32_I2C1_TIMEOUTR (STM32_I2C1_BASE+STM32_I2C_TIMEOUTR_OFFSET) +# define STM32_I2C1_ISR (STM32_I2C1_BASE+STM32_I2C_ISR_OFFSET) +# define STM32_I2C1_ICR (STM32_I2C1_BASE+STM32_I2C_ICR_OFFSET) +# define STM32_I2C1_PECR (STM32_I2C1_BASE+STM32_I2C_PECR_OFFSET) +# define STM32_I2C1_RXDR (STM32_I2C1_BASE+STM32_I2C_RXDR_OFFSET) +# define STM32_I2C1_TXDR (STM32_I2C1_BASE+STM32_I2C_TXDR_OFFSET) #endif -#if STM32L4_NI2C > 1 -# define STM32L4_I2C2_CR1 (STM32L4_I2C2_BASE+STM32L4_I2C_CR1_OFFSET) -# define STM32L4_I2C2_CR2 (STM32L4_I2C2_BASE+STM32L4_I2C_CR2_OFFSET) -# define STM32L4_I2C2_OAR1 (STM32L4_I2C2_BASE+STM32L4_I2C_OAR1_OFFSET) -# define STM32L4_I2C2_OAR2 (STM32L4_I2C2_BASE+STM32L4_I2C_OAR2_OFFSET) -# define STM32L4_I2C2_TIMINGR (STM32L4_I2C2_BASE+STM32L4_I2C_TIMINGR_OFFSET) -# define STM32L4_I2C2_TIMEOUTR (STM32L4_I2C2_BASE+STM32L4_I2C_TIMEOUTR_OFFSET) -# define STM32L4_I2C2_ISR (STM32L4_I2C2_BASE+STM32L4_I2C_ISR_OFFSET) -# define STM32L4_I2C2_ICR (STM32L4_I2C2_BASE+STM32L4_I2C_ICR_OFFSET) -# define STM32L4_I2C2_PECR (STM32L4_I2C2_BASE+STM32L4_I2C_PECR_OFFSET) -# define STM32L4_I2C2_RXDR (STM32L4_I2C2_BASE+STM32L4_I2C_RXDR_OFFSET) -# define STM32L4_I2C2_TXDR (STM32L4_I2C2_BASE+STM32L4_I2C_TXDR_OFFSET) +#if STM32_NI2C > 1 +# define STM32_I2C2_CR1 (STM32_I2C2_BASE+STM32_I2C_CR1_OFFSET) +# define STM32_I2C2_CR2 (STM32_I2C2_BASE+STM32_I2C_CR2_OFFSET) +# define STM32_I2C2_OAR1 (STM32_I2C2_BASE+STM32_I2C_OAR1_OFFSET) +# define STM32_I2C2_OAR2 (STM32_I2C2_BASE+STM32_I2C_OAR2_OFFSET) +# define STM32_I2C2_TIMINGR (STM32_I2C2_BASE+STM32_I2C_TIMINGR_OFFSET) +# define STM32_I2C2_TIMEOUTR (STM32_I2C2_BASE+STM32_I2C_TIMEOUTR_OFFSET) +# define STM32_I2C2_ISR (STM32_I2C2_BASE+STM32_I2C_ISR_OFFSET) +# define STM32_I2C2_ICR (STM32_I2C2_BASE+STM32_I2C_ICR_OFFSET) +# define STM32_I2C2_PECR (STM32_I2C2_BASE+STM32_I2C_PECR_OFFSET) +# define STM32_I2C2_RXDR (STM32_I2C2_BASE+STM32_I2C_RXDR_OFFSET) +# define STM32_I2C2_TXDR (STM32_I2C2_BASE+STM32_I2C_TXDR_OFFSET) #endif -#if STM32L4_NI2C > 2 -# define STM32L4_I2C3_CR1 (STM32L4_I2C3_BASE+STM32L4_I2C_CR1_OFFSET) -# define STM32L4_I2C3_CR2 (STM32L4_I2C3_BASE+STM32L4_I2C_CR2_OFFSET) -# define STM32L4_I2C3_OAR1 (STM32L4_I2C3_BASE+STM32L4_I2C_OAR1_OFFSET) -# define STM32L4_I2C3_OAR2 (STM32L4_I2C3_BASE+STM32L4_I2C_OAR2_OFFSET) -# define STM32L4_I2C3_TIMINGR (STM32L4_I2C3_BASE+STM32L4_I2C_TIMINGR_OFFSET) -# define STM32L4_I2C3_TIMEOUTR (STM32L4_I2C3_BASE+STM32L4_I2C_TIMEOUTR_OFFSET) -# define STM32L4_I2C3_ISR (STM32L4_I2C3_BASE+STM32L4_I2C_ISR_OFFSET) -# define STM32L4_I2C3_ICR (STM32L4_I2C3_BASE+STM32L4_I2C_ICR_OFFSET) -# define STM32L4_I2C3_PECR (STM32L4_I2C3_BASE+STM32L4_I2C_PECR_OFFSET) -# define STM32L4_I2C3_RXDR (STM32L4_I2C3_BASE+STM32L4_I2C_RXDR_OFFSET) -# define STM32L4_I2C3_TXDR (STM32L4_I2C3_BASE+STM32L4_I2C_TXDR_OFFSET) +#if STM32_NI2C > 2 +# define STM32_I2C3_CR1 (STM32_I2C3_BASE+STM32_I2C_CR1_OFFSET) +# define STM32_I2C3_CR2 (STM32_I2C3_BASE+STM32_I2C_CR2_OFFSET) +# define STM32_I2C3_OAR1 (STM32_I2C3_BASE+STM32_I2C_OAR1_OFFSET) +# define STM32_I2C3_OAR2 (STM32_I2C3_BASE+STM32_I2C_OAR2_OFFSET) +# define STM32_I2C3_TIMINGR (STM32_I2C3_BASE+STM32_I2C_TIMINGR_OFFSET) +# define STM32_I2C3_TIMEOUTR (STM32_I2C3_BASE+STM32_I2C_TIMEOUTR_OFFSET) +# define STM32_I2C3_ISR (STM32_I2C3_BASE+STM32_I2C_ISR_OFFSET) +# define STM32_I2C3_ICR (STM32_I2C3_BASE+STM32_I2C_ICR_OFFSET) +# define STM32_I2C3_PECR (STM32_I2C3_BASE+STM32_I2C_PECR_OFFSET) +# define STM32_I2C3_RXDR (STM32_I2C3_BASE+STM32_I2C_RXDR_OFFSET) +# define STM32_I2C3_TXDR (STM32_I2C3_BASE+STM32_I2C_TXDR_OFFSET) #endif -#if STM32L4_NI2C > 3 -# define STM32L4_I2C4_CR1 (STM32L4_I2C4_BASE+STM32L4_I2C_CR1_OFFSET) -# define STM32L4_I2C4_CR2 (STM32L4_I2C4_BASE+STM32L4_I2C_CR2_OFFSET) -# define STM32L4_I2C4_OAR1 (STM32L4_I2C4_BASE+STM32L4_I2C_OAR1_OFFSET) -# define STM32L4_I2C4_OAR2 (STM32L4_I2C4_BASE+STM32L4_I2C_OAR2_OFFSET) -# define STM32L4_I2C4_TIMINGR (STM32L4_I2C4_BASE+STM32L4_I2C_TIMINGR_OFFSET) -# define STM32L4_I2C4_TIMEOUTR (STM32L4_I2C4_BASE+STM32L4_I2C_TIMEOUTR_OFFSET) -# define STM32L4_I2C4_ISR (STM32L4_I2C4_BASE+STM32L4_I2C_ISR_OFFSET) -# define STM32L4_I2C4_ICR (STM32L4_I2C4_BASE+STM32L4_I2C_ICR_OFFSET) -# define STM32L4_I2C4_PECR (STM32L4_I2C4_BASE+STM32L4_I2C_PECR_OFFSET) -# define STM32L4_I2C4_RXDR (STM32L4_I2C4_BASE+STM32L4_I2C_RXDR_OFFSET) -# define STM32L4_I2C4_TXDR (STM32L4_I2C4_BASE+STM32L4_I2C_TXDR_OFFSET) +#if STM32_NI2C > 3 +# define STM32_I2C4_CR1 (STM32_I2C4_BASE+STM32_I2C_CR1_OFFSET) +# define STM32_I2C4_CR2 (STM32_I2C4_BASE+STM32_I2C_CR2_OFFSET) +# define STM32_I2C4_OAR1 (STM32_I2C4_BASE+STM32_I2C_OAR1_OFFSET) +# define STM32_I2C4_OAR2 (STM32_I2C4_BASE+STM32_I2C_OAR2_OFFSET) +# define STM32_I2C4_TIMINGR (STM32_I2C4_BASE+STM32_I2C_TIMINGR_OFFSET) +# define STM32_I2C4_TIMEOUTR (STM32_I2C4_BASE+STM32_I2C_TIMEOUTR_OFFSET) +# define STM32_I2C4_ISR (STM32_I2C4_BASE+STM32_I2C_ISR_OFFSET) +# define STM32_I2C4_ICR (STM32_I2C4_BASE+STM32_I2C_ICR_OFFSET) +# define STM32_I2C4_PECR (STM32_I2C4_BASE+STM32_I2C_PECR_OFFSET) +# define STM32_I2C4_RXDR (STM32_I2C4_BASE+STM32_I2C_RXDR_OFFSET) +# define STM32_I2C4_TXDR (STM32_I2C4_BASE+STM32_I2C_TXDR_OFFSET) #endif /* Register Bitfield Definitions ********************************************/ @@ -249,4 +249,4 @@ #define I2C_TXDR_MASK (0xff) -#endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_I2C_H */ +#endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32_I2C_H */ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4_lptim.h b/arch/arm/src/stm32l4/hardware/stm32l4_lptim.h index 1da51068e5564..bdd2b5f5aa31c 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4_lptim.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4_lptim.h @@ -36,8 +36,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_LPTIM_H -#define __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_LPTIM_H +#ifndef __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32_LPTIM_H +#define __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32_LPTIM_H /**************************************************************************** * Pre-processor Definitions @@ -47,36 +47,36 @@ /* Basic Timers - TIM6 and TIM7 */ -#define STM32L4_LPTIM_ISR_OFFSET 0x0000 /* Interrupt and Status Register */ -#define STM32L4_LPTIM_ICR_OFFSET 0x0004 /* Interrupt Clear Register */ -#define STM32L4_LPTIM_IER_OFFSET 0x0008 /* Interrupt Enable Register */ -#define STM32L4_LPTIM_CFGR_OFFSET 0x000c /* Configuration Register */ -#define STM32L4_LPTIM_CR_OFFSET 0x0010 /* Control Register */ -#define STM32L4_LPTIM_CMP_OFFSET 0x0014 /* Compare Register */ -#define STM32L4_LPTIM_ARR_OFFSET 0x0018 /* Autoreload Register */ -#define STM32L4_LPTIM_CNT_OFFSET 0x001c /* Counter Register */ +#define STM32_LPTIM_ISR_OFFSET 0x0000 /* Interrupt and Status Register */ +#define STM32_LPTIM_ICR_OFFSET 0x0004 /* Interrupt Clear Register */ +#define STM32_LPTIM_IER_OFFSET 0x0008 /* Interrupt Enable Register */ +#define STM32_LPTIM_CFGR_OFFSET 0x000c /* Configuration Register */ +#define STM32_LPTIM_CR_OFFSET 0x0010 /* Control Register */ +#define STM32_LPTIM_CMP_OFFSET 0x0014 /* Compare Register */ +#define STM32_LPTIM_ARR_OFFSET 0x0018 /* Autoreload Register */ +#define STM32_LPTIM_CNT_OFFSET 0x001c /* Counter Register */ /* Register Addresses *******************************************************/ /* Low-Power Timers - LPTIM1 and LPTIM2 */ -#define STM32L4_LPTIM1_ISR (STM32L4_LPTIM1_BASE+STM32L4_LPTIM_ISR_OFFSET) -#define STM32L4_LPTIM1_ICR (STM32L4_LPTIM1_BASE+STM32L4_LPTIM_ICR_OFFSET) -#define STM32L4_LPTIM1_IER (STM32L4_LPTIM1_BASE+STM32L4_LPTIM_IER_OFFSET) -#define STM32L4_LPTIM1_CFGR (STM32L4_LPTIM1_BASE+STM32L4_LPTIM_CFGR_OFFSET) -#define STM32L4_LPTIM1_CR (STM32L4_LPTIM1_BASE+STM32L4_LPTIM_CR_OFFSET) -#define STM32L4_LPTIM1_CMP (STM32L4_LPTIM1_BASE+STM32L4_LPTIM_CMP_OFFSET) -#define STM32L4_LPTIM1_ARR (STM32L4_LPTIM1_BASE+STM32L4_LPTIM_ARR_OFFSET) -#define STM32L4_LPTIM1_CNT (STM32L4_LPTIM1_BASE+STM32L4_LPTIM_CNT_OFFSET) - -#define STM32L4_LPTIM2_ISR (STM32L4_LPTIM2_BASE+STM32L4_LPTIM_ISR_OFFSET) -#define STM32L4_LPTIM2_ICR (STM32L4_LPTIM2_BASE+STM32L4_LPTIM_ICR_OFFSET) -#define STM32L4_LPTIM2_IER (STM32L4_LPTIM2_BASE+STM32L4_LPTIM_IER_OFFSET) -#define STM32L4_LPTIM2_CFGR (STM32L4_LPTIM2_BASE+STM32L4_LPTIM_CFGR_OFFSET) -#define STM32L4_LPTIM2_CR (STM32L4_LPTIM2_BASE+STM32L4_LPTIM_CR_OFFSET) -#define STM32L4_LPTIM2_CMP (STM32L4_LPTIM2_BASE+STM32L4_LPTIM_CMP_OFFSET) -#define STM32L4_LPTIM2_ARR (STM32L4_LPTIM2_BASE+STM32L4_LPTIM_ARR_OFFSET) -#define STM32L4_LPTIM2_CNT (STM32L4_LPTIM2_BASE+STM32L4_LPTIM_CNT_OFFSET) +#define STM32_LPTIM1_ISR (STM32_LPTIM1_BASE+STM32_LPTIM_ISR_OFFSET) +#define STM32_LPTIM1_ICR (STM32_LPTIM1_BASE+STM32_LPTIM_ICR_OFFSET) +#define STM32_LPTIM1_IER (STM32_LPTIM1_BASE+STM32_LPTIM_IER_OFFSET) +#define STM32_LPTIM1_CFGR (STM32_LPTIM1_BASE+STM32_LPTIM_CFGR_OFFSET) +#define STM32_LPTIM1_CR (STM32_LPTIM1_BASE+STM32_LPTIM_CR_OFFSET) +#define STM32_LPTIM1_CMP (STM32_LPTIM1_BASE+STM32_LPTIM_CMP_OFFSET) +#define STM32_LPTIM1_ARR (STM32_LPTIM1_BASE+STM32_LPTIM_ARR_OFFSET) +#define STM32_LPTIM1_CNT (STM32_LPTIM1_BASE+STM32_LPTIM_CNT_OFFSET) + +#define STM32_LPTIM2_ISR (STM32_LPTIM2_BASE+STM32_LPTIM_ISR_OFFSET) +#define STM32_LPTIM2_ICR (STM32_LPTIM2_BASE+STM32_LPTIM_ICR_OFFSET) +#define STM32_LPTIM2_IER (STM32_LPTIM2_BASE+STM32_LPTIM_IER_OFFSET) +#define STM32_LPTIM2_CFGR (STM32_LPTIM2_BASE+STM32_LPTIM_CFGR_OFFSET) +#define STM32_LPTIM2_CR (STM32_LPTIM2_BASE+STM32_LPTIM_CR_OFFSET) +#define STM32_LPTIM2_CMP (STM32_LPTIM2_BASE+STM32_LPTIM_CMP_OFFSET) +#define STM32_LPTIM2_ARR (STM32_LPTIM2_BASE+STM32_LPTIM_ARR_OFFSET) +#define STM32_LPTIM2_CNT (STM32_LPTIM2_BASE+STM32_LPTIM_CNT_OFFSET) /* Register Bitfield Definitions ********************************************/ @@ -134,4 +134,4 @@ #define LPTIM_ISR_UP (1 << 5) /* Bit 5: Counter direction change down to up */ #define LPTIM_ISR_DOWN (1 << 6) /* Bit 6: Counter direction change up to down */ -#endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_LPTIM_H */ +#endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32_LPTIM_H */ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4_memorymap.h b/arch/arm/src/stm32l4/hardware/stm32l4_memorymap.h index 0cb4e62cac313..7adfe4082c203 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4_memorymap.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4_memorymap.h @@ -29,60 +29,60 @@ /* STM32L4XXX Address Blocks ************************************************/ -#define STM32L4_CODE_BASE 0x00000000 /* 0x00000000-0x1fffffff: 512Mb code block */ -#define STM32L4_SRAM_BASE 0x20000000 /* 0x20000000-0x3fffffff: 512Mb sram block (48k to 256k) */ -#define STM32L4_PERIPH_BASE 0x40000000 /* 0x40000000-0x5fffffff: 512Mb peripheral block */ -#define STM32L4_FSMC_BASE12 0x60000000 /* 0x60000000-0x7fffffff: 512Mb FSMC bank1&2 block */ -# define STM32L4_FSMC_BANK1 0x60000000 /* 0x60000000-0x6fffffff: 256Mb NOR/SRAM */ -# define STM32L4_FSMC_BANK2 0x70000000 /* 0x70000000-0x7fffffff: 256Mb NAND FLASH */ -#define STM32L4_FSMC_BASE34 0x80000000 /* 0x80000000-0x8fffffff: 512Mb FSMC bank3 / QSPI block */ -# define STM32L4_FSMC_BANK3 0x80000000 /* 0x80000000-0x8fffffff: 256Mb NAND FLASH */ -# define STM32L4_QSPI_BANK 0x90000000 /* 0x90000000-0x9fffffff: 256Mb QUADSPI */ -#define STM32L4_FSMC_BASE 0xa0000000 /* 0xa0000000-0xbfffffff: FSMC register block */ -#define STM32L4_QSPI_BASE 0xa0001000 /* 0xa0001000-0xbfffffff: QSPI register block */ -#define STM32L4_OCTOSPI1_BASE 0xa0001000 /* 0xa0001000-0xa00013ff: OCTOSPI1 register block */ -#define STM32L4_OCTOSPI2_BASE 0xa0001400 /* 0xa0001400-0xa00017ff: OCTOSPI2 register block */ - /* 0xc0000000-0xdfffffff: 512Mb (not used) */ -#define STM32L4_CORTEX_BASE 0xe0000000 /* 0xe0000000-0xffffffff: 512Mb Cortex-M4 block */ - -#define STM32L4_REGION_MASK 0xf0000000 -#define STM32L4_IS_SRAM(a) ((((uint32_t)(a)) & STM32L4_REGION_MASK) == STM32L4_SRAM_BASE) -#define STM32L4_IS_EXTSRAM(a) ((((uint32_t)(a)) & STM32L4_REGION_MASK) == STM32L4_FSMC_BANK1) +#define STM32_CODE_BASE 0x00000000 /* 0x00000000-0x1fffffff: 512Mb code block */ +#define STM32_SRAM_BASE 0x20000000 /* 0x20000000-0x3fffffff: 512Mb sram block (48k to 256k) */ +#define STM32_PERIPH_BASE 0x40000000 /* 0x40000000-0x5fffffff: 512Mb peripheral block */ +#define STM32_FSMC_BASE12 0x60000000 /* 0x60000000-0x7fffffff: 512Mb FSMC bank1&2 block */ +# define STM32_FSMC_BANK1 0x60000000 /* 0x60000000-0x6fffffff: 256Mb NOR/SRAM */ +# define STM32_FSMC_BANK2 0x70000000 /* 0x70000000-0x7fffffff: 256Mb NAND FLASH */ +#define STM32_FSMC_BASE34 0x80000000 /* 0x80000000-0x8fffffff: 512Mb FSMC bank3 / QSPI block */ +# define STM32_FSMC_BANK3 0x80000000 /* 0x80000000-0x8fffffff: 256Mb NAND FLASH */ +# define STM32_QSPI_BANK 0x90000000 /* 0x90000000-0x9fffffff: 256Mb QUADSPI */ +#define STM32_FSMC_BASE 0xa0000000 /* 0xa0000000-0xbfffffff: FSMC register block */ +#define STM32_QSPI_BASE 0xa0001000 /* 0xa0001000-0xbfffffff: QSPI register block */ +#define STM32_OCTOSPI1_BASE 0xa0001000 /* 0xa0001000-0xa00013ff: OCTOSPI1 register block */ +#define STM32_OCTOSPI2_BASE 0xa0001400 /* 0xa0001400-0xa00017ff: OCTOSPI2 register block */ + /* 0xc0000000-0xdfffffff: 512Mb (not used) */ +#define STM32_CORTEX_BASE 0xe0000000 /* 0xe0000000-0xffffffff: 512Mb Cortex-M4 block */ + +#define STM32_REGION_MASK 0xf0000000 +#define STM32_IS_SRAM(a) ((((uint32_t)(a)) & STM32_REGION_MASK) == STM32_SRAM_BASE) +#define STM32_IS_EXTSRAM(a) ((((uint32_t)(a)) & STM32_REGION_MASK) == STM32_FSMC_BANK1) /* Code Base Addresses ******************************************************/ -#define STM32L4_BOOT_BASE 0x00000000 /* 0x00000000-0x000fffff: Aliased boot memory */ - /* 0x00100000-0x07ffffff: Reserved */ -#define STM32L4_FLASH_BASE 0x08000000 /* 0x08000000-0x080fffff: FLASH memory */ - /* 0x08100000-0x0fffffff: Reserved */ -#define STM32L4_FLASH_MASK 0xf8000000 /* Test if addr in FLASH */ -#define STM32L4_SRAM2_BASE 0x10000000 /* 0x10000000-0x1000ffff: 16k to 64k SRAM2 */ - /* 0x10010000-0x1ffeffff: Reserved */ -#define STM32L4_SRAM3_BASE 0x20040000 /* 0x20040000-0x3fffffff: SRAM3 (STM32L4R9xx only, 384k) */ -#define STM32L4_SYSMEM_BASE 0x1fff0000 /* 0x1fff0000-0x1fff6fff: System memory */ -#define STM32L4_OTP_BASE 0x1fff7000 /* 0x1fff7000-0x1fff73ff: OTP memory */ - /* 0x1fff7400-0x1fff77ff: Reserved */ -#ifdef CONFIG_STM32L4_STM32L4XR -# define STM32L4_OPTION_BASE 0x1ff00000 /* 0x1ff00000-0x1ff0000f: Option bytes */ - /* 0x1ff00010-0x1ff00fff: Reserved */ -# define STM32L4_OPTION2_BASE 0x1ff01000 /* 0x1ff01000-0x1ff0100f: Option bytes 2 */ - /* 0x1ff01010-0x1ff01fff: Reserved */ +#define STM32_BOOT_BASE 0x00000000 /* 0x00000000-0x000fffff: Aliased boot memory */ + /* 0x00100000-0x07ffffff: Reserved */ +#define STM32_FLASH_BASE 0x08000000 /* 0x08000000-0x080fffff: FLASH memory */ + /* 0x08100000-0x0fffffff: Reserved */ +#define STM32_FLASH_MASK 0xf8000000 /* Test if addr in FLASH */ +#define STM32_SRAM2_BASE 0x10000000 /* 0x10000000-0x1000ffff: 16k to 64k SRAM2 */ + /* 0x10010000-0x1ffeffff: Reserved */ +#define STM32_SRAM3_BASE 0x20040000 /* 0x20040000-0x3fffffff: SRAM3 (STM32L4R9xx only, 384k) */ +#define STM32_SYSMEM_BASE 0x1fff0000 /* 0x1fff0000-0x1fff6fff: System memory */ +#define STM32_OTP_BASE 0x1fff7000 /* 0x1fff7000-0x1fff73ff: OTP memory */ + /* 0x1fff7400-0x1fff77ff: Reserved */ +#ifdef CONFIG_STM32_STM32L4XR +# define STM32_OPTION_BASE 0x1ff00000 /* 0x1ff00000-0x1ff0000f: Option bytes */ + /* 0x1ff00010-0x1ff00fff: Reserved */ +# define STM32_OPTION2_BASE 0x1ff01000 /* 0x1ff01000-0x1ff0100f: Option bytes 2 */ + /* 0x1ff01010-0x1ff01fff: Reserved */ #else -# define STM32L4_OPTION_BASE 0x1fff7800 /* 0x1fff7800-0x1fff780f: Option bytes */ - /* 0x1fff7810-0x1ffff7ff: Reserved */ -# define STM32L4_OPTION2_BASE 0x1ffff800 /* 0x1ffff800-0x1ffff80f: Option bytes 2 */ - /* 0x1ffff810-0x1fffffff: Reserved */ +# define STM32_OPTION_BASE 0x1fff7800 /* 0x1fff7800-0x1fff780f: Option bytes */ + /* 0x1fff7810-0x1ffff7ff: Reserved */ +# define STM32_OPTION2_BASE 0x1ffff800 /* 0x1ffff800-0x1ffff80f: Option bytes 2 */ + /* 0x1ffff810-0x1fffffff: Reserved */ #endif /* System Memory Addresses **************************************************/ -#define STM32L4_SYSMEM_UID 0x1fff7590 /* The 96-bit unique device identifier */ -#define STM32L4_SYSMEM_FSIZE 0x1fff75E0 /* This bitfield indicates the size of +#define STM32_SYSMEM_UID 0x1fff7590 /* The 96-bit unique device identifier */ +#define STM32_SYSMEM_FSIZE 0x1fff75E0 /* This bitfield indicates the size of * the device Flash memory expressed in * Kbytes. Example: 0x0400 corresponds * to 1024 Kbytes. */ -#define STM32L4_SYSMEM_PACKAGE 0x1fff7500 /* This bitfield indicates the package +#define STM32_SYSMEM_PACKAGE 0x1fff7500 /* This bitfield indicates the package * type. * 0: LQFP64 * 1: WLCSP64 @@ -105,123 +105,123 @@ /* 0x2001c000-0x2001ffff: * 16Kb aliased by bit-banding */ -#define STM32L4_SRAMBB_BASE 0x22000000 /* 0x22000000- : SRAM bit-band region */ +#define STM32_SRAMBB_BASE 0x22000000 /* 0x22000000- : SRAM bit-band region */ /* Peripheral Base Addresses ************************************************/ -#define STM32L4_APB1_BASE 0x40000000 /* 0x40000000-0x400097ff: APB1 */ - /* 0x40009800-0x4000ffff: Reserved */ -#define STM32L4_APB2_BASE 0x40010000 /* 0x40010000-0x400163ff: APB2 */ - /* 0x40016400-0x4001ffff: Reserved */ -#define STM32L4_AHB1_BASE 0x40020000 /* 0x40020000-0x400243ff: APB1 */ - /* 0x40024400-0x47ffffff: Reserved */ -#define STM32L4_AHB2_BASE 0x48000000 /* 0x48000000-0x50060bff: AHB2 */ - /* 0x50060c00-0x5fffffff: Reserved */ +#define STM32_APB1_BASE 0x40000000 /* 0x40000000-0x400097ff: APB1 */ + /* 0x40009800-0x4000ffff: Reserved */ +#define STM32_APB2_BASE 0x40010000 /* 0x40010000-0x400163ff: APB2 */ + /* 0x40016400-0x4001ffff: Reserved */ +#define STM32_AHB1_BASE 0x40020000 /* 0x40020000-0x400243ff: APB1 */ + /* 0x40024400-0x47ffffff: Reserved */ +#define STM32_AHB2_BASE 0x48000000 /* 0x48000000-0x50060bff: AHB2 */ + /* 0x50060c00-0x5fffffff: Reserved */ /* FSMC/QSPI Base Addresses *************************************************/ -#define STM32L4_AHB3_BASE 0x60000000 /* 0x60000000-0xa0000fff: AHB3 */ +#define STM32_AHB3_BASE 0x60000000 /* 0x60000000-0xa0000fff: AHB3 */ /* in datasheet order */ /* APB1 Base Addresses ******************************************************/ -#define STM32L4_LPTIM2_BASE 0x40009400 -#define STM32L4_SWPMI1_BASE 0x40008800 -#define STM32L4_I2C4_BASE 0x40008400 -#define STM32L4_LPUART1_BASE 0x40008000 -#define STM32L4_LPTIM1_BASE 0x40007c00 -#define STM32L4_OPAMP_BASE 0x40007800 -#define STM32L4_DAC_BASE 0x40007400 -#define STM32L4_PWR_BASE 0x40007000 -#if defined(CONFIG_STM32L4_STM32L4X3) -# define STM32L4_USB_SRAM_BASE 0x40006c00 -# define STM32L4_USB_FS_BASE 0x40006800 +#define STM32_LPTIM2_BASE 0x40009400 +#define STM32_SWPMI1_BASE 0x40008800 +#define STM32_I2C4_BASE 0x40008400 +#define STM32_LPUART1_BASE 0x40008000 +#define STM32_LPTIM1_BASE 0x40007c00 +#define STM32_OPAMP_BASE 0x40007800 +#define STM32_DAC_BASE 0x40007400 +#define STM32_PWR_BASE 0x40007000 +#if defined(CONFIG_STM32_STM32L4X3) +# define STM32_USB_SRAM_BASE 0x40006c00 +# define STM32_USB_FS_BASE 0x40006800 #else -# define STM32L4_CAN2_BASE 0x40006800 +# define STM32_CAN2_BASE 0x40006800 #endif -#define STM32L4_CAN1_BASE 0x40006400 -#define STM32L4_CRS_BASE 0x40006000 -#define STM32L4_I2C3_BASE 0x40005c00 -#define STM32L4_I2C2_BASE 0x40005800 -#define STM32L4_I2C1_BASE 0x40005400 -#define STM32L4_UART5_BASE 0x40005000 -#define STM32L4_UART4_BASE 0x40004c00 -#define STM32L4_USART3_BASE 0x40004800 -#define STM32L4_USART2_BASE 0x40004400 -#define STM32L4_SPI3_BASE 0x40003c00 -#define STM32L4_SPI2_BASE 0x40003800 -#define STM32L4_IWDG_BASE 0x40003000 -#define STM32L4_WWDG_BASE 0x40002c00 -#define STM32L4_RTC_BASE 0x40002800 -#define STM32L4_LCD_BASE 0x40002400 -#define STM32L4_TIM7_BASE 0x40001400 -#define STM32L4_TIM6_BASE 0x40001000 -#define STM32L4_TIM5_BASE 0x40000c00 -#define STM32L4_TIM4_BASE 0x40000800 -#define STM32L4_TIM3_BASE 0x40000400 -#define STM32L4_TIM2_BASE 0x40000000 +#define STM32_CAN1_BASE 0x40006400 +#define STM32_CRS_BASE 0x40006000 +#define STM32_I2C3_BASE 0x40005c00 +#define STM32_I2C2_BASE 0x40005800 +#define STM32_I2C1_BASE 0x40005400 +#define STM32_UART5_BASE 0x40005000 +#define STM32_UART4_BASE 0x40004c00 +#define STM32_USART3_BASE 0x40004800 +#define STM32_USART2_BASE 0x40004400 +#define STM32_SPI3_BASE 0x40003c00 +#define STM32_SPI2_BASE 0x40003800 +#define STM32_IWDG_BASE 0x40003000 +#define STM32_WWDG_BASE 0x40002c00 +#define STM32_RTC_BASE 0x40002800 +#define STM32_LCD_BASE 0x40002400 +#define STM32_TIM7_BASE 0x40001400 +#define STM32_TIM6_BASE 0x40001000 +#define STM32_TIM5_BASE 0x40000c00 +#define STM32_TIM4_BASE 0x40000800 +#define STM32_TIM3_BASE 0x40000400 +#define STM32_TIM2_BASE 0x40000000 /* APB2 Base Addresses ******************************************************/ -#define STM32L4_DSI_BASE 0x40016c00 -#define STM32L4_LTDC_BASE 0x40016800 -#define STM32L4_DFSDM_BASE 0x40016000 -#define STM32L4_SAI2_BASE 0x40015800 -#define STM32L4_SAI1_BASE 0x40015400 -#define STM32L4_TIM17_BASE 0x40014800 -#define STM32L4_TIM16_BASE 0x40014400 -#define STM32L4_TIM15_BASE 0x40014000 -#define STM32L4_USART1_BASE 0x40013800 -#define STM32L4_TIM8_BASE 0x40013400 -#define STM32L4_SPI1_BASE 0x40013000 -#define STM32L4_TIM1_BASE 0x40012c00 -#ifndef CONFIG_STM32L4_STM32L4XR -# define STM32L4_SDMMC1_BASE 0x40012800 +#define STM32_DSI_BASE 0x40016c00 +#define STM32_LTDC_BASE 0x40016800 +#define STM32_DFSDM_BASE 0x40016000 +#define STM32_SAI2_BASE 0x40015800 +#define STM32_SAI1_BASE 0x40015400 +#define STM32_TIM17_BASE 0x40014800 +#define STM32_TIM16_BASE 0x40014400 +#define STM32_TIM15_BASE 0x40014000 +#define STM32_USART1_BASE 0x40013800 +#define STM32_TIM8_BASE 0x40013400 +#define STM32_SPI1_BASE 0x40013000 +#define STM32_TIM1_BASE 0x40012c00 +#ifndef CONFIG_STM32_STM32L4XR +# define STM32_SDMMC1_BASE 0x40012800 #endif -#define STM32L4_FIREWALL_BASE 0x40011c00 -#define STM32L4_EXTI_BASE 0x40010400 -#define STM32L4_COMP_BASE 0x40010200 -#define STM32L4_VREFBUF_BASE 0x40010030 -#define STM32L4_SYSCFG_BASE 0x40010000 +#define STM32_FIREWALL_BASE 0x40011c00 +#define STM32_EXTI_BASE 0x40010400 +#define STM32_COMP_BASE 0x40010200 +#define STM32_VREFBUF_BASE 0x40010030 +#define STM32_SYSCFG_BASE 0x40010000 /* AHB1 Base Addresses ******************************************************/ -#define STM32L4_GFXMMU_BASE 0x4002c000 -#define STM32L4_DMA2D_BASE 0x4002b000 -#define STM32L4_TSC_BASE 0x40024000 -#define STM32L4_CRC_BASE 0x40023000 -#define STM32L4_FLASHIF_BASE 0x40022000 -#define STM32L4_RCC_BASE 0x40021000 -#define STM32L4_DMAMUX1_BASE 0x40020800 -#define STM32L4_DMA2_BASE 0x40020400 -#define STM32L4_DMA1_BASE 0x40020000 +#define STM32_GFXMMU_BASE 0x4002c000 +#define STM32_DMA2D_BASE 0x4002b000 +#define STM32_TSC_BASE 0x40024000 +#define STM32_CRC_BASE 0x40023000 +#define STM32_FLASHIF_BASE 0x40022000 +#define STM32_RCC_BASE 0x40021000 +#define STM32_DMAMUX1_BASE 0x40020800 +#define STM32_DMA2_BASE 0x40020400 +#define STM32_DMA1_BASE 0x40020000 /* AHB2 Base Addresses ******************************************************/ -#ifdef CONFIG_STM32L4_STM32L4XR -# define STM32L4_SDMMC1_BASE 0x50062400 +#ifdef CONFIG_STM32_STM32L4XR +# define STM32_SDMMC1_BASE 0x50062400 #endif -#define STM32L4_OCTOSPIIOM_BASE 0x50061c00 -#define STM32L4_RNG_BASE 0x50060800 -#define STM32L4_HASH_BASE 0x50060400 -#define STM32L4_AES_BASE 0x50060000 -#define STM32L4_DCMI_BASE 0x50050000 -#define STM32L4_ADC_BASE 0x50040000 -# define STM32L4_ADC1_BASE 0x50040000 /* ADC1 */ -# define STM32L4_ADC2_BASE 0x50040100 /* ADC2 */ -# define STM32L4_ADC3_BASE 0x50040200 /* ADC3 */ -# define STM32L4_ADCCMN_BASE 0x50040300 /* Common */ -#define STM32L4_OTGFS_BASE 0x50000000 -#define STM32L4_GPIOI_BASE 0x48002000 -#define STM32L4_GPIOH_BASE 0x48001c00 -#define STM32L4_GPIOG_BASE 0x48001800 -#define STM32L4_GPIOF_BASE 0x48001400 -#define STM32L4_GPIOE_BASE 0x48001000 -#define STM32L4_GPIOD_BASE 0x48000c00 -#define STM32L4_GPIOC_BASE 0x48000800 -#define STM32L4_GPIOB_BASE 0x48000400 -#define STM32L4_GPIOA_BASE 0x48000000 +#define STM32_OCTOSPIIOM_BASE 0x50061c00 +#define STM32_RNG_BASE 0x50060800 +#define STM32_HASH_BASE 0x50060400 +#define STM32_AES_BASE 0x50060000 +#define STM32_DCMI_BASE 0x50050000 +#define STM32_ADC_BASE 0x50040000 +# define STM32_ADC1_BASE 0x50040000 /* ADC1 */ +# define STM32_ADC2_BASE 0x50040100 /* ADC2 */ +# define STM32_ADC3_BASE 0x50040200 /* ADC3 */ +# define STM32_ADCCMN_BASE 0x50040300 /* Common */ +#define STM32_OTGFS_BASE 0x50000000 +#define STM32_GPIOI_BASE 0x48002000 +#define STM32_GPIOH_BASE 0x48001c00 +#define STM32_GPIOG_BASE 0x48001800 +#define STM32_GPIOF_BASE 0x48001400 +#define STM32_GPIOE_BASE 0x48001000 +#define STM32_GPIOD_BASE 0x48000c00 +#define STM32_GPIOC_BASE 0x48000800 +#define STM32_GPIOB_BASE 0x48000400 +#define STM32_GPIOA_BASE 0x48000000 /* Cortex-M4 Base Addresses *************************************************/ @@ -229,7 +229,7 @@ * this address range */ -#define STM32L4_SCS_BASE 0xe000e000 -#define STM32L4_DEBUGMCU_BASE 0xe0042000 +#define STM32_SCS_BASE 0xe000e000 +#define STM32_DEBUGMCU_BASE 0xe0042000 #endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_MEMORYMAP_H */ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4_pinmap.h b/arch/arm/src/stm32l4/hardware/stm32l4_pinmap.h index c8e33f62f181f..57bf610937565 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4_pinmap.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4_pinmap.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_PINMAP_H -#define __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_PINMAP_H +#ifndef __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32_PINMAP_H +#define __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32_PINMAP_H /**************************************************************************** * Included Files @@ -30,16 +30,16 @@ #include #include "chip.h" -#if defined(CONFIG_STM32L4_STM32L4X3) +#if defined(CONFIG_STM32_STM32L4X3) # include "hardware/stm32l4x3xx_pinmap.h" -#elif defined(CONFIG_STM32L4_STM32L4X5) +#elif defined(CONFIG_STM32_STM32L4X5) # include "hardware/stm32l4x5xx_pinmap.h" -#elif defined(CONFIG_STM32L4_STM32L4X6) +#elif defined(CONFIG_STM32_STM32L4X6) # include "hardware/stm32l4x6xx_pinmap.h" -#elif defined(CONFIG_STM32L4_STM32L4XR) +#elif defined(CONFIG_STM32_STM32L4XR) # include "hardware/stm32l4xrxx_pinmap.h" #else # error "Unsupported STM32 L4 pin map" #endif -#endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_PINMAP_H */ +#endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32_PINMAP_H */ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4_pwr.h b/arch/arm/src/stm32l4/hardware/stm32l4_pwr.h index ab598f0c70ac6..09be34e1e027e 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4_pwr.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4_pwr.h @@ -36,64 +36,64 @@ /* Register Offsets *********************************************************/ -#define STM32L4_PWR_CR1_OFFSET 0x0000 /* Power control register 1 */ -#define STM32L4_PWR_CR2_OFFSET 0x0004 /* Power control register 2 */ -#define STM32L4_PWR_CR3_OFFSET 0x0008 /* Power control register 3 */ -#define STM32L4_PWR_CR4_OFFSET 0x000C /* Power control register 4 */ -#define STM32L4_PWR_SR1_OFFSET 0x0010 /* Power status register 1 */ -#define STM32L4_PWR_SR2_OFFSET 0x0014 /* Power status register 2 */ -#define STM32L4_PWR_SCR_OFFSET 0x0018 /* Power status clear register */ -#define STM32L4_PWR_PUCRA_OFFSET 0x0020 /* Power Port A pull-up control register */ -#define STM32L4_PWR_PDCRA_OFFSET 0x0024 /* Power Port A pull-down control register */ -#define STM32L4_PWR_PUCRB_OFFSET 0x0028 /* Power Port B pull-up control register */ -#define STM32L4_PWR_PDCRB_OFFSET 0x002C /* Power Port B pull-down control register */ -#define STM32L4_PWR_PUCRC_OFFSET 0x0030 /* Power Port C pull-up control register */ -#define STM32L4_PWR_PDCRC_OFFSET 0x0034 /* Power Port C pull-down control register */ -#define STM32L4_PWR_PUCRD_OFFSET 0x0038 /* Power Port D pull-up control register */ -#define STM32L4_PWR_PDCRD_OFFSET 0x003C /* Power Port D pull-down control register */ -#define STM32L4_PWR_PUCRE_OFFSET 0x0040 /* Power Port E pull-up control register */ -#define STM32L4_PWR_PDCRE_OFFSET 0x0044 /* Power Port E pull-down control register */ -#define STM32L4_PWR_PUCRF_OFFSET 0x0048 /* Power Port F pull-up control register */ -#define STM32L4_PWR_PDCRF_OFFSET 0x004C /* Power Port F pull-down control register */ -#define STM32L4_PWR_PUCRG_OFFSET 0x0050 /* Power Port G pull-up control register */ -#define STM32L4_PWR_PDCRG_OFFSET 0x0054 /* Power Port G pull-down control register */ -#define STM32L4_PWR_PUCRH_OFFSET 0x0058 /* Power Port H pull-up control register */ -#define STM32L4_PWR_PDCRH_OFFSET 0x005C /* Power Port H pull-down control register */ -#define STM32L4_PWR_PUCRI_OFFSET 0x0060 /* Power Port I pull-up control register */ -#define STM32L4_PWR_PDCRI_OFFSET 0x0064 /* Power Port I pull-down control register */ -#if defined(CONFIG_STM32L4_STM32L4XR) -# define STM32L4_PWR_CR5_OFFSET 0x0080 /* Power control register 5 */ +#define STM32_PWR_CR1_OFFSET 0x0000 /* Power control register 1 */ +#define STM32_PWR_CR2_OFFSET 0x0004 /* Power control register 2 */ +#define STM32_PWR_CR3_OFFSET 0x0008 /* Power control register 3 */ +#define STM32_PWR_CR4_OFFSET 0x000C /* Power control register 4 */ +#define STM32_PWR_SR1_OFFSET 0x0010 /* Power status register 1 */ +#define STM32_PWR_SR2_OFFSET 0x0014 /* Power status register 2 */ +#define STM32_PWR_SCR_OFFSET 0x0018 /* Power status clear register */ +#define STM32_PWR_PUCRA_OFFSET 0x0020 /* Power Port A pull-up control register */ +#define STM32_PWR_PDCRA_OFFSET 0x0024 /* Power Port A pull-down control register */ +#define STM32_PWR_PUCRB_OFFSET 0x0028 /* Power Port B pull-up control register */ +#define STM32_PWR_PDCRB_OFFSET 0x002C /* Power Port B pull-down control register */ +#define STM32_PWR_PUCRC_OFFSET 0x0030 /* Power Port C pull-up control register */ +#define STM32_PWR_PDCRC_OFFSET 0x0034 /* Power Port C pull-down control register */ +#define STM32_PWR_PUCRD_OFFSET 0x0038 /* Power Port D pull-up control register */ +#define STM32_PWR_PDCRD_OFFSET 0x003C /* Power Port D pull-down control register */ +#define STM32_PWR_PUCRE_OFFSET 0x0040 /* Power Port E pull-up control register */ +#define STM32_PWR_PDCRE_OFFSET 0x0044 /* Power Port E pull-down control register */ +#define STM32_PWR_PUCRF_OFFSET 0x0048 /* Power Port F pull-up control register */ +#define STM32_PWR_PDCRF_OFFSET 0x004C /* Power Port F pull-down control register */ +#define STM32_PWR_PUCRG_OFFSET 0x0050 /* Power Port G pull-up control register */ +#define STM32_PWR_PDCRG_OFFSET 0x0054 /* Power Port G pull-down control register */ +#define STM32_PWR_PUCRH_OFFSET 0x0058 /* Power Port H pull-up control register */ +#define STM32_PWR_PDCRH_OFFSET 0x005C /* Power Port H pull-down control register */ +#define STM32_PWR_PUCRI_OFFSET 0x0060 /* Power Port I pull-up control register */ +#define STM32_PWR_PDCRI_OFFSET 0x0064 /* Power Port I pull-down control register */ +#if defined(CONFIG_STM32_STM32L4XR) +# define STM32_PWR_CR5_OFFSET 0x0080 /* Power control register 5 */ #endif /* Register Addresses *******************************************************/ -#define STM32L4_PWR_CR1 (STM32L4_PWR_BASE+STM32L4_PWR_CR1_OFFSET) -#define STM32L4_PWR_CR2 (STM32L4_PWR_BASE+STM32L4_PWR_CR2_OFFSET) -#define STM32L4_PWR_CR3 (STM32L4_PWR_BASE+STM32L4_PWR_CR3_OFFSET) -#define STM32L4_PWR_CR4 (STM32L4_PWR_BASE+STM32L4_PWR_CR4_OFFSET) -#define STM32L4_PWR_SR1 (STM32L4_PWR_BASE+STM32L4_PWR_SR1_OFFSET) -#define STM32L4_PWR_SR2 (STM32L4_PWR_BASE+STM32L4_PWR_SR2_OFFSET) -#define STM32L4_PWR_SCR (STM32L4_PWR_BASE+STM32L4_PWR_SCR_OFFSET) -#define STM32L4_PWR_PUCRA (STM32L4_PWR_BASE+STM32L4_PWR_PUCRA_OFFSET) -#define STM32L4_PWR_PDCRA (STM32L4_PWR_BASE+STM32L4_PWR_PDCRA_OFFSET) -#define STM32L4_PWR_PUCRB (STM32L4_PWR_BASE+STM32L4_PWR_PUCRB_OFFSET) -#define STM32L4_PWR_PDCRB (STM32L4_PWR_BASE+STM32L4_PWR_PDCRB_OFFSET) -#define STM32L4_PWR_PUCRC (STM32L4_PWR_BASE+STM32L4_PWR_PUCRC_OFFSET) -#define STM32L4_PWR_PDCRC (STM32L4_PWR_BASE+STM32L4_PWR_PDCRC_OFFSET) -#define STM32L4_PWR_PUCRD (STM32L4_PWR_BASE+STM32L4_PWR_PUCRD_OFFSET) -#define STM32L4_PWR_PDCRD (STM32L4_PWR_BASE+STM32L4_PWR_PDCRD_OFFSET) -#define STM32L4_PWR_PUCRE (STM32L4_PWR_BASE+STM32L4_PWR_PUCRE_OFFSET) -#define STM32L4_PWR_PDCRE (STM32L4_PWR_BASE+STM32L4_PWR_PDCRE_OFFSET) -#define STM32L4_PWR_PUCRF (STM32L4_PWR_BASE+STM32L4_PWR_PUCRF_OFFSET) -#define STM32L4_PWR_PDCRF (STM32L4_PWR_BASE+STM32L4_PWR_PDCRF_OFFSET) -#define STM32L4_PWR_PUCRG (STM32L4_PWR_BASE+STM32L4_PWR_PUCRG_OFFSET) -#define STM32L4_PWR_PDCRG (STM32L4_PWR_BASE+STM32L4_PWR_PDCRG_OFFSET) -#define STM32L4_PWR_PUCRH (STM32L4_PWR_BASE+STM32L4_PWR_PUCRH_OFFSET) -#define STM32L4_PWR_PDCRH (STM32L4_PWR_BASE+STM32L4_PWR_PDCRH_OFFSET) -#define STM32L4_PWR_PUCRI (STM32L4_PWR_BASE+STM32L4_PWR_PUCRI_OFFSET) -#define STM32L4_PWR_PDCRI (STM32L4_PWR_BASE+STM32L4_PWR_PDCRI_OFFSET) -#if defined(CONFIG_STM32L4_STM32L4XR) -# define STM32L4_PWR_CR5 (STM32L4_PWR_BASE+STM32L4_PWR_CR5_OFFSET) +#define STM32_PWR_CR1 (STM32_PWR_BASE+STM32_PWR_CR1_OFFSET) +#define STM32_PWR_CR2 (STM32_PWR_BASE+STM32_PWR_CR2_OFFSET) +#define STM32_PWR_CR3 (STM32_PWR_BASE+STM32_PWR_CR3_OFFSET) +#define STM32_PWR_CR4 (STM32_PWR_BASE+STM32_PWR_CR4_OFFSET) +#define STM32_PWR_SR1 (STM32_PWR_BASE+STM32_PWR_SR1_OFFSET) +#define STM32_PWR_SR2 (STM32_PWR_BASE+STM32_PWR_SR2_OFFSET) +#define STM32_PWR_SCR (STM32_PWR_BASE+STM32_PWR_SCR_OFFSET) +#define STM32_PWR_PUCRA (STM32_PWR_BASE+STM32_PWR_PUCRA_OFFSET) +#define STM32_PWR_PDCRA (STM32_PWR_BASE+STM32_PWR_PDCRA_OFFSET) +#define STM32_PWR_PUCRB (STM32_PWR_BASE+STM32_PWR_PUCRB_OFFSET) +#define STM32_PWR_PDCRB (STM32_PWR_BASE+STM32_PWR_PDCRB_OFFSET) +#define STM32_PWR_PUCRC (STM32_PWR_BASE+STM32_PWR_PUCRC_OFFSET) +#define STM32_PWR_PDCRC (STM32_PWR_BASE+STM32_PWR_PDCRC_OFFSET) +#define STM32_PWR_PUCRD (STM32_PWR_BASE+STM32_PWR_PUCRD_OFFSET) +#define STM32_PWR_PDCRD (STM32_PWR_BASE+STM32_PWR_PDCRD_OFFSET) +#define STM32_PWR_PUCRE (STM32_PWR_BASE+STM32_PWR_PUCRE_OFFSET) +#define STM32_PWR_PDCRE (STM32_PWR_BASE+STM32_PWR_PDCRE_OFFSET) +#define STM32_PWR_PUCRF (STM32_PWR_BASE+STM32_PWR_PUCRF_OFFSET) +#define STM32_PWR_PDCRF (STM32_PWR_BASE+STM32_PWR_PDCRF_OFFSET) +#define STM32_PWR_PUCRG (STM32_PWR_BASE+STM32_PWR_PUCRG_OFFSET) +#define STM32_PWR_PDCRG (STM32_PWR_BASE+STM32_PWR_PDCRG_OFFSET) +#define STM32_PWR_PUCRH (STM32_PWR_BASE+STM32_PWR_PUCRH_OFFSET) +#define STM32_PWR_PDCRH (STM32_PWR_BASE+STM32_PWR_PDCRH_OFFSET) +#define STM32_PWR_PUCRI (STM32_PWR_BASE+STM32_PWR_PUCRI_OFFSET) +#define STM32_PWR_PDCRI (STM32_PWR_BASE+STM32_PWR_PDCRI_OFFSET) +#if defined(CONFIG_STM32_STM32L4XR) +# define STM32_PWR_CR5 (STM32_PWR_BASE+STM32_PWR_CR5_OFFSET) #endif /* Register Bitfield Definitions ********************************************/ @@ -107,7 +107,7 @@ # define PWR_CR1_LPMS_STOP2 (2 << PWR_CR1_LPMS_SHIFT) /* 010: Stop 2 mode */ # define PWR_CR1_LPMS_STANDBY (3 << PWR_CR1_LPMS_SHIFT) /* 011: Standby mode */ # define PWR_CR1_LPMS_SHUTDOWN (4 << PWR_CR1_LPMS_SHIFT) /* 1xx: Shutdown mode */ -#if defined(CONFIG_STM32L4_STM32L4XR) +#if defined(CONFIG_STM32_STM32L4XR) # define PWR_CR1_RRSTP (1 << 4) /* Bit 4: SRAM3 retention in Stop 2 mode */ #endif #define PWR_CR1_DBP (1 << 8) /* Bit 8: Disable Backup domain write protection */ @@ -133,12 +133,12 @@ # define PWR_CR2_PLS_EXT (7 << PWR_CR2_PLS_SHIFT) /* 111: External input analog voltage PVD_IN */ #define PWR_CR2_PVME1 (1 << 4) /* Bit 4: Peripheral voltage monitoring 1 enable (VDDUSB vs 1.2V) */ -#if !defined(CONFIG_STM32L4_STM32L4X3) +#if !defined(CONFIG_STM32_STM32L4X3) # define PWR_CR2_PVME2 (1 << 5) /* Bit 5: Peripheral voltage monitoring 2 enable (VDDIO2 vs 0.9V) */ #endif #define PWR_CR2_PVME3 (1 << 6) /* Bit 6: Peripheral voltage monitoring 3 enable (VDDA vs 1.62V) */ #define PWR_CR2_PVME4 (1 << 7) /* Bit 7: Peripheral voltage monitoring 4 enable (VDDA vs 2.2V) */ -#if !defined(CONFIG_STM32L4_STM32L4X3) +#if !defined(CONFIG_STM32_STM32L4X3) # define PWR_CR2_IOSV (1 << 9) /* Bit 9: VDDIO2 Independent I/Os supply valid */ #endif #define PWR_CR2_USV (1 << 10) /* Bit 10: VDDUSB USB supply valid */ @@ -152,7 +152,7 @@ #define PWR_CR3_EWUP5 (1 << 4) /* Bit 4: Enable Wakeup pin WKUP5 */ #define PWR_CR3_RRS (1 << 8) /* Bit 8: SRAM2 retention in Standby mode */ #define PWR_CR3_APC (1 << 10) /* Bit 10: Apply pull-up and pull-down configuration */ -#if defined(CONFIG_STM32L4_STM32L4XR) +#if defined(CONFIG_STM32_STM32L4XR) # define PWR_CR3_DSIPDEN (1 << 12) /* Bit 12: Enable Pull-down activation on DSI pins */ #endif #define PWR_CR3_EIWUL (1 << 15) /* Bit 15: Enable internal wakeup line */ @@ -187,7 +187,7 @@ #define PWR_SR2_VOSF (1 << 10) /* Bit 10: Voltage scaling flag */ #define PWR_SR2_PVDO (1 << 11) /* Bit 11: Power voltage detector output */ #define PWR_SR2_PVMO1 (1 << 12) /* Bit 12: Peripheral voltage monitoring output 1 (VDDUSB vs 1.2V) */ -#if !defined(CONFIG_STM32L4_STM32L4X3) +#if !defined(CONFIG_STM32_STM32L4X3) # define PWR_SR2_PVMO2 (1 << 13) /* Bit 13: Peripheral voltage monitoring output 2 (VDDIO2 vs 0.9V) */ #endif #define PWR_SR2_PVMO3 (1 << 14) /* Bit 14: Peripheral voltage monitoring output 3 (VDDA vs 1.62V) */ @@ -208,7 +208,7 @@ /* Power control register 5 */ -#if defined(CONFIG_STM32L4_STM32L4XR) +#if defined(CONFIG_STM32_STM32L4XR) # define PWR_CR5_R1MODE (1 << 8) /* Bit 8: Main regulator in Range 1 normal mode. */ #endif diff --git a/arch/arm/src/stm32l4/hardware/stm32l4_qspi.h b/arch/arm/src/stm32l4/hardware/stm32l4_qspi.h index 3a1b8214d2c86..80d7a52e1e59d 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4_qspi.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4_qspi.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_QSPI_H -#define __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_QSPI_H +#ifndef __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32_QSPI_H +#define __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32_QSPI_H /**************************************************************************** * Included Files @@ -38,40 +38,40 @@ /* General Characteristics **************************************************/ -#define STM32L4_QSPI_MINBITS 8 /* Minimum word width */ -#define STM32L4_QSPI_MAXBITS 32 /* Maximum word width */ +#define STM32_QSPI_MINBITS 8 /* Minimum word width */ +#define STM32_QSPI_MAXBITS 32 /* Maximum word width */ /* QSPI register offsets ****************************************************/ -#define STM32L4_QUADSPI_CR_OFFSET 0x0000 /* Control Register */ -#define STM32L4_QUADSPI_DCR_OFFSET 0x0004 /* Device Configuration Register */ -#define STM32L4_QUADSPI_SR_OFFSET 0x0008 /* Status Register */ -#define STM32L4_QUADSPI_FCR_OFFSET 0x000c /* Flag Clear Register */ -#define STM32L4_QUADSPI_DLR_OFFSET 0x0010 /* Data Length Register */ -#define STM32L4_QUADSPI_CCR_OFFSET 0x0014 /* Communication Configuration Register */ -#define STM32L4_QUADSPI_AR_OFFSET 0x0018 /* Address Register */ -#define STM32L4_QUADSPI_ABR_OFFSET 0x001c /* Alternate Bytes Register */ -#define STM32L4_QUADSPI_DR_OFFSET 0x0020 /* Data Register */ -#define STM32L4_QUADSPI_PSMKR_OFFSET 0x0024 /* Polling Status mask Register */ -#define STM32L4_QUADSPI_PSMAR_OFFSET 0x0028 /* Polling Status match Register */ -#define STM32L4_QUADSPI_PIR_OFFSET 0x002c /* Polling Interval Register */ -#define STM32L4_QUADSPI_LPTR_OFFSET 0x0030 /* Low-Power Timeout Register */ +#define STM32_QUADSPI_CR_OFFSET 0x0000 /* Control Register */ +#define STM32_QUADSPI_DCR_OFFSET 0x0004 /* Device Configuration Register */ +#define STM32_QUADSPI_SR_OFFSET 0x0008 /* Status Register */ +#define STM32_QUADSPI_FCR_OFFSET 0x000c /* Flag Clear Register */ +#define STM32_QUADSPI_DLR_OFFSET 0x0010 /* Data Length Register */ +#define STM32_QUADSPI_CCR_OFFSET 0x0014 /* Communication Configuration Register */ +#define STM32_QUADSPI_AR_OFFSET 0x0018 /* Address Register */ +#define STM32_QUADSPI_ABR_OFFSET 0x001c /* Alternate Bytes Register */ +#define STM32_QUADSPI_DR_OFFSET 0x0020 /* Data Register */ +#define STM32_QUADSPI_PSMKR_OFFSET 0x0024 /* Polling Status mask Register */ +#define STM32_QUADSPI_PSMAR_OFFSET 0x0028 /* Polling Status match Register */ +#define STM32_QUADSPI_PIR_OFFSET 0x002c /* Polling Interval Register */ +#define STM32_QUADSPI_LPTR_OFFSET 0x0030 /* Low-Power Timeout Register */ /* QSPI register addresses **************************************************/ -#define STM32L4_QUADSPI_CR (STM32L4_QSPI_BASE+STM32L4_QUADSPI_CR_OFFSET) /* Control Register */ -#define STM32L4_QUADSPI_DCR (STM32L4_QSPI_BASE+STM32L4_QUADSPI_DCR_OFFSET) /* Device Configuration Register */ -#define STM32L4_QUADSPI_SR (STM32L4_QSPI_BASE+STM32L4_QUADSPI_SR_OFFSET) /* Status Register */ -#define STM32L4_QUADSPI_FCR (STM32L4_QSPI_BASE+STM32L4_QUADSPI_FCR_OFFSET) /* Flag Clear Register */ -#define STM32L4_QUADSPI_DLR (STM32L4_QSPI_BASE+STM32L4_QUADSPI_DLR_OFFSET) /* Data Length Register */ -#define STM32L4_QUADSPI_CCR (STM32L4_QSPI_BASE+STM32L4_QUADSPI_CCR_OFFSET) /* Communication Configuration Register */ -#define STM32L4_QUADSPI_AR (STM32L4_QSPI_BASE+STM32L4_QUADSPI_AR_OFFSET) /* Address Register */ -#define STM32L4_QUADSPI_ABR (STM32L4_QSPI_BASE+STM32L4_QUADSPI_ABR_OFFSET) /* Alternate Bytes Register */ -#define STM32L4_QUADSPI_DR (STM32L4_QSPI_BASE+STM32L4_QUADSPI_DR_OFFSET) /* Data Register */ -#define STM32L4_QUADSPI_PSMKR (STM32L4_QSPI_BASE+STM32L4_QUADSPI_PSMKR_OFFSET) /* Polling Status mask Register */ -#define STM32L4_QUADSPI_PSMAR (STM32L4_QSPI_BASE+STM32L4_QUADSPI_PSMAR_OFFSET) /* Polling Status match Register */ -#define STM32L4_QUADSPI_PIR (STM32L4_QSPI_BASE+STM32L4_QUADSPI_PIR_OFFSET) /* Polling Interval Register */ -#define STM32L4_QUADSPI_LPTR (STM32L4_QSPI_BASE+STM32L4_QUADSPI_LPTR_OFFSET) /* Low-Power Timeout Register */ +#define STM32_QUADSPI_CR (STM32_QSPI_BASE+STM32_QUADSPI_CR_OFFSET) /* Control Register */ +#define STM32_QUADSPI_DCR (STM32_QSPI_BASE+STM32_QUADSPI_DCR_OFFSET) /* Device Configuration Register */ +#define STM32_QUADSPI_SR (STM32_QSPI_BASE+STM32_QUADSPI_SR_OFFSET) /* Status Register */ +#define STM32_QUADSPI_FCR (STM32_QSPI_BASE+STM32_QUADSPI_FCR_OFFSET) /* Flag Clear Register */ +#define STM32_QUADSPI_DLR (STM32_QSPI_BASE+STM32_QUADSPI_DLR_OFFSET) /* Data Length Register */ +#define STM32_QUADSPI_CCR (STM32_QSPI_BASE+STM32_QUADSPI_CCR_OFFSET) /* Communication Configuration Register */ +#define STM32_QUADSPI_AR (STM32_QSPI_BASE+STM32_QUADSPI_AR_OFFSET) /* Address Register */ +#define STM32_QUADSPI_ABR (STM32_QSPI_BASE+STM32_QUADSPI_ABR_OFFSET) /* Alternate Bytes Register */ +#define STM32_QUADSPI_DR (STM32_QSPI_BASE+STM32_QUADSPI_DR_OFFSET) /* Data Register */ +#define STM32_QUADSPI_PSMKR (STM32_QSPI_BASE+STM32_QUADSPI_PSMKR_OFFSET) /* Polling Status mask Register */ +#define STM32_QUADSPI_PSMAR (STM32_QSPI_BASE+STM32_QUADSPI_PSMAR_OFFSET) /* Polling Status match Register */ +#define STM32_QUADSPI_PIR (STM32_QSPI_BASE+STM32_QUADSPI_PIR_OFFSET) /* Polling Interval Register */ +#define STM32_QUADSPI_LPTR (STM32_QSPI_BASE+STM32_QUADSPI_LPTR_OFFSET) /* Low-Power Timeout Register */ /* QSPI register bit definitions ********************************************/ @@ -221,4 +221,4 @@ * Public Functions Prototypes ****************************************************************************/ -#endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_QSPI_H */ +#endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32_QSPI_H */ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4_rng.h b/arch/arm/src/stm32l4/hardware/stm32l4_rng.h index 387776eb2ab50..b7aafe108ca18 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4_rng.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4_rng.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_RNG_H -#define __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_RNG_H +#ifndef __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32_RNG_H +#define __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32_RNG_H /**************************************************************************** * Included Files @@ -36,15 +36,15 @@ /* Register Offsets *********************************************************/ -#define STM32L4_RNG_CR_OFFSET 0x0000 /* RNG Control Register */ -#define STM32L4_RNG_SR_OFFSET 0x0004 /* RNG Status Register */ -#define STM32L4_RNG_DR_OFFSET 0x0008 /* RNG Data Register */ +#define STM32_RNG_CR_OFFSET 0x0000 /* RNG Control Register */ +#define STM32_RNG_SR_OFFSET 0x0004 /* RNG Status Register */ +#define STM32_RNG_DR_OFFSET 0x0008 /* RNG Data Register */ /* Register Addresses *******************************************************/ -#define STM32L4_RNG_CR (STM32L4_RNG_BASE+STM32L4_RNG_CR_OFFSET) -#define STM32L4_RNG_SR (STM32L4_RNG_BASE+STM32L4_RNG_SR_OFFSET) -#define STM32L4_RNG_DR (STM32L4_RNG_BASE+STM32L4_RNG_DR_OFFSET) +#define STM32_RNG_CR (STM32_RNG_BASE+STM32_RNG_CR_OFFSET) +#define STM32_RNG_SR (STM32_RNG_BASE+STM32_RNG_SR_OFFSET) +#define STM32_RNG_DR (STM32_RNG_BASE+STM32_RNG_DR_OFFSET) /* Register Bitfield Definitions ********************************************/ @@ -61,4 +61,4 @@ #define RNG_SR_CEIS (1 << 5) /* Bit 5: Clock error interrupt status */ #define RNG_SR_SEIS (1 << 6) /* Bit 6: Seed error interrupt status */ -#endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_RNG_H */ +#endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32_RNG_H */ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4_rtcc.h b/arch/arm/src/stm32l4/hardware/stm32l4_rtcc.h index d2f1ad30b0863..c0f47afb6f680 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4_rtcc.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4_rtcc.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_RTCC_H -#define __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_RTCC_H +#ifndef __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32_RTCC_H +#define __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32_RTCC_H /**************************************************************************** * Pre-processor Definitions @@ -29,117 +29,117 @@ /* Register Offsets *********************************************************/ -#define STM32L4_RTC_TR_OFFSET 0x0000 /* RTC time register */ -#define STM32L4_RTC_DR_OFFSET 0x0004 /* RTC date register */ -#define STM32L4_RTC_CR_OFFSET 0x0008 /* RTC control register */ -#define STM32L4_RTC_ISR_OFFSET 0x000c /* RTC initialization and status register */ -#define STM32L4_RTC_PRER_OFFSET 0x0010 /* RTC prescaler register */ -#define STM32L4_RTC_WUTR_OFFSET 0x0014 /* RTC wakeup timer register */ -#define STM32L4_RTC_ALRMAR_OFFSET 0x001c /* RTC alarm A register */ -#define STM32L4_RTC_ALRMBR_OFFSET 0x0020 /* RTC alarm B register */ -#define STM32L4_RTC_WPR_OFFSET 0x0024 /* RTC write protection register */ -#define STM32L4_RTC_SSR_OFFSET 0x0028 /* RTC sub second register */ -#define STM32L4_RTC_SHIFTR_OFFSET 0x002c /* RTC shift control register */ -#define STM32L4_RTC_TSTR_OFFSET 0x0030 /* RTC time stamp time register */ -#define STM32L4_RTC_TSDR_OFFSET 0x0034 /* RTC time stamp date register */ -#define STM32L4_RTC_TSSSR_OFFSET 0x0038 /* RTC timestamp sub second register */ -#define STM32L4_RTC_CALR_OFFSET 0x003c /* RTC calibration register */ -#define STM32L4_RTC_TAMPCR_OFFSET 0x0040 /* RTC tamper configuration register */ -#define STM32L4_RTC_ALRMASSR_OFFSET 0x0044 /* RTC alarm A sub second register */ -#define STM32L4_RTC_ALRMBSSR_OFFSET 0x0048 /* RTC alarm B sub second register */ -#define STM32L4_RTC_OR_OFFSET 0x004c /* RTC option register */ - -#define STM32L4_RTC_BKR_OFFSET(n) (0x0050+((n)<<2)) -#define STM32L4_RTC_BK0R_OFFSET 0x0050 /* RTC backup register 0 */ -#define STM32L4_RTC_BK1R_OFFSET 0x0054 /* RTC backup register 1 */ -#define STM32L4_RTC_BK2R_OFFSET 0x0058 /* RTC backup register 2 */ -#define STM32L4_RTC_BK3R_OFFSET 0x005c /* RTC backup register 3 */ -#define STM32L4_RTC_BK4R_OFFSET 0x0060 /* RTC backup register 4 */ -#define STM32L4_RTC_BK5R_OFFSET 0x0064 /* RTC backup register 5 */ -#define STM32L4_RTC_BK6R_OFFSET 0x0068 /* RTC backup register 6 */ -#define STM32L4_RTC_BK7R_OFFSET 0x006c /* RTC backup register 7 */ -#define STM32L4_RTC_BK8R_OFFSET 0x0070 /* RTC backup register 8 */ -#define STM32L4_RTC_BK9R_OFFSET 0x0074 /* RTC backup register 9 */ -#define STM32L4_RTC_BK10R_OFFSET 0x0078 /* RTC backup register 10 */ -#define STM32L4_RTC_BK11R_OFFSET 0x007c /* RTC backup register 11 */ -#define STM32L4_RTC_BK12R_OFFSET 0x0080 /* RTC backup register 12 */ -#define STM32L4_RTC_BK13R_OFFSET 0x0084 /* RTC backup register 13 */ -#define STM32L4_RTC_BK14R_OFFSET 0x0088 /* RTC backup register 14 */ -#define STM32L4_RTC_BK15R_OFFSET 0x008c /* RTC backup register 15 */ -#define STM32L4_RTC_BK16R_OFFSET 0x0090 /* RTC backup register 16 */ -#define STM32L4_RTC_BK17R_OFFSET 0x0094 /* RTC backup register 17 */ -#define STM32L4_RTC_BK18R_OFFSET 0x0098 /* RTC backup register 18 */ -#define STM32L4_RTC_BK19R_OFFSET 0x009c /* RTC backup register 19 */ -#define STM32L4_RTC_BK20R_OFFSET 0x00a0 /* RTC backup register 20 */ -#define STM32L4_RTC_BK21R_OFFSET 0x00a4 /* RTC backup register 21 */ -#define STM32L4_RTC_BK22R_OFFSET 0x00a8 /* RTC backup register 22 */ -#define STM32L4_RTC_BK23R_OFFSET 0x00ac /* RTC backup register 23 */ -#define STM32L4_RTC_BK24R_OFFSET 0x00b0 /* RTC backup register 24 */ -#define STM32L4_RTC_BK25R_OFFSET 0x00b4 /* RTC backup register 25 */ -#define STM32L4_RTC_BK26R_OFFSET 0x00b8 /* RTC backup register 26 */ -#define STM32L4_RTC_BK27R_OFFSET 0x00bc /* RTC backup register 27 */ -#define STM32L4_RTC_BK28R_OFFSET 0x00c0 /* RTC backup register 28 */ -#define STM32L4_RTC_BK29R_OFFSET 0x00c4 /* RTC backup register 29 */ -#define STM32L4_RTC_BK30R_OFFSET 0x00c8 /* RTC backup register 30 */ -#define STM32L4_RTC_BK31R_OFFSET 0x00cc /* RTC backup register 31 */ +#define STM32_RTC_TR_OFFSET 0x0000 /* RTC time register */ +#define STM32_RTC_DR_OFFSET 0x0004 /* RTC date register */ +#define STM32_RTC_CR_OFFSET 0x0008 /* RTC control register */ +#define STM32_RTC_ISR_OFFSET 0x000c /* RTC initialization and status register */ +#define STM32_RTC_PRER_OFFSET 0x0010 /* RTC prescaler register */ +#define STM32_RTC_WUTR_OFFSET 0x0014 /* RTC wakeup timer register */ +#define STM32_RTC_ALRMAR_OFFSET 0x001c /* RTC alarm A register */ +#define STM32_RTC_ALRMBR_OFFSET 0x0020 /* RTC alarm B register */ +#define STM32_RTC_WPR_OFFSET 0x0024 /* RTC write protection register */ +#define STM32_RTC_SSR_OFFSET 0x0028 /* RTC sub second register */ +#define STM32_RTC_SHIFTR_OFFSET 0x002c /* RTC shift control register */ +#define STM32_RTC_TSTR_OFFSET 0x0030 /* RTC time stamp time register */ +#define STM32_RTC_TSDR_OFFSET 0x0034 /* RTC time stamp date register */ +#define STM32_RTC_TSSSR_OFFSET 0x0038 /* RTC timestamp sub second register */ +#define STM32_RTC_CALR_OFFSET 0x003c /* RTC calibration register */ +#define STM32_RTC_TAMPCR_OFFSET 0x0040 /* RTC tamper configuration register */ +#define STM32_RTC_ALRMASSR_OFFSET 0x0044 /* RTC alarm A sub second register */ +#define STM32_RTC_ALRMBSSR_OFFSET 0x0048 /* RTC alarm B sub second register */ +#define STM32_RTC_OR_OFFSET 0x004c /* RTC option register */ + +#define STM32_RTC_BKR_OFFSET(n) (0x0050+((n)<<2)) +#define STM32_RTC_BK0R_OFFSET 0x0050 /* RTC backup register 0 */ +#define STM32_RTC_BK1R_OFFSET 0x0054 /* RTC backup register 1 */ +#define STM32_RTC_BK2R_OFFSET 0x0058 /* RTC backup register 2 */ +#define STM32_RTC_BK3R_OFFSET 0x005c /* RTC backup register 3 */ +#define STM32_RTC_BK4R_OFFSET 0x0060 /* RTC backup register 4 */ +#define STM32_RTC_BK5R_OFFSET 0x0064 /* RTC backup register 5 */ +#define STM32_RTC_BK6R_OFFSET 0x0068 /* RTC backup register 6 */ +#define STM32_RTC_BK7R_OFFSET 0x006c /* RTC backup register 7 */ +#define STM32_RTC_BK8R_OFFSET 0x0070 /* RTC backup register 8 */ +#define STM32_RTC_BK9R_OFFSET 0x0074 /* RTC backup register 9 */ +#define STM32_RTC_BK10R_OFFSET 0x0078 /* RTC backup register 10 */ +#define STM32_RTC_BK11R_OFFSET 0x007c /* RTC backup register 11 */ +#define STM32_RTC_BK12R_OFFSET 0x0080 /* RTC backup register 12 */ +#define STM32_RTC_BK13R_OFFSET 0x0084 /* RTC backup register 13 */ +#define STM32_RTC_BK14R_OFFSET 0x0088 /* RTC backup register 14 */ +#define STM32_RTC_BK15R_OFFSET 0x008c /* RTC backup register 15 */ +#define STM32_RTC_BK16R_OFFSET 0x0090 /* RTC backup register 16 */ +#define STM32_RTC_BK17R_OFFSET 0x0094 /* RTC backup register 17 */ +#define STM32_RTC_BK18R_OFFSET 0x0098 /* RTC backup register 18 */ +#define STM32_RTC_BK19R_OFFSET 0x009c /* RTC backup register 19 */ +#define STM32_RTC_BK20R_OFFSET 0x00a0 /* RTC backup register 20 */ +#define STM32_RTC_BK21R_OFFSET 0x00a4 /* RTC backup register 21 */ +#define STM32_RTC_BK22R_OFFSET 0x00a8 /* RTC backup register 22 */ +#define STM32_RTC_BK23R_OFFSET 0x00ac /* RTC backup register 23 */ +#define STM32_RTC_BK24R_OFFSET 0x00b0 /* RTC backup register 24 */ +#define STM32_RTC_BK25R_OFFSET 0x00b4 /* RTC backup register 25 */ +#define STM32_RTC_BK26R_OFFSET 0x00b8 /* RTC backup register 26 */ +#define STM32_RTC_BK27R_OFFSET 0x00bc /* RTC backup register 27 */ +#define STM32_RTC_BK28R_OFFSET 0x00c0 /* RTC backup register 28 */ +#define STM32_RTC_BK29R_OFFSET 0x00c4 /* RTC backup register 29 */ +#define STM32_RTC_BK30R_OFFSET 0x00c8 /* RTC backup register 30 */ +#define STM32_RTC_BK31R_OFFSET 0x00cc /* RTC backup register 31 */ /* Register Addresses *******************************************************/ -#define STM32L4_RTC_TR (STM32L4_RTC_BASE+STM32L4_RTC_TR_OFFSET) -#define STM32L4_RTC_DR (STM32L4_RTC_BASE+STM32L4_RTC_DR_OFFSET) -#define STM32L4_RTC_CR (STM32L4_RTC_BASE+STM32L4_RTC_CR_OFFSET) -#define STM32L4_RTC_ISR (STM32L4_RTC_BASE+STM32L4_RTC_ISR_OFFSET) -#define STM32L4_RTC_PRER (STM32L4_RTC_BASE+STM32L4_RTC_PRER_OFFSET) -#define STM32L4_RTC_WUTR (STM32L4_RTC_BASE+STM32L4_RTC_WUTR_OFFSET) -#define STM32L4_RTC_ALRMAR (STM32L4_RTC_BASE+STM32L4_RTC_ALRMAR_OFFSET) -#define STM32L4_RTC_ALRMBR (STM32L4_RTC_BASE+STM32L4_RTC_ALRMBR_OFFSET) -#define STM32L4_RTC_WPR (STM32L4_RTC_BASE+STM32L4_RTC_WPR_OFFSET) -#define STM32L4_RTC_SSR (STM32L4_RTC_BASE+STM32L4_RTC_SSR_OFFSET) -#define STM32L4_RTC_SHIFTR (STM32L4_RTC_BASE+STM32L4_RTC_SHIFTR_OFFSET) -#define STM32L4_RTC_TSTR (STM32L4_RTC_BASE+STM32L4_RTC_TSTR_OFFSET) -#define STM32L4_RTC_TSDR (STM32L4_RTC_BASE+STM32L4_RTC_TSDR_OFFSET) -#define STM32L4_RTC_TSSSR (STM32L4_RTC_BASE+STM32L4_RTC_TSSSR_OFFSET) -#define STM32L4_RTC_CALR (STM32L4_RTC_BASE+STM32L4_RTC_CALR_OFFSET) -#define STM32L4_RTC_TAMPCR (STM32L4_RTC_BASE+STM32L4_RTC_TAMPCR_OFFSET) -#define STM32L4_RTC_ALRMASSR (STM32L4_RTC_BASE+STM32L4_RTC_ALRMASSR_OFFSET) -#define STM32L4_RTC_ALRMBSSR (STM32L4_RTC_BASE+STM32L4_RTC_ALRMBSSR_OFFSET) -#define STM32L4_RTC_OR (STM32L4_RTC_BASE+STM32L4_RTC_OR_OFFSET) - -#define STM32L4_RTC_BKR(n) (STM32L4_RTC_BASE+STM32L4_RTC_BKR_OFFSET(n)) -#define STM32L4_RTC_BK0R (STM32L4_RTC_BASE+STM32L4_RTC_BK0R_OFFSET) -#define STM32L4_RTC_BK1R (STM32L4_RTC_BASE+STM32L4_RTC_BK1R_OFFSET) -#define STM32L4_RTC_BK2R (STM32L4_RTC_BASE+STM32L4_RTC_BK2R_OFFSET) -#define STM32L4_RTC_BK3R (STM32L4_RTC_BASE+STM32L4_RTC_BK3R_OFFSET) -#define STM32L4_RTC_BK4R (STM32L4_RTC_BASE+STM32L4_RTC_BK4R_OFFSET) -#define STM32L4_RTC_BK5R (STM32L4_RTC_BASE+STM32L4_RTC_BK5R_OFFSET) -#define STM32L4_RTC_BK6R (STM32L4_RTC_BASE+STM32L4_RTC_BK6R_OFFSET) -#define STM32L4_RTC_BK7R (STM32L4_RTC_BASE+STM32L4_RTC_BK7R_OFFSET) -#define STM32L4_RTC_BK8R (STM32L4_RTC_BASE+STM32L4_RTC_BK8R_OFFSET) -#define STM32L4_RTC_BK9R (STM32L4_RTC_BASE+STM32L4_RTC_BK9R_OFFSET) -#define STM32L4_RTC_BK10R (STM32L4_RTC_BASE+STM32L4_RTC_BK10R_OFFSET) -#define STM32L4_RTC_BK11R (STM32L4_RTC_BASE+STM32L4_RTC_BK11R_OFFSET) -#define STM32L4_RTC_BK12R (STM32L4_RTC_BASE+STM32L4_RTC_BK12R_OFFSET) -#define STM32L4_RTC_BK13R (STM32L4_RTC_BASE+STM32L4_RTC_BK13R_OFFSET) -#define STM32L4_RTC_BK14R (STM32L4_RTC_BASE+STM32L4_RTC_BK14R_OFFSET) -#define STM32L4_RTC_BK15R (STM32L4_RTC_BASE+STM32L4_RTC_BK15R_OFFSET) -#define STM32L4_RTC_BK16R (STM32L4_RTC_BASE+STM32L4_RTC_BK16R_OFFSET) -#define STM32L4_RTC_BK17R (STM32L4_RTC_BASE+STM32L4_RTC_BK17R_OFFSET) -#define STM32L4_RTC_BK18R (STM32L4_RTC_BASE+STM32L4_RTC_BK18R_OFFSET) -#define STM32L4_RTC_BK19R (STM32L4_RTC_BASE+STM32L4_RTC_BK19R_OFFSET) -#define STM32L4_RTC_BK20R (STM32L4_RTC_BASE+STM32L4_RTC_BK20R_OFFSET) -#define STM32L4_RTC_BK21R (STM32L4_RTC_BASE+STM32L4_RTC_BK21R_OFFSET) -#define STM32L4_RTC_BK22R (STM32L4_RTC_BASE+STM32L4_RTC_BK22R_OFFSET) -#define STM32L4_RTC_BK23R (STM32L4_RTC_BASE+STM32L4_RTC_BK23R_OFFSET) -#define STM32L4_RTC_BK24R (STM32L4_RTC_BASE+STM32L4_RTC_BK24R_OFFSET) -#define STM32L4_RTC_BK25R (STM32L4_RTC_BASE+STM32L4_RTC_BK25R_OFFSET) -#define STM32L4_RTC_BK26R (STM32L4_RTC_BASE+STM32L4_RTC_BK26R_OFFSET) -#define STM32L4_RTC_BK27R (STM32L4_RTC_BASE+STM32L4_RTC_BK27R_OFFSET) -#define STM32L4_RTC_BK28R (STM32L4_RTC_BASE+STM32L4_RTC_BK28R_OFFSET) -#define STM32L4_RTC_BK29R (STM32L4_RTC_BASE+STM32L4_RTC_BK29R_OFFSET) -#define STM32L4_RTC_BK30R (STM32L4_RTC_BASE+STM32L4_RTC_BK30R_OFFSET) -#define STM32L4_RTC_BK31R (STM32L4_RTC_BASE+STM32L4_RTC_BK31R_OFFSET) - -# define STM32L4_RTC_BKCOUNT 32 +#define STM32_RTC_TR (STM32_RTC_BASE+STM32_RTC_TR_OFFSET) +#define STM32_RTC_DR (STM32_RTC_BASE+STM32_RTC_DR_OFFSET) +#define STM32_RTC_CR (STM32_RTC_BASE+STM32_RTC_CR_OFFSET) +#define STM32_RTC_ISR (STM32_RTC_BASE+STM32_RTC_ISR_OFFSET) +#define STM32_RTC_PRER (STM32_RTC_BASE+STM32_RTC_PRER_OFFSET) +#define STM32_RTC_WUTR (STM32_RTC_BASE+STM32_RTC_WUTR_OFFSET) +#define STM32_RTC_ALRMAR (STM32_RTC_BASE+STM32_RTC_ALRMAR_OFFSET) +#define STM32_RTC_ALRMBR (STM32_RTC_BASE+STM32_RTC_ALRMBR_OFFSET) +#define STM32_RTC_WPR (STM32_RTC_BASE+STM32_RTC_WPR_OFFSET) +#define STM32_RTC_SSR (STM32_RTC_BASE+STM32_RTC_SSR_OFFSET) +#define STM32_RTC_SHIFTR (STM32_RTC_BASE+STM32_RTC_SHIFTR_OFFSET) +#define STM32_RTC_TSTR (STM32_RTC_BASE+STM32_RTC_TSTR_OFFSET) +#define STM32_RTC_TSDR (STM32_RTC_BASE+STM32_RTC_TSDR_OFFSET) +#define STM32_RTC_TSSSR (STM32_RTC_BASE+STM32_RTC_TSSSR_OFFSET) +#define STM32_RTC_CALR (STM32_RTC_BASE+STM32_RTC_CALR_OFFSET) +#define STM32_RTC_TAMPCR (STM32_RTC_BASE+STM32_RTC_TAMPCR_OFFSET) +#define STM32_RTC_ALRMASSR (STM32_RTC_BASE+STM32_RTC_ALRMASSR_OFFSET) +#define STM32_RTC_ALRMBSSR (STM32_RTC_BASE+STM32_RTC_ALRMBSSR_OFFSET) +#define STM32_RTC_OR (STM32_RTC_BASE+STM32_RTC_OR_OFFSET) + +#define STM32_RTC_BKR(n) (STM32_RTC_BASE+STM32_RTC_BKR_OFFSET(n)) +#define STM32_RTC_BK0R (STM32_RTC_BASE+STM32_RTC_BK0R_OFFSET) +#define STM32_RTC_BK1R (STM32_RTC_BASE+STM32_RTC_BK1R_OFFSET) +#define STM32_RTC_BK2R (STM32_RTC_BASE+STM32_RTC_BK2R_OFFSET) +#define STM32_RTC_BK3R (STM32_RTC_BASE+STM32_RTC_BK3R_OFFSET) +#define STM32_RTC_BK4R (STM32_RTC_BASE+STM32_RTC_BK4R_OFFSET) +#define STM32_RTC_BK5R (STM32_RTC_BASE+STM32_RTC_BK5R_OFFSET) +#define STM32_RTC_BK6R (STM32_RTC_BASE+STM32_RTC_BK6R_OFFSET) +#define STM32_RTC_BK7R (STM32_RTC_BASE+STM32_RTC_BK7R_OFFSET) +#define STM32_RTC_BK8R (STM32_RTC_BASE+STM32_RTC_BK8R_OFFSET) +#define STM32_RTC_BK9R (STM32_RTC_BASE+STM32_RTC_BK9R_OFFSET) +#define STM32_RTC_BK10R (STM32_RTC_BASE+STM32_RTC_BK10R_OFFSET) +#define STM32_RTC_BK11R (STM32_RTC_BASE+STM32_RTC_BK11R_OFFSET) +#define STM32_RTC_BK12R (STM32_RTC_BASE+STM32_RTC_BK12R_OFFSET) +#define STM32_RTC_BK13R (STM32_RTC_BASE+STM32_RTC_BK13R_OFFSET) +#define STM32_RTC_BK14R (STM32_RTC_BASE+STM32_RTC_BK14R_OFFSET) +#define STM32_RTC_BK15R (STM32_RTC_BASE+STM32_RTC_BK15R_OFFSET) +#define STM32_RTC_BK16R (STM32_RTC_BASE+STM32_RTC_BK16R_OFFSET) +#define STM32_RTC_BK17R (STM32_RTC_BASE+STM32_RTC_BK17R_OFFSET) +#define STM32_RTC_BK18R (STM32_RTC_BASE+STM32_RTC_BK18R_OFFSET) +#define STM32_RTC_BK19R (STM32_RTC_BASE+STM32_RTC_BK19R_OFFSET) +#define STM32_RTC_BK20R (STM32_RTC_BASE+STM32_RTC_BK20R_OFFSET) +#define STM32_RTC_BK21R (STM32_RTC_BASE+STM32_RTC_BK21R_OFFSET) +#define STM32_RTC_BK22R (STM32_RTC_BASE+STM32_RTC_BK22R_OFFSET) +#define STM32_RTC_BK23R (STM32_RTC_BASE+STM32_RTC_BK23R_OFFSET) +#define STM32_RTC_BK24R (STM32_RTC_BASE+STM32_RTC_BK24R_OFFSET) +#define STM32_RTC_BK25R (STM32_RTC_BASE+STM32_RTC_BK25R_OFFSET) +#define STM32_RTC_BK26R (STM32_RTC_BASE+STM32_RTC_BK26R_OFFSET) +#define STM32_RTC_BK27R (STM32_RTC_BASE+STM32_RTC_BK27R_OFFSET) +#define STM32_RTC_BK28R (STM32_RTC_BASE+STM32_RTC_BK28R_OFFSET) +#define STM32_RTC_BK29R (STM32_RTC_BASE+STM32_RTC_BK29R_OFFSET) +#define STM32_RTC_BK30R (STM32_RTC_BASE+STM32_RTC_BK30R_OFFSET) +#define STM32_RTC_BK31R (STM32_RTC_BASE+STM32_RTC_BK31R_OFFSET) + +# define STM32_RTC_BKCOUNT 32 /* Register Bitfield Definitions ********************************************/ @@ -388,4 +388,4 @@ #define RTC_OR_ALARMTYPE (1 << 0) /* Bit 0: RTC alarm type on PC13, pushpull/OD */ #define RTC_OR_OUTRMP (1 << 1) /* Bit 1: remap output to PB2 */ -#endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_RTCC_H */ +#endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32_RTCC_H */ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4_sai.h b/arch/arm/src/stm32l4/hardware/stm32l4_sai.h index ea33be29c5270..3dc1e420552eb 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4_sai.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4_sai.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_SAI_H -#define __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_SAI_H +#ifndef __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32_SAI_H +#define __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32_SAI_H /**************************************************************************** * Included Files @@ -36,67 +36,67 @@ /* Register Offsets *********************************************************/ -#define STM32L4_SAI_GCR_OFFSET 0x0000 /* SAI Global Configuration Register */ +#define STM32_SAI_GCR_OFFSET 0x0000 /* SAI Global Configuration Register */ -#define STM32L4_SAI_A_OFFSET 0x0004 -#define STM32L4_SAI_B_OFFSET 0x0024 +#define STM32_SAI_A_OFFSET 0x0004 +#define STM32_SAI_B_OFFSET 0x0024 -#define STM32L4_SAI_CR1_OFFSET 0x0000 /* SAI Configuration Register 1 A */ -#define STM32L4_SAI_CR2_OFFSET 0x0004 /* SAI Configuration Register 2 A */ -#define STM32L4_SAI_FRCR_OFFSET 0x0008 /* SAI Frame Configuration Register A */ -#define STM32L4_SAI_SLOTR_OFFSET 0x000c /* SAI Slot Register A */ -#define STM32L4_SAI_IM_OFFSET 0x0010 /* SAI Interrupt Mask Register 2 A */ -#define STM32L4_SAI_SR_OFFSET 0x0014 /* SAI Status Register A */ -#define STM32L4_SAI_CLRFR_OFFSET 0x0018 /* SAI Clear Flag Register A */ -#define STM32L4_SAI_DR_OFFSET 0x001c /* SAI Data Register A */ +#define STM32_SAI_CR1_OFFSET 0x0000 /* SAI Configuration Register 1 A */ +#define STM32_SAI_CR2_OFFSET 0x0004 /* SAI Configuration Register 2 A */ +#define STM32_SAI_FRCR_OFFSET 0x0008 /* SAI Frame Configuration Register A */ +#define STM32_SAI_SLOTR_OFFSET 0x000c /* SAI Slot Register A */ +#define STM32_SAI_IM_OFFSET 0x0010 /* SAI Interrupt Mask Register 2 A */ +#define STM32_SAI_SR_OFFSET 0x0014 /* SAI Status Register A */ +#define STM32_SAI_CLRFR_OFFSET 0x0018 /* SAI Clear Flag Register A */ +#define STM32_SAI_DR_OFFSET 0x001c /* SAI Data Register A */ /* Register Addresses *******************************************************/ -#define STM32L4_SAI1_GCR (STM32L4_SAI_GCR_OFFSET) - -#define STM32L4_SAI1_A_BASE (STM32L4_SAI1_BASE+STM32L4_SAI_A_OFFSET) -#define STM32L4_SAI1_B_BASE (STM32L4_SAI1_BASE+STM32L4_SAI_B_OFFSET) - -#define STM32L4_SAI1_ACR1 (STM32L4_SAI1_A_BASE+STM32L4_SAI_ACR1_OFFSET) -#define STM32L4_SAI1_ACR2 (STM32L4_SAI1_A_BASE+STM32L4_SAI_ACR2_OFFSET) -#define STM32L4_SAI1_AFRCR (STM32L4_SAI1_A_BASE+STM32L4_SAI_AFRCR_OFFSET) -#define STM32L4_SAI1_ASLOTR (STM32L4_SAI1_A_BASE+STM32L4_SAI_ASLOTR_OFFSET) -#define STM32L4_SAI1_AIM (STM32L4_SAI1_A_BASE+STM32L4_SAI_AIM_OFFSET) -#define STM32L4_SAI1_ASR (STM32L4_SAI1_A_BASE+STM32L4_SAI_ASR_OFFSET) -#define STM32L4_SAI1_ACLRFR (STM32L4_SAI1_A_BASE+STM32L4_SAI_ACLRFR_OFFSET) -#define STM32L4_SAI1_ADR (STM32L4_SAI1_A_BASE+STM32L4_SAI_ADR_OFFSET) - -#define STM32L4_SAI1_BCR1 (STM32L4_SAI1_B_BASE+STM32L4_SAI_BCR1_OFFSET) -#define STM32L4_SAI1_BCR2 (STM32L4_SAI1_B_BASE+STM32L4_SAI_BCR2_OFFSET) -#define STM32L4_SAI1_BFRCR (STM32L4_SAI1_B_BASE+STM32L4_SAI_BFRCR_OFFSET) -#define STM32L4_SAI1_BSLOTR (STM32L4_SAI1_B_BASE+STM32L4_SAI_BSLOTR_OFFSET) -#define STM32L4_SAI1_BIM (STM32L4_SAI1_B_BASE+STM32L4_SAI_BIM_OFFSET) -#define STM32L4_SAI1_BSR (STM32L4_SAI1_B_BASE+STM32L4_SAI_BSR_OFFSET) -#define STM32L4_SAI1_BCLRFR (STM32L4_SAI1_B_BASE+STM32L4_SAI_BCLRFR_OFFSET) -#define STM32L4_SAI1_BDR (STM32L4_SAI1_B_BASE+STM32L4_SAI_BDR_OFFSET) - -#define STM32L4_SAI2_GCR (STM32L4_SAI2_BASE+STM32L4_SAI_GCR_OFFSET) - -#define STM32L4_SAI2_A_BASE (STM32L4_SAI2_BASE+STM32L4_SAI_A_OFFSET) -#define STM32L4_SAI2_B_BASE (STM32L4_SAI2_BASE+STM32L4_SAI_B_OFFSET) - -#define STM32L4_SAI2_ACR1 (STM32L4_SAI2_A_BASE+STM32L4_SAI_ACR1_OFFSET) -#define STM32L4_SAI2_ACR2 (STM32L4_SAI2_A_BASE+STM32L4_SAI_ACR2_OFFSET) -#define STM32L4_SAI2_AFRCR (STM32L4_SAI2_A_BASE+STM32L4_SAI_AFRCR_OFFSET) -#define STM32L4_SAI2_ASLOTR (STM32L4_SAI2_A_BASE+STM32L4_SAI_ASLOTR_OFFSET) -#define STM32L4_SAI2_AIM (STM32L4_SAI2_A_BASE+STM32L4_SAI_AIM_OFFSET) -#define STM32L4_SAI2_ASR (STM32L4_SAI2_A_BASE+STM32L4_SAI_ASR_OFFSET) -#define STM32L4_SAI2_ACLRFR (STM32L4_SAI2_A_BASE+STM32L4_SAI_ACLRFR_OFFSET) -#define STM32L4_SAI2_ADR (STM32L4_SAI2_A_BASE+STM32L4_SAI_ADR_OFFSET) - -#define STM32L4_SAI2_BCR1 (STM32L4_SAI2_B_BASE+STM32L4_SAI_BCR1_OFFSET) -#define STM32L4_SAI2_BCR2 (STM32L4_SAI2_B_BASE+STM32L4_SAI_BCR2_OFFSET) -#define STM32L4_SAI2_BFRCR (STM32L4_SAI2_B_BASE+STM32L4_SAI_BFRCR_OFFSET) -#define STM32L4_SAI2_BSLOTR (STM32L4_SAI2_B_BASE+STM32L4_SAI_BSLOTR_OFFSET) -#define STM32L4_SAI2_BIM (STM32L4_SAI2_B_BASE+STM32L4_SAI_BIM_OFFSET) -#define STM32L4_SAI2_BSR (STM32L4_SAI2_B_BASE+STM32L4_SAI_BSR_OFFSET) -#define STM32L4_SAI2_BCLRFR (STM32L4_SAI2_B_BASE+STM32L4_SAI_BCLRFR_OFFSET) -#define STM32L4_SAI2_BDR (STM32L4_SAI2_B_BASE+STM32L4_SAI_BDR_OFFSET) +#define STM32_SAI1_GCR (STM32_SAI_GCR_OFFSET) + +#define STM32_SAI1_A_BASE (STM32_SAI1_BASE+STM32_SAI_A_OFFSET) +#define STM32_SAI1_B_BASE (STM32_SAI1_BASE+STM32_SAI_B_OFFSET) + +#define STM32_SAI1_ACR1 (STM32_SAI1_A_BASE+STM32_SAI_ACR1_OFFSET) +#define STM32_SAI1_ACR2 (STM32_SAI1_A_BASE+STM32_SAI_ACR2_OFFSET) +#define STM32_SAI1_AFRCR (STM32_SAI1_A_BASE+STM32_SAI_AFRCR_OFFSET) +#define STM32_SAI1_ASLOTR (STM32_SAI1_A_BASE+STM32_SAI_ASLOTR_OFFSET) +#define STM32_SAI1_AIM (STM32_SAI1_A_BASE+STM32_SAI_AIM_OFFSET) +#define STM32_SAI1_ASR (STM32_SAI1_A_BASE+STM32_SAI_ASR_OFFSET) +#define STM32_SAI1_ACLRFR (STM32_SAI1_A_BASE+STM32_SAI_ACLRFR_OFFSET) +#define STM32_SAI1_ADR (STM32_SAI1_A_BASE+STM32_SAI_ADR_OFFSET) + +#define STM32_SAI1_BCR1 (STM32_SAI1_B_BASE+STM32_SAI_BCR1_OFFSET) +#define STM32_SAI1_BCR2 (STM32_SAI1_B_BASE+STM32_SAI_BCR2_OFFSET) +#define STM32_SAI1_BFRCR (STM32_SAI1_B_BASE+STM32_SAI_BFRCR_OFFSET) +#define STM32_SAI1_BSLOTR (STM32_SAI1_B_BASE+STM32_SAI_BSLOTR_OFFSET) +#define STM32_SAI1_BIM (STM32_SAI1_B_BASE+STM32_SAI_BIM_OFFSET) +#define STM32_SAI1_BSR (STM32_SAI1_B_BASE+STM32_SAI_BSR_OFFSET) +#define STM32_SAI1_BCLRFR (STM32_SAI1_B_BASE+STM32_SAI_BCLRFR_OFFSET) +#define STM32_SAI1_BDR (STM32_SAI1_B_BASE+STM32_SAI_BDR_OFFSET) + +#define STM32_SAI2_GCR (STM32_SAI2_BASE+STM32_SAI_GCR_OFFSET) + +#define STM32_SAI2_A_BASE (STM32_SAI2_BASE+STM32_SAI_A_OFFSET) +#define STM32_SAI2_B_BASE (STM32_SAI2_BASE+STM32_SAI_B_OFFSET) + +#define STM32_SAI2_ACR1 (STM32_SAI2_A_BASE+STM32_SAI_ACR1_OFFSET) +#define STM32_SAI2_ACR2 (STM32_SAI2_A_BASE+STM32_SAI_ACR2_OFFSET) +#define STM32_SAI2_AFRCR (STM32_SAI2_A_BASE+STM32_SAI_AFRCR_OFFSET) +#define STM32_SAI2_ASLOTR (STM32_SAI2_A_BASE+STM32_SAI_ASLOTR_OFFSET) +#define STM32_SAI2_AIM (STM32_SAI2_A_BASE+STM32_SAI_AIM_OFFSET) +#define STM32_SAI2_ASR (STM32_SAI2_A_BASE+STM32_SAI_ASR_OFFSET) +#define STM32_SAI2_ACLRFR (STM32_SAI2_A_BASE+STM32_SAI_ACLRFR_OFFSET) +#define STM32_SAI2_ADR (STM32_SAI2_A_BASE+STM32_SAI_ADR_OFFSET) + +#define STM32_SAI2_BCR1 (STM32_SAI2_B_BASE+STM32_SAI_BCR1_OFFSET) +#define STM32_SAI2_BCR2 (STM32_SAI2_B_BASE+STM32_SAI_BCR2_OFFSET) +#define STM32_SAI2_BFRCR (STM32_SAI2_B_BASE+STM32_SAI_BFRCR_OFFSET) +#define STM32_SAI2_BSLOTR (STM32_SAI2_B_BASE+STM32_SAI_BSLOTR_OFFSET) +#define STM32_SAI2_BIM (STM32_SAI2_B_BASE+STM32_SAI_BIM_OFFSET) +#define STM32_SAI2_BSR (STM32_SAI2_B_BASE+STM32_SAI_BSR_OFFSET) +#define STM32_SAI2_BCLRFR (STM32_SAI2_B_BASE+STM32_SAI_BCLRFR_OFFSET) +#define STM32_SAI2_BDR (STM32_SAI2_B_BASE+STM32_SAI_BDR_OFFSET) /* Register Bitfield Definitions ********************************************/ @@ -259,4 +259,4 @@ /* SAI Data Register (32-bit data) */ -#endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_SAI_H */ +#endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32_SAI_H */ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4_sdmmc.h b/arch/arm/src/stm32l4/hardware/stm32l4_sdmmc.h index 00cebe249dd8b..7749c402716d3 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4_sdmmc.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4_sdmmc.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_SDMMC_H -#define __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_SDMMC_H +#ifndef __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32_SDMMC_H +#define __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32_SDMMC_H /**************************************************************************** * Pre-processor Definitions diff --git a/arch/arm/src/stm32l4/hardware/stm32l4_spi.h b/arch/arm/src/stm32l4/hardware/stm32l4_spi.h index 6098c3949d376..060a9978451c4 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4_spi.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4_spi.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_SPI_H -#define __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_SPI_H +#ifndef __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32_SPI_H +#define __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32_SPI_H /**************************************************************************** * Included Files @@ -36,48 +36,48 @@ /* Maximum allowed speed as per specifications for all SPIs */ -#define STM32L4_SPI_CLK_MAX 40000000UL +#define STM32_SPI_CLK_MAX 40000000UL /* Register Offsets *********************************************************/ -#define STM32L4_SPI_CR1_OFFSET 0x0000 /* SPI Control Register 1 (16-bit) */ -#define STM32L4_SPI_CR2_OFFSET 0x0004 /* SPI control register 2 (16-bit) */ -#define STM32L4_SPI_SR_OFFSET 0x0008 /* SPI status register (16-bit) */ -#define STM32L4_SPI_DR_OFFSET 0x000c /* SPI data register (16-bit) */ -#define STM32L4_SPI_CRCPR_OFFSET 0x0010 /* SPI CRC polynomial register (16-bit) */ -#define STM32L4_SPI_RXCRCR_OFFSET 0x0014 /* SPI Rx CRC register (16-bit) */ -#define STM32L4_SPI_TXCRCR_OFFSET 0x0018 /* SPI Tx CRC register (16-bit) */ +#define STM32_SPI_CR1_OFFSET 0x0000 /* SPI Control Register 1 (16-bit) */ +#define STM32_SPI_CR2_OFFSET 0x0004 /* SPI control register 2 (16-bit) */ +#define STM32_SPI_SR_OFFSET 0x0008 /* SPI status register (16-bit) */ +#define STM32_SPI_DR_OFFSET 0x000c /* SPI data register (16-bit) */ +#define STM32_SPI_CRCPR_OFFSET 0x0010 /* SPI CRC polynomial register (16-bit) */ +#define STM32_SPI_RXCRCR_OFFSET 0x0014 /* SPI Rx CRC register (16-bit) */ +#define STM32_SPI_TXCRCR_OFFSET 0x0018 /* SPI Tx CRC register (16-bit) */ /* Register Addresses *******************************************************/ -#if STM32L4_NSPI > 0 -# define STM32L4_SPI1_CR1 (STM32L4_SPI1_BASE+STM32L4_SPI_CR1_OFFSET) -# define STM32L4_SPI1_CR2 (STM32L4_SPI1_BASE+STM32L4_SPI_CR2_OFFSET) -# define STM32L4_SPI1_SR (STM32L4_SPI1_BASE+STM32L4_SPI_SR_OFFSET) -# define STM32L4_SPI1_DR (STM32L4_SPI1_BASE+STM32L4_SPI_DR_OFFSET) -# define STM32L4_SPI1_CRCPR (STM32L4_SPI1_BASE+STM32L4_SPI_CRCPR_OFFSET) -# define STM32L4_SPI1_RXCRCR (STM32L4_SPI1_BASE+STM32L4_SPI_RXCRCR_OFFSET) -# define STM32L4_SPI1_TXCRCR (STM32L4_SPI1_BASE+STM32L4_SPI_TXCRCR_OFFSET) +#if STM32_NSPI > 0 +# define STM32_SPI1_CR1 (STM32_SPI1_BASE+STM32_SPI_CR1_OFFSET) +# define STM32_SPI1_CR2 (STM32_SPI1_BASE+STM32_SPI_CR2_OFFSET) +# define STM32_SPI1_SR (STM32_SPI1_BASE+STM32_SPI_SR_OFFSET) +# define STM32_SPI1_DR (STM32_SPI1_BASE+STM32_SPI_DR_OFFSET) +# define STM32_SPI1_CRCPR (STM32_SPI1_BASE+STM32_SPI_CRCPR_OFFSET) +# define STM32_SPI1_RXCRCR (STM32_SPI1_BASE+STM32_SPI_RXCRCR_OFFSET) +# define STM32_SPI1_TXCRCR (STM32_SPI1_BASE+STM32_SPI_TXCRCR_OFFSET) #endif -#if STM32L4_NSPI > 1 -# define STM32L4_SPI2_CR1 (STM32L4_SPI2_BASE+STM32L4_SPI_CR1_OFFSET) -# define STM32L4_SPI2_CR2 (STM32L4_SPI2_BASE+STM32L4_SPI_CR2_OFFSET) -# define STM32L4_SPI2_SR (STM32L4_SPI2_BASE+STM32L4_SPI_SR_OFFSET) -# define STM32L4_SPI2_DR (STM32L4_SPI2_BASE+STM32L4_SPI_DR_OFFSET) -# define STM32L4_SPI2_CRCPR (STM32L4_SPI2_BASE+STM32L4_SPI_CRCPR_OFFSET) -# define STM32L4_SPI2_RXCRCR (STM32L4_SPI2_BASE+STM32L4_SPI_RXCRCR_OFFSET) -# define STM32L4_SPI2_TXCRCR (STM32L4_SPI2_BASE+STM32L4_SPI_TXCRCR_OFFSET) +#if STM32_NSPI > 1 +# define STM32_SPI2_CR1 (STM32_SPI2_BASE+STM32_SPI_CR1_OFFSET) +# define STM32_SPI2_CR2 (STM32_SPI2_BASE+STM32_SPI_CR2_OFFSET) +# define STM32_SPI2_SR (STM32_SPI2_BASE+STM32_SPI_SR_OFFSET) +# define STM32_SPI2_DR (STM32_SPI2_BASE+STM32_SPI_DR_OFFSET) +# define STM32_SPI2_CRCPR (STM32_SPI2_BASE+STM32_SPI_CRCPR_OFFSET) +# define STM32_SPI2_RXCRCR (STM32_SPI2_BASE+STM32_SPI_RXCRCR_OFFSET) +# define STM32_SPI2_TXCRCR (STM32_SPI2_BASE+STM32_SPI_TXCRCR_OFFSET) #endif -#if STM32L4_NSPI > 2 -# define STM32L4_SPI3_CR1 (STM32L4_SPI3_BASE+STM32L4_SPI_CR1_OFFSET) -# define STM32L4_SPI3_CR2 (STM32L4_SPI3_BASE+STM32L4_SPI_CR2_OFFSET) -# define STM32L4_SPI3_SR (STM32L4_SPI3_BASE+STM32L4_SPI_SR_OFFSET) -# define STM32L4_SPI3_DR (STM32L4_SPI3_BASE+STM32L4_SPI_DR_OFFSET) -# define STM32L4_SPI3_CRCPR (STM32L4_SPI3_BASE+STM32L4_SPI_CRCPR_OFFSET) -# define STM32L4_SPI3_RXCRCR (STM32L4_SPI3_BASE+STM32L4_SPI_RXCRCR_OFFSET) -# define STM32L4_SPI3_TXCRCR (STM32L4_SPI3_BASE+STM32L4_SPI_TXCRCR_OFFSET) +#if STM32_NSPI > 2 +# define STM32_SPI3_CR1 (STM32_SPI3_BASE+STM32_SPI_CR1_OFFSET) +# define STM32_SPI3_CR2 (STM32_SPI3_BASE+STM32_SPI_CR2_OFFSET) +# define STM32_SPI3_SR (STM32_SPI3_BASE+STM32_SPI_SR_OFFSET) +# define STM32_SPI3_DR (STM32_SPI3_BASE+STM32_SPI_DR_OFFSET) +# define STM32_SPI3_CRCPR (STM32_SPI3_BASE+STM32_SPI_CRCPR_OFFSET) +# define STM32_SPI3_RXCRCR (STM32_SPI3_BASE+STM32_SPI_RXCRCR_OFFSET) +# define STM32_SPI3_TXCRCR (STM32_SPI3_BASE+STM32_SPI_TXCRCR_OFFSET) #endif /* Register Bitfield Definitions ********************************************/ @@ -162,4 +162,4 @@ # define SPI_SR_FTLVL_HALF (2 << SPI_SR_FTLVL_SHIFT) /* 1/2 FIFO */ # define SPI_SR_FTLVL_FULL (3 << SPI_SR_FTLVL_SHIFT) /* FIFO full */ -#endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_SPI_H */ +#endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32_SPI_H */ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4_syscfg.h b/arch/arm/src/stm32l4/hardware/stm32l4_syscfg.h index a038906b332e7..23e4bf662da76 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4_syscfg.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4_syscfg.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_SYSCFG_H -#define __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_SYSCFG_H +#ifndef __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32_SYSCFG_H +#define __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32_SYSCFG_H /**************************************************************************** * Included Files @@ -30,16 +30,16 @@ #include #include "chip.h" -#if defined(CONFIG_STM32L4_STM32L4X3) +#if defined(CONFIG_STM32_STM32L4X3) # include "hardware/stm32l4x3xx_syscfg.h" -#elif defined(CONFIG_STM32L4_STM32L4X5) +#elif defined(CONFIG_STM32_STM32L4X5) # include "hardware/stm32l4x5xx_syscfg.h" -#elif defined(CONFIG_STM32L4_STM32L4X6) +#elif defined(CONFIG_STM32_STM32L4X6) # include "hardware/stm32l4x6xx_syscfg.h" -#elif defined(CONFIG_STM32L4_STM32L4XR) +#elif defined(CONFIG_STM32_STM32L4XR) # include "hardware/stm32l4xrxx_syscfg.h" #else # error "Unsupported STM32 L4 chip" #endif -#endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_SYSCFG_H */ +#endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32_SYSCFG_H */ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4_tim.h b/arch/arm/src/stm32l4/hardware/stm32l4_tim.h index b643e79014eef..0baadf3c961d4 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4_tim.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4_tim.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_TIM_H -#define __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_TIM_H +#ifndef __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32_TIM_H +#define __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32_TIM_H /**************************************************************************** * Pre-processor Definitions @@ -31,14 +31,14 @@ /* Basic Timers - TIM6 and TIM7 */ -#define STM32L4_BTIM_CR1_OFFSET 0x0000 /* Control register 1 (16-bit) */ -#define STM32L4_BTIM_CR2_OFFSET 0x0004 /* Control register 2 (16-bit) */ -#define STM32L4_BTIM_DIER_OFFSET 0x000c /* DMA/Interrupt enable register (16-bit) */ -#define STM32L4_BTIM_SR_OFFSET 0x0010 /* Status register (16-bit) */ -#define STM32L4_BTIM_EGR_OFFSET 0x0014 /* Event generation register (16-bit) */ -#define STM32L4_BTIM_CNT_OFFSET 0x0024 /* Counter (16-bit) */ -#define STM32L4_BTIM_PSC_OFFSET 0x0028 /* Prescaler (16-bit) */ -#define STM32L4_BTIM_ARR_OFFSET 0x002c /* Auto-reload register (16-bit) */ +#define STM32_BTIM_CR1_OFFSET 0x0000 /* Control register 1 (16-bit) */ +#define STM32_BTIM_CR2_OFFSET 0x0004 /* Control register 2 (16-bit) */ +#define STM32_BTIM_DIER_OFFSET 0x000c /* DMA/Interrupt enable register (16-bit) */ +#define STM32_BTIM_SR_OFFSET 0x0010 /* Status register (16-bit) */ +#define STM32_BTIM_EGR_OFFSET 0x0014 /* Event generation register (16-bit) */ +#define STM32_BTIM_CNT_OFFSET 0x0024 /* Counter (16-bit) */ +#define STM32_BTIM_PSC_OFFSET 0x0028 /* Prescaler (16-bit) */ +#define STM32_BTIM_ARR_OFFSET 0x002c /* Auto-reload register (16-bit) */ /* 16-/32-bit General Timers - TIM2, TIM3, TIM4, TIM5, and TIM15-17. * TIM3 and 4 are 16-bit. @@ -46,119 +46,119 @@ * TIM15, 16 and 17 are 16-bit. */ -#define STM32L4_GTIM_CR1_OFFSET 0x0000 /* Control register 1 (16-bit) */ -#define STM32L4_GTIM_CR2_OFFSET 0x0004 /* Control register 2 (16-bit) */ -#define STM32L4_GTIM_SMCR_OFFSET 0x0008 /* Slave mode control register (16-bit, TIM2-5,15 only) */ -#define STM32L4_GTIM_DIER_OFFSET 0x000c /* DMA/Interrupt enable register (16-bit) */ -#define STM32L4_GTIM_SR_OFFSET 0x0010 /* Status register (16-bit) */ -#define STM32L4_GTIM_EGR_OFFSET 0x0014 /* Event generation register (16-bit) */ -#define STM32L4_GTIM_CCMR1_OFFSET 0x0018 /* Capture/compare mode register 1 (32-bit) */ -#define STM32L4_GTIM_CCMR2_OFFSET 0x001c /* Capture/compare mode register 2 (32-bit, TIM2-5 only) */ -#define STM32L4_GTIM_CCER_OFFSET 0x0020 /* Capture/compare enable register (16-bit) */ -#define STM32L4_GTIM_CNT_OFFSET 0x0024 /* Counter (16-bit or 32-bit TIM2/5) */ -#define STM32L4_GTIM_PSC_OFFSET 0x0028 /* Prescaler (16-bit) */ -#define STM32L4_GTIM_ARR_OFFSET 0x002c /* Auto-reload register (16-bit or 32-bit TIM2/5) */ -#define STM32L4_GTIM_CCR1_OFFSET 0x0034 /* Capture/compare register 1 (16-bit or 32-bit TIM2/5) */ -#define STM32L4_GTIM_CCR2_OFFSET 0x0038 /* Capture/compare register 2 (16-bit TIM2-5,15 only or 32-bit TIM2/5) */ -#define STM32L4_GTIM_CCR3_OFFSET 0x003c /* Capture/compare register 3 (16-bit TIM2-5 only or 32-bit TIM2/5) */ -#define STM32L4_GTIM_CCR4_OFFSET 0x0040 /* Capture/compare register 4 (16-bit TIM2-5 only or 32-bit TIM2/5) */ -#define STM32L4_GTIM_DCR_OFFSET 0x0048 /* DMA control register (16-bit) */ -#define STM32L4_GTIM_DMAR_OFFSET 0x004c /* DMA address for burst mode (16-bit) */ -#define STM32L4_GTIM_OR1_OFFSET 0x0050 /* Option register 1 */ -#define STM32L4_GTIM_OR2_OFFSET 0x0060 /* Option register 2 */ +#define STM32_GTIM_CR1_OFFSET 0x0000 /* Control register 1 (16-bit) */ +#define STM32_GTIM_CR2_OFFSET 0x0004 /* Control register 2 (16-bit) */ +#define STM32_GTIM_SMCR_OFFSET 0x0008 /* Slave mode control register (16-bit, TIM2-5,15 only) */ +#define STM32_GTIM_DIER_OFFSET 0x000c /* DMA/Interrupt enable register (16-bit) */ +#define STM32_GTIM_SR_OFFSET 0x0010 /* Status register (16-bit) */ +#define STM32_GTIM_EGR_OFFSET 0x0014 /* Event generation register (16-bit) */ +#define STM32_GTIM_CCMR1_OFFSET 0x0018 /* Capture/compare mode register 1 (32-bit) */ +#define STM32_GTIM_CCMR2_OFFSET 0x001c /* Capture/compare mode register 2 (32-bit, TIM2-5 only) */ +#define STM32_GTIM_CCER_OFFSET 0x0020 /* Capture/compare enable register (16-bit) */ +#define STM32_GTIM_CNT_OFFSET 0x0024 /* Counter (16-bit or 32-bit TIM2/5) */ +#define STM32_GTIM_PSC_OFFSET 0x0028 /* Prescaler (16-bit) */ +#define STM32_GTIM_ARR_OFFSET 0x002c /* Auto-reload register (16-bit or 32-bit TIM2/5) */ +#define STM32_GTIM_CCR1_OFFSET 0x0034 /* Capture/compare register 1 (16-bit or 32-bit TIM2/5) */ +#define STM32_GTIM_CCR2_OFFSET 0x0038 /* Capture/compare register 2 (16-bit TIM2-5,15 only or 32-bit TIM2/5) */ +#define STM32_GTIM_CCR3_OFFSET 0x003c /* Capture/compare register 3 (16-bit TIM2-5 only or 32-bit TIM2/5) */ +#define STM32_GTIM_CCR4_OFFSET 0x0040 /* Capture/compare register 4 (16-bit TIM2-5 only or 32-bit TIM2/5) */ +#define STM32_GTIM_DCR_OFFSET 0x0048 /* DMA control register (16-bit) */ +#define STM32_GTIM_DMAR_OFFSET 0x004c /* DMA address for burst mode (16-bit) */ +#define STM32_GTIM_OR1_OFFSET 0x0050 /* Option register 1 */ +#define STM32_GTIM_OR2_OFFSET 0x0060 /* Option register 2 */ /* TIM15, 16, and 17 only. */ -#define STM32L4_GTIM_RCR_OFFSET 0x0030 /* Repetition counter register (TIM16/TIM17) */ -#define STM32L4_GTIM_BDTR_OFFSET 0x0044 /* Break and dead-time register (TIM16/TIM17) */ +#define STM32_GTIM_RCR_OFFSET 0x0030 /* Repetition counter register (TIM16/TIM17) */ +#define STM32_GTIM_BDTR_OFFSET 0x0044 /* Break and dead-time register (TIM16/TIM17) */ /* Advanced Timers - TIM1 and TIM8 */ -#define STM32L4_ATIM_CR1_OFFSET 0x0000 /* Control register 1 (16-bit) */ -#define STM32L4_ATIM_CR2_OFFSET 0x0004 /* Control register 2 (16-bit*) */ -#define STM32L4_ATIM_SMCR_OFFSET 0x0008 /* Slave mode control register (16-bit) */ -#define STM32L4_ATIM_DIER_OFFSET 0x000c /* DMA/Interrupt enable register (16-bit) */ -#define STM32L4_ATIM_SR_OFFSET 0x0010 /* Status register (16-bit*) */ -#define STM32L4_ATIM_EGR_OFFSET 0x0014 /* Event generation register (16-bit) */ -#define STM32L4_ATIM_CCMR1_OFFSET 0x0018 /* Capture/compare mode register 1 (16-bit*) */ -#define STM32L4_ATIM_CCMR2_OFFSET 0x001c /* Capture/compare mode register 2 (16-bit*) */ -#define STM32L4_ATIM_CCER_OFFSET 0x0020 /* Capture/compare enable register (16-bit*) */ -#define STM32L4_ATIM_CNT_OFFSET 0x0024 /* Counter (16-bit) */ -#define STM32L4_ATIM_PSC_OFFSET 0x0028 /* Prescaler (16-bit) */ -#define STM32L4_ATIM_ARR_OFFSET 0x002c /* Auto-reload register (16-bit) */ -#define STM32L4_ATIM_RCR_OFFSET 0x0030 /* Repetition counter register (16-bit) */ -#define STM32L4_ATIM_CCR1_OFFSET 0x0034 /* Capture/compare register 1 (16-bit) */ -#define STM32L4_ATIM_CCR2_OFFSET 0x0038 /* Capture/compare register 2 (16-bit) */ -#define STM32L4_ATIM_CCR3_OFFSET 0x003c /* Capture/compare register 3 (16-bit) */ -#define STM32L4_ATIM_CCR4_OFFSET 0x0040 /* Capture/compare register 4 (16-bit) */ -#define STM32L4_ATIM_BDTR_OFFSET 0x0044 /* Break and dead-time register (16-bit*) */ -#define STM32L4_ATIM_DCR_OFFSET 0x0048 /* DMA control register (16-bit) */ -#define STM32L4_ATIM_DMAR_OFFSET 0x004c /* DMA address for burst mode (16-bit) */ -#define STM32L4_ATIM_OR1_OFFSET 0x0050 /* Timer option register 1 */ -#define STM32L4_ATIM_CCMR3_OFFSET 0x0054 /* Capture/compare mode register 3 (32-bit) */ -#define STM32L4_ATIM_CCR5_OFFSET 0x0058 /* Capture/compare register 4 (16-bit) */ -#define STM32L4_ATIM_CCR6_OFFSET 0x005c /* Capture/compare register 4 (32-bit) */ -#define STM32L4_ATIM_OR2_OFFSET 0x0050 /* Timer option register 2 */ -#define STM32L4_ATIM_OR3_OFFSET 0x0050 /* Timer option register 3 */ +#define STM32_ATIM_CR1_OFFSET 0x0000 /* Control register 1 (16-bit) */ +#define STM32_ATIM_CR2_OFFSET 0x0004 /* Control register 2 (16-bit*) */ +#define STM32_ATIM_SMCR_OFFSET 0x0008 /* Slave mode control register (16-bit) */ +#define STM32_ATIM_DIER_OFFSET 0x000c /* DMA/Interrupt enable register (16-bit) */ +#define STM32_ATIM_SR_OFFSET 0x0010 /* Status register (16-bit*) */ +#define STM32_ATIM_EGR_OFFSET 0x0014 /* Event generation register (16-bit) */ +#define STM32_ATIM_CCMR1_OFFSET 0x0018 /* Capture/compare mode register 1 (16-bit*) */ +#define STM32_ATIM_CCMR2_OFFSET 0x001c /* Capture/compare mode register 2 (16-bit*) */ +#define STM32_ATIM_CCER_OFFSET 0x0020 /* Capture/compare enable register (16-bit*) */ +#define STM32_ATIM_CNT_OFFSET 0x0024 /* Counter (16-bit) */ +#define STM32_ATIM_PSC_OFFSET 0x0028 /* Prescaler (16-bit) */ +#define STM32_ATIM_ARR_OFFSET 0x002c /* Auto-reload register (16-bit) */ +#define STM32_ATIM_RCR_OFFSET 0x0030 /* Repetition counter register (16-bit) */ +#define STM32_ATIM_CCR1_OFFSET 0x0034 /* Capture/compare register 1 (16-bit) */ +#define STM32_ATIM_CCR2_OFFSET 0x0038 /* Capture/compare register 2 (16-bit) */ +#define STM32_ATIM_CCR3_OFFSET 0x003c /* Capture/compare register 3 (16-bit) */ +#define STM32_ATIM_CCR4_OFFSET 0x0040 /* Capture/compare register 4 (16-bit) */ +#define STM32_ATIM_BDTR_OFFSET 0x0044 /* Break and dead-time register (16-bit*) */ +#define STM32_ATIM_DCR_OFFSET 0x0048 /* DMA control register (16-bit) */ +#define STM32_ATIM_DMAR_OFFSET 0x004c /* DMA address for burst mode (16-bit) */ +#define STM32_ATIM_OR1_OFFSET 0x0050 /* Timer option register 1 */ +#define STM32_ATIM_CCMR3_OFFSET 0x0054 /* Capture/compare mode register 3 (32-bit) */ +#define STM32_ATIM_CCR5_OFFSET 0x0058 /* Capture/compare register 4 (16-bit) */ +#define STM32_ATIM_CCR6_OFFSET 0x005c /* Capture/compare register 4 (32-bit) */ +#define STM32_ATIM_OR2_OFFSET 0x0050 /* Timer option register 2 */ +#define STM32_ATIM_OR3_OFFSET 0x0050 /* Timer option register 3 */ /* Register Addresses *******************************************************/ /* Advanced Timers - TIM1 and TIM8 */ -#define STM32L4_TIM1_CR1 (STM32L4_TIM1_BASE+STM32L4_ATIM_CR1_OFFSET) -#define STM32L4_TIM1_CR2 (STM32L4_TIM1_BASE+STM32L4_ATIM_CR2_OFFSET) -#define STM32L4_TIM1_SMCR (STM32L4_TIM1_BASE+STM32L4_ATIM_SMCR_OFFSET) -#define STM32L4_TIM1_DIER (STM32L4_TIM1_BASE+STM32L4_ATIM_DIER_OFFSET) -#define STM32L4_TIM1_SR (STM32L4_TIM1_BASE+STM32L4_ATIM_SR_OFFSET) -#define STM32L4_TIM1_EGR (STM32L4_TIM1_BASE+STM32L4_ATIM_EGR_OFFSET) -#define STM32L4_TIM1_CCMR1 (STM32L4_TIM1_BASE+STM32L4_ATIM_CCMR1_OFFSET) -#define STM32L4_TIM1_CCMR2 (STM32L4_TIM1_BASE+STM32L4_ATIM_CCMR2_OFFSET) -#define STM32L4_TIM1_CCER (STM32L4_TIM1_BASE+STM32L4_ATIM_CCER_OFFSET) -#define STM32L4_TIM1_CNT (STM32L4_TIM1_BASE+STM32L4_ATIM_CNT_OFFSET) -#define STM32L4_TIM1_PSC (STM32L4_TIM1_BASE+STM32L4_ATIM_PSC_OFFSET) -#define STM32L4_TIM1_ARR (STM32L4_TIM1_BASE+STM32L4_ATIM_ARR_OFFSET) -#define STM32L4_TIM1_RCR (STM32L4_TIM1_BASE+STM32L4_ATIM_RCR_OFFSET) -#define STM32L4_TIM1_CCR1 (STM32L4_TIM1_BASE+STM32L4_ATIM_CCR1_OFFSET) -#define STM32L4_TIM1_CCR2 (STM32L4_TIM1_BASE+STM32L4_ATIM_CCR2_OFFSET) -#define STM32L4_TIM1_CCR3 (STM32L4_TIM1_BASE+STM32L4_ATIM_CCR3_OFFSET) -#define STM32L4_TIM1_CCR4 (STM32L4_TIM1_BASE+STM32L4_ATIM_CCR4_OFFSET) -#define STM32L4_TIM1_BDTR (STM32L4_TIM1_BASE+STM32L4_ATIM_BDTR_OFFSET) -#define STM32L4_TIM1_DCR (STM32L4_TIM1_BASE+STM32L4_ATIM_DCR_OFFSET) -#define STM32L4_TIM1_DMAR (STM32L4_TIM1_BASE+STM32L4_ATIM_DMAR_OFFSET) -#define STM32L4_TIM1_OR1 (STM32L4_TIM1_BASE+STM32L4_ATIM_OR1_OFFSET) -#define STM32L4_TIM1_CCMR3 (STM32L4_TIM1_BASE+STM32L4_ATIM_CCMR3_OFFSET) -#define STM32L4_TIM1_CCR5 (STM32L4_TIM1_BASE+STM32L4_ATIM_CCR5_OFFSET) -#define STM32L4_TIM1_CCR6 (STM32L4_TIM1_BASE+STM32L4_ATIM_CCR6_OFFSET) -#define STM32L4_TIM1_OR2 (STM32L4_TIM1_BASE+STM32L4_ATIM_OR2_OFFSET) -#define STM32L4_TIM1_OR3 (STM32L4_TIM1_BASE+STM32L4_ATIM_OR3_OFFSET) - -#define STM32L4_TIM8_CR1 (STM32L4_TIM8_BASE+STM32L4_ATIM_CR1_OFFSET) -#define STM32L4_TIM8_CR2 (STM32L4_TIM8_BASE+STM32L4_ATIM_CR2_OFFSET) -#define STM32L4_TIM8_SMCR (STM32L4_TIM8_BASE+STM32L4_ATIM_SMCR_OFFSET) -#define STM32L4_TIM8_DIER (STM32L4_TIM8_BASE+STM32L4_ATIM_DIER_OFFSET) -#define STM32L4_TIM8_SR (STM32L4_TIM8_BASE+STM32L4_ATIM_SR_OFFSET) -#define STM32L4_TIM8_EGR (STM32L4_TIM8_BASE+STM32L4_ATIM_EGR_OFFSET) -#define STM32L4_TIM8_CCMR1 (STM32L4_TIM8_BASE+STM32L4_ATIM_CCMR1_OFFSET) -#define STM32L4_TIM8_CCMR2 (STM32L4_TIM8_BASE+STM32L4_ATIM_CCMR2_OFFSET) -#define STM32L4_TIM8_CCER (STM32L4_TIM8_BASE+STM32L4_ATIM_CCER_OFFSET) -#define STM32L4_TIM8_CNT (STM32L4_TIM8_BASE+STM32L4_ATIM_CNT_OFFSET) -#define STM32L4_TIM8_PSC (STM32L4_TIM8_BASE+STM32L4_ATIM_PSC_OFFSET) -#define STM32L4_TIM8_ARR (STM32L4_TIM8_BASE+STM32L4_ATIM_ARR_OFFSET) -#define STM32L4_TIM8_RCR (STM32L4_TIM8_BASE+STM32L4_ATIM_RCR_OFFSET) -#define STM32L4_TIM8_CCR1 (STM32L4_TIM8_BASE+STM32L4_ATIM_CCR1_OFFSET) -#define STM32L4_TIM8_CCR2 (STM32L4_TIM8_BASE+STM32L4_ATIM_CCR2_OFFSET) -#define STM32L4_TIM8_CCR3 (STM32L4_TIM8_BASE+STM32L4_ATIM_CCR3_OFFSET) -#define STM32L4_TIM8_CCR4 (STM32L4_TIM8_BASE+STM32L4_ATIM_CCR4_OFFSET) -#define STM32L4_TIM8_BDTR (STM32L4_TIM8_BASE+STM32L4_ATIM_BDTR_OFFSET) -#define STM32L4_TIM8_DCR (STM32L4_TIM8_BASE+STM32L4_ATIM_DCR_OFFSET) -#define STM32L4_TIM8_DMAR (STM32L4_TIM8_BASE+STM32L4_ATIM_DMAR_OFFSET) -#define STM32L4_TIM8_OR1 (STM32L4_TIM8_BASE+STM32L4_ATIM_OR1_OFFSET) -#define STM32L4_TIM8_CCMR3 (STM32L4_TIM8_BASE+STM32L4_ATIM_CCMR3_OFFSET) -#define STM32L4_TIM8_CCR5 (STM32L4_TIM8_BASE+STM32L4_ATIM_CCR5_OFFSET) -#define STM32L4_TIM8_CCR6 (STM32L4_TIM8_BASE+STM32L4_ATIM_CCR6_OFFSET) -#define STM32L4_TIM8_OR2 (STM32L4_TIM8_BASE+STM32L4_ATIM_OR2_OFFSET) -#define STM32L4_TIM8_OR3 (STM32L4_TIM8_BASE+STM32L4_ATIM_OR3_OFFSET) +#define STM32_TIM1_CR1 (STM32_TIM1_BASE+STM32_ATIM_CR1_OFFSET) +#define STM32_TIM1_CR2 (STM32_TIM1_BASE+STM32_ATIM_CR2_OFFSET) +#define STM32_TIM1_SMCR (STM32_TIM1_BASE+STM32_ATIM_SMCR_OFFSET) +#define STM32_TIM1_DIER (STM32_TIM1_BASE+STM32_ATIM_DIER_OFFSET) +#define STM32_TIM1_SR (STM32_TIM1_BASE+STM32_ATIM_SR_OFFSET) +#define STM32_TIM1_EGR (STM32_TIM1_BASE+STM32_ATIM_EGR_OFFSET) +#define STM32_TIM1_CCMR1 (STM32_TIM1_BASE+STM32_ATIM_CCMR1_OFFSET) +#define STM32_TIM1_CCMR2 (STM32_TIM1_BASE+STM32_ATIM_CCMR2_OFFSET) +#define STM32_TIM1_CCER (STM32_TIM1_BASE+STM32_ATIM_CCER_OFFSET) +#define STM32_TIM1_CNT (STM32_TIM1_BASE+STM32_ATIM_CNT_OFFSET) +#define STM32_TIM1_PSC (STM32_TIM1_BASE+STM32_ATIM_PSC_OFFSET) +#define STM32_TIM1_ARR (STM32_TIM1_BASE+STM32_ATIM_ARR_OFFSET) +#define STM32_TIM1_RCR (STM32_TIM1_BASE+STM32_ATIM_RCR_OFFSET) +#define STM32_TIM1_CCR1 (STM32_TIM1_BASE+STM32_ATIM_CCR1_OFFSET) +#define STM32_TIM1_CCR2 (STM32_TIM1_BASE+STM32_ATIM_CCR2_OFFSET) +#define STM32_TIM1_CCR3 (STM32_TIM1_BASE+STM32_ATIM_CCR3_OFFSET) +#define STM32_TIM1_CCR4 (STM32_TIM1_BASE+STM32_ATIM_CCR4_OFFSET) +#define STM32_TIM1_BDTR (STM32_TIM1_BASE+STM32_ATIM_BDTR_OFFSET) +#define STM32_TIM1_DCR (STM32_TIM1_BASE+STM32_ATIM_DCR_OFFSET) +#define STM32_TIM1_DMAR (STM32_TIM1_BASE+STM32_ATIM_DMAR_OFFSET) +#define STM32_TIM1_OR1 (STM32_TIM1_BASE+STM32_ATIM_OR1_OFFSET) +#define STM32_TIM1_CCMR3 (STM32_TIM1_BASE+STM32_ATIM_CCMR3_OFFSET) +#define STM32_TIM1_CCR5 (STM32_TIM1_BASE+STM32_ATIM_CCR5_OFFSET) +#define STM32_TIM1_CCR6 (STM32_TIM1_BASE+STM32_ATIM_CCR6_OFFSET) +#define STM32_TIM1_OR2 (STM32_TIM1_BASE+STM32_ATIM_OR2_OFFSET) +#define STM32_TIM1_OR3 (STM32_TIM1_BASE+STM32_ATIM_OR3_OFFSET) + +#define STM32_TIM8_CR1 (STM32_TIM8_BASE+STM32_ATIM_CR1_OFFSET) +#define STM32_TIM8_CR2 (STM32_TIM8_BASE+STM32_ATIM_CR2_OFFSET) +#define STM32_TIM8_SMCR (STM32_TIM8_BASE+STM32_ATIM_SMCR_OFFSET) +#define STM32_TIM8_DIER (STM32_TIM8_BASE+STM32_ATIM_DIER_OFFSET) +#define STM32_TIM8_SR (STM32_TIM8_BASE+STM32_ATIM_SR_OFFSET) +#define STM32_TIM8_EGR (STM32_TIM8_BASE+STM32_ATIM_EGR_OFFSET) +#define STM32_TIM8_CCMR1 (STM32_TIM8_BASE+STM32_ATIM_CCMR1_OFFSET) +#define STM32_TIM8_CCMR2 (STM32_TIM8_BASE+STM32_ATIM_CCMR2_OFFSET) +#define STM32_TIM8_CCER (STM32_TIM8_BASE+STM32_ATIM_CCER_OFFSET) +#define STM32_TIM8_CNT (STM32_TIM8_BASE+STM32_ATIM_CNT_OFFSET) +#define STM32_TIM8_PSC (STM32_TIM8_BASE+STM32_ATIM_PSC_OFFSET) +#define STM32_TIM8_ARR (STM32_TIM8_BASE+STM32_ATIM_ARR_OFFSET) +#define STM32_TIM8_RCR (STM32_TIM8_BASE+STM32_ATIM_RCR_OFFSET) +#define STM32_TIM8_CCR1 (STM32_TIM8_BASE+STM32_ATIM_CCR1_OFFSET) +#define STM32_TIM8_CCR2 (STM32_TIM8_BASE+STM32_ATIM_CCR2_OFFSET) +#define STM32_TIM8_CCR3 (STM32_TIM8_BASE+STM32_ATIM_CCR3_OFFSET) +#define STM32_TIM8_CCR4 (STM32_TIM8_BASE+STM32_ATIM_CCR4_OFFSET) +#define STM32_TIM8_BDTR (STM32_TIM8_BASE+STM32_ATIM_BDTR_OFFSET) +#define STM32_TIM8_DCR (STM32_TIM8_BASE+STM32_ATIM_DCR_OFFSET) +#define STM32_TIM8_DMAR (STM32_TIM8_BASE+STM32_ATIM_DMAR_OFFSET) +#define STM32_TIM8_OR1 (STM32_TIM8_BASE+STM32_ATIM_OR1_OFFSET) +#define STM32_TIM8_CCMR3 (STM32_TIM8_BASE+STM32_ATIM_CCMR3_OFFSET) +#define STM32_TIM8_CCR5 (STM32_TIM8_BASE+STM32_ATIM_CCR5_OFFSET) +#define STM32_TIM8_CCR6 (STM32_TIM8_BASE+STM32_ATIM_CCR6_OFFSET) +#define STM32_TIM8_OR2 (STM32_TIM8_BASE+STM32_ATIM_OR2_OFFSET) +#define STM32_TIM8_OR3 (STM32_TIM8_BASE+STM32_ATIM_OR3_OFFSET) /* 16-/32-bit General Timers - TIM2, TIM3, TIM4, TIM5, and TIM15-17. * TIM3 and 4 are 16-bit. @@ -166,154 +166,154 @@ * TIM15, 16 and 17 are 16-bit. */ -#define STM32L4_TIM2_CR1 (STM32L4_TIM2_BASE+STM32L4_GTIM_CR1_OFFSET) -#define STM32L4_TIM2_CR2 (STM32L4_TIM2_BASE+STM32L4_GTIM_CR2_OFFSET) -#define STM32L4_TIM2_SMCR (STM32L4_TIM2_BASE+STM32L4_GTIM_SMCR_OFFSET) -#define STM32L4_TIM2_DIER (STM32L4_TIM2_BASE+STM32L4_GTIM_DIER_OFFSET) -#define STM32L4_TIM2_SR (STM32L4_TIM2_BASE+STM32L4_GTIM_SR_OFFSET) -#define STM32L4_TIM2_EGR (STM32L4_TIM2_BASE+STM32L4_GTIM_EGR_OFFSET) -#define STM32L4_TIM2_CCMR1 (STM32L4_TIM2_BASE+STM32L4_GTIM_CCMR1_OFFSET) -#define STM32L4_TIM2_CCMR2 (STM32L4_TIM2_BASE+STM32L4_GTIM_CCMR2_OFFSET) -#define STM32L4_TIM2_CCER (STM32L4_TIM2_BASE+STM32L4_GTIM_CCER_OFFSET) -#define STM32L4_TIM2_CNT (STM32L4_TIM2_BASE+STM32L4_GTIM_CNT_OFFSET) -#define STM32L4_TIM2_PSC (STM32L4_TIM2_BASE+STM32L4_GTIM_PSC_OFFSET) -#define STM32L4_TIM2_ARR (STM32L4_TIM2_BASE+STM32L4_GTIM_ARR_OFFSET) -#define STM32L4_TIM2_CCR1 (STM32L4_TIM2_BASE+STM32L4_GTIM_CCR1_OFFSET) -#define STM32L4_TIM2_CCR2 (STM32L4_TIM2_BASE+STM32L4_GTIM_CCR2_OFFSET) -#define STM32L4_TIM2_CCR3 (STM32L4_TIM2_BASE+STM32L4_GTIM_CCR3_OFFSET) -#define STM32L4_TIM2_CCR4 (STM32L4_TIM2_BASE+STM32L4_GTIM_CCR4_OFFSET) -#define STM32L4_TIM2_DCR (STM32L4_TIM2_BASE+STM32L4_GTIM_DCR_OFFSET) -#define STM32L4_TIM2_DMAR (STM32L4_TIM2_BASE+STM32L4_GTIM_DMAR_OFFSET) -#define STM32L4_TIM2_OR (STM32L4_TIM2_BASE+STM32L4_GTIM_OR_OFFSET) - -#define STM32L4_TIM3_CR1 (STM32L4_TIM3_BASE+STM32L4_GTIM_CR1_OFFSET) -#define STM32L4_TIM3_CR2 (STM32L4_TIM3_BASE+STM32L4_GTIM_CR2_OFFSET) -#define STM32L4_TIM3_SMCR (STM32L4_TIM3_BASE+STM32L4_GTIM_SMCR_OFFSET) -#define STM32L4_TIM3_DIER (STM32L4_TIM3_BASE+STM32L4_GTIM_DIER_OFFSET) -#define STM32L4_TIM3_SR (STM32L4_TIM3_BASE+STM32L4_GTIM_SR_OFFSET) -#define STM32L4_TIM3_EGR (STM32L4_TIM3_BASE+STM32L4_GTIM_EGR_OFFSET) -#define STM32L4_TIM3_CCMR1 (STM32L4_TIM3_BASE+STM32L4_GTIM_CCMR1_OFFSET) -#define STM32L4_TIM3_CCMR2 (STM32L4_TIM3_BASE+STM32L4_GTIM_CCMR2_OFFSET) -#define STM32L4_TIM3_CCER (STM32L4_TIM3_BASE+STM32L4_GTIM_CCER_OFFSET) -#define STM32L4_TIM3_CNT (STM32L4_TIM3_BASE+STM32L4_GTIM_CNT_OFFSET) -#define STM32L4_TIM3_PSC (STM32L4_TIM3_BASE+STM32L4_GTIM_PSC_OFFSET) -#define STM32L4_TIM3_ARR (STM32L4_TIM3_BASE+STM32L4_GTIM_ARR_OFFSET) -#define STM32L4_TIM3_CCR1 (STM32L4_TIM3_BASE+STM32L4_GTIM_CCR1_OFFSET) -#define STM32L4_TIM3_CCR2 (STM32L4_TIM3_BASE+STM32L4_GTIM_CCR2_OFFSET) -#define STM32L4_TIM3_CCR3 (STM32L4_TIM3_BASE+STM32L4_GTIM_CCR3_OFFSET) -#define STM32L4_TIM3_CCR4 (STM32L4_TIM3_BASE+STM32L4_GTIM_CCR4_OFFSET) -#define STM32L4_TIM3_DCR (STM32L4_TIM3_BASE+STM32L4_GTIM_DCR_OFFSET) -#define STM32L4_TIM3_DMAR (STM32L4_TIM3_BASE+STM32L4_GTIM_DMAR_OFFSET) - -#define STM32L4_TIM4_CR1 (STM32L4_TIM4_BASE+STM32L4_GTIM_CR1_OFFSET) -#define STM32L4_TIM4_CR2 (STM32L4_TIM4_BASE+STM32L4_GTIM_CR2_OFFSET) -#define STM32L4_TIM4_SMCR (STM32L4_TIM4_BASE+STM32L4_GTIM_SMCR_OFFSET) -#define STM32L4_TIM4_DIER (STM32L4_TIM4_BASE+STM32L4_GTIM_DIER_OFFSET) -#define STM32L4_TIM4_SR (STM32L4_TIM4_BASE+STM32L4_GTIM_SR_OFFSET) -#define STM32L4_TIM4_EGR (STM32L4_TIM4_BASE+STM32L4_GTIM_EGR_OFFSET) -#define STM32L4_TIM4_CCMR1 (STM32L4_TIM4_BASE+STM32L4_GTIM_CCMR1_OFFSET) -#define STM32L4_TIM4_CCMR2 (STM32L4_TIM4_BASE+STM32L4_GTIM_CCMR2_OFFSET) -#define STM32L4_TIM4_CCER (STM32L4_TIM4_BASE+STM32L4_GTIM_CCER_OFFSET) -#define STM32L4_TIM4_CNT (STM32L4_TIM4_BASE+STM32L4_GTIM_CNT_OFFSET) -#define STM32L4_TIM4_PSC (STM32L4_TIM4_BASE+STM32L4_GTIM_PSC_OFFSET) -#define STM32L4_TIM4_ARR (STM32L4_TIM4_BASE+STM32L4_GTIM_ARR_OFFSET) -#define STM32L4_TIM4_CCR1 (STM32L4_TIM4_BASE+STM32L4_GTIM_CCR1_OFFSET) -#define STM32L4_TIM4_CCR2 (STM32L4_TIM4_BASE+STM32L4_GTIM_CCR2_OFFSET) -#define STM32L4_TIM4_CCR3 (STM32L4_TIM4_BASE+STM32L4_GTIM_CCR3_OFFSET) -#define STM32L4_TIM4_CCR4 (STM32L4_TIM4_BASE+STM32L4_GTIM_CCR4_OFFSET) -#define STM32L4_TIM4_DCR (STM32L4_TIM4_BASE+STM32L4_GTIM_DCR_OFFSET) -#define STM32L4_TIM4_DMAR (STM32L4_TIM4_BASE+STM32L4_GTIM_DMAR_OFFSET) - -#define STM32L4_TIM5_CR1 (STM32L4_TIM5_BASE+STM32L4_GTIM_CR1_OFFSET) -#define STM32L4_TIM5_CR2 (STM32L4_TIM5_BASE+STM32L4_GTIM_CR2_OFFSET) -#define STM32L4_TIM5_SMCR (STM32L4_TIM5_BASE+STM32L4_GTIM_SMCR_OFFSET) -#define STM32L4_TIM5_DIER (STM32L4_TIM5_BASE+STM32L4_GTIM_DIER_OFFSET) -#define STM32L4_TIM5_SR (STM32L4_TIM5_BASE+STM32L4_GTIM_SR_OFFSET) -#define STM32L4_TIM5_EGR (STM32L4_TIM5_BASE+STM32L4_GTIM_EGR_OFFSET) -#define STM32L4_TIM5_CCMR1 (STM32L4_TIM5_BASE+STM32L4_GTIM_CCMR1_OFFSET) -#define STM32L4_TIM5_CCMR2 (STM32L4_TIM5_BASE+STM32L4_GTIM_CCMR2_OFFSET) -#define STM32L4_TIM5_CCER (STM32L4_TIM5_BASE+STM32L4_GTIM_CCER_OFFSET) -#define STM32L4_TIM5_CNT (STM32L4_TIM5_BASE+STM32L4_GTIM_CNT_OFFSET) -#define STM32L4_TIM5_PSC (STM32L4_TIM5_BASE+STM32L4_GTIM_PSC_OFFSET) -#define STM32L4_TIM5_ARR (STM32L4_TIM5_BASE+STM32L4_GTIM_ARR_OFFSET) -#define STM32L4_TIM5_CCR1 (STM32L4_TIM5_BASE+STM32L4_GTIM_CCR1_OFFSET) -#define STM32L4_TIM5_CCR2 (STM32L4_TIM5_BASE+STM32L4_GTIM_CCR2_OFFSET) -#define STM32L4_TIM5_CCR3 (STM32L4_TIM5_BASE+STM32L4_GTIM_CCR3_OFFSET) -#define STM32L4_TIM5_CCR4 (STM32L4_TIM5_BASE+STM32L4_GTIM_CCR4_OFFSET) -#define STM32L4_TIM5_DCR (STM32L4_TIM5_BASE+STM32L4_GTIM_DCR_OFFSET) -#define STM32L4_TIM5_DMAR (STM32L4_TIM5_BASE+STM32L4_GTIM_DMAR_OFFSET) -#define STM32L4_TIM5_OR (STM32L4_TIM5_BASE+STM32L4_GTIM_OR_OFFSET) - -#define STM32L4_TIM15_CR1 (STM32L4_TIM15_BASE+STM32L4_GTIM_CR1_OFFSET) -#define STM32L4_TIM15_CR2 (STM32L4_TIM15_BASE+STM32L4_GTIM_CR2_OFFSET) -#define STM32L4_TIM15_SMCR (STM32L4_TIM15_BASE+STM32L4_GTIM_SMCR_OFFSET) -#define STM32L4_TIM15_DIER (STM32L4_TIM15_BASE+STM32L4_GTIM_DIER_OFFSET) -#define STM32L4_TIM15_SR (STM32L4_TIM15_BASE+STM32L4_GTIM_SR_OFFSET) -#define STM32L4_TIM15_EGR (STM32L4_TIM15_BASE+STM32L4_GTIM_EGR_OFFSET) -#define STM32L4_TIM15_CCMR1 (STM32L4_TIM15_BASE+STM32L4_GTIM_CCMR1_OFFSET) -#define STM32L4_TIM15_CCER (STM32L4_TIM15_BASE+STM32L4_GTIM_CCER_OFFSET) -#define STM32L4_TIM15_CNT (STM32L4_TIM15_BASE+STM32L4_GTIM_CNT_OFFSET) -#define STM32L4_TIM15_PSC (STM32L4_TIM15_BASE+STM32L4_GTIM_PSC_OFFSET) -#define STM32L4_TIM15_ARR (STM32L4_TIM15_BASE+STM32L4_GTIM_ARR_OFFSET) -#define STM32L4_TIM15_RCR (STM32L4_TIM15_BASE+STM32L4_GTIM_RCR_OFFSET) -#define STM32L4_TIM15_CCR1 (STM32L4_TIM15_BASE+STM32L4_GTIM_CCR1_OFFSET) -#define STM32L4_TIM15_CCR2 (STM32L4_TIM15_BASE+STM32L4_GTIM_CCR2_OFFSET) -#define STM32L4_TIM15_BDTR (STM32L4_TIM15_BASE+STM32L4_GTIM_BDTR_OFFSET) -#define STM32L4_TIM15_DCR (STM32L4_TIM15_BASE+STM32L4_GTIM_DCR_OFFSET) -#define STM32L4_TIM15_DMAR (STM32L4_TIM15_BASE+STM32L4_GTIM_DMAR_OFFSET) - -#define STM32L4_TIM16_CR1 (STM32L4_TIM16_BASE+STM32L4_GTIM_CR1_OFFSET) -#define STM32L4_TIM16_CR2 (STM32L4_TIM16_BASE+STM32L4_GTIM_CR2_OFFSET) -#define STM32L4_TIM16_DIER (STM32L4_TIM16_BASE+STM32L4_GTIM_DIER_OFFSET) -#define STM32L4_TIM16_SR (STM32L4_TIM16_BASE+STM32L4_GTIM_SR_OFFSET) -#define STM32L4_TIM16_EGR (STM32L4_TIM16_BASE+STM32L4_GTIM_EGR_OFFSET) -#define STM32L4_TIM16_CCMR1 (STM32L4_TIM16_BASE+STM32L4_GTIM_CCMR1_OFFSET) -#define STM32L4_TIM16_CCER (STM32L4_TIM16_BASE+STM32L4_GTIM_CCER_OFFSET) -#define STM32L4_TIM16_CNT (STM32L4_TIM16_BASE+STM32L4_GTIM_CNT_OFFSET) -#define STM32L4_TIM16_PSC (STM32L4_TIM16_BASE+STM32L4_GTIM_PSC_OFFSET) -#define STM32L4_TIM16_ARR (STM32L4_TIM16_BASE+STM32L4_GTIM_ARR_OFFSET) -#define STM32L4_TIM16_RCR (STM32L4_TIM16_BASE+STM32L4_GTIM_RCR_OFFSET) -#define STM32L4_TIM16_CCR1 (STM32L4_TIM16_BASE+STM32L4_GTIM_CCR1_OFFSET) -#define STM32L4_TIM16_BDTR (STM32L4_TIM16_BASE+STM32L4_GTIM_BDTR_OFFSET) -#define STM32L4_TIM16_DCR (STM32L4_TIM16_BASE+STM32L4_GTIM_DCR_OFFSET) -#define STM32L4_TIM16_DMAR (STM32L4_TIM16_BASE+STM32L4_GTIM_DMAR_OFFSET) -#define STM32L4_TIM16_OR (STM32L4_TIM16_BASE+STM32L4_GTIM_OR_OFFSET) - -#define STM32L4_TIM17_CR1 (STM32L4_TIM17_BASE+STM32L4_GTIM_CR1_OFFSET) -#define STM32L4_TIM17_CR2 (STM32L4_TIM17_BASE+STM32L4_GTIM_CR2_OFFSET) -#define STM32L4_TIM17_DIER (STM32L4_TIM17_BASE+STM32L4_GTIM_DIER_OFFSET) -#define STM32L4_TIM17_SR (STM32L4_TIM17_BASE+STM32L4_GTIM_SR_OFFSET) -#define STM32L4_TIM17_EGR (STM32L4_TIM17_BASE+STM32L4_GTIM_EGR_OFFSET) -#define STM32L4_TIM17_CCMR1 (STM32L4_TIM17_BASE+STM32L4_GTIM_CCMR1_OFFSET) -#define STM32L4_TIM17_CCER (STM32L4_TIM17_BASE+STM32L4_GTIM_CCER_OFFSET) -#define STM32L4_TIM17_CNT (STM32L4_TIM17_BASE+STM32L4_GTIM_CNT_OFFSET) -#define STM32L4_TIM17_PSC (STM32L4_TIM17_BASE+STM32L4_GTIM_PSC_OFFSET) -#define STM32L4_TIM17_ARR (STM32L4_TIM17_BASE+STM32L4_GTIM_ARR_OFFSET) -#define STM32L4_TIM17_RCR (STM32L4_TIM17_BASE+STM32L4_GTIM_RCR_OFFSET) -#define STM32L4_TIM17_CCR1 (STM32L4_TIM17_BASE+STM32L4_GTIM_CCR1_OFFSET) -#define STM32L4_TIM17_BDTR (STM32L4_TIM17_BASE+STM32L4_GTIM_BDTR_OFFSET) -#define STM32L4_TIM17_DCR (STM32L4_TIM17_BASE+STM32L4_GTIM_DCR_OFFSET) -#define STM32L4_TIM17_DMAR (STM32L4_TIM17_BASE+STM32L4_GTIM_DMAR_OFFSET) +#define STM32_TIM2_CR1 (STM32_TIM2_BASE+STM32_GTIM_CR1_OFFSET) +#define STM32_TIM2_CR2 (STM32_TIM2_BASE+STM32_GTIM_CR2_OFFSET) +#define STM32_TIM2_SMCR (STM32_TIM2_BASE+STM32_GTIM_SMCR_OFFSET) +#define STM32_TIM2_DIER (STM32_TIM2_BASE+STM32_GTIM_DIER_OFFSET) +#define STM32_TIM2_SR (STM32_TIM2_BASE+STM32_GTIM_SR_OFFSET) +#define STM32_TIM2_EGR (STM32_TIM2_BASE+STM32_GTIM_EGR_OFFSET) +#define STM32_TIM2_CCMR1 (STM32_TIM2_BASE+STM32_GTIM_CCMR1_OFFSET) +#define STM32_TIM2_CCMR2 (STM32_TIM2_BASE+STM32_GTIM_CCMR2_OFFSET) +#define STM32_TIM2_CCER (STM32_TIM2_BASE+STM32_GTIM_CCER_OFFSET) +#define STM32_TIM2_CNT (STM32_TIM2_BASE+STM32_GTIM_CNT_OFFSET) +#define STM32_TIM2_PSC (STM32_TIM2_BASE+STM32_GTIM_PSC_OFFSET) +#define STM32_TIM2_ARR (STM32_TIM2_BASE+STM32_GTIM_ARR_OFFSET) +#define STM32_TIM2_CCR1 (STM32_TIM2_BASE+STM32_GTIM_CCR1_OFFSET) +#define STM32_TIM2_CCR2 (STM32_TIM2_BASE+STM32_GTIM_CCR2_OFFSET) +#define STM32_TIM2_CCR3 (STM32_TIM2_BASE+STM32_GTIM_CCR3_OFFSET) +#define STM32_TIM2_CCR4 (STM32_TIM2_BASE+STM32_GTIM_CCR4_OFFSET) +#define STM32_TIM2_DCR (STM32_TIM2_BASE+STM32_GTIM_DCR_OFFSET) +#define STM32_TIM2_DMAR (STM32_TIM2_BASE+STM32_GTIM_DMAR_OFFSET) +#define STM32_TIM2_OR (STM32_TIM2_BASE+STM32_GTIM_OR_OFFSET) + +#define STM32_TIM3_CR1 (STM32_TIM3_BASE+STM32_GTIM_CR1_OFFSET) +#define STM32_TIM3_CR2 (STM32_TIM3_BASE+STM32_GTIM_CR2_OFFSET) +#define STM32_TIM3_SMCR (STM32_TIM3_BASE+STM32_GTIM_SMCR_OFFSET) +#define STM32_TIM3_DIER (STM32_TIM3_BASE+STM32_GTIM_DIER_OFFSET) +#define STM32_TIM3_SR (STM32_TIM3_BASE+STM32_GTIM_SR_OFFSET) +#define STM32_TIM3_EGR (STM32_TIM3_BASE+STM32_GTIM_EGR_OFFSET) +#define STM32_TIM3_CCMR1 (STM32_TIM3_BASE+STM32_GTIM_CCMR1_OFFSET) +#define STM32_TIM3_CCMR2 (STM32_TIM3_BASE+STM32_GTIM_CCMR2_OFFSET) +#define STM32_TIM3_CCER (STM32_TIM3_BASE+STM32_GTIM_CCER_OFFSET) +#define STM32_TIM3_CNT (STM32_TIM3_BASE+STM32_GTIM_CNT_OFFSET) +#define STM32_TIM3_PSC (STM32_TIM3_BASE+STM32_GTIM_PSC_OFFSET) +#define STM32_TIM3_ARR (STM32_TIM3_BASE+STM32_GTIM_ARR_OFFSET) +#define STM32_TIM3_CCR1 (STM32_TIM3_BASE+STM32_GTIM_CCR1_OFFSET) +#define STM32_TIM3_CCR2 (STM32_TIM3_BASE+STM32_GTIM_CCR2_OFFSET) +#define STM32_TIM3_CCR3 (STM32_TIM3_BASE+STM32_GTIM_CCR3_OFFSET) +#define STM32_TIM3_CCR4 (STM32_TIM3_BASE+STM32_GTIM_CCR4_OFFSET) +#define STM32_TIM3_DCR (STM32_TIM3_BASE+STM32_GTIM_DCR_OFFSET) +#define STM32_TIM3_DMAR (STM32_TIM3_BASE+STM32_GTIM_DMAR_OFFSET) + +#define STM32_TIM4_CR1 (STM32_TIM4_BASE+STM32_GTIM_CR1_OFFSET) +#define STM32_TIM4_CR2 (STM32_TIM4_BASE+STM32_GTIM_CR2_OFFSET) +#define STM32_TIM4_SMCR (STM32_TIM4_BASE+STM32_GTIM_SMCR_OFFSET) +#define STM32_TIM4_DIER (STM32_TIM4_BASE+STM32_GTIM_DIER_OFFSET) +#define STM32_TIM4_SR (STM32_TIM4_BASE+STM32_GTIM_SR_OFFSET) +#define STM32_TIM4_EGR (STM32_TIM4_BASE+STM32_GTIM_EGR_OFFSET) +#define STM32_TIM4_CCMR1 (STM32_TIM4_BASE+STM32_GTIM_CCMR1_OFFSET) +#define STM32_TIM4_CCMR2 (STM32_TIM4_BASE+STM32_GTIM_CCMR2_OFFSET) +#define STM32_TIM4_CCER (STM32_TIM4_BASE+STM32_GTIM_CCER_OFFSET) +#define STM32_TIM4_CNT (STM32_TIM4_BASE+STM32_GTIM_CNT_OFFSET) +#define STM32_TIM4_PSC (STM32_TIM4_BASE+STM32_GTIM_PSC_OFFSET) +#define STM32_TIM4_ARR (STM32_TIM4_BASE+STM32_GTIM_ARR_OFFSET) +#define STM32_TIM4_CCR1 (STM32_TIM4_BASE+STM32_GTIM_CCR1_OFFSET) +#define STM32_TIM4_CCR2 (STM32_TIM4_BASE+STM32_GTIM_CCR2_OFFSET) +#define STM32_TIM4_CCR3 (STM32_TIM4_BASE+STM32_GTIM_CCR3_OFFSET) +#define STM32_TIM4_CCR4 (STM32_TIM4_BASE+STM32_GTIM_CCR4_OFFSET) +#define STM32_TIM4_DCR (STM32_TIM4_BASE+STM32_GTIM_DCR_OFFSET) +#define STM32_TIM4_DMAR (STM32_TIM4_BASE+STM32_GTIM_DMAR_OFFSET) + +#define STM32_TIM5_CR1 (STM32_TIM5_BASE+STM32_GTIM_CR1_OFFSET) +#define STM32_TIM5_CR2 (STM32_TIM5_BASE+STM32_GTIM_CR2_OFFSET) +#define STM32_TIM5_SMCR (STM32_TIM5_BASE+STM32_GTIM_SMCR_OFFSET) +#define STM32_TIM5_DIER (STM32_TIM5_BASE+STM32_GTIM_DIER_OFFSET) +#define STM32_TIM5_SR (STM32_TIM5_BASE+STM32_GTIM_SR_OFFSET) +#define STM32_TIM5_EGR (STM32_TIM5_BASE+STM32_GTIM_EGR_OFFSET) +#define STM32_TIM5_CCMR1 (STM32_TIM5_BASE+STM32_GTIM_CCMR1_OFFSET) +#define STM32_TIM5_CCMR2 (STM32_TIM5_BASE+STM32_GTIM_CCMR2_OFFSET) +#define STM32_TIM5_CCER (STM32_TIM5_BASE+STM32_GTIM_CCER_OFFSET) +#define STM32_TIM5_CNT (STM32_TIM5_BASE+STM32_GTIM_CNT_OFFSET) +#define STM32_TIM5_PSC (STM32_TIM5_BASE+STM32_GTIM_PSC_OFFSET) +#define STM32_TIM5_ARR (STM32_TIM5_BASE+STM32_GTIM_ARR_OFFSET) +#define STM32_TIM5_CCR1 (STM32_TIM5_BASE+STM32_GTIM_CCR1_OFFSET) +#define STM32_TIM5_CCR2 (STM32_TIM5_BASE+STM32_GTIM_CCR2_OFFSET) +#define STM32_TIM5_CCR3 (STM32_TIM5_BASE+STM32_GTIM_CCR3_OFFSET) +#define STM32_TIM5_CCR4 (STM32_TIM5_BASE+STM32_GTIM_CCR4_OFFSET) +#define STM32_TIM5_DCR (STM32_TIM5_BASE+STM32_GTIM_DCR_OFFSET) +#define STM32_TIM5_DMAR (STM32_TIM5_BASE+STM32_GTIM_DMAR_OFFSET) +#define STM32_TIM5_OR (STM32_TIM5_BASE+STM32_GTIM_OR_OFFSET) + +#define STM32_TIM15_CR1 (STM32_TIM15_BASE+STM32_GTIM_CR1_OFFSET) +#define STM32_TIM15_CR2 (STM32_TIM15_BASE+STM32_GTIM_CR2_OFFSET) +#define STM32_TIM15_SMCR (STM32_TIM15_BASE+STM32_GTIM_SMCR_OFFSET) +#define STM32_TIM15_DIER (STM32_TIM15_BASE+STM32_GTIM_DIER_OFFSET) +#define STM32_TIM15_SR (STM32_TIM15_BASE+STM32_GTIM_SR_OFFSET) +#define STM32_TIM15_EGR (STM32_TIM15_BASE+STM32_GTIM_EGR_OFFSET) +#define STM32_TIM15_CCMR1 (STM32_TIM15_BASE+STM32_GTIM_CCMR1_OFFSET) +#define STM32_TIM15_CCER (STM32_TIM15_BASE+STM32_GTIM_CCER_OFFSET) +#define STM32_TIM15_CNT (STM32_TIM15_BASE+STM32_GTIM_CNT_OFFSET) +#define STM32_TIM15_PSC (STM32_TIM15_BASE+STM32_GTIM_PSC_OFFSET) +#define STM32_TIM15_ARR (STM32_TIM15_BASE+STM32_GTIM_ARR_OFFSET) +#define STM32_TIM15_RCR (STM32_TIM15_BASE+STM32_GTIM_RCR_OFFSET) +#define STM32_TIM15_CCR1 (STM32_TIM15_BASE+STM32_GTIM_CCR1_OFFSET) +#define STM32_TIM15_CCR2 (STM32_TIM15_BASE+STM32_GTIM_CCR2_OFFSET) +#define STM32_TIM15_BDTR (STM32_TIM15_BASE+STM32_GTIM_BDTR_OFFSET) +#define STM32_TIM15_DCR (STM32_TIM15_BASE+STM32_GTIM_DCR_OFFSET) +#define STM32_TIM15_DMAR (STM32_TIM15_BASE+STM32_GTIM_DMAR_OFFSET) + +#define STM32_TIM16_CR1 (STM32_TIM16_BASE+STM32_GTIM_CR1_OFFSET) +#define STM32_TIM16_CR2 (STM32_TIM16_BASE+STM32_GTIM_CR2_OFFSET) +#define STM32_TIM16_DIER (STM32_TIM16_BASE+STM32_GTIM_DIER_OFFSET) +#define STM32_TIM16_SR (STM32_TIM16_BASE+STM32_GTIM_SR_OFFSET) +#define STM32_TIM16_EGR (STM32_TIM16_BASE+STM32_GTIM_EGR_OFFSET) +#define STM32_TIM16_CCMR1 (STM32_TIM16_BASE+STM32_GTIM_CCMR1_OFFSET) +#define STM32_TIM16_CCER (STM32_TIM16_BASE+STM32_GTIM_CCER_OFFSET) +#define STM32_TIM16_CNT (STM32_TIM16_BASE+STM32_GTIM_CNT_OFFSET) +#define STM32_TIM16_PSC (STM32_TIM16_BASE+STM32_GTIM_PSC_OFFSET) +#define STM32_TIM16_ARR (STM32_TIM16_BASE+STM32_GTIM_ARR_OFFSET) +#define STM32_TIM16_RCR (STM32_TIM16_BASE+STM32_GTIM_RCR_OFFSET) +#define STM32_TIM16_CCR1 (STM32_TIM16_BASE+STM32_GTIM_CCR1_OFFSET) +#define STM32_TIM16_BDTR (STM32_TIM16_BASE+STM32_GTIM_BDTR_OFFSET) +#define STM32_TIM16_DCR (STM32_TIM16_BASE+STM32_GTIM_DCR_OFFSET) +#define STM32_TIM16_DMAR (STM32_TIM16_BASE+STM32_GTIM_DMAR_OFFSET) +#define STM32_TIM16_OR (STM32_TIM16_BASE+STM32_GTIM_OR_OFFSET) + +#define STM32_TIM17_CR1 (STM32_TIM17_BASE+STM32_GTIM_CR1_OFFSET) +#define STM32_TIM17_CR2 (STM32_TIM17_BASE+STM32_GTIM_CR2_OFFSET) +#define STM32_TIM17_DIER (STM32_TIM17_BASE+STM32_GTIM_DIER_OFFSET) +#define STM32_TIM17_SR (STM32_TIM17_BASE+STM32_GTIM_SR_OFFSET) +#define STM32_TIM17_EGR (STM32_TIM17_BASE+STM32_GTIM_EGR_OFFSET) +#define STM32_TIM17_CCMR1 (STM32_TIM17_BASE+STM32_GTIM_CCMR1_OFFSET) +#define STM32_TIM17_CCER (STM32_TIM17_BASE+STM32_GTIM_CCER_OFFSET) +#define STM32_TIM17_CNT (STM32_TIM17_BASE+STM32_GTIM_CNT_OFFSET) +#define STM32_TIM17_PSC (STM32_TIM17_BASE+STM32_GTIM_PSC_OFFSET) +#define STM32_TIM17_ARR (STM32_TIM17_BASE+STM32_GTIM_ARR_OFFSET) +#define STM32_TIM17_RCR (STM32_TIM17_BASE+STM32_GTIM_RCR_OFFSET) +#define STM32_TIM17_CCR1 (STM32_TIM17_BASE+STM32_GTIM_CCR1_OFFSET) +#define STM32_TIM17_BDTR (STM32_TIM17_BASE+STM32_GTIM_BDTR_OFFSET) +#define STM32_TIM17_DCR (STM32_TIM17_BASE+STM32_GTIM_DCR_OFFSET) +#define STM32_TIM17_DMAR (STM32_TIM17_BASE+STM32_GTIM_DMAR_OFFSET) /* Basic Timers - TIM6 and TIM7 */ -#define STM32L4_TIM6_CR1 (STM32L4_TIM6_BASE+STM32L4_BTIM_CR1_OFFSET) -#define STM32L4_TIM6_CR2 (STM32L4_TIM6_BASE+STM32L4_BTIM_CR2_OFFSET) -#define STM32L4_TIM6_DIER (STM32L4_TIM6_BASE+STM32L4_BTIM_DIER_OFFSET) -#define STM32L4_TIM6_SR (STM32L4_TIM6_BASE+STM32L4_BTIM_SR_OFFSET) -#define STM32L4_TIM6_EGR (STM32L4_TIM6_BASE+STM32L4_BTIM_EGR_OFFSET) -#define STM32L4_TIM6_CNT (STM32L4_TIM6_BASE+STM32L4_BTIM_CNT_OFFSET) -#define STM32L4_TIM6_PSC (STM32L4_TIM6_BASE+STM32L4_BTIM_PSC_OFFSET) -#define STM32L4_TIM6_ARR (STM32L4_TIM6_BASE+STM32L4_BTIM_ARR_OFFSET) - -#define STM32L4_TIM7_CR1 (STM32L4_TIM7_BASE+STM32L4_BTIM_CR1_OFFSET) -#define STM32L4_TIM7_CR2 (STM32L4_TIM7_BASE+STM32L4_BTIM_CR2_OFFSET) -#define STM32L4_TIM7_DIER (STM32L4_TIM7_BASE+STM32L4_BTIM_DIER_OFFSET) -#define STM32L4_TIM7_SR (STM32L4_TIM7_BASE+STM32L4_BTIM_SR_OFFSET) -#define STM32L4_TIM7_EGR (STM32L4_TIM7_BASE+STM32L4_BTIM_EGR_OFFSET) -#define STM32L4_TIM7_CNT (STM32L4_TIM7_BASE+STM32L4_BTIM_CNT_OFFSET) -#define STM32L4_TIM7_PSC (STM32L4_TIM7_BASE+STM32L4_BTIM_PSC_OFFSET) -#define STM32L4_TIM7_ARR (STM32L4_TIM7_BASE+STM32L4_BTIM_ARR_OFFSET) +#define STM32_TIM6_CR1 (STM32_TIM6_BASE+STM32_BTIM_CR1_OFFSET) +#define STM32_TIM6_CR2 (STM32_TIM6_BASE+STM32_BTIM_CR2_OFFSET) +#define STM32_TIM6_DIER (STM32_TIM6_BASE+STM32_BTIM_DIER_OFFSET) +#define STM32_TIM6_SR (STM32_TIM6_BASE+STM32_BTIM_SR_OFFSET) +#define STM32_TIM6_EGR (STM32_TIM6_BASE+STM32_BTIM_EGR_OFFSET) +#define STM32_TIM6_CNT (STM32_TIM6_BASE+STM32_BTIM_CNT_OFFSET) +#define STM32_TIM6_PSC (STM32_TIM6_BASE+STM32_BTIM_PSC_OFFSET) +#define STM32_TIM6_ARR (STM32_TIM6_BASE+STM32_BTIM_ARR_OFFSET) + +#define STM32_TIM7_CR1 (STM32_TIM7_BASE+STM32_BTIM_CR1_OFFSET) +#define STM32_TIM7_CR2 (STM32_TIM7_BASE+STM32_BTIM_CR2_OFFSET) +#define STM32_TIM7_DIER (STM32_TIM7_BASE+STM32_BTIM_DIER_OFFSET) +#define STM32_TIM7_SR (STM32_TIM7_BASE+STM32_BTIM_SR_OFFSET) +#define STM32_TIM7_EGR (STM32_TIM7_BASE+STM32_BTIM_EGR_OFFSET) +#define STM32_TIM7_CNT (STM32_TIM7_BASE+STM32_BTIM_CNT_OFFSET) +#define STM32_TIM7_PSC (STM32_TIM7_BASE+STM32_BTIM_PSC_OFFSET) +#define STM32_TIM7_ARR (STM32_TIM7_BASE+STM32_BTIM_ARR_OFFSET) /* Register Bitfield Definitions ********************************************/ @@ -1124,4 +1124,4 @@ #define BTIM_EGR_UG (1 << 0) /* Bit 0: Update generation */ -#endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_TIM_H */ +#endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32_TIM_H */ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4_uart.h b/arch/arm/src/stm32l4/hardware/stm32l4_uart.h index c904dba002a48..cf3135593e540 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4_uart.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4_uart.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_UART_H -#define __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_UART_H +#ifndef __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32_UART_H +#define __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32_UART_H /**************************************************************************** * Included Files @@ -37,88 +37,88 @@ /* Register Offsets *********************************************************/ -#define STM32L4_USART_CR1_OFFSET 0x0000 /* Control register 1 */ -#define STM32L4_USART_CR2_OFFSET 0x0004 /* Control register 2 */ -#define STM32L4_USART_CR3_OFFSET 0x0008 /* Control register 3 */ -#define STM32L4_USART_BRR_OFFSET 0x000c /* Baud Rate register */ -#define STM32L4_USART_GTPR_OFFSET 0x0010 /* Guard time and prescaler register */ -#define STM32L4_USART_RTOR_OFFSET 0x0014 /* Receiver timeout register */ -#define STM32L4_USART_RQR_OFFSET 0x0018 /* Request register */ -#define STM32L4_USART_ISR_OFFSET 0x001c /* Interrupt and status register */ -#define STM32L4_USART_ICR_OFFSET 0x0020 /* Interrupt flag clear register */ -#define STM32L4_USART_RDR_OFFSET 0x0024 /* Receive Data register */ -#define STM32L4_USART_TDR_OFFSET 0x0028 /* Transmit Data register */ +#define STM32_USART_CR1_OFFSET 0x0000 /* Control register 1 */ +#define STM32_USART_CR2_OFFSET 0x0004 /* Control register 2 */ +#define STM32_USART_CR3_OFFSET 0x0008 /* Control register 3 */ +#define STM32_USART_BRR_OFFSET 0x000c /* Baud Rate register */ +#define STM32_USART_GTPR_OFFSET 0x0010 /* Guard time and prescaler register */ +#define STM32_USART_RTOR_OFFSET 0x0014 /* Receiver timeout register */ +#define STM32_USART_RQR_OFFSET 0x0018 /* Request register */ +#define STM32_USART_ISR_OFFSET 0x001c /* Interrupt and status register */ +#define STM32_USART_ICR_OFFSET 0x0020 /* Interrupt flag clear register */ +#define STM32_USART_RDR_OFFSET 0x0024 /* Receive Data register */ +#define STM32_USART_TDR_OFFSET 0x0028 /* Transmit Data register */ /* Register Addresses *******************************************************/ -#if STM32L4_NUSART > 0 -# define STM32L4_USART1_CR1 (STM32L4_USART1_BASE+STM32L4_USART_CR1_OFFSET) -# define STM32L4_USART1_CR2 (STM32L4_USART1_BASE+STM32L4_USART_CR2_OFFSET) -# define STM32L4_USART1_CR3 (STM32L4_USART1_BASE+STM32L4_USART_CR3_OFFSET) -# define STM32L4_USART1_BRR (STM32L4_USART1_BASE+STM32L4_USART_BRR_OFFSET) -# define STM32L4_USART1_GTPR (STM32L4_USART1_BASE+STM32L4_USART_GTPR_OFFSET) -# define STM32L4_USART1_RTOR (STM32L4_USART1_BASE+STM32L4_USART_RTOR_OFFSET) -# define STM32L4_USART1_RQR (STM32L4_USART1_BASE+STM32L4_USART_RQR_OFFSET) -# define STM32L4_USART1_ISR (STM32L4_USART1_BASE+STM32L4_USART_ISR_OFFSET) -# define STM32L4_USART1_ICR (STM32L4_USART1_BASE+STM32L4_USART_ICR_OFFSET) -# define STM32L4_USART1_RDR (STM32L4_USART1_BASE+STM32L4_USART_RDR_OFFSET) -# define STM32L4_USART1_TDR (STM32L4_USART1_BASE+STM32L4_USART_TDR_OFFSET) +#if STM32_NUSART > 0 +# define STM32_USART1_CR1 (STM32_USART1_BASE+STM32_USART_CR1_OFFSET) +# define STM32_USART1_CR2 (STM32_USART1_BASE+STM32_USART_CR2_OFFSET) +# define STM32_USART1_CR3 (STM32_USART1_BASE+STM32_USART_CR3_OFFSET) +# define STM32_USART1_BRR (STM32_USART1_BASE+STM32_USART_BRR_OFFSET) +# define STM32_USART1_GTPR (STM32_USART1_BASE+STM32_USART_GTPR_OFFSET) +# define STM32_USART1_RTOR (STM32_USART1_BASE+STM32_USART_RTOR_OFFSET) +# define STM32_USART1_RQR (STM32_USART1_BASE+STM32_USART_RQR_OFFSET) +# define STM32_USART1_ISR (STM32_USART1_BASE+STM32_USART_ISR_OFFSET) +# define STM32_USART1_ICR (STM32_USART1_BASE+STM32_USART_ICR_OFFSET) +# define STM32_USART1_RDR (STM32_USART1_BASE+STM32_USART_RDR_OFFSET) +# define STM32_USART1_TDR (STM32_USART1_BASE+STM32_USART_TDR_OFFSET) #endif -#if STM32L4_NUSART > 1 -# define STM32L4_USART2_CR1 (STM32L4_USART2_BASE+STM32L4_USART_CR1_OFFSET) -# define STM32L4_USART2_CR2 (STM32L4_USART2_BASE+STM32L4_USART_CR2_OFFSET) -# define STM32L4_USART2_CR3 (STM32L4_USART2_BASE+STM32L4_USART_CR3_OFFSET) -# define STM32L4_USART2_BRR (STM32L4_USART2_BASE+STM32L4_USART_BRR_OFFSET) -# define STM32L4_USART2_GTPR (STM32L4_USART2_BASE+STM32L4_USART_GTPR_OFFSET) -# define STM32L4_USART2_RTOR (STM32L4_USART2_BASE+STM32L4_USART_RTOR_OFFSET) -# define STM32L4_USART2_RQR (STM32L4_USART2_BASE+STM32L4_USART_RQR_OFFSET) -# define STM32L4_USART2_ISR (STM32L4_USART2_BASE+STM32L4_USART_ISR_OFFSET) -# define STM32L4_USART2_ICR (STM32L4_USART2_BASE+STM32L4_USART_ICR_OFFSET) -# define STM32L4_USART2_RDR (STM32L4_USART2_BASE+STM32L4_USART_RDR_OFFSET) -# define STM32L4_USART2_TDR (STM32L4_USART2_BASE+STM32L4_USART_TDR_OFFSET) +#if STM32_NUSART > 1 +# define STM32_USART2_CR1 (STM32_USART2_BASE+STM32_USART_CR1_OFFSET) +# define STM32_USART2_CR2 (STM32_USART2_BASE+STM32_USART_CR2_OFFSET) +# define STM32_USART2_CR3 (STM32_USART2_BASE+STM32_USART_CR3_OFFSET) +# define STM32_USART2_BRR (STM32_USART2_BASE+STM32_USART_BRR_OFFSET) +# define STM32_USART2_GTPR (STM32_USART2_BASE+STM32_USART_GTPR_OFFSET) +# define STM32_USART2_RTOR (STM32_USART2_BASE+STM32_USART_RTOR_OFFSET) +# define STM32_USART2_RQR (STM32_USART2_BASE+STM32_USART_RQR_OFFSET) +# define STM32_USART2_ISR (STM32_USART2_BASE+STM32_USART_ISR_OFFSET) +# define STM32_USART2_ICR (STM32_USART2_BASE+STM32_USART_ICR_OFFSET) +# define STM32_USART2_RDR (STM32_USART2_BASE+STM32_USART_RDR_OFFSET) +# define STM32_USART2_TDR (STM32_USART2_BASE+STM32_USART_TDR_OFFSET) #endif -#if STM32L4_NUSART > 2 -# define STM32L4_USART3_CR1 (STM32L4_USART3_BASE+STM32L4_USART_CR1_OFFSET) -# define STM32L4_USART3_CR2 (STM32L4_USART3_BASE+STM32L4_USART_CR2_OFFSET) -# define STM32L4_USART3_CR3 (STM32L4_USART3_BASE+STM32L4_USART_CR3_OFFSET) -# define STM32L4_USART3_BRR (STM32L4_USART3_BASE+STM32L4_USART_BRR_OFFSET) -# define STM32L4_USART3_GTPR (STM32L4_USART3_BASE+STM32L4_USART_GTPR_OFFSET) -# define STM32L4_USART3_RTOR (STM32L4_USART3_BASE+STM32L4_USART_RTOR_OFFSET) -# define STM32L4_USART3_RQR (STM32L4_USART3_BASE+STM32L4_USART_RQR_OFFSET) -# define STM32L4_USART3_ISR (STM32L4_USART3_BASE+STM32L4_USART_ISR_OFFSET) -# define STM32L4_USART3_ICR (STM32L4_USART3_BASE+STM32L4_USART_ICR_OFFSET) -# define STM32L4_USART3_RDR (STM32L4_USART3_BASE+STM32L4_USART_RDR_OFFSET) -# define STM32L4_USART3_TDR (STM32L4_USART3_BASE+STM32L4_USART_TDR_OFFSET) +#if STM32_NUSART > 2 +# define STM32_USART3_CR1 (STM32_USART3_BASE+STM32_USART_CR1_OFFSET) +# define STM32_USART3_CR2 (STM32_USART3_BASE+STM32_USART_CR2_OFFSET) +# define STM32_USART3_CR3 (STM32_USART3_BASE+STM32_USART_CR3_OFFSET) +# define STM32_USART3_BRR (STM32_USART3_BASE+STM32_USART_BRR_OFFSET) +# define STM32_USART3_GTPR (STM32_USART3_BASE+STM32_USART_GTPR_OFFSET) +# define STM32_USART3_RTOR (STM32_USART3_BASE+STM32_USART_RTOR_OFFSET) +# define STM32_USART3_RQR (STM32_USART3_BASE+STM32_USART_RQR_OFFSET) +# define STM32_USART3_ISR (STM32_USART3_BASE+STM32_USART_ISR_OFFSET) +# define STM32_USART3_ICR (STM32_USART3_BASE+STM32_USART_ICR_OFFSET) +# define STM32_USART3_RDR (STM32_USART3_BASE+STM32_USART_RDR_OFFSET) +# define STM32_USART3_TDR (STM32_USART3_BASE+STM32_USART_TDR_OFFSET) #endif -#if STM32L4_NUSART > 3 -# define STM32L4_UART4_CR1 (STM32L4_UART4_BASE+STM32L4_USART_CR1_OFFSET) -# define STM32L4_UART4_CR2 (STM32L4_UART4_BASE+STM32L4_USART_CR2_OFFSET) -# define STM32L4_UART4_CR3 (STM32L4_UART4_BASE+STM32L4_USART_CR3_OFFSET) -# define STM32L4_UART4_BRR (STM32L4_UART4_BASE+STM32L4_USART_BRR_OFFSET) -# define STM32L4_UART4_GTPR (STM32L4_UART4_BASE+STM32L4_USART_GTPR_OFFSET) -# define STM32L4_UART4_RTOR (STM32L4_UART4_BASE+STM32L4_USART_RTOR_OFFSET) -# define STM32L4_UART4_RQR (STM32L4_UART4_BASE+STM32L4_USART_RQR_OFFSET) -# define STM32L4_UART4_ISR (STM32L4_UART4_BASE+STM32L4_USART_ISR_OFFSET) -# define STM32L4_UART4_ICR (STM32L4_UART4_BASE+STM32L4_USART_ICR_OFFSET) -# define STM32L4_UART4_RDR (STM32L4_UART4_BASE+STM32L4_USART_RDR_OFFSET) -# define STM32L4_UART4_TDR (STM32L4_UART4_BASE+STM32L4_USART_TDR_OFFSET) +#if STM32_NUSART > 3 +# define STM32_UART4_CR1 (STM32_UART4_BASE+STM32_USART_CR1_OFFSET) +# define STM32_UART4_CR2 (STM32_UART4_BASE+STM32_USART_CR2_OFFSET) +# define STM32_UART4_CR3 (STM32_UART4_BASE+STM32_USART_CR3_OFFSET) +# define STM32_UART4_BRR (STM32_UART4_BASE+STM32_USART_BRR_OFFSET) +# define STM32_UART4_GTPR (STM32_UART4_BASE+STM32_USART_GTPR_OFFSET) +# define STM32_UART4_RTOR (STM32_UART4_BASE+STM32_USART_RTOR_OFFSET) +# define STM32_UART4_RQR (STM32_UART4_BASE+STM32_USART_RQR_OFFSET) +# define STM32_UART4_ISR (STM32_UART4_BASE+STM32_USART_ISR_OFFSET) +# define STM32_UART4_ICR (STM32_UART4_BASE+STM32_USART_ICR_OFFSET) +# define STM32_UART4_RDR (STM32_UART4_BASE+STM32_USART_RDR_OFFSET) +# define STM32_UART4_TDR (STM32_UART4_BASE+STM32_USART_TDR_OFFSET) #endif -#if STM32L4_NUSART > 4 -# define STM32L4_UART5_CR1 (STM32L4_UART5_BASE+STM32L4_USART_CR1_OFFSET) -# define STM32L4_UART5_CR2 (STM32L4_UART5_BASE+STM32L4_USART_CR2_OFFSET) -# define STM32L4_UART5_CR3 (STM32L4_UART5_BASE+STM32L4_USART_CR3_OFFSET) -# define STM32L4_UART5_BRR (STM32L4_UART5_BASE+STM32L4_USART_BRR_OFFSET) -# define STM32L4_UART5_GTPR (STM32L4_UART5_BASE+STM32L4_USART_GTPR_OFFSET) -# define STM32L4_UART5_RTOR (STM32L4_UART5_BASE+STM32L4_USART_RTOR_OFFSET) -# define STM32L4_UART5_RQR (STM32L4_UART5_BASE+STM32L4_USART_RQR_OFFSET) -# define STM32L4_UART5_ISR (STM32L4_UART5_BASE+STM32L4_USART_ISR_OFFSET) -# define STM32L4_UART5_ICR (STM32L4_UART5_BASE+STM32L4_USART_ICR_OFFSET) -# define STM32L4_UART5_RDR (STM32L4_UART5_BASE+STM32L4_USART_RDR_OFFSET) -# define STM32L4_UART5_TDR (STM32L4_UART5_BASE+STM32L4_USART_TDR_OFFSET) +#if STM32_NUSART > 4 +# define STM32_UART5_CR1 (STM32_UART5_BASE+STM32_USART_CR1_OFFSET) +# define STM32_UART5_CR2 (STM32_UART5_BASE+STM32_USART_CR2_OFFSET) +# define STM32_UART5_CR3 (STM32_UART5_BASE+STM32_USART_CR3_OFFSET) +# define STM32_UART5_BRR (STM32_UART5_BASE+STM32_USART_BRR_OFFSET) +# define STM32_UART5_GTPR (STM32_UART5_BASE+STM32_USART_GTPR_OFFSET) +# define STM32_UART5_RTOR (STM32_UART5_BASE+STM32_USART_RTOR_OFFSET) +# define STM32_UART5_RQR (STM32_UART5_BASE+STM32_USART_RQR_OFFSET) +# define STM32_UART5_ISR (STM32_UART5_BASE+STM32_USART_ISR_OFFSET) +# define STM32_UART5_ICR (STM32_UART5_BASE+STM32_USART_ICR_OFFSET) +# define STM32_UART5_RDR (STM32_UART5_BASE+STM32_USART_RDR_OFFSET) +# define STM32_UART5_TDR (STM32_UART5_BASE+STM32_USART_TDR_OFFSET) #endif /* Register Bitfield Definitions ********************************************/ @@ -308,4 +308,4 @@ * Public Functions Prototypes ****************************************************************************/ -#endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_UART_H */ +#endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32_UART_H */ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4_usbdev.h b/arch/arm/src/stm32l4/hardware/stm32l4_usbdev.h index acea9cc7e31e9..e3adb9b3109dc 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4_usbdev.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4_usbdev.h @@ -30,7 +30,7 @@ #include #include -#if defined(CONFIG_STM32L4_STM32L4X2) +#if defined(CONFIG_STM32_STM32L4X2) /**************************************************************************** * Pre-processor Definitions @@ -40,71 +40,71 @@ /* Endpoint Registers */ -#define STM32L4_USB_EPR_OFFSET(n) ((n) << 2) /* USB endpoint n register (16-bits) */ +#define STM32_USB_EPR_OFFSET(n) ((n) << 2) /* USB endpoint n register (16-bits) */ -#define STM32L4_USB_EP0R_OFFSET 0x0000 /* USB endpoint 0 register (16-bits) */ -#define STM32L4_USB_EP1R_OFFSET 0x0004 /* USB endpoint 1 register (16-bits) */ -#define STM32L4_USB_EP2R_OFFSET 0x0008 /* USB endpoint 2 register (16-bits) */ -#define STM32L4_USB_EP3R_OFFSET 0x000c /* USB endpoint 3 register (16-bits) */ -#define STM32L4_USB_EP4R_OFFSET 0x0010 /* USB endpoint 4 register (16-bits) */ -#define STM32L4_USB_EP5R_OFFSET 0x0014 /* USB endpoint 5 register (16-bits) */ -#define STM32L4_USB_EP6R_OFFSET 0x0018 /* USB endpoint 6 register (16-bits) */ -#define STM32L4_USB_EP7R_OFFSET 0x001c /* USB endpoint 7 register (16-bits) */ +#define STM32_USB_EP0R_OFFSET 0x0000 /* USB endpoint 0 register (16-bits) */ +#define STM32_USB_EP1R_OFFSET 0x0004 /* USB endpoint 1 register (16-bits) */ +#define STM32_USB_EP2R_OFFSET 0x0008 /* USB endpoint 2 register (16-bits) */ +#define STM32_USB_EP3R_OFFSET 0x000c /* USB endpoint 3 register (16-bits) */ +#define STM32_USB_EP4R_OFFSET 0x0010 /* USB endpoint 4 register (16-bits) */ +#define STM32_USB_EP5R_OFFSET 0x0014 /* USB endpoint 5 register (16-bits) */ +#define STM32_USB_EP6R_OFFSET 0x0018 /* USB endpoint 6 register (16-bits) */ +#define STM32_USB_EP7R_OFFSET 0x001c /* USB endpoint 7 register (16-bits) */ /* Common Registers */ -#define STM32L4_USB_CNTR_OFFSET 0x0040 /* USB control register (16-bits) */ -#define STM32L4_USB_ISTR_OFFSET 0x0044 /* USB interrupt status register (16-bits) */ -#define STM32L4_USB_FNR_OFFSET 0x0048 /* USB frame number register (16-bits) */ -#define STM32L4_USB_DADDR_OFFSET 0x004c /* USB device address (16-bits) */ -#define STM32L4_USB_BTABLE_OFFSET 0x0050 /* Buffer table address (16-bits) */ -#define STM32L4_USB_LPMCSR_OFFSET 0x0054 /* LPM control and status register */ -#define STM32L4_USB_BCDR_OFFSET 0x0058 /* Battery charging detector */ +#define STM32_USB_CNTR_OFFSET 0x0040 /* USB control register (16-bits) */ +#define STM32_USB_ISTR_OFFSET 0x0044 /* USB interrupt status register (16-bits) */ +#define STM32_USB_FNR_OFFSET 0x0048 /* USB frame number register (16-bits) */ +#define STM32_USB_DADDR_OFFSET 0x004c /* USB device address (16-bits) */ +#define STM32_USB_BTABLE_OFFSET 0x0050 /* Buffer table address (16-bits) */ +#define STM32_USB_LPMCSR_OFFSET 0x0054 /* LPM control and status register */ +#define STM32_USB_BCDR_OFFSET 0x0058 /* Battery charging detector */ /* Buffer Descriptor Table (Relatative to BTABLE address) */ -#define STM32L4_USB_ADDR_TX_WOFFSET (0) /* Transmission buffer address n (16-bits) */ -#define STM32L4_USB_COUNT_TX_WOFFSET (2) /* Transmission byte count n (16-bits) */ -#define STM32L4_USB_ADDR_RX_WOFFSET (4) /* Reception buffer address n (16-bits) */ -#define STM32L4_USB_COUNT_RX_WOFFSET (6) /* Reception byte count n (16-bits) */ +#define STM32_USB_ADDR_TX_WOFFSET (0) /* Transmission buffer address n (16-bits) */ +#define STM32_USB_COUNT_TX_WOFFSET (2) /* Transmission byte count n (16-bits) */ +#define STM32_USB_ADDR_RX_WOFFSET (4) /* Reception buffer address n (16-bits) */ +#define STM32_USB_COUNT_RX_WOFFSET (6) /* Reception byte count n (16-bits) */ -#define STM32L4_USB_BTABLE_RADDR(ep,o) (((uint32_t)getreg16(STM32L4_USB_BTABLE) + ((ep) << 3)) + (o)) -#define STM32L4_USB_ADDR_TX_OFFSET(ep) STM32L4_USB_BTABLE_RADDR(ep,STM32L4_USB_ADDR_TX_WOFFSET) -#define STM32L4_USB_COUNT_TX_OFFSET(ep) STM32L4_USB_BTABLE_RADDR(ep,STM32L4_USB_COUNT_TX_WOFFSET) -#define STM32L4_USB_ADDR_RX_OFFSET(ep) STM32L4_USB_BTABLE_RADDR(ep,STM32L4_USB_ADDR_RX_WOFFSET) -#define STM32L4_USB_COUNT_RX_OFFSET(ep) STM32L4_USB_BTABLE_RADDR(ep,STM32L4_USB_COUNT_RX_WOFFSET) +#define STM32_USB_BTABLE_RADDR(ep,o) (((uint32_t)getreg16(STM32_USB_BTABLE) + ((ep) << 3)) + (o)) +#define STM32_USB_ADDR_TX_OFFSET(ep) STM32_USB_BTABLE_RADDR(ep,STM32_USB_ADDR_TX_WOFFSET) +#define STM32_USB_COUNT_TX_OFFSET(ep) STM32_USB_BTABLE_RADDR(ep,STM32_USB_COUNT_TX_WOFFSET) +#define STM32_USB_ADDR_RX_OFFSET(ep) STM32_USB_BTABLE_RADDR(ep,STM32_USB_ADDR_RX_WOFFSET) +#define STM32_USB_COUNT_RX_OFFSET(ep) STM32_USB_BTABLE_RADDR(ep,STM32_USB_COUNT_RX_WOFFSET) /* Register Addresses *******************************************************/ /* Endpoint Registers */ -#define STM32L4_USB_EPR(n) (STM32L4_USB_FS_BASE + STM32L4_USB_EPR_OFFSET(n)) -#define STM32L4_USB_EP0R (STM32L4_USB_FS_BASE + STM32L4_USB_EP0R_OFFSET) -#define STM32L4_USB_EP1R (STM32L4_USB_FS_BASE + STM32L4_USB_EP1R_OFFSET) -#define STM32L4_USB_EP2R (STM32L4_USB_FS_BASE + STM32L4_USB_EP2R_OFFSET) -#define STM32L4_USB_EP3R (STM32L4_USB_FS_BASE + STM32L4_USB_EP3R_OFFSET) -#define STM32L4_USB_EP4R (STM32L4_USB_FS_BASE + STM32L4_USB_EP4R_OFFSET) -#define STM32L4_USB_EP5R (STM32L4_USB_FS_BASE + STM32L4_USB_EP5R_OFFSET) -#define STM32L4_USB_EP6R (STM32L4_USB_FS_BASE + STM32L4_USB_EP6R_OFFSET) -#define STM32L4_USB_EP7R (STM32L4_USB_FS_BASE + STM32L4_USB_EP7R_OFFSET) +#define STM32_USB_EPR(n) (STM32_USB_FS_BASE + STM32_USB_EPR_OFFSET(n)) +#define STM32_USB_EP0R (STM32_USB_FS_BASE + STM32_USB_EP0R_OFFSET) +#define STM32_USB_EP1R (STM32_USB_FS_BASE + STM32_USB_EP1R_OFFSET) +#define STM32_USB_EP2R (STM32_USB_FS_BASE + STM32_USB_EP2R_OFFSET) +#define STM32_USB_EP3R (STM32_USB_FS_BASE + STM32_USB_EP3R_OFFSET) +#define STM32_USB_EP4R (STM32_USB_FS_BASE + STM32_USB_EP4R_OFFSET) +#define STM32_USB_EP5R (STM32_USB_FS_BASE + STM32_USB_EP5R_OFFSET) +#define STM32_USB_EP6R (STM32_USB_FS_BASE + STM32_USB_EP6R_OFFSET) +#define STM32_USB_EP7R (STM32_USB_FS_BASE + STM32_USB_EP7R_OFFSET) /* Common Registers */ -#define STM32L4_USB_CNTR (STM32L4_USB_FS_BASE + STM32L4_USB_CNTR_OFFSET) -#define STM32L4_USB_ISTR (STM32L4_USB_FS_BASE + STM32L4_USB_ISTR_OFFSET) -#define STM32L4_USB_FNR (STM32L4_USB_FS_BASE + STM32L4_USB_FNR_OFFSET) -#define STM32L4_USB_DADDR (STM32L4_USB_FS_BASE + STM32L4_USB_DADDR_OFFSET) -#define STM32L4_USB_BTABLE (STM32L4_USB_FS_BASE + STM32L4_USB_BTABLE_OFFSET) -#define STM32L4_USB_LPMCSR (STM32L4_USB_FS_BASE + STM32L4_USB_LPMCSR_OFFSET) -#define STM32L4_USB_BCDR (STM32L4_USB_FS_BASE + STM32L4_USB_BCDR_OFFSET) +#define STM32_USB_CNTR (STM32_USB_FS_BASE + STM32_USB_CNTR_OFFSET) +#define STM32_USB_ISTR (STM32_USB_FS_BASE + STM32_USB_ISTR_OFFSET) +#define STM32_USB_FNR (STM32_USB_FS_BASE + STM32_USB_FNR_OFFSET) +#define STM32_USB_DADDR (STM32_USB_FS_BASE + STM32_USB_DADDR_OFFSET) +#define STM32_USB_BTABLE (STM32_USB_FS_BASE + STM32_USB_BTABLE_OFFSET) +#define STM32_USB_LPMCSR (STM32_USB_FS_BASE + STM32_USB_LPMCSR_OFFSET) +#define STM32_USB_BCDR (STM32_USB_FS_BASE + STM32_USB_BCDR_OFFSET) /* Buffer Descriptor Table (Relatative to BTABLE address) */ -#define STM32L4_USB_BTABLE_ADDR(ep,o) (STM32L4_USB_SRAM_BASE + STM32L4_USB_BTABLE_RADDR(ep,o)) -#define STM32L4_USB_ADDR_TX(ep) STM32L4_USB_BTABLE_ADDR(ep,STM32L4_USB_ADDR_TX_WOFFSET) -#define STM32L4_USB_COUNT_TX(ep) STM32L4_USB_BTABLE_ADDR(ep,STM32L4_USB_COUNT_TX_WOFFSET) -#define STM32L4_USB_ADDR_RX(ep) STM32L4_USB_BTABLE_ADDR(ep,STM32L4_USB_ADDR_RX_WOFFSET) -#define STM32L4_USB_COUNT_RX(ep) STM32L4_USB_BTABLE_ADDR(ep,STM32L4_USB_COUNT_RX_WOFFSET) +#define STM32_USB_BTABLE_ADDR(ep,o) (STM32_USB_SRAM_BASE + STM32_USB_BTABLE_RADDR(ep,o)) +#define STM32_USB_ADDR_TX(ep) STM32_USB_BTABLE_ADDR(ep,STM32_USB_ADDR_TX_WOFFSET) +#define STM32_USB_COUNT_TX(ep) STM32_USB_BTABLE_ADDR(ep,STM32_USB_COUNT_TX_WOFFSET) +#define STM32_USB_ADDR_RX(ep) STM32_USB_BTABLE_ADDR(ep,STM32_USB_ADDR_RX_WOFFSET) +#define STM32_USB_COUNT_RX(ep) STM32_USB_BTABLE_ADDR(ep,STM32_USB_COUNT_RX_WOFFSET) /* Register Bitfield Definitions ********************************************/ @@ -251,5 +251,5 @@ #define USB_BCDR_PS2DET (1 << 7) /* Bit 7: DM pull-up detection status */ #define USB_BCDR_DPPU (1 << 15) /* Bit 15: DP pull-up control */ -#endif /* CONFIG_STM32L4_STM32L4X2 */ +#endif /* CONFIG_STM32_STM32L4X2 */ #endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_USBDEV_H */ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4_wdg.h b/arch/arm/src/stm32l4/hardware/stm32l4_wdg.h index 335086592073e..b286b92dce290 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4_wdg.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4_wdg.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_WDG_H -#define __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_WDG_H +#ifndef __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32_WDG_H +#define __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32_WDG_H /**************************************************************************** * Included Files @@ -37,27 +37,27 @@ /* Register Offsets *********************************************************/ -#define STM32L4_IWDG_KR_OFFSET 0x0000 /* Key register (32-bit) */ -#define STM32L4_IWDG_PR_OFFSET 0x0004 /* Prescaler register (32-bit) */ -#define STM32L4_IWDG_RLR_OFFSET 0x0008 /* Reload register (32-bit) */ -#define STM32L4_IWDG_SR_OFFSET 0x000c /* Status register (32-bit) */ -#define STM32L4_IWDG_WINR_OFFSET 0x0010 /* Window register (32-bit) */ +#define STM32_IWDG_KR_OFFSET 0x0000 /* Key register (32-bit) */ +#define STM32_IWDG_PR_OFFSET 0x0004 /* Prescaler register (32-bit) */ +#define STM32_IWDG_RLR_OFFSET 0x0008 /* Reload register (32-bit) */ +#define STM32_IWDG_SR_OFFSET 0x000c /* Status register (32-bit) */ +#define STM32_IWDG_WINR_OFFSET 0x0010 /* Window register (32-bit) */ -#define STM32L4_WWDG_CR_OFFSET 0x0000 /* Control Register (32-bit) */ -#define STM32L4_WWDG_CFR_OFFSET 0x0004 /* Configuration register (32-bit) */ -#define STM32L4_WWDG_SR_OFFSET 0x0008 /* Status register (32-bit) */ +#define STM32_WWDG_CR_OFFSET 0x0000 /* Control Register (32-bit) */ +#define STM32_WWDG_CFR_OFFSET 0x0004 /* Configuration register (32-bit) */ +#define STM32_WWDG_SR_OFFSET 0x0008 /* Status register (32-bit) */ /* Register Addresses *******************************************************/ -#define STM32L4_IWDG_KR (STM32L4_IWDG_BASE+STM32L4_IWDG_KR_OFFSET) -#define STM32L4_IWDG_PR (STM32L4_IWDG_BASE+STM32L4_IWDG_PR_OFFSET) -#define STM32L4_IWDG_RLR (STM32L4_IWDG_BASE+STM32L4_IWDG_RLR_OFFSET) -#define STM32L4_IWDG_SR (STM32L4_IWDG_BASE+STM32L4_IWDG_SR_OFFSET) -#define STM32L4_IWDG_WINR (STM32L4_IWDG_BASE+STM32L4_IWDG_WINR_OFFSET) +#define STM32_IWDG_KR (STM32_IWDG_BASE+STM32_IWDG_KR_OFFSET) +#define STM32_IWDG_PR (STM32_IWDG_BASE+STM32_IWDG_PR_OFFSET) +#define STM32_IWDG_RLR (STM32_IWDG_BASE+STM32_IWDG_RLR_OFFSET) +#define STM32_IWDG_SR (STM32_IWDG_BASE+STM32_IWDG_SR_OFFSET) +#define STM32_IWDG_WINR (STM32_IWDG_BASE+STM32_IWDG_WINR_OFFSET) -#define STM32L4_WWDG_CR (STM32L4_WWDG_BASE+STM32L4_WWDG_CR_OFFSET) -#define STM32L4_WWDG_CFR (STM32L4_WWDG_BASE+STM32L4_WWDG_CFR_OFFSET) -#define STM32L4_WWDG_SR (STM32L4_WWDG_BASE+STM32L4_WWDG_SR_OFFSET) +#define STM32_WWDG_CR (STM32_WWDG_BASE+STM32_WWDG_CR_OFFSET) +#define STM32_WWDG_CFR (STM32_WWDG_BASE+STM32_WWDG_CFR_OFFSET) +#define STM32_WWDG_SR (STM32_WWDG_BASE+STM32_WWDG_SR_OFFSET) /* Register Bitfield Definitions ********************************************/ @@ -138,4 +138,4 @@ * Public Functions Prototypes ****************************************************************************/ -#endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_WDG_H */ +#endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32_WDG_H */ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4x3xx_dma.h b/arch/arm/src/stm32l4/hardware/stm32l4x3xx_dma.h index bc4070f7dfcb0..587031ae9344a 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4x3xx_dma.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4x3xx_dma.h @@ -34,141 +34,141 @@ /* Register Offsets *********************************************************/ -#define STM32L4_DMA_ISR_OFFSET 0x0000 /* DMA interrupt status register */ -#define STM32L4_DMA_IFCR_OFFSET 0x0004 /* DMA interrupt flag clear register */ - -#define STM32L4_DMACHAN_OFFSET(n) (0x0014*(n)) -#define STM32L4_DMACHAN1_OFFSET 0x0000 -#define STM32L4_DMACHAN2_OFFSET 0x0014 -#define STM32L4_DMACHAN3_OFFSET 0x0028 -#define STM32L4_DMACHAN4_OFFSET 0x003c -#define STM32L4_DMACHAN5_OFFSET 0x0050 -#define STM32L4_DMACHAN6_OFFSET 0x0064 -#define STM32L4_DMACHAN7_OFFSET 0x0078 - -#define STM32L4_DMACHAN_CCR_OFFSET 0x0008 /* DMA channel configuration register */ -#define STM32L4_DMACHAN_CNDTR_OFFSET 0x000c /* DMA channel number of data register */ -#define STM32L4_DMACHAN_CPAR_OFFSET 0x0010 /* DMA channel peripheral address register */ -#define STM32L4_DMACHAN_CMAR_OFFSET 0x0014 /* DMA channel memory address register */ - -#define STM32L4_DMA_CCR_OFFSET(n) (STM32L4_DMACHAN_CCR_OFFSET+STM32L4_DMACHAN_OFFSET(n)) -#define STM32L4_DMA_CNDTR_OFFSET(n) (STM32L4_DMACHAN_CNDTR_OFFSET+STM32L4_DMACHAN_OFFSET(n)) -#define STM32L4_DMA_CPAR_OFFSET(n) (STM32L4_DMACHAN_CPAR_OFFSET+STM32L4_DMACHAN_OFFSET(n)) -#define STM32L4_DMA_CMAR_OFFSET(n) (STM32L4_DMACHAN_CMAR_OFFSET+STM32L4_DMACHAN_OFFSET(n)) - -#define STM32L4_DMA_CCR1_OFFSET 0x0008 /* DMA channel 1 configuration register */ -#define STM32L4_DMA_CCR2_OFFSET 0x001c /* DMA channel 2 configuration register */ -#define STM32L4_DMA_CCR3_OFFSET 0x0030 /* DMA channel 3 configuration register */ -#define STM32L4_DMA_CCR4_OFFSET 0x0044 /* DMA channel 4 configuration register */ -#define STM32L4_DMA_CCR5_OFFSET 0x0058 /* DMA channel 5 configuration register */ -#define STM32L4_DMA_CCR6_OFFSET 0x006c /* DMA channel 6 configuration register */ -#define STM32L4_DMA_CCR7_OFFSET 0x0080 /* DMA channel 7 configuration register */ - -#define STM32L4_DMA_CNDTR1_OFFSET 0x000c /* DMA channel 1 number of data register */ -#define STM32L4_DMA_CNDTR2_OFFSET 0x0020 /* DMA channel 2 number of data register */ -#define STM32L4_DMA_CNDTR3_OFFSET 0x0034 /* DMA channel 3 number of data register */ -#define STM32L4_DMA_CNDTR4_OFFSET 0x0048 /* DMA channel 4 number of data register */ -#define STM32L4_DMA_CNDTR5_OFFSET 0x005c /* DMA channel 5 number of data register */ -#define STM32L4_DMA_CNDTR6_OFFSET 0x0070 /* DMA channel 6 number of data register */ -#define STM32L4_DMA_CNDTR7_OFFSET 0x0084 /* DMA channel 7 number of data register */ - -#define STM32L4_DMA_CPAR1_OFFSET 0x0010 /* DMA channel 1 peripheral address register */ -#define STM32L4_DMA_CPAR2_OFFSET 0x0024 /* DMA channel 2 peripheral address register */ -#define STM32L4_DMA_CPAR3_OFFSET 0x0038 /* DMA channel 3 peripheral address register */ -#define STM32L4_DMA_CPAR4_OFFSET 0x004c /* DMA channel 4 peripheral address register */ -#define STM32L4_DMA_CPAR5_OFFSET 0x0060 /* DMA channel 5 peripheral address register */ -#define STM32L4_DMA_CPAR6_OFFSET 0x0074 /* DMA channel 6 peripheral address register */ -#define STM32L4_DMA_CPAR7_OFFSET 0x0088 /* DMA channel 7 peripheral address register */ - -#define STM32L4_DMA_CMAR1_OFFSET 0x0014 /* DMA channel 1 memory address register */ -#define STM32L4_DMA_CMAR2_OFFSET 0x0028 /* DMA channel 2 memory address register */ -#define STM32L4_DMA_CMAR3_OFFSET 0x003c /* DMA channel 3 memory address register */ -#define STM32L4_DMA_CMAR4_OFFSET 0x0050 /* DMA channel 4 memory address register */ -#define STM32L4_DMA_CMAR5_OFFSET 0x0064 /* DMA channel 5 memory address register */ -#define STM32L4_DMA_CMAR6_OFFSET 0x0078 /* DMA channel 6 memory address register */ -#define STM32L4_DMA_CMAR7_OFFSET 0x008c /* DMA channel 7 memory address register */ - -#define STM32L4_DMA_CSELR_OFFSET 0x00a8 /* DMA channel selection register */ +#define STM32_DMA_ISR_OFFSET 0x0000 /* DMA interrupt status register */ +#define STM32_DMA_IFCR_OFFSET 0x0004 /* DMA interrupt flag clear register */ + +#define STM32_DMACHAN_OFFSET(n) (0x0014*(n)) +#define STM32_DMACHAN1_OFFSET 0x0000 +#define STM32_DMACHAN2_OFFSET 0x0014 +#define STM32_DMACHAN3_OFFSET 0x0028 +#define STM32_DMACHAN4_OFFSET 0x003c +#define STM32_DMACHAN5_OFFSET 0x0050 +#define STM32_DMACHAN6_OFFSET 0x0064 +#define STM32_DMACHAN7_OFFSET 0x0078 + +#define STM32_DMACHAN_CCR_OFFSET 0x0008 /* DMA channel configuration register */ +#define STM32_DMACHAN_CNDTR_OFFSET 0x000c /* DMA channel number of data register */ +#define STM32_DMACHAN_CPAR_OFFSET 0x0010 /* DMA channel peripheral address register */ +#define STM32_DMACHAN_CMAR_OFFSET 0x0014 /* DMA channel memory address register */ + +#define STM32_DMA_CCR_OFFSET(n) (STM32_DMACHAN_CCR_OFFSET+STM32_DMACHAN_OFFSET(n)) +#define STM32_DMA_CNDTR_OFFSET(n) (STM32_DMACHAN_CNDTR_OFFSET+STM32_DMACHAN_OFFSET(n)) +#define STM32_DMA_CPAR_OFFSET(n) (STM32_DMACHAN_CPAR_OFFSET+STM32_DMACHAN_OFFSET(n)) +#define STM32_DMA_CMAR_OFFSET(n) (STM32_DMACHAN_CMAR_OFFSET+STM32_DMACHAN_OFFSET(n)) + +#define STM32_DMA_CCR1_OFFSET 0x0008 /* DMA channel 1 configuration register */ +#define STM32_DMA_CCR2_OFFSET 0x001c /* DMA channel 2 configuration register */ +#define STM32_DMA_CCR3_OFFSET 0x0030 /* DMA channel 3 configuration register */ +#define STM32_DMA_CCR4_OFFSET 0x0044 /* DMA channel 4 configuration register */ +#define STM32_DMA_CCR5_OFFSET 0x0058 /* DMA channel 5 configuration register */ +#define STM32_DMA_CCR6_OFFSET 0x006c /* DMA channel 6 configuration register */ +#define STM32_DMA_CCR7_OFFSET 0x0080 /* DMA channel 7 configuration register */ + +#define STM32_DMA_CNDTR1_OFFSET 0x000c /* DMA channel 1 number of data register */ +#define STM32_DMA_CNDTR2_OFFSET 0x0020 /* DMA channel 2 number of data register */ +#define STM32_DMA_CNDTR3_OFFSET 0x0034 /* DMA channel 3 number of data register */ +#define STM32_DMA_CNDTR4_OFFSET 0x0048 /* DMA channel 4 number of data register */ +#define STM32_DMA_CNDTR5_OFFSET 0x005c /* DMA channel 5 number of data register */ +#define STM32_DMA_CNDTR6_OFFSET 0x0070 /* DMA channel 6 number of data register */ +#define STM32_DMA_CNDTR7_OFFSET 0x0084 /* DMA channel 7 number of data register */ + +#define STM32_DMA_CPAR1_OFFSET 0x0010 /* DMA channel 1 peripheral address register */ +#define STM32_DMA_CPAR2_OFFSET 0x0024 /* DMA channel 2 peripheral address register */ +#define STM32_DMA_CPAR3_OFFSET 0x0038 /* DMA channel 3 peripheral address register */ +#define STM32_DMA_CPAR4_OFFSET 0x004c /* DMA channel 4 peripheral address register */ +#define STM32_DMA_CPAR5_OFFSET 0x0060 /* DMA channel 5 peripheral address register */ +#define STM32_DMA_CPAR6_OFFSET 0x0074 /* DMA channel 6 peripheral address register */ +#define STM32_DMA_CPAR7_OFFSET 0x0088 /* DMA channel 7 peripheral address register */ + +#define STM32_DMA_CMAR1_OFFSET 0x0014 /* DMA channel 1 memory address register */ +#define STM32_DMA_CMAR2_OFFSET 0x0028 /* DMA channel 2 memory address register */ +#define STM32_DMA_CMAR3_OFFSET 0x003c /* DMA channel 3 memory address register */ +#define STM32_DMA_CMAR4_OFFSET 0x0050 /* DMA channel 4 memory address register */ +#define STM32_DMA_CMAR5_OFFSET 0x0064 /* DMA channel 5 memory address register */ +#define STM32_DMA_CMAR6_OFFSET 0x0078 /* DMA channel 6 memory address register */ +#define STM32_DMA_CMAR7_OFFSET 0x008c /* DMA channel 7 memory address register */ + +#define STM32_DMA_CSELR_OFFSET 0x00a8 /* DMA channel selection register */ /* Register Addresses *******************************************************/ -#define STM32L4_DMA1_ISRC (STM32L4_DMA1_BASE+STM32L4_DMA_ISR_OFFSET) -#define STM32L4_DMA1_IFCR (STM32L4_DMA1_BASE+STM32L4_DMA_IFCR_OFFSET) - -#define STM32L4_DMA1_CCR(n) (STM32L4_DMA1_BASE+STM32L4_DMA_CCR_OFFSET(n)) -#define STM32L4_DMA1_CCR1 (STM32L4_DMA1_BASE+STM32L4_DMA_CCR1_OFFSET) -#define STM32L4_DMA1_CCR2 (STM32L4_DMA1_BASE+STM32L4_DMA_CCR2_OFFSET) -#define STM32L4_DMA1_CCR3 (STM32L4_DMA1_BASE+STM32L4_DMA_CCR3_OFFSET) -#define STM32L4_DMA1_CCR4 (STM32L4_DMA1_BASE+STM32L4_DMA_CCR4_OFFSET) -#define STM32L4_DMA1_CCR5 (STM32L4_DMA1_BASE+STM32L4_DMA_CCR5_OFFSET) -#define STM32L4_DMA1_CCR6 (STM32L4_DMA1_BASE+STM32L4_DMA_CCR6_OFFSET) -#define STM32L4_DMA1_CCR7 (STM32L4_DMA1_BASE+STM32L4_DMA_CCR7_OFFSET) - -#define STM32L4_DMA1_CNDTR(n) (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR_OFFSET(n)) -#define STM32L4_DMA1_CNDTR1 (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR1_OFFSET) -#define STM32L4_DMA1_CNDTR2 (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR2_OFFSET) -#define STM32L4_DMA1_CNDTR3 (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR3_OFFSET) -#define STM32L4_DMA1_CNDTR4 (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR4_OFFSET) -#define STM32L4_DMA1_CNDTR5 (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR5_OFFSET) -#define STM32L4_DMA1_CNDTR6 (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR6_OFFSET) -#define STM32L4_DMA1_CNDTR7 (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR7_OFFSET) - -#define STM32L4_DMA1_CPAR(n) (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR_OFFSET(n)) -#define STM32L4_DMA1_CPAR1 (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR1_OFFSET) -#define STM32L4_DMA1_CPAR2 (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR2_OFFSET) -#define STM32L4_DMA1_CPAR3 (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR3_OFFSET) -#define STM32L4_DMA1_CPAR4 (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR4_OFFSET) -#define STM32L4_DMA1_CPAR5 (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR5_OFFSET) -#define STM32L4_DMA1_CPAR6 (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR6_OFFSET) -#define STM32L4_DMA1_CPAR7 (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR7_OFFSET) - -#define STM32L4_DMA1_CMAR(n) (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR_OFFSET(n)) -#define STM32L4_DMA1_CMAR1 (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR1_OFFSET) -#define STM32L4_DMA1_CMAR2 (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR2_OFFSET) -#define STM32L4_DMA1_CMAR3 (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR3_OFFSET) -#define STM32L4_DMA1_CMAR4 (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR4_OFFSET) -#define STM32L4_DMA1_CMAR5 (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR5_OFFSET) -#define STM32L4_DMA1_CMAR6 (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR6_OFFSET) -#define STM32L4_DMA1_CMAR7 (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR7_OFFSET) - -#define STM32L4_DMA2_ISRC (STM32L4_DMA2_BASE+STM32L4_DMA_ISR_OFFSET) -#define STM32L4_DMA2_IFCR (STM32L4_DMA2_BASE+STM32L4_DMA_IFCR_OFFSET) - -#define STM32L4_DMA2_CCR(n) (STM32L4_DMA2_BASE+STM32L4_DMA_CCR_OFFSET(n)) -#define STM32L4_DMA2_CCR1 (STM32L4_DMA2_BASE+STM32L4_DMA_CCR1_OFFSET) -#define STM32L4_DMA2_CCR2 (STM32L4_DMA2_BASE+STM32L4_DMA_CCR2_OFFSET) -#define STM32L4_DMA2_CCR3 (STM32L4_DMA2_BASE+STM32L4_DMA_CCR3_OFFSET) -#define STM32L4_DMA2_CCR4 (STM32L4_DMA2_BASE+STM32L4_DMA_CCR4_OFFSET) -#define STM32L4_DMA2_CCR5 (STM32L4_DMA2_BASE+STM32L4_DMA_CCR5_OFFSET) -#define STM32L4_DMA2_CCR6 (STM32L4_DMA2_BASE+STM32L4_DMA_CCR6_OFFSET) -#define STM32L4_DMA2_CCR7 (STM32L4_DMA2_BASE+STM32L4_DMA_CCR7_OFFSET) - -#define STM32L4_DMA2_CNDTR(n) (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR_OFFSET(n)) -#define STM32L4_DMA2_CNDTR1 (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR1_OFFSET) -#define STM32L4_DMA2_CNDTR2 (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR2_OFFSET) -#define STM32L4_DMA2_CNDTR3 (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR3_OFFSET) -#define STM32L4_DMA2_CNDTR4 (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR4_OFFSET) -#define STM32L4_DMA2_CNDTR5 (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR5_OFFSET) -#define STM32L4_DMA2_CNDTR6 (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR6_OFFSET) -#define STM32L4_DMA2_CNDTR7 (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR7_OFFSET) - -#define STM32L4_DMA2_CPAR(n) (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR_OFFSET(n)) -#define STM32L4_DMA2_CPAR1 (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR1_OFFSET) -#define STM32L4_DMA2_CPAR2 (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR2_OFFSET) -#define STM32L4_DMA2_CPAR3 (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR3_OFFSET) -#define STM32L4_DMA2_CPAR4 (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR4_OFFSET) -#define STM32L4_DMA2_CPAR5 (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR5_OFFSET) -#define STM32L4_DMA2_CPAR6 (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR6_OFFSET) -#define STM32L4_DMA2_CPAR7 (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR7_OFFSET) - -#define STM32L4_DMA2_CMAR(n) (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR_OFFSET(n)) -#define STM32L4_DMA2_CMAR1 (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR1_OFFSET) -#define STM32L4_DMA2_CMAR2 (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR2_OFFSET) -#define STM32L4_DMA2_CMAR3 (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR3_OFFSET) -#define STM32L4_DMA2_CMAR4 (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR4_OFFSET) -#define STM32L4_DMA2_CMAR5 (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR5_OFFSET) -#define STM32L4_DMA2_CMAR6 (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR6_OFFSET) -#define STM32L4_DMA2_CMAR7 (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR7_OFFSET) +#define STM32_DMA1_ISRC (STM32_DMA1_BASE+STM32_DMA_ISR_OFFSET) +#define STM32_DMA1_IFCR (STM32_DMA1_BASE+STM32_DMA_IFCR_OFFSET) + +#define STM32_DMA1_CCR(n) (STM32_DMA1_BASE+STM32_DMA_CCR_OFFSET(n)) +#define STM32_DMA1_CCR1 (STM32_DMA1_BASE+STM32_DMA_CCR1_OFFSET) +#define STM32_DMA1_CCR2 (STM32_DMA1_BASE+STM32_DMA_CCR2_OFFSET) +#define STM32_DMA1_CCR3 (STM32_DMA1_BASE+STM32_DMA_CCR3_OFFSET) +#define STM32_DMA1_CCR4 (STM32_DMA1_BASE+STM32_DMA_CCR4_OFFSET) +#define STM32_DMA1_CCR5 (STM32_DMA1_BASE+STM32_DMA_CCR5_OFFSET) +#define STM32_DMA1_CCR6 (STM32_DMA1_BASE+STM32_DMA_CCR6_OFFSET) +#define STM32_DMA1_CCR7 (STM32_DMA1_BASE+STM32_DMA_CCR7_OFFSET) + +#define STM32_DMA1_CNDTR(n) (STM32_DMA1_BASE+STM32_DMA_CNDTR_OFFSET(n)) +#define STM32_DMA1_CNDTR1 (STM32_DMA1_BASE+STM32_DMA_CNDTR1_OFFSET) +#define STM32_DMA1_CNDTR2 (STM32_DMA1_BASE+STM32_DMA_CNDTR2_OFFSET) +#define STM32_DMA1_CNDTR3 (STM32_DMA1_BASE+STM32_DMA_CNDTR3_OFFSET) +#define STM32_DMA1_CNDTR4 (STM32_DMA1_BASE+STM32_DMA_CNDTR4_OFFSET) +#define STM32_DMA1_CNDTR5 (STM32_DMA1_BASE+STM32_DMA_CNDTR5_OFFSET) +#define STM32_DMA1_CNDTR6 (STM32_DMA1_BASE+STM32_DMA_CNDTR6_OFFSET) +#define STM32_DMA1_CNDTR7 (STM32_DMA1_BASE+STM32_DMA_CNDTR7_OFFSET) + +#define STM32_DMA1_CPAR(n) (STM32_DMA1_BASE+STM32_DMA_CPAR_OFFSET(n)) +#define STM32_DMA1_CPAR1 (STM32_DMA1_BASE+STM32_DMA_CPAR1_OFFSET) +#define STM32_DMA1_CPAR2 (STM32_DMA1_BASE+STM32_DMA_CPAR2_OFFSET) +#define STM32_DMA1_CPAR3 (STM32_DMA1_BASE+STM32_DMA_CPAR3_OFFSET) +#define STM32_DMA1_CPAR4 (STM32_DMA1_BASE+STM32_DMA_CPAR4_OFFSET) +#define STM32_DMA1_CPAR5 (STM32_DMA1_BASE+STM32_DMA_CPAR5_OFFSET) +#define STM32_DMA1_CPAR6 (STM32_DMA1_BASE+STM32_DMA_CPAR6_OFFSET) +#define STM32_DMA1_CPAR7 (STM32_DMA1_BASE+STM32_DMA_CPAR7_OFFSET) + +#define STM32_DMA1_CMAR(n) (STM32_DMA1_BASE+STM32_DMA_CMAR_OFFSET(n)) +#define STM32_DMA1_CMAR1 (STM32_DMA1_BASE+STM32_DMA_CMAR1_OFFSET) +#define STM32_DMA1_CMAR2 (STM32_DMA1_BASE+STM32_DMA_CMAR2_OFFSET) +#define STM32_DMA1_CMAR3 (STM32_DMA1_BASE+STM32_DMA_CMAR3_OFFSET) +#define STM32_DMA1_CMAR4 (STM32_DMA1_BASE+STM32_DMA_CMAR4_OFFSET) +#define STM32_DMA1_CMAR5 (STM32_DMA1_BASE+STM32_DMA_CMAR5_OFFSET) +#define STM32_DMA1_CMAR6 (STM32_DMA1_BASE+STM32_DMA_CMAR6_OFFSET) +#define STM32_DMA1_CMAR7 (STM32_DMA1_BASE+STM32_DMA_CMAR7_OFFSET) + +#define STM32_DMA2_ISRC (STM32_DMA2_BASE+STM32_DMA_ISR_OFFSET) +#define STM32_DMA2_IFCR (STM32_DMA2_BASE+STM32_DMA_IFCR_OFFSET) + +#define STM32_DMA2_CCR(n) (STM32_DMA2_BASE+STM32_DMA_CCR_OFFSET(n)) +#define STM32_DMA2_CCR1 (STM32_DMA2_BASE+STM32_DMA_CCR1_OFFSET) +#define STM32_DMA2_CCR2 (STM32_DMA2_BASE+STM32_DMA_CCR2_OFFSET) +#define STM32_DMA2_CCR3 (STM32_DMA2_BASE+STM32_DMA_CCR3_OFFSET) +#define STM32_DMA2_CCR4 (STM32_DMA2_BASE+STM32_DMA_CCR4_OFFSET) +#define STM32_DMA2_CCR5 (STM32_DMA2_BASE+STM32_DMA_CCR5_OFFSET) +#define STM32_DMA2_CCR6 (STM32_DMA2_BASE+STM32_DMA_CCR6_OFFSET) +#define STM32_DMA2_CCR7 (STM32_DMA2_BASE+STM32_DMA_CCR7_OFFSET) + +#define STM32_DMA2_CNDTR(n) (STM32_DMA2_BASE+STM32_DMA_CNDTR_OFFSET(n)) +#define STM32_DMA2_CNDTR1 (STM32_DMA2_BASE+STM32_DMA_CNDTR1_OFFSET) +#define STM32_DMA2_CNDTR2 (STM32_DMA2_BASE+STM32_DMA_CNDTR2_OFFSET) +#define STM32_DMA2_CNDTR3 (STM32_DMA2_BASE+STM32_DMA_CNDTR3_OFFSET) +#define STM32_DMA2_CNDTR4 (STM32_DMA2_BASE+STM32_DMA_CNDTR4_OFFSET) +#define STM32_DMA2_CNDTR5 (STM32_DMA2_BASE+STM32_DMA_CNDTR5_OFFSET) +#define STM32_DMA2_CNDTR6 (STM32_DMA2_BASE+STM32_DMA_CNDTR6_OFFSET) +#define STM32_DMA2_CNDTR7 (STM32_DMA2_BASE+STM32_DMA_CNDTR7_OFFSET) + +#define STM32_DMA2_CPAR(n) (STM32_DMA2_BASE+STM32_DMA_CPAR_OFFSET(n)) +#define STM32_DMA2_CPAR1 (STM32_DMA2_BASE+STM32_DMA_CPAR1_OFFSET) +#define STM32_DMA2_CPAR2 (STM32_DMA2_BASE+STM32_DMA_CPAR2_OFFSET) +#define STM32_DMA2_CPAR3 (STM32_DMA2_BASE+STM32_DMA_CPAR3_OFFSET) +#define STM32_DMA2_CPAR4 (STM32_DMA2_BASE+STM32_DMA_CPAR4_OFFSET) +#define STM32_DMA2_CPAR5 (STM32_DMA2_BASE+STM32_DMA_CPAR5_OFFSET) +#define STM32_DMA2_CPAR6 (STM32_DMA2_BASE+STM32_DMA_CPAR6_OFFSET) +#define STM32_DMA2_CPAR7 (STM32_DMA2_BASE+STM32_DMA_CPAR7_OFFSET) + +#define STM32_DMA2_CMAR(n) (STM32_DMA2_BASE+STM32_DMA_CMAR_OFFSET(n)) +#define STM32_DMA2_CMAR1 (STM32_DMA2_BASE+STM32_DMA_CMAR1_OFFSET) +#define STM32_DMA2_CMAR2 (STM32_DMA2_BASE+STM32_DMA_CMAR2_OFFSET) +#define STM32_DMA2_CMAR3 (STM32_DMA2_BASE+STM32_DMA_CMAR3_OFFSET) +#define STM32_DMA2_CMAR4 (STM32_DMA2_BASE+STM32_DMA_CMAR4_OFFSET) +#define STM32_DMA2_CMAR5 (STM32_DMA2_BASE+STM32_DMA_CMAR5_OFFSET) +#define STM32_DMA2_CMAR6 (STM32_DMA2_BASE+STM32_DMA_CMAR6_OFFSET) +#define STM32_DMA2_CMAR7 (STM32_DMA2_BASE+STM32_DMA_CMAR7_OFFSET) /* Register Bitfield Definitions ********************************************/ @@ -277,21 +277,21 @@ * numeric suffix. Additional definitions are required in the board.h file. */ -#define STM32L4_DMA1_CHAN1 (0) -#define STM32L4_DMA1_CHAN2 (1) -#define STM32L4_DMA1_CHAN3 (2) -#define STM32L4_DMA1_CHAN4 (3) -#define STM32L4_DMA1_CHAN5 (4) -#define STM32L4_DMA1_CHAN6 (5) -#define STM32L4_DMA1_CHAN7 (6) - -#define STM32L4_DMA2_CHAN1 (7) -#define STM32L4_DMA2_CHAN2 (8) -#define STM32L4_DMA2_CHAN3 (9) -#define STM32L4_DMA2_CHAN4 (10) -#define STM32L4_DMA2_CHAN5 (11) -#define STM32L4_DMA2_CHAN6 (12) -#define STM32L4_DMA2_CHAN7 (13) +#define STM32_DMA1_CHAN1 (0) +#define STM32_DMA1_CHAN2 (1) +#define STM32_DMA1_CHAN3 (2) +#define STM32_DMA1_CHAN4 (3) +#define STM32_DMA1_CHAN5 (4) +#define STM32_DMA1_CHAN6 (5) +#define STM32_DMA1_CHAN7 (6) + +#define STM32_DMA2_CHAN1 (7) +#define STM32_DMA2_CHAN2 (8) +#define STM32_DMA2_CHAN3 (9) +#define STM32_DMA2_CHAN4 (10) +#define STM32_DMA2_CHAN5 (11) +#define STM32_DMA2_CHAN6 (12) +#define STM32_DMA2_CHAN7 (13) /* DMA Channel settings include a channel and an alternative function. * Channel is in bits 0..7 @@ -306,145 +306,145 @@ /* ADC */ -#define DMACHAN_ADC1_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN1, 0) -#define DMACHAN_ADC1_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN3, 0) +#define DMACHAN_ADC1_1 DMACHAN_SETTING(STM32_DMA1_CHAN1, 0) +#define DMACHAN_ADC1_2 DMACHAN_SETTING(STM32_DMA2_CHAN3, 0) /* AES */ -#define DMACHAN_AES_IN_1 DMACHAN_SETTING(STM32L4_DMA2_CHAN1, 6) -#define DMACHAN_AES_IN_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN5, 6) -#define DMACHAN_AES_OUT_1 DMACHAN_SETTING(STM32L4_DMA2_CHAN2, 6) -#define DMACHAN_AES_OUT_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN3, 6) +#define DMACHAN_AES_IN_1 DMACHAN_SETTING(STM32_DMA2_CHAN1, 6) +#define DMACHAN_AES_IN_2 DMACHAN_SETTING(STM32_DMA2_CHAN5, 6) +#define DMACHAN_AES_OUT_1 DMACHAN_SETTING(STM32_DMA2_CHAN2, 6) +#define DMACHAN_AES_OUT_2 DMACHAN_SETTING(STM32_DMA2_CHAN3, 6) /* DAC */ -#define DMACHAN_DAC1_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 6) -#define DMACHAN_DAC1_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN4, 3) +#define DMACHAN_DAC1_1 DMACHAN_SETTING(STM32_DMA1_CHAN3, 6) +#define DMACHAN_DAC1_2 DMACHAN_SETTING(STM32_DMA2_CHAN4, 3) -#define DMACHAN_DAC2_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN4, 5) -#define DMACHAN_DAC2_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN5, 3) +#define DMACHAN_DAC2_1 DMACHAN_SETTING(STM32_DMA1_CHAN4, 5) +#define DMACHAN_DAC2_2 DMACHAN_SETTING(STM32_DMA2_CHAN5, 3) /* DCMI */ -#define DMACHAN_DCMI_1 DMACHAN_SETTING(STM32L4_DMA2_CHAN5, 4) -#define DMACHAN_DCMI_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN6, 0) +#define DMACHAN_DCMI_1 DMACHAN_SETTING(STM32_DMA2_CHAN5, 4) +#define DMACHAN_DCMI_2 DMACHAN_SETTING(STM32_DMA2_CHAN6, 0) /* DFSDM */ -#define DMACHAN_DFSDM0 DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 0) -#define DMACHAN_DFSDM1 DMACHAN_SETTING(STM32L4_DMA1_CHAN6, 0) +#define DMACHAN_DFSDM0 DMACHAN_SETTING(STM32_DMA1_CHAN5, 0) +#define DMACHAN_DFSDM1 DMACHAN_SETTING(STM32_DMA1_CHAN6, 0) /* I2C */ -#define DMACHAN_I2C1_RX_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN7, 3) -#define DMACHAN_I2C1_RX_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN6, 5) -#define DMACHAN_I2C1_TX_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN6, 3) -#define DMACHAN_I2C1_TX_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN7, 5) +#define DMACHAN_I2C1_RX_1 DMACHAN_SETTING(STM32_DMA1_CHAN7, 3) +#define DMACHAN_I2C1_RX_2 DMACHAN_SETTING(STM32_DMA2_CHAN6, 5) +#define DMACHAN_I2C1_TX_1 DMACHAN_SETTING(STM32_DMA1_CHAN6, 3) +#define DMACHAN_I2C1_TX_2 DMACHAN_SETTING(STM32_DMA2_CHAN7, 5) -#define DMACHAN_I2C2_RX DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 3) -#define DMACHAN_I2C2_TX DMACHAN_SETTING(STM32L4_DMA1_CHAN4, 3) +#define DMACHAN_I2C2_RX DMACHAN_SETTING(STM32_DMA1_CHAN5, 3) +#define DMACHAN_I2C2_TX DMACHAN_SETTING(STM32_DMA1_CHAN4, 3) -#define DMACHAN_I2C3_RX DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 2) -#define DMACHAN_I2C3_TX DMACHAN_SETTING(STM32L4_DMA1_CHAN2, 3) +#define DMACHAN_I2C3_RX DMACHAN_SETTING(STM32_DMA1_CHAN3, 2) +#define DMACHAN_I2C3_TX DMACHAN_SETTING(STM32_DMA1_CHAN2, 3) -#define DMACHAN_I2C4_RX DMACHAN_SETTING(STM32L4_DMA2_CHAN1, 0) -#define DMACHAN_I2C4_TX DMACHAN_SETTING(STM32L4_DMA2_CHAN2, 0) +#define DMACHAN_I2C4_RX DMACHAN_SETTING(STM32_DMA2_CHAN1, 0) +#define DMACHAN_I2C4_TX DMACHAN_SETTING(STM32_DMA2_CHAN2, 0) /* QUADSPI */ -#define DMACHAN_QUADSPI_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 5) -#define DMACHAN_QUADSPI_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN7, 3) +#define DMACHAN_QUADSPI_1 DMACHAN_SETTING(STM32_DMA1_CHAN5, 5) +#define DMACHAN_QUADSPI_2 DMACHAN_SETTING(STM32_DMA2_CHAN7, 3) /* SAI */ -#define DMACHAN_SAI1_A_1 DMACHAN_SETTING(STM32L4_DMA2_CHAN1, 1) -#define DMACHAN_SAI1_A_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN6, 1) -#define DMACHAN_SAI1_B_1 DMACHAN_SETTING(STM32L4_DMA2_CHAN2, 1) -#define DMACHAN_SAI1_B_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN7, 1) +#define DMACHAN_SAI1_A_1 DMACHAN_SETTING(STM32_DMA2_CHAN1, 1) +#define DMACHAN_SAI1_A_2 DMACHAN_SETTING(STM32_DMA2_CHAN6, 1) +#define DMACHAN_SAI1_B_1 DMACHAN_SETTING(STM32_DMA2_CHAN2, 1) +#define DMACHAN_SAI1_B_2 DMACHAN_SETTING(STM32_DMA2_CHAN7, 1) -#define DMACHAN_SAI2_A_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN6, 1) -#define DMACHAN_SAI2_A_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN3, 1) -#define DMACHAN_SAI2_B_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN7, 1) -#define DMACHAN_SAI2_B_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN4, 1) +#define DMACHAN_SAI2_A_1 DMACHAN_SETTING(STM32_DMA1_CHAN6, 1) +#define DMACHAN_SAI2_A_2 DMACHAN_SETTING(STM32_DMA2_CHAN3, 1) +#define DMACHAN_SAI2_B_1 DMACHAN_SETTING(STM32_DMA1_CHAN7, 1) +#define DMACHAN_SAI2_B_2 DMACHAN_SETTING(STM32_DMA2_CHAN4, 1) /* SDMMC */ -#define DMACHAN_SDMMC_1 DMACHAN_SETTING(STM32L4_DMA2_CHAN4, 7) -#define DMACHAN_SDMMC_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN5, 7) +#define DMACHAN_SDMMC_1 DMACHAN_SETTING(STM32_DMA2_CHAN4, 7) +#define DMACHAN_SDMMC_2 DMACHAN_SETTING(STM32_DMA2_CHAN5, 7) /* SPI */ -#define DMACHAN_SPI1_RX_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN2, 1) -#define DMACHAN_SPI1_RX_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN3, 4) -#define DMACHAN_SPI1_TX_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 1) -#define DMACHAN_SPI1_TX_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN4, 4) +#define DMACHAN_SPI1_RX_1 DMACHAN_SETTING(STM32_DMA1_CHAN2, 1) +#define DMACHAN_SPI1_RX_2 DMACHAN_SETTING(STM32_DMA2_CHAN3, 4) +#define DMACHAN_SPI1_TX_1 DMACHAN_SETTING(STM32_DMA1_CHAN3, 1) +#define DMACHAN_SPI1_TX_2 DMACHAN_SETTING(STM32_DMA2_CHAN4, 4) -#define DMACHAN_SPI2_RX DMACHAN_SETTING(STM32L4_DMA1_CHAN4, 1) -#define DMACHAN_SPI2_TX DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 1) +#define DMACHAN_SPI2_RX DMACHAN_SETTING(STM32_DMA1_CHAN4, 1) +#define DMACHAN_SPI2_TX DMACHAN_SETTING(STM32_DMA1_CHAN5, 1) -#define DMACHAN_SPI3_RX DMACHAN_SETTING(STM32L4_DMA2_CHAN1, 3) -#define DMACHAN_SPI3_TX DMACHAN_SETTING(STM32L4_DMA2_CHAN2, 3) +#define DMACHAN_SPI3_RX DMACHAN_SETTING(STM32_DMA2_CHAN1, 3) +#define DMACHAN_SPI3_TX DMACHAN_SETTING(STM32_DMA2_CHAN2, 3) /* SWPMI */ -#define DMACHAN_SWPMI_RX DMACHAN_SETTING(STM32L4_DMA2_CHAN1, 4) -#define DMACHAN_SWPMI_TX DMACHAN_SETTING(STM32L4_DMA2_CHAN2, 4) +#define DMACHAN_SWPMI_RX DMACHAN_SETTING(STM32_DMA2_CHAN1, 4) +#define DMACHAN_SWPMI_TX DMACHAN_SETTING(STM32_DMA2_CHAN2, 4) /* TIM */ -#define DMACHAN_TIM1_CH1 DMACHAN_SETTING(STM32L4_DMA1_CHAN2, 7) -#define DMACHAN_TIM1_CH2 DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 7) -#define DMACHAN_TIM1_CH3 DMACHAN_SETTING(STM32L4_DMA1_CHAN7, 7) -#define DMACHAN_TIM1_CH4 DMACHAN_SETTING(STM32L4_DMA1_CHAN4, 7) -#define DMACHAN_TIM1_COM DMACHAN_SETTING(STM32L4_DMA1_CHAN4, 7) -#define DMACHAN_TIM1_TRIG DMACHAN_SETTING(STM32L4_DMA1_CHAN4, 7) -#define DMACHAN_TIM1_UP DMACHAN_SETTING(STM32L4_DMA1_CHAN6, 7) - -#define DMACHAN_TIM2_CH1 DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 4) -#define DMACHAN_TIM2_CH2 DMACHAN_SETTING(STM32L4_DMA1_CHAN7, 4) -#define DMACHAN_TIM2_CH3 DMACHAN_SETTING(STM32L4_DMA1_CHAN1, 4) -#define DMACHAN_TIM2_CH4 DMACHAN_SETTING(STM32L4_DMA1_CHAN7, 4) -#define DMACHAN_TIM2_UP DMACHAN_SETTING(STM32L4_DMA1_CHAN2, 4) - -#define DMACHAN_TIM3_CH1 DMACHAN_SETTING(STM32L4_DMA1_CHAN6, 5) -#define DMACHAN_TIM3_CH3 DMACHAN_SETTING(STM32L4_DMA1_CHAN2, 5) -#define DMACHAN_TIM3_CH4 DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 5) -#define DMACHAN_TIM3_TRIG DMACHAN_SETTING(STM32L4_DMA1_CHAN6, 5) -#define DMACHAN_TIM3_UP DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 5) - -#define DMACHAN_TIM6_UP_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 6) -#define DMACHAN_TIM6_UP_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN4, 3) - -#define DMACHAN_TIM7_UP_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN4, 5) -#define DMACHAN_TIM7_UP_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN5, 3) - -#define DMACHAN_TIM15_CH1 DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 7) -#define DMACHAN_TIM15_COM DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 7) -#define DMACHAN_TIM15_TRIG DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 7) -#define DMACHAN_TIM15_UP DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 7) - -#define DMACHAN_TIM16_CH1_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 4) -#define DMACHAN_TIM16_CH1_2 DMACHAN_SETTING(STM32L4_DMA1_CHAN6, 4) -#define DMACHAN_TIM16_UP_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 4) -#define DMACHAN_TIM16_UP_2 DMACHAN_SETTING(STM32L4_DMA1_CHAN6, 4) +#define DMACHAN_TIM1_CH1 DMACHAN_SETTING(STM32_DMA1_CHAN2, 7) +#define DMACHAN_TIM1_CH2 DMACHAN_SETTING(STM32_DMA1_CHAN3, 7) +#define DMACHAN_TIM1_CH3 DMACHAN_SETTING(STM32_DMA1_CHAN7, 7) +#define DMACHAN_TIM1_CH4 DMACHAN_SETTING(STM32_DMA1_CHAN4, 7) +#define DMACHAN_TIM1_COM DMACHAN_SETTING(STM32_DMA1_CHAN4, 7) +#define DMACHAN_TIM1_TRIG DMACHAN_SETTING(STM32_DMA1_CHAN4, 7) +#define DMACHAN_TIM1_UP DMACHAN_SETTING(STM32_DMA1_CHAN6, 7) + +#define DMACHAN_TIM2_CH1 DMACHAN_SETTING(STM32_DMA1_CHAN5, 4) +#define DMACHAN_TIM2_CH2 DMACHAN_SETTING(STM32_DMA1_CHAN7, 4) +#define DMACHAN_TIM2_CH3 DMACHAN_SETTING(STM32_DMA1_CHAN1, 4) +#define DMACHAN_TIM2_CH4 DMACHAN_SETTING(STM32_DMA1_CHAN7, 4) +#define DMACHAN_TIM2_UP DMACHAN_SETTING(STM32_DMA1_CHAN2, 4) + +#define DMACHAN_TIM3_CH1 DMACHAN_SETTING(STM32_DMA1_CHAN6, 5) +#define DMACHAN_TIM3_CH3 DMACHAN_SETTING(STM32_DMA1_CHAN2, 5) +#define DMACHAN_TIM3_CH4 DMACHAN_SETTING(STM32_DMA1_CHAN3, 5) +#define DMACHAN_TIM3_TRIG DMACHAN_SETTING(STM32_DMA1_CHAN6, 5) +#define DMACHAN_TIM3_UP DMACHAN_SETTING(STM32_DMA1_CHAN3, 5) + +#define DMACHAN_TIM6_UP_1 DMACHAN_SETTING(STM32_DMA1_CHAN3, 6) +#define DMACHAN_TIM6_UP_2 DMACHAN_SETTING(STM32_DMA2_CHAN4, 3) + +#define DMACHAN_TIM7_UP_1 DMACHAN_SETTING(STM32_DMA1_CHAN4, 5) +#define DMACHAN_TIM7_UP_2 DMACHAN_SETTING(STM32_DMA2_CHAN5, 3) + +#define DMACHAN_TIM15_CH1 DMACHAN_SETTING(STM32_DMA1_CHAN5, 7) +#define DMACHAN_TIM15_COM DMACHAN_SETTING(STM32_DMA1_CHAN5, 7) +#define DMACHAN_TIM15_TRIG DMACHAN_SETTING(STM32_DMA1_CHAN5, 7) +#define DMACHAN_TIM15_UP DMACHAN_SETTING(STM32_DMA1_CHAN5, 7) + +#define DMACHAN_TIM16_CH1_1 DMACHAN_SETTING(STM32_DMA1_CHAN3, 4) +#define DMACHAN_TIM16_CH1_2 DMACHAN_SETTING(STM32_DMA1_CHAN6, 4) +#define DMACHAN_TIM16_UP_1 DMACHAN_SETTING(STM32_DMA1_CHAN3, 4) +#define DMACHAN_TIM16_UP_2 DMACHAN_SETTING(STM32_DMA1_CHAN6, 4) /* UART */ -#define DMACHAN_USART1_RX_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 2) -#define DMACHAN_USART1_RX_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN7, 2) -#define DMACHAN_USART1_TX_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN4, 2) -#define DMACHAN_USART1_TX_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN6, 2) +#define DMACHAN_USART1_RX_1 DMACHAN_SETTING(STM32_DMA1_CHAN5, 2) +#define DMACHAN_USART1_RX_2 DMACHAN_SETTING(STM32_DMA2_CHAN7, 2) +#define DMACHAN_USART1_TX_1 DMACHAN_SETTING(STM32_DMA1_CHAN4, 2) +#define DMACHAN_USART1_TX_2 DMACHAN_SETTING(STM32_DMA2_CHAN6, 2) -#define DMACHAN_USART2_RX DMACHAN_SETTING(STM32L4_DMA1_CHAN6, 2) -#define DMACHAN_USART2_TX DMACHAN_SETTING(STM32L4_DMA1_CHAN7, 2) +#define DMACHAN_USART2_RX DMACHAN_SETTING(STM32_DMA1_CHAN6, 2) +#define DMACHAN_USART2_TX DMACHAN_SETTING(STM32_DMA1_CHAN7, 2) -#define DMACHAN_USART3_RX DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 2) -#define DMACHAN_USART3_TX DMACHAN_SETTING(STM32L4_DMA1_CHAN2, 2) +#define DMACHAN_USART3_RX DMACHAN_SETTING(STM32_DMA1_CHAN3, 2) +#define DMACHAN_USART3_TX DMACHAN_SETTING(STM32_DMA1_CHAN2, 2) -#define DMACHAN_UART4_RX DMACHAN_SETTING(STM32L4_DMA2_CHAN5, 2) -#define DMACHAN_UART4_TX DMACHAN_SETTING(STM32L4_DMA2_CHAN3, 2) +#define DMACHAN_UART4_RX DMACHAN_SETTING(STM32_DMA2_CHAN5, 2) +#define DMACHAN_UART4_TX DMACHAN_SETTING(STM32_DMA2_CHAN3, 2) -#define DMACHAN_LPUART_RX DMACHAN_SETTING(STM32L4_DMA2_CHAN7, 4) -#define DMACHAN_LPUART_TX DMACHAN_SETTING(STM32L4_DMA2_CHAN6, 4) +#define DMACHAN_LPUART_RX DMACHAN_SETTING(STM32_DMA2_CHAN7, 4) +#define DMACHAN_LPUART_TX DMACHAN_SETTING(STM32_DMA2_CHAN6, 4) #endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4X3XX_DMA_H */ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4x3xx_firewall.h b/arch/arm/src/stm32l4/hardware/stm32l4x3xx_firewall.h index 153953e705af3..7aa56323221ea 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4x3xx_firewall.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4x3xx_firewall.h @@ -38,23 +38,23 @@ /* Register Offsets *********************************************************/ -#define STM32L4_FIREWALL_CSSA_OFFSET 0x0000 -#define STM32L4_FIREWALL_CSL_OFFSET 0x0004 -#define STM32L4_FIREWALL_NVDSSA_OFFSET 0x0008 -#define STM32L4_FIREWALL_NVDSL_OFFSET 0x000c -#define STM32L4_FIREWALL_VDSSA_OFFSET 0x0010 -#define STM32L4_FIREWALL_VDSL_OFFSET 0x0014 -#define STM32L4_FIREWALL_CR_OFFSET 0x0020 +#define STM32_FIREWALL_CSSA_OFFSET 0x0000 +#define STM32_FIREWALL_CSL_OFFSET 0x0004 +#define STM32_FIREWALL_NVDSSA_OFFSET 0x0008 +#define STM32_FIREWALL_NVDSL_OFFSET 0x000c +#define STM32_FIREWALL_VDSSA_OFFSET 0x0010 +#define STM32_FIREWALL_VDSL_OFFSET 0x0014 +#define STM32_FIREWALL_CR_OFFSET 0x0020 /* Register Addresses *******************************************************/ -#define STM32L4_FIREWALL_CSSA (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_CSSA_OFFSET) -#define STM32L4_FIREWALL_CSL (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_CSL_OFFSET) -#define STM32L4_FIREWALL_NVDSSA (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_NVDSSA_OFFSET) -#define STM32L4_FIREWALL_NVDSL (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_NVDSL_OFFSET) -#define STM32L4_FIREWALL_VDSSA (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_VDSSA_OFFSET) -#define STM32L4_FIREWALL_VDSL (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_VDSL_OFFSET) -#define STM32L4_FIREWALL_CR (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_CR_OFFSET) +#define STM32_FIREWALL_CSSA (STM32_FIREWALL_BASE+STM32_FIREWALL_CSSA_OFFSET) +#define STM32_FIREWALL_CSL (STM32_FIREWALL_BASE+STM32_FIREWALL_CSL_OFFSET) +#define STM32_FIREWALL_NVDSSA (STM32_FIREWALL_BASE+STM32_FIREWALL_NVDSSA_OFFSET) +#define STM32_FIREWALL_NVDSL (STM32_FIREWALL_BASE+STM32_FIREWALL_NVDSL_OFFSET) +#define STM32_FIREWALL_VDSSA (STM32_FIREWALL_BASE+STM32_FIREWALL_VDSSA_OFFSET) +#define STM32_FIREWALL_VDSL (STM32_FIREWALL_BASE+STM32_FIREWALL_VDSL_OFFSET) +#define STM32_FIREWALL_CR (STM32_FIREWALL_BASE+STM32_FIREWALL_CR_OFFSET) /* Register Bitfield Definitions ********************************************/ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4x3xx_rcc.h b/arch/arm/src/stm32l4/hardware/stm32l4x3xx_rcc.h index 73fcb283519c8..38db3afd93887 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4x3xx_rcc.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4x3xx_rcc.h @@ -29,7 +29,7 @@ #include -#if defined(CONFIG_STM32L4_STM32L4X3) +#if defined(CONFIG_STM32_STM32L4X3) /**************************************************************************** * Pre-processor Definitions @@ -37,73 +37,73 @@ /* Register Offsets *********************************************************/ -#define STM32L4_RCC_CR_OFFSET 0x0000 /* Clock control register */ -#define STM32L4_RCC_ICSCR_OFFSET 0x0004 /* Internal clock sources calibration register */ -#define STM32L4_RCC_CFGR_OFFSET 0x0008 /* Clock configuration register */ -#define STM32L4_RCC_PLLCFG_OFFSET 0x000c /* PLL configuration register */ -#define STM32L4_RCC_PLLSAI1CFG_OFFSET 0x0010 /* PLLSAI1 configuration register */ -#define STM32L4_RCC_PLLSAI2CFG_OFFSET 0x0014 /* PLLSAI2 configuration register */ -#define STM32L4_RCC_CIER_OFFSET 0x0018 /* Clock interrupt enable register */ -#define STM32L4_RCC_CIFR_OFFSET 0x001c /* Clock interrupt flag register */ -#define STM32L4_RCC_CICR_OFFSET 0x0020 /* Clock interrupt clear register */ -#define STM32L4_RCC_AHB1RSTR_OFFSET 0x0028 /* AHB1 peripheral reset register */ -#define STM32L4_RCC_AHB2RSTR_OFFSET 0x002c /* AHB2 peripheral reset register */ -#define STM32L4_RCC_AHB3RSTR_OFFSET 0x0030 /* AHB3 peripheral reset register */ -#define STM32L4_RCC_APB1RSTR1_OFFSET 0x0038 /* APB1 Peripheral reset register 1 */ -#define STM32L4_RCC_APB1RSTR2_OFFSET 0x003c /* APB1 Peripheral reset register 2 */ -#define STM32L4_RCC_APB2RSTR_OFFSET 0x0040 /* APB2 Peripheral reset register */ -#define STM32L4_RCC_AHB1ENR_OFFSET 0x0048 /* AHB1 Peripheral Clock enable register */ -#define STM32L4_RCC_AHB2ENR_OFFSET 0x004c /* AHB2 Peripheral Clock enable register */ -#define STM32L4_RCC_AHB3ENR_OFFSET 0x0050 /* AHB3 Peripheral Clock enable register */ -#define STM32L4_RCC_APB1ENR1_OFFSET 0x0058 /* APB1 Peripheral Clock enable register 1 */ -#define STM32L4_RCC_APB1ENR2_OFFSET 0x005c /* APB1 Peripheral Clock enable register 2 */ -#define STM32L4_RCC_APB2ENR_OFFSET 0x0060 /* APB2 Peripheral Clock enable register */ -#define STM32L4_RCC_AHB1SMENR_OFFSET 0x0068 /* RCC AHB1 low power mode peripheral clock enable register */ -#define STM32L4_RCC_AHB2SMENR_OFFSET 0x006c /* RCC AHB2 low power mode peripheral clock enable register */ -#define STM32L4_RCC_AHB3SMENR_OFFSET 0x0070 /* RCC AHB3 low power mode peripheral clock enable register */ -#define STM32L4_RCC_APB1SMENR1_OFFSET 0x0078 /* RCC APB1 low power mode peripheral clock enable register 1 */ -#define STM32L4_RCC_APB1SMENR2_OFFSET 0x007c /* RCC APB1 low power mode peripheral clock enable register 2 */ -#define STM32L4_RCC_APB2SMENR_OFFSET 0x0080 /* RCC APB2 low power mode peripheral clock enable register */ -#define STM32L4_RCC_CCIPR_OFFSET 0x0088 /* Peripherals independent clock configuration register 1 */ -#define STM32L4_RCC_BDCR_OFFSET 0x0090 /* Backup domain control register */ -#define STM32L4_RCC_CSR_OFFSET 0x0094 /* Control/status register */ -#define STM32L4_RCC_CRRCR_OFFSET 0x0098 /* Clock recovery RC register */ -#define STM32L4_RCC_CCIPR2_OFFSET 0x009c /* Peripherals independent clock configuration register 2 */ +#define STM32_RCC_CR_OFFSET 0x0000 /* Clock control register */ +#define STM32_RCC_ICSCR_OFFSET 0x0004 /* Internal clock sources calibration register */ +#define STM32_RCC_CFGR_OFFSET 0x0008 /* Clock configuration register */ +#define STM32_RCC_PLLCFG_OFFSET 0x000c /* PLL configuration register */ +#define STM32_RCC_PLLSAI1CFG_OFFSET 0x0010 /* PLLSAI1 configuration register */ +#define STM32_RCC_PLLSAI2CFG_OFFSET 0x0014 /* PLLSAI2 configuration register */ +#define STM32_RCC_CIER_OFFSET 0x0018 /* Clock interrupt enable register */ +#define STM32_RCC_CIFR_OFFSET 0x001c /* Clock interrupt flag register */ +#define STM32_RCC_CICR_OFFSET 0x0020 /* Clock interrupt clear register */ +#define STM32_RCC_AHB1RSTR_OFFSET 0x0028 /* AHB1 peripheral reset register */ +#define STM32_RCC_AHB2RSTR_OFFSET 0x002c /* AHB2 peripheral reset register */ +#define STM32_RCC_AHB3RSTR_OFFSET 0x0030 /* AHB3 peripheral reset register */ +#define STM32_RCC_APB1RSTR1_OFFSET 0x0038 /* APB1 Peripheral reset register 1 */ +#define STM32_RCC_APB1RSTR2_OFFSET 0x003c /* APB1 Peripheral reset register 2 */ +#define STM32_RCC_APB2RSTR_OFFSET 0x0040 /* APB2 Peripheral reset register */ +#define STM32_RCC_AHB1ENR_OFFSET 0x0048 /* AHB1 Peripheral Clock enable register */ +#define STM32_RCC_AHB2ENR_OFFSET 0x004c /* AHB2 Peripheral Clock enable register */ +#define STM32_RCC_AHB3ENR_OFFSET 0x0050 /* AHB3 Peripheral Clock enable register */ +#define STM32_RCC_APB1ENR1_OFFSET 0x0058 /* APB1 Peripheral Clock enable register 1 */ +#define STM32_RCC_APB1ENR2_OFFSET 0x005c /* APB1 Peripheral Clock enable register 2 */ +#define STM32_RCC_APB2ENR_OFFSET 0x0060 /* APB2 Peripheral Clock enable register */ +#define STM32_RCC_AHB1SMENR_OFFSET 0x0068 /* RCC AHB1 low power mode peripheral clock enable register */ +#define STM32_RCC_AHB2SMENR_OFFSET 0x006c /* RCC AHB2 low power mode peripheral clock enable register */ +#define STM32_RCC_AHB3SMENR_OFFSET 0x0070 /* RCC AHB3 low power mode peripheral clock enable register */ +#define STM32_RCC_APB1SMENR1_OFFSET 0x0078 /* RCC APB1 low power mode peripheral clock enable register 1 */ +#define STM32_RCC_APB1SMENR2_OFFSET 0x007c /* RCC APB1 low power mode peripheral clock enable register 2 */ +#define STM32_RCC_APB2SMENR_OFFSET 0x0080 /* RCC APB2 low power mode peripheral clock enable register */ +#define STM32_RCC_CCIPR_OFFSET 0x0088 /* Peripherals independent clock configuration register 1 */ +#define STM32_RCC_BDCR_OFFSET 0x0090 /* Backup domain control register */ +#define STM32_RCC_CSR_OFFSET 0x0094 /* Control/status register */ +#define STM32_RCC_CRRCR_OFFSET 0x0098 /* Clock recovery RC register */ +#define STM32_RCC_CCIPR2_OFFSET 0x009c /* Peripherals independent clock configuration register 2 */ /* Register Addresses *******************************************************/ -#define STM32L4_RCC_CR (STM32L4_RCC_BASE+STM32L4_RCC_CR_OFFSET) -#define STM32L4_RCC_ICSCR (STM32L4_RCC_BASE+STM32L4_RCC_ICSCR_OFFSET) -#define STM32L4_RCC_CFGR (STM32L4_RCC_BASE+STM32L4_RCC_CFGR_OFFSET) -#define STM32L4_RCC_PLLCFG (STM32L4_RCC_BASE+STM32L4_RCC_PLLCFG_OFFSET) -#define STM32L4_RCC_PLLSAI1CFG (STM32L4_RCC_BASE+STM32L4_RCC_PLLSAI1CFG_OFFSET) -#define STM32L4_RCC_PLLSAI2CFG (STM32L4_RCC_BASE+STM32L4_RCC_PLLSAI2CFG_OFFSET) -#define STM32L4_RCC_CIER (STM32L4_RCC_BASE+STM32L4_RCC_CIER_OFFSET) -#define STM32L4_RCC_CIFR (STM32L4_RCC_BASE+STM32L4_RCC_CIFR_OFFSET) -#define STM32L4_RCC_CICR (STM32L4_RCC_BASE+STM32L4_RCC_CICR_OFFSET) -#define STM32L4_RCC_AHB1RSTR (STM32L4_RCC_BASE+STM32L4_RCC_AHB1RSTR_OFFSET) -#define STM32L4_RCC_AHB2RSTR (STM32L4_RCC_BASE+STM32L4_RCC_AHB2RSTR_OFFSET) -#define STM32L4_RCC_AHB3RSTR (STM32L4_RCC_BASE+STM32L4_RCC_AHB3RSTR_OFFSET) -#define STM32L4_RCC_APB1RSTR1 (STM32L4_RCC_BASE+STM32L4_RCC_APB1RSTR1_OFFSET) -#define STM32L4_RCC_APB1RSTR2 (STM32L4_RCC_BASE+STM32L4_RCC_APB1RSTR2_OFFSET) -#define STM32L4_RCC_APB2RSTR (STM32L4_RCC_BASE+STM32L4_RCC_APB2RSTR_OFFSET) -#define STM32L4_RCC_AHB1ENR (STM32L4_RCC_BASE+STM32L4_RCC_AHB1ENR_OFFSET) -#define STM32L4_RCC_AHB2ENR (STM32L4_RCC_BASE+STM32L4_RCC_AHB2ENR_OFFSET) -#define STM32L4_RCC_AHB3ENR (STM32L4_RCC_BASE+STM32L4_RCC_AHB3ENR_OFFSET) -#define STM32L4_RCC_APB1ENR1 (STM32L4_RCC_BASE+STM32L4_RCC_APB1ENR1_OFFSET) -#define STM32L4_RCC_APB1ENR2 (STM32L4_RCC_BASE+STM32L4_RCC_APB1ENR2_OFFSET) -#define STM32L4_RCC_APB2ENR (STM32L4_RCC_BASE+STM32L4_RCC_APB2ENR_OFFSET) -#define STM32L4_RCC_AHB1SMENR (STM32L4_RCC_BASE+STM32L4_RCC_AHB1SMENR_OFFSET) -#define STM32L4_RCC_AHB2SMENR (STM32L4_RCC_BASE+STM32L4_RCC_AHB2SMENR_OFFSET) -#define STM32L4_RCC_AHB3SMENR (STM32L4_RCC_BASE+STM32L4_RCC_AHB3SMENR_OFFSET) -#define STM32L4_RCC_APB1SMENR1 (STM32L4_RCC_BASE+STM32L4_RCC_APB1SMENR1_OFFSET) -#define STM32L4_RCC_APB1SMENR2 (STM32L4_RCC_BASE+STM32L4_RCC_APB1SMENR2_OFFSET) -#define STM32L4_RCC_APB2SMENR (STM32L4_RCC_BASE+STM32L4_RCC_APB2SMENR_OFFSET) -#define STM32L4_RCC_CCIPR (STM32L4_RCC_BASE+STM32L4_RCC_CCIPR_OFFSET) -#define STM32L4_RCC_BDCR (STM32L4_RCC_BASE+STM32L4_RCC_BDCR_OFFSET) -#define STM32L4_RCC_CSR (STM32L4_RCC_BASE+STM32L4_RCC_CSR_OFFSET) -#define STM32L4_RCC_CRRCR (STM32L4_RCC_BASE+STM32L4_RCC_CRRCR_OFFSET) -#define STM32L4_RCC_CCIPR2 (STM32L4_RCC_BASE+STM32L4_RCC_CCIPR2_OFFSET) +#define STM32_RCC_CR (STM32_RCC_BASE+STM32_RCC_CR_OFFSET) +#define STM32_RCC_ICSCR (STM32_RCC_BASE+STM32_RCC_ICSCR_OFFSET) +#define STM32_RCC_CFGR (STM32_RCC_BASE+STM32_RCC_CFGR_OFFSET) +#define STM32_RCC_PLLCFG (STM32_RCC_BASE+STM32_RCC_PLLCFG_OFFSET) +#define STM32_RCC_PLLSAI1CFG (STM32_RCC_BASE+STM32_RCC_PLLSAI1CFG_OFFSET) +#define STM32_RCC_PLLSAI2CFG (STM32_RCC_BASE+STM32_RCC_PLLSAI2CFG_OFFSET) +#define STM32_RCC_CIER (STM32_RCC_BASE+STM32_RCC_CIER_OFFSET) +#define STM32_RCC_CIFR (STM32_RCC_BASE+STM32_RCC_CIFR_OFFSET) +#define STM32_RCC_CICR (STM32_RCC_BASE+STM32_RCC_CICR_OFFSET) +#define STM32_RCC_AHB1RSTR (STM32_RCC_BASE+STM32_RCC_AHB1RSTR_OFFSET) +#define STM32_RCC_AHB2RSTR (STM32_RCC_BASE+STM32_RCC_AHB2RSTR_OFFSET) +#define STM32_RCC_AHB3RSTR (STM32_RCC_BASE+STM32_RCC_AHB3RSTR_OFFSET) +#define STM32_RCC_APB1RSTR1 (STM32_RCC_BASE+STM32_RCC_APB1RSTR1_OFFSET) +#define STM32_RCC_APB1RSTR2 (STM32_RCC_BASE+STM32_RCC_APB1RSTR2_OFFSET) +#define STM32_RCC_APB2RSTR (STM32_RCC_BASE+STM32_RCC_APB2RSTR_OFFSET) +#define STM32_RCC_AHB1ENR (STM32_RCC_BASE+STM32_RCC_AHB1ENR_OFFSET) +#define STM32_RCC_AHB2ENR (STM32_RCC_BASE+STM32_RCC_AHB2ENR_OFFSET) +#define STM32_RCC_AHB3ENR (STM32_RCC_BASE+STM32_RCC_AHB3ENR_OFFSET) +#define STM32_RCC_APB1ENR1 (STM32_RCC_BASE+STM32_RCC_APB1ENR1_OFFSET) +#define STM32_RCC_APB1ENR2 (STM32_RCC_BASE+STM32_RCC_APB1ENR2_OFFSET) +#define STM32_RCC_APB2ENR (STM32_RCC_BASE+STM32_RCC_APB2ENR_OFFSET) +#define STM32_RCC_AHB1SMENR (STM32_RCC_BASE+STM32_RCC_AHB1SMENR_OFFSET) +#define STM32_RCC_AHB2SMENR (STM32_RCC_BASE+STM32_RCC_AHB2SMENR_OFFSET) +#define STM32_RCC_AHB3SMENR (STM32_RCC_BASE+STM32_RCC_AHB3SMENR_OFFSET) +#define STM32_RCC_APB1SMENR1 (STM32_RCC_BASE+STM32_RCC_APB1SMENR1_OFFSET) +#define STM32_RCC_APB1SMENR2 (STM32_RCC_BASE+STM32_RCC_APB1SMENR2_OFFSET) +#define STM32_RCC_APB2SMENR (STM32_RCC_BASE+STM32_RCC_APB2SMENR_OFFSET) +#define STM32_RCC_CCIPR (STM32_RCC_BASE+STM32_RCC_CCIPR_OFFSET) +#define STM32_RCC_BDCR (STM32_RCC_BASE+STM32_RCC_BDCR_OFFSET) +#define STM32_RCC_CSR (STM32_RCC_BASE+STM32_RCC_CSR_OFFSET) +#define STM32_RCC_CRRCR (STM32_RCC_BASE+STM32_RCC_CRRCR_OFFSET) +#define STM32_RCC_CCIPR2 (STM32_RCC_BASE+STM32_RCC_CCIPR2_OFFSET) /* Register Bitfield Definitions ********************************************/ @@ -791,5 +791,5 @@ # define RCC_CCIPR2_I2C4SEL_SYSCLK (1 << RCC_CCIPR2_I2C4SEL_SHIFT) # define RCC_CCIPR2_I2C4SEL_HSI (2 << RCC_CCIPR2_I2C4SEL_SHIFT) -#endif /* CONFIG_STM32L4_STM32L4X3 */ +#endif /* CONFIG_STM32_STM32L4X3 */ #endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4X3XX_RCC_H */ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4x3xx_syscfg.h b/arch/arm/src/stm32l4/hardware/stm32l4x3xx_syscfg.h index 968eddee74915..17502c2562f14 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4x3xx_syscfg.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4x3xx_syscfg.h @@ -30,7 +30,7 @@ #include #include "chip.h" -#if defined(CONFIG_STM32L4_STM32L4X3) +#if defined(CONFIG_STM32_STM32L4X3) /**************************************************************************** * Pre-processor Definitions @@ -38,33 +38,33 @@ /* Register Offsets *********************************************************/ -#define STM32L4_SYSCFG_MEMRMP_OFFSET 0x0000 /* SYSCFG memory remap register */ -#define STM32L4_SYSCFG_CFGR1_OFFSET 0x0004 /* SYSCFG configuration register 1 */ +#define STM32_SYSCFG_MEMRMP_OFFSET 0x0000 /* SYSCFG memory remap register */ +#define STM32_SYSCFG_CFGR1_OFFSET 0x0004 /* SYSCFG configuration register 1 */ -#define STM32L4_SYSCFG_EXTICR_OFFSET(p) (0x0008 + ((p) & 0x000c)) /* Registers are displaced by 4! */ +#define STM32_SYSCFG_EXTICR_OFFSET(p) (0x0008 + ((p) & 0x000c)) /* Registers are displaced by 4! */ -#define STM32L4_SYSCFG_EXTICR1_OFFSET 0x0008 /* SYSCFG external interrupt configuration register 1 */ -#define STM32L4_SYSCFG_EXTICR2_OFFSET 0x000c /* SYSCFG external interrupt configuration register 2 */ -#define STM32L4_SYSCFG_EXTICR3_OFFSET 0x0010 /* SYSCFG external interrupt configuration register 3 */ -#define STM32L4_SYSCFG_EXTICR4_OFFSET 0x0014 /* SYSCFG external interrupt configuration register 4 */ -#define STM32L4_SYSCFG_SCSR_OFFSET 0x0018 /* SYSCFG SRAM2 control and status register */ -#define STM32L4_SYSCFG_CFGR2_OFFSET 0x001c /* SYSCFG configuration register 2 */ -#define STM32L4_SYSCFG_SWPR_OFFSET 0x0020 /* SYSCFG SRAM2 write protection register */ -#define STM32L4_SYSCFG_SKR_OFFSET 0x0024 /* SYSCFG SRAM2 key register */ +#define STM32_SYSCFG_EXTICR1_OFFSET 0x0008 /* SYSCFG external interrupt configuration register 1 */ +#define STM32_SYSCFG_EXTICR2_OFFSET 0x000c /* SYSCFG external interrupt configuration register 2 */ +#define STM32_SYSCFG_EXTICR3_OFFSET 0x0010 /* SYSCFG external interrupt configuration register 3 */ +#define STM32_SYSCFG_EXTICR4_OFFSET 0x0014 /* SYSCFG external interrupt configuration register 4 */ +#define STM32_SYSCFG_SCSR_OFFSET 0x0018 /* SYSCFG SRAM2 control and status register */ +#define STM32_SYSCFG_CFGR2_OFFSET 0x001c /* SYSCFG configuration register 2 */ +#define STM32_SYSCFG_SWPR_OFFSET 0x0020 /* SYSCFG SRAM2 write protection register */ +#define STM32_SYSCFG_SKR_OFFSET 0x0024 /* SYSCFG SRAM2 key register */ /* Register Addresses *******************************************************/ -#define STM32L4_SYSCFG_MEMRMP (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_MEMRMP_OFFSET) -#define STM32L4_SYSCFG_CFGR1 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_CFGR1_OFFSET) -#define STM32L4_SYSCFG_EXTICR(p) (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_EXTICR_OFFSET(p)) -#define STM32L4_SYSCFG_EXTICR1 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_EXTICR1_OFFSET) -#define STM32L4_SYSCFG_EXTICR2 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_EXTICR2_OFFSET) -#define STM32L4_SYSCFG_EXTICR3 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_EXTICR3_OFFSET) -#define STM32L4_SYSCFG_EXTICR4 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_EXTICR4_OFFSET) -#define STM32L4_SYSCFG_SCSR (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_SCSR_OFFSET) -#define STM32L4_SYSCFG_CFGR2 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_CFGR2_OFFSET) -#define STM32L4_SYSCFG_SWPR (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_SWPR_OFFSET) -#define STM32L4_SYSCFG_SKR (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_SKR_OFFSET) +#define STM32_SYSCFG_MEMRMP (STM32_SYSCFG_BASE+STM32_SYSCFG_MEMRMP_OFFSET) +#define STM32_SYSCFG_CFGR1 (STM32_SYSCFG_BASE+STM32_SYSCFG_CFGR1_OFFSET) +#define STM32_SYSCFG_EXTICR(p) (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR_OFFSET(p)) +#define STM32_SYSCFG_EXTICR1 (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR1_OFFSET) +#define STM32_SYSCFG_EXTICR2 (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR2_OFFSET) +#define STM32_SYSCFG_EXTICR3 (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR3_OFFSET) +#define STM32_SYSCFG_EXTICR4 (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR4_OFFSET) +#define STM32_SYSCFG_SCSR (STM32_SYSCFG_BASE+STM32_SYSCFG_SCSR_OFFSET) +#define STM32_SYSCFG_CFGR2 (STM32_SYSCFG_BASE+STM32_SYSCFG_CFGR2_OFFSET) +#define STM32_SYSCFG_SWPR (STM32_SYSCFG_BASE+STM32_SYSCFG_SWPR_OFFSET) +#define STM32_SYSCFG_SKR (STM32_SYSCFG_BASE+STM32_SYSCFG_SKR_OFFSET) /* Register Bitfield Definitions ********************************************/ @@ -169,5 +169,5 @@ #define SYSCFG_SKR_SHIFT 0 #define SYSCFG_SKR_MASK (0xFF << SYSCFG_SKR_SHIFT) -#endif /* CONFIG_STM32L4_STM32L4X3 */ +#endif /* CONFIG_STM32_STM32L4X3 */ #endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4X3XX_SYSCFG_H */ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4x5xx_dma.h b/arch/arm/src/stm32l4/hardware/stm32l4x5xx_dma.h index b56cb00fc7035..0ff70f0abf297 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4x5xx_dma.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4x5xx_dma.h @@ -34,141 +34,141 @@ /* Register Offsets *********************************************************/ -#define STM32L4_DMA_ISR_OFFSET 0x0000 /* DMA interrupt status register */ -#define STM32L4_DMA_IFCR_OFFSET 0x0004 /* DMA interrupt flag clear register */ - -#define STM32L4_DMACHAN_OFFSET(n) (0x0014*(n)) -#define STM32L4_DMACHAN1_OFFSET 0x0000 -#define STM32L4_DMACHAN2_OFFSET 0x0014 -#define STM32L4_DMACHAN3_OFFSET 0x0028 -#define STM32L4_DMACHAN4_OFFSET 0x003c -#define STM32L4_DMACHAN5_OFFSET 0x0050 -#define STM32L4_DMACHAN6_OFFSET 0x0064 -#define STM32L4_DMACHAN7_OFFSET 0x0078 - -#define STM32L4_DMACHAN_CCR_OFFSET 0x0008 /* DMA channel configuration register */ -#define STM32L4_DMACHAN_CNDTR_OFFSET 0x000c /* DMA channel number of data register */ -#define STM32L4_DMACHAN_CPAR_OFFSET 0x0010 /* DMA channel peripheral address register */ -#define STM32L4_DMACHAN_CMAR_OFFSET 0x0014 /* DMA channel memory address register */ - -#define STM32L4_DMA_CCR_OFFSET(n) (STM32L4_DMACHAN_CCR_OFFSET+STM32L4_DMACHAN_OFFSET(n)) -#define STM32L4_DMA_CNDTR_OFFSET(n) (STM32L4_DMACHAN_CNDTR_OFFSET+STM32L4_DMACHAN_OFFSET(n)) -#define STM32L4_DMA_CPAR_OFFSET(n) (STM32L4_DMACHAN_CPAR_OFFSET+STM32L4_DMACHAN_OFFSET(n)) -#define STM32L4_DMA_CMAR_OFFSET(n) (STM32L4_DMACHAN_CMAR_OFFSET+STM32L4_DMACHAN_OFFSET(n)) - -#define STM32L4_DMA_CCR1_OFFSET 0x0008 /* DMA channel 1 configuration register */ -#define STM32L4_DMA_CCR2_OFFSET 0x001c /* DMA channel 2 configuration register */ -#define STM32L4_DMA_CCR3_OFFSET 0x0030 /* DMA channel 3 configuration register */ -#define STM32L4_DMA_CCR4_OFFSET 0x0044 /* DMA channel 4 configuration register */ -#define STM32L4_DMA_CCR5_OFFSET 0x0058 /* DMA channel 5 configuration register */ -#define STM32L4_DMA_CCR6_OFFSET 0x006c /* DMA channel 6 configuration register */ -#define STM32L4_DMA_CCR7_OFFSET 0x0080 /* DMA channel 7 configuration register */ - -#define STM32L4_DMA_CNDTR1_OFFSET 0x000c /* DMA channel 1 number of data register */ -#define STM32L4_DMA_CNDTR2_OFFSET 0x0020 /* DMA channel 2 number of data register */ -#define STM32L4_DMA_CNDTR3_OFFSET 0x0034 /* DMA channel 3 number of data register */ -#define STM32L4_DMA_CNDTR4_OFFSET 0x0048 /* DMA channel 4 number of data register */ -#define STM32L4_DMA_CNDTR5_OFFSET 0x005c /* DMA channel 5 number of data register */ -#define STM32L4_DMA_CNDTR6_OFFSET 0x0070 /* DMA channel 6 number of data register */ -#define STM32L4_DMA_CNDTR7_OFFSET 0x0084 /* DMA channel 7 number of data register */ - -#define STM32L4_DMA_CPAR1_OFFSET 0x0010 /* DMA channel 1 peripheral address register */ -#define STM32L4_DMA_CPAR2_OFFSET 0x0024 /* DMA channel 2 peripheral address register */ -#define STM32L4_DMA_CPAR3_OFFSET 0x0038 /* DMA channel 3 peripheral address register */ -#define STM32L4_DMA_CPAR4_OFFSET 0x004c /* DMA channel 4 peripheral address register */ -#define STM32L4_DMA_CPAR5_OFFSET 0x0060 /* DMA channel 5 peripheral address register */ -#define STM32L4_DMA_CPAR6_OFFSET 0x0074 /* DMA channel 6 peripheral address register */ -#define STM32L4_DMA_CPAR7_OFFSET 0x0088 /* DMA channel 7 peripheral address register */ - -#define STM32L4_DMA_CMAR1_OFFSET 0x0014 /* DMA channel 1 memory address register */ -#define STM32L4_DMA_CMAR2_OFFSET 0x0028 /* DMA channel 2 memory address register */ -#define STM32L4_DMA_CMAR3_OFFSET 0x003c /* DMA channel 3 memory address register */ -#define STM32L4_DMA_CMAR4_OFFSET 0x0050 /* DMA channel 4 memory address register */ -#define STM32L4_DMA_CMAR5_OFFSET 0x0064 /* DMA channel 5 memory address register */ -#define STM32L4_DMA_CMAR6_OFFSET 0x0078 /* DMA channel 6 memory address register */ -#define STM32L4_DMA_CMAR7_OFFSET 0x008c /* DMA channel 7 memory address register */ - -#define STM32L4_DMA_CSELR_OFFSET 0x00a8 /* DMA channel selection register */ +#define STM32_DMA_ISR_OFFSET 0x0000 /* DMA interrupt status register */ +#define STM32_DMA_IFCR_OFFSET 0x0004 /* DMA interrupt flag clear register */ + +#define STM32_DMACHAN_OFFSET(n) (0x0014*(n)) +#define STM32_DMACHAN1_OFFSET 0x0000 +#define STM32_DMACHAN2_OFFSET 0x0014 +#define STM32_DMACHAN3_OFFSET 0x0028 +#define STM32_DMACHAN4_OFFSET 0x003c +#define STM32_DMACHAN5_OFFSET 0x0050 +#define STM32_DMACHAN6_OFFSET 0x0064 +#define STM32_DMACHAN7_OFFSET 0x0078 + +#define STM32_DMACHAN_CCR_OFFSET 0x0008 /* DMA channel configuration register */ +#define STM32_DMACHAN_CNDTR_OFFSET 0x000c /* DMA channel number of data register */ +#define STM32_DMACHAN_CPAR_OFFSET 0x0010 /* DMA channel peripheral address register */ +#define STM32_DMACHAN_CMAR_OFFSET 0x0014 /* DMA channel memory address register */ + +#define STM32_DMA_CCR_OFFSET(n) (STM32_DMACHAN_CCR_OFFSET+STM32_DMACHAN_OFFSET(n)) +#define STM32_DMA_CNDTR_OFFSET(n) (STM32_DMACHAN_CNDTR_OFFSET+STM32_DMACHAN_OFFSET(n)) +#define STM32_DMA_CPAR_OFFSET(n) (STM32_DMACHAN_CPAR_OFFSET+STM32_DMACHAN_OFFSET(n)) +#define STM32_DMA_CMAR_OFFSET(n) (STM32_DMACHAN_CMAR_OFFSET+STM32_DMACHAN_OFFSET(n)) + +#define STM32_DMA_CCR1_OFFSET 0x0008 /* DMA channel 1 configuration register */ +#define STM32_DMA_CCR2_OFFSET 0x001c /* DMA channel 2 configuration register */ +#define STM32_DMA_CCR3_OFFSET 0x0030 /* DMA channel 3 configuration register */ +#define STM32_DMA_CCR4_OFFSET 0x0044 /* DMA channel 4 configuration register */ +#define STM32_DMA_CCR5_OFFSET 0x0058 /* DMA channel 5 configuration register */ +#define STM32_DMA_CCR6_OFFSET 0x006c /* DMA channel 6 configuration register */ +#define STM32_DMA_CCR7_OFFSET 0x0080 /* DMA channel 7 configuration register */ + +#define STM32_DMA_CNDTR1_OFFSET 0x000c /* DMA channel 1 number of data register */ +#define STM32_DMA_CNDTR2_OFFSET 0x0020 /* DMA channel 2 number of data register */ +#define STM32_DMA_CNDTR3_OFFSET 0x0034 /* DMA channel 3 number of data register */ +#define STM32_DMA_CNDTR4_OFFSET 0x0048 /* DMA channel 4 number of data register */ +#define STM32_DMA_CNDTR5_OFFSET 0x005c /* DMA channel 5 number of data register */ +#define STM32_DMA_CNDTR6_OFFSET 0x0070 /* DMA channel 6 number of data register */ +#define STM32_DMA_CNDTR7_OFFSET 0x0084 /* DMA channel 7 number of data register */ + +#define STM32_DMA_CPAR1_OFFSET 0x0010 /* DMA channel 1 peripheral address register */ +#define STM32_DMA_CPAR2_OFFSET 0x0024 /* DMA channel 2 peripheral address register */ +#define STM32_DMA_CPAR3_OFFSET 0x0038 /* DMA channel 3 peripheral address register */ +#define STM32_DMA_CPAR4_OFFSET 0x004c /* DMA channel 4 peripheral address register */ +#define STM32_DMA_CPAR5_OFFSET 0x0060 /* DMA channel 5 peripheral address register */ +#define STM32_DMA_CPAR6_OFFSET 0x0074 /* DMA channel 6 peripheral address register */ +#define STM32_DMA_CPAR7_OFFSET 0x0088 /* DMA channel 7 peripheral address register */ + +#define STM32_DMA_CMAR1_OFFSET 0x0014 /* DMA channel 1 memory address register */ +#define STM32_DMA_CMAR2_OFFSET 0x0028 /* DMA channel 2 memory address register */ +#define STM32_DMA_CMAR3_OFFSET 0x003c /* DMA channel 3 memory address register */ +#define STM32_DMA_CMAR4_OFFSET 0x0050 /* DMA channel 4 memory address register */ +#define STM32_DMA_CMAR5_OFFSET 0x0064 /* DMA channel 5 memory address register */ +#define STM32_DMA_CMAR6_OFFSET 0x0078 /* DMA channel 6 memory address register */ +#define STM32_DMA_CMAR7_OFFSET 0x008c /* DMA channel 7 memory address register */ + +#define STM32_DMA_CSELR_OFFSET 0x00a8 /* DMA channel selection register */ /* Register Addresses *******************************************************/ -#define STM32L4_DMA1_ISRC (STM32L4_DMA1_BASE+STM32L4_DMA_ISR_OFFSET) -#define STM32L4_DMA1_IFCR (STM32L4_DMA1_BASE+STM32L4_DMA_IFCR_OFFSET) - -#define STM32L4_DMA1_CCR(n) (STM32L4_DMA1_BASE+STM32L4_DMA_CCR_OFFSET(n)) -#define STM32L4_DMA1_CCR1 (STM32L4_DMA1_BASE+STM32L4_DMA_CCR1_OFFSET) -#define STM32L4_DMA1_CCR2 (STM32L4_DMA1_BASE+STM32L4_DMA_CCR2_OFFSET) -#define STM32L4_DMA1_CCR3 (STM32L4_DMA1_BASE+STM32L4_DMA_CCR3_OFFSET) -#define STM32L4_DMA1_CCR4 (STM32L4_DMA1_BASE+STM32L4_DMA_CCR4_OFFSET) -#define STM32L4_DMA1_CCR5 (STM32L4_DMA1_BASE+STM32L4_DMA_CCR5_OFFSET) -#define STM32L4_DMA1_CCR6 (STM32L4_DMA1_BASE+STM32L4_DMA_CCR6_OFFSET) -#define STM32L4_DMA1_CCR7 (STM32L4_DMA1_BASE+STM32L4_DMA_CCR7_OFFSET) - -#define STM32L4_DMA1_CNDTR(n) (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR_OFFSET(n)) -#define STM32L4_DMA1_CNDTR1 (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR1_OFFSET) -#define STM32L4_DMA1_CNDTR2 (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR2_OFFSET) -#define STM32L4_DMA1_CNDTR3 (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR3_OFFSET) -#define STM32L4_DMA1_CNDTR4 (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR4_OFFSET) -#define STM32L4_DMA1_CNDTR5 (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR5_OFFSET) -#define STM32L4_DMA1_CNDTR6 (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR6_OFFSET) -#define STM32L4_DMA1_CNDTR7 (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR7_OFFSET) - -#define STM32L4_DMA1_CPAR(n) (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR_OFFSET(n)) -#define STM32L4_DMA1_CPAR1 (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR1_OFFSET) -#define STM32L4_DMA1_CPAR2 (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR2_OFFSET) -#define STM32L4_DMA1_CPAR3 (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR3_OFFSET) -#define STM32L4_DMA1_CPAR4 (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR4_OFFSET) -#define STM32L4_DMA1_CPAR5 (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR5_OFFSET) -#define STM32L4_DMA1_CPAR6 (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR6_OFFSET) -#define STM32L4_DMA1_CPAR7 (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR7_OFFSET) - -#define STM32L4_DMA1_CMAR(n) (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR_OFFSET(n)) -#define STM32L4_DMA1_CMAR1 (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR1_OFFSET) -#define STM32L4_DMA1_CMAR2 (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR2_OFFSET) -#define STM32L4_DMA1_CMAR3 (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR3_OFFSET) -#define STM32L4_DMA1_CMAR4 (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR4_OFFSET) -#define STM32L4_DMA1_CMAR5 (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR5_OFFSET) -#define STM32L4_DMA1_CMAR6 (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR6_OFFSET) -#define STM32L4_DMA1_CMAR7 (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR7_OFFSET) - -#define STM32L4_DMA2_ISRC (STM32L4_DMA2_BASE+STM32L4_DMA_ISR_OFFSET) -#define STM32L4_DMA2_IFCR (STM32L4_DMA2_BASE+STM32L4_DMA_IFCR_OFFSET) - -#define STM32L4_DMA2_CCR(n) (STM32L4_DMA2_BASE+STM32L4_DMA_CCR_OFFSET(n)) -#define STM32L4_DMA2_CCR1 (STM32L4_DMA2_BASE+STM32L4_DMA_CCR1_OFFSET) -#define STM32L4_DMA2_CCR2 (STM32L4_DMA2_BASE+STM32L4_DMA_CCR2_OFFSET) -#define STM32L4_DMA2_CCR3 (STM32L4_DMA2_BASE+STM32L4_DMA_CCR3_OFFSET) -#define STM32L4_DMA2_CCR4 (STM32L4_DMA2_BASE+STM32L4_DMA_CCR4_OFFSET) -#define STM32L4_DMA2_CCR5 (STM32L4_DMA2_BASE+STM32L4_DMA_CCR5_OFFSET) -#define STM32L4_DMA2_CCR6 (STM32L4_DMA2_BASE+STM32L4_DMA_CCR6_OFFSET) -#define STM32L4_DMA2_CCR7 (STM32L4_DMA2_BASE+STM32L4_DMA_CCR7_OFFSET) - -#define STM32L4_DMA2_CNDTR(n) (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR_OFFSET(n)) -#define STM32L4_DMA2_CNDTR1 (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR1_OFFSET) -#define STM32L4_DMA2_CNDTR2 (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR2_OFFSET) -#define STM32L4_DMA2_CNDTR3 (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR3_OFFSET) -#define STM32L4_DMA2_CNDTR4 (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR4_OFFSET) -#define STM32L4_DMA2_CNDTR5 (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR5_OFFSET) -#define STM32L4_DMA2_CNDTR6 (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR6_OFFSET) -#define STM32L4_DMA2_CNDTR7 (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR7_OFFSET) - -#define STM32L4_DMA2_CPAR(n) (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR_OFFSET(n)) -#define STM32L4_DMA2_CPAR1 (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR1_OFFSET) -#define STM32L4_DMA2_CPAR2 (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR2_OFFSET) -#define STM32L4_DMA2_CPAR3 (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR3_OFFSET) -#define STM32L4_DMA2_CPAR4 (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR4_OFFSET) -#define STM32L4_DMA2_CPAR5 (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR5_OFFSET) -#define STM32L4_DMA2_CPAR6 (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR6_OFFSET) -#define STM32L4_DMA2_CPAR7 (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR7_OFFSET) - -#define STM32L4_DMA2_CMAR(n) (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR_OFFSET(n)) -#define STM32L4_DMA2_CMAR1 (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR1_OFFSET) -#define STM32L4_DMA2_CMAR2 (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR2_OFFSET) -#define STM32L4_DMA2_CMAR3 (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR3_OFFSET) -#define STM32L4_DMA2_CMAR4 (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR4_OFFSET) -#define STM32L4_DMA2_CMAR5 (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR5_OFFSET) -#define STM32L4_DMA2_CMAR6 (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR6_OFFSET) -#define STM32L4_DMA2_CMAR7 (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR7_OFFSET) +#define STM32_DMA1_ISRC (STM32_DMA1_BASE+STM32_DMA_ISR_OFFSET) +#define STM32_DMA1_IFCR (STM32_DMA1_BASE+STM32_DMA_IFCR_OFFSET) + +#define STM32_DMA1_CCR(n) (STM32_DMA1_BASE+STM32_DMA_CCR_OFFSET(n)) +#define STM32_DMA1_CCR1 (STM32_DMA1_BASE+STM32_DMA_CCR1_OFFSET) +#define STM32_DMA1_CCR2 (STM32_DMA1_BASE+STM32_DMA_CCR2_OFFSET) +#define STM32_DMA1_CCR3 (STM32_DMA1_BASE+STM32_DMA_CCR3_OFFSET) +#define STM32_DMA1_CCR4 (STM32_DMA1_BASE+STM32_DMA_CCR4_OFFSET) +#define STM32_DMA1_CCR5 (STM32_DMA1_BASE+STM32_DMA_CCR5_OFFSET) +#define STM32_DMA1_CCR6 (STM32_DMA1_BASE+STM32_DMA_CCR6_OFFSET) +#define STM32_DMA1_CCR7 (STM32_DMA1_BASE+STM32_DMA_CCR7_OFFSET) + +#define STM32_DMA1_CNDTR(n) (STM32_DMA1_BASE+STM32_DMA_CNDTR_OFFSET(n)) +#define STM32_DMA1_CNDTR1 (STM32_DMA1_BASE+STM32_DMA_CNDTR1_OFFSET) +#define STM32_DMA1_CNDTR2 (STM32_DMA1_BASE+STM32_DMA_CNDTR2_OFFSET) +#define STM32_DMA1_CNDTR3 (STM32_DMA1_BASE+STM32_DMA_CNDTR3_OFFSET) +#define STM32_DMA1_CNDTR4 (STM32_DMA1_BASE+STM32_DMA_CNDTR4_OFFSET) +#define STM32_DMA1_CNDTR5 (STM32_DMA1_BASE+STM32_DMA_CNDTR5_OFFSET) +#define STM32_DMA1_CNDTR6 (STM32_DMA1_BASE+STM32_DMA_CNDTR6_OFFSET) +#define STM32_DMA1_CNDTR7 (STM32_DMA1_BASE+STM32_DMA_CNDTR7_OFFSET) + +#define STM32_DMA1_CPAR(n) (STM32_DMA1_BASE+STM32_DMA_CPAR_OFFSET(n)) +#define STM32_DMA1_CPAR1 (STM32_DMA1_BASE+STM32_DMA_CPAR1_OFFSET) +#define STM32_DMA1_CPAR2 (STM32_DMA1_BASE+STM32_DMA_CPAR2_OFFSET) +#define STM32_DMA1_CPAR3 (STM32_DMA1_BASE+STM32_DMA_CPAR3_OFFSET) +#define STM32_DMA1_CPAR4 (STM32_DMA1_BASE+STM32_DMA_CPAR4_OFFSET) +#define STM32_DMA1_CPAR5 (STM32_DMA1_BASE+STM32_DMA_CPAR5_OFFSET) +#define STM32_DMA1_CPAR6 (STM32_DMA1_BASE+STM32_DMA_CPAR6_OFFSET) +#define STM32_DMA1_CPAR7 (STM32_DMA1_BASE+STM32_DMA_CPAR7_OFFSET) + +#define STM32_DMA1_CMAR(n) (STM32_DMA1_BASE+STM32_DMA_CMAR_OFFSET(n)) +#define STM32_DMA1_CMAR1 (STM32_DMA1_BASE+STM32_DMA_CMAR1_OFFSET) +#define STM32_DMA1_CMAR2 (STM32_DMA1_BASE+STM32_DMA_CMAR2_OFFSET) +#define STM32_DMA1_CMAR3 (STM32_DMA1_BASE+STM32_DMA_CMAR3_OFFSET) +#define STM32_DMA1_CMAR4 (STM32_DMA1_BASE+STM32_DMA_CMAR4_OFFSET) +#define STM32_DMA1_CMAR5 (STM32_DMA1_BASE+STM32_DMA_CMAR5_OFFSET) +#define STM32_DMA1_CMAR6 (STM32_DMA1_BASE+STM32_DMA_CMAR6_OFFSET) +#define STM32_DMA1_CMAR7 (STM32_DMA1_BASE+STM32_DMA_CMAR7_OFFSET) + +#define STM32_DMA2_ISRC (STM32_DMA2_BASE+STM32_DMA_ISR_OFFSET) +#define STM32_DMA2_IFCR (STM32_DMA2_BASE+STM32_DMA_IFCR_OFFSET) + +#define STM32_DMA2_CCR(n) (STM32_DMA2_BASE+STM32_DMA_CCR_OFFSET(n)) +#define STM32_DMA2_CCR1 (STM32_DMA2_BASE+STM32_DMA_CCR1_OFFSET) +#define STM32_DMA2_CCR2 (STM32_DMA2_BASE+STM32_DMA_CCR2_OFFSET) +#define STM32_DMA2_CCR3 (STM32_DMA2_BASE+STM32_DMA_CCR3_OFFSET) +#define STM32_DMA2_CCR4 (STM32_DMA2_BASE+STM32_DMA_CCR4_OFFSET) +#define STM32_DMA2_CCR5 (STM32_DMA2_BASE+STM32_DMA_CCR5_OFFSET) +#define STM32_DMA2_CCR6 (STM32_DMA2_BASE+STM32_DMA_CCR6_OFFSET) +#define STM32_DMA2_CCR7 (STM32_DMA2_BASE+STM32_DMA_CCR7_OFFSET) + +#define STM32_DMA2_CNDTR(n) (STM32_DMA2_BASE+STM32_DMA_CNDTR_OFFSET(n)) +#define STM32_DMA2_CNDTR1 (STM32_DMA2_BASE+STM32_DMA_CNDTR1_OFFSET) +#define STM32_DMA2_CNDTR2 (STM32_DMA2_BASE+STM32_DMA_CNDTR2_OFFSET) +#define STM32_DMA2_CNDTR3 (STM32_DMA2_BASE+STM32_DMA_CNDTR3_OFFSET) +#define STM32_DMA2_CNDTR4 (STM32_DMA2_BASE+STM32_DMA_CNDTR4_OFFSET) +#define STM32_DMA2_CNDTR5 (STM32_DMA2_BASE+STM32_DMA_CNDTR5_OFFSET) +#define STM32_DMA2_CNDTR6 (STM32_DMA2_BASE+STM32_DMA_CNDTR6_OFFSET) +#define STM32_DMA2_CNDTR7 (STM32_DMA2_BASE+STM32_DMA_CNDTR7_OFFSET) + +#define STM32_DMA2_CPAR(n) (STM32_DMA2_BASE+STM32_DMA_CPAR_OFFSET(n)) +#define STM32_DMA2_CPAR1 (STM32_DMA2_BASE+STM32_DMA_CPAR1_OFFSET) +#define STM32_DMA2_CPAR2 (STM32_DMA2_BASE+STM32_DMA_CPAR2_OFFSET) +#define STM32_DMA2_CPAR3 (STM32_DMA2_BASE+STM32_DMA_CPAR3_OFFSET) +#define STM32_DMA2_CPAR4 (STM32_DMA2_BASE+STM32_DMA_CPAR4_OFFSET) +#define STM32_DMA2_CPAR5 (STM32_DMA2_BASE+STM32_DMA_CPAR5_OFFSET) +#define STM32_DMA2_CPAR6 (STM32_DMA2_BASE+STM32_DMA_CPAR6_OFFSET) +#define STM32_DMA2_CPAR7 (STM32_DMA2_BASE+STM32_DMA_CPAR7_OFFSET) + +#define STM32_DMA2_CMAR(n) (STM32_DMA2_BASE+STM32_DMA_CMAR_OFFSET(n)) +#define STM32_DMA2_CMAR1 (STM32_DMA2_BASE+STM32_DMA_CMAR1_OFFSET) +#define STM32_DMA2_CMAR2 (STM32_DMA2_BASE+STM32_DMA_CMAR2_OFFSET) +#define STM32_DMA2_CMAR3 (STM32_DMA2_BASE+STM32_DMA_CMAR3_OFFSET) +#define STM32_DMA2_CMAR4 (STM32_DMA2_BASE+STM32_DMA_CMAR4_OFFSET) +#define STM32_DMA2_CMAR5 (STM32_DMA2_BASE+STM32_DMA_CMAR5_OFFSET) +#define STM32_DMA2_CMAR6 (STM32_DMA2_BASE+STM32_DMA_CMAR6_OFFSET) +#define STM32_DMA2_CMAR7 (STM32_DMA2_BASE+STM32_DMA_CMAR7_OFFSET) /* Register Bitfield Definitions ********************************************/ @@ -277,21 +277,21 @@ * numeric suffix. Additional definitions are required in the board.h file. */ -#define STM32L4_DMA1_CHAN1 (0) -#define STM32L4_DMA1_CHAN2 (1) -#define STM32L4_DMA1_CHAN3 (2) -#define STM32L4_DMA1_CHAN4 (3) -#define STM32L4_DMA1_CHAN5 (4) -#define STM32L4_DMA1_CHAN6 (5) -#define STM32L4_DMA1_CHAN7 (6) - -#define STM32L4_DMA2_CHAN1 (7) -#define STM32L4_DMA2_CHAN2 (8) -#define STM32L4_DMA2_CHAN3 (9) -#define STM32L4_DMA2_CHAN4 (10) -#define STM32L4_DMA2_CHAN5 (11) -#define STM32L4_DMA2_CHAN6 (12) -#define STM32L4_DMA2_CHAN7 (13) +#define STM32_DMA1_CHAN1 (0) +#define STM32_DMA1_CHAN2 (1) +#define STM32_DMA1_CHAN3 (2) +#define STM32_DMA1_CHAN4 (3) +#define STM32_DMA1_CHAN5 (4) +#define STM32_DMA1_CHAN6 (5) +#define STM32_DMA1_CHAN7 (6) + +#define STM32_DMA2_CHAN1 (7) +#define STM32_DMA2_CHAN2 (8) +#define STM32_DMA2_CHAN3 (9) +#define STM32_DMA2_CHAN4 (10) +#define STM32_DMA2_CHAN5 (11) +#define STM32_DMA2_CHAN6 (12) +#define STM32_DMA2_CHAN7 (13) /* DMA Channel settings include a channel and an alternative function. * Channel is in bits 0..7 @@ -306,167 +306,167 @@ /* ADC */ -#define DMACHAN_ADC1_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN1, 0) -#define DMACHAN_ADC1_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN3, 0) +#define DMACHAN_ADC1_1 DMACHAN_SETTING(STM32_DMA1_CHAN1, 0) +#define DMACHAN_ADC1_2 DMACHAN_SETTING(STM32_DMA2_CHAN3, 0) -#define DMACHAN_ADC2_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN1, 0) -#define DMACHAN_ADC2_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN4, 0) +#define DMACHAN_ADC2_1 DMACHAN_SETTING(STM32_DMA1_CHAN1, 0) +#define DMACHAN_ADC2_2 DMACHAN_SETTING(STM32_DMA2_CHAN4, 0) -#define DMACHAN_ADC3_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN1, 0) -#define DMACHAN_ADC3_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN5, 0) +#define DMACHAN_ADC3_1 DMACHAN_SETTING(STM32_DMA1_CHAN1, 0) +#define DMACHAN_ADC3_2 DMACHAN_SETTING(STM32_DMA2_CHAN5, 0) /* DAC */ -#define DMACHAN_DAC1_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 6) -#define DMACHAN_DAC1_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN4, 3) +#define DMACHAN_DAC1_1 DMACHAN_SETTING(STM32_DMA1_CHAN3, 6) +#define DMACHAN_DAC1_2 DMACHAN_SETTING(STM32_DMA2_CHAN4, 3) -#define DMACHAN_DAC2_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN4, 5) -#define DMACHAN_DAC2_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN5, 3) +#define DMACHAN_DAC2_1 DMACHAN_SETTING(STM32_DMA1_CHAN4, 5) +#define DMACHAN_DAC2_2 DMACHAN_SETTING(STM32_DMA2_CHAN5, 3) /* DFSDM */ -#define DMACHAN_DFSDM0 DMACHAN_SETTING(STM32L4_DMA1_CHAN4, 0) -#define DMACHAN_DFSDM1 DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 0) -#define DMACHAN_DFSDM2 DMACHAN_SETTING(STM32L4_DMA1_CHAN6, 0) -#define DMACHAN_DFSDM3 DMACHAN_SETTING(STM32L4_DMA1_CHAN7, 0) +#define DMACHAN_DFSDM0 DMACHAN_SETTING(STM32_DMA1_CHAN4, 0) +#define DMACHAN_DFSDM1 DMACHAN_SETTING(STM32_DMA1_CHAN5, 0) +#define DMACHAN_DFSDM2 DMACHAN_SETTING(STM32_DMA1_CHAN6, 0) +#define DMACHAN_DFSDM3 DMACHAN_SETTING(STM32_DMA1_CHAN7, 0) /* I2C */ -#define DMACHAN_I2C1_RX_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN7, 3) -#define DMACHAN_I2C1_RX_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN6, 5) -#define DMACHAN_I2C1_TX_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN6, 3) -#define DMACHAN_I2C1_TX_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN7, 5) +#define DMACHAN_I2C1_RX_1 DMACHAN_SETTING(STM32_DMA1_CHAN7, 3) +#define DMACHAN_I2C1_RX_2 DMACHAN_SETTING(STM32_DMA2_CHAN6, 5) +#define DMACHAN_I2C1_TX_1 DMACHAN_SETTING(STM32_DMA1_CHAN6, 3) +#define DMACHAN_I2C1_TX_2 DMACHAN_SETTING(STM32_DMA2_CHAN7, 5) -#define DMACHAN_I2C2_RX DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 3) -#define DMACHAN_I2C2_TX DMACHAN_SETTING(STM32L4_DMA1_CHAN4, 3) +#define DMACHAN_I2C2_RX DMACHAN_SETTING(STM32_DMA1_CHAN5, 3) +#define DMACHAN_I2C2_TX DMACHAN_SETTING(STM32_DMA1_CHAN4, 3) -#define DMACHAN_I2C3_RX DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 3) -#define DMACHAN_I2C3_TX DMACHAN_SETTING(STM32L4_DMA1_CHAN2, 3) +#define DMACHAN_I2C3_RX DMACHAN_SETTING(STM32_DMA1_CHAN3, 3) +#define DMACHAN_I2C3_TX DMACHAN_SETTING(STM32_DMA1_CHAN2, 3) /* QUADSPI */ -#define DMACHAN_QUADSPI_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 5) -#define DMACHAN_QUADSPI_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN7, 3) +#define DMACHAN_QUADSPI_1 DMACHAN_SETTING(STM32_DMA1_CHAN5, 5) +#define DMACHAN_QUADSPI_2 DMACHAN_SETTING(STM32_DMA2_CHAN7, 3) /* SAI */ -#define DMACHAN_SAI1_A_1 DMACHAN_SETTING(STM32L4_DMA2_CHAN1, 1) -#define DMACHAN_SAI1_A_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN6, 1) -#define DMACHAN_SAI1_B_1 DMACHAN_SETTING(STM32L4_DMA2_CHAN2, 1) -#define DMACHAN_SAI1_B_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN7, 1) +#define DMACHAN_SAI1_A_1 DMACHAN_SETTING(STM32_DMA2_CHAN1, 1) +#define DMACHAN_SAI1_A_2 DMACHAN_SETTING(STM32_DMA2_CHAN6, 1) +#define DMACHAN_SAI1_B_1 DMACHAN_SETTING(STM32_DMA2_CHAN2, 1) +#define DMACHAN_SAI1_B_2 DMACHAN_SETTING(STM32_DMA2_CHAN7, 1) -#define DMACHAN_SAI2_A_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN6, 1) -#define DMACHAN_SAI2_A_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN3, 1) -#define DMACHAN_SAI2_B_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN7, 1) -#define DMACHAN_SAI2_B_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN4, 1) +#define DMACHAN_SAI2_A_1 DMACHAN_SETTING(STM32_DMA1_CHAN6, 1) +#define DMACHAN_SAI2_A_2 DMACHAN_SETTING(STM32_DMA2_CHAN3, 1) +#define DMACHAN_SAI2_B_1 DMACHAN_SETTING(STM32_DMA1_CHAN7, 1) +#define DMACHAN_SAI2_B_2 DMACHAN_SETTING(STM32_DMA2_CHAN4, 1) /* SDMMC */ -#define DMACHAN_SDMMC_1 DMACHAN_SETTING(STM32L4_DMA2_CHAN4, 7) -#define DMACHAN_SDMMC_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN5, 7) +#define DMACHAN_SDMMC_1 DMACHAN_SETTING(STM32_DMA2_CHAN4, 7) +#define DMACHAN_SDMMC_2 DMACHAN_SETTING(STM32_DMA2_CHAN5, 7) /* SPI */ -#define DMACHAN_SPI1_RX_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN2, 1) -#define DMACHAN_SPI1_RX_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN3, 4) -#define DMACHAN_SPI1_TX_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 1) -#define DMACHAN_SPI1_TX_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN4, 4) +#define DMACHAN_SPI1_RX_1 DMACHAN_SETTING(STM32_DMA1_CHAN2, 1) +#define DMACHAN_SPI1_RX_2 DMACHAN_SETTING(STM32_DMA2_CHAN3, 4) +#define DMACHAN_SPI1_TX_1 DMACHAN_SETTING(STM32_DMA1_CHAN3, 1) +#define DMACHAN_SPI1_TX_2 DMACHAN_SETTING(STM32_DMA2_CHAN4, 4) -#define DMACHAN_SPI2_RX DMACHAN_SETTING(STM32L4_DMA1_CHAN4, 1) -#define DMACHAN_SPI2_TX DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 1) +#define DMACHAN_SPI2_RX DMACHAN_SETTING(STM32_DMA1_CHAN4, 1) +#define DMACHAN_SPI2_TX DMACHAN_SETTING(STM32_DMA1_CHAN5, 1) -#define DMACHAN_SPI3_RX DMACHAN_SETTING(STM32L4_DMA2_CHAN1, 3) -#define DMACHAN_SPI3_TX DMACHAN_SETTING(STM32L4_DMA2_CHAN2, 3) +#define DMACHAN_SPI3_RX DMACHAN_SETTING(STM32_DMA2_CHAN1, 3) +#define DMACHAN_SPI3_TX DMACHAN_SETTING(STM32_DMA2_CHAN2, 3) /* SWPMI */ -#define DMACHAN_SWPMI_RX DMACHAN_SETTING(STM32L4_DMA2_CHAN1, 4) -#define DMACHAN_SWPMI_TX DMACHAN_SETTING(STM32L4_DMA2_CHAN2, 4) +#define DMACHAN_SWPMI_RX DMACHAN_SETTING(STM32_DMA2_CHAN1, 4) +#define DMACHAN_SWPMI_TX DMACHAN_SETTING(STM32_DMA2_CHAN2, 4) /* TIM */ -#define DMACHAN_TIM1_CH1 DMACHAN_SETTING(STM32L4_DMA1_CHAN2, 7) -#define DMACHAN_TIM1_CH2 DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 7) -#define DMACHAN_TIM1_CH3 DMACHAN_SETTING(STM32L4_DMA1_CHAN7, 7) -#define DMACHAN_TIM1_CH4 DMACHAN_SETTING(STM32L4_DMA1_CHAN4, 7) -#define DMACHAN_TIM1_COM DMACHAN_SETTING(STM32L4_DMA1_CHAN4, 7) -#define DMACHAN_TIM1_TRIG DMACHAN_SETTING(STM32L4_DMA1_CHAN4, 7) -#define DMACHAN_TIM1_UP DMACHAN_SETTING(STM32L4_DMA1_CHAN6, 7) - -#define DMACHAN_TIM2_CH1 DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 4) -#define DMACHAN_TIM2_CH2 DMACHAN_SETTING(STM32L4_DMA1_CHAN7, 4) -#define DMACHAN_TIM2_CH3 DMACHAN_SETTING(STM32L4_DMA1_CHAN1, 4) -#define DMACHAN_TIM2_CH4 DMACHAN_SETTING(STM32L4_DMA1_CHAN7, 4) -#define DMACHAN_TIM2_UP DMACHAN_SETTING(STM32L4_DMA1_CHAN2, 4) - -#define DMACHAN_TIM3_CH1 DMACHAN_SETTING(STM32L4_DMA1_CHAN6, 5) -#define DMACHAN_TIM3_CH3 DMACHAN_SETTING(STM32L4_DMA1_CHAN2, 5) -#define DMACHAN_TIM3_CH4 DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 5) -#define DMACHAN_TIM3_TRIG DMACHAN_SETTING(STM32L4_DMA1_CHAN6, 5) -#define DMACHAN_TIM3_UP DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 5) - -#define DMACHAN_TIM4_CH1 DMACHAN_SETTING(STM32L4_DMA1_CHAN1, 6) -#define DMACHAN_TIM4_CH2 DMACHAN_SETTING(STM32L4_DMA1_CHAN4, 6) -#define DMACHAN_TIM4_CH3 DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 6) -#define DMACHAN_TIM4_UP DMACHAN_SETTING(STM32L4_DMA1_CHAN7, 6) - -#define DMACHAN_TIM5_CH1 DMACHAN_SETTING(STM32L4_DMA2_CHAN5, 5) -#define DMACHAN_TIM5_CH2 DMACHAN_SETTING(STM32L4_DMA2_CHAN4, 5) -#define DMACHAN_TIM5_CH3 DMACHAN_SETTING(STM32L4_DMA2_CHAN2, 5) -#define DMACHAN_TIM5_CH4 DMACHAN_SETTING(STM32L4_DMA2_CHAN1, 5) -#define DMACHAN_TIM5_COM DMACHAN_SETTING(STM32L4_DMA2_CHAN1, 5) -#define DMACHAN_TIM5_TRIG DMACHAN_SETTING(STM32L4_DMA2_CHAN1, 5) -#define DMACHAN_TIM5_UP DMACHAN_SETTING(STM32L4_DMA2_CHAN2, 5) - -#define DMACHAN_TIM6_UP_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 6) -#define DMACHAN_TIM6_UP_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN4, 3) - -#define DMACHAN_TIM7_UP_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN4, 5) -#define DMACHAN_TIM7_UP_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN5, 3) - -#define DMACHAN_TIM8_CH1 DMACHAN_SETTING(STM32L4_DMA2_CHAN6, 7) -#define DMACHAN_TIM8_CH2 DMACHAN_SETTING(STM32L4_DMA2_CHAN7, 7) -#define DMACHAN_TIM8_CH3 DMACHAN_SETTING(STM32L4_DMA2_CHAN1, 7) -#define DMACHAN_TIM8_CH4 DMACHAN_SETTING(STM32L4_DMA2_CHAN2, 7) -#define DMACHAN_TIM8_COM DMACHAN_SETTING(STM32L4_DMA2_CHAN2, 7) -#define DMACHAN_TIM8_TRIG DMACHAN_SETTING(STM32L4_DMA2_CHAN2, 7) -#define DMACHAN_TIM8_UP DMACHAN_SETTING(STM32L4_DMA2_CHAN1, 7) - -#define DMACHAN_TIM15_CH1 DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 7) -#define DMACHAN_TIM15_COM DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 7) -#define DMACHAN_TIM15_TRIG DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 7) -#define DMACHAN_TIM15_UP DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 7) - -#define DMACHAN_TIM16_CH1_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 4) -#define DMACHAN_TIM16_CH1_2 DMACHAN_SETTING(STM32L4_DMA1_CHAN6, 4) -#define DMACHAN_TIM16_UP_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 4) -#define DMACHAN_TIM16_UP_2 DMACHAN_SETTING(STM32L4_DMA1_CHAN6, 4) - -#define DMACHAN_TIM17_CH1_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN1, 5) -#define DMACHAN_TIM17_CH1_2 DMACHAN_SETTING(STM32L4_DMA1_CHAN7, 5) -#define DMACHAN_TIM17_UP_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN1, 5) -#define DMACHAN_TIM17_UP_2 DMACHAN_SETTING(STM32L4_DMA1_CHAN7, 5) +#define DMACHAN_TIM1_CH1 DMACHAN_SETTING(STM32_DMA1_CHAN2, 7) +#define DMACHAN_TIM1_CH2 DMACHAN_SETTING(STM32_DMA1_CHAN3, 7) +#define DMACHAN_TIM1_CH3 DMACHAN_SETTING(STM32_DMA1_CHAN7, 7) +#define DMACHAN_TIM1_CH4 DMACHAN_SETTING(STM32_DMA1_CHAN4, 7) +#define DMACHAN_TIM1_COM DMACHAN_SETTING(STM32_DMA1_CHAN4, 7) +#define DMACHAN_TIM1_TRIG DMACHAN_SETTING(STM32_DMA1_CHAN4, 7) +#define DMACHAN_TIM1_UP DMACHAN_SETTING(STM32_DMA1_CHAN6, 7) + +#define DMACHAN_TIM2_CH1 DMACHAN_SETTING(STM32_DMA1_CHAN5, 4) +#define DMACHAN_TIM2_CH2 DMACHAN_SETTING(STM32_DMA1_CHAN7, 4) +#define DMACHAN_TIM2_CH3 DMACHAN_SETTING(STM32_DMA1_CHAN1, 4) +#define DMACHAN_TIM2_CH4 DMACHAN_SETTING(STM32_DMA1_CHAN7, 4) +#define DMACHAN_TIM2_UP DMACHAN_SETTING(STM32_DMA1_CHAN2, 4) + +#define DMACHAN_TIM3_CH1 DMACHAN_SETTING(STM32_DMA1_CHAN6, 5) +#define DMACHAN_TIM3_CH3 DMACHAN_SETTING(STM32_DMA1_CHAN2, 5) +#define DMACHAN_TIM3_CH4 DMACHAN_SETTING(STM32_DMA1_CHAN3, 5) +#define DMACHAN_TIM3_TRIG DMACHAN_SETTING(STM32_DMA1_CHAN6, 5) +#define DMACHAN_TIM3_UP DMACHAN_SETTING(STM32_DMA1_CHAN3, 5) + +#define DMACHAN_TIM4_CH1 DMACHAN_SETTING(STM32_DMA1_CHAN1, 6) +#define DMACHAN_TIM4_CH2 DMACHAN_SETTING(STM32_DMA1_CHAN4, 6) +#define DMACHAN_TIM4_CH3 DMACHAN_SETTING(STM32_DMA1_CHAN5, 6) +#define DMACHAN_TIM4_UP DMACHAN_SETTING(STM32_DMA1_CHAN7, 6) + +#define DMACHAN_TIM5_CH1 DMACHAN_SETTING(STM32_DMA2_CHAN5, 5) +#define DMACHAN_TIM5_CH2 DMACHAN_SETTING(STM32_DMA2_CHAN4, 5) +#define DMACHAN_TIM5_CH3 DMACHAN_SETTING(STM32_DMA2_CHAN2, 5) +#define DMACHAN_TIM5_CH4 DMACHAN_SETTING(STM32_DMA2_CHAN1, 5) +#define DMACHAN_TIM5_COM DMACHAN_SETTING(STM32_DMA2_CHAN1, 5) +#define DMACHAN_TIM5_TRIG DMACHAN_SETTING(STM32_DMA2_CHAN1, 5) +#define DMACHAN_TIM5_UP DMACHAN_SETTING(STM32_DMA2_CHAN2, 5) + +#define DMACHAN_TIM6_UP_1 DMACHAN_SETTING(STM32_DMA1_CHAN3, 6) +#define DMACHAN_TIM6_UP_2 DMACHAN_SETTING(STM32_DMA2_CHAN4, 3) + +#define DMACHAN_TIM7_UP_1 DMACHAN_SETTING(STM32_DMA1_CHAN4, 5) +#define DMACHAN_TIM7_UP_2 DMACHAN_SETTING(STM32_DMA2_CHAN5, 3) + +#define DMACHAN_TIM8_CH1 DMACHAN_SETTING(STM32_DMA2_CHAN6, 7) +#define DMACHAN_TIM8_CH2 DMACHAN_SETTING(STM32_DMA2_CHAN7, 7) +#define DMACHAN_TIM8_CH3 DMACHAN_SETTING(STM32_DMA2_CHAN1, 7) +#define DMACHAN_TIM8_CH4 DMACHAN_SETTING(STM32_DMA2_CHAN2, 7) +#define DMACHAN_TIM8_COM DMACHAN_SETTING(STM32_DMA2_CHAN2, 7) +#define DMACHAN_TIM8_TRIG DMACHAN_SETTING(STM32_DMA2_CHAN2, 7) +#define DMACHAN_TIM8_UP DMACHAN_SETTING(STM32_DMA2_CHAN1, 7) + +#define DMACHAN_TIM15_CH1 DMACHAN_SETTING(STM32_DMA1_CHAN5, 7) +#define DMACHAN_TIM15_COM DMACHAN_SETTING(STM32_DMA1_CHAN5, 7) +#define DMACHAN_TIM15_TRIG DMACHAN_SETTING(STM32_DMA1_CHAN5, 7) +#define DMACHAN_TIM15_UP DMACHAN_SETTING(STM32_DMA1_CHAN5, 7) + +#define DMACHAN_TIM16_CH1_1 DMACHAN_SETTING(STM32_DMA1_CHAN3, 4) +#define DMACHAN_TIM16_CH1_2 DMACHAN_SETTING(STM32_DMA1_CHAN6, 4) +#define DMACHAN_TIM16_UP_1 DMACHAN_SETTING(STM32_DMA1_CHAN3, 4) +#define DMACHAN_TIM16_UP_2 DMACHAN_SETTING(STM32_DMA1_CHAN6, 4) + +#define DMACHAN_TIM17_CH1_1 DMACHAN_SETTING(STM32_DMA1_CHAN1, 5) +#define DMACHAN_TIM17_CH1_2 DMACHAN_SETTING(STM32_DMA1_CHAN7, 5) +#define DMACHAN_TIM17_UP_1 DMACHAN_SETTING(STM32_DMA1_CHAN1, 5) +#define DMACHAN_TIM17_UP_2 DMACHAN_SETTING(STM32_DMA1_CHAN7, 5) /* UART */ -#define DMACHAN_USART1_RX_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 2) -#define DMACHAN_USART1_RX_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN7, 2) -#define DMACHAN_USART1_TX_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN4, 2) -#define DMACHAN_USART1_TX_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN6, 2) +#define DMACHAN_USART1_RX_1 DMACHAN_SETTING(STM32_DMA1_CHAN5, 2) +#define DMACHAN_USART1_RX_2 DMACHAN_SETTING(STM32_DMA2_CHAN7, 2) +#define DMACHAN_USART1_TX_1 DMACHAN_SETTING(STM32_DMA1_CHAN4, 2) +#define DMACHAN_USART1_TX_2 DMACHAN_SETTING(STM32_DMA2_CHAN6, 2) -#define DMACHAN_USART2_RX DMACHAN_SETTING(STM32L4_DMA1_CHAN6, 2) -#define DMACHAN_USART2_TX DMACHAN_SETTING(STM32L4_DMA1_CHAN7, 2) +#define DMACHAN_USART2_RX DMACHAN_SETTING(STM32_DMA1_CHAN6, 2) +#define DMACHAN_USART2_TX DMACHAN_SETTING(STM32_DMA1_CHAN7, 2) -#define DMACHAN_USART3_RX DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 2) -#define DMACHAN_USART3_TX DMACHAN_SETTING(STM32L4_DMA1_CHAN2, 2) +#define DMACHAN_USART3_RX DMACHAN_SETTING(STM32_DMA1_CHAN3, 2) +#define DMACHAN_USART3_TX DMACHAN_SETTING(STM32_DMA1_CHAN2, 2) -#define DMACHAN_UART5_RX DMACHAN_SETTING(STM32L4_DMA2_CHAN2, 2) -#define DMACHAN_UART5_TX DMACHAN_SETTING(STM32L4_DMA2_CHAN1, 2) +#define DMACHAN_UART5_RX DMACHAN_SETTING(STM32_DMA2_CHAN2, 2) +#define DMACHAN_UART5_TX DMACHAN_SETTING(STM32_DMA2_CHAN1, 2) -#define DMACHAN_UART4_RX DMACHAN_SETTING(STM32L4_DMA2_CHAN5, 2) -#define DMACHAN_UART4_TX DMACHAN_SETTING(STM32L4_DMA2_CHAN3, 2) +#define DMACHAN_UART4_RX DMACHAN_SETTING(STM32_DMA2_CHAN5, 2) +#define DMACHAN_UART4_TX DMACHAN_SETTING(STM32_DMA2_CHAN3, 2) -#define DMACHAN_LPUART_RX DMACHAN_SETTING(STM32L4_DMA2_CHAN7, 4) -#define DMACHAN_LPUART_TX DMACHAN_SETTING(STM32L4_DMA2_CHAN6, 4) +#define DMACHAN_LPUART_RX DMACHAN_SETTING(STM32_DMA2_CHAN7, 4) +#define DMACHAN_LPUART_TX DMACHAN_SETTING(STM32_DMA2_CHAN6, 4) #endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4X5XX_DMA_H */ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4x5xx_firewall.h b/arch/arm/src/stm32l4/hardware/stm32l4x5xx_firewall.h index 6ca4fea84720a..df83782f5a863 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4x5xx_firewall.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4x5xx_firewall.h @@ -38,23 +38,23 @@ /* Register Offsets *********************************************************/ -#define STM32L4_FIREWALL_CSSA_OFFSET 0x0000 -#define STM32L4_FIREWALL_CSL_OFFSET 0x0004 -#define STM32L4_FIREWALL_NVDSSA_OFFSET 0x0008 -#define STM32L4_FIREWALL_NVDSL_OFFSET 0x000c -#define STM32L4_FIREWALL_VDSSA_OFFSET 0x0010 -#define STM32L4_FIREWALL_VDSL_OFFSET 0x0014 -#define STM32L4_FIREWALL_CR_OFFSET 0x0020 +#define STM32_FIREWALL_CSSA_OFFSET 0x0000 +#define STM32_FIREWALL_CSL_OFFSET 0x0004 +#define STM32_FIREWALL_NVDSSA_OFFSET 0x0008 +#define STM32_FIREWALL_NVDSL_OFFSET 0x000c +#define STM32_FIREWALL_VDSSA_OFFSET 0x0010 +#define STM32_FIREWALL_VDSL_OFFSET 0x0014 +#define STM32_FIREWALL_CR_OFFSET 0x0020 /* Register Addresses *******************************************************/ -#define STM32L4_FIREWALL_CSSA (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_CSSA_OFFSET) -#define STM32L4_FIREWALL_CSL (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_CSL_OFFSET) -#define STM32L4_FIREWALL_NVDSSA (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_NVDSSA_OFFSET) -#define STM32L4_FIREWALL_NVDSL (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_NVDSL_OFFSET) -#define STM32L4_FIREWALL_VDSSA (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_VDSSA_OFFSET) -#define STM32L4_FIREWALL_VDSL (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_VDSL_OFFSET) -#define STM32L4_FIREWALL_CR (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_CR_OFFSET) +#define STM32_FIREWALL_CSSA (STM32_FIREWALL_BASE+STM32_FIREWALL_CSSA_OFFSET) +#define STM32_FIREWALL_CSL (STM32_FIREWALL_BASE+STM32_FIREWALL_CSL_OFFSET) +#define STM32_FIREWALL_NVDSSA (STM32_FIREWALL_BASE+STM32_FIREWALL_NVDSSA_OFFSET) +#define STM32_FIREWALL_NVDSL (STM32_FIREWALL_BASE+STM32_FIREWALL_NVDSL_OFFSET) +#define STM32_FIREWALL_VDSSA (STM32_FIREWALL_BASE+STM32_FIREWALL_VDSSA_OFFSET) +#define STM32_FIREWALL_VDSL (STM32_FIREWALL_BASE+STM32_FIREWALL_VDSL_OFFSET) +#define STM32_FIREWALL_CR (STM32_FIREWALL_BASE+STM32_FIREWALL_CR_OFFSET) /* Register Bitfield Definitions ********************************************/ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4x5xx_otgfs.h b/arch/arm/src/stm32l4/hardware/stm32l4x5xx_otgfs.h index 9ca5ed2dbecc6..7e78f15e1711e 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4x5xx_otgfs.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4x5xx_otgfs.h @@ -48,182 +48,182 @@ /* Core global control and status registers */ -#define STM32L4_OTGFS_GOTGCTL_OFFSET 0x0000 /* Control and status register */ -#define STM32L4_OTGFS_GOTGINT_OFFSET 0x0004 /* Interrupt register */ -#define STM32L4_OTGFS_GAHBCFG_OFFSET 0x0008 /* AHB configuration register */ -#define STM32L4_OTGFS_GUSBCFG_OFFSET 0x000c /* USB configuration register */ -#define STM32L4_OTGFS_GRSTCTL_OFFSET 0x0010 /* Reset register */ -#define STM32L4_OTGFS_GINTSTS_OFFSET 0x0014 /* Core interrupt register */ -#define STM32L4_OTGFS_GINTMSK_OFFSET 0x0018 /* Interrupt mask register */ -#define STM32L4_OTGFS_GRXSTSR_OFFSET 0x001c /* Receive status debug read/OTG status read register */ -#define STM32L4_OTGFS_GRXSTSP_OFFSET 0x0020 /* Receive status debug read/OTG status pop register */ -#define STM32L4_OTGFS_GRXFSIZ_OFFSET 0x0024 /* Receive FIFO size register */ -#define STM32L4_OTGFS_HNPTXFSIZ_OFFSET 0x0028 /* Host non-periodic transmit FIFO size register */ -#define STM32L4_OTGFS_DIEPTXF0_OFFSET 0x0028 /* Endpoint 0 Transmit FIFO size */ -#define STM32L4_OTGFS_HNPTXSTS_OFFSET 0x002c /* Non-periodic transmit FIFO/queue status register */ -#define STM32L4_OTGFS_GCCFG_OFFSET 0x0038 /* General core configuration register */ -#define STM32L4_OTGFS_CID_OFFSET 0x003c /* Core ID register */ -#define STM32L4_OTGFS_GLPMCFG_OFFSET 0x0054 /* LPM configuration register */ -#define STM32L4_OTGFS_GPWRDN_OFFSET 0x0058 /* Power down register */ -#define STM32L4_OTGFS_GADPCTL_OFSSET 0x0060 /* ADP timer, control and status register */ -#define STM32L4_OTGFS_HPTXFSIZ_OFFSET 0x0100 /* Host periodic transmit FIFO size register */ - -#define STM32L4_OTGFS_DIEPTXF_OFFSET(n) (0x0104+(((n)-1) << 2)) +#define STM32_OTGFS_GOTGCTL_OFFSET 0x0000 /* Control and status register */ +#define STM32_OTGFS_GOTGINT_OFFSET 0x0004 /* Interrupt register */ +#define STM32_OTGFS_GAHBCFG_OFFSET 0x0008 /* AHB configuration register */ +#define STM32_OTGFS_GUSBCFG_OFFSET 0x000c /* USB configuration register */ +#define STM32_OTGFS_GRSTCTL_OFFSET 0x0010 /* Reset register */ +#define STM32_OTGFS_GINTSTS_OFFSET 0x0014 /* Core interrupt register */ +#define STM32_OTGFS_GINTMSK_OFFSET 0x0018 /* Interrupt mask register */ +#define STM32_OTGFS_GRXSTSR_OFFSET 0x001c /* Receive status debug read/OTG status read register */ +#define STM32_OTGFS_GRXSTSP_OFFSET 0x0020 /* Receive status debug read/OTG status pop register */ +#define STM32_OTGFS_GRXFSIZ_OFFSET 0x0024 /* Receive FIFO size register */ +#define STM32_OTGFS_HNPTXFSIZ_OFFSET 0x0028 /* Host non-periodic transmit FIFO size register */ +#define STM32_OTGFS_DIEPTXF0_OFFSET 0x0028 /* Endpoint 0 Transmit FIFO size */ +#define STM32_OTGFS_HNPTXSTS_OFFSET 0x002c /* Non-periodic transmit FIFO/queue status register */ +#define STM32_OTGFS_GCCFG_OFFSET 0x0038 /* General core configuration register */ +#define STM32_OTGFS_CID_OFFSET 0x003c /* Core ID register */ +#define STM32_OTGFS_GLPMCFG_OFFSET 0x0054 /* LPM configuration register */ +#define STM32_OTGFS_GPWRDN_OFFSET 0x0058 /* Power down register */ +#define STM32_OTGFS_GADPCTL_OFSSET 0x0060 /* ADP timer, control and status register */ +#define STM32_OTGFS_HPTXFSIZ_OFFSET 0x0100 /* Host periodic transmit FIFO size register */ + +#define STM32_OTGFS_DIEPTXF_OFFSET(n) (0x0104+(((n)-1) << 2)) /* Host-mode control and status registers */ -#define STM32L4_OTGFS_HCFG_OFFSET 0x0400 /* Host configuration register */ -#define STM32L4_OTGFS_HFIR_OFFSET 0x0404 /* Host frame interval register */ -#define STM32L4_OTGFS_HFNUM_OFFSET 0x0408 /* Host frame number/frame time remaining register */ -#define STM32L4_OTGFS_HPTXSTS_OFFSET 0x0410 /* Host periodic transmit FIFO/queue status register */ -#define STM32L4_OTGFS_HAINT_OFFSET 0x0414 /* Host all channels interrupt register */ -#define STM32L4_OTGFS_HAINTMSK_OFFSET 0x0418 /* Host all channels interrupt mask register */ -#define STM32L4_OTGFS_HPRT_OFFSET 0x0440 /* Host port control and status register */ +#define STM32_OTGFS_HCFG_OFFSET 0x0400 /* Host configuration register */ +#define STM32_OTGFS_HFIR_OFFSET 0x0404 /* Host frame interval register */ +#define STM32_OTGFS_HFNUM_OFFSET 0x0408 /* Host frame number/frame time remaining register */ +#define STM32_OTGFS_HPTXSTS_OFFSET 0x0410 /* Host periodic transmit FIFO/queue status register */ +#define STM32_OTGFS_HAINT_OFFSET 0x0414 /* Host all channels interrupt register */ +#define STM32_OTGFS_HAINTMSK_OFFSET 0x0418 /* Host all channels interrupt mask register */ +#define STM32_OTGFS_HPRT_OFFSET 0x0440 /* Host port control and status register */ -#define STM32L4_OTGFS_CHAN_OFFSET(n) (0x500 + ((n) << 5) -#define STM32L4_OTGFS_HCCHAR_CHOFFSET 0x0000 /* Host channel characteristics register */ -#define STM32L4_OTGFS_HCINT_CHOFFSET 0x0008 /* Host channel interrupt register */ -#define STM32L4_OTGFS_HCINTMSK_CHOFFSET 0x000c /* Host channel interrupt mask register */ -#define STM32L4_OTGFS_HCTSIZ_CHOFFSET 0x0010 /* Host channel interrupt register */ +#define STM32_OTGFS_CHAN_OFFSET(n) (0x500 + ((n) << 5) +#define STM32_OTGFS_HCCHAR_CHOFFSET 0x0000 /* Host channel characteristics register */ +#define STM32_OTGFS_HCINT_CHOFFSET 0x0008 /* Host channel interrupt register */ +#define STM32_OTGFS_HCINTMSK_CHOFFSET 0x000c /* Host channel interrupt mask register */ +#define STM32_OTGFS_HCTSIZ_CHOFFSET 0x0010 /* Host channel interrupt register */ -#define STM32L4_OTGFS_HCCHAR_OFFSET(n) (0x500 + ((n) << 5)) +#define STM32_OTGFS_HCCHAR_OFFSET(n) (0x500 + ((n) << 5)) -#define STM32L4_OTGFS_HCINT_OFFSET(n) (0x508 + ((n) << 5)) +#define STM32_OTGFS_HCINT_OFFSET(n) (0x508 + ((n) << 5)) -#define STM32L4_OTGFS_HCINTMSK_OFFSET(n) (0x50c + ((n) << 5)) +#define STM32_OTGFS_HCINTMSK_OFFSET(n) (0x50c + ((n) << 5)) -#define STM32L4_OTGFS_HCTSIZ_OFFSET(n) (0x510 + ((n) << 5)) +#define STM32_OTGFS_HCTSIZ_OFFSET(n) (0x510 + ((n) << 5)) /* Device-mode control and status registers */ -#define STM32L4_OTGFS_DCFG_OFFSET 0x0800 /* Device configuration register */ -#define STM32L4_OTGFS_DCTL_OFFSET 0x0804 /* Device control register */ -#define STM32L4_OTGFS_DSTS_OFFSET 0x0808 /* Device status register */ -#define STM32L4_OTGFS_DIEPMSK_OFFSET 0x0810 /* Device IN endpoint common interrupt mask register */ -#define STM32L4_OTGFS_DOEPMSK_OFFSET 0x0814 /* Device OUT endpoint common interrupt mask register */ -#define STM32L4_OTGFS_DAINT_OFFSET 0x0818 /* Device all endpoints interrupt register */ -#define STM32L4_OTGFS_DAINTMSK_OFFSET 0x081c /* All endpoints interrupt mask register */ -#define STM32L4_OTGFS_DVBUSDIS_OFFSET 0x0828 /* Device VBUS discharge time register */ -#define STM32L4_OTGFS_DVBUSPULSE_OFFSET 0x082c /* Device VBUS pulsing time register */ -#define STM32L4_OTGFS_DIEPEMPMSK_OFFSET 0x0834 /* Device IN endpoint FIFO empty interrupt mask register */ +#define STM32_OTGFS_DCFG_OFFSET 0x0800 /* Device configuration register */ +#define STM32_OTGFS_DCTL_OFFSET 0x0804 /* Device control register */ +#define STM32_OTGFS_DSTS_OFFSET 0x0808 /* Device status register */ +#define STM32_OTGFS_DIEPMSK_OFFSET 0x0810 /* Device IN endpoint common interrupt mask register */ +#define STM32_OTGFS_DOEPMSK_OFFSET 0x0814 /* Device OUT endpoint common interrupt mask register */ +#define STM32_OTGFS_DAINT_OFFSET 0x0818 /* Device all endpoints interrupt register */ +#define STM32_OTGFS_DAINTMSK_OFFSET 0x081c /* All endpoints interrupt mask register */ +#define STM32_OTGFS_DVBUSDIS_OFFSET 0x0828 /* Device VBUS discharge time register */ +#define STM32_OTGFS_DVBUSPULSE_OFFSET 0x082c /* Device VBUS pulsing time register */ +#define STM32_OTGFS_DIEPEMPMSK_OFFSET 0x0834 /* Device IN endpoint FIFO empty interrupt mask register */ -#define STM32L4_OTGFS_DIEP_OFFSET(n) (0x0900 + ((n) << 5)) -#define STM32L4_OTGFS_DIEPCTL_EPOFFSET 0x0000 /* Device endpoint control register */ -#define STM32L4_OTGFS_DIEPINT_EPOFFSET 0x0008 /* Device endpoint interrupt register */ -#define STM32L4_OTGFS_DIEPTSIZ_EPOFFSET 0x0010 /* Device IN endpoint transfer size register */ -#define STM32L4_OTGFS_DTXFSTS_EPOFFSET 0x0018 /* Device IN endpoint transmit FIFO status register */ +#define STM32_OTGFS_DIEP_OFFSET(n) (0x0900 + ((n) << 5)) +#define STM32_OTGFS_DIEPCTL_EPOFFSET 0x0000 /* Device endpoint control register */ +#define STM32_OTGFS_DIEPINT_EPOFFSET 0x0008 /* Device endpoint interrupt register */ +#define STM32_OTGFS_DIEPTSIZ_EPOFFSET 0x0010 /* Device IN endpoint transfer size register */ +#define STM32_OTGFS_DTXFSTS_EPOFFSET 0x0018 /* Device IN endpoint transmit FIFO status register */ -#define STM32L4_OTGFS_DIEPCTL_OFFSET(n) (0x0900 + ((n) << 5)) +#define STM32_OTGFS_DIEPCTL_OFFSET(n) (0x0900 + ((n) << 5)) -#define STM32L4_OTGFS_DIEPINT_OFFSET(n) (0x0908 + ((n) << 5)) +#define STM32_OTGFS_DIEPINT_OFFSET(n) (0x0908 + ((n) << 5)) -#define STM32L4_OTGFS_DIEPTSIZ_OFFSET(n) (0x910 + ((n) << 5)) +#define STM32_OTGFS_DIEPTSIZ_OFFSET(n) (0x910 + ((n) << 5)) -#define STM32L4_OTGFS_DTXFSTS_OFFSET(n) (0x0918 + ((n) << 5)) +#define STM32_OTGFS_DTXFSTS_OFFSET(n) (0x0918 + ((n) << 5)) -#define STM32L4_OTGFS_DOEP_OFFSET(n) (0x0b00 + ((n) << 5)) -#define STM32L4_OTGFS_DOEPCTL_EPOFFSET 0x0000 /* Device control OUT endpoint 0 control register */ -#define STM32L4_OTGFS_DOEPINT_EPOFFSET 0x0008 /* Device endpoint-x interrupt register */ -#define STM32L4_OTGFS_DOEPTSIZ_EPOFFSET 0x0010 /* Device endpoint OUT transfer size register */ +#define STM32_OTGFS_DOEP_OFFSET(n) (0x0b00 + ((n) << 5)) +#define STM32_OTGFS_DOEPCTL_EPOFFSET 0x0000 /* Device control OUT endpoint 0 control register */ +#define STM32_OTGFS_DOEPINT_EPOFFSET 0x0008 /* Device endpoint-x interrupt register */ +#define STM32_OTGFS_DOEPTSIZ_EPOFFSET 0x0010 /* Device endpoint OUT transfer size register */ -#define STM32L4_OTGFS_DOEPCTL_OFFSET(n) (0x0b00 + ((n) << 5)) +#define STM32_OTGFS_DOEPCTL_OFFSET(n) (0x0b00 + ((n) << 5)) -#define STM32L4_OTGFS_DOEPINT_OFFSET(n) (0x0b08 + ((n) << 5)) +#define STM32_OTGFS_DOEPINT_OFFSET(n) (0x0b08 + ((n) << 5)) -#define STM32L4_OTGFS_DOEPTSIZ_OFFSET(n) (0x0b10 + ((n) << 5)) +#define STM32_OTGFS_DOEPTSIZ_OFFSET(n) (0x0b10 + ((n) << 5)) /* Power and clock gating registers */ -#define STM32L4_OTGFS_PCGCCTL_OFFSET 0x0e00 /* Power and clock gating control register */ +#define STM32_OTGFS_PCGCCTL_OFFSET 0x0e00 /* Power and clock gating control register */ /* Data FIFO (DFIFO) access registers */ -#define STM32L4_OTGFS_DFIFO_DEP_OFFSET(n) (0x1000 + ((n) << 12)) -#define STM32L4_OTGFS_DFIFO_HCH_OFFSET(n) (0x1000 + ((n) << 12)) +#define STM32_OTGFS_DFIFO_DEP_OFFSET(n) (0x1000 + ((n) << 12)) +#define STM32_OTGFS_DFIFO_HCH_OFFSET(n) (0x1000 + ((n) << 12)) /* Register Addresses *******************************************************/ -#define STM32L4_OTGFS_GOTGCTL (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GOTGCTL_OFFSET) -#define STM32L4_OTGFS_GOTGINT (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GOTGINT_OFFSET) -#define STM32L4_OTGFS_GAHBCFG (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GAHBCFG_OFFSET) -#define STM32L4_OTGFS_GUSBCFG (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GUSBCFG_OFFSET) -#define STM32L4_OTGFS_GRSTCTL (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GRSTCTL_OFFSET) -#define STM32L4_OTGFS_GINTSTS (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GINTSTS_OFFSET) -#define STM32L4_OTGFS_GINTMSK (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GINTMSK_OFFSET) -#define STM32L4_OTGFS_GRXSTSR (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GRXSTSR_OFFSET) -#define STM32L4_OTGFS_GRXSTSP (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GRXSTSP_OFFSET) -#define STM32L4_OTGFS_GRXFSIZ (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GRXFSIZ_OFFSET) -#define STM32L4_OTGFS_HNPTXFSIZ (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HNPTXFSIZ_OFFSET) -#define STM32L4_OTGFS_DIEPTXF0 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DIEPTXF0_OFFSET) -#define STM32L4_OTGFS_HNPTXSTS (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HNPTXSTS_OFFSET) -#define STM32L4_OTGFS_GCCFG (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GCCFG_OFFSET) -#define STM32L4_OTGFS_CID (STM32L4_OTGFS_BASE+STM32L4_OTGFS_CID_OFFSET) -#define STM32L4_OTGFS_GLPMCFG (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GLPMCFG_OFFSET) -#define STM32L4_OTGFS_GPWRDN (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GPWRDN_OFFSET) -#define STM32L4_OTGFS_GADPCTL (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GADPCTL_OFSSET) -#define STM32L4_OTGFS_HPTXFSIZ (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HPTXFSIZ_OFFSET) - -#define STM32L4_OTGFS_DIEPTXF(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DIEPTXF_OFFSET(n)) +#define STM32_OTGFS_GOTGCTL (STM32_OTGFS_BASE+STM32_OTGFS_GOTGCTL_OFFSET) +#define STM32_OTGFS_GOTGINT (STM32_OTGFS_BASE+STM32_OTGFS_GOTGINT_OFFSET) +#define STM32_OTGFS_GAHBCFG (STM32_OTGFS_BASE+STM32_OTGFS_GAHBCFG_OFFSET) +#define STM32_OTGFS_GUSBCFG (STM32_OTGFS_BASE+STM32_OTGFS_GUSBCFG_OFFSET) +#define STM32_OTGFS_GRSTCTL (STM32_OTGFS_BASE+STM32_OTGFS_GRSTCTL_OFFSET) +#define STM32_OTGFS_GINTSTS (STM32_OTGFS_BASE+STM32_OTGFS_GINTSTS_OFFSET) +#define STM32_OTGFS_GINTMSK (STM32_OTGFS_BASE+STM32_OTGFS_GINTMSK_OFFSET) +#define STM32_OTGFS_GRXSTSR (STM32_OTGFS_BASE+STM32_OTGFS_GRXSTSR_OFFSET) +#define STM32_OTGFS_GRXSTSP (STM32_OTGFS_BASE+STM32_OTGFS_GRXSTSP_OFFSET) +#define STM32_OTGFS_GRXFSIZ (STM32_OTGFS_BASE+STM32_OTGFS_GRXFSIZ_OFFSET) +#define STM32_OTGFS_HNPTXFSIZ (STM32_OTGFS_BASE+STM32_OTGFS_HNPTXFSIZ_OFFSET) +#define STM32_OTGFS_DIEPTXF0 (STM32_OTGFS_BASE+STM32_OTGFS_DIEPTXF0_OFFSET) +#define STM32_OTGFS_HNPTXSTS (STM32_OTGFS_BASE+STM32_OTGFS_HNPTXSTS_OFFSET) +#define STM32_OTGFS_GCCFG (STM32_OTGFS_BASE+STM32_OTGFS_GCCFG_OFFSET) +#define STM32_OTGFS_CID (STM32_OTGFS_BASE+STM32_OTGFS_CID_OFFSET) +#define STM32_OTGFS_GLPMCFG (STM32_OTGFS_BASE+STM32_OTGFS_GLPMCFG_OFFSET) +#define STM32_OTGFS_GPWRDN (STM32_OTGFS_BASE+STM32_OTGFS_GPWRDN_OFFSET) +#define STM32_OTGFS_GADPCTL (STM32_OTGFS_BASE+STM32_OTGFS_GADPCTL_OFSSET) +#define STM32_OTGFS_HPTXFSIZ (STM32_OTGFS_BASE+STM32_OTGFS_HPTXFSIZ_OFFSET) + +#define STM32_OTGFS_DIEPTXF(n) (STM32_OTGFS_BASE+STM32_OTGFS_DIEPTXF_OFFSET(n)) /* Host-mode control and status registers */ -#define STM32L4_OTGFS_HCFG (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HCFG_OFFSET) -#define STM32L4_OTGFS_HFIR (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HFIR_OFFSET) -#define STM32L4_OTGFS_HFNUM (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HFNUM_OFFSET) -#define STM32L4_OTGFS_HPTXSTS (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HPTXSTS_OFFSET) -#define STM32L4_OTGFS_HAINT (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HAINT_OFFSET) -#define STM32L4_OTGFS_HAINTMSK (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HAINTMSK_OFFSET) -#define STM32L4_OTGFS_HPRT (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HPRT_OFFSET) +#define STM32_OTGFS_HCFG (STM32_OTGFS_BASE+STM32_OTGFS_HCFG_OFFSET) +#define STM32_OTGFS_HFIR (STM32_OTGFS_BASE+STM32_OTGFS_HFIR_OFFSET) +#define STM32_OTGFS_HFNUM (STM32_OTGFS_BASE+STM32_OTGFS_HFNUM_OFFSET) +#define STM32_OTGFS_HPTXSTS (STM32_OTGFS_BASE+STM32_OTGFS_HPTXSTS_OFFSET) +#define STM32_OTGFS_HAINT (STM32_OTGFS_BASE+STM32_OTGFS_HAINT_OFFSET) +#define STM32_OTGFS_HAINTMSK (STM32_OTGFS_BASE+STM32_OTGFS_HAINTMSK_OFFSET) +#define STM32_OTGFS_HPRT (STM32_OTGFS_BASE+STM32_OTGFS_HPRT_OFFSET) -#define STM32L4_OTGFS_CHAN(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_CHAN_OFFSET(n)) +#define STM32_OTGFS_CHAN(n) (STM32_OTGFS_BASE+STM32_OTGFS_CHAN_OFFSET(n)) -#define STM32L4_OTGFS_HCCHAR(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HCCHAR_OFFSET(n)) +#define STM32_OTGFS_HCCHAR(n) (STM32_OTGFS_BASE+STM32_OTGFS_HCCHAR_OFFSET(n)) -#define STM32L4_OTGFS_HCINT(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HCINT_OFFSET(n)) +#define STM32_OTGFS_HCINT(n) (STM32_OTGFS_BASE+STM32_OTGFS_HCINT_OFFSET(n)) -#define STM32L4_OTGFS_HCINTMSK(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HCINTMSK_OFFSET(n)) +#define STM32_OTGFS_HCINTMSK(n) (STM32_OTGFS_BASE+STM32_OTGFS_HCINTMSK_OFFSET(n)) -#define STM32L4_OTGFS_HCTSIZ(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HCTSIZ_OFFSET(n)) +#define STM32_OTGFS_HCTSIZ(n) (STM32_OTGFS_BASE+STM32_OTGFS_HCTSIZ_OFFSET(n)) /* Device-mode control and status registers */ -#define STM32L4_OTGFS_DCFG (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DCFG_OFFSET) -#define STM32L4_OTGFS_DCTL (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DCTL_OFFSET) -#define STM32L4_OTGFS_DSTS (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DSTS_OFFSET) -#define STM32L4_OTGFS_DIEPMSK (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DIEPMSK_OFFSET) -#define STM32L4_OTGFS_DOEPMSK (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DOEPMSK_OFFSET) -#define STM32L4_OTGFS_DAINT (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DAINT_OFFSET) -#define STM32L4_OTGFS_DAINTMSK (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DAINTMSK_OFFSET) -#define STM32L4_OTGFS_DVBUSDIS (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DVBUSDIS_OFFSET) -#define STM32L4_OTGFS_DVBUSPULSE (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DVBUSPULSE_OFFSET) -#define STM32L4_OTGFS_DIEPEMPMSK (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DIEPEMPMSK_OFFSET) +#define STM32_OTGFS_DCFG (STM32_OTGFS_BASE+STM32_OTGFS_DCFG_OFFSET) +#define STM32_OTGFS_DCTL (STM32_OTGFS_BASE+STM32_OTGFS_DCTL_OFFSET) +#define STM32_OTGFS_DSTS (STM32_OTGFS_BASE+STM32_OTGFS_DSTS_OFFSET) +#define STM32_OTGFS_DIEPMSK (STM32_OTGFS_BASE+STM32_OTGFS_DIEPMSK_OFFSET) +#define STM32_OTGFS_DOEPMSK (STM32_OTGFS_BASE+STM32_OTGFS_DOEPMSK_OFFSET) +#define STM32_OTGFS_DAINT (STM32_OTGFS_BASE+STM32_OTGFS_DAINT_OFFSET) +#define STM32_OTGFS_DAINTMSK (STM32_OTGFS_BASE+STM32_OTGFS_DAINTMSK_OFFSET) +#define STM32_OTGFS_DVBUSDIS (STM32_OTGFS_BASE+STM32_OTGFS_DVBUSDIS_OFFSET) +#define STM32_OTGFS_DVBUSPULSE (STM32_OTGFS_BASE+STM32_OTGFS_DVBUSPULSE_OFFSET) +#define STM32_OTGFS_DIEPEMPMSK (STM32_OTGFS_BASE+STM32_OTGFS_DIEPEMPMSK_OFFSET) -#define STM32L4_OTGFS_DIEP(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DIEP_OFFSET(n)) +#define STM32_OTGFS_DIEP(n) (STM32_OTGFS_BASE+STM32_OTGFS_DIEP_OFFSET(n)) -#define STM32L4_OTGFS_DIEPCTL(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DIEPCTL_OFFSET(n)) +#define STM32_OTGFS_DIEPCTL(n) (STM32_OTGFS_BASE+STM32_OTGFS_DIEPCTL_OFFSET(n)) -#define STM32L4_OTGFS_DIEPINT(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DIEPINT_OFFSET(n)) +#define STM32_OTGFS_DIEPINT(n) (STM32_OTGFS_BASE+STM32_OTGFS_DIEPINT_OFFSET(n)) -#define STM32L4_OTGFS_DIEPTSIZ(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DIEPTSIZ_OFFSET(n)) +#define STM32_OTGFS_DIEPTSIZ(n) (STM32_OTGFS_BASE+STM32_OTGFS_DIEPTSIZ_OFFSET(n)) -#define STM32L4_OTGFS_DTXFSTS(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DTXFSTS_OFFSET(n)) +#define STM32_OTGFS_DTXFSTS(n) (STM32_OTGFS_BASE+STM32_OTGFS_DTXFSTS_OFFSET(n)) -#define STM32L4_OTGFS_DOEP(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DOEP_OFFSET(n)) +#define STM32_OTGFS_DOEP(n) (STM32_OTGFS_BASE+STM32_OTGFS_DOEP_OFFSET(n)) -#define STM32L4_OTGFS_DOEPCTL(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DOEPCTL_OFFSET(n)) +#define STM32_OTGFS_DOEPCTL(n) (STM32_OTGFS_BASE+STM32_OTGFS_DOEPCTL_OFFSET(n)) -#define STM32L4_OTGFS_DOEPINT(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DOEPINT_OFFSET(n)) +#define STM32_OTGFS_DOEPINT(n) (STM32_OTGFS_BASE+STM32_OTGFS_DOEPINT_OFFSET(n)) -#define STM32L4_OTGFS_DOEPTSIZ(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DOEPTSIZ_OFFSET(n)) +#define STM32_OTGFS_DOEPTSIZ(n) (STM32_OTGFS_BASE+STM32_OTGFS_DOEPTSIZ_OFFSET(n)) /* Power and clock gating registers */ -#define STM32L4_OTGFS_PCGCCTL (STM32L4_OTGFS_BASE+STM32L4_OTGFS_PCGCCTL_OFFSET) +#define STM32_OTGFS_PCGCCTL (STM32_OTGFS_BASE+STM32_OTGFS_PCGCCTL_OFFSET) /* Data FIFO (DFIFO) access registers */ -#define STM32L4_OTGFS_DFIFO_DEP(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DFIFO_DEP_OFFSET(n)) -#define STM32L4_OTGFS_DFIFO_HCH(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DFIFO_HCH_OFFSET(n)) +#define STM32_OTGFS_DFIFO_DEP(n) (STM32_OTGFS_BASE+STM32_OTGFS_DFIFO_DEP_OFFSET(n)) +#define STM32_OTGFS_DFIFO_HCH(n) (STM32_OTGFS_BASE+STM32_OTGFS_DFIFO_HCH_OFFSET(n)) /* Register Bitfield Definitions ********************************************/ @@ -741,7 +741,7 @@ #define OTGFS_DSTS_SOFFN_ODD OTGFS_DSTS_SOFFN0 #define OTGFS_DSTS_DEVLNSTS_SHIFT (22) /* Bits 22-23: XXX */ #define OTGFS_DSTS_DEVLNSTS_MASK (0x3 << OTGFS_DSTS_DEVLNSTS_SHIFT) - /* Bits 24-31: Reserved, must be kept at reset value */ + /* Bits 24-31: Reserved, must be kept at reset value */ /* Device IN endpoint common interrupt mask register */ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4x5xx_rcc.h b/arch/arm/src/stm32l4/hardware/stm32l4x5xx_rcc.h index 218ac07c4bb84..5d81e280f129d 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4x5xx_rcc.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4x5xx_rcc.h @@ -29,7 +29,7 @@ #include -#if defined(CONFIG_STM32L4_STM32L4X5) +#if defined(CONFIG_STM32_STM32L4X5) /**************************************************************************** * Pre-processor Definitions @@ -37,69 +37,69 @@ /* Register Offsets *********************************************************/ -#define STM32L4_RCC_CR_OFFSET 0x0000 /* Clock control register */ -#define STM32L4_RCC_ICSCR_OFFSET 0x0004 /* Internal clock sources calibration register */ -#define STM32L4_RCC_CFGR_OFFSET 0x0008 /* Clock configuration register */ -#define STM32L4_RCC_PLLCFG_OFFSET 0x000c /* PLL configuration register */ -#define STM32L4_RCC_PLLSAI1CFG_OFFSET 0x0010 /* PLLSAI1 configuration register */ -#define STM32L4_RCC_PLLSAI2CFG_OFFSET 0x0014 /* PLLSAI2 configuration register */ -#define STM32L4_RCC_CIER_OFFSET 0x0018 /* Clock interrupt enable register */ -#define STM32L4_RCC_CIFR_OFFSET 0x001c /* Clock interrupt flag register */ -#define STM32L4_RCC_CICR_OFFSET 0x0020 /* Clock interrupt clear register */ -#define STM32L4_RCC_AHB1RSTR_OFFSET 0x0028 /* AHB1 peripheral reset register */ -#define STM32L4_RCC_AHB2RSTR_OFFSET 0x002c /* AHB2 peripheral reset register */ -#define STM32L4_RCC_AHB3RSTR_OFFSET 0x0030 /* AHB3 peripheral reset register */ -#define STM32L4_RCC_APB1RSTR1_OFFSET 0x0038 /* APB1 Peripheral reset register 1 */ -#define STM32L4_RCC_APB1RSTR2_OFFSET 0x003c /* APB1 Peripheral reset register 2 */ -#define STM32L4_RCC_APB2RSTR_OFFSET 0x0040 /* APB2 Peripheral reset register */ -#define STM32L4_RCC_AHB1ENR_OFFSET 0x0048 /* AHB1 Peripheral Clock enable register */ -#define STM32L4_RCC_AHB2ENR_OFFSET 0x004c /* AHB2 Peripheral Clock enable register */ -#define STM32L4_RCC_AHB3ENR_OFFSET 0x0050 /* AHB3 Peripheral Clock enable register */ -#define STM32L4_RCC_APB1ENR1_OFFSET 0x0058 /* APB1 Peripheral Clock enable register 1 */ -#define STM32L4_RCC_APB1ENR2_OFFSET 0x005c /* APB1 Peripheral Clock enable register 2 */ -#define STM32L4_RCC_APB2ENR_OFFSET 0x0060 /* APB2 Peripheral Clock enable register */ -#define STM32L4_RCC_AHB1SMENR_OFFSET 0x0068 /* RCC AHB1 low power mode peripheral clock enable register */ -#define STM32L4_RCC_AHB2SMENR_OFFSET 0x006c /* RCC AHB2 low power mode peripheral clock enable register */ -#define STM32L4_RCC_AHB3SMENR_OFFSET 0x0070 /* RCC AHB3 low power mode peripheral clock enable register */ -#define STM32L4_RCC_APB1SMENR1_OFFSET 0x0078 /* RCC APB1 low power mode peripheral clock enable register 1 */ -#define STM32L4_RCC_APB1SMENR2_OFFSET 0x007c /* RCC APB1 low power mode peripheral clock enable register 2 */ -#define STM32L4_RCC_APB2SMENR_OFFSET 0x0080 /* RCC APB2 low power mode peripheral clock enable register */ -#define STM32L4_RCC_CCIPR_OFFSET 0x0088 /* Peripherals independent clock configuration register 1 */ -#define STM32L4_RCC_BDCR_OFFSET 0x0090 /* Backup domain control register */ -#define STM32L4_RCC_CSR_OFFSET 0x0094 /* Control/status register */ +#define STM32_RCC_CR_OFFSET 0x0000 /* Clock control register */ +#define STM32_RCC_ICSCR_OFFSET 0x0004 /* Internal clock sources calibration register */ +#define STM32_RCC_CFGR_OFFSET 0x0008 /* Clock configuration register */ +#define STM32_RCC_PLLCFG_OFFSET 0x000c /* PLL configuration register */ +#define STM32_RCC_PLLSAI1CFG_OFFSET 0x0010 /* PLLSAI1 configuration register */ +#define STM32_RCC_PLLSAI2CFG_OFFSET 0x0014 /* PLLSAI2 configuration register */ +#define STM32_RCC_CIER_OFFSET 0x0018 /* Clock interrupt enable register */ +#define STM32_RCC_CIFR_OFFSET 0x001c /* Clock interrupt flag register */ +#define STM32_RCC_CICR_OFFSET 0x0020 /* Clock interrupt clear register */ +#define STM32_RCC_AHB1RSTR_OFFSET 0x0028 /* AHB1 peripheral reset register */ +#define STM32_RCC_AHB2RSTR_OFFSET 0x002c /* AHB2 peripheral reset register */ +#define STM32_RCC_AHB3RSTR_OFFSET 0x0030 /* AHB3 peripheral reset register */ +#define STM32_RCC_APB1RSTR1_OFFSET 0x0038 /* APB1 Peripheral reset register 1 */ +#define STM32_RCC_APB1RSTR2_OFFSET 0x003c /* APB1 Peripheral reset register 2 */ +#define STM32_RCC_APB2RSTR_OFFSET 0x0040 /* APB2 Peripheral reset register */ +#define STM32_RCC_AHB1ENR_OFFSET 0x0048 /* AHB1 Peripheral Clock enable register */ +#define STM32_RCC_AHB2ENR_OFFSET 0x004c /* AHB2 Peripheral Clock enable register */ +#define STM32_RCC_AHB3ENR_OFFSET 0x0050 /* AHB3 Peripheral Clock enable register */ +#define STM32_RCC_APB1ENR1_OFFSET 0x0058 /* APB1 Peripheral Clock enable register 1 */ +#define STM32_RCC_APB1ENR2_OFFSET 0x005c /* APB1 Peripheral Clock enable register 2 */ +#define STM32_RCC_APB2ENR_OFFSET 0x0060 /* APB2 Peripheral Clock enable register */ +#define STM32_RCC_AHB1SMENR_OFFSET 0x0068 /* RCC AHB1 low power mode peripheral clock enable register */ +#define STM32_RCC_AHB2SMENR_OFFSET 0x006c /* RCC AHB2 low power mode peripheral clock enable register */ +#define STM32_RCC_AHB3SMENR_OFFSET 0x0070 /* RCC AHB3 low power mode peripheral clock enable register */ +#define STM32_RCC_APB1SMENR1_OFFSET 0x0078 /* RCC APB1 low power mode peripheral clock enable register 1 */ +#define STM32_RCC_APB1SMENR2_OFFSET 0x007c /* RCC APB1 low power mode peripheral clock enable register 2 */ +#define STM32_RCC_APB2SMENR_OFFSET 0x0080 /* RCC APB2 low power mode peripheral clock enable register */ +#define STM32_RCC_CCIPR_OFFSET 0x0088 /* Peripherals independent clock configuration register 1 */ +#define STM32_RCC_BDCR_OFFSET 0x0090 /* Backup domain control register */ +#define STM32_RCC_CSR_OFFSET 0x0094 /* Control/status register */ /* Register Addresses *******************************************************/ -#define STM32L4_RCC_CR (STM32L4_RCC_BASE+STM32L4_RCC_CR_OFFSET) -#define STM32L4_RCC_ICSCR (STM32L4_RCC_BASE+STM32L4_RCC_ICSCR_OFFSET) -#define STM32L4_RCC_CFGR (STM32L4_RCC_BASE+STM32L4_RCC_CFGR_OFFSET) -#define STM32L4_RCC_PLLCFG (STM32L4_RCC_BASE+STM32L4_RCC_PLLCFG_OFFSET) -#define STM32L4_RCC_PLLSAI1CFG (STM32L4_RCC_BASE+STM32L4_RCC_PLLSAI1CFG_OFFSET) -#define STM32L4_RCC_PLLSAI2CFG (STM32L4_RCC_BASE+STM32L4_RCC_PLLSAI2CFG_OFFSET) -#define STM32L4_RCC_CIER (STM32L4_RCC_BASE+STM32L4_RCC_CIER_OFFSET) -#define STM32L4_RCC_CIFR (STM32L4_RCC_BASE+STM32L4_RCC_CIFR_OFFSET) -#define STM32L4_RCC_CICR (STM32L4_RCC_BASE+STM32L4_RCC_CICR_OFFSET) -#define STM32L4_RCC_AHB1RSTR (STM32L4_RCC_BASE+STM32L4_RCC_AHB1RSTR_OFFSET) -#define STM32L4_RCC_AHB2RSTR (STM32L4_RCC_BASE+STM32L4_RCC_AHB2RSTR_OFFSET) -#define STM32L4_RCC_AHB3RSTR (STM32L4_RCC_BASE+STM32L4_RCC_AHB3RSTR_OFFSET) -#define STM32L4_RCC_APB1RSTR1 (STM32L4_RCC_BASE+STM32L4_RCC_APB1RSTR1_OFFSET) -#define STM32L4_RCC_APB1RSTR2 (STM32L4_RCC_BASE+STM32L4_RCC_APB1RSTR2_OFFSET) -#define STM32L4_RCC_APB2RSTR (STM32L4_RCC_BASE+STM32L4_RCC_APB2RSTR_OFFSET) -#define STM32L4_RCC_AHB1ENR (STM32L4_RCC_BASE+STM32L4_RCC_AHB1ENR_OFFSET) -#define STM32L4_RCC_AHB2ENR (STM32L4_RCC_BASE+STM32L4_RCC_AHB2ENR_OFFSET) -#define STM32L4_RCC_AHB3ENR (STM32L4_RCC_BASE+STM32L4_RCC_AHB3ENR_OFFSET) -#define STM32L4_RCC_APB1ENR1 (STM32L4_RCC_BASE+STM32L4_RCC_APB1ENR1_OFFSET) -#define STM32L4_RCC_APB1ENR2 (STM32L4_RCC_BASE+STM32L4_RCC_APB1ENR2_OFFSET) -#define STM32L4_RCC_APB2ENR (STM32L4_RCC_BASE+STM32L4_RCC_APB2ENR_OFFSET) -#define STM32L4_RCC_AHB1SMENR (STM32L4_RCC_BASE+STM32L4_RCC_AHB1SMENR_OFFSET) -#define STM32L4_RCC_AHB2SMENR (STM32L4_RCC_BASE+STM32L4_RCC_AHB2SMENR_OFFSET) -#define STM32L4_RCC_AHB3SMENR (STM32L4_RCC_BASE+STM32L4_RCC_AHB3SMENR_OFFSET) -#define STM32L4_RCC_APB1SMENR1 (STM32L4_RCC_BASE+STM32L4_RCC_APB1SMENR1_OFFSET) -#define STM32L4_RCC_APB1SMENR2 (STM32L4_RCC_BASE+STM32L4_RCC_APB1SMENR2_OFFSET) -#define STM32L4_RCC_APB2SMENR (STM32L4_RCC_BASE+STM32L4_RCC_APB2SMENR_OFFSET) -#define STM32L4_RCC_CCIPR (STM32L4_RCC_BASE+STM32L4_RCC_CCIPR_OFFSET) -#define STM32L4_RCC_BDCR (STM32L4_RCC_BASE+STM32L4_RCC_BDCR_OFFSET) -#define STM32L4_RCC_CSR (STM32L4_RCC_BASE+STM32L4_RCC_CSR_OFFSET) +#define STM32_RCC_CR (STM32_RCC_BASE+STM32_RCC_CR_OFFSET) +#define STM32_RCC_ICSCR (STM32_RCC_BASE+STM32_RCC_ICSCR_OFFSET) +#define STM32_RCC_CFGR (STM32_RCC_BASE+STM32_RCC_CFGR_OFFSET) +#define STM32_RCC_PLLCFG (STM32_RCC_BASE+STM32_RCC_PLLCFG_OFFSET) +#define STM32_RCC_PLLSAI1CFG (STM32_RCC_BASE+STM32_RCC_PLLSAI1CFG_OFFSET) +#define STM32_RCC_PLLSAI2CFG (STM32_RCC_BASE+STM32_RCC_PLLSAI2CFG_OFFSET) +#define STM32_RCC_CIER (STM32_RCC_BASE+STM32_RCC_CIER_OFFSET) +#define STM32_RCC_CIFR (STM32_RCC_BASE+STM32_RCC_CIFR_OFFSET) +#define STM32_RCC_CICR (STM32_RCC_BASE+STM32_RCC_CICR_OFFSET) +#define STM32_RCC_AHB1RSTR (STM32_RCC_BASE+STM32_RCC_AHB1RSTR_OFFSET) +#define STM32_RCC_AHB2RSTR (STM32_RCC_BASE+STM32_RCC_AHB2RSTR_OFFSET) +#define STM32_RCC_AHB3RSTR (STM32_RCC_BASE+STM32_RCC_AHB3RSTR_OFFSET) +#define STM32_RCC_APB1RSTR1 (STM32_RCC_BASE+STM32_RCC_APB1RSTR1_OFFSET) +#define STM32_RCC_APB1RSTR2 (STM32_RCC_BASE+STM32_RCC_APB1RSTR2_OFFSET) +#define STM32_RCC_APB2RSTR (STM32_RCC_BASE+STM32_RCC_APB2RSTR_OFFSET) +#define STM32_RCC_AHB1ENR (STM32_RCC_BASE+STM32_RCC_AHB1ENR_OFFSET) +#define STM32_RCC_AHB2ENR (STM32_RCC_BASE+STM32_RCC_AHB2ENR_OFFSET) +#define STM32_RCC_AHB3ENR (STM32_RCC_BASE+STM32_RCC_AHB3ENR_OFFSET) +#define STM32_RCC_APB1ENR1 (STM32_RCC_BASE+STM32_RCC_APB1ENR1_OFFSET) +#define STM32_RCC_APB1ENR2 (STM32_RCC_BASE+STM32_RCC_APB1ENR2_OFFSET) +#define STM32_RCC_APB2ENR (STM32_RCC_BASE+STM32_RCC_APB2ENR_OFFSET) +#define STM32_RCC_AHB1SMENR (STM32_RCC_BASE+STM32_RCC_AHB1SMENR_OFFSET) +#define STM32_RCC_AHB2SMENR (STM32_RCC_BASE+STM32_RCC_AHB2SMENR_OFFSET) +#define STM32_RCC_AHB3SMENR (STM32_RCC_BASE+STM32_RCC_AHB3SMENR_OFFSET) +#define STM32_RCC_APB1SMENR1 (STM32_RCC_BASE+STM32_RCC_APB1SMENR1_OFFSET) +#define STM32_RCC_APB1SMENR2 (STM32_RCC_BASE+STM32_RCC_APB1SMENR2_OFFSET) +#define STM32_RCC_APB2SMENR (STM32_RCC_BASE+STM32_RCC_APB2SMENR_OFFSET) +#define STM32_RCC_CCIPR (STM32_RCC_BASE+STM32_RCC_CCIPR_OFFSET) +#define STM32_RCC_BDCR (STM32_RCC_BASE+STM32_RCC_BDCR_OFFSET) +#define STM32_RCC_CSR (STM32_RCC_BASE+STM32_RCC_CSR_OFFSET) /* Register Bitfield Definitions ********************************************/ @@ -721,5 +721,5 @@ #define RCC_CSR_WWDGRSTF (1 << 30) /* Bit 30: Window watchdog reset flag */ #define RCC_CSR_LPWRRSTF (1 << 31) /* Bit 31: Low-Power reset flag */ -#endif /* CONFIG_STM32L4_STM32L4X5 */ +#endif /* CONFIG_STM32_STM32L4X5 */ #endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4X5XX_RCC_H */ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4x5xx_syscfg.h b/arch/arm/src/stm32l4/hardware/stm32l4x5xx_syscfg.h index c092d69675ac4..40983ec429787 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4x5xx_syscfg.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4x5xx_syscfg.h @@ -30,7 +30,7 @@ #include #include "chip.h" -#if defined(CONFIG_STM32L4_STM32L4X5) +#if defined(CONFIG_STM32_STM32L4X5) /**************************************************************************** * Pre-processor Definitions @@ -38,33 +38,33 @@ /* Register Offsets *********************************************************/ -#define STM32L4_SYSCFG_MEMRMP_OFFSET 0x0000 /* SYSCFG memory remap register */ -#define STM32L4_SYSCFG_CFGR1_OFFSET 0x0004 /* SYSCFG configuration register 1 */ +#define STM32_SYSCFG_MEMRMP_OFFSET 0x0000 /* SYSCFG memory remap register */ +#define STM32_SYSCFG_CFGR1_OFFSET 0x0004 /* SYSCFG configuration register 1 */ -#define STM32L4_SYSCFG_EXTICR_OFFSET(p) (0x0008 + ((p) & 0x000c)) /* Registers are displaced by 4! */ +#define STM32_SYSCFG_EXTICR_OFFSET(p) (0x0008 + ((p) & 0x000c)) /* Registers are displaced by 4! */ -#define STM32L4_SYSCFG_EXTICR1_OFFSET 0x0008 /* SYSCFG external interrupt configuration register 1 */ -#define STM32L4_SYSCFG_EXTICR2_OFFSET 0x000c /* SYSCFG external interrupt configuration register 2 */ -#define STM32L4_SYSCFG_EXTICR3_OFFSET 0x0010 /* SYSCFG external interrupt configuration register 3 */ -#define STM32L4_SYSCFG_EXTICR4_OFFSET 0x0014 /* SYSCFG external interrupt configuration register 4 */ -#define STM32L4_SYSCFG_SCSR_OFFSET 0x0018 /* SYSCFG SRAM2 control and status register */ -#define STM32L4_SYSCFG_CFGR2_OFFSET 0x001c /* SYSCFG configuration register 2 */ -#define STM32L4_SYSCFG_SWPR_OFFSET 0x0020 /* SYSCFG SRAM2 write protection register */ -#define STM32L4_SYSCFG_SKR_OFFSET 0x0024 /* SYSCFG SRAM2 key register */ +#define STM32_SYSCFG_EXTICR1_OFFSET 0x0008 /* SYSCFG external interrupt configuration register 1 */ +#define STM32_SYSCFG_EXTICR2_OFFSET 0x000c /* SYSCFG external interrupt configuration register 2 */ +#define STM32_SYSCFG_EXTICR3_OFFSET 0x0010 /* SYSCFG external interrupt configuration register 3 */ +#define STM32_SYSCFG_EXTICR4_OFFSET 0x0014 /* SYSCFG external interrupt configuration register 4 */ +#define STM32_SYSCFG_SCSR_OFFSET 0x0018 /* SYSCFG SRAM2 control and status register */ +#define STM32_SYSCFG_CFGR2_OFFSET 0x001c /* SYSCFG configuration register 2 */ +#define STM32_SYSCFG_SWPR_OFFSET 0x0020 /* SYSCFG SRAM2 write protection register */ +#define STM32_SYSCFG_SKR_OFFSET 0x0024 /* SYSCFG SRAM2 key register */ /* Register Addresses *******************************************************/ -#define STM32L4_SYSCFG_MEMRMP (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_MEMRMP_OFFSET) -#define STM32L4_SYSCFG_CFGR1 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_CFGR1_OFFSET) -#define STM32L4_SYSCFG_EXTICR(p) (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_EXTICR_OFFSET(p)) -#define STM32L4_SYSCFG_EXTICR1 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_EXTICR1_OFFSET) -#define STM32L4_SYSCFG_EXTICR2 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_EXTICR2_OFFSET) -#define STM32L4_SYSCFG_EXTICR3 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_EXTICR3_OFFSET) -#define STM32L4_SYSCFG_EXTICR4 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_EXTICR4_OFFSET) -#define STM32L4_SYSCFG_SCSR (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_SCSR_OFFSET) -#define STM32L4_SYSCFG_CFGR2 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_CFGR2_OFFSET) -#define STM32L4_SYSCFG_SWPR (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_SWPR_OFFSET) -#define STM32L4_SYSCFG_SKR (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_SKR_OFFSET) +#define STM32_SYSCFG_MEMRMP (STM32_SYSCFG_BASE+STM32_SYSCFG_MEMRMP_OFFSET) +#define STM32_SYSCFG_CFGR1 (STM32_SYSCFG_BASE+STM32_SYSCFG_CFGR1_OFFSET) +#define STM32_SYSCFG_EXTICR(p) (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR_OFFSET(p)) +#define STM32_SYSCFG_EXTICR1 (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR1_OFFSET) +#define STM32_SYSCFG_EXTICR2 (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR2_OFFSET) +#define STM32_SYSCFG_EXTICR3 (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR3_OFFSET) +#define STM32_SYSCFG_EXTICR4 (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR4_OFFSET) +#define STM32_SYSCFG_SCSR (STM32_SYSCFG_BASE+STM32_SYSCFG_SCSR_OFFSET) +#define STM32_SYSCFG_CFGR2 (STM32_SYSCFG_BASE+STM32_SYSCFG_CFGR2_OFFSET) +#define STM32_SYSCFG_SWPR (STM32_SYSCFG_BASE+STM32_SYSCFG_SWPR_OFFSET) +#define STM32_SYSCFG_SKR (STM32_SYSCFG_BASE+STM32_SYSCFG_SKR_OFFSET) /* Register Bitfield Definitions ********************************************/ @@ -163,5 +163,5 @@ #define SYSCFG_CFGR2_ECCL (1 << 3) /* Bit 3: ECC lock enable (same) */ #define SYSCFG_CFGR2_SPF (1 << 8) /* Bit 8: SRAM2 parity error flag */ -#endif /* CONFIG_STM32L4_STM32L4X5 */ +#endif /* CONFIG_STM32_STM32L4X5 */ #endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4X5XX_SYSCFG_H */ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4x6xx_dbgmcu.h b/arch/arm/src/stm32l4/hardware/stm32l4x6xx_dbgmcu.h index 34509ed7668fe..f8dc5a363257e 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4x6xx_dbgmcu.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4x6xx_dbgmcu.h @@ -81,14 +81,14 @@ #define DBGMCU_APB1_I2C2STOP (1 << 22) /* Bit 22: I2C2 SMBUS timeout mode stopped when Core is halted */ #define DBGMCU_APB1_I2C3STOP (1 << 23) /* Bit 23: I2C3 SMBUS timeout mode stopped when Core is halted */ #define DBGMCU_APB1_CAN1STOP (1 << 25) /* Bit 25: CAN1 stopped when core is halted */ -#if defined(CONFIG_STM32L4_STM32L496XX) +#if defined(CONFIG_STM32_STM32L496XX) # define DBGMCU_APB1_CAN2STOP (1 << 26) /* Bit 26: CAN2 stopped when core is halted */ #endif #define DBGMCU_APB1_LPTIM1STOP (1 << 31) /* Bit 31: LPTIM1 stopper when core is halted */ /* Debug MCU APB1 freeze register 2 */ -#if defined(CONFIG_STM32L4_STM32L496XX) +#if defined(CONFIG_STM32_STM32L496XX) # define DBGMCU_APB1_FZ2_I2C4STOP (1 << 1) /* Bit 1: I2C4 SMBUS timeout mode stopped when Core is halted */ #endif #define DBGMCU_APB1_FZ2_LPTIM2STOP (1 << 5) /* Bit 5: LPTIM2 stopper when core is halted */ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4x6xx_dma.h b/arch/arm/src/stm32l4/hardware/stm32l4x6xx_dma.h index 48c9a9d1d99d5..f0dbeddab006f 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4x6xx_dma.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4x6xx_dma.h @@ -34,141 +34,141 @@ /* Register Offsets *********************************************************/ -#define STM32L4_DMA_ISR_OFFSET 0x0000 /* DMA interrupt status register */ -#define STM32L4_DMA_IFCR_OFFSET 0x0004 /* DMA interrupt flag clear register */ - -#define STM32L4_DMACHAN_OFFSET(n) (0x0014*(n)) -#define STM32L4_DMACHAN1_OFFSET 0x0000 -#define STM32L4_DMACHAN2_OFFSET 0x0014 -#define STM32L4_DMACHAN3_OFFSET 0x0028 -#define STM32L4_DMACHAN4_OFFSET 0x003c -#define STM32L4_DMACHAN5_OFFSET 0x0050 -#define STM32L4_DMACHAN6_OFFSET 0x0064 -#define STM32L4_DMACHAN7_OFFSET 0x0078 - -#define STM32L4_DMACHAN_CCR_OFFSET 0x0008 /* DMA channel configuration register */ -#define STM32L4_DMACHAN_CNDTR_OFFSET 0x000c /* DMA channel number of data register */ -#define STM32L4_DMACHAN_CPAR_OFFSET 0x0010 /* DMA channel peripheral address register */ -#define STM32L4_DMACHAN_CMAR_OFFSET 0x0014 /* DMA channel memory address register */ - -#define STM32L4_DMA_CCR_OFFSET(n) (STM32L4_DMACHAN_CCR_OFFSET+STM32L4_DMACHAN_OFFSET(n)) -#define STM32L4_DMA_CNDTR_OFFSET(n) (STM32L4_DMACHAN_CNDTR_OFFSET+STM32L4_DMACHAN_OFFSET(n)) -#define STM32L4_DMA_CPAR_OFFSET(n) (STM32L4_DMACHAN_CPAR_OFFSET+STM32L4_DMACHAN_OFFSET(n)) -#define STM32L4_DMA_CMAR_OFFSET(n) (STM32L4_DMACHAN_CMAR_OFFSET+STM32L4_DMACHAN_OFFSET(n)) - -#define STM32L4_DMA_CCR1_OFFSET 0x0008 /* DMA channel 1 configuration register */ -#define STM32L4_DMA_CCR2_OFFSET 0x001c /* DMA channel 2 configuration register */ -#define STM32L4_DMA_CCR3_OFFSET 0x0030 /* DMA channel 3 configuration register */ -#define STM32L4_DMA_CCR4_OFFSET 0x0044 /* DMA channel 4 configuration register */ -#define STM32L4_DMA_CCR5_OFFSET 0x0058 /* DMA channel 5 configuration register */ -#define STM32L4_DMA_CCR6_OFFSET 0x006c /* DMA channel 6 configuration register */ -#define STM32L4_DMA_CCR7_OFFSET 0x0080 /* DMA channel 7 configuration register */ - -#define STM32L4_DMA_CNDTR1_OFFSET 0x000c /* DMA channel 1 number of data register */ -#define STM32L4_DMA_CNDTR2_OFFSET 0x0020 /* DMA channel 2 number of data register */ -#define STM32L4_DMA_CNDTR3_OFFSET 0x0034 /* DMA channel 3 number of data register */ -#define STM32L4_DMA_CNDTR4_OFFSET 0x0048 /* DMA channel 4 number of data register */ -#define STM32L4_DMA_CNDTR5_OFFSET 0x005c /* DMA channel 5 number of data register */ -#define STM32L4_DMA_CNDTR6_OFFSET 0x0070 /* DMA channel 6 number of data register */ -#define STM32L4_DMA_CNDTR7_OFFSET 0x0084 /* DMA channel 7 number of data register */ - -#define STM32L4_DMA_CPAR1_OFFSET 0x0010 /* DMA channel 1 peripheral address register */ -#define STM32L4_DMA_CPAR2_OFFSET 0x0024 /* DMA channel 2 peripheral address register */ -#define STM32L4_DMA_CPAR3_OFFSET 0x0038 /* DMA channel 3 peripheral address register */ -#define STM32L4_DMA_CPAR4_OFFSET 0x004c /* DMA channel 4 peripheral address register */ -#define STM32L4_DMA_CPAR5_OFFSET 0x0060 /* DMA channel 5 peripheral address register */ -#define STM32L4_DMA_CPAR6_OFFSET 0x0074 /* DMA channel 6 peripheral address register */ -#define STM32L4_DMA_CPAR7_OFFSET 0x0088 /* DMA channel 7 peripheral address register */ - -#define STM32L4_DMA_CMAR1_OFFSET 0x0014 /* DMA channel 1 memory address register */ -#define STM32L4_DMA_CMAR2_OFFSET 0x0028 /* DMA channel 2 memory address register */ -#define STM32L4_DMA_CMAR3_OFFSET 0x003c /* DMA channel 3 memory address register */ -#define STM32L4_DMA_CMAR4_OFFSET 0x0050 /* DMA channel 4 memory address register */ -#define STM32L4_DMA_CMAR5_OFFSET 0x0064 /* DMA channel 5 memory address register */ -#define STM32L4_DMA_CMAR6_OFFSET 0x0078 /* DMA channel 6 memory address register */ -#define STM32L4_DMA_CMAR7_OFFSET 0x008c /* DMA channel 7 memory address register */ - -#define STM32L4_DMA_CSELR_OFFSET 0x00a8 /* DMA channel selection register */ +#define STM32_DMA_ISR_OFFSET 0x0000 /* DMA interrupt status register */ +#define STM32_DMA_IFCR_OFFSET 0x0004 /* DMA interrupt flag clear register */ + +#define STM32_DMACHAN_OFFSET(n) (0x0014*(n)) +#define STM32_DMACHAN1_OFFSET 0x0000 +#define STM32_DMACHAN2_OFFSET 0x0014 +#define STM32_DMACHAN3_OFFSET 0x0028 +#define STM32_DMACHAN4_OFFSET 0x003c +#define STM32_DMACHAN5_OFFSET 0x0050 +#define STM32_DMACHAN6_OFFSET 0x0064 +#define STM32_DMACHAN7_OFFSET 0x0078 + +#define STM32_DMACHAN_CCR_OFFSET 0x0008 /* DMA channel configuration register */ +#define STM32_DMACHAN_CNDTR_OFFSET 0x000c /* DMA channel number of data register */ +#define STM32_DMACHAN_CPAR_OFFSET 0x0010 /* DMA channel peripheral address register */ +#define STM32_DMACHAN_CMAR_OFFSET 0x0014 /* DMA channel memory address register */ + +#define STM32_DMA_CCR_OFFSET(n) (STM32_DMACHAN_CCR_OFFSET+STM32_DMACHAN_OFFSET(n)) +#define STM32_DMA_CNDTR_OFFSET(n) (STM32_DMACHAN_CNDTR_OFFSET+STM32_DMACHAN_OFFSET(n)) +#define STM32_DMA_CPAR_OFFSET(n) (STM32_DMACHAN_CPAR_OFFSET+STM32_DMACHAN_OFFSET(n)) +#define STM32_DMA_CMAR_OFFSET(n) (STM32_DMACHAN_CMAR_OFFSET+STM32_DMACHAN_OFFSET(n)) + +#define STM32_DMA_CCR1_OFFSET 0x0008 /* DMA channel 1 configuration register */ +#define STM32_DMA_CCR2_OFFSET 0x001c /* DMA channel 2 configuration register */ +#define STM32_DMA_CCR3_OFFSET 0x0030 /* DMA channel 3 configuration register */ +#define STM32_DMA_CCR4_OFFSET 0x0044 /* DMA channel 4 configuration register */ +#define STM32_DMA_CCR5_OFFSET 0x0058 /* DMA channel 5 configuration register */ +#define STM32_DMA_CCR6_OFFSET 0x006c /* DMA channel 6 configuration register */ +#define STM32_DMA_CCR7_OFFSET 0x0080 /* DMA channel 7 configuration register */ + +#define STM32_DMA_CNDTR1_OFFSET 0x000c /* DMA channel 1 number of data register */ +#define STM32_DMA_CNDTR2_OFFSET 0x0020 /* DMA channel 2 number of data register */ +#define STM32_DMA_CNDTR3_OFFSET 0x0034 /* DMA channel 3 number of data register */ +#define STM32_DMA_CNDTR4_OFFSET 0x0048 /* DMA channel 4 number of data register */ +#define STM32_DMA_CNDTR5_OFFSET 0x005c /* DMA channel 5 number of data register */ +#define STM32_DMA_CNDTR6_OFFSET 0x0070 /* DMA channel 6 number of data register */ +#define STM32_DMA_CNDTR7_OFFSET 0x0084 /* DMA channel 7 number of data register */ + +#define STM32_DMA_CPAR1_OFFSET 0x0010 /* DMA channel 1 peripheral address register */ +#define STM32_DMA_CPAR2_OFFSET 0x0024 /* DMA channel 2 peripheral address register */ +#define STM32_DMA_CPAR3_OFFSET 0x0038 /* DMA channel 3 peripheral address register */ +#define STM32_DMA_CPAR4_OFFSET 0x004c /* DMA channel 4 peripheral address register */ +#define STM32_DMA_CPAR5_OFFSET 0x0060 /* DMA channel 5 peripheral address register */ +#define STM32_DMA_CPAR6_OFFSET 0x0074 /* DMA channel 6 peripheral address register */ +#define STM32_DMA_CPAR7_OFFSET 0x0088 /* DMA channel 7 peripheral address register */ + +#define STM32_DMA_CMAR1_OFFSET 0x0014 /* DMA channel 1 memory address register */ +#define STM32_DMA_CMAR2_OFFSET 0x0028 /* DMA channel 2 memory address register */ +#define STM32_DMA_CMAR3_OFFSET 0x003c /* DMA channel 3 memory address register */ +#define STM32_DMA_CMAR4_OFFSET 0x0050 /* DMA channel 4 memory address register */ +#define STM32_DMA_CMAR5_OFFSET 0x0064 /* DMA channel 5 memory address register */ +#define STM32_DMA_CMAR6_OFFSET 0x0078 /* DMA channel 6 memory address register */ +#define STM32_DMA_CMAR7_OFFSET 0x008c /* DMA channel 7 memory address register */ + +#define STM32_DMA_CSELR_OFFSET 0x00a8 /* DMA channel selection register */ /* Register Addresses *******************************************************/ -#define STM32L4_DMA1_ISRC (STM32L4_DMA1_BASE+STM32L4_DMA_ISR_OFFSET) -#define STM32L4_DMA1_IFCR (STM32L4_DMA1_BASE+STM32L4_DMA_IFCR_OFFSET) - -#define STM32L4_DMA1_CCR(n) (STM32L4_DMA1_BASE+STM32L4_DMA_CCR_OFFSET(n)) -#define STM32L4_DMA1_CCR1 (STM32L4_DMA1_BASE+STM32L4_DMA_CCR1_OFFSET) -#define STM32L4_DMA1_CCR2 (STM32L4_DMA1_BASE+STM32L4_DMA_CCR2_OFFSET) -#define STM32L4_DMA1_CCR3 (STM32L4_DMA1_BASE+STM32L4_DMA_CCR3_OFFSET) -#define STM32L4_DMA1_CCR4 (STM32L4_DMA1_BASE+STM32L4_DMA_CCR4_OFFSET) -#define STM32L4_DMA1_CCR5 (STM32L4_DMA1_BASE+STM32L4_DMA_CCR5_OFFSET) -#define STM32L4_DMA1_CCR6 (STM32L4_DMA1_BASE+STM32L4_DMA_CCR6_OFFSET) -#define STM32L4_DMA1_CCR7 (STM32L4_DMA1_BASE+STM32L4_DMA_CCR7_OFFSET) - -#define STM32L4_DMA1_CNDTR(n) (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR_OFFSET(n)) -#define STM32L4_DMA1_CNDTR1 (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR1_OFFSET) -#define STM32L4_DMA1_CNDTR2 (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR2_OFFSET) -#define STM32L4_DMA1_CNDTR3 (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR3_OFFSET) -#define STM32L4_DMA1_CNDTR4 (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR4_OFFSET) -#define STM32L4_DMA1_CNDTR5 (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR5_OFFSET) -#define STM32L4_DMA1_CNDTR6 (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR6_OFFSET) -#define STM32L4_DMA1_CNDTR7 (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR7_OFFSET) - -#define STM32L4_DMA1_CPAR(n) (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR_OFFSET(n)) -#define STM32L4_DMA1_CPAR1 (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR1_OFFSET) -#define STM32L4_DMA1_CPAR2 (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR2_OFFSET) -#define STM32L4_DMA1_CPAR3 (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR3_OFFSET) -#define STM32L4_DMA1_CPAR4 (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR4_OFFSET) -#define STM32L4_DMA1_CPAR5 (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR5_OFFSET) -#define STM32L4_DMA1_CPAR6 (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR6_OFFSET) -#define STM32L4_DMA1_CPAR7 (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR7_OFFSET) - -#define STM32L4_DMA1_CMAR(n) (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR_OFFSET(n)) -#define STM32L4_DMA1_CMAR1 (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR1_OFFSET) -#define STM32L4_DMA1_CMAR2 (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR2_OFFSET) -#define STM32L4_DMA1_CMAR3 (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR3_OFFSET) -#define STM32L4_DMA1_CMAR4 (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR4_OFFSET) -#define STM32L4_DMA1_CMAR5 (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR5_OFFSET) -#define STM32L4_DMA1_CMAR6 (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR6_OFFSET) -#define STM32L4_DMA1_CMAR7 (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR7_OFFSET) - -#define STM32L4_DMA2_ISRC (STM32L4_DMA2_BASE+STM32L4_DMA_ISR_OFFSET) -#define STM32L4_DMA2_IFCR (STM32L4_DMA2_BASE+STM32L4_DMA_IFCR_OFFSET) - -#define STM32L4_DMA2_CCR(n) (STM32L4_DMA2_BASE+STM32L4_DMA_CCR_OFFSET(n)) -#define STM32L4_DMA2_CCR1 (STM32L4_DMA2_BASE+STM32L4_DMA_CCR1_OFFSET) -#define STM32L4_DMA2_CCR2 (STM32L4_DMA2_BASE+STM32L4_DMA_CCR2_OFFSET) -#define STM32L4_DMA2_CCR3 (STM32L4_DMA2_BASE+STM32L4_DMA_CCR3_OFFSET) -#define STM32L4_DMA2_CCR4 (STM32L4_DMA2_BASE+STM32L4_DMA_CCR4_OFFSET) -#define STM32L4_DMA2_CCR5 (STM32L4_DMA2_BASE+STM32L4_DMA_CCR5_OFFSET) -#define STM32L4_DMA2_CCR6 (STM32L4_DMA2_BASE+STM32L4_DMA_CCR6_OFFSET) -#define STM32L4_DMA2_CCR7 (STM32L4_DMA2_BASE+STM32L4_DMA_CCR7_OFFSET) - -#define STM32L4_DMA2_CNDTR(n) (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR_OFFSET(n)) -#define STM32L4_DMA2_CNDTR1 (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR1_OFFSET) -#define STM32L4_DMA2_CNDTR2 (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR2_OFFSET) -#define STM32L4_DMA2_CNDTR3 (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR3_OFFSET) -#define STM32L4_DMA2_CNDTR4 (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR4_OFFSET) -#define STM32L4_DMA2_CNDTR5 (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR5_OFFSET) -#define STM32L4_DMA2_CNDTR6 (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR6_OFFSET) -#define STM32L4_DMA2_CNDTR7 (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR7_OFFSET) - -#define STM32L4_DMA2_CPAR(n) (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR_OFFSET(n)) -#define STM32L4_DMA2_CPAR1 (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR1_OFFSET) -#define STM32L4_DMA2_CPAR2 (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR2_OFFSET) -#define STM32L4_DMA2_CPAR3 (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR3_OFFSET) -#define STM32L4_DMA2_CPAR4 (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR4_OFFSET) -#define STM32L4_DMA2_CPAR5 (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR5_OFFSET) -#define STM32L4_DMA2_CPAR6 (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR6_OFFSET) -#define STM32L4_DMA2_CPAR7 (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR7_OFFSET) - -#define STM32L4_DMA2_CMAR(n) (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR_OFFSET(n)) -#define STM32L4_DMA2_CMAR1 (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR1_OFFSET) -#define STM32L4_DMA2_CMAR2 (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR2_OFFSET) -#define STM32L4_DMA2_CMAR3 (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR3_OFFSET) -#define STM32L4_DMA2_CMAR4 (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR4_OFFSET) -#define STM32L4_DMA2_CMAR5 (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR5_OFFSET) -#define STM32L4_DMA2_CMAR6 (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR6_OFFSET) -#define STM32L4_DMA2_CMAR7 (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR7_OFFSET) +#define STM32_DMA1_ISRC (STM32_DMA1_BASE+STM32_DMA_ISR_OFFSET) +#define STM32_DMA1_IFCR (STM32_DMA1_BASE+STM32_DMA_IFCR_OFFSET) + +#define STM32_DMA1_CCR(n) (STM32_DMA1_BASE+STM32_DMA_CCR_OFFSET(n)) +#define STM32_DMA1_CCR1 (STM32_DMA1_BASE+STM32_DMA_CCR1_OFFSET) +#define STM32_DMA1_CCR2 (STM32_DMA1_BASE+STM32_DMA_CCR2_OFFSET) +#define STM32_DMA1_CCR3 (STM32_DMA1_BASE+STM32_DMA_CCR3_OFFSET) +#define STM32_DMA1_CCR4 (STM32_DMA1_BASE+STM32_DMA_CCR4_OFFSET) +#define STM32_DMA1_CCR5 (STM32_DMA1_BASE+STM32_DMA_CCR5_OFFSET) +#define STM32_DMA1_CCR6 (STM32_DMA1_BASE+STM32_DMA_CCR6_OFFSET) +#define STM32_DMA1_CCR7 (STM32_DMA1_BASE+STM32_DMA_CCR7_OFFSET) + +#define STM32_DMA1_CNDTR(n) (STM32_DMA1_BASE+STM32_DMA_CNDTR_OFFSET(n)) +#define STM32_DMA1_CNDTR1 (STM32_DMA1_BASE+STM32_DMA_CNDTR1_OFFSET) +#define STM32_DMA1_CNDTR2 (STM32_DMA1_BASE+STM32_DMA_CNDTR2_OFFSET) +#define STM32_DMA1_CNDTR3 (STM32_DMA1_BASE+STM32_DMA_CNDTR3_OFFSET) +#define STM32_DMA1_CNDTR4 (STM32_DMA1_BASE+STM32_DMA_CNDTR4_OFFSET) +#define STM32_DMA1_CNDTR5 (STM32_DMA1_BASE+STM32_DMA_CNDTR5_OFFSET) +#define STM32_DMA1_CNDTR6 (STM32_DMA1_BASE+STM32_DMA_CNDTR6_OFFSET) +#define STM32_DMA1_CNDTR7 (STM32_DMA1_BASE+STM32_DMA_CNDTR7_OFFSET) + +#define STM32_DMA1_CPAR(n) (STM32_DMA1_BASE+STM32_DMA_CPAR_OFFSET(n)) +#define STM32_DMA1_CPAR1 (STM32_DMA1_BASE+STM32_DMA_CPAR1_OFFSET) +#define STM32_DMA1_CPAR2 (STM32_DMA1_BASE+STM32_DMA_CPAR2_OFFSET) +#define STM32_DMA1_CPAR3 (STM32_DMA1_BASE+STM32_DMA_CPAR3_OFFSET) +#define STM32_DMA1_CPAR4 (STM32_DMA1_BASE+STM32_DMA_CPAR4_OFFSET) +#define STM32_DMA1_CPAR5 (STM32_DMA1_BASE+STM32_DMA_CPAR5_OFFSET) +#define STM32_DMA1_CPAR6 (STM32_DMA1_BASE+STM32_DMA_CPAR6_OFFSET) +#define STM32_DMA1_CPAR7 (STM32_DMA1_BASE+STM32_DMA_CPAR7_OFFSET) + +#define STM32_DMA1_CMAR(n) (STM32_DMA1_BASE+STM32_DMA_CMAR_OFFSET(n)) +#define STM32_DMA1_CMAR1 (STM32_DMA1_BASE+STM32_DMA_CMAR1_OFFSET) +#define STM32_DMA1_CMAR2 (STM32_DMA1_BASE+STM32_DMA_CMAR2_OFFSET) +#define STM32_DMA1_CMAR3 (STM32_DMA1_BASE+STM32_DMA_CMAR3_OFFSET) +#define STM32_DMA1_CMAR4 (STM32_DMA1_BASE+STM32_DMA_CMAR4_OFFSET) +#define STM32_DMA1_CMAR5 (STM32_DMA1_BASE+STM32_DMA_CMAR5_OFFSET) +#define STM32_DMA1_CMAR6 (STM32_DMA1_BASE+STM32_DMA_CMAR6_OFFSET) +#define STM32_DMA1_CMAR7 (STM32_DMA1_BASE+STM32_DMA_CMAR7_OFFSET) + +#define STM32_DMA2_ISRC (STM32_DMA2_BASE+STM32_DMA_ISR_OFFSET) +#define STM32_DMA2_IFCR (STM32_DMA2_BASE+STM32_DMA_IFCR_OFFSET) + +#define STM32_DMA2_CCR(n) (STM32_DMA2_BASE+STM32_DMA_CCR_OFFSET(n)) +#define STM32_DMA2_CCR1 (STM32_DMA2_BASE+STM32_DMA_CCR1_OFFSET) +#define STM32_DMA2_CCR2 (STM32_DMA2_BASE+STM32_DMA_CCR2_OFFSET) +#define STM32_DMA2_CCR3 (STM32_DMA2_BASE+STM32_DMA_CCR3_OFFSET) +#define STM32_DMA2_CCR4 (STM32_DMA2_BASE+STM32_DMA_CCR4_OFFSET) +#define STM32_DMA2_CCR5 (STM32_DMA2_BASE+STM32_DMA_CCR5_OFFSET) +#define STM32_DMA2_CCR6 (STM32_DMA2_BASE+STM32_DMA_CCR6_OFFSET) +#define STM32_DMA2_CCR7 (STM32_DMA2_BASE+STM32_DMA_CCR7_OFFSET) + +#define STM32_DMA2_CNDTR(n) (STM32_DMA2_BASE+STM32_DMA_CNDTR_OFFSET(n)) +#define STM32_DMA2_CNDTR1 (STM32_DMA2_BASE+STM32_DMA_CNDTR1_OFFSET) +#define STM32_DMA2_CNDTR2 (STM32_DMA2_BASE+STM32_DMA_CNDTR2_OFFSET) +#define STM32_DMA2_CNDTR3 (STM32_DMA2_BASE+STM32_DMA_CNDTR3_OFFSET) +#define STM32_DMA2_CNDTR4 (STM32_DMA2_BASE+STM32_DMA_CNDTR4_OFFSET) +#define STM32_DMA2_CNDTR5 (STM32_DMA2_BASE+STM32_DMA_CNDTR5_OFFSET) +#define STM32_DMA2_CNDTR6 (STM32_DMA2_BASE+STM32_DMA_CNDTR6_OFFSET) +#define STM32_DMA2_CNDTR7 (STM32_DMA2_BASE+STM32_DMA_CNDTR7_OFFSET) + +#define STM32_DMA2_CPAR(n) (STM32_DMA2_BASE+STM32_DMA_CPAR_OFFSET(n)) +#define STM32_DMA2_CPAR1 (STM32_DMA2_BASE+STM32_DMA_CPAR1_OFFSET) +#define STM32_DMA2_CPAR2 (STM32_DMA2_BASE+STM32_DMA_CPAR2_OFFSET) +#define STM32_DMA2_CPAR3 (STM32_DMA2_BASE+STM32_DMA_CPAR3_OFFSET) +#define STM32_DMA2_CPAR4 (STM32_DMA2_BASE+STM32_DMA_CPAR4_OFFSET) +#define STM32_DMA2_CPAR5 (STM32_DMA2_BASE+STM32_DMA_CPAR5_OFFSET) +#define STM32_DMA2_CPAR6 (STM32_DMA2_BASE+STM32_DMA_CPAR6_OFFSET) +#define STM32_DMA2_CPAR7 (STM32_DMA2_BASE+STM32_DMA_CPAR7_OFFSET) + +#define STM32_DMA2_CMAR(n) (STM32_DMA2_BASE+STM32_DMA_CMAR_OFFSET(n)) +#define STM32_DMA2_CMAR1 (STM32_DMA2_BASE+STM32_DMA_CMAR1_OFFSET) +#define STM32_DMA2_CMAR2 (STM32_DMA2_BASE+STM32_DMA_CMAR2_OFFSET) +#define STM32_DMA2_CMAR3 (STM32_DMA2_BASE+STM32_DMA_CMAR3_OFFSET) +#define STM32_DMA2_CMAR4 (STM32_DMA2_BASE+STM32_DMA_CMAR4_OFFSET) +#define STM32_DMA2_CMAR5 (STM32_DMA2_BASE+STM32_DMA_CMAR5_OFFSET) +#define STM32_DMA2_CMAR6 (STM32_DMA2_BASE+STM32_DMA_CMAR6_OFFSET) +#define STM32_DMA2_CMAR7 (STM32_DMA2_BASE+STM32_DMA_CMAR7_OFFSET) /* Register Bitfield Definitions ********************************************/ @@ -276,21 +276,21 @@ * numeric suffix. Additional definitions are required in the board.h file. */ -#define STM32L4_DMA1_CHAN1 (0) -#define STM32L4_DMA1_CHAN2 (1) -#define STM32L4_DMA1_CHAN3 (2) -#define STM32L4_DMA1_CHAN4 (3) -#define STM32L4_DMA1_CHAN5 (4) -#define STM32L4_DMA1_CHAN6 (5) -#define STM32L4_DMA1_CHAN7 (6) - -#define STM32L4_DMA2_CHAN1 (7) -#define STM32L4_DMA2_CHAN2 (8) -#define STM32L4_DMA2_CHAN3 (9) -#define STM32L4_DMA2_CHAN4 (10) -#define STM32L4_DMA2_CHAN5 (11) -#define STM32L4_DMA2_CHAN6 (12) -#define STM32L4_DMA2_CHAN7 (13) +#define STM32_DMA1_CHAN1 (0) +#define STM32_DMA1_CHAN2 (1) +#define STM32_DMA1_CHAN3 (2) +#define STM32_DMA1_CHAN4 (3) +#define STM32_DMA1_CHAN5 (4) +#define STM32_DMA1_CHAN6 (5) +#define STM32_DMA1_CHAN7 (6) + +#define STM32_DMA2_CHAN1 (7) +#define STM32_DMA2_CHAN2 (8) +#define STM32_DMA2_CHAN3 (9) +#define STM32_DMA2_CHAN4 (10) +#define STM32_DMA2_CHAN5 (11) +#define STM32_DMA2_CHAN6 (12) +#define STM32_DMA2_CHAN7 (13) /* DMA Channel settings include a channel and an alternative function. * Channel is in bits 0..7 @@ -305,186 +305,186 @@ /* ADC */ -#define DMACHAN_ADC1_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN1, 0) -#define DMACHAN_ADC1_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN3, 0) +#define DMACHAN_ADC1_1 DMACHAN_SETTING(STM32_DMA1_CHAN1, 0) +#define DMACHAN_ADC1_2 DMACHAN_SETTING(STM32_DMA2_CHAN3, 0) -#define DMACHAN_ADC2_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN1, 0) -#define DMACHAN_ADC2_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN4, 0) +#define DMACHAN_ADC2_1 DMACHAN_SETTING(STM32_DMA1_CHAN1, 0) +#define DMACHAN_ADC2_2 DMACHAN_SETTING(STM32_DMA2_CHAN4, 0) -#define DMACHAN_ADC3_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN1, 0) -#define DMACHAN_ADC3_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN5, 0) +#define DMACHAN_ADC3_1 DMACHAN_SETTING(STM32_DMA1_CHAN1, 0) +#define DMACHAN_ADC3_2 DMACHAN_SETTING(STM32_DMA2_CHAN5, 0) /* AES */ -#define DMACHAN_AES_IN_1 DMACHAN_SETTING(STM32L4_DMA2_CHAN1, 6) -#define DMACHAN_AES_IN_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN5, 6) -#define DMACHAN_AES_OUT_1 DMACHAN_SETTING(STM32L4_DMA2_CHAN2, 6) -#define DMACHAN_AES_OUT_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN3, 6) +#define DMACHAN_AES_IN_1 DMACHAN_SETTING(STM32_DMA2_CHAN1, 6) +#define DMACHAN_AES_IN_2 DMACHAN_SETTING(STM32_DMA2_CHAN5, 6) +#define DMACHAN_AES_OUT_1 DMACHAN_SETTING(STM32_DMA2_CHAN2, 6) +#define DMACHAN_AES_OUT_2 DMACHAN_SETTING(STM32_DMA2_CHAN3, 6) /* DAC */ -#define DMACHAN_DAC1_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 6) -#define DMACHAN_DAC1_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN4, 3) +#define DMACHAN_DAC1_1 DMACHAN_SETTING(STM32_DMA1_CHAN3, 6) +#define DMACHAN_DAC1_2 DMACHAN_SETTING(STM32_DMA2_CHAN4, 3) -#define DMACHAN_DAC2_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN4, 5) -#define DMACHAN_DAC2_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN5, 3) +#define DMACHAN_DAC2_1 DMACHAN_SETTING(STM32_DMA1_CHAN4, 5) +#define DMACHAN_DAC2_2 DMACHAN_SETTING(STM32_DMA2_CHAN5, 3) /* DCMI */ -#define DMACHAN_DCMI_1 DMACHAN_SETTING(STM32L4_DMA2_CHAN5, 4) -#define DMACHAN_DCMI_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN6, 0) +#define DMACHAN_DCMI_1 DMACHAN_SETTING(STM32_DMA2_CHAN5, 4) +#define DMACHAN_DCMI_2 DMACHAN_SETTING(STM32_DMA2_CHAN6, 0) /* DFSDM */ -#define DMACHAN_DFSDM0 DMACHAN_SETTING(STM32L4_DMA1_CHAN4, 0) -#define DMACHAN_DFSDM1 DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 0) -#define DMACHAN_DFSDM2 DMACHAN_SETTING(STM32L4_DMA1_CHAN6, 0) -#define DMACHAN_DFSDM3 DMACHAN_SETTING(STM32L4_DMA1_CHAN7, 0) +#define DMACHAN_DFSDM0 DMACHAN_SETTING(STM32_DMA1_CHAN4, 0) +#define DMACHAN_DFSDM1 DMACHAN_SETTING(STM32_DMA1_CHAN5, 0) +#define DMACHAN_DFSDM2 DMACHAN_SETTING(STM32_DMA1_CHAN6, 0) +#define DMACHAN_DFSDM3 DMACHAN_SETTING(STM32_DMA1_CHAN7, 0) /* HASH */ -#define DMACHAN_HASH_IN DMACHAN_SETTING(STM32L4_DMA2_CHAN7, 6) +#define DMACHAN_HASH_IN DMACHAN_SETTING(STM32_DMA2_CHAN7, 6) /* I2C */ -#define DMACHAN_I2C1_RX_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN7, 3) -#define DMACHAN_I2C1_RX_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN6, 5) -#define DMACHAN_I2C1_TX_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN6, 3) -#define DMACHAN_I2C1_TX_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN7, 5) +#define DMACHAN_I2C1_RX_1 DMACHAN_SETTING(STM32_DMA1_CHAN7, 3) +#define DMACHAN_I2C1_RX_2 DMACHAN_SETTING(STM32_DMA2_CHAN6, 5) +#define DMACHAN_I2C1_TX_1 DMACHAN_SETTING(STM32_DMA1_CHAN6, 3) +#define DMACHAN_I2C1_TX_2 DMACHAN_SETTING(STM32_DMA2_CHAN7, 5) -#define DMACHAN_I2C2_RX DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 3) -#define DMACHAN_I2C2_TX DMACHAN_SETTING(STM32L4_DMA1_CHAN4, 3) +#define DMACHAN_I2C2_RX DMACHAN_SETTING(STM32_DMA1_CHAN5, 3) +#define DMACHAN_I2C2_TX DMACHAN_SETTING(STM32_DMA1_CHAN4, 3) -#define DMACHAN_I2C3_RX DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 2) -#define DMACHAN_I2C3_TX DMACHAN_SETTING(STM32L4_DMA1_CHAN2, 3) +#define DMACHAN_I2C3_RX DMACHAN_SETTING(STM32_DMA1_CHAN3, 2) +#define DMACHAN_I2C3_TX DMACHAN_SETTING(STM32_DMA1_CHAN2, 3) -#define DMACHAN_I2C4_RX DMACHAN_SETTING(STM32L4_DMA2_CHAN1, 0) -#define DMACHAN_I2C4_TX DMACHAN_SETTING(STM32L4_DMA2_CHAN2, 0) +#define DMACHAN_I2C4_RX DMACHAN_SETTING(STM32_DMA2_CHAN1, 0) +#define DMACHAN_I2C4_TX DMACHAN_SETTING(STM32_DMA2_CHAN2, 0) /* QUADSPI */ -#define DMACHAN_QUADSPI_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 5) -#define DMACHAN_QUADSPI_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN7, 3) +#define DMACHAN_QUADSPI_1 DMACHAN_SETTING(STM32_DMA1_CHAN5, 5) +#define DMACHAN_QUADSPI_2 DMACHAN_SETTING(STM32_DMA2_CHAN7, 3) /* SAI */ -#define DMACHAN_SAI1_A_1 DMACHAN_SETTING(STM32L4_DMA2_CHAN1, 1) -#define DMACHAN_SAI1_A_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN6, 1) -#define DMACHAN_SAI1_B_1 DMACHAN_SETTING(STM32L4_DMA2_CHAN2, 1) -#define DMACHAN_SAI1_B_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN7, 1) +#define DMACHAN_SAI1_A_1 DMACHAN_SETTING(STM32_DMA2_CHAN1, 1) +#define DMACHAN_SAI1_A_2 DMACHAN_SETTING(STM32_DMA2_CHAN6, 1) +#define DMACHAN_SAI1_B_1 DMACHAN_SETTING(STM32_DMA2_CHAN2, 1) +#define DMACHAN_SAI1_B_2 DMACHAN_SETTING(STM32_DMA2_CHAN7, 1) -#define DMACHAN_SAI2_A_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN6, 1) -#define DMACHAN_SAI2_A_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN3, 1) -#define DMACHAN_SAI2_B_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN7, 1) -#define DMACHAN_SAI2_B_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN4, 1) +#define DMACHAN_SAI2_A_1 DMACHAN_SETTING(STM32_DMA1_CHAN6, 1) +#define DMACHAN_SAI2_A_2 DMACHAN_SETTING(STM32_DMA2_CHAN3, 1) +#define DMACHAN_SAI2_B_1 DMACHAN_SETTING(STM32_DMA1_CHAN7, 1) +#define DMACHAN_SAI2_B_2 DMACHAN_SETTING(STM32_DMA2_CHAN4, 1) /* SDMMC */ -#define DMACHAN_SDMMC_1 DMACHAN_SETTING(STM32L4_DMA2_CHAN4, 7) -#define DMACHAN_SDMMC_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN5, 7) +#define DMACHAN_SDMMC_1 DMACHAN_SETTING(STM32_DMA2_CHAN4, 7) +#define DMACHAN_SDMMC_2 DMACHAN_SETTING(STM32_DMA2_CHAN5, 7) /* SPI */ -#define DMACHAN_SPI1_RX_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN2, 1) -#define DMACHAN_SPI1_RX_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN3, 4) -#define DMACHAN_SPI1_TX_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 1) -#define DMACHAN_SPI1_TX_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN4, 4) +#define DMACHAN_SPI1_RX_1 DMACHAN_SETTING(STM32_DMA1_CHAN2, 1) +#define DMACHAN_SPI1_RX_2 DMACHAN_SETTING(STM32_DMA2_CHAN3, 4) +#define DMACHAN_SPI1_TX_1 DMACHAN_SETTING(STM32_DMA1_CHAN3, 1) +#define DMACHAN_SPI1_TX_2 DMACHAN_SETTING(STM32_DMA2_CHAN4, 4) -#define DMACHAN_SPI2_RX DMACHAN_SETTING(STM32L4_DMA1_CHAN4, 1) -#define DMACHAN_SPI2_TX DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 1) +#define DMACHAN_SPI2_RX DMACHAN_SETTING(STM32_DMA1_CHAN4, 1) +#define DMACHAN_SPI2_TX DMACHAN_SETTING(STM32_DMA1_CHAN5, 1) -#define DMACHAN_SPI3_RX DMACHAN_SETTING(STM32L4_DMA2_CHAN1, 3) -#define DMACHAN_SPI3_TX DMACHAN_SETTING(STM32L4_DMA2_CHAN2, 3) +#define DMACHAN_SPI3_RX DMACHAN_SETTING(STM32_DMA2_CHAN1, 3) +#define DMACHAN_SPI3_TX DMACHAN_SETTING(STM32_DMA2_CHAN2, 3) /* SWPMI */ -#define DMACHAN_SWPMI_RX DMACHAN_SETTING(STM32L4_DMA2_CHAN1, 4) -#define DMACHAN_SWPMI_TX DMACHAN_SETTING(STM32L4_DMA2_CHAN2, 4) +#define DMACHAN_SWPMI_RX DMACHAN_SETTING(STM32_DMA2_CHAN1, 4) +#define DMACHAN_SWPMI_TX DMACHAN_SETTING(STM32_DMA2_CHAN2, 4) /* TIM */ -#define DMACHAN_TIM1_CH1 DMACHAN_SETTING(STM32L4_DMA1_CHAN2, 7) -#define DMACHAN_TIM1_CH2 DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 7) -#define DMACHAN_TIM1_CH3 DMACHAN_SETTING(STM32L4_DMA1_CHAN7, 7) -#define DMACHAN_TIM1_CH4 DMACHAN_SETTING(STM32L4_DMA1_CHAN4, 7) -#define DMACHAN_TIM1_COM DMACHAN_SETTING(STM32L4_DMA1_CHAN4, 7) -#define DMACHAN_TIM1_TRIG DMACHAN_SETTING(STM32L4_DMA1_CHAN4, 7) -#define DMACHAN_TIM1_UP DMACHAN_SETTING(STM32L4_DMA1_CHAN6, 7) - -#define DMACHAN_TIM2_CH1 DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 4) -#define DMACHAN_TIM2_CH2 DMACHAN_SETTING(STM32L4_DMA1_CHAN7, 4) -#define DMACHAN_TIM2_CH3 DMACHAN_SETTING(STM32L4_DMA1_CHAN1, 4) -#define DMACHAN_TIM2_CH4 DMACHAN_SETTING(STM32L4_DMA1_CHAN7, 4) -#define DMACHAN_TIM2_UP DMACHAN_SETTING(STM32L4_DMA1_CHAN2, 4) - -#define DMACHAN_TIM3_CH1 DMACHAN_SETTING(STM32L4_DMA1_CHAN6, 5) -#define DMACHAN_TIM3_CH3 DMACHAN_SETTING(STM32L4_DMA1_CHAN2, 5) -#define DMACHAN_TIM3_CH4 DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 5) -#define DMACHAN_TIM3_TRIG DMACHAN_SETTING(STM32L4_DMA1_CHAN6, 5) -#define DMACHAN_TIM3_UP DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 5) - -#define DMACHAN_TIM4_CH1 DMACHAN_SETTING(STM32L4_DMA1_CHAN1, 6) -#define DMACHAN_TIM4_CH2 DMACHAN_SETTING(STM32L4_DMA1_CHAN4, 6) -#define DMACHAN_TIM4_CH3 DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 6) -#define DMACHAN_TIM4_UP DMACHAN_SETTING(STM32L4_DMA1_CHAN7, 6) - -#define DMACHAN_TIM5_CH1 DMACHAN_SETTING(STM32L4_DMA2_CHAN5, 5) -#define DMACHAN_TIM5_CH2 DMACHAN_SETTING(STM32L4_DMA2_CHAN4, 5) -#define DMACHAN_TIM5_CH3 DMACHAN_SETTING(STM32L4_DMA2_CHAN2, 5) -#define DMACHAN_TIM5_CH4 DMACHAN_SETTING(STM32L4_DMA2_CHAN1, 5) -#define DMACHAN_TIM5_COM DMACHAN_SETTING(STM32L4_DMA2_CHAN1, 5) -#define DMACHAN_TIM5_TRIG DMACHAN_SETTING(STM32L4_DMA2_CHAN1, 5) -#define DMACHAN_TIM5_UP DMACHAN_SETTING(STM32L4_DMA2_CHAN2, 5) - -#define DMACHAN_TIM6_UP_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 6) -#define DMACHAN_TIM6_UP_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN4, 3) - -#define DMACHAN_TIM7_UP_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN4, 5) -#define DMACHAN_TIM7_UP_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN5, 3) - -#define DMACHAN_TIM8_CH1 DMACHAN_SETTING(STM32L4_DMA2_CHAN6, 7) -#define DMACHAN_TIM8_CH2 DMACHAN_SETTING(STM32L4_DMA2_CHAN7, 7) -#define DMACHAN_TIM8_CH3 DMACHAN_SETTING(STM32L4_DMA2_CHAN1, 7) -#define DMACHAN_TIM8_CH4 DMACHAN_SETTING(STM32L4_DMA2_CHAN2, 7) -#define DMACHAN_TIM8_COM DMACHAN_SETTING(STM32L4_DMA2_CHAN2, 7) -#define DMACHAN_TIM8_TRIG DMACHAN_SETTING(STM32L4_DMA2_CHAN2, 7) -#define DMACHAN_TIM8_UP DMACHAN_SETTING(STM32L4_DMA2_CHAN1, 7) - -#define DMACHAN_TIM15_CH1 DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 7) -#define DMACHAN_TIM15_COM DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 7) -#define DMACHAN_TIM15_TRIG DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 7) -#define DMACHAN_TIM15_UP DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 7) - -#define DMACHAN_TIM16_CH1_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 4) -#define DMACHAN_TIM16_CH1_2 DMACHAN_SETTING(STM32L4_DMA1_CHAN6, 4) -#define DMACHAN_TIM16_UP_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 4) -#define DMACHAN_TIM16_UP_2 DMACHAN_SETTING(STM32L4_DMA1_CHAN6, 4) - -#define DMACHAN_TIM17_CH1_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN1, 5) -#define DMACHAN_TIM17_CH1_2 DMACHAN_SETTING(STM32L4_DMA1_CHAN7, 5) -#define DMACHAN_TIM17_UP_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN1, 5) -#define DMACHAN_TIM17_UP_2 DMACHAN_SETTING(STM32L4_DMA1_CHAN7, 5) +#define DMACHAN_TIM1_CH1 DMACHAN_SETTING(STM32_DMA1_CHAN2, 7) +#define DMACHAN_TIM1_CH2 DMACHAN_SETTING(STM32_DMA1_CHAN3, 7) +#define DMACHAN_TIM1_CH3 DMACHAN_SETTING(STM32_DMA1_CHAN7, 7) +#define DMACHAN_TIM1_CH4 DMACHAN_SETTING(STM32_DMA1_CHAN4, 7) +#define DMACHAN_TIM1_COM DMACHAN_SETTING(STM32_DMA1_CHAN4, 7) +#define DMACHAN_TIM1_TRIG DMACHAN_SETTING(STM32_DMA1_CHAN4, 7) +#define DMACHAN_TIM1_UP DMACHAN_SETTING(STM32_DMA1_CHAN6, 7) + +#define DMACHAN_TIM2_CH1 DMACHAN_SETTING(STM32_DMA1_CHAN5, 4) +#define DMACHAN_TIM2_CH2 DMACHAN_SETTING(STM32_DMA1_CHAN7, 4) +#define DMACHAN_TIM2_CH3 DMACHAN_SETTING(STM32_DMA1_CHAN1, 4) +#define DMACHAN_TIM2_CH4 DMACHAN_SETTING(STM32_DMA1_CHAN7, 4) +#define DMACHAN_TIM2_UP DMACHAN_SETTING(STM32_DMA1_CHAN2, 4) + +#define DMACHAN_TIM3_CH1 DMACHAN_SETTING(STM32_DMA1_CHAN6, 5) +#define DMACHAN_TIM3_CH3 DMACHAN_SETTING(STM32_DMA1_CHAN2, 5) +#define DMACHAN_TIM3_CH4 DMACHAN_SETTING(STM32_DMA1_CHAN3, 5) +#define DMACHAN_TIM3_TRIG DMACHAN_SETTING(STM32_DMA1_CHAN6, 5) +#define DMACHAN_TIM3_UP DMACHAN_SETTING(STM32_DMA1_CHAN3, 5) + +#define DMACHAN_TIM4_CH1 DMACHAN_SETTING(STM32_DMA1_CHAN1, 6) +#define DMACHAN_TIM4_CH2 DMACHAN_SETTING(STM32_DMA1_CHAN4, 6) +#define DMACHAN_TIM4_CH3 DMACHAN_SETTING(STM32_DMA1_CHAN5, 6) +#define DMACHAN_TIM4_UP DMACHAN_SETTING(STM32_DMA1_CHAN7, 6) + +#define DMACHAN_TIM5_CH1 DMACHAN_SETTING(STM32_DMA2_CHAN5, 5) +#define DMACHAN_TIM5_CH2 DMACHAN_SETTING(STM32_DMA2_CHAN4, 5) +#define DMACHAN_TIM5_CH3 DMACHAN_SETTING(STM32_DMA2_CHAN2, 5) +#define DMACHAN_TIM5_CH4 DMACHAN_SETTING(STM32_DMA2_CHAN1, 5) +#define DMACHAN_TIM5_COM DMACHAN_SETTING(STM32_DMA2_CHAN1, 5) +#define DMACHAN_TIM5_TRIG DMACHAN_SETTING(STM32_DMA2_CHAN1, 5) +#define DMACHAN_TIM5_UP DMACHAN_SETTING(STM32_DMA2_CHAN2, 5) + +#define DMACHAN_TIM6_UP_1 DMACHAN_SETTING(STM32_DMA1_CHAN3, 6) +#define DMACHAN_TIM6_UP_2 DMACHAN_SETTING(STM32_DMA2_CHAN4, 3) + +#define DMACHAN_TIM7_UP_1 DMACHAN_SETTING(STM32_DMA1_CHAN4, 5) +#define DMACHAN_TIM7_UP_2 DMACHAN_SETTING(STM32_DMA2_CHAN5, 3) + +#define DMACHAN_TIM8_CH1 DMACHAN_SETTING(STM32_DMA2_CHAN6, 7) +#define DMACHAN_TIM8_CH2 DMACHAN_SETTING(STM32_DMA2_CHAN7, 7) +#define DMACHAN_TIM8_CH3 DMACHAN_SETTING(STM32_DMA2_CHAN1, 7) +#define DMACHAN_TIM8_CH4 DMACHAN_SETTING(STM32_DMA2_CHAN2, 7) +#define DMACHAN_TIM8_COM DMACHAN_SETTING(STM32_DMA2_CHAN2, 7) +#define DMACHAN_TIM8_TRIG DMACHAN_SETTING(STM32_DMA2_CHAN2, 7) +#define DMACHAN_TIM8_UP DMACHAN_SETTING(STM32_DMA2_CHAN1, 7) + +#define DMACHAN_TIM15_CH1 DMACHAN_SETTING(STM32_DMA1_CHAN5, 7) +#define DMACHAN_TIM15_COM DMACHAN_SETTING(STM32_DMA1_CHAN5, 7) +#define DMACHAN_TIM15_TRIG DMACHAN_SETTING(STM32_DMA1_CHAN5, 7) +#define DMACHAN_TIM15_UP DMACHAN_SETTING(STM32_DMA1_CHAN5, 7) + +#define DMACHAN_TIM16_CH1_1 DMACHAN_SETTING(STM32_DMA1_CHAN3, 4) +#define DMACHAN_TIM16_CH1_2 DMACHAN_SETTING(STM32_DMA1_CHAN6, 4) +#define DMACHAN_TIM16_UP_1 DMACHAN_SETTING(STM32_DMA1_CHAN3, 4) +#define DMACHAN_TIM16_UP_2 DMACHAN_SETTING(STM32_DMA1_CHAN6, 4) + +#define DMACHAN_TIM17_CH1_1 DMACHAN_SETTING(STM32_DMA1_CHAN1, 5) +#define DMACHAN_TIM17_CH1_2 DMACHAN_SETTING(STM32_DMA1_CHAN7, 5) +#define DMACHAN_TIM17_UP_1 DMACHAN_SETTING(STM32_DMA1_CHAN1, 5) +#define DMACHAN_TIM17_UP_2 DMACHAN_SETTING(STM32_DMA1_CHAN7, 5) /* UART */ -#define DMACHAN_USART1_RX_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 2) -#define DMACHAN_USART1_RX_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN7, 2) -#define DMACHAN_USART1_TX_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN4, 2) -#define DMACHAN_USART1_TX_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN6, 2) +#define DMACHAN_USART1_RX_1 DMACHAN_SETTING(STM32_DMA1_CHAN5, 2) +#define DMACHAN_USART1_RX_2 DMACHAN_SETTING(STM32_DMA2_CHAN7, 2) +#define DMACHAN_USART1_TX_1 DMACHAN_SETTING(STM32_DMA1_CHAN4, 2) +#define DMACHAN_USART1_TX_2 DMACHAN_SETTING(STM32_DMA2_CHAN6, 2) -#define DMACHAN_USART2_RX DMACHAN_SETTING(STM32L4_DMA1_CHAN6, 2) -#define DMACHAN_USART2_TX DMACHAN_SETTING(STM32L4_DMA1_CHAN7, 2) +#define DMACHAN_USART2_RX DMACHAN_SETTING(STM32_DMA1_CHAN6, 2) +#define DMACHAN_USART2_TX DMACHAN_SETTING(STM32_DMA1_CHAN7, 2) -#define DMACHAN_USART3_RX DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 2) -#define DMACHAN_USART3_TX DMACHAN_SETTING(STM32L4_DMA1_CHAN2, 2) +#define DMACHAN_USART3_RX DMACHAN_SETTING(STM32_DMA1_CHAN3, 2) +#define DMACHAN_USART3_TX DMACHAN_SETTING(STM32_DMA1_CHAN2, 2) -#define DMACHAN_UART5_RX DMACHAN_SETTING(STM32L4_DMA2_CHAN2, 2) -#define DMACHAN_UART5_TX DMACHAN_SETTING(STM32L4_DMA2_CHAN1, 2) +#define DMACHAN_UART5_RX DMACHAN_SETTING(STM32_DMA2_CHAN2, 2) +#define DMACHAN_UART5_TX DMACHAN_SETTING(STM32_DMA2_CHAN1, 2) -#define DMACHAN_UART4_RX DMACHAN_SETTING(STM32L4_DMA2_CHAN5, 2) -#define DMACHAN_UART4_TX DMACHAN_SETTING(STM32L4_DMA2_CHAN3, 2) +#define DMACHAN_UART4_RX DMACHAN_SETTING(STM32_DMA2_CHAN5, 2) +#define DMACHAN_UART4_TX DMACHAN_SETTING(STM32_DMA2_CHAN3, 2) -#define DMACHAN_LPUART_RX DMACHAN_SETTING(STM32L4_DMA2_CHAN7, 4) -#define DMACHAN_LPUART_TX DMACHAN_SETTING(STM32L4_DMA2_CHAN6, 4) +#define DMACHAN_LPUART_RX DMACHAN_SETTING(STM32_DMA2_CHAN7, 4) +#define DMACHAN_LPUART_TX DMACHAN_SETTING(STM32_DMA2_CHAN6, 4) #endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4X6XX_DMA_H */ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4x6xx_firewall.h b/arch/arm/src/stm32l4/hardware/stm32l4x6xx_firewall.h index 4272f345b7604..6428f606e4b1a 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4x6xx_firewall.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4x6xx_firewall.h @@ -38,23 +38,23 @@ /* Register Offsets *********************************************************/ -#define STM32L4_FIREWALL_CSSA_OFFSET 0x0000 -#define STM32L4_FIREWALL_CSL_OFFSET 0x0004 -#define STM32L4_FIREWALL_NVDSSA_OFFSET 0x0008 -#define STM32L4_FIREWALL_NVDSL_OFFSET 0x000c -#define STM32L4_FIREWALL_VDSSA_OFFSET 0x0010 -#define STM32L4_FIREWALL_VDSL_OFFSET 0x0014 -#define STM32L4_FIREWALL_CR_OFFSET 0x0020 +#define STM32_FIREWALL_CSSA_OFFSET 0x0000 +#define STM32_FIREWALL_CSL_OFFSET 0x0004 +#define STM32_FIREWALL_NVDSSA_OFFSET 0x0008 +#define STM32_FIREWALL_NVDSL_OFFSET 0x000c +#define STM32_FIREWALL_VDSSA_OFFSET 0x0010 +#define STM32_FIREWALL_VDSL_OFFSET 0x0014 +#define STM32_FIREWALL_CR_OFFSET 0x0020 /* Register Addresses *******************************************************/ -#define STM32L4_FIREWALL_CSSA (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_CSSA_OFFSET) -#define STM32L4_FIREWALL_CSL (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_CSL_OFFSET) -#define STM32L4_FIREWALL_NVDSSA (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_NVDSSA_OFFSET) -#define STM32L4_FIREWALL_NVDSL (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_NVDSL_OFFSET) -#define STM32L4_FIREWALL_VDSSA (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_VDSSA_OFFSET) -#define STM32L4_FIREWALL_VDSL (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_VDSL_OFFSET) -#define STM32L4_FIREWALL_CR (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_CR_OFFSET) +#define STM32_FIREWALL_CSSA (STM32_FIREWALL_BASE+STM32_FIREWALL_CSSA_OFFSET) +#define STM32_FIREWALL_CSL (STM32_FIREWALL_BASE+STM32_FIREWALL_CSL_OFFSET) +#define STM32_FIREWALL_NVDSSA (STM32_FIREWALL_BASE+STM32_FIREWALL_NVDSSA_OFFSET) +#define STM32_FIREWALL_NVDSL (STM32_FIREWALL_BASE+STM32_FIREWALL_NVDSL_OFFSET) +#define STM32_FIREWALL_VDSSA (STM32_FIREWALL_BASE+STM32_FIREWALL_VDSSA_OFFSET) +#define STM32_FIREWALL_VDSL (STM32_FIREWALL_BASE+STM32_FIREWALL_VDSL_OFFSET) +#define STM32_FIREWALL_CR (STM32_FIREWALL_BASE+STM32_FIREWALL_CR_OFFSET) /* Register Bitfield Definitions ********************************************/ @@ -81,7 +81,7 @@ /* Volatile Data Segment Start Address */ #define FIREWALL_VDSADD_SHIFT 6 -#if defined(CONFIG_STM32L4_STM32L496XX) +#if defined(CONFIG_STM32_STM32L496XX) # define FIREWALL_VDSADD_MASK (0x0fff << FIREWALL_VDSADD_SHIFT) #else # define FIREWALL_VDSADD_MASK (0x07ff << FIREWALL_VDSADD_SHIFT) @@ -90,7 +90,7 @@ /* Volatile Data Segment Length */ #define FIREWALL_VDSLENG_SHIFT 6 -#if defined(CONFIG_STM32L4_STM32L496XX) +#if defined(CONFIG_STM32_STM32L496XX) # define FIREWALL_VDSLENG_MASK (0x0fff << FIREWALL_VDSLENG_SHIFT) #else # define FIREWALL_VDSLENG_MASK (0x07ff << FIREWALL_VDSLENG_SHIFT) diff --git a/arch/arm/src/stm32l4/hardware/stm32l4x6xx_otgfs.h b/arch/arm/src/stm32l4/hardware/stm32l4x6xx_otgfs.h index 12288d4b39f99..c92296e69f669 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4x6xx_otgfs.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4x6xx_otgfs.h @@ -48,182 +48,182 @@ /* Core global control and status registers */ -#define STM32L4_OTGFS_GOTGCTL_OFFSET 0x0000 /* Control and status register */ -#define STM32L4_OTGFS_GOTGINT_OFFSET 0x0004 /* Interrupt register */ -#define STM32L4_OTGFS_GAHBCFG_OFFSET 0x0008 /* AHB configuration register */ -#define STM32L4_OTGFS_GUSBCFG_OFFSET 0x000c /* USB configuration register */ -#define STM32L4_OTGFS_GRSTCTL_OFFSET 0x0010 /* Reset register */ -#define STM32L4_OTGFS_GINTSTS_OFFSET 0x0014 /* Core interrupt register */ -#define STM32L4_OTGFS_GINTMSK_OFFSET 0x0018 /* Interrupt mask register */ -#define STM32L4_OTGFS_GRXSTSR_OFFSET 0x001c /* Receive status debug read/OTG status read register */ -#define STM32L4_OTGFS_GRXSTSP_OFFSET 0x0020 /* Receive status debug read/OTG status pop register */ -#define STM32L4_OTGFS_GRXFSIZ_OFFSET 0x0024 /* Receive FIFO size register */ -#define STM32L4_OTGFS_HNPTXFSIZ_OFFSET 0x0028 /* Host non-periodic transmit FIFO size register */ -#define STM32L4_OTGFS_DIEPTXF0_OFFSET 0x0028 /* Endpoint 0 Transmit FIFO size */ -#define STM32L4_OTGFS_HNPTXSTS_OFFSET 0x002c /* Non-periodic transmit FIFO/queue status register */ -#define STM32L4_OTGFS_GCCFG_OFFSET 0x0038 /* General core configuration register */ -#define STM32L4_OTGFS_CID_OFFSET 0x003c /* Core ID register */ -#define STM32L4_OTGFS_GLPMCFG_OFFSET 0x0054 /* LPM configuration register */ -#define STM32L4_OTGFS_GPWRDN_OFFSET 0x0058 /* Power down register */ -#define STM32L4_OTGFS_GADPCTL_OFSSET 0x0060 /* ADP timer, control and status register */ -#define STM32L4_OTGFS_HPTXFSIZ_OFFSET 0x0100 /* Host periodic transmit FIFO size register */ - -#define STM32L4_OTGFS_DIEPTXF_OFFSET(n) (0x0104+(((n)-1) << 2)) +#define STM32_OTGFS_GOTGCTL_OFFSET 0x0000 /* Control and status register */ +#define STM32_OTGFS_GOTGINT_OFFSET 0x0004 /* Interrupt register */ +#define STM32_OTGFS_GAHBCFG_OFFSET 0x0008 /* AHB configuration register */ +#define STM32_OTGFS_GUSBCFG_OFFSET 0x000c /* USB configuration register */ +#define STM32_OTGFS_GRSTCTL_OFFSET 0x0010 /* Reset register */ +#define STM32_OTGFS_GINTSTS_OFFSET 0x0014 /* Core interrupt register */ +#define STM32_OTGFS_GINTMSK_OFFSET 0x0018 /* Interrupt mask register */ +#define STM32_OTGFS_GRXSTSR_OFFSET 0x001c /* Receive status debug read/OTG status read register */ +#define STM32_OTGFS_GRXSTSP_OFFSET 0x0020 /* Receive status debug read/OTG status pop register */ +#define STM32_OTGFS_GRXFSIZ_OFFSET 0x0024 /* Receive FIFO size register */ +#define STM32_OTGFS_HNPTXFSIZ_OFFSET 0x0028 /* Host non-periodic transmit FIFO size register */ +#define STM32_OTGFS_DIEPTXF0_OFFSET 0x0028 /* Endpoint 0 Transmit FIFO size */ +#define STM32_OTGFS_HNPTXSTS_OFFSET 0x002c /* Non-periodic transmit FIFO/queue status register */ +#define STM32_OTGFS_GCCFG_OFFSET 0x0038 /* General core configuration register */ +#define STM32_OTGFS_CID_OFFSET 0x003c /* Core ID register */ +#define STM32_OTGFS_GLPMCFG_OFFSET 0x0054 /* LPM configuration register */ +#define STM32_OTGFS_GPWRDN_OFFSET 0x0058 /* Power down register */ +#define STM32_OTGFS_GADPCTL_OFSSET 0x0060 /* ADP timer, control and status register */ +#define STM32_OTGFS_HPTXFSIZ_OFFSET 0x0100 /* Host periodic transmit FIFO size register */ + +#define STM32_OTGFS_DIEPTXF_OFFSET(n) (0x0104+(((n)-1) << 2)) /* Host-mode control and status registers */ -#define STM32L4_OTGFS_HCFG_OFFSET 0x0400 /* Host configuration register */ -#define STM32L4_OTGFS_HFIR_OFFSET 0x0404 /* Host frame interval register */ -#define STM32L4_OTGFS_HFNUM_OFFSET 0x0408 /* Host frame number/frame time remaining register */ -#define STM32L4_OTGFS_HPTXSTS_OFFSET 0x0410 /* Host periodic transmit FIFO/queue status register */ -#define STM32L4_OTGFS_HAINT_OFFSET 0x0414 /* Host all channels interrupt register */ -#define STM32L4_OTGFS_HAINTMSK_OFFSET 0x0418 /* Host all channels interrupt mask register */ -#define STM32L4_OTGFS_HPRT_OFFSET 0x0440 /* Host port control and status register */ +#define STM32_OTGFS_HCFG_OFFSET 0x0400 /* Host configuration register */ +#define STM32_OTGFS_HFIR_OFFSET 0x0404 /* Host frame interval register */ +#define STM32_OTGFS_HFNUM_OFFSET 0x0408 /* Host frame number/frame time remaining register */ +#define STM32_OTGFS_HPTXSTS_OFFSET 0x0410 /* Host periodic transmit FIFO/queue status register */ +#define STM32_OTGFS_HAINT_OFFSET 0x0414 /* Host all channels interrupt register */ +#define STM32_OTGFS_HAINTMSK_OFFSET 0x0418 /* Host all channels interrupt mask register */ +#define STM32_OTGFS_HPRT_OFFSET 0x0440 /* Host port control and status register */ -#define STM32L4_OTGFS_CHAN_OFFSET(n) (0x500 + ((n) << 5) -#define STM32L4_OTGFS_HCCHAR_CHOFFSET 0x0000 /* Host channel characteristics register */ -#define STM32L4_OTGFS_HCINT_CHOFFSET 0x0008 /* Host channel interrupt register */ -#define STM32L4_OTGFS_HCINTMSK_CHOFFSET 0x000c /* Host channel interrupt mask register */ -#define STM32L4_OTGFS_HCTSIZ_CHOFFSET 0x0010 /* Host channel interrupt register */ +#define STM32_OTGFS_CHAN_OFFSET(n) (0x500 + ((n) << 5) +#define STM32_OTGFS_HCCHAR_CHOFFSET 0x0000 /* Host channel characteristics register */ +#define STM32_OTGFS_HCINT_CHOFFSET 0x0008 /* Host channel interrupt register */ +#define STM32_OTGFS_HCINTMSK_CHOFFSET 0x000c /* Host channel interrupt mask register */ +#define STM32_OTGFS_HCTSIZ_CHOFFSET 0x0010 /* Host channel interrupt register */ -#define STM32L4_OTGFS_HCCHAR_OFFSET(n) (0x500 + ((n) << 5)) +#define STM32_OTGFS_HCCHAR_OFFSET(n) (0x500 + ((n) << 5)) -#define STM32L4_OTGFS_HCINT_OFFSET(n) (0x508 + ((n) << 5)) +#define STM32_OTGFS_HCINT_OFFSET(n) (0x508 + ((n) << 5)) -#define STM32L4_OTGFS_HCINTMSK_OFFSET(n) (0x50c + ((n) << 5)) +#define STM32_OTGFS_HCINTMSK_OFFSET(n) (0x50c + ((n) << 5)) -#define STM32L4_OTGFS_HCTSIZ_OFFSET(n) (0x510 + ((n) << 5)) +#define STM32_OTGFS_HCTSIZ_OFFSET(n) (0x510 + ((n) << 5)) /* Device-mode control and status registers */ -#define STM32L4_OTGFS_DCFG_OFFSET 0x0800 /* Device configuration register */ -#define STM32L4_OTGFS_DCTL_OFFSET 0x0804 /* Device control register */ -#define STM32L4_OTGFS_DSTS_OFFSET 0x0808 /* Device status register */ -#define STM32L4_OTGFS_DIEPMSK_OFFSET 0x0810 /* Device IN endpoint common interrupt mask register */ -#define STM32L4_OTGFS_DOEPMSK_OFFSET 0x0814 /* Device OUT endpoint common interrupt mask register */ -#define STM32L4_OTGFS_DAINT_OFFSET 0x0818 /* Device all endpoints interrupt register */ -#define STM32L4_OTGFS_DAINTMSK_OFFSET 0x081c /* All endpoints interrupt mask register */ -#define STM32L4_OTGFS_DVBUSDIS_OFFSET 0x0828 /* Device VBUS discharge time register */ -#define STM32L4_OTGFS_DVBUSPULSE_OFFSET 0x082c /* Device VBUS pulsing time register */ -#define STM32L4_OTGFS_DIEPEMPMSK_OFFSET 0x0834 /* Device IN endpoint FIFO empty interrupt mask register */ +#define STM32_OTGFS_DCFG_OFFSET 0x0800 /* Device configuration register */ +#define STM32_OTGFS_DCTL_OFFSET 0x0804 /* Device control register */ +#define STM32_OTGFS_DSTS_OFFSET 0x0808 /* Device status register */ +#define STM32_OTGFS_DIEPMSK_OFFSET 0x0810 /* Device IN endpoint common interrupt mask register */ +#define STM32_OTGFS_DOEPMSK_OFFSET 0x0814 /* Device OUT endpoint common interrupt mask register */ +#define STM32_OTGFS_DAINT_OFFSET 0x0818 /* Device all endpoints interrupt register */ +#define STM32_OTGFS_DAINTMSK_OFFSET 0x081c /* All endpoints interrupt mask register */ +#define STM32_OTGFS_DVBUSDIS_OFFSET 0x0828 /* Device VBUS discharge time register */ +#define STM32_OTGFS_DVBUSPULSE_OFFSET 0x082c /* Device VBUS pulsing time register */ +#define STM32_OTGFS_DIEPEMPMSK_OFFSET 0x0834 /* Device IN endpoint FIFO empty interrupt mask register */ -#define STM32L4_OTGFS_DIEP_OFFSET(n) (0x0900 + ((n) << 5)) -#define STM32L4_OTGFS_DIEPCTL_EPOFFSET 0x0000 /* Device endpoint control register */ -#define STM32L4_OTGFS_DIEPINT_EPOFFSET 0x0008 /* Device endpoint interrupt register */ -#define STM32L4_OTGFS_DIEPTSIZ_EPOFFSET 0x0010 /* Device IN endpoint transfer size register */ -#define STM32L4_OTGFS_DTXFSTS_EPOFFSET 0x0018 /* Device IN endpoint transmit FIFO status register */ +#define STM32_OTGFS_DIEP_OFFSET(n) (0x0900 + ((n) << 5)) +#define STM32_OTGFS_DIEPCTL_EPOFFSET 0x0000 /* Device endpoint control register */ +#define STM32_OTGFS_DIEPINT_EPOFFSET 0x0008 /* Device endpoint interrupt register */ +#define STM32_OTGFS_DIEPTSIZ_EPOFFSET 0x0010 /* Device IN endpoint transfer size register */ +#define STM32_OTGFS_DTXFSTS_EPOFFSET 0x0018 /* Device IN endpoint transmit FIFO status register */ -#define STM32L4_OTGFS_DIEPCTL_OFFSET(n) (0x0900 + ((n) << 5)) +#define STM32_OTGFS_DIEPCTL_OFFSET(n) (0x0900 + ((n) << 5)) -#define STM32L4_OTGFS_DIEPINT_OFFSET(n) (0x0908 + ((n) << 5)) +#define STM32_OTGFS_DIEPINT_OFFSET(n) (0x0908 + ((n) << 5)) -#define STM32L4_OTGFS_DIEPTSIZ_OFFSET(n) (0x910 + ((n) << 5)) +#define STM32_OTGFS_DIEPTSIZ_OFFSET(n) (0x910 + ((n) << 5)) -#define STM32L4_OTGFS_DTXFSTS_OFFSET(n) (0x0918 + ((n) << 5)) +#define STM32_OTGFS_DTXFSTS_OFFSET(n) (0x0918 + ((n) << 5)) -#define STM32L4_OTGFS_DOEP_OFFSET(n) (0x0b00 + ((n) << 5)) -#define STM32L4_OTGFS_DOEPCTL_EPOFFSET 0x0000 /* Device control OUT endpoint 0 control register */ -#define STM32L4_OTGFS_DOEPINT_EPOFFSET 0x0008 /* Device endpoint-x interrupt register */ -#define STM32L4_OTGFS_DOEPTSIZ_EPOFFSET 0x0010 /* Device endpoint OUT transfer size register */ +#define STM32_OTGFS_DOEP_OFFSET(n) (0x0b00 + ((n) << 5)) +#define STM32_OTGFS_DOEPCTL_EPOFFSET 0x0000 /* Device control OUT endpoint 0 control register */ +#define STM32_OTGFS_DOEPINT_EPOFFSET 0x0008 /* Device endpoint-x interrupt register */ +#define STM32_OTGFS_DOEPTSIZ_EPOFFSET 0x0010 /* Device endpoint OUT transfer size register */ -#define STM32L4_OTGFS_DOEPCTL_OFFSET(n) (0x0b00 + ((n) << 5)) +#define STM32_OTGFS_DOEPCTL_OFFSET(n) (0x0b00 + ((n) << 5)) -#define STM32L4_OTGFS_DOEPINT_OFFSET(n) (0x0b08 + ((n) << 5)) +#define STM32_OTGFS_DOEPINT_OFFSET(n) (0x0b08 + ((n) << 5)) -#define STM32L4_OTGFS_DOEPTSIZ_OFFSET(n) (0x0b10 + ((n) << 5)) +#define STM32_OTGFS_DOEPTSIZ_OFFSET(n) (0x0b10 + ((n) << 5)) /* Power and clock gating registers */ -#define STM32L4_OTGFS_PCGCCTL_OFFSET 0x0e00 /* Power and clock gating control register */ +#define STM32_OTGFS_PCGCCTL_OFFSET 0x0e00 /* Power and clock gating control register */ /* Data FIFO (DFIFO) access registers */ -#define STM32L4_OTGFS_DFIFO_DEP_OFFSET(n) (0x1000 + ((n) << 12)) -#define STM32L4_OTGFS_DFIFO_HCH_OFFSET(n) (0x1000 + ((n) << 12)) +#define STM32_OTGFS_DFIFO_DEP_OFFSET(n) (0x1000 + ((n) << 12)) +#define STM32_OTGFS_DFIFO_HCH_OFFSET(n) (0x1000 + ((n) << 12)) /* Register Addresses *******************************************************/ -#define STM32L4_OTGFS_GOTGCTL (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GOTGCTL_OFFSET) -#define STM32L4_OTGFS_GOTGINT (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GOTGINT_OFFSET) -#define STM32L4_OTGFS_GAHBCFG (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GAHBCFG_OFFSET) -#define STM32L4_OTGFS_GUSBCFG (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GUSBCFG_OFFSET) -#define STM32L4_OTGFS_GRSTCTL (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GRSTCTL_OFFSET) -#define STM32L4_OTGFS_GINTSTS (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GINTSTS_OFFSET) -#define STM32L4_OTGFS_GINTMSK (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GINTMSK_OFFSET) -#define STM32L4_OTGFS_GRXSTSR (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GRXSTSR_OFFSET) -#define STM32L4_OTGFS_GRXSTSP (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GRXSTSP_OFFSET) -#define STM32L4_OTGFS_GRXFSIZ (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GRXFSIZ_OFFSET) -#define STM32L4_OTGFS_HNPTXFSIZ (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HNPTXFSIZ_OFFSET) -#define STM32L4_OTGFS_DIEPTXF0 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DIEPTXF0_OFFSET) -#define STM32L4_OTGFS_HNPTXSTS (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HNPTXSTS_OFFSET) -#define STM32L4_OTGFS_GCCFG (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GCCFG_OFFSET) -#define STM32L4_OTGFS_CID (STM32L4_OTGFS_BASE+STM32L4_OTGFS_CID_OFFSET) -#define STM32L4_OTGFS_GLPMCFG (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GLPMCFG_OFFSET) -#define STM32L4_OTGFS_GPWRDN (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GPWRDN_OFFSET) -#define STM32L4_OTGFS_GADPCTL (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GADPCTL_OFSSET) -#define STM32L4_OTGFS_HPTXFSIZ (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HPTXFSIZ_OFFSET) - -#define STM32L4_OTGFS_DIEPTXF(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DIEPTXF_OFFSET(n)) +#define STM32_OTGFS_GOTGCTL (STM32_OTGFS_BASE+STM32_OTGFS_GOTGCTL_OFFSET) +#define STM32_OTGFS_GOTGINT (STM32_OTGFS_BASE+STM32_OTGFS_GOTGINT_OFFSET) +#define STM32_OTGFS_GAHBCFG (STM32_OTGFS_BASE+STM32_OTGFS_GAHBCFG_OFFSET) +#define STM32_OTGFS_GUSBCFG (STM32_OTGFS_BASE+STM32_OTGFS_GUSBCFG_OFFSET) +#define STM32_OTGFS_GRSTCTL (STM32_OTGFS_BASE+STM32_OTGFS_GRSTCTL_OFFSET) +#define STM32_OTGFS_GINTSTS (STM32_OTGFS_BASE+STM32_OTGFS_GINTSTS_OFFSET) +#define STM32_OTGFS_GINTMSK (STM32_OTGFS_BASE+STM32_OTGFS_GINTMSK_OFFSET) +#define STM32_OTGFS_GRXSTSR (STM32_OTGFS_BASE+STM32_OTGFS_GRXSTSR_OFFSET) +#define STM32_OTGFS_GRXSTSP (STM32_OTGFS_BASE+STM32_OTGFS_GRXSTSP_OFFSET) +#define STM32_OTGFS_GRXFSIZ (STM32_OTGFS_BASE+STM32_OTGFS_GRXFSIZ_OFFSET) +#define STM32_OTGFS_HNPTXFSIZ (STM32_OTGFS_BASE+STM32_OTGFS_HNPTXFSIZ_OFFSET) +#define STM32_OTGFS_DIEPTXF0 (STM32_OTGFS_BASE+STM32_OTGFS_DIEPTXF0_OFFSET) +#define STM32_OTGFS_HNPTXSTS (STM32_OTGFS_BASE+STM32_OTGFS_HNPTXSTS_OFFSET) +#define STM32_OTGFS_GCCFG (STM32_OTGFS_BASE+STM32_OTGFS_GCCFG_OFFSET) +#define STM32_OTGFS_CID (STM32_OTGFS_BASE+STM32_OTGFS_CID_OFFSET) +#define STM32_OTGFS_GLPMCFG (STM32_OTGFS_BASE+STM32_OTGFS_GLPMCFG_OFFSET) +#define STM32_OTGFS_GPWRDN (STM32_OTGFS_BASE+STM32_OTGFS_GPWRDN_OFFSET) +#define STM32_OTGFS_GADPCTL (STM32_OTGFS_BASE+STM32_OTGFS_GADPCTL_OFSSET) +#define STM32_OTGFS_HPTXFSIZ (STM32_OTGFS_BASE+STM32_OTGFS_HPTXFSIZ_OFFSET) + +#define STM32_OTGFS_DIEPTXF(n) (STM32_OTGFS_BASE+STM32_OTGFS_DIEPTXF_OFFSET(n)) /* Host-mode control and status registers */ -#define STM32L4_OTGFS_HCFG (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HCFG_OFFSET) -#define STM32L4_OTGFS_HFIR (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HFIR_OFFSET) -#define STM32L4_OTGFS_HFNUM (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HFNUM_OFFSET) -#define STM32L4_OTGFS_HPTXSTS (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HPTXSTS_OFFSET) -#define STM32L4_OTGFS_HAINT (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HAINT_OFFSET) -#define STM32L4_OTGFS_HAINTMSK (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HAINTMSK_OFFSET) -#define STM32L4_OTGFS_HPRT (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HPRT_OFFSET) +#define STM32_OTGFS_HCFG (STM32_OTGFS_BASE+STM32_OTGFS_HCFG_OFFSET) +#define STM32_OTGFS_HFIR (STM32_OTGFS_BASE+STM32_OTGFS_HFIR_OFFSET) +#define STM32_OTGFS_HFNUM (STM32_OTGFS_BASE+STM32_OTGFS_HFNUM_OFFSET) +#define STM32_OTGFS_HPTXSTS (STM32_OTGFS_BASE+STM32_OTGFS_HPTXSTS_OFFSET) +#define STM32_OTGFS_HAINT (STM32_OTGFS_BASE+STM32_OTGFS_HAINT_OFFSET) +#define STM32_OTGFS_HAINTMSK (STM32_OTGFS_BASE+STM32_OTGFS_HAINTMSK_OFFSET) +#define STM32_OTGFS_HPRT (STM32_OTGFS_BASE+STM32_OTGFS_HPRT_OFFSET) -#define STM32L4_OTGFS_CHAN(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_CHAN_OFFSET(n)) +#define STM32_OTGFS_CHAN(n) (STM32_OTGFS_BASE+STM32_OTGFS_CHAN_OFFSET(n)) -#define STM32L4_OTGFS_HCCHAR(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HCCHAR_OFFSET(n)) +#define STM32_OTGFS_HCCHAR(n) (STM32_OTGFS_BASE+STM32_OTGFS_HCCHAR_OFFSET(n)) -#define STM32L4_OTGFS_HCINT(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HCINT_OFFSET(n)) +#define STM32_OTGFS_HCINT(n) (STM32_OTGFS_BASE+STM32_OTGFS_HCINT_OFFSET(n)) -#define STM32L4_OTGFS_HCINTMSK(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HCINTMSK_OFFSET(n)) +#define STM32_OTGFS_HCINTMSK(n) (STM32_OTGFS_BASE+STM32_OTGFS_HCINTMSK_OFFSET(n)) -#define STM32L4_OTGFS_HCTSIZ(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HCTSIZ_OFFSET(n)) +#define STM32_OTGFS_HCTSIZ(n) (STM32_OTGFS_BASE+STM32_OTGFS_HCTSIZ_OFFSET(n)) /* Device-mode control and status registers */ -#define STM32L4_OTGFS_DCFG (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DCFG_OFFSET) -#define STM32L4_OTGFS_DCTL (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DCTL_OFFSET) -#define STM32L4_OTGFS_DSTS (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DSTS_OFFSET) -#define STM32L4_OTGFS_DIEPMSK (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DIEPMSK_OFFSET) -#define STM32L4_OTGFS_DOEPMSK (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DOEPMSK_OFFSET) -#define STM32L4_OTGFS_DAINT (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DAINT_OFFSET) -#define STM32L4_OTGFS_DAINTMSK (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DAINTMSK_OFFSET) -#define STM32L4_OTGFS_DVBUSDIS (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DVBUSDIS_OFFSET) -#define STM32L4_OTGFS_DVBUSPULSE (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DVBUSPULSE_OFFSET) -#define STM32L4_OTGFS_DIEPEMPMSK (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DIEPEMPMSK_OFFSET) +#define STM32_OTGFS_DCFG (STM32_OTGFS_BASE+STM32_OTGFS_DCFG_OFFSET) +#define STM32_OTGFS_DCTL (STM32_OTGFS_BASE+STM32_OTGFS_DCTL_OFFSET) +#define STM32_OTGFS_DSTS (STM32_OTGFS_BASE+STM32_OTGFS_DSTS_OFFSET) +#define STM32_OTGFS_DIEPMSK (STM32_OTGFS_BASE+STM32_OTGFS_DIEPMSK_OFFSET) +#define STM32_OTGFS_DOEPMSK (STM32_OTGFS_BASE+STM32_OTGFS_DOEPMSK_OFFSET) +#define STM32_OTGFS_DAINT (STM32_OTGFS_BASE+STM32_OTGFS_DAINT_OFFSET) +#define STM32_OTGFS_DAINTMSK (STM32_OTGFS_BASE+STM32_OTGFS_DAINTMSK_OFFSET) +#define STM32_OTGFS_DVBUSDIS (STM32_OTGFS_BASE+STM32_OTGFS_DVBUSDIS_OFFSET) +#define STM32_OTGFS_DVBUSPULSE (STM32_OTGFS_BASE+STM32_OTGFS_DVBUSPULSE_OFFSET) +#define STM32_OTGFS_DIEPEMPMSK (STM32_OTGFS_BASE+STM32_OTGFS_DIEPEMPMSK_OFFSET) -#define STM32L4_OTGFS_DIEP(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DIEP_OFFSET(n)) +#define STM32_OTGFS_DIEP(n) (STM32_OTGFS_BASE+STM32_OTGFS_DIEP_OFFSET(n)) -#define STM32L4_OTGFS_DIEPCTL(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DIEPCTL_OFFSET(n)) +#define STM32_OTGFS_DIEPCTL(n) (STM32_OTGFS_BASE+STM32_OTGFS_DIEPCTL_OFFSET(n)) -#define STM32L4_OTGFS_DIEPINT(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DIEPINT_OFFSET(n)) +#define STM32_OTGFS_DIEPINT(n) (STM32_OTGFS_BASE+STM32_OTGFS_DIEPINT_OFFSET(n)) -#define STM32L4_OTGFS_DIEPTSIZ(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DIEPTSIZ_OFFSET(n)) +#define STM32_OTGFS_DIEPTSIZ(n) (STM32_OTGFS_BASE+STM32_OTGFS_DIEPTSIZ_OFFSET(n)) -#define STM32L4_OTGFS_DTXFSTS(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DTXFSTS_OFFSET(n)) +#define STM32_OTGFS_DTXFSTS(n) (STM32_OTGFS_BASE+STM32_OTGFS_DTXFSTS_OFFSET(n)) -#define STM32L4_OTGFS_DOEP(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DOEP_OFFSET(n)) +#define STM32_OTGFS_DOEP(n) (STM32_OTGFS_BASE+STM32_OTGFS_DOEP_OFFSET(n)) -#define STM32L4_OTGFS_DOEPCTL(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DOEPCTL_OFFSET(n)) +#define STM32_OTGFS_DOEPCTL(n) (STM32_OTGFS_BASE+STM32_OTGFS_DOEPCTL_OFFSET(n)) -#define STM32L4_OTGFS_DOEPINT(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DOEPINT_OFFSET(n)) +#define STM32_OTGFS_DOEPINT(n) (STM32_OTGFS_BASE+STM32_OTGFS_DOEPINT_OFFSET(n)) -#define STM32L4_OTGFS_DOEPTSIZ(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DOEPTSIZ_OFFSET(n)) +#define STM32_OTGFS_DOEPTSIZ(n) (STM32_OTGFS_BASE+STM32_OTGFS_DOEPTSIZ_OFFSET(n)) /* Power and clock gating registers */ -#define STM32L4_OTGFS_PCGCCTL (STM32L4_OTGFS_BASE+STM32L4_OTGFS_PCGCCTL_OFFSET) +#define STM32_OTGFS_PCGCCTL (STM32_OTGFS_BASE+STM32_OTGFS_PCGCCTL_OFFSET) /* Data FIFO (DFIFO) access registers */ -#define STM32L4_OTGFS_DFIFO_DEP(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DFIFO_DEP_OFFSET(n)) -#define STM32L4_OTGFS_DFIFO_HCH(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DFIFO_HCH_OFFSET(n)) +#define STM32_OTGFS_DFIFO_DEP(n) (STM32_OTGFS_BASE+STM32_OTGFS_DFIFO_DEP_OFFSET(n)) +#define STM32_OTGFS_DFIFO_HCH(n) (STM32_OTGFS_BASE+STM32_OTGFS_DFIFO_HCH_OFFSET(n)) /* Register Bitfield Definitions ********************************************/ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4x6xx_rcc.h b/arch/arm/src/stm32l4/hardware/stm32l4x6xx_rcc.h index 991c15297562a..29a19f63a1457 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4x6xx_rcc.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4x6xx_rcc.h @@ -29,7 +29,7 @@ #include -#if defined(CONFIG_STM32L4_STM32L4X6) +#if defined(CONFIG_STM32_STM32L4X6) /**************************************************************************** * Pre-processor Definitions @@ -37,73 +37,73 @@ /* Register Offsets *********************************************************/ -#define STM32L4_RCC_CR_OFFSET 0x0000 /* Clock control register */ -#define STM32L4_RCC_ICSCR_OFFSET 0x0004 /* Internal clock sources calibration register */ -#define STM32L4_RCC_CFGR_OFFSET 0x0008 /* Clock configuration register */ -#define STM32L4_RCC_PLLCFG_OFFSET 0x000c /* PLL configuration register */ -#define STM32L4_RCC_PLLSAI1CFG_OFFSET 0x0010 /* PLLSAI1 configuration register */ -#define STM32L4_RCC_PLLSAI2CFG_OFFSET 0x0014 /* PLLSAI2 configuration register */ -#define STM32L4_RCC_CIER_OFFSET 0x0018 /* Clock interrupt enable register */ -#define STM32L4_RCC_CIFR_OFFSET 0x001c /* Clock interrupt flag register */ -#define STM32L4_RCC_CICR_OFFSET 0x0020 /* Clock interrupt clear register */ -#define STM32L4_RCC_AHB1RSTR_OFFSET 0x0028 /* AHB1 peripheral reset register */ -#define STM32L4_RCC_AHB2RSTR_OFFSET 0x002c /* AHB2 peripheral reset register */ -#define STM32L4_RCC_AHB3RSTR_OFFSET 0x0030 /* AHB3 peripheral reset register */ -#define STM32L4_RCC_APB1RSTR1_OFFSET 0x0038 /* APB1 Peripheral reset register 1 */ -#define STM32L4_RCC_APB1RSTR2_OFFSET 0x003c /* APB1 Peripheral reset register 2 */ -#define STM32L4_RCC_APB2RSTR_OFFSET 0x0040 /* APB2 Peripheral reset register */ -#define STM32L4_RCC_AHB1ENR_OFFSET 0x0048 /* AHB1 Peripheral Clock enable register */ -#define STM32L4_RCC_AHB2ENR_OFFSET 0x004c /* AHB2 Peripheral Clock enable register */ -#define STM32L4_RCC_AHB3ENR_OFFSET 0x0050 /* AHB3 Peripheral Clock enable register */ -#define STM32L4_RCC_APB1ENR1_OFFSET 0x0058 /* APB1 Peripheral Clock enable register 1 */ -#define STM32L4_RCC_APB1ENR2_OFFSET 0x005c /* APB1 Peripheral Clock enable register 2 */ -#define STM32L4_RCC_APB2ENR_OFFSET 0x0060 /* APB2 Peripheral Clock enable register */ -#define STM32L4_RCC_AHB1SMENR_OFFSET 0x0068 /* RCC AHB1 low power mode peripheral clock enable register */ -#define STM32L4_RCC_AHB2SMENR_OFFSET 0x006c /* RCC AHB2 low power mode peripheral clock enable register */ -#define STM32L4_RCC_AHB3SMENR_OFFSET 0x0070 /* RCC AHB3 low power mode peripheral clock enable register */ -#define STM32L4_RCC_APB1SMENR1_OFFSET 0x0078 /* RCC APB1 low power mode peripheral clock enable register 1 */ -#define STM32L4_RCC_APB1SMENR2_OFFSET 0x007c /* RCC APB1 low power mode peripheral clock enable register 2 */ -#define STM32L4_RCC_APB2SMENR_OFFSET 0x0080 /* RCC APB2 low power mode peripheral clock enable register */ -#define STM32L4_RCC_CCIPR_OFFSET 0x0088 /* Peripherals independent clock configuration register 1 */ -#define STM32L4_RCC_BDCR_OFFSET 0x0090 /* Backup domain control register */ -#define STM32L4_RCC_CSR_OFFSET 0x0094 /* Control/status register */ -#define STM32L4_RCC_CRRCR_OFFSET 0x0098 /* Clock recovery RC register */ -#define STM32L4_RCC_CCIPR2_OFFSET 0x009c /* Peripherals independent clock configuration register 2 */ +#define STM32_RCC_CR_OFFSET 0x0000 /* Clock control register */ +#define STM32_RCC_ICSCR_OFFSET 0x0004 /* Internal clock sources calibration register */ +#define STM32_RCC_CFGR_OFFSET 0x0008 /* Clock configuration register */ +#define STM32_RCC_PLLCFG_OFFSET 0x000c /* PLL configuration register */ +#define STM32_RCC_PLLSAI1CFG_OFFSET 0x0010 /* PLLSAI1 configuration register */ +#define STM32_RCC_PLLSAI2CFG_OFFSET 0x0014 /* PLLSAI2 configuration register */ +#define STM32_RCC_CIER_OFFSET 0x0018 /* Clock interrupt enable register */ +#define STM32_RCC_CIFR_OFFSET 0x001c /* Clock interrupt flag register */ +#define STM32_RCC_CICR_OFFSET 0x0020 /* Clock interrupt clear register */ +#define STM32_RCC_AHB1RSTR_OFFSET 0x0028 /* AHB1 peripheral reset register */ +#define STM32_RCC_AHB2RSTR_OFFSET 0x002c /* AHB2 peripheral reset register */ +#define STM32_RCC_AHB3RSTR_OFFSET 0x0030 /* AHB3 peripheral reset register */ +#define STM32_RCC_APB1RSTR1_OFFSET 0x0038 /* APB1 Peripheral reset register 1 */ +#define STM32_RCC_APB1RSTR2_OFFSET 0x003c /* APB1 Peripheral reset register 2 */ +#define STM32_RCC_APB2RSTR_OFFSET 0x0040 /* APB2 Peripheral reset register */ +#define STM32_RCC_AHB1ENR_OFFSET 0x0048 /* AHB1 Peripheral Clock enable register */ +#define STM32_RCC_AHB2ENR_OFFSET 0x004c /* AHB2 Peripheral Clock enable register */ +#define STM32_RCC_AHB3ENR_OFFSET 0x0050 /* AHB3 Peripheral Clock enable register */ +#define STM32_RCC_APB1ENR1_OFFSET 0x0058 /* APB1 Peripheral Clock enable register 1 */ +#define STM32_RCC_APB1ENR2_OFFSET 0x005c /* APB1 Peripheral Clock enable register 2 */ +#define STM32_RCC_APB2ENR_OFFSET 0x0060 /* APB2 Peripheral Clock enable register */ +#define STM32_RCC_AHB1SMENR_OFFSET 0x0068 /* RCC AHB1 low power mode peripheral clock enable register */ +#define STM32_RCC_AHB2SMENR_OFFSET 0x006c /* RCC AHB2 low power mode peripheral clock enable register */ +#define STM32_RCC_AHB3SMENR_OFFSET 0x0070 /* RCC AHB3 low power mode peripheral clock enable register */ +#define STM32_RCC_APB1SMENR1_OFFSET 0x0078 /* RCC APB1 low power mode peripheral clock enable register 1 */ +#define STM32_RCC_APB1SMENR2_OFFSET 0x007c /* RCC APB1 low power mode peripheral clock enable register 2 */ +#define STM32_RCC_APB2SMENR_OFFSET 0x0080 /* RCC APB2 low power mode peripheral clock enable register */ +#define STM32_RCC_CCIPR_OFFSET 0x0088 /* Peripherals independent clock configuration register 1 */ +#define STM32_RCC_BDCR_OFFSET 0x0090 /* Backup domain control register */ +#define STM32_RCC_CSR_OFFSET 0x0094 /* Control/status register */ +#define STM32_RCC_CRRCR_OFFSET 0x0098 /* Clock recovery RC register */ +#define STM32_RCC_CCIPR2_OFFSET 0x009c /* Peripherals independent clock configuration register 2 */ /* Register Addresses *******************************************************/ -#define STM32L4_RCC_CR (STM32L4_RCC_BASE+STM32L4_RCC_CR_OFFSET) -#define STM32L4_RCC_ICSCR (STM32L4_RCC_BASE+STM32L4_RCC_ICSCR_OFFSET) -#define STM32L4_RCC_CFGR (STM32L4_RCC_BASE+STM32L4_RCC_CFGR_OFFSET) -#define STM32L4_RCC_PLLCFG (STM32L4_RCC_BASE+STM32L4_RCC_PLLCFG_OFFSET) -#define STM32L4_RCC_PLLSAI1CFG (STM32L4_RCC_BASE+STM32L4_RCC_PLLSAI1CFG_OFFSET) -#define STM32L4_RCC_PLLSAI2CFG (STM32L4_RCC_BASE+STM32L4_RCC_PLLSAI2CFG_OFFSET) -#define STM32L4_RCC_CIER (STM32L4_RCC_BASE+STM32L4_RCC_CIER_OFFSET) -#define STM32L4_RCC_CIFR (STM32L4_RCC_BASE+STM32L4_RCC_CIFR_OFFSET) -#define STM32L4_RCC_CICR (STM32L4_RCC_BASE+STM32L4_RCC_CICR_OFFSET) -#define STM32L4_RCC_AHB1RSTR (STM32L4_RCC_BASE+STM32L4_RCC_AHB1RSTR_OFFSET) -#define STM32L4_RCC_AHB2RSTR (STM32L4_RCC_BASE+STM32L4_RCC_AHB2RSTR_OFFSET) -#define STM32L4_RCC_AHB3RSTR (STM32L4_RCC_BASE+STM32L4_RCC_AHB3RSTR_OFFSET) -#define STM32L4_RCC_APB1RSTR1 (STM32L4_RCC_BASE+STM32L4_RCC_APB1RSTR1_OFFSET) -#define STM32L4_RCC_APB1RSTR2 (STM32L4_RCC_BASE+STM32L4_RCC_APB1RSTR2_OFFSET) -#define STM32L4_RCC_APB2RSTR (STM32L4_RCC_BASE+STM32L4_RCC_APB2RSTR_OFFSET) -#define STM32L4_RCC_AHB1ENR (STM32L4_RCC_BASE+STM32L4_RCC_AHB1ENR_OFFSET) -#define STM32L4_RCC_AHB2ENR (STM32L4_RCC_BASE+STM32L4_RCC_AHB2ENR_OFFSET) -#define STM32L4_RCC_AHB3ENR (STM32L4_RCC_BASE+STM32L4_RCC_AHB3ENR_OFFSET) -#define STM32L4_RCC_APB1ENR1 (STM32L4_RCC_BASE+STM32L4_RCC_APB1ENR1_OFFSET) -#define STM32L4_RCC_APB1ENR2 (STM32L4_RCC_BASE+STM32L4_RCC_APB1ENR2_OFFSET) -#define STM32L4_RCC_APB2ENR (STM32L4_RCC_BASE+STM32L4_RCC_APB2ENR_OFFSET) -#define STM32L4_RCC_AHB1SMENR (STM32L4_RCC_BASE+STM32L4_RCC_AHB1SMENR_OFFSET) -#define STM32L4_RCC_AHB2SMENR (STM32L4_RCC_BASE+STM32L4_RCC_AHB2SMENR_OFFSET) -#define STM32L4_RCC_AHB3SMENR (STM32L4_RCC_BASE+STM32L4_RCC_AHB3SMENR_OFFSET) -#define STM32L4_RCC_APB1SMENR1 (STM32L4_RCC_BASE+STM32L4_RCC_APB1SMENR1_OFFSET) -#define STM32L4_RCC_APB1SMENR2 (STM32L4_RCC_BASE+STM32L4_RCC_APB1SMENR2_OFFSET) -#define STM32L4_RCC_APB2SMENR (STM32L4_RCC_BASE+STM32L4_RCC_APB2SMENR_OFFSET) -#define STM32L4_RCC_CCIPR (STM32L4_RCC_BASE+STM32L4_RCC_CCIPR_OFFSET) -#define STM32L4_RCC_BDCR (STM32L4_RCC_BASE+STM32L4_RCC_BDCR_OFFSET) -#define STM32L4_RCC_CSR (STM32L4_RCC_BASE+STM32L4_RCC_CSR_OFFSET) -#define STM32L4_RCC_CRRCR (STM32L4_RCC_BASE+STM32L4_RCC_CRRCR_OFFSET) -#define STM32L4_RCC_CCIPR2 (STM32L4_RCC_BASE+STM32L4_RCC_CCIPR2_OFFSET) +#define STM32_RCC_CR (STM32_RCC_BASE+STM32_RCC_CR_OFFSET) +#define STM32_RCC_ICSCR (STM32_RCC_BASE+STM32_RCC_ICSCR_OFFSET) +#define STM32_RCC_CFGR (STM32_RCC_BASE+STM32_RCC_CFGR_OFFSET) +#define STM32_RCC_PLLCFG (STM32_RCC_BASE+STM32_RCC_PLLCFG_OFFSET) +#define STM32_RCC_PLLSAI1CFG (STM32_RCC_BASE+STM32_RCC_PLLSAI1CFG_OFFSET) +#define STM32_RCC_PLLSAI2CFG (STM32_RCC_BASE+STM32_RCC_PLLSAI2CFG_OFFSET) +#define STM32_RCC_CIER (STM32_RCC_BASE+STM32_RCC_CIER_OFFSET) +#define STM32_RCC_CIFR (STM32_RCC_BASE+STM32_RCC_CIFR_OFFSET) +#define STM32_RCC_CICR (STM32_RCC_BASE+STM32_RCC_CICR_OFFSET) +#define STM32_RCC_AHB1RSTR (STM32_RCC_BASE+STM32_RCC_AHB1RSTR_OFFSET) +#define STM32_RCC_AHB2RSTR (STM32_RCC_BASE+STM32_RCC_AHB2RSTR_OFFSET) +#define STM32_RCC_AHB3RSTR (STM32_RCC_BASE+STM32_RCC_AHB3RSTR_OFFSET) +#define STM32_RCC_APB1RSTR1 (STM32_RCC_BASE+STM32_RCC_APB1RSTR1_OFFSET) +#define STM32_RCC_APB1RSTR2 (STM32_RCC_BASE+STM32_RCC_APB1RSTR2_OFFSET) +#define STM32_RCC_APB2RSTR (STM32_RCC_BASE+STM32_RCC_APB2RSTR_OFFSET) +#define STM32_RCC_AHB1ENR (STM32_RCC_BASE+STM32_RCC_AHB1ENR_OFFSET) +#define STM32_RCC_AHB2ENR (STM32_RCC_BASE+STM32_RCC_AHB2ENR_OFFSET) +#define STM32_RCC_AHB3ENR (STM32_RCC_BASE+STM32_RCC_AHB3ENR_OFFSET) +#define STM32_RCC_APB1ENR1 (STM32_RCC_BASE+STM32_RCC_APB1ENR1_OFFSET) +#define STM32_RCC_APB1ENR2 (STM32_RCC_BASE+STM32_RCC_APB1ENR2_OFFSET) +#define STM32_RCC_APB2ENR (STM32_RCC_BASE+STM32_RCC_APB2ENR_OFFSET) +#define STM32_RCC_AHB1SMENR (STM32_RCC_BASE+STM32_RCC_AHB1SMENR_OFFSET) +#define STM32_RCC_AHB2SMENR (STM32_RCC_BASE+STM32_RCC_AHB2SMENR_OFFSET) +#define STM32_RCC_AHB3SMENR (STM32_RCC_BASE+STM32_RCC_AHB3SMENR_OFFSET) +#define STM32_RCC_APB1SMENR1 (STM32_RCC_BASE+STM32_RCC_APB1SMENR1_OFFSET) +#define STM32_RCC_APB1SMENR2 (STM32_RCC_BASE+STM32_RCC_APB1SMENR2_OFFSET) +#define STM32_RCC_APB2SMENR (STM32_RCC_BASE+STM32_RCC_APB2SMENR_OFFSET) +#define STM32_RCC_CCIPR (STM32_RCC_BASE+STM32_RCC_CCIPR_OFFSET) +#define STM32_RCC_BDCR (STM32_RCC_BASE+STM32_RCC_BDCR_OFFSET) +#define STM32_RCC_CSR (STM32_RCC_BASE+STM32_RCC_CSR_OFFSET) +#define STM32_RCC_CRRCR (STM32_RCC_BASE+STM32_RCC_CRRCR_OFFSET) +#define STM32_RCC_CCIPR2 (STM32_RCC_BASE+STM32_RCC_CCIPR2_OFFSET) /* Register Bitfield Definitions ********************************************/ @@ -712,7 +712,7 @@ #define RCC_CCIPR_CLK48SEL_SHIFT (26) #define RCC_CCIPR_CLK48SEL_MASK (3 << RCC_CCIPR_CLK48SEL_SHIFT) -#if defined(CONFIG_STM32L4_STM32L496XX) +#if defined(CONFIG_STM32_STM32L496XX) # define RCC_CCIPR_CLK48SEL_HSI48 (0 << RCC_CCIPR_CLK48SEL_SHIFT) #else # define RCC_CCIPR_CLK48SEL_NONE (0 << RCC_CCIPR_CLK48SEL_SHIFT) @@ -807,5 +807,5 @@ # define RCC_CCIPR2_I2C4SEL_SYSCLK (1 << RCC_CCIPR2_I2C4SEL_SHIFT) # define RCC_CCIPR2_I2C4SEL_HSI (2 << RCC_CCIPR2_I2C4SEL_SHIFT) -#endif /* CONFIG_STM32L4_STM32L4X6 */ +#endif /* CONFIG_STM32_STM32L4X6 */ #endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4X6XX_RCC_H */ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4x6xx_syscfg.h b/arch/arm/src/stm32l4/hardware/stm32l4x6xx_syscfg.h index 1bf04c71f6e05..bc0ff376cfbaa 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4x6xx_syscfg.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4x6xx_syscfg.h @@ -30,7 +30,7 @@ #include #include "chip.h" -#if defined(CONFIG_STM32L4_STM32L4X6) +#if defined(CONFIG_STM32_STM32L4X6) /**************************************************************************** * Pre-processor Definitions @@ -38,35 +38,35 @@ /* Register Offsets *********************************************************/ -#define STM32L4_SYSCFG_MEMRMP_OFFSET 0x0000 /* SYSCFG memory remap register */ -#define STM32L4_SYSCFG_CFGR1_OFFSET 0x0004 /* SYSCFG configuration register 1 */ +#define STM32_SYSCFG_MEMRMP_OFFSET 0x0000 /* SYSCFG memory remap register */ +#define STM32_SYSCFG_CFGR1_OFFSET 0x0004 /* SYSCFG configuration register 1 */ -#define STM32L4_SYSCFG_EXTICR_OFFSET(p) (0x0008 + ((p) & 0x000c)) /* Registers are displaced by 4! */ +#define STM32_SYSCFG_EXTICR_OFFSET(p) (0x0008 + ((p) & 0x000c)) /* Registers are displaced by 4! */ -#define STM32L4_SYSCFG_EXTICR1_OFFSET 0x0008 /* SYSCFG external interrupt configuration register 1 */ -#define STM32L4_SYSCFG_EXTICR2_OFFSET 0x000c /* SYSCFG external interrupt configuration register 2 */ -#define STM32L4_SYSCFG_EXTICR3_OFFSET 0x0010 /* SYSCFG external interrupt configuration register 3 */ -#define STM32L4_SYSCFG_EXTICR4_OFFSET 0x0014 /* SYSCFG external interrupt configuration register 4 */ -#define STM32L4_SYSCFG_SCSR_OFFSET 0x0018 /* SYSCFG SRAM2 control and status register */ -#define STM32L4_SYSCFG_CFGR2_OFFSET 0x001c /* SYSCFG configuration register 2 */ -#define STM32L4_SYSCFG_SWPR_OFFSET 0x0020 /* SYSCFG SRAM2 write protection register */ -#define STM32L4_SYSCFG_SKR_OFFSET 0x0024 /* SYSCFG SRAM2 key register */ -#define STM32L4_SYSCFG_SWPR2_OFFSET 0x0028 /* SYSCFG SRAM2 write protection register 2 */ +#define STM32_SYSCFG_EXTICR1_OFFSET 0x0008 /* SYSCFG external interrupt configuration register 1 */ +#define STM32_SYSCFG_EXTICR2_OFFSET 0x000c /* SYSCFG external interrupt configuration register 2 */ +#define STM32_SYSCFG_EXTICR3_OFFSET 0x0010 /* SYSCFG external interrupt configuration register 3 */ +#define STM32_SYSCFG_EXTICR4_OFFSET 0x0014 /* SYSCFG external interrupt configuration register 4 */ +#define STM32_SYSCFG_SCSR_OFFSET 0x0018 /* SYSCFG SRAM2 control and status register */ +#define STM32_SYSCFG_CFGR2_OFFSET 0x001c /* SYSCFG configuration register 2 */ +#define STM32_SYSCFG_SWPR_OFFSET 0x0020 /* SYSCFG SRAM2 write protection register */ +#define STM32_SYSCFG_SKR_OFFSET 0x0024 /* SYSCFG SRAM2 key register */ +#define STM32_SYSCFG_SWPR2_OFFSET 0x0028 /* SYSCFG SRAM2 write protection register 2 */ /* Register Addresses *******************************************************/ -#define STM32L4_SYSCFG_MEMRMP (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_MEMRMP_OFFSET) -#define STM32L4_SYSCFG_CFGR1 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_CFGR1_OFFSET) -#define STM32L4_SYSCFG_EXTICR(p) (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_EXTICR_OFFSET(p)) -#define STM32L4_SYSCFG_EXTICR1 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_EXTICR1_OFFSET) -#define STM32L4_SYSCFG_EXTICR2 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_EXTICR2_OFFSET) -#define STM32L4_SYSCFG_EXTICR3 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_EXTICR3_OFFSET) -#define STM32L4_SYSCFG_EXTICR4 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_EXTICR4_OFFSET) -#define STM32L4_SYSCFG_SCSR (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_SCSR_OFFSET) -#define STM32L4_SYSCFG_CFGR2 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_CFGR2_OFFSET) -#define STM32L4_SYSCFG_SWPR (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_SWPR_OFFSET) -#define STM32L4_SYSCFG_SKR (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_SKR_OFFSET) -#define STM32L4_SYSCFG_SWPR2 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_SWPR2_OFFSET) +#define STM32_SYSCFG_MEMRMP (STM32_SYSCFG_BASE+STM32_SYSCFG_MEMRMP_OFFSET) +#define STM32_SYSCFG_CFGR1 (STM32_SYSCFG_BASE+STM32_SYSCFG_CFGR1_OFFSET) +#define STM32_SYSCFG_EXTICR(p) (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR_OFFSET(p)) +#define STM32_SYSCFG_EXTICR1 (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR1_OFFSET) +#define STM32_SYSCFG_EXTICR2 (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR2_OFFSET) +#define STM32_SYSCFG_EXTICR3 (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR3_OFFSET) +#define STM32_SYSCFG_EXTICR4 (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR4_OFFSET) +#define STM32_SYSCFG_SCSR (STM32_SYSCFG_BASE+STM32_SYSCFG_SCSR_OFFSET) +#define STM32_SYSCFG_CFGR2 (STM32_SYSCFG_BASE+STM32_SYSCFG_CFGR2_OFFSET) +#define STM32_SYSCFG_SWPR (STM32_SYSCFG_BASE+STM32_SYSCFG_SWPR_OFFSET) +#define STM32_SYSCFG_SKR (STM32_SYSCFG_BASE+STM32_SYSCFG_SKR_OFFSET) +#define STM32_SYSCFG_SWPR2 (STM32_SYSCFG_BASE+STM32_SYSCFG_SWPR2_OFFSET) /* Register Bitfield Definitions ********************************************/ @@ -179,5 +179,5 @@ /* There is one bit per SRAM2 page (32 to 63) */ -#endif /* CONFIG_STM32L4_STM32L4X6 */ +#endif /* CONFIG_STM32_STM32L4X6 */ #endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4X6XX_SYSCFG_H */ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4xrxx_dma.h b/arch/arm/src/stm32l4/hardware/stm32l4xrxx_dma.h index 8229ac0413c8d..5f32ee5ef75d1 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4xrxx_dma.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4xrxx_dma.h @@ -41,139 +41,139 @@ /* Register Offsets *********************************************************/ -#define STM32L4_DMA_ISR_OFFSET 0x0000 /* DMA interrupt status register */ -#define STM32L4_DMA_IFCR_OFFSET 0x0004 /* DMA interrupt flag clear register */ - -#define STM32L4_DMACHAN_OFFSET(n) (0x0014*(n)) -#define STM32L4_DMACHAN1_OFFSET 0x0000 -#define STM32L4_DMACHAN2_OFFSET 0x0014 -#define STM32L4_DMACHAN3_OFFSET 0x0028 -#define STM32L4_DMACHAN4_OFFSET 0x003c -#define STM32L4_DMACHAN5_OFFSET 0x0050 -#define STM32L4_DMACHAN6_OFFSET 0x0064 -#define STM32L4_DMACHAN7_OFFSET 0x0078 - -#define STM32L4_DMACHAN_CCR_OFFSET 0x0008 /* DMA channel configuration register */ -#define STM32L4_DMACHAN_CNDTR_OFFSET 0x000c /* DMA channel number of data register */ -#define STM32L4_DMACHAN_CPAR_OFFSET 0x0010 /* DMA channel peripheral address register */ -#define STM32L4_DMACHAN_CMAR_OFFSET 0x0014 /* DMA channel memory address register */ - -#define STM32L4_DMA_CCR_OFFSET(n) (STM32L4_DMACHAN_CCR_OFFSET+STM32L4_DMACHAN_OFFSET(n)) -#define STM32L4_DMA_CNDTR_OFFSET(n) (STM32L4_DMACHAN_CNDTR_OFFSET+STM32L4_DMACHAN_OFFSET(n)) -#define STM32L4_DMA_CPAR_OFFSET(n) (STM32L4_DMACHAN_CPAR_OFFSET+STM32L4_DMACHAN_OFFSET(n)) -#define STM32L4_DMA_CMAR_OFFSET(n) (STM32L4_DMACHAN_CMAR_OFFSET+STM32L4_DMACHAN_OFFSET(n)) - -#define STM32L4_DMA_CCR1_OFFSET 0x0008 /* DMA channel 1 configuration register */ -#define STM32L4_DMA_CCR2_OFFSET 0x001c /* DMA channel 2 configuration register */ -#define STM32L4_DMA_CCR3_OFFSET 0x0030 /* DMA channel 3 configuration register */ -#define STM32L4_DMA_CCR4_OFFSET 0x0044 /* DMA channel 4 configuration register */ -#define STM32L4_DMA_CCR5_OFFSET 0x0058 /* DMA channel 5 configuration register */ -#define STM32L4_DMA_CCR6_OFFSET 0x006c /* DMA channel 6 configuration register */ -#define STM32L4_DMA_CCR7_OFFSET 0x0080 /* DMA channel 7 configuration register */ - -#define STM32L4_DMA_CNDTR1_OFFSET 0x000c /* DMA channel 1 number of data register */ -#define STM32L4_DMA_CNDTR2_OFFSET 0x0020 /* DMA channel 2 number of data register */ -#define STM32L4_DMA_CNDTR3_OFFSET 0x0034 /* DMA channel 3 number of data register */ -#define STM32L4_DMA_CNDTR4_OFFSET 0x0048 /* DMA channel 4 number of data register */ -#define STM32L4_DMA_CNDTR5_OFFSET 0x005c /* DMA channel 5 number of data register */ -#define STM32L4_DMA_CNDTR6_OFFSET 0x0070 /* DMA channel 6 number of data register */ -#define STM32L4_DMA_CNDTR7_OFFSET 0x0084 /* DMA channel 7 number of data register */ - -#define STM32L4_DMA_CPAR1_OFFSET 0x0010 /* DMA channel 1 peripheral address register */ -#define STM32L4_DMA_CPAR2_OFFSET 0x0024 /* DMA channel 2 peripheral address register */ -#define STM32L4_DMA_CPAR3_OFFSET 0x0038 /* DMA channel 3 peripheral address register */ -#define STM32L4_DMA_CPAR4_OFFSET 0x004c /* DMA channel 4 peripheral address register */ -#define STM32L4_DMA_CPAR5_OFFSET 0x0060 /* DMA channel 5 peripheral address register */ -#define STM32L4_DMA_CPAR6_OFFSET 0x0074 /* DMA channel 6 peripheral address register */ -#define STM32L4_DMA_CPAR7_OFFSET 0x0088 /* DMA channel 7 peripheral address register */ - -#define STM32L4_DMA_CMAR1_OFFSET 0x0014 /* DMA channel 1 memory address register */ -#define STM32L4_DMA_CMAR2_OFFSET 0x0028 /* DMA channel 2 memory address register */ -#define STM32L4_DMA_CMAR3_OFFSET 0x003c /* DMA channel 3 memory address register */ -#define STM32L4_DMA_CMAR4_OFFSET 0x0050 /* DMA channel 4 memory address register */ -#define STM32L4_DMA_CMAR5_OFFSET 0x0064 /* DMA channel 5 memory address register */ -#define STM32L4_DMA_CMAR6_OFFSET 0x0078 /* DMA channel 6 memory address register */ -#define STM32L4_DMA_CMAR7_OFFSET 0x008c /* DMA channel 7 memory address register */ +#define STM32_DMA_ISR_OFFSET 0x0000 /* DMA interrupt status register */ +#define STM32_DMA_IFCR_OFFSET 0x0004 /* DMA interrupt flag clear register */ + +#define STM32_DMACHAN_OFFSET(n) (0x0014*(n)) +#define STM32_DMACHAN1_OFFSET 0x0000 +#define STM32_DMACHAN2_OFFSET 0x0014 +#define STM32_DMACHAN3_OFFSET 0x0028 +#define STM32_DMACHAN4_OFFSET 0x003c +#define STM32_DMACHAN5_OFFSET 0x0050 +#define STM32_DMACHAN6_OFFSET 0x0064 +#define STM32_DMACHAN7_OFFSET 0x0078 + +#define STM32_DMACHAN_CCR_OFFSET 0x0008 /* DMA channel configuration register */ +#define STM32_DMACHAN_CNDTR_OFFSET 0x000c /* DMA channel number of data register */ +#define STM32_DMACHAN_CPAR_OFFSET 0x0010 /* DMA channel peripheral address register */ +#define STM32_DMACHAN_CMAR_OFFSET 0x0014 /* DMA channel memory address register */ + +#define STM32_DMA_CCR_OFFSET(n) (STM32_DMACHAN_CCR_OFFSET+STM32_DMACHAN_OFFSET(n)) +#define STM32_DMA_CNDTR_OFFSET(n) (STM32_DMACHAN_CNDTR_OFFSET+STM32_DMACHAN_OFFSET(n)) +#define STM32_DMA_CPAR_OFFSET(n) (STM32_DMACHAN_CPAR_OFFSET+STM32_DMACHAN_OFFSET(n)) +#define STM32_DMA_CMAR_OFFSET(n) (STM32_DMACHAN_CMAR_OFFSET+STM32_DMACHAN_OFFSET(n)) + +#define STM32_DMA_CCR1_OFFSET 0x0008 /* DMA channel 1 configuration register */ +#define STM32_DMA_CCR2_OFFSET 0x001c /* DMA channel 2 configuration register */ +#define STM32_DMA_CCR3_OFFSET 0x0030 /* DMA channel 3 configuration register */ +#define STM32_DMA_CCR4_OFFSET 0x0044 /* DMA channel 4 configuration register */ +#define STM32_DMA_CCR5_OFFSET 0x0058 /* DMA channel 5 configuration register */ +#define STM32_DMA_CCR6_OFFSET 0x006c /* DMA channel 6 configuration register */ +#define STM32_DMA_CCR7_OFFSET 0x0080 /* DMA channel 7 configuration register */ + +#define STM32_DMA_CNDTR1_OFFSET 0x000c /* DMA channel 1 number of data register */ +#define STM32_DMA_CNDTR2_OFFSET 0x0020 /* DMA channel 2 number of data register */ +#define STM32_DMA_CNDTR3_OFFSET 0x0034 /* DMA channel 3 number of data register */ +#define STM32_DMA_CNDTR4_OFFSET 0x0048 /* DMA channel 4 number of data register */ +#define STM32_DMA_CNDTR5_OFFSET 0x005c /* DMA channel 5 number of data register */ +#define STM32_DMA_CNDTR6_OFFSET 0x0070 /* DMA channel 6 number of data register */ +#define STM32_DMA_CNDTR7_OFFSET 0x0084 /* DMA channel 7 number of data register */ + +#define STM32_DMA_CPAR1_OFFSET 0x0010 /* DMA channel 1 peripheral address register */ +#define STM32_DMA_CPAR2_OFFSET 0x0024 /* DMA channel 2 peripheral address register */ +#define STM32_DMA_CPAR3_OFFSET 0x0038 /* DMA channel 3 peripheral address register */ +#define STM32_DMA_CPAR4_OFFSET 0x004c /* DMA channel 4 peripheral address register */ +#define STM32_DMA_CPAR5_OFFSET 0x0060 /* DMA channel 5 peripheral address register */ +#define STM32_DMA_CPAR6_OFFSET 0x0074 /* DMA channel 6 peripheral address register */ +#define STM32_DMA_CPAR7_OFFSET 0x0088 /* DMA channel 7 peripheral address register */ + +#define STM32_DMA_CMAR1_OFFSET 0x0014 /* DMA channel 1 memory address register */ +#define STM32_DMA_CMAR2_OFFSET 0x0028 /* DMA channel 2 memory address register */ +#define STM32_DMA_CMAR3_OFFSET 0x003c /* DMA channel 3 memory address register */ +#define STM32_DMA_CMAR4_OFFSET 0x0050 /* DMA channel 4 memory address register */ +#define STM32_DMA_CMAR5_OFFSET 0x0064 /* DMA channel 5 memory address register */ +#define STM32_DMA_CMAR6_OFFSET 0x0078 /* DMA channel 6 memory address register */ +#define STM32_DMA_CMAR7_OFFSET 0x008c /* DMA channel 7 memory address register */ /* Register Addresses *******************************************************/ -#define STM32L4_DMA1_ISRC (STM32L4_DMA1_BASE+STM32L4_DMA_ISR_OFFSET) -#define STM32L4_DMA1_IFCR (STM32L4_DMA1_BASE+STM32L4_DMA_IFCR_OFFSET) - -#define STM32L4_DMA1_CCR(n) (STM32L4_DMA1_BASE+STM32L4_DMA_CCR_OFFSET(n)) -#define STM32L4_DMA1_CCR1 (STM32L4_DMA1_BASE+STM32L4_DMA_CCR1_OFFSET) -#define STM32L4_DMA1_CCR2 (STM32L4_DMA1_BASE+STM32L4_DMA_CCR2_OFFSET) -#define STM32L4_DMA1_CCR3 (STM32L4_DMA1_BASE+STM32L4_DMA_CCR3_OFFSET) -#define STM32L4_DMA1_CCR4 (STM32L4_DMA1_BASE+STM32L4_DMA_CCR4_OFFSET) -#define STM32L4_DMA1_CCR5 (STM32L4_DMA1_BASE+STM32L4_DMA_CCR5_OFFSET) -#define STM32L4_DMA1_CCR6 (STM32L4_DMA1_BASE+STM32L4_DMA_CCR6_OFFSET) -#define STM32L4_DMA1_CCR7 (STM32L4_DMA1_BASE+STM32L4_DMA_CCR7_OFFSET) - -#define STM32L4_DMA1_CNDTR(n) (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR_OFFSET(n)) -#define STM32L4_DMA1_CNDTR1 (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR1_OFFSET) -#define STM32L4_DMA1_CNDTR2 (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR2_OFFSET) -#define STM32L4_DMA1_CNDTR3 (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR3_OFFSET) -#define STM32L4_DMA1_CNDTR4 (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR4_OFFSET) -#define STM32L4_DMA1_CNDTR5 (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR5_OFFSET) -#define STM32L4_DMA1_CNDTR6 (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR6_OFFSET) -#define STM32L4_DMA1_CNDTR7 (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR7_OFFSET) - -#define STM32L4_DMA1_CPAR(n) (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR_OFFSET(n)) -#define STM32L4_DMA1_CPAR1 (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR1_OFFSET) -#define STM32L4_DMA1_CPAR2 (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR2_OFFSET) -#define STM32L4_DMA1_CPAR3 (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR3_OFFSET) -#define STM32L4_DMA1_CPAR4 (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR4_OFFSET) -#define STM32L4_DMA1_CPAR5 (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR5_OFFSET) -#define STM32L4_DMA1_CPAR6 (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR6_OFFSET) -#define STM32L4_DMA1_CPAR7 (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR7_OFFSET) - -#define STM32L4_DMA1_CMAR(n) (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR_OFFSET(n)) -#define STM32L4_DMA1_CMAR1 (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR1_OFFSET) -#define STM32L4_DMA1_CMAR2 (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR2_OFFSET) -#define STM32L4_DMA1_CMAR3 (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR3_OFFSET) -#define STM32L4_DMA1_CMAR4 (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR4_OFFSET) -#define STM32L4_DMA1_CMAR5 (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR5_OFFSET) -#define STM32L4_DMA1_CMAR6 (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR6_OFFSET) -#define STM32L4_DMA1_CMAR7 (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR7_OFFSET) - -#define STM32L4_DMA2_ISRC (STM32L4_DMA2_BASE+STM32L4_DMA_ISR_OFFSET) -#define STM32L4_DMA2_IFCR (STM32L4_DMA2_BASE+STM32L4_DMA_IFCR_OFFSET) - -#define STM32L4_DMA2_CCR(n) (STM32L4_DMA2_BASE+STM32L4_DMA_CCR_OFFSET(n)) -#define STM32L4_DMA2_CCR1 (STM32L4_DMA2_BASE+STM32L4_DMA_CCR1_OFFSET) -#define STM32L4_DMA2_CCR2 (STM32L4_DMA2_BASE+STM32L4_DMA_CCR2_OFFSET) -#define STM32L4_DMA2_CCR3 (STM32L4_DMA2_BASE+STM32L4_DMA_CCR3_OFFSET) -#define STM32L4_DMA2_CCR4 (STM32L4_DMA2_BASE+STM32L4_DMA_CCR4_OFFSET) -#define STM32L4_DMA2_CCR5 (STM32L4_DMA2_BASE+STM32L4_DMA_CCR5_OFFSET) -#define STM32L4_DMA2_CCR6 (STM32L4_DMA2_BASE+STM32L4_DMA_CCR6_OFFSET) -#define STM32L4_DMA2_CCR7 (STM32L4_DMA2_BASE+STM32L4_DMA_CCR7_OFFSET) - -#define STM32L4_DMA2_CNDTR(n) (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR_OFFSET(n)) -#define STM32L4_DMA2_CNDTR1 (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR1_OFFSET) -#define STM32L4_DMA2_CNDTR2 (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR2_OFFSET) -#define STM32L4_DMA2_CNDTR3 (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR3_OFFSET) -#define STM32L4_DMA2_CNDTR4 (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR4_OFFSET) -#define STM32L4_DMA2_CNDTR5 (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR5_OFFSET) -#define STM32L4_DMA2_CNDTR6 (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR6_OFFSET) -#define STM32L4_DMA2_CNDTR7 (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR7_OFFSET) - -#define STM32L4_DMA2_CPAR(n) (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR_OFFSET(n)) -#define STM32L4_DMA2_CPAR1 (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR1_OFFSET) -#define STM32L4_DMA2_CPAR2 (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR2_OFFSET) -#define STM32L4_DMA2_CPAR3 (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR3_OFFSET) -#define STM32L4_DMA2_CPAR4 (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR4_OFFSET) -#define STM32L4_DMA2_CPAR5 (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR5_OFFSET) -#define STM32L4_DMA2_CPAR6 (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR6_OFFSET) -#define STM32L4_DMA2_CPAR7 (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR7_OFFSET) - -#define STM32L4_DMA2_CMAR(n) (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR_OFFSET(n)) -#define STM32L4_DMA2_CMAR1 (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR1_OFFSET) -#define STM32L4_DMA2_CMAR2 (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR2_OFFSET) -#define STM32L4_DMA2_CMAR3 (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR3_OFFSET) -#define STM32L4_DMA2_CMAR4 (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR4_OFFSET) -#define STM32L4_DMA2_CMAR5 (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR5_OFFSET) -#define STM32L4_DMA2_CMAR6 (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR6_OFFSET) -#define STM32L4_DMA2_CMAR7 (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR7_OFFSET) +#define STM32_DMA1_ISRC (STM32_DMA1_BASE+STM32_DMA_ISR_OFFSET) +#define STM32_DMA1_IFCR (STM32_DMA1_BASE+STM32_DMA_IFCR_OFFSET) + +#define STM32_DMA1_CCR(n) (STM32_DMA1_BASE+STM32_DMA_CCR_OFFSET(n)) +#define STM32_DMA1_CCR1 (STM32_DMA1_BASE+STM32_DMA_CCR1_OFFSET) +#define STM32_DMA1_CCR2 (STM32_DMA1_BASE+STM32_DMA_CCR2_OFFSET) +#define STM32_DMA1_CCR3 (STM32_DMA1_BASE+STM32_DMA_CCR3_OFFSET) +#define STM32_DMA1_CCR4 (STM32_DMA1_BASE+STM32_DMA_CCR4_OFFSET) +#define STM32_DMA1_CCR5 (STM32_DMA1_BASE+STM32_DMA_CCR5_OFFSET) +#define STM32_DMA1_CCR6 (STM32_DMA1_BASE+STM32_DMA_CCR6_OFFSET) +#define STM32_DMA1_CCR7 (STM32_DMA1_BASE+STM32_DMA_CCR7_OFFSET) + +#define STM32_DMA1_CNDTR(n) (STM32_DMA1_BASE+STM32_DMA_CNDTR_OFFSET(n)) +#define STM32_DMA1_CNDTR1 (STM32_DMA1_BASE+STM32_DMA_CNDTR1_OFFSET) +#define STM32_DMA1_CNDTR2 (STM32_DMA1_BASE+STM32_DMA_CNDTR2_OFFSET) +#define STM32_DMA1_CNDTR3 (STM32_DMA1_BASE+STM32_DMA_CNDTR3_OFFSET) +#define STM32_DMA1_CNDTR4 (STM32_DMA1_BASE+STM32_DMA_CNDTR4_OFFSET) +#define STM32_DMA1_CNDTR5 (STM32_DMA1_BASE+STM32_DMA_CNDTR5_OFFSET) +#define STM32_DMA1_CNDTR6 (STM32_DMA1_BASE+STM32_DMA_CNDTR6_OFFSET) +#define STM32_DMA1_CNDTR7 (STM32_DMA1_BASE+STM32_DMA_CNDTR7_OFFSET) + +#define STM32_DMA1_CPAR(n) (STM32_DMA1_BASE+STM32_DMA_CPAR_OFFSET(n)) +#define STM32_DMA1_CPAR1 (STM32_DMA1_BASE+STM32_DMA_CPAR1_OFFSET) +#define STM32_DMA1_CPAR2 (STM32_DMA1_BASE+STM32_DMA_CPAR2_OFFSET) +#define STM32_DMA1_CPAR3 (STM32_DMA1_BASE+STM32_DMA_CPAR3_OFFSET) +#define STM32_DMA1_CPAR4 (STM32_DMA1_BASE+STM32_DMA_CPAR4_OFFSET) +#define STM32_DMA1_CPAR5 (STM32_DMA1_BASE+STM32_DMA_CPAR5_OFFSET) +#define STM32_DMA1_CPAR6 (STM32_DMA1_BASE+STM32_DMA_CPAR6_OFFSET) +#define STM32_DMA1_CPAR7 (STM32_DMA1_BASE+STM32_DMA_CPAR7_OFFSET) + +#define STM32_DMA1_CMAR(n) (STM32_DMA1_BASE+STM32_DMA_CMAR_OFFSET(n)) +#define STM32_DMA1_CMAR1 (STM32_DMA1_BASE+STM32_DMA_CMAR1_OFFSET) +#define STM32_DMA1_CMAR2 (STM32_DMA1_BASE+STM32_DMA_CMAR2_OFFSET) +#define STM32_DMA1_CMAR3 (STM32_DMA1_BASE+STM32_DMA_CMAR3_OFFSET) +#define STM32_DMA1_CMAR4 (STM32_DMA1_BASE+STM32_DMA_CMAR4_OFFSET) +#define STM32_DMA1_CMAR5 (STM32_DMA1_BASE+STM32_DMA_CMAR5_OFFSET) +#define STM32_DMA1_CMAR6 (STM32_DMA1_BASE+STM32_DMA_CMAR6_OFFSET) +#define STM32_DMA1_CMAR7 (STM32_DMA1_BASE+STM32_DMA_CMAR7_OFFSET) + +#define STM32_DMA2_ISRC (STM32_DMA2_BASE+STM32_DMA_ISR_OFFSET) +#define STM32_DMA2_IFCR (STM32_DMA2_BASE+STM32_DMA_IFCR_OFFSET) + +#define STM32_DMA2_CCR(n) (STM32_DMA2_BASE+STM32_DMA_CCR_OFFSET(n)) +#define STM32_DMA2_CCR1 (STM32_DMA2_BASE+STM32_DMA_CCR1_OFFSET) +#define STM32_DMA2_CCR2 (STM32_DMA2_BASE+STM32_DMA_CCR2_OFFSET) +#define STM32_DMA2_CCR3 (STM32_DMA2_BASE+STM32_DMA_CCR3_OFFSET) +#define STM32_DMA2_CCR4 (STM32_DMA2_BASE+STM32_DMA_CCR4_OFFSET) +#define STM32_DMA2_CCR5 (STM32_DMA2_BASE+STM32_DMA_CCR5_OFFSET) +#define STM32_DMA2_CCR6 (STM32_DMA2_BASE+STM32_DMA_CCR6_OFFSET) +#define STM32_DMA2_CCR7 (STM32_DMA2_BASE+STM32_DMA_CCR7_OFFSET) + +#define STM32_DMA2_CNDTR(n) (STM32_DMA2_BASE+STM32_DMA_CNDTR_OFFSET(n)) +#define STM32_DMA2_CNDTR1 (STM32_DMA2_BASE+STM32_DMA_CNDTR1_OFFSET) +#define STM32_DMA2_CNDTR2 (STM32_DMA2_BASE+STM32_DMA_CNDTR2_OFFSET) +#define STM32_DMA2_CNDTR3 (STM32_DMA2_BASE+STM32_DMA_CNDTR3_OFFSET) +#define STM32_DMA2_CNDTR4 (STM32_DMA2_BASE+STM32_DMA_CNDTR4_OFFSET) +#define STM32_DMA2_CNDTR5 (STM32_DMA2_BASE+STM32_DMA_CNDTR5_OFFSET) +#define STM32_DMA2_CNDTR6 (STM32_DMA2_BASE+STM32_DMA_CNDTR6_OFFSET) +#define STM32_DMA2_CNDTR7 (STM32_DMA2_BASE+STM32_DMA_CNDTR7_OFFSET) + +#define STM32_DMA2_CPAR(n) (STM32_DMA2_BASE+STM32_DMA_CPAR_OFFSET(n)) +#define STM32_DMA2_CPAR1 (STM32_DMA2_BASE+STM32_DMA_CPAR1_OFFSET) +#define STM32_DMA2_CPAR2 (STM32_DMA2_BASE+STM32_DMA_CPAR2_OFFSET) +#define STM32_DMA2_CPAR3 (STM32_DMA2_BASE+STM32_DMA_CPAR3_OFFSET) +#define STM32_DMA2_CPAR4 (STM32_DMA2_BASE+STM32_DMA_CPAR4_OFFSET) +#define STM32_DMA2_CPAR5 (STM32_DMA2_BASE+STM32_DMA_CPAR5_OFFSET) +#define STM32_DMA2_CPAR6 (STM32_DMA2_BASE+STM32_DMA_CPAR6_OFFSET) +#define STM32_DMA2_CPAR7 (STM32_DMA2_BASE+STM32_DMA_CPAR7_OFFSET) + +#define STM32_DMA2_CMAR(n) (STM32_DMA2_BASE+STM32_DMA_CMAR_OFFSET(n)) +#define STM32_DMA2_CMAR1 (STM32_DMA2_BASE+STM32_DMA_CMAR1_OFFSET) +#define STM32_DMA2_CMAR2 (STM32_DMA2_BASE+STM32_DMA_CMAR2_OFFSET) +#define STM32_DMA2_CMAR3 (STM32_DMA2_BASE+STM32_DMA_CMAR3_OFFSET) +#define STM32_DMA2_CMAR4 (STM32_DMA2_BASE+STM32_DMA_CMAR4_OFFSET) +#define STM32_DMA2_CMAR5 (STM32_DMA2_BASE+STM32_DMA_CMAR5_OFFSET) +#define STM32_DMA2_CMAR6 (STM32_DMA2_BASE+STM32_DMA_CMAR6_OFFSET) +#define STM32_DMA2_CMAR7 (STM32_DMA2_BASE+STM32_DMA_CMAR7_OFFSET) /* Register Bitfield Definitions ********************************************/ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4xrxx_dmamux.h b/arch/arm/src/stm32l4/hardware/stm32l4xrxx_dmamux.h index c0572faa6bccd..19a79a36e07e7 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4xrxx_dmamux.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4xrxx_dmamux.h @@ -39,64 +39,65 @@ /* Register Offsets *********************************************************/ -#define STM32L4_DMAMUX_CXCR_OFFSET(x) (0x0000+0x0004*(x)) /* DMAMUX1 request line multiplexer channel x configuration register */ -#define STM32L4_DMAMUX_C0CR_OFFSET STM32L4_DMAMUX_CXCR_OFFSET(0) -#define STM32L4_DMAMUX_C1CR_OFFSET STM32L4_DMAMUX_CXCR_OFFSET(1) -#define STM32L4_DMAMUX_C2CR_OFFSET STM32L4_DMAMUX_CXCR_OFFSET(2) -#define STM32L4_DMAMUX_C3CR_OFFSET STM32L4_DMAMUX_CXCR_OFFSET(3) -#define STM32L4_DMAMUX_C4CR_OFFSET STM32L4_DMAMUX_CXCR_OFFSET(4) -#define STM32L4_DMAMUX_C5CR_OFFSET STM32L4_DMAMUX_CXCR_OFFSET(5) -#define STM32L4_DMAMUX_C6CR_OFFSET STM32L4_DMAMUX_CXCR_OFFSET(6) -#define STM32L4_DMAMUX_C7CR_OFFSET STM32L4_DMAMUX_CXCR_OFFSET(7) -#define STM32L4_DMAMUX_C8CR_OFFSET STM32L4_DMAMUX_CXCR_OFFSET(8) -#define STM32L4_DMAMUX_C9CR_OFFSET STM32L4_DMAMUX_CXCR_OFFSET(9) -#define STM32L4_DMAMUX_C10CR_OFFSET STM32L4_DMAMUX_CXCR_OFFSET(10) -#define STM32L4_DMAMUX_C11CR_OFFSET STM32L4_DMAMUX_CXCR_OFFSET(11) -#define STM32L4_DMAMUX_C12CR_OFFSET STM32L4_DMAMUX_CXCR_OFFSET(12) -#define STM32L4_DMAMUX_C13CR_OFFSET STM32L4_DMAMUX_CXCR_OFFSET(13) - /* 0x034-0x07C: Reserved */ -#define STM32L4_DMAMUX_CSR_OFFSET 0x0080 /* DMAMUX1 request line multiplexer interrupt channel status register */ -#define STM32L4_DMAMUX_CFR_OFFSET 0x0084 /* DMAMUX1 request line multiplexer interrupt clear flag register */ - /* 0x088-0x0FC: Reserved */ - -#define STM32L4_DMAMUX_RGXCR_OFFSET(x) (0x0100+0x004*(x)) /* DMAMUX1 request generator channel x configuration register */ -#define STM32L4_DMAMUX_RG0CR_OFFSET STM32L4_DMAMUX_RGXCR_OFFSET(0) -#define STM32L4_DMAMUX_RG1CR_OFFSET STM32L4_DMAMUX_RGXCR_OFFSET(1) -#define STM32L4_DMAMUX_RG2CR_OFFSET STM32L4_DMAMUX_RGXCR_OFFSET(2) -#define STM32L4_DMAMUX_RG3CR_OFFSET STM32L4_DMAMUX_RGXCR_OFFSET(3) -#define STM32L4_DMAMUX_RGSR_OFFSET 0x0140 /* DMAMUX1 request generator interrupt status register */ -#define STM32L4_DMAMUX_RGCFR_OFFSET 0x0144 /* DMAMUX1 request generator interrupt clear flag register */ - /* 0x148-0x3FC: Reserved */ +#define STM32_DMAMUX_CXCR_OFFSET(x) (0x0000+0x0004*(x)) /* DMAMUX1 request line multiplexer channel x configuration register */ +#define STM32_DMAMUX_C0CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(0) +#define STM32_DMAMUX_C1CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(1) +#define STM32_DMAMUX_C2CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(2) +#define STM32_DMAMUX_C3CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(3) +#define STM32_DMAMUX_C4CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(4) +#define STM32_DMAMUX_C5CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(5) +#define STM32_DMAMUX_C6CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(6) +#define STM32_DMAMUX_C7CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(7) +#define STM32_DMAMUX_C8CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(8) +#define STM32_DMAMUX_C9CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(9) +#define STM32_DMAMUX_C10CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(10) +#define STM32_DMAMUX_C11CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(11) +#define STM32_DMAMUX_C12CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(12) +#define STM32_DMAMUX_C13CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(13) +/* 0x034-0x07C: Reserved */ + +#define STM32_DMAMUX_CSR_OFFSET 0x0080 /* DMAMUX1 request line multiplexer interrupt channel status register */ +#define STM32_DMAMUX_CFR_OFFSET 0x0084 /* DMAMUX1 request line multiplexer interrupt clear flag register */ + /* 0x088-0x0FC: Reserved */ + +#define STM32_DMAMUX_RGXCR_OFFSET(x) (0x0100+0x004*(x)) /* DMAMUX1 request generator channel x configuration register */ +#define STM32_DMAMUX_RG0CR_OFFSET STM32_DMAMUX_RGXCR_OFFSET(0) +#define STM32_DMAMUX_RG1CR_OFFSET STM32_DMAMUX_RGXCR_OFFSET(1) +#define STM32_DMAMUX_RG2CR_OFFSET STM32_DMAMUX_RGXCR_OFFSET(2) +#define STM32_DMAMUX_RG3CR_OFFSET STM32_DMAMUX_RGXCR_OFFSET(3) +#define STM32_DMAMUX_RGSR_OFFSET 0x0140 /* DMAMUX1 request generator interrupt status register */ +#define STM32_DMAMUX_RGCFR_OFFSET 0x0144 /* DMAMUX1 request generator interrupt clear flag register */ + /* 0x148-0x3FC: Reserved */ /* Register Addresses *******************************************************/ -#define STM32L4_DMAMUX1_CXCR(x) (STM32L4_DMAMUX1_BASE+STM32L4_DMAMUX_CXCR_OFFSET(x)) -#define STM32L4_DMAMUX1_C0CR (STM32L4_DMAMUX1_BASE+STM32L4_DMAMUX_C0CR_OFFSET) -#define STM32L4_DMAMUX1_C1CR (STM32L4_DMAMUX1_BASE+STM32L4_DMAMUX_C1CR_OFFSET) -#define STM32L4_DMAMUX1_C2CR (STM32L4_DMAMUX1_BASE+STM32L4_DMAMUX_C2CR_OFFSET) -#define STM32L4_DMAMUX1_C3CR (STM32L4_DMAMUX1_BASE+STM32L4_DMAMUX_C3CR_OFFSET) -#define STM32L4_DMAMUX1_C4CR (STM32L4_DMAMUX1_BASE+STM32L4_DMAMUX_C4CR_OFFSET) -#define STM32L4_DMAMUX1_C5CR (STM32L4_DMAMUX1_BASE+STM32L4_DMAMUX_C5CR_OFFSET) -#define STM32L4_DMAMUX1_C6CR (STM32L4_DMAMUX1_BASE+STM32L4_DMAMUX_C6CR_OFFSET) -#define STM32L4_DMAMUX1_C7CR (STM32L4_DMAMUX1_BASE+STM32L4_DMAMUX_C7CR_OFFSET) -#define STM32L4_DMAMUX1_C8CR (STM32L4_DMAMUX1_BASE+STM32L4_DMAMUX_C8CR_OFFSET) -#define STM32L4_DMAMUX1_C9CR (STM32L4_DMAMUX1_BASE+STM32L4_DMAMUX_C9CR_OFFSET) -#define STM32L4_DMAMUX1_C10CR (STM32L4_DMAMUX1_BASE+STM32L4_DMAMUX_C10CR_OFFSET) -#define STM32L4_DMAMUX1_C11CR (STM32L4_DMAMUX1_BASE+STM32L4_DMAMUX_C11CR_OFFSET) -#define STM32L4_DMAMUX1_C12CR (STM32L4_DMAMUX1_BASE+STM32L4_DMAMUX_C12CR_OFFSET) -#define STM32L4_DMAMUX1_C13CR (STM32L4_DMAMUX1_BASE+STM32L4_DMAMUX_C13CR_OFFSET) - -#define STM32L4_DMAMUX1_CSR (STM32L4_DMAMUX1_BASE+STM32L4_DMAMUX_CSR_OFFSET) -#define STM32L4_DMAMUX1_CFR (STM32L4_DMAMUX1_BASE+STM32L4_DMAMUX_CFR_OFFSET) - -#define STM32L4_DMAMUX1_RGXCR(x) (STM32L4_DMAMUX1_BASE+STM32L4_DMAMUX_RGXCR_OFFSET(x)) -#define STM32L4_DMAMUX1_RG0CR (STM32L4_DMAMUX1_BASE+STM32L4_DMAMUX_RG0CR_OFFSET) -#define STM32L4_DMAMUX1_RG1CR (STM32L4_DMAMUX1_BASE+STM32L4_DMAMUX_RG1CR_OFFSET) -#define STM32L4_DMAMUX1_RG2CR (STM32L4_DMAMUX1_BASE+STM32L4_DMAMUX_RG2CR_OFFSET) -#define STM32L4_DMAMUX1_RG3CR (STM32L4_DMAMUX1_BASE+STM32L4_DMAMUX_RG3CR_OFFSET) - -#define STM32L4_DMAMUX1_RGSR (STM32L4_DMAMUX1_BASE+STM32L4_DMAMUX_RGSR_OFFSET) -#define STM32L4_DMAMUX1_RGCFR (STM32L4_DMAMUX1_BASE+STM32L4_DMAMUX_RGCFR_OFFSET) +#define STM32_DMAMUX1_CXCR(x) (STM32_DMAMUX1_BASE+STM32_DMAMUX_CXCR_OFFSET(x)) +#define STM32_DMAMUX1_C0CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_C0CR_OFFSET) +#define STM32_DMAMUX1_C1CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_C1CR_OFFSET) +#define STM32_DMAMUX1_C2CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_C2CR_OFFSET) +#define STM32_DMAMUX1_C3CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_C3CR_OFFSET) +#define STM32_DMAMUX1_C4CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_C4CR_OFFSET) +#define STM32_DMAMUX1_C5CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_C5CR_OFFSET) +#define STM32_DMAMUX1_C6CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_C6CR_OFFSET) +#define STM32_DMAMUX1_C7CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_C7CR_OFFSET) +#define STM32_DMAMUX1_C8CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_C8CR_OFFSET) +#define STM32_DMAMUX1_C9CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_C9CR_OFFSET) +#define STM32_DMAMUX1_C10CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_C10CR_OFFSET) +#define STM32_DMAMUX1_C11CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_C11CR_OFFSET) +#define STM32_DMAMUX1_C12CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_C12CR_OFFSET) +#define STM32_DMAMUX1_C13CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_C13CR_OFFSET) + +#define STM32_DMAMUX1_CSR (STM32_DMAMUX1_BASE+STM32_DMAMUX_CSR_OFFSET) +#define STM32_DMAMUX1_CFR (STM32_DMAMUX1_BASE+STM32_DMAMUX_CFR_OFFSET) + +#define STM32_DMAMUX1_RGXCR(x) (STM32_DMAMUX1_BASE+STM32_DMAMUX_RGXCR_OFFSET(x)) +#define STM32_DMAMUX1_RG0CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_RG0CR_OFFSET) +#define STM32_DMAMUX1_RG1CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_RG1CR_OFFSET) +#define STM32_DMAMUX1_RG2CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_RG2CR_OFFSET) +#define STM32_DMAMUX1_RG3CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_RG3CR_OFFSET) + +#define STM32_DMAMUX1_RGSR (STM32_DMAMUX1_BASE+STM32_DMAMUX_RGSR_OFFSET) +#define STM32_DMAMUX1_RGCFR (STM32_DMAMUX1_BASE+STM32_DMAMUX_RGCFR_OFFSET) /* Register Bitfield Definitions ********************************************/ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4xrxx_firewall.h b/arch/arm/src/stm32l4/hardware/stm32l4xrxx_firewall.h index 9c2f082d507b5..d6b0830307809 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4xrxx_firewall.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4xrxx_firewall.h @@ -38,23 +38,23 @@ /* Register Offsets *********************************************************/ -#define STM32L4_FIREWALL_CSSA_OFFSET 0x0000 -#define STM32L4_FIREWALL_CSL_OFFSET 0x0004 -#define STM32L4_FIREWALL_NVDSSA_OFFSET 0x0008 -#define STM32L4_FIREWALL_NVDSL_OFFSET 0x000c -#define STM32L4_FIREWALL_VDSSA_OFFSET 0x0010 -#define STM32L4_FIREWALL_VDSL_OFFSET 0x0014 -#define STM32L4_FIREWALL_CR_OFFSET 0x0020 +#define STM32_FIREWALL_CSSA_OFFSET 0x0000 +#define STM32_FIREWALL_CSL_OFFSET 0x0004 +#define STM32_FIREWALL_NVDSSA_OFFSET 0x0008 +#define STM32_FIREWALL_NVDSL_OFFSET 0x000c +#define STM32_FIREWALL_VDSSA_OFFSET 0x0010 +#define STM32_FIREWALL_VDSL_OFFSET 0x0014 +#define STM32_FIREWALL_CR_OFFSET 0x0020 /* Register Addresses *******************************************************/ -#define STM32L4_FIREWALL_CSSA (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_CSSA_OFFSET) -#define STM32L4_FIREWALL_CSL (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_CSL_OFFSET) -#define STM32L4_FIREWALL_NVDSSA (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_NVDSSA_OFFSET) -#define STM32L4_FIREWALL_NVDSL (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_NVDSL_OFFSET) -#define STM32L4_FIREWALL_VDSSA (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_VDSSA_OFFSET) -#define STM32L4_FIREWALL_VDSL (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_VDSL_OFFSET) -#define STM32L4_FIREWALL_CR (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_CR_OFFSET) +#define STM32_FIREWALL_CSSA (STM32_FIREWALL_BASE+STM32_FIREWALL_CSSA_OFFSET) +#define STM32_FIREWALL_CSL (STM32_FIREWALL_BASE+STM32_FIREWALL_CSL_OFFSET) +#define STM32_FIREWALL_NVDSSA (STM32_FIREWALL_BASE+STM32_FIREWALL_NVDSSA_OFFSET) +#define STM32_FIREWALL_NVDSL (STM32_FIREWALL_BASE+STM32_FIREWALL_NVDSL_OFFSET) +#define STM32_FIREWALL_VDSSA (STM32_FIREWALL_BASE+STM32_FIREWALL_VDSSA_OFFSET) +#define STM32_FIREWALL_VDSL (STM32_FIREWALL_BASE+STM32_FIREWALL_VDSL_OFFSET) +#define STM32_FIREWALL_CR (STM32_FIREWALL_BASE+STM32_FIREWALL_CR_OFFSET) /* Register Bitfield Definitions ********************************************/ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4xrxx_rcc.h b/arch/arm/src/stm32l4/hardware/stm32l4xrxx_rcc.h index c2bc0db32bc09..467ee101d5a83 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4xrxx_rcc.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4xrxx_rcc.h @@ -29,7 +29,7 @@ #include -#if defined(CONFIG_STM32L4_STM32L4XR) +#if defined(CONFIG_STM32_STM32L4XR) /**************************************************************************** * Pre-processor Definitions @@ -37,73 +37,73 @@ /* Register Offsets *********************************************************/ -#define STM32L4_RCC_CR_OFFSET 0x0000 /* Clock control register */ -#define STM32L4_RCC_ICSCR_OFFSET 0x0004 /* Internal clock sources calibration register */ -#define STM32L4_RCC_CFGR_OFFSET 0x0008 /* Clock configuration register */ -#define STM32L4_RCC_PLLCFG_OFFSET 0x000c /* PLL configuration register */ -#define STM32L4_RCC_PLLSAI1CFG_OFFSET 0x0010 /* PLLSAI1 configuration register */ -#define STM32L4_RCC_PLLSAI2CFG_OFFSET 0x0014 /* PLLSAI2 configuration register */ -#define STM32L4_RCC_CIER_OFFSET 0x0018 /* Clock interrupt enable register */ -#define STM32L4_RCC_CIFR_OFFSET 0x001c /* Clock interrupt flag register */ -#define STM32L4_RCC_CICR_OFFSET 0x0020 /* Clock interrupt clear register */ -#define STM32L4_RCC_AHB1RSTR_OFFSET 0x0028 /* AHB1 peripheral reset register */ -#define STM32L4_RCC_AHB2RSTR_OFFSET 0x002c /* AHB2 peripheral reset register */ -#define STM32L4_RCC_AHB3RSTR_OFFSET 0x0030 /* AHB3 peripheral reset register */ -#define STM32L4_RCC_APB1RSTR1_OFFSET 0x0038 /* APB1 Peripheral reset register 1 */ -#define STM32L4_RCC_APB1RSTR2_OFFSET 0x003c /* APB1 Peripheral reset register 2 */ -#define STM32L4_RCC_APB2RSTR_OFFSET 0x0040 /* APB2 Peripheral reset register */ -#define STM32L4_RCC_AHB1ENR_OFFSET 0x0048 /* AHB1 Peripheral Clock enable register */ -#define STM32L4_RCC_AHB2ENR_OFFSET 0x004c /* AHB2 Peripheral Clock enable register */ -#define STM32L4_RCC_AHB3ENR_OFFSET 0x0050 /* AHB3 Peripheral Clock enable register */ -#define STM32L4_RCC_APB1ENR1_OFFSET 0x0058 /* APB1 Peripheral Clock enable register 1 */ -#define STM32L4_RCC_APB1ENR2_OFFSET 0x005c /* APB1 Peripheral Clock enable register 2 */ -#define STM32L4_RCC_APB2ENR_OFFSET 0x0060 /* APB2 Peripheral Clock enable register */ -#define STM32L4_RCC_AHB1SMENR_OFFSET 0x0068 /* RCC AHB1 low power mode peripheral clock enable register */ -#define STM32L4_RCC_AHB2SMENR_OFFSET 0x006c /* RCC AHB2 low power mode peripheral clock enable register */ -#define STM32L4_RCC_AHB3SMENR_OFFSET 0x0070 /* RCC AHB3 low power mode peripheral clock enable register */ -#define STM32L4_RCC_APB1SMENR1_OFFSET 0x0078 /* RCC APB1 low power mode peripheral clock enable register 1 */ -#define STM32L4_RCC_APB1SMENR2_OFFSET 0x007c /* RCC APB1 low power mode peripheral clock enable register 2 */ -#define STM32L4_RCC_APB2SMENR_OFFSET 0x0080 /* RCC APB2 low power mode peripheral clock enable register */ -#define STM32L4_RCC_CCIPR_OFFSET 0x0088 /* Peripherals independent clock configuration register 1 */ -#define STM32L4_RCC_BDCR_OFFSET 0x0090 /* Backup domain control register */ -#define STM32L4_RCC_CSR_OFFSET 0x0094 /* Control/status register */ -#define STM32L4_RCC_CRRCR_OFFSET 0x0098 /* Clock recovery RC register */ -#define STM32L4_RCC_CCIPR2_OFFSET 0x009c /* Peripherals independent clock configuration register 2 */ +#define STM32_RCC_CR_OFFSET 0x0000 /* Clock control register */ +#define STM32_RCC_ICSCR_OFFSET 0x0004 /* Internal clock sources calibration register */ +#define STM32_RCC_CFGR_OFFSET 0x0008 /* Clock configuration register */ +#define STM32_RCC_PLLCFG_OFFSET 0x000c /* PLL configuration register */ +#define STM32_RCC_PLLSAI1CFG_OFFSET 0x0010 /* PLLSAI1 configuration register */ +#define STM32_RCC_PLLSAI2CFG_OFFSET 0x0014 /* PLLSAI2 configuration register */ +#define STM32_RCC_CIER_OFFSET 0x0018 /* Clock interrupt enable register */ +#define STM32_RCC_CIFR_OFFSET 0x001c /* Clock interrupt flag register */ +#define STM32_RCC_CICR_OFFSET 0x0020 /* Clock interrupt clear register */ +#define STM32_RCC_AHB1RSTR_OFFSET 0x0028 /* AHB1 peripheral reset register */ +#define STM32_RCC_AHB2RSTR_OFFSET 0x002c /* AHB2 peripheral reset register */ +#define STM32_RCC_AHB3RSTR_OFFSET 0x0030 /* AHB3 peripheral reset register */ +#define STM32_RCC_APB1RSTR1_OFFSET 0x0038 /* APB1 Peripheral reset register 1 */ +#define STM32_RCC_APB1RSTR2_OFFSET 0x003c /* APB1 Peripheral reset register 2 */ +#define STM32_RCC_APB2RSTR_OFFSET 0x0040 /* APB2 Peripheral reset register */ +#define STM32_RCC_AHB1ENR_OFFSET 0x0048 /* AHB1 Peripheral Clock enable register */ +#define STM32_RCC_AHB2ENR_OFFSET 0x004c /* AHB2 Peripheral Clock enable register */ +#define STM32_RCC_AHB3ENR_OFFSET 0x0050 /* AHB3 Peripheral Clock enable register */ +#define STM32_RCC_APB1ENR1_OFFSET 0x0058 /* APB1 Peripheral Clock enable register 1 */ +#define STM32_RCC_APB1ENR2_OFFSET 0x005c /* APB1 Peripheral Clock enable register 2 */ +#define STM32_RCC_APB2ENR_OFFSET 0x0060 /* APB2 Peripheral Clock enable register */ +#define STM32_RCC_AHB1SMENR_OFFSET 0x0068 /* RCC AHB1 low power mode peripheral clock enable register */ +#define STM32_RCC_AHB2SMENR_OFFSET 0x006c /* RCC AHB2 low power mode peripheral clock enable register */ +#define STM32_RCC_AHB3SMENR_OFFSET 0x0070 /* RCC AHB3 low power mode peripheral clock enable register */ +#define STM32_RCC_APB1SMENR1_OFFSET 0x0078 /* RCC APB1 low power mode peripheral clock enable register 1 */ +#define STM32_RCC_APB1SMENR2_OFFSET 0x007c /* RCC APB1 low power mode peripheral clock enable register 2 */ +#define STM32_RCC_APB2SMENR_OFFSET 0x0080 /* RCC APB2 low power mode peripheral clock enable register */ +#define STM32_RCC_CCIPR_OFFSET 0x0088 /* Peripherals independent clock configuration register 1 */ +#define STM32_RCC_BDCR_OFFSET 0x0090 /* Backup domain control register */ +#define STM32_RCC_CSR_OFFSET 0x0094 /* Control/status register */ +#define STM32_RCC_CRRCR_OFFSET 0x0098 /* Clock recovery RC register */ +#define STM32_RCC_CCIPR2_OFFSET 0x009c /* Peripherals independent clock configuration register 2 */ /* Register Addresses *******************************************************/ -#define STM32L4_RCC_CR (STM32L4_RCC_BASE+STM32L4_RCC_CR_OFFSET) -#define STM32L4_RCC_ICSCR (STM32L4_RCC_BASE+STM32L4_RCC_ICSCR_OFFSET) -#define STM32L4_RCC_CFGR (STM32L4_RCC_BASE+STM32L4_RCC_CFGR_OFFSET) -#define STM32L4_RCC_PLLCFG (STM32L4_RCC_BASE+STM32L4_RCC_PLLCFG_OFFSET) -#define STM32L4_RCC_PLLSAI1CFG (STM32L4_RCC_BASE+STM32L4_RCC_PLLSAI1CFG_OFFSET) -#define STM32L4_RCC_PLLSAI2CFG (STM32L4_RCC_BASE+STM32L4_RCC_PLLSAI2CFG_OFFSET) -#define STM32L4_RCC_CIER (STM32L4_RCC_BASE+STM32L4_RCC_CIER_OFFSET) -#define STM32L4_RCC_CIFR (STM32L4_RCC_BASE+STM32L4_RCC_CIFR_OFFSET) -#define STM32L4_RCC_CICR (STM32L4_RCC_BASE+STM32L4_RCC_CICR_OFFSET) -#define STM32L4_RCC_AHB1RSTR (STM32L4_RCC_BASE+STM32L4_RCC_AHB1RSTR_OFFSET) -#define STM32L4_RCC_AHB2RSTR (STM32L4_RCC_BASE+STM32L4_RCC_AHB2RSTR_OFFSET) -#define STM32L4_RCC_AHB3RSTR (STM32L4_RCC_BASE+STM32L4_RCC_AHB3RSTR_OFFSET) -#define STM32L4_RCC_APB1RSTR1 (STM32L4_RCC_BASE+STM32L4_RCC_APB1RSTR1_OFFSET) -#define STM32L4_RCC_APB1RSTR2 (STM32L4_RCC_BASE+STM32L4_RCC_APB1RSTR2_OFFSET) -#define STM32L4_RCC_APB2RSTR (STM32L4_RCC_BASE+STM32L4_RCC_APB2RSTR_OFFSET) -#define STM32L4_RCC_AHB1ENR (STM32L4_RCC_BASE+STM32L4_RCC_AHB1ENR_OFFSET) -#define STM32L4_RCC_AHB2ENR (STM32L4_RCC_BASE+STM32L4_RCC_AHB2ENR_OFFSET) -#define STM32L4_RCC_AHB3ENR (STM32L4_RCC_BASE+STM32L4_RCC_AHB3ENR_OFFSET) -#define STM32L4_RCC_APB1ENR1 (STM32L4_RCC_BASE+STM32L4_RCC_APB1ENR1_OFFSET) -#define STM32L4_RCC_APB1ENR2 (STM32L4_RCC_BASE+STM32L4_RCC_APB1ENR2_OFFSET) -#define STM32L4_RCC_APB2ENR (STM32L4_RCC_BASE+STM32L4_RCC_APB2ENR_OFFSET) -#define STM32L4_RCC_AHB1SMENR (STM32L4_RCC_BASE+STM32L4_RCC_AHB1SMENR_OFFSET) -#define STM32L4_RCC_AHB2SMENR (STM32L4_RCC_BASE+STM32L4_RCC_AHB2SMENR_OFFSET) -#define STM32L4_RCC_AHB3SMENR (STM32L4_RCC_BASE+STM32L4_RCC_AHB3SMENR_OFFSET) -#define STM32L4_RCC_APB1SMENR1 (STM32L4_RCC_BASE+STM32L4_RCC_APB1SMENR1_OFFSET) -#define STM32L4_RCC_APB1SMENR2 (STM32L4_RCC_BASE+STM32L4_RCC_APB1SMENR2_OFFSET) -#define STM32L4_RCC_APB2SMENR (STM32L4_RCC_BASE+STM32L4_RCC_APB2SMENR_OFFSET) -#define STM32L4_RCC_CCIPR (STM32L4_RCC_BASE+STM32L4_RCC_CCIPR_OFFSET) -#define STM32L4_RCC_BDCR (STM32L4_RCC_BASE+STM32L4_RCC_BDCR_OFFSET) -#define STM32L4_RCC_CSR (STM32L4_RCC_BASE+STM32L4_RCC_CSR_OFFSET) -#define STM32L4_RCC_CRRCR (STM32L4_RCC_BASE+STM32L4_RCC_CRRCR_OFFSET) -#define STM32L4_RCC_CCIPR2 (STM32L4_RCC_BASE+STM32L4_RCC_CCIPR2_OFFSET) +#define STM32_RCC_CR (STM32_RCC_BASE+STM32_RCC_CR_OFFSET) +#define STM32_RCC_ICSCR (STM32_RCC_BASE+STM32_RCC_ICSCR_OFFSET) +#define STM32_RCC_CFGR (STM32_RCC_BASE+STM32_RCC_CFGR_OFFSET) +#define STM32_RCC_PLLCFG (STM32_RCC_BASE+STM32_RCC_PLLCFG_OFFSET) +#define STM32_RCC_PLLSAI1CFG (STM32_RCC_BASE+STM32_RCC_PLLSAI1CFG_OFFSET) +#define STM32_RCC_PLLSAI2CFG (STM32_RCC_BASE+STM32_RCC_PLLSAI2CFG_OFFSET) +#define STM32_RCC_CIER (STM32_RCC_BASE+STM32_RCC_CIER_OFFSET) +#define STM32_RCC_CIFR (STM32_RCC_BASE+STM32_RCC_CIFR_OFFSET) +#define STM32_RCC_CICR (STM32_RCC_BASE+STM32_RCC_CICR_OFFSET) +#define STM32_RCC_AHB1RSTR (STM32_RCC_BASE+STM32_RCC_AHB1RSTR_OFFSET) +#define STM32_RCC_AHB2RSTR (STM32_RCC_BASE+STM32_RCC_AHB2RSTR_OFFSET) +#define STM32_RCC_AHB3RSTR (STM32_RCC_BASE+STM32_RCC_AHB3RSTR_OFFSET) +#define STM32_RCC_APB1RSTR1 (STM32_RCC_BASE+STM32_RCC_APB1RSTR1_OFFSET) +#define STM32_RCC_APB1RSTR2 (STM32_RCC_BASE+STM32_RCC_APB1RSTR2_OFFSET) +#define STM32_RCC_APB2RSTR (STM32_RCC_BASE+STM32_RCC_APB2RSTR_OFFSET) +#define STM32_RCC_AHB1ENR (STM32_RCC_BASE+STM32_RCC_AHB1ENR_OFFSET) +#define STM32_RCC_AHB2ENR (STM32_RCC_BASE+STM32_RCC_AHB2ENR_OFFSET) +#define STM32_RCC_AHB3ENR (STM32_RCC_BASE+STM32_RCC_AHB3ENR_OFFSET) +#define STM32_RCC_APB1ENR1 (STM32_RCC_BASE+STM32_RCC_APB1ENR1_OFFSET) +#define STM32_RCC_APB1ENR2 (STM32_RCC_BASE+STM32_RCC_APB1ENR2_OFFSET) +#define STM32_RCC_APB2ENR (STM32_RCC_BASE+STM32_RCC_APB2ENR_OFFSET) +#define STM32_RCC_AHB1SMENR (STM32_RCC_BASE+STM32_RCC_AHB1SMENR_OFFSET) +#define STM32_RCC_AHB2SMENR (STM32_RCC_BASE+STM32_RCC_AHB2SMENR_OFFSET) +#define STM32_RCC_AHB3SMENR (STM32_RCC_BASE+STM32_RCC_AHB3SMENR_OFFSET) +#define STM32_RCC_APB1SMENR1 (STM32_RCC_BASE+STM32_RCC_APB1SMENR1_OFFSET) +#define STM32_RCC_APB1SMENR2 (STM32_RCC_BASE+STM32_RCC_APB1SMENR2_OFFSET) +#define STM32_RCC_APB2SMENR (STM32_RCC_BASE+STM32_RCC_APB2SMENR_OFFSET) +#define STM32_RCC_CCIPR (STM32_RCC_BASE+STM32_RCC_CCIPR_OFFSET) +#define STM32_RCC_BDCR (STM32_RCC_BASE+STM32_RCC_BDCR_OFFSET) +#define STM32_RCC_CSR (STM32_RCC_BASE+STM32_RCC_CSR_OFFSET) +#define STM32_RCC_CRRCR (STM32_RCC_BASE+STM32_RCC_CRRCR_OFFSET) +#define STM32_RCC_CCIPR2 (STM32_RCC_BASE+STM32_RCC_CCIPR2_OFFSET) /* Register Bitfield Definitions ********************************************/ @@ -860,5 +860,5 @@ # define RCC_CCIPR2_SAI2SEL_SAI2_EXT (3 << RCC_CCIPR2_SAI2SEL_SHIFT) # define RCC_CCIPR2_SAI2SEL_HSI (4 << RCC_CCIPR2_SAI2SEL_SHIFT) -#endif /* CONFIG_STM32L4_STM32L4XR */ +#endif /* CONFIG_STM32_STM32L4XR */ #endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4XRXX_RCC_H */ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4xrxx_syscfg.h b/arch/arm/src/stm32l4/hardware/stm32l4xrxx_syscfg.h index d95a8e753639d..b24b23bc0fcf4 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4xrxx_syscfg.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4xrxx_syscfg.h @@ -30,7 +30,7 @@ #include #include "chip.h" -#if defined(CONFIG_STM32L4_STM32L4XR) +#if defined(CONFIG_STM32_STM32L4XR) /**************************************************************************** * Pre-processor Definitions @@ -38,35 +38,35 @@ /* Register Offsets *********************************************************/ -#define STM32L4_SYSCFG_MEMRMP_OFFSET 0x0000 /* SYSCFG memory remap register */ -#define STM32L4_SYSCFG_CFGR1_OFFSET 0x0004 /* SYSCFG configuration register 1 */ +#define STM32_SYSCFG_MEMRMP_OFFSET 0x0000 /* SYSCFG memory remap register */ +#define STM32_SYSCFG_CFGR1_OFFSET 0x0004 /* SYSCFG configuration register 1 */ -#define STM32L4_SYSCFG_EXTICR_OFFSET(p) (0x0008 + ((p) & 0x000c)) /* Registers are displaced by 4! */ +#define STM32_SYSCFG_EXTICR_OFFSET(p) (0x0008 + ((p) & 0x000c)) /* Registers are displaced by 4! */ -#define STM32L4_SYSCFG_EXTICR1_OFFSET 0x0008 /* SYSCFG external interrupt configuration register 1 */ -#define STM32L4_SYSCFG_EXTICR2_OFFSET 0x000c /* SYSCFG external interrupt configuration register 2 */ -#define STM32L4_SYSCFG_EXTICR3_OFFSET 0x0010 /* SYSCFG external interrupt configuration register 3 */ -#define STM32L4_SYSCFG_EXTICR4_OFFSET 0x0014 /* SYSCFG external interrupt configuration register 4 */ -#define STM32L4_SYSCFG_SCSR_OFFSET 0x0018 /* SYSCFG SRAM2 control and status register */ -#define STM32L4_SYSCFG_CFGR2_OFFSET 0x001c /* SYSCFG configuration register 2 */ -#define STM32L4_SYSCFG_SWPR_OFFSET 0x0020 /* SYSCFG SRAM2 write protection register */ -#define STM32L4_SYSCFG_SKR_OFFSET 0x0024 /* SYSCFG SRAM2 key register */ -#define STM32L4_SYSCFG_SWPR2_OFFSET 0x0028 /* SYSCFG SRAM2 write protection register 2 */ +#define STM32_SYSCFG_EXTICR1_OFFSET 0x0008 /* SYSCFG external interrupt configuration register 1 */ +#define STM32_SYSCFG_EXTICR2_OFFSET 0x000c /* SYSCFG external interrupt configuration register 2 */ +#define STM32_SYSCFG_EXTICR3_OFFSET 0x0010 /* SYSCFG external interrupt configuration register 3 */ +#define STM32_SYSCFG_EXTICR4_OFFSET 0x0014 /* SYSCFG external interrupt configuration register 4 */ +#define STM32_SYSCFG_SCSR_OFFSET 0x0018 /* SYSCFG SRAM2 control and status register */ +#define STM32_SYSCFG_CFGR2_OFFSET 0x001c /* SYSCFG configuration register 2 */ +#define STM32_SYSCFG_SWPR_OFFSET 0x0020 /* SYSCFG SRAM2 write protection register */ +#define STM32_SYSCFG_SKR_OFFSET 0x0024 /* SYSCFG SRAM2 key register */ +#define STM32_SYSCFG_SWPR2_OFFSET 0x0028 /* SYSCFG SRAM2 write protection register 2 */ /* Register Addresses *******************************************************/ -#define STM32L4_SYSCFG_MEMRMP (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_MEMRMP_OFFSET) -#define STM32L4_SYSCFG_CFGR1 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_CFGR1_OFFSET) -#define STM32L4_SYSCFG_EXTICR(p) (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_EXTICR_OFFSET(p)) -#define STM32L4_SYSCFG_EXTICR1 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_EXTICR1_OFFSET) -#define STM32L4_SYSCFG_EXTICR2 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_EXTICR2_OFFSET) -#define STM32L4_SYSCFG_EXTICR3 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_EXTICR3_OFFSET) -#define STM32L4_SYSCFG_EXTICR4 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_EXTICR4_OFFSET) -#define STM32L4_SYSCFG_SCSR (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_SCSR_OFFSET) -#define STM32L4_SYSCFG_CFGR2 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_CFGR2_OFFSET) -#define STM32L4_SYSCFG_SWPR (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_SWPR_OFFSET) -#define STM32L4_SYSCFG_SKR (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_SKR_OFFSET) -#define STM32L4_SYSCFG_SWPR2 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_SWPR2_OFFSET) +#define STM32_SYSCFG_MEMRMP (STM32_SYSCFG_BASE+STM32_SYSCFG_MEMRMP_OFFSET) +#define STM32_SYSCFG_CFGR1 (STM32_SYSCFG_BASE+STM32_SYSCFG_CFGR1_OFFSET) +#define STM32_SYSCFG_EXTICR(p) (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR_OFFSET(p)) +#define STM32_SYSCFG_EXTICR1 (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR1_OFFSET) +#define STM32_SYSCFG_EXTICR2 (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR2_OFFSET) +#define STM32_SYSCFG_EXTICR3 (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR3_OFFSET) +#define STM32_SYSCFG_EXTICR4 (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR4_OFFSET) +#define STM32_SYSCFG_SCSR (STM32_SYSCFG_BASE+STM32_SYSCFG_SCSR_OFFSET) +#define STM32_SYSCFG_CFGR2 (STM32_SYSCFG_BASE+STM32_SYSCFG_CFGR2_OFFSET) +#define STM32_SYSCFG_SWPR (STM32_SYSCFG_BASE+STM32_SYSCFG_SWPR_OFFSET) +#define STM32_SYSCFG_SKR (STM32_SYSCFG_BASE+STM32_SYSCFG_SKR_OFFSET) +#define STM32_SYSCFG_SWPR2 (STM32_SYSCFG_BASE+STM32_SYSCFG_SWPR2_OFFSET) /* Register Bitfield Definitions ********************************************/ @@ -181,5 +181,5 @@ /* There is one bit per SRAM2 page (32 to 63) */ -#endif /* CONFIG_STM32L4_STM32L4XR */ +#endif /* CONFIG_STM32_STM32L4XR */ #endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4XRXX_SYSCFG_H */ diff --git a/arch/arm/src/stm32l4/stm32.h b/arch/arm/src/stm32l4/stm32.h new file mode 100644 index 0000000000000..b996ad1a7d9ca --- /dev/null +++ b/arch/arm/src/stm32l4/stm32.h @@ -0,0 +1,65 @@ +/**************************************************************************** + * arch/arm/src/stm32l4/stm32.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32L4_STM32_H +#define __ARCH_ARM_SRC_STM32L4_STM32_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include +#include + +#include "arm_internal.h" + +/* Peripherals **************************************************************/ + +#include "chip.h" +#include "stm32l4_adc.h" +#include "stm32l4_can.h" +#include "stm32l4_comp.h" +#include "stm32l4_dac.h" +#include "stm32l4_dbgmcu.h" +#include "stm32l4_dma.h" +#include "stm32l4_exti.h" +#include "stm32l4_flash.h" +#include "stm32l4_gpio.h" +#include "stm32l4_i2c.h" +#include "stm32l4_pwr.h" +#include "stm32l4_rcc.h" +#include "stm32l4_rtc.h" +#include "stm32l4_sdmmc.h" +#include "stm32l4_spi.h" +#include "stm32l4_tim.h" +#include "stm32l4_uart.h" +#include "stm32l4_usbdev.h" +#include "stm32l4_wdg.h" +#include "stm32l4_lowputc.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#endif /* __ARCH_ARM_SRC_STM32L4_STM32_H */ diff --git a/arch/arm/src/stm32l4/stm32l4.h b/arch/arm/src/stm32l4/stm32l4.h deleted file mode 100644 index 8aeee5c68619b..0000000000000 --- a/arch/arm/src/stm32l4/stm32l4.h +++ /dev/null @@ -1,65 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32l4/stm32l4.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32L4_STM32L4_H -#define __ARCH_ARM_SRC_STM32L4_STM32L4_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include -#include -#include - -#include "arm_internal.h" - -/* Peripherals **************************************************************/ - -#include "chip.h" -#include "stm32l4_adc.h" -#include "stm32l4_can.h" -#include "stm32l4_comp.h" -#include "stm32l4_dac.h" -#include "stm32l4_dbgmcu.h" -#include "stm32l4_dma.h" -#include "stm32l4_exti.h" -#include "stm32l4_flash.h" -#include "stm32l4_gpio.h" -#include "stm32l4_i2c.h" -#include "stm32l4_pwr.h" -#include "stm32l4_rcc.h" -#include "stm32l4_rtc.h" -#include "stm32l4_sdmmc.h" -#include "stm32l4_spi.h" -#include "stm32l4_tim.h" -#include "stm32l4_uart.h" -#include "stm32l4_usbdev.h" -#include "stm32l4_wdg.h" -#include "stm32l4_lowputc.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#endif /* __ARCH_ARM_SRC_STM32L4_STM32L4_H */ diff --git a/arch/arm/src/stm32l4/stm32l4_1wire.c b/arch/arm/src/stm32l4/stm32l4_1wire.c index 21f9264bc5289..d22c0e8d5a9e4 100644 --- a/arch/arm/src/stm32l4/stm32l4_1wire.c +++ b/arch/arm/src/stm32l4/stm32l4_1wire.c @@ -172,14 +172,14 @@ static int stm32_1wire_pm_prepare(struct pm_callback_s *cb, int domain, /* 1-Wire device structures */ -#ifdef CONFIG_STM32L4_USART1_1WIREDRIVER +#ifdef CONFIG_STM32_USART1_1WIREDRIVER static const struct stm32_1wire_config_s stm32_1wire1_config = { - .usartbase = STM32L4_USART1_BASE, - .apbclock = STM32L4_PCLK2_FREQUENCY, + .usartbase = STM32_USART1_BASE, + .apbclock = STM32_PCLK2_FREQUENCY, .data_pin = PIN_OPENDRAIN(GPIO_USART1_TX), - .irq = STM32L4_IRQ_USART1, + .irq = STM32_IRQ_USART1, }; static struct stm32_1wire_priv_s stm32_1wire1_priv = @@ -196,14 +196,14 @@ static struct stm32_1wire_priv_s stm32_1wire1_priv = #endif -#ifdef CONFIG_STM32L4_USART2_1WIREDRIVER +#ifdef CONFIG_STM32_USART2_1WIREDRIVER static const struct stm32_1wire_config_s stm32_1wire2_config = { - .usartbase = STM32L4_USART2_BASE, - .apbclock = STM32L4_PCLK1_FREQUENCY, + .usartbase = STM32_USART2_BASE, + .apbclock = STM32_PCLK1_FREQUENCY, .data_pin = PIN_OPENDRAIN(GPIO_USART2_TX), - .irq = STM32L4_IRQ_USART2, + .irq = STM32_IRQ_USART2, }; static struct stm32_1wire_priv_s stm32_1wire2_priv = @@ -220,14 +220,14 @@ static struct stm32_1wire_priv_s stm32_1wire2_priv = #endif -#ifdef CONFIG_STM32L4_USART3_1WIREDRIVER +#ifdef CONFIG_STM32_USART3_1WIREDRIVER static const struct stm32_1wire_config_s stm32_1wire3_config = { - .usartbase = STM32L4_USART3_BASE, - .apbclock = STM32L4_PCLK1_FREQUENCY, + .usartbase = STM32_USART3_BASE, + .apbclock = STM32_PCLK1_FREQUENCY, .data_pin = PIN_OPENDRAIN(GPIO_USART3_TX), - .irq = STM32L4_IRQ_USART3, + .irq = STM32_IRQ_USART3, }; static struct stm32_1wire_priv_s stm32_1wire3_priv = @@ -244,14 +244,14 @@ static struct stm32_1wire_priv_s stm32_1wire3_priv = #endif -#ifdef CONFIG_STM32L4_UART4_1WIREDRIVER +#ifdef CONFIG_STM32_UART4_1WIREDRIVER static const struct stm32_1wire_config_s stm32_1wire4_config = { - .usartbase = STM32L4_UART4_BASE, - .apbclock = STM32L4_PCLK1_FREQUENCY, + .usartbase = STM32_UART4_BASE, + .apbclock = STM32_PCLK1_FREQUENCY, .data_pin = PIN_OPENDRAIN(GPIO_UART4_TX), - .irq = STM32L4_IRQ_UART4, + .irq = STM32_IRQ_UART4, }; static struct stm32_1wire_priv_s stm32_1wire4_priv = @@ -268,14 +268,14 @@ static struct stm32_1wire_priv_s stm32_1wire4_priv = #endif -#ifdef CONFIG_STM32L4_UART5_1WIREDRIVER +#ifdef CONFIG_STM32_UART5_1WIREDRIVER static const struct stm32_1wire_config_s stm32_1wire5_config = { - .usartbase = STM32L4_UART5_BASE, - .apbclock = STM32L4_PCLK1_FREQUENCY, + .usartbase = STM32_UART5_BASE, + .apbclock = STM32_PCLK1_FREQUENCY, .data_pin = PIN_OPENDRAIN(GPIO_UART5_TX), - .irq = STM32L4_IRQ_UART5, + .irq = STM32_IRQ_UART5, }; static struct stm32_1wire_priv_s stm32_1wire5_priv = @@ -338,7 +338,7 @@ static inline void stm32_1wire_out(struct stm32_1wire_priv_s *priv, static int stm32_1wire_recv(struct stm32_1wire_priv_s *priv) { - return stm32_1wire_in(priv, STM32L4_USART_RDR_OFFSET) & 0xff; + return stm32_1wire_in(priv, STM32_USART_RDR_OFFSET) & 0xff; } /**************************************************************************** @@ -351,7 +351,7 @@ static int stm32_1wire_recv(struct stm32_1wire_priv_s *priv) static void stm32_1wire_send(struct stm32_1wire_priv_s *priv, int ch) { - stm32_1wire_out(priv, STM32L4_USART_TDR_OFFSET, (uint32_t)(ch & 0xff)); + stm32_1wire_out(priv, STM32_USART_TDR_OFFSET, (uint32_t)(ch & 0xff)); } /**************************************************************************** @@ -377,13 +377,13 @@ static void stm32_1wire_set_baud(struct stm32_1wire_priv_s *priv) * for baud changing. */ - cr1 = stm32_1wire_in(priv, STM32L4_USART_CR1_OFFSET); + cr1 = stm32_1wire_in(priv, STM32_USART_CR1_OFFSET); enabled = cr1 & USART_CR1_UE; if (enabled) { cr1 &= ~USART_CR1_UE; - stm32_1wire_out(priv, STM32L4_USART_CR1_OFFSET, cr1); + stm32_1wire_out(priv, STM32_USART_CR1_OFFSET, cr1); } /* In case of oversampling by 8, the equation is: @@ -428,12 +428,12 @@ static void stm32_1wire_set_baud(struct stm32_1wire_priv_s *priv) cr1 |= USART_CR1_OVER8; } - stm32_1wire_out(priv, STM32L4_USART_CR1_OFFSET, cr1); - stm32_1wire_out(priv, STM32L4_USART_BRR_OFFSET, brr); + stm32_1wire_out(priv, STM32_USART_CR1_OFFSET, cr1); + stm32_1wire_out(priv, STM32_USART_BRR_OFFSET, brr); if (enabled) { - stm32_1wire_out(priv, STM32L4_USART_CR1_OFFSET, cr1 | USART_CR1_UE); + stm32_1wire_out(priv, STM32_USART_CR1_OFFSET, cr1 | USART_CR1_UE); } } @@ -463,38 +463,38 @@ static void stm32_1wire_set_apb_clock(struct stm32_1wire_priv_s *priv, default: return; -#ifdef CONFIG_STM32L4_USART1_1WIREDRIVER - case STM32L4_USART1_BASE: +#ifdef CONFIG_STM32_USART1_1WIREDRIVER + case STM32_USART1_BASE: rcc_en = RCC_APB2ENR_USART1EN; - regaddr = STM32L4_RCC_APB2ENR; + regaddr = STM32_RCC_APB2ENR; break; #endif -#ifdef CONFIG_STM32L4_USART2_1WIREDRIVER - case STM32L4_USART2_BASE: +#ifdef CONFIG_STM32_USART2_1WIREDRIVER + case STM32_USART2_BASE: rcc_en = RCC_APB1ENR1_USART2EN; - regaddr = STM32L4_RCC_APB1ENR1; + regaddr = STM32_RCC_APB1ENR1; break; #endif -#ifdef CONFIG_STM32L4_USART3_1WIREDRIVER - case STM32L4_USART3_BASE: +#ifdef CONFIG_STM32_USART3_1WIREDRIVER + case STM32_USART3_BASE: rcc_en = RCC_APB1ENR1_USART3EN; - regaddr = STM32L4_RCC_APB1ENR1; + regaddr = STM32_RCC_APB1ENR1; break; #endif -#ifdef CONFIG_STM32L4_UART4_1WIREDRIVER - case STM32L4_UART4_BASE: +#ifdef CONFIG_STM32_UART4_1WIREDRIVER + case STM32_UART4_BASE: rcc_en = RCC_APB1ENR1_UART4EN; - regaddr = STM32L4_RCC_APB1ENR1; + regaddr = STM32_RCC_APB1ENR1; break; #endif -#ifdef CONFIG_STM32L4_UART5_1WIREDRIVER - case STM32L4_UART5_BASE: +#ifdef CONFIG_STM32_UART5_1WIREDRIVER + case STM32_UART5_BASE: rcc_en = RCC_APB1ENR1_UART5EN; - regaddr = STM32L4_RCC_APB1ENR1; + regaddr = STM32_RCC_APB1ENR1; break; #endif } @@ -534,33 +534,33 @@ static int stm32_1wire_init(struct stm32_1wire_priv_s *priv) * Set LBDIE */ - regval = stm32_1wire_in(priv, STM32L4_USART_CR2_OFFSET); + regval = stm32_1wire_in(priv, STM32_USART_CR2_OFFSET); regval &= ~(USART_CR2_STOP_MASK | USART_CR2_CLKEN | USART_CR2_CPOL | USART_CR2_CPHA | USART_CR2_LBCL | USART_CR2_LBDIE); regval |= USART_CR2_LBDIE; - stm32_1wire_out(priv, STM32L4_USART_CR2_OFFSET, regval); + stm32_1wire_out(priv, STM32_USART_CR2_OFFSET, regval); /* Configure CR1 * Clear TE, REm, all interrupt enable bits, PCE, PS and M * Set RXNEIE */ - regval = stm32_1wire_in(priv, STM32L4_USART_CR1_OFFSET); + regval = stm32_1wire_in(priv, STM32_USART_CR1_OFFSET); regval &= ~(USART_CR1_TE | USART_CR1_RE | USART_CR1_ALLINTS | USART_CR1_PCE | USART_CR1_PS | USART_CR1_M0 | USART_CR1_M1); regval |= USART_CR1_RXNEIE; - stm32_1wire_out(priv, STM32L4_USART_CR1_OFFSET, regval); + stm32_1wire_out(priv, STM32_USART_CR1_OFFSET, regval); /* Configure CR3 * Clear CTSE, RTSE, and all interrupt enable bits * Set ONEBIT, HDSEL and EIE */ - regval = stm32_1wire_in(priv, STM32L4_USART_CR3_OFFSET); + regval = stm32_1wire_in(priv, STM32_USART_CR3_OFFSET); regval &= ~(USART_CR3_CTSIE | USART_CR3_CTSE | USART_CR3_RTSE | USART_CR3_EIE); regval |= (USART_CR3_ONEBIT | USART_CR3_HDSEL | USART_CR3_EIE); - stm32_1wire_out(priv, STM32L4_USART_CR3_OFFSET, regval); + stm32_1wire_out(priv, STM32_USART_CR3_OFFSET, regval); /* Set baud rate */ @@ -569,13 +569,13 @@ static int stm32_1wire_init(struct stm32_1wire_priv_s *priv) /* Enable Rx, Tx, and the USART */ - regval = stm32_1wire_in(priv, STM32L4_USART_CR1_OFFSET); + regval = stm32_1wire_in(priv, STM32_USART_CR1_OFFSET); regval |= (USART_CR1_UE | USART_CR1_TE | USART_CR1_RE); - stm32_1wire_out(priv, STM32L4_USART_CR1_OFFSET, regval); + stm32_1wire_out(priv, STM32_USART_CR1_OFFSET, regval); /* Configure pins for USART use */ - stm32l4_configgpio(config->data_pin); + stm32_configgpio(config->data_pin); ret = irq_attach(config->irq, stm32_1wire_isr, priv); if (ret == OK) @@ -604,25 +604,25 @@ static int stm32_1wire_deinit(struct stm32_1wire_priv_s *priv) /* Unconfigure GPIO pins */ - stm32l4_unconfiggpio(config->data_pin); + stm32_unconfiggpio(config->data_pin); /* Disable RXNEIE, Rx, Tx, and the USART */ - regval = stm32_1wire_in(priv, STM32L4_USART_CR1_OFFSET); + regval = stm32_1wire_in(priv, STM32_USART_CR1_OFFSET); regval &= ~(USART_CR1_UE | USART_CR1_TE | USART_CR1_RE | USART_CR1_RXNEIE); - stm32_1wire_out(priv, STM32L4_USART_CR1_OFFSET, regval); + stm32_1wire_out(priv, STM32_USART_CR1_OFFSET, regval); /* Clear LBDIE */ - regval = stm32_1wire_in(priv, STM32L4_USART_CR2_OFFSET); + regval = stm32_1wire_in(priv, STM32_USART_CR2_OFFSET); regval &= ~USART_CR2_LBDIE; - stm32_1wire_out(priv, STM32L4_USART_CR2_OFFSET, regval); + stm32_1wire_out(priv, STM32_USART_CR2_OFFSET, regval); /* Clear ONEBIT, HDSEL and EIE */ - regval = stm32_1wire_in(priv, STM32L4_USART_CR3_OFFSET); + regval = stm32_1wire_in(priv, STM32_USART_CR3_OFFSET); regval &= ~(USART_CR3_ONEBIT | USART_CR3_HDSEL | USART_CR3_EIE); - stm32_1wire_out(priv, STM32L4_USART_CR3_OFFSET, regval); + stm32_1wire_out(priv, STM32_USART_CR3_OFFSET, regval); /* Disable USART APB1/2 clock */ @@ -765,7 +765,7 @@ static int stm32_1wire_isr(int irq, void *context, void *arg) /* Get the masked USART status word. */ - sr = stm32_1wire_in(priv, STM32L4_USART_ISR_OFFSET); + sr = stm32_1wire_in(priv, STM32_USART_ISR_OFFSET); /* Receive loop */ @@ -858,7 +858,7 @@ static int stm32_1wire_isr(int irq, void *context, void *arg) * interrupt clear register (ICR). */ - stm32_1wire_out(priv, STM32L4_USART_ICR_OFFSET, + stm32_1wire_out(priv, STM32_USART_ICR_OFFSET, (USART_ICR_NCF | USART_ICR_ORECF | USART_ICR_FECF)); if (priv->msgs != NULL) @@ -873,7 +873,7 @@ static int stm32_1wire_isr(int irq, void *context, void *arg) if ((sr & USART_ISR_LBDF) != 0) { - stm32_1wire_out(priv, STM32L4_USART_ICR_OFFSET, USART_ICR_LBDCF); + stm32_1wire_out(priv, STM32_USART_ICR_OFFSET, USART_ICR_LBDCF); if (priv->msgs != NULL) { @@ -1125,7 +1125,7 @@ static int stm32_1wire_pm_prepare(struct pm_callback_s *cb, int domain, ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_1wireinitialize + * Name: stm32_1wireinitialize * * Description: * Initialize the selected 1-Wire port. And return a unique instance of @@ -1141,7 +1141,7 @@ static int stm32_1wire_pm_prepare(struct pm_callback_s *cb, int domain, * ****************************************************************************/ -struct onewire_dev_s *stm32l4_1wireinitialize(int port) +struct onewire_dev_s *stm32_1wireinitialize(int port) { struct stm32_1wire_priv_s *priv = NULL; /* Private data of device with multiple instances */ struct stm32_1wire_inst_s *inst = NULL; /* Device, single instance */ @@ -1150,31 +1150,31 @@ struct onewire_dev_s *stm32l4_1wireinitialize(int port) switch (port) { -#ifdef CONFIG_STM32L4_USART1_1WIREDRIVER +#ifdef CONFIG_STM32_USART1_1WIREDRIVER case 1: priv = &stm32_1wire1_priv; break; #endif -#ifdef CONFIG_STM32L4_USART2_1WIREDRIVER +#ifdef CONFIG_STM32_USART2_1WIREDRIVER case 2: priv = &stm32_1wire2_priv; break; #endif -#ifdef CONFIG_STM32L4_USART3_1WIREDRIVER +#ifdef CONFIG_STM32_USART3_1WIREDRIVER case 3: priv = &stm32_1wire3_priv; break; #endif -#ifdef CONFIG_STM32L4_UART4_1WIREDRIVER +#ifdef CONFIG_STM32_UART4_1WIREDRIVER case 4: priv = &stm32_1wire4_priv; break; #endif -#ifdef CONFIG_STM32L4_UART5_1WIREDRIVER +#ifdef CONFIG_STM32_UART5_1WIREDRIVER case 5: priv = &stm32_1wire5_priv; break; @@ -1218,13 +1218,13 @@ struct onewire_dev_s *stm32l4_1wireinitialize(int port) } /**************************************************************************** - * Name: stm32l4_1wireuninitialize + * Name: stm32_1wireuninitialize * * Description: * De-initialize the selected 1-Wire port, and power down the device. * * Input Parameters: - * Device structure as returned by the stm32l4_1wireinitialize() + * Device structure as returned by the stm32_1wireinitialize() * * Returned Value: * OK on success, ERROR when internal reference count mismatch or dev @@ -1232,7 +1232,7 @@ struct onewire_dev_s *stm32l4_1wireinitialize(int port) * ****************************************************************************/ -int stm32l4_1wireuninitialize(struct onewire_dev_s *dev) +int stm32_1wireuninitialize(struct onewire_dev_s *dev) { struct stm32_1wire_priv_s *priv = ((struct stm32_1wire_inst_s *)dev)->priv; diff --git a/arch/arm/src/stm32l4/stm32l4_1wire.h b/arch/arm/src/stm32l4/stm32l4_1wire.h index b196230e6557d..9cb407b6ac401 100644 --- a/arch/arm/src/stm32l4/stm32l4_1wire.h +++ b/arch/arm/src/stm32l4/stm32l4_1wire.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32L4_STM32L4_1WIRE_H -#define __ARCH_ARM_SRC_STM32L4_STM32L4_1WIRE_H +#ifndef __ARCH_ARM_SRC_STM32L4_STM32_1WIRE_H +#define __ARCH_ARM_SRC_STM32L4_STM32_1WIRE_H /**************************************************************************** * Included Files @@ -36,7 +36,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_1wireinitialize + * Name: stm32_1wireinitialize * * Description: * Initialize the selected 1-Wire port. And return a unique instance of @@ -52,16 +52,16 @@ * ****************************************************************************/ -struct onewire_dev_s *stm32l4_1wireinitialize(int port); +struct onewire_dev_s *stm32_1wireinitialize(int port); /**************************************************************************** - * Name: stm32l4_1wireuninitialize + * Name: stm32_1wireuninitialize * * Description: * De-initialize the selected 1-Wire port, and power down the device. * * Input Parameters: - * Device structure as returned by the stm32l4_1wireinitialize() + * Device structure as returned by the stm32_1wireinitialize() * * Returned Value: * OK on success, ERROR when internal reference count mismatch or dev @@ -69,6 +69,6 @@ struct onewire_dev_s *stm32l4_1wireinitialize(int port); * ****************************************************************************/ -int stm32l4_1wireuninitialize(struct onewire_dev_s *dev); +int stm32_1wireuninitialize(struct onewire_dev_s *dev); -#endif /* __ARCH_ARM_SRC_STM32L4_STM32L4_1WIRE_H */ +#endif /* __ARCH_ARM_SRC_STM32L4_STM32_1WIRE_H */ diff --git a/arch/arm/src/stm32l4/stm32l4_adc.c b/arch/arm/src/stm32l4/stm32l4_adc.c index d6f484eed911f..ee7347f7f56fd 100644 --- a/arch/arm/src/stm32l4/stm32l4_adc.c +++ b/arch/arm/src/stm32l4/stm32l4_adc.c @@ -56,16 +56,16 @@ /* Some ADC peripheral must be enabled */ -#if defined(CONFIG_STM32L4_ADC1) || defined(CONFIG_STM32L4_ADC2) || \ - defined(CONFIG_STM32L4_ADC3) +#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) || \ + defined(CONFIG_STM32_ADC3) -#if !(defined(CONFIG_STM32L4_STM32L4X3) || defined(CONFIG_STM32L4_STM32L4X5) || \ - defined(CONFIG_STM32L4_STM32L4X6) || defined(CONFIG_STM32L4_STM32L4XR)) +#if !(defined(CONFIG_STM32_STM32L4X3) || defined(CONFIG_STM32_STM32L4X5) || \ + defined(CONFIG_STM32_STM32L4X6) || defined(CONFIG_STM32_STM32L4XR)) # error "Unrecognized STM32 chip" #endif -#if defined(CONFIG_STM32L4_STM32L4X3) || defined(CONFIG_STM32L4_STM32L4XR) -# if defined(CONFIG_STM32L4_ADC2) || defined(CONFIG_STM32L4_ADC3) +#if defined(CONFIG_STM32_STM32L4X3) || defined(CONFIG_STM32_STM32L4XR) +# if defined(CONFIG_STM32_ADC2) || defined(CONFIG_STM32_ADC3) # error "Using non-existent ADC" # endif #endif @@ -81,23 +81,23 @@ /* RCC reset ****************************************************************/ -#define STM32L4_RCC_RSTR STM32L4_RCC_AHB2RSTR +#define STM32_RCC_RSTR STM32_RCC_AHB2RSTR #define RCC_RSTR_ADC1RST RCC_AHB2RSTR_ADCRST #define RCC_RSTR_ADC2RST RCC_AHB2RSTR_ADCRST #define RCC_RSTR_ADC3RST RCC_AHB2RSTR_ADCRST /* ADC interrupts ***********************************************************/ -#if defined(CONFIG_STM32L4_STM32L4X3) || defined(CONFIG_STM32L4_STM32L4XR) -# define STM32L4_IRQ_ADC12 STM32L4_IRQ_ADC1 +#if defined(CONFIG_STM32_STM32L4X3) || defined(CONFIG_STM32_STM32L4XR) +# define STM32_IRQ_ADC12 STM32_IRQ_ADC1 #endif /* ADC Channels/DMA *********************************************************/ #ifdef ADC_HAVE_DMA -# if !defined(CONFIG_STM32L4_DMA1) && !defined(CONFIG_STM32L4_DMA2) +# if !defined(CONFIG_STM32_DMA1) && !defined(CONFIG_STM32_DMA2) # /* REVISIT: check accordingly to which one is configured in board.h */ -# error "STM32L4 ADC DMA support requires CONFIG_STM32L4_DMA1 or CONFIG_STM32L4_DMA2" +# error "STM32L4 ADC DMA support requires CONFIG_STM32_DMA1 or CONFIG_STM32_DMA2" # endif #endif @@ -110,10 +110,10 @@ /* Sample time default configuration */ -#ifndef CONFIG_STM32L4_ADC_SMPR +#ifndef CONFIG_STM32_ADC_SMPR # define ADC_SMPR_DEFAULT ADC_SMPR_640p5 #else -# define ADC_SMPR_DEFAULT CONFIG_STM32L4_ADC_SMPR +# define ADC_SMPR_DEFAULT CONFIG_STM32_ADC_SMPR #endif #define ADC_SMPR1_DEFAULT ((ADC_SMPR_DEFAULT << ADC_SMPR1_SMP0_SHIFT) | \ @@ -161,10 +161,10 @@ struct stm32_dev_s { -#ifdef CONFIG_STM32L4_ADC_LL_OPS +#ifdef CONFIG_STM32_ADC_LL_OPS const struct stm32_adc_ops_s *llops; /* Low-level ADC ops */ #endif -#ifndef CONFIG_STM32L4_ADC_NOIRQ +#ifndef CONFIG_STM32_ADC_NOIRQ const struct adc_callback_s *cb; uint8_t irq; /* Interrupt generated by this ADC block */ #endif @@ -219,7 +219,7 @@ struct stm32_dev_s /* List of selected ADC channels to sample */ - uint8_t r_chanlist[CONFIG_STM32L4_ADC_MAX_SAMPLES]; + uint8_t r_chanlist[CONFIG_STM32_ADC_MAX_SAMPLES]; #ifdef ADC_HAVE_INJECTED /* List of selected ADC injected channels to sample */ @@ -280,12 +280,12 @@ static int adc_timinit(struct stm32_dev_s *priv); #ifdef ADC_HAVE_DMA static void adc_dma_cfg(struct stm32_dev_s *priv); static void adc_dma_start(struct adc_dev_s *dev); -# ifndef CONFIG_STM32L4_ADC_NOIRQ +# ifndef CONFIG_STM32_ADC_NOIRQ static void adc_dmaconvcallback(DMA_HANDLE handle, uint8_t isr, void *arg); # endif #endif -#if defined(ADC_HAVE_DFSDM) || defined(CONFIG_STM32L4_ADC_LL_OPS) +#if defined(ADC_HAVE_DFSDM) || defined(CONFIG_STM32_ADC_LL_OPS) static int adc_offset_set(struct stm32_dev_s *priv, uint8_t ch, uint8_t i, uint16_t offset); #endif @@ -303,7 +303,7 @@ static int adc_pm_prepare(struct pm_callback_s *cb, int domain, enum pm_state_e state); #endif -#ifdef CONFIG_STM32L4_ADC_LL_OPS +#ifdef CONFIG_STM32_ADC_LL_OPS static void adc_llops_intack(struct stm32_adc_dev_s *dev, uint32_t source); static void adc_llops_inten(struct stm32_adc_dev_s *dev, @@ -339,19 +339,19 @@ static uint32_t adc_llops_injget(struct stm32_adc_dev_s *dev, static void adc_llops_inj_startconv(struct stm32_adc_dev_s *dev, bool enable); # endif -#endif /* CONFIG_STM32L4_ADC_LL_OPS */ +#endif /* CONFIG_STM32_ADC_LL_OPS */ /* ADC Interrupt Handler */ -#ifndef CONFIG_STM32L4_ADC_NOIRQ +#ifndef CONFIG_STM32_ADC_NOIRQ static int adc_interrupt(struct adc_dev_s *dev, uint32_t regval); -# if defined(CONFIG_STM32L4_ADC1) || defined(CONFIG_STM32L4_ADC2) +# if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) static int adc12_interrupt(int irq, void *context, void *arg); # endif -# if defined(CONFIG_STM32L4_ADC3) +# if defined(CONFIG_STM32_ADC3) static int adc3_interrupt(int irq, void *context, void *arg); # endif -#endif /* CONFIG_STM32L4_ADC_NOIRQ */ +#endif /* CONFIG_STM32_ADC_NOIRQ */ /* ADC Driver Methods */ @@ -381,7 +381,7 @@ static const struct adc_ops_s g_adcops = /* Publicly visible ADC lower-half operations */ -#ifdef CONFIG_STM32L4_ADC_LL_OPS +#ifdef CONFIG_STM32_ADC_LL_OPS static const struct stm32_adc_ops_s g_adc_llops = { .int_ack = adc_llops_intack, @@ -408,31 +408,31 @@ static const struct stm32_adc_ops_s g_adc_llops = # endif .dump_regs = adc_llops_dumpregs }; -#endif /* CONFIG_STM32L4_ADC_LL_OPS */ +#endif /* CONFIG_STM32_ADC_LL_OPS */ /* ADC1 state */ -#ifdef CONFIG_STM32L4_ADC1 +#ifdef CONFIG_STM32_ADC1 #ifdef ADC1_HAVE_DMA -static uint16_t g_adc1_dmabuffer[CONFIG_STM32L4_ADC_MAX_SAMPLES * - CONFIG_STM32L4_ADC1_DMA_BATCH]; +static uint16_t g_adc1_dmabuffer[CONFIG_STM32_ADC_MAX_SAMPLES * + CONFIG_STM32_ADC1_DMA_BATCH]; #endif static struct stm32_dev_s g_adcpriv1 = { -#ifdef CONFIG_STM32L4_ADC_LL_OPS +#ifdef CONFIG_STM32_ADC_LL_OPS .llops = &g_adc_llops, #endif -#ifndef CONFIG_STM32L4_ADC_NOIRQ - .irq = STM32L4_IRQ_ADC12, +#ifndef CONFIG_STM32_ADC_NOIRQ + .irq = STM32_IRQ_ADC12, .isr = adc12_interrupt, -#endif /* CONFIG_STM32L4_ADC_NOIRQ */ +#endif /* CONFIG_STM32_ADC_NOIRQ */ .intf = 1, #ifdef HAVE_ADC_RESOLUTION - .resolution = CONFIG_STM32L4_ADC1_RESOLUTION, + .resolution = CONFIG_STM32_ADC1_RESOLUTION, #endif - .base = STM32L4_ADC1_BASE, + .base = STM32_ADC1_BASE, #if defined(ADC1_HAVE_TIMER) || defined(ADC1_HAVE_EXTCFG) .extcfg = ADC1_EXTCFG_VALUE, #endif @@ -443,14 +443,14 @@ static struct stm32_dev_s g_adcpriv1 = .channel = ADC1_TIMER_CHANNEL, .tbase = ADC1_TIMER_BASE, .pclck = ADC1_TIMER_PCLK_FREQUENCY, - .freq = CONFIG_STM32L4_ADC1_SAMPLE_FREQUENCY, + .freq = CONFIG_STM32_ADC1_SAMPLE_FREQUENCY, #endif #ifdef ADC1_HAVE_DMA .dmachan = ADC1_DMA_CHAN, - .dmacfg = CONFIG_STM32L4_ADC1_DMA_CFG, + .dmacfg = CONFIG_STM32_ADC1_DMA_CFG, .hasdma = true, .r_dmabuffer = g_adc1_dmabuffer, - .dmabatch = CONFIG_STM32L4_ADC1_DMA_BATCH + .dmabatch = CONFIG_STM32_ADC1_DMA_BATCH #endif #ifdef ADC1_HAVE_DFSDM .hasdfsdm = true, @@ -472,27 +472,27 @@ static struct adc_dev_s g_adcdev1 = /* ADC2 state */ -#ifdef CONFIG_STM32L4_ADC2 +#ifdef CONFIG_STM32_ADC2 #ifdef ADC2_HAVE_DMA -static uint16_t g_adc2_dmabuffer[CONFIG_STM32L4_ADC_MAX_SAMPLES * - CONFIG_STM32L4_ADC2_DMA_BATCH]; +static uint16_t g_adc2_dmabuffer[CONFIG_STM32_ADC_MAX_SAMPLES * + CONFIG_STM32_ADC2_DMA_BATCH]; #endif static struct stm32_dev_s g_adcpriv2 = { -#ifdef CONFIG_STM32L4_ADC_LL_OPS +#ifdef CONFIG_STM32_ADC_LL_OPS .llops = &g_adc_llops, #endif -#ifndef CONFIG_STM32L4_ADC_NOIRQ - .irq = STM32L4_IRQ_ADC12, +#ifndef CONFIG_STM32_ADC_NOIRQ + .irq = STM32_IRQ_ADC12, .isr = adc12_interrupt, -#endif /* CONFIG_STM32L4_ADC_NOIRQ */ +#endif /* CONFIG_STM32_ADC_NOIRQ */ .intf = 2, #ifdef HAVE_ADC_RESOLUTION - .resolution = CONFIG_STM32L4_ADC2_RESOLUTION, + .resolution = CONFIG_STM32_ADC2_RESOLUTION, #endif - .base = STM32L4_ADC2_BASE, + .base = STM32_ADC2_BASE, #if defined(ADC2_HAVE_TIMER) || defined(ADC2_HAVE_EXTCFG) .extcfg = ADC2_EXTCFG_VALUE, #endif @@ -503,14 +503,14 @@ static struct stm32_dev_s g_adcpriv2 = .channel = ADC2_TIMER_CHANNEL, .tbase = ADC2_TIMER_BASE, .pclck = ADC2_TIMER_PCLK_FREQUENCY, - .freq = CONFIG_STM32L4_ADC2_SAMPLE_FREQUENCY, + .freq = CONFIG_STM32_ADC2_SAMPLE_FREQUENCY, #endif #ifdef ADC2_HAVE_DMA .dmachan = ADC2_DMA_CHAN, - .dmacfg = CONFIG_STM32L4_ADC2_DMA_CFG, + .dmacfg = CONFIG_STM32_ADC2_DMA_CFG, .hasdma = true, .r_dmabuffer = g_adc2_dmabuffer, - .dmabatch = CONFIG_STM32L4_ADC2_DMA_BATCH + .dmabatch = CONFIG_STM32_ADC2_DMA_BATCH #endif #ifdef ADC2_HAVE_DFSDM .hasdfsdm = true, @@ -532,27 +532,27 @@ static struct adc_dev_s g_adcdev2 = /* ADC3 state */ -#ifdef CONFIG_STM32L4_ADC3 +#ifdef CONFIG_STM32_ADC3 #ifdef ADC3_HAVE_DMA -static uint16_t g_adc3_dmabuffer[CONFIG_STM32L4_ADC_MAX_SAMPLES * - CONFIG_STM32L4_ADC3_DMA_BATCH]; +static uint16_t g_adc3_dmabuffer[CONFIG_STM32_ADC_MAX_SAMPLES * + CONFIG_STM32_ADC3_DMA_BATCH]; #endif static struct stm32_dev_s g_adcpriv3 = { -#ifdef CONFIG_STM32L4_ADC_LL_OPS +#ifdef CONFIG_STM32_ADC_LL_OPS .llops = &g_adc_llops, #endif -#ifndef CONFIG_STM32L4_ADC_NOIRQ - .irq = STM32L4_IRQ_ADC3, +#ifndef CONFIG_STM32_ADC_NOIRQ + .irq = STM32_IRQ_ADC3, .isr = adc3_interrupt, -#endif /* CONFIG_STM32L4_ADC_NOIRQ */ +#endif /* CONFIG_STM32_ADC_NOIRQ */ .intf = 3, #ifdef HAVE_ADC_RESOLUTION - .resolution = CONFIG_STM32L4_ADC3_RESOLUTION, + .resolution = CONFIG_STM32_ADC3_RESOLUTION, #endif - .base = STM32L4_ADC3_BASE, + .base = STM32_ADC3_BASE, #if defined(ADC3_HAVE_TIMER) || defined(ADC3_HAVE_EXTCFG) .extcfg = ADC3_EXTCFG_VALUE, #endif @@ -563,14 +563,14 @@ static struct stm32_dev_s g_adcpriv3 = .channel = ADC3_TIMER_CHANNEL, .tbase = ADC3_TIMER_BASE, .pclck = ADC3_TIMER_PCLK_FREQUENCY, - .freq = CONFIG_STM32L4_ADC3_SAMPLE_FREQUENCY, + .freq = CONFIG_STM32_ADC3_SAMPLE_FREQUENCY, #endif #ifdef ADC3_HAVE_DMA .dmachan = ADC3_DMA_CHAN, - .dmacfg = CONFIG_STM32L4_ADC3_DMA_CFG, + .dmacfg = CONFIG_STM32_ADC3_DMA_CFG, .hasdma = true, .r_dmabuffer = g_adc3_dmabuffer, - .dmabatch = CONFIG_STM32L4_ADC3_DMA_BATCH + .dmabatch = CONFIG_STM32_ADC3_DMA_BATCH #endif #ifdef ADC3_HAVE_DFSDM .hasdfsdm = true, @@ -771,38 +771,38 @@ static void tim_dumpregs(struct stm32_dev_s *priv, const char *msg) { ainfo("%s:\n", msg); ainfo(" CR1: %04x CR2: %04x SMCR: %04x DIER: %04x\n", - tim_getreg(priv, STM32L4_GTIM_CR1_OFFSET), - tim_getreg(priv, STM32L4_GTIM_CR2_OFFSET), - tim_getreg(priv, STM32L4_GTIM_SMCR_OFFSET), - tim_getreg(priv, STM32L4_GTIM_DIER_OFFSET)); + tim_getreg(priv, STM32_GTIM_CR1_OFFSET), + tim_getreg(priv, STM32_GTIM_CR2_OFFSET), + tim_getreg(priv, STM32_GTIM_SMCR_OFFSET), + tim_getreg(priv, STM32_GTIM_DIER_OFFSET)); ainfo(" SR: %04x EGR: 0000 CCMR1: %04x CCMR2: %04x\n", - tim_getreg(priv, STM32L4_GTIM_SR_OFFSET), - tim_getreg(priv, STM32L4_GTIM_CCMR1_OFFSET), - tim_getreg(priv, STM32L4_GTIM_CCMR2_OFFSET)); + tim_getreg(priv, STM32_GTIM_SR_OFFSET), + tim_getreg(priv, STM32_GTIM_CCMR1_OFFSET), + tim_getreg(priv, STM32_GTIM_CCMR2_OFFSET)); ainfo(" CCER: %04x CNT: %04x PSC: %04x ARR: %04x\n", - tim_getreg(priv, STM32L4_GTIM_CCER_OFFSET), - tim_getreg(priv, STM32L4_GTIM_CNT_OFFSET), - tim_getreg(priv, STM32L4_GTIM_PSC_OFFSET), - tim_getreg(priv, STM32L4_GTIM_ARR_OFFSET)); + tim_getreg(priv, STM32_GTIM_CCER_OFFSET), + tim_getreg(priv, STM32_GTIM_CNT_OFFSET), + tim_getreg(priv, STM32_GTIM_PSC_OFFSET), + tim_getreg(priv, STM32_GTIM_ARR_OFFSET)); ainfo(" CCR1: %04x CCR2: %04x CCR3: %04x CCR4: %04x\n", - tim_getreg(priv, STM32L4_GTIM_CCR1_OFFSET), - tim_getreg(priv, STM32L4_GTIM_CCR2_OFFSET), - tim_getreg(priv, STM32L4_GTIM_CCR3_OFFSET), - tim_getreg(priv, STM32L4_GTIM_CCR4_OFFSET)); + tim_getreg(priv, STM32_GTIM_CCR1_OFFSET), + tim_getreg(priv, STM32_GTIM_CCR2_OFFSET), + tim_getreg(priv, STM32_GTIM_CCR3_OFFSET), + tim_getreg(priv, STM32_GTIM_CCR4_OFFSET)); - if (priv->tbase == STM32L4_TIM1_BASE || priv->tbase == STM32L4_TIM8_BASE) + if (priv->tbase == STM32_TIM1_BASE || priv->tbase == STM32_TIM8_BASE) { ainfo(" RCR: %04x BDTR: %04x DCR: %04x DMAR: %04x\n", - tim_getreg(priv, STM32L4_ATIM_RCR_OFFSET), - tim_getreg(priv, STM32L4_ATIM_BDTR_OFFSET), - tim_getreg(priv, STM32L4_ATIM_DCR_OFFSET), - tim_getreg(priv, STM32L4_ATIM_DMAR_OFFSET)); + tim_getreg(priv, STM32_ATIM_RCR_OFFSET), + tim_getreg(priv, STM32_ATIM_BDTR_OFFSET), + tim_getreg(priv, STM32_ATIM_DCR_OFFSET), + tim_getreg(priv, STM32_ATIM_DMAR_OFFSET)); } else { ainfo(" DCR: %04x DMAR: %04x\n", - tim_getreg(priv, STM32L4_GTIM_DCR_OFFSET), - tim_getreg(priv, STM32L4_GTIM_DMAR_OFFSET)); + tim_getreg(priv, STM32_GTIM_DCR_OFFSET), + tim_getreg(priv, STM32_GTIM_DMAR_OFFSET)); } } #endif @@ -830,14 +830,14 @@ static void adc_timstart(struct stm32_dev_s *priv, bool enable) { /* Start the counter */ - tim_modifyreg(priv, STM32L4_GTIM_EGR_OFFSET, 0, GTIM_EGR_UG); - tim_modifyreg(priv, STM32L4_GTIM_CR1_OFFSET, 0, GTIM_CR1_CEN); + tim_modifyreg(priv, STM32_GTIM_EGR_OFFSET, 0, GTIM_EGR_UG); + tim_modifyreg(priv, STM32_GTIM_CR1_OFFSET, 0, GTIM_CR1_CEN); } else { /* Disable the counter */ - tim_modifyreg(priv, STM32L4_GTIM_CR1_OFFSET, GTIM_CR1_CEN, 0); + tim_modifyreg(priv, STM32_GTIM_CR1_OFFSET, GTIM_CR1_CEN, 0); } } #endif @@ -870,7 +870,7 @@ static int adc_timinit(struct stm32_dev_s *priv) uint16_t ccmr_val = 0; uint16_t ccmr_mask = 0xff; uint16_t ccer_val; - uint8_t ccmr_offset = STM32L4_GTIM_CCMR1_OFFSET; + uint8_t ccmr_offset = STM32_GTIM_CCMR1_OFFSET; uint32_t channel = priv->channel - 1; /* If the timer base address is zero, then this ADC was not configured to @@ -955,30 +955,30 @@ static int adc_timinit(struct stm32_dev_s *priv) clrbits = GTIM_CR1_DIR | GTIM_CR1_CMS_MASK | GTIM_CR1_CKD_MASK; setbits = GTIM_CR1_EDGE; - tim_modifyreg(priv, STM32L4_GTIM_CR1_OFFSET, clrbits, setbits); + tim_modifyreg(priv, STM32_GTIM_CR1_OFFSET, clrbits, setbits); /* Set the ARR Preload Bit */ - tim_modifyreg(priv, STM32L4_GTIM_CR1_OFFSET, 0, GTIM_CR1_ARPE); + tim_modifyreg(priv, STM32_GTIM_CR1_OFFSET, 0, GTIM_CR1_ARPE); /* Set the reload and prescaler values */ - tim_putreg(priv, STM32L4_GTIM_PSC_OFFSET, prescaler - 1); - tim_putreg(priv, STM32L4_GTIM_ARR_OFFSET, reload); + tim_putreg(priv, STM32_GTIM_PSC_OFFSET, prescaler - 1); + tim_putreg(priv, STM32_GTIM_ARR_OFFSET, reload); /* Clear the advanced timers repetition counter in TIM1 */ - if (priv->tbase == STM32L4_TIM1_BASE || priv->tbase == STM32L4_TIM8_BASE) + if (priv->tbase == STM32_TIM1_BASE || priv->tbase == STM32_TIM8_BASE) { - tim_putreg(priv, STM32L4_ATIM_RCR_OFFSET, 0); - tim_putreg(priv, STM32L4_ATIM_BDTR_OFFSET, ATIM_BDTR_MOE); /* Check me */ + tim_putreg(priv, STM32_ATIM_RCR_OFFSET, 0); + tim_putreg(priv, STM32_ATIM_BDTR_OFFSET, ATIM_BDTR_MOE); /* Check me */ } /* Handle channel specific setup */ /* Assume that channel is disabled and polarity is active high */ - ccer_val = tim_getreg(priv, STM32L4_GTIM_CCER_OFFSET); + ccer_val = tim_getreg(priv, STM32_GTIM_CCER_OFFSET); ccer_val &= ~((GTIM_CCER_CC1P | GTIM_CCER_CC1E) << GTIM_CCER_CCXBASE(channel)); @@ -995,41 +995,41 @@ static int adc_timinit(struct stm32_dev_s *priv) if (channel > 1) { - ccmr_offset = STM32L4_GTIM_CCMR2_OFFSET; + ccmr_offset = STM32_GTIM_CCMR2_OFFSET; } ccmr_orig = tim_getreg(priv, ccmr_offset); ccmr_orig &= ~ccmr_mask; ccmr_orig |= ccmr_val; tim_putreg(priv, ccmr_offset, ccmr_orig); - tim_putreg(priv, STM32L4_GTIM_CCER_OFFSET, ccer_val); + tim_putreg(priv, STM32_GTIM_CCER_OFFSET, ccer_val); switch (channel) { case 0: /* TIMx CC1 */ { - tim_putreg(priv, STM32L4_GTIM_CCR1_OFFSET, + tim_putreg(priv, STM32_GTIM_CCR1_OFFSET, (uint16_t)(reload >> 1)); } break; case 1: /* TIMx CC2 */ { - tim_putreg(priv, STM32L4_GTIM_CCR2_OFFSET, + tim_putreg(priv, STM32_GTIM_CCR2_OFFSET, (uint16_t)(reload >> 1)); } break; case 2: /* TIMx CC3 */ { - tim_putreg(priv, STM32L4_GTIM_CCR3_OFFSET, + tim_putreg(priv, STM32_GTIM_CCR3_OFFSET, (uint16_t)(reload >> 1)); } break; case 3: /* TIMx CC4 */ { - tim_putreg(priv, STM32L4_GTIM_CCR4_OFFSET, + tim_putreg(priv, STM32_GTIM_CCR4_OFFSET, (uint16_t)(reload >> 1)); } break; @@ -1063,7 +1063,7 @@ static int adc_pm_prepare(struct pm_callback_s *cb, int domain, container_of(cb, struct stm32_dev_s, pm_callback); uint32_t regval; - regval = adc_getreg(priv, STM32L4_ADC_CR_OFFSET); + regval = adc_getreg(priv, STM32_ADC_CR_OFFSET); if ((state >= PM_IDLE) && (regval & ADC_CR_ADSTART)) { return -EBUSY; @@ -1087,16 +1087,16 @@ static void adc_wdog_enable(struct stm32_dev_s *priv) /* Initialize the Analog watchdog enable */ - regval = adc_getreg(priv, STM32L4_ADC_CFGR_OFFSET); + regval = adc_getreg(priv, STM32_ADC_CFGR_OFFSET); regval |= ADC_CFGR_AWD1EN | ADC_CFGR_CONT | ADC_CFGR_OVRMOD; - adc_putreg(priv, STM32L4_ADC_CFGR_OFFSET, regval); + adc_putreg(priv, STM32_ADC_CFGR_OFFSET, regval); /* Switch to analog watchdog interrupt */ - regval = adc_getreg(priv, STM32L4_ADC_IER_OFFSET); + regval = adc_getreg(priv, STM32_ADC_IER_OFFSET); regval |= ADC_INT_AWD1; regval &= ~ADC_INT_EOC; - adc_putreg(priv, STM32L4_ADC_IER_OFFSET, regval); + adc_putreg(priv, STM32_ADC_IER_OFFSET, regval); } /**************************************************************************** @@ -1119,7 +1119,7 @@ static void adc_startconv(struct stm32_dev_s *priv, bool enable) ainfo("enable: %d\n", enable ? 1 : 0); - regval = adc_getreg(priv, STM32L4_ADC_CR_OFFSET); + regval = adc_getreg(priv, STM32_ADC_CR_OFFSET); if (enable) { /* Start conversion of regular channels */ @@ -1133,7 +1133,7 @@ static void adc_startconv(struct stm32_dev_s *priv, bool enable) regval |= ADC_CR_ADSTP; } - adc_putreg(priv, STM32L4_ADC_CR_OFFSET, regval); + adc_putreg(priv, STM32_ADC_CR_OFFSET, regval); } #ifdef ADC_HAVE_INJECTED @@ -1162,11 +1162,11 @@ static void adc_inj_startconv(struct stm32_dev_s *priv, bool enable) { /* Start the conversion of regular channels */ - adc_modifyreg(priv, STM32L4_ADC_CR_OFFSET, 0, ADC_CR_JADSTART); + adc_modifyreg(priv, STM32_ADC_CR_OFFSET, 0, ADC_CR_JADSTART); } else { - regval = adc_getreg(priv, STM32L4_ADC_CR_OFFSET); + regval = adc_getreg(priv, STM32_ADC_CR_OFFSET); /* Is a conversion ongoing? */ @@ -1174,11 +1174,11 @@ static void adc_inj_startconv(struct stm32_dev_s *priv, bool enable) { /* Stop the conversion */ - adc_putreg(priv, STM32L4_ADC_CR_OFFSET, regval | ADC_CR_JADSTP); + adc_putreg(priv, STM32_ADC_CR_OFFSET, regval | ADC_CR_JADSTP); /* Wait for the conversion to stop */ - while ((adc_getreg(priv, STM32L4_ADC_CR_OFFSET) & + while ((adc_getreg(priv, STM32_ADC_CR_OFFSET) & ADC_CR_JADSTP) != 0); } } @@ -1216,7 +1216,7 @@ static void adc_rccreset(struct stm32_dev_s *priv, bool reset) /* Set or clear the selected bit in the AHB2 reset register */ - regval = getreg32(STM32L4_RCC_AHB2RSTR); + regval = getreg32(STM32_RCC_AHB2RSTR); if (reset) { regval |= RCC_AHB2RSTR_ADCRST; @@ -1226,7 +1226,7 @@ static void adc_rccreset(struct stm32_dev_s *priv, bool reset) regval &= ~RCC_AHB2RSTR_ADCRST; } - putreg32(regval, STM32L4_RCC_AHB2RSTR); + putreg32(regval, STM32_RCC_AHB2RSTR); leave_critical_section(flags); } @@ -1247,13 +1247,13 @@ static void adc_enable(struct stm32_dev_s *priv) { uint32_t regval; - regval = adc_getreg(priv, STM32L4_ADC_CR_OFFSET); + regval = adc_getreg(priv, STM32_ADC_CR_OFFSET); /* Exit deep power down mode and enable voltage regulator */ regval &= ~ADC_CR_DEEPPWD; regval |= ADC_CR_ADVREGEN; - adc_putreg(priv, STM32L4_ADC_CR_OFFSET, regval); + adc_putreg(priv, STM32_ADC_CR_OFFSET, regval); /* Wait for voltage regulator to power up */ @@ -1264,11 +1264,11 @@ static void adc_enable(struct stm32_dev_s *priv) */ regval |= ADC_CR_ADCAL; - adc_putreg(priv, STM32L4_ADC_CR_OFFSET, regval); + adc_putreg(priv, STM32_ADC_CR_OFFSET, regval); /* Wait for calibration to complete */ - while (adc_getreg(priv, STM32L4_ADC_CR_OFFSET) & ADC_CR_ADCAL); + while (adc_getreg(priv, STM32_ADC_CR_OFFSET) & ADC_CR_ADCAL); /* Enable ADC * Note: ADEN bit cannot be set during ADCAL=1 and 4 ADC clock cycle @@ -1277,13 +1277,13 @@ static void adc_enable(struct stm32_dev_s *priv) * ARM instructions. */ - regval = adc_getreg(priv, STM32L4_ADC_CR_OFFSET); + regval = adc_getreg(priv, STM32_ADC_CR_OFFSET); regval |= ADC_CR_ADEN; - adc_putreg(priv, STM32L4_ADC_CR_OFFSET, regval); + adc_putreg(priv, STM32_ADC_CR_OFFSET, regval); /* Wait for hardware to be ready for conversions */ - while (!(adc_getreg(priv, STM32L4_ADC_ISR_OFFSET) & ADC_INT_ADRDY)); + while (!(adc_getreg(priv, STM32_ADC_ISR_OFFSET) & ADC_INT_ADRDY)); } /**************************************************************************** @@ -1298,7 +1298,7 @@ static void adc_enable(struct stm32_dev_s *priv) static int adc_bind(struct adc_dev_s *dev, const struct adc_callback_s *callback) { -#ifndef CONFIG_STM32L4_ADC_NOIRQ +#ifndef CONFIG_STM32_ADC_NOIRQ struct stm32_dev_s *priv = (struct stm32_dev_s *)dev->ad_priv; DEBUGASSERT(priv != NULL); @@ -1353,8 +1353,8 @@ static void adc_reset(struct adc_dev_s *dev) static int adc_setup(struct adc_dev_s *dev) { -#if !defined(CONFIG_STM32L4_ADC_NOIRQ) || defined(ADC_HAVE_TIMER) || \ - !defined(CONFIG_STM32L4_ADC_NO_STARTUP_CONV) || defined(HAVE_ADC_RESOLUTION) +#if !defined(CONFIG_STM32_ADC_NOIRQ) || defined(ADC_HAVE_TIMER) || \ + !defined(CONFIG_STM32_ADC_NO_STARTUP_CONV) || defined(HAVE_ADC_RESOLUTION) struct stm32_dev_s *priv = (struct stm32_dev_s *)dev->ad_priv; #endif int ret = OK; @@ -1364,7 +1364,7 @@ static int adc_setup(struct adc_dev_s *dev) /* Attach the ADC interrupt */ -#ifndef CONFIG_STM32L4_ADC_NOIRQ +#ifndef CONFIG_STM32_ADC_NOIRQ ret = irq_attach(priv->irq, priv->isr, NULL); if (ret < 0) { @@ -1400,7 +1400,7 @@ static int adc_setup(struct adc_dev_s *dev) /* Set CFGR configuration */ - adc_modifyreg(priv, STM32L4_ADC_CFGR_OFFSET, clrbits, setbits); + adc_modifyreg(priv, STM32_ADC_CFGR_OFFSET, clrbits, setbits); /* Configuration of the channel conversions */ @@ -1432,7 +1432,7 @@ static int adc_setup(struct adc_dev_s *dev) adc_internal(priv, &setbits); - stm32_modifyreg32(STM32L4_ADC_CCR, clrbits, setbits); + stm32_modifyreg32(STM32_ADC_CCR, clrbits, setbits); #ifdef ADC_HAVE_DMA if (priv->hasdma) @@ -1479,7 +1479,7 @@ static int adc_setup(struct adc_dev_s *dev) * or later with ANIOC_TRIGGER ioctl call. */ -#ifndef CONFIG_STM32L4_ADC_NO_STARTUP_CONV +#ifndef CONFIG_STM32_ADC_NO_STARTUP_CONV /* Start regular conversion */ if (priv->cchannels > 0) @@ -1496,7 +1496,7 @@ static int adc_setup(struct adc_dev_s *dev) /* Enable the ADC interrupt */ -#ifndef CONFIG_STM32L4_ADC_NOIRQ +#ifndef CONFIG_STM32_ADC_NOIRQ ainfo("Enable the ADC interrupt: irq=%d\n", priv->irq); up_enable_irq(priv->irq); #endif @@ -1536,7 +1536,7 @@ static int adc_setup(struct adc_dev_s *dev) static void adc_shutdown(struct adc_dev_s *dev) { -#ifndef CONFIG_STM32L4_ADC_NOIRQ +#ifndef CONFIG_STM32_ADC_NOIRQ /* Disable ADC interrupts and detach the ADC interrupt handler */ struct stm32_dev_s *priv = (struct stm32_dev_s *)dev->ad_priv; @@ -1569,7 +1569,7 @@ static void adc_rxint(struct adc_dev_s *dev, bool enable) ainfo("intf: %d enable: %d\n", priv->intf, enable ? 1 : 0); - regval = adc_getreg(priv, STM32L4_ADC_IER_OFFSET); + regval = adc_getreg(priv, STM32_ADC_IER_OFFSET); if (enable) { /* Enable end of conversion interrupt */ @@ -1592,7 +1592,7 @@ static void adc_rxint(struct adc_dev_s *dev, bool enable) regval &= ~ADC_INT_MASK; } - adc_putreg(priv, STM32L4_ADC_IER_OFFSET, regval); + adc_putreg(priv, STM32_ADC_IER_OFFSET, regval); } /**************************************************************************** @@ -1615,7 +1615,7 @@ static int adc_resolution_set(struct adc_dev_s *dev, uint8_t res) /* Modify appropriate register */ - adc_modifyreg(priv, STM32L4_ADC_CFGR_OFFSET, ADC_CFGR_RES_MASK, + adc_modifyreg(priv, STM32_ADC_CFGR_OFFSET, ADC_CFGR_RES_MASK, res << ADC_CFGR_RES_SHIFT); errout: @@ -1635,8 +1635,8 @@ static void adc_sample_time_set(struct adc_dev_s *dev) struct stm32_dev_s *priv = (struct stm32_dev_s *)dev->ad_priv; - adc_putreg(priv, STM32L4_ADC_SMPR1_OFFSET, ADC_SMPR1_DEFAULT); - adc_putreg(priv, STM32L4_ADC_SMPR2_OFFSET, ADC_SMPR2_DEFAULT); + adc_putreg(priv, STM32_ADC_SMPR1_OFFSET, ADC_SMPR1_DEFAULT); + adc_putreg(priv, STM32_ADC_SMPR2_OFFSET, ADC_SMPR2_DEFAULT); } /**************************************************************************** @@ -1673,7 +1673,7 @@ static int adc_extsel_set(struct stm32_dev_s *priv, uint32_t extcfg) /* Write register */ - adc_modifyreg(priv, STM32L4_ADC_CFGR_OFFSET, clrbits, setbits); + adc_modifyreg(priv, STM32_ADC_CFGR_OFFSET, clrbits, setbits); } return OK; @@ -1714,7 +1714,7 @@ static int adc_jextsel_set(struct stm32_dev_s *priv, uint32_t jextcfg) /* Write register */ - adc_modifyreg(priv, STM32L4_ADC_JSQR_OFFSET, clrbits, setbits); + adc_modifyreg(priv, STM32_ADC_JSQR_OFFSET, clrbits, setbits); } return OK; @@ -1731,25 +1731,25 @@ static void adc_dumpregs(struct stm32_dev_s *priv) ainfo("ISR: 0x%08" PRIx32 " IER: 0x%08" PRIx32 " CR: 0x%08" PRIx32 " CFGR1: 0x%08" PRIx32 "\n", - adc_getreg(priv, STM32L4_ADC_ISR_OFFSET), - adc_getreg(priv, STM32L4_ADC_IER_OFFSET), - adc_getreg(priv, STM32L4_ADC_CR_OFFSET), - adc_getreg(priv, STM32L4_ADC_CFGR_OFFSET)); + adc_getreg(priv, STM32_ADC_ISR_OFFSET), + adc_getreg(priv, STM32_ADC_IER_OFFSET), + adc_getreg(priv, STM32_ADC_CR_OFFSET), + adc_getreg(priv, STM32_ADC_CFGR_OFFSET)); ainfo("SQR1: 0x%08" PRIx32 " SQR2: 0x%08" PRIx32 " SQR3: 0x%08" PRIx32 " SQR4: 0x%08" PRIx32 "\n", - adc_getreg(priv, STM32L4_ADC_SQR1_OFFSET), - adc_getreg(priv, STM32L4_ADC_SQR2_OFFSET), - adc_getreg(priv, STM32L4_ADC_SQR3_OFFSET), - adc_getreg(priv, STM32L4_ADC_SQR4_OFFSET)); + adc_getreg(priv, STM32_ADC_SQR1_OFFSET), + adc_getreg(priv, STM32_ADC_SQR2_OFFSET), + adc_getreg(priv, STM32_ADC_SQR3_OFFSET), + adc_getreg(priv, STM32_ADC_SQR4_OFFSET)); ainfo("SMPR1: 0x%08" PRIx32 " SMPR2: 0x%08" PRIx32 "\n", - adc_getreg(priv, STM32L4_ADC_SMPR1_OFFSET), - adc_getreg(priv, STM32L4_ADC_SMPR2_OFFSET)); + adc_getreg(priv, STM32_ADC_SMPR1_OFFSET), + adc_getreg(priv, STM32_ADC_SMPR2_OFFSET)); #ifdef ADC_HAVE_INJECTED ainfo("JSQR: 0x%08" PRIx32 "\n", - adc_getreg(priv, STM32L4_ADC_JSQR_OFFSET)); + adc_getreg(priv, STM32_ADC_JSQR_OFFSET)); #endif } @@ -1801,12 +1801,12 @@ static bool adc_internal(struct stm32_dev_s * priv, uint32_t *adc_ccr) break; case 17: -#if !(defined(CONFIG_STM32L4_STM32L4X3) && defined(CONFIG_STM32L4_DAC1_OUTPUT_ADC)) +#if !(defined(CONFIG_STM32_STM32L4X3) && defined(CONFIG_STM32_DAC1_OUTPUT_ADC)) *adc_ccr |= ADC_CCR_TSEN; #endif break; case 18: -#if !(defined(CONFIG_STM32L4_STM32L4X3) && defined(CONFIG_STM32L4_DAC2_OUTPUT_ADC)) +#if !(defined(CONFIG_STM32_STM32L4X3) && defined(CONFIG_STM32_DAC2_OUTPUT_ADC)) *adc_ccr |= ADC_CCR_VBATEN; #endif break; @@ -1824,7 +1824,7 @@ static bool adc_internal(struct stm32_dev_s * priv, uint32_t *adc_ccr) * Name: adc_offset_set ****************************************************************************/ -#if defined(ADC_HAVE_DFSDM) || defined(CONFIG_STM32L4_ADC_LL_OPS) +#if defined(ADC_HAVE_DFSDM) || defined(CONFIG_STM32_ADC_LL_OPS) static int adc_offset_set(struct stm32_dev_s *priv, uint8_t ch, uint8_t i, uint16_t offset) @@ -1841,7 +1841,7 @@ static int adc_offset_set(struct stm32_dev_s *priv, goto errout; } - reg = STM32L4_ADC_OFR1_OFFSET + i * 4; + reg = STM32_ADC_OFR1_OFFSET + i * 4; regval = ADC_OFR_OFFSETY_EN; adc_putreg(priv, reg, regval); @@ -1893,28 +1893,28 @@ static int adc_set_ch(struct adc_dev_s *dev, uint8_t ch) priv->rnchannels = 1; } - DEBUGASSERT(priv->rnchannels <= CONFIG_STM32L4_ADC_MAX_SAMPLES); + DEBUGASSERT(priv->rnchannels <= CONFIG_STM32_ADC_MAX_SAMPLES); bits = adc_sqrbits(priv, ADC_SQR4_FIRST, ADC_SQR4_LAST, ADC_SQR4_SQ_OFFSET); adc_modifyreg(priv, - STM32L4_ADC_SQR4_OFFSET, ~ADC_SQR4_RESERVED, bits); + STM32_ADC_SQR4_OFFSET, ~ADC_SQR4_RESERVED, bits); bits = adc_sqrbits(priv, ADC_SQR3_FIRST, ADC_SQR3_LAST, ADC_SQR3_SQ_OFFSET); adc_modifyreg(priv, - STM32L4_ADC_SQR3_OFFSET, ~ADC_SQR3_RESERVED, bits); + STM32_ADC_SQR3_OFFSET, ~ADC_SQR3_RESERVED, bits); bits = adc_sqrbits(priv, ADC_SQR2_FIRST, ADC_SQR2_LAST, ADC_SQR2_SQ_OFFSET); adc_modifyreg(priv, - STM32L4_ADC_SQR2_OFFSET, ~ADC_SQR2_RESERVED, bits); + STM32_ADC_SQR2_OFFSET, ~ADC_SQR2_RESERVED, bits); bits = ((uint32_t)priv->rnchannels - 1) << ADC_SQR1_L_SHIFT | adc_sqrbits(priv, ADC_SQR1_FIRST, ADC_SQR1_LAST, ADC_SQR1_SQ_OFFSET); adc_modifyreg(priv, - STM32L4_ADC_SQR1_OFFSET, ~ADC_SQR1_RESERVED, bits); + STM32_ADC_SQR1_OFFSET, ~ADC_SQR1_RESERVED, bits); #ifdef ADC_HAVE_DFSDM if (priv->hasdfsdm) @@ -1966,7 +1966,7 @@ static int adc_inj_set_ch(struct adc_dev_s *dev, uint8_t ch) /* Write register */ - adc_modifyreg(priv, STM32L4_ADC_JSQR_OFFSET, clrbits, setbits); + adc_modifyreg(priv, STM32_ADC_JSQR_OFFSET, clrbits, setbits); return OK; } @@ -2026,7 +2026,7 @@ static int adc_ioctl(struct adc_dev_s *dev, int cmd, unsigned long arg) case ANIOC_WDOG_UPPER: /* Set watchdog upper threshold */ { - regval = adc_getreg(priv, STM32L4_ADC_TR1_OFFSET); + regval = adc_getreg(priv, STM32_ADC_TR1_OFFSET); /* Verify new upper threshold greater than lower threshold */ @@ -2041,7 +2041,7 @@ static int adc_ioctl(struct adc_dev_s *dev, int cmd, unsigned long arg) regval &= ~ADC_TR1_HT_MASK; regval |= ((arg << ADC_TR1_HT_SHIFT) & ADC_TR1_HT_MASK); - adc_putreg(priv, STM32L4_ADC_TR1_OFFSET, regval); + adc_putreg(priv, STM32_ADC_TR1_OFFSET, regval); /* Ensure analog watchdog is enabled */ @@ -2051,7 +2051,7 @@ static int adc_ioctl(struct adc_dev_s *dev, int cmd, unsigned long arg) case ANIOC_WDOG_LOWER: /* Set watchdog lower threshold */ { - regval = adc_getreg(priv, STM32L4_ADC_TR1_OFFSET); + regval = adc_getreg(priv, STM32_ADC_TR1_OFFSET); /* Verify new lower threshold less than upper threshold */ @@ -2066,7 +2066,7 @@ static int adc_ioctl(struct adc_dev_s *dev, int cmd, unsigned long arg) regval &= ~ADC_TR1_LT_MASK; regval |= ((arg << ADC_TR1_LT_SHIFT) & ADC_TR1_LT_MASK); - adc_putreg(priv, STM32L4_ADC_TR1_OFFSET, regval); + adc_putreg(priv, STM32_ADC_TR1_OFFSET, regval); /* Ensure analog watchdog is enabled */ @@ -2074,7 +2074,7 @@ static int adc_ioctl(struct adc_dev_s *dev, int cmd, unsigned long arg) } break; - case ANIOC_STM32L4_TRIGGER_REG: + case ANIOC_STM32_TRIGGER_REG: /* Start regular conversion if regular channels configured */ @@ -2086,7 +2086,7 @@ static int adc_ioctl(struct adc_dev_s *dev, int cmd, unsigned long arg) break; #ifdef ADC_HAVE_INJECTED - case ANIOC_STM32L4_TRIGGER_INJ: + case ANIOC_STM32_TRIGGER_INJ: /* Start injected conversion if injected channels configured */ @@ -2107,7 +2107,7 @@ static int adc_ioctl(struct adc_dev_s *dev, int cmd, unsigned long arg) return ret; } -#ifndef CONFIG_STM32L4_ADC_NOIRQ +#ifndef CONFIG_STM32_ADC_NOIRQ /**************************************************************************** * Name: adc_interrupt @@ -2133,7 +2133,7 @@ static int adc_interrupt(struct adc_dev_s *dev, uint32_t adcisr) if ((adcisr & ADC_INT_AWD1) != 0) { - value = adc_getreg(priv, STM32L4_ADC_DR_OFFSET); + value = adc_getreg(priv, STM32_ADC_DR_OFFSET); value &= ADC_DR_MASK; awarn("WARNING: Analog Watchdog, " @@ -2158,7 +2158,7 @@ static int adc_interrupt(struct adc_dev_s *dev, uint32_t adcisr) * (It is cleared by reading the ADC_DR) */ - value = adc_getreg(priv, STM32L4_ADC_DR_OFFSET); + value = adc_getreg(priv, STM32_ADC_DR_OFFSET); value &= ADC_DR_MASK; /* Verify that the upper-half driver has bound its callback functions */ @@ -2198,7 +2198,7 @@ static int adc_interrupt(struct adc_dev_s *dev, uint32_t adcisr) { for (i = 0; i < priv->cjchannels; i++) { - value = adc_getreg(priv, STM32L4_ADC_JDR1_OFFSET + (4 * i)) & + value = adc_getreg(priv, STM32_ADC_JDR1_OFFSET + (4 * i)) & ADC_JDR_MASK; if (priv->cb != NULL) @@ -2225,14 +2225,14 @@ static int adc_interrupt(struct adc_dev_s *dev, uint32_t adcisr) * ****************************************************************************/ -#if defined(CONFIG_STM32L4_ADC1) || defined(CONFIG_STM32L4_ADC2) +#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) static int adc12_interrupt(int irq, void *context, void *arg) { uint32_t regval; uint32_t pending; -#ifdef CONFIG_STM32L4_ADC1 - regval = getreg32(STM32L4_ADC1_ISR); +#ifdef CONFIG_STM32_ADC1 + regval = getreg32(STM32_ADC1_ISR); pending = regval & ADC_INT_MASK; if (pending != 0) { @@ -2240,12 +2240,12 @@ static int adc12_interrupt(int irq, void *context, void *arg) /* Clear interrupts */ - putreg32(regval, STM32L4_ADC1_ISR); + putreg32(regval, STM32_ADC1_ISR); } #endif -#ifdef CONFIG_STM32L4_ADC2 - regval = getreg32(STM32L4_ADC2_ISR); +#ifdef CONFIG_STM32_ADC2 + regval = getreg32(STM32_ADC2_ISR); pending = regval & ADC_INT_MASK; if (pending != 0) { @@ -2253,7 +2253,7 @@ static int adc12_interrupt(int irq, void *context, void *arg) /* Clear interrupts */ - putreg32(regval, STM32L4_ADC2_ISR); + putreg32(regval, STM32_ADC2_ISR); } #endif @@ -2273,13 +2273,13 @@ static int adc12_interrupt(int irq, void *context, void *arg) * ****************************************************************************/ -#ifdef CONFIG_STM32L4_ADC3 +#ifdef CONFIG_STM32_ADC3 static int adc3_interrupt(int irq, void *context, void *arg) { uint32_t regval; uint32_t pending; - regval = getreg32(STM32L4_ADC3_ISR); + regval = getreg32(STM32_ADC3_ISR); pending = regval & ADC_INT_MASK; if (pending != 0) { @@ -2287,13 +2287,13 @@ static int adc3_interrupt(int irq, void *context, void *arg) /* Clear interrupts */ - putreg32(regval, STM32L4_ADC3_ISR); + putreg32(regval, STM32_ADC3_ISR); } return OK; } #endif -#endif /* CONFIG_STM32L4_ADC_NOIRQ */ +#endif /* CONFIG_STM32_ADC_NOIRQ */ #ifdef ADC_HAVE_DMA /**************************************************************************** @@ -2339,7 +2339,7 @@ static void adc_dma_cfg(struct stm32_dev_s *priv) /* Modify CFGR configuration */ - adc_modifyreg(priv, STM32L4_ADC_CFGR_OFFSET, clrbits, setbits); + adc_modifyreg(priv, STM32_ADC_CFGR_OFFSET, clrbits, setbits); } /**************************************************************************** @@ -2354,20 +2354,20 @@ static void adc_dma_start(struct adc_dev_s *dev) if (priv->dma != NULL) { - stm32l4_dmastop(priv->dma); - stm32l4_dmafree(priv->dma); + stm32_dmastop(priv->dma); + stm32_dmafree(priv->dma); } - priv->dma = stm32l4_dmachannel(priv->dmachan); + priv->dma = stm32_dmachannel(priv->dmachan); -#ifndef CONFIG_STM32L4_ADC_NOIRQ - stm32l4_dmasetup(priv->dma, - priv->base + STM32L4_ADC_DR_OFFSET, +#ifndef CONFIG_STM32_ADC_NOIRQ + stm32_dmasetup(priv->dma, + priv->base + STM32_ADC_DR_OFFSET, (uint32_t)priv->r_dmabuffer, priv->rnchannels * priv->dmabatch, ADC_DMA_CONTROL_WORD); - stm32l4_dmastart(priv->dma, adc_dmaconvcallback, dev, false); + stm32_dmastart(priv->dma, adc_dmaconvcallback, dev, false); #endif } @@ -2388,7 +2388,7 @@ static void adc_dma_start(struct adc_dev_s *dev) * ****************************************************************************/ -#ifndef CONFIG_STM32L4_ADC_NOIRQ +#ifndef CONFIG_STM32_ADC_NOIRQ static void adc_dmaconvcallback(DMA_HANDLE handle, uint8_t isr, void *arg) { @@ -2418,13 +2418,13 @@ static void adc_dmaconvcallback(DMA_HANDLE handle, /* Restart DMA for the next conversion series */ - adc_modifyreg(priv, STM32L4_ADC_CFGR_OFFSET, ADC_CFGR_DMAEN, 0); - adc_modifyreg(priv, STM32L4_ADC_CFGR_OFFSET, 0, ADC_CFGR_DMAEN); + adc_modifyreg(priv, STM32_ADC_CFGR_OFFSET, ADC_CFGR_DMAEN, 0); + adc_modifyreg(priv, STM32_ADC_CFGR_OFFSET, 0, ADC_CFGR_DMAEN); } #endif #endif /* ADC_HAVE_DMA */ -#ifdef CONFIG_STM32L4_ADC_LL_OPS +#ifdef CONFIG_STM32_ADC_LL_OPS /**************************************************************************** * Name: adc_llops_intack @@ -2437,7 +2437,7 @@ static void adc_llops_intack(struct stm32_adc_dev_s *dev, /* Clear pending interrupts */ - adc_putreg(priv, STM32L4_ADC_ISR_OFFSET, (source & ADC_ISR_ALLINTS)); + adc_putreg(priv, STM32_ADC_ISR_OFFSET, (source & ADC_ISR_ALLINTS)); } /**************************************************************************** @@ -2451,7 +2451,7 @@ static void adc_llops_inten(struct stm32_adc_dev_s *dev, /* Enable interrupts */ - adc_modifyreg(priv, STM32L4_ADC_IER_OFFSET, 0, (source & ADC_IER_ALLINTS)); + adc_modifyreg(priv, STM32_ADC_IER_OFFSET, 0, (source & ADC_IER_ALLINTS)); } /**************************************************************************** @@ -2465,7 +2465,7 @@ static void adc_llops_intdis(struct stm32_adc_dev_s *dev, /* Disable interrupts */ - adc_modifyreg(priv, STM32L4_ADC_IER_OFFSET, (source & ADC_IER_ALLINTS), 0); + adc_modifyreg(priv, STM32_ADC_IER_OFFSET, (source & ADC_IER_ALLINTS), 0); } /**************************************************************************** @@ -2478,7 +2478,7 @@ static uint32_t adc_llops_intget(struct stm32_adc_dev_s *dev) uint32_t regval; uint32_t pending; - regval = adc_getreg(priv, STM32L4_ADC_ISR_OFFSET); + regval = adc_getreg(priv, STM32_ADC_ISR_OFFSET); pending = regval & ADC_ISR_ALLINTS; return pending; @@ -2492,7 +2492,7 @@ static uint32_t adc_llops_regget(struct stm32_adc_dev_s *dev) { struct stm32_dev_s *priv = (struct stm32_dev_s *)dev; - return adc_getreg(priv, STM32L4_ADC_DR_OFFSET) & ADC_DR_MASK; + return adc_getreg(priv, STM32_ADC_DR_OFFSET) & ADC_DR_MASK; } /**************************************************************************** @@ -2544,15 +2544,15 @@ static int adc_regbufregister(struct stm32_adc_dev_s *dev, { struct stm32_dev_s *priv = (struct stm32_dev_s *)dev; - stm32l4_dmasetup(priv->dma, - priv->base + STM32L4_ADC_DR_OFFSET, + stm32_dmasetup(priv->dma, + priv->base + STM32_ADC_DR_OFFSET, (uint32_t)buffer, len, ADC_DMA_CONTROL_WORD); /* No DMA callback */ - stm32l4_dmastart(priv->dma, NULL, dev, false); + stm32_dmastart(priv->dma, NULL, dev, false); return OK; } @@ -2571,19 +2571,19 @@ static void adc_llops_dma_start(struct stm32_adc_dev_s *adc, if (dev->dma != NULL) { - stm32l4_dmastop(dev->dma); - stm32l4_dmafree(dev->dma); + stm32_dmastop(dev->dma); + stm32_dmafree(dev->dma); } - dev->dma = stm32l4_dmachannel(dev->dmachan); + dev->dma = stm32_dmachannel(dev->dmachan); - stm32l4_dmasetup(dev->dma, - dev->base + STM32L4_ADC_DR_OFFSET, + stm32_dmasetup(dev->dma, + dev->base + STM32_ADC_DR_OFFSET, (uint32_t)buffer, len, ADC_DMA_CONTROL_WORD); - stm32l4_dmastart(dev->dma, callback, dev, false); + stm32_dmastart(dev->dma, callback, dev, false); } /**************************************************************************** @@ -2598,8 +2598,8 @@ static void adc_llops_dma_stop(struct stm32_adc_dev_s *adc) if (dev->dma != NULL) { - stm32l4_dmastop(dev->dma); - stm32l4_dmafree(dev->dma); + stm32_dmastop(dev->dma); + stm32_dmafree(dev->dma); } } @@ -2639,7 +2639,7 @@ static uint32_t adc_llops_injget(struct stm32_adc_dev_s *dev, goto errout; } - regval = adc_getreg(priv, STM32L4_ADC_JDR1_OFFSET + (4 * chan)) & + regval = adc_getreg(priv, STM32_ADC_JDR1_OFFSET + (4 * chan)) & ADC_JDR_MASK; errout: @@ -2671,14 +2671,14 @@ static void adc_llops_dumpregs(struct stm32_adc_dev_s *dev) adc_dumpregs(priv); } -#endif /* CONFIG_STM32L4_ADC_LL_OPS */ +#endif /* CONFIG_STM32_ADC_LL_OPS */ /**************************************************************************** * Public Functions ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_adc_initialize + * Name: stm32_adc_initialize * * Description: * Initialize the ADC. @@ -2686,7 +2686,7 @@ static void adc_llops_dumpregs(struct stm32_adc_dev_s *dev) * The logic allow initialize ADC regular and injected channels. * * The number of injected channels for given ADC is selected from Kconfig - * with CONFIG_STM32L4_ADCx_INJECTED_CHAN definitions + * with CONFIG_STM32_ADCx_INJECTED_CHAN definitions * * The number of regular channels is obtained from the equation: * @@ -2710,9 +2710,9 @@ static void adc_llops_dumpregs(struct stm32_adc_dev_s *dev) * chanlist[channels] -> ADC_JSQR_ISQy * * where: - * y = CONFIG_STM32L4_ADCx_INJECTED_CHAN, and y > 0 + * y = CONFIG_STM32_ADCx_INJECTED_CHAN, and y > 0 * - * If CONFIG_STM32L4_ADCx_INJECTED_CHAN = 0, then all channels from + * If CONFIG_STM32_ADCx_INJECTED_CHAN = 0, then all channels from * chanlist are regular channels. * * Input Parameters: @@ -2725,7 +2725,7 @@ static void adc_llops_dumpregs(struct stm32_adc_dev_s *dev) * ****************************************************************************/ -struct adc_dev_s *stm32l4_adc_initialize(int intf, +struct adc_dev_s *stm32_adc_initialize(int intf, const uint8_t *chanlist, int cchannels) { @@ -2739,11 +2739,11 @@ struct adc_dev_s *stm32l4_adc_initialize(int intf, switch (intf) { -#ifdef CONFIG_STM32L4_ADC1 +#ifdef CONFIG_STM32_ADC1 case 1: { ainfo("ADC1 selected\n"); - cjchannels = CONFIG_STM32L4_ADC1_INJ_CHAN; + cjchannels = CONFIG_STM32_ADC1_INJ_CHAN; crchannels = cchannels - cjchannels; ainfo(" Reg. chan: %d Inj chan: %d\n", crchannels, cjchannels); # ifdef ADC_HAVE_INJECTED @@ -2758,11 +2758,11 @@ struct adc_dev_s *stm32l4_adc_initialize(int intf, break; #endif -#ifdef CONFIG_STM32L4_ADC2 +#ifdef CONFIG_STM32_ADC2 case 2: { ainfo("ADC2 selected\n"); - cjchannels = CONFIG_STM32L4_ADC2_INJ_CHAN; + cjchannels = CONFIG_STM32_ADC2_INJ_CHAN; crchannels = cchannels - cjchannels; ainfo(" Reg. chan: %d Inj chan: %d\n", crchannels, cjchannels); # ifdef ADC_HAVE_INJECTED @@ -2777,11 +2777,11 @@ struct adc_dev_s *stm32l4_adc_initialize(int intf, break; #endif -#ifdef CONFIG_STM32L4_ADC3 +#ifdef CONFIG_STM32_ADC3 case 3: { ainfo("ADC3 selected\n"); - cjchannels = CONFIG_STM32L4_ADC3_INJ_CHAN; + cjchannels = CONFIG_STM32_ADC3_INJ_CHAN; crchannels = cchannels - cjchannels; ainfo(" Reg. chan: %d Inj chan: %d\n", crchannels, cjchannels); # ifdef ADC_HAVE_INJECTED @@ -2805,10 +2805,10 @@ struct adc_dev_s *stm32l4_adc_initialize(int intf, priv = (struct stm32_dev_s *)dev->ad_priv; - DEBUGASSERT(crchannels <= CONFIG_STM32L4_ADC_MAX_SAMPLES); - if (crchannels > CONFIG_STM32L4_ADC_MAX_SAMPLES) + DEBUGASSERT(crchannels <= CONFIG_STM32_ADC_MAX_SAMPLES); + if (crchannels > CONFIG_STM32_ADC_MAX_SAMPLES) { - crchannels = CONFIG_STM32L4_ADC_MAX_SAMPLES; + crchannels = CONFIG_STM32_ADC_MAX_SAMPLES; } priv->cchannels = crchannels; @@ -2824,7 +2824,7 @@ struct adc_dev_s *stm32l4_adc_initialize(int intf, #endif -#ifndef CONFIG_STM32L4_ADC_NOIRQ +#ifndef CONFIG_STM32_ADC_NOIRQ priv->cb = NULL; #endif @@ -2839,5 +2839,5 @@ struct adc_dev_s *stm32l4_adc_initialize(int intf, return dev; } -#endif /* CONFIG_STM32L4_ADC1 || CONFIG_STM32L4_ADC2 || CONFIG_STM32L4_ADC3 */ +#endif /* CONFIG_STM32_ADC1 || CONFIG_STM32_ADC2 || CONFIG_STM32_ADC3 */ #endif /* CONFIG_ADC */ diff --git a/arch/arm/src/stm32l4/stm32l4_adc.h b/arch/arm/src/stm32l4/stm32l4_adc.h index b2f2c16b7f997..da39bab518e9e 100644 --- a/arch/arm/src/stm32l4/stm32l4_adc.h +++ b/arch/arm/src/stm32l4/stm32l4_adc.h @@ -40,100 +40,100 @@ /* Configuration ************************************************************/ /* Timer devices may be used for different purposes. One special purpose is - * to control periodic ADC sampling. If CONFIG_STM32L4_TIMn is defined then - * CONFIG_STM32L4_TIMn_ADC must also be defined to indicate that timer "n" is + * to control periodic ADC sampling. If CONFIG_STM32_TIMn is defined then + * CONFIG_STM32_TIMn_ADC must also be defined to indicate that timer "n" is * intended to be used for that purpose. Timers 1,2,3,6 and 15 may be used on * STM32L4X3, while STM32L4X6 adds support for timers 4 and 8 as well. */ -#ifndef CONFIG_STM32L4_TIM1 -# undef CONFIG_STM32L4_TIM1_ADC -# undef CONFIG_STM32L4_TIM1_ADC1 -# undef CONFIG_STM32L4_TIM1_ADC2 -# undef CONFIG_STM32L4_TIM1_ADC3 -#endif -#ifndef CONFIG_STM32L4_TIM2 -# undef CONFIG_STM32L4_TIM2_ADC -# undef CONFIG_STM32L4_TIM2_ADC1 -# undef CONFIG_STM32L4_TIM2_ADC2 -# undef CONFIG_STM32L4_TIM2_ADC3 -#endif -#ifndef CONFIG_STM32L4_TIM3 -# undef CONFIG_STM32L4_TIM3_ADC -# undef CONFIG_STM32L4_TIM3_ADC1 -# undef CONFIG_STM32L4_TIM3_ADC2 -# undef CONFIG_STM32L4_TIM3_ADC3 -#endif -#ifndef CONFIG_STM32L4_TIM4 -# undef CONFIG_STM32L4_TIM4_ADC -# undef CONFIG_STM32L4_TIM4_ADC1 -# undef CONFIG_STM32L4_TIM4_ADC2 -# undef CONFIG_STM32L4_TIM4_ADC3 -#endif -#ifndef CONFIG_STM32L4_TIM6 -# undef CONFIG_STM32L4_TIM6_ADC -# undef CONFIG_STM32L4_TIM6_ADC1 -# undef CONFIG_STM32L4_TIM6_ADC2 -# undef CONFIG_STM32L4_TIM6_ADC3 -#endif -#ifndef CONFIG_STM32L4_TIM8 -# undef CONFIG_STM32L4_TIM8_ADC -# undef CONFIG_STM32L4_TIM8_ADC1 -# undef CONFIG_STM32L4_TIM8_ADC2 -# undef CONFIG_STM32L4_TIM8_ADC3 -#endif -#ifndef CONFIG_STM32L4_TIM15 -# undef CONFIG_STM32L4_TIM15_ADC -# undef CONFIG_STM32L4_TIM15_ADC1 -# undef CONFIG_STM32L4_TIM15_ADC2 -# undef CONFIG_STM32L4_TIM15_ADC3 +#ifndef CONFIG_STM32_TIM1 +# undef CONFIG_STM32_TIM1_ADC +# undef CONFIG_STM32_TIM1_ADC1 +# undef CONFIG_STM32_TIM1_ADC2 +# undef CONFIG_STM32_TIM1_ADC3 +#endif +#ifndef CONFIG_STM32_TIM2 +# undef CONFIG_STM32_TIM2_ADC +# undef CONFIG_STM32_TIM2_ADC1 +# undef CONFIG_STM32_TIM2_ADC2 +# undef CONFIG_STM32_TIM2_ADC3 +#endif +#ifndef CONFIG_STM32_TIM3 +# undef CONFIG_STM32_TIM3_ADC +# undef CONFIG_STM32_TIM3_ADC1 +# undef CONFIG_STM32_TIM3_ADC2 +# undef CONFIG_STM32_TIM3_ADC3 +#endif +#ifndef CONFIG_STM32_TIM4 +# undef CONFIG_STM32_TIM4_ADC +# undef CONFIG_STM32_TIM4_ADC1 +# undef CONFIG_STM32_TIM4_ADC2 +# undef CONFIG_STM32_TIM4_ADC3 +#endif +#ifndef CONFIG_STM32_TIM6 +# undef CONFIG_STM32_TIM6_ADC +# undef CONFIG_STM32_TIM6_ADC1 +# undef CONFIG_STM32_TIM6_ADC2 +# undef CONFIG_STM32_TIM6_ADC3 +#endif +#ifndef CONFIG_STM32_TIM8 +# undef CONFIG_STM32_TIM8_ADC +# undef CONFIG_STM32_TIM8_ADC1 +# undef CONFIG_STM32_TIM8_ADC2 +# undef CONFIG_STM32_TIM8_ADC3 +#endif +#ifndef CONFIG_STM32_TIM15 +# undef CONFIG_STM32_TIM15_ADC +# undef CONFIG_STM32_TIM15_ADC1 +# undef CONFIG_STM32_TIM15_ADC2 +# undef CONFIG_STM32_TIM15_ADC3 #endif /* Up to 3 ADC interfaces are supported */ -#if STM32L4_NADC < 3 -# undef CONFIG_STM32L4_ADC3 +#if STM32_NADC < 3 +# undef CONFIG_STM32_ADC3 #endif -#if STM32L4_NADC < 2 -# undef CONFIG_STM32L4_ADC2 +#if STM32_NADC < 2 +# undef CONFIG_STM32_ADC2 #endif -#if STM32L4_NADC < 1 -# undef CONFIG_STM32L4_ADC1 +#if STM32_NADC < 1 +# undef CONFIG_STM32_ADC1 #endif -#if defined(CONFIG_STM32L4_ADC1) || defined(CONFIG_STM32L4_ADC2) || \ - defined(CONFIG_STM32L4_ADC3) +#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) || \ + defined(CONFIG_STM32_ADC3) /* ADC output to DFSDM support. Note that DFSDM and DMA are * mutually exclusive. */ #undef ADC_HAVE_DFSDM -#if defined(CONFIG_STM32L4_ADC1_OUTPUT_DFSDM) || \ - defined(CONFIG_STM32L4_ADC2_OUTPUT_DFSDM) || \ - defined(CONFIG_STM32L4_ADC3_OUTPUT_DFSDM) +#if defined(CONFIG_STM32_ADC1_OUTPUT_DFSDM) || \ + defined(CONFIG_STM32_ADC2_OUTPUT_DFSDM) || \ + defined(CONFIG_STM32_ADC3_OUTPUT_DFSDM) # define ADC_HAVE_DFSDM #endif -#if defined(CONFIG_STM32L4_ADC1_OUTPUT_DFSDM) +#if defined(CONFIG_STM32_ADC1_OUTPUT_DFSDM) # define ADC1_HAVE_DFSDM 1 -# undef CONFIG_STM32L4_ADC1_DMA +# undef CONFIG_STM32_ADC1_DMA #else # undef ADC1_HAVE_DFSDM #endif -#if defined(CONFIG_STM32L4_ADC2_OUTPUT_DFSDM) +#if defined(CONFIG_STM32_ADC2_OUTPUT_DFSDM) # define ADC2_HAVE_DFSDM 1 -# undef CONFIG_STM32L4_ADC2_DMA +# undef CONFIG_STM32_ADC2_DMA #else # undef ADC2_HAVE_DFSDM #endif -#if defined(CONFIG_STM32L4_ADC3_OUTPUT_DFSDM) +#if defined(CONFIG_STM32_ADC3_OUTPUT_DFSDM) # define ADC3_HAVE_DFSDM 1 -# undef CONFIG_STM32L4_ADC3_DMA +# undef CONFIG_STM32_ADC3_DMA #else # undef ADC3_HAVE_DFSDM #endif @@ -141,24 +141,24 @@ /* DMA support */ #undef ADC_HAVE_DMA -#if defined(CONFIG_STM32L4_ADC1_DMA) || defined(CONFIG_STM32L4_ADC2_DMA) || \ - defined(CONFIG_STM32L4_ADC3_DMA) +#if defined(CONFIG_STM32_ADC1_DMA) || defined(CONFIG_STM32_ADC2_DMA) || \ + defined(CONFIG_STM32_ADC3_DMA) # define ADC_HAVE_DMA 1 #endif -#ifdef CONFIG_STM32L4_ADC1_DMA +#ifdef CONFIG_STM32_ADC1_DMA # define ADC1_HAVE_DMA 1 #else # undef ADC1_HAVE_DMA #endif -#ifdef CONFIG_STM32L4_ADC2_DMA +#ifdef CONFIG_STM32_ADC2_DMA # define ADC2_HAVE_DMA 1 #else # undef ADC2_HAVE_DMA #endif -#ifdef CONFIG_STM32L4_ADC3_DMA +#ifdef CONFIG_STM32_ADC3_DMA # define ADC3_HAVE_DMA 1 #else # undef ADC3_HAVE_DMA @@ -166,9 +166,9 @@ /* Injected channels support */ -#if (defined(CONFIG_STM32L4_ADC1) && (CONFIG_STM32L4_ADC1_INJ_CHAN > 0)) || \ - (defined(CONFIG_STM32L4_ADC2) && (CONFIG_STM32L4_ADC2_INJ_CHAN > 0)) || \ - (defined(CONFIG_STM32L4_ADC3) && (CONFIG_STM32L4_ADC3_INJ_CHAN > 0)) +#if (defined(CONFIG_STM32_ADC1) && (CONFIG_STM32_ADC1_INJ_CHAN > 0)) || \ + (defined(CONFIG_STM32_ADC2) && (CONFIG_STM32_ADC2_INJ_CHAN > 0)) || \ + (defined(CONFIG_STM32_ADC3) && (CONFIG_STM32_ADC3_INJ_CHAN > 0)) # define ADC_HAVE_INJECTED #endif @@ -176,149 +176,149 @@ * information about the timer. */ -#if defined(CONFIG_STM32L4_TIM1_ADC1) +#if defined(CONFIG_STM32_TIM1_ADC1) # define ADC1_HAVE_TIMER 1 -# define ADC1_TIMER_BASE STM32L4_TIM1_BASE -# define ADC1_TIMER_PCLK_FREQUENCY STM32L4_APB2_TIM1_CLKIN -# define ADC1_TIMER_CHANNEL CONFIG_STM32L4_TIM1_ADC_CHAN -#elif defined(CONFIG_STM32L4_TIM2_ADC1) +# define ADC1_TIMER_BASE STM32_TIM1_BASE +# define ADC1_TIMER_PCLK_FREQUENCY STM32_APB2_TIM1_CLKIN +# define ADC1_TIMER_CHANNEL CONFIG_STM32_TIM1_ADC_CHAN +#elif defined(CONFIG_STM32_TIM2_ADC1) # define ADC1_HAVE_TIMER 1 -# define ADC1_TIMER_BASE STM32L4_TIM2_BASE -# define ADC1_TIMER_PCLK_FREQUENCY STM32L4_APB1_TIM2_CLKIN -# define ADC1_TIMER_CHANNEL CONFIG_STM32L4_TIM2_ADC_CHAN -#elif defined(CONFIG_STM32L4_TIM3_ADC1) +# define ADC1_TIMER_BASE STM32_TIM2_BASE +# define ADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM2_CLKIN +# define ADC1_TIMER_CHANNEL CONFIG_STM32_TIM2_ADC_CHAN +#elif defined(CONFIG_STM32_TIM3_ADC1) # define ADC1_HAVE_TIMER 1 -# define ADC1_TIMER_BASE STM32L4_TIM3_BASE -# define ADC1_TIMER_PCLK_FREQUENCY STM32L4_APB1_TIM3_CLKIN -# define ADC1_TIMER_CHANNEL CONFIG_STM32L4_TIM3_ADC_CHAN -#elif defined(CONFIG_STM32L4_TIM4_ADC1) +# define ADC1_TIMER_BASE STM32_TIM3_BASE +# define ADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM3_CLKIN +# define ADC1_TIMER_CHANNEL CONFIG_STM32_TIM3_ADC_CHAN +#elif defined(CONFIG_STM32_TIM4_ADC1) # define ADC1_HAVE_TIMER 1 -# define ADC1_TIMER_BASE STM32L4_TIM4_BASE -# define ADC1_TIMER_PCLK_FREQUENCY STM32L4_APB1_TIM4_CLKIN -# define ADC1_TIMER_CHANNEL CONFIG_STM32L4_TIM4_ADC_CHAN -#elif defined(CONFIG_STM32L4_TIM6_ADC1) +# define ADC1_TIMER_BASE STM32_TIM4_BASE +# define ADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM4_CLKIN +# define ADC1_TIMER_CHANNEL CONFIG_STM32_TIM4_ADC_CHAN +#elif defined(CONFIG_STM32_TIM6_ADC1) # define ADC1_HAVE_TIMER 1 -# define ADC1_TIMER_BASE STM32L4_TIM6_BASE -# define ADC1_TIMER_PCLK_FREQUENCY STM32L4_APB1_TIM6_CLKIN -# define ADC1_TIMER_CHANNEL CONFIG_STM32L4_TIM6_ADC_CHAN -#elif defined(CONFIG_STM32L4_TIM8_ADC1) +# define ADC1_TIMER_BASE STM32_TIM6_BASE +# define ADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM6_CLKIN +# define ADC1_TIMER_CHANNEL CONFIG_STM32_TIM6_ADC_CHAN +#elif defined(CONFIG_STM32_TIM8_ADC1) # define ADC1_HAVE_TIMER 1 -# define ADC1_TIMER_BASE STM32L4_TIM8_BASE -# define ADC1_TIMER_PCLK_FREQUENCY STM32L4_APB2_TIM8_CLKIN -# define ADC1_TIMER_CHANNEL CONFIG_STM32L4_TIM8_ADC_CHAN -#elif defined(CONFIG_STM32L4_TIM15_ADC1) +# define ADC1_TIMER_BASE STM32_TIM8_BASE +# define ADC1_TIMER_PCLK_FREQUENCY STM32_APB2_TIM8_CLKIN +# define ADC1_TIMER_CHANNEL CONFIG_STM32_TIM8_ADC_CHAN +#elif defined(CONFIG_STM32_TIM15_ADC1) # define ADC1_HAVE_TIMER 1 -# define ADC1_TIMER_BASE STM32L4_TIM15_BASE -# define ADC1_TIMER_PCLK_FREQUENCY STM32L4_APB2_TIM15_CLKIN -# define ADC1_TIMER_CHANNEL CONFIG_STM32L4_TIM15_ADC_CHAN +# define ADC1_TIMER_BASE STM32_TIM15_BASE +# define ADC1_TIMER_PCLK_FREQUENCY STM32_APB2_TIM15_CLKIN +# define ADC1_TIMER_CHANNEL CONFIG_STM32_TIM15_ADC_CHAN #else # undef ADC1_HAVE_TIMER #endif #ifdef ADC1_HAVE_TIMER -# ifndef CONFIG_STM32L4_ADC1_SAMPLE_FREQUENCY -# error "CONFIG_STM32L4_ADC1_SAMPLE_FREQUENCY not defined" +# ifndef CONFIG_STM32_ADC1_SAMPLE_FREQUENCY +# error "CONFIG_STM32_ADC1_SAMPLE_FREQUENCY not defined" # endif -# if ((CONFIG_STM32L4_ADC1_EXTTRIG == 0) && \ - (CONFIG_STM32L4_ADC1_JEXTTRIG == 0)) +# if ((CONFIG_STM32_ADC1_EXTTRIG == 0) && \ + (CONFIG_STM32_ADC1_JEXTTRIG == 0)) # error "ADC1 External trigger must be enabled" # endif #endif -#if defined(CONFIG_STM32L4_TIM1_ADC2) +#if defined(CONFIG_STM32_TIM1_ADC2) # define ADC2_HAVE_TIMER 1 -# define ADC2_TIMER_BASE STM32L4_TIM1_BASE -# define ADC2_TIMER_PCLK_FREQUENCY STM32L4_APB2_TIM1_CLKIN -# define ADC2_TIMER_CHANNEL CONFIG_STM32L4_TIM1_ADC_CHAN -#elif defined(CONFIG_STM32L4_TIM2_ADC2) +# define ADC2_TIMER_BASE STM32_TIM1_BASE +# define ADC2_TIMER_PCLK_FREQUENCY STM32_APB2_TIM1_CLKIN +# define ADC2_TIMER_CHANNEL CONFIG_STM32_TIM1_ADC_CHAN +#elif defined(CONFIG_STM32_TIM2_ADC2) # define ADC2_HAVE_TIMER 1 -# define ADC2_TIMER_BASE STM32L4_TIM2_BASE -# define ADC2_TIMER_PCLK_FREQUENCY STM32L4_APB1_TIM2_CLKIN -# define ADC2_TIMER_CHANNEL CONFIG_STM32L4_TIM2_ADC_CHAN -#elif defined(CONFIG_STM32L4_TIM3_ADC2) +# define ADC2_TIMER_BASE STM32_TIM2_BASE +# define ADC2_TIMER_PCLK_FREQUENCY STM32_APB1_TIM2_CLKIN +# define ADC2_TIMER_CHANNEL CONFIG_STM32_TIM2_ADC_CHAN +#elif defined(CONFIG_STM32_TIM3_ADC2) # define ADC2_HAVE_TIMER 1 -# define ADC2_TIMER_BASE STM32L4_TIM3_BASE -# define ADC2_TIMER_PCLK_FREQUENCY STM32L4_APB1_TIM3_CLKIN -# define ADC2_TIMER_CHANNEL CONFIG_STM32L4_TIM3_ADC_CHAN -#elif defined(CONFIG_STM32L4_TIM4_ADC2) +# define ADC2_TIMER_BASE STM32_TIM3_BASE +# define ADC2_TIMER_PCLK_FREQUENCY STM32_APB1_TIM3_CLKIN +# define ADC2_TIMER_CHANNEL CONFIG_STM32_TIM3_ADC_CHAN +#elif defined(CONFIG_STM32_TIM4_ADC2) # define ADC2_HAVE_TIMER 1 -# define ADC2_TIMER_BASE STM32L4_TIM4_BASE -# define ADC2_TIMER_PCLK_FREQUENCY STM32L4_APB1_TIM4_CLKIN -# define ADC2_TIMER_CHANNEL CONFIG_STM32L4_TIM4_ADC_CHAN -#elif defined(CONFIG_STM32L4_TIM6_ADC2) +# define ADC2_TIMER_BASE STM32_TIM4_BASE +# define ADC2_TIMER_PCLK_FREQUENCY STM32_APB1_TIM4_CLKIN +# define ADC2_TIMER_CHANNEL CONFIG_STM32_TIM4_ADC_CHAN +#elif defined(CONFIG_STM32_TIM6_ADC2) # define ADC2_HAVE_TIMER 1 -# define ADC2_TIMER_BASE STM32L4_TIM6_BASE -# define ADC2_TIMER_PCLK_FREQUENCY STM32L4_APB1_TIM6_CLKIN -# define ADC2_TIMER_CHANNEL CONFIG_STM32L4_TIM6_ADC_CHAN -#elif defined(CONFIG_STM32L4_TIM8_ADC2) +# define ADC2_TIMER_BASE STM32_TIM6_BASE +# define ADC2_TIMER_PCLK_FREQUENCY STM32_APB1_TIM6_CLKIN +# define ADC2_TIMER_CHANNEL CONFIG_STM32_TIM6_ADC_CHAN +#elif defined(CONFIG_STM32_TIM8_ADC2) # define ADC2_HAVE_TIMER 1 -# define ADC2_TIMER_BASE STM32L4_TIM8_BASE -# define ADC2_TIMER_PCLK_FREQUENCY STM32L4_APB2_TIM8_CLKIN -# define ADC2_TIMER_CHANNEL CONFIG_STM32L4_TIM8_ADC_CHAN -#elif defined(CONFIG_STM32L4_TIM15_ADC2) +# define ADC2_TIMER_BASE STM32_TIM8_BASE +# define ADC2_TIMER_PCLK_FREQUENCY STM32_APB2_TIM8_CLKIN +# define ADC2_TIMER_CHANNEL CONFIG_STM32_TIM8_ADC_CHAN +#elif defined(CONFIG_STM32_TIM15_ADC2) # define ADC2_HAVE_TIMER 1 -# define ADC2_TIMER_BASE STM32L4_TIM15_BASE -# define ADC2_TIMER_PCLK_FREQUENCY STM32L4_APB2_TIM15_CLKIN -# define ADC2_TIMER_CHANNEL CONFIG_STM32L4_TIM15_ADC_CHAN +# define ADC2_TIMER_BASE STM32_TIM15_BASE +# define ADC2_TIMER_PCLK_FREQUENCY STM32_APB2_TIM15_CLKIN +# define ADC2_TIMER_CHANNEL CONFIG_STM32_TIM15_ADC_CHAN #else # undef ADC2_HAVE_TIMER #endif #ifdef ADC2_HAVE_TIMER -# ifndef CONFIG_STM32L4_ADC2_SAMPLE_FREQUENCY -# error "CONFIG_STM32L4_ADC2_SAMPLE_FREQUENCY not defined" +# ifndef CONFIG_STM32_ADC2_SAMPLE_FREQUENCY +# error "CONFIG_STM32_ADC2_SAMPLE_FREQUENCY not defined" # endif -# if ((CONFIG_STM32L4_ADC2_EXTTRIG == 0) && \ - (CONFIG_STM32L4_ADC2_JEXTTRIG == 0)) +# if ((CONFIG_STM32_ADC2_EXTTRIG == 0) && \ + (CONFIG_STM32_ADC2_JEXTTRIG == 0)) # error "ADC2 External trigger must be enabled" # endif #endif -#if defined(CONFIG_STM32L4_TIM1_ADC3) +#if defined(CONFIG_STM32_TIM1_ADC3) # define ADC3_HAVE_TIMER 1 -# define ADC3_TIMER_BASE STM32L4_TIM1_BASE -# define ADC3_TIMER_PCLK_FREQUENCY STM32L4_APB2_TIM1_CLKIN -# define ADC3_TIMER_CHANNEL CONFIG_STM32L4_TIM1_ADC_CHAN -#elif defined(CONFIG_STM32L4_TIM2_ADC3) +# define ADC3_TIMER_BASE STM32_TIM1_BASE +# define ADC3_TIMER_PCLK_FREQUENCY STM32_APB2_TIM1_CLKIN +# define ADC3_TIMER_CHANNEL CONFIG_STM32_TIM1_ADC_CHAN +#elif defined(CONFIG_STM32_TIM2_ADC3) # define ADC3_HAVE_TIMER 1 -# define ADC3_TIMER_BASE STM32L4_TIM2_BASE -# define ADC3_TIMER_PCLK_FREQUENCY STM32L4_APB1_TIM2_CLKIN -# define ADC3_TIMER_CHANNEL CONFIG_STM32L4_TIM1_ADC_CHAN -#elif defined(CONFIG_STM32L4_TIM3_ADC3) +# define ADC3_TIMER_BASE STM32_TIM2_BASE +# define ADC3_TIMER_PCLK_FREQUENCY STM32_APB1_TIM2_CLKIN +# define ADC3_TIMER_CHANNEL CONFIG_STM32_TIM1_ADC_CHAN +#elif defined(CONFIG_STM32_TIM3_ADC3) # define ADC3_HAVE_TIMER 1 -# define ADC3_TIMER_BASE STM32L4_TIM3_BASE -# define ADC3_TIMER_PCLK_FREQUENCY STM32L4_APB1_TIM3_CLKIN -# define ADC3_TIMER_CHANNEL CONFIG_STM32L4_TIM3_ADC_CHAN -#elif defined(CONFIG_STM32L4_TIM4_ADC3) +# define ADC3_TIMER_BASE STM32_TIM3_BASE +# define ADC3_TIMER_PCLK_FREQUENCY STM32_APB1_TIM3_CLKIN +# define ADC3_TIMER_CHANNEL CONFIG_STM32_TIM3_ADC_CHAN +#elif defined(CONFIG_STM32_TIM4_ADC3) # define ADC3_HAVE_TIMER 1 -# define ADC3_TIMER_BASE STM32L4_TIM4_BASE -# define ADC3_TIMER_PCLK_FREQUENCY STM32L4_APB1_TIM4_CLKIN -# define ADC3_TIMER_CHANNEL CONFIG_STM32L4_TIM4_ADC_CHAN -#elif defined(CONFIG_STM32L4_TIM6_ADC3) +# define ADC3_TIMER_BASE STM32_TIM4_BASE +# define ADC3_TIMER_PCLK_FREQUENCY STM32_APB1_TIM4_CLKIN +# define ADC3_TIMER_CHANNEL CONFIG_STM32_TIM4_ADC_CHAN +#elif defined(CONFIG_STM32_TIM6_ADC3) # define ADC3_HAVE_TIMER 1 -# define ADC3_TIMER_BASE STM32L4_TIM6_BASE -# define ADC3_TIMER_PCLK_FREQUENCY STM32L4_APB1_TIM6_CLKIN -# define ADC3_TIMER_CHANNEL CONFIG_STM32L4_TIM6_ADC_CHAN -#elif defined(CONFIG_STM32L4_TIM8_ADC3) +# define ADC3_TIMER_BASE STM32_TIM6_BASE +# define ADC3_TIMER_PCLK_FREQUENCY STM32_APB1_TIM6_CLKIN +# define ADC3_TIMER_CHANNEL CONFIG_STM32_TIM6_ADC_CHAN +#elif defined(CONFIG_STM32_TIM8_ADC3) # define ADC3_HAVE_TIMER 1 -# define ADC3_TIMER_BASE STM32L4_TIM8_BASE -# define ADC3_TIMER_PCLK_FREQUENCY STM32L4_APB2_TIM8_CLKIN -# define ADC3_TIMER_CHANNEL CONFIG_STM32L4_TIM8_ADC_CHAN -#elif defined(CONFIG_STM32L4_TIM15_ADC3) +# define ADC3_TIMER_BASE STM32_TIM8_BASE +# define ADC3_TIMER_PCLK_FREQUENCY STM32_APB2_TIM8_CLKIN +# define ADC3_TIMER_CHANNEL CONFIG_STM32_TIM8_ADC_CHAN +#elif defined(CONFIG_STM32_TIM15_ADC3) # define ADC3_HAVE_TIMER 1 -# define ADC3_TIMER_BASE STM32L4_TIM15_BASE -# define ADC3_TIMER_PCLK_FREQUENCY STM32L4_APB2_TIM15_CLKIN -# define ADC3_TIMER_CHANNEL CONFIG_STM32L4_TIM15_ADC_CHAN +# define ADC3_TIMER_BASE STM32_TIM15_BASE +# define ADC3_TIMER_PCLK_FREQUENCY STM32_APB2_TIM15_CLKIN +# define ADC3_TIMER_CHANNEL CONFIG_STM32_TIM15_ADC_CHAN #else # undef ADC3_HAVE_TIMER #endif #ifdef ADC3_HAVE_TIMER -# ifndef CONFIG_STM32L4_ADC3_SAMPLE_FREQUENCY -# error "CONFIG_STM32L4_ADC3_SAMPLE_FREQUENCY not defined" +# ifndef CONFIG_STM32_ADC3_SAMPLE_FREQUENCY +# error "CONFIG_STM32_ADC3_SAMPLE_FREQUENCY not defined" # endif -# if ((CONFIG_STM32L4_ADC3_EXTTRIG == 0) && \ - (CONFIG_STM32L4_ADC3_JEXTTRIG == 0)) +# if ((CONFIG_STM32_ADC3_EXTTRIG == 0) && \ + (CONFIG_STM32_ADC3_JEXTTRIG == 0)) # error "ADC3 External trigger must be enabled" # endif #endif @@ -332,18 +332,18 @@ /* EXTSEL configuration *****************************************************/ -/* If external trigger is enabled, (CONFIG_STM32L4_ADC1_EXTTRIG > 0), +/* If external trigger is enabled, (CONFIG_STM32_ADC1_EXTTRIG > 0), * ADCx_EXTSEL_VALUE is set based on trigger polarity and event number. No * effort is made to check if the configuration is valid. */ -#ifdef CONFIG_STM32L4_ADC1_EXTTRIG -# if CONFIG_STM32L4_ADC1_EXTTRIG > 0 +#ifdef CONFIG_STM32_ADC1_EXTTRIG +# if CONFIG_STM32_ADC1_EXTTRIG > 0 # define ADC1_EXTCFG_VALUE \ - ADC_CFGR_EXTEN(CONFIG_STM32L4_ADC1_EXTTRIG) | \ - ADC_CFGR_EXTSEL(CONFIG_STM32L4_ADC1_EXTSEL) + ADC_CFGR_EXTEN(CONFIG_STM32_ADC1_EXTTRIG) | \ + ADC_CFGR_EXTSEL(CONFIG_STM32_ADC_L4_ADC1_EXTSEL) # endif -#endif /* CONFIG_STM32L4_ADC1_EXTTRIG */ +#endif /* CONFIG_STM32_ADC1_EXTTRIG */ #ifdef ADC1_EXTCFG_VALUE # define ADC1_HAVE_EXTCFG 1 @@ -351,13 +351,13 @@ # undef ADC1_HAVE_EXTCFG #endif -#ifdef CONFIG_STM32L4_ADC2_EXTTRIG -# if CONFIG_STM32L4_ADC2_EXTTRIG > 0 +#ifdef CONFIG_STM32_ADC2_EXTTRIG +# if CONFIG_STM32_ADC2_EXTTRIG > 0 # define ADC2_EXTCFG_VALUE \ - ADC_CFGR_EXTEN(CONFIG_STM32L4_ADC2_EXTTRIG) | \ - ADC_CFGR_EXTSEL(CONFIG_STM32L4_ADC2_EXTSEL) + ADC_CFGR_EXTEN(CONFIG_STM32_ADC2_EXTTRIG) | \ + ADC_CFGR_EXTSEL(CONFIG_STM32_ADC_L4_ADC2_EXTSEL) # endif -#endif /* CONFIG_STM32L4_ADC2_EXTTRIG */ +#endif /* CONFIG_STM32_ADC2_EXTTRIG */ #ifdef ADC2_EXTCFG_VALUE # define ADC2_HAVE_EXTCFG 1 @@ -365,13 +365,13 @@ # undef ADC2_HAVE_EXTCFG #endif -#ifdef CONFIG_STM32L4_ADC3_EXTTRIG -# if CONFIG_STM32L4_ADC3_EXTTRIG > 0 +#ifdef CONFIG_STM32_ADC3_EXTTRIG +# if CONFIG_STM32_ADC3_EXTTRIG > 0 # define ADC3_EXTCFG_VALUE \ - ADC_CFGR_EXTEN(CONFIG_STM32L4_ADC3_EXTTRIG) | \ - ADC_CFGR_EXTSEL(CONFIG_STM32L4_ADC3_EXTSEL) + ADC_CFGR_EXTEN(CONFIG_STM32_ADC3_EXTTRIG) | \ + ADC_CFGR_EXTSEL(CONFIG_STM32_ADC_L4_ADC3_EXTSEL) # endif -#endif /* CONFIG_STM32L4_ADC3_EXTTRIG */ +#endif /* CONFIG_STM32_ADC3_EXTTRIG */ #ifdef ADC3_EXTCFG_VALUE # define ADC3_HAVE_EXTCFG 1 @@ -386,37 +386,37 @@ /* JEXTSEL configuration ****************************************************/ -#ifdef CONFIG_STM32L4_ADC1_JEXTTRIG -# if CONFIG_STM32L4_ADC1_JEXTTRIG > 0 +#ifdef CONFIG_STM32_ADC1_JEXTTRIG +# if CONFIG_STM32_ADC1_JEXTTRIG > 0 # define ADC1_JEXTCFG_VALUE \ - ADC_JSQR_JEXTEN(CONFIG_STM32L4_ADC1_JEXTTRIG) | \ - ADC_JSQR_JEXTSEL(CONFIG_STM32L4_ADC1_JEXTSEL) + ADC_JSQR_JEXTEN(CONFIG_STM32_ADC1_JEXTTRIG) | \ + ADC_JSQR_JEXTSEL(CONFIG_STM32_ADC_L4_ADC1_JEXTSEL) # endif -#endif /* CONFIG_STM32L4_ADC1_JEXTTRIG */ +#endif /* CONFIG_STM32_ADC1_JEXTTRIG */ #ifdef ADC1_JEXTCFG_VALUE # define ADC1_HAVE_JEXTCFG 1 #endif -#ifdef CONFIG_STM32L4_ADC2_JEXTTRIG -# if CONFIG_STM32L4_ADC2_JEXTTRIG > 0 +#ifdef CONFIG_STM32_ADC2_JEXTTRIG +# if CONFIG_STM32_ADC2_JEXTTRIG > 0 # define ADC2_JEXTCFG_VALUE \ - ADC_JSQR_JEXTEN(CONFIG_STM32L4_ADC2_JEXTTRIG) | \ - ADC_JSQR_JEXTSEL(CONFIG_STM32L4_ADC2_JEXTSEL) + ADC_JSQR_JEXTEN(CONFIG_STM32_ADC2_JEXTTRIG) | \ + ADC_JSQR_JEXTSEL(CONFIG_STM32_ADC_L4_ADC2_JEXTSEL) # endif -#endif /* CONFIG_STM32L4_ADC2_JEXTTRIG */ +#endif /* CONFIG_STM32_ADC2_JEXTTRIG */ #ifdef ADC2_JEXTCFG_VALUE # define ADC2_HAVE_JEXTCFG 1 #endif -#ifdef CONFIG_STM32L4_ADC3_JEXTTRIG -# if CONFIG_STM32L4_ADC3_JEXTTRIG > 0 +#ifdef CONFIG_STM32_ADC3_JEXTTRIG +# if CONFIG_STM32_ADC3_JEXTTRIG > 0 # define ADC3_JEXTCFG_VALUE \ - ADC_JSQR_JEXTEN(CONFIG_STM32L4_ADC3_JEXTTRIG) | \ - ADC_JSQR_JEXTSEL(CONFIG_STM32L4_ADC3_JEXTSEL) + ADC_JSQR_JEXTEN(CONFIG_STM32_ADC3_JEXTTRIG) | \ + ADC_JSQR_JEXTSEL(CONFIG_STM32_ADC_L4_ADC3_JEXTSEL) # endif -#endif /* CONFIG_STM32L4_ADC3_JEXTTRIG */ +#endif /* CONFIG_STM32_ADC3_JEXTTRIG */ #ifdef ADC3_JEXTCFG_VALUE # define ADC3_HAVE_JEXTCFG 1 @@ -483,19 +483,19 @@ /* IOCTL Commands *********************************************************** * - * Cmd: ANIOC_STM32L4_TRIGGER_REG Arg: - * Cmd: ANIOC_STM32L4_TRIGGER_INJ Arg: + * Cmd: ANIOC_STM32_TRIGGER_REG Arg: + * Cmd: ANIOC_STM32_TRIGGER_INJ Arg: * */ -#define ANIOC_STM32L4_TRIGGER_REG _ANIOC(AN_STM32L4_FIRST + 0) -#define ANIOC_STM32L4_TRIGGER_INJ _ANIOC(AN_STM32L4_FIRST + 1) +#define ANIOC_STM32_TRIGGER_REG _ANIOC(AN_STM32_FIRST + 0) +#define ANIOC_STM32_TRIGGER_INJ _ANIOC(AN_STM32_FIRST + 1) /**************************************************************************** * Public Types ****************************************************************************/ -#ifdef CONFIG_STM32L4_ADC_LL_OPS +#ifdef CONFIG_STM32_ADC_LL_OPS /* This structure provides the publicly visible representation of the * "lower-half" ADC driver structure. @@ -584,7 +584,7 @@ struct stm32_adc_ops_s void (*dump_regs)(struct stm32_adc_dev_s *dev); }; -#endif /* CONFIG_STM32L4_ADC_LL_OPS */ +#endif /* CONFIG_STM32_ADC_LL_OPS */ /**************************************************************************** * Public Function Prototypes @@ -600,7 +600,7 @@ extern "C" #endif /**************************************************************************** - * Name: stm32l4_adc_initialize + * Name: stm32_adc_initialize * * Description: * Initialize the ADC. @@ -616,7 +616,7 @@ extern "C" ****************************************************************************/ struct adc_dev_s; -struct adc_dev_s *stm32l4_adc_initialize(int intf, +struct adc_dev_s *stm32_adc_initialize(int intf, const uint8_t *chanlist, int nchannels); #undef EXTERN @@ -625,5 +625,5 @@ struct adc_dev_s *stm32l4_adc_initialize(int intf, #endif #endif /* __ASSEMBLY__ */ -#endif /* CONFIG_STM32L4_ADC1 || CONFIG_STM32L4_ADC2 || CONFIG_STM32L4_ADC3 */ +#endif /* CONFIG_STM32_ADC1 || CONFIG_STM32_ADC2 || CONFIG_STM32_ADC3 */ #endif /* __ARCH_ARM_SRC_STM32L4_STM32L4_ADC_H */ \ No newline at end of file diff --git a/arch/arm/src/stm32l4/stm32l4_allocateheap.c b/arch/arm/src/stm32l4/stm32l4_allocateheap.c index 1edbe3d122a38..d05e804dff984 100644 --- a/arch/arm/src/stm32l4/stm32l4_allocateheap.c +++ b/arch/arm/src/stm32l4/stm32l4_allocateheap.c @@ -60,8 +60,8 @@ * FSMC. In order to use FSMC SRAM, the following additional things need to * be present in the NuttX configuration file: * - * CONFIG_STM32L4_FSMC=y : Enables the FSMC - * CONFIG_STM32L4_FSMC_SRAM=y : Indicates that SRAM is available via the + * CONFIG_STM32_FSMC=y : Enables the FSMC + * CONFIG_STM32_FSMC_SRAM=y : Indicates that SRAM is available via the * FSMC (as opposed to an LCD or FLASH). * CONFIG_HEAP2_BASE : The base address of the SRAM in the FSMC * address space @@ -71,8 +71,8 @@ * include the additional regions. */ -#ifndef CONFIG_STM32L4_FSMC -# undef CONFIG_STM32L4_FSMC_SRAM +#ifndef CONFIG_STM32_FSMC +# undef CONFIG_STM32_FSMC_SRAM #endif /* STM32L4[7,8]6xx have 128 Kib in two banks, both accessible to DMA: @@ -96,19 +96,19 @@ /* Set the range of system SRAM */ -#define SRAM1_START STM32L4_SRAM_BASE -#define SRAM1_END (SRAM1_START + STM32L4_SRAM1_SIZE) +#define SRAM1_START STM32_SRAM_BASE +#define SRAM1_END (SRAM1_START + STM32_SRAM1_SIZE) /* Set the range of SRAM2 as well, requires a second memory region */ -#define SRAM2_START STM32L4_SRAM2_BASE -#define SRAM2_END (SRAM2_START + STM32L4_SRAM2_SIZE) +#define SRAM2_START STM32_SRAM2_BASE +#define SRAM2_END (SRAM2_START + STM32_SRAM2_SIZE) /* Set the range of SRAM3, requiring a third memory region */ -#ifdef STM32L4_SRAM3_SIZE -# define SRAM3_START STM32L4_SRAM3_BASE -# define SRAM3_END (SRAM3_START + STM32L4_SRAM3_SIZE) +#ifdef STM32_SRAM3_SIZE +# define SRAM3_START STM32_SRAM3_BASE +# define SRAM3_END (SRAM3_START + STM32_SRAM3_SIZE) #endif /* Some sanity checking. If multiple memory regions are defined, verify @@ -116,15 +116,15 @@ * that we have been asked to add to the heap. */ -#if CONFIG_MM_REGIONS < defined(CONFIG_STM32L4_SRAM2_HEAP) + \ - defined(CONFIG_STM32L4_SRAM3_HEAP) + \ - defined(CONFIG_STM32L4_FSMC_SRAM_HEAP) + 1 +#if CONFIG_MM_REGIONS < defined(CONFIG_STM32_SRAM2_HEAP) + \ + defined(CONFIG_STM32_SRAM3_HEAP) + \ + defined(CONFIG_STM32_FSMC_SRAM_HEAP) + 1 # error "You need more memory manager regions to support selected heap components" #endif -#if CONFIG_MM_REGIONS > defined(CONFIG_STM32L4_SRAM2_HEAP) + \ - defined(CONFIG_STM32L4_SRAM3_HEAP) + \ - defined(CONFIG_STM32L4_FSMC_SRAM_HEAP) + 1 +#if CONFIG_MM_REGIONS > defined(CONFIG_STM32_SRAM2_HEAP) + \ + defined(CONFIG_STM32_SRAM3_HEAP) + \ + defined(CONFIG_STM32_FSMC_SRAM_HEAP) + 1 # warning "CONFIG_MM_REGIONS large enough but I do not know what some of the region(s) are" #endif @@ -133,10 +133,10 @@ * configuration (as CONFIG_HEAP2_BASE and CONFIG_HEAP2_SIZE). */ -#ifdef CONFIG_STM32L4_FSMC_SRAM +#ifdef CONFIG_STM32_FSMC_SRAM # if !defined(CONFIG_HEAP2_BASE) || !defined(CONFIG_HEAP2_SIZE) # error "CONFIG_HEAP2_BASE and CONFIG_HEAP2_SIZE must be provided" -# undef CONFIG_STM32L4_FSMC_SRAM +# undef CONFIG_STM32_FSMC_SRAM # endif #endif @@ -241,7 +241,7 @@ void up_allocate_heap(void **heap_start, size_t *heap_size) /* Allow user-mode access to the user heap memory */ - stm32l4_mpu_uheap((uintptr_t)ubase, usize); + stm32_mpu_uheap((uintptr_t)ubase, usize); #else /* Return the heap settings */ @@ -313,13 +313,13 @@ void up_allocate_kheap(void **heap_start, size_t *heap_size) #if CONFIG_MM_REGIONS > 1 void arm_addregion(void) { -#ifdef CONFIG_STM32L4_SRAM2_HEAP +#ifdef CONFIG_STM32_SRAM2_HEAP #if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP) /* Allow user-mode access to the SRAM2 heap */ - stm32l4_mpu_uheap((uintptr_t)SRAM2_START, SRAM2_END - SRAM2_START); + stm32_mpu_uheap((uintptr_t)SRAM2_START, SRAM2_END - SRAM2_START); #endif /* Colorize the heap for debug */ @@ -332,13 +332,13 @@ void arm_addregion(void) #endif /* SRAM2 */ -#ifdef CONFIG_STM32L4_SRAM3_HEAP +#ifdef CONFIG_STM32_SRAM3_HEAP #if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP) /* Allow user-mode access to the SRAM3 heap */ - stm32l4_mpu_uheap((uintptr_t)SRAM3_START, SRAM3_END - SRAM3_START); + stm32_mpu_uheap((uintptr_t)SRAM3_START, SRAM3_END - SRAM3_START); #endif @@ -352,12 +352,12 @@ void arm_addregion(void) #endif /* SRAM3 */ -#ifdef CONFIG_STM32L4_FSMC_SRAM_HEAP +#ifdef CONFIG_STM32_FSMC_SRAM_HEAP #if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP) /* Allow user-mode access to the FSMC SRAM user heap memory */ - stm32l4_mpu_uheap((uintptr_t)CONFIG_HEAP2_BASE, CONFIG_HEAP2_SIZE); + stm32_mpu_uheap((uintptr_t)CONFIG_HEAP2_BASE, CONFIG_HEAP2_SIZE); #endif diff --git a/arch/arm/src/stm32l4/stm32l4_can.c b/arch/arm/src/stm32l4/stm32l4_can.c index 71e397a63254b..9d6231f4f1f13 100644 --- a/arch/arm/src/stm32l4/stm32l4_can.c +++ b/arch/arm/src/stm32l4/stm32l4_can.c @@ -41,10 +41,10 @@ #include "arm_internal.h" #include "chip.h" -#include "stm32l4.h" +#include "stm32.h" #include "stm32l4_can.h" -#if defined(CONFIG_CAN) && defined(CONFIG_STM32L4_CAN1) +#if defined(CONFIG_CAN) && defined(CONFIG_STM32_CAN1) /**************************************************************************** * Pre-processor Definitions @@ -62,17 +62,17 @@ /* Bit timing ***************************************************************/ -#define CAN_BIT_QUANTA (CONFIG_STM32L4_CAN_TSEG1 + CONFIG_STM32L4_CAN_TSEG2 + 1) +#define CAN_BIT_QUANTA (CONFIG_STM32_CAN_TSEG1 + CONFIG_STM32_CAN_TSEG2 + 1) #ifndef CONFIG_DEBUG_CAN_INFO -# undef CONFIG_STM32L4_CAN_REGDEBUG +# undef CONFIG_STM32_CAN_REGDEBUG #endif /**************************************************************************** * Private Types ****************************************************************************/ -struct stm32l4_can_s +struct stm32_can_s { uint8_t port; /* CAN port number (1 or 2) */ uint8_t canrx[2]; /* CAN RX FIFO 0/1 IRQ number */ @@ -89,20 +89,20 @@ struct stm32l4_can_s /* CAN Register access */ -static uint32_t stm32l4can_getreg(struct stm32l4_can_s *priv, +static uint32_t stm32l4can_getreg(struct stm32_can_s *priv, int offset); -static uint32_t stm32l4can_getfreg(struct stm32l4_can_s *priv, +static uint32_t stm32l4can_getfreg(struct stm32_can_s *priv, int offset); -static void stm32l4can_putreg(struct stm32l4_can_s *priv, int offset, +static void stm32l4can_putreg(struct stm32_can_s *priv, int offset, uint32_t value); -static void stm32l4can_putfreg(struct stm32l4_can_s *priv, int offset, +static void stm32l4can_putfreg(struct stm32_can_s *priv, int offset, uint32_t value); -#ifdef CONFIG_STM32L4_CAN_REGDEBUG -static void stm32l4can_dumpctrlregs(struct stm32l4_can_s *priv, +#ifdef CONFIG_STM32_CAN_REGDEBUG +static void stm32l4can_dumpctrlregs(struct stm32_can_s *priv, const char *msg); -static void stm32l4can_dumpmbregs(struct stm32l4_can_s *priv, +static void stm32l4can_dumpmbregs(struct stm32_can_s *priv, const char *msg); -static void stm32l4can_dumpfiltregs(struct stm32l4_can_s *priv, +static void stm32l4can_dumpfiltregs(struct stm32_can_s *priv, const char *msg); #else # define stm32l4can_dumpctrlregs(priv,msg) @@ -113,14 +113,14 @@ static void stm32l4can_dumpfiltregs(struct stm32l4_can_s *priv, /* Filtering (todo) */ #ifdef CONFIG_CAN_EXTID -static int stm32l4can_addextfilter(struct stm32l4_can_s *priv, +static int stm32l4can_addextfilter(struct stm32_can_s *priv, struct canioc_extfilter_s *arg); -static int stm32l4can_delextfilter(struct stm32l4_can_s *priv, +static int stm32l4can_delextfilter(struct stm32_can_s *priv, int arg); #endif -static int stm32l4can_addstdfilter(struct stm32l4_can_s *priv, +static int stm32l4can_addstdfilter(struct stm32_can_s *priv, struct canioc_stdfilter_s *arg); -static int stm32l4can_delstdfilter(struct stm32l4_can_s *priv, +static int stm32l4can_delstdfilter(struct stm32_can_s *priv, int arg); /* CAN driver methods */ @@ -151,11 +151,11 @@ static int stm32l4can_txinterrupt(int irq, void *context, /* Initialization */ -static int stm32l4can_enterinitmode(struct stm32l4_can_s *priv); -static int stm32l4can_exitinitmode(struct stm32l4_can_s *priv); -static int stm32l4can_bittiming(struct stm32l4_can_s *priv); -static int stm32l4can_cellinit(struct stm32l4_can_s *priv); -static int stm32l4can_filterinit(struct stm32l4_can_s *priv); +static int stm32l4can_enterinitmode(struct stm32_can_s *priv); +static int stm32l4can_exitinitmode(struct stm32_can_s *priv); +static int stm32l4can_bittiming(struct stm32_can_s *priv); +static int stm32l4can_cellinit(struct stm32_can_s *priv); +static int stm32l4can_filterinit(struct stm32_can_s *priv); /**************************************************************************** * Private Data @@ -175,20 +175,20 @@ static const struct can_ops_s g_canops = .co_txempty = stm32l4can_txempty, }; -#ifdef CONFIG_STM32L4_CAN1 -static struct stm32l4_can_s g_can1priv = +#ifdef CONFIG_STM32_CAN1 +static struct stm32_can_s g_can1priv = { .port = 1, .canrx = { - STM32L4_IRQ_CAN1RX0, - STM32L4_IRQ_CAN1RX1, + STM32_IRQ_CAN1RX0, + STM32_IRQ_CAN1RX1, }, - .cantx = STM32L4_IRQ_CAN1TX, + .cantx = STM32_IRQ_CAN1TX, .filter = 0, - .base = STM32L4_CAN1_BASE, - .fbase = STM32L4_CAN1_BASE, - .baud = CONFIG_STM32L4_CAN1_BAUD, + .base = STM32_CAN1_BASE, + .fbase = STM32_CAN1_BASE, + .baud = CONFIG_STM32_CAN1_BAUD, }; static struct can_dev_s g_can1dev = @@ -217,7 +217,7 @@ static struct can_dev_s g_can1dev = * ****************************************************************************/ -#ifdef CONFIG_STM32L4_CAN_REGDEBUG +#ifdef CONFIG_STM32_CAN_REGDEBUG static uint32_t stm32l4can_vgetreg(uint32_t addr) { static uint32_t prevaddr = 0; @@ -271,24 +271,24 @@ static uint32_t stm32l4can_vgetreg(uint32_t addr) return val; } -static uint32_t stm32l4can_getreg(struct stm32l4_can_s *priv, int offset) +static uint32_t stm32l4can_getreg(struct stm32_can_s *priv, int offset) { return stm32l4can_vgetreg(priv->base + offset); } -static uint32_t stm32l4can_getfreg(struct stm32l4_can_s *priv, +static uint32_t stm32l4can_getfreg(struct stm32_can_s *priv, int offset) { return stm32l4can_vgetreg(priv->fbase + offset); } #else -static uint32_t stm32l4can_getreg(struct stm32l4_can_s *priv, int offset) +static uint32_t stm32l4can_getreg(struct stm32_can_s *priv, int offset) { return getreg32(priv->base + offset); } -static uint32_t stm32l4can_getfreg(struct stm32l4_can_s *priv, +static uint32_t stm32l4can_getfreg(struct stm32_can_s *priv, int offset) { return getreg32(priv->fbase + offset); @@ -313,7 +313,7 @@ static uint32_t stm32l4can_getfreg(struct stm32l4_can_s *priv, * ****************************************************************************/ -#ifdef CONFIG_STM32L4_CAN_REGDEBUG +#ifdef CONFIG_STM32_CAN_REGDEBUG static void stm32l4can_vputreg(uint32_t addr, uint32_t value) { /* Show the register value being written */ @@ -325,26 +325,26 @@ static void stm32l4can_vputreg(uint32_t addr, uint32_t value) putreg32(value, addr); } -static void stm32l4can_putreg(struct stm32l4_can_s *priv, int offset, +static void stm32l4can_putreg(struct stm32_can_s *priv, int offset, uint32_t value) { stm32l4can_vputreg(priv->base + offset, value); } -static void stm32l4can_putfreg(struct stm32l4_can_s *priv, int offset, +static void stm32l4can_putfreg(struct stm32_can_s *priv, int offset, uint32_t value) { stm32l4can_vputreg(priv->fbase + offset, value); } #else -static void stm32l4can_putreg(struct stm32l4_can_s *priv, int offset, +static void stm32l4can_putreg(struct stm32_can_s *priv, int offset, uint32_t value) { putreg32(value, priv->base + offset); } -static void stm32l4can_putfreg(struct stm32l4_can_s *priv, int offset, +static void stm32l4can_putfreg(struct stm32_can_s *priv, int offset, uint32_t value) { putreg32(value, priv->fbase + offset); @@ -365,8 +365,8 @@ static void stm32l4can_putfreg(struct stm32l4_can_s *priv, int offset, * ****************************************************************************/ -#ifdef CONFIG_STM32L4_CAN_REGDEBUG -static void stm32l4can_dumpctrlregs(struct stm32l4_can_s *priv, +#ifdef CONFIG_STM32_CAN_REGDEBUG +static void stm32l4can_dumpctrlregs(struct stm32_can_s *priv, const char *msg) { if (msg) @@ -381,18 +381,18 @@ static void stm32l4can_dumpctrlregs(struct stm32l4_can_s *priv, /* CAN control and status registers */ caninfo(" MCR: %08" PRIx32 " MSR: %08" PRIx32 " TSR: %08" PRIx32 "\n", - getreg32(priv->base + STM32L4_CAN_MCR_OFFSET), - getreg32(priv->base + STM32L4_CAN_MSR_OFFSET), - getreg32(priv->base + STM32L4_CAN_TSR_OFFSET)); + getreg32(priv->base + STM32_CAN_MCR_OFFSET), + getreg32(priv->base + STM32_CAN_MSR_OFFSET), + getreg32(priv->base + STM32_CAN_TSR_OFFSET)); caninfo(" RF0R: %08" PRIx32 " RF1R: %08" PRIx32 "\n", - getreg32(priv->base + STM32L4_CAN_RF0R_OFFSET), - getreg32(priv->base + STM32L4_CAN_RF1R_OFFSET)); + getreg32(priv->base + STM32_CAN_RF0R_OFFSET), + getreg32(priv->base + STM32_CAN_RF1R_OFFSET)); caninfo(" IER: %08" PRIx32 " ESR: %08" PRIx32 " BTR: %08" PRIx32 "\n", - getreg32(priv->base + STM32L4_CAN_IER_OFFSET), - getreg32(priv->base + STM32L4_CAN_ESR_OFFSET), - getreg32(priv->base + STM32L4_CAN_BTR_OFFSET)); + getreg32(priv->base + STM32_CAN_IER_OFFSET), + getreg32(priv->base + STM32_CAN_ESR_OFFSET), + getreg32(priv->base + STM32_CAN_BTR_OFFSET)); } #endif @@ -410,8 +410,8 @@ static void stm32l4can_dumpctrlregs(struct stm32l4_can_s *priv, * ****************************************************************************/ -#ifdef CONFIG_STM32L4_CAN_REGDEBUG -static void stm32l4can_dumpmbregs(struct stm32l4_can_s *priv, +#ifdef CONFIG_STM32_CAN_REGDEBUG +static void stm32l4can_dumpmbregs(struct stm32_can_s *priv, const char *msg) { if (msg) @@ -427,38 +427,38 @@ static void stm32l4can_dumpmbregs(struct stm32l4_can_s *priv, caninfo(" TI0R: %08" PRIx32 " TDT0R: %08" PRIx32 " TDL0R: %08" PRIx32 " TDH0R: %08" PRIx32 "\n", - getreg32(priv->base + STM32L4_CAN_TI0R_OFFSET), - getreg32(priv->base + STM32L4_CAN_TDT0R_OFFSET), - getreg32(priv->base + STM32L4_CAN_TDL0R_OFFSET), - getreg32(priv->base + STM32L4_CAN_TDH0R_OFFSET)); + getreg32(priv->base + STM32_CAN_TI0R_OFFSET), + getreg32(priv->base + STM32_CAN_TDT0R_OFFSET), + getreg32(priv->base + STM32_CAN_TDL0R_OFFSET), + getreg32(priv->base + STM32_CAN_TDH0R_OFFSET)); caninfo(" TI1R: %08" PRIx32 " TDT1R: %08" PRIx32 " TDL1R: %08" PRIx32 " TDH1R: %08" PRIx32 "\n", - getreg32(priv->base + STM32L4_CAN_TI1R_OFFSET), - getreg32(priv->base + STM32L4_CAN_TDT1R_OFFSET), - getreg32(priv->base + STM32L4_CAN_TDL1R_OFFSET), - getreg32(priv->base + STM32L4_CAN_TDH1R_OFFSET)); + getreg32(priv->base + STM32_CAN_TI1R_OFFSET), + getreg32(priv->base + STM32_CAN_TDT1R_OFFSET), + getreg32(priv->base + STM32_CAN_TDL1R_OFFSET), + getreg32(priv->base + STM32_CAN_TDH1R_OFFSET)); caninfo(" TI2R: %08" PRIx32 " TDT2R: %08" PRIx32 " TDL2R: %08" PRIx32 " TDH2R: %08" PRIx32 "\n", - getreg32(priv->base + STM32L4_CAN_TI2R_OFFSET), - getreg32(priv->base + STM32L4_CAN_TDT2R_OFFSET), - getreg32(priv->base + STM32L4_CAN_TDL2R_OFFSET), - getreg32(priv->base + STM32L4_CAN_TDH2R_OFFSET)); + getreg32(priv->base + STM32_CAN_TI2R_OFFSET), + getreg32(priv->base + STM32_CAN_TDT2R_OFFSET), + getreg32(priv->base + STM32_CAN_TDL2R_OFFSET), + getreg32(priv->base + STM32_CAN_TDH2R_OFFSET)); caninfo(" RI0R: %08" PRIx32 " RDT0R: %08" PRIx32 " RDL0R: %08" PRIx32 " RDH0R: %08" PRIx32 "\n", - getreg32(priv->base + STM32L4_CAN_RI0R_OFFSET), - getreg32(priv->base + STM32L4_CAN_RDT0R_OFFSET), - getreg32(priv->base + STM32L4_CAN_RDL0R_OFFSET), - getreg32(priv->base + STM32L4_CAN_RDH0R_OFFSET)); + getreg32(priv->base + STM32_CAN_RI0R_OFFSET), + getreg32(priv->base + STM32_CAN_RDT0R_OFFSET), + getreg32(priv->base + STM32_CAN_RDL0R_OFFSET), + getreg32(priv->base + STM32_CAN_RDH0R_OFFSET)); caninfo(" RI1R: %08" PRIx32 " RDT1R: %08" PRIx32 " RDL1R: %08" PRIx32 " RDH1R: %08" PRIx32 "\n", - getreg32(priv->base + STM32L4_CAN_RI1R_OFFSET), - getreg32(priv->base + STM32L4_CAN_RDT1R_OFFSET), - getreg32(priv->base + STM32L4_CAN_RDL1R_OFFSET), - getreg32(priv->base + STM32L4_CAN_RDH1R_OFFSET)); + getreg32(priv->base + STM32_CAN_RI1R_OFFSET), + getreg32(priv->base + STM32_CAN_RDT1R_OFFSET), + getreg32(priv->base + STM32_CAN_RDL1R_OFFSET), + getreg32(priv->base + STM32_CAN_RDH1R_OFFSET)); } #endif @@ -476,8 +476,8 @@ static void stm32l4can_dumpmbregs(struct stm32l4_can_s *priv, * ****************************************************************************/ -#ifdef CONFIG_STM32L4_CAN_REGDEBUG -static void stm32l4can_dumpfiltregs(struct stm32l4_can_s *priv, +#ifdef CONFIG_STM32_CAN_REGDEBUG +static void stm32l4can_dumpfiltregs(struct stm32_can_s *priv, const char *msg) { int i; @@ -494,17 +494,17 @@ static void stm32l4can_dumpfiltregs(struct stm32l4_can_s *priv, caninfo(" FMR: %08" PRIx32 " FM1R: %08" PRIx32 " FS1R: %08" PRIx32 " FFA1R: %08" PRIx32 " FA1R: %08" PRIx32 "\n", - getreg32(priv->base + STM32L4_CAN_FMR_OFFSET), - getreg32(priv->base + STM32L4_CAN_FM1R_OFFSET), - getreg32(priv->base + STM32L4_CAN_FS1R_OFFSET), - getreg32(priv->base + STM32L4_CAN_FFA1R_OFFSET), - getreg32(priv->base + STM32L4_CAN_FA1R_OFFSET)); + getreg32(priv->base + STM32_CAN_FMR_OFFSET), + getreg32(priv->base + STM32_CAN_FM1R_OFFSET), + getreg32(priv->base + STM32_CAN_FS1R_OFFSET), + getreg32(priv->base + STM32_CAN_FFA1R_OFFSET), + getreg32(priv->base + STM32_CAN_FA1R_OFFSET)); for (i = 0; i < CAN_NFILTERS; i++) { caninfo(" F%dR1: %08" PRIx32 " F%dR2: %08" PRIx32 "\n", - i, getreg32(priv->base + STM32L4_CAN_FIR_OFFSET(i, 1)), - i, getreg32(priv->base + STM32L4_CAN_FIR_OFFSET(i, 2))); + i, getreg32(priv->base + STM32_CAN_FIR_OFFSET(i, 1)), + i, getreg32(priv->base + STM32_CAN_FIR_OFFSET(i, 2))); } } #endif @@ -526,7 +526,7 @@ static void stm32l4can_dumpfiltregs(struct stm32l4_can_s *priv, static void stm32l4can_reset(struct can_dev_s *dev) { - struct stm32l4_can_s *priv = dev->cd_priv; + struct stm32_can_s *priv = dev->cd_priv; uint32_t regval; uint32_t regbit = 0; irqstate_t flags; @@ -535,7 +535,7 @@ static void stm32l4can_reset(struct can_dev_s *dev) /* Get the bits in the AHB1RSTR1 register needed to reset this CAN device */ -#ifdef CONFIG_STM32L4_CAN1 +#ifdef CONFIG_STM32_CAN1 if (priv->port == 1) { regbit = RCC_APB1RSTR1_CAN1RST; @@ -555,12 +555,12 @@ static void stm32l4can_reset(struct can_dev_s *dev) /* Reset the CAN */ - regval = getreg32(STM32L4_RCC_APB1RSTR1); + regval = getreg32(STM32_RCC_APB1RSTR1); regval |= regbit; - putreg32(regval, STM32L4_RCC_APB1RSTR1); + putreg32(regval, STM32_RCC_APB1RSTR1); regval &= ~regbit; - putreg32(regval, STM32L4_RCC_APB1RSTR1); + putreg32(regval, STM32_RCC_APB1RSTR1); leave_critical_section(flags); } @@ -583,7 +583,7 @@ static void stm32l4can_reset(struct can_dev_s *dev) static int stm32l4can_setup(struct can_dev_s *dev) { - struct stm32l4_can_s *priv = dev->cd_priv; + struct stm32_can_s *priv = dev->cd_priv; int ret; caninfo("CAN%d RX0 irq: %d RX1 irq: %d TX irq: %d\n", @@ -670,7 +670,7 @@ static int stm32l4can_setup(struct can_dev_s *dev) static void stm32l4can_shutdown(struct can_dev_s *dev) { - struct stm32l4_can_s *priv = dev->cd_priv; + struct stm32_can_s *priv = dev->cd_priv; caninfo("CAN%d\n", priv->port); @@ -707,14 +707,14 @@ static void stm32l4can_shutdown(struct can_dev_s *dev) static void stm32l4can_rxint(struct can_dev_s *dev, bool enable) { - struct stm32l4_can_s *priv = dev->cd_priv; + struct stm32_can_s *priv = dev->cd_priv; uint32_t regval; caninfo("CAN%d enable: %d\n", priv->port, enable); /* Enable/disable the FIFO 0/1 message pending interrupt */ - regval = stm32l4can_getreg(priv, STM32L4_CAN_IER_OFFSET); + regval = stm32l4can_getreg(priv, STM32_CAN_IER_OFFSET); if (enable) { regval |= CAN_IER_FMPIE0 | CAN_IER_FMPIE1; @@ -724,7 +724,7 @@ static void stm32l4can_rxint(struct can_dev_s *dev, bool enable) regval &= ~(CAN_IER_FMPIE0 | CAN_IER_FMPIE1); } - stm32l4can_putreg(priv, STM32L4_CAN_IER_OFFSET, regval); + stm32l4can_putreg(priv, STM32_CAN_IER_OFFSET, regval); } /**************************************************************************** @@ -743,7 +743,7 @@ static void stm32l4can_rxint(struct can_dev_s *dev, bool enable) static void stm32l4can_txint(struct can_dev_s *dev, bool enable) { - struct stm32l4_can_s *priv = dev->cd_priv; + struct stm32_can_s *priv = dev->cd_priv; uint32_t regval; caninfo("CAN%d enable: %d\n", priv->port, enable); @@ -752,9 +752,9 @@ static void stm32l4can_txint(struct can_dev_s *dev, bool enable) if (!enable) { - regval = stm32l4can_getreg(priv, STM32L4_CAN_IER_OFFSET); + regval = stm32l4can_getreg(priv, STM32_CAN_IER_OFFSET); regval &= ~CAN_IER_TMEIE; - stm32l4can_putreg(priv, STM32L4_CAN_IER_OFFSET, regval); + stm32l4can_putreg(priv, STM32_CAN_IER_OFFSET, regval); } } @@ -775,7 +775,7 @@ static void stm32l4can_txint(struct can_dev_s *dev, bool enable) static int stm32l4can_ioctl(struct can_dev_s *dev, int cmd, unsigned long arg) { - struct stm32l4_can_s *priv; + struct stm32_can_s *priv; int ret = -ENOTTY; caninfo("cmd=%04x arg=%lu\n", cmd, arg); @@ -806,7 +806,7 @@ static int stm32l4can_ioctl(struct can_dev_s *dev, int cmd, uint32_t brp; DEBUGASSERT(bt != NULL); - regval = stm32l4can_getreg(priv, STM32L4_CAN_BTR_OFFSET); + regval = stm32l4can_getreg(priv, STM32_CAN_BTR_OFFSET); bt->bt_sjw = ((regval & CAN_BTR_SJW_MASK) >> CAN_BTR_SJW_SHIFT) + 1; bt->bt_tseg1 = ((regval & CAN_BTR_TS1_MASK) >> @@ -815,7 +815,7 @@ static int stm32l4can_ioctl(struct can_dev_s *dev, int cmd, CAN_BTR_TS2_SHIFT) + 1; brp = ((regval & CAN_BTR_BRP_MASK) >> CAN_BTR_BRP_SHIFT) + 1; - bt->bt_baud = STM32L4_PCLK1_FREQUENCY / + bt->bt_baud = STM32_PCLK1_FREQUENCY / (brp * (bt->bt_tseg1 + bt->bt_tseg2 + 1)); ret = OK; } @@ -848,18 +848,18 @@ static int stm32l4can_ioctl(struct can_dev_s *dev, int cmd, uint32_t regval; DEBUGASSERT(bt != NULL); - DEBUGASSERT(bt->bt_baud < STM32L4_PCLK1_FREQUENCY); + DEBUGASSERT(bt->bt_baud < STM32_PCLK1_FREQUENCY); DEBUGASSERT(bt->bt_sjw > 0 && bt->bt_sjw <= 4); DEBUGASSERT(bt->bt_tseg1 > 0 && bt->bt_tseg1 <= 16); DEBUGASSERT(bt->bt_tseg2 > 0 && bt->bt_tseg2 <= 8); - regval = stm32l4can_getreg(priv, STM32L4_CAN_BTR_OFFSET); + regval = stm32l4can_getreg(priv, STM32_CAN_BTR_OFFSET); /* Extract bit timing data. * tmp is in clocks per bit time. */ - tmp = STM32L4_PCLK1_FREQUENCY / bt->bt_baud; + tmp = STM32_PCLK1_FREQUENCY / bt->bt_baud; /* This value is dynamic as requested by user */ @@ -904,12 +904,12 @@ static int stm32l4can_ioctl(struct can_dev_s *dev, int cmd, break; } - stm32l4can_putreg(priv, STM32L4_CAN_BTR_OFFSET, regval); + stm32l4can_putreg(priv, STM32_CAN_BTR_OFFSET, regval); ret = stm32l4can_exitinitmode(priv); if (ret >= 0) { - priv->baud = STM32L4_PCLK1_FREQUENCY / + priv->baud = STM32_PCLK1_FREQUENCY / (brp * (bt->bt_tseg1 + bt->bt_tseg2 + 1)); } } @@ -934,7 +934,7 @@ static int stm32l4can_ioctl(struct can_dev_s *dev, int cmd, DEBUGASSERT(bm != NULL); - regval = stm32l4can_getreg(priv, STM32L4_CAN_BTR_OFFSET); + regval = stm32l4can_getreg(priv, STM32_CAN_BTR_OFFSET); bm->bm_loopback = ((regval & CAN_BTR_LBKM) == CAN_BTR_LBKM); bm->bm_silent = ((regval & CAN_BTR_SILM) == CAN_BTR_SILM); @@ -961,7 +961,7 @@ static int stm32l4can_ioctl(struct can_dev_s *dev, int cmd, DEBUGASSERT(bm != NULL); - regval = stm32l4can_getreg(priv, STM32L4_CAN_BTR_OFFSET); + regval = stm32l4can_getreg(priv, STM32_CAN_BTR_OFFSET); if (bm->bm_loopback) { @@ -989,7 +989,7 @@ static int stm32l4can_ioctl(struct can_dev_s *dev, int cmd, break; } - stm32l4can_putreg(priv, STM32L4_CAN_BTR_OFFSET, regval); + stm32l4can_putreg(priv, STM32_CAN_BTR_OFFSET, regval); ret = stm32l4can_exitinitmode(priv); } @@ -1078,7 +1078,7 @@ static int stm32l4can_ioctl(struct can_dev_s *dev, int cmd, return ret; } - regval = stm32l4can_getreg(priv, STM32L4_CAN_MCR_OFFSET); + regval = stm32l4can_getreg(priv, STM32_CAN_MCR_OFFSET); if (arg == 1) { regval |= CAN_MCR_NART; @@ -1088,7 +1088,7 @@ static int stm32l4can_ioctl(struct can_dev_s *dev, int cmd, regval &= ~CAN_MCR_NART; } - stm32l4can_putreg(priv, STM32L4_CAN_MCR_OFFSET, regval); + stm32l4can_putreg(priv, STM32_CAN_MCR_OFFSET, regval); return stm32l4can_exitinitmode(priv); } break; @@ -1102,7 +1102,7 @@ static int stm32l4can_ioctl(struct can_dev_s *dev, int cmd, return ret; } - regval = stm32l4can_getreg(priv, STM32L4_CAN_MCR_OFFSET); + regval = stm32l4can_getreg(priv, STM32_CAN_MCR_OFFSET); if (arg == 1) { regval |= CAN_MCR_ABOM; @@ -1112,7 +1112,7 @@ static int stm32l4can_ioctl(struct can_dev_s *dev, int cmd, regval &= ~CAN_MCR_ABOM; } - stm32l4can_putreg(priv, STM32L4_CAN_MCR_OFFSET, regval); + stm32l4can_putreg(priv, STM32_CAN_MCR_OFFSET, regval); return stm32l4can_exitinitmode(priv); } break; @@ -1173,7 +1173,7 @@ static int stm32l4can_remoterequest(struct can_dev_s *dev, uint16_t id) static int stm32l4can_send(struct can_dev_s *dev, struct can_msg_s *msg) { - struct stm32l4_can_s *priv = dev->cd_priv; + struct stm32_can_s *priv = dev->cd_priv; uint8_t *ptr; uint32_t regval; uint32_t tmp; @@ -1185,7 +1185,7 @@ static int stm32l4can_send(struct can_dev_s *dev, /* Select one empty transmit mailbox */ - regval = stm32l4can_getreg(priv, STM32L4_CAN_TSR_OFFSET); + regval = stm32l4can_getreg(priv, STM32_CAN_TSR_OFFSET); if ((regval & CAN_TSR_TME0) != 0 && (regval & CAN_TSR_RQCP0) == 0) { txmb = 0; @@ -1206,10 +1206,10 @@ static int stm32l4can_send(struct can_dev_s *dev, /* Clear TXRQ, RTR, IDE, EXID, and STID fields */ - regval = stm32l4can_getreg(priv, STM32L4_CAN_TIR_OFFSET(txmb)); + regval = stm32l4can_getreg(priv, STM32_CAN_TIR_OFFSET(txmb)); regval &= ~(CAN_TIR_TXRQ | CAN_TIR_RTR | CAN_TIR_IDE | CAN_TIR_EXID_MASK | CAN_TIR_STID_MASK); - stm32l4can_putreg(priv, STM32L4_CAN_TIR_OFFSET(txmb), regval); + stm32l4can_putreg(priv, STM32_CAN_TIR_OFFSET(txmb), regval); /* Set up the ID, standard 11-bit or extended 29-bit. */ @@ -1233,15 +1233,15 @@ static int stm32l4can_send(struct can_dev_s *dev, regval |= (msg->cm_hdr.ch_rtr ? CAN_TIR_RTR : 0); #endif #endif - stm32l4can_putreg(priv, STM32L4_CAN_TIR_OFFSET(txmb), regval); + stm32l4can_putreg(priv, STM32_CAN_TIR_OFFSET(txmb), regval); /* Set up the DLC */ dlc = msg->cm_hdr.ch_dlc; - regval = stm32l4can_getreg(priv, STM32L4_CAN_TDTR_OFFSET(txmb)); + regval = stm32l4can_getreg(priv, STM32_CAN_TDTR_OFFSET(txmb)); regval &= ~(CAN_TDTR_DLC_MASK | CAN_TDTR_TGT); regval |= (uint32_t)dlc << CAN_TDTR_DLC_SHIFT; - stm32l4can_putreg(priv, STM32L4_CAN_TDTR_OFFSET(txmb), regval); + stm32l4can_putreg(priv, STM32_CAN_TDTR_OFFSET(txmb), regval); /* Set up the data fields */ @@ -1272,7 +1272,7 @@ static int stm32l4can_send(struct can_dev_s *dev, } } - stm32l4can_putreg(priv, STM32L4_CAN_TDLR_OFFSET(txmb), regval); + stm32l4can_putreg(priv, STM32_CAN_TDLR_OFFSET(txmb), regval); regval = 0; if (dlc > 4) @@ -1299,19 +1299,19 @@ static int stm32l4can_send(struct can_dev_s *dev, } } - stm32l4can_putreg(priv, STM32L4_CAN_TDHR_OFFSET(txmb), regval); + stm32l4can_putreg(priv, STM32_CAN_TDHR_OFFSET(txmb), regval); /* Enable the transmit mailbox empty interrupt (may already be enabled) */ - regval = stm32l4can_getreg(priv, STM32L4_CAN_IER_OFFSET); + regval = stm32l4can_getreg(priv, STM32_CAN_IER_OFFSET); regval |= CAN_IER_TMEIE; - stm32l4can_putreg(priv, STM32L4_CAN_IER_OFFSET, regval); + stm32l4can_putreg(priv, STM32_CAN_IER_OFFSET, regval); /* Request transmission */ - regval = stm32l4can_getreg(priv, STM32L4_CAN_TIR_OFFSET(txmb)); + regval = stm32l4can_getreg(priv, STM32_CAN_TIR_OFFSET(txmb)); regval |= CAN_TIR_TXRQ; /* Transmit Mailbox Request */ - stm32l4can_putreg(priv, STM32L4_CAN_TIR_OFFSET(txmb), regval); + stm32l4can_putreg(priv, STM32_CAN_TIR_OFFSET(txmb), regval); stm32l4can_dumpmbregs(priv, "After send"); return OK; @@ -1333,12 +1333,12 @@ static int stm32l4can_send(struct can_dev_s *dev, static bool stm32l4can_txready(struct can_dev_s *dev) { - struct stm32l4_can_s *priv = dev->cd_priv; + struct stm32_can_s *priv = dev->cd_priv; uint32_t regval; /* Return true if any mailbox is available */ - regval = stm32l4can_getreg(priv, STM32L4_CAN_TSR_OFFSET); + regval = stm32l4can_getreg(priv, STM32_CAN_TSR_OFFSET); caninfo("CAN%d TSR: %08" PRIx32 "\n", priv->port, regval); return (regval & CAN_ALL_MAILBOXES) != 0; @@ -1364,12 +1364,12 @@ static bool stm32l4can_txready(struct can_dev_s *dev) static bool stm32l4can_txempty(struct can_dev_s *dev) { - struct stm32l4_can_s *priv = dev->cd_priv; + struct stm32_can_s *priv = dev->cd_priv; uint32_t regval; /* Return true if all mailboxes are available */ - regval = stm32l4can_getreg(priv, STM32L4_CAN_TSR_OFFSET); + regval = stm32l4can_getreg(priv, STM32_CAN_TSR_OFFSET); caninfo("CAN%d TSR: %08" PRIx32 "\n", priv->port, regval); return (regval & CAN_ALL_MAILBOXES) == CAN_ALL_MAILBOXES; @@ -1394,7 +1394,7 @@ static bool stm32l4can_txempty(struct can_dev_s *dev) static int stm32l4can_rxinterrupt(int irq, void *context, int rxmb) { struct can_dev_s *dev = NULL; - struct stm32l4_can_s *priv; + struct stm32_can_s *priv; struct can_hdr_s hdr; uint8_t data[CAN_MAXDATALEN]; uint32_t regval; @@ -1406,7 +1406,7 @@ static int stm32l4can_rxinterrupt(int irq, void *context, int rxmb) /* Verify that a message is pending in the FIFO */ - regval = stm32l4can_getreg(priv, STM32L4_CAN_RFR_OFFSET(rxmb)); + regval = stm32l4can_getreg(priv, STM32_CAN_RFR_OFFSET(rxmb)); npending = (regval & CAN_RFR_FMP_MASK) >> CAN_RFR_FMP_SHIFT; if (npending < 1) { @@ -1425,7 +1425,7 @@ static int stm32l4can_rxinterrupt(int irq, void *context, int rxmb) /* Get the CAN identifier. */ - regval = stm32l4can_getreg(priv, STM32L4_CAN_RIR_OFFSET(rxmb)); + regval = stm32l4can_getreg(priv, STM32_CAN_RIR_OFFSET(rxmb)); #ifdef CONFIG_CAN_EXTID if ((regval & CAN_RIR_IDE) != 0) @@ -1462,18 +1462,18 @@ static int stm32l4can_rxinterrupt(int irq, void *context, int rxmb) /* Get the DLC */ - regval = stm32l4can_getreg(priv, STM32L4_CAN_RDTR_OFFSET(rxmb)); + regval = stm32l4can_getreg(priv, STM32_CAN_RDTR_OFFSET(rxmb)); hdr.ch_dlc = (regval & CAN_RDTR_DLC_MASK) >> CAN_RDTR_DLC_SHIFT; /* Save the message data */ - regval = stm32l4can_getreg(priv, STM32L4_CAN_RDLR_OFFSET(rxmb)); + regval = stm32l4can_getreg(priv, STM32_CAN_RDLR_OFFSET(rxmb)); data[0] = (regval & CAN_RDLR_DATA0_MASK) >> CAN_RDLR_DATA0_SHIFT; data[1] = (regval & CAN_RDLR_DATA1_MASK) >> CAN_RDLR_DATA1_SHIFT; data[2] = (regval & CAN_RDLR_DATA2_MASK) >> CAN_RDLR_DATA2_SHIFT; data[3] = (regval & CAN_RDLR_DATA3_MASK) >> CAN_RDLR_DATA3_SHIFT; - regval = stm32l4can_getreg(priv, STM32L4_CAN_RDHR_OFFSET(rxmb)); + regval = stm32l4can_getreg(priv, STM32_CAN_RDHR_OFFSET(rxmb)); data[4] = (regval & CAN_RDHR_DATA4_MASK) >> CAN_RDHR_DATA4_SHIFT; data[5] = (regval & CAN_RDHR_DATA5_MASK) >> CAN_RDHR_DATA5_SHIFT; data[6] = (regval & CAN_RDHR_DATA6_MASK) >> CAN_RDHR_DATA6_SHIFT; @@ -1488,9 +1488,9 @@ static int stm32l4can_rxinterrupt(int irq, void *context, int rxmb) #ifndef CONFIG_CAN_EXTID errout: #endif - regval = stm32l4can_getreg(priv, STM32L4_CAN_RFR_OFFSET(rxmb)); + regval = stm32l4can_getreg(priv, STM32_CAN_RFR_OFFSET(rxmb)); regval |= CAN_RFR_RFOM; - stm32l4can_putreg(priv, STM32L4_CAN_RFR_OFFSET(rxmb), regval); + stm32l4can_putreg(priv, STM32_CAN_RFR_OFFSET(rxmb), regval); return ret; } @@ -1552,7 +1552,7 @@ static int stm32l4can_rx1interrupt(int irq, void *context, void *arg) static int stm32l4can_txinterrupt(int irq, void *context, void *arg) { struct can_dev_s *dev = NULL; - struct stm32l4_can_s *priv; + struct stm32_can_s *priv; uint32_t regval; dev = &g_can1dev; @@ -1560,7 +1560,7 @@ static int stm32l4can_txinterrupt(int irq, void *context, void *arg) /* Get the transmit status */ - regval = stm32l4can_getreg(priv, STM32L4_CAN_TSR_OFFSET); + regval = stm32l4can_getreg(priv, STM32_CAN_TSR_OFFSET); /* Check for RQCP0: Request completed mailbox 0 */ @@ -1570,7 +1570,7 @@ static int stm32l4can_txinterrupt(int irq, void *context, void *arg) * ALST0 and TERR0) for Mailbox 0. */ - stm32l4can_putreg(priv, STM32L4_CAN_TSR_OFFSET, CAN_TSR_RQCP0); + stm32l4can_putreg(priv, STM32_CAN_TSR_OFFSET, CAN_TSR_RQCP0); /* Check for errors */ @@ -1590,7 +1590,7 @@ static int stm32l4can_txinterrupt(int irq, void *context, void *arg) * ALST1 and TERR1) for Mailbox 1. */ - stm32l4can_putreg(priv, STM32L4_CAN_TSR_OFFSET, CAN_TSR_RQCP1); + stm32l4can_putreg(priv, STM32_CAN_TSR_OFFSET, CAN_TSR_RQCP1); /* Check for errors */ @@ -1610,7 +1610,7 @@ static int stm32l4can_txinterrupt(int irq, void *context, void *arg) * ALST2 and TERR2) for Mailbox 2. */ - stm32l4can_putreg(priv, STM32L4_CAN_TSR_OFFSET, CAN_TSR_RQCP2); + stm32l4can_putreg(priv, STM32_CAN_TSR_OFFSET, CAN_TSR_RQCP2); /* Check for errors */ @@ -1682,7 +1682,7 @@ static int stm32l4can_txinterrupt(int irq, void *context, void *arg) * ****************************************************************************/ -static int stm32l4can_bittiming(struct stm32l4_can_s *priv) +static int stm32l4can_bittiming(struct stm32_can_s *priv) { uint32_t tmp; uint32_t brp; @@ -1690,7 +1690,7 @@ static int stm32l4can_bittiming(struct stm32l4_can_s *priv) uint32_t ts2; caninfo("CAN%d PCLK1: %d baud: %d\n", - priv->port, STM32L4_PCLK1_FREQUENCY, priv->baud); + priv->port, STM32_PCLK1_FREQUENCY, priv->baud); /* Try to get CAN_BIT_QUANTA quanta in one bit_time. * @@ -1708,7 +1708,7 @@ static int stm32l4can_bittiming(struct stm32l4_can_s *priv) * PCLK1 = 42,000,000 baud = 700,000 nquanta = 14 : brp = 4 */ - tmp = STM32L4_PCLK1_FREQUENCY / priv->baud; + tmp = STM32_PCLK1_FREQUENCY / priv->baud; if (tmp < CAN_BIT_QUANTA) { /* At the smallest brp value (1), there are already too few bit times @@ -1729,15 +1729,15 @@ static int stm32l4can_bittiming(struct stm32l4_can_s *priv) } } - /* Otherwise, nquanta is CAN_BIT_QUANTA, ts1 is CONFIG_STM32L4_CAN_TSEG1, - * ts2 is CONFIG_STM32L4_CAN_TSEG2 and we calculate brp to achieve + /* Otherwise, nquanta is CAN_BIT_QUANTA, ts1 is CONFIG_STM32_CAN_TSEG1, + * ts2 is CONFIG_STM32_CAN_TSEG2 and we calculate brp to achieve * CAN_BIT_QUANTA quanta in the bit time */ else { - ts1 = CONFIG_STM32L4_CAN_TSEG1; - ts2 = CONFIG_STM32L4_CAN_TSEG2; + ts1 = CONFIG_STM32_CAN_TSEG1; + ts2 = CONFIG_STM32_CAN_TSEG2; brp = (tmp + (CAN_BIT_QUANTA / 2)) / CAN_BIT_QUANTA; DEBUGASSERT(brp >= 1 && brp <= CAN_BTR_BRP_MAX); } @@ -1762,7 +1762,7 @@ static int stm32l4can_bittiming(struct stm32l4_can_s *priv) tmp |= CAN_BTR_LBKM; #endif - stm32l4can_putreg(priv, STM32L4_CAN_BTR_OFFSET, tmp); + stm32l4can_putreg(priv, STM32_CAN_BTR_OFFSET, tmp); return OK; } @@ -1782,7 +1782,7 @@ static int stm32l4can_bittiming(struct stm32l4_can_s *priv) * ****************************************************************************/ -static int stm32l4can_enterinitmode(struct stm32l4_can_s *priv) +static int stm32l4can_enterinitmode(struct stm32_can_s *priv) { uint32_t regval; volatile uint32_t timeout; @@ -1791,15 +1791,15 @@ static int stm32l4can_enterinitmode(struct stm32l4_can_s *priv) /* Enter initialization mode */ - regval = stm32l4can_getreg(priv, STM32L4_CAN_MCR_OFFSET); + regval = stm32l4can_getreg(priv, STM32_CAN_MCR_OFFSET); regval |= CAN_MCR_INRQ; - stm32l4can_putreg(priv, STM32L4_CAN_MCR_OFFSET, regval); + stm32l4can_putreg(priv, STM32_CAN_MCR_OFFSET, regval); /* Wait until initialization mode is acknowledged */ for (timeout = INAK_TIMEOUT; timeout > 0; timeout--) { - regval = stm32l4can_getreg(priv, STM32L4_CAN_MSR_OFFSET); + regval = stm32l4can_getreg(priv, STM32_CAN_MSR_OFFSET); if ((regval & CAN_MSR_INAK) != 0) { /* We are in initialization mode */ @@ -1833,22 +1833,22 @@ static int stm32l4can_enterinitmode(struct stm32l4_can_s *priv) * ****************************************************************************/ -static int stm32l4can_exitinitmode(struct stm32l4_can_s *priv) +static int stm32l4can_exitinitmode(struct stm32_can_s *priv) { uint32_t regval; volatile uint32_t timeout; /* Exit Initialization mode, enter Normal mode */ - regval = stm32l4can_getreg(priv, STM32L4_CAN_MCR_OFFSET); + regval = stm32l4can_getreg(priv, STM32_CAN_MCR_OFFSET); regval &= ~CAN_MCR_INRQ; - stm32l4can_putreg(priv, STM32L4_CAN_MCR_OFFSET, regval); + stm32l4can_putreg(priv, STM32_CAN_MCR_OFFSET, regval); /* Wait until the initialization mode exit is acknowledged */ for (timeout = INAK_TIMEOUT; timeout > 0; timeout--) { - regval = stm32l4can_getreg(priv, STM32L4_CAN_MSR_OFFSET); + regval = stm32l4can_getreg(priv, STM32_CAN_MSR_OFFSET); if ((regval & CAN_MSR_INAK) == 0) { /* We are out of initialization mode */ @@ -1884,7 +1884,7 @@ static int stm32l4can_exitinitmode(struct stm32l4_can_s *priv) * ****************************************************************************/ -static int stm32l4can_cellinit(struct stm32l4_can_s *priv) +static int stm32l4can_cellinit(struct stm32_can_s *priv) { uint32_t regval; int ret; @@ -1893,9 +1893,9 @@ static int stm32l4can_cellinit(struct stm32l4_can_s *priv) /* Exit from sleep mode */ - regval = stm32l4can_getreg(priv, STM32L4_CAN_MCR_OFFSET); + regval = stm32l4can_getreg(priv, STM32_CAN_MCR_OFFSET); regval &= ~CAN_MCR_SLEEP; - stm32l4can_putreg(priv, STM32L4_CAN_MCR_OFFSET, regval); + stm32l4can_putreg(priv, STM32_CAN_MCR_OFFSET, regval); ret = stm32l4can_enterinitmode(priv); if (ret != 0) @@ -1913,10 +1913,10 @@ static int stm32l4can_cellinit(struct stm32l4_can_s *priv) * - Transmit FIFO priority */ - regval = stm32l4can_getreg(priv, STM32L4_CAN_MCR_OFFSET); + regval = stm32l4can_getreg(priv, STM32_CAN_MCR_OFFSET); regval &= ~(CAN_MCR_TXFP | CAN_MCR_RFLM | CAN_MCR_NART | CAN_MCR_AWUM | CAN_MCR_ABOM | CAN_MCR_TTCM); - stm32l4can_putreg(priv, STM32L4_CAN_MCR_OFFSET, regval); + stm32l4can_putreg(priv, STM32_CAN_MCR_OFFSET, regval); /* Configure bit timing. */ @@ -1962,7 +1962,7 @@ static int stm32l4can_cellinit(struct stm32l4_can_s *priv) * ****************************************************************************/ -static int stm32l4can_filterinit(struct stm32l4_can_s *priv) +static int stm32l4can_filterinit(struct stm32_can_s *priv) { uint32_t regval; uint32_t bitmask; @@ -1975,52 +1975,52 @@ static int stm32l4can_filterinit(struct stm32l4_can_s *priv) /* Enter filter initialization mode */ - regval = stm32l4can_getfreg(priv, STM32L4_CAN_FMR_OFFSET); + regval = stm32l4can_getfreg(priv, STM32_CAN_FMR_OFFSET); regval |= CAN_FMR_FINIT; - stm32l4can_putfreg(priv, STM32L4_CAN_FMR_OFFSET, regval); + stm32l4can_putfreg(priv, STM32_CAN_FMR_OFFSET, regval); /* Disable the filter */ - regval = stm32l4can_getfreg(priv, STM32L4_CAN_FA1R_OFFSET); + regval = stm32l4can_getfreg(priv, STM32_CAN_FA1R_OFFSET); regval &= ~bitmask; - stm32l4can_putfreg(priv, STM32L4_CAN_FA1R_OFFSET, regval); + stm32l4can_putfreg(priv, STM32_CAN_FA1R_OFFSET, regval); /* Select the 32-bit scale for the filter */ - regval = stm32l4can_getfreg(priv, STM32L4_CAN_FS1R_OFFSET); + regval = stm32l4can_getfreg(priv, STM32_CAN_FS1R_OFFSET); regval |= bitmask; - stm32l4can_putfreg(priv, STM32L4_CAN_FS1R_OFFSET, regval); + stm32l4can_putfreg(priv, STM32_CAN_FS1R_OFFSET, regval); /* There are 14 or 28 filter banks (depending) on the device. * Each filter bank is composed of two 32-bit registers, CAN_FiR: */ - stm32l4can_putfreg(priv, STM32L4_CAN_FIR_OFFSET(priv->filter, 1), 0); - stm32l4can_putfreg(priv, STM32L4_CAN_FIR_OFFSET(priv->filter, 2), 0); + stm32l4can_putfreg(priv, STM32_CAN_FIR_OFFSET(priv->filter, 1), 0); + stm32l4can_putfreg(priv, STM32_CAN_FIR_OFFSET(priv->filter, 2), 0); /* Set Id/Mask mode for the filter */ - regval = stm32l4can_getfreg(priv, STM32L4_CAN_FM1R_OFFSET); + regval = stm32l4can_getfreg(priv, STM32_CAN_FM1R_OFFSET); regval &= ~bitmask; - stm32l4can_putfreg(priv, STM32L4_CAN_FM1R_OFFSET, regval); + stm32l4can_putfreg(priv, STM32_CAN_FM1R_OFFSET, regval); /* Assign FIFO 0 for the filter */ - regval = stm32l4can_getfreg(priv, STM32L4_CAN_FFA1R_OFFSET); + regval = stm32l4can_getfreg(priv, STM32_CAN_FFA1R_OFFSET); regval &= ~bitmask; - stm32l4can_putfreg(priv, STM32L4_CAN_FFA1R_OFFSET, regval); + stm32l4can_putfreg(priv, STM32_CAN_FFA1R_OFFSET, regval); /* Enable the filter */ - regval = stm32l4can_getfreg(priv, STM32L4_CAN_FA1R_OFFSET); + regval = stm32l4can_getfreg(priv, STM32_CAN_FA1R_OFFSET); regval |= bitmask; - stm32l4can_putfreg(priv, STM32L4_CAN_FA1R_OFFSET, regval); + stm32l4can_putfreg(priv, STM32_CAN_FA1R_OFFSET, regval); /* Exit filter initialization mode */ - regval = stm32l4can_getfreg(priv, STM32L4_CAN_FMR_OFFSET); + regval = stm32l4can_getfreg(priv, STM32_CAN_FMR_OFFSET); regval &= ~CAN_FMR_FINIT; - stm32l4can_putfreg(priv, STM32L4_CAN_FMR_OFFSET, regval); + stm32l4can_putfreg(priv, STM32_CAN_FMR_OFFSET, regval); return OK; } @@ -2042,7 +2042,7 @@ static int stm32l4can_filterinit(struct stm32l4_can_s *priv) ****************************************************************************/ #ifdef CONFIG_CAN_EXTID -static int stm32l4can_addextfilter(struct stm32l4_can_s *priv, +static int stm32l4can_addextfilter(struct stm32_can_s *priv, struct canioc_extfilter_s *arg) { return -ENOTTY; @@ -2068,7 +2068,7 @@ static int stm32l4can_addextfilter(struct stm32l4_can_s *priv, ****************************************************************************/ #ifdef CONFIG_CAN_EXTID -static int stm32l4can_delextfilter(struct stm32l4_can_s *priv, int arg) +static int stm32l4can_delextfilter(struct stm32_can_s *priv, int arg) { return -ENOTTY; } @@ -2091,7 +2091,7 @@ static int stm32l4can_delextfilter(struct stm32l4_can_s *priv, int arg) * ****************************************************************************/ -static int stm32l4can_addstdfilter(struct stm32l4_can_s *priv, +static int stm32l4can_addstdfilter(struct stm32_can_s *priv, struct canioc_stdfilter_s *arg) { return -ENOTTY; @@ -2115,7 +2115,7 @@ static int stm32l4can_addstdfilter(struct stm32l4_can_s *priv, * ****************************************************************************/ -static int stm32l4can_delstdfilter(struct stm32l4_can_s *priv, int arg) +static int stm32l4can_delstdfilter(struct stm32_can_s *priv, int arg) { return -ENOTTY; } @@ -2125,7 +2125,7 @@ static int stm32l4can_delstdfilter(struct stm32l4_can_s *priv, int arg) ****************************************************************************/ /**************************************************************************** - * Name: stm32l4can_initialize + * Name: stm32_caninitialize * * Description: * Initialize the selected CAN port @@ -2138,17 +2138,17 @@ static int stm32l4can_delstdfilter(struct stm32l4_can_s *priv, int arg) * ****************************************************************************/ -struct can_dev_s *stm32l4can_initialize(int port) +struct can_dev_s *stm32_caninitialize(int port) { struct can_dev_s *dev = NULL; caninfo("CAN%d\n", port); /* NOTE: Peripherical clocking for CAN1 and/or CAN2 was already provided - * by stm32l4_clockconfig() early in the reset sequence. + * by stm32_clockconfig() early in the reset sequence. */ -#ifdef CONFIG_STM32L4_CAN1 +#ifdef CONFIG_STM32_CAN1 if (port == 1) { /* Select the CAN1 device structure */ @@ -2159,8 +2159,8 @@ struct can_dev_s *stm32l4can_initialize(int port) * file must have been disambiguated in the board.h file. */ - stm32l4_configgpio(GPIO_CAN1_RX); - stm32l4_configgpio(GPIO_CAN1_TX); + stm32_configgpio(GPIO_CAN1_RX); + stm32_configgpio(GPIO_CAN1_TX); } else #endif @@ -2172,4 +2172,4 @@ struct can_dev_s *stm32l4can_initialize(int port) return dev; } -#endif /* CONFIG_CAN && (CONFIG_STM32L4_CAN1 || CONFIG_STM32L4_CAN2) */ +#endif /* CONFIG_CAN && (CONFIG_STM32_CAN1 || CONFIG_STM32_CAN2) */ diff --git a/arch/arm/src/stm32l4/stm32l4_can.h b/arch/arm/src/stm32l4/stm32l4_can.h index 8328d9a13fb9c..1a4d5e9731578 100644 --- a/arch/arm/src/stm32l4/stm32l4_can.h +++ b/arch/arm/src/stm32l4/stm32l4_can.h @@ -42,39 +42,39 @@ /* Up to 1 CAN interfaces are supported */ -#if STM32L4_NCAN < 1 -# undef CONFIG_STM32L4_CAN1 +#if STM32_NCAN < 1 +# undef CONFIG_STM32_CAN1 #endif -#if defined(CONFIG_CAN) && defined(CONFIG_STM32L4_CAN1) +#if defined(CONFIG_CAN) && defined(CONFIG_STM32_CAN1) /* CAN BAUD */ -#if defined(CONFIG_STM32L4_CAN1) && !defined(CONFIG_STM32L4_CAN1_BAUD) -# error "CONFIG_STM32L4_CAN1_BAUD is not defined" +#if defined(CONFIG_STM32_CAN1) && !defined(CONFIG_STM32_CAN1_BAUD) +# error "CONFIG_STM32_CAN1_BAUD is not defined" #endif /* User-defined TSEG1 and TSEG2 settings may be used. * - * CONFIG_STM32L4_CAN_TSEG1 = the number of CAN time quanta in segment 1 - * CONFIG_STM32L4_CAN_TSEG2 = the number of CAN time quanta in segment 2 + * CONFIG_STM32_CAN_TSEG1 = the number of CAN time quanta in segment 1 + * CONFIG_STM32_CAN_TSEG2 = the number of CAN time quanta in segment 2 * CAN_BIT_QUANTA = The number of CAN time quanta in on bit time */ -#ifndef CONFIG_STM32L4_CAN_TSEG1 -# define CONFIG_STM32L4_CAN_TSEG1 6 +#ifndef CONFIG_STM32_CAN_TSEG1 +# define CONFIG_STM32_CAN_TSEG1 6 #endif -#if CONFIG_STM32L4_CAN_TSEG1 < 1 || CONFIG_STM32L4_CAN_TSEG1 > CAN_BTR_TSEG1_MAX -# error "CONFIG_STM32L4_CAN_TSEG1 is out of range" +#if CONFIG_STM32_CAN_TSEG1 < 1 || CONFIG_STM32_CAN_TSEG1 > CAN_BTR_TSEG1_MAX +# error "CONFIG_STM32_CAN_TSEG1 is out of range" #endif -#ifndef CONFIG_STM32L4_CAN_TSEG2 -# define CONFIG_STM32L4_CAN_TSEG2 7 +#ifndef CONFIG_STM32_CAN_TSEG2 +# define CONFIG_STM32_CAN_TSEG2 7 #endif -#if CONFIG_STM32L4_CAN_TSEG2 < 1 || CONFIG_STM32L4_CAN_TSEG2 > CAN_BTR_TSEG2_MAX -# error "CONFIG_STM32L4_CAN_TSEG2 is out of range" +#if CONFIG_STM32_CAN_TSEG2 < 1 || CONFIG_STM32_CAN_TSEG2 > CAN_BTR_TSEG2_MAX +# error "CONFIG_STM32_CAN_TSEG2 is out of range" #endif /**************************************************************************** @@ -101,7 +101,7 @@ extern "C" ****************************************************************************/ /**************************************************************************** - * Name: stm32l4can_initialize + * Name: stm32_caninitialize * * Description: * Initialize the selected CAN port @@ -115,7 +115,7 @@ extern "C" ****************************************************************************/ struct can_dev_s; -struct can_dev_s *stm32l4can_initialize(int port); +struct can_dev_s *stm32_caninitialize(int port); #undef EXTERN #if defined(__cplusplus) @@ -123,5 +123,5 @@ struct can_dev_s *stm32l4can_initialize(int port); #endif #endif /* __ASSEMBLY__ */ -#endif /* CONFIG_CAN && CONFIG_STM32L4_CAN1 */ +#endif /* CONFIG_CAN && CONFIG_STM32_CAN1 */ #endif /* __ARCH_ARM_SRC_STM32L4_STM32L4_CAN_H */ diff --git a/arch/arm/src/stm32l4/stm32l4_comp.c b/arch/arm/src/stm32l4/stm32l4_comp.c index 6bc365394b3f1..90df1275b718d 100644 --- a/arch/arm/src/stm32l4/stm32l4_comp.c +++ b/arch/arm/src/stm32l4/stm32l4_comp.c @@ -53,12 +53,12 @@ #include -#if !(defined(CONFIG_STM32L4_STM32L4X3) || defined(CONFIG_STM32L4_STM32L4X5) || \ - defined(CONFIG_STM32L4_STM32L4X6) || defined(CONFIG_STM32L4_STM32L4XR)) +#if !(defined(CONFIG_STM32_STM32L4X3) || defined(CONFIG_STM32_STM32L4X5) || \ + defined(CONFIG_STM32_STM32L4X6) || defined(CONFIG_STM32_STM32L4XR)) # error "Unrecognized STM32 chip" #endif -#ifdef CONFIG_STM32L4_COMP +#ifdef CONFIG_STM32_COMP /**************************************************************************** * Private Function Prototypes @@ -66,12 +66,12 @@ /* COMP Register access */ -static inline void modify_csr(const struct stm32l4_comp_config_s *cfg, +static inline void modify_csr(const struct stm32_comp_config_s *cfg, uint32_t clearbits, uint32_t setbits); -static inline uint32_t get_csr(const struct stm32l4_comp_config_s *cfg); -static void stm32l4_compenable(struct stm32l4_comp_config_s *cfg, +static inline uint32_t get_csr(const struct stm32_comp_config_s *cfg); +static void stm32_compenable(struct stm32_comp_config_s *cfg, bool en); -static int stm32l4_compconfig(const struct comp_dev_s *dev); +static int stm32_compconfig(const struct comp_dev_s *dev); /* COMP Driver Methods */ @@ -96,7 +96,7 @@ static const struct comp_ops_s g_compops = .ao_bind = comp_bind, }; -static struct stm32l4_comp_config_s g_comp1priv = +static struct stm32_comp_config_s g_comp1priv = { .interrupt = { @@ -104,12 +104,12 @@ static struct stm32l4_comp_config_s g_comp1priv = .rising = true, .falling = false }, - .inp = STM32L4_COMP_INP_PIN_2, - .inm = STM32L4_COMP_INM_VREF, - .hyst = STM32L4_COMP_HYST_LOW, - .speed = STM32L4_COMP_SPEED_MEDIUM, + .inp = STM32_COMP_INP_PIN_2, + .inm = STM32_COMP_INM_VREF, + .hyst = STM32_COMP_HYST_LOW, + .speed = STM32_COMP_SPEED_MEDIUM, .inverted = false, - .csr = STM32L4_COMP1_CSR, + .csr = STM32_COMP1_CSR, }; static struct comp_dev_s g_comp1dev = @@ -118,7 +118,7 @@ static struct comp_dev_s g_comp1dev = .ad_priv = &g_comp1priv, }; -static struct stm32l4_comp_config_s g_comp2priv = +static struct stm32_comp_config_s g_comp2priv = { .interrupt = { @@ -126,12 +126,12 @@ static struct stm32l4_comp_config_s g_comp2priv = .rising = true, .falling = false }, - .inp = STM32L4_COMP_INP_PIN_1, - .inm = STM32L4_COMP_INM_DAC_1, - .hyst = STM32L4_COMP_HYST_LOW, - .speed = STM32L4_COMP_SPEED_MEDIUM, + .inp = STM32_COMP_INP_PIN_1, + .inm = STM32_COMP_INM_DAC_1, + .hyst = STM32_COMP_HYST_LOW, + .speed = STM32_COMP_SPEED_MEDIUM, .inverted = false, - .csr = STM32L4_COMP2_CSR, + .csr = STM32_COMP2_CSR, }; static struct comp_dev_s g_comp2dev = @@ -148,7 +148,7 @@ static struct comp_dev_s g_comp2dev = * Name: modify_csr ****************************************************************************/ -static inline void modify_csr(const struct stm32l4_comp_config_s *cfg, +static inline void modify_csr(const struct stm32_comp_config_s *cfg, uint32_t clearbits, uint32_t setbits) { modifyreg32(cfg->csr, clearbits, setbits); @@ -158,7 +158,7 @@ static inline void modify_csr(const struct stm32l4_comp_config_s *cfg, * Name: get_csr ****************************************************************************/ -static inline uint32_t get_csr(const struct stm32l4_comp_config_s *cfg) +static inline uint32_t get_csr(const struct stm32_comp_config_s *cfg) { return getreg32(cfg->csr); } @@ -184,7 +184,7 @@ static int comp_setup(struct comp_dev_s *dev) /* Configure selected comparator */ - ret = stm32l4_compconfig(dev); + ret = stm32_compconfig(dev); if (ret < 0) { aerr("ERROR: Failed to initialize COMP: %d\n", ret); @@ -212,10 +212,10 @@ static int comp_setup(struct comp_dev_s *dev) static void comp_shutdown(struct comp_dev_s *dev) { - struct stm32l4_comp_config_s *cfg; + struct stm32_comp_config_s *cfg; cfg = dev->ad_priv; - stm32l4_compenable(cfg, false); + stm32_compenable(cfg, false); } /**************************************************************************** @@ -235,7 +235,7 @@ static void comp_shutdown(struct comp_dev_s *dev) static int comp_read(struct comp_dev_s *dev) { - struct stm32l4_comp_config_s *cfg; + struct stm32_comp_config_s *cfg; uint32_t regval; cfg = dev->ad_priv; @@ -283,8 +283,8 @@ static int comp_ioctl(struct comp_dev_s *dev, int cmd, unsigned long arg) static int comp_bind(struct comp_dev_s *dev, const struct comp_callback_s *callback) { - struct stm32l4_comp_config_s *priv = - (struct stm32l4_comp_config_s *)dev->ad_priv; + struct stm32_comp_config_s *priv = + (struct stm32_comp_config_s *)dev->ad_priv; DEBUGASSERT(priv != NULL); priv->interrupt.cb = callback; @@ -296,7 +296,7 @@ static int comp_bind(struct comp_dev_s *dev, ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_compenable + * Name: stm32_compenable * * Description: * Enable/disable comparator @@ -307,7 +307,7 @@ static int comp_bind(struct comp_dev_s *dev, * ****************************************************************************/ -static void stm32l4_compenable(struct stm32l4_comp_config_s *cfg, +static void stm32_compenable(struct stm32_comp_config_s *cfg, bool en) { uint32_t clearbits = en ? 0 : COMP_CSR_EN; @@ -316,15 +316,15 @@ static void stm32l4_compenable(struct stm32l4_comp_config_s *cfg, modify_csr(cfg, clearbits, setbits); } -static int stm32l4_exti_comp_isr(int irq, void *context, void *arg) +static int stm32_exti_comp_isr(int irq, void *context, void *arg) { struct comp_dev_s *dev = (struct comp_dev_s *)arg; - struct stm32l4_comp_config_s *cfg = dev->ad_priv; + struct stm32_comp_config_s *cfg = dev->ad_priv; DEBUGASSERT(cfg->interrupt.cb && (cfg->interrupt.rising || cfg->interrupt.falling)); - ainfo("isr: %d\n", (cfg->csr == STM32L4_COMP1_CSR ? 0 : 1)); + ainfo("isr: %d\n", (cfg->csr == STM32_COMP1_CSR ? 0 : 1)); cfg->interrupt.cb->au_notify(dev, comp_read(dev)); @@ -332,7 +332,7 @@ static int stm32l4_exti_comp_isr(int irq, void *context, void *arg) } /**************************************************************************** - * Name: stm32l4_compconfig + * Name: stm32_compconfig * * Description: * Configure comparator and I/Os used as comparators inputs @@ -345,9 +345,9 @@ static int stm32l4_exti_comp_isr(int irq, void *context, void *arg) * ****************************************************************************/ -static int stm32l4_compconfig(const struct comp_dev_s *dev) +static int stm32_compconfig(const struct comp_dev_s *dev) { - struct stm32l4_comp_config_s *cfg; + struct stm32_comp_config_s *cfg; uint32_t regval = 0; uint32_t mask = 0; uint32_t clearbits; @@ -356,28 +356,28 @@ static int stm32l4_compconfig(const struct comp_dev_s *dev) int cmp; cfg = dev->ad_priv; - cmp = cfg->csr == STM32L4_COMP1_CSR ? STM32L4_COMP1 : STM32L4_COMP2; + cmp = cfg->csr == STM32_COMP1_CSR ? STM32_COMP1 : STM32_COMP2; /* Input plus */ mask |= COMP_CSR_INPSEL_MASK; switch (cfg->inp) { - case STM32L4_COMP_INP_PIN_1: - stm32l4_configgpio(cmp == STM32L4_COMP1 ? GPIO_COMP1_INP_1 : + case STM32_COMP_INP_PIN_1: + stm32_configgpio(cmp == STM32_COMP1 ? GPIO_COMP1_INP_1 : GPIO_COMP2_INP_1); regval |= COMP_CSR_INPSEL_PIN1; break; - case STM32L4_COMP_INP_PIN_2: - stm32l4_configgpio(cmp == STM32L4_COMP1 ? GPIO_COMP1_INP_2 : + case STM32_COMP_INP_PIN_2: + stm32_configgpio(cmp == STM32_COMP1 ? GPIO_COMP1_INP_2 : GPIO_COMP2_INP_2); regval |= COMP_CSR_INPSEL_PIN2; break; -#if defined(CONFIG_STM32L4_STM32L4X3) - case STM32L4_COMP_INP_PIN_3: - stm32l4_configgpio(cmp == STM32L4_COMP1 ? GPIO_COMP1_INP_3 : +#if defined(CONFIG_STM32_STM32L4X3) + case STM32_COMP_INP_PIN_3: + stm32_configgpio(cmp == STM32_COMP1 ? GPIO_COMP1_INP_3 : GPIO_COMP2_INP_3); regval |= COMP_CSR_INPSEL_PIN3; break; @@ -392,49 +392,49 @@ static int stm32l4_compconfig(const struct comp_dev_s *dev) mask |= COMP_CSR_INMSEL_MASK; switch (cfg->inm) { - case STM32L4_COMP_INM_1_4_VREF: + case STM32_COMP_INM_1_4_VREF: regval |= COMP_CSR_INMSEL_25PCT; mask |= (COMP_CSR_SCALEN | COMP_CSR_BRGEN); regval |= (COMP_CSR_SCALEN | COMP_CSR_BRGEN); break; - case STM32L4_COMP_INM_1_2_VREF: + case STM32_COMP_INM_1_2_VREF: regval |= COMP_CSR_INMSEL_50PCT; mask |= (COMP_CSR_SCALEN | COMP_CSR_BRGEN); regval |= (COMP_CSR_SCALEN | COMP_CSR_BRGEN); break; - case STM32L4_COMP_INM_3_4_VREF: + case STM32_COMP_INM_3_4_VREF: regval |= COMP_CSR_INMSEL_75PCT; mask |= (COMP_CSR_SCALEN | COMP_CSR_BRGEN); regval |= (COMP_CSR_SCALEN | COMP_CSR_BRGEN); break; - case STM32L4_COMP_INM_VREF: + case STM32_COMP_INM_VREF: regval |= COMP_CSR_INMSEL_VREF; mask |= (COMP_CSR_SCALEN | COMP_CSR_BRGEN); regval |= COMP_CSR_SCALEN; break; - case STM32L4_COMP_INM_DAC_1: + case STM32_COMP_INM_DAC_1: regval |= COMP_CSR_INMSEL_DAC1; break; - case STM32L4_COMP_INM_DAC_2: + case STM32_COMP_INM_DAC_2: regval |= COMP_CSR_INMSEL_DAC2; break; - case STM32L4_COMP_INM_PIN_1: - stm32l4_configgpio(cmp == STM32L4_COMP1 ? GPIO_COMP1_INM_1 : + case STM32_COMP_INM_PIN_1: + stm32_configgpio(cmp == STM32_COMP1 ? GPIO_COMP1_INM_1 : GPIO_COMP2_INM_1); regval |= COMP_CSR_INMSEL_PIN1; break; - case STM32L4_COMP_INM_PIN_2: - stm32l4_configgpio(cmp == STM32L4_COMP1 ? GPIO_COMP1_INM_2 : + case STM32_COMP_INM_PIN_2: + stm32_configgpio(cmp == STM32_COMP1 ? GPIO_COMP1_INM_2 : GPIO_COMP2_INM_2); -#if defined(CONFIG_STM32L4_STM32L4X5) || defined(CONFIG_STM32L4_STM32L4X6) || \ - defined(CONFIG_STM32L4_STM32L4XR) +#if defined(CONFIG_STM32_STM32L4X5) || defined(CONFIG_STM32_STM32L4X6) || \ + defined(CONFIG_STM32_STM32L4XR) regval |= COMP_CSR_INMSEL_PIN2; #else regval |= COMP_CSR_INMSEL_INMESEL; @@ -443,25 +443,25 @@ static int stm32l4_compconfig(const struct comp_dev_s *dev) #endif break; -#if defined(CONFIG_STM32L4_STM32L4X3) - case STM32L4_COMP_INM_PIN_3: - stm32l4_configgpio(cmp == STM32L4_COMP1 ? GPIO_COMP1_INM_3 : +#if defined(CONFIG_STM32_STM32L4X3) + case STM32_COMP_INM_PIN_3: + stm32_configgpio(cmp == STM32_COMP1 ? GPIO_COMP1_INM_3 : GPIO_COMP2_INM_3); regval |= COMP_CSR_INMSEL_INMESEL; mask |= COMP_CSR_INMESEL_MASK; regval |= COMP_CSR_INMESEL_PIN3; break; - case STM32L4_COMP_INM_PIN_4: - stm32l4_configgpio(cmp == STM32L4_COMP1 ? GPIO_COMP1_INM_4 : + case STM32_COMP_INM_PIN_4: + stm32_configgpio(cmp == STM32_COMP1 ? GPIO_COMP1_INM_4 : GPIO_COMP2_INM_4); regval |= COMP_CSR_INMSEL_INMESEL; mask |= COMP_CSR_INMESEL_MASK; regval |= COMP_CSR_INMESEL_PIN4; break; - case STM32L4_COMP_INM_PIN_5: - stm32l4_configgpio(cmp == STM32L4_COMP1 ? GPIO_COMP1_INM_5 : + case STM32_COMP_INM_PIN_5: + stm32_configgpio(cmp == STM32_COMP1 ? GPIO_COMP1_INM_5 : GPIO_COMP2_INM_5); regval |= COMP_CSR_INMSEL_INMESEL; mask |= COMP_CSR_INMESEL_MASK; @@ -478,19 +478,19 @@ static int stm32l4_compconfig(const struct comp_dev_s *dev) mask |= COMP_CSR_HYST_MASK; switch (cfg->hyst) { - case STM32L4_COMP_HYST_NONE: + case STM32_COMP_HYST_NONE: regval |= COMP_CSR_HYST_NONE; break; - case STM32L4_COMP_HYST_LOW: + case STM32_COMP_HYST_LOW: regval |= COMP_CSR_HYST_LOW; break; - case STM32L4_COMP_HYST_MEDIUM: + case STM32_COMP_HYST_MEDIUM: regval |= COMP_CSR_HYST_MEDIUM; break; - case STM32L4_COMP_HYST_HIGH: + case STM32_COMP_HYST_HIGH: regval |= COMP_CSR_HYST_HIGH; break; @@ -503,15 +503,15 @@ static int stm32l4_compconfig(const struct comp_dev_s *dev) mask |= COMP_CSR_PWRMODE_MASK; switch (cfg->speed) { - case STM32L4_COMP_SPEED_HIGH: + case STM32_COMP_SPEED_HIGH: regval |= COMP_CSR_PWRMODE_HIGH; break; - case STM32L4_COMP_SPEED_MEDIUM: + case STM32_COMP_SPEED_MEDIUM: regval |= COMP_CSR_PWRMODE_MEDIUM; break; - case STM32L4_COMP_SPEED_LOW: + case STM32_COMP_SPEED_LOW: regval |= COMP_CSR_PWRMODE_LOW; break; @@ -539,18 +539,18 @@ static int stm32l4_compconfig(const struct comp_dev_s *dev) /* Enable */ - stm32l4_compenable(cfg, true); + stm32_compenable(cfg, true); /* Enable interrupt */ if (cfg->interrupt.cb && (cfg->interrupt.rising || cfg->interrupt.falling)) { - ret = stm32l4_exti_comp(cmp, cfg->interrupt.rising, + ret = stm32_exti_comp(cmp, cfg->interrupt.rising, cfg->interrupt.falling, 0, - stm32l4_exti_comp_isr, (void *)dev); + stm32_exti_comp_isr, (void *)dev); if (ret < 0) { - aerr("stm32l4_exti_comp failed ret = %d\n", ret); + aerr("stm32_exti_comp failed ret = %d\n", ret); return ERROR; } } @@ -561,7 +561,7 @@ static int stm32l4_compconfig(const struct comp_dev_s *dev) } /**************************************************************************** - * Name: stm32l4_compinitialize + * Name: stm32_compinitialize * * Description: * Initialize the COMP. @@ -579,8 +579,8 @@ static int stm32l4_compconfig(const struct comp_dev_s *dev) ****************************************************************************/ struct comp_dev_s * - stm32l4_compinitialize(int intf, - const struct stm32l4_comp_config_s *cfg) + stm32_compinitialize(int intf, + const struct stm32_comp_config_s *cfg) { struct comp_dev_s *dev; @@ -609,4 +609,4 @@ struct comp_dev_s * return dev; } -#endif /* CONFIG_STM32L4_COMP */ +#endif /* CONFIG_STM32_COMP */ diff --git a/arch/arm/src/stm32l4/stm32l4_comp.h b/arch/arm/src/stm32l4/stm32l4_comp.h index d862d14a9eef6..ecf645f2818ee 100644 --- a/arch/arm/src/stm32l4/stm32l4_comp.h +++ b/arch/arm/src/stm32l4/stm32l4_comp.h @@ -33,8 +33,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32L4_STM32L4_COMP_H -#define __ARCH_ARM_SRC_STM32L4_STM32L4_COMP_H +#ifndef __ARCH_ARM_SRC_STM32L4_STM32_COMP_H +#define __ARCH_ARM_SRC_STM32L4_STM32_COMP_H /**************************************************************************** * Included Files @@ -50,99 +50,99 @@ * Public Types ****************************************************************************/ -#if defined(CONFIG_STM32L4_STM32L4X3) +#if defined(CONFIG_STM32_STM32L4X3) /* Comparators */ -enum stm32l4_comp_e +enum stm32_comp_e { - STM32L4_COMP1, - STM32L4_COMP2, - STM32L4_COMP_NUM /* Number of comparators */ + STM32_COMP1, + STM32_COMP2, + STM32_COMP_NUM /* Number of comparators */ }; /* Plus input */ -enum stm32l4_comp_inp_e +enum stm32_comp_inp_e { - STM32L4_COMP_INP_PIN_1, /* COMP1: PC5, COMP2: PB4 */ - STM32L4_COMP_INP_PIN_2, /* COMP1: PB2, COMP2: PB6 */ - STM32L4_COMP_INP_PIN_3 /* COMP1: PA1, COMP2: PA3 */ + STM32_COMP_INP_PIN_1, /* COMP1: PC5, COMP2: PB4 */ + STM32_COMP_INP_PIN_2, /* COMP1: PB2, COMP2: PB6 */ + STM32_COMP_INP_PIN_3 /* COMP1: PA1, COMP2: PA3 */ }; /* Minus input */ -enum stm32l4_comp_inm_e +enum stm32_comp_inm_e { - STM32L4_COMP_INM_1_4_VREF, - STM32L4_COMP_INM_1_2_VREF, - STM32L4_COMP_INM_3_4_VREF, - STM32L4_COMP_INM_VREF, - STM32L4_COMP_INM_DAC_1, - STM32L4_COMP_INM_DAC_2, - STM32L4_COMP_INM_PIN_1, /* COMP1: PB1, COMP2: PB3 */ - STM32L4_COMP_INM_PIN_2, /* COMP1: PC4, COMP2: PB7 */ - STM32L4_COMP_INM_PIN_3, /* COMP1: PA0, COMP2: PA2 */ - STM32L4_COMP_INM_PIN_4, /* COMP1: PA4, COMP2: PA4 */ - STM32L4_COMP_INM_PIN_5 /* COMP1: PA5, COMP2: PA5 */ + STM32_COMP_INM_1_4_VREF, + STM32_COMP_INM_1_2_VREF, + STM32_COMP_INM_3_4_VREF, + STM32_COMP_INM_VREF, + STM32_COMP_INM_DAC_1, + STM32_COMP_INM_DAC_2, + STM32_COMP_INM_PIN_1, /* COMP1: PB1, COMP2: PB3 */ + STM32_COMP_INM_PIN_2, /* COMP1: PC4, COMP2: PB7 */ + STM32_COMP_INM_PIN_3, /* COMP1: PA0, COMP2: PA2 */ + STM32_COMP_INM_PIN_4, /* COMP1: PA4, COMP2: PA4 */ + STM32_COMP_INM_PIN_5 /* COMP1: PA5, COMP2: PA5 */ }; #else /* Comparators */ -enum stm32l4_comp_e +enum stm32_comp_e { - STM32L4_COMP1, - STM32L4_COMP2, - STM32L4_COMP_NUM /* Number of comparators */ + STM32_COMP1, + STM32_COMP2, + STM32_COMP_NUM /* Number of comparators */ }; /* Plus input */ -enum stm32l4_comp_inp_e +enum stm32_comp_inp_e { - STM32L4_COMP_INP_PIN_1, /* COMP1: PC5, COMP2: PB4 */ - STM32L4_COMP_INP_PIN_2 /* COMP1: PB2, COMP2: PB6 */ + STM32_COMP_INP_PIN_1, /* COMP1: PC5, COMP2: PB4 */ + STM32_COMP_INP_PIN_2 /* COMP1: PB2, COMP2: PB6 */ }; /* Minus input */ -enum stm32l4_comp_inm_e +enum stm32_comp_inm_e { - STM32L4_COMP_INM_1_4_VREF, - STM32L4_COMP_INM_1_2_VREF, - STM32L4_COMP_INM_3_4_VREF, - STM32L4_COMP_INM_VREF, - STM32L4_COMP_INM_DAC_1, - STM32L4_COMP_INM_DAC_2, - STM32L4_COMP_INM_PIN_1, /* COMP1: PB1, COMP2: PB3 */ - STM32L4_COMP_INM_PIN_2 /* COMP1: PC4, COMP2: PB7 */ + STM32_COMP_INM_1_4_VREF, + STM32_COMP_INM_1_2_VREF, + STM32_COMP_INM_3_4_VREF, + STM32_COMP_INM_VREF, + STM32_COMP_INM_DAC_1, + STM32_COMP_INM_DAC_2, + STM32_COMP_INM_PIN_1, /* COMP1: PB1, COMP2: PB3 */ + STM32_COMP_INM_PIN_2 /* COMP1: PC4, COMP2: PB7 */ }; #endif /* Hysteresis */ -enum stm32l4_comp_hyst_e +enum stm32_comp_hyst_e { - STM32L4_COMP_HYST_NONE, - STM32L4_COMP_HYST_LOW, - STM32L4_COMP_HYST_MEDIUM, - STM32L4_COMP_HYST_HIGH + STM32_COMP_HYST_NONE, + STM32_COMP_HYST_LOW, + STM32_COMP_HYST_MEDIUM, + STM32_COMP_HYST_HIGH }; /* Power/Speed Modes */ -enum stm32l4_comp_speed_e +enum stm32_comp_speed_e { - STM32L4_COMP_SPEED_HIGH, - STM32L4_COMP_SPEED_MEDIUM, - STM32L4_COMP_SPEED_LOW + STM32_COMP_SPEED_HIGH, + STM32_COMP_SPEED_MEDIUM, + STM32_COMP_SPEED_LOW }; /* Comparator configuration *************************************************/ -struct stm32l4_comp_config_s +struct stm32_comp_config_s { struct { @@ -151,10 +151,10 @@ struct stm32l4_comp_config_s bool falling; } interrupt; - uint8_t inp; /* Plus input pin (see enum stm32l4_comp_inp_e) */ - uint8_t inm; /* Minus input pin (see enum stm32l4_comp_inm_e) */ - uint8_t hyst; /* Hysteresis (see enum stm32l4_comp_hyst_e) */ - uint8_t speed; /* Speed (see stm32l4_comp_speed_e) */ + uint8_t inp; /* Plus input pin (see enum stm32_comp_inp_e) */ + uint8_t inm; /* Minus input pin (see enum stm32_comp_inm_e) */ + uint8_t hyst; /* Hysteresis (see enum stm32_comp_hyst_e) */ + uint8_t speed; /* Speed (see stm32_comp_speed_e) */ bool inverted; /* Invert output? */ uint32_t csr; /* Control and status register */ }; @@ -173,7 +173,7 @@ extern "C" #endif /**************************************************************************** - * Name: stm32l4_compinitialize + * Name: stm32_compinitialize * * Description: * Initialize the COMP. @@ -192,8 +192,8 @@ extern "C" ****************************************************************************/ struct -comp_dev_s *stm32l4_compinitialize(int intf, - const struct stm32l4_comp_config_s *cfg); +comp_dev_s *stm32_compinitialize(int intf, + const struct stm32_comp_config_s *cfg); #undef EXTERN #ifdef __cplusplus @@ -201,4 +201,4 @@ comp_dev_s *stm32l4_compinitialize(int intf, #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32L4_STM32L4_COMP_H */ +#endif /* __ARCH_ARM_SRC_STM32L4_STM32_COMP_H */ diff --git a/arch/arm/src/stm32l4/stm32l4_dac.c b/arch/arm/src/stm32l4/stm32l4_dac.c index a2c59beca1726..15cd9f3e4f57c 100644 --- a/arch/arm/src/stm32l4/stm32l4_dac.c +++ b/arch/arm/src/stm32l4/stm32l4_dac.c @@ -40,7 +40,7 @@ #include "arm_internal.h" #include "chip.h" -#include "stm32l4.h" +#include "stm32.h" #include "stm32l4_dac.h" #include "stm32l4_rcc.h" #include "stm32l4_dma.h" @@ -55,25 +55,25 @@ /* Up to 1 DAC interface for up to 2 channels are supported */ -#if STM32L4_NDAC > 2 +#if STM32_NDAC > 2 # warning "Extra DAC channels. Only DAC1 and DAC2 are supported" #endif -#if STM32L4_NDAC < 2 -# undef CONFIG_STM32L4_DAC2 -# undef CONFIG_STM32L4_DAC2_DMA -# undef CONFIG_STM32L4_DAC2_TIMER -# undef CONFIG_STM32L4_DAC2_TIMER_FREQUENCY +#if STM32_NDAC < 2 +# undef CONFIG_STM32_DAC2 +# undef CONFIG_STM32_DAC2_DMA +# undef CONFIG_STM32_DAC2_TIMER +# undef CONFIG_STM32_DAC2_TIMER_FREQUENCY #endif -#if STM32L4_NDAC < 1 -# undef CONFIG_STM32L4_DAC1 -# undef CONFIG_STM32L4_DAC1_DMA -# undef CONFIG_STM32L4_DAC1_TIMER -# undef CONFIG_STM32L4_DAC1_TIMER_FREQUENCY +#if STM32_NDAC < 1 +# undef CONFIG_STM32_DAC1 +# undef CONFIG_STM32_DAC1_DMA +# undef CONFIG_STM32_DAC1_TIMER +# undef CONFIG_STM32_DAC1_TIMER_FREQUENCY #endif -#if defined(CONFIG_STM32L4_DAC1) || defined(CONFIG_STM32L4_DAC2) +#if defined(CONFIG_STM32_DAC1) || defined(CONFIG_STM32_DAC2) /* DMA configuration. */ @@ -83,63 +83,63 @@ * supported by the driver. */ -#ifdef CONFIG_STM32L4_DAC1_DMA -# if !defined(CONFIG_STM32L4_DAC1_DMA_BUFFER_SIZE) || CONFIG_STM32L4_DAC1_DMA_BUFFER_SIZE < 1 -# define CONFIG_STM32L4_DAC1_DMA_BUFFER_SIZE 1 +#ifdef CONFIG_STM32_DAC1_DMA +# if !defined(CONFIG_STM32_DAC1_DMA_BUFFER_SIZE) || CONFIG_STM32_DAC1_DMA_BUFFER_SIZE < 1 +# define CONFIG_STM32_DAC1_DMA_BUFFER_SIZE 1 # endif -# if !defined(CONFIG_STM32L4_DAC1_TIMER) -# warning "A timer number must be specified in CONFIG_STM32L4_DAC1_TIMER" -# undef CONFIG_STM32L4_DAC1_DMA -# undef CONFIG_STM32L4_DAC1_TIMER_FREQUENCY -# elif !defined(CONFIG_STM32L4_DAC1_TIMER_FREQUENCY) || \ - (CONFIG_STM32L4_DAC1_TIMER_FREQUENCY < 1) -# warning "A timer frequency (>0) must be specified in CONFIG_STM32L4_DAC1_TIMER_FREQUENCY" -# undef CONFIG_STM32L4_DAC1_DMA -# undef CONFIG_STM32L4_DAC1_TIMER +# if !defined(CONFIG_STM32_DAC1_TIMER) +# warning "A timer number must be specified in CONFIG_STM32_DAC1_TIMER" +# undef CONFIG_STM32_DAC1_DMA +# undef CONFIG_STM32_DAC1_TIMER_FREQUENCY +# elif !defined(CONFIG_STM32_DAC1_TIMER_FREQUENCY) || \ + (CONFIG_STM32_DAC1_TIMER_FREQUENCY < 1) +# warning "A timer frequency (>0) must be specified in CONFIG_STM32_DAC1_TIMER_FREQUENCY" +# undef CONFIG_STM32_DAC1_DMA +# undef CONFIG_STM32_DAC1_TIMER # endif #endif -#ifdef CONFIG_STM32L4_DAC2_DMA -# if !defined(CONFIG_STM32L4_DAC2_DMA_BUFFER_SIZE) || CONFIG_STM32L4_DAC2_DMA_BUFFER_SIZE < 1 -# define CONFIG_STM32L4_DAC2_DMA_BUFFER_SIZE 1 +#ifdef CONFIG_STM32_DAC2_DMA +# if !defined(CONFIG_STM32_DAC2_DMA_BUFFER_SIZE) || CONFIG_STM32_DAC2_DMA_BUFFER_SIZE < 1 +# define CONFIG_STM32_DAC2_DMA_BUFFER_SIZE 1 # endif -# if !defined(CONFIG_STM32L4_DAC2_TIMER) -# warning "A timer number must be specified in CONFIG_STM32L4_DAC2_TIMER" -# undef CONFIG_STM32L4_DAC2_DMA -# undef CONFIG_STM32L4_DAC2_TIMER_FREQUENCY -# elif !defined(CONFIG_STM32L4_DAC2_TIMER_FREQUENCY) || \ - (CONFIG_STM32L4_DAC2_TIMER_FREQUENCY < 1) -# warning "A timer frequency (>0) must be specified in CONFIG_STM32L4_DAC2_TIMER_FREQUENCY" -# undef CONFIG_STM32L4_DAC2_DMA -# undef CONFIG_STM32L4_DAC2_TIMER +# if !defined(CONFIG_STM32_DAC2_TIMER) +# warning "A timer number must be specified in CONFIG_STM32_DAC2_TIMER" +# undef CONFIG_STM32_DAC2_DMA +# undef CONFIG_STM32_DAC2_TIMER_FREQUENCY +# elif !defined(CONFIG_STM32_DAC2_TIMER_FREQUENCY) || \ + (CONFIG_STM32_DAC2_TIMER_FREQUENCY < 1) +# warning "A timer frequency (>0) must be specified in CONFIG_STM32_DAC2_TIMER_FREQUENCY" +# undef CONFIG_STM32_DAC2_DMA +# undef CONFIG_STM32_DAC2_TIMER # endif #endif /* Select DMA channels, favor DMA1 if configured. */ #undef HAVE_DMA -#ifdef CONFIG_STM32L4_DAC1_DMA -# if defined(CONFIG_STM32L4_DMAMUX1) && defined(CONFIG_STM32L4_DMA1) +#ifdef CONFIG_STM32_DAC1_DMA +# if defined(CONFIG_STM32_DMAMUX1) && defined(CONFIG_STM32_DMA1) # define DAC1_DMA_CHAN DMAMAP_DAC1_0 -# elif defined(CONFIG_STM32L4_DMAMUX1) && defined(CONFIG_STM32L4_DMA2) +# elif defined(CONFIG_STM32_DMAMUX1) && defined(CONFIG_STM32_DMA2) # define DAC1_DMA_CHAN DMAMAP_DAC1_1 -# elif defined(CONFIG_STM32L4_DMA1) +# elif defined(CONFIG_STM32_DMA1) # define DAC1_DMA_CHAN DMACHAN_DAC1_1 -# elif defined(CONFIG_STM32L4_DMA2) +# elif defined(CONFIG_STM32_DMA2) # define DAC1_DMA_CHAN DMACHAN_DAC1_2 # else # error "No DMA channel for DAC1" # endif # define HAVE_DMA #endif -#ifdef CONFIG_STM32L4_DAC2_DMA -# if defined(CONFIG_STM32L4_DMAMUX1) && defined(CONFIG_STM32L4_DMA1) +#ifdef CONFIG_STM32_DAC2_DMA +# if defined(CONFIG_STM32_DMAMUX1) && defined(CONFIG_STM32_DMA1) # define DAC2_DMA_CHAN DMAMAP_DAC2_0 -# elif defined(CONFIG_STM32L4_DMAMUX1) && defined(CONFIG_STM32L4_DMA2) +# elif defined(CONFIG_STM32_DMAMUX1) && defined(CONFIG_STM32_DMA2) # define DAC2_DMA_CHAN DMAMAP_DAC2_1 -# elif defined(CONFIG_STM32L4_DMA1) +# elif defined(CONFIG_STM32_DMA1) # define DAC2_DMA_CHAN DMACHAN_DAC2_1 -# elif defined(CONFIG_STM32L4_DMA2) +# elif defined(CONFIG_STM32_DMA2) # define DAC2_DMA_CHAN DMACHAN_DAC2_2 # else # error "No DMA channel for DAC2" @@ -171,113 +171,113 @@ #undef NEED_TIM2 #undef NEED_TIM4 -#ifdef CONFIG_STM32L4_DAC1_DMA -# if CONFIG_STM32L4_DAC1_TIMER == 6 -# ifndef CONFIG_STM32L4_TIM6_DAC -# error "CONFIG_STM32L4_TIM6_DAC required for DAC1" +#ifdef CONFIG_STM32_DAC1_DMA +# if CONFIG_STM32_DAC1_TIMER == 6 +# ifndef CONFIG_STM32_TIM6_DAC +# error "CONFIG_STM32_TIM6_DAC required for DAC1" # endif # define NEED_TIM6 # define DAC1_TSEL_VALUE DAC_CR_TSEL_TIM6 -# define DAC1_TIMER_BASE STM32L4_TIM6_BASE -# define DAC1_TIMER_PCLK_FREQUENCY STM32L4_PCLK1_FREQUENCY -# elif CONFIG_STM32L4_DAC1_TIMER == 8 -# ifndef CONFIG_STM32L4_TIM8_DAC -# error "CONFIG_STM32L4_TIM8_DAC required for DAC1" +# define DAC1_TIMER_BASE STM32_TIM6_BASE +# define DAC1_TIMER_PCLK_FREQUENCY STM32_PCLK1_FREQUENCY +# elif CONFIG_STM32_DAC1_TIMER == 8 +# ifndef CONFIG_STM32_TIM8_DAC +# error "CONFIG_STM32_TIM8_DAC required for DAC1" # endif # define NEED_TIM8 # define DAC1_TSEL_VALUE DAC_CR_TSEL_TIM8 -# define DAC1_TIMER_BASE STM32L4_TIM8_BASE -# define DAC1_TIMER_PCLK_FREQUENCY STM32L4_PCLK2_FREQUENCY -# elif CONFIG_STM32L4_DAC1_TIMER == 7 -# ifndef CONFIG_STM32L4_TIM7_DAC -# error "CONFIG_STM32L4_TIM7_DAC required for DAC1" +# define DAC1_TIMER_BASE STM32_TIM8_BASE +# define DAC1_TIMER_PCLK_FREQUENCY STM32_PCLK2_FREQUENCY +# elif CONFIG_STM32_DAC1_TIMER == 7 +# ifndef CONFIG_STM32_TIM7_DAC +# error "CONFIG_STM32_TIM7_DAC required for DAC1" # endif # define NEED_TIM7 # define DAC1_TSEL_VALUE DAC_CR_TSEL_TIM7 -# define DAC1_TIMER_BASE STM32L4_TIM7_BASE -# elif CONFIG_STM32L4_DAC1_TIMER == 5 -# ifndef CONFIG_STM32L4_TIM5_DAC -# error "CONFIG_STM32L4_TIM5_DAC required for DAC1" +# define DAC1_TIMER_BASE STM32_TIM7_BASE +# elif CONFIG_STM32_DAC1_TIMER == 5 +# ifndef CONFIG_STM32_TIM5_DAC +# error "CONFIG_STM32_TIM5_DAC required for DAC1" # endif # define NEED_TIM5 # define DAC1_TSEL_VALUE DAC_CR_TSEL_TIM5 -# define DAC1_TIMER_BASE STM32L4_TIM5_BASE -# define DAC1_TIMER_PCLK_FREQUENCY STM32L4_PCLK1_FREQUENCY -# elif CONFIG_STM32L4_DAC1_TIMER == 2 -# ifndef CONFIG_STM32L4_TIM2_DAC -# error "CONFIG_STM32L4_TIM2_DAC required for DAC1" +# define DAC1_TIMER_BASE STM32_TIM5_BASE +# define DAC1_TIMER_PCLK_FREQUENCY STM32_PCLK1_FREQUENCY +# elif CONFIG_STM32_DAC1_TIMER == 2 +# ifndef CONFIG_STM32_TIM2_DAC +# error "CONFIG_STM32_TIM2_DAC required for DAC1" # endif # define NEED_TIM2 # define DAC1_TSEL_VALUE DAC_CR_TSEL_TIM2 -# define DAC1_TIMER_BASE STM32L4_TIM2_BASE -# define DAC1_TIMER_PCLK_FREQUENCY STM32L4_PCLK1_FREQUENCY -# elif CONFIG_STM32L4_DAC1_TIMER == 4 -# ifndef CONFIG_STM32L4_TIM4_DAC -# error "CONFIG_STM32L4_TIM4_DAC required for DAC1" +# define DAC1_TIMER_BASE STM32_TIM2_BASE +# define DAC1_TIMER_PCLK_FREQUENCY STM32_PCLK1_FREQUENCY +# elif CONFIG_STM32_DAC1_TIMER == 4 +# ifndef CONFIG_STM32_TIM4_DAC +# error "CONFIG_STM32_TIM4_DAC required for DAC1" # endif # define NEED_TIM4 # define DAC1_TSEL_VALUE DAC_CR_TSEL_TIM4 -# define DAC1_TIMER_BASE STM32L4_TIM4_BASE -# define DAC1_TIMER_PCLK_FREQUENCY STM32L4_PCLK1_FREQUENCY +# define DAC1_TIMER_BASE STM32_TIM4_BASE +# define DAC1_TIMER_PCLK_FREQUENCY STM32_PCLK1_FREQUENCY # else -# error "Unsupported CONFIG_STM32L4_DAC1_TIMER" +# error "Unsupported CONFIG_STM32_DAC1_TIMER" # endif #else # define DAC1_TSEL_VALUE DAC_CR_TSEL_SW #endif -#ifdef CONFIG_STM32L4_DAC2_DMA -# if CONFIG_STM32L4_DAC2_TIMER == 6 -# ifndef CONFIG_STM32L4_TIM6_DAC -# error "CONFIG_STM32L4_TIM6_DAC required for DAC2" +#ifdef CONFIG_STM32_DAC2_DMA +# if CONFIG_STM32_DAC2_TIMER == 6 +# ifndef CONFIG_STM32_TIM6_DAC +# error "CONFIG_STM32_TIM6_DAC required for DAC2" # endif # define DAC2_TSEL_VALUE DAC_CR_TSEL_TIM6 -# define DAC2_TIMER_BASE STM32L4_TIM6_BASE -# define DAC2_TIMER_PCLK_FREQUENCY STM32L4_PCLK1_FREQUENCY -# elif CONFIG_STM32L4_DAC2_TIMER == 8 -# ifndef CONFIG_STM32L4_TIM8_DAC -# error "CONFIG_STM32L4_TIM8_DAC required for DAC2" +# define DAC2_TIMER_BASE STM32_TIM6_BASE +# define DAC2_TIMER_PCLK_FREQUENCY STM32_PCLK1_FREQUENCY +# elif CONFIG_STM32_DAC2_TIMER == 8 +# ifndef CONFIG_STM32_TIM8_DAC +# error "CONFIG_STM32_TIM8_DAC required for DAC2" # endif # define DAC2_TSEL_VALUE DAC_CR_TSEL_TIM8 -# define DAC2_TIMER_BASE STM32L4_TIM8_BASE -# define DAC2_TIMER_PCLK_FREQUENCY STM32L4_PCLK2_FREQUENCY -# elif CONFIG_STM32L4_DAC2_TIMER == 7 -# ifndef CONFIG_STM32L4_TIM7_DAC -# error "CONFIG_STM32L4_TIM7_DAC required for DAC2" +# define DAC2_TIMER_BASE STM32_TIM8_BASE +# define DAC2_TIMER_PCLK_FREQUENCY STM32_PCLK2_FREQUENCY +# elif CONFIG_STM32_DAC2_TIMER == 7 +# ifndef CONFIG_STM32_TIM7_DAC +# error "CONFIG_STM32_TIM7_DAC required for DAC2" # endif # define DAC2_TSEL_VALUE DAC_CR_TSEL_TIM7 -# define DAC2_TIMER_BASE STM32L4_TIM7_BASE -# define DAC2_TIMER_PCLK_FREQUENCY STM32L4_PCLK1_FREQUENCY -# elif CONFIG_STM32L4_DAC2_TIMER == 5 -# ifndef CONFIG_STM32L4_TIM5_DAC -# error "CONFIG_STM32L4_TIM5_DAC required for DAC2" +# define DAC2_TIMER_BASE STM32_TIM7_BASE +# define DAC2_TIMER_PCLK_FREQUENCY STM32_PCLK1_FREQUENCY +# elif CONFIG_STM32_DAC2_TIMER == 5 +# ifndef CONFIG_STM32_TIM5_DAC +# error "CONFIG_STM32_TIM5_DAC required for DAC2" # endif # define DAC2_TSEL_VALUE DAC_CR_TSEL_TIM5 -# define DAC2_TIMER_BASE STM32L4_TIM5_BASE -# define DAC2_TIMER_PCLK_FREQUENCY STM32L4_PCLK1_FREQUENCY -# elif CONFIG_STM32L4_DAC2_TIMER == 2 -# ifndef CONFIG_STM32L4_TIM2_DAC -# error "CONFIG_STM32L4_TIM2_DAC required for DAC2" +# define DAC2_TIMER_BASE STM32_TIM5_BASE +# define DAC2_TIMER_PCLK_FREQUENCY STM32_PCLK1_FREQUENCY +# elif CONFIG_STM32_DAC2_TIMER == 2 +# ifndef CONFIG_STM32_TIM2_DAC +# error "CONFIG_STM32_TIM2_DAC required for DAC2" # endif # define DAC2_TSEL_VALUE DAC_CR_TSEL_TIM2 -# define DAC2_TIMER_BASE STM32L4_TIM2_BASE -# define DAC2_TIMER_PCLK_FREQUENCY STM32L4_PCLK1_FREQUENCY -# elif CONFIG_STM32L4_DAC2_TIMER == 4 -# ifndef CONFIG_STM32L4_TIM4_DAC -# error "CONFIG_STM32L4_TIM4_DAC required for DAC2" +# define DAC2_TIMER_BASE STM32_TIM2_BASE +# define DAC2_TIMER_PCLK_FREQUENCY STM32_PCLK1_FREQUENCY +# elif CONFIG_STM32_DAC2_TIMER == 4 +# ifndef CONFIG_STM32_TIM4_DAC +# error "CONFIG_STM32_TIM4_DAC required for DAC2" # endif # define DAC2_TSEL_VALUE DAC_CR_TSEL_TIM4 -# define DAC2_TIMER_BASE STM32L4_TIM4_BASE -# define DAC2_TIMER_PCLK_FREQUENCY STM32L4_PCLK1_FREQUENCY +# define DAC2_TIMER_BASE STM32_TIM4_BASE +# define DAC2_TIMER_PCLK_FREQUENCY STM32_PCLK1_FREQUENCY # else -# error "Unsupported CONFIG_STM32L4_DAC2_TIMER" +# error "Unsupported CONFIG_STM32_DAC2_TIMER" # endif #else # define DAC2_TSEL_VALUE DAC_CR_TSEL_SW #endif /* Calculate timer divider values based upon DACn_TIMER_PCLK_FREQUENCY and - * CONFIG_STM32L4_DACn_TIMER_FREQUENCY. + * CONFIG_STM32_DACn_TIMER_FREQUENCY. */ #warning "Missing Logic" @@ -307,7 +307,7 @@ struct stm32_dac_s struct stm32_chan_s { -#ifdef CONFIG_STM32L4_DAC_LL_OPS +#ifdef CONFIG_STM32_DAC_LL_OPS const struct stm32_dac_ops_s *llops; /* Low-level DAC ops */ #endif uint8_t inuse : 1; /* True, the driver is in use and not available */ @@ -365,7 +365,7 @@ static int dac_timinit(struct stm32_chan_s *chan); static int dac_chaninit(struct stm32_chan_s *chan); static void dac_blockinit(void); -#ifdef CONFIG_STM32L4_DAC_LL_OPS +#ifdef CONFIG_STM32_DAC_LL_OPS static void dac_llops_enable(struct stm32_dac_dev_s *dev, bool enabled); static void dac_llops_writedro(struct stm32_dac_dev_s *dev, uint16_t data); #ifdef HAVE_DMA @@ -373,7 +373,7 @@ static void dac_llops_startdma(struct stm32_dac_dev_s *dev); static void dac_llops_stopdma(struct stm32_dac_dev_s *dev); #endif static void dac_llops_dumpregs(struct stm32_dac_dev_s *dev); -#endif /* CONFIG_STM32L4_DAC_LL_OPS */ +#endif /* CONFIG_STM32_DAC_LL_OPS */ /**************************************************************************** * Private Data @@ -391,7 +391,7 @@ static const struct dac_ops_s g_dacops = /* Publicly visible DAC lower-half operations */ -#ifdef CONFIG_STM32L4_DAC_LL_OPS +#ifdef CONFIG_STM32_DAC_LL_OPS static const struct stm32_dac_ops_s g_dac_llops = { .enable = dac_llops_enable, @@ -402,37 +402,37 @@ static const struct stm32_dac_ops_s g_dac_llops = #endif .dump_regs = dac_llops_dumpregs }; -#endif /* CONFIG_STM32L4_DAC_LL_OPS */ +#endif /* CONFIG_STM32_DAC_LL_OPS */ -#ifdef CONFIG_STM32L4_DAC1 +#ifdef CONFIG_STM32_DAC1 /* Channel 1 */ -#ifdef CONFIG_STM32L4_DAC1_DMA -uint16_t stm32l4_dac1_dmabuffer[CONFIG_STM32L4_DAC1_DMA_BUFFER_SIZE]; +#ifdef CONFIG_STM32_DAC1_DMA +uint16_t stm32_dac1_dmabuffer[CONFIG_STM32_DAC1_DMA_BUFFER_SIZE]; #endif static struct stm32_chan_s g_dac1priv = { -#ifdef CONFIG_STM32L4_DAC_LL_OPS +#ifdef CONFIG_STM32_DAC_LL_OPS .llops = &g_dac_llops, #endif .intf = 0, -#ifdef CONFIG_STM32L4_DAC1_OUTPUT_ADC +#ifdef CONFIG_STM32_DAC1_OUTPUT_ADC .pin = 0xffffffffu, #else .pin = GPIO_DAC1_OUT, #endif - .dro = STM32L4_DAC_DHR12R1, - .cr = STM32L4_DAC_CR, -#ifdef CONFIG_STM32L4_DAC1_DMA + .dro = STM32_DAC_DHR12R1, + .cr = STM32_DAC_CR, +#ifdef CONFIG_STM32_DAC1_DMA .hasdma = 1, .dmachan = DAC1_DMA_CHAN, - .buffer_len = CONFIG_STM32L4_DAC1_DMA_BUFFER_SIZE, - .dmabuffer = stm32l4_dac1_dmabuffer, - .timer = CONFIG_STM32L4_DAC1_TIMER, + .buffer_len = CONFIG_STM32_DAC1_DMA_BUFFER_SIZE, + .dmabuffer = stm32_dac1_dmabuffer, + .timer = CONFIG_STM32_DAC1_TIMER, .tsel = DAC1_TSEL_VALUE, .tbase = DAC1_TIMER_BASE, - .tfrequency = CONFIG_STM32L4_DAC1_TIMER_FREQUENCY, + .tfrequency = CONFIG_STM32_DAC1_TIMER_FREQUENCY, #endif }; @@ -442,37 +442,37 @@ static struct dac_dev_s g_dac1dev = .ad_priv = &g_dac1priv, }; -#endif /* CONFIG_STM32L4_DAC1 */ +#endif /* CONFIG_STM32_DAC1 */ -#ifdef CONFIG_STM32L4_DAC2 +#ifdef CONFIG_STM32_DAC2 /* Channel 2 */ -#ifdef CONFIG_STM32L4_DAC2_DMA -uint16_t stm32l4_dac2_dmabuffer[CONFIG_STM32L4_DAC2_DMA_BUFFER_SIZE]; +#ifdef CONFIG_STM32_DAC2_DMA +uint16_t stm32_dac2_dmabuffer[CONFIG_STM32_DAC2_DMA_BUFFER_SIZE]; #endif static struct stm32_chan_s g_dac2priv = { -#ifdef CONFIG_STM32L4_DAC_LL_OPS +#ifdef CONFIG_STM32_DAC_LL_OPS .llops = &g_dac_llops, #endif .intf = 1, -#ifdef CONFIG_STM32L4_DAC2_OUTPUT_ADC +#ifdef CONFIG_STM32_DAC2_OUTPUT_ADC .pin = 0xffffffffu, #else .pin = GPIO_DAC2_OUT, #endif - .dro = STM32L4_DAC_DHR12R2, - .cr = STM32L4_DAC_CR, -#ifdef CONFIG_STM32L4_DAC2_DMA + .dro = STM32_DAC_DHR12R2, + .cr = STM32_DAC_CR, +#ifdef CONFIG_STM32_DAC2_DMA .hasdma = 1, .dmachan = DAC2_DMA_CHAN, - .buffer_len = CONFIG_STM32L4_DAC2_DMA_BUFFER_SIZE, - .dmabuffer = stm32l4_dac2_dmabuffer, - .timer = CONFIG_STM32L4_DAC2_TIMER, + .buffer_len = CONFIG_STM32_DAC2_DMA_BUFFER_SIZE, + .dmabuffer = stm32_dac2_dmabuffer, + .timer = CONFIG_STM32_DAC2_TIMER, .tsel = DAC2_TSEL_VALUE, .tbase = DAC2_TIMER_BASE, - .tfrequency = CONFIG_STM32L4_DAC2_TIMER_FREQUENCY, + .tfrequency = CONFIG_STM32_DAC2_TIMER_FREQUENCY, #endif }; @@ -482,7 +482,7 @@ static struct dac_dev_s g_dac2dev = .ad_priv = &g_dac2priv, }; -#endif /* CONFIG_STM32L4_DAC2 */ +#endif /* CONFIG_STM32_DAC2 */ static struct stm32_dac_s g_dacblock; @@ -507,11 +507,11 @@ static struct stm32_dac_s g_dacblock; static uint32_t dac_getreg(struct stm32_chan_s *priv, int offset) { - return getreg32(STM32L4_DAC_BASE + offset); + return getreg32(STM32_DAC_BASE + offset); } /**************************************************************************** - * Name: stm32l4_dac_modify_cr + * Name: stm32_dac_modify_cr * * Description: * Modify the contents of the DAC control register. @@ -526,13 +526,13 @@ static uint32_t dac_getreg(struct stm32_chan_s *priv, int offset) * ****************************************************************************/ -static inline void stm32l4_dac_modify_cr(struct stm32_chan_s *chan, +static inline void stm32_dac_modify_cr(struct stm32_chan_s *chan, uint32_t clearbits, uint32_t setbits) { unsigned int shift; - /* DAC channels 1 and 2 share the STM32L4_DAC[1]_CR control register. If + /* DAC channels 1 and 2 share the STM32_DAC[1]_CR control register. If * future chips have DAC channel 3 (and perhaps channel 4) they likely have * their own register like in STM32. In either case, bit 0 of the interface * number provides the correct shift. @@ -546,7 +546,7 @@ static inline void stm32l4_dac_modify_cr(struct stm32_chan_s *chan, } /**************************************************************************** - * Name: stm32l4_dac_modify_mcr + * Name: stm32_dac_modify_mcr * * Description: * Modify the contents of the DAC mode register. @@ -561,13 +561,13 @@ static inline void stm32l4_dac_modify_cr(struct stm32_chan_s *chan, * ****************************************************************************/ -static inline void stm32l4_dac_modify_mcr(struct stm32_chan_s *chan, +static inline void stm32_dac_modify_mcr(struct stm32_chan_s *chan, uint32_t clearbits, uint32_t setbits) { unsigned int shift; - /* DAC channels 1 and 2 share the STM32L4_DAC_MCR control register. + /* DAC channels 1 and 2 share the STM32_DAC_MCR control register. * Bit 0 of the interface number provides the correct shift. * * Bit 0 = 0: Shift = 0 @@ -575,7 +575,7 @@ static inline void stm32l4_dac_modify_mcr(struct stm32_chan_s *chan, */ shift = (chan->intf & 1) << 4; - modifyreg32(STM32L4_DAC_MCR, clearbits << shift, setbits << shift); + modifyreg32(STM32_DAC_MCR, clearbits << shift, setbits << shift); } /**************************************************************************** @@ -588,10 +588,10 @@ static void dac_dumpregs(struct stm32_chan_s *priv) ainfo("CR: 0x%08" PRIx32 " SWTRGR: 0x%08" PRIx32 "SR: 0x%08" PRIx32 " MCR: 0x%08" PRIx32 "\n", - dac_getreg(priv, STM32L4_DAC_CR_OFFSET), - dac_getreg(priv, STM32L4_DAC_SWTRIGR_OFFSET), - dac_getreg(priv, STM32L4_DAC_SR_OFFSET), - dac_getreg(priv, STM32L4_DAC_MCR_OFFSET)); + dac_getreg(priv, STM32_DAC_CR_OFFSET), + dac_getreg(priv, STM32_DAC_SWTRIGR_OFFSET), + dac_getreg(priv, STM32_DAC_SR_OFFSET), + dac_getreg(priv, STM32_DAC_MCR_OFFSET)); } /**************************************************************************** @@ -755,12 +755,12 @@ static void dac_dmatxcallback(DMA_HANDLE handle, uint8_t isr, switch (chan->intf) { -#ifdef CONFIG_STM32L4_DAC1 +#ifdef CONFIG_STM32_DAC1 case 0: dev = &g_dac1dev; break; #endif -#ifdef CONFIG_STM32L4_DAC2 +#ifdef CONFIG_STM32_DAC2 case 1: dev = &g_dac2dev; break; @@ -807,7 +807,7 @@ static int dac_send(struct dac_dev_s *dev, struct dac_msg_s *msg) /* Enable DAC Channel */ - stm32l4_dac_modify_cr(chan, 0, DAC_CR_EN); + stm32_dac_modify_cr(chan, 0, DAC_CR_EN); #ifdef HAVE_DMA if (chan->hasdma) @@ -843,17 +843,17 @@ static int dac_send(struct dac_dev_s *dev, struct dac_msg_s *msg) * - Peripheral Burst: single */ - stm32l4_dmasetup(chan->dma, chan->dro, (uint32_t)chan->dmabuffer, + stm32_dmasetup(chan->dma, chan->dro, (uint32_t)chan->dmabuffer, chan->buffer_len, DAC_DMA_CONTROL_WORD); /* Start the DMA */ chan->result = -EBUSY; - stm32l4_dmastart(chan->dma, dac_dmatxcallback, chan, false); + stm32_dmastart(chan->dma, dac_dmatxcallback, chan, false); /* Enable DMA for DAC Channel */ - stm32l4_dac_modify_cr(chan, 0, DAC_CR_DMAEN); + stm32_dac_modify_cr(chan, 0, DAC_CR_DMAEN); } else #endif @@ -867,7 +867,7 @@ static int dac_send(struct dac_dev_s *dev, struct dac_msg_s *msg) /* Reset counters (generate an update) */ #ifdef HAVE_DMA - tim_modifyreg(chan, STM32L4_GTIM_EGR_OFFSET, 0, GTIM_EGR_UG); + tim_modifyreg(chan, STM32_GTIM_EGR_OFFSET, 0, GTIM_EGR_UG); #endif return OK; } @@ -923,7 +923,7 @@ static int dac_timinit(struct stm32_chan_s *chan) * default) will be enabled */ - regaddr = STM32L4_RCC_APB1ENR1; + regaddr = STM32_RCC_APB1ENR1; switch (chan->timer) { @@ -965,7 +965,7 @@ static int dac_timinit(struct stm32_chan_s *chan) #endif #ifdef NEED_TIM8 case 8: - regaddr = STM32L4_RCC_APB2ENR; + regaddr = STM32_RCC_APB2ENR; setbits = RCC_APB2ENR_TIM8EN; pclk = BOARD_TIM8_FREQUENCY; break; @@ -1036,26 +1036,26 @@ static int dac_timinit(struct stm32_chan_s *chan) /* Set the reload and prescaler values */ - tim_putreg(chan, STM32L4_GTIM_ARR_OFFSET, (uint16_t)reload); - tim_putreg(chan, STM32L4_GTIM_PSC_OFFSET, (uint16_t)(prescaler - 1)); + tim_putreg(chan, STM32_GTIM_ARR_OFFSET, (uint16_t)reload); + tim_putreg(chan, STM32_GTIM_PSC_OFFSET, (uint16_t)(prescaler - 1)); /* Count mode up, auto reload */ - tim_modifyreg(chan, STM32L4_GTIM_CR1_OFFSET, 0, GTIM_CR1_ARPE); + tim_modifyreg(chan, STM32_GTIM_CR1_OFFSET, 0, GTIM_CR1_ARPE); /* Selection TRGO selection: update */ - tim_modifyreg(chan, STM32L4_GTIM_CR2_OFFSET, GTIM_CR2_MMS_MASK, + tim_modifyreg(chan, STM32_GTIM_CR2_OFFSET, GTIM_CR2_MMS_MASK, GTIM_CR2_MMS_UPDATE); /* Update DMA request enable ???? */ #if 0 - tim_modifyreg(chan, STM32L4_GTIM_DIER_OFFSET, 0, GTIM_DIER_UDE); + tim_modifyreg(chan, STM32_GTIM_DIER_OFFSET, 0, GTIM_DIER_UDE); #endif /* Enable the counter */ - tim_modifyreg(chan, STM32L4_GTIM_CR1_OFFSET, 0, GTIM_CR1_CEN); + tim_modifyreg(chan, STM32_GTIM_CR1_OFFSET, 0, GTIM_CR1_CEN); return OK; } #endif @@ -1098,7 +1098,7 @@ static int dac_chaninit(struct stm32_chan_s *chan) if (chan->pin != 0xffffffffu) { - stm32l4_configgpio(chan->pin); + stm32_configgpio(chan->pin); } /* DAC channel configuration: @@ -1110,7 +1110,7 @@ static int dac_chaninit(struct stm32_chan_s *chan) /* Disable before change */ - stm32l4_dac_modify_cr(chan, DAC_CR_EN, 0); + stm32_dac_modify_cr(chan, DAC_CR_EN, 0); clearbits = DAC_CR_TSEL_MASK | DAC_CR_MAMP_MASK | @@ -1119,7 +1119,7 @@ static int dac_chaninit(struct stm32_chan_s *chan) chan->tsel | /* Set trigger source (SW or timer TRGO event) */ DAC_CR_MAMP_AMP1 | /* Set waveform characteristics */ DAC_CR_WAVE_DISABLED; /* Set no noise */ - stm32l4_dac_modify_cr(chan, clearbits, setbits); + stm32_dac_modify_cr(chan, clearbits, setbits); /* Enable output buffer or route DAC output to on-chip peripherals (ADC) */ @@ -1133,7 +1133,7 @@ static int dac_chaninit(struct stm32_chan_s *chan) setbits = DAC_MCR_MODE_IN; } - stm32l4_dac_modify_mcr(chan, clearbits, setbits); + stm32_dac_modify_mcr(chan, clearbits, setbits); #ifdef HAVE_DMA /* Determine if DMA is supported by this channel */ @@ -1144,11 +1144,11 @@ static int dac_chaninit(struct stm32_chan_s *chan) /* Yes.. DAC trigger enable */ - stm32l4_dac_modify_cr(chan, 0, DAC_CR_TEN); + stm32_dac_modify_cr(chan, 0, DAC_CR_TEN); /* Allocate a DMA channel */ - chan->dma = stm32l4_dmachannel(chan->dmachan); + chan->dma = stm32_dmachannel(chan->dmachan); if (!chan->dma) { aerr("ERROR: Failed to allocate a DMA channel\n"); @@ -1161,7 +1161,7 @@ static int dac_chaninit(struct stm32_chan_s *chan) if (ret < 0) { aerr("ERROR: Failed to initialize the DMA timer: %d\n", ret); - stm32l4_dmafree(chan->dma); + stm32_dmafree(chan->dma); return ret; } } @@ -1200,14 +1200,14 @@ static void dac_blockinit(void) /* Put the entire DAC block in reset state */ flags = enter_critical_section(); - regval = getreg32(STM32L4_RCC_APB1RSTR1); + regval = getreg32(STM32_RCC_APB1RSTR1); regval |= RCC_APB1RSTR1_DAC1RST; - putreg32(regval, STM32L4_RCC_APB1RSTR1); + putreg32(regval, STM32_RCC_APB1RSTR1); /* Take the DAC out of reset state */ regval &= ~RCC_APB1RSTR1_DAC1RST; - putreg32(regval, STM32L4_RCC_APB1RSTR1); + putreg32(regval, STM32_RCC_APB1RSTR1); leave_critical_section(flags); /* Mark the DAC block as initialized */ @@ -1215,7 +1215,7 @@ static void dac_blockinit(void) g_dacblock.init = 1; } -#ifdef CONFIG_STM32L4_DAC_LL_OPS +#ifdef CONFIG_STM32_DAC_LL_OPS /**************************************************************************** * Name: dac_llops_enable @@ -1229,11 +1229,11 @@ static void dac_llops_enable(struct stm32_dac_dev_s *dev, bool enabled) if (enabled) { - stm32l4_dac_modify_cr(priv, 0, DAC_CR_EN); + stm32_dac_modify_cr(priv, 0, DAC_CR_EN); } else { - stm32l4_dac_modify_cr(priv, DAC_CR_EN, 0); + stm32_dac_modify_cr(priv, DAC_CR_EN, 0); } } @@ -1272,21 +1272,21 @@ static void dac_llops_startdma(struct stm32_dac_dev_s *dev) * - Peripheral Burst: single */ - stm32l4_dmasetup(priv->dma, priv->dro, (uint32_t)priv->dmabuffer, + stm32_dmasetup(priv->dma, priv->dro, (uint32_t)priv->dmabuffer, priv->buffer_len, DAC_DMA_CONTROL_WORD); /* Start the DMA */ priv->result = -EBUSY; - stm32l4_dmastart(priv->dma, dac_dmatxcallback, priv, false); + stm32_dmastart(priv->dma, dac_dmatxcallback, priv, false); /* Enable DMA for DAC Channel */ - stm32l4_dac_modify_cr(priv, 0, DAC_CR_DMAEN); + stm32_dac_modify_cr(priv, 0, DAC_CR_DMAEN); /* Reset counters (generate an update) */ - tim_modifyreg(priv, STM32L4_GTIM_EGR_OFFSET, 0, GTIM_EGR_UG); + tim_modifyreg(priv, STM32_GTIM_EGR_OFFSET, 0, GTIM_EGR_UG); } /**************************************************************************** @@ -1300,11 +1300,11 @@ static void dac_llops_stopdma(struct stm32_dac_dev_s *dev) /* Stop the DMA */ priv->result = -EBUSY; - stm32l4_dmastop(priv->dma); + stm32_dmastop(priv->dma); /* Enable DMA for DAC Channel */ - stm32l4_dac_modify_cr(priv, 0, DAC_CR_DMAEN); + stm32_dac_modify_cr(priv, 0, DAC_CR_DMAEN); } #endif @@ -1319,14 +1319,14 @@ static void dac_llops_dumpregs(struct stm32_dac_dev_s *dev) dac_dumpregs(priv); } -#endif /* CONFIG_STM32L4_DAC_LL_OPS */ +#endif /* CONFIG_STM32_DAC_LL_OPS */ /**************************************************************************** * Public Functions ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_dacinitialize + * Name: stm32_dacinitialize * * Description: * Initialize the DAC. @@ -1343,7 +1343,7 @@ static void dac_llops_dumpregs(struct stm32_dac_dev_s *dev) * ****************************************************************************/ -struct dac_dev_s *stm32l4_dacinitialize(int intf) +struct dac_dev_s *stm32_dacinitialize(int intf) { struct dac_dev_s *dev; struct stm32_chan_s *chan; @@ -1351,13 +1351,13 @@ struct dac_dev_s *stm32l4_dacinitialize(int intf) switch (intf) { -#ifdef CONFIG_STM32L4_DAC1 +#ifdef CONFIG_STM32_DAC1 case 0: ainfo("DAC1-1 Selected\n"); dev = &g_dac1dev; break; #endif -#ifdef CONFIG_STM32L4_DAC2 +#ifdef CONFIG_STM32_DAC2 case 1: ainfo("DAC1-2 Selected\n"); dev = &g_dac2dev; @@ -1385,5 +1385,5 @@ struct dac_dev_s *stm32l4_dacinitialize(int intf) return dev; } -#endif /* CONFIG_STM32L4_DAC1 || CONFIG_STM32L4_DAC2 */ +#endif /* CONFIG_STM32_DAC1 || CONFIG_STM32_DAC2 */ #endif /* CONFIG_DAC */ diff --git a/arch/arm/src/stm32l4/stm32l4_dac.h b/arch/arm/src/stm32l4/stm32l4_dac.h index 6bf30f75ab4e1..67636aebb1d1e 100644 --- a/arch/arm/src/stm32l4/stm32l4_dac.h +++ b/arch/arm/src/stm32l4/stm32l4_dac.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32L4_STM32L4_DAC_H -#define __ARCH_ARM_SRC_STM32L4_STM32L4_DAC_H +#ifndef __ARCH_ARM_SRC_STM32L4_STM32_DAC_H +#define __ARCH_ARM_SRC_STM32L4_STM32_DAC_H /**************************************************************************** * Included Files @@ -41,43 +41,43 @@ /* Configuration ************************************************************/ /* Timer devices may be used for different purposes. One special purpose is - * to control periodic DAC outputs. If CONFIG_STM32L4_TIMn is defined then - * CONFIG_STM32L4_TIMn_DAC must also be defined to indicate that timer "n" + * to control periodic DAC outputs. If CONFIG_STM32_TIMn is defined then + * CONFIG_STM32_TIMn_DAC must also be defined to indicate that timer "n" * is intended to be used for that purpose. */ -#ifndef CONFIG_STM32L4_TIM1 -# undef CONFIG_STM32L4_TIM1_DAC +#ifndef CONFIG_STM32_TIM1 +# undef CONFIG_STM32_TIM1_DAC #endif -#ifndef CONFIG_STM32L4_TIM2 -# undef CONFIG_STM32L4_TIM2_DAC +#ifndef CONFIG_STM32_TIM2 +# undef CONFIG_STM32_TIM2_DAC #endif -#ifndef CONFIG_STM32L4_TIM3 -# undef CONFIG_STM32L4_TIM3_DAC +#ifndef CONFIG_STM32_TIM3 +# undef CONFIG_STM32_TIM3_DAC #endif -#ifndef CONFIG_STM32L4_TIM4 -# undef CONFIG_STM32L4_TIM4_DAC +#ifndef CONFIG_STM32_TIM4 +# undef CONFIG_STM32_TIM4_DAC #endif -#ifndef CONFIG_STM32L4_TIM5 -# undef CONFIG_STM32L4_TIM5_DAC +#ifndef CONFIG_STM32_TIM5 +# undef CONFIG_STM32_TIM5_DAC #endif -#ifndef CONFIG_STM32L4_TIM6 -# undef CONFIG_STM32L4_TIM6_DAC +#ifndef CONFIG_STM32_TIM6 +# undef CONFIG_STM32_TIM6_DAC #endif -#ifndef CONFIG_STM32L4_TIM7 -# undef CONFIG_STM32L4_TIM7_DAC +#ifndef CONFIG_STM32_TIM7 +# undef CONFIG_STM32_TIM7_DAC #endif -#ifndef CONFIG_STM32L4_TIM8 -# undef CONFIG_STM32L4_TIM8_DAC +#ifndef CONFIG_STM32_TIM8 +# undef CONFIG_STM32_TIM8_DAC #endif -#ifndef CONFIG_STM32L4_TIM15 -# undef CONFIG_STM32L4_TIM15_DAC +#ifndef CONFIG_STM32_TIM15 +# undef CONFIG_STM32_TIM15_DAC #endif -#ifndef CONFIG_STM32L4_TIM16 -# undef CONFIG_STM32L4_TIM16_DAC +#ifndef CONFIG_STM32_TIM16 +# undef CONFIG_STM32_TIM16_DAC #endif -#ifndef CONFIG_STM32L4_TIM17 -# undef CONFIG_STM32L4_TIM17_DAC +#ifndef CONFIG_STM32_TIM17 +# undef CONFIG_STM32_TIM17_DAC #endif /* Low-level ops helpers ****************************************************/ @@ -97,7 +97,7 @@ * Public Types ****************************************************************************/ -#ifdef CONFIG_STM32L4_DAC_LL_OPS +#ifdef CONFIG_STM32_DAC_LL_OPS /* This structure provides the publicly visible representation of the * "lower-half" DAC driver structure. @@ -137,17 +137,17 @@ struct stm32_dac_ops_s void (*dump_regs)(struct stm32_dac_dev_s *dev); }; -#endif /* CONFIG_STM32L4_DAC_LL_OPS */ +#endif /* CONFIG_STM32_DAC_LL_OPS */ /**************************************************************************** * Public Data ****************************************************************************/ -#ifdef CONFIG_STM32L4_DAC1_DMA -extern uint16_t stm32l4_dac1_dmabuffer[]; +#ifdef CONFIG_STM32_DAC1_DMA +extern uint16_t stm32_dac1_dmabuffer[]; #endif -#ifdef CONFIG_STM32L4_DAC2_DMA -extern uint16_t stm32l4_dac2_dmabuffer[]; +#ifdef CONFIG_STM32_DAC2_DMA +extern uint16_t stm32_dac2_dmabuffer[]; #endif /**************************************************************************** @@ -164,7 +164,7 @@ extern "C" #endif /**************************************************************************** - * Name: stm32l4_dacinitialize + * Name: stm32_dacinitialize * * Description: * Initialize the DAC @@ -178,7 +178,7 @@ extern "C" ****************************************************************************/ struct dac_dev_s; -struct dac_dev_s *stm32l4_dacinitialize(int intf); +struct dac_dev_s *stm32_dacinitialize(int intf); #undef EXTERN #ifdef __cplusplus @@ -186,4 +186,4 @@ struct dac_dev_s *stm32l4_dacinitialize(int intf); #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32L4_STM32L4_DAC_H */ +#endif /* __ARCH_ARM_SRC_STM32L4_STM32_DAC_H */ diff --git a/arch/arm/src/stm32l4/stm32l4_dbgmcu.h b/arch/arm/src/stm32l4/stm32l4_dbgmcu.h index 5e460f90603ce..d4bc258925698 100644 --- a/arch/arm/src/stm32l4/stm32l4_dbgmcu.h +++ b/arch/arm/src/stm32l4/stm32l4_dbgmcu.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32L4_STM32L4_DBGMCU_H -#define __ARCH_ARM_SRC_STM32L4_STM32L4_DBGMCU_H +#ifndef __ARCH_ARM_SRC_STM32L4_STM32_DBGMCU_H +#define __ARCH_ARM_SRC_STM32L4_STM32_DBGMCU_H /**************************************************************************** * Included Files @@ -31,16 +31,16 @@ #include "chip.h" -#if defined(CONFIG_STM32L4_STM32L4X3) +#if defined(CONFIG_STM32_STM32L4X3) # include "hardware/stm32l4x3xx_dbgmcu.h" -#elif defined(CONFIG_STM32L4_STM32L4X5) +#elif defined(CONFIG_STM32_STM32L4X5) # include "hardware/stm32l4x5xx_dbgmcu.h" -#elif defined(CONFIG_STM32L4_STM32L4X6) +#elif defined(CONFIG_STM32_STM32L4X6) # include "hardware/stm32l4x6xx_dbgmcu.h" -#elif defined(CONFIG_STM32L4_STM32L4XR) +#elif defined(CONFIG_STM32_STM32L4XR) # include "hardware/stm32l4xrxx_dbgmcu.h" #else # error "Unsupported STM32L4 chip" #endif -#endif /* __ARCH_ARM_SRC_STM32L4_STM32L4_DBGMCU_H */ +#endif /* __ARCH_ARM_SRC_STM32L4_STM32_DBGMCU_H */ diff --git a/arch/arm/src/stm32l4/stm32l4_dfsdm.c b/arch/arm/src/stm32l4/stm32l4_dfsdm.c index 0c4d0c9534494..61293972da312 100644 --- a/arch/arm/src/stm32l4/stm32l4_dfsdm.c +++ b/arch/arm/src/stm32l4/stm32l4_dfsdm.c @@ -53,7 +53,7 @@ /* The peripheral must be enabled */ -#ifdef CONFIG_STM32L4_DFSDM +#ifdef CONFIG_STM32_DFSDM /**************************************************************************** * Pre-processor Definitions @@ -61,35 +61,35 @@ /* Sanity checking **********************************************************/ -#if !defined(CONFIG_STM32L4_DFSDM1_FLT0) && \ - !defined(CONFIG_STM32L4_DFSDM1_FLT1) && \ - !defined(CONFIG_STM32L4_DFSDM1_FLT2) && !defined(CONFIG_STM32L4_DFSDM1_FLT3) +#if !defined(CONFIG_STM32_DFSDM1_FLT0) && \ + !defined(CONFIG_STM32_DFSDM1_FLT1) && \ + !defined(CONFIG_STM32_DFSDM1_FLT2) && !defined(CONFIG_STM32_DFSDM1_FLT3) # error "At least one DFSDM filter must be defined" #endif -#if defined(CONFIG_STM32L4_STM32L4X3) -# if defined(CONFIG_STM32L4_DFSDM1_FLT2) || defined(CONFIG_STM32L4_DFSDM1_FLT3) +#if defined(CONFIG_STM32_STM32L4X3) +# if defined(CONFIG_STM32_DFSDM1_FLT2) || defined(CONFIG_STM32_DFSDM1_FLT3) # error "Non-existent DFSDM filter defined" # endif #endif /* Abbreviated register access **********************************************/ -#define CHCFGR1_OFFSET(priv) STM32L4_DFSDM_CHCFGR1_OFFSET((priv)->current) -#define CHCFGR2_OFFSET(priv) STM32L4_DFSDM_CHCFGR2_OFFSET((priv)->current) - -#define FLTCR1_OFFSET(priv) STM32L4_DFSDM_FLTCR1_OFFSET((priv)->intf) -#define FLTCR2_OFFSET(priv) STM32L4_DFSDM_FLTCR2_OFFSET((priv)->intf) -#define FLTISR_OFFSET(priv) STM32L4_DFSDM_FLTISR_OFFSET((priv)->intf) -#define FLTICR_OFFSET(priv) STM32L4_DFSDM_FLTICR_OFFSET((priv)->intf) -#define FLTFCR_OFFSET(priv) STM32L4_DFSDM_FLTFCR_OFFSET((priv)->intf) -#define FLTRDATAR_OFFSET(priv) STM32L4_DFSDM_FLTRDATAR_OFFSET((priv)->intf) -#define FLTAWHTR_OFFSET(priv) STM32L4_DFSDM_FLTAWHTR_OFFSET((priv)->intf) -#define FLTAWLTR_OFFSET(priv) STM32L4_DFSDM_FLTAWLTR_OFFSET((priv)->intf) -#define FLTAWSR_OFFSET(priv) STM32L4_DFSDM_FLTAWSR_OFFSET((priv)->intf) -#define FLTAWCFR_OFFSET(priv) STM32L4_DFSDM_FLTAWCFR_OFFSET((priv)->intf) -#define FLTEXMAX_OFFSET(priv) STM32L4_DFSDM_FLTEXMAX_OFFSET((priv)->intf) -#define FLTEXMIN_OFFSET(priv) STM32L4_DFSDM_FLTEXMIN_OFFSET((priv)->intf) +#define CHCFGR1_OFFSET(priv) STM32_DFSDM_CHCFGR1_OFFSET((priv)->current) +#define CHCFGR2_OFFSET(priv) STM32_DFSDM_CHCFGR2_OFFSET((priv)->current) + +#define FLTCR1_OFFSET(priv) STM32_DFSDM_FLTCR1_OFFSET((priv)->intf) +#define FLTCR2_OFFSET(priv) STM32_DFSDM_FLTCR2_OFFSET((priv)->intf) +#define FLTISR_OFFSET(priv) STM32_DFSDM_FLTISR_OFFSET((priv)->intf) +#define FLTICR_OFFSET(priv) STM32_DFSDM_FLTICR_OFFSET((priv)->intf) +#define FLTFCR_OFFSET(priv) STM32_DFSDM_FLTFCR_OFFSET((priv)->intf) +#define FLTRDATAR_OFFSET(priv) STM32_DFSDM_FLTRDATAR_OFFSET((priv)->intf) +#define FLTAWHTR_OFFSET(priv) STM32_DFSDM_FLTAWHTR_OFFSET((priv)->intf) +#define FLTAWLTR_OFFSET(priv) STM32_DFSDM_FLTAWLTR_OFFSET((priv)->intf) +#define FLTAWSR_OFFSET(priv) STM32_DFSDM_FLTAWSR_OFFSET((priv)->intf) +#define FLTAWCFR_OFFSET(priv) STM32_DFSDM_FLTAWCFR_OFFSET((priv)->intf) +#define FLTEXMAX_OFFSET(priv) STM32_DFSDM_FLTEXMAX_OFFSET((priv)->intf) +#define FLTEXMIN_OFFSET(priv) STM32_DFSDM_FLTEXMIN_OFFSET((priv)->intf) /* DFSDM Filter interrupts **************************************************/ @@ -122,7 +122,7 @@ * without, although there is a risk of overrun. */ -#if defined(CONFIG_STM32L4_STM32L4X3) +#if defined(CONFIG_STM32_STM32L4X3) # define DFSDM_MAX_CHANNELS 4 # define DFSDM_MAX_FILTERS 2 #else @@ -131,8 +131,8 @@ #endif #ifdef DFSDM_HAVE_DMA -# if !defined(CONFIG_STM32L4_DMA1) && !defined(CONFIG_STM32L4_DMAMUX) -# error "STM32L4 DFSDM DMA support requires CONFIG_STM32L4_DMA1" +# if !defined(CONFIG_STM32_DMA1) && !defined(CONFIG_STM32_DMAMUX) +# error "STM32L4 DFSDM DMA support requires CONFIG_STM32_DMA1" # endif #endif @@ -232,16 +232,16 @@ static void dfsdm_startconv(struct stm32_dev_s *priv, bool enable); /* Interrupt Handler */ static int dfsdm_interrupt(struct adc_dev_s *dev, uint32_t regval); -#if defined(CONFIG_STM32L4_DFSDM1_FLT0) +#if defined(CONFIG_STM32_DFSDM1_FLT0) static int dfsdm_flt0_interrupt(int irq, void *context, void *arg); #endif -#if defined(CONFIG_STM32L4_DFSDM1_FLT1) +#if defined(CONFIG_STM32_DFSDM1_FLT1) static int dfsdm_flt1_interrupt(int irq, void *context, void *arg); #endif -#if defined(CONFIG_STM32L4_DFSDM1_FLT2) +#if defined(CONFIG_STM32_DFSDM1_FLT2) static int dfsdm_flt2_interrupt(int irq, void *context, void *arg); #endif -#if defined(CONFIG_STM32L4_DFSDM1_FLT3) +#if defined(CONFIG_STM32_DFSDM1_FLT3) static int dfsdm_flt3_interrupt(int irq, void *context, void *arg); #endif @@ -274,19 +274,19 @@ static const struct adc_ops_s g_adcops = /* DFSDM FLT0 */ -#if defined(CONFIG_STM32L4_DFSDM1_FLT0) +#if defined(CONFIG_STM32_DFSDM1_FLT0) static struct stm32_dev_s g_dfsdmpriv0 = { - .irq = STM32L4_IRQ_DFSDM0, + .irq = STM32_IRQ_DFSDM0, .isr = dfsdm_flt0_interrupt, .intf = 0, - .base = STM32L4_DFSDM_BASE, + .base = STM32_DFSDM_BASE, #ifdef DFSDM_HAVE_TIMER - .trigger = CONFIG_STM32L4_DFSDM_TIMTRIG, + .trigger = CONFIG_STM32_DFSDM_TIMTRIG, .tbase = DFSDM_TIMER_BASE, .extsel = DFSDM_JEXTSEL_VALUE, .pclck = DFSDM_TIMER_PCLK_FREQUENCY, - .freq = CONFIG_STM32L4_DFSDM_SAMPLE_FREQUENCY, + .freq = CONFIG_STM32_DFSDM_SAMPLE_FREQUENCY, #endif #ifdef DFSDM_HAVE_DMA .dmachan = DMACHAN_DFSDM0, @@ -303,19 +303,19 @@ static struct adc_dev_s g_dfsdmdev0 = /* DFSDM FLT1 */ -#if defined(CONFIG_STM32L4_DFSDM1_FLT1) +#if defined(CONFIG_STM32_DFSDM1_FLT1) static struct stm32_dev_s g_dfsdmpriv1 = { - .irq = STM32L4_IRQ_DFSDM1, + .irq = STM32_IRQ_DFSDM1, .isr = dfsdm_flt1_interrupt, .intf = 1, - .base = STM32L4_DFSDM_BASE, + .base = STM32_DFSDM_BASE, #ifdef DFSDM_HAVE_TIMER - .trigger = CONFIG_STM32L4_DFSDM_TIMTRIG, + .trigger = CONFIG_STM32_DFSDM_TIMTRIG, .tbase = DFSDM_TIMER_BASE, .extsel = DFSDM_JEXTSEL_VALUE, .pclck = DFSDM_TIMER_PCLK_FREQUENCY, - .freq = CONFIG_STM32L4_DFSDM_SAMPLE_FREQUENCY, + .freq = CONFIG_STM32_DFSDM_SAMPLE_FREQUENCY, #endif #ifdef DFSDM_HAVE_DMA .dmachan = DMACHAN_DFSDM1, @@ -332,19 +332,19 @@ static struct adc_dev_s g_dfsdmdev1 = /* DFSDM FLT2 */ -#if defined(CONFIG_STM32L4_DFSDM1_FLT2) +#if defined(CONFIG_STM32_DFSDM1_FLT2) static struct stm32_dev_s g_dfsdmpriv2 = { - .irq = STM32L4_IRQ_DFSDM2, + .irq = STM32_IRQ_DFSDM2, .isr = dfsdm_flt2_interrupt, .intf = 0, - .base = STM32L4_DFSDM_BASE, + .base = STM32_DFSDM_BASE, #ifdef DFSDM_HAVE_TIMER - .trigger = CONFIG_STM32L4_DFSDM_TIMTRIG, + .trigger = CONFIG_STM32_DFSDM_TIMTRIG, .tbase = DFSDM_TIMER_BASE, .extsel = DFSDM_JEXTSEL_VALUE, .pclck = DFSDM_TIMER_PCLK_FREQUENCY, - .freq = CONFIG_STM32L4_DFSDM_SAMPLE_FREQUENCY, + .freq = CONFIG_STM32_DFSDM_SAMPLE_FREQUENCY, #endif #ifdef DFSDM_HAVE_DMA .dmachan = DMACHAN_DFSDM2, @@ -361,19 +361,19 @@ static struct adc_dev_s g_dfsdmdev2 = /* DFSDM FLT3 */ -#if defined(CONFIG_STM32L4_DFSDM1_FLT3) +#if defined(CONFIG_STM32_DFSDM1_FLT3) static struct stm32_dev_s g_dfsdmpriv3 = { - .irq = STM32L4_IRQ_DFSDM3, + .irq = STM32_IRQ_DFSDM3, .isr = dfsdm_flt3_interrupt, .intf = 0, - .base = STM32L4_DFSDM_BASE, + .base = STM32_DFSDM_BASE, #ifdef DFSDM_HAVE_TIMER - .trigger = CONFIG_STM32L4_DFSDM_TIMTRIG, + .trigger = CONFIG_STM32_DFSDM_TIMTRIG, .tbase = DFSDM_TIMER_BASE, .extsel = DFSDM_JEXTSEL_VALUE, .pclck = DFSDM_TIMER_PCLK_FREQUENCY, - .freq = CONFIG_STM32L4_DFSDM_SAMPLE_FREQUENCY, + .freq = CONFIG_STM32_DFSDM_SAMPLE_FREQUENCY, #endif #ifdef DFSDM_HAVE_DMA .dmachan = DMACHAN_DFSDM3, @@ -548,38 +548,38 @@ static void tim_dumpregs(struct stm32_dev_s *priv, const char *msg) { ainfo("%s:\n", msg); ainfo(" CR1: %04x CR2: %04x SMCR: %04x DIER: %04x\n", - tim_getreg(priv, STM32L4_GTIM_CR1_OFFSET), - tim_getreg(priv, STM32L4_GTIM_CR2_OFFSET), - tim_getreg(priv, STM32L4_GTIM_SMCR_OFFSET), - tim_getreg(priv, STM32L4_GTIM_DIER_OFFSET)); + tim_getreg(priv, STM32_GTIM_CR1_OFFSET), + tim_getreg(priv, STM32_GTIM_CR2_OFFSET), + tim_getreg(priv, STM32_GTIM_SMCR_OFFSET), + tim_getreg(priv, STM32_GTIM_DIER_OFFSET)); ainfo(" SR: %04x EGR: 0000 CCMR1: %04x CCMR2: %04x\n", - tim_getreg(priv, STM32L4_GTIM_SR_OFFSET), - tim_getreg(priv, STM32L4_GTIM_CCMR1_OFFSET), - tim_getreg(priv, STM32L4_GTIM_CCMR2_OFFSET)); + tim_getreg(priv, STM32_GTIM_SR_OFFSET), + tim_getreg(priv, STM32_GTIM_CCMR1_OFFSET), + tim_getreg(priv, STM32_GTIM_CCMR2_OFFSET)); ainfo(" CCER: %04x CNT: %04x PSC: %04x ARR: %04x\n", - tim_getreg(priv, STM32L4_GTIM_CCER_OFFSET), - tim_getreg(priv, STM32L4_GTIM_CNT_OFFSET), - tim_getreg(priv, STM32L4_GTIM_PSC_OFFSET), - tim_getreg(priv, STM32L4_GTIM_ARR_OFFSET)); + tim_getreg(priv, STM32_GTIM_CCER_OFFSET), + tim_getreg(priv, STM32_GTIM_CNT_OFFSET), + tim_getreg(priv, STM32_GTIM_PSC_OFFSET), + tim_getreg(priv, STM32_GTIM_ARR_OFFSET)); ainfo(" CCR1: %04x CCR2: %04x CCR3: %04x CCR4: %04x\n", - tim_getreg(priv, STM32L4_GTIM_CCR1_OFFSET), - tim_getreg(priv, STM32L4_GTIM_CCR2_OFFSET), - tim_getreg(priv, STM32L4_GTIM_CCR3_OFFSET), - tim_getreg(priv, STM32L4_GTIM_CCR4_OFFSET)); + tim_getreg(priv, STM32_GTIM_CCR1_OFFSET), + tim_getreg(priv, STM32_GTIM_CCR2_OFFSET), + tim_getreg(priv, STM32_GTIM_CCR3_OFFSET), + tim_getreg(priv, STM32_GTIM_CCR4_OFFSET)); - if (priv->tbase == STM32L4_TIM1_BASE || priv->tbase == STM32L4_TIM8_BASE) + if (priv->tbase == STM32_TIM1_BASE || priv->tbase == STM32_TIM8_BASE) { ainfo(" RCR: %04x BDTR: %04x DCR: %04x DMAR: %04x\n", - tim_getreg(priv, STM32L4_ATIM_RCR_OFFSET), - tim_getreg(priv, STM32L4_ATIM_BDTR_OFFSET), - tim_getreg(priv, STM32L4_ATIM_DCR_OFFSET), - tim_getreg(priv, STM32L4_ATIM_DMAR_OFFSET)); + tim_getreg(priv, STM32_ATIM_RCR_OFFSET), + tim_getreg(priv, STM32_ATIM_BDTR_OFFSET), + tim_getreg(priv, STM32_ATIM_DCR_OFFSET), + tim_getreg(priv, STM32_ATIM_DMAR_OFFSET)); } else { ainfo(" DCR: %04x DMAR: %04x\n", - tim_getreg(priv, STM32L4_GTIM_DCR_OFFSET), - tim_getreg(priv, STM32L4_GTIM_DMAR_OFFSET)); + tim_getreg(priv, STM32_GTIM_DCR_OFFSET), + tim_getreg(priv, STM32_GTIM_DMAR_OFFSET)); } } #endif @@ -607,13 +607,13 @@ static void dfsdm_timstart(struct stm32_dev_s *priv, bool enable) { /* Start the counter */ - tim_modifyreg(priv, STM32L4_GTIM_CR1_OFFSET, 0, GTIM_CR1_CEN); + tim_modifyreg(priv, STM32_GTIM_CR1_OFFSET, 0, GTIM_CR1_CEN); } else { /* Disable the counter */ - tim_modifyreg(priv, STM32L4_GTIM_CR1_OFFSET, GTIM_CR1_CEN, 0); + tim_modifyreg(priv, STM32_GTIM_CR1_OFFSET, GTIM_CR1_CEN, 0); } } #endif @@ -747,24 +747,24 @@ static int dfsdm_timinit(struct stm32_dev_s *priv) clrbits = GTIM_CR1_DIR | GTIM_CR1_CMS_MASK | GTIM_CR1_CKD_MASK; setbits = GTIM_CR1_EDGE; - tim_modifyreg(priv, STM32L4_GTIM_CR1_OFFSET, clrbits, setbits); + tim_modifyreg(priv, STM32_GTIM_CR1_OFFSET, clrbits, setbits); /* Set the reload and prescaler values */ - tim_putreg(priv, STM32L4_GTIM_PSC_OFFSET, prescaler - 1); - tim_putreg(priv, STM32L4_GTIM_ARR_OFFSET, reload); + tim_putreg(priv, STM32_GTIM_PSC_OFFSET, prescaler - 1); + tim_putreg(priv, STM32_GTIM_ARR_OFFSET, reload); /* Clear the advanced timers repetition counter in TIM1 */ - if (priv->tbase == STM32L4_TIM1_BASE || priv->tbase == STM32L4_TIM8_BASE) + if (priv->tbase == STM32_TIM1_BASE || priv->tbase == STM32_TIM8_BASE) { - tim_putreg(priv, STM32L4_ATIM_RCR_OFFSET, 0); - tim_putreg(priv, STM32L4_ATIM_BDTR_OFFSET, ATIM_BDTR_MOE); /* Check me */ + tim_putreg(priv, STM32_ATIM_RCR_OFFSET, 0); + tim_putreg(priv, STM32_ATIM_BDTR_OFFSET, ATIM_BDTR_MOE); /* Check me */ } /* TIMx event generation: Bit 0 UG: Update generation */ - tim_putreg(priv, STM32L4_GTIM_EGR_OFFSET, GTIM_EGR_UG); + tim_putreg(priv, STM32_GTIM_EGR_OFFSET, GTIM_EGR_UG); /* Handle channel specific setup */ @@ -788,7 +788,7 @@ static int dfsdm_timinit(struct stm32_dev_s *priv) * channel */ - tim_putreg(priv, STM32L4_GTIM_CCR1_OFFSET, + tim_putreg(priv, STM32_GTIM_CCR1_OFFSET, (uint16_t)(reload >> 1)); } break; @@ -808,7 +808,7 @@ static int dfsdm_timinit(struct stm32_dev_s *priv) * channel */ - tim_putreg(priv, STM32L4_GTIM_CCR2_OFFSET, + tim_putreg(priv, STM32_GTIM_CCR2_OFFSET, (uint16_t)(reload >> 1)); } break; @@ -828,7 +828,7 @@ static int dfsdm_timinit(struct stm32_dev_s *priv) * channel */ - tim_putreg(priv, STM32L4_GTIM_CCR3_OFFSET, + tim_putreg(priv, STM32_GTIM_CCR3_OFFSET, (uint16_t)(reload >> 1)); } break; @@ -848,7 +848,7 @@ static int dfsdm_timinit(struct stm32_dev_s *priv) * channel */ - tim_putreg(priv, STM32L4_GTIM_CCR4_OFFSET, + tim_putreg(priv, STM32_GTIM_CCR4_OFFSET, (uint16_t)(reload >> 1)); } break; @@ -866,7 +866,7 @@ static int dfsdm_timinit(struct stm32_dev_s *priv) * channel */ - tim_putreg(priv, STM32L4_GTIM_CCR4_OFFSET, + tim_putreg(priv, STM32_GTIM_CCR4_OFFSET, (uint16_t)(reload >> 1)); } break; @@ -878,15 +878,15 @@ static int dfsdm_timinit(struct stm32_dev_s *priv) /* Disable the Channel by resetting the CCxE Bit in the CCER register */ - ccer = tim_getreg(priv, STM32L4_GTIM_CCER_OFFSET); + ccer = tim_getreg(priv, STM32_GTIM_CCER_OFFSET); ccer &= ~ccenable; - tim_putreg(priv, STM32L4_GTIM_CCER_OFFSET, ccer); + tim_putreg(priv, STM32_GTIM_CCER_OFFSET, ccer); /* Fetch the CR2, CCMR1, and CCMR2 register (already have ccer) */ - cr2 = tim_getreg(priv, STM32L4_GTIM_CR2_OFFSET); - ccmr1 = tim_getreg(priv, STM32L4_GTIM_CCMR1_OFFSET); - ccmr2 = tim_getreg(priv, STM32L4_GTIM_CCMR2_OFFSET); + cr2 = tim_getreg(priv, STM32_GTIM_CR2_OFFSET); + ccmr1 = tim_getreg(priv, STM32_GTIM_CCMR1_OFFSET); + ccmr2 = tim_getreg(priv, STM32_GTIM_CCMR2_OFFSET); /* Reset the Output Compare Mode Bits and set the select output compare * mode @@ -912,7 +912,7 @@ static int dfsdm_timinit(struct stm32_dev_s *priv) ATIM_CCER_CC3E | ATIM_CCER_CC4E); ccer |= ccenable; - if (priv->tbase == STM32L4_TIM1_BASE || priv->tbase == STM32L4_TIM8_BASE) + if (priv->tbase == STM32_TIM1_BASE || priv->tbase == STM32_TIM8_BASE) { /* Reset output N polarity level, output N state, output compare state, * output compare N idle state. @@ -937,15 +937,15 @@ static int dfsdm_timinit(struct stm32_dev_s *priv) /* Save the modified register values */ - tim_putreg(priv, STM32L4_GTIM_CR2_OFFSET, cr2); - tim_putreg(priv, STM32L4_GTIM_CCMR1_OFFSET, ccmr1); - tim_putreg(priv, STM32L4_GTIM_CCMR2_OFFSET, ccmr2); - tim_putreg(priv, STM32L4_GTIM_CCER_OFFSET, ccer); - tim_putreg(priv, STM32L4_GTIM_EGR_OFFSET, egr); + tim_putreg(priv, STM32_GTIM_CR2_OFFSET, cr2); + tim_putreg(priv, STM32_GTIM_CCMR1_OFFSET, ccmr1); + tim_putreg(priv, STM32_GTIM_CCMR2_OFFSET, ccmr2); + tim_putreg(priv, STM32_GTIM_CCER_OFFSET, ccer); + tim_putreg(priv, STM32_GTIM_EGR_OFFSET, egr); /* Set the ARR Preload Bit */ - tim_modifyreg(priv, STM32L4_GTIM_CR1_OFFSET, 0, GTIM_CR1_ARPE); + tim_modifyreg(priv, STM32_GTIM_CR1_OFFSET, 0, GTIM_CR1_ARPE); /* Enable the timer counter */ @@ -1050,7 +1050,7 @@ static void dfsdm_rccreset(struct stm32_dev_s *priv, bool reset) /* Set or clear the selected bit in the APB2 reset register */ - regval = getreg32(STM32L4_RCC_APB2RSTR); + regval = getreg32(STM32_RCC_APB2RSTR); if (reset) { regval |= RCC_APB2RSTR_DFSDMRST; @@ -1060,7 +1060,7 @@ static void dfsdm_rccreset(struct stm32_dev_s *priv, bool reset) regval &= ~RCC_APB2RSTR_DFSDMRST; } - putreg32(regval, STM32L4_RCC_APB2RSTR); + putreg32(regval, STM32_RCC_APB2RSTR); leave_critical_section(flags); } @@ -1079,12 +1079,12 @@ static void dfsdm_enable(struct stm32_dev_s *priv) { uint32_t regval; - regval = dfsdm_getreg(priv, STM32L4_DFSDM_CH0CFGR1_OFFSET); + regval = dfsdm_getreg(priv, STM32_DFSDM_CH0CFGR1_OFFSET); /* Enable DFSMDM */ regval |= DFSDM_CH0CFGR1_DFSDMEN; - dfsdm_putreg(priv, STM32L4_DFSDM_CH0CFGR1_OFFSET, regval); + dfsdm_putreg(priv, STM32_DFSDM_CH0CFGR1_OFFSET, regval); } /**************************************************************************** @@ -1204,19 +1204,19 @@ static int dfsdm_setup(struct adc_dev_s *dev) if (priv->dma != NULL) { - stm32l4_dmastop(priv->dma); - stm32l4_dmafree(priv->dma); + stm32_dmastop(priv->dma); + stm32_dmafree(priv->dma); } - priv->dma = stm32l4_dmachannel(priv->dmachan); + priv->dma = stm32_dmachannel(priv->dmachan); - stm32l4_dmasetup(priv->dma, + stm32_dmasetup(priv->dma, priv->base + FLTRDATAR_OFFSET(priv), (uint32_t)priv->dmabuffer, priv->nchannels, DFSDM_DMA_CONTROL_WORD); - stm32l4_dmastart(priv->dma, dfsdm_dmaconvcallback, dev, false); + stm32_dmastart(priv->dma, dfsdm_dmaconvcallback, dev, false); } #endif @@ -1582,13 +1582,13 @@ static int dfsdm_interrupt(struct adc_dev_s *dev, uint32_t isr) * ****************************************************************************/ -#if defined(CONFIG_STM32L4_DFSDM1_FLT0) +#if defined(CONFIG_STM32_DFSDM1_FLT0) static int dfsdm_flt0_interrupt(int irq, void *context, void *arg) { uint32_t regval; uint32_t pending; - regval = getreg32(STM32L4_DFSDM_FLTISR(0)); + regval = getreg32(STM32_DFSDM_FLTISR(0)); pending = regval & DFSDM_ISR_MASK; if (pending != 0) { @@ -1607,13 +1607,13 @@ static int dfsdm_flt0_interrupt(int irq, void *context, void *arg) * ****************************************************************************/ -#if defined(CONFIG_STM32L4_DFSDM1_FLT1) +#if defined(CONFIG_STM32_DFSDM1_FLT1) static int dfsdm_flt1_interrupt(int irq, void *context, void *arg) { uint32_t regval; uint32_t pending; - regval = getreg32(STM32L4_DFSDM_FLTISR(1)); + regval = getreg32(STM32_DFSDM_FLTISR(1)); pending = regval & DFSDM_ISR_MASK; if (pending != 0) { @@ -1632,13 +1632,13 @@ static int dfsdm_flt1_interrupt(int irq, void *context, void *arg) * ****************************************************************************/ -#if defined(CONFIG_STM32L4_DFSDM1_FLT2) +#if defined(CONFIG_STM32_DFSDM1_FLT2) static int dfsdm_flt2_interrupt(int irq, void *context, void *arg) { uint32_t regval; uint32_t pending; - regval = getreg32(STM32L4_DFSDM_FLTISR(2)); + regval = getreg32(STM32_DFSDM_FLTISR(2)); pending = regval & DFSDM_ISR_MASK; if (pending != 0) { @@ -1657,13 +1657,13 @@ static int dfsdm_flt2_interrupt(int irq, void *context, void *arg) * ****************************************************************************/ -#if defined(CONFIG_STM32L4_DFSDM1_FLT3) +#if defined(CONFIG_STM32_DFSDM1_FLT3) static int dfsdm_flt3_interrupt(int irq, void *context, void *arg) { uint32_t regval; uint32_t pending; - regval = getreg32(STM32L4_DFSDM_FLTISR(3)); + regval = getreg32(STM32_DFSDM_FLTISR(3)); pending = regval & DFSDM_ISR_MASK; if (pending != 0) { @@ -1735,7 +1735,7 @@ static void dfsdm_dmaconvcallback(DMA_HANDLE handle, ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_dfsdm_initialize + * Name: stm32_dfsdm_initialize * * Description: * Initialize the DFSDM. @@ -1750,7 +1750,7 @@ static void dfsdm_dmaconvcallback(DMA_HANDLE handle, * ****************************************************************************/ -struct adc_dev_s *stm32l4_dfsdm_initialize(int intf, +struct adc_dev_s *stm32_dfsdm_initialize(int intf, const uint8_t *chanlist, int cchannels) { @@ -1761,25 +1761,25 @@ struct adc_dev_s *stm32l4_dfsdm_initialize(int intf, switch (intf) { -#if defined(CONFIG_STM32L4_DFSDM1_FLT0) +#if defined(CONFIG_STM32_DFSDM1_FLT0) case 0: ainfo("DFSDM FLT0 selected\n"); dev = &g_dfsdmdev0; break; #endif -#if defined(CONFIG_STM32L4_DFSDM1_FLT1) +#if defined(CONFIG_STM32_DFSDM1_FLT1) case 1: ainfo("DFSDM FLT1 selected\n"); dev = &g_dfsdmdev1; break; #endif -#if defined(CONFIG_STM32L4_DFSDM1_FLT2) +#if defined(CONFIG_STM32_DFSDM1_FLT2) case 2: ainfo("DFSDM FLT2 selected\n"); dev = &g_dfsdmdev2; break; #endif -#if defined(CONFIG_STM32L4_DFSDM1_FLT3) +#if defined(CONFIG_STM32_DFSDM1_FLT3) case 3: ainfo("DFSDM FLT3 selected\n"); dev = &g_dfsdmdev3; @@ -1818,5 +1818,5 @@ struct adc_dev_s *stm32l4_dfsdm_initialize(int intf, return dev; } -#endif /* CONFIG_STM32L4_DFSDM */ +#endif /* CONFIG_STM32_DFSDM */ #endif /* CONFIG_ADC */ diff --git a/arch/arm/src/stm32l4/stm32l4_dfsdm.h b/arch/arm/src/stm32l4/stm32l4_dfsdm.h index 6039443f5ab53..aa0768b5a3cd9 100644 --- a/arch/arm/src/stm32l4/stm32l4_dfsdm.h +++ b/arch/arm/src/stm32l4/stm32l4_dfsdm.h @@ -39,49 +39,49 @@ /* Configuration ************************************************************/ /* Timer devices may be used for different purposes. One special purpose is - * to control periodic ADC sampling. If CONFIG_STM32L4_TIMn is defined then - * CONFIG_STM32L4_TIMn_DFSDM must also be defined to indicate that timer "n" + * to control periodic ADC sampling. If CONFIG_STM32_TIMn is defined then + * CONFIG_STM32_TIMn_DFSDM must also be defined to indicate that timer "n" * is intended to be used for that purpose. Timers 1,3,6 and 16 may be used * on STM32L4X3, while STM32L4X6 adds support for timers 4,7 and 8 as well. */ -#ifndef CONFIG_STM32L4_TIM1 -# undef CONFIG_STM32L4_TIM1_DFSDM +#ifndef CONFIG_STM32_TIM1 +# undef CONFIG_STM32_TIM1_DFSDM #endif -#ifndef CONFIG_STM32L4_TIM3 -# undef CONFIG_STM32L4_TIM3_DFSDM +#ifndef CONFIG_STM32_TIM3 +# undef CONFIG_STM32_TIM3_DFSDM #endif -#ifndef CONFIG_STM32L4_TIM4 -# undef CONFIG_STM32L4_TIM4_DFSDM +#ifndef CONFIG_STM32_TIM4 +# undef CONFIG_STM32_TIM4_DFSDM #endif -#ifndef CONFIG_STM32L4_TIM6 -# undef CONFIG_STM32L4_TIM6_DFSDM +#ifndef CONFIG_STM32_TIM6 +# undef CONFIG_STM32_TIM6_DFSDM #endif -#ifndef CONFIG_STM32L4_TIM7 -# undef CONFIG_STM32L4_TIM7_DFSDM +#ifndef CONFIG_STM32_TIM7 +# undef CONFIG_STM32_TIM7_DFSDM #endif -#ifndef CONFIG_STM32L4_TIM8 -# undef CONFIG_STM32L4_TIM8_DFSDM +#ifndef CONFIG_STM32_TIM8 +# undef CONFIG_STM32_TIM8_DFSDM #endif -#ifndef CONFIG_STM32L4_TIM16 -# undef CONFIG_STM32L4_TIM16_DFSDM +#ifndef CONFIG_STM32_TIM16 +# undef CONFIG_STM32_TIM16_DFSDM #endif -#if defined(CONFIG_STM32L4_DFSDM) +#if defined(CONFIG_STM32_DFSDM) /* DMA support */ #undef DFSDM_HAVE_DMA -#if defined(CONFIG_STM32L4_DFSDM1_DMA) +#if defined(CONFIG_STM32_DFSDM1_DMA) # define DFSDM_HAVE_DMA 1 #endif /* ADC output to DFSDM support */ #undef ADC_HAVE_DFSDM -#if defined(CONFIG_STM32L4_ADC1_OUTPUT_DFSDM) || \ - defined(CONFIG_STM32L4_ADC2_OUTPUT_DFSDM) || \ - defined(CONFIG_STM32L4_ADC3_OUTPUT_DFSDM) +#if defined(CONFIG_STM32_ADC1_OUTPUT_DFSDM) || \ + defined(CONFIG_STM32_ADC2_OUTPUT_DFSDM) || \ + defined(CONFIG_STM32_ADC3_OUTPUT_DFSDM) # define ADC_HAVE_DFSDM #endif @@ -89,44 +89,44 @@ * information about the timer. */ -#if defined(CONFIG_STM32L4_TIM1_DFSDM) +#if defined(CONFIG_STM32_TIM1_DFSDM) # define DFSDM_HAVE_TIMER 1 -# define DFSDM_TIMER_BASE STM32L4_TIM1_BASE -# define DFSDM_TIMER_PCLK_FREQUENCY STM32L4_APB2_TIM1_CLKIN -#elif defined(CONFIG_STM32L4_TIM3_DFSDM) +# define DFSDM_TIMER_BASE STM32_TIM1_BASE +# define DFSDM_TIMER_PCLK_FREQUENCY STM32_APB2_TIM1_CLKIN +#elif defined(CONFIG_STM32_TIM3_DFSDM) # define DFSDM_HAVE_TIMER 1 -# define DFSDM_TIMER_BASE STM32L4_TIM3_BASE -# define DFSDM_TIMER_PCLK_FREQUENCY STM32L4_APB1_TIM3_CLKIN -#elif defined(CONFIG_STM32L4_TIM4_DFSDM) +# define DFSDM_TIMER_BASE STM32_TIM3_BASE +# define DFSDM_TIMER_PCLK_FREQUENCY STM32_APB1_TIM3_CLKIN +#elif defined(CONFIG_STM32_TIM4_DFSDM) # define DFSDM_HAVE_TIMER 1 -# define DFSDM_TIMER_BASE STM32L4_TIM4_BASE -# define DFSDM_TIMER_PCLK_FREQUENCY STM32L4_APB1_TIM4_CLKIN -#elif defined(CONFIG_STM32L4_TIM6_DFSDM) +# define DFSDM_TIMER_BASE STM32_TIM4_BASE +# define DFSDM_TIMER_PCLK_FREQUENCY STM32_APB1_TIM4_CLKIN +#elif defined(CONFIG_STM32_TIM6_DFSDM) # define DFSDM_HAVE_TIMER 1 -# define DFSDM_TIMER_BASE STM32L4_TIM6_BASE -# define DFSDM_TIMER_PCLK_FREQUENCY STM32L4_APB1_TIM6_CLKIN -#elif defined(CONFIG_STM32L4_TIM7_DFSDM) +# define DFSDM_TIMER_BASE STM32_TIM6_BASE +# define DFSDM_TIMER_PCLK_FREQUENCY STM32_APB1_TIM6_CLKIN +#elif defined(CONFIG_STM32_TIM7_DFSDM) # define DFSDM_HAVE_TIMER 1 -# define DFSDM_TIMER_BASE STM32L4_TIM7_BASE -# define DFSDM_TIMER_PCLK_FREQUENCY STM32L4_APB1_TIM7_CLKIN -#elif defined(CONFIG_STM32L4_TIM8_DFSDM) +# define DFSDM_TIMER_BASE STM32_TIM7_BASE +# define DFSDM_TIMER_PCLK_FREQUENCY STM32_APB1_TIM7_CLKIN +#elif defined(CONFIG_STM32_TIM8_DFSDM) # define DFSDM_HAVE_TIMER 1 -# define DFSDM_TIMER_BASE STM32L4_TIM8_BASE -# define DFSDM_TIMER_PCLK_FREQUENCY STM32L4_APB2_TIM8_CLKIN -#elif defined(CONFIG_STM32L4_TIM16_DFSDM) +# define DFSDM_TIMER_BASE STM32_TIM8_BASE +# define DFSDM_TIMER_PCLK_FREQUENCY STM32_APB2_TIM8_CLKIN +#elif defined(CONFIG_STM32_TIM16_DFSDM) # define DFSDM_HAVE_TIMER 1 -# define DFSDM_TIMER_BASE STM32L4_TIM16_BASE -# define DFSDM_TIMER_PCLK_FREQUENCY STM32L4_APB2_TIM16_CLKIN +# define DFSDM_TIMER_BASE STM32_TIM16_BASE +# define DFSDM_TIMER_PCLK_FREQUENCY STM32_APB2_TIM16_CLKIN #else # undef DFSDM_HAVE_TIMER #endif #ifdef DFSDM_HAVE_TIMER -# ifndef CONFIG_STM32L4_DFSDM_SAMPLE_FREQUENCY -# error "CONFIG_STM32L4_DFSDM_SAMPLE_FREQUENCY not defined" +# ifndef CONFIG_STM32_DFSDM_SAMPLE_FREQUENCY +# error "CONFIG_STM32_DFSDM_SAMPLE_FREQUENCY not defined" # endif -# ifndef CONFIG_STM32L4_DFSDM_TIMTRIG -# error "CONFIG_STM32L4_DFSDM_TIMTRIG not defined" +# ifndef CONFIG_STM32_DFSDM_TIMTRIG +# error "CONFIG_STM32_DFSDM_TIMTRIG not defined" # warning "Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO 5:TRGO2" # endif #endif @@ -184,107 +184,107 @@ #define DFSDM_JEXTSEL_T16CC4 DFSDM_FLTCR1_JEXTSEL_T16CC4 #define DFSDM_JEXTSEL_T16TRGO DFSDM_FLTCR1_JEXTSEL_T16TRGO -#if defined(CONFIG_STM32L4_TIM1_DFSDM) -# if CONFIG_STM32L4_DFSDM_TIMTRIG == 0 +#if defined(CONFIG_STM32_TIM1_DFSDM) +# if CONFIG_STM32_DFSDM_TIMTRIG == 0 # define DFSDM_JEXTSEL_VALUE DFSDM_JEXTSEL_T1CC1 -# elif CONFIG_STM32L4_DFSDM_TIMTRIG == 1 +# elif CONFIG_STM32_DFSDM_TIMTRIG == 1 # define DFSDM_JEXTSEL_VALUE DFSDM_JEXTSEL_T1CC2 -# elif CONFIG_STM32L4_DFSDM_TIMTRIG == 2 +# elif CONFIG_STM32_DFSDM_TIMTRIG == 2 # define DFSDM_JEXTSEL_VALUE DFSDM_JEXTSEL_T1CC3 -# elif CONFIG_STM32L4_DFSDM_TIMTRIG == 3 +# elif CONFIG_STM32_DFSDM_TIMTRIG == 3 # define DFSDM_JEXTSEL_VALUE DFSDM_JEXTSEL_T1CC4 -# elif CONFIG_STM32L4_DFSDM_TIMTRIG == 4 +# elif CONFIG_STM32_DFSDM_TIMTRIG == 4 # define DFSDM_JEXTSEL_VALUE DFSDM_JEXTSEL_T1TRGO -# elif CONFIG_STM32L4_DFSDM_TIMTRIG == 5 +# elif CONFIG_STM32_DFSDM_TIMTRIG == 5 # define DFSDM_JEXTSEL_VALUE DFSDM_JEXTSEL_T1TRGO2 # else -# error "CONFIG_STM32L4_DFSDM_TIMTRIG is out of range" +# error "CONFIG_STM32_DFSDM_TIMTRIG is out of range" # endif -#elif defined(CONFIG_STM32L4_TIM3_DFSDM) -# if CONFIG_STM32L4_DFSDM_TIMTRIG == 0 +#elif defined(CONFIG_STM32_TIM3_DFSDM) +# if CONFIG_STM32_DFSDM_TIMTRIG == 0 # define DFSDM_JEXTSEL_VALUE DFSDM_JEXTSEL_T3CC1 -# elif CONFIG_STM32L4_DFSDM_TIMTRIG == 1 +# elif CONFIG_STM32_DFSDM_TIMTRIG == 1 # define DFSDM_JEXTSEL_VALUE DFSDM_JEXTSEL_T3CC2 -# elif CONFIG_STM32L4_DFSDM_TIMTRIG == 2 +# elif CONFIG_STM32_DFSDM_TIMTRIG == 2 # define DFSDM_JEXTSEL_VALUE DFSDM_JEXTSEL_T3CC3 -# elif CONFIG_STM32L4_DFSDM_TIMTRIG == 3 +# elif CONFIG_STM32_DFSDM_TIMTRIG == 3 # define DFSDM_JEXTSEL_VALUE DFSDM_JEXTSEL_T3CC4 -# elif CONFIG_STM32L4_DFSDM_TIMTRIG == 4 +# elif CONFIG_STM32_DFSDM_TIMTRIG == 4 # define DFSDM_JEXTSEL_VALUE DFSDM_JEXTSEL_T3TRGO # else -# error "CONFIG_STM32L4_DFSDM_TIMTRIG is out of range" +# error "CONFIG_STM32_DFSDM_TIMTRIG is out of range" # endif -#elif defined(CONFIG_STM32L4_TIM4_DFSDM) -# if CONFIG_STM32L4_DFSDM_TIMTRIG == 0 +#elif defined(CONFIG_STM32_TIM4_DFSDM) +# if CONFIG_STM32_DFSDM_TIMTRIG == 0 # define DFSDM_JEXTSEL_VALUE DFSDM_JEXTSEL_T4CC1 -# elif CONFIG_STM32L4_DFSDM_TIMTRIG == 1 +# elif CONFIG_STM32_DFSDM_TIMTRIG == 1 # define DFSDM_JEXTSEL_VALUE DFSDM_JEXTSEL_T4CC2 -# elif CONFIG_STM32L4_DFSDM_TIMTRIG == 2 +# elif CONFIG_STM32_DFSDM_TIMTRIG == 2 # define DFSDM_JEXTSEL_VALUE DFSDM_JEXTSEL_T4CC3 -# elif CONFIG_STM32L4_DFSDM_TIMTRIG == 3 +# elif CONFIG_STM32_DFSDM_TIMTRIG == 3 # define DFSDM_JEXTSEL_VALUE DFSDM_JEXTSEL_T4CC4 -# elif CONFIG_STM32L4_DFSDM_TIMTRIG == 4 +# elif CONFIG_STM32_DFSDM_TIMTRIG == 4 # define DFSDM_JEXTSEL_VALUE DFSDM_JEXTSEL_T4TRGO # else -# error "CONFIG_STM32L4_DFSDM_TIMTRIG is out of range" +# error "CONFIG_STM32_DFSDM_TIMTRIG is out of range" # endif -#elif defined(CONFIG_STM32L4_TIM6_DFSDM) -# if CONFIG_STM32L4_DFSDM_TIMTRIG == 0 +#elif defined(CONFIG_STM32_TIM6_DFSDM) +# if CONFIG_STM32_DFSDM_TIMTRIG == 0 # define DFSDM_JEXTSEL_VALUE DFSDM_JEXTSEL_T6CC1 -# elif CONFIG_STM32L4_DFSDM_TIMTRIG == 1 +# elif CONFIG_STM32_DFSDM_TIMTRIG == 1 # define DFSDM_JEXTSEL_VALUE DFSDM_JEXTSEL_T6CC2 -# elif CONFIG_STM32L4_DFSDM_TIMTRIG == 2 +# elif CONFIG_STM32_DFSDM_TIMTRIG == 2 # define DFSDM_JEXTSEL_VALUE DFSDM_JEXTSEL_T6CC3 -# elif CONFIG_STM32L4_DFSDM_TIMTRIG == 3 +# elif CONFIG_STM32_DFSDM_TIMTRIG == 3 # define DFSDM_JEXTSEL_VALUE DFSDM_JEXTSEL_T6CC4 -# elif CONFIG_STM32L4_DFSDM_TIMTRIG == 4 +# elif CONFIG_STM32_DFSDM_TIMTRIG == 4 # define DFSDM_JEXTSEL_VALUE DFSDM_JEXTSEL_T6TRGO # else -# error "CONFIG_STM32L4_DFSDM_TIMTRIG is out of range" +# error "CONFIG_STM32_DFSDM_TIMTRIG is out of range" # endif -#elif defined(CONFIG_STM32L4_TIM7_DFSDM) -# if CONFIG_STM32L4_DFSDM_TIMTRIG == 0 +#elif defined(CONFIG_STM32_TIM7_DFSDM) +# if CONFIG_STM32_DFSDM_TIMTRIG == 0 # define DFSDM_JEXTSEL_VALUE DFSDM_JEXTSEL_T7CC1 -# elif CONFIG_STM32L4_DFSDM_TIMTRIG == 1 +# elif CONFIG_STM32_DFSDM_TIMTRIG == 1 # define DFSDM_JEXTSEL_VALUE DFSDM_JEXTSEL_T7CC2 -# elif CONFIG_STM32L4_DFSDM_TIMTRIG == 2 +# elif CONFIG_STM32_DFSDM_TIMTRIG == 2 # define DFSDM_JEXTSEL_VALUE DFSDM_JEXTSEL_T7CC3 -# elif CONFIG_STM32L4_DFSDM_TIMTRIG == 3 +# elif CONFIG_STM32_DFSDM_TIMTRIG == 3 # define DFSDM_JEXTSEL_VALUE DFSDM_JEXTSEL_T7CC4 -# elif CONFIG_STM32L4_DFSDM_TIMTRIG == 4 +# elif CONFIG_STM32_DFSDM_TIMTRIG == 4 # define DFSDM_JEXTSEL_VALUE DFSDM_JEXTSEL_T7TRGO # else -# error "CONFIG_STM32L4_DFSDM_TIMTRIG is out of range" +# error "CONFIG_STM32_DFSDM_TIMTRIG is out of range" # endif -#elif defined(CONFIG_STM32L4_TIM8_DFSDM) -# if CONFIG_STM32L4_DFSDM_TIMTRIG == 0 +#elif defined(CONFIG_STM32_TIM8_DFSDM) +# if CONFIG_STM32_DFSDM_TIMTRIG == 0 # define DFSDM_JEXTSEL_VALUE DFSDM_JEXTSEL_T8CC1 -# elif CONFIG_STM32L4_DFSDM_TIMTRIG == 1 +# elif CONFIG_STM32_DFSDM_TIMTRIG == 1 # define DFSDM_JEXTSEL_VALUE DFSDM_JEXTSEL_T8CC2 -# elif CONFIG_STM32L4_DFSDM_TIMTRIG == 2 +# elif CONFIG_STM32_DFSDM_TIMTRIG == 2 # define DFSDM_JEXTSEL_VALUE DFSDM_JEXTSEL_T8CC3 -# elif CONFIG_STM32L4_DFSDM_TIMTRIG == 3 +# elif CONFIG_STM32_DFSDM_TIMTRIG == 3 # define DFSDM_JEXTSEL_VALUE DFSDM_JEXTSEL_T8CC4 -# elif CONFIG_STM32L4_DFSDM_TIMTRIG == 4 +# elif CONFIG_STM32_DFSDM_TIMTRIG == 4 # define DFSDM_JEXTSEL_VALUE DFSDM_JEXTSEL_T8TRGO -# elif CONFIG_STM32L4_DFSDM_TIMTRIG == 5 +# elif CONFIG_STM32_DFSDM_TIMTRIG == 5 # define DFSDM_JEXTSEL_VALUE DFSDM_JEXTSEL_T8TRGO2 # else -# error "CONFIG_STM32L4_DFSDM_TIMTRIG is out of range" +# error "CONFIG_STM32_DFSDM_TIMTRIG is out of range" # endif -#elif defined(CONFIG_STM32L4_TIM16_DFSDM) -# if CONFIG_STM32L4_DFSDM_TIMTRIG == 0 +#elif defined(CONFIG_STM32_TIM16_DFSDM) +# if CONFIG_STM32_DFSDM_TIMTRIG == 0 # define DFSDM_JEXTSEL_VALUE DFSDM_JEXTSEL_T16CC1 -# elif CONFIG_STM32L4_DFSDM_TIMTRIG == 1 +# elif CONFIG_STM32_DFSDM_TIMTRIG == 1 # define DFSDM_JEXTSEL_VALUE DFSDM_JEXTSEL_T16CC2 -# elif CONFIG_STM32L4_DFSDM_TIMTRIG == 2 +# elif CONFIG_STM32_DFSDM_TIMTRIG == 2 # define DFSDM_JEXTSEL_VALUE DFSDM_JEXTSEL_T16CC3 -# elif CONFIG_STM32L4_DFSDM_TIMTRIG == 3 +# elif CONFIG_STM32_DFSDM_TIMTRIG == 3 # define DFSDM_JEXTSEL_VALUE DFSDM_JEXTSEL_T16CC4 -# elif CONFIG_STM32L4_DFSDM_TIMTRIG == 4 +# elif CONFIG_STM32_DFSDM_TIMTRIG == 4 # define DFSDM_JEXTSEL_VALUE DFSDM_JEXTSEL_T16TRGO # else -# error "CONFIG_STM32L4_DFSDM_TIMTRIG is out of range" +# error "CONFIG_STM32_DFSDM_TIMTRIG is out of range" # endif #endif @@ -306,7 +306,7 @@ extern "C" #endif /**************************************************************************** - * Name: stm32l4_dfsdm_initialize + * Name: stm32_dfsdm_initialize * * Description: * Initialize the DFSDM. @@ -322,7 +322,7 @@ extern "C" ****************************************************************************/ struct adc_dev_s; -struct adc_dev_s *stm32l4_dfsdm_initialize(int intf, +struct adc_dev_s *stm32_dfsdm_initialize(int intf, const uint8_t *chanlist, int nchannels); #undef EXTERN @@ -331,5 +331,5 @@ struct adc_dev_s *stm32l4_dfsdm_initialize(int intf, #endif #endif /* __ASSEMBLY__ */ -#endif /* CONFIG_STM32L4_DFSDM */ +#endif /* CONFIG_STM32_DFSDM */ #endif /* __ARCH_ARM_SRC_STM32L4_STM32L4_DFSDM_H */ diff --git a/arch/arm/src/stm32l4/stm32l4_dfumode.c b/arch/arm/src/stm32l4/stm32l4_dfumode.c index 026c03f7bcb10..a4c76d51dfde8 100644 --- a/arch/arm/src/stm32l4/stm32l4_dfumode.c +++ b/arch/arm/src/stm32l4/stm32l4_dfumode.c @@ -44,74 +44,74 @@ typedef void (*boot_call_t)(void); * Private Functions ****************************************************************************/ -#if defined(CONFIG_STM32L4_STM32L4X6) || defined(CONFIG_STM32L4_STM32L4XR) +#if defined(CONFIG_STM32_STM32L4X6) || defined(CONFIG_STM32_STM32L4XR) static inline void rcc_reset(void) { uint32_t regval; /* Enable the MSI clock */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_MSION; - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); - while (!(getreg32(STM32L4_RCC_CR) & RCC_CR_MSIRDY)); + while (!(getreg32(STM32_RCC_CR) & RCC_CR_MSIRDY)); /* Set MSI to 4MHz */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval &= ~RCC_CR_MSIRANGE_MASK; regval |= RCC_CR_MSIRANGE_4M | RCC_CR_MSIRGSEL; - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Reset CFGR register */ - putreg32(0x00000000, STM32L4_RCC_CFGR); + putreg32(0x00000000, STM32_RCC_CFGR); /* Reset enable bits for other clocks than MSI */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval &= ~(RCC_CR_HSION | RCC_CR_HSIKERON | RCC_CR_HSEON | RCC_CR_HSIASFS | RCC_CR_CSSON | RCC_CR_PLLON | RCC_CR_PLLSAI1ON | RCC_CR_PLLSAI2ON); - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Reset PLLCFGR register to reset default */ - putreg32(RCC_PLLCFG_RESET, STM32L4_RCC_PLLCFG); + putreg32(RCC_PLLCFG_RESET, STM32_RCC_PLLCFG); - putreg32(0, STM32L4_RCC_PLLSAI1CFG); - putreg32(RCC_PLLSAI1CFG_PLLN(16), STM32L4_RCC_PLLSAI1CFG); + putreg32(0, STM32_RCC_PLLSAI1CFG); + putreg32(RCC_PLLSAI1CFG_PLLN(16), STM32_RCC_PLLSAI1CFG); - putreg32(0, STM32L4_RCC_PLLSAI2CFG); - putreg32(RCC_PLLSAI2CFG_PLLN(16), STM32L4_RCC_PLLSAI1CFG); + putreg32(0, STM32_RCC_PLLSAI2CFG); + putreg32(RCC_PLLSAI2CFG_PLLN(16), STM32_RCC_PLLSAI1CFG); /* Reset HSEBYP bit */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval &= ~RCC_CR_HSEBYP; - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Disable all interrupts */ - putreg32(0x00000000, STM32L4_RCC_CIER); + putreg32(0x00000000, STM32_RCC_CIER); } static inline void apb_reset(void) { - putreg32(0xffffffff, STM32L4_RCC_APB1RSTR1); - putreg32(0xffffffff, STM32L4_RCC_APB1RSTR2); - putreg32(0xffffffff, STM32L4_RCC_APB2RSTR); - putreg32(0xffffffff, STM32L4_RCC_AHB1RSTR); - putreg32(0xffffffff, STM32L4_RCC_AHB2RSTR); - putreg32(0xffffffff, STM32L4_RCC_AHB3RSTR); - - putreg32(0, STM32L4_RCC_APB1RSTR1); - putreg32(0, STM32L4_RCC_APB1RSTR2); - putreg32(0, STM32L4_RCC_APB2RSTR); - putreg32(0, STM32L4_RCC_AHB1RSTR); - putreg32(0, STM32L4_RCC_AHB2RSTR); - putreg32(0, STM32L4_RCC_AHB3RSTR); + putreg32(0xffffffff, STM32_RCC_APB1RSTR1); + putreg32(0xffffffff, STM32_RCC_APB1RSTR2); + putreg32(0xffffffff, STM32_RCC_APB2RSTR); + putreg32(0xffffffff, STM32_RCC_AHB1RSTR); + putreg32(0xffffffff, STM32_RCC_AHB2RSTR); + putreg32(0xffffffff, STM32_RCC_AHB3RSTR); + + putreg32(0, STM32_RCC_APB1RSTR1); + putreg32(0, STM32_RCC_APB1RSTR2); + putreg32(0, STM32_RCC_APB2RSTR); + putreg32(0, STM32_RCC_AHB1RSTR); + putreg32(0, STM32_RCC_AHB2RSTR); + putreg32(0, STM32_RCC_AHB3RSTR); } #endif @@ -120,15 +120,15 @@ static inline void apb_reset(void) ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_dfumode + * Name: stm32_dfumode * * Description: * Reboot the part in DFU mode (GCC only). * ****************************************************************************/ -#if defined(CONFIG_STM32L4_STM32L4X6) || defined(CONFIG_STM32L4_STM32L4XR) -void stm32l4_dfumode(void) +#if defined(CONFIG_STM32_STM32L4X6) || defined(CONFIG_STM32_STM32L4XR) +void stm32_dfumode(void) { uint32_t regval; boot_call_t boot; @@ -144,10 +144,10 @@ void stm32l4_dfumode(void) /* remap ROM at address zero */ - regval = getreg32(STM32L4_RCC_APB2ENR); + regval = getreg32(STM32_RCC_APB2ENR); regval |= RCC_APB2ENR_SYSCFGEN; - putreg32(regval, STM32L4_RCC_APB2ENR); - putreg32(SYSCFG_MEMRMP_SYSTEM, STM32L4_SYSCFG_MEMRMP); + putreg32(regval, STM32_RCC_APB2ENR); + putreg32(SYSCFG_MEMRMP_SYSTEM, STM32_SYSCFG_MEMRMP); /* set stack pointer and program-counter to ROM values */ diff --git a/arch/arm/src/stm32l4/stm32l4_dfumode.h b/arch/arm/src/stm32l4/stm32l4_dfumode.h index 67cd03b0db0af..b9d02d0c46622 100644 --- a/arch/arm/src/stm32l4/stm32l4_dfumode.h +++ b/arch/arm/src/stm32l4/stm32l4_dfumode.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32L4_STM32L4_DFUMODE_H -#define __ARCH_ARM_SRC_STM32L4_STM32L4_DFUMODE_H +#ifndef __ARCH_ARM_SRC_STM32L4_STM32_DFUMODE_H +#define __ARCH_ARM_SRC_STM32L4_STM32_DFUMODE_H /**************************************************************************** * Included Files @@ -34,15 +34,15 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_dfumode + * Name: stm32_dfumode * * Description: * Reboot the part in DFU mode. * ****************************************************************************/ -#if defined(CONFIG_STM32L4_STM32L4X6) || defined(CONFIG_STM32L4_STM32L4XR) -void stm32l4_dfumode(void) noreturn_function; +#if defined(CONFIG_STM32_STM32L4X6) || defined(CONFIG_STM32_STM32L4XR) +void stm32_dfumode(void) noreturn_function; #endif -#endif /* __ARCH_ARM_SRC_STM32L4_STM32L4_DFUMODE_H */ +#endif /* __ARCH_ARM_SRC_STM32L4_STM32_DFUMODE_H */ diff --git a/arch/arm/src/stm32l4/stm32l4_dma.c b/arch/arm/src/stm32l4/stm32l4_dma.c index 5c2b8826acb28..c0e9bf79add9b 100644 --- a/arch/arm/src/stm32l4/stm32l4_dma.c +++ b/arch/arm/src/stm32l4/stm32l4_dma.c @@ -35,10 +35,10 @@ * family. */ -#if defined(CONFIG_STM32L4_STM32L4X3) || defined(CONFIG_STM32L4_STM32L4X5) || \ - defined(CONFIG_STM32L4_STM32L4X6) +#if defined(CONFIG_STM32_STM32L4X3) || defined(CONFIG_STM32_STM32L4X5) || \ + defined(CONFIG_STM32_STM32L4X6) #include "stm32l4x6xx_dma.c" -#elif defined(CONFIG_STM32L4_STM32L4XR) +#elif defined(CONFIG_STM32_STM32L4XR) #include "stm32l4xrxx_dma.c" #else # error "Unsupported STM32L4 chip" diff --git a/arch/arm/src/stm32l4/stm32l4_dma.h b/arch/arm/src/stm32l4/stm32l4_dma.h index 5044edb200b5d..178dc5ad99f92 100644 --- a/arch/arm/src/stm32l4/stm32l4_dma.h +++ b/arch/arm/src/stm32l4/stm32l4_dma.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32L4_STM32L4_DMA_H -#define __ARCH_ARM_SRC_STM32L4_STM32L4_DMA_H +#ifndef __ARCH_ARM_SRC_STM32L4_STM32_DMA_H +#define __ARCH_ARM_SRC_STM32L4_STM32_DMA_H /**************************************************************************** * Included Files @@ -34,13 +34,13 @@ /* Include the correct DMA register definitions for this STM32 family */ -#if defined(CONFIG_STM32L4_STM32L4X3) +#if defined(CONFIG_STM32_STM32L4X3) # include "hardware/stm32l4x3xx_dma.h" -#elif defined(CONFIG_STM32L4_STM32L4X5) +#elif defined(CONFIG_STM32_STM32L4X5) # include "hardware/stm32l4x5xx_dma.h" -#elif defined(CONFIG_STM32L4_STM32L4X6) +#elif defined(CONFIG_STM32_STM32L4X6) # include "hardware/stm32l4x6xx_dma.h" -#elif defined(CONFIG_STM32L4_STM32L4XR) +#elif defined(CONFIG_STM32_STM32L4XR) # include "hardware/stm32l4xrxx_dma.h" # include "hardware/stm32l4xrxx_dmamux.h" #else @@ -77,20 +77,20 @@ typedef void *DMA_HANDLE; * status - A bit encoded value that provides the completion status. See * the DMASTATUS_* definitions above. * arg - A user-provided value that was provided when - * stm32l4_dmastart() was called. + * stm32_dmastart() was called. */ typedef void (*dma_callback_t)(DMA_HANDLE handle, uint8_t status, void *arg); #ifdef CONFIG_DEBUG_DMA_INFO -struct stm32l4_dmaregs_s +struct stm32_dmaregs_s { uint32_t isr; /* Interrupt Status Register; each channel gets 4 bits */ uint32_t ccr; /* Channel Configuration Register; determines functionality */ uint32_t cndtr; /* Channel Count Register; determines number of transfers */ uint32_t cpar; /* Channel Peripheral Address Register; determines start */ uint32_t cmar; /* Channel Memory Address Register; determines start */ -#ifndef CONFIG_STM32L4_HAVE_DMAMUX +#ifndef CONFIG_STM32_HAVE_DMAMUX uint32_t cselr; /* Channel Selection Register; chooses peripheral bound */ #else struct @@ -126,11 +126,11 @@ extern "C" * Public Function Prototypes ****************************************************************************/ -#if defined(CONFIG_STM32L4_STM32L4X3) || defined(CONFIG_STM32L4_STM32L4X5) || \ - defined(CONFIG_STM32L4_STM32L4X6) +#if defined(CONFIG_STM32_STM32L4X3) || defined(CONFIG_STM32_STM32L4X5) || \ + defined(CONFIG_STM32_STM32L4X6) /**************************************************************************** - * Name: stm32l4_dmachannel + * Name: stm32_dmachannel * * Description: * Allocate a DMA channel. This function gives the caller mutually @@ -139,11 +139,11 @@ extern "C" * channel cannot do DMA concurrently! See the DMACHAN_* definitions in * stm32l4_dma.h. * - * If the DMA channel is not available, then stm32l4_dmachannel() will + * If the DMA channel is not available, then stm32_dmachannel() will * wait until the holder of the channel relinquishes the channel by - * calling stm32l4_dmafree(). WARNING: If you have two devices sharing a + * calling stm32_dmafree(). WARNING: If you have two devices sharing a * DMA channel and the code never releases the channel, the - * stm32l4_dmachannel call for the other will hang forever in this + * stm32_dmachannel call for the other will hang forever in this * function! Don't let your design do that! * * Hmm.. I suppose this interface could be extended to make a non-blocking @@ -166,9 +166,9 @@ extern "C" * ****************************************************************************/ -DMA_HANDLE stm32l4_dmachannel(unsigned int chan); +DMA_HANDLE stm32_dmachannel(unsigned int chan); -#elif defined(CONFIG_STM32L4_STM32L4XR) +#elif defined(CONFIG_STM32_STM32L4XR) /**************************************************************************** * Name: stm32_dmachannel @@ -195,20 +195,20 @@ DMA_HANDLE stm32l4_dmachannel(unsigned int chan); * ****************************************************************************/ -DMA_HANDLE stm32l4_dmachannel(unsigned int dmamap); +DMA_HANDLE stm32_dmachannel(unsigned int dmamap); #endif /**************************************************************************** - * Name: stm32l4_dmafree + * Name: stm32_dmafree * * Description: * Release a DMA channel. If another thread is waiting for this DMA - * channel in a call to stm32l4_dmachannel, then this function will + * channel in a call to stm32_dmachannel, then this function will * re-assign the DMA channel to that thread and wake it up. * * NOTE: The 'handle' used in this argument must NEVER be used again - * until stm32l4_dmachannel() is called again to re-gain access to + * until stm32_dmachannel() is called again to re-gain access to * the channel. * * Returned Value: @@ -220,64 +220,64 @@ DMA_HANDLE stm32l4_dmachannel(unsigned int dmamap); * ****************************************************************************/ -void stm32l4_dmafree(DMA_HANDLE handle); +void stm32_dmafree(DMA_HANDLE handle); /**************************************************************************** - * Name: stm32l4_dmasetup + * Name: stm32_dmasetup * * Description: * Configure DMA before using * ****************************************************************************/ -void stm32l4_dmasetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr, +void stm32_dmasetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr, size_t ntransfers, uint32_t ccr); /**************************************************************************** - * Name: stm32l4_dmastart + * Name: stm32_dmastart * * Description: * Start the DMA transfer * * Assumptions: - * - DMA handle allocated by stm32l4_dmachannel() + * - DMA handle allocated by stm32_dmachannel() * - No DMA in progress * ****************************************************************************/ -void stm32l4_dmastart(DMA_HANDLE handle, dma_callback_t callback, void *arg, +void stm32_dmastart(DMA_HANDLE handle, dma_callback_t callback, void *arg, bool half); /**************************************************************************** - * Name: stm32l4_dmastop + * Name: stm32_dmastop * * Description: - * Cancel the DMA. After stm32l4_dmastop() is called, the DMA channel is - * reset and stm32l4_dmasetup() must be called before stm32l4_dmastart() + * Cancel the DMA. After stm32_dmastop() is called, the DMA channel is + * reset and stm32_dmasetup() must be called before stm32_dmastart() * can be called again * * Assumptions: - * - DMA handle allocated by stm32l4_dmachannel() + * - DMA handle allocated by stm32_dmachannel() * ****************************************************************************/ -void stm32l4_dmastop(DMA_HANDLE handle); +void stm32_dmastop(DMA_HANDLE handle); /**************************************************************************** - * Name: stm32l4_dmaresidual + * Name: stm32_dmaresidual * * Description: * Returns the number of bytes remaining to be transferred * * Assumptions: - * - DMA handle allocated by stm32l4_dmachannel() + * - DMA handle allocated by stm32_dmachannel() * ****************************************************************************/ -size_t stm32l4_dmaresidual(DMA_HANDLE handle); +size_t stm32_dmaresidual(DMA_HANDLE handle); /**************************************************************************** - * Name: stm32l4_dmacapable + * Name: stm32_dmacapable * * Description: * Check if the DMA controller can transfer data to/from given memory @@ -291,45 +291,45 @@ size_t stm32l4_dmaresidual(DMA_HANDLE handle); * ****************************************************************************/ -#ifdef CONFIG_STM32L4_DMACAPABLE -bool stm32l4_dmacapable(uintptr_t maddr, uint32_t count, uint32_t ccr); +#ifdef CONFIG_STM32_DMACAPABLE +bool stm32_dmacapable(uintptr_t maddr, uint32_t count, uint32_t ccr); #else -# define stm32l4_dmacapable(maddr, count, ccr) (true) +# define stm32_dmacapable(maddr, count, ccr) (true) #endif /**************************************************************************** - * Name: stm32l4_dmasample + * Name: stm32_dmasample * * Description: * Sample DMA register contents * * Assumptions: - * - DMA handle allocated by stm32l4_dmachannel() + * - DMA handle allocated by stm32_dmachannel() * ****************************************************************************/ #ifdef CONFIG_DEBUG_DMA_INFO -void stm32l4_dmasample(DMA_HANDLE handle, struct stm32l4_dmaregs_s *regs); +void stm32_dmasample(DMA_HANDLE handle, struct stm32_dmaregs_s *regs); #else -# define stm32l4_dmasample(handle,regs) ((void)0) +# define stm32_dmasample(handle,regs) ((void)0) #endif /**************************************************************************** - * Name: stm32l4_dmadump + * Name: stm32_dmadump * * Description: * Dump previously sampled DMA register contents * * Assumptions: - * - DMA handle allocated by stm32l4_dmachannel() + * - DMA handle allocated by stm32_dmachannel() * ****************************************************************************/ #ifdef CONFIG_DEBUG_DMA_INFO -void stm32l4_dmadump(DMA_HANDLE handle, const struct stm32l4_dmaregs_s *regs, +void stm32_dmadump(DMA_HANDLE handle, const struct stm32_dmaregs_s *regs, const char *msg); #else -# define stm32l4_dmadump(handle,regs,msg) ((void)0) +# define stm32_dmadump(handle,regs,msg) ((void)0) #endif #undef EXTERN @@ -338,4 +338,4 @@ void stm32l4_dmadump(DMA_HANDLE handle, const struct stm32l4_dmaregs_s *regs, #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32L4_STM32L4_DMA_H */ +#endif /* __ARCH_ARM_SRC_STM32L4_STM32_DMA_H */ diff --git a/arch/arm/src/stm32l4/stm32l4_dumpgpio.c b/arch/arm/src/stm32l4/stm32l4_dumpgpio.c index a9f32ad8a822f..96b483ff201c9 100644 --- a/arch/arm/src/stm32l4/stm32l4_dumpgpio.c +++ b/arch/arm/src/stm32l4/stm32l4_dumpgpio.c @@ -50,31 +50,31 @@ /* Port letters for prettier debug output */ -static const char g_portchar[STM32L4_NPORTS] = +static const char g_portchar[STM32_NPORTS] = { -#if STM32L4_NPORTS > 11 +#if STM32_NPORTS > 11 # error "Additional support required for this number of GPIOs" -#elif STM32L4_NPORTS > 10 +#elif STM32_NPORTS > 10 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 'I', 'J', 'K' -#elif STM32L4_NPORTS > 9 +#elif STM32_NPORTS > 9 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 'I', 'J' -#elif STM32L4_NPORTS > 8 +#elif STM32_NPORTS > 8 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 'I' -#elif STM32L4_NPORTS > 7 +#elif STM32_NPORTS > 7 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H' -#elif STM32L4_NPORTS > 6 +#elif STM32_NPORTS > 6 'A', 'B', 'C', 'D', 'E', 'F', 'G' -#elif STM32L4_NPORTS > 5 +#elif STM32_NPORTS > 5 'A', 'B', 'C', 'D', 'E', 'F' -#elif STM32L4_NPORTS > 4 +#elif STM32_NPORTS > 4 'A', 'B', 'C', 'D', 'E' -#elif STM32L4_NPORTS > 3 +#elif STM32_NPORTS > 3 'A', 'B', 'C', 'D' -#elif STM32L4_NPORTS > 2 +#elif STM32_NPORTS > 2 'A', 'B', 'C' -#elif STM32L4_NPORTS > 1 +#elif STM32_NPORTS > 1 'A', 'B' -#elif STM32L4_NPORTS > 0 +#elif STM32_NPORTS > 0 'A' #else # error "Bad number of GPIOs" @@ -86,14 +86,14 @@ static const char g_portchar[STM32L4_NPORTS] = ****************************************************************************/ /**************************************************************************** - * Function: stm32l4_dumpgpio + * Function: stm32_dumpgpio * * Description: * Dump all GPIO registers associated with the provided base address * ****************************************************************************/ -int stm32l4_dumpgpio(uint32_t pinset, const char *msg) +int stm32_dumpgpio(uint32_t pinset, const char *msg) { irqstate_t flags; uint32_t base; @@ -108,33 +108,33 @@ int stm32l4_dumpgpio(uint32_t pinset, const char *msg) flags = enter_critical_section(); - DEBUGASSERT(port < STM32L4_NPORTS); + DEBUGASSERT(port < STM32_NPORTS); _info("GPIO%c pinset: %08" PRIx32 " base: %08" PRIx32 " -- %s\n", g_portchar[port], pinset, base, msg); - if ((getreg32(STM32L4_RCC_AHB2ENR) & RCC_AHB2ENR_GPIOEN(port)) != 0) + if ((getreg32(STM32_RCC_AHB2ENR) & RCC_AHB2ENR_GPIOEN(port)) != 0) { _info(" MODE: %08" PRIx32 " OTYPE: %04" PRIx32 " OSPEED: %08" PRIx32 " PUPDR: %08" PRIx32 "\n", - getreg32(base + STM32L4_GPIO_MODER_OFFSET), - getreg32(base + STM32L4_GPIO_OTYPER_OFFSET), - getreg32(base + STM32L4_GPIO_OSPEED_OFFSET), - getreg32(base + STM32L4_GPIO_PUPDR_OFFSET)); + getreg32(base + STM32_GPIO_MODER_OFFSET), + getreg32(base + STM32_GPIO_OTYPER_OFFSET), + getreg32(base + STM32_GPIO_OSPEED_OFFSET), + getreg32(base + STM32_GPIO_PUPDR_OFFSET)); _info(" IDR: %04" PRIx32 " ODR: %04" PRIx32 " BSRR: %08" PRIx32 " LCKR: %04x\n", - getreg32(base + STM32L4_GPIO_IDR_OFFSET), - getreg32(base + STM32L4_GPIO_ODR_OFFSET), - getreg32(base + STM32L4_GPIO_BSRR_OFFSET), - getreg32(base + STM32L4_GPIO_LCKR_OFFSET)); + getreg32(base + STM32_GPIO_IDR_OFFSET), + getreg32(base + STM32_GPIO_ODR_OFFSET), + getreg32(base + STM32_GPIO_BSRR_OFFSET), + getreg32(base + STM32_GPIO_LCKR_OFFSET)); _info(" AFRH: %08" PRIx32 " AFRL: %08" PRIx32 "\n", - getreg32(base + STM32L4_GPIO_AFRH_OFFSET), - getreg32(base + STM32L4_GPIO_AFRL_OFFSET)); + getreg32(base + STM32_GPIO_AFRH_OFFSET), + getreg32(base + STM32_GPIO_AFRL_OFFSET)); } else { _info(" GPIO%c not enabled: AHB2ENR: %08" PRIx32 "\n", - g_portchar[port], getreg32(STM32L4_RCC_AHB2ENR)); + g_portchar[port], getreg32(STM32_RCC_AHB2ENR)); } leave_critical_section(flags); diff --git a/arch/arm/src/stm32l4/stm32l4_exti.h b/arch/arm/src/stm32l4/stm32l4_exti.h index 212fab58d3139..9b8b2e77cbe1b 100644 --- a/arch/arm/src/stm32l4/stm32l4_exti.h +++ b/arch/arm/src/stm32l4/stm32l4_exti.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32L4_STM32L4_EXTI_H -#define __ARCH_ARM_SRC_STM32L4_STM32L4_EXTI_H +#ifndef __ARCH_ARM_SRC_STM32L4_STM32_EXTI_H +#define __ARCH_ARM_SRC_STM32L4_STM32_EXTI_H /**************************************************************************** * Included Files @@ -54,7 +54,7 @@ extern "C" ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_gpiosetevent + * Name: stm32_gpiosetevent * * Description: * Sets/clears GPIO based event and interrupt triggers. @@ -73,11 +73,11 @@ extern "C" * ****************************************************************************/ -int stm32l4_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, +int stm32_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, bool event, xcpt_t func, void *arg); /**************************************************************************** - * Name: stm32l4_exti_alarm + * Name: stm32_exti_alarm * * Description: * Sets/clears EXTI alarm interrupt. @@ -95,12 +95,12 @@ int stm32l4_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, ****************************************************************************/ #ifdef CONFIG_RTC_ALARM -int stm32l4_exti_alarm(bool risingedge, bool fallingedge, bool event, +int stm32_exti_alarm(bool risingedge, bool fallingedge, bool event, xcpt_t func, void *arg); #endif /**************************************************************************** - * Name: stm32l4_exti_wakeup + * Name: stm32_exti_wakeup * * Description: * Sets/clears EXTI wakeup interrupt. @@ -118,12 +118,12 @@ int stm32l4_exti_alarm(bool risingedge, bool fallingedge, bool event, ****************************************************************************/ #ifdef CONFIG_RTC_PERIODIC -int stm32l4_exti_wakeup(bool risingedge, bool fallingedge, bool event, +int stm32_exti_wakeup(bool risingedge, bool fallingedge, bool event, xcpt_t func, void *arg); #endif /**************************************************************************** - * Name: stm32l4_exti_comp + * Name: stm32_exti_comp * * Description: * Sets/clears comparator based events and interrupt triggers. @@ -141,8 +141,8 @@ int stm32l4_exti_wakeup(bool risingedge, bool fallingedge, bool event, * ****************************************************************************/ -#ifdef CONFIG_STM32L4_COMP -int stm32l4_exti_comp(int cmp, bool risingedge, bool fallingedge, +#ifdef CONFIG_STM32_COMP +int stm32_exti_comp(int cmp, bool risingedge, bool fallingedge, bool event, xcpt_t func, void *arg); #endif @@ -152,4 +152,4 @@ int stm32l4_exti_comp(int cmp, bool risingedge, bool fallingedge, #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32L4_STM32L4_EXTI_H */ +#endif /* __ARCH_ARM_SRC_STM32L4_STM32_EXTI_H */ diff --git a/arch/arm/src/stm32l4/stm32l4_exti_alarm.c b/arch/arm/src/stm32l4/stm32l4_exti_alarm.c index c67451e4437d3..34f2632605085 100644 --- a/arch/arm/src/stm32l4/stm32l4_exti_alarm.c +++ b/arch/arm/src/stm32l4/stm32l4_exti_alarm.c @@ -53,14 +53,14 @@ static void *g_callback_arg; ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_exti_alarm_isr + * Name: stm32_exti_alarm_isr * * Description: * EXTI ALARM interrupt service routine/dispatcher * ****************************************************************************/ -static int stm32l4_exti_alarm_isr(int irq, void *context, void *arg) +static int stm32_exti_alarm_isr(int irq, void *context, void *arg) { int ret = OK; @@ -73,7 +73,7 @@ static int stm32l4_exti_alarm_isr(int irq, void *context, void *arg) /* Clear the pending EXTI interrupt */ - putreg32(EXTI1_RTC_ALARM, STM32L4_EXTI1_PR); + putreg32(EXTI1_RTC_ALARM, STM32_EXTI1_PR); return ret; } @@ -83,7 +83,7 @@ static int stm32l4_exti_alarm_isr(int irq, void *context, void *arg) ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_exti_alarm + * Name: stm32_exti_alarm * * Description: * Sets/clears EXTI alarm interrupt. @@ -99,7 +99,7 @@ static int stm32l4_exti_alarm_isr(int irq, void *context, void *arg) * ****************************************************************************/ -int stm32l4_exti_alarm(bool risingedge, bool fallingedge, bool event, +int stm32_exti_alarm(bool risingedge, bool fallingedge, bool event, xcpt_t func, void *arg) { g_alarm_callback = func; @@ -109,29 +109,29 @@ int stm32l4_exti_alarm(bool risingedge, bool fallingedge, bool event, if (func) { - irq_attach(STM32L4_IRQ_RTCALRM, stm32l4_exti_alarm_isr, NULL); - up_enable_irq(STM32L4_IRQ_RTCALRM); + irq_attach(STM32_IRQ_RTCALRM, stm32_exti_alarm_isr, NULL); + up_enable_irq(STM32_IRQ_RTCALRM); } else { - up_disable_irq(STM32L4_IRQ_RTCALRM); + up_disable_irq(STM32_IRQ_RTCALRM); } /* Configure rising/falling edges */ - modifyreg32(STM32L4_EXTI1_RTSR, + modifyreg32(STM32_EXTI1_RTSR, risingedge ? 0 : EXTI1_RTC_ALARM, risingedge ? EXTI1_RTC_ALARM : 0); - modifyreg32(STM32L4_EXTI1_FTSR, + modifyreg32(STM32_EXTI1_FTSR, fallingedge ? 0 : EXTI1_RTC_ALARM, fallingedge ? EXTI1_RTC_ALARM : 0); /* Enable Events and Interrupts */ - modifyreg32(STM32L4_EXTI1_EMR, + modifyreg32(STM32_EXTI1_EMR, event ? 0 : EXTI1_RTC_ALARM, event ? EXTI1_RTC_ALARM : 0); - modifyreg32(STM32L4_EXTI1_IMR, + modifyreg32(STM32_EXTI1_IMR, func ? 0 : EXTI1_RTC_ALARM, func ? EXTI1_RTC_ALARM : 0); diff --git a/arch/arm/src/stm32l4/stm32l4_exti_comp.c b/arch/arm/src/stm32l4/stm32l4_exti_comp.c index b3b39ce340fa9..8579f144a093b 100644 --- a/arch/arm/src/stm32l4/stm32l4_exti_comp.c +++ b/arch/arm/src/stm32l4/stm32l4_exti_comp.c @@ -64,14 +64,14 @@ struct comp_callback_s /* Interrupt handlers attached to the COMP EXTI lines */ -static struct comp_callback_s g_comp_handlers[STM32L4_COMP_NUM]; +static struct comp_callback_s g_comp_handlers[STM32_COMP_NUM]; /* Comparator EXTI lines */ -static const uint32_t g_comp_lines[STM32L4_COMP_NUM] = +static const uint32_t g_comp_lines[STM32_COMP_NUM] = { -#if defined(CONFIG_STM32L4_STM32L4X3) || defined(CONFIG_STM32L4_STM32L4X5) || \ - defined(CONFIG_STM32L4_STM32L4X6) || defined(CONFIG_STM32L4_STM32L4XR) +#if defined(CONFIG_STM32_STM32L4X3) || defined(CONFIG_STM32_STM32L4X5) || \ + defined(CONFIG_STM32_STM32L4X6) || defined(CONFIG_STM32_STM32L4XR) EXTI1_COMP1, EXTI1_COMP2 #else @@ -83,7 +83,7 @@ static const uint32_t g_comp_lines[STM32L4_COMP_NUM] = * Private Functions ****************************************************************************/ -static int stm32l4_exti_comp_isr(int irq, void *context, void *arg) +static int stm32_exti_comp_isr(int irq, void *context, void *arg) { uint32_t pr; uint32_t ln; @@ -92,15 +92,15 @@ static int stm32l4_exti_comp_isr(int irq, void *context, void *arg) /* Examine the state of each comparator line and dispatch interrupts */ - pr = getreg32(STM32L4_EXTI1_PR); - for (i = 0; i < STM32L4_COMP_NUM; i++) + pr = getreg32(STM32_EXTI1_PR); + for (i = 0; i < STM32_COMP_NUM; i++) { ln = g_comp_lines[i]; if ((pr & ln) != 0) { /* Clear the pending interrupt */ - putreg32(ln, STM32L4_EXTI1_PR); + putreg32(ln, STM32_EXTI1_PR); if (g_comp_handlers[i].callback != NULL) { xcpt_t callback = g_comp_handlers[i].callback; @@ -118,7 +118,7 @@ static int stm32l4_exti_comp_isr(int irq, void *context, void *arg) ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_exti_comp + * Name: stm32_exti_comp * * Description: * Sets/clears comparator based events and interrupt triggers. @@ -136,7 +136,7 @@ static int stm32l4_exti_comp_isr(int irq, void *context, void *arg) * ****************************************************************************/ -int stm32l4_exti_comp(int cmp, bool risingedge, bool fallingedge, +int stm32_exti_comp(int cmp, bool risingedge, bool fallingedge, bool event, xcpt_t func, void *arg) { irqstate_t flags; @@ -152,25 +152,25 @@ int stm32l4_exti_comp(int cmp, bool risingedge, bool fallingedge, if (func != NULL) { - irq_attach(STM32L4_IRQ_COMP, stm32l4_exti_comp_isr, NULL); - up_enable_irq(STM32L4_IRQ_COMP); + irq_attach(STM32_IRQ_COMP, stm32_exti_comp_isr, NULL); + up_enable_irq(STM32_IRQ_COMP); } else { - up_disable_irq(STM32L4_IRQ_COMP); + up_disable_irq(STM32_IRQ_COMP); } /* Configure rising/falling edges */ - modifyreg32(STM32L4_EXTI1_RTSR, risingedge ? + modifyreg32(STM32_EXTI1_RTSR, risingedge ? 0 : ln, risingedge ? ln : 0); - modifyreg32(STM32L4_EXTI1_FTSR, fallingedge ? + modifyreg32(STM32_EXTI1_FTSR, fallingedge ? 0 : ln, fallingedge ? ln : 0); /* Enable Events and Interrupts */ - modifyreg32(STM32L4_EXTI1_EMR, event ? 0 : ln, event ? ln : 0); - modifyreg32(STM32L4_EXTI1_IMR, func ? 0 : ln, func ? ln : 0); + modifyreg32(STM32_EXTI1_EMR, event ? 0 : ln, event ? ln : 0); + modifyreg32(STM32_EXTI1_IMR, func ? 0 : ln, func ? ln : 0); /* Get the previous IRQ handler and save the new IRQ handler. */ diff --git a/arch/arm/src/stm32l4/stm32l4_exti_gpio.c b/arch/arm/src/stm32l4/stm32l4_exti_gpio.c index 2b02e9d15aa0c..1418d7c75d644 100644 --- a/arch/arm/src/stm32l4/stm32l4_exti_gpio.c +++ b/arch/arm/src/stm32l4/stm32l4_exti_gpio.c @@ -66,13 +66,13 @@ static struct gpio_callback_s g_gpio_handlers[16]; * Interrupt Service Routines - Dispatchers ****************************************************************************/ -static int stm32l4_exti0_isr(int irq, void *context, void *arg) +static int stm32_exti0_isr(int irq, void *context, void *arg) { int ret = OK; /* Clear the pending interrupt */ - putreg32(0x0001, STM32L4_EXTI1_PR); + putreg32(0x0001, STM32_EXTI1_PR); /* And dispatch the interrupt to the handler */ @@ -87,13 +87,13 @@ static int stm32l4_exti0_isr(int irq, void *context, void *arg) return ret; } -static int stm32l4_exti1_isr(int irq, void *context, void *arg) +static int stm32_exti1_isr(int irq, void *context, void *arg) { int ret = OK; /* Clear the pending interrupt */ - putreg32(0x0002, STM32L4_EXTI1_PR); + putreg32(0x0002, STM32_EXTI1_PR); /* And dispatch the interrupt to the handler */ @@ -108,13 +108,13 @@ static int stm32l4_exti1_isr(int irq, void *context, void *arg) return ret; } -static int stm32l4_exti2_isr(int irq, void *context, void *arg) +static int stm32_exti2_isr(int irq, void *context, void *arg) { int ret = OK; /* Clear the pending interrupt */ - putreg32(0x0004, STM32L4_EXTI1_PR); + putreg32(0x0004, STM32_EXTI1_PR); /* And dispatch the interrupt to the handler */ @@ -129,13 +129,13 @@ static int stm32l4_exti2_isr(int irq, void *context, void *arg) return ret; } -static int stm32l4_exti3_isr(int irq, void *context, void *arg) +static int stm32_exti3_isr(int irq, void *context, void *arg) { int ret = OK; /* Clear the pending interrupt */ - putreg32(0x0008, STM32L4_EXTI1_PR); + putreg32(0x0008, STM32_EXTI1_PR); /* And dispatch the interrupt to the handler */ @@ -150,13 +150,13 @@ static int stm32l4_exti3_isr(int irq, void *context, void *arg) return ret; } -static int stm32l4_exti4_isr(int irq, void *context, void *arg) +static int stm32_exti4_isr(int irq, void *context, void *arg) { int ret = OK; /* Clear the pending interrupt */ - putreg32(0x0010, STM32L4_EXTI1_PR); + putreg32(0x0010, STM32_EXTI1_PR); /* And dispatch the interrupt to the handler */ @@ -171,7 +171,7 @@ static int stm32l4_exti4_isr(int irq, void *context, void *arg) return ret; } -static int stm32l4_exti_multiisr(int irq, void *context, void *arg, +static int stm32_exti_multiisr(int irq, void *context, void *arg, int first, int last) { uint32_t pr; @@ -180,7 +180,7 @@ static int stm32l4_exti_multiisr(int irq, void *context, void *arg, /* Examine the state of each pin in the group */ - pr = getreg32(STM32L4_EXTI1_PR); + pr = getreg32(STM32_EXTI1_PR); /* And dispatch the interrupt to the handler */ @@ -193,7 +193,7 @@ static int stm32l4_exti_multiisr(int irq, void *context, void *arg, { /* Clear the pending interrupt */ - putreg32(mask, STM32L4_EXTI1_PR); + putreg32(mask, STM32_EXTI1_PR); /* And dispatch the interrupt to the handler */ @@ -215,14 +215,14 @@ static int stm32l4_exti_multiisr(int irq, void *context, void *arg, return ret; } -static int stm32l4_exti95_isr(int irq, void *context, void *arg) +static int stm32_exti95_isr(int irq, void *context, void *arg) { - return stm32l4_exti_multiisr(irq, context, arg, 5, 9); + return stm32_exti_multiisr(irq, context, arg, 5, 9); } -static int stm32l4_exti1510_isr(int irq, void *context, void *arg) +static int stm32_exti1510_isr(int irq, void *context, void *arg) { - return stm32l4_exti_multiisr(irq, context, arg, 10, 15); + return stm32_exti_multiisr(irq, context, arg, 10, 15); } /**************************************************************************** @@ -230,7 +230,7 @@ static int stm32l4_exti1510_isr(int irq, void *context, void *arg) ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_gpiosetevent + * Name: stm32_gpiosetevent * * Description: * Sets/clears GPIO based event and interrupt triggers. @@ -252,12 +252,12 @@ static int stm32l4_exti1510_isr(int irq, void *context, void *arg) * ****************************************************************************/ -int stm32l4_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, +int stm32_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, bool event, xcpt_t func, void *arg) { struct gpio_callback_s *shared_cbs; uint32_t pin = pinset & GPIO_PIN_MASK; - uint32_t exti = STM32L4_EXTI1_BIT(pin); + uint32_t exti = STM32_EXTI1_BIT(pin); int irq; xcpt_t handler; int nshared; @@ -267,43 +267,43 @@ int stm32l4_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, if (pin < 5) { - irq = pin + STM32L4_IRQ_EXTI0; + irq = pin + STM32_IRQ_EXTI0; nshared = 1; shared_cbs = &g_gpio_handlers[pin]; switch (pin) { case 0: - handler = stm32l4_exti0_isr; + handler = stm32_exti0_isr; break; case 1: - handler = stm32l4_exti1_isr; + handler = stm32_exti1_isr; break; case 2: - handler = stm32l4_exti2_isr; + handler = stm32_exti2_isr; break; case 3: - handler = stm32l4_exti3_isr; + handler = stm32_exti3_isr; break; default: - handler = stm32l4_exti4_isr; + handler = stm32_exti4_isr; break; } } else if (pin < 10) { - irq = STM32L4_IRQ_EXTI95; - handler = stm32l4_exti95_isr; + irq = STM32_IRQ_EXTI95; + handler = stm32_exti95_isr; shared_cbs = &g_gpio_handlers[5]; nshared = 5; } else { - irq = STM32L4_IRQ_EXTI1510; - handler = stm32l4_exti1510_isr; + irq = STM32_IRQ_EXTI1510; + handler = stm32_exti1510_isr; shared_cbs = &g_gpio_handlers[10]; nshared = 6; } @@ -349,23 +349,23 @@ int stm32l4_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, pinset |= GPIO_EXTI; } - stm32l4_configgpio(pinset); + stm32_configgpio(pinset); /* Configure rising/falling edges */ - modifyreg32(STM32L4_EXTI1_RTSR, + modifyreg32(STM32_EXTI1_RTSR, risingedge ? 0 : exti, risingedge ? exti : 0); - modifyreg32(STM32L4_EXTI1_FTSR, + modifyreg32(STM32_EXTI1_FTSR, fallingedge ? 0 : exti, fallingedge ? exti : 0); /* Enable Events and Interrupts */ - modifyreg32(STM32L4_EXTI1_EMR, + modifyreg32(STM32_EXTI1_EMR, event ? 0 : exti, event ? exti : 0); - modifyreg32(STM32L4_EXTI1_IMR, + modifyreg32(STM32_EXTI1_IMR, func ? 0 : exti, func ? exti : 0); diff --git a/arch/arm/src/stm32l4/stm32l4_exti_pwr.c b/arch/arm/src/stm32l4/stm32l4_exti_pwr.c index b18efc39ef771..01a6dd882f8f5 100644 --- a/arch/arm/src/stm32l4/stm32l4_exti_pwr.c +++ b/arch/arm/src/stm32l4/stm32l4_exti_pwr.c @@ -58,20 +58,20 @@ static void *g_callback_arg; ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_exti_pvd_isr + * Name: stm32_exti_pvd_isr * * Description: * EXTI PVD interrupt service routine/dispatcher * ****************************************************************************/ -static int stm32l4_exti_pvd_isr(int irq, void *context, void *arg) +static int stm32_exti_pvd_isr(int irq, void *context, void *arg) { int ret = OK; /* Clear the pending EXTI interrupt */ - putreg32(EXTI1_PVD_LINE, STM32L4_EXTI1_PR); + putreg32(EXTI1_PVD_LINE, STM32_EXTI1_PR); /* And dispatch the interrupt to the handler */ @@ -88,7 +88,7 @@ static int stm32l4_exti_pvd_isr(int irq, void *context, void *arg) ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_exti_pvd + * Name: stm32_exti_pvd * * Description: * Sets/clears EXTI PVD interrupt. @@ -104,7 +104,7 @@ static int stm32l4_exti_pvd_isr(int irq, void *context, void *arg) * ****************************************************************************/ -int stm32l4_exti_pvd(bool risingedge, bool fallingedge, bool event, +int stm32_exti_pvd(bool risingedge, bool fallingedge, bool event, xcpt_t func, void *arg) { /* Get the previous GPIO IRQ handler; Save the new IRQ handler. */ @@ -116,29 +116,29 @@ int stm32l4_exti_pvd(bool risingedge, bool fallingedge, bool event, if (func) { - irq_attach(STM32L4_IRQ_PVD, stm32l4_exti_pvd_isr, NULL); - up_enable_irq(STM32L4_IRQ_PVD); + irq_attach(STM32_IRQ_PVD, stm32_exti_pvd_isr, NULL); + up_enable_irq(STM32_IRQ_PVD); } else { - up_disable_irq(STM32L4_IRQ_PVD); + up_disable_irq(STM32_IRQ_PVD); } /* Configure rising/falling edges */ - modifyreg32(STM32L4_EXTI1_RTSR, + modifyreg32(STM32_EXTI1_RTSR, risingedge ? 0 : EXTI1_PVD_LINE, risingedge ? EXTI1_PVD_LINE : 0); - modifyreg32(STM32L4_EXTI1_FTSR, + modifyreg32(STM32_EXTI1_FTSR, fallingedge ? 0 : EXTI1_PVD_LINE, fallingedge ? EXTI1_PVD_LINE : 0); /* Enable Events and Interrupts */ - modifyreg32(STM32L4_EXTI1_EMR, + modifyreg32(STM32_EXTI1_EMR, event ? 0 : EXTI1_PVD_LINE, event ? EXTI1_PVD_LINE : 0); - modifyreg32(STM32L4_EXTI1_IMR, + modifyreg32(STM32_EXTI1_IMR, func ? 0 : EXTI1_PVD_LINE, func ? EXTI1_PVD_LINE : 0); diff --git a/arch/arm/src/stm32l4/stm32l4_exti_pwr.h b/arch/arm/src/stm32l4/stm32l4_exti_pwr.h index a9d6b3f0ec0d0..31c177d19ee9c 100644 --- a/arch/arm/src/stm32l4/stm32l4_exti_pwr.h +++ b/arch/arm/src/stm32l4/stm32l4_exti_pwr.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef STM32L4_EXTI_PWR_H_ -#define STM32L4_EXTI_PWR_H_ +#ifndef __ARCH_ARM_SRC_STM32L4_EXTI_PWR_H +#define __ARCH_ARM_SRC_STM32L4_EXTI_PWR_H /**************************************************************************** * Included Files @@ -35,7 +35,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_exti_pvd + * Name: stm32_exti_pvd * * Description: * Sets/clears EXTI PVD interrupt. @@ -52,7 +52,7 @@ * ****************************************************************************/ -int stm32l4_exti_pvd(bool risingedge, bool fallingedge, bool event, +int stm32_exti_pvd(bool risingedge, bool fallingedge, bool event, xcpt_t func, void *arg); -#endif /* STM32L4_EXTI_PWR_H_ */ +#endif /* __ARCH_ARM_SRC_STM32L4_EXTI_PWR_H */ diff --git a/arch/arm/src/stm32l4/stm32l4_exti_wakeup.c b/arch/arm/src/stm32l4/stm32l4_exti_wakeup.c index 24f4e00b3055c..dd0c8b7d44046 100644 --- a/arch/arm/src/stm32l4/stm32l4_exti_wakeup.c +++ b/arch/arm/src/stm32l4/stm32l4_exti_wakeup.c @@ -53,14 +53,14 @@ static void *g_callback_arg; ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_exti_wakeup_isr + * Name: stm32_exti_wakeup_isr * * Description: * EXTI periodic WAKEUP interrupt service routine/dispatcher * ****************************************************************************/ -static int stm32l4_exti_wakeup_isr(int irq, void *context, void *arg) +static int stm32_exti_wakeup_isr(int irq, void *context, void *arg) { int ret = OK; @@ -73,7 +73,7 @@ static int stm32l4_exti_wakeup_isr(int irq, void *context, void *arg) /* Clear the pending EXTI interrupt */ - putreg32(EXTI1_RTC_WAKEUP, STM32L4_EXTI1_PR); + putreg32(EXTI1_RTC_WAKEUP, STM32_EXTI1_PR); return ret; } @@ -83,7 +83,7 @@ static int stm32l4_exti_wakeup_isr(int irq, void *context, void *arg) ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_exti_wakeup + * Name: stm32_exti_wakeup * * Description: * Sets/clears EXTI wakeup interrupt. @@ -99,7 +99,7 @@ static int stm32l4_exti_wakeup_isr(int irq, void *context, void *arg) * ****************************************************************************/ -int stm32l4_exti_wakeup(bool risingedge, bool fallingedge, bool event, +int stm32_exti_wakeup(bool risingedge, bool fallingedge, bool event, xcpt_t func, void *arg) { g_wakeup_callback = func; @@ -109,29 +109,29 @@ int stm32l4_exti_wakeup(bool risingedge, bool fallingedge, bool event, if (func) { - irq_attach(STM32L4_IRQ_RTC_WKUP, stm32l4_exti_wakeup_isr, NULL); - up_enable_irq(STM32L4_IRQ_RTC_WKUP); + irq_attach(STM32_IRQ_RTC_WKUP, stm32_exti_wakeup_isr, NULL); + up_enable_irq(STM32_IRQ_RTC_WKUP); } else { - up_disable_irq(STM32L4_IRQ_RTC_WKUP); + up_disable_irq(STM32_IRQ_RTC_WKUP); } /* Configure rising/falling edges */ - modifyreg32(STM32L4_EXTI1_RTSR, + modifyreg32(STM32_EXTI1_RTSR, risingedge ? 0 : EXTI1_RTC_WAKEUP, risingedge ? EXTI1_RTC_WAKEUP : 0); - modifyreg32(STM32L4_EXTI1_FTSR, + modifyreg32(STM32_EXTI1_FTSR, fallingedge ? 0 : EXTI1_RTC_WAKEUP, fallingedge ? EXTI1_RTC_WAKEUP : 0); /* Enable Events and Interrupts */ - modifyreg32(STM32L4_EXTI1_EMR, + modifyreg32(STM32_EXTI1_EMR, event ? 0 : EXTI1_RTC_WAKEUP, event ? EXTI1_RTC_WAKEUP : 0); - modifyreg32(STM32L4_EXTI1_IMR, + modifyreg32(STM32_EXTI1_IMR, func ? 0 : EXTI1_RTC_WAKEUP, func ? EXTI1_RTC_WAKEUP : 0); diff --git a/arch/arm/src/stm32l4/stm32l4_firewall.c b/arch/arm/src/stm32l4/stm32l4_firewall.c index 56b92cf9b0821..2a427efb118fa 100644 --- a/arch/arm/src/stm32l4/stm32l4_firewall.c +++ b/arch/arm/src/stm32l4/stm32l4_firewall.c @@ -39,7 +39,7 @@ * Public Functions ****************************************************************************/ -int stm32l4_firewallsetup(struct stm32l4_firewall_t *setup) +int stm32_firewallsetup(struct stm32_firewall_t *setup) { uint32_t reg; @@ -67,34 +67,34 @@ int stm32l4_firewallsetup(struct stm32l4_firewall_t *setup) * data must be in SRAM1 */ - if ((setup->codestart & STM32L4_FLASH_MASK) != STM32L4_FLASH_BASE) + if ((setup->codestart & STM32_FLASH_MASK) != STM32_FLASH_BASE) { return -EINVAL; } - if ((setup->nvdatastart & STM32L4_FLASH_MASK) != STM32L4_FLASH_BASE) + if ((setup->nvdatastart & STM32_FLASH_MASK) != STM32_FLASH_BASE) { return -EINVAL; } /* Define address and length registers */ - modifyreg32(STM32L4_FIREWALL_CSSA, FIREWALL_CSSADD_MASK, + modifyreg32(STM32_FIREWALL_CSSA, FIREWALL_CSSADD_MASK, setup->codestart); - modifyreg32(STM32L4_FIREWALL_CSL, FIREWALL_CSSLENG_MASK, + modifyreg32(STM32_FIREWALL_CSL, FIREWALL_CSSLENG_MASK, setup->codelen); - modifyreg32(STM32L4_FIREWALL_NVDSSA, FIREWALL_NVDSADD_MASK, + modifyreg32(STM32_FIREWALL_NVDSSA, FIREWALL_NVDSADD_MASK, setup->nvdatastart); - modifyreg32(STM32L4_FIREWALL_NVDSL, FIREWALL_NVDSLENG_MASK, + modifyreg32(STM32_FIREWALL_NVDSL, FIREWALL_NVDSLENG_MASK, setup->nvdatalen); - modifyreg32(STM32L4_FIREWALL_VDSSA, FIREWALL_VDSADD_MASK, + modifyreg32(STM32_FIREWALL_VDSSA, FIREWALL_VDSADD_MASK, setup->datastart); - modifyreg32(STM32L4_FIREWALL_VDSL, FIREWALL_VDSLENG_MASK, + modifyreg32(STM32_FIREWALL_VDSL, FIREWALL_VDSLENG_MASK, setup->datalen); /* Define access options */ - reg = getreg32(STM32L4_FIREWALL_CR); + reg = getreg32(STM32_FIREWALL_CR); if (setup->datashared) { reg |= FIREWALL_CR_VDS; @@ -105,13 +105,13 @@ int stm32l4_firewallsetup(struct stm32l4_firewall_t *setup) reg |= FIREWALL_CR_VDE; } - putreg32(reg, STM32L4_FIREWALL_CR); + putreg32(reg, STM32_FIREWALL_CR); /* Enable firewall */ - reg = getreg32(STM32L4_SYSCFG_CFGR1); + reg = getreg32(STM32_SYSCFG_CFGR1); reg &= ~SYSCFG_CFGR1_FWDIS; - putreg32(reg, STM32L4_SYSCFG_CFGR1); + putreg32(reg, STM32_SYSCFG_CFGR1); /* Now protected code can only be accessed by jumping to the FW gate */ diff --git a/arch/arm/src/stm32l4/stm32l4_firewall.h b/arch/arm/src/stm32l4/stm32l4_firewall.h index 6e69bddca2e51..9cf2f575ecf61 100644 --- a/arch/arm/src/stm32l4/stm32l4_firewall.h +++ b/arch/arm/src/stm32l4/stm32l4_firewall.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32L4_STM32L4_FIREWALL_H -#define __ARCH_ARM_SRC_STM32L4_STM32L4_FIREWALL_H +#ifndef __ARCH_ARM_SRC_STM32L4_STM32_FIREWALL_H +#define __ARCH_ARM_SRC_STM32L4_STM32_FIREWALL_H /**************************************************************************** * Included Files @@ -36,13 +36,13 @@ * family */ -#if defined(CONFIG_STM32L4_STM32L4X3) +#if defined(CONFIG_STM32_STM32L4X3) # include "hardware/stm32l4x3xx_firewall.h" -#elif defined(CONFIG_STM32L4_STM32L4X5) +#elif defined(CONFIG_STM32_STM32L4X5) # include "hardware/stm32l4x5xx_firewall.h" -#elif defined(CONFIG_STM32L4_STM32L4X6) +#elif defined(CONFIG_STM32_STM32L4X6) # include "hardware/stm32l4x6xx_firewall.h" -#elif defined(CONFIG_STM32L4_STM32L4XR) +#elif defined(CONFIG_STM32_STM32L4XR) # include "hardware/stm32l4xrxx_firewall.h" #else # error "Unsupported STM32L4 chip" @@ -52,7 +52,7 @@ * Public Types ****************************************************************************/ -struct stm32l4_firewall_t +struct stm32_firewall_t { uintptr_t codestart; size_t codelen; @@ -84,7 +84,7 @@ extern "C" ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_firewallsetup + * Name: stm32_firewallsetup * * Description: * Configure the STM32L4 firewall. After this, protected code will only @@ -95,7 +95,7 @@ extern "C" * ****************************************************************************/ -int stm32l4_firewallsetup(struct stm32l4_firewall_t *setup); +int stm32_firewallsetup(struct stm32_firewall_t *setup); #undef EXTERN #if defined(__cplusplus) @@ -103,4 +103,4 @@ int stm32l4_firewallsetup(struct stm32l4_firewall_t *setup); #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32L4_STM32L4_FIREWALL_H */ +#endif /* __ARCH_ARM_SRC_STM32L4_STM32_FIREWALL_H */ diff --git a/arch/arm/src/stm32l4/stm32l4_flash.c b/arch/arm/src/stm32l4/stm32l4_flash.c index dc6983cd00f53..299199b5bb52b 100644 --- a/arch/arm/src/stm32l4/stm32l4_flash.c +++ b/arch/arm/src/stm32l4/stm32l4_flash.c @@ -46,16 +46,16 @@ #include #include "stm32l4_rcc.h" -#include "stm32l4_waste.h" +#include "stm32_waste.h" #include "stm32l4_flash.h" #include "arm_internal.h" -#if !(defined(CONFIG_STM32L4_STM32L4X3) || defined(CONFIG_STM32L4_STM32L4X5) || \ - defined(CONFIG_STM32L4_STM32L4X6) || defined(CONFIG_STM32L4_STM32L4XR)) +#if !(defined(CONFIG_STM32_STM32L4X3) || defined(CONFIG_STM32_STM32L4X5) || \ + defined(CONFIG_STM32_STM32L4X6) || defined(CONFIG_STM32_STM32L4XR)) # error "Unrecognized STM32 chip" #endif -#if !defined(CONFIG_STM32L4_FLASH_OVERRIDE_DEFAULT) +#if !defined(CONFIG_STM32_FLASH_OVERRIDE_DEFAULT) # warning "Flash Configuration has been overridden - make sure it is correct" #endif @@ -70,7 +70,7 @@ #define OPTBYTES_KEY1 0x08192A3B #define OPTBYTES_KEY2 0x4C5D6E7F -#define FLASH_PAGE_SIZE STM32L4_FLASH_PAGESIZE +#define FLASH_PAGE_SIZE STM32_FLASH_PAGESIZE #define FLASH_PAGE_WORDS (FLASH_PAGE_SIZE / 4) #define FLASH_PAGE_MASK (FLASH_PAGE_SIZE - 1) #if FLASH_PAGE_SIZE == 2048 @@ -78,7 +78,7 @@ #elif FLASH_PAGE_SIZE == 4096 # define FLASH_PAGE_SHIFT (12) /* 2**12 = 4096B */ #else -# error Unsupported STM32L4_FLASH_PAGESIZE +# error Unsupported STM32_FLASH_PAGESIZE #endif #define FLASH_BYTE2PAGE(o) ((o) >> FLASH_PAGE_SHIFT) @@ -104,35 +104,35 @@ static uint32_t g_page_buffer[FLASH_PAGE_WORDS]; static void flash_unlock(void) { - while (getreg32(STM32L4_FLASH_SR) & FLASH_SR_BSY) + while (getreg32(STM32_FLASH_SR) & FLASH_SR_BSY) { - stm32l4_waste(); + stm32_waste(); } - if (getreg32(STM32L4_FLASH_CR) & FLASH_CR_LOCK) + if (getreg32(STM32_FLASH_CR) & FLASH_CR_LOCK) { /* Unlock sequence */ - putreg32(FLASH_KEY1, STM32L4_FLASH_KEYR); - putreg32(FLASH_KEY2, STM32L4_FLASH_KEYR); + putreg32(FLASH_KEY1, STM32_FLASH_KEYR); + putreg32(FLASH_KEY2, STM32_FLASH_KEYR); } } static void flash_lock(void) { - modifyreg32(STM32L4_FLASH_CR, 0, FLASH_CR_LOCK); + modifyreg32(STM32_FLASH_CR, 0, FLASH_CR_LOCK); } static void flash_optbytes_unlock(void) { flash_unlock(); - if (getreg32(STM32L4_FLASH_CR) & FLASH_CR_OPTLOCK) + if (getreg32(STM32_FLASH_CR) & FLASH_CR_OPTLOCK) { /* Unlock Option Bytes sequence */ - putreg32(OPTBYTES_KEY1, STM32L4_FLASH_OPTKEYR); - putreg32(OPTBYTES_KEY2, STM32L4_FLASH_OPTKEYR); + putreg32(OPTBYTES_KEY1, STM32_FLASH_OPTKEYR); + putreg32(OPTBYTES_KEY2, STM32_FLASH_OPTKEYR); } } @@ -149,60 +149,60 @@ static inline void flash_erase(size_t page) { finfo("erase page %u\n", page); - modifyreg32(STM32L4_FLASH_CR, 0, FLASH_CR_PAGE_ERASE); - modifyreg32(STM32L4_FLASH_CR, FLASH_CR_PNB_MASK, + modifyreg32(STM32_FLASH_CR, 0, FLASH_CR_PAGE_ERASE); + modifyreg32(STM32_FLASH_CR, FLASH_CR_PNB_MASK, FLASH_CR_PNB(page & 0xff)); -#if defined(CONFIG_STM32L4_STM32L4X5) || \ - defined(CONFIG_STM32L4_STM32L4X6) || \ - defined(CONFIG_STM32L4_STM32L4XR) +#if defined(CONFIG_STM32_STM32L4X5) || \ + defined(CONFIG_STM32_STM32L4X6) || \ + defined(CONFIG_STM32_STM32L4XR) if (page <= 0xff) { /* Select bank 1 */ - modifyreg32(STM32L4_FLASH_CR, FLASH_CR_BKER, 0); + modifyreg32(STM32_FLASH_CR, FLASH_CR_BKER, 0); } else { /* Select bank 2 */ - modifyreg32(STM32L4_FLASH_CR, 0, FLASH_CR_BKER); + modifyreg32(STM32_FLASH_CR, 0, FLASH_CR_BKER); } #endif - modifyreg32(STM32L4_FLASH_CR, 0, FLASH_CR_START); + modifyreg32(STM32_FLASH_CR, 0, FLASH_CR_START); - while (getreg32(STM32L4_FLASH_SR) & FLASH_SR_BSY) + while (getreg32(STM32_FLASH_SR) & FLASH_SR_BSY) { - stm32l4_waste(); + stm32_waste(); } - modifyreg32(STM32L4_FLASH_CR, FLASH_CR_PAGE_ERASE, 0); + modifyreg32(STM32_FLASH_CR, FLASH_CR_PAGE_ERASE, 0); } -#if defined(CONFIG_STM32L4_FLASH_WORKAROUND_DATA_CACHE_CORRUPTION_ON_RWW) +#if defined(CONFIG_STM32_FLASH_WORKAROUND_DATA_CACHE_CORRUPTION_ON_RWW) static void data_cache_disable(void) { - modifyreg32(STM32L4_FLASH_ACR, FLASH_ACR_DCEN, 0); + modifyreg32(STM32_FLASH_ACR, FLASH_ACR_DCEN, 0); } static void data_cache_enable(void) { /* Reset data cache */ - modifyreg32(STM32L4_FLASH_ACR, 0, FLASH_ACR_DCRST); + modifyreg32(STM32_FLASH_ACR, 0, FLASH_ACR_DCRST); /* Enable data cache */ - modifyreg32(STM32L4_FLASH_ACR, 0, FLASH_ACR_DCEN); + modifyreg32(STM32_FLASH_ACR, 0, FLASH_ACR_DCEN); } -#endif /* defined(CONFIG_STM32L4_FLASH_WORKAROUND_DATA_CACHE_CORRUPTION_ON_RWW) */ +#endif /* defined(CONFIG_STM32_FLASH_WORKAROUND_DATA_CACHE_CORRUPTION_ON_RWW) */ /**************************************************************************** * Public Functions ****************************************************************************/ -int stm32l4_flash_unlock(void) +int stm32_flash_unlock(void) { int ret; @@ -218,7 +218,7 @@ int stm32l4_flash_unlock(void) return ret; } -int stm32l4_flash_lock(void) +int stm32_flash_lock(void) { int ret; @@ -235,7 +235,7 @@ int stm32l4_flash_lock(void) } /**************************************************************************** - * Name: stm32l4_flash_user_optbytes + * Name: stm32_flash_user_optbytes * * Description: * Modify the contents of the user option bytes (USR OPT) on the flash. @@ -251,7 +251,7 @@ int stm32l4_flash_lock(void) * ****************************************************************************/ -uint32_t stm32l4_flash_user_optbytes(uint32_t clrbits, uint32_t setbits) +uint32_t stm32_flash_user_optbytes(uint32_t clrbits, uint32_t setbits) { uint32_t regval; int ret; @@ -274,22 +274,22 @@ uint32_t stm32l4_flash_user_optbytes(uint32_t clrbits, uint32_t setbits) /* Modify Option Bytes in register. */ - regval = getreg32(STM32L4_FLASH_OPTR); + regval = getreg32(STM32_FLASH_OPTR); finfo("Flash option bytes before: 0x%" PRIx32 "\n", regval); regval = (regval & ~clrbits) | setbits; - putreg32(regval, STM32L4_FLASH_OPTR); + putreg32(regval, STM32_FLASH_OPTR); finfo("Flash option bytes after: 0x%" PRIx32 "\n", regval); /* Start Option Bytes programming and wait for completion. */ - modifyreg32(STM32L4_FLASH_CR, 0, FLASH_CR_OPTSTRT); + modifyreg32(STM32_FLASH_CR, 0, FLASH_CR_OPTSTRT); - while (getreg32(STM32L4_FLASH_SR) & FLASH_SR_BSY) + while (getreg32(STM32_FLASH_SR) & FLASH_SR_BSY) { - stm32l4_waste(); + stm32_waste(); } flash_optbytes_lock(); @@ -300,42 +300,42 @@ uint32_t stm32l4_flash_user_optbytes(uint32_t clrbits, uint32_t setbits) size_t up_progmem_pagesize(size_t page) { - return STM32L4_FLASH_PAGESIZE; + return STM32_FLASH_PAGESIZE; } size_t up_progmem_erasesize(size_t block) { - return STM32L4_FLASH_PAGESIZE; + return STM32_FLASH_PAGESIZE; } ssize_t up_progmem_getpage(size_t addr) { - if (addr >= STM32L4_FLASH_BASE) + if (addr >= STM32_FLASH_BASE) { - addr -= STM32L4_FLASH_BASE; + addr -= STM32_FLASH_BASE; } - if (addr >= STM32L4_FLASH_SIZE) + if (addr >= STM32_FLASH_SIZE) { return -EFAULT; } - return addr / STM32L4_FLASH_PAGESIZE; + return addr / STM32_FLASH_PAGESIZE; } size_t up_progmem_getaddress(size_t page) { - if (page >= STM32L4_FLASH_NPAGES) + if (page >= STM32_FLASH_NPAGES) { return SIZE_MAX; } - return page * STM32L4_FLASH_PAGESIZE + STM32L4_FLASH_BASE; + return page * STM32_FLASH_PAGESIZE + STM32_FLASH_BASE; } size_t up_progmem_neraseblocks(void) { - return STM32L4_FLASH_NPAGES; + return STM32_FLASH_NPAGES; } bool up_progmem_isuniform(void) @@ -347,7 +347,7 @@ ssize_t up_progmem_eraseblock(size_t block) { int ret; - if (block >= STM32L4_FLASH_NPAGES) + if (block >= STM32_FLASH_NPAGES) { return -EFAULT; } @@ -385,7 +385,7 @@ ssize_t up_progmem_ispageerased(size_t page) size_t count; size_t bwritten = 0; - if (page >= STM32L4_FLASH_NPAGES) + if (page >= STM32_FLASH_NPAGES) { return -EFAULT; } @@ -419,12 +419,12 @@ ssize_t up_progmem_write(size_t addr, const void *buf, size_t buflen) /* Check for valid address range. */ offset = addr; - if (addr >= STM32L4_FLASH_BASE) + if (addr >= STM32_FLASH_BASE) { - offset -= STM32L4_FLASH_BASE; + offset -= STM32_FLASH_BASE; } - if (offset + buflen > STM32L4_FLASH_SIZE) + if (offset + buflen > STM32_FLASH_SIZE) { return -EFAULT; } @@ -494,11 +494,11 @@ ssize_t up_progmem_write(size_t addr, const void *buf, size_t buflen) /* Write the page. Must be with double-words. */ -#if defined(CONFIG_STM32L4_FLASH_WORKAROUND_DATA_CACHE_CORRUPTION_ON_RWW) +#if defined(CONFIG_STM32_FLASH_WORKAROUND_DATA_CACHE_CORRUPTION_ON_RWW) data_cache_disable(); #endif - modifyreg32(STM32L4_FLASH_CR, 0, FLASH_CR_PG); + modifyreg32(STM32_FLASH_CR, 0, FLASH_CR_PG); set_pg_bit = true; for (i = 0; i < FLASH_PAGE_WORDS; i += 2) @@ -506,14 +506,14 @@ ssize_t up_progmem_write(size_t addr, const void *buf, size_t buflen) *dest++ = *src++; *dest++ = *src++; - while (getreg32(STM32L4_FLASH_SR) & FLASH_SR_BSY) + while (getreg32(STM32_FLASH_SR) & FLASH_SR_BSY) { - stm32l4_waste(); + stm32_waste(); } /* Verify */ - if (getreg32(STM32L4_FLASH_SR) & FLASH_SR_WRITE_PROTECTION_ERROR) + if (getreg32(STM32_FLASH_SR) & FLASH_SR_WRITE_PROTECTION_ERROR) { ret = -EROFS; goto out; @@ -527,10 +527,10 @@ ssize_t up_progmem_write(size_t addr, const void *buf, size_t buflen) } } - modifyreg32(STM32L4_FLASH_CR, FLASH_CR_PG, 0); + modifyreg32(STM32_FLASH_CR, FLASH_CR_PG, 0); set_pg_bit = false; -#if defined(CONFIG_STM32L4_FLASH_WORKAROUND_DATA_CACHE_CORRUPTION_ON_RWW) +#if defined(CONFIG_STM32_FLASH_WORKAROUND_DATA_CACHE_CORRUPTION_ON_RWW) data_cache_enable(); #endif @@ -547,8 +547,8 @@ ssize_t up_progmem_write(size_t addr, const void *buf, size_t buflen) out: if (set_pg_bit) { - modifyreg32(STM32L4_FLASH_CR, FLASH_CR_PG, 0); -#if defined(CONFIG_STM32L4_FLASH_WORKAROUND_DATA_CACHE_CORRUPTION_ON_RWW) + modifyreg32(STM32_FLASH_CR, FLASH_CR_PG, 0); +#if defined(CONFIG_STM32_FLASH_WORKAROUND_DATA_CACHE_CORRUPTION_ON_RWW) data_cache_enable(); #endif } @@ -560,9 +560,9 @@ ssize_t up_progmem_write(size_t addr, const void *buf, size_t buflen) if (ret != OK) { ferr("flash write error: %d, status: 0x%" PRIx32 "\n", - ret, getreg32(STM32L4_FLASH_SR)); + ret, getreg32(STM32_FLASH_SR)); - modifyreg32(STM32L4_FLASH_SR, 0, FLASH_SR_ALLERRS); + modifyreg32(STM32_FLASH_SR, 0, FLASH_SR_ALLERRS); } flash_lock(); diff --git a/arch/arm/src/stm32l4/stm32l4_flash.h b/arch/arm/src/stm32l4/stm32l4_flash.h index 89cf22190fa85..3cc3a8a0bfdfe 100644 --- a/arch/arm/src/stm32l4/stm32l4_flash.h +++ b/arch/arm/src/stm32l4/stm32l4_flash.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32L4_STM32L4_FLASH_H -#define __ARCH_ARM_SRC_STM32L4_STM32L4_FLASH_H +#ifndef __ARCH_ARM_SRC_STM32L4_STM32_FLASH_H +#define __ARCH_ARM_SRC_STM32L4_STM32_FLASH_H /**************************************************************************** * Included Files @@ -34,11 +34,11 @@ * Public Functions Prototypes ****************************************************************************/ -int stm32l4_flash_lock(void); -int stm32l4_flash_unlock(void); +int stm32_flash_lock(void); +int stm32_flash_unlock(void); /**************************************************************************** - * Name: stm32l4_flash_user_optbytes + * Name: stm32_flash_user_optbytes * * Description: * Modify the contents of the user option bytes (USR OPT) on the flash. @@ -54,6 +54,6 @@ int stm32l4_flash_unlock(void); * ****************************************************************************/ -uint32_t stm32l4_flash_user_optbytes(uint32_t clrbits, uint32_t setbits); +uint32_t stm32_flash_user_optbytes(uint32_t clrbits, uint32_t setbits); -#endif /* __ARCH_ARM_SRC_STM32L4_STM32L4_FLASH_H */ +#endif /* __ARCH_ARM_SRC_STM32L4_STM32_FLASH_H */ diff --git a/arch/arm/src/stm32l4/stm32l4_freerun.c b/arch/arm/src/stm32l4/stm32l4_freerun.c index 433a55288f29c..c768b6237e352 100644 --- a/arch/arm/src/stm32l4/stm32l4_freerun.c +++ b/arch/arm/src/stm32l4/stm32l4_freerun.c @@ -37,14 +37,14 @@ #include "stm32l4_freerun.h" -#ifdef CONFIG_STM32L4_FREERUN +#ifdef CONFIG_STM32_FREERUN /**************************************************************************** * Private Functions ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_freerun_handler + * Name: stm32_freerun_handler * * Description: * Timer interrupt callback. When the freerun timer counter overflows, @@ -61,15 +61,15 @@ * ****************************************************************************/ -static int stm32l4_freerun_handler(int irq, void *context, void *arg) +static int stm32_freerun_handler(int irq, void *context, void *arg) { - struct stm32l4_freerun_s *freerun = - (struct stm32l4_freerun_s *)arg; + struct stm32_freerun_s *freerun = + (struct stm32_freerun_s *)arg; DEBUGASSERT(freerun != NULL && freerun->overflow < UINT32_MAX); freerun->overflow++; - STM32L4_TIM_ACKINT(freerun->tch, 0); + STM32_TIM_ACKINT(freerun->tch, 0); return OK; } @@ -78,7 +78,7 @@ static int stm32l4_freerun_handler(int irq, void *context, void *arg) ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_freerun_initialize + * Name: stm32_freerun_initialize * * Description: * Initialize the freerun timer wrapper @@ -96,7 +96,7 @@ static int stm32l4_freerun_handler(int irq, void *context, void *arg) * ****************************************************************************/ -int stm32l4_freerun_initialize(struct stm32l4_freerun_s *freerun, +int stm32_freerun_initialize(struct stm32_freerun_s *freerun, int chan, uint16_t resolution) { @@ -110,14 +110,14 @@ int stm32l4_freerun_initialize(struct stm32l4_freerun_s *freerun, frequency = USEC_PER_SEC / (uint32_t)resolution; freerun->frequency = frequency; - freerun->tch = stm32l4_tim_init(chan); + freerun->tch = stm32_tim_init(chan); if (!freerun->tch) { tmrerr("ERROR: Failed to allocate TIM%d\n", chan); return -EBUSY; } - STM32L4_TIM_SETCLOCK(freerun->tch, frequency); + STM32_TIM_SETCLOCK(freerun->tch, frequency); /* Initialize the remaining fields in the state structure and return * success. @@ -128,23 +128,23 @@ int stm32l4_freerun_initialize(struct stm32l4_freerun_s *freerun, /* Set up to receive the callback when the counter overflow occurs */ - STM32L4_TIM_SETISR(freerun->tch, stm32l4_freerun_handler, freerun, 0); + STM32_TIM_SETISR(freerun->tch, stm32_freerun_handler, freerun, 0); /* Set timer period */ - STM32L4_TIM_SETPERIOD(freerun->tch, UINT32_MAX); + STM32_TIM_SETPERIOD(freerun->tch, UINT32_MAX); /* Start the counter */ - STM32L4_TIM_SETMODE(freerun->tch, STM32L4_TIM_MODE_UP); - STM32L4_TIM_ACKINT(freerun->tch, 0); - STM32L4_TIM_ENABLEINT(freerun->tch, 0); + STM32_TIM_SETMODE(freerun->tch, STM32_TIM_MODE_UP); + STM32_TIM_ACKINT(freerun->tch, 0); + STM32_TIM_ENABLEINT(freerun->tch, 0); return OK; } /**************************************************************************** - * Name: stm32l4_freerun_counter + * Name: stm32_freerun_counter * * Description: * Read the counter register of the free-running timer. @@ -152,7 +152,7 @@ int stm32l4_freerun_initialize(struct stm32l4_freerun_s *freerun, * Input Parameters: * freerun Caller allocated instance of the freerun state structure. This * structure must have been previously initialized via a call to - * stm32l4_freerun_initialize(); + * stm32_freerun_initialize(); * ts The location in which to return the time from the free-running * timer. * @@ -162,7 +162,7 @@ int stm32l4_freerun_initialize(struct stm32l4_freerun_s *freerun, * ****************************************************************************/ -int stm32l4_freerun_counter(struct stm32l4_freerun_s *freerun, +int stm32_freerun_counter(struct stm32_freerun_s *freerun, struct timespec *ts) { uint64_t usec; @@ -176,7 +176,7 @@ int stm32l4_freerun_counter(struct stm32l4_freerun_s *freerun, DEBUGASSERT(freerun && freerun->tch && ts); /* Temporarily disable the overflow counter. NOTE that we have to be - * careful here because stm32l4_tc_getpending() will reset the pending + * careful here because stm32_tc_getpending() will reset the pending * interrupt status. If we do not handle the overflow here then, it will * be lost. */ @@ -184,9 +184,9 @@ int stm32l4_freerun_counter(struct stm32l4_freerun_s *freerun, flags = enter_critical_section(); overflow = freerun->overflow; - counter = STM32L4_TIM_GETCOUNTER(freerun->tch); - pending = STM32L4_TIM_CHECKINT(freerun->tch, 0); - verify = STM32L4_TIM_GETCOUNTER(freerun->tch); + counter = STM32_TIM_GETCOUNTER(freerun->tch); + pending = STM32_TIM_CHECKINT(freerun->tch, 0); + verify = STM32_TIM_GETCOUNTER(freerun->tch); /* If an interrupt was pending before we re-enabled interrupts, * then the overflow needs to be incremented. @@ -194,7 +194,7 @@ int stm32l4_freerun_counter(struct stm32l4_freerun_s *freerun, if (pending) { - STM32L4_TIM_ACKINT(freerun->tch, 0); + STM32_TIM_ACKINT(freerun->tch, 0); /* Increment the overflow count and use the value of the * guaranteed to be AFTER the overflow occurred. @@ -238,7 +238,7 @@ int stm32l4_freerun_counter(struct stm32l4_freerun_s *freerun, } /**************************************************************************** - * Name: stm32l4_freerun_uninitialize + * Name: stm32_freerun_uninitialize * * Description: * Stop the free-running timer and release all resources that it uses. @@ -246,7 +246,7 @@ int stm32l4_freerun_counter(struct stm32l4_freerun_s *freerun, * Input Parameters: * freerun Caller allocated instance of the freerun state structure. This * structure must have been previously initialized via a call to - * stm32l4_freerun_initialize(); + * stm32_freerun_initialize(); * * Returned Value: * Zero (OK) is returned on success; a negated errno value is returned @@ -254,22 +254,22 @@ int stm32l4_freerun_counter(struct stm32l4_freerun_s *freerun, * ****************************************************************************/ -int stm32l4_freerun_uninitialize(struct stm32l4_freerun_s *freerun) +int stm32_freerun_uninitialize(struct stm32_freerun_s *freerun) { DEBUGASSERT(freerun && freerun->tch); /* Now we can disable the timer interrupt and disable the timer. */ - STM32L4_TIM_DISABLEINT(freerun->tch, 0); - STM32L4_TIM_SETMODE(freerun->tch, STM32L4_TIM_MODE_DISABLED); - STM32L4_TIM_SETISR(freerun->tch, NULL, NULL, 0); + STM32_TIM_DISABLEINT(freerun->tch, 0); + STM32_TIM_SETMODE(freerun->tch, STM32_TIM_MODE_DISABLED); + STM32_TIM_SETISR(freerun->tch, NULL, NULL, 0); /* Free the timer */ - stm32l4_tim_deinit(freerun->tch); + stm32_tim_deinit(freerun->tch); freerun->tch = NULL; return OK; } -#endif /* CONFIG_STM32L4_FREERUN */ +#endif /* CONFIG_STM32_FREERUN */ diff --git a/arch/arm/src/stm32l4/stm32l4_freerun.h b/arch/arm/src/stm32l4/stm32l4_freerun.h index 21ce87d262809..c1aeacf7afdcb 100644 --- a/arch/arm/src/stm32l4/stm32l4_freerun.h +++ b/arch/arm/src/stm32l4/stm32l4_freerun.h @@ -35,23 +35,23 @@ #include "stm32l4_tim.h" -#ifdef CONFIG_STM32L4_FREERUN +#ifdef CONFIG_STM32_FREERUN /**************************************************************************** * Public Types ****************************************************************************/ /* The freerun client must allocate an instance of this structure and called - * stm32l4_freerun_initialize() before using the freerun facilities. The + * stm32_freerun_initialize() before using the freerun facilities. The * client should not access the contents of this structure directly since the * contents are subject to change. */ -struct stm32l4_freerun_s +struct stm32_freerun_s { uint8_t chan; /* The timer/counter in use */ uint32_t overflow; /* Timer counter overflow */ - struct stm32l4_tim_dev_s *tch; /* Handle returned by stm32l4_tim_init() */ + struct stm32_tim_dev_s *tch; /* Handle returned by stm32_tim_init() */ uint32_t frequency; }; @@ -73,7 +73,7 @@ extern "C" ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_freerun_initialize + * Name: stm32_freerun_initialize * * Description: * Initialize the freerun timer wrapper @@ -91,11 +91,11 @@ extern "C" * ****************************************************************************/ -int stm32l4_freerun_initialize(struct stm32l4_freerun_s *freerun, int chan, +int stm32_freerun_initialize(struct stm32_freerun_s *freerun, int chan, uint16_t resolution); /**************************************************************************** - * Name: stm32l4_freerun_counter + * Name: stm32_freerun_counter * * Description: * Read the counter register of the free-running timer. @@ -103,7 +103,7 @@ int stm32l4_freerun_initialize(struct stm32l4_freerun_s *freerun, int chan, * Input Parameters: * freerun Caller allocated instance of the freerun state structure. This * structure must have been previously initialized via a call to - * stm32l4_freerun_initialize(); + * stm32_freerun_initialize(); * ts The location in which to return the time remaining on the * oneshot timer. * @@ -113,11 +113,11 @@ int stm32l4_freerun_initialize(struct stm32l4_freerun_s *freerun, int chan, * ****************************************************************************/ -int stm32l4_freerun_counter(struct stm32l4_freerun_s *freerun, +int stm32_freerun_counter(struct stm32_freerun_s *freerun, struct timespec *ts); /**************************************************************************** - * Name: stm32l4_freerun_uninitialize + * Name: stm32_freerun_uninitialize * * Description: * Stop the free-running timer and release all resources that it uses. @@ -125,7 +125,7 @@ int stm32l4_freerun_counter(struct stm32l4_freerun_s *freerun, * Input Parameters: * freerun Caller allocated instance of the freerun state structure. This * structure must have been previously initialized via a call to - * stm32l4_freerun_initialize(); + * stm32_freerun_initialize(); * * Returned Value: * Zero (OK) is returned on success; a negated errno value is returned @@ -133,12 +133,12 @@ int stm32l4_freerun_counter(struct stm32l4_freerun_s *freerun, * ****************************************************************************/ -int stm32l4_freerun_uninitialize(struct stm32l4_freerun_s *freerun); +int stm32_freerun_uninitialize(struct stm32_freerun_s *freerun); #undef EXTERN #ifdef __cplusplus } #endif -#endif /* CONFIG_STM32L4_FREERUN */ +#endif /* CONFIG_STM32_FREERUN */ #endif /* __ARCH_ARM_SRC_STM32L4_STM32L4_FREERUN_H */ diff --git a/arch/arm/src/stm32l4/stm32l4_gpio.c b/arch/arm/src/stm32l4/stm32l4_gpio.c index 1cf19f3dac6cb..1a1e18a76f895 100644 --- a/arch/arm/src/stm32l4/stm32l4_gpio.c +++ b/arch/arm/src/stm32l4/stm32l4_gpio.c @@ -54,34 +54,34 @@ static spinlock_t g_configgpio_lock = SP_UNLOCKED; /* Base addresses for each GPIO block */ -const uint32_t g_gpiobase[STM32L4_NPORTS] = +const uint32_t g_gpiobase[STM32_NPORTS] = { -#if STM32L4_NPORTS > 0 - STM32L4_GPIOA_BASE, +#if STM32_NPORTS > 0 + STM32_GPIOA_BASE, #endif -#if STM32L4_NPORTS > 1 - STM32L4_GPIOB_BASE, +#if STM32_NPORTS > 1 + STM32_GPIOB_BASE, #endif -#if STM32L4_NPORTS > 2 - STM32L4_GPIOC_BASE, +#if STM32_NPORTS > 2 + STM32_GPIOC_BASE, #endif -#if STM32L4_NPORTS > 3 - STM32L4_GPIOD_BASE, +#if STM32_NPORTS > 3 + STM32_GPIOD_BASE, #endif -#if STM32L4_NPORTS > 4 - STM32L4_GPIOE_BASE, +#if STM32_NPORTS > 4 + STM32_GPIOE_BASE, #endif -#if STM32L4_NPORTS > 5 - STM32L4_GPIOF_BASE, +#if STM32_NPORTS > 5 + STM32_GPIOF_BASE, #endif -#if STM32L4_NPORTS > 6 - STM32L4_GPIOG_BASE, +#if STM32_NPORTS > 6 + STM32_GPIOG_BASE, #endif -#if STM32L4_NPORTS > 7 - STM32L4_GPIOH_BASE, +#if STM32_NPORTS > 7 + STM32_GPIOH_BASE, #endif -#if STM32L4_NPORTS > 8 - STM32L4_GPIOI_BASE, +#if STM32_NPORTS > 8 + STM32_GPIOI_BASE, #endif }; @@ -94,13 +94,13 @@ const uint32_t g_gpiobase[STM32L4_NPORTS] = ****************************************************************************/ /**************************************************************************** - * Function: stm32l4_gpioinit + * Function: stm32_gpioinit * * Description: * Based on configuration within the .config file, it does: * - Remaps positions of alternative functions. * - * Typically called from stm32l4_start(). + * Typically called from stm32_start(). * * Assumptions: * This function is called early in the initialization sequence so that @@ -108,17 +108,17 @@ const uint32_t g_gpiobase[STM32L4_NPORTS] = * ****************************************************************************/ -void stm32l4_gpioinit(void) +void stm32_gpioinit(void) { } /**************************************************************************** - * Name: stm32l4_configgpio + * Name: stm32_configgpio * * Description: * Configure a GPIO pin based on bit-encoded description of the pin. * Once it is configured as Alternative (GPIO_ALT|GPIO_CNF_AFPP|...) - * function, it must be unconfigured with stm32l4_unconfiggpio() with + * function, it must be unconfigured with stm32_unconfiggpio() with * the same cfgset first before it can be set to non-alternative function. * * Returned Value: @@ -129,7 +129,7 @@ void stm32l4_gpioinit(void) * To-Do: Auto Power Enable ****************************************************************************/ -int stm32l4_configgpio(uint32_t cfgset) +int stm32_configgpio(uint32_t cfgset) { uintptr_t base; uint32_t regval; @@ -144,7 +144,7 @@ int stm32l4_configgpio(uint32_t cfgset) /* Verify that this hardware supports the select GPIO port */ port = (cfgset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; - if (port >= STM32L4_NPORTS) + if (port >= STM32_NPORTS) { return -EINVAL; } @@ -177,7 +177,7 @@ int stm32l4_configgpio(uint32_t cfgset) /* Set the initial output value */ - stm32l4_gpiowrite(cfgset, (cfgset & GPIO_OUTPUT_SET) != 0); + stm32_gpiowrite(cfgset, (cfgset & GPIO_OUTPUT_SET) != 0); pinmode = GPIO_MODER_OUTPUT; break; @@ -202,10 +202,10 @@ int stm32l4_configgpio(uint32_t cfgset) /* Now apply the configuration to the mode register */ - regval = getreg32(base + STM32L4_GPIO_MODER_OFFSET); + regval = getreg32(base + STM32_GPIO_MODER_OFFSET); regval &= ~GPIO_MODER_MASK(pin); regval |= ((uint32_t)pinmode << GPIO_MODER_SHIFT(pin)); - putreg32(regval, base + STM32L4_GPIO_MODER_OFFSET); + putreg32(regval, base + STM32_GPIO_MODER_OFFSET); /* Set up the pull-up/pull-down configuration (all but analog pins) */ @@ -228,10 +228,10 @@ int stm32l4_configgpio(uint32_t cfgset) } } - regval = getreg32(base + STM32L4_GPIO_PUPDR_OFFSET); + regval = getreg32(base + STM32_GPIO_PUPDR_OFFSET); regval &= ~GPIO_PUPDR_MASK(pin); regval |= (setting << GPIO_PUPDR_SHIFT(pin)); - putreg32(regval, base + STM32L4_GPIO_PUPDR_OFFSET); + putreg32(regval, base + STM32_GPIO_PUPDR_OFFSET); /* Set the alternate function (Only alternate function pins) */ @@ -246,12 +246,12 @@ int stm32l4_configgpio(uint32_t cfgset) if (pin < 8) { - regoffset = STM32L4_GPIO_AFRL_OFFSET; + regoffset = STM32_GPIO_AFRL_OFFSET; pos = pin; } else { - regoffset = STM32L4_GPIO_AFRH_OFFSET; + regoffset = STM32_GPIO_AFRH_OFFSET; pos = pin - 8; } @@ -289,14 +289,14 @@ int stm32l4_configgpio(uint32_t cfgset) setting = 0; } - regval = getreg32(base + STM32L4_GPIO_OSPEED_OFFSET); + regval = getreg32(base + STM32_GPIO_OSPEED_OFFSET); regval &= ~GPIO_OSPEED_MASK(pin); regval |= (setting << GPIO_OSPEED_SHIFT(pin)); - putreg32(regval, base + STM32L4_GPIO_OSPEED_OFFSET); + putreg32(regval, base + STM32_GPIO_OSPEED_OFFSET); /* Set push-pull/open-drain (Only outputs and alternate function pins) */ - regval = getreg32(base + STM32L4_GPIO_OTYPER_OFFSET); + regval = getreg32(base + STM32_GPIO_OTYPER_OFFSET); setting = GPIO_OTYPER_OD(pin); if ((pinmode == GPIO_MODER_OUTPUT || pinmode == GPIO_MODER_ALT) && @@ -309,7 +309,7 @@ int stm32l4_configgpio(uint32_t cfgset) regval &= ~setting; } - putreg32(regval, base + STM32L4_GPIO_OTYPER_OFFSET); + putreg32(regval, base + STM32_GPIO_OTYPER_OFFSET); /* Otherwise, it is an input pin. Should it configured as an * EXTI interrupt? @@ -331,7 +331,7 @@ int stm32l4_configgpio(uint32_t cfgset) /* Set the bits in the SYSCFG EXTICR register */ - regaddr = STM32L4_SYSCFG_EXTICR(pin); + regaddr = STM32_SYSCFG_EXTICR(pin); regval = getreg32(regaddr); shift = SYSCFG_EXTICR_EXTI_SHIFT(pin); regval &= ~(SYSCFG_EXTICR_PORT_MASK << shift); @@ -344,18 +344,18 @@ int stm32l4_configgpio(uint32_t cfgset) * (RM0351 Rev 7, p521) */ -#if defined(CONFIG_STM32L4_STM32L471XX) || \ - defined(CONFIG_STM32L4_STM32L475XX) || \ - defined(CONFIG_STM32L4_STM32L476XX) || \ - defined(CONFIG_STM32L4_STM32L486XX) +#if defined(CONFIG_STM32_STM32L471XX) || \ + defined(CONFIG_STM32_STM32L475XX) || \ + defined(CONFIG_STM32_STM32L476XX) || \ + defined(CONFIG_STM32_STM32L486XX) if (pinmode == GPIO_MODER_ANALOG) { - modifyreg32(base + STM32L4_GPIO_ASCR_OFFSET, 0, GPIO_ASCR(pin)); + modifyreg32(base + STM32_GPIO_ASCR_OFFSET, 0, GPIO_ASCR(pin)); } else { - modifyreg32(base + STM32L4_GPIO_ASCR_OFFSET, GPIO_ASCR(pin), 0); + modifyreg32(base + STM32_GPIO_ASCR_OFFSET, GPIO_ASCR(pin), 0); } #endif @@ -364,7 +364,7 @@ int stm32l4_configgpio(uint32_t cfgset) } /**************************************************************************** - * Name: stm32l4_unconfiggpio + * Name: stm32_unconfiggpio * * Description: * Unconfigure a GPIO pin based on bit-encoded description of the pin, set @@ -384,7 +384,7 @@ int stm32l4_configgpio(uint32_t cfgset) * To-Do: Auto Power Disable ****************************************************************************/ -int stm32l4_unconfiggpio(uint32_t cfgset) +int stm32_unconfiggpio(uint32_t cfgset) { /* Reuse port and pin number and set it to default HiZ INPUT */ @@ -393,18 +393,18 @@ int stm32l4_unconfiggpio(uint32_t cfgset) /* To-Do: Mark its unuse for automatic power saving options */ - return stm32l4_configgpio(cfgset); + return stm32_configgpio(cfgset); } /**************************************************************************** - * Name: stm32l4_gpiowrite + * Name: stm32_gpiowrite * * Description: * Write one or zero to the selected GPIO pin * ****************************************************************************/ -void stm32l4_gpiowrite(uint32_t pinset, bool value) +void stm32_gpiowrite(uint32_t pinset, bool value) { uint32_t base; uint32_t bit; @@ -412,7 +412,7 @@ void stm32l4_gpiowrite(uint32_t pinset, bool value) unsigned int pin; port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; - if (port < STM32L4_NPORTS) + if (port < STM32_NPORTS) { /* Get the port base address */ @@ -433,26 +433,26 @@ void stm32l4_gpiowrite(uint32_t pinset, bool value) bit = GPIO_BSRR_RESET(pin); } - putreg32(bit, base + STM32L4_GPIO_BSRR_OFFSET); + putreg32(bit, base + STM32_GPIO_BSRR_OFFSET); } } /**************************************************************************** - * Name: stm32l4_gpioread + * Name: stm32_gpioread * * Description: * Read one or zero from the selected GPIO pin * ****************************************************************************/ -bool stm32l4_gpioread(uint32_t pinset) +bool stm32_gpioread(uint32_t pinset) { uint32_t base; unsigned int port; unsigned int pin; port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; - if (port < STM32L4_NPORTS) + if (port < STM32_NPORTS) { /* Get the port base address */ @@ -461,7 +461,7 @@ bool stm32l4_gpioread(uint32_t pinset) /* Get the pin number and return the input state of that pin */ pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT; - return ((getreg32(base + STM32L4_GPIO_IDR_OFFSET) & (1 << pin)) != 0); + return ((getreg32(base + STM32_GPIO_IDR_OFFSET) & (1 << pin)) != 0); } return 0; diff --git a/arch/arm/src/stm32l4/stm32l4_gpio.h b/arch/arm/src/stm32l4/stm32l4_gpio.h index 2df58191ee1c9..bfdcbe57a5614 100644 --- a/arch/arm/src/stm32l4/stm32l4_gpio.h +++ b/arch/arm/src/stm32l4/stm32l4_gpio.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32L4_STM32L4_GPIO_H -#define __ARCH_ARM_SRC_STM32L4_STM32L4_GPIO_H +#ifndef __ARCH_ARM_SRC_STM32L4_STM32_GPIO_H +#define __ARCH_ARM_SRC_STM32L4_STM32_GPIO_H /**************************************************************************** * Included Files @@ -39,8 +39,8 @@ #include "chip.h" -#if defined(CONFIG_STM32L4_STM32L4X3) || defined(CONFIG_STM32L4_STM32L4X5) || \ - defined(CONFIG_STM32L4_STM32L4X6) || defined(CONFIG_STM32L4_STM32L4XR) +#if defined(CONFIG_STM32_STM32L4X3) || defined(CONFIG_STM32_STM32L4X5) || \ + defined(CONFIG_STM32_STM32L4X6) || defined(CONFIG_STM32_STM32L4XR) # include "hardware/stm32l4_gpio.h" #else # error "Unsupported STM32L4 chip" @@ -50,7 +50,7 @@ * Pre-Processor Declarations ****************************************************************************/ -/* Bit-encoded input to stm32l4_configgpio() */ +/* Bit-encoded input to stm32_configgpio() */ /* Each port bit of the general-purpose I/O (GPIO) ports can be individually * configured by software in several modes: @@ -244,19 +244,19 @@ extern "C" /* Base addresses for each GPIO block */ -EXTERN const uint32_t g_gpiobase[STM32L4_NPORTS]; +EXTERN const uint32_t g_gpiobase[STM32_NPORTS]; /**************************************************************************** * Public Function Prototypes ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_configgpio + * Name: stm32_configgpio * * Description: * Configure a GPIO pin based on bit-encoded description of the pin. * Once it is configured as Alternative (GPIO_ALT|GPIO_CNF_AFPP|...) - * function, it must be unconfigured with stm32l4_unconfiggpio() with + * function, it must be unconfigured with stm32_unconfiggpio() with * the same cfgset first before it can be set to non-alternative * function. * @@ -266,10 +266,10 @@ EXTERN const uint32_t g_gpiobase[STM32L4_NPORTS]; * ****************************************************************************/ -int stm32l4_configgpio(uint32_t cfgset); +int stm32_configgpio(uint32_t cfgset); /**************************************************************************** - * Name: stm32l4_unconfiggpio + * Name: stm32_unconfiggpio * * Description: * Unconfigure a GPIO pin based on bit-encoded description of the pin, set @@ -288,30 +288,30 @@ int stm32l4_configgpio(uint32_t cfgset); * ****************************************************************************/ -int stm32l4_unconfiggpio(uint32_t cfgset); +int stm32_unconfiggpio(uint32_t cfgset); /**************************************************************************** - * Name: stm32l4_gpiowrite + * Name: stm32_gpiowrite * * Description: * Write one or zero to the selected GPIO pin * ****************************************************************************/ -void stm32l4_gpiowrite(uint32_t pinset, bool value); +void stm32_gpiowrite(uint32_t pinset, bool value); /**************************************************************************** - * Name: stm32l4_gpioread + * Name: stm32_gpioread * * Description: * Read one or zero from the selected GPIO pin * ****************************************************************************/ -bool stm32l4_gpioread(uint32_t pinset); +bool stm32_gpioread(uint32_t pinset); /**************************************************************************** - * Name: stm32l4_gpiosetevent + * Name: stm32_gpiosetevent * * Description: * Sets/clears GPIO based event and interrupt triggers. @@ -330,11 +330,11 @@ bool stm32l4_gpioread(uint32_t pinset); * ****************************************************************************/ -int stm32l4_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, +int stm32_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, bool event, xcpt_t func, void *arg); /**************************************************************************** - * Function: stm32l4_dumpgpio + * Function: stm32_dumpgpio * * Description: * Dump all GPIO registers associated with the provided base address @@ -342,23 +342,23 @@ int stm32l4_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, ****************************************************************************/ #ifdef CONFIG_DEBUG_FEATURES -int stm32l4_dumpgpio(uint32_t pinset, const char *msg); +int stm32_dumpgpio(uint32_t pinset, const char *msg); #else -# define stm32l4_dumpgpio(p,m) +# define stm32_dumpgpio(p,m) #endif /**************************************************************************** - * Function: stm32l4_gpioinit + * Function: stm32_gpioinit * * Description: * Based on configuration within the .config file, it does: * - Remaps positions of alternative functions. * - * Typically called from stm32l4_start(). + * Typically called from stm32_start(). * ****************************************************************************/ -void stm32l4_gpioinit(void); +void stm32_gpioinit(void); #undef EXTERN #if defined(__cplusplus) @@ -366,4 +366,4 @@ void stm32l4_gpioinit(void); #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32L4_STM32L4_GPIO_H */ +#endif /* __ARCH_ARM_SRC_STM32L4_STM32_GPIO_H */ diff --git a/arch/arm/src/stm32l4/stm32l4_hsi48.c b/arch/arm/src/stm32l4/stm32l4_hsi48.c index 75ab0311ff4b5..65716843cb1dd 100644 --- a/arch/arm/src/stm32l4/stm32l4_hsi48.c +++ b/arch/arm/src/stm32l4/stm32l4_hsi48.c @@ -38,7 +38,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_enable_hsi48 + * Name: stm32_enable_hsi48 * * Description: * On STM32L4X3, STM32L496xx/4A6xx and STM32L4XR devices only, the HSI48 @@ -64,7 +64,7 @@ * ****************************************************************************/ -void stm32l4_enable_hsi48(enum syncsrc_e syncsrc) +void stm32_enable_hsi48(enum syncsrc_e syncsrc) { uint32_t regval; @@ -80,13 +80,13 @@ void stm32l4_enable_hsi48(enum syncsrc_e syncsrc) * enabled. */ - regval = getreg32(STM32L4_RCC_CRRCR); + regval = getreg32(STM32_RCC_CRRCR); regval |= RCC_CRRCR_HSI48ON; - putreg32(regval, STM32L4_RCC_CRRCR); + putreg32(regval, STM32_RCC_CRRCR); /* Wait for the HSI48 clock to stabilize */ - while ((getreg32(STM32L4_RCC_CRRCR) & RCC_CRRCR_HSI48RDY) == 0); + while ((getreg32(STM32_RCC_CRRCR) & RCC_CRRCR_HSI48RDY) == 0); /* Return if no synchronization */ @@ -100,7 +100,7 @@ void stm32l4_enable_hsi48(enum syncsrc_e syncsrc) * clock or the USB SOF signal. */ - regval = getreg32(STM32L4_CRS_CFGR); + regval = getreg32(STM32_CRS_CFGR); regval &= ~CRS_CFGR_SYNCSRC_MASK; switch (syncsrc) @@ -119,7 +119,7 @@ void stm32l4_enable_hsi48(enum syncsrc_e syncsrc) break; } - putreg32(regval, STM32L4_CRS_CFGR); + putreg32(regval, STM32_CRS_CFGR); /* Set the AUTOTRIMEN bit the CRS_CR register to enables the automatic * hardware adjustment of TRIM bits according to the measured frequency @@ -127,13 +127,13 @@ void stm32l4_enable_hsi48(enum syncsrc_e syncsrc) * frequency error counter and SYNC events. */ - regval = getreg32(STM32L4_CRS_CR); + regval = getreg32(STM32_CRS_CR); regval |= CRS_CR_AUTOTRIMEN | CRS_CR_CEN; - putreg32(regval, STM32L4_CRS_CR); + putreg32(regval, STM32_CRS_CR); } /**************************************************************************** - * Name: stm32l4_disable_hsi48 + * Name: stm32_disable_hsi48 * * Description: * Disable the HSI48 clock. @@ -146,23 +146,23 @@ void stm32l4_enable_hsi48(enum syncsrc_e syncsrc) * ****************************************************************************/ -void stm32l4_disable_hsi48(void) +void stm32_disable_hsi48(void) { uint32_t regval; /* Disable the HSI48 clock */ - regval = getreg32(STM32L4_RCC_CRRCR); + regval = getreg32(STM32_RCC_CRRCR); regval &= ~RCC_CRRCR_HSI48ON; - putreg32(regval, STM32L4_RCC_CRRCR); + putreg32(regval, STM32_RCC_CRRCR); /* Set other registers to the default settings. */ - regval = getreg32(STM32L4_CRS_CFGR); + regval = getreg32(STM32_CRS_CFGR); regval &= ~CRS_CFGR_SYNCSRC_MASK; - putreg32(regval, STM32L4_CRS_CFGR); + putreg32(regval, STM32_CRS_CFGR); - regval = getreg32(STM32L4_CRS_CR); + regval = getreg32(STM32_CRS_CR); regval &= ~CRS_CR_AUTOTRIMEN; - putreg32(regval, STM32L4_CRS_CR); + putreg32(regval, STM32_CRS_CR); } diff --git a/arch/arm/src/stm32l4/stm32l4_hsi48.h b/arch/arm/src/stm32l4/stm32l4_hsi48.h index 4028f5a2bbc82..de78d9f6be944 100644 --- a/arch/arm/src/stm32l4/stm32l4_hsi48.h +++ b/arch/arm/src/stm32l4/stm32l4_hsi48.h @@ -29,7 +29,7 @@ #include -#ifdef CONFIG_STM32L4_HAVE_HSI48 +#ifdef CONFIG_STM32_HAVE_HSI48 /**************************************************************************** * Public Types @@ -48,7 +48,7 @@ enum syncsrc_e ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_enable_hsi48 + * Name: stm32_enable_hsi48 * * Description: * On STM32L4X3, STM32L496xx/4A6xx and STM32L4XR devices only, the HSI48 @@ -74,10 +74,10 @@ enum syncsrc_e * ****************************************************************************/ -void stm32l4_enable_hsi48(enum syncsrc_e syncsrc); +void stm32_enable_hsi48(enum syncsrc_e syncsrc); /**************************************************************************** - * Name: stm32l4_disable_hsi48 + * Name: stm32_disable_hsi48 * * Description: * Disable the HSI48 clock. @@ -90,7 +90,7 @@ void stm32l4_enable_hsi48(enum syncsrc_e syncsrc); * ****************************************************************************/ -void stm32l4_disable_hsi48(void); +void stm32_disable_hsi48(void); -#endif /* CONFIG_STM32L4_HAVE_HSI48 */ +#endif /* CONFIG_STM32_HAVE_HSI48 */ #endif /* __ARCH_ARM_SRC_STM32L4_STM32L4_HSI48_H */ diff --git a/arch/arm/src/stm32l4/stm32l4_i2c.c b/arch/arm/src/stm32l4/stm32l4_i2c.c index 15dfac9e14ee0..235ae86b9ff65 100644 --- a/arch/arm/src/stm32l4/stm32l4_i2c.c +++ b/arch/arm/src/stm32l4/stm32l4_i2c.c @@ -171,28 +171,28 @@ * * To use this driver, enable the following configuration variable: * - * CONFIG_STM32L4_I2C + * CONFIG_STM32_I2C * * and one or more interfaces: * - * CONFIG_STM32L4_I2C1 - * CONFIG_STM32L4_I2C2 - * CONFIG_STM32L4_I2C3 - * CONFIG_STM32L4_I2C4 + * CONFIG_STM32_I2C1 + * CONFIG_STM32_I2C2 + * CONFIG_STM32_I2C3 + * CONFIG_STM32_I2C4 * * To configure the ISR timeout using fixed values - * (CONFIG_STM32L4_I2C_DYNTIMEO=n): + * (CONFIG_STM32_I2C_DYNTIMEO=n): * - * CONFIG_STM32L4_I2CTIMEOSEC (Timeout in seconds) - * CONFIG_STM32L4_I2CTIMEOMS (Timeout in milliseconds) - * CONFIG_STM32L4_I2CTIMEOTICKS (Timeout in ticks) + * CONFIG_STM32_I2CTIMEOSEC (Timeout in seconds) + * CONFIG_STM32_I2CTIMEOMS (Timeout in milliseconds) + * CONFIG_STM32_I2CTIMEOTICKS (Timeout in ticks) * * To configure the ISR timeout using dynamic values - * (CONFIG_STM32L4_I2C_DYNTIMEO=y): + * (CONFIG_STM32_I2C_DYNTIMEO=y): * - * CONFIG_STM32L4_I2C_DYNTIMEO_USECPERBYTE + * CONFIG_STM32_I2C_DYNTIMEO_USECPERBYTE * (Timeout in microseconds per byte) - * CONFIG_STM32L4_I2C_DYNTIMEO_STARTSTOP + * CONFIG_STM32_I2C_DYNTIMEO_STARTSTOP * (Timeout for start/stop inmilliseconds) * * Debugging output enabled with: @@ -268,12 +268,12 @@ #include "stm32l4_gpio.h" #include "stm32l4_rcc.h" #include "stm32l4_i2c.h" -#include "stm32l4_waste.h" +#include "stm32_waste.h" /* At least one I2C peripheral must be enabled */ -#if defined(CONFIG_STM32L4_I2C1) || defined(CONFIG_STM32L4_I2C2) || \ - defined(CONFIG_STM32L4_I2C3) || defined(CONFIG_STM32L4_I2C4) +#if defined(CONFIG_STM32_I2C1) || defined(CONFIG_STM32_I2C2) || \ + defined(CONFIG_STM32_I2C3) || defined(CONFIG_STM32_I2C4) /**************************************************************************** * Pre-processor Definitions @@ -285,25 +285,25 @@ /* Interrupt wait timeout in seconds and milliseconds */ -#if !defined(CONFIG_STM32L4_I2CTIMEOSEC) && !defined(CONFIG_STM32L4_I2CTIMEOMS) -# define CONFIG_STM32L4_I2CTIMEOSEC 0 -# define CONFIG_STM32L4_I2CTIMEOMS 500 /* Default is 500 milliseconds */ +#if !defined(CONFIG_STM32_I2CTIMEOSEC) && !defined(CONFIG_STM32_I2CTIMEOMS) +# define CONFIG_STM32_I2CTIMEOSEC 0 +# define CONFIG_STM32_I2CTIMEOMS 500 /* Default is 500 milliseconds */ # warning "Using Default 500 Ms Timeout" -#elif !defined(CONFIG_STM32L4_I2CTIMEOSEC) -# define CONFIG_STM32L4_I2CTIMEOSEC 0 /* User provided milliseconds */ -#elif !defined(CONFIG_STM32L4_I2CTIMEOMS) -# define CONFIG_STM32L4_I2CTIMEOMS 0 /* User provided seconds */ +#elif !defined(CONFIG_STM32_I2CTIMEOSEC) +# define CONFIG_STM32_I2CTIMEOSEC 0 /* User provided milliseconds */ +#elif !defined(CONFIG_STM32_I2CTIMEOMS) +# define CONFIG_STM32_I2CTIMEOMS 0 /* User provided seconds */ #endif /* Interrupt wait time timeout in system timer ticks */ -#ifndef CONFIG_STM32L4_I2CTIMEOTICKS -# define CONFIG_STM32L4_I2CTIMEOTICKS \ - (SEC2TICK(CONFIG_STM32L4_I2CTIMEOSEC) + MSEC2TICK(CONFIG_STM32L4_I2CTIMEOMS)) +#ifndef CONFIG_STM32_I2CTIMEOTICKS +# define CONFIG_STM32_I2CTIMEOTICKS \ + (SEC2TICK(CONFIG_STM32_I2CTIMEOSEC) + MSEC2TICK(CONFIG_STM32_I2CTIMEOMS)) #endif -#ifndef CONFIG_STM32L4_I2C_DYNTIMEO_STARTSTOP -# define CONFIG_STM32L4_I2C_DYNTIMEO_STARTSTOP TICK2USEC(CONFIG_STM32L4_I2CTIMEOTICKS) +#ifndef CONFIG_STM32_I2C_DYNTIMEO_STARTSTOP +# define CONFIG_STM32_I2C_DYNTIMEO_STARTSTOP TICK2USEC(CONFIG_STM32_I2CTIMEOTICKS) #endif /* Macros to convert a I2C pin to a GPIO output */ @@ -328,10 +328,10 @@ */ #ifndef CONFIG_I2C_TRACE -# define stm32l4_i2c_tracereset(p) -# define stm32l4_i2c_tracenew(p,s) -# define stm32l4_i2c_traceevent(p,e,a) -# define stm32l4_i2c_tracedump(p) +# define stm32_i2c_tracereset(p) +# define stm32_i2c_tracenew(p,s) +# define stm32_i2c_traceevent(p,e,a) +# define stm32_i2c_tracedump(p) #endif #ifndef CONFIG_I2C_NTRACE @@ -344,7 +344,7 @@ /* Interrupt state */ -enum stm32l4_intstate_e +enum stm32_intstate_e { INTSTATE_IDLE = 0, /* No I2C activity */ INTSTATE_WAITING, /* Waiting for completion of interrupt activity */ @@ -353,7 +353,7 @@ enum stm32l4_intstate_e /* Trace events */ -enum stm32l4_trace_e +enum stm32_trace_e { I2CEVENT_NONE = 0, I2CEVENT_STATE_ERROR, @@ -381,18 +381,18 @@ enum stm32l4_trace_e /* Trace data */ -struct stm32l4_trace_s +struct stm32_trace_s { uint32_t status; /* I2C 32-bit SR2|SR1 status */ uint32_t count; /* Interrupt count when status change */ - enum stm32l4_intstate_e event; /* Last event that occurred with this status */ + enum stm32_intstate_e event; /* Last event that occurred with status */ uint32_t parm; /* Parameter associated with the event */ clock_t time; /* First of event or first status */ }; /* I2C Device hardware configuration */ -struct stm32l4_i2c_config_s +struct stm32_i2c_config_s { uint32_t base; /* I2C base address */ uint32_t clk_bit; /* Clock enable bit */ @@ -407,18 +407,18 @@ struct stm32l4_i2c_config_s /* I2C Device Private Data */ -struct stm32l4_i2c_priv_s +struct stm32_i2c_priv_s { /* Port configuration */ - const struct stm32l4_i2c_config_s *config; + const struct stm32_i2c_config_s *config; int refs; /* Reference count */ mutex_t lock; /* Mutual exclusion mutex */ #ifndef CONFIG_I2C_POLLED sem_t sem_isr; /* Interrupt wait semaphore */ #endif - volatile uint8_t intstate; /* Interrupt handshake (see enum stm32l4_intstate_e) */ + volatile uint8_t intstate; /* Interrupt handshake (see enum stm32_intstate_e) */ uint8_t msgc; /* Message count */ struct i2c_msg_s *msgv; /* Message list */ @@ -436,7 +436,7 @@ struct stm32l4_i2c_priv_s /* The actual trace data */ - struct stm32l4_trace_s trace[CONFIG_I2C_NTRACE]; + struct stm32_trace_s trace[CONFIG_I2C_NTRACE]; #endif uint32_t status; /* End of transfer SR2|SR1 status */ @@ -448,10 +448,10 @@ struct stm32l4_i2c_priv_s /* I2C Device, Instance */ -struct stm32l4_i2c_inst_s +struct stm32_i2c_inst_s { const struct i2c_ops_s *ops; /* Standard I2C operations */ - struct stm32l4_i2c_priv_s *priv; /* Common driver private data structure */ + struct stm32_i2c_priv_s *priv; /* Common driver private data structure */ }; /**************************************************************************** @@ -459,57 +459,57 @@ struct stm32l4_i2c_inst_s ****************************************************************************/ static inline -uint16_t stm32l4_i2c_getreg(struct stm32l4_i2c_priv_s *priv, +uint16_t stm32_i2c_getreg(struct stm32_i2c_priv_s *priv, uint8_t offset); static inline -void stm32l4_i2c_putreg(struct stm32l4_i2c_priv_s *priv, +void stm32_i2c_putreg(struct stm32_i2c_priv_s *priv, uint8_t offset, uint16_t value); static inline -void stm32l4_i2c_putreg32(struct stm32l4_i2c_priv_s *priv, +void stm32_i2c_putreg32(struct stm32_i2c_priv_s *priv, uint8_t offset, uint32_t value); static inline -void stm32l4_i2c_modifyreg32(struct stm32l4_i2c_priv_s *priv, +void stm32_i2c_modifyreg32(struct stm32_i2c_priv_s *priv, uint8_t offset, uint32_t clearbits, uint32_t setbits); -#ifdef CONFIG_STM32L4_I2C_DYNTIMEO -static uint32_t stm32l4_i2c_toticks(int msgc, struct i2c_msg_s *msgs); -#endif /* CONFIG_STM32L4_I2C_DYNTIMEO */ +#ifdef CONFIG_STM32_I2C_DYNTIMEO +static uint32_t stm32_i2c_toticks(int msgc, struct i2c_msg_s *msgs); +#endif /* CONFIG_STM32_I2C_DYNTIMEO */ static inline -int stm32l4_i2c_sem_waitdone(struct stm32l4_i2c_priv_s *priv); +int stm32_i2c_sem_waitdone(struct stm32_i2c_priv_s *priv); static inline -void stm32l4_i2c_sem_waitstop(struct stm32l4_i2c_priv_s *priv); +void stm32_i2c_sem_waitstop(struct stm32_i2c_priv_s *priv); #ifdef CONFIG_I2C_TRACE -static void stm32l4_i2c_tracereset(struct stm32l4_i2c_priv_s *priv); -static void stm32l4_i2c_tracenew(struct stm32l4_i2c_priv_s *priv, +static void stm32_i2c_tracereset(struct stm32_i2c_priv_s *priv); +static void stm32_i2c_tracenew(struct stm32_i2c_priv_s *priv, uint32_t status); static void -stm32l4_i2c_traceevent(struct stm32l4_i2c_priv_s *priv, - enum stm32l4_trace_e event, uint32_t parm); -static void stm32l4_i2c_tracedump(struct stm32l4_i2c_priv_s *priv); +stm32_i2c_traceevent(struct stm32_i2c_priv_s *priv, + enum stm32_trace_e event, uint32_t parm); +static void stm32_i2c_tracedump(struct stm32_i2c_priv_s *priv); #endif /* CONFIG_I2C_TRACE */ -static void stm32l4_i2c_setclock(struct stm32l4_i2c_priv_s *priv, +static void stm32_i2c_setclock(struct stm32_i2c_priv_s *priv, uint32_t frequency); static inline -void stm32l4_i2c_sendstart(struct stm32l4_i2c_priv_s *priv); -static inline void stm32l4_i2c_sendstop(struct stm32l4_i2c_priv_s *priv); +void stm32_i2c_sendstart(struct stm32_i2c_priv_s *priv); +static inline void stm32_i2c_sendstop(struct stm32_i2c_priv_s *priv); static inline -uint32_t stm32l4_i2c_getstatus(struct stm32l4_i2c_priv_s *priv); -static int stm32l4_i2c_isr_process(struct stm32l4_i2c_priv_s *priv); +uint32_t stm32_i2c_getstatus(struct stm32_i2c_priv_s *priv); +static int stm32_i2c_isr_process(struct stm32_i2c_priv_s *priv); #ifndef CONFIG_I2C_POLLED -static int stm32l4_i2c_isr(int irq, void *context, void *arg); +static int stm32_i2c_isr(int irq, void *context, void *arg); #endif -static int stm32l4_i2c_init(struct stm32l4_i2c_priv_s *priv); -static int stm32l4_i2c_deinit(struct stm32l4_i2c_priv_s *priv); +static int stm32_i2c_init(struct stm32_i2c_priv_s *priv); +static int stm32_i2c_deinit(struct stm32_i2c_priv_s *priv); -static int stm32l4_i2c_process(struct i2c_master_s *dev, +static int stm32_i2c_process(struct i2c_master_s *dev, struct i2c_msg_s *msgs, int count); -static int stm32l4_i2c_transfer(struct i2c_master_s *dev, +static int stm32_i2c_transfer(struct i2c_master_s *dev, struct i2c_msg_s *msgs, int count); #ifdef CONFIG_I2C_RESET -static int stm32l4_i2c_reset(struct i2c_master_s *dev); +static int stm32_i2c_reset(struct i2c_master_s *dev); #endif #ifdef CONFIG_PM -static int stm32l4_i2c_pm_prepare(struct pm_callback_s *cb, int domain, +static int stm32_i2c_pm_prepare(struct pm_callback_s *cb, int domain, enum pm_state_e pmstate); #endif @@ -517,23 +517,23 @@ static int stm32l4_i2c_pm_prepare(struct pm_callback_s *cb, int domain, * Private Data ****************************************************************************/ -#ifdef CONFIG_STM32L4_I2C1 -static const struct stm32l4_i2c_config_s stm32l4_i2c1_config = +#ifdef CONFIG_STM32_I2C1 +static const struct stm32_i2c_config_s stm32_i2c1_config = { - .base = STM32L4_I2C1_BASE, + .base = STM32_I2C1_BASE, .clk_bit = RCC_APB1ENR1_I2C1EN, .reset_bit = RCC_APB1RSTR1_I2C1RST, .scl_pin = GPIO_I2C1_SCL, .sda_pin = GPIO_I2C1_SDA, #ifndef CONFIG_I2C_POLLED - .ev_irq = STM32L4_IRQ_I2C1EV, - .er_irq = STM32L4_IRQ_I2C1ER + .ev_irq = STM32_IRQ_I2C1EV, + .er_irq = STM32_IRQ_I2C1ER #endif }; -static struct stm32l4_i2c_priv_s stm32l4_i2c1_priv = +static struct stm32_i2c_priv_s stm32_i2c1_priv = { - .config = &stm32l4_i2c1_config, + .config = &stm32_i2c1_config, .refs = 0, .lock = NXMUTEX_INITIALIZER, #ifndef CONFIG_I2C_POLLED @@ -548,28 +548,28 @@ static struct stm32l4_i2c_priv_s stm32l4_i2c1_priv = .flags = 0, .status = 0, #ifdef CONFIG_PM - .pm_cb.prepare = stm32l4_i2c_pm_prepare, + .pm_cb.prepare = stm32_i2c_pm_prepare, #endif }; #endif -#ifdef CONFIG_STM32L4_I2C2 -static const struct stm32l4_i2c_config_s stm32l4_i2c2_config = +#ifdef CONFIG_STM32_I2C2 +static const struct stm32_i2c_config_s stm32_i2c2_config = { - .base = STM32L4_I2C2_BASE, + .base = STM32_I2C2_BASE, .clk_bit = RCC_APB1ENR1_I2C2EN, .reset_bit = RCC_APB1RSTR1_I2C2RST, .scl_pin = GPIO_I2C2_SCL, .sda_pin = GPIO_I2C2_SDA, #ifndef CONFIG_I2C_POLLED - .ev_irq = STM32L4_IRQ_I2C2EV, - .er_irq = STM32L4_IRQ_I2C2ER + .ev_irq = STM32_IRQ_I2C2EV, + .er_irq = STM32_IRQ_I2C2ER #endif }; -static struct stm32l4_i2c_priv_s stm32l4_i2c2_priv = +static struct stm32_i2c_priv_s stm32_i2c2_priv = { - .config = &stm32l4_i2c2_config, + .config = &stm32_i2c2_config, .refs = 0, .lock = NXMUTEX_INITIALIZER, #ifndef CONFIG_I2C_POLLED @@ -584,28 +584,28 @@ static struct stm32l4_i2c_priv_s stm32l4_i2c2_priv = .flags = 0, .status = 0, #ifdef CONFIG_PM - .pm_cb.prepare = stm32l4_i2c_pm_prepare, + .pm_cb.prepare = stm32_i2c_pm_prepare, #endif }; #endif -#ifdef CONFIG_STM32L4_I2C3 -static const struct stm32l4_i2c_config_s stm32l4_i2c3_config = +#ifdef CONFIG_STM32_I2C3 +static const struct stm32_i2c_config_s stm32_i2c3_config = { - .base = STM32L4_I2C3_BASE, + .base = STM32_I2C3_BASE, .clk_bit = RCC_APB1ENR1_I2C3EN, .reset_bit = RCC_APB1RSTR1_I2C3RST, .scl_pin = GPIO_I2C3_SCL, .sda_pin = GPIO_I2C3_SDA, #ifndef CONFIG_I2C_POLLED - .ev_irq = STM32L4_IRQ_I2C3EV, - .er_irq = STM32L4_IRQ_I2C3ER + .ev_irq = STM32_IRQ_I2C3EV, + .er_irq = STM32_IRQ_I2C3ER #endif }; -static struct stm32l4_i2c_priv_s stm32l4_i2c3_priv = +static struct stm32_i2c_priv_s stm32_i2c3_priv = { - .config = &stm32l4_i2c3_config, + .config = &stm32_i2c3_config, .refs = 0, .lock = NXMUTEX_INITIALIZER, #ifndef CONFIG_I2C_POLLED @@ -620,28 +620,28 @@ static struct stm32l4_i2c_priv_s stm32l4_i2c3_priv = .flags = 0, .status = 0, #ifdef CONFIG_PM - .pm_cb.prepare = stm32l4_i2c_pm_prepare, + .pm_cb.prepare = stm32_i2c_pm_prepare, #endif }; #endif -#ifdef CONFIG_STM32L4_I2C4 -static const struct stm32l4_i2c_config_s stm32l4_i2c4_config = +#ifdef CONFIG_STM32_I2C4 +static const struct stm32_i2c_config_s stm32_i2c4_config = { - .base = STM32L4_I2C4_BASE, + .base = STM32_I2C4_BASE, .clk_bit = RCC_APB1ENR2_I2C4EN, .reset_bit = RCC_APB1RSTR2_I2C4RST, .scl_pin = GPIO_I2C4_SCL, .sda_pin = GPIO_I2C4_SDA, #ifndef CONFIG_I2C_POLLED - .ev_irq = STM32L4_IRQ_I2C4EV, - .er_irq = STM32L4_IRQ_I2C4ER + .ev_irq = STM32_IRQ_I2C4EV, + .er_irq = STM32_IRQ_I2C4ER #endif }; -static struct stm32l4_i2c_priv_s stm32l4_i2c4_priv = +static struct stm32_i2c_priv_s stm32_i2c4_priv = { - .config = &stm32l4_i2c4_config, + .config = &stm32_i2c4_config, .refs = 0, .lock = NXMUTEX_INITIALIZER, #ifndef CONFIG_I2C_POLLED @@ -656,18 +656,18 @@ static struct stm32l4_i2c_priv_s stm32l4_i2c4_priv = .flags = 0, .status = 0, #ifdef CONFIG_PM - .pm_cb.prepare = stm32l4_i2c_pm_prepare, + .pm_cb.prepare = stm32_i2c_pm_prepare, #endif }; #endif /* Device Structures, Instantiation */ -static const struct i2c_ops_s stm32l4_i2c_ops = +static const struct i2c_ops_s stm32_i2c_ops = { - .transfer = stm32l4_i2c_transfer + .transfer = stm32_i2c_transfer #ifdef CONFIG_I2C_RESET - , .reset = stm32l4_i2c_reset + , .reset = stm32_i2c_reset #endif }; @@ -676,7 +676,7 @@ static const struct i2c_ops_s stm32l4_i2c_ops = ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_i2c_getreg + * Name: stm32_i2c_getreg * * Description: * Get a 16-bit register value by offset @@ -684,14 +684,14 @@ static const struct i2c_ops_s stm32l4_i2c_ops = ****************************************************************************/ static inline -uint16_t stm32l4_i2c_getreg(struct stm32l4_i2c_priv_s *priv, +uint16_t stm32_i2c_getreg(struct stm32_i2c_priv_s *priv, uint8_t offset) { return getreg16(priv->config->base + offset); } /**************************************************************************** - * Name: stm32l4_i2c_getreg32 + * Name: stm32_i2c_getreg32 * * Description: * Get a 32-bit register value by offset @@ -699,42 +699,42 @@ uint16_t stm32l4_i2c_getreg(struct stm32l4_i2c_priv_s *priv, ****************************************************************************/ static inline -uint32_t stm32l4_i2c_getreg32(struct stm32l4_i2c_priv_s *priv, +uint32_t stm32_i2c_getreg32(struct stm32_i2c_priv_s *priv, uint8_t offset) { return getreg32(priv->config->base + offset); } /**************************************************************************** - * Name: stm32l4_i2c_putreg + * Name: stm32_i2c_putreg * * Description: * Put a 16-bit register value by offset * ****************************************************************************/ -static inline void stm32l4_i2c_putreg(struct stm32l4_i2c_priv_s *priv, +static inline void stm32_i2c_putreg(struct stm32_i2c_priv_s *priv, uint8_t offset, uint16_t value) { putreg16(value, priv->config->base + offset); } /**************************************************************************** - * Name: stm32l4_i2c_putreg32 + * Name: stm32_i2c_putreg32 * * Description: * Put a 32-bit register value by offset * ****************************************************************************/ -static inline void stm32l4_i2c_putreg32(struct stm32l4_i2c_priv_s *priv, +static inline void stm32_i2c_putreg32(struct stm32_i2c_priv_s *priv, uint8_t offset, uint32_t value) { putreg32(value, priv->config->base + offset); } /**************************************************************************** - * Name: stm32l4_i2c_modifyreg32 + * Name: stm32_i2c_modifyreg32 * * Description: * Modify a 32-bit register value by offset @@ -742,7 +742,7 @@ static inline void stm32l4_i2c_putreg32(struct stm32l4_i2c_priv_s *priv, ****************************************************************************/ static inline -void stm32l4_i2c_modifyreg32(struct stm32l4_i2c_priv_s *priv, +void stm32_i2c_modifyreg32(struct stm32_i2c_priv_s *priv, uint8_t offset, uint32_t clearbits, uint32_t setbits) { @@ -750,7 +750,7 @@ void stm32l4_i2c_modifyreg32(struct stm32l4_i2c_priv_s *priv, } /**************************************************************************** - * Name: stm32l4_i2c_toticks + * Name: stm32_i2c_toticks * * Description: * Return a micro-second delay based on the number of bytes left to be @@ -758,8 +758,8 @@ void stm32l4_i2c_modifyreg32(struct stm32l4_i2c_priv_s *priv, * ****************************************************************************/ -#ifdef CONFIG_STM32L4_I2C_DYNTIMEO -static uint32_t stm32l4_i2c_toticks(int msgc, struct i2c_msg_s *msgs) +#ifdef CONFIG_STM32_I2C_DYNTIMEO +static uint32_t stm32_i2c_toticks(int msgc, struct i2c_msg_s *msgs) { size_t bytecount = 0; int i; @@ -775,12 +775,12 @@ static uint32_t stm32l4_i2c_toticks(int msgc, struct i2c_msg_s *msgs) * factor. */ - return USEC2TICK(CONFIG_STM32L4_I2C_DYNTIMEO_USECPERBYTE * bytecount); + return USEC2TICK(CONFIG_STM32_I2C_DYNTIMEO_USECPERBYTE * bytecount); } #endif /**************************************************************************** - * Name: stm32l4_i2c_enableinterrupts + * Name: stm32_i2c_enableinterrupts * * Description: * Enable I2C interrupts @@ -789,15 +789,15 @@ static uint32_t stm32l4_i2c_toticks(int msgc, struct i2c_msg_s *msgs) #ifndef CONFIG_I2C_POLLED static inline -void stm32l4_i2c_enableinterrupts(struct stm32l4_i2c_priv_s *priv) +void stm32_i2c_enableinterrupts(struct stm32_i2c_priv_s *priv) { - stm32l4_i2c_modifyreg32(priv, STM32L4_I2C_CR1_OFFSET, 0, + stm32_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, 0, (I2C_CR1_TXRX | I2C_CR1_NACKIE)); } #endif /**************************************************************************** - * Name: stm32l4_i2c_sem_waitdone + * Name: stm32_i2c_sem_waitdone * * Description: * Wait for a transfer to complete @@ -809,7 +809,7 @@ void stm32l4_i2c_enableinterrupts(struct stm32l4_i2c_priv_s *priv) #ifndef CONFIG_I2C_POLLED static inline -int stm32l4_i2c_sem_waitdone(struct stm32l4_i2c_priv_s *priv) +int stm32_i2c_sem_waitdone(struct stm32_i2c_priv_s *priv) { irqstate_t flags; int ret; @@ -819,11 +819,11 @@ int stm32l4_i2c_sem_waitdone(struct stm32l4_i2c_priv_s *priv) /* Enable I2C interrupts */ /* The TXIE and RXIE interrupts are enabled initially in - * stm32l4_i2c_process. The remainder of the interrupts, including + * stm32_i2c_process. The remainder of the interrupts, including * error-related, are enabled here. */ - stm32l4_i2c_modifyreg32(priv, STM32L4_I2C_CR1_OFFSET, 0, + stm32_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, 0, (I2C_CR1_ALLINTS & ~I2C_CR1_TXRX)); /* Signal the interrupt handler that we are waiting */ @@ -833,12 +833,12 @@ int stm32l4_i2c_sem_waitdone(struct stm32l4_i2c_priv_s *priv) { /* Wait until either the transfer is complete or the timeout expires */ -#ifdef CONFIG_STM32L4_I2C_DYNTIMEO +#ifdef CONFIG_STM32_I2C_DYNTIMEO ret = nxsem_tickwait_uninterruptible(&priv->sem_isr, - stm32l4_i2c_toticks(priv->msgc, priv->msgv)); + stm32_i2c_toticks(priv->msgc, priv->msgv)); #else ret = nxsem_tickwait_uninterruptible(&priv->sem_isr, - CONFIG_STM32L4_I2CTIMEOTICKS); + CONFIG_STM32_I2CTIMEOTICKS); #endif if (ret < 0) { @@ -861,14 +861,14 @@ int stm32l4_i2c_sem_waitdone(struct stm32l4_i2c_priv_s *priv) /* Disable I2C interrupts */ - stm32l4_i2c_modifyreg32(priv, STM32L4_I2C_CR1_OFFSET, I2C_CR1_ALLINTS, 0); + stm32_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, I2C_CR1_ALLINTS, 0); leave_critical_section(flags); return ret; } #else static inline -int stm32l4_i2c_sem_waitdone(struct stm32l4_i2c_priv_s *priv) +int stm32_i2c_sem_waitdone(struct stm32_i2c_priv_s *priv) { clock_t timeout; clock_t start; @@ -877,10 +877,10 @@ int stm32l4_i2c_sem_waitdone(struct stm32l4_i2c_priv_s *priv) /* Get the timeout value */ -#ifdef CONFIG_STM32L4_I2C_DYNTIMEO - timeout = stm32l4_i2c_toticks(priv->msgc, priv->msgv); +#ifdef CONFIG_STM32_I2C_DYNTIMEO + timeout = stm32_i2c_toticks(priv->msgc, priv->msgv); #else - timeout = CONFIG_STM32L4_I2CTIMEOTICKS; + timeout = CONFIG_STM32_I2CTIMEOTICKS; #endif /* Signal the interrupt handler that we are waiting. NOTE: Interrupts @@ -901,7 +901,7 @@ int stm32l4_i2c_sem_waitdone(struct stm32l4_i2c_priv_s *priv) * reports that it is done. */ - stm32l4_i2c_isr_process(priv); + stm32_i2c_isr_process(priv); } /* Loop until the transfer is complete. */ @@ -921,91 +921,91 @@ int stm32l4_i2c_sem_waitdone(struct stm32l4_i2c_priv_s *priv) #endif /**************************************************************************** - * Name: stm32l4_i2c_set_7bit_address + * Name: stm32_i2c_set_7bit_address * * Description: * ****************************************************************************/ static inline void -stm32l4_i2c_set_7bit_address(struct stm32l4_i2c_priv_s *priv) +stm32_i2c_set_7bit_address(struct stm32_i2c_priv_s *priv) { - stm32l4_i2c_modifyreg32(priv, STM32L4_I2C_CR2_OFFSET, I2C_CR2_SADD7_MASK, + stm32_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, I2C_CR2_SADD7_MASK, ((priv->msgv->addr & 0x7f) << I2C_CR2_SADD7_SHIFT)); } /**************************************************************************** - * Name: stm32l4_i2c_set_bytes_to_transfer + * Name: stm32_i2c_set_bytes_to_transfer * * Description: * ****************************************************************************/ static inline void -stm32l4_i2c_set_bytes_to_transfer(struct stm32l4_i2c_priv_s *priv, +stm32_i2c_set_bytes_to_transfer(struct stm32_i2c_priv_s *priv, uint8_t n_bytes) { - stm32l4_i2c_modifyreg32(priv, STM32L4_I2C_CR2_OFFSET, I2C_CR2_NBYTES_MASK, + stm32_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, I2C_CR2_NBYTES_MASK, (n_bytes << I2C_CR2_NBYTES_SHIFT)); } /**************************************************************************** - * Name: stm32l4_i2c_set_write_transfer_dir + * Name: stm32_i2c_set_write_transfer_dir * * Description: * ****************************************************************************/ static inline void -stm32l4_i2c_set_write_transfer_dir(struct stm32l4_i2c_priv_s *priv) +stm32_i2c_set_write_transfer_dir(struct stm32_i2c_priv_s *priv) { - stm32l4_i2c_modifyreg32(priv, STM32L4_I2C_CR2_OFFSET, I2C_CR2_RD_WRN, 0); + stm32_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, I2C_CR2_RD_WRN, 0); } /**************************************************************************** - * Name: stm32l4_i2c_set_read_transfer_dir + * Name: stm32_i2c_set_read_transfer_dir * * Description: * ****************************************************************************/ static inline void -stm32l4_i2c_set_read_transfer_dir(struct stm32l4_i2c_priv_s *priv) +stm32_i2c_set_read_transfer_dir(struct stm32_i2c_priv_s *priv) { - stm32l4_i2c_modifyreg32(priv, STM32L4_I2C_CR2_OFFSET, + stm32_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, 0, I2C_CR2_RD_WRN); } /**************************************************************************** - * Name: stm32l4_i2c_enable_reload + * Name: stm32_i2c_enable_reload * * Description: * ****************************************************************************/ static inline void -stm32l4_i2c_enable_reload(struct stm32l4_i2c_priv_s *priv) +stm32_i2c_enable_reload(struct stm32_i2c_priv_s *priv) { - stm32l4_i2c_modifyreg32(priv, STM32L4_I2C_CR2_OFFSET, + stm32_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, 0, I2C_CR2_RELOAD); } /**************************************************************************** - * Name: stm32l4_i2c_disable_reload + * Name: stm32_i2c_disable_reload * * Description: * ****************************************************************************/ static inline void -stm32l4_i2c_disable_reload(struct stm32l4_i2c_priv_s *priv) +stm32_i2c_disable_reload(struct stm32_i2c_priv_s *priv) { - stm32l4_i2c_modifyreg32(priv, STM32L4_I2C_CR2_OFFSET, + stm32_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, I2C_CR2_RELOAD, 0); } /**************************************************************************** - * Name: stm32l4_i2c_sem_waitstop + * Name: stm32_i2c_sem_waitstop * * Description: * Wait for a STOP to complete @@ -1013,7 +1013,7 @@ stm32l4_i2c_disable_reload(struct stm32l4_i2c_priv_s *priv) ****************************************************************************/ static inline -void stm32l4_i2c_sem_waitstop(struct stm32l4_i2c_priv_s *priv) +void stm32_i2c_sem_waitstop(struct stm32_i2c_priv_s *priv) { clock_t start; clock_t elapsed; @@ -1023,10 +1023,10 @@ void stm32l4_i2c_sem_waitstop(struct stm32l4_i2c_priv_s *priv) /* Select a timeout */ -#ifdef CONFIG_STM32L4_I2C_DYNTIMEO - timeout = USEC2TICK(CONFIG_STM32L4_I2C_DYNTIMEO_STARTSTOP); +#ifdef CONFIG_STM32_I2C_DYNTIMEO + timeout = USEC2TICK(CONFIG_STM32_I2C_DYNTIMEO_STARTSTOP); #else - timeout = CONFIG_STM32L4_I2CTIMEOTICKS; + timeout = CONFIG_STM32_I2CTIMEOTICKS; #endif /* Wait as stop might still be in progress */ @@ -1040,7 +1040,7 @@ void stm32l4_i2c_sem_waitstop(struct stm32l4_i2c_priv_s *priv) /* Check for STOP condition */ - cr = stm32l4_i2c_getreg32(priv, STM32L4_I2C_CR2_OFFSET); + cr = stm32_i2c_getreg32(priv, STM32_I2C_CR2_OFFSET); if ((cr & I2C_CR2_STOP) == 0) { return; @@ -1048,7 +1048,7 @@ void stm32l4_i2c_sem_waitstop(struct stm32l4_i2c_priv_s *priv) /* Check for timeout error */ - sr = stm32l4_i2c_getreg(priv, STM32L4_I2C_ISR_OFFSET); + sr = stm32_i2c_getreg(priv, STM32_I2C_ISR_OFFSET); if ((sr & I2C_INT_TIMEOUT) != 0) { return; @@ -1067,7 +1067,7 @@ void stm32l4_i2c_sem_waitstop(struct stm32l4_i2c_priv_s *priv) } /**************************************************************************** - * Name: stm32l4_i2c_trace* + * Name: stm32_i2c_trace* * * Description: * I2C trace instrumentation @@ -1075,9 +1075,9 @@ void stm32l4_i2c_sem_waitstop(struct stm32l4_i2c_priv_s *priv) ****************************************************************************/ #ifdef CONFIG_I2C_TRACE -static void stm32l4_i2c_traceclear(struct stm32l4_i2c_priv_s *priv) +static void stm32_i2c_traceclear(struct stm32_i2c_priv_s *priv) { - struct stm32l4_trace_s *trace = &priv->trace[priv->tndx]; + struct stm32_trace_s *trace = &priv->trace[priv->tndx]; trace->status = 0; /* I2C 32-bit status */ trace->count = 0; /* Interrupt count when status change */ @@ -1086,19 +1086,19 @@ static void stm32l4_i2c_traceclear(struct stm32l4_i2c_priv_s *priv) trace->time = 0; /* Time of first status or event */ } -static void stm32l4_i2c_tracereset(struct stm32l4_i2c_priv_s *priv) +static void stm32_i2c_tracereset(struct stm32_i2c_priv_s *priv) { /* Reset the trace info for a new data collection */ priv->tndx = 0; priv->start_time = clock_systime_ticks(); - stm32l4_i2c_traceclear(priv); + stm32_i2c_traceclear(priv); } -static void stm32l4_i2c_tracenew(struct stm32l4_i2c_priv_s *priv, +static void stm32_i2c_tracenew(struct stm32_i2c_priv_s *priv, uint32_t status) { - struct stm32l4_trace_s *trace = &priv->trace[priv->tndx]; + struct stm32_trace_s *trace = &priv->trace[priv->tndx]; /* Is the current entry uninitialized? Has the status changed? */ @@ -1124,7 +1124,7 @@ static void stm32l4_i2c_tracenew(struct stm32l4_i2c_priv_s *priv, /* Initialize the new trace entry */ - stm32l4_i2c_traceclear(priv); + stm32_i2c_traceclear(priv); trace->status = status; trace->count = 1; trace->time = clock_systime_ticks(); @@ -1137,10 +1137,10 @@ static void stm32l4_i2c_tracenew(struct stm32l4_i2c_priv_s *priv, } } -static void stm32l4_i2c_traceevent(struct stm32l4_i2c_priv_s *priv, - enum stm32l4_trace_e event, uint32_t parm) +static void stm32_i2c_traceevent(struct stm32_i2c_priv_s *priv, + enum stm32_trace_e event, uint32_t parm) { - struct stm32l4_trace_s *trace; + struct stm32_trace_s *trace; if (event != I2CEVENT_NONE) { @@ -1160,13 +1160,13 @@ static void stm32l4_i2c_traceevent(struct stm32l4_i2c_priv_s *priv, } priv->tndx++; - stm32l4_i2c_traceclear(priv); + stm32_i2c_traceclear(priv); } } -static void stm32l4_i2c_tracedump(struct stm32l4_i2c_priv_s *priv) +static void stm32_i2c_tracedump(struct stm32_i2c_priv_s *priv) { - struct stm32l4_trace_s *trace; + struct stm32_trace_s *trace; int i; syslog(LOG_DEBUG, "Elapsed time: %d\n", @@ -1185,7 +1185,7 @@ static void stm32l4_i2c_tracedump(struct stm32l4_i2c_priv_s *priv) #endif /* CONFIG_I2C_TRACE */ /**************************************************************************** - * Name: stm32l4_i2c_setclock + * Name: stm32_i2c_setclock * * Description: * @@ -1237,7 +1237,7 @@ static void stm32l4_i2c_tracedump(struct stm32l4_i2c_priv_s *priv) * ****************************************************************************/ -static void stm32l4_i2c_setclock(struct stm32l4_i2c_priv_s *priv, +static void stm32_i2c_setclock(struct stm32_i2c_priv_s *priv, uint32_t frequency) { int i2cclk_mhz; @@ -1252,21 +1252,21 @@ static void stm32l4_i2c_setclock(struct stm32l4_i2c_priv_s *priv, { /* I2C peripheral must be disabled to update clocking configuration */ - pe = (stm32l4_i2c_getreg32(priv, - STM32L4_I2C_CR1_OFFSET) & I2C_CR1_PE); + pe = (stm32_i2c_getreg32(priv, + STM32_I2C_CR1_OFFSET) & I2C_CR1_PE); if (pe) { - stm32l4_i2c_modifyreg32(priv, STM32L4_I2C_CR1_OFFSET, + stm32_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, I2C_CR1_PE, 0); } -#if defined(STM32L4_I2C_USE_HSI16) || (STM32L4_PCLK1_FREQUENCY == 16000000) +#if defined(STM32_I2C_USE_HSI16) || (STM32_PCLK1_FREQUENCY == 16000000) i2cclk_mhz = 16; -#elif STM32L4_PCLK1_FREQUENCY == 48000000 +#elif STM32_PCLK1_FREQUENCY == 48000000 i2cclk_mhz = 48; -#elif STM32L4_PCLK1_FREQUENCY == 80000000 +#elif STM32_PCLK1_FREQUENCY == 80000000 i2cclk_mhz = 80; -#elif STM32L4_PCLK1_FREQUENCY == 120000000 +#elif STM32_PCLK1_FREQUENCY == 120000000 i2cclk_mhz = 120; #else # warning STM32_I2C_INIT: Peripheral clock is PCLK and the speed/timing calculations need to be redone. @@ -1454,11 +1454,11 @@ static void stm32l4_i2c_setclock(struct stm32l4_i2c_priv_s *priv, (scl_h_period << I2C_TIMINGR_SCLH_SHIFT) | (scl_l_period << I2C_TIMINGR_SCLL_SHIFT); - stm32l4_i2c_putreg32(priv, STM32L4_I2C_TIMINGR_OFFSET, timingr); + stm32_i2c_putreg32(priv, STM32_I2C_TIMINGR_OFFSET, timingr); if (pe) { - stm32l4_i2c_modifyreg32(priv, STM32L4_I2C_CR1_OFFSET, + stm32_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, 0, I2C_CR1_PE); } @@ -1467,7 +1467,7 @@ static void stm32l4_i2c_setclock(struct stm32l4_i2c_priv_s *priv, } /**************************************************************************** - * Name: stm32l4_i2c_sendstart + * Name: stm32_i2c_sendstart * * Description: * Send the START condition / force Master mode @@ -1494,7 +1494,7 @@ static void stm32l4_i2c_setclock(struct stm32l4_i2c_priv_s *priv, ****************************************************************************/ static inline -void stm32l4_i2c_sendstart(struct stm32l4_i2c_priv_s *priv) +void stm32_i2c_sendstart(struct stm32_i2c_priv_s *priv) { bool next_norestart = false; @@ -1556,13 +1556,13 @@ void stm32l4_i2c_sendstart(struct stm32l4_i2c_priv_s *priv) { i2cinfo("RELOAD enabled: dcnt = %i msgc = %i\n", priv->dcnt, priv->msgc); - stm32l4_i2c_enable_reload(priv); + stm32_i2c_enable_reload(priv); } else { i2cinfo("RELOAD disable: dcnt = %i msgc = %i\n", priv->dcnt, priv->msgc); - stm32l4_i2c_disable_reload(priv); + stm32_i2c_disable_reload(priv); } /* Set the number of bytes to transfer (I2C_CR2->NBYTES) to the number of @@ -1572,18 +1572,18 @@ void stm32l4_i2c_sendstart(struct stm32l4_i2c_priv_s *priv) if (priv->dcnt > 255) { - stm32l4_i2c_set_bytes_to_transfer(priv, 255); + stm32_i2c_set_bytes_to_transfer(priv, 255); } else { - stm32l4_i2c_set_bytes_to_transfer(priv, priv->dcnt); + stm32_i2c_set_bytes_to_transfer(priv, priv->dcnt); } /* Set the (7 bit) address. * 10 bit addressing is not yet supported. */ - stm32l4_i2c_set_7bit_address(priv); + stm32_i2c_set_7bit_address(priv); /* The flag of the current message is used to determine the direction of * transfer required for the current message. @@ -1591,11 +1591,11 @@ void stm32l4_i2c_sendstart(struct stm32l4_i2c_priv_s *priv) if (priv->flags & I2C_M_READ) { - stm32l4_i2c_set_read_transfer_dir(priv); + stm32_i2c_set_read_transfer_dir(priv); } else { - stm32l4_i2c_set_write_transfer_dir(priv); + stm32_i2c_set_write_transfer_dir(priv); } /* Set the I2C_CR2->START bit to 1 to instruct the hardware to send the @@ -1605,11 +1605,11 @@ void stm32l4_i2c_sendstart(struct stm32l4_i2c_priv_s *priv) i2cinfo("Sending START: dcnt=%i msgc=%i flags=0x%04x\n", priv->dcnt, priv->msgc, priv->flags); - stm32l4_i2c_modifyreg32(priv, STM32L4_I2C_CR2_OFFSET, 0, I2C_CR2_START); + stm32_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, 0, I2C_CR2_START); } /**************************************************************************** - * Name: stm32l4_i2c_sendstop + * Name: stm32_i2c_sendstop * * Description: * Send the STOP conditions @@ -1621,17 +1621,17 @@ void stm32l4_i2c_sendstart(struct stm32l4_i2c_priv_s *priv) ****************************************************************************/ static inline -void stm32l4_i2c_sendstop(struct stm32l4_i2c_priv_s *priv) +void stm32_i2c_sendstop(struct stm32_i2c_priv_s *priv) { i2cinfo("Sending STOP\n"); - stm32l4_i2c_traceevent(priv, I2CEVENT_WRITE_STOP, 0); + stm32_i2c_traceevent(priv, I2CEVENT_WRITE_STOP, 0); - stm32l4_i2c_modifyreg32(priv, STM32L4_I2C_CR2_OFFSET, + stm32_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, 0, I2C_CR2_STOP); } /**************************************************************************** - * Name: stm32l4_i2c_getstatus + * Name: stm32_i2c_getstatus * * Description: * Get 32-bit status (SR1 and SR2 combined) @@ -1639,13 +1639,13 @@ void stm32l4_i2c_sendstop(struct stm32l4_i2c_priv_s *priv) ****************************************************************************/ static inline -uint32_t stm32l4_i2c_getstatus(struct stm32l4_i2c_priv_s *priv) +uint32_t stm32_i2c_getstatus(struct stm32_i2c_priv_s *priv) { - return getreg32(priv->config->base + STM32L4_I2C_ISR_OFFSET); + return getreg32(priv->config->base + STM32_I2C_ISR_OFFSET); } /**************************************************************************** - * Name: stm32l4_i2c_clearinterrupts + * Name: stm32_i2c_clearinterrupts * * Description: * Clear all interrupts @@ -1653,14 +1653,14 @@ uint32_t stm32l4_i2c_getstatus(struct stm32l4_i2c_priv_s *priv) ****************************************************************************/ static inline -void stm32l4_i2c_clearinterrupts(struct stm32l4_i2c_priv_s *priv) +void stm32_i2c_clearinterrupts(struct stm32_i2c_priv_s *priv) { - stm32l4_i2c_modifyreg32(priv, STM32L4_I2C_ICR_OFFSET, + stm32_i2c_modifyreg32(priv, STM32_I2C_ICR_OFFSET, 0, I2C_ICR_CLEARMASK); } /**************************************************************************** - * Name: stm32l4_i2c_isr_process + * Name: stm32_i2c_isr_process * * Description: * Common interrupt service routine (ISR) that handles I2C protocol logic. @@ -1669,22 +1669,22 @@ void stm32l4_i2c_clearinterrupts(struct stm32l4_i2c_priv_s *priv) * * This ISR is activated and deactivated by: * - * stm32l4_i2c_process + * stm32_i2c_process * and - * stm32l4_i2c_waitdone + * stm32_i2c_waitdone * * Input Parameters: * priv - The private struct of the I2C driver. * ****************************************************************************/ -static int stm32l4_i2c_isr_process(struct stm32l4_i2c_priv_s *priv) +static int stm32_i2c_isr_process(struct stm32_i2c_priv_s *priv) { uint32_t status; /* Get state of the I2C controller */ - status = stm32l4_i2c_getreg32(priv, STM32L4_I2C_ISR_OFFSET); + status = stm32_i2c_getreg32(priv, STM32_I2C_ISR_OFFSET); i2cinfo("ENTER: status = 0x%08" PRIx32 "\n", status); @@ -1694,8 +1694,8 @@ static int stm32l4_i2c_isr_process(struct stm32l4_i2c_priv_s *priv) /* If this is a new transmission set up the trace table accordingly */ - stm32l4_i2c_tracenew(priv, status); - stm32l4_i2c_traceevent(priv, I2CEVENT_ISR_CALL, 0); + stm32_i2c_tracenew(priv, status); + stm32_i2c_traceevent(priv, I2CEVENT_ISR_CALL, 0); /* ------------------- Start of I2C protocol handling ------------------ */ @@ -1737,7 +1737,7 @@ static int stm32l4_i2c_isr_process(struct stm32l4_i2c_priv_s *priv) i2cinfo("NACK: Address invalid: dcnt=%i " "msgc=%i status=0x%08" PRIx32 "\n", priv->dcnt, priv->msgc, status); - stm32l4_i2c_traceevent(priv, I2CEVENT_ADDRESS_NACKED, + stm32_i2c_traceevent(priv, I2CEVENT_ADDRESS_NACKED, priv->msgv->addr); } else @@ -1747,7 +1747,7 @@ static int stm32l4_i2c_isr_process(struct stm32l4_i2c_priv_s *priv) i2cinfo("NACK: NACK received: dcnt=%i " "msgc=%i status=0x%08" PRIx32 "\n", priv->dcnt, priv->msgc, status); - stm32l4_i2c_traceevent(priv, I2CEVENT_ADDRESS_NACKED, + stm32_i2c_traceevent(priv, I2CEVENT_ADDRESS_NACKED, priv->msgv->addr); } @@ -1801,7 +1801,7 @@ static int stm32l4_i2c_isr_process(struct stm32l4_i2c_priv_s *priv) { /* TXIS interrupt occurred, address valid, ready to transmit */ - stm32l4_i2c_traceevent(priv, I2CEVENT_WRITE, 0); + stm32_i2c_traceevent(priv, I2CEVENT_WRITE, 0); i2cinfo("TXIS: ENTER dcnt = %i msgc = %i status 0x%08" PRIx32 "\n", priv->dcnt, priv->msgc, status); @@ -1814,7 +1814,7 @@ static int stm32l4_i2c_isr_process(struct stm32l4_i2c_priv_s *priv) if (priv->astart == true) { i2cinfo("TXIS: Address Valid\n"); - stm32l4_i2c_traceevent(priv, I2CEVENT_ADDRESS_ACKED, + stm32_i2c_traceevent(priv, I2CEVENT_ADDRESS_ACKED, priv->msgv->addr); priv->astart = false; } @@ -1825,7 +1825,7 @@ static int stm32l4_i2c_isr_process(struct stm32l4_i2c_priv_s *priv) { /* Prepare to transmit the current byte */ - stm32l4_i2c_traceevent(priv, I2CEVENT_WRITE_TO_DR, priv->dcnt); + stm32_i2c_traceevent(priv, I2CEVENT_WRITE_TO_DR, priv->dcnt); i2cinfo("TXIS: Write Data 0x%02x\n", *priv->ptr); /* Decrement byte counter */ @@ -1847,13 +1847,13 @@ static int stm32l4_i2c_isr_process(struct stm32l4_i2c_priv_s *priv) if (priv->msgc == 1) { - stm32l4_i2c_disable_reload(priv); + stm32_i2c_disable_reload(priv); } } /* Transmit current byte */ - stm32l4_i2c_putreg(priv, STM32L4_I2C_TXDR_OFFSET, *priv->ptr); + stm32_i2c_putreg(priv, STM32_I2C_TXDR_OFFSET, *priv->ptr); /* Advance to next byte */ @@ -1866,7 +1866,7 @@ static int stm32l4_i2c_isr_process(struct stm32l4_i2c_priv_s *priv) i2cerr("ERROR: TXIS Unsupported state detected, dcnt=%i, " "status 0x%08" PRIx32 "\n", priv->dcnt, status); - stm32l4_i2c_traceevent(priv, I2CEVENT_WRITE_ERROR, 0); + stm32_i2c_traceevent(priv, I2CEVENT_WRITE_ERROR, 0); } i2cinfo("TXIS: EXIT dcnt = %i msgc = %i status 0x%08" PRIx32 "\n", @@ -1909,7 +1909,7 @@ static int stm32l4_i2c_isr_process(struct stm32l4_i2c_priv_s *priv) * (RXNE is set) then the driver can read from the data register. */ - stm32l4_i2c_traceevent(priv, I2CEVENT_READ, 0); + stm32_i2c_traceevent(priv, I2CEVENT_READ, 0); i2cinfo("RXNE: ENTER dcnt = %i msgc = %i status 0x%08" PRIx32 "\n", priv->dcnt, priv->msgc, status); @@ -1917,7 +1917,7 @@ static int stm32l4_i2c_isr_process(struct stm32l4_i2c_priv_s *priv) if (priv->dcnt > 0) { - stm32l4_i2c_traceevent(priv, I2CEVENT_RCVBYTE, priv->dcnt); + stm32_i2c_traceevent(priv, I2CEVENT_RCVBYTE, priv->dcnt); /* No interrupts or context switches may occur in the following * sequence. Otherwise, additional bytes may be received. @@ -1928,7 +1928,7 @@ static int stm32l4_i2c_isr_process(struct stm32l4_i2c_priv_s *priv) #endif /* Receive a byte */ - *priv->ptr = stm32l4_i2c_getreg(priv, STM32L4_I2C_RXDR_OFFSET); + *priv->ptr = stm32_i2c_getreg(priv, STM32_I2C_RXDR_OFFSET); i2cinfo("RXNE: Read Data 0x%02x\n", *priv->ptr); @@ -1948,8 +1948,8 @@ static int stm32l4_i2c_isr_process(struct stm32l4_i2c_priv_s *priv) { /* Unsupported state */ - stm32l4_i2c_traceevent(priv, I2CEVENT_READ_ERROR, 0); - status = stm32l4_i2c_getreg(priv, STM32L4_I2C_ISR_OFFSET); + stm32_i2c_traceevent(priv, I2CEVENT_READ_ERROR, 0); + status = stm32_i2c_getreg(priv, STM32_I2C_ISR_OFFSET); i2cerr("ERROR: RXNE Unsupported state detected, dcnt=%i, " "status 0x%08" PRIx32 "\n", priv->dcnt, status); @@ -2015,7 +2015,7 @@ static int stm32l4_i2c_isr_process(struct stm32l4_i2c_priv_s *priv) { i2cinfo("TC: RESTART: dcnt=%i, msgc=%i\n", priv->dcnt, priv->msgc); - stm32l4_i2c_traceevent(priv, I2CEVENT_TC_NO_RESTART, priv->msgc); + stm32_i2c_traceevent(priv, I2CEVENT_TC_NO_RESTART, priv->msgc); /* Issue a START condition. * @@ -2029,7 +2029,7 @@ static int stm32l4_i2c_isr_process(struct stm32l4_i2c_priv_s *priv) priv->msgv++; - stm32l4_i2c_sendstart(priv); + stm32_i2c_sendstart(priv); } else { @@ -2042,9 +2042,9 @@ static int stm32l4_i2c_isr_process(struct stm32l4_i2c_priv_s *priv) i2cinfo("TC: STOP: dcnt=%i msgc=%i\n", priv->dcnt, priv->msgc); - stm32l4_i2c_traceevent(priv, I2CEVENT_STOP, priv->dcnt); + stm32_i2c_traceevent(priv, I2CEVENT_STOP, priv->dcnt); - stm32l4_i2c_sendstop(priv); + stm32_i2c_sendstop(priv); /* Set signals that will terminate ISR and wake waiting thread */ @@ -2123,7 +2123,7 @@ static int stm32l4_i2c_isr_process(struct stm32l4_i2c_priv_s *priv) i2cinfo("TCR: DISABLE RELOAD: dcnt = %i msgc = %i\n", priv->dcnt, priv->msgc); - stm32l4_i2c_disable_reload(priv); + stm32_i2c_disable_reload(priv); } /* Update NBYTES with length of current message */ @@ -2131,7 +2131,7 @@ static int stm32l4_i2c_isr_process(struct stm32l4_i2c_priv_s *priv) i2cinfo("TCR: NEXT MSG dcnt = %i msgc = %i\n", priv->dcnt, priv->msgc); - stm32l4_i2c_set_bytes_to_transfer(priv, priv->dcnt); + stm32_i2c_set_bytes_to_transfer(priv, priv->dcnt); } else { @@ -2156,9 +2156,9 @@ static int stm32l4_i2c_isr_process(struct stm32l4_i2c_priv_s *priv) * the transfer. */ - stm32l4_i2c_enable_reload(priv); + stm32_i2c_enable_reload(priv); - stm32l4_i2c_set_bytes_to_transfer(priv, 255); + stm32_i2c_set_bytes_to_transfer(priv, 255); } else { @@ -2175,9 +2175,9 @@ static int stm32l4_i2c_isr_process(struct stm32l4_i2c_priv_s *priv) i2cinfo("TCR: DISABLE RELOAD: NBYTES = dcnt = %i msgc = %i\n", priv->dcnt, priv->msgc); - stm32l4_i2c_disable_reload(priv); + stm32_i2c_disable_reload(priv); - stm32l4_i2c_set_bytes_to_transfer(priv, priv->dcnt); + stm32_i2c_set_bytes_to_transfer(priv, priv->dcnt); } i2cinfo("TCR: EXIT dcnt = %i msgc = %i status 0x%08" PRIx32 "\n", @@ -2193,10 +2193,10 @@ static int stm32l4_i2c_isr_process(struct stm32l4_i2c_priv_s *priv) else if (priv->dcnt == -1 && priv->msgc == 0) { - status = stm32l4_i2c_getreg(priv, STM32L4_I2C_ISR_OFFSET); + status = stm32_i2c_getreg(priv, STM32_I2C_ISR_OFFSET); i2cwarn("WARNING: EMPTY CALL: Stopping ISR: status 0x%08" PRIx32 "\n", status); - stm32l4_i2c_traceevent(priv, I2CEVENT_ISR_EMPTY_CALL, 0); + stm32_i2c_traceevent(priv, I2CEVENT_ISR_EMPTY_CALL, 0); } /* Error handler @@ -2212,11 +2212,11 @@ static int stm32l4_i2c_isr_process(struct stm32l4_i2c_priv_s *priv) else { #ifdef CONFIG_I2C_POLLED - stm32l4_i2c_traceevent(priv, I2CEVENT_POLL_DEV_NOT_RDY, 0); + stm32_i2c_traceevent(priv, I2CEVENT_POLL_DEV_NOT_RDY, 0); #else /* Read rest of the state */ - status = stm32l4_i2c_getreg(priv, STM32L4_I2C_ISR_OFFSET); + status = stm32_i2c_getreg(priv, STM32_I2C_ISR_OFFSET); i2cerr("ERROR: Invalid state detected, status 0x%08" PRIx32 "\n", status); @@ -2225,7 +2225,7 @@ static int stm32l4_i2c_isr_process(struct stm32l4_i2c_priv_s *priv) priv->dcnt = -1; priv->msgc = 0; - stm32l4_i2c_traceevent(priv, I2CEVENT_STATE_ERROR, 0); + stm32_i2c_traceevent(priv, I2CEVENT_STATE_ERROR, 0); #endif } @@ -2234,7 +2234,7 @@ static int stm32l4_i2c_isr_process(struct stm32l4_i2c_priv_s *priv) /* Message Handling * * Transmission of the whole message chain has been completed. We have to - * terminate the ISR and wake up stm32l4_i2c_process() that is waiting for + * terminate the ISR and wake up stm32_i2c_process() that is waiting for * the ISR cycle to handle the sending/receiving of the messages. */ @@ -2242,7 +2242,7 @@ static int stm32l4_i2c_isr_process(struct stm32l4_i2c_priv_s *priv) { i2cinfo("MSG: Shutting down I2C ISR\n"); - stm32l4_i2c_traceevent(priv, I2CEVENT_ISR_SHUTDOWN, 0); + stm32_i2c_traceevent(priv, I2CEVENT_ISR_SHUTDOWN, 0); /* clear pointer to message content to reflect we are done * with the current transaction. @@ -2254,7 +2254,7 @@ static int stm32l4_i2c_isr_process(struct stm32l4_i2c_priv_s *priv) priv->intstate = INTSTATE_DONE; #else - status = stm32l4_i2c_getreg32(priv, STM32L4_I2C_ISR_OFFSET); + status = stm32_i2c_getreg32(priv, STM32_I2C_ISR_OFFSET); /* Update private state to capture NACK which is used in combination * with the astart flag to report the type of NACK received (address @@ -2268,7 +2268,7 @@ static int stm32l4_i2c_isr_process(struct stm32l4_i2c_priv_s *priv) /* Clear all interrupts */ - stm32l4_i2c_modifyreg32(priv, STM32L4_I2C_ICR_OFFSET, + stm32_i2c_modifyreg32(priv, STM32_I2C_ICR_OFFSET, 0, I2C_ICR_CLEARMASK); /* If a thread is waiting then inform it transfer is complete */ @@ -2281,14 +2281,14 @@ static int stm32l4_i2c_isr_process(struct stm32l4_i2c_priv_s *priv) #endif } - status = stm32l4_i2c_getreg32(priv, STM32L4_I2C_ISR_OFFSET); + status = stm32_i2c_getreg32(priv, STM32_I2C_ISR_OFFSET); i2cinfo("EXIT: status = 0x%08" PRIx32 "\n", status); return OK; } /**************************************************************************** - * Name: stm32l4_i2c_isr + * Name: stm32_i2c_isr * * Description: * Common I2C interrupt service routine @@ -2296,62 +2296,62 @@ static int stm32l4_i2c_isr_process(struct stm32l4_i2c_priv_s *priv) ****************************************************************************/ #ifndef CONFIG_I2C_POLLED -static int stm32l4_i2c_isr(int irq, void *context, void *arg) +static int stm32_i2c_isr(int irq, void *context, void *arg) { - struct stm32l4_i2c_priv_s *priv = (struct stm32l4_i2c_priv_s *)arg; + struct stm32_i2c_priv_s *priv = (struct stm32_i2c_priv_s *)arg; DEBUGASSERT(priv != NULL); - return stm32l4_i2c_isr_process(priv); + return stm32_i2c_isr_process(priv); } #endif /**************************************************************************** - * Name: stm32l4_i2c_init + * Name: stm32_i2c_init * * Description: * Setup the I2C hardware, ready for operation with defaults * ****************************************************************************/ -static int stm32l4_i2c_init(struct stm32l4_i2c_priv_s *priv) +static int stm32_i2c_init(struct stm32_i2c_priv_s *priv) { /* Power-up and configure GPIOs */ /* Enable power and reset the peripheral */ -#ifdef CONFIG_STM32L4_I2C4 - if (priv->config->base == STM32L4_I2C4_BASE) +#ifdef CONFIG_STM32_I2C4 + if (priv->config->base == STM32_I2C4_BASE) { - modifyreg32(STM32L4_RCC_APB1ENR2, 0, priv->config->clk_bit); - modifyreg32(STM32L4_RCC_APB1RSTR2, 0, priv->config->reset_bit); - modifyreg32(STM32L4_RCC_APB1RSTR2, priv->config->reset_bit, 0); + modifyreg32(STM32_RCC_APB1ENR2, 0, priv->config->clk_bit); + modifyreg32(STM32_RCC_APB1RSTR2, 0, priv->config->reset_bit); + modifyreg32(STM32_RCC_APB1RSTR2, priv->config->reset_bit, 0); } else #endif { - modifyreg32(STM32L4_RCC_APB1ENR1, 0, priv->config->clk_bit); - modifyreg32(STM32L4_RCC_APB1RSTR1, 0, priv->config->reset_bit); - modifyreg32(STM32L4_RCC_APB1RSTR1, priv->config->reset_bit, 0); + modifyreg32(STM32_RCC_APB1ENR1, 0, priv->config->clk_bit); + modifyreg32(STM32_RCC_APB1RSTR1, 0, priv->config->reset_bit); + modifyreg32(STM32_RCC_APB1RSTR1, priv->config->reset_bit, 0); } /* Configure pins */ - if (stm32l4_configgpio(priv->config->scl_pin) < 0) + if (stm32_configgpio(priv->config->scl_pin) < 0) { return ERROR; } - if (stm32l4_configgpio(priv->config->sda_pin) < 0) + if (stm32_configgpio(priv->config->sda_pin) < 0) { - stm32l4_unconfiggpio(priv->config->scl_pin); + stm32_unconfiggpio(priv->config->scl_pin); return ERROR; } #ifndef CONFIG_I2C_POLLED /* Attach error and event interrupts to the ISRs */ - irq_attach(priv->config->ev_irq, stm32l4_i2c_isr, priv); - irq_attach(priv->config->er_irq, stm32l4_i2c_isr, priv); + irq_attach(priv->config->ev_irq, stm32_i2c_isr, priv); + irq_attach(priv->config->er_irq, stm32_i2c_isr, priv); up_enable_irq(priv->config->ev_irq); up_enable_irq(priv->config->er_irq); #endif @@ -2364,33 +2364,33 @@ static int stm32l4_i2c_init(struct stm32l4_i2c_priv_s *priv) /* Force a frequency update */ priv->frequency = 0; - stm32l4_i2c_setclock(priv, 100000); + stm32_i2c_setclock(priv, 100000); /* Enable I2C peripheral */ - stm32l4_i2c_modifyreg32(priv, STM32L4_I2C_CR1_OFFSET, 0, I2C_CR1_PE); + stm32_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, 0, I2C_CR1_PE); return OK; } /**************************************************************************** - * Name: stm32l4_i2c_deinit + * Name: stm32_i2c_deinit * * Description: * Shutdown the I2C hardware * ****************************************************************************/ -static int stm32l4_i2c_deinit(struct stm32l4_i2c_priv_s *priv) +static int stm32_i2c_deinit(struct stm32_i2c_priv_s *priv) { /* Disable I2C */ - stm32l4_i2c_putreg32(priv, STM32L4_I2C_CR1_OFFSET, 0); + stm32_i2c_putreg32(priv, STM32_I2C_CR1_OFFSET, 0); /* Unconfigure GPIO pins */ - stm32l4_unconfiggpio(priv->config->scl_pin); - stm32l4_unconfiggpio(priv->config->sda_pin); + stm32_unconfiggpio(priv->config->scl_pin); + stm32_unconfiggpio(priv->config->sda_pin); #ifndef CONFIG_I2C_POLLED @@ -2404,22 +2404,22 @@ static int stm32l4_i2c_deinit(struct stm32l4_i2c_priv_s *priv) /* Disable clocking */ -#ifdef CONFIG_STM32L4_I2C4 - if (priv->config->base == STM32L4_I2C4_BASE) +#ifdef CONFIG_STM32_I2C4 + if (priv->config->base == STM32_I2C4_BASE) { - modifyreg32(STM32L4_RCC_APB1ENR2, priv->config->clk_bit, 0); + modifyreg32(STM32_RCC_APB1ENR2, priv->config->clk_bit, 0); } else #endif { - modifyreg32(STM32L4_RCC_APB1ENR1, priv->config->clk_bit, 0); + modifyreg32(STM32_RCC_APB1ENR1, priv->config->clk_bit, 0); } return OK; } /**************************************************************************** - * Name: stm32l4_i2c_process + * Name: stm32_i2c_process * * Description: * Common I2C transfer logic @@ -2429,11 +2429,11 @@ static int stm32l4_i2c_deinit(struct stm32l4_i2c_priv_s *priv) * ****************************************************************************/ -static int stm32l4_i2c_process(struct i2c_master_s *dev, +static int stm32_i2c_process(struct i2c_master_s *dev, struct i2c_msg_s *msgs, int count) { - struct stm32l4_i2c_inst_s *inst = (struct stm32l4_i2c_inst_s *)dev; - struct stm32l4_i2c_priv_s *priv = inst->priv; + struct stm32_i2c_inst_s *inst = (struct stm32_i2c_inst_s *)dev; + struct stm32_i2c_priv_s *priv = inst->priv; uint32_t status = 0; uint32_t cr1; uint32_t cr2; @@ -2444,11 +2444,11 @@ static int stm32l4_i2c_process(struct i2c_master_s *dev, /* Wait for any STOP in progress */ - stm32l4_i2c_sem_waitstop(priv); + stm32_i2c_sem_waitstop(priv); /* Clear any pending error interrupts */ - stm32l4_i2c_clearinterrupts(priv); + stm32_i2c_clearinterrupts(priv); /* Old transfers are done */ @@ -2457,14 +2457,14 @@ static int stm32l4_i2c_process(struct i2c_master_s *dev, /* Reset I2C trace logic */ - stm32l4_i2c_tracereset(priv); + stm32_i2c_tracereset(priv); /* Set I2C clock frequency (on change it toggles I2C_CR1_PE !) */ - stm32l4_i2c_setclock(priv, msgs->frequency); + stm32_i2c_setclock(priv, msgs->frequency); /* Trigger start condition, then the process moves into the ISR. I2C - * interrupts will be enabled within stm32l4_i2c_waitdone(). + * interrupts will be enabled within stm32_i2c_waitdone(). */ priv->status = 0; @@ -2473,17 +2473,17 @@ static int stm32l4_i2c_process(struct i2c_master_s *dev, /* Enable transmit and receive interrupts here so when we send the start * condition below the ISR will fire if the data was sent and some * response from the slave received. All other interrupts relevant to - * our needs are enabled in stm32l4_i2c_sem_waitdone() below. + * our needs are enabled in stm32_i2c_sem_waitdone() below. */ - stm32l4_i2c_enableinterrupts(priv); + stm32_i2c_enableinterrupts(priv); #endif /* Trigger START condition generation, which also sends the slave address * with read/write flag and the data in the first message */ - stm32l4_i2c_sendstart(priv); + stm32_i2c_sendstart(priv); /* Wait for the ISR to tell us that the transfer is complete by attempting * to grab the semaphore that is initially locked by the ISR. If the ISR @@ -2491,10 +2491,10 @@ static int stm32l4_i2c_process(struct i2c_master_s *dev, * the timeout period waitdone returns error and we report a timeout. */ - waitrc = stm32l4_i2c_sem_waitdone(priv); + waitrc = stm32_i2c_sem_waitdone(priv); - cr1 = stm32l4_i2c_getreg32(priv, STM32L4_I2C_CR1_OFFSET); - cr2 = stm32l4_i2c_getreg32(priv, STM32L4_I2C_CR2_OFFSET); + cr1 = stm32_i2c_getreg32(priv, STM32_I2C_CR1_OFFSET); + cr2 = stm32_i2c_getreg32(priv, STM32_I2C_CR2_OFFSET); #if !defined(CONFIG_DEBUG_I2C) UNUSED(cr1); UNUSED(cr2); @@ -2508,7 +2508,7 @@ static int stm32l4_i2c_process(struct i2c_master_s *dev, * like a NACK, so we reset the status field to include that information. */ - status = stm32l4_i2c_getstatus(priv); + status = stm32_i2c_getstatus(priv); /* The priv->status field can hold additional information like a NACK * event so we include that information. @@ -2613,7 +2613,7 @@ static int stm32l4_i2c_process(struct i2c_master_s *dev, /* This is not an error, but should not happen. The BUSY signal can be * present if devices on the bus are in an odd state and need to be reset. * NOTE: - * We will only see this busy indication if stm32l4_i2c_sem_waitdone() + * We will only see this busy indication if stm32_i2c_sem_waitdone() * fails above; Otherwise it is cleared. */ @@ -2623,7 +2623,7 @@ static int stm32l4_i2c_process(struct i2c_master_s *dev, * * This is a status condition rather than an error. * - * We will only see this busy indication if stm32l4_i2c_sem_waitdone() + * We will only see this busy indication if stm32_i2c_sem_waitdone() * fails above; Otherwise it is cleared by the hardware when the ISR * wraps up the transfer with a STOP condition. */ @@ -2631,7 +2631,7 @@ static int stm32l4_i2c_process(struct i2c_master_s *dev, clock_t start = clock_systime_ticks(); clock_t timeout = USEC2TICK(USEC_PER_SEC / priv->frequency) + 1; - status = stm32l4_i2c_getstatus(priv); + status = stm32_i2c_getstatus(priv); while (status & I2C_ISR_BUSY) { @@ -2642,49 +2642,49 @@ static int stm32l4_i2c_process(struct i2c_master_s *dev, break; } - status = stm32l4_i2c_getstatus(priv); + status = stm32_i2c_getstatus(priv); } } /* Dump the trace result */ - stm32l4_i2c_tracedump(priv); + stm32_i2c_tracedump(priv); nxmutex_unlock(&priv->lock); return -errval; } /**************************************************************************** - * Name: stm32l4_i2c_transfer + * Name: stm32_i2c_transfer * * Description: * Generic I2C transfer function * ****************************************************************************/ -static int stm32l4_i2c_transfer(struct i2c_master_s *dev, +static int stm32_i2c_transfer(struct i2c_master_s *dev, struct i2c_msg_s *msgs, int count) { - struct stm32l4_i2c_priv_s *priv; + struct stm32_i2c_priv_s *priv; int ret; DEBUGASSERT(dev); - priv = ((struct stm32l4_i2c_inst_s *)dev)->priv; + priv = ((struct stm32_i2c_inst_s *)dev)->priv; /* Ensure that address or flags don't change meanwhile */ ret = nxmutex_lock(&priv->lock); if (ret >= 0) { - ret = stm32l4_i2c_process(dev, msgs, count); + ret = stm32_i2c_process(dev, msgs, count); } return ret; } /**************************************************************************** - * Name: stm32l4_i2c_reset + * Name: stm32_i2c_reset * * Description: * Reset an I2C bus @@ -2692,9 +2692,9 @@ static int stm32l4_i2c_transfer(struct i2c_master_s *dev, ****************************************************************************/ #ifdef CONFIG_I2C_RESET -static int stm32l4_i2c_reset(struct i2c_master_s *dev) +static int stm32_i2c_reset(struct i2c_master_s *dev) { - struct stm32l4_i2c_priv_s *priv; + struct stm32_i2c_priv_s *priv; unsigned int clock_count; unsigned int stretch_count; uint32_t scl_gpio; @@ -2706,7 +2706,7 @@ static int stm32l4_i2c_reset(struct i2c_master_s *dev) /* Get I2C private structure */ - priv = ((struct stm32l4_i2c_inst_s *)dev)->priv; + priv = ((struct stm32_i2c_inst_s *)dev)->priv; /* Our caller must own a ref */ @@ -2728,7 +2728,7 @@ static int stm32l4_i2c_reset(struct i2c_master_s *dev) /* De-init the port */ - stm32l4_i2c_deinit(priv); + stm32_i2c_deinit(priv); /* Use GPIO configuration to un-wedge the bus */ @@ -2737,12 +2737,12 @@ static int stm32l4_i2c_reset(struct i2c_master_s *dev) /* Let SDA go high */ - stm32l4_gpiowrite(sda_gpio, 1); + stm32_gpiowrite(sda_gpio, 1); /* Clock the bus until any slaves currently driving it let it go. */ clock_count = 0; - while (!stm32l4_gpioread(sda_gpio)) + while (!stm32_gpioread(sda_gpio)) { /* Give up if we have tried too hard */ @@ -2757,7 +2757,7 @@ static int stm32l4_i2c_reset(struct i2c_master_s *dev) */ stretch_count = 0; - while (!stm32l4_gpioread(scl_gpio)) + while (!stm32_gpioread(scl_gpio)) { /* Give up if we have tried too hard */ @@ -2771,12 +2771,12 @@ static int stm32l4_i2c_reset(struct i2c_master_s *dev) /* Drive SCL low */ - stm32l4_gpiowrite(scl_gpio, 0); + stm32_gpiowrite(scl_gpio, 0); up_udelay(10); /* Drive SCL high again */ - stm32l4_gpiowrite(scl_gpio, 1); + stm32_gpiowrite(scl_gpio, 1); up_udelay(10); } @@ -2784,27 +2784,27 @@ static int stm32l4_i2c_reset(struct i2c_master_s *dev) * state machines. */ - stm32l4_gpiowrite(sda_gpio, 0); + stm32_gpiowrite(sda_gpio, 0); up_udelay(10); - stm32l4_gpiowrite(scl_gpio, 0); + stm32_gpiowrite(scl_gpio, 0); up_udelay(10); - stm32l4_gpiowrite(scl_gpio, 1); + stm32_gpiowrite(scl_gpio, 1); up_udelay(10); - stm32l4_gpiowrite(sda_gpio, 1); + stm32_gpiowrite(sda_gpio, 1); up_udelay(10); /* Revert the GPIO configuration. */ - stm32l4_unconfiggpio(sda_gpio); - stm32l4_unconfiggpio(scl_gpio); + stm32_unconfiggpio(sda_gpio); + stm32_unconfiggpio(scl_gpio); /* Re-init the port */ - stm32l4_i2c_init(priv); + stm32_i2c_init(priv); /* Restore the frequency */ - stm32l4_i2c_setclock(priv, frequency); + stm32_i2c_setclock(priv, frequency); ret = OK; out: @@ -2817,7 +2817,7 @@ static int stm32l4_i2c_reset(struct i2c_master_s *dev) #endif /* CONFIG_I2C_RESET */ /**************************************************************************** - * Name: stm32l4_i2c_pm_prepare + * Name: stm32_i2c_pm_prepare * * Description: * Request the driver to prepare for a new power state. This is a @@ -2846,12 +2846,12 @@ static int stm32l4_i2c_reset(struct i2c_master_s *dev) ****************************************************************************/ #ifdef CONFIG_PM -static int stm32l4_i2c_pm_prepare(struct pm_callback_s *cb, int domain, +static int stm32_i2c_pm_prepare(struct pm_callback_s *cb, int domain, enum pm_state_e pmstate) { - struct stm32l4_i2c_priv_s *priv = - (struct stm32l4_i2c_priv_s *)((char *)cb - - offsetof(struct stm32l4_i2c_priv_s, pm_cb)); + struct stm32_i2c_priv_s *priv = + (struct stm32_i2c_priv_s *)((char *)cb - + offsetof(struct stm32_i2c_priv_s, pm_cb)); /* Logic to prepare for a reduced power state goes here. */ @@ -2893,40 +2893,40 @@ static int stm32l4_i2c_pm_prepare(struct pm_callback_s *cb, int domain, ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_i2cbus_initialize + * Name: stm32_i2cbus_initialize * * Description: * Initialize one I2C bus * ****************************************************************************/ -struct i2c_master_s *stm32l4_i2cbus_initialize(int port) +struct i2c_master_s *stm32_i2cbus_initialize(int port) { - struct stm32l4_i2c_priv_s *priv = NULL; /* private data of device with multiple instances */ - struct stm32l4_i2c_inst_s *inst = NULL; /* device, single instance */ + struct stm32_i2c_priv_s *priv = NULL; /* private data of device with multiple instances */ + struct stm32_i2c_inst_s *inst = NULL; /* device, single instance */ /* Get I2C private structure */ switch (port) { -#ifdef CONFIG_STM32L4_I2C1 +#ifdef CONFIG_STM32_I2C1 case 1: - priv = (struct stm32l4_i2c_priv_s *)&stm32l4_i2c1_priv; + priv = (struct stm32_i2c_priv_s *)&stm32_i2c1_priv; break; #endif -#ifdef CONFIG_STM32L4_I2C2 +#ifdef CONFIG_STM32_I2C2 case 2: - priv = (struct stm32l4_i2c_priv_s *)&stm32l4_i2c2_priv; + priv = (struct stm32_i2c_priv_s *)&stm32_i2c2_priv; break; #endif -#ifdef CONFIG_STM32L4_I2C3 +#ifdef CONFIG_STM32_I2C3 case 3: - priv = (struct stm32l4_i2c_priv_s *)&stm32l4_i2c3_priv; + priv = (struct stm32_i2c_priv_s *)&stm32_i2c3_priv; break; #endif -#ifdef CONFIG_STM32L4_I2C4 +#ifdef CONFIG_STM32_I2C4 case 4: - priv = (struct stm32l4_i2c_priv_s *)&stm32l4_i2c4_priv; + priv = (struct stm32_i2c_priv_s *)&stm32_i2c4_priv; break; #endif default: @@ -2935,14 +2935,14 @@ struct i2c_master_s *stm32l4_i2cbus_initialize(int port) /* Allocate instance */ - if (!(inst = kmm_malloc(sizeof(struct stm32l4_i2c_inst_s)))) + if (!(inst = kmm_malloc(sizeof(struct stm32_i2c_inst_s)))) { return NULL; } /* Initialize instance */ - inst->ops = &stm32l4_i2c_ops; + inst->ops = &stm32_i2c_ops; inst->priv = priv; /* Init private data for the first time, increment refs count, @@ -2952,7 +2952,7 @@ struct i2c_master_s *stm32l4_i2cbus_initialize(int port) nxmutex_lock(&priv->lock); if (priv->refs++ == 0) { - stm32l4_i2c_init(priv); + stm32_i2c_init(priv); #ifdef CONFIG_PM /* Register to receive power management callbacks */ @@ -2966,19 +2966,19 @@ struct i2c_master_s *stm32l4_i2cbus_initialize(int port) } /**************************************************************************** - * Name: stm32l4_i2cbus_uninitialize + * Name: stm32_i2cbus_uninitialize * * Description: * Uninitialize an I2C bus * ****************************************************************************/ -int stm32l4_i2cbus_uninitialize(struct i2c_master_s *dev) +int stm32_i2cbus_uninitialize(struct i2c_master_s *dev) { - struct stm32l4_i2c_priv_s *priv; + struct stm32_i2c_priv_s *priv; DEBUGASSERT(dev); - priv = ((struct stm32l4_i2c_inst_s *)dev)->priv; + priv = ((struct stm32_i2c_inst_s *)dev)->priv; /* Decrement refs and check for underflow */ @@ -3003,11 +3003,11 @@ int stm32l4_i2cbus_uninitialize(struct i2c_master_s *dev) /* Disable power and other HW resource (GPIO's) */ - stm32l4_i2c_deinit(priv); + stm32_i2c_deinit(priv); nxmutex_unlock(&priv->lock); kmm_free(dev); return OK; } -#endif /* CONFIG_STM32L4_I2C1 || CONFIG_STM32L4_I2C2 || CONFIG_STM32L4_I2C3 || CONFIG_STM32L4_I2C4 */ +#endif /* CONFIG_STM32_I2C1 || CONFIG_STM32_I2C2 || CONFIG_STM32_I2C3 || CONFIG_STM32_I2C4 */ diff --git a/arch/arm/src/stm32l4/stm32l4_i2c.h b/arch/arm/src/stm32l4/stm32l4_i2c.h index 9381a169230a7..c69ed3b9b28da 100644 --- a/arch/arm/src/stm32l4/stm32l4_i2c.h +++ b/arch/arm/src/stm32l4/stm32l4_i2c.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32L4_STM32L4_I2C_H -#define __ARCH_ARM_SRC_STM32L4_STM32L4_I2C_H +#ifndef __ARCH_ARM_SRC_STM32L4_STM32_I2C_H +#define __ARCH_ARM_SRC_STM32L4_STM32_I2C_H /**************************************************************************** * Included Files @@ -41,10 +41,10 @@ * seconds per byte value must be provided as well. */ -#ifdef CONFIG_STM32L4_I2C_DYNTIMEO -# if CONFIG_STM32L4_I2C_DYNTIMEO_USECPERBYTE < 1 -# warning "Ignoring CONFIG_STM32L4_I2C_DYNTIMEO because of CONFIG_STM32L4_I2C_DYNTIMEO_USECPERBYTE" -# undef CONFIG_STM32L4_I2C_DYNTIMEO +#ifdef CONFIG_STM32_I2C_DYNTIMEO +# if CONFIG_STM32_I2C_DYNTIMEO_USECPERBYTE < 1 +# warning "Ignoring CONFIG_STM32_I2C_DYNTIMEO because of CONFIG_STM32_I2C_DYNTIMEO_USECPERBYTE" +# undef CONFIG_STM32_I2C_DYNTIMEO # endif #endif @@ -53,7 +53,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_i2cbus_initialize + * Name: stm32_i2cbus_initialize * * Description: * Initialize the selected I2C port. And return a unique instance of struct @@ -69,16 +69,16 @@ * ****************************************************************************/ -struct i2c_master_s *stm32l4_i2cbus_initialize(int port); +struct i2c_master_s *stm32_i2cbus_initialize(int port); /**************************************************************************** - * Name: stm32l4_i2cbus_uninitialize + * Name: stm32_i2cbus_uninitialize * * Description: * De-initialize the selected I2C port, and power down the device. * * Input Parameters: - * Device structure as returned by the stm32l4_i2cbus_initialize() + * Device structure as returned by the stm32_i2cbus_initialize() * * Returned Value: * OK on success, ERROR when internal reference count mismatch or dev @@ -86,6 +86,6 @@ struct i2c_master_s *stm32l4_i2cbus_initialize(int port); * ****************************************************************************/ -int stm32l4_i2cbus_uninitialize(struct i2c_master_s *dev); +int stm32_i2cbus_uninitialize(struct i2c_master_s *dev); -#endif /* __ARCH_ARM_SRC_STM32L4_STM32L4_I2C_H */ +#endif /* __ARCH_ARM_SRC_STM32L4_STM32_I2C_H */ diff --git a/arch/arm/src/stm32l4/stm32l4_idle.c b/arch/arm/src/stm32l4/stm32l4_idle.c index 9ab0ccdf05984..985d307308bf1 100644 --- a/arch/arm/src/stm32l4/stm32l4_idle.c +++ b/arch/arm/src/stm32l4/stm32l4_idle.c @@ -119,12 +119,12 @@ static void up_idlepm(void) /* Enter STOP mode */ BEGIN_IDLE(); - stm32l4_pmstop(true); + stm32_pmstop(true); END_IDLE(); /* Set correct clock again after returning from STOP */ - stm32l4_clockenable(); + stm32_clockenable(); /* Inform of all drivers of the new state */ @@ -137,7 +137,7 @@ static void up_idlepm(void) break; case PM_SLEEP: - stm32l4_pmstandby(); + stm32_pmstandby(); break; default: @@ -184,7 +184,7 @@ void up_idle(void) /* Sleep until an interrupt occurs to save power. */ -#if !(defined(CONFIG_DEBUG_SYMBOLS) && defined(CONFIG_STM32L4_DISABLE_IDLE_SLEEP_DURING_DEBUG)) +#if !(defined(CONFIG_DEBUG_SYMBOLS) && defined(CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG)) BEGIN_IDLE(); asm("WFI"); END_IDLE(); diff --git a/arch/arm/src/stm32l4/stm32l4_irq.c b/arch/arm/src/stm32l4/stm32l4_irq.c index 3cbb653dd08db..53ec98f34f6c8 100644 --- a/arch/arm/src/stm32l4/stm32l4_irq.c +++ b/arch/arm/src/stm32l4/stm32l4_irq.c @@ -38,7 +38,7 @@ #include "nvic.h" #include "ram_vectors.h" #include "arm_internal.h" -#include "stm32l4.h" +#include "stm32.h" /**************************************************************************** * Pre-processor Definitions @@ -64,7 +64,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_dumpnvic + * Name: stm32_dumpnvic * * Description: * Dump some interesting NVIC registers @@ -72,7 +72,7 @@ ****************************************************************************/ #if defined(CONFIG_DEBUG_IRQ_INFO) -static void stm32l4_dumpnvic(const char *msg, int irq) +static void stm32_dumpnvic(const char *msg, int irq) { irqstate_t flags; @@ -128,11 +128,11 @@ static void stm32l4_dumpnvic(const char *msg, int irq) leave_critical_section(flags); } #else -# define stm32l4_dumpnvic(msg, irq) +# define stm32_dumpnvic(msg, irq) #endif /**************************************************************************** - * Name: stm32l4_nmi, stm32l4_pendsv, stm32l4_pendsv, stm32l4_reserved + * Name: stm32_nmi, stm32_pendsv, stm32_pendsv, stm32_reserved * * Description: * Handlers for various exceptions. None are handled and all are fatal @@ -142,7 +142,7 @@ static void stm32l4_dumpnvic(const char *msg, int irq) ****************************************************************************/ #ifdef CONFIG_DEBUG_FEATURES -static int stm32l4_nmi(int irq, void *context, void *arg) +static int stm32_nmi(int irq, void *context, void *arg) { up_irq_save(); _err("PANIC!!! NMI received\n"); @@ -150,7 +150,7 @@ static int stm32l4_nmi(int irq, void *context, void *arg) return 0; } -static int stm32l4_pendsv(int irq, void *context, void *arg) +static int stm32_pendsv(int irq, void *context, void *arg) { #ifndef CONFIG_ARCH_HIPRI_INTERRUPT up_irq_save(); @@ -160,7 +160,7 @@ static int stm32l4_pendsv(int irq, void *context, void *arg) return 0; } -static int stm32l4_reserved(int irq, void *context, void *arg) +static int stm32_reserved(int irq, void *context, void *arg) { up_irq_save(); _err("PANIC!!! Reserved interrupt\n"); @@ -170,7 +170,7 @@ static int stm32l4_reserved(int irq, void *context, void *arg) #endif /**************************************************************************** - * Name: stm32l4_prioritize_syscall + * Name: stm32_prioritize_syscall * * Description: * Set the priority of an exception. This function may be needed @@ -178,7 +178,7 @@ static int stm32l4_reserved(int irq, void *context, void *arg) * ****************************************************************************/ -static inline void stm32l4_prioritize_syscall(int priority) +static inline void stm32_prioritize_syscall(int priority) { uint32_t regval; @@ -191,7 +191,7 @@ static inline void stm32l4_prioritize_syscall(int priority) } /**************************************************************************** - * Name: stm32l4_irqinfo + * Name: stm32_irqinfo * * Description: * Given an IRQ number, provide the register and bit setting to enable or @@ -199,18 +199,18 @@ static inline void stm32l4_prioritize_syscall(int priority) * ****************************************************************************/ -static int stm32l4_irqinfo(int irq, uintptr_t *regaddr, uint32_t *bit, +static int stm32_irqinfo(int irq, uintptr_t *regaddr, uint32_t *bit, uintptr_t offset) { int n; - DEBUGASSERT(irq >= STM32L4_IRQ_NMI && irq < NR_IRQS); + DEBUGASSERT(irq >= STM32_IRQ_NMI && irq < NR_IRQS); /* Check for external interrupt */ - if (irq >= STM32L4_IRQ_FIRST) + if (irq >= STM32_IRQ_FIRST) { - n = irq - STM32L4_IRQ_FIRST; + n = irq - STM32_IRQ_FIRST; *regaddr = NVIC_IRQ_ENABLE(n) + offset; *bit = (uint32_t)1 << (n & 0x1f); } @@ -220,19 +220,19 @@ static int stm32l4_irqinfo(int irq, uintptr_t *regaddr, uint32_t *bit, else { *regaddr = NVIC_SYSHCON; - if (irq == STM32L4_IRQ_MEMFAULT) + if (irq == STM32_IRQ_MEMFAULT) { *bit = NVIC_SYSHCON_MEMFAULTENA; } - else if (irq == STM32L4_IRQ_BUSFAULT) + else if (irq == STM32_IRQ_BUSFAULT) { *bit = NVIC_SYSHCON_BUSFAULTENA; } - else if (irq == STM32L4_IRQ_USAGEFAULT) + else if (irq == STM32_IRQ_USAGEFAULT) { *bit = NVIC_SYSHCON_USGFAULTENA; } - else if (irq == STM32L4_IRQ_SYSTICK) + else if (irq == STM32_IRQ_SYSTICK) { *regaddr = NVIC_SYSTICK_CTRL; *bit = NVIC_SYSTICK_CTRL_ENABLE; @@ -262,7 +262,7 @@ void up_irqinitialize(void) /* Disable all interrupts */ - for (i = 0; i < NR_IRQS - STM32L4_IRQ_FIRST; i += 32) + for (i = 0; i < NR_IRQS - STM32_IRQ_FIRST; i += 32) { putreg32(0xffffffff, NVIC_IRQ_CLEAR(i)); } @@ -316,42 +316,42 @@ void up_irqinitialize(void) * under certain conditions. */ - irq_attach(STM32L4_IRQ_SVCALL, arm_svcall, NULL); - irq_attach(STM32L4_IRQ_HARDFAULT, arm_hardfault, NULL); + irq_attach(STM32_IRQ_SVCALL, arm_svcall, NULL); + irq_attach(STM32_IRQ_HARDFAULT, arm_hardfault, NULL); /* Set the priority of the SVCall interrupt */ #ifdef CONFIG_ARCH_IRQPRIO - /* up_prioritize_irq(STM32L4_IRQ_PENDSV, NVIC_SYSH_PRIORITY_MIN); */ + /* up_prioritize_irq(STM32_IRQ_PENDSV, NVIC_SYSH_PRIORITY_MIN); */ #endif - stm32l4_prioritize_syscall(NVIC_SYSH_SVCALL_PRIORITY); + stm32_prioritize_syscall(NVIC_SYSH_SVCALL_PRIORITY); /* If the MPU is enabled, then attach and enable the Memory Management * Fault handler. */ #ifdef CONFIG_ARM_MPU - irq_attach(STM32L4_IRQ_MEMFAULT, arm_memfault, NULL); - up_enable_irq(STM32L4_IRQ_MEMFAULT); + irq_attach(STM32_IRQ_MEMFAULT, arm_memfault, NULL); + up_enable_irq(STM32_IRQ_MEMFAULT); #endif /* Attach all other processor exceptions (except reset and sys tick) */ #ifdef CONFIG_DEBUG_FEATURES - irq_attach(STM32L4_IRQ_NMI, stm32l4_nmi, NULL); + irq_attach(STM32_IRQ_NMI, stm32_nmi, NULL); #ifndef CONFIG_ARM_MPU - irq_attach(STM32L4_IRQ_MEMFAULT, arm_memfault, NULL); + irq_attach(STM32_IRQ_MEMFAULT, arm_memfault, NULL); #endif - irq_attach(STM32L4_IRQ_BUSFAULT, arm_busfault, NULL); - irq_attach(STM32L4_IRQ_USAGEFAULT, arm_usagefault, NULL); - irq_attach(STM32L4_IRQ_PENDSV, stm32l4_pendsv, NULL); + irq_attach(STM32_IRQ_BUSFAULT, arm_busfault, NULL); + irq_attach(STM32_IRQ_USAGEFAULT, arm_usagefault, NULL); + irq_attach(STM32_IRQ_PENDSV, stm32_pendsv, NULL); arm_enable_dbgmonitor(); - irq_attach(STM32L4_IRQ_DBGMONITOR, arm_dbgmonitor, NULL); - irq_attach(STM32L4_IRQ_RESERVED, stm32l4_reserved, NULL); + irq_attach(STM32_IRQ_DBGMONITOR, arm_dbgmonitor, NULL); + irq_attach(STM32_IRQ_RESERVED, stm32_reserved, NULL); #endif - stm32l4_dumpnvic("initial", NR_IRQS); + stm32_dumpnvic("initial", NR_IRQS); #ifndef CONFIG_SUPPRESS_INTERRUPTS @@ -376,7 +376,7 @@ void up_disable_irq(int irq) uint32_t regval; uint32_t bit; - if (stm32l4_irqinfo(irq, ®addr, &bit, NVIC_CLRENA_OFFSET) == 0) + if (stm32_irqinfo(irq, ®addr, &bit, NVIC_CLRENA_OFFSET) == 0) { /* Modify the appropriate bit in the register to disable the interrupt. * For normal interrupts, we need to set the bit in the associated @@ -384,7 +384,7 @@ void up_disable_irq(int irq) * clear the bit in the System Handler Control and State Register. */ - if (irq >= STM32L4_IRQ_FIRST) + if (irq >= STM32_IRQ_FIRST) { putreg32(bit, regaddr); } @@ -411,7 +411,7 @@ void up_enable_irq(int irq) uint32_t regval; uint32_t bit; - if (stm32l4_irqinfo(irq, ®addr, &bit, NVIC_ENA_OFFSET) == 0) + if (stm32_irqinfo(irq, ®addr, &bit, NVIC_ENA_OFFSET) == 0) { /* Modify the appropriate bit in the register to enable the interrupt. * For normal interrupts, we need to set the bit in the associated @@ -419,7 +419,7 @@ void up_enable_irq(int irq) * set the bit in the System Handler Control and State Register. */ - if (irq >= STM32L4_IRQ_FIRST) + if (irq >= STM32_IRQ_FIRST) { putreg32(bit, regaddr); } @@ -462,10 +462,10 @@ int up_prioritize_irq(int irq, int priority) uint32_t regval; int shift; - DEBUGASSERT(irq >= STM32L4_IRQ_MEMFAULT && irq < NR_IRQS && + DEBUGASSERT(irq >= STM32_IRQ_MEMFAULT && irq < NR_IRQS && (unsigned)priority <= NVIC_SYSH_PRIORITY_MIN); - if (irq < STM32L4_IRQ_FIRST) + if (irq < STM32_IRQ_FIRST) { /* NVIC_SYSH_PRIORITY() maps {0..15} to one of three priority * registers (0-3 are invalid) @@ -478,7 +478,7 @@ int up_prioritize_irq(int irq, int priority) { /* NVIC_IRQ_PRIORITY() maps {0..} to one of many priority registers */ - irq -= STM32L4_IRQ_FIRST; + irq -= STM32_IRQ_FIRST; regaddr = NVIC_IRQ_PRIORITY(irq); } @@ -488,7 +488,7 @@ int up_prioritize_irq(int irq, int priority) regval |= (priority << shift); putreg32(regval, regaddr); - stm32l4_dumpnvic("prioritize", irq); + stm32_dumpnvic("prioritize", irq); return OK; } #endif diff --git a/arch/arm/src/stm32l4/stm32l4_iwdg.c b/arch/arm/src/stm32l4/stm32l4_iwdg.c index 2c0894c78bee7..13df82a38ae22 100644 --- a/arch/arm/src/stm32l4/stm32l4_iwdg.c +++ b/arch/arm/src/stm32l4/stm32l4_iwdg.c @@ -42,7 +42,7 @@ #include "stm32l4_dbgmcu.h" #include "stm32l4_wdg.h" -#if defined(CONFIG_WATCHDOG) && defined(CONFIG_STM32L4_IWDG) +#if defined(CONFIG_WATCHDOG) && defined(CONFIG_STM32_IWDG) /**************************************************************************** * Pre-processor Definitions @@ -65,17 +65,17 @@ * 1000 * 4095 / Fmin = 34,944 MSec */ -#define IWDG_FMIN (STM32L4_LSI_FREQUENCY / 256) +#define IWDG_FMIN (STM32_LSI_FREQUENCY / 256) #define IWDG_MAXTIMEOUT (1000 * IWDG_RLR_MAX / IWDG_FMIN) /* Configuration ************************************************************/ -#ifndef CONFIG_STM32L4_IWDG_DEFTIMOUT -# define CONFIG_STM32L4_IWDG_DEFTIMOUT IWDG_MAXTIMEOUT +#ifndef CONFIG_STM32_IWDG_DEFTIMOUT +# define CONFIG_STM32_IWDG_DEFTIMOUT IWDG_MAXTIMEOUT #endif #ifndef CONFIG_DEBUG_WATCHDOG_INFO -# undef CONFIG_STM32L4_IWDG_REGDEBUG +# undef CONFIG_STM32_IWDG_REGDEBUG #endif /**************************************************************************** @@ -87,7 +87,7 @@ * well-known watchdog_lowerhalf_s structure. */ -struct stm32l4_lowerhalf_s +struct stm32_lowerhalf_s { const struct watchdog_ops_s *ops; /* Lower half operations */ uint32_t lsifreq; /* The calibrated frequency of the LSI oscillator */ @@ -104,25 +104,25 @@ struct stm32l4_lowerhalf_s /* Register operations ******************************************************/ -#ifdef CONFIG_STM32L4_IWDG_REGDEBUG -static uint16_t stm32l4_getreg(uint32_t addr); -static void stm32l4_putreg(uint16_t val, uint32_t addr); +#ifdef CONFIG_STM32_IWDG_REGDEBUG +static uint16_t stm32_getreg(uint32_t addr); +static void stm32_putreg(uint16_t val, uint32_t addr); #else -# define stm32l4_getreg(addr) getreg16(addr) -# define stm32l4_putreg(val,addr) putreg16(val,addr) +# define stm32_getreg(addr) getreg16(addr) +# define stm32_putreg(val,addr) putreg16(val,addr) #endif static inline void -stm32l4_setprescaler(struct stm32l4_lowerhalf_s *priv); +stm32_setprescaler(struct stm32_lowerhalf_s *priv); /* "Lower half" driver methods **********************************************/ -static int stm32l4_start(struct watchdog_lowerhalf_s *lower); -static int stm32l4_stop(struct watchdog_lowerhalf_s *lower); -static int stm32l4_keepalive(struct watchdog_lowerhalf_s *lower); -static int stm32l4_getstatus(struct watchdog_lowerhalf_s *lower, +static int stm32_start(struct watchdog_lowerhalf_s *lower); +static int stm32_stop(struct watchdog_lowerhalf_s *lower); +static int stm32_keepalive(struct watchdog_lowerhalf_s *lower); +static int stm32_getstatus(struct watchdog_lowerhalf_s *lower, struct watchdog_status_s *status); -static int stm32l4_settimeout(struct watchdog_lowerhalf_s *lower, +static int stm32_settimeout(struct watchdog_lowerhalf_s *lower, uint32_t timeout); /**************************************************************************** @@ -133,33 +133,33 @@ static int stm32l4_settimeout(struct watchdog_lowerhalf_s *lower, static const struct watchdog_ops_s g_wdgops = { - .start = stm32l4_start, - .stop = stm32l4_stop, - .keepalive = stm32l4_keepalive, - .getstatus = stm32l4_getstatus, - .settimeout = stm32l4_settimeout, + .start = stm32_start, + .stop = stm32_stop, + .keepalive = stm32_keepalive, + .getstatus = stm32_getstatus, + .settimeout = stm32_settimeout, .capture = NULL, .ioctl = NULL, }; /* "Lower half" driver state */ -static struct stm32l4_lowerhalf_s g_wdgdev; +static struct stm32_lowerhalf_s g_wdgdev; /**************************************************************************** * Private Functions ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_getreg + * Name: stm32_getreg * * Description: * Get the contents of an STM32 IWDG register * ****************************************************************************/ -#ifdef CONFIG_STM32L4_IWDG_REGDEBUG -static uint16_t stm32l4_getreg(uint32_t addr) +#ifdef CONFIG_STM32_IWDG_REGDEBUG +static uint16_t stm32_getreg(uint32_t addr) { static uint32_t prevaddr = 0; static uint32_t count = 0; @@ -214,15 +214,15 @@ static uint16_t stm32l4_getreg(uint32_t addr) #endif /**************************************************************************** - * Name: stm32l4_putreg + * Name: stm32_putreg * * Description: * Set the contents of an STM32 register to a value * ****************************************************************************/ -#ifdef CONFIG_STM32L4_IWDG_REGDEBUG -static void stm32l4_putreg(uint16_t val, uint32_t addr) +#ifdef CONFIG_STM32_IWDG_REGDEBUG +static void stm32_putreg(uint16_t val, uint32_t addr) { /* Show the register value being written */ @@ -235,7 +235,7 @@ static void stm32l4_putreg(uint16_t val, uint32_t addr) #endif /**************************************************************************** - * Name: stm32l4_setprescaler + * Name: stm32_setprescaler * * Description: * Set up the prescaler and reload values. @@ -246,7 +246,7 @@ static void stm32l4_putreg(uint16_t val, uint32_t addr) * ****************************************************************************/ -static inline void stm32l4_setprescaler(struct stm32l4_lowerhalf_s *priv) +static inline void stm32_setprescaler(struct stm32_lowerhalf_s *priv) { irqstate_t flags; @@ -254,26 +254,26 @@ static inline void stm32l4_setprescaler(struct stm32l4_lowerhalf_s *priv) /* Enable write access to IWDG_PR and IWDG_RLR registers */ - stm32l4_putreg(IWDG_KR_KEY_ENABLE, STM32L4_IWDG_KR); + stm32_putreg(IWDG_KR_KEY_ENABLE, STM32_IWDG_KR); /* Wait for the PVU and RVU bits to be reset by hardware. These bits * were set the last time that the PR register was written and may not * yet be cleared. */ - while (stm32l4_getreg(STM32L4_IWDG_SR) & (IWDG_SR_PVU | IWDG_SR_RVU)); + while (stm32_getreg(STM32_IWDG_SR) & (IWDG_SR_PVU | IWDG_SR_RVU)); /* Set the prescaler */ - stm32l4_putreg(priv->prescaler << IWDG_PR_SHIFT, STM32L4_IWDG_PR); + stm32_putreg(priv->prescaler << IWDG_PR_SHIFT, STM32_IWDG_PR); /* Set the reload value */ - stm32l4_putreg((uint16_t)priv->reload, STM32L4_IWDG_RLR); + stm32_putreg((uint16_t)priv->reload, STM32_IWDG_RLR); /* Reload the counter (and disable write access) */ - stm32l4_putreg(IWDG_KR_KEY_RELOAD, STM32L4_IWDG_KR); + stm32_putreg(IWDG_KR_KEY_RELOAD, STM32_IWDG_KR); /* Wait for the PVU and RVU bits to be reset by hardware. This is * to wait for the change to take effect before exiting critical section, @@ -289,14 +289,14 @@ static inline void stm32l4_setprescaler(struct stm32l4_lowerhalf_s *priv) if (priv->started) { - while (stm32l4_getreg(STM32L4_IWDG_SR) & (IWDG_SR_PVU | IWDG_SR_RVU)); + while (stm32_getreg(STM32_IWDG_SR) & (IWDG_SR_PVU | IWDG_SR_RVU)); } leave_critical_section(flags); } /**************************************************************************** - * Name: stm32l4_start + * Name: stm32_start * * Description: * Start the watchdog timer, resetting the time to the current timeout, @@ -310,10 +310,10 @@ static inline void stm32l4_setprescaler(struct stm32l4_lowerhalf_s *priv) * ****************************************************************************/ -static int stm32l4_start(struct watchdog_lowerhalf_s *lower) +static int stm32_start(struct watchdog_lowerhalf_s *lower) { - struct stm32l4_lowerhalf_s *priv = - (struct stm32l4_lowerhalf_s *)lower; + struct stm32_lowerhalf_s *priv = + (struct stm32_lowerhalf_s *)lower; irqstate_t flags; wdinfo("Entry: started\n"); @@ -327,7 +327,7 @@ static int stm32l4_start(struct watchdog_lowerhalf_s *lower) * starting the watchdog timer. */ - stm32l4_setprescaler(priv); + stm32_setprescaler(priv); /* Enable IWDG (the LSI oscillator will be enabled by hardware). NOTE: * If the "Hardware watchdog" feature is enabled through the device @@ -335,7 +335,7 @@ static int stm32l4_start(struct watchdog_lowerhalf_s *lower) */ flags = enter_critical_section(); - stm32l4_putreg(IWDG_KR_KEY_START, STM32L4_IWDG_KR); + stm32_putreg(IWDG_KR_KEY_START, STM32_IWDG_KR); priv->lastreset = clock_systime_ticks(); priv->started = true; leave_critical_section(flags); @@ -345,7 +345,7 @@ static int stm32l4_start(struct watchdog_lowerhalf_s *lower) } /**************************************************************************** - * Name: stm32l4_stop + * Name: stm32_stop * * Description: * Stop the watchdog timer @@ -359,7 +359,7 @@ static int stm32l4_start(struct watchdog_lowerhalf_s *lower) * ****************************************************************************/ -static int stm32l4_stop(struct watchdog_lowerhalf_s *lower) +static int stm32_stop(struct watchdog_lowerhalf_s *lower) { /* There is no way to disable the IDWG timer once it has been started */ @@ -368,7 +368,7 @@ static int stm32l4_stop(struct watchdog_lowerhalf_s *lower) } /**************************************************************************** - * Name: stm32l4_keepalive + * Name: stm32_keepalive * * Description: * Reset the watchdog timer to the current timeout value, prevent any @@ -384,10 +384,10 @@ static int stm32l4_stop(struct watchdog_lowerhalf_s *lower) * ****************************************************************************/ -static int stm32l4_keepalive(struct watchdog_lowerhalf_s *lower) +static int stm32_keepalive(struct watchdog_lowerhalf_s *lower) { - struct stm32l4_lowerhalf_s *priv = - (struct stm32l4_lowerhalf_s *)lower; + struct stm32_lowerhalf_s *priv = + (struct stm32_lowerhalf_s *)lower; irqstate_t flags; wdinfo("Entry\n"); @@ -395,7 +395,7 @@ static int stm32l4_keepalive(struct watchdog_lowerhalf_s *lower) /* Reload the IWDG timer */ flags = enter_critical_section(); - stm32l4_putreg(IWDG_KR_KEY_RELOAD, STM32L4_IWDG_KR); + stm32_putreg(IWDG_KR_KEY_RELOAD, STM32_IWDG_KR); priv->lastreset = clock_systime_ticks(); leave_critical_section(flags); @@ -403,7 +403,7 @@ static int stm32l4_keepalive(struct watchdog_lowerhalf_s *lower) } /**************************************************************************** - * Name: stm32l4_getstatus + * Name: stm32_getstatus * * Description: * Get the current watchdog timer status @@ -418,11 +418,11 @@ static int stm32l4_keepalive(struct watchdog_lowerhalf_s *lower) * ****************************************************************************/ -static int stm32l4_getstatus(struct watchdog_lowerhalf_s *lower, +static int stm32_getstatus(struct watchdog_lowerhalf_s *lower, struct watchdog_status_s *status) { - struct stm32l4_lowerhalf_s *priv = - (struct stm32l4_lowerhalf_s *)lower; + struct stm32_lowerhalf_s *priv = + (struct stm32_lowerhalf_s *)lower; uint32_t ticks; uint32_t elapsed; @@ -463,7 +463,7 @@ static int stm32l4_getstatus(struct watchdog_lowerhalf_s *lower, } /**************************************************************************** - * Name: stm32l4_settimeout + * Name: stm32_settimeout * * Description: * Set a new timeout value (and reset the watchdog timer) @@ -478,11 +478,11 @@ static int stm32l4_getstatus(struct watchdog_lowerhalf_s *lower, * ****************************************************************************/ -static int stm32l4_settimeout(struct watchdog_lowerhalf_s *lower, +static int stm32_settimeout(struct watchdog_lowerhalf_s *lower, uint32_t timeout) { - struct stm32l4_lowerhalf_s *priv = - (struct stm32l4_lowerhalf_s *)lower; + struct stm32_lowerhalf_s *priv = + (struct stm32_lowerhalf_s *)lower; uint32_t fiwdg; uint64_t reload; int prescaler; @@ -574,7 +574,7 @@ static int stm32l4_settimeout(struct watchdog_lowerhalf_s *lower, if (priv->started) { - stm32l4_setprescaler(priv); + stm32_setprescaler(priv); } wdinfo("prescaler=%d fiwdg=%" PRId32 " reload=%" PRId64 "\n", @@ -588,7 +588,7 @@ static int stm32l4_settimeout(struct watchdog_lowerhalf_s *lower, ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_iwdginitialize + * Name: stm32_iwdginitialize * * Description: * Initialize the IWDG watchdog timer. The watchdog timer is initialized @@ -605,9 +605,9 @@ static int stm32l4_settimeout(struct watchdog_lowerhalf_s *lower, * ****************************************************************************/ -void stm32l4_iwdginitialize(const char *devpath, uint32_t lsifreq) +void stm32_iwdginitialize(const char *devpath, uint32_t lsifreq) { - struct stm32l4_lowerhalf_s *priv = &g_wdgdev; + struct stm32_lowerhalf_s *priv = &g_wdgdev; wdinfo("Entry: devpath=%s lsifreq=%" PRId32 "\n", devpath, lsifreq); @@ -628,16 +628,16 @@ void stm32l4_iwdginitialize(const char *devpath, uint32_t lsifreq) * LSI controls outside of this file. */ - stm32l4_rcc_enablelsi(); - wdinfo("RCC CSR: %08" PRIx32 "\n", getreg32(STM32L4_RCC_CSR)); + stm32_rcc_enablelsi(); + wdinfo("RCC CSR: %08" PRIx32 "\n", getreg32(STM32_RCC_CSR)); /* Select an arbitrary initial timeout value. But don't start the watchdog * yet. NOTE: If the "Hardware watchdog" feature is enabled through the * device option bits, the watchdog is automatically enabled at power-on. */ - stm32l4_settimeout((struct watchdog_lowerhalf_s *)priv, - CONFIG_STM32L4_IWDG_DEFTIMOUT); + stm32_settimeout((struct watchdog_lowerhalf_s *)priv, + CONFIG_STM32_IWDG_DEFTIMOUT); /* Register the watchdog driver as /dev/watchdog0 */ @@ -648,9 +648,9 @@ void stm32l4_iwdginitialize(const char *devpath, uint32_t lsifreq) * on DBG_IWDG_STOP configuration bit in DBG module. */ -#if defined(CONFIG_STM32L4_JTAG_FULL_ENABLE) || \ - defined(CONFIG_STM32L4_JTAG_NOJNTRST_ENABLE) || \ - defined(CONFIG_STM32L4_JTAG_SW_ENABLE) +#if defined(CONFIG_STM32_JTAG_FULL_ENABLE) || \ + defined(CONFIG_STM32_JTAG_NOJNTRST_ENABLE) || \ + defined(CONFIG_STM32_JTAG_SW_ENABLE) { uint32_t cr; @@ -661,4 +661,4 @@ void stm32l4_iwdginitialize(const char *devpath, uint32_t lsifreq) #endif } -#endif /* CONFIG_WATCHDOG && CONFIG_STM32L4_IWDG */ +#endif /* CONFIG_WATCHDOG && CONFIG_STM32_IWDG */ diff --git a/arch/arm/src/stm32l4/stm32l4_lowputc.c b/arch/arm/src/stm32l4/stm32l4_lowputc.c index 56a8fc0391182..d94d25eacc5bc 100644 --- a/arch/arm/src/stm32l4/stm32l4_lowputc.c +++ b/arch/arm/src/stm32l4/stm32l4_lowputc.c @@ -33,7 +33,7 @@ #include "arm_internal.h" #include "chip.h" -#include "stm32l4.h" +#include "stm32.h" #include "stm32l4_rcc.h" #include "stm32l4_gpio.h" #include "stm32l4_uart.h" @@ -46,127 +46,127 @@ #ifdef HAVE_CONSOLE # if defined(CONFIG_LPUART1_SERIAL_CONSOLE) -# define STM32L4_CONSOLE_BASE STM32L4_LPUART1_BASE -# define STM32L4_APBCLOCK STM32L4_PCLK1_FREQUENCY -# define STM32L4_CONSOLE_APBREG STM32L4_RCC_APB1ENR2 -# define STM32L4_CONSOLE_APBEN RCC_APB1ENR2_LPUART1EN -# define STM32L4_CONSOLE_BAUD CONFIG_LPUART1_BAUD -# define STM32L4_CONSOLE_BITS CONFIG_LPUART1_BITS -# define STM32L4_CONSOLE_PARITY CONFIG_LPUART1_PARITY -# define STM32L4_CONSOLE_2STOP CONFIG_LPUART1_2STOP -# define STM32L4_CONSOLE_TX GPIO_LPUART1_TX -# define STM32L4_CONSOLE_RX GPIO_LPUART1_RX +# define STM32_CONSOLE_BASE STM32_LPUART1_BASE +# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY +# define STM32_CONSOLE_APBREG STM32_RCC_APB1ENR2 +# define STM32_CONSOLE_APBEN RCC_APB1ENR2_LPUART1EN +# define STM32_CONSOLE_BAUD CONFIG_LPUART1_BAUD +# define STM32_CONSOLE_BITS CONFIG_LPUART1_BITS +# define STM32_CONSOLE_PARITY CONFIG_LPUART1_PARITY +# define STM32_CONSOLE_2STOP CONFIG_LPUART1_2STOP +# define STM32_CONSOLE_TX GPIO_LPUART1_TX +# define STM32_CONSOLE_RX GPIO_LPUART1_RX # ifdef CONFIG_LPUART1_RS485 -# define STM32L4_CONSOLE_RS485_DIR GPIO_LPUART1_RS485_DIR +# define STM32_CONSOLE_RS485_DIR GPIO_LPUART1_RS485_DIR # if (CONFIG_LPUART1_RS485_DIR_POLARITY == 0) -# define STM32L4_CONSOLE_RS485_DIR_POLARITY false +# define STM32_CONSOLE_RS485_DIR_POLARITY false # else -# define STM32L4_CONSOLE_RS485_DIR_POLARITY true +# define STM32_CONSOLE_RS485_DIR_POLARITY true # endif # endif # elif defined(CONFIG_USART1_SERIAL_CONSOLE) -# define STM32L4_CONSOLE_BASE STM32L4_USART1_BASE -# define STM32L4_APBCLOCK STM32L4_PCLK2_FREQUENCY -# define STM32L4_CONSOLE_APBREG STM32L4_RCC_APB2ENR -# define STM32L4_CONSOLE_APBEN RCC_APB2ENR_USART1EN -# define STM32L4_CONSOLE_BAUD CONFIG_USART1_BAUD -# define STM32L4_CONSOLE_BITS CONFIG_USART1_BITS -# define STM32L4_CONSOLE_PARITY CONFIG_USART1_PARITY -# define STM32L4_CONSOLE_2STOP CONFIG_USART1_2STOP -# define STM32L4_CONSOLE_TX GPIO_USART1_TX -# define STM32L4_CONSOLE_RX GPIO_USART1_RX +# define STM32_CONSOLE_BASE STM32_USART1_BASE +# define STM32_APBCLOCK STM32_PCLK2_FREQUENCY +# define STM32_CONSOLE_APBREG STM32_RCC_APB2ENR +# define STM32_CONSOLE_APBEN RCC_APB2ENR_USART1EN +# define STM32_CONSOLE_BAUD CONFIG_USART1_BAUD +# define STM32_CONSOLE_BITS CONFIG_USART1_BITS +# define STM32_CONSOLE_PARITY CONFIG_USART1_PARITY +# define STM32_CONSOLE_2STOP CONFIG_USART1_2STOP +# define STM32_CONSOLE_TX GPIO_USART1_TX +# define STM32_CONSOLE_RX GPIO_USART1_RX # ifdef CONFIG_USART1_RS485 -# define STM32L4_CONSOLE_RS485_DIR GPIO_USART1_RS485_DIR +# define STM32_CONSOLE_RS485_DIR GPIO_USART1_RS485_DIR # if (CONFIG_USART1_RS485_DIR_POLARITY == 0) -# define STM32L4_CONSOLE_RS485_DIR_POLARITY false +# define STM32_CONSOLE_RS485_DIR_POLARITY false # else -# define STM32L4_CONSOLE_RS485_DIR_POLARITY true +# define STM32_CONSOLE_RS485_DIR_POLARITY true # endif # endif # elif defined(CONFIG_USART2_SERIAL_CONSOLE) -# define STM32L4_CONSOLE_BASE STM32L4_USART2_BASE -# define STM32L4_APBCLOCK STM32L4_PCLK1_FREQUENCY -# define STM32L4_CONSOLE_APBREG STM32L4_RCC_APB1ENR1 -# define STM32L4_CONSOLE_APBEN RCC_APB1ENR1_USART2EN -# define STM32L4_CONSOLE_BAUD CONFIG_USART2_BAUD -# define STM32L4_CONSOLE_BITS CONFIG_USART2_BITS -# define STM32L4_CONSOLE_PARITY CONFIG_USART2_PARITY -# define STM32L4_CONSOLE_2STOP CONFIG_USART2_2STOP -# define STM32L4_CONSOLE_TX GPIO_USART2_TX -# define STM32L4_CONSOLE_RX GPIO_USART2_RX +# define STM32_CONSOLE_BASE STM32_USART2_BASE +# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY +# define STM32_CONSOLE_APBREG STM32_RCC_APB1ENR1 +# define STM32_CONSOLE_APBEN RCC_APB1ENR1_USART2EN +# define STM32_CONSOLE_BAUD CONFIG_USART2_BAUD +# define STM32_CONSOLE_BITS CONFIG_USART2_BITS +# define STM32_CONSOLE_PARITY CONFIG_USART2_PARITY +# define STM32_CONSOLE_2STOP CONFIG_USART2_2STOP +# define STM32_CONSOLE_TX GPIO_USART2_TX +# define STM32_CONSOLE_RX GPIO_USART2_RX # ifdef CONFIG_USART2_RS485 -# define STM32L4_CONSOLE_RS485_DIR GPIO_USART2_RS485_DIR +# define STM32_CONSOLE_RS485_DIR GPIO_USART2_RS485_DIR # if (CONFIG_USART2_RS485_DIR_POLARITY == 0) -# define STM32L4_CONSOLE_RS485_DIR_POLARITY false +# define STM32_CONSOLE_RS485_DIR_POLARITY false # else -# define STM32L4_CONSOLE_RS485_DIR_POLARITY true +# define STM32_CONSOLE_RS485_DIR_POLARITY true # endif # endif # elif defined(CONFIG_USART3_SERIAL_CONSOLE) -# define STM32L4_CONSOLE_BASE STM32L4_USART3_BASE -# define STM32L4_APBCLOCK STM32L4_PCLK1_FREQUENCY -# define STM32L4_CONSOLE_APBREG STM32L4_RCC_APB1ENR1 -# define STM32L4_CONSOLE_APBEN RCC_APB1ENR1_USART3EN -# define STM32L4_CONSOLE_BAUD CONFIG_USART3_BAUD -# define STM32L4_CONSOLE_BITS CONFIG_USART3_BITS -# define STM32L4_CONSOLE_PARITY CONFIG_USART3_PARITY -# define STM32L4_CONSOLE_2STOP CONFIG_USART3_2STOP -# define STM32L4_CONSOLE_TX GPIO_USART3_TX -# define STM32L4_CONSOLE_RX GPIO_USART3_RX +# define STM32_CONSOLE_BASE STM32_USART3_BASE +# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY +# define STM32_CONSOLE_APBREG STM32_RCC_APB1ENR1 +# define STM32_CONSOLE_APBEN RCC_APB1ENR1_USART3EN +# define STM32_CONSOLE_BAUD CONFIG_USART3_BAUD +# define STM32_CONSOLE_BITS CONFIG_USART3_BITS +# define STM32_CONSOLE_PARITY CONFIG_USART3_PARITY +# define STM32_CONSOLE_2STOP CONFIG_USART3_2STOP +# define STM32_CONSOLE_TX GPIO_USART3_TX +# define STM32_CONSOLE_RX GPIO_USART3_RX # ifdef CONFIG_USART3_RS485 -# define STM32L4_CONSOLE_RS485_DIR GPIO_USART3_RS485_DIR +# define STM32_CONSOLE_RS485_DIR GPIO_USART3_RS485_DIR # if (CONFIG_USART3_RS485_DIR_POLARITY == 0) -# define STM32L4_CONSOLE_RS485_DIR_POLARITY false +# define STM32_CONSOLE_RS485_DIR_POLARITY false # else -# define STM32L4_CONSOLE_RS485_DIR_POLARITY true +# define STM32_CONSOLE_RS485_DIR_POLARITY true # endif # endif # elif defined(CONFIG_UART4_SERIAL_CONSOLE) -# define STM32L4_CONSOLE_BASE STM32L4_UART4_BASE -# define STM32L4_APBCLOCK STM32L4_PCLK1_FREQUENCY -# define STM32L4_CONSOLE_APBREG STM32L4_RCC_APB1ENR1 -# define STM32L4_CONSOLE_APBEN RCC_APB1ENR1_UART4EN -# define STM32L4_CONSOLE_BAUD CONFIG_UART4_BAUD -# define STM32L4_CONSOLE_BITS CONFIG_UART4_BITS -# define STM32L4_CONSOLE_PARITY CONFIG_UART4_PARITY -# define STM32L4_CONSOLE_2STOP CONFIG_UART4_2STOP -# define STM32L4_CONSOLE_TX GPIO_UART4_TX -# define STM32L4_CONSOLE_RX GPIO_UART4_RX +# define STM32_CONSOLE_BASE STM32_UART4_BASE +# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY +# define STM32_CONSOLE_APBREG STM32_RCC_APB1ENR1 +# define STM32_CONSOLE_APBEN RCC_APB1ENR1_UART4EN +# define STM32_CONSOLE_BAUD CONFIG_UART4_BAUD +# define STM32_CONSOLE_BITS CONFIG_UART4_BITS +# define STM32_CONSOLE_PARITY CONFIG_UART4_PARITY +# define STM32_CONSOLE_2STOP CONFIG_UART4_2STOP +# define STM32_CONSOLE_TX GPIO_UART4_TX +# define STM32_CONSOLE_RX GPIO_UART4_RX # ifdef CONFIG_UART4_RS485 -# define STM32L4_CONSOLE_RS485_DIR GPIO_UART4_RS485_DIR +# define STM32_CONSOLE_RS485_DIR GPIO_UART4_RS485_DIR # if (CONFIG_UART4_RS485_DIR_POLARITY == 0) -# define STM32L4_CONSOLE_RS485_DIR_POLARITY false +# define STM32_CONSOLE_RS485_DIR_POLARITY false # else -# define STM32L4_CONSOLE_RS485_DIR_POLARITY true +# define STM32_CONSOLE_RS485_DIR_POLARITY true # endif # endif # elif defined(CONFIG_UART5_SERIAL_CONSOLE) -# define STM32L4_CONSOLE_BASE STM32L4_UART5_BASE -# define STM32L4_APBCLOCK STM32L4_PCLK1_FREQUENCY -# define STM32L4_CONSOLE_APBREG STM32L4_RCC_APB1ENR1 -# define STM32L4_CONSOLE_APBEN RCC_APB1ENR1_UART5EN -# define STM32L4_CONSOLE_BAUD CONFIG_UART5_BAUD -# define STM32L4_CONSOLE_BITS CONFIG_UART5_BITS -# define STM32L4_CONSOLE_PARITY CONFIG_UART5_PARITY -# define STM32L4_CONSOLE_2STOP CONFIG_UART5_2STOP -# define STM32L4_CONSOLE_TX GPIO_UART5_TX -# define STM32L4_CONSOLE_RX GPIO_UART5_RX +# define STM32_CONSOLE_BASE STM32_UART5_BASE +# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY +# define STM32_CONSOLE_APBREG STM32_RCC_APB1ENR1 +# define STM32_CONSOLE_APBEN RCC_APB1ENR1_UART5EN +# define STM32_CONSOLE_BAUD CONFIG_UART5_BAUD +# define STM32_CONSOLE_BITS CONFIG_UART5_BITS +# define STM32_CONSOLE_PARITY CONFIG_UART5_PARITY +# define STM32_CONSOLE_2STOP CONFIG_UART5_2STOP +# define STM32_CONSOLE_TX GPIO_UART5_TX +# define STM32_CONSOLE_RX GPIO_UART5_RX # ifdef CONFIG_UART5_RS485 -# define STM32L4_CONSOLE_RS485_DIR GPIO_UART5_RS485_DIR +# define STM32_CONSOLE_RS485_DIR GPIO_UART5_RS485_DIR # if (CONFIG_UART5_RS485_DIR_POLARITY == 0) -# define STM32L4_CONSOLE_RS485_DIR_POLARITY false +# define STM32_CONSOLE_RS485_DIR_POLARITY false # else -# define STM32L4_CONSOLE_RS485_DIR_POLARITY true +# define STM32_CONSOLE_RS485_DIR_POLARITY true # endif # endif # endif /* CR1 settings */ -# if STM32L4_CONSOLE_BITS == 9 +# if STM32_CONSOLE_BITS == 9 # define USART_CR1_M0_VALUE USART_CR1_M0 # define USART_CR1_M1_VALUE 0 -# elif STM32L4_CONSOLE_BITS == 7 +# elif STM32_CONSOLE_BITS == 7 # define USART_CR1_M0_VALUE 0 # define USART_CR1_M1_VALUE USART_CR1_M1 # else /* 8 bits */ @@ -174,9 +174,9 @@ # define USART_CR1_M1_VALUE 0 # endif -# if STM32L4_CONSOLE_PARITY == 1 /* odd parity */ +# if STM32_CONSOLE_PARITY == 1 /* odd parity */ # define USART_CR1_PARITY_VALUE (USART_CR1_PCE|USART_CR1_PS) -# elif STM32L4_CONSOLE_PARITY == 2 /* even parity */ +# elif STM32_CONSOLE_PARITY == 2 /* even parity */ # define USART_CR1_PARITY_VALUE USART_CR1_PCE # else /* no parity */ # define USART_CR1_PARITY_VALUE 0 @@ -192,7 +192,7 @@ /* CR2 settings */ -# if STM32L4_CONSOLE_2STOP != 0 +# if STM32_CONSOLE_2STOP != 0 # define USART_CR2_STOP2_VALUE USART_CR2_STOP2 # else # define USART_CR2_STOP2_VALUE 0 @@ -234,19 +234,19 @@ * UARTDIV = 2 * fCK / baud */ -# define STM32L4_USARTDIV8 \ - (((STM32L4_APBCLOCK << 1) + (STM32L4_CONSOLE_BAUD >> 1)) / STM32L4_CONSOLE_BAUD) -# define STM32L4_USARTDIV16 \ - ((STM32L4_APBCLOCK + (STM32L4_CONSOLE_BAUD >> 1)) / STM32L4_CONSOLE_BAUD) +# define STM32_USARTDIV8 \ + (((STM32_APBCLOCK << 1) + (STM32_CONSOLE_BAUD >> 1)) / STM32_CONSOLE_BAUD) +# define STM32_USARTDIV16 \ + ((STM32_APBCLOCK + (STM32_CONSOLE_BAUD >> 1)) / STM32_CONSOLE_BAUD) /* Use oversamply by 8 only if the divisor is small. But what is small? */ -# if STM32L4_USARTDIV8 > 100 -# define STM32L4_BRR_VALUE STM32L4_USARTDIV16 +# if STM32_USARTDIV8 > 100 +# define STM32_BRR_VALUE STM32_USARTDIV16 # else # define USE_OVER8 1 -# define STM32L4_BRR_VALUE \ - ((STM32L4_USARTDIV8 & 0xfff0) | ((STM32L4_USARTDIV8 & 0x000f) >> 1)) +# define STM32_BRR_VALUE \ + ((STM32_USARTDIV8 & 0xfff0) | ((STM32_USARTDIV8 & 0x000f) >> 1)) # endif #endif /* HAVE_CONSOLE */ @@ -288,29 +288,29 @@ void arm_lowputc(char ch) #ifdef HAVE_CONSOLE /* Wait until the TX data register is empty */ - while ((getreg32(STM32L4_CONSOLE_BASE + STM32L4_USART_ISR_OFFSET) & + while ((getreg32(STM32_CONSOLE_BASE + STM32_USART_ISR_OFFSET) & USART_ISR_TXE) == 0); -#ifdef STM32L4_CONSOLE_RS485_DIR - stm32l4_gpiowrite(STM32L4_CONSOLE_RS485_DIR, - STM32L4_CONSOLE_RS485_DIR_POLARITY); +#ifdef STM32_CONSOLE_RS485_DIR + stm32_gpiowrite(STM32_CONSOLE_RS485_DIR, + STM32_CONSOLE_RS485_DIR_POLARITY); #endif /* Then send the character */ - putreg32((uint32_t)ch, STM32L4_CONSOLE_BASE + STM32L4_USART_TDR_OFFSET); + putreg32((uint32_t)ch, STM32_CONSOLE_BASE + STM32_USART_TDR_OFFSET); -#ifdef STM32L4_CONSOLE_RS485_DIR - while ((getreg32(STM32L4_CONSOLE_BASE + STM32L4_USART_ISR_OFFSET) & +#ifdef STM32_CONSOLE_RS485_DIR + while ((getreg32(STM32_CONSOLE_BASE + STM32_USART_ISR_OFFSET) & USART_ISR_TC) == 0); - stm32l4_gpiowrite(STM32L4_CONSOLE_RS485_DIR, - !STM32L4_CONSOLE_RS485_DIR_POLARITY); + stm32_gpiowrite(STM32_CONSOLE_RS485_DIR, + !STM32_CONSOLE_RS485_DIR_POLARITY); #endif #endif /* HAVE_CONSOLE */ } /**************************************************************************** - * Name: stm32l4_lowsetup + * Name: stm32_lowsetup * * Description: * This performs basic initialization of the USART used for the serial @@ -319,7 +319,7 @@ void arm_lowputc(char ch) * ****************************************************************************/ -void stm32l4_lowsetup(void) +void stm32_lowsetup(void) { #if defined(HAVE_UART) #if defined(HAVE_CONSOLE) && !defined(CONFIG_SUPPRESS_UART_CONFIG) @@ -329,26 +329,26 @@ void stm32l4_lowsetup(void) #if defined(HAVE_CONSOLE) /* Enable USART APB1/2 clock */ - modifyreg32(STM32L4_CONSOLE_APBREG, 0, STM32L4_CONSOLE_APBEN); + modifyreg32(STM32_CONSOLE_APBREG, 0, STM32_CONSOLE_APBEN); #endif /* Enable the console USART and configure GPIO pins needed for rx/tx. * * NOTE: Clocking for selected U[S]ARTs was already provided in - * stm32l4_rcc.c + * stm32_rcc.c */ -#ifdef STM32L4_CONSOLE_TX - stm32l4_configgpio(STM32L4_CONSOLE_TX); +#ifdef STM32_CONSOLE_TX + stm32_configgpio(STM32_CONSOLE_TX); #endif -#ifdef STM32L4_CONSOLE_RX - stm32l4_configgpio(STM32L4_CONSOLE_RX); +#ifdef STM32_CONSOLE_RX + stm32_configgpio(STM32_CONSOLE_RX); #endif -#ifdef STM32L4_CONSOLE_RS485_DIR - stm32l4_configgpio(STM32L4_CONSOLE_RS485_DIR); - stm32l4_gpiowrite(STM32L4_CONSOLE_RS485_DIR, - !STM32L4_CONSOLE_RS485_DIR_POLARITY); +#ifdef STM32_CONSOLE_RS485_DIR + stm32_configgpio(STM32_CONSOLE_RS485_DIR); + stm32_gpiowrite(STM32_CONSOLE_RS485_DIR, + !STM32_CONSOLE_RS485_DIR_POLARITY); #endif /* Enable and configure the selected console device */ @@ -356,42 +356,42 @@ void stm32l4_lowsetup(void) #if defined(HAVE_CONSOLE) && !defined(CONFIG_SUPPRESS_UART_CONFIG) /* Configure CR2 */ - cr = getreg32(STM32L4_CONSOLE_BASE + STM32L4_USART_CR2_OFFSET); + cr = getreg32(STM32_CONSOLE_BASE + STM32_USART_CR2_OFFSET); cr &= ~USART_CR2_CLRBITS; cr |= USART_CR2_SETBITS; - putreg32(cr, STM32L4_CONSOLE_BASE + STM32L4_USART_CR2_OFFSET); + putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR2_OFFSET); /* Configure CR1 */ - cr = getreg32(STM32L4_CONSOLE_BASE + STM32L4_USART_CR1_OFFSET); + cr = getreg32(STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET); cr &= ~USART_CR1_CLRBITS; cr |= USART_CR1_SETBITS; - putreg32(cr, STM32L4_CONSOLE_BASE + STM32L4_USART_CR1_OFFSET); + putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET); /* Configure CR3 */ - cr = getreg32(STM32L4_CONSOLE_BASE + STM32L4_USART_CR3_OFFSET); + cr = getreg32(STM32_CONSOLE_BASE + STM32_USART_CR3_OFFSET); cr &= ~USART_CR3_CLRBITS; cr |= USART_CR3_SETBITS; - putreg32(cr, STM32L4_CONSOLE_BASE + STM32L4_USART_CR3_OFFSET); + putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR3_OFFSET); /* Configure the USART Baud Rate */ - putreg32(STM32L4_BRR_VALUE, - STM32L4_CONSOLE_BASE + STM32L4_USART_BRR_OFFSET); + putreg32(STM32_BRR_VALUE, + STM32_CONSOLE_BASE + STM32_USART_BRR_OFFSET); /* Select oversampling by 8 */ - cr = getreg32(STM32L4_CONSOLE_BASE + STM32L4_USART_CR1_OFFSET); + cr = getreg32(STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET); #ifdef USE_OVER8 cr |= USART_CR1_OVER8; - putreg32(cr, STM32L4_CONSOLE_BASE + STM32L4_USART_CR1_OFFSET); + putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET); #endif /* Enable Rx, Tx, and the USART */ cr |= (USART_CR1_UE | USART_CR1_TE | USART_CR1_RE); - putreg32(cr, STM32L4_CONSOLE_BASE + STM32L4_USART_CR1_OFFSET); + putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET); #endif /* HAVE_CONSOLE && !CONFIG_SUPPRESS_UART_CONFIG */ #endif /* HAVE_UART */ diff --git a/arch/arm/src/stm32l4/stm32l4_lowputc.h b/arch/arm/src/stm32l4/stm32l4_lowputc.h index b28b6d975794e..511fc227a5cf8 100644 --- a/arch/arm/src/stm32l4/stm32l4_lowputc.h +++ b/arch/arm/src/stm32l4/stm32l4_lowputc.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32L4_STM32L4_LOWPUTC_H -#define __ARCH_ARM_SRC_STM32L4_STM32L4_LOWPUTC_H +#ifndef __ARCH_ARM_SRC_STM32L4_STM32_LOWPUTC_H +#define __ARCH_ARM_SRC_STM32L4_STM32_LOWPUTC_H /**************************************************************************** * Included Files @@ -47,7 +47,7 @@ extern "C" #endif /**************************************************************************** - * Name: stm32l4_lowsetup + * Name: stm32_lowsetup * * Description: * Called at the very beginning of _start. @@ -55,7 +55,7 @@ extern "C" * ****************************************************************************/ -void stm32l4_lowsetup(void); +void stm32_lowsetup(void); #undef EXTERN #if defined(__cplusplus) @@ -63,4 +63,4 @@ void stm32l4_lowsetup(void); #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32L4_STM32L4_LOWPUTC_H */ +#endif /* __ARCH_ARM_SRC_STM32L4_STM32_LOWPUTC_H */ diff --git a/arch/arm/src/stm32l4/stm32l4_lptim.c b/arch/arm/src/stm32l4/stm32l4_lptim.c index 0426016bd4464..9ce24f201a3de 100644 --- a/arch/arm/src/stm32l4/stm32l4_lptim.c +++ b/arch/arm/src/stm32l4/stm32l4_lptim.c @@ -79,12 +79,12 @@ #include -#include "stm32l4.h" +#include "stm32.h" #include "stm32l4_gpio.h" #include "stm32l4_lptim.h" #include "stm32l4_rcc.h" -#if defined(CONFIG_STM32L4_LPTIM1) || defined(CONFIG_STM32L4_LPTIM2) +#if defined(CONFIG_STM32_LPTIM1) || defined(CONFIG_STM32_LPTIM2) /**************************************************************************** * Private Types @@ -92,10 +92,10 @@ /* TIM Device Structure */ -struct stm32l4_lptim_priv_s +struct stm32_lptim_priv_s { - const struct stm32l4_lptim_ops_s *ops; - stm32l4_lptim_mode_t mode; + const struct stm32_lptim_ops_s *ops; + stm32_lptim_mode_t mode; uint32_t base; /* LPTIMn base address */ uint32_t freq; /* Clocking for the LPTIM module */ }; @@ -104,69 +104,69 @@ struct stm32l4_lptim_priv_s * Private Function Prototypes ****************************************************************************/ -static struct stm32l4_lptim_dev_s *stm32l4_lptim_getstruct(int timer); -static inline void stm32l4_modifyreg32(struct stm32l4_lptim_dev_s *dev, +static struct stm32_lptim_dev_s *stm32_lptim_getstruct(int timer); +static inline void stm32_modifyreg32(struct stm32_lptim_dev_s *dev, uint8_t offset, uint32_t clearbits, uint32_t setbits); -static int stm32l4_lptim_enable(struct stm32l4_lptim_dev_s *dev); -static int stm32l4_lptim_disable(struct stm32l4_lptim_dev_s *dev); -static int stm32l4_lptim_reset(struct stm32l4_lptim_dev_s *dev); -static int stm32l4_lptim_get_gpioconfig(struct stm32l4_lptim_dev_s *dev, - stm32l4_lptim_channel_t channel, +static int stm32_lptim_enable(struct stm32_lptim_dev_s *dev); +static int stm32_lptim_disable(struct stm32_lptim_dev_s *dev); +static int stm32_lptim_reset(struct stm32_lptim_dev_s *dev); +static int stm32_lptim_get_gpioconfig(struct stm32_lptim_dev_s *dev, + stm32_lptim_channel_t channel, uint32_t *cfg); -static int stm32l4_lptim_setmode(struct stm32l4_lptim_dev_s *dev, - stm32l4_lptim_mode_t mode); -static int stm32l4_lptim_setclock(struct stm32l4_lptim_dev_s *dev, +static int stm32_lptim_setmode(struct stm32_lptim_dev_s *dev, + stm32_lptim_mode_t mode); +static int stm32_lptim_setclock(struct stm32_lptim_dev_s *dev, uint32_t freq); -static int stm32l4_lptim_setchannel(struct stm32l4_lptim_dev_s *dev, - stm32l4_lptim_channel_t channel, +static int stm32_lptim_setchannel(struct stm32_lptim_dev_s *dev, + stm32_lptim_channel_t channel, int enable); -static int stm32l4_lptim_setclocksource(struct stm32l4_lptim_dev_s *dev, - stm32l4_lptim_clksrc_t clksrc); -static int stm32l4_lptim_setpolarity(struct stm32l4_lptim_dev_s *dev, - stm32l4_lptim_clkpol_t polarity); +static int stm32_lptim_setclocksource(struct stm32_lptim_dev_s *dev, + stm32_lptim_clksrc_t clksrc); +static int stm32_lptim_setpolarity(struct stm32_lptim_dev_s *dev, + stm32_lptim_clkpol_t polarity); static -uint32_t stm32l4_lptim_getcounter(struct stm32l4_lptim_dev_s *dev); -static int stm32l4_lptim_setcountmode(struct stm32l4_lptim_dev_s *dev, - stm32l4_lptim_cntmode_t cntmode); -static void stm32l4_lptim_setperiod(struct stm32l4_lptim_dev_s *dev, +uint32_t stm32_lptim_getcounter(struct stm32_lptim_dev_s *dev); +static int stm32_lptim_setcountmode(struct stm32_lptim_dev_s *dev, + stm32_lptim_cntmode_t cntmode); +static void stm32_lptim_setperiod(struct stm32_lptim_dev_s *dev, uint32_t period); -static uint32_t stm32l4_lptim_getperiod(struct stm32l4_lptim_dev_s *dev); +static uint32_t stm32_lptim_getperiod(struct stm32_lptim_dev_s *dev); /**************************************************************************** * Private Data ****************************************************************************/ -static const struct stm32l4_lptim_ops_s stm32l4_lptim_ops = +static const struct stm32_lptim_ops_s stm32_lptim_ops = { - .setmode = &stm32l4_lptim_setmode, - .setclock = &stm32l4_lptim_setclock, - .setchannel = &stm32l4_lptim_setchannel, - .setclocksource = &stm32l4_lptim_setclocksource, - .setpolarity = &stm32l4_lptim_setpolarity, - .getcounter = &stm32l4_lptim_getcounter, - .setcountmode = &stm32l4_lptim_setcountmode, - .setperiod = &stm32l4_lptim_setperiod, - .getperiod = &stm32l4_lptim_getperiod + .setmode = &stm32_lptim_setmode, + .setclock = &stm32_lptim_setclock, + .setchannel = &stm32_lptim_setchannel, + .setclocksource = &stm32_lptim_setclocksource, + .setpolarity = &stm32_lptim_setpolarity, + .getcounter = &stm32_lptim_getcounter, + .setcountmode = &stm32_lptim_setcountmode, + .setperiod = &stm32_lptim_setperiod, + .getperiod = &stm32_lptim_getperiod }; -#if defined(CONFIG_STM32L4_LPTIM1) -static struct stm32l4_lptim_priv_s stm32l4_lptim1_priv = +#if defined(CONFIG_STM32_LPTIM1) +static struct stm32_lptim_priv_s stm32_lptim1_priv = { - .ops = &stm32l4_lptim_ops, - .mode = STM32L4_LPTIM_MODE_UNUSED, - .base = STM32L4_LPTIM1_BASE, - .freq = STM32L4_LPTIM1_FREQUENCY, /* Must be defined in board.h */ + .ops = &stm32_lptim_ops, + .mode = STM32_LPTIM_MODE_UNUSED, + .base = STM32_LPTIM1_BASE, + .freq = STM32_LPTIM1_FREQUENCY, /* Must be defined in board.h */ }; #endif -#if defined(CONFIG_STM32L4_LPTIM2) -static struct stm32l4_lptim_priv_s stm32l4_lptim2_priv = +#if defined(CONFIG_STM32_LPTIM2) +static struct stm32_lptim_priv_s stm32_lptim2_priv = { - .ops = &stm32l4_lptim_ops, - .mode = STM32L4_LPTIM_MODE_UNUSED, - .base = STM32L4_LPTIM2_BASE, - .freq = STM32L4_LPTIM2_FREQUENCY, /* Must be defined in board.h */ + .ops = &stm32_lptim_ops, + .mode = STM32_LPTIM_MODE_UNUSED, + .base = STM32_LPTIM2_BASE, + .freq = STM32_LPTIM2_FREQUENCY, /* Must be defined in board.h */ }; #endif @@ -175,20 +175,20 @@ static struct stm32l4_lptim_priv_s stm32l4_lptim2_priv = ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_lptim_getstruct + * Name: stm32_lptim_getstruct ****************************************************************************/ -static struct stm32l4_lptim_dev_s *stm32l4_lptim_getstruct(int timer) +static struct stm32_lptim_dev_s *stm32_lptim_getstruct(int timer) { switch (timer) { -#if defined(CONFIG_STM32L4_LPTIM1) +#if defined(CONFIG_STM32_LPTIM1) case 1: - return (struct stm32l4_lptim_dev_s *)&stm32l4_lptim1_priv; + return (struct stm32_lptim_dev_s *)&stm32_lptim1_priv; #endif -#if defined(CONFIG_STM32L4_LPTIM2) +#if defined(CONFIG_STM32_LPTIM2) case 2: - return (struct stm32l4_lptim_dev_s *)&stm32l4_lptim2_priv; + return (struct stm32_lptim_dev_s *)&stm32_lptim2_priv; #endif default: return NULL; @@ -196,35 +196,35 @@ static struct stm32l4_lptim_dev_s *stm32l4_lptim_getstruct(int timer) } /**************************************************************************** - * Name: stm32l4_modifyreg32 + * Name: stm32_modifyreg32 ****************************************************************************/ -static inline void stm32l4_modifyreg32(struct stm32l4_lptim_dev_s *dev, +static inline void stm32_modifyreg32(struct stm32_lptim_dev_s *dev, uint8_t offset, uint32_t clearbits, uint32_t setbits) { - modifyreg32(((struct stm32l4_lptim_priv_s *)dev)->base + offset, + modifyreg32(((struct stm32_lptim_priv_s *)dev)->base + offset, clearbits, setbits); } /**************************************************************************** - * Name: stm32l4_lptim_enable + * Name: stm32_lptim_enable ****************************************************************************/ -static int stm32l4_lptim_enable(struct stm32l4_lptim_dev_s *dev) +static int stm32_lptim_enable(struct stm32_lptim_dev_s *dev) { DEBUGASSERT(dev != NULL); - switch (((struct stm32l4_lptim_priv_s *)dev)->base) + switch (((struct stm32_lptim_priv_s *)dev)->base) { -#if defined(CONFIG_STM32L4_LPTIM1) - case STM32L4_LPTIM1_BASE: - modifyreg32(STM32L4_RCC_APB1ENR1, 0, RCC_APB1ENR1_LPTIM1EN); +#if defined(CONFIG_STM32_LPTIM1) + case STM32_LPTIM1_BASE: + modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_LPTIM1EN); break; #endif -#if defined(CONFIG_STM32L4_LPTIM2) - case STM32L4_LPTIM2_BASE: - modifyreg32(STM32L4_RCC_APB1ENR2, 0, RCC_APB1ENR2_LPTIM2EN); +#if defined(CONFIG_STM32_LPTIM2) + case STM32_LPTIM2_BASE: + modifyreg32(STM32_RCC_APB1ENR2, 0, RCC_APB1ENR2_LPTIM2EN); break; #endif @@ -236,23 +236,23 @@ static int stm32l4_lptim_enable(struct stm32l4_lptim_dev_s *dev) } /**************************************************************************** - * Name: stm32l4_lptim_disable + * Name: stm32_lptim_disable ****************************************************************************/ -static int stm32l4_lptim_disable(struct stm32l4_lptim_dev_s *dev) +static int stm32_lptim_disable(struct stm32_lptim_dev_s *dev) { DEBUGASSERT(dev != NULL); - switch (((struct stm32l4_lptim_priv_s *)dev)->base) + switch (((struct stm32_lptim_priv_s *)dev)->base) { -#if defined(CONFIG_STM32L4_LPTIM1) - case STM32L4_LPTIM1_BASE: - modifyreg32(STM32L4_RCC_APB1ENR1, RCC_APB1ENR1_LPTIM1EN, 0); +#if defined(CONFIG_STM32_LPTIM1) + case STM32_LPTIM1_BASE: + modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_LPTIM1EN, 0); break; #endif -#if defined(CONFIG_STM32L4_LPTIM2) - case STM32L4_LPTIM2_BASE: - modifyreg32(STM32L4_RCC_APB1ENR2, RCC_APB1ENR2_LPTIM2EN, 0); +#if defined(CONFIG_STM32_LPTIM2) + case STM32_LPTIM2_BASE: + modifyreg32(STM32_RCC_APB1ENR2, RCC_APB1ENR2_LPTIM2EN, 0); break; #endif @@ -264,25 +264,25 @@ static int stm32l4_lptim_disable(struct stm32l4_lptim_dev_s *dev) } /**************************************************************************** - * Name: stm32l4_lptim_reset + * Name: stm32_lptim_reset ****************************************************************************/ -static int stm32l4_lptim_reset(struct stm32l4_lptim_dev_s *dev) +static int stm32_lptim_reset(struct stm32_lptim_dev_s *dev) { DEBUGASSERT(dev != NULL); - switch (((struct stm32l4_lptim_priv_s *)dev)->base) + switch (((struct stm32_lptim_priv_s *)dev)->base) { -#if defined(CONFIG_STM32L4_LPTIM1) - case STM32L4_LPTIM1_BASE: - modifyreg32(STM32L4_RCC_APB1RSTR1, 0, RCC_APB1RSTR1_LPTIM1RST); - modifyreg32(STM32L4_RCC_APB1RSTR1, RCC_APB1RSTR1_LPTIM1RST, 0); +#if defined(CONFIG_STM32_LPTIM1) + case STM32_LPTIM1_BASE: + modifyreg32(STM32_RCC_APB1RSTR1, 0, RCC_APB1RSTR1_LPTIM1RST); + modifyreg32(STM32_RCC_APB1RSTR1, RCC_APB1RSTR1_LPTIM1RST, 0); break; #endif -#if defined(CONFIG_STM32L4_LPTIM2) - case STM32L4_LPTIM2_BASE: - modifyreg32(STM32L4_RCC_APB1RSTR2, 0, RCC_APB1RSTR2_LPTIM2RST); - modifyreg32(STM32L4_RCC_APB1RSTR2, RCC_APB1RSTR2_LPTIM2RST, 0); +#if defined(CONFIG_STM32_LPTIM2) + case STM32_LPTIM2_BASE: + modifyreg32(STM32_RCC_APB1RSTR2, 0, RCC_APB1RSTR2_LPTIM2RST); + modifyreg32(STM32_RCC_APB1RSTR2, RCC_APB1RSTR2_LPTIM2RST, 0); break; #endif } @@ -291,21 +291,21 @@ static int stm32l4_lptim_reset(struct stm32l4_lptim_dev_s *dev) } /**************************************************************************** - * Name: stm32l4_lptim_get_gpioconfig + * Name: stm32_lptim_get_gpioconfig ****************************************************************************/ -static int stm32l4_lptim_get_gpioconfig(struct stm32l4_lptim_dev_s *dev, - stm32l4_lptim_channel_t channel, +static int stm32_lptim_get_gpioconfig(struct stm32_lptim_dev_s *dev, + stm32_lptim_channel_t channel, uint32_t *cfg) { DEBUGASSERT(dev != NULL && cfg != NULL); - channel &= STM32L4_LPTIM_CH_MASK; + channel &= STM32_LPTIM_CH_MASK; - switch (((struct stm32l4_lptim_priv_s *)dev)->base) + switch (((struct stm32_lptim_priv_s *)dev)->base) { -#if defined(CONFIG_STM32L4_LPTIM1) - case STM32L4_LPTIM1_BASE: +#if defined(CONFIG_STM32_LPTIM1) + case STM32_LPTIM1_BASE: switch (channel) { # if defined(GPIO_LPTIM1_OUT_1) @@ -327,10 +327,10 @@ static int stm32l4_lptim_get_gpioconfig(struct stm32l4_lptim_dev_s *dev, return ERROR; } break; -#endif /* CONFIG_STM32L4_LPTIM1 */ +#endif /* CONFIG_STM32_LPTIM1 */ -#if defined(CONFIG_STM32L4_LPTIM2) - case STM32L4_LPTIM2_BASE: +#if defined(CONFIG_STM32_LPTIM2) + case STM32_LPTIM2_BASE: switch (channel) { # if defined(GPIO_LPTIM2_OUT_1) @@ -352,7 +352,7 @@ static int stm32l4_lptim_get_gpioconfig(struct stm32l4_lptim_dev_s *dev, return ERROR; } break; -#endif /* CONFIG_STM32L4_LPTIM2 */ +#endif /* CONFIG_STM32_LPTIM2 */ default: return ERROR; @@ -362,31 +362,31 @@ static int stm32l4_lptim_get_gpioconfig(struct stm32l4_lptim_dev_s *dev, } /**************************************************************************** - * Name: stm32l4_lptim_setmode + * Name: stm32_lptim_setmode ****************************************************************************/ -static int stm32l4_lptim_setmode(struct stm32l4_lptim_dev_s *dev, - stm32l4_lptim_mode_t mode) +static int stm32_lptim_setmode(struct stm32_lptim_dev_s *dev, + stm32_lptim_mode_t mode) { - const uint32_t addr = ((struct stm32l4_lptim_priv_s *)dev)->base + - STM32L4_LPTIM_CR_OFFSET; + const uint32_t addr = ((struct stm32_lptim_priv_s *)dev)->base + + STM32_LPTIM_CR_OFFSET; DEBUGASSERT(dev != NULL); /* Mode */ - switch (mode & STM32L4_LPTIM_MODE_MASK) + switch (mode & STM32_LPTIM_MODE_MASK) { - case STM32L4_LPTIM_MODE_DISABLED: + case STM32_LPTIM_MODE_DISABLED: modifyreg32(addr, LPTIM_CR_ENABLE, 0); break; - case STM32L4_LPTIM_MODE_SINGLE: + case STM32_LPTIM_MODE_SINGLE: modifyreg32(addr, 0, LPTIM_CR_ENABLE); modifyreg32(addr, 0, LPTIM_CR_SNGSTRT); break; - case STM32L4_LPTIM_MODE_CONTINUOUS: + case STM32_LPTIM_MODE_CONTINUOUS: modifyreg32(addr, 0, LPTIM_CR_ENABLE); modifyreg32(addr, 0, LPTIM_CR_CNTSTRT); break; @@ -397,20 +397,20 @@ static int stm32l4_lptim_setmode(struct stm32l4_lptim_dev_s *dev, /* Save mode */ - ((struct stm32l4_lptim_priv_s *)dev)->mode = mode; + ((struct stm32_lptim_priv_s *)dev)->mode = mode; return OK; } /**************************************************************************** - * Name: stm32l4_lptim_setclock + * Name: stm32_lptim_setclock ****************************************************************************/ -static int stm32l4_lptim_setclock(struct stm32l4_lptim_dev_s *dev, +static int stm32_lptim_setclock(struct stm32_lptim_dev_s *dev, uint32_t freq) { - struct stm32l4_lptim_priv_s *priv = - (struct stm32l4_lptim_priv_s *)dev; + struct stm32_lptim_priv_s *priv = + (struct stm32_lptim_priv_s *)dev; uint32_t setbits; uint32_t actual; @@ -420,7 +420,7 @@ static int stm32l4_lptim_setclock(struct stm32l4_lptim_dev_s *dev, if (freq == 0) { - stm32l4_lptim_disable(dev); + stm32_lptim_disable(dev); return 0; } @@ -469,19 +469,19 @@ static int stm32l4_lptim_setclock(struct stm32l4_lptim_dev_s *dev, actual = priv->freq >> 7; } - stm32l4_modifyreg32(dev, STM32L4_LPTIM_CFGR_OFFSET, LPTIM_CFGR_PRESC_MASK, + stm32_modifyreg32(dev, STM32_LPTIM_CFGR_OFFSET, LPTIM_CFGR_PRESC_MASK, setbits); - stm32l4_lptim_enable(dev); + stm32_lptim_enable(dev); return actual; } /**************************************************************************** - * Name: stm32l4_lptim_setchannel + * Name: stm32_lptim_setchannel ****************************************************************************/ -static int stm32l4_lptim_setchannel(struct stm32l4_lptim_dev_s *dev, - stm32l4_lptim_channel_t channel, +static int stm32_lptim_setchannel(struct stm32_lptim_dev_s *dev, + stm32_lptim_channel_t channel, int enable) { int ret = OK; @@ -491,16 +491,16 @@ static int stm32l4_lptim_setchannel(struct stm32l4_lptim_dev_s *dev, /* Configure GPIOs */ - ret = stm32l4_lptim_get_gpioconfig(dev, channel, &cfg); + ret = stm32_lptim_get_gpioconfig(dev, channel, &cfg); if (!ret) { if (enable) { - stm32l4_configgpio(cfg); + stm32_configgpio(cfg); } else { - stm32l4_unconfiggpio(cfg); + stm32_unconfiggpio(cfg); } } @@ -508,20 +508,20 @@ static int stm32l4_lptim_setchannel(struct stm32l4_lptim_dev_s *dev, } /**************************************************************************** - * Name: stm32l4_lptim_setclocksource + * Name: stm32_lptim_setclocksource ****************************************************************************/ -static int stm32l4_lptim_setclocksource(struct stm32l4_lptim_dev_s *dev, - stm32l4_lptim_clksrc_t clksrc) +static int stm32_lptim_setclocksource(struct stm32_lptim_dev_s *dev, + stm32_lptim_clksrc_t clksrc) { - struct stm32l4_lptim_priv_s *priv = - (struct stm32l4_lptim_priv_s *)dev; + struct stm32_lptim_priv_s *priv = + (struct stm32_lptim_priv_s *)dev; DEBUGASSERT(dev != NULL); - if (clksrc == STM32L4_LPTIM_CLK_EXT) + if (clksrc == STM32_LPTIM_CLK_EXT) { - stm32l4_modifyreg32(dev, STM32L4_LPTIM_CFGR_OFFSET, + stm32_modifyreg32(dev, STM32_LPTIM_CFGR_OFFSET, LPTIM_CFGR_CKSEL_MASK, LPTIM_CFGR_CKSEL_EXTCLK); } @@ -531,13 +531,13 @@ static int stm32l4_lptim_setclocksource(struct stm32l4_lptim_dev_s *dev, switch (priv->base) { -#ifdef CONFIG_STM32L4_LPTIM1 - case STM32L4_LPTIM1_BASE: +#ifdef CONFIG_STM32_LPTIM1 + case STM32_LPTIM1_BASE: ccr_mask = RCC_CCIPR_LPTIM1SEL_MASK; break; #endif -#ifdef CONFIG_STM32L4_LPTIM2 - case STM32L4_LPTIM2_BASE: +#ifdef CONFIG_STM32_LPTIM2 + case STM32_LPTIM2_BASE: ccr_mask = RCC_CCIPR_LPTIM2SEL_MASK; break; #endif @@ -547,61 +547,61 @@ static int stm32l4_lptim_setclocksource(struct stm32l4_lptim_dev_s *dev, switch (clksrc) { - case STM32L4_LPTIM_CLK_PCLK: + case STM32_LPTIM_CLK_PCLK: switch (priv->base) { -#ifdef CONFIG_STM32L4_LPTIM1 - case STM32L4_LPTIM1_BASE: +#ifdef CONFIG_STM32_LPTIM1 + case STM32_LPTIM1_BASE: ccr_bits = RCC_CCIPR_LPTIM1SEL_PCLK; break; #endif -#ifdef CONFIG_STM32L4_LPTIM2 - case STM32L4_LPTIM2_BASE: +#ifdef CONFIG_STM32_LPTIM2 + case STM32_LPTIM2_BASE: ccr_bits = RCC_CCIPR_LPTIM2SEL_PCLK; break; #endif } break; - case STM32L4_LPTIM_CLK_HSI: + case STM32_LPTIM_CLK_HSI: switch (priv->base) { -#ifdef CONFIG_STM32L4_LPTIM1 - case STM32L4_LPTIM1_BASE: +#ifdef CONFIG_STM32_LPTIM1 + case STM32_LPTIM1_BASE: ccr_bits = RCC_CCIPR_LPTIM1SEL_HSI; break; #endif -#ifdef CONFIG_STM32L4_LPTIM2 - case STM32L4_LPTIM2_BASE: +#ifdef CONFIG_STM32_LPTIM2 + case STM32_LPTIM2_BASE: ccr_bits = RCC_CCIPR_LPTIM2SEL_HSI; break; #endif } break; - case STM32L4_LPTIM_CLK_LSI: + case STM32_LPTIM_CLK_LSI: switch (priv->base) { -#ifdef CONFIG_STM32L4_LPTIM1 - case STM32L4_LPTIM1_BASE: +#ifdef CONFIG_STM32_LPTIM1 + case STM32_LPTIM1_BASE: ccr_bits = RCC_CCIPR_LPTIM1SEL_LSI; break; #endif -#ifdef CONFIG_STM32L4_LPTIM2 - case STM32L4_LPTIM2_BASE: +#ifdef CONFIG_STM32_LPTIM2 + case STM32_LPTIM2_BASE: ccr_bits = RCC_CCIPR_LPTIM2SEL_LSI; break; #endif } break; - case STM32L4_LPTIM_CLK_LSE: + case STM32_LPTIM_CLK_LSE: switch (priv->base) { -#ifdef CONFIG_STM32L4_LPTIM1 - case STM32L4_LPTIM1_BASE: +#ifdef CONFIG_STM32_LPTIM1 + case STM32_LPTIM1_BASE: ccr_bits = RCC_CCIPR_LPTIM1SEL_LSE; break; #endif -#ifdef CONFIG_STM32L4_LPTIM2 - case STM32L4_LPTIM2_BASE: +#ifdef CONFIG_STM32_LPTIM2 + case STM32_LPTIM2_BASE: ccr_bits = RCC_CCIPR_LPTIM2SEL_LSE; break; #endif @@ -611,9 +611,9 @@ static int stm32l4_lptim_setclocksource(struct stm32l4_lptim_dev_s *dev, break; } - modifyreg32(STM32L4_RCC_CCIPR, ccr_mask, ccr_bits); + modifyreg32(STM32_RCC_CCIPR, ccr_mask, ccr_bits); - stm32l4_modifyreg32(dev, STM32L4_LPTIM_CFGR_OFFSET, + stm32_modifyreg32(dev, STM32_LPTIM_CFGR_OFFSET, LPTIM_CFGR_CKSEL_MASK, LPTIM_CFGR_CKSEL_INTCLK); } @@ -622,49 +622,49 @@ static int stm32l4_lptim_setclocksource(struct stm32l4_lptim_dev_s *dev, } /**************************************************************************** - * Name: stm32l4_lptim_setperiod + * Name: stm32_lptim_setperiod ****************************************************************************/ -static void stm32l4_lptim_setperiod(struct stm32l4_lptim_dev_s *dev, +static void stm32_lptim_setperiod(struct stm32_lptim_dev_s *dev, uint32_t period) { - struct stm32l4_lptim_priv_s *priv = - (struct stm32l4_lptim_priv_s *)dev; + struct stm32_lptim_priv_s *priv = + (struct stm32_lptim_priv_s *)dev; DEBUGASSERT(dev != NULL); - putreg32(period, (uintptr_t)(priv->base + STM32L4_LPTIM_ARR_OFFSET)); + putreg32(period, (uintptr_t)(priv->base + STM32_LPTIM_ARR_OFFSET)); } /**************************************************************************** - * Name: stm32l4_tim_getperiod + * Name: stm32_tim_getperiod ****************************************************************************/ -static uint32_t stm32l4_lptim_getperiod(struct stm32l4_lptim_dev_s *dev) +static uint32_t stm32_lptim_getperiod(struct stm32_lptim_dev_s *dev) { - struct stm32l4_lptim_priv_s *priv = - (struct stm32l4_lptim_priv_s *)dev; + struct stm32_lptim_priv_s *priv = + (struct stm32_lptim_priv_s *)dev; DEBUGASSERT(dev != NULL); - return getreg32((uintptr_t)(priv->base + STM32L4_LPTIM_ARR_OFFSET)); + return getreg32((uintptr_t)(priv->base + STM32_LPTIM_ARR_OFFSET)); } /**************************************************************************** - * Name: stm32l4_lptim_setcountmode + * Name: stm32_lptim_setcountmode ****************************************************************************/ -static int stm32l4_lptim_setcountmode(struct stm32l4_lptim_dev_s *dev, - stm32l4_lptim_cntmode_t cntmode) +static int stm32_lptim_setcountmode(struct stm32_lptim_dev_s *dev, + stm32_lptim_cntmode_t cntmode) { DEBUGASSERT(dev != NULL); - if (cntmode == STM32L4_LPTIM_COUNT_CLOCK) + if (cntmode == STM32_LPTIM_COUNT_CLOCK) { - stm32l4_modifyreg32(dev, STM32L4_LPTIM_CFGR_OFFSET, + stm32_modifyreg32(dev, STM32_LPTIM_CFGR_OFFSET, LPTIM_CFGR_COUNTMODE, 0); } - else if (cntmode == STM32L4_LPTIM_COUNT_EXTTRIG) + else if (cntmode == STM32_LPTIM_COUNT_EXTTRIG) { - stm32l4_modifyreg32(dev, STM32L4_LPTIM_CFGR_OFFSET, + stm32_modifyreg32(dev, STM32_LPTIM_CFGR_OFFSET, 0, LPTIM_CFGR_COUNTMODE); } else @@ -676,30 +676,30 @@ static int stm32l4_lptim_setcountmode(struct stm32l4_lptim_dev_s *dev, } /**************************************************************************** - * Name: stm32l4_lptim_setpolarity + * Name: stm32_lptim_setpolarity ****************************************************************************/ -static int stm32l4_lptim_setpolarity(struct stm32l4_lptim_dev_s *dev, - stm32l4_lptim_clkpol_t polarity) +static int stm32_lptim_setpolarity(struct stm32_lptim_dev_s *dev, + stm32_lptim_clkpol_t polarity) { DEBUGASSERT(dev != NULL); switch (polarity) { - case STM32L4_LPTIM_CLKPOL_RISING: - stm32l4_modifyreg32(dev, STM32L4_LPTIM_CFGR_OFFSET, + case STM32_LPTIM_CLKPOL_RISING: + stm32_modifyreg32(dev, STM32_LPTIM_CFGR_OFFSET, LPTIM_CFGR_CKPOL_MASK, LPTIM_CFGR_CKPOL_RISING); break; - case STM32L4_LPTIM_CLKPOL_FALLING: - stm32l4_modifyreg32(dev, STM32L4_LPTIM_CFGR_OFFSET, + case STM32_LPTIM_CLKPOL_FALLING: + stm32_modifyreg32(dev, STM32_LPTIM_CFGR_OFFSET, LPTIM_CFGR_CKPOL_MASK, LPTIM_CFGR_CKPOL_FALLING); break; - case STM32L4_LPTIM_CLKPOL_BOTH: - stm32l4_modifyreg32(dev, STM32L4_LPTIM_CFGR_OFFSET, + case STM32_LPTIM_CLKPOL_BOTH: + stm32_modifyreg32(dev, STM32_LPTIM_CFGR_OFFSET, LPTIM_CFGR_CKPOL_MASK, LPTIM_CFGR_CKPOL_BOTH); break; @@ -709,13 +709,13 @@ static int stm32l4_lptim_setpolarity(struct stm32l4_lptim_dev_s *dev, } /**************************************************************************** - * Name: stm32l4_lptim_setpolarity + * Name: stm32_lptim_setpolarity ****************************************************************************/ -static uint32_t stm32l4_lptim_getcounter(struct stm32l4_lptim_dev_s *dev) +static uint32_t stm32_lptim_getcounter(struct stm32_lptim_dev_s *dev) { - struct stm32l4_lptim_priv_s *priv = - (struct stm32l4_lptim_priv_s *)dev; + struct stm32_lptim_priv_s *priv = + (struct stm32_lptim_priv_s *)dev; DEBUGASSERT(dev != NULL); @@ -725,9 +725,9 @@ static uint32_t stm32l4_lptim_getcounter(struct stm32l4_lptim_dev_s *dev) do { counter1 = getreg32((uintptr_t)(priv->base + - STM32L4_LPTIM_CNT_OFFSET)); + STM32_LPTIM_CNT_OFFSET)); counter2 = getreg32((uintptr_t)(priv->base + - STM32L4_LPTIM_CNT_OFFSET)); + STM32_LPTIM_CNT_OFFSET)); } while (counter1 != counter2); @@ -739,16 +739,16 @@ static uint32_t stm32l4_lptim_getcounter(struct stm32l4_lptim_dev_s *dev) ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_lptim_init + * Name: stm32_lptim_init ****************************************************************************/ -struct stm32l4_lptim_dev_s *stm32l4_lptim_init(int timer) +struct stm32_lptim_dev_s *stm32_lptim_init(int timer) { - struct stm32l4_lptim_dev_s *dev = NULL; + struct stm32_lptim_dev_s *dev = NULL; /* Get structure and enable power */ - dev = stm32l4_lptim_getstruct(timer); + dev = stm32_lptim_getstruct(timer); if (!dev) { return NULL; @@ -756,44 +756,44 @@ struct stm32l4_lptim_dev_s *stm32l4_lptim_init(int timer) /* Is device already allocated */ - if (((struct stm32l4_lptim_priv_s *)dev)->mode != - STM32L4_LPTIM_MODE_UNUSED) + if (((struct stm32_lptim_priv_s *)dev)->mode != + STM32_LPTIM_MODE_UNUSED) { return NULL; } /* Enable power */ - stm32l4_lptim_enable(dev); + stm32_lptim_enable(dev); /* Reset timer */ - stm32l4_lptim_reset(dev); + stm32_lptim_reset(dev); /* Mark it as used */ - ((struct stm32l4_lptim_priv_s *)dev)->mode = STM32L4_LPTIM_MODE_DISABLED; + ((struct stm32_lptim_priv_s *)dev)->mode = STM32_LPTIM_MODE_DISABLED; return dev; } /**************************************************************************** - * Name: stm32l4_lptim_deinit + * Name: stm32_lptim_deinit ****************************************************************************/ -int stm32l4_lptim_deinit(struct stm32l4_lptim_dev_s * dev) +int stm32_lptim_deinit(struct stm32_lptim_dev_s * dev) { DEBUGASSERT(dev); /* Disable power */ - stm32l4_lptim_disable(dev); + stm32_lptim_disable(dev); /* Mark it as free */ - ((struct stm32l4_lptim_priv_s *)dev)->mode = STM32L4_LPTIM_MODE_UNUSED; + ((struct stm32_lptim_priv_s *)dev)->mode = STM32_LPTIM_MODE_UNUSED; return OK; } -#endif /* CONFIG_STM32L4_LPTIM1 || CONFIG_STM32L4_LPTIM2 */ +#endif /* CONFIG_STM32_LPTIM1 || CONFIG_STM32_LPTIM2 */ diff --git a/arch/arm/src/stm32l4/stm32l4_lptim.h b/arch/arm/src/stm32l4/stm32l4_lptim.h index 1f57f6ac9eda1..1293aa551bc69 100644 --- a/arch/arm/src/stm32l4/stm32l4_lptim.h +++ b/arch/arm/src/stm32l4/stm32l4_lptim.h @@ -68,8 +68,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32L4_STM32L4_LPTIM_H -#define __ARCH_ARM_SRC_STM32L4_STM32L4_LPTIM_H +#ifndef __ARCH_ARM_SRC_STM32L4_STM32_LPTIM_H +#define __ARCH_ARM_SRC_STM32L4_STM32_LPTIM_H /**************************************************************************** * Included Files @@ -86,14 +86,14 @@ /* Helpers ******************************************************************/ -#define STM32L4_LPTIM_SETMODE(d,mode) ((d)->ops->setmode(d,mode)) -#define STM32L4_LPTIM_SETCLOCK(d,freq) ((d)->ops->setclock(d,freq)) -#define STM32L4_LPTIM_SETCHANNEL(d,ch,en) ((d)->ops->setchannel(d,ch,en)) -#define STM32L4_LPTIM_SETCLOCKSOURCE(d,s) ((d)->ops->setclocksource(d,s)) -#define STM32L4_LPTIM_GETCOUNTER(d) ((d)->ops->getcounter(d)) -#define STM32L4_LPTIM_SETCOUNTMODE(d,m) ((d)->ops->setcountmode(d,m)) -#define STM32L4_LPTIM_SETPERIOD(d,period) ((d)->ops->setperiod(d,period)) -#define STM32L4_LPTIM_GETPERIOD(d) ((d)->ops->getperiod(d)) +#define STM32_LPTIM_SETMODE(d,mode) ((d)->ops->setmode(d,mode)) +#define STM32_LPTIM_SETCLOCK(d,freq) ((d)->ops->setclock(d,freq)) +#define STM32_LPTIM_SETCHANNEL(d,ch,en) ((d)->ops->setchannel(d,ch,en)) +#define STM32_LPTIM_SETCLOCKSOURCE(d,s) ((d)->ops->setclocksource(d,s)) +#define STM32_LPTIM_GETCOUNTER(d) ((d)->ops->getcounter(d)) +#define STM32_LPTIM_SETCOUNTMODE(d,m) ((d)->ops->setcountmode(d,m)) +#define STM32_LPTIM_SETPERIOD(d,period) ((d)->ops->setperiod(d,period)) +#define STM32_LPTIM_GETPERIOD(d) ((d)->ops->getperiod(d)) /**************************************************************************** * Public Types @@ -112,24 +112,24 @@ extern "C" /* LPTIM Device Structure */ -struct stm32l4_lptim_dev_s +struct stm32_lptim_dev_s { - struct stm32l4_lptim_ops_s *ops; + struct stm32_lptim_ops_s *ops; }; /* LPTIM Modes of Operation */ typedef enum { - STM32L4_LPTIM_MODE_UNUSED = -1, + STM32_LPTIM_MODE_UNUSED = -1, /* MODES */ - STM32L4_LPTIM_MODE_DISABLED = 0x0000, - STM32L4_LPTIM_MODE_SINGLE = 0x0001, - STM32L4_LPTIM_MODE_CONTINUOUS = 0x0002, - STM32L4_LPTIM_MODE_MASK = 0x000f, -} stm32l4_lptim_mode_t; + STM32_LPTIM_MODE_DISABLED = 0x0000, + STM32_LPTIM_MODE_SINGLE = 0x0001, + STM32_LPTIM_MODE_CONTINUOUS = 0x0002, + STM32_LPTIM_MODE_MASK = 0x000f, +} stm32_lptim_mode_t; /* LPTIM Clock Source */ @@ -137,12 +137,12 @@ typedef enum { /* Clock Sources */ - STM32L4_LPTIM_CLK_PCLK = 0x0000, - STM32L4_LPTIM_CLK_LSI = 0x0001, - STM32L4_LPTIM_CLK_HSI = 0x0002, - STM32L4_LPTIM_CLK_LSE = 0x0003, - STM32L4_LPTIM_CLK_EXT = 0x0004, -} stm32l4_lptim_clksrc_t; + STM32_LPTIM_CLK_PCLK = 0x0000, + STM32_LPTIM_CLK_LSI = 0x0001, + STM32_LPTIM_CLK_HSI = 0x0002, + STM32_LPTIM_CLK_LSE = 0x0003, + STM32_LPTIM_CLK_EXT = 0x0004, +} stm32_lptim_clksrc_t; /* LPTIM Counter Modes */ @@ -150,9 +150,9 @@ typedef enum { /* Modes */ - STM32L4_LPTIM_COUNT_CLOCK = 0x0000, - STM32L4_LPTIM_COUNT_EXTTRIG = 0x0001, -} stm32l4_lptim_cntmode_t; + STM32_LPTIM_COUNT_CLOCK = 0x0000, + STM32_LPTIM_COUNT_EXTTRIG = 0x0001, +} stm32_lptim_cntmode_t; /* LPTIM Clock Polarity */ @@ -160,44 +160,44 @@ typedef enum { /* MODES */ - STM32L4_LPTIM_CLKPOL_RISING = 0x0000, - STM32L4_LPTIM_CLKPOL_FALLING = 0x0001, - STM32L4_LPTIM_CLKPOL_BOTH = 0x0002, -} stm32l4_lptim_clkpol_t; + STM32_LPTIM_CLKPOL_RISING = 0x0000, + STM32_LPTIM_CLKPOL_FALLING = 0x0001, + STM32_LPTIM_CLKPOL_BOTH = 0x0002, +} stm32_lptim_clkpol_t; /* LPTIM Channel Modes */ typedef enum { - STM32L4_LPTIM_CH_DISABLED = 0x0000, + STM32_LPTIM_CH_DISABLED = 0x0000, /* CHANNELS */ - STM32L4_LPTIM_CH_CHINVALID = 0x0000, - STM32L4_LPTIM_CH_CH1 = 0x0001, - STM32L4_LPTIM_CH_CH2 = 0x0002, - STM32L4_LPTIM_CH_CH3 = 0x0003, - STM32L4_LPTIM_CH_MASK = 0x000f, -} stm32l4_lptim_channel_t; + STM32_LPTIM_CH_CHINVALID = 0x0000, + STM32_LPTIM_CH_CH1 = 0x0001, + STM32_LPTIM_CH_CH2 = 0x0002, + STM32_LPTIM_CH_CH3 = 0x0003, + STM32_LPTIM_CH_MASK = 0x000f, +} stm32_lptim_channel_t; /* LPTIM Operations */ -struct stm32l4_lptim_ops_s +struct stm32_lptim_ops_s { - int (*setmode)(struct stm32l4_lptim_dev_s *dev, - stm32l4_lptim_mode_t mode); - int (*setclock)(struct stm32l4_lptim_dev_s *dev, uint32_t freq); - int (*setchannel)(struct stm32l4_lptim_dev_s *dev, - stm32l4_lptim_channel_t channel, int enable); - int (*setclocksource)(struct stm32l4_lptim_dev_s *dev, - stm32l4_lptim_clksrc_t clksrc); - int (*setpolarity)(struct stm32l4_lptim_dev_s *dev, - stm32l4_lptim_clkpol_t polarity); - uint32_t (*getcounter)(struct stm32l4_lptim_dev_s *dev); - int (*setcountmode)(struct stm32l4_lptim_dev_s *dev, - stm32l4_lptim_cntmode_t cntmode); - void (*setperiod)(struct stm32l4_lptim_dev_s *dev, uint32_t period); - uint32_t (*getperiod)(struct stm32l4_lptim_dev_s *dev); + int (*setmode)(struct stm32_lptim_dev_s *dev, + stm32_lptim_mode_t mode); + int (*setclock)(struct stm32_lptim_dev_s *dev, uint32_t freq); + int (*setchannel)(struct stm32_lptim_dev_s *dev, + stm32_lptim_channel_t channel, int enable); + int (*setclocksource)(struct stm32_lptim_dev_s *dev, + stm32_lptim_clksrc_t clksrc); + int (*setpolarity)(struct stm32_lptim_dev_s *dev, + stm32_lptim_clkpol_t polarity); + uint32_t (*getcounter)(struct stm32_lptim_dev_s *dev); + int (*setcountmode)(struct stm32_lptim_dev_s *dev, + stm32_lptim_cntmode_t cntmode); + void (*setperiod)(struct stm32_lptim_dev_s *dev, uint32_t period); + uint32_t (*getperiod)(struct stm32_lptim_dev_s *dev); }; /**************************************************************************** @@ -206,11 +206,11 @@ struct stm32l4_lptim_ops_s /* Get timer structure, power-up, reset, and mark it as used */ -struct stm32l4_lptim_dev_s *stm32l4_lptim_init(int timer); +struct stm32_lptim_dev_s *stm32_lptim_init(int timer); /* Power-down timer, mark it as unused */ -int stm32l4_lptim_deinit(struct stm32l4_lptim_dev_s *dev); +int stm32_lptim_deinit(struct stm32_lptim_dev_s *dev); #undef EXTERN #if defined(__cplusplus) @@ -218,4 +218,4 @@ int stm32l4_lptim_deinit(struct stm32l4_lptim_dev_s *dev); #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32L4_STM32L4_LPTIM_H */ +#endif /* __ARCH_ARM_SRC_STM32L4_STM32_LPTIM_H */ diff --git a/arch/arm/src/stm32l4/stm32l4_lse.c b/arch/arm/src/stm32l4/stm32l4_lse.c index 19914bc5b05ab..bd434cf69f307 100644 --- a/arch/arm/src/stm32l4/stm32l4_lse.c +++ b/arch/arm/src/stm32l4/stm32l4_lse.c @@ -29,22 +29,22 @@ #include "arm_internal.h" #include "stm32l4_pwr.h" #include "stm32l4_rcc.h" -#include "stm32l4_waste.h" +#include "stm32_waste.h" /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ -#ifdef CONFIG_STM32L4_RTC_LSECLOCK_START_DRV_CAPABILITY -# if CONFIG_STM32L4_RTC_LSECLOCK_START_DRV_CAPABILITY < 0 || \ - CONFIG_STM32L4_RTC_LSECLOCK_START_DRV_CAPABILITY > 3 +#ifdef CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY +# if CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY < 0 || \ + CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY > 3 # error "Invalid LSE drive capability setting" # endif #endif -#ifdef CONFIG_STM32L4_RTC_LSECLOCK_RUN_DRV_CAPABILITY -# if CONFIG_STM32L4_RTC_LSECLOCK_RUN_DRV_CAPABILITY < 0 || \ - CONFIG_STM32L4_RTC_LSECLOCK_RUN_DRV_CAPABILITY > 3 +#ifdef CONFIG_STM32_RTC_LSECLOCK_RUN_DRV_CAPABILITY +# if CONFIG_STM32_RTC_LSECLOCK_RUN_DRV_CAPABILITY < 0 || \ + CONFIG_STM32_RTC_LSECLOCK_RUN_DRV_CAPABILITY > 3 # error "Invalid LSE drive capability setting" # endif #endif @@ -54,21 +54,21 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_rcc_enablelse + * Name: stm32_rcc_enablelse * * Description: * Enable the External Low-Speed (LSE) oscillator. * ****************************************************************************/ -void stm32l4_rcc_enablelse(void) +void stm32_rcc_enablelse(void) { bool writable; uint32_t regval; /* Check if the External Low-Speed (LSE) oscillator is already running. */ - regval = getreg32(STM32L4_RCC_BDCR); + regval = getreg32(STM32_RCC_BDCR); if ((regval & (RCC_BDCR_LSEON | RCC_BDCR_LSERDY)) != (RCC_BDCR_LSEON | RCC_BDCR_LSERDY)) @@ -78,7 +78,7 @@ void stm32l4_rcc_enablelse(void) * in the PWR CR register before to configuring the LSE. */ - writable = stm32l4_pwr_enablebkp(true); + writable = stm32_pwr_enablebkp(true); /* Enable the External Low-Speed (LSE) oscillator by setting the * LSEON bit the RCC BDCR register. @@ -86,41 +86,41 @@ void stm32l4_rcc_enablelse(void) regval |= RCC_BDCR_LSEON; -#ifdef CONFIG_STM32L4_RTC_LSECLOCK_START_DRV_CAPABILITY +#ifdef CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY /* Set start-up drive capability for LSE oscillator. */ regval &= ~RCC_BDCR_LSEDRV_MASK; - regval |= CONFIG_STM32L4_RTC_LSECLOCK_START_DRV_CAPABILITY << + regval |= CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY << RCC_BDCR_LSEDRV_SHIFT; #endif - putreg32(regval, STM32L4_RCC_BDCR); + putreg32(regval, STM32_RCC_BDCR); /* Wait for the LSE clock to be ready */ - while (((regval = getreg32(STM32L4_RCC_BDCR)) & RCC_BDCR_LSERDY) == 0) + while (((regval = getreg32(STM32_RCC_BDCR)) & RCC_BDCR_LSERDY) == 0) { - stm32l4_waste(); + stm32_waste(); } -#if defined(CONFIG_STM32L4_RTC_LSECLOCK_RUN_DRV_CAPABILITY) && \ - CONFIG_STM32L4_RTC_LSECLOCK_START_DRV_CAPABILITY != \ - CONFIG_STM32L4_RTC_LSECLOCK_RUN_DRV_CAPABILITY +#if defined(CONFIG_STM32_RTC_LSECLOCK_RUN_DRV_CAPABILITY) && \ + CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY != \ + CONFIG_STM32_RTC_LSECLOCK_RUN_DRV_CAPABILITY -# if CONFIG_STM32L4_RTC_LSECLOCK_RUN_DRV_CAPABILITY != 0 +# if CONFIG_STM32_RTC_LSECLOCK_RUN_DRV_CAPABILITY != 0 # error "STM32L4 only allows lowering LSE drive capability to zero" # endif /* Set running drive capability for LSE oscillator. */ regval &= ~RCC_BDCR_LSEDRV_MASK; - regval |= CONFIG_STM32L4_RTC_LSECLOCK_RUN_DRV_CAPABILITY << + regval |= CONFIG_STM32_RTC_LSECLOCK_RUN_DRV_CAPABILITY << RCC_BDCR_LSEDRV_SHIFT; - putreg32(regval, STM32L4_RCC_BDCR); + putreg32(regval, STM32_RCC_BDCR); #endif /* Disable backup domain access if it was disabled on entry */ - stm32l4_pwr_enablebkp(writable); + stm32_pwr_enablebkp(writable); } } diff --git a/arch/arm/src/stm32l4/stm32l4_lsi.c b/arch/arm/src/stm32l4/stm32l4_lsi.c index fb26a31ba160f..ae42b876ca25d 100644 --- a/arch/arm/src/stm32l4/stm32l4_lsi.c +++ b/arch/arm/src/stm32l4/stm32l4_lsi.c @@ -33,41 +33,41 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_rcc_enablelsi + * Name: stm32_rcc_enablelsi * * Description: * Enable the Internal Low-Speed (LSI) RC Oscillator. * ****************************************************************************/ -void stm32l4_rcc_enablelsi(void) +void stm32_rcc_enablelsi(void) { /* Enable the Internal Low-Speed (LSI) RC Oscillator by setting the LSION * bit the RCC CSR register. */ - modifyreg32(STM32L4_RCC_CSR, 0, RCC_CSR_LSION); + modifyreg32(STM32_RCC_CSR, 0, RCC_CSR_LSION); /* Wait for the internal LSI oscillator to be stable. */ - while ((getreg32(STM32L4_RCC_CSR) & RCC_CSR_LSIRDY) == 0); + while ((getreg32(STM32_RCC_CSR) & RCC_CSR_LSIRDY) == 0); } /**************************************************************************** - * Name: stm32l4_rcc_disablelsi + * Name: stm32_rcc_disablelsi * * Description: * Disable the Internal Low-Speed (LSI) RC Oscillator. * ****************************************************************************/ -void stm32l4_rcc_disablelsi(void) +void stm32_rcc_disablelsi(void) { /* Enable the Internal Low-Speed (LSI) RC Oscillator by setting the LSION * bit the RCC CSR register. */ - modifyreg32(STM32L4_RCC_CSR, RCC_CSR_LSION, 0); + modifyreg32(STM32_RCC_CSR, RCC_CSR_LSION, 0); /* LSIRDY should go low after 3 LSI clock cycles */ } diff --git a/arch/arm/src/stm32l4/stm32l4_mpuinit.c b/arch/arm/src/stm32l4/stm32l4_mpuinit.c index fe22ca17d483d..1deb74cdf96c4 100644 --- a/arch/arm/src/stm32l4/stm32l4_mpuinit.c +++ b/arch/arm/src/stm32l4/stm32l4_mpuinit.c @@ -41,7 +41,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_mpuinitialize + * Name: stm32_mpuinitialize * * Description: * Configure the MPU to permit user-space access to only restricted SAM3U @@ -49,7 +49,7 @@ * ****************************************************************************/ -void stm32l4_mpuinitialize(void) +void stm32_mpuinitialize(void) { uintptr_t datastart = MIN(USERSPACE->us_datastart, USERSPACE->us_bssstart); uintptr_t dataend = MAX(USERSPACE->us_dataend, USERSPACE->us_bssend); @@ -74,7 +74,7 @@ void stm32l4_mpuinitialize(void) } /**************************************************************************** - * Name: stm32l4_mpu_uheap + * Name: stm32_mpu_uheap * * Description: * Map the user-heap region. @@ -83,7 +83,7 @@ void stm32l4_mpuinitialize(void) * ****************************************************************************/ -void stm32l4_mpu_uheap(uintptr_t start, size_t size) +void stm32_mpu_uheap(uintptr_t start, size_t size) { mpu_user_intsram(start, size); } diff --git a/arch/arm/src/stm32l4/stm32l4_mpuinit.h b/arch/arm/src/stm32l4/stm32l4_mpuinit.h index 986554b2ba8ea..4a7df2c276471 100644 --- a/arch/arm/src/stm32l4/stm32l4_mpuinit.h +++ b/arch/arm/src/stm32l4/stm32l4_mpuinit.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32L4_STM32L4_MPUINIT_H -#define __ARCH_ARM_SRC_STM32L4_STM32L4_MPUINIT_H +#ifndef __ARCH_ARM_SRC_STM32L4_STM32_MPUINIT_H +#define __ARCH_ARM_SRC_STM32L4_STM32_MPUINIT_H /**************************************************************************** * Included Files @@ -34,7 +34,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_mpuinitialize + * Name: stm32_mpuinitialize * * Description: * Configure the MPU to permit user-space access to only unrestricted MCU @@ -43,13 +43,13 @@ ****************************************************************************/ #ifdef CONFIG_BUILD_PROTECTED -void stm32l4_mpuinitialize(void); +void stm32_mpuinitialize(void); #else -# define stm32l4_mpuinitialize() +# define stm32_mpuinitialize() #endif /**************************************************************************** - * Name: stm32l4_mpu_uheap + * Name: stm32_mpu_uheap * * Description: * Map the user heap region. @@ -57,9 +57,9 @@ void stm32l4_mpuinitialize(void); ****************************************************************************/ #ifdef CONFIG_BUILD_PROTECTED -void stm32l4_mpu_uheap(uintptr_t start, size_t size); +void stm32_mpu_uheap(uintptr_t start, size_t size); #else -# define stm32l4_mpu_uheap(start,size) +# define stm32_mpu_uheap(start,size) #endif -#endif /* __ARCH_ARM_SRC_STM32L4_STM32L4_MPUINIT_H */ +#endif /* __ARCH_ARM_SRC_STM32L4_STM32_MPUINIT_H */ diff --git a/arch/arm/src/stm32l4/stm32l4_oneshot.c b/arch/arm/src/stm32l4/stm32l4_oneshot.c index 0b70b905db882..ebacd10a6096c 100644 --- a/arch/arm/src/stm32l4/stm32l4_oneshot.c +++ b/arch/arm/src/stm32l4/stm32l4_oneshot.c @@ -39,26 +39,26 @@ #include "stm32l4_oneshot.h" -#ifdef CONFIG_STM32L4_ONESHOT +#ifdef CONFIG_STM32_ONESHOT /**************************************************************************** * Private Function Prototypes ****************************************************************************/ -static int stm32l4_oneshot_handler(int irq, void *context, void *arg); +static int stm32_oneshot_handler(int irq, void *context, void *arg); /**************************************************************************** * Private Data ****************************************************************************/ -static struct stm32l4_oneshot_s *g_oneshot[CONFIG_STM32L4_ONESHOT_MAXTIMERS]; +static struct stm32_oneshot_s *g_oneshot[CONFIG_STM32_ONESHOT_MAXTIMERS]; /**************************************************************************** * Private Functions ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_oneshot_handler + * Name: stm32_oneshot_handler * * Description: * Common timer interrupt callback. When any oneshot timer interrupt @@ -73,9 +73,9 @@ static struct stm32l4_oneshot_s *g_oneshot[CONFIG_STM32L4_ONESHOT_MAXTIMERS]; * ****************************************************************************/ -static int stm32l4_oneshot_handler(int irq, void *context, void *arg) +static int stm32_oneshot_handler(int irq, void *context, void *arg) { - struct stm32l4_oneshot_s *oneshot = (struct stm32l4_oneshot_s *) arg; + struct stm32_oneshot_s *oneshot = (struct stm32_oneshot_s *) arg; oneshot_handler_t oneshot_handler; void *oneshot_arg; @@ -86,10 +86,10 @@ static int stm32l4_oneshot_handler(int irq, void *context, void *arg) * Disable the TC now and disable any further interrupts. */ - STM32L4_TIM_SETISR(oneshot->tch, NULL, NULL, 0); - STM32L4_TIM_DISABLEINT(oneshot->tch, 0); - STM32L4_TIM_SETMODE(oneshot->tch, STM32L4_TIM_MODE_DISABLED); - STM32L4_TIM_ACKINT(oneshot->tch, 0); + STM32_TIM_SETISR(oneshot->tch, NULL, NULL, 0); + STM32_TIM_DISABLEINT(oneshot->tch, 0); + STM32_TIM_SETMODE(oneshot->tch, STM32_TIM_MODE_DISABLED); + STM32_TIM_ACKINT(oneshot->tch, 0); /* The timer is no longer running */ @@ -107,7 +107,7 @@ static int stm32l4_oneshot_handler(int irq, void *context, void *arg) } /**************************************************************************** - * Name: stm32l4_allocate_handler + * Name: stm32_allocate_handler * * Description: * Allocate a timer callback handler for the oneshot instance. @@ -117,19 +117,19 @@ static int stm32l4_oneshot_handler(int irq, void *context, void *arg) * * Returned Value: * Returns zero (OK) on success. This can only fail if the number of - * timers exceeds CONFIG_STM32L4_ONESHOT_MAXTIMERS. + * timers exceeds CONFIG_STM32_ONESHOT_MAXTIMERS. * ****************************************************************************/ -static inline int stm32l4_allocate_handler(struct stm32l4_oneshot_s *oneshot) +static inline int stm32_allocate_handler(struct stm32_oneshot_s *oneshot) { -#if CONFIG_STM32L4_ONESHOT_MAXTIMERS > 1 +#if CONFIG_STM32_ONESHOT_MAXTIMERS > 1 int ret = -EBUSY; int i; /* Search for an unused handler */ - for (i = 0; i < CONFIG_STM32L4_ONESHOT_MAXTIMERS; i++) + for (i = 0; i < CONFIG_STM32_ONESHOT_MAXTIMERS; i++) { /* Is this handler available? */ @@ -162,7 +162,7 @@ static inline int stm32l4_allocate_handler(struct stm32l4_oneshot_s *oneshot) ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_oneshot_initialize + * Name: stm32_oneshot_initialize * * Description: * Initialize the oneshot timer wrapper @@ -180,7 +180,7 @@ static inline int stm32l4_allocate_handler(struct stm32l4_oneshot_s *oneshot) * ****************************************************************************/ -int stm32l4_oneshot_initialize(struct stm32l4_oneshot_s *oneshot, +int stm32_oneshot_initialize(struct stm32_oneshot_s *oneshot, int chan, uint16_t resolution) { uint32_t frequency; @@ -193,14 +193,14 @@ int stm32l4_oneshot_initialize(struct stm32l4_oneshot_s *oneshot, frequency = USEC_PER_SEC / (uint32_t)resolution; oneshot->frequency = frequency; - oneshot->tch = stm32l4_tim_init(chan); + oneshot->tch = stm32_tim_init(chan); if (!oneshot->tch) { tmrerr("ERROR: Failed to allocate TIM%d\n", chan); return -EBUSY; } - STM32L4_TIM_SETCLOCK(oneshot->tch, frequency); + STM32_TIM_SETCLOCK(oneshot->tch, frequency); /* Initialize the remaining fields in the state structure. */ @@ -211,18 +211,18 @@ int stm32l4_oneshot_initialize(struct stm32l4_oneshot_s *oneshot, /* Assign a callback handler to the oneshot */ - return stm32l4_allocate_handler(oneshot); + return stm32_allocate_handler(oneshot); } /**************************************************************************** - * Name: stm32l4_oneshot_max_delay + * Name: stm32_oneshot_max_delay * * Description: * Determine the maximum delay of the one-shot timer (in microseconds) * ****************************************************************************/ -int stm32l4_oneshot_max_delay(struct stm32l4_oneshot_s *oneshot, +int stm32_oneshot_max_delay(struct stm32_oneshot_s *oneshot, uint64_t *usec) { DEBUGASSERT(oneshot != NULL && usec != NULL); @@ -233,7 +233,7 @@ int stm32l4_oneshot_max_delay(struct stm32l4_oneshot_s *oneshot, } /**************************************************************************** - * Name: stm32l4_oneshot_start + * Name: stm32_oneshot_start * * Description: * Start the oneshot timer @@ -241,7 +241,7 @@ int stm32l4_oneshot_max_delay(struct stm32l4_oneshot_s *oneshot, * Input Parameters: * oneshot Caller allocated instance of the oneshot state structure. This * structure must have been previously initialized via a call to - * stm32l4_oneshot_initialize(); + * stm32_oneshot_initialize(); * handler The function to call when when the oneshot timer expires. * arg An opaque argument that will accompany the callback. * ts Provides the duration of the one shot timer. @@ -252,7 +252,7 @@ int stm32l4_oneshot_max_delay(struct stm32l4_oneshot_s *oneshot, * ****************************************************************************/ -int stm32l4_oneshot_start(struct stm32l4_oneshot_s *oneshot, +int stm32_oneshot_start(struct stm32_oneshot_s *oneshot, oneshot_handler_t handler, void *arg, const struct timespec *ts) { @@ -273,7 +273,7 @@ int stm32l4_oneshot_start(struct stm32l4_oneshot_s *oneshot, /* Yes.. then cancel it */ tmrinfo("Already running... cancelling\n"); - stm32l4_oneshot_cancel(oneshot, NULL); + stm32_oneshot_cancel(oneshot, NULL); } /* Save the new handler and its argument */ @@ -302,19 +302,19 @@ int stm32l4_oneshot_start(struct stm32l4_oneshot_s *oneshot, /* Set up to receive the callback when the interrupt occurs */ - STM32L4_TIM_SETISR(oneshot->tch, stm32l4_oneshot_handler, oneshot, 0); + STM32_TIM_SETISR(oneshot->tch, stm32_oneshot_handler, oneshot, 0); /* Set timer period */ oneshot->period = (uint32_t)period; - STM32L4_TIM_SETPERIOD(oneshot->tch, (uint32_t)period); + STM32_TIM_SETPERIOD(oneshot->tch, (uint32_t)period); /* Start the counter */ - STM32L4_TIM_SETMODE(oneshot->tch, STM32L4_TIM_MODE_PULSE); + STM32_TIM_SETMODE(oneshot->tch, STM32_TIM_MODE_PULSE); - STM32L4_TIM_ACKINT(oneshot->tch, 0); - STM32L4_TIM_ENABLEINT(oneshot->tch, 0); + STM32_TIM_ACKINT(oneshot->tch, 0); + STM32_TIM_ENABLEINT(oneshot->tch, 0); /* Enable interrupts. We should get the callback when the interrupt * occurs. @@ -326,7 +326,7 @@ int stm32l4_oneshot_start(struct stm32l4_oneshot_s *oneshot, } /**************************************************************************** - * Name: stm32l4_oneshot_cancel + * Name: stm32_oneshot_cancel * * Description: * Cancel the oneshot timer and return the time remaining on the timer. @@ -337,7 +337,7 @@ int stm32l4_oneshot_start(struct stm32l4_oneshot_s *oneshot, * Input Parameters: * oneshot Caller allocated instance of the oneshot state structure. This * structure must have been previously initialized via a call to - * stm32l4_oneshot_initialize(); + * stm32_oneshot_initialize(); * ts The location in which to return the time remaining on the * oneshot timer. A time of zero is returned if the timer is * not running. ts may be zero in which case the time remaining @@ -350,7 +350,7 @@ int stm32l4_oneshot_start(struct stm32l4_oneshot_s *oneshot, * ****************************************************************************/ -int stm32l4_oneshot_cancel(struct stm32l4_oneshot_s *oneshot, +int stm32_oneshot_cancel(struct stm32_oneshot_s *oneshot, struct timespec *ts) { irqstate_t flags; @@ -389,14 +389,14 @@ int stm32l4_oneshot_cancel(struct stm32l4_oneshot_s *oneshot, tmrinfo("Cancelling...\n"); - count = STM32L4_TIM_GETCOUNTER(oneshot->tch); + count = STM32_TIM_GETCOUNTER(oneshot->tch); period = oneshot->period; /* Now we can disable the interrupt and stop the timer. */ - STM32L4_TIM_DISABLEINT(oneshot->tch, 0); - STM32L4_TIM_SETISR(oneshot->tch, NULL, NULL, 0); - STM32L4_TIM_SETMODE(oneshot->tch, STM32L4_TIM_MODE_DISABLED); + STM32_TIM_DISABLEINT(oneshot->tch, 0); + STM32_TIM_SETISR(oneshot->tch, NULL, NULL, 0); + STM32_TIM_SETMODE(oneshot->tch, STM32_TIM_MODE_DISABLED); oneshot->running = false; oneshot->handler = NULL; @@ -457,4 +457,4 @@ int stm32l4_oneshot_cancel(struct stm32l4_oneshot_s *oneshot, return OK; } -#endif /* CONFIG_STM32L4_ONESHOT */ +#endif /* CONFIG_STM32_ONESHOT */ diff --git a/arch/arm/src/stm32l4/stm32l4_oneshot.h b/arch/arm/src/stm32l4/stm32l4_oneshot.h index 0a7d2ff34d526..d8e77479d2080 100644 --- a/arch/arm/src/stm32l4/stm32l4_oneshot.h +++ b/arch/arm/src/stm32l4/stm32l4_oneshot.h @@ -36,22 +36,22 @@ #include "stm32l4_tim.h" -#ifdef CONFIG_STM32L4_ONESHOT +#ifdef CONFIG_STM32_ONESHOT /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ -#if !defined(CONFIG_STM32L4_ONESHOT_MAXTIMERS) || \ - CONFIG_STM32L4_ONESHOT_MAXTIMERS < 1 -# undef CONFIG_STM32L4_ONESHOT_MAXTIMERS -# define CONFIG_STM32L4_ONESHOT_MAXTIMERS 1 +#if !defined(CONFIG_STM32_ONESHOT_MAXTIMERS) || \ + CONFIG_STM32_ONESHOT_MAXTIMERS < 1 +# undef CONFIG_STM32_ONESHOT_MAXTIMERS +# define CONFIG_STM32_ONESHOT_MAXTIMERS 1 #endif -#if CONFIG_STM32L4_ONESHOT_MAXTIMERS > 8 +#if CONFIG_STM32_ONESHOT_MAXTIMERS > 8 # warning Additional logic required to handle more than 8 timers -# undef CONFIG_STM32L4_ONESHOT_MAXTIMERS -# define CONFIG_STM32L4_ONESHOT_MAXTIMERS 8 +# undef CONFIG_STM32_ONESHOT_MAXTIMERS +# define CONFIG_STM32_ONESHOT_MAXTIMERS 8 #endif /**************************************************************************** @@ -67,20 +67,20 @@ typedef void (*oneshot_handler_t)(void *arg); /* The oneshot client must allocate an instance of this structure and called - * stm32l4_oneshot_initialize() before using the oneshot facilities. The + * stm32_oneshot_initialize() before using the oneshot facilities. The * client should not access the contents of this structure directly since * the contents are subject to change. */ -struct stm32l4_oneshot_s +struct stm32_oneshot_s { uint8_t chan; /* The timer/counter in use */ -#if CONFIG_STM32L4_ONESHOT_MAXTIMERS > 1 +#if CONFIG_STM32_ONESHOT_MAXTIMERS > 1 uint8_t cbndx; /* Timer callback handler index */ #endif volatile bool running; /* True: the timer is running */ - struct stm32l4_tim_dev_s *tch; /* Pointer returned by - * stm32l4_tim_init() */ + struct stm32_tim_dev_s *tch; /* Pointer returned by + * stm32_tim_init() */ volatile oneshot_handler_t handler; /* Oneshot expiration callback */ volatile void *arg; /* The argument that will accompany * the callback */ @@ -106,7 +106,7 @@ extern "C" ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_oneshot_initialize + * Name: stm32_oneshot_initialize * * Description: * Initialize the oneshot timer wrapper @@ -124,22 +124,22 @@ extern "C" * ****************************************************************************/ -int stm32l4_oneshot_initialize(struct stm32l4_oneshot_s *oneshot, int chan, +int stm32_oneshot_initialize(struct stm32_oneshot_s *oneshot, int chan, uint16_t resolution); /**************************************************************************** - * Name: stm32l4_oneshot_max_delay + * Name: stm32_oneshot_max_delay * * Description: * Determine the maximum delay of the one-shot timer (in microseconds) * ****************************************************************************/ -int stm32l4_oneshot_max_delay(struct stm32l4_oneshot_s *oneshot, +int stm32_oneshot_max_delay(struct stm32_oneshot_s *oneshot, uint64_t *usec); /**************************************************************************** - * Name: stm32l4_oneshot_start + * Name: stm32_oneshot_start * * Description: * Start the oneshot timer @@ -147,7 +147,7 @@ int stm32l4_oneshot_max_delay(struct stm32l4_oneshot_s *oneshot, * Input Parameters: * oneshot Caller allocated instance of the oneshot state structure. This * structure must have been previously initialized via a call to - * stm32l4_oneshot_initialize(); + * stm32_oneshot_initialize(); * handler The function to call when when the oneshot timer expires. * arg An opaque argument that will accompany the callback. * ts Provides the duration of the one shot timer. @@ -158,12 +158,12 @@ int stm32l4_oneshot_max_delay(struct stm32l4_oneshot_s *oneshot, * ****************************************************************************/ -int stm32l4_oneshot_start(struct stm32l4_oneshot_s *oneshot, +int stm32_oneshot_start(struct stm32_oneshot_s *oneshot, oneshot_handler_t handler, void *arg, const struct timespec *ts); /**************************************************************************** - * Name: stm32l4_oneshot_cancel + * Name: stm32_oneshot_cancel * * Description: * Cancel the oneshot timer and return the time remaining on the timer. @@ -174,7 +174,7 @@ int stm32l4_oneshot_start(struct stm32l4_oneshot_s *oneshot, * Input Parameters: * oneshot Caller allocated instance of the oneshot state structure. This * structure must have been previously initialized via a call to - * stm32l4_oneshot_initialize(); + * stm32_oneshot_initialize(); * ts The location in which to return the time remaining on the * oneshot timer. A time of zero is returned if the timer is * not running. @@ -186,7 +186,7 @@ int stm32l4_oneshot_start(struct stm32l4_oneshot_s *oneshot, * ****************************************************************************/ -int stm32l4_oneshot_cancel(struct stm32l4_oneshot_s *oneshot, +int stm32_oneshot_cancel(struct stm32_oneshot_s *oneshot, struct timespec *ts); #undef EXTERN @@ -194,5 +194,5 @@ int stm32l4_oneshot_cancel(struct stm32l4_oneshot_s *oneshot, } #endif -#endif /* CONFIG_STM32L4_ONESHOT */ +#endif /* CONFIG_STM32_ONESHOT */ #endif /* __ARCH_ARM_SRC_STM32L4_STM32L4_ONESHOT_H */ diff --git a/arch/arm/src/stm32l4/stm32l4_oneshot_lowerhalf.c b/arch/arm/src/stm32l4/stm32l4_oneshot_lowerhalf.c index 7dd0b0cd73f30..12474e6080762 100644 --- a/arch/arm/src/stm32l4/stm32l4_oneshot_lowerhalf.c +++ b/arch/arm/src/stm32l4/stm32l4_oneshot_lowerhalf.c @@ -45,32 +45,32 @@ * driver */ -struct stm32l4_oneshot_lowerhalf_s +struct stm32_oneshot_lowerhalf_s { /* This is the part of the lower half driver that is visible to the upper- * half client of the driver. This must be the first thing in this * structure so that pointers to struct oneshot_lowerhalf_s are cast - * compatible to struct stm32l4_oneshot_lowerhalf_s and vice versa. + * compatible to struct stm32_oneshot_lowerhalf_s and vice versa. */ struct oneshot_lowerhalf_s lh; /* Common lower-half driver fields */ /* Private lower half data follows */ - struct stm32l4_oneshot_s oneshot; /* STM32-specific oneshot state */ + struct stm32_oneshot_s oneshot; /* STM32-specific oneshot state */ }; /**************************************************************************** * Private Function Prototypes ****************************************************************************/ -static void stm32l4_oneshot_handler(void *arg); +static void stm32_oneshot_handler(void *arg); -static int stm32l4_max_delay(struct oneshot_lowerhalf_s *lower, +static int stm32_max_delay(struct oneshot_lowerhalf_s *lower, struct timespec *ts); -static int stm32l4_start(struct oneshot_lowerhalf_s *lower, +static int stm32_start(struct oneshot_lowerhalf_s *lower, const struct timespec *ts); -static int stm32l4_cancel(struct oneshot_lowerhalf_s *lower, +static int stm32_cancel(struct oneshot_lowerhalf_s *lower, struct timespec *ts); /**************************************************************************** @@ -81,9 +81,9 @@ static int stm32l4_cancel(struct oneshot_lowerhalf_s *lower, static const struct oneshot_operations_s g_oneshot_ops = { - .max_delay = stm32l4_max_delay, - .start = stm32l4_start, - .cancel = stm32l4_cancel, + .max_delay = stm32_max_delay, + .start = stm32_start, + .cancel = stm32_cancel, }; /**************************************************************************** @@ -91,13 +91,13 @@ static const struct oneshot_operations_s g_oneshot_ops = ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_oneshot_handler + * Name: stm32_oneshot_handler * * Description: * Timer expiration handler * * Input Parameters: - * arg - Should be the same argument provided when stm32l4_oneshot_start() + * arg - Should be the same argument provided when stm32_oneshot_start() * was called. * * Returned Value: @@ -105,22 +105,22 @@ static const struct oneshot_operations_s g_oneshot_ops = * ****************************************************************************/ -static void stm32l4_oneshot_handler(void *arg) +static void stm32_oneshot_handler(void *arg) { - struct stm32l4_oneshot_lowerhalf_s *priv = - (struct stm32l4_oneshot_lowerhalf_s *)arg; + struct stm32_oneshot_lowerhalf_s *priv = + (struct stm32_oneshot_lowerhalf_s *)arg; DEBUGASSERT(priv != NULL); /* Perhaps the callback was nullified in a race condition with - * stm32l4_cancel? + * stm32_cancel? */ oneshot_process_callback(&priv->lh); } /**************************************************************************** - * Name: stm32l4_max_delay + * Name: stm32_max_delay * * Description: * Determine the maximum delay of the one-shot timer (in microseconds) @@ -137,16 +137,16 @@ static void stm32l4_oneshot_handler(void *arg) * ****************************************************************************/ -static int stm32l4_max_delay(struct oneshot_lowerhalf_s *lower, +static int stm32_max_delay(struct oneshot_lowerhalf_s *lower, struct timespec *ts) { - struct stm32l4_oneshot_lowerhalf_s *priv = - (struct stm32l4_oneshot_lowerhalf_s *)lower; + struct stm32_oneshot_lowerhalf_s *priv = + (struct stm32_oneshot_lowerhalf_s *)lower; uint64_t usecs; int ret; DEBUGASSERT(priv != NULL && ts != NULL); - ret = stm32l4_oneshot_max_delay(&priv->oneshot, &usecs); + ret = stm32_oneshot_max_delay(&priv->oneshot, &usecs); if (ret >= 0) { uint64_t sec = usecs / 1000000; @@ -160,7 +160,7 @@ static int stm32l4_max_delay(struct oneshot_lowerhalf_s *lower, } /**************************************************************************** - * Name: stm32l4_start + * Name: stm32_start * * Description: * Start the oneshot timer @@ -179,11 +179,11 @@ static int stm32l4_max_delay(struct oneshot_lowerhalf_s *lower, * ****************************************************************************/ -static int stm32l4_start(struct oneshot_lowerhalf_s *lower, +static int stm32_start(struct oneshot_lowerhalf_s *lower, const struct timespec *ts) { - struct stm32l4_oneshot_lowerhalf_s *priv = - (struct stm32l4_oneshot_lowerhalf_s *)lower; + struct stm32_oneshot_lowerhalf_s *priv = + (struct stm32_oneshot_lowerhalf_s *)lower; irqstate_t flags; int ret; @@ -192,20 +192,20 @@ static int stm32l4_start(struct oneshot_lowerhalf_s *lower, /* Save the callback information and start the timer */ flags = enter_critical_section(); - ret = stm32l4_oneshot_start(&priv->oneshot, - stm32l4_oneshot_handler, priv, ts); + ret = stm32_oneshot_start(&priv->oneshot, + stm32_oneshot_handler, priv, ts); leave_critical_section(flags); if (ret < 0) { - tmrerr("ERROR: stm32l4_oneshot_start failed: %d\n", flags); + tmrerr("ERROR: stm32_oneshot_start failed: %d\n", flags); } return ret; } /**************************************************************************** - * Name: stm32l4_cancel + * Name: stm32_cancel * * Description: * Cancel the oneshot timer and return the time remaining on the timer. @@ -228,11 +228,11 @@ static int stm32l4_start(struct oneshot_lowerhalf_s *lower, * ****************************************************************************/ -static int stm32l4_cancel(struct oneshot_lowerhalf_s *lower, +static int stm32_cancel(struct oneshot_lowerhalf_s *lower, struct timespec *ts) { - struct stm32l4_oneshot_lowerhalf_s *priv = - (struct stm32l4_oneshot_lowerhalf_s *)lower; + struct stm32_oneshot_lowerhalf_s *priv = + (struct stm32_oneshot_lowerhalf_s *)lower; irqstate_t flags; int ret; @@ -241,12 +241,12 @@ static int stm32l4_cancel(struct oneshot_lowerhalf_s *lower, /* Cancel the timer */ flags = enter_critical_section(); - ret = stm32l4_oneshot_cancel(&priv->oneshot, ts); + ret = stm32_oneshot_cancel(&priv->oneshot, ts); leave_critical_section(flags); if (ret < 0) { - tmrerr("ERROR: stm32l4_oneshot_cancel failed: %d\n", flags); + tmrerr("ERROR: stm32_oneshot_cancel failed: %d\n", flags); } return ret; @@ -278,13 +278,13 @@ static int stm32l4_cancel(struct oneshot_lowerhalf_s *lower, struct oneshot_lowerhalf_s *oneshot_initialize(int chan, uint16_t resolution) { - struct stm32l4_oneshot_lowerhalf_s *priv; + struct stm32_oneshot_lowerhalf_s *priv; int ret; /* Allocate an instance of the lower half driver */ - priv = (struct stm32l4_oneshot_lowerhalf_s *) - kmm_zalloc(sizeof(struct stm32l4_oneshot_lowerhalf_s)); + priv = (struct stm32_oneshot_lowerhalf_s *) + kmm_zalloc(sizeof(struct stm32_oneshot_lowerhalf_s)); if (priv == NULL) { @@ -298,10 +298,10 @@ struct oneshot_lowerhalf_s *oneshot_initialize(int chan, /* Initialize the contained STM32 oneshot timer */ - ret = stm32l4_oneshot_initialize(&priv->oneshot, chan, resolution); + ret = stm32_oneshot_initialize(&priv->oneshot, chan, resolution); if (ret < 0) { - tmrerr("ERROR: stm32l4_oneshot_initialize failed: %d\n", ret); + tmrerr("ERROR: stm32_oneshot_initialize failed: %d\n", ret); kmm_free(priv); return NULL; } diff --git a/arch/arm/src/stm32l4/stm32l4_otgfs.h b/arch/arm/src/stm32l4/stm32l4_otgfs.h index bce7dcc074286..9a930afa96238 100644 --- a/arch/arm/src/stm32l4/stm32l4_otgfs.h +++ b/arch/arm/src/stm32l4/stm32l4_otgfs.h @@ -31,13 +31,13 @@ #include -#include "stm32l4.h" +#include "stm32.h" -#if defined(CONFIG_STM32L4_OTGFS) +#if defined(CONFIG_STM32_OTGFS) -#if defined(CONFIG_STM32L4_STM32L4X5) +#if defined(CONFIG_STM32_STM32L4X5) # include "hardware/stm32l4x5xx_otgfs.h" -#elif defined(CONFIG_STM32L4_STM32L4X6) || defined(CONFIG_STM32L4_STM32L4XR) +#elif defined(CONFIG_STM32_STM32L4X6) || defined(CONFIG_STM32_STM32L4XR) # include "hardware/stm32l4x6xx_otgfs.h" #else # error "Unsupported STM32L4 chip" @@ -49,7 +49,7 @@ /* Number of endpoints */ -#define STM32L4_NENDPOINTS (6) /* ep0-5 x 2 for IN and OUT */ +#define STM32_NENDPOINTS (6) /* ep0-5 x 2 for IN and OUT */ /**************************************************************************** * Public Functions Prototypes @@ -67,7 +67,7 @@ extern "C" #endif /**************************************************************************** - * Name: stm32l4_otgfshost_initialize + * Name: stm32_otgfshost_initialize * * Description: * Initialize USB host device controller hardware. @@ -94,21 +94,21 @@ extern "C" #ifdef CONFIG_USBHOST struct usbhost_connection_s; struct -usbhost_connection_s *stm32l4_otgfshost_initialize(int controller); +usbhost_connection_s *stm32_otgfshost_initialize(int controller); #endif /**************************************************************************** - * Name: stm32l4_usbsuspend + * Name: stm32_usbsuspend * * Description: - * Board logic must provide the stm32l4_usbsuspend logic if the OTG FS + * Board logic must provide the stm32_usbsuspend logic if the OTG FS * device driver is used. This function is called whenever the USB enters * or leaves suspend mode. This is an opportunity for the board logic to * shutdown clocks, power, etc. while the USB is suspended. * ****************************************************************************/ -void stm32l4_usbsuspend(struct usbdev_s *dev, bool resume); +void stm32_usbsuspend(struct usbdev_s *dev, bool resume); #undef EXTERN #if defined(__cplusplus) @@ -116,5 +116,5 @@ void stm32l4_usbsuspend(struct usbdev_s *dev, bool resume); #endif #endif /* __ASSEMBLY__ */ -#endif /* CONFIG_STM32L4_OTGFS */ +#endif /* CONFIG_STM32_OTGFS */ #endif /* __ARCH_ARM_SRC_STM32L4_STM32L4_OTGFS_H */ diff --git a/arch/arm/src/stm32l4/stm32l4_otgfsdev.c b/arch/arm/src/stm32l4/stm32l4_otgfsdev.c index cfaf97f447309..af2df0c32ada4 100644 --- a/arch/arm/src/stm32l4/stm32l4_otgfsdev.c +++ b/arch/arm/src/stm32l4/stm32l4_otgfsdev.c @@ -50,7 +50,7 @@ #include "stm32l4_otgfs.h" #include "stm32l4_pwr.h" -#if defined(CONFIG_USBDEV) && (defined(CONFIG_STM32L4_OTGFS)) +#if defined(CONFIG_USBDEV) && (defined(CONFIG_STM32_OTGFS)) /**************************************************************************** * Pre-processor Definitions @@ -58,8 +58,8 @@ /* Configuration ************************************************************/ -#ifndef CONFIG_STM32L4_SYSCFG -# error "CONFIG_STM32L4_SYSCFG is required" +#ifndef CONFIG_STM32_SYSCFG +# error "CONFIG_STM32_SYSCFG is required" #endif #ifndef CONFIG_USBDEV_EP0_MAXSIZE @@ -115,8 +115,8 @@ */ #if CONFIG_USBDEV_EP1_TXFIFO_SIZE == 0 -# undef STM32L4_NENDPOINTS -# define STM32L4_NENDPOINTS 1 +# undef STM32_NENDPOINTS +# define STM32_NENDPOINTS 1 # undef CONFIG_USBDEV_EP2_TXFIFO_SIZE # define CONFIG_USBDEV_EP2_TXFIFO_SIZE 0 # undef CONFIG_USBDEV_EP3_TXFIFO_SIZE @@ -126,8 +126,8 @@ # undef CONFIG_USBDEV_EP5_TXFIFO_SIZE # define CONFIG_USBDEV_EP5_TXFIFO_SIZE 0 #elif CONFIG_USBDEV_EP2_TXFIFO_SIZE == 0 -# undef STM32L4_NENDPOINTS -# define STM32L4_NENDPOINTS 2 +# undef STM32_NENDPOINTS +# define STM32_NENDPOINTS 2 # undef CONFIG_USBDEV_EP3_TXFIFO_SIZE # define CONFIG_USBDEV_EP3_TXFIFO_SIZE 0 # undef CONFIG_USBDEV_EP4_TXFIFO_SIZE @@ -135,20 +135,20 @@ # undef CONFIG_USBDEV_EP5_TXFIFO_SIZE # define CONFIG_USBDEV_EP5_TXFIFO_SIZE 0 #elif CONFIG_USBDEV_EP3_TXFIFO_SIZE == 0 -# undef STM32L4_NENDPOINTS -# define STM32L4_NENDPOINTS 3 +# undef STM32_NENDPOINTS +# define STM32_NENDPOINTS 3 # undef CONFIG_USBDEV_EP4_TXFIFO_SIZE # define CONFIG_USBDEV_EP4_TXFIFO_SIZE 0 # undef CONFIG_USBDEV_EP5_TXFIFO_SIZE # define CONFIG_USBDEV_EP5_TXFIFO_SIZE 0 #elif CONFIG_USBDEV_EP4_TXFIFO_SIZE == 0 -# undef STM32L4_NENDPOINTS -# define STM32L4_NENDPOINTS 4 +# undef STM32_NENDPOINTS +# define STM32_NENDPOINTS 4 # undef CONFIG_USBDEV_EP5_TXFIFO_SIZE # define CONFIG_USBDEV_EP5_TXFIFO_SIZE 0 #elif CONFIG_USBDEV_EP5_TXFIFO_SIZE == 0 -# undef STM32L4_NENDPOINTS -# define STM32L4_NENDPOINTS 5 +# undef STM32_NENDPOINTS +# define STM32_NENDPOINTS 5 #endif /* Sanity check on allocations specified. */ @@ -168,48 +168,48 @@ * boundaries; FIFO sizes must be provided in units of 32-bit words. */ -#define STM32L4_RXFIFO_BYTES ((CONFIG_USBDEV_RXFIFO_SIZE + 3) & ~3) -#define STM32L4_RXFIFO_WORDS ((CONFIG_USBDEV_RXFIFO_SIZE + 3) >> 2) +#define STM32_RXFIFO_BYTES ((CONFIG_USBDEV_RXFIFO_SIZE + 3) & ~3) +#define STM32_RXFIFO_WORDS ((CONFIG_USBDEV_RXFIFO_SIZE + 3) >> 2) -#define STM32L4_EP0_TXFIFO_BYTES ((CONFIG_USBDEV_EP0_TXFIFO_SIZE + 3) & ~3) -#define STM32L4_EP0_TXFIFO_WORDS ((CONFIG_USBDEV_EP0_TXFIFO_SIZE + 3) >> 2) +#define STM32_EP0_TXFIFO_BYTES ((CONFIG_USBDEV_EP0_TXFIFO_SIZE + 3) & ~3) +#define STM32_EP0_TXFIFO_WORDS ((CONFIG_USBDEV_EP0_TXFIFO_SIZE + 3) >> 2) -#if STM32L4_EP0_TXFIFO_WORDS < 16 || STM32L4_EP0_TXFIFO_WORDS > 256 +#if STM32_EP0_TXFIFO_WORDS < 16 || STM32_EP0_TXFIFO_WORDS > 256 # error "CONFIG_USBDEV_EP0_TXFIFO_SIZE is out of range" #endif -#define STM32L4_EP1_TXFIFO_BYTES ((CONFIG_USBDEV_EP1_TXFIFO_SIZE + 3) & ~3) -#define STM32L4_EP1_TXFIFO_WORDS ((CONFIG_USBDEV_EP1_TXFIFO_SIZE + 3) >> 2) +#define STM32_EP1_TXFIFO_BYTES ((CONFIG_USBDEV_EP1_TXFIFO_SIZE + 3) & ~3) +#define STM32_EP1_TXFIFO_WORDS ((CONFIG_USBDEV_EP1_TXFIFO_SIZE + 3) >> 2) -#if STM32L4_EP1_TXFIFO_BYTES != 0 && STM32L4_EP1_TXFIFO_WORDS < 16 +#if STM32_EP1_TXFIFO_BYTES != 0 && STM32_EP1_TXFIFO_WORDS < 16 # error "CONFIG_USBDEV_EP1_TXFIFO_SIZE is out of range" #endif -#define STM32L4_EP2_TXFIFO_BYTES ((CONFIG_USBDEV_EP2_TXFIFO_SIZE + 3) & ~3) -#define STM32L4_EP2_TXFIFO_WORDS ((CONFIG_USBDEV_EP2_TXFIFO_SIZE + 3) >> 2) +#define STM32_EP2_TXFIFO_BYTES ((CONFIG_USBDEV_EP2_TXFIFO_SIZE + 3) & ~3) +#define STM32_EP2_TXFIFO_WORDS ((CONFIG_USBDEV_EP2_TXFIFO_SIZE + 3) >> 2) -#if STM32L4_EP2_TXFIFO_BYTES != 0 && STM32L4_EP2_TXFIFO_WORDS < 16 +#if STM32_EP2_TXFIFO_BYTES != 0 && STM32_EP2_TXFIFO_WORDS < 16 # error "CONFIG_USBDEV_EP2_TXFIFO_SIZE is out of range" #endif -#define STM32L4_EP3_TXFIFO_BYTES ((CONFIG_USBDEV_EP3_TXFIFO_SIZE + 3) & ~3) -#define STM32L4_EP3_TXFIFO_WORDS ((CONFIG_USBDEV_EP3_TXFIFO_SIZE + 3) >> 2) +#define STM32_EP3_TXFIFO_BYTES ((CONFIG_USBDEV_EP3_TXFIFO_SIZE + 3) & ~3) +#define STM32_EP3_TXFIFO_WORDS ((CONFIG_USBDEV_EP3_TXFIFO_SIZE + 3) >> 2) -#if STM32L4_EP3_TXFIFO_BYTES != 0 && STM32L4_EP3_TXFIFO_WORDS < 16 +#if STM32_EP3_TXFIFO_BYTES != 0 && STM32_EP3_TXFIFO_WORDS < 16 # error "CONFIG_USBDEV_EP3_TXFIFO_SIZE is out of range" #endif -#define STM32L4_EP4_TXFIFO_BYTES ((CONFIG_USBDEV_EP4_TXFIFO_SIZE + 3) & ~3) -#define STM32L4_EP4_TXFIFO_WORDS ((CONFIG_USBDEV_EP4_TXFIFO_SIZE + 3) >> 2) +#define STM32_EP4_TXFIFO_BYTES ((CONFIG_USBDEV_EP4_TXFIFO_SIZE + 3) & ~3) +#define STM32_EP4_TXFIFO_WORDS ((CONFIG_USBDEV_EP4_TXFIFO_SIZE + 3) >> 2) -#if STM32L4_EP4_TXFIFO_BYTES != 0 && STM32L4_EP4_TXFIFO_WORDS < 16 +#if STM32_EP4_TXFIFO_BYTES != 0 && STM32_EP4_TXFIFO_WORDS < 16 # error "CONFIG_USBDEV_EP4_TXFIFO_SIZE is out of range" #endif -#define STM32L4_EP5_TXFIFO_BYTES ((CONFIG_USBDEV_EP5_TXFIFO_SIZE + 3) & ~3) -#define STM32L4_EP5_TXFIFO_WORDS ((CONFIG_USBDEV_EP5_TXFIFO_SIZE + 3) >> 2) +#define STM32_EP5_TXFIFO_BYTES ((CONFIG_USBDEV_EP5_TXFIFO_SIZE + 3) & ~3) +#define STM32_EP5_TXFIFO_WORDS ((CONFIG_USBDEV_EP5_TXFIFO_SIZE + 3) >> 2) -#if STM32L4_EP5_TXFIFO_BYTES != 0 && STM32L4_EP5_TXFIFO_WORDS < 16 +#if STM32_EP5_TXFIFO_BYTES != 0 && STM32_EP5_TXFIFO_WORDS < 16 # error "CONFIG_USBDEV_EP5_TXFIFO_SIZE is out of range" #endif @@ -238,95 +238,95 @@ /* Trace error codes */ -#define STM32L4_TRACEERR_ALLOCFAIL 0x01 -#define STM32L4_TRACEERR_BADCLEARFEATURE 0x02 -#define STM32L4_TRACEERR_BADDEVGETSTATUS 0x03 -#define STM32L4_TRACEERR_BADEPNO 0x04 -#define STM32L4_TRACEERR_BADEPGETSTATUS 0x05 -#define STM32L4_TRACEERR_BADGETCONFIG 0x06 -#define STM32L4_TRACEERR_BADGETSETDESC 0x07 -#define STM32L4_TRACEERR_BADGETSTATUS 0x08 -#define STM32L4_TRACEERR_BADSETADDRESS 0x09 -#define STM32L4_TRACEERR_BADSETCONFIG 0x0a -#define STM32L4_TRACEERR_BADSETFEATURE 0x0b -#define STM32L4_TRACEERR_BADTESTMODE 0x0c -#define STM32L4_TRACEERR_BINDFAILED 0x0d -#define STM32L4_TRACEERR_DISPATCHSTALL 0x0e -#define STM32L4_TRACEERR_DRIVER 0x0f -#define STM32L4_TRACEERR_DRIVERREGISTERED 0x10 -#define STM32L4_TRACEERR_EP0NOSETUP 0x11 -#define STM32L4_TRACEERR_EP0SETUPSTALLED 0x12 -#define STM32L4_TRACEERR_EPINNULLPACKET 0x13 -#define STM32L4_TRACEERR_EPINUNEXPECTED 0x14 -#define STM32L4_TRACEERR_EPOUTNULLPACKET 0x15 -#define STM32L4_TRACEERR_EPOUTUNEXPECTED 0x16 -#define STM32L4_TRACEERR_INVALIDCTRLREQ 0x17 -#define STM32L4_TRACEERR_INVALIDPARMS 0x18 -#define STM32L4_TRACEERR_IRQREGISTRATION 0x19 -#define STM32L4_TRACEERR_NOEP 0x1a -#define STM32L4_TRACEERR_NOTCONFIGURED 0x1b -#define STM32L4_TRACEERR_EPOUTQEMPTY 0x1c -#define STM32L4_TRACEERR_EPINREQEMPTY 0x1d -#define STM32L4_TRACEERR_NOOUTSETUP 0x1e -#define STM32L4_TRACEERR_POLLTIMEOUT 0x1f +#define STM32_TRACEERR_ALLOCFAIL 0x01 +#define STM32_TRACEERR_BADCLEARFEATURE 0x02 +#define STM32_TRACEERR_BADDEVGETSTATUS 0x03 +#define STM32_TRACEERR_BADEPNO 0x04 +#define STM32_TRACEERR_BADEPGETSTATUS 0x05 +#define STM32_TRACEERR_BADGETCONFIG 0x06 +#define STM32_TRACEERR_BADGETSETDESC 0x07 +#define STM32_TRACEERR_BADGETSTATUS 0x08 +#define STM32_TRACEERR_BADSETADDRESS 0x09 +#define STM32_TRACEERR_BADSETCONFIG 0x0a +#define STM32_TRACEERR_BADSETFEATURE 0x0b +#define STM32_TRACEERR_BADTESTMODE 0x0c +#define STM32_TRACEERR_BINDFAILED 0x0d +#define STM32_TRACEERR_DISPATCHSTALL 0x0e +#define STM32_TRACEERR_DRIVER 0x0f +#define STM32_TRACEERR_DRIVERREGISTERED 0x10 +#define STM32_TRACEERR_EP0NOSETUP 0x11 +#define STM32_TRACEERR_EP0SETUPSTALLED 0x12 +#define STM32_TRACEERR_EPINNULLPACKET 0x13 +#define STM32_TRACEERR_EPINUNEXPECTED 0x14 +#define STM32_TRACEERR_EPOUTNULLPACKET 0x15 +#define STM32_TRACEERR_EPOUTUNEXPECTED 0x16 +#define STM32_TRACEERR_INVALIDCTRLREQ 0x17 +#define STM32_TRACEERR_INVALIDPARMS 0x18 +#define STM32_TRACEERR_IRQREGISTRATION 0x19 +#define STM32_TRACEERR_NOEP 0x1a +#define STM32_TRACEERR_NOTCONFIGURED 0x1b +#define STM32_TRACEERR_EPOUTQEMPTY 0x1c +#define STM32_TRACEERR_EPINREQEMPTY 0x1d +#define STM32_TRACEERR_NOOUTSETUP 0x1e +#define STM32_TRACEERR_POLLTIMEOUT 0x1f /* Trace interrupt codes */ -#define STM32L4_TRACEINTID_USB 1 /* USB Interrupt entry/exit */ -#define STM32L4_TRACEINTID_INTPENDING 2 /* On each pass through the loop */ - -#define STM32L4_TRACEINTID_EPOUT (10 + 0) /* First level interrupt decode */ -#define STM32L4_TRACEINTID_EPIN (10 + 1) -#define STM32L4_TRACEINTID_MISMATCH (10 + 2) -#define STM32L4_TRACEINTID_WAKEUP (10 + 3) -#define STM32L4_TRACEINTID_SUSPEND (10 + 4) -#define STM32L4_TRACEINTID_SOF (10 + 5) -#define STM32L4_TRACEINTID_RXFIFO (10 + 6) -#define STM32L4_TRACEINTID_DEVRESET (10 + 7) -#define STM32L4_TRACEINTID_ENUMDNE (10 + 8) -#define STM32L4_TRACEINTID_IISOIXFR (10 + 9) -#define STM32L4_TRACEINTID_IISOOXFR (10 + 10) -#define STM32L4_TRACEINTID_SRQ (10 + 11) -#define STM32L4_TRACEINTID_OTG (10 + 12) - -#define STM32L4_TRACEINTID_EPOUT_XFRC (40 + 0) /* EPOUT second level decode */ -#define STM32L4_TRACEINTID_EPOUT_EPDISD (40 + 1) -#define STM32L4_TRACEINTID_EPOUT_SETUP (40 + 2) -#define STM32L4_TRACEINTID_DISPATCH (40 + 3) - -#define STM32L4_TRACEINTID_GETSTATUS (50 + 0) /* EPOUT third level decode */ -#define STM32L4_TRACEINTID_EPGETSTATUS (50 + 1) -#define STM32L4_TRACEINTID_DEVGETSTATUS (50 + 2) -#define STM32L4_TRACEINTID_IFGETSTATUS (50 + 3) -#define STM32L4_TRACEINTID_CLEARFEATURE (50 + 4) -#define STM32L4_TRACEINTID_SETFEATURE (50 + 5) -#define STM32L4_TRACEINTID_SETADDRESS (50 + 6) -#define STM32L4_TRACEINTID_GETSETDESC (50 + 7) -#define STM32L4_TRACEINTID_GETCONFIG (50 + 8) -#define STM32L4_TRACEINTID_SETCONFIG (50 + 9) -#define STM32L4_TRACEINTID_GETSETIF (50 + 10) -#define STM32L4_TRACEINTID_SYNCHFRAME (50 + 11) - -#define STM32L4_TRACEINTID_EPIN_XFRC (70 + 0) /* EPIN second level decode */ -#define STM32L4_TRACEINTID_EPIN_TOC (70 + 1) -#define STM32L4_TRACEINTID_EPIN_ITTXFE (70 + 2) -#define STM32L4_TRACEINTID_EPIN_EPDISD (70 + 3) -#define STM32L4_TRACEINTID_EPIN_TXFE (70 + 4) - -#define STM32L4_TRACEINTID_EPIN_EMPWAIT (80 + 0) /* EPIN second level decode */ - -#define STM32L4_TRACEINTID_OUTNAK (90 + 0) /* RXFLVL second level decode */ -#define STM32L4_TRACEINTID_OUTRECVD (90 + 1) -#define STM32L4_TRACEINTID_OUTDONE (90 + 2) -#define STM32L4_TRACEINTID_SETUPDONE (90 + 3) -#define STM32L4_TRACEINTID_SETUPRECVD (90 + 4) +#define STM32_TRACEINTID_USB 1 /* USB Interrupt entry/exit */ +#define STM32_TRACEINTID_INTPENDING 2 /* On each pass through the loop */ + +#define STM32_TRACEINTID_EPOUT (10 + 0) /* First level interrupt decode */ +#define STM32_TRACEINTID_EPIN (10 + 1) +#define STM32_TRACEINTID_MISMATCH (10 + 2) +#define STM32_TRACEINTID_WAKEUP (10 + 3) +#define STM32_TRACEINTID_SUSPEND (10 + 4) +#define STM32_TRACEINTID_SOF (10 + 5) +#define STM32_TRACEINTID_RXFIFO (10 + 6) +#define STM32_TRACEINTID_DEVRESET (10 + 7) +#define STM32_TRACEINTID_ENUMDNE (10 + 8) +#define STM32_TRACEINTID_IISOIXFR (10 + 9) +#define STM32_TRACEINTID_IISOOXFR (10 + 10) +#define STM32_TRACEINTID_SRQ (10 + 11) +#define STM32_TRACEINTID_OTG (10 + 12) + +#define STM32_TRACEINTID_EPOUT_XFRC (40 + 0) /* EPOUT second level decode */ +#define STM32_TRACEINTID_EPOUT_EPDISD (40 + 1) +#define STM32_TRACEINTID_EPOUT_SETUP (40 + 2) +#define STM32_TRACEINTID_DISPATCH (40 + 3) + +#define STM32_TRACEINTID_GETSTATUS (50 + 0) /* EPOUT third level decode */ +#define STM32_TRACEINTID_EPGETSTATUS (50 + 1) +#define STM32_TRACEINTID_DEVGETSTATUS (50 + 2) +#define STM32_TRACEINTID_IFGETSTATUS (50 + 3) +#define STM32_TRACEINTID_CLEARFEATURE (50 + 4) +#define STM32_TRACEINTID_SETFEATURE (50 + 5) +#define STM32_TRACEINTID_SETADDRESS (50 + 6) +#define STM32_TRACEINTID_GETSETDESC (50 + 7) +#define STM32_TRACEINTID_GETCONFIG (50 + 8) +#define STM32_TRACEINTID_SETCONFIG (50 + 9) +#define STM32_TRACEINTID_GETSETIF (50 + 10) +#define STM32_TRACEINTID_SYNCHFRAME (50 + 11) + +#define STM32_TRACEINTID_EPIN_XFRC (70 + 0) /* EPIN second level decode */ +#define STM32_TRACEINTID_EPIN_TOC (70 + 1) +#define STM32_TRACEINTID_EPIN_ITTXFE (70 + 2) +#define STM32_TRACEINTID_EPIN_EPDISD (70 + 3) +#define STM32_TRACEINTID_EPIN_TXFE (70 + 4) + +#define STM32_TRACEINTID_EPIN_EMPWAIT (80 + 0) /* EPIN second level decode */ + +#define STM32_TRACEINTID_OUTNAK (90 + 0) /* RXFLVL second level decode */ +#define STM32_TRACEINTID_OUTRECVD (90 + 1) +#define STM32_TRACEINTID_OUTDONE (90 + 2) +#define STM32_TRACEINTID_SETUPDONE (90 + 3) +#define STM32_TRACEINTID_SETUPRECVD (90 + 4) /* Endpoints ****************************************************************/ /* Odd physical endpoint numbers are IN; even are OUT */ -#define STM32L4_EPPHYIN2LOG(epphy) ((uint8_t)(epphy)|USB_DIR_IN) -#define STM32L4_EPPHYOUT2LOG(epphy) ((uint8_t)(epphy)|USB_DIR_OUT) +#define STM32_EPPHYIN2LOG(epphy) ((uint8_t)(epphy)|USB_DIR_IN) +#define STM32_EPPHYOUT2LOG(epphy) ((uint8_t)(epphy)|USB_DIR_OUT) /* Endpoint 0 */ @@ -336,21 +336,21 @@ * This is a bitmap, and the first endpoint (0) is reserved. */ -#define STM32L4_EP_AVAILABLE (((1 << STM32L4_NENDPOINTS) - 1) & ~1) +#define STM32_EP_AVAILABLE (((1 << STM32_NENDPOINTS) - 1) & ~1) /* Maximum packet sizes for full speed endpoints */ -#define STM32L4_MAXPACKET (64) /* Max packet size (1-64) */ +#define STM32_MAXPACKET (64) /* Max packet size (1-64) */ /* Delays *******************************************************************/ -#define STM32L4_READY_DELAY 200000 -#define STM32L4_FLUSH_DELAY 200000 +#define STM32_READY_DELAY 200000 +#define STM32_FLUSH_DELAY 200000 /* Request queue operations *************************************************/ -#define stm32l4_rqempty(ep) ((ep)->head == NULL) -#define stm32l4_rqpeek(ep) ((ep)->head) +#define stm32_rqempty(ep) ((ep)->head == NULL) +#define stm32_rqpeek(ep) ((ep)->head) /**************************************************************************** * Private Types @@ -358,7 +358,7 @@ /* Overall device state */ -enum stm32l4_devstate_e +enum stm32_devstate_e { DEVSTATE_DEFAULT = 0, /* Power-up, unconfigured state. This state simply * means that the device is not yet been given an @@ -385,11 +385,11 @@ enum stm32l4_devstate_e /* Endpoint 0 states */ -enum stm32l4_ep0state_e +enum stm32_ep0state_e { EP0STATE_IDLE = 0, /* Idle State, leave on receiving a SETUP packet or * epsubmit: - * SET: In stm32l4_epin() and stm32l4_epout() when + * SET: In stm32_epin() and stm32_epout() when * we revert from request processing to * SETUP processing. * TESTED: Never @@ -397,51 +397,51 @@ enum stm32l4_ep0state_e EP0STATE_SETUP_OUT, /* OUT SETUP packet received. Waiting for the DATA * OUT phase of SETUP Packet to complete before * processing a SETUP command (without a USB request): - * SET: Set in stm32l4_rxinterrupt() when SETUP OUT + * SET: Set in stm32_rxinterrupt() when SETUP OUT * packet is received. - * TESTED: In stm32l4_ep0out_receive() + * TESTED: In stm32_ep0out_receive() */ EP0STATE_SETUP_READY, /* IN SETUP packet received -OR- OUT SETUP packet and * accompanying data have been received. Processing * of SETUP command will happen soon. - * SET: (1) stm32l4_ep0out_receive() when the OUT + * SET: (1) stm32_ep0out_receive() when the OUT * SETUP data phase completes, or (2) - * stm32l4_rxinterrupt() when an IN SETUP is + * stm32_rxinterrupt() when an IN SETUP is * packet received. - * TESTED: Tested in stm32l4_epout_interrupt() when + * TESTED: Tested in stm32_epout_interrupt() when * SETUP phase is done to see if the SETUP * command is ready to be processed. Also - * tested in stm32l4_ep0out_setup() just to + * tested in stm32_ep0out_setup() just to * double-check that we have a SETUP request * and any accompanying data. */ - EP0STATE_SETUP_PROCESS, /* SETUP Packet is being processed by stm32l4_ep0out_setup(): + EP0STATE_SETUP_PROCESS, /* SETUP Packet is being processed by stm32_ep0out_setup(): * SET: When SETUP packet received in EP0 OUT * TESTED: Never */ EP0STATE_SETUPRESPONSE, /* Short SETUP response write (without a USB request): * SET: When SETUP response is sent by - * stm32l4_ep0in_setupresponse() + * stm32_ep0in_setupresponse() * TESTED: Never */ EP0STATE_DATA_IN, /* Waiting for data out stage (with a USB request): - * SET: In stm32l4_epin_request() when a write + * SET: In stm32_epin_request() when a write * request is processed on EP0. - * TESTED: In stm32l4_epin() to see if we should + * TESTED: In stm32_epin() to see if we should * revert to SETUP processing. */ EP0STATE_DATA_OUT /* Waiting for data in phase to complete ( with a * USB request) - * SET: In stm32l4_epout_request() when a read + * SET: In stm32_epout_request() when a read * request is processed on EP0. - * TESTED: In stm32l4_epout() to see if we should + * TESTED: In stm32_epout() to see if we should * revert to SETUP processing */ }; /* Parsed control request */ -struct stm32l4_ctrlreq_s +struct stm32_ctrlreq_s { uint8_t type; uint8_t req; @@ -452,28 +452,28 @@ struct stm32l4_ctrlreq_s /* A container for a request so that the request may be retained in a list */ -struct stm32l4_req_s +struct stm32_req_s { struct usbdev_req_s req; /* Standard USB request */ - struct stm32l4_req_s *flink; /* Supports a singly linked list */ + struct stm32_req_s *flink; /* Supports a singly linked list */ }; /* This is the internal representation of an endpoint */ -struct stm32l4_ep_s +struct stm32_ep_s { /* Common endpoint fields. This must be the first thing defined in the * structure so that it is possible to simply cast from struct usbdev_ep_s - * to struct stm32l4_ep_s. + * to struct stm32_ep_s. */ struct usbdev_ep_s ep; /* Standard endpoint structure */ /* STM32-specific fields */ - struct stm32l4_usbdev_s *dev; /* Reference to private driver data */ - struct stm32l4_req_s *head; /* Request list for this endpoint */ - struct stm32l4_req_s *tail; + struct stm32_usbdev_s *dev; /* Reference to private driver data */ + struct stm32_req_s *head; /* Request list for this endpoint */ + struct stm32_req_s *tail; uint8_t epphy; /* Physical EP address */ uint8_t eptype:2; /* Endpoint type */ uint8_t active:1; /* 1: A request is being processed */ @@ -485,11 +485,11 @@ struct stm32l4_ep_s /* This structure retains the state of the USB device controller */ -struct stm32l4_usbdev_s +struct stm32_usbdev_s { /* Common device fields. This must be the first thing defined in the * structure so that it is possible to simply cast from struct usbdev_s - * to struct stm32l4_usbdev_s. + * to struct stm32_usbdev_s. */ struct usbdev_s usbdev; @@ -507,8 +507,8 @@ struct stm32l4_usbdev_s uint8_t wakeup:1; /* 1: Device remote wake-up */ uint8_t dotest:1; /* 1: Test mode selected */ - uint8_t devstate:4; /* See enum stm32l4_devstate_e */ - uint8_t ep0state:4; /* See enum stm32l4_ep0state_e */ + uint8_t devstate:4; /* See enum stm32_devstate_e */ + uint8_t ep0state:4; /* See enum stm32_ep0state_e */ uint8_t testmode:4; /* Selected test mode */ uint8_t epavail[2]; /* Bitset of available OUT/IN endpoints */ @@ -538,8 +538,8 @@ struct stm32l4_usbdev_s /* The endpoint lists */ - struct stm32l4_ep_s epin[STM32L4_NENDPOINTS]; - struct stm32l4_ep_s epout[STM32L4_NENDPOINTS]; + struct stm32_ep_s epin[STM32_NENDPOINTS]; + struct stm32_ep_s epout[STM32_NENDPOINTS]; }; /**************************************************************************** @@ -548,204 +548,204 @@ struct stm32l4_usbdev_s /* Register operations ******************************************************/ -#if defined(CONFIG_STM32L4_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES) -static uint32_t stm32l4_getreg(uint32_t addr); -static void stm32l4_putreg(uint32_t val, uint32_t addr); +#if defined(CONFIG_STM32_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES) +static uint32_t stm32_getreg(uint32_t addr); +static void stm32_putreg(uint32_t val, uint32_t addr); #else -# define stm32l4_getreg(addr) getreg32(addr) -# define stm32l4_putreg(val,addr) putreg32(val,addr) +# define stm32_getreg(addr) getreg32(addr) +# define stm32_putreg(val,addr) putreg32(val,addr) #endif /* Request queue operations *************************************************/ static struct -stm32l4_req_s *stm32l4_req_remfirst(struct stm32l4_ep_s *privep); -static bool stm32l4_req_addlast(struct stm32l4_ep_s *privep, - struct stm32l4_req_s *req); +stm32_req_s *stm32_req_remfirst(struct stm32_ep_s *privep); +static bool stm32_req_addlast(struct stm32_ep_s *privep, + struct stm32_req_s *req); /* Low level data transfers and request operations **************************/ /* Special endpoint 0 data transfer logic */ static -void stm32l4_ep0in_setupresponse(struct stm32l4_usbdev_s *priv, +void stm32_ep0in_setupresponse(struct stm32_usbdev_s *priv, uint8_t *data, uint32_t nbytes); static inline -void stm32l4_ep0in_transmitzlp(struct stm32l4_usbdev_s *priv); -static void stm32l4_ep0in_activate(void); +void stm32_ep0in_transmitzlp(struct stm32_usbdev_s *priv); +static void stm32_ep0in_activate(void); static -void stm32l4_ep0out_ctrlsetup(struct stm32l4_usbdev_s *priv); +void stm32_ep0out_ctrlsetup(struct stm32_usbdev_s *priv); /* IN request and TxFIFO handling */ -static void stm32l4_txfifo_write(struct stm32l4_ep_s *privep, +static void stm32_txfifo_write(struct stm32_ep_s *privep, uint8_t *buf, int nbytes); -static void stm32l4_epin_transfer(struct stm32l4_ep_s *privep, +static void stm32_epin_transfer(struct stm32_ep_s *privep, uint8_t *buf, int nbytes); -static void stm32l4_epin_request(struct stm32l4_usbdev_s *priv, - struct stm32l4_ep_s *privep); +static void stm32_epin_request(struct stm32_usbdev_s *priv, + struct stm32_ep_s *privep); /* OUT request and RxFIFO handling */ -static void stm32l4_rxfifo_read(struct stm32l4_ep_s *privep, +static void stm32_rxfifo_read(struct stm32_ep_s *privep, uint8_t *dest, uint16_t len); -static void stm32l4_rxfifo_discard(struct stm32l4_ep_s *privep, +static void stm32_rxfifo_discard(struct stm32_ep_s *privep, int len); -static void stm32l4_epout_complete(struct stm32l4_usbdev_s *priv, - struct stm32l4_ep_s *privep); -static inline void stm32l4_ep0out_receive(struct stm32l4_ep_s *privep, +static void stm32_epout_complete(struct stm32_usbdev_s *priv, + struct stm32_ep_s *privep); +static inline void stm32_ep0out_receive(struct stm32_ep_s *privep, int bcnt); -static inline void stm32l4_epout_receive(struct stm32l4_ep_s *privep, +static inline void stm32_epout_receive(struct stm32_ep_s *privep, int bcnt); -static void stm32l4_epout_request(struct stm32l4_usbdev_s *priv, - struct stm32l4_ep_s *privep); +static void stm32_epout_request(struct stm32_usbdev_s *priv, + struct stm32_ep_s *privep); /* General request handling */ -static void stm32l4_ep_flush(struct stm32l4_ep_s *privep); -static void stm32l4_req_complete(struct stm32l4_ep_s *privep, +static void stm32_ep_flush(struct stm32_ep_s *privep); +static void stm32_req_complete(struct stm32_ep_s *privep, int16_t result); -static void stm32l4_req_cancel(struct stm32l4_ep_s *privep, +static void stm32_req_cancel(struct stm32_ep_s *privep, int16_t status); /* Interrupt handling *******************************************************/ static -struct stm32l4_ep_s *stm32l4_ep_findbyaddr(struct stm32l4_usbdev_s *priv, +struct stm32_ep_s *stm32_ep_findbyaddr(struct stm32_usbdev_s *priv, uint16_t eplog); -static int stm32l4_req_dispatch(struct stm32l4_usbdev_s *priv, +static int stm32_req_dispatch(struct stm32_usbdev_s *priv, const struct usb_ctrlreq_s *ctrl); -static void stm32l4_usbreset(struct stm32l4_usbdev_s *priv); +static void stm32_usbreset(struct stm32_usbdev_s *priv); /* Second level OUT endpoint interrupt processing */ -static inline void stm32l4_ep0out_testmode(struct stm32l4_usbdev_s *priv, +static inline void stm32_ep0out_testmode(struct stm32_usbdev_s *priv, uint16_t index); -static inline void stm32l4_ep0out_stdrequest(struct stm32l4_usbdev_s *priv, - struct stm32l4_ctrlreq_s *ctrlreq); -static inline void stm32l4_ep0out_setup(struct stm32l4_usbdev_s *priv); -static inline void stm32l4_epout(struct stm32l4_usbdev_s *priv, +static inline void stm32_ep0out_stdrequest(struct stm32_usbdev_s *priv, + struct stm32_ctrlreq_s *ctrlreq); +static inline void stm32_ep0out_setup(struct stm32_usbdev_s *priv); +static inline void stm32_epout(struct stm32_usbdev_s *priv, uint8_t epno); static inline -void stm32l4_epout_interrupt(struct stm32l4_usbdev_s *priv); +void stm32_epout_interrupt(struct stm32_usbdev_s *priv); /* Second level IN endpoint interrupt processing */ static inline -void stm32l4_epin_runtestmode(struct stm32l4_usbdev_s *priv); +void stm32_epin_runtestmode(struct stm32_usbdev_s *priv); static inline -void stm32l4_epin(struct stm32l4_usbdev_s *priv, uint8_t epno); +void stm32_epin(struct stm32_usbdev_s *priv, uint8_t epno); static inline -void stm32l4_epin_txfifoempty(struct stm32l4_usbdev_s *priv, +void stm32_epin_txfifoempty(struct stm32_usbdev_s *priv, int epno); -static inline void stm32l4_epin_interrupt(struct stm32l4_usbdev_s *priv); +static inline void stm32_epin_interrupt(struct stm32_usbdev_s *priv); /* Other second level interrupt processing */ static inline -void stm32l4_resumeinterrupt(struct stm32l4_usbdev_s *priv); +void stm32_resumeinterrupt(struct stm32_usbdev_s *priv); static inline -void stm32l4_suspendinterrupt(struct stm32l4_usbdev_s *priv); -static inline void stm32l4_rxinterrupt(struct stm32l4_usbdev_s *priv); -static inline void stm32l4_enuminterrupt(struct stm32l4_usbdev_s *priv); +void stm32_suspendinterrupt(struct stm32_usbdev_s *priv); +static inline void stm32_rxinterrupt(struct stm32_usbdev_s *priv); +static inline void stm32_enuminterrupt(struct stm32_usbdev_s *priv); #ifdef CONFIG_USBDEV_ISOCHRONOUS static inline -void stm32l4_isocininterrupt(struct stm32l4_usbdev_s *priv); +void stm32_isocininterrupt(struct stm32_usbdev_s *priv); static inline -void stm32l4_isocoutinterrupt(struct stm32l4_usbdev_s *priv); +void stm32_isocoutinterrupt(struct stm32_usbdev_s *priv); #endif #ifdef CONFIG_USBDEV_VBUSSENSING static inline -void stm32l4_sessioninterrupt(struct stm32l4_usbdev_s *priv); -static inline void stm32l4_otginterrupt(struct stm32l4_usbdev_s *priv); +void stm32_sessioninterrupt(struct stm32_usbdev_s *priv); +static inline void stm32_otginterrupt(struct stm32_usbdev_s *priv); #endif /* First level interrupt processing */ -static int stm32l4_usbinterrupt(int irq, void *context, +static int stm32_usbinterrupt(int irq, void *context, void *arg); /* Endpoint operations ******************************************************/ /* Global OUT NAK controls */ -static void stm32l4_enablegonak(struct stm32l4_ep_s *privep); -static void stm32l4_disablegonak(struct stm32l4_ep_s *privep); +static void stm32_enablegonak(struct stm32_ep_s *privep); +static void stm32_disablegonak(struct stm32_ep_s *privep); /* Endpoint configuration */ -static int stm32l4_epout_configure(struct stm32l4_ep_s *privep, +static int stm32_epout_configure(struct stm32_ep_s *privep, uint8_t eptype, uint16_t maxpacket); -static int stm32l4_epin_configure(struct stm32l4_ep_s *privep, +static int stm32_epin_configure(struct stm32_ep_s *privep, uint8_t eptype, uint16_t maxpacket); -static int stm32l4_ep_configure(struct usbdev_ep_s *ep, +static int stm32_ep_configure(struct usbdev_ep_s *ep, const struct usb_epdesc_s *desc, bool last); -static void stm32l4_ep0_configure(struct stm32l4_usbdev_s *priv); +static void stm32_ep0_configure(struct stm32_usbdev_s *priv); /* Endpoint disable */ -static void stm32l4_epout_disable(struct stm32l4_ep_s *privep); -static void stm32l4_epin_disable(struct stm32l4_ep_s *privep); -static int stm32l4_ep_disable(struct usbdev_ep_s *ep); +static void stm32_epout_disable(struct stm32_ep_s *privep); +static void stm32_epin_disable(struct stm32_ep_s *privep); +static int stm32_ep_disable(struct usbdev_ep_s *ep); /* Endpoint request management */ -static struct usbdev_req_s *stm32l4_ep_allocreq(struct usbdev_ep_s *ep); -static void stm32l4_ep_freereq(struct usbdev_ep_s *ep, +static struct usbdev_req_s *stm32_ep_allocreq(struct usbdev_ep_s *ep); +static void stm32_ep_freereq(struct usbdev_ep_s *ep, struct usbdev_req_s *); /* Endpoint buffer management */ #ifdef CONFIG_USBDEV_DMA -static void *stm32l4_ep_allocbuffer(struct usbdev_ep_s *ep, +static void *stm32_ep_allocbuffer(struct usbdev_ep_s *ep, uint16_t bytes); -static void stm32l4_ep_freebuffer(struct usbdev_ep_s *ep, +static void stm32_ep_freebuffer(struct usbdev_ep_s *ep, void *buf); #endif /* Endpoint request submission */ -static int stm32l4_ep_submit(struct usbdev_ep_s *ep, +static int stm32_ep_submit(struct usbdev_ep_s *ep, struct usbdev_req_s *req); /* Endpoint request cancellation */ -static int stm32l4_ep_cancel(struct usbdev_ep_s *ep, +static int stm32_ep_cancel(struct usbdev_ep_s *ep, struct usbdev_req_s *req); /* Stall handling */ -static int stm32l4_epout_setstall(struct stm32l4_ep_s *privep); -static int stm32l4_epin_setstall(struct stm32l4_ep_s *privep); -static int stm32l4_ep_setstall(struct stm32l4_ep_s *privep); -static int stm32l4_ep_clrstall(struct stm32l4_ep_s *privep); -static int stm32l4_ep_stall(struct usbdev_ep_s *ep, bool resume); -static void stm32l4_ep0_stall(struct stm32l4_usbdev_s *priv); +static int stm32_epout_setstall(struct stm32_ep_s *privep); +static int stm32_epin_setstall(struct stm32_ep_s *privep); +static int stm32_ep_setstall(struct stm32_ep_s *privep); +static int stm32_ep_clrstall(struct stm32_ep_s *privep); +static int stm32_ep_stall(struct usbdev_ep_s *ep, bool resume); +static void stm32_ep0_stall(struct stm32_usbdev_s *priv); /* Endpoint allocation */ -static struct usbdev_ep_s *stm32l4_ep_alloc(struct usbdev_s *dev, +static struct usbdev_ep_s *stm32_ep_alloc(struct usbdev_s *dev, uint8_t epno, bool in, uint8_t eptype); -static void stm32l4_ep_free(struct usbdev_s *dev, +static void stm32_ep_free(struct usbdev_s *dev, struct usbdev_ep_s *ep); /* USB device controller operations *****************************************/ -static int stm32l4_getframe(struct usbdev_s *dev); -static int stm32l4_wakeup(struct usbdev_s *dev); -static int stm32l4_selfpowered(struct usbdev_s *dev, +static int stm32_getframe(struct usbdev_s *dev); +static int stm32_wakeup(struct usbdev_s *dev); +static int stm32_selfpowered(struct usbdev_s *dev, bool selfpowered); -static int stm32l4_pullup(struct usbdev_s *dev, bool enable); -static void stm32l4_setaddress(struct stm32l4_usbdev_s *priv, +static int stm32_pullup(struct usbdev_s *dev, bool enable); +static void stm32_setaddress(struct stm32_usbdev_s *priv, uint16_t address); -static int stm32l4_txfifo_flush(uint32_t txfnum); -static int stm32l4_rxfifo_flush(void); +static int stm32_txfifo_flush(uint32_t txfnum); +static int stm32_rxfifo_flush(void); /* Initialization ***********************************************************/ -static void stm32l4_swinitialize(struct stm32l4_usbdev_s *priv); -static void stm32l4_hwinitialize(struct stm32l4_usbdev_s *priv); +static void stm32_swinitialize(struct stm32_usbdev_s *priv); +static void stm32_hwinitialize(struct stm32_usbdev_s *priv); /**************************************************************************** * Private Data @@ -755,31 +755,31 @@ static void stm32l4_hwinitialize(struct stm32l4_usbdev_s *priv); * be simply retained in a single global instance. */ -static struct stm32l4_usbdev_s g_otgfsdev; +static struct stm32_usbdev_s g_otgfsdev; static const struct usbdev_epops_s g_epops = { - .configure = stm32l4_ep_configure, - .disable = stm32l4_ep_disable, - .allocreq = stm32l4_ep_allocreq, - .freereq = stm32l4_ep_freereq, + .configure = stm32_ep_configure, + .disable = stm32_ep_disable, + .allocreq = stm32_ep_allocreq, + .freereq = stm32_ep_freereq, #ifdef CONFIG_USBDEV_DMA - .allocbuffer = stm32l4_ep_allocbuffer, - .freebuffer = stm32l4_ep_freebuffer, + .allocbuffer = stm32_ep_allocbuffer, + .freebuffer = stm32_ep_freebuffer, #endif - .submit = stm32l4_ep_submit, - .cancel = stm32l4_ep_cancel, - .stall = stm32l4_ep_stall, + .submit = stm32_ep_submit, + .cancel = stm32_ep_cancel, + .stall = stm32_ep_stall, }; static const struct usbdev_ops_s g_devops = { - .allocep = stm32l4_ep_alloc, - .freeep = stm32l4_ep_free, - .getframe = stm32l4_getframe, - .wakeup = stm32l4_wakeup, - .selfpowered = stm32l4_selfpowered, - .pullup = stm32l4_pullup, + .allocep = stm32_ep_alloc, + .freeep = stm32_ep_free, + .getframe = stm32_getframe, + .wakeup = stm32_wakeup, + .selfpowered = stm32_selfpowered, + .pullup = stm32_pullup, }; /* Device error strings that may be enabled for more descriptive USB trace @@ -789,37 +789,37 @@ static const struct usbdev_ops_s g_devops = #ifdef CONFIG_USBDEV_TRACE_STRINGS const struct trace_msg_t g_usb_trace_strings_deverror[] = { - TRACE_STR(STM32L4_TRACEERR_ALLOCFAIL), - TRACE_STR(STM32L4_TRACEERR_BADCLEARFEATURE), - TRACE_STR(STM32L4_TRACEERR_BADDEVGETSTATUS), - TRACE_STR(STM32L4_TRACEERR_BADEPNO), - TRACE_STR(STM32L4_TRACEERR_BADEPGETSTATUS), - TRACE_STR(STM32L4_TRACEERR_BADGETCONFIG), - TRACE_STR(STM32L4_TRACEERR_BADGETSETDESC), - TRACE_STR(STM32L4_TRACEERR_BADGETSTATUS), - TRACE_STR(STM32L4_TRACEERR_BADSETADDRESS), - TRACE_STR(STM32L4_TRACEERR_BADSETCONFIG), - TRACE_STR(STM32L4_TRACEERR_BADSETFEATURE), - TRACE_STR(STM32L4_TRACEERR_BADTESTMODE), - TRACE_STR(STM32L4_TRACEERR_BINDFAILED), - TRACE_STR(STM32L4_TRACEERR_DISPATCHSTALL), - TRACE_STR(STM32L4_TRACEERR_DRIVER), - TRACE_STR(STM32L4_TRACEERR_DRIVERREGISTERED), - TRACE_STR(STM32L4_TRACEERR_EP0NOSETUP), - TRACE_STR(STM32L4_TRACEERR_EP0SETUPSTALLED), - TRACE_STR(STM32L4_TRACEERR_EPINNULLPACKET), - TRACE_STR(STM32L4_TRACEERR_EPINUNEXPECTED), - TRACE_STR(STM32L4_TRACEERR_EPOUTNULLPACKET), - TRACE_STR(STM32L4_TRACEERR_EPOUTUNEXPECTED), - TRACE_STR(STM32L4_TRACEERR_INVALIDCTRLREQ), - TRACE_STR(STM32L4_TRACEERR_INVALIDPARMS), - TRACE_STR(STM32L4_TRACEERR_IRQREGISTRATION), - TRACE_STR(STM32L4_TRACEERR_NOEP), - TRACE_STR(STM32L4_TRACEERR_NOTCONFIGURED), - TRACE_STR(STM32L4_TRACEERR_EPOUTQEMPTY), - TRACE_STR(STM32L4_TRACEERR_EPINREQEMPTY), - TRACE_STR(STM32L4_TRACEERR_NOOUTSETUP), - TRACE_STR(STM32L4_TRACEERR_POLLTIMEOUT), + TRACE_STR(STM32_TRACEERR_ALLOCFAIL), + TRACE_STR(STM32_TRACEERR_BADCLEARFEATURE), + TRACE_STR(STM32_TRACEERR_BADDEVGETSTATUS), + TRACE_STR(STM32_TRACEERR_BADEPNO), + TRACE_STR(STM32_TRACEERR_BADEPGETSTATUS), + TRACE_STR(STM32_TRACEERR_BADGETCONFIG), + TRACE_STR(STM32_TRACEERR_BADGETSETDESC), + TRACE_STR(STM32_TRACEERR_BADGETSTATUS), + TRACE_STR(STM32_TRACEERR_BADSETADDRESS), + TRACE_STR(STM32_TRACEERR_BADSETCONFIG), + TRACE_STR(STM32_TRACEERR_BADSETFEATURE), + TRACE_STR(STM32_TRACEERR_BADTESTMODE), + TRACE_STR(STM32_TRACEERR_BINDFAILED), + TRACE_STR(STM32_TRACEERR_DISPATCHSTALL), + TRACE_STR(STM32_TRACEERR_DRIVER), + TRACE_STR(STM32_TRACEERR_DRIVERREGISTERED), + TRACE_STR(STM32_TRACEERR_EP0NOSETUP), + TRACE_STR(STM32_TRACEERR_EP0SETUPSTALLED), + TRACE_STR(STM32_TRACEERR_EPINNULLPACKET), + TRACE_STR(STM32_TRACEERR_EPINUNEXPECTED), + TRACE_STR(STM32_TRACEERR_EPOUTNULLPACKET), + TRACE_STR(STM32_TRACEERR_EPOUTUNEXPECTED), + TRACE_STR(STM32_TRACEERR_INVALIDCTRLREQ), + TRACE_STR(STM32_TRACEERR_INVALIDPARMS), + TRACE_STR(STM32_TRACEERR_IRQREGISTRATION), + TRACE_STR(STM32_TRACEERR_NOEP), + TRACE_STR(STM32_TRACEERR_NOTCONFIGURED), + TRACE_STR(STM32_TRACEERR_EPOUTQEMPTY), + TRACE_STR(STM32_TRACEERR_EPINREQEMPTY), + TRACE_STR(STM32_TRACEERR_NOOUTSETUP), + TRACE_STR(STM32_TRACEERR_POLLTIMEOUT), TRACE_STR_END }; #endif @@ -831,48 +831,48 @@ const struct trace_msg_t g_usb_trace_strings_deverror[] = #ifdef CONFIG_USBDEV_TRACE_STRINGS const struct trace_msg_t g_usb_trace_strings_intdecode[] = { - TRACE_STR(STM32L4_TRACEINTID_USB), - TRACE_STR(STM32L4_TRACEINTID_INTPENDING), - TRACE_STR(STM32L4_TRACEINTID_EPOUT), - TRACE_STR(STM32L4_TRACEINTID_EPIN), - TRACE_STR(STM32L4_TRACEINTID_MISMATCH), - TRACE_STR(STM32L4_TRACEINTID_WAKEUP), - TRACE_STR(STM32L4_TRACEINTID_SUSPEND), - TRACE_STR(STM32L4_TRACEINTID_SOF), - TRACE_STR(STM32L4_TRACEINTID_RXFIFO), - TRACE_STR(STM32L4_TRACEINTID_DEVRESET), - TRACE_STR(STM32L4_TRACEINTID_ENUMDNE), - TRACE_STR(STM32L4_TRACEINTID_IISOIXFR), - TRACE_STR(STM32L4_TRACEINTID_IISOOXFR), - TRACE_STR(STM32L4_TRACEINTID_SRQ), - TRACE_STR(STM32L4_TRACEINTID_OTG), - TRACE_STR(STM32L4_TRACEINTID_EPOUT_XFRC), - TRACE_STR(STM32L4_TRACEINTID_EPOUT_EPDISD), - TRACE_STR(STM32L4_TRACEINTID_EPOUT_SETUP), - TRACE_STR(STM32L4_TRACEINTID_DISPATCH), - TRACE_STR(STM32L4_TRACEINTID_GETSTATUS), - TRACE_STR(STM32L4_TRACEINTID_EPGETSTATUS), - TRACE_STR(STM32L4_TRACEINTID_DEVGETSTATUS), - TRACE_STR(STM32L4_TRACEINTID_IFGETSTATUS), - TRACE_STR(STM32L4_TRACEINTID_CLEARFEATURE), - TRACE_STR(STM32L4_TRACEINTID_SETFEATURE), - TRACE_STR(STM32L4_TRACEINTID_SETADDRESS), - TRACE_STR(STM32L4_TRACEINTID_GETSETDESC), - TRACE_STR(STM32L4_TRACEINTID_GETCONFIG), - TRACE_STR(STM32L4_TRACEINTID_SETCONFIG), - TRACE_STR(STM32L4_TRACEINTID_GETSETIF), - TRACE_STR(STM32L4_TRACEINTID_SYNCHFRAME), - TRACE_STR(STM32L4_TRACEINTID_EPIN_XFRC), - TRACE_STR(STM32L4_TRACEINTID_EPIN_TOC), - TRACE_STR(STM32L4_TRACEINTID_EPIN_ITTXFE), - TRACE_STR(STM32L4_TRACEINTID_EPIN_EPDISD), - TRACE_STR(STM32L4_TRACEINTID_EPIN_TXFE), - TRACE_STR(STM32L4_TRACEINTID_EPIN_EMPWAIT), - TRACE_STR(STM32L4_TRACEINTID_OUTNAK), - TRACE_STR(STM32L4_TRACEINTID_OUTRECVD), - TRACE_STR(STM32L4_TRACEINTID_OUTDONE), - TRACE_STR(STM32L4_TRACEINTID_SETUPDONE), - TRACE_STR(STM32L4_TRACEINTID_SETUPRECVD), + TRACE_STR(STM32_TRACEINTID_USB), + TRACE_STR(STM32_TRACEINTID_INTPENDING), + TRACE_STR(STM32_TRACEINTID_EPOUT), + TRACE_STR(STM32_TRACEINTID_EPIN), + TRACE_STR(STM32_TRACEINTID_MISMATCH), + TRACE_STR(STM32_TRACEINTID_WAKEUP), + TRACE_STR(STM32_TRACEINTID_SUSPEND), + TRACE_STR(STM32_TRACEINTID_SOF), + TRACE_STR(STM32_TRACEINTID_RXFIFO), + TRACE_STR(STM32_TRACEINTID_DEVRESET), + TRACE_STR(STM32_TRACEINTID_ENUMDNE), + TRACE_STR(STM32_TRACEINTID_IISOIXFR), + TRACE_STR(STM32_TRACEINTID_IISOOXFR), + TRACE_STR(STM32_TRACEINTID_SRQ), + TRACE_STR(STM32_TRACEINTID_OTG), + TRACE_STR(STM32_TRACEINTID_EPOUT_XFRC), + TRACE_STR(STM32_TRACEINTID_EPOUT_EPDISD), + TRACE_STR(STM32_TRACEINTID_EPOUT_SETUP), + TRACE_STR(STM32_TRACEINTID_DISPATCH), + TRACE_STR(STM32_TRACEINTID_GETSTATUS), + TRACE_STR(STM32_TRACEINTID_EPGETSTATUS), + TRACE_STR(STM32_TRACEINTID_DEVGETSTATUS), + TRACE_STR(STM32_TRACEINTID_IFGETSTATUS), + TRACE_STR(STM32_TRACEINTID_CLEARFEATURE), + TRACE_STR(STM32_TRACEINTID_SETFEATURE), + TRACE_STR(STM32_TRACEINTID_SETADDRESS), + TRACE_STR(STM32_TRACEINTID_GETSETDESC), + TRACE_STR(STM32_TRACEINTID_GETCONFIG), + TRACE_STR(STM32_TRACEINTID_SETCONFIG), + TRACE_STR(STM32_TRACEINTID_GETSETIF), + TRACE_STR(STM32_TRACEINTID_SYNCHFRAME), + TRACE_STR(STM32_TRACEINTID_EPIN_XFRC), + TRACE_STR(STM32_TRACEINTID_EPIN_TOC), + TRACE_STR(STM32_TRACEINTID_EPIN_ITTXFE), + TRACE_STR(STM32_TRACEINTID_EPIN_EPDISD), + TRACE_STR(STM32_TRACEINTID_EPIN_TXFE), + TRACE_STR(STM32_TRACEINTID_EPIN_EMPWAIT), + TRACE_STR(STM32_TRACEINTID_OUTNAK), + TRACE_STR(STM32_TRACEINTID_OUTRECVD), + TRACE_STR(STM32_TRACEINTID_OUTDONE), + TRACE_STR(STM32_TRACEINTID_SETUPDONE), + TRACE_STR(STM32_TRACEINTID_SETUPRECVD), TRACE_STR_END }; #endif @@ -886,15 +886,15 @@ const struct trace_msg_t g_usb_trace_strings_intdecode[] = ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_getreg + * Name: stm32_getreg * * Description: * Get the contents of an STM32 register * ****************************************************************************/ -#if defined(CONFIG_STM32L4_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES) -static uint32_t stm32l4_getreg(uint32_t addr) +#if defined(CONFIG_STM32_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES) +static uint32_t stm32_getreg(uint32_t addr) { static uint32_t prevaddr = 0; static uint32_t preval = 0; @@ -949,15 +949,15 @@ static uint32_t stm32l4_getreg(uint32_t addr) #endif /**************************************************************************** - * Name: stm32l4_putreg + * Name: stm32_putreg * * Description: * Set the contents of an STM32 register to a value * ****************************************************************************/ -#if defined(CONFIG_STM32L4_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES) -static void stm32l4_putreg(uint32_t val, uint32_t addr) +#if defined(CONFIG_STM32_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES) +static void stm32_putreg(uint32_t val, uint32_t addr) { /* Show the register value being written */ @@ -970,17 +970,17 @@ static void stm32l4_putreg(uint32_t val, uint32_t addr) #endif /**************************************************************************** - * Name: stm32l4_req_remfirst + * Name: stm32_req_remfirst * * Description: * Remove a request from the head of an endpoint request queue * ****************************************************************************/ -static struct stm32l4_req_s * -stm32l4_req_remfirst(struct stm32l4_ep_s *privep) +static struct stm32_req_s * +stm32_req_remfirst(struct stm32_ep_s *privep) { - struct stm32l4_req_s *ret = privep->head; + struct stm32_req_s *ret = privep->head; if (ret) { @@ -997,15 +997,15 @@ stm32l4_req_remfirst(struct stm32l4_ep_s *privep) } /**************************************************************************** - * Name: stm32l4_req_addlast + * Name: stm32_req_addlast * * Description: * Add a request to the end of an endpoint request queue * ****************************************************************************/ -static bool stm32l4_req_addlast(struct stm32l4_ep_s *privep, - struct stm32l4_req_s *req) +static bool stm32_req_addlast(struct stm32_ep_s *privep, + struct stm32_req_s *req) { bool is_empty = !privep->head; @@ -1025,23 +1025,23 @@ static bool stm32l4_req_addlast(struct stm32l4_ep_s *privep, } /**************************************************************************** - * Name: stm32l4_ep0in_setupresponse + * Name: stm32_ep0in_setupresponse * * Description: * Schedule a short transfer on Endpoint 0 (IN or OUT) * ****************************************************************************/ -static void stm32l4_ep0in_setupresponse(struct stm32l4_usbdev_s *priv, +static void stm32_ep0in_setupresponse(struct stm32_usbdev_s *priv, uint8_t *buf, uint32_t nbytes) { - stm32l4_epin_transfer(&priv->epin[EP0], buf, nbytes); + stm32_epin_transfer(&priv->epin[EP0], buf, nbytes); priv->ep0state = EP0STATE_SETUPRESPONSE; - stm32l4_ep0out_ctrlsetup(priv); + stm32_ep0out_ctrlsetup(priv); } /**************************************************************************** - * Name: stm32l4_ep0in_transmitzlp + * Name: stm32_ep0in_transmitzlp * * Description: * Send a zero length packet (ZLP) on endpoint 0 IN @@ -1049,26 +1049,26 @@ static void stm32l4_ep0in_setupresponse(struct stm32l4_usbdev_s *priv, ****************************************************************************/ static inline void -stm32l4_ep0in_transmitzlp(struct stm32l4_usbdev_s *priv) +stm32_ep0in_transmitzlp(struct stm32_usbdev_s *priv) { - stm32l4_ep0in_setupresponse(priv, NULL, 0); + stm32_ep0in_setupresponse(priv, NULL, 0); } /**************************************************************************** - * Name: stm32l4_ep0in_activate + * Name: stm32_ep0in_activate * * Description: * Activate the endpoint 0 IN endpoint. * ****************************************************************************/ -static void stm32l4_ep0in_activate(void) +static void stm32_ep0in_activate(void) { uint32_t regval; /* Set the max packet size of the IN EP. */ - regval = stm32l4_getreg(STM32L4_OTGFS_DIEPCTL(0)); + regval = stm32_getreg(STM32_OTGFS_DIEPCTL(0)); regval &= ~OTGFS_DIEPCTL0_MPSIZ_MASK; #if CONFIG_USBDEV_EP0_MAXSIZE == 8 @@ -1083,24 +1083,24 @@ static void stm32l4_ep0in_activate(void) # error "Unsupported value of CONFIG_USBDEV_EP0_MAXSIZE" #endif - stm32l4_putreg(regval, STM32L4_OTGFS_DIEPCTL(0)); + stm32_putreg(regval, STM32_OTGFS_DIEPCTL(0)); /* Clear global IN NAK */ - regval = stm32l4_getreg(STM32L4_OTGFS_DCTL); + regval = stm32_getreg(STM32_OTGFS_DCTL); regval |= OTGFS_DCTL_CGINAK; - stm32l4_putreg(regval, STM32L4_OTGFS_DCTL); + stm32_putreg(regval, STM32_OTGFS_DCTL); } /**************************************************************************** - * Name: stm32l4_ep0out_ctrlsetup + * Name: stm32_ep0out_ctrlsetup * * Description: * Setup to receive a SETUP packet. * ****************************************************************************/ -static void stm32l4_ep0out_ctrlsetup(struct stm32l4_usbdev_s *priv) +static void stm32_ep0out_ctrlsetup(struct stm32_usbdev_s *priv) { uint32_t regval; @@ -1109,24 +1109,24 @@ static void stm32l4_ep0out_ctrlsetup(struct stm32l4_usbdev_s *priv) regval = (USB_SIZEOF_CTRLREQ * 3 << OTGFS_DOEPTSIZ0_XFRSIZ_SHIFT) | (OTGFS_DOEPTSIZ0_PKTCNT) | (3 << OTGFS_DOEPTSIZ0_STUPCNT_SHIFT); - stm32l4_putreg(regval, STM32L4_OTGFS_DOEPTSIZ(0)); + stm32_putreg(regval, STM32_OTGFS_DOEPTSIZ(0)); /* Then clear NAKing and enable the transfer */ - regval = stm32l4_getreg(STM32L4_OTGFS_DOEPCTL(0)); + regval = stm32_getreg(STM32_OTGFS_DOEPCTL(0)); regval |= (OTGFS_DOEPCTL0_CNAK | OTGFS_DOEPCTL0_EPENA); - stm32l4_putreg(regval, STM32L4_OTGFS_DOEPCTL(0)); + stm32_putreg(regval, STM32_OTGFS_DOEPCTL(0)); } /**************************************************************************** - * Name: stm32l4_txfifo_write + * Name: stm32_txfifo_write * * Description: * Send data to the endpoint's TxFIFO. * ****************************************************************************/ -static void stm32l4_txfifo_write(struct stm32l4_ep_s *privep, +static void stm32_txfifo_write(struct stm32_ep_s *privep, uint8_t *buf, int nbytes) { uint32_t regaddr; @@ -1140,7 +1140,7 @@ static void stm32l4_txfifo_write(struct stm32l4_ep_s *privep, /* Get the TxFIFO for this endpoint (same as the endpoint number) */ - regaddr = STM32L4_OTGFS_DFIFO_DEP(privep->epphy); + regaddr = STM32_OTGFS_DFIFO_DEP(privep->epphy); /* Then transfer each word to the TxFIFO */ @@ -1157,19 +1157,19 @@ static void stm32l4_txfifo_write(struct stm32l4_ep_s *privep, /* Then write the packet data to the TxFIFO */ - stm32l4_putreg(regval, regaddr); + stm32_putreg(regval, regaddr); } } /**************************************************************************** - * Name: stm32l4_epin_transfer + * Name: stm32_epin_transfer * * Description: * Start the Tx data transfer * ****************************************************************************/ -static void stm32l4_epin_transfer(struct stm32l4_ep_s *privep, +static void stm32_epin_transfer(struct stm32_ep_s *privep, uint8_t *buf, int nbytes) { uint32_t pktcnt; @@ -1177,7 +1177,7 @@ static void stm32l4_epin_transfer(struct stm32l4_ep_s *privep, /* Read the DIEPSIZx register */ - regval = stm32l4_getreg(STM32L4_OTGFS_DIEPTSIZ(privep->epphy)); + regval = stm32_getreg(STM32_OTGFS_DIEPTSIZ(privep->epphy)); /* Clear the XFRSIZ, PKTCNT, and MCNT field of the DIEPSIZx register */ @@ -1223,11 +1223,11 @@ static void stm32l4_epin_transfer(struct stm32l4_ep_s *privep, /* Save DIEPSIZx register value */ - stm32l4_putreg(regval, STM32L4_OTGFS_DIEPTSIZ(privep->epphy)); + stm32_putreg(regval, STM32_OTGFS_DIEPTSIZ(privep->epphy)); /* Read the DIEPCTLx register */ - regval = stm32l4_getreg(STM32L4_OTGFS_DIEPCTL(privep->epphy)); + regval = stm32_getreg(STM32_OTGFS_DIEPCTL(privep->epphy)); /* If this is an isochronous endpoint, then set the even/odd frame bit * the DIEPCTLx register. @@ -1239,7 +1239,7 @@ static void stm32l4_epin_transfer(struct stm32l4_ep_s *privep, * even/odd frame to match. */ - uint32_t status = stm32l4_getreg(STM32L4_OTGFS_DSTS); + uint32_t status = stm32_getreg(STM32_OTGFS_DSTS); if ((status & OTGFS_DSTS_SOFFN0) == OTGFS_DSTS_SOFFN_EVEN) { regval |= OTGFS_DIEPCTL_SEVNFRM; @@ -1254,28 +1254,28 @@ static void stm32l4_epin_transfer(struct stm32l4_ep_s *privep, regval &= ~OTGFS_DIEPCTL_EPDIS; regval |= (OTGFS_DIEPCTL_CNAK | OTGFS_DIEPCTL_EPENA); - stm32l4_putreg(regval, STM32L4_OTGFS_DIEPCTL(privep->epphy)); + stm32_putreg(regval, STM32_OTGFS_DIEPCTL(privep->epphy)); /* Transfer the data to the TxFIFO. At this point, the caller has already * assured that there is sufficient space in the TxFIFO to hold the * transfer we can just blindly continue. */ - stm32l4_txfifo_write(privep, buf, nbytes); + stm32_txfifo_write(privep, buf, nbytes); } /**************************************************************************** - * Name: stm32l4_epin_request + * Name: stm32_epin_request * * Description: * Begin or continue write request processing. * ****************************************************************************/ -static void stm32l4_epin_request(struct stm32l4_usbdev_s *priv, - struct stm32l4_ep_s *privep) +static void stm32_epin_request(struct stm32_usbdev_s *priv, + struct stm32_ep_s *privep) { - struct stm32l4_req_s *privreq; + struct stm32_req_s *privreq; uint32_t regaddr; uint32_t regval; uint8_t *buf; @@ -1286,12 +1286,12 @@ static void stm32l4_epin_request(struct stm32l4_usbdev_s *priv, /* We get here in one of four possible ways. From three interrupting * events: * - * 1. From stm32l4_epin as part of the transfer complete interrupt + * 1. From stm32_epin as part of the transfer complete interrupt * processing This interrupt indicates that the last transfer has * completed. * 2. As part of the ITTXFE interrupt processing. That interrupt indicates * that an IN token was received when the associated TxFIFO was empty. - * 3. From stm32l4_epin_txfifoempty as part of the TXFE interrupt + * 3. From stm32_epin_txfifoempty as part of the TXFE interrupt * processing. The TXFE interrupt is only enabled when the TxFIFO is * full and the software must wait for space to become available in the * TxFIFO. @@ -1299,16 +1299,16 @@ static void stm32l4_epin_request(struct stm32l4_usbdev_s *priv, * And this function may be called immediately when the write request is * queue to start up the next transaction. * - * 4. From stm32l4_ep_submit when a new write request is received WHILE the + * 4. From stm32_ep_submit when a new write request is received WHILE the * endpoint is not active (privep->active == false). */ /* Check the request from the head of the endpoint request queue */ - privreq = stm32l4_rqpeek(privep); + privreq = stm32_rqpeek(privep); if (!privreq) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_EPINREQEMPTY), privep->epphy); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EPINREQEMPTY), privep->epphy); /* There is no TX transfer in progress and no new pending TX * requests to send. To stop transmitting any data on a particular @@ -1316,10 +1316,10 @@ static void stm32l4_epin_request(struct stm32l4_usbdev_s *priv, * bit, the following field must be programmed. */ - regaddr = STM32L4_OTGFS_DIEPCTL(privep->epphy); - regval = stm32l4_getreg(regaddr); + regaddr = STM32_OTGFS_DIEPCTL(privep->epphy); + regval = stm32_getreg(regaddr); regval |= OTGFS_DIEPCTL_SNAK; - stm32l4_putreg(regval, regaddr); + stm32_putreg(regval, regaddr); /* The endpoint is no longer active */ @@ -1419,33 +1419,33 @@ static void stm32l4_epin_request(struct stm32l4_usbdev_s *priv, * n: n words available */ - regaddr = STM32L4_OTGFS_DTXFSTS(privep->epphy); + regaddr = STM32_OTGFS_DTXFSTS(privep->epphy); /* Check for space in the TxFIFO. If space in the TxFIFO is not * available, then set up an interrupt to resume the transfer when * the TxFIFO is empty. */ - regval = stm32l4_getreg(regaddr); + regval = stm32_getreg(regaddr); if ((int)(regval & OTGFS_DTXFSTS_MASK) < nwords) { - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_EPIN_EMPWAIT), + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPIN_EMPWAIT), (uint16_t)regval); /* There is insufficient space in the TxFIFO. Wait for a TxFIFO * empty interrupt and try again. */ - uint32_t empmsk = stm32l4_getreg(STM32L4_OTGFS_DIEPEMPMSK); + uint32_t empmsk = stm32_getreg(STM32_OTGFS_DIEPEMPMSK); empmsk |= OTGFS_DIEPEMPMSK(privep->epphy); - stm32l4_putreg(empmsk, STM32L4_OTGFS_DIEPEMPMSK); + stm32_putreg(empmsk, STM32_OTGFS_DIEPEMPMSK); #ifdef CONFIG_DEBUG_FEATURES /* Check if the configured TXFIFO size is sufficient for a given * request. If not, raise an assertion here. */ - regval = stm32l4_getreg(STM32L4_OTG_DIEPTXF(privep->epphy)); + regval = stm32_getreg(STM32_OTG_DIEPTXF(privep->epphy)); regval &= OTGFS_DIEPTXF_INEPTXFD_MASK; regval >>= OTGFS_DIEPTXF_INEPTXFD_SHIFT; uerr("EP%" PRId8 " TXLEN=%" PRId32 " nwords=%d\n", @@ -1463,7 +1463,7 @@ static void stm32l4_epin_request(struct stm32l4_usbdev_s *priv, /* Transfer data to the TxFIFO */ buf = privreq->req.buf + privreq->req.xfrd; - stm32l4_epin_transfer(privep, buf, nbytes); + stm32_epin_transfer(privep, buf, nbytes); /* If it was not before, the OUT endpoint is now actively transferring * data. @@ -1497,19 +1497,19 @@ static void stm32l4_epin_request(struct stm32l4_usbdev_s *priv, * yet completed). */ - stm32l4_req_complete(privep, OK); + stm32_req_complete(privep, OK); } } /**************************************************************************** - * Name: stm32l4_rxfifo_read + * Name: stm32_rxfifo_read * * Description: * Read packet from the RxFIFO into a read request. * ****************************************************************************/ -static void stm32l4_rxfifo_read(struct stm32l4_ep_s *privep, +static void stm32_rxfifo_read(struct stm32_ep_s *privep, uint8_t *dest, uint16_t len) { uint32_t regaddr; @@ -1519,7 +1519,7 @@ static void stm32l4_rxfifo_read(struct stm32l4_ep_s *privep, * we might as well use the address associated with EP0. */ - regaddr = STM32L4_OTGFS_DFIFO_DEP(EP0); + regaddr = STM32_OTGFS_DFIFO_DEP(EP0); /* Read 32-bits and write 4 x 8-bits at time * (to avoid unaligned accesses) @@ -1535,7 +1535,7 @@ static void stm32l4_rxfifo_read(struct stm32l4_ep_s *privep, /* Read 1 x 32-bits of EP0 packet data */ - data.w = stm32l4_getreg(regaddr); + data.w = stm32_getreg(regaddr); /* Write 4 x 8-bits of EP0 packet data */ @@ -1547,14 +1547,14 @@ static void stm32l4_rxfifo_read(struct stm32l4_ep_s *privep, } /**************************************************************************** - * Name: stm32l4_rxfifo_discard + * Name: stm32_rxfifo_discard * * Description: * Discard packet data from the RxFIFO. * ****************************************************************************/ -static void stm32l4_rxfifo_discard(struct stm32l4_ep_s *privep, int len) +static void stm32_rxfifo_discard(struct stm32_ep_s *privep, int len) { if (len > 0) { @@ -1565,13 +1565,13 @@ static void stm32l4_rxfifo_discard(struct stm32l4_ep_s *privep, int len) * we might as well use the address associated with EP0. */ - regaddr = STM32L4_OTGFS_DFIFO_DEP(EP0); + regaddr = STM32_OTGFS_DFIFO_DEP(EP0); /* Read 32-bits at time */ for (i = 0; i < len; i += 4) { - volatile uint32_t data = stm32l4_getreg(regaddr); + volatile uint32_t data = stm32_getreg(regaddr); UNUSED(data); } @@ -1580,7 +1580,7 @@ static void stm32l4_rxfifo_discard(struct stm32l4_ep_s *privep, int len) } /**************************************************************************** - * Name: stm32l4_epout_complete + * Name: stm32_epout_complete * * Description: * This function is called when an OUT transfer complete interrupt is @@ -1589,16 +1589,16 @@ static void stm32l4_rxfifo_discard(struct stm32l4_ep_s *privep, int len) * ****************************************************************************/ -static void stm32l4_epout_complete(struct stm32l4_usbdev_s *priv, - struct stm32l4_ep_s *privep) +static void stm32_epout_complete(struct stm32_usbdev_s *priv, + struct stm32_ep_s *privep) { - struct stm32l4_req_s *privreq; + struct stm32_req_s *privreq; /* Since a transfer just completed, there must be a read request at the * head of the endpoint request queue. */ - privreq = stm32l4_rqpeek(privep); + privreq = stm32_rqpeek(privep); DEBUGASSERT(privreq); if (!privreq) @@ -1607,7 +1607,7 @@ static void stm32l4_epout_complete(struct stm32l4_usbdev_s *priv, * should not happen. */ - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_EPOUTQEMPTY), privep->epphy); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EPOUTQEMPTY), privep->epphy); privep->active = false; return; } @@ -1620,16 +1620,16 @@ static void stm32l4_epout_complete(struct stm32l4_usbdev_s *priv, */ usbtrace(TRACE_COMPLETE(privep->epphy), privreq->req.xfrd); - stm32l4_req_complete(privep, OK); + stm32_req_complete(privep, OK); privep->active = false; /* Now set up the next read request (if any) */ - stm32l4_epout_request(priv, privep); + stm32_epout_request(priv, privep); } /**************************************************************************** - * Name: stm32l4_ep0out_receive + * Name: stm32_ep0out_receive * * Description: * This function is called from the RXFLVL interrupt handler when new @@ -1638,15 +1638,15 @@ static void stm32l4_epout_complete(struct stm32l4_usbdev_s *priv, * ****************************************************************************/ -static inline void stm32l4_ep0out_receive(struct stm32l4_ep_s *privep, +static inline void stm32_ep0out_receive(struct stm32_ep_s *privep, int bcnt) { - struct stm32l4_usbdev_s *priv; + struct stm32_usbdev_s *priv; /* Sanity Checking */ DEBUGASSERT(privep && privep->dev); - priv = (struct stm32l4_usbdev_s *)privep->dev; + priv = (struct stm32_usbdev_s *)privep->dev; uinfo("EP0: bcnt=%d\n", bcnt); usbtrace(TRACE_READ(EP0), bcnt); @@ -1660,11 +1660,11 @@ static inline void stm32l4_ep0out_receive(struct stm32l4_ep_s *privep, /* Read the data into our special buffer for SETUP data */ int readlen = MIN(CONFIG_USBDEV_SETUP_MAXDATASIZE, bcnt); - stm32l4_rxfifo_read(privep, priv->ep0data, readlen); + stm32_rxfifo_read(privep, priv->ep0data, readlen); /* Do we have to discard any excess bytes? */ - stm32l4_rxfifo_discard(privep, bcnt - readlen); + stm32_rxfifo_discard(privep, bcnt - readlen); /* Now we can process the setup command */ @@ -1672,7 +1672,7 @@ static inline void stm32l4_ep0out_receive(struct stm32l4_ep_s *privep, priv->ep0state = EP0STATE_SETUP_READY; priv->ep0datlen = readlen; - stm32l4_ep0out_setup(priv); + stm32_ep0out_setup(priv); } else { @@ -1681,14 +1681,14 @@ static inline void stm32l4_ep0out_receive(struct stm32l4_ep_s *privep, * does not become constipated. */ - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_NOOUTSETUP), priv->ep0state); - stm32l4_rxfifo_discard(privep, bcnt); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_NOOUTSETUP), priv->ep0state); + stm32_rxfifo_discard(privep, bcnt); privep->active = false; } } /**************************************************************************** - * Name: stm32l4_epout_receive + * Name: stm32_epout_receive * * Description: * This function is called from the RXFLVL interrupt handler when new @@ -1697,10 +1697,10 @@ static inline void stm32l4_ep0out_receive(struct stm32l4_ep_s *privep, * ****************************************************************************/ -static inline void stm32l4_epout_receive(struct stm32l4_ep_s *privep, +static inline void stm32_epout_receive(struct stm32_ep_s *privep, int bcnt) { - struct stm32l4_req_s *privreq; + struct stm32_req_s *privreq; uint8_t *dest; int buflen; int readlen; @@ -1709,7 +1709,7 @@ static inline void stm32l4_epout_receive(struct stm32l4_ep_s *privep, * queue. */ - privreq = stm32l4_rqpeek(privep); + privreq = stm32_rqpeek(privep); if (!privreq) { /* Incoming data is available in the RxFIFO, but there is no read setup @@ -1724,7 +1724,7 @@ static inline void stm32l4_epout_receive(struct stm32l4_ep_s *privep, if (privep->epphy == 0) { - stm32l4_ep0out_receive(privep, bcnt); + stm32_ep0out_receive(privep, bcnt); } else { @@ -1732,12 +1732,12 @@ static inline void stm32l4_epout_receive(struct stm32l4_ep_s *privep, * NAKing is working as expected. */ - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_EPOUTQEMPTY), + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EPOUTQEMPTY), privep->epphy); /* Discard the data in the RxFIFO */ - stm32l4_rxfifo_discard(privep, bcnt); + stm32_rxfifo_discard(privep, bcnt); } privep->active = false; @@ -1760,13 +1760,13 @@ static inline void stm32l4_epout_receive(struct stm32l4_ep_s *privep, /* Transfer the data from the RxFIFO to the request's data buffer */ - stm32l4_rxfifo_read(privep, dest, readlen); + stm32_rxfifo_read(privep, dest, readlen); /* If there were more bytes in the RxFIFO than could be held in the read * request, then we will have to discard those. */ - stm32l4_rxfifo_discard(privep, bcnt - readlen); + stm32_rxfifo_discard(privep, bcnt - readlen); /* Update the number of bytes transferred */ @@ -1774,7 +1774,7 @@ static inline void stm32l4_epout_receive(struct stm32l4_ep_s *privep, } /**************************************************************************** - * Name: stm32l4_epout_request + * Name: stm32_epout_request * * Description: * This function is called when either @@ -1784,10 +1784,10 @@ static inline void stm32l4_epout_receive(struct stm32l4_ep_s *privep, * ****************************************************************************/ -static void stm32l4_epout_request(struct stm32l4_usbdev_s *priv, - struct stm32l4_ep_s *privep) +static void stm32_epout_request(struct stm32_usbdev_s *priv, + struct stm32_ep_s *privep) { - struct stm32l4_req_s *privreq; + struct stm32_req_s *privreq; uint32_t regaddr; uint32_t regval; uint32_t xfrsize; @@ -1811,10 +1811,10 @@ static void stm32l4_epout_request(struct stm32l4_usbdev_s *priv, * request queue */ - privreq = stm32l4_rqpeek(privep); + privreq = stm32_rqpeek(privep); if (!privreq) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_EPOUTQEMPTY), + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EPOUTQEMPTY), privep->epphy); /* There are no read requests to be setup. Configure the @@ -1823,10 +1823,10 @@ static void stm32l4_epout_request(struct stm32l4_usbdev_s *priv, * NAK after a transfer is completed until SNAK is cleared). */ - regaddr = STM32L4_OTGFS_DOEPCTL(privep->epphy); - regval = stm32l4_getreg(regaddr); + regaddr = STM32_OTGFS_DOEPCTL(privep->epphy); + regval = stm32_getreg(regaddr); regval |= OTGFS_DOEPCTL_SNAK; - stm32l4_putreg(regval, regaddr); + stm32_putreg(regval, regaddr); /* This endpoint is no longer actively transferring */ @@ -1842,8 +1842,8 @@ static void stm32l4_epout_request(struct stm32l4_usbdev_s *priv, if (privreq->req.len <= 0) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_EPOUTNULLPACKET), 0); - stm32l4_req_complete(privep, OK); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EPOUTNULLPACKET), 0); + stm32_req_complete(privep, OK); } /* Otherwise, we have a usable read request... @@ -1870,17 +1870,17 @@ static void stm32l4_epout_request(struct stm32l4_usbdev_s *priv, /* Then setup the hardware to perform this transfer */ - regaddr = STM32L4_OTGFS_DOEPTSIZ(privep->epphy); - regval = stm32l4_getreg(regaddr); + regaddr = STM32_OTGFS_DOEPTSIZ(privep->epphy); + regval = stm32_getreg(regaddr); regval &= ~(OTGFS_DOEPTSIZ_XFRSIZ_MASK | OTGFS_DOEPTSIZ_PKTCNT_MASK); regval |= (xfrsize << OTGFS_DOEPTSIZ_XFRSIZ_SHIFT); regval |= (pktcnt << OTGFS_DOEPTSIZ_PKTCNT_SHIFT); - stm32l4_putreg(regval, regaddr); + stm32_putreg(regval, regaddr); /* Then enable the transfer */ - regaddr = STM32L4_OTGFS_DOEPCTL(privep->epphy); - regval = stm32l4_getreg(regaddr); + regaddr = STM32_OTGFS_DOEPCTL(privep->epphy); + regval = stm32_getreg(regaddr); /* When an isochronous transfer is enabled the Even/Odd frame bit must * also be set appropriately. @@ -1903,7 +1903,7 @@ static void stm32l4_epout_request(struct stm32l4_usbdev_s *priv, /* Clearing NAKing and enable the transfer. */ regval |= (OTGFS_DOEPCTL_CNAK | OTGFS_DOEPCTL_EPENA); - stm32l4_putreg(regval, regaddr); + stm32_putreg(regval, regaddr); /* A transfer is now active on this endpoint */ @@ -1921,27 +1921,27 @@ static void stm32l4_epout_request(struct stm32l4_usbdev_s *priv, } /**************************************************************************** - * Name: stm32l4_ep_flush + * Name: stm32_ep_flush * * Description: * Flush any primed descriptors from this ep * ****************************************************************************/ -static void stm32l4_ep_flush(struct stm32l4_ep_s *privep) +static void stm32_ep_flush(struct stm32_ep_s *privep) { if (privep->isin) { - stm32l4_txfifo_flush(OTGFS_GRSTCTL_TXFNUM_D(privep->epphy)); + stm32_txfifo_flush(OTGFS_GRSTCTL_TXFNUM_D(privep->epphy)); } else { - stm32l4_rxfifo_flush(); + stm32_rxfifo_flush(); } } /**************************************************************************** - * Name: stm32l4_req_complete + * Name: stm32_req_complete * * Description: * Handle termination of the request at the head of the endpoint request @@ -1949,14 +1949,14 @@ static void stm32l4_ep_flush(struct stm32l4_ep_s *privep) * ****************************************************************************/ -static void stm32l4_req_complete(struct stm32l4_ep_s *privep, +static void stm32_req_complete(struct stm32_ep_s *privep, int16_t result) { - struct stm32l4_req_s *privreq; + struct stm32_req_s *privreq; /* Remove the request at the head of the request list */ - privreq = stm32l4_req_remfirst(privep); + privreq = stm32_req_remfirst(privep); DEBUGASSERT(privreq != NULL); /* If endpoint 0, temporarily reflect the state of protocol stalled @@ -1983,30 +1983,30 @@ static void stm32l4_req_complete(struct stm32l4_ep_s *privep, } /**************************************************************************** - * Name: stm32l4_req_cancel + * Name: stm32_req_cancel * * Description: * Cancel all pending requests for an endpoint * ****************************************************************************/ -static void stm32l4_req_cancel(struct stm32l4_ep_s *privep, int16_t status) +static void stm32_req_cancel(struct stm32_ep_s *privep, int16_t status) { - if (!stm32l4_rqempty(privep)) + if (!stm32_rqempty(privep)) { - stm32l4_ep_flush(privep); + stm32_ep_flush(privep); } - while (!stm32l4_rqempty(privep)) + while (!stm32_rqempty(privep)) { usbtrace(TRACE_COMPLETE(privep->epphy), - (stm32l4_rqpeek(privep))->req.xfrd); - stm32l4_req_complete(privep, status); + (stm32_rqpeek(privep))->req.xfrd); + stm32_req_complete(privep, status); } } /**************************************************************************** - * Name: stm32l4_ep_findbyaddr + * Name: stm32_ep_findbyaddr * * Description: * Find the physical endpoint structure corresponding to a logic endpoint @@ -2015,13 +2015,13 @@ static void stm32l4_req_cancel(struct stm32l4_ep_s *privep, int16_t status) ****************************************************************************/ static -struct stm32l4_ep_s *stm32l4_ep_findbyaddr(struct stm32l4_usbdev_s *priv, +struct stm32_ep_s *stm32_ep_findbyaddr(struct stm32_usbdev_s *priv, uint16_t eplog) { - struct stm32l4_ep_s *privep; + struct stm32_ep_s *privep; uint8_t epphy = USB_EPNO(eplog); - if (epphy >= STM32L4_NENDPOINTS) + if (epphy >= STM32_NENDPOINTS) { return NULL; } @@ -2044,7 +2044,7 @@ struct stm32l4_ep_s *stm32l4_ep_findbyaddr(struct stm32l4_usbdev_s *priv, } /**************************************************************************** - * Name: stm32l4_req_dispatch + * Name: stm32_req_dispatch * * Description: * Provide unhandled setup actions to the class driver. This is logically @@ -2052,12 +2052,12 @@ struct stm32l4_ep_s *stm32l4_ep_findbyaddr(struct stm32l4_usbdev_s *priv, * ****************************************************************************/ -static int stm32l4_req_dispatch(struct stm32l4_usbdev_s *priv, +static int stm32_req_dispatch(struct stm32_usbdev_s *priv, const struct usb_ctrlreq_s *ctrl) { int ret = -EIO; - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_DISPATCH), 0); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_DISPATCH), 0); if (priv->driver) { /* Forward to the control request to the class driver implementation */ @@ -2070,7 +2070,7 @@ static int stm32l4_req_dispatch(struct stm32l4_usbdev_s *priv, { /* Stall on failure */ - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_DISPATCHSTALL), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_DISPATCHSTALL), 0); priv->stalled = true; } @@ -2078,28 +2078,28 @@ static int stm32l4_req_dispatch(struct stm32l4_usbdev_s *priv, } /**************************************************************************** - * Name: stm32l4_usbreset + * Name: stm32_usbreset * * Description: * Reset Usb engine * ****************************************************************************/ -static void stm32l4_usbreset(struct stm32l4_usbdev_s *priv) +static void stm32_usbreset(struct stm32_usbdev_s *priv) { - struct stm32l4_ep_s *privep; + struct stm32_ep_s *privep; uint32_t regval; int i; /* Clear the Remote Wake-up Signaling */ - regval = stm32l4_getreg(STM32L4_OTGFS_DCTL); + regval = stm32_getreg(STM32_OTGFS_DCTL); regval &= ~OTGFS_DCTL_RWUSIG; - stm32l4_putreg(regval, STM32L4_OTGFS_DCTL); + stm32_putreg(regval, STM32_OTGFS_DCTL); /* Flush the EP0 Tx FIFO */ - stm32l4_txfifo_flush(OTGFS_GRSTCTL_TXFNUM_D(EP0)); + stm32_txfifo_flush(OTGFS_GRSTCTL_TXFNUM_D(EP0)); /* Tell the class driver that we are disconnected. The class * driver should then accept any new configurations. @@ -2112,22 +2112,22 @@ static void stm32l4_usbreset(struct stm32l4_usbdev_s *priv) /* Mark all endpoints as available */ - priv->epavail[0] = STM32L4_EP_AVAILABLE; - priv->epavail[1] = STM32L4_EP_AVAILABLE; + priv->epavail[0] = STM32_EP_AVAILABLE; + priv->epavail[1] = STM32_EP_AVAILABLE; /* Disable all end point interrupts */ - for (i = 0; i < STM32L4_NENDPOINTS ; i++) + for (i = 0; i < STM32_NENDPOINTS ; i++) { /* Disable endpoint interrupts */ - stm32l4_putreg(0xff, STM32L4_OTGFS_DIEPINT(i)); - stm32l4_putreg(0xff, STM32L4_OTGFS_DOEPINT(i)); + stm32_putreg(0xff, STM32_OTGFS_DIEPINT(i)); + stm32_putreg(0xff, STM32_OTGFS_DOEPINT(i)); /* Return write requests to the class implementation */ privep = &priv->epin[i]; - stm32l4_req_cancel(privep, -ESHUTDOWN); + stm32_req_cancel(privep, -ESHUTDOWN); /* Reset IN endpoint status */ @@ -2136,54 +2136,54 @@ static void stm32l4_usbreset(struct stm32l4_usbdev_s *priv) /* Return read requests to the class implementation */ privep = &priv->epout[i]; - stm32l4_req_cancel(privep, -ESHUTDOWN); + stm32_req_cancel(privep, -ESHUTDOWN); /* Reset endpoint status */ privep->stalled = false; } - stm32l4_putreg(0xffffffff, STM32L4_OTGFS_DAINT); + stm32_putreg(0xffffffff, STM32_OTGFS_DAINT); /* Mask all device endpoint interrupts except EP0 */ regval = (OTGFS_DAINT_IEP(EP0) | OTGFS_DAINT_OEP(EP0)); - stm32l4_putreg(regval, STM32L4_OTGFS_DAINTMSK); + stm32_putreg(regval, STM32_OTGFS_DAINTMSK); /* Unmask OUT interrupts */ regval = (OTGFS_DOEPMSK_XFRCM | OTGFS_DOEPMSK_STUPM | OTGFS_DOEPMSK_EPDM); - stm32l4_putreg(regval, STM32L4_OTGFS_DOEPMSK); + stm32_putreg(regval, STM32_OTGFS_DOEPMSK); /* Unmask IN interrupts */ regval = (OTGFS_DIEPMSK_XFRCM | OTGFS_DIEPMSK_EPDM | OTGFS_DIEPMSK_TOM); - stm32l4_putreg(regval, STM32L4_OTGFS_DIEPMSK); + stm32_putreg(regval, STM32_OTGFS_DIEPMSK); /* Reset device address to 0 */ - stm32l4_setaddress(priv, 0); + stm32_setaddress(priv, 0); priv->devstate = DEVSTATE_DEFAULT; priv->usbdev.speed = USB_SPEED_FULL; /* Re-configure EP0 */ - stm32l4_ep0_configure(priv); + stm32_ep0_configure(priv); /* Setup EP0 to receive SETUP packets */ - stm32l4_ep0out_ctrlsetup(priv); + stm32_ep0out_ctrlsetup(priv); } /**************************************************************************** - * Name: stm32l4_ep0out_testmode + * Name: stm32_ep0out_testmode * * Description: * Select test mode * ****************************************************************************/ -static inline void stm32l4_ep0out_testmode(struct stm32l4_usbdev_s *priv, +static inline void stm32_ep0out_testmode(struct stm32_usbdev_s *priv, uint16_t index) { uint8_t testmode; @@ -2212,18 +2212,18 @@ static inline void stm32l4_ep0out_testmode(struct stm32l4_usbdev_s *priv, break; default: - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_BADTESTMODE), testmode); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADTESTMODE), testmode); priv->dotest = false; priv->testmode = OTGFS_TESTMODE_DISABLED; priv->stalled = true; } priv->dotest = true; - stm32l4_ep0in_transmitzlp(priv); + stm32_ep0in_transmitzlp(priv); } /**************************************************************************** - * Name: stm32l4_ep0out_stdrequest + * Name: stm32_ep0out_stdrequest * * Description: * Handle a standard request on EP0. Pick off the things of interest to @@ -2232,10 +2232,10 @@ static inline void stm32l4_ep0out_testmode(struct stm32l4_usbdev_s *priv, ****************************************************************************/ static inline -void stm32l4_ep0out_stdrequest(struct stm32l4_usbdev_s *priv, - struct stm32l4_ctrlreq_s *ctrlreq) +void stm32_ep0out_stdrequest(struct stm32_usbdev_s *priv, + struct stm32_ctrlreq_s *ctrlreq) { - struct stm32l4_ep_s *privep; + struct stm32_ep_s *privep; /* Handle standard request */ @@ -2249,7 +2249,7 @@ void stm32l4_ep0out_stdrequest(struct stm32l4_usbdev_s *priv, * len: 2; data = status */ - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_GETSTATUS), 0); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_GETSTATUS), 0); if (!priv->addressed || ctrlreq->len != 2 || USB_REQ_ISOUT(ctrlreq->type) || @@ -2264,12 +2264,12 @@ void stm32l4_ep0out_stdrequest(struct stm32l4_usbdev_s *priv, case USB_REQ_RECIPIENT_ENDPOINT: { usbtrace(TRACE_INTDECODE( - STM32L4_TRACEINTID_EPGETSTATUS), 0); - privep = stm32l4_ep_findbyaddr(priv, ctrlreq->index); + STM32_TRACEINTID_EPGETSTATUS), 0); + privep = stm32_ep_findbyaddr(priv, ctrlreq->index); if (!privep) { usbtrace(TRACE_DEVERROR( - STM32L4_TRACEERR_BADEPGETSTATUS), 0); + STM32_TRACEERR_BADEPGETSTATUS), 0); priv->stalled = true; } else @@ -2284,7 +2284,7 @@ void stm32l4_ep0out_stdrequest(struct stm32l4_usbdev_s *priv, } priv->ep0data[1] = 0; - stm32l4_ep0in_setupresponse(priv, priv->ep0data, 2); + stm32_ep0in_setupresponse(priv, priv->ep0data, 2); } } break; @@ -2294,7 +2294,7 @@ void stm32l4_ep0out_stdrequest(struct stm32l4_usbdev_s *priv, if (ctrlreq->index == 0) { usbtrace(TRACE_INTDECODE( - STM32L4_TRACEINTID_DEVGETSTATUS), 0); + STM32_TRACEINTID_DEVGETSTATUS), 0); /* Features: Remote Wakeup and self-powered */ @@ -2304,12 +2304,12 @@ void stm32l4_ep0out_stdrequest(struct stm32l4_usbdev_s *priv, USB_FEATURE_REMOTEWAKEUP); priv->ep0data[1] = 0; - stm32l4_ep0in_setupresponse(priv, priv->ep0data, 2); + stm32_ep0in_setupresponse(priv, priv->ep0data, 2); } else { usbtrace(TRACE_DEVERROR( - STM32L4_TRACEERR_BADDEVGETSTATUS), 0); + STM32_TRACEERR_BADDEVGETSTATUS), 0); priv->stalled = true; } } @@ -2318,18 +2318,18 @@ void stm32l4_ep0out_stdrequest(struct stm32l4_usbdev_s *priv, case USB_REQ_RECIPIENT_INTERFACE: { usbtrace(TRACE_INTDECODE( - STM32L4_TRACEINTID_IFGETSTATUS), 0); + STM32_TRACEINTID_IFGETSTATUS), 0); priv->ep0data[0] = 0; priv->ep0data[1] = 0; - stm32l4_ep0in_setupresponse(priv, priv->ep0data, 2); + stm32_ep0in_setupresponse(priv, priv->ep0data, 2); } break; default: { usbtrace(TRACE_DEVERROR( - STM32L4_TRACEERR_BADGETSTATUS), 0); + STM32_TRACEERR_BADGETSTATUS), 0); priv->stalled = true; } break; @@ -2346,34 +2346,34 @@ void stm32l4_ep0out_stdrequest(struct stm32l4_usbdev_s *priv, * len: zero, data = none */ - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_CLEARFEATURE), 0); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_CLEARFEATURE), 0); if (priv->addressed != 0 && ctrlreq->len == 0) { uint8_t recipient = ctrlreq->type & USB_REQ_RECIPIENT_MASK; if (recipient == USB_REQ_RECIPIENT_ENDPOINT && ctrlreq->value == USB_FEATURE_ENDPOINTHALT && - (privep = stm32l4_ep_findbyaddr(priv, ctrlreq->index)) != + (privep = stm32_ep_findbyaddr(priv, ctrlreq->index)) != NULL) { - stm32l4_ep_clrstall(privep); - stm32l4_ep0in_transmitzlp(priv); + stm32_ep_clrstall(privep); + stm32_ep0in_transmitzlp(priv); } else if (recipient == USB_REQ_RECIPIENT_DEVICE && ctrlreq->value == USB_FEATURE_REMOTEWAKEUP) { priv->wakeup = 0; - stm32l4_ep0in_transmitzlp(priv); + stm32_ep0in_transmitzlp(priv); } else { /* Actually, I think we could just stall here. */ - stm32l4_req_dispatch(priv, &priv->ctrlreq); + stm32_req_dispatch(priv, &priv->ctrlreq); } } else { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_BADCLEARFEATURE), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADCLEARFEATURE), 0); priv->stalled = true; } } @@ -2387,45 +2387,45 @@ void stm32l4_ep0out_stdrequest(struct stm32l4_usbdev_s *priv, * len: 0; data = none */ - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_SETFEATURE), 0); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SETFEATURE), 0); if (priv->addressed != 0 && ctrlreq->len == 0) { uint8_t recipient = ctrlreq->type & USB_REQ_RECIPIENT_MASK; if (recipient == USB_REQ_RECIPIENT_ENDPOINT && ctrlreq->value == USB_FEATURE_ENDPOINTHALT && - (privep = stm32l4_ep_findbyaddr(priv, ctrlreq->index)) != + (privep = stm32_ep_findbyaddr(priv, ctrlreq->index)) != NULL) { - stm32l4_ep_setstall(privep); - stm32l4_ep0in_transmitzlp(priv); + stm32_ep_setstall(privep); + stm32_ep0in_transmitzlp(priv); } else if (recipient == USB_REQ_RECIPIENT_DEVICE && ctrlreq->value == USB_FEATURE_REMOTEWAKEUP) { priv->wakeup = 1; - stm32l4_ep0in_transmitzlp(priv); + stm32_ep0in_transmitzlp(priv); } else if (recipient == USB_REQ_RECIPIENT_DEVICE && ctrlreq->value == USB_FEATURE_TESTMODE && ((ctrlreq->index & 0xff) == 0)) { - stm32l4_ep0out_testmode(priv, ctrlreq->index); + stm32_ep0out_testmode(priv, ctrlreq->index); } else if (priv->configured) { /* Actually, I think we could just stall here. */ - stm32l4_req_dispatch(priv, &priv->ctrlreq); + stm32_req_dispatch(priv, &priv->ctrlreq); } else { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_BADSETFEATURE), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADSETFEATURE), 0); priv->stalled = true; } } else { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_BADSETFEATURE), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADSETFEATURE), 0); priv->stalled = true; } } @@ -2439,7 +2439,7 @@ void stm32l4_ep0out_stdrequest(struct stm32l4_usbdev_s *priv, * len: 0; data = none */ - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_SETADDRESS), + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SETADDRESS), ctrlreq->value); if ((ctrlreq->type & USB_REQ_RECIPIENT_MASK) == USB_REQ_RECIPIENT_DEVICE && @@ -2452,12 +2452,12 @@ void stm32l4_ep0out_stdrequest(struct stm32l4_usbdev_s *priv, * address until the completion of the status phase. */ - stm32l4_setaddress(priv, (uint16_t)priv->ctrlreq.value[0]); - stm32l4_ep0in_transmitzlp(priv); + stm32_setaddress(priv, (uint16_t)priv->ctrlreq.value[0]); + stm32_ep0in_transmitzlp(priv); } else { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_BADSETADDRESS), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADSETADDRESS), 0); priv->stalled = true; } } @@ -2478,15 +2478,15 @@ void stm32l4_ep0out_stdrequest(struct stm32l4_usbdev_s *priv, */ { - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_GETSETDESC), 0); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_GETSETDESC), 0); if ((ctrlreq->type & USB_REQ_RECIPIENT_MASK) == USB_REQ_RECIPIENT_DEVICE) { - stm32l4_req_dispatch(priv, &priv->ctrlreq); + stm32_req_dispatch(priv, &priv->ctrlreq); } else { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_BADGETSETDESC), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADGETSETDESC), 0); priv->stalled = true; } } @@ -2500,7 +2500,7 @@ void stm32l4_ep0out_stdrequest(struct stm32l4_usbdev_s *priv, */ { - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_GETCONFIG), 0); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_GETCONFIG), 0); if (priv->addressed && (ctrlreq->type & USB_REQ_RECIPIENT_MASK) == USB_REQ_RECIPIENT_DEVICE && @@ -2508,11 +2508,11 @@ void stm32l4_ep0out_stdrequest(struct stm32l4_usbdev_s *priv, ctrlreq->index == 0 && ctrlreq->len == 1) { - stm32l4_req_dispatch(priv, &priv->ctrlreq); + stm32_req_dispatch(priv, &priv->ctrlreq); } else { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_BADGETCONFIG), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADGETCONFIG), 0); priv->stalled = true; } } @@ -2526,7 +2526,7 @@ void stm32l4_ep0out_stdrequest(struct stm32l4_usbdev_s *priv, */ { - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_SETCONFIG), 0); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SETCONFIG), 0); if (priv->addressed && (ctrlreq->type & USB_REQ_RECIPIENT_MASK) == USB_REQ_RECIPIENT_DEVICE && @@ -2535,7 +2535,7 @@ void stm32l4_ep0out_stdrequest(struct stm32l4_usbdev_s *priv, { /* Give the configuration to the class driver */ - int ret = stm32l4_req_dispatch(priv, &priv->ctrlreq); + int ret = stm32_req_dispatch(priv, &priv->ctrlreq); /* If the class driver accepted the configuration, then mark the * device state as configured (or not, depending on the @@ -2559,7 +2559,7 @@ void stm32l4_ep0out_stdrequest(struct stm32l4_usbdev_s *priv, } else { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_BADSETCONFIG), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADSETCONFIG), 0); priv->stalled = true; } } @@ -2580,8 +2580,8 @@ void stm32l4_ep0out_stdrequest(struct stm32l4_usbdev_s *priv, */ { - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_GETSETIF), 0); - stm32l4_req_dispatch(priv, &priv->ctrlreq); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_GETSETIF), 0); + stm32_req_dispatch(priv, &priv->ctrlreq); } break; @@ -2593,13 +2593,13 @@ void stm32l4_ep0out_stdrequest(struct stm32l4_usbdev_s *priv, */ { - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_SYNCHFRAME), 0); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SYNCHFRAME), 0); } break; default: { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_INVALIDCTRLREQ), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDCTRLREQ), 0); priv->stalled = true; } break; @@ -2607,7 +2607,7 @@ void stm32l4_ep0out_stdrequest(struct stm32l4_usbdev_s *priv, } /**************************************************************************** - * Name: stm32l4_ep0out_setup + * Name: stm32_ep0out_setup * * Description: * USB Ctrl EP Setup Event. This is logically part of the USB interrupt @@ -2615,22 +2615,22 @@ void stm32l4_ep0out_stdrequest(struct stm32l4_usbdev_s *priv, * ****************************************************************************/ -static inline void stm32l4_ep0out_setup(struct stm32l4_usbdev_s *priv) +static inline void stm32_ep0out_setup(struct stm32_usbdev_s *priv) { - struct stm32l4_ctrlreq_s ctrlreq; + struct stm32_ctrlreq_s ctrlreq; /* Verify that a SETUP was received */ if (priv->ep0state != EP0STATE_SETUP_READY) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_EP0NOSETUP), priv->ep0state); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EP0NOSETUP), priv->ep0state); return; } /* Terminate any pending requests */ - stm32l4_req_cancel(&priv->epout[EP0], -EPROTO); - stm32l4_req_cancel(&priv->epin[EP0], -EPROTO); + stm32_req_cancel(&priv->epout[EP0], -EPROTO); + stm32_req_cancel(&priv->epin[EP0], -EPROTO); /* Assume NOT stalled */ @@ -2660,22 +2660,22 @@ static inline void stm32l4_ep0out_setup(struct stm32l4_usbdev_s *priv) { /* Dispatch any non-standard requests */ - stm32l4_req_dispatch(priv, &priv->ctrlreq); + stm32_req_dispatch(priv, &priv->ctrlreq); } else { /* Handle standard requests. */ - stm32l4_ep0out_stdrequest(priv, &ctrlreq); + stm32_ep0out_stdrequest(priv, &ctrlreq); } /* Check if the setup processing resulted in a STALL */ if (priv->stalled) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_EP0SETUPSTALLED), + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EP0SETUPSTALLED), priv->ep0state); - stm32l4_ep0_stall(priv); + stm32_ep0_stall(priv); } /* Reset state/data associated with the SETUP request */ @@ -2684,7 +2684,7 @@ static inline void stm32l4_ep0out_setup(struct stm32l4_usbdev_s *priv) } /**************************************************************************** - * Name: stm32l4_epout + * Name: stm32_epout * * Description: * This is part of the OUT endpoint interrupt processing. This function @@ -2692,10 +2692,10 @@ static inline void stm32l4_ep0out_setup(struct stm32l4_usbdev_s *priv) * ****************************************************************************/ -static inline void stm32l4_epout(struct stm32l4_usbdev_s *priv, +static inline void stm32_epout(struct stm32_usbdev_s *priv, uint8_t epno) { - struct stm32l4_ep_s *privep; + struct stm32_ep_s *privep; /* Endpoint 0 is a special case. */ @@ -2712,7 +2712,7 @@ static inline void stm32l4_epout(struct stm32l4_usbdev_s *priv, { /* Continue processing data from the EP0 OUT request queue */ - stm32l4_epout_complete(priv, privep); + stm32_epout_complete(priv, privep); /* If we are not actively processing an OUT request, then we * need to setup to receive the next control request. @@ -2720,7 +2720,7 @@ static inline void stm32l4_epout(struct stm32l4_usbdev_s *priv, if (!privep->active) { - stm32l4_ep0out_ctrlsetup(priv); + stm32_ep0out_ctrlsetup(priv); priv->ep0state = EP0STATE_IDLE; } } @@ -2732,12 +2732,12 @@ static inline void stm32l4_epout(struct stm32l4_usbdev_s *priv, else if (priv->devstate == DEVSTATE_CONFIGURED) { - stm32l4_epout_complete(priv, &priv->epout[epno]); + stm32_epout_complete(priv, &priv->epout[epno]); } } /**************************************************************************** - * Name: stm32l4_epout_interrupt + * Name: stm32_epout_interrupt * * Description: * USB OUT endpoint interrupt handler. @@ -2750,7 +2750,7 @@ static inline void stm32l4_epout(struct stm32l4_usbdev_s *priv, * ****************************************************************************/ -static inline void stm32l4_epout_interrupt(struct stm32l4_usbdev_s *priv) +static inline void stm32_epout_interrupt(struct stm32_usbdev_s *priv) { uint32_t daint; uint32_t regval; @@ -2761,8 +2761,8 @@ static inline void stm32l4_epout_interrupt(struct stm32l4_usbdev_s *priv) * endpoint interrupt status register. */ - regval = stm32l4_getreg(STM32L4_OTGFS_DAINT); - regval &= stm32l4_getreg(STM32L4_OTGFS_DAINTMSK); + regval = stm32_getreg(STM32_OTGFS_DAINT); + regval &= stm32_getreg(STM32_OTGFS_DAINTMSK); daint = (regval & OTGFS_DAINT_OEP_MASK) >> OTGFS_DAINT_OEP_SHIFT; if (daint == 0) @@ -2777,10 +2777,10 @@ static inline void stm32l4_epout_interrupt(struct stm32l4_usbdev_s *priv) * It works by clearing each endpoint flags, masked or not. */ - regval = stm32l4_getreg(STM32L4_OTGFS_DAINT); + regval = stm32_getreg(STM32_OTGFS_DAINT); daint = (regval & OTGFS_DAINT_OEP_MASK) >> OTGFS_DAINT_OEP_SHIFT; - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_EPOUTUNEXPECTED), + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EPOUTUNEXPECTED), (uint16_t)regval); epno = 0; @@ -2788,9 +2788,9 @@ static inline void stm32l4_epout_interrupt(struct stm32l4_usbdev_s *priv) { if ((daint & 1) != 0) { - regval = stm32l4_getreg(STM32L4_OTGFS_DOEPINT(epno)); + regval = stm32_getreg(STM32_OTGFS_DOEPINT(epno)); uinfo("DOEPINT(%d) = %08" PRIx32 "\n", epno, regval); - stm32l4_putreg(0xff, STM32L4_OTGFS_DOEPINT(epno)); + stm32_putreg(0xff, STM32_OTGFS_DOEPINT(epno)); } epno++; @@ -2811,11 +2811,11 @@ static inline void stm32l4_epout_interrupt(struct stm32l4_usbdev_s *priv) { /* Yes.. get the OUT endpoint interrupt status */ - doepint = stm32l4_getreg(STM32L4_OTGFS_DOEPINT(epno)); - doepint &= stm32l4_getreg(STM32L4_OTGFS_DOEPMSK); + doepint = stm32_getreg(STM32_OTGFS_DOEPINT(epno)); + doepint &= stm32_getreg(STM32_OTGFS_DOEPMSK); /* Transfer completed interrupt. - * This interrupt is triggered when stm32l4_rxinterrupt() removes + * This interrupt is triggered when stm32_rxinterrupt() removes * the last packet data from the RxFIFO. * In this case, core internally sets the NAK bit for this endpoint * to prevent it from receiving any more packets. @@ -2823,17 +2823,17 @@ static inline void stm32l4_epout_interrupt(struct stm32l4_usbdev_s *priv) if ((doepint & OTGFS_DOEPINT_XFRC) != 0) { - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_EPOUT_XFRC), + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPOUT_XFRC), (uint16_t)doepint); /* Clear the bit in DOEPINTn for this interrupt */ - stm32l4_putreg(OTGFS_DOEPINT_XFRC, - STM32L4_OTGFS_DOEPINT(epno)); + stm32_putreg(OTGFS_DOEPINT_XFRC, + STM32_OTGFS_DOEPINT(epno)); /* Handle the RX transfer data ready event */ - stm32l4_epout(priv, epno); + stm32_epout(priv, epno); } /* Endpoint disabled interrupt (ignored because this interrupt is @@ -2844,13 +2844,13 @@ static inline void stm32l4_epout_interrupt(struct stm32l4_usbdev_s *priv) if ((doepint & OTGFS_DOEPINT_EPDISD) != 0) { - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_EPOUT_EPDISD), + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPOUT_EPDISD), (uint16_t)doepint); /* Clear the bit in DOEPINTn for this interrupt */ - stm32l4_putreg(OTGFS_DOEPINT_EPDISD, - STM32L4_OTGFS_DOEPINT(epno)); + stm32_putreg(OTGFS_DOEPINT_EPDISD, + STM32_OTGFS_DOEPINT(epno)); } #endif @@ -2858,7 +2858,7 @@ static inline void stm32l4_epout_interrupt(struct stm32l4_usbdev_s *priv) if ((doepint & OTGFS_DOEPINT_SETUP) != 0) { - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_EPOUT_SETUP), + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPOUT_SETUP), priv->ep0state); /* Handle the receipt of the IN SETUP packets now (OUT setup @@ -2868,11 +2868,11 @@ static inline void stm32l4_epout_interrupt(struct stm32l4_usbdev_s *priv) if (priv->ep0state == EP0STATE_SETUP_READY) { - stm32l4_ep0out_setup(priv); + stm32_ep0out_setup(priv); } - stm32l4_putreg(OTGFS_DOEPINT_SETUP, - STM32L4_OTGFS_DOEPINT(epno)); + stm32_putreg(OTGFS_DOEPINT_SETUP, + STM32_OTGFS_DOEPINT(epno)); } } @@ -2882,7 +2882,7 @@ static inline void stm32l4_epout_interrupt(struct stm32l4_usbdev_s *priv) } /**************************************************************************** - * Name: stm32l4_epin_runtestmode + * Name: stm32_epin_runtestmode * * Description: * Execute the test mode setup by the SET FEATURE request @@ -2890,19 +2890,19 @@ static inline void stm32l4_epout_interrupt(struct stm32l4_usbdev_s *priv) ****************************************************************************/ static inline -void stm32l4_epin_runtestmode(struct stm32l4_usbdev_s *priv) +void stm32_epin_runtestmode(struct stm32_usbdev_s *priv) { - uint32_t regval = stm32l4_getreg(STM32L4_OTGFS_DCTL); + uint32_t regval = stm32_getreg(STM32_OTGFS_DCTL); regval &= OTGFS_DCTL_TCTL_MASK; regval |= (uint32_t)priv->testmode << OTGFS_DCTL_TCTL_SHIFT; - stm32l4_putreg(regval , STM32L4_OTGFS_DCTL); + stm32_putreg(regval , STM32_OTGFS_DCTL); priv->dotest = 0; priv->testmode = OTGFS_TESTMODE_DISABLED; } /**************************************************************************** - * Name: stm32l4_epin + * Name: stm32_epin * * Description: * This is part of the IN endpoint interrupt processing. This function @@ -2910,10 +2910,10 @@ void stm32l4_epin_runtestmode(struct stm32l4_usbdev_s *priv) * ****************************************************************************/ -static inline void stm32l4_epin(struct stm32l4_usbdev_s *priv, +static inline void stm32_epin(struct stm32_usbdev_s *priv, uint8_t epno) { - struct stm32l4_ep_s *privep = &priv->epin[epno]; + struct stm32_ep_s *privep = &priv->epin[epno]; /* Endpoint 0 is a special case. */ @@ -2927,7 +2927,7 @@ static inline void stm32l4_epin(struct stm32l4_usbdev_s *priv, { /* Continue processing data from the EP0 OUT request queue */ - stm32l4_epin_request(priv, privep); + stm32_epin_request(priv, privep); /* If we are not actively processing an OUT request, then we * need to setup to receive the next control request. @@ -2935,7 +2935,7 @@ static inline void stm32l4_epin(struct stm32l4_usbdev_s *priv, if (!privep->active) { - stm32l4_ep0out_ctrlsetup(priv); + stm32_ep0out_ctrlsetup(priv); priv->ep0state = EP0STATE_IDLE; } } @@ -2944,7 +2944,7 @@ static inline void stm32l4_epin(struct stm32l4_usbdev_s *priv, if (priv->dotest) { - stm32l4_epin_runtestmode(priv); + stm32_epin_runtestmode(priv); } } @@ -2956,12 +2956,12 @@ static inline void stm32l4_epin(struct stm32l4_usbdev_s *priv, { /* Continue processing data from the endpoint write request queue */ - stm32l4_epin_request(priv, privep); + stm32_epin_request(priv, privep); } } /**************************************************************************** - * Name: stm32l4_epin_txfifoempty + * Name: stm32_epin_txfifoempty * * Description: * TxFIFO empty interrupt handling @@ -2969,20 +2969,20 @@ static inline void stm32l4_epin(struct stm32l4_usbdev_s *priv, ****************************************************************************/ static inline -void stm32l4_epin_txfifoempty(struct stm32l4_usbdev_s *priv, int epno) +void stm32_epin_txfifoempty(struct stm32_usbdev_s *priv, int epno) { - struct stm32l4_ep_s *privep = &priv->epin[epno]; + struct stm32_ep_s *privep = &priv->epin[epno]; /* Continue processing the write request queue. This may mean sending * more data from the existing request or terminating the current requests * and (perhaps) starting the IN transfer from the next write request. */ - stm32l4_epin_request(priv, privep); + stm32_epin_request(priv, privep); } /**************************************************************************** - * Name: stm32l4_epin_interrupt + * Name: stm32_epin_interrupt * * Description: * USB IN endpoint interrupt handler. The core generates this interrupt @@ -2994,7 +2994,7 @@ void stm32l4_epin_txfifoempty(struct stm32l4_usbdev_s *priv, int epno) * ****************************************************************************/ -static inline void stm32l4_epin_interrupt(struct stm32l4_usbdev_s *priv) +static inline void stm32_epin_interrupt(struct stm32_usbdev_s *priv) { uint32_t diepint; uint32_t daint; @@ -3006,8 +3006,8 @@ static inline void stm32l4_epin_interrupt(struct stm32l4_usbdev_s *priv) * endpoint interrupt status register. */ - daint = stm32l4_getreg(STM32L4_OTGFS_DAINT); - daint &= stm32l4_getreg(STM32L4_OTGFS_DAINTMSK); + daint = stm32_getreg(STM32_OTGFS_DAINT); + daint &= stm32_getreg(STM32_OTGFS_DAINTMSK); daint &= OTGFS_DAINT_IEP_MASK; if (daint == 0) @@ -3022,8 +3022,8 @@ static inline void stm32l4_epin_interrupt(struct stm32l4_usbdev_s *priv) * It works by clearing each endpoint flags, masked or not. */ - daint = stm32l4_getreg(STM32L4_OTGFS_DAINT); - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_EPINUNEXPECTED), + daint = stm32_getreg(STM32_OTGFS_DAINT); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EPINUNEXPECTED), (uint16_t)daint); daint &= OTGFS_DAINT_IEP_MASK; @@ -3034,8 +3034,8 @@ static inline void stm32l4_epin_interrupt(struct stm32l4_usbdev_s *priv) if ((daint & 1) != 0) { uerr("DIEPINT(%d) = %08" PRIx32 "\n", - epno, stm32l4_getreg(STM32L4_OTGFS_DIEPINT(epno))); - stm32l4_putreg(0xff, STM32L4_OTGFS_DIEPINT(epno)); + epno, stm32_getreg(STM32_OTGFS_DIEPINT(epno))); + stm32_putreg(0xff, STM32_OTGFS_DIEPINT(epno)); } epno++; @@ -3059,7 +3059,7 @@ static inline void stm32l4_epin_interrupt(struct stm32l4_usbdev_s *priv) * register. */ - mask = stm32l4_getreg(STM32L4_OTGFS_DIEPMSK); + mask = stm32_getreg(STM32_OTGFS_DIEPMSK); /* Check if the TxFIFO not empty interrupt is enabled for this * endpoint in the DIEPMSK register. Bits n corresponds to @@ -3068,7 +3068,7 @@ static inline void stm32l4_epin_interrupt(struct stm32l4_usbdev_s *priv) * no TXFE bit in the mask register, so we fake one here. */ - empty = stm32l4_getreg(STM32L4_OTGFS_DIEPEMPMSK); + empty = stm32_getreg(STM32_OTGFS_DIEPEMPMSK); if ((empty & OTGFS_DIEPEMPMSK(epno)) != 0) { mask |= OTGFS_DIEPINT_TXFE; @@ -3078,7 +3078,7 @@ static inline void stm32l4_epin_interrupt(struct stm32l4_usbdev_s *priv) * interrupts. */ - diepint = stm32l4_getreg(STM32L4_OTGFS_DIEPINT(epno)) & mask; + diepint = stm32_getreg(STM32_OTGFS_DIEPINT(epno)) & mask; /* Decode and process the enabled, pending interrupts */ @@ -3086,7 +3086,7 @@ static inline void stm32l4_epin_interrupt(struct stm32l4_usbdev_s *priv) if ((diepint & OTGFS_DIEPINT_XFRC) != 0) { - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_EPIN_XFRC), + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPIN_XFRC), (uint16_t)diepint); /* It is possible that logic may be waiting for a the @@ -3096,22 +3096,22 @@ static inline void stm32l4_epin_interrupt(struct stm32l4_usbdev_s *priv) */ empty &= ~OTGFS_DIEPEMPMSK(epno); - stm32l4_putreg(empty, STM32L4_OTGFS_DIEPEMPMSK); - stm32l4_putreg(OTGFS_DIEPINT_XFRC, - STM32L4_OTGFS_DIEPINT(epno)); + stm32_putreg(empty, STM32_OTGFS_DIEPEMPMSK); + stm32_putreg(OTGFS_DIEPINT_XFRC, + STM32_OTGFS_DIEPINT(epno)); /* IN transfer complete */ - stm32l4_epin(priv, epno); + stm32_epin(priv, epno); } /* Timeout condition */ if ((diepint & OTGFS_DIEPINT_TOC) != 0) { - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_EPIN_TOC), + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPIN_TOC), (uint16_t)diepint); - stm32l4_putreg(OTGFS_DIEPINT_TOC, STM32L4_OTGFS_DIEPINT(epno)); + stm32_putreg(OTGFS_DIEPINT_TOC, STM32_OTGFS_DIEPINT(epno)); } /* IN token received when TxFIFO is empty. Applies to non-periodic @@ -3123,11 +3123,11 @@ static inline void stm32l4_epin_interrupt(struct stm32l4_usbdev_s *priv) if ((diepint & OTGFS_DIEPINT_ITTXFE) != 0) { - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_EPIN_ITTXFE), + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPIN_ITTXFE), (uint16_t)diepint); - stm32l4_epin_request(priv, &priv->epin[epno]); - stm32l4_putreg(OTGFS_DIEPINT_ITTXFE, - STM32L4_OTGFS_DIEPINT(epno)); + stm32_epin_request(priv, &priv->epin[epno]); + stm32_putreg(OTGFS_DIEPINT_ITTXFE, + STM32_OTGFS_DIEPINT(epno)); } /* IN endpoint NAK effective (ignored as this used only in polled @@ -3136,10 +3136,10 @@ static inline void stm32l4_epin_interrupt(struct stm32l4_usbdev_s *priv) #if 0 if ((diepint & OTGFS_DIEPINT_INEPNE) != 0) { - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_EPIN_INEPNE), + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPIN_INEPNE), (uint16_t)diepint); - stm32l4_putreg(OTGFS_DIEPINT_INEPNE, - STM32L4_OTGFS_DIEPINT(epno)); + stm32_putreg(OTGFS_DIEPINT_INEPNE, + STM32_OTGFS_DIEPINT(epno)); } #endif @@ -3149,10 +3149,10 @@ static inline void stm32l4_epin_interrupt(struct stm32l4_usbdev_s *priv) #if 0 if ((diepint & OTGFS_DIEPINT_EPDISD) != 0) { - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_EPIN_EPDISD), + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPIN_EPDISD), (uint16_t)diepint); - stm32l4_putreg(OTGFS_DIEPINT_EPDISD, - STM32L4_OTGFS_DIEPINT(epno)); + stm32_putreg(OTGFS_DIEPINT_EPDISD, + STM32_OTGFS_DIEPINT(epno)); } #endif @@ -3160,7 +3160,7 @@ static inline void stm32l4_epin_interrupt(struct stm32l4_usbdev_s *priv) if ((diepint & OTGFS_DIEPINT_TXFE) != 0) { - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_EPIN_TXFE), + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPIN_TXFE), (uint16_t)diepint); /* If we were waiting for TxFIFO to become empty, the we might @@ -3176,17 +3176,17 @@ static inline void stm32l4_epin_interrupt(struct stm32l4_usbdev_s *priv) */ empty &= ~OTGFS_DIEPEMPMSK(epno); - stm32l4_putreg(empty, STM32L4_OTGFS_DIEPEMPMSK); + stm32_putreg(empty, STM32_OTGFS_DIEPEMPMSK); /* Handle TxFIFO empty */ - stm32l4_epin_txfifoempty(priv, epno); + stm32_epin_txfifoempty(priv, epno); } /* Clear the pending TxFIFO empty interrupt */ - stm32l4_putreg(OTGFS_DIEPINT_TXFE, - STM32L4_OTGFS_DIEPINT(epno)); + stm32_putreg(OTGFS_DIEPINT_TXFE, + STM32_OTGFS_DIEPINT(epno)); } } @@ -3196,34 +3196,34 @@ static inline void stm32l4_epin_interrupt(struct stm32l4_usbdev_s *priv) } /**************************************************************************** - * Name: stm32l4_resumeinterrupt + * Name: stm32_resumeinterrupt * * Description: * Resume/remote wakeup detected interrupt * ****************************************************************************/ -static inline void stm32l4_resumeinterrupt(struct stm32l4_usbdev_s *priv) +static inline void stm32_resumeinterrupt(struct stm32_usbdev_s *priv) { uint32_t regval; /* Restart the PHY clock and un-gate USB core clock (HCLK) */ #ifdef CONFIG_USBDEV_LOWPOWER - regval = stm32l4_getreg(STM32L4_OTGFS_PCGCCTL); + regval = stm32_getreg(STM32_OTGFS_PCGCCTL); regval &= ~(OTGFS_PCGCCTL_STPPCLK | OTGFS_PCGCCTL_GATEHCLK); - stm32l4_putreg(regval, STM32L4_OTGFS_PCGCCTL); + stm32_putreg(regval, STM32_OTGFS_PCGCCTL); #endif /* Clear remote wake-up signaling */ - regval = stm32l4_getreg(STM32L4_OTGFS_DCTL); + regval = stm32_getreg(STM32_OTGFS_DCTL); regval &= ~OTGFS_DCTL_RWUSIG; - stm32l4_putreg(regval, STM32L4_OTGFS_DCTL); + stm32_putreg(regval, STM32_OTGFS_DCTL); /* Restore full power -- whatever that means for this particular board */ - stm32l4_usbsuspend((struct usbdev_s *)priv, true); + stm32_usbsuspend((struct usbdev_s *)priv, true); /* Notify the class driver of the resume event */ @@ -3234,7 +3234,7 @@ static inline void stm32l4_resumeinterrupt(struct stm32l4_usbdev_s *priv) } /**************************************************************************** - * Name: stm32l4_suspendinterrupt + * Name: stm32_suspendinterrupt * * Description: * USB suspend interrupt @@ -3242,7 +3242,7 @@ static inline void stm32l4_resumeinterrupt(struct stm32l4_usbdev_s *priv) ****************************************************************************/ static inline -void stm32l4_suspendinterrupt(struct stm32l4_usbdev_s *priv) +void stm32_suspendinterrupt(struct stm32_usbdev_s *priv) { #ifdef CONFIG_USBDEV_LOWPOWER uint32_t regval; @@ -3261,7 +3261,7 @@ void stm32l4_suspendinterrupt(struct stm32l4_usbdev_s *priv) * connected to the host, and that we have been configured. */ - regval = stm32l4_getreg(STM32L4_OTGFS_DSTS); + regval = stm32_getreg(STM32_OTGFS_DSTS); if ((regval & OTGFS_DSTS_SUSPSTS) != 0 && devstate == DEVSTATE_CONFIGURED) { @@ -3269,16 +3269,16 @@ void stm32l4_suspendinterrupt(struct stm32l4_usbdev_s *priv) * PHY clock. */ - regval = stm32l4_getreg(STM32L4_OTGFS_PCGCCTL); + regval = stm32_getreg(STM32_OTGFS_PCGCCTL); regval |= OTGFS_PCGCCTL_STPPCLK; - stm32l4_putreg(regval, STM32L4_OTGFS_PCGCCTL); + stm32_putreg(regval, STM32_OTGFS_PCGCCTL); /* Setting OTGFS_PCGCCTL_GATEHCLK gate HCLK to modules other than * the AHB Slave and Master and wakeup logic. */ regval |= OTGFS_PCGCCTL_GATEHCLK; - stm32l4_putreg(regval, STM32L4_OTGFS_PCGCCTL); + stm32_putreg(regval, STM32_OTGFS_PCGCCTL); } #endif @@ -3286,11 +3286,11 @@ void stm32l4_suspendinterrupt(struct stm32l4_usbdev_s *priv) * state */ - stm32l4_usbsuspend((struct usbdev_s *)priv, false); + stm32_usbsuspend((struct usbdev_s *)priv, false); } /**************************************************************************** - * Name: stm32l4_rxinterrupt + * Name: stm32_rxinterrupt * * Description: * RxFIFO non-empty interrupt. This interrupt indicates that there is at @@ -3298,30 +3298,30 @@ void stm32l4_suspendinterrupt(struct stm32l4_usbdev_s *priv) * ****************************************************************************/ -static inline void stm32l4_rxinterrupt(struct stm32l4_usbdev_s *priv) +static inline void stm32_rxinterrupt(struct stm32_usbdev_s *priv) { - struct stm32l4_ep_s *privep; + struct stm32_ep_s *privep; uint32_t regval; int bcnt; int epphy; - while (0 != (stm32l4_getreg(STM32L4_OTGFS_GINTSTS) & OTGFS_GINT_RXFLVL)) + while (0 != (stm32_getreg(STM32_OTGFS_GINTSTS) & OTGFS_GINT_RXFLVL)) { /* Get the status from the top of the FIFO */ - regval = stm32l4_getreg(STM32L4_OTGFS_GRXSTSP); + regval = stm32_getreg(STM32_OTGFS_GRXSTSP); /* Decode status fields */ epphy = (regval & OTGFS_GRXSTSD_EPNUM_MASK) >> OTGFS_GRXSTSD_EPNUM_SHIFT; - /* Workaround for bad values read from the STM32L4_OTGFS_GRXSTSP + /* Workaround for bad values read from the STM32_OTGFS_GRXSTSP * register happens regval is 0xb4e48168 or 0xa80c9367 or 267E781c * All of which provide out of range indexes for epout[epphy] */ - if (epphy < STM32L4_NENDPOINTS) + if (epphy < STM32_NENDPOINTS) { privep = &priv->epout[epphy]; @@ -3338,7 +3338,7 @@ static inline void stm32l4_rxinterrupt(struct stm32l4_usbdev_s *priv) case OTGFS_GRXSTSD_PKTSTS_OUTNAK: { - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_OUTNAK), 0); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_OUTNAK), 0); } break; @@ -3351,13 +3351,13 @@ static inline void stm32l4_rxinterrupt(struct stm32l4_usbdev_s *priv) case OTGFS_GRXSTSD_PKTSTS_OUTRECVD: { - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_OUTRECVD), + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_OUTRECVD), epphy); bcnt = (regval & OTGFS_GRXSTSD_BCNT_MASK) >> OTGFS_GRXSTSD_BCNT_SHIFT; if (bcnt > 0) { - stm32l4_epout_receive(privep, bcnt); + stm32_epout_receive(privep, bcnt); } } break; @@ -3375,7 +3375,7 @@ static inline void stm32l4_rxinterrupt(struct stm32l4_usbdev_s *priv) case OTGFS_GRXSTSD_PKTSTS_OUTDONE: { - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_OUTDONE), epphy); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_OUTDONE), epphy); } break; @@ -3392,7 +3392,7 @@ static inline void stm32l4_rxinterrupt(struct stm32l4_usbdev_s *priv) case OTGFS_GRXSTSD_PKTSTS_SETUPDONE: { - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_SETUPDONE), + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SETUPDONE), epphy); /* On the L4 This event does not occur on the next SETUP @@ -3412,7 +3412,7 @@ static inline void stm32l4_rxinterrupt(struct stm32l4_usbdev_s *priv) { uint16_t datlen; - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_SETUPRECVD), + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SETUPRECVD), epphy); /* Read EP0 setup data. NOTE: If multiple SETUP packets are @@ -3420,7 +3420,7 @@ static inline void stm32l4_rxinterrupt(struct stm32l4_usbdev_s *priv) * packets and only that last SETUP packet will be processed. */ - stm32l4_rxfifo_read(&priv->epout[EP0], + stm32_rxfifo_read(&priv->epout[EP0], (uint8_t *)&priv->ctrlreq, USB_SIZEOF_CTRLREQ); @@ -3439,7 +3439,7 @@ static inline void stm32l4_rxinterrupt(struct stm32l4_usbdev_s *priv) { /* Reset the endpoint and Stop NAK-ing */ - stm32l4_ep0out_ctrlsetup(priv); + stm32_ep0out_ctrlsetup(priv); /* Wait for the data phase. */ @@ -3452,14 +3452,14 @@ static inline void stm32l4_rxinterrupt(struct stm32l4_usbdev_s *priv) */ priv->ep0state = EP0STATE_SETUP_READY; - stm32l4_ep0out_setup(priv); + stm32_ep0out_setup(priv); } } break; default: { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_INVALIDPARMS), + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), (regval & OTGFS_GRXSTSD_PKTSTS_MASK) >> OTGFS_GRXSTSD_PKTSTS_SHIFT); } @@ -3470,33 +3470,33 @@ static inline void stm32l4_rxinterrupt(struct stm32l4_usbdev_s *priv) } /**************************************************************************** - * Name: stm32l4_enuminterrupt + * Name: stm32_enuminterrupt * * Description: * Enumeration done interrupt * ****************************************************************************/ -static inline void stm32l4_enuminterrupt(struct stm32l4_usbdev_s *priv) +static inline void stm32_enuminterrupt(struct stm32_usbdev_s *priv) { uint32_t regval; /* Activate EP0 */ - stm32l4_ep0in_activate(); + stm32_ep0in_activate(); /* Set USB turn-around time for the full speed device with internal * PHY interface. */ - regval = stm32l4_getreg(STM32L4_OTGFS_GUSBCFG); + regval = stm32_getreg(STM32_OTGFS_GUSBCFG); regval &= ~OTGFS_GUSBCFG_TRDT_MASK; regval |= OTGFS_GUSBCFG_TRDT(6); - stm32l4_putreg(regval, STM32L4_OTGFS_GUSBCFG); + stm32_putreg(regval, STM32_OTGFS_GUSBCFG); } /**************************************************************************** - * Name: stm32l4_isocininterrupt + * Name: stm32_isocininterrupt * * Description: * Incomplete isochronous IN transfer interrupt. Assertion of the @@ -3506,7 +3506,7 @@ static inline void stm32l4_enuminterrupt(struct stm32l4_usbdev_s *priv) ****************************************************************************/ #ifdef CONFIG_USBDEV_ISOCHRONOUS -static inline void stm32l4_isocininterrupt(struct stm32l4_usbdev_s *priv) +static inline void stm32_isocininterrupt(struct stm32_usbdev_s *priv) { int i; @@ -3515,7 +3515,7 @@ static inline void stm32l4_isocininterrupt(struct stm32l4_usbdev_s *priv) * transfers. */ - for (i = 0; i < STM32L4_NENDPOINTS; i++) + for (i = 0; i < STM32_NENDPOINTS; i++) { /* Is this an isochronous IN endpoint? */ @@ -3538,9 +3538,9 @@ static inline void stm32l4_isocininterrupt(struct stm32l4_usbdev_s *priv) /* Check if this is the endpoint that had the incomplete transfer */ - regaddr = STM32L4_OTGFS_DIEPCTL(privep->epphy); - doepctl = stm32l4_getreg(regaddr); - dsts = stm32l4_getreg(STM32L4_OTGFS_DSTS); + regaddr = STM32_OTGFS_DIEPCTL(privep->epphy); + doepctl = stm32_getreg(regaddr); + dsts = stm32_getreg(STM32_OTGFS_DSTS); /* EONUM = 0:even frame, 1:odd frame * SOFFN = Frame number of the received SOF @@ -3561,16 +3561,16 @@ static inline void stm32l4_isocininterrupt(struct stm32l4_usbdev_s *priv) * disable the endpoint. */ - stm32l4_req_complete(privep, -EIO); + stm32_req_complete(privep, -EIO); #warning "Will clear OTGFS_DIEPCTL_USBAEP too" - stm32l4_epin_disable(privep); + stm32_epin_disable(privep); break; } } #endif /**************************************************************************** - * Name: stm32l4_isocoutinterrupt + * Name: stm32_isocoutinterrupt * * Description: * Incomplete periodic transfer interrupt @@ -3579,10 +3579,10 @@ static inline void stm32l4_isocininterrupt(struct stm32l4_usbdev_s *priv) #ifdef CONFIG_USBDEV_ISOCHRONOUS static inline -void stm32l4_isocoutinterrupt(struct stm32l4_usbdev_s *priv) +void stm32_isocoutinterrupt(struct stm32_usbdev_s *priv) { - struct stm32l4_ep_s *privep; - struct stm32l4_req_s *privreq; + struct stm32_ep_s *privep; + struct stm32_req_s *privreq; uint32_t regaddr; uint32_t doepctl; uint32_t dsts; @@ -3599,7 +3599,7 @@ void stm32l4_isocoutinterrupt(struct stm32l4_usbdev_s *priv) * DOEPCTLx:EPENA = 1 */ - for (i = 0; i < STM32L4_NENDPOINTS; i++) + for (i = 0; i < STM32_NENDPOINTS; i++) { /* Is this an isochronous OUT endpoint? */ @@ -3622,9 +3622,9 @@ void stm32l4_isocoutinterrupt(struct stm32l4_usbdev_s *priv) /* Check if this is the endpoint that had the incomplete transfer */ - regaddr = STM32L4_OTGFS_DOEPCTL(privep->epphy); - doepctl = stm32l4_getreg(regaddr); - dsts = stm32l4_getreg(STM32L4_OTGFS_DSTS); + regaddr = STM32_OTGFS_DOEPCTL(privep->epphy); + doepctl = stm32_getreg(regaddr); + dsts = stm32_getreg(STM32_OTGFS_DSTS); /* EONUM = 0:even frame, 1:odd frame * SOFFN = Frame number of the received SOF @@ -3645,16 +3645,16 @@ void stm32l4_isocoutinterrupt(struct stm32l4_usbdev_s *priv) * disable the endpoint. */ - stm32l4_req_complete(privep, -EIO); + stm32_req_complete(privep, -EIO); #warning "Will clear OTGFS_DOEPCTL_USBAEP too" - stm32l4_epout_disable(privep); + stm32_epout_disable(privep); break; } } #endif /**************************************************************************** - * Name: stm32l4_sessioninterrupt + * Name: stm32_sessioninterrupt * * Description: * Session request/new session detected interrupt @@ -3663,14 +3663,14 @@ void stm32l4_isocoutinterrupt(struct stm32l4_usbdev_s *priv) #ifdef CONFIG_USBDEV_VBUSSENSING static inline -void stm32l4_sessioninterrupt(struct stm32l4_usbdev_s *priv) +void stm32_sessioninterrupt(struct stm32_usbdev_s *priv) { #warning "Missing logic" } #endif /**************************************************************************** - * Name: stm32l4_otginterrupt + * Name: stm32_otginterrupt * * Description: * OTG interrupt @@ -3678,13 +3678,13 @@ void stm32l4_sessioninterrupt(struct stm32l4_usbdev_s *priv) ****************************************************************************/ #ifdef CONFIG_USBDEV_VBUSSENSING -static inline void stm32l4_otginterrupt(struct stm32l4_usbdev_s *priv) +static inline void stm32_otginterrupt(struct stm32_usbdev_s *priv) { uint32_t regval; /* Check for session end detected */ - regval = stm32l4_getreg(STM32L4_OTGFS_GOTGINT); + regval = stm32_getreg(STM32_OTGFS_GOTGINT); if ((regval & OTGFS_GOTGINT_SEDET) != 0) { #warning "Missing logic" @@ -3692,19 +3692,19 @@ static inline void stm32l4_otginterrupt(struct stm32l4_usbdev_s *priv) /* Clear OTG interrupt */ - stm32l4_putreg(regval, STM32L4_OTGFS_GOTGINT); + stm32_putreg(regval, STM32_OTGFS_GOTGINT); } #endif /**************************************************************************** - * Name: stm32l4_usbinterrupt + * Name: stm32_usbinterrupt * * Description: * USB interrupt handler * ****************************************************************************/ -static int stm32l4_usbinterrupt(int irq, void *context, void *arg) +static int stm32_usbinterrupt(int irq, void *context, void *arg) { /* At present, there is only a single OTG FS device support. Hence it is * pre-allocated as g_otgfsdev. However, in most code, the private data @@ -3713,15 +3713,15 @@ static int stm32l4_usbinterrupt(int irq, void *context, void *arg) * devices. */ - struct stm32l4_usbdev_s *priv = &g_otgfsdev; + struct stm32_usbdev_s *priv = &g_otgfsdev; uint32_t regval; uint32_t reserved; - usbtrace(TRACE_INTENTRY(STM32L4_TRACEINTID_USB), priv->ep0state); + usbtrace(TRACE_INTENTRY(STM32_TRACEINTID_USB), priv->ep0state); /* Assure that we are in device mode */ - DEBUGASSERT((stm32l4_getreg(STM32L4_OTGFS_GINTSTS) & OTGFS_GINTSTS_CMOD) == + DEBUGASSERT((stm32_getreg(STM32_OTGFS_GINTSTS) & OTGFS_GINTSTS_CMOD) == OTGFS_GINTSTS_DEVMODE); /* Get the state of all enabled interrupts. We will do this repeatedly @@ -3733,16 +3733,16 @@ static int stm32l4_usbinterrupt(int irq, void *context, void *arg) { /* Get the set of pending, un-masked interrupts */ - regval = stm32l4_getreg(STM32L4_OTGFS_GINTSTS); + regval = stm32_getreg(STM32_OTGFS_GINTSTS); reserved = (regval & OTGFS_GINT_RESERVED); - regval &= stm32l4_getreg(STM32L4_OTGFS_GINTMSK); + regval &= stm32_getreg(STM32_OTGFS_GINTMSK); /* With out modifying the reserved bits, acknowledge all * **Writable** pending irqs we will service below */ - stm32l4_putreg(((regval | reserved) & OTGFS_GINT_RC_W1), - STM32L4_OTGFS_GINTSTS); + stm32_putreg(((regval | reserved) & OTGFS_GINT_RC_W1), + STM32_OTGFS_GINTSTS); /* Break out of the loop when there are no further pending (and * unmasked) interrupts to be processes. @@ -3753,7 +3753,7 @@ static int stm32l4_usbinterrupt(int irq, void *context, void *arg) break; } - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_INTPENDING), + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_INTPENDING), (uint16_t)regval); /* OUT endpoint interrupt. The core sets this bit to indicate that an @@ -3762,9 +3762,9 @@ static int stm32l4_usbinterrupt(int irq, void *context, void *arg) if ((regval & OTGFS_GINT_OEP) != 0) { - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_EPOUT), + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPOUT), (uint16_t)regval); - stm32l4_epout_interrupt(priv); + stm32_epout_interrupt(priv); } /* IN endpoint interrupt. The core sets this bit to indicate that @@ -3773,9 +3773,9 @@ static int stm32l4_usbinterrupt(int irq, void *context, void *arg) if ((regval & OTGFS_GINT_IEP) != 0) { - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_EPIN), + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPIN), (uint16_t)regval); - stm32l4_epin_interrupt(priv); + stm32_epin_interrupt(priv); } /* Host/device mode mismatch error interrupt */ @@ -3783,7 +3783,7 @@ static int stm32l4_usbinterrupt(int irq, void *context, void *arg) #ifdef CONFIG_DEBUG_FEATURES if ((regval & OTGFS_GINT_MMIS) != 0) { - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_MISMATCH), + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_MISMATCH), (uint16_t)regval); } #endif @@ -3792,18 +3792,18 @@ static int stm32l4_usbinterrupt(int irq, void *context, void *arg) if ((regval & OTGFS_GINT_WKUP) != 0) { - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_WAKEUP), + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_WAKEUP), (uint16_t)regval); - stm32l4_resumeinterrupt(priv); + stm32_resumeinterrupt(priv); } /* USB suspend interrupt */ if ((regval & OTGFS_GINT_USBSUSP) != 0) { - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_SUSPEND), + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SUSPEND), (uint16_t)regval); - stm32l4_suspendinterrupt(priv); + stm32_suspendinterrupt(priv); } /* Start of frame interrupt */ @@ -3811,9 +3811,9 @@ static int stm32l4_usbinterrupt(int irq, void *context, void *arg) #ifdef CONFIG_USBDEV_SOFINTERRUPT if ((regval & OTGFS_GINT_SOF) != 0) { - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_SOF), + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SOF), (uint16_t)regval); - usbdev_sof_irq(&priv->usbdev, stm32l4_getframe(&priv->usbdev)); + usbdev_sof_irq(&priv->usbdev, stm32_getframe(&priv->usbdev)); } #endif @@ -3823,22 +3823,22 @@ static int stm32l4_usbinterrupt(int irq, void *context, void *arg) if ((regval & OTGFS_GINT_RXFLVL) != 0) { - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_RXFIFO), + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_RXFIFO), (uint16_t)regval); - stm32l4_rxinterrupt(priv); + stm32_rxinterrupt(priv); } /* USB reset interrupt */ if ((regval & (OTGFS_GINT_USBRST | OTGFS_GINT_RSTDET)) != 0) { - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_DEVRESET), + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_DEVRESET), (uint16_t)regval); /* Perform the device reset */ - stm32l4_usbreset(priv); - usbtrace(TRACE_INTEXIT(STM32L4_TRACEINTID_USB), priv->ep0state); + stm32_usbreset(priv); + usbtrace(TRACE_INTEXIT(STM32_TRACEINTID_USB), priv->ep0state); return OK; } @@ -3846,9 +3846,9 @@ static int stm32l4_usbinterrupt(int irq, void *context, void *arg) if ((regval & OTGFS_GINT_ENUMDNE) != 0) { - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_ENUMDNE), + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_ENUMDNE), (uint16_t)regval); - stm32l4_enuminterrupt(priv); + stm32_enuminterrupt(priv); } /* Incomplete isochronous IN transfer interrupt. When the core finds @@ -3860,9 +3860,9 @@ static int stm32l4_usbinterrupt(int irq, void *context, void *arg) #ifdef CONFIG_USBDEV_ISOCHRONOUS if ((regval & OTGFS_GINT_IISOIXFR) != 0) { - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_IISOIXFR), + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_IISOIXFR), (uint16_t)regval); - stm32l4_isocininterrupt(priv); + stm32_isocininterrupt(priv); } /* Incomplete isochronous OUT transfer. For isochronous OUT @@ -3877,9 +3877,9 @@ static int stm32l4_usbinterrupt(int irq, void *context, void *arg) if ((regval & OTGFS_GINT_IISOOXFR) != 0) { - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_IISOOXFR), + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_IISOOXFR), (uint16_t)regval); - stm32l4_isocoutinterrupt(priv); + stm32_isocoutinterrupt(priv); } #endif @@ -3888,23 +3888,23 @@ static int stm32l4_usbinterrupt(int irq, void *context, void *arg) #ifdef CONFIG_USBDEV_VBUSSENSING if ((regval & OTGFS_GINT_SRQ) != 0) { - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_SRQ), + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SRQ), (uint16_t)regval); - stm32l4_sessioninterrupt(priv); + stm32_sessioninterrupt(priv); } /* OTG interrupt */ if ((regval & OTGFS_GINT_OTG) != 0) { - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_OTG), + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_OTG), (uint16_t)regval); - stm32l4_otginterrupt(priv); + stm32_otginterrupt(priv); } #endif } - usbtrace(TRACE_INTEXIT(STM32L4_TRACEINTID_USB), priv->ep0state); + usbtrace(TRACE_INTEXIT(STM32_TRACEINTID_USB), priv->ep0state); return OK; } @@ -3913,28 +3913,28 @@ static int stm32l4_usbinterrupt(int irq, void *context, void *arg) ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_enablegonak + * Name: stm32_enablegonak * * Description: * Enable global OUT NAK mode * ****************************************************************************/ -static void stm32l4_enablegonak(struct stm32l4_ep_s *privep) +static void stm32_enablegonak(struct stm32_ep_s *privep) { uint32_t regval; /* First, make sure that there is no GNOAKEFF interrupt pending. */ #if 0 - stm32l4_putreg(OTGFS_GINT_GONAKEFF, STM32L4_OTGFS_GINTSTS); + stm32_putreg(OTGFS_GINT_GONAKEFF, STM32_OTGFS_GINTSTS); #endif /* Enable Global OUT NAK mode in the core. */ - regval = stm32l4_getreg(STM32L4_OTGFS_DCTL); + regval = stm32_getreg(STM32_OTGFS_DCTL); regval |= OTGFS_DCTL_SGONAK; - stm32l4_putreg(regval, STM32L4_OTGFS_DCTL); + stm32_putreg(regval, STM32_OTGFS_DCTL); #if 0 /* Wait for the GONAKEFF interrupt that indicates that the OUT NAK @@ -3942,8 +3942,8 @@ static void stm32l4_enablegonak(struct stm32l4_ep_s *privep) * from the RxFIFO, the core sets the GONAKEFF interrupt. */ - while ((stm32l4_getreg(STM32L4_OTGFS_GINTSTS) & OTGFS_GINT_GONAKEFF) == 0); - stm32l4_putreg(OTGFS_GINT_GONAKEFF, STM32L4_OTGFS_GINTSTS); + while ((stm32_getreg(STM32_OTGFS_GINTSTS) & OTGFS_GINT_GONAKEFF) == 0); + stm32_putreg(OTGFS_GINT_GONAKEFF, STM32_OTGFS_GINTSTS); #else /* Since we are in the interrupt handler, we cannot wait inline for the @@ -3954,31 +3954,31 @@ static void stm32l4_enablegonak(struct stm32l4_ep_s *privep) * reported in OTGFS DCTL register? */ - while ((stm32l4_getreg(STM32L4_OTGFS_DCTL) & OTGFS_DCTL_GONSTS) == 0); + while ((stm32_getreg(STM32_OTGFS_DCTL) & OTGFS_DCTL_GONSTS) == 0); #endif } /**************************************************************************** - * Name: stm32l4_disablegonak + * Name: stm32_disablegonak * * Description: * Disable global OUT NAK mode * ****************************************************************************/ -static void stm32l4_disablegonak(struct stm32l4_ep_s *privep) +static void stm32_disablegonak(struct stm32_ep_s *privep) { uint32_t regval; /* Set the "Clear the Global OUT NAK bit" to disable global OUT NAK mode */ - regval = stm32l4_getreg(STM32L4_OTGFS_DCTL); + regval = stm32_getreg(STM32_OTGFS_DCTL); regval |= OTGFS_DCTL_CGONAK; - stm32l4_putreg(regval, STM32L4_OTGFS_DCTL); + stm32_putreg(regval, STM32_OTGFS_DCTL); } /**************************************************************************** - * Name: stm32l4_epout_configure + * Name: stm32_epout_configure * * Description: * Configure an OUT endpoint, making it usable @@ -3990,7 +3990,7 @@ static void stm32l4_disablegonak(struct stm32l4_ep_s *privep) * ****************************************************************************/ -static int stm32l4_epout_configure(struct stm32l4_ep_s *privep, +static int stm32_epout_configure(struct stm32_ep_s *privep, uint8_t eptype, uint16_t maxpacket) { uint32_t mpsiz; @@ -4042,8 +4042,8 @@ static int stm32l4_epout_configure(struct stm32l4_ep_s *privep, * register. */ - regaddr = STM32L4_OTGFS_DOEPCTL(privep->epphy); - regval = stm32l4_getreg(regaddr); + regaddr = STM32_OTGFS_DOEPCTL(privep->epphy); + regval = stm32_getreg(regaddr); if ((regval & OTGFS_DOEPCTL_USBAEP) == 0) { if (regval & OTGFS_DOEPCTL_NAKSTS) @@ -4055,7 +4055,7 @@ static int stm32l4_epout_configure(struct stm32l4_ep_s *privep, regval |= mpsiz; regval |= (eptype << OTGFS_DOEPCTL_EPTYP_SHIFT); regval |= (OTGFS_DOEPCTL_SD0PID | OTGFS_DOEPCTL_USBAEP); - stm32l4_putreg(regval, regaddr); + stm32_putreg(regval, regaddr); /* Save the endpoint configuration */ @@ -4066,14 +4066,14 @@ static int stm32l4_epout_configure(struct stm32l4_ep_s *privep, /* Enable the interrupt for this endpoint */ - regval = stm32l4_getreg(STM32L4_OTGFS_DAINTMSK); + regval = stm32_getreg(STM32_OTGFS_DAINTMSK); regval |= OTGFS_DAINT_OEP(privep->epphy); - stm32l4_putreg(regval, STM32L4_OTGFS_DAINTMSK); + stm32_putreg(regval, STM32_OTGFS_DAINTMSK); return OK; } /**************************************************************************** - * Name: stm32l4_epin_configure + * Name: stm32_epin_configure * * Description: * Configure an IN endpoint, making it usable @@ -4085,7 +4085,7 @@ static int stm32l4_epout_configure(struct stm32l4_ep_s *privep, * ****************************************************************************/ -static int stm32l4_epin_configure(struct stm32l4_ep_s *privep, +static int stm32_epin_configure(struct stm32_ep_s *privep, uint8_t eptype, uint16_t maxpacket) { @@ -4138,8 +4138,8 @@ static int stm32l4_epin_configure(struct stm32l4_ep_s *privep, * register. */ - regaddr = STM32L4_OTGFS_DIEPCTL(privep->epphy); - regval = stm32l4_getreg(regaddr); + regaddr = STM32_OTGFS_DIEPCTL(privep->epphy); + regval = stm32_getreg(regaddr); if ((regval & OTGFS_DIEPCTL_USBAEP) == 0) { if (regval & OTGFS_DIEPCTL_NAKSTS) @@ -4153,7 +4153,7 @@ static int stm32l4_epin_configure(struct stm32l4_ep_s *privep, regval |= (eptype << OTGFS_DIEPCTL_EPTYP_SHIFT); regval |= (privep->epphy << OTGFS_DIEPCTL_TXFNUM_SHIFT); regval |= (OTGFS_DIEPCTL_SD0PID | OTGFS_DIEPCTL_USBAEP); - stm32l4_putreg(regval, regaddr); + stm32_putreg(regval, regaddr); /* Save the endpoint configuration */ @@ -4164,15 +4164,15 @@ static int stm32l4_epin_configure(struct stm32l4_ep_s *privep, /* Enable the interrupt for this endpoint */ - regval = stm32l4_getreg(STM32L4_OTGFS_DAINTMSK); + regval = stm32_getreg(STM32_OTGFS_DAINTMSK); regval |= OTGFS_DAINT_IEP(privep->epphy); - stm32l4_putreg(regval, STM32L4_OTGFS_DAINTMSK); + stm32_putreg(regval, STM32_OTGFS_DAINTMSK); return OK; } /**************************************************************************** - * Name: stm32l4_ep_configure + * Name: stm32_ep_configure * * Description: * Configure endpoint, making it usable @@ -4186,11 +4186,11 @@ static int stm32l4_epin_configure(struct stm32l4_ep_s *privep, * ****************************************************************************/ -static int stm32l4_ep_configure(struct usbdev_ep_s *ep, +static int stm32_ep_configure(struct usbdev_ep_s *ep, const struct usb_epdesc_s *desc, bool last) { - struct stm32l4_ep_s *privep = (struct stm32l4_ep_s *)ep; + struct stm32_ep_s *privep = (struct stm32_ep_s *)ep; uint16_t maxpacket; uint8_t eptype; int ret; @@ -4207,43 +4207,43 @@ static int stm32l4_ep_configure(struct usbdev_ep_s *ep, if (privep->isin) { - ret = stm32l4_epin_configure(privep, eptype, maxpacket); + ret = stm32_epin_configure(privep, eptype, maxpacket); } else { - ret = stm32l4_epout_configure(privep, eptype, maxpacket); + ret = stm32_epout_configure(privep, eptype, maxpacket); } return ret; } /**************************************************************************** - * Name: stm32l4_ep0_configure + * Name: stm32_ep0_configure * * Description: * Reset Usb engine * ****************************************************************************/ -static void stm32l4_ep0_configure(struct stm32l4_usbdev_s *priv) +static void stm32_ep0_configure(struct stm32_usbdev_s *priv) { /* Enable EP0 IN and OUT */ - stm32l4_epin_configure(&priv->epin[EP0], USB_EP_ATTR_XFER_CONTROL, + stm32_epin_configure(&priv->epin[EP0], USB_EP_ATTR_XFER_CONTROL, CONFIG_USBDEV_EP0_MAXSIZE); - stm32l4_epout_configure(&priv->epout[EP0], USB_EP_ATTR_XFER_CONTROL, + stm32_epout_configure(&priv->epout[EP0], USB_EP_ATTR_XFER_CONTROL, CONFIG_USBDEV_EP0_MAXSIZE); } /**************************************************************************** - * Name: stm32l4_epout_disable + * Name: stm32_epout_disable * * Description: * Disable an OUT endpoint will no longer be used * ****************************************************************************/ -static void stm32l4_epout_disable(struct stm32l4_ep_s *privep) +static void stm32_epout_disable(struct stm32_ep_s *privep) { uint32_t regaddr; uint32_t regval; @@ -4258,25 +4258,25 @@ static void stm32l4_epout_disable(struct stm32l4_ep_s *privep) */ flags = enter_critical_section(); - stm32l4_enablegonak(privep); + stm32_enablegonak(privep); /* Disable the required OUT endpoint by setting the EPDIS and SNAK bits * int DOECPTL register. */ - regaddr = STM32L4_OTGFS_DOEPCTL(privep->epphy); - regval = stm32l4_getreg(regaddr); + regaddr = STM32_OTGFS_DOEPCTL(privep->epphy); + regval = stm32_getreg(regaddr); regval &= ~OTGFS_DOEPCTL_USBAEP; regval |= (OTGFS_DOEPCTL_EPDIS | OTGFS_DOEPCTL_SNAK); - stm32l4_putreg(regval, regaddr); + stm32_putreg(regval, regaddr); /* Wait for the EPDISD interrupt which indicates that the OUT * endpoint is completely disabled. */ #if 0 /* Doesn't happen */ - regaddr = STM32L4_OTGFS_DOEPINT(privep->epphy); - while ((stm32l4_getreg(regaddr) & OTGFS_DOEPINT_EPDISD) == 0); + regaddr = STM32_OTGFS_DOEPINT(privep->epphy); + while ((stm32_getreg(regaddr) & OTGFS_DOEPINT_EPDISD) == 0); #else /* REVISIT: */ @@ -4285,36 +4285,36 @@ static void stm32l4_epout_disable(struct stm32l4_ep_s *privep) /* Clear the EPDISD interrupt indication */ - stm32l4_putreg(OTGFS_DOEPINT_EPDISD, STM32L4_OTGFS_DOEPINT(privep->epphy)); + stm32_putreg(OTGFS_DOEPINT_EPDISD, STM32_OTGFS_DOEPINT(privep->epphy)); /* Then disable the Global OUT NAK mode to continue receiving data * from other non-disabled OUT endpoints. */ - stm32l4_disablegonak(privep); + stm32_disablegonak(privep); /* Disable endpoint interrupts */ - regval = stm32l4_getreg(STM32L4_OTGFS_DAINTMSK); + regval = stm32_getreg(STM32_OTGFS_DAINTMSK); regval &= ~OTGFS_DAINT_OEP(privep->epphy); - stm32l4_putreg(regval, STM32L4_OTGFS_DAINTMSK); + stm32_putreg(regval, STM32_OTGFS_DAINTMSK); /* Cancel any queued read requests */ - stm32l4_req_cancel(privep, -ESHUTDOWN); + stm32_req_cancel(privep, -ESHUTDOWN); leave_critical_section(flags); } /**************************************************************************** - * Name: stm32l4_epin_disable + * Name: stm32_epin_disable * * Description: * Disable an IN endpoint when it will no longer be used * ****************************************************************************/ -static void stm32l4_epin_disable(struct stm32l4_ep_s *privep) +static void stm32_epin_disable(struct stm32_ep_s *privep) { uint32_t regaddr; uint32_t regval; @@ -4326,8 +4326,8 @@ static void stm32l4_epin_disable(struct stm32l4_ep_s *privep) * hardware. Trying to disable again will just hang in the wait. */ - regaddr = STM32L4_OTGFS_DIEPCTL(privep->epphy); - regval = stm32l4_getreg(regaddr); + regaddr = STM32_OTGFS_DIEPCTL(privep->epphy); + regval = stm32_getreg(regaddr); if ((regval & OTGFS_DIEPCTL_USBAEP) == 0) { return; @@ -4342,26 +4342,26 @@ static void stm32l4_epin_disable(struct stm32l4_ep_s *privep) * to poll this bit below). */ - stm32l4_putreg(OTGFS_DIEPINT_INEPNE, STM32L4_OTGFS_DIEPINT(privep->epphy)); + stm32_putreg(OTGFS_DIEPINT_INEPNE, STM32_OTGFS_DIEPINT(privep->epphy)); /* Set the endpoint in NAK mode */ - regaddr = STM32L4_OTGFS_DIEPCTL(privep->epphy); - regval = stm32l4_getreg(regaddr); + regaddr = STM32_OTGFS_DIEPCTL(privep->epphy); + regval = stm32_getreg(regaddr); regval &= ~OTGFS_DIEPCTL_USBAEP; regval |= (OTGFS_DIEPCTL_EPDIS | OTGFS_DIEPCTL_SNAK); - stm32l4_putreg(regval, regaddr); + stm32_putreg(regval, regaddr); /* Wait for the INEPNE interrupt that indicates that we are now in * NAK mode */ - regaddr = STM32L4_OTGFS_DIEPINT(privep->epphy); - while ((stm32l4_getreg(regaddr) & OTGFS_DIEPINT_INEPNE) == 0); + regaddr = STM32_OTGFS_DIEPINT(privep->epphy); + while ((stm32_getreg(regaddr) & OTGFS_DIEPINT_INEPNE) == 0); /* Clear the INEPNE interrupt indication */ - stm32l4_putreg(OTGFS_DIEPINT_INEPNE, regaddr); + stm32_putreg(OTGFS_DIEPINT_INEPNE, regaddr); #endif /* Deactivate and disable the endpoint by setting the EPDIS and SNAK bits @@ -4369,55 +4369,55 @@ static void stm32l4_epin_disable(struct stm32l4_ep_s *privep) */ flags = enter_critical_section(); - regaddr = STM32L4_OTGFS_DIEPCTL(privep->epphy); - regval = stm32l4_getreg(regaddr); + regaddr = STM32_OTGFS_DIEPCTL(privep->epphy); + regval = stm32_getreg(regaddr); regval &= ~OTGFS_DIEPCTL_USBAEP; regval |= (OTGFS_DIEPCTL_EPDIS | OTGFS_DIEPCTL_SNAK); - stm32l4_putreg(regval, regaddr); + stm32_putreg(regval, regaddr); /* Wait for the EPDISD interrupt which indicates that the IN * endpoint is completely disabled. */ - regaddr = STM32L4_OTGFS_DIEPINT(privep->epphy); - while ((stm32l4_getreg(regaddr) & OTGFS_DIEPINT_EPDISD) == 0); + regaddr = STM32_OTGFS_DIEPINT(privep->epphy); + while ((stm32_getreg(regaddr) & OTGFS_DIEPINT_EPDISD) == 0); /* Clear the EPDISD interrupt indication */ - stm32l4_putreg(OTGFS_DIEPINT_EPDISD, stm32l4_getreg(regaddr)); + stm32_putreg(OTGFS_DIEPINT_EPDISD, stm32_getreg(regaddr)); /* Flush any data remaining in the TxFIFO */ - stm32l4_txfifo_flush(OTGFS_GRSTCTL_TXFNUM_D(privep->epphy)); + stm32_txfifo_flush(OTGFS_GRSTCTL_TXFNUM_D(privep->epphy)); /* Disable endpoint interrupts */ - regval = stm32l4_getreg(STM32L4_OTGFS_DAINTMSK); + regval = stm32_getreg(STM32_OTGFS_DAINTMSK); regval &= ~OTGFS_DAINT_IEP(privep->epphy); - stm32l4_putreg(regval, STM32L4_OTGFS_DAINTMSK); + stm32_putreg(regval, STM32_OTGFS_DAINTMSK); /* Cancel any queued write requests */ - stm32l4_req_cancel(privep, -ESHUTDOWN); + stm32_req_cancel(privep, -ESHUTDOWN); leave_critical_section(flags); } /**************************************************************************** - * Name: stm32l4_ep_disable + * Name: stm32_ep_disable * * Description: * The endpoint will no longer be used * ****************************************************************************/ -static int stm32l4_ep_disable(struct usbdev_ep_s *ep) +static int stm32_ep_disable(struct usbdev_ep_s *ep) { - struct stm32l4_ep_s *privep = (struct stm32l4_ep_s *)ep; + struct stm32_ep_s *privep = (struct stm32_ep_s *)ep; #ifdef CONFIG_DEBUG_FEATURES if (!ep) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_INVALIDPARMS), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); return -EINVAL; } #endif @@ -4430,79 +4430,79 @@ static int stm32l4_ep_disable(struct usbdev_ep_s *ep) { /* Disable the IN endpoint */ - stm32l4_epin_disable(privep); + stm32_epin_disable(privep); } else { /* Disable the OUT endpoint */ - stm32l4_epout_disable(privep); + stm32_epout_disable(privep); } return OK; } /**************************************************************************** - * Name: stm32l4_ep_allocreq + * Name: stm32_ep_allocreq * * Description: * Allocate an I/O request * ****************************************************************************/ -static struct usbdev_req_s *stm32l4_ep_allocreq(struct usbdev_ep_s *ep) +static struct usbdev_req_s *stm32_ep_allocreq(struct usbdev_ep_s *ep) { - struct stm32l4_req_s *privreq; + struct stm32_req_s *privreq; #ifdef CONFIG_DEBUG_FEATURES if (!ep) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_INVALIDPARMS), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); return NULL; } #endif - usbtrace(TRACE_EPALLOCREQ, ((struct stm32l4_ep_s *)ep)->epphy); + usbtrace(TRACE_EPALLOCREQ, ((struct stm32_ep_s *)ep)->epphy); - privreq = (struct stm32l4_req_s *) - kmm_malloc(sizeof(struct stm32l4_req_s)); + privreq = (struct stm32_req_s *) + kmm_malloc(sizeof(struct stm32_req_s)); if (!privreq) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_ALLOCFAIL), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_ALLOCFAIL), 0); return NULL; } - memset(privreq, 0, sizeof(struct stm32l4_req_s)); + memset(privreq, 0, sizeof(struct stm32_req_s)); return &privreq->req; } /**************************************************************************** - * Name: stm32l4_ep_freereq + * Name: stm32_ep_freereq * * Description: * Free an I/O request * ****************************************************************************/ -static void stm32l4_ep_freereq(struct usbdev_ep_s *ep, +static void stm32_ep_freereq(struct usbdev_ep_s *ep, struct usbdev_req_s *req) { - struct stm32l4_req_s *privreq = (struct stm32l4_req_s *)req; + struct stm32_req_s *privreq = (struct stm32_req_s *)req; #ifdef CONFIG_DEBUG_FEATURES if (!ep || !req) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_INVALIDPARMS), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); return; } #endif - usbtrace(TRACE_EPFREEREQ, ((struct stm32l4_ep_s *)ep)->epphy); + usbtrace(TRACE_EPFREEREQ, ((struct stm32_ep_s *)ep)->epphy); kmm_free(privreq); } /**************************************************************************** - * Name: stm32l4_ep_allocbuffer + * Name: stm32_ep_allocbuffer * * Description: * Allocate an I/O buffer @@ -4510,10 +4510,10 @@ static void stm32l4_ep_freereq(struct usbdev_ep_s *ep, ****************************************************************************/ #ifdef CONFIG_USBDEV_DMA -static void *stm32l4_ep_allocbuffer(struct usbdev_ep_s *ep, +static void *stm32_ep_allocbuffer(struct usbdev_ep_s *ep, uint16_t bytes) { - usbtrace(TRACE_EPALLOCBUFFER, ((struct stm32l4_ep_s *)ep)->epphy); + usbtrace(TRACE_EPALLOCBUFFER, ((struct stm32_ep_s *)ep)->epphy); #ifdef CONFIG_USBDEV_DMAMEMORY return usbdev_dma_alloc(bytes); @@ -4524,7 +4524,7 @@ static void *stm32l4_ep_allocbuffer(struct usbdev_ep_s *ep, #endif /**************************************************************************** - * Name: stm32l4_ep_freebuffer + * Name: stm32_ep_freebuffer * * Description: * Free an I/O buffer @@ -4532,9 +4532,9 @@ static void *stm32l4_ep_allocbuffer(struct usbdev_ep_s *ep, ****************************************************************************/ #ifdef CONFIG_USBDEV_DMA -static void stm32l4_ep_freebuffer(struct usbdev_ep_s *ep, void *buf) +static void stm32_ep_freebuffer(struct usbdev_ep_s *ep, void *buf) { - usbtrace(TRACE_EPFREEBUFFER, ((struct stm32l4_ep_s *)ep)->epphy); + usbtrace(TRACE_EPFREEBUFFER, ((struct stm32_ep_s *)ep)->epphy); #ifdef CONFIG_USBDEV_DMAMEMORY usbdev_dma_free(buf); @@ -4545,19 +4545,19 @@ static void stm32l4_ep_freebuffer(struct usbdev_ep_s *ep, void *buf) #endif /**************************************************************************** - * Name: stm32l4_ep_submit + * Name: stm32_ep_submit * * Description: * Submit an I/O request to the endpoint * ****************************************************************************/ -static int stm32l4_ep_submit(struct usbdev_ep_s *ep, +static int stm32_ep_submit(struct usbdev_ep_s *ep, struct usbdev_req_s *req) { - struct stm32l4_req_s *privreq = (struct stm32l4_req_s *)req; - struct stm32l4_ep_s *privep = (struct stm32l4_ep_s *)ep; - struct stm32l4_usbdev_s *priv; + struct stm32_req_s *privreq = (struct stm32_req_s *)req; + struct stm32_ep_s *privep = (struct stm32_ep_s *)ep; + struct stm32_usbdev_s *priv; irqstate_t flags; int ret = OK; @@ -4566,7 +4566,7 @@ static int stm32l4_ep_submit(struct usbdev_ep_s *ep, #ifdef CONFIG_DEBUG_FEATURES if (!req || !req->callback || !req->buf || !ep) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_INVALIDPARMS), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); uinfo("req=%p callback=%p buf=%p ep=%p\n", req, req->callback, req->buf, ep); return -EINVAL; @@ -4579,7 +4579,7 @@ static int stm32l4_ep_submit(struct usbdev_ep_s *ep, #ifdef CONFIG_DEBUG_FEATURES if (!priv->driver) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_NOTCONFIGURED), + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_NOTCONFIGURED), priv->usbdev.speed); return -ESHUTDOWN; } @@ -4604,7 +4604,7 @@ static int stm32l4_ep_submit(struct usbdev_ep_s *ep, { /* Add the new request to the request queue for the endpoint. */ - if (stm32l4_req_addlast(privep, privreq) && !privep->active) + if (stm32_req_addlast(privep, privreq) && !privep->active) { /* If a request was added to an IN endpoint, then attempt to send * the request data buffer now. @@ -4620,7 +4620,7 @@ static int stm32l4_ep_submit(struct usbdev_ep_s *ep, if (!privep->active) { - stm32l4_epin_request(priv, privep); + stm32_epin_request(priv, privep); } } @@ -4632,7 +4632,7 @@ static int stm32l4_ep_submit(struct usbdev_ep_s *ep, else { usbtrace(TRACE_OUTREQQUEUED(privep->epphy), privreq->req.len); - stm32l4_epout_request(priv, privep); + stm32_epout_request(priv, privep); } } } @@ -4642,23 +4642,23 @@ static int stm32l4_ep_submit(struct usbdev_ep_s *ep, } /**************************************************************************** - * Name: stm32l4_ep_cancel + * Name: stm32_ep_cancel * * Description: * Cancel an I/O request previously sent to an endpoint * ****************************************************************************/ -static int stm32l4_ep_cancel(struct usbdev_ep_s *ep, +static int stm32_ep_cancel(struct usbdev_ep_s *ep, struct usbdev_req_s *req) { - struct stm32l4_ep_s *privep = (struct stm32l4_ep_s *)ep; + struct stm32_ep_s *privep = (struct stm32_ep_s *)ep; irqstate_t flags; #ifdef CONFIG_DEBUG_FEATURES if (!ep || !req) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_INVALIDPARMS), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); return -EINVAL; } #endif @@ -4673,20 +4673,20 @@ static int stm32l4_ep_cancel(struct usbdev_ep_s *ep, * but ... all other implementations cancel all requests ... */ - stm32l4_req_cancel(privep, -ESHUTDOWN); + stm32_req_cancel(privep, -ESHUTDOWN); leave_critical_section(flags); return OK; } /**************************************************************************** - * Name: stm32l4_epout_setstall + * Name: stm32_epout_setstall * * Description: * Stall an OUT endpoint * ****************************************************************************/ -static int stm32l4_epout_setstall(struct stm32l4_ep_s *privep) +static int stm32_epout_setstall(struct stm32_ep_s *privep) { #if 1 /* This implementation follows the requirements from the STM32 F4 reference @@ -4698,24 +4698,24 @@ static int stm32l4_epout_setstall(struct stm32l4_ep_s *privep) /* Put the core in the Global OUT NAK mode */ - stm32l4_enablegonak(privep); + stm32_enablegonak(privep); /* Disable and STALL the OUT endpoint by setting the EPDIS and STALL bits * in the DOECPTL register. */ - regaddr = STM32L4_OTGFS_DOEPCTL(privep->epphy); - regval = stm32l4_getreg(regaddr); + regaddr = STM32_OTGFS_DOEPCTL(privep->epphy); + regval = stm32_getreg(regaddr); regval |= (OTGFS_DOEPCTL_EPDIS | OTGFS_DOEPCTL_STALL); - stm32l4_putreg(regval, regaddr); + stm32_putreg(regval, regaddr); /* Wait for the EPDISD interrupt which indicates that the OUT * endpoint is completely disabled. */ #if 0 /* Doesn't happen */ - regaddr = STM32L4_OTGFS_DOEPINT(privep->epphy); - while ((stm32l4_getreg(regaddr) & OTGFS_DOEPINT_EPDISD) == 0); + regaddr = STM32_OTGFS_DOEPINT(privep->epphy); + while ((stm32_getreg(regaddr) & OTGFS_DOEPINT_EPDISD) == 0); #else /* REVISIT: */ @@ -4724,7 +4724,7 @@ static int stm32l4_epout_setstall(struct stm32l4_ep_s *privep) /* Disable Global OUT NAK mode */ - stm32l4_disablegonak(privep); + stm32_disablegonak(privep); /* The endpoint is now stalled */ @@ -4742,10 +4742,10 @@ static int stm32l4_epout_setstall(struct stm32l4_ep_s *privep) * register. */ - regaddr = STM32L4_OTGFS_DOEPCTL(privep->epphy); - regval = stm32l4_getreg(regaddr); + regaddr = STM32_OTGFS_DOEPCTL(privep->epphy); + regval = stm32_getreg(regaddr); regval |= OTGFS_DOEPCTL_STALL; - stm32l4_putreg(regval, regaddr); + stm32_putreg(regval, regaddr); /* The endpoint is now stalled */ @@ -4755,27 +4755,27 @@ static int stm32l4_epout_setstall(struct stm32l4_ep_s *privep) } /**************************************************************************** - * Name: stm32l4_epin_setstall + * Name: stm32_epin_setstall * * Description: * Stall an IN endpoint * ****************************************************************************/ -static int stm32l4_epin_setstall(struct stm32l4_ep_s *privep) +static int stm32_epin_setstall(struct stm32_ep_s *privep) { uint32_t regaddr; uint32_t regval; /* Get the IN endpoint device control register */ - regaddr = STM32L4_OTGFS_DIEPCTL(privep->epphy); - regval = stm32l4_getreg(regaddr); + regaddr = STM32_OTGFS_DIEPCTL(privep->epphy); + regval = stm32_getreg(regaddr); /* Then stall the endpoint */ regval |= OTGFS_DIEPCTL_STALL; - stm32l4_putreg(regval, regaddr); + stm32_putreg(regval, regaddr); /* The endpoint is now stalled */ @@ -4784,14 +4784,14 @@ static int stm32l4_epin_setstall(struct stm32l4_ep_s *privep) } /**************************************************************************** - * Name: stm32l4_ep_setstall + * Name: stm32_ep_setstall * * Description: * Stall an endpoint * ****************************************************************************/ -static int stm32l4_ep_setstall(struct stm32l4_ep_s *privep) +static int stm32_ep_setstall(struct stm32_ep_s *privep) { usbtrace(TRACE_EPSTALL, privep->epphy); @@ -4799,23 +4799,23 @@ static int stm32l4_ep_setstall(struct stm32l4_ep_s *privep) if (privep->isin == 1) { - return stm32l4_epin_setstall(privep); + return stm32_epin_setstall(privep); } else { - return stm32l4_epout_setstall(privep); + return stm32_epout_setstall(privep); } } /**************************************************************************** - * Name: stm32l4_ep_clrstall + * Name: stm32_ep_clrstall * * Description: * Resume a stalled endpoint * ****************************************************************************/ -static int stm32l4_ep_clrstall(struct stm32l4_ep_s *privep) +static int stm32_ep_clrstall(struct stm32_ep_s *privep) { uint32_t regaddr; uint32_t regval; @@ -4830,7 +4830,7 @@ static int stm32l4_ep_clrstall(struct stm32l4_ep_s *privep) { /* Clear the stall bit in the IN endpoint device control register */ - regaddr = STM32L4_OTGFS_DIEPCTL(privep->epphy); + regaddr = STM32_OTGFS_DIEPCTL(privep->epphy); stallbit = OTGFS_DIEPCTL_STALL; data0bit = OTGFS_DIEPCTL_SD0PID; } @@ -4838,14 +4838,14 @@ static int stm32l4_ep_clrstall(struct stm32l4_ep_s *privep) { /* Clear the stall bit in the IN endpoint device control register */ - regaddr = STM32L4_OTGFS_DOEPCTL(privep->epphy); + regaddr = STM32_OTGFS_DOEPCTL(privep->epphy); stallbit = OTGFS_DOEPCTL_STALL; data0bit = OTGFS_DOEPCTL_SD0PID; } /* Clear the stall bit */ - regval = stm32l4_getreg(regaddr); + regval = stm32_getreg(regaddr); regval &= ~stallbit; /* Set the DATA0 pid for interrupt and bulk endpoints */ @@ -4858,7 +4858,7 @@ static int stm32l4_ep_clrstall(struct stm32l4_ep_s *privep) regval |= data0bit; } - stm32l4_putreg(regval, regaddr); + stm32_putreg(regval, regaddr); /* The endpoint is no longer stalled */ @@ -4867,16 +4867,16 @@ static int stm32l4_ep_clrstall(struct stm32l4_ep_s *privep) } /**************************************************************************** - * Name: stm32l4_ep_stall + * Name: stm32_ep_stall * * Description: * Stall or resume an endpoint * ****************************************************************************/ -static int stm32l4_ep_stall(struct usbdev_ep_s *ep, bool resume) +static int stm32_ep_stall(struct usbdev_ep_s *ep, bool resume) { - struct stm32l4_ep_s *privep = (struct stm32l4_ep_s *)ep; + struct stm32_ep_s *privep = (struct stm32_ep_s *)ep; irqstate_t flags; int ret; @@ -4885,11 +4885,11 @@ static int stm32l4_ep_stall(struct usbdev_ep_s *ep, bool resume) flags = enter_critical_section(); if (resume) { - ret = stm32l4_ep_clrstall(privep); + ret = stm32_ep_clrstall(privep); } else { - ret = stm32l4_ep_setstall(privep); + ret = stm32_ep_setstall(privep); } leave_critical_section(flags); @@ -4898,19 +4898,19 @@ static int stm32l4_ep_stall(struct usbdev_ep_s *ep, bool resume) } /**************************************************************************** - * Name: stm32l4_ep0_stall + * Name: stm32_ep0_stall * * Description: * Stall endpoint 0 * ****************************************************************************/ -static void stm32l4_ep0_stall(struct stm32l4_usbdev_s *priv) +static void stm32_ep0_stall(struct stm32_usbdev_s *priv) { - stm32l4_epin_setstall(&priv->epin[EP0]); - stm32l4_epout_setstall(&priv->epout[EP0]); + stm32_epin_setstall(&priv->epin[EP0]); + stm32_epout_setstall(&priv->epout[EP0]); priv->stalled = true; - stm32l4_ep0out_ctrlsetup(priv); + stm32_ep0out_ctrlsetup(priv); } /**************************************************************************** @@ -4918,7 +4918,7 @@ static void stm32l4_ep0_stall(struct stm32l4_usbdev_s *priv) ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_ep_alloc + * Name: stm32_ep_alloc * * Description: * Allocate an endpoint matching the parameters. @@ -4933,11 +4933,11 @@ static void stm32l4_ep0_stall(struct stm32l4_usbdev_s *priv) * ****************************************************************************/ -static struct usbdev_ep_s *stm32l4_ep_alloc(struct usbdev_s *dev, +static struct usbdev_ep_s *stm32_ep_alloc(struct usbdev_s *dev, uint8_t eplog, bool in, uint8_t eptype) { - struct stm32l4_usbdev_s *priv = (struct stm32l4_usbdev_s *)dev; + struct stm32_usbdev_s *priv = (struct stm32_usbdev_s *)dev; uint8_t epavail; irqstate_t flags; int epphy; @@ -4966,9 +4966,9 @@ static struct usbdev_ep_s *stm32l4_ep_alloc(struct usbdev_s *dev, * by the hardware. */ - if (epphy >= STM32L4_NENDPOINTS) + if (epphy >= STM32_NENDPOINTS) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_BADEPNO), + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADEPNO), (uint16_t)epphy); return NULL; } @@ -4988,7 +4988,7 @@ static struct usbdev_ep_s *stm32l4_ep_alloc(struct usbdev_s *dev, * endpoints. */ - for (epno = 1; epno < STM32L4_NENDPOINTS; epno++) + for (epno = 1; epno < STM32_NENDPOINTS; epno++) { uint8_t bit = 1 << epno; if ((epavail & bit) != 0) @@ -5007,24 +5007,24 @@ static struct usbdev_ep_s *stm32l4_ep_alloc(struct usbdev_s *dev, /* We should not get here */ } - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_NOEP), (uint16_t)eplog); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_NOEP), (uint16_t)eplog); leave_critical_section(flags); return NULL; } /**************************************************************************** - * Name: stm32l4_ep_free + * Name: stm32_ep_free * * Description: * Free the previously allocated endpoint * ****************************************************************************/ -static void stm32l4_ep_free(struct usbdev_s *dev, +static void stm32_ep_free(struct usbdev_s *dev, struct usbdev_ep_s *ep) { - struct stm32l4_usbdev_s *priv = (struct stm32l4_usbdev_s *)dev; - struct stm32l4_ep_s *privep = (struct stm32l4_ep_s *)ep; + struct stm32_usbdev_s *priv = (struct stm32_usbdev_s *)dev; + struct stm32_ep_s *privep = (struct stm32_ep_s *)ep; irqstate_t flags; usbtrace(TRACE_DEVFREEEP, (uint16_t)privep->epphy); @@ -5040,14 +5040,14 @@ static void stm32l4_ep_free(struct usbdev_s *dev, } /**************************************************************************** - * Name: stm32l4_getframe + * Name: stm32_getframe * * Description: * Returns the current frame number * ****************************************************************************/ -static int stm32l4_getframe(struct usbdev_s *dev) +static int stm32_getframe(struct usbdev_s *dev) { uint32_t regval; @@ -5055,21 +5055,21 @@ static int stm32l4_getframe(struct usbdev_s *dev) /* Return the last frame number of the last SOF detected by the hardware */ - regval = stm32l4_getreg(STM32L4_OTGFS_DSTS); + regval = stm32_getreg(STM32_OTGFS_DSTS); return (int)((regval & OTGFS_DSTS_SOFFN_MASK) >> OTGFS_DSTS_SOFFN_SHIFT); } /**************************************************************************** - * Name: stm32l4_wakeup + * Name: stm32_wakeup * * Description: * Exit suspend mode. * ****************************************************************************/ -static int stm32l4_wakeup(struct usbdev_s *dev) +static int stm32_wakeup(struct usbdev_s *dev) { - struct stm32l4_usbdev_s *priv = (struct stm32l4_usbdev_s *)dev; + struct stm32_usbdev_s *priv = (struct stm32_usbdev_s *)dev; uint32_t regval; irqstate_t flags; @@ -5082,24 +5082,24 @@ static int stm32l4_wakeup(struct usbdev_s *dev) { /* Yes... is the core suspended? */ - regval = stm32l4_getreg(STM32L4_OTGFS_DSTS); + regval = stm32_getreg(STM32_OTGFS_DSTS); if ((regval & OTGFS_DSTS_SUSPSTS) != 0) { /* Re-start the PHY clock and un-gate USB core clock (HCLK) */ #ifdef CONFIG_USBDEV_LOWPOWER - regval = stm32l4_getreg(STM32L4_OTGFS_PCGCCTL); + regval = stm32_getreg(STM32_OTGFS_PCGCCTL); regval &= ~(OTGFS_PCGCCTL_STPPCLK | OTGFS_PCGCCTL_GATEHCLK); - stm32l4_putreg(regval, STM32L4_OTGFS_PCGCCTL); + stm32_putreg(regval, STM32_OTGFS_PCGCCTL); #endif /* Activate Remote wakeup signaling */ - regval = stm32l4_getreg(STM32L4_OTGFS_DCTL); + regval = stm32_getreg(STM32_OTGFS_DCTL); regval |= OTGFS_DCTL_RWUSIG; - stm32l4_putreg(regval, STM32L4_OTGFS_DCTL); + stm32_putreg(regval, STM32_OTGFS_DCTL); up_mdelay(5); regval &= ~OTGFS_DCTL_RWUSIG; - stm32l4_putreg(regval, STM32L4_OTGFS_DCTL); + stm32_putreg(regval, STM32_OTGFS_DCTL); } } @@ -5108,23 +5108,23 @@ static int stm32l4_wakeup(struct usbdev_s *dev) } /**************************************************************************** - * Name: stm32l4_selfpowered + * Name: stm32_selfpowered * * Description: * Sets/clears the device self-powered feature * ****************************************************************************/ -static int stm32l4_selfpowered(struct usbdev_s *dev, bool selfpowered) +static int stm32_selfpowered(struct usbdev_s *dev, bool selfpowered) { - struct stm32l4_usbdev_s *priv = (struct stm32l4_usbdev_s *)dev; + struct stm32_usbdev_s *priv = (struct stm32_usbdev_s *)dev; usbtrace(TRACE_DEVSELFPOWERED, (uint16_t)selfpowered); #ifdef CONFIG_DEBUG_FEATURES if (!dev) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_INVALIDPARMS), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); return -ENODEV; } #endif @@ -5134,21 +5134,21 @@ static int stm32l4_selfpowered(struct usbdev_s *dev, bool selfpowered) } /**************************************************************************** - * Name: stm32l4_pullup + * Name: stm32_pullup * * Description: * Software-controlled connect to/disconnect from USB host * ****************************************************************************/ -static int stm32l4_pullup(struct usbdev_s *dev, bool enable) +static int stm32_pullup(struct usbdev_s *dev, bool enable) { uint32_t regval; usbtrace(TRACE_DEVPULLUP, (uint16_t)enable); irqstate_t flags = enter_critical_section(); - regval = stm32l4_getreg(STM32L4_OTGFS_DCTL); + regval = stm32_getreg(STM32_OTGFS_DCTL); if (enable) { /* Connect the device by clearing the soft disconnect bit in the DCTL @@ -5166,30 +5166,30 @@ static int stm32l4_pullup(struct usbdev_s *dev, bool enable) regval |= OTGFS_DCTL_SDIS; } - stm32l4_putreg(regval, STM32L4_OTGFS_DCTL); + stm32_putreg(regval, STM32_OTGFS_DCTL); leave_critical_section(flags); return OK; } /**************************************************************************** - * Name: stm32l4_setaddress + * Name: stm32_setaddress * * Description: * Set the devices USB address * ****************************************************************************/ -static void stm32l4_setaddress(struct stm32l4_usbdev_s *priv, +static void stm32_setaddress(struct stm32_usbdev_s *priv, uint16_t address) { uint32_t regval; /* Set the device address in the DCFG register */ - regval = stm32l4_getreg(STM32L4_OTGFS_DCFG); + regval = stm32_getreg(STM32_OTGFS_DCFG); regval &= ~OTGFS_DCFG_DAD_MASK; regval |= ((uint32_t)address << OTGFS_DCFG_DAD_SHIFT); - stm32l4_putreg(regval, STM32L4_OTGFS_DCFG); + stm32_putreg(regval, STM32_OTGFS_DCFG); /* Are we now addressed? (i.e., do we have a non-NULL device * address?) @@ -5208,14 +5208,14 @@ static void stm32l4_setaddress(struct stm32l4_usbdev_s *priv, } /**************************************************************************** - * Name: stm32l4_txfifo_flush + * Name: stm32_txfifo_flush * * Description: * Flush the specific TX fifo. * ****************************************************************************/ -static int stm32l4_txfifo_flush(uint32_t txfnum) +static int stm32_txfifo_flush(uint32_t txfnum) { uint32_t regval; uint32_t timeout; @@ -5223,13 +5223,13 @@ static int stm32l4_txfifo_flush(uint32_t txfnum) /* Initiate the TX FIFO flush operation */ regval = OTGFS_GRSTCTL_TXFFLSH | txfnum; - stm32l4_putreg(regval, STM32L4_OTGFS_GRSTCTL); + stm32_putreg(regval, STM32_OTGFS_GRSTCTL); /* Wait for the FLUSH to complete */ - for (timeout = 0; timeout < STM32L4_FLUSH_DELAY; timeout++) + for (timeout = 0; timeout < STM32_FLUSH_DELAY; timeout++) { - regval = stm32l4_getreg(STM32L4_OTGFS_GRSTCTL); + regval = stm32_getreg(STM32_OTGFS_GRSTCTL); if ((regval & OTGFS_GRSTCTL_TXFFLSH) == 0) { break; @@ -5243,27 +5243,27 @@ static int stm32l4_txfifo_flush(uint32_t txfnum) } /**************************************************************************** - * Name: stm32l4_rxfifo_flush + * Name: stm32_rxfifo_flush * * Description: * Flush the RX fifo. * ****************************************************************************/ -static int stm32l4_rxfifo_flush(void) +static int stm32_rxfifo_flush(void) { uint32_t regval; uint32_t timeout; /* Initiate the RX FIFO flush operation */ - stm32l4_putreg(OTGFS_GRSTCTL_RXFFLSH, STM32L4_OTGFS_GRSTCTL); + stm32_putreg(OTGFS_GRSTCTL_RXFFLSH, STM32_OTGFS_GRSTCTL); /* Wait for the FLUSH to complete */ - for (timeout = 0; timeout < STM32L4_FLUSH_DELAY; timeout++) + for (timeout = 0; timeout < STM32_FLUSH_DELAY; timeout++) { - regval = stm32l4_getreg(STM32L4_OTGFS_GRSTCTL); + regval = stm32_getreg(STM32_OTGFS_GRSTCTL); if ((regval & OTGFS_GRSTCTL_RXFFLSH) == 0) { break; @@ -5277,31 +5277,31 @@ static int stm32l4_rxfifo_flush(void) } /**************************************************************************** - * Name: stm32l4_swinitialize + * Name: stm32_swinitialize * * Description: * Initialize all driver data structures. * ****************************************************************************/ -static void stm32l4_swinitialize(struct stm32l4_usbdev_s *priv) +static void stm32_swinitialize(struct stm32_usbdev_s *priv) { - struct stm32l4_ep_s *privep; + struct stm32_ep_s *privep; int i; /* Initialize the device state structure */ - memset(priv, 0, sizeof(struct stm32l4_usbdev_s)); + memset(priv, 0, sizeof(struct stm32_usbdev_s)); priv->usbdev.ops = &g_devops; priv->usbdev.ep0 = &priv->epin[EP0].ep; - priv->epavail[0] = STM32L4_EP_AVAILABLE; - priv->epavail[1] = STM32L4_EP_AVAILABLE; + priv->epavail[0] = STM32_EP_AVAILABLE; + priv->epavail[1] = STM32_EP_AVAILABLE; /* Initialize the IN endpoint list */ - for (i = 0; i < STM32L4_NENDPOINTS; i++) + for (i = 0; i < STM32_NENDPOINTS; i++) { /* Set endpoint operations, reference to driver structure (not * really necessary because there is only one controller), and @@ -5319,7 +5319,7 @@ static void stm32l4_swinitialize(struct stm32l4_usbdev_s *priv) */ privep->epphy = i; - privep->ep.eplog = STM32L4_EPPHYIN2LOG(i); + privep->ep.eplog = STM32_EPPHYIN2LOG(i); /* Control until endpoint is activated */ @@ -5329,7 +5329,7 @@ static void stm32l4_swinitialize(struct stm32l4_usbdev_s *priv) /* Initialize the OUT endpoint list */ - for (i = 0; i < STM32L4_NENDPOINTS; i++) + for (i = 0; i < STM32_NENDPOINTS; i++) { /* Set endpoint operations, reference to driver structure (not * really necessary because there is only one controller), and @@ -5346,7 +5346,7 @@ static void stm32l4_swinitialize(struct stm32l4_usbdev_s *priv) */ privep->epphy = i; - privep->ep.eplog = STM32L4_EPPHYOUT2LOG(i); + privep->ep.eplog = STM32_EPPHYOUT2LOG(i); /* Control until endpoint is activated */ @@ -5356,14 +5356,14 @@ static void stm32l4_swinitialize(struct stm32l4_usbdev_s *priv) } /**************************************************************************** - * Name: stm32l4_hwinitialize + * Name: stm32_hwinitialize * * Description: * Configure the OTG FS core for operation. * ****************************************************************************/ -static void stm32l4_hwinitialize(struct stm32l4_usbdev_s *priv) +static void stm32_hwinitialize(struct stm32_usbdev_s *priv) { uint32_t regval; uint32_t timeout; @@ -5372,7 +5372,7 @@ static void stm32l4_hwinitialize(struct stm32l4_usbdev_s *priv) /* Enable Vbus monitoring in the Power control */ - stm32l4_pwr_enableusv(true); + stm32_pwr_enableusv(true); /* At start-up the core is in FS mode. */ @@ -5382,7 +5382,7 @@ static void stm32l4_hwinitialize(struct stm32l4_usbdev_s *priv) * (not just half full). */ - stm32l4_putreg(OTGFS_GAHBCFG_TXFELVL, STM32L4_OTGFS_GAHBCFG); + stm32_putreg(OTGFS_GAHBCFG_TXFELVL, STM32_OTGFS_GAHBCFG); /* Common USB OTG core initialization */ @@ -5390,10 +5390,10 @@ static void stm32l4_hwinitialize(struct stm32l4_usbdev_s *priv) * IDLE state. */ - for (timeout = 0; timeout < STM32L4_READY_DELAY; timeout++) + for (timeout = 0; timeout < STM32_READY_DELAY; timeout++) { up_udelay(3); - regval = stm32l4_getreg(STM32L4_OTGFS_GRSTCTL); + regval = stm32_getreg(STM32_OTGFS_GRSTCTL); if ((regval & OTGFS_GRSTCTL_AHBIDL) != 0) { break; @@ -5402,10 +5402,10 @@ static void stm32l4_hwinitialize(struct stm32l4_usbdev_s *priv) /* Then perform the core soft reset. */ - stm32l4_putreg(OTGFS_GRSTCTL_CSRST, STM32L4_OTGFS_GRSTCTL); - for (timeout = 0; timeout < STM32L4_READY_DELAY; timeout++) + stm32_putreg(OTGFS_GRSTCTL_CSRST, STM32_OTGFS_GRSTCTL); + for (timeout = 0; timeout < STM32_READY_DELAY; timeout++) { - regval = stm32l4_getreg(STM32L4_OTGFS_GRSTCTL); + regval = stm32_getreg(STM32_OTGFS_GRSTCTL); if ((regval & OTGFS_GRSTCTL_CSRST) == 0) { break; @@ -5426,121 +5426,121 @@ static void stm32l4_hwinitialize(struct stm32l4_usbdev_s *priv) regval |= OTGFS_GCCFG_VBDEN; #endif - stm32l4_putreg(regval, STM32L4_OTGFS_GCCFG); + stm32_putreg(regval, STM32_OTGFS_GCCFG); up_mdelay(20); /* When VBUS sensing is not used we need to force the B session valid */ #ifndef CONFIG_USBDEV_VBUSSENSING - regval = stm32l4_getreg(STM32L4_OTGFS_GOTGCTL); + regval = stm32_getreg(STM32_OTGFS_GOTGCTL); regval |= (OTGFS_GOTGCTL_BVALOEN | OTGFS_GOTGCTL_BVALOVAL); - stm32l4_putreg(regval, STM32L4_OTGFS_GOTGCTL); + stm32_putreg(regval, STM32_OTGFS_GOTGCTL); #endif /* Force Device Mode */ - regval = stm32l4_getreg(STM32L4_OTGFS_GUSBCFG); + regval = stm32_getreg(STM32_OTGFS_GUSBCFG); regval &= ~OTGFS_GUSBCFG_FHMOD; regval |= OTGFS_GUSBCFG_FDMOD; - stm32l4_putreg(regval, STM32L4_OTGFS_GUSBCFG); + stm32_putreg(regval, STM32_OTGFS_GUSBCFG); up_mdelay(50); /* Initialize device mode */ /* Restart the PHY Clock */ - stm32l4_putreg(0, STM32L4_OTGFS_PCGCCTL); + stm32_putreg(0, STM32_OTGFS_PCGCCTL); /* Device configuration register */ - regval = stm32l4_getreg(STM32L4_OTGFS_DCFG); + regval = stm32_getreg(STM32_OTGFS_DCFG); regval &= ~OTGFS_DCFG_PFIVL_MASK; regval |= OTGFS_DCFG_PFIVL_80PCT; - stm32l4_putreg(regval, STM32L4_OTGFS_DCFG); + stm32_putreg(regval, STM32_OTGFS_DCFG); /* Set full speed PHY */ - regval = stm32l4_getreg(STM32L4_OTGFS_DCFG); + regval = stm32_getreg(STM32_OTGFS_DCFG); regval &= ~OTGFS_DCFG_DSPD_MASK; regval |= OTGFS_DCFG_DSPD_FS; - stm32l4_putreg(regval, STM32L4_OTGFS_DCFG); + stm32_putreg(regval, STM32_OTGFS_DCFG); /* Set Rx FIFO size */ - stm32l4_putreg(STM32L4_RXFIFO_WORDS, STM32L4_OTGFS_GRXFSIZ); + stm32_putreg(STM32_RXFIFO_WORDS, STM32_OTGFS_GRXFSIZ); -#if STM32L4_NENDPOINTS > 0 +#if STM32_NENDPOINTS > 0 /* EP0 TX */ - address = STM32L4_RXFIFO_WORDS; + address = STM32_RXFIFO_WORDS; regval = (address << OTGFS_DIEPTXF0_TX0FD_SHIFT) | - (STM32L4_EP0_TXFIFO_WORDS << OTGFS_DIEPTXF0_TX0FSA_SHIFT); - stm32l4_putreg(regval, STM32L4_OTGFS_DIEPTXF0); + (STM32_EP0_TXFIFO_WORDS << OTGFS_DIEPTXF0_TX0FSA_SHIFT); + stm32_putreg(regval, STM32_OTGFS_DIEPTXF0); #endif -#if STM32L4_NENDPOINTS > 1 +#if STM32_NENDPOINTS > 1 /* EP1 TX */ - address += STM32L4_EP0_TXFIFO_WORDS; + address += STM32_EP0_TXFIFO_WORDS; regval = (address << OTGFS_DIEPTXF_INEPTXSA_SHIFT) | - (STM32L4_EP1_TXFIFO_WORDS << OTGFS_DIEPTXF_INEPTXFD_SHIFT); - stm32l4_putreg(regval, STM32L4_OTGFS_DIEPTXF(1)); + (STM32_EP1_TXFIFO_WORDS << OTGFS_DIEPTXF_INEPTXFD_SHIFT); + stm32_putreg(regval, STM32_OTGFS_DIEPTXF(1)); #endif -#if STM32L4_NENDPOINTS > 2 +#if STM32_NENDPOINTS > 2 /* EP2 TX */ - address += STM32L4_EP1_TXFIFO_WORDS; + address += STM32_EP1_TXFIFO_WORDS; regval = (address << OTGFS_DIEPTXF_INEPTXSA_SHIFT) | - (STM32L4_EP2_TXFIFO_WORDS << OTGFS_DIEPTXF_INEPTXFD_SHIFT); - stm32l4_putreg(regval, STM32L4_OTGFS_DIEPTXF(2)); + (STM32_EP2_TXFIFO_WORDS << OTGFS_DIEPTXF_INEPTXFD_SHIFT); + stm32_putreg(regval, STM32_OTGFS_DIEPTXF(2)); #endif -#if STM32L4_NENDPOINTS > 3 +#if STM32_NENDPOINTS > 3 /* EP3 TX */ - address += STM32L4_EP2_TXFIFO_WORDS; + address += STM32_EP2_TXFIFO_WORDS; regval = (address << OTGFS_DIEPTXF_INEPTXSA_SHIFT) | - (STM32L4_EP3_TXFIFO_WORDS << OTGFS_DIEPTXF_INEPTXFD_SHIFT); - stm32l4_putreg(regval, STM32L4_OTGFS_DIEPTXF(3)); + (STM32_EP3_TXFIFO_WORDS << OTGFS_DIEPTXF_INEPTXFD_SHIFT); + stm32_putreg(regval, STM32_OTGFS_DIEPTXF(3)); #endif -#if STM32L4_NENDPOINTS > 4 +#if STM32_NENDPOINTS > 4 /* EP4 TX */ - address += STM32L4_EP3_TXFIFO_WORDS; + address += STM32_EP3_TXFIFO_WORDS; regval = (address << OTGFS_DIEPTXF_INEPTXSA_SHIFT) | - (STM32L4_EP4_TXFIFO_WORDS << OTGFS_DIEPTXF_INEPTXFD_SHIFT); - stm32l4_putreg(regval, STM32L4_OTGFS_DIEPTXF(4)); + (STM32_EP4_TXFIFO_WORDS << OTGFS_DIEPTXF_INEPTXFD_SHIFT); + stm32_putreg(regval, STM32_OTGFS_DIEPTXF(4)); #endif -#if STM32L4_NENDPOINTS > 5 +#if STM32_NENDPOINTS > 5 /* EP5 TX */ - address += STM32L4_EP4_TXFIFO_WORDS; + address += STM32_EP4_TXFIFO_WORDS; regval = (address << OTGFS_DIEPTXF_INEPTXSA_SHIFT) | - (STM32L4_EP5_TXFIFO_WORDS << OTGFS_DIEPTXF_INEPTXFD_SHIFT); - stm32l4_putreg(regval, STM32L4_OTGFS_DIEPTXF(5)); + (STM32_EP5_TXFIFO_WORDS << OTGFS_DIEPTXF_INEPTXFD_SHIFT); + stm32_putreg(regval, STM32_OTGFS_DIEPTXF(5)); #endif /* Flush the FIFOs */ - stm32l4_txfifo_flush(OTGFS_GRSTCTL_TXFNUM_DALL); - stm32l4_rxfifo_flush(); + stm32_txfifo_flush(OTGFS_GRSTCTL_TXFNUM_DALL); + stm32_rxfifo_flush(); /* Clear all pending Device Interrupts */ - stm32l4_putreg(0, STM32L4_OTGFS_DIEPMSK); - stm32l4_putreg(0, STM32L4_OTGFS_DOEPMSK); - stm32l4_putreg(0, STM32L4_OTGFS_DIEPEMPMSK); - stm32l4_putreg(0xffffffff, STM32L4_OTGFS_DAINT); - stm32l4_putreg(0, STM32L4_OTGFS_DAINTMSK); + stm32_putreg(0, STM32_OTGFS_DIEPMSK); + stm32_putreg(0, STM32_OTGFS_DOEPMSK); + stm32_putreg(0, STM32_OTGFS_DIEPEMPMSK); + stm32_putreg(0xffffffff, STM32_OTGFS_DAINT); + stm32_putreg(0, STM32_OTGFS_DAINTMSK); /* Configure all IN endpoints */ - for (i = 0; i < STM32L4_NENDPOINTS; i++) + for (i = 0; i < STM32_NENDPOINTS; i++) { - regval = stm32l4_getreg(STM32L4_OTGFS_DIEPCTL(i)); + regval = stm32_getreg(STM32_OTGFS_DIEPCTL(i)); if ((regval & OTGFS_DIEPCTL_EPENA) != 0) { /* The endpoint is already enabled */ @@ -5552,16 +5552,16 @@ static void stm32l4_hwinitialize(struct stm32l4_usbdev_s *priv) regval = 0; } - stm32l4_putreg(regval, STM32L4_OTGFS_DIEPCTL(i)); - stm32l4_putreg(0, STM32L4_OTGFS_DIEPTSIZ(i)); - stm32l4_putreg(0xff, STM32L4_OTGFS_DIEPINT(i)); + stm32_putreg(regval, STM32_OTGFS_DIEPCTL(i)); + stm32_putreg(0, STM32_OTGFS_DIEPTSIZ(i)); + stm32_putreg(0xff, STM32_OTGFS_DIEPINT(i)); } /* Configure all OUT endpoints */ - for (i = 0; i < STM32L4_NENDPOINTS; i++) + for (i = 0; i < STM32_NENDPOINTS; i++) { - regval = stm32l4_getreg(STM32L4_OTGFS_DOEPCTL(i)); + regval = stm32_getreg(STM32_OTGFS_DOEPCTL(i)); if ((regval & OTGFS_DOEPCTL_EPENA) != 0) { /* The endpoint is already enabled */ @@ -5573,24 +5573,24 @@ static void stm32l4_hwinitialize(struct stm32l4_usbdev_s *priv) regval = 0; } - stm32l4_putreg(regval, STM32L4_OTGFS_DOEPCTL(i)); - stm32l4_putreg(0, STM32L4_OTGFS_DOEPTSIZ(i)); - stm32l4_putreg(0xff, STM32L4_OTGFS_DOEPINT(i)); + stm32_putreg(regval, STM32_OTGFS_DOEPCTL(i)); + stm32_putreg(0, STM32_OTGFS_DOEPTSIZ(i)); + stm32_putreg(0xff, STM32_OTGFS_DOEPINT(i)); } /* Disable all interrupts. */ - stm32l4_putreg(0, STM32L4_OTGFS_GINTMSK); + stm32_putreg(0, STM32_OTGFS_GINTMSK); /* Clear any pending USB_OTG Interrupts */ - stm32l4_putreg(0xffffffff, STM32L4_OTGFS_GOTGINT); + stm32_putreg(0xffffffff, STM32_OTGFS_GOTGINT); /* Clear any pending interrupts */ - regval = stm32l4_getreg(STM32L4_OTGFS_GINTSTS); + regval = stm32_getreg(STM32_OTGFS_GINTSTS); regval &= OTGFS_GINT_RESERVED; - stm32l4_putreg(regval | OTGFS_GINT_RC_W1, STM32L4_OTGFS_GINTSTS); + stm32_putreg(regval | OTGFS_GINT_RC_W1, STM32_OTGFS_GINTSTS); /* Enable the interrupts in the INTMSK */ @@ -5613,7 +5613,7 @@ static void stm32l4_hwinitialize(struct stm32l4_usbdev_s *priv) regval |= OTGFS_GINT_MMIS; #endif - stm32l4_putreg(regval, STM32L4_OTGFS_GINTMSK); + stm32_putreg(regval, STM32_OTGFS_GINTMSK); /* Enable the USB global interrupt by setting GINTMSK in the global OTG * FS AHB configuration register; Set the TXFELVL bit in the GAHBCFG @@ -5621,8 +5621,8 @@ static void stm32l4_hwinitialize(struct stm32l4_usbdev_s *priv) * empty (not just half full). */ - stm32l4_putreg(OTGFS_GAHBCFG_GINTMSK | OTGFS_GAHBCFG_TXFELVL, - STM32L4_OTGFS_GAHBCFG); + stm32_putreg(OTGFS_GAHBCFG_GINTMSK | OTGFS_GAHBCFG_TXFELVL, + STM32_OTGFS_GAHBCFG); } /**************************************************************************** @@ -5653,7 +5653,7 @@ void arm_usbinitialize(void) * devices. */ - struct stm32l4_usbdev_s *priv = &g_otgfsdev; + struct stm32_usbdev_s *priv = &g_otgfsdev; int ret; usbtrace(TRACE_DEVINIT, 0); @@ -5681,14 +5681,14 @@ void arm_usbinitialize(void) * *Pins may vary from device-to-device. */ - stm32l4_configgpio(GPIO_OTGFS_DM); - stm32l4_configgpio(GPIO_OTGFS_DP); - stm32l4_configgpio(GPIO_OTGFS_ID); /* Only needed for OTG */ + stm32_configgpio(GPIO_OTGFS_DM); + stm32_configgpio(GPIO_OTGFS_DP); + stm32_configgpio(GPIO_OTGFS_ID); /* Only needed for OTG */ /* SOF output pin configuration is configurable. */ -#ifdef CONFIG_STM32L4_OTGFS_SOFOUTPUT - stm32l4_configgpio(GPIO_OTGFS_SOF); +#ifdef CONFIG_STM32_OTGFS_SOFOUTPUT + stm32_configgpio(GPIO_OTGFS_SOF); #endif /* Uninitialize the hardware so that we know that we are starting from a @@ -5699,11 +5699,11 @@ void arm_usbinitialize(void) /* Initialize the driver data structure */ - stm32l4_swinitialize(priv); + stm32_swinitialize(priv); /* Attach the OTG FS interrupt handler */ - ret = irq_attach(STM32L4_IRQ_OTGFS, stm32l4_usbinterrupt, NULL); + ret = irq_attach(STM32_IRQ_OTGFS, stm32_usbinterrupt, NULL); if (ret < 0) { uerr("ERROR: irq_attach failed: %d\n", ret); @@ -5712,19 +5712,19 @@ void arm_usbinitialize(void) /* Initialize the USB OTG core */ - stm32l4_hwinitialize(priv); + stm32_hwinitialize(priv); /* Disconnect device */ - stm32l4_pullup(&priv->usbdev, false); + stm32_pullup(&priv->usbdev, false); /* Reset/Re-initialize the USB hardware */ - stm32l4_usbreset(priv); + stm32_usbreset(priv); /* Enable USB controller interrupts at the NVIC */ - up_enable_irq(STM32L4_IRQ_OTGFS); + up_enable_irq(STM32_IRQ_OTGFS); return; errout: @@ -5744,7 +5744,7 @@ void arm_usbuninitialize(void) * devices. */ - struct stm32l4_usbdev_s *priv = &g_otgfsdev; + struct stm32_usbdev_s *priv = &g_otgfsdev; irqstate_t flags; int i; @@ -5752,39 +5752,39 @@ void arm_usbuninitialize(void) if (priv->driver) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_DRIVERREGISTERED), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_DRIVERREGISTERED), 0); usbdev_unregister(priv->driver); } /* Disconnect device */ flags = enter_critical_section(); - stm32l4_pullup(&priv->usbdev, false); + stm32_pullup(&priv->usbdev, false); priv->usbdev.speed = USB_SPEED_UNKNOWN; /* Disable and detach IRQs */ - up_disable_irq(STM32L4_IRQ_OTGFS); - irq_detach(STM32L4_IRQ_OTGFS); + up_disable_irq(STM32_IRQ_OTGFS); + irq_detach(STM32_IRQ_OTGFS); /* Disable all endpoint interrupts */ - for (i = 0; i < STM32L4_NENDPOINTS; i++) + for (i = 0; i < STM32_NENDPOINTS; i++) { - stm32l4_putreg(0xff, STM32L4_OTGFS_DIEPINT(i)); - stm32l4_putreg(0xff, STM32L4_OTGFS_DOEPINT(i)); + stm32_putreg(0xff, STM32_OTGFS_DIEPINT(i)); + stm32_putreg(0xff, STM32_OTGFS_DOEPINT(i)); } - stm32l4_putreg(0, STM32L4_OTGFS_DIEPMSK); - stm32l4_putreg(0, STM32L4_OTGFS_DOEPMSK); - stm32l4_putreg(0, STM32L4_OTGFS_DIEPEMPMSK); - stm32l4_putreg(0, STM32L4_OTGFS_DAINTMSK); - stm32l4_putreg(0xffffffff, STM32L4_OTGFS_DAINT); + stm32_putreg(0, STM32_OTGFS_DIEPMSK); + stm32_putreg(0, STM32_OTGFS_DOEPMSK); + stm32_putreg(0, STM32_OTGFS_DIEPEMPMSK); + stm32_putreg(0, STM32_OTGFS_DAINTMSK); + stm32_putreg(0xffffffff, STM32_OTGFS_DAINT); /* Flush the FIFOs */ - stm32l4_txfifo_flush(OTGFS_GRSTCTL_TXFNUM_DALL); - stm32l4_rxfifo_flush(); + stm32_txfifo_flush(OTGFS_GRSTCTL_TXFNUM_DALL); + stm32_rxfifo_flush(); /* TODO: Turn off USB power and clocking */ @@ -5810,7 +5810,7 @@ int usbdev_register(struct usbdevclass_driver_s *driver) * devices. */ - struct stm32l4_usbdev_s *priv = &g_otgfsdev; + struct stm32_usbdev_s *priv = &g_otgfsdev; int ret; usbtrace(TRACE_DEVREGISTER, 0); @@ -5819,13 +5819,13 @@ int usbdev_register(struct usbdevclass_driver_s *driver) if (!driver || !driver->ops->bind || !driver->ops->unbind || !driver->ops->disconnect || !driver->ops->setup) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_INVALIDPARMS), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); return -EINVAL; } if (priv->driver) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_DRIVER), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_DRIVER), 0); return -EBUSY; } #endif @@ -5839,14 +5839,14 @@ int usbdev_register(struct usbdevclass_driver_s *driver) ret = CLASS_BIND(driver, &priv->usbdev); if (ret) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_BINDFAILED), (uint16_t)-ret); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BINDFAILED), (uint16_t)-ret); priv->driver = NULL; } else { /* Enable USB controller interrupts */ - up_enable_irq(STM32L4_IRQ_OTGFS); + up_enable_irq(STM32_IRQ_OTGFS); /* FIXME: nothing seems to call DEV_CONNECT(), but we need to set * the RS bit to enable the controller. It kind of makes sense @@ -5856,7 +5856,7 @@ int usbdev_register(struct usbdevclass_driver_s *driver) * that logic to the class drivers but left this logic here. */ - stm32l4_pullup(&priv->usbdev, true); + stm32_pullup(&priv->usbdev, true); priv->usbdev.speed = USB_SPEED_FULL; } @@ -5883,7 +5883,7 @@ int usbdev_unregister(struct usbdevclass_driver_s *driver) * devices. */ - struct stm32l4_usbdev_s *priv = &g_otgfsdev; + struct stm32_usbdev_s *priv = &g_otgfsdev; irqstate_t flags; usbtrace(TRACE_DEVUNREGISTER, 0); @@ -5891,7 +5891,7 @@ int usbdev_unregister(struct usbdevclass_driver_s *driver) #ifdef CONFIG_DEBUG_FEATURES if (driver != priv->driver) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_INVALIDPARMS), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); return -EINVAL; } #endif @@ -5901,7 +5901,7 @@ int usbdev_unregister(struct usbdevclass_driver_s *driver) */ flags = enter_critical_section(); - stm32l4_usbreset(priv); + stm32_usbreset(priv); leave_critical_section(flags); /* Unbind the class driver */ @@ -5911,11 +5911,11 @@ int usbdev_unregister(struct usbdevclass_driver_s *driver) /* Disable USB controller interrupts */ flags = enter_critical_section(); - up_disable_irq(STM32L4_IRQ_OTGFS); + up_disable_irq(STM32_IRQ_OTGFS); /* Disconnect device */ - stm32l4_pullup(&priv->usbdev, false); + stm32_pullup(&priv->usbdev, false); /* Unhook the driver */ @@ -5925,4 +5925,4 @@ int usbdev_unregister(struct usbdevclass_driver_s *driver) return OK; } -#endif /* CONFIG_USBDEV && CONFIG_STM32L4_OTGFSDEV */ +#endif /* CONFIG_USBDEV && CONFIG_STM32_OTGFSDEV */ diff --git a/arch/arm/src/stm32l4/stm32l4_otgfshost.c b/arch/arm/src/stm32l4/stm32l4_otgfshost.c index fa712e9494478..a560625f724f6 100644 --- a/arch/arm/src/stm32l4/stm32l4_otgfshost.c +++ b/arch/arm/src/stm32l4/stm32l4_otgfshost.c @@ -56,7 +56,7 @@ #include "arm_internal.h" #include "stm32l4_usbhost.h" -#if defined(CONFIG_USBHOST) && defined(CONFIG_STM32L4_OTGFS) +#if defined(CONFIG_USBHOST) && defined(CONFIG_STM32_OTGFS) /**************************************************************************** * Pre-processor Definitions @@ -69,82 +69,82 @@ * Pre-requisites * * CONFIG_USBHOST - Enable general USB host support - * CONFIG_STM32L4_OTGFS - Enable the STM32 USB OTG FS block - * CONFIG_STM32L4_SYSCFG - Needed + * CONFIG_STM32_OTGFS - Enable the STM32 USB OTG FS block + * CONFIG_STM32_SYSCFG - Needed * * Options: * - * CONFIG_STM32L4_OTGFS_RXFIFO_SIZE - Size of the RX FIFO in 32-bit words. + * CONFIG_STM32_OTGFS_RXFIFO_SIZE - Size of the RX FIFO in 32-bit words. * Default 128 (512 bytes) - * CONFIG_STM32L4_OTGFS_NPTXFIFO_SIZE - Size of the non-periodic Tx FIFO + * CONFIG_STM32_OTGFS_NPTXFIFO_SIZE - Size of the non-periodic Tx FIFO * in 32-bit words. Default 96 (384 bytes) - * CONFIG_STM32L4_OTGFS_PTXFIFO_SIZE - Size of the periodic Tx FIFO in + * CONFIG_STM32_OTGFS_PTXFIFO_SIZE - Size of the periodic Tx FIFO in * 32-bit words. Default 96 (384 bytes) - * CONFIG_STM32L4_OTGFS_DESCSIZE - Maximum size of a descriptor. Default: + * CONFIG_STM32_OTGFS_DESCSIZE - Maximum size of a descriptor. Default: * 128 - * CONFIG_STM32L4_OTGFS_SOFINTR - Enable SOF interrupts. Why would you ever + * CONFIG_STM32_OTGFS_SOFINTR - Enable SOF interrupts. Why would you ever * want to do that? - * CONFIG_STM32L4_USBHOST_REGDEBUG - Enable very low-level register access + * CONFIG_STM32_USBHOST_REGDEBUG - Enable very low-level register access * debug. Depends on CONFIG_DEBUG. - * CONFIG_STM32L4_USBHOST_PKTDUMP - Dump all incoming and outgoing USB + * CONFIG_STM32_USBHOST_PKTDUMP - Dump all incoming and outgoing USB * packets. Depends on CONFIG_DEBUG. */ /* Pre-requisites (partial) */ -#ifndef CONFIG_STM32L4_SYSCFG -# error "CONFIG_STM32L4_SYSCFG is required" +#ifndef CONFIG_STM32_SYSCFG +# error "CONFIG_STM32_SYSCFG is required" #endif /* Default RxFIFO size */ -#ifndef CONFIG_STM32L4_OTGFS_RXFIFO_SIZE -# define CONFIG_STM32L4_OTGFS_RXFIFO_SIZE 128 +#ifndef CONFIG_STM32_OTGFS_RXFIFO_SIZE +# define CONFIG_STM32_OTGFS_RXFIFO_SIZE 128 #endif /* Default host non-periodic Tx FIFO size */ -#ifndef CONFIG_STM32L4_OTGFS_NPTXFIFO_SIZE -# define CONFIG_STM32L4_OTGFS_NPTXFIFO_SIZE 96 +#ifndef CONFIG_STM32_OTGFS_NPTXFIFO_SIZE +# define CONFIG_STM32_OTGFS_NPTXFIFO_SIZE 96 #endif /* Default host periodic Tx fifo size register */ -#ifndef CONFIG_STM32L4_OTGFS_PTXFIFO_SIZE -# define CONFIG_STM32L4_OTGFS_PTXFIFO_SIZE 96 +#ifndef CONFIG_STM32_OTGFS_PTXFIFO_SIZE +# define CONFIG_STM32_OTGFS_PTXFIFO_SIZE 96 #endif /* Maximum size of a descriptor */ -#ifndef CONFIG_STM32L4_OTGFS_DESCSIZE -# define CONFIG_STM32L4_OTGFS_DESCSIZE 128 +#ifndef CONFIG_STM32_OTGFS_DESCSIZE +# define CONFIG_STM32_OTGFS_DESCSIZE 128 #endif /* Register/packet debug depends on CONFIG_DEBUG */ #ifndef CONFIG_DEBUG -# undef CONFIG_STM32L4_USBHOST_REGDEBUG -# undef CONFIG_STM32L4_USBHOST_PKTDUMP +# undef CONFIG_STM32_USBHOST_REGDEBUG +# undef CONFIG_STM32_USBHOST_PKTDUMP #endif /* HCD Setup ****************************************************************/ /* Hardware capabilities */ -#define STM32L4_NHOST_CHANNELS 8 /* Number of host channels */ -#define STM32L4_MAX_PACKET_SIZE 64 /* Full speed max packet size */ -#define STM32L4_EP0_DEF_PACKET_SIZE 8 /* EP0 default packet size */ -#define STM32L4_EP0_MAX_PACKET_SIZE 64 /* EP0 FS max packet size */ -#define STM32L4_MAX_TX_FIFOS 15 /* Max number of TX FIFOs */ -#define STM32L4_MAX_PKTCOUNT 256 /* Max packet count */ -#define STM32L4_RETRY_COUNT 3 /* Number of ctrl transfer retries */ +#define STM32_NHOST_CHANNELS 8 /* Number of host channels */ +#define STM32_MAX_PACKET_SIZE 64 /* Full speed max packet size */ +#define STM32_EP0_DEF_PACKET_SIZE 8 /* EP0 default packet size */ +#define STM32_EP0_MAX_PACKET_SIZE 64 /* EP0 FS max packet size */ +#define STM32_MAX_TX_FIFOS 15 /* Max number of TX FIFOs */ +#define STM32_MAX_PKTCOUNT 256 /* Max packet count */ +#define STM32_RETRY_COUNT 3 /* Number of ctrl transfer retries */ /* Delays *******************************************************************/ -#define STM32L4_READY_DELAY 200000 /* In loop counts */ -#define STM32L4_FLUSH_DELAY 200000 /* In loop counts */ -#define STM32L4_SETUP_DELAY SEC2TICK(5) /* 5 seconds in system ticks */ -#define STM32L4_DATANAK_DELAY SEC2TICK(5) /* 5 seconds in system ticks */ +#define STM32_READY_DELAY 200000 /* In loop counts */ +#define STM32_FLUSH_DELAY 200000 /* In loop counts */ +#define STM32_SETUP_DELAY SEC2TICK(5) /* 5 seconds in system ticks */ +#define STM32_DATANAK_DELAY SEC2TICK(5) /* 5 seconds in system ticks */ /**************************************************************************** * Private Types @@ -154,7 +154,7 @@ * state machine (for debug purposes only) */ -enum stm32l4_smstate_e +enum stm32_smstate_e { SMSTATE_DETACHED = 0, /* Not attached to a device */ SMSTATE_ATTACHED, /* Attached to a device */ @@ -164,7 +164,7 @@ enum stm32l4_smstate_e /* This enumeration provides the reason for the channel halt. */ -enum stm32l4_chreason_e +enum stm32_chreason_e { CHREASON_IDLE = 0, /* Inactive (initial state) */ CHREASON_FREED, /* Channel is no longer in use */ @@ -180,15 +180,15 @@ enum stm32l4_chreason_e /* This structure retains the state of one host channel. NOTE: Since there * is only one channel operation active at a time, some of the fields in - * in the structure could be moved in struct stm32l4_ubhost_s to achieve + * in the structure could be moved in struct stm32_ubhost_s to achieve * some memory savings. */ -struct stm32l4_chan_s +struct stm32_chan_s { sem_t waitsem; /* Channel wait semaphore */ volatile uint8_t result; /* The result of the transfer */ - volatile uint8_t chreason; /* Channel halt reason. See enum stm32l4_chreason_e */ + volatile uint8_t chreason; /* Channel halt reason. See enum stm32_chreason_e */ uint8_t chidx; /* Channel index */ uint8_t epno; /* Device endpoint number (0-127) */ uint8_t eptype; /* See OTGFS_EPTYPE_* definitions */ @@ -218,7 +218,7 @@ struct stm32l4_chan_s * the endpoint. */ -struct stm32l4_ctrlinfo_s +struct stm32_ctrlinfo_s { uint8_t inndx; /* EP0 IN control channel index */ uint8_t outndx; /* EP0 OUT control channel index */ @@ -226,7 +226,7 @@ struct stm32l4_ctrlinfo_s /* This structure retains the state of the USB host controller */ -struct stm32l4_usbhost_s +struct stm32_usbhost_s { /* Common device fields. This must be the first thing defined in the * structure so that it is possible to simply cast from struct usbhost_s @@ -248,7 +248,7 @@ struct stm32l4_usbhost_s volatile bool pscwait; /* True: Thread is waiting for a port event */ mutex_t lock; /* Support mutually exclusive access */ sem_t pscsem; /* Semaphore to wait for a port event */ - struct stm32l4_ctrlinfo_s ep0; /* Root hub port EP0 description */ + struct stm32_ctrlinfo_s ep0; /* Root hub port EP0 description */ #ifdef CONFIG_USBHOST_HUB /* Used to pass external hub port events */ @@ -260,7 +260,7 @@ struct stm32l4_usbhost_s /* The state of each host channel */ - struct stm32l4_chan_s chan[STM32L4_MAX_TX_FIFOS]; + struct stm32_chan_s chan[STM32_MAX_TX_FIFOS]; }; /**************************************************************************** @@ -269,97 +269,97 @@ struct stm32l4_usbhost_s /* Register operations ******************************************************/ -#ifdef CONFIG_STM32L4_USBHOST_REGDEBUG -static void stm32l4_printreg(uint32_t addr, uint32_t val, bool iswrite); -static void stm32l4_checkreg(uint32_t addr, uint32_t val, bool iswrite); -static uint32_t stm32l4_getreg(uint32_t addr); -static void stm32l4_putreg(uint32_t addr, uint32_t value); +#ifdef CONFIG_STM32_USBHOST_REGDEBUG +static void stm32_printreg(uint32_t addr, uint32_t val, bool iswrite); +static void stm32_checkreg(uint32_t addr, uint32_t val, bool iswrite); +static uint32_t stm32_getreg(uint32_t addr); +static void stm32_putreg(uint32_t addr, uint32_t value); #else -# define stm32l4_getreg(addr) getreg32(addr) -# define stm32l4_putreg(addr,val) putreg32(val,addr) +# define stm32_getreg(addr) getreg32(addr) +# define stm32_putreg(addr,val) putreg32(val,addr) #endif -static inline void stm32l4_modifyreg(uint32_t addr, uint32_t clrbits, +static inline void stm32_modifyreg(uint32_t addr, uint32_t clrbits, uint32_t setbits); -#ifdef CONFIG_STM32L4_USBHOST_PKTDUMP -# define stm32l4_pktdump(m,b,n) lib_dumpbuffer(m,b,n) +#ifdef CONFIG_STM32_USBHOST_PKTDUMP +# define stm32_pktdump(m,b,n) lib_dumpbuffer(m,b,n) #else -# define stm32l4_pktdump(m,b,n) +# define stm32_pktdump(m,b,n) #endif /* Byte stream access helper functions **************************************/ -static inline uint16_t stm32l4_getle16(const uint8_t *val); +static inline uint16_t stm32_getle16(const uint8_t *val); /* Channel management *******************************************************/ -static int stm32l4_chan_alloc(struct stm32l4_usbhost_s *priv); -static inline void stm32l4_chan_free(struct stm32l4_usbhost_s *priv, +static int stm32_chan_alloc(struct stm32_usbhost_s *priv); +static inline void stm32_chan_free(struct stm32_usbhost_s *priv, int chidx); -static inline void stm32l4_chan_freeall(struct stm32l4_usbhost_s *priv); -static void stm32l4_chan_configure(struct stm32l4_usbhost_s *priv, +static inline void stm32_chan_freeall(struct stm32_usbhost_s *priv); +static void stm32_chan_configure(struct stm32_usbhost_s *priv, int chidx); -static void stm32l4_chan_halt(struct stm32l4_usbhost_s *priv, - int chidx, enum stm32l4_chreason_e chreason); -static int stm32l4_chan_waitsetup(struct stm32l4_usbhost_s *priv, - struct stm32l4_chan_s *chan); +static void stm32_chan_halt(struct stm32_usbhost_s *priv, + int chidx, enum stm32_chreason_e chreason); +static int stm32_chan_waitsetup(struct stm32_usbhost_s *priv, + struct stm32_chan_s *chan); #ifdef CONFIG_USBHOST_ASYNCH -static int stm32l4_chan_asynchsetup(struct stm32l4_usbhost_s *priv, - struct stm32l4_chan_s *chan, +static int stm32_chan_asynchsetup(struct stm32_usbhost_s *priv, + struct stm32_chan_s *chan, usbhost_asynch_t callback, void *arg); #endif -static int stm32l4_chan_wait(struct stm32l4_usbhost_s *priv, - struct stm32l4_chan_s *chan); -static void stm32l4_chan_wakeup(struct stm32l4_usbhost_s *priv, - struct stm32l4_chan_s *chan); -static int stm32l4_ctrlchan_alloc(struct stm32l4_usbhost_s *priv, +static int stm32_chan_wait(struct stm32_usbhost_s *priv, + struct stm32_chan_s *chan); +static void stm32_chan_wakeup(struct stm32_usbhost_s *priv, + struct stm32_chan_s *chan); +static int stm32_ctrlchan_alloc(struct stm32_usbhost_s *priv, uint8_t epno, uint8_t funcaddr, uint8_t speed, - struct stm32l4_ctrlinfo_s *ctrlep); -static int stm32l4_ctrlep_alloc(struct stm32l4_usbhost_s *priv, + struct stm32_ctrlinfo_s *ctrlep); +static int stm32_ctrlep_alloc(struct stm32_usbhost_s *priv, const struct usbhost_epdesc_s *epdesc, usbhost_ep_t *ep); -static int stm32l4_xfrep_alloc(struct stm32l4_usbhost_s *priv, +static int stm32_xfrep_alloc(struct stm32_usbhost_s *priv, const struct usbhost_epdesc_s *epdesc, usbhost_ep_t *ep); /* Control/data transfer logic **********************************************/ -static void stm32l4_transfer_start(struct stm32l4_usbhost_s *priv, +static void stm32_transfer_start(struct stm32_usbhost_s *priv, int chidx); #if 0 /* Not used */ -static inline uint16_t stm32l4_getframe(void); +static inline uint16_t stm32_getframe(void); #endif -static int stm32l4_ctrl_sendsetup(struct stm32l4_usbhost_s *priv, - struct stm32l4_ctrlinfo_s *ep0, +static int stm32_ctrl_sendsetup(struct stm32_usbhost_s *priv, + struct stm32_ctrlinfo_s *ep0, const struct usb_ctrlreq_s *req); -static int stm32l4_ctrl_senddata(struct stm32l4_usbhost_s *priv, - struct stm32l4_ctrlinfo_s *ep0, +static int stm32_ctrl_senddata(struct stm32_usbhost_s *priv, + struct stm32_ctrlinfo_s *ep0, uint8_t *buffer, unsigned int buflen); -static int stm32l4_ctrl_recvdata(struct stm32l4_usbhost_s *priv, - struct stm32l4_ctrlinfo_s *ep0, +static int stm32_ctrl_recvdata(struct stm32_usbhost_s *priv, + struct stm32_ctrlinfo_s *ep0, uint8_t *buffer, unsigned int buflen); -static int stm32l4_in_setup(struct stm32l4_usbhost_s *priv, int chidx); -static ssize_t stm32l4_in_transfer(struct stm32l4_usbhost_s *priv, +static int stm32_in_setup(struct stm32_usbhost_s *priv, int chidx); +static ssize_t stm32_in_transfer(struct stm32_usbhost_s *priv, int chidx, uint8_t *buffer, size_t buflen); #ifdef CONFIG_USBHOST_ASYNCH -static void stm32l4_in_next(struct stm32l4_usbhost_s *priv, - struct stm32l4_chan_s *chan); -static int stm32l4_in_asynch(struct stm32l4_usbhost_s *priv, int chidx, +static void stm32_in_next(struct stm32_usbhost_s *priv, + struct stm32_chan_s *chan); +static int stm32_in_asynch(struct stm32_usbhost_s *priv, int chidx, uint8_t *buffer, size_t buflen, usbhost_asynch_t callback, void *arg); #endif -static int stm32l4_out_setup(struct stm32l4_usbhost_s *priv, int chidx); -static ssize_t stm32l4_out_transfer(struct stm32l4_usbhost_s *priv, +static int stm32_out_setup(struct stm32_usbhost_s *priv, int chidx); +static ssize_t stm32_out_transfer(struct stm32_usbhost_s *priv, int chidx, uint8_t *buffer, size_t buflen); #ifdef CONFIG_USBHOST_ASYNCH -static void stm32l4_out_next(struct stm32l4_usbhost_s *priv, - struct stm32l4_chan_s *chan); -static int stm32l4_out_asynch(struct stm32l4_usbhost_s *priv, int chidx, +static void stm32_out_next(struct stm32_usbhost_s *priv, + struct stm32_chan_s *chan); +static int stm32_out_asynch(struct stm32_usbhost_s *priv, int chidx, uint8_t *buffer, size_t buflen, usbhost_asynch_t callback, void *arg); #endif @@ -368,106 +368,106 @@ static int stm32l4_out_asynch(struct stm32l4_usbhost_s *priv, int chidx, /* Lower level interrupt handlers */ -static void stm32l4_gint_wrpacket(struct stm32l4_usbhost_s *priv, +static void stm32_gint_wrpacket(struct stm32_usbhost_s *priv, uint8_t *buffer, int chidx, int buflen); -static inline void stm32l4_gint_hcinisr(struct stm32l4_usbhost_s *priv, +static inline void stm32_gint_hcinisr(struct stm32_usbhost_s *priv, int chidx); -static inline void stm32l4_gint_hcoutisr(struct stm32l4_usbhost_s *priv, +static inline void stm32_gint_hcoutisr(struct stm32_usbhost_s *priv, int chidx); -static void stm32l4_gint_connected(struct stm32l4_usbhost_s *priv); -static void stm32l4_gint_disconnected(struct stm32l4_usbhost_s *priv); +static void stm32_gint_connected(struct stm32_usbhost_s *priv); +static void stm32_gint_disconnected(struct stm32_usbhost_s *priv); /* Second level interrupt handlers */ -#ifdef CONFIG_STM32L4_OTGFS_SOFINTR -static inline void stm32l4_gint_sofisr(struct stm32l4_usbhost_s *priv); +#ifdef CONFIG_STM32_OTGFS_SOFINTR +static inline void stm32_gint_sofisr(struct stm32_usbhost_s *priv); #endif static inline void -stm32l4_gint_rxflvlisr(struct stm32l4_usbhost_s *priv); +stm32_gint_rxflvlisr(struct stm32_usbhost_s *priv); static inline void -stm32l4_gint_nptxfeisr(struct stm32l4_usbhost_s *priv); -static inline void stm32l4_gint_ptxfeisr(struct stm32l4_usbhost_s *priv); -static inline void stm32l4_gint_hcisr(struct stm32l4_usbhost_s *priv); -static inline void stm32l4_gint_hprtisr(struct stm32l4_usbhost_s *priv); -static inline void stm32l4_gint_discisr(struct stm32l4_usbhost_s *priv); -static inline void stm32l4_gint_ipxfrisr(struct stm32l4_usbhost_s *priv); +stm32_gint_nptxfeisr(struct stm32_usbhost_s *priv); +static inline void stm32_gint_ptxfeisr(struct stm32_usbhost_s *priv); +static inline void stm32_gint_hcisr(struct stm32_usbhost_s *priv); +static inline void stm32_gint_hprtisr(struct stm32_usbhost_s *priv); +static inline void stm32_gint_discisr(struct stm32_usbhost_s *priv); +static inline void stm32_gint_ipxfrisr(struct stm32_usbhost_s *priv); /* First level, global interrupt handler */ -static int stm32l4_gint_isr(int irq, void *context, void *arg); +static int stm32_gint_isr(int irq, void *context, void *arg); /* Interrupt controls */ -static void stm32l4_gint_enable(void); -static void stm32l4_gint_disable(void); -static inline void stm32l4_hostinit_enable(void); -static void stm32l4_txfe_enable(struct stm32l4_usbhost_s *priv, +static void stm32_gint_enable(void); +static void stm32_gint_disable(void); +static inline void stm32_hostinit_enable(void); +static void stm32_txfe_enable(struct stm32_usbhost_s *priv, int chidx); /* USB host controller operations *******************************************/ -static int stm32l4_wait(struct usbhost_connection_s *conn, +static int stm32_wait(struct usbhost_connection_s *conn, struct usbhost_hubport_s **hport); -static int stm32l4_rh_enumerate(struct stm32l4_usbhost_s *priv, +static int stm32_rh_enumerate(struct stm32_usbhost_s *priv, struct usbhost_connection_s *conn, struct usbhost_hubport_s *hport); -static int stm32l4_enumerate(struct usbhost_connection_s *conn, +static int stm32_enumerate(struct usbhost_connection_s *conn, struct usbhost_hubport_s *hport); -static int stm32l4_ep0configure(struct usbhost_driver_s *drvr, +static int stm32_ep0configure(struct usbhost_driver_s *drvr, usbhost_ep_t ep0, uint8_t funcaddr, uint8_t speed, uint16_t maxpacketsize); -static int stm32l4_epalloc(struct usbhost_driver_s *drvr, +static int stm32_epalloc(struct usbhost_driver_s *drvr, const struct usbhost_epdesc_s *epdesc, usbhost_ep_t *ep); -static int stm32l4_epfree(struct usbhost_driver_s *drvr, +static int stm32_epfree(struct usbhost_driver_s *drvr, usbhost_ep_t ep); -static int stm32l4_alloc(struct usbhost_driver_s *drvr, +static int stm32_alloc(struct usbhost_driver_s *drvr, uint8_t **buffer, size_t *maxlen); -static int stm32l4_free(struct usbhost_driver_s *drvr, +static int stm32_free(struct usbhost_driver_s *drvr, uint8_t *buffer); -static int stm32l4_ioalloc(struct usbhost_driver_s *drvr, +static int stm32_ioalloc(struct usbhost_driver_s *drvr, uint8_t **buffer, size_t buflen); -static int stm32l4_iofree(struct usbhost_driver_s *drvr, +static int stm32_iofree(struct usbhost_driver_s *drvr, uint8_t *buffer); -static int stm32l4_ctrlin(struct usbhost_driver_s *drvr, +static int stm32_ctrlin(struct usbhost_driver_s *drvr, usbhost_ep_t ep0, const struct usb_ctrlreq_s *req, uint8_t *buffer); -static int stm32l4_ctrlout(struct usbhost_driver_s *drvr, +static int stm32_ctrlout(struct usbhost_driver_s *drvr, usbhost_ep_t ep0, const struct usb_ctrlreq_s *req, const uint8_t *buffer); -static ssize_t stm32l4_transfer(struct usbhost_driver_s *drvr, +static ssize_t stm32_transfer(struct usbhost_driver_s *drvr, usbhost_ep_t ep, uint8_t *buffer, size_t buflen); #ifdef CONFIG_USBHOST_ASYNCH -static int stm32l4_asynch(struct usbhost_driver_s *drvr, usbhost_ep_t ep, +static int stm32_asynch(struct usbhost_driver_s *drvr, usbhost_ep_t ep, uint8_t *buffer, size_t buflen, usbhost_asynch_t callback, void *arg); #endif -static int stm32l4_cancel(struct usbhost_driver_s *drvr, +static int stm32_cancel(struct usbhost_driver_s *drvr, usbhost_ep_t ep); #ifdef CONFIG_USBHOST_HUB -static int stm32l4_connect(struct usbhost_driver_s *drvr, +static int stm32_connect(struct usbhost_driver_s *drvr, struct usbhost_hubport_s *hport, bool connected); #endif -static void stm32l4_disconnect(struct usbhost_driver_s *drvr, +static void stm32_disconnect(struct usbhost_driver_s *drvr, struct usbhost_hubport_s *hport); /* Initialization ***********************************************************/ -static void stm32l4_portreset(struct stm32l4_usbhost_s *priv); -static void stm32l4_flush_txfifos(uint32_t txfnum); -static void stm32l4_flush_rxfifo(void); -static void stm32l4_vbusdrive(struct stm32l4_usbhost_s *priv, +static void stm32_portreset(struct stm32_usbhost_s *priv); +static void stm32_flush_txfifos(uint32_t txfnum); +static void stm32_flush_rxfifo(void); +static void stm32_vbusdrive(struct stm32_usbhost_s *priv, bool state); -static void stm32l4_host_initialize(struct stm32l4_usbhost_s *priv); +static void stm32_host_initialize(struct stm32_usbhost_s *priv); -static inline void stm32l4_sw_initialize(struct stm32l4_usbhost_s *priv); -static inline int stm32l4_hw_initialize(struct stm32l4_usbhost_s *priv); +static inline void stm32_sw_initialize(struct stm32_usbhost_s *priv); +static inline int stm32_hw_initialize(struct stm32_usbhost_s *priv); /**************************************************************************** * Private Data @@ -478,7 +478,7 @@ static inline int stm32l4_hw_initialize(struct stm32l4_usbhost_s *priv); * single global instance. */ -static struct stm32l4_usbhost_s g_usbhost = +static struct stm32_usbhost_s g_usbhost = { .lock = NXMUTEX_INITIALIZER, .pscsem = SEM_INITIALIZER(0), @@ -488,8 +488,8 @@ static struct stm32l4_usbhost_s g_usbhost = static struct usbhost_connection_s g_usbconn = { - .wait = stm32l4_wait, - .enumerate = stm32l4_enumerate, + .wait = stm32_wait, + .enumerate = stm32_enumerate, }; /**************************************************************************** @@ -497,30 +497,30 @@ static struct usbhost_connection_s g_usbconn = ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_printreg + * Name: stm32_printreg * * Description: * Print the contents of an STM32xx register operation * ****************************************************************************/ -#ifdef CONFIG_STM32L4_USBHOST_REGDEBUG -static void stm32l4_printreg(uint32_t addr, uint32_t val, bool iswrite) +#ifdef CONFIG_STM32_USBHOST_REGDEBUG +static void stm32_printreg(uint32_t addr, uint32_t val, bool iswrite) { lldbg("%08" PRIx32 "%s%08" PRIx32 "\n", addr, iswrite ? "<-" : "->", val); } #endif /**************************************************************************** - * Name: stm32l4_checkreg + * Name: stm32_checkreg * * Description: * Get the contents of an STM32 register * ****************************************************************************/ -#ifdef CONFIG_STM32L4_USBHOST_REGDEBUG -static void stm32l4_checkreg(uint32_t addr, uint32_t val, bool iswrite) +#ifdef CONFIG_STM32_USBHOST_REGDEBUG +static void stm32_checkreg(uint32_t addr, uint32_t val, bool iswrite) { static uint32_t prevaddr = 0; static uint32_t preval = 0; @@ -551,7 +551,7 @@ static void stm32l4_checkreg(uint32_t addr, uint32_t val, bool iswrite) { /* Yes.. Just one */ - stm32l4_printreg(prevaddr, preval, prevwrite); + stm32_printreg(prevaddr, preval, prevwrite); } else { @@ -570,21 +570,21 @@ static void stm32l4_checkreg(uint32_t addr, uint32_t val, bool iswrite) /* Show the new regisgter access */ - stm32l4_printreg(addr, val, iswrite); + stm32_printreg(addr, val, iswrite); } } #endif /**************************************************************************** - * Name: stm32l4_getreg + * Name: stm32_getreg * * Description: * Get the contents of an STM32 register * ****************************************************************************/ -#ifdef CONFIG_STM32L4_USBHOST_REGDEBUG -static uint32_t stm32l4_getreg(uint32_t addr) +#ifdef CONFIG_STM32_USBHOST_REGDEBUG +static uint32_t stm32_getreg(uint32_t addr) { /* Read the value from the register */ @@ -592,25 +592,25 @@ static uint32_t stm32l4_getreg(uint32_t addr) /* Check if we need to print this value */ - stm32l4_checkreg(addr, val, false); + stm32_checkreg(addr, val, false); return val; } #endif /**************************************************************************** - * Name: stm32l4_putreg + * Name: stm32_putreg * * Description: * Set the contents of an STM32 register to a value * ****************************************************************************/ -#ifdef CONFIG_STM32L4_USBHOST_REGDEBUG -static void stm32l4_putreg(uint32_t addr, uint32_t val) +#ifdef CONFIG_STM32_USBHOST_REGDEBUG +static void stm32_putreg(uint32_t addr, uint32_t val) { /* Check if we need to print this value */ - stm32l4_checkreg(addr, val, true); + stm32_checkreg(addr, val, true); /* Write the value */ @@ -619,47 +619,47 @@ static void stm32l4_putreg(uint32_t addr, uint32_t val) #endif /**************************************************************************** - * Name: stm32l4_modifyreg + * Name: stm32_modifyreg * * Description: * Modify selected bits of an STM32 register. * ****************************************************************************/ -static inline void stm32l4_modifyreg(uint32_t addr, uint32_t clrbits, +static inline void stm32_modifyreg(uint32_t addr, uint32_t clrbits, uint32_t setbits) { - stm32l4_putreg(addr, (((stm32l4_getreg(addr)) & ~clrbits) | setbits)); + stm32_putreg(addr, (((stm32_getreg(addr)) & ~clrbits) | setbits)); } /**************************************************************************** - * Name: stm32l4_getle16 + * Name: stm32_getle16 * * Description: * Get a (possibly unaligned) 16-bit little endian value. * ****************************************************************************/ -static inline uint16_t stm32l4_getle16(const uint8_t *val) +static inline uint16_t stm32_getle16(const uint8_t *val) { return (uint16_t)val[1] << 8 | (uint16_t)val[0]; } /**************************************************************************** - * Name: stm32l4_chan_alloc + * Name: stm32_chan_alloc * * Description: * Allocate a channel. * ****************************************************************************/ -static int stm32l4_chan_alloc(struct stm32l4_usbhost_s *priv) +static int stm32_chan_alloc(struct stm32_usbhost_s *priv) { int chidx; /* Search the table of channels */ - for (chidx = 0; chidx < STM32L4_NHOST_CHANNELS; chidx++) + for (chidx = 0; chidx < STM32_NHOST_CHANNELS; chidx++) { /* Is this channel available? */ @@ -678,20 +678,20 @@ static int stm32l4_chan_alloc(struct stm32l4_usbhost_s *priv) } /**************************************************************************** - * Name: stm32l4_chan_free + * Name: stm32_chan_free * * Description: * Free a previoiusly allocated channel. * ****************************************************************************/ -static void stm32l4_chan_free(struct stm32l4_usbhost_s *priv, int chidx) +static void stm32_chan_free(struct stm32_usbhost_s *priv, int chidx) { - DEBUGASSERT((unsigned)chidx < STM32L4_NHOST_CHANNELS); + DEBUGASSERT((unsigned)chidx < STM32_NHOST_CHANNELS); /* Halt the channel */ - stm32l4_chan_halt(priv, chidx, CHREASON_FREED); + stm32_chan_halt(priv, chidx, CHREASON_FREED); /* Mark the channel available */ @@ -699,27 +699,27 @@ static void stm32l4_chan_free(struct stm32l4_usbhost_s *priv, int chidx) } /**************************************************************************** - * Name: stm32l4_chan_freeall + * Name: stm32_chan_freeall * * Description: * Free all channels. * ****************************************************************************/ -static inline void stm32l4_chan_freeall(struct stm32l4_usbhost_s *priv) +static inline void stm32_chan_freeall(struct stm32_usbhost_s *priv) { uint8_t chidx; /* Free all host channels */ - for (chidx = 2; chidx < STM32L4_NHOST_CHANNELS; chidx++) + for (chidx = 2; chidx < STM32_NHOST_CHANNELS; chidx++) { - stm32l4_chan_free(priv, chidx); + stm32_chan_free(priv, chidx); } } /**************************************************************************** - * Name: stm32l4_chan_configure + * Name: stm32_chan_configure * * Description: * Configure or re-configure a host channel. Host channels are configured @@ -728,15 +728,15 @@ static inline void stm32l4_chan_freeall(struct stm32l4_usbhost_s *priv) * ****************************************************************************/ -static void stm32l4_chan_configure(struct stm32l4_usbhost_s *priv, +static void stm32_chan_configure(struct stm32_usbhost_s *priv, int chidx) { - struct stm32l4_chan_s *chan = &priv->chan[chidx]; + struct stm32_chan_s *chan = &priv->chan[chidx]; uint32_t regval; /* Clear any old pending interrupts for this host channel. */ - stm32l4_putreg(STM32L4_OTGFS_HCINT(chidx), 0xffffffff); + stm32_putreg(STM32_OTGFS_HCINT(chidx), 0xffffffff); /* Enable channel interrupts required for transfers on this channel. */ @@ -836,15 +836,15 @@ static void stm32l4_chan_configure(struct stm32l4_usbhost_s *priv, break; } - stm32l4_putreg(STM32L4_OTGFS_HCINTMSK(chidx), regval); + stm32_putreg(STM32_OTGFS_HCINTMSK(chidx), regval); /* Enable the top level host channel interrupt. */ - stm32l4_modifyreg(STM32L4_OTGFS_HAINTMSK, 0, OTGFS_HAINT(chidx)); + stm32_modifyreg(STM32_OTGFS_HAINTMSK, 0, OTGFS_HAINT(chidx)); /* Make sure host channel interrupts are enabled. */ - stm32l4_modifyreg(STM32L4_OTGFS_GINTMSK, 0, OTGFS_GINT_HC); + stm32_modifyreg(STM32_OTGFS_GINTMSK, 0, OTGFS_GINT_HC); /* Program the HCCHAR register */ @@ -876,11 +876,11 @@ static void stm32l4_chan_configure(struct stm32l4_usbhost_s *priv, /* Write the channel configuration */ - stm32l4_putreg(STM32L4_OTGFS_HCCHAR(chidx), regval); + stm32_putreg(STM32_OTGFS_HCCHAR(chidx), regval); } /**************************************************************************** - * Name: stm32l4_chan_halt + * Name: stm32_chan_halt * * Description: * Halt the channel associated with 'chidx' by setting the CHannel DISable @@ -888,8 +888,8 @@ static void stm32l4_chan_configure(struct stm32l4_usbhost_s *priv, * ****************************************************************************/ -static void stm32l4_chan_halt(struct stm32l4_usbhost_s *priv, int chidx, - enum stm32l4_chreason_e chreason) +static void stm32_chan_halt(struct stm32_usbhost_s *priv, int chidx, + enum stm32_chreason_e chreason) { uint32_t hcchar; uint32_t intmsk; @@ -913,7 +913,7 @@ static void stm32l4_chan_halt(struct stm32l4_usbhost_s *priv, int chidx, * transaction that has already been started on the USB." */ - hcchar = stm32l4_getreg(STM32L4_OTGFS_HCCHAR(chidx)); + hcchar = stm32_getreg(STM32_OTGFS_HCCHAR(chidx)); hcchar |= (OTGFS_HCCHAR_CHDIS | OTGFS_HCCHAR_CHENA); /* Get the endpoint type from the HCCHAR register */ @@ -935,14 +935,14 @@ static void stm32l4_chan_halt(struct stm32l4_usbhost_s *priv, int chidx, { /* Get the number of words available in the non-periodic Tx FIFO. */ - avail = stm32l4_getreg(STM32L4_OTGFS_HNPTXSTS) & + avail = stm32_getreg(STM32_OTGFS_HNPTXSTS) & OTGFS_HNPTXSTS_NPTXFSAV_MASK; } else { /* Get the number of words available in the non-periodic Tx FIFO. */ - avail = stm32l4_getreg(STM32L4_OTGFS_HPTXSTS) & + avail = stm32_getreg(STM32_OTGFS_HPTXSTS) & OTGFS_HPTXSTS_PTXFSAVL_MASK; } @@ -957,17 +957,17 @@ static void stm32l4_chan_halt(struct stm32l4_usbhost_s *priv, int chidx, /* Unmask the CHannel Halted (CHH) interrupt */ - intmsk = stm32l4_getreg(STM32L4_OTGFS_HCINTMSK(chidx)); + intmsk = stm32_getreg(STM32_OTGFS_HCINTMSK(chidx)); intmsk |= OTGFS_HCINT_CHH; - stm32l4_putreg(STM32L4_OTGFS_HCINTMSK(chidx), intmsk); + stm32_putreg(STM32_OTGFS_HCINTMSK(chidx), intmsk); /* Halt the channel by setting CHDIS (and maybe CHENA) in the HCCHAR */ - stm32l4_putreg(STM32L4_OTGFS_HCCHAR(chidx), hcchar); + stm32_putreg(STM32_OTGFS_HCCHAR(chidx), hcchar); } /**************************************************************************** - * Name: stm32l4_chan_waitsetup + * Name: stm32_chan_waitsetup * * Description: * Set the request for the transfer complete event well BEFORE enabling @@ -982,8 +982,8 @@ static void stm32l4_chan_halt(struct stm32l4_usbhost_s *priv, int chidx, * ****************************************************************************/ -static int stm32l4_chan_waitsetup(struct stm32l4_usbhost_s *priv, - struct stm32l4_chan_s *chan) +static int stm32_chan_waitsetup(struct stm32_usbhost_s *priv, + struct stm32_chan_s *chan) { irqstate_t flags = enter_critical_section(); int ret = -ENODEV; @@ -1010,7 +1010,7 @@ static int stm32l4_chan_waitsetup(struct stm32l4_usbhost_s *priv, } /**************************************************************************** - * Name: stm32l4_chan_asynchsetup + * Name: stm32_chan_asynchsetup * * Description: * Set the request for the transfer complete event well BEFORE enabling @@ -1025,8 +1025,8 @@ static int stm32l4_chan_waitsetup(struct stm32l4_usbhost_s *priv, ****************************************************************************/ #ifdef CONFIG_USBHOST_ASYNCH -static int stm32l4_chan_asynchsetup(struct stm32l4_usbhost_s *priv, - struct stm32l4_chan_s *chan, +static int stm32_chan_asynchsetup(struct stm32_usbhost_s *priv, + struct stm32_chan_s *chan, usbhost_asynch_t callback, void *arg) { irqstate_t flags = enter_critical_section(); @@ -1053,7 +1053,7 @@ static int stm32l4_chan_asynchsetup(struct stm32l4_usbhost_s *priv, #endif /**************************************************************************** - * Name: stm32l4_chan_wait + * Name: stm32_chan_wait * * Description: * Wait for a transfer on a channel to complete. @@ -1063,8 +1063,8 @@ static int stm32l4_chan_asynchsetup(struct stm32l4_usbhost_s *priv, * ****************************************************************************/ -static int stm32l4_chan_wait(struct stm32l4_usbhost_s *priv, - struct stm32l4_chan_s *chan) +static int stm32_chan_wait(struct stm32_usbhost_s *priv, + struct stm32_chan_s *chan) { irqstate_t flags; int ret; @@ -1102,7 +1102,7 @@ static int stm32l4_chan_wait(struct stm32l4_usbhost_s *priv, } /**************************************************************************** - * Name: stm32l4_chan_wakeup + * Name: stm32_chan_wakeup * * Description: * A channel transfer has completed... wakeup any threads waiting for the @@ -1114,8 +1114,8 @@ static int stm32l4_chan_wait(struct stm32l4_usbhost_s *priv, * ****************************************************************************/ -static void stm32l4_chan_wakeup(struct stm32l4_usbhost_s *priv, - struct stm32l4_chan_s *chan) +static void stm32_chan_wakeup(struct stm32_usbhost_s *priv, + struct stm32_chan_s *chan) { /* Is the transfer complete? */ @@ -1151,11 +1151,11 @@ static void stm32l4_chan_wakeup(struct stm32l4_usbhost_s *priv, if (chan->in) { - stm32l4_in_next(priv, chan); + stm32_in_next(priv, chan); } else { - stm32l4_out_next(priv, chan); + stm32_out_next(priv, chan); } } #endif @@ -1163,23 +1163,23 @@ static void stm32l4_chan_wakeup(struct stm32l4_usbhost_s *priv, } /**************************************************************************** - * Name: stm32l4_ctrlchan_alloc + * Name: stm32_ctrlchan_alloc * * Description: * Allocate and configured channels for a control pipe. * ****************************************************************************/ -static int stm32l4_ctrlchan_alloc(struct stm32l4_usbhost_s *priv, +static int stm32_ctrlchan_alloc(struct stm32_usbhost_s *priv, uint8_t epno, uint8_t funcaddr, uint8_t speed, - struct stm32l4_ctrlinfo_s *ctrlep) + struct stm32_ctrlinfo_s *ctrlep) { - struct stm32l4_chan_s *chan; + struct stm32_chan_s *chan; int inndx; int outndx; - outndx = stm32l4_chan_alloc(priv); + outndx = stm32_chan_alloc(priv); if (outndx < 0) { return -ENOMEM; @@ -1193,20 +1193,20 @@ static int stm32l4_ctrlchan_alloc(struct stm32l4_usbhost_s *priv, chan->funcaddr = funcaddr; chan->speed = speed; chan->interval = 0; - chan->maxpacket = STM32L4_EP0_DEF_PACKET_SIZE; + chan->maxpacket = STM32_EP0_DEF_PACKET_SIZE; chan->indata1 = false; chan->outdata1 = false; /* Configure control OUT channels */ - stm32l4_chan_configure(priv, outndx); + stm32_chan_configure(priv, outndx); /* Allocate and initialize the control IN channel */ - inndx = stm32l4_chan_alloc(priv); + inndx = stm32_chan_alloc(priv); if (inndx < 0) { - stm32l4_chan_free(priv, outndx); + stm32_chan_free(priv, outndx); return -ENOMEM; } @@ -1218,18 +1218,18 @@ static int stm32l4_ctrlchan_alloc(struct stm32l4_usbhost_s *priv, chan->funcaddr = funcaddr; chan->speed = speed; chan->interval = 0; - chan->maxpacket = STM32L4_EP0_DEF_PACKET_SIZE; + chan->maxpacket = STM32_EP0_DEF_PACKET_SIZE; chan->indata1 = false; chan->outdata1 = false; /* Configure control IN channels */ - stm32l4_chan_configure(priv, inndx); + stm32_chan_configure(priv, inndx); return OK; } /**************************************************************************** - * Name: stm32l4_ctrlep_alloc + * Name: stm32_ctrlep_alloc * * Description: * Allocate a container and channels for control pipe. @@ -1249,12 +1249,12 @@ static int stm32l4_ctrlchan_alloc(struct stm32l4_usbhost_s *priv, * ****************************************************************************/ -static int stm32l4_ctrlep_alloc(struct stm32l4_usbhost_s *priv, +static int stm32_ctrlep_alloc(struct stm32_usbhost_s *priv, const struct usbhost_epdesc_s *epdesc, usbhost_ep_t *ep) { struct usbhost_hubport_s *hport; - struct stm32l4_ctrlinfo_s *ctrlep; + struct stm32_ctrlinfo_s *ctrlep; int ret; /* Sanity check. NOTE that this method should only be called if a device @@ -1266,8 +1266,8 @@ static int stm32l4_ctrlep_alloc(struct stm32l4_usbhost_s *priv, /* Allocate a container for the control endpoint */ - ctrlep = (struct stm32l4_ctrlinfo_s *) - kmm_malloc(sizeof(struct stm32l4_ctrlinfo_s)); + ctrlep = (struct stm32_ctrlinfo_s *) + kmm_malloc(sizeof(struct stm32_ctrlinfo_s)); if (ctrlep == NULL) { uerr("ERROR: Failed to allocate control endpoint container\n"); @@ -1276,11 +1276,11 @@ static int stm32l4_ctrlep_alloc(struct stm32l4_usbhost_s *priv, /* Then allocate and configure the IN/OUT channels */ - ret = stm32l4_ctrlchan_alloc(priv, epdesc->addr & USB_EPNO_MASK, + ret = stm32_ctrlchan_alloc(priv, epdesc->addr & USB_EPNO_MASK, hport->funcaddr, hport->speed, ctrlep); if (ret < 0) { - uerr("ERROR: stm32l4_ctrlchan_alloc failed: %d\n", ret); + uerr("ERROR: stm32_ctrlchan_alloc failed: %d\n", ret); kmm_free(ctrlep); return ret; } @@ -1292,7 +1292,7 @@ static int stm32l4_ctrlep_alloc(struct stm32l4_usbhost_s *priv, } /**************************************************************************** - * Name: stm32l4_xfrep_alloc + * Name: stm32_xfrep_alloc * * Description: * Allocate and configure one unidirectional endpoint. @@ -1312,12 +1312,12 @@ static int stm32l4_ctrlep_alloc(struct stm32l4_usbhost_s *priv, * ****************************************************************************/ -static int stm32l4_xfrep_alloc(struct stm32l4_usbhost_s *priv, +static int stm32_xfrep_alloc(struct stm32_usbhost_s *priv, const struct usbhost_epdesc_s *epdesc, usbhost_ep_t *ep) { struct usbhost_hubport_s *hport; - struct stm32l4_chan_s *chan; + struct stm32_chan_s *chan; int chidx; /* Sanity check. NOTE that this method should only be called if a device @@ -1329,7 +1329,7 @@ static int stm32l4_xfrep_alloc(struct stm32l4_usbhost_s *priv, /* Allocate a host channel for the endpoint */ - chidx = stm32l4_chan_alloc(priv); + chidx = stm32_chan_alloc(priv); if (chidx < 0) { uerr("ERROR: Failed to allocate a host channel\n"); @@ -1355,7 +1355,7 @@ static int stm32l4_xfrep_alloc(struct stm32l4_usbhost_s *priv, /* Then configure the endpoint */ - stm32l4_chan_configure(priv, chidx); + stm32_chan_configure(priv, chidx); /* Return the index to the allocated channel as the endpoint "handle" */ @@ -1364,17 +1364,17 @@ static int stm32l4_xfrep_alloc(struct stm32l4_usbhost_s *priv, } /**************************************************************************** - * Name: stm32l4_transfer_start + * Name: stm32_transfer_start * * Description: * Start at transfer on the select IN or OUT channel. * ****************************************************************************/ -static void stm32l4_transfer_start(struct stm32l4_usbhost_s *priv, +static void stm32_transfer_start(struct stm32_usbhost_s *priv, int chidx) { - struct stm32l4_chan_s *chan; + struct stm32_chan_s *chan; uint32_t regval; unsigned int npackets; unsigned int maxpacket; @@ -1413,10 +1413,10 @@ static void stm32l4_transfer_start(struct stm32l4_usbhost_s *priv, * packets that can be transferred (this should not happen). */ - if (npackets > STM32L4_MAX_PKTCOUNT) + if (npackets > STM32_MAX_PKTCOUNT) { - npackets = STM32L4_MAX_PKTCOUNT; - chan->buflen = STM32L4_MAX_PKTCOUNT * maxpacket; + npackets = STM32_MAX_PKTCOUNT; + chan->buflen = STM32_MAX_PKTCOUNT * maxpacket; usbhost_trace2(OTGFS_TRACE2_CLIP, chidx, chan->buflen); } } @@ -1453,18 +1453,18 @@ static void stm32l4_transfer_start(struct stm32l4_usbhost_s *priv, regval = ((uint32_t)chan->buflen << OTGFS_HCTSIZ_XFRSIZ_SHIFT) | ((uint32_t)npackets << OTGFS_HCTSIZ_PKTCNT_SHIFT) | ((uint32_t)chan->pid << OTGFS_HCTSIZ_DPID_SHIFT); - stm32l4_putreg(STM32L4_OTGFS_HCTSIZ(chidx), regval); + stm32_putreg(STM32_OTGFS_HCTSIZ(chidx), regval); /* Setup the HCCHAR register: Frame oddness and host channel enable */ - regval = stm32l4_getreg(STM32L4_OTGFS_HCCHAR(chidx)); + regval = stm32_getreg(STM32_OTGFS_HCCHAR(chidx)); /* Set/clear the Odd Frame bit. Check for an even frame; if so set Odd * Frame. This field is applicable for only periodic (isochronous and * interrupt) channels. */ - if ((stm32l4_getreg(STM32L4_OTGFS_HFNUM) & 1) == 0) + if ((stm32_getreg(STM32_OTGFS_HFNUM) & 1) == 0) { regval |= OTGFS_HCCHAR_ODDFRM; } @@ -1475,7 +1475,7 @@ static void stm32l4_transfer_start(struct stm32l4_usbhost_s *priv, regval &= ~OTGFS_HCCHAR_CHDIS; regval |= OTGFS_HCCHAR_CHENA; - stm32l4_putreg(STM32L4_OTGFS_HCCHAR(chidx), regval); + stm32_putreg(STM32_OTGFS_HCCHAR(chidx), regval); /* If this is an out transfer, then we need to do more.. we need to copy * the outgoing data into the correct TxFIFO. @@ -1496,7 +1496,7 @@ static void stm32l4_transfer_start(struct stm32l4_usbhost_s *priv, { /* Read the Non-periodic Tx FIFO status register */ - regval = stm32l4_getreg(STM32L4_OTGFS_HNPTXSTS); + regval = stm32_getreg(STM32_OTGFS_HNPTXSTS); avail = ((regval & OTGFS_HNPTXSTS_NPTXFSAV_MASK) >> OTGFS_HNPTXSTS_NPTXFSAV_SHIFT) << 2; } @@ -1509,7 +1509,7 @@ static void stm32l4_transfer_start(struct stm32l4_usbhost_s *priv, { /* Read the Non-periodic Tx FIFO status register */ - regval = stm32l4_getreg(STM32L4_OTGFS_HPTXSTS); + regval = stm32_getreg(STM32_OTGFS_HPTXSTS); avail = ((regval & OTGFS_HPTXSTS_PTXFSAVL_MASK) >> OTGFS_HPTXSTS_PTXFSAVL_SHIFT) << 2; } @@ -1541,7 +1541,7 @@ static void stm32l4_transfer_start(struct stm32l4_usbhost_s *priv, /* Write packet into the Tx FIFO. */ - stm32l4_gint_wrpacket(priv, chan->buffer, chidx, wrsize); + stm32_gint_wrpacket(priv, chan->buffer, chidx, wrsize); } /* Did we put the entire buffer into the Tx FIFO? */ @@ -1553,13 +1553,13 @@ static void stm32l4_transfer_start(struct stm32l4_usbhost_s *priv, * FIFO becomes empty. */ - stm32l4_txfe_enable(priv, chidx); + stm32_txfe_enable(priv, chidx); } } } /**************************************************************************** - * Name: stm32l4_getframe + * Name: stm32_getframe * * Description: * Get the current frame number. The frame number (FRNUM) field increments @@ -1569,26 +1569,26 @@ static void stm32l4_transfer_start(struct stm32l4_usbhost_s *priv, ****************************************************************************/ #if 0 /* Not used */ -static inline uint16_t stm32l4_getframe(void) +static inline uint16_t stm32_getframe(void) { return (uint16_t) - (stm32l4_getreg(STM32L4_OTGFS_HFNUM) & OTGFS_HFNUM_FRNUM_MASK); + (stm32_getreg(STM32_OTGFS_HFNUM) & OTGFS_HFNUM_FRNUM_MASK); } #endif /**************************************************************************** - * Name: stm32l4_ctrl_sendsetup + * Name: stm32_ctrl_sendsetup * * Description: * Send an IN/OUT SETUP packet. * ****************************************************************************/ -static int stm32l4_ctrl_sendsetup(struct stm32l4_usbhost_s *priv, - struct stm32l4_ctrlinfo_s *ep0, +static int stm32_ctrl_sendsetup(struct stm32_usbhost_s *priv, + struct stm32_ctrlinfo_s *ep0, const struct usb_ctrlreq_s *req) { - struct stm32l4_chan_s *chan; + struct stm32_chan_s *chan; clock_t start; clock_t elapsed; int ret; @@ -1609,7 +1609,7 @@ static int stm32l4_ctrl_sendsetup(struct stm32l4_usbhost_s *priv, /* Set up for the wait BEFORE starting the transfer */ - ret = stm32l4_chan_waitsetup(priv, chan); + ret = stm32_chan_waitsetup(priv, chan); if (ret < 0) { usbhost_trace1(OTGFS_TRACE1_DEVDISCONN, 0); @@ -1618,11 +1618,11 @@ static int stm32l4_ctrl_sendsetup(struct stm32l4_usbhost_s *priv, /* Start the transfer */ - stm32l4_transfer_start(priv, ep0->outndx); + stm32_transfer_start(priv, ep0->outndx); /* Wait for the transfer to complete */ - ret = stm32l4_chan_wait(priv, chan); + ret = stm32_chan_wait(priv, chan); /* Return on success and for all failures other than EAGAIN. EAGAIN * means that the device NAKed the SETUP command and that we should @@ -1647,13 +1647,13 @@ static int stm32l4_ctrl_sendsetup(struct stm32l4_usbhost_s *priv, elapsed = clock_systime_ticks() - start; } - while (elapsed < STM32L4_SETUP_DELAY); + while (elapsed < STM32_SETUP_DELAY); return -ETIMEDOUT; } /**************************************************************************** - * Name: stm32l4_ctrl_senddata + * Name: stm32_ctrl_senddata * * Description: * Send data in the data phase of an OUT control transfer. Or send status @@ -1661,11 +1661,11 @@ static int stm32l4_ctrl_sendsetup(struct stm32l4_usbhost_s *priv, * ****************************************************************************/ -static int stm32l4_ctrl_senddata(struct stm32l4_usbhost_s *priv, - struct stm32l4_ctrlinfo_s *ep0, +static int stm32_ctrl_senddata(struct stm32_usbhost_s *priv, + struct stm32_ctrlinfo_s *ep0, uint8_t *buffer, unsigned int buflen) { - struct stm32l4_chan_s *chan = &priv->chan[ep0->outndx]; + struct stm32_chan_s *chan = &priv->chan[ep0->outndx]; int ret; /* Save buffer information */ @@ -1689,7 +1689,7 @@ static int stm32l4_ctrl_senddata(struct stm32l4_usbhost_s *priv, /* Set up for the wait BEFORE starting the transfer */ - ret = stm32l4_chan_waitsetup(priv, chan); + ret = stm32_chan_waitsetup(priv, chan); if (ret < 0) { usbhost_trace1(OTGFS_TRACE1_DEVDISCONN, 0); @@ -1698,15 +1698,15 @@ static int stm32l4_ctrl_senddata(struct stm32l4_usbhost_s *priv, /* Start the transfer */ - stm32l4_transfer_start(priv, ep0->outndx); + stm32_transfer_start(priv, ep0->outndx); /* Wait for the transfer to complete and return the result */ - return stm32l4_chan_wait(priv, chan); + return stm32_chan_wait(priv, chan); } /**************************************************************************** - * Name: stm32l4_ctrl_recvdata + * Name: stm32_ctrl_recvdata * * Description: * Receive data in the data phase of an IN control transfer. Or receive @@ -1714,11 +1714,11 @@ static int stm32l4_ctrl_senddata(struct stm32l4_usbhost_s *priv, * ****************************************************************************/ -static int stm32l4_ctrl_recvdata(struct stm32l4_usbhost_s *priv, - struct stm32l4_ctrlinfo_s *ep0, +static int stm32_ctrl_recvdata(struct stm32_usbhost_s *priv, + struct stm32_ctrlinfo_s *ep0, uint8_t *buffer, unsigned int buflen) { - struct stm32l4_chan_s *chan = &priv->chan[ep0->inndx]; + struct stm32_chan_s *chan = &priv->chan[ep0->inndx]; int ret; /* Save buffer information */ @@ -1730,7 +1730,7 @@ static int stm32l4_ctrl_recvdata(struct stm32l4_usbhost_s *priv, /* Set up for the wait BEFORE starting the transfer */ - ret = stm32l4_chan_waitsetup(priv, chan); + ret = stm32_chan_waitsetup(priv, chan); if (ret < 0) { usbhost_trace1(OTGFS_TRACE1_DEVDISCONN, 0); @@ -1739,24 +1739,24 @@ static int stm32l4_ctrl_recvdata(struct stm32l4_usbhost_s *priv, /* Start the transfer */ - stm32l4_transfer_start(priv, ep0->inndx); + stm32_transfer_start(priv, ep0->inndx); /* Wait for the transfer to complete and return the result */ - return stm32l4_chan_wait(priv, chan); + return stm32_chan_wait(priv, chan); } /**************************************************************************** - * Name: stm32l4_in_setup + * Name: stm32_in_setup * * Description: * Initiate an IN transfer on an bulk, interrupt, or isochronous pipe. * ****************************************************************************/ -static int stm32l4_in_setup(struct stm32l4_usbhost_s *priv, int chidx) +static int stm32_in_setup(struct stm32_usbhost_s *priv, int chidx) { - struct stm32l4_chan_s *chan; + struct stm32_chan_s *chan; /* Set up for the transfer based on the direction and the endpoint type */ @@ -1803,23 +1803,23 @@ static int stm32l4_in_setup(struct stm32l4_usbhost_s *priv, int chidx) /* Start the transfer */ - stm32l4_transfer_start(priv, chidx); + stm32_transfer_start(priv, chidx); return OK; } /**************************************************************************** - * Name: stm32l4_in_transfer + * Name: stm32_in_transfer * * Description: * Transfer 'buflen' bytes into 'buffer' from an IN channel. * ****************************************************************************/ -static ssize_t stm32l4_in_transfer(struct stm32l4_usbhost_s *priv, +static ssize_t stm32_in_transfer(struct stm32_usbhost_s *priv, int chidx, uint8_t *buffer, size_t buflen) { - struct stm32l4_chan_s *chan; + struct stm32_chan_s *chan; clock_t start; ssize_t xfrd; int ret; @@ -1840,7 +1840,7 @@ static ssize_t stm32l4_in_transfer(struct stm32l4_usbhost_s *priv, { /* Set up for the wait BEFORE starting the transfer */ - ret = stm32l4_chan_waitsetup(priv, chan); + ret = stm32_chan_waitsetup(priv, chan); if (ret < 0) { usbhost_trace1(OTGFS_TRACE1_DEVDISCONN, 0); @@ -1849,16 +1849,16 @@ static ssize_t stm32l4_in_transfer(struct stm32l4_usbhost_s *priv, /* Set up for the transfer based on the direction and the endpoint */ - ret = stm32l4_in_setup(priv, chidx); + ret = stm32_in_setup(priv, chidx); if (ret < 0) { - uerr("ERROR: stm32l4_in_setup failed: %d\n", ret); + uerr("ERROR: stm32_in_setup failed: %d\n", ret); return (ssize_t)ret; } /* Wait for the transfer to complete and get the result */ - ret = stm32l4_chan_wait(priv, chan); + ret = stm32_chan_wait(priv, chan); /* EAGAIN indicates that the device NAKed the transfer. */ @@ -1893,7 +1893,7 @@ static ssize_t stm32l4_in_transfer(struct stm32l4_usbhost_s *priv, */ clock_t elapsed = clock_systime_ticks() - start; - if (elapsed >= STM32L4_DATANAK_DELAY) + if (elapsed >= STM32_DATANAK_DELAY) { /* Timeout out... break out returning the NAK as * as a failure. @@ -1973,7 +1973,7 @@ static ssize_t stm32l4_in_transfer(struct stm32l4_usbhost_s *priv, /* Break out and return the error */ - uerr("ERROR: stm32l4_chan_wait failed: %d\n", ret); + uerr("ERROR: stm32_chan_wait failed: %d\n", ret); return (ssize_t)ret; } } @@ -1993,7 +1993,7 @@ static ssize_t stm32l4_in_transfer(struct stm32l4_usbhost_s *priv, } /**************************************************************************** - * Name: stm32l4_in_next + * Name: stm32_in_next * * Description: * Initiate the next of a sequence of asynchronous transfers. @@ -2004,8 +2004,8 @@ static ssize_t stm32l4_in_transfer(struct stm32l4_usbhost_s *priv, ****************************************************************************/ #ifdef CONFIG_USBHOST_ASYNCH -static void stm32l4_in_next(struct stm32l4_usbhost_s *priv, - struct stm32l4_chan_s *chan) +static void stm32_in_next(struct stm32_usbhost_s *priv, + struct stm32_chan_s *chan) { usbhost_asynch_t callback; void *arg; @@ -2022,13 +2022,13 @@ static void stm32l4_in_next(struct stm32l4_usbhost_s *priv, * endpoint type */ - ret = stm32l4_in_setup(priv, chan->chidx); + ret = stm32_in_setup(priv, chan->chidx); if (ret >= 0) { return; } - uerr("ERROR: stm32l4_in_setup failed: %d\n", ret); + uerr("ERROR: stm32_in_setup failed: %d\n", ret); result = ret; } @@ -2058,7 +2058,7 @@ static void stm32l4_in_next(struct stm32l4_usbhost_s *priv, #endif /**************************************************************************** - * Name: stm32l4_in_asynch + * Name: stm32_in_asynch * * Description: * Initiate the first of a sequence of asynchronous transfers. @@ -2069,11 +2069,11 @@ static void stm32l4_in_next(struct stm32l4_usbhost_s *priv, ****************************************************************************/ #ifdef CONFIG_USBHOST_ASYNCH -static int stm32l4_in_asynch(struct stm32l4_usbhost_s *priv, int chidx, +static int stm32_in_asynch(struct stm32_usbhost_s *priv, int chidx, uint8_t *buffer, size_t buflen, usbhost_asynch_t callback, void *arg) { - struct stm32l4_chan_s *chan; + struct stm32_chan_s *chan; int ret; /* Set up for the transfer BEFORE starting the first transfer */ @@ -2083,19 +2083,19 @@ static int stm32l4_in_asynch(struct stm32l4_usbhost_s *priv, int chidx, chan->buflen = buflen; chan->xfrd = 0; - ret = stm32l4_chan_asynchsetup(priv, chan, callback, arg); + ret = stm32_chan_asynchsetup(priv, chan, callback, arg); if (ret < 0) { - uerr("ERROR: stm32l4_chan_asynchsetup failed: %d\n", ret); + uerr("ERROR: stm32_chan_asynchsetup failed: %d\n", ret); return ret; } /* Set up for the transfer based on the direction and the endpoint type */ - ret = stm32l4_in_setup(priv, chidx); + ret = stm32_in_setup(priv, chidx); if (ret < 0) { - uerr("ERROR: stm32l4_in_setup failed: %d\n", ret); + uerr("ERROR: stm32_in_setup failed: %d\n", ret); } /* And return with the transfer pending */ @@ -2105,16 +2105,16 @@ static int stm32l4_in_asynch(struct stm32l4_usbhost_s *priv, int chidx, #endif /**************************************************************************** - * Name: stm32l4_out_setup + * Name: stm32_out_setup * * Description: * Initiate an OUT transfer on an bulk, interrupt, or isochronous pipe. * ****************************************************************************/ -static int stm32l4_out_setup(struct stm32l4_usbhost_s *priv, int chidx) +static int stm32_out_setup(struct stm32_usbhost_s *priv, int chidx) { - struct stm32l4_chan_s *chan; + struct stm32_chan_s *chan; /* Set up for the transfer based on the direction and the endpoint type */ @@ -2165,23 +2165,23 @@ static int stm32l4_out_setup(struct stm32l4_usbhost_s *priv, int chidx) /* Start the transfer */ - stm32l4_transfer_start(priv, chidx); + stm32_transfer_start(priv, chidx); return OK; } /**************************************************************************** - * Name: stm32l4_out_transfer + * Name: stm32_out_transfer * * Description: * Transfer the 'buflen' bytes in 'buffer' through an OUT channel. * ****************************************************************************/ -static ssize_t stm32l4_out_transfer(struct stm32l4_usbhost_s *priv, +static ssize_t stm32_out_transfer(struct stm32_usbhost_s *priv, int chidx, uint8_t *buffer, size_t buflen) { - struct stm32l4_chan_s *chan; + struct stm32_chan_s *chan; clock_t start; clock_t elapsed; size_t xfrlen; @@ -2212,7 +2212,7 @@ static ssize_t stm32l4_out_transfer(struct stm32l4_usbhost_s *priv, /* Set up for the wait BEFORE starting the transfer */ - ret = stm32l4_chan_waitsetup(priv, chan); + ret = stm32_chan_waitsetup(priv, chan); if (ret < 0) { usbhost_trace1(OTGFS_TRACE1_DEVDISCONN, 0); @@ -2221,16 +2221,16 @@ static ssize_t stm32l4_out_transfer(struct stm32l4_usbhost_s *priv, /* Set up for the transfer based on the direction and the endpoint */ - ret = stm32l4_out_setup(priv, chidx); + ret = stm32_out_setup(priv, chidx); if (ret < 0) { - uerr("ERROR: stm32l4_out_setup failed: %d\n", ret); + uerr("ERROR: stm32_out_setup failed: %d\n", ret); return (ssize_t)ret; } /* Wait for the transfer to complete and get the result */ - ret = stm32l4_chan_wait(priv, chan); + ret = stm32_chan_wait(priv, chan); /* Handle transfer failures */ @@ -2247,13 +2247,13 @@ static ssize_t stm32l4_out_transfer(struct stm32l4_usbhost_s *priv, elapsed = clock_systime_ticks() - start; if (ret != -EAGAIN || /* Not a NAK condition OR */ - elapsed >= STM32L4_DATANAK_DELAY || /* Timeout has elapsed OR */ + elapsed >= STM32_DATANAK_DELAY || /* Timeout has elapsed OR */ chan->xfrd > 0) /* Data has been partially * transferred */ { /* Break out and return the error */ - uerr("ERROR: stm32l4_chan_wait failed: %d\n", ret); + uerr("ERROR: stm32_chan_wait failed: %d\n", ret); return (ssize_t)ret; } @@ -2261,7 +2261,7 @@ static ssize_t stm32l4_out_transfer(struct stm32l4_usbhost_s *priv, * the data in the FIFO when the NAK occurs? Does it discard it? */ - stm32l4_flush_txfifos(OTGFS_GRSTCTL_TXFNUM_HALL); + stm32_flush_txfifos(OTGFS_GRSTCTL_TXFNUM_HALL); /* Get the device a little time to catch up. Then retry the * transfer using the same buffer pointer and length. @@ -2284,7 +2284,7 @@ static ssize_t stm32l4_out_transfer(struct stm32l4_usbhost_s *priv, } /**************************************************************************** - * Name: stm32l4_out_next + * Name: stm32_out_next * * Description: * Initiate the next of a sequence of asynchronous transfers. @@ -2295,8 +2295,8 @@ static ssize_t stm32l4_out_transfer(struct stm32l4_usbhost_s *priv, ****************************************************************************/ #ifdef CONFIG_USBHOST_ASYNCH -static void stm32l4_out_next(struct stm32l4_usbhost_s *priv, - struct stm32l4_chan_s *chan) +static void stm32_out_next(struct stm32_usbhost_s *priv, + struct stm32_chan_s *chan) { usbhost_asynch_t callback; void *arg; @@ -2313,13 +2313,13 @@ static void stm32l4_out_next(struct stm32l4_usbhost_s *priv, * endpoint type */ - ret = stm32l4_out_setup(priv, chan->chidx); + ret = stm32_out_setup(priv, chan->chidx); if (ret >= 0) { return; } - uerr("ERROR: stm32l4_out_setup failed: %d\n", ret); + uerr("ERROR: stm32_out_setup failed: %d\n", ret); result = ret; } @@ -2349,7 +2349,7 @@ static void stm32l4_out_next(struct stm32l4_usbhost_s *priv, #endif /**************************************************************************** - * Name: stm32l4_out_asynch + * Name: stm32_out_asynch * * Description: * Initiate the first of a sequence of asynchronous transfers. @@ -2360,11 +2360,11 @@ static void stm32l4_out_next(struct stm32l4_usbhost_s *priv, ****************************************************************************/ #ifdef CONFIG_USBHOST_ASYNCH -static int stm32l4_out_asynch(struct stm32l4_usbhost_s *priv, int chidx, +static int stm32_out_asynch(struct stm32_usbhost_s *priv, int chidx, uint8_t *buffer, size_t buflen, usbhost_asynch_t callback, void *arg) { - struct stm32l4_chan_s *chan; + struct stm32_chan_s *chan; int ret; /* Set up for the transfer BEFORE starting the first transfer */ @@ -2374,19 +2374,19 @@ static int stm32l4_out_asynch(struct stm32l4_usbhost_s *priv, int chidx, chan->buflen = buflen; chan->xfrd = 0; - ret = stm32l4_chan_asynchsetup(priv, chan, callback, arg); + ret = stm32_chan_asynchsetup(priv, chan, callback, arg); if (ret < 0) { - uerr("ERROR: stm32l4_chan_asynchsetup failed: %d\n", ret); + uerr("ERROR: stm32_chan_asynchsetup failed: %d\n", ret); return ret; } /* Set up for the transfer based on the direction and the endpoint type */ - ret = stm32l4_out_setup(priv, chidx); + ret = stm32_out_setup(priv, chidx); if (ret < 0) { - uerr("ERROR: stm32l4_out_setup failed: %d\n", ret); + uerr("ERROR: stm32_out_setup failed: %d\n", ret); } /* And return with the transfer pending */ @@ -2396,7 +2396,7 @@ static int stm32l4_out_asynch(struct stm32l4_usbhost_s *priv, int chidx, #endif /**************************************************************************** - * Name: stm32l4_gint_wrpacket + * Name: stm32_gint_wrpacket * * Description: * Transfer the 'buflen' bytes in 'buffer' to the Tx FIFO associated with @@ -2404,14 +2404,14 @@ static int stm32l4_out_asynch(struct stm32l4_usbhost_s *priv, int chidx, * ****************************************************************************/ -static void stm32l4_gint_wrpacket(struct stm32l4_usbhost_s *priv, +static void stm32_gint_wrpacket(struct stm32_usbhost_s *priv, uint8_t *buffer, int chidx, int buflen) { uint32_t *src; uint32_t fifo; int buflen32; - stm32l4_pktdump("Sending", buffer, buflen); + stm32_pktdump("Sending", buffer, buflen); /* Get the number of 32-byte words associated with this byte size */ @@ -2419,7 +2419,7 @@ static void stm32l4_gint_wrpacket(struct stm32l4_usbhost_s *priv, /* Get the address of the Tx FIFO associated with this channel */ - fifo = STM32L4_OTGFS_DFIFO_HCH(chidx); + fifo = STM32_OTGFS_DFIFO_HCH(chidx); /* Transfer all of the data into the Tx FIFO */ @@ -2427,7 +2427,7 @@ static void stm32l4_gint_wrpacket(struct stm32l4_usbhost_s *priv, for (; buflen32 > 0; buflen32--) { uint32_t data = *src++; - stm32l4_putreg(fifo, data); + stm32_putreg(fifo, data); } /* Increment the count of bytes "in-flight" in the Tx FIFO */ @@ -2436,7 +2436,7 @@ static void stm32l4_gint_wrpacket(struct stm32l4_usbhost_s *priv, } /**************************************************************************** - * Name: stm32l4_gint_hcinisr + * Name: stm32_gint_hcinisr * * Description: * USB OTG FS host IN channels interrupt handler @@ -2454,10 +2454,10 @@ static void stm32l4_gint_wrpacket(struct stm32l4_usbhost_s *priv, * ****************************************************************************/ -static inline void stm32l4_gint_hcinisr(struct stm32l4_usbhost_s *priv, +static inline void stm32_gint_hcinisr(struct stm32_usbhost_s *priv, int chidx) { - struct stm32l4_chan_s *chan = &priv->chan[chidx]; + struct stm32_chan_s *chan = &priv->chan[chidx]; uint32_t regval; uint32_t pending; @@ -2465,8 +2465,8 @@ static inline void stm32l4_gint_hcinisr(struct stm32l4_usbhost_s *priv, * HCINTMSK register to get the set of enabled HC interrupts. */ - pending = stm32l4_getreg(STM32L4_OTGFS_HCINT(chidx)); - regval = stm32l4_getreg(STM32L4_OTGFS_HCINTMSK(chidx)); + pending = stm32_getreg(STM32_OTGFS_HCINT(chidx)); + regval = stm32_getreg(STM32_OTGFS_HCINTMSK(chidx)); /* AND the two to get the set of enabled, pending HC interrupts */ @@ -2480,7 +2480,7 @@ static inline void stm32l4_gint_hcinisr(struct stm32l4_usbhost_s *priv, { /* Clear the pending the ACK response received/transmitted interrupt */ - stm32l4_putreg(STM32L4_OTGFS_HCINT(chidx), OTGFS_HCINT_ACK); + stm32_putreg(STM32_OTGFS_HCINT(chidx), OTGFS_HCINT_ACK); } /* Check for a pending STALL response receive (STALL) interrupt */ @@ -2489,14 +2489,14 @@ static inline void stm32l4_gint_hcinisr(struct stm32l4_usbhost_s *priv, { /* Clear the NAK and STALL Conditions. */ - stm32l4_putreg(STM32L4_OTGFS_HCINT(chidx), + stm32_putreg(STM32_OTGFS_HCINT(chidx), (OTGFS_HCINT_NAK | OTGFS_HCINT_STALL)); /* Halt the channel when a STALL, TXERR, BBERR or DTERR interrupt is * received on the channel. */ - stm32l4_chan_halt(priv, chidx, CHREASON_STALL); + stm32_chan_halt(priv, chidx, CHREASON_STALL); /* When there is a STALL, clear any pending NAK so that it is not * processed below. @@ -2513,11 +2513,11 @@ static inline void stm32l4_gint_hcinisr(struct stm32l4_usbhost_s *priv, * received on the channel. */ - stm32l4_chan_halt(priv, chidx, CHREASON_DTERR); + stm32_chan_halt(priv, chidx, CHREASON_DTERR); /* Clear the NAK and data toggle error conditions */ - stm32l4_putreg(STM32L4_OTGFS_HCINT(chidx), + stm32_putreg(STM32_OTGFS_HCINT(chidx), (OTGFS_HCINT_NAK | OTGFS_HCINT_DTERR)); } @@ -2527,11 +2527,11 @@ static inline void stm32l4_gint_hcinisr(struct stm32l4_usbhost_s *priv, { /* Halt the channel -- the CHH interrupt is expected next */ - stm32l4_chan_halt(priv, chidx, CHREASON_FRMOR); + stm32_chan_halt(priv, chidx, CHREASON_FRMOR); /* Clear the FRaMe OverRun (FRMOR) condition */ - stm32l4_putreg(STM32L4_OTGFS_HCINT(chidx), OTGFS_HCINT_FRMOR); + stm32_putreg(STM32_OTGFS_HCINT(chidx), OTGFS_HCINT_FRMOR); } /* Check for a pending TransFeR Completed (XFRC) interrupt */ @@ -2540,7 +2540,7 @@ static inline void stm32l4_gint_hcinisr(struct stm32l4_usbhost_s *priv, { /* Clear the TransFeR Completed (XFRC) condition */ - stm32l4_putreg(STM32L4_OTGFS_HCINT(chidx), OTGFS_HCINT_XFRC); + stm32_putreg(STM32_OTGFS_HCINT(chidx), OTGFS_HCINT_XFRC); /* Then handle the transfer completion event based on the endpoint */ @@ -2549,22 +2549,22 @@ static inline void stm32l4_gint_hcinisr(struct stm32l4_usbhost_s *priv, { /* Halt the channel -- the CHH interrupt is expected next */ - stm32l4_chan_halt(priv, chidx, CHREASON_XFRC); + stm32_chan_halt(priv, chidx, CHREASON_XFRC); /* Clear any pending NAK condition. The 'indata1' data toggle * should have been appropriately updated by the RxFIFO * logic as each packet was received. */ - stm32l4_putreg(STM32L4_OTGFS_HCINT(chidx), OTGFS_HCINT_NAK); + stm32_putreg(STM32_OTGFS_HCINT(chidx), OTGFS_HCINT_NAK); } else if (chan->eptype == OTGFS_EPTYPE_INTR) { /* Force the next transfer on an ODD frame */ - regval = stm32l4_getreg(STM32L4_OTGFS_HCCHAR(chidx)); + regval = stm32_getreg(STM32_OTGFS_HCCHAR(chidx)); regval |= OTGFS_HCCHAR_ODDFRM; - stm32l4_putreg(STM32L4_OTGFS_HCCHAR(chidx), regval); + stm32_putreg(STM32_OTGFS_HCCHAR(chidx), regval); /* Set the request done state */ @@ -2578,9 +2578,9 @@ static inline void stm32l4_gint_hcinisr(struct stm32l4_usbhost_s *priv, { /* Mask the CHannel Halted (CHH) interrupt */ - regval = stm32l4_getreg(STM32L4_OTGFS_HCINTMSK(chidx)); + regval = stm32_getreg(STM32_OTGFS_HCINTMSK(chidx)); regval &= ~OTGFS_HCINT_CHH; - stm32l4_putreg(STM32L4_OTGFS_HCINTMSK(chidx), regval); + stm32_putreg(STM32_OTGFS_HCINTMSK(chidx), regval); /* Update the request state based on the host state machine state */ @@ -2618,7 +2618,7 @@ static inline void stm32l4_gint_hcinisr(struct stm32l4_usbhost_s *priv, /* Clear the CHannel Halted (CHH) condition */ - stm32l4_putreg(STM32L4_OTGFS_HCINT(chidx), OTGFS_HCINT_CHH); + stm32_putreg(STM32_OTGFS_HCINT(chidx), OTGFS_HCINT_CHH); } /* Check for a pending Transaction ERror (TXERR) interrupt */ @@ -2629,11 +2629,11 @@ static inline void stm32l4_gint_hcinisr(struct stm32l4_usbhost_s *priv, * received on the channel. */ - stm32l4_chan_halt(priv, chidx, CHREASON_TXERR); + stm32_chan_halt(priv, chidx, CHREASON_TXERR); /* Clear the Transaction ERror (TXERR) condition */ - stm32l4_putreg(STM32L4_OTGFS_HCINT(chidx), OTGFS_HCINT_TXERR); + stm32_putreg(STM32_OTGFS_HCINT(chidx), OTGFS_HCINT_TXERR); } /* Check for a pending NAK response received (NAK) interrupt */ @@ -2654,7 +2654,7 @@ static inline void stm32l4_gint_hcinisr(struct stm32l4_usbhost_s *priv, { /* Halt the channel -- the CHH interrupt is expected next */ - stm32l4_chan_halt(priv, chidx, CHREASON_NAK); + stm32_chan_halt(priv, chidx, CHREASON_NAK); } /* Re-activate CTRL and BULK channels. @@ -2671,30 +2671,30 @@ static inline void stm32l4_gint_hcinisr(struct stm32l4_usbhost_s *priv, * TODO: set channel reason to NACK? */ - regval = stm32l4_getreg(STM32L4_OTGFS_HCCHAR(chidx)); + regval = stm32_getreg(STM32_OTGFS_HCCHAR(chidx)); regval |= OTGFS_HCCHAR_CHENA; regval &= ~OTGFS_HCCHAR_CHDIS; - stm32l4_putreg(STM32L4_OTGFS_HCCHAR(chidx), regval); + stm32_putreg(STM32_OTGFS_HCCHAR(chidx), regval); } #else /* Halt all transfers on the NAK -- CHH interrupt is expected next */ - stm32l4_chan_halt(priv, chidx, CHREASON_NAK); + stm32_chan_halt(priv, chidx, CHREASON_NAK); #endif /* Clear the NAK condition */ - stm32l4_putreg(STM32L4_OTGFS_HCINT(chidx), OTGFS_HCINT_NAK); + stm32_putreg(STM32_OTGFS_HCINT(chidx), OTGFS_HCINT_NAK); } /* Check for a transfer complete event */ - stm32l4_chan_wakeup(priv, chan); + stm32_chan_wakeup(priv, chan); } /**************************************************************************** - * Name: stm32l4_gint_hcoutisr + * Name: stm32_gint_hcoutisr * * Description: * USB OTG FS host OUT channels interrupt handler @@ -2712,10 +2712,10 @@ static inline void stm32l4_gint_hcinisr(struct stm32l4_usbhost_s *priv, * ****************************************************************************/ -static inline void stm32l4_gint_hcoutisr(struct stm32l4_usbhost_s *priv, +static inline void stm32_gint_hcoutisr(struct stm32_usbhost_s *priv, int chidx) { - struct stm32l4_chan_s *chan = &priv->chan[chidx]; + struct stm32_chan_s *chan = &priv->chan[chidx]; uint32_t regval; uint32_t pending; @@ -2723,8 +2723,8 @@ static inline void stm32l4_gint_hcoutisr(struct stm32l4_usbhost_s *priv, * HCINTMSK register to get the set of enabled HC interrupts. */ - pending = stm32l4_getreg(STM32L4_OTGFS_HCINT(chidx)); - regval = stm32l4_getreg(STM32L4_OTGFS_HCINTMSK(chidx)); + pending = stm32_getreg(STM32_OTGFS_HCINT(chidx)); + regval = stm32_getreg(STM32_OTGFS_HCINTMSK(chidx)); /* AND the two to get the set of enabled, pending HC interrupts */ @@ -2738,7 +2738,7 @@ static inline void stm32l4_gint_hcoutisr(struct stm32l4_usbhost_s *priv, { /* Clear the pending the ACK response received/transmitted interrupt */ - stm32l4_putreg(STM32L4_OTGFS_HCINT(chidx), OTGFS_HCINT_ACK); + stm32_putreg(STM32_OTGFS_HCINT(chidx), OTGFS_HCINT_ACK); } /* Check for a pending FRaMe OverRun (FRMOR) interrupt */ @@ -2747,11 +2747,11 @@ static inline void stm32l4_gint_hcoutisr(struct stm32l4_usbhost_s *priv, { /* Halt the channel (probably not necessary for FRMOR) */ - stm32l4_chan_halt(priv, chidx, CHREASON_FRMOR); + stm32_chan_halt(priv, chidx, CHREASON_FRMOR); /* Clear the pending the FRaMe OverRun (FRMOR) interrupt */ - stm32l4_putreg(STM32L4_OTGFS_HCINT(chidx), OTGFS_HCINT_FRMOR); + stm32_putreg(STM32_OTGFS_HCINT(chidx), OTGFS_HCINT_FRMOR); } /* Check for a pending TransFeR Completed (XFRC) interrupt */ @@ -2768,11 +2768,11 @@ static inline void stm32l4_gint_hcoutisr(struct stm32l4_usbhost_s *priv, /* Halt the channel -- the CHH interrupt is expected next */ - stm32l4_chan_halt(priv, chidx, CHREASON_XFRC); + stm32_chan_halt(priv, chidx, CHREASON_XFRC); /* Clear the pending the TransFeR Completed (XFRC) interrupt */ - stm32l4_putreg(STM32L4_OTGFS_HCINT(chidx), OTGFS_HCINT_XFRC); + stm32_putreg(STM32_OTGFS_HCINT(chidx), OTGFS_HCINT_XFRC); } /* Check for a pending STALL response receive (STALL) interrupt */ @@ -2781,13 +2781,13 @@ static inline void stm32l4_gint_hcoutisr(struct stm32l4_usbhost_s *priv, { /* Clear the pending STALL response receive (STALL) interrupt */ - stm32l4_putreg(STM32L4_OTGFS_HCINT(chidx), OTGFS_HCINT_STALL); + stm32_putreg(STM32_OTGFS_HCINT(chidx), OTGFS_HCINT_STALL); /* Halt the channel when a STALL, TXERR, BBERR or DTERR interrupt is * received on the channel. */ - stm32l4_chan_halt(priv, chidx, CHREASON_STALL); + stm32_chan_halt(priv, chidx, CHREASON_STALL); } /* Check for a pending NAK response received (NAK) interrupt */ @@ -2796,11 +2796,11 @@ static inline void stm32l4_gint_hcoutisr(struct stm32l4_usbhost_s *priv, { /* Halt the channel -- the CHH interrupt is expected next */ - stm32l4_chan_halt(priv, chidx, CHREASON_NAK); + stm32_chan_halt(priv, chidx, CHREASON_NAK); /* Clear the pending the NAK response received (NAK) interrupt */ - stm32l4_putreg(STM32L4_OTGFS_HCINT(chidx), OTGFS_HCINT_NAK); + stm32_putreg(STM32_OTGFS_HCINT(chidx), OTGFS_HCINT_NAK); } /* Check for a pending Transaction ERror (TXERR) interrupt */ @@ -2811,11 +2811,11 @@ static inline void stm32l4_gint_hcoutisr(struct stm32l4_usbhost_s *priv, * received on the channel. */ - stm32l4_chan_halt(priv, chidx, CHREASON_TXERR); + stm32_chan_halt(priv, chidx, CHREASON_TXERR); /* Clear the pending the Transaction ERror (TXERR) interrupt */ - stm32l4_putreg(STM32L4_OTGFS_HCINT(chidx), OTGFS_HCINT_TXERR); + stm32_putreg(STM32_OTGFS_HCINT(chidx), OTGFS_HCINT_TXERR); } /* Check for a NYET interrupt */ @@ -2825,11 +2825,11 @@ static inline void stm32l4_gint_hcoutisr(struct stm32l4_usbhost_s *priv, { /* Halt the channel */ - stm32l4_chan_halt(priv, chidx, CHREASON_NYET); + stm32_chan_halt(priv, chidx, CHREASON_NYET); /* Clear the pending the NYET interrupt */ - stm32l4_putreg(STM32L4_OTGFS_HCINT(chidx), OTGFS_HCINT_NYET); + stm32_putreg(STM32_OTGFS_HCINT(chidx), OTGFS_HCINT_NYET); } #endif @@ -2841,11 +2841,11 @@ static inline void stm32l4_gint_hcoutisr(struct stm32l4_usbhost_s *priv, * received on the channel. */ - stm32l4_chan_halt(priv, chidx, CHREASON_DTERR); + stm32_chan_halt(priv, chidx, CHREASON_DTERR); /* Clear the pending the Data Toggle ERRor (DTERR) and NAK interrupts */ - stm32l4_putreg(STM32L4_OTGFS_HCINT(chidx), + stm32_putreg(STM32_OTGFS_HCINT(chidx), (OTGFS_HCINT_DTERR | OTGFS_HCINT_NAK)); } @@ -2855,9 +2855,9 @@ static inline void stm32l4_gint_hcoutisr(struct stm32l4_usbhost_s *priv, { /* Mask the CHannel Halted (CHH) interrupt */ - regval = stm32l4_getreg(STM32L4_OTGFS_HCINTMSK(chidx)); + regval = stm32_getreg(STM32_OTGFS_HCINTMSK(chidx)); regval &= ~OTGFS_HCINT_CHH; - stm32l4_putreg(STM32L4_OTGFS_HCINTMSK(chidx), regval); + stm32_putreg(STM32_OTGFS_HCINTMSK(chidx), regval); if (chan->chreason == CHREASON_XFRC) { @@ -2869,7 +2869,7 @@ static inline void stm32l4_gint_hcoutisr(struct stm32l4_usbhost_s *priv, * the endpoint type. */ - regval = stm32l4_getreg(STM32L4_OTGFS_HCCHAR(chidx)); + regval = stm32_getreg(STM32_OTGFS_HCCHAR(chidx)); /* Is it a bulk endpoint? Were an odd number of packets * transferred? @@ -2913,23 +2913,23 @@ static inline void stm32l4_gint_hcoutisr(struct stm32l4_usbhost_s *priv, /* Clear the pending the CHannel Halted (CHH) interrupt */ - stm32l4_putreg(STM32L4_OTGFS_HCINT(chidx), OTGFS_HCINT_CHH); + stm32_putreg(STM32_OTGFS_HCINT(chidx), OTGFS_HCINT_CHH); } /* Check for a transfer complete event */ - stm32l4_chan_wakeup(priv, chan); + stm32_chan_wakeup(priv, chan); } /**************************************************************************** - * Name: stm32l4_gint_connected + * Name: stm32_gint_connected * * Description: * Handle a connection event. * ****************************************************************************/ -static void stm32l4_gint_connected(struct stm32l4_usbhost_s *priv) +static void stm32_gint_connected(struct stm32_usbhost_s *priv) { /* We we previously disconnected? */ @@ -2954,14 +2954,14 @@ static void stm32l4_gint_connected(struct stm32l4_usbhost_s *priv) } /**************************************************************************** - * Name: stm32l4_gint_disconnected + * Name: stm32_gint_disconnected * * Description: * Handle a disconnection event. * ****************************************************************************/ -static void stm32l4_gint_disconnected(struct stm32l4_usbhost_s *priv) +static void stm32_gint_disconnected(struct stm32_usbhost_s *priv) { /* Were we previously connected? */ @@ -2986,7 +2986,7 @@ static void stm32l4_gint_disconnected(struct stm32l4_usbhost_s *priv) priv->smstate = SMSTATE_DETACHED; priv->connected = false; priv->change = true; - stm32l4_chan_freeall(priv); + stm32_chan_freeall(priv); priv->rhport.hport.speed = USB_SPEED_FULL; priv->rhport.hport.funcaddr = 0; @@ -3002,15 +3002,15 @@ static void stm32l4_gint_disconnected(struct stm32l4_usbhost_s *priv) } /**************************************************************************** - * Name: stm32l4_gint_sofisr + * Name: stm32_gint_sofisr * * Description: * USB OTG FS start-of-frame interrupt handler * ****************************************************************************/ -#ifdef CONFIG_STM32L4_OTGFS_SOFINTR -static inline void stm32l4_gint_sofisr(struct stm32l4_usbhost_s *priv) +#ifdef CONFIG_STM32_OTGFS_SOFINTR +static inline void stm32_gint_sofisr(struct stm32_usbhost_s *priv) { /* Handle SOF interrupt */ @@ -3018,19 +3018,19 @@ static inline void stm32l4_gint_sofisr(struct stm32l4_usbhost_s *priv) /* Clear pending SOF interrupt */ - stm32l4_putreg(STM32L4_OTGFS_GINTSTS, OTGFS_GINT_SOF); + stm32_putreg(STM32_OTGFS_GINTSTS, OTGFS_GINT_SOF); } #endif /**************************************************************************** - * Name: stm32l4_gint_rxflvlisr + * Name: stm32_gint_rxflvlisr * * Description: * USB OTG FS RxFIFO non-empty interrupt handler * ****************************************************************************/ -static inline void stm32l4_gint_rxflvlisr(struct stm32l4_usbhost_s *priv) +static inline void stm32_gint_rxflvlisr(struct stm32_usbhost_s *priv) { uint32_t *dest; uint32_t grxsts; @@ -3045,13 +3045,13 @@ static inline void stm32l4_gint_rxflvlisr(struct stm32l4_usbhost_s *priv) /* Disable the RxFIFO non-empty interrupt */ - intmsk = stm32l4_getreg(STM32L4_OTGFS_GINTMSK); + intmsk = stm32_getreg(STM32_OTGFS_GINTMSK); intmsk &= ~OTGFS_GINT_RXFLVL; - stm32l4_putreg(STM32L4_OTGFS_GINTMSK, intmsk); + stm32_putreg(STM32_OTGFS_GINTMSK, intmsk); /* Read and pop the next status from the Rx FIFO */ - grxsts = stm32l4_getreg(STM32L4_OTGFS_GRXSTSP); + grxsts = stm32_getreg(STM32_OTGFS_GRXSTSP); uinfo("GRXSTS: %08" PRIx32 "\n", grxsts); /* Isolate the channel number/index in the status word */ @@ -3060,7 +3060,7 @@ static inline void stm32l4_gint_rxflvlisr(struct stm32l4_usbhost_s *priv) /* Get the host channel characteristics register (HCCHAR) */ - hcchar = stm32l4_getreg(STM32L4_OTGFS_HCCHAR(chidx)); + hcchar = stm32_getreg(STM32_OTGFS_HCCHAR(chidx)); /* Then process the interrupt according to the packet status */ @@ -3077,15 +3077,15 @@ static inline void stm32l4_gint_rxflvlisr(struct stm32l4_usbhost_s *priv) /* Transfer the packet from the Rx FIFO into the user buffer */ dest = (uint32_t *)priv->chan[chidx].buffer; - fifo = STM32L4_OTGFS_DFIFO_HCH(0); + fifo = STM32_OTGFS_DFIFO_HCH(0); bcnt32 = (bcnt + 3) >> 2; for (i = 0; i < bcnt32; i++) { - *dest++ = stm32l4_getreg(fifo); + *dest++ = stm32_getreg(fifo); } - stm32l4_pktdump("Received", priv->chan[chidx].buffer, bcnt); + stm32_pktdump("Received", priv->chan[chidx].buffer, bcnt); /* Toggle the IN data pid (Used by Bulk and INTR only) */ @@ -3098,14 +3098,14 @@ static inline void stm32l4_gint_rxflvlisr(struct stm32l4_usbhost_s *priv) /* Check if more packets are expected */ - hctsiz = stm32l4_getreg(STM32L4_OTGFS_HCTSIZ(chidx)); + hctsiz = stm32_getreg(STM32_OTGFS_HCTSIZ(chidx)); if ((hctsiz & OTGFS_HCTSIZ_PKTCNT_MASK) != 0) { /* Re-activate the channel when more packets are expected */ hcchar |= OTGFS_HCCHAR_CHENA; hcchar &= ~OTGFS_HCCHAR_CHDIS; - stm32l4_putreg(STM32L4_OTGFS_HCCHAR(chidx), hcchar); + stm32_putreg(STM32_OTGFS_HCCHAR(chidx), hcchar); } } } @@ -3121,20 +3121,20 @@ static inline void stm32l4_gint_rxflvlisr(struct stm32l4_usbhost_s *priv) /* Re-enable the RxFIFO non-empty interrupt */ intmsk |= OTGFS_GINT_RXFLVL; - stm32l4_putreg(STM32L4_OTGFS_GINTMSK, intmsk); + stm32_putreg(STM32_OTGFS_GINTMSK, intmsk); } /**************************************************************************** - * Name: stm32l4_gint_nptxfeisr + * Name: stm32_gint_nptxfeisr * * Description: * USB OTG FS non-periodic TxFIFO empty interrupt handler * ****************************************************************************/ -static inline void stm32l4_gint_nptxfeisr(struct stm32l4_usbhost_s *priv) +static inline void stm32_gint_nptxfeisr(struct stm32_usbhost_s *priv) { - struct stm32l4_chan_s *chan; + struct stm32_chan_s *chan; uint32_t regval; unsigned int wrsize; unsigned int avail; @@ -3164,13 +3164,13 @@ static inline void stm32l4_gint_nptxfeisr(struct stm32l4_usbhost_s *priv) { /* Disable further Tx FIFO empty interrupts and bail. */ - stm32l4_modifyreg(STM32L4_OTGFS_GINTMSK, OTGFS_GINT_NPTXFE, 0); + stm32_modifyreg(STM32_OTGFS_GINTMSK, OTGFS_GINT_NPTXFE, 0); return; } /* Read the status from the top of the non-periodic TxFIFO */ - regval = stm32l4_getreg(STM32L4_OTGFS_HNPTXSTS); + regval = stm32_getreg(STM32_OTGFS_HNPTXSTS); /* Extract the number of bytes available in the non-periodic Tx FIFO. */ @@ -3202,7 +3202,7 @@ static inline void stm32l4_gint_nptxfeisr(struct stm32l4_usbhost_s *priv) else { - stm32l4_modifyreg(STM32L4_OTGFS_GINTMSK, OTGFS_GINT_NPTXFE, 0); + stm32_modifyreg(STM32_OTGFS_GINTMSK, OTGFS_GINT_NPTXFE, 0); } /* Write the next group of packets into the Tx FIFO */ @@ -3211,20 +3211,20 @@ static inline void stm32l4_gint_nptxfeisr(struct stm32l4_usbhost_s *priv) "wrsize: %d\n", regval, chidx, avail, chan->buflen, chan->xfrd, wrsize); - stm32l4_gint_wrpacket(priv, chan->buffer, chidx, wrsize); + stm32_gint_wrpacket(priv, chan->buffer, chidx, wrsize); } /**************************************************************************** - * Name: stm32l4_gint_ptxfeisr + * Name: stm32_gint_ptxfeisr * * Description: * USB OTG FS periodic TxFIFO empty interrupt handler * ****************************************************************************/ -static inline void stm32l4_gint_ptxfeisr(struct stm32l4_usbhost_s *priv) +static inline void stm32_gint_ptxfeisr(struct stm32_usbhost_s *priv) { - struct stm32l4_chan_s *chan; + struct stm32_chan_s *chan; uint32_t regval; unsigned int wrsize; unsigned int avail; @@ -3254,13 +3254,13 @@ static inline void stm32l4_gint_ptxfeisr(struct stm32l4_usbhost_s *priv) { /* Disable further Tx FIFO empty interrupts and bail. */ - stm32l4_modifyreg(STM32L4_OTGFS_GINTMSK, OTGFS_GINT_PTXFE, 0); + stm32_modifyreg(STM32_OTGFS_GINTMSK, OTGFS_GINT_PTXFE, 0); return; } /* Read the status from the top of the periodic TxFIFO */ - regval = stm32l4_getreg(STM32L4_OTGFS_HPTXSTS); + regval = stm32_getreg(STM32_OTGFS_HPTXSTS); /* Extract the number of bytes available in the periodic Tx FIFO. */ @@ -3292,7 +3292,7 @@ static inline void stm32l4_gint_ptxfeisr(struct stm32l4_usbhost_s *priv) else { - stm32l4_modifyreg(STM32L4_OTGFS_GINTMSK, OTGFS_GINT_PTXFE, 0); + stm32_modifyreg(STM32_OTGFS_GINTMSK, OTGFS_GINT_PTXFE, 0); } /* Write the next group of packets into the Tx FIFO */ @@ -3301,30 +3301,30 @@ static inline void stm32l4_gint_ptxfeisr(struct stm32l4_usbhost_s *priv) " buflen: %d xfrd: %d wrsize: %d\n", regval, chidx, avail, chan->buflen, chan->xfrd, wrsize); - stm32l4_gint_wrpacket(priv, chan->buffer, chidx, wrsize); + stm32_gint_wrpacket(priv, chan->buffer, chidx, wrsize); } /**************************************************************************** - * Name: stm32l4_gint_hcisr + * Name: stm32_gint_hcisr * * Description: * USB OTG FS host channels interrupt handler * ****************************************************************************/ -static inline void stm32l4_gint_hcisr(struct stm32l4_usbhost_s *priv) +static inline void stm32_gint_hcisr(struct stm32_usbhost_s *priv) { uint32_t haint; uint32_t hcchar; int i = 0; /* Read the Host all channels interrupt register and test each bit in the - * register. Each bit i, i=0...(STM32L4_NHOST_CHANNELS-1), corresponds to + * register. Each bit i, i=0...(STM32_NHOST_CHANNELS-1), corresponds to * a pending interrupt on channel i. */ - haint = stm32l4_getreg(STM32L4_OTGFS_HAINT); - for (i = 0; i < STM32L4_NHOST_CHANNELS; i++) + haint = stm32_getreg(STM32_OTGFS_HAINT); + for (i = 0; i < STM32_NHOST_CHANNELS; i++) { /* Is an interrupt pending on this channel? */ @@ -3332,7 +3332,7 @@ static inline void stm32l4_gint_hcisr(struct stm32l4_usbhost_s *priv) { /* Yes... read the HCCHAR register to get the direction bit */ - hcchar = stm32l4_getreg(STM32L4_OTGFS_HCCHAR(i)); + hcchar = stm32_getreg(STM32_OTGFS_HCCHAR(i)); /* Was this an interrupt on an IN or an OUT channel? */ @@ -3340,27 +3340,27 @@ static inline void stm32l4_gint_hcisr(struct stm32l4_usbhost_s *priv) { /* Handle the HC IN channel interrupt */ - stm32l4_gint_hcinisr(priv, i); + stm32_gint_hcinisr(priv, i); } else { /* Handle the HC OUT channel interrupt */ - stm32l4_gint_hcoutisr(priv, i); + stm32_gint_hcoutisr(priv, i); } } } } /**************************************************************************** - * Name: stm32l4_gint_hprtisr + * Name: stm32_gint_hprtisr * * Description: * USB OTG FS host port interrupt handler * ****************************************************************************/ -static inline void stm32l4_gint_hprtisr(struct stm32l4_usbhost_s *priv) +static inline void stm32_gint_hprtisr(struct stm32_usbhost_s *priv) { uint32_t hprt; uint32_t newhprt; @@ -3370,7 +3370,7 @@ static inline void stm32l4_gint_hprtisr(struct stm32l4_usbhost_s *priv) /* Read the port status and control register (HPRT) */ - hprt = stm32l4_getreg(STM32L4_OTGFS_HPRT); + hprt = stm32_getreg(STM32_OTGFS_HPRT); /* Setup to clear the interrupt bits in GINTSTS by setting the * corresponding bits in the HPRT. The HCINT interrupt bit is cleared @@ -3402,8 +3402,8 @@ static inline void stm32l4_gint_hprtisr(struct stm32l4_usbhost_s *priv) usbhost_vtrace1(OTGFS_VTRACE1_GINT_HPRT_PCDET, 0); newhprt |= OTGFS_HPRT_PCDET; - stm32l4_portreset(priv); - stm32l4_gint_connected(priv); + stm32_portreset(priv); + stm32_gint_connected(priv); } /* Check for Port Enable CHaNGed (PENCHNG) */ @@ -3421,11 +3421,11 @@ static inline void stm32l4_gint_hprtisr(struct stm32l4_usbhost_s *priv) { /* Yes.. handle the new connection event */ - stm32l4_gint_connected(priv); + stm32_gint_connected(priv); /* Check the Host ConFiGuration register (HCFG) */ - hcfg = stm32l4_getreg(STM32L4_OTGFS_HCFG); + hcfg = stm32_getreg(STM32_OTGFS_HCFG); /* Is this a low speed or full speed connection (OTG FS does not * support high speed) @@ -3436,7 +3436,7 @@ static inline void stm32l4_gint_hprtisr(struct stm32l4_usbhost_s *priv) /* Set the Host Frame Interval Register for the 6KHz speed */ usbhost_vtrace1(OTGFS_VTRACE1_GINT_HPRT_LSDEV, 0); - stm32l4_putreg(STM32L4_OTGFS_HFIR, 6000); + stm32_putreg(STM32_OTGFS_HFIR, 6000); /* Are we switching from FS to LS? */ @@ -3449,17 +3449,17 @@ static inline void stm32l4_gint_hprtisr(struct stm32l4_usbhost_s *priv) hcfg &= ~OTGFS_HCFG_FSLSPCS_MASK; hcfg |= OTGFS_HCFG_FSLSPCS_LS6MHz; - stm32l4_putreg(STM32L4_OTGFS_HCFG, hcfg); + stm32_putreg(STM32_OTGFS_HCFG, hcfg); /* And reset the port */ - stm32l4_portreset(priv); + stm32_portreset(priv); } } else /* if ((hprt & OTGFS_HPRT_PSPD_MASK) == OTGFS_HPRT_PSPD_FS) */ { usbhost_vtrace1(OTGFS_VTRACE1_GINT_HPRT_FSDEV, 0); - stm32l4_putreg(STM32L4_OTGFS_HFIR, 48000); + stm32_putreg(STM32_OTGFS_HFIR, 48000); /* Are we switching from LS to FS? */ @@ -3472,11 +3472,11 @@ static inline void stm32l4_gint_hprtisr(struct stm32l4_usbhost_s *priv) hcfg &= ~OTGFS_HCFG_FSLSPCS_MASK; hcfg |= OTGFS_HCFG_FSLSPCS_FS48MHz; - stm32l4_putreg(STM32L4_OTGFS_HCFG, hcfg); + stm32_putreg(STM32_OTGFS_HCFG, hcfg); /* And reset the port */ - stm32l4_portreset(priv); + stm32_portreset(priv); } } } @@ -3484,37 +3484,37 @@ static inline void stm32l4_gint_hprtisr(struct stm32l4_usbhost_s *priv) /* Clear port interrupts by setting bits in the HPRT */ - stm32l4_putreg(STM32L4_OTGFS_HPRT, newhprt); + stm32_putreg(STM32_OTGFS_HPRT, newhprt); } /**************************************************************************** - * Name: stm32l4_gint_discisr + * Name: stm32_gint_discisr * * Description: * USB OTG FS disconnect detected interrupt handler * ****************************************************************************/ -static inline void stm32l4_gint_discisr(struct stm32l4_usbhost_s *priv) +static inline void stm32_gint_discisr(struct stm32_usbhost_s *priv) { /* Handle the disconnection event */ - stm32l4_gint_disconnected(priv); + stm32_gint_disconnected(priv); /* Clear the dicsonnect interrupt */ - stm32l4_putreg(STM32L4_OTGFS_GINTSTS, OTGFS_GINT_DISC); + stm32_putreg(STM32_OTGFS_GINTSTS, OTGFS_GINT_DISC); } /**************************************************************************** - * Name: stm32l4_gint_ipxfrisr + * Name: stm32_gint_ipxfrisr * * Description: * USB OTG FS incomplete periodic interrupt handler * ****************************************************************************/ -static inline void stm32l4_gint_ipxfrisr(struct stm32l4_usbhost_s *priv) +static inline void stm32_gint_ipxfrisr(struct stm32_usbhost_s *priv) { uint32_t regval; @@ -3522,24 +3522,24 @@ static inline void stm32l4_gint_ipxfrisr(struct stm32l4_usbhost_s *priv) * CHDIS : Set to stop transmitting/receiving data on a channel */ - regval = stm32l4_getreg(STM32L4_OTGFS_HCCHAR(0)); + regval = stm32_getreg(STM32_OTGFS_HCCHAR(0)); regval |= (OTGFS_HCCHAR_CHDIS | OTGFS_HCCHAR_CHENA); - stm32l4_putreg(STM32L4_OTGFS_HCCHAR(0), regval); + stm32_putreg(STM32_OTGFS_HCCHAR(0), regval); /* Clear the incomplete isochronous OUT interrupt */ - stm32l4_putreg(STM32L4_OTGFS_GINTSTS, OTGFS_GINT_IPXFR); + stm32_putreg(STM32_OTGFS_GINTSTS, OTGFS_GINT_IPXFR); } /**************************************************************************** - * Name: stm32l4_gint_isr + * Name: stm32_gint_isr * * Description: * USB OTG FS global interrupt handler * ****************************************************************************/ -static int stm32l4_gint_isr(int irq, void *context, void *arg) +static int stm32_gint_isr(int irq, void *context, void *arg) { /* At present, there is only support for a single OTG FS host. Hence it is * pre-allocated as g_usbhost. However, in most code, the private data @@ -3548,7 +3548,7 @@ static int stm32l4_gint_isr(int irq, void *context, void *arg) * devices. */ - struct stm32l4_usbhost_s *priv = &g_usbhost; + struct stm32_usbhost_s *priv = &g_usbhost; uint32_t pending; /* If OTG were supported, we would need to check if we are in host or @@ -3564,8 +3564,8 @@ static int stm32l4_gint_isr(int irq, void *context, void *arg) { /* Get the unmasked bits in the GINT status */ - pending = stm32l4_getreg(STM32L4_OTGFS_GINTSTS); - pending &= stm32l4_getreg(STM32L4_OTGFS_GINTMSK); + pending = stm32_getreg(STM32_OTGFS_GINTSTS); + pending &= stm32_getreg(STM32_OTGFS_GINTMSK); /* Return from the interrupt when there are no further pending * interrupts. @@ -3580,11 +3580,11 @@ static int stm32l4_gint_isr(int irq, void *context, void *arg) /* Handle the start of frame interrupt */ -#ifdef CONFIG_STM32L4_OTGFS_SOFINTR +#ifdef CONFIG_STM32_OTGFS_SOFINTR if ((pending & OTGFS_GINT_SOF) != 0) { usbhost_vtrace1(OTGFS_VTRACE1_GINT_SOF, 0); - stm32l4_gint_sofisr(priv); + stm32_gint_sofisr(priv); } #endif @@ -3593,7 +3593,7 @@ static int stm32l4_gint_isr(int irq, void *context, void *arg) if ((pending & OTGFS_GINT_RXFLVL) != 0) { usbhost_vtrace1(OTGFS_VTRACE1_GINT_RXFLVL, 0); - stm32l4_gint_rxflvlisr(priv); + stm32_gint_rxflvlisr(priv); } /* Handle the non-periodic TxFIFO empty interrupt */ @@ -3601,7 +3601,7 @@ static int stm32l4_gint_isr(int irq, void *context, void *arg) if ((pending & OTGFS_GINT_NPTXFE) != 0) { usbhost_vtrace1(OTGFS_VTRACE1_GINT_NPTXFE, 0); - stm32l4_gint_nptxfeisr(priv); + stm32_gint_nptxfeisr(priv); } /* Handle the periodic TxFIFO empty interrupt */ @@ -3609,7 +3609,7 @@ static int stm32l4_gint_isr(int irq, void *context, void *arg) if ((pending & OTGFS_GINT_PTXFE) != 0) { usbhost_vtrace1(OTGFS_VTRACE1_GINT_PTXFE, 0); - stm32l4_gint_ptxfeisr(priv); + stm32_gint_ptxfeisr(priv); } /* Handle the host channels interrupt */ @@ -3617,14 +3617,14 @@ static int stm32l4_gint_isr(int irq, void *context, void *arg) if ((pending & OTGFS_GINT_HC) != 0) { usbhost_vtrace1(OTGFS_VTRACE1_GINT_HC, 0); - stm32l4_gint_hcisr(priv); + stm32_gint_hcisr(priv); } /* Handle the host port interrupt */ if ((pending & OTGFS_GINT_HPRT) != 0) { - stm32l4_gint_hprtisr(priv); + stm32_gint_hprtisr(priv); } /* Handle the disconnect detected interrupt */ @@ -3632,7 +3632,7 @@ static int stm32l4_gint_isr(int irq, void *context, void *arg) if ((pending & OTGFS_GINT_DISC) != 0) { usbhost_vtrace1(OTGFS_VTRACE1_GINT_DISC, 0); - stm32l4_gint_discisr(priv); + stm32_gint_discisr(priv); } /* Handle the incomplete periodic transfer */ @@ -3640,7 +3640,7 @@ static int stm32l4_gint_isr(int irq, void *context, void *arg) if ((pending & OTGFS_GINT_IPXFR) != 0) { usbhost_vtrace1(OTGFS_VTRACE1_GINT_IPXFR, 0); - stm32l4_gint_ipxfrisr(priv); + stm32_gint_ipxfrisr(priv); } } @@ -3650,7 +3650,7 @@ static int stm32l4_gint_isr(int irq, void *context, void *arg) } /**************************************************************************** - * Name: stm32l4_gint_enable and stm32l4_gint_disable + * Name: stm32_gint_enable and stm32_gint_disable * * Description: * Respectively enable or disable the global OTG FS interrupt. @@ -3663,30 +3663,30 @@ static int stm32l4_gint_isr(int irq, void *context, void *arg) * ****************************************************************************/ -static void stm32l4_gint_enable(void) +static void stm32_gint_enable(void) { uint32_t regval; /* Set the GINTMSK bit to unmask the interrupt */ - regval = stm32l4_getreg(STM32L4_OTGFS_GAHBCFG); + regval = stm32_getreg(STM32_OTGFS_GAHBCFG); regval |= OTGFS_GAHBCFG_GINTMSK; - stm32l4_putreg(STM32L4_OTGFS_GAHBCFG, regval); + stm32_putreg(STM32_OTGFS_GAHBCFG, regval); } -static void stm32l4_gint_disable(void) +static void stm32_gint_disable(void) { uint32_t regval; /* Clear the GINTMSK bit to mask the interrupt */ - regval = stm32l4_getreg(STM32L4_OTGFS_GAHBCFG); + regval = stm32_getreg(STM32_OTGFS_GAHBCFG); regval &= ~OTGFS_GAHBCFG_GINTMSK; - stm32l4_putreg(STM32L4_OTGFS_GAHBCFG, regval); + stm32_putreg(STM32_OTGFS_GAHBCFG, regval); } /**************************************************************************** - * Name: stm32l4_hostinit_enable + * Name: stm32_hostinit_enable * * Description: * Enable host interrupts. @@ -3699,25 +3699,25 @@ static void stm32l4_gint_disable(void) * ****************************************************************************/ -static inline void stm32l4_hostinit_enable(void) +static inline void stm32_hostinit_enable(void) { uint32_t regval; /* Disable all interrupts. */ - stm32l4_putreg(STM32L4_OTGFS_GINTMSK, 0); + stm32_putreg(STM32_OTGFS_GINTMSK, 0); /* Clear any pending interrupts. */ - stm32l4_putreg(STM32L4_OTGFS_GINTSTS, 0xffffffff); + stm32_putreg(STM32_OTGFS_GINTSTS, 0xffffffff); /* Clear any pending USB OTG Interrupts */ - stm32l4_putreg(STM32L4_OTGFS_GOTGINT, 0xffffffff); + stm32_putreg(STM32_OTGFS_GOTGINT, 0xffffffff); /* Clear any pending USB OTG interrupts */ - stm32l4_putreg(STM32L4_OTGFS_GINTSTS, 0xbfffffff); + stm32_putreg(STM32_OTGFS_GINTSTS, 0xbfffffff); /* Enable the host interrupts */ @@ -3746,18 +3746,18 @@ static inline void stm32l4_hostinit_enable(void) * OTGFS_GINT_DISC : Disconnect detected interrupt */ -#ifdef CONFIG_STM32L4_OTGFS_SOFINTR +#ifdef CONFIG_STM32_OTGFS_SOFINTR regval |= (OTGFS_GINT_SOF | OTGFS_GINT_RXFLVL | OTGFS_GINT_IISOOXFR | OTGFS_GINT_HPRT | OTGFS_GINT_HC | OTGFS_GINT_DISC); #else regval |= (OTGFS_GINT_RXFLVL | OTGFS_GINT_IPXFR | OTGFS_GINT_HPRT | OTGFS_GINT_HC | OTGFS_GINT_DISC); #endif - stm32l4_putreg(STM32L4_OTGFS_GINTMSK, regval); + stm32_putreg(STM32_OTGFS_GINTMSK, regval); } /**************************************************************************** - * Name: stm32l4_txfe_enable + * Name: stm32_txfe_enable * * Description: * Enable Tx FIFO empty interrupts. This is necessary when the entire @@ -3778,10 +3778,10 @@ static inline void stm32l4_hostinit_enable(void) * ****************************************************************************/ -static void stm32l4_txfe_enable(struct stm32l4_usbhost_s *priv, +static void stm32_txfe_enable(struct stm32_usbhost_s *priv, int chidx) { - struct stm32l4_chan_s *chan = &priv->chan[chidx]; + struct stm32_chan_s *chan = &priv->chan[chidx]; irqstate_t flags; uint32_t regval; @@ -3793,7 +3793,7 @@ static void stm32l4_txfe_enable(struct stm32l4_usbhost_s *priv, /* Should we enable the periodic or non-peridic Tx FIFO empty interrupts */ - regval = stm32l4_getreg(STM32L4_OTGFS_GINTMSK); + regval = stm32_getreg(STM32_OTGFS_GINTMSK); switch (chan->eptype) { default: @@ -3810,7 +3810,7 @@ static void stm32l4_txfe_enable(struct stm32l4_usbhost_s *priv, /* Enable interrupts */ - stm32l4_putreg(STM32L4_OTGFS_GINTMSK, regval); + stm32_putreg(STM32_OTGFS_GINTMSK, regval); leave_critical_section(flags); } @@ -3819,7 +3819,7 @@ static void stm32l4_txfe_enable(struct stm32l4_usbhost_s *priv, ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_wait + * Name: stm32_wait * * Description: * Wait for a device to be connected or disconnected to/from a hub port. @@ -3843,10 +3843,10 @@ static void stm32l4_txfe_enable(struct stm32l4_usbhost_s *priv, * ****************************************************************************/ -static int stm32l4_wait(struct usbhost_connection_s *conn, +static int stm32_wait(struct usbhost_connection_s *conn, struct usbhost_hubport_s **hport) { - struct stm32l4_usbhost_s *priv = &g_usbhost; + struct stm32_usbhost_s *priv = &g_usbhost; struct usbhost_hubport_s *connport; irqstate_t flags; int ret; @@ -3910,7 +3910,7 @@ static int stm32l4_wait(struct usbhost_connection_s *conn, } /**************************************************************************** - * Name: stm32l4_enumerate + * Name: stm32_enumerate * * Description: * Enumerate the connected device. As part of this enumeration process, @@ -3937,7 +3937,7 @@ static int stm32l4_wait(struct usbhost_connection_s *conn, * ****************************************************************************/ -static int stm32l4_rh_enumerate(struct stm32l4_usbhost_s *priv, +static int stm32_rh_enumerate(struct stm32_usbhost_s *priv, struct usbhost_connection_s *conn, struct usbhost_hubport_s *hport) { @@ -3968,11 +3968,11 @@ static int stm32l4_rh_enumerate(struct stm32l4_usbhost_s *priv, /* Reset the host port */ - stm32l4_portreset(priv); + stm32_portreset(priv); /* Get the current device speed */ - regval = stm32l4_getreg(STM32L4_OTGFS_HPRT); + regval = stm32_getreg(STM32_OTGFS_HPRT); if ((regval & OTGFS_HPRT_PSPD_MASK) == OTGFS_HPRT_PSPD_LS) { priv->rhport.hport.speed = USB_SPEED_LOW; @@ -3984,7 +3984,7 @@ static int stm32l4_rh_enumerate(struct stm32l4_usbhost_s *priv, /* Allocate and initialize the root hub port EP0 channels */ - ret = stm32l4_ctrlchan_alloc(priv, 0, 0, priv->rhport.hport.speed, + ret = stm32_ctrlchan_alloc(priv, 0, 0, priv->rhport.hport.speed, &priv->ep0); if (ret < 0) { @@ -3994,10 +3994,10 @@ static int stm32l4_rh_enumerate(struct stm32l4_usbhost_s *priv, return ret; } -static int stm32l4_enumerate(struct usbhost_connection_s *conn, +static int stm32_enumerate(struct usbhost_connection_s *conn, struct usbhost_hubport_s *hport) { - struct stm32l4_usbhost_s *priv = &g_usbhost; + struct stm32_usbhost_s *priv = &g_usbhost; int ret; DEBUGASSERT(hport); @@ -4011,7 +4011,7 @@ static int stm32l4_enumerate(struct usbhost_connection_s *conn, if (ROOTHUB(hport)) #endif { - ret = stm32l4_rh_enumerate(priv, conn, hport); + ret = stm32_rh_enumerate(priv, conn, hport); if (ret < 0) { return ret; @@ -4035,14 +4035,14 @@ static int stm32l4_enumerate(struct usbhost_connection_s *conn, /* Return to the disconnected state */ uerr("ERROR: Enumeration failed: %d\n", ret); - stm32l4_gint_disconnected(priv); + stm32_gint_disconnected(priv); } return ret; } /**************************************************************************** - * Name: stm32l4_ep0configure + * Name: stm32_ep0configure * * Description: * Configure endpoint 0. This method is normally used internally by the @@ -4068,14 +4068,14 @@ static int stm32l4_enumerate(struct usbhost_connection_s *conn, * ****************************************************************************/ -static int stm32l4_ep0configure(struct usbhost_driver_s *drvr, +static int stm32_ep0configure(struct usbhost_driver_s *drvr, usbhost_ep_t ep0, uint8_t funcaddr, uint8_t speed, uint16_t maxpacketsize) { - struct stm32l4_usbhost_s *priv = (struct stm32l4_usbhost_s *)drvr; - struct stm32l4_ctrlinfo_s *ep0info = - (struct stm32l4_ctrlinfo_s *)ep0; - struct stm32l4_chan_s *chan; + struct stm32_usbhost_s *priv = (struct stm32_usbhost_s *)drvr; + struct stm32_ctrlinfo_s *ep0info = + (struct stm32_ctrlinfo_s *)ep0; + struct stm32_chan_s *chan; int ret; DEBUGASSERT(drvr != NULL && ep0info != NULL && funcaddr < 128 && @@ -4096,7 +4096,7 @@ static int stm32l4_ep0configure(struct usbhost_driver_s *drvr, chan->speed = speed; chan->maxpacket = maxpacketsize; - stm32l4_chan_configure(priv, ep0info->outndx); + stm32_chan_configure(priv, ep0info->outndx); /* Configure the EP0 IN channel */ @@ -4105,14 +4105,14 @@ static int stm32l4_ep0configure(struct usbhost_driver_s *drvr, chan->speed = speed; chan->maxpacket = maxpacketsize; - stm32l4_chan_configure(priv, ep0info->inndx); + stm32_chan_configure(priv, ep0info->inndx); nxmutex_unlock(&priv->lock); return OK; } /**************************************************************************** - * Name: stm32l4_epalloc + * Name: stm32_epalloc * * Description: * Allocate and configure one endpoint. @@ -4133,11 +4133,11 @@ static int stm32l4_ep0configure(struct usbhost_driver_s *drvr, * ****************************************************************************/ -static int stm32l4_epalloc(struct usbhost_driver_s *drvr, +static int stm32_epalloc(struct usbhost_driver_s *drvr, const struct usbhost_epdesc_s *epdesc, usbhost_ep_t *ep) { - struct stm32l4_usbhost_s *priv = (struct stm32l4_usbhost_s *)drvr; + struct stm32_usbhost_s *priv = (struct stm32_usbhost_s *)drvr; int ret; /* Sanity check. NOTE that this method should only be called if a device @@ -4162,11 +4162,11 @@ static int stm32l4_epalloc(struct usbhost_driver_s *drvr, if (epdesc->xfrtype == OTGFS_EPTYPE_CTRL) { - ret = stm32l4_ctrlep_alloc(priv, epdesc, ep); + ret = stm32_ctrlep_alloc(priv, epdesc, ep); } else { - ret = stm32l4_xfrep_alloc(priv, epdesc, ep); + ret = stm32_xfrep_alloc(priv, epdesc, ep); } nxmutex_unlock(&priv->lock); @@ -4174,7 +4174,7 @@ static int stm32l4_epalloc(struct usbhost_driver_s *drvr, } /**************************************************************************** - * Name: stm32l4_epfree + * Name: stm32_epfree * * Description: * Free and endpoint previously allocated by DRVR_EPALLOC. @@ -4193,9 +4193,9 @@ static int stm32l4_epalloc(struct usbhost_driver_s *drvr, * ****************************************************************************/ -static int stm32l4_epfree(struct usbhost_driver_s *drvr, usbhost_ep_t ep) +static int stm32_epfree(struct usbhost_driver_s *drvr, usbhost_ep_t ep) { - struct stm32l4_usbhost_s *priv = (struct stm32l4_usbhost_s *)drvr; + struct stm32_usbhost_s *priv = (struct stm32_usbhost_s *)drvr; int ret; DEBUGASSERT(priv); @@ -4205,25 +4205,25 @@ static int stm32l4_epfree(struct usbhost_driver_s *drvr, usbhost_ep_t ep) ret = nxmutex_lock(&priv->lock); /* A single channel is represent by an index in the range of 0 to - * STM32L4_MAX_TX_FIFOS. Otherwise, the ep must be a pointer to an + * STM32_MAX_TX_FIFOS. Otherwise, the ep must be a pointer to an * allocated control endpoint structure. */ - if ((uintptr_t)ep < STM32L4_MAX_TX_FIFOS) + if ((uintptr_t)ep < STM32_MAX_TX_FIFOS) { /* Halt the channel and mark the channel available */ - stm32l4_chan_free(priv, (int)ep); + stm32_chan_free(priv, (int)ep); } else { /* Halt both control channel and mark the channels available */ - struct stm32l4_ctrlinfo_s *ctrlep = - (struct stm32l4_ctrlinfo_s *)ep; + struct stm32_ctrlinfo_s *ctrlep = + (struct stm32_ctrlinfo_s *)ep; - stm32l4_chan_free(priv, ctrlep->inndx); - stm32l4_chan_free(priv, ctrlep->outndx); + stm32_chan_free(priv, ctrlep->inndx); + stm32_chan_free(priv, ctrlep->outndx); /* And free the control endpoint container */ @@ -4235,7 +4235,7 @@ static int stm32l4_epfree(struct usbhost_driver_s *drvr, usbhost_ep_t ep) } /**************************************************************************** - * Name: stm32l4_alloc + * Name: stm32_alloc * * Description: * Some hardware supports special memory in which request and descriptor @@ -4268,7 +4268,7 @@ static int stm32l4_epfree(struct usbhost_driver_s *drvr, usbhost_ep_t ep) ****************************************************************************/ #warning this function name is too generic -static int stm32l4_alloc(struct usbhost_driver_s *drvr, +static int stm32_alloc(struct usbhost_driver_s *drvr, uint8_t **buffer, size_t *maxlen) { uint8_t *alloc; @@ -4277,7 +4277,7 @@ static int stm32l4_alloc(struct usbhost_driver_s *drvr, /* There is no special memory requirement for the STM32. */ - alloc = kmm_malloc(CONFIG_STM32L4_OTGFS_DESCSIZE); + alloc = kmm_malloc(CONFIG_STM32_OTGFS_DESCSIZE); if (!alloc) { return -ENOMEM; @@ -4286,12 +4286,12 @@ static int stm32l4_alloc(struct usbhost_driver_s *drvr, /* Return the allocated address and size of the descriptor buffer */ *buffer = alloc; - *maxlen = CONFIG_STM32L4_OTGFS_DESCSIZE; + *maxlen = CONFIG_STM32_OTGFS_DESCSIZE; return OK; } /**************************************************************************** - * Name: stm32l4_free + * Name: stm32_free * * Description: * Some hardware supports special memory in which request and descriptor @@ -4315,7 +4315,7 @@ static int stm32l4_alloc(struct usbhost_driver_s *drvr, ****************************************************************************/ #warning this function name is too generic -static int stm32l4_free(struct usbhost_driver_s *drvr, +static int stm32_free(struct usbhost_driver_s *drvr, uint8_t *buffer) { /* There is no special memory requirement */ @@ -4326,7 +4326,7 @@ static int stm32l4_free(struct usbhost_driver_s *drvr, } /**************************************************************************** - * Name: stm32l4_ioalloc + * Name: stm32_ioalloc * * Description: * Some hardware supports special memory in which larger IO buffers can @@ -4355,7 +4355,7 @@ static int stm32l4_free(struct usbhost_driver_s *drvr, ****************************************************************************/ #warning this function name is too generic -static int stm32l4_ioalloc(struct usbhost_driver_s *drvr, +static int stm32_ioalloc(struct usbhost_driver_s *drvr, uint8_t **buffer, size_t buflen) { uint8_t *alloc; @@ -4377,7 +4377,7 @@ static int stm32l4_ioalloc(struct usbhost_driver_s *drvr, } /**************************************************************************** - * Name: stm32l4_iofree + * Name: stm32_iofree * * Description: * Some hardware supports special memory in which IO data can be accessed @@ -4399,7 +4399,7 @@ static int stm32l4_ioalloc(struct usbhost_driver_s *drvr, * ****************************************************************************/ -static int stm32l4_iofree(struct usbhost_driver_s *drvr, +static int stm32_iofree(struct usbhost_driver_s *drvr, uint8_t *buffer) { /* There is no special memory requirement */ @@ -4410,7 +4410,7 @@ static int stm32l4_iofree(struct usbhost_driver_s *drvr, } /**************************************************************************** - * Name: stm32l4_ctrlin and stm32l4_ctrlout + * Name: stm32_ctrlin and stm32_ctrlout * * Description: * Process a IN or OUT request on the control endpoint. These methods @@ -4446,14 +4446,14 @@ static int stm32l4_iofree(struct usbhost_driver_s *drvr, * ****************************************************************************/ -static int stm32l4_ctrlin(struct usbhost_driver_s *drvr, +static int stm32_ctrlin(struct usbhost_driver_s *drvr, usbhost_ep_t ep0, const struct usb_ctrlreq_s *req, uint8_t *buffer) { - struct stm32l4_usbhost_s *priv = (struct stm32l4_usbhost_s *)drvr; - struct stm32l4_ctrlinfo_s *ep0info = - (struct stm32l4_ctrlinfo_s *)ep0; + struct stm32_usbhost_s *priv = (struct stm32_usbhost_s *)drvr; + struct stm32_ctrlinfo_s *ep0info = + (struct stm32_ctrlinfo_s *)ep0; uint16_t buflen; clock_t start; clock_t elapsed; @@ -4468,7 +4468,7 @@ static int stm32l4_ctrlin(struct usbhost_driver_s *drvr, /* Extract values from the request */ - buflen = stm32l4_getle16(req->len); + buflen = stm32_getle16(req->len); /* We must have exclusive access to the USB host hardware and structures */ @@ -4480,11 +4480,11 @@ static int stm32l4_ctrlin(struct usbhost_driver_s *drvr, /* Loop, retrying until the retry time expires */ - for (retries = 0; retries < STM32L4_RETRY_COUNT; retries++) + for (retries = 0; retries < STM32_RETRY_COUNT; retries++) { /* Send the SETUP request */ - ret = stm32l4_ctrl_sendsetup(priv, ep0info, req); + ret = stm32_ctrl_sendsetup(priv, ep0info, req); if (ret < 0) { usbhost_trace1(OTGFS_TRACE1_SENDSETUP, -ret); @@ -4495,7 +4495,7 @@ static int stm32l4_ctrlin(struct usbhost_driver_s *drvr, if (buflen > 0) { - ret = stm32l4_ctrl_recvdata(priv, ep0info, buffer, buflen); + ret = stm32_ctrl_recvdata(priv, ep0info, buffer, buflen); if (ret < 0) { usbhost_trace1(OTGFS_TRACE1_RECVDATA, -ret); @@ -4511,7 +4511,7 @@ static int stm32l4_ctrlin(struct usbhost_driver_s *drvr, /* Handle the status OUT phase */ priv->chan[ep0info->outndx].outdata1 ^= true; - ret = stm32l4_ctrl_senddata(priv, ep0info, NULL, 0); + ret = stm32_ctrl_senddata(priv, ep0info, NULL, 0); if (ret == OK) { /* All success transactions exit here */ @@ -4526,7 +4526,7 @@ static int stm32l4_ctrlin(struct usbhost_driver_s *drvr, elapsed = clock_systime_ticks() - start; } - while (elapsed < STM32L4_DATANAK_DELAY); + while (elapsed < STM32_DATANAK_DELAY); } /* All failures exit here after all retries and timeouts are exhausted */ @@ -4535,14 +4535,14 @@ static int stm32l4_ctrlin(struct usbhost_driver_s *drvr, return -ETIMEDOUT; } -static int stm32l4_ctrlout(struct usbhost_driver_s *drvr, +static int stm32_ctrlout(struct usbhost_driver_s *drvr, usbhost_ep_t ep0, const struct usb_ctrlreq_s *req, const uint8_t *buffer) { - struct stm32l4_usbhost_s *priv = (struct stm32l4_usbhost_s *)drvr; - struct stm32l4_ctrlinfo_s *ep0info = - (struct stm32l4_ctrlinfo_s *)ep0; + struct stm32_usbhost_s *priv = (struct stm32_usbhost_s *)drvr; + struct stm32_ctrlinfo_s *ep0info = + (struct stm32_ctrlinfo_s *)ep0; uint16_t buflen; clock_t start; clock_t elapsed; @@ -4557,7 +4557,7 @@ static int stm32l4_ctrlout(struct usbhost_driver_s *drvr, /* Extract values from the request */ - buflen = stm32l4_getle16(req->len); + buflen = stm32_getle16(req->len); /* We must have exclusive access to the USB host hardware and structures */ @@ -4569,11 +4569,11 @@ static int stm32l4_ctrlout(struct usbhost_driver_s *drvr, /* Loop, retrying until the retry time expires */ - for (retries = 0; retries < STM32L4_RETRY_COUNT; retries++) + for (retries = 0; retries < STM32_RETRY_COUNT; retries++) { /* Send the SETUP request */ - ret = stm32l4_ctrl_sendsetup(priv, ep0info, req); + ret = stm32_ctrl_sendsetup(priv, ep0info, req); if (ret < 0) { usbhost_trace1(OTGFS_TRACE1_SENDSETUP, -ret); @@ -4592,7 +4592,7 @@ static int stm32l4_ctrlout(struct usbhost_driver_s *drvr, /* Start DATA out transfer (only one DATA packet) */ priv->chan[ep0info->outndx].outdata1 = true; - ret = stm32l4_ctrl_senddata(priv, ep0info, NULL, 0); + ret = stm32_ctrl_senddata(priv, ep0info, NULL, 0); if (ret < 0) { usbhost_trace1(OTGFS_TRACE1_SENDDATA, -ret); @@ -4603,7 +4603,7 @@ static int stm32l4_ctrlout(struct usbhost_driver_s *drvr, if (ret == OK) { - ret = stm32l4_ctrl_recvdata(priv, ep0info, NULL, 0); + ret = stm32_ctrl_recvdata(priv, ep0info, NULL, 0); if (ret == OK) { /* All success transactins exit here */ @@ -4619,7 +4619,7 @@ static int stm32l4_ctrlout(struct usbhost_driver_s *drvr, elapsed = clock_systime_ticks() - start; } - while (elapsed < STM32L4_DATANAK_DELAY); + while (elapsed < STM32_DATANAK_DELAY); } /* All failures exit here after all retries and timeouts are exhausted */ @@ -4629,7 +4629,7 @@ static int stm32l4_ctrlout(struct usbhost_driver_s *drvr, } /**************************************************************************** - * Name: stm32l4_transfer + * Name: stm32_transfer * * Description: * Process a request to handle a transfer descriptor. This method will @@ -4667,18 +4667,18 @@ static int stm32l4_ctrlout(struct usbhost_driver_s *drvr, * ****************************************************************************/ -static ssize_t stm32l4_transfer(struct usbhost_driver_s *drvr, +static ssize_t stm32_transfer(struct usbhost_driver_s *drvr, usbhost_ep_t ep, uint8_t *buffer, size_t buflen) { - struct stm32l4_usbhost_s *priv = (struct stm32l4_usbhost_s *)drvr; + struct stm32_usbhost_s *priv = (struct stm32_usbhost_s *)drvr; unsigned int chidx = (unsigned int)ep; ssize_t nbytes; int ret; uvdbg("chidx: %d buflen: %d\n", (unsigned int)ep, buflen); - DEBUGASSERT(priv && buffer && chidx < STM32L4_MAX_TX_FIFOS && buflen > 0); + DEBUGASSERT(priv && buffer && chidx < STM32_MAX_TX_FIFOS && buflen > 0); /* We must have exclusive access to the USB host hardware and structures */ @@ -4692,11 +4692,11 @@ static ssize_t stm32l4_transfer(struct usbhost_driver_s *drvr, if (priv->chan[chidx].in) { - nbytes = stm32l4_in_transfer(priv, chidx, buffer, buflen); + nbytes = stm32_in_transfer(priv, chidx, buffer, buflen); } else { - nbytes = stm32l4_out_transfer(priv, chidx, buffer, buflen); + nbytes = stm32_out_transfer(priv, chidx, buffer, buflen); } nxmutex_unlock(&priv->lock); @@ -4704,7 +4704,7 @@ static ssize_t stm32l4_transfer(struct usbhost_driver_s *drvr, } /**************************************************************************** - * Name: stm32l4_asynch + * Name: stm32_asynch * * Description: * Process a request to handle a transfer descriptor. This method will @@ -4740,17 +4740,17 @@ static ssize_t stm32l4_transfer(struct usbhost_driver_s *drvr, ****************************************************************************/ #ifdef CONFIG_USBHOST_ASYNCH -static int stm32l4_asynch(struct usbhost_driver_s *drvr, usbhost_ep_t ep, +static int stm32_asynch(struct usbhost_driver_s *drvr, usbhost_ep_t ep, uint8_t *buffer, size_t buflen, usbhost_asynch_t callback, void *arg) { - struct stm32l4_usbhost_s *priv = (struct stm32l4_usbhost_s *)drvr; + struct stm32_usbhost_s *priv = (struct stm32_usbhost_s *)drvr; unsigned int chidx = (unsigned int)ep; int ret; uvdbg("chidx: %d buflen: %d\n", (unsigned int)ep, buflen); - DEBUGASSERT(priv && buffer && chidx < STM32L4_MAX_TX_FIFOS && buflen > 0); + DEBUGASSERT(priv && buffer && chidx < STM32_MAX_TX_FIFOS && buflen > 0); /* We must have exclusive access to the USB host hardware and structures */ @@ -4764,11 +4764,11 @@ static int stm32l4_asynch(struct usbhost_driver_s *drvr, usbhost_ep_t ep, if (priv->chan[chidx].in) { - ret = stm32l4_in_asynch(priv, chidx, buffer, buflen, callback, arg); + ret = stm32_in_asynch(priv, chidx, buffer, buflen, callback, arg); } else { - ret = stm32l4_out_asynch(priv, chidx, buffer, buflen, callback, arg); + ret = stm32_out_asynch(priv, chidx, buffer, buflen, callback, arg); } nxmutex_unlock(&priv->lock); @@ -4777,7 +4777,7 @@ static int stm32l4_asynch(struct usbhost_driver_s *drvr, usbhost_ep_t ep, #endif /* CONFIG_USBHOST_ASYNCH */ /**************************************************************************** - * Name: stm32l4_cancel + * Name: stm32_cancel * * Description: * Cancel a pending transfer on an endpoint. Cancelled synchronous or @@ -4795,16 +4795,16 @@ static int stm32l4_asynch(struct usbhost_driver_s *drvr, usbhost_ep_t ep, * ****************************************************************************/ -static int stm32l4_cancel(struct usbhost_driver_s *drvr, usbhost_ep_t ep) +static int stm32_cancel(struct usbhost_driver_s *drvr, usbhost_ep_t ep) { - struct stm32l4_usbhost_s *priv = (struct stm32l4_usbhost_s *)drvr; - struct stm32l4_chan_s *chan; + struct stm32_usbhost_s *priv = (struct stm32_usbhost_s *)drvr; + struct stm32_chan_s *chan; unsigned int chidx = (unsigned int)ep; irqstate_t flags; uvdbg("chidx: %u: %d\n", chidx); - DEBUGASSERT(priv && chidx < STM32L4_MAX_TX_FIFOS); + DEBUGASSERT(priv && chidx < STM32_MAX_TX_FIFOS); chan = &priv->chan[chidx]; /* We need to disable interrupts to avoid race conditions with the @@ -4815,7 +4815,7 @@ static int stm32l4_cancel(struct usbhost_driver_s *drvr, usbhost_ep_t ep) /* Halt the channel */ - stm32l4_chan_halt(priv, chidx, CHREASON_CANCELLED); + stm32_chan_halt(priv, chidx, CHREASON_CANCELLED); chan->result = -ESHUTDOWN; /* Is there a thread waiting for this transfer to complete? */ @@ -4864,7 +4864,7 @@ static int stm32l4_cancel(struct usbhost_driver_s *drvr, usbhost_ep_t ep) } /**************************************************************************** - * Name: stm32l4_connect + * Name: stm32_connect * * Description: * New connections may be detected by an attached hub. This method is @@ -4885,11 +4885,11 @@ static int stm32l4_cancel(struct usbhost_driver_s *drvr, usbhost_ep_t ep) ****************************************************************************/ #ifdef CONFIG_USBHOST_HUB -static int stm32l4_connect(struct usbhost_driver_s *drvr, +static int stm32_connect(struct usbhost_driver_s *drvr, struct usbhost_hubport_s *hport, bool connected) { - struct stm32l4_usbhost_s *priv = (struct stm32l4_usbhost_s *)drvr; + struct stm32_usbhost_s *priv = (struct stm32_usbhost_s *)drvr; irqstate_t flags; DEBUGASSERT(priv != NULL && hport != NULL); @@ -4916,7 +4916,7 @@ static int stm32l4_connect(struct usbhost_driver_s *drvr, #endif /**************************************************************************** - * Name: stm32l4_disconnect + * Name: stm32_disconnect * * Description: * Called by the class when an error occurs and driver has been @@ -4941,7 +4941,7 @@ static int stm32l4_connect(struct usbhost_driver_s *drvr, * ****************************************************************************/ -static void stm32l4_disconnect(struct usbhost_driver_s *drvr, +static void stm32_disconnect(struct usbhost_driver_s *drvr, struct usbhost_hubport_s *hport) { DEBUGASSERT(hport != NULL); @@ -4953,7 +4953,7 @@ static void stm32l4_disconnect(struct usbhost_driver_s *drvr, ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_portreset + * Name: stm32_portreset * * Description: * Reset the USB host port. @@ -4972,26 +4972,26 @@ static void stm32l4_disconnect(struct usbhost_driver_s *drvr, * ****************************************************************************/ -static void stm32l4_portreset(struct stm32l4_usbhost_s *priv) +static void stm32_portreset(struct stm32_usbhost_s *priv) { uint32_t regval; - regval = stm32l4_getreg(STM32L4_OTGFS_HPRT); + regval = stm32_getreg(STM32_OTGFS_HPRT); regval &= ~(OTGFS_HPRT_PENA | OTGFS_HPRT_PCDET | OTGFS_HPRT_PENCHNG | OTGFS_HPRT_POCCHNG); regval |= OTGFS_HPRT_PRST; - stm32l4_putreg(STM32L4_OTGFS_HPRT, regval); + stm32_putreg(STM32_OTGFS_HPRT, regval); up_mdelay(20); regval &= ~OTGFS_HPRT_PRST; - stm32l4_putreg(STM32L4_OTGFS_HPRT, regval); + stm32_putreg(STM32_OTGFS_HPRT, regval); up_mdelay(20); } /**************************************************************************** - * Name: stm32l4_flush_txfifos + * Name: stm32_flush_txfifos * * Description: * Flush the selected Tx FIFO. @@ -5004,7 +5004,7 @@ static void stm32l4_portreset(struct stm32l4_usbhost_s *priv) * ****************************************************************************/ -static void stm32l4_flush_txfifos(uint32_t txfnum) +static void stm32_flush_txfifos(uint32_t txfnum) { uint32_t regval; uint32_t timeout; @@ -5012,13 +5012,13 @@ static void stm32l4_flush_txfifos(uint32_t txfnum) /* Initiate the TX FIFO flush operation */ regval = OTGFS_GRSTCTL_TXFFLSH | txfnum; - stm32l4_putreg(STM32L4_OTGFS_GRSTCTL, regval); + stm32_putreg(STM32_OTGFS_GRSTCTL, regval); /* Wait for the FLUSH to complete */ - for (timeout = 0; timeout < STM32L4_FLUSH_DELAY; timeout++) + for (timeout = 0; timeout < STM32_FLUSH_DELAY; timeout++) { - regval = stm32l4_getreg(STM32L4_OTGFS_GRSTCTL); + regval = stm32_getreg(STM32_OTGFS_GRSTCTL); if ((regval & OTGFS_GRSTCTL_TXFFLSH) == 0) { break; @@ -5031,7 +5031,7 @@ static void stm32l4_flush_txfifos(uint32_t txfnum) } /**************************************************************************** - * Name: stm32l4_flush_rxfifo + * Name: stm32_flush_rxfifo * * Description: * Flush the Rx FIFO. @@ -5044,20 +5044,20 @@ static void stm32l4_flush_txfifos(uint32_t txfnum) * ****************************************************************************/ -static void stm32l4_flush_rxfifo(void) +static void stm32_flush_rxfifo(void) { uint32_t regval; uint32_t timeout; /* Initiate the RX FIFO flush operation */ - stm32l4_putreg(STM32L4_OTGFS_GRSTCTL, OTGFS_GRSTCTL_RXFFLSH); + stm32_putreg(STM32_OTGFS_GRSTCTL, OTGFS_GRSTCTL_RXFFLSH); /* Wait for the FLUSH to complete */ - for (timeout = 0; timeout < STM32L4_FLUSH_DELAY; timeout++) + for (timeout = 0; timeout < STM32_FLUSH_DELAY; timeout++) { - regval = stm32l4_getreg(STM32L4_OTGFS_GRSTCTL); + regval = stm32_getreg(STM32_OTGFS_GRSTCTL); if ((regval & OTGFS_GRSTCTL_RXFFLSH) == 0) { break; @@ -5070,7 +5070,7 @@ static void stm32l4_flush_rxfifo(void) } /**************************************************************************** - * Name: stm32l4_vbusdrive + * Name: stm32_vbusdrive * * Description: * Drive the Vbus +5V. @@ -5084,41 +5084,41 @@ static void stm32l4_flush_rxfifo(void) * ****************************************************************************/ -static void stm32l4_vbusdrive(struct stm32l4_usbhost_s *priv, bool state) +static void stm32_vbusdrive(struct stm32_usbhost_s *priv, bool state) { uint32_t regval; /* Enable/disable the external charge pump */ - stm32l4_usbhost_vbusdrive(0, state); + stm32_usbhost_vbusdrive(0, state); /* Turn on the Host port power. */ - regval = stm32l4_getreg(STM32L4_OTGFS_HPRT); + regval = stm32_getreg(STM32_OTGFS_HPRT); regval &= ~(OTGFS_HPRT_PENA | OTGFS_HPRT_PCDET | OTGFS_HPRT_PENCHNG | OTGFS_HPRT_POCCHNG); if (((regval & OTGFS_HPRT_PPWR) == 0) && state) { regval |= OTGFS_HPRT_PPWR; - stm32l4_putreg(STM32L4_OTGFS_HPRT, regval); + stm32_putreg(STM32_OTGFS_HPRT, regval); } if (((regval & OTGFS_HPRT_PPWR) != 0) && !state) { regval &= ~OTGFS_HPRT_PPWR; - stm32l4_putreg(STM32L4_OTGFS_HPRT, regval); + stm32_putreg(STM32_OTGFS_HPRT, regval); } up_mdelay(200); } /**************************************************************************** - * Name: stm32l4_host_initialize + * Name: stm32_host_initialize * * Description: * Initialize/re-initialize hardware for host mode operation. At present, - * this function is called only from stm32l4_hw_initialize(). But if OTG + * this function is called only from stm32_hw_initialize(). But if OTG * mode were supported, this function would also be called to switch * between host and device modes on a connector ID change interrupt. * @@ -5130,7 +5130,7 @@ static void stm32l4_vbusdrive(struct stm32l4_usbhost_s *priv, bool state) * ****************************************************************************/ -static void stm32l4_host_initialize(struct stm32l4_usbhost_s *priv) +static void stm32_host_initialize(struct stm32_usbhost_s *priv) { uint32_t regval; uint32_t offset; @@ -5138,24 +5138,24 @@ static void stm32l4_host_initialize(struct stm32l4_usbhost_s *priv) /* Restart the PHY Clock */ - stm32l4_putreg(STM32L4_OTGFS_PCGCCTL, 0); + stm32_putreg(STM32_OTGFS_PCGCCTL, 0); /* Initialize Host Configuration (HCFG) register */ - regval = stm32l4_getreg(STM32L4_OTGFS_HCFG); + regval = stm32_getreg(STM32_OTGFS_HCFG); regval &= ~OTGFS_HCFG_FSLSPCS_MASK; regval |= OTGFS_HCFG_FSLSPCS_FS48MHz; - stm32l4_putreg(STM32L4_OTGFS_HCFG, regval); + stm32_putreg(STM32_OTGFS_HCFG, regval); /* Reset the host port */ - stm32l4_portreset(priv); + stm32_portreset(priv); /* Clear the FS-/LS-only support bit in the HCFG register */ - regval = stm32l4_getreg(STM32L4_OTGFS_HCFG); + regval = stm32_getreg(STM32_OTGFS_HCFG); regval &= ~OTGFS_HCFG_FSLSS; - stm32l4_putreg(STM32L4_OTGFS_HCFG, regval); + stm32_putreg(STM32_OTGFS_HCFG, regval); /* Carve up FIFO memory for the Rx FIFO and the periodic and non-periodic * Tx FIFOs @@ -5163,23 +5163,23 @@ static void stm32l4_host_initialize(struct stm32l4_usbhost_s *priv) /* Configure Rx FIFO size (GRXFSIZ) */ - stm32l4_putreg(STM32L4_OTGFS_GRXFSIZ, CONFIG_STM32L4_OTGFS_RXFIFO_SIZE); - offset = CONFIG_STM32L4_OTGFS_RXFIFO_SIZE; + stm32_putreg(STM32_OTGFS_GRXFSIZ, CONFIG_STM32_OTGFS_RXFIFO_SIZE); + offset = CONFIG_STM32_OTGFS_RXFIFO_SIZE; /* Setup the host non-periodic Tx FIFO size (HNPTXFSIZ) */ regval = (offset | - (CONFIG_STM32L4_OTGFS_NPTXFIFO_SIZE << + (CONFIG_STM32_OTGFS_NPTXFIFO_SIZE << OTGFS_HNPTXFSIZ_NPTXFD_SHIFT)); - stm32l4_putreg(STM32L4_OTGFS_HNPTXFSIZ, regval); - offset += CONFIG_STM32L4_OTGFS_NPTXFIFO_SIZE; + stm32_putreg(STM32_OTGFS_HNPTXFSIZ, regval); + offset += CONFIG_STM32_OTGFS_NPTXFIFO_SIZE; /* Set up the host periodic Tx fifo size register (HPTXFSIZ) */ regval = (offset | - (CONFIG_STM32L4_OTGFS_PTXFIFO_SIZE << + (CONFIG_STM32_OTGFS_PTXFIFO_SIZE << OTGFS_HPTXFSIZ_PTXFD_SHIFT)); - stm32l4_putreg(STM32L4_OTGFS_HPTXFSIZ, regval); + stm32_putreg(STM32_OTGFS_HPTXFSIZ, regval); /* If OTG were supported, we should need to clear HNP enable bit in the * USB_OTG control register about here. @@ -5187,30 +5187,30 @@ static void stm32l4_host_initialize(struct stm32l4_usbhost_s *priv) /* Flush all FIFOs */ - stm32l4_flush_txfifos(OTGFS_GRSTCTL_TXFNUM_HALL); - stm32l4_flush_rxfifo(); + stm32_flush_txfifos(OTGFS_GRSTCTL_TXFNUM_HALL); + stm32_flush_rxfifo(); /* Clear all pending HC Interrupts */ - for (i = 0; i < STM32L4_NHOST_CHANNELS; i++) + for (i = 0; i < STM32_NHOST_CHANNELS; i++) { - stm32l4_putreg(STM32L4_OTGFS_HCINT(i), 0xffffffff); - stm32l4_putreg(STM32L4_OTGFS_HCINTMSK(i), 0); + stm32_putreg(STM32_OTGFS_HCINT(i), 0xffffffff); + stm32_putreg(STM32_OTGFS_HCINTMSK(i), 0); } /* Driver Vbus +5V (the smoke test). Should be done elsewhere in OTG * mode. */ - stm32l4_vbusdrive(priv, true); + stm32_vbusdrive(priv, true); /* Enable host interrupts */ - stm32l4_hostinit_enable(); + stm32_hostinit_enable(); } /**************************************************************************** - * Name: stm32l4_sw_initialize + * Name: stm32_sw_initialize * * Description: * One-time setup of the host driver state structure. @@ -5223,7 +5223,7 @@ static void stm32l4_host_initialize(struct stm32l4_usbhost_s *priv) * ****************************************************************************/ -static inline void stm32l4_sw_initialize(struct stm32l4_usbhost_s *priv) +static inline void stm32_sw_initialize(struct stm32_usbhost_s *priv) { struct usbhost_driver_s *drvr; struct usbhost_hubport_s *hport; @@ -5232,24 +5232,24 @@ static inline void stm32l4_sw_initialize(struct stm32l4_usbhost_s *priv) /* Initialize the device operations */ drvr = &priv->drvr; - drvr->ep0configure = stm32l4_ep0configure; - drvr->epalloc = stm32l4_epalloc; - drvr->epfree = stm32l4_epfree; - drvr->alloc = stm32l4_alloc; - drvr->free = stm32l4_free; - drvr->ioalloc = stm32l4_ioalloc; - drvr->iofree = stm32l4_iofree; - drvr->ctrlin = stm32l4_ctrlin; - drvr->ctrlout = stm32l4_ctrlout; - drvr->transfer = stm32l4_transfer; + drvr->ep0configure = stm32_ep0configure; + drvr->epalloc = stm32_epalloc; + drvr->epfree = stm32_epfree; + drvr->alloc = stm32_alloc; + drvr->free = stm32_free; + drvr->ioalloc = stm32_ioalloc; + drvr->iofree = stm32_iofree; + drvr->ctrlin = stm32_ctrlin; + drvr->ctrlout = stm32_ctrlout; + drvr->transfer = stm32_transfer; #ifdef CONFIG_USBHOST_ASYNCH - drvr->asynch = stm32l4_asynch; + drvr->asynch = stm32_asynch; #endif - drvr->cancel = stm32l4_cancel; + drvr->cancel = stm32_cancel; #ifdef CONFIG_USBHOST_HUB - drvr->connect = stm32l4_connect; + drvr->connect = stm32_connect; #endif - drvr->disconnect = stm32l4_disconnect; + drvr->disconnect = stm32_disconnect; /* Initialize the public port representation */ @@ -5275,13 +5275,13 @@ static inline void stm32l4_sw_initialize(struct stm32l4_usbhost_s *priv) /* Put all of the channels back in their initial, allocated state */ memset(priv->chan, 0, - STM32L4_MAX_TX_FIFOS * sizeof(struct stm32l4_chan_s)); + STM32_MAX_TX_FIFOS * sizeof(struct stm32_chan_s)); /* Initialize each channel */ - for (i = 0; i < STM32L4_MAX_TX_FIFOS; i++) + for (i = 0; i < STM32_MAX_TX_FIFOS; i++) { - struct stm32l4_chan_s *chan = &priv->chan[i]; + struct stm32_chan_s *chan = &priv->chan[i]; chan->chidx = i; nxsem_init(&chan->waitsem, 0, 0); @@ -5289,7 +5289,7 @@ static inline void stm32l4_sw_initialize(struct stm32l4_usbhost_s *priv) } /**************************************************************************** - * Name: stm32l4_hw_initialize + * Name: stm32_hw_initialize * * Description: * One-time setup of the host controller hardware for normal operations. @@ -5302,7 +5302,7 @@ static inline void stm32l4_sw_initialize(struct stm32l4_usbhost_s *priv) * ****************************************************************************/ -static inline int stm32l4_hw_initialize(struct stm32l4_usbhost_s *priv) +static inline int stm32_hw_initialize(struct stm32_usbhost_s *priv) { uint32_t regval; unsigned long timeout; @@ -5311,18 +5311,18 @@ static inline int stm32l4_hw_initialize(struct stm32l4_usbhost_s *priv) * transceiver: "This bit is always 1 with write-only access" */ - regval = stm32l4_getreg(STM32L4_OTGFS_GUSBCFG); + regval = stm32_getreg(STM32_OTGFS_GUSBCFG); regval |= OTGFS_GUSBCFG_PHYSEL; - stm32l4_putreg(STM32L4_OTGFS_GUSBCFG, regval); + stm32_putreg(STM32_OTGFS_GUSBCFG, regval); /* Reset after a PHY select and set Host mode. First, wait for AHB master * IDLE state. */ - for (timeout = 0; timeout < STM32L4_READY_DELAY; timeout++) + for (timeout = 0; timeout < STM32_READY_DELAY; timeout++) { up_udelay(3); - regval = stm32l4_getreg(STM32L4_OTGFS_GRSTCTL); + regval = stm32_getreg(STM32_OTGFS_GRSTCTL); if ((regval & OTGFS_GRSTCTL_AHBIDL) != 0) { break; @@ -5331,10 +5331,10 @@ static inline int stm32l4_hw_initialize(struct stm32l4_usbhost_s *priv) /* Then perform the core soft reset. */ - stm32l4_putreg(STM32L4_OTGFS_GRSTCTL, OTGFS_GRSTCTL_CSRST); - for (timeout = 0; timeout < STM32L4_READY_DELAY; timeout++) + stm32_putreg(STM32_OTGFS_GRSTCTL, OTGFS_GRSTCTL_CSRST); + for (timeout = 0; timeout < STM32_READY_DELAY; timeout++) { - regval = stm32l4_getreg(STM32L4_OTGFS_GRSTCTL); + regval = stm32_getreg(STM32_OTGFS_GRSTCTL); if ((regval & OTGFS_GRSTCTL_CSRST) == 0) { break; @@ -5352,10 +5352,10 @@ static inline int stm32l4_hw_initialize(struct stm32l4_usbhost_s *priv) #ifndef CONFIG_USBDEV_VBUSSENSING regval |= OTGFS_GCCFG_NOVBUSSENS; #endif -#ifdef CONFIG_STM32L4_OTGFS_SOFOUTPUT +#ifdef CONFIG_STM32_OTGFS_SOFOUTPUT regval |= OTGFS_GCCFG_SOFOUTEN; #endif - stm32l4_putreg(STM32L4_OTGFS_GCCFG, regval); + stm32_putreg(STM32_OTGFS_GCCFG, regval); up_mdelay(20); /* Initialize OTG features: In order to support OTP, the HNPCAP and SRPCAP @@ -5364,15 +5364,15 @@ static inline int stm32l4_hw_initialize(struct stm32l4_usbhost_s *priv) /* Force Host Mode */ - regval = stm32l4_getreg(STM32L4_OTGFS_GUSBCFG); + regval = stm32_getreg(STM32_OTGFS_GUSBCFG); regval &= ~OTGFS_GUSBCFG_FDMOD; regval |= OTGFS_GUSBCFG_FHMOD; - stm32l4_putreg(STM32L4_OTGFS_GUSBCFG, regval); + stm32_putreg(STM32_OTGFS_GUSBCFG, regval); up_mdelay(50); /* Initialize host mode and return success */ - stm32l4_host_initialize(priv); + stm32_host_initialize(priv); return OK; } @@ -5381,7 +5381,7 @@ static inline int stm32l4_hw_initialize(struct stm32l4_usbhost_s *priv) ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_otgfshost_initialize + * Name: stm32_otgfshost_initialize * * Description: * Initialize USB host device controller hardware. @@ -5405,7 +5405,7 @@ static inline int stm32l4_hw_initialize(struct stm32l4_usbhost_s *priv) * ****************************************************************************/ -struct usbhost_connection_s *stm32l4_otgfshost_initialize(int controller) +struct usbhost_connection_s *stm32_otgfshost_initialize(int controller) { /* At present, there is only support for a single OTG FS host. Hence it is * pre-allocated as g_usbhost. However, in most code, the private data @@ -5414,7 +5414,7 @@ struct usbhost_connection_s *stm32l4_otgfshost_initialize(int controller) * devices. */ - struct stm32l4_usbhost_s *priv = &g_usbhost; + struct stm32_usbhost_s *priv = &g_usbhost; /* Sanity checks */ @@ -5422,11 +5422,11 @@ struct usbhost_connection_s *stm32l4_otgfshost_initialize(int controller) /* Make sure that interrupts from the OTG FS core are disabled */ - stm32l4_gint_disable(); + stm32_gint_disable(); /* Reset the state of the host driver */ - stm32l4_sw_initialize(priv); + stm32_sw_initialize(priv); /* Alternate function pin configuration. Here we assume that: * @@ -5451,23 +5451,23 @@ struct usbhost_connection_s *stm32l4_otgfshost_initialize(int controller) * *Pins may vary from device-to-device. */ - stm32l4_configgpio(GPIO_OTGFS_DM); - stm32l4_configgpio(GPIO_OTGFS_DP); - stm32l4_configgpio(GPIO_OTGFS_ID); /* Only needed for OTG */ + stm32_configgpio(GPIO_OTGFS_DM); + stm32_configgpio(GPIO_OTGFS_DP); + stm32_configgpio(GPIO_OTGFS_ID); /* Only needed for OTG */ /* SOF output pin configuration is configurable */ -#ifdef CONFIG_STM32L4_OTGFS_SOFOUTPUT - stm32l4_configgpio(GPIO_OTGFS_SOF); +#ifdef CONFIG_STM32_OTGFS_SOFOUTPUT + stm32_configgpio(GPIO_OTGFS_SOF); #endif /* Initialize the USB OTG FS core */ - stm32l4_hw_initialize(priv); + stm32_hw_initialize(priv); /* Attach USB host controller interrupt handler */ - if (irq_attach(STM32L4_IRQ_OTGFS, stm32l4_gint_isr, NULL) != 0) + if (irq_attach(STM32_IRQ_OTGFS, stm32_gint_isr, NULL) != 0) { usbhost_trace1(OTGFS_TRACE1_IRQATTACH, 0); return NULL; @@ -5475,12 +5475,12 @@ struct usbhost_connection_s *stm32l4_otgfshost_initialize(int controller) /* Enable USB OTG FS global interrupts */ - stm32l4_gint_enable(); + stm32_gint_enable(); /* Enable interrupts at the interrupt controller */ - up_enable_irq(STM32L4_IRQ_OTGFS); + up_enable_irq(STM32_IRQ_OTGFS); return &g_usbconn; } -#endif /* CONFIG_USBHOST && CONFIG_STM32L4_OTGFS */ +#endif /* CONFIG_USBHOST && CONFIG_STM32_OTGFS */ diff --git a/arch/arm/src/stm32l4/stm32l4_pm.h b/arch/arm/src/stm32l4/stm32l4_pm.h index d8f276e282a03..b4cf0be0318fa 100644 --- a/arch/arm/src/stm32l4/stm32l4_pm.h +++ b/arch/arm/src/stm32l4/stm32l4_pm.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32L4_STM32L4_PM_H -#define __ARCH_ARM_SRC_STM32L4_STM32L4_PM_H +#ifndef __ARCH_ARM_SRC_STM32L4_STM32_PM_H +#define __ARCH_ARM_SRC_STM32L4_STM32_PM_H /**************************************************************************** * Included Files @@ -48,7 +48,7 @@ extern "C" #endif /**************************************************************************** - * Name: stm32l4_pmstop + * Name: stm32_pmstop * * Description: * Enter STOP mode. @@ -66,10 +66,10 @@ extern "C" * ****************************************************************************/ -int stm32l4_pmstop(bool lpds); +int stm32_pmstop(bool lpds); /**************************************************************************** - * Name: stm32l4_pmstop2 + * Name: stm32_pmstop2 * * Description: * Enter STOP2 mode. @@ -84,10 +84,10 @@ int stm32l4_pmstop(bool lpds); * ****************************************************************************/ -int stm32l4_pmstop2(void); +int stm32_pmstop2(void); /**************************************************************************** - * Name: stm32l4_pmstandby + * Name: stm32_pmstandby * * Description: * Enter STANDBY mode. @@ -103,10 +103,10 @@ int stm32l4_pmstop2(void); * ****************************************************************************/ -int stm32l4_pmstandby(void); +int stm32_pmstandby(void); /**************************************************************************** - * Name: stm32l4_pmsleep + * Name: stm32_pmsleep * * Description: * Enter SLEEP mode. @@ -122,10 +122,10 @@ int stm32l4_pmstandby(void); * ****************************************************************************/ -void stm32l4_pmsleep(bool sleeponexit); +void stm32_pmsleep(bool sleeponexit); /**************************************************************************** - * Name: stm32l4_pmlpr + * Name: stm32_pmlpr * * Description: * Enter Low-Power Run (LPR) mode. @@ -140,7 +140,7 @@ void stm32l4_pmsleep(bool sleeponexit); * ****************************************************************************/ -int stm32l4_pmlpr(void); +int stm32_pmlpr(void); #undef EXTERN #ifdef __cplusplus @@ -148,4 +148,4 @@ int stm32l4_pmlpr(void); #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32L4_STM32L4_PM_H */ +#endif /* __ARCH_ARM_SRC_STM32L4_STM32_PM_H */ diff --git a/arch/arm/src/stm32l4/stm32l4_pmlpr.c b/arch/arm/src/stm32l4/stm32l4_pmlpr.c index 100de46b5d0af..ae7a525c5eb21 100644 --- a/arch/arm/src/stm32l4/stm32l4_pmlpr.c +++ b/arch/arm/src/stm32l4/stm32l4_pmlpr.c @@ -54,7 +54,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_pmlpr + * Name: stm32_pmlpr * * Description: * Enter Low-Power Run (LPR) mode. @@ -69,13 +69,13 @@ * ****************************************************************************/ -int stm32l4_pmlpr(void) +int stm32_pmlpr(void) { uint32_t regval; /* Enable MSI clock */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_MSION; /* Set MSI clock to 2 MHz */ @@ -83,27 +83,27 @@ int stm32l4_pmlpr(void) regval &= ~RCC_CR_MSIRANGE_MASK; regval |= RCC_CR_MSIRANGE_2M; /* 2 MHz */ regval |= RCC_CR_MSIRGSEL; /* Select new MSIRANGE */ - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Select MSI clock as system clock source */ - regval = getreg32(STM32L4_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_SW_MASK; regval |= RCC_CFGR_SW_MSI; - putreg32(regval, STM32L4_RCC_CFGR); + putreg32(regval, STM32_RCC_CFGR); /* Wait until the MSI source is used as the system clock source */ - while ((getreg32(STM32L4_RCC_CFGR) & RCC_CFGR_SWS_MASK) != + while ((getreg32(STM32_RCC_CFGR) & RCC_CFGR_SWS_MASK) != RCC_CFGR_SWS_MSI) { } /* Enable Low-Power Run */ - regval = getreg32(STM32L4_PWR_CR1); + regval = getreg32(STM32_PWR_CR1); regval |= PWR_CR1_LPR; - putreg32(regval, STM32L4_PWR_CR1); + putreg32(regval, STM32_PWR_CR1); return OK; } diff --git a/arch/arm/src/stm32l4/stm32l4_pmsleep.c b/arch/arm/src/stm32l4/stm32l4_pmsleep.c index 24e4170a62acf..24dd46592318e 100644 --- a/arch/arm/src/stm32l4/stm32l4_pmsleep.c +++ b/arch/arm/src/stm32l4/stm32l4_pmsleep.c @@ -38,7 +38,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_pmsleep + * Name: stm32_pmsleep * * Description: * Enter SLEEP mode. @@ -54,7 +54,7 @@ * ****************************************************************************/ -void stm32l4_pmsleep(bool sleeponexit) +void stm32_pmsleep(bool sleeponexit) { uint32_t regval; diff --git a/arch/arm/src/stm32l4/stm32l4_pmstandby.c b/arch/arm/src/stm32l4/stm32l4_pmstandby.c index da50343ec3956..759ef841e9bf0 100644 --- a/arch/arm/src/stm32l4/stm32l4_pmstandby.c +++ b/arch/arm/src/stm32l4/stm32l4_pmstandby.c @@ -53,7 +53,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_pmstandby + * Name: stm32_pmstandby * * Description: * Enter STANDBY mode. @@ -69,7 +69,7 @@ * ****************************************************************************/ -int stm32l4_pmstandby(void) +int stm32_pmstandby(void) { uint32_t regval; @@ -79,15 +79,15 @@ int stm32l4_pmstandby(void) regval = PWR_SCR_CWUF1 | PWR_SCR_CWUF2 | PWR_SCR_CWUF3 | PWR_SCR_CWUF4 | PWR_SCR_CWUF5; - putreg32(regval, STM32L4_PWR_SCR); + putreg32(regval, STM32_PWR_SCR); /* Select Standby mode */ - regval = getreg32(STM32L4_PWR_CR1); + regval = getreg32(STM32_PWR_CR1); regval &= ~PWR_CR1_LPMS_MASK; regval |= PWR_CR1_LPMS_STANDBY; - putreg32(regval, STM32L4_PWR_CR1); + putreg32(regval, STM32_PWR_CR1); /* Set SLEEPDEEP bit of Cortex System Control Register */ diff --git a/arch/arm/src/stm32l4/stm32l4_pmstop.c b/arch/arm/src/stm32l4/stm32l4_pmstop.c index 8718d575322f4..cd57bbd4aa83d 100644 --- a/arch/arm/src/stm32l4/stm32l4_pmstop.c +++ b/arch/arm/src/stm32l4/stm32l4_pmstop.c @@ -88,7 +88,7 @@ static int do_stop(void) ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_pmstop + * Name: stm32_pmstop * * Description: * Enter STOP mode. @@ -106,7 +106,7 @@ static int do_stop(void) * ****************************************************************************/ -int stm32l4_pmstop(bool lpds) +int stm32_pmstop(bool lpds) { uint32_t regval; @@ -114,7 +114,7 @@ int stm32l4_pmstop(bool lpds) * register 1. */ - regval = getreg32(STM32L4_PWR_CR1); + regval = getreg32(STM32_PWR_CR1); regval &= ~PWR_CR1_LPMS_MASK; /* Select Stop 1 mode with low-power regulator if so requested */ @@ -124,13 +124,13 @@ int stm32l4_pmstop(bool lpds) regval |= PWR_CR1_LPMS_STOP1LPR; } - putreg32(regval, STM32L4_PWR_CR1); + putreg32(regval, STM32_PWR_CR1); return do_stop(); } /**************************************************************************** - * Name: stm32l4_pmstop2 + * Name: stm32_pmstop2 * * Description: * Enter STOP2 mode. @@ -145,12 +145,12 @@ int stm32l4_pmstop(bool lpds) * ****************************************************************************/ -int stm32l4_pmstop2(void) +int stm32_pmstop2(void) { uint32_t regval; - regval = getreg32(STM32L4_PWR_CR1); -#ifdef CONFIG_STM32L4_SRAM3_HEAP + regval = getreg32(STM32_PWR_CR1); +#ifdef CONFIG_STM32_SRAM3_HEAP /* SRAM3 is used as heap, so it must not be powered off in Stop 2 mode. */ regval |= PWR_CR1_RRSTP; @@ -160,7 +160,7 @@ int stm32l4_pmstop2(void) regval &= ~PWR_CR1_LPMS_MASK; regval |= PWR_CR1_LPMS_STOP2; - putreg32(regval, STM32L4_PWR_CR1); + putreg32(regval, STM32_PWR_CR1); return do_stop(); } diff --git a/arch/arm/src/stm32l4/stm32l4_pulsecount.c b/arch/arm/src/stm32l4/stm32l4_pulsecount.c index 08807a2334e21..14704082eb707 100644 --- a/arch/arm/src/stm32l4/stm32l4_pulsecount.c +++ b/arch/arm/src/stm32l4/stm32l4_pulsecount.c @@ -39,14 +39,14 @@ #include "arm_internal.h" #include "chip.h" #include "stm32l4_pulsecount.h" -#include "stm32l4.h" +#include "stm32.h" #include "stm32l4_tim.h" /* This module then only compiles if there is at least one enabled timer * intended for use with the pulsecount upper half driver. */ -#if defined(CONFIG_STM32L4_TIM1_PULSECOUNT) || defined(CONFIG_STM32L4_TIM8_PULSECOUNT) +#if defined(CONFIG_STM32_TIM1_PULSECOUNT) || defined(CONFIG_STM32_TIM8_PULSECOUNT) /**************************************************************************** * Pre-processor Definitions @@ -66,7 +66,7 @@ /* Debug ********************************************************************/ #ifdef CONFIG_DEBUG_TIMER_INFO -# define pulsecount_dumpgpio(p,m) stm32l4_dumpgpio(p,m) +# define pulsecount_dumpgpio(p,m) stm32_dumpgpio(p,m) #else # define pulsecount_dumpgpio(p,m) #endif @@ -77,7 +77,7 @@ /* Pulsecount output configuration */ -struct stm32l4_out_s +struct stm32_out_s { uint8_t in_use:1; uint8_t pol:1; @@ -88,17 +88,17 @@ struct stm32l4_out_s /* Pulsecount channel configuration */ -struct stm32l4_chan_s +struct stm32_chan_s { uint8_t channel; - struct stm32l4_out_s out1; + struct stm32_out_s out1; }; /* This structure represents the state of one pulsecount timer */ -struct stm32l4_tim_s +struct stm32_tim_s { - struct stm32l4_chan_s channel; + struct stm32_chan_s channel; uint8_t timid:5; uint8_t timtype:3; uint8_t t_dts:3; @@ -113,10 +113,10 @@ struct stm32l4_tim_s void *handle; }; -struct stm32l4_pulsecount_s +struct stm32_pulsecount_s { const struct pulsecount_ops_s *ops; - struct stm32l4_tim_s *timer; + struct stm32_tim_s *timer; }; /**************************************************************************** @@ -125,10 +125,10 @@ struct stm32l4_pulsecount_s /* Register access */ -static uint16_t pulsecount_getreg(struct stm32l4_tim_s *priv, int offset); -static void pulsecount_putreg(struct stm32l4_tim_s *priv, int offset, +static uint16_t pulsecount_getreg(struct stm32_tim_s *priv, int offset); +static void pulsecount_putreg(struct stm32_tim_s *priv, int offset, uint16_t value); -static void pulsecount_modifyreg(struct stm32l4_tim_s *priv, uint32_t offset, +static void pulsecount_modifyreg(struct stm32_tim_s *priv, uint32_t offset, uint32_t clearbits, uint32_t setbits); #ifdef CONFIG_DEBUG_TIMER_INFO @@ -146,11 +146,11 @@ static int pulsecount_duty_update(struct pulsecount_lowerhalf_s *dev, uint8_t channel, ub16_t duty); static int pulsecount_frequency_update(struct pulsecount_lowerhalf_s *dev, uint32_t frequency); -static int pulsecount_timer_configure(struct stm32l4_tim_s *priv); +static int pulsecount_timer_configure(struct stm32_tim_s *priv); static int pulsecount_channel_configure(struct pulsecount_lowerhalf_s *dev, uint8_t channel); -static int pulsecount_output_configure(struct stm32l4_tim_s *priv, - struct stm32l4_chan_s *chan); +static int pulsecount_output_configure(struct stm32_tim_s *priv, + struct stm32_chan_s *chan); static int pulsecount_outputs_enable(struct pulsecount_lowerhalf_s *dev, uint16_t outputs, bool state); static void pulsecount_moe_enable(struct pulsecount_lowerhalf_s *dev, @@ -159,10 +159,10 @@ static int pulsecount_configure(struct pulsecount_lowerhalf_s *dev); static int pulsecount_timer(struct pulsecount_lowerhalf_s *dev, const struct pulsecount_info_s *info); static int pulsecount_interrupt(struct pulsecount_lowerhalf_s *dev); -# ifdef CONFIG_STM32L4_TIM1_PULSECOUNT +# ifdef CONFIG_STM32_TIM1_PULSECOUNT static int pulsecount_tim1interrupt(int irq, void *context, void *arg); # endif -# ifdef CONFIG_STM32L4_TIM8_PULSECOUNT +# ifdef CONFIG_STM32_TIM8_PULSECOUNT static int pulsecount_tim8interrupt(int irq, void *context, void *arg); # endif static uint8_t pulsecount_count(uint32_t count); @@ -189,107 +189,107 @@ static int pulsecount_ioctl(struct pulsecount_lowerhalf_s *dev, * Private Data ****************************************************************************/ -#ifdef CONFIG_STM32L4_TIM1_PULSECOUNT +#ifdef CONFIG_STM32_TIM1_PULSECOUNT -static struct stm32l4_tim_s g_pulsecount1dev = +static struct stm32_tim_s g_pulsecount1dev = { .channel = { - .channel = CONFIG_STM32L4_TIM1_PULSECOUNT_CHANNEL, -#if CONFIG_STM32L4_TIM1_PULSECOUNT_CHANNEL == 1 + .channel = CONFIG_STM32_TIM1_PULSECOUNT_CHANNEL, +#if CONFIG_STM32_TIM1_PULSECOUNT_CHANNEL == 1 .out1 = { .in_use = 1, - .pol = CONFIG_STM32L4_TIM1_PULSECOUNT_POL, - .idle = CONFIG_STM32L4_TIM1_PULSECOUNT_IDLE, + .pol = CONFIG_STM32_TIM1_PULSECOUNT_POL, + .idle = CONFIG_STM32_TIM1_PULSECOUNT_IDLE, .pincfg = GPIO_TIM1_CH1OUT, }, -#elif CONFIG_STM32L4_TIM1_PULSECOUNT_CHANNEL == 2 +#elif CONFIG_STM32_TIM1_PULSECOUNT_CHANNEL == 2 .out1 = { .in_use = 1, - .pol = CONFIG_STM32L4_TIM1_PULSECOUNT_POL, - .idle = CONFIG_STM32L4_TIM1_PULSECOUNT_IDLE, + .pol = CONFIG_STM32_TIM1_PULSECOUNT_POL, + .idle = CONFIG_STM32_TIM1_PULSECOUNT_IDLE, .pincfg = GPIO_TIM1_CH2OUT, }, -#elif CONFIG_STM32L4_TIM1_PULSECOUNT_CHANNEL == 3 +#elif CONFIG_STM32_TIM1_PULSECOUNT_CHANNEL == 3 .out1 = { .in_use = 1, - .pol = CONFIG_STM32L4_TIM1_PULSECOUNT_POL, - .idle = CONFIG_STM32L4_TIM1_PULSECOUNT_IDLE, + .pol = CONFIG_STM32_TIM1_PULSECOUNT_POL, + .idle = CONFIG_STM32_TIM1_PULSECOUNT_IDLE, .pincfg = GPIO_TIM1_CH3OUT, }, -#elif CONFIG_STM32L4_TIM1_PULSECOUNT_CHANNEL == 4 +#elif CONFIG_STM32_TIM1_PULSECOUNT_CHANNEL == 4 .out1 = { .in_use = 1, - .pol = CONFIG_STM32L4_TIM1_PULSECOUNT_POL, - .idle = CONFIG_STM32L4_TIM1_PULSECOUNT_IDLE, + .pol = CONFIG_STM32_TIM1_PULSECOUNT_POL, + .idle = CONFIG_STM32_TIM1_PULSECOUNT_IDLE, .pincfg = GPIO_TIM1_CH4OUT, }, #endif }, .timid = 1, .timtype = TIMTYPE_TIM1, - .t_dts = CONFIG_STM32L4_TIM1_PULSECOUNT_TDTS, - .irq = STM32L4_IRQ_TIM1UP, - .base = STM32L4_TIM1_BASE, - .pclk = STM32L4_APB2_TIM1_CLKIN, + .t_dts = CONFIG_STM32_TIM1_PULSECOUNT_TDTS, + .irq = STM32_IRQ_TIM1UP, + .base = STM32_TIM1_BASE, + .pclk = STM32_APB2_TIM1_CLKIN, }; -#endif /* CONFIG_STM32L4_TIM1_PULSECOUNT */ +#endif /* CONFIG_STM32_TIM1_PULSECOUNT */ -#ifdef CONFIG_STM32L4_TIM8_PULSECOUNT +#ifdef CONFIG_STM32_TIM8_PULSECOUNT -static struct stm32l4_tim_s g_pulsecount8dev = +static struct stm32_tim_s g_pulsecount8dev = { .channel = { - .channel = CONFIG_STM32L4_TIM8_PULSECOUNT_CHANNEL, -#if CONFIG_STM32L4_TIM8_PULSECOUNT_CHANNEL == 1 + .channel = CONFIG_STM32_TIM8_PULSECOUNT_CHANNEL, +#if CONFIG_STM32_TIM8_PULSECOUNT_CHANNEL == 1 .out1 = { .in_use = 1, - .pol = CONFIG_STM32L4_TIM8_PULSECOUNT_POL, - .idle = CONFIG_STM32L4_TIM8_PULSECOUNT_IDLE, + .pol = CONFIG_STM32_TIM8_PULSECOUNT_POL, + .idle = CONFIG_STM32_TIM8_PULSECOUNT_IDLE, .pincfg = GPIO_TIM8_CH1OUT, }, -#elif CONFIG_STM32L4_TIM8_PULSECOUNT_CHANNEL == 2 +#elif CONFIG_STM32_TIM8_PULSECOUNT_CHANNEL == 2 .out1 = { .in_use = 1, - .pol = CONFIG_STM32L4_TIM8_PULSECOUNT_POL, - .idle = CONFIG_STM32L4_TIM8_PULSECOUNT_IDLE, + .pol = CONFIG_STM32_TIM8_PULSECOUNT_POL, + .idle = CONFIG_STM32_TIM8_PULSECOUNT_IDLE, .pincfg = GPIO_TIM8_CH2OUT, }, -#elif CONFIG_STM32L4_TIM8_PULSECOUNT_CHANNEL == 3 +#elif CONFIG_STM32_TIM8_PULSECOUNT_CHANNEL == 3 .out1 = { .in_use = 1, - .pol = CONFIG_STM32L4_TIM8_PULSECOUNT_POL, - .idle = CONFIG_STM32L4_TIM8_PULSECOUNT_IDLE, + .pol = CONFIG_STM32_TIM8_PULSECOUNT_POL, + .idle = CONFIG_STM32_TIM8_PULSECOUNT_IDLE, .pincfg = GPIO_TIM8_CH3OUT, }, -#elif CONFIG_STM32L4_TIM8_PULSECOUNT_CHANNEL == 4 +#elif CONFIG_STM32_TIM8_PULSECOUNT_CHANNEL == 4 .out1 = { .in_use = 1, - .pol = CONFIG_STM32L4_TIM8_PULSECOUNT_POL, - .idle = CONFIG_STM32L4_TIM8_PULSECOUNT_IDLE, + .pol = CONFIG_STM32_TIM8_PULSECOUNT_POL, + .idle = CONFIG_STM32_TIM8_PULSECOUNT_IDLE, .pincfg = GPIO_TIM8_CH4OUT, }, #endif }, .timid = 8, .timtype = TIMTYPE_TIM8, - .t_dts = CONFIG_STM32L4_TIM8_PULSECOUNT_TDTS, - .irq = STM32L4_IRQ_TIM8UP, - .base = STM32L4_TIM8_BASE, - .pclk = STM32L4_APB2_TIM8_CLKIN, + .t_dts = CONFIG_STM32_TIM8_PULSECOUNT_TDTS, + .irq = STM32_IRQ_TIM8UP, + .base = STM32_TIM8_BASE, + .pclk = STM32_APB2_TIM8_CLKIN, }; -#endif /* CONFIG_STM32L4_TIM8_PULSECOUNT */ +#endif /* CONFIG_STM32_TIM8_PULSECOUNT */ static const struct pulsecount_ops_s g_pulsecountops = { @@ -300,16 +300,16 @@ static const struct pulsecount_ops_s g_pulsecountops = .ioctl = pulsecount_ioctl, }; -#ifdef CONFIG_STM32L4_TIM1_PULSECOUNT -static struct stm32l4_pulsecount_s g_pulsecount1lower = +#ifdef CONFIG_STM32_TIM1_PULSECOUNT +static struct stm32_pulsecount_s g_pulsecount1lower = { .ops = &g_pulsecountops, .timer = &g_pulsecount1dev, }; #endif -#ifdef CONFIG_STM32L4_TIM8_PULSECOUNT -static struct stm32l4_pulsecount_s g_pulsecount8lower = +#ifdef CONFIG_STM32_TIM8_PULSECOUNT +static struct stm32_pulsecount_s g_pulsecount8lower = { .ops = &g_pulsecountops, .timer = &g_pulsecount8dev, @@ -335,7 +335,7 @@ static struct stm32l4_pulsecount_s g_pulsecount8lower = * ****************************************************************************/ -static uint16_t pulsecount_getreg(struct stm32l4_tim_s *priv, int offset) +static uint16_t pulsecount_getreg(struct stm32_tim_s *priv, int offset) { return getreg16(priv->base + offset); } @@ -355,7 +355,7 @@ static uint16_t pulsecount_getreg(struct stm32l4_tim_s *priv, int offset) * ****************************************************************************/ -static void pulsecount_putreg(struct stm32l4_tim_s *priv, int offset, +static void pulsecount_putreg(struct stm32_tim_s *priv, int offset, uint16_t value) { putreg16(value, priv->base + offset); @@ -378,7 +378,7 @@ static void pulsecount_putreg(struct stm32l4_tim_s *priv, int offset, * ****************************************************************************/ -static void pulsecount_modifyreg(struct stm32l4_tim_s *priv, uint32_t offset, +static void pulsecount_modifyreg(struct stm32_tim_s *priv, uint32_t offset, uint32_t clearbits, uint32_t setbits) { modifyreg16(priv->base + offset, (uint16_t)clearbits, @@ -403,34 +403,34 @@ static void pulsecount_modifyreg(struct stm32l4_tim_s *priv, uint32_t offset, static void pulsecount_dumpregs(struct pulsecount_lowerhalf_s *dev, const char *msg) { - struct stm32l4_tim_s *priv = (struct stm32l4_tim_s *)dev; + struct stm32_tim_s *priv = (struct stm32_tim_s *)dev; _info("%s:\n", msg); _info(" CR1: %04x CR2: %04x SMCR: %04x DIER: %04x\n", - pulsecount_getreg(priv, STM32L4_GTIM_CR1_OFFSET), - pulsecount_getreg(priv, STM32L4_GTIM_CR2_OFFSET), - pulsecount_getreg(priv, STM32L4_GTIM_SMCR_OFFSET), - pulsecount_getreg(priv, STM32L4_GTIM_DIER_OFFSET)); + pulsecount_getreg(priv, STM32_GTIM_CR1_OFFSET), + pulsecount_getreg(priv, STM32_GTIM_CR2_OFFSET), + pulsecount_getreg(priv, STM32_GTIM_SMCR_OFFSET), + pulsecount_getreg(priv, STM32_GTIM_DIER_OFFSET)); _info(" SR: %04x EGR: %04x CCMR1: %04x CCMR2: %04x\n", - pulsecount_getreg(priv, STM32L4_GTIM_SR_OFFSET), - pulsecount_getreg(priv, STM32L4_GTIM_EGR_OFFSET), - pulsecount_getreg(priv, STM32L4_GTIM_CCMR1_OFFSET), - pulsecount_getreg(priv, STM32L4_GTIM_CCMR2_OFFSET)); + pulsecount_getreg(priv, STM32_GTIM_SR_OFFSET), + pulsecount_getreg(priv, STM32_GTIM_EGR_OFFSET), + pulsecount_getreg(priv, STM32_GTIM_CCMR1_OFFSET), + pulsecount_getreg(priv, STM32_GTIM_CCMR2_OFFSET)); _info(" CCER: %04x CNT: %04x PSC: %04x ARR: %04x\n", - pulsecount_getreg(priv, STM32L4_GTIM_CCER_OFFSET), - pulsecount_getreg(priv, STM32L4_GTIM_CNT_OFFSET), - pulsecount_getreg(priv, STM32L4_GTIM_PSC_OFFSET), - pulsecount_getreg(priv, STM32L4_GTIM_ARR_OFFSET)); + pulsecount_getreg(priv, STM32_GTIM_CCER_OFFSET), + pulsecount_getreg(priv, STM32_GTIM_CNT_OFFSET), + pulsecount_getreg(priv, STM32_GTIM_PSC_OFFSET), + pulsecount_getreg(priv, STM32_GTIM_ARR_OFFSET)); _info(" CCR1: %04x CCR2: %04x CCR3: %04x CCR4: %04x\n", - pulsecount_getreg(priv, STM32L4_GTIM_CCR1_OFFSET), - pulsecount_getreg(priv, STM32L4_GTIM_CCR2_OFFSET), - pulsecount_getreg(priv, STM32L4_GTIM_CCR3_OFFSET), - pulsecount_getreg(priv, STM32L4_GTIM_CCR4_OFFSET)); + pulsecount_getreg(priv, STM32_GTIM_CCR1_OFFSET), + pulsecount_getreg(priv, STM32_GTIM_CCR2_OFFSET), + pulsecount_getreg(priv, STM32_GTIM_CCR3_OFFSET), + pulsecount_getreg(priv, STM32_GTIM_CCR4_OFFSET)); _info(" RCR: %04x BDTR: %04x DCR: %04x DMAR: %04x\n", - pulsecount_getreg(priv, STM32L4_ATIM_RCR_OFFSET), - pulsecount_getreg(priv, STM32L4_ATIM_BDTR_OFFSET), - pulsecount_getreg(priv, STM32L4_ATIM_DCR_OFFSET), - pulsecount_getreg(priv, STM32L4_ATIM_DMAR_OFFSET)); + pulsecount_getreg(priv, STM32_ATIM_RCR_OFFSET), + pulsecount_getreg(priv, STM32_ATIM_BDTR_OFFSET), + pulsecount_getreg(priv, STM32_ATIM_DCR_OFFSET), + pulsecount_getreg(priv, STM32_ATIM_DMAR_OFFSET)); } #endif @@ -441,7 +441,7 @@ static void pulsecount_dumpregs(struct pulsecount_lowerhalf_s *dev, static int pulsecount_ccr_update(struct pulsecount_lowerhalf_s *dev, uint8_t index, uint32_t ccr) { - struct stm32l4_tim_s *priv = (struct stm32l4_tim_s *)dev; + struct stm32_tim_s *priv = (struct stm32_tim_s *)dev; uint32_t offset = 0; /* CCR channel indices are one-based to match timer channel numbers. */ @@ -450,25 +450,25 @@ static int pulsecount_ccr_update(struct pulsecount_lowerhalf_s *dev, { case 1: { - offset = STM32L4_GTIM_CCR1_OFFSET; + offset = STM32_GTIM_CCR1_OFFSET; break; } case 2: { - offset = STM32L4_GTIM_CCR2_OFFSET; + offset = STM32_GTIM_CCR2_OFFSET; break; } case 3: { - offset = STM32L4_GTIM_CCR3_OFFSET; + offset = STM32_GTIM_CCR3_OFFSET; break; } case 4: { - offset = STM32L4_GTIM_CCR4_OFFSET; + offset = STM32_GTIM_CCR4_OFFSET; break; } @@ -505,7 +505,7 @@ static int pulsecount_ccr_update(struct pulsecount_lowerhalf_s *dev, static int pulsecount_duty_update(struct pulsecount_lowerhalf_s *dev, uint8_t channel, ub16_t duty) { - struct stm32l4_tim_s *priv = (struct stm32l4_tim_s *)dev; + struct stm32_tim_s *priv = (struct stm32_tim_s *)dev; uint32_t reload = 0; uint32_t ccr = 0; @@ -520,7 +520,7 @@ static int pulsecount_duty_update(struct pulsecount_lowerhalf_s *dev, /* Get the reload values */ - reload = pulsecount_getreg(priv, STM32L4_GTIM_ARR_OFFSET); + reload = pulsecount_getreg(priv, STM32_GTIM_ARR_OFFSET); /* Duty cycle: * @@ -547,7 +547,7 @@ static int pulsecount_duty_update(struct pulsecount_lowerhalf_s *dev, static int pulsecount_frequency_update(struct pulsecount_lowerhalf_s *dev, uint32_t frequency) { - struct stm32l4_tim_s *priv = (struct stm32l4_tim_s *)dev; + struct stm32_tim_s *priv = (struct stm32_tim_s *)dev; uint32_t reload = 0; uint32_t timclk = 0; uint32_t prescaler = 0; @@ -617,8 +617,8 @@ static int pulsecount_frequency_update(struct pulsecount_lowerhalf_s *dev, /* Set the reload and prescaler values */ - pulsecount_putreg(priv, STM32L4_GTIM_ARR_OFFSET, reload); - pulsecount_putreg(priv, STM32L4_GTIM_PSC_OFFSET, + pulsecount_putreg(priv, STM32_GTIM_ARR_OFFSET, reload); + pulsecount_putreg(priv, STM32_GTIM_PSC_OFFSET, (uint16_t)(prescaler - 1)); return OK; @@ -632,13 +632,13 @@ static int pulsecount_frequency_update(struct pulsecount_lowerhalf_s *dev, * ****************************************************************************/ -static int pulsecount_timer_configure(struct stm32l4_tim_s *priv) +static int pulsecount_timer_configure(struct stm32_tim_s *priv) { uint16_t cr1 = 0; /* Set up the advanced timer CR1 register. */ - cr1 = pulsecount_getreg(priv, STM32L4_GTIM_CR1_OFFSET); + cr1 = pulsecount_getreg(priv, STM32_GTIM_CR1_OFFSET); /* Pulsecount always uses edge-aligned up-counting mode. */ @@ -653,7 +653,7 @@ static int pulsecount_timer_configure(struct stm32l4_tim_s *priv) /* Write CR1 */ - pulsecount_putreg(priv, STM32L4_GTIM_CR1_OFFSET, cr1); + pulsecount_putreg(priv, STM32_GTIM_CR1_OFFSET, cr1); return OK; } @@ -669,7 +669,7 @@ static int pulsecount_timer_configure(struct stm32l4_tim_s *priv) static int pulsecount_channel_configure(struct pulsecount_lowerhalf_s *dev, uint8_t channel) { - struct stm32l4_tim_s *priv = (struct stm32l4_tim_s *)dev; + struct stm32_tim_s *priv = (struct stm32_tim_s *)dev; uint32_t chanmode = 0; uint32_t ocmode = 0; uint32_t ccmr = 0; @@ -689,14 +689,14 @@ static int pulsecount_channel_configure(struct pulsecount_lowerhalf_s *dev, case 1: case 2: { - offset = STM32L4_GTIM_CCMR1_OFFSET; + offset = STM32_GTIM_CCMR1_OFFSET; break; } case 3: case 4: { - offset = STM32L4_GTIM_CCMR2_OFFSET; + offset = STM32_GTIM_CCMR2_OFFSET; break; } @@ -765,7 +765,7 @@ static int pulsecount_channel_configure(struct pulsecount_lowerhalf_s *dev, * ****************************************************************************/ -static int pulsecount_output_configure(struct stm32l4_tim_s *priv, +static int pulsecount_output_configure(struct stm32_tim_s *priv, uint8_t channel) { uint32_t cr2 = 0; @@ -773,8 +773,8 @@ static int pulsecount_output_configure(struct stm32l4_tim_s *priv, /* Get current registers state */ - cr2 = pulsecount_getreg(priv, STM32L4_GTIM_CR2_OFFSET); - ccer = pulsecount_getreg(priv, STM32L4_GTIM_CCER_OFFSET); + cr2 = pulsecount_getreg(priv, STM32_GTIM_CR2_OFFSET); + ccer = pulsecount_getreg(priv, STM32_GTIM_CCER_OFFSET); /* | OISx | IDLE | advanced timers | CR2 register * | CCxP | POL | all pulsecount timers | CCER register @@ -807,8 +807,8 @@ static int pulsecount_output_configure(struct stm32l4_tim_s *priv, /* Write registers */ - pulsecount_modifyreg(priv, STM32L4_GTIM_CR2_OFFSET, 0, cr2); - pulsecount_modifyreg(priv, STM32L4_GTIM_CCER_OFFSET, 0, ccer); + pulsecount_modifyreg(priv, STM32_GTIM_CR2_OFFSET, 0, cr2); + pulsecount_modifyreg(priv, STM32_GTIM_CCER_OFFSET, 0, ccer); return OK; } @@ -824,7 +824,7 @@ static int pulsecount_output_configure(struct stm32l4_tim_s *priv, * * Input Parameters: * dev - A reference to the lower half driver state structure - * outputs - outputs to set (look at enum stm32l4_pulsecount_chan_e) + * outputs - outputs to set (look at enum stm32_pulsecount_chan_e) * state - Enable/disable operation * ****************************************************************************/ @@ -832,13 +832,13 @@ static int pulsecount_output_configure(struct stm32l4_tim_s *priv, static int pulsecount_outputs_enable(struct pulsecount_lowerhalf_s *dev, uint16_t outputs, bool state) { - struct stm32l4_tim_s *priv = (struct stm32l4_tim_s *)dev; + struct stm32_tim_s *priv = (struct stm32_tim_s *)dev; uint32_t ccer = 0; uint32_t regval = 0; /* Get current register state */ - ccer = pulsecount_getreg(priv, STM32L4_GTIM_CCER_OFFSET); + ccer = pulsecount_getreg(priv, STM32_GTIM_CCER_OFFSET); /* Get outputs configuration */ @@ -865,7 +865,7 @@ static int pulsecount_outputs_enable(struct pulsecount_lowerhalf_s *dev, /* Write register */ - pulsecount_putreg(priv, STM32L4_GTIM_CCER_OFFSET, ccer); + pulsecount_putreg(priv, STM32_GTIM_CCER_OFFSET, ccer); return OK; } @@ -877,15 +877,15 @@ static int pulsecount_outputs_enable(struct pulsecount_lowerhalf_s *dev, static void pulsecount_moe_enable(struct pulsecount_lowerhalf_s *dev, bool enable) { - struct stm32l4_tim_s *priv = (struct stm32l4_tim_s *)dev; + struct stm32_tim_s *priv = (struct stm32_tim_s *)dev; if (enable) { - pulsecount_modifyreg(priv, STM32L4_ATIM_BDTR_OFFSET, 0, ATIM_BDTR_MOE); + pulsecount_modifyreg(priv, STM32_ATIM_BDTR_OFFSET, 0, ATIM_BDTR_MOE); } else { - pulsecount_modifyreg(priv, STM32L4_ATIM_BDTR_OFFSET, ATIM_BDTR_MOE, 0); + pulsecount_modifyreg(priv, STM32_ATIM_BDTR_OFFSET, ATIM_BDTR_MOE, 0); } } @@ -898,7 +898,7 @@ static void pulsecount_moe_enable(struct pulsecount_lowerhalf_s *dev, ****************************************************************************/ static uint16_t -pulsecount_outputs_from_channels(struct stm32l4_tim_s *priv, +pulsecount_outputs_from_channels(struct stm32_tim_s *priv, uint8_t selected) { uint16_t outputs = 0; @@ -925,7 +925,7 @@ pulsecount_outputs_from_channels(struct stm32l4_tim_s *priv, static int pulsecount_configure(struct pulsecount_lowerhalf_s *dev) { - struct stm32l4_tim_s *priv = (struct stm32l4_tim_s *)dev; + struct stm32_tim_s *priv = (struct stm32_tim_s *)dev; uint16_t outputs = 0; int ret = OK; @@ -933,7 +933,7 @@ static int pulsecount_configure(struct pulsecount_lowerhalf_s *dev) /* Disable the timer until we get it configured */ - pulsecount_modifyreg(priv, STM32L4_GTIM_CR1_OFFSET, GTIM_CR1_CEN, 0); + pulsecount_modifyreg(priv, STM32_GTIM_CR1_OFFSET, GTIM_CR1_CEN, 0); /* Get configured outputs */ @@ -991,7 +991,7 @@ static int pulsecount_configure(struct pulsecount_lowerhalf_s *dev) static int pulsecount_timer(struct pulsecount_lowerhalf_s *dev, const struct pulsecount_info_s *info) { - struct stm32l4_tim_s *priv = (struct stm32l4_tim_s *)dev; + struct stm32_tim_s *priv = (struct stm32_tim_s *)dev; ub16_t duty = 0; uint8_t channel = 0; uint16_t outputs = 0; @@ -1015,8 +1015,8 @@ static int pulsecount_timer(struct pulsecount_lowerhalf_s *dev, /* Disable all interrupts and DMA requests, clear all pending status */ - pulsecount_putreg(priv, STM32L4_GTIM_DIER_OFFSET, 0); - pulsecount_putreg(priv, STM32L4_GTIM_SR_OFFSET, 0); + pulsecount_putreg(priv, STM32_GTIM_DIER_OFFSET, 0); + pulsecount_putreg(priv, STM32_GTIM_SR_OFFSET, 0); /* Set timer frequency */ @@ -1051,14 +1051,14 @@ static int pulsecount_timer(struct pulsecount_lowerhalf_s *dev, */ priv->prev = pulsecount_count(info->count); - pulsecount_putreg(priv, STM32L4_GTIM_RCR_OFFSET, + pulsecount_putreg(priv, STM32_GTIM_RCR_OFFSET, (uint16_t)priv->prev - 1); /* Generate an update event to reload the prescaler. This should * preload the RCR into active repetition counter. */ - pulsecount_putreg(priv, STM32L4_GTIM_EGR_OFFSET, GTIM_EGR_UG); + pulsecount_putreg(priv, STM32_GTIM_EGR_OFFSET, GTIM_EGR_UG); /* Now set the value of the RCR that will be loaded on the next * update event. @@ -1066,7 +1066,7 @@ static int pulsecount_timer(struct pulsecount_lowerhalf_s *dev, priv->count = info->count; priv->curr = pulsecount_count(info->count - priv->prev); - pulsecount_putreg(priv, STM32L4_GTIM_RCR_OFFSET, + pulsecount_putreg(priv, STM32_GTIM_RCR_OFFSET, (uint16_t)priv->curr - 1); } @@ -1076,11 +1076,11 @@ static int pulsecount_timer(struct pulsecount_lowerhalf_s *dev, { /* Set the repetition counter to zero */ - pulsecount_putreg(priv, STM32L4_GTIM_RCR_OFFSET, 0); + pulsecount_putreg(priv, STM32_GTIM_RCR_OFFSET, 0); /* Generate an update event to reload the prescaler */ - pulsecount_putreg(priv, STM32L4_GTIM_EGR_OFFSET, GTIM_EGR_UG); + pulsecount_putreg(priv, STM32_GTIM_EGR_OFFSET, GTIM_EGR_UG); } /* Get configured outputs */ @@ -1105,12 +1105,12 @@ static int pulsecount_timer(struct pulsecount_lowerhalf_s *dev, { /* Clear all pending interrupts and enable the update interrupt. */ - pulsecount_putreg(priv, STM32L4_GTIM_SR_OFFSET, 0); - pulsecount_putreg(priv, STM32L4_GTIM_DIER_OFFSET, GTIM_DIER_UIE); + pulsecount_putreg(priv, STM32_GTIM_SR_OFFSET, 0); + pulsecount_putreg(priv, STM32_GTIM_DIER_OFFSET, GTIM_DIER_UIE); /* Enable the timer */ - pulsecount_modifyreg(priv, STM32L4_GTIM_CR1_OFFSET, 0, GTIM_CR1_CEN); + pulsecount_modifyreg(priv, STM32_GTIM_CR1_OFFSET, 0, GTIM_CR1_CEN); /* And enable timer interrupts at the NVIC */ @@ -1139,17 +1139,17 @@ static int pulsecount_timer(struct pulsecount_lowerhalf_s *dev, static int pulsecount_interrupt(struct pulsecount_lowerhalf_s *dev) { - struct stm32l4_tim_s *priv = (struct stm32l4_tim_s *)dev; + struct stm32_tim_s *priv = (struct stm32_tim_s *)dev; uint16_t regval; /* Verify that this is an update interrupt. Nothing else is expected. */ - regval = pulsecount_getreg(priv, STM32L4_ATIM_SR_OFFSET); + regval = pulsecount_getreg(priv, STM32_ATIM_SR_OFFSET); DEBUGASSERT((regval & ATIM_SR_UIF) != 0); /* Clear the UIF interrupt bit */ - pulsecount_putreg(priv, STM32L4_ATIM_SR_OFFSET, regval & ~ATIM_SR_UIF); + pulsecount_putreg(priv, STM32_ATIM_SR_OFFSET, regval & ~ATIM_SR_UIF); /* Calculate the new count by subtracting the number of pulses * since the last interrupt. @@ -1161,9 +1161,9 @@ static int pulsecount_interrupt(struct pulsecount_lowerhalf_s *dev) * quickly as possible. */ - regval = pulsecount_getreg(priv, STM32L4_ATIM_BDTR_OFFSET); + regval = pulsecount_getreg(priv, STM32_ATIM_BDTR_OFFSET); regval &= ~ATIM_BDTR_MOE; - pulsecount_putreg(priv, STM32L4_ATIM_BDTR_OFFSET, regval); + pulsecount_putreg(priv, STM32_ATIM_BDTR_OFFSET, regval); /* Disable first interrupts, stop and reset the timer */ @@ -1194,7 +1194,7 @@ static int pulsecount_interrupt(struct pulsecount_lowerhalf_s *dev) priv->prev = priv->curr; priv->curr = pulsecount_count(priv->count - priv->prev); - pulsecount_putreg(priv, STM32L4_ATIM_RCR_OFFSET, + pulsecount_putreg(priv, STM32_ATIM_RCR_OFFSET, (uint16_t)priv->curr - 1); } @@ -1224,21 +1224,21 @@ static int pulsecount_interrupt(struct pulsecount_lowerhalf_s *dev) * ****************************************************************************/ -#ifdef CONFIG_STM32L4_TIM1_PULSECOUNT +#ifdef CONFIG_STM32_TIM1_PULSECOUNT static int pulsecount_tim1interrupt(int irq, void *context, void *arg) { return pulsecount_interrupt((struct pulsecount_lowerhalf_s *) &g_pulsecount1dev); } -#endif /* CONFIG_STM32L4_TIM1_PULSECOUNT */ +#endif /* CONFIG_STM32_TIM1_PULSECOUNT */ -#ifdef CONFIG_STM32L4_TIM8_PULSECOUNT +#ifdef CONFIG_STM32_TIM8_PULSECOUNT static int pulsecount_tim8interrupt(int irq, void *context, void *arg) { return pulsecount_interrupt((struct pulsecount_lowerhalf_s *) &g_pulsecount8dev); } -#endif /* CONFIG_STM32L4_TIM8_PULSECOUNT */ +#endif /* CONFIG_STM32_TIM8_PULSECOUNT */ /**************************************************************************** * Name: pulsecount_count @@ -1297,7 +1297,7 @@ static uint8_t pulsecount_count(uint32_t count) * ****************************************************************************/ -static int pulsecount_setapbclock(struct stm32l4_tim_s *priv, +static int pulsecount_setapbclock(struct stm32_tim_s *priv, bool on) { uint32_t en_bit; @@ -1308,19 +1308,19 @@ static int pulsecount_setapbclock(struct stm32l4_tim_s *priv, switch (priv->timid) { -#ifdef CONFIG_STM32L4_TIM1_PULSECOUNT +#ifdef CONFIG_STM32_TIM1_PULSECOUNT case 1: { - regaddr = STM32L4_RCC_APB2ENR; + regaddr = STM32_RCC_APB2ENR; en_bit = RCC_APB2ENR_TIM1EN; break; } #endif -#ifdef CONFIG_STM32L4_TIM8_PULSECOUNT +#ifdef CONFIG_STM32_TIM8_PULSECOUNT case 8: { - regaddr = STM32L4_RCC_APB2ENR; + regaddr = STM32_RCC_APB2ENR; en_bit = RCC_APB2ENR_TIM8EN; break; } @@ -1371,7 +1371,7 @@ static int pulsecount_setapbclock(struct stm32l4_tim_s *priv, static int pulsecount_ll_setup(struct pulsecount_lowerhalf_s *dev) { - struct stm32l4_tim_s *priv = (struct stm32l4_tim_s *)dev; + struct stm32_tim_s *priv = (struct stm32_tim_s *)dev; uint32_t pincfg; _info("TIM%u\n", priv->timid); @@ -1389,7 +1389,7 @@ static int pulsecount_ll_setup(struct pulsecount_lowerhalf_s *dev) pincfg = priv->channel.out1.pincfg; _info("pincfg: %08" PRIx32 "\n", pincfg); - stm32l4_configgpio(pincfg); + stm32_configgpio(pincfg); pulsecount_dumpgpio(pincfg, "pulsecount setup"); } @@ -1414,7 +1414,7 @@ static int pulsecount_ll_setup(struct pulsecount_lowerhalf_s *dev) static int pulsecount_ll_shutdown(struct pulsecount_lowerhalf_s *dev) { - struct stm32l4_tim_s *priv = (struct stm32l4_tim_s *)dev; + struct stm32_tim_s *priv = (struct stm32_tim_s *)dev; uint32_t pincfg = 0; int ret = OK; @@ -1442,7 +1442,7 @@ static int pulsecount_ll_shutdown(struct pulsecount_lowerhalf_s *dev) pincfg &= (GPIO_PORT_MASK | GPIO_PIN_MASK); pincfg |= GPIO_INPUT | GPIO_FLOAT; - stm32l4_configgpio(pincfg); + stm32_configgpio(pincfg); } errout: @@ -1470,7 +1470,7 @@ static int pulsecount_ll_shutdown(struct pulsecount_lowerhalf_s *dev) static int pulsecount_ll_stop(struct pulsecount_lowerhalf_s *dev) { - struct stm32l4_tim_s *priv = (struct stm32l4_tim_s *)dev; + struct stm32_tim_s *priv = (struct stm32_tim_s *)dev; uint32_t resetbit = 0; uint32_t regaddr; uint32_t regval; @@ -1482,15 +1482,15 @@ static int pulsecount_ll_stop(struct pulsecount_lowerhalf_s *dev) switch (priv->timid) { -#ifdef CONFIG_STM32L4_TIM1_PULSECOUNT +#ifdef CONFIG_STM32_TIM1_PULSECOUNT case 1: - regaddr = STM32L4_RCC_APB2RSTR; + regaddr = STM32_RCC_APB2RSTR; resetbit = RCC_APB2RSTR_TIM1RST; break; #endif -#ifdef CONFIG_STM32L4_TIM8_PULSECOUNT +#ifdef CONFIG_STM32_TIM8_PULSECOUNT case 8: - regaddr = STM32L4_RCC_APB2RSTR; + regaddr = STM32_RCC_APB2RSTR; resetbit = RCC_APB2RSTR_TIM8RST; break; #endif @@ -1506,8 +1506,8 @@ static int pulsecount_ll_stop(struct pulsecount_lowerhalf_s *dev) /* Disable further interrupts and stop the timer */ - pulsecount_putreg(priv, STM32L4_GTIM_DIER_OFFSET, 0); - pulsecount_putreg(priv, STM32L4_GTIM_SR_OFFSET, 0); + pulsecount_putreg(priv, STM32_GTIM_DIER_OFFSET, 0); + pulsecount_putreg(priv, STM32_GTIM_SR_OFFSET, 0); /* Reset the timer - stopping the output and putting the timer back * into a state where pulsecount_start() can be called. @@ -1547,7 +1547,7 @@ static int pulsecount_ll_ioctl(struct pulsecount_lowerhalf_s *dev, int cmd, unsigned long arg) { #ifdef CONFIG_DEBUG_TIMER_INFO - struct stm32l4_tim_s *priv = (struct stm32l4_tim_s *)dev; + struct stm32_tim_s *priv = (struct stm32_tim_s *)dev; /* There are no platform-specific ioctl commands */ @@ -1558,7 +1558,7 @@ static int pulsecount_ll_ioctl(struct pulsecount_lowerhalf_s *dev, int cmd, static int pulsecount_setup(struct pulsecount_lowerhalf_s *dev) { - struct stm32l4_pulsecount_s *pulse = (struct stm32l4_pulsecount_s *)dev; + struct stm32_pulsecount_s *pulse = (struct stm32_pulsecount_s *)dev; int ret; ret = pulsecount_ll_setup((struct pulsecount_lowerhalf_s *)pulse->timer); @@ -1572,7 +1572,7 @@ static int pulsecount_setup(struct pulsecount_lowerhalf_s *dev) static int pulsecount_shutdown(struct pulsecount_lowerhalf_s *dev) { - struct stm32l4_pulsecount_s *pulse = (struct stm32l4_pulsecount_s *)dev; + struct stm32_pulsecount_s *pulse = (struct stm32_pulsecount_s *)dev; return pulsecount_ll_shutdown((struct pulsecount_lowerhalf_s *) pulse->timer); } @@ -1581,8 +1581,8 @@ static int pulsecount_start(struct pulsecount_lowerhalf_s *dev, const struct pulsecount_info_s *info, void *handle) { - struct stm32l4_pulsecount_s *pulse = (struct stm32l4_pulsecount_s *)dev; - struct stm32l4_tim_s *priv = pulse->timer; + struct stm32_pulsecount_s *pulse = (struct stm32_pulsecount_s *)dev; + struct stm32_tim_s *priv = pulse->timer; if (info->count > 0) { @@ -1600,14 +1600,14 @@ static int pulsecount_start(struct pulsecount_lowerhalf_s *dev, static int pulsecount_stop(struct pulsecount_lowerhalf_s *dev) { - struct stm32l4_pulsecount_s *pulse = (struct stm32l4_pulsecount_s *)dev; + struct stm32_pulsecount_s *pulse = (struct stm32_pulsecount_s *)dev; return pulsecount_ll_stop((struct pulsecount_lowerhalf_s *)pulse->timer); } static int pulsecount_ioctl(struct pulsecount_lowerhalf_s *dev, int cmd, unsigned long arg) { - struct stm32l4_pulsecount_s *pulse = (struct stm32l4_pulsecount_s *)dev; + struct stm32_pulsecount_s *pulse = (struct stm32_pulsecount_s *)dev; return pulsecount_ll_ioctl((struct pulsecount_lowerhalf_s *)pulse->timer, cmd, arg); } @@ -1616,15 +1616,15 @@ static int pulsecount_ioctl(struct pulsecount_lowerhalf_s *dev, * Public Functions ****************************************************************************/ -struct pulsecount_lowerhalf_s *stm32l4_pulsecountinitialize(int timer) +struct pulsecount_lowerhalf_s *stm32_pulsecountinitialize(int timer) { - struct stm32l4_pulsecount_s *lower = NULL; + struct stm32_pulsecount_s *lower = NULL; _info("TIM%u\n", timer); switch (timer) { -#ifdef CONFIG_STM32L4_TIM1_PULSECOUNT +#ifdef CONFIG_STM32_TIM1_PULSECOUNT case 1: { lower = &g_pulsecount1lower; @@ -1634,7 +1634,7 @@ struct pulsecount_lowerhalf_s *stm32l4_pulsecountinitialize(int timer) } #endif -#ifdef CONFIG_STM32L4_TIM8_PULSECOUNT +#ifdef CONFIG_STM32_TIM8_PULSECOUNT case 8: { lower = &g_pulsecount8lower; @@ -1654,4 +1654,4 @@ struct pulsecount_lowerhalf_s *stm32l4_pulsecountinitialize(int timer) return (struct pulsecount_lowerhalf_s *)lower; } -#endif /* CONFIG_STM32L4_TIM1_PULSECOUNT || CONFIG_STM32L4_TIM8_PULSECOUNT */ +#endif /* CONFIG_STM32_TIM1_PULSECOUNT || CONFIG_STM32_TIM8_PULSECOUNT */ diff --git a/arch/arm/src/stm32l4/stm32l4_pulsecount.h b/arch/arm/src/stm32l4/stm32l4_pulsecount.h index 8d1a95c595ba9..1e0fd8667a5a7 100644 --- a/arch/arm/src/stm32l4/stm32l4_pulsecount.h +++ b/arch/arm/src/stm32l4/stm32l4_pulsecount.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32L4_STM32L4_PULSECOUNT_H -#define __ARCH_ARM_SRC_STM32L4_STM32L4_PULSECOUNT_H +#ifndef __ARCH_ARM_SRC_STM32L4_STM32_PULSECOUNT_H +#define __ARCH_ARM_SRC_STM32L4_STM32_PULSECOUNT_H /**************************************************************************** * Included Files @@ -34,6 +34,6 @@ * Public Function Prototypes ****************************************************************************/ -struct pulsecount_lowerhalf_s *stm32l4_pulsecountinitialize(int timer); +struct pulsecount_lowerhalf_s *stm32_pulsecountinitialize(int timer); -#endif /* __ARCH_ARM_SRC_STM32L4_STM32L4_PULSECOUNT_H */ +#endif /* __ARCH_ARM_SRC_STM32L4_STM32_PULSECOUNT_H */ diff --git a/arch/arm/src/stm32l4/stm32l4_pwm.c b/arch/arm/src/stm32l4/stm32l4_pwm.c index 46d0aff819376..dabf608f7b6cf 100644 --- a/arch/arm/src/stm32l4/stm32l4_pwm.c +++ b/arch/arm/src/stm32l4/stm32l4_pwm.c @@ -40,18 +40,18 @@ #include "arm_internal.h" #include "chip.h" #include "stm32l4_pwm.h" -#include "stm32l4.h" +#include "stm32.h" /* This module then only compiles if there is at least one enabled timer * intended for use with the PWM upper half driver. */ -#if defined(CONFIG_STM32L4_TIM1_PWM) || defined(CONFIG_STM32L4_TIM2_PWM) || \ - defined(CONFIG_STM32L4_TIM3_PWM) || defined(CONFIG_STM32L4_TIM4_PWM) || \ - defined(CONFIG_STM32L4_TIM5_PWM) || defined(CONFIG_STM32L4_TIM8_PWM) || \ - defined(CONFIG_STM32L4_TIM15_PWM) || defined(CONFIG_STM32L4_TIM16_PWM) || \ - defined(CONFIG_STM32L4_TIM17_PWM) || defined(CONFIG_STM32L4_LPTIM1_PWM) || \ - defined(CONFIG_STM32L4_LPTIM2_PWM) +#if defined(CONFIG_STM32_TIM1_PWM) || defined(CONFIG_STM32_TIM2_PWM) || \ + defined(CONFIG_STM32_TIM3_PWM) || defined(CONFIG_STM32_TIM4_PWM) || \ + defined(CONFIG_STM32_TIM5_PWM) || defined(CONFIG_STM32_TIM8_PWM) || \ + defined(CONFIG_STM32_TIM15_PWM) || defined(CONFIG_STM32_TIM16_PWM) || \ + defined(CONFIG_STM32_TIM17_PWM) || defined(CONFIG_STM32_LPTIM1_PWM) || \ + defined(CONFIG_STM32_LPTIM2_PWM) /**************************************************************************** * Pre-processor Definitions @@ -91,9 +91,9 @@ * supported capture/compare. */ -#if defined(CONFIG_STM32L4_TIM1_PWM) || defined(CONFIG_STM32L4_TIM8_PWM) || \ - defined(CONFIG_STM32L4_TIM15_PWM) || defined(CONFIG_STM32L4_TIM16_PWM) || \ - defined(CONFIG_STM32L4_TIM17_PWM) +#if defined(CONFIG_STM32_TIM1_PWM) || defined(CONFIG_STM32_TIM8_PWM) || \ + defined(CONFIG_STM32_TIM15_PWM) || defined(CONFIG_STM32_TIM16_PWM) || \ + defined(CONFIG_STM32_TIM17_PWM) # define HAVE_ADVTIM #else # undef HAVE_ADVTIM @@ -101,7 +101,7 @@ /* Low power Timer support */ -#if defined(CONFIG_STM32L4_LPTIM1_PWM) || defined(CONFIG_STM32L4_LPTIM2_PWM) +#if defined(CONFIG_STM32_LPTIM1_PWM) || defined(CONFIG_STM32_LPTIM2_PWM) # define HAVE_LPTIM #else # undef HAVE_LPTIM @@ -109,23 +109,23 @@ /* Synchronisation support */ -#ifdef CONFIG_STM32L4_PWM_TRGO +#ifdef CONFIG_STM32_PWM_TRGO # define HAVE_TRGO #endif /* Break support */ -#if defined(CONFIG_STM32L4_TIM1_BREAK1) || defined(CONFIG_STM32L4_TIM1_BREAK2) || \ - defined(CONFIG_STM32L4_TIM8_BREAK1) || defined(CONFIG_STM32L4_TIM8_BREAK2) || \ - defined(CONFIG_STM32L4_TIM15_BREAK1) || defined(CONFIG_STM32L4_TIM16_BREAK1) || \ - defined(CONFIG_STM32L4_TIM17_BREAK1) +#if defined(CONFIG_STM32_TIM1_BREAK1) || defined(CONFIG_STM32_TIM1_BREAK2) || \ + defined(CONFIG_STM32_TIM8_BREAK1) || defined(CONFIG_STM32_TIM8_BREAK2) || \ + defined(CONFIG_STM32_TIM15_BREAK1) || defined(CONFIG_STM32_TIM16_BREAK1) || \ + defined(CONFIG_STM32_TIM17_BREAK1) # defined HAVE_BREAK #endif /* Debug ********************************************************************/ #ifdef CONFIG_DEBUG_PWM_INFO -# define pwm_dumpgpio(p,m) stm32l4_dumpgpio(p,m) +# define pwm_dumpgpio(p,m) stm32_dumpgpio(p,m) #else # define pwm_dumpgpio(p,m) #endif @@ -136,7 +136,7 @@ /* PWM output configuration */ -struct stm32l4_pwm_out_s +struct stm32_pwm_out_s { uint8_t in_use:1; /* Output in use */ uint8_t pol:1; /* Polarity. Default: positive */ @@ -147,33 +147,33 @@ struct stm32l4_pwm_out_s /* PWM channel configuration */ -struct stm32l4_pwmchan_s +struct stm32_pwmchan_s { uint8_t channel:4; /* Timer output channel: {1,..4} */ - uint8_t mode:4; /* PWM channel mode (see stm32l4_pwm_chanmode_e) */ - struct stm32l4_pwm_out_s out1; /* PWM output configuration */ + uint8_t mode:4; /* PWM channel mode (see stm32_pwm_chanmode_e) */ + struct stm32_pwm_out_s out1; /* PWM output configuration */ #ifdef HAVE_BREAK - struct stm32l4_pwm_break_s brk; /* PWM break configuration */ + struct stm32_pwm_break_s brk; /* PWM break configuration */ #endif #ifdef HAVE_PWM_COMPLEMENTARY - struct stm32l4_pwm_out_s out2; /* PWM complementary output configuration */ + struct stm32_pwm_out_s out2; /* PWM complementary output configuration */ #endif }; /* This structure represents the state of one PWM timer */ -struct stm32l4_pwmtimer_s +struct stm32_pwmtimer_s { const struct pwm_ops_s *ops; /* PWM operations */ -#ifdef CONFIG_STM32L4_PWM_LL_OPS - const struct stm32l4_pwm_ops_s *llops; /* Low-level PWM ops */ +#ifdef CONFIG_STM32_PWM_LL_OPS + const struct stm32_pwm_ops_s *llops; /* Low-level PWM ops */ #endif - struct stm32l4_pwmchan_s *channels; /* Channels configuration */ + struct stm32_pwmchan_s *channels; /* Channels configuration */ uint8_t timid:5; /* Timer ID {1,...,17} */ uint8_t chan_num:3; /* Number of configured channels */ uint8_t timtype:3; /* See the TIMTYPE_* definitions */ - uint8_t mode:3; /* Timer mode (see stm32l4_pwm_tim_mode_e) */ + uint8_t mode:3; /* Timer mode (see stm32_pwm_tim_mode_e) */ uint8_t lock:2; /* TODO: Lock configuration */ uint8_t t_dts:3; /* Clock division for t_DTS */ uint8_t _res:5; /* Reserved */ @@ -197,10 +197,10 @@ struct stm32l4_pwmtimer_s /* Register access */ -static uint16_t pwm_getreg(struct stm32l4_pwmtimer_s *priv, int offset); -static void pwm_putreg(struct stm32l4_pwmtimer_s *priv, int offset, +static uint16_t pwm_getreg(struct stm32_pwmtimer_s *priv, int offset); +static void pwm_putreg(struct stm32_pwmtimer_s *priv, int offset, uint16_t value); -static void pwm_modifyreg(struct stm32l4_pwmtimer_s *priv, uint32_t offset, +static void pwm_modifyreg(struct stm32_pwmtimer_s *priv, uint32_t offset, uint32_t clearbits, uint32_t setbits); #ifdef CONFIG_DEBUG_PWM_INFO @@ -226,7 +226,7 @@ static int pwm_ccr_update(struct pwm_lowerhalf_s *dev, uint8_t index, uint32_t ccr); static int pwm_mode_configure(struct pwm_lowerhalf_s *dev, uint8_t channel, uint32_t mode); -#ifdef CONFIG_STM32L4_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS static uint32_t pwm_ccr_get(struct pwm_lowerhalf_s *dev, uint8_t index); #endif static int pwm_arr_update(struct pwm_lowerhalf_s *dev, uint32_t arr); @@ -237,10 +237,10 @@ static int pwm_soft_update(struct pwm_lowerhalf_s *dev); static int pwm_frequency_update(struct pwm_lowerhalf_s *dev, uint32_t frequency); static int pwm_timer_enable(struct pwm_lowerhalf_s *dev, bool state); -#if defined(HAVE_PWM_COMPLEMENTARY) && defined(CONFIG_STM32L4_PWM_LL_OPS) +#if defined(HAVE_PWM_COMPLEMENTARY) && defined(CONFIG_STM32_PWM_LL_OPS) static int pwm_deadtime_update(struct pwm_lowerhalf_s *dev, uint8_t dt); #endif -#ifdef CONFIG_STM32L4_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS static uint32_t pwm_ccr_get(struct pwm_lowerhalf_s *dev, uint8_t index); #endif @@ -273,8 +273,8 @@ static const struct pwm_ops_s g_pwmops = .ioctl = pwm_ioctl, }; -#ifdef CONFIG_STM32L4_PWM_LL_OPS -static const struct stm32l4_pwm_ops_s g_llpwmops = +#ifdef CONFIG_STM32_PWM_LL_OPS +static const struct stm32_pwm_ops_s g_llpwmops = { .configure = pwm_configure, .soft_break = pwm_soft_break, @@ -296,138 +296,138 @@ static const struct stm32l4_pwm_ops_s g_llpwmops = }; #endif -#ifdef CONFIG_STM32L4_TIM1_PWM +#ifdef CONFIG_STM32_TIM1_PWM -static struct stm32l4_pwmchan_s g_pwm1channels[] = +static struct stm32_pwmchan_s g_pwm1channels[] = { /* TIM1 has 4 channels, 4 complementary */ -#ifdef CONFIG_STM32L4_TIM1_CHANNEL1 +#ifdef CONFIG_STM32_TIM1_CHANNEL1 { .channel = 1, - .mode = CONFIG_STM32L4_TIM1_CH1MODE, + .mode = CONFIG_STM32_TIM1_CH1MODE, #ifdef HAVE_BREAK .brk = { -#ifdef CONFIG_STM32L4_TIM1_BREAK1 +#ifdef CONFIG_STM32_TIM1_BREAK1 .en1 = 1, - .pol1 = CONFIG_STM32L4_TIM1_BRK1POL, + .pol1 = CONFIG_STM32_TIM1_BRK1POL, #endif -#ifdef CONFIG_STM32L4_TIM1_BREAK2 +#ifdef CONFIG_STM32_TIM1_BREAK2 .en2 = 1, - .pol2 = CONFIG_STM32L4_TIM1_BRK2POL, - .flt2 = CONFIG_STM32L4_TIM1_BRK2FLT, + .pol2 = CONFIG_STM32_TIM1_BRK2POL, + .flt2 = CONFIG_STM32_TIM1_BRK2FLT, #endif }, #endif -#ifdef CONFIG_STM32L4_TIM1_CH1OUT +#ifdef CONFIG_STM32_TIM1_CH1OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32L4_TIM1_CH1POL, - .idle = CONFIG_STM32L4_TIM1_CH1IDLE, + .pol = CONFIG_STM32_TIM1_CH1POL, + .idle = CONFIG_STM32_TIM1_CH1IDLE, .pincfg = PWM_TIM1_CH1CFG, }, #endif -#ifdef CONFIG_STM32L4_TIM1_CH1NOUT +#ifdef CONFIG_STM32_TIM1_CH1NOUT .out2 = { .in_use = 1, - .pol = CONFIG_STM32L4_TIM1_CH1NPOL, - .idle = CONFIG_STM32L4_TIM1_CH1NIDLE, + .pol = CONFIG_STM32_TIM1_CH1NPOL, + .idle = CONFIG_STM32_TIM1_CH1NIDLE, .pincfg = PWM_TIM1_CH1NCFG, } #endif }, #endif -#ifdef CONFIG_STM32L4_TIM1_CHANNEL2 +#ifdef CONFIG_STM32_TIM1_CHANNEL2 { .channel = 2, - .mode = CONFIG_STM32L4_TIM1_CH2MODE, -#ifdef CONFIG_STM32L4_TIM1_CH2OUT + .mode = CONFIG_STM32_TIM1_CH2MODE, +#ifdef CONFIG_STM32_TIM1_CH2OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32L4_TIM1_CH2POL, - .idle = CONFIG_STM32L4_TIM1_CH2IDLE, + .pol = CONFIG_STM32_TIM1_CH2POL, + .idle = CONFIG_STM32_TIM1_CH2IDLE, .pincfg = PWM_TIM1_CH2CFG, }, #endif -#ifdef CONFIG_STM32L4_TIM1_CH2NOUT +#ifdef CONFIG_STM32_TIM1_CH2NOUT .out2 = { .in_use = 1, - .pol = CONFIG_STM32L4_TIM1_CH2NPOL, - .idle = CONFIG_STM32L4_TIM1_CH2NIDLE, + .pol = CONFIG_STM32_TIM1_CH2NPOL, + .idle = CONFIG_STM32_TIM1_CH2NIDLE, .pincfg = PWM_TIM1_CH2NCFG, } #endif }, #endif -#ifdef CONFIG_STM32L4_TIM1_CHANNEL3 +#ifdef CONFIG_STM32_TIM1_CHANNEL3 { .channel = 3, - .mode = CONFIG_STM32L4_TIM1_CH3MODE, -#ifdef CONFIG_STM32L4_TIM1_CH3OUT + .mode = CONFIG_STM32_TIM1_CH3MODE, +#ifdef CONFIG_STM32_TIM1_CH3OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32L4_TIM1_CH3POL, - .idle = CONFIG_STM32L4_TIM1_CH3IDLE, + .pol = CONFIG_STM32_TIM1_CH3POL, + .idle = CONFIG_STM32_TIM1_CH3IDLE, .pincfg = PWM_TIM1_CH3CFG, }, #endif -#ifdef CONFIG_STM32L4_TIM1_CH3NOUT +#ifdef CONFIG_STM32_TIM1_CH3NOUT .out2 = { .in_use = 1, - .pol = CONFIG_STM32L4_TIM1_CH3NPOL, - .idle = CONFIG_STM32L4_TIM1_CH3NIDLE, + .pol = CONFIG_STM32_TIM1_CH3NPOL, + .idle = CONFIG_STM32_TIM1_CH3NIDLE, .pincfg = PWM_TIM1_CH3NCFG, } #endif }, #endif -#ifdef CONFIG_STM32L4_TIM1_CHANNEL4 +#ifdef CONFIG_STM32_TIM1_CHANNEL4 { .channel = 4, - .mode = CONFIG_STM32L4_TIM1_CH4MODE, -#ifdef CONFIG_STM32L4_TIM1_CH4OUT + .mode = CONFIG_STM32_TIM1_CH4MODE, +#ifdef CONFIG_STM32_TIM1_CH4OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32L4_TIM1_CH4POL, - .idle = CONFIG_STM32L4_TIM1_CH4IDLE, + .pol = CONFIG_STM32_TIM1_CH4POL, + .idle = CONFIG_STM32_TIM1_CH4IDLE, .pincfg = PWM_TIM1_CH4CFG, } #endif }, #endif -#ifdef CONFIG_STM32L4_TIM1_CHANNEL5 +#ifdef CONFIG_STM32_TIM1_CHANNEL5 { .channel = 5, - .mode = CONFIG_STM32L4_TIM1_CH5MODE, -#ifdef CONFIG_STM32L4_TIM1_CH5OUT + .mode = CONFIG_STM32_TIM1_CH5MODE, +#ifdef CONFIG_STM32_TIM1_CH5OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32L4_TIM1_CH5POL, - .idle = CONFIG_STM32L4_TIM1_CH5IDLE, + .pol = CONFIG_STM32_TIM1_CH5POL, + .idle = CONFIG_STM32_TIM1_CH5IDLE, .pincfg = 0, /* Not available externally */ } #endif }, #endif -#ifdef CONFIG_STM32L4_TIM1_CHANNEL6 +#ifdef CONFIG_STM32_TIM1_CHANNEL6 { .channel = 6, - .mode = CONFIG_STM32L4_TIM1_CH6MODE, -#ifdef CONFIG_STM32L4_TIM1_CH6OUT + .mode = CONFIG_STM32_TIM1_CH6MODE, +#ifdef CONFIG_STM32_TIM1_CH6OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32L4_TIM1_CH6POL, - .idle = CONFIG_STM32L4_TIM1_CH6IDLE, + .pol = CONFIG_STM32_TIM1_CH6POL, + .idle = CONFIG_STM32_TIM1_CH6IDLE, .pincfg = 0, /* Not available externally */ } #endif @@ -435,94 +435,94 @@ static struct stm32l4_pwmchan_s g_pwm1channels[] = #endif }; -static struct stm32l4_pwmtimer_s g_pwm1dev = +static struct stm32_pwmtimer_s g_pwm1dev = { .ops = &g_pwmops, -#ifdef CONFIG_STM32L4_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS .llops = &g_llpwmops, #endif .timid = 1, .chan_num = PWM_TIM1_NCHANNELS, .channels = g_pwm1channels, .timtype = TIMTYPE_TIM1, - .mode = CONFIG_STM32L4_TIM1_MODE, - .lock = CONFIG_STM32L4_TIM1_LOCK, - .t_dts = CONFIG_STM32L4_TIM1_TDTS, + .mode = CONFIG_STM32_TIM1_MODE, + .lock = CONFIG_STM32_TIM1_LOCK, + .t_dts = CONFIG_STM32_TIM1_TDTS, #ifdef HAVE_PWM_COMPLEMENTARY - .deadtime = CONFIG_STM32L4_TIM1_DEADTIME, + .deadtime = CONFIG_STM32_TIM1_DEADTIME, #endif -#if defined(HAVE_TRGO) && defined(STM32L4_TIM1_TRGO) - .trgo = STM32L4_TIM1_TRGO, +#if defined(HAVE_TRGO) && defined(STM32_TIM1_TRGO) + .trgo = STM32_TIM1_TRGO, #endif - .base = STM32L4_TIM1_BASE, - .pclk = STM32L4_APB2_TIM1_CLKIN, + .base = STM32_TIM1_BASE, + .pclk = STM32_APB2_TIM1_CLKIN, }; -#endif /* CONFIG_STM32L4_TIM1_PWM */ +#endif /* CONFIG_STM32_TIM1_PWM */ -#ifdef CONFIG_STM32L4_TIM2_PWM +#ifdef CONFIG_STM32_TIM2_PWM -static struct stm32l4_pwmchan_s g_pwm2channels[] = +static struct stm32_pwmchan_s g_pwm2channels[] = { /* TIM2 has 4 channels */ -#ifdef CONFIG_STM32L4_TIM2_CHANNEL1 +#ifdef CONFIG_STM32_TIM2_CHANNEL1 { .channel = 1, - .mode = CONFIG_STM32L4_TIM2_CH1MODE, -#ifdef CONFIG_STM32L4_TIM2_CH1OUT + .mode = CONFIG_STM32_TIM2_CH1MODE, +#ifdef CONFIG_STM32_TIM2_CH1OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32L4_TIM2_CH1POL, - .idle = CONFIG_STM32L4_TIM2_CH1IDLE, + .pol = CONFIG_STM32_TIM2_CH1POL, + .idle = CONFIG_STM32_TIM2_CH1IDLE, .pincfg = PWM_TIM2_CH1CFG, } #endif /* No complementary outputs */ }, #endif -#ifdef CONFIG_STM32L4_TIM2_CHANNEL2 +#ifdef CONFIG_STM32_TIM2_CHANNEL2 { .channel = 2, - .mode = CONFIG_STM32L4_TIM2_CH2MODE, -#ifdef CONFIG_STM32L4_TIM2_CH2OUT + .mode = CONFIG_STM32_TIM2_CH2MODE, +#ifdef CONFIG_STM32_TIM2_CH2OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32L4_TIM2_CH2POL, - .idle = CONFIG_STM32L4_TIM2_CH2IDLE, + .pol = CONFIG_STM32_TIM2_CH2POL, + .idle = CONFIG_STM32_TIM2_CH2IDLE, .pincfg = PWM_TIM2_CH2CFG, } #endif /* No complementary outputs */ }, #endif -#ifdef CONFIG_STM32L4_TIM2_CHANNEL3 +#ifdef CONFIG_STM32_TIM2_CHANNEL3 { .channel = 3, - .mode = CONFIG_STM32L4_TIM2_CH3MODE, -#ifdef CONFIG_STM32L4_TIM2_CH3OUT + .mode = CONFIG_STM32_TIM2_CH3MODE, +#ifdef CONFIG_STM32_TIM2_CH3OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32L4_TIM2_CH3POL, - .idle = CONFIG_STM32L4_TIM2_CH3IDLE, + .pol = CONFIG_STM32_TIM2_CH3POL, + .idle = CONFIG_STM32_TIM2_CH3IDLE, .pincfg = PWM_TIM2_CH3CFG, } #endif /* No complementary outputs */ }, #endif -#ifdef CONFIG_STM32L4_TIM2_CHANNEL4 +#ifdef CONFIG_STM32_TIM2_CHANNEL4 { .channel = 4, - .mode = CONFIG_STM32L4_TIM2_CH4MODE, -#ifdef CONFIG_STM32L4_TIM2_CH4OUT + .mode = CONFIG_STM32_TIM2_CH4MODE, +#ifdef CONFIG_STM32_TIM2_CH4OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32L4_TIM2_CH4POL, - .idle = CONFIG_STM32L4_TIM2_CH4IDLE, + .pol = CONFIG_STM32_TIM2_CH4POL, + .idle = CONFIG_STM32_TIM2_CH4IDLE, .pincfg = PWM_TIM2_CH4CFG, } #endif @@ -531,95 +531,95 @@ static struct stm32l4_pwmchan_s g_pwm2channels[] = #endif }; -static struct stm32l4_pwmtimer_s g_pwm2dev = +static struct stm32_pwmtimer_s g_pwm2dev = { .ops = &g_pwmops, -#ifdef CONFIG_STM32L4_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS .llops = &g_llpwmops, #endif .timid = 2, .chan_num = PWM_TIM2_NCHANNELS, .channels = g_pwm2channels, .timtype = TIMTYPE_TIM2, - .mode = CONFIG_STM32L4_TIM2_MODE, + .mode = CONFIG_STM32_TIM2_MODE, .lock = 0, /* No lock */ .t_dts = 0, /* No t_dts */ #ifdef HAVE_PWM_COMPLEMENTARY .deadtime = 0, /* No deadtime */ #endif -#if defined(HAVE_TRGO) && defined(STM32L4_TIM2_TRGO) - .trgo = STM32L4_TIM2_TRGO, +#if defined(HAVE_TRGO) && defined(STM32_TIM2_TRGO) + .trgo = STM32_TIM2_TRGO, #endif - .base = STM32L4_TIM2_BASE, - .pclk = STM32L4_APB1_TIM2_CLKIN, + .base = STM32_TIM2_BASE, + .pclk = STM32_APB1_TIM2_CLKIN, }; -#endif /* CONFIG_STM32L4_TIM2_PWM */ +#endif /* CONFIG_STM32_TIM2_PWM */ -#ifdef CONFIG_STM32L4_TIM3_PWM +#ifdef CONFIG_STM32_TIM3_PWM -static struct stm32l4_pwmchan_s g_pwm3channels[] = +static struct stm32_pwmchan_s g_pwm3channels[] = { /* TIM3 has 4 channels */ -#ifdef CONFIG_STM32L4_TIM3_CHANNEL1 +#ifdef CONFIG_STM32_TIM3_CHANNEL1 { .channel = 1, - .mode = CONFIG_STM32L4_TIM3_CH1MODE, -#ifdef CONFIG_STM32L4_TIM3_CH1OUT + .mode = CONFIG_STM32_TIM3_CH1MODE, +#ifdef CONFIG_STM32_TIM3_CH1OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32L4_TIM3_CH1POL, - .idle = CONFIG_STM32L4_TIM3_CH1IDLE, + .pol = CONFIG_STM32_TIM3_CH1POL, + .idle = CONFIG_STM32_TIM3_CH1IDLE, .pincfg = PWM_TIM3_CH1CFG, } #endif /* No complementary outputs */ }, #endif -#ifdef CONFIG_STM32L4_TIM3_CHANNEL2 +#ifdef CONFIG_STM32_TIM3_CHANNEL2 { .channel = 2, - .mode = CONFIG_STM32L4_TIM3_CH2MODE, -#ifdef CONFIG_STM32L4_TIM3_CH2OUT + .mode = CONFIG_STM32_TIM3_CH2MODE, +#ifdef CONFIG_STM32_TIM3_CH2OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32L4_TIM3_CH2POL, - .idle = CONFIG_STM32L4_TIM3_CH2IDLE, + .pol = CONFIG_STM32_TIM3_CH2POL, + .idle = CONFIG_STM32_TIM3_CH2IDLE, .pincfg = PWM_TIM3_CH2CFG, } #endif /* No complementary outputs */ }, #endif -#ifdef CONFIG_STM32L4_TIM3_CHANNEL3 +#ifdef CONFIG_STM32_TIM3_CHANNEL3 { .channel = 3, - .mode = CONFIG_STM32L4_TIM3_CH3MODE, -#ifdef CONFIG_STM32L4_TIM3_CH3OUT + .mode = CONFIG_STM32_TIM3_CH3MODE, +#ifdef CONFIG_STM32_TIM3_CH3OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32L4_TIM3_CH3POL, - .idle = CONFIG_STM32L4_TIM3_CH3IDLE, + .pol = CONFIG_STM32_TIM3_CH3POL, + .idle = CONFIG_STM32_TIM3_CH3IDLE, .pincfg = PWM_TIM3_CH3CFG, } #endif /* No complementary outputs */ }, #endif -#ifdef CONFIG_STM32L4_TIM3_CHANNEL4 +#ifdef CONFIG_STM32_TIM3_CHANNEL4 { .channel = 4, - .mode = CONFIG_STM32L4_TIM3_CH4MODE, -#ifdef CONFIG_STM32L4_TIM3_CH4OUT + .mode = CONFIG_STM32_TIM3_CH4MODE, +#ifdef CONFIG_STM32_TIM3_CH4OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32L4_TIM3_CH4POL, - .idle = CONFIG_STM32L4_TIM3_CH4IDLE, + .pol = CONFIG_STM32_TIM3_CH4POL, + .idle = CONFIG_STM32_TIM3_CH4IDLE, .pincfg = PWM_TIM3_CH4CFG, } #endif @@ -628,94 +628,94 @@ static struct stm32l4_pwmchan_s g_pwm3channels[] = #endif }; -static struct stm32l4_pwmtimer_s g_pwm3dev = +static struct stm32_pwmtimer_s g_pwm3dev = { .ops = &g_pwmops, -#ifdef CONFIG_STM32L4_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS .llops = &g_llpwmops, #endif .timid = 3, .chan_num = PWM_TIM3_NCHANNELS, .channels = g_pwm3channels, .timtype = TIMTYPE_TIM3, - .mode = CONFIG_STM32L4_TIM3_MODE, + .mode = CONFIG_STM32_TIM3_MODE, .lock = 0, /* No lock */ .t_dts = 0, /* No t_dts */ #ifdef HAVE_PWM_COMPLEMENTARY .deadtime = 0, /* No deadtime */ #endif -#if defined(HAVE_TRGO) && defined(STM32L4_TIM3_TRGO) - .trgo = STM32L4_TIM3_TRGO, +#if defined(HAVE_TRGO) && defined(STM32_TIM3_TRGO) + .trgo = STM32_TIM3_TRGO, #endif - .base = STM32L4_TIM3_BASE, - .pclk = STM32L4_APB1_TIM3_CLKIN, + .base = STM32_TIM3_BASE, + .pclk = STM32_APB1_TIM3_CLKIN, }; -#endif /* CONFIG_STM32L4_TIM3_PWM */ +#endif /* CONFIG_STM32_TIM3_PWM */ -#ifdef CONFIG_STM32L4_TIM4_PWM +#ifdef CONFIG_STM32_TIM4_PWM -static struct stm32l4_pwmchan_s g_pwm4channels[] = +static struct stm32_pwmchan_s g_pwm4channels[] = { /* TIM4 has 4 channels */ -#ifdef CONFIG_STM32L4_TIM4_CHANNEL1 +#ifdef CONFIG_STM32_TIM4_CHANNEL1 { .channel = 1, - .mode = CONFIG_STM32L4_TIM4_CH1MODE, -#ifdef CONFIG_STM32L4_TIM4_CH1OUT + .mode = CONFIG_STM32_TIM4_CH1MODE, +#ifdef CONFIG_STM32_TIM4_CH1OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32L4_TIM4_CH1POL, - .idle = CONFIG_STM32L4_TIM4_CH1IDLE, + .pol = CONFIG_STM32_TIM4_CH1POL, + .idle = CONFIG_STM32_TIM4_CH1IDLE, .pincfg = PWM_TIM4_CH1CFG, } #endif /* No complementary outputs */ }, #endif -#ifdef CONFIG_STM32L4_TIM4_CHANNEL2 +#ifdef CONFIG_STM32_TIM4_CHANNEL2 { .channel = 2, - .mode = CONFIG_STM32L4_TIM4_CH2MODE, -#ifdef CONFIG_STM32L4_TIM4_CH2OUT + .mode = CONFIG_STM32_TIM4_CH2MODE, +#ifdef CONFIG_STM32_TIM4_CH2OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32L4_TIM4_CH2POL, - .idle = CONFIG_STM32L4_TIM4_CH2IDLE, + .pol = CONFIG_STM32_TIM4_CH2POL, + .idle = CONFIG_STM32_TIM4_CH2IDLE, .pincfg = PWM_TIM4_CH2CFG, } #endif /* No complementary outputs */ }, #endif -#ifdef CONFIG_STM32L4_TIM4_CHANNEL3 +#ifdef CONFIG_STM32_TIM4_CHANNEL3 { .channel = 3, - .mode = CONFIG_STM32L4_TIM4_CH3MODE, -#ifdef CONFIG_STM32L4_TIM4_CH3OUT + .mode = CONFIG_STM32_TIM4_CH3MODE, +#ifdef CONFIG_STM32_TIM4_CH3OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32L4_TIM4_CH3POL, - .idle = CONFIG_STM32L4_TIM4_CH3IDLE, + .pol = CONFIG_STM32_TIM4_CH3POL, + .idle = CONFIG_STM32_TIM4_CH3IDLE, .pincfg = PWM_TIM4_CH3CFG, } #endif /* No complementary outputs */ }, #endif -#ifdef CONFIG_STM32L4_TIM4_CHANNEL4 +#ifdef CONFIG_STM32_TIM4_CHANNEL4 { .channel = 4, - .mode = CONFIG_STM32L4_TIM4_CH4MODE, -#ifdef CONFIG_STM32L4_TIM4_CH4OUT + .mode = CONFIG_STM32_TIM4_CH4MODE, +#ifdef CONFIG_STM32_TIM4_CH4OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32L4_TIM4_CH4POL, - .idle = CONFIG_STM32L4_TIM4_CH4IDLE, + .pol = CONFIG_STM32_TIM4_CH4POL, + .idle = CONFIG_STM32_TIM4_CH4IDLE, .pincfg = PWM_TIM4_CH4CFG, } #endif @@ -724,93 +724,93 @@ static struct stm32l4_pwmchan_s g_pwm4channels[] = #endif }; -static struct stm32l4_pwmtimer_s g_pwm4dev = +static struct stm32_pwmtimer_s g_pwm4dev = { .ops = &g_pwmops, -#ifdef CONFIG_STM32L4_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS .llops = &g_llpwmops, #endif .timid = 4, .chan_num = PWM_TIM4_NCHANNELS, .channels = g_pwm4channels, .timtype = TIMTYPE_TIM4, - .mode = CONFIG_STM32L4_TIM4_MODE, + .mode = CONFIG_STM32_TIM4_MODE, .lock = 0, /* No lock */ .t_dts = 0, /* No t_dts */ #ifdef HAVE_PWM_COMPLEMENTARY .deadtime = 0, /* No deadtime */ #endif -#if defined(HAVE_TRGO) && defined(STM32L4_TIM4_TRGO) - .trgo = STM32L4_TIM4_TRGO, +#if defined(HAVE_TRGO) && defined(STM32_TIM4_TRGO) + .trgo = STM32_TIM4_TRGO, #endif - .base = STM32L4_TIM4_BASE, - .pclk = STM32L4_APB1_TIM4_CLKIN, + .base = STM32_TIM4_BASE, + .pclk = STM32_APB1_TIM4_CLKIN, }; -#endif /* CONFIG_STM32L4_TIM4_PWM */ +#endif /* CONFIG_STM32_TIM4_PWM */ -#ifdef CONFIG_STM32L4_TIM5_PWM +#ifdef CONFIG_STM32_TIM5_PWM -static struct stm32l4_pwmchan_s g_pwm5channels[] = +static struct stm32_pwmchan_s g_pwm5channels[] = { /* TIM5 has 4 channels */ -#ifdef CONFIG_STM32L4_TIM5_CHANNEL1 +#ifdef CONFIG_STM32_TIM5_CHANNEL1 { .channel = 1, - .mode = CONFIG_STM32L4_TIM5_CH1MODE, -#ifdef CONFIG_STM32L4_TIM5_CH1OUT + .mode = CONFIG_STM32_TIM5_CH1MODE, +#ifdef CONFIG_STM32_TIM5_CH1OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32L4_TIM5_CH1POL, - .idle = CONFIG_STM32L4_TIM5_CH1IDLE, + .pol = CONFIG_STM32_TIM5_CH1POL, + .idle = CONFIG_STM32_TIM5_CH1IDLE, .pincfg = PWM_TIM5_CH1CFG, } #endif /* No complementary outputs */ }, #endif -#ifdef CONFIG_STM32L4_TIM5_CHANNEL2 +#ifdef CONFIG_STM32_TIM5_CHANNEL2 { .channel = 2, - .mode = CONFIG_STM32L4_TIM5_CH2MODE, -#ifdef CONFIG_STM32L4_TIM5_CH2OUT + .mode = CONFIG_STM32_TIM5_CH2MODE, +#ifdef CONFIG_STM32_TIM5_CH2OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32L4_TIM5_CH2POL, - .idle = CONFIG_STM32L4_TIM5_CH2IDLE, + .pol = CONFIG_STM32_TIM5_CH2POL, + .idle = CONFIG_STM32_TIM5_CH2IDLE, .pincfg = PWM_TIM5_CH2CFG, } #endif /* No complementary outputs */ }, #endif -#ifdef CONFIG_STM32L4_TIM5_CHANNEL3 +#ifdef CONFIG_STM32_TIM5_CHANNEL3 { .channel = 3, - .mode = CONFIG_STM32L4_TIM5_CH3MODE, -#ifdef CONFIG_STM32L4_TIM5_CH3OUT + .mode = CONFIG_STM32_TIM5_CH3MODE, +#ifdef CONFIG_STM32_TIM5_CH3OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32L4_TIM5_CH3POL, - .idle = CONFIG_STM32L4_TIM5_CH3IDLE, + .pol = CONFIG_STM32_TIM5_CH3POL, + .idle = CONFIG_STM32_TIM5_CH3IDLE, .pincfg = PWM_TIM5_CH3CFG, } #endif }, #endif -#ifdef CONFIG_STM32L4_TIM5_CHANNEL4 +#ifdef CONFIG_STM32_TIM5_CHANNEL4 { .channel = 4, - .mode = CONFIG_STM32L4_TIM5_CH4MODE, -#ifdef CONFIG_STM32L4_TIM5_CH4OUT + .mode = CONFIG_STM32_TIM5_CH4MODE, +#ifdef CONFIG_STM32_TIM5_CH4OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32L4_TIM5_CH4POL, - .idle = CONFIG_STM32L4_TIM5_CH4IDLE, + .pol = CONFIG_STM32_TIM5_CH4POL, + .idle = CONFIG_STM32_TIM5_CH4IDLE, .pincfg = PWM_TIM5_CH4CFG, } #endif @@ -818,162 +818,162 @@ static struct stm32l4_pwmchan_s g_pwm5channels[] = #endif }; -static struct stm32l4_pwmtimer_s g_pwm5dev = +static struct stm32_pwmtimer_s g_pwm5dev = { .ops = &g_pwmops, -#ifdef CONFIG_STM32L4_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS .llops = &g_llpwmops, #endif .timid = 5, .chan_num = PWM_TIM5_NCHANNELS, .channels = g_pwm5channels, .timtype = TIMTYPE_TIM5, - .mode = CONFIG_STM32L4_TIM5_MODE, + .mode = CONFIG_STM32_TIM5_MODE, .lock = 0, /* No lock */ .t_dts = 0, /* No t_dts */ #ifdef HAVE_PWM_COMPLEMENTARY .deadtime = 0, /* No deadtime */ #endif -#if defined(HAVE_TRGO) && defined(STM32L4_TIM5_TRGO) - .trgo = STM32L4_TIM5_TRGO +#if defined(HAVE_TRGO) && defined(STM32_TIM5_TRGO) + .trgo = STM32_TIM5_TRGO #endif - .base = STM32L4_TIM5_BASE, - .pclk = STM32L4_APB1_TIM5_CLKIN, + .base = STM32_TIM5_BASE, + .pclk = STM32_APB1_TIM5_CLKIN, }; -#endif /* CONFIG_STM32L4_TIM5_PWM */ +#endif /* CONFIG_STM32_TIM5_PWM */ -#ifdef CONFIG_STM32L4_TIM8_PWM +#ifdef CONFIG_STM32_TIM8_PWM -static struct stm32l4_pwmchan_s g_pwm8channels[] = +static struct stm32_pwmchan_s g_pwm8channels[] = { /* TIM8 has 4 channels, 4 complementary */ -#ifdef CONFIG_STM32L4_TIM8_CHANNEL1 +#ifdef CONFIG_STM32_TIM8_CHANNEL1 { .channel = 1, - .mode = CONFIG_STM32L4_TIM8_CH1MODE, + .mode = CONFIG_STM32_TIM8_CH1MODE, #ifdef HAVE_BREAK .brk = { -#ifdef CONFIG_STM32L4_TIM8_BREAK1 +#ifdef CONFIG_STM32_TIM8_BREAK1 .en1 = 1, - .pol1 = CONFIG_STM32L4_TIM8_BRK1POL, + .pol1 = CONFIG_STM32_TIM8_BRK1POL, #endif -#ifdef CONFIG_STM32L4_TIM8_BREAK2 +#ifdef CONFIG_STM32_TIM8_BREAK2 .en2 = 1, - .pol2 = CONFIG_STM32L4_TIM8_BRK2POL, - .flt2 = CONFIG_STM32L4_TIM8_BRK2FLT, + .pol2 = CONFIG_STM32_TIM8_BRK2POL, + .flt2 = CONFIG_STM32_TIM8_BRK2FLT, #endif }, #endif -#ifdef CONFIG_STM32L4_TIM8_CH1OUT +#ifdef CONFIG_STM32_TIM8_CH1OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32L4_TIM8_CH1POL, - .idle = CONFIG_STM32L4_TIM8_CH1IDLE, + .pol = CONFIG_STM32_TIM8_CH1POL, + .idle = CONFIG_STM32_TIM8_CH1IDLE, .pincfg = PWM_TIM8_CH1CFG, }, #endif -#ifdef CONFIG_STM32L4_TIM8_CH1NOUT +#ifdef CONFIG_STM32_TIM8_CH1NOUT .out2 = { .in_use = 1, - .pol = CONFIG_STM32L4_TIM8_CH1NPOL, - .idle = CONFIG_STM32L4_TIM8_CH1NIDLE, + .pol = CONFIG_STM32_TIM8_CH1NPOL, + .idle = CONFIG_STM32_TIM8_CH1NIDLE, .pincfg = PWM_TIM8_CH1NCFG, } #endif }, #endif -#ifdef CONFIG_STM32L4_TIM8_CHANNEL2 +#ifdef CONFIG_STM32_TIM8_CHANNEL2 { .channel = 2, - .mode = CONFIG_STM32L4_TIM8_CH2MODE, -#ifdef CONFIG_STM32L4_TIM8_CH2OUT + .mode = CONFIG_STM32_TIM8_CH2MODE, +#ifdef CONFIG_STM32_TIM8_CH2OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32L4_TIM8_CH2POL, - .idle = CONFIG_STM32L4_TIM8_CH2IDLE, + .pol = CONFIG_STM32_TIM8_CH2POL, + .idle = CONFIG_STM32_TIM8_CH2IDLE, .pincfg = PWM_TIM8_CH2CFG, }, #endif -#ifdef CONFIG_STM32L4_TIM8_CH2NOUT +#ifdef CONFIG_STM32_TIM8_CH2NOUT .out2 = { .in_use = 1, - .pol = CONFIG_STM32L4_TIM8_CH2NPOL, - .idle = CONFIG_STM32L4_TIM8_CH2NIDLE, + .pol = CONFIG_STM32_TIM8_CH2NPOL, + .idle = CONFIG_STM32_TIM8_CH2NIDLE, .pincfg = PWM_TIM8_CH2NCFG, } #endif }, #endif -#ifdef CONFIG_STM32L4_TIM8_CHANNEL3 +#ifdef CONFIG_STM32_TIM8_CHANNEL3 { .channel = 3, - .mode = CONFIG_STM32L4_TIM8_CH3MODE, -#ifdef CONFIG_STM32L4_TIM8_CH3OUT + .mode = CONFIG_STM32_TIM8_CH3MODE, +#ifdef CONFIG_STM32_TIM8_CH3OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32L4_TIM8_CH3POL, - .idle = CONFIG_STM32L4_TIM8_CH3IDLE, + .pol = CONFIG_STM32_TIM8_CH3POL, + .idle = CONFIG_STM32_TIM8_CH3IDLE, .pincfg = PWM_TIM8_CH3CFG, }, #endif -#ifdef CONFIG_STM32L4_TIM8_CH3NOUT +#ifdef CONFIG_STM32_TIM8_CH3NOUT .out2 = { .in_use = 1, - .pol = CONFIG_STM32L4_TIM8_CH3NPOL, - .idle = CONFIG_STM32L4_TIM8_CH3NIDLE, + .pol = CONFIG_STM32_TIM8_CH3NPOL, + .idle = CONFIG_STM32_TIM8_CH3NIDLE, .pincfg = PWM_TIM8_CH3NCFG, } #endif }, #endif -#ifdef CONFIG_STM32L4_TIM8_CHANNEL4 +#ifdef CONFIG_STM32_TIM8_CHANNEL4 { .channel = 4, - .mode = CONFIG_STM32L4_TIM8_CH4MODE, -#ifdef CONFIG_STM32L4_TIM8_CH4OUT + .mode = CONFIG_STM32_TIM8_CH4MODE, +#ifdef CONFIG_STM32_TIM8_CH4OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32L4_TIM8_CH4POL, - .idle = CONFIG_STM32L4_TIM8_CH4IDLE, + .pol = CONFIG_STM32_TIM8_CH4POL, + .idle = CONFIG_STM32_TIM8_CH4IDLE, .pincfg = PWM_TIM8_CH4CFG, } #endif }, #endif -#ifdef CONFIG_STM32L4_TIM8_CHANNEL5 +#ifdef CONFIG_STM32_TIM8_CHANNEL5 { .channel = 5, - .mode = CONFIG_STM32L4_TIM8_CH5MODE, -#ifdef CONFIG_STM32L4_TIM8_CH5OUT + .mode = CONFIG_STM32_TIM8_CH5MODE, +#ifdef CONFIG_STM32_TIM8_CH5OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32L4_TIM8_CH5POL, - .idle = CONFIG_STM32L4_TIM8_CH5IDLE, + .pol = CONFIG_STM32_TIM8_CH5POL, + .idle = CONFIG_STM32_TIM8_CH5IDLE, .pincfg = 0, /* Not available externally */ } #endif }, #endif -#ifdef CONFIG_STM32L4_TIM8_CHANNEL6 +#ifdef CONFIG_STM32_TIM8_CHANNEL6 { .channel = 6, - .mode = CONFIG_STM32L4_TIM8_CH6MODE, -#ifdef CONFIG_STM32L4_TIM8_CH6OUT + .mode = CONFIG_STM32_TIM8_CH6MODE, +#ifdef CONFIG_STM32_TIM8_CH6OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32L4_TIM8_CH6POL, - .idle = CONFIG_STM32L4_TIM8_CH6IDLE, + .pol = CONFIG_STM32_TIM8_CH6POL, + .idle = CONFIG_STM32_TIM8_CH6IDLE, .pincfg = 0, /* Not available externally */ } #endif @@ -981,80 +981,80 @@ static struct stm32l4_pwmchan_s g_pwm8channels[] = #endif }; -static struct stm32l4_pwmtimer_s g_pwm8dev = +static struct stm32_pwmtimer_s g_pwm8dev = { .ops = &g_pwmops, -#ifdef CONFIG_STM32L4_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS .llops = &g_llpwmops, #endif .timid = 8, .chan_num = PWM_TIM8_NCHANNELS, .channels = g_pwm8channels, .timtype = TIMTYPE_TIM8, - .mode = CONFIG_STM32L4_TIM8_MODE, - .lock = CONFIG_STM32L4_TIM8_LOCK, - .t_dts = CONFIG_STM32L4_TIM8_TDTS, + .mode = CONFIG_STM32_TIM8_MODE, + .lock = CONFIG_STM32_TIM8_LOCK, + .t_dts = CONFIG_STM32_TIM8_TDTS, #ifdef HAVE_PWM_COMPLEMENTARY - .deadtime = CONFIG_STM32L4_TIM8_DEADTIME, + .deadtime = CONFIG_STM32_TIM8_DEADTIME, #endif -#if defined(HAVE_TRGO) && defined(STM32L4_TIM8_TRGO) - .trgo = STM32L4_TIM8_TRGO, +#if defined(HAVE_TRGO) && defined(STM32_TIM8_TRGO) + .trgo = STM32_TIM8_TRGO, #endif - .base = STM32L4_TIM8_BASE, - .pclk = STM32L4_APB2_TIM8_CLKIN, + .base = STM32_TIM8_BASE, + .pclk = STM32_APB2_TIM8_CLKIN, }; -#endif /* CONFIG_STM32L4_TIM8_PWM */ +#endif /* CONFIG_STM32_TIM8_PWM */ -#ifdef CONFIG_STM32L4_TIM15_PWM +#ifdef CONFIG_STM32_TIM15_PWM -static struct stm32l4_pwmchan_s g_pwm15channels[] = +static struct stm32_pwmchan_s g_pwm15channels[] = { /* TIM15 has 2 channels, 1 complementary */ -#ifdef CONFIG_STM32L4_TIM15_CHANNEL1 +#ifdef CONFIG_STM32_TIM15_CHANNEL1 { .channel = 1, - .mode = CONFIG_STM32L4_TIM15_CH1MODE, + .mode = CONFIG_STM32_TIM15_CH1MODE, #ifdef HAVE_BREAK .brk = { -#ifdef CONFIG_STM32L4_TIM15_BREAK1 +#ifdef CONFIG_STM32_TIM15_BREAK1 .en1 = 1, - .pol1 = CONFIG_STM32L4_TIM15_BRK1POL, + .pol1 = CONFIG_STM32_TIM15_BRK1POL, #endif /* No BREAK2 */ }, #endif -#ifdef CONFIG_STM32L4_TIM15_CH1OUT +#ifdef CONFIG_STM32_TIM15_CH1OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32L4_TIM15_CH1POL, - .idle = CONFIG_STM32L4_TIM15_CH1IDLE, + .pol = CONFIG_STM32_TIM15_CH1POL, + .idle = CONFIG_STM32_TIM15_CH1IDLE, .pincfg = PWM_TIM15_CH1CFG, }, #endif -#ifdef CONFIG_STM32L4_TIM15_CH1NOUT +#ifdef CONFIG_STM32_TIM15_CH1NOUT .out2 = { .in_use = 1, - .pol = CONFIG_STM32L4_TIM15_CH1NPOL, - .idle = CONFIG_STM32L4_TIM15_CH1NIDLE, + .pol = CONFIG_STM32_TIM15_CH1NPOL, + .idle = CONFIG_STM32_TIM15_CH1NIDLE, .pincfg = PWM_TIM15_CH2CFG, } #endif }, #endif -#ifdef CONFIG_STM32L4_TIM15_CHANNEL2 +#ifdef CONFIG_STM32_TIM15_CHANNEL2 { .channel = 2, - .mode = CONFIG_STM32L4_TIM15_CH2MODE, -#ifdef CONFIG_STM32L4_TIM15_CH2OUT + .mode = CONFIG_STM32_TIM15_CH2MODE, +#ifdef CONFIG_STM32_TIM15_CH2OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32L4_TIM15_CH2POL, - .idle = CONFIG_STM32L4_TIM15_CH2IDLE, + .pol = CONFIG_STM32_TIM15_CH2POL, + .idle = CONFIG_STM32_TIM15_CH2IDLE, .pincfg = PWM_TIM15_CH2CFG, } #endif @@ -1063,65 +1063,65 @@ static struct stm32l4_pwmchan_s g_pwm15channels[] = #endif }; -static struct stm32l4_pwmtimer_s g_pwm15dev = +static struct stm32_pwmtimer_s g_pwm15dev = { .ops = &g_pwmops, -#ifdef CONFIG_STM32L4_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS .llops = &g_llpwmops, #endif .timid = 15, .chan_num = PWM_TIM15_NCHANNELS, .channels = g_pwm15channels, .timtype = TIMTYPE_TIM15, - .mode = STM32L4_TIMMODE_COUNTUP, - .lock = CONFIG_STM32L4_TIM15_LOCK, - .t_dts = CONFIG_STM32L4_TIM15_TDTS, + .mode = STM32_TIMMODE_COUNTUP, + .lock = CONFIG_STM32_TIM15_LOCK, + .t_dts = CONFIG_STM32_TIM15_TDTS, #ifdef HAVE_PWM_COMPLEMENTARY - .deadtime = CONFIG_STM32L4_TIM15_DEADTIME, + .deadtime = CONFIG_STM32_TIM15_DEADTIME, #endif -#if defined(HAVE_TRGO) && defined(STM32L4_TIM15_TRGO) - .trgo = STM32L4_TIM15_TRGO, +#if defined(HAVE_TRGO) && defined(STM32_TIM15_TRGO) + .trgo = STM32_TIM15_TRGO, #endif - .base = STM32L4_TIM15_BASE, - .pclk = STM32L4_APB2_TIM15_CLKIN, + .base = STM32_TIM15_BASE, + .pclk = STM32_APB2_TIM15_CLKIN, }; -#endif /* CONFIG_STM32L4_TIM15_PWM */ +#endif /* CONFIG_STM32_TIM15_PWM */ -#ifdef CONFIG_STM32L4_TIM16_PWM +#ifdef CONFIG_STM32_TIM16_PWM -static struct stm32l4_pwmchan_s g_pwm16channels[] = +static struct stm32_pwmchan_s g_pwm16channels[] = { /* TIM16 has 1 channel, 1 complementary */ -#ifdef CONFIG_STM32L4_TIM16_CHANNEL1 +#ifdef CONFIG_STM32_TIM16_CHANNEL1 { .channel = 1, - .mode = CONFIG_STM32L4_TIM16_CH1MODE, + .mode = CONFIG_STM32_TIM16_CH1MODE, #ifdef HAVE_BREAK .brk = { -#ifdef CONFIG_STM32L4_TIM16_BREAK1 +#ifdef CONFIG_STM32_TIM16_BREAK1 .en1 = 1, - .pol1 = CONFIG_STM32L4_TIM16_BRK1POL, + .pol1 = CONFIG_STM32_TIM16_BRK1POL, #endif /* No BREAK2 */ }, #endif -#ifdef CONFIG_STM32L4_TIM16_CH1OUT +#ifdef CONFIG_STM32_TIM16_CH1OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32L4_TIM16_CH1POL, - .idle = CONFIG_STM32L4_TIM16_CH1IDLE, + .pol = CONFIG_STM32_TIM16_CH1POL, + .idle = CONFIG_STM32_TIM16_CH1IDLE, .pincfg = PWM_TIM16_CH1CFG, }, #endif -#ifdef CONFIG_STM32L4_TIM16_CH1NOUT +#ifdef CONFIG_STM32_TIM16_CH1NOUT .out2 = { .in_use = 1, - .pol = CONFIG_STM32L4_TIM16_CH1NPOL, - .idle = CONFIG_STM32L4_TIM16_CH1NIDLE, + .pol = CONFIG_STM32_TIM16_CH1NPOL, + .idle = CONFIG_STM32_TIM16_CH1NIDLE, .pincfg = PWM_TIM16_CH2CFG, } #endif @@ -1129,65 +1129,65 @@ static struct stm32l4_pwmchan_s g_pwm16channels[] = #endif }; -static struct stm32l4_pwmtimer_s g_pwm16dev = +static struct stm32_pwmtimer_s g_pwm16dev = { .ops = &g_pwmops, -#ifdef CONFIG_STM32L4_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS .llops = &g_llpwmops, #endif .timid = 16, .chan_num = PWM_TIM16_NCHANNELS, .channels = g_pwm16channels, .timtype = TIMTYPE_TIM16, - .mode = STM32L4_TIMMODE_COUNTUP, - .lock = CONFIG_STM32L4_TIM16_LOCK, - .t_dts = CONFIG_STM32L4_TIM16_TDTS, + .mode = STM32_TIMMODE_COUNTUP, + .lock = CONFIG_STM32_TIM16_LOCK, + .t_dts = CONFIG_STM32_TIM16_TDTS, #ifdef HAVE_PWM_COMPLEMENTARY - .deadtime = CONFIG_STM32L4_TIM16_DEADTIME, + .deadtime = CONFIG_STM32_TIM16_DEADTIME, #endif #if defined(HAVE_TRGO) .trgo = 0, /* TRGO not supported for TIM16 */ #endif - .base = STM32L4_TIM16_BASE, - .pclk = STM32L4_APB2_TIM16_CLKIN, + .base = STM32_TIM16_BASE, + .pclk = STM32_APB2_TIM16_CLKIN, }; -#endif /* CONFIG_STM32L4_TIM16_PWM */ +#endif /* CONFIG_STM32_TIM16_PWM */ -#ifdef CONFIG_STM32L4_TIM17_PWM +#ifdef CONFIG_STM32_TIM17_PWM -static struct stm32l4_pwmchan_s g_pwm17channels[] = +static struct stm32_pwmchan_s g_pwm17channels[] = { /* TIM17 has 1 channel, 1 complementary */ -#ifdef CONFIG_STM32L4_TIM17_CHANNEL1 +#ifdef CONFIG_STM32_TIM17_CHANNEL1 { .channel = 1, - .mode = CONFIG_STM32L4_TIM17_CH1MODE, + .mode = CONFIG_STM32_TIM17_CH1MODE, #ifdef HAVE_BREAK .brk = { -#ifdef CONFIG_STM32L4_TIM17_BREAK1 +#ifdef CONFIG_STM32_TIM17_BREAK1 .en1 = 1, - .pol1 = CONFIG_STM32L4_TIM17_BRK1POL, + .pol1 = CONFIG_STM32_TIM17_BRK1POL, #endif /* No BREAK2 */ }, #endif -#ifdef CONFIG_STM32L4_TIM17_CH1OUT +#ifdef CONFIG_STM32_TIM17_CH1OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32L4_TIM17_CH1POL, - .idle = CONFIG_STM32L4_TIM17_CH1IDLE, + .pol = CONFIG_STM32_TIM17_CH1POL, + .idle = CONFIG_STM32_TIM17_CH1IDLE, .pincfg = PWM_TIM17_CH1CFG, }, #endif -#ifdef CONFIG_STM32L4_TIM17_CH1NOUT +#ifdef CONFIG_STM32_TIM17_CH1NOUT .out2 = { .in_use = 1, - .pol = CONFIG_STM32L4_TIM17_CH1NPOL, - .idle = CONFIG_STM32L4_TIM17_CH1NIDLE, + .pol = CONFIG_STM32_TIM17_CH1NPOL, + .idle = CONFIG_STM32_TIM17_CH1NIDLE, .pincfg = PWM_TIM17_CH2CFG, } #endif @@ -1195,45 +1195,45 @@ static struct stm32l4_pwmchan_s g_pwm17channels[] = #endif }; -static struct stm32l4_pwmtimer_s g_pwm17dev = +static struct stm32_pwmtimer_s g_pwm17dev = { .ops = &g_pwmops, -#ifdef CONFIG_STM32L4_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS .llops = &g_llpwmops, #endif .timid = 17, .chan_num = PWM_TIM17_NCHANNELS, .channels = g_pwm17channels, .timtype = TIMTYPE_TIM17, - .mode = STM32L4_TIMMODE_COUNTUP, - .lock = CONFIG_STM32L4_TIM17_LOCK, - .t_dts = CONFIG_STM32L4_TIM17_TDTS, + .mode = STM32_TIMMODE_COUNTUP, + .lock = CONFIG_STM32_TIM17_LOCK, + .t_dts = CONFIG_STM32_TIM17_TDTS, #ifdef HAVE_PWM_COMPLEMENTARY - .deadtime = CONFIG_STM32L4_TIM17_DEADTIME, + .deadtime = CONFIG_STM32_TIM17_DEADTIME, #endif #if defined(HAVE_TRGO) .trgo = 0, /* TRGO not supported for TIM17 */ #endif - .base = STM32L4_TIM17_BASE, - .pclk = STM32L4_APB2_TIM17_CLKIN, + .base = STM32_TIM17_BASE, + .pclk = STM32_APB2_TIM17_CLKIN, }; -#endif /* CONFIG_STM32L4_TIM17_PWM */ +#endif /* CONFIG_STM32_TIM17_PWM */ -#ifdef CONFIG_STM32L4_LPTIM1_PWM +#ifdef CONFIG_STM32_LPTIM1_PWM -static struct stm32l4_pwmchan_s g_pwmlp1channels[] = +static struct stm32_pwmchan_s g_pwmlp1channels[] = { /* LPTIM1 has 1 channel */ -#ifdef CONFIG_STM32L4_LPTIM1_CHANNEL1 +#ifdef CONFIG_STM32_LPTIM1_CHANNEL1 { .channel = 1, .mode = 0, -#ifdef CONFIG_STM32L4_LPTIM1_CH1OUT +#ifdef CONFIG_STM32_LPTIM1_CH1OUT .out1 = { .in_use = 1, - .pol = 0, /* REVISIT: Configure using CONFIG_STM32L4_LPTIM1_CH1POL, */ + .pol = 0, /* REVISIT: Configure using CONFIG_STM32_LPTIM1_CH1POL, */ .idle = 0, /* No idle */ .pincfg = PWM_LPTIM1_CH1CFG, } @@ -1243,17 +1243,17 @@ static struct stm32l4_pwmchan_s g_pwmlp1channels[] = #endif }; -static struct stm32l4_pwmtimer_s g_pwmlp1dev = +static struct stm32_pwmtimer_s g_pwmlp1dev = { .ops = &g_pwmops, -#ifdef CONFIG_STM32L4_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS .llops = &g_llpwmops, #endif .timid = 1, .chan_num = PWM_LPTIM1_NCHANNELS, .channels = g_pwmlp1channels, .timtype = TIMTYPE_LPTIM1, - .mode = STM32L4_TIMMODE_COUNTUP, + .mode = STM32_TIMMODE_COUNTUP, .lock = 0, /* No lock */ .t_dts = 0, /* No t_dts */ #ifdef HAVE_PWM_COMPLEMENTARY @@ -1262,34 +1262,34 @@ static struct stm32l4_pwmtimer_s g_pwmlp1dev = #if defined(HAVE_TRGO) .trgo = 0, /* TRGO not supported for LPTIM1 */ #endif - .base = STM32L4_LPTIM1_BASE, -#if defined(CONFIG_STM32L4_LPTIM1_CLK_APB1) - .pclk = STM32L4_PCLK1_FREQUENCY, -#elif defined(CONFIG_STM32L4_LPTIM1_CLK_LSE) - .pclk = STM32L4_LSE_FREQUENCY, -#elif defined(CONFIG_STM32L4_LPTIM1_CLK_LSI) - .pclk = STM32L4_LSI_FREQUENCY, -#elif defined(CONFIG_STM32L4_LPTIM1_CLK_HSI) - .pclk = STM32L4_HSI_FREQUENCY, + .base = STM32_LPTIM1_BASE, +#if defined(CONFIG_STM32_LPTIM1_CLK_APB1) + .pclk = STM32_PCLK1_FREQUENCY, +#elif defined(CONFIG_STM32_LPTIM1_CLK_LSE) + .pclk = STM32_LSE_FREQUENCY, +#elif defined(CONFIG_STM32_LPTIM1_CLK_LSI) + .pclk = STM32_LSI_FREQUENCY, +#elif defined(CONFIG_STM32_LPTIM1_CLK_HSI) + .pclk = STM32_HSI_FREQUENCY, #endif }; -#endif /* CONFIG_STM32L4_LPTIM1_PWM */ +#endif /* CONFIG_STM32_LPTIM1_PWM */ -#ifdef CONFIG_STM32L4_LPTIM2_PWM +#ifdef CONFIG_STM32_LPTIM2_PWM -static struct stm32l4_pwmchan_s g_pwmlp2channels[] = +static struct stm32_pwmchan_s g_pwmlp2channels[] = { /* LPTIM2 has 1 channel */ -#ifdef CONFIG_STM32L4_LPTIM2_CHANNEL1 +#ifdef CONFIG_STM32_LPTIM2_CHANNEL1 { .channel = 1, .mode = 0, -#ifdef CONFIG_STM32L4_LPTIM2_CH1OUT +#ifdef CONFIG_STM32_LPTIM2_CH1OUT .out1 = { .in_use = 1, - .pol = 0, /* REVISIT: Configure using CONFIG_STM32L4_LPTIM2_CH1POL, */ + .pol = 0, /* REVISIT: Configure using CONFIG_STM32_LPTIM2_CH1POL, */ .idle = 0, /* No idle */ .pincfg = PWM_LPTIM2_CH1CFG, } @@ -1299,17 +1299,17 @@ static struct stm32l4_pwmchan_s g_pwmlp2channels[] = #endif }; -static struct stm32l4_pwmtimer_s g_pwmlp2dev = +static struct stm32_pwmtimer_s g_pwmlp2dev = { .ops = &g_pwmops, -#ifdef CONFIG_STM32L4_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS .llops = &g_llpwmops, #endif .timid = 2, .chan_num = PWM_LPTIM2_NCHANNELS, .channels = g_pwmlp2channels, .timtype = TIMTYPE_LPTIM2, - .mode = STM32L4_TIMMODE_COUNTUP, + .mode = STM32_TIMMODE_COUNTUP, .lock = 0, /* No lock */ .t_dts = 0, /* No t_dts */ #ifdef HAVE_PWM_COMPLEMENTARY @@ -1318,18 +1318,18 @@ static struct stm32l4_pwmtimer_s g_pwmlp2dev = #if defined(HAVE_TRGO) .trgo = 0, /* TRGO not supported for LPTIM2 */ #endif - .base = STM32L4_LPTIM2_BASE, -#if defined(CONFIG_STM32L4_LPTIM2_CLK_APB1) - .pclk = STM32L4_PCLK1_FREQUENCY, -#elif defined(CONFIG_STM32L4_LPTIM2_CLK_LSE) - .pclk = STM32L4_LSE_FREQUENCY, -#elif defined(CONFIG_STM32L4_LPTIM2_CLK_LSI) - .pclk = STM32L4_LSI_FREQUENCY, -#elif defined(CONFIG_STM32L4_LPTIM2_CLK_HSI) - .pclk = STM32L4_HSI_FREQUENCY, + .base = STM32_LPTIM2_BASE, +#if defined(CONFIG_STM32_LPTIM2_CLK_APB1) + .pclk = STM32_PCLK1_FREQUENCY, +#elif defined(CONFIG_STM32_LPTIM2_CLK_LSE) + .pclk = STM32_LSE_FREQUENCY, +#elif defined(CONFIG_STM32_LPTIM2_CLK_LSI) + .pclk = STM32_LSI_FREQUENCY, +#elif defined(CONFIG_STM32_LPTIM2_CLK_HSI) + .pclk = STM32_HSI_FREQUENCY, #endif }; -#endif /* CONFIG_STM32L4_LPTIM2_PWM */ +#endif /* CONFIG_STM32_LPTIM2_PWM */ /**************************************************************************** * Private Functions @@ -1350,7 +1350,7 @@ static struct stm32l4_pwmtimer_s g_pwmlp2dev = * ****************************************************************************/ -static uint16_t pwm_getreg(struct stm32l4_pwmtimer_s *priv, int offset) +static uint16_t pwm_getreg(struct stm32_pwmtimer_s *priv, int offset) { return getreg16(priv->base + offset); } @@ -1370,16 +1370,16 @@ static uint16_t pwm_getreg(struct stm32l4_pwmtimer_s *priv, int offset) * ****************************************************************************/ -static void pwm_putreg(struct stm32l4_pwmtimer_s *priv, int offset, +static void pwm_putreg(struct stm32_pwmtimer_s *priv, int offset, uint16_t value) { if (priv->timtype == TIMTYPE_GENERAL32 && - (offset == STM32L4_GTIM_CNT_OFFSET || - offset == STM32L4_GTIM_ARR_OFFSET || - offset == STM32L4_GTIM_CCR1_OFFSET || - offset == STM32L4_GTIM_CCR2_OFFSET || - offset == STM32L4_GTIM_CCR3_OFFSET || - offset == STM32L4_GTIM_CCR4_OFFSET)) + (offset == STM32_GTIM_CNT_OFFSET || + offset == STM32_GTIM_ARR_OFFSET || + offset == STM32_GTIM_CCR1_OFFSET || + offset == STM32_GTIM_CCR2_OFFSET || + offset == STM32_GTIM_CCR3_OFFSET || + offset == STM32_GTIM_CCR4_OFFSET)) { /* a 32 bit access is required for a 32 bit register: * if only a 16 bit write would be performed, then the @@ -1412,16 +1412,16 @@ static void pwm_putreg(struct stm32l4_pwmtimer_s *priv, int offset, * ****************************************************************************/ -static void pwm_modifyreg(struct stm32l4_pwmtimer_s *priv, uint32_t offset, +static void pwm_modifyreg(struct stm32_pwmtimer_s *priv, uint32_t offset, uint32_t clearbits, uint32_t setbits) { if (priv->timtype == TIMTYPE_GENERAL32 && - (offset == STM32L4_GTIM_CNT_OFFSET || - offset == STM32L4_GTIM_ARR_OFFSET || - offset == STM32L4_GTIM_CCR1_OFFSET || - offset == STM32L4_GTIM_CCR2_OFFSET || - offset == STM32L4_GTIM_CCR3_OFFSET || - offset == STM32L4_GTIM_CCR4_OFFSET)) + (offset == STM32_GTIM_CNT_OFFSET || + offset == STM32_GTIM_ARR_OFFSET || + offset == STM32_GTIM_CCR1_OFFSET || + offset == STM32_GTIM_CCR2_OFFSET || + offset == STM32_GTIM_CCR3_OFFSET || + offset == STM32_GTIM_CCR4_OFFSET)) { /* a 32 bit access is required for a 32 bit register: * if only a 16 bit write would be performed, then the @@ -1456,58 +1456,58 @@ static void pwm_modifyreg(struct stm32l4_pwmtimer_s *priv, uint32_t offset, static void pwm_dumpregs(struct pwm_lowerhalf_s *dev, const char *msg) { - struct stm32l4_pwmtimer_s *priv = (struct stm32l4_pwmtimer_s *)dev; + struct stm32_pwmtimer_s *priv = (struct stm32_pwmtimer_s *)dev; if (priv->timtype == TIMTYPE_LOWPOWER) { pwminfo("%s:\n", msg); pwminfo(" CFGR: %04x CR: %04x CMP: %04x ARR: %04x\n", - pwm_getreg(priv, STM32L4_LPTIM_CFGR_OFFSET), - pwm_getreg(priv, STM32L4_LPTIM_CR_OFFSET), - pwm_getreg(priv, STM32L4_LPTIM_CMP_OFFSET), - pwm_getreg(priv, STM32L4_LPTIM_ARR_OFFSET)); + pwm_getreg(priv, STM32_LPTIM_CFGR_OFFSET), + pwm_getreg(priv, STM32_LPTIM_CR_OFFSET), + pwm_getreg(priv, STM32_LPTIM_CMP_OFFSET), + pwm_getreg(priv, STM32_LPTIM_ARR_OFFSET)); pwminfo(" ISR: %04x CNT: %04x\n", - pwm_getreg(priv, STM32L4_LPTIM_ISR_OFFSET), - pwm_getreg(priv, STM32L4_LPTIM_CNT_OFFSET)); + pwm_getreg(priv, STM32_LPTIM_ISR_OFFSET), + pwm_getreg(priv, STM32_LPTIM_CNT_OFFSET)); } else { pwminfo("%s:\n", msg); pwminfo(" CR1: %04x CR2: %04x SMCR: %04x DIER: %04x\n", - pwm_getreg(priv, STM32L4_GTIM_CR1_OFFSET), - pwm_getreg(priv, STM32L4_GTIM_CR2_OFFSET), - pwm_getreg(priv, STM32L4_GTIM_SMCR_OFFSET), - pwm_getreg(priv, STM32L4_GTIM_DIER_OFFSET)); + pwm_getreg(priv, STM32_GTIM_CR1_OFFSET), + pwm_getreg(priv, STM32_GTIM_CR2_OFFSET), + pwm_getreg(priv, STM32_GTIM_SMCR_OFFSET), + pwm_getreg(priv, STM32_GTIM_DIER_OFFSET)); pwminfo(" SR: %04x EGR: %04x CCMR1: %04x CCMR2: %04x\n", - pwm_getreg(priv, STM32L4_GTIM_SR_OFFSET), - pwm_getreg(priv, STM32L4_GTIM_EGR_OFFSET), - pwm_getreg(priv, STM32L4_GTIM_CCMR1_OFFSET), - pwm_getreg(priv, STM32L4_GTIM_CCMR2_OFFSET)); + pwm_getreg(priv, STM32_GTIM_SR_OFFSET), + pwm_getreg(priv, STM32_GTIM_EGR_OFFSET), + pwm_getreg(priv, STM32_GTIM_CCMR1_OFFSET), + pwm_getreg(priv, STM32_GTIM_CCMR2_OFFSET)); pwminfo(" CCER: %04x CNT: %04x PSC: %04x ARR: %04x\n", - pwm_getreg(priv, STM32L4_GTIM_CCER_OFFSET), - pwm_getreg(priv, STM32L4_GTIM_CNT_OFFSET), - pwm_getreg(priv, STM32L4_GTIM_PSC_OFFSET), - pwm_getreg(priv, STM32L4_GTIM_ARR_OFFSET)); + pwm_getreg(priv, STM32_GTIM_CCER_OFFSET), + pwm_getreg(priv, STM32_GTIM_CNT_OFFSET), + pwm_getreg(priv, STM32_GTIM_PSC_OFFSET), + pwm_getreg(priv, STM32_GTIM_ARR_OFFSET)); pwminfo(" CCR1: %04x CCR2: %04x CCR3: %04x CCR4: %04x\n", - pwm_getreg(priv, STM32L4_GTIM_CCR1_OFFSET), - pwm_getreg(priv, STM32L4_GTIM_CCR2_OFFSET), - pwm_getreg(priv, STM32L4_GTIM_CCR3_OFFSET), - pwm_getreg(priv, STM32L4_GTIM_CCR4_OFFSET)); -#if defined(CONFIG_STM32L4_TIM1_PWM) || defined(CONFIG_STM32L4_TIM8_PWM) + pwm_getreg(priv, STM32_GTIM_CCR1_OFFSET), + pwm_getreg(priv, STM32_GTIM_CCR2_OFFSET), + pwm_getreg(priv, STM32_GTIM_CCR3_OFFSET), + pwm_getreg(priv, STM32_GTIM_CCR4_OFFSET)); +#if defined(CONFIG_STM32_TIM1_PWM) || defined(CONFIG_STM32_TIM8_PWM) if (priv->timtype == TIMTYPE_ADVANCED) { pwminfo(" RCR: %04x BDTR: %04x DCR: %04x DMAR: %04x\n", - pwm_getreg(priv, STM32L4_ATIM_RCR_OFFSET), - pwm_getreg(priv, STM32L4_ATIM_BDTR_OFFSET), - pwm_getreg(priv, STM32L4_ATIM_DCR_OFFSET), - pwm_getreg(priv, STM32L4_ATIM_DMAR_OFFSET)); + pwm_getreg(priv, STM32_ATIM_RCR_OFFSET), + pwm_getreg(priv, STM32_ATIM_BDTR_OFFSET), + pwm_getreg(priv, STM32_ATIM_DCR_OFFSET), + pwm_getreg(priv, STM32_ATIM_DMAR_OFFSET)); } else #endif { pwminfo(" DCR: %04x DMAR: %04x\n", - pwm_getreg(priv, STM32L4_GTIM_DCR_OFFSET), - pwm_getreg(priv, STM32L4_GTIM_DMAR_OFFSET)); + pwm_getreg(priv, STM32_GTIM_DCR_OFFSET), + pwm_getreg(priv, STM32_GTIM_DMAR_OFFSET)); } } } @@ -1520,7 +1520,7 @@ static void pwm_dumpregs(struct pwm_lowerhalf_s *dev, static int pwm_ccr_update(struct pwm_lowerhalf_s *dev, uint8_t index, uint32_t ccr) { - struct stm32l4_pwmtimer_s *priv = (struct stm32l4_pwmtimer_s *)dev; + struct stm32_pwmtimer_s *priv = (struct stm32_pwmtimer_s *)dev; uint32_t offset = 0; #ifdef HAVE_LPTIM @@ -1528,7 +1528,7 @@ static int pwm_ccr_update(struct pwm_lowerhalf_s *dev, uint8_t index, { /* REVISIT: What about index? Is it necessary for LPTIM? */ - offset = STM32L4_LPTIM_CMP_OFFSET; + offset = STM32_LPTIM_CMP_OFFSET; pwm_putreg(priv, offset, ccr); return OK; @@ -1547,39 +1547,39 @@ static int pwm_ccr_update(struct pwm_lowerhalf_s *dev, uint8_t index, switch (index) { - case STM32L4_PWM_CHAN1: + case STM32_PWM_CHAN1: { - offset = STM32L4_GTIM_CCR1_OFFSET; + offset = STM32_GTIM_CCR1_OFFSET; break; } - case STM32L4_PWM_CHAN2: + case STM32_PWM_CHAN2: { - offset = STM32L4_GTIM_CCR2_OFFSET; + offset = STM32_GTIM_CCR2_OFFSET; break; } - case STM32L4_PWM_CHAN3: + case STM32_PWM_CHAN3: { - offset = STM32L4_GTIM_CCR3_OFFSET; + offset = STM32_GTIM_CCR3_OFFSET; break; } - case STM32L4_PWM_CHAN4: + case STM32_PWM_CHAN4: { - offset = STM32L4_GTIM_CCR4_OFFSET; + offset = STM32_GTIM_CCR4_OFFSET; break; } - case STM32L4_PWM_CHAN5: + case STM32_PWM_CHAN5: { - offset = STM32L4_ATIM_CCR5_OFFSET; + offset = STM32_ATIM_CCR5_OFFSET; break; } - case STM32L4_PWM_CHAN6: + case STM32_PWM_CHAN6: { - offset = STM32L4_ATIM_CCR6_OFFSET; + offset = STM32_ATIM_CCR6_OFFSET; break; } @@ -1601,47 +1601,47 @@ static int pwm_ccr_update(struct pwm_lowerhalf_s *dev, uint8_t index, * Name: pwm_ccr_get ****************************************************************************/ -#ifdef CONFIG_STM32L4_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS static uint32_t pwm_ccr_get(struct pwm_lowerhalf_s *dev, uint8_t index) { - struct stm32l4_pwmtimer_s *priv = (struct stm32l4_pwmtimer_s *)dev; + struct stm32_pwmtimer_s *priv = (struct stm32_pwmtimer_s *)dev; uint32_t offset = 0; switch (index) { - case STM32L4_PWM_CHAN1: + case STM32_PWM_CHAN1: { - offset = STM32L4_GTIM_CCR1_OFFSET; + offset = STM32_GTIM_CCR1_OFFSET; break; } - case STM32L4_PWM_CHAN2: + case STM32_PWM_CHAN2: { - offset = STM32L4_GTIM_CCR2_OFFSET; + offset = STM32_GTIM_CCR2_OFFSET; break; } - case STM32L4_PWM_CHAN3: + case STM32_PWM_CHAN3: { - offset = STM32L4_GTIM_CCR3_OFFSET; + offset = STM32_GTIM_CCR3_OFFSET; break; } - case STM32L4_PWM_CHAN4: + case STM32_PWM_CHAN4: { - offset = STM32L4_GTIM_CCR4_OFFSET; + offset = STM32_GTIM_CCR4_OFFSET; break; } - case STM32L4_PWM_CHAN5: + case STM32_PWM_CHAN5: { - offset = STM32L4_ATIM_CCR5_OFFSET; + offset = STM32_ATIM_CCR5_OFFSET; break; } - case STM32L4_PWM_CHAN6: + case STM32_PWM_CHAN6: { - offset = STM32L4_ATIM_CCR6_OFFSET; + offset = STM32_ATIM_CCR6_OFFSET; break; } @@ -1656,7 +1656,7 @@ static uint32_t pwm_ccr_get(struct pwm_lowerhalf_s *dev, uint8_t index) return pwm_getreg(priv, offset); } -#endif /* CONFIG_STM32L4_PWM_LL_OPS */ +#endif /* CONFIG_STM32_PWM_LL_OPS */ /**************************************************************************** * Name: pwm_arr_update @@ -1664,17 +1664,17 @@ static uint32_t pwm_ccr_get(struct pwm_lowerhalf_s *dev, uint8_t index) static int pwm_arr_update(struct pwm_lowerhalf_s *dev, uint32_t arr) { - struct stm32l4_pwmtimer_s *priv = (struct stm32l4_pwmtimer_s *)dev; + struct stm32_pwmtimer_s *priv = (struct stm32_pwmtimer_s *)dev; /* Update ARR register */ if (priv->timtype == TIMTYPE_LOWPOWER) { - pwm_putreg(priv, STM32L4_LPTIM_ARR_OFFSET, arr); + pwm_putreg(priv, STM32_LPTIM_ARR_OFFSET, arr); } else { - pwm_putreg(priv, STM32L4_GTIM_ARR_OFFSET, arr); + pwm_putreg(priv, STM32_GTIM_ARR_OFFSET, arr); } return OK; @@ -1686,15 +1686,15 @@ static int pwm_arr_update(struct pwm_lowerhalf_s *dev, uint32_t arr) static uint32_t pwm_arr_get(struct pwm_lowerhalf_s *dev) { - struct stm32l4_pwmtimer_s *priv = (struct stm32l4_pwmtimer_s *)dev; + struct stm32_pwmtimer_s *priv = (struct stm32_pwmtimer_s *)dev; if (priv->timtype == TIMTYPE_LOWPOWER) { - return pwm_getreg(priv, STM32L4_LPTIM_ARR_OFFSET); + return pwm_getreg(priv, STM32_LPTIM_ARR_OFFSET); } else { - return pwm_getreg(priv, STM32L4_GTIM_ARR_OFFSET); + return pwm_getreg(priv, STM32_GTIM_ARR_OFFSET); } } @@ -1717,7 +1717,7 @@ static uint32_t pwm_arr_get(struct pwm_lowerhalf_s *dev) static int pwm_duty_update(struct pwm_lowerhalf_s *dev, uint8_t channel, ub16_t duty) { - struct stm32l4_pwmtimer_s *priv = (struct stm32l4_pwmtimer_s *)dev; + struct stm32_pwmtimer_s *priv = (struct stm32_pwmtimer_s *)dev; uint32_t reload = 0; uint32_t ccr = 0; @@ -1730,6 +1730,11 @@ static int pwm_duty_update(struct pwm_lowerhalf_s *dev, uint8_t channel, pwminfo("TIM%u channel: %u duty: %08" PRIx32 "\n", priv->timid, channel, duty); +#ifndef CONFIG_STM32_PWM_MULTICHAN + DEBUGASSERT(channel == priv->channels[0].channel); + DEBUGASSERT(duty >= 0 && duty < uitoub16(100)); +#endif + /* Get the reload values */ reload = pwm_arr_get(dev); @@ -1756,7 +1761,7 @@ static int pwm_duty_update(struct pwm_lowerhalf_s *dev, uint8_t channel, static int pwm_timer_enable(struct pwm_lowerhalf_s *dev, bool state) { - struct stm32l4_pwmtimer_s *priv = (struct stm32l4_pwmtimer_s *)dev; + struct stm32_pwmtimer_s *priv = (struct stm32_pwmtimer_s *)dev; #ifdef HAVE_LPTIM if (priv->timtype != TIMTYPE_LOWPOWER) @@ -1766,13 +1771,13 @@ static int pwm_timer_enable(struct pwm_lowerhalf_s *dev, bool state) { /* Enable timer counter */ - pwm_modifyreg(priv, STM32L4_GTIM_CR1_OFFSET, 0, GTIM_CR1_CEN); + pwm_modifyreg(priv, STM32_GTIM_CR1_OFFSET, 0, GTIM_CR1_CEN); } else { /* Disable timer counter */ - pwm_modifyreg(priv, STM32L4_GTIM_CR1_OFFSET, GTIM_CR1_CEN, 0); + pwm_modifyreg(priv, STM32_GTIM_CR1_OFFSET, GTIM_CR1_CEN, 0); } #ifdef HAVE_LPTIM } @@ -1782,13 +1787,13 @@ static int pwm_timer_enable(struct pwm_lowerhalf_s *dev, bool state) { /* Enable timer counter */ - pwm_modifyreg(priv, STM32L4_LPTIM_CR_OFFSET, 0, LPTIM_CR_ENABLE); + pwm_modifyreg(priv, STM32_LPTIM_CR_OFFSET, 0, LPTIM_CR_ENABLE); } else { /* Disable timer counter */ - pwm_modifyreg(priv, STM32L4_LPTIM_CR_OFFSET, LPTIM_CR_ENABLE, 0); + pwm_modifyreg(priv, STM32_LPTIM_CR_OFFSET, LPTIM_CR_ENABLE, 0); } } #endif @@ -1807,7 +1812,7 @@ static int pwm_timer_enable(struct pwm_lowerhalf_s *dev, bool state) static int pwm_frequency_update(struct pwm_lowerhalf_s *dev, uint32_t frequency) { - struct stm32l4_pwmtimer_s *priv = (struct stm32l4_pwmtimer_s *)dev; + struct stm32_pwmtimer_s *priv = (struct stm32_pwmtimer_s *)dev; uint32_t reload = 0; uint32_t timclk = 0; uint32_t prescaler = 0; @@ -1849,9 +1854,9 @@ static int pwm_frequency_update(struct pwm_lowerhalf_s *dev, * intended so multiply by x2 */ - if ((priv->mode == STM32L4_TIMMODE_CENTER1) || - (priv->mode == STM32L4_TIMMODE_CENTER2) || - (priv->mode == STM32L4_TIMMODE_CENTER3)) + if ((priv->mode == STM32_TIMMODE_CENTER1) || + (priv->mode == STM32_TIMMODE_CENTER2) || + (priv->mode == STM32_TIMMODE_CENTER3)) { frequency = frequency * 2; } @@ -1889,7 +1894,7 @@ static int pwm_frequency_update(struct pwm_lowerhalf_s *dev, /* Set the reload and prescaler values */ pwm_arr_update(dev, reload); - pwm_putreg(priv, STM32L4_GTIM_PSC_OFFSET, (uint16_t)(prescaler - 1)); + pwm_putreg(priv, STM32_GTIM_PSC_OFFSET, (uint16_t)(prescaler - 1)); return OK; } @@ -1906,7 +1911,7 @@ static int pwm_frequency_update(struct pwm_lowerhalf_s *dev, static int pwm_lp_frequency_update(struct pwm_lowerhalf_s *dev, uint32_t frequency) { - struct stm32l4_pwmtimer_s *priv = (struct stm32l4_pwmtimer_s *)dev; + struct stm32_pwmtimer_s *priv = (struct stm32_pwmtimer_s *)dev; /* Calculated values */ @@ -1961,12 +1966,12 @@ static int pwm_lp_frequency_update(struct pwm_lowerhalf_s *dev, /* Set the prescaler value */ - cfgr = pwm_getreg(priv, STM32L4_LPTIM_CFGR_OFFSET); + cfgr = pwm_getreg(priv, STM32_LPTIM_CFGR_OFFSET); cfgr &= ~LPTIM_CFGR_PRESC_MASK; cfgr |= (prescaler << LPTIM_CFGR_PRESC_SHIFT); - pwm_putreg(priv, STM32L4_LPTIM_CFGR_OFFSET, cfgr); + pwm_putreg(priv, STM32_LPTIM_CFGR_OFFSET, cfgr); return OK; } @@ -1980,7 +1985,7 @@ static int pwm_lp_frequency_update(struct pwm_lowerhalf_s *dev, * ****************************************************************************/ -static int pwm_timer_configure(struct stm32l4_pwmtimer_s *priv) +static int pwm_timer_configure(struct stm32_pwmtimer_s *priv) { uint16_t cr1 = 0; int ret = OK; @@ -1994,7 +1999,7 @@ static int pwm_timer_configure(struct stm32l4_pwmtimer_s *priv) * 15-17 CKD[1:0] ARPE OPM URS UDIS CEN */ - cr1 = pwm_getreg(priv, STM32L4_GTIM_CR1_OFFSET); + cr1 = pwm_getreg(priv, STM32_GTIM_CR1_OFFSET); /* Set the counter mode for the advanced timers (1,8) and most general * purpose timers (all 2-5, but not 9-17), i.e., all but TIMTYPE_COUNTUP16 @@ -2016,31 +2021,31 @@ static int pwm_timer_configure(struct stm32l4_pwmtimer_s *priv) switch (priv->mode) { - case STM32L4_TIMMODE_COUNTUP: + case STM32_TIMMODE_COUNTUP: { cr1 |= GTIM_CR1_EDGE; break; } - case STM32L4_TIMMODE_COUNTDOWN: + case STM32_TIMMODE_COUNTDOWN: { cr1 |= GTIM_CR1_EDGE | GTIM_CR1_DIR; break; } - case STM32L4_TIMMODE_CENTER1: + case STM32_TIMMODE_CENTER1: { cr1 |= GTIM_CR1_CENTER1; break; } - case STM32L4_TIMMODE_CENTER2: + case STM32_TIMMODE_CENTER2: { cr1 |= GTIM_CR1_CENTER2; break; } - case STM32L4_TIMMODE_CENTER3: + case STM32_TIMMODE_CENTER3: { cr1 |= GTIM_CR1_CENTER3; break; @@ -2064,7 +2069,7 @@ static int pwm_timer_configure(struct stm32l4_pwmtimer_s *priv) /* Write CR1 */ - pwm_putreg(priv, STM32L4_GTIM_CR1_OFFSET, cr1); + pwm_putreg(priv, STM32_GTIM_CR1_OFFSET, cr1); errout: return ret; @@ -2081,7 +2086,7 @@ static int pwm_timer_configure(struct stm32l4_pwmtimer_s *priv) static int pwm_mode_configure(struct pwm_lowerhalf_s *dev, uint8_t channel, uint32_t mode) { - struct stm32l4_pwmtimer_s *priv = (struct stm32l4_pwmtimer_s *)dev; + struct stm32_pwmtimer_s *priv = (struct stm32_pwmtimer_s *)dev; uint32_t chanmode = 0; uint32_t ocmode = 0; uint32_t ccmr = 0; @@ -2104,76 +2109,76 @@ static int pwm_mode_configure(struct pwm_lowerhalf_s *dev, switch (mode) { - case STM32L4_CHANMODE_FRZN: + case STM32_CHANMODE_FRZN: { chanmode = GTIM_CCMR_MODE_FRZN; break; } - case STM32L4_CHANMODE_CHACT: + case STM32_CHANMODE_CHACT: { chanmode = GTIM_CCMR_MODE_CHACT; break; } - case STM32L4_CHANMODE_CHINACT: + case STM32_CHANMODE_CHINACT: { chanmode = GTIM_CCMR_MODE_CHINACT; break; } - case STM32L4_CHANMODE_OCREFTOG: + case STM32_CHANMODE_OCREFTOG: { chanmode = GTIM_CCMR_MODE_OCREFTOG; break; } - case STM32L4_CHANMODE_OCREFLO: + case STM32_CHANMODE_OCREFLO: { chanmode = GTIM_CCMR_MODE_OCREFLO; break; } - case STM32L4_CHANMODE_OCREFHI: + case STM32_CHANMODE_OCREFHI: { chanmode = GTIM_CCMR_MODE_OCREFHI; break; } - case STM32L4_CHANMODE_PWM1: + case STM32_CHANMODE_PWM1: { chanmode = GTIM_CCMR_MODE_PWM1; break; } - case STM32L4_CHANMODE_PWM2: + case STM32_CHANMODE_PWM2: { chanmode = GTIM_CCMR_MODE_PWM2; break; } - case STM32L4_CHANMODE_COMBINED1: + case STM32_CHANMODE_COMBINED1: { chanmode = ATIM_CCMR_MODE_COMBINED1; ocmbit = true; break; } - case STM32L4_CHANMODE_COMBINED2: + case STM32_CHANMODE_COMBINED2: { chanmode = ATIM_CCMR_MODE_COMBINED2; ocmbit = true; break; } - case STM32L4_CHANMODE_ASYMMETRIC1: + case STM32_CHANMODE_ASYMMETRIC1: { chanmode = ATIM_CCMR_MODE_ASYMMETRIC1; ocmbit = true; break; } - case STM32L4_CHANMODE_ASYMMETRIC2: + case STM32_CHANMODE_ASYMMETRIC2: { chanmode = ATIM_CCMR_MODE_ASYMMETRIC2; ocmbit = true; @@ -2194,24 +2199,24 @@ static int pwm_mode_configure(struct pwm_lowerhalf_s *dev, { /* Get CCMR offset */ - case STM32L4_PWM_CHAN1: - case STM32L4_PWM_CHAN2: + case STM32_PWM_CHAN1: + case STM32_PWM_CHAN2: { - offset = STM32L4_GTIM_CCMR1_OFFSET; + offset = STM32_GTIM_CCMR1_OFFSET; break; } - case STM32L4_PWM_CHAN3: - case STM32L4_PWM_CHAN4: + case STM32_PWM_CHAN3: + case STM32_PWM_CHAN4: { - offset = STM32L4_GTIM_CCMR2_OFFSET; + offset = STM32_GTIM_CCMR2_OFFSET; break; } - case STM32L4_PWM_CHAN5: - case STM32L4_PWM_CHAN6: + case STM32_PWM_CHAN5: + case STM32_PWM_CHAN6: { - offset = STM32L4_ATIM_CCMR3_OFFSET; + offset = STM32_ATIM_CCMR3_OFFSET; break; } @@ -2235,9 +2240,9 @@ static int pwm_mode_configure(struct pwm_lowerhalf_s *dev, { /* Configure channel 1/3/5 */ - case STM32L4_PWM_CHAN1: - case STM32L4_PWM_CHAN3: - case STM32L4_PWM_CHAN5: + case STM32_PWM_CHAN1: + case STM32_PWM_CHAN3: + case STM32_PWM_CHAN5: { /* Reset current channel 1/3/5 mode configuration */ @@ -2271,9 +2276,9 @@ static int pwm_mode_configure(struct pwm_lowerhalf_s *dev, /* Configure channel 2/4/6 */ - case STM32L4_PWM_CHAN2: - case STM32L4_PWM_CHAN4: - case STM32L4_PWM_CHAN6: + case STM32_PWM_CHAN2: + case STM32_PWM_CHAN4: + case STM32_PWM_CHAN6: { /* Reset current channel 2/4/6 mode configuration */ @@ -2326,7 +2331,7 @@ static int pwm_mode_configure(struct pwm_lowerhalf_s *dev, * ****************************************************************************/ -static int pwm_output_configure(struct stm32l4_pwmtimer_s *priv, +static int pwm_output_configure(struct stm32_pwmtimer_s *priv, uint8_t channel) { uint32_t cr2 = 0; @@ -2334,8 +2339,8 @@ static int pwm_output_configure(struct stm32l4_pwmtimer_s *priv, /* Get current registers state */ - cr2 = pwm_getreg(priv, STM32L4_GTIM_CR2_OFFSET); - ccer = pwm_getreg(priv, STM32L4_GTIM_CCER_OFFSET); + cr2 = pwm_getreg(priv, STM32_GTIM_CR2_OFFSET); + ccer = pwm_getreg(priv, STM32_GTIM_CCER_OFFSET); /* | OISx/OISxN | IDLE | for ADVANCED and COUNTUP16 | CR2 register * | CCxP/CCxNP | POL | all PWM timers | CCER register @@ -2343,7 +2348,7 @@ static int pwm_output_configure(struct stm32l4_pwmtimer_s *priv, /* Configure output polarity (all PWM timers) */ - if (priv->channels[channel - 1].out1.pol == STM32L4_POL_NEG) + if (priv->channels[channel - 1].out1.pol == STM32_POL_NEG) { ccer |= (GTIM_CCER_CC1P << ((channel - 1) * 4)); } @@ -2358,7 +2363,7 @@ static int pwm_output_configure(struct stm32l4_pwmtimer_s *priv, { /* Configure output IDLE State */ - if (priv->channels[channel - 1].out1.idle == STM32L4_IDLE_ACTIVE) + if (priv->channels[channel - 1].out1.idle == STM32_IDLE_ACTIVE) { cr2 |= (ATIM_CR2_OIS1 << ((channel - 1) * 2)); } @@ -2370,7 +2375,7 @@ static int pwm_output_configure(struct stm32l4_pwmtimer_s *priv, #ifdef HAVE_PWM_COMPLEMENTARY /* Configure complementary output IDLE state */ - if (priv->channels[channel - 1].out2.idle == STM32L4_IDLE_ACTIVE) + if (priv->channels[channel - 1].out2.idle == STM32_IDLE_ACTIVE) { cr2 |= (ATIM_CR2_OIS1N << ((channel - 1) * 2)); } @@ -2381,7 +2386,7 @@ static int pwm_output_configure(struct stm32l4_pwmtimer_s *priv, /* Configure complementary output polarity */ - if (priv->channels[channel - 1].out2.pol == STM32L4_POL_NEG) + if (priv->channels[channel - 1].out2.pol == STM32_POL_NEG) { ccer |= (ATIM_CCER_CC1NP << ((channel - 1) * 4)); } @@ -2417,8 +2422,8 @@ static int pwm_output_configure(struct stm32l4_pwmtimer_s *priv, /* Write registers */ - pwm_modifyreg(priv, STM32L4_GTIM_CR2_OFFSET, 0, cr2); - pwm_modifyreg(priv, STM32L4_GTIM_CCER_OFFSET, 0, ccer); + pwm_modifyreg(priv, STM32_GTIM_CR2_OFFSET, 0, cr2); + pwm_modifyreg(priv, STM32_GTIM_CCER_OFFSET, 0, ccer); return OK; } @@ -2434,7 +2439,7 @@ static int pwm_output_configure(struct stm32l4_pwmtimer_s *priv, * * Input Parameters: * dev - A reference to the lower half PWM driver state structure - * outputs - outputs to set (look at enum stm32l4_chan_e in stm32l4_pwm.h) + * outputs - outputs to set (look at enum stm32_chan_e in stm32l4_pwm.h) * state - Enable/disable operation * ****************************************************************************/ @@ -2442,29 +2447,29 @@ static int pwm_output_configure(struct stm32l4_pwmtimer_s *priv, static int pwm_outputs_enable(struct pwm_lowerhalf_s *dev, uint16_t outputs, bool state) { - struct stm32l4_pwmtimer_s *priv = (struct stm32l4_pwmtimer_s *)dev; + struct stm32_pwmtimer_s *priv = (struct stm32_pwmtimer_s *)dev; uint32_t ccer = 0; uint32_t regval = 0; /* Get current register state */ - ccer = pwm_getreg(priv, STM32L4_GTIM_CCER_OFFSET); + ccer = pwm_getreg(priv, STM32_GTIM_CCER_OFFSET); /* Get outputs configuration */ - regval |= ((outputs & STM32L4_PWM_OUT1) ? GTIM_CCER_CC1E : 0); - regval |= ((outputs & STM32L4_PWM_OUT1N) ? ATIM_CCER_CC1NE : 0); - regval |= ((outputs & STM32L4_PWM_OUT2) ? GTIM_CCER_CC2E : 0); - regval |= ((outputs & STM32L4_PWM_OUT2N) ? ATIM_CCER_CC2NE : 0); - regval |= ((outputs & STM32L4_PWM_OUT3) ? GTIM_CCER_CC3E : 0); - regval |= ((outputs & STM32L4_PWM_OUT3N) ? ATIM_CCER_CC3NE : 0); - regval |= ((outputs & STM32L4_PWM_OUT4) ? GTIM_CCER_CC4E : 0); + regval |= ((outputs & STM32_PWM_OUT1) ? GTIM_CCER_CC1E : 0); + regval |= ((outputs & STM32_PWM_OUT1N) ? ATIM_CCER_CC1NE : 0); + regval |= ((outputs & STM32_PWM_OUT2) ? GTIM_CCER_CC2E : 0); + regval |= ((outputs & STM32_PWM_OUT2N) ? ATIM_CCER_CC2NE : 0); + regval |= ((outputs & STM32_PWM_OUT3) ? GTIM_CCER_CC3E : 0); + regval |= ((outputs & STM32_PWM_OUT3N) ? ATIM_CCER_CC3NE : 0); + regval |= ((outputs & STM32_PWM_OUT4) ? GTIM_CCER_CC4E : 0); /* NOTE: CC4N does not exist, but some docs show configuration bits for it */ - regval |= ((outputs & STM32L4_PWM_OUT5) ? ATIM_CCER_CC5E : 0); - regval |= ((outputs & STM32L4_PWM_OUT6) ? ATIM_CCER_CC6E : 0); + regval |= ((outputs & STM32_PWM_OUT5) ? ATIM_CCER_CC5E : 0); + regval |= ((outputs & STM32_PWM_OUT6) ? ATIM_CCER_CC6E : 0); if (state == true) { @@ -2481,12 +2486,12 @@ static int pwm_outputs_enable(struct pwm_lowerhalf_s *dev, /* Write register */ - pwm_putreg(priv, STM32L4_GTIM_CCER_OFFSET, ccer); + pwm_putreg(priv, STM32_GTIM_CCER_OFFSET, ccer); return OK; } -#if defined(HAVE_PWM_COMPLEMENTARY) && defined(CONFIG_STM32L4_PWM_LL_OPS) +#if defined(HAVE_PWM_COMPLEMENTARY) && defined(CONFIG_STM32_PWM_LL_OPS) /**************************************************************************** * Name: pwm_deadtime_update @@ -2494,7 +2499,7 @@ static int pwm_outputs_enable(struct pwm_lowerhalf_s *dev, static int pwm_deadtime_update(struct pwm_lowerhalf_s *dev, uint8_t dt) { - struct stm32l4_pwmtimer_s *priv = (struct stm32l4_pwmtimer_s *)dev; + struct stm32_pwmtimer_s *priv = (struct stm32_pwmtimer_s *)dev; uint32_t bdtr = 0; int ret = OK; @@ -2508,7 +2513,7 @@ static int pwm_deadtime_update(struct pwm_lowerhalf_s *dev, uint8_t dt) /* Get current register state */ - bdtr = pwm_getreg(priv, STM32L4_ATIM_BDTR_OFFSET); + bdtr = pwm_getreg(priv, STM32_ATIM_BDTR_OFFSET); /* TODO: check if BDTR not locked */ @@ -2519,7 +2524,7 @@ static int pwm_deadtime_update(struct pwm_lowerhalf_s *dev, uint8_t dt) /* Write BDTR register */ - pwm_putreg(priv, STM32L4_ATIM_BDTR_OFFSET, bdtr); + pwm_putreg(priv, STM32_ATIM_BDTR_OFFSET, bdtr); errout: return ret; @@ -2536,9 +2541,9 @@ static int pwm_deadtime_update(struct pwm_lowerhalf_s *dev, uint8_t dt) static int pwm_soft_update(struct pwm_lowerhalf_s *dev) { - struct stm32l4_pwmtimer_s *priv = (struct stm32l4_pwmtimer_s *)dev; + struct stm32_pwmtimer_s *priv = (struct stm32_pwmtimer_s *)dev; - pwm_putreg(priv, STM32L4_GTIM_EGR_OFFSET, GTIM_EGR_UG); + pwm_putreg(priv, STM32_GTIM_EGR_OFFSET, GTIM_EGR_UG); return OK; } @@ -2559,19 +2564,19 @@ static int pwm_soft_update(struct pwm_lowerhalf_s *dev) static int pwm_soft_break(struct pwm_lowerhalf_s *dev, bool state) { - struct stm32l4_pwmtimer_s *priv = (struct stm32l4_pwmtimer_s *)dev; + struct stm32_pwmtimer_s *priv = (struct stm32_pwmtimer_s *)dev; if (state == true) { /* Reset MOE bit */ - pwm_modifyreg(priv, STM32L4_ATIM_BDTR_OFFSET, ATIM_BDTR_MOE, 0); + pwm_modifyreg(priv, STM32_ATIM_BDTR_OFFSET, ATIM_BDTR_MOE, 0); } else { /* Set MOE bit */ - pwm_modifyreg(priv, STM32L4_ATIM_BDTR_OFFSET, 0, ATIM_BDTR_MOE); + pwm_modifyreg(priv, STM32_ATIM_BDTR_OFFSET, 0, ATIM_BDTR_MOE); } return OK; @@ -2586,7 +2591,7 @@ static int pwm_soft_break(struct pwm_lowerhalf_s *dev, bool state) ****************************************************************************/ static uint16_t -pwm_outputs_from_channels(struct stm32l4_pwmtimer_s *priv) +pwm_outputs_from_channels(struct stm32_pwmtimer_s *priv) { uint16_t outputs = 0; uint8_t channel = 0; @@ -2606,7 +2611,7 @@ pwm_outputs_from_channels(struct stm32l4_pwmtimer_s *priv) if (priv->channels[i].out1.in_use == 1) { - outputs |= (STM32L4_PWM_OUT1 << ((channel - 1) * 2)); + outputs |= (STM32_PWM_OUT1 << ((channel - 1) * 2)); } #ifdef HAVE_PWM_COMPLEMENTARY @@ -2614,7 +2619,7 @@ pwm_outputs_from_channels(struct stm32l4_pwmtimer_s *priv) if (priv->channels[i].out2.in_use == 1) { - outputs |= (STM32L4_PWM_OUT1N << ((channel - 1) * 2)); + outputs |= (STM32_PWM_OUT1N << ((channel - 1) * 2)); } #endif } @@ -2636,7 +2641,7 @@ pwm_outputs_from_channels(struct stm32l4_pwmtimer_s *priv) * ****************************************************************************/ -static int pwm_break_dt_configure(struct stm32l4_pwmtimer_s *priv) +static int pwm_break_dt_configure(struct stm32_pwmtimer_s *priv) { uint32_t bdtr = 0; @@ -2644,7 +2649,7 @@ static int pwm_break_dt_configure(struct stm32l4_pwmtimer_s *priv) * should be no basic timers in this context */ - pwm_modifyreg(priv, STM32L4_GTIM_CR1_OFFSET, GTIM_CR1_CKD_MASK, + pwm_modifyreg(priv, STM32_GTIM_CR1_OFFSET, GTIM_CR1_CKD_MASK, priv->t_dts << GTIM_CR1_CKD_SHIFT); #ifdef HAVE_PWM_COMPLEMENTARY @@ -2664,7 +2669,7 @@ static int pwm_break_dt_configure(struct stm32l4_pwmtimer_s *priv) /* Set Break 1 polarity */ - bdtr |= (priv->brk.pol1 == STM32L4_POL_NEG ? ATIM_BDTR_BKP : 0); + bdtr |= (priv->brk.pol1 == STM32_POL_NEG ? ATIM_BDTR_BKP : 0); } /* Configure Break 1 */ @@ -2677,7 +2682,7 @@ static int pwm_break_dt_configure(struct stm32l4_pwmtimer_s *priv) /* Set Break 2 polarity */ - bdtr |= (priv->brk.pol2 == STM32L4_POL_NEG ? ATIM_BDTR_BK2P : 0); + bdtr |= (priv->brk.pol2 == STM32_POL_NEG ? ATIM_BDTR_BK2P : 0); /* Configure BRK2 filter */ @@ -2699,7 +2704,7 @@ static int pwm_break_dt_configure(struct stm32l4_pwmtimer_s *priv) /* Write BDTR register at once */ - pwm_putreg(priv, STM32L4_ATIM_BDTR_OFFSET, bdtr); + pwm_putreg(priv, STM32_ATIM_BDTR_OFFSET, bdtr); return OK; } @@ -2716,7 +2721,7 @@ static int pwm_break_dt_configure(struct stm32l4_pwmtimer_s *priv) static int pwm_configure(struct pwm_lowerhalf_s *dev) { - struct stm32l4_pwmtimer_s *priv = (struct stm32l4_pwmtimer_s *)dev; + struct stm32_pwmtimer_s *priv = (struct stm32_pwmtimer_s *)dev; uint16_t outputs = 0; uint8_t j = 0; int ret = OK; @@ -2840,15 +2845,20 @@ static int pwm_configure(struct pwm_lowerhalf_s *dev) static int pwm_duty_channels_update(struct pwm_lowerhalf_s *dev, const struct pwm_info_s *info) { - struct stm32l4_pwmtimer_s *priv = (struct stm32l4_pwmtimer_s *)dev; + struct stm32_pwmtimer_s *priv = (struct stm32_pwmtimer_s *)dev; uint8_t channel = 0; ub16_t duty = 0; int ret = OK; +#ifdef CONFIG_STM32_PWM_MULTICHAN int i = 0; int j = 0; +#endif +#ifdef CONFIG_STM32_PWM_MULTICHAN for (i = 0; i < CONFIG_PWM_NCHANNELS; i++) +#endif { +#ifdef CONFIG_STM32_PWM_MULTICHAN /* Break the loop if all following channels are not configured */ if (info->channels[i].channel == -1) @@ -2881,6 +2891,10 @@ static int pwm_duty_channels_update(struct pwm_lowerhalf_s *dev, ret = -EINVAL; goto errout; } +#else + duty = info->channels[0].duty; + channel = priv->channels[0].channel; +#endif /* Update duty cycle */ @@ -2889,7 +2903,9 @@ static int pwm_duty_channels_update(struct pwm_lowerhalf_s *dev, { goto errout; } +#ifdef CONFIG_STM32_PWM_MULTICHAN } +#endif } errout: @@ -2914,16 +2930,26 @@ static int pwm_duty_channels_update(struct pwm_lowerhalf_s *dev, static int pwm_timer(struct pwm_lowerhalf_s *dev, const struct pwm_info_s *info) { - struct stm32l4_pwmtimer_s *priv = (struct stm32l4_pwmtimer_s *)dev; + struct stm32_pwmtimer_s *priv = (struct stm32_pwmtimer_s *)dev; uint16_t outputs = 0; int ret = OK; DEBUGASSERT(priv != NULL && info != NULL); +#if defined(CONFIG_STM32_PWM_MULTICHAN) pwminfo("TIM%u frequency: %" PRIu32 "\n", priv->timid, info->frequency); +#else + pwminfo("TIM%u channel: %u frequency: %" PRIu32 " duty: %08" PRIx32 "\n", + priv->timid, priv->channels[0].channel, + info->frequency, info->channels[0].duty); +#endif DEBUGASSERT(info->frequency > 0); +#ifndef CONFIG_STM32_PWM_MULTICHAN + DEBUGASSERT(info->channels[0].duty >= 0 && + info->channels[0].duty < uitoub16(100)); +#endif /* TODO: what if we have pwm running and we want disable some channels ? */ @@ -2956,7 +2982,7 @@ static int pwm_timer(struct pwm_lowerhalf_s *dev, /* Set the repetition counter to zero */ - pwm_putreg(priv, STM32L4_ATIM_RCR_OFFSET, 0); + pwm_putreg(priv, STM32_ATIM_RCR_OFFSET, 0); /* Generate an update event to reload the prescaler */ @@ -3012,16 +3038,26 @@ static int pwm_timer(struct pwm_lowerhalf_s *dev, static int pwm_lptimer(struct pwm_lowerhalf_s *dev, const struct pwm_info_s *info) { - struct stm32l4_pwmtimer_s *priv = (struct stm32l4_pwmtimer_s *)dev; + struct stm32_pwmtimer_s *priv = (struct stm32_pwmtimer_s *)dev; uint16_t cr; int ret = OK; DEBUGASSERT(priv != NULL && info != NULL); +#if defined(CONFIG_STM32_PWM_MULTICHAN) pwminfo("LPTIM%u frequency: %u\n", priv->timid, info->frequency); +#else + pwminfo("LPTIM%u channel: %u frequency: %u duty: %08x\n", + priv->timid, priv->channels[0].channel, + info->frequency, info->channels[0].duty); +#endif DEBUGASSERT(info->frequency > 0); +#ifndef CONFIG_STM32_PWM_MULTICHAN + DEBUGASSERT(info->channels[0].duty >= 0 && + info->channels[0].duty < uitoub16(100)); +#endif /* Enable again, ARR and CMP need to be written while enabled */ @@ -3035,7 +3071,11 @@ static int pwm_lptimer(struct pwm_lowerhalf_s *dev, goto errout; } +#ifdef CONFIG_STM32_PWM_MULTICHAN ub16_t duty = info->channels[0].duty; +#else + ub16_t duty = info->channels[0].duty; +#endif /* Update duty cycle */ @@ -3047,9 +3087,9 @@ static int pwm_lptimer(struct pwm_lowerhalf_s *dev, /* Start counter */ - cr = pwm_getreg(priv, STM32L4_LPTIM_CR_OFFSET); + cr = pwm_getreg(priv, STM32_LPTIM_CR_OFFSET); cr |= LPTIM_CR_CNTSTRT; - pwm_putreg(priv, STM32L4_LPTIM_CR_OFFSET, cr); + pwm_putreg(priv, STM32_LPTIM_CR_OFFSET, cr); pwm_dumpregs(dev, "After starting"); @@ -3070,7 +3110,7 @@ static int pwm_lptimer(struct pwm_lowerhalf_s *dev, * ****************************************************************************/ -static int pwm_setapbclock(struct stm32l4_pwmtimer_s *priv, +static int pwm_setapbclock(struct stm32_pwmtimer_s *priv, bool on) { uint32_t en_bit; @@ -3083,82 +3123,82 @@ static int pwm_setapbclock(struct stm32l4_pwmtimer_s *priv, { switch (priv->timid) { -#ifdef CONFIG_STM32L4_TIM1_PWM +#ifdef CONFIG_STM32_TIM1_PWM case 1: { - regaddr = STM32L4_RCC_APB2ENR; + regaddr = STM32_RCC_APB2ENR; en_bit = RCC_APB2ENR_TIM1EN; break; } #endif -#ifdef CONFIG_STM32L4_TIM2_PWM +#ifdef CONFIG_STM32_TIM2_PWM case 2: { - regaddr = STM32L4_RCC_APB1ENR1; + regaddr = STM32_RCC_APB1ENR1; en_bit = RCC_APB1ENR1_TIM2EN; break; } #endif -#ifdef CONFIG_STM32L4_TIM3_PWM +#ifdef CONFIG_STM32_TIM3_PWM case 3: { - regaddr = STM32L4_RCC_APB1ENR1; + regaddr = STM32_RCC_APB1ENR1; en_bit = RCC_APB1ENR1_TIM3EN; break; } #endif -#ifdef CONFIG_STM32L4_TIM4_PWM +#ifdef CONFIG_STM32_TIM4_PWM case 4: { - regaddr = STM32L4_RCC_APB1ENR1; + regaddr = STM32_RCC_APB1ENR1; en_bit = RCC_APB1ENR1_TIM4EN; break; } #endif -#ifdef CONFIG_STM32L4_TIM5_PWM +#ifdef CONFIG_STM32_TIM5_PWM case 5: { - regaddr = STM32L4_RCC_APB1ENR1; + regaddr = STM32_RCC_APB1ENR1; en_bit = RCC_APB1ENR1_TIM5EN; break; } #endif -#ifdef CONFIG_STM32L4_TIM8_PWM +#ifdef CONFIG_STM32_TIM8_PWM case 8: { - regaddr = STM32L4_RCC_APB2ENR; + regaddr = STM32_RCC_APB2ENR; en_bit = RCC_APB2ENR_TIM8EN; break; } #endif -#ifdef CONFIG_STM32L4_TIM15_PWM +#ifdef CONFIG_STM32_TIM15_PWM case 15: { - regaddr = STM32L4_RCC_APB2ENR; + regaddr = STM32_RCC_APB2ENR; en_bit = RCC_APB2ENR_TIM15EN; break; } #endif -#ifdef CONFIG_STM32L4_TIM16_PWM +#ifdef CONFIG_STM32_TIM16_PWM case 16: { - regaddr = STM32L4_RCC_APB2ENR; + regaddr = STM32_RCC_APB2ENR; en_bit = RCC_APB2ENR_TIM16EN; break; } #endif -#ifdef CONFIG_STM32L4_TIM17_PWM +#ifdef CONFIG_STM32_TIM17_PWM case 17: { - regaddr = STM32L4_RCC_APB2ENR; + regaddr = STM32_RCC_APB2ENR; en_bit = RCC_APB2ENR_TIM17EN; break; } @@ -3190,67 +3230,67 @@ static int pwm_setapbclock(struct stm32l4_pwmtimer_s *priv, switch (priv->timid) { -#ifdef CONFIG_STM32L4_LPTIM1_PWM +#ifdef CONFIG_STM32_LPTIM1_PWM case 1: { -#if defined(CONFIG_STM32L4_LPTIM1_CLK_APB1) +#if defined(CONFIG_STM32_LPTIM1_CLK_APB1) /* Enable APB clock for LPTIM1 */ if (on) { - modifyreg32(STM32L4_RCC_APB1ENR1, + modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_LPTIM1EN); } else { - modifyreg32(STM32L4_RCC_APB1ENR1, + modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_LPTIM1EN, 0); } clock_bits = RCC_CCIPR_LPTIM1SEL_PCLK; -#elif defined(CONFIG_STM32L4_LPTIM1_CLK_LSI) +#elif defined(CONFIG_STM32_LPTIM1_CLK_LSI) clock_bits = RCC_CCIPR_LPTIM1SEL_LSI; -#elif defined(CONFIG_STM32L4_LPTIM1_CLK_LSE) +#elif defined(CONFIG_STM32_LPTIM1_CLK_LSE) clock_bits = RCC_CCIPR_LPTIM1SEL_LSE; -#elif defined(CONFIG_STM32L4_LPTIM1_CLK_HSI) +#elif defined(CONFIG_STM32_LPTIM1_CLK_HSI) clock_bits = RCC_CCIPR_LPTIM1SEL_HSI; #endif /* Choose which clock will be used for LPTIM1 */ - modifyreg32(STM32L4_RCC_CCIPR, RCC_CCIPR_LPTIM1SEL_MASK, + modifyreg32(STM32_RCC_CCIPR, RCC_CCIPR_LPTIM1SEL_MASK, clock_bits); break; } #endif -#ifdef CONFIG_STM32L4_LPTIM2_PWM +#ifdef CONFIG_STM32_LPTIM2_PWM case 2: { -#if defined(CONFIG_STM32L4_LPTIM2_CLK_APB1) +#if defined(CONFIG_STM32_LPTIM2_CLK_APB1) /* Enable APB clock for LPTIM2 */ if (on) { - modifyreg32(STM32L4_RCC_APB1ENR2, + modifyreg32(STM32_RCC_APB1ENR2, 0, RCC_APB1ENR2_LPTIM2EN); } else { - modifyreg32(STM32L4_RCC_APB1ENR2, + modifyreg32(STM32_RCC_APB1ENR2, RCC_APB1ENR2_LPTIM2EN, 0); } clock_bits = RCC_CCIPR_LPTIM2SEL_PCLK; -#elif defined(CONFIG_STM32L4_LPTIM2_CLK_LSI) +#elif defined(CONFIG_STM32_LPTIM2_CLK_LSI) clock_bits = RCC_CCIPR_LPTIM2SEL_LSI; -#elif defined(CONFIG_STM32L4_LPTIM2_CLK_LSE) +#elif defined(CONFIG_STM32_LPTIM2_CLK_LSE) clock_bits = RCC_CCIPR_LPTIM2SEL_LSE; -#elif defined(CONFIG_STM32L4_LPTIM2_CLK_HSI) +#elif defined(CONFIG_STM32_LPTIM2_CLK_HSI) clock_bits = RCC_CCIPR_LPTIM2SEL_HSI; #endif /* Choose which clock will be used for LPTIM2 */ - modifyreg32(STM32L4_RCC_CCIPR, RCC_CCIPR_LPTIM2SEL_MASK, + modifyreg32(STM32_RCC_CCIPR, RCC_CCIPR_LPTIM2SEL_MASK, clock_bits); break; } @@ -3292,7 +3332,7 @@ static int pwm_setapbclock(struct stm32l4_pwmtimer_s *priv, static int pwm_setup(struct pwm_lowerhalf_s *dev) { - struct stm32l4_pwmtimer_s *priv = (struct stm32l4_pwmtimer_s *)dev; + struct stm32_pwmtimer_s *priv = (struct stm32_pwmtimer_s *)dev; uint32_t pincfg; int ret; int i; @@ -3321,7 +3361,7 @@ static int pwm_setup(struct pwm_lowerhalf_s *dev) pincfg = priv->channels[i].out1.pincfg; pwminfo("pincfg: %08" PRIx32 "\n", pincfg); - stm32l4_configgpio(pincfg); + stm32_configgpio(pincfg); pwm_dumpgpio(pincfg, "PWM setup"); } @@ -3331,7 +3371,7 @@ static int pwm_setup(struct pwm_lowerhalf_s *dev) pincfg = priv->channels[i].out2.pincfg; pwminfo("pincfg: %08" PRIx32 "\n", pincfg); - stm32l4_configgpio(pincfg); + stm32_configgpio(pincfg); pwm_dumpgpio(pincfg, "PWM setup"); } #endif @@ -3371,7 +3411,7 @@ static int pwm_setup(struct pwm_lowerhalf_s *dev) static int pwm_shutdown(struct pwm_lowerhalf_s *dev) { - struct stm32l4_pwmtimer_s *priv = (struct stm32l4_pwmtimer_s *)dev; + struct stm32_pwmtimer_s *priv = (struct stm32_pwmtimer_s *)dev; uint32_t pincfg = 0; int i = 0; int ret = OK; @@ -3409,7 +3449,7 @@ static int pwm_shutdown(struct pwm_lowerhalf_s *dev) pincfg &= (GPIO_PORT_MASK | GPIO_PIN_MASK); pincfg |= GPIO_INPUT | GPIO_FLOAT; - stm32l4_configgpio(pincfg); + stm32_configgpio(pincfg); } #ifdef HAVE_PWM_COMPLEMENTARY @@ -3421,7 +3461,7 @@ static int pwm_shutdown(struct pwm_lowerhalf_s *dev) pincfg &= (GPIO_PORT_MASK | GPIO_PIN_MASK); pincfg |= GPIO_INPUT | GPIO_FLOAT; - stm32l4_configgpio(pincfg); + stm32_configgpio(pincfg); } #endif } @@ -3449,12 +3489,13 @@ static int pwm_start(struct pwm_lowerhalf_s *dev, const struct pwm_info_s *info) { int ret = OK; - struct stm32l4_pwmtimer_s *priv = (struct stm32l4_pwmtimer_s *)dev; + struct stm32_pwmtimer_s *priv = (struct stm32_pwmtimer_s *)dev; /* if frequency has not changed we just update duty */ if (info->frequency == priv->frequency) { +#ifdef CONFIG_STM32_PWM_MULTICHAN int i; for (i = 0; ret == OK && i < CONFIG_PWM_NCHANNELS; i++) @@ -3474,6 +3515,10 @@ static int pwm_start(struct pwm_lowerhalf_s *dev, info->channels[i].duty); } } +#else + ret = pwm_duty_update(dev, priv->channels[0].channel, + info->channels[0].duty); +#endif /* CONFIG_STM32_PWM_MULTICHAN */ } else { @@ -3520,7 +3565,7 @@ static int pwm_start(struct pwm_lowerhalf_s *dev, static int pwm_stop(struct pwm_lowerhalf_s *dev) { - struct stm32l4_pwmtimer_s *priv = (struct stm32l4_pwmtimer_s *)dev; + struct stm32_pwmtimer_s *priv = (struct stm32_pwmtimer_s *)dev; uint32_t resetbit = 0; uint32_t regaddr; uint32_t regval; @@ -3541,51 +3586,51 @@ static int pwm_stop(struct pwm_lowerhalf_s *dev) { switch (priv->timid) { -#ifdef CONFIG_STM32L4_TIM1_PWM +#ifdef CONFIG_STM32_TIM1_PWM case 1: - regaddr = STM32L4_RCC_APB2RSTR; + regaddr = STM32_RCC_APB2RSTR; resetbit = RCC_APB2RSTR_TIM1RST; break; #endif -#ifdef CONFIG_STM32L4_TIM2_PWM +#ifdef CONFIG_STM32_TIM2_PWM case 2: - regaddr = STM32L4_RCC_APB1RSTR1; + regaddr = STM32_RCC_APB1RSTR1; resetbit = RCC_APB1RSTR1_TIM2RST; break; #endif -#ifdef CONFIG_STM32L4_TIM3_PWM +#ifdef CONFIG_STM32_TIM3_PWM case 3: - regaddr = STM32L4_RCC_APB1RSTR1; + regaddr = STM32_RCC_APB1RSTR1; resetbit = RCC_APB1RSTR1_TIM3RST; break; #endif -#ifdef CONFIG_STM32L4_TIM4_PWM +#ifdef CONFIG_STM32_TIM4_PWM case 4: - regaddr = STM32L4_RCC_APB1RSTR1; + regaddr = STM32_RCC_APB1RSTR1; resetbit = RCC_APB1RSTR1_TIM4RST; break; #endif -#ifdef CONFIG_STM32L4_TIM5_PWM +#ifdef CONFIG_STM32_TIM5_PWM case 5: - regaddr = STM32L4_RCC_APB1RSTR1; + regaddr = STM32_RCC_APB1RSTR1; resetbit = RCC_APB1RSTR1_TIM5RST; break; #endif -#ifdef CONFIG_STM32L4_TIM8_PWM +#ifdef CONFIG_STM32_TIM8_PWM case 8: - regaddr = STM32L4_RCC_APB2RSTR; + regaddr = STM32_RCC_APB2RSTR; resetbit = RCC_APB2RSTR_TIM8RST; break; #endif -#ifdef CONFIG_STM32L4_TIM16_PWM +#ifdef CONFIG_STM32_TIM16_PWM case 16: - regaddr = STM32L4_RCC_APB2RSTR; + regaddr = STM32_RCC_APB2RSTR; resetbit = RCC_APB2RSTR_TIM16RST; break; #endif -#ifdef CONFIG_STM32L4_TIM17_PWM +#ifdef CONFIG_STM32_TIM17_PWM case 17: - regaddr = STM32L4_RCC_APB2RSTR; + regaddr = STM32_RCC_APB2RSTR; resetbit = RCC_APB2RSTR_TIM17RST; break; #endif @@ -3597,15 +3642,15 @@ static int pwm_stop(struct pwm_lowerhalf_s *dev) { switch (priv->timid) { -#ifdef CONFIG_STM32L4_LPTIM1_PWM +#ifdef CONFIG_STM32_LPTIM1_PWM case 1: - regaddr = STM32L4_RCC_APB1RSTR1; + regaddr = STM32_RCC_APB1RSTR1; resetbit = RCC_APB1RSTR1_LPTIM1RST; break; #endif -#ifdef CONFIG_STM32L4_LPTIM2_PWM +#ifdef CONFIG_STM32_LPTIM2_PWM case 2: - regaddr = STM32L4_RCC_APB1RSTR2; + regaddr = STM32_RCC_APB1RSTR2; resetbit = RCC_APB1RSTR2_LPTIM2RST; break; #endif @@ -3626,8 +3671,8 @@ static int pwm_stop(struct pwm_lowerhalf_s *dev) /* Disable further interrupts and stop the timer */ - pwm_putreg(priv, STM32L4_GTIM_DIER_OFFSET, 0); - pwm_putreg(priv, STM32L4_GTIM_SR_OFFSET, 0); + pwm_putreg(priv, STM32_GTIM_DIER_OFFSET, 0); + pwm_putreg(priv, STM32_GTIM_SR_OFFSET, 0); /* Reset the timer - stopping the output and putting the timer back * into a state where pwm_start() can be called. @@ -3667,7 +3712,7 @@ static int pwm_ioctl(struct pwm_lowerhalf_s *dev, int cmd, unsigned long arg) { #ifdef CONFIG_DEBUG_PWM_INFO - struct stm32l4_pwmtimer_s *priv = (struct stm32l4_pwmtimer_s *)dev; + struct stm32_pwmtimer_s *priv = (struct stm32_pwmtimer_s *)dev; /* There are no platform-specific ioctl commands */ @@ -3681,7 +3726,7 @@ static int pwm_ioctl(struct pwm_lowerhalf_s *dev, int cmd, ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_pwminitialize + * Name: stm32_pwminitialize * * Description: * Initialize one timer for use with the upper_level PWM driver. @@ -3697,15 +3742,15 @@ static int pwm_ioctl(struct pwm_lowerhalf_s *dev, int cmd, * ****************************************************************************/ -struct pwm_lowerhalf_s *stm32l4_pwminitialize(int timer) +struct pwm_lowerhalf_s *stm32_pwminitialize(int timer) { - struct stm32l4_pwmtimer_s *lower; + struct stm32_pwmtimer_s *lower; pwminfo("TIM%u\n", timer); switch (timer) { -#ifdef CONFIG_STM32L4_TIM1_PWM +#ifdef CONFIG_STM32_TIM1_PWM case 1: lower = &g_pwm1dev; @@ -3714,31 +3759,31 @@ struct pwm_lowerhalf_s *stm32l4_pwminitialize(int timer) break; #endif -#ifdef CONFIG_STM32L4_TIM2_PWM +#ifdef CONFIG_STM32_TIM2_PWM case 2: lower = &g_pwm2dev; break; #endif -#ifdef CONFIG_STM32L4_TIM3_PWM +#ifdef CONFIG_STM32_TIM3_PWM case 3: lower = &g_pwm3dev; break; #endif -#ifdef CONFIG_STM32L4_TIM4_PWM +#ifdef CONFIG_STM32_TIM4_PWM case 4: lower = &g_pwm4dev; break; #endif -#ifdef CONFIG_STM32L4_TIM5_PWM +#ifdef CONFIG_STM32_TIM5_PWM case 5: lower = &g_pwm5dev; break; #endif -#ifdef CONFIG_STM32L4_TIM8_PWM +#ifdef CONFIG_STM32_TIM8_PWM case 8: lower = &g_pwm8dev; @@ -3747,19 +3792,19 @@ struct pwm_lowerhalf_s *stm32l4_pwminitialize(int timer) break; #endif -#ifdef CONFIG_STM32L4_TIM15_PWM +#ifdef CONFIG_STM32_TIM15_PWM case 15: lower = &g_pwm15dev; break; #endif -#ifdef CONFIG_STM32L4_TIM16_PWM +#ifdef CONFIG_STM32_TIM16_PWM case 16: lower = &g_pwm16dev; break; #endif -#ifdef CONFIG_STM32L4_TIM17_PWM +#ifdef CONFIG_STM32_TIM17_PWM case 17: lower = &g_pwm17dev; break; @@ -3774,7 +3819,7 @@ struct pwm_lowerhalf_s *stm32l4_pwminitialize(int timer) } /**************************************************************************** - * Name: stm32l4_lp_pwminitialize + * Name: stm32_lp_pwminitialize * * Description: * Initialize one low-power timer for use with the upper_level PWM driver. @@ -3791,21 +3836,21 @@ struct pwm_lowerhalf_s *stm32l4_pwminitialize(int timer) ****************************************************************************/ #ifdef HAVE_LPTIM -struct pwm_lowerhalf_s *stm32l4_lp_pwminitialize(int timer) +struct pwm_lowerhalf_s *stm32_lp_pwminitialize(int timer) { - struct stm32l4_pwmtimer_s *lower; + struct stm32_pwmtimer_s *lower; pwminfo("LPTIM%u\n", timer); switch (timer) { -#ifdef CONFIG_STM32L4_LPTIM1_PWM +#ifdef CONFIG_STM32_LPTIM1_PWM case 1: lower = &g_pwmlp1dev; break; #endif -#ifdef CONFIG_STM32L4_LPTIM2_PWM +#ifdef CONFIG_STM32_LPTIM2_PWM case 2: lower = &g_pwmlp2dev; break; @@ -3820,4 +3865,4 @@ struct pwm_lowerhalf_s *stm32l4_lp_pwminitialize(int timer) } #endif /* HAVE_LPTIM */ -#endif /* CONFIG_STM32L4_TIMn_PWM, n = 1,...,17 */ +#endif /* CONFIG_STM32_TIMn_PWM, n = 1,...,17 */ diff --git a/arch/arm/src/stm32l4/stm32l4_pwm.h b/arch/arm/src/stm32l4/stm32l4_pwm.h index 14c75affd5f17..71fa1ed14689a 100644 --- a/arch/arm/src/stm32l4/stm32l4_pwm.h +++ b/arch/arm/src/stm32l4/stm32l4_pwm.h @@ -50,72 +50,72 @@ /* Timer devices may be used for different purposes. One special purpose is * to generate modulated outputs for such things as motor control. If - * CONFIG_STM32L4_TIMn is defined then the CONFIG_STM32L4_TIMn_PWM must also + * CONFIG_STM32_TIMn is defined then the CONFIG_STM32_TIMn_PWM must also * be defined to indicate that timer "n" is intended to be used for pulsed * output signal generation. */ -#ifndef CONFIG_STM32L4_TIM1 -# undef CONFIG_STM32L4_TIM1_PWM +#ifndef CONFIG_STM32_TIM1 +# undef CONFIG_STM32_TIM1_PWM #endif -#ifndef CONFIG_STM32L4_TIM2 -# undef CONFIG_STM32L4_TIM2_PWM +#ifndef CONFIG_STM32_TIM2 +# undef CONFIG_STM32_TIM2_PWM #endif -#ifndef CONFIG_STM32L4_TIM3 -# undef CONFIG_STM32L4_TIM3_PWM +#ifndef CONFIG_STM32_TIM3 +# undef CONFIG_STM32_TIM3_PWM #endif -#ifndef CONFIG_STM32L4_TIM4 -# undef CONFIG_STM32L4_TIM4_PWM +#ifndef CONFIG_STM32_TIM4 +# undef CONFIG_STM32_TIM4_PWM #endif -#ifndef CONFIG_STM32L4_TIM5 -# undef CONFIG_STM32L4_TIM5_PWM +#ifndef CONFIG_STM32_TIM5 +# undef CONFIG_STM32_TIM5_PWM #endif -#ifndef CONFIG_STM32L4_TIM8 -# undef CONFIG_STM32L4_TIM8_PWM +#ifndef CONFIG_STM32_TIM8 +# undef CONFIG_STM32_TIM8_PWM #endif -#ifndef CONFIG_STM32L4_TIM15 -# undef CONFIG_STM32L4_TIM15_PWM +#ifndef CONFIG_STM32_TIM15 +# undef CONFIG_STM32_TIM15_PWM #endif -#ifndef CONFIG_STM32L4_TIM16 -# undef CONFIG_STM32L4_TIM16_PWM +#ifndef CONFIG_STM32_TIM16 +# undef CONFIG_STM32_TIM16_PWM #endif -#ifndef CONFIG_STM32L4_TIM17 -# undef CONFIG_STM32L4_TIM17_PWM +#ifndef CONFIG_STM32_TIM17 +# undef CONFIG_STM32_TIM17_PWM #endif -#ifndef CONFIG_STM32L4_LPTIM1 -# undef CONFIG_STM32L4_LPTIM1_PWM +#ifndef CONFIG_STM32_LPTIM1 +# undef CONFIG_STM32_LPTIM1_PWM #endif -#ifndef CONFIG_STM32L4_LPTIM2 -# undef CONFIG_STM32L4_LPTIM2_PWM +#ifndef CONFIG_STM32_LPTIM2 +# undef CONFIG_STM32_LPTIM2_PWM #endif /* The basic timers (timer 6 and 7) are not capable of generating output * pulses. */ -#undef CONFIG_STM32L4_TIM6_PWM -#undef CONFIG_STM32L4_TIM7_PWM +#undef CONFIG_STM32_TIM6_PWM +#undef CONFIG_STM32_TIM7_PWM /* Check if PWM support for any channel is enabled. */ -#if defined(CONFIG_STM32L4_TIM1_PWM) || defined(CONFIG_STM32L4_TIM2_PWM) || \ - defined(CONFIG_STM32L4_TIM3_PWM) || defined(CONFIG_STM32L4_TIM4_PWM) || \ - defined(CONFIG_STM32L4_TIM5_PWM) || defined(CONFIG_STM32L4_TIM8_PWM) || \ - defined(CONFIG_STM32L4_TIM15_PWM) || defined(CONFIG_STM32L4_TIM16_PWM) || \ - defined(CONFIG_STM32L4_TIM17_PWM) || defined(CONFIG_STM32L4_LPTIM1_PWM) || \ - defined(CONFIG_STM32L4_LPTIM2_PWM) +#if defined(CONFIG_STM32_TIM1_PWM) || defined(CONFIG_STM32_TIM2_PWM) || \ + defined(CONFIG_STM32_TIM3_PWM) || defined(CONFIG_STM32_TIM4_PWM) || \ + defined(CONFIG_STM32_TIM5_PWM) || defined(CONFIG_STM32_TIM8_PWM) || \ + defined(CONFIG_STM32_TIM15_PWM) || defined(CONFIG_STM32_TIM16_PWM) || \ + defined(CONFIG_STM32_TIM17_PWM) || defined(CONFIG_STM32_LPTIM1_PWM) || \ + defined(CONFIG_STM32_LPTIM2_PWM) /* PWM driver channels configuration */ -#ifdef CONFIG_STM32L4_PWM_MULTICHAN +#ifdef CONFIG_STM32_PWM_MULTICHAN -#ifdef CONFIG_STM32L4_TIM1_CHANNEL1 -# ifdef CONFIG_STM32L4_TIM1_CH1OUT +#ifdef CONFIG_STM32_TIM1_CHANNEL1 +# ifdef CONFIG_STM32_TIM1_CH1OUT # define PWM_TIM1_CH1CFG GPIO_TIM1_CH1OUT # else # define PWM_TIM1_CH1CFG 0 # endif -# ifdef CONFIG_STM32L4_TIM1_CH1NOUT +# ifdef CONFIG_STM32_TIM1_CH1NOUT # define PWM_TIM1_CH1NCFG GPIO_TIM1_CH1NOUT # else # define PWM_TIM1_CH1NCFG 0 @@ -124,13 +124,13 @@ #else # define PWM_TIM1_CHANNEL1 0 #endif -#ifdef CONFIG_STM32L4_TIM1_CHANNEL2 -# ifdef CONFIG_STM32L4_TIM1_CH2OUT +#ifdef CONFIG_STM32_TIM1_CHANNEL2 +# ifdef CONFIG_STM32_TIM1_CH2OUT # define PWM_TIM1_CH2CFG GPIO_TIM1_CH2OUT # else # define PWM_TIM1_CH2CFG 0 # endif -# ifdef CONFIG_STM32L4_TIM1_CH2NOUT +# ifdef CONFIG_STM32_TIM1_CH2NOUT # define PWM_TIM1_CH2NCFG GPIO_TIM1_CH2NOUT # else # define PWM_TIM1_CH2NCFG 0 @@ -139,13 +139,13 @@ #else # define PWM_TIM1_CHANNEL2 0 #endif -#ifdef CONFIG_STM32L4_TIM1_CHANNEL3 -# ifdef CONFIG_STM32L4_TIM1_CH3OUT +#ifdef CONFIG_STM32_TIM1_CHANNEL3 +# ifdef CONFIG_STM32_TIM1_CH3OUT # define PWM_TIM1_CH3CFG GPIO_TIM1_CH3OUT # else # define PWM_TIM1_CH3CFG 0 # endif -# ifdef CONFIG_STM32L4_TIM1_CH3NOUT +# ifdef CONFIG_STM32_TIM1_CH3NOUT # define PWM_TIM1_CH3NCFG GPIO_TIM1_CH3NOUT # else # define PWM_TIM1_CH3NCFG 0 @@ -154,8 +154,8 @@ #else # define PWM_TIM1_CHANNEL3 0 #endif -#ifdef CONFIG_STM32L4_TIM1_CHANNEL4 -# ifdef CONFIG_STM32L4_TIM1_CH4OUT +#ifdef CONFIG_STM32_TIM1_CHANNEL4 +# ifdef CONFIG_STM32_TIM1_CH4OUT # define PWM_TIM1_CH4CFG GPIO_TIM1_CH4OUT # else # define PWM_TIM1_CH4CFG 0 @@ -167,8 +167,8 @@ #define PWM_TIM1_NCHANNELS (PWM_TIM1_CHANNEL1 + PWM_TIM1_CHANNEL2 + \ PWM_TIM1_CHANNEL3 + PWM_TIM1_CHANNEL4) -#ifdef CONFIG_STM32L4_TIM2_CHANNEL1 -# ifdef CONFIG_STM32L4_TIM2_CH1OUT +#ifdef CONFIG_STM32_TIM2_CHANNEL1 +# ifdef CONFIG_STM32_TIM2_CH1OUT # define PWM_TIM2_CH1CFG GPIO_TIM2_CH1OUT # else # define PWM_TIM2_CH1CFG 0 @@ -177,8 +177,8 @@ #else # define PWM_TIM2_CHANNEL1 0 #endif -#ifdef CONFIG_STM32L4_TIM2_CHANNEL2 -# ifdef CONFIG_STM32L4_TIM2_CH2OUT +#ifdef CONFIG_STM32_TIM2_CHANNEL2 +# ifdef CONFIG_STM32_TIM2_CH2OUT # define PWM_TIM2_CH2CFG GPIO_TIM2_CH2OUT # else # define PWM_TIM2_CH2CFG 0 @@ -187,8 +187,8 @@ #else # define PWM_TIM2_CHANNEL2 0 #endif -#ifdef CONFIG_STM32L4_TIM2_CHANNEL3 -# ifdef CONFIG_STM32L4_TIM2_CH3OUT +#ifdef CONFIG_STM32_TIM2_CHANNEL3 +# ifdef CONFIG_STM32_TIM2_CH3OUT # define PWM_TIM2_CH3CFG GPIO_TIM2_CH3OUT # else # define PWM_TIM2_CH3CFG 0 @@ -197,8 +197,8 @@ #else # define PWM_TIM2_CHANNEL3 0 #endif -#ifdef CONFIG_STM32L4_TIM2_CHANNEL4 -# ifdef CONFIG_STM32L4_TIM2_CH4OUT +#ifdef CONFIG_STM32_TIM2_CHANNEL4 +# ifdef CONFIG_STM32_TIM2_CH4OUT # define PWM_TIM2_CH4CFG GPIO_TIM2_CH4OUT # else # define PWM_TIM2_CH4CFG 0 @@ -210,8 +210,8 @@ #define PWM_TIM2_NCHANNELS (PWM_TIM2_CHANNEL1 + PWM_TIM2_CHANNEL2 + \ PWM_TIM2_CHANNEL3 + PWM_TIM2_CHANNEL4) -#ifdef CONFIG_STM32L4_TIM3_CHANNEL1 -# ifdef CONFIG_STM32L4_TIM3_CH1OUT +#ifdef CONFIG_STM32_TIM3_CHANNEL1 +# ifdef CONFIG_STM32_TIM3_CH1OUT # define PWM_TIM3_CH1CFG GPIO_TIM3_CH1OUT # else # define PWM_TIM3_CH1CFG 0 @@ -220,8 +220,8 @@ #else # define PWM_TIM3_CHANNEL1 0 #endif -#ifdef CONFIG_STM32L4_TIM3_CHANNEL2 -# ifdef CONFIG_STM32L4_TIM3_CH2OUT +#ifdef CONFIG_STM32_TIM3_CHANNEL2 +# ifdef CONFIG_STM32_TIM3_CH2OUT # define PWM_TIM3_CH2CFG GPIO_TIM3_CH2OUT # else # define PWM_TIM3_CH2CFG 0 @@ -230,8 +230,8 @@ #else # define PWM_TIM3_CHANNEL2 0 #endif -#ifdef CONFIG_STM32L4_TIM3_CHANNEL3 -# ifdef CONFIG_STM32L4_TIM3_CH3OUT +#ifdef CONFIG_STM32_TIM3_CHANNEL3 +# ifdef CONFIG_STM32_TIM3_CH3OUT # define PWM_TIM3_CH3CFG GPIO_TIM3_CH3OUT # else # define PWM_TIM3_CH3CFG 0 @@ -240,8 +240,8 @@ #else # define PWM_TIM3_CHANNEL3 0 #endif -#ifdef CONFIG_STM32L4_TIM3_CHANNEL4 -# ifdef CONFIG_STM32L4_TIM3_CH4OUT +#ifdef CONFIG_STM32_TIM3_CHANNEL4 +# ifdef CONFIG_STM32_TIM3_CH4OUT # define PWM_TIM3_CH4CFG GPIO_TIM3_CH4OUT # else # define PWM_TIM3_CH4CFG 0 @@ -253,8 +253,8 @@ #define PWM_TIM3_NCHANNELS (PWM_TIM3_CHANNEL1 + PWM_TIM3_CHANNEL2 + \ PWM_TIM3_CHANNEL3 + PWM_TIM3_CHANNEL4) -#ifdef CONFIG_STM32L4_TIM4_CHANNEL1 -# ifdef CONFIG_STM32L4_TIM4_CH1OUT +#ifdef CONFIG_STM32_TIM4_CHANNEL1 +# ifdef CONFIG_STM32_TIM4_CH1OUT # define PWM_TIM4_CH1CFG GPIO_TIM4_CH1OUT # else # define PWM_TIM4_CH1CFG 0 @@ -263,8 +263,8 @@ #else # define PWM_TIM4_CHANNEL1 0 #endif -#ifdef CONFIG_STM32L4_TIM4_CHANNEL2 -# ifdef CONFIG_STM32L4_TIM4_CH2OUT +#ifdef CONFIG_STM32_TIM4_CHANNEL2 +# ifdef CONFIG_STM32_TIM4_CH2OUT # define PWM_TIM4_CH2CFG GPIO_TIM4_CH2OUT # else # define PWM_TIM4_CH2CFG 0 @@ -273,8 +273,8 @@ #else # define PWM_TIM4_CHANNEL2 0 #endif -#ifdef CONFIG_STM32L4_TIM4_CHANNEL3 -# ifdef CONFIG_STM32L4_TIM4_CH3OUT +#ifdef CONFIG_STM32_TIM4_CHANNEL3 +# ifdef CONFIG_STM32_TIM4_CH3OUT # define PWM_TIM4_CH3CFG GPIO_TIM4_CH3OUT # else # define PWM_TIM4_CH3CFG 0 @@ -283,8 +283,8 @@ #else # define PWM_TIM4_CHANNEL3 0 #endif -#ifdef CONFIG_STM32L4_TIM4_CHANNEL4 -# ifdef CONFIG_STM32L4_TIM4_CH4OUT +#ifdef CONFIG_STM32_TIM4_CHANNEL4 +# ifdef CONFIG_STM32_TIM4_CH4OUT # define PWM_TIM4_CH4CFG GPIO_TIM4_CH4OUT # else # define PWM_TIM4_CH4CFG 0 @@ -296,8 +296,8 @@ #define PWM_TIM4_NCHANNELS (PWM_TIM4_CHANNEL1 + PWM_TIM4_CHANNEL2 + \ PWM_TIM4_CHANNEL3 + PWM_TIM4_CHANNEL4) -#ifdef CONFIG_STM32L4_TIM5_CHANNEL1 -# ifdef CONFIG_STM32L4_TIM5_CH1OUT +#ifdef CONFIG_STM32_TIM5_CHANNEL1 +# ifdef CONFIG_STM32_TIM5_CH1OUT # define PWM_TIM5_CH1CFG GPIO_TIM5_CH1OUT # else # define PWM_TIM5_CH1CFG 0 @@ -306,8 +306,8 @@ #else # define PWM_TIM5_CHANNEL1 0 #endif -#ifdef CONFIG_STM32L4_TIM5_CHANNEL2 -# ifdef CONFIG_STM32L4_TIM5_CH2OUT +#ifdef CONFIG_STM32_TIM5_CHANNEL2 +# ifdef CONFIG_STM32_TIM5_CH2OUT # define PWM_TIM5_CH2CFG GPIO_TIM5_CH2OUT # else # define PWM_TIM5_CH2CFG 0 @@ -316,8 +316,8 @@ #else # define PWM_TIM5_CHANNEL2 0 #endif -#ifdef CONFIG_STM32L4_TIM5_CHANNEL3 -# ifdef CONFIG_STM32L4_TIM5_CH3OUT +#ifdef CONFIG_STM32_TIM5_CHANNEL3 +# ifdef CONFIG_STM32_TIM5_CH3OUT # define PWM_TIM5_CH3CFG GPIO_TIM5_CH3OUT # else # define PWM_TIM5_CH3CFG 0 @@ -326,8 +326,8 @@ #else # define PWM_TIM5_CHANNEL3 0 #endif -#ifdef CONFIG_STM32L4_TIM5_CHANNEL4 -# ifdef CONFIG_STM32L4_TIM5_CH4OUT +#ifdef CONFIG_STM32_TIM5_CHANNEL4 +# ifdef CONFIG_STM32_TIM5_CH4OUT # define PWM_TIM5_CH4CFG GPIO_TIM5_CH4OUT # else # define PWM_TIM5_CH4CFG 0 @@ -339,13 +339,13 @@ #define PWM_TIM5_NCHANNELS (PWM_TIM5_CHANNEL1 + PWM_TIM5_CHANNEL2 + \ PWM_TIM5_CHANNEL3 + PWM_TIM5_CHANNEL4) -#ifdef CONFIG_STM32L4_TIM8_CHANNEL1 -# ifdef CONFIG_STM32L4_TIM8_CH1OUT +#ifdef CONFIG_STM32_TIM8_CHANNEL1 +# ifdef CONFIG_STM32_TIM8_CH1OUT # define PWM_TIM8_CH1CFG GPIO_TIM8_CH1OUT # else # define PWM_TIM8_CH1CFG 0 # endif -# ifdef CONFIG_STM32L4_TIM8_CH1OUT +# ifdef CONFIG_STM32_TIM8_CH1OUT # define PWM_TIM8_CH1NCFG GPIO_TIM8_CH1NOUT # else # define PWM_TIM8_CH1NCFG 0 @@ -354,13 +354,13 @@ #else # define PWM_TIM8_CHANNEL1 0 #endif -#ifdef CONFIG_STM32L4_TIM8_CHANNEL2 -# ifdef CONFIG_STM32L4_TIM8_CH2OUT +#ifdef CONFIG_STM32_TIM8_CHANNEL2 +# ifdef CONFIG_STM32_TIM8_CH2OUT # define PWM_TIM8_CH2CFG GPIO_TIM8_CH2OUT # else # define PWM_TIM8_CH2CFG 0 # endif -# ifdef CONFIG_STM32L4_TIM8_CH2NOUT +# ifdef CONFIG_STM32_TIM8_CH2NOUT # define PWM_TIM8_CH2NCFG GPIO_TIM8_CH2NOUT # else # define PWM_TIM8_CH2NCFG 0 @@ -369,13 +369,13 @@ #else # define PWM_TIM8_CHANNEL2 0 #endif -#ifdef CONFIG_STM32L4_TIM8_CHANNEL3 -# ifdef CONFIG_STM32L4_TIM8_CH3OUT +#ifdef CONFIG_STM32_TIM8_CHANNEL3 +# ifdef CONFIG_STM32_TIM8_CH3OUT # define PWM_TIM8_CH3CFG GPIO_TIM8_CH3OUT # else # define PWM_TIM8_CH3CFG 0 # endif -# ifdef CONFIG_STM32L4_TIM8_CH3NOUT +# ifdef CONFIG_STM32_TIM8_CH3NOUT # define PWM_TIM8_CH3NCFG GPIO_TIM8_CH3NOUT # else # define PWM_TIM8_CH3NCFG 0 @@ -384,8 +384,8 @@ #else # define PWM_TIM8_CHANNEL3 0 #endif -#ifdef CONFIG_STM32L4_TIM8_CHANNEL4 -# ifdef CONFIG_STM32L4_TIM8_CH4OUT +#ifdef CONFIG_STM32_TIM8_CHANNEL4 +# ifdef CONFIG_STM32_TIM8_CH4OUT # define PWM_TIM8_CH4CFG GPIO_TIM8_CH4OUT # else # define PWM_TIM8_CH4CFG 0 @@ -397,13 +397,13 @@ #define PWM_TIM8_NCHANNELS (PWM_TIM8_CHANNEL1 + PWM_TIM8_CHANNEL2 + \ PWM_TIM8_CHANNEL3 + PWM_TIM8_CHANNEL4) -#ifdef CONFIG_STM32L4_TIM15_CHANNEL1 -# ifdef CONFIG_STM32L4_TIM15_CH1OUT +#ifdef CONFIG_STM32_TIM15_CHANNEL1 +# ifdef CONFIG_STM32_TIM15_CH1OUT # define PWM_TIM15_CH1CFG GPIO_TIM15_CH1OUT # else # define PWM_TIM15_CH1CFG 0 # endif -# ifdef CONFIG_STM32L4_TIM15_CH1NOUT +# ifdef CONFIG_STM32_TIM15_CH1NOUT # define PWM_TIM15_CH1NCFG GPIO_TIM15_CH1NOUT # else # define PWM_TIM15_CH1NCFG 0 @@ -412,8 +412,8 @@ #else # define PWM_TIM15_CHANNEL1 0 #endif -#ifdef CONFIG_STM32L4_TIM15_CHANNEL2 -# ifdef CONFIG_STM32L4_TIM15_CH2OUT +#ifdef CONFIG_STM32_TIM15_CHANNEL2 +# ifdef CONFIG_STM32_TIM15_CH2OUT # define PWM_TIM15_CH2CFG GPIO_TIM15_CH2OUT # else # define PWM_TIM15_CH2CFG 0 @@ -424,13 +424,13 @@ #endif #define PWM_TIM15_NCHANNELS (PWM_TIM15_CHANNEL1 + PWM_TIM15_CHANNEL2) -#ifdef CONFIG_STM32L4_TIM16_CHANNEL1 -# ifdef CONFIG_STM32L4_TIM16_CH1OUT +#ifdef CONFIG_STM32_TIM16_CHANNEL1 +# ifdef CONFIG_STM32_TIM16_CH1OUT # define PWM_TIM16_CH1CFG GPIO_TIM16_CH1OUT # else # define PWM_TIM16_CH1CFG 0 # endif -# ifdef CONFIG_STM32L4_TIM16_CH1NOUT +# ifdef CONFIG_STM32_TIM16_CH1NOUT # define PWM_TIM16_CH1NCFG GPIO_TIM16_CH1NOUT # else # define PWM_TIM16_CH1NCFG 0 @@ -441,13 +441,13 @@ #endif #define PWM_TIM16_NCHANNELS PWM_TIM16_CHANNEL1 -#ifdef CONFIG_STM32L4_TIM17_CHANNEL1 -# ifdef CONFIG_STM32L4_TIM17_CH1OUT +#ifdef CONFIG_STM32_TIM17_CHANNEL1 +# ifdef CONFIG_STM32_TIM17_CH1OUT # define PWM_TIM17_CH1CFG GPIO_TIM17_CH1OUT # else # define PWM_TIM17_CH1CFG 0 # endif -# ifdef CONFIG_STM32L4_TIM17_CH1NOUT +# ifdef CONFIG_STM32_TIM17_CH1NOUT # define PWM_TIM17_CH1NCFG GPIO_TIM17_CH1NOUT # else # define PWM_TIM17_CH1NCFG 0 @@ -458,13 +458,13 @@ #endif #define PWM_TIM17_NCHANNELS PWM_TIM17_CHANNEL1 -#ifdef CONFIG_STM32L4_LPTIM1_CHANNEL1 -# ifdef CONFIG_STM32L4_LPTIM1_CH1OUT +#ifdef CONFIG_STM32_LPTIM1_CHANNEL1 +# ifdef CONFIG_STM32_LPTIM1_CH1OUT # define PWM_LPTIM1_CH1CFG GPIO_LPTIM1_CH1OUT # else # define PWM_LPTIM1_CH1CFG 0 # endif -# ifdef CONFIG_STM32L4_LPTIM1_CH1NOUT +# ifdef CONFIG_STM32_LPTIM1_CH1NOUT # define PWM_LPTIM1_CH1NCFG GPIO_LPTIM1_CH1NOUT # else # define PWM_LPTIM1_CH1NCFG 0 @@ -475,13 +475,13 @@ #endif #define PWM_LPTIM1_NCHANNELS PWM_LPTIM1_CHANNEL1 -#ifdef CONFIG_STM32L4_LPTIM2_CHANNEL1 -# ifdef CONFIG_STM32L4_LPTIM2_CH1OUT +#ifdef CONFIG_STM32_LPTIM2_CHANNEL1 +# ifdef CONFIG_STM32_LPTIM2_CH1OUT # define PWM_LPTIM2_CH1CFG GPIO_LPTIM2_CH1OUT # else # define PWM_LPTIM2_CH1CFG 0 # endif -# ifdef CONFIG_STM32L4_LPTIM2_CH1NOUT +# ifdef CONFIG_STM32_LPTIM2_CH1NOUT # define PWM_LPTIM2_CH1NCFG GPIO_LPTIM2_CH1NOUT # else # define PWM_LPTIM2_CH1NCFG 0 @@ -492,12 +492,12 @@ #endif #define PWM_LPTIM2_NCHANNELS PWM_LPTIM2_CHANNEL1 -#else /* !CONFIG_STM32L4_PWM_MULTICHAN */ +#else /* !CONFIG_STM32_PWM_MULTICHAN */ /* For each timer that is enabled for PWM usage, we need the following * additional configuration settings: * - * CONFIG_STM32L4_TIMx_CHANNEL - Specifies the timer output channel + * CONFIG_STM32_TIMx_CHANNEL - Specifies the timer output channel * {1,..,4} * PWM_TIMx_CHn - One of the values defined in chip/stm32*_pinmap.h. * In the case where there are multiple pin selections, the correct @@ -510,250 +510,250 @@ * Only one output channel per timer. */ -#ifdef CONFIG_STM32L4_TIM1_PWM -# if !defined(CONFIG_STM32L4_TIM1_CHANNEL) -# error "CONFIG_STM32L4_TIM1_CHANNEL must be provided" -# elif CONFIG_STM32L4_TIM1_CHANNEL == 1 -# define CONFIG_STM32L4_TIM1_CHANNEL1 1 -# define CONFIG_STM32L4_TIM1_CH1MODE CONFIG_STM32L4_TIM1_CHMODE -# ifdef CONFIG_STM32L4_TIM1_CH1OUT +#ifdef CONFIG_STM32_TIM1_PWM +# if !defined(CONFIG_STM32_TIM1_CHANNEL) +# error "CONFIG_STM32_TIM1_CHANNEL must be provided" +# elif CONFIG_STM32_TIM1_CHANNEL == 1 +# define CONFIG_STM32_TIM1_CHANNEL1 1 +# define CONFIG_STM32_TIM1_CH1MODE CONFIG_STM32_TIM1_CHMODE +# ifdef CONFIG_STM32_TIM1_CH1OUT # define PWM_TIM1_CH1CFG GPIO_TIM1_CH1OUT # endif -# ifdef CONFIG_STM32L4_TIM1_CH1NOUT +# ifdef CONFIG_STM32_TIM1_CH1NOUT # define PWM_TIM1_CH1NCFG GPIO_TIM1_CH1NOUT # else # define PWM_TIM1_CH1NCFG 0 # endif -# elif CONFIG_STM32L4_TIM1_CHANNEL == 2 -# define CONFIG_STM32L4_TIM1_CHANNEL2 1 -# define CONFIG_STM32L4_TIM1_CH2MODE CONFIG_STM32L4_TIM1_CHMODE -# ifdef CONFIG_STM32L4_TIM1_CH2OUT +# elif CONFIG_STM32_TIM1_CHANNEL == 2 +# define CONFIG_STM32_TIM1_CHANNEL2 1 +# define CONFIG_STM32_TIM1_CH2MODE CONFIG_STM32_TIM1_CHMODE +# ifdef CONFIG_STM32_TIM1_CH2OUT # define PWM_TIM1_CH2CFG GPIO_TIM1_CH2OUT # endif -# ifdef CONFIG_STM32L4_TIM1_CH2NOUT +# ifdef CONFIG_STM32_TIM1_CH2NOUT # define PWM_TIM1_CH2NCFG GPIO_TIM1_CH2NOUT # else # define PWM_TIM1_CH2NCFG 0 # endif -# elif CONFIG_STM32L4_TIM1_CHANNEL == 3 -# define CONFIG_STM32L4_TIM1_CHANNEL3 1 -# define CONFIG_STM32L4_TIM1_CH3MODE CONFIG_STM32L4_TIM1_CHMODE -# ifdef CONFIG_STM32L4_TIM1_CH3OUT +# elif CONFIG_STM32_TIM1_CHANNEL == 3 +# define CONFIG_STM32_TIM1_CHANNEL3 1 +# define CONFIG_STM32_TIM1_CH3MODE CONFIG_STM32_TIM1_CHMODE +# ifdef CONFIG_STM32_TIM1_CH3OUT # define PWM_TIM1_CH3CFG GPIO_TIM1_CH3OUT # endif -# ifdef CONFIG_STM32L4_TIM1_CH3NOUT +# ifdef CONFIG_STM32_TIM1_CH3NOUT # define PWM_TIM1_CH3NCFG GPIO_TIM1_CH3NOUT # else # define PWM_TIM1_CH3NCFG 0 # endif -# elif CONFIG_STM32L4_TIM1_CHANNEL == 4 -# define CONFIG_STM32L4_TIM1_CHANNEL4 1 -# define CONFIG_STM32L4_TIM1_CH4MODE CONFIG_STM32L4_TIM1_CHMODE -# ifdef CONFIG_STM32L4_TIM1_CH4OUT +# elif CONFIG_STM32_TIM1_CHANNEL == 4 +# define CONFIG_STM32_TIM1_CHANNEL4 1 +# define CONFIG_STM32_TIM1_CH4MODE CONFIG_STM32_TIM1_CHMODE +# ifdef CONFIG_STM32_TIM1_CH4OUT # define PWM_TIM1_CH4CFG GPIO_TIM1_CH4OUT # endif # else -# error "Unsupported value of CONFIG_STM32L4_TIM1_CHANNEL" +# error "Unsupported value of CONFIG_STM32_TIM1_CHANNEL" # endif # define PWM_TIM1_NCHANNELS 1 #endif -#ifdef CONFIG_STM32L4_TIM2_PWM -# if !defined(CONFIG_STM32L4_TIM2_CHANNEL) -# error "CONFIG_STM32L4_TIM2_CHANNEL must be provided" -# elif CONFIG_STM32L4_TIM2_CHANNEL == 1 -# define CONFIG_STM32L4_TIM2_CHANNEL1 1 -# define CONFIG_STM32L4_TIM2_CH1MODE CONFIG_STM32L4_TIM2_CHMODE +#ifdef CONFIG_STM32_TIM2_PWM +# if !defined(CONFIG_STM32_TIM2_CHANNEL) +# error "CONFIG_STM32_TIM2_CHANNEL must be provided" +# elif CONFIG_STM32_TIM2_CHANNEL == 1 +# define CONFIG_STM32_TIM2_CHANNEL1 1 +# define CONFIG_STM32_TIM2_CH1MODE CONFIG_STM32_TIM2_CHMODE # define PWM_TIM2_CH1CFG GPIO_TIM2_CH1OUT -# elif CONFIG_STM32L4_TIM2_CHANNEL == 2 -# define CONFIG_STM32L4_TIM2_CHANNEL2 1 -# define CONFIG_STM32L4_TIM2_CH2MODE CONFIG_STM32L4_TIM2_CHMODE +# elif CONFIG_STM32_TIM2_CHANNEL == 2 +# define CONFIG_STM32_TIM2_CHANNEL2 1 +# define CONFIG_STM32_TIM2_CH2MODE CONFIG_STM32_TIM2_CHMODE # define PWM_TIM2_CH2CFG GPIO_TIM2_CH2OUT -# elif CONFIG_STM32L4_TIM2_CHANNEL == 3 -# define CONFIG_STM32L4_TIM2_CHANNEL3 1 -# define CONFIG_STM32L4_TIM2_CH3MODE CONFIG_STM32L4_TIM2_CHMODE +# elif CONFIG_STM32_TIM2_CHANNEL == 3 +# define CONFIG_STM32_TIM2_CHANNEL3 1 +# define CONFIG_STM32_TIM2_CH3MODE CONFIG_STM32_TIM2_CHMODE # define PWM_TIM2_CH3CFG GPIO_TIM2_CH3OUT -# elif CONFIG_STM32L4_TIM2_CHANNEL == 4 -# define CONFIG_STM32L4_TIM2_CHANNEL4 1 -# define CONFIG_STM32L4_TIM2_CH4MODE CONFIG_STM32L4_TIM2_CHMODE +# elif CONFIG_STM32_TIM2_CHANNEL == 4 +# define CONFIG_STM32_TIM2_CHANNEL4 1 +# define CONFIG_STM32_TIM2_CH4MODE CONFIG_STM32_TIM2_CHMODE # define PWM_TIM2_CH4CFG GPIO_TIM2_CH4OUT # else -# error "Unsupported value of CONFIG_STM32L4_TIM2_CHANNEL" +# error "Unsupported value of CONFIG_STM32_TIM2_CHANNEL" # endif # define PWM_TIM2_NCHANNELS 1 #endif -#ifdef CONFIG_STM32L4_TIM3_PWM -# if !defined(CONFIG_STM32L4_TIM3_CHANNEL) -# error "CONFIG_STM32L4_TIM3_CHANNEL must be provided" -# elif CONFIG_STM32L4_TIM3_CHANNEL == 1 -# define CONFIG_STM32L4_TIM3_CHANNEL1 1 -# define CONFIG_STM32L4_TIM3_CH1MODE CONFIG_STM32L4_TIM3_CHMODE +#ifdef CONFIG_STM32_TIM3_PWM +# if !defined(CONFIG_STM32_TIM3_CHANNEL) +# error "CONFIG_STM32_TIM3_CHANNEL must be provided" +# elif CONFIG_STM32_TIM3_CHANNEL == 1 +# define CONFIG_STM32_TIM3_CHANNEL1 1 +# define CONFIG_STM32_TIM3_CH1MODE CONFIG_STM32_TIM3_CHMODE # define PWM_TIM3_CH1CFG GPIO_TIM3_CH1OUT -# elif CONFIG_STM32L4_TIM3_CHANNEL == 2 -# define CONFIG_STM32L4_TIM3_CHANNEL2 1 -# define CONFIG_STM32L4_TIM3_CH2MODE CONFIG_STM32L4_TIM3_CHMODE +# elif CONFIG_STM32_TIM3_CHANNEL == 2 +# define CONFIG_STM32_TIM3_CHANNEL2 1 +# define CONFIG_STM32_TIM3_CH2MODE CONFIG_STM32_TIM3_CHMODE # define PWM_TIM3_CH2CFG GPIO_TIM3_CH2OUT -# elif CONFIG_STM32L4_TIM3_CHANNEL == 3 -# define CONFIG_STM32L4_TIM3_CHANNEL3 1 -# define CONFIG_STM32L4_TIM3_CH3MODE CONFIG_STM32L4_TIM3_CHMODE +# elif CONFIG_STM32_TIM3_CHANNEL == 3 +# define CONFIG_STM32_TIM3_CHANNEL3 1 +# define CONFIG_STM32_TIM3_CH3MODE CONFIG_STM32_TIM3_CHMODE # define PWM_TIM3_CH3CFG GPIO_TIM3_CH3OUT -# elif CONFIG_STM32L4_TIM3_CHANNEL == 4 -# define CONFIG_STM32L4_TIM3_CHANNEL4 1 -# define CONFIG_STM32L4_TIM3_CH4MODE CONFIG_STM32L4_TIM3_CHMODE +# elif CONFIG_STM32_TIM3_CHANNEL == 4 +# define CONFIG_STM32_TIM3_CHANNEL4 1 +# define CONFIG_STM32_TIM3_CH4MODE CONFIG_STM32_TIM3_CHMODE # define PWM_TIM3_CH4CFG GPIO_TIM3_CH4OUT # else -# error "Unsupported value of CONFIG_STM32L4_TIM3_CHANNEL" +# error "Unsupported value of CONFIG_STM32_TIM3_CHANNEL" # endif # define PWM_TIM3_NCHANNELS 1 #endif -#ifdef CONFIG_STM32L4_TIM4_PWM -# if !defined(CONFIG_STM32L4_TIM4_CHANNEL) -# error "CONFIG_STM32L4_TIM4_CHANNEL must be provided" -# elif CONFIG_STM32L4_TIM4_CHANNEL == 1 -# define CONFIG_STM32L4_TIM4_CHANNEL1 1 -# define CONFIG_STM32L4_TIM4_CH1MODE CONFIG_STM32L4_TIM4_CHMODE +#ifdef CONFIG_STM32_TIM4_PWM +# if !defined(CONFIG_STM32_TIM4_CHANNEL) +# error "CONFIG_STM32_TIM4_CHANNEL must be provided" +# elif CONFIG_STM32_TIM4_CHANNEL == 1 +# define CONFIG_STM32_TIM4_CHANNEL1 1 +# define CONFIG_STM32_TIM4_CH1MODE CONFIG_STM32_TIM4_CHMODE # define PWM_TIM4_CH1CFG GPIO_TIM4_CH1OUT -# elif CONFIG_STM32L4_TIM4_CHANNEL == 2 -# define CONFIG_STM32L4_TIM4_CHANNEL2 1 -# define CONFIG_STM32L4_TIM4_CH2MODE CONFIG_STM32L4_TIM4_CHMODE +# elif CONFIG_STM32_TIM4_CHANNEL == 2 +# define CONFIG_STM32_TIM4_CHANNEL2 1 +# define CONFIG_STM32_TIM4_CH2MODE CONFIG_STM32_TIM4_CHMODE # define PWM_TIM4_CH2CFG GPIO_TIM4_CH2OUT -# elif CONFIG_STM32L4_TIM4_CHANNEL == 3 -# define CONFIG_STM32L4_TIM4_CHANNEL3 1 -# define CONFIG_STM32L4_TIM4_CH3MODE CONFIG_STM32L4_TIM4_CHMODE +# elif CONFIG_STM32_TIM4_CHANNEL == 3 +# define CONFIG_STM32_TIM4_CHANNEL3 1 +# define CONFIG_STM32_TIM4_CH3MODE CONFIG_STM32_TIM4_CHMODE # define PWM_TIM4_CH3CFG GPIO_TIM4_CH3OUT -# elif CONFIG_STM32L4_TIM4_CHANNEL == 4 -# define CONFIG_STM32L4_TIM4_CHANNEL4 1 -# define CONFIG_STM32L4_TIM4_CH4MODE CONFIG_STM32L4_TIM4_CHMODE +# elif CONFIG_STM32_TIM4_CHANNEL == 4 +# define CONFIG_STM32_TIM4_CHANNEL4 1 +# define CONFIG_STM32_TIM4_CH4MODE CONFIG_STM32_TIM4_CHMODE # define PWM_TIM4_CH4CFG GPIO_TIM4_CH4OUT # else -# error "Unsupported value of CONFIG_STM32L4_TIM4_CHANNEL" +# error "Unsupported value of CONFIG_STM32_TIM4_CHANNEL" # endif # define PWM_TIM4_NCHANNELS 1 #endif -#ifdef CONFIG_STM32L4_TIM5_PWM -# if !defined(CONFIG_STM32L4_TIM5_CHANNEL) -# error "CONFIG_STM32L4_TIM5_CHANNEL must be provided" -# elif CONFIG_STM32L4_TIM5_CHANNEL == 1 -# define CONFIG_STM32L4_TIM5_CHANNEL1 1 -# define CONFIG_STM32L4_TIM5_CH1MODE CONFIG_STM32L4_TIM5_CHMODE +#ifdef CONFIG_STM32_TIM5_PWM +# if !defined(CONFIG_STM32_TIM5_CHANNEL) +# error "CONFIG_STM32_TIM5_CHANNEL must be provided" +# elif CONFIG_STM32_TIM5_CHANNEL == 1 +# define CONFIG_STM32_TIM5_CHANNEL1 1 +# define CONFIG_STM32_TIM5_CH1MODE CONFIG_STM32_TIM5_CHMODE # define PWM_TIM5_CH1CFG GPIO_TIM5_CH1OUT -# elif CONFIG_STM32L4_TIM5_CHANNEL == 2 -# define CONFIG_STM32L4_TIM5_CHANNEL2 1 -# define CONFIG_STM32L4_TIM5_CH2MODE CONFIG_STM32L4_TIM5_CHMODE +# elif CONFIG_STM32_TIM5_CHANNEL == 2 +# define CONFIG_STM32_TIM5_CHANNEL2 1 +# define CONFIG_STM32_TIM5_CH2MODE CONFIG_STM32_TIM5_CHMODE # define PWM_TIM5_CH2CFG GPIO_TIM5_CH2OUT -# elif CONFIG_STM32L4_TIM5_CHANNEL == 3 -# define CONFIG_STM32L4_TIM5_CHANNEL3 1 -# define CONFIG_STM32L4_TIM5_CH3MODE CONFIG_STM32L4_TIM5_CHMODE +# elif CONFIG_STM32_TIM5_CHANNEL == 3 +# define CONFIG_STM32_TIM5_CHANNEL3 1 +# define CONFIG_STM32_TIM5_CH3MODE CONFIG_STM32_TIM5_CHMODE # define PWM_TIM5_CH3CFG GPIO_TIM5_CH3OUT -# elif CONFIG_STM32L4_TIM5_CHANNEL == 4 -# define CONFIG_STM32L4_TIM5_CHANNEL4 1 -# define CONFIG_STM32L4_TIM5_CH4MODE CONFIG_STM32L4_TIM5_CHMODE +# elif CONFIG_STM32_TIM5_CHANNEL == 4 +# define CONFIG_STM32_TIM5_CHANNEL4 1 +# define CONFIG_STM32_TIM5_CH4MODE CONFIG_STM32_TIM5_CHMODE # define PWM_TIM5_CH4CFG GPIO_TIM5_CH4OUT # else -# error "Unsupported value of CONFIG_STM32L4_TIM5_CHANNEL" +# error "Unsupported value of CONFIG_STM32_TIM5_CHANNEL" # endif # define PWM_TIM5_NCHANNELS 1 #endif -#ifdef CONFIG_STM32L4_TIM8_PWM -# if !defined(CONFIG_STM32L4_TIM8_CHANNEL) -# error "CONFIG_STM32L4_TIM8_CHANNEL must be provided" -# elif CONFIG_STM32L4_TIM8_CHANNEL == 1 -# define CONFIG_STM32L4_TIM8_CHANNEL1 1 -# define CONFIG_STM32L4_TIM8_CH1MODE CONFIG_STM32L4_TIM8_CHMODE +#ifdef CONFIG_STM32_TIM8_PWM +# if !defined(CONFIG_STM32_TIM8_CHANNEL) +# error "CONFIG_STM32_TIM8_CHANNEL must be provided" +# elif CONFIG_STM32_TIM8_CHANNEL == 1 +# define CONFIG_STM32_TIM8_CHANNEL1 1 +# define CONFIG_STM32_TIM8_CH1MODE CONFIG_STM32_TIM8_CHMODE # define PWM_TIM8_CH1CFG GPIO_TIM8_CH1OUT # define PWM_TIM8_CH1NCFG 0 -# elif CONFIG_STM32L4_TIM8_CHANNEL == 2 -# define CONFIG_STM32L4_TIM8_CHANNEL2 1 -# define CONFIG_STM32L4_TIM8_CH2MODE CONFIG_STM32L4_TIM8_CHMODE +# elif CONFIG_STM32_TIM8_CHANNEL == 2 +# define CONFIG_STM32_TIM8_CHANNEL2 1 +# define CONFIG_STM32_TIM8_CH2MODE CONFIG_STM32_TIM8_CHMODE # define PWM_TIM8_CH2CFG GPIO_TIM8_CH2OUT # define PWM_TIM8_CH2NCFG 0 -# elif CONFIG_STM32L4_TIM8_CHANNEL == 3 -# define CONFIG_STM32L4_TIM8_CHANNEL3 1 -# define CONFIG_STM32L4_TIM8_CH3MODE CONFIG_STM32L4_TIM8_CHMODE +# elif CONFIG_STM32_TIM8_CHANNEL == 3 +# define CONFIG_STM32_TIM8_CHANNEL3 1 +# define CONFIG_STM32_TIM8_CH3MODE CONFIG_STM32_TIM8_CHMODE # define PWM_TIM8_CH3CFG GPIO_TIM8_CH3OUT # define PWM_TIM8_CH3NCFG 0 -# elif CONFIG_STM32L4_TIM8_CHANNEL == 4 -# define CONFIG_STM32L4_TIM8_CHANNEL4 1 -# define CONFIG_STM32L4_TIM8_CH4MODE CONFIG_STM32L4_TIM8_CHMODE +# elif CONFIG_STM32_TIM8_CHANNEL == 4 +# define CONFIG_STM32_TIM8_CHANNEL4 1 +# define CONFIG_STM32_TIM8_CH4MODE CONFIG_STM32_TIM8_CHMODE # define PWM_TIM8_CH4CFG GPIO_TIM8_CH4OUT # else -# error "Unsupported value of CONFIG_STM32L4_TIM8_CHANNEL" +# error "Unsupported value of CONFIG_STM32_TIM8_CHANNEL" # endif # define PWM_TIM8_NCHANNELS 1 #endif -#ifdef CONFIG_STM32L4_TIM15_PWM -# if !defined(CONFIG_STM32L4_TIM15_CHANNEL) -# error "CONFIG_STM32L4_TIM15_CHANNEL must be provided" -# elif CONFIG_STM32L4_TIM15_CHANNEL == 1 -# define CONFIG_STM32L4_TIM15_CHANNEL1 1 -# define CONFIG_STM32L4_TIM15_CH1MODE CONFIG_STM32L4_TIM15_CHMODE +#ifdef CONFIG_STM32_TIM15_PWM +# if !defined(CONFIG_STM32_TIM15_CHANNEL) +# error "CONFIG_STM32_TIM15_CHANNEL must be provided" +# elif CONFIG_STM32_TIM15_CHANNEL == 1 +# define CONFIG_STM32_TIM15_CHANNEL1 1 +# define CONFIG_STM32_TIM15_CH1MODE CONFIG_STM32_TIM15_CHMODE # define PWM_TIM15_CH1CFG GPIO_TIM15_CH1OUT # define PWM_TIM15_CH1NCFG 0 -# elif CONFIG_STM32L4_TIM15_CHANNEL == 2 -# define CONFIG_STM32L4_TIM15_CHANNEL2 1 -# define CONFIG_STM32L4_TIM15_CH2MODE CONFIG_STM32L4_TIM15_CHMODE +# elif CONFIG_STM32_TIM15_CHANNEL == 2 +# define CONFIG_STM32_TIM15_CHANNEL2 1 +# define CONFIG_STM32_TIM15_CH2MODE CONFIG_STM32_TIM15_CHMODE # define PWM_TIM15_CH2CFG GPIO_TIM15_CH2OUT # else -# error "Unsupported value of CONFIG_STM32L4_TIM15_CHANNEL" +# error "Unsupported value of CONFIG_STM32_TIM15_CHANNEL" # endif # define PWM_TIM15_NCHANNELS 1 #endif -#ifdef CONFIG_STM32L4_TIM16_PWM -# if !defined(CONFIG_STM32L4_TIM16_CHANNEL) -# error "CONFIG_STM32L4_TIM16_CHANNEL must be provided" -# elif CONFIG_STM32L4_TIM16_CHANNEL == 1 -# define CONFIG_STM32L4_TIM16_CHANNEL1 1 -# define CONFIG_STM32L4_TIM16_CH1MODE CONFIG_STM32L4_TIM16_CHMODE +#ifdef CONFIG_STM32_TIM16_PWM +# if !defined(CONFIG_STM32_TIM16_CHANNEL) +# error "CONFIG_STM32_TIM16_CHANNEL must be provided" +# elif CONFIG_STM32_TIM16_CHANNEL == 1 +# define CONFIG_STM32_TIM16_CHANNEL1 1 +# define CONFIG_STM32_TIM16_CH1MODE CONFIG_STM32_TIM16_CHMODE # define PWM_TIM16_CH1CFG GPIO_TIM16_CH1OUT # define PWM_TIM16_CH1NCFG 0 # else -# error "Unsupported value of CONFIG_STM32L4_TIM16_CHANNEL" +# error "Unsupported value of CONFIG_STM32_TIM16_CHANNEL" # endif # define PWM_TIM16_NCHANNELS 1 #endif -#ifdef CONFIG_STM32L4_TIM17_PWM -# if !defined(CONFIG_STM32L4_TIM17_CHANNEL) -# error "CONFIG_STM32L4_TIM17_CHANNEL must be provided" -# elif CONFIG_STM32L4_TIM17_CHANNEL == 1 -# define CONFIG_STM32L4_TIM17_CHANNEL1 1 -# define CONFIG_STM32L4_TIM17_CH1MODE CONFIG_STM32L4_TIM17_CHMODE +#ifdef CONFIG_STM32_TIM17_PWM +# if !defined(CONFIG_STM32_TIM17_CHANNEL) +# error "CONFIG_STM32_TIM17_CHANNEL must be provided" +# elif CONFIG_STM32_TIM17_CHANNEL == 1 +# define CONFIG_STM32_TIM17_CHANNEL1 1 +# define CONFIG_STM32_TIM17_CH1MODE CONFIG_STM32_TIM17_CHMODE # define PWM_TIM17_CH1CFG GPIO_TIM17_CH1OUT # define PWM_TIM17_CH1NCFG 0 # else -# error "Unsupported value of CONFIG_STM32L4_TIM17_CHANNEL" +# error "Unsupported value of CONFIG_STM32_TIM17_CHANNEL" # endif # define PWM_TIM17_NCHANNELS 1 #endif -#ifdef CONFIG_STM32L4_LPTIM1_PWM -# if !defined(CONFIG_STM32L4_LPTIM1_CHANNEL) -# error "CONFIG_STM32L4_LPTIM1_CHANNEL must be provided" -# elif CONFIG_STM32L4_LPTIM1_CHANNEL == 1 -# define CONFIG_STM32L4_LPTIM1_CHANNEL1 1 +#ifdef CONFIG_STM32_LPTIM1_PWM +# if !defined(CONFIG_STM32_LPTIM1_CHANNEL) +# error "CONFIG_STM32_LPTIM1_CHANNEL must be provided" +# elif CONFIG_STM32_LPTIM1_CHANNEL == 1 +# define CONFIG_STM32_LPTIM1_CHANNEL1 1 # define PWM_LPTIM1_CH1CFG GPIO_LPTIM1_CH1OUT # define PWM_LPTIM1_CH1NCFG 0 # else -# error "Unsupported value of CONFIG_STM32L4_LPTIM1_CHANNEL" +# error "Unsupported value of CONFIG_STM32_LPTIM1_CHANNEL" # endif # define PWM_LPTIM1_NCHANNELS 1 #endif -#ifdef CONFIG_STM32L4_LPTIM2_PWM -# if !defined(CONFIG_STM32L4_LPTIM2_CHANNEL) -# error "CONFIG_STM32L4_LPTIM2_CHANNEL must be provided" -# elif CONFIG_STM32L4_LPTIM2_CHANNEL == 1 -# define CONFIG_STM32L4_LPTIM2_CHANNEL1 1 +#ifdef CONFIG_STM32_LPTIM2_PWM +# if !defined(CONFIG_STM32_LPTIM2_CHANNEL) +# error "CONFIG_STM32_LPTIM2_CHANNEL must be provided" +# elif CONFIG_STM32_LPTIM2_CHANNEL == 1 +# define CONFIG_STM32_LPTIM2_CHANNEL1 1 # define PWM_LPTIM2_CH1CFG GPIO_LPTIM2_CH1OUT # define PWM_LPTIM2_CH1NCFG 0 # else -# error "Unsupported value of CONFIG_STM32L4_LPTIM2_CHANNEL" +# error "Unsupported value of CONFIG_STM32_LPTIM2_CHANNEL" # endif # define PWM_LPTIM2_NCHANNELS 1 #endif @@ -762,27 +762,27 @@ /* Complementary outputs support */ -#if defined(CONFIG_STM32L4_TIM1_CH1NOUT) || defined(CONFIG_STM32L4_TIM1_CH2NOUT) || \ - defined(CONFIG_STM32L4_TIM1_CH3NOUT) +#if defined(CONFIG_STM32_TIM1_CH1NOUT) || defined(CONFIG_STM32_TIM1_CH2NOUT) || \ + defined(CONFIG_STM32_TIM1_CH3NOUT) # define HAVE_TIM1_COMPLEMENTARY #endif -#if defined(CONFIG_STM32L4_TIM8_CH1NOUT) || defined(CONFIG_STM32L4_TIM8_CH2NOUT) || \ - defined(CONFIG_STM32L4_TIM8_CH3NOUT) +#if defined(CONFIG_STM32_TIM8_CH1NOUT) || defined(CONFIG_STM32_TIM8_CH2NOUT) || \ + defined(CONFIG_STM32_TIM8_CH3NOUT) # define HAVE_TIM8_COMPLEMENTARY #endif -#if defined(CONFIG_STM32L4_TIM15_CH1NOUT) +#if defined(CONFIG_STM32_TIM15_CH1NOUT) # define HAVE_TIM15_COMPLEMENTARY #endif -#if defined(CONFIG_STM32L4_TIM16_CH1NOUT) +#if defined(CONFIG_STM32_TIM16_CH1NOUT) # define HAVE_TIM16_COMPLEMENTARY #endif -#if defined(CONFIG_STM32L4_TIM17_CH1NOUT) +#if defined(CONFIG_STM32_TIM17_CH1NOUT) # define HAVE_TIM17_COMPLEMENTARY #endif -#if defined(CONFIG_STM32L4_LPTIM1_CH1NOUT) +#if defined(CONFIG_STM32_LPTIM1_CH1NOUT) # define HAVE_LPTIM1_COMPLEMENTARY #endif -#if defined(CONFIG_STM32L4_LPTIM2_CH1NOUT) +#if defined(CONFIG_STM32_LPTIM2_CH1NOUT) # define HAVE_LPTIM2_COMPLEMENTARY #endif #if defined(HAVE_TIM1_COMPLEMENTARY) || defined(HAVE_TIM8_COMPLEMENTARY) || \ @@ -794,10 +794,10 @@ /* Low-level ops helpers ****************************************************/ -#ifdef CONFIG_STM32L4_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS /* NOTE: low-level ops accept pwm_lowerhalf_s as first argument, but llops - * access can be found in stm32l4_pwm_dev_s + * access can be found in stm32_pwm_dev_s */ #define PWM_SETUP(dev) \ @@ -826,7 +826,7 @@ (dev)->llops->freq_update((struct pwm_lowerhalf_s *)dev, freq) #define PWM_TIM_ENABLE(dev, state) \ (dev)->llops->tim_enable((struct pwm_lowerhalf_s *)dev, state) -#ifdef CONFIG_DEBUG_STM32L4_PWM_INFO +#ifdef CONFIG_DEBUG_STM32_PWM_INFO # define PWM_DUMP_REGS(dev, msg) \ (dev)->llops->dump_regs((struct pwm_lowerhalf_s *)dev, msg) #else @@ -842,93 +842,93 @@ /* Timer mode */ -enum stm32l4_timmode_e +enum stm32_timmode_e { - STM32L4_TIMMODE_COUNTUP = 0, - STM32L4_TIMMODE_COUNTDOWN = 1, - STM32L4_TIMMODE_CENTER1 = 2, - STM32L4_TIMMODE_CENTER2 = 3, - STM32L4_TIMMODE_CENTER3 = 4, + STM32_TIMMODE_COUNTUP = 0, + STM32_TIMMODE_COUNTDOWN = 1, + STM32_TIMMODE_CENTER1 = 2, + STM32_TIMMODE_CENTER2 = 3, + STM32_TIMMODE_CENTER3 = 4, }; /* Timer output polarity */ -enum stm32l4_pwm_pol_e +enum stm32_pwm_pol_e { - STM32L4_POL_POS = 0, - STM32L4_POL_NEG = 1, + STM32_POL_POS = 0, + STM32_POL_NEG = 1, }; /* Timer output IDLE state */ -enum stm32l4_pwm_idle_e +enum stm32_pwm_idle_e { - STM32L4_IDLE_INACTIVE = 0, - STM32L4_IDLE_ACTIVE = 1 + STM32_IDLE_INACTIVE = 0, + STM32_IDLE_ACTIVE = 1 }; /* PWM channel mode */ -enum stm32l4_chanmode_e +enum stm32_chanmode_e { - STM32L4_CHANMODE_FRZN = 0, /* CCRx matches has no effects on outputs */ - STM32L4_CHANMODE_CHACT = 1, /* OCxREF active on match */ - STM32L4_CHANMODE_CHINACT = 2, /* OCxREF inactive on match */ - STM32L4_CHANMODE_OCREFTOG = 3, /* OCxREF toggles when TIMy_CNT=TIMyCCRx */ - STM32L4_CHANMODE_OCREFLO = 4, /* OCxREF is forced low */ - STM32L4_CHANMODE_OCREFHI = 5, /* OCxREF is forced high */ - STM32L4_CHANMODE_PWM1 = 6, /* PWM mode 1 */ - STM32L4_CHANMODE_PWM2 = 7, /* PWM mode 2 */ - STM32L4_CHANMODE_COMBINED1 = 8, /* Combined PWM mode 1 */ - STM32L4_CHANMODE_COMBINED2 = 9, /* Combined PWM mode 2 */ - STM32L4_CHANMODE_ASYMMETRIC1 = 10, /* Asymmetric PWM mode 1 */ - STM32L4_CHANMODE_ASYMMETRIC2 = 11, /* Asymmetric PWM mode 2 */ + STM32_CHANMODE_FRZN = 0, /* CCRx matches has no effects on outputs */ + STM32_CHANMODE_CHACT = 1, /* OCxREF active on match */ + STM32_CHANMODE_CHINACT = 2, /* OCxREF inactive on match */ + STM32_CHANMODE_OCREFTOG = 3, /* OCxREF toggles when TIMy_CNT=TIMyCCRx */ + STM32_CHANMODE_OCREFLO = 4, /* OCxREF is forced low */ + STM32_CHANMODE_OCREFHI = 5, /* OCxREF is forced high */ + STM32_CHANMODE_PWM1 = 6, /* PWM mode 1 */ + STM32_CHANMODE_PWM2 = 7, /* PWM mode 2 */ + STM32_CHANMODE_COMBINED1 = 8, /* Combined PWM mode 1 */ + STM32_CHANMODE_COMBINED2 = 9, /* Combined PWM mode 2 */ + STM32_CHANMODE_ASYMMETRIC1 = 10, /* Asymmetric PWM mode 1 */ + STM32_CHANMODE_ASYMMETRIC2 = 11, /* Asymmetric PWM mode 2 */ }; /* PWM timer channel */ -enum stm32l4_pwm_chan_e +enum stm32_pwm_chan_e { - STM32L4_PWM_CHAN1 = 1, - STM32L4_PWM_CHAN2 = 2, - STM32L4_PWM_CHAN3 = 3, - STM32L4_PWM_CHAN4 = 4, - STM32L4_PWM_CHAN5 = 5, - STM32L4_PWM_CHAN6 = 6, + STM32_PWM_CHAN1 = 1, + STM32_PWM_CHAN2 = 2, + STM32_PWM_CHAN3 = 3, + STM32_PWM_CHAN4 = 4, + STM32_PWM_CHAN5 = 5, + STM32_PWM_CHAN6 = 6, }; /* PWM timer channel output */ -enum stm32l4_pwm_output_e +enum stm32_pwm_output_e { - STM32L4_PWM_OUT1 = (1 << 0), - STM32L4_PWM_OUT1N = (1 << 1), - STM32L4_PWM_OUT2 = (1 << 2), - STM32L4_PWM_OUT2N = (1 << 3), - STM32L4_PWM_OUT3 = (1 << 4), - STM32L4_PWM_OUT3N = (1 << 5), - STM32L4_PWM_OUT4 = (1 << 6), + STM32_PWM_OUT1 = (1 << 0), + STM32_PWM_OUT1N = (1 << 1), + STM32_PWM_OUT2 = (1 << 2), + STM32_PWM_OUT2N = (1 << 3), + STM32_PWM_OUT3 = (1 << 4), + STM32_PWM_OUT3N = (1 << 5), + STM32_PWM_OUT4 = (1 << 6), /* 1 << 7 reserved - no complementary output for CH4 */ /* Only available inside micro */ - STM32L4_PWM_OUT5 = (1 << 8), + STM32_PWM_OUT5 = (1 << 8), /* 1 << 9 reserved - no complementary output for CH5 */ - STM32L4_PWM_OUT6 = (1 << 10), + STM32_PWM_OUT6 = (1 << 10), /* 1 << 11 reserved - no complementary output for CH6 */ }; -#ifdef CONFIG_STM32L4_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS /* This structure provides the publicly visible representation of the * "lower-half" PWM driver structure. */ -struct stm32l4_pwm_dev_s +struct stm32_pwm_dev_s { /* The first field of this state structure must be a pointer to the PWM * callback structure to be consistent with upper-half PWM driver. @@ -938,7 +938,7 @@ struct stm32l4_pwm_dev_s /* Publicly visible portion of the "lower-half" PWM driver structure */ - const struct stm32l4_pwm_ops_s *llops; + const struct stm32_pwm_ops_s *llops; /* Require cast-compatibility with private "lower-half" PWM structure */ }; @@ -946,7 +946,7 @@ struct stm32l4_pwm_dev_s /* Low-level operations for PWM */ struct pwm_lowerhalf_s; -struct stm32l4_pwm_ops_s +struct stm32_pwm_ops_s { /* Update CCR register */ @@ -1008,7 +1008,7 @@ struct stm32l4_pwm_ops_s #endif }; -#endif /* CONFIG_STM32L4_PWM_LL_OPS */ +#endif /* CONFIG_STM32_PWM_LL_OPS */ /**************************************************************************** * Public Data @@ -1030,7 +1030,7 @@ extern "C" ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_pwminitialize + * Name: stm32_pwminitialize * * Description: * Initialize one timer for use with the upper_level PWM driver. @@ -1046,10 +1046,10 @@ extern "C" * ****************************************************************************/ -struct pwm_lowerhalf_s *stm32l4_pwminitialize(int timer); +struct pwm_lowerhalf_s *stm32_pwminitialize(int timer); /**************************************************************************** - * Name: stm32l4_lp_pwminitialize + * Name: stm32_lp_pwminitialize * * Description: * Initialize one low-power timer for use with the upper_level PWM driver. @@ -1065,7 +1065,7 @@ struct pwm_lowerhalf_s *stm32l4_pwminitialize(int timer); * ****************************************************************************/ -struct pwm_lowerhalf_s *stm32l4_lp_pwminitialize(int timer); +struct pwm_lowerhalf_s *stm32_lp_pwminitialize(int timer); #undef EXTERN #if defined(__cplusplus) @@ -1073,5 +1073,5 @@ struct pwm_lowerhalf_s *stm32l4_lp_pwminitialize(int timer); #endif #endif /* __ASSEMBLY__ */ -#endif /* CONFIG_STM32L4_TIMx_PWM */ +#endif /* CONFIG_STM32_TIMx_PWM */ #endif /* __ARCH_ARM_SRC_STM32L4_STM32L4_PWM_H */ diff --git a/arch/arm/src/stm32l4/stm32l4_pwr.c b/arch/arm/src/stm32l4/stm32l4_pwr.c index cd78d8d6d436d..5bd1d6db51eee 100644 --- a/arch/arm/src/stm32l4/stm32l4_pwr.c +++ b/arch/arm/src/stm32l4/stm32l4_pwr.c @@ -39,14 +39,14 @@ * Private Functions ****************************************************************************/ -static inline uint16_t stm32l4_pwr_getreg(uint8_t offset) +static inline uint16_t stm32_pwr_getreg(uint8_t offset) { - return (uint16_t)getreg32(STM32L4_PWR_BASE + (uint32_t)offset); + return (uint16_t)getreg32(STM32_PWR_BASE + (uint32_t)offset); } -static inline void stm32l4_pwr_putreg(uint8_t offset, uint16_t value) +static inline void stm32_pwr_putreg(uint8_t offset, uint16_t value) { - putreg32((uint32_t)value, STM32L4_PWR_BASE + (uint32_t)offset); + putreg32((uint32_t)value, STM32_PWR_BASE + (uint32_t)offset); } /**************************************************************************** @@ -70,12 +70,12 @@ static inline void stm32l4_pwr_putreg(uint8_t offset, uint16_t value) * ****************************************************************************/ -bool stm32l4_pwr_enableclk(bool enable) +bool stm32_pwr_enableclk(bool enable) { uint32_t regval; bool wasenabled; - regval = getreg32(STM32L4_RCC_APB1ENR1); + regval = getreg32(STM32_RCC_APB1ENR1); wasenabled = ((regval & RCC_APB1ENR1_PWREN) != 0); /* Power interface clock enable. */ @@ -85,21 +85,21 @@ bool stm32l4_pwr_enableclk(bool enable) /* Disable power interface clock */ regval &= ~RCC_APB1ENR1_PWREN; - putreg32(regval, STM32L4_RCC_APB1ENR1); + putreg32(regval, STM32_RCC_APB1ENR1); } else if (!wasenabled && enable) { /* Enable power interface clock */ regval |= RCC_APB1ENR1_PWREN; - putreg32(regval, STM32L4_RCC_APB1ENR1); + putreg32(regval, STM32_RCC_APB1ENR1); } return wasenabled; } /**************************************************************************** - * Name: stm32l4_pwr_enablebkp + * Name: stm32_pwr_enablebkp * * Description: * Enables access to the backup domain (RTC registers, RTC backup data @@ -113,14 +113,14 @@ bool stm32l4_pwr_enableclk(bool enable) * ****************************************************************************/ -bool stm32l4_pwr_enablebkp(bool writable) +bool stm32_pwr_enablebkp(bool writable) { uint16_t regval; bool waswritable; /* Get the current state of the STM32L4 PWR control register 1 */ - regval = stm32l4_pwr_getreg(STM32L4_PWR_CR1_OFFSET); + regval = stm32_pwr_getreg(STM32_PWR_CR1_OFFSET); waswritable = ((regval & PWR_CR1_DBP) != 0); /* Enable or disable the ability to write */ @@ -130,14 +130,14 @@ bool stm32l4_pwr_enablebkp(bool writable) /* Disable backup domain access */ regval &= ~PWR_CR1_DBP; - stm32l4_pwr_putreg(STM32L4_PWR_CR1_OFFSET, regval); + stm32_pwr_putreg(STM32_PWR_CR1_OFFSET, regval); } else if (!waswritable && writable) { /* Enable backup domain access */ regval |= PWR_CR1_DBP; - stm32l4_pwr_putreg(STM32L4_PWR_CR1_OFFSET, regval); + stm32_pwr_putreg(STM32_PWR_CR1_OFFSET, regval); /* Enable does not happen right away */ @@ -148,7 +148,7 @@ bool stm32l4_pwr_enablebkp(bool writable) } /**************************************************************************** - * Name: stm32l4_pwr_enableusv + * Name: stm32_pwr_enableusv * * Description: * Enables or disables the USB Supply Valid monitoring. Setting this bit @@ -163,23 +163,23 @@ bool stm32l4_pwr_enablebkp(bool writable) * ****************************************************************************/ -bool stm32l4_pwr_enableusv(bool set) +bool stm32_pwr_enableusv(bool set) { uint32_t regval; bool was_set; bool was_clk_enabled; - regval = getreg32(STM32L4_RCC_APB1ENR1); + regval = getreg32(STM32_RCC_APB1ENR1); was_clk_enabled = ((regval & RCC_APB1ENR1_PWREN) != 0); if (!was_clk_enabled) { - stm32l4_pwr_enableclk(true); + stm32_pwr_enableclk(true); } /* Get the current state of the STM32L4 PWR control register 2 */ - regval = stm32l4_pwr_getreg(STM32L4_PWR_CR2_OFFSET); + regval = stm32_pwr_getreg(STM32_PWR_CR2_OFFSET); was_set = ((regval & PWR_CR2_USV) != 0); /* Enable or disable the ability to write */ @@ -189,26 +189,26 @@ bool stm32l4_pwr_enableusv(bool set) /* Disable the Vddusb monitoring */ regval &= ~PWR_CR2_USV; - stm32l4_pwr_putreg(STM32L4_PWR_CR2_OFFSET, regval); + stm32_pwr_putreg(STM32_PWR_CR2_OFFSET, regval); } else if (!was_set && set) { /* Enable the Vddusb monitoring */ regval |= PWR_CR2_USV; - stm32l4_pwr_putreg(STM32L4_PWR_CR2_OFFSET, regval); + stm32_pwr_putreg(STM32_PWR_CR2_OFFSET, regval); } if (!was_clk_enabled) { - stm32l4_pwr_enableclk(false); + stm32_pwr_enableclk(false); } return was_set; } /**************************************************************************** - * Name: stm32l4_pwr_enable_pvme2 + * Name: stm32_pwr_enable_pvme2 * * Description: * Enables or disables the peripheral voltage monitoring for Vddio2. @@ -221,24 +221,24 @@ bool stm32l4_pwr_enableusv(bool set) * ****************************************************************************/ -#if !defined(CONFIG_STM32L4_STM32L4X3) -bool stm32l4_pwr_enable_pvme2(bool set) +#if !defined(CONFIG_STM32_STM32L4X3) +bool stm32_pwr_enable_pvme2(bool set) { uint32_t regval; bool was_set; bool was_clk_enabled; - regval = getreg32(STM32L4_RCC_APB1ENR1); + regval = getreg32(STM32_RCC_APB1ENR1); was_clk_enabled = ((regval & RCC_APB1ENR1_PWREN) != 0); if (!was_clk_enabled) { - stm32l4_pwr_enableclk(true); + stm32_pwr_enableclk(true); } /* Get the current state of the STM32L4 PWR control register 2 */ - regval = stm32l4_pwr_getreg(STM32L4_PWR_CR2_OFFSET); + regval = stm32_pwr_getreg(STM32_PWR_CR2_OFFSET); was_set = ((regval & PWR_CR2_PVME2) != 0); /* Enable or disable the ability to write */ @@ -248,26 +248,26 @@ bool stm32l4_pwr_enable_pvme2(bool set) /* Disable the Vddio2 monitoring */ regval &= ~PWR_CR2_PVME2; - stm32l4_pwr_putreg(STM32L4_PWR_CR2_OFFSET, regval); + stm32_pwr_putreg(STM32_PWR_CR2_OFFSET, regval); } else if (!was_set && set) { /* Enable the Vddio2 monitoring */ regval |= PWR_CR2_PVME2; - stm32l4_pwr_putreg(STM32L4_PWR_CR2_OFFSET, regval); + stm32_pwr_putreg(STM32_PWR_CR2_OFFSET, regval); } if (!was_clk_enabled) { - stm32l4_pwr_enableclk(false); + stm32_pwr_enableclk(false); } return was_set; } /**************************************************************************** - * Name: stm32l4_pwr_get_pvmo2 + * Name: stm32_pwr_get_pvmo2 * * Description: * Get value of peripheral voltage monitor output 2 (Vddio2). @@ -278,33 +278,33 @@ bool stm32l4_pwr_enable_pvme2(bool set) * ****************************************************************************/ -bool stm32l4_pwr_get_pvmo2(void) +bool stm32_pwr_get_pvmo2(void) { uint32_t regval; bool was_clk_enabled; - regval = getreg32(STM32L4_RCC_APB1ENR1); + regval = getreg32(STM32_RCC_APB1ENR1); was_clk_enabled = ((regval & RCC_APB1ENR1_PWREN) != 0); if (!was_clk_enabled) { - stm32l4_pwr_enableclk(true); + stm32_pwr_enableclk(true); } /* Get the current state of the STM32L4 SR2 control register 2 */ - regval = stm32l4_pwr_getreg(STM32L4_PWR_SR2_OFFSET); + regval = stm32_pwr_getreg(STM32_PWR_SR2_OFFSET); if (!was_clk_enabled) { - stm32l4_pwr_enableclk(false); + stm32_pwr_enableclk(false); } return !!(regval & PWR_SR2_PVMO2); } /**************************************************************************** - * Name: stm32l4_pwr_vddio2_valid + * Name: stm32_pwr_vddio2_valid * * Description: * Report that the Vddio2 independent I/Os supply voltage is valid or not. @@ -319,23 +319,23 @@ bool stm32l4_pwr_get_pvmo2(void) * ****************************************************************************/ -bool stm32l4_pwr_vddio2_valid(bool set) +bool stm32_pwr_vddio2_valid(bool set) { uint32_t regval; bool was_set; bool was_clk_enabled; - regval = getreg32(STM32L4_RCC_APB1ENR1); + regval = getreg32(STM32_RCC_APB1ENR1); was_clk_enabled = ((regval & RCC_APB1ENR1_PWREN) != 0); if (!was_clk_enabled) { - stm32l4_pwr_enableclk(true); + stm32_pwr_enableclk(true); } /* Get the current state of the STM32L4 PWR control register 2 */ - regval = stm32l4_pwr_getreg(STM32L4_PWR_CR2_OFFSET); + regval = stm32_pwr_getreg(STM32_PWR_CR2_OFFSET); was_set = ((regval & PWR_CR2_IOSV) != 0); /* Enable or disable the ability to write */ @@ -345,19 +345,19 @@ bool stm32l4_pwr_vddio2_valid(bool set) /* Reset the Vddio2 independent I/O supply valid bit. */ regval &= ~PWR_CR2_IOSV; - stm32l4_pwr_putreg(STM32L4_PWR_CR2_OFFSET, regval); + stm32_pwr_putreg(STM32_PWR_CR2_OFFSET, regval); } else if (!was_set && set) { /* Set the Vddio2 independent I/O supply valid bit. */ regval |= PWR_CR2_IOSV; - stm32l4_pwr_putreg(STM32L4_PWR_CR2_OFFSET, regval); + stm32_pwr_putreg(STM32_PWR_CR2_OFFSET, regval); } if (!was_clk_enabled) { - stm32l4_pwr_enableclk(false); + stm32_pwr_enableclk(false); } return was_set; @@ -392,7 +392,7 @@ void stm32_pwr_setvos(int vos) return; } - regval = getreg32(STM32L4_PWR_CR1); + regval = getreg32(STM32_PWR_CR1); regval &= ~PWR_CR1_VOS_MASK; if (vos == 1) @@ -404,5 +404,5 @@ void stm32_pwr_setvos(int vos) regval |= PWR_CR1_VOS_RANGE2; } - putreg32(regval, STM32L4_PWR_CR1); + putreg32(regval, STM32_PWR_CR1); } diff --git a/arch/arm/src/stm32l4/stm32l4_pwr.h b/arch/arm/src/stm32l4/stm32l4_pwr.h index 0208128cae8f4..c10f8a982f3be 100644 --- a/arch/arm/src/stm32l4/stm32l4_pwr.h +++ b/arch/arm/src/stm32l4/stm32l4_pwr.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32L4_STM32L4_PWR_H -#define __ARCH_ARM_SRC_STM32L4_STM32L4_PWR_H +#ifndef __ARCH_ARM_SRC_STM32L4_STM32_PWR_H +#define __ARCH_ARM_SRC_STM32L4_STM32_PWR_H /**************************************************************************** * Included Files @@ -70,10 +70,10 @@ extern "C" * ****************************************************************************/ -bool stm32l4_pwr_enableclk(bool enable); +bool stm32_pwr_enableclk(bool enable); /**************************************************************************** - * Name: stm32l4_pwr_enablebkp + * Name: stm32_pwr_enablebkp * * Description: * Enables access to the backup domain (RTC registers, RTC backup data @@ -87,10 +87,10 @@ bool stm32l4_pwr_enableclk(bool enable); * ****************************************************************************/ -bool stm32l4_pwr_enablebkp(bool writable); +bool stm32_pwr_enablebkp(bool writable); /**************************************************************************** - * Name: stm32l4_pwr_enableusv + * Name: stm32_pwr_enableusv * * Description: * Enables or disables the USB Supply Valid monitoring. Setting this bit @@ -105,10 +105,10 @@ bool stm32l4_pwr_enablebkp(bool writable); * ****************************************************************************/ -bool stm32l4_pwr_enableusv(bool set); +bool stm32_pwr_enableusv(bool set); /**************************************************************************** - * Name: stm32l4_pwr_enable_pvme2 + * Name: stm32_pwr_enable_pvme2 * * Description: * Enables or disables the peripheral voltage monitoring for Vddio2. @@ -121,12 +121,12 @@ bool stm32l4_pwr_enableusv(bool set); * ****************************************************************************/ -#if !defined(CONFIG_STM32L4_STM32L4X3) -bool stm32l4_pwr_enable_pvme2(bool set); +#if !defined(CONFIG_STM32_STM32L4X3) +bool stm32_pwr_enable_pvme2(bool set); #endif /**************************************************************************** - * Name: stm32l4_pwr_get_pvmo2 + * Name: stm32_pwr_get_pvmo2 * * Description: * Get value of peripheral voltage monitor output 2 (Vddio2). @@ -137,12 +137,12 @@ bool stm32l4_pwr_enable_pvme2(bool set); * ****************************************************************************/ -#if !defined(CONFIG_STM32L4_STM32L4X3) -bool stm32l4_pwr_get_pvmo2(void); +#if !defined(CONFIG_STM32_STM32L4X3) +bool stm32_pwr_get_pvmo2(void); #endif /**************************************************************************** - * Name: stm32l4_pwr_vddio2_valid + * Name: stm32_pwr_vddio2_valid * * Description: * Report that the Vddio2 independent I/Os supply voltage is valid or not. @@ -156,8 +156,8 @@ bool stm32l4_pwr_get_pvmo2(void); * True: The bit was previously set. ****************************************************************************/ -#if !defined(CONFIG_STM32L4_STM32L4X3) -bool stm32l4_pwr_vddio2_valid(bool set); +#if !defined(CONFIG_STM32_STM32L4X3) +bool stm32_pwr_vddio2_valid(bool set); #endif /**************************************************************************** @@ -187,4 +187,4 @@ void stm32_pwr_setvos(int vos); #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32L4_STM32L4_PWR_H */ +#endif /* __ARCH_ARM_SRC_STM32L4_STM32_PWR_H */ diff --git a/arch/arm/src/stm32l4/stm32l4_qencoder.c b/arch/arm/src/stm32l4/stm32l4_qencoder.c index 7f12c3b3990b8..18ca8468adf45 100644 --- a/arch/arm/src/stm32l4/stm32l4_qencoder.c +++ b/arch/arm/src/stm32l4/stm32l4_qencoder.c @@ -40,7 +40,7 @@ #include "chip.h" #include "arm_internal.h" -#include "stm32l4.h" +#include "stm32.h" #include "stm32l4_gpio.h" #include "stm32l4_tim.h" #include "stm32l4_qencoder.h" @@ -62,14 +62,14 @@ /* If TIM2 or TIM5 are enabled, then we have 32-bit timers */ -#if defined(CONFIG_STM32L4_TIM2_QE) || defined(CONFIG_STM32L4_TIM5_QE) +#if defined(CONFIG_STM32_TIM2_QE) || defined(CONFIG_STM32_TIM5_QE) # define HAVE_32BIT_TIMERS 1 #endif /* If TIM1,3,4, or 8 are enabled, then we have 16-bit timers */ -#if defined(CONFIG_STM32L4_TIM1_QE) || defined(CONFIG_STM32L4_TIM3_QE) || \ - defined(CONFIG_STM32L4_TIM4_QE) || defined(CONFIG_STM32L4_TIM8_QE) +#if defined(CONFIG_STM32_TIM1_QE) || defined(CONFIG_STM32_TIM3_QE) || \ + defined(CONFIG_STM32_TIM4_QE) || defined(CONFIG_STM32_TIM8_QE) # define HAVE_16BIT_TIMERS 1 #endif @@ -91,65 +91,65 @@ /* Input filter *************************************************************/ -#ifdef CONFIG_STM32L4_QENCODER_FILTER -# if defined(CONFIG_STM32L4_QENCODER_SAMPLE_FDTS) -# if defined(CONFIG_STM32L4_QENCODER_SAMPLE_EVENT_1) -# define STM32L4_QENCODER_ICF GTIM_CCMR_ICF_NOFILT +#ifdef CONFIG_STM32_QENCODER_FILTER +# if defined(CONFIG_STM32_QENCODER_SAMPLE_FDTS) +# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_1) +# define STM32_QENCODER_ICF GTIM_CCMR_ICF_NOFILT # endif -# elif defined(CONFIG_STM32L4_QENCODER_SAMPLE_CKINT) -# if defined(CONFIG_STM32L4_QENCODER_SAMPLE_EVENT_2) -# define STM32L4_QENCODER_ICF GTIM_CCMR_ICF_FCKINT2 -# elif defined(CONFIG_STM32L4_QENCODER_SAMPLE_EVENT_4) -# define STM32L4_QENCODER_ICF GTIM_CCMR_ICF_FCKINT4 -# elif defined(CONFIG_STM32L4_QENCODER_SAMPLE_EVENT_8) -# define STM32L4_QENCODER_ICF GTIM_CCMR_ICF_FCKINT8 +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_CKINT) +# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_2) +# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FCKINT2 +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_4) +# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FCKINT4 +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_8) +# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FCKINT8 # endif -# elif defined(CONFIG_STM32L4_QENCODER_SAMPLE_FDTS_2) -# if defined(CONFIG_STM32L4_QENCODER_SAMPLE_EVENT_6) -# define STM32L4_QENCODER_ICF GTIM_CCMR_ICF_FDTSd26 -# elif defined(CONFIG_STM32L4_QENCODER_SAMPLE_EVENT_8) -# define STM32L4_QENCODER_ICF GTIM_CCMR_ICF_FDTSd28 +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_FDTS_2) +# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_6) +# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd26 +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_8) +# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd28 # endif -# elif defined(CONFIG_STM32L4_QENCODER_SAMPLE_FDTS_4) -# if defined(CONFIG_STM32L4_QENCODER_SAMPLE_EVENT_6) -# define STM32L4_QENCODER_ICF GTIM_CCMR_ICF_FDTSd46 -# elif defined(CONFIG_STM32L4_QENCODER_SAMPLE_EVENT_8) -# define STM32L4_QENCODER_ICF GTIM_CCMR_ICF_FDTSd48 +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_FDTS_4) +# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_6) +# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd46 +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_8) +# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd48 # endif -# elif defined(CONFIG_STM32L4_QENCODER_SAMPLE_FDTS_8) -# if defined(CONFIG_STM32L4_QENCODER_SAMPLE_EVENT_6) -# define STM32L4_QENCODER_ICF GTIM_CCMR_ICF_FDTSd86 -# elif defined(CONFIG_STM32L4_QENCODER_SAMPLE_EVENT_8) -# define STM32L4_QENCODER_ICF GTIM_CCMR_ICF_FDTSd88 +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_FDTS_8) +# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_6) +# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd86 +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_8) +# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd88 # endif -# elif defined(CONFIG_STM32L4_QENCODER_SAMPLE_FDTS_16) -# if defined(CONFIG_STM32L4_QENCODER_SAMPLE_EVENT_5) -# define STM32L4_QENCODER_ICF GTIM_CCMR_ICF_FDTSd165 -# elif defined(CONFIG_STM32L4_QENCODER_SAMPLE_EVENT_6) -# define STM32L4_QENCODER_ICF GTIM_CCMR_ICF_FDTSd166 -# elif defined(CONFIG_STM32L4_QENCODER_SAMPLE_EVENT_8) -# define STM32L4_QENCODER_ICF GTIM_CCMR_ICF_FDTSd168 +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_FDTS_16) +# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_5) +# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd165 +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_6) +# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd166 +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_8) +# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd168 # endif -# elif defined(CONFIG_STM32L4_QENCODER_SAMPLE_FDTS_32) -# if defined(CONFIG_STM32L4_QENCODER_SAMPLE_EVENT_5) -# define STM32L4_QENCODER_ICF GTIM_CCMR_ICF_FDTSd325 -# elif defined(CONFIG_STM32L4_QENCODER_SAMPLE_EVENT_6) -# define STM32L4_QENCODER_ICF GTIM_CCMR_ICF_FDTSd326 -# elif defined(CONFIG_STM32L4_QENCODER_SAMPLE_EVENT_8) -# define STM32L4_QENCODER_ICF GTIM_CCMR_ICF_FDTSd328 +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_FDTS_32) +# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_5) +# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd325 +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_6) +# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd326 +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_8) +# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd328 # endif # endif -# ifndef STM32L4_QENCODER_ICF +# ifndef STM32_QENCODER_ICF # warning "Invalid encoder filter combination, filter disabled" # endif #endif -#ifndef STM32L4_QENCODER_ICF -# define STM32L4_QENCODER_ICF GTIM_CCMR_ICF_NOFILT +#ifndef STM32_QENCODER_ICF +# define STM32_QENCODER_ICF GTIM_CCMR_ICF_NOFILT #endif -#define STM32L4_GPIO_INPUT_FLOAT (GPIO_INPUT | GPIO_FLOAT) +#define STM32_GPIO_INPUT_FLOAT (GPIO_INPUT | GPIO_FLOAT) /* Debug ********************************************************************/ @@ -163,7 +163,7 @@ #ifdef CONFIG_DEBUG_SENSORS # ifdef CONFIG_DEBUG_INFO -# define qe_dumpgpio(p,m) stm32l4_dumpgpio(p,m) +# define qe_dumpgpio(p,m) stm32_dumpgpio(p,m) # else # define qe_dumpgpio(p,m) # endif @@ -177,7 +177,7 @@ /* Constant configuration structure that is retained in FLASH */ -struct stm32l4_qeconfig_s +struct stm32_qeconfig_s { uint8_t timid; /* Timer ID {1,2,3,4,5,8} */ uint8_t irq; /* Timer update IRQ */ @@ -192,7 +192,7 @@ struct stm32l4_qeconfig_s /* Overall, RAM-based state structure */ -struct stm32l4_lowerhalf_s +struct stm32_lowerhalf_s { /* The first field of this state structure must be a pointer to the lower- * half callback structure: @@ -202,7 +202,7 @@ struct stm32l4_lowerhalf_s /* STM32 driver-specific fields: */ - const struct stm32l4_qeconfig_s *config; /* static onfiguration */ + const struct stm32_qeconfig_s *config; /* static onfiguration */ bool inuse; /* True: The lower-half driver is in-use */ @@ -218,38 +218,38 @@ struct stm32l4_lowerhalf_s /* Helper functions */ -static uint16_t stm32l4_getreg16(struct stm32l4_lowerhalf_s *priv, +static uint16_t stm32_getreg16(struct stm32_lowerhalf_s *priv, int offset); -static void stm32l4_putreg16(struct stm32l4_lowerhalf_s *priv, +static void stm32_putreg16(struct stm32_lowerhalf_s *priv, int offset, uint16_t value); -static uint32_t stm32l4_getreg32(struct stm32l4_lowerhalf_s *priv, +static uint32_t stm32_getreg32(struct stm32_lowerhalf_s *priv, int offset); -static void stm32l4_putreg32(struct stm32l4_lowerhalf_s *priv, +static void stm32_putreg32(struct stm32_lowerhalf_s *priv, int offset, uint32_t value); #if defined(CONFIG_DEBUG_SENSORS) && defined(CONFIG_DEBUG_INFO) -static void stm32l4_dumpregs(struct stm32l4_lowerhalf_s *priv, +static void stm32_dumpregs(struct stm32_lowerhalf_s *priv, const char *msg); #else -# define stm32l4_dumpregs(priv,msg) +# define stm32_dumpregs(priv,msg) #endif -static struct stm32l4_lowerhalf_s *stm32l4_tim2lower(int tim); +static struct stm32_lowerhalf_s *stm32_tim2lower(int tim); /* Interrupt handling */ #ifdef HAVE_16BIT_TIMERS -static int stm32l4_interrupt(int irq, void *context, void *arg); +static int stm32_interrupt(int irq, void *context, void *arg); #endif /* Lower-half Quadrature Encoder Driver Methods */ -static int stm32l4_setup(struct qe_lowerhalf_s *lower); -static int stm32l4_shutdown(struct qe_lowerhalf_s *lower); -static int stm32l4_position(struct qe_lowerhalf_s *lower, +static int stm32_setup(struct qe_lowerhalf_s *lower); +static int stm32_shutdown(struct qe_lowerhalf_s *lower); +static int stm32_position(struct qe_lowerhalf_s *lower, int32_t *pos); -static int stm32l4_reset(struct qe_lowerhalf_s *lower); -static int stm32l4_ioctl(struct qe_lowerhalf_s *lower, int cmd, +static int stm32_reset(struct qe_lowerhalf_s *lower); +static int stm32_ioctl(struct qe_lowerhalf_s *lower, int cmd, unsigned long arg); /**************************************************************************** @@ -260,32 +260,32 @@ static int stm32l4_ioctl(struct qe_lowerhalf_s *lower, int cmd, static const struct qe_ops_s g_qecallbacks = { - .setup = stm32l4_setup, - .shutdown = stm32l4_shutdown, - .position = stm32l4_position, + .setup = stm32_setup, + .shutdown = stm32_shutdown, + .position = stm32_position, .setposmax = NULL, /* not supported yet */ - .reset = stm32l4_reset, + .reset = stm32_reset, .setindex = NULL, /* not supported yet */ - .ioctl = stm32l4_ioctl, + .ioctl = stm32_ioctl, }; /* Per-timer state structures */ -#ifdef CONFIG_STM32L4_TIM1_QE -static const struct stm32l4_qeconfig_s g_tim1config = +#ifdef CONFIG_STM32_TIM1_QE +static const struct stm32_qeconfig_s g_tim1config = { .timid = 1, - .irq = STM32L4_IRQ_TIM1UP, + .irq = STM32_IRQ_TIM1UP, #ifdef HAVE_MIXEDWIDTH_TIMERS .width = TIM1_BITWIDTH, #endif - .base = STM32L4_TIM1_BASE, - .psc = CONFIG_STM32L4_TIM1_QEPSC, + .base = STM32_TIM1_BASE, + .psc = CONFIG_STM32_TIM1_QEPSC, .ti1cfg = GPIO_TIM1_CH1IN, .ti2cfg = GPIO_TIM1_CH2IN, }; -static struct stm32l4_lowerhalf_s g_tim1lower = +static struct stm32_lowerhalf_s g_tim1lower = { .ops = &g_qecallbacks, .config = &g_tim1config, @@ -295,21 +295,21 @@ static struct stm32l4_lowerhalf_s g_tim1lower = #endif -#ifdef CONFIG_STM32L4_TIM2_QE -static const struct stm32l4_qeconfig_s g_tim2config = +#ifdef CONFIG_STM32_TIM2_QE +static const struct stm32_qeconfig_s g_tim2config = { .timid = 2, - .irq = STM32L4_IRQ_TIM2, + .irq = STM32_IRQ_TIM2, #ifdef HAVE_MIXEDWIDTH_TIMERS .width = TIM2_BITWIDTH, #endif - .base = STM32L4_TIM2_BASE, - .psc = CONFIG_STM32L4_TIM2_QEPSC, + .base = STM32_TIM2_BASE, + .psc = CONFIG_STM32_TIM2_QEPSC, .ti1cfg = GPIO_TIM2_CH1IN, .ti2cfg = GPIO_TIM2_CH2IN, }; -static struct stm32l4_lowerhalf_s g_tim2lower = +static struct stm32_lowerhalf_s g_tim2lower = { .ops = &g_qecallbacks, .config = &g_tim2config, @@ -319,21 +319,21 @@ static struct stm32l4_lowerhalf_s g_tim2lower = #endif -#ifdef CONFIG_STM32L4_TIM3_QE -static const struct stm32l4_qeconfig_s g_tim3config = +#ifdef CONFIG_STM32_TIM3_QE +static const struct stm32_qeconfig_s g_tim3config = { .timid = 3, - .irq = STM32L4_IRQ_TIM3, + .irq = STM32_IRQ_TIM3, #ifdef HAVE_MIXEDWIDTH_TIMERS .width = TIM3_BITWIDTH, #endif - .base = STM32L4_TIM3_BASE, - .psc = CONFIG_STM32L4_TIM3_QEPSC, + .base = STM32_TIM3_BASE, + .psc = CONFIG_STM32_TIM3_QEPSC, .ti1cfg = GPIO_TIM3_CH1IN, .ti2cfg = GPIO_TIM3_CH2IN, }; -static struct stm32l4_lowerhalf_s g_tim3lower = +static struct stm32_lowerhalf_s g_tim3lower = { .ops = &g_qecallbacks, .config = &g_tim3config, @@ -343,21 +343,21 @@ static struct stm32l4_lowerhalf_s g_tim3lower = #endif -#ifdef CONFIG_STM32L4_TIM4_QE -static const struct stm32l4_qeconfig_s g_tim4config = +#ifdef CONFIG_STM32_TIM4_QE +static const struct stm32_qeconfig_s g_tim4config = { .timid = 4, - .irq = STM32L4_IRQ_TIM4, + .irq = STM32_IRQ_TIM4, #ifdef HAVE_MIXEDWIDTH_TIMERS .width = TIM4_BITWIDTH, #endif - .base = STM32L4_TIM4_BASE, - .psc = CONFIG_STM32L4_TIM4_QEPSC, + .base = STM32_TIM4_BASE, + .psc = CONFIG_STM32_TIM4_QEPSC, .ti1cfg = GPIO_TIM4_CH1IN, .ti2cfg = GPIO_TIM4_CH2IN, }; -static struct stm32l4_lowerhalf_s g_tim4lower = +static struct stm32_lowerhalf_s g_tim4lower = { .ops = &g_qecallbacks, .config = &g_tim4config, @@ -367,21 +367,21 @@ static struct stm32l4_lowerhalf_s g_tim4lower = #endif -#ifdef CONFIG_STM32L4_TIM5_QE -static const struct stm32l4_qeconfig_s g_tim5config = +#ifdef CONFIG_STM32_TIM5_QE +static const struct stm32_qeconfig_s g_tim5config = { .timid = 5, - .irq = STM32L4_IRQ_TIM5, + .irq = STM32_IRQ_TIM5, #ifdef HAVE_MIXEDWIDTH_TIMERS .width = TIM5_BITWIDTH, #endif - .base = STM32L4_TIM5_BASE, - .psc = CONFIG_STM32L4_TIM5_QEPSC, + .base = STM32_TIM5_BASE, + .psc = CONFIG_STM32_TIM5_QEPSC, .ti1cfg = GPIO_TIM5_CH1IN, .ti2cfg = GPIO_TIM5_CH2IN, }; -static struct stm32l4_lowerhalf_s g_tim5lower = +static struct stm32_lowerhalf_s g_tim5lower = { .ops = &g_qecallbacks, .config = &g_tim5config, @@ -391,21 +391,21 @@ static struct stm32l4_lowerhalf_s g_tim5lower = #endif -#ifdef CONFIG_STM32L4_TIM8_QE -static const struct stm32l4_qeconfig_s g_tim8config = +#ifdef CONFIG_STM32_TIM8_QE +static const struct stm32_qeconfig_s g_tim8config = { .timid = 8, - .irq = STM32L4_IRQ_TIM8UP, + .irq = STM32_IRQ_TIM8UP, #ifdef HAVE_MIXEDWIDTH_TIMERS .width = TIM8_BITWIDTH, #endif - .base = STM32L4_TIM8_BASE, - .psc = CONFIG_STM32L4_TIM8_QEPSC, + .base = STM32_TIM8_BASE, + .psc = CONFIG_STM32_TIM8_QEPSC, .ti1cfg = GPIO_TIM8_CH1IN, .ti2cfg = GPIO_TIM8_CH2IN, }; -static struct stm32l4_lowerhalf_s g_tim8lower = +static struct stm32_lowerhalf_s g_tim8lower = { .ops = &g_qecallbacks, .config = &g_tim8config, @@ -420,7 +420,7 @@ static struct stm32l4_lowerhalf_s g_tim8lower = ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_getreg16 + * Name: stm32_getreg16 * * Description: * Read the value of a 16-bit timer register. @@ -434,14 +434,14 @@ static struct stm32l4_lowerhalf_s g_tim8lower = * ****************************************************************************/ -static uint16_t stm32l4_getreg16(struct stm32l4_lowerhalf_s *priv, +static uint16_t stm32_getreg16(struct stm32_lowerhalf_s *priv, int offset) { return getreg16(priv->config->base + offset); } /**************************************************************************** - * Name: stm32l4_putreg16 + * Name: stm32_putreg16 * * Description: * Write a value to a 16-bit timer register. @@ -455,7 +455,7 @@ static uint16_t stm32l4_getreg16(struct stm32l4_lowerhalf_s *priv, * ****************************************************************************/ -static void stm32l4_putreg16(struct stm32l4_lowerhalf_s *priv, +static void stm32_putreg16(struct stm32_lowerhalf_s *priv, int offset, uint16_t value) { @@ -463,7 +463,7 @@ static void stm32l4_putreg16(struct stm32l4_lowerhalf_s *priv, } /**************************************************************************** - * Name: stm32l4_getreg32 + * Name: stm32_getreg32 * * Description: * Read the value of a 32-bit timer register. @@ -480,14 +480,14 @@ static void stm32l4_putreg16(struct stm32l4_lowerhalf_s *priv, * ****************************************************************************/ -static uint32_t stm32l4_getreg32(struct stm32l4_lowerhalf_s *priv, +static uint32_t stm32_getreg32(struct stm32_lowerhalf_s *priv, int offset) { return getreg32(priv->config->base + offset); } /**************************************************************************** - * Name: stm32l4_putreg16 + * Name: stm32_putreg16 * * Description: * Write a value to a 32-bit timer register. @@ -504,7 +504,7 @@ static uint32_t stm32l4_getreg32(struct stm32l4_lowerhalf_s *priv, * ****************************************************************************/ -static void stm32l4_putreg32(struct stm32l4_lowerhalf_s *priv, +static void stm32_putreg32(struct stm32_lowerhalf_s *priv, int offset, uint32_t value) { @@ -512,7 +512,7 @@ static void stm32l4_putreg32(struct stm32l4_lowerhalf_s *priv, } /**************************************************************************** - * Name: stm32l4_dumpregs + * Name: stm32_dumpregs * * Description: * Dump all timer registers. @@ -526,85 +526,85 @@ static void stm32l4_putreg32(struct stm32l4_lowerhalf_s *priv, ****************************************************************************/ #if defined(CONFIG_DEBUG_SENSORS) && defined(CONFIG_DEBUG_INFO) -static void stm32l4_dumpregs(struct stm32l4_lowerhalf_s *priv, +static void stm32_dumpregs(struct stm32_lowerhalf_s *priv, const char *msg) { sninfo("%s:\n", msg); sninfo(" CR1: %04x CR2: %04x SMCR: %08" PRIx32 " DIER: %04x\n", - stm32l4_getreg16(priv, STM32L4_GTIM_CR1_OFFSET), - stm32l4_getreg16(priv, STM32L4_GTIM_CR2_OFFSET), - stm32l4_getreg32(priv, STM32L4_GTIM_SMCR_OFFSET), - stm32l4_getreg16(priv, STM32L4_GTIM_DIER_OFFSET)); + stm32_getreg16(priv, STM32_GTIM_CR1_OFFSET), + stm32_getreg16(priv, STM32_GTIM_CR2_OFFSET), + stm32_getreg32(priv, STM32_GTIM_SMCR_OFFSET), + stm32_getreg16(priv, STM32_GTIM_DIER_OFFSET)); sninfo(" SR: %04x EGR: %04x CCMR1: %08" PRIx32 " CCMR2: %08" PRIx32 "\n", - stm32l4_getreg16(priv, STM32L4_GTIM_SR_OFFSET), - stm32l4_getreg16(priv, STM32L4_GTIM_EGR_OFFSET), - stm32l4_getreg32(priv, STM32L4_GTIM_CCMR1_OFFSET), - stm32l4_getreg32(priv, STM32L4_GTIM_CCMR2_OFFSET)); + stm32_getreg16(priv, STM32_GTIM_SR_OFFSET), + stm32_getreg16(priv, STM32_GTIM_EGR_OFFSET), + stm32_getreg32(priv, STM32_GTIM_CCMR1_OFFSET), + stm32_getreg32(priv, STM32_GTIM_CCMR2_OFFSET)); sninfo(" CCER: %04x CNT: %08" PRIx32 " PSC: %04x" " ARR: %08" PRIx32 "\n", - stm32l4_getreg16(priv, STM32L4_GTIM_CCER_OFFSET), - stm32l4_getreg32(priv, STM32L4_GTIM_CNT_OFFSET), - stm32l4_getreg16(priv, STM32L4_GTIM_PSC_OFFSET), - stm32l4_getreg32(priv, STM32L4_GTIM_ARR_OFFSET)); + stm32_getreg16(priv, STM32_GTIM_CCER_OFFSET), + stm32_getreg32(priv, STM32_GTIM_CNT_OFFSET), + stm32_getreg16(priv, STM32_GTIM_PSC_OFFSET), + stm32_getreg32(priv, STM32_GTIM_ARR_OFFSET)); sninfo(" CCR1: %08" PRIx32 " CCR2: %08" PRIx32 "\n", - stm32l4_getreg32(priv, STM32L4_GTIM_CCR1_OFFSET), - stm32l4_getreg32(priv, STM32L4_GTIM_CCR2_OFFSET)); + stm32_getreg32(priv, STM32_GTIM_CCR1_OFFSET), + stm32_getreg32(priv, STM32_GTIM_CCR2_OFFSET)); sninfo(" CCR3: %08" PRIx32 " CCR4: %08" PRIx32 "\n", - stm32l4_getreg32(priv, STM32L4_GTIM_CCR3_OFFSET), - stm32l4_getreg32(priv, STM32L4_GTIM_CCR4_OFFSET)); -#if defined(CONFIG_STM32L4_TIM1_QE) || defined(CONFIG_STM32L4_TIM8_QE) + stm32_getreg32(priv, STM32_GTIM_CCR3_OFFSET), + stm32_getreg32(priv, STM32_GTIM_CCR4_OFFSET)); +#if defined(CONFIG_STM32_TIM1_QE) || defined(CONFIG_STM32_TIM8_QE) if (priv->config->timid == 1 || priv->config->timid == 8) { sninfo(" RCR: %04x BDTR: %04x DCR: %04x DMAR: %04x\n", - stm32l4_getreg16(priv, STM32L4_ATIM_RCR_OFFSET), - stm32l4_getreg16(priv, STM32L4_ATIM_BDTR_OFFSET), - stm32l4_getreg16(priv, STM32L4_ATIM_DCR_OFFSET), - stm32l4_getreg16(priv, STM32L4_ATIM_DMAR_OFFSET)); + stm32_getreg16(priv, STM32_ATIM_RCR_OFFSET), + stm32_getreg16(priv, STM32_ATIM_BDTR_OFFSET), + stm32_getreg16(priv, STM32_ATIM_DCR_OFFSET), + stm32_getreg16(priv, STM32_ATIM_DMAR_OFFSET)); } else #endif { sninfo(" DCR: %04x DMAR: %04x\n", - stm32l4_getreg16(priv, STM32L4_GTIM_DCR_OFFSET), - stm32l4_getreg16(priv, STM32L4_GTIM_DMAR_OFFSET)); + stm32_getreg16(priv, STM32_GTIM_DCR_OFFSET), + stm32_getreg16(priv, STM32_GTIM_DMAR_OFFSET)); } } #endif /**************************************************************************** - * Name: stm32l4_tim2lower + * Name: stm32_tim2lower * * Description: * Map a timer number to a device structure * ****************************************************************************/ -static struct stm32l4_lowerhalf_s *stm32l4_tim2lower(int tim) +static struct stm32_lowerhalf_s *stm32_tim2lower(int tim) { switch (tim) { -#ifdef CONFIG_STM32L4_TIM1_QE +#ifdef CONFIG_STM32_TIM1_QE case 1: return &g_tim1lower; #endif -#ifdef CONFIG_STM32L4_TIM2_QE +#ifdef CONFIG_STM32_TIM2_QE case 2: return &g_tim2lower; #endif -#ifdef CONFIG_STM32L4_TIM3_QE +#ifdef CONFIG_STM32_TIM3_QE case 3: return &g_tim3lower; #endif -#ifdef CONFIG_STM32L4_TIM4_QE +#ifdef CONFIG_STM32_TIM4_QE case 4: return &g_tim4lower; #endif -#ifdef CONFIG_STM32L4_TIM5_QE +#ifdef CONFIG_STM32_TIM5_QE case 5: return &g_tim5lower; #endif -#ifdef CONFIG_STM32L4_TIM8_QE +#ifdef CONFIG_STM32_TIM8_QE case 8: return &g_tim8lower; #endif @@ -614,7 +614,7 @@ static struct stm32l4_lowerhalf_s *stm32l4_tim2lower(int tim) } /**************************************************************************** - * Name: stm32l4_interrupt + * Name: stm32_interrupt * * Description: * Common timer interrupt handling. NOTE: Only 16-bit timers require timer @@ -623,10 +623,10 @@ static struct stm32l4_lowerhalf_s *stm32l4_tim2lower(int tim) ****************************************************************************/ #ifdef HAVE_16BIT_TIMERS -static int stm32l4_interrupt(int irq, void *context, void *arg) +static int stm32_interrupt(int irq, void *context, void *arg) { - struct stm32l4_lowerhalf_s *priv = - (struct stm32l4_lowerhalf_s *)arg; + struct stm32_lowerhalf_s *priv = + (struct stm32_lowerhalf_s *)arg; uint16_t regval; DEBUGASSERT(priv != NULL); @@ -635,18 +635,18 @@ static int stm32l4_interrupt(int irq, void *context, void *arg) * Nothing else is expected. */ - regval = stm32l4_getreg16(priv, STM32L4_GTIM_SR_OFFSET); + regval = stm32_getreg16(priv, STM32_GTIM_SR_OFFSET); DEBUGASSERT((regval & ATIM_SR_UIF) != 0); /* Clear the UIF interrupt bit */ - stm32l4_putreg16(priv, STM32L4_GTIM_SR_OFFSET, regval & ~GTIM_SR_UIF); + stm32_putreg16(priv, STM32_GTIM_SR_OFFSET, regval & ~GTIM_SR_UIF); /* Check the direction bit in the CR1 register and add or subtract the * maximum value, as appropriate. */ - regval = stm32l4_getreg16(priv, STM32L4_GTIM_CR1_OFFSET); + regval = stm32_getreg16(priv, STM32_GTIM_CR1_OFFSET); if ((regval & ATIM_CR1_DIR) != 0) { priv->position -= (int32_t)0x0000ffff; @@ -661,7 +661,7 @@ static int stm32l4_interrupt(int irq, void *context, void *arg) #endif /**************************************************************************** - * Name: stm32l4_setup + * Name: stm32_setup * * Description: * This method is called when the driver is opened. The lower half driver @@ -670,10 +670,10 @@ static int stm32l4_interrupt(int irq, void *context, void *arg) * ****************************************************************************/ -static int stm32l4_setup(struct qe_lowerhalf_s *lower) +static int stm32_setup(struct qe_lowerhalf_s *lower) { - struct stm32l4_lowerhalf_s *priv = - (struct stm32l4_lowerhalf_s *)lower; + struct stm32_lowerhalf_s *priv = + (struct stm32_lowerhalf_s *)lower; uint16_t dier; uint32_t smcr; uint32_t ccmr1; @@ -690,7 +690,7 @@ static int stm32l4_setup(struct qe_lowerhalf_s *lower) /* Timer base configuration */ - cr1 = stm32l4_getreg16(priv, STM32L4_GTIM_CR1_OFFSET); + cr1 = stm32_getreg16(priv, STM32_GTIM_CR1_OFFSET); /* Clear the direction bit (0=count up) and select the Counter Mode * (0=Edge aligned) @@ -698,23 +698,23 @@ static int stm32l4_setup(struct qe_lowerhalf_s *lower) */ cr1 &= ~(GTIM_CR1_DIR | GTIM_CR1_CMS_MASK); - stm32l4_putreg16(priv, STM32L4_GTIM_CR1_OFFSET, cr1); + stm32_putreg16(priv, STM32_GTIM_CR1_OFFSET, cr1); /* Set the Autoreload value */ #if defined(HAVE_MIXEDWIDTH_TIMERS) if (priv->config->width == 32) { - stm32l4_putreg32(priv, STM32L4_GTIM_ARR_OFFSET, 0xffffffff); + stm32_putreg32(priv, STM32_GTIM_ARR_OFFSET, 0xffffffff); } else { - stm32l4_putreg16(priv, STM32L4_GTIM_ARR_OFFSET, 0xffff); + stm32_putreg16(priv, STM32_GTIM_ARR_OFFSET, 0xffff); } #elif defined(HAVE_32BIT_TIMERS) - stm32l4_putreg32(priv, STM32L4_GTIM_ARR_OFFSET, 0xffffffff); + stm32_putreg32(priv, STM32_GTIM_ARR_OFFSET, 0xffffffff); #else - stm32l4_putreg16(priv, STM32L4_GTIM_ARR_OFFSET, 0xffff); + stm32_putreg16(priv, STM32_GTIM_ARR_OFFSET, 0xffff); #endif /* Set the timer prescaler value. @@ -736,15 +736,15 @@ static int stm32l4_setup(struct qe_lowerhalf_s *lower) * on the encoder resolution. */ - stm32l4_putreg16(priv, - STM32L4_GTIM_PSC_OFFSET, (uint16_t)priv->config->psc); + stm32_putreg16(priv, + STM32_GTIM_PSC_OFFSET, (uint16_t)priv->config->psc); -#if defined(CONFIG_STM32L4_TIM1_QE) || defined(CONFIG_STM32L4_TIM8_QE) +#if defined(CONFIG_STM32_TIM1_QE) || defined(CONFIG_STM32_TIM8_QE) if (priv->config->timid == 1 || priv->config->timid == 8) { /* Clear the Repetition Counter value */ - stm32l4_putreg16(priv, STM32L4_ATIM_RCR_OFFSET, 0); + stm32_putreg16(priv, STM32_ATIM_RCR_OFFSET, 0); } #endif @@ -752,36 +752,36 @@ static int stm32l4_setup(struct qe_lowerhalf_s *lower) * and the repetition counter (only for TIM1 and TIM8) value immediately */ - stm32l4_putreg16(priv, STM32L4_GTIM_EGR_OFFSET, GTIM_EGR_UG); + stm32_putreg16(priv, STM32_GTIM_EGR_OFFSET, GTIM_EGR_UG); /* GPIO pin configuration */ - stm32l4_configgpio(priv->config->ti1cfg); - stm32l4_configgpio(priv->config->ti2cfg); + stm32_configgpio(priv->config->ti1cfg); + stm32_configgpio(priv->config->ti2cfg); /* Set the encoder Mode 3 */ - smcr = stm32l4_getreg32(priv, STM32L4_GTIM_SMCR_OFFSET); + smcr = stm32_getreg32(priv, STM32_GTIM_SMCR_OFFSET); smcr &= ~GTIM_SMCR_SMS_MASK; smcr |= GTIM_SMCR_ENCMD3; - stm32l4_putreg32(priv, STM32L4_GTIM_SMCR_OFFSET, smcr); + stm32_putreg32(priv, STM32_GTIM_SMCR_OFFSET, smcr); /* TI1 Channel Configuration */ /* Disable the Channel 1: Reset the CC1E Bit */ - ccer = stm32l4_getreg16(priv, STM32L4_GTIM_CCER_OFFSET); + ccer = stm32_getreg16(priv, STM32_GTIM_CCER_OFFSET); ccer &= ~GTIM_CCER_CC1E; - stm32l4_putreg16(priv, STM32L4_GTIM_CCER_OFFSET, ccer); + stm32_putreg16(priv, STM32_GTIM_CCER_OFFSET, ccer); - ccmr1 = stm32l4_getreg32(priv, STM32L4_GTIM_CCMR1_OFFSET); - ccer = stm32l4_getreg16(priv, STM32L4_GTIM_CCER_OFFSET); + ccmr1 = stm32_getreg32(priv, STM32_GTIM_CCMR1_OFFSET); + ccer = stm32_getreg16(priv, STM32_GTIM_CCER_OFFSET); /* Select the Input IC1=TI1 and set the filter fSAMPLING=fDTS/4, N=6 */ ccmr1 &= ~(GTIM_CCMR1_CC1S_MASK | GTIM_CCMR1_IC1F_MASK); ccmr1 |= GTIM_CCMR_CCS_CCIN1 << GTIM_CCMR1_CC1S_SHIFT; - ccmr1 |= STM32L4_QENCODER_ICF << GTIM_CCMR1_IC1F_SHIFT; + ccmr1 |= STM32_QENCODER_ICF << GTIM_CCMR1_IC1F_SHIFT; /* Select the Polarity=rising and set the CC1E Bit */ @@ -790,34 +790,34 @@ static int stm32l4_setup(struct qe_lowerhalf_s *lower) /* Write to TIM CCMR1 and CCER registers */ - stm32l4_putreg32(priv, STM32L4_GTIM_CCMR1_OFFSET, ccmr1); - stm32l4_putreg16(priv, STM32L4_GTIM_CCER_OFFSET, ccer); + stm32_putreg32(priv, STM32_GTIM_CCMR1_OFFSET, ccmr1); + stm32_putreg16(priv, STM32_GTIM_CCER_OFFSET, ccer); /* Set the Input Capture Prescaler value: Capture performed each time an * edge is detected on the capture input. */ - ccmr1 = stm32l4_getreg32(priv, STM32L4_GTIM_CCMR1_OFFSET); + ccmr1 = stm32_getreg32(priv, STM32_GTIM_CCMR1_OFFSET); ccmr1 &= ~GTIM_CCMR1_IC1PSC_MASK; ccmr1 |= (GTIM_CCMR_ICPSC_NOPSC << GTIM_CCMR1_IC1PSC_SHIFT); - stm32l4_putreg32(priv, STM32L4_GTIM_CCMR1_OFFSET, ccmr1); + stm32_putreg32(priv, STM32_GTIM_CCMR1_OFFSET, ccmr1); /* TI2 Channel Configuration */ /* Disable the Channel 2: Reset the CC2E Bit */ - ccer = stm32l4_getreg16(priv, STM32L4_GTIM_CCER_OFFSET); + ccer = stm32_getreg16(priv, STM32_GTIM_CCER_OFFSET); ccer &= ~GTIM_CCER_CC2E; - stm32l4_putreg16(priv, STM32L4_GTIM_CCER_OFFSET, ccer); + stm32_putreg16(priv, STM32_GTIM_CCER_OFFSET, ccer); - ccmr1 = stm32l4_getreg32(priv, STM32L4_GTIM_CCMR1_OFFSET); - ccer = stm32l4_getreg16(priv, STM32L4_GTIM_CCER_OFFSET); + ccmr1 = stm32_getreg32(priv, STM32_GTIM_CCMR1_OFFSET); + ccer = stm32_getreg16(priv, STM32_GTIM_CCER_OFFSET); /* Select the Input IC2=TI2 and set the filter fSAMPLING=fDTS/4, N=6 */ ccmr1 &= ~(GTIM_CCMR1_CC2S_MASK | GTIM_CCMR1_IC2F_MASK); ccmr1 |= GTIM_CCMR_CCS_CCIN1 << GTIM_CCMR1_CC2S_SHIFT; - ccmr1 |= STM32L4_QENCODER_ICF << GTIM_CCMR1_IC2F_SHIFT; + ccmr1 |= STM32_QENCODER_ICF << GTIM_CCMR1_IC2F_SHIFT; /* Select the Polarity=rising and set the CC2E Bit */ @@ -826,23 +826,23 @@ static int stm32l4_setup(struct qe_lowerhalf_s *lower) /* Write to TIM CCMR1 and CCER registers */ - stm32l4_putreg32(priv, STM32L4_GTIM_CCMR1_OFFSET, ccmr1); - stm32l4_putreg16(priv, STM32L4_GTIM_CCER_OFFSET, ccer); + stm32_putreg32(priv, STM32_GTIM_CCMR1_OFFSET, ccmr1); + stm32_putreg16(priv, STM32_GTIM_CCER_OFFSET, ccer); /* Set the Input Capture Prescaler value: Capture performed each time an * edge is detected on the capture input. */ - ccmr1 = stm32l4_getreg32(priv, STM32L4_GTIM_CCMR1_OFFSET); + ccmr1 = stm32_getreg32(priv, STM32_GTIM_CCMR1_OFFSET); ccmr1 &= ~GTIM_CCMR1_IC2PSC_MASK; ccmr1 |= (GTIM_CCMR_ICPSC_NOPSC << GTIM_CCMR1_IC2PSC_SHIFT); - stm32l4_putreg32(priv, STM32L4_GTIM_CCMR1_OFFSET, ccmr1); + stm32_putreg32(priv, STM32_GTIM_CCMR1_OFFSET, ccmr1); /* Disable the update interrupt */ - dier = stm32l4_getreg16(priv, STM32L4_GTIM_DIER_OFFSET); + dier = stm32_getreg16(priv, STM32_GTIM_DIER_OFFSET); dier &= ~GTIM_DIER_UIE; - stm32l4_putreg16(priv, STM32L4_GTIM_DIER_OFFSET, dier); + stm32_putreg16(priv, STM32_GTIM_DIER_OFFSET, dier); /* There is no need for interrupts with 32-bit timers */ @@ -853,10 +853,10 @@ static int stm32l4_setup(struct qe_lowerhalf_s *lower) { /* Attach the interrupt handler */ - ret = irq_attach(priv->config->irq, stm32l4_interrupt, priv); + ret = irq_attach(priv->config->irq, stm32_interrupt, priv); if (ret < 0) { - stm32l4_shutdown(lower); + stm32_shutdown(lower); return ret; } @@ -868,14 +868,14 @@ static int stm32l4_setup(struct qe_lowerhalf_s *lower) /* Reset the Update Disable Bit */ - cr1 = stm32l4_getreg16(priv, STM32L4_GTIM_CR1_OFFSET); + cr1 = stm32_getreg16(priv, STM32_GTIM_CR1_OFFSET); cr1 &= ~GTIM_CR1_UDIS; - stm32l4_putreg16(priv, STM32L4_GTIM_CR1_OFFSET, cr1); + stm32_putreg16(priv, STM32_GTIM_CR1_OFFSET, cr1); /* Reset the URS Bit */ cr1 &= ~GTIM_CR1_URS; - stm32l4_putreg16(priv, STM32L4_GTIM_CR1_OFFSET, cr1); + stm32_putreg16(priv, STM32_GTIM_CR1_OFFSET, cr1); /* There is no need for interrupts with 32-bit timers */ @@ -886,30 +886,30 @@ static int stm32l4_setup(struct qe_lowerhalf_s *lower) { /* Clear any pending update interrupts */ - regval = stm32l4_getreg16(priv, STM32L4_GTIM_SR_OFFSET); - stm32l4_putreg16(priv, STM32L4_GTIM_SR_OFFSET, regval & ~GTIM_SR_UIF); + regval = stm32_getreg16(priv, STM32_GTIM_SR_OFFSET); + stm32_putreg16(priv, STM32_GTIM_SR_OFFSET, regval & ~GTIM_SR_UIF); /* Then enable the update interrupt */ - dier = stm32l4_getreg16(priv, STM32L4_GTIM_DIER_OFFSET); + dier = stm32_getreg16(priv, STM32_GTIM_DIER_OFFSET); dier |= GTIM_DIER_UIE; - stm32l4_putreg16(priv, STM32L4_GTIM_DIER_OFFSET, dier); + stm32_putreg16(priv, STM32_GTIM_DIER_OFFSET, dier); } #endif /* Enable the TIM Counter */ - cr1 = stm32l4_getreg16(priv, STM32L4_GTIM_CR1_OFFSET); + cr1 = stm32_getreg16(priv, STM32_GTIM_CR1_OFFSET); cr1 |= GTIM_CR1_CEN; - stm32l4_putreg16(priv, STM32L4_GTIM_CR1_OFFSET, cr1); + stm32_putreg16(priv, STM32_GTIM_CR1_OFFSET, cr1); - stm32l4_dumpregs(priv, "After setup"); + stm32_dumpregs(priv, "After setup"); return OK; } /**************************************************************************** - * Name: stm32l4_shutdown + * Name: stm32_shutdown * * Description: * This method is called when the driver is closed. The lower half driver @@ -918,10 +918,10 @@ static int stm32l4_setup(struct qe_lowerhalf_s *lower) * ****************************************************************************/ -static int stm32l4_shutdown(struct qe_lowerhalf_s *lower) +static int stm32_shutdown(struct qe_lowerhalf_s *lower) { - struct stm32l4_lowerhalf_s *priv = - (struct stm32l4_lowerhalf_s *)lower; + struct stm32_lowerhalf_s *priv = + (struct stm32_lowerhalf_s *)lower; irqstate_t flags; uint32_t regaddr; uint32_t regval; @@ -943,46 +943,46 @@ static int stm32l4_shutdown(struct qe_lowerhalf_s *lower) /* Disable further interrupts and stop the timer */ - stm32l4_putreg16(priv, STM32L4_GTIM_DIER_OFFSET, 0); - stm32l4_putreg16(priv, STM32L4_GTIM_SR_OFFSET, 0); + stm32_putreg16(priv, STM32_GTIM_DIER_OFFSET, 0); + stm32_putreg16(priv, STM32_GTIM_SR_OFFSET, 0); /* Determine which timer to reset */ switch (priv->config->timid) { -#ifdef CONFIG_STM32L4_TIM1_QE +#ifdef CONFIG_STM32_TIM1_QE case 1: - regaddr = STM32L4_RCC_APB2RSTR; + regaddr = STM32_RCC_APB2RSTR; resetbit = RCC_APB2RSTR_TIM1RST; break; #endif -#ifdef CONFIG_STM32L4_TIM2_QE +#ifdef CONFIG_STM32_TIM2_QE case 2: - regaddr = STM32L4_RCC_APB1RSTR1; + regaddr = STM32_RCC_APB1RSTR1; resetbit = RCC_APB1RSTR1_TIM2RST; break; #endif -#ifdef CONFIG_STM32L4_TIM3_QE +#ifdef CONFIG_STM32_TIM3_QE case 3: - regaddr = STM32L4_RCC_APB1RSTR1; + regaddr = STM32_RCC_APB1RSTR1; resetbit = RCC_APB1RSTR1_TIM3RST; break; #endif -#ifdef CONFIG_STM32L4_TIM4_QE +#ifdef CONFIG_STM32_TIM4_QE case 4: - regaddr = STM32L4_RCC_APB1RSTR1; + regaddr = STM32_RCC_APB1RSTR1; resetbit = RCC_APB1RSTR1_TIM4RST; break; #endif -#ifdef CONFIG_STM32L4_TIM5_QE +#ifdef CONFIG_STM32_TIM5_QE case 5: - regaddr = STM32L4_RCC_APB1RSTR1; + regaddr = STM32_RCC_APB1RSTR1; resetbit = RCC_APB1RSTR1_TIM5RST; break; #endif -#ifdef CONFIG_STM32L4_TIM8_QE +#ifdef CONFIG_STM32_TIM8_QE case 8: - regaddr = STM32L4_RCC_APB2RSTR; + regaddr = STM32_RCC_APB2RSTR; resetbit = RCC_APB2RSTR_TIM8RST; break; #endif @@ -992,7 +992,7 @@ static int stm32l4_shutdown(struct qe_lowerhalf_s *lower) } /* Reset the timer - stopping the output and putting the timer back - * into a state where stm32l4_start() can be called. + * into a state where stm32_start() can be called. */ regval = getreg32(regaddr); @@ -1005,37 +1005,37 @@ static int stm32l4_shutdown(struct qe_lowerhalf_s *lower) sninfo("regaddr: %08" PRIx32 " resetbit: %08" PRIx32 "\n", regaddr, resetbit); - stm32l4_dumpregs(priv, "After stop"); + stm32_dumpregs(priv, "After stop"); /* Put the TI1 GPIO pin back to its default state */ pincfg = priv->config->ti1cfg & (GPIO_PORT_MASK | GPIO_PIN_MASK); - pincfg |= STM32L4_GPIO_INPUT_FLOAT; + pincfg |= STM32_GPIO_INPUT_FLOAT; - stm32l4_configgpio(pincfg); + stm32_configgpio(pincfg); /* Put the TI2 GPIO pin back to its default state */ pincfg = priv->config->ti2cfg & (GPIO_PORT_MASK | GPIO_PIN_MASK); - pincfg |= STM32L4_GPIO_INPUT_FLOAT; + pincfg |= STM32_GPIO_INPUT_FLOAT; - stm32l4_configgpio(pincfg); + stm32_configgpio(pincfg); return OK; } /**************************************************************************** - * Name: stm32l4_position + * Name: stm32_position * * Description: * Return the current position measurement. * ****************************************************************************/ -static int stm32l4_position(struct qe_lowerhalf_s *lower, +static int stm32_position(struct qe_lowerhalf_s *lower, int32_t *pos) { - struct stm32l4_lowerhalf_s *priv = - (struct stm32l4_lowerhalf_s *)lower; + struct stm32_lowerhalf_s *priv = + (struct stm32_lowerhalf_s *)lower; #ifdef HAVE_16BIT_TIMERS irqstate_t flags; int32_t position; @@ -1050,7 +1050,7 @@ static int stm32l4_position(struct qe_lowerhalf_s *lower, do { position = priv->position; - count = stm32l4_getreg32(priv, STM32L4_GTIM_CNT_OFFSET); + count = stm32_getreg32(priv, STM32_GTIM_CNT_OFFSET); verify = priv->position; } while (position != verify); @@ -1062,23 +1062,23 @@ static int stm32l4_position(struct qe_lowerhalf_s *lower, #else /* Return the counter value */ - *pos = (int32_t)stm32l4_getreg32(priv, STM32L4_GTIM_CNT_OFFSET); + *pos = (int32_t)stm32_getreg32(priv, STM32_GTIM_CNT_OFFSET); #endif return OK; } /**************************************************************************** - * Name: stm32l4_reset + * Name: stm32_reset * * Description: * Reset the position measurement to zero. * ****************************************************************************/ -static int stm32l4_reset(struct qe_lowerhalf_s *lower) +static int stm32_reset(struct qe_lowerhalf_s *lower) { - struct stm32l4_lowerhalf_s *priv = - (struct stm32l4_lowerhalf_s *)lower; + struct stm32_lowerhalf_s *priv = + (struct stm32_lowerhalf_s *)lower; #ifdef HAVE_16BIT_TIMERS irqstate_t flags; @@ -1090,7 +1090,7 @@ static int stm32l4_reset(struct qe_lowerhalf_s *lower) */ flags = spin_lock_irqsave(&priv->lock); - stm32l4_putreg32(priv, STM32L4_GTIM_CNT_OFFSET, 0); + stm32_putreg32(priv, STM32_GTIM_CNT_OFFSET, 0); priv->position = 0; spin_unlock_irqrestore(&priv->lock, flags); #else @@ -1099,20 +1099,20 @@ static int stm32l4_reset(struct qe_lowerhalf_s *lower) /* Reset the counter to zero */ - stm32l4_putreg32(priv, STM32L4_GTIM_CNT_OFFSET, 0); + stm32_putreg32(priv, STM32_GTIM_CNT_OFFSET, 0); #endif return OK; } /**************************************************************************** - * Name: stm32l4_ioctl + * Name: stm32_ioctl * * Description: * Lower-half logic may support platform-specific ioctl commands * ****************************************************************************/ -static int stm32l4_ioctl(struct qe_lowerhalf_s *lower, +static int stm32_ioctl(struct qe_lowerhalf_s *lower, int cmd, unsigned long arg) { /* No ioctl commands supported */ @@ -1127,7 +1127,7 @@ static int stm32l4_ioctl(struct qe_lowerhalf_s *lower, ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_qeinitialize + * Name: stm32_qeinitialize * * Description: * Initialize a quadrature encoder interface. @@ -1143,16 +1143,16 @@ static int stm32l4_ioctl(struct qe_lowerhalf_s *lower, * ****************************************************************************/ -int stm32l4_qeinitialize(const char *devpath, int tim) +int stm32_qeinitialize(const char *devpath, int tim) { - struct stm32l4_lowerhalf_s *priv; + struct stm32_lowerhalf_s *priv; int ret; /* Find the pre-allocated timer state structure corresponding to this * timer */ - priv = stm32l4_tim2lower(tim); + priv = stm32_tim2lower(tim); if (!priv) { snerr("ERROR: TIM%d support not configured\n", tim); @@ -1178,7 +1178,7 @@ int stm32l4_qeinitialize(const char *devpath, int tim) /* Make sure that the timer is in the shutdown state */ - stm32l4_shutdown((struct qe_lowerhalf_s *)priv); + stm32_shutdown((struct qe_lowerhalf_s *)priv); /* The driver is now in-use */ diff --git a/arch/arm/src/stm32l4/stm32l4_qencoder.h b/arch/arm/src/stm32l4/stm32l4_qencoder.h index 9d88bdb8323c9..1197bdfc67acc 100644 --- a/arch/arm/src/stm32l4/stm32l4_qencoder.h +++ b/arch/arm/src/stm32l4/stm32l4_qencoder.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32L4_STM32L4_QENCODER_H -#define __ARCH_ARM_SRC_STM32L4_STM32L4_QENCODER_H +#ifndef __ARCH_ARM_SRC_STM32L4_STM32_QENCODER_H +#define __ARCH_ARM_SRC_STM32L4_STM32_QENCODER_H /**************************************************************************** * Included Files @@ -38,48 +38,48 @@ ****************************************************************************/ /* Timer devices may be used for different purposes. One special purpose is - * as a quadrature encoder input device. If CONFIG_STM32L4_TIMn is defined - * then the CONFIG_STM32L4_TIMn_QE must also be defined to indicate that + * as a quadrature encoder input device. If CONFIG_STM32_TIMn is defined + * then the CONFIG_STM32_TIMn_QE must also be defined to indicate that * timer "n" is intended to be used for as a quadrature encoder. */ -#ifndef CONFIG_STM32L4_TIM1 -# undef CONFIG_STM32L4_TIM1_QE +#ifndef CONFIG_STM32_TIM1 +# undef CONFIG_STM32_TIM1_QE #endif -#ifndef CONFIG_STM32L4_TIM2 -# undef CONFIG_STM32L4_TIM2_QE +#ifndef CONFIG_STM32_TIM2 +# undef CONFIG_STM32_TIM2_QE #endif -#ifndef CONFIG_STM32L4_TIM3 -# undef CONFIG_STM32L4_TIM3_QE +#ifndef CONFIG_STM32_TIM3 +# undef CONFIG_STM32_TIM3_QE #endif -#ifndef CONFIG_STM32L4_TIM4 -# undef CONFIG_STM32L4_TIM4_QE +#ifndef CONFIG_STM32_TIM4 +# undef CONFIG_STM32_TIM4_QE #endif -#ifndef CONFIG_STM32L4_TIM5 -# undef CONFIG_STM32L4_TIM5_QE +#ifndef CONFIG_STM32_TIM5 +# undef CONFIG_STM32_TIM5_QE #endif -#ifndef CONFIG_STM32L4_TIM8 -# undef CONFIG_STM32L4_TIM8_QE +#ifndef CONFIG_STM32_TIM8 +# undef CONFIG_STM32_TIM8_QE #endif /* Only timers 2-5, and 1 & 8 can be used as a quadrature encoder */ -#undef CONFIG_STM32L4_TIM6_QE -#undef CONFIG_STM32L4_TIM7_QE -#undef CONFIG_STM32L4_TIM9_QE -#undef CONFIG_STM32L4_TIM10_QE -#undef CONFIG_STM32L4_TIM11_QE -#undef CONFIG_STM32L4_TIM12_QE -#undef CONFIG_STM32L4_TIM13_QE -#undef CONFIG_STM32L4_TIM14_QE +#undef CONFIG_STM32_TIM6_QE +#undef CONFIG_STM32_TIM7_QE +#undef CONFIG_STM32_TIM9_QE +#undef CONFIG_STM32_TIM10_QE +#undef CONFIG_STM32_TIM11_QE +#undef CONFIG_STM32_TIM12_QE +#undef CONFIG_STM32_TIM13_QE +#undef CONFIG_STM32_TIM14_QE /**************************************************************************** * Included Files ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_qeinitialize + * Name: stm32_qeinitialize * * Description: * Initialize a quadrature encoder interface. @@ -95,7 +95,7 @@ * ****************************************************************************/ -int stm32l4_qeinitialize(const char *devpath, int tim); +int stm32_qeinitialize(const char *devpath, int tim); #endif /* CONFIG_SENSORS_QENCODER */ -#endif /* __ARCH_ARM_SRC_STM32L4_STM32L4_QENCODER_H */ +#endif /* __ARCH_ARM_SRC_STM32L4_STM32_QENCODER_H */ diff --git a/arch/arm/src/stm32l4/stm32l4_qspi.c b/arch/arm/src/stm32l4/stm32l4_qspi.c index 954f8b460cec1..5c5f29eeb08d3 100644 --- a/arch/arm/src/stm32l4/stm32l4_qspi.c +++ b/arch/arm/src/stm32l4/stm32l4_qspi.c @@ -56,7 +56,7 @@ #include "hardware/stm32l4_qspi.h" #include "hardware/stm32l4_pinmap.h" -#ifdef CONFIG_STM32L4_QSPI +#ifdef CONFIG_STM32_QSPI /**************************************************************************** * Pre-processor Definitions @@ -67,7 +67,7 @@ /* Check if QSPI debug is enabled */ #ifndef CONFIG_DEBUG_DMA -# undef CONFIG_STM32L4_QSPI_DMADEBUG +# undef CONFIG_STM32_QSPI_DMADEBUG #endif #define DMA_INITIAL 0 @@ -80,7 +80,7 @@ /* Can't have both interrupt-driven QSPI and DMA QSPI */ -#if defined(STM32L4_QSPI_INTERRUPTS) && defined(CONFIG_STM32L4_QSPI_DMA) +#if defined(STM32_QSPI_INTERRUPTS) && defined(CONFIG_STM32_QSPI_DMA) # error "Cannot enable both interrupt mode and DMA mode for QSPI" #endif @@ -92,23 +92,23 @@ GPIO_QSPI_IO1 GPIO_QSPI_IO2 GPIO_QSPI_IO3 GPIO_QSPI_SCK in your board.h #endif -#ifdef CONFIG_STM32L4_QSPI_DMA +#ifdef CONFIG_STM32_QSPI_DMA -# if defined(CONFIG_STM32L4_QSPI_DMA_CHAN_1_5) +# if defined(CONFIG_STM32_QSPI_DMA_CHAN_1_5) # define DMACHAN_QUADSPI DMACHAN_QUADSPI_1 -# elif defined(CONFIG_STM32L4_QSPI_DMA_CHAN_2_7) +# elif defined(CONFIG_STM32_QSPI_DMA_CHAN_2_7) # define DMACHAN_QUADSPI DMACHAN_QUADSPI_2 # else # error QSPI DMA channel must be specified via DMACHAN_QUADSPI in your board.h # endif -# if defined(CONFIG_STM32L4_QSPI_DMAPRIORITY_LOW) +# if defined(CONFIG_STM32_QSPI_DMAPRIORITY_LOW) # define QSPI_DMA_PRIO DMA_CCR_PRILO -# elif defined(CONFIG_STM32L4_QSPI_DMAPRIORITY_MEDIUM) +# elif defined(CONFIG_STM32_QSPI_DMAPRIORITY_MEDIUM) # define QSPI_DMA_PRIO DMA_CCR_PRIMED -# elif defined(CONFIG_STM32L4_QSPI_DMAPRIORITY_HIGH) +# elif defined(CONFIG_STM32_QSPI_DMAPRIORITY_HIGH) # define QSPI_DMA_PRIO DMA_CCR_PRIHI -# elif defined(CONFIG_STM32L4_QSPI_DMAPRIORITY_VERYHIGH) +# elif defined(CONFIG_STM32_QSPI_DMAPRIORITY_VERYHIGH) # define QSPI_DMA_PRIO DMA_CCR_PRIVERYHI # else # define QSPI_DMA_PRIO DMA_CCR_PRIMED @@ -120,8 +120,8 @@ # error your board.h needs to define the value of BOARD_AHB_FREQUENCY #endif -#if !defined(CONFIG_STM32L4_QSPI_FLASH_SIZE) || 0 == CONFIG_STM32L4_QSPI_FLASH_SIZE -# error you must specify a positive flash size via CONFIG_STM32L4_QSPI_FLASH_SIZE +#if !defined(CONFIG_STM32_QSPI_FLASH_SIZE) || 0 == CONFIG_STM32_QSPI_FLASH_SIZE +# error you must specify a positive flash size via CONFIG_STM32_QSPI_FLASH_SIZE #endif /* DMA timeout. The value is not critical; we just don't want the system to @@ -149,7 +149,7 @@ * designed to support multiple QSPI peripherals. */ -struct stm32l4_qspidev_s +struct stm32_qspidev_s { struct qspi_dev_s qspi; /* Externally visible part of the QSPI interface */ uint32_t base; /* QSPI controller register base address */ @@ -162,14 +162,14 @@ struct stm32l4_qspidev_s mutex_t lock; /* Assures mutually exclusive access to QSPI */ bool memmap; /* TRUE: Controller is in memory mapped mode */ -#ifdef STM32L4_QSPI_INTERRUPTS +#ifdef STM32_QSPI_INTERRUPTS xcpt_t handler; /* Interrupt handler */ uint8_t irq; /* Interrupt number */ sem_t op_sem; /* Block until complete */ struct qspi_xctnspec_s *xctn; /* context of transaction in progress */ #endif -#ifdef CONFIG_STM32L4_QSPI_DMA +#ifdef CONFIG_STM32_QSPI_DMA bool candma; /* DMA is supported */ sem_t dmawait; /* Used to wait for DMA completion */ int result; /* DMA result */ @@ -179,11 +179,11 @@ struct stm32l4_qspidev_s /* Debug stuff */ -#ifdef CONFIG_STM32L4_QSPI_DMADEBUG - struct stm32l4_dmaregs_s dmaregs[DMA_NSAMPLES]; +#ifdef CONFIG_STM32_QSPI_DMADEBUG + struct stm32_dmaregs_s dmaregs[DMA_NSAMPLES]; #endif -#ifdef CONFIG_STM32L4_QSPI_REGDEBUG +#ifdef CONFIG_STM32_QSPI_REGDEBUG bool wrlast; /* Last was a write */ uint32_t addresslast; /* Last address */ uint32_t valuelast; /* Last value */ @@ -220,7 +220,7 @@ struct qspi_xctnspec_s uint8_t isddr; /* true if 'double data rate' */ uint8_t issioo; /* true if 'send instruction only once' mode */ -#ifdef STM32L4_QSPI_INTERRUPTS +#ifdef STM32_QSPI_INTERRUPTS uint8_t function; /* functional mode; to distinguish a read or write */ int8_t disposition; /* how it all turned out */ uint32_t idxnow; /* index into databuffer of current byte in transfer */ @@ -233,20 +233,20 @@ struct qspi_xctnspec_s /* Helpers */ -#ifdef CONFIG_STM32L4_QSPI_REGDEBUG -static bool qspi_checkreg(struct stm32l4_qspidev_s *priv, bool wr, +#ifdef CONFIG_STM32_QSPI_REGDEBUG +static bool qspi_checkreg(struct stm32_qspidev_s *priv, bool wr, uint32_t value, uint32_t address); #else # define qspi_checkreg(priv,wr,value,address) (false) #endif -static inline uint32_t qspi_getreg(struct stm32l4_qspidev_s *priv, +static inline uint32_t qspi_getreg(struct stm32_qspidev_s *priv, unsigned int offset); -static inline void qspi_putreg(struct stm32l4_qspidev_s *priv, +static inline void qspi_putreg(struct stm32_qspidev_s *priv, uint32_t value, unsigned int offset); #ifdef CONFIG_DEBUG_SPI_INFO -static void qspi_dumpregs(struct stm32l4_qspidev_s *priv, +static void qspi_dumpregs(struct stm32_qspidev_s *priv, const char *msg); #else # define qspi_dumpregs(priv,msg) @@ -260,27 +260,27 @@ static void qspi_dumpgpioconfig(const char *msg); /* Interrupts */ -#ifdef STM32L4_QSPI_INTERRUPTS +#ifdef STM32_QSPI_INTERRUPTS static int qspi0_interrupt(int irq, void *context, void *arg); #endif /* DMA support */ -#ifdef CONFIG_STM32L4_QSPI_DMA +#ifdef CONFIG_STM32_QSPI_DMA -# ifdef CONFIG_STM32L4_QSPI_DMADEBUG -# define qspi_dma_sample(s,i) stm32l4_dmasample((s)->dmach, &(s)->dmaregs[i]) -static void qspi_dma_sampleinit(struct stm32l4_qspidev_s *priv); -static void qspi_dma_sampledone(struct stm32l4_qspidev_s *priv); +# ifdef CONFIG_STM32_QSPI_DMADEBUG +# define qspi_dma_sample(s,i) stm32_dmasample((s)->dmach, &(s)->dmaregs[i]) +static void qspi_dma_sampleinit(struct stm32_qspidev_s *priv); +static void qspi_dma_sampledone(struct stm32_qspidev_s *priv); # else # define qspi_dma_sample(s,i) # define qspi_dma_sampleinit(s) # define qspi_dma_sampledone(s) # endif -# ifndef CONFIG_STM32L4_QSPI_DMATHRESHOLD -# define CONFIG_STM32L4_QSPI_DMATHRESHOLD 4 +# ifndef CONFIG_STM32_QSPI_DMATHRESHOLD +# define CONFIG_STM32_QSPI_DMATHRESHOLD 4 # endif #endif @@ -301,7 +301,7 @@ static void qspi_free(struct qspi_dev_s *dev, void *buffer); /* Initialization */ -static int qspi_hw_initialize(struct stm32l4_qspidev_s *priv); +static int qspi_hw_initialize(struct stm32_qspidev_s *priv); /**************************************************************************** * Private Data @@ -326,21 +326,21 @@ static const struct qspi_ops_s g_qspi0ops = /* This is the overall state of the QSPI0 controller */ -static struct stm32l4_qspidev_s g_qspi0dev = +static struct stm32_qspidev_s g_qspi0dev = { .qspi = { .ops = &g_qspi0ops, }, - .base = STM32L4_QSPI_BASE, + .base = STM32_QSPI_BASE, .lock = NXMUTEX_INITIALIZER, -#ifdef STM32L4_QSPI_INTERRUPTS +#ifdef STM32_QSPI_INTERRUPTS .handler = qspi0_interrupt, - .irq = STM32L4_IRQ_QUADSPI, + .irq = STM32_IRQ_QUADSPI, .op_sem = SEM_INITIALIZER(0), #endif .intf = 0, -#ifdef CONFIG_STM32L4_QSPI_DMA +#ifdef CONFIG_STM32_QSPI_DMA .candma = true, .dmawait = SEM_INITIALIZER(0), #endif @@ -366,8 +366,8 @@ static struct stm32l4_qspidev_s g_qspi0dev = * ****************************************************************************/ -#ifdef CONFIG_STM32L4_QSPI_REGDEBUG -static bool qspi_checkreg(struct stm32l4_qspidev_s *priv, bool wr, +#ifdef CONFIG_STM32_QSPI_REGDEBUG +static bool qspi_checkreg(struct stm32_qspidev_s *priv, bool wr, uint32_t value, uint32_t address) { if (wr == priv->wrlast && /* Same kind of access? */ @@ -412,13 +412,13 @@ static bool qspi_checkreg(struct stm32l4_qspidev_s *priv, bool wr, * ****************************************************************************/ -static inline uint32_t qspi_getreg(struct stm32l4_qspidev_s *priv, +static inline uint32_t qspi_getreg(struct stm32_qspidev_s *priv, unsigned int offset) { uint32_t address = priv->base + offset; uint32_t value = getreg32(address); -#ifdef CONFIG_STM32L4_QSPI_REGDEBUG +#ifdef CONFIG_STM32_QSPI_REGDEBUG if (qspi_checkreg(priv, false, value, address)) { spiinfo("%08" PRIx32 "->%08" PRIx32 "\n", address, value); @@ -436,12 +436,12 @@ static inline uint32_t qspi_getreg(struct stm32l4_qspidev_s *priv, * ****************************************************************************/ -static inline void qspi_putreg(struct stm32l4_qspidev_s *priv, +static inline void qspi_putreg(struct stm32_qspidev_s *priv, uint32_t value, unsigned int offset) { uint32_t address = priv->base + offset; -#ifdef CONFIG_STM32L4_QSPI_REGDEBUG +#ifdef CONFIG_STM32_QSPI_REGDEBUG if (qspi_checkreg(priv, true, value, address)) { spiinfo("%08" PRIx32 "<-%08" PRIx32 "\n", address, value); @@ -467,7 +467,7 @@ static inline void qspi_putreg(struct stm32l4_qspidev_s *priv, ****************************************************************************/ #ifdef CONFIG_DEBUG_SPI_INFO -static void qspi_dumpregs(struct stm32l4_qspidev_s *priv, const char *msg) +static void qspi_dumpregs(struct stm32_qspidev_s *priv, const char *msg) { uint32_t regval; spiinfo("%s:\n", msg); @@ -478,7 +478,7 @@ static void qspi_dumpregs(struct stm32l4_qspidev_s *priv, const char *msg) * output. */ - regval = getreg32(priv->base + STM32L4_QUADSPI_CR_OFFSET); /* Control Register */ + regval = getreg32(priv->base + STM32_QUADSPI_CR_OFFSET); /* Control Register */ spiinfo("CR:%08" PRIx32 "\n", regval); spiinfo(" EN:%1d ABORT:%1d DMAEN:%1d TCEN:%1d SSHIFT:%1d\n" " FTHRES: %d\n" @@ -499,14 +499,14 @@ static void qspi_dumpregs(struct stm32l4_qspidev_s *priv, const char *msg) (regval & QSPI_CR_PMM) ? 1 : 0, (regval & QSPI_CR_PRESCALER_MASK) >> QSPI_CR_PRESCALER_SHIFT); - regval = getreg32(priv->base + STM32L4_QUADSPI_DCR_OFFSET); /* Device Configuration Register */ + regval = getreg32(priv->base + STM32_QUADSPI_DCR_OFFSET); /* Device Configuration Register */ spiinfo("DCR:%08" PRIx32 "\n", regval); spiinfo(" CKMODE:%1d CSHT:%d FSIZE:%d\n", (regval & QSPI_DCR_CKMODE) ? 1 : 0, (regval & QSPI_DCR_CSHT_MASK) >> QSPI_DCR_CSHT_SHIFT, (regval & QSPI_DCR_FSIZE_MASK) >> QSPI_DCR_FSIZE_SHIFT); - regval = getreg32(priv->base + STM32L4_QUADSPI_CCR_OFFSET); /* Communication Configuration Register */ + regval = getreg32(priv->base + STM32_QUADSPI_CCR_OFFSET); /* Communication Configuration Register */ spiinfo("CCR:%08" PRIx32 "\n", regval); spiinfo(" INST:%02x IMODE:%d ADMODE:%d ADSIZE:%d ABMODE:%d\n" " ABSIZE:%d DCYC:%d DMODE:%d FMODE:%d\n" @@ -523,7 +523,7 @@ static void qspi_dumpregs(struct stm32l4_qspidev_s *priv, const char *msg) (regval & QSPI_CCR_SIOO) ? 1 : 0, (regval & QSPI_CCR_DDRM) ? 1 : 0); - regval = getreg32(priv->base + STM32L4_QUADSPI_SR_OFFSET); /* Status Register */ + regval = getreg32(priv->base + STM32_QUADSPI_SR_OFFSET); /* Status Register */ spiinfo("SR:%08" PRIx32 "\n", regval); spiinfo(" TEF:%1d TCF:%1d FTF:%1d SMF:%1d TOF:%1d BUSY:%1d FLEVEL:%d\n", (regval & QSPI_SR_TEF) ? 1 : 0, @@ -537,19 +537,19 @@ static void qspi_dumpregs(struct stm32l4_qspidev_s *priv, const char *msg) #else spiinfo(" CR:%08" PRIx32 " DCR:%08" PRIx32 " CCR:%08" PRIx32 " SR:%08" PRIx32 "\n", - getreg32(priv->base + STM32L4_QUADSPI_CR_OFFSET), /* Control Register */ - getreg32(priv->base + STM32L4_QUADSPI_DCR_OFFSET), /* Device Configuration Register */ - getreg32(priv->base + STM32L4_QUADSPI_CCR_OFFSET), /* Communication Configuration Register */ - getreg32(priv->base + STM32L4_QUADSPI_SR_OFFSET)); /* Status Register */ + getreg32(priv->base + STM32_QUADSPI_CR_OFFSET), /* Control Register */ + getreg32(priv->base + STM32_QUADSPI_DCR_OFFSET), /* Device Configuration Register */ + getreg32(priv->base + STM32_QUADSPI_CCR_OFFSET), /* Communication Configuration Register */ + getreg32(priv->base + STM32_QUADSPI_SR_OFFSET)); /* Status Register */ spiinfo(" DLR:%08" PRIx32 " ABR:%08" PRIx32 " PSMKR:%08" PRIx32 " PSMAR:%08" PRIx32 "\n", - getreg32(priv->base + STM32L4_QUADSPI_DLR_OFFSET), /* Data Length Register */ - getreg32(priv->base + STM32L4_QUADSPI_ABR_OFFSET), /* Alternate Bytes Register */ - getreg32(priv->base + STM32L4_QUADSPI_PSMKR_OFFSET), /* Polling Status mask Register */ - getreg32(priv->base + STM32L4_QUADSPI_PSMAR_OFFSET)); /* Polling Status match Register */ + getreg32(priv->base + STM32_QUADSPI_DLR_OFFSET), /* Data Length Register */ + getreg32(priv->base + STM32_QUADSPI_ABR_OFFSET), /* Alternate Bytes Register */ + getreg32(priv->base + STM32_QUADSPI_PSMKR_OFFSET), /* Polling Status mask Register */ + getreg32(priv->base + STM32_QUADSPI_PSMAR_OFFSET)); /* Polling Status match Register */ spiinfo(" PIR:%08" PRIx32 " LPTR:%08" PRIx32 "\n", - getreg32(priv->base + STM32L4_QUADSPI_PIR_OFFSET), /* Polling Interval Register */ - getreg32(priv->base + STM32L4_QUADSPI_LPTR_OFFSET)); /* Low-Power Timeout Register */ + getreg32(priv->base + STM32_QUADSPI_PIR_OFFSET), /* Polling Interval Register */ + getreg32(priv->base + STM32_QUADSPI_LPTR_OFFSET)); /* Low-Power Timeout Register */ UNUSED(regval); #endif } @@ -561,27 +561,27 @@ static void qspi_dumpgpioconfig(const char *msg) uint32_t regval; spiinfo("%s:\n", msg); - regval = getreg32(STM32L4_GPIOE_MODER); + regval = getreg32(STM32_GPIOE_MODER); spiinfo("E_MODER:%08" PRIx32 "\n", regval); - regval = getreg32(STM32L4_GPIOE_OTYPER); + regval = getreg32(STM32_GPIOE_OTYPER); spiinfo("E_OTYPER:%08" PRIx32 "\n", regval); - regval = getreg32(STM32L4_GPIOE_OSPEED); + regval = getreg32(STM32_GPIOE_OSPEED); spiinfo("E_OSPEED:%08" PRIx32 "\n", regval); - regval = getreg32(STM32L4_GPIOE_PUPDR); + regval = getreg32(STM32_GPIOE_PUPDR); spiinfo("E_PUPDR:%08" PRIx32 "\n", regval); - regval = getreg32(STM32L4_GPIOE_AFRL); + regval = getreg32(STM32_GPIOE_AFRL); spiinfo("E_AFRL:%08" PRIx32 "\n", regval); - regval = getreg32(STM32L4_GPIOE_AFRH); + regval = getreg32(STM32_GPIOE_AFRH); spiinfo("E_AFRH:%08" PRIx32 "\n", regval); } #endif -#ifdef CONFIG_STM32L4_QSPI_DMADEBUG +#ifdef CONFIG_STM32_QSPI_DMADEBUG /**************************************************************************** * Name: qspi_dma_sampleinit * @@ -596,16 +596,16 @@ static void qspi_dumpgpioconfig(const char *msg) * ****************************************************************************/ -static void qspi_dma_sampleinit(struct stm32l4_qspidev_s *priv) +static void qspi_dma_sampleinit(struct stm32_qspidev_s *priv) { /* Put contents of register samples into a known state */ memset(priv->dmaregs, 0xff, - DMA_NSAMPLES * sizeof(struct stm32l4_dmaregs_s)); + DMA_NSAMPLES * sizeof(struct stm32_dmaregs_s)); /* Then get the initial samples */ - stm32l4_dmasample(priv->dmach, &priv->dmaregs[DMA_INITIAL]); + stm32_dmasample(priv->dmach, &priv->dmaregs[DMA_INITIAL]); } /**************************************************************************** @@ -622,27 +622,27 @@ static void qspi_dma_sampleinit(struct stm32l4_qspidev_s *priv) * ****************************************************************************/ -static void qspi_dma_sampledone(struct stm32l4_qspidev_s *priv) +static void qspi_dma_sampledone(struct stm32_qspidev_s *priv) { /* Sample the final registers */ - stm32l4_dmasample(priv->dmach, &priv->dmaregs[DMA_END_TRANSFER]); + stm32_dmasample(priv->dmach, &priv->dmaregs[DMA_END_TRANSFER]); /* Then dump the sampled DMA registers */ /* Initial register values */ - stm32l4_dmadump(priv->dmach, &priv->dmaregs[DMA_INITIAL], + stm32_dmadump(priv->dmach, &priv->dmaregs[DMA_INITIAL], "Initial Registers"); /* Register values after DMA setup */ - stm32l4_dmadump(priv->dmach, &priv->dmaregs[DMA_AFTER_SETUP], + stm32_dmadump(priv->dmach, &priv->dmaregs[DMA_AFTER_SETUP], "After DMA Setup"); /* Register values after DMA start */ - stm32l4_dmadump(priv->dmach, &priv->dmaregs[DMA_AFTER_START], + stm32_dmadump(priv->dmach, &priv->dmaregs[DMA_AFTER_START], "After DMA Start"); /* Register values at the time of the TX and RX DMA callbacks @@ -655,16 +655,16 @@ static void qspi_dma_sampledone(struct stm32l4_qspidev_s *priv) if (priv->result == -ETIMEDOUT) { - stm32l4_dmadump(priv->dmach, &priv->dmaregs[DMA_TIMEOUT], + stm32_dmadump(priv->dmach, &priv->dmaregs[DMA_TIMEOUT], "At DMA timeout"); } else { - stm32l4_dmadump(priv->dmach, &priv->dmaregs[DMA_CALLBACK], + stm32_dmadump(priv->dmach, &priv->dmaregs[DMA_CALLBACK], "At DMA callback"); } - stm32l4_dmadump(priv->dmach, &priv->dmaregs[DMA_END_TRANSFER], + stm32_dmadump(priv->dmach, &priv->dmaregs[DMA_END_TRANSFER], "At End-of-Transfer"); } #endif @@ -787,7 +787,7 @@ static int qspi_setupxctnfromcmd(struct qspi_xctnspec_s *xctn, xctn->isddr = 0; } -#if defined(STM32L4_QSPI_INTERRUPTS) +#if defined(STM32_QSPI_INTERRUPTS) xctn->function = QSPICMD_ISWRITE(cmdinfo->flags) ? CCR_FMODE_INDWR : CCR_FMODE_INDRD; xctn->disposition = - EIO; @@ -918,7 +918,7 @@ static int qspi_setupxctnfrommem(struct qspi_xctnspec_s *xctn, xctn->isddr = 0; -#if defined(STM32L4_QSPI_INTERRUPTS) +#if defined(STM32_QSPI_INTERRUPTS) xctn->function = QSPIMEM_ISWRITE(meminfo->flags) ? CCR_FMODE_INDWR : CCR_FMODE_INDRD; xctn->disposition = - EIO; @@ -944,19 +944,19 @@ static int qspi_setupxctnfrommem(struct qspi_xctnspec_s *xctn, * ****************************************************************************/ -static void qspi_waitstatusflags(struct stm32l4_qspidev_s *priv, +static void qspi_waitstatusflags(struct stm32_qspidev_s *priv, uint32_t mask, int polarity) { uint32_t regval; if (polarity) { - while (!((regval = qspi_getreg(priv, STM32L4_QUADSPI_SR_OFFSET)) + while (!((regval = qspi_getreg(priv, STM32_QUADSPI_SR_OFFSET)) & mask)); } else { - while (((regval = qspi_getreg(priv, STM32L4_QUADSPI_SR_OFFSET)) + while (((regval = qspi_getreg(priv, STM32_QUADSPI_SR_OFFSET)) & mask)); } } @@ -975,13 +975,13 @@ static void qspi_waitstatusflags(struct stm32l4_qspidev_s *priv, * ****************************************************************************/ -static void qspi_abort(struct stm32l4_qspidev_s *priv) +static void qspi_abort(struct stm32_qspidev_s *priv) { uint32_t regval; - regval = qspi_getreg(priv, STM32L4_QUADSPI_CR_OFFSET); + regval = qspi_getreg(priv, STM32_QUADSPI_CR_OFFSET); regval |= QSPI_CR_ABORT; - qspi_putreg(priv, regval, STM32L4_QUADSPI_CR_OFFSET); + qspi_putreg(priv, regval, STM32_QUADSPI_CR_OFFSET); } /**************************************************************************** @@ -1000,7 +1000,7 @@ static void qspi_abort(struct stm32l4_qspidev_s *priv) * ****************************************************************************/ -static void qspi_ccrconfig(struct stm32l4_qspidev_s *priv, +static void qspi_ccrconfig(struct stm32_qspidev_s *priv, struct qspi_xctnspec_s *xctn, uint8_t fctn) { @@ -1010,14 +1010,14 @@ static void qspi_ccrconfig(struct stm32l4_qspidev_s *priv, if (CCR_DMODE_NONE != xctn->datamode && CCR_FMODE_MEMMAP != fctn) { - qspi_putreg(priv, xctn->datasize - 1, STM32L4_QUADSPI_DLR_OFFSET); + qspi_putreg(priv, xctn->datasize - 1, STM32_QUADSPI_DLR_OFFSET); } /* If we have alternate bytes, stick them in now */ if (CCR_ABMODE_NONE != xctn->altbytesmode) { - qspi_putreg(priv, xctn->altbytes, STM32L4_QUADSPI_ABR_OFFSET); + qspi_putreg(priv, xctn->altbytes, STM32_QUADSPI_ABR_OFFSET); } /* Build the CCR value and set it */ @@ -1033,17 +1033,17 @@ static void qspi_ccrconfig(struct stm32l4_qspidev_s *priv, QSPI_CCR_FMODE(fctn) | (xctn->isddr ? QSPI_CCR_SIOO : 0) | (xctn->issioo ? QSPI_CCR_DDRM : 0); - qspi_putreg(priv, regval, STM32L4_QUADSPI_CCR_OFFSET); + qspi_putreg(priv, regval, STM32_QUADSPI_CCR_OFFSET); /* If we have and need and address, set that now, too */ if (CCR_ADMODE_NONE != xctn->addrmode && CCR_FMODE_MEMMAP != fctn) { - qspi_putreg(priv, xctn->addr, STM32L4_QUADSPI_AR_OFFSET); + qspi_putreg(priv, xctn->addr, STM32_QUADSPI_AR_OFFSET); } } -#if defined(STM32L4_QSPI_INTERRUPTS) +#if defined(STM32_QSPI_INTERRUPTS) /**************************************************************************** * Name: qspi0_interrupt * @@ -1068,22 +1068,22 @@ static int qspi0_interrupt(int irq, void *context, void *arg) /* Let's find out what is going on */ - status = qspi_getreg(&g_qspi0dev, STM32L4_QUADSPI_SR_OFFSET); - cr = qspi_getreg(&g_qspi0dev, STM32L4_QUADSPI_CR_OFFSET); + status = qspi_getreg(&g_qspi0dev, STM32_QUADSPI_SR_OFFSET); + cr = qspi_getreg(&g_qspi0dev, STM32_QUADSPI_CR_OFFSET); /* Is it 'FIFO Threshold'? */ if ((status & QSPI_SR_FTF) && (cr & QSPI_CR_FTIE)) { volatile uint32_t *datareg = (volatile uint32_t *) - (g_qspi0dev.base + STM32L4_QUADSPI_DR_OFFSET); + (g_qspi0dev.base + STM32_QUADSPI_DR_OFFSET); if (g_qspi0dev.xctn->function == CCR_FMODE_INDWR) { /* Write data until we have no more or have no place to put it */ while ((regval = qspi_getreg(&g_qspi0dev, - STM32L4_QUADSPI_SR_OFFSET)) + STM32_QUADSPI_SR_OFFSET)) & QSPI_SR_FTF) { if (g_qspi0dev.xctn->idxnow < g_qspi0dev.xctn->datasize) @@ -1105,7 +1105,7 @@ static int qspi0_interrupt(int irq, void *context, void *arg) /* Read data until we have no more or have no place to put it */ while ((regval = qspi_getreg(&g_qspi0dev, - STM32L4_QUADSPI_SR_OFFSET)) + STM32_QUADSPI_SR_OFFSET)) & QSPI_SR_FTF) { if (g_qspi0dev.xctn->idxnow < g_qspi0dev.xctn->datasize) @@ -1131,27 +1131,27 @@ static int qspi0_interrupt(int irq, void *context, void *arg) { /* Acknowledge interrupt */ - qspi_putreg(&g_qspi0dev, QSPI_FCR_CTCF, STM32L4_QUADSPI_FCR); + qspi_putreg(&g_qspi0dev, QSPI_FCR_CTCF, STM32_QUADSPI_FCR); /* Disable the QSPI FIFO Threshold, Transfer Error and Transfer * complete Interrupts */ - regval = qspi_getreg(&g_qspi0dev, STM32L4_QUADSPI_CR_OFFSET); + regval = qspi_getreg(&g_qspi0dev, STM32_QUADSPI_CR_OFFSET); regval &= ~(QSPI_CR_TEIE | QSPI_CR_TCIE | QSPI_CR_FTIE); - qspi_putreg(&g_qspi0dev, regval, STM32L4_QUADSPI_CR_OFFSET); + qspi_putreg(&g_qspi0dev, regval, STM32_QUADSPI_CR_OFFSET); /* Do the last bit of read if needed */ if (g_qspi0dev.xctn->function == CCR_FMODE_INDRD) { volatile uint32_t *datareg = (volatile uint32_t *) - (g_qspi0dev.base + STM32L4_QUADSPI_DR_OFFSET); + (g_qspi0dev.base + STM32_QUADSPI_DR_OFFSET); /* Read any remaining data */ while (((regval = qspi_getreg(&g_qspi0dev, - STM32L4_QUADSPI_SR_OFFSET)) & + STM32_QUADSPI_SR_OFFSET)) & QSPI_SR_FLEVEL_MASK) != 0) { if (g_qspi0dev.xctn->idxnow < g_qspi0dev.xctn->datasize) @@ -1189,7 +1189,7 @@ static int qspi0_interrupt(int irq, void *context, void *arg) { /* Acknowledge interrupt */ - qspi_putreg(&g_qspi0dev, QSPI_FCR_CSMF, STM32L4_QUADSPI_FCR); + qspi_putreg(&g_qspi0dev, QSPI_FCR_CSMF, STM32_QUADSPI_FCR); /* If 'automatic poll mode stop' is activated, we're done */ @@ -1197,9 +1197,9 @@ static int qspi0_interrupt(int irq, void *context, void *arg) { /* Disable the QSPI Transfer Error and Status Match Interrupts */ - regval = qspi_getreg(&g_qspi0dev, STM32L4_QUADSPI_CR_OFFSET); + regval = qspi_getreg(&g_qspi0dev, STM32_QUADSPI_CR_OFFSET); regval &= ~(QSPI_CR_TEIE | QSPI_CR_SMIE); - qspi_putreg(&g_qspi0dev, regval, STM32L4_QUADSPI_CR_OFFSET); + qspi_putreg(&g_qspi0dev, regval, STM32_QUADSPI_CR_OFFSET); /* Set success status */ @@ -1223,14 +1223,14 @@ static int qspi0_interrupt(int irq, void *context, void *arg) { /* Acknowledge interrupt */ - qspi_putreg(&g_qspi0dev, QSPI_FCR_CTEF, STM32L4_QUADSPI_FCR); + qspi_putreg(&g_qspi0dev, QSPI_FCR_CTEF, STM32_QUADSPI_FCR); /* Disable all the QSPI Interrupts */ - regval = qspi_getreg(&g_qspi0dev, STM32L4_QUADSPI_CR_OFFSET); + regval = qspi_getreg(&g_qspi0dev, STM32_QUADSPI_CR_OFFSET); regval &= ~(QSPI_CR_TEIE | QSPI_CR_TCIE | QSPI_CR_FTIE | QSPI_CR_SMIE | QSPI_CR_TOIE); - qspi_putreg(&g_qspi0dev, regval, STM32L4_QUADSPI_CR_OFFSET); + qspi_putreg(&g_qspi0dev, regval, STM32_QUADSPI_CR_OFFSET); /* Set error status; 'transfer error' means that, in 'indirect mode', * an invalid address is attempted to be accessed. 'Invalid' is @@ -1251,7 +1251,7 @@ static int qspi0_interrupt(int irq, void *context, void *arg) { /* Acknowledge interrupt */ - qspi_putreg(&g_qspi0dev, QSPI_FCR_CTOF, STM32L4_QUADSPI_FCR); + qspi_putreg(&g_qspi0dev, QSPI_FCR_CTOF, STM32_QUADSPI_FCR); /* XXX this interrupt simply means that, in 'memory mapped mode', * the QSPI memory has not been accessed for a while, and the @@ -1269,7 +1269,7 @@ static int qspi0_interrupt(int irq, void *context, void *arg) return OK; } -#elif defined(CONFIG_STM32L4_QSPI_DMA) +#elif defined(CONFIG_STM32_QSPI_DMA) /**************************************************************************** * Name: qspi_dma_timeout * @@ -1290,7 +1290,7 @@ static int qspi0_interrupt(int irq, void *context, void *arg) static void qspi_dma_timeout(wdparm_t arg) { - struct stm32l4_qspidev_s *priv = (struct stm32l4_qspidev_s *)arg; + struct stm32_qspidev_s *priv = (struct stm32_qspidev_s *)arg; DEBUGASSERT(priv != NULL); /* Sample DMA registers at the time of the timeout */ @@ -1326,7 +1326,7 @@ static void qspi_dma_timeout(wdparm_t arg) static void qspi_dma_callback(DMA_HANDLE handle, uint8_t isr, void *arg) { - struct stm32l4_qspidev_s *priv = (struct stm32l4_qspidev_s *)arg; + struct stm32_qspidev_s *priv = (struct stm32_qspidev_s *)arg; DEBUGASSERT(priv != NULL); /* Cancel the watchdog timeout */ @@ -1374,7 +1374,7 @@ static void qspi_dma_callback(DMA_HANDLE handle, uint8_t isr, void *arg) * ****************************************************************************/ -static inline uintptr_t qspi_regaddr(struct stm32l4_qspidev_s *priv, +static inline uintptr_t qspi_regaddr(struct stm32_qspidev_s *priv, unsigned int offset) { return priv->base + offset; @@ -1396,7 +1396,7 @@ static inline uintptr_t qspi_regaddr(struct stm32l4_qspidev_s *priv, * ****************************************************************************/ -static int qspi_memory_dma(struct stm32l4_qspidev_s *priv, +static int qspi_memory_dma(struct stm32_qspidev_s *priv, struct qspi_meminfo_s *meminfo, struct qspi_xctnspec_s *xctn) { @@ -1425,17 +1425,17 @@ static int qspi_memory_dma(struct stm32l4_qspidev_s *priv, DMA_CCR_MINC); } - stm32l4_dmasetup(priv->dmach, qspi_regaddr(priv, - STM32L4_QUADSPI_DR_OFFSET), + stm32_dmasetup(priv->dmach, qspi_regaddr(priv, + STM32_QUADSPI_DR_OFFSET), (uint32_t)meminfo->buffer, meminfo->buflen, dmaflags); qspi_dma_sample(priv, DMA_AFTER_SETUP); /* Enable the memory transfer */ - regval = qspi_getreg(priv, STM32L4_QUADSPI_CR_OFFSET); + regval = qspi_getreg(priv, STM32_QUADSPI_CR_OFFSET); regval |= QSPI_CR_DMAEN; - qspi_putreg(priv, regval, STM32L4_QUADSPI_CR_OFFSET); + qspi_putreg(priv, regval, STM32_QUADSPI_CR_OFFSET); /* Set up the Communications Configuration Register as per command info */ @@ -1446,7 +1446,7 @@ static int qspi_memory_dma(struct stm32l4_qspidev_s *priv, /* Start the DMA */ priv->result = -EBUSY; - stm32l4_dmastart(priv->dmach, qspi_dma_callback, priv, false); + stm32_dmastart(priv->dmach, qspi_dma_callback, priv, false); qspi_dma_sample(priv, DMA_AFTER_START); @@ -1481,9 +1481,9 @@ static int qspi_memory_dma(struct stm32l4_qspidev_s *priv, if (ret < 0) { DEBUGPANIC(); - regval = qspi_getreg(priv, STM32L4_QUADSPI_CR_OFFSET); + regval = qspi_getreg(priv, STM32_QUADSPI_CR_OFFSET); regval &= ~QSPI_CR_DMAEN; - qspi_putreg(priv, regval, STM32L4_QUADSPI_CR_OFFSET); + qspi_putreg(priv, regval, STM32_QUADSPI_CR_OFFSET); return ret; } @@ -1510,11 +1510,11 @@ static int qspi_memory_dma(struct stm32l4_qspidev_s *priv, * on an error condition). */ - stm32l4_dmastop(priv->dmach); + stm32_dmastop(priv->dmach); - regval = qspi_getreg(priv, STM32L4_QUADSPI_CR_OFFSET); + regval = qspi_getreg(priv, STM32_QUADSPI_CR_OFFSET); regval &= ~QSPI_CR_DMAEN; - qspi_putreg(priv, regval, STM32L4_QUADSPI_CR_OFFSET); + qspi_putreg(priv, regval, STM32_QUADSPI_CR_OFFSET); /* Complain if the DMA fails */ @@ -1527,7 +1527,7 @@ static int qspi_memory_dma(struct stm32l4_qspidev_s *priv, } #endif -#if !defined(STM32L4_QSPI_INTERRUPTS) +#if !defined(STM32_QSPI_INTERRUPTS) /**************************************************************************** * Name: qspi_receive_blocking * @@ -1543,17 +1543,17 @@ static int qspi_memory_dma(struct stm32l4_qspidev_s *priv, * ****************************************************************************/ -static int qspi_receive_blocking(struct stm32l4_qspidev_s *priv, +static int qspi_receive_blocking(struct stm32_qspidev_s *priv, struct qspi_xctnspec_s *xctn) { int ret = OK; volatile uint32_t *datareg = - (volatile uint32_t *)(priv->base + STM32L4_QUADSPI_DR_OFFSET); + (volatile uint32_t *)(priv->base + STM32_QUADSPI_DR_OFFSET); uint8_t *dest = (uint8_t *)xctn->buffer; uint32_t addrval; uint32_t regval; - addrval = qspi_getreg(priv, STM32L4_QUADSPI_AR_OFFSET); + addrval = qspi_getreg(priv, STM32_QUADSPI_AR_OFFSET); if (dest != NULL) { /* Counter of remaining data */ @@ -1562,14 +1562,14 @@ static int qspi_receive_blocking(struct stm32l4_qspidev_s *priv, /* Ensure CCR register specifies indirect read */ - regval = qspi_getreg(priv, STM32L4_QUADSPI_CCR_OFFSET); + regval = qspi_getreg(priv, STM32_QUADSPI_CCR_OFFSET); regval &= ~QSPI_CCR_FMODE_MASK; regval |= QSPI_CCR_FMODE(CCR_FMODE_INDRD); - qspi_putreg(priv, regval, STM32L4_QUADSPI_CCR_OFFSET); + qspi_putreg(priv, regval, STM32_QUADSPI_CCR_OFFSET); /* Start the transfer by re-writing the address in AR register */ - qspi_putreg(priv, addrval, STM32L4_QUADSPI_AR_OFFSET); + qspi_putreg(priv, addrval, STM32_QUADSPI_AR_OFFSET); /* Transfer loop */ @@ -1589,7 +1589,7 @@ static int qspi_receive_blocking(struct stm32l4_qspidev_s *priv, /* Wait for transfer complete, then clear it */ qspi_waitstatusflags(priv, QSPI_SR_TCF, 1); - qspi_putreg(priv, QSPI_FCR_CTCF, STM32L4_QUADSPI_FCR); + qspi_putreg(priv, QSPI_FCR_CTCF, STM32_QUADSPI_FCR); /* Use Abort to clear the busy flag, and ditch any extra bytes in * fifo @@ -1621,12 +1621,12 @@ static int qspi_receive_blocking(struct stm32l4_qspidev_s *priv, * ****************************************************************************/ -static int qspi_transmit_blocking(struct stm32l4_qspidev_s *priv, +static int qspi_transmit_blocking(struct stm32_qspidev_s *priv, struct qspi_xctnspec_s *xctn) { int ret = OK; volatile uint32_t *datareg = - (volatile uint32_t *)(priv->base + STM32L4_QUADSPI_DR_OFFSET); + (volatile uint32_t *)(priv->base + STM32_QUADSPI_DR_OFFSET); uint8_t *src = (uint8_t *)xctn->buffer; if (src != NULL) @@ -1652,7 +1652,7 @@ static int qspi_transmit_blocking(struct stm32l4_qspidev_s *priv, /* Wait for transfer complete, then clear it */ qspi_waitstatusflags(priv, QSPI_SR_TCF, 1); - qspi_putreg(priv, QSPI_FCR_CTCF, STM32L4_QUADSPI_FCR); + qspi_putreg(priv, QSPI_FCR_CTCF, STM32_QUADSPI_FCR); /* Use Abort to clear the Busy flag */ @@ -1692,7 +1692,7 @@ static int qspi_transmit_blocking(struct stm32l4_qspidev_s *priv, static int qspi_lock(struct qspi_dev_s *dev, bool lock) { - struct stm32l4_qspidev_s *priv = (struct stm32l4_qspidev_s *)dev; + struct stm32_qspidev_s *priv = (struct stm32_qspidev_s *)dev; int ret; spiinfo("lock=%d\n", lock); @@ -1725,7 +1725,7 @@ static int qspi_lock(struct qspi_dev_s *dev, bool lock) static uint32_t qspi_setfrequency(struct qspi_dev_s *dev, uint32_t frequency) { - struct stm32l4_qspidev_s *priv = (struct stm32l4_qspidev_s *)dev; + struct stm32_qspidev_s *priv = (struct stm32_qspidev_s *)dev; uint32_t actual; uint32_t prescaler; uint32_t regval; @@ -1765,7 +1765,7 @@ static uint32_t qspi_setfrequency(struct qspi_dev_s *dev, uint32_t frequency) * prescaler = STL32L4_QSPI_CLOCK / frequency * * Where prescaler can have the range 1 to 256 and the - * STM32L4_QUADSPI_CR_OFFSET register field holds prescaler - 1. + * STM32_QUADSPI_CR_OFFSET register field holds prescaler - 1. * NOTE that a "ceiling" type of calculation is performed. * 'frequency' is treated as a not-to-exceed value. */ @@ -1785,10 +1785,10 @@ static uint32_t qspi_setfrequency(struct qspi_dev_s *dev, uint32_t frequency) /* Save the new prescaler value (minus one) */ - regval = qspi_getreg(priv, STM32L4_QUADSPI_CR_OFFSET); + regval = qspi_getreg(priv, STM32_QUADSPI_CR_OFFSET); regval &= ~(QSPI_CR_PRESCALER_MASK); regval |= (prescaler - 1) << QSPI_CR_PRESCALER_SHIFT; - qspi_putreg(priv, regval, STM32L4_QUADSPI_CR_OFFSET); + qspi_putreg(priv, regval, STM32_QUADSPI_CR_OFFSET); /* Calculate the new actual frequency */ @@ -1822,7 +1822,7 @@ static uint32_t qspi_setfrequency(struct qspi_dev_s *dev, uint32_t frequency) static void qspi_setmode(struct qspi_dev_s *dev, enum qspi_mode_e mode) { - struct stm32l4_qspidev_s *priv = (struct stm32l4_qspidev_s *)dev; + struct stm32_qspidev_s *priv = (struct stm32_qspidev_s *)dev; uint32_t regval; if (priv->memmap) @@ -1850,7 +1850,7 @@ static void qspi_setmode(struct qspi_dev_s *dev, enum qspi_mode_e mode) * 3 1 1 */ - regval = qspi_getreg(priv, STM32L4_QUADSPI_DCR); + regval = qspi_getreg(priv, STM32_QUADSPI_DCR); regval &= ~(QSPI_DCR_CKMODE); switch (mode) @@ -1870,7 +1870,7 @@ static void qspi_setmode(struct qspi_dev_s *dev, enum qspi_mode_e mode) return; } - qspi_putreg(priv, regval, STM32L4_QUADSPI_DCR); + qspi_putreg(priv, regval, STM32_QUADSPI_DCR); spiinfo("DCR=%08" PRIx32 "\n", regval); /* Save the mode so that subsequent re-configurations will be faster */ @@ -1924,7 +1924,7 @@ static void qspi_setbits(struct qspi_dev_s *dev, int nbits) static int qspi_command(struct qspi_dev_s *dev, struct qspi_cmdinfo_s *cmdinfo) { - struct stm32l4_qspidev_s *priv = (struct stm32l4_qspidev_s *)dev; + struct stm32_qspidev_s *priv = (struct stm32_qspidev_s *)dev; struct qspi_xctnspec_s xctn; int ret; @@ -1957,9 +1957,9 @@ static int qspi_command(struct qspi_dev_s *dev, qspi_putreg(priv, QSPI_FCR_CTEF | QSPI_FCR_CTCF | QSPI_FCR_CSMF | QSPI_FCR_CTOF, - STM32L4_QUADSPI_FCR); + STM32_QUADSPI_FCR); -#ifdef STM32L4_QSPI_INTERRUPTS +#ifdef STM32_QSPI_INTERRUPTS /* interrupt mode will need access to the transaction context */ priv->xctn = &xctn; @@ -1983,16 +1983,16 @@ static int qspi_command(struct qspi_dev_s *dev, * Complete' interrupts. */ - regval = qspi_getreg(priv, STM32L4_QUADSPI_CR_OFFSET); + regval = qspi_getreg(priv, STM32_QUADSPI_CR_OFFSET); regval |= (QSPI_CR_TEIE | QSPI_CR_FTIE | QSPI_CR_TCIE); - qspi_putreg(priv, regval, STM32L4_QUADSPI_CR_OFFSET); + qspi_putreg(priv, regval, STM32_QUADSPI_CR_OFFSET); } else { uint32_t regval; uint32_t addrval; - addrval = qspi_getreg(priv, STM32L4_QUADSPI_AR_OFFSET); + addrval = qspi_getreg(priv, STM32_QUADSPI_AR_OFFSET); /* Set up the Communications Configuration Register as per command * info @@ -2002,15 +2002,15 @@ static int qspi_command(struct qspi_dev_s *dev, /* Start the transfer by re-writing the address in AR register */ - qspi_putreg(priv, addrval, STM32L4_QUADSPI_AR_OFFSET); + qspi_putreg(priv, addrval, STM32_QUADSPI_AR_OFFSET); /* Enable 'Transfer Error' 'FIFO Threshhold' and 'Transfer * Complete' interrupts */ - regval = qspi_getreg(priv, STM32L4_QUADSPI_CR_OFFSET); + regval = qspi_getreg(priv, STM32_QUADSPI_CR_OFFSET); regval |= (QSPI_CR_TEIE | QSPI_CR_FTIE | QSPI_CR_TCIE); - qspi_putreg(priv, regval, STM32L4_QUADSPI_CR_OFFSET); + qspi_putreg(priv, regval, STM32_QUADSPI_CR_OFFSET); } } else @@ -2023,9 +2023,9 @@ static int qspi_command(struct qspi_dev_s *dev, /* Enable 'Transfer Error' and 'Transfer Complete' interrupts */ - regval = qspi_getreg(priv, STM32L4_QUADSPI_CR_OFFSET); + regval = qspi_getreg(priv, STM32_QUADSPI_CR_OFFSET); regval |= (QSPI_CR_TEIE | QSPI_CR_TCIE); - qspi_putreg(priv, regval, STM32L4_QUADSPI_CR_OFFSET); + qspi_putreg(priv, regval, STM32_QUADSPI_CR_OFFSET); /* Set up the Communications Configuration Register as per command * info @@ -2106,7 +2106,7 @@ static int qspi_command(struct qspi_dev_s *dev, static int qspi_memory(struct qspi_dev_s *dev, struct qspi_meminfo_s *meminfo) { - struct stm32l4_qspidev_s *priv = (struct stm32l4_qspidev_s *)dev; + struct stm32_qspidev_s *priv = (struct stm32_qspidev_s *)dev; struct qspi_xctnspec_s xctn; int ret; @@ -2139,9 +2139,9 @@ static int qspi_memory(struct qspi_dev_s *dev, qspi_putreg(priv, QSPI_FCR_CTEF | QSPI_FCR_CTCF | QSPI_FCR_CSMF | QSPI_FCR_CTOF, - STM32L4_QUADSPI_FCR); + STM32_QUADSPI_FCR); -#ifdef STM32L4_QSPI_INTERRUPTS +#ifdef STM32_QSPI_INTERRUPTS /* interrupt mode will need access to the transaction context */ priv->xctn = &xctn; @@ -2163,16 +2163,16 @@ static int qspi_memory(struct qspi_dev_s *dev, * interrupts */ - regval = qspi_getreg(priv, STM32L4_QUADSPI_CR_OFFSET); + regval = qspi_getreg(priv, STM32_QUADSPI_CR_OFFSET); regval |= (QSPI_CR_TEIE | QSPI_CR_FTIE | QSPI_CR_TCIE); - qspi_putreg(priv, regval, STM32L4_QUADSPI_CR_OFFSET); + qspi_putreg(priv, regval, STM32_QUADSPI_CR_OFFSET); } else { uint32_t regval; uint32_t addrval; - addrval = qspi_getreg(priv, STM32L4_QUADSPI_AR_OFFSET); + addrval = qspi_getreg(priv, STM32_QUADSPI_AR_OFFSET); /* Set up the Communications Configuration Register as per command * info @@ -2182,15 +2182,15 @@ static int qspi_memory(struct qspi_dev_s *dev, /* Start the transfer by re-writing the address in AR register */ - qspi_putreg(priv, addrval, STM32L4_QUADSPI_AR_OFFSET); + qspi_putreg(priv, addrval, STM32_QUADSPI_AR_OFFSET); /* Enable 'Transfer Error' 'FIFO Threshhold' and 'Transfer Complete' * interrupts */ - regval = qspi_getreg(priv, STM32L4_QUADSPI_CR_OFFSET); + regval = qspi_getreg(priv, STM32_QUADSPI_CR_OFFSET); regval |= (QSPI_CR_TEIE | QSPI_CR_FTIE | QSPI_CR_TCIE); - qspi_putreg(priv, regval, STM32L4_QUADSPI_CR_OFFSET); + qspi_putreg(priv, regval, STM32_QUADSPI_CR_OFFSET); } /* Wait for the interrupt routine to finish it's magic */ @@ -2202,11 +2202,11 @@ static int qspi_memory(struct qspi_dev_s *dev, ret = xctn.disposition; -#elif defined(CONFIG_STM32L4_QSPI_DMA) +#elif defined(CONFIG_STM32_QSPI_DMA) /* Can we perform DMA? Should we perform DMA? */ if (priv->candma && - meminfo->buflen > CONFIG_STM32L4_QSPI_DMATHRESHOLD && + meminfo->buflen > CONFIG_STM32_QSPI_DMATHRESHOLD && IS_ALIGNED((uintptr_t)meminfo->buffer, 4) && IS_ALIGNED(meminfo->buflen, 4)) { @@ -2346,7 +2346,7 @@ static void qspi_free(struct qspi_dev_s *dev, void *buffer) * ****************************************************************************/ -static int qspi_hw_initialize(struct stm32l4_qspidev_s *priv) +static int qspi_hw_initialize(struct stm32_qspidev_s *priv) { uint32_t regval; @@ -2356,7 +2356,7 @@ static int qspi_hw_initialize(struct stm32l4_qspidev_s *priv) regval = 0; regval &= ~(QSPI_CR_EN); - qspi_putreg(priv, regval, STM32L4_QUADSPI_CR_OFFSET); + qspi_putreg(priv, regval, STM32_QUADSPI_CR_OFFSET); /* Wait till BUSY flag reset */ @@ -2364,16 +2364,16 @@ static int qspi_hw_initialize(struct stm32l4_qspidev_s *priv) /* Disable all interrupt sources for starters */ - regval = qspi_getreg(priv, STM32L4_QUADSPI_CR_OFFSET); + regval = qspi_getreg(priv, STM32_QUADSPI_CR_OFFSET); regval &= ~(QSPI_CR_TEIE | QSPI_CR_TCIE | QSPI_CR_FTIE | QSPI_CR_SMIE | QSPI_CR_TOIE); /* Configure QSPI FIFO Threshold */ regval &= ~(QSPI_CR_FTHRES_MASK); - regval |= ((CONFIG_STM32L4_QSPI_FIFO_THESHOLD - 1) << + regval |= ((CONFIG_STM32_QSPI_FIFO_THESHOLD - 1) << QSPI_CR_FTHRES_SHIFT); - qspi_putreg(priv, regval, STM32L4_QUADSPI_CR_OFFSET); + qspi_putreg(priv, regval, STM32_QUADSPI_CR_OFFSET); /* Wait till BUSY flag reset */ @@ -2381,21 +2381,21 @@ static int qspi_hw_initialize(struct stm32l4_qspidev_s *priv) /* Configure QSPI Clock Prescaler and Sample Shift */ - regval = qspi_getreg(priv, STM32L4_QUADSPI_CR_OFFSET); + regval = qspi_getreg(priv, STM32_QUADSPI_CR_OFFSET); regval &= ~(QSPI_CR_PRESCALER_MASK | QSPI_CR_SSHIFT); regval |= (0x01 << QSPI_CR_PRESCALER_SHIFT); regval |= (0x00); - qspi_putreg(priv, regval, STM32L4_QUADSPI_CR_OFFSET); + qspi_putreg(priv, regval, STM32_QUADSPI_CR_OFFSET); /* Configure QSPI Flash Size, CS High Time and Clock Mode */ - regval = qspi_getreg(priv, STM32L4_QUADSPI_DCR_OFFSET); + regval = qspi_getreg(priv, STM32_QUADSPI_DCR_OFFSET); regval &= ~(QSPI_DCR_CKMODE | QSPI_DCR_CSHT_MASK | QSPI_DCR_FSIZE_MASK); regval |= (0x00); - regval |= ((CONFIG_STM32L4_QSPI_CSHT - 1) << QSPI_DCR_CSHT_SHIFT); - if (0 != CONFIG_STM32L4_QSPI_FLASH_SIZE) + regval |= ((CONFIG_STM32_QSPI_CSHT - 1) << QSPI_DCR_CSHT_SHIFT); + if (0 != CONFIG_STM32_QSPI_FLASH_SIZE) { - unsigned int nsize = CONFIG_STM32L4_QSPI_FLASH_SIZE; + unsigned int nsize = CONFIG_STM32_QSPI_FLASH_SIZE; int nlog2size = 31; while (!(nsize & 0x80000000)) { @@ -2406,13 +2406,13 @@ static int qspi_hw_initialize(struct stm32l4_qspidev_s *priv) regval |= ((nlog2size - 1) << QSPI_DCR_FSIZE_SHIFT); } - qspi_putreg(priv, regval, STM32L4_QUADSPI_DCR_OFFSET); + qspi_putreg(priv, regval, STM32_QUADSPI_DCR_OFFSET); /* Enable QSPI */ - regval = qspi_getreg(priv, STM32L4_QUADSPI_CR_OFFSET); + regval = qspi_getreg(priv, STM32_QUADSPI_CR_OFFSET); regval |= QSPI_CR_EN; - qspi_putreg(priv, regval, STM32L4_QUADSPI_CR_OFFSET); + qspi_putreg(priv, regval, STM32_QUADSPI_CR_OFFSET); /* Wait till BUSY flag reset */ @@ -2429,7 +2429,7 @@ static int qspi_hw_initialize(struct stm32l4_qspidev_s *priv) ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_qspi_initialize + * Name: stm32_qspi_initialize * * Description: * Initialize the selected QSPI port in master mode @@ -2442,9 +2442,9 @@ static int qspi_hw_initialize(struct stm32l4_qspidev_s *priv) * ****************************************************************************/ -struct qspi_dev_s *stm32l4_qspi_initialize(int intf) +struct qspi_dev_s *stm32_qspi_initialize(int intf) { - struct stm32l4_qspidev_s *priv; + struct stm32_qspidev_s *priv; uint32_t regval; int ret; @@ -2467,27 +2467,27 @@ struct qspi_dev_s *stm32l4_qspi_initialize(int intf) /* Enable clocking to the QSPI peripheral */ - regval = getreg32(STM32L4_RCC_AHB3ENR); + regval = getreg32(STM32_RCC_AHB3ENR); regval |= RCC_AHB3ENR_QSPIEN; - putreg32(regval, STM32L4_RCC_AHB3ENR); - regval = getreg32(STM32L4_RCC_AHB3ENR); + putreg32(regval, STM32_RCC_AHB3ENR); + regval = getreg32(STM32_RCC_AHB3ENR); /* Reset the QSPI peripheral */ - regval = getreg32(STM32L4_RCC_AHB3RSTR); + regval = getreg32(STM32_RCC_AHB3RSTR); regval |= RCC_AHB3RSTR_QSPIRST; - putreg32(regval, STM32L4_RCC_AHB3RSTR); + putreg32(regval, STM32_RCC_AHB3RSTR); regval &= ~RCC_AHB3RSTR_QSPIRST; - putreg32(regval, STM32L4_RCC_AHB3RSTR); + putreg32(regval, STM32_RCC_AHB3RSTR); /* Configure multiplexed pins as connected on the board. */ - stm32l4_configgpio(GPIO_QSPI_CS); - stm32l4_configgpio(GPIO_QSPI_IO0); - stm32l4_configgpio(GPIO_QSPI_IO1); - stm32l4_configgpio(GPIO_QSPI_IO2); - stm32l4_configgpio(GPIO_QSPI_IO3); - stm32l4_configgpio(GPIO_QSPI_SCK); + stm32_configgpio(GPIO_QSPI_CS); + stm32_configgpio(GPIO_QSPI_IO0); + stm32_configgpio(GPIO_QSPI_IO1); + stm32_configgpio(GPIO_QSPI_IO2); + stm32_configgpio(GPIO_QSPI_IO3); + stm32_configgpio(GPIO_QSPI_SCK); } else { @@ -2501,12 +2501,12 @@ struct qspi_dev_s *stm32l4_qspi_initialize(int intf) { /* Now perform one time initialization */ -#ifdef CONFIG_STM32L4_QSPI_DMA +#ifdef CONFIG_STM32_QSPI_DMA /* Pre-allocate DMA channels. */ if (priv->candma) { - priv->dmach = stm32l4_dmachannel(DMACHAN_QUADSPI); + priv->dmach = stm32_dmachannel(DMACHAN_QUADSPI); if (!priv->dmach) { spierr("ERROR: Failed to allocate the DMA channel\n"); @@ -2515,7 +2515,7 @@ struct qspi_dev_s *stm32l4_qspi_initialize(int intf) } #endif -#ifdef STM32L4_QSPI_INTERRUPTS +#ifdef STM32_QSPI_INTERRUPTS /* Attach the interrupt handler */ ret = irq_attach(priv->irq, priv->handler, NULL); @@ -2541,7 +2541,7 @@ struct qspi_dev_s *stm32l4_qspi_initialize(int intf) priv->initialized = true; priv->memmap = false; -#ifdef STM32L4_QSPI_INTERRUPTS +#ifdef STM32_QSPI_INTERRUPTS up_enable_irq(priv->irq); #endif } @@ -2549,15 +2549,15 @@ struct qspi_dev_s *stm32l4_qspi_initialize(int intf) return &priv->qspi; errout_with_irq: -#ifdef STM32L4_QSPI_INTERRUPTS +#ifdef STM32_QSPI_INTERRUPTS irq_detach(priv->irq); errout_with_dmach: #endif -#ifdef CONFIG_STM32L4_QSPI_DMA +#ifdef CONFIG_STM32_QSPI_DMA if (priv->dmach) { - stm32l4_dmafree(priv->dmach); + stm32_dmafree(priv->dmach); priv->dmach = NULL; } #endif @@ -2566,7 +2566,7 @@ struct qspi_dev_s *stm32l4_qspi_initialize(int intf) } /**************************************************************************** - * Name: stm32l4_qspi_enter_memorymapped + * Name: stm32_qspi_enter_memorymapped * * Description: * Put the QSPI device into memory mapped mode @@ -2580,11 +2580,11 @@ struct qspi_dev_s *stm32l4_qspi_initialize(int intf) * ****************************************************************************/ -void stm32l4_qspi_enter_memorymapped(struct qspi_dev_s *dev, +void stm32_qspi_enter_memorymapped(struct qspi_dev_s *dev, const struct qspi_meminfo_s *meminfo, uint32_t lpto) { - struct stm32l4_qspidev_s *priv = (struct stm32l4_qspidev_s *)dev; + struct stm32_qspidev_s *priv = (struct stm32_qspidev_s *)dev; uint32_t regval; struct qspi_xctnspec_s xctn; @@ -2614,32 +2614,32 @@ void stm32l4_qspi_enter_memorymapped(struct qspi_dev_s *dev, * CS if memory is not accessed for a while) */ - qspi_putreg(priv, lpto, STM32L4_QUADSPI_LPTR_OFFSET); + qspi_putreg(priv, lpto, STM32_QUADSPI_LPTR_OFFSET); /* Clear Timeout interrupt */ - qspi_putreg(&g_qspi0dev, QSPI_FCR_CTOF, STM32L4_QUADSPI_FCR); + qspi_putreg(&g_qspi0dev, QSPI_FCR_CTOF, STM32_QUADSPI_FCR); -#ifdef STM32L4_QSPI_INTERRUPTS +#ifdef STM32_QSPI_INTERRUPTS /* Enable Timeout interrupt */ - regval = qspi_getreg(priv, STM32L4_QUADSPI_CR_OFFSET); + regval = qspi_getreg(priv, STM32_QUADSPI_CR_OFFSET); regval |= (QSPI_CR_TCEN | QSPI_CR_TOIE); - qspi_putreg(priv, regval, STM32L4_QUADSPI_CR_OFFSET); + qspi_putreg(priv, regval, STM32_QUADSPI_CR_OFFSET); #endif } else { - regval = qspi_getreg(priv, STM32L4_QUADSPI_CR_OFFSET); + regval = qspi_getreg(priv, STM32_QUADSPI_CR_OFFSET); regval &= ~QSPI_CR_TCEN; - qspi_putreg(priv, regval, STM32L4_QUADSPI_CR_OFFSET); + qspi_putreg(priv, regval, STM32_QUADSPI_CR_OFFSET); } /* create a transaction object */ qspi_setupxctnfrommem(&xctn, meminfo); -#ifdef STM32L4_QSPI_INTERRUPTS +#ifdef STM32_QSPI_INTERRUPTS priv->xctn = NULL; #endif @@ -2658,7 +2658,7 @@ void stm32l4_qspi_enter_memorymapped(struct qspi_dev_s *dev, } /**************************************************************************** - * Name: stm32l4_qspi_exit_memorymapped + * Name: stm32_qspi_exit_memorymapped * * Description: * Take the QSPI device out of memory mapped mode @@ -2671,9 +2671,9 @@ void stm32l4_qspi_enter_memorymapped(struct qspi_dev_s *dev, * ****************************************************************************/ -void stm32l4_qspi_exit_memorymapped(struct qspi_dev_s *dev) +void stm32_qspi_exit_memorymapped(struct qspi_dev_s *dev) { - struct stm32l4_qspidev_s *priv = (struct stm32l4_qspidev_s *)dev; + struct stm32_qspidev_s *priv = (struct stm32_qspidev_s *)dev; qspi_lock(dev, true); @@ -2685,4 +2685,4 @@ void stm32l4_qspi_exit_memorymapped(struct qspi_dev_s *dev) qspi_lock(dev, false); } -#endif /* CONFIG_STM32L4_QSPI */ +#endif /* CONFIG_STM32_QSPI */ diff --git a/arch/arm/src/stm32l4/stm32l4_qspi.h b/arch/arm/src/stm32l4/stm32l4_qspi.h index f2e7fd119a9c9..3e6f059093630 100644 --- a/arch/arm/src/stm32l4/stm32l4_qspi.h +++ b/arch/arm/src/stm32l4/stm32l4_qspi.h @@ -34,7 +34,7 @@ #include "chip.h" -#ifdef CONFIG_STM32L4_QSPI +#ifdef CONFIG_STM32_QSPI /**************************************************************************** * Pre-processor Definitions @@ -68,7 +68,7 @@ extern "C" ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_qspi_initialize + * Name: stm32_qspi_initialize * * Description: * Initialize the selected QSPI port in master mode @@ -82,10 +82,10 @@ extern "C" ****************************************************************************/ struct qspi_dev_s; -struct qspi_dev_s *stm32l4_qspi_initialize(int intf); +struct qspi_dev_s *stm32_qspi_initialize(int intf); /**************************************************************************** - * Name: stm32l4_qspi_enter_memorymapped + * Name: stm32_qspi_enter_memorymapped * * Description: * Put the QSPI device into memory mapped mode @@ -100,12 +100,12 @@ struct qspi_dev_s *stm32l4_qspi_initialize(int intf); * ****************************************************************************/ -void stm32l4_qspi_enter_memorymapped(struct qspi_dev_s *dev, +void stm32_qspi_enter_memorymapped(struct qspi_dev_s *dev, const struct qspi_meminfo_s *meminfo, uint32_t lpto); /**************************************************************************** - * Name: stm32l4_qspi_exit_memorymapped + * Name: stm32_qspi_exit_memorymapped * * Description: * Take the QSPI device out of memory mapped mode @@ -118,7 +118,7 @@ void stm32l4_qspi_enter_memorymapped(struct qspi_dev_s *dev, * ****************************************************************************/ -void stm32l4_qspi_exit_memorymapped(struct qspi_dev_s *dev); +void stm32_qspi_exit_memorymapped(struct qspi_dev_s *dev); #undef EXTERN #if defined(__cplusplus) @@ -126,5 +126,5 @@ void stm32l4_qspi_exit_memorymapped(struct qspi_dev_s *dev); #endif #endif /* __ASSEMBLY__ */ -#endif /* CONFIG_STM32L4_QSPI */ +#endif /* CONFIG_STM32_QSPI */ #endif /* __ARCH_ARM_SRC_STM32L4_STM32L4_QSPI_H */ diff --git a/arch/arm/src/stm32l4/stm32l4_rcc.c b/arch/arm/src/stm32l4/stm32l4_rcc.c index f59a6be1753c8..f50e55aa0c793 100644 --- a/arch/arm/src/stm32l4/stm32l4_rcc.c +++ b/arch/arm/src/stm32l4/stm32l4_rcc.c @@ -37,19 +37,19 @@ #include "chip.h" #include "stm32l4_rcc.h" #include "stm32l4_flash.h" -#include "stm32l4.h" -#include "stm32l4_waste.h" +#include "stm32.h" +#include "stm32_waste.h" #include "stm32l4_rtc.h" /* Include chip-specific clocking initialization logic */ -#if defined(CONFIG_STM32L4_STM32L4X3) +#if defined(CONFIG_STM32_STM32L4X3) # include "stm32l4x3xx_rcc.c" -#elif defined(CONFIG_STM32L4_STM32L4X5) +#elif defined(CONFIG_STM32_STM32L4X5) # include "stm32l4x5xx_rcc.c" -#elif defined(CONFIG_STM32L4_STM32L4X6) +#elif defined(CONFIG_STM32_STM32L4X6) # include "stm32l4x6xx_rcc.c" -#elif defined(CONFIG_STM32L4_STM32L4XR) +#elif defined(CONFIG_STM32_STM32L4XR) # include "stm32l4xrxx_rcc.c" #else # error "Unsupported STM32L4 chip" @@ -98,52 +98,52 @@ static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1, * ****************************************************************************/ -#if defined(CONFIG_STM32L4_PWR) && defined(CONFIG_STM32L4_RTC) +#if defined(CONFIG_STM32_PWR) && defined(CONFIG_STM32_RTC) static inline void rcc_resetbkp(void) { bool init_stat; /* Check if the RTC is already configured */ - init_stat = stm32l4_rtc_is_initialized(); + init_stat = stm32_rtc_is_initialized(); if (!init_stat) { - uint32_t bkregs[STM32L4_RTC_BKCOUNT]; + uint32_t bkregs[STM32_RTC_BKCOUNT]; int i; /* Backup backup-registers before RTC reset. */ - for (i = 0; i < STM32L4_RTC_BKCOUNT; i++) + for (i = 0; i < STM32_RTC_BKCOUNT; i++) { - bkregs[i] = getreg32(STM32L4_RTC_BKR(i)); + bkregs[i] = getreg32(STM32_RTC_BKR(i)); } /* Enable write access to the backup domain (RTC registers, RTC * backup data registers and backup SRAM). */ - stm32l4_pwr_enablebkp(true); + stm32_pwr_enablebkp(true); /* We might be changing RTCSEL - to ensure such changes work, we must * reset the backup domain (having backed up the RTC_MAGIC token) */ - modifyreg32(STM32L4_RCC_BDCR, 0, RCC_BDCR_BDRST); - modifyreg32(STM32L4_RCC_BDCR, RCC_BDCR_BDRST, 0); + modifyreg32(STM32_RCC_BDCR, 0, RCC_BDCR_BDRST); + modifyreg32(STM32_RCC_BDCR, RCC_BDCR_BDRST, 0); /* Restore backup-registers, except RTC related. */ - for (i = 0; i < STM32L4_RTC_BKCOUNT; i++) + for (i = 0; i < STM32_RTC_BKCOUNT; i++) { - if (RTC_MAGIC_REG == STM32L4_RTC_BKR(i)) + if (RTC_MAGIC_REG == STM32_RTC_BKR(i)) { continue; } - putreg32(bkregs[i], STM32L4_RTC_BKR(i)); + putreg32(bkregs[i], STM32_RTC_BKR(i)); } - stm32l4_pwr_enablebkp(false); + stm32_pwr_enablebkp(false); } } #else @@ -155,7 +155,7 @@ static inline void rcc_resetbkp(void) ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_clockconfig + * Name: stm32_clockconfig * * Description: * Called to establish the clock settings based on the values in board.h. @@ -163,9 +163,9 @@ static inline void rcc_resetbkp(void) * and enable peripheral clocking for all peripherals enabled in the NuttX * configuration file. * - * If CONFIG_ARCH_BOARD_STM32L4_CUSTOM_CLOCKCONFIG is defined, then + * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then * clocking will be enabled by an externally provided, board-specific - * function called stm32l4_board_clockconfig(). + * function called stm32_board_clockconfig(). * * Input Parameters: * None @@ -175,7 +175,7 @@ static inline void rcc_resetbkp(void) * ****************************************************************************/ -void stm32l4_clockconfig(void) +void stm32_clockconfig(void) { /* Make sure that we are starting in the reset state */ @@ -185,11 +185,11 @@ void stm32l4_clockconfig(void) rcc_resetbkp(); -#if defined(CONFIG_ARCH_BOARD_STM32L4_CUSTOM_CLOCKCONFIG) +#if defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) /* Invoke Board Custom Clock Configuration */ - stm32l4_board_clockconfig(); + stm32_board_clockconfig(); #else @@ -197,7 +197,7 @@ void stm32l4_clockconfig(void) * board.h */ - stm32l4_stdclockconfig(); + stm32_stdclockconfig(); #endif @@ -207,7 +207,7 @@ void stm32l4_clockconfig(void) } /**************************************************************************** - * Name: stm32l4_clockenable + * Name: stm32_clockenable * * Description: * Re-enable the clock and restore the clock settings based on settings in @@ -217,12 +217,12 @@ void stm32l4_clockconfig(void) * re-enable/re-start the PLL * * This functional performs a subset of the operations performed by - * stm32l4_clockconfig(): It does not reset any devices, and it does not + * stm32_clockconfig(): It does not reset any devices, and it does not * reset the currently enabled peripheral clocks. * - * If CONFIG_ARCH_BOARD_STM32L4_CUSTOM_CLOCKCONFIG is defined, then + * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then * clocking will be enabled by an externally provided, board-specific - * function called stm32l4_board_clockconfig(). + * function called stm32_board_clockconfig(). * * Input Parameters: * None @@ -233,13 +233,13 @@ void stm32l4_clockconfig(void) ****************************************************************************/ #ifdef CONFIG_PM -void stm32l4_clockenable(void) +void stm32_clockenable(void) { -#if defined(CONFIG_ARCH_BOARD_STM32L4_CUSTOM_CLOCKCONFIG) +#if defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) /* Invoke Board Custom Clock Configuration */ - stm32l4_board_clockconfig(); + stm32_board_clockconfig(); #else @@ -247,7 +247,7 @@ void stm32l4_clockenable(void) * board.h */ - stm32l4_stdclockconfig(); + stm32_stdclockconfig(); #endif } diff --git a/arch/arm/src/stm32l4/stm32l4_rcc.h b/arch/arm/src/stm32l4/stm32l4_rcc.h index 29c8257c00bbc..624a25ec93391 100644 --- a/arch/arm/src/stm32l4/stm32l4_rcc.h +++ b/arch/arm/src/stm32l4/stm32l4_rcc.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32L4_STM32L4_RCC_H -#define __ARCH_ARM_SRC_STM32L4_STM32L4_RCC_H +#ifndef __ARCH_ARM_SRC_STM32L4_STM32_RCC_H +#define __ARCH_ARM_SRC_STM32L4_STM32_RCC_H /**************************************************************************** * Included Files @@ -32,13 +32,13 @@ #include "arm_internal.h" #include "chip.h" -#if defined(CONFIG_STM32L4_STM32L4X3) +#if defined(CONFIG_STM32_STM32L4X3) # include "hardware/stm32l4x3xx_rcc.h" -#elif defined(CONFIG_STM32L4_STM32L4X5) +#elif defined(CONFIG_STM32_STM32L4X5) # include "hardware/stm32l4x5xx_rcc.h" -#elif defined(CONFIG_STM32L4_STM32L4X6) +#elif defined(CONFIG_STM32_STM32L4X6) # include "hardware/stm32l4x6xx_rcc.h" -#elif defined(CONFIG_STM32L4_STM32L4XR) +#elif defined(CONFIG_STM32_STM32L4XR) # include "hardware/stm32l4xrxx_rcc.h" #else # error "Unsupported STM32L4 chip" @@ -64,7 +64,7 @@ extern "C" ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_mcoconfig + * Name: stm32_mcoconfig * * Description: * Selects the clock source to output on MC pin (PA8) for stm32f10xxx. @@ -82,16 +82,16 @@ extern "C" * ****************************************************************************/ -static inline void stm32l4_mcoconfig(uint32_t source) +static inline void stm32_mcoconfig(uint32_t source) { uint32_t regval; /* Set MCO source */ - regval = getreg32(STM32L4_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~(RCC_CFGR_MCO_MASK); regval |= (source & RCC_CFGR_MCO_MASK); - putreg32(regval, STM32L4_RCC_CFGR); + putreg32(regval, STM32_RCC_CFGR); } /**************************************************************************** @@ -99,7 +99,7 @@ static inline void stm32l4_mcoconfig(uint32_t source) ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_clockconfig + * Name: stm32_clockconfig * * Description: * Called to establish the clock settings based on the values in board.h. @@ -107,9 +107,9 @@ static inline void stm32l4_mcoconfig(uint32_t source) * and enable peripheral clocking for all periperipherals enabled in the * NuttX configuration file. * - * If CONFIG_ARCH_BOARD_STM32L4_CUSTOM_CLOCKCONFIG is defined, then + * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then * clocking will be enabled by an externally provided, board-specific - * function called stm32l4_board_clockconfig(). + * function called stm32_board_clockconfig(). * * Input Parameters: * None @@ -119,10 +119,10 @@ static inline void stm32l4_mcoconfig(uint32_t source) * ****************************************************************************/ -void stm32l4_clockconfig(void); +void stm32_clockconfig(void); /**************************************************************************** - * Name: stm32l4_board_clockconfig + * Name: stm32_board_clockconfig * * Description: * Any STM32L4 board may replace the "standard" board clock configuration @@ -130,12 +130,12 @@ void stm32l4_clockconfig(void); * ****************************************************************************/ -#ifdef CONFIG_ARCH_BOARD_STM32L4_CUSTOM_CLOCKCONFIG -void stm32l4_board_clockconfig(void); +#ifdef CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG +void stm32_board_clockconfig(void); #endif /**************************************************************************** - * Name: stm32l4_clockenable + * Name: stm32_clockenable * * Description: * Re-enable the clock and restore the clock settings based on settings in @@ -144,12 +144,12 @@ void stm32l4_board_clockconfig(void); * re-enable/re-start the PLL * * This functional performs a subset of the operations performed by - * stm32l4_clockconfig(): It does not reset any devices, and it does not + * stm32_clockconfig(): It does not reset any devices, and it does not * reset the currently enabled peripheral clocks. * - * If CONFIG_ARCH_BOARD_STM32L4_CUSTOM_CLOCKCONFIG is defined, then + * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then * clocking will be enabled by an externally provided, board-specific - * function called stm32l4_board_clockconfig(). + * function called stm32_board_clockconfig(). * * Input Parameters: * None @@ -160,11 +160,11 @@ void stm32l4_board_clockconfig(void); ****************************************************************************/ #ifdef CONFIG_PM -void stm32l4_clockenable(void); +void stm32_clockenable(void); #endif /**************************************************************************** - * Name: stm32l4_rcc_enablelse + * Name: stm32_rcc_enablelse * * Description: * Enable the External Low-Speed (LSE) Oscillator. @@ -177,31 +177,31 @@ void stm32l4_clockenable(void); * ****************************************************************************/ -void stm32l4_rcc_enablelse(void); +void stm32_rcc_enablelse(void); /**************************************************************************** - * Name: stm32l4_rcc_enablelsi + * Name: stm32_rcc_enablelsi * * Description: * Enable the Internal Low-Speed (LSI) RC Oscillator. * ****************************************************************************/ -void stm32l4_rcc_enablelsi(void); +void stm32_rcc_enablelsi(void); /**************************************************************************** - * Name: stm32l4_rcc_disablelsi + * Name: stm32_rcc_disablelsi * * Description: * Disable the Internal Low-Speed (LSI) RC Oscillator. * ****************************************************************************/ -void stm32l4_rcc_disablelsi(void); +void stm32_rcc_disablelsi(void); #undef EXTERN #if defined(__cplusplus) } #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32L4_STM32L4_RCC_H */ +#endif /* __ARCH_ARM_SRC_STM32L4_STM32_RCC_H */ diff --git a/arch/arm/src/stm32l4/stm32l4_rng.c b/arch/arm/src/stm32l4/stm32l4_rng.c index 142890ddad972..9c3e70831ae7a 100644 --- a/arch/arm/src/stm32l4/stm32l4_rng.c +++ b/arch/arm/src/stm32l4/stm32l4_rng.c @@ -41,18 +41,18 @@ #include "hardware/stm32l4_rng.h" #include "arm_internal.h" -#if defined(CONFIG_STM32L4_RNG) +#if defined(CONFIG_STM32_RNG) #if defined(CONFIG_DEV_RANDOM) || defined(CONFIG_DEV_URANDOM_ARCH) /**************************************************************************** * Private Function Prototypes ****************************************************************************/ -static int stm32l4_rng_initialize(void); -static int stm32l4_rnginterrupt(int irq, void *context, void *arg); -static void stm32l4_rngenable(void); -static void stm32l4_rngdisable(void); -static ssize_t stm32l4_rngread(struct file *filep, char *buffer, size_t); +static int stm32_rng_initialize(void); +static int stm32_rnginterrupt(int irq, void *context, void *arg); +static void stm32_rngenable(void); +static void stm32_rngdisable(void); +static ssize_t stm32_rngread(struct file *filep, char *buffer, size_t); /**************************************************************************** * Private Types @@ -82,18 +82,18 @@ static const struct file_operations g_rngops = { NULL, /* open */ NULL, /* close */ - stm32l4_rngread, /* read */ + stm32_rngread, /* read */ }; /**************************************************************************** * Private functions ****************************************************************************/ -static int stm32l4_rng_initialize(void) +static int stm32_rng_initialize(void) { _info("Initializing RNG\n"); - if (irq_attach(STM32L4_IRQ_RNG, stm32l4_rnginterrupt, NULL)) + if (irq_attach(STM32_IRQ_RNG, stm32_rnginterrupt, NULL)) { /* We could not attach the ISR to the interrupt */ @@ -105,7 +105,7 @@ static int stm32l4_rng_initialize(void) return OK; } -static void stm32l4_rngenable(void) +static void stm32_rngenable(void) { uint32_t regval; @@ -113,37 +113,37 @@ static void stm32l4_rngenable(void) /* Enable generation and interrupts */ - regval = getreg32(STM32L4_RNG_CR); + regval = getreg32(STM32_RNG_CR); regval |= RNG_CR_RNGEN; regval |= RNG_CR_IE; - putreg32(regval, STM32L4_RNG_CR); + putreg32(regval, STM32_RNG_CR); - up_enable_irq(STM32L4_IRQ_RNG); + up_enable_irq(STM32_IRQ_RNG); } -static void stm32l4_rngdisable(void) +static void stm32_rngdisable(void) { uint32_t regval; - up_disable_irq(STM32L4_IRQ_RNG); + up_disable_irq(STM32_IRQ_RNG); - regval = getreg32(STM32L4_RNG_CR); + regval = getreg32(STM32_RNG_CR); regval &= ~RNG_CR_IE; regval &= ~RNG_CR_RNGEN; - putreg32(regval, STM32L4_RNG_CR); + putreg32(regval, STM32_RNG_CR); } -static int stm32l4_rnginterrupt(int irq, void *context, void *arg) +static int stm32_rnginterrupt(int irq, void *context, void *arg) { uint32_t rngsr; uint32_t data; - rngsr = getreg32(STM32L4_RNG_SR); + rngsr = getreg32(STM32_RNG_SR); if (rngsr & RNG_SR_CEIS) /* Check for clock error int stat */ { /* Clear it, we will try again. */ - putreg32(rngsr & ~RNG_SR_CEIS, STM32L4_RNG_SR); + putreg32(rngsr & ~RNG_SR_CEIS, STM32_RNG_SR); return OK; } @@ -153,12 +153,12 @@ static int stm32l4_rnginterrupt(int irq, void *context, void *arg) /* Clear seed error, then disable/enable the rng and try again. */ - putreg32(rngsr & ~RNG_SR_SEIS, STM32L4_RNG_SR); - crval = getreg32(STM32L4_RNG_CR); + putreg32(rngsr & ~RNG_SR_SEIS, STM32_RNG_SR); + crval = getreg32(STM32_RNG_CR); crval &= ~RNG_CR_RNGEN; - putreg32(crval, STM32L4_RNG_CR); + putreg32(crval, STM32_RNG_CR); crval |= RNG_CR_RNGEN; - putreg32(crval, STM32L4_RNG_CR); + putreg32(crval, STM32_RNG_CR); return OK; } @@ -169,7 +169,7 @@ static int stm32l4_rnginterrupt(int irq, void *context, void *arg) return OK; } - data = getreg32(STM32L4_RNG_DR); + data = getreg32(STM32_RNG_DR); /* As required by the FIPS PUB (Federal Information Processing Standard * Publication) 140-2, the first random number generated after setting the @@ -216,7 +216,7 @@ static int stm32l4_rnginterrupt(int irq, void *context, void *arg) { /* Buffer filled, stop further interrupts. */ - stm32l4_rngdisable(); + stm32_rngdisable(); nxsem_post(&g_rngdev.rd_readsem); } @@ -224,10 +224,10 @@ static int stm32l4_rnginterrupt(int irq, void *context, void *arg) } /**************************************************************************** - * Name: stm32l4_rngread + * Name: stm32_rngread ****************************************************************************/ -static ssize_t stm32l4_rngread(struct file *filep, +static ssize_t stm32_rngread(struct file *filep, char *buffer, size_t buflen) { int ret; @@ -251,7 +251,7 @@ static ssize_t stm32l4_rngread(struct file *filep, /* Enable RNG with interrupts */ - stm32l4_rngenable(); + stm32_rngenable(); /* Wait until the buffer is filled */ @@ -285,7 +285,7 @@ static ssize_t stm32l4_rngread(struct file *filep, #ifdef CONFIG_DEV_RANDOM void devrandom_register(void) { - stm32l4_rng_initialize(); + stm32_rng_initialize(); register_driver("/dev/random", &g_rngops, 0444, NULL); } #endif @@ -308,11 +308,11 @@ void devrandom_register(void) void devurandom_register(void) { #ifndef CONFIG_DEV_RANDOM - stm32l4_rng_initialize(); + stm32_rng_initialize(); #endif register_driver("/dev/urandom", &g_rngops, 0444, NULL); } #endif #endif /* CONFIG_DEV_RANDOM || CONFIG_DEV_URANDOM_ARCH */ -#endif /* CONFIG_STM32L4_RNG */ +#endif /* CONFIG_STM32_RNG */ diff --git a/arch/arm/src/stm32l4/stm32l4_rtc.c b/arch/arm/src/stm32l4/stm32l4_rtc.c index 17cd5e349f3a4..afd88e708aa8a 100644 --- a/arch/arm/src/stm32l4/stm32l4_rtc.c +++ b/arch/arm/src/stm32l4/stm32l4_rtc.c @@ -46,7 +46,7 @@ #include "stm32l4_exti.h" #include "stm32l4_rtc.h" -#ifdef CONFIG_STM32L4_RTC +#ifdef CONFIG_STM32_RTC /**************************************************************************** * Pre-processor Definitions @@ -67,8 +67,8 @@ # error "CONFIG_RTC_HIRES must NOT be set with this driver" #endif -#ifndef CONFIG_STM32L4_PWR -# error "CONFIG_STM32L4_PWR must selected to use this driver" +#ifndef CONFIG_STM32_PWR +# error "CONFIG_STM32_PWR must selected to use this driver" #endif /* Constants ****************************************************************/ @@ -142,23 +142,23 @@ static inline void rtc_enable_alarm(void); static void rtc_dumpregs(const char *msg) { rtcinfo("%s:\n", msg); - rtcinfo(" TR: %08" PRIx32 "\n", getreg32(STM32L4_RTC_TR)); - rtcinfo(" DR: %08" PRIx32 "\n", getreg32(STM32L4_RTC_DR)); - rtcinfo(" CR: %08" PRIx32 "\n", getreg32(STM32L4_RTC_CR)); - rtcinfo(" ISR: %08" PRIx32 "\n", getreg32(STM32L4_RTC_ISR)); - rtcinfo(" PRER: %08" PRIx32 "\n", getreg32(STM32L4_RTC_PRER)); - rtcinfo(" WUTR: %08" PRIx32 "\n", getreg32(STM32L4_RTC_WUTR)); - - rtcinfo(" ALRMAR: %08" PRIx32 "\n", getreg32(STM32L4_RTC_ALRMAR)); - rtcinfo(" ALRMBR: %08" PRIx32 "\n", getreg32(STM32L4_RTC_ALRMBR)); - rtcinfo(" SHIFTR: %08" PRIx32 "\n", getreg32(STM32L4_RTC_SHIFTR)); - rtcinfo(" TSTR: %08" PRIx32 "\n", getreg32(STM32L4_RTC_TSTR)); - rtcinfo(" TSDR: %08" PRIx32 "\n", getreg32(STM32L4_RTC_TSDR)); - rtcinfo(" TSSSR: %08" PRIx32 "\n", getreg32(STM32L4_RTC_TSSSR)); - rtcinfo(" CALR: %08" PRIx32 "\n", getreg32(STM32L4_RTC_CALR)); - rtcinfo(" TAMPCR: %08" PRIx32 "\n", getreg32(STM32L4_RTC_TAMPCR)); - rtcinfo("ALRMASSR: %08" PRIx32 "\n", getreg32(STM32L4_RTC_ALRMASSR)); - rtcinfo("ALRMBSSR: %08" PRIx32 "\n", getreg32(STM32L4_RTC_ALRMBSSR)); + rtcinfo(" TR: %08" PRIx32 "\n", getreg32(STM32_RTC_TR)); + rtcinfo(" DR: %08" PRIx32 "\n", getreg32(STM32_RTC_DR)); + rtcinfo(" CR: %08" PRIx32 "\n", getreg32(STM32_RTC_CR)); + rtcinfo(" ISR: %08" PRIx32 "\n", getreg32(STM32_RTC_ISR)); + rtcinfo(" PRER: %08" PRIx32 "\n", getreg32(STM32_RTC_PRER)); + rtcinfo(" WUTR: %08" PRIx32 "\n", getreg32(STM32_RTC_WUTR)); + + rtcinfo(" ALRMAR: %08" PRIx32 "\n", getreg32(STM32_RTC_ALRMAR)); + rtcinfo(" ALRMBR: %08" PRIx32 "\n", getreg32(STM32_RTC_ALRMBR)); + rtcinfo(" SHIFTR: %08" PRIx32 "\n", getreg32(STM32_RTC_SHIFTR)); + rtcinfo(" TSTR: %08" PRIx32 "\n", getreg32(STM32_RTC_TSTR)); + rtcinfo(" TSDR: %08" PRIx32 "\n", getreg32(STM32_RTC_TSDR)); + rtcinfo(" TSSSR: %08" PRIx32 "\n", getreg32(STM32_RTC_TSSSR)); + rtcinfo(" CALR: %08" PRIx32 "\n", getreg32(STM32_RTC_CALR)); + rtcinfo(" TAMPCR: %08" PRIx32 "\n", getreg32(STM32_RTC_TAMPCR)); + rtcinfo("ALRMASSR: %08" PRIx32 "\n", getreg32(STM32_RTC_ALRMASSR)); + rtcinfo("ALRMBSSR: %08" PRIx32 "\n", getreg32(STM32_RTC_ALRMBSSR)); rtcinfo("MAGICREG: %08" PRIx32 "\n", getreg32(RTC_MAGIC_REG)); } #else @@ -208,7 +208,7 @@ static void rtc_wprunlock(void) { /* Enable write access to the backup domain. */ - stm32l4_pwr_enablebkp(true); + stm32_pwr_enablebkp(true); /* The following steps are required to unlock the write protection on * all the RTC registers (except for RTC_ISR[13:8], RTC_TAFCR, and @@ -220,8 +220,8 @@ static void rtc_wprunlock(void) * Writing a wrong key re-activates the write protection. */ - putreg32(0xca, STM32L4_RTC_WPR); - putreg32(0x53, STM32L4_RTC_WPR); + putreg32(0xca, STM32_RTC_WPR); + putreg32(0x53, STM32_RTC_WPR); } /**************************************************************************** @@ -242,11 +242,11 @@ static inline void rtc_wprlock(void) { /* Writing any wrong key re-activates the write protection. */ - putreg32(0xff, STM32L4_RTC_WPR); + putreg32(0xff, STM32_RTC_WPR); /* Disable write access to the backup domain. */ - stm32l4_pwr_enablebkp(false); + stm32_pwr_enablebkp(false); } /**************************************************************************** @@ -272,16 +272,16 @@ static int rtc_synchwait(void) /* Clear Registers synchronization flag (RSF) */ - regval = getreg32(STM32L4_RTC_ISR); + regval = getreg32(STM32_RTC_ISR); regval &= ~RTC_ISR_RSF; - putreg32(regval, STM32L4_RTC_ISR); + putreg32(regval, STM32_RTC_ISR); /* Now wait the registers to become synchronised */ ret = -ETIMEDOUT; for (timeout = 0; timeout < SYNCHRO_TIMEOUT; timeout++) { - regval = getreg32(STM32L4_RTC_ISR); + regval = getreg32(STM32_RTC_ISR); if ((regval & RTC_ISR_RSF) != 0) { /* Synchronized */ @@ -316,21 +316,21 @@ static int rtc_enterinit(void) /* Check if the Initialization mode is already set */ - regval = getreg32(STM32L4_RTC_ISR); + regval = getreg32(STM32_RTC_ISR); ret = OK; if ((regval & RTC_ISR_INITF) == 0) { /* Set the Initialization mode */ - putreg32(RTC_ISR_INIT, STM32L4_RTC_ISR); + putreg32(RTC_ISR_INIT, STM32_RTC_ISR); /* Wait until the RTC is in the INIT state (or a timeout occurs) */ ret = -ETIMEDOUT; for (timeout = 0; timeout < INITMODE_TIMEOUT; timeout++) { - regval = getreg32(STM32L4_RTC_ISR); + regval = getreg32(STM32_RTC_ISR); if ((regval & RTC_ISR_INITF) != 0) { ret = OK; @@ -360,9 +360,9 @@ static void rtc_exitinit(void) { uint32_t regval; - regval = getreg32(STM32L4_RTC_ISR); + regval = getreg32(STM32_RTC_ISR); regval &= ~(RTC_ISR_INIT); - putreg32(regval, STM32L4_RTC_ISR); + putreg32(regval, STM32_RTC_ISR); } /**************************************************************************** @@ -434,18 +434,18 @@ static void rtc_resume(void) /* Clear the RTC alarm flags */ - regval = getreg32(STM32L4_RTC_ISR); + regval = getreg32(STM32_RTC_ISR); regval &= ~(RTC_ISR_ALRAF | RTC_ISR_ALRBF); - putreg32(regval, STM32L4_RTC_ISR); + putreg32(regval, STM32_RTC_ISR); /* Clear the EXTI Line 18 Pending bit (Connected internally to RTC Alarm) */ - putreg32(EXTI1_RTC_ALARM, STM32L4_EXTI1_PR); + putreg32(EXTI1_RTC_ALARM, STM32_EXTI1_PR); #endif } /**************************************************************************** - * Name: stm32l4_rtc_alarm_handler + * Name: stm32_rtc_alarm_handler * * Description: * RTC ALARM interrupt service routine through the EXTI line @@ -460,7 +460,7 @@ static void rtc_resume(void) ****************************************************************************/ #ifdef CONFIG_RTC_ALARM -static int stm32l4_rtc_alarm_handler(int irq, void *context, +static int stm32_rtc_alarm_handler(int irq, void *context, void *rtc_handler_arg) { struct alm_cbinfo_s *cbinfo; @@ -474,14 +474,14 @@ static int stm32l4_rtc_alarm_handler(int irq, void *context, * backup data registers and backup SRAM). */ - stm32l4_pwr_enablebkp(true); + stm32_pwr_enablebkp(true); /* Check for EXTI from Alarm A or B and handle according */ - cr = getreg32(STM32L4_RTC_CR); + cr = getreg32(STM32_RTC_CR); if ((cr & RTC_CR_ALRAIE) != 0) { - isr = getreg32(STM32L4_RTC_ISR); + isr = getreg32(STM32_RTC_ISR); if ((isr & RTC_ISR_ALRAF) != 0) { cbinfo = &g_alarmcb[RTC_ALARMA]; @@ -500,17 +500,17 @@ static int stm32l4_rtc_alarm_handler(int irq, void *context, /* note, bits 8-13 do /not/ require the write enable procedure */ - isr = getreg32(STM32L4_RTC_ISR); + isr = getreg32(STM32_RTC_ISR); isr &= ~RTC_ISR_ALRAF; - putreg32(isr, STM32L4_RTC_ISR); + putreg32(isr, STM32_RTC_ISR); } } #if CONFIG_RTC_NALARMS > 1 - cr = getreg32(STM32L4_RTC_CR); + cr = getreg32(STM32_RTC_CR); if ((cr & RTC_CR_ALRBIE) != 0) { - isr = getreg32(STM32L4_RTC_ISR); + isr = getreg32(STM32_RTC_ISR); if ((isr & RTC_ISR_ALRBF) != 0) { cbinfo = &g_alarmcb[RTC_ALARMB]; @@ -529,9 +529,9 @@ static int stm32l4_rtc_alarm_handler(int irq, void *context, /* note, bits 8-13 do /not/ require the write enable procedure */ - isr = getreg32(STM32L4_RTC_ISR); + isr = getreg32(STM32_RTC_ISR); isr &= ~RTC_ISR_ALRBF; - putreg32(isr, STM32L4_RTC_ISR); + putreg32(isr, STM32_RTC_ISR); } } #endif @@ -540,7 +540,7 @@ static int stm32l4_rtc_alarm_handler(int irq, void *context, * data registers and backup SRAM). */ - stm32l4_pwr_enablebkp(false); + stm32_pwr_enablebkp(false); return ret; } @@ -574,7 +574,7 @@ static int rtchw_check_alrawf(void) for (timeout = 0; timeout < INITMODE_TIMEOUT; timeout++) { - regval = getreg32(STM32L4_RTC_ISR); + regval = getreg32(STM32_RTC_ISR); if ((regval & RTC_ISR_ALRAWF) != 0) { ret = OK; @@ -600,7 +600,7 @@ static int rtchw_check_alrbwf(void) for (timeout = 0; timeout < INITMODE_TIMEOUT; timeout++) { - regval = getreg32(STM32L4_RTC_ISR); + regval = getreg32(STM32_RTC_ISR); if ((regval & RTC_ISR_ALRBWF) != 0) { ret = OK; @@ -639,12 +639,12 @@ static int rtchw_set_alrmar(rtc_alarmreg_t alarmreg) /* Disable RTC alarm A & Interrupt A */ - modifyreg32(STM32L4_RTC_CR, (RTC_CR_ALRAE | RTC_CR_ALRAIE), 0); + modifyreg32(STM32_RTC_CR, (RTC_CR_ALRAE | RTC_CR_ALRAIE), 0); /* Ensure Alarm A flag reset; this is edge triggered */ - isr = getreg32(STM32L4_RTC_ISR) & ~RTC_ISR_ALRAF; - putreg32(isr, STM32L4_RTC_ISR); + isr = getreg32(STM32_RTC_ISR) & ~RTC_ISR_ALRAF; + putreg32(isr, STM32_RTC_ISR); /* Wait for Alarm A to be writable */ @@ -656,13 +656,13 @@ static int rtchw_set_alrmar(rtc_alarmreg_t alarmreg) /* Set the RTC Alarm A register */ - putreg32(alarmreg, STM32L4_RTC_ALRMAR); - putreg32(0, STM32L4_RTC_ALRMASSR); - rtcinfo(" ALRMAR: %08" PRIx32 "\n", getreg32(STM32L4_RTC_ALRMAR)); + putreg32(alarmreg, STM32_RTC_ALRMAR); + putreg32(0, STM32_RTC_ALRMASSR); + rtcinfo(" ALRMAR: %08" PRIx32 "\n", getreg32(STM32_RTC_ALRMAR)); /* Enable RTC alarm A */ - modifyreg32(STM32L4_RTC_CR, 0, (RTC_CR_ALRAE | RTC_CR_ALRAIE)); + modifyreg32(STM32_RTC_CR, 0, (RTC_CR_ALRAE | RTC_CR_ALRAIE)); errout_with_wprunlock: rtc_wprlock(); @@ -682,12 +682,12 @@ static int rtchw_set_alrmbr(rtc_alarmreg_t alarmreg) /* Disable RTC alarm B & Interrupt B */ - modifyreg32(STM32L4_RTC_CR, (RTC_CR_ALRBE | RTC_CR_ALRBIE), 0); + modifyreg32(STM32_RTC_CR, (RTC_CR_ALRBE | RTC_CR_ALRBIE), 0); /* Ensure Alarm B flag reset; this is edge triggered */ - isr = getreg32(STM32L4_RTC_ISR) & ~RTC_ISR_ALRBF; - putreg32(isr, STM32L4_RTC_ISR); + isr = getreg32(STM32_RTC_ISR) & ~RTC_ISR_ALRBF; + putreg32(isr, STM32_RTC_ISR); /* Wait for Alarm B to be writable */ @@ -699,13 +699,13 @@ static int rtchw_set_alrmbr(rtc_alarmreg_t alarmreg) /* Set the RTC Alarm B register */ - putreg32(alarmreg, STM32L4_RTC_ALRMBR); - putreg32(0, STM32L4_RTC_ALRMBSSR); - rtcinfo(" ALRMBR: %08" PRIx32 "\n", getreg32(STM32L4_RTC_ALRMBR)); + putreg32(alarmreg, STM32_RTC_ALRMBR); + putreg32(0, STM32_RTC_ALRMBSSR); + rtcinfo(" ALRMBR: %08" PRIx32 "\n", getreg32(STM32_RTC_ALRMBR)); /* Enable RTC alarm B */ - modifyreg32(STM32L4_RTC_CR, 0, (RTC_CR_ALRBE | RTC_CR_ALRBIE)); + modifyreg32(STM32_RTC_CR, 0, (RTC_CR_ALRBE | RTC_CR_ALRBIE)); rtchw_set_alrmbr_exit: rtc_wprlock(); @@ -746,14 +746,14 @@ static inline void rtc_enable_alarm(void) * 3. Configure the RTC to generate RTC alarms (Alarm A or Alarm B). */ - stm32l4_exti_alarm(true, false, true, stm32l4_rtc_alarm_handler, NULL); + stm32_exti_alarm(true, false, true, stm32_rtc_alarm_handler, NULL); g_alarm_enabled = true; } } #endif /**************************************************************************** - * Name: stm32l4_rtc_getalarmdatetime + * Name: stm32_rtc_getalarmdatetime * * Description: * Get the current date and time for a RTC alarm. @@ -768,7 +768,7 @@ static inline void rtc_enable_alarm(void) ****************************************************************************/ #ifdef CONFIG_RTC_ALARM -static int stm32l4_rtc_getalarmdatetime(rtc_alarmreg_t reg, +static int stm32_rtc_getalarmdatetime(rtc_alarmreg_t reg, struct tm *tp) { uint32_t data; @@ -809,7 +809,7 @@ static int stm32l4_rtc_getalarmdatetime(rtc_alarmreg_t reg, ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_rtc_is_initialized + * Name: stm32_rtc_is_initialized * * Description: * Returns 'true' if the RTC has been initialized @@ -825,7 +825,7 @@ static int stm32l4_rtc_getalarmdatetime(rtc_alarmreg_t reg, * ****************************************************************************/ -bool stm32l4_rtc_is_initialized(void) +bool stm32_rtc_is_initialized(void) { uint32_t regval; @@ -860,23 +860,23 @@ int up_rtc_initialize(void) * backed, we don't need or want to re-initialize on each reset. */ - init_stat = stm32l4_rtc_is_initialized(); + init_stat = stm32_rtc_is_initialized(); if (!init_stat) { /* Enable write access to the backup domain (RTC registers, RTC * backup data registers and backup SRAM). */ - stm32l4_pwr_enablebkp(true); + stm32_pwr_enablebkp(true); -#if defined(CONFIG_STM32L4_RTC_HSECLOCK) - modifyreg32(STM32L4_RCC_BDCR, RCC_BDCR_RTCSEL_MASK, +#if defined(CONFIG_STM32_RTC_HSECLOCK) + modifyreg32(STM32_RCC_BDCR, RCC_BDCR_RTCSEL_MASK, RCC_BDCR_RTCSEL_HSE); -#elif defined(CONFIG_STM32L4_RTC_LSICLOCK) - modifyreg32(STM32L4_RCC_BDCR, RCC_BDCR_RTCSEL_MASK, +#elif defined(CONFIG_STM32_RTC_LSICLOCK) + modifyreg32(STM32_RCC_BDCR, RCC_BDCR_RTCSEL_MASK, RCC_BDCR_RTCSEL_LSI); -#elif defined(CONFIG_STM32L4_RTC_LSECLOCK) - modifyreg32(STM32L4_RCC_BDCR, RCC_BDCR_RTCSEL_MASK, +#elif defined(CONFIG_STM32_RTC_LSECLOCK) + modifyreg32(STM32_RCC_BDCR, RCC_BDCR_RTCSEL_MASK, RCC_BDCR_RTCSEL_LSE); #else # error "No clock for RTC!" @@ -884,7 +884,7 @@ int up_rtc_initialize(void) /* Enable the RTC Clock by setting the RTCEN bit in the RCC register */ - modifyreg32(STM32L4_RCC_BDCR, 0, RCC_BDCR_RTCEN); + modifyreg32(STM32_RCC_BDCR, 0, RCC_BDCR_RTCEN); /* Disable the write protection for RTC registers */ @@ -902,7 +902,7 @@ int up_rtc_initialize(void) * RTC backup data registers and backup SRAM). */ - stm32l4_pwr_enablebkp(false); + stm32_pwr_enablebkp(false); rtc_dumpregs("After Failed Initialization"); @@ -912,13 +912,13 @@ int up_rtc_initialize(void) { /* Clear RTC_CR FMT, OSEL and POL Bits */ - regval = getreg32(STM32L4_RTC_CR); + regval = getreg32(STM32_RTC_CR); regval &= ~(RTC_CR_FMT | RTC_CR_OSEL_MASK | RTC_CR_POL); - putreg32(regval, STM32L4_RTC_CR); + putreg32(regval, STM32_RTC_CR); /* Configure RTC pre-scaler with the required values */ -#ifdef CONFIG_STM32L4_RTC_HSECLOCK +#ifdef CONFIG_STM32_RTC_HSECLOCK /* The HSE is divided by 32 prior to the prescaler we set here. * 1953 * NOTE: max HSE/32 is 4 MHz if it is to be used with RTC @@ -930,21 +930,21 @@ int up_rtc_initialize(void) putreg32(((uint32_t)7812 << RTC_PRER_PREDIV_S_SHIFT) | ((uint32_t)0x7f << RTC_PRER_PREDIV_A_SHIFT), - STM32L4_RTC_PRER); -#elif defined(CONFIG_STM32L4_RTC_LSICLOCK) + STM32_RTC_PRER); +#elif defined(CONFIG_STM32_RTC_LSICLOCK) /* Suitable values for 32.000 KHz LSI clock (29.5 - 34 KHz, * though) */ putreg32(((uint32_t)0xf9 << RTC_PRER_PREDIV_S_SHIFT) | ((uint32_t)0x7f << RTC_PRER_PREDIV_A_SHIFT), - STM32L4_RTC_PRER); -#else /* defined(CONFIG_STM32L4_RTC_LSECLOCK) */ + STM32_RTC_PRER); +#else /* defined(CONFIG_STM32_RTC_LSECLOCK) */ /* Correct values for 32.768 KHz LSE clock */ putreg32(((uint32_t)0xff << RTC_PRER_PREDIV_S_SHIFT) | ((uint32_t)0x7f << RTC_PRER_PREDIV_A_SHIFT), - STM32L4_RTC_PRER); + STM32_RTC_PRER); #endif /* Exit Initialization mode */ @@ -969,7 +969,7 @@ int up_rtc_initialize(void) * RTC backup data registers and backup SRAM). */ - stm32l4_pwr_enablebkp(false); + stm32_pwr_enablebkp(false); } } else @@ -978,7 +978,7 @@ int up_rtc_initialize(void) * backup data registers and backup SRAM). */ - stm32l4_pwr_enablebkp(true); + stm32_pwr_enablebkp(true); /* Write protection for RTC registers does not need to be disabled. */ @@ -988,7 +988,7 @@ int up_rtc_initialize(void) * data registers and backup SRAM). */ - stm32l4_pwr_enablebkp(false); + stm32_pwr_enablebkp(false); } g_rtc_enabled = true; @@ -998,7 +998,7 @@ int up_rtc_initialize(void) } /**************************************************************************** - * Name: stm32l4_rtc_getdatetime_with_subseconds + * Name: stm32_rtc_getdatetime_with_subseconds * * Description: * Get the current date and time from the date/time RTC. This interface @@ -1018,10 +1018,10 @@ int up_rtc_initialize(void) * ****************************************************************************/ -int stm32l4_rtc_getdatetime_with_subseconds(struct tm *tp, +int stm32_rtc_getdatetime_with_subseconds(struct tm *tp, long *nsec) { -#ifdef CONFIG_STM32L4_HAVE_RTC_SUBSECONDS +#ifdef CONFIG_STM32_HAVE_RTC_SUBSECONDS uint32_t ssr; #endif uint32_t dr; @@ -1038,18 +1038,18 @@ int stm32l4_rtc_getdatetime_with_subseconds(struct tm *tp, do { - dr = getreg32(STM32L4_RTC_DR); - tr = getreg32(STM32L4_RTC_TR); -#ifdef CONFIG_STM32L4_HAVE_RTC_SUBSECONDS - ssr = getreg32(STM32L4_RTC_SSR); - tmp = getreg32(STM32L4_RTC_TR); + dr = getreg32(STM32_RTC_DR); + tr = getreg32(STM32_RTC_TR); +#ifdef CONFIG_STM32_HAVE_RTC_SUBSECONDS + ssr = getreg32(STM32_RTC_SSR); + tmp = getreg32(STM32_RTC_TR); if (tmp != tr) { continue; } #endif - tmp = getreg32(STM32L4_RTC_DR); + tmp = getreg32(STM32_RTC_DR); if (tmp == dr) { break; @@ -1102,13 +1102,13 @@ int stm32l4_rtc_getdatetime_with_subseconds(struct tm *tp, * of nsec has been provided to receive the sub-second value. */ -#ifdef CONFIG_STM32L4_HAVE_RTC_SUBSECONDS +#ifdef CONFIG_STM32_HAVE_RTC_SUBSECONDS if (nsec) { uint32_t prediv_s; uint32_t usecs; - prediv_s = getreg32(STM32L4_RTC_PRER) & RTC_PRER_PREDIV_S_MASK; + prediv_s = getreg32(STM32_RTC_PRER) & RTC_PRER_PREDIV_S_MASK; prediv_s >>= RTC_PRER_PREDIV_S_SHIFT; ssr &= RTC_SSR_MASK; @@ -1153,7 +1153,7 @@ int stm32l4_rtc_getdatetime_with_subseconds(struct tm *tp, int up_rtc_getdatetime(struct tm *tp) { - return stm32l4_rtc_getdatetime_with_subseconds(tp, NULL); + return stm32_rtc_getdatetime_with_subseconds(tp, NULL); } /**************************************************************************** @@ -1182,17 +1182,17 @@ int up_rtc_getdatetime(struct tm *tp) ****************************************************************************/ #ifdef CONFIG_ARCH_HAVE_RTC_SUBSECONDS -# ifndef CONFIG_STM32L4_HAVE_RTC_SUBSECONDS -# error "Invalid config, enable CONFIG_STM32L4_HAVE_RTC_SUBSECONDS." +# ifndef CONFIG_STM32_HAVE_RTC_SUBSECONDS +# error "Invalid config, enable CONFIG_STM32_HAVE_RTC_SUBSECONDS." # endif int up_rtc_getdatetime_with_subseconds(struct tm *tp, long *nsec) { - return stm32l4_rtc_getdatetime_with_subseconds(tp, nsec); + return stm32_rtc_getdatetime_with_subseconds(tp, nsec); } #endif /**************************************************************************** - * Name: stm32l4_rtc_setdatetime + * Name: stm32_rtc_setdatetime * * Description: * Set the RTC to the provided time. RTC implementations which provide @@ -1207,7 +1207,7 @@ int up_rtc_getdatetime_with_subseconds(struct tm *tp, long *nsec) * ****************************************************************************/ -int stm32l4_rtc_setdatetime(const struct tm *tp) +int stm32_rtc_setdatetime(const struct tm *tp) { uint32_t tr; uint32_t dr; @@ -1255,8 +1255,8 @@ int stm32l4_rtc_setdatetime(const struct tm *tp) { /* Set the RTC TR and DR registers */ - putreg32(tr, STM32L4_RTC_TR); - putreg32(dr, STM32L4_RTC_DR); + putreg32(tr, STM32_RTC_TR); + putreg32(dr, STM32_RTC_DR); /* Exit Initialization mode and wait for the RTC Time and Date * registers to be synchronized with RTC APB clock. @@ -1270,9 +1270,9 @@ int stm32l4_rtc_setdatetime(const struct tm *tp) if (getreg32(RTC_MAGIC_REG) != RTC_MAGIC_TIME_SET) { - stm32l4_pwr_enablebkp(true); + stm32_pwr_enablebkp(true); putreg32(RTC_MAGIC_TIME_SET, RTC_MAGIC_REG); - stm32l4_pwr_enablebkp(false); + stm32_pwr_enablebkp(false); } /* Re-enable the write protection for RTC registers */ @@ -1283,7 +1283,7 @@ int stm32l4_rtc_setdatetime(const struct tm *tp) } /**************************************************************************** - * Name: stm32l4_rtc_havesettime + * Name: stm32_rtc_havesettime * * Description: * Check if RTC time has been set. @@ -1293,7 +1293,7 @@ int stm32l4_rtc_setdatetime(const struct tm *tp) * ****************************************************************************/ -bool stm32l4_rtc_havesettime(void) +bool stm32_rtc_havesettime(void) { return getreg32(RTC_MAGIC_REG) == RTC_MAGIC_TIME_SET; } @@ -1322,11 +1322,11 @@ int up_rtc_settime(const struct timespec *tp) */ gmtime_r(&tp->tv_sec, &newtime); - return stm32l4_rtc_setdatetime(&newtime); + return stm32_rtc_setdatetime(&newtime); } /**************************************************************************** - * Name: stm32l4_rtc_setalarm + * Name: stm32_rtc_setalarm * * Description: * Set an alarm to an absolute time using associated hardware. @@ -1340,7 +1340,7 @@ int up_rtc_settime(const struct timespec *tp) ****************************************************************************/ #ifdef CONFIG_RTC_ALARM -int stm32l4_rtc_setalarm(struct alm_setalarm_s *alminfo) +int stm32_rtc_setalarm(struct alm_setalarm_s *alminfo) { struct alm_cbinfo_s *cbinfo; rtc_alarmreg_t alarmreg; @@ -1415,7 +1415,7 @@ int stm32l4_rtc_setalarm(struct alm_setalarm_s *alminfo) #endif /**************************************************************************** - * Name: stm32l4_rtc_cancelalarm + * Name: stm32_rtc_cancelalarm * * Description: * Cancel an alarm. @@ -1429,7 +1429,7 @@ int stm32l4_rtc_setalarm(struct alm_setalarm_s *alminfo) ****************************************************************************/ #ifdef CONFIG_RTC_ALARM -int stm32l4_rtc_cancelalarm(enum alm_id_e alarmid) +int stm32_rtc_cancelalarm(enum alm_id_e alarmid) { int ret = -EINVAL; @@ -1452,7 +1452,7 @@ int stm32l4_rtc_cancelalarm(enum alm_id_e alarmid) /* Disable RTC alarm and interrupt */ - modifyreg32(STM32L4_RTC_CR, (RTC_CR_ALRAE | RTC_CR_ALRAIE), 0); + modifyreg32(STM32_RTC_CR, (RTC_CR_ALRAE | RTC_CR_ALRAIE), 0); ret = rtchw_check_alrawf(); if (ret < 0) @@ -1462,8 +1462,8 @@ int stm32l4_rtc_cancelalarm(enum alm_id_e alarmid) /* Unset the alarm */ - putreg32(-1, STM32L4_RTC_ALRMAR); - modifyreg32(STM32L4_RTC_ISR, RTC_ISR_ALRAF, 0); + putreg32(-1, STM32_RTC_ALRMAR); + modifyreg32(STM32_RTC_ISR, RTC_ISR_ALRAF, 0); rtc_wprlock(); ret = OK; } @@ -1483,7 +1483,7 @@ int stm32l4_rtc_cancelalarm(enum alm_id_e alarmid) /* Disable RTC alarm and interrupt */ - modifyreg32(STM32L4_RTC_CR, (RTC_CR_ALRBE | RTC_CR_ALRBIE), 0); + modifyreg32(STM32_RTC_CR, (RTC_CR_ALRBE | RTC_CR_ALRBIE), 0); ret = rtchw_check_alrbwf(); if (ret < 0) @@ -1493,8 +1493,8 @@ int stm32l4_rtc_cancelalarm(enum alm_id_e alarmid) /* Unset the alarm */ - putreg32(-1, STM32L4_RTC_ALRMBR); - modifyreg32(STM32L4_RTC_ISR, RTC_ISR_ALRBF, 0); + putreg32(-1, STM32_RTC_ALRMBR); + modifyreg32(STM32_RTC_ISR, RTC_ISR_ALRBF, 0); rtc_wprlock(); ret = OK; } @@ -1515,7 +1515,7 @@ int stm32l4_rtc_cancelalarm(enum alm_id_e alarmid) #endif /**************************************************************************** - * Name: stm32l4_rtc_rdalarm + * Name: stm32_rtc_rdalarm * * Description: * Query an alarm configured in hardware. @@ -1529,7 +1529,7 @@ int stm32l4_rtc_cancelalarm(enum alm_id_e alarmid) ****************************************************************************/ #ifdef CONFIG_RTC_ALARM -int stm32l4_rtc_rdalarm(struct alm_rdalarm_s *alminfo) +int stm32_rtc_rdalarm(struct alm_rdalarm_s *alminfo) { rtc_alarmreg_t alarmreg; int ret = -EINVAL; @@ -1541,8 +1541,8 @@ int stm32l4_rtc_rdalarm(struct alm_rdalarm_s *alminfo) { case RTC_ALARMA: { - alarmreg = STM32L4_RTC_ALRMAR; - ret = stm32l4_rtc_getalarmdatetime(alarmreg, + alarmreg = STM32_RTC_ALRMAR; + ret = stm32_rtc_getalarmdatetime(alarmreg, (struct tm *)alminfo->ar_time); } break; @@ -1550,8 +1550,8 @@ int stm32l4_rtc_rdalarm(struct alm_rdalarm_s *alminfo) #if CONFIG_RTC_NALARMS > 1 case RTC_ALARMB: { - alarmreg = STM32L4_RTC_ALRMBR; - ret = stm32l4_rtc_getalarmdatetime(alarmreg, + alarmreg = STM32_RTC_ALRMBR; + ret = stm32_rtc_getalarmdatetime(alarmreg, (struct tm *)alminfo->ar_time); } break; @@ -1567,7 +1567,7 @@ int stm32l4_rtc_rdalarm(struct alm_rdalarm_s *alminfo) #endif /**************************************************************************** - * Name: stm32l4_rtc_wakeup_handler + * Name: stm32_rtc_wakeup_handler * * Description: * RTC WAKEUP interrupt service routine through the EXTI line @@ -1581,18 +1581,18 @@ int stm32l4_rtc_rdalarm(struct alm_rdalarm_s *alminfo) ****************************************************************************/ #ifdef CONFIG_RTC_PERIODIC -static int stm32l4_rtc_wakeup_handler(int irq, void *context, +static int stm32_rtc_wakeup_handler(int irq, void *context, void *arg) { uint32_t regval = 0; - stm32l4_pwr_enablebkp(true); + stm32_pwr_enablebkp(true); - regval = getreg32(STM32L4_RTC_ISR); + regval = getreg32(STM32_RTC_ISR); regval &= ~RTC_ISR_WUTF; - putreg32(regval, STM32L4_RTC_ISR); + putreg32(regval, STM32_RTC_ISR); - stm32l4_pwr_enablebkp(false); + stm32_pwr_enablebkp(false); if (g_wakeupcb != NULL) { @@ -1616,7 +1616,7 @@ static inline void rtc_enable_wakeup(void) { if (!g_wakeup_enabled) { - stm32l4_exti_wakeup(true, false, true, stm32l4_rtc_wakeup_handler, + stm32_exti_wakeup(true, false, true, stm32_rtc_wakeup_handler, NULL); g_wakeup_enabled = true; } @@ -1636,15 +1636,15 @@ static inline void rtc_set_wcksel(unsigned int wucksel) { uint32_t regval = 0; - regval = getreg32(STM32L4_RTC_CR); + regval = getreg32(STM32_RTC_CR); regval &= ~RTC_CR_WUCKSEL_MASK; regval |= wucksel; - putreg32(regval, STM32L4_RTC_CR); + putreg32(regval, STM32_RTC_CR); } #endif /**************************************************************************** - * Name: stm32l4_rtc_setperiodic + * Name: stm32_rtc_setperiodic * * Description: * Set a periodic RTC wakeup @@ -1659,7 +1659,7 @@ static inline void rtc_set_wcksel(unsigned int wucksel) ****************************************************************************/ #ifdef CONFIG_RTC_PERIODIC -int stm32l4_rtc_setperiodic(const struct timespec *period, +int stm32_rtc_setperiodic(const struct timespec *period, wakeupcb_t callback) { unsigned int wutr_val; @@ -1669,13 +1669,13 @@ int stm32l4_rtc_setperiodic(const struct timespec *period, uint32_t secs; uint32_t millisecs; -#if defined(CONFIG_STM32L4_RTC_HSECLOCK) +#if defined(CONFIG_STM32_RTC_HSECLOCK) # error "Periodic wakeup not available for HSE" -#elif defined(CONFIG_STM32L4_RTC_LSICLOCK) +#elif defined(CONFIG_STM32_RTC_LSICLOCK) # error "Periodic wakeup not available for LSI (and it is too inaccurate!)" -#elif defined(CONFIG_STM32L4_RTC_LSECLOCK) +#elif defined(CONFIG_STM32_RTC_LSECLOCK) const uint32_t rtc_div16_max_msecs = 16 * 1000 * 0xffffu / - STM32L4_LSE_FREQUENCY; + STM32_LSE_FREQUENCY; #else # error "No clock for RTC!" #endif @@ -1713,9 +1713,9 @@ int stm32l4_rtc_setperiodic(const struct timespec *period, /* Clear WUTE in RTC_CR to disable the wakeup timer */ - regval = getreg32(STM32L4_RTC_CR); + regval = getreg32(STM32_RTC_CR); regval &= ~RTC_CR_WUTE; - putreg32(regval, STM32L4_RTC_CR); + putreg32(regval, STM32_RTC_CR); /* Poll WUTWF until it is set in RTC_ISR (takes around 2 RTCCLK * clock cycles) @@ -1724,7 +1724,7 @@ int stm32l4_rtc_setperiodic(const struct timespec *period, ret = -ETIMEDOUT; for (timeout = 0; timeout < SYNCHRO_TIMEOUT; timeout++) { - regval = getreg32(STM32L4_RTC_ISR); + regval = getreg32(STM32_RTC_ISR); if ((regval & RTC_ISR_WUTWF) != 0) { /* Synchronized */ @@ -1748,7 +1748,7 @@ int stm32l4_rtc_setperiodic(const struct timespec *period, /* Get number of ticks. */ - ticks = millisecs * STM32L4_LSE_FREQUENCY / (16 * 1000); + ticks = millisecs * STM32_LSE_FREQUENCY / (16 * 1000); /* Wake-up is after WUT+1 ticks. */ @@ -1769,17 +1769,17 @@ int stm32l4_rtc_setperiodic(const struct timespec *period, * selection. */ - putreg32(wutr_val, STM32L4_RTC_WUTR); + putreg32(wutr_val, STM32_RTC_WUTR); - regval = getreg32(STM32L4_RTC_CR); + regval = getreg32(STM32_RTC_CR); regval |= RTC_CR_WUTIE | RTC_CR_WUTE; - putreg32(regval, STM32L4_RTC_CR); + putreg32(regval, STM32_RTC_CR); /* Just in case resets the WUTF flag in RTC_ISR */ - regval = getreg32(STM32L4_RTC_ISR); + regval = getreg32(STM32_RTC_ISR); regval &= ~RTC_ISR_WUTF; - putreg32(regval, STM32L4_RTC_ISR); + putreg32(regval, STM32_RTC_ISR); rtc_wprlock(); @@ -1788,7 +1788,7 @@ int stm32l4_rtc_setperiodic(const struct timespec *period, #endif /**************************************************************************** - * Name: stm32l4_rtc_cancelperiodic + * Name: stm32_rtc_cancelperiodic * * Description: * Cancel a periodic wakeup @@ -1801,7 +1801,7 @@ int stm32l4_rtc_setperiodic(const struct timespec *period, ****************************************************************************/ #ifdef CONFIG_RTC_PERIODIC -int stm32l4_rtc_cancelperiodic(void) +int stm32_rtc_cancelperiodic(void) { int ret = OK; int timeout = 0; @@ -1811,9 +1811,9 @@ int stm32l4_rtc_cancelperiodic(void) /* Clear WUTE and WUTIE in RTC_CR to disable the wakeup timer */ - regval = getreg32(STM32L4_RTC_CR); + regval = getreg32(STM32_RTC_CR); regval &= ~(RTC_CR_WUTE | RTC_CR_WUTIE); - putreg32(regval, STM32L4_RTC_CR); + putreg32(regval, STM32_RTC_CR); /* Poll WUTWF until it is set in RTC_ISR (takes around 2 RTCCLK * clock cycles) @@ -1822,7 +1822,7 @@ int stm32l4_rtc_cancelperiodic(void) ret = -ETIMEDOUT; for (timeout = 0; timeout < SYNCHRO_TIMEOUT; timeout++) { - regval = getreg32(STM32L4_RTC_ISR); + regval = getreg32(STM32_RTC_ISR); if ((regval & RTC_ISR_WUTWF) != 0) { /* Synchronized */ @@ -1834,9 +1834,9 @@ int stm32l4_rtc_cancelperiodic(void) /* Clears RTC_WUTR register */ - regval = getreg32(STM32L4_RTC_WUTR); + regval = getreg32(STM32_RTC_WUTR); regval &= ~RTC_WUTR_MASK; - putreg32(regval, STM32L4_RTC_WUTR); + putreg32(regval, STM32_RTC_WUTR); rtc_wprlock(); @@ -1844,4 +1844,4 @@ int stm32l4_rtc_cancelperiodic(void) } #endif -#endif /* CONFIG_STM32L4_RTC */ +#endif /* CONFIG_STM32_RTC */ diff --git a/arch/arm/src/stm32l4/stm32l4_rtc.h b/arch/arm/src/stm32l4/stm32l4_rtc.h index b89807b7c0768..af354a7bd7d72 100644 --- a/arch/arm/src/stm32l4/stm32l4_rtc.h +++ b/arch/arm/src/stm32l4/stm32l4_rtc.h @@ -38,24 +38,24 @@ * Pre-processor Definitions ****************************************************************************/ -#define STM32L4_RTC_PRESCALER_SECOND 32767 /* Default prescaler to get a second base */ -#define STM32L4_RTC_PRESCALER_MIN 1 /* Maximum speed of 16384 Hz */ +#define STM32_RTC_PRESCALER_SECOND 32767 /* Default prescaler to get a second base */ +#define STM32_RTC_PRESCALER_MIN 1 /* Maximum speed of 16384 Hz */ -#if !defined(CONFIG_STM32L4_RTC_MAGIC) -# define CONFIG_STM32L4_RTC_MAGIC (0xfacefeee) +#if !defined(CONFIG_STM32_RTC_MAGIC) +# define CONFIG_STM32_RTC_MAGIC (0xfacefeee) #endif -#if !defined(CONFIG_STM32L4_RTC_MAGIC_TIME_SET) -# define CONFIG_STM32L4_RTC_MAGIC_TIME_SET (0xf00dface) +#if !defined(CONFIG_STM32_RTC_MAGIC_TIME_SET) +# define CONFIG_STM32_RTC_MAGIC_TIME_SET (0xf00dface) #endif -#if !defined(CONFIG_STM32L4_RTC_MAGIC_REG) -# define CONFIG_STM32L4_RTC_MAGIC_REG (0) +#if !defined(CONFIG_STM32_RTC_MAGIC_REG) +# define CONFIG_STM32_RTC_MAGIC_REG (0) #endif -#define RTC_MAGIC CONFIG_STM32L4_RTC_MAGIC -#define RTC_MAGIC_TIME_SET CONFIG_STM32L4_RTC_MAGIC_TIME_SET -#define RTC_MAGIC_REG STM32L4_RTC_BKR(CONFIG_STM32L4_RTC_MAGIC_REG) +#define RTC_MAGIC CONFIG_STM32_RTC_MAGIC +#define RTC_MAGIC_TIME_SET CONFIG_STM32_RTC_MAGIC_TIME_SET +#define RTC_MAGIC_REG STM32_RTC_BKR(CONFIG_STM32_RTC_MAGIC_REG) /**************************************************************************** * Public Types @@ -118,7 +118,7 @@ extern "C" ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_rtc_is_initialized + * Name: stm32_rtc_is_initialized * * Description: * Returns 'true' if the RTC has been initialized @@ -133,10 +133,10 @@ extern "C" * ****************************************************************************/ -bool stm32l4_rtc_is_initialized(void); +bool stm32_rtc_is_initialized(void); /**************************************************************************** - * Name: stm32l4_rtc_getdatetime_with_subseconds + * Name: stm32_rtc_getdatetime_with_subseconds * * Description: * Get the current date and time from the date/time RTC. This interface @@ -156,13 +156,13 @@ bool stm32l4_rtc_is_initialized(void); * ****************************************************************************/ -#ifdef CONFIG_STM32L4_HAVE_RTC_SUBSECONDS -int stm32l4_rtc_getdatetime_with_subseconds(struct tm *tp, +#ifdef CONFIG_STM32_HAVE_RTC_SUBSECONDS +int stm32_rtc_getdatetime_with_subseconds(struct tm *tp, long *nsec); #endif /**************************************************************************** - * Name: stm32l4_rtc_setdatetime + * Name: stm32_rtc_setdatetime * * Description: * Set the RTC to the provided time. RTC implementations which provide @@ -179,11 +179,11 @@ int stm32l4_rtc_getdatetime_with_subseconds(struct tm *tp, #ifdef CONFIG_RTC_DATETIME struct tm; -int stm32l4_rtc_setdatetime(const struct tm *tp); +int stm32_rtc_setdatetime(const struct tm *tp); #endif /**************************************************************************** - * Name: stm32l4_rtc_havesettime + * Name: stm32_rtc_havesettime * * Description: * Check if RTC time has been set. @@ -193,11 +193,11 @@ int stm32l4_rtc_setdatetime(const struct tm *tp); * ****************************************************************************/ -bool stm32l4_rtc_havesettime(void); +bool stm32_rtc_havesettime(void); #ifdef CONFIG_RTC_ALARM /**************************************************************************** - * Name: stm32l4_rtc_setalarm + * Name: stm32_rtc_setalarm * * Description: * Set an alarm to an absolute time using associated hardware. @@ -210,10 +210,10 @@ bool stm32l4_rtc_havesettime(void); * ****************************************************************************/ -int stm32l4_rtc_setalarm(struct alm_setalarm_s *alminfo); +int stm32_rtc_setalarm(struct alm_setalarm_s *alminfo); /**************************************************************************** - * Name: stm32l4_rtc_rdalarm + * Name: stm32_rtc_rdalarm * * Description: * Query an alarm configured in hardware. @@ -226,10 +226,10 @@ int stm32l4_rtc_setalarm(struct alm_setalarm_s *alminfo); * ****************************************************************************/ -int stm32l4_rtc_rdalarm(struct alm_rdalarm_s *alminfo); +int stm32_rtc_rdalarm(struct alm_rdalarm_s *alminfo); /**************************************************************************** - * Name: stm32l4_rtc_cancelalarm + * Name: stm32_rtc_cancelalarm * * Description: * Cancel an alarm. @@ -242,13 +242,13 @@ int stm32l4_rtc_rdalarm(struct alm_rdalarm_s *alminfo); * ****************************************************************************/ -int stm32l4_rtc_cancelalarm(enum alm_id_e alarmid); +int stm32_rtc_cancelalarm(enum alm_id_e alarmid); #endif /* CONFIG_RTC_ALARM */ #ifdef CONFIG_RTC_PERIODIC /**************************************************************************** - * Name: stm32l4_rtc_setperiodic + * Name: stm32_rtc_setperiodic * * Description: * Set a periodic RTC wakeup @@ -262,11 +262,11 @@ int stm32l4_rtc_cancelalarm(enum alm_id_e alarmid); * ****************************************************************************/ -int stm32l4_rtc_setperiodic(const struct timespec *period, +int stm32_rtc_setperiodic(const struct timespec *period, wakeupcb_t callback); /**************************************************************************** - * Name: stm32l4_rtc_cancelperiodic + * Name: stm32_rtc_cancelperiodic * * Description: * Cancel a periodic wakeup @@ -278,11 +278,11 @@ int stm32l4_rtc_setperiodic(const struct timespec *period, * ****************************************************************************/ -int stm32l4_rtc_cancelperiodic(void); +int stm32_rtc_cancelperiodic(void); #endif /* CONFIG_RTC_PERIODIC */ /**************************************************************************** - * Name: stm32l4_rtc_lowerhalf + * Name: stm32_rtc_lowerhalf * * Description: * Instantiate the RTC lower half driver for the STM32L4. General usage: @@ -291,7 +291,7 @@ int stm32l4_rtc_cancelperiodic(void); * #include "stm32l4_rtc.h> * * struct rtc_lowerhalf_s *lower; - * lower = stm32l4_rtc_lowerhalf(); + * lower = stm32_rtc_lowerhalf(); * rtc_initialize(0, lower); * * Input Parameters: @@ -305,7 +305,7 @@ int stm32l4_rtc_cancelperiodic(void); #ifdef CONFIG_RTC_DRIVER struct rtc_lowerhalf_s; -struct rtc_lowerhalf_s *stm32l4_rtc_lowerhalf(void); +struct rtc_lowerhalf_s *stm32_rtc_lowerhalf(void); #endif #undef EXTERN diff --git a/arch/arm/src/stm32l4/stm32l4_rtc_lowerhalf.c b/arch/arm/src/stm32l4/stm32l4_rtc_lowerhalf.c index bac80beef62f9..0d87286eb681e 100644 --- a/arch/arm/src/stm32l4/stm32l4_rtc_lowerhalf.c +++ b/arch/arm/src/stm32l4/stm32l4_rtc_lowerhalf.c @@ -45,14 +45,14 @@ * Pre-processor Definitions ****************************************************************************/ -#define STM32L4_NALARMS 2 +#define STM32_NALARMS 2 /**************************************************************************** * Private Types ****************************************************************************/ #ifdef CONFIG_RTC_ALARM -struct stm32l4_cbinfo_s +struct stm32_cbinfo_s { volatile rtc_alarm_callback_t cb; /* Callback when the alarm expires */ volatile void *priv; /* Private argument to accompany callback */ @@ -64,7 +64,7 @@ struct stm32l4_cbinfo_s * with struct rtc_lowerhalf_s. */ -struct stm32l4_lowerhalf_s +struct stm32_lowerhalf_s { /* This is the contained reference to the read-only, lower-half * operations vtable (which may lie in FLASH or ROM) @@ -81,7 +81,7 @@ struct stm32l4_lowerhalf_s #ifdef CONFIG_RTC_ALARM /* Alarm callback information */ - struct stm32l4_cbinfo_s cbinfo[STM32L4_NALARMS]; + struct stm32_cbinfo_s cbinfo[STM32_NALARMS]; #endif #ifdef CONFIG_RTC_PERIODIC @@ -97,30 +97,30 @@ struct stm32l4_lowerhalf_s /* Prototypes for static methods in struct rtc_ops_s */ -static int stm32l4_rdtime(struct rtc_lowerhalf_s *lower, +static int stm32_rdtime(struct rtc_lowerhalf_s *lower, struct rtc_time *rtctime); -static int stm32l4_settime(struct rtc_lowerhalf_s *lower, +static int stm32_settime(struct rtc_lowerhalf_s *lower, const struct rtc_time *rtctime); -static bool stm32l4_havesettime(struct rtc_lowerhalf_s *lower); +static bool stm32_havesettime(struct rtc_lowerhalf_s *lower); #ifdef CONFIG_RTC_ALARM -static int stm32l4_setalarm(struct rtc_lowerhalf_s *lower, +static int stm32_setalarm(struct rtc_lowerhalf_s *lower, const struct lower_setalarm_s *alarminfo); static int -stm32l4_setrelative(struct rtc_lowerhalf_s *lower, +stm32_setrelative(struct rtc_lowerhalf_s *lower, const struct lower_setrelative_s *alarminfo); -static int stm32l4_cancelalarm(struct rtc_lowerhalf_s *lower, +static int stm32_cancelalarm(struct rtc_lowerhalf_s *lower, int alarmid); -static int stm32l4_rdalarm(struct rtc_lowerhalf_s *lower, +static int stm32_rdalarm(struct rtc_lowerhalf_s *lower, struct lower_rdalarm_s *alarminfo); #endif #ifdef CONFIG_RTC_PERIODIC static int -stm32l4_setperiodic(struct rtc_lowerhalf_s *lower, +stm32_setperiodic(struct rtc_lowerhalf_s *lower, const struct lower_setperiodic_s *alarminfo); static int -stm32l4_cancelperiodic(struct rtc_lowerhalf_s *lower, int id); +stm32_cancelperiodic(struct rtc_lowerhalf_s *lower, int id); #endif /**************************************************************************** @@ -131,24 +131,24 @@ stm32l4_cancelperiodic(struct rtc_lowerhalf_s *lower, int id); static const struct rtc_ops_s g_rtc_ops = { - .rdtime = stm32l4_rdtime, - .settime = stm32l4_settime, - .havesettime = stm32l4_havesettime, + .rdtime = stm32_rdtime, + .settime = stm32_settime, + .havesettime = stm32_havesettime, #ifdef CONFIG_RTC_ALARM - .setalarm = stm32l4_setalarm, - .setrelative = stm32l4_setrelative, - .cancelalarm = stm32l4_cancelalarm, - .rdalarm = stm32l4_rdalarm, + .setalarm = stm32_setalarm, + .setrelative = stm32_setrelative, + .cancelalarm = stm32_cancelalarm, + .rdalarm = stm32_rdalarm, #endif #ifdef CONFIG_RTC_PERIODIC - .setperiodic = stm32l4_setperiodic, - .cancelperiodic = stm32l4_cancelperiodic, + .setperiodic = stm32_setperiodic, + .cancelperiodic = stm32_cancelperiodic, #endif }; /* STM32L4 RTC device state */ -static struct stm32l4_lowerhalf_s g_rtc_lowerhalf = +static struct stm32_lowerhalf_s g_rtc_lowerhalf = { .ops = &g_rtc_ops, .devlock = NXMUTEX_INITIALIZER, @@ -159,7 +159,7 @@ static struct stm32l4_lowerhalf_s g_rtc_lowerhalf = ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_alarm_callback + * Name: stm32_alarm_callback * * Description: * This is the function that is called from the RTC driver when the alarm @@ -174,17 +174,17 @@ static struct stm32l4_lowerhalf_s g_rtc_lowerhalf = ****************************************************************************/ #ifdef CONFIG_RTC_ALARM -static void stm32l4_alarm_callback(void *arg, unsigned int alarmid) +static void stm32_alarm_callback(void *arg, unsigned int alarmid) { - struct stm32l4_lowerhalf_s *lower; - struct stm32l4_cbinfo_s *cbinfo; + struct stm32_lowerhalf_s *lower; + struct stm32_cbinfo_s *cbinfo; rtc_alarm_callback_t cb; void *priv; DEBUGASSERT(arg != NULL); DEBUGASSERT(alarmid == RTC_ALARMA || alarmid == RTC_ALARMB); - lower = (struct stm32l4_lowerhalf_s *)arg; + lower = (struct stm32_lowerhalf_s *)arg; cbinfo = &lower->cbinfo[alarmid]; /* Sample and clear the callback information to minimize the window in @@ -207,7 +207,7 @@ static void stm32l4_alarm_callback(void *arg, unsigned int alarmid) #endif /* CONFIG_RTC_ALARM */ /**************************************************************************** - * Name: stm32l4_rdtime + * Name: stm32_rdtime * * Description: * Implements the rdtime() method of the RTC driver interface @@ -222,13 +222,13 @@ static void stm32l4_alarm_callback(void *arg, unsigned int alarmid) * ****************************************************************************/ -static int stm32l4_rdtime(struct rtc_lowerhalf_s *lower, +static int stm32_rdtime(struct rtc_lowerhalf_s *lower, struct rtc_time *rtctime) { - struct stm32l4_lowerhalf_s *priv; + struct stm32_lowerhalf_s *priv; int ret; - priv = (struct stm32l4_lowerhalf_s *)lower; + priv = (struct stm32_lowerhalf_s *)lower; ret = nxmutex_lock(&priv->devlock); if (ret < 0) @@ -247,7 +247,7 @@ static int stm32l4_rdtime(struct rtc_lowerhalf_s *lower, } /**************************************************************************** - * Name: stm32l4_settime + * Name: stm32_settime * * Description: * Implements the settime() method of the RTC driver interface @@ -262,13 +262,13 @@ static int stm32l4_rdtime(struct rtc_lowerhalf_s *lower, * ****************************************************************************/ -static int stm32l4_settime(struct rtc_lowerhalf_s *lower, +static int stm32_settime(struct rtc_lowerhalf_s *lower, const struct rtc_time *rtctime) { - struct stm32l4_lowerhalf_s *priv; + struct stm32_lowerhalf_s *priv; int ret; - priv = (struct stm32l4_lowerhalf_s *)lower; + priv = (struct stm32_lowerhalf_s *)lower; ret = nxmutex_lock(&priv->devlock); if (ret < 0) @@ -280,14 +280,14 @@ static int stm32l4_settime(struct rtc_lowerhalf_s *lower, * compatible with struct tm. */ - ret = stm32l4_rtc_setdatetime((const struct tm *)rtctime); + ret = stm32_rtc_setdatetime((const struct tm *)rtctime); nxmutex_unlock(&priv->devlock); return ret; } /**************************************************************************** - * Name: stm32l4_havesettime + * Name: stm32_havesettime * * Description: * Implements the havesettime() method of the RTC driver interface @@ -300,13 +300,13 @@ static int stm32l4_settime(struct rtc_lowerhalf_s *lower, * ****************************************************************************/ -static bool stm32l4_havesettime(struct rtc_lowerhalf_s *lower) +static bool stm32_havesettime(struct rtc_lowerhalf_s *lower) { - return stm32l4_rtc_havesettime(); + return stm32_rtc_havesettime(); } /**************************************************************************** - * Name: stm32l4_setalarm + * Name: stm32_setalarm * * Description: * Set a new alarm. This function implements the setalarm() method of the @@ -323,11 +323,11 @@ static bool stm32l4_havesettime(struct rtc_lowerhalf_s *lower) ****************************************************************************/ #ifdef CONFIG_RTC_ALARM -static int stm32l4_setalarm(struct rtc_lowerhalf_s *lower, +static int stm32_setalarm(struct rtc_lowerhalf_s *lower, const struct lower_setalarm_s *alarminfo) { - struct stm32l4_lowerhalf_s *priv; - struct stm32l4_cbinfo_s *cbinfo; + struct stm32_lowerhalf_s *priv; + struct stm32_cbinfo_s *cbinfo; struct alm_setalarm_s lowerinfo; int ret; @@ -335,7 +335,7 @@ static int stm32l4_setalarm(struct rtc_lowerhalf_s *lower, DEBUGASSERT(lower != NULL && alarminfo != NULL); DEBUGASSERT(alarminfo->id == RTC_ALARMA || alarminfo->id == RTC_ALARMB); - priv = (struct stm32l4_lowerhalf_s *)lower; + priv = (struct stm32_lowerhalf_s *)lower; ret = nxmutex_lock(&priv->devlock); if (ret < 0) @@ -356,13 +356,13 @@ static int stm32l4_setalarm(struct rtc_lowerhalf_s *lower, /* Set the alarm */ lowerinfo.as_id = alarminfo->id; - lowerinfo.as_cb = stm32l4_alarm_callback; + lowerinfo.as_cb = stm32_alarm_callback; lowerinfo.as_arg = priv; memcpy(&lowerinfo.as_time, &alarminfo->time, sizeof(struct tm)); /* And set the alarm */ - ret = stm32l4_rtc_setalarm(&lowerinfo); + ret = stm32_rtc_setalarm(&lowerinfo); if (ret < 0) { cbinfo->cb = NULL; @@ -376,7 +376,7 @@ static int stm32l4_setalarm(struct rtc_lowerhalf_s *lower, #endif /**************************************************************************** - * Name: stm32l4_setrelative + * Name: stm32_setrelative * * Description: * Set a new alarm relative to the current time. This function implements @@ -394,7 +394,7 @@ static int stm32l4_setalarm(struct rtc_lowerhalf_s *lower, #ifdef CONFIG_RTC_ALARM static int -stm32l4_setrelative(struct rtc_lowerhalf_s *lower, +stm32_setrelative(struct rtc_lowerhalf_s *lower, const struct lower_setrelative_s *alarminfo) { struct lower_setalarm_s setalarm; @@ -440,7 +440,7 @@ stm32l4_setrelative(struct rtc_lowerhalf_s *lower, setalarm.cb = alarminfo->cb; setalarm.priv = alarminfo->priv; - ret = stm32l4_setalarm(lower, &setalarm); + ret = stm32_setalarm(lower, &setalarm); } leave_critical_section(flags); @@ -451,7 +451,7 @@ stm32l4_setrelative(struct rtc_lowerhalf_s *lower, #endif /**************************************************************************** - * Name: stm32l4_cancelalarm + * Name: stm32_cancelalarm * * Description: * Cancel the current alarm. This function implements the cancelalarm() @@ -468,16 +468,16 @@ stm32l4_setrelative(struct rtc_lowerhalf_s *lower, ****************************************************************************/ #ifdef CONFIG_RTC_ALARM -static int stm32l4_cancelalarm(struct rtc_lowerhalf_s *lower, +static int stm32_cancelalarm(struct rtc_lowerhalf_s *lower, int alarmid) { - struct stm32l4_lowerhalf_s *priv; - struct stm32l4_cbinfo_s *cbinfo; + struct stm32_lowerhalf_s *priv; + struct stm32_cbinfo_s *cbinfo; int ret; DEBUGASSERT(lower != NULL); DEBUGASSERT(alarmid == RTC_ALARMA || alarmid == RTC_ALARMB); - priv = (struct stm32l4_lowerhalf_s *)lower; + priv = (struct stm32_lowerhalf_s *)lower; ret = nxmutex_lock(&priv->devlock); if (ret < 0) @@ -498,7 +498,7 @@ static int stm32l4_cancelalarm(struct rtc_lowerhalf_s *lower, /* Then cancel the alarm */ - ret = stm32l4_rtc_cancelalarm((enum alm_id_e)alarmid); + ret = stm32_rtc_cancelalarm((enum alm_id_e)alarmid); } nxmutex_unlock(&priv->devlock); @@ -507,7 +507,7 @@ static int stm32l4_cancelalarm(struct rtc_lowerhalf_s *lower, #endif /**************************************************************************** - * Name: stm32l4_rdalarm + * Name: stm32_rdalarm * * Description: * Query the RTC alarm. @@ -523,7 +523,7 @@ static int stm32l4_cancelalarm(struct rtc_lowerhalf_s *lower, ****************************************************************************/ #ifdef CONFIG_RTC_ALARM -static int stm32l4_rdalarm(struct rtc_lowerhalf_s *lower, +static int stm32_rdalarm(struct rtc_lowerhalf_s *lower, struct lower_rdalarm_s *alarminfo) { struct alm_rdalarm_s lowerinfo; @@ -544,7 +544,7 @@ static int stm32l4_rdalarm(struct rtc_lowerhalf_s *lower, lowerinfo.ar_id = alarminfo->id; lowerinfo.ar_time = alarminfo->time; - ret = stm32l4_rtc_rdalarm(&lowerinfo); + ret = stm32_rtc_rdalarm(&lowerinfo); leave_critical_section(flags); } @@ -554,7 +554,7 @@ static int stm32l4_rdalarm(struct rtc_lowerhalf_s *lower, #endif /**************************************************************************** - * Name: stm32l4_periodic_callback + * Name: stm32_periodic_callback * * Description: * This is the function that is called from the RTC driver when the @@ -570,14 +570,14 @@ static int stm32l4_rdalarm(struct rtc_lowerhalf_s *lower, ****************************************************************************/ #ifdef CONFIG_RTC_PERIODIC -static int stm32l4_periodic_callback(void) +static int stm32_periodic_callback(void) { - struct stm32l4_lowerhalf_s *lower; + struct stm32_lowerhalf_s *lower; struct lower_setperiodic_s *cbinfo; rtc_wakeup_callback_t cb; void *priv; - lower = (struct stm32l4_lowerhalf_s *)&g_rtc_lowerhalf; + lower = (struct stm32_lowerhalf_s *)&g_rtc_lowerhalf; cbinfo = &lower->periodic; cb = (rtc_wakeup_callback_t)cbinfo->cb; @@ -595,7 +595,7 @@ static int stm32l4_periodic_callback(void) #endif /* CONFIG_RTC_PERIODIC */ /**************************************************************************** - * Name: stm32l4_setperiodic + * Name: stm32_setperiodic * * Description: * Set a new periodic wakeup relative to the current time, with a given @@ -614,14 +614,14 @@ static int stm32l4_periodic_callback(void) #ifdef CONFIG_RTC_PERIODIC static int -stm32l4_setperiodic(struct rtc_lowerhalf_s *lower, +stm32_setperiodic(struct rtc_lowerhalf_s *lower, const struct lower_setperiodic_s *alarminfo) { - struct stm32l4_lowerhalf_s *priv; + struct stm32_lowerhalf_s *priv; int ret; DEBUGASSERT(lower != NULL && alarminfo != NULL); - priv = (struct stm32l4_lowerhalf_s *)lower; + priv = (struct stm32_lowerhalf_s *)lower; ret = nxmutex_lock(&priv->devlock); if (ret < 0) @@ -630,8 +630,8 @@ stm32l4_setperiodic(struct rtc_lowerhalf_s *lower, } memcpy(&priv->periodic, alarminfo, sizeof(struct lower_setperiodic_s)); - ret = stm32l4_rtc_setperiodic(&alarminfo->period, - stm32l4_periodic_callback); + ret = stm32_rtc_setperiodic(&alarminfo->period, + stm32_periodic_callback); nxmutex_unlock(&priv->devlock); return ret; @@ -639,7 +639,7 @@ stm32l4_setperiodic(struct rtc_lowerhalf_s *lower, #endif /**************************************************************************** - * Name: stm32l4_cancelperiodic + * Name: stm32_cancelperiodic * * Description: * Cancel the current periodic wakeup activity. This function implements @@ -655,13 +655,13 @@ stm32l4_setperiodic(struct rtc_lowerhalf_s *lower, ****************************************************************************/ #ifdef CONFIG_RTC_PERIODIC -static int stm32l4_cancelperiodic(struct rtc_lowerhalf_s *lower, int id) +static int stm32_cancelperiodic(struct rtc_lowerhalf_s *lower, int id) { - struct stm32l4_lowerhalf_s *priv; + struct stm32_lowerhalf_s *priv; int ret; DEBUGASSERT(lower != NULL); - priv = (struct stm32l4_lowerhalf_s *)lower; + priv = (struct stm32_lowerhalf_s *)lower; DEBUGASSERT(id == 0); @@ -671,7 +671,7 @@ static int stm32l4_cancelperiodic(struct rtc_lowerhalf_s *lower, int id) return ret; } - ret = stm32l4_rtc_cancelperiodic(); + ret = stm32_rtc_cancelperiodic(); nxmutex_unlock(&priv->devlock); return ret; @@ -683,7 +683,7 @@ static int stm32l4_cancelperiodic(struct rtc_lowerhalf_s *lower, int id) ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_rtc_lowerhalf + * Name: stm32_rtc_lowerhalf * * Description: * Instantiate the RTC lower half driver for the STM32. General usage: @@ -692,7 +692,7 @@ static int stm32l4_cancelperiodic(struct rtc_lowerhalf_s *lower, int id) * #include "stm32l4_rtc.h> * * struct rtc_lowerhalf_s *lower; - * lower = stm32l4_rtc_lowerhalf(); + * lower = stm32_rtc_lowerhalf(); * rtc_initialize(0, lower); * * Input Parameters: @@ -704,7 +704,7 @@ static int stm32l4_cancelperiodic(struct rtc_lowerhalf_s *lower, int id) * ****************************************************************************/ -struct rtc_lowerhalf_s *stm32l4_rtc_lowerhalf(void) +struct rtc_lowerhalf_s *stm32_rtc_lowerhalf(void) { return (struct rtc_lowerhalf_s *)&g_rtc_lowerhalf; } diff --git a/arch/arm/src/stm32l4/stm32l4_sai.c b/arch/arm/src/stm32l4/stm32l4_sai.c index 5344b764b36ae..775cb3a429c64 100644 --- a/arch/arm/src/stm32l4/stm32l4_sai.c +++ b/arch/arm/src/stm32l4/stm32l4_sai.c @@ -63,7 +63,7 @@ #include "stm32l4_gpio.h" #include "stm32l4_sai.h" -#ifdef CONFIG_STM32L4_SAI +#ifdef CONFIG_STM32_SAI /**************************************************************************** * Pre-processor Definitions @@ -81,37 +81,37 @@ # error CONFIG_I2S required by this driver #endif -#ifdef CONFIG_STM32L4_SAI_POLLING +#ifdef CONFIG_STM32_SAI_POLLING # error "Polling SAI not yet supported" #endif -#ifdef CONFIG_STM32L4_SAI_INTERRUPTS +#ifdef CONFIG_STM32_SAI_INTERRUPTS # error "Interrupt driven SAI not yet supported" #endif -#ifndef CONFIG_STM32L4_SAI_DEFAULT_SAMPLERATE -# define CONFIG_STM32L4_SAI_DEFAULT_SAMPLERATE (48000) +#ifndef CONFIG_STM32_SAI_DEFAULT_SAMPLERATE +# define CONFIG_STM32_SAI_DEFAULT_SAMPLERATE (48000) #endif -#ifndef CONFIG_STM32L4_SAI_DEFAULT_DATALEN -# define CONFIG_STM32L4_SAI_DEFAULT_DATALEN (16) +#ifndef CONFIG_STM32_SAI_DEFAULT_DATALEN +# define CONFIG_STM32_SAI_DEFAULT_DATALEN (16) #endif -#ifndef CONFIG_STM32L4_SAI_MAXINFLIGHT -# define CONFIG_STM32L4_SAI_MAXINFLIGHT (16) +#ifndef CONFIG_STM32_SAI_MAXINFLIGHT +# define CONFIG_STM32_SAI_MAXINFLIGHT (16) #endif -#ifdef CONFIG_STM32L4_SAI_DMA +#ifdef CONFIG_STM32_SAI_DMA /* SAI DMA priority */ -# if defined(CONFIG_STM32L4_SAI_DMAPRIO) -# define SAI_DMA_PRIO CONFIG_STM32L4_SAI_DMAPRIO +# if defined(CONFIG_STM32_SAI_DMAPRIO) +# define SAI_DMA_PRIO CONFIG_STM32_SAI_DMAPRIO # else # define SAI_DMA_PRIO DMA_CCR_PRIMED # endif # if (SAI_DMA_PRIO & ~DMA_CCR_PL_MASK) != 0 -# error "Illegal value for CONFIG_STM32L4_SAI_DMAPRIO" +# error "Illegal value for CONFIG_STM32_SAI_DMAPRIO" # endif /* DMA channel configuration */ @@ -142,14 +142,14 @@ struct sai_buffer_s /* The state of the one SAI peripheral */ -struct stm32l4_sai_s +struct stm32_sai_s { struct i2s_dev_s dev; /* Externally visible I2S interface */ uintptr_t base; /* SAI block register base address */ mutex_t lock; /* Assures mutually exclusive access to SAI */ uint32_t frequency; /* SAI clock frequency */ uint32_t syncen; /* Synchronization setting */ -#ifdef CONFIG_STM32L4_SAI_DMA +#ifdef CONFIG_STM32_SAI_DMA uint16_t dma_ch; /* DMA channel number */ DMA_HANDLE dma; /* DMA channel handle */ uint32_t dma_ccr; /* DMA control register */ @@ -168,7 +168,7 @@ struct stm32l4_sai_s sem_t bufsem; /* Buffer wait semaphore */ struct sai_buffer_s *freelist; /* A list a free buffer containers */ - struct sai_buffer_s containers[CONFIG_STM32L4_SAI_MAXINFLIGHT]; + struct sai_buffer_s containers[CONFIG_STM32_SAI_MAXINFLIGHT]; }; /**************************************************************************** @@ -176,7 +176,7 @@ struct stm32l4_sai_s ****************************************************************************/ #ifdef CONFIG_DEBUG_I2S_INFO -static void sai_dump_regs(struct stm32l4_sai_s *priv, const char *msg); +static void sai_dump_regs(struct stm32_sai_s *priv, const char *msg); #else # define sai_dump_regs(s,m) #endif @@ -184,15 +184,15 @@ static void sai_dump_regs(struct stm32l4_sai_s *priv, const char *msg); /* Buffer container helpers */ static struct sai_buffer_s * - sai_buf_allocate(struct stm32l4_sai_s *priv); -static void sai_buf_free(struct stm32l4_sai_s *priv, + sai_buf_allocate(struct stm32_sai_s *priv); +static void sai_buf_free(struct stm32_sai_s *priv, struct sai_buffer_s *bfcontainer); -static void sai_buf_initialize(struct stm32l4_sai_s *priv); +static void sai_buf_initialize(struct stm32_sai_s *priv); /* DMA support */ -#ifdef CONFIG_STM32L4_SAI_DMA -static void sai_schedule(struct stm32l4_sai_s *priv, int result); +#ifdef CONFIG_STM32_SAI_DMA +static void sai_schedule(struct stm32_sai_s *priv, int result); static void sai_dma_callback(DMA_HANDLE handle, uint8_t isr, void *arg); #endif @@ -229,89 +229,89 @@ static const struct i2s_ops_s g_i2sops = /* SAI1 state */ -#ifdef CONFIG_STM32L4_SAI1_A -static struct stm32l4_sai_s g_sai1a_priv = +#ifdef CONFIG_STM32_SAI1_A +static struct stm32_sai_s g_sai1a_priv = { .dev.ops = &g_i2sops, - .base = STM32L4_SAI1_A_BASE, + .base = STM32_SAI1_A_BASE, .lock = NXMUTEX_INITIALIZER, - .frequency = STM32L4_SAI1_FREQUENCY, -#ifdef CONFIG_STM32L4_SAI1_A_SYNC_WITH_B + .frequency = STM32_SAI1_FREQUENCY, +#ifdef CONFIG_STM32_SAI1_A_SYNC_WITH_B .syncen = SAI_CR1_SYNCEN_SYNC_INT, #else .syncen = SAI_CR1_SYNCEN_ASYNC, #endif -#ifdef CONFIG_STM32L4_SAI_DMA +#ifdef CONFIG_STM32_SAI_DMA .dma_ch = DMACHAN_SAI1_A, #endif - .datalen = CONFIG_STM32L4_SAI_DEFAULT_DATALEN, - .samplerate = CONFIG_STM32L4_SAI_DEFAULT_SAMPLERATE, - .bufsem = SEM_INITIALIZER(CONFIG_STM32L4_SAI_MAXINFLIGHT), + .datalen = CONFIG_STM32_SAI_DEFAULT_DATALEN, + .samplerate = CONFIG_STM32_SAI_DEFAULT_SAMPLERATE, + .bufsem = SEM_INITIALIZER(CONFIG_STM32_SAI_MAXINFLIGHT), }; #endif -#ifdef CONFIG_STM32L4_SAI1_B -static struct stm32l4_sai_s g_sai1b_priv = +#ifdef CONFIG_STM32_SAI1_B +static struct stm32_sai_s g_sai1b_priv = { .dev.ops = &g_i2sops, - .base = STM32L4_SAI1_B_BASE, + .base = STM32_SAI1_B_BASE, .lock = NXMUTEX_INITIALIZER, - .frequency = STM32L4_SAI1_FREQUENCY, -#ifdef CONFIG_STM32L4_SAI1_B_SYNC_WITH_A + .frequency = STM32_SAI1_FREQUENCY, +#ifdef CONFIG_STM32_SAI1_B_SYNC_WITH_A .syncen = SAI_CR1_SYNCEN_SYNC_INT, #else .syncen = SAI_CR1_SYNCEN_ASYNC, #endif -#ifdef CONFIG_STM32L4_SAI_DMA +#ifdef CONFIG_STM32_SAI_DMA .dma_ch = DMACHAN_SAI1_B, #endif - .datalen = CONFIG_STM32L4_SAI_DEFAULT_DATALEN, - .samplerate = CONFIG_STM32L4_SAI_DEFAULT_SAMPLERATE, - .bufsem = SEM_INITIALIZER(CONFIG_STM32L4_SAI_MAXINFLIGHT), + .datalen = CONFIG_STM32_SAI_DEFAULT_DATALEN, + .samplerate = CONFIG_STM32_SAI_DEFAULT_SAMPLERATE, + .bufsem = SEM_INITIALIZER(CONFIG_STM32_SAI_MAXINFLIGHT), }; #endif /* SAI2 state */ -#ifdef CONFIG_STM32L4_SAI2_A -static struct stm32l4_sai_s g_sai2a_priv = +#ifdef CONFIG_STM32_SAI2_A +static struct stm32_sai_s g_sai2a_priv = { .dev.ops = &g_i2sops, - .base = STM32L4_SAI2_A_BASE, + .base = STM32_SAI2_A_BASE, .lock = NXMUTEX_INITIALIZER, - .frequency = STM32L4_SAI2_FREQUENCY, -#ifdef CONFIG_STM32L4_SAI2_A_SYNC_WITH_B + .frequency = STM32_SAI2_FREQUENCY, +#ifdef CONFIG_STM32_SAI2_A_SYNC_WITH_B .syncen = SAI_CR1_SYNCEN_SYNC_INT, #else .syncen = SAI_CR1_SYNCEN_ASYNC, #endif -#ifdef CONFIG_STM32L4_SAI_DMA +#ifdef CONFIG_STM32_SAI_DMA .dma_ch = DMACHAN_SAI2_A, #endif - .datalen = CONFIG_STM32L4_SAI_DEFAULT_DATALEN, - .samplerate = CONFIG_STM32L4_SAI_DEFAULT_SAMPLERATE, - .bufsem = SEM_INITIALIZER(CONFIG_STM32L4_SAI_MAXINFLIGHT), + .datalen = CONFIG_STM32_SAI_DEFAULT_DATALEN, + .samplerate = CONFIG_STM32_SAI_DEFAULT_SAMPLERATE, + .bufsem = SEM_INITIALIZER(CONFIG_STM32_SAI_MAXINFLIGHT), }; #endif -#ifdef CONFIG_STM32L4_SAI2_B -static struct stm32l4_sai_s g_sai2b_priv = +#ifdef CONFIG_STM32_SAI2_B +static struct stm32_sai_s g_sai2b_priv = { .dev.ops = &g_i2sops, - .base = STM32L4_SAI2_B_BASE, + .base = STM32_SAI2_B_BASE, .lock = NXMUTEX_INITIALIZER, - .frequency = STM32L4_SAI2_FREQUENCY, -#ifdef CONFIG_STM32L4_SAI2_B_SYNC_WITH_A + .frequency = STM32_SAI2_FREQUENCY, +#ifdef CONFIG_STM32_SAI2_B_SYNC_WITH_A .syncen = SAI_CR1_SYNCEN_SYNC_INT, #else .syncen = SAI_CR1_SYNCEN_ASYNC, #endif -#ifdef CONFIG_STM32L4_SAI_DMA +#ifdef CONFIG_STM32_SAI_DMA .dma_ch = DMACHAN_SAI2_B, #endif - .datalen = CONFIG_STM32L4_SAI_DEFAULT_DATALEN, - .samplerate = CONFIG_STM32L4_SAI_DEFAULT_SAMPLERATE, - .bufsem = SEM_INITIALIZER(CONFIG_STM32L4_SAI_MAXINFLIGHT), + .datalen = CONFIG_STM32_SAI_DEFAULT_DATALEN, + .samplerate = CONFIG_STM32_SAI_DEFAULT_SAMPLERATE, + .bufsem = SEM_INITIALIZER(CONFIG_STM32_SAI_MAXINFLIGHT), }; #endif @@ -333,7 +333,7 @@ static struct stm32l4_sai_s g_sai2b_priv = * ****************************************************************************/ -static inline uint32_t sai_getbitrate(struct stm32l4_sai_s *priv) +static inline uint32_t sai_getbitrate(struct stm32_sai_s *priv) { /* Calculate the bitrate in Hz */ @@ -355,7 +355,7 @@ static inline uint32_t sai_getbitrate(struct stm32l4_sai_s *priv) * ****************************************************************************/ -static inline uint32_t sai_getreg(struct stm32l4_sai_s *priv, uint8_t offset) +static inline uint32_t sai_getreg(struct stm32_sai_s *priv, uint8_t offset) { return getreg32(priv->base + offset); } @@ -376,7 +376,7 @@ static inline uint32_t sai_getreg(struct stm32l4_sai_s *priv, uint8_t offset) * ****************************************************************************/ -static inline void sai_putreg(struct stm32l4_sai_s *priv, uint8_t offset, +static inline void sai_putreg(struct stm32_sai_s *priv, uint8_t offset, uint32_t value) { putreg32(value, priv->base + offset); @@ -399,7 +399,7 @@ static inline void sai_putreg(struct stm32l4_sai_s *priv, uint8_t offset, * ****************************************************************************/ -static void sai_modifyreg(struct stm32l4_sai_s *priv, uint8_t offset, +static void sai_modifyreg(struct stm32_sai_s *priv, uint8_t offset, uint32_t clrbits, uint32_t setbits) { uint32_t regval; @@ -426,21 +426,21 @@ static void sai_modifyreg(struct stm32l4_sai_s *priv, uint8_t offset, ****************************************************************************/ #ifdef CONFIG_DEBUG_I2S_INFO -static void sai_dump_regs(struct stm32l4_sai_s *priv, const char *msg) +static void sai_dump_regs(struct stm32_sai_s *priv, const char *msg) { if (msg) i2sinfo("%s\n", msg); i2sinfo("CR1:%08" PRIx32 " CR2:%08" PRIx32 " FRCR:%08" PRIx32 " SLOTR:%08" PRIx32 "\n", - sai_getreg(priv, STM32L4_SAI_CR1_OFFSET), - sai_getreg(priv, STM32L4_SAI_CR2_OFFSET), - sai_getreg(priv, STM32L4_SAI_FRCR_OFFSET), - sai_getreg(priv, STM32L4_SAI_SLOTR_OFFSET)); + sai_getreg(priv, STM32_SAI_CR1_OFFSET), + sai_getreg(priv, STM32_SAI_CR2_OFFSET), + sai_getreg(priv, STM32_SAI_FRCR_OFFSET), + sai_getreg(priv, STM32_SAI_SLOTR_OFFSET)); i2sinfo(" IM:%08" PRIx32 " SR:%08" PRIx32 " CLRFR:%08" PRIx32 "\n", - sai_getreg(priv, STM32L4_SAI_IM_OFFSET), - sai_getreg(priv, STM32L4_SAI_SR_OFFSET), - sai_getreg(priv, STM32L4_SAI_CLRFR_OFFSET)); + sai_getreg(priv, STM32_SAI_IM_OFFSET), + sai_getreg(priv, STM32_SAI_SR_OFFSET), + sai_getreg(priv, STM32_SAI_CLRFR_OFFSET)); } #endif @@ -460,7 +460,7 @@ static void sai_dump_regs(struct stm32l4_sai_s *priv, const char *msg) * ****************************************************************************/ -static void sai_mckdivider(struct stm32l4_sai_s *priv) +static void sai_mckdivider(struct stm32_sai_s *priv) { uint32_t mckdiv; @@ -474,7 +474,7 @@ static void sai_mckdivider(struct stm32l4_sai_s *priv) mckdiv = priv->frequency / (priv->samplerate * 2 * 256); - sai_modifyreg(priv, STM32L4_SAI_CR1_OFFSET, SAI_CR1_MCKDIV_MASK, + sai_modifyreg(priv, STM32_SAI_CR1_OFFSET, SAI_CR1_MCKDIV_MASK, mckdiv << SAI_CR1_MCKDIV_SHIFT); } @@ -497,13 +497,13 @@ static void sai_mckdivider(struct stm32l4_sai_s *priv) static void sai_timeout(wdparm_t arg) { - struct stm32l4_sai_s *priv = (struct stm32l4_sai_s *)arg; + struct stm32_sai_s *priv = (struct stm32_sai_s *)arg; DEBUGASSERT(priv != NULL); -#ifdef CONFIG_STM32L4_SAI_DMA +#ifdef CONFIG_STM32_SAI_DMA /* Cancel the DMA */ - stm32l4_dmastop(priv->dma); + stm32_dmastop(priv->dma); #endif /* Then schedule completion of the transfer to occur on the worker @@ -530,8 +530,8 @@ static void sai_timeout(wdparm_t arg) * ****************************************************************************/ -#ifdef CONFIG_STM32L4_SAI_DMA -static int sai_dma_setup(struct stm32l4_sai_s *priv) +#ifdef CONFIG_STM32_SAI_DMA +static int sai_dma_setup(struct stm32_sai_s *priv) { struct sai_buffer_s *bfcontainer; struct ap_buffer_s *apb; @@ -621,7 +621,7 @@ static int sai_dma_setup(struct stm32l4_sai_s *priv) DEBUGASSERT(ntransfers > 0); - stm32l4_dmasetup(priv->dma, priv->base + STM32L4_SAI_DR_OFFSET, + stm32_dmasetup(priv->dma, priv->base + STM32_SAI_DR_OFFSET, samp, ntransfers, priv->dma_ccr); /* Add the container to the list of active DMAs */ @@ -630,11 +630,11 @@ static int sai_dma_setup(struct stm32l4_sai_s *priv) /* Start the DMA, saving the container as the current active transfer */ - stm32l4_dmastart(priv->dma, sai_dma_callback, priv, false); + stm32_dmastart(priv->dma, sai_dma_callback, priv, false); /* Enable the transmitter */ - sai_modifyreg(priv, STM32L4_SAI_CR1_OFFSET, 0, SAI_CR1_SAIEN); + sai_modifyreg(priv, STM32_SAI_CR1_OFFSET, 0, SAI_CR1_SAIEN); /* Start a watchdog to catch DMA timeouts */ @@ -675,7 +675,7 @@ static int sai_dma_setup(struct stm32l4_sai_s *priv) static void sai_worker(void *arg) { - struct stm32l4_sai_s *priv = (struct stm32l4_sai_s *)arg; + struct stm32_sai_s *priv = (struct stm32_sai_s *)arg; struct sai_buffer_s *bfcontainer; irqstate_t flags; @@ -702,7 +702,7 @@ static void sai_worker(void *arg) */ flags = enter_critical_section(); -#ifdef CONFIG_STM32L4_SAI_DMA +#ifdef CONFIG_STM32_SAI_DMA sai_dma_setup(priv); #endif leave_critical_section(flags); @@ -759,7 +759,7 @@ static void sai_worker(void *arg) * ****************************************************************************/ -static void sai_schedule(struct stm32l4_sai_s *priv, int result) +static void sai_schedule(struct stm32_sai_s *priv, int result) { struct sai_buffer_s *bfcontainer; int ret; @@ -814,10 +814,10 @@ static void sai_schedule(struct stm32l4_sai_s *priv, int result) * ****************************************************************************/ -#ifdef CONFIG_STM32L4_SAI_DMA +#ifdef CONFIG_STM32_SAI_DMA static void sai_dma_callback(DMA_HANDLE handle, uint8_t isr, void *arg) { - struct stm32l4_sai_s *priv = (struct stm32l4_sai_s *)arg; + struct stm32_sai_s *priv = (struct stm32_sai_s *)arg; DEBUGASSERT(priv); /* Cancel the watchdog timeout */ @@ -847,7 +847,7 @@ static void sai_dma_callback(DMA_HANDLE handle, uint8_t isr, void *arg) static uint32_t sai_samplerate(struct i2s_dev_s *dev, uint32_t rate) { - struct stm32l4_sai_s *priv = (struct stm32l4_sai_s *)dev; + struct stm32_sai_s *priv = (struct stm32_sai_s *)dev; DEBUGASSERT(priv && rate > 0); @@ -877,7 +877,7 @@ static uint32_t sai_samplerate(struct i2s_dev_s *dev, uint32_t rate) static uint32_t sai_datawidth(struct i2s_dev_s *dev, int bits) { - struct stm32l4_sai_s *priv = (struct stm32l4_sai_s *)dev; + struct stm32_sai_s *priv = (struct stm32_sai_s *)dev; uint32_t setbits; DEBUGASSERT(priv && bits >= 8); @@ -901,9 +901,9 @@ static uint32_t sai_datawidth(struct i2s_dev_s *dev, int bits) return 0; } - sai_modifyreg(priv, STM32L4_SAI_CR1_OFFSET, SAI_CR1_DS_MASK, setbits); + sai_modifyreg(priv, STM32_SAI_CR1_OFFSET, SAI_CR1_DS_MASK, setbits); - sai_modifyreg(priv, STM32L4_SAI_FRCR_OFFSET, + sai_modifyreg(priv, STM32_SAI_FRCR_OFFSET, SAI_FRCR_FSALL_MASK | SAI_FRCR_FRL_MASK, SAI_FRCR_FSALL(bits) | SAI_FRCR_FRL(bits * 2)); @@ -947,7 +947,7 @@ static uint32_t sai_datawidth(struct i2s_dev_s *dev, int bits) static int sai_receive(struct i2s_dev_s *dev, struct ap_buffer_s *apb, i2s_callback_t callback, void *arg, uint32_t timeout) { - struct stm32l4_sai_s *priv = (struct stm32l4_sai_s *)dev; + struct stm32_sai_s *priv = (struct stm32_sai_s *)dev; struct sai_buffer_s *bfcontainer; uint32_t mode; irqstate_t flags; @@ -981,7 +981,7 @@ static int sai_receive(struct i2s_dev_s *dev, struct ap_buffer_s *apb, } mode = priv->syncen ? SAI_CR1_MODE_SLAVE_RX : SAI_CR1_MODE_MASTER_RX; - sai_modifyreg(priv, STM32L4_SAI_CR1_OFFSET, SAI_CR1_MODE_MASK, mode); + sai_modifyreg(priv, STM32_SAI_CR1_OFFSET, SAI_CR1_MODE_MASK, mode); priv->rxenab = true; /* Add a reference to the audio buffer */ @@ -1005,7 +1005,7 @@ static int sai_receive(struct i2s_dev_s *dev, struct ap_buffer_s *apb, * progress, then this will do nothing. */ -#ifdef CONFIG_STM32L4_SAI_DMA +#ifdef CONFIG_STM32_SAI_DMA ret = sai_dma_setup(priv); #endif DEBUGASSERT(ret == OK); @@ -1052,7 +1052,7 @@ static int sai_receive(struct i2s_dev_s *dev, struct ap_buffer_s *apb, static int sai_send(struct i2s_dev_s *dev, struct ap_buffer_s *apb, i2s_callback_t callback, void *arg, uint32_t timeout) { - struct stm32l4_sai_s *priv = (struct stm32l4_sai_s *)dev; + struct stm32_sai_s *priv = (struct stm32_sai_s *)dev; struct sai_buffer_s *bfcontainer; uint32_t mode; irqstate_t flags; @@ -1086,7 +1086,7 @@ static int sai_send(struct i2s_dev_s *dev, struct ap_buffer_s *apb, } mode = priv->syncen ? SAI_CR1_MODE_SLAVE_TX : SAI_CR1_MODE_MASTER_TX; - sai_modifyreg(priv, STM32L4_SAI_CR1_OFFSET, SAI_CR1_MODE_MASK, mode); + sai_modifyreg(priv, STM32_SAI_CR1_OFFSET, SAI_CR1_MODE_MASK, mode); priv->txenab = true; /* Add a reference to the audio buffer */ @@ -1110,7 +1110,7 @@ static int sai_send(struct i2s_dev_s *dev, struct ap_buffer_s *apb, * progress, then this will do nothing. */ -#ifdef CONFIG_STM32L4_SAI_DMA +#ifdef CONFIG_STM32_SAI_DMA ret = sai_dma_setup(priv); #endif DEBUGASSERT(ret == OK); @@ -1144,7 +1144,7 @@ static int sai_send(struct i2s_dev_s *dev, struct ap_buffer_s *apb, * ****************************************************************************/ -static struct sai_buffer_s *sai_buf_allocate(struct stm32l4_sai_s *priv) +static struct sai_buffer_s *sai_buf_allocate(struct stm32_sai_s *priv) { struct sai_buffer_s *bfcontainer; irqstate_t flags; @@ -1191,7 +1191,7 @@ static struct sai_buffer_s *sai_buf_allocate(struct stm32l4_sai_s *priv) * ****************************************************************************/ -static void sai_buf_free(struct stm32l4_sai_s *priv, +static void sai_buf_free(struct stm32_sai_s *priv, struct sai_buffer_s *bfcontainer) { irqstate_t flags; @@ -1227,12 +1227,12 @@ static void sai_buf_free(struct stm32l4_sai_s *priv, * ****************************************************************************/ -static void sai_buf_initialize(struct stm32l4_sai_s *priv) +static void sai_buf_initialize(struct stm32_sai_s *priv) { int i; priv->freelist = NULL; - for (i = 0; i < CONFIG_STM32L4_SAI_MAXINFLIGHT; i++) + for (i = 0; i < CONFIG_STM32_SAI_MAXINFLIGHT; i++) { sai_buf_free(priv, &priv->containers[i]); } @@ -1252,7 +1252,7 @@ static void sai_buf_initialize(struct stm32l4_sai_s *priv) * ****************************************************************************/ -static void sai_portinitialize(struct stm32l4_sai_s *priv) +static void sai_portinitialize(struct stm32_sai_s *priv) { sai_dump_regs(priv, "Before initialization"); @@ -1267,29 +1267,29 @@ static void sai_portinitialize(struct stm32l4_sai_s *priv) /* Configure the data width */ sai_datawidth((struct i2s_dev_s *)priv, - CONFIG_STM32L4_SAI_DEFAULT_DATALEN); + CONFIG_STM32_SAI_DEFAULT_DATALEN); -#ifdef CONFIG_STM32L4_SAI_DMA +#ifdef CONFIG_STM32_SAI_DMA /* Get DMA channel */ - priv->dma = stm32l4_dmachannel(priv->dma_ch); + priv->dma = stm32_dmachannel(priv->dma_ch); DEBUGASSERT(priv->dma); - sai_modifyreg(priv, STM32L4_SAI_CR1_OFFSET, 0, SAI_CR1_DMAEN); + sai_modifyreg(priv, STM32_SAI_CR1_OFFSET, 0, SAI_CR1_DMAEN); #endif - sai_modifyreg(priv, STM32L4_SAI_CR1_OFFSET, SAI_CR1_SYNCEN_MASK, + sai_modifyreg(priv, STM32_SAI_CR1_OFFSET, SAI_CR1_SYNCEN_MASK, priv->syncen); - sai_modifyreg(priv, STM32L4_SAI_CR2_OFFSET, SAI_CR2_FTH_MASK, + sai_modifyreg(priv, STM32_SAI_CR2_OFFSET, SAI_CR2_FTH_MASK, SAI_CR2_FTH_1QF); - sai_modifyreg(priv, STM32L4_SAI_FRCR_OFFSET, + sai_modifyreg(priv, STM32_SAI_FRCR_OFFSET, SAI_FRCR_FSDEF | SAI_FRCR_FSPOL | SAI_FRCR_FSOFF, SAI_FRCR_FSDEF_CHID | SAI_FRCR_FSPOL_LOW | SAI_FRCR_FSOFF_BFB); - sai_modifyreg(priv, STM32L4_SAI_SLOTR_OFFSET, + sai_modifyreg(priv, STM32_SAI_SLOTR_OFFSET, SAI_SLOTR_NBSLOT_MASK | SAI_SLOTR_SLOTEN_MASK, SAI_SLOTR_NBSLOT(2) | SAI_SLOTR_SLOTEN_0 | SAI_SLOTR_SLOTEN_1); @@ -1302,7 +1302,7 @@ static void sai_portinitialize(struct stm32l4_sai_s *priv) ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_sai_initialize + * Name: stm32_sai_initialize * * Description: * Initialize the selected SAI block @@ -1315,74 +1315,74 @@ static void sai_portinitialize(struct stm32l4_sai_s *priv) * ****************************************************************************/ -struct i2s_dev_s *stm32l4_sai_initialize(int intf) +struct i2s_dev_s *stm32_sai_initialize(int intf) { - struct stm32l4_sai_s *priv; + struct stm32_sai_s *priv; irqstate_t flags; flags = enter_critical_section(); switch (intf) { -#ifdef CONFIG_STM32L4_SAI1_A +#ifdef CONFIG_STM32_SAI1_A case SAI1_BLOCK_A: { i2sinfo("SAI1 Block A Selected\n"); priv = &g_sai1a_priv; - stm32l4_configgpio(GPIO_SAI1_SD_A); -# ifndef CONFIG_STM32L4_SAI1_A_SYNC_WITH_B - stm32l4_configgpio(GPIO_SAI1_FS_A); - stm32l4_configgpio(GPIO_SAI1_SCK_A); - stm32l4_configgpio(GPIO_SAI1_MCLK_A); + stm32_configgpio(GPIO_SAI1_SD_A); +# ifndef CONFIG_STM32_SAI1_A_SYNC_WITH_B + stm32_configgpio(GPIO_SAI1_FS_A); + stm32_configgpio(GPIO_SAI1_SCK_A); + stm32_configgpio(GPIO_SAI1_MCLK_A); # endif break; } #endif -#ifdef CONFIG_STM32L4_SAI1_B +#ifdef CONFIG_STM32_SAI1_B case SAI1_BLOCK_B: { i2sinfo("SAI1 Block B Selected\n"); priv = &g_sai1b_priv; - stm32l4_configgpio(GPIO_SAI1_SD_B); -# ifndef CONFIG_STM32L4_SAI1_B_SYNC_WITH_A - stm32l4_configgpio(GPIO_SAI1_FS_B); - stm32l4_configgpio(GPIO_SAI1_SCK_B); - stm32l4_configgpio(GPIO_SAI1_MCLK_B); + stm32_configgpio(GPIO_SAI1_SD_B); +# ifndef CONFIG_STM32_SAI1_B_SYNC_WITH_A + stm32_configgpio(GPIO_SAI1_FS_B); + stm32_configgpio(GPIO_SAI1_SCK_B); + stm32_configgpio(GPIO_SAI1_MCLK_B); # endif break; } #endif -#ifdef CONFIG_STM32L4_SAI2_A +#ifdef CONFIG_STM32_SAI2_A case SAI2_BLOCK_A: { i2sinfo("SAI2 Block A Selected\n"); priv = &g_sai2a_priv; - stm32l4_configgpio(GPIO_SAI2_SD_A); -# ifndef CONFIG_STM32L4_SAI2_A_SYNC_WITH_B - stm32l4_configgpio(GPIO_SAI2_FS_A); - stm32l4_configgpio(GPIO_SAI2_SCK_A); - stm32l4_configgpio(GPIO_SAI2_MCLK_A); + stm32_configgpio(GPIO_SAI2_SD_A); +# ifndef CONFIG_STM32_SAI2_A_SYNC_WITH_B + stm32_configgpio(GPIO_SAI2_FS_A); + stm32_configgpio(GPIO_SAI2_SCK_A); + stm32_configgpio(GPIO_SAI2_MCLK_A); # endif break; } #endif -#ifdef CONFIG_STM32L4_SAI2_B +#ifdef CONFIG_STM32_SAI2_B case SAI2_BLOCK_B: { i2sinfo("SAI2 Block B Selected\n"); priv = &g_sai2b_priv; - stm32l4_configgpio(GPIO_SAI2_SD_B); -# ifndef CONFIG_STM32L4_SAI2_B_SYNC_WITH_A - stm32l4_configgpio(GPIO_SAI2_FS_B); - stm32l4_configgpio(GPIO_SAI2_SCK_B); - stm32l4_configgpio(GPIO_SAI2_MCLK_B); + stm32_configgpio(GPIO_SAI2_SD_B); +# ifndef CONFIG_STM32_SAI2_B_SYNC_WITH_A + stm32_configgpio(GPIO_SAI2_FS_B); + stm32_configgpio(GPIO_SAI2_SCK_B); + stm32_configgpio(GPIO_SAI2_MCLK_B); # endif break; } diff --git a/arch/arm/src/stm32l4/stm32l4_sai.h b/arch/arm/src/stm32l4/stm32l4_sai.h index 69c305ba8b12b..8de7dcc14f597 100644 --- a/arch/arm/src/stm32l4/stm32l4_sai.h +++ b/arch/arm/src/stm32l4/stm32l4_sai.h @@ -34,8 +34,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32L4_STM32L4_SAI_H -#define __ARCH_ARM_SRC_STM32L4_STM32L4_SAI_H +#ifndef __ARCH_ARM_SRC_STM32L4_STM32_SAI_H +#define __ARCH_ARM_SRC_STM32L4_STM32_SAI_H /**************************************************************************** * Included Files @@ -71,7 +71,7 @@ extern "C" #endif /**************************************************************************** - * Name: stm32l4_sai_initialize + * Name: stm32_sai_initialize * * Description: * Initialize the selected SAI block @@ -84,7 +84,7 @@ extern "C" * ****************************************************************************/ -struct i2s_dev_s *stm32l4_sai_initialize(int intf); +struct i2s_dev_s *stm32_sai_initialize(int intf); #undef EXTERN #ifdef __cplusplus @@ -92,4 +92,4 @@ struct i2s_dev_s *stm32l4_sai_initialize(int intf); #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32L4_STM32L4_SAI_H */ +#endif /* __ARCH_ARM_SRC_STM32L4_STM32_SAI_H */ diff --git a/arch/arm/src/stm32l4/stm32l4_sdmmc.c b/arch/arm/src/stm32l4/stm32l4_sdmmc.c index 49e54607c3400..bea2a35c088d8 100644 --- a/arch/arm/src/stm32l4/stm32l4_sdmmc.c +++ b/arch/arm/src/stm32l4/stm32l4_sdmmc.c @@ -50,7 +50,7 @@ #include "stm32l4_gpio.h" #include "stm32l4_sdmmc.h" -#if defined(CONFIG_STM32L4_SDMMC1) || defined(CONFIG_STM32L4_SDMMC2) +#if defined(CONFIG_STM32_SDMMC1) || defined(CONFIG_STM32_SDMMC2) /**************************************************************************** * Pre-processor Definitions @@ -62,7 +62,7 @@ * * CONFIG_ARCH_DMA - Enable architecture-specific DMA subsystem * initialization. Required if CONFIG_SDMMC[1|2]_DMA is enabled. - * CONFIG_STM32L4_DMA2 - Enable STM32 DMA2 support. Required if + * CONFIG_STM32_DMA2 - Enable STM32 DMA2 support. Required if * CONFIG_SDMMC[1|2]_DMA is enabled * CONFIG_SCHED_WORKQUEUE -- Callback support requires work queue support. * @@ -71,27 +71,27 @@ * CONFIG_SDIO_MUXBUS - Setting this configuration enables some locking * APIs to manage concurrent accesses on the SDMMC bus. This is not * needed for the simple case of a single SD card, for example. - * CONFIG_STM32L4_SDMMC_DMA - Enable SDMMC. This is a marginally + * CONFIG_STM32_SDMMC_DMA - Enable SDMMC. This is a marginally * optional. For most usages, SDMMC will cause data overruns if used * without DMA. NOTE the above system DMA configuration options. * CONFIG_SDMMC1/2_WIDTH_D1_ONLY - This may be selected to force the driver * operate with only a single data line (the default is to use all * 4 SD data lines). * CONFIG_SDMMC_DMAPRIO - SDMMC DMA priority. This can be selected if - * CONFIG_STM32L4_SDMMC_DMA is enabled. - * CONFIG_STM32L4_SDMMC_XFRDEBUG - Enables some very low-level + * CONFIG_STM32_SDMMC_DMA is enabled. + * CONFIG_STM32_SDMMC_XFRDEBUG - Enables some very low-level * debug output. This also requires CONFIG_DEBUG_FS and * CONFIG_DEBUG_INFO */ -#ifndef CONFIG_STM32L4_SDMMC_DMA +#ifndef CONFIG_STM32_SDMMC_DMA # warning "Large Non-DMA transfer may result in RX overrun failures" #else -# if !defined(CONFIG_STM32L4_DMA2) && !defined(CONFIG_STM32L4_DMAMUX) -# error "CONFIG_STM32L4_SDMMC_DMA support requires CONFIG_STM32L4_DMA2" +# if !defined(CONFIG_STM32_DMA2) && !defined(CONFIG_STM32_DMAMUX) +# error "CONFIG_STM32_SDMMC_DMA support requires CONFIG_STM32_DMA2" # endif # ifndef CONFIG_SDIO_DMA -# error CONFIG_SDIO_DMA must be defined with CONFIG_STM32L4_SDMMC_DMA +# error CONFIG_SDIO_DMA must be defined with CONFIG_STM32_SDMMC_DMA # endif #endif @@ -99,34 +99,34 @@ # error "Callback support requires CONFIG_SCHED_WORKQUEUE and CONFIG_SCHED_HPWORK" #endif -#ifdef CONFIG_STM32L4_SDMMC1 -# ifdef CONFIG_STM32L4_SDMMC_DMA -# ifndef CONFIG_STM32L4_SDMMC1_DMAPRIO -# define CONFIG_STM32L4_SDMMC1_DMAPRIO DMA_SCR_PRIVERYHI +#ifdef CONFIG_STM32_SDMMC1 +# ifdef CONFIG_STM32_SDMMC_DMA +# ifndef CONFIG_STM32_SDMMC1_DMAPRIO +# define CONFIG_STM32_SDMMC1_DMAPRIO DMA_SCR_PRIVERYHI # endif -# if (CONFIG_STM32L4_SDMMC1_DMAPRIO & ~DMA_CCR_PL_MASK) != 0 -# error "Illegal value for CONFIG_STM32L4_SDMMC1_DMAPRIO" +# if (CONFIG_STM32_SDMMC1_DMAPRIO & ~DMA_CCR_PL_MASK) != 0 +# error "Illegal value for CONFIG_STM32_SDMMC1_DMAPRIO" # endif # else -# undef CONFIG_STM32L4_SDMMC1_DMAPRIO +# undef CONFIG_STM32_SDMMC1_DMAPRIO # endif #endif -#ifdef CONFIG_STM32L4_SDMMC2 -# ifdef CONFIG_STM32L4_SDMMC_DMA -# ifndef CONFIG_STM32L4_SDMMC2_DMAPRIO -# define CONFIG_STM32L4_SDMMC2_DMAPRIO DMA_SCR_PRIVERYHI +#ifdef CONFIG_STM32_SDMMC2 +# ifdef CONFIG_STM32_SDMMC_DMA +# ifndef CONFIG_STM32_SDMMC2_DMAPRIO +# define CONFIG_STM32_SDMMC2_DMAPRIO DMA_SCR_PRIVERYHI # endif -# if (CONFIG_STM32L4_SDMMC2_DMAPRIO & ~DMA_CCR_PL_MASK) != 0 -# error "Illegal value for CONFIG_STM32L4_SDMMC2_DMAPRIO" +# if (CONFIG_STM32_SDMMC2_DMAPRIO & ~DMA_CCR_PL_MASK) != 0 +# error "Illegal value for CONFIG_STM32_SDMMC2_DMAPRIO" # endif # else -# undef CONFIG_STM32L4_SDMMC2_DMAPRIO +# undef CONFIG_STM32_SDMMC2_DMAPRIO # endif #endif #if !defined(CONFIG_DEBUG_FS) || !defined(CONFIG_DEBUG_FEATURES) -# undef CONFIG_STM32L4_SDMMC_XFRDEBUG +# undef CONFIG_STM32_SDMMC_XFRDEBUG #endif /* Friendly CLKCR bit re-definitions ****************************************/ @@ -288,8 +288,8 @@ /* Register logging support */ -#ifdef CONFIG_STM32L4_SDMMC_XFRDEBUG -# ifdef CONFIG_STM32L4_SDMMC_DMA +#ifdef CONFIG_STM32_SDMMC_XFRDEBUG +# ifdef CONFIG_STM32_SDMMC_DMA # define SAMPLENDX_BEFORE_SETUP 0 # define SAMPLENDX_BEFORE_ENABLE 1 # define SAMPLENDX_AFTER_SETUP 2 @@ -321,7 +321,7 @@ struct stm32_dev_s #ifdef CONFIG_MMCSD_SDIOWAIT_WRCOMPLETE uint32_t d0_gpio; #endif -#ifdef CONFIG_STM32L4_SDMMC_DMA +#ifdef CONFIG_STM32_SDMMC_DMA uint32_t dmapri; #endif @@ -351,7 +351,7 @@ struct stm32_dev_s bool widebus; /* Required for DMA support */ bool onebit; /* true: Only 1-bit transfers are supported */ -#ifdef CONFIG_STM32L4_SDMMC_DMA +#ifdef CONFIG_STM32_SDMMC_DMA volatile uint8_t xfrflags; /* Used to synchronize SDMMC and DMA completion events */ bool dmamode; /* true: DMA mode transfer */ DMA_HANDLE dma; /* Handle for DMA channel */ @@ -360,7 +360,7 @@ struct stm32_dev_s /* Register logging support */ -#ifdef CONFIG_STM32L4_SDMMC_XFRDEBUG +#ifdef CONFIG_STM32_SDMMC_XFRDEBUG struct stm32_sdioregs_s { uint8_t power; @@ -377,7 +377,7 @@ struct stm32_sdioregs_s struct stm32_sampleregs_s { struct stm32_sdioregs_s sdio; -#if defined(CONFIG_DEBUG_DMA_INFO) && defined(CONFIG_STM32L4_SDMMC_DMA) +#if defined(CONFIG_DEBUG_DMA_INFO) && defined(CONFIG_STM32_SDMMC_DMA) struct stm32_dmaregs_s dma; #endif }; @@ -400,7 +400,7 @@ static void stm32_setpwrctrl(struct stm32_dev_s *priv, uint32_t pwrctrl); /* DMA Helpers **************************************************************/ -#ifdef CONFIG_STM32L4_SDMMC_XFRDEBUG +#ifdef CONFIG_STM32_SDMMC_XFRDEBUG static void stm32_sampleinit(void); static void stm32_sdiosample(struct stm32_dev_s *priv, struct stm32_sdioregs_s *regs); @@ -415,7 +415,7 @@ static void stm32_dumpsamples(struct stm32_dev_s *priv); # define stm32_dumpsamples(priv) #endif -#ifdef CONFIG_STM32L4_SDMMC_DMA +#ifdef CONFIG_STM32_SDMMC_DMA static void stm32_dmacallback(DMA_HANDLE handle, uint8_t status, void *arg); #endif @@ -490,7 +490,7 @@ static int stm32_registercallback(struct sdio_dev_s *dev, /* DMA */ -#ifdef CONFIG_STM32L4_SDMMC_DMA +#ifdef CONFIG_STM32_SDMMC_DMA #ifdef CONFIG_ARCH_HAVE_SDIO_PREFLIGHT static int stm32_dmapreflight(struct sdio_dev_s *dev, const uint8_t *buffer, size_t buflen); @@ -510,7 +510,7 @@ static void stm32_default(struct stm32_dev_s *priv); * Private Data ****************************************************************************/ -#ifdef CONFIG_STM32L4_SDMMC1 +#ifdef CONFIG_STM32_SDMMC1 struct stm32_dev_s g_sdmmcdev1 = { .dev = @@ -546,7 +546,7 @@ struct stm32_dev_s g_sdmmcdev1 = .registercallback = stm32_registercallback, #endif #ifdef CONFIG_SDIO_DMA -#ifdef CONFIG_STM32L4_SDMMC_DMA +#ifdef CONFIG_STM32_SDMMC_DMA #ifdef CONFIG_ARCH_HAVE_SDIO_PREFLIGHT .dmapreflight = stm32_dmapreflight, #endif @@ -561,18 +561,18 @@ struct stm32_dev_s g_sdmmcdev1 = #endif #endif }, - .base = STM32L4_SDMMC1_BASE, - .nirq = STM32L4_IRQ_SDMMC1, + .base = STM32_SDMMC1_BASE, + .nirq = STM32_IRQ_SDMMC1, #ifdef CONFIG_MMCSD_SDIOWAIT_WRCOMPLETE .d0_gpio = GPIO_SDMMC1_D0, #endif -#ifdef CONFIG_STM32L4_SDMMC1_DMAPRIO - .dmapri = CONFIG_STM32L4_SDMMC1_DMAPRIO, +#ifdef CONFIG_STM32_SDMMC1_DMAPRIO + .dmapri = CONFIG_STM32_SDMMC1_DMAPRIO, #endif .waitsem = SEM_INITIALIZER(0), }; #endif -#ifdef CONFIG_STM32L4_SDMMC2 +#ifdef CONFIG_STM32_SDMMC2 struct stm32_dev_s g_sdmmcdev2 = { .dev = @@ -620,8 +620,8 @@ struct stm32_dev_s g_sdmmcdev2 = #ifdef CONFIG_MMCSD_SDIOWAIT_WRCOMPLETE .d0_gpio = GPIO_SDMMC2_D0, #endif -#ifdef CONFIG_STM32L4_SDMMC2_DMAPRIO - .dmapri = CONFIG_STM32L4_SDMMC2_DMAPRIO, +#ifdef CONFIG_STM32_SDMMC2_DMAPRIO + .dmapri = CONFIG_STM32_SDMMC2_DMAPRIO, #endif .waitsem = SEM_INITIALIZER(0), }; @@ -629,7 +629,7 @@ struct stm32_dev_s g_sdmmcdev2 = /* Register logging support */ -#ifdef CONFIG_STM32L4_SDMMC_XFRDEBUG +#ifdef CONFIG_STM32_SDMMC_XFRDEBUG static struct stm32_sampleregs_s g_sampleregs[DEBUG_NSAMPLES]; #endif @@ -779,7 +779,7 @@ static void stm32_configwaitints(struct stm32_dev_s *priv, uint32_t waitmask, priv->waitevents = waitevents; priv->wkupevent = wkupevent; priv->waitmask = waitmask; -#ifdef CONFIG_STM32L4_SDMMC_DMA +#ifdef CONFIG_STM32_SDMMC_DMA priv->xfrflags = 0; #endif sdmmc_putreg32(priv, priv->xfrmask | priv->waitmask, @@ -847,7 +847,7 @@ static void stm32_setpwrctrl(struct stm32_dev_s *priv, uint32_t pwrctrl) * ****************************************************************************/ -#ifdef CONFIG_STM32L4_SDMMC_XFRDEBUG +#ifdef CONFIG_STM32_SDMMC_XFRDEBUG static void stm32_sampleinit(void) { memset(g_sampleregs, 0xff, @@ -863,7 +863,7 @@ static void stm32_sampleinit(void) * ****************************************************************************/ -#ifdef CONFIG_STM32L4_SDMMC_XFRDEBUG +#ifdef CONFIG_STM32_SDMMC_XFRDEBUG static void stm32_sdiosample(struct stm32_dev_s *priv, struct stm32_sdioregs_s *regs) { @@ -887,12 +887,12 @@ static void stm32_sdiosample(struct stm32_dev_s *priv, * ****************************************************************************/ -#ifdef CONFIG_STM32L4_SDMMC_XFRDEBUG +#ifdef CONFIG_STM32_SDMMC_XFRDEBUG static void stm32_sample(struct stm32_dev_s *priv, int index) { struct stm32_sampleregs_s *regs = &g_sampleregs[index]; -#if defined(CONFIG_DEBUG_DMA_INFO) && defined(CONFIG_STM32L4_SDMMC_DMA) +#if defined(CONFIG_DEBUG_DMA_INFO) && defined(CONFIG_STM32_SDMMC_DMA) if (priv->dmamode) { stm32_dmasample(priv->dma, ®s->dma); @@ -911,7 +911,7 @@ static void stm32_sample(struct stm32_dev_s *priv, int index) * ****************************************************************************/ -#ifdef CONFIG_STM32L4_SDMMC_XFRDEBUG +#ifdef CONFIG_STM32_SDMMC_XFRDEBUG static void stm32_sdiodump(struct stm32_sdioregs_s *regs, const char *msg) { mcinfo("SDIO Registers: %s\n", msg); @@ -941,12 +941,12 @@ static void stm32_sdiodump(struct stm32_sdioregs_s *regs, const char *msg) * ****************************************************************************/ -#ifdef CONFIG_STM32L4_SDMMC_XFRDEBUG +#ifdef CONFIG_STM32_SDMMC_XFRDEBUG static void stm32_dumpsample(struct stm32_dev_s *priv, struct stm32_sampleregs_s *regs, const char *msg) { -#if defined(CONFIG_DEBUG_DMA_INFO) && defined(CONFIG_STM32L4_SDMMC_DMA) +#if defined(CONFIG_DEBUG_DMA_INFO) && defined(CONFIG_STM32_SDMMC_DMA) if (priv->dmamode) { stm32_dmadump(priv->dma, ®s->dma, msg); @@ -965,13 +965,13 @@ static void stm32_dumpsample(struct stm32_dev_s *priv, * ****************************************************************************/ -#ifdef CONFIG_STM32L4_SDMMC_XFRDEBUG +#ifdef CONFIG_STM32_SDMMC_XFRDEBUG static void stm32_dumpsamples(struct stm32_dev_s *priv) { stm32_dumpsample(priv, &g_sampleregs[SAMPLENDX_BEFORE_SETUP], "Before setup"); -#if defined(CONFIG_DEBUG_DMA_INFO) && defined(CONFIG_STM32L4_SDMMC_DMA) +#if defined(CONFIG_DEBUG_DMA_INFO) && defined(CONFIG_STM32_SDMMC_DMA) if (priv->dmamode) { stm32_dumpsample(priv, &g_sampleregs[SAMPLENDX_BEFORE_ENABLE], @@ -984,7 +984,7 @@ static void stm32_dumpsamples(struct stm32_dev_s *priv) stm32_dumpsample(priv, &g_sampleregs[SAMPLENDX_END_TRANSFER], "End of transfer"); -#if defined(CONFIG_DEBUG_DMA_INFO) && defined(CONFIG_STM32L4_SDMMC_DMA) +#if defined(CONFIG_DEBUG_DMA_INFO) && defined(CONFIG_STM32_SDMMC_DMA) if (priv->dmamode) { stm32_dumpsample(priv, &g_sampleregs[SAMPLENDX_DMA_CALLBACK], @@ -1002,7 +1002,7 @@ static void stm32_dumpsamples(struct stm32_dev_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32L4_SDMMC_DMA +#ifdef CONFIG_STM32_SDMMC_DMA static void stm32_dmacallback(DMA_HANDLE handle, uint8_t status, void *arg) { struct stm32_dev_s *priv = (struct stm32_dev_s *)arg; @@ -1361,7 +1361,7 @@ static void stm32_endtransfer(struct stm32_dev_s *priv, /* If this was a DMA transfer, make sure that DMA is stopped */ -#ifdef CONFIG_STM32L4_SDMMC_DMA +#ifdef CONFIG_STM32_SDMMC_DMA if (priv->dmamode) { /* DMA debug instrumentation */ @@ -1373,7 +1373,7 @@ static void stm32_endtransfer(struct stm32_dev_s *priv, * terminates on an error condition). */ - stm32l4_dmastop(priv->dma); + stm32_dmastop(priv->dma); } #endif @@ -1453,7 +1453,7 @@ static int stm32_sdmmc_interrupt(int irq, void *context, void *arg) pending = enabled & priv->xfrmask; if (pending != 0) { -#ifdef CONFIG_STM32L4_SDMMC_DMA +#ifdef CONFIG_STM32_SDMMC_DMA if (!priv->dmamode) #endif { @@ -1492,7 +1492,7 @@ static int stm32_sdmmc_interrupt(int irq, void *context, void *arg) /* Was this transfer performed in DMA mode? */ -#ifdef CONFIG_STM32L4_SDMMC_DMA +#ifdef CONFIG_STM32_SDMMC_DMA if (priv->dmamode) { /* Yes.. Terminate the transfers only if the DMA has also @@ -1684,7 +1684,7 @@ static void stm32_reset(struct sdio_dev_s *dev) priv->waitevents = 0; /* Set of events to be waited for */ priv->waitmask = 0; /* Interrupt enables for event waiting */ priv->wkupevent = 0; /* The event that caused the wakeup */ -#ifdef CONFIG_STM32L4_SDMMC_DMA +#ifdef CONFIG_STM32_SDMMC_DMA priv->xfrflags = 0; /* Used to synchronize SDIO and DMA * completion events */ #endif @@ -1700,7 +1700,7 @@ static void stm32_reset(struct sdio_dev_s *dev) /* DMA data transfer support */ priv->widebus = false; /* Required for DMA support */ -#ifdef CONFIG_STM32L4_SDMMC_DMA +#ifdef CONFIG_STM32_SDMMC_DMA priv->dmamode = false; /* true: DMA mode transfer */ #endif @@ -1739,7 +1739,7 @@ static sdio_capset_t stm32_capabilities(struct sdio_dev_s *dev) caps |= SDIO_CAPS_1BIT_ONLY; } -#ifdef CONFIG_STM32L4_SDMMC_DMA +#ifdef CONFIG_STM32_SDMMC_DMA caps |= SDIO_CAPS_DMASUPPORTED; #endif @@ -2010,7 +2010,7 @@ static int stm32_recvsetup(struct sdio_dev_s *dev, uint8_t *buffer, priv->buffer = (uint32_t *)buffer; priv->remaining = nbytes; -#ifdef CONFIG_STM32L4_SDMMC_DMA +#ifdef CONFIG_STM32_SDMMC_DMA priv->dmamode = false; #endif @@ -2065,7 +2065,7 @@ static int stm32_sendsetup(struct sdio_dev_s *dev, const priv->buffer = (uint32_t *)buffer; priv->remaining = nbytes; -#ifdef CONFIG_STM32L4_SDMMC_DMA +#ifdef CONFIG_STM32_SDMMC_DMA priv->dmamode = false; #endif @@ -2119,7 +2119,7 @@ static int stm32_cancel(struct sdio_dev_s *dev) /* If this was a DMA transfer, make sure that DMA is stopped */ -#ifdef CONFIG_STM32L4_SDMMC_DMA +#ifdef CONFIG_STM32_SDMMC_DMA if (priv->dmamode) { /* Make sure that the DMA is stopped (it will be stopped automatically @@ -2127,7 +2127,7 @@ static int stm32_cancel(struct sdio_dev_s *dev) * terminates on an error condition. */ - stm32l4_dmastop(priv->dma); + stm32_dmastop(priv->dma); } #endif @@ -2644,7 +2644,7 @@ static sdio_eventset_t stm32_eventwait(struct sdio_dev_s *dev) errout_with_waitints: stm32_configwaitints(priv, 0, 0, 0); -#ifdef CONFIG_STM32L4_SDMMC_DMA +#ifdef CONFIG_STM32_SDMMC_DMA priv->xfrflags = 0; #endif @@ -2741,7 +2741,7 @@ static int stm32_registercallback(struct sdio_dev_s *dev, * OK on success; a negated errno on failure ****************************************************************************/ -#if defined(CONFIG_STM32L4_SDMMC_DMA) && defined(CONFIG_ARCH_HAVE_SDIO_PREFLIGHT) +#if defined(CONFIG_STM32_SDMMC_DMA) && defined(CONFIG_ARCH_HAVE_SDIO_PREFLIGHT) static int stm32_dmapreflight(struct sdio_dev_s *dev, const uint8_t *buffer, size_t buflen) { @@ -2751,7 +2751,7 @@ static int stm32_dmapreflight(struct sdio_dev_s *dev, /* DMA must be possible to the buffer */ - if (!stm32l4_dmacapable((uintptr_t)buffer, (buflen + 3) >> 2, + if (!stm32_dmacapable((uintptr_t)buffer, (buflen + 3) >> 2, SDMMC_RXDMA32_CONFIG | priv->dmapri)) { return -EFAULT; @@ -2777,7 +2777,7 @@ static int stm32_dmapreflight(struct sdio_dev_s *dev, * ****************************************************************************/ -#ifdef CONFIG_STM32L4_SDMMC_DMA +#ifdef CONFIG_STM32_SDMMC_DMA static int stm32_dmarecvsetup(struct sdio_dev_s *dev, uint8_t *buffer, size_t buflen) { @@ -2818,14 +2818,14 @@ static int stm32_dmarecvsetup(struct sdio_dev_s *dev, sdmmc_modifyreg32(priv, STM32_SDMMC_DCTRL_OFFSET, 0, STM32_SDMMC_DCTRL_DMAEN); - stm32l4_dmasetup(priv->dma, priv->base + STM32_SDMMC_FIFO_OFFSET, + stm32_dmasetup(priv->dma, priv->base + STM32_SDMMC_FIFO_OFFSET, (uint32_t)buffer, (buflen + 3) >> 2, SDMMC_RXDMA32_CONFIG | priv->dmapri); /* Start the DMA */ stm32_sample(priv, SAMPLENDX_BEFORE_ENABLE); - stm32l4_dmastart(priv->dma, stm32_dmacallback, priv, false); + stm32_dmastart(priv->dma, stm32_dmacallback, priv, false); stm32_sample(priv, SAMPLENDX_AFTER_SETUP); return OK; @@ -2848,7 +2848,7 @@ static int stm32_dmarecvsetup(struct sdio_dev_s *dev, * ****************************************************************************/ -#ifdef CONFIG_STM32L4_SDMMC_DMA +#ifdef CONFIG_STM32_SDMMC_DMA static int stm32_dmasendsetup(struct sdio_dev_s *dev, const uint8_t *buffer, size_t buflen) { @@ -2883,7 +2883,7 @@ static int stm32_dmasendsetup(struct sdio_dev_s *dev, /* Configure the TX DMA */ - stm32l4_dmasetup(priv->dma, priv->base + STM32_SDMMC_FIFO_OFFSET, + stm32_dmasetup(priv->dma, priv->base + STM32_SDMMC_FIFO_OFFSET, (uint32_t)buffer, (buflen + 3) >> 2, SDMMC_TXDMA32_CONFIG | priv->dmapri); @@ -2893,7 +2893,7 @@ static int stm32_dmasendsetup(struct sdio_dev_s *dev, /* Start the DMA */ - stm32l4_dmastart(priv->dma, stm32_dmacallback, priv, false); + stm32_dmastart(priv->dma, stm32_dmacallback, priv, false); stm32_sample(priv, SAMPLENDX_AFTER_SETUP); /* Enable TX interrupts */ @@ -3028,18 +3028,18 @@ static void stm32_default(struct stm32_dev_s *priv) struct sdio_dev_s *sdio_initialize(int slotno) { struct stm32_dev_s *priv = NULL; -#ifdef CONFIG_STM32L4_SDMMC_DMA +#ifdef CONFIG_STM32_SDMMC_DMA unsigned int dmachan; #endif -#ifdef CONFIG_STM32L4_SDMMC1 +#ifdef CONFIG_STM32_SDMMC1 if (slotno == 0) { /* Select SDMMC 1 */ priv = &g_sdmmcdev1; -#ifdef CONFIG_STM32L4_SDMMC_DMA +#ifdef CONFIG_STM32_SDMMC_DMA dmachan = SDMMC1_DMACHAN; #endif @@ -3056,26 +3056,26 @@ struct sdio_dev_s *sdio_initialize(int slotno) * utility in the scope of the board support package. */ #ifndef CONFIG_SDIO_MUXBUS - stm32l4_configgpio(GPIO_SDMMC1_D0); + stm32_configgpio(GPIO_SDMMC1_D0); #ifndef CONFIG_SDMMC1_WIDTH_D1_ONLY - stm32l4_configgpio(GPIO_SDMMC1_D1); - stm32l4_configgpio(GPIO_SDMMC1_D2); - stm32l4_configgpio(GPIO_SDMMC1_D3); + stm32_configgpio(GPIO_SDMMC1_D1); + stm32_configgpio(GPIO_SDMMC1_D2); + stm32_configgpio(GPIO_SDMMC1_D3); #endif - stm32l4_configgpio(GPIO_SDMMC1_CK); - stm32l4_configgpio(GPIO_SDMMC1_CMD); + stm32_configgpio(GPIO_SDMMC1_CK); + stm32_configgpio(GPIO_SDMMC1_CMD); #endif } else #endif -#ifdef CONFIG_STM32L4_SDMMC2 +#ifdef CONFIG_STM32_SDMMC2 if (slotno == 1) { /* Select SDMMC 2 */ priv = &g_sdmmcdev2; -#ifdef CONFIG_STM32L4_SDMMC_DMA +#ifdef CONFIG_STM32_SDMMC_DMA dmachan = SDMMC2_DMACHAN; #endif @@ -3110,10 +3110,10 @@ struct sdio_dev_s *sdio_initialize(int slotno) return NULL; } -#ifdef CONFIG_STM32L4_SDMMC_DMA +#ifdef CONFIG_STM32_SDMMC_DMA /* Allocate a DMA channel */ - priv->dma = stm32l4_dmachannel(dmachan); + priv->dma = stm32_dmachannel(dmachan); DEBUGASSERT(priv->dma); #endif @@ -3211,4 +3211,4 @@ void sdio_wrprotect(struct sdio_dev_s *dev, bool wrprotect) mcinfo("cdstatus: %02x\n", priv->cdstatus); leave_critical_section(flags); } -#endif /* CONFIG_STM32L4_SDMMC1 || CONFIG_STM32L4_SDMMC2 */ +#endif /* CONFIG_STM32_SDMMC1 || CONFIG_STM32_SDMMC2 */ diff --git a/arch/arm/src/stm32l4/stm32l4_serial.c b/arch/arm/src/stm32l4/stm32l4_serial.c index bf78be0ddf899..1e3180a641b52 100644 --- a/arch/arm/src/stm32l4/stm32l4_serial.c +++ b/arch/arm/src/stm32l4/stm32l4_serial.c @@ -79,14 +79,14 @@ */ # if defined(CONFIG_USART2_RXDMA) || defined(CONFIG_USART3_RXDMA) -# if !defined(CONFIG_STM32L4_DMA1) && !defined(CONFIG_STM32L4_DMAMUX) -# error STM32L4 USART2/3 receive DMA requires CONFIG_STM32L4_DMA1 +# if !defined(CONFIG_STM32_DMA1) && !defined(CONFIG_STM32_DMAMUX) +# error STM32L4 USART2/3 receive DMA requires CONFIG_STM32_DMA1 # endif # endif # if defined(CONFIG_UART4_RXDMA) || defined(CONFIG_UART5_RXDMA) -# if !defined(CONFIG_STM32L4_DMA2) && !defined(CONFIG_STM32L4_DMAMUX) -# error STM32L4 UART4/5 receive DMA requires CONFIG_STM32L4_DMA2 +# if !defined(CONFIG_STM32_DMA2) && !defined(CONFIG_STM32_DMAMUX) +# error STM32L4 UART4/5 receive DMA requires CONFIG_STM32_DMA2 # endif # endif @@ -113,7 +113,7 @@ /* UART2-5 have no alternate channels without DMAMUX */ -# ifndef CONFIG_STM32L4_HAVE_DMAMUX +# ifndef CONFIG_STM32_HAVE_DMAMUX # define DMAMAP_USART2_RX DMACHAN_USART2_RX # define DMAMAP_USART3_RX DMACHAN_USART3_RX # define DMAMAP_UART4_RX DMACHAN_UART4_RX @@ -146,11 +146,11 @@ * can be individually invalidated. */ -# if !defined(CONFIG_STM32L4_SERIAL_RXDMA_BUFFER_SIZE) || \ - CONFIG_STM32L4_SERIAL_RXDMA_BUFFER_SIZE == 0 +# if !defined(CONFIG_STM32_SERIAL_RXDMA_BUFFER_SIZE) || \ + CONFIG_STM32_SERIAL_RXDMA_BUFFER_SIZE == 0 # define RXDMA_BUFFER_SIZE 32 # else -# define RXDMA_BUFFER_SIZE ((CONFIG_STM32L4_SERIAL_RXDMA_BUFFER_SIZE + 31) & ~31) +# define RXDMA_BUFFER_SIZE ((CONFIG_STM32_SERIAL_RXDMA_BUFFER_SIZE + 31) & ~31) # endif /* DMA priority */ @@ -182,8 +182,8 @@ /* Power management definitions */ -#if defined(CONFIG_PM) && !defined(CONFIG_STM32L4_PM_SERIAL_ACTIVITY) -# define CONFIG_STM32L4_PM_SERIAL_ACTIVITY 10 +#if defined(CONFIG_PM) && !defined(CONFIG_STM32_PM_SERIAL_ACTIVITY) +# define CONFIG_STM32_PM_SERIAL_ACTIVITY 10 #endif /* Keep track if a Break was set @@ -197,7 +197,7 @@ * See stm32l4serial_restoreusartint where the masking is done. */ -#ifdef CONFIG_STM32L4_SERIALBRK_BSDCOMPAT +#ifdef CONFIG_STM32_SERIALBRK_BSDCOMPAT # define USART_CR1_IE_BREAK_INPROGRESS_SHFTS 15 # define USART_CR1_IE_BREAK_INPROGRESS (1 << USART_CR1_IE_BREAK_INPROGRESS_SHFTS) #endif @@ -209,7 +209,7 @@ * Private Types ****************************************************************************/ -struct stm32l4_serial_s +struct stm32_serial_s { struct uart_dev_s dev; /* Generic UART device */ uint16_t ie; /* Saved interrupt mask bits value */ @@ -323,9 +323,9 @@ static int stm32l4serial_dmasetup(struct uart_dev_s *dev); static void stm32l4serial_dmashutdown(struct uart_dev_s *dev); static int stm32l4serial_dmareceive(struct uart_dev_s *dev, unsigned int *status); -static void stm32l4serial_dmareenable(struct stm32l4_serial_s *priv); +static void stm32l4serial_dmareenable(struct stm32_serial_s *priv); #ifdef CONFIG_SERIAL_IFLOWCONTROL -static bool stm32l4serial_dmaiflowrestart(struct stm32l4_serial_s *priv); +static bool stm32l4serial_dmaiflowrestart(struct stm32_serial_s *priv); #endif static void stm32l4serial_dmarxint(struct uart_dev_s *dev, bool enable); static bool stm32l4serial_dmarxavailable(struct uart_dev_s *dev); @@ -391,7 +391,7 @@ static const struct uart_ops_s g_uart_dma_ops = /* I/O buffers */ -#ifdef CONFIG_STM32L4_LPUART1_SERIALDRIVER +#ifdef CONFIG_STM32_LPUART1_SERIALDRIVER static char g_lpuart1rxbuffer[CONFIG_LPUART1_RXBUFSIZE]; static char g_lpuart1txbuffer[CONFIG_LPUART1_TXBUFSIZE]; # ifdef CONFIG_LPUART1_RXDMA @@ -399,7 +399,7 @@ static char g_lpuart1rxfifo[RXDMA_BUFFER_SIZE]; # endif #endif -#ifdef CONFIG_STM32L4_USART1_SERIALDRIVER +#ifdef CONFIG_STM32_USART1_SERIALDRIVER static char g_usart1rxbuffer[CONFIG_USART1_RXBUFSIZE]; static char g_usart1txbuffer[CONFIG_USART1_TXBUFSIZE]; # ifdef CONFIG_USART1_RXDMA @@ -407,7 +407,7 @@ static char g_usart1rxfifo[RXDMA_BUFFER_SIZE]; # endif #endif -#ifdef CONFIG_STM32L4_USART2_SERIALDRIVER +#ifdef CONFIG_STM32_USART2_SERIALDRIVER static char g_usart2rxbuffer[CONFIG_USART2_RXBUFSIZE]; static char g_usart2txbuffer[CONFIG_USART2_TXBUFSIZE]; # ifdef CONFIG_USART2_RXDMA @@ -415,7 +415,7 @@ static char g_usart2rxfifo[RXDMA_BUFFER_SIZE]; # endif #endif -#ifdef CONFIG_STM32L4_USART3_SERIALDRIVER +#ifdef CONFIG_STM32_USART3_SERIALDRIVER static char g_usart3rxbuffer[CONFIG_USART3_RXBUFSIZE]; static char g_usart3txbuffer[CONFIG_USART3_TXBUFSIZE]; # ifdef CONFIG_USART3_RXDMA @@ -423,7 +423,7 @@ static char g_usart3rxfifo[RXDMA_BUFFER_SIZE]; # endif #endif -#ifdef CONFIG_STM32L4_UART4_SERIALDRIVER +#ifdef CONFIG_STM32_UART4_SERIALDRIVER static char g_uart4rxbuffer[CONFIG_UART4_RXBUFSIZE]; static char g_uart4txbuffer[CONFIG_UART4_TXBUFSIZE]; # ifdef CONFIG_UART4_RXDMA @@ -431,7 +431,7 @@ static char g_uart4rxfifo[RXDMA_BUFFER_SIZE]; # endif #endif -#ifdef CONFIG_STM32L4_UART5_SERIALDRIVER +#ifdef CONFIG_STM32_UART5_SERIALDRIVER static char g_uart5rxbuffer[CONFIG_UART5_RXBUFSIZE]; static char g_uart5txbuffer[CONFIG_UART5_TXBUFSIZE]; # ifdef CONFIG_UART5_RXDMA @@ -441,8 +441,8 @@ static char g_uart5rxfifo[RXDMA_BUFFER_SIZE]; /* This describes the state of the STM32 LPUART1 port. */ -#ifdef CONFIG_STM32L4_LPUART1_SERIALDRIVER -static struct stm32l4_serial_s g_lpuart1priv = +#ifdef CONFIG_STM32_LPUART1_SERIALDRIVER +static struct stm32_serial_s g_lpuart1priv = { .dev = { @@ -467,13 +467,13 @@ static struct stm32l4_serial_s g_lpuart1priv = .priv = &g_lpuart1priv, }, - .irq = STM32L4_IRQ_LPUART1, + .irq = STM32_IRQ_LPUART1, .parity = CONFIG_LPUART1_PARITY, .bits = CONFIG_LPUART1_BITS, .stopbits2 = CONFIG_LPUART1_2STOP, .baud = CONFIG_LPUART1_BAUD, - .apbclock = STM32L4_PCLK1_FREQUENCY, - .usartbase = STM32L4_LPUART1_BASE, + .apbclock = STM32_PCLK1_FREQUENCY, + .usartbase = STM32_LPUART1_BASE, .tx_gpio = GPIO_LPUART1_TX, .rx_gpio = GPIO_LPUART1_RX, # if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_LPUART1_OFLOWCONTROL) @@ -503,8 +503,8 @@ static struct stm32l4_serial_s g_lpuart1priv = /* This describes the state of the STM32 USART1 port. */ -#ifdef CONFIG_STM32L4_USART1_SERIALDRIVER -static struct stm32l4_serial_s g_usart1priv = +#ifdef CONFIG_STM32_USART1_SERIALDRIVER +static struct stm32_serial_s g_usart1priv = { .dev = { @@ -529,13 +529,13 @@ static struct stm32l4_serial_s g_usart1priv = .priv = &g_usart1priv, }, - .irq = STM32L4_IRQ_USART1, + .irq = STM32_IRQ_USART1, .parity = CONFIG_USART1_PARITY, .bits = CONFIG_USART1_BITS, .stopbits2 = CONFIG_USART1_2STOP, .baud = CONFIG_USART1_BAUD, - .apbclock = STM32L4_PCLK2_FREQUENCY, - .usartbase = STM32L4_USART1_BASE, + .apbclock = STM32_PCLK2_FREQUENCY, + .usartbase = STM32_USART1_BASE, .tx_gpio = GPIO_USART1_TX, .rx_gpio = GPIO_USART1_RX, # if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_USART1_OFLOWCONTROL) @@ -565,8 +565,8 @@ static struct stm32l4_serial_s g_usart1priv = /* This describes the state of the STM32 USART2 port. */ -#ifdef CONFIG_STM32L4_USART2_SERIALDRIVER -static struct stm32l4_serial_s g_usart2priv = +#ifdef CONFIG_STM32_USART2_SERIALDRIVER +static struct stm32_serial_s g_usart2priv = { .dev = { @@ -591,13 +591,13 @@ static struct stm32l4_serial_s g_usart2priv = .priv = &g_usart2priv, }, - .irq = STM32L4_IRQ_USART2, + .irq = STM32_IRQ_USART2, .parity = CONFIG_USART2_PARITY, .bits = CONFIG_USART2_BITS, .stopbits2 = CONFIG_USART2_2STOP, .baud = CONFIG_USART2_BAUD, - .apbclock = STM32L4_PCLK1_FREQUENCY, - .usartbase = STM32L4_USART2_BASE, + .apbclock = STM32_PCLK1_FREQUENCY, + .usartbase = STM32_USART2_BASE, .tx_gpio = GPIO_USART2_TX, .rx_gpio = GPIO_USART2_RX, # if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_USART2_OFLOWCONTROL) @@ -627,8 +627,8 @@ static struct stm32l4_serial_s g_usart2priv = /* This describes the state of the STM32 USART3 port. */ -#ifdef CONFIG_STM32L4_USART3_SERIALDRIVER -static struct stm32l4_serial_s g_usart3priv = +#ifdef CONFIG_STM32_USART3_SERIALDRIVER +static struct stm32_serial_s g_usart3priv = { .dev = { @@ -653,13 +653,13 @@ static struct stm32l4_serial_s g_usart3priv = .priv = &g_usart3priv, }, - .irq = STM32L4_IRQ_USART3, + .irq = STM32_IRQ_USART3, .parity = CONFIG_USART3_PARITY, .bits = CONFIG_USART3_BITS, .stopbits2 = CONFIG_USART3_2STOP, .baud = CONFIG_USART3_BAUD, - .apbclock = STM32L4_PCLK1_FREQUENCY, - .usartbase = STM32L4_USART3_BASE, + .apbclock = STM32_PCLK1_FREQUENCY, + .usartbase = STM32_USART3_BASE, .tx_gpio = GPIO_USART3_TX, .rx_gpio = GPIO_USART3_RX, # if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_USART3_OFLOWCONTROL) @@ -689,8 +689,8 @@ static struct stm32l4_serial_s g_usart3priv = /* This describes the state of the STM32 UART4 port. */ -#ifdef CONFIG_STM32L4_UART4_SERIALDRIVER -static struct stm32l4_serial_s g_uart4priv = +#ifdef CONFIG_STM32_UART4_SERIALDRIVER +static struct stm32_serial_s g_uart4priv = { .dev = { @@ -715,7 +715,7 @@ static struct stm32l4_serial_s g_uart4priv = .priv = &g_uart4priv, }, - .irq = STM32L4_IRQ_UART4, + .irq = STM32_IRQ_UART4, .parity = CONFIG_UART4_PARITY, .bits = CONFIG_UART4_BITS, .stopbits2 = CONFIG_UART4_2STOP, @@ -728,8 +728,8 @@ static struct stm32l4_serial_s g_uart4priv = .rts_gpio = GPIO_UART4_RTS, # endif .baud = CONFIG_UART4_BAUD, - .apbclock = STM32L4_PCLK1_FREQUENCY, - .usartbase = STM32L4_UART4_BASE, + .apbclock = STM32_PCLK1_FREQUENCY, + .usartbase = STM32_UART4_BASE, .tx_gpio = GPIO_UART4_TX, .rx_gpio = GPIO_UART4_RX, # ifdef CONFIG_UART4_RXDMA @@ -751,8 +751,8 @@ static struct stm32l4_serial_s g_uart4priv = /* This describes the state of the STM32 UART5 port. */ -#ifdef CONFIG_STM32L4_UART5_SERIALDRIVER -static struct stm32l4_serial_s g_uart5priv = +#ifdef CONFIG_STM32_UART5_SERIALDRIVER +static struct stm32_serial_s g_uart5priv = { .dev = { @@ -777,7 +777,7 @@ static struct stm32l4_serial_s g_uart5priv = .priv = &g_uart5priv, }, - .irq = STM32L4_IRQ_UART5, + .irq = STM32_IRQ_UART5, .parity = CONFIG_UART5_PARITY, .bits = CONFIG_UART5_BITS, .stopbits2 = CONFIG_UART5_2STOP, @@ -790,8 +790,8 @@ static struct stm32l4_serial_s g_uart5priv = .rts_gpio = GPIO_UART5_RTS, # endif .baud = CONFIG_UART5_BAUD, - .apbclock = STM32L4_PCLK1_FREQUENCY, - .usartbase = STM32L4_UART5_BASE, + .apbclock = STM32_PCLK1_FREQUENCY, + .usartbase = STM32_UART5_BASE, .tx_gpio = GPIO_UART5_TX, .rx_gpio = GPIO_UART5_RX, # ifdef CONFIG_UART5_RXDMA @@ -813,25 +813,25 @@ static struct stm32l4_serial_s g_uart5priv = /* This table lets us iterate over the configured USARTs */ -static struct stm32l4_serial_s * -const g_uart_devs[STM32L4_NLPUART + STM32L4_NUSART + STM32L4_NUART] = +static struct stm32_serial_s * +const g_uart_devs[STM32_NLPUART + STM32_NUSART + STM32_NUART] = { -#ifdef CONFIG_STM32L4_LPUART1_SERIALDRIVER +#ifdef CONFIG_STM32_LPUART1_SERIALDRIVER [0] = &g_lpuart1priv, #endif -#ifdef CONFIG_STM32L4_USART1_SERIALDRIVER +#ifdef CONFIG_STM32_USART1_SERIALDRIVER [1] = &g_usart1priv, #endif -#ifdef CONFIG_STM32L4_USART2_SERIALDRIVER +#ifdef CONFIG_STM32_USART2_SERIALDRIVER [2] = &g_usart2priv, #endif -#ifdef CONFIG_STM32L4_USART3_SERIALDRIVER +#ifdef CONFIG_STM32_USART3_SERIALDRIVER [3] = &g_usart3priv, #endif -#ifdef CONFIG_STM32L4_UART4_SERIALDRIVER +#ifdef CONFIG_STM32_UART4_SERIALDRIVER [4] = &g_uart4priv, #endif -#ifdef CONFIG_STM32L4_UART5_SERIALDRIVER +#ifdef CONFIG_STM32_UART5_SERIALDRIVER [5] = &g_uart5priv, #endif }; @@ -858,7 +858,7 @@ static struct ****************************************************************************/ static inline -uint32_t stm32l4serial_getreg(struct stm32l4_serial_s *priv, int offset) +uint32_t stm32l4serial_getreg(struct stm32_serial_s *priv, int offset) { return getreg32(priv->usartbase + offset); } @@ -867,7 +867,7 @@ uint32_t stm32l4serial_getreg(struct stm32l4_serial_s *priv, int offset) * Name: stm32l4serial_putreg ****************************************************************************/ -static inline void stm32l4serial_putreg(struct stm32l4_serial_s *priv, +static inline void stm32l4serial_putreg(struct stm32_serial_s *priv, int offset, uint32_t value) { putreg32(value, priv->usartbase + offset); @@ -878,7 +878,7 @@ static inline void stm32l4serial_putreg(struct stm32l4_serial_s *priv, ****************************************************************************/ static inline -void stm32l4serial_setusartint(struct stm32l4_serial_s *priv, +void stm32l4serial_setusartint(struct stm32_serial_s *priv, uint16_t ie) { uint32_t cr; @@ -891,22 +891,22 @@ void stm32l4serial_setusartint(struct stm32l4_serial_s *priv, * enable/usage table above) */ - cr = stm32l4serial_getreg(priv, STM32L4_USART_CR1_OFFSET); + cr = stm32l4serial_getreg(priv, STM32_USART_CR1_OFFSET); cr &= ~(USART_CR1_USED_INTS); cr |= (ie & (USART_CR1_USED_INTS)); - stm32l4serial_putreg(priv, STM32L4_USART_CR1_OFFSET, cr); + stm32l4serial_putreg(priv, STM32_USART_CR1_OFFSET, cr); - cr = stm32l4serial_getreg(priv, STM32L4_USART_CR3_OFFSET); + cr = stm32l4serial_getreg(priv, STM32_USART_CR3_OFFSET); cr &= ~USART_CR3_EIE; cr |= (ie & USART_CR3_EIE); - stm32l4serial_putreg(priv, STM32L4_USART_CR3_OFFSET, cr); + stm32l4serial_putreg(priv, STM32_USART_CR3_OFFSET, cr); } /**************************************************************************** * Name: up_restoreusartint ****************************************************************************/ -static void stm32l4serial_restoreusartint(struct stm32l4_serial_s *priv, +static void stm32l4serial_restoreusartint(struct stm32_serial_s *priv, uint16_t ie) { irqstate_t flags; @@ -922,7 +922,7 @@ static void stm32l4serial_restoreusartint(struct stm32l4_serial_s *priv, * Name: stm32l4serial_disableusartint ****************************************************************************/ -static void stm32l4serial_disableusartint(struct stm32l4_serial_s *priv, +static void stm32l4serial_disableusartint(struct stm32_serial_s *priv, uint16_t *ie) { irqstate_t flags; @@ -959,8 +959,8 @@ static void stm32l4serial_disableusartint(struct stm32l4_serial_s *priv, * USART_CR3_CTSIE USART_ISR_CTS CTS flag (not used) */ - cr1 = stm32l4serial_getreg(priv, STM32L4_USART_CR1_OFFSET); - cr3 = stm32l4serial_getreg(priv, STM32L4_USART_CR3_OFFSET); + cr1 = stm32l4serial_getreg(priv, STM32_USART_CR1_OFFSET); + cr3 = stm32l4serial_getreg(priv, STM32_USART_CR3_OFFSET); /* Return the current interrupt mask value for the used interrupts. * Notice that this depends on the fact that none of the used interrupt @@ -988,11 +988,11 @@ static void stm32l4serial_disableusartint(struct stm32l4_serial_s *priv, ****************************************************************************/ #ifdef SERIAL_HAVE_RXDMA -static int stm32l4serial_dmanextrx(struct stm32l4_serial_s *priv) +static int stm32l4serial_dmanextrx(struct stm32_serial_s *priv) { size_t dmaresidual; - dmaresidual = stm32l4_dmaresidual(priv->rxdma); + dmaresidual = stm32_dmaresidual(priv->rxdma); return (RXDMA_BUFFER_SIZE - (int)dmaresidual); } @@ -1007,7 +1007,7 @@ static int stm32l4serial_dmanextrx(struct stm32l4_serial_s *priv) ****************************************************************************/ #ifndef CONFIG_SUPPRESS_UART_CONFIG -static void stm32l4serial_setbaud_usart(struct stm32l4_serial_s *priv) +static void stm32l4serial_setbaud_usart(struct stm32_serial_s *priv) { /* This first implementation is for U[S]ARTs that support oversampling * by 8 in additional to the standard oversampling by 16. @@ -1035,8 +1035,8 @@ static void stm32l4serial_setbaud_usart(struct stm32l4_serial_s *priv) /* Use oversamply by 8 only if the divisor is small. But what is small? */ - cr1 = stm32l4serial_getreg(priv, STM32L4_USART_CR1_OFFSET); - brr = stm32l4serial_getreg(priv, STM32L4_USART_BRR_OFFSET); + cr1 = stm32l4serial_getreg(priv, STM32_USART_CR1_OFFSET); + brr = stm32l4serial_getreg(priv, STM32_USART_BRR_OFFSET); brr &= ~(USART_BRR_MANT_MASK | USART_BRR_FRAC_MASK); if (usartdiv8 > 100) @@ -1062,8 +1062,8 @@ static void stm32l4serial_setbaud_usart(struct stm32l4_serial_s *priv) cr1 |= USART_CR1_OVER8; } - stm32l4serial_putreg(priv, STM32L4_USART_CR1_OFFSET, cr1); - stm32l4serial_putreg(priv, STM32L4_USART_BRR_OFFSET, brr); + stm32l4serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1); + stm32l4serial_putreg(priv, STM32_USART_BRR_OFFSET, brr); } #endif @@ -1076,8 +1076,8 @@ static void stm32l4serial_setbaud_usart(struct stm32l4_serial_s *priv) ****************************************************************************/ #ifndef CONFIG_SUPPRESS_UART_CONFIG -#ifdef CONFIG_STM32L4_LPUART1_SERIALDRIVER -static void stm32l4serial_setbaud_lpuart(struct stm32l4_serial_s *priv) +#ifdef CONFIG_STM32_LPUART1_SERIALDRIVER +static void stm32l4serial_setbaud_lpuart(struct stm32_serial_s *priv) { uint32_t brr; @@ -1099,7 +1099,7 @@ static void stm32l4serial_setbaud_lpuart(struct stm32l4_serial_s *priv) brr = LPUART_BRR_MIN; } - stm32l4serial_putreg(priv, STM32L4_USART_BRR_OFFSET, brr); + stm32l4serial_putreg(priv, STM32_USART_BRR_OFFSET, brr); } #endif #endif @@ -1115,14 +1115,14 @@ static void stm32l4serial_setbaud_lpuart(struct stm32l4_serial_s *priv) #ifndef CONFIG_SUPPRESS_UART_CONFIG static void stm32l4serial_setformat(struct uart_dev_s *dev) { - struct stm32l4_serial_s *priv = - (struct stm32l4_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; uint32_t regval; /* Set baud rate */ -#ifdef CONFIG_STM32L4_LPUART1_SERIALDRIVER - if (priv->usartbase == STM32L4_LPUART1_BASE) +#ifdef CONFIG_STM32_LPUART1_SERIALDRIVER + if (priv->usartbase == STM32_LPUART1_BASE) { stm32l4serial_setbaud_lpuart(priv); } @@ -1134,7 +1134,7 @@ static void stm32l4serial_setformat(struct uart_dev_s *dev) /* Configure parity mode */ - regval = stm32l4serial_getreg(priv, STM32L4_USART_CR1_OFFSET); + regval = stm32l4serial_getreg(priv, STM32_USART_CR1_OFFSET); regval &= ~(USART_CR1_PCE | USART_CR1_PS | USART_CR1_M0 | USART_CR1_M1); if (priv->parity == 1) /* Odd parity */ @@ -1172,11 +1172,11 @@ static void stm32l4serial_setformat(struct uart_dev_s *dev) * 1 start, 8 data (no parity), n stop. */ - stm32l4serial_putreg(priv, STM32L4_USART_CR1_OFFSET, regval); + stm32l4serial_putreg(priv, STM32_USART_CR1_OFFSET, regval); /* Configure STOP bits */ - regval = stm32l4serial_getreg(priv, STM32L4_USART_CR2_OFFSET); + regval = stm32l4serial_getreg(priv, STM32_USART_CR2_OFFSET); regval &= ~(USART_CR2_STOP_MASK); if (priv->stopbits2) @@ -1184,14 +1184,14 @@ static void stm32l4serial_setformat(struct uart_dev_s *dev) regval |= USART_CR2_STOP2; } - stm32l4serial_putreg(priv, STM32L4_USART_CR2_OFFSET, regval); + stm32l4serial_putreg(priv, STM32_USART_CR2_OFFSET, regval); /* Configure hardware flow control */ - regval = stm32l4serial_getreg(priv, STM32L4_USART_CR3_OFFSET); + regval = stm32l4serial_getreg(priv, STM32_USART_CR3_OFFSET); regval &= ~(USART_CR3_CTSE | USART_CR3_RTSE); -#if defined(CONFIG_SERIAL_IFLOWCONTROL) && !defined(CONFIG_STM32L4_FLOWCONTROL_BROKEN) +#if defined(CONFIG_SERIAL_IFLOWCONTROL) && !defined(CONFIG_STM32_FLOWCONTROL_BROKEN) if (priv->iflow && (priv->rts_gpio != 0)) { regval |= USART_CR3_RTSE; @@ -1205,7 +1205,7 @@ static void stm32l4serial_setformat(struct uart_dev_s *dev) } #endif - stm32l4serial_putreg(priv, STM32L4_USART_CR3_OFFSET, regval); + stm32l4serial_putreg(priv, STM32_USART_CR3_OFFSET, regval); } #endif /* CONFIG_SUPPRESS_UART_CONFIG */ @@ -1220,7 +1220,7 @@ static void stm32l4serial_setformat(struct uart_dev_s *dev) #ifdef CONFIG_PM static void stm32l4serial_setsuspend(struct uart_dev_s *dev, bool suspend) { - struct stm32l4_serial_s *priv = (struct stm32l4_serial_s *)dev->priv; + struct stm32_serial_s *priv = (struct stm32_serial_s *)dev->priv; #ifdef SERIAL_HAVE_RXDMA bool dmarestored = false; #endif @@ -1239,7 +1239,7 @@ static void stm32l4serial_setsuspend(struct uart_dev_s *dev, bool suspend) { /* Force RTS high to prevent further Rx. */ - stm32l4_configgpio((priv->rts_gpio & ~GPIO_MODE_MASK) + stm32_configgpio((priv->rts_gpio & ~GPIO_MODE_MASK) | (GPIO_OUTPUT | GPIO_OUTPUT_SET)); } #endif @@ -1250,7 +1250,7 @@ static void stm32l4serial_setsuspend(struct uart_dev_s *dev, bool suspend) /* Wait last Tx to complete. */ - while ((stm32l4serial_getreg(priv, STM32L4_USART_ISR_OFFSET) & + while ((stm32l4serial_getreg(priv, STM32_USART_ISR_OFFSET) & USART_ISR_TC) == 0); #ifdef SERIAL_HAVE_RXDMA @@ -1268,7 +1268,7 @@ static void stm32l4serial_setsuspend(struct uart_dev_s *dev, bool suspend) { /* Suspend Rx DMA. */ - stm32l4_dmastop(priv->rxdma); + stm32_dmastop(priv->rxdma); priv->rxdmasusp = true; } } @@ -1309,7 +1309,7 @@ static void stm32l4serial_setsuspend(struct uart_dev_s *dev, bool suspend) { /* Restore peripheral RTS control. */ - stm32l4_configgpio(priv->rts_gpio); + stm32_configgpio(priv->rts_gpio); } #endif } @@ -1356,9 +1356,9 @@ static void stm32l4serial_pm_setsuspend(bool suspend) g_serialpm.serial_suspended = suspend; - for (n = 0; n < STM32L4_NLPUART + STM32L4_NUSART + STM32L4_NUART; n++) + for (n = 0; n < STM32_NLPUART + STM32_NUSART + STM32_NUART; n++) { - struct stm32l4_serial_s *priv = g_uart_devs[n]; + struct stm32_serial_s *priv = g_uart_devs[n]; if (!priv || !priv->initialized) { @@ -1384,8 +1384,8 @@ static void stm32l4serial_pm_setsuspend(bool suspend) static void stm32l4serial_setapbclock(struct uart_dev_s *dev, bool on) { - struct stm32l4_serial_s *priv = - (struct stm32l4_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; uint32_t rcc_en; uint32_t regaddr; @@ -1395,40 +1395,40 @@ static void stm32l4serial_setapbclock(struct uart_dev_s *dev, bool on) { default: return; -#ifdef CONFIG_STM32L4_LPUART1_SERIALDRIVER - case STM32L4_LPUART1_BASE: +#ifdef CONFIG_STM32_LPUART1_SERIALDRIVER + case STM32_LPUART1_BASE: rcc_en = RCC_APB1ENR2_LPUART1EN; - regaddr = STM32L4_RCC_APB1ENR2; + regaddr = STM32_RCC_APB1ENR2; break; #endif -#ifdef CONFIG_STM32L4_USART1_SERIALDRIVER - case STM32L4_USART1_BASE: +#ifdef CONFIG_STM32_USART1_SERIALDRIVER + case STM32_USART1_BASE: rcc_en = RCC_APB2ENR_USART1EN; - regaddr = STM32L4_RCC_APB2ENR; + regaddr = STM32_RCC_APB2ENR; break; #endif -#ifdef CONFIG_STM32L4_USART2_SERIALDRIVER - case STM32L4_USART2_BASE: +#ifdef CONFIG_STM32_USART2_SERIALDRIVER + case STM32_USART2_BASE: rcc_en = RCC_APB1ENR1_USART2EN; - regaddr = STM32L4_RCC_APB1ENR1; + regaddr = STM32_RCC_APB1ENR1; break; #endif -#ifdef CONFIG_STM32L4_USART3_SERIALDRIVER - case STM32L4_USART3_BASE: +#ifdef CONFIG_STM32_USART3_SERIALDRIVER + case STM32_USART3_BASE: rcc_en = RCC_APB1ENR1_USART3EN; - regaddr = STM32L4_RCC_APB1ENR1; + regaddr = STM32_RCC_APB1ENR1; break; #endif -#ifdef CONFIG_STM32L4_UART4_SERIALDRIVER - case STM32L4_UART4_BASE: +#ifdef CONFIG_STM32_UART4_SERIALDRIVER + case STM32_UART4_BASE: rcc_en = RCC_APB1ENR1_UART4EN; - regaddr = STM32L4_RCC_APB1ENR1; + regaddr = STM32_RCC_APB1ENR1; break; #endif -#ifdef CONFIG_STM32L4_UART5_SERIALDRIVER - case STM32L4_UART5_BASE: +#ifdef CONFIG_STM32_UART5_SERIALDRIVER + case STM32_UART5_BASE: rcc_en = RCC_APB1ENR1_UART5EN; - regaddr = STM32L4_RCC_APB1ENR1; + regaddr = STM32_RCC_APB1ENR1; break; #endif } @@ -1456,14 +1456,14 @@ static void stm32l4serial_setapbclock(struct uart_dev_s *dev, bool on) static int stm32l4serial_setup(struct uart_dev_s *dev) { - struct stm32l4_serial_s *priv = - (struct stm32l4_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; #ifndef CONFIG_SUPPRESS_UART_CONFIG uint32_t regval; /* Note: The logic here depends on the fact that that the USART module - * was enabled in stm32l4_lowsetup(). + * was enabled in stm32_lowsetup(). */ /* Enable USART APB1/2 clock */ @@ -1474,18 +1474,18 @@ static int stm32l4serial_setup(struct uart_dev_s *dev) if (priv->tx_gpio != 0) { - stm32l4_configgpio(priv->tx_gpio); + stm32_configgpio(priv->tx_gpio); } if (priv->rx_gpio != 0) { - stm32l4_configgpio(priv->rx_gpio); + stm32_configgpio(priv->rx_gpio); } #ifdef CONFIG_SERIAL_OFLOWCONTROL if (priv->cts_gpio != 0) { - stm32l4_configgpio(priv->cts_gpio); + stm32_configgpio(priv->cts_gpio); } #endif @@ -1494,20 +1494,20 @@ static int stm32l4serial_setup(struct uart_dev_s *dev) { uint32_t config = priv->rts_gpio; -#ifdef CONFIG_STM32L4_FLOWCONTROL_BROKEN +#ifdef CONFIG_STM32_FLOWCONTROL_BROKEN /* Instead of letting hw manage this pin, we will bitbang */ config = (config & ~GPIO_MODE_MASK) | GPIO_OUTPUT; #endif - stm32l4_configgpio(config); + stm32_configgpio(config); } #endif #ifdef HAVE_RS485 if (priv->rs485_dir_gpio != 0) { - stm32l4_configgpio(priv->rs485_dir_gpio); - stm32l4_gpiowrite(priv->rs485_dir_gpio, !priv->rs485_dir_polarity); + stm32_configgpio(priv->rs485_dir_gpio); + stm32_gpiowrite(priv->rs485_dir_gpio, !priv->rs485_dir_polarity); } #endif @@ -1515,7 +1515,7 @@ static int stm32l4serial_setup(struct uart_dev_s *dev) /* Clear STOP, CLKEN, CPOL, CPHA, LBCL, and interrupt enable bits */ - regval = stm32l4serial_getreg(priv, STM32L4_USART_CR2_OFFSET); + regval = stm32l4serial_getreg(priv, STM32_USART_CR2_OFFSET); regval &= ~(USART_CR2_STOP_MASK | USART_CR2_CLKEN | USART_CR2_CPOL | USART_CR2_CPHA | USART_CR2_LBCL | USART_CR2_LBDIE); @@ -1526,26 +1526,26 @@ static int stm32l4serial_setup(struct uart_dev_s *dev) regval |= USART_CR2_STOP2; } - stm32l4serial_putreg(priv, STM32L4_USART_CR2_OFFSET, regval); + stm32l4serial_putreg(priv, STM32_USART_CR2_OFFSET, regval); /* Configure CR1 */ /* Clear TE, REm and all interrupt enable bits */ - regval = stm32l4serial_getreg(priv, STM32L4_USART_CR1_OFFSET); + regval = stm32l4serial_getreg(priv, STM32_USART_CR1_OFFSET); regval &= ~(USART_CR1_TE | USART_CR1_RE | USART_CR1_ALLINTS); - stm32l4serial_putreg(priv, STM32L4_USART_CR1_OFFSET, regval); + stm32l4serial_putreg(priv, STM32_USART_CR1_OFFSET, regval); /* Configure CR3 */ /* Clear CTSE, RTSE, and all interrupt enable bits */ - regval = stm32l4serial_getreg(priv, STM32L4_USART_CR3_OFFSET); + regval = stm32l4serial_getreg(priv, STM32_USART_CR3_OFFSET); regval &= ~(USART_CR3_CTSIE | USART_CR3_CTSE | USART_CR3_RTSE | USART_CR3_EIE); - stm32l4serial_putreg(priv, STM32L4_USART_CR3_OFFSET, regval); + stm32l4serial_putreg(priv, STM32_USART_CR3_OFFSET, regval); /* Configure the USART line format and speed. */ @@ -1553,9 +1553,9 @@ static int stm32l4serial_setup(struct uart_dev_s *dev) /* Enable Rx, Tx, and the USART */ - regval = stm32l4serial_getreg(priv, STM32L4_USART_CR1_OFFSET); + regval = stm32l4serial_getreg(priv, STM32_USART_CR1_OFFSET); regval |= (USART_CR1_UE | USART_CR1_TE | USART_CR1_RE); - stm32l4serial_putreg(priv, STM32L4_USART_CR1_OFFSET, regval); + stm32l4serial_putreg(priv, STM32_USART_CR1_OFFSET, regval); #endif /* CONFIG_SUPPRESS_UART_CONFIG */ @@ -1582,8 +1582,8 @@ static int stm32l4serial_setup(struct uart_dev_s *dev) #ifdef SERIAL_HAVE_RXDMA static int stm32l4serial_dmasetup(struct uart_dev_s *dev) { - struct stm32l4_serial_s *priv = - (struct stm32l4_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; int result; uint32_t regval; @@ -1600,15 +1600,15 @@ static int stm32l4serial_dmasetup(struct uart_dev_s *dev) /* Acquire the DMA channel. This should always succeed. */ - priv->rxdma = stm32l4_dmachannel(priv->rxdma_channel); + priv->rxdma = stm32_dmachannel(priv->rxdma_channel); #ifdef CONFIG_SERIAL_IFLOWCONTROL if (priv->iflow) { /* Configure for non-circular DMA reception into the RX FIFO */ - stm32l4_dmasetup(priv->rxdma, - priv->usartbase + STM32L4_USART_RDR_OFFSET, + stm32_dmasetup(priv->rxdma, + priv->usartbase + STM32_USART_RDR_OFFSET, (uint32_t)priv->rxfifo, RXDMA_BUFFER_SIZE, SERIAL_DMA_IFLOW_CONTROL_WORD); @@ -1618,8 +1618,8 @@ static int stm32l4serial_dmasetup(struct uart_dev_s *dev) { /* Configure for circular DMA reception into the RX FIFO */ - stm32l4_dmasetup(priv->rxdma, - priv->usartbase + STM32L4_USART_RDR_OFFSET, + stm32_dmasetup(priv->rxdma, + priv->usartbase + STM32_USART_RDR_OFFSET, (uint32_t)priv->rxfifo, RXDMA_BUFFER_SIZE, SERIAL_DMA_CONTROL_WORD); @@ -1633,9 +1633,9 @@ static int stm32l4serial_dmasetup(struct uart_dev_s *dev) /* Enable receive DMA for the UART */ - regval = stm32l4serial_getreg(priv, STM32L4_USART_CR3_OFFSET); + regval = stm32l4serial_getreg(priv, STM32_USART_CR3_OFFSET); regval |= USART_CR3_DMAR; - stm32l4serial_putreg(priv, STM32L4_USART_CR3_OFFSET, regval); + stm32l4serial_putreg(priv, STM32_USART_CR3_OFFSET, regval); #ifdef CONFIG_SERIAL_IFLOWCONTROL if (priv->iflow) @@ -1645,7 +1645,7 @@ static int stm32l4serial_dmasetup(struct uart_dev_s *dev) * in and DMA transfer is stopped. */ - stm32l4_dmastart(priv->rxdma, stm32l4serial_dmarxcallback, + stm32_dmastart(priv->rxdma, stm32l4serial_dmarxcallback, (void *)priv, false); } else @@ -1656,7 +1656,7 @@ static int stm32l4serial_dmasetup(struct uart_dev_s *dev) * worth of time to claim bytes before they are overwritten. */ - stm32l4_dmastart(priv->rxdma, stm32l4serial_dmarxcallback, + stm32_dmastart(priv->rxdma, stm32l4serial_dmarxcallback, (void *)priv, true); } @@ -1675,8 +1675,8 @@ static int stm32l4serial_dmasetup(struct uart_dev_s *dev) static void stm32l4serial_shutdown(struct uart_dev_s *dev) { - struct stm32l4_serial_s *priv = - (struct stm32l4_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; uint32_t regval; /* Mark device as uninitialized. */ @@ -1693,9 +1693,9 @@ static void stm32l4serial_shutdown(struct uart_dev_s *dev) /* Disable Rx, Tx, and the UART */ - regval = stm32l4serial_getreg(priv, STM32L4_USART_CR1_OFFSET); + regval = stm32l4serial_getreg(priv, STM32_USART_CR1_OFFSET); regval &= ~(USART_CR1_UE | USART_CR1_TE | USART_CR1_RE); - stm32l4serial_putreg(priv, STM32L4_USART_CR1_OFFSET, regval); + stm32l4serial_putreg(priv, STM32_USART_CR1_OFFSET, regval); /* Release pins. "If the serial-attached device is powered down, the TX * pin causes back-powering, potentially confusing the device to the point @@ -1707,32 +1707,32 @@ static void stm32l4serial_shutdown(struct uart_dev_s *dev) if (priv->tx_gpio != 0) { - stm32l4_unconfiggpio(priv->tx_gpio); + stm32_unconfiggpio(priv->tx_gpio); } if (priv->rx_gpio != 0) { - stm32l4_unconfiggpio(priv->rx_gpio); + stm32_unconfiggpio(priv->rx_gpio); } #ifdef CONFIG_SERIAL_OFLOWCONTROL if (priv->cts_gpio != 0) { - stm32l4_unconfiggpio(priv->cts_gpio); + stm32_unconfiggpio(priv->cts_gpio); } #endif #ifdef CONFIG_SERIAL_IFLOWCONTROL if (priv->rts_gpio != 0) { - stm32l4_unconfiggpio(priv->rts_gpio); + stm32_unconfiggpio(priv->rts_gpio); } #endif #ifdef HAVE_RS485 if (priv->rs485_dir_gpio != 0) { - stm32l4_unconfiggpio(priv->rs485_dir_gpio); + stm32_unconfiggpio(priv->rs485_dir_gpio); } #endif } @@ -1749,8 +1749,8 @@ static void stm32l4serial_shutdown(struct uart_dev_s *dev) #ifdef SERIAL_HAVE_RXDMA static void stm32l4serial_dmashutdown(struct uart_dev_s *dev) { - struct stm32l4_serial_s *priv = - (struct stm32l4_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; /* Perform the normal UART shutdown */ @@ -1758,11 +1758,11 @@ static void stm32l4serial_dmashutdown(struct uart_dev_s *dev) /* Stop the DMA channel */ - stm32l4_dmastop(priv->rxdma); + stm32_dmastop(priv->rxdma); /* Release the DMA channel */ - stm32l4_dmafree(priv->rxdma); + stm32_dmafree(priv->rxdma); priv->rxdma = NULL; } #endif @@ -1785,8 +1785,8 @@ static void stm32l4serial_dmashutdown(struct uart_dev_s *dev) static int stm32l4serial_attach(struct uart_dev_s *dev) { - struct stm32l4_serial_s *priv = - (struct stm32l4_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; int ret; /* Attach and enable the IRQ */ @@ -1816,8 +1816,8 @@ static int stm32l4serial_attach(struct uart_dev_s *dev) static void stm32l4serial_detach(struct uart_dev_s *dev) { - struct stm32l4_serial_s *priv = - (struct stm32l4_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; up_disable_irq(priv->irq); irq_detach(priv->irq); } @@ -1836,7 +1836,7 @@ static void stm32l4serial_detach(struct uart_dev_s *dev) static int up_interrupt(int irq, void *context, void *arg) { - struct stm32l4_serial_s *priv = (struct stm32l4_serial_s *)arg; + struct stm32_serial_s *priv = (struct stm32_serial_s *)arg; int passes; bool handled; @@ -1844,8 +1844,8 @@ static int up_interrupt(int irq, void *context, void *arg) /* Report serial activity to the power management logic */ -#if defined(CONFIG_PM) && CONFIG_STM32L4_PM_SERIAL_ACTIVITY > 0 - pm_activity(PM_IDLE_DOMAIN, CONFIG_STM32L4_PM_SERIAL_ACTIVITY); +#if defined(CONFIG_PM) && CONFIG_STM32_PM_SERIAL_ACTIVITY > 0 + pm_activity(PM_IDLE_DOMAIN, CONFIG_STM32_PM_SERIAL_ACTIVITY); #endif /* Loop until there are no characters to be transferred or, @@ -1859,7 +1859,7 @@ static int up_interrupt(int irq, void *context, void *arg) /* Get the masked USART status word. */ - priv->sr = stm32l4serial_getreg(priv, STM32L4_USART_ISR_OFFSET); + priv->sr = stm32l4serial_getreg(priv, STM32_USART_ISR_OFFSET); /* USART interrupts: * @@ -1901,7 +1901,7 @@ static int up_interrupt(int irq, void *context, void *arg) (priv->ie & USART_CR1_TCIE) != 0 && (priv->ie & USART_CR1_TXEIE) == 0) { - stm32l4_gpiowrite(priv->rs485_dir_gpio, !priv->rs485_dir_polarity); + stm32_gpiowrite(priv->rs485_dir_gpio, !priv->rs485_dir_polarity); stm32l4serial_restoreusartint(priv, priv->ie & ~USART_CR1_TCIE); } #endif @@ -1931,7 +1931,7 @@ static int up_interrupt(int irq, void *context, void *arg) * interrupt clear register (ICR). */ - stm32l4serial_putreg(priv, STM32L4_USART_ICR_OFFSET, + stm32l4serial_putreg(priv, STM32_USART_ICR_OFFSET, (USART_ICR_NCF | USART_ICR_ORECF | USART_ICR_FECF)); } @@ -1967,8 +1967,8 @@ static int stm32l4serial_ioctl(struct file *filep, int cmd, struct uart_dev_s *dev = inode->i_private; #endif #if defined(CONFIG_SERIAL_TERMIOS) - struct stm32l4_serial_s *priv = - (struct stm32l4_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; #endif int ret = OK; @@ -1977,21 +1977,21 @@ static int stm32l4serial_ioctl(struct file *filep, int cmd, #ifdef CONFIG_SERIAL_TIOCSERGSTRUCT case TIOCSERGSTRUCT: { - struct stm32l4_serial_s *user = - (struct stm32l4_serial_s *)arg; + struct stm32_serial_s *user = + (struct stm32_serial_s *)arg; if (!user) { ret = -EINVAL; } else { - memcpy(user, dev, sizeof(struct stm32l4_serial_s)); + memcpy(user, dev, sizeof(struct stm32_serial_s)); } } break; #endif -#ifdef CONFIG_STM32L4_USART_SINGLEWIRE +#ifdef CONFIG_STM32_USART_SINGLEWIRE case TIOCSSINGLEWIRE: { uint32_t cr1; @@ -2002,19 +2002,19 @@ static int stm32l4serial_ioctl(struct file *filep, int cmd, /* Get the original state of UE */ - cr1 = stm32l4serial_getreg(priv, STM32L4_USART_CR1_OFFSET); + cr1 = stm32l4serial_getreg(priv, STM32_USART_CR1_OFFSET); cr1_ue = cr1 & USART_CR1_UE; cr1 &= ~USART_CR1_UE; /* Disable UE, HDSEL can only be written when UE=0 */ - stm32l4serial_putreg(priv, STM32L4_USART_CR1_OFFSET, cr1); + stm32l4serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1); /* Change the TX port to be open-drain/push-pull and enable/disable * half-duplex mode. */ - uint32_t cr = stm32l4serial_getreg(priv, STM32L4_USART_CR3_OFFSET); + uint32_t cr = stm32l4serial_getreg(priv, STM32_USART_CR3_OFFSET); if ((arg & SER_SINGLEWIRE_ENABLED) != 0) { @@ -2031,7 +2031,7 @@ static int stm32l4serial_ioctl(struct file *filep, int cmd, if (priv->tx_gpio != 0) { - stm32l4_configgpio((priv->tx_gpio & ~(GPIO_PUPD_MASK | + stm32_configgpio((priv->tx_gpio & ~(GPIO_PUPD_MASK | GPIO_OPENDRAIN)) | gpio_val); } @@ -2042,7 +2042,7 @@ static int stm32l4serial_ioctl(struct file *filep, int cmd, { if (priv->tx_gpio != 0) { - stm32l4_configgpio((priv->tx_gpio & ~(GPIO_PUPD_MASK | + stm32_configgpio((priv->tx_gpio & ~(GPIO_PUPD_MASK | GPIO_OPENDRAIN)) | GPIO_PUSHPULL); } @@ -2050,17 +2050,17 @@ static int stm32l4serial_ioctl(struct file *filep, int cmd, cr &= ~USART_CR3_HDSEL; } - stm32l4serial_putreg(priv, STM32L4_USART_CR3_OFFSET, cr); + stm32l4serial_putreg(priv, STM32_USART_CR3_OFFSET, cr); /* Re-enable UE if appropriate */ - stm32l4serial_putreg(priv, STM32L4_USART_CR1_OFFSET, cr1 | cr1_ue); + stm32l4serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1 | cr1_ue); leave_critical_section(flags); } break; #endif -#ifdef CONFIG_STM32L4_USART_INVERT +#ifdef CONFIG_STM32_USART_INVERT case TIOCSINVERT: { uint32_t cr1; @@ -2071,17 +2071,17 @@ static int stm32l4serial_ioctl(struct file *filep, int cmd, /* Get the original state of UE */ - cr1 = stm32l4serial_getreg(priv, STM32L4_USART_CR1_OFFSET); + cr1 = stm32l4serial_getreg(priv, STM32_USART_CR1_OFFSET); cr1_ue = cr1 & USART_CR1_UE; cr1 &= ~USART_CR1_UE; /* Disable UE, {R,T}XINV can only be written when UE=0 */ - stm32l4serial_putreg(priv, STM32L4_USART_CR1_OFFSET, cr1); + stm32l4serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1); /* Enable/disable signal inversion. */ - uint32_t cr = stm32l4serial_getreg(priv, STM32L4_USART_CR2_OFFSET); + uint32_t cr = stm32l4serial_getreg(priv, STM32_USART_CR2_OFFSET); if (arg & SER_INVERT_ENABLED_RX) { @@ -2101,17 +2101,17 @@ static int stm32l4serial_ioctl(struct file *filep, int cmd, cr &= ~USART_CR2_TXINV; } - stm32l4serial_putreg(priv, STM32L4_USART_CR2_OFFSET, cr); + stm32l4serial_putreg(priv, STM32_USART_CR2_OFFSET, cr); /* Re-enable UE if appropriate */ - stm32l4serial_putreg(priv, STM32L4_USART_CR1_OFFSET, cr1 | cr1_ue); + stm32l4serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1 | cr1_ue); leave_critical_section(flags); } break; #endif -#ifdef CONFIG_STM32L4_USART_SWAP +#ifdef CONFIG_STM32_USART_SWAP case TIOCSSWAP: { uint32_t cr1; @@ -2122,17 +2122,17 @@ static int stm32l4serial_ioctl(struct file *filep, int cmd, /* Get the original state of UE */ - cr1 = stm32l4serial_getreg(priv, STM32L4_USART_CR1_OFFSET); + cr1 = stm32l4serial_getreg(priv, STM32_USART_CR1_OFFSET); cr1_ue = cr1 & USART_CR1_UE; cr1 &= ~USART_CR1_UE; /* Disable UE, SWAP can only be written when UE=0 */ - stm32l4serial_putreg(priv, STM32L4_USART_CR1_OFFSET, cr1); + stm32l4serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1); /* Enable/disable Swap mode. */ - uint32_t cr = stm32l4serial_getreg(priv, STM32L4_USART_CR2_OFFSET); + uint32_t cr = stm32l4serial_getreg(priv, STM32_USART_CR2_OFFSET); if (arg == SER_SWAP_ENABLED) { @@ -2143,11 +2143,11 @@ static int stm32l4serial_ioctl(struct file *filep, int cmd, cr &= ~USART_CR2_SWAP; } - stm32l4serial_putreg(priv, STM32L4_USART_CR2_OFFSET, cr); + stm32l4serial_putreg(priv, STM32_USART_CR2_OFFSET, cr); /* Re-enable UE if appropriate */ - stm32l4serial_putreg(priv, STM32L4_USART_CR1_OFFSET, cr1 | cr1_ue); + stm32l4serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1 | cr1_ue); leave_critical_section(flags); } break; @@ -2248,8 +2248,8 @@ static int stm32l4serial_ioctl(struct file *filep, int cmd, break; #endif /* CONFIG_SERIAL_TERMIOS */ -#ifdef CONFIG_STM32L4_USART_BREAKS -# ifdef CONFIG_STM32L4_SERIALBRK_BSDCOMPAT +#ifdef CONFIG_STM32_USART_BREAKS +# ifdef CONFIG_STM32_SERIALBRK_BSDCOMPAT case TIOCSBRK: /* BSD compatibility: Turn break on, unconditionally */ { irqstate_t flags; @@ -2268,7 +2268,7 @@ static int stm32l4serial_ioctl(struct file *filep, int cmd, { uint32_t tx_break = GPIO_OUTPUT | (~(GPIO_MODE_MASK | GPIO_OUTPUT_SET) & priv->tx_gpio); - stm32l4_configgpio(tx_break); + stm32_configgpio(tx_break); } leave_critical_section(flags); @@ -2285,7 +2285,7 @@ static int stm32l4serial_ioctl(struct file *filep, int cmd, if (priv->tx_gpio != 0) { - stm32l4_configgpio(priv->tx_gpio); + stm32_configgpio(priv->tx_gpio); } priv->ie &= ~USART_CR1_IE_BREAK_INPROGRESS; @@ -2304,8 +2304,8 @@ static int stm32l4serial_ioctl(struct file *filep, int cmd, irqstate_t flags; flags = enter_critical_section(); - cr1 = stm32l4serial_getreg(priv, STM32L4_USART_CR1_OFFSET); - stm32l4serial_putreg(priv, STM32L4_USART_CR1_OFFSET, + cr1 = stm32l4serial_getreg(priv, STM32_USART_CR1_OFFSET); + stm32l4serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1 | USART_CR1_SBK); leave_critical_section(flags); } @@ -2317,8 +2317,8 @@ static int stm32l4serial_ioctl(struct file *filep, int cmd, irqstate_t flags; flags = enter_critical_section(); - cr1 = stm32l4serial_getreg(priv, STM32L4_USART_CR1_OFFSET); - stm32l4serial_putreg(priv, STM32L4_USART_CR1_OFFSET, + cr1 = stm32l4serial_getreg(priv, STM32_USART_CR1_OFFSET); + stm32l4serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1 & ~USART_CR1_SBK); leave_critical_section(flags); } @@ -2348,13 +2348,13 @@ static int stm32l4serial_ioctl(struct file *filep, int cmd, static int stm32l4serial_receive(struct uart_dev_s *dev, unsigned int *status) { - struct stm32l4_serial_s *priv = - (struct stm32l4_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; uint32_t rdr; /* Get the Rx byte */ - rdr = stm32l4serial_getreg(priv, STM32L4_USART_RDR_OFFSET); + rdr = stm32l4serial_getreg(priv, STM32_USART_RDR_OFFSET); /* Get the Rx byte plux error information. Return those in status */ @@ -2378,8 +2378,8 @@ static int stm32l4serial_receive(struct uart_dev_s *dev, #ifndef SERIAL_HAVE_ONLY_DMA static void stm32l4serial_rxint(struct uart_dev_s *dev, bool enable) { - struct stm32l4_serial_s *priv = - (struct stm32l4_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; irqstate_t flags; uint16_t ie; @@ -2441,10 +2441,10 @@ static void stm32l4serial_rxint(struct uart_dev_s *dev, bool enable) #ifndef SERIAL_HAVE_ONLY_DMA static bool stm32l4serial_rxavailable(struct uart_dev_s *dev) { - struct stm32l4_serial_s *priv = - (struct stm32l4_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; - return ((stm32l4serial_getreg(priv, STM32L4_USART_ISR_OFFSET) & + return ((stm32l4serial_getreg(priv, STM32_USART_ISR_OFFSET) & USART_ISR_RXNE) != 0); } #endif @@ -2476,16 +2476,16 @@ static bool stm32l4serial_rxavailable(struct uart_dev_s *dev) static bool stm32l4serial_rxflowcontrol(struct uart_dev_s *dev, unsigned int nbuffered, bool upper) { - struct stm32l4_serial_s *priv = - (struct stm32l4_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; #if defined(CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS) && \ - defined(CONFIG_STM32L4_FLOWCONTROL_BROKEN) + defined(CONFIG_STM32_FLOWCONTROL_BROKEN) if (priv->iflow && (priv->rts_gpio != 0)) { /* Assert/de-assert nRTS set it high resume/stop sending */ - stm32l4_gpiowrite(priv->rts_gpio, upper); + stm32_gpiowrite(priv->rts_gpio, upper); if (upper) { @@ -2560,8 +2560,8 @@ static bool stm32l4serial_rxflowcontrol(struct uart_dev_s *dev, static int stm32l4serial_dmareceive(struct uart_dev_s *dev, unsigned int *status) { - struct stm32l4_serial_s *priv = - (struct stm32l4_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; int c = 0; if (stm32l4serial_dmanextrx(priv) != priv->rxdmanext) @@ -2599,15 +2599,15 @@ static int stm32l4serial_dmareceive(struct uart_dev_s *dev, ****************************************************************************/ #if defined(SERIAL_HAVE_RXDMA) -static void stm32l4serial_dmareenable(struct stm32l4_serial_s *priv) +static void stm32l4serial_dmareenable(struct stm32_serial_s *priv) { #ifdef CONFIG_SERIAL_IFLOWCONTROL if (priv->iflow) { /* Configure for non-circular DMA reception into the RX FIFO */ - stm32l4_dmasetup(priv->rxdma, - priv->usartbase + STM32L4_USART_RDR_OFFSET, + stm32_dmasetup(priv->rxdma, + priv->usartbase + STM32_USART_RDR_OFFSET, (uint32_t)priv->rxfifo, RXDMA_BUFFER_SIZE, SERIAL_DMA_IFLOW_CONTROL_WORD); @@ -2617,8 +2617,8 @@ static void stm32l4serial_dmareenable(struct stm32l4_serial_s *priv) { /* Configure for circular DMA reception into the RX FIFO */ - stm32l4_dmasetup(priv->rxdma, - priv->usartbase + STM32L4_USART_RDR_OFFSET, + stm32_dmasetup(priv->rxdma, + priv->usartbase + STM32_USART_RDR_OFFSET, (uint32_t)priv->rxfifo, RXDMA_BUFFER_SIZE, SERIAL_DMA_CONTROL_WORD); @@ -2638,7 +2638,7 @@ static void stm32l4serial_dmareenable(struct stm32l4_serial_s *priv) * in and DMA transfer is stopped. */ - stm32l4_dmastart(priv->rxdma, stm32l4serial_dmarxcallback, + stm32_dmastart(priv->rxdma, stm32l4serial_dmarxcallback, (void *)priv, false); } else @@ -2649,7 +2649,7 @@ static void stm32l4serial_dmareenable(struct stm32l4_serial_s *priv) * worth of time to claim bytes before they are overwritten. */ - stm32l4_dmastart(priv->rxdma, stm32l4serial_dmarxcallback, + stm32_dmastart(priv->rxdma, stm32l4serial_dmarxcallback, (void *)priv, true); } @@ -2670,7 +2670,7 @@ static void stm32l4serial_dmareenable(struct stm32l4_serial_s *priv) ****************************************************************************/ #if defined(SERIAL_HAVE_RXDMA) && defined(CONFIG_SERIAL_IFLOWCONTROL) -static bool stm32l4serial_dmaiflowrestart(struct stm32l4_serial_s *priv) +static bool stm32l4serial_dmaiflowrestart(struct stm32_serial_s *priv) { if (!priv->rxenable) { @@ -2721,8 +2721,8 @@ static bool stm32l4serial_dmaiflowrestart(struct stm32l4_serial_s *priv) #ifdef SERIAL_HAVE_RXDMA static void stm32l4serial_dmarxint(struct uart_dev_s *dev, bool enable) { - struct stm32l4_serial_s *priv = - (struct stm32l4_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; /* En/disable DMA reception. * @@ -2756,8 +2756,8 @@ static void stm32l4serial_dmarxint(struct uart_dev_s *dev, bool enable) #ifdef SERIAL_HAVE_RXDMA static bool stm32l4serial_dmarxavailable(struct uart_dev_s *dev) { - struct stm32l4_serial_s *priv = - (struct stm32l4_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; /* Compare our receive pointer to the current DMA pointer, if they * do not match, then there are bytes to be received. @@ -2777,17 +2777,17 @@ static bool stm32l4serial_dmarxavailable(struct uart_dev_s *dev) static void stm32l4serial_send(struct uart_dev_s *dev, int ch) { - struct stm32l4_serial_s *priv = - (struct stm32l4_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; #ifdef HAVE_RS485 if (priv->rs485_dir_gpio != 0) { - stm32l4_gpiowrite(priv->rs485_dir_gpio, priv->rs485_dir_polarity); + stm32_gpiowrite(priv->rs485_dir_gpio, priv->rs485_dir_polarity); } #endif - stm32l4serial_putreg(priv, STM32L4_USART_TDR_OFFSET, (uint32_t)ch); + stm32l4serial_putreg(priv, STM32_USART_TDR_OFFSET, (uint32_t)ch); } /**************************************************************************** @@ -2800,8 +2800,8 @@ static void stm32l4serial_send(struct uart_dev_s *dev, int ch) static void stm32l4serial_txint(struct uart_dev_s *dev, bool enable) { - struct stm32l4_serial_s *priv = - (struct stm32l4_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; irqstate_t flags; @@ -2836,7 +2836,7 @@ static void stm32l4serial_txint(struct uart_dev_s *dev, bool enable) } # endif -# ifdef CONFIG_STM32L4_SERIALBRK_BSDCOMPAT +# ifdef CONFIG_STM32_SERIALBRK_BSDCOMPAT if (priv->ie & USART_CR1_IE_BREAK_INPROGRESS) { leave_critical_section(flags); @@ -2873,9 +2873,9 @@ static void stm32l4serial_txint(struct uart_dev_s *dev, bool enable) static bool stm32l4serial_txready(struct uart_dev_s *dev) { - struct stm32l4_serial_s *priv = - (struct stm32l4_serial_s *)dev->priv; - return ((stm32l4serial_getreg(priv, STM32L4_USART_ISR_OFFSET) & + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; + return ((stm32l4serial_getreg(priv, STM32_USART_ISR_OFFSET) & USART_ISR_TXE) != 0); } @@ -2892,7 +2892,7 @@ static bool stm32l4serial_txready(struct uart_dev_s *dev) static void stm32l4serial_dmarxcallback(DMA_HANDLE handle, uint8_t status, void *arg) { - struct stm32l4_serial_s *priv = (struct stm32l4_serial_s *)arg; + struct stm32_serial_s *priv = (struct stm32_serial_s *)arg; if (priv->rxenable && stm32l4serial_dmarxavailable(&priv->dev)) { @@ -2918,11 +2918,11 @@ static void stm32l4serial_dmarxcallback(DMA_HANDLE handle, uint8_t status, * will release Rx DMA. */ - priv->sr = stm32l4serial_getreg(priv, STM32L4_USART_ISR_OFFSET); + priv->sr = stm32l4serial_getreg(priv, STM32_USART_ISR_OFFSET); if ((priv->sr & (USART_ISR_ORE | USART_ISR_NF | USART_ISR_FE)) != 0) { - stm32l4serial_putreg(priv, STM32L4_USART_ICR_OFFSET, + stm32l4serial_putreg(priv, STM32_USART_ICR_OFFSET, (USART_ICR_NCF | USART_ICR_ORECF | USART_ICR_FECF)); } @@ -3051,16 +3051,16 @@ static int stm32l4serial_pmprepare(struct pm_callback_s *cb, int domain, * buffers. */ - stm32l4_serial_dma_poll(); + stm32_serial_dma_poll(); #endif /* Check if any of the active ports have data pending on Tx/Rx * buffers. */ - for (n = 0; n < STM32L4_NLPUART + STM32L4_NUSART + STM32L4_NUART; n++) + for (n = 0; n < STM32_NLPUART + STM32_NUSART + STM32_NUART; n++) { - struct stm32l4_serial_s *priv = g_uart_devs[n]; + struct stm32_serial_s *priv = g_uart_devs[n]; if (!priv || !priv->initialized) { @@ -3128,7 +3128,7 @@ void arm_earlyserialinit(void) /* Disable all USART interrupts */ - for (i = 0; i < STM32L4_NLPUART + STM32L4_NUSART + STM32L4_NUART; i++) + for (i = 0; i < STM32_NLPUART + STM32_NUSART + STM32_NUART; i++) { if (g_uart_devs[i]) { @@ -3177,7 +3177,7 @@ void arm_serialinit(void) #if CONSOLE_UART > 0 uart_register("/dev/console", &g_uart_devs[CONSOLE_UART - 1]->dev); -#ifndef CONFIG_STM32L4_SERIAL_DISABLE_REORDERING +#ifndef CONFIG_STM32_SERIAL_DISABLE_REORDERING /* If not disabled, register the console UART to ttyS0 and exclude * it from initializing it further down */ @@ -3197,7 +3197,7 @@ void arm_serialinit(void) strlcpy(devname, "/dev/ttySx", sizeof(devname)); - for (i = 0; i < STM32L4_NLPUART + STM32L4_NUSART + STM32L4_NUART; i++) + for (i = 0; i < STM32_NLPUART + STM32_NUSART + STM32_NUART; i++) { /* Don't create a device for non-configured ports. */ @@ -3206,7 +3206,7 @@ void arm_serialinit(void) continue; } -#ifndef CONFIG_STM32L4_SERIAL_DISABLE_REORDERING +#ifndef CONFIG_STM32_SERIAL_DISABLE_REORDERING /* Don't create a device for the console - we did that above */ if (g_uart_devs[i]->dev.isconsole) @@ -3224,7 +3224,7 @@ void arm_serialinit(void) } /**************************************************************************** - * Name: stm32l4_serial_dma_poll + * Name: stm32_serial_dma_poll * * Description: * Checks receive DMA buffers for received bytes that have not accumulated @@ -3235,7 +3235,7 @@ void arm_serialinit(void) ****************************************************************************/ #ifdef SERIAL_HAVE_RXDMA -void stm32l4_serial_dma_poll(void) +void stm32_serial_dma_poll(void) { irqstate_t flags; @@ -3298,7 +3298,7 @@ void stm32l4_serial_dma_poll(void) void up_putc(int ch) { #if CONSOLE_UART > 0 - struct stm32l4_serial_s *priv = g_uart_devs[CONSOLE_UART - 1]; + struct stm32_serial_s *priv = g_uart_devs[CONSOLE_UART - 1]; uint16_t ie; stm32l4serial_disableusartint(priv, &ie); diff --git a/arch/arm/src/stm32l4/stm32l4_spi.c b/arch/arm/src/stm32l4/stm32l4_spi.c index b53213580ea0b..8eb04f9ef9e30 100644 --- a/arch/arm/src/stm32l4/stm32l4_spi.c +++ b/arch/arm/src/stm32l4/stm32l4_spi.c @@ -21,22 +21,22 @@ ****************************************************************************/ /**************************************************************************** - * The external functions, stm32l4_spi1/2/3select and stm32l4_spi1/2/3status + * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status * must be provided by board-specific logic. They are implementations of the * select and status methods of the SPI interface defined by struct spi_ops_s * (see include/nuttx/spi/spi.h). All other methods (including - * stm32l4_spibus_initialize()) are provided by common STM32 logic. To use + * stm32_spibus_initialize()) are provided by common STM32 logic. To use * this common SPI logic on your board: * - * 1. Provide logic in stm32l4_board_initialize() to configure SPI chip + * 1. Provide logic in stm32_board_initialize() to configure SPI chip * select pins. - * 2. Provide stm32l4_spi1/2/3select() and stm32l4_spi1/2/3status() + * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() * functions in your board-specific logic. These functions will perform * chip selection and status operations using GPIOs in the way your * board is configured. - * 3. Add a calls to stm32l4_spibus_initialize() in your low level + * 3. Add a calls to stm32_spibus_initialize() in your low level * application initialization logic - * 4. The handle returned by stm32l4_spibus_initialize() may then be used + * 4. The handle returned by stm32_spibus_initialize() may then be used * to bind the SPI driver to higher level logic (e.g., calling * mmcsd_spislotinitialize(), for example, will bind the SPI driver to * the SPI MMC/SD driver). @@ -73,15 +73,15 @@ #include "arm_internal.h" #include "chip.h" -#include "stm32l4.h" +#include "stm32.h" #include "stm32l4_gpio.h" #include "stm32l4_dma.h" #include "stm32l4_spi.h" #include -#if defined(CONFIG_STM32L4_SPI1) || defined(CONFIG_STM32L4_SPI2) || \ - defined(CONFIG_STM32L4_SPI3) +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || \ + defined(CONFIG_STM32_SPI3) /**************************************************************************** * Pre-processor Definitions @@ -91,19 +91,19 @@ /* SPI interrupts */ -#ifdef CONFIG_STM32L4_SPI_INTERRUPTS +#ifdef CONFIG_STM32_SPI_INTERRUPTS # error "Interrupt driven SPI not yet supported" #endif /* Can't have both interrupt driven SPI and SPI DMA */ -#if defined(CONFIG_STM32L4_SPI_INTERRUPTS) && defined(CONFIG_STM32L4_SPI_DMA) +#if defined(CONFIG_STM32_SPI_INTERRUPTS) && defined(CONFIG_STM32_SPI_DMA) # error "Cannot enable both interrupt mode and DMA mode for SPI" #endif /* SPI DMA priority */ -#ifdef CONFIG_STM32L4_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA # if defined(CONFIG_SPI_DMAPRIO) # define SPI_DMA_PRIO CONFIG_SPI_DMAPRIO @@ -132,15 +132,15 @@ * Private Types ****************************************************************************/ -struct stm32l4_spidev_s +struct stm32_spidev_s { struct spi_dev_s spidev; /* Externally visible part of the SPI interface */ uint32_t spibase; /* SPIn base address */ uint32_t spiclock; /* Clocking for the SPI module */ -#ifdef CONFIG_STM32L4_SPI_INTERRUPTS +#ifdef CONFIG_STM32_SPI_INTERRUPTS uint8_t spiirq; /* SPI IRQ number */ #endif -#ifdef CONFIG_STM32L4_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA volatile uint8_t rxresult; /* Result of the RX DMA */ volatile uint8_t txresult; /* Result of the RX DMA */ #ifdef CONFIG_SPI_TRIGGER @@ -173,37 +173,37 @@ struct stm32l4_spidev_s /* Helpers */ -static inline uint16_t spi_getreg(struct stm32l4_spidev_s *priv, +static inline uint16_t spi_getreg(struct stm32_spidev_s *priv, uint8_t offset); -static inline void spi_putreg(struct stm32l4_spidev_s *priv, +static inline void spi_putreg(struct stm32_spidev_s *priv, uint8_t offset, uint16_t value); -static inline uint16_t spi_readword(struct stm32l4_spidev_s *priv); -static inline void spi_writeword(struct stm32l4_spidev_s *priv, +static inline uint16_t spi_readword(struct stm32_spidev_s *priv); +static inline void spi_writeword(struct stm32_spidev_s *priv, uint16_t byte); -static inline bool spi_16bitmode(struct stm32l4_spidev_s *priv); +static inline bool spi_16bitmode(struct stm32_spidev_s *priv); /* DMA support */ -#ifdef CONFIG_STM32L4_SPI_DMA -static int spi_dmarxwait(struct stm32l4_spidev_s *priv); -static int spi_dmatxwait(struct stm32l4_spidev_s *priv); -static inline void spi_dmarxwakeup(struct stm32l4_spidev_s *priv); -static inline void spi_dmatxwakeup(struct stm32l4_spidev_s *priv); +#ifdef CONFIG_STM32_SPI_DMA +static int spi_dmarxwait(struct stm32_spidev_s *priv); +static int spi_dmatxwait(struct stm32_spidev_s *priv); +static inline void spi_dmarxwakeup(struct stm32_spidev_s *priv); +static inline void spi_dmatxwakeup(struct stm32_spidev_s *priv); static void spi_dmarxcallback(DMA_HANDLE handle, uint8_t isr, void *arg); static void spi_dmatxcallback(DMA_HANDLE handle, uint8_t isr, void *arg); -static void spi_dmarxsetup(struct stm32l4_spidev_s *priv, +static void spi_dmarxsetup(struct stm32_spidev_s *priv, void *rxbuffer, void *rxdummy, size_t nwords); -static void spi_dmatxsetup(struct stm32l4_spidev_s *priv, +static void spi_dmatxsetup(struct stm32_spidev_s *priv, const void *txbuffer, const void *txdummy, size_t nwords); -static inline void spi_dmarxstart(struct stm32l4_spidev_s *priv); -static inline void spi_dmatxstart(struct stm32l4_spidev_s *priv); +static inline void spi_dmarxstart(struct stm32_spidev_s *priv); +static inline void spi_dmatxstart(struct stm32_spidev_s *priv); #endif /* SPI methods */ @@ -234,7 +234,7 @@ static void spi_recvblock(struct spi_dev_s *dev, /* Initialization */ -static void spi_bus_initialize(struct stm32l4_spidev_s *priv); +static void spi_bus_initialize(struct stm32_spidev_s *priv); /* PM interface */ @@ -247,20 +247,20 @@ static int spi_pm_prepare(struct pm_callback_s *cb, int domain, * Private Data ****************************************************************************/ -#ifdef CONFIG_STM32L4_SPI1 +#ifdef CONFIG_STM32_SPI1 static const struct spi_ops_s g_spi1ops = { .lock = spi_lock, - .select = stm32l4_spi1select, + .select = stm32_spi1select, .setfrequency = spi_setfrequency, .setmode = spi_setmode, .setbits = spi_setbits, #ifdef CONFIG_SPI_HWFEATURES .hwfeatures = spi_hwfeatures, #endif - .status = stm32l4_spi1status, + .status = stm32_spi1status, #ifdef CONFIG_SPI_CMDDATA - .cmddata = stm32l4_spi1cmddata, + .cmddata = stm32_spi1cmddata, #endif .send = spi_send, #ifdef CONFIG_SPI_EXCHANGE @@ -273,24 +273,24 @@ static const struct spi_ops_s g_spi1ops = .trigger = spi_trigger, #endif #ifdef CONFIG_SPI_CALLBACK - .registercallback = stm32l4_spi1register, /* Provided externally */ + .registercallback = stm32_spi1register, /* Provided externally */ #else .registercallback = 0, /* Not implemented */ #endif }; -static struct stm32l4_spidev_s g_spi1dev = +static struct stm32_spidev_s g_spi1dev = { .spidev = { .ops = &g_spi1ops, }, - .spibase = STM32L4_SPI1_BASE, - .spiclock = STM32L4_PCLK2_FREQUENCY, -#ifdef CONFIG_STM32L4_SPI_INTERRUPTS - .spiirq = STM32L4_IRQ_SPI1, + .spibase = STM32_SPI1_BASE, + .spiclock = STM32_PCLK2_FREQUENCY, +#ifdef CONFIG_STM32_SPI_INTERRUPTS + .spiirq = STM32_IRQ_SPI1, #endif -#ifdef CONFIG_STM32L4_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA /* lines must be configured in board.h */ .rxch = DMACHAN_SPI1_RX, @@ -305,20 +305,20 @@ static struct stm32l4_spidev_s g_spi1dev = }; #endif -#ifdef CONFIG_STM32L4_SPI2 +#ifdef CONFIG_STM32_SPI2 static const struct spi_ops_s g_spi2ops = { .lock = spi_lock, - .select = stm32l4_spi2select, + .select = stm32_spi2select, .setfrequency = spi_setfrequency, .setmode = spi_setmode, .setbits = spi_setbits, #ifdef CONFIG_SPI_HWFEATURES .hwfeatures = spi_hwfeatures, #endif - .status = stm32l4_spi2status, + .status = stm32_spi2status, #ifdef CONFIG_SPI_CMDDATA - .cmddata = stm32l4_spi2cmddata, + .cmddata = stm32_spi2cmddata, #endif .send = spi_send, #ifdef CONFIG_SPI_EXCHANGE @@ -331,24 +331,24 @@ static const struct spi_ops_s g_spi2ops = .trigger = spi_trigger, #endif #ifdef CONFIG_SPI_CALLBACK - .registercallback = stm32l4_spi2register, /* provided externally */ + .registercallback = stm32_spi2register, /* provided externally */ #else .registercallback = 0, /* not implemented */ #endif }; -static struct stm32l4_spidev_s g_spi2dev = +static struct stm32_spidev_s g_spi2dev = { .spidev = { .ops = &g_spi2ops, }, - .spibase = STM32L4_SPI2_BASE, - .spiclock = STM32L4_PCLK1_FREQUENCY, -#ifdef CONFIG_STM32L4_SPI_INTERRUPTS - .spiirq = STM32L4_IRQ_SPI2, + .spibase = STM32_SPI2_BASE, + .spiclock = STM32_PCLK1_FREQUENCY, +#ifdef CONFIG_STM32_SPI_INTERRUPTS + .spiirq = STM32_IRQ_SPI2, #endif -#ifdef CONFIG_STM32L4_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA .rxch = DMACHAN_SPI2_RX, .txch = DMACHAN_SPI2_TX, .rxsem = SEM_INITIALIZER(0), @@ -361,20 +361,20 @@ static struct stm32l4_spidev_s g_spi2dev = }; #endif -#ifdef CONFIG_STM32L4_SPI3 +#ifdef CONFIG_STM32_SPI3 static const struct spi_ops_s g_spi3ops = { .lock = spi_lock, - .select = stm32l4_spi3select, + .select = stm32_spi3select, .setfrequency = spi_setfrequency, .setmode = spi_setmode, .setbits = spi_setbits, #ifdef CONFIG_SPI_HWFEATURES .hwfeatures = spi_hwfeatures, #endif - .status = stm32l4_spi3status, + .status = stm32_spi3status, #ifdef CONFIG_SPI_CMDDATA - .cmddata = stm32l4_spi3cmddata, + .cmddata = stm32_spi3cmddata, #endif .send = spi_send, #ifdef CONFIG_SPI_EXCHANGE @@ -387,24 +387,24 @@ static const struct spi_ops_s g_spi3ops = .trigger = spi_trigger, #endif #ifdef CONFIG_SPI_CALLBACK - .registercallback = stm32l4_spi3register, /* provided externally */ + .registercallback = stm32_spi3register, /* provided externally */ #else .registercallback = 0, /* not implemented */ #endif }; -static struct stm32l4_spidev_s g_spi3dev = +static struct stm32_spidev_s g_spi3dev = { .spidev = { .ops = &g_spi3ops, }, - .spibase = STM32L4_SPI3_BASE, - .spiclock = STM32L4_PCLK1_FREQUENCY, -#ifdef CONFIG_STM32L4_SPI_INTERRUPTS - .spiirq = STM32L4_IRQ_SPI3, + .spibase = STM32_SPI3_BASE, + .spiclock = STM32_PCLK1_FREQUENCY, +#ifdef CONFIG_STM32_SPI_INTERRUPTS + .spiirq = STM32_IRQ_SPI3, #endif -#ifdef CONFIG_STM32L4_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA .rxch = DMACHAN_SPI3_RX, .txch = DMACHAN_SPI3_TX, .rxsem = SEM_INITIALIZER(0), @@ -436,7 +436,7 @@ static struct stm32l4_spidev_s g_spi3dev = * ****************************************************************************/ -static inline uint16_t spi_getreg(struct stm32l4_spidev_s *priv, +static inline uint16_t spi_getreg(struct stm32_spidev_s *priv, uint8_t offset) { return getreg16(priv->spibase + offset); @@ -458,7 +458,7 @@ static inline uint16_t spi_getreg(struct stm32l4_spidev_s *priv, * ****************************************************************************/ -static inline void spi_putreg(struct stm32l4_spidev_s *priv, +static inline void spi_putreg(struct stm32_spidev_s *priv, uint8_t offset, uint16_t value) { putreg16(value, priv->spibase + offset); @@ -479,7 +479,7 @@ static inline void spi_putreg(struct stm32l4_spidev_s *priv, * ****************************************************************************/ -static inline uint8_t spi_getreg8(struct stm32l4_spidev_s *priv, +static inline uint8_t spi_getreg8(struct stm32_spidev_s *priv, uint8_t offset) { return getreg8(priv->spibase + offset); @@ -498,7 +498,7 @@ static inline uint8_t spi_getreg8(struct stm32l4_spidev_s *priv, * ****************************************************************************/ -static inline void spi_putreg8(struct stm32l4_spidev_s *priv, +static inline void spi_putreg8(struct stm32_spidev_s *priv, uint8_t offset, uint8_t value) { putreg8(value, priv->spibase + offset); @@ -518,15 +518,15 @@ static inline void spi_putreg8(struct stm32l4_spidev_s *priv, * ****************************************************************************/ -static inline uint16_t spi_readword(struct stm32l4_spidev_s *priv) +static inline uint16_t spi_readword(struct stm32_spidev_s *priv) { /* Wait until the receive buffer is not empty */ - while ((spi_getreg(priv, STM32L4_SPI_SR_OFFSET) & SPI_SR_RXNE) == 0); + while ((spi_getreg(priv, STM32_SPI_SR_OFFSET) & SPI_SR_RXNE) == 0); /* Then return the received byte */ - return spi_getreg(priv, STM32L4_SPI_DR_OFFSET); + return spi_getreg(priv, STM32_SPI_DR_OFFSET); } /**************************************************************************** @@ -543,15 +543,15 @@ static inline uint16_t spi_readword(struct stm32l4_spidev_s *priv) * ****************************************************************************/ -static inline uint8_t spi_readbyte(struct stm32l4_spidev_s *priv) +static inline uint8_t spi_readbyte(struct stm32_spidev_s *priv) { /* Wait until the receive buffer is not empty */ - while ((spi_getreg(priv, STM32L4_SPI_SR_OFFSET) & SPI_SR_RXNE) == 0); + while ((spi_getreg(priv, STM32_SPI_SR_OFFSET) & SPI_SR_RXNE) == 0); /* Then return the received byte */ - return spi_getreg8(priv, STM32L4_SPI_DR_OFFSET); + return spi_getreg8(priv, STM32_SPI_DR_OFFSET); } /**************************************************************************** @@ -569,16 +569,16 @@ static inline uint8_t spi_readbyte(struct stm32l4_spidev_s *priv) * ****************************************************************************/ -static inline void spi_writeword(struct stm32l4_spidev_s *priv, +static inline void spi_writeword(struct stm32_spidev_s *priv, uint16_t word) { /* Wait until the transmit buffer is empty */ - while ((spi_getreg(priv, STM32L4_SPI_SR_OFFSET) & SPI_SR_TXE) == 0); + while ((spi_getreg(priv, STM32_SPI_SR_OFFSET) & SPI_SR_TXE) == 0); /* Then send the byte */ - spi_putreg(priv, STM32L4_SPI_DR_OFFSET, word); + spi_putreg(priv, STM32_SPI_DR_OFFSET, word); } /**************************************************************************** @@ -596,16 +596,16 @@ static inline void spi_writeword(struct stm32l4_spidev_s *priv, * ****************************************************************************/ -static inline void spi_writebyte(struct stm32l4_spidev_s *priv, +static inline void spi_writebyte(struct stm32_spidev_s *priv, uint8_t byte) { /* Wait until the transmit buffer is empty */ - while ((spi_getreg(priv, STM32L4_SPI_SR_OFFSET) & SPI_SR_TXE) == 0); + while ((spi_getreg(priv, STM32_SPI_SR_OFFSET) & SPI_SR_TXE) == 0); /* Then send the byte */ - spi_putreg8(priv, STM32L4_SPI_DR_OFFSET, byte); + spi_putreg8(priv, STM32_SPI_DR_OFFSET, byte); } /**************************************************************************** @@ -622,7 +622,7 @@ static inline void spi_writebyte(struct stm32l4_spidev_s *priv, * ****************************************************************************/ -static inline bool spi_16bitmode(struct stm32l4_spidev_s *priv) +static inline bool spi_16bitmode(struct stm32_spidev_s *priv) { return (priv->nbits > 8); } @@ -635,8 +635,8 @@ static inline bool spi_16bitmode(struct stm32l4_spidev_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32L4_SPI_DMA -static int spi_dmarxwait(struct stm32l4_spidev_s *priv) +#ifdef CONFIG_STM32_SPI_DMA +static int spi_dmarxwait(struct stm32_spidev_s *priv) { int ret; @@ -668,8 +668,8 @@ static int spi_dmarxwait(struct stm32l4_spidev_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32L4_SPI_DMA -static int spi_dmatxwait(struct stm32l4_spidev_s *priv) +#ifdef CONFIG_STM32_SPI_DMA +static int spi_dmatxwait(struct stm32_spidev_s *priv) { int ret; @@ -701,8 +701,8 @@ static int spi_dmatxwait(struct stm32l4_spidev_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32L4_SPI_DMA -static inline void spi_dmarxwakeup(struct stm32l4_spidev_s *priv) +#ifdef CONFIG_STM32_SPI_DMA +static inline void spi_dmarxwakeup(struct stm32_spidev_s *priv) { nxsem_post(&priv->rxsem); } @@ -716,8 +716,8 @@ static inline void spi_dmarxwakeup(struct stm32l4_spidev_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32L4_SPI_DMA -static inline void spi_dmatxwakeup(struct stm32l4_spidev_s *priv) +#ifdef CONFIG_STM32_SPI_DMA +static inline void spi_dmatxwakeup(struct stm32_spidev_s *priv) { nxsem_post(&priv->txsem); } @@ -731,10 +731,10 @@ static inline void spi_dmatxwakeup(struct stm32l4_spidev_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32L4_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_dmarxcallback(DMA_HANDLE handle, uint8_t isr, void *arg) { - struct stm32l4_spidev_s *priv = (struct stm32l4_spidev_s *)arg; + struct stm32_spidev_s *priv = (struct stm32_spidev_s *)arg; /* Wake-up the SPI driver */ @@ -751,10 +751,10 @@ static void spi_dmarxcallback(DMA_HANDLE handle, uint8_t isr, void *arg) * ****************************************************************************/ -#ifdef CONFIG_STM32L4_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_dmatxcallback(DMA_HANDLE handle, uint8_t isr, void *arg) { - struct stm32l4_spidev_s *priv = (struct stm32l4_spidev_s *)arg; + struct stm32_spidev_s *priv = (struct stm32_spidev_s *)arg; /* Wake-up the SPI driver */ @@ -771,8 +771,8 @@ static void spi_dmatxcallback(DMA_HANDLE handle, uint8_t isr, void *arg) * ****************************************************************************/ -#ifdef CONFIG_STM32L4_SPI_DMA -static void spi_dmarxsetup(struct stm32l4_spidev_s *priv, +#ifdef CONFIG_STM32_SPI_DMA +static void spi_dmarxsetup(struct stm32_spidev_s *priv, void *rxbuffer, void *rxdummy, size_t nwords) { @@ -809,7 +809,7 @@ static void spi_dmarxsetup(struct stm32l4_spidev_s *priv, /* Configure the RX DMA */ - stm32l4_dmasetup(priv->rxdma, priv->spibase + STM32L4_SPI_DR_OFFSET, + stm32_dmasetup(priv->rxdma, priv->spibase + STM32_SPI_DR_OFFSET, (uint32_t)rxbuffer, nwords, priv->rxccr); } #endif @@ -822,8 +822,8 @@ static void spi_dmarxsetup(struct stm32l4_spidev_s *priv, * ****************************************************************************/ -#ifdef CONFIG_STM32L4_SPI_DMA -static void spi_dmatxsetup(struct stm32l4_spidev_s *priv, +#ifdef CONFIG_STM32_SPI_DMA +static void spi_dmatxsetup(struct stm32_spidev_s *priv, const void *txbuffer, const void *txdummy, size_t nwords) @@ -861,7 +861,7 @@ static void spi_dmatxsetup(struct stm32l4_spidev_s *priv, /* Setup the TX DMA */ - stm32l4_dmasetup(priv->txdma, priv->spibase + STM32L4_SPI_DR_OFFSET, + stm32_dmasetup(priv->txdma, priv->spibase + STM32_SPI_DR_OFFSET, (uint32_t)txbuffer, nwords, priv->txccr); } #endif @@ -874,11 +874,11 @@ static void spi_dmatxsetup(struct stm32l4_spidev_s *priv, * ****************************************************************************/ -#ifdef CONFIG_STM32L4_SPI_DMA -static inline void spi_dmarxstart(struct stm32l4_spidev_s *priv) +#ifdef CONFIG_STM32_SPI_DMA +static inline void spi_dmarxstart(struct stm32_spidev_s *priv) { priv->rxresult = 0; - stm32l4_dmastart(priv->rxdma, spi_dmarxcallback, priv, false); + stm32_dmastart(priv->rxdma, spi_dmarxcallback, priv, false); } #endif @@ -890,11 +890,11 @@ static inline void spi_dmarxstart(struct stm32l4_spidev_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32L4_SPI_DMA -static inline void spi_dmatxstart(struct stm32l4_spidev_s *priv) +#ifdef CONFIG_STM32_SPI_DMA +static inline void spi_dmatxstart(struct stm32_spidev_s *priv) { priv->txresult = 0; - stm32l4_dmastart(priv->txdma, spi_dmatxcallback, priv, false); + stm32_dmastart(priv->txdma, spi_dmatxcallback, priv, false); } #endif @@ -914,7 +914,7 @@ static inline void spi_dmatxstart(struct stm32l4_spidev_s *priv) * ****************************************************************************/ -static void spi_modifycr(uint32_t addr, struct stm32l4_spidev_s *priv, +static void spi_modifycr(uint32_t addr, struct stm32_spidev_s *priv, uint16_t setbits, uint16_t clrbits) { uint16_t cr; @@ -948,7 +948,7 @@ static void spi_modifycr(uint32_t addr, struct stm32l4_spidev_s *priv, static int spi_lock(struct spi_dev_s *dev, bool lock) { - struct stm32l4_spidev_s *priv = (struct stm32l4_spidev_s *)dev; + struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev; int ret; if (lock) @@ -981,15 +981,15 @@ static int spi_lock(struct spi_dev_s *dev, bool lock) static uint32_t spi_setfrequency(struct spi_dev_s *dev, uint32_t frequency) { - struct stm32l4_spidev_s *priv = (struct stm32l4_spidev_s *)dev; + struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev; uint16_t setbits; uint32_t actual; - /* Limit to max possible (if STM32L4_SPI_CLK_MAX is defined in board.h) */ + /* Limit to max possible (if STM32_SPI_CLK_MAX is defined in board.h) */ - if (frequency > STM32L4_SPI_CLK_MAX) + if (frequency > STM32_SPI_CLK_MAX) { - frequency = STM32L4_SPI_CLK_MAX; + frequency = STM32_SPI_CLK_MAX; } /* Has the frequency changed? */ @@ -1055,9 +1055,9 @@ static uint32_t spi_setfrequency(struct spi_dev_s *dev, actual = priv->spiclock >> 8; } - spi_modifycr(STM32L4_SPI_CR1_OFFSET, priv, 0, SPI_CR1_SPE); - spi_modifycr(STM32L4_SPI_CR1_OFFSET, priv, setbits, SPI_CR1_BR_MASK); - spi_modifycr(STM32L4_SPI_CR1_OFFSET, priv, SPI_CR1_SPE, 0); + spi_modifycr(STM32_SPI_CR1_OFFSET, priv, 0, SPI_CR1_SPE); + spi_modifycr(STM32_SPI_CR1_OFFSET, priv, setbits, SPI_CR1_BR_MASK); + spi_modifycr(STM32_SPI_CR1_OFFSET, priv, SPI_CR1_SPE, 0); /* Save the frequency selection so that subsequent reconfigurations * will be faster. @@ -1089,7 +1089,7 @@ static uint32_t spi_setfrequency(struct spi_dev_s *dev, static void spi_setmode(struct spi_dev_s *dev, enum spi_mode_e mode) { - struct stm32l4_spidev_s *priv = (struct stm32l4_spidev_s *)dev; + struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev; uint16_t setbits; uint16_t clrbits; @@ -1127,9 +1127,9 @@ static void spi_setmode(struct spi_dev_s *dev, enum spi_mode_e mode) return; } - spi_modifycr(STM32L4_SPI_CR1_OFFSET, priv, 0, SPI_CR1_SPE); - spi_modifycr(STM32L4_SPI_CR1_OFFSET, priv, setbits, clrbits); - spi_modifycr(STM32L4_SPI_CR1_OFFSET, priv, SPI_CR1_SPE, 0); + spi_modifycr(STM32_SPI_CR1_OFFSET, priv, 0, SPI_CR1_SPE); + spi_modifycr(STM32_SPI_CR1_OFFSET, priv, setbits, clrbits); + spi_modifycr(STM32_SPI_CR1_OFFSET, priv, SPI_CR1_SPE, 0); /* Save the mode so that subsequent re-configurations will be * faster. @@ -1157,7 +1157,7 @@ static void spi_setmode(struct spi_dev_s *dev, enum spi_mode_e mode) static void spi_setbits(struct spi_dev_s *dev, int nbits) { - struct stm32l4_spidev_s *priv = (struct stm32l4_spidev_s *)dev; + struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev; uint16_t setbits; uint16_t clrbits; @@ -1193,9 +1193,9 @@ static void spi_setbits(struct spi_dev_s *dev, int nbits) clrbits |= SPI_CR2_FRXTH; /* RX FIFO Threshold = 2 bytes */ } - spi_modifycr(STM32L4_SPI_CR1_OFFSET, priv, 0, SPI_CR1_SPE); - spi_modifycr(STM32L4_SPI_CR2_OFFSET, priv, setbits, clrbits); - spi_modifycr(STM32L4_SPI_CR1_OFFSET, priv, SPI_CR1_SPE, 0); + spi_modifycr(STM32_SPI_CR1_OFFSET, priv, 0, SPI_CR1_SPE); + spi_modifycr(STM32_SPI_CR2_OFFSET, priv, setbits, clrbits); + spi_modifycr(STM32_SPI_CR1_OFFSET, priv, SPI_CR1_SPE, 0); /* Save the selection so that subsequent re-configurations will be * faster. @@ -1226,7 +1226,7 @@ static int spi_hwfeatures(struct spi_dev_s *dev, spi_hwfeatures_t features) { #if defined(CONFIG_SPI_BITORDER) || defined(CONFIG_SPI_TRIGGER) - struct stm32l4_spidev_s *priv = (struct stm32l4_spidev_s *)dev; + struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev; #endif #ifdef CONFIG_SPI_BITORDER @@ -1248,9 +1248,9 @@ static int spi_hwfeatures(struct spi_dev_s *dev, clrbits = SPI_CR1_LSBFIRST; } - spi_modifycr(STM32L4_SPI_CR1_OFFSET, priv, 0, SPI_CR1_SPE); - spi_modifycr(STM32L4_SPI_CR1_OFFSET, priv, setbits, clrbits); - spi_modifycr(STM32L4_SPI_CR1_OFFSET, priv, SPI_CR1_SPE, 0); + spi_modifycr(STM32_SPI_CR1_OFFSET, priv, 0, SPI_CR1_SPE); + spi_modifycr(STM32_SPI_CR1_OFFSET, priv, setbits, clrbits); + spi_modifycr(STM32_SPI_CR1_OFFSET, priv, SPI_CR1_SPE, 0); features &= ~HWFEAT_LSBFIRST; #endif @@ -1290,7 +1290,7 @@ static int spi_hwfeatures(struct spi_dev_s *dev, static uint32_t spi_send(struct spi_dev_s *dev, uint32_t wd) { - struct stm32l4_spidev_s *priv = (struct stm32l4_spidev_s *)dev; + struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev; uint32_t regval; uint32_t ret; @@ -1316,7 +1316,7 @@ static uint32_t spi_send(struct spi_dev_s *dev, uint32_t wd) * flags). */ - regval = spi_getreg(priv, STM32L4_SPI_SR_OFFSET); + regval = spi_getreg(priv, STM32_SPI_SR_OFFSET); if (spi_16bitmode(priv)) { @@ -1354,8 +1354,8 @@ static uint32_t spi_send(struct spi_dev_s *dev, uint32_t wd) * ****************************************************************************/ -#if !defined(CONFIG_STM32L4_SPI_DMA) || defined(CONFIG_STM32L4_DMACAPABLE) -#if !defined(CONFIG_STM32L4_SPI_DMA) +#if !defined(CONFIG_STM32_SPI_DMA) || defined(CONFIG_STM32_DMACAPABLE) +#if !defined(CONFIG_STM32_SPI_DMA) static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, void *rxbuffer, size_t nwords) #else @@ -1364,7 +1364,7 @@ static void spi_exchange_nodma(struct spi_dev_s *dev, size_t nwords) #endif { - struct stm32l4_spidev_s *priv = (struct stm32l4_spidev_s *)dev; + struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev; DEBUGASSERT(priv && priv->spibase); spiinfo("txbuffer=%p rxbuffer=%p nwords=%d\n", txbuffer, rxbuffer, nwords); @@ -1438,7 +1438,7 @@ static void spi_exchange_nodma(struct spi_dev_s *dev, } } } -#endif /* !CONFIG_STM32L4_SPI_DMA || CONFIG_STM32L4_DMACAPABLE */ +#endif /* !CONFIG_STM32_SPI_DMA || CONFIG_STM32_DMACAPABLE */ /**************************************************************************** * Name: spi_exchange (with DMA capability) @@ -1461,18 +1461,18 @@ static void spi_exchange_nodma(struct spi_dev_s *dev, * ****************************************************************************/ -#ifdef CONFIG_STM32L4_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, void *rxbuffer, size_t nwords) { - struct stm32l4_spidev_s *priv = (struct stm32l4_spidev_s *)dev; + struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev; int ret; -#ifdef CONFIG_STM32L4_DMACAPABLE +#ifdef CONFIG_STM32_DMACAPABLE if ((txbuffer && - !stm32l4_dmacapable((uint32_t)txbuffer, nwords, priv->txccr)) || + !stm32_dmacapable((uint32_t)txbuffer, nwords, priv->txccr)) || (rxbuffer && - !stm32l4_dmacapable((uint32_t)rxbuffer, nwords, priv->rxccr))) + !stm32_dmacapable((uint32_t)rxbuffer, nwords, priv->rxccr))) { /* Unsupported memory region, fall back to non-DMA method. */ @@ -1530,7 +1530,7 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, #endif } } -#endif /* CONFIG_STM32L4_SPI_DMA */ +#endif /* CONFIG_STM32_SPI_DMA */ /**************************************************************************** * Name: spi_trigger @@ -1551,7 +1551,7 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, #ifdef CONFIG_SPI_TRIGGER static int spi_trigger(struct spi_dev_s *dev) { -#ifdef CONFIG_STM32L4_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev; if (!priv->trigarmed) @@ -1662,8 +1662,8 @@ static void spi_recvblock(struct spi_dev_s *dev, static int spi_pm_prepare(struct pm_callback_s *cb, int domain, enum pm_state_e pmstate) { - struct stm32l4_spidev_s *priv = (struct stm32l4_spidev_s *)((char *)cb - - offsetof(struct stm32l4_spidev_s, pm_cb)); + struct stm32_spidev_s *priv = (struct stm32_spidev_s *)((char *)cb - + offsetof(struct stm32_spidev_s, pm_cb)); /* Logic to prepare for a reduced power state goes here. */ @@ -1715,7 +1715,7 @@ static int spi_pm_prepare(struct pm_callback_s *cb, int domain, * ****************************************************************************/ -static void spi_bus_initialize(struct stm32l4_spidev_s *priv) +static void spi_bus_initialize(struct stm32_spidev_s *priv) { uint16_t setbits; uint16_t clrbits; @@ -1738,11 +1738,11 @@ static void spi_bus_initialize(struct stm32l4_spidev_s *priv) SPI_CR1_LSBFIRST | SPI_CR1_RXONLY | SPI_CR1_BIDIOE | SPI_CR1_BIDIMODE; setbits = SPI_CR1_MSTR | SPI_CR1_SSI | SPI_CR1_SSM; - spi_modifycr(STM32L4_SPI_CR1_OFFSET, priv, setbits, clrbits); + spi_modifycr(STM32_SPI_CR1_OFFSET, priv, setbits, clrbits); clrbits = SPI_CR2_DS_MASK; setbits = SPI_CR2_DS_8BIT | SPI_CR2_FRXTH; /* FRXTH must be high in 8-bit mode */ - spi_modifycr(STM32L4_SPI_CR2_OFFSET, priv, setbits, clrbits); + spi_modifycr(STM32_SPI_CR2_OFFSET, priv, setbits, clrbits); priv->frequency = 0; priv->nbits = 8; @@ -1754,28 +1754,28 @@ static void spi_bus_initialize(struct stm32l4_spidev_s *priv) /* CRCPOLY configuration */ - spi_putreg(priv, STM32L4_SPI_CRCPR_OFFSET, 7); + spi_putreg(priv, STM32_SPI_CRCPR_OFFSET, 7); -#ifdef CONFIG_STM32L4_SPI_DMA - /* Get DMA channels. NOTE: stm32l4_dmachannel() will always assign the DMA - * channel. If the channel is not available, then stm32l4_dmachannel() +#ifdef CONFIG_STM32_SPI_DMA + /* Get DMA channels. NOTE: stm32_dmachannel() will always assign the DMA + * channel. If the channel is not available, then stm32_dmachannel() * will block and wait until the channel becomes available. WARNING: If * you have another device sharing a DMA channel with SPI and the code - * never releases that channel, then the call to stm32l4_dmachannel() will + * never releases that channel, then the call to stm32_dmachannel() will * hang forever in this function! Don't let your design do that! */ - priv->rxdma = stm32l4_dmachannel(priv->rxch); - priv->txdma = stm32l4_dmachannel(priv->txch); + priv->rxdma = stm32_dmachannel(priv->rxch); + priv->txdma = stm32_dmachannel(priv->txch); DEBUGASSERT(priv->rxdma && priv->txdma); - spi_modifycr(STM32L4_SPI_CR2_OFFSET, priv, + spi_modifycr(STM32_SPI_CR2_OFFSET, priv, SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN, 0); #endif /* Enable spi */ - spi_modifycr(STM32L4_SPI_CR1_OFFSET, priv, SPI_CR1_SPE, 0); + spi_modifycr(STM32_SPI_CR1_OFFSET, priv, SPI_CR1_SPE, 0); #ifdef CONFIG_PM /* Register to receive power management callbacks */ @@ -1791,7 +1791,7 @@ static void spi_bus_initialize(struct stm32l4_spidev_s *priv) ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_spibus_initialize + * Name: stm32_spibus_initialize * * Description: * Initialize the selected SPI bus @@ -1804,13 +1804,13 @@ static void spi_bus_initialize(struct stm32l4_spidev_s *priv) * ****************************************************************************/ -struct spi_dev_s *stm32l4_spibus_initialize(int bus) +struct spi_dev_s *stm32_spibus_initialize(int bus) { - struct stm32l4_spidev_s *priv = NULL; + struct stm32_spidev_s *priv = NULL; irqstate_t flags = enter_critical_section(); -#ifdef CONFIG_STM32L4_SPI1 +#ifdef CONFIG_STM32_SPI1 if (bus == 1) { /* Select SPI1 */ @@ -1823,9 +1823,9 @@ struct spi_dev_s *stm32l4_spibus_initialize(int bus) { /* Configure SPI1 pins: SCK, MISO, and MOSI */ - stm32l4_configgpio(GPIO_SPI1_SCK); - stm32l4_configgpio(GPIO_SPI1_MISO); - stm32l4_configgpio(GPIO_SPI1_MOSI); + stm32_configgpio(GPIO_SPI1_SCK); + stm32_configgpio(GPIO_SPI1_MISO); + stm32_configgpio(GPIO_SPI1_MOSI); /* Set up default configuration: Master, 8-bit, etc. */ @@ -1835,7 +1835,7 @@ struct spi_dev_s *stm32l4_spibus_initialize(int bus) } else #endif -#ifdef CONFIG_STM32L4_SPI2 +#ifdef CONFIG_STM32_SPI2 if (bus == 2) { /* Select SPI2 */ @@ -1848,9 +1848,9 @@ struct spi_dev_s *stm32l4_spibus_initialize(int bus) { /* Configure SPI2 pins: SCK, MISO, and MOSI */ - stm32l4_configgpio(GPIO_SPI2_SCK); - stm32l4_configgpio(GPIO_SPI2_MISO); - stm32l4_configgpio(GPIO_SPI2_MOSI); + stm32_configgpio(GPIO_SPI2_SCK); + stm32_configgpio(GPIO_SPI2_MISO); + stm32_configgpio(GPIO_SPI2_MOSI); /* Set up default configuration: Master, 8-bit, etc. */ @@ -1860,7 +1860,7 @@ struct spi_dev_s *stm32l4_spibus_initialize(int bus) } else #endif -#ifdef CONFIG_STM32L4_SPI3 +#ifdef CONFIG_STM32_SPI3 if (bus == 3) { /* Select SPI3 */ @@ -1873,9 +1873,9 @@ struct spi_dev_s *stm32l4_spibus_initialize(int bus) { /* Configure SPI3 pins: SCK, MISO, and MOSI */ - stm32l4_configgpio(GPIO_SPI3_SCK); - stm32l4_configgpio(GPIO_SPI3_MISO); - stm32l4_configgpio(GPIO_SPI3_MOSI); + stm32_configgpio(GPIO_SPI3_SCK); + stm32_configgpio(GPIO_SPI3_MISO); + stm32_configgpio(GPIO_SPI3_MOSI); /* Set up default configuration: Master, 8-bit, etc. */ @@ -1893,4 +1893,4 @@ struct spi_dev_s *stm32l4_spibus_initialize(int bus) return (struct spi_dev_s *)priv; } -#endif /* CONFIG_STM32L4_SPI1 || CONFIG_STM32L4_SPI2 || CONFIG_STM32L4_SPI3 */ +#endif /* CONFIG_STM32_SPI1 || CONFIG_STM32_SPI2 || CONFIG_STM32_SPI3 */ diff --git a/arch/arm/src/stm32l4/stm32l4_spi.h b/arch/arm/src/stm32l4/stm32l4_spi.h index b946487353f4e..a86dbf23c5711 100644 --- a/arch/arm/src/stm32l4/stm32l4_spi.h +++ b/arch/arm/src/stm32l4/stm32l4_spi.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32L4_STM32L4_SPI_H -#define __ARCH_ARM_SRC_STM32L4_STM32L4_SPI_H +#ifndef __ARCH_ARM_SRC_STM32L4_STM32_SPI_H +#define __ARCH_ARM_SRC_STM32L4_STM32_SPI_H /**************************************************************************** * Included Files @@ -58,7 +58,7 @@ struct spi_dev_s; ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_spibus_initialize + * Name: stm32_spibus_initialize * * Description: * Initialize the selected SPI bus @@ -71,62 +71,62 @@ struct spi_dev_s; * ****************************************************************************/ -struct spi_dev_s *stm32l4_spibus_initialize(int bus); +struct spi_dev_s *stm32_spibus_initialize(int bus); /**************************************************************************** - * Name: stm32l4_spi1/2/...select and stm32l4_spi1/2/...status + * Name: stm32_spi1/2/...select and stm32_spi1/2/...status * * Description: - * The external functions, stm32l4_spi1/2/...select, - * stm32l4_spi1/2/...status, and stm32l4_spi1/2/...cmddata must be + * The external functions, stm32_spi1/2/...select, + * stm32_spi1/2/...status, and stm32_spi1/2/...cmddata must be * provided by board-specific logic. These are implementations of the * select, status, and cmddata methods of the SPI interface defined by * struct spi_ops_s (see include/nuttx/spi/spi.h). All other methods - * (including stm32l4_spibus_initialize()) are provided by common + * (including stm32_spibus_initialize()) are provided by common * STM32 logic. To use this common SPI logic on your board: * - * 1. Provide logic in stm32l4_board_initialize() to configure SPI chip + * 1. Provide logic in stm32_board_initialize() to configure SPI chip * select pins. - * 2. Provide stm32l4_spi1/2/...select() and stm32l4_spi1/2/...status() + * 2. Provide stm32_spi1/2/...select() and stm32_spi1/2/...status() * functions in your board-specific logic. These functions will perform * chip selection and status operations using GPIOs in the way your * board is configured. * 3. If CONFIG_SPI_CMDDATA is defined in your NuttX configuration file, - * then provide stm32l4_spi1/2/...cmddata() functions in your + * then provide stm32_spi1/2/...cmddata() functions in your * board-specific logic. These functions will perform cmd/data selection * operations using GPIOs in the way your board is configured. - * 4. Add a calls to stm32l4_spibus_initialize() in your low level + * 4. Add a calls to stm32_spibus_initialize() in your low level * application initialization logic - * 5. The handle returned by stm32l4_spibus_initialize() may then be used + * 5. The handle returned by stm32_spibus_initialize() may then be used * to bind the SPI driver to higher level logic (e.g., calling * mmcsd_spislotinitialize(), for example, will bind the SPI driver to * the SPI MMC/SD driver). * ****************************************************************************/ -#ifdef CONFIG_STM32L4_SPI1 -void stm32l4_spi1select(struct spi_dev_s *dev, +#ifdef CONFIG_STM32_SPI1 +void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, bool selected); -uint8_t stm32l4_spi1status(struct spi_dev_s *dev, uint32_t devid); -int stm32l4_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); +uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid); +int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); #endif -#ifdef CONFIG_STM32L4_SPI2 -void stm32l4_spi2select(struct spi_dev_s *dev, +#ifdef CONFIG_STM32_SPI2 +void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid, bool selected); -uint8_t stm32l4_spi2status(struct spi_dev_s *dev, uint32_t devid); -int stm32l4_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); +uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid); +int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); #endif -#ifdef CONFIG_STM32L4_SPI3 -void stm32l4_spi3select(struct spi_dev_s *dev, +#ifdef CONFIG_STM32_SPI3 +void stm32_spi3select(struct spi_dev_s *dev, uint32_t devid, bool selected); -uint8_t stm32l4_spi3status(struct spi_dev_s *dev, uint32_t devid); -int stm32l4_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); +uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid); +int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); #endif /**************************************************************************** - * Name: stm32l4_spi1/2/...register + * Name: stm32_spi1/2/...register * * Description: * If the board supports a card detect callback to inform the SPI-based @@ -146,20 +146,20 @@ int stm32l4_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); ****************************************************************************/ #ifdef CONFIG_SPI_CALLBACK -#ifdef CONFIG_STM32L4_SPI1 -int stm32l4_spi1register(struct spi_dev_s *dev, +#ifdef CONFIG_STM32_SPI1 +int stm32_spi1register(struct spi_dev_s *dev, spi_mediachange_t callback, void *arg); #endif -#ifdef CONFIG_STM32L4_SPI2 -int stm32l4_spi2register(struct spi_dev_s *dev, +#ifdef CONFIG_STM32_SPI2 +int stm32_spi2register(struct spi_dev_s *dev, spi_mediachange_t callback, void *arg); #endif -#ifdef CONFIG_STM32L4_SPI3 -int stm32l4_spi3register(struct spi_dev_s *dev, +#ifdef CONFIG_STM32_SPI3 +int stm32_spi3register(struct spi_dev_s *dev, spi_mediachange_t callback, void *arg); #endif @@ -171,4 +171,4 @@ int stm32l4_spi3register(struct spi_dev_s *dev, #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32L4_STM32L4_SPI_H */ +#endif /* __ARCH_ARM_SRC_STM32L4_STM32_SPI_H */ diff --git a/arch/arm/src/stm32l4/stm32l4_start.c b/arch/arm/src/stm32l4/stm32l4_start.c index 64aacd7fc9a01..411490c5bbcba 100644 --- a/arch/arm/src/stm32l4/stm32l4_start.c +++ b/arch/arm/src/stm32l4/stm32l4_start.c @@ -36,7 +36,7 @@ #include "arm_internal.h" #include "nvic.h" -#include "stm32l4.h" +#include "stm32.h" #include "stm32l4_gpio.h" #include "stm32l4_userspace.h" #include "stm32l4_start.h" @@ -60,8 +60,8 @@ * the stack + 4; */ -#define SRAM2_START STM32L4_SRAM2_BASE -#define SRAM2_END (SRAM2_START + STM32L4_SRAM2_SIZE) +#define SRAM2_START STM32_SRAM2_BASE +#define SRAM2_END (SRAM2_START + STM32_SRAM2_SIZE) #define HEAP_BASE ((uintptr_t)_ebss + CONFIG_IDLETHREAD_STACKSIZE) @@ -129,7 +129,7 @@ void __start(void) "r"(CONFIG_IDLETHREAD_STACKSIZE - 64) :); #endif -#ifdef CONFIG_STM32L4_SRAM2_INIT +#ifdef CONFIG_STM32_SRAM2_INIT /* The SRAM2 region is parity checked, but upon power up, it will be in * a random state and probably invalid with respect to parity, potentially * generating faults if accessed. If elected, we will write zeros to the @@ -149,10 +149,10 @@ void __start(void) /* Configure the UART so that we can get debug output as soon as possible */ - stm32l4_clockconfig(); + stm32_clockconfig(); arm_fpuconfig(); - stm32l4_lowsetup(); - stm32l4_gpioinit(); + stm32_lowsetup(); + stm32_gpioinit(); showprogress('A'); /* Clear .bss. We'll do this inline (vs. calling memset) just to be @@ -203,13 +203,13 @@ void __start(void) */ #ifdef CONFIG_BUILD_PROTECTED - stm32l4_userspace(); + stm32_userspace(); showprogress('E'); #endif /* Initialize onboard resources */ - stm32l4_board_initialize(); + stm32_board_initialize(); showprogress('F'); /* Then start NuttX */ diff --git a/arch/arm/src/stm32l4/stm32l4_start.h b/arch/arm/src/stm32l4/stm32l4_start.h index 60f19e7a16a18..ed06d18ea65c1 100644 --- a/arch/arm/src/stm32l4/stm32l4_start.h +++ b/arch/arm/src/stm32l4/stm32l4_start.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32L4_STM32L4_START_H -#define __ARCH_ARM_SRC_STM32L4_STM32L4_START_H +#ifndef __ARCH_ARM_SRC_STM32L4_STM32_START_H +#define __ARCH_ARM_SRC_STM32L4_STM32_START_H /**************************************************************************** * Included Files @@ -32,7 +32,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_board_initialize + * Name: stm32_board_initialize * * Description: * All STM32L4 architectures must provide the following entry point. This @@ -42,6 +42,6 @@ * ****************************************************************************/ -void stm32l4_board_initialize(void); +void stm32_board_initialize(void); -#endif /* __ARCH_ARM_SRC_STM32L4_STM32L4_START_H */ +#endif /* __ARCH_ARM_SRC_STM32L4_STM32_START_H */ diff --git a/arch/arm/src/stm32l4/stm32l4_tickless.c b/arch/arm/src/stm32l4/stm32l4_tickless.c index dba5a51fd3f9f..541399ba03829 100644 --- a/arch/arm/src/stm32l4/stm32l4_tickless.c +++ b/arch/arm/src/stm32l4/stm32l4_tickless.c @@ -87,44 +87,44 @@ * Pre-processor Definitions ****************************************************************************/ -#ifndef CONFIG_STM32L4_ONESHOT -# error CONFIG_STM32L4_ONESHOT must be selected for the Tickless OS option +#ifndef CONFIG_STM32_ONESHOT +# error CONFIG_STM32_ONESHOT must be selected for the Tickless OS option #endif -#ifndef CONFIG_STM32L4_FREERUN -# error CONFIG_STM32L4_FREERUN must be selected for the Tickless OS option +#ifndef CONFIG_STM32_FREERUN +# error CONFIG_STM32_FREERUN must be selected for the Tickless OS option #endif -#ifndef CONFIG_STM32L4_TICKLESS_FREERUN -# error CONFIG_STM32L4_TICKLESS_FREERUN must be selected for the Tickless OS option +#ifndef CONFIG_STM32_TICKLESS_FREERUN +# error CONFIG_STM32_TICKLESS_FREERUN must be selected for the Tickless OS option #endif -#ifndef CONFIG_STM32L4_TICKLESS_ONESHOT -# error CONFIG_STM32L4_TICKLESS_ONESHOT must be selected for the Tickless OS option +#ifndef CONFIG_STM32_TICKLESS_ONESHOT +# error CONFIG_STM32_TICKLESS_ONESHOT must be selected for the Tickless OS option #endif /**************************************************************************** * Private Types ****************************************************************************/ -struct stm32l4_tickless_s +struct stm32_tickless_s { - struct stm32l4_oneshot_s oneshot; - struct stm32l4_freerun_s freerun; + struct stm32_oneshot_s oneshot; + struct stm32_freerun_s freerun; }; /**************************************************************************** * Private Data ****************************************************************************/ -static struct stm32l4_tickless_s g_tickless; +static struct stm32_tickless_s g_tickless; /**************************************************************************** * Private Functions ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_oneshot_handler + * Name: stm32_oneshot_handler * * Description: * Called when the one shot timer expires @@ -141,7 +141,7 @@ static struct stm32l4_tickless_s g_tickless; * ****************************************************************************/ -static void stm32l4_oneshot_handler(void *arg) +static void stm32_oneshot_handler(void *arg) { tmrinfo("Expired...\n"); nxsched_process_timer(); @@ -185,22 +185,22 @@ void up_timer_initialize(void) /* Initialize the one-shot timer */ - ret = stm32l4_oneshot_initialize(&g_tickless.oneshot, - CONFIG_STM32L4_TICKLESS_ONESHOT, + ret = stm32_oneshot_initialize(&g_tickless.oneshot, + CONFIG_STM32_TICKLESS_ONESHOT, CONFIG_USEC_PER_TICK); if (ret < 0) { - tmrerr("ERROR: stm32l4_oneshot_initialize failed\n"); + tmrerr("ERROR: stm32_oneshot_initialize failed\n"); DEBUGPANIC(); } #ifdef CONFIG_SCHED_TICKLESS_LIMIT_MAX_SLEEP /* Get the maximum delay of the one-shot timer in microseconds */ - ret = stm32l4_oneshot_max_delay(&g_tickless.oneshot, &max_delay); + ret = stm32_oneshot_max_delay(&g_tickless.oneshot, &max_delay); if (ret < 0) { - tmrerr("ERROR: stm32l4_oneshot_max_delay failed\n"); + tmrerr("ERROR: stm32_oneshot_max_delay failed\n"); DEBUGPANIC(); } @@ -219,12 +219,12 @@ void up_timer_initialize(void) /* Initialize the free-running timer */ - ret = stm32l4_freerun_initialize(&g_tickless.freerun, - CONFIG_STM32L4_TICKLESS_FREERUN, + ret = stm32_freerun_initialize(&g_tickless.freerun, + CONFIG_STM32_TICKLESS_FREERUN, CONFIG_USEC_PER_TICK); if (ret < 0) { - tmrerr("ERROR: stm32l4_freerun_initialize failed\n"); + tmrerr("ERROR: stm32_freerun_initialize failed\n"); DEBUGPANIC(); } } @@ -264,7 +264,7 @@ void up_timer_initialize(void) int up_timer_gettime(struct timespec *ts) { - return stm32l4_freerun_counter(&g_tickless.freerun, ts); + return stm32_freerun_counter(&g_tickless.freerun, ts); } /**************************************************************************** @@ -305,7 +305,7 @@ int up_timer_gettime(struct timespec *ts) int up_timer_cancel(struct timespec *ts) { - return stm32l4_oneshot_cancel(&g_tickless.oneshot, ts); + return stm32_oneshot_cancel(&g_tickless.oneshot, ts); } /**************************************************************************** @@ -335,7 +335,7 @@ int up_timer_cancel(struct timespec *ts) int up_timer_start(const struct timespec *ts) { - return stm32l4_oneshot_start(&g_tickless.oneshot, - stm32l4_oneshot_handler, NULL, ts); + return stm32_oneshot_start(&g_tickless.oneshot, + stm32_oneshot_handler, NULL, ts); } #endif /* CONFIG_SCHED_TICKLESS */ diff --git a/arch/arm/src/stm32l4/stm32l4_tim.c b/arch/arm/src/stm32l4/stm32l4_tim.c index 6facb4e747f88..65a83b9158990 100644 --- a/arch/arm/src/stm32l4/stm32l4_tim.c +++ b/arch/arm/src/stm32l4/stm32l4_tim.c @@ -39,7 +39,7 @@ #include "chip.h" #include "arm_internal.h" -#include "stm32l4.h" +#include "stm32.h" #include "stm32l4_gpio.h" #include "stm32l4_tim.h" @@ -53,137 +53,137 @@ * Such special purposes include: * * - To generate modulated outputs for such things as motor control. If - * CONFIG_STM32L4_TIMn is defined then the CONFIG_STM32L4_TIMn_PWM may also + * CONFIG_STM32_TIMn is defined then the CONFIG_STM32_TIMn_PWM may also * be defined to indicate that the timer is intended to be used for pulsed * output modulation. * - * - To control periodic ADC input sampling. If CONFIG_STM32L4_TIMn is - * defined then CONFIG_STM32L4_TIMn_ADC may also be defined to indicate + * - To control periodic ADC input sampling. If CONFIG_STM32_TIMn is + * defined then CONFIG_STM32_TIMn_ADC may also be defined to indicate * that timer "n" is intended to be used for that purpose. * - * - To control periodic DAC outputs. If CONFIG_STM32L4_TIMn is defined then - * CONFIG_STM32L4_TIMn_DAC may also be defined to indicate that timer "n" + * - To control periodic DAC outputs. If CONFIG_STM32_TIMn is defined then + * CONFIG_STM32_TIMn_DAC may also be defined to indicate that timer "n" * is intended to be used for that purpose. * - * - To use a Quadrature Encoder. If CONFIG_STM32L4_TIMn is defined then - * CONFIG_STM32L4_TIMn_QE may also be defined to indicate that timer "n" + * - To use a Quadrature Encoder. If CONFIG_STM32_TIMn is defined then + * CONFIG_STM32_TIMn_QE may also be defined to indicate that timer "n" * is intended to be used for that purpose. * * In any of these cases, the timer will not be used by this timer module. */ -#if defined(CONFIG_STM32L4_TIM1_PWM) || defined (CONFIG_STM32L4_TIM1_ADC) || \ - defined(CONFIG_STM32L4_TIM1_DAC) || defined(CONFIG_STM32L4_TIM1_QE) -# undef CONFIG_STM32L4_TIM1 +#if defined(CONFIG_STM32_TIM1_PWM) || defined (CONFIG_STM32_TIM1_ADC) || \ + defined(CONFIG_STM32_TIM1_DAC) || defined(CONFIG_STM32_TIM1_QE) +# undef CONFIG_STM32_TIM1 #endif -#if defined(CONFIG_STM32L4_TIM2_PWM) || defined (CONFIG_STM32L4_TIM2_ADC) || \ - defined(CONFIG_STM32L4_TIM2_DAC) || defined(CONFIG_STM32L4_TIM2_QE) -# undef CONFIG_STM32L4_TIM2 +#if defined(CONFIG_STM32_TIM2_PWM) || defined (CONFIG_STM32_TIM2_ADC) || \ + defined(CONFIG_STM32_TIM2_DAC) || defined(CONFIG_STM32_TIM2_QE) +# undef CONFIG_STM32_TIM2 #endif -#if defined(CONFIG_STM32L4_TIM3_PWM) || defined (CONFIG_STM32L4_TIM3_ADC) || \ - defined(CONFIG_STM32L4_TIM3_DAC) || defined(CONFIG_STM32L4_TIM3_QE) -# undef CONFIG_STM32L4_TIM3 +#if defined(CONFIG_STM32_TIM3_PWM) || defined (CONFIG_STM32_TIM3_ADC) || \ + defined(CONFIG_STM32_TIM3_DAC) || defined(CONFIG_STM32_TIM3_QE) +# undef CONFIG_STM32_TIM3 #endif -#if defined(CONFIG_STM32L4_TIM4_PWM) || defined (CONFIG_STM32L4_TIM4_ADC) || \ - defined(CONFIG_STM32L4_TIM4_DAC) || defined(CONFIG_STM32L4_TIM4_QE) -# undef CONFIG_STM32L4_TIM4 +#if defined(CONFIG_STM32_TIM4_PWM) || defined (CONFIG_STM32_TIM4_ADC) || \ + defined(CONFIG_STM32_TIM4_DAC) || defined(CONFIG_STM32_TIM4_QE) +# undef CONFIG_STM32_TIM4 #endif -#if defined(CONFIG_STM32L4_TIM5_PWM) || defined (CONFIG_STM32L4_TIM5_ADC) || \ - defined(CONFIG_STM32L4_TIM5_DAC) || defined(CONFIG_STM32L4_TIM5_QE) -# undef CONFIG_STM32L4_TIM5 +#if defined(CONFIG_STM32_TIM5_PWM) || defined (CONFIG_STM32_TIM5_ADC) || \ + defined(CONFIG_STM32_TIM5_DAC) || defined(CONFIG_STM32_TIM5_QE) +# undef CONFIG_STM32_TIM5 #endif -#if defined(CONFIG_STM32L4_TIM6_PWM) || defined (CONFIG_STM32L4_TIM6_ADC) || \ - defined(CONFIG_STM32L4_TIM6_DAC) || defined(CONFIG_STM32L4_TIM6_QE) -# undef CONFIG_STM32L4_TIM6 +#if defined(CONFIG_STM32_TIM6_PWM) || defined (CONFIG_STM32_TIM6_ADC) || \ + defined(CONFIG_STM32_TIM6_DAC) || defined(CONFIG_STM32_TIM6_QE) +# undef CONFIG_STM32_TIM6 #endif -#if defined(CONFIG_STM32L4_TIM7_PWM) || defined (CONFIG_STM32L4_TIM7_ADC) || \ - defined(CONFIG_STM32L4_TIM7_DAC) || defined(CONFIG_STM32L4_TIM7_QE) -# undef CONFIG_STM32L4_TIM7 +#if defined(CONFIG_STM32_TIM7_PWM) || defined (CONFIG_STM32_TIM7_ADC) || \ + defined(CONFIG_STM32_TIM7_DAC) || defined(CONFIG_STM32_TIM7_QE) +# undef CONFIG_STM32_TIM7 #endif -#if defined(CONFIG_STM32L4_TIM8_PWM) || defined (CONFIG_STM32L4_TIM8_ADC) || \ - defined(CONFIG_STM32L4_TIM8_DAC) || defined(CONFIG_STM32L4_TIM8_QE) -# undef CONFIG_STM32L4_TIM8 +#if defined(CONFIG_STM32_TIM8_PWM) || defined (CONFIG_STM32_TIM8_ADC) || \ + defined(CONFIG_STM32_TIM8_DAC) || defined(CONFIG_STM32_TIM8_QE) +# undef CONFIG_STM32_TIM8 #endif -#if defined(CONFIG_STM32L4_TIM15_PWM) || defined (CONFIG_STM32L4_TIM15_ADC) || \ - defined(CONFIG_STM32L4_TIM15_DAC) || defined(CONFIG_STM32L4_TIM15_QE) -# undef CONFIG_STM32L4_TIM15 +#if defined(CONFIG_STM32_TIM15_PWM) || defined (CONFIG_STM32_TIM15_ADC) || \ + defined(CONFIG_STM32_TIM15_DAC) || defined(CONFIG_STM32_TIM15_QE) +# undef CONFIG_STM32_TIM15 #endif -#if defined(CONFIG_STM32L4_TIM16_PWM) || defined (CONFIG_STM32L4_TIM16_ADC) || \ - defined(CONFIG_STM32L4_TIM16_DAC) || defined(CONFIG_STM32L4_TIM16_QE) -# undef CONFIG_STM32L4_TIM16 +#if defined(CONFIG_STM32_TIM16_PWM) || defined (CONFIG_STM32_TIM16_ADC) || \ + defined(CONFIG_STM32_TIM16_DAC) || defined(CONFIG_STM32_TIM16_QE) +# undef CONFIG_STM32_TIM16 #endif -#if defined(CONFIG_STM32L4_TIM17_PWM) || defined (CONFIG_STM32L4_TIM17_ADC) || \ - defined(CONFIG_STM32L4_TIM17_DAC) || defined(CONFIG_STM32L4_TIM17_QE) -# undef CONFIG_STM32L4_TIM17 +#if defined(CONFIG_STM32_TIM17_PWM) || defined (CONFIG_STM32_TIM17_ADC) || \ + defined(CONFIG_STM32_TIM17_DAC) || defined(CONFIG_STM32_TIM17_QE) +# undef CONFIG_STM32_TIM17 #endif -#if defined(CONFIG_STM32L4_TIM1) +#if defined(CONFIG_STM32_TIM1) # if defined(GPIO_TIM1_CH1OUT) ||defined(GPIO_TIM1_CH2OUT)||\ defined(GPIO_TIM1_CH3OUT) ||defined(GPIO_TIM1_CH4OUT) # define HAVE_TIM1_GPIOCONFIG 1 #endif #endif -#if defined(CONFIG_STM32L4_TIM2) +#if defined(CONFIG_STM32_TIM2) # if defined(GPIO_TIM2_CH1OUT) ||defined(GPIO_TIM2_CH2OUT)||\ defined(GPIO_TIM2_CH3OUT) ||defined(GPIO_TIM2_CH4OUT) # define HAVE_TIM2_GPIOCONFIG 1 #endif #endif -#if defined(CONFIG_STM32L4_TIM3) +#if defined(CONFIG_STM32_TIM3) # if defined(GPIO_TIM3_CH1OUT) ||defined(GPIO_TIM3_CH2OUT)||\ defined(GPIO_TIM3_CH3OUT) ||defined(GPIO_TIM3_CH4OUT) # define HAVE_TIM3_GPIOCONFIG 1 #endif #endif -#if defined(CONFIG_STM32L4_TIM4) +#if defined(CONFIG_STM32_TIM4) # if defined(GPIO_TIM4_CH1OUT) ||defined(GPIO_TIM4_CH2OUT)||\ defined(GPIO_TIM4_CH3OUT) ||defined(GPIO_TIM4_CH4OUT) # define HAVE_TIM4_GPIOCONFIG 1 #endif #endif -#if defined(CONFIG_STM32L4_TIM5) +#if defined(CONFIG_STM32_TIM5) # if defined(GPIO_TIM5_CH1OUT) ||defined(GPIO_TIM5_CH2OUT)||\ defined(GPIO_TIM5_CH3OUT) ||defined(GPIO_TIM5_CH4OUT) # define HAVE_TIM5_GPIOCONFIG 1 #endif #endif -#if defined(CONFIG_STM32L4_TIM8) +#if defined(CONFIG_STM32_TIM8) # if defined(GPIO_TIM8_CH1OUT) ||defined(GPIO_TIM8_CH2OUT)||\ defined(GPIO_TIM8_CH3OUT) ||defined(GPIO_TIM8_CH4OUT) # define HAVE_TIM8_GPIOCONFIG 1 #endif #endif -#if defined(CONFIG_STM32L4_TIM15) +#if defined(CONFIG_STM32_TIM15) # if defined(GPIO_TIM15_CH1OUT) ||defined(GPIO_TIM15_CH2OUT)||\ defined(GPIO_TIM15_CH3OUT) ||defined(GPIO_TIM15_CH4OUT) # define HAVE_TIM15_GPIOCONFIG 1 #endif #endif -#if defined(CONFIG_STM32L4_TIM16) +#if defined(CONFIG_STM32_TIM16) # if defined(GPIO_TIM16_CH1OUT) ||defined(GPIO_TIM16_CH2OUT)||\ defined(GPIO_TIM16_CH3OUT) ||defined(GPIO_TIM16_CH4OUT) # define HAVE_TIM16_GPIOCONFIG 1 #endif #endif -#if defined(CONFIG_STM32L4_TIM17) +#if defined(CONFIG_STM32_TIM17) # if defined(GPIO_TIM17_CH1OUT) ||defined(GPIO_TIM17_CH2OUT)||\ defined(GPIO_TIM17_CH3OUT) ||defined(GPIO_TIM17_CH4OUT) # define HAVE_TIM17_GPIOCONFIG 1 @@ -194,12 +194,12 @@ * intended for some other purpose. */ -#if defined(CONFIG_STM32L4_TIM1) || defined(CONFIG_STM32L4_TIM2) || \ - defined(CONFIG_STM32L4_TIM3) || defined(CONFIG_STM32L4_TIM4) || \ - defined(CONFIG_STM32L4_TIM5) || defined(CONFIG_STM32L4_TIM6) || \ - defined(CONFIG_STM32L4_TIM7) || defined(CONFIG_STM32L4_TIM8) || \ - defined(CONFIG_STM32L4_TIM15) || defined(CONFIG_STM32L4_TIM16) || \ - defined(CONFIG_STM32L4_TIM17) +#if defined(CONFIG_STM32_TIM1) || defined(CONFIG_STM32_TIM2) || \ + defined(CONFIG_STM32_TIM3) || defined(CONFIG_STM32_TIM4) || \ + defined(CONFIG_STM32_TIM5) || defined(CONFIG_STM32_TIM6) || \ + defined(CONFIG_STM32_TIM7) || defined(CONFIG_STM32_TIM8) || \ + defined(CONFIG_STM32_TIM15) || defined(CONFIG_STM32_TIM16) || \ + defined(CONFIG_STM32_TIM17) /**************************************************************************** * Private Types @@ -207,10 +207,10 @@ /* TIM Device Structure */ -struct stm32l4_tim_priv_s +struct stm32_tim_priv_s { - const struct stm32l4_tim_ops_s *ops; - enum stm32l4_tim_mode_e mode; + const struct stm32_tim_ops_s *ops; + enum stm32_tim_mode_e mode; uint32_t base; /* TIMn base address */ }; @@ -220,186 +220,186 @@ struct stm32l4_tim_priv_s /* Register helpers */ -static inline uint16_t stm32l4_getreg16(struct stm32l4_tim_dev_s *dev, +static inline uint16_t stm32_getreg16(struct stm32_tim_dev_s *dev, uint8_t offset); -static inline void stm32l4_putreg16(struct stm32l4_tim_dev_s *dev, +static inline void stm32_putreg16(struct stm32_tim_dev_s *dev, uint8_t offset, uint16_t value); -static inline void stm32l4_modifyreg16(struct stm32l4_tim_dev_s *dev, +static inline void stm32_modifyreg16(struct stm32_tim_dev_s *dev, uint8_t offset, uint16_t clearbits, uint16_t setbits); -static inline uint32_t stm32l4_getreg32(struct stm32l4_tim_dev_s *dev, +static inline uint32_t stm32_getreg32(struct stm32_tim_dev_s *dev, uint8_t offset); -static inline void stm32l4_putreg32(struct stm32l4_tim_dev_s *dev, +static inline void stm32_putreg32(struct stm32_tim_dev_s *dev, uint8_t offset, uint32_t value); /* Timer helpers */ -static void stm32l4_tim_reload_counter(struct stm32l4_tim_dev_s *dev); -static void stm32l4_tim_enable(struct stm32l4_tim_dev_s *dev); -static void stm32l4_tim_disable(struct stm32l4_tim_dev_s *dev); -static void stm32l4_tim_reset(struct stm32l4_tim_dev_s *dev); +static void stm32_tim_reload_counter(struct stm32_tim_dev_s *dev); +static void stm32_tim_enable(struct stm32_tim_dev_s *dev); +static void stm32_tim_disable(struct stm32_tim_dev_s *dev); +static void stm32_tim_reset(struct stm32_tim_dev_s *dev); #if defined(HAVE_TIM1_GPIOCONFIG) || defined(HAVE_TIM2_GPIOCONFIG) || \ defined(HAVE_TIM3_GPIOCONFIG) || defined(HAVE_TIM4_GPIOCONFIG) || \ defined(HAVE_TIM5_GPIOCONFIG) || defined(HAVE_TIM8_GPIOCONFIG) || \ defined(HAVE_TIM15_GPIOCONFIG) || defined(HAVE_TIM16_GPIOCONFIG) || \ defined(HAVE_TIM17_GPIOCONFIG) -static void stm32l4_tim_gpioconfig(uint32_t cfg, - enum stm32l4_tim_channel_e mode); +static void stm32_tim_gpioconfig(uint32_t cfg, + enum stm32_tim_channel_e mode); #endif -static void stm32l4_tim_dumpregs(struct stm32l4_tim_dev_s *dev); +static void stm32_tim_dumpregs(struct stm32_tim_dev_s *dev); /* Timer methods */ -static int stm32l4_tim_setmode(struct stm32l4_tim_dev_s *dev, - enum stm32l4_tim_mode_e mode); -static int stm32l4_tim_setfreq(struct stm32l4_tim_dev_s *dev, +static int stm32_tim_setmode(struct stm32_tim_dev_s *dev, + enum stm32_tim_mode_e mode); +static int stm32_tim_setfreq(struct stm32_tim_dev_s *dev, uint32_t freq); -static int stm32l4_tim_setclock(struct stm32l4_tim_dev_s *dev, +static int stm32_tim_setclock(struct stm32_tim_dev_s *dev, uint32_t freq); -static uint32_t stm32l4_tim_getclock(struct stm32l4_tim_dev_s *dev); -static void stm32l4_tim_setperiod(struct stm32l4_tim_dev_s *dev, +static uint32_t stm32_tim_getclock(struct stm32_tim_dev_s *dev); +static void stm32_tim_setperiod(struct stm32_tim_dev_s *dev, uint32_t period); -static uint32_t stm32l4_tim_getperiod(struct stm32l4_tim_dev_s *dev); -static uint32_t stm32l4_tim_getcounter(struct stm32l4_tim_dev_s *dev); -static int stm32l4_tim_setchannel(struct stm32l4_tim_dev_s *dev, +static uint32_t stm32_tim_getperiod(struct stm32_tim_dev_s *dev); +static uint32_t stm32_tim_getcounter(struct stm32_tim_dev_s *dev); +static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, uint8_t channel, - enum stm32l4_tim_channel_e mode); -static int stm32l4_tim_setcompare(struct stm32l4_tim_dev_s *dev, + enum stm32_tim_channel_e mode); +static int stm32_tim_setcompare(struct stm32_tim_dev_s *dev, uint8_t channel, uint32_t compare); -static int stm32l4_tim_getcapture(struct stm32l4_tim_dev_s *dev, +static int stm32_tim_getcapture(struct stm32_tim_dev_s *dev, uint8_t channel); -static int stm32l4_tim_setisr(struct stm32l4_tim_dev_s *dev, +static int stm32_tim_setisr(struct stm32_tim_dev_s *dev, xcpt_t handler, void *arg, int source); -static void stm32l4_tim_enableint(struct stm32l4_tim_dev_s *dev, +static void stm32_tim_enableint(struct stm32_tim_dev_s *dev, int source); -static void stm32l4_tim_disableint(struct stm32l4_tim_dev_s *dev, +static void stm32_tim_disableint(struct stm32_tim_dev_s *dev, int source); -static void stm32l4_tim_ackint(struct stm32l4_tim_dev_s *dev, +static void stm32_tim_ackint(struct stm32_tim_dev_s *dev, int source); -static int stm32l4_tim_checkint(struct stm32l4_tim_dev_s *dev, +static int stm32_tim_checkint(struct stm32_tim_dev_s *dev, int source); /**************************************************************************** * Private Data ****************************************************************************/ -static const struct stm32l4_tim_ops_s stm32l4_tim_ops = +static const struct stm32_tim_ops_s stm32_tim_ops = { - .enable = stm32l4_tim_enable, - .disable = stm32l4_tim_disable, - .setmode = stm32l4_tim_setmode, - .setfreq = stm32l4_tim_setfreq, - .setclock = stm32l4_tim_setclock, - .getclock = stm32l4_tim_getclock, - .setperiod = stm32l4_tim_setperiod, - .getperiod = stm32l4_tim_getperiod, - .getcounter = stm32l4_tim_getcounter, - .setchannel = stm32l4_tim_setchannel, - .setcompare = stm32l4_tim_setcompare, - .getcapture = stm32l4_tim_getcapture, - .setisr = stm32l4_tim_setisr, - .enableint = stm32l4_tim_enableint, - .disableint = stm32l4_tim_disableint, - .ackint = stm32l4_tim_ackint, - .checkint = stm32l4_tim_checkint, - .dump_regs = stm32l4_tim_dumpregs, + .enable = stm32_tim_enable, + .disable = stm32_tim_disable, + .setmode = stm32_tim_setmode, + .setfreq = stm32_tim_setfreq, + .setclock = stm32_tim_setclock, + .getclock = stm32_tim_getclock, + .setperiod = stm32_tim_setperiod, + .getperiod = stm32_tim_getperiod, + .getcounter = stm32_tim_getcounter, + .setchannel = stm32_tim_setchannel, + .setcompare = stm32_tim_setcompare, + .getcapture = stm32_tim_getcapture, + .setisr = stm32_tim_setisr, + .enableint = stm32_tim_enableint, + .disableint = stm32_tim_disableint, + .ackint = stm32_tim_ackint, + .checkint = stm32_tim_checkint, + .dump_regs = stm32_tim_dumpregs, }; -#ifdef CONFIG_STM32L4_TIM1 -struct stm32l4_tim_priv_s stm32l4_tim1_priv = +#ifdef CONFIG_STM32_TIM1 +struct stm32_tim_priv_s stm32_tim1_priv = { - .ops = &stm32l4_tim_ops, - .mode = STM32L4_TIM_MODE_UNUSED, - .base = STM32L4_TIM1_BASE, + .ops = &stm32_tim_ops, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM1_BASE, }; #endif -#ifdef CONFIG_STM32L4_TIM2 -struct stm32l4_tim_priv_s stm32l4_tim2_priv = +#ifdef CONFIG_STM32_TIM2 +struct stm32_tim_priv_s stm32_tim2_priv = { - .ops = &stm32l4_tim_ops, - .mode = STM32L4_TIM_MODE_UNUSED, - .base = STM32L4_TIM2_BASE, + .ops = &stm32_tim_ops, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM2_BASE, }; #endif -#ifdef CONFIG_STM32L4_TIM3 -struct stm32l4_tim_priv_s stm32l4_tim3_priv = +#ifdef CONFIG_STM32_TIM3 +struct stm32_tim_priv_s stm32_tim3_priv = { - .ops = &stm32l4_tim_ops, - .mode = STM32L4_TIM_MODE_UNUSED, - .base = STM32L4_TIM3_BASE, + .ops = &stm32_tim_ops, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM3_BASE, }; #endif -#ifdef CONFIG_STM32L4_TIM4 -struct stm32l4_tim_priv_s stm32l4_tim4_priv = +#ifdef CONFIG_STM32_TIM4 +struct stm32_tim_priv_s stm32_tim4_priv = { - .ops = &stm32l4_tim_ops, - .mode = STM32L4_TIM_MODE_UNUSED, - .base = STM32L4_TIM4_BASE, + .ops = &stm32_tim_ops, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM4_BASE, }; #endif -#ifdef CONFIG_STM32L4_TIM5 -struct stm32l4_tim_priv_s stm32l4_tim5_priv = +#ifdef CONFIG_STM32_TIM5 +struct stm32_tim_priv_s stm32_tim5_priv = { - .ops = &stm32l4_tim_ops, - .mode = STM32L4_TIM_MODE_UNUSED, - .base = STM32L4_TIM5_BASE, + .ops = &stm32_tim_ops, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM5_BASE, }; #endif -#ifdef CONFIG_STM32L4_TIM6 -struct stm32l4_tim_priv_s stm32l4_tim6_priv = +#ifdef CONFIG_STM32_TIM6 +struct stm32_tim_priv_s stm32_tim6_priv = { - .ops = &stm32l4_tim_ops, - .mode = STM32L4_TIM_MODE_UNUSED, - .base = STM32L4_TIM6_BASE, + .ops = &stm32_tim_ops, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM6_BASE, }; #endif -#ifdef CONFIG_STM32L4_TIM7 -struct stm32l4_tim_priv_s stm32l4_tim7_priv = +#ifdef CONFIG_STM32_TIM7 +struct stm32_tim_priv_s stm32_tim7_priv = { - .ops = &stm32l4_tim_ops, - .mode = STM32L4_TIM_MODE_UNUSED, - .base = STM32L4_TIM7_BASE, + .ops = &stm32_tim_ops, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM7_BASE, }; #endif -#ifdef CONFIG_STM32L4_TIM8 -struct stm32l4_tim_priv_s stm32l4_tim8_priv = +#ifdef CONFIG_STM32_TIM8 +struct stm32_tim_priv_s stm32_tim8_priv = { - .ops = &stm32l4_tim_ops, - .mode = STM32L4_TIM_MODE_UNUSED, - .base = STM32L4_TIM8_BASE, + .ops = &stm32_tim_ops, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM8_BASE, }; #endif -#ifdef CONFIG_STM32L4_TIM15 -struct stm32l4_tim_priv_s stm32l4_tim15_priv = +#ifdef CONFIG_STM32_TIM15 +struct stm32_tim_priv_s stm32_tim15_priv = { - .ops = &stm32l4_tim_ops, - .mode = STM32L4_TIM_MODE_UNUSED, - .base = STM32L4_TIM15_BASE, + .ops = &stm32_tim_ops, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM15_BASE, }; #endif -#ifdef CONFIG_STM32L4_TIM16 -struct stm32l4_tim_priv_s stm32l4_tim16_priv = +#ifdef CONFIG_STM32_TIM16 +struct stm32_tim_priv_s stm32_tim16_priv = { - .ops = &stm32l4_tim_ops, - .mode = STM32L4_TIM_MODE_UNUSED, - .base = STM32L4_TIM16_BASE, + .ops = &stm32_tim_ops, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM16_BASE, }; #endif -#ifdef CONFIG_STM32L4_TIM17 -struct stm32l4_tim_priv_s stm32l4_tim17_priv = +#ifdef CONFIG_STM32_TIM17 +struct stm32_tim_priv_s stm32_tim17_priv = { - .ops = &stm32l4_tim_ops, - .mode = STM32L4_TIM_MODE_UNUSED, - .base = STM32L4_TIM17_BASE, + .ops = &stm32_tim_ops, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM17_BASE, }; #endif @@ -408,51 +408,51 @@ struct stm32l4_tim_priv_s stm32l4_tim17_priv = ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_getreg16 + * Name: stm32_getreg16 * * Description: * Get a 16-bit register value by offset * ****************************************************************************/ -static inline uint16_t stm32l4_getreg16(struct stm32l4_tim_dev_s *dev, +static inline uint16_t stm32_getreg16(struct stm32_tim_dev_s *dev, uint8_t offset) { - return getreg16(((struct stm32l4_tim_priv_s *)dev)->base + offset); + return getreg16(((struct stm32_tim_priv_s *)dev)->base + offset); } /**************************************************************************** - * Name: stm32l4_putreg16 + * Name: stm32_putreg16 * * Description: * Put a 16-bit register value by offset * ****************************************************************************/ -static inline void stm32l4_putreg16(struct stm32l4_tim_dev_s *dev, +static inline void stm32_putreg16(struct stm32_tim_dev_s *dev, uint8_t offset, uint16_t value) { - putreg16(value, ((struct stm32l4_tim_priv_s *)dev)->base + offset); + putreg16(value, ((struct stm32_tim_priv_s *)dev)->base + offset); } /**************************************************************************** - * Name: stm32l4_modifyreg16 + * Name: stm32_modifyreg16 * * Description: * Modify a 16-bit register value by offset * ****************************************************************************/ -static inline void stm32l4_modifyreg16(struct stm32l4_tim_dev_s *dev, +static inline void stm32_modifyreg16(struct stm32_tim_dev_s *dev, uint8_t offset, uint16_t clearbits, uint16_t setbits) { - modifyreg16(((struct stm32l4_tim_priv_s *)dev)->base + offset, clearbits, + modifyreg16(((struct stm32_tim_priv_s *)dev)->base + offset, clearbits, setbits); } /**************************************************************************** - * Name: stm32l4_getreg32 + * Name: stm32_getreg32 * * Description: * Get a 32-bit register value by offset. This applies only for the STM32 @@ -460,14 +460,14 @@ static inline void stm32l4_modifyreg16(struct stm32l4_tim_dev_s *dev, * ****************************************************************************/ -static inline uint32_t stm32l4_getreg32(struct stm32l4_tim_dev_s *dev, +static inline uint32_t stm32_getreg32(struct stm32_tim_dev_s *dev, uint8_t offset) { - return getreg32(((struct stm32l4_tim_priv_s *)dev)->base + offset); + return getreg32(((struct stm32_tim_priv_s *)dev)->base + offset); } /**************************************************************************** - * Name: stm32l4_putreg32 + * Name: stm32_putreg32 * * Description: * Put a 32-bit register value by offset. This applies only for the STM32 @@ -475,49 +475,49 @@ static inline uint32_t stm32l4_getreg32(struct stm32l4_tim_dev_s *dev, * ****************************************************************************/ -static inline void stm32l4_putreg32(struct stm32l4_tim_dev_s *dev, +static inline void stm32_putreg32(struct stm32_tim_dev_s *dev, uint8_t offset, uint32_t value) { - putreg32(value, ((struct stm32l4_tim_priv_s *)dev)->base + offset); + putreg32(value, ((struct stm32_tim_priv_s *)dev)->base + offset); } /**************************************************************************** - * Name: stm32l4_tim_reload_counter + * Name: stm32_tim_reload_counter ****************************************************************************/ -static void stm32l4_tim_reload_counter(struct stm32l4_tim_dev_s *dev) +static void stm32_tim_reload_counter(struct stm32_tim_dev_s *dev) { - uint16_t val = stm32l4_getreg16(dev, STM32L4_GTIM_EGR_OFFSET); + uint16_t val = stm32_getreg16(dev, STM32_GTIM_EGR_OFFSET); val |= GTIM_EGR_UG; - stm32l4_putreg16(dev, STM32L4_GTIM_EGR_OFFSET, val); + stm32_putreg16(dev, STM32_GTIM_EGR_OFFSET, val); } /**************************************************************************** - * Name: stm32l4_tim_enable + * Name: stm32_tim_enable ****************************************************************************/ -static void stm32l4_tim_enable(struct stm32l4_tim_dev_s *dev) +static void stm32_tim_enable(struct stm32_tim_dev_s *dev) { - uint16_t val = stm32l4_getreg16(dev, STM32L4_GTIM_CR1_OFFSET); + uint16_t val = stm32_getreg16(dev, STM32_GTIM_CR1_OFFSET); val |= GTIM_CR1_CEN; - stm32l4_tim_reload_counter(dev); - stm32l4_putreg16(dev, STM32L4_GTIM_CR1_OFFSET, val); + stm32_tim_reload_counter(dev); + stm32_putreg16(dev, STM32_GTIM_CR1_OFFSET, val); } /**************************************************************************** - * Name: stm32l4_tim_disable + * Name: stm32_tim_disable ****************************************************************************/ -static void stm32l4_tim_disable(struct stm32l4_tim_dev_s *dev) +static void stm32_tim_disable(struct stm32_tim_dev_s *dev) { - uint16_t val = stm32l4_getreg16(dev, STM32L4_GTIM_CR1_OFFSET); + uint16_t val = stm32_getreg16(dev, STM32_GTIM_CR1_OFFSET); val &= ~GTIM_CR1_CEN; - stm32l4_putreg16(dev, STM32L4_GTIM_CR1_OFFSET, val); + stm32_putreg16(dev, STM32_GTIM_CR1_OFFSET, val); } /**************************************************************************** - * Name: stm32l4_tim_reset + * Name: stm32_tim_reset * * Description: * Reset timer into system default state, but do not affect output/input @@ -525,14 +525,14 @@ static void stm32l4_tim_disable(struct stm32l4_tim_dev_s *dev) * ****************************************************************************/ -static void stm32l4_tim_reset(struct stm32l4_tim_dev_s *dev) +static void stm32_tim_reset(struct stm32_tim_dev_s *dev) { - ((struct stm32l4_tim_priv_s *)dev)->mode = STM32L4_TIM_MODE_DISABLED; - stm32l4_tim_disable(dev); + ((struct stm32_tim_priv_s *)dev)->mode = STM32_TIM_MODE_DISABLED; + stm32_tim_disable(dev); } /**************************************************************************** - * Name: stm32l4_tim_gpioconfig + * Name: stm32_tim_gpioconfig ****************************************************************************/ #if defined(HAVE_TIM1_GPIOCONFIG) || defined(HAVE_TIM2_GPIOCONFIG) || \ @@ -540,78 +540,78 @@ static void stm32l4_tim_reset(struct stm32l4_tim_dev_s *dev) defined(HAVE_TIM5_GPIOCONFIG) || defined(HAVE_TIM8_GPIOCONFIG) || \ defined(HAVE_TIM15_GPIOCONFIG) || defined(HAVE_TIM16_GPIOCONFIG) || \ defined(HAVE_TIM17_GPIOCONFIG) -static void stm32l4_tim_gpioconfig(uint32_t cfg, - enum stm32l4_tim_channel_e mode) +static void stm32_tim_gpioconfig(uint32_t cfg, + enum stm32_tim_channel_e mode) { /* TODO: * Add support for input capture and bipolar dual outputs for TIM8 */ - if (mode & STM32L4_TIM_CH_MODE_MASK) + if (mode & STM32_TIM_CH_MODE_MASK) { - stm32l4_configgpio(cfg); + stm32_configgpio(cfg); } else { - stm32l4_unconfiggpio(cfg); + stm32_unconfiggpio(cfg); } } #endif /**************************************************************************** - * Name: stm32l4_tim_dumpregs + * Name: stm32_tim_dumpregs ****************************************************************************/ -static void stm32l4_tim_dumpregs(struct stm32l4_tim_dev_s *dev) +static void stm32_tim_dumpregs(struct stm32_tim_dev_s *dev) { - struct stm32l4_tim_priv_s *priv = (struct stm32l4_tim_priv_s *)dev; + struct stm32_tim_priv_s *priv = (struct stm32_tim_priv_s *)dev; ainfo(" CR1: %04x CR2: %04x SMCR: %04x DIER: %04x\n", - stm32l4_getreg16(dev, STM32L4_GTIM_CR1_OFFSET), - stm32l4_getreg16(dev, STM32L4_GTIM_CR2_OFFSET), - stm32l4_getreg16(dev, STM32L4_GTIM_SMCR_OFFSET), - stm32l4_getreg16(dev, STM32L4_GTIM_DIER_OFFSET) + stm32_getreg16(dev, STM32_GTIM_CR1_OFFSET), + stm32_getreg16(dev, STM32_GTIM_CR2_OFFSET), + stm32_getreg16(dev, STM32_GTIM_SMCR_OFFSET), + stm32_getreg16(dev, STM32_GTIM_DIER_OFFSET) ); ainfo(" SR: %04x EGR: 0000 CCMR1: %04x CCMR2: %04x\n", - stm32l4_getreg16(dev, STM32L4_GTIM_SR_OFFSET), - stm32l4_getreg16(dev, STM32L4_GTIM_CCMR1_OFFSET), - stm32l4_getreg16(dev, STM32L4_GTIM_CCMR2_OFFSET) + stm32_getreg16(dev, STM32_GTIM_SR_OFFSET), + stm32_getreg16(dev, STM32_GTIM_CCMR1_OFFSET), + stm32_getreg16(dev, STM32_GTIM_CCMR2_OFFSET) ); ainfo(" CCER: %04x CNT: %04x PSC: %04x ARR: %04x\n", - stm32l4_getreg16(dev, STM32L4_GTIM_CCER_OFFSET), - stm32l4_getreg16(dev, STM32L4_GTIM_CNT_OFFSET), - stm32l4_getreg16(dev, STM32L4_GTIM_PSC_OFFSET), - stm32l4_getreg16(dev, STM32L4_GTIM_ARR_OFFSET) + stm32_getreg16(dev, STM32_GTIM_CCER_OFFSET), + stm32_getreg16(dev, STM32_GTIM_CNT_OFFSET), + stm32_getreg16(dev, STM32_GTIM_PSC_OFFSET), + stm32_getreg16(dev, STM32_GTIM_ARR_OFFSET) ); ainfo(" CCR1: %04x CCR2: %04x CCR3: %04x CCR4: %04x\n", - stm32l4_getreg16(dev, STM32L4_GTIM_CCR1_OFFSET), - stm32l4_getreg16(dev, STM32L4_GTIM_CCR2_OFFSET), - stm32l4_getreg16(dev, STM32L4_GTIM_CCR3_OFFSET), - stm32l4_getreg16(dev, STM32L4_GTIM_CCR4_OFFSET) + stm32_getreg16(dev, STM32_GTIM_CCR1_OFFSET), + stm32_getreg16(dev, STM32_GTIM_CCR2_OFFSET), + stm32_getreg16(dev, STM32_GTIM_CCR3_OFFSET), + stm32_getreg16(dev, STM32_GTIM_CCR4_OFFSET) ); - if (priv->base == STM32L4_TIM1_BASE || priv->base == STM32L4_TIM8_BASE) + if (priv->base == STM32_TIM1_BASE || priv->base == STM32_TIM8_BASE) { ainfo(" RCR: %04x BDTR: %04x DCR: %04x DMAR: %04x\n", - stm32l4_getreg16(dev, STM32L4_ATIM_RCR_OFFSET), - stm32l4_getreg16(dev, STM32L4_ATIM_BDTR_OFFSET), - stm32l4_getreg16(dev, STM32L4_ATIM_DCR_OFFSET), - stm32l4_getreg16(dev, STM32L4_ATIM_DMAR_OFFSET)); + stm32_getreg16(dev, STM32_ATIM_RCR_OFFSET), + stm32_getreg16(dev, STM32_ATIM_BDTR_OFFSET), + stm32_getreg16(dev, STM32_ATIM_DCR_OFFSET), + stm32_getreg16(dev, STM32_ATIM_DMAR_OFFSET)); } else { ainfo(" DCR: %04x DMAR: %04x\n", - stm32l4_getreg16(dev, STM32L4_GTIM_DCR_OFFSET), - stm32l4_getreg16(dev, STM32L4_GTIM_DMAR_OFFSET)); + stm32_getreg16(dev, STM32_GTIM_DCR_OFFSET), + stm32_getreg16(dev, STM32_GTIM_DMAR_OFFSET)); } } /**************************************************************************** - * Name: stm32l4_tim_setmode + * Name: stm32_tim_setmode ****************************************************************************/ -static int stm32l4_tim_setmode(struct stm32l4_tim_dev_s *dev, - enum stm32l4_tim_mode_e mode) +static int stm32_tim_setmode(struct stm32_tim_dev_s *dev, + enum stm32_tim_mode_e mode) { uint16_t val = GTIM_CR1_CEN | GTIM_CR1_ARPE; @@ -621,13 +621,13 @@ static int stm32l4_tim_setmode(struct stm32l4_tim_dev_s *dev, * disable it, simply set its clock to valid frequency or zero. */ -#if STM32L4_NBTIM > 0 - if (((struct stm32l4_tim_priv_s *)dev)->base == STM32L4_TIM6_BASE +#if STM32_NBTIM > 0 + if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM6_BASE #endif -#if STM32L4_NBTIM > 1 - || ((struct stm32l4_tim_priv_s *)dev)->base == STM32L4_TIM7_BASE +#if STM32_NBTIM > 1 + || ((struct stm32_tim_priv_s *)dev)->base == STM32_TIM7_BASE #endif -#if STM32L4_NBTIM > 0 +#if STM32_NBTIM > 0 ) { return -EINVAL; @@ -636,21 +636,21 @@ static int stm32l4_tim_setmode(struct stm32l4_tim_dev_s *dev, /* Decode operational modes */ - switch (mode & STM32L4_TIM_MODE_MASK) + switch (mode & STM32_TIM_MODE_MASK) { - case STM32L4_TIM_MODE_DISABLED: + case STM32_TIM_MODE_DISABLED: val = 0; break; - case STM32L4_TIM_MODE_DOWN: + case STM32_TIM_MODE_DOWN: val |= GTIM_CR1_DIR; break; - case STM32L4_TIM_MODE_UP: + case STM32_TIM_MODE_UP: val &= ~GTIM_CR1_DIR; break; - case STM32L4_TIM_MODE_UPDOWN: + case STM32_TIM_MODE_UPDOWN: val |= GTIM_CR1_CENTER1; /* Our default: @@ -659,7 +659,7 @@ static int stm32l4_tim_setmode(struct stm32l4_tim_dev_s *dev, break; - case STM32L4_TIM_MODE_PULSE: + case STM32_TIM_MODE_PULSE: val |= GTIM_CR1_OPM; break; @@ -667,16 +667,16 @@ static int stm32l4_tim_setmode(struct stm32l4_tim_dev_s *dev, return -EINVAL; } - stm32l4_tim_reload_counter(dev); - stm32l4_putreg16(dev, STM32L4_GTIM_CR1_OFFSET, val); + stm32_tim_reload_counter(dev); + stm32_putreg16(dev, STM32_GTIM_CR1_OFFSET, val); -#if STM32L4_NATIM > 0 +#if STM32_NATIM > 0 /* Advanced registers require Main Output Enable */ - if (((struct stm32l4_tim_priv_s *)dev)->base == STM32L4_TIM1_BASE || - ((struct stm32l4_tim_priv_s *)dev)->base == STM32L4_TIM8_BASE) + if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM1_BASE || + ((struct stm32_tim_priv_s *)dev)->base == STM32_TIM8_BASE) { - stm32l4_modifyreg16(dev, STM32L4_ATIM_BDTR_OFFSET, 0, ATIM_BDTR_MOE); + stm32_modifyreg16(dev, STM32_ATIM_BDTR_OFFSET, 0, ATIM_BDTR_MOE); } #endif @@ -684,10 +684,10 @@ static int stm32l4_tim_setmode(struct stm32l4_tim_dev_s *dev, } /**************************************************************************** - * Name: stm32l4_tim_setfreq + * Name: stm32_tim_setfreq ****************************************************************************/ -static int stm32l4_tim_setfreq(struct stm32l4_tim_dev_s *dev, +static int stm32_tim_setfreq(struct stm32_tim_dev_s *dev, uint32_t freq) { uint32_t freqin; @@ -701,7 +701,7 @@ static int stm32l4_tim_setfreq(struct stm32l4_tim_dev_s *dev, if (freq == 0) { - stm32l4_tim_disable(dev); + stm32_tim_disable(dev); return 0; } @@ -711,69 +711,69 @@ static int stm32l4_tim_setfreq(struct stm32l4_tim_dev_s *dev, * must be defined in the board.h header file. */ - switch (((struct stm32l4_tim_priv_s *)dev)->base) + switch (((struct stm32_tim_priv_s *)dev)->base) { -#ifdef CONFIG_STM32L4_TIM1 - case STM32L4_TIM1_BASE: +#ifdef CONFIG_STM32_TIM1 + case STM32_TIM1_BASE: freqin = BOARD_TIM1_FREQUENCY; break; #endif -#ifdef CONFIG_STM32L4_TIM2 - case STM32L4_TIM2_BASE: +#ifdef CONFIG_STM32_TIM2 + case STM32_TIM2_BASE: freqin = BOARD_TIM2_FREQUENCY; break; #endif -#ifdef CONFIG_STM32L4_TIM3 - case STM32L4_TIM3_BASE: +#ifdef CONFIG_STM32_TIM3 + case STM32_TIM3_BASE: freqin = BOARD_TIM3_FREQUENCY; break; #endif -#ifdef CONFIG_STM32L4_TIM4 - case STM32L4_TIM4_BASE: +#ifdef CONFIG_STM32_TIM4 + case STM32_TIM4_BASE: freqin = BOARD_TIM4_FREQUENCY; break; #endif -#ifdef CONFIG_STM32L4_TIM5 - case STM32L4_TIM5_BASE: +#ifdef CONFIG_STM32_TIM5 + case STM32_TIM5_BASE: freqin = BOARD_TIM5_FREQUENCY; break; #endif -#ifdef CONFIG_STM32L4_TIM6 - case STM32L4_TIM6_BASE: +#ifdef CONFIG_STM32_TIM6 + case STM32_TIM6_BASE: freqin = BOARD_TIM6_FREQUENCY; break; #endif -#ifdef CONFIG_STM32L4_TIM7 - case STM32L4_TIM7_BASE: +#ifdef CONFIG_STM32_TIM7 + case STM32_TIM7_BASE: freqin = BOARD_TIM7_FREQUENCY; break; #endif -#ifdef CONFIG_STM32L4_TIM8 - case STM32L4_TIM8_BASE: +#ifdef CONFIG_STM32_TIM8 + case STM32_TIM8_BASE: freqin = BOARD_TIM8_FREQUENCY; break; #endif -#ifdef CONFIG_STM32L4_TIM15 - case STM32L4_TIM15_BASE: +#ifdef CONFIG_STM32_TIM15 + case STM32_TIM15_BASE: freqin = BOARD_TIM15_FREQUENCY; break; #endif -#ifdef CONFIG_STM32L4_TIM16 - case STM32L4_TIM16_BASE: +#ifdef CONFIG_STM32_TIM16 + case STM32_TIM16_BASE: freqin = BOARD_TIM16_FREQUENCY; break; #endif -#ifdef CONFIG_STM32L4_TIM17 - case STM32L4_TIM17_BASE: +#ifdef CONFIG_STM32_TIM17 + case STM32_TIM17_BASE: freqin = BOARD_TIM17_FREQUENCY; break; #endif @@ -838,17 +838,17 @@ static int stm32l4_tim_setfreq(struct stm32l4_tim_dev_s *dev, /* Set the reload and prescaler values */ - stm32l4_putreg16(dev, STM32L4_GTIM_PSC_OFFSET, prescaler - 1); - stm32l4_putreg16(dev, STM32L4_GTIM_ARR_OFFSET, reload); + stm32_putreg16(dev, STM32_GTIM_PSC_OFFSET, prescaler - 1); + stm32_putreg16(dev, STM32_GTIM_ARR_OFFSET, reload); return (timclk / reload); } /**************************************************************************** - * Name: stm32l4_tim_setclock + * Name: stm32_tim_setclock ****************************************************************************/ -static int stm32l4_tim_setclock(struct stm32l4_tim_dev_s *dev, +static int stm32_tim_setclock(struct stm32_tim_dev_s *dev, uint32_t freq) { uint32_t freqin; @@ -860,7 +860,7 @@ static int stm32l4_tim_setclock(struct stm32l4_tim_dev_s *dev, if (freq == 0) { - stm32l4_tim_disable(dev); + stm32_tim_disable(dev); return 0; } @@ -870,69 +870,69 @@ static int stm32l4_tim_setclock(struct stm32l4_tim_dev_s *dev, * must be defined in the board.h header file. */ - switch (((struct stm32l4_tim_priv_s *)dev)->base) + switch (((struct stm32_tim_priv_s *)dev)->base) { -#ifdef CONFIG_STM32L4_TIM1 - case STM32L4_TIM1_BASE: +#ifdef CONFIG_STM32_TIM1 + case STM32_TIM1_BASE: freqin = BOARD_TIM1_FREQUENCY; break; #endif -#ifdef CONFIG_STM32L4_TIM2 - case STM32L4_TIM2_BASE: +#ifdef CONFIG_STM32_TIM2 + case STM32_TIM2_BASE: freqin = BOARD_TIM2_FREQUENCY; break; #endif -#ifdef CONFIG_STM32L4_TIM3 - case STM32L4_TIM3_BASE: +#ifdef CONFIG_STM32_TIM3 + case STM32_TIM3_BASE: freqin = BOARD_TIM3_FREQUENCY; break; #endif -#ifdef CONFIG_STM32L4_TIM4 - case STM32L4_TIM4_BASE: +#ifdef CONFIG_STM32_TIM4 + case STM32_TIM4_BASE: freqin = BOARD_TIM4_FREQUENCY; break; #endif -#ifdef CONFIG_STM32L4_TIM5 - case STM32L4_TIM5_BASE: +#ifdef CONFIG_STM32_TIM5 + case STM32_TIM5_BASE: freqin = BOARD_TIM5_FREQUENCY; break; #endif -#ifdef CONFIG_STM32L4_TIM6 - case STM32L4_TIM6_BASE: +#ifdef CONFIG_STM32_TIM6 + case STM32_TIM6_BASE: freqin = BOARD_TIM6_FREQUENCY; break; #endif -#ifdef CONFIG_STM32L4_TIM7 - case STM32L4_TIM7_BASE: +#ifdef CONFIG_STM32_TIM7 + case STM32_TIM7_BASE: freqin = BOARD_TIM7_FREQUENCY; break; #endif -#ifdef CONFIG_STM32L4_TIM8 - case STM32L4_TIM8_BASE: +#ifdef CONFIG_STM32_TIM8 + case STM32_TIM8_BASE: freqin = BOARD_TIM8_FREQUENCY; break; #endif -#ifdef CONFIG_STM32L4_TIM15 - case STM32L4_TIM15_BASE: +#ifdef CONFIG_STM32_TIM15 + case STM32_TIM15_BASE: freqin = BOARD_TIM15_FREQUENCY; break; #endif -#ifdef CONFIG_STM32L4_TIM16 - case STM32L4_TIM16_BASE: +#ifdef CONFIG_STM32_TIM16 + case STM32_TIM16_BASE: freqin = BOARD_TIM16_FREQUENCY; break; #endif -#ifdef CONFIG_STM32L4_TIM17 - case STM32L4_TIM17_BASE: +#ifdef CONFIG_STM32_TIM17 + case STM32_TIM17_BASE: freqin = BOARD_TIM17_FREQUENCY; break; #endif @@ -963,16 +963,16 @@ static int stm32l4_tim_setclock(struct stm32l4_tim_dev_s *dev, prescaler = 0xffff; } - stm32l4_putreg16(dev, STM32L4_GTIM_PSC_OFFSET, prescaler); + stm32_putreg16(dev, STM32_GTIM_PSC_OFFSET, prescaler); return prescaler; } /**************************************************************************** - * Name: stm32l4_tim_getclock + * Name: stm32_tim_getclock ****************************************************************************/ -static uint32_t stm32l4_tim_getclock(struct stm32l4_tim_dev_s *dev) +static uint32_t stm32_tim_getclock(struct stm32_tim_dev_s *dev) { uint32_t freqin; uint32_t clock; @@ -984,67 +984,67 @@ static uint32_t stm32l4_tim_getclock(struct stm32l4_tim_dev_s *dev) * must be defined in the board.h header file. */ - switch (((struct stm32l4_tim_priv_s *)dev)->base) + switch (((struct stm32_tim_priv_s *)dev)->base) { -#ifdef CONFIG_STM32L4_TIM1 - case STM32L4_TIM1_BASE: +#ifdef CONFIG_STM32_TIM1 + case STM32_TIM1_BASE: freqin = BOARD_TIM1_FREQUENCY; break; #endif -#ifdef CONFIG_STM32L4_TIM2 - case STM32L4_TIM2_BASE: +#ifdef CONFIG_STM32_TIM2 + case STM32_TIM2_BASE: freqin = BOARD_TIM2_FREQUENCY; break; #endif -#ifdef CONFIG_STM32L4_TIM3 - case STM32L4_TIM3_BASE: +#ifdef CONFIG_STM32_TIM3 + case STM32_TIM3_BASE: freqin = BOARD_TIM3_FREQUENCY; break; #endif -#ifdef CONFIG_STM32L4_TIM4 - case STM32L4_TIM4_BASE: +#ifdef CONFIG_STM32_TIM4 + case STM32_TIM4_BASE: freqin = BOARD_TIM4_FREQUENCY; break; #endif -#ifdef CONFIG_STM32L4_TIM5 - case STM32L4_TIM5_BASE: +#ifdef CONFIG_STM32_TIM5 + case STM32_TIM5_BASE: freqin = BOARD_TIM5_FREQUENCY; break; #endif -#ifdef CONFIG_STM32L4_TIM6 - case STM32L4_TIM6_BASE: +#ifdef CONFIG_STM32_TIM6 + case STM32_TIM6_BASE: freqin = BOARD_TIM6_FREQUENCY; break; #endif -#ifdef CONFIG_STM32L4_TIM7 - case STM32L4_TIM7_BASE: +#ifdef CONFIG_STM32_TIM7 + case STM32_TIM7_BASE: freqin = BOARD_TIM7_FREQUENCY; break; #endif -#ifdef CONFIG_STM32L4_TIM8 - case STM32L4_TIM8_BASE: +#ifdef CONFIG_STM32_TIM8 + case STM32_TIM8_BASE: freqin = BOARD_TIM8_FREQUENCY; break; #endif -#ifdef CONFIG_STM32L4_TIM15 - case STM32L4_TIM15_BASE: +#ifdef CONFIG_STM32_TIM15 + case STM32_TIM15_BASE: freqin = BOARD_TIM15_FREQUENCY; break; #endif -#ifdef CONFIG_STM32L4_TIM16 - case STM32L4_TIM16_BASE: +#ifdef CONFIG_STM32_TIM16 + case STM32_TIM16_BASE: freqin = BOARD_TIM16_FREQUENCY; break; #endif -#ifdef CONFIG_STM32L4_TIM17 - case STM32L4_TIM17_BASE: +#ifdef CONFIG_STM32_TIM17 + case STM32_TIM17_BASE: freqin = BOARD_TIM17_FREQUENCY; break; #endif @@ -1054,52 +1054,52 @@ static uint32_t stm32l4_tim_getclock(struct stm32l4_tim_dev_s *dev) /* From chip datasheet, at page 1179. */ - clock = freqin / (stm32l4_getreg16(dev, STM32L4_GTIM_PSC_OFFSET) + 1); + clock = freqin / (stm32_getreg16(dev, STM32_GTIM_PSC_OFFSET) + 1); return clock; } /**************************************************************************** - * Name: stm32l4_tim_setperiod + * Name: stm32_tim_setperiod ****************************************************************************/ -static void stm32l4_tim_setperiod(struct stm32l4_tim_dev_s *dev, +static void stm32_tim_setperiod(struct stm32_tim_dev_s *dev, uint32_t period) { DEBUGASSERT(dev != NULL); - stm32l4_putreg32(dev, STM32L4_GTIM_ARR_OFFSET, period); + stm32_putreg32(dev, STM32_GTIM_ARR_OFFSET, period); } /**************************************************************************** - * Name: stm32l4_tim_getperiod + * Name: stm32_tim_getperiod ****************************************************************************/ -static uint32_t stm32l4_tim_getperiod (struct stm32l4_tim_dev_s *dev) +static uint32_t stm32_tim_getperiod (struct stm32_tim_dev_s *dev) { DEBUGASSERT(dev != NULL); - return stm32l4_getreg32 (dev, STM32L4_GTIM_ARR_OFFSET); + return stm32_getreg32 (dev, STM32_GTIM_ARR_OFFSET); } /**************************************************************************** - * Name: stm32l4_tim_getcounter + * Name: stm32_tim_getcounter ****************************************************************************/ -static uint32_t stm32l4_tim_getcounter(struct stm32l4_tim_dev_s *dev) +static uint32_t stm32_tim_getcounter(struct stm32_tim_dev_s *dev) { DEBUGASSERT(dev != NULL); - uint32_t counter = stm32l4_getreg32(dev, STM32L4_GTIM_CNT_OFFSET); + uint32_t counter = stm32_getreg32(dev, STM32_GTIM_CNT_OFFSET); /* In datasheet page 988, there is a useless bit named UIFCPY in TIMx_CNT. * reset it it result when not TIM2 or TIM5. */ -#if defined(CONFIG_STM32L4_TIM2) || defined(CONFIG_STM32L4_TIM5) - switch (((struct stm32l4_tim_priv_s *)dev)->base) +#if defined(CONFIG_STM32_TIM2) || defined(CONFIG_STM32_TIM5) + switch (((struct stm32_tim_priv_s *)dev)->base) { -#ifdef CONFIG_STM32L4_TIM2 - case STM32L4_TIM2_BASE: +#ifdef CONFIG_STM32_TIM2 + case STM32_TIM2_BASE: #endif -#ifdef CONFIG_STM32L4_TIM5 - case STM32L4_TIM5_BASE: +#ifdef CONFIG_STM32_TIM5 + case STM32_TIM5_BASE: #endif return counter; @@ -1112,18 +1112,18 @@ static uint32_t stm32l4_tim_getcounter(struct stm32l4_tim_dev_s *dev) } /**************************************************************************** - * Name: stm32l4_tim_setchannel + * Name: stm32_tim_setchannel ****************************************************************************/ -static int stm32l4_tim_setchannel(struct stm32l4_tim_dev_s *dev, +static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, uint8_t channel, - enum stm32l4_tim_channel_e mode) + enum stm32_tim_channel_e mode) { uint16_t ccmr_orig = 0; uint16_t ccmr_val = 0; uint16_t ccmr_mask = 0xff; uint16_t ccer_val; - uint8_t ccmr_offset = STM32L4_GTIM_CCMR1_OFFSET; + uint8_t ccmr_offset = STM32_GTIM_CCMR1_OFFSET; DEBUGASSERT(dev != NULL); @@ -1136,7 +1136,7 @@ static int stm32l4_tim_setchannel(struct stm32l4_tim_dev_s *dev, /* Assume that channel is disabled and polarity is active high */ - ccer_val = stm32l4_getreg16(dev, STM32L4_GTIM_CCER_OFFSET); + ccer_val = stm32_getreg16(dev, STM32_GTIM_CCER_OFFSET); ccer_val &= ~((GTIM_CCER_CC1P | GTIM_CCER_CC1E) << GTIM_CCER_CCXBASE(channel)); @@ -1144,13 +1144,13 @@ static int stm32l4_tim_setchannel(struct stm32l4_tim_dev_s *dev, * disable it, simply set its clock to valid frequency or zero. */ -#if STM32L4_NBTIM > 0 - if (((struct stm32l4_tim_priv_s *)dev)->base == STM32L4_TIM6_BASE +#if STM32_NBTIM > 0 + if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM6_BASE #endif -#if STM32L4_NBTIM > 1 - || ((struct stm32l4_tim_priv_s *)dev)->base == STM32L4_TIM7_BASE +#if STM32_NBTIM > 1 + || ((struct stm32_tim_priv_s *)dev)->base == STM32_TIM7_BASE #endif -#if STM32L4_NBTIM > 0 +#if STM32_NBTIM > 0 ) { return -EINVAL; @@ -1159,12 +1159,12 @@ static int stm32l4_tim_setchannel(struct stm32l4_tim_dev_s *dev, /* Decode configuration */ - switch (mode & STM32L4_TIM_CH_MODE_MASK) + switch (mode & STM32_TIM_CH_MODE_MASK) { - case STM32L4_TIM_CH_DISABLED: + case STM32_TIM_CH_DISABLED: break; - case STM32L4_TIM_CH_OUTPWM: + case STM32_TIM_CH_OUTPWM: ccmr_val = (GTIM_CCMR_MODE_PWM1 << GTIM_CCMR1_OC1M_SHIFT) + GTIM_CCMR1_OC1PE; ccer_val |= GTIM_CCER_CC1E << GTIM_CCER_CCXBASE(channel); @@ -1176,7 +1176,7 @@ static int stm32l4_tim_setchannel(struct stm32l4_tim_dev_s *dev, /* Set polarity */ - if (mode & STM32L4_TIM_CH_POLARITY_NEG) + if (mode & STM32_TIM_CH_POLARITY_NEG) { ccer_val |= GTIM_CCER_CC1P << GTIM_CCER_CCXBASE(channel); } @@ -1191,44 +1191,44 @@ static int stm32l4_tim_setchannel(struct stm32l4_tim_dev_s *dev, if (channel > 1) { - ccmr_offset = STM32L4_GTIM_CCMR2_OFFSET; + ccmr_offset = STM32_GTIM_CCMR2_OFFSET; } - ccmr_orig = stm32l4_getreg16(dev, ccmr_offset); + ccmr_orig = stm32_getreg16(dev, ccmr_offset); ccmr_orig &= ~ccmr_mask; ccmr_orig |= ccmr_val; - stm32l4_putreg16(dev, ccmr_offset, ccmr_orig); - stm32l4_putreg16(dev, STM32L4_GTIM_CCER_OFFSET, ccer_val); + stm32_putreg16(dev, ccmr_offset, ccmr_orig); + stm32_putreg16(dev, STM32_GTIM_CCER_OFFSET, ccer_val); /* set GPIO */ - switch (((struct stm32l4_tim_priv_s *)dev)->base) + switch (((struct stm32_tim_priv_s *)dev)->base) { -#ifdef CONFIG_STM32L4_TIM1 - case STM32L4_TIM1_BASE: +#ifdef CONFIG_STM32_TIM1 + case STM32_TIM1_BASE: switch (channel) { #if defined(GPIO_TIM1_CH1OUT) case 0: - stm32l4_tim_gpioconfig(GPIO_TIM1_CH1OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM1_CH1OUT, mode); break; #endif #if defined(GPIO_TIM1_CH2OUT) case 1: - stm32l4_tim_gpioconfig(GPIO_TIM1_CH2OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM1_CH2OUT, mode); break; #endif #if defined(GPIO_TIM1_CH3OUT) case 2: - stm32l4_tim_gpioconfig(GPIO_TIM1_CH3OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM1_CH3OUT, mode); break; #endif #if defined(GPIO_TIM1_CH4OUT) case 3: - stm32l4_tim_gpioconfig(GPIO_TIM1_CH4OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM1_CH4OUT, mode); break; #endif @@ -1237,31 +1237,31 @@ static int stm32l4_tim_setchannel(struct stm32l4_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32L4_TIM2 - case STM32L4_TIM2_BASE: +#ifdef CONFIG_STM32_TIM2 + case STM32_TIM2_BASE: switch (channel) { #if defined(GPIO_TIM2_CH1OUT) case 0: - stm32l4_tim_gpioconfig(GPIO_TIM2_CH1OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM2_CH1OUT, mode); break; #endif #if defined(GPIO_TIM2_CH2OUT) case 1: - stm32l4_tim_gpioconfig(GPIO_TIM2_CH2OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM2_CH2OUT, mode); break; #endif #if defined(GPIO_TIM2_CH3OUT) case 2: - stm32l4_tim_gpioconfig(GPIO_TIM2_CH3OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM2_CH3OUT, mode); break; #endif #if defined(GPIO_TIM2_CH4OUT) case 3: - stm32l4_tim_gpioconfig(GPIO_TIM2_CH4OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM2_CH4OUT, mode); break; #endif @@ -1270,31 +1270,31 @@ static int stm32l4_tim_setchannel(struct stm32l4_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32L4_TIM3 - case STM32L4_TIM3_BASE: +#ifdef CONFIG_STM32_TIM3 + case STM32_TIM3_BASE: switch (channel) { #if defined(GPIO_TIM3_CH1OUT) case 0: - stm32l4_tim_gpioconfig(GPIO_TIM3_CH1OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM3_CH1OUT, mode); break; #endif #if defined(GPIO_TIM3_CH2OUT) case 1: - stm32l4_tim_gpioconfig(GPIO_TIM3_CH2OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM3_CH2OUT, mode); break; #endif #if defined(GPIO_TIM3_CH3OUT) case 2: - stm32l4_tim_gpioconfig(GPIO_TIM3_CH3OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM3_CH3OUT, mode); break; #endif #if defined(GPIO_TIM3_CH4OUT) case 3: - stm32l4_tim_gpioconfig(GPIO_TIM3_CH4OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM3_CH4OUT, mode); break; #endif @@ -1303,30 +1303,30 @@ static int stm32l4_tim_setchannel(struct stm32l4_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32L4_TIM4 - case STM32L4_TIM4_BASE: +#ifdef CONFIG_STM32_TIM4 + case STM32_TIM4_BASE: switch (channel) { #if defined(GPIO_TIM4_CH1OUT) case 0: - stm32l4_tim_gpioconfig(GPIO_TIM4_CH1OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM4_CH1OUT, mode); break; #endif #if defined(GPIO_TIM4_CH2OUT) case 1: - stm32l4_tim_gpioconfig(GPIO_TIM4_CH2OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM4_CH2OUT, mode); break; #endif #if defined(GPIO_TIM4_CH3OUT) case 2: - stm32l4_tim_gpioconfig(GPIO_TIM4_CH3OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM4_CH3OUT, mode); break; #endif #if defined(GPIO_TIM4_CH4OUT) case 3: - stm32l4_tim_gpioconfig(GPIO_TIM4_CH4OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM4_CH4OUT, mode); break; #endif @@ -1335,31 +1335,31 @@ static int stm32l4_tim_setchannel(struct stm32l4_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32L4_TIM5 - case STM32L4_TIM5_BASE: +#ifdef CONFIG_STM32_TIM5 + case STM32_TIM5_BASE: switch (channel) { #if defined(GPIO_TIM5_CH1OUT) case 0: - stm32l4_tim_gpioconfig(GPIO_TIM5_CH1OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM5_CH1OUT, mode); break; #endif #if defined(GPIO_TIM5_CH2OUT) case 1: - stm32l4_tim_gpioconfig(GPIO_TIM5_CH2OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM5_CH2OUT, mode); break; #endif #if defined(GPIO_TIM5_CH3OUT) case 2: - stm32l4_tim_gpioconfig(GPIO_TIM5_CH3OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM5_CH3OUT, mode); break; #endif #if defined(GPIO_TIM5_CH4OUT) case 3: - stm32l4_tim_gpioconfig(GPIO_TIM5_CH4OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM5_CH4OUT, mode); break; #endif @@ -1368,31 +1368,31 @@ static int stm32l4_tim_setchannel(struct stm32l4_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32L4_TIM8 - case STM32L4_TIM8_BASE: +#ifdef CONFIG_STM32_TIM8 + case STM32_TIM8_BASE: switch (channel) { #if defined(GPIO_TIM8_CH1OUT) case 0: - stm32l4_tim_gpioconfig(GPIO_TIM8_CH1OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM8_CH1OUT, mode); break; #endif #if defined(GPIO_TIM8_CH2OUT) case 1: - stm32l4_tim_gpioconfig(GPIO_TIM8_CH2OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM8_CH2OUT, mode); break; #endif #if defined(GPIO_TIM8_CH3OUT) case 2: - stm32l4_tim_gpioconfig(GPIO_TIM8_CH3OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM8_CH3OUT, mode); break; #endif #if defined(GPIO_TIM8_CH4OUT) case 3: - stm32l4_tim_gpioconfig(GPIO_TIM8_CH4OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM8_CH4OUT, mode); break; #endif @@ -1401,31 +1401,31 @@ static int stm32l4_tim_setchannel(struct stm32l4_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32L4_TIM15 - case STM32L4_TIM15_BASE: +#ifdef CONFIG_STM32_TIM15 + case STM32_TIM15_BASE: switch (channel) { #if defined(GPIO_TIM15_CH1OUT) case 0: - stm32l4_tim_gpioconfig(GPIO_TIM15_CH1OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM15_CH1OUT, mode); break; #endif #if defined(GPIO_TIM15_CH2OUT) case 1: - stm32l4_tim_gpioconfig(GPIO_TIM15_CH2OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM15_CH2OUT, mode); break; #endif #if defined(GPIO_TIM15_CH3OUT) case 2: - stm32l4_tim_gpioconfig(GPIO_TIM15_CH3OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM15_CH3OUT, mode); break; #endif #if defined(GPIO_TIM15_CH4OUT) case 3: - stm32l4_tim_gpioconfig(GPIO_TIM15_CH4OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM15_CH4OUT, mode); break; #endif @@ -1434,31 +1434,31 @@ static int stm32l4_tim_setchannel(struct stm32l4_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32L4_TIM16 - case STM32L4_TIM16_BASE: +#ifdef CONFIG_STM32_TIM16 + case STM32_TIM16_BASE: switch (channel) { #if defined(GPIO_TIM16_CH1OUT) case 0: - stm32l4_tim_gpioconfig(GPIO_TIM16_CH1OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM16_CH1OUT, mode); break; #endif #if defined(GPIO_TIM16_CH2OUT) case 1: - stm32l4_tim_gpioconfig(GPIO_TIM16_CH2OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM16_CH2OUT, mode); break; #endif #if defined(GPIO_TIM16_CH3OUT) case 2: - stm32l4_tim_gpioconfig(GPIO_TIM16_CH3OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM16_CH3OUT, mode); break; #endif #if defined(GPIO_TIM16_CH4OUT) case 3: - stm32l4_tim_gpioconfig(GPIO_TIM16_CH4OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM16_CH4OUT, mode); break; #endif @@ -1467,31 +1467,31 @@ static int stm32l4_tim_setchannel(struct stm32l4_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32L4_TIM17 - case STM32L4_TIM17_BASE: +#ifdef CONFIG_STM32_TIM17 + case STM32_TIM17_BASE: switch (channel) { #if defined(GPIO_TIM17_CH1OUT) case 0: - stm32l4_tim_gpioconfig(GPIO_TIM17_CH1OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM17_CH1OUT, mode); break; #endif #if defined(GPIO_TIM17_CH2OUT) case 1: - stm32l4_tim_gpioconfig(GPIO_TIM17_CH2OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM17_CH2OUT, mode); break; #endif #if defined(GPIO_TIM17_CH3OUT) case 2: - stm32l4_tim_gpioconfig(GPIO_TIM17_CH3OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM17_CH3OUT, mode); break; #endif #if defined(GPIO_TIM17_CH4OUT) case 3: - stm32l4_tim_gpioconfig(GPIO_TIM17_CH4OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM17_CH4OUT, mode); break; #endif @@ -1509,10 +1509,10 @@ static int stm32l4_tim_setchannel(struct stm32l4_tim_dev_s *dev, } /**************************************************************************** - * Name: stm32l4_tim_setcompare + * Name: stm32_tim_setcompare ****************************************************************************/ -static int stm32l4_tim_setcompare(struct stm32l4_tim_dev_s *dev, +static int stm32_tim_setcompare(struct stm32_tim_dev_s *dev, uint8_t channel, uint32_t compare) { DEBUGASSERT(dev != NULL); @@ -1520,19 +1520,19 @@ static int stm32l4_tim_setcompare(struct stm32l4_tim_dev_s *dev, switch (channel) { case 1: - stm32l4_putreg32(dev, STM32L4_GTIM_CCR1_OFFSET, compare); + stm32_putreg32(dev, STM32_GTIM_CCR1_OFFSET, compare); break; case 2: - stm32l4_putreg32(dev, STM32L4_GTIM_CCR2_OFFSET, compare); + stm32_putreg32(dev, STM32_GTIM_CCR2_OFFSET, compare); break; case 3: - stm32l4_putreg32(dev, STM32L4_GTIM_CCR3_OFFSET, compare); + stm32_putreg32(dev, STM32_GTIM_CCR3_OFFSET, compare); break; case 4: - stm32l4_putreg32(dev, STM32L4_GTIM_CCR4_OFFSET, compare); + stm32_putreg32(dev, STM32_GTIM_CCR4_OFFSET, compare); break; default: @@ -1543,10 +1543,10 @@ static int stm32l4_tim_setcompare(struct stm32l4_tim_dev_s *dev, } /**************************************************************************** - * Name: stm32l4_tim_getcapture + * Name: stm32_tim_getcapture ****************************************************************************/ -static int stm32l4_tim_getcapture(struct stm32l4_tim_dev_s *dev, +static int stm32_tim_getcapture(struct stm32_tim_dev_s *dev, uint8_t channel) { DEBUGASSERT(dev != NULL); @@ -1554,26 +1554,26 @@ static int stm32l4_tim_getcapture(struct stm32l4_tim_dev_s *dev, switch (channel) { case 1: - return stm32l4_getreg32(dev, STM32L4_GTIM_CCR1_OFFSET); + return stm32_getreg32(dev, STM32_GTIM_CCR1_OFFSET); case 2: - return stm32l4_getreg32(dev, STM32L4_GTIM_CCR2_OFFSET); + return stm32_getreg32(dev, STM32_GTIM_CCR2_OFFSET); case 3: - return stm32l4_getreg32(dev, STM32L4_GTIM_CCR3_OFFSET); + return stm32_getreg32(dev, STM32_GTIM_CCR3_OFFSET); case 4: - return stm32l4_getreg32(dev, STM32L4_GTIM_CCR4_OFFSET); + return stm32_getreg32(dev, STM32_GTIM_CCR4_OFFSET); } return -EINVAL; } /**************************************************************************** - * Name: stm32l4_tim_setisr + * Name: stm32_tim_setisr ****************************************************************************/ -static int stm32l4_tim_setisr(struct stm32l4_tim_dev_s *dev, +static int stm32_tim_setisr(struct stm32_tim_dev_s *dev, xcpt_t handler, void *arg, int source) { int vectorno; @@ -1581,69 +1581,69 @@ static int stm32l4_tim_setisr(struct stm32l4_tim_dev_s *dev, DEBUGASSERT(dev != NULL); DEBUGASSERT(source == 0); - switch (((struct stm32l4_tim_priv_s *)dev)->base) + switch (((struct stm32_tim_priv_s *)dev)->base) { -#ifdef CONFIG_STM32L4_TIM1 - case STM32L4_TIM1_BASE: - vectorno = STM32L4_IRQ_TIM1UP; +#ifdef CONFIG_STM32_TIM1 + case STM32_TIM1_BASE: + vectorno = STM32_IRQ_TIM1UP; break; #endif -#ifdef CONFIG_STM32L4_TIM2 - case STM32L4_TIM2_BASE: - vectorno = STM32L4_IRQ_TIM2; +#ifdef CONFIG_STM32_TIM2 + case STM32_TIM2_BASE: + vectorno = STM32_IRQ_TIM2; break; #endif -#ifdef CONFIG_STM32L4_TIM3 - case STM32L4_TIM3_BASE: - vectorno = STM32L4_IRQ_TIM3; +#ifdef CONFIG_STM32_TIM3 + case STM32_TIM3_BASE: + vectorno = STM32_IRQ_TIM3; break; #endif -#ifdef CONFIG_STM32L4_TIM4 - case STM32L4_TIM4_BASE: - vectorno = STM32L4_IRQ_TIM4; +#ifdef CONFIG_STM32_TIM4 + case STM32_TIM4_BASE: + vectorno = STM32_IRQ_TIM4; break; #endif -#ifdef CONFIG_STM32L4_TIM5 - case STM32L4_TIM5_BASE: - vectorno = STM32L4_IRQ_TIM5; +#ifdef CONFIG_STM32_TIM5 + case STM32_TIM5_BASE: + vectorno = STM32_IRQ_TIM5; break; #endif -#ifdef CONFIG_STM32L4_TIM6 - case STM32L4_TIM6_BASE: - vectorno = STM32L4_IRQ_TIM6; +#ifdef CONFIG_STM32_TIM6 + case STM32_TIM6_BASE: + vectorno = STM32_IRQ_TIM6; break; #endif -#ifdef CONFIG_STM32L4_TIM7 - case STM32L4_TIM7_BASE: - vectorno = STM32L4_IRQ_TIM7; +#ifdef CONFIG_STM32_TIM7 + case STM32_TIM7_BASE: + vectorno = STM32_IRQ_TIM7; break; #endif -#ifdef CONFIG_STM32L4_TIM8 - case STM32L4_TIM8_BASE: - vectorno = STM32L4_IRQ_TIM8UP; +#ifdef CONFIG_STM32_TIM8 + case STM32_TIM8_BASE: + vectorno = STM32_IRQ_TIM8UP; break; #endif -#ifdef CONFIG_STM32L4_TIM15 - case STM32L4_TIM15_BASE: - vectorno = STM32L4_IRQ_TIM15; +#ifdef CONFIG_STM32_TIM15 + case STM32_TIM15_BASE: + vectorno = STM32_IRQ_TIM15; break; #endif -#ifdef CONFIG_STM32L4_TIM16 - case STM32L4_TIM16_BASE: - vectorno = STM32L4_IRQ_TIM16; +#ifdef CONFIG_STM32_TIM16 + case STM32_TIM16_BASE: + vectorno = STM32_IRQ_TIM16; break; #endif -#ifdef CONFIG_STM32L4_TIM17 - case STM32L4_TIM17_BASE: - vectorno = STM32L4_IRQ_TIM17; +#ifdef CONFIG_STM32_TIM17 + case STM32_TIM17_BASE: + vectorno = STM32_IRQ_TIM17; break; #endif @@ -1669,44 +1669,44 @@ static int stm32l4_tim_setisr(struct stm32l4_tim_dev_s *dev, } /**************************************************************************** - * Name: stm32l4_tim_enableint + * Name: stm32_tim_enableint ****************************************************************************/ -static void stm32l4_tim_enableint(struct stm32l4_tim_dev_s *dev, +static void stm32_tim_enableint(struct stm32_tim_dev_s *dev, int source) { DEBUGASSERT(dev != NULL); - stm32l4_modifyreg16(dev, STM32L4_GTIM_DIER_OFFSET, 0, GTIM_DIER_UIE); + stm32_modifyreg16(dev, STM32_GTIM_DIER_OFFSET, 0, GTIM_DIER_UIE); } /**************************************************************************** - * Name: stm32l4_tim_disableint + * Name: stm32_tim_disableint ****************************************************************************/ -static void stm32l4_tim_disableint(struct stm32l4_tim_dev_s *dev, +static void stm32_tim_disableint(struct stm32_tim_dev_s *dev, int source) { DEBUGASSERT(dev != NULL); - stm32l4_modifyreg16(dev, STM32L4_GTIM_DIER_OFFSET, GTIM_DIER_UIE, 0); + stm32_modifyreg16(dev, STM32_GTIM_DIER_OFFSET, GTIM_DIER_UIE, 0); } /**************************************************************************** - * Name: stm32l4_tim_ackint + * Name: stm32_tim_ackint ****************************************************************************/ -static void stm32l4_tim_ackint(struct stm32l4_tim_dev_s *dev, int source) +static void stm32_tim_ackint(struct stm32_tim_dev_s *dev, int source) { - stm32l4_putreg16(dev, STM32L4_GTIM_SR_OFFSET, ~GTIM_SR_UIF); + stm32_putreg16(dev, STM32_GTIM_SR_OFFSET, ~GTIM_SR_UIF); } /**************************************************************************** - * Name: stm32l4_tim_checkint + * Name: stm32_tim_checkint ****************************************************************************/ -static int stm32l4_tim_checkint(struct stm32l4_tim_dev_s *dev, +static int stm32_tim_checkint(struct stm32_tim_dev_s *dev, int source) { - uint16_t regval = stm32l4_getreg16(dev, STM32L4_GTIM_SR_OFFSET); + uint16_t regval = stm32_getreg16(dev, STM32_GTIM_SR_OFFSET); return (regval & GTIM_SR_UIF) ? 1 : 0; } @@ -1715,90 +1715,90 @@ static int stm32l4_tim_checkint(struct stm32l4_tim_dev_s *dev, ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_tim_init + * Name: stm32_tim_init ****************************************************************************/ -struct stm32l4_tim_dev_s *stm32l4_tim_init(int timer) +struct stm32_tim_dev_s *stm32_tim_init(int timer) { - struct stm32l4_tim_dev_s *dev = NULL; + struct stm32_tim_dev_s *dev = NULL; /* Get structure and enable power */ switch (timer) { -#ifdef CONFIG_STM32L4_TIM1 +#ifdef CONFIG_STM32_TIM1 case 1: - dev = (struct stm32l4_tim_dev_s *)&stm32l4_tim1_priv; - modifyreg32(STM32L4_RCC_APB2ENR, 0, RCC_APB2ENR_TIM1EN); + dev = (struct stm32_tim_dev_s *)&stm32_tim1_priv; + modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM1EN); break; #endif -#ifdef CONFIG_STM32L4_TIM2 +#ifdef CONFIG_STM32_TIM2 case 2: - dev = (struct stm32l4_tim_dev_s *)&stm32l4_tim2_priv; - modifyreg32(STM32L4_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM2EN); + dev = (struct stm32_tim_dev_s *)&stm32_tim2_priv; + modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM2EN); break; #endif -#ifdef CONFIG_STM32L4_TIM3 +#ifdef CONFIG_STM32_TIM3 case 3: - dev = (struct stm32l4_tim_dev_s *)&stm32l4_tim3_priv; - modifyreg32(STM32L4_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM3EN); + dev = (struct stm32_tim_dev_s *)&stm32_tim3_priv; + modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM3EN); break; #endif -#ifdef CONFIG_STM32L4_TIM4 +#ifdef CONFIG_STM32_TIM4 case 4: - dev = (struct stm32l4_tim_dev_s *)&stm32l4_tim4_priv; - modifyreg32(STM32L4_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM4EN); + dev = (struct stm32_tim_dev_s *)&stm32_tim4_priv; + modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM4EN); break; #endif -#ifdef CONFIG_STM32L4_TIM5 +#ifdef CONFIG_STM32_TIM5 case 5: - dev = (struct stm32l4_tim_dev_s *)&stm32l4_tim5_priv; - modifyreg32(STM32L4_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM5EN); + dev = (struct stm32_tim_dev_s *)&stm32_tim5_priv; + modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM5EN); break; #endif -#ifdef CONFIG_STM32L4_TIM6 +#ifdef CONFIG_STM32_TIM6 case 6: - dev = (struct stm32l4_tim_dev_s *)&stm32l4_tim6_priv; - modifyreg32(STM32L4_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM6EN); + dev = (struct stm32_tim_dev_s *)&stm32_tim6_priv; + modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM6EN); break; #endif -#ifdef CONFIG_STM32L4_TIM7 +#ifdef CONFIG_STM32_TIM7 case 7: - dev = (struct stm32l4_tim_dev_s *)&stm32l4_tim7_priv; - modifyreg32(STM32L4_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM7EN); + dev = (struct stm32_tim_dev_s *)&stm32_tim7_priv; + modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM7EN); break; #endif -#ifdef CONFIG_STM32L4_TIM8 +#ifdef CONFIG_STM32_TIM8 case 8: - dev = (struct stm32l4_tim_dev_s *)&stm32l4_tim8_priv; - modifyreg32(STM32L4_RCC_APB2ENR, 0, RCC_APB2ENR_TIM8EN); + dev = (struct stm32_tim_dev_s *)&stm32_tim8_priv; + modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM8EN); break; #endif -#ifdef CONFIG_STM32L4_TIM15 +#ifdef CONFIG_STM32_TIM15 case 15: - dev = (struct stm32l4_tim_dev_s *)&stm32l4_tim15_priv; - modifyreg32(STM32L4_RCC_APB2ENR, 0, RCC_APB2ENR_TIM15EN); + dev = (struct stm32_tim_dev_s *)&stm32_tim15_priv; + modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM15EN); break; #endif -#ifdef CONFIG_STM32L4_TIM16 +#ifdef CONFIG_STM32_TIM16 case 16: - dev = (struct stm32l4_tim_dev_s *)&stm32l4_tim16_priv; - modifyreg32(STM32L4_RCC_APB2ENR, 0, RCC_APB2ENR_TIM16EN); + dev = (struct stm32_tim_dev_s *)&stm32_tim16_priv; + modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM16EN); break; #endif -#ifdef CONFIG_STM32L4_TIM17 +#ifdef CONFIG_STM32_TIM17 case 17: - dev = (struct stm32l4_tim_dev_s *)&stm32l4_tim17_priv; - modifyreg32(STM32L4_RCC_APB2ENR, 0, RCC_APB2ENR_TIM17EN); + dev = (struct stm32_tim_dev_s *)&stm32_tim17_priv; + modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM17EN); break; #endif @@ -1808,93 +1808,93 @@ struct stm32l4_tim_dev_s *stm32l4_tim_init(int timer) /* Is device already allocated */ - if (((struct stm32l4_tim_priv_s *)dev)->mode != STM32L4_TIM_MODE_UNUSED) + if (((struct stm32_tim_priv_s *)dev)->mode != STM32_TIM_MODE_UNUSED) { return NULL; } - stm32l4_tim_reset(dev); + stm32_tim_reset(dev); return dev; } /**************************************************************************** - * Name: stm32l4_tim_deinit + * Name: stm32_tim_deinit * * TODO: Detach interrupts, and close down all TIM Channels * ****************************************************************************/ -int stm32l4_tim_deinit(struct stm32l4_tim_dev_s *dev) +int stm32_tim_deinit(struct stm32_tim_dev_s *dev) { DEBUGASSERT(dev != NULL); /* Disable power */ - switch (((struct stm32l4_tim_priv_s *)dev)->base) + switch (((struct stm32_tim_priv_s *)dev)->base) { -#ifdef CONFIG_STM32L4_TIM1 - case STM32L4_TIM1_BASE: - modifyreg32(STM32L4_RCC_APB2ENR, RCC_APB2ENR_TIM1EN, 0); +#ifdef CONFIG_STM32_TIM1 + case STM32_TIM1_BASE: + modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM1EN, 0); break; #endif -#ifdef CONFIG_STM32L4_TIM2 - case STM32L4_TIM2_BASE: - modifyreg32(STM32L4_RCC_APB1ENR1, RCC_APB1ENR1_TIM2EN, 0); +#ifdef CONFIG_STM32_TIM2 + case STM32_TIM2_BASE: + modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM2EN, 0); break; #endif -#ifdef CONFIG_STM32L4_TIM3 - case STM32L4_TIM3_BASE: - modifyreg32(STM32L4_RCC_APB1ENR1, RCC_APB1ENR1_TIM3EN, 0); +#ifdef CONFIG_STM32_TIM3 + case STM32_TIM3_BASE: + modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM3EN, 0); break; #endif -#ifdef CONFIG_STM32L4_TIM4 - case STM32L4_TIM4_BASE: - modifyreg32(STM32L4_RCC_APB1ENR1, RCC_APB1ENR1_TIM4EN, 0); +#ifdef CONFIG_STM32_TIM4 + case STM32_TIM4_BASE: + modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM4EN, 0); break; #endif -#ifdef CONFIG_STM32L4_TIM5 - case STM32L4_TIM5_BASE: - modifyreg32(STM32L4_RCC_APB1ENR1, RCC_APB1ENR1_TIM5EN, 0); +#ifdef CONFIG_STM32_TIM5 + case STM32_TIM5_BASE: + modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM5EN, 0); break; #endif -#ifdef CONFIG_STM32L4_TIM6 - case STM32L4_TIM6_BASE: - modifyreg32(STM32L4_RCC_APB1ENR1, RCC_APB1ENR1_TIM6EN, 0); +#ifdef CONFIG_STM32_TIM6 + case STM32_TIM6_BASE: + modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM6EN, 0); break; #endif -#ifdef CONFIG_STM32L4_TIM7 - case STM32L4_TIM7_BASE: - modifyreg32(STM32L4_RCC_APB1ENR1, RCC_APB1ENR1_TIM7EN, 0); +#ifdef CONFIG_STM32_TIM7 + case STM32_TIM7_BASE: + modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM7EN, 0); break; #endif -#ifdef CONFIG_STM32L4_TIM8 - case STM32L4_TIM8_BASE: - modifyreg32(STM32L4_RCC_APB2ENR, RCC_APB2ENR_TIM8EN, 0); +#ifdef CONFIG_STM32_TIM8 + case STM32_TIM8_BASE: + modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM8EN, 0); break; #endif -#ifdef CONFIG_STM32L4_TIM15 - case STM32L4_TIM15_BASE: - modifyreg32(STM32L4_RCC_APB2ENR, RCC_APB2ENR_TIM15EN, 0); +#ifdef CONFIG_STM32_TIM15 + case STM32_TIM15_BASE: + modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM15EN, 0); break; #endif -#ifdef CONFIG_STM32L4_TIM16 - case STM32L4_TIM16_BASE: - modifyreg32(STM32L4_RCC_APB2ENR, RCC_APB2ENR_TIM16EN, 0); +#ifdef CONFIG_STM32_TIM16 + case STM32_TIM16_BASE: + modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM16EN, 0); break; #endif -#ifdef CONFIG_STM32L4_TIM17 - case STM32L4_TIM17_BASE: - modifyreg32(STM32L4_RCC_APB2ENR, RCC_APB2ENR_TIM17EN, 0); +#ifdef CONFIG_STM32_TIM17 + case STM32_TIM17_BASE: + modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM17EN, 0); break; #endif @@ -1904,9 +1904,9 @@ int stm32l4_tim_deinit(struct stm32l4_tim_dev_s *dev) /* Mark it as free */ - ((struct stm32l4_tim_priv_s *)dev)->mode = STM32L4_TIM_MODE_UNUSED; + ((struct stm32_tim_priv_s *)dev)->mode = STM32_TIM_MODE_UNUSED; return OK; } -#endif /* defined(CONFIG_STM32L4_TIM1 || ... || TIM17) */ +#endif /* defined(CONFIG_STM32_TIM1 || ... || TIM17) */ diff --git a/arch/arm/src/stm32l4/stm32l4_tim.h b/arch/arm/src/stm32l4/stm32l4_tim.h index 06a800a351951..46cd7a6e2efa1 100644 --- a/arch/arm/src/stm32l4/stm32l4_tim.h +++ b/arch/arm/src/stm32l4/stm32l4_tim.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32L4_STM32L4_TIM_H -#define __ARCH_ARM_SRC_STM32L4_STM32L4_TIM_H +#ifndef __ARCH_ARM_SRC_STM32L4_STM32_TIM_H +#define __ARCH_ARM_SRC_STM32L4_STM32_TIM_H /**************************************************************************** * Included Files @@ -38,24 +38,24 @@ /* Helpers ******************************************************************/ -#define STM32L4_TIM_SETMODE(d,mode) ((d)->ops->setmode(d,mode)) -#define STM32L4_TIM_SETFREQ(d,freq) ((d)->ops->setfreq(d,freq)) -#define STM32L4_TIM_SETCLOCK(d,freq) ((d)->ops->setclock(d,freq)) -#define STM32L4_TIM_GETCLOCK(d) ((d)->ops->getclock(d)) -#define STM32L4_TIM_SETPERIOD(d,period) ((d)->ops->setperiod(d,period)) -#define STM32L4_TIM_GETPERIOD(d) ((d)->ops->getperiod(d)) -#define STM32L4_TIM_GETCOUNTER(d) ((d)->ops->getcounter(d)) -#define STM32L4_TIM_SETCHANNEL(d,ch,mode) ((d)->ops->setchannel(d,ch,mode)) -#define STM32L4_TIM_SETCOMPARE(d,ch,comp) ((d)->ops->setcompare(d,ch,comp)) -#define STM32L4_TIM_GETCAPTURE(d,ch) ((d)->ops->getcapture(d,ch)) -#define STM32L4_TIM_SETISR(d,hnd,arg,s) ((d)->ops->setisr(d,hnd,arg,s)) -#define STM32L4_TIM_ENABLEINT(d,s) ((d)->ops->enableint(d,s)) -#define STM32L4_TIM_DISABLEINT(d,s) ((d)->ops->disableint(d,s)) -#define STM32L4_TIM_ACKINT(d,s) ((d)->ops->ackint(d,s)) -#define STM32L4_TIM_CHECKINT(d,s) ((d)->ops->checkint(d,s)) -#define STM32L4_TIM_ENABLE(d) ((d)->ops->enable(d)) -#define STM32L4_TIM_DISABLE(d) ((d)->ops->disable(d)) -#define STM32L4_TIM_DUMPREGS(d) ((d)->ops->dump_regs(d)) +#define STM32_TIM_SETMODE(d,mode) ((d)->ops->setmode(d,mode)) +#define STM32_TIM_SETFREQ(d,freq) ((d)->ops->setfreq(d,freq)) +#define STM32_TIM_SETCLOCK(d,freq) ((d)->ops->setclock(d,freq)) +#define STM32_TIM_GETCLOCK(d) ((d)->ops->getclock(d)) +#define STM32_TIM_SETPERIOD(d,period) ((d)->ops->setperiod(d,period)) +#define STM32_TIM_GETPERIOD(d) ((d)->ops->getperiod(d)) +#define STM32_TIM_GETCOUNTER(d) ((d)->ops->getcounter(d)) +#define STM32_TIM_SETCHANNEL(d,ch,mode) ((d)->ops->setchannel(d,ch,mode)) +#define STM32_TIM_SETCOMPARE(d,ch,comp) ((d)->ops->setcompare(d,ch,comp)) +#define STM32_TIM_GETCAPTURE(d,ch) ((d)->ops->getcapture(d,ch)) +#define STM32_TIM_SETISR(d,hnd,arg,s) ((d)->ops->setisr(d,hnd,arg,s)) +#define STM32_TIM_ENABLEINT(d,s) ((d)->ops->enableint(d,s)) +#define STM32_TIM_DISABLEINT(d,s) ((d)->ops->disableint(d,s)) +#define STM32_TIM_ACKINT(d,s) ((d)->ops->ackint(d,s)) +#define STM32_TIM_CHECKINT(d,s) ((d)->ops->checkint(d,s)) +#define STM32_TIM_ENABLE(d) ((d)->ops->enable(d)) +#define STM32_TIM_DISABLE(d) ((d)->ops->disable(d)) +#define STM32_TIM_DUMPREGS(d) ((d)->ops->dump_regs(d)) /**************************************************************************** * Public Types @@ -74,43 +74,43 @@ extern "C" /* TIM Device Structure */ -struct stm32l4_tim_dev_s +struct stm32_tim_dev_s { - struct stm32l4_tim_ops_s *ops; + struct stm32_tim_ops_s *ops; }; /* TIM Modes of Operation */ -enum stm32l4_tim_mode_e +enum stm32_tim_mode_e { - STM32L4_TIM_MODE_UNUSED = -1, + STM32_TIM_MODE_UNUSED = -1, /* One of the following */ - STM32L4_TIM_MODE_MASK = 0x0310, - STM32L4_TIM_MODE_DISABLED = 0x0000, - STM32L4_TIM_MODE_UP = 0x0100, - STM32L4_TIM_MODE_DOWN = 0x0110, - STM32L4_TIM_MODE_UPDOWN = 0x0200, - STM32L4_TIM_MODE_PULSE = 0x0300, + STM32_TIM_MODE_MASK = 0x0310, + STM32_TIM_MODE_DISABLED = 0x0000, + STM32_TIM_MODE_UP = 0x0100, + STM32_TIM_MODE_DOWN = 0x0110, + STM32_TIM_MODE_UPDOWN = 0x0200, + STM32_TIM_MODE_PULSE = 0x0300, /* One of the following */ - STM32L4_TIM_MODE_CK_INT = 0x0000, + STM32_TIM_MODE_CK_INT = 0x0000, #if 0 - STM32L4_TIM_MODE_CK_INT_TRIG = 0x0400, - STM32L4_TIM_MODE_CK_EXT = 0x0800, - STM32L4_TIM_MODE_CK_EXT_TRIG = 0x0c00, + STM32_TIM_MODE_CK_INT_TRIG = 0x0400, + STM32_TIM_MODE_CK_EXT = 0x0800, + STM32_TIM_MODE_CK_EXT_TRIG = 0x0c00, #endif /* Clock sources, OR'ed with CK_EXT */ #if 0 - STM32L4_TIM_MODE_CK_CHINVALID = 0x0000, - STM32L4_TIM_MODE_CK_CH1 = 0x0001, - STM32L4_TIM_MODE_CK_CH2 = 0x0002, - STM32L4_TIM_MODE_CK_CH3 = 0x0003, - STM32L4_TIM_MODE_CK_CH4 = 0x0004 + STM32_TIM_MODE_CK_CHINVALID = 0x0000, + STM32_TIM_MODE_CK_CH1 = 0x0001, + STM32_TIM_MODE_CK_CH2 = 0x0002, + STM32_TIM_MODE_CK_CH3 = 0x0003, + STM32_TIM_MODE_CK_CH4 = 0x0004 #endif /* Todo: external trigger block */ @@ -118,74 +118,74 @@ enum stm32l4_tim_mode_e /* TIM Channel Modes */ -enum stm32l4_tim_channel_e +enum stm32_tim_channel_e { - STM32L4_TIM_CH_DISABLED = 0x00, + STM32_TIM_CH_DISABLED = 0x00, /* Common configuration */ - STM32L4_TIM_CH_POLARITY_POS = 0x00, - STM32L4_TIM_CH_POLARITY_NEG = 0x01, + STM32_TIM_CH_POLARITY_POS = 0x00, + STM32_TIM_CH_POLARITY_NEG = 0x01, /* MODES: */ - STM32L4_TIM_CH_MODE_MASK = 0x06, + STM32_TIM_CH_MODE_MASK = 0x06, /* Output Compare Modes */ - STM32L4_TIM_CH_OUTPWM = 0x04, /* Enable standard PWM mode, active + STM32_TIM_CH_OUTPWM = 0x04, /* Enable standard PWM mode, active * high when counter < compare */ #if 0 - STM32L4_TIM_CH_OUTCOMPARE = 0x06, + STM32_TIM_CH_OUTCOMPARE = 0x06, #endif /* TODO other modes ... as PWM capture, ENCODER and Hall Sensor */ #if 0 - STM32L4_TIM_CH_INCAPTURE = 0x10, - STM32L4_TIM_CH_INPWM = 0x20 - STM32L4_TIM_CH_DRIVE_OC = open collector mode + STM32_TIM_CH_INCAPTURE = 0x10, + STM32_TIM_CH_INPWM = 0x20 + STM32_TIM_CH_DRIVE_OC = open collector mode #endif }; /* TIM Operations */ -struct stm32l4_tim_ops_s +struct stm32_tim_ops_s { /* Basic Timers */ - void (*enable)(struct stm32l4_tim_dev_s *dev); - void (*disable)(struct stm32l4_tim_dev_s *dev); - int (*setmode)(struct stm32l4_tim_dev_s *dev, - enum stm32l4_tim_mode_e mode); - int (*setfreq)(struct stm32l4_tim_dev_s *dev, uint32_t freq); - int (*setclock)(struct stm32l4_tim_dev_s *dev, uint32_t freq); - uint32_t (*getclock)(struct stm32l4_tim_dev_s *dev); - void (*setperiod)(struct stm32l4_tim_dev_s *dev, uint32_t period); - uint32_t (*getperiod)(struct stm32l4_tim_dev_s *dev); - uint32_t (*getcounter)(struct stm32l4_tim_dev_s *dev); + void (*enable)(struct stm32_tim_dev_s *dev); + void (*disable)(struct stm32_tim_dev_s *dev); + int (*setmode)(struct stm32_tim_dev_s *dev, + enum stm32_tim_mode_e mode); + int (*setfreq)(struct stm32_tim_dev_s *dev, uint32_t freq); + int (*setclock)(struct stm32_tim_dev_s *dev, uint32_t freq); + uint32_t (*getclock)(struct stm32_tim_dev_s *dev); + void (*setperiod)(struct stm32_tim_dev_s *dev, uint32_t period); + uint32_t (*getperiod)(struct stm32_tim_dev_s *dev); + uint32_t (*getcounter)(struct stm32_tim_dev_s *dev); /* General and Advanced Timers Adds */ - int (*setchannel)(struct stm32l4_tim_dev_s *dev, uint8_t channel, - enum stm32l4_tim_channel_e mode); - int (*setcompare)(struct stm32l4_tim_dev_s *dev, uint8_t channel, + int (*setchannel)(struct stm32_tim_dev_s *dev, uint8_t channel, + enum stm32_tim_channel_e mode); + int (*setcompare)(struct stm32_tim_dev_s *dev, uint8_t channel, uint32_t compare); - int (*getcapture)(struct stm32l4_tim_dev_s *dev, uint8_t channel); + int (*getcapture)(struct stm32_tim_dev_s *dev, uint8_t channel); /* Timer interrupts */ - int (*setisr)(struct stm32l4_tim_dev_s *dev, + int (*setisr)(struct stm32_tim_dev_s *dev, xcpt_t handler, void *arg, int source); - void (*enableint)(struct stm32l4_tim_dev_s *dev, int source); - void (*disableint)(struct stm32l4_tim_dev_s *dev, int source); - void (*ackint)(struct stm32l4_tim_dev_s *dev, int source); - int (*checkint)(struct stm32l4_tim_dev_s *dev, int source); + void (*enableint)(struct stm32_tim_dev_s *dev, int source); + void (*disableint)(struct stm32_tim_dev_s *dev, int source); + void (*ackint)(struct stm32_tim_dev_s *dev, int source); + int (*checkint)(struct stm32_tim_dev_s *dev, int source); /* Debug */ - void (*dump_regs)(struct stm32l4_tim_dev_s *dev); + void (*dump_regs)(struct stm32_tim_dev_s *dev); }; /**************************************************************************** @@ -194,14 +194,14 @@ struct stm32l4_tim_ops_s /* Power-up timer and get its structure */ -struct stm32l4_tim_dev_s *stm32l4_tim_init(int timer); +struct stm32_tim_dev_s *stm32_tim_init(int timer); /* Power-down timer, mark it as unused */ -int stm32l4_tim_deinit(struct stm32l4_tim_dev_s *dev); +int stm32_tim_deinit(struct stm32_tim_dev_s *dev); /**************************************************************************** - * Name: stm32l4_timer_initialize + * Name: stm32_timer_initialize * * Description: * Bind the configuration timer to a timer lower half instance and @@ -219,7 +219,7 @@ int stm32l4_tim_deinit(struct stm32l4_tim_dev_s *dev); ****************************************************************************/ #ifdef CONFIG_TIMER -int stm32l4_timer_initialize(const char *devpath, int timer); +int stm32_timer_initialize(const char *devpath, int timer); #endif #undef EXTERN @@ -228,4 +228,4 @@ int stm32l4_timer_initialize(const char *devpath, int timer); #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32L4_STM32L4_TIM_H */ +#endif /* __ARCH_ARM_SRC_STM32L4_STM32_TIM_H */ diff --git a/arch/arm/src/stm32l4/stm32l4_tim_lowerhalf.c b/arch/arm/src/stm32l4/stm32l4_tim_lowerhalf.c index 0f2d6376b29e5..1c60f9abcf5e6 100644 --- a/arch/arm/src/stm32l4/stm32l4_tim_lowerhalf.c +++ b/arch/arm/src/stm32l4/stm32l4_tim_lowerhalf.c @@ -60,28 +60,28 @@ #include "stm32l4_tim.h" #if defined(CONFIG_TIMER) && \ - (defined(CONFIG_STM32L4_TIM1) || defined(CONFIG_STM32L4_TIM2) || \ - defined(CONFIG_STM32L4_TIM3) || defined(CONFIG_STM32L4_TIM4) || \ - defined(CONFIG_STM32L4_TIM5) || defined(CONFIG_STM32L4_TIM6) || \ - defined(CONFIG_STM32L4_TIM7) || defined(CONFIG_STM32L4_TIM8) || \ - defined(CONFIG_STM32L4_TIM15) || defined(CONFIG_STM32L4_TIM16) || \ - defined(CONFIG_STM32L4_TIM17)) + (defined(CONFIG_STM32_TIM1) || defined(CONFIG_STM32_TIM2) || \ + defined(CONFIG_STM32_TIM3) || defined(CONFIG_STM32_TIM4) || \ + defined(CONFIG_STM32_TIM5) || defined(CONFIG_STM32_TIM6) || \ + defined(CONFIG_STM32_TIM7) || defined(CONFIG_STM32_TIM8) || \ + defined(CONFIG_STM32_TIM15) || defined(CONFIG_STM32_TIM16) || \ + defined(CONFIG_STM32_TIM17)) /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ -#define STM32L4_TIM1_RES 16 -#define STM32L4_TIM2_RES 32 -#define STM32L4_TIM3_RES 16 -#define STM32L4_TIM4_RES 16 -#define STM32L4_TIM5_RES 32 -#define STM32L4_TIM6_RES 16 -#define STM32L4_TIM7_RES 16 -#define STM32L4_TIM8_RES 16 -#define STM32L4_TIM15_RES 16 -#define STM32L4_TIM16_RES 16 -#define STM32L4_TIM17_RES 16 +#define STM32_TIM1_RES 16 +#define STM32_TIM2_RES 32 +#define STM32_TIM3_RES 16 +#define STM32_TIM4_RES 16 +#define STM32_TIM5_RES 32 +#define STM32_TIM6_RES 16 +#define STM32_TIM7_RES 16 +#define STM32_TIM8_RES 16 +#define STM32_TIM15_RES 16 +#define STM32_TIM16_RES 16 +#define STM32_TIM17_RES 16 /**************************************************************************** * Private Types @@ -92,10 +92,10 @@ * timer_lowerhalf_s structure. */ -struct stm32l4_lowerhalf_s +struct stm32_lowerhalf_s { const struct timer_ops_s *ops; /* Lower half operations */ - struct stm32l4_tim_dev_s *tim; /* stm32 timer driver */ + struct stm32_tim_dev_s *tim; /* stm32 timer driver */ tccb_t callback; /* Current upper half interrupt callback */ void *arg; /* Argument passed to upper half callback */ bool started; /* True: Timer has been started */ @@ -108,17 +108,17 @@ struct stm32l4_lowerhalf_s /* Interrupt handling *******************************************************/ -static int stm32l4_timer_handler(int irq, void *context, void *arg); +static int stm32_timer_handler(int irq, void *context, void *arg); /* "Lower half" driver methods **********************************************/ -static int stm32l4_start(struct timer_lowerhalf_s *lower); -static int stm32l4_stop(struct timer_lowerhalf_s *lower); -static int stm32l4_getstatus(struct timer_lowerhalf_s *lower, +static int stm32_start(struct timer_lowerhalf_s *lower); +static int stm32_stop(struct timer_lowerhalf_s *lower); +static int stm32_getstatus(struct timer_lowerhalf_s *lower, struct timer_status_s *status); -static int stm32l4_settimeout(struct timer_lowerhalf_s *lower, +static int stm32_settimeout(struct timer_lowerhalf_s *lower, uint32_t timeout); -static void stm32l4_setcallback(struct timer_lowerhalf_s *lower, +static void stm32_setcallback(struct timer_lowerhalf_s *lower, tccb_t callback, void *arg); /**************************************************************************** @@ -129,99 +129,99 @@ static void stm32l4_setcallback(struct timer_lowerhalf_s *lower, static const struct timer_ops_s g_timer_ops = { - .start = stm32l4_start, - .stop = stm32l4_stop, - .getstatus = stm32l4_getstatus, - .settimeout = stm32l4_settimeout, - .setcallback = stm32l4_setcallback, + .start = stm32_start, + .stop = stm32_stop, + .getstatus = stm32_getstatus, + .settimeout = stm32_settimeout, + .setcallback = stm32_setcallback, .ioctl = NULL, }; -#ifdef CONFIG_STM32L4_TIM1 -static struct stm32l4_lowerhalf_s g_tim1_lowerhalf = +#ifdef CONFIG_STM32_TIM1 +static struct stm32_lowerhalf_s g_tim1_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32L4_TIM1_RES, + .resolution = STM32_TIM1_RES, }; #endif -#ifdef CONFIG_STM32L4_TIM2 -static struct stm32l4_lowerhalf_s g_tim2_lowerhalf = +#ifdef CONFIG_STM32_TIM2 +static struct stm32_lowerhalf_s g_tim2_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32L4_TIM2_RES, + .resolution = STM32_TIM2_RES, }; #endif -#ifdef CONFIG_STM32L4_TIM3 -static struct stm32l4_lowerhalf_s g_tim3_lowerhalf = +#ifdef CONFIG_STM32_TIM3 +static struct stm32_lowerhalf_s g_tim3_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32L4_TIM3_RES, + .resolution = STM32_TIM3_RES, }; #endif -#ifdef CONFIG_STM32L4_TIM4 -static struct stm32l4_lowerhalf_s g_tim4_lowerhalf = +#ifdef CONFIG_STM32_TIM4 +static struct stm32_lowerhalf_s g_tim4_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32L4_TIM4_RES, + .resolution = STM32_TIM4_RES, }; #endif -#ifdef CONFIG_STM32L4_TIM5 -static struct stm32l4_lowerhalf_s g_tim5_lowerhalf = +#ifdef CONFIG_STM32_TIM5 +static struct stm32_lowerhalf_s g_tim5_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32L4_TIM5_RES, + .resolution = STM32_TIM5_RES, }; #endif -#ifdef CONFIG_STM32L4_TIM6 -static struct stm32l4_lowerhalf_s g_tim6_lowerhalf = +#ifdef CONFIG_STM32_TIM6 +static struct stm32_lowerhalf_s g_tim6_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32L4_TIM6_RES, + .resolution = STM32_TIM6_RES, }; #endif -#ifdef CONFIG_STM32L4_TIM7 -static struct stm32l4_lowerhalf_s g_tim7_lowerhalf = +#ifdef CONFIG_STM32_TIM7 +static struct stm32_lowerhalf_s g_tim7_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32L4_TIM7_RES, + .resolution = STM32_TIM7_RES, }; #endif -#ifdef CONFIG_STM32L4_TIM8 -static struct stm32l4_lowerhalf_s g_tim8_lowerhalf = +#ifdef CONFIG_STM32_TIM8 +static struct stm32_lowerhalf_s g_tim8_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32L4_TIM8_RES, + .resolution = STM32_TIM8_RES, }; #endif -#ifdef CONFIG_STM32L4_TIM15 -static struct stm32l4_lowerhalf_s g_tim15_lowerhalf = +#ifdef CONFIG_STM32_TIM15 +static struct stm32_lowerhalf_s g_tim15_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32L4_TIM15_RES, + .resolution = STM32_TIM15_RES, }; #endif -#ifdef CONFIG_STM32L4_TIM16 -static struct stm32l4_lowerhalf_s g_tim16_lowerhalf = +#ifdef CONFIG_STM32_TIM16 +static struct stm32_lowerhalf_s g_tim16_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32L4_TIM16_RES, + .resolution = STM32_TIM16_RES, }; #endif -#ifdef CONFIG_STM32L4_TIM17 -static struct stm32l4_lowerhalf_s g_tim17_lowerhalf = +#ifdef CONFIG_STM32_TIM17 +static struct stm32_lowerhalf_s g_tim17_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32L4_TIM17_RES, + .resolution = STM32_TIM17_RES, }; #endif @@ -230,7 +230,7 @@ static struct stm32l4_lowerhalf_s g_tim17_lowerhalf = ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_timer_handler + * Name: stm32_timer_handler * * Description: * timer interrupt handler @@ -241,31 +241,31 @@ static struct stm32l4_lowerhalf_s g_tim17_lowerhalf = * ****************************************************************************/ -static int stm32l4_timer_handler(int irq, void *context, void *arg) +static int stm32_timer_handler(int irq, void *context, void *arg) { - struct stm32l4_lowerhalf_s *lower = - (struct stm32l4_lowerhalf_s *) arg; + struct stm32_lowerhalf_s *lower = + (struct stm32_lowerhalf_s *) arg; uint32_t next_interval_us = 0; - STM32L4_TIM_ACKINT(lower->tim, 0); + STM32_TIM_ACKINT(lower->tim, 0); if (lower->callback(&next_interval_us, lower->arg)) { if (next_interval_us > 0) { - STM32L4_TIM_SETPERIOD(lower->tim, next_interval_us); + STM32_TIM_SETPERIOD(lower->tim, next_interval_us); } } else { - stm32l4_stop((struct timer_lowerhalf_s *)lower); + stm32_stop((struct timer_lowerhalf_s *)lower); } return OK; } /**************************************************************************** - * Name: stm32l4_start + * Name: stm32_start * * Description: * Start the timer, resetting the time to the current timeout, @@ -279,19 +279,19 @@ static int stm32l4_timer_handler(int irq, void *context, void *arg) * ****************************************************************************/ -static int stm32l4_start(struct timer_lowerhalf_s *lower) +static int stm32_start(struct timer_lowerhalf_s *lower) { - struct stm32l4_lowerhalf_s *priv = - (struct stm32l4_lowerhalf_s *)lower; + struct stm32_lowerhalf_s *priv = + (struct stm32_lowerhalf_s *)lower; if (!priv->started) { - STM32L4_TIM_SETMODE(priv->tim, STM32L4_TIM_MODE_UP); + STM32_TIM_SETMODE(priv->tim, STM32_TIM_MODE_UP); if (priv->callback != NULL) { - STM32L4_TIM_SETISR(priv->tim, stm32l4_timer_handler, priv, 0); - STM32L4_TIM_ENABLEINT(priv->tim, 0); + STM32_TIM_SETISR(priv->tim, stm32_timer_handler, priv, 0); + STM32_TIM_ENABLEINT(priv->tim, 0); } priv->started = true; @@ -304,7 +304,7 @@ static int stm32l4_start(struct timer_lowerhalf_s *lower) } /**************************************************************************** - * Name: stm32l4_stop + * Name: stm32_stop * * Description: * Stop the timer @@ -318,16 +318,16 @@ static int stm32l4_start(struct timer_lowerhalf_s *lower) * ****************************************************************************/ -static int stm32l4_stop(struct timer_lowerhalf_s *lower) +static int stm32_stop(struct timer_lowerhalf_s *lower) { - struct stm32l4_lowerhalf_s *priv = - (struct stm32l4_lowerhalf_s *)lower; + struct stm32_lowerhalf_s *priv = + (struct stm32_lowerhalf_s *)lower; if (priv->started) { - STM32L4_TIM_SETMODE(priv->tim, STM32L4_TIM_MODE_DISABLED); - STM32L4_TIM_DISABLEINT(priv->tim, 0); - STM32L4_TIM_SETISR(priv->tim, NULL, NULL, 0); + STM32_TIM_SETMODE(priv->tim, STM32_TIM_MODE_DISABLED); + STM32_TIM_DISABLEINT(priv->tim, 0); + STM32_TIM_SETISR(priv->tim, NULL, NULL, 0); priv->started = false; return OK; } @@ -338,7 +338,7 @@ static int stm32l4_stop(struct timer_lowerhalf_s *lower) } /**************************************************************************** - * Name: stm32l4_getstatus + * Name: stm32_getstatus * * Description: * get timer status @@ -353,11 +353,11 @@ static int stm32l4_stop(struct timer_lowerhalf_s *lower) * ****************************************************************************/ -static int stm32l4_getstatus(struct timer_lowerhalf_s *lower, +static int stm32_getstatus(struct timer_lowerhalf_s *lower, struct timer_status_s *status) { - struct stm32l4_lowerhalf_s *priv = - (struct stm32l4_lowerhalf_s *)lower; + struct stm32_lowerhalf_s *priv = + (struct stm32_lowerhalf_s *)lower; uint64_t maxtimeout; uint32_t timeout; uint32_t clock; @@ -382,8 +382,8 @@ static int stm32l4_getstatus(struct timer_lowerhalf_s *lower, /* Get timeout */ maxtimeout = (1 << priv->resolution) - 1; - clock = STM32L4_TIM_GETCLOCK(priv->tim); - period = STM32L4_TIM_GETPERIOD(priv->tim); + clock = STM32_TIM_GETCLOCK(priv->tim); + period = STM32_TIM_GETPERIOD(priv->tim); if (clock == 1000000) { @@ -399,13 +399,13 @@ static int stm32l4_getstatus(struct timer_lowerhalf_s *lower, /* Get the time remaining until the timer expires (in microseconds) */ clock_factor = (clock == 1000000) ? 1 : (clock / 1000000); - status->timeleft = (timeout - STM32L4_TIM_GETCOUNTER(priv->tim)) * + status->timeleft = (timeout - STM32_TIM_GETCOUNTER(priv->tim)) * clock_factor; return OK; } /**************************************************************************** - * Name: stm32l4_settimeout + * Name: stm32_settimeout * * Description: * Set a new timeout value (and reset the timer) @@ -420,11 +420,11 @@ static int stm32l4_getstatus(struct timer_lowerhalf_s *lower, * ****************************************************************************/ -static int stm32l4_settimeout(struct timer_lowerhalf_s *lower, +static int stm32_settimeout(struct timer_lowerhalf_s *lower, uint32_t timeout) { - struct stm32l4_lowerhalf_s *priv = - (struct stm32l4_lowerhalf_s *)lower; + struct stm32_lowerhalf_s *priv = + (struct stm32_lowerhalf_s *)lower; uint64_t maxtimeout; if (priv->started) @@ -436,20 +436,20 @@ static int stm32l4_settimeout(struct timer_lowerhalf_s *lower, if (timeout > maxtimeout) { uint64_t freq = (maxtimeout * 1000000) / timeout; - STM32L4_TIM_SETCLOCK(priv->tim, freq); - STM32L4_TIM_SETPERIOD(priv->tim, maxtimeout); + STM32_TIM_SETCLOCK(priv->tim, freq); + STM32_TIM_SETPERIOD(priv->tim, maxtimeout); } else { - STM32L4_TIM_SETCLOCK(priv->tim, 1000000); - STM32L4_TIM_SETPERIOD(priv->tim, timeout); + STM32_TIM_SETCLOCK(priv->tim, 1000000); + STM32_TIM_SETPERIOD(priv->tim, timeout); } return OK; } /**************************************************************************** - * Name: stm32l4_sethandler + * Name: stm32_sethandler * * Description: * Call this user provided timeout handler. @@ -468,11 +468,11 @@ static int stm32l4_settimeout(struct timer_lowerhalf_s *lower, * ****************************************************************************/ -static void stm32l4_setcallback(struct timer_lowerhalf_s *lower, +static void stm32_setcallback(struct timer_lowerhalf_s *lower, tccb_t callback, void *arg) { - struct stm32l4_lowerhalf_s *priv = - (struct stm32l4_lowerhalf_s *)lower; + struct stm32_lowerhalf_s *priv = + (struct stm32_lowerhalf_s *)lower; irqstate_t flags = enter_critical_section(); /* Save the new callback */ @@ -482,13 +482,13 @@ static void stm32l4_setcallback(struct timer_lowerhalf_s *lower, if (callback != NULL && priv->started) { - STM32L4_TIM_SETISR(priv->tim, stm32l4_timer_handler, priv, 0); - STM32L4_TIM_ENABLEINT(priv->tim, 0); + STM32_TIM_SETISR(priv->tim, stm32_timer_handler, priv, 0); + STM32_TIM_ENABLEINT(priv->tim, 0); } else { - STM32L4_TIM_DISABLEINT(priv->tim, 0); - STM32L4_TIM_SETISR(priv->tim, NULL, NULL, 0); + STM32_TIM_DISABLEINT(priv->tim, 0); + STM32_TIM_SETISR(priv->tim, NULL, NULL, 0); } leave_critical_section(flags); @@ -499,7 +499,7 @@ static void stm32l4_setcallback(struct timer_lowerhalf_s *lower, ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_timer_initialize + * Name: stm32_timer_initialize * * Description: * Bind the configuration timer to a timer lower half instance and @@ -516,72 +516,72 @@ static void stm32l4_setcallback(struct timer_lowerhalf_s *lower, * ****************************************************************************/ -int stm32l4_timer_initialize(const char *devpath, int timer) +int stm32_timer_initialize(const char *devpath, int timer) { - struct stm32l4_lowerhalf_s *lower; + struct stm32_lowerhalf_s *lower; switch (timer) { -#ifdef CONFIG_STM32L4_TIM1 +#ifdef CONFIG_STM32_TIM1 case 1: lower = &g_tim1_lowerhalf; break; #endif -#ifdef CONFIG_STM32L4_TIM2 +#ifdef CONFIG_STM32_TIM2 case 2: lower = &g_tim2_lowerhalf; break; #endif -#ifdef CONFIG_STM32L4_TIM3 +#ifdef CONFIG_STM32_TIM3 case 3: lower = &g_tim3_lowerhalf; break; #endif -#ifdef CONFIG_STM32L4_TIM4 +#ifdef CONFIG_STM32_TIM4 case 4: lower = &g_tim4_lowerhalf; break; #endif -#ifdef CONFIG_STM32L4_TIM5 +#ifdef CONFIG_STM32_TIM5 case 5: lower = &g_tim5_lowerhalf; break; #endif -#ifdef CONFIG_STM32L4_TIM6 +#ifdef CONFIG_STM32_TIM6 case 6: lower = &g_tim6_lowerhalf; break; #endif -#ifdef CONFIG_STM32L4_TIM7 +#ifdef CONFIG_STM32_TIM7 case 7: lower = &g_tim7_lowerhalf; break; #endif -#ifdef CONFIG_STM32L4_TIM8 +#ifdef CONFIG_STM32_TIM8 case 8: lower = &g_tim8_lowerhalf; break; #endif -#ifdef CONFIG_STM32L4_TIM15 +#ifdef CONFIG_STM32_TIM15 case 15: lower = &g_tim15_lowerhalf; break; #endif -#ifdef CONFIG_STM32L4_TIM16 +#ifdef CONFIG_STM32_TIM16 case 16: lower = &g_tim16_lowerhalf; break; #endif -#ifdef CONFIG_STM32L4_TIM17 +#ifdef CONFIG_STM32_TIM17 case 17: lower = &g_tim17_lowerhalf; break; @@ -595,7 +595,7 @@ int stm32l4_timer_initialize(const char *devpath, int timer) lower->started = false; lower->callback = NULL; - lower->tim = stm32l4_tim_init(timer); + lower->tim = stm32_tim_init(timer); if (lower->tim == NULL) { diff --git a/arch/arm/src/stm32l4/stm32l4_timerisr.c b/arch/arm/src/stm32l4/stm32l4_timerisr.c index 1a37a689243e4..2c2b0747a38b8 100644 --- a/arch/arm/src/stm32l4/stm32l4_timerisr.c +++ b/arch/arm/src/stm32l4/stm32l4_timerisr.c @@ -37,7 +37,7 @@ #include "clock/clock.h" #include "arm_internal.h" #include "chip.h" -#include "stm32l4.h" +#include "stm32.h" /**************************************************************************** * Pre-processor Definitions @@ -54,13 +54,13 @@ * register. */ -#undef CONFIG_STM32L4_SYSTICK_HCLKd8 /* Power up default is HCLK, not HCLK/8 */ +#undef CONFIG_STM32_SYSTICK_HCLKd8 /* Power up default is HCLK, not HCLK/8 */ /* And I don't know now to re-configure it yet */ -#ifdef CONFIG_STM32L4_SYSTICK_HCLKd8 -# define SYSTICK_RELOAD ((STM32L4_HCLK_FREQUENCY / 8 / CLK_TCK) - 1) +#ifdef CONFIG_STM32_SYSTICK_HCLKd8 +# define SYSTICK_RELOAD ((STM32_HCLK_FREQUENCY / 8 / CLK_TCK) - 1) #else -# define SYSTICK_RELOAD ((STM32L4_HCLK_FREQUENCY / CLK_TCK) - 1) +# define SYSTICK_RELOAD ((STM32_HCLK_FREQUENCY / CLK_TCK) - 1) #endif /* The size of the reload field is 24 bits. Verify that the reload value @@ -76,7 +76,7 @@ ****************************************************************************/ /**************************************************************************** - * Function: stm32l4_timerisr + * Function: stm32_timerisr * * Description: * The timer ISR will perform a variety of services for various portions @@ -84,7 +84,7 @@ * ****************************************************************************/ -static int stm32l4_timerisr(int irq, uint32_t *regs, void *arg) +static int stm32_timerisr(int irq, uint32_t *regs, void *arg) { /* Process timer interrupt */ @@ -120,7 +120,7 @@ void up_timer_initialize(void) #if 0 /* Does not work. Comes up with HCLK source and I can't change it */ regval = getreg32(NVIC_SYSTICK_CTRL); -#ifdef CONFIG_STM32L4_SYSTICK_HCLKd8 +#ifdef CONFIG_STM32_SYSTICK_HCLKd8 regval &= ~NVIC_SYSTICK_CTRL_CLKSOURCE; #else regval |= NVIC_SYSTICK_CTRL_CLKSOURCE; @@ -134,7 +134,7 @@ void up_timer_initialize(void) /* Attach the timer interrupt vector */ - irq_attach(STM32L4_IRQ_SYSTICK, (xcpt_t)stm32l4_timerisr, NULL); + irq_attach(STM32_IRQ_SYSTICK, (xcpt_t)stm32_timerisr, NULL); /* Enable SysTick interrupts */ @@ -143,5 +143,5 @@ void up_timer_initialize(void) /* And enable the timer interrupt */ - up_enable_irq(STM32L4_IRQ_SYSTICK); + up_enable_irq(STM32_IRQ_SYSTICK); } diff --git a/arch/arm/src/stm32l4/stm32l4_uart.h b/arch/arm/src/stm32l4/stm32l4_uart.h index 4aa9468634648..059b5335cb58a 100644 --- a/arch/arm/src/stm32l4/stm32l4_uart.h +++ b/arch/arm/src/stm32l4/stm32l4_uart.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_STC_STM32L4_STM32L4_UART_H -#define __ARCH_ARM_STC_STM32L4_STM32L4_UART_H +#ifndef __ARCH_ARM_SRC_STM32L4_STM32_UART_H +#define __ARCH_ARM_SRC_STM32L4_STM32_UART_H /**************************************************************************** * Included Files @@ -32,8 +32,8 @@ #include "chip.h" -#if defined(CONFIG_STM32L4_STM32L4X3) || defined(CONFIG_STM32L4_STM32L4X5) || \ - defined(CONFIG_STM32L4_STM32L4X6) || defined(CONFIG_STM32L4_STM32L4XR) +#if defined(CONFIG_STM32_STM32L4X3) || defined(CONFIG_STM32_STM32L4X5) || \ + defined(CONFIG_STM32_STM32L4X6) || defined(CONFIG_STM32_STM32L4XR) # include "hardware/stm32l4_uart.h" #else # error "Unsupported STM32L4 chip" @@ -47,63 +47,63 @@ * the device. */ -#if !defined(CONFIG_STM32L4_HAVE_UART5) -# undef CONFIG_STM32L4_UART5 +#if !defined(CONFIG_STM32_HAVE_UART5) +# undef CONFIG_STM32_UART5 #endif -#if !defined(CONFIG_STM32L4_HAVE_UART4) -# undef CONFIG_STM32L4_UART4 +#if !defined(CONFIG_STM32_HAVE_UART4) +# undef CONFIG_STM32_UART4 #endif -#if !defined(CONFIG_STM32L4_HAVE_USART3) -# undef CONFIG_STM32L4_USART3 +#if !defined(CONFIG_STM32_HAVE_USART3) +# undef CONFIG_STM32_USART3 #endif -#if !defined(CONFIG_STM32L4_HAVE_USART2) -# undef CONFIG_STM32L4_USART2 +#if !defined(CONFIG_STM32_HAVE_USART2) +# undef CONFIG_STM32_USART2 #endif -#if !defined(CONFIG_STM32L4_HAVE_USART1) -# undef CONFIG_STM32L4_USART1 +#if !defined(CONFIG_STM32_HAVE_USART1) +# undef CONFIG_STM32_USART1 #endif -#if !defined(CONFIG_STM32L4_HAVE_LPUART1) -# undef CONFIG_STM32L4_LPUART1 +#if !defined(CONFIG_STM32_HAVE_LPUART1) +# undef CONFIG_STM32_LPUART1 #endif /* Sanity checks */ -#if !defined(CONFIG_STM32L4_LPUART1) -# undef CONFIG_STM32L4_LPUART1_SERIALDRIVER -# undef CONFIG_STM32L4_LPUART1_1WIREDRIVER +#if !defined(CONFIG_STM32_LPUART1) +# undef CONFIG_STM32_LPUART1_SERIALDRIVER +# undef CONFIG_STM32_LPUART1_1WIREDRIVER #endif -#if !defined(CONFIG_STM32L4_USART1) -# undef CONFIG_STM32L4_USART1_SERIALDRIVER -# undef CONFIG_STM32L4_USART1_1WIREDRIVER +#if !defined(CONFIG_STM32_USART1) +# undef CONFIG_STM32_USART1_SERIALDRIVER +# undef CONFIG_STM32_USART1_1WIREDRIVER #endif -#if !defined(CONFIG_STM32L4_USART2) -# undef CONFIG_STM32L4_USART2_SERIALDRIVER -# undef CONFIG_STM32L4_USART2_1WIREDRIVER +#if !defined(CONFIG_STM32_USART2) +# undef CONFIG_STM32_USART2_SERIALDRIVER +# undef CONFIG_STM32_USART2_1WIREDRIVER #endif -#if !defined(CONFIG_STM32L4_USART3) -# undef CONFIG_STM32L4_USART3_SERIALDRIVER -# undef CONFIG_STM32L4_USART3_1WIREDRIVER +#if !defined(CONFIG_STM32_USART3) +# undef CONFIG_STM32_USART3_SERIALDRIVER +# undef CONFIG_STM32_USART3_1WIREDRIVER #endif -#if !defined(CONFIG_STM32L4_UART4) -# undef CONFIG_STM32L4_UART4_SERIALDRIVER -# undef CONFIG_STM32L4_UART4_1WIREDRIVER +#if !defined(CONFIG_STM32_UART4) +# undef CONFIG_STM32_UART4_SERIALDRIVER +# undef CONFIG_STM32_UART4_1WIREDRIVER #endif -#if !defined(CONFIG_STM32L4_UART5) -# undef CONFIG_STM32L4_UART5_SERIALDRIVER -# undef CONFIG_STM32L4_UART5_1WIREDRIVER +#if !defined(CONFIG_STM32_UART5) +# undef CONFIG_STM32_UART5_SERIALDRIVER +# undef CONFIG_STM32_UART5_1WIREDRIVER #endif /* Is there a USART enabled? */ -#if defined(CONFIG_STM32L4_LPUART1) || defined(CONFIG_STM32L4_USART1) || \ - defined(CONFIG_STM32L4_USART2) || defined(CONFIG_STM32L4_USART3) || \ - defined(CONFIG_STM32L4_UART4) || defined(CONFIG_STM32L4_UART5) +#if defined(CONFIG_STM32_LPUART1) || defined(CONFIG_STM32_USART1) || \ + defined(CONFIG_STM32_USART2) || defined(CONFIG_STM32_USART3) || \ + defined(CONFIG_STM32_UART4) || defined(CONFIG_STM32_UART5) # define HAVE_UART 1 #endif /* Is there a serial console? */ -#if defined(CONFIG_LPUART1_SERIAL_CONSOLE) && defined(CONFIG_STM32L4_LPUART1_SERIALDRIVER) +#if defined(CONFIG_LPUART1_SERIAL_CONSOLE) && defined(CONFIG_STM32_LPUART1_SERIALDRIVER) # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE @@ -111,7 +111,7 @@ # undef CONFIG_UART5_SERIAL_CONSOLE # define CONSOLE_UART 1 # define HAVE_CONSOLE 1 -#elif defined(CONFIG_USART1_SERIAL_CONSOLE) && defined(CONFIG_STM32L4_USART1_SERIALDRIVER) +#elif defined(CONFIG_USART1_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART1_SERIALDRIVER) # undef CONFIG_LPUART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE @@ -119,7 +119,7 @@ # undef CONFIG_UART5_SERIAL_CONSOLE # define CONSOLE_UART 2 # define HAVE_CONSOLE 1 -#elif defined(CONFIG_USART2_SERIAL_CONSOLE) && defined(CONFIG_STM32L4_USART2_SERIALDRIVER) +#elif defined(CONFIG_USART2_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART2_SERIALDRIVER) # undef CONFIG_LPUART1_SERIAL_CONSOLE # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE @@ -127,7 +127,7 @@ # undef CONFIG_UART5_SERIAL_CONSOLE # define CONSOLE_UART 3 # define HAVE_CONSOLE 1 -#elif defined(CONFIG_USART3_SERIAL_CONSOLE) && defined(CONFIG_STM32L4_USART3_SERIALDRIVER) +#elif defined(CONFIG_USART3_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART3_SERIALDRIVER) # undef CONFIG_LPUART1_SERIAL_CONSOLE # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE @@ -135,7 +135,7 @@ # undef CONFIG_UART5_SERIAL_CONSOLE # define CONSOLE_UART 4 # define HAVE_CONSOLE 1 -#elif defined(CONFIG_UART4_SERIAL_CONSOLE) && defined(CONFIG_STM32L4_UART4_SERIALDRIVER) +#elif defined(CONFIG_UART4_SERIAL_CONSOLE) && defined(CONFIG_STM32_UART4_SERIALDRIVER) # undef CONFIG_LPUART1_SERIAL_CONSOLE # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE @@ -143,7 +143,7 @@ # undef CONFIG_UART5_SERIAL_CONSOLE # define CONSOLE_UART 5 # define HAVE_CONSOLE 1 -#elif defined(CONFIG_UART5_SERIAL_CONSOLE) && defined(CONFIG_STM32L4_UART5_SERIALDRIVER) +#elif defined(CONFIG_UART5_SERIAL_CONSOLE) && defined(CONFIG_STM32_UART5_SERIALDRIVER) # undef CONFIG_LPUART1_SERIAL_CONSOLE # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE @@ -177,27 +177,27 @@ /* Disable the DMA configuration on all unused USARTs */ -#ifndef CONFIG_STM32L4_LPUART1_SERIALDRIVER +#ifndef CONFIG_STM32_LPUART1_SERIALDRIVER # undef CONFIG_LPUART1_RXDMA #endif -#ifndef CONFIG_STM32L4_USART1_SERIALDRIVER +#ifndef CONFIG_STM32_USART1_SERIALDRIVER # undef CONFIG_USART1_RXDMA #endif -#ifndef CONFIG_STM32L4_USART2_SERIALDRIVER +#ifndef CONFIG_STM32_USART2_SERIALDRIVER # undef CONFIG_USART2_RXDMA #endif -#ifndef CONFIG_STM32L4_USART3_SERIALDRIVER +#ifndef CONFIG_STM32_USART3_SERIALDRIVER # undef CONFIG_USART3_RXDMA #endif -#ifndef CONFIG_STM32L4_UART4_SERIALDRIVER +#ifndef CONFIG_STM32_UART4_SERIALDRIVER # undef CONFIG_UART4_RXDMA #endif -#ifndef CONFIG_STM32L4_UART5_SERIALDRIVER +#ifndef CONFIG_STM32_UART5_SERIALDRIVER # undef CONFIG_UART5_RXDMA #endif @@ -230,17 +230,17 @@ /* Is DMA used on all (enabled) USARTs */ #define SERIAL_HAVE_ONLY_DMA 1 -#if defined(CONFIG_STM32L4_LPUART1_SERIALDRIVER) && !defined(CONFIG_LPUART1_RXDMA) +#if defined(CONFIG_STM32_LPUART1_SERIALDRIVER) && !defined(CONFIG_LPUART1_RXDMA) # undef SERIAL_HAVE_ONLY_DMA -#elif defined(CONFIG_STM32L4_USART1_SERIALDRIVER) && !defined(CONFIG_USART1_RXDMA) +#elif defined(CONFIG_STM32_USART1_SERIALDRIVER) && !defined(CONFIG_USART1_RXDMA) # undef SERIAL_HAVE_ONLY_DMA -#elif defined(CONFIG_STM32L4_USART2_SERIALDRIVER) && !defined(CONFIG_USART2_RXDMA) +#elif defined(CONFIG_STM32_USART2_SERIALDRIVER) && !defined(CONFIG_USART2_RXDMA) # undef SERIAL_HAVE_ONLY_DMA -#elif defined(CONFIG_STM32L4_USART3_SERIALDRIVER) && !defined(CONFIG_USART3_RXDMA) +#elif defined(CONFIG_STM32_USART3_SERIALDRIVER) && !defined(CONFIG_USART3_RXDMA) # undef SERIAL_HAVE_ONLY_DMA -#elif defined(CONFIG_STM32L4_UART4_SERIALDRIVER) && !defined(CONFIG_UART4_RXDMA) +#elif defined(CONFIG_STM32_UART4_SERIALDRIVER) && !defined(CONFIG_UART4_RXDMA) # undef SERIAL_HAVE_ONLY_DMA -#elif defined(CONFIG_STM32L4_UART5_SERIALDRIVER) && !defined(CONFIG_UART5_RXDMA) +#elif defined(CONFIG_STM32_UART5_SERIALDRIVER) && !defined(CONFIG_UART5_RXDMA) # undef SERIAL_HAVE_ONLY_DMA #endif @@ -282,7 +282,7 @@ extern "C" ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_serial_dma_poll + * Name: stm32_serial_dma_poll * * Description: * Must be called periodically if any STM32 UART is configured for DMA. @@ -295,7 +295,7 @@ extern "C" ****************************************************************************/ #ifdef SERIAL_HAVE_RXDMA -void stm32l4_serial_dma_poll(void); +void stm32_serial_dma_poll(void); #endif #undef EXTERN @@ -304,4 +304,4 @@ void stm32l4_serial_dma_poll(void); #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_STC_STM32L4_STM32L4_UART_H */ +#endif /* __ARCH_ARM_SRC_STM32L4_STM32_UART_H */ diff --git a/arch/arm/src/stm32l4/stm32l4_uid.c b/arch/arm/src/stm32l4/stm32l4_uid.c deleted file mode 100644 index ef9d52da06400..0000000000000 --- a/arch/arm/src/stm32l4/stm32l4_uid.c +++ /dev/null @@ -1,63 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32l4/stm32l4_uid.c - * - * SPDX-License-Identifier: BSD-3-Clause - * SPDX-FileCopyrightText: 2015 Marawan Ragab. All rights reserved. - * SPDX-FileContributor: Marawan Ragab - * SPDX-FileContributor: dev@ziggurat9.com - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "hardware/stm32l4_memorymap.h" -#include "stm32l4_uid.h" - -#ifdef STM32L4_SYSMEM_UID - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -void stm32l4_get_uniqueid(uint8_t uniqueid[12]) -{ - int i; - - for (i = 0; i < 12; i++) - { - uniqueid[i] = *((uint8_t *)(STM32L4_SYSMEM_UID)+i); - } -} - -#endif /* STM32L4_SYSMEM_UID */ diff --git a/arch/arm/src/stm32l4/stm32l4_uid.h b/arch/arm/src/stm32l4/stm32l4_uid.h deleted file mode 100644 index a9b1cf4027f6b..0000000000000 --- a/arch/arm/src/stm32l4/stm32l4_uid.h +++ /dev/null @@ -1,53 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32l4/stm32l4_uid.h - * - * SPDX-License-Identifier: BSD-3-Clause - * SPDX-FileCopyrightText: 2015 Marawan Ragab. All rights reserved. - * SPDX-FileContributor: Marawan Ragab - * SPDX-FileContributor: dev@ziggurat9.com - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32L4_STM32L4_UID_H -#define __ARCH_ARM_SRC_STM32L4_STM32L4_UID_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -void stm32l4_get_uniqueid(uint8_t uniqueid[12]); - -#endif /* __ARCH_ARM_SRC_STM32L4_STM32L4_UID_H */ diff --git a/arch/arm/src/stm32l4/stm32l4_usbdev.c b/arch/arm/src/stm32l4/stm32l4_usbdev.c index f3424f388a3e5..5bbac6ed9b726 100644 --- a/arch/arm/src/stm32l4/stm32l4_usbdev.c +++ b/arch/arm/src/stm32l4/stm32l4_usbdev.c @@ -45,11 +45,11 @@ #include #include "arm_internal.h" -#include "stm32l4.h" +#include "stm32.h" #include "stm32l4_gpio.h" #include "stm32l4_usbdev.h" -#if defined(CONFIG_USBDEV) && defined(CONFIG_STM32L4_USBFS) +#if defined(CONFIG_USBDEV) && defined(CONFIG_STM32_USBFS) /**************************************************************************** * Pre-processor Definitions @@ -70,22 +70,22 @@ */ #ifndef CONFIG_DEBUG_USB_INFO -# undef CONFIG_STM32L4_USBDEV_REGDEBUG +# undef CONFIG_STM32_USBDEV_REGDEBUG #endif /* Initial interrupt mask: Reset + Suspend + Correct Transfer */ -#define STM32L4_CNTR_SETUP (USB_CNTR_RESETM|USB_CNTR_SUSPM|USB_CNTR_CTRM) +#define STM32_CNTR_SETUP (USB_CNTR_RESETM|USB_CNTR_SUSPM|USB_CNTR_CTRM) /* Endpoint identifiers. The STM32L4 supports up to 16 mono-directional or 8 * bidirectional endpoints. However, when you take into account PMA buffer * usage (see below) and the fact that EP0 is bidirectional, then there is * a functional limitation of EP0 + 5 mono-directional endpoints = 6. We'll - * define STM32L4_NENDPOINTS to be 8, however, because that is how many + * define STM32_NENDPOINTS to be 8, however, because that is how many * endpoint register sets there are. */ -#define STM32L4_NENDPOINTS (8) +#define STM32_NENDPOINTS (8) #define EP0 (0) #define EP1 (1) #define EP2 (2) @@ -95,47 +95,47 @@ #define EP6 (6) #define EP7 (7) -#define STM32L4_ENDP_BIT(ep) (1 << (ep)) -#define STM32L4_ENDP_ALLSET 0xff +#define STM32_ENDP_BIT(ep) (1 << (ep)) +#define STM32_ENDP_ALLSET 0xff /* Packet sizes. We us a fixed 64 max packet size for all endpoint types */ -#define STM32L4_MAXPACKET_SHIFT (6) -#define STM32L4_MAXPACKET_SIZE (1 << (STM32L4_MAXPACKET_SHIFT)) -#define STM32L4_MAXPACKET_MASK (STM32L4_MAXPACKET_SIZE-1) +#define STM32_MAXPACKET_SHIFT (6) +#define STM32_MAXPACKET_SIZE (1 << (STM32_MAXPACKET_SHIFT)) +#define STM32_MAXPACKET_MASK (STM32_MAXPACKET_SIZE-1) -#define STM32L4_EP0MAXPACKET STM32L4_MAXPACKET_SIZE +#define STM32_EP0MAXPACKET STM32_MAXPACKET_SIZE /* Buffer descriptor table. * The buffer table is positioned at the beginning of the 1024-byte - * USB memory. We will use the first STM32L4_NENDPOINTS*8 bytes for + * USB memory. We will use the first STM32_NENDPOINTS*8 bytes for * the buffer table. That is exactly 64 bytes, leaving 15*64 bytes for * endpoint buffers. */ -#define STM32L4_BTABLE_ADDRESS (0x00) /* Start at the beginning of USB +#define STM32_BTABLE_ADDRESS (0x00) /* Start at the beginning of USB * RAM */ -#define STM32L4_DESC_SIZE (8) /* Each descriptor is 4*2=8 +#define STM32_DESC_SIZE (8) /* Each descriptor is 4*2=8 * bytes in size */ -#define STM32L4_BTABLE_SIZE (STM32L4_NENDPOINTS*STM32L4_DESC_SIZE) +#define STM32_BTABLE_SIZE (STM32_NENDPOINTS*STM32_DESC_SIZE) /* Buffer layout. Assume that all buffers are 64-bytes (maxpacketsize), * then we have space for only 7 buffers; endpoint 0 will require two * buffers, leaving 5 for other endpoints. */ -#define STM32L4_BUFFER_START STM32L4_BTABLE_SIZE -#define STM32L4_EP0_RXADDR STM32L4_BUFFER_START -#define STM32L4_EP0_TXADDR (STM32L4_EP0_RXADDR+STM32L4_EP0MAXPACKET) +#define STM32_BUFFER_START STM32_BTABLE_SIZE +#define STM32_EP0_RXADDR STM32_BUFFER_START +#define STM32_EP0_TXADDR (STM32_EP0_RXADDR+STM32_EP0MAXPACKET) -#define STM32L4_BUFFER_EP0 0x03 -#define STM32L4_NBUFFERS 7 -#define STM32L4_BUFFER_BIT(bn) (1 << (bn)) -#define STM32L4_BUFFER_ALLSET 0x7f -#define STM32L4_BUFNO2BUF(bn) (STM32L4_BUFFER_START+((bn)<head == NULL) -#define stm32l4_rqpeek(ep) ((ep)->head) +#define stm32_rqempty(ep) ((ep)->head == NULL) +#define stm32_rqpeek(ep) ((ep)->head) /* USB trace ****************************************************************/ /* Trace error codes */ -#define STM32L4_TRACEERR_ALLOCFAIL 0x0001 -#define STM32L4_TRACEERR_BADCLEARFEATURE 0x0002 -#define STM32L4_TRACEERR_BADDEVGETSTATUS 0x0003 -#define STM32L4_TRACEERR_BADEPGETSTATUS 0x0004 -#define STM32L4_TRACEERR_BADEPNO 0x0005 -#define STM32L4_TRACEERR_BADEPTYPE 0x0006 -#define STM32L4_TRACEERR_BADGETCONFIG 0x0007 -#define STM32L4_TRACEERR_BADGETSETDESC 0x0008 -#define STM32L4_TRACEERR_BADGETSTATUS 0x0009 -#define STM32L4_TRACEERR_BADSETADDRESS 0x000a -#define STM32L4_TRACEERR_BADSETCONFIG 0x000b -#define STM32L4_TRACEERR_BADSETFEATURE 0x000c -#define STM32L4_TRACEERR_BINDFAILED 0x000d -#define STM32L4_TRACEERR_DISPATCHSTALL 0x000e -#define STM32L4_TRACEERR_DRIVER 0x000f -#define STM32L4_TRACEERR_DRIVERREGISTERED 0x0010 -#define STM32L4_TRACEERR_EP0BADCTR 0x0011 -#define STM32L4_TRACEERR_EP0SETUPSTALLED 0x0012 -#define STM32L4_TRACEERR_EPBUFFER 0x0013 -#define STM32L4_TRACEERR_EPDISABLED 0x0014 -#define STM32L4_TRACEERR_EPOUTNULLPACKET 0x0015 -#define STM32L4_TRACEERR_EPRESERVE 0x0016 -#define STM32L4_TRACEERR_INVALIDCTRLREQ 0x0017 -#define STM32L4_TRACEERR_INVALIDPARMS 0x0018 -#define STM32L4_TRACEERR_IRQREGISTRATION 0x0019 -#define STM32L4_TRACEERR_NOTCONFIGURED 0x001a -#define STM32L4_TRACEERR_REQABORTED 0x001b +#define STM32_TRACEERR_ALLOCFAIL 0x0001 +#define STM32_TRACEERR_BADCLEARFEATURE 0x0002 +#define STM32_TRACEERR_BADDEVGETSTATUS 0x0003 +#define STM32_TRACEERR_BADEPGETSTATUS 0x0004 +#define STM32_TRACEERR_BADEPNO 0x0005 +#define STM32_TRACEERR_BADEPTYPE 0x0006 +#define STM32_TRACEERR_BADGETCONFIG 0x0007 +#define STM32_TRACEERR_BADGETSETDESC 0x0008 +#define STM32_TRACEERR_BADGETSTATUS 0x0009 +#define STM32_TRACEERR_BADSETADDRESS 0x000a +#define STM32_TRACEERR_BADSETCONFIG 0x000b +#define STM32_TRACEERR_BADSETFEATURE 0x000c +#define STM32_TRACEERR_BINDFAILED 0x000d +#define STM32_TRACEERR_DISPATCHSTALL 0x000e +#define STM32_TRACEERR_DRIVER 0x000f +#define STM32_TRACEERR_DRIVERREGISTERED 0x0010 +#define STM32_TRACEERR_EP0BADCTR 0x0011 +#define STM32_TRACEERR_EP0SETUPSTALLED 0x0012 +#define STM32_TRACEERR_EPBUFFER 0x0013 +#define STM32_TRACEERR_EPDISABLED 0x0014 +#define STM32_TRACEERR_EPOUTNULLPACKET 0x0015 +#define STM32_TRACEERR_EPRESERVE 0x0016 +#define STM32_TRACEERR_INVALIDCTRLREQ 0x0017 +#define STM32_TRACEERR_INVALIDPARMS 0x0018 +#define STM32_TRACEERR_IRQREGISTRATION 0x0019 +#define STM32_TRACEERR_NOTCONFIGURED 0x001a +#define STM32_TRACEERR_REQABORTED 0x001b /* Trace interrupt codes */ -#define STM32L4_TRACEINTID_CLEARFEATURE 0x0001 -#define STM32L4_TRACEINTID_DEVGETSTATUS 0x0002 -#define STM32L4_TRACEINTID_DISPATCH 0x0003 -#define STM32L4_TRACEINTID_EP0IN 0x0004 -#define STM32L4_TRACEINTID_EP0INDONE 0x0005 -#define STM32L4_TRACEINTID_EP0OUTDONE 0x0006 -#define STM32L4_TRACEINTID_EP0SETUPDONE 0x0007 -#define STM32L4_TRACEINTID_EP0SETUPSETADDRESS 0x0008 -#define STM32L4_TRACEINTID_EPGETSTATUS 0x0009 -#define STM32L4_TRACEINTID_EPINDONE 0x000a -#define STM32L4_TRACEINTID_EPINQEMPTY 0x000b -#define STM32L4_TRACEINTID_EPOUTDONE 0x000c -#define STM32L4_TRACEINTID_EPOUTPENDING 0x000d -#define STM32L4_TRACEINTID_EPOUTQEMPTY 0x000e -#define STM32L4_TRACEINTID_ESOF 0x000f -#define STM32L4_TRACEINTID_GETCONFIG 0x0010 -#define STM32L4_TRACEINTID_GETSETDESC 0x0011 -#define STM32L4_TRACEINTID_GETSETIF 0x0012 -#define STM32L4_TRACEINTID_GETSTATUS 0x0013 +#define STM32_TRACEINTID_CLEARFEATURE 0x0001 +#define STM32_TRACEINTID_DEVGETSTATUS 0x0002 +#define STM32_TRACEINTID_DISPATCH 0x0003 +#define STM32_TRACEINTID_EP0IN 0x0004 +#define STM32_TRACEINTID_EP0INDONE 0x0005 +#define STM32_TRACEINTID_EP0OUTDONE 0x0006 +#define STM32_TRACEINTID_EP0SETUPDONE 0x0007 +#define STM32_TRACEINTID_EP0SETUPSETADDRESS 0x0008 +#define STM32_TRACEINTID_EPGETSTATUS 0x0009 +#define STM32_TRACEINTID_EPINDONE 0x000a +#define STM32_TRACEINTID_EPINQEMPTY 0x000b +#define STM32_TRACEINTID_EPOUTDONE 0x000c +#define STM32_TRACEINTID_EPOUTPENDING 0x000d +#define STM32_TRACEINTID_EPOUTQEMPTY 0x000e +#define STM32_TRACEINTID_ESOF 0x000f +#define STM32_TRACEINTID_GETCONFIG 0x0010 +#define STM32_TRACEINTID_GETSETDESC 0x0011 +#define STM32_TRACEINTID_GETSETIF 0x0012 +#define STM32_TRACEINTID_GETSTATUS 0x0013 /* HPINTERRUPT not used */ -#define STM32L4_TRACEINTID_IFGETSTATUS 0x0015 -#define STM32L4_TRACEINTID_USBCTR 0x0016 -#define STM32L4_TRACEINTID_USBINTERRUPT 0x0017 -#define STM32L4_TRACEINTID_NOSTDREQ 0x0018 -#define STM32L4_TRACEINTID_RESET 0x0019 -#define STM32L4_TRACEINTID_SETCONFIG 0x001a -#define STM32L4_TRACEINTID_SETFEATURE 0x001b -#define STM32L4_TRACEINTID_SUSP 0x001c -#define STM32L4_TRACEINTID_SYNCHFRAME 0x001d -#define STM32L4_TRACEINTID_WKUP 0x001e -#define STM32L4_TRACEINTID_EP0SETUPOUT 0x001f -#define STM32L4_TRACEINTID_EP0SETUPOUTDATA 0x0020 +#define STM32_TRACEINTID_IFGETSTATUS 0x0015 +#define STM32_TRACEINTID_USBCTR 0x0016 +#define STM32_TRACEINTID_USBINTERRUPT 0x0017 +#define STM32_TRACEINTID_NOSTDREQ 0x0018 +#define STM32_TRACEINTID_RESET 0x0019 +#define STM32_TRACEINTID_SETCONFIG 0x001a +#define STM32_TRACEINTID_SETFEATURE 0x001b +#define STM32_TRACEINTID_SUSP 0x001c +#define STM32_TRACEINTID_SYNCHFRAME 0x001d +#define STM32_TRACEINTID_WKUP 0x001e +#define STM32_TRACEINTID_EP0SETUPOUT 0x001f +#define STM32_TRACEINTID_EP0SETUPOUTDATA 0x0020 /* Byte ordering in host-based values */ @@ -236,7 +236,7 @@ /* The various states of a control pipe */ -enum stm32l4_ep0state_e +enum stm32_ep0state_e { EP0STATE_IDLE = 0, /* No request in progress */ EP0STATE_SETUP_OUT, /* Set up received with data for device OUT in progress */ @@ -249,7 +249,7 @@ enum stm32l4_ep0state_e /* Resume states */ -enum stm32l4_rsmstate_e +enum stm32_rsmstate_e { RSMSTATE_IDLE = 0, /* Device is either fully suspended or running */ RSMSTATE_STARTED, /* Resume sequence has been started */ @@ -264,28 +264,28 @@ union wb_u /* A container for a request so that the request make be retained in a list */ -struct stm32l4_req_s +struct stm32_req_s { struct usbdev_req_s req; /* Standard USB request */ - struct stm32l4_req_s *flink; /* Supports a singly linked list */ + struct stm32_req_s *flink; /* Supports a singly linked list */ }; /* This is the internal representation of an endpoint */ -struct stm32l4_ep_s +struct stm32_ep_s { /* Common endpoint fields. This must be the first thing defined in the * structure so that it is possible to simply cast from struct usbdev_ep_s - * to struct stm32l4_ep_s. + * to struct stm32_ep_s. */ struct usbdev_ep_s ep; /* Standard endpoint structure */ /* STM32-specific fields */ - struct stm32l4_usbdev_s *dev; /* Reference to private driver data */ - struct stm32l4_req_s *head; /* Request list for this endpoint */ - struct stm32l4_req_s *tail; + struct stm32_usbdev_s *dev; /* Reference to private driver data */ + struct stm32_req_s *head; /* Request list for this endpoint */ + struct stm32_req_s *tail; uint8_t bufno; /* Allocated buffer number */ uint8_t stalled:1; /* true: Endpoint is stalled */ uint8_t halted:1; /* true: Endpoint feature halted */ @@ -293,7 +293,7 @@ struct stm32l4_ep_s uint8_t txnullpkt:1; /* Null packet needed at end of transfer */ }; -struct stm32l4_usbdev_s +struct stm32_usbdev_s { /* Common device fields. This must be the first thing defined in the * structure so that it is possible to simply cast from struct usbdev_s @@ -308,8 +308,8 @@ struct stm32l4_usbdev_s /* STM32-specific fields */ - uint8_t ep0state; /* State of EP0 (see enum stm32l4_ep0state_e) */ - uint8_t rsmstate; /* Resume state (see enum stm32l4_rsmstate_e) */ + uint8_t ep0state; /* State of EP0 (see enum stm32_ep0state_e) */ + uint8_t rsmstate; /* Resume state (see enum stm32_rsmstate_e) */ uint8_t nesofs; /* ESOF counter (for resume support) */ uint8_t rxpending:1; /* 1: OUT data in PMA, but no read requests */ uint8_t selfpowered:1; /* 1: Device is self powered */ @@ -328,7 +328,7 @@ struct stm32l4_usbdev_s * ep0data * For OUT SETUP requests, the SETUP data phase must also complete before * the SETUP command can be processed. The ep0 packet receipt logic - * stm32l4_ep0_rdrequest will save the accompanying EP0 OUT data in + * stm32_ep0_rdrequest will save the accompanying EP0 OUT data in * ep0data[] before the SETUP command is re-processed. * * ep0datlen @@ -342,7 +342,7 @@ struct stm32l4_usbdev_s /* The endpoint list */ - struct stm32l4_ep_s eplist[STM32L4_NENDPOINTS]; + struct stm32_ep_s eplist[STM32_NENDPOINTS]; }; /**************************************************************************** @@ -351,157 +351,157 @@ struct stm32l4_usbdev_s /* Register operations ******************************************************/ -#ifdef CONFIG_STM32L4_USBDEV_REGDEBUG -static uint16_t stm32l4_getreg(uint32_t addr); -static void stm32l4_putreg(uint16_t val, uint32_t addr); -static void stm32l4_checksetup(void); -static void stm32l4_dumpep(int epno); +#ifdef CONFIG_STM32_USBDEV_REGDEBUG +static uint16_t stm32_getreg(uint32_t addr); +static void stm32_putreg(uint16_t val, uint32_t addr); +static void stm32_checksetup(void); +static void stm32_dumpep(int epno); #else -# define stm32l4_getreg(addr) getreg16(addr) -# define stm32l4_putreg(val,addr) putreg16(val,addr) -# define stm32l4_checksetup() -# define stm32l4_dumpep(epno) +# define stm32_getreg(addr) getreg16(addr) +# define stm32_putreg(val,addr) putreg16(val,addr) +# define stm32_checksetup() +# define stm32_dumpep(epno) #endif /* Low-Level Helpers ********************************************************/ static inline void - stm32l4_seteptxcount(uint8_t epno, uint16_t count); + stm32_seteptxcount(uint8_t epno, uint16_t count); static inline void - stm32l4_seteptxaddr(uint8_t epno, uint16_t addr); + stm32_seteptxaddr(uint8_t epno, uint16_t addr); static inline uint16_t - stm32l4_geteptxaddr(uint8_t epno); -static void stm32l4_seteprxcount(uint8_t epno, uint16_t count); + stm32_geteptxaddr(uint8_t epno); +static void stm32_seteprxcount(uint8_t epno, uint16_t count); static inline uint16_t - stm32l4_geteprxcount(uint8_t epno); + stm32_geteprxcount(uint8_t epno); static inline void - stm32l4_seteprxaddr(uint8_t epno, uint16_t addr); + stm32_seteprxaddr(uint8_t epno, uint16_t addr); static inline uint16_t - stm32l4_geteprxaddr(uint8_t epno); + stm32_geteprxaddr(uint8_t epno); static inline void - stm32l4_setepaddress(uint8_t epno, uint16_t addr); + stm32_setepaddress(uint8_t epno, uint16_t addr); static inline void - stm32l4_seteptype(uint8_t epno, uint16_t type); + stm32_seteptype(uint8_t epno, uint16_t type); static inline void - stm32l4_seteptxaddr(uint8_t epno, uint16_t addr); + stm32_seteptxaddr(uint8_t epno, uint16_t addr); static inline void - stm32l4_setstatusout(uint8_t epno); + stm32_setstatusout(uint8_t epno); static inline void - stm32l4_clrstatusout(uint8_t epno); -static void stm32l4_clrrxdtog(uint8_t epno); -static void stm32l4_clrtxdtog(uint8_t epno); -static void stm32l4_clrepctrrx(uint8_t epno); -static void stm32l4_clrepctrtx(uint8_t epno); -static void stm32l4_seteptxstatus(uint8_t epno, uint16_t state); -static void stm32l4_seteprxstatus(uint8_t epno, uint16_t state); + stm32_clrstatusout(uint8_t epno); +static void stm32_clrrxdtog(uint8_t epno); +static void stm32_clrtxdtog(uint8_t epno); +static void stm32_clrepctrrx(uint8_t epno); +static void stm32_clrepctrtx(uint8_t epno); +static void stm32_seteptxstatus(uint8_t epno, uint16_t state); +static void stm32_seteprxstatus(uint8_t epno, uint16_t state); static inline uint16_t - stm32l4_geteptxstatus(uint8_t epno); + stm32_geteptxstatus(uint8_t epno); static inline uint16_t - stm32l4_geteprxstatus(uint8_t epno); -static bool stm32l4_eptxstalled(uint8_t epno); -static bool stm32l4_eprxstalled(uint8_t epno); -static void stm32l4_setimask(struct stm32l4_usbdev_s *priv, + stm32_geteprxstatus(uint8_t epno); +static bool stm32_eptxstalled(uint8_t epno); +static bool stm32_eprxstalled(uint8_t epno); +static void stm32_setimask(struct stm32_usbdev_s *priv, uint16_t setbits, uint16_t clrbits); /* Suspend/Resume Helpers ***************************************************/ -static void stm32l4_suspend(struct stm32l4_usbdev_s *priv); -static void stm32l4_initresume(struct stm32l4_usbdev_s *priv); -static void stm32l4_esofpoll(struct stm32l4_usbdev_s *priv) ; +static void stm32_suspend(struct stm32_usbdev_s *priv); +static void stm32_initresume(struct stm32_usbdev_s *priv); +static void stm32_esofpoll(struct stm32_usbdev_s *priv) ; /* Request Helpers **********************************************************/ -static void stm32l4_copytopma(const uint8_t *buffer, uint16_t pma, +static void stm32_copytopma(const uint8_t *buffer, uint16_t pma, uint16_t nbytes); static inline void - stm32l4_copyfrompma(uint8_t *buffer, uint16_t pma, + stm32_copyfrompma(uint8_t *buffer, uint16_t pma, uint16_t nbytes); -static struct stm32l4_req_s * - stm32l4_rqdequeue(struct stm32l4_ep_s *privep); -static void stm32l4_rqenqueue(struct stm32l4_ep_s *privep, - struct stm32l4_req_s *req); +static struct stm32_req_s * + stm32_rqdequeue(struct stm32_ep_s *privep); +static void stm32_rqenqueue(struct stm32_ep_s *privep, + struct stm32_req_s *req); static inline void - stm32l4_abortrequest(struct stm32l4_ep_s *privep, - struct stm32l4_req_s *privreq, + stm32_abortrequest(struct stm32_ep_s *privep, + struct stm32_req_s *privreq, int16_t result); -static void stm32l4_reqcomplete(struct stm32l4_ep_s *privep, +static void stm32_reqcomplete(struct stm32_ep_s *privep, int16_t result); -static void stm32l4_epwrite(struct stm32l4_usbdev_s *buf, - struct stm32l4_ep_s *privep, +static void stm32_epwrite(struct stm32_usbdev_s *buf, + struct stm32_ep_s *privep, const uint8_t *data, uint32_t nbytes); -static int stm32l4_wrrequest(struct stm32l4_usbdev_s *priv, - struct stm32l4_ep_s *privep); +static int stm32_wrrequest(struct stm32_usbdev_s *priv, + struct stm32_ep_s *privep); inline static int - stm32l4_wrrequest_ep0(struct stm32l4_usbdev_s *priv, - struct stm32l4_ep_s *privep); + stm32_wrrequest_ep0(struct stm32_usbdev_s *priv, + struct stm32_ep_s *privep); static inline int - stm32l4_ep0_rdrequest(struct stm32l4_usbdev_s *priv); -static int stm32l4_rdrequest(struct stm32l4_usbdev_s *priv, - struct stm32l4_ep_s *privep); -static void stm32l4_cancelrequests(struct stm32l4_ep_s *privep); + stm32_ep0_rdrequest(struct stm32_usbdev_s *priv); +static int stm32_rdrequest(struct stm32_usbdev_s *priv, + struct stm32_ep_s *privep); +static void stm32_cancelrequests(struct stm32_ep_s *privep); /* Interrupt level processing ***********************************************/ -static void stm32l4_dispatchrequest(struct stm32l4_usbdev_s *priv); -static void stm32l4_epdone(struct stm32l4_usbdev_s *priv, uint8_t epno); -static void stm32l4_setdevaddr(struct stm32l4_usbdev_s *priv, +static void stm32_dispatchrequest(struct stm32_usbdev_s *priv); +static void stm32_epdone(struct stm32_usbdev_s *priv, uint8_t epno); +static void stm32_setdevaddr(struct stm32_usbdev_s *priv, uint8_t value); -static void stm32l4_ep0setup(struct stm32l4_usbdev_s *priv); -static void stm32l4_ep0out(struct stm32l4_usbdev_s *priv); -static void stm32l4_ep0in(struct stm32l4_usbdev_s *priv); +static void stm32_ep0setup(struct stm32_usbdev_s *priv); +static void stm32_ep0out(struct stm32_usbdev_s *priv); +static void stm32_ep0in(struct stm32_usbdev_s *priv); static inline void - stm32l4_ep0done(struct stm32l4_usbdev_s *priv, uint16_t istr); -static void stm32l4_lptransfer(struct stm32l4_usbdev_s *priv); -static int stm32l4_usbinterrupt(int irq, void *context, void *arg); + stm32_ep0done(struct stm32_usbdev_s *priv, uint16_t istr); +static void stm32_lptransfer(struct stm32_usbdev_s *priv); +static int stm32_usbinterrupt(int irq, void *context, void *arg); /* Endpoint helpers *********************************************************/ -static inline struct stm32l4_ep_s * - stm32l4_epreserve(struct stm32l4_usbdev_s *priv, +static inline struct stm32_ep_s * + stm32_epreserve(struct stm32_usbdev_s *priv, uint8_t epset); static inline void - stm32l4_epunreserve(struct stm32l4_usbdev_s *priv, - struct stm32l4_ep_s *privep); + stm32_epunreserve(struct stm32_usbdev_s *priv, + struct stm32_ep_s *privep); static inline bool - stm32l4_epreserved(struct stm32l4_usbdev_s *priv, int epno); -static int stm32l4_epallocpma(struct stm32l4_usbdev_s *priv); + stm32_epreserved(struct stm32_usbdev_s *priv, int epno); +static int stm32_epallocpma(struct stm32_usbdev_s *priv); static inline void - stm32l4_epfreepma(struct stm32l4_usbdev_s *priv, - struct stm32l4_ep_s *privep); + stm32_epfreepma(struct stm32_usbdev_s *priv, + struct stm32_ep_s *privep); /* Endpoint operations ******************************************************/ -static int stm32l4_epconfigure(struct usbdev_ep_s *ep, +static int stm32_epconfigure(struct usbdev_ep_s *ep, const struct usb_epdesc_s *desc, bool last); -static int stm32l4_epdisable(struct usbdev_ep_s *ep); +static int stm32_epdisable(struct usbdev_ep_s *ep); static struct usbdev_req_s * - stm32l4_epallocreq(struct usbdev_ep_s *ep); -static void stm32l4_epfreereq(struct usbdev_ep_s *ep, + stm32_epallocreq(struct usbdev_ep_s *ep); +static void stm32_epfreereq(struct usbdev_ep_s *ep, struct usbdev_req_s *); -static int stm32l4_epsubmit(struct usbdev_ep_s *ep, +static int stm32_epsubmit(struct usbdev_ep_s *ep, struct usbdev_req_s *req); -static int stm32l4_epcancel(struct usbdev_ep_s *ep, +static int stm32_epcancel(struct usbdev_ep_s *ep, struct usbdev_req_s *req); -static int stm32l4_epstall(struct usbdev_ep_s *ep, bool resume); +static int stm32_epstall(struct usbdev_ep_s *ep, bool resume); /* USB device controller operations *****************************************/ static struct usbdev_ep_s * - stm32l4_allocep(struct usbdev_s *dev, uint8_t epno, bool in, + stm32_allocep(struct usbdev_s *dev, uint8_t epno, bool in, uint8_t eptype); -static void stm32l4_freeep(struct usbdev_s *dev, struct usbdev_ep_s *ep); -static int stm32l4_getframe(struct usbdev_s *dev); -static int stm32l4_wakeup(struct usbdev_s *dev); -static int stm32l4_selfpowered(struct usbdev_s *dev, bool selfpowered); -static int stm32l4_pullup(struct usbdev_s *dev, bool enable); +static void stm32_freeep(struct usbdev_s *dev, struct usbdev_ep_s *ep); +static int stm32_getframe(struct usbdev_s *dev); +static int stm32_wakeup(struct usbdev_s *dev); +static int stm32_selfpowered(struct usbdev_s *dev, bool selfpowered); +static int stm32_pullup(struct usbdev_s *dev, bool enable); /* Initialization/Reset *****************************************************/ -static void stm32l4_reset(struct stm32l4_usbdev_s *priv); -static void stm32l4_hwreset(struct stm32l4_usbdev_s *priv); -static void stm32l4_hwsetup(struct stm32l4_usbdev_s *priv); -static void stm32l4_hwshutdown(struct stm32l4_usbdev_s *priv); +static void stm32_reset(struct stm32_usbdev_s *priv); +static void stm32_hwreset(struct stm32_usbdev_s *priv); +static void stm32_hwsetup(struct stm32_usbdev_s *priv); +static void stm32_hwshutdown(struct stm32_usbdev_s *priv); /**************************************************************************** * Private Data @@ -511,27 +511,27 @@ static void stm32l4_hwshutdown(struct stm32l4_usbdev_s *priv); * be simply retained in a single global instance. */ -static struct stm32l4_usbdev_s g_usbdev; +static struct stm32_usbdev_s g_usbdev; static const struct usbdev_epops_s g_epops = { - .configure = stm32l4_epconfigure, - .disable = stm32l4_epdisable, - .allocreq = stm32l4_epallocreq, - .freereq = stm32l4_epfreereq, - .submit = stm32l4_epsubmit, - .cancel = stm32l4_epcancel, - .stall = stm32l4_epstall, + .configure = stm32_epconfigure, + .disable = stm32_epdisable, + .allocreq = stm32_epallocreq, + .freereq = stm32_epfreereq, + .submit = stm32_epsubmit, + .cancel = stm32_epcancel, + .stall = stm32_epstall, }; static const struct usbdev_ops_s g_devops = { - .allocep = stm32l4_allocep, - .freeep = stm32l4_freeep, - .getframe = stm32l4_getframe, - .wakeup = stm32l4_wakeup, - .selfpowered = stm32l4_selfpowered, - .pullup = stm32l4_pullup, + .allocep = stm32_allocep, + .freeep = stm32_freeep, + .getframe = stm32_getframe, + .wakeup = stm32_wakeup, + .selfpowered = stm32_selfpowered, + .pullup = stm32_pullup, }; /**************************************************************************** @@ -541,37 +541,37 @@ static const struct usbdev_ops_s g_devops = #ifdef CONFIG_USBDEV_TRACE_STRINGS const struct trace_msg_t g_usb_trace_strings_intdecode[] = { - TRACE_STR(STM32L4_TRACEINTID_CLEARFEATURE), - TRACE_STR(STM32L4_TRACEINTID_DEVGETSTATUS), - TRACE_STR(STM32L4_TRACEINTID_DISPATCH), - TRACE_STR(STM32L4_TRACEINTID_EP0IN), - TRACE_STR(STM32L4_TRACEINTID_EP0INDONE), - TRACE_STR(STM32L4_TRACEINTID_EP0OUTDONE), - TRACE_STR(STM32L4_TRACEINTID_EP0SETUPDONE), - TRACE_STR(STM32L4_TRACEINTID_EP0SETUPSETADDRESS), - TRACE_STR(STM32L4_TRACEINTID_EPGETSTATUS), - TRACE_STR(STM32L4_TRACEINTID_EPINDONE), - TRACE_STR(STM32L4_TRACEINTID_EPINQEMPTY), - TRACE_STR(STM32L4_TRACEINTID_EPOUTDONE), - TRACE_STR(STM32L4_TRACEINTID_EPOUTPENDING), - TRACE_STR(STM32L4_TRACEINTID_EPOUTQEMPTY), - TRACE_STR(STM32L4_TRACEINTID_ESOF), - TRACE_STR(STM32L4_TRACEINTID_GETCONFIG), - TRACE_STR(STM32L4_TRACEINTID_GETSETDESC), - TRACE_STR(STM32L4_TRACEINTID_GETSETIF), - TRACE_STR(STM32L4_TRACEINTID_GETSTATUS), - TRACE_STR(STM32L4_TRACEINTID_IFGETSTATUS), - TRACE_STR(STM32L4_TRACEINTID_USBCTR), - TRACE_STR(STM32L4_TRACEINTID_USBINTERRUPT), - TRACE_STR(STM32L4_TRACEINTID_NOSTDREQ), - TRACE_STR(STM32L4_TRACEINTID_RESET), - TRACE_STR(STM32L4_TRACEINTID_SETCONFIG), - TRACE_STR(STM32L4_TRACEINTID_SETFEATURE), - TRACE_STR(STM32L4_TRACEINTID_SUSP), - TRACE_STR(STM32L4_TRACEINTID_SYNCHFRAME), - TRACE_STR(STM32L4_TRACEINTID_WKUP), - TRACE_STR(STM32L4_TRACEINTID_EP0SETUPOUT), - TRACE_STR(STM32L4_TRACEINTID_EP0SETUPOUTDATA), + TRACE_STR(STM32_TRACEINTID_CLEARFEATURE), + TRACE_STR(STM32_TRACEINTID_DEVGETSTATUS), + TRACE_STR(STM32_TRACEINTID_DISPATCH), + TRACE_STR(STM32_TRACEINTID_EP0IN), + TRACE_STR(STM32_TRACEINTID_EP0INDONE), + TRACE_STR(STM32_TRACEINTID_EP0OUTDONE), + TRACE_STR(STM32_TRACEINTID_EP0SETUPDONE), + TRACE_STR(STM32_TRACEINTID_EP0SETUPSETADDRESS), + TRACE_STR(STM32_TRACEINTID_EPGETSTATUS), + TRACE_STR(STM32_TRACEINTID_EPINDONE), + TRACE_STR(STM32_TRACEINTID_EPINQEMPTY), + TRACE_STR(STM32_TRACEINTID_EPOUTDONE), + TRACE_STR(STM32_TRACEINTID_EPOUTPENDING), + TRACE_STR(STM32_TRACEINTID_EPOUTQEMPTY), + TRACE_STR(STM32_TRACEINTID_ESOF), + TRACE_STR(STM32_TRACEINTID_GETCONFIG), + TRACE_STR(STM32_TRACEINTID_GETSETDESC), + TRACE_STR(STM32_TRACEINTID_GETSETIF), + TRACE_STR(STM32_TRACEINTID_GETSTATUS), + TRACE_STR(STM32_TRACEINTID_IFGETSTATUS), + TRACE_STR(STM32_TRACEINTID_USBCTR), + TRACE_STR(STM32_TRACEINTID_USBINTERRUPT), + TRACE_STR(STM32_TRACEINTID_NOSTDREQ), + TRACE_STR(STM32_TRACEINTID_RESET), + TRACE_STR(STM32_TRACEINTID_SETCONFIG), + TRACE_STR(STM32_TRACEINTID_SETFEATURE), + TRACE_STR(STM32_TRACEINTID_SUSP), + TRACE_STR(STM32_TRACEINTID_SYNCHFRAME), + TRACE_STR(STM32_TRACEINTID_WKUP), + TRACE_STR(STM32_TRACEINTID_EP0SETUPOUT), + TRACE_STR(STM32_TRACEINTID_EP0SETUPOUTDATA), TRACE_STR_END }; #endif @@ -579,33 +579,33 @@ const struct trace_msg_t g_usb_trace_strings_intdecode[] = #ifdef CONFIG_USBDEV_TRACE_STRINGS const struct trace_msg_t g_usb_trace_strings_deverror[] = { - TRACE_STR(STM32L4_TRACEERR_ALLOCFAIL), - TRACE_STR(STM32L4_TRACEERR_BADCLEARFEATURE), - TRACE_STR(STM32L4_TRACEERR_BADDEVGETSTATUS), - TRACE_STR(STM32L4_TRACEERR_BADEPGETSTATUS), - TRACE_STR(STM32L4_TRACEERR_BADEPNO), - TRACE_STR(STM32L4_TRACEERR_BADEPTYPE), - TRACE_STR(STM32L4_TRACEERR_BADGETCONFIG), - TRACE_STR(STM32L4_TRACEERR_BADGETSETDESC), - TRACE_STR(STM32L4_TRACEERR_BADGETSTATUS), - TRACE_STR(STM32L4_TRACEERR_BADSETADDRESS), - TRACE_STR(STM32L4_TRACEERR_BADSETCONFIG), - TRACE_STR(STM32L4_TRACEERR_BADSETFEATURE), - TRACE_STR(STM32L4_TRACEERR_BINDFAILED), - TRACE_STR(STM32L4_TRACEERR_DISPATCHSTALL), - TRACE_STR(STM32L4_TRACEERR_DRIVER), - TRACE_STR(STM32L4_TRACEERR_DRIVERREGISTERED), - TRACE_STR(STM32L4_TRACEERR_EP0BADCTR), - TRACE_STR(STM32L4_TRACEERR_EP0SETUPSTALLED), - TRACE_STR(STM32L4_TRACEERR_EPBUFFER), - TRACE_STR(STM32L4_TRACEERR_EPDISABLED), - TRACE_STR(STM32L4_TRACEERR_EPOUTNULLPACKET), - TRACE_STR(STM32L4_TRACEERR_EPRESERVE), - TRACE_STR(STM32L4_TRACEERR_INVALIDCTRLREQ), - TRACE_STR(STM32L4_TRACEERR_INVALIDPARMS), - TRACE_STR(STM32L4_TRACEERR_IRQREGISTRATION), - TRACE_STR(STM32L4_TRACEERR_NOTCONFIGURED), - TRACE_STR(STM32L4_TRACEERR_REQABORTED), + TRACE_STR(STM32_TRACEERR_ALLOCFAIL), + TRACE_STR(STM32_TRACEERR_BADCLEARFEATURE), + TRACE_STR(STM32_TRACEERR_BADDEVGETSTATUS), + TRACE_STR(STM32_TRACEERR_BADEPGETSTATUS), + TRACE_STR(STM32_TRACEERR_BADEPNO), + TRACE_STR(STM32_TRACEERR_BADEPTYPE), + TRACE_STR(STM32_TRACEERR_BADGETCONFIG), + TRACE_STR(STM32_TRACEERR_BADGETSETDESC), + TRACE_STR(STM32_TRACEERR_BADGETSTATUS), + TRACE_STR(STM32_TRACEERR_BADSETADDRESS), + TRACE_STR(STM32_TRACEERR_BADSETCONFIG), + TRACE_STR(STM32_TRACEERR_BADSETFEATURE), + TRACE_STR(STM32_TRACEERR_BINDFAILED), + TRACE_STR(STM32_TRACEERR_DISPATCHSTALL), + TRACE_STR(STM32_TRACEERR_DRIVER), + TRACE_STR(STM32_TRACEERR_DRIVERREGISTERED), + TRACE_STR(STM32_TRACEERR_EP0BADCTR), + TRACE_STR(STM32_TRACEERR_EP0SETUPSTALLED), + TRACE_STR(STM32_TRACEERR_EPBUFFER), + TRACE_STR(STM32_TRACEERR_EPDISABLED), + TRACE_STR(STM32_TRACEERR_EPOUTNULLPACKET), + TRACE_STR(STM32_TRACEERR_EPRESERVE), + TRACE_STR(STM32_TRACEERR_INVALIDCTRLREQ), + TRACE_STR(STM32_TRACEERR_INVALIDPARMS), + TRACE_STR(STM32_TRACEERR_IRQREGISTRATION), + TRACE_STR(STM32_TRACEERR_NOTCONFIGURED), + TRACE_STR(STM32_TRACEERR_REQABORTED), TRACE_STR_END }; #endif @@ -615,11 +615,11 @@ const struct trace_msg_t g_usb_trace_strings_deverror[] = ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_getreg + * Name: stm32_getreg ****************************************************************************/ -#ifdef CONFIG_STM32L4_USBDEV_REGDEBUG -static uint16_t stm32l4_getreg(uint32_t addr) +#ifdef CONFIG_STM32_USBDEV_REGDEBUG +static uint16_t stm32_getreg(uint32_t addr) { static uint32_t prevaddr = 0; static uint16_t preval = 0; @@ -674,11 +674,11 @@ static uint16_t stm32l4_getreg(uint32_t addr) #endif /**************************************************************************** - * Name: stm32l4_putreg + * Name: stm32_putreg ****************************************************************************/ -#ifdef CONFIG_STM32L4_USBDEV_REGDEBUG -static void stm32l4_putreg(uint16_t val, uint32_t addr) +#ifdef CONFIG_STM32_USBDEV_REGDEBUG +static void stm32_putreg(uint16_t val, uint32_t addr) { /* Show the register value being written */ @@ -691,58 +691,58 @@ static void stm32l4_putreg(uint16_t val, uint32_t addr) #endif /**************************************************************************** - * Name: stm32l4_dumpep + * Name: stm32_dumpep ****************************************************************************/ -#ifdef CONFIG_STM32L4_USBDEV_REGDEBUG -static void stm32l4_dumpep(int epno) +#ifdef CONFIG_STM32_USBDEV_REGDEBUG +static void stm32_dumpep(int epno) { uint32_t addr; /* Common registers */ - uinfo("CNTR: %04x\n", getreg16(STM32L4_USB_CNTR)); - uinfo("ISTR: %04x\n", getreg16(STM32L4_USB_ISTR)); - uinfo("FNR: %04x\n", getreg16(STM32L4_USB_FNR)); - uinfo("DADDR: %04x\n", getreg16(STM32L4_USB_DADDR)); - uinfo("BTABLE: %04x\n", getreg16(STM32L4_USB_BTABLE)); + uinfo("CNTR: %04x\n", getreg16(STM32_USB_CNTR)); + uinfo("ISTR: %04x\n", getreg16(STM32_USB_ISTR)); + uinfo("FNR: %04x\n", getreg16(STM32_USB_FNR)); + uinfo("DADDR: %04x\n", getreg16(STM32_USB_DADDR)); + uinfo("BTABLE: %04x\n", getreg16(STM32_USB_BTABLE)); /* Endpoint register */ - addr = STM32L4_USB_EPR(epno); + addr = STM32_USB_EPR(epno); uinfo("EPR%d: [%08" PRIx32 "] %04x\n", epno, addr, getreg16(addr)); /* Endpoint descriptor */ - addr = STM32L4_USB_BTABLE_ADDR(epno, 0); + addr = STM32_USB_BTABLE_ADDR(epno, 0); uinfo("DESC: %08" PRIx32 "\n", addr); /* Endpoint buffer descriptor */ - addr = STM32L4_USB_ADDR_TX(epno); + addr = STM32_USB_ADDR_TX(epno); uinfo(" TX ADDR: [%08" PRIx32 "] %04x\n", addr, getreg16(addr)); - addr = STM32L4_USB_COUNT_TX(epno); + addr = STM32_USB_COUNT_TX(epno); uinfo(" COUNT: [%08" PRIx32 "] %04x\n", addr, getreg16(addr)); - addr = STM32L4_USB_ADDR_RX(epno); + addr = STM32_USB_ADDR_RX(epno); uinfo(" RX ADDR: [%08" PRIx32 "] %04x\n", addr, getreg16(addr)); - addr = STM32L4_USB_COUNT_RX(epno); + addr = STM32_USB_COUNT_RX(epno); uinfo(" COUNT: [%08" PRIx32 "] %04x\n", addr, getreg16(addr)); } #endif /**************************************************************************** - * Name: stm32l4_checksetup + * Name: stm32_checksetup ****************************************************************************/ -#ifdef CONFIG_STM32L4_USBDEV_REGDEBUG -static void stm32l4_checksetup(void) +#ifdef CONFIG_STM32_USBDEV_REGDEBUG +static void stm32_checksetup(void) { - uint32_t cfgr = getreg32(STM32L4_RCC_CFGR); - uint32_t apb1rstr = getreg32(STM32L4_RCC_APB1RSTR1); - uint32_t apb1enr = getreg32(STM32L4_RCC_APB1ENR1); + uint32_t cfgr = getreg32(STM32_RCC_CFGR); + uint32_t apb1rstr = getreg32(STM32_RCC_APB1RSTR1); + uint32_t apb1enr = getreg32(STM32_RCC_APB1ENR1); uinfo("CFGR: %08" PRIx32 " APB1RSTR1: %08" PRIx32 " APB1ENR1: %08" PRIx32 "\n", cfgr, apb1rstr, @@ -757,42 +757,42 @@ static void stm32l4_checksetup(void) #endif /**************************************************************************** - * Name: stm32l4_seteptxcount + * Name: stm32_seteptxcount ****************************************************************************/ -static inline void stm32l4_seteptxcount(uint8_t epno, uint16_t count) +static inline void stm32_seteptxcount(uint8_t epno, uint16_t count) { - volatile uint16_t *epaddr = (uint16_t *)STM32L4_USB_COUNT_TX(epno); + volatile uint16_t *epaddr = (uint16_t *)STM32_USB_COUNT_TX(epno); *epaddr = count; } /**************************************************************************** - * Name: stm32l4_seteptxaddr + * Name: stm32_seteptxaddr ****************************************************************************/ -static inline void stm32l4_seteptxaddr(uint8_t epno, uint16_t addr) +static inline void stm32_seteptxaddr(uint8_t epno, uint16_t addr) { - volatile uint16_t *txaddr = (uint16_t *)STM32L4_USB_ADDR_TX(epno); + volatile uint16_t *txaddr = (uint16_t *)STM32_USB_ADDR_TX(epno); *txaddr = addr; } /**************************************************************************** - * Name: stm32l4_geteptxaddr + * Name: stm32_geteptxaddr ****************************************************************************/ -static inline uint16_t stm32l4_geteptxaddr(uint8_t epno) +static inline uint16_t stm32_geteptxaddr(uint8_t epno) { - volatile uint16_t *txaddr = (uint16_t *)STM32L4_USB_ADDR_TX(epno); + volatile uint16_t *txaddr = (uint16_t *)STM32_USB_ADDR_TX(epno); return (uint16_t)*txaddr; } /**************************************************************************** - * Name: stm32l4_seteprxcount + * Name: stm32_seteprxcount ****************************************************************************/ -static void stm32l4_seteprxcount(uint8_t epno, uint16_t count) +static void stm32_seteprxcount(uint8_t epno, uint16_t count) { - volatile uint16_t *epaddr = (uint16_t *)STM32L4_USB_COUNT_RX(epno); + volatile uint16_t *epaddr = (uint16_t *)STM32_USB_COUNT_RX(epno); uint32_t rxcount = 0; uint16_t nblocks; @@ -836,74 +836,74 @@ static void stm32l4_seteprxcount(uint8_t epno, uint16_t count) } /**************************************************************************** - * Name: stm32l4_geteprxcount + * Name: stm32_geteprxcount ****************************************************************************/ -static inline uint16_t stm32l4_geteprxcount(uint8_t epno) +static inline uint16_t stm32_geteprxcount(uint8_t epno) { - volatile uint16_t *epaddr = (uint16_t *)STM32L4_USB_COUNT_RX(epno); + volatile uint16_t *epaddr = (uint16_t *)STM32_USB_COUNT_RX(epno); return (*epaddr) & USB_COUNT_RX_MASK; } /**************************************************************************** - * Name: stm32l4_seteprxaddr + * Name: stm32_seteprxaddr ****************************************************************************/ -static inline void stm32l4_seteprxaddr(uint8_t epno, uint16_t addr) +static inline void stm32_seteprxaddr(uint8_t epno, uint16_t addr) { - volatile uint16_t *rxaddr = (uint16_t *)STM32L4_USB_ADDR_RX(epno); + volatile uint16_t *rxaddr = (uint16_t *)STM32_USB_ADDR_RX(epno); *rxaddr = addr; } /**************************************************************************** - * Name: stm32l4_seteprxaddr + * Name: stm32_seteprxaddr ****************************************************************************/ -static inline uint16_t stm32l4_geteprxaddr(uint8_t epno) +static inline uint16_t stm32_geteprxaddr(uint8_t epno) { - volatile uint16_t *rxaddr = (uint16_t *)STM32L4_USB_ADDR_RX(epno); + volatile uint16_t *rxaddr = (uint16_t *)STM32_USB_ADDR_RX(epno); return (uint16_t)*rxaddr; } /**************************************************************************** - * Name: stm32l4_setepaddress + * Name: stm32_setepaddress ****************************************************************************/ -static inline void stm32l4_setepaddress(uint8_t epno, uint16_t addr) +static inline void stm32_setepaddress(uint8_t epno, uint16_t addr) { - uint32_t epaddr = STM32L4_USB_EPR(epno); + uint32_t epaddr = STM32_USB_EPR(epno); uint16_t regval; - regval = stm32l4_getreg(epaddr); + regval = stm32_getreg(epaddr); regval &= EPR_NOTOG_MASK; regval &= ~USB_EPR_EA_MASK; regval |= (addr << USB_EPR_EA_SHIFT); - stm32l4_putreg(regval, epaddr); + stm32_putreg(regval, epaddr); } /**************************************************************************** - * Name: stm32l4_seteptype + * Name: stm32_seteptype ****************************************************************************/ -static inline void stm32l4_seteptype(uint8_t epno, uint16_t type) +static inline void stm32_seteptype(uint8_t epno, uint16_t type) { - uint32_t epaddr = STM32L4_USB_EPR(epno); + uint32_t epaddr = STM32_USB_EPR(epno); uint16_t regval; - regval = stm32l4_getreg(epaddr); + regval = stm32_getreg(epaddr); regval &= EPR_NOTOG_MASK; regval &= ~USB_EPR_EPTYPE_MASK; regval |= type; - stm32l4_putreg(regval, epaddr); + stm32_putreg(regval, epaddr); } /**************************************************************************** - * Name: stm32l4_setstatusout + * Name: stm32_setstatusout ****************************************************************************/ -static inline void stm32l4_setstatusout(uint8_t epno) +static inline void stm32_setstatusout(uint8_t epno) { - uint32_t epaddr = STM32L4_USB_EPR(epno); + uint32_t epaddr = STM32_USB_EPR(epno); uint16_t regval; /* For a BULK endpoint the EP_KIND bit is used to enabled double buffering; @@ -911,19 +911,19 @@ static inline void stm32l4_setstatusout(uint8_t epno) * transaction is expected. The bit is not used with out endpoint types. */ - regval = stm32l4_getreg(epaddr); + regval = stm32_getreg(epaddr); regval &= EPR_NOTOG_MASK; regval |= USB_EPR_EP_KIND; - stm32l4_putreg(regval, epaddr); + stm32_putreg(regval, epaddr); } /**************************************************************************** - * Name: stm32l4_clrstatusout + * Name: stm32_clrstatusout ****************************************************************************/ -static inline void stm32l4_clrstatusout(uint8_t epno) +static inline void stm32_clrstatusout(uint8_t epno) { - uint32_t epaddr = STM32L4_USB_EPR(epno); + uint32_t epaddr = STM32_USB_EPR(epno); uint16_t regval; /* For a BULK endpoint the EP_KIND bit is used to enabled double buffering; @@ -931,104 +931,104 @@ static inline void stm32l4_clrstatusout(uint8_t epno) * transaction is expected. The bit is not used with out endpoint types. */ - regval = stm32l4_getreg(epaddr); + regval = stm32_getreg(epaddr); regval &= EPR_NOTOG_MASK; regval &= ~USB_EPR_EP_KIND; - stm32l4_putreg(regval, epaddr); + stm32_putreg(regval, epaddr); } /**************************************************************************** - * Name: stm32l4_clrrxdtog + * Name: stm32_clrrxdtog ****************************************************************************/ -static void stm32l4_clrrxdtog(uint8_t epno) +static void stm32_clrrxdtog(uint8_t epno) { - uint32_t epaddr = STM32L4_USB_EPR(epno); + uint32_t epaddr = STM32_USB_EPR(epno); uint16_t regval; - regval = stm32l4_getreg(epaddr); + regval = stm32_getreg(epaddr); if ((regval & USB_EPR_DTOG_RX) != 0) { regval &= EPR_NOTOG_MASK; regval |= USB_EPR_DTOG_RX; - stm32l4_putreg(regval, epaddr); + stm32_putreg(regval, epaddr); } } /**************************************************************************** - * Name: stm32l4_clrtxdtog + * Name: stm32_clrtxdtog ****************************************************************************/ -static void stm32l4_clrtxdtog(uint8_t epno) +static void stm32_clrtxdtog(uint8_t epno) { - uint32_t epaddr = STM32L4_USB_EPR(epno); + uint32_t epaddr = STM32_USB_EPR(epno); uint16_t regval; - regval = stm32l4_getreg(epaddr); + regval = stm32_getreg(epaddr); if ((regval & USB_EPR_DTOG_TX) != 0) { regval &= EPR_NOTOG_MASK; regval |= USB_EPR_DTOG_TX; - stm32l4_putreg(regval, epaddr); + stm32_putreg(regval, epaddr); } } /**************************************************************************** - * Name: stm32l4_clrepctrrx + * Name: stm32_clrepctrrx ****************************************************************************/ -static void stm32l4_clrepctrrx(uint8_t epno) +static void stm32_clrepctrrx(uint8_t epno) { - uint32_t epaddr = STM32L4_USB_EPR(epno); + uint32_t epaddr = STM32_USB_EPR(epno); uint16_t regval; - regval = stm32l4_getreg(epaddr); + regval = stm32_getreg(epaddr); regval &= EPR_NOTOG_MASK; regval &= ~USB_EPR_CTR_RX; - stm32l4_putreg(regval, epaddr); + stm32_putreg(regval, epaddr); } /**************************************************************************** - * Name: stm32l4_clrepctrtx + * Name: stm32_clrepctrtx ****************************************************************************/ -static void stm32l4_clrepctrtx(uint8_t epno) +static void stm32_clrepctrtx(uint8_t epno) { - uint32_t epaddr = STM32L4_USB_EPR(epno); + uint32_t epaddr = STM32_USB_EPR(epno); uint16_t regval; - regval = stm32l4_getreg(epaddr); + regval = stm32_getreg(epaddr); regval &= EPR_NOTOG_MASK; regval &= ~USB_EPR_CTR_TX; - stm32l4_putreg(regval, epaddr); + stm32_putreg(regval, epaddr); } /**************************************************************************** - * Name: stm32l4_geteptxstatus + * Name: stm32_geteptxstatus ****************************************************************************/ -static inline uint16_t stm32l4_geteptxstatus(uint8_t epno) +static inline uint16_t stm32_geteptxstatus(uint8_t epno) { - return (uint16_t)(stm32l4_getreg(STM32L4_USB_EPR(epno)) & + return (uint16_t)(stm32_getreg(STM32_USB_EPR(epno)) & USB_EPR_STATTX_MASK); } /**************************************************************************** - * Name: stm32l4_geteprxstatus + * Name: stm32_geteprxstatus ****************************************************************************/ -static inline uint16_t stm32l4_geteprxstatus(uint8_t epno) +static inline uint16_t stm32_geteprxstatus(uint8_t epno) { - return (stm32l4_getreg(STM32L4_USB_EPR(epno)) & USB_EPR_STATRX_MASK); + return (stm32_getreg(STM32_USB_EPR(epno)) & USB_EPR_STATRX_MASK); } /**************************************************************************** - * Name: stm32l4_seteptxstatus + * Name: stm32_seteptxstatus ****************************************************************************/ -static void stm32l4_seteptxstatus(uint8_t epno, uint16_t state) +static void stm32_seteptxstatus(uint8_t epno, uint16_t state) { - uint32_t epaddr = STM32L4_USB_EPR(epno); + uint32_t epaddr = STM32_USB_EPR(epno); uint16_t regval; /* The bits in the STAT_TX field can be toggled by software to set their @@ -1036,7 +1036,7 @@ static void stm32l4_seteptxstatus(uint8_t epno, uint16_t state) * value toggles. */ - regval = stm32l4_getreg(epaddr); + regval = stm32_getreg(epaddr); /* The exclusive OR will set STAT_TX bits to 1 if there value is different * from the bits requested in 'state' @@ -1044,16 +1044,16 @@ static void stm32l4_seteptxstatus(uint8_t epno, uint16_t state) regval ^= state; regval &= EPR_TXDTOG_MASK; - stm32l4_putreg(regval, epaddr); + stm32_putreg(regval, epaddr); } /**************************************************************************** - * Name: stm32l4_seteprxstatus + * Name: stm32_seteprxstatus ****************************************************************************/ -static void stm32l4_seteprxstatus(uint8_t epno, uint16_t state) +static void stm32_seteprxstatus(uint8_t epno, uint16_t state) { - uint32_t epaddr = STM32L4_USB_EPR(epno); + uint32_t epaddr = STM32_USB_EPR(epno); uint16_t regval; /* The bits in the STAT_RX field can be toggled by software to set their @@ -1061,7 +1061,7 @@ static void stm32l4_seteprxstatus(uint8_t epno, uint16_t state) * value toggles. */ - regval = stm32l4_getreg(epaddr); + regval = stm32_getreg(epaddr); /* The exclusive OR will set STAT_RX bits to 1 if there value is different * from the bits requested in 'state' @@ -1069,32 +1069,32 @@ static void stm32l4_seteprxstatus(uint8_t epno, uint16_t state) regval ^= state; regval &= EPR_RXDTOG_MASK; - stm32l4_putreg(regval, epaddr); + stm32_putreg(regval, epaddr); } /**************************************************************************** - * Name: stm32l4_eptxstalled + * Name: stm32_eptxstalled ****************************************************************************/ -static inline bool stm32l4_eptxstalled(uint8_t epno) +static inline bool stm32_eptxstalled(uint8_t epno) { - return (stm32l4_geteptxstatus(epno) == USB_EPR_STATTX_STALL); + return (stm32_geteptxstatus(epno) == USB_EPR_STATTX_STALL); } /**************************************************************************** - * Name: stm32l4_eprxstalled + * Name: stm32_eprxstalled ****************************************************************************/ -static inline bool stm32l4_eprxstalled(uint8_t epno) +static inline bool stm32_eprxstalled(uint8_t epno) { - return (stm32l4_geteprxstatus(epno) == USB_EPR_STATRX_STALL); + return (stm32_geteprxstatus(epno) == USB_EPR_STATRX_STALL); } /**************************************************************************** - * Name: stm32l4_copytopma + * Name: stm32_copytopma ****************************************************************************/ -static void stm32l4_copytopma(const uint8_t *buffer, uint16_t pma, +static void stm32_copytopma(const uint8_t *buffer, uint16_t pma, uint16_t nbytes) { volatile uint16_t *dest; @@ -1105,7 +1105,7 @@ static void stm32l4_copytopma(const uint8_t *buffer, uint16_t pma, /* Copy loop. Source=user buffer, Dest=packet memory */ - dest = (volatile uint16_t *)(STM32L4_USB_SRAM_BASE + (uint32_t)pma); + dest = (volatile uint16_t *)(STM32_USB_SRAM_BASE + (uint32_t)pma); for (i = nwords; i != 0; i--) { /* Read two bytes and pack into on 16-bit word */ @@ -1123,11 +1123,11 @@ static void stm32l4_copytopma(const uint8_t *buffer, uint16_t pma, } /**************************************************************************** - * Name: stm32l4_copyfrompma + * Name: stm32_copyfrompma ****************************************************************************/ static inline void -stm32l4_copyfrompma(uint8_t *buffer, uint16_t pma, uint16_t nbytes) +stm32_copyfrompma(uint8_t *buffer, uint16_t pma, uint16_t nbytes) { volatile uint16_t *src; int nwords = (nbytes + 1) >> 1; @@ -1135,7 +1135,7 @@ stm32l4_copyfrompma(uint8_t *buffer, uint16_t pma, uint16_t nbytes) /* Copy loop. Source=packet memory, Dest=user buffer */ - src = (volatile uint16_t *)(STM32L4_USB_SRAM_BASE + (uint32_t)pma); + src = (volatile uint16_t *)(STM32_USB_SRAM_BASE + (uint32_t)pma); for (i = nwords; i != 0; i--) { /* Copy 16-bits from packet memory to user buffer. */ @@ -1151,12 +1151,12 @@ stm32l4_copyfrompma(uint8_t *buffer, uint16_t pma, uint16_t nbytes) } /**************************************************************************** - * Name: stm32l4_rqdequeue + * Name: stm32_rqdequeue ****************************************************************************/ -static struct stm32l4_req_s *stm32l4_rqdequeue(struct stm32l4_ep_s *privep) +static struct stm32_req_s *stm32_rqdequeue(struct stm32_ep_s *privep) { - struct stm32l4_req_s *ret = privep->head; + struct stm32_req_s *ret = privep->head; if (ret) { @@ -1173,11 +1173,11 @@ static struct stm32l4_req_s *stm32l4_rqdequeue(struct stm32l4_ep_s *privep) } /**************************************************************************** - * Name: stm32l4_rqenqueue + * Name: stm32_rqenqueue ****************************************************************************/ -static void stm32l4_rqenqueue(struct stm32l4_ep_s *privep, - struct stm32l4_req_s *req) +static void stm32_rqenqueue(struct stm32_ep_s *privep, + struct stm32_req_s *req) { req->flink = NULL; if (!privep->head) @@ -1193,14 +1193,14 @@ static void stm32l4_rqenqueue(struct stm32l4_ep_s *privep, } /**************************************************************************** - * Name: stm32l4_abortrequest + * Name: stm32_abortrequest ****************************************************************************/ static inline void -stm32l4_abortrequest(struct stm32l4_ep_s *privep, - struct stm32l4_req_s *privreq, int16_t result) +stm32_abortrequest(struct stm32_ep_s *privep, + struct stm32_req_s *privreq, int16_t result) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_REQABORTED), + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_REQABORTED), (uint16_t)USB_EPNO(privep->ep.eplog)); /* Save the result in the request structure */ @@ -1213,18 +1213,18 @@ stm32l4_abortrequest(struct stm32l4_ep_s *privep, } /**************************************************************************** - * Name: stm32l4_reqcomplete + * Name: stm32_reqcomplete ****************************************************************************/ -static void stm32l4_reqcomplete(struct stm32l4_ep_s *privep, int16_t result) +static void stm32_reqcomplete(struct stm32_ep_s *privep, int16_t result) { - struct stm32l4_req_s *privreq; + struct stm32_req_s *privreq; irqstate_t flags; /* Remove the completed request at the head of the endpoint request list */ flags = enter_critical_section(); - privreq = stm32l4_rqdequeue(privep); + privreq = stm32_rqdequeue(privep); leave_critical_section(flags); if (privreq) @@ -1258,8 +1258,8 @@ static void stm32l4_reqcomplete(struct stm32l4_ep_s *privep, int16_t result) * Name: tm32_epwrite ****************************************************************************/ -static void stm32l4_epwrite(struct stm32l4_usbdev_s *priv, - struct stm32l4_ep_s *privep, +static void stm32_epwrite(struct stm32_usbdev_s *priv, + struct stm32_ep_s *privep, const uint8_t *buf, uint32_t nbytes) { uint8_t epno = USB_EPNO(privep->ep.eplog); @@ -1273,12 +1273,12 @@ static void stm32l4_epwrite(struct stm32l4_usbdev_s *priv, * endpoint */ - stm32l4_copytopma(buf, stm32l4_geteptxaddr(epno), nbytes); + stm32_copytopma(buf, stm32_geteptxaddr(epno), nbytes); } /* Send the packet (might be a null packet nbytes == 0) */ - stm32l4_seteptxcount(epno, nbytes); + stm32_seteptxcount(epno, nbytes); priv->txstatus = USB_EPR_STATTX_VALID; /* Indicate that there is data in the TX packet memory. This will be @@ -1289,30 +1289,30 @@ static void stm32l4_epwrite(struct stm32l4_usbdev_s *priv, } /**************************************************************************** - * Name: stm32l4_wrrequest_ep0 + * Name: stm32_wrrequest_ep0 * * Description: * Handle the ep0 state on writes. * ****************************************************************************/ -inline static int stm32l4_wrrequest_ep0(struct stm32l4_usbdev_s *priv, - struct stm32l4_ep_s *privep) +inline static int stm32_wrrequest_ep0(struct stm32_usbdev_s *priv, + struct stm32_ep_s *privep) { int ret; - ret = stm32l4_wrrequest(priv, privep); + ret = stm32_wrrequest(priv, privep); priv->ep0state = ((ret == OK) ? EP0STATE_WRREQUEST : EP0STATE_IDLE); return ret; } /**************************************************************************** - * Name: stm32l4_wrrequest + * Name: stm32_wrrequest ****************************************************************************/ -static int stm32l4_wrrequest(struct stm32l4_usbdev_s *priv, - struct stm32l4_ep_s *privep) +static int stm32_wrrequest(struct stm32_usbdev_s *priv, + struct stm32_ep_s *privep) { - struct stm32l4_req_s *privreq; + struct stm32_req_s *privreq; uint8_t *buf; uint8_t epno; int nbytes; @@ -1326,14 +1326,14 @@ static int stm32l4_wrrequest(struct stm32l4_usbdev_s *priv, /* Check the request from the head of the endpoint request queue */ - privreq = stm32l4_rqpeek(privep); + privreq = stm32_rqpeek(privep); if (!privreq) { /* There is no TX transfer in progress and no new pending TX * requests to send. */ - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_EPINQEMPTY), 0); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPINQEMPTY), 0); return -ENOENT; } @@ -1388,7 +1388,7 @@ static int stm32l4_wrrequest(struct stm32l4_usbdev_s *priv, /* Send the packet (might be a null packet nbytes == 0) */ buf = privreq->req.buf + privreq->req.xfrd; - stm32l4_epwrite(priv, privep, buf, nbytes); + stm32_epwrite(priv, privep, buf, nbytes); /* Update for the next data IN interrupt */ @@ -1406,24 +1406,24 @@ static int stm32l4_wrrequest(struct stm32l4_usbdev_s *priv, usbtrace(TRACE_COMPLETE(USB_EPNO(privep->ep.eplog)), privreq->req.xfrd); privep->txnullpkt = 0; - stm32l4_reqcomplete(privep, OK); + stm32_reqcomplete(privep, OK); } return OK; } /**************************************************************************** - * Name: stm32l4_ep0_rdrequest + * Name: stm32_ep0_rdrequest * * Description: - * This function is called from the stm32l4_ep0out handler when the + * This function is called from the stm32_ep0out handler when the * ep0state is EP0STATE_SETUP_OUT and upon new incoming data is available * in the endpoint 0's buffer. This function will simply copy the OUT data * into ep0data. * ****************************************************************************/ -static inline int stm32l4_ep0_rdrequest(struct stm32l4_usbdev_s *priv) +static inline int stm32_ep0_rdrequest(struct stm32_usbdev_s *priv) { uint32_t src; int pmalen; @@ -1431,7 +1431,7 @@ static inline int stm32l4_ep0_rdrequest(struct stm32l4_usbdev_s *priv) /* Get the number of bytes to read from packet memory */ - pmalen = stm32l4_geteprxcount(EP0); + pmalen = stm32_geteprxcount(EP0); uinfo("EP0: pmalen=%d\n", pmalen); usbtrace(TRACE_READ(EP0), pmalen); @@ -1439,32 +1439,32 @@ static inline int stm32l4_ep0_rdrequest(struct stm32l4_usbdev_s *priv) /* Read the data into our special buffer for SETUP data */ readlen = MIN(CONFIG_USBDEV_SETUP_MAXDATASIZE, pmalen); - src = stm32l4_geteprxaddr(EP0); + src = stm32_geteprxaddr(EP0); /* Receive the next packet */ - stm32l4_copyfrompma(&priv->ep0data[0], src, readlen); + stm32_copyfrompma(&priv->ep0data[0], src, readlen); /* Now we can process the setup command */ priv->ep0state = EP0STATE_SETUP_READY; priv->ep0datlen = readlen; - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_EP0SETUPOUTDATA), readlen); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EP0SETUPOUTDATA), readlen); - stm32l4_ep0setup(priv); + stm32_ep0setup(priv); priv->ep0datlen = 0; /* mark the date consumed */ return OK; } /**************************************************************************** - * Name: stm32l4_rdrequest + * Name: stm32_rdrequest ****************************************************************************/ -static int stm32l4_rdrequest(struct stm32l4_usbdev_s *priv, - struct stm32l4_ep_s *privep) +static int stm32_rdrequest(struct stm32_usbdev_s *priv, + struct stm32_ep_s *privep) { - struct stm32l4_req_s *privreq; + struct stm32_req_s *privreq; uint32_t src; uint8_t *dest; uint8_t epno; @@ -1474,7 +1474,7 @@ static int stm32l4_rdrequest(struct stm32l4_usbdev_s *priv, /* Check the request from the head of the endpoint request queue */ epno = USB_EPNO(privep->ep.eplog); - privreq = stm32l4_rqpeek(privep); + privreq = stm32_rqpeek(privep); if (!privreq) { /* Incoming data available in PMA, but no packet to receive the data. @@ -1482,7 +1482,7 @@ static int stm32l4_rdrequest(struct stm32l4_usbdev_s *priv, * soon. */ - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_EPOUTQEMPTY), epno); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPOUTQEMPTY), epno); return -ENOENT; } @@ -1493,8 +1493,8 @@ static int stm32l4_rdrequest(struct stm32l4_usbdev_s *priv, if (privreq->req.len == 0) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_EPOUTNULLPACKET), 0); - stm32l4_reqcomplete(privep, OK); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EPOUTNULLPACKET), 0); + stm32_reqcomplete(privep, OK); return OK; } @@ -1503,16 +1503,16 @@ static int stm32l4_rdrequest(struct stm32l4_usbdev_s *priv, /* Get the source and destination transfer addresses */ dest = privreq->req.buf + privreq->req.xfrd; - src = stm32l4_geteprxaddr(epno); + src = stm32_geteprxaddr(epno); /* Get the number of bytes to read from packet memory */ - pmalen = stm32l4_geteprxcount(epno); + pmalen = stm32_geteprxcount(epno); readlen = MIN(privreq->req.len, pmalen); /* Receive the next packet */ - stm32l4_copyfrompma(dest, src, readlen); + stm32_copyfrompma(dest, src, readlen); /* If the receive buffer is full or this is a partial packet, * then we are finished with the request buffer). @@ -1524,23 +1524,23 @@ static int stm32l4_rdrequest(struct stm32l4_usbdev_s *priv, /* Return the read request to the class driver. */ usbtrace(TRACE_COMPLETE(epno), privreq->req.xfrd); - stm32l4_reqcomplete(privep, OK); + stm32_reqcomplete(privep, OK); } return OK; } /**************************************************************************** - * Name: stm32l4_cancelrequests + * Name: stm32_cancelrequests ****************************************************************************/ -static void stm32l4_cancelrequests(struct stm32l4_ep_s *privep) +static void stm32_cancelrequests(struct stm32_ep_s *privep) { - while (!stm32l4_rqempty(privep)) + while (!stm32_rqempty(privep)) { usbtrace(TRACE_COMPLETE(USB_EPNO(privep->ep.eplog)), - (stm32l4_rqpeek(privep))->req.xfrd); - stm32l4_reqcomplete(privep, -ESHUTDOWN); + (stm32_rqpeek(privep))->req.xfrd); + stm32_reqcomplete(privep, -ESHUTDOWN); } } @@ -1549,14 +1549,14 @@ static void stm32l4_cancelrequests(struct stm32l4_ep_s *privep) ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_dispatchrequest + * Name: stm32_dispatchrequest ****************************************************************************/ -static void stm32l4_dispatchrequest(struct stm32l4_usbdev_s *priv) +static void stm32_dispatchrequest(struct stm32_usbdev_s *priv) { int ret; - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_DISPATCH), 0); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_DISPATCH), 0); if (priv && priv->driver) { /* Forward to the control request to the class driver implementation */ @@ -1567,24 +1567,24 @@ static void stm32l4_dispatchrequest(struct stm32l4_usbdev_s *priv) { /* Stall on failure */ - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_DISPATCHSTALL), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_DISPATCHSTALL), 0); priv->ep0state = EP0STATE_STALLED; } } } /**************************************************************************** - * Name: stm32l4_epdone + * Name: stm32_epdone ****************************************************************************/ -static void stm32l4_epdone(struct stm32l4_usbdev_s *priv, uint8_t epno) +static void stm32_epdone(struct stm32_usbdev_s *priv, uint8_t epno) { - struct stm32l4_ep_s *privep; + struct stm32_ep_s *privep; uint16_t epr; /* Decode and service non control endpoints interrupt */ - epr = stm32l4_getreg(STM32L4_USB_EPR(epno)); + epr = stm32_getreg(STM32_USB_EPR(epno)); privep = &priv->eplist[epno]; /* OUT: host-to-device @@ -1594,17 +1594,17 @@ static void stm32l4_epdone(struct stm32l4_usbdev_s *priv, uint8_t epno) if ((epr & USB_EPR_CTR_RX) != 0) { - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_EPOUTDONE), epr); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPOUTDONE), epr); /* Handle read requests. First check if a read request is available to * accept the host data. */ - if (!stm32l4_rqempty(privep)) + if (!stm32_rqempty(privep)) { /* Read host data into the current read request */ - stm32l4_rdrequest(priv, privep); + stm32_rdrequest(priv, privep); /* "After the received data is processed, the application software * should set the STAT_RX bits to '11' (Valid) in the USB_EPnR, @@ -1616,9 +1616,9 @@ static void stm32l4_epdone(struct stm32l4_usbdev_s *priv, uint8_t epno) /* NAK further OUT packets if there there no more read requests */ - if (stm32l4_rqempty(privep)) + if (stm32_rqempty(privep)) { - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_EPOUTPENDING), + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPOUTPENDING), (uint16_t)epno); /* Mark the RX processing as pending and NAK any OUT actions @@ -1634,8 +1634,8 @@ static void stm32l4_epdone(struct stm32l4_usbdev_s *priv, uint8_t epno) /* Clear the interrupt status and set the new RX status */ - stm32l4_clrepctrrx(epno); - stm32l4_seteprxstatus(epno, priv->rxstatus); + stm32_clrepctrrx(epno); + stm32_seteprxstatus(epno, priv->rxstatus); } /* IN: device-to-host @@ -1647,59 +1647,59 @@ static void stm32l4_epdone(struct stm32l4_usbdev_s *priv, uint8_t epno) { /* Clear interrupt status */ - stm32l4_clrepctrtx(epno); - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_EPINDONE), epr); + stm32_clrepctrtx(epno); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPINDONE), epr); /* Handle write requests */ priv->txstatus = USB_EPR_STATTX_NAK; if (epno == EP0) { - stm32l4_wrrequest_ep0(priv, privep); + stm32_wrrequest_ep0(priv, privep); } else { - stm32l4_wrrequest(priv, privep); + stm32_wrrequest(priv, privep); } /* Set the new TX status */ - stm32l4_seteptxstatus(epno, priv->txstatus); + stm32_seteptxstatus(epno, priv->txstatus); } } /**************************************************************************** - * Name: stm32l4_setdevaddr + * Name: stm32_setdevaddr ****************************************************************************/ -static void stm32l4_setdevaddr(struct stm32l4_usbdev_s *priv, uint8_t value) +static void stm32_setdevaddr(struct stm32_usbdev_s *priv, uint8_t value) { int epno; /* Set address in every allocated endpoint */ - for (epno = 0; epno < STM32L4_NENDPOINTS; epno++) + for (epno = 0; epno < STM32_NENDPOINTS; epno++) { - if (stm32l4_epreserved(priv, epno)) + if (stm32_epreserved(priv, epno)) { - stm32l4_setepaddress((uint8_t)epno, (uint8_t)epno); + stm32_setepaddress((uint8_t)epno, (uint8_t)epno); } } /* Set the device address and enable function */ - stm32l4_putreg(value | USB_DADDR_EF, STM32L4_USB_DADDR); + stm32_putreg(value | USB_DADDR_EF, STM32_USB_DADDR); } /**************************************************************************** - * Name: stm32l4_ep0setup + * Name: stm32_ep0setup ****************************************************************************/ -static void stm32l4_ep0setup(struct stm32l4_usbdev_s *priv) +static void stm32_ep0setup(struct stm32_usbdev_s *priv) { - struct stm32l4_ep_s *ep0 = &priv->eplist[EP0]; - struct stm32l4_req_s *privreq = stm32l4_rqpeek(ep0); - struct stm32l4_ep_s *privep; + struct stm32_ep_s *ep0 = &priv->eplist[EP0]; + struct stm32_req_s *privreq = stm32_rqpeek(ep0); + struct stm32_ep_s *privep; union wb_u value; union wb_u index; union wb_u len; @@ -1712,7 +1712,7 @@ static void stm32l4_ep0setup(struct stm32l4_usbdev_s *priv) * was a zero-length transfer!) */ - while (!stm32l4_rqempty(ep0)) + while (!stm32_rqempty(ep0)) { int16_t result = OK; if (privreq->req.xfrd != privreq->req.len) @@ -1721,7 +1721,7 @@ static void stm32l4_ep0setup(struct stm32l4_usbdev_s *priv) } usbtrace(TRACE_COMPLETE(ep0->ep.eplog), privreq->req.xfrd); - stm32l4_reqcomplete(ep0, result); + stm32_reqcomplete(ep0, result); } /* Assume NOT stalled; no TX in progress */ @@ -1739,7 +1739,7 @@ static void stm32l4_ep0setup(struct stm32l4_usbdev_s *priv) * request */ - stm32l4_copyfrompma((uint8_t *)&priv->ctrl, stm32l4_geteprxaddr(EP0), + stm32_copyfrompma((uint8_t *)&priv->ctrl, stm32_geteprxaddr(EP0), USB_SIZEOF_CTRLREQ); /* And extract the little-endian 16-bit values to host order */ @@ -1755,7 +1755,7 @@ static void stm32l4_ep0setup(struct stm32l4_usbdev_s *priv) if (USB_REQ_ISOUT(priv->ctrl.type) && len.w > 0) { - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_EP0SETUPOUT), len.w); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EP0SETUPOUT), len.w); /* At this point priv->ctrl is the setup packet. */ @@ -1772,12 +1772,12 @@ static void stm32l4_ep0setup(struct stm32l4_usbdev_s *priv) if ((priv->ctrl.type & USB_REQ_TYPE_MASK) != USB_REQ_TYPE_STANDARD) { - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_NOSTDREQ), + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_NOSTDREQ), priv->ctrl.type); /* Let the class implementation handle all non-standar requests */ - stm32l4_dispatchrequest(priv); + stm32_dispatchrequest(priv); return; } @@ -1795,12 +1795,12 @@ static void stm32l4_ep0setup(struct stm32l4_usbdev_s *priv) * len: 2; data = status */ - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_GETSTATUS), + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_GETSTATUS), priv->ctrl.type); if (len.w != 2 || (priv->ctrl.type & USB_REQ_DIR_IN) == 0 || index.b[MSB] != 0 || value.w != 0) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_BADEPGETSTATUS), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADEPGETSTATUS), 0); priv->ep0state = EP0STATE_STALLED; } else @@ -1810,12 +1810,12 @@ static void stm32l4_ep0setup(struct stm32l4_usbdev_s *priv) case USB_REQ_RECIPIENT_ENDPOINT: { epno = USB_EPNO(index.b[LSB]); - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_EPGETSTATUS), + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPGETSTATUS), epno); - if (epno >= STM32L4_NENDPOINTS) + if (epno >= STM32_NENDPOINTS) { usbtrace(TRACE_DEVERROR( - STM32L4_TRACEERR_BADEPGETSTATUS), + STM32_TRACEERR_BADEPGETSTATUS), epno); priv->ep0state = EP0STATE_STALLED; } @@ -1828,7 +1828,7 @@ static void stm32l4_ep0setup(struct stm32l4_usbdev_s *priv) { /* IN endpoint */ - if (stm32l4_eptxstalled(epno)) + if (stm32_eptxstalled(epno)) { /* IN Endpoint stalled */ @@ -1839,7 +1839,7 @@ static void stm32l4_ep0setup(struct stm32l4_usbdev_s *priv) { /* OUT endpoint */ - if (stm32l4_eprxstalled(epno)) + if (stm32_eprxstalled(epno)) { /* OUT Endpoint stalled */ @@ -1855,7 +1855,7 @@ static void stm32l4_ep0setup(struct stm32l4_usbdev_s *priv) if (index.w == 0) { usbtrace(TRACE_INTDECODE( - STM32L4_TRACEINTID_DEVGETSTATUS), + STM32_TRACEINTID_DEVGETSTATUS), 0); /* Features: Remote Wakeup=YES; selfpowered=? */ @@ -1869,7 +1869,7 @@ static void stm32l4_ep0setup(struct stm32l4_usbdev_s *priv) else { usbtrace(TRACE_DEVERROR( - STM32L4_TRACEERR_BADDEVGETSTATUS), + STM32_TRACEERR_BADDEVGETSTATUS), 0); priv->ep0state = EP0STATE_STALLED; } @@ -1878,7 +1878,7 @@ static void stm32l4_ep0setup(struct stm32l4_usbdev_s *priv) case USB_REQ_RECIPIENT_INTERFACE: { - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_IFGETSTATUS), + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_IFGETSTATUS), 0); response.w = 0; nbytes = 2; /* Response size: 2 bytes */ @@ -1887,7 +1887,7 @@ static void stm32l4_ep0setup(struct stm32l4_usbdev_s *priv) default: { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_BADGETSTATUS), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADGETSTATUS), 0); priv->ep0state = EP0STATE_STALLED; } break; @@ -1904,7 +1904,7 @@ static void stm32l4_ep0setup(struct stm32l4_usbdev_s *priv) * len: zero, data = none */ - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_CLEARFEATURE), + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_CLEARFEATURE), priv->ctrl.type); if ((priv->ctrl.type & USB_REQ_RECIPIENT_MASK) != USB_REQ_RECIPIENT_ENDPOINT) @@ -1913,7 +1913,7 @@ static void stm32l4_ep0setup(struct stm32l4_usbdev_s *priv) * the endpoint recipient) */ - stm32l4_dispatchrequest(priv); + stm32_dispatchrequest(priv); handled = true; } else @@ -1921,16 +1921,16 @@ static void stm32l4_ep0setup(struct stm32l4_usbdev_s *priv) /* Endpoint recipient */ epno = USB_EPNO(index.b[LSB]); - if (epno < STM32L4_NENDPOINTS && index.b[MSB] == 0 && + if (epno < STM32_NENDPOINTS && index.b[MSB] == 0 && value.w == USB_FEATURE_ENDPOINTHALT && len.w == 0) { privep = &priv->eplist[epno]; privep->halted = 0; - stm32l4_epstall(&privep->ep, true); + stm32_epstall(&privep->ep, true); } else { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_BADCLEARFEATURE), + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADCLEARFEATURE), 0); priv->ep0state = EP0STATE_STALLED; } @@ -1946,7 +1946,7 @@ static void stm32l4_ep0setup(struct stm32l4_usbdev_s *priv) * len: 0; data = none */ - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_SETFEATURE), + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SETFEATURE), priv->ctrl.type); if (((priv->ctrl.type & USB_REQ_RECIPIENT_MASK) == USB_REQ_RECIPIENT_DEVICE) && value.w == USB_FEATURE_TESTMODE) @@ -1962,7 +1962,7 @@ static void stm32l4_ep0setup(struct stm32l4_usbdev_s *priv) * endpoint */ - stm32l4_dispatchrequest(priv); + stm32_dispatchrequest(priv); handled = true; } else @@ -1970,16 +1970,16 @@ static void stm32l4_ep0setup(struct stm32l4_usbdev_s *priv) /* Handler recipient=endpoint */ epno = USB_EPNO(index.b[LSB]); - if (epno < STM32L4_NENDPOINTS && index.b[MSB] == 0 && + if (epno < STM32_NENDPOINTS && index.b[MSB] == 0 && value.w == USB_FEATURE_ENDPOINTHALT && len.w == 0) { privep = &priv->eplist[epno]; privep->halted = 1; - stm32l4_epstall(&privep->ep, false); + stm32_epstall(&privep->ep, false); } else { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_BADSETFEATURE), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADSETFEATURE), 0); priv->ep0state = EP0STATE_STALLED; } } @@ -1994,13 +1994,13 @@ static void stm32l4_ep0setup(struct stm32l4_usbdev_s *priv) * len: 0; data = none */ - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_EP0SETUPSETADDRESS), + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EP0SETUPSETADDRESS), value.w); if ((priv->ctrl.type & USB_REQ_RECIPIENT_MASK) != USB_REQ_RECIPIENT_DEVICE || index.w != 0 || len.w != 0 || value.w > 127) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_BADSETADDRESS), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADSETADDRESS), 0); priv->ep0state = EP0STATE_STALLED; } @@ -2026,14 +2026,14 @@ static void stm32l4_ep0setup(struct stm32l4_usbdev_s *priv) */ { - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_GETSETDESC), + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_GETSETDESC), priv->ctrl.type); /* The request seems valid... * let the class implementation handle it */ - stm32l4_dispatchrequest(priv); + stm32_dispatchrequest(priv); handled = true; } break; @@ -2046,7 +2046,7 @@ static void stm32l4_ep0setup(struct stm32l4_usbdev_s *priv) */ { - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_GETCONFIG), + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_GETCONFIG), priv->ctrl.type); if ((priv->ctrl.type & USB_REQ_RECIPIENT_MASK) == USB_REQ_RECIPIENT_DEVICE && @@ -2056,12 +2056,12 @@ static void stm32l4_ep0setup(struct stm32l4_usbdev_s *priv) * let the class implementation handle it */ - stm32l4_dispatchrequest(priv); + stm32_dispatchrequest(priv); handled = true; } else { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_BADGETCONFIG), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADGETCONFIG), 0); priv->ep0state = EP0STATE_STALLED; } } @@ -2075,7 +2075,7 @@ static void stm32l4_ep0setup(struct stm32l4_usbdev_s *priv) */ { - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_SETCONFIG), + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SETCONFIG), priv->ctrl.type); if ((priv->ctrl.type & USB_REQ_RECIPIENT_MASK) == USB_REQ_RECIPIENT_DEVICE && index.w == 0 && len.w == 0) @@ -2084,12 +2084,12 @@ static void stm32l4_ep0setup(struct stm32l4_usbdev_s *priv) * let the class implementation handle it */ - stm32l4_dispatchrequest(priv); + stm32_dispatchrequest(priv); handled = true; } else { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_BADSETCONFIG), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADSETCONFIG), 0); priv->ep0state = EP0STATE_STALLED; } } @@ -2112,9 +2112,9 @@ static void stm32l4_ep0setup(struct stm32l4_usbdev_s *priv) { /* Let the class implementation handle the request */ - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_GETSETIF), + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_GETSETIF), priv->ctrl.type); - stm32l4_dispatchrequest(priv); + stm32_dispatchrequest(priv); handled = true; } break; @@ -2127,13 +2127,13 @@ static void stm32l4_ep0setup(struct stm32l4_usbdev_s *priv) */ { - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_SYNCHFRAME), 0); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SYNCHFRAME), 0); } break; default: { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_INVALIDCTRLREQ), + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDCTRLREQ), priv->ctrl.req); priv->ep0state = EP0STATE_STALLED; } @@ -2171,16 +2171,16 @@ static void stm32l4_ep0setup(struct stm32l4_usbdev_s *priv) /* Send the response (might be a zero-length packet) */ - stm32l4_epwrite(priv, ep0, response.b, nbytes); + stm32_epwrite(priv, ep0, response.b, nbytes); priv->ep0state = EP0STATE_IDLE; } } /**************************************************************************** - * Name: stm32l4_ep0in + * Name: stm32_ep0in ****************************************************************************/ -static void stm32l4_ep0in(struct stm32l4_usbdev_s *priv) +static void stm32_ep0in(struct stm32_usbdev_s *priv) { /* There is no longer anything in the EP0 TX packet memory */ @@ -2192,7 +2192,7 @@ static void stm32l4_ep0in(struct stm32l4_usbdev_s *priv) if (priv->ep0state == EP0STATE_WRREQUEST) { - stm32l4_wrrequest_ep0(priv, &priv->eplist[EP0]); + stm32_wrrequest_ep0(priv, &priv->eplist[EP0]); } /* No.. Are we processing the completion of a status response? */ @@ -2209,7 +2209,7 @@ static void stm32l4_ep0in(struct stm32l4_usbdev_s *priv) { union wb_u value; value.w = GETUINT16(priv->ctrl.value); - stm32l4_setdevaddr(priv, value.b[LSB]); + stm32_setdevaddr(priv, value.b[LSB]); } } else @@ -2219,24 +2219,24 @@ static void stm32l4_ep0in(struct stm32l4_usbdev_s *priv) } /**************************************************************************** - * Name: stm32l4_ep0out + * Name: stm32_ep0out ****************************************************************************/ -static void stm32l4_ep0out(struct stm32l4_usbdev_s *priv) +static void stm32_ep0out(struct stm32_usbdev_s *priv) { int ret; - struct stm32l4_ep_s *privep = &priv->eplist[EP0]; + struct stm32_ep_s *privep = &priv->eplist[EP0]; switch (priv->ep0state) { case EP0STATE_RDREQUEST: /* Read request in progress */ case EP0STATE_IDLE: /* No transfer in progress */ - ret = stm32l4_rdrequest(priv, privep); + ret = stm32_rdrequest(priv, privep); priv->ep0state = ((ret == OK) ? EP0STATE_RDREQUEST : EP0STATE_IDLE); break; case EP0STATE_SETUP_OUT: /* SETUP was waiting for data */ - ret = stm32l4_ep0_rdrequest(priv); /* Off load the data and run the + ret = stm32_ep0_rdrequest(priv); /* Off load the data and run the * last set up command with the * OUT data */ @@ -2259,10 +2259,10 @@ static void stm32l4_ep0out(struct stm32l4_usbdev_s *priv) } /**************************************************************************** - * Name: stm32l4_ep0done + * Name: stm32_ep0done ****************************************************************************/ -static inline void stm32l4_ep0done(struct stm32l4_usbdev_s *priv, +static inline void stm32_ep0done(struct stm32_usbdev_s *priv, uint16_t istr) { uint16_t epr; @@ -2277,8 +2277,8 @@ static inline void stm32l4_ep0done(struct stm32l4_usbdev_s *priv, /* Set both RX and TX status to NAK */ - stm32l4_seteprxstatus(EP0, USB_EPR_STATRX_NAK); - stm32l4_seteptxstatus(EP0, USB_EPR_STATTX_NAK); + stm32_seteprxstatus(EP0, USB_EPR_STATRX_NAK); + stm32_seteptxstatus(EP0, USB_EPR_STATTX_NAK); /* Check the direction bit to determine if this the completion of an EP0 * packet sent to or received from the host PC. @@ -2288,15 +2288,15 @@ static inline void stm32l4_ep0done(struct stm32l4_usbdev_s *priv, { /* EP0 IN: device-to-host (DIR=0) */ - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_EP0IN), istr); - stm32l4_clrepctrtx(EP0); - stm32l4_ep0in(priv); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EP0IN), istr); + stm32_clrepctrtx(EP0); + stm32_ep0in(priv); } else { /* EP0 OUT: host-to-device (DIR=1) */ - epr = stm32l4_getreg(STM32L4_USB_EPR(EP0)); + epr = stm32_getreg(STM32_USB_EPR(EP0)); /* CTR_TX is set when an IN transaction successfully * completes on an endpoint @@ -2304,9 +2304,9 @@ static inline void stm32l4_ep0done(struct stm32l4_usbdev_s *priv, if ((epr & USB_EPR_CTR_TX) != 0) { - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_EP0INDONE), epr); - stm32l4_clrepctrtx(EP0); - stm32l4_ep0in(priv); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EP0INDONE), epr); + stm32_clrepctrtx(EP0); + stm32_ep0in(priv); } /* SETUP is set by the hardware when the last completed @@ -2315,9 +2315,9 @@ static inline void stm32l4_ep0done(struct stm32l4_usbdev_s *priv, else if ((epr & USB_EPR_SETUP) != 0) { - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_EP0SETUPDONE), epr); - stm32l4_clrepctrrx(EP0); - stm32l4_ep0setup(priv); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EP0SETUPDONE), epr); + stm32_clrepctrrx(EP0); + stm32_ep0setup(priv); } /* Set by the hardware when an OUT/SETUP transaction successfully @@ -2326,23 +2326,23 @@ static inline void stm32l4_ep0done(struct stm32l4_usbdev_s *priv, else if ((epr & USB_EPR_CTR_RX) != 0) { - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_EP0OUTDONE), epr); - stm32l4_clrepctrrx(EP0); - stm32l4_ep0out(priv); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EP0OUTDONE), epr); + stm32_clrepctrrx(EP0); + stm32_ep0out(priv); } /* None of the above */ else { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_EP0BADCTR), epr); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EP0BADCTR), epr); return; /* Does this ever happen? */ } } /* Make sure that the EP0 packet size is still OK (superstitious?) */ - stm32l4_seteprxcount(EP0, STM32L4_EP0MAXPACKET); + stm32_seteprxcount(EP0, STM32_EP0MAXPACKET); /* Now figure out the new RX/TX status. Here are all possible * consequences of the above EP0 operations: @@ -2359,7 +2359,7 @@ static inline void stm32l4_ep0done(struct stm32l4_usbdev_s *priv, if (priv->ep0state == EP0STATE_STALLED) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_EP0SETUPSTALLED), + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EP0SETUPSTALLED), priv->ep0state); priv->rxstatus = USB_EPR_STATRX_STALL; priv->txstatus = USB_EPR_STATTX_STALL; @@ -2379,24 +2379,24 @@ static inline void stm32l4_ep0done(struct stm32l4_usbdev_s *priv, /* Now set the new TX and RX status */ - stm32l4_seteprxstatus(EP0, priv->rxstatus); - stm32l4_seteptxstatus(EP0, priv->txstatus); + stm32_seteprxstatus(EP0, priv->rxstatus); + stm32_seteptxstatus(EP0, priv->txstatus); } /**************************************************************************** - * Name: stm32l4_lptransfer + * Name: stm32_lptransfer ****************************************************************************/ -static void stm32l4_lptransfer(struct stm32l4_usbdev_s *priv) +static void stm32_lptransfer(struct stm32_usbdev_s *priv) { uint8_t epno; uint16_t istr; /* Stay in loop while LP interrupts are pending */ - while (((istr = stm32l4_getreg(STM32L4_USB_ISTR)) & USB_ISTR_CTR) != 0) + while (((istr = stm32_getreg(STM32_USB_ISTR)) & USB_ISTR_CTR) != 0) { - stm32l4_putreg((uint16_t)~USB_ISTR_CTR, STM32L4_USB_ISTR); + stm32_putreg((uint16_t)~USB_ISTR_CTR, STM32_USB_ISTR); /* Extract highest priority endpoint number */ @@ -2406,33 +2406,33 @@ static void stm32l4_lptransfer(struct stm32l4_usbdev_s *priv) if (epno == 0) { - stm32l4_ep0done(priv, istr); + stm32_ep0done(priv, istr); } /* Handle other endpoint completion events */ else { - stm32l4_epdone(priv, epno); + stm32_epdone(priv, epno); } } } /**************************************************************************** - * Name: stm32l4_usbinterrupt + * Name: stm32_usbinterrupt ****************************************************************************/ -static int stm32l4_usbinterrupt(int irq, void *context, void *arg) +static int stm32_usbinterrupt(int irq, void *context, void *arg) { /* For now there is only one USB controller, but we will always refer to * it using a pointer to make any future ports to multiple USB controllers * easier. */ - struct stm32l4_usbdev_s *priv = &g_usbdev; - uint16_t istr = stm32l4_getreg(STM32L4_USB_ISTR); + struct stm32_usbdev_s *priv = &g_usbdev; + uint16_t istr = stm32_getreg(STM32_USB_ISTR); - usbtrace(TRACE_INTENTRY(STM32L4_TRACEINTID_USBINTERRUPT), istr); + usbtrace(TRACE_INTENTRY(STM32_TRACEINTID_USBINTERRUPT), istr); /* Handle Reset interrupts. When this event occurs, the peripheral is left * in the same conditions it is left by the system reset (but with the @@ -2443,14 +2443,14 @@ static int stm32l4_usbinterrupt(int irq, void *context, void *arg) { /* Reset interrupt received. Clear the RESET interrupt status. */ - stm32l4_putreg(~USB_ISTR_RESET, STM32L4_USB_ISTR); - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_RESET), istr); + stm32_putreg(~USB_ISTR_RESET, STM32_USB_ISTR); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_RESET), istr); /* Restore our power-up state and exit now because istr is no longer * valid. */ - stm32l4_reset(priv); + stm32_reset(priv); goto out; } @@ -2464,13 +2464,13 @@ static int stm32l4_usbinterrupt(int irq, void *context, void *arg) * cause of the resume is indicated in the FNR register */ - stm32l4_putreg(~USB_ISTR_WKUP, STM32L4_USB_ISTR); - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_WKUP), - stm32l4_getreg(STM32L4_USB_FNR)); + stm32_putreg(~USB_ISTR_WKUP, STM32_USB_ISTR); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_WKUP), + stm32_getreg(STM32_USB_FNR)); /* Perform the wakeup action */ - stm32l4_initresume(priv); + stm32_initresume(priv); priv->rsmstate = RSMSTATE_IDLE; /* Disable ESOF polling, disable the wakeup interrupt, and @@ -2478,52 +2478,52 @@ static int stm32l4_usbinterrupt(int irq, void *context, void *arg) * interrupts. */ - stm32l4_setimask(priv, USB_CNTR_SUSPM, USB_CNTR_ESOFM | + stm32_setimask(priv, USB_CNTR_SUSPM, USB_CNTR_ESOFM | USB_CNTR_WKUPM); - stm32l4_putreg(~USB_CNTR_SUSPM, STM32L4_USB_ISTR); + stm32_putreg(~USB_CNTR_SUSPM, STM32_USB_ISTR); } if ((istr & USB_ISTR_SUSP & priv->imask) != 0) { - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_SUSP), 0); - stm32l4_suspend(priv); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SUSP), 0); + stm32_suspend(priv); /* Clear of the ISTR bit must be done after setting of * USB_CNTR_FSUSP */ - stm32l4_putreg(~USB_ISTR_SUSP, STM32L4_USB_ISTR); + stm32_putreg(~USB_ISTR_SUSP, STM32_USB_ISTR); } if ((istr & USB_ISTR_ESOF & priv->imask) != 0) { - stm32l4_putreg(~USB_ISTR_ESOF, STM32L4_USB_ISTR); + stm32_putreg(~USB_ISTR_ESOF, STM32_USB_ISTR); /* Resume handling timing is made with ESOFs */ - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_ESOF), 0); - stm32l4_esofpoll(priv); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_ESOF), 0); + stm32_esofpoll(priv); } if ((istr & USB_ISTR_CTR & priv->imask) != 0) { /* Low priority endpoint correct transfer interrupt */ - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_USBCTR), istr); - stm32l4_lptransfer(priv); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_USBCTR), istr); + stm32_lptransfer(priv); } out: - usbtrace(TRACE_INTEXIT(STM32L4_TRACEINTID_USBINTERRUPT), - stm32l4_getreg(STM32L4_USB_EP0R)); + usbtrace(TRACE_INTEXIT(STM32_TRACEINTID_USBINTERRUPT), + stm32_getreg(STM32_USB_EP0R)); return OK; } /**************************************************************************** - * Name: stm32l4_setimask + * Name: stm32_setimask ****************************************************************************/ -static void stm32l4_setimask(struct stm32l4_usbdev_s *priv, +static void stm32_setimask(struct stm32_usbdev_s *priv, uint16_t setbits, uint16_t clrbits) { uint16_t regval; @@ -2537,10 +2537,10 @@ static void stm32l4_setimask(struct stm32l4_usbdev_s *priv, * register (Hmmm... who is shadowing whom?) */ - regval = stm32l4_getreg(STM32L4_USB_CNTR); + regval = stm32_getreg(STM32_USB_CNTR); regval &= ~USB_CNTR_ALLINTS; regval |= priv->imask; - stm32l4_putreg(regval, STM32L4_USB_CNTR); + stm32_putreg(regval, STM32_USB_CNTR); } /**************************************************************************** @@ -2548,10 +2548,10 @@ static void stm32l4_setimask(struct stm32l4_usbdev_s *priv, ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_suspend + * Name: stm32_suspend ****************************************************************************/ -static void stm32l4_suspend(struct stm32l4_usbdev_s *priv) +static void stm32_suspend(struct stm32_usbdev_s *priv) { uint16_t regval; @@ -2566,16 +2566,16 @@ static void stm32l4_suspend(struct stm32l4_usbdev_s *priv) * interrupt. Clear any pending WKUP interrupt. */ - stm32l4_setimask(priv, USB_CNTR_WKUPM, USB_CNTR_ESOFM | USB_CNTR_SUSPM); - stm32l4_putreg(~USB_ISTR_WKUP, STM32L4_USB_ISTR); + stm32_setimask(priv, USB_CNTR_WKUPM, USB_CNTR_ESOFM | USB_CNTR_SUSPM); + stm32_putreg(~USB_ISTR_WKUP, STM32_USB_ISTR); /* Set the FSUSP bit in the CNTR register. This activates suspend mode * within the USB peripheral and disables further SUSP interrupts. */ - regval = stm32l4_getreg(STM32L4_USB_CNTR); + regval = stm32_getreg(STM32_USB_CNTR); regval |= USB_CNTR_FSUSP; - stm32l4_putreg(regval, STM32L4_USB_CNTR); + stm32_putreg(regval, STM32_USB_CNTR); /* If we are not a self-powered device, the got to low-power mode */ @@ -2586,23 +2586,23 @@ static void stm32l4_suspend(struct stm32l4_usbdev_s *priv) * able to detect resume activity */ - regval = stm32l4_getreg(STM32L4_USB_CNTR); + regval = stm32_getreg(STM32_USB_CNTR); regval |= USB_CNTR_LPMODE; - stm32l4_putreg(regval, STM32L4_USB_CNTR); + stm32_putreg(regval, STM32_USB_CNTR); } /* Let the board-specific logic know that we have entered the suspend * state */ - stm32l4_usbsuspend((struct usbdev_s *)priv, false); + stm32_usbsuspend((struct usbdev_s *)priv, false); } /**************************************************************************** - * Name: stm32l4_initresume + * Name: stm32_initresume ****************************************************************************/ -static void stm32l4_initresume(struct stm32l4_usbdev_s *priv) +static void stm32_initresume(struct stm32_usbdev_s *priv) { uint16_t regval; @@ -2616,17 +2616,17 @@ static void stm32l4_initresume(struct stm32l4_usbdev_s *priv) * hardware when a WKUP interrupt event occurs). */ - regval = stm32l4_getreg(STM32L4_USB_CNTR); + regval = stm32_getreg(STM32_USB_CNTR); regval &= (~USB_CNTR_LPMODE); - stm32l4_putreg(regval, STM32L4_USB_CNTR); + stm32_putreg(regval, STM32_USB_CNTR); /* Restore full power -- whatever that means for this particular board */ - stm32l4_usbsuspend((struct usbdev_s *)priv, true); + stm32_usbsuspend((struct usbdev_s *)priv, true); /* Reset FSUSP bit and enable normal interrupt handling */ - stm32l4_putreg(STM32L4_CNTR_SETUP, STM32L4_USB_CNTR); + stm32_putreg(STM32_CNTR_SETUP, STM32_USB_CNTR); /* Notify the class driver of the resume event */ @@ -2637,10 +2637,10 @@ static void stm32l4_initresume(struct stm32l4_usbdev_s *priv) } /**************************************************************************** - * Name: stm32l4_esofpoll + * Name: stm32_esofpoll ****************************************************************************/ -static void stm32l4_esofpoll(struct stm32l4_usbdev_s *priv) +static void stm32_esofpoll(struct stm32_usbdev_s *priv) { uint16_t regval; @@ -2651,9 +2651,9 @@ static void stm32l4_esofpoll(struct stm32l4_usbdev_s *priv) /* One ESOF after internal resume requested */ case RSMSTATE_STARTED: - regval = stm32l4_getreg(STM32L4_USB_CNTR); + regval = stm32_getreg(STM32_USB_CNTR); regval |= USB_CNTR_RESUME; - stm32l4_putreg(regval, STM32L4_USB_CNTR); + stm32_putreg(regval, STM32_USB_CNTR); priv->rsmstate = RSMSTATE_WAITING; priv->nesofs = 10; break; @@ -2666,18 +2666,18 @@ static void stm32l4_esofpoll(struct stm32l4_usbdev_s *priv) { /* Okay.. we are ready to resume normal operation */ - regval = stm32l4_getreg(STM32L4_USB_CNTR); + regval = stm32_getreg(STM32_USB_CNTR); regval &= (~USB_CNTR_RESUME); - stm32l4_putreg(regval, STM32L4_USB_CNTR); + stm32_putreg(regval, STM32_USB_CNTR); priv->rsmstate = RSMSTATE_IDLE; /* Disable ESOF polling, disable the SUSP interrupt, and enable * the WKUP interrupt. Clear any pending WKUP interrupt. */ - stm32l4_setimask(priv, USB_CNTR_WKUPM, USB_CNTR_ESOFM | + stm32_setimask(priv, USB_CNTR_WKUPM, USB_CNTR_ESOFM | USB_CNTR_SUSPM); - stm32l4_putreg(~USB_ISTR_WKUP, STM32L4_USB_ISTR); + stm32_putreg(~USB_ISTR_WKUP, STM32_USB_ISTR); } break; @@ -2693,13 +2693,13 @@ static void stm32l4_esofpoll(struct stm32l4_usbdev_s *priv) ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_epreserve + * Name: stm32_epreserve ****************************************************************************/ -static inline struct stm32l4_ep_s * -stm32l4_epreserve(struct stm32l4_usbdev_s *priv, uint8_t epset) +static inline struct stm32_ep_s * +stm32_epreserve(struct stm32_usbdev_s *priv, uint8_t epset) { - struct stm32l4_ep_s *privep = NULL; + struct stm32_ep_s *privep = NULL; irqstate_t flags; int epndx = 0; @@ -2711,9 +2711,9 @@ stm32l4_epreserve(struct stm32l4_usbdev_s *priv, uint8_t epset) * (skipping EP0) */ - for (epndx = 1; epndx < STM32L4_NENDPOINTS; epndx++) + for (epndx = 1; epndx < STM32_NENDPOINTS; epndx++) { - uint8_t bit = STM32L4_ENDP_BIT(epndx); + uint8_t bit = STM32_ENDP_BIT(epndx); if ((epset & bit) != 0) { /* Mark the endpoint no longer available */ @@ -2733,44 +2733,44 @@ stm32l4_epreserve(struct stm32l4_usbdev_s *priv, uint8_t epset) } /**************************************************************************** - * Name: stm32l4_epunreserve + * Name: stm32_epunreserve ****************************************************************************/ static inline void -stm32l4_epunreserve(struct stm32l4_usbdev_s *priv, - struct stm32l4_ep_s *privep) +stm32_epunreserve(struct stm32_usbdev_s *priv, + struct stm32_ep_s *privep) { irqstate_t flags = enter_critical_section(); - priv->epavail |= STM32L4_ENDP_BIT(USB_EPNO(privep->ep.eplog)); + priv->epavail |= STM32_ENDP_BIT(USB_EPNO(privep->ep.eplog)); leave_critical_section(flags); } /**************************************************************************** - * Name: stm32l4_epreserved + * Name: stm32_epreserved ****************************************************************************/ static inline bool -stm32l4_epreserved(struct stm32l4_usbdev_s *priv, int epno) +stm32_epreserved(struct stm32_usbdev_s *priv, int epno) { - return ((priv->epavail & STM32L4_ENDP_BIT(epno)) == 0); + return ((priv->epavail & STM32_ENDP_BIT(epno)) == 0); } /**************************************************************************** - * Name: stm32l4_epallocpma + * Name: stm32_epallocpma ****************************************************************************/ -static int stm32l4_epallocpma(struct stm32l4_usbdev_s *priv) +static int stm32_epallocpma(struct stm32_usbdev_s *priv) { irqstate_t flags; int bufno = ERROR; int bufndx; flags = enter_critical_section(); - for (bufndx = 2; bufndx < STM32L4_NBUFFERS; bufndx++) + for (bufndx = 2; bufndx < STM32_NBUFFERS; bufndx++) { /* Check if this buffer is available */ - uint8_t bit = STM32L4_BUFFER_BIT(bufndx); + uint8_t bit = STM32_BUFFER_BIT(bufndx); if ((priv->bufavail & bit) != 0) { /* Yes.. Mark the endpoint no longer available */ @@ -2789,14 +2789,14 @@ static int stm32l4_epallocpma(struct stm32l4_usbdev_s *priv) } /**************************************************************************** - * Name: stm32l4_epfreepma + * Name: stm32_epfreepma ****************************************************************************/ static inline void -stm32l4_epfreepma(struct stm32l4_usbdev_s *priv, struct stm32l4_ep_s *privep) +stm32_epfreepma(struct stm32_usbdev_s *priv, struct stm32_ep_s *privep) { irqstate_t flags = enter_critical_section(); - priv->epavail |= STM32L4_ENDP_BIT(privep->bufno); + priv->epavail |= STM32_ENDP_BIT(privep->bufno); leave_critical_section(flags); } @@ -2805,14 +2805,14 @@ stm32l4_epfreepma(struct stm32l4_usbdev_s *priv, struct stm32l4_ep_s *privep) ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_epconfigure + * Name: stm32_epconfigure ****************************************************************************/ -static int stm32l4_epconfigure(struct usbdev_ep_s *ep, +static int stm32_epconfigure(struct usbdev_ep_s *ep, const struct usb_epdesc_s *desc, bool last) { - struct stm32l4_ep_s *privep = (struct stm32l4_ep_s *)ep; + struct stm32_ep_s *privep = (struct stm32_ep_s *)ep; uint16_t pma; uint16_t setting; uint16_t maxpacket; @@ -2821,7 +2821,7 @@ static int stm32l4_epconfigure(struct usbdev_ep_s *ep, #ifdef CONFIG_DEBUG_FEATURES if (!ep || !desc) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_INVALIDPARMS), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); uerr("ERROR: ep=%p desc=%p\n", ep, desc); return -EINVAL; } @@ -2855,22 +2855,22 @@ static int stm32l4_epconfigure(struct usbdev_ep_s *ep, break; default: - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_BADEPTYPE), + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADEPTYPE), (uint16_t)desc->type); return -EINVAL; } - stm32l4_seteptype(epno, setting); + stm32_seteptype(epno, setting); /* Get the address of the PMA buffer allocated for this endpoint */ #warning "REVISIT: Should configure BULK EPs using double buffer feature" - pma = STM32L4_BUFNO2BUF(privep->bufno); + pma = STM32_BUFNO2BUF(privep->bufno); /* Get the maxpacket size of the endpoint. */ maxpacket = GETUINT16(desc->mxpacketsize); - DEBUGASSERT(maxpacket <= STM32L4_MAXPACKET_SIZE); + DEBUGASSERT(maxpacket <= STM32_MAXPACKET_SIZE); ep->maxpacket = maxpacket; /* Get the subset matching the requested direction */ @@ -2883,9 +2883,9 @@ static int stm32l4_epconfigure(struct usbdev_ep_s *ep, /* Set up TX; disable RX */ - stm32l4_seteptxaddr(epno, pma); - stm32l4_seteptxstatus(epno, USB_EPR_STATTX_NAK); - stm32l4_seteprxstatus(epno, USB_EPR_STATRX_DIS); + stm32_seteptxaddr(epno, pma); + stm32_seteptxstatus(epno, USB_EPR_STATTX_NAK); + stm32_seteprxstatus(epno, USB_EPR_STATRX_DIS); } else { @@ -2895,30 +2895,30 @@ static int stm32l4_epconfigure(struct usbdev_ep_s *ep, /* Set up RX; disable TX */ - stm32l4_seteprxaddr(epno, pma); - stm32l4_seteprxcount(epno, maxpacket); - stm32l4_seteprxstatus(epno, USB_EPR_STATRX_VALID); - stm32l4_seteptxstatus(epno, USB_EPR_STATTX_DIS); + stm32_seteprxaddr(epno, pma); + stm32_seteprxcount(epno, maxpacket); + stm32_seteprxstatus(epno, USB_EPR_STATRX_VALID); + stm32_seteptxstatus(epno, USB_EPR_STATTX_DIS); } - stm32l4_dumpep(epno); + stm32_dumpep(epno); return OK; } /**************************************************************************** - * Name: stm32l4_epdisable + * Name: stm32_epdisable ****************************************************************************/ -static int stm32l4_epdisable(struct usbdev_ep_s *ep) +static int stm32_epdisable(struct usbdev_ep_s *ep) { - struct stm32l4_ep_s *privep = (struct stm32l4_ep_s *)ep; + struct stm32_ep_s *privep = (struct stm32_ep_s *)ep; irqstate_t flags; uint8_t epno; #ifdef CONFIG_DEBUG_FEATURES if (!ep) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_INVALIDPARMS), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); uerr("ERROR: ep=%p\n", ep); return -EINVAL; } @@ -2930,60 +2930,60 @@ static int stm32l4_epdisable(struct usbdev_ep_s *ep) /* Cancel any ongoing activity */ flags = enter_critical_section(); - stm32l4_cancelrequests(privep); + stm32_cancelrequests(privep); /* Disable TX; disable RX */ - stm32l4_seteprxcount(epno, 0); - stm32l4_seteprxstatus(epno, USB_EPR_STATRX_DIS); - stm32l4_seteptxstatus(epno, USB_EPR_STATTX_DIS); + stm32_seteprxcount(epno, 0); + stm32_seteprxstatus(epno, USB_EPR_STATRX_DIS); + stm32_seteptxstatus(epno, USB_EPR_STATTX_DIS); leave_critical_section(flags); return OK; } /**************************************************************************** - * Name: stm32l4_epallocreq + * Name: stm32_epallocreq ****************************************************************************/ -static struct usbdev_req_s *stm32l4_epallocreq(struct usbdev_ep_s *ep) +static struct usbdev_req_s *stm32_epallocreq(struct usbdev_ep_s *ep) { - struct stm32l4_req_s *privreq; + struct stm32_req_s *privreq; #ifdef CONFIG_DEBUG_FEATURES if (!ep) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_INVALIDPARMS), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); return NULL; } #endif usbtrace(TRACE_EPALLOCREQ, USB_EPNO(ep->eplog)); - privreq = kmm_malloc(sizeof(struct stm32l4_req_s)); + privreq = kmm_malloc(sizeof(struct stm32_req_s)); if (!privreq) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_ALLOCFAIL), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_ALLOCFAIL), 0); return NULL; } - memset(privreq, 0, sizeof(struct stm32l4_req_s)); + memset(privreq, 0, sizeof(struct stm32_req_s)); return &privreq->req; } /**************************************************************************** - * Name: stm32l4_epfreereq + * Name: stm32_epfreereq ****************************************************************************/ -static void stm32l4_epfreereq(struct usbdev_ep_s *ep, +static void stm32_epfreereq(struct usbdev_ep_s *ep, struct usbdev_req_s *req) { - struct stm32l4_req_s *privreq = (struct stm32l4_req_s *)req; + struct stm32_req_s *privreq = (struct stm32_req_s *)req; #ifdef CONFIG_DEBUG_FEATURES if (!ep || !req) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_INVALIDPARMS), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); return; } #endif @@ -2994,14 +2994,14 @@ static void stm32l4_epfreereq(struct usbdev_ep_s *ep, } /**************************************************************************** - * Name: stm32l4_epsubmit + * Name: stm32_epsubmit ****************************************************************************/ -static int stm32l4_epsubmit(struct usbdev_ep_s *ep, struct usbdev_req_s *req) +static int stm32_epsubmit(struct usbdev_ep_s *ep, struct usbdev_req_s *req) { - struct stm32l4_req_s *privreq = (struct stm32l4_req_s *)req; - struct stm32l4_ep_s *privep = (struct stm32l4_ep_s *)ep; - struct stm32l4_usbdev_s *priv; + struct stm32_req_s *privreq = (struct stm32_req_s *)req; + struct stm32_ep_s *privep = (struct stm32_ep_s *)ep; + struct stm32_usbdev_s *priv; irqstate_t flags; uint8_t epno; int ret = OK; @@ -3009,7 +3009,7 @@ static int stm32l4_epsubmit(struct usbdev_ep_s *ep, struct usbdev_req_s *req) #ifdef CONFIG_DEBUG_FEATURES if (!req || !req->callback || !req->buf || !ep) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_INVALIDPARMS), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); uerr("ERROR: req=%p callback=%p buf=%p ep=%p\n", req, req->callback, req->buf, ep); return -EINVAL; @@ -3022,7 +3022,7 @@ static int stm32l4_epsubmit(struct usbdev_ep_s *ep, struct usbdev_req_s *req) #ifdef CONFIG_DEBUG_FEATURES if (!priv->driver) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_NOTCONFIGURED), + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_NOTCONFIGURED), priv->usbdev.speed); uerr("ERROR: driver=%p\n", priv->driver); return -ESHUTDOWN; @@ -3040,7 +3040,7 @@ static int stm32l4_epsubmit(struct usbdev_ep_s *ep, struct usbdev_req_s *req) if (privep->stalled) { - stm32l4_abortrequest(privep, privreq, -EBUSY); + stm32_abortrequest(privep, privreq, -EBUSY); uerr("ERROR: stalled\n"); ret = -EBUSY; } @@ -3054,7 +3054,7 @@ static int stm32l4_epsubmit(struct usbdev_ep_s *ep, struct usbdev_req_s *req) { /* Add the new request to the request queue for the IN endpoint */ - stm32l4_rqenqueue(privep, privreq); + stm32_rqenqueue(privep, privreq); usbtrace(TRACE_INREQQUEUED(epno), req->len); /* If the IN endpoint FIFO is available, then transfer the data now */ @@ -3064,16 +3064,16 @@ static int stm32l4_epsubmit(struct usbdev_ep_s *ep, struct usbdev_req_s *req) priv->txstatus = USB_EPR_STATTX_NAK; if (epno == EP0) { - ret = stm32l4_wrrequest_ep0(priv, privep); + ret = stm32_wrrequest_ep0(priv, privep); } else { - ret = stm32l4_wrrequest(priv, privep); + ret = stm32_wrrequest(priv, privep); } /* Set the new TX status */ - stm32l4_seteptxstatus(epno, priv->txstatus); + stm32_seteptxstatus(epno, priv->txstatus); } } @@ -3084,7 +3084,7 @@ static int stm32l4_epsubmit(struct usbdev_ep_s *ep, struct usbdev_req_s *req) /* Add the new request to the request queue for the OUT endpoint */ privep->txnullpkt = 0; - stm32l4_rqenqueue(privep, privreq); + stm32_rqenqueue(privep, privreq); usbtrace(TRACE_OUTREQQUEUED(epno), req->len); /* This there a incoming data pending the availability of a request? */ @@ -3099,7 +3099,7 @@ static int stm32l4_epsubmit(struct usbdev_ep_s *ep, struct usbdev_req_s *req) */ priv->rxstatus = USB_EPR_STATRX_VALID; - stm32l4_seteprxstatus(epno, priv->rxstatus); + stm32_seteprxstatus(epno, priv->rxstatus); /* Data is no longer pending */ @@ -3112,18 +3112,18 @@ static int stm32l4_epsubmit(struct usbdev_ep_s *ep, struct usbdev_req_s *req) } /**************************************************************************** - * Name: stm32l4_epcancel + * Name: stm32_epcancel ****************************************************************************/ -static int stm32l4_epcancel(struct usbdev_ep_s *ep, struct usbdev_req_s *req) +static int stm32_epcancel(struct usbdev_ep_s *ep, struct usbdev_req_s *req) { - struct stm32l4_ep_s *privep = (struct stm32l4_ep_s *)ep; + struct stm32_ep_s *privep = (struct stm32_ep_s *)ep; irqstate_t flags; #ifdef CONFIG_DEBUG_USB if (!ep || !req) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_INVALIDPARMS), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); return -EINVAL; } #endif @@ -3131,19 +3131,19 @@ static int stm32l4_epcancel(struct usbdev_ep_s *ep, struct usbdev_req_s *req) usbtrace(TRACE_EPCANCEL, USB_EPNO(ep->eplog)); flags = enter_critical_section(); - stm32l4_cancelrequests(privep); + stm32_cancelrequests(privep); leave_critical_section(flags); return OK; } /**************************************************************************** - * Name: stm32l4_epstall + * Name: stm32_epstall ****************************************************************************/ -static int stm32l4_epstall(struct usbdev_ep_s *ep, bool resume) +static int stm32_epstall(struct usbdev_ep_s *ep, bool resume) { - struct stm32l4_ep_s *privep; - struct stm32l4_usbdev_s *priv; + struct stm32_ep_s *privep; + struct stm32_usbdev_s *priv; uint8_t epno; uint16_t status; irqstate_t flags; @@ -3151,13 +3151,13 @@ static int stm32l4_epstall(struct usbdev_ep_s *ep, bool resume) #ifdef CONFIG_DEBUG_USB if (!ep) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_INVALIDPARMS), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); return -EINVAL; } #endif - privep = (struct stm32l4_ep_s *)ep; - priv = (struct stm32l4_usbdev_s *)privep->dev; + privep = (struct stm32_ep_s *)ep; + priv = (struct stm32_usbdev_s *)privep->dev; epno = USB_EPNO(ep->eplog); /* STALL or RESUME the endpoint */ @@ -3171,16 +3171,16 @@ static int stm32l4_epstall(struct usbdev_ep_s *ep, bool resume) if (USB_ISEPIN(ep->eplog)) { - status = stm32l4_geteptxstatus(epno); + status = stm32_geteptxstatus(epno); } else { - status = stm32l4_geteprxstatus(epno); + status = stm32_geteprxstatus(epno); } if (status == 0) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_EPDISABLED), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EPDISABLED), 0); if (epno == 0) { @@ -3204,32 +3204,32 @@ static int stm32l4_epstall(struct usbdev_ep_s *ep, bool resume) { /* IN endpoint */ - if (stm32l4_eptxstalled(epno)) + if (stm32_eptxstalled(epno)) { - stm32l4_clrtxdtog(epno); + stm32_clrtxdtog(epno); /* Restart any queued write requests */ priv->txstatus = USB_EPR_STATTX_NAK; if (epno == EP0) { - stm32l4_wrrequest_ep0(priv, privep); + stm32_wrrequest_ep0(priv, privep); } else { - stm32l4_wrrequest(priv, privep); + stm32_wrrequest(priv, privep); } /* Set the new TX status */ - stm32l4_seteptxstatus(epno, priv->txstatus); + stm32_seteptxstatus(epno, priv->txstatus); } } else { /* OUT endpoint */ - if (stm32l4_eprxstalled(epno)) + if (stm32_eprxstalled(epno)) { if (epno == EP0) { @@ -3237,15 +3237,15 @@ static int stm32l4_epstall(struct usbdev_ep_s *ep, bool resume) * enable the default endpoint receiver */ - stm32l4_seteprxcount(epno, ep->maxpacket); + stm32_seteprxcount(epno, ep->maxpacket); } else { - stm32l4_clrrxdtog(epno); + stm32_clrrxdtog(epno); } priv->rxstatus = USB_EPR_STATRX_VALID; - stm32l4_seteprxstatus(epno, USB_EPR_STATRX_VALID); + stm32_seteprxstatus(epno, USB_EPR_STATRX_VALID); } } } @@ -3262,14 +3262,14 @@ static int stm32l4_epstall(struct usbdev_ep_s *ep, bool resume) /* IN endpoint */ priv->txstatus = USB_EPR_STATTX_STALL; - stm32l4_seteptxstatus(epno, USB_EPR_STATTX_STALL); + stm32_seteptxstatus(epno, USB_EPR_STATTX_STALL); } else { /* OUT endpoint */ priv->rxstatus = USB_EPR_STATRX_STALL; - stm32l4_seteprxstatus(epno, USB_EPR_STATRX_STALL); + stm32_seteprxstatus(epno, USB_EPR_STATRX_STALL); } } @@ -3282,23 +3282,23 @@ static int stm32l4_epstall(struct usbdev_ep_s *ep, bool resume) ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_allocep + * Name: stm32_allocep ****************************************************************************/ -static struct usbdev_ep_s *stm32l4_allocep(struct usbdev_s *dev, +static struct usbdev_ep_s *stm32_allocep(struct usbdev_s *dev, uint8_t epno, bool in, uint8_t eptype) { - struct stm32l4_usbdev_s *priv = (struct stm32l4_usbdev_s *)dev; - struct stm32l4_ep_s *privep = NULL; - uint8_t epset = STM32L4_ENDP_ALLSET; + struct stm32_usbdev_s *priv = (struct stm32_usbdev_s *)dev; + struct stm32_ep_s *privep = NULL; + uint8_t epset = STM32_ENDP_ALLSET; int bufno; usbtrace(TRACE_DEVALLOCEP, (uint16_t)epno); #ifdef CONFIG_DEBUG_USB if (!dev) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_INVALIDPARMS), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); return NULL; } #endif @@ -3319,9 +3319,9 @@ static struct usbdev_ep_s *stm32l4_allocep(struct usbdev_s *dev, * by the hardware. */ - if (epno >= STM32L4_NENDPOINTS) + if (epno >= STM32_NENDPOINTS) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_BADEPNO), (uint16_t)epno); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADEPNO), (uint16_t)epno); return NULL; } @@ -3330,25 +3330,25 @@ static struct usbdev_ep_s *stm32l4_allocep(struct usbdev_s *dev, * the IN/OUT pair for this logical address. */ - epset = STM32L4_ENDP_BIT(epno); + epset = STM32_ENDP_BIT(epno); } /* Check if the selected endpoint number is available */ - privep = stm32l4_epreserve(priv, epset); + privep = stm32_epreserve(priv, epset); if (!privep) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_EPRESERVE), (uint16_t)epset); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EPRESERVE), (uint16_t)epset); goto errout; } /* Allocate a PMA buffer for this endpoint */ #warning "REVISIT: Should configure BULK EPs using double buffer feature" - bufno = stm32l4_epallocpma(priv); + bufno = stm32_epallocpma(priv); if (bufno < 0) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_EPBUFFER), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EPBUFFER), 0); goto errout_with_ep; } @@ -3356,81 +3356,81 @@ static struct usbdev_ep_s *stm32l4_allocep(struct usbdev_s *dev, return &privep->ep; errout_with_ep: - stm32l4_epunreserve(priv, privep); + stm32_epunreserve(priv, privep); errout: return NULL; } /**************************************************************************** - * Name: stm32l4_freeep + * Name: stm32_freeep ****************************************************************************/ -static void stm32l4_freeep(struct usbdev_s *dev, struct usbdev_ep_s *ep) +static void stm32_freeep(struct usbdev_s *dev, struct usbdev_ep_s *ep) { - struct stm32l4_usbdev_s *priv; - struct stm32l4_ep_s *privep; + struct stm32_usbdev_s *priv; + struct stm32_ep_s *privep; #ifdef CONFIG_DEBUG_USB if (!dev || !ep) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_INVALIDPARMS), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); return; } #endif - priv = (struct stm32l4_usbdev_s *)dev; - privep = (struct stm32l4_ep_s *)ep; + priv = (struct stm32_usbdev_s *)dev; + privep = (struct stm32_ep_s *)ep; usbtrace(TRACE_DEVFREEEP, (uint16_t)USB_EPNO(ep->eplog)); if (priv && privep) { /* Free the PMA buffer assigned to this endpoint */ - stm32l4_epfreepma(priv, privep); + stm32_epfreepma(priv, privep); /* Mark the endpoint as available */ - stm32l4_epunreserve(priv, privep); + stm32_epunreserve(priv, privep); } } /**************************************************************************** - * Name: stm32l4_getframe + * Name: stm32_getframe ****************************************************************************/ -static int stm32l4_getframe(struct usbdev_s *dev) +static int stm32_getframe(struct usbdev_s *dev) { uint16_t fnr; #ifdef CONFIG_DEBUG_USB if (!dev) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_INVALIDPARMS), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); return -EINVAL; } #endif /* Return the last frame number detected by the hardware */ - fnr = stm32l4_getreg(STM32L4_USB_FNR); + fnr = stm32_getreg(STM32_USB_FNR); usbtrace(TRACE_DEVGETFRAME, fnr); return (fnr & USB_FNR_FN_MASK); } /**************************************************************************** - * Name: stm32l4_wakeup + * Name: stm32_wakeup ****************************************************************************/ -static int stm32l4_wakeup(struct usbdev_s *dev) +static int stm32_wakeup(struct usbdev_s *dev) { - struct stm32l4_usbdev_s *priv = (struct stm32l4_usbdev_s *)dev; + struct stm32_usbdev_s *priv = (struct stm32_usbdev_s *)dev; irqstate_t flags; usbtrace(TRACE_DEVWAKEUP, 0); #ifdef CONFIG_DEBUG_USB if (!dev) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_INVALIDPARMS), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); return -EINVAL; } #endif @@ -3440,7 +3440,7 @@ static int stm32l4_wakeup(struct usbdev_s *dev) */ flags = enter_critical_section(); - stm32l4_initresume(priv); + stm32_initresume(priv); priv->rsmstate = RSMSTATE_STARTED; /* Disable the SUSP interrupt (until we are fully resumed), disable @@ -3449,26 +3449,26 @@ static int stm32l4_wakeup(struct usbdev_s *dev) * pending ESOF interrupt. */ - stm32l4_setimask(priv, USB_CNTR_ESOFM, USB_CNTR_WKUPM | USB_CNTR_SUSPM); - stm32l4_putreg(~USB_ISTR_ESOF, STM32L4_USB_ISTR); + stm32_setimask(priv, USB_CNTR_ESOFM, USB_CNTR_WKUPM | USB_CNTR_SUSPM); + stm32_putreg(~USB_ISTR_ESOF, STM32_USB_ISTR); leave_critical_section(flags); return OK; } /**************************************************************************** - * Name: stm32l4_selfpowered + * Name: stm32_selfpowered ****************************************************************************/ -static int stm32l4_selfpowered(struct usbdev_s *dev, bool selfpowered) +static int stm32_selfpowered(struct usbdev_s *dev, bool selfpowered) { - struct stm32l4_usbdev_s *priv = (struct stm32l4_usbdev_s *)dev; + struct stm32_usbdev_s *priv = (struct stm32_usbdev_s *)dev; usbtrace(TRACE_DEVSELFPOWERED, (uint16_t)selfpowered); #ifdef CONFIG_DEBUG_USB if (!dev) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_INVALIDPARMS), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); return -ENODEV; } #endif @@ -3478,10 +3478,10 @@ static int stm32l4_selfpowered(struct usbdev_s *dev, bool selfpowered) } /**************************************************************************** - * Name: stm32l4_pullup + * Name: stm32_pullup ****************************************************************************/ -static int stm32l4_pullup(struct usbdev_s *dev, bool enable) +static int stm32_pullup(struct usbdev_s *dev, bool enable) { uint32_t regval; irqstate_t flags; @@ -3489,7 +3489,7 @@ static int stm32l4_pullup(struct usbdev_s *dev, bool enable) usbtrace(TRACE_DEVPULLUP, (uint16_t)enable); flags = enter_critical_section(); - regval = stm32l4_getreg(STM32L4_USB_BCDR); + regval = stm32_getreg(STM32_USB_BCDR); if (enable) { /* Connect the device by setting the DP pull-up bit in the BCDR @@ -3507,7 +3507,7 @@ static int stm32l4_pullup(struct usbdev_s *dev, bool enable) regval &= ~USB_BCDR_DPPU; } - stm32l4_putreg(regval, STM32L4_USB_BCDR); + stm32_putreg(regval, STM32_USB_BCDR); leave_critical_section(flags); return OK; } @@ -3517,16 +3517,16 @@ static int stm32l4_pullup(struct usbdev_s *dev, bool enable) ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_reset + * Name: stm32_reset ****************************************************************************/ -static void stm32l4_reset(struct stm32l4_usbdev_s *priv) +static void stm32_reset(struct stm32_usbdev_s *priv) { int epno; /* Put the USB controller in reset, disable all interrupts */ - stm32l4_putreg(USB_CNTR_FRES, STM32L4_USB_CNTR); + stm32_putreg(USB_CNTR_FRES, STM32_USB_CNTR); /* Tell the class driver that we are disconnected. The class driver * should then accept any new configurations. @@ -3542,19 +3542,19 @@ static void stm32l4_reset(struct stm32l4_usbdev_s *priv) /* Reset endpoints */ - for (epno = 0; epno < STM32L4_NENDPOINTS; epno++) + for (epno = 0; epno < STM32_NENDPOINTS; epno++) { - struct stm32l4_ep_s *privep = &priv->eplist[epno]; + struct stm32_ep_s *privep = &priv->eplist[epno]; /* Cancel any queued requests. Since they are canceled * with status -ESHUTDOWN, then will not be requeued * until the configuration is reset. NOTE: This should * not be necessary... the CLASS_DISCONNECT above should - * result in the class implementation calling stm32l4_epdisable + * result in the class implementation calling stm32_epdisable * for each of its configured endpoints. */ - stm32l4_cancelrequests(privep); + stm32_cancelrequests(privep); /* Reset endpoint status */ @@ -3566,59 +3566,59 @@ static void stm32l4_reset(struct stm32l4_usbdev_s *priv) /* Re-configure the USB controller in its initial, unconnected state */ - stm32l4_hwreset(priv); + stm32_hwreset(priv); priv->usbdev.speed = USB_SPEED_FULL; } /**************************************************************************** - * Name: stm32l4_hwreset + * Name: stm32_hwreset ****************************************************************************/ -static void stm32l4_hwreset(struct stm32l4_usbdev_s *priv) +static void stm32_hwreset(struct stm32_usbdev_s *priv) { /* Put the USB controller into reset, clear all interrupt enables */ - stm32l4_putreg(USB_CNTR_FRES, STM32L4_USB_CNTR); + stm32_putreg(USB_CNTR_FRES, STM32_USB_CNTR); /* Disable interrupts (and perhaps take the USB controller out of reset) */ priv->imask = 0; - stm32l4_putreg(priv->imask, STM32L4_USB_CNTR); + stm32_putreg(priv->imask, STM32_USB_CNTR); /* Set the STM32 BTABLE address */ - stm32l4_putreg(STM32L4_BTABLE_ADDRESS & 0xfff8, STM32L4_USB_BTABLE); + stm32_putreg(STM32_BTABLE_ADDRESS & 0xfff8, STM32_USB_BTABLE); /* Initialize EP0 */ - stm32l4_seteptype(EP0, USB_EPR_EPTYPE_CONTROL); - stm32l4_seteptxstatus(EP0, USB_EPR_STATTX_NAK); - stm32l4_seteprxaddr(EP0, STM32L4_EP0_RXADDR); - stm32l4_seteprxcount(EP0, STM32L4_EP0MAXPACKET); - stm32l4_seteptxaddr(EP0, STM32L4_EP0_TXADDR); - stm32l4_clrstatusout(EP0); - stm32l4_seteprxstatus(EP0, USB_EPR_STATRX_VALID); + stm32_seteptype(EP0, USB_EPR_EPTYPE_CONTROL); + stm32_seteptxstatus(EP0, USB_EPR_STATTX_NAK); + stm32_seteprxaddr(EP0, STM32_EP0_RXADDR); + stm32_seteprxcount(EP0, STM32_EP0MAXPACKET); + stm32_seteptxaddr(EP0, STM32_EP0_TXADDR); + stm32_clrstatusout(EP0); + stm32_seteprxstatus(EP0, USB_EPR_STATRX_VALID); /* Set the device to respond on default address */ - stm32l4_setdevaddr(priv, 0); + stm32_setdevaddr(priv, 0); /* Clear any pending interrupts */ - stm32l4_putreg(0, STM32L4_USB_ISTR); + stm32_putreg(0, STM32_USB_ISTR); /* Enable interrupts at the USB controller */ - stm32l4_setimask(priv, STM32L4_CNTR_SETUP, - (USB_CNTR_ALLINTS & ~STM32L4_CNTR_SETUP)); - stm32l4_dumpep(EP0); + stm32_setimask(priv, STM32_CNTR_SETUP, + (USB_CNTR_ALLINTS & ~STM32_CNTR_SETUP)); + stm32_dumpep(EP0); } /**************************************************************************** - * Name: stm32l4_hwsetup + * Name: stm32_hwsetup ****************************************************************************/ -static void stm32l4_hwsetup(struct stm32l4_usbdev_s *priv) +static void stm32_hwsetup(struct stm32_usbdev_s *priv) { int epno; @@ -3626,28 +3626,28 @@ static void stm32l4_hwsetup(struct stm32l4_usbdev_s *priv) * all USB interrupts */ - stm32l4_putreg(USB_CNTR_FRES | USB_CNTR_PDWN, STM32L4_USB_CNTR); + stm32_putreg(USB_CNTR_FRES | USB_CNTR_PDWN, STM32_USB_CNTR); /* Disconnect the device / disable the pull-up. We don't want the * host to enumerate us until the class driver is registered. */ - stm32l4_pullup(&priv->usbdev, false); + stm32_pullup(&priv->usbdev, false); /* Initialize the device state structure. NOTE: many fields * have the initial value of zero and, hence, are not explicitly * initialized here. */ - memset(priv, 0, sizeof(struct stm32l4_usbdev_s)); + memset(priv, 0, sizeof(struct stm32_usbdev_s)); priv->usbdev.ops = &g_devops; priv->usbdev.ep0 = &priv->eplist[EP0].ep; - priv->epavail = STM32L4_ENDP_ALLSET & ~STM32L4_ENDP_BIT(EP0); - priv->bufavail = STM32L4_BUFFER_ALLSET & ~STM32L4_BUFFER_EP0; + priv->epavail = STM32_ENDP_ALLSET & ~STM32_ENDP_BIT(EP0); + priv->bufavail = STM32_BUFFER_ALLSET & ~STM32_BUFFER_EP0; /* Initialize the endpoint list */ - for (epno = 0; epno < STM32L4_NENDPOINTS; epno++) + for (epno = 0; epno < STM32_NENDPOINTS; epno++) { /* Set endpoint operations, reference to driver structure (not * really necessary because there is only one controller), and @@ -3664,13 +3664,13 @@ static void stm32l4_hwsetup(struct stm32l4_usbdev_s *priv) * packet size can be selected when the endpoint is configured. */ - priv->eplist[epno].ep.maxpacket = STM32L4_MAXPACKET_SIZE; + priv->eplist[epno].ep.maxpacket = STM32_MAXPACKET_SIZE; } /* Select a smaller endpoint size for EP0 */ -#if STM32L4_EP0MAXPACKET < STM32L4_MAXPACKET_SIZE - priv->eplist[EP0].ep.maxpacket = STM32L4_EP0MAXPACKET; +#if STM32_EP0MAXPACKET < STM32_MAXPACKET_SIZE + priv->eplist[EP0].ep.maxpacket = STM32_EP0MAXPACKET; #endif /* Configure the USB controller. USB uses the following GPIO pins: @@ -3691,33 +3691,33 @@ static void stm32l4_hwsetup(struct stm32l4_usbdev_s *priv) * class driver has been bound. */ - stm32l4_putreg(USB_CNTR_FRES, STM32L4_USB_CNTR); + stm32_putreg(USB_CNTR_FRES, STM32_USB_CNTR); up_mdelay(5); } /**************************************************************************** - * Name: stm32l4_hwshutdown + * Name: stm32_hwshutdown ****************************************************************************/ -static void stm32l4_hwshutdown(struct stm32l4_usbdev_s *priv) +static void stm32_hwshutdown(struct stm32_usbdev_s *priv) { priv->usbdev.speed = USB_SPEED_UNKNOWN; /* Disable all interrupts and force the USB controller into reset */ - stm32l4_putreg(USB_CNTR_FRES, STM32L4_USB_CNTR); + stm32_putreg(USB_CNTR_FRES, STM32_USB_CNTR); /* Clear any pending interrupts */ - stm32l4_putreg(0, STM32L4_USB_ISTR); + stm32_putreg(0, STM32_USB_ISTR); /* Disconnect the device / disable the pull-up */ - stm32l4_pullup(&priv->usbdev, false); + stm32_pullup(&priv->usbdev, false); /* Power down the USB controller */ - stm32l4_putreg(USB_CNTR_FRES | USB_CNTR_PDWN, STM32L4_USB_CNTR); + stm32_putreg(USB_CNTR_FRES | USB_CNTR_PDWN, STM32_USB_CNTR); } /**************************************************************************** @@ -3739,28 +3739,28 @@ void arm_usbinitialize(void) * easier. */ - struct stm32l4_usbdev_s *priv = &g_usbdev; + struct stm32_usbdev_s *priv = &g_usbdev; usbtrace(TRACE_DEVINIT, 0); - stm32l4_checksetup(); + stm32_checksetup(); /* Enable Vbus monitoring in the Power control */ - stm32l4_pwr_enableusv(true); + stm32_pwr_enableusv(true); /* Power up the USB controller, but leave it in the reset state */ - stm32l4_hwsetup(priv); + stm32_hwsetup(priv); /* Attach USB controller interrupt handler. The hardware will not be * initialized and interrupts will not be enabled until the class device * driver is bound. */ - if (irq_attach(STM32L4_IRQ_USB_FS, stm32l4_usbinterrupt, NULL) != 0) + if (irq_attach(STM32_IRQ_USB_FS, stm32_usbinterrupt, NULL) != 0) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_IRQREGISTRATION), - (uint16_t)STM32L4_IRQ_USB_FS); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_IRQREGISTRATION), + (uint16_t)STM32_IRQ_USB_FS); arm_usbuninitialize(); } } @@ -3780,7 +3780,7 @@ void arm_usbuninitialize(void) * easier. */ - struct stm32l4_usbdev_s *priv = &g_usbdev; + struct stm32_usbdev_s *priv = &g_usbdev; irqstate_t flags; flags = enter_critical_section(); @@ -3788,22 +3788,22 @@ void arm_usbuninitialize(void) /* Disable and detach the USB IRQ */ - up_disable_irq(STM32L4_IRQ_USB_FS); - irq_detach(STM32L4_IRQ_USB_FS); + up_disable_irq(STM32_IRQ_USB_FS); + irq_detach(STM32_IRQ_USB_FS); if (priv->driver) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_DRIVERREGISTERED), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_DRIVERREGISTERED), 0); usbdev_unregister(priv->driver); } /* Put the hardware in an inactive state */ - stm32l4_hwshutdown(priv); + stm32_hwshutdown(priv); /* Disable Vbus monitoring in the Power control */ - stm32l4_pwr_enableusv(false); + stm32_pwr_enableusv(false); leave_critical_section(flags); } @@ -3824,7 +3824,7 @@ int usbdev_register(struct usbdevclass_driver_s *driver) * easier. */ - struct stm32l4_usbdev_s *priv = &g_usbdev; + struct stm32_usbdev_s *priv = &g_usbdev; int ret; usbtrace(TRACE_DEVREGISTER, 0); @@ -3833,13 +3833,13 @@ int usbdev_register(struct usbdevclass_driver_s *driver) if (!driver || !driver->ops->bind || !driver->ops->unbind || !driver->ops->disconnect || !driver->ops->setup) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_INVALIDPARMS), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); return -EINVAL; } if (priv->driver) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_DRIVER), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_DRIVER), 0); return -EBUSY; } #endif @@ -3853,7 +3853,7 @@ int usbdev_register(struct usbdevclass_driver_s *driver) ret = CLASS_BIND(driver, &priv->usbdev); if (ret) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_BINDFAILED), (uint16_t)-ret); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BINDFAILED), (uint16_t)-ret); } else { @@ -3861,17 +3861,17 @@ int usbdev_register(struct usbdevclass_driver_s *driver) * the USB controller */ - stm32l4_hwreset(priv); + stm32_hwreset(priv); /* Enable USB controller interrupt at the NVIC */ - up_enable_irq(STM32L4_IRQ_USB_FS); + up_enable_irq(STM32_IRQ_USB_FS); /* Enable pull-up to connect the device. * The host should enumerate us some time after this */ - stm32l4_pullup(&priv->usbdev, true); + stm32_pullup(&priv->usbdev, true); priv->usbdev.speed = USB_SPEED_FULL; } @@ -3896,7 +3896,7 @@ int usbdev_unregister(struct usbdevclass_driver_s *driver) * easier. */ - struct stm32l4_usbdev_s *priv = &g_usbdev; + struct stm32_usbdev_s *priv = &g_usbdev; irqstate_t flags; usbtrace(TRACE_DEVUNREGISTER, 0); @@ -3904,7 +3904,7 @@ int usbdev_unregister(struct usbdevclass_driver_s *driver) #ifdef CONFIG_DEBUG_USB if (driver != priv->driver) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_INVALIDPARMS), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); return -EINVAL; } #endif @@ -3914,7 +3914,7 @@ int usbdev_unregister(struct usbdevclass_driver_s *driver) */ flags = enter_critical_section(); - stm32l4_reset(priv); + stm32_reset(priv); /* Unbind the class driver */ @@ -3922,15 +3922,15 @@ int usbdev_unregister(struct usbdevclass_driver_s *driver) /* Disable USB controller interrupt (but keep attached) */ - up_disable_irq(STM32L4_IRQ_USB_FS); + up_disable_irq(STM32_IRQ_USB_FS); /* Put the hardware in an inactive state. Then bring the hardware back up - * in the reset state (this is probably not necessary, the stm32l4_reset() + * in the reset state (this is probably not necessary, the stm32_reset() * call above was probably sufficient). */ - stm32l4_hwshutdown(priv); - stm32l4_hwsetup(priv); + stm32_hwshutdown(priv); + stm32_hwsetup(priv); /* Unhook the driver */ @@ -3939,4 +3939,4 @@ int usbdev_unregister(struct usbdevclass_driver_s *driver) return OK; } -#endif /* CONFIG_USBDEV && CONFIG_STM32L4_USB */ +#endif /* CONFIG_USBDEV && CONFIG_STM32_USB */ diff --git a/arch/arm/src/stm32l4/stm32l4_usbdev.h b/arch/arm/src/stm32l4/stm32l4_usbdev.h index 97492ddf7d73b..427244a5789af 100644 --- a/arch/arm/src/stm32l4/stm32l4_usbdev.h +++ b/arch/arm/src/stm32l4/stm32l4_usbdev.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32L4_STM32L4_USBDEV_H -#define __ARCH_ARM_SRC_STM32L4_STM32L4_USBDEV_H +#ifndef __ARCH_ARM_SRC_STM32L4_STM32_USBDEV_H +#define __ARCH_ARM_SRC_STM32L4_STM32_USBDEV_H /**************************************************************************** * Included Files @@ -50,17 +50,17 @@ extern "C" #endif /**************************************************************************** - * Name: stm32l4_usbsuspend + * Name: stm32_usbsuspend * * Description: - * Board logic must provide the stm32l4_usbsuspend logic if the USBDEV + * Board logic must provide the stm32_usbsuspend logic if the USBDEV * driver is used. This function is called whenever the USB enters or * leaves suspend mode. This is an opportunity for the board logic to * shutdown clocks, power, etc. while the USB is suspended. * ****************************************************************************/ -void stm32l4_usbsuspend(struct usbdev_s *dev, bool resume); +void stm32_usbsuspend(struct usbdev_s *dev, bool resume); #undef EXTERN #if defined(__cplusplus) @@ -68,4 +68,4 @@ void stm32l4_usbsuspend(struct usbdev_s *dev, bool resume); #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32L4_STM32L4_USBDEV_H */ +#endif /* __ARCH_ARM_SRC_STM32L4_STM32_USBDEV_H */ diff --git a/arch/arm/src/stm32l4/stm32l4_usbhost.h b/arch/arm/src/stm32l4/stm32l4_usbhost.h index f0446e960db93..d38e24247ceda 100644 --- a/arch/arm/src/stm32l4/stm32l4_usbhost.h +++ b/arch/arm/src/stm32l4/stm32l4_usbhost.h @@ -34,11 +34,11 @@ #include "chip.h" -#if defined(CONFIG_STM32L4_OTGFS) && defined(CONFIG_USBHOST) +#if defined(CONFIG_STM32_OTGFS) && defined(CONFIG_USBHOST) -#if defined(CONFIG_STM32L4_STM32L4X5) +#if defined(CONFIG_STM32_STM32L4X5) # include "hardware/stm32l4x5xx_otgfs.h" -#elif defined(CONFIG_STM32L4_STM32L4X6) +#elif defined(CONFIG_STM32_STM32L4X6) # include "hardware/stm32l4x6xx_otgfs.h" #else # error "Unsupported STM32L4 chip" @@ -134,21 +134,21 @@ enum usbhost_trace1codes_e * Pre-requisites * * CONFIG_USBHOST - Enable general USB host support - * CONFIG_STM32L4_OTGFS - Enable the STM32 USB OTG FS block - * CONFIG_STM32L4_SYSCFG - Needed + * CONFIG_STM32_OTGFS - Enable the STM32 USB OTG FS block + * CONFIG_STM32_SYSCFG - Needed * * Options: * - * CONFIG_STM32L4_OTGFS_RXFIFO_SIZE - Size of the RX FIFO in 32-bit words. + * CONFIG_STM32_OTGFS_RXFIFO_SIZE - Size of the RX FIFO in 32-bit words. * Default 128 (512 bytes) - * CONFIG_STM32L4_OTGFS_NPTXFIFO_SIZE - Size of the non-periodic Tx FIFO + * CONFIG_STM32_OTGFS_NPTXFIFO_SIZE - Size of the non-periodic Tx FIFO * in 32-bit words. Default 96 (384 bytes) - * CONFIG_STM32L4_OTGFS_PTXFIFO_SIZE - Size of the periodic Tx FIFO in + * CONFIG_STM32_OTGFS_PTXFIFO_SIZE - Size of the periodic Tx FIFO in * 32-bit words. Default 96 (384 bytes) - * CONFIG_STM32L4_OTGFS_SOFINTR - Enable SOF interrupts. Why would you ever + * CONFIG_STM32_OTGFS_SOFINTR - Enable SOF interrupts. Why would you ever * want to do that? * - * CONFIG_STM32L4_USBHOST_REGDEBUG - Enable very low-level register access + * CONFIG_STM32_USBHOST_REGDEBUG - Enable very low-level register access * debug. Depends on CONFIG_DEBUG. */ @@ -168,7 +168,7 @@ extern "C" #endif /**************************************************************************** - * Name: stm32l4_usbhost_vbusdrive + * Name: stm32_usbhost_vbusdrive * * Description: * Enable/disable driving of VBUS 5V output. This function must be @@ -196,7 +196,7 @@ extern "C" * ****************************************************************************/ -void stm32l4_usbhost_vbusdrive(int iface, bool enable); +void stm32_usbhost_vbusdrive(int iface, bool enable); #undef EXTERN #if defined(__cplusplus) @@ -204,5 +204,5 @@ void stm32l4_usbhost_vbusdrive(int iface, bool enable); #endif #endif /* __ASSEMBLY__ */ -#endif /* CONFIG_STM32L4_OTGFS && CONFIG_USBHOST */ +#endif /* CONFIG_STM32_OTGFS && CONFIG_USBHOST */ #endif /* __ARCH_ARM_SRC_STM32L4_STM32L4_USBHOST_H */ diff --git a/arch/arm/src/stm32l4/stm32l4_usbhost_trace.c b/arch/arm/src/stm32l4/stm32l4_usbhost_trace.c index 178beee45e5e8..8ff1252348072 100644 --- a/arch/arm/src/stm32l4/stm32l4_usbhost_trace.c +++ b/arch/arm/src/stm32l4/stm32l4_usbhost_trace.c @@ -47,7 +47,7 @@ * Private Types ****************************************************************************/ -struct stm32l4_usbhost_trace_s +struct stm32_usbhost_trace_s { #if 0 uint16_t id; @@ -60,7 +60,7 @@ struct stm32l4_usbhost_trace_s * Private Data ****************************************************************************/ -static const struct stm32l4_usbhost_trace_s g_trace1[TRACE1_NSTRINGS] = +static const struct stm32_usbhost_trace_s g_trace1[TRACE1_NSTRINGS] = { TRENTRY(OTGFS_TRACE1_DEVDISCONN, TR_FMT1, "OTGFS ERROR: Host Port %d. Device disconnected\n"), @@ -117,7 +117,7 @@ static const struct stm32l4_usbhost_trace_s g_trace1[TRACE1_NSTRINGS] = #endif }; -static const struct stm32l4_usbhost_trace_s g_trace2[TRACE2_NSTRINGS] = +static const struct stm32_usbhost_trace_s g_trace2[TRACE2_NSTRINGS] = { TRENTRY(OTGFS_TRACE2_CLIP, TR_FMT2, "OTGFS CLIP: chidx: %d buflen: %d\n"), diff --git a/arch/arm/src/stm32l4/stm32l4_userspace.c b/arch/arm/src/stm32l4/stm32l4_userspace.c index e6e181f9e19d9..d23687632538b 100644 --- a/arch/arm/src/stm32l4/stm32l4_userspace.c +++ b/arch/arm/src/stm32l4/stm32l4_userspace.c @@ -41,7 +41,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_userspace + * Name: stm32_userspace * * Description: * For the case of the separate user-/kernel-space build, perform whatever @@ -51,7 +51,7 @@ * ****************************************************************************/ -void stm32l4_userspace(void) +void stm32_userspace(void) { uint8_t *src; uint8_t *dest; @@ -87,7 +87,7 @@ void stm32l4_userspace(void) /* Configure the MPU to permit user-space access to its FLASH and RAM */ - stm32l4_mpuinitialize(); + stm32_mpuinitialize(); } #endif /* CONFIG_BUILD_PROTECTED */ diff --git a/arch/arm/src/stm32l4/stm32l4_userspace.h b/arch/arm/src/stm32l4/stm32l4_userspace.h index f965dc09ffd8d..c1b820bff13e6 100644 --- a/arch/arm/src/stm32l4/stm32l4_userspace.h +++ b/arch/arm/src/stm32l4/stm32l4_userspace.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32L4_STM32L4_USERSPACE_H -#define __ARCH_ARM_SRC_STM32L4_STM32L4_USERSPACE_H +#ifndef __ARCH_ARM_SRC_STM32L4_STM32_USERSPACE_H +#define __ARCH_ARM_SRC_STM32L4_STM32_USERSPACE_H /**************************************************************************** * Included Files @@ -34,7 +34,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_userspace + * Name: stm32_userspace * * Description: * For the case of the separate user-/kernel-space build, perform whatever @@ -45,7 +45,7 @@ ****************************************************************************/ #ifdef CONFIG_BUILD_PROTECTED -void stm32l4_userspace(void); +void stm32_userspace(void); #endif -#endif /* __ARCH_ARM_SRC_STM32L4_STM32L4_USERSPACE_H */ +#endif /* __ARCH_ARM_SRC_STM32L4_STM32_USERSPACE_H */ diff --git a/arch/arm/src/stm32l4/stm32l4_waste.c b/arch/arm/src/stm32l4/stm32l4_waste.c deleted file mode 100644 index 1335005e75b5a..0000000000000 --- a/arch/arm/src/stm32l4/stm32l4_waste.c +++ /dev/null @@ -1,44 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32l4/stm32l4_waste.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include -#include "stm32l4_waste.h" - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -uint32_t g_waste_counter = 0; - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -void stm32l4_waste(void) -{ - g_waste_counter++; -} diff --git a/arch/arm/src/stm32l4/stm32l4_waste.h b/arch/arm/src/stm32l4/stm32l4_waste.h deleted file mode 100644 index bc24eff6c3990..0000000000000 --- a/arch/arm/src/stm32l4/stm32l4_waste.h +++ /dev/null @@ -1,66 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32l4/stm32l4_waste.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32L4_STM32L4_WASTE_H -#define __ARCH_ARM_SRC_STM32L4_STM32L4_WASTE_H - -/* Waste CPU Time */ - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#ifndef __ASSEMBLY__ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/* Waste CPU Time - * - * stm32l4_waste() is the logic that will be executed when portions of - * kernel or user-app is polling some register or similar, waiting for - * desired status. This time is wasted away. This function offers a - * measure of badly written piece of software or some undesired behavior. - * - * At the same time this function adds to some IDLE time which portion - * cannot be used for other purposes (yet). - */ - -void stm32l4_waste(void); - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32L4_STM32L4_WASTE_H */ diff --git a/arch/arm/src/stm32l4/stm32l4_wdg.h b/arch/arm/src/stm32l4/stm32l4_wdg.h index 1e2a8e1dbdd3f..99a41479eb3bd 100644 --- a/arch/arm/src/stm32l4/stm32l4_wdg.h +++ b/arch/arm/src/stm32l4/stm32l4_wdg.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32L4_STM32L4_WDG_H -#define __ARCH_ARM_SRC_STM32L4_STM32L4_WDG_H +#ifndef __ARCH_ARM_SRC_STM32L4_STM32_WDG_H +#define __ARCH_ARM_SRC_STM32L4_STM32_WDG_H /**************************************************************************** * Included Files @@ -54,7 +54,7 @@ extern "C" ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_iwdginitialize + * Name: stm32_iwdginitialize * * Description: * Initialize the IWDG watchdog time. The watchdog timer is initialized @@ -71,12 +71,12 @@ extern "C" * ****************************************************************************/ -#ifdef CONFIG_STM32L4_IWDG -void stm32l4_iwdginitialize(const char *devpath, uint32_t lsifreq); +#ifdef CONFIG_STM32_IWDG +void stm32_iwdginitialize(const char *devpath, uint32_t lsifreq); #endif /**************************************************************************** - * Name: stm32l4_wwdginitialize + * Name: stm32_wwdginitialize * * Description: * Initialize the WWDG watchdog time. The watchdog timer is initialized @@ -92,8 +92,8 @@ void stm32l4_iwdginitialize(const char *devpath, uint32_t lsifreq); * ****************************************************************************/ -#ifdef CONFIG_STM32L4_WWDG -void stm32l4_wwdginitialize(const char *devpath); +#ifdef CONFIG_STM32_WWDG +void stm32_wwdginitialize(const char *devpath); #endif #undef EXTERN @@ -103,4 +103,4 @@ void stm32l4_wwdginitialize(const char *devpath); #endif /* __ASSEMBLY__ */ #endif /* CONFIG_WATCHDOG */ -#endif /* __ARCH_ARM_SRC_STM32L4_STM32L4_WDG_H */ +#endif /* __ARCH_ARM_SRC_STM32L4_STM32_WDG_H */ diff --git a/arch/arm/src/stm32l4/stm32l4x3xx_rcc.c b/arch/arm/src/stm32l4/stm32l4x3xx_rcc.c index 31e48e84d61aa..5c46cc182bcad 100644 --- a/arch/arm/src/stm32l4/stm32l4x3xx_rcc.c +++ b/arch/arm/src/stm32l4/stm32l4x3xx_rcc.c @@ -55,9 +55,9 @@ static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1, /* Determine if board wants to use HSI48 as 48 MHz oscillator. */ -#if defined(CONFIG_STM32L4_HAVE_HSI48) && defined(STM32L4_USE_CLK48) -# if STM32L4_CLK48_SEL == RCC_CCIPR_CLK48SEL_HSI48 -# define STM32L4_USE_HSI48 +#if defined(CONFIG_STM32_HAVE_HSI48) && defined(STM32_USE_CLK48) +# if STM32_CLK48_SEL == RCC_CCIPR_CLK48SEL_HSI48 +# define STM32_USE_HSI48 # endif #endif @@ -83,33 +83,33 @@ static inline void rcc_reset(void) /* Enable the Internal High Speed clock (HSI) */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_HSION; - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Reset CFGR register */ - putreg32(0x00000000, STM32L4_RCC_CFGR); + putreg32(0x00000000, STM32_RCC_CFGR); /* Reset HSION, HSEON, CSSON and PLLON bits */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval &= ~(RCC_CR_HSION | RCC_CR_HSEON | RCC_CR_CSSON | RCC_CR_PLLON); - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Reset PLLCFGR register to reset default */ - putreg32(RCC_PLLCFG_RESET, STM32L4_RCC_PLLCFG); + putreg32(RCC_PLLCFG_RESET, STM32_RCC_PLLCFG); /* Reset HSEBYP bit */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval &= ~RCC_CR_HSEBYP; - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Disable all interrupts */ - putreg32(0x00000000, STM32L4_RCC_CIER); + putreg32(0x00000000, STM32_RCC_CIER); } /**************************************************************************** @@ -128,33 +128,33 @@ static inline void rcc_enableahb1(void) * selected AHB1 peripherals. */ - regval = getreg32(STM32L4_RCC_AHB1ENR); + regval = getreg32(STM32_RCC_AHB1ENR); -#ifdef CONFIG_STM32L4_DMA1 +#ifdef CONFIG_STM32_DMA1 /* DMA 1 clock enable */ regval |= RCC_AHB1ENR_DMA1EN; #endif -#ifdef CONFIG_STM32L4_DMA2 +#ifdef CONFIG_STM32_DMA2 /* DMA 2 clock enable */ regval |= RCC_AHB1ENR_DMA2EN; #endif -#ifdef CONFIG_STM32L4_CRC +#ifdef CONFIG_STM32_CRC /* CRC clock enable */ regval |= RCC_AHB1ENR_CRCEN; #endif -#ifdef CONFIG_STM32L4_TSC +#ifdef CONFIG_STM32_TSC /* TSC clock enable */ regval |= RCC_AHB1ENR_TSCEN; #endif - putreg32(regval, STM32L4_RCC_AHB1ENR); /* Enable peripherals */ + putreg32(regval, STM32_RCC_AHB1ENR); /* Enable peripherals */ } /**************************************************************************** @@ -173,50 +173,50 @@ static inline void rcc_enableahb2(void) * selected AHB2 peripherals. */ - regval = getreg32(STM32L4_RCC_AHB2ENR); + regval = getreg32(STM32_RCC_AHB2ENR); /* Enable GPIOA, GPIOB, .... GPIOH */ -#if STM32L4_NPORTS > 0 +#if STM32_NPORTS > 0 regval |= (RCC_AHB2ENR_GPIOAEN -#if STM32L4_NPORTS > 1 +#if STM32_NPORTS > 1 | RCC_AHB2ENR_GPIOBEN #endif -#if STM32L4_NPORTS > 2 +#if STM32_NPORTS > 2 | RCC_AHB2ENR_GPIOCEN #endif -#if STM32L4_NPORTS > 3 +#if STM32_NPORTS > 3 | RCC_AHB2ENR_GPIODEN #endif -#if STM32L4_NPORTS > 4 +#if STM32_NPORTS > 4 | RCC_AHB2ENR_GPIOEEN #endif /* These chips have no GPIOF, GPIOG or GPIOI */ -#if STM32L4_NPORTS > 7 +#if STM32_NPORTS > 7 | RCC_AHB2ENR_GPIOHEN #endif ); #endif -#if defined(CONFIG_STM32L4_ADC1) +#if defined(CONFIG_STM32_ADC1) /* ADC clock enable */ regval |= RCC_AHB2ENR_ADCEN; #endif -#ifdef CONFIG_STM32L4_AES +#ifdef CONFIG_STM32_AES /* Cryptographic modules clock enable */ regval |= RCC_AHB2ENR_AESEN; #endif -#ifdef CONFIG_STM32L4_RNG +#ifdef CONFIG_STM32_RNG /* Random number generator clock enable */ regval |= RCC_AHB2ENR_RNGEN; #endif - putreg32(regval, STM32L4_RCC_AHB2ENR); /* Enable peripherals */ + putreg32(regval, STM32_RCC_AHB2ENR); /* Enable peripherals */ } /**************************************************************************** @@ -235,15 +235,15 @@ static inline void rcc_enableahb3(void) * selected AHB3 peripherals. */ - regval = getreg32(STM32L4_RCC_AHB3ENR); + regval = getreg32(STM32_RCC_AHB3ENR); -#ifdef CONFIG_STM32L4_QSPI +#ifdef CONFIG_STM32_QSPI /* QuadSPI module clock enable */ regval |= RCC_AHB3ENR_QSPIEN; #endif - putreg32(regval, STM32L4_RCC_AHB3ENR); /* Enable peripherals */ + putreg32(regval, STM32_RCC_AHB3ENR); /* Enable peripherals */ } /**************************************************************************** @@ -262,100 +262,100 @@ static inline void rcc_enableapb1(void) * selected APB1 peripherals. */ - regval = getreg32(STM32L4_RCC_APB1ENR1); + regval = getreg32(STM32_RCC_APB1ENR1); -#ifdef CONFIG_STM32L4_TIM2 +#ifdef CONFIG_STM32_TIM2 /* TIM2 clock enable */ regval |= RCC_APB1ENR1_TIM2EN; #endif -#ifdef CONFIG_STM32L4_TIM3 +#ifdef CONFIG_STM32_TIM3 /* TIM3 clock enable */ regval |= RCC_APB1ENR1_TIM3EN; #endif -#ifdef CONFIG_STM32L4_TIM6 +#ifdef CONFIG_STM32_TIM6 /* TIM6 clock enable */ regval |= RCC_APB1ENR1_TIM6EN; #endif -#ifdef CONFIG_STM32L4_TIM7 +#ifdef CONFIG_STM32_TIM7 /* TIM7 clock enable */ regval |= RCC_APB1ENR1_TIM7EN; #endif -#ifdef CONFIG_STM32L4_LCD +#ifdef CONFIG_STM32_LCD /* LCD clock enable */ regval |= RCC_APB1ENR1_LCDEN; #endif -#ifdef CONFIG_STM32L4_SPI2 +#ifdef CONFIG_STM32_SPI2 /* SPI2 clock enable */ regval |= RCC_APB1ENR1_SPI2EN; #endif -#ifdef CONFIG_STM32L4_SPI3 +#ifdef CONFIG_STM32_SPI3 /* SPI3 clock enable */ regval |= RCC_APB1ENR1_SPI3EN; #endif -#ifdef CONFIG_STM32L4_USART2 +#ifdef CONFIG_STM32_USART2 /* USART 2 clock enable */ regval |= RCC_APB1ENR1_USART2EN; #endif -#ifdef CONFIG_STM32L4_USART3 +#ifdef CONFIG_STM32_USART3 /* USART3 clock enable */ regval |= RCC_APB1ENR1_USART3EN; #endif -#ifdef CONFIG_STM32L4_UART4 +#ifdef CONFIG_STM32_UART4 /* UART4 clock enable */ regval |= RCC_APB1ENR1_UART4EN; #endif -#ifdef CONFIG_STM32L4_I2C1 +#ifdef CONFIG_STM32_I2C1 /* I2C1 clock enable */ regval |= RCC_APB1ENR1_I2C1EN; #endif -#ifdef CONFIG_STM32L4_I2C2 +#ifdef CONFIG_STM32_I2C2 /* I2C2 clock enable */ regval |= RCC_APB1ENR1_I2C2EN; #endif -#ifdef CONFIG_STM32L4_I2C3 +#ifdef CONFIG_STM32_I2C3 /* I2C3 clock enable */ regval |= RCC_APB1ENR1_I2C3EN; #endif -#ifdef CONFIG_STM32L4_CAN1 +#ifdef CONFIG_STM32_CAN1 /* CAN 1 clock enable */ regval |= RCC_APB1ENR1_CAN1EN; #endif -#ifdef CONFIG_STM32L4_USBFS +#ifdef CONFIG_STM32_USBFS /* USB FS clock enable */ regval |= RCC_APB1ENR1_USBFSEN; #endif -#ifdef STM32L4_USE_HSI48 - if (STM32L4_HSI48_SYNCSRC != SYNCSRC_NONE) +#ifdef STM32_USE_HSI48 + if (STM32_HSI48_SYNCSRC != SYNCSRC_NONE) { /* Clock Recovery System clock enable */ @@ -369,55 +369,55 @@ static inline void rcc_enableapb1(void) regval |= RCC_APB1ENR1_PWREN; -#if defined (CONFIG_STM32L4_DAC1) || defined(CONFIG_STM32L4_DAC2) +#if defined (CONFIG_STM32_DAC1) || defined(CONFIG_STM32_DAC2) /* DAC interface clock enable */ regval |= RCC_APB1ENR1_DAC1EN; #endif -#ifdef CONFIG_STM32L4_OPAMP +#ifdef CONFIG_STM32_OPAMP /* OPAMP clock enable */ regval |= RCC_APB1ENR1_OPAMPEN; #endif -#ifdef CONFIG_STM32L4_LPTIM1 +#ifdef CONFIG_STM32_LPTIM1 /* Low power timer 1 clock enable */ regval |= RCC_APB1ENR1_LPTIM1EN; #endif - putreg32(regval, STM32L4_RCC_APB1ENR1); /* Enable peripherals */ + putreg32(regval, STM32_RCC_APB1ENR1); /* Enable peripherals */ /* Second APB1 register */ - regval = getreg32(STM32L4_RCC_APB1ENR2); + regval = getreg32(STM32_RCC_APB1ENR2); -#ifdef CONFIG_STM32L4_LPUART1 +#ifdef CONFIG_STM32_LPUART1 /* Low power uart clock enable */ regval |= RCC_APB1ENR2_LPUART1EN; #endif -#ifdef CONFIG_STM32L4_I2C4 +#ifdef CONFIG_STM32_I2C4 /* I2C4 clock enable */ regval |= RCC_APB1ENR2_I2C4EN; #endif -#ifdef CONFIG_STM32L4_SWPMI +#ifdef CONFIG_STM32_SWPMI /* Single-wire protocol master clock enable */ regval |= RCC_APB1ENR2_SWPMI1EN; #endif -#ifdef CONFIG_STM32L4_LPTIM2 +#ifdef CONFIG_STM32_LPTIM2 /* Low power timer 2 clock enable */ regval |= RCC_APB1ENR2_LPTIM2EN; #endif - putreg32(regval, STM32L4_RCC_APB1ENR2); /* Enable peripherals */ + putreg32(regval, STM32_RCC_APB1ENR2); /* Enable peripherals */ } /**************************************************************************** @@ -436,9 +436,9 @@ static inline void rcc_enableapb2(void) * selected APB2 peripherals. */ - regval = getreg32(STM32L4_RCC_APB2ENR); + regval = getreg32(STM32_RCC_APB2ENR); -#if defined(CONFIG_STM32L4_SYSCFG) || defined(CONFIG_STM32L4_COMP) +#if defined(CONFIG_STM32_SYSCFG) || defined(CONFIG_STM32_COMP) /* System configuration controller, comparators, and voltage reference * buffer clock enable */ @@ -446,61 +446,61 @@ static inline void rcc_enableapb2(void) regval |= RCC_APB2ENR_SYSCFGEN; #endif -#ifdef CONFIG_STM32L4_FIREWALL +#ifdef CONFIG_STM32_FIREWALL /* Firewall clock enable */ regval |= RCC_APB2ENR_FWEN; #endif -#ifdef CONFIG_STM32L4_SDMMC +#ifdef CONFIG_STM32_SDMMC /* SDMMC clock enable */ regval |= RCC_APB2ENR_SDMMCEN; #endif -#ifdef CONFIG_STM32L4_TIM1 +#ifdef CONFIG_STM32_TIM1 /* TIM1 clock enable */ regval |= RCC_APB2ENR_TIM1EN; #endif -#ifdef CONFIG_STM32L4_SPI1 +#ifdef CONFIG_STM32_SPI1 /* SPI1 clock enable */ regval |= RCC_APB2ENR_SPI1EN; #endif -#ifdef CONFIG_STM32L4_USART1 +#ifdef CONFIG_STM32_USART1 /* USART1 clock enable */ regval |= RCC_APB2ENR_USART1EN; #endif -#ifdef CONFIG_STM32L4_TIM15 +#ifdef CONFIG_STM32_TIM15 /* TIM15 clock enable */ regval |= RCC_APB2ENR_TIM15EN; #endif -#ifdef CONFIG_STM32L4_TIM16 +#ifdef CONFIG_STM32_TIM16 /* TIM16 clock enable */ regval |= RCC_APB2ENR_TIM16EN; #endif -#ifdef CONFIG_STM32L4_SAI1 +#ifdef CONFIG_STM32_SAI1 /* SAI1 clock enable */ regval |= RCC_APB2ENR_SAI1EN; #endif -#ifdef CONFIG_STM32L4_DFSDM1 +#ifdef CONFIG_STM32_DFSDM1 /* DFSDM clock enable */ regval |= RCC_APB2ENR_DFSDMEN; #endif - putreg32(regval, STM32L4_RCC_APB2ENR); /* Enable peripherals */ + putreg32(regval, STM32_RCC_APB2ENR); /* Enable peripherals */ } /**************************************************************************** @@ -520,47 +520,47 @@ static inline void rcc_enableccip(void) * will at least have a clock. */ - regval = getreg32(STM32L4_RCC_CCIPR); + regval = getreg32(STM32_RCC_CCIPR); -#if defined(STM32L4_I2C_USE_HSI16) -#ifdef CONFIG_STM32L4_I2C1 +#if defined(STM32_I2C_USE_HSI16) +#ifdef CONFIG_STM32_I2C1 /* Select HSI16 as I2C1 clock source. */ regval &= ~RCC_CCIPR_I2C1SEL_MASK; regval |= RCC_CCIPR_I2C1SEL_HSI; #endif -#ifdef CONFIG_STM32L4_I2C2 +#ifdef CONFIG_STM32_I2C2 /* Select HSI16 as I2C2 clock source. */ regval &= ~RCC_CCIPR_I2C2SEL_MASK; regval |= RCC_CCIPR_I2C2SEL_HSI; #endif -#ifdef CONFIG_STM32L4_I2C3 +#ifdef CONFIG_STM32_I2C3 /* Select HSI16 as I2C3 clock source. */ regval &= ~RCC_CCIPR_I2C3SEL_MASK; regval |= RCC_CCIPR_I2C3SEL_HSI; #endif -#endif /* STM32L4_I2C_USE_HSI16 */ +#endif /* STM32_I2C_USE_HSI16 */ -#if defined(STM32L4_USE_CLK48) +#if defined(STM32_USE_CLK48) /* XXX sanity if sdmmc1 or usb or rng, then we need to set the clk48 source - * and then we can also do away with STM32L4_USE_CLK48, and give better + * and then we can also do away with STM32_USE_CLK48, and give better * warning messages. */ regval &= ~RCC_CCIPR_CLK48SEL_MASK; - regval |= STM32L4_CLK48_SEL; + regval |= STM32_CLK48_SEL; #endif -#if defined(CONFIG_STM32L4_ADC1) +#if defined(CONFIG_STM32_ADC1) /* Select SYSCLK as ADC clock source */ regval &= ~RCC_CCIPR_ADCSEL_MASK; regval |= RCC_CCIPR_ADCSEL_SYSCLK; #endif -#ifdef CONFIG_STM32L4_DFSDM1 +#ifdef CONFIG_STM32_DFSDM1 /* Select SYSCLK as DFSDM clock source */ /* RM0394 Rev 3, p. 525 is confused about DFSDM clock source. @@ -572,26 +572,26 @@ static inline void rcc_enableccip(void) regval |= RCC_CCIPR_DFSDMSEL_SYSCLK; #endif - putreg32(regval, STM32L4_RCC_CCIPR); + putreg32(regval, STM32_RCC_CCIPR); /* I2C4 alone has their clock selection in CCIPR2 register. */ -#if defined(STM32L4_I2C_USE_HSI16) -#ifdef CONFIG_STM32L4_I2C4 - regval = getreg32(STM32L4_RCC_CCIPR2); +#if defined(STM32_I2C_USE_HSI16) +#ifdef CONFIG_STM32_I2C4 + regval = getreg32(STM32_RCC_CCIPR2); /* Select HSI16 as I2C4 clock source. */ regval &= ~RCC_CCIPR2_I2C4SEL_MASK; regval |= RCC_CCIPR2_I2C4SEL_HSI; - putreg32(regval, STM32L4_RCC_CCIPR2); + putreg32(regval, STM32_RCC_CCIPR2); #endif #endif } /**************************************************************************** - * Name: stm32l4_stdclockconfig + * Name: stm32_stdclockconfig * * Description: * Called to change to new clock based on settings in board.h @@ -600,18 +600,18 @@ static inline void rcc_enableccip(void) * power clocking modes! ****************************************************************************/ -#ifndef CONFIG_ARCH_BOARD_STM32L4_CUSTOM_CLOCKCONFIG -static void stm32l4_stdclockconfig(void) +#ifndef CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG +static void stm32_stdclockconfig(void) { uint32_t regval; volatile int32_t timeout; -#if defined(STM32L4_BOARD_USEHSI) || defined(STM32L4_I2C_USE_HSI16) +#if defined(STM32_BOARD_USEHSI) || defined(STM32_I2C_USE_HSI16) /* Enable Internal High-Speed Clock (HSI) */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_HSION; /* Enable HSI */ - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Wait until the HSI is ready (or until a timeout elapsed) */ @@ -619,7 +619,7 @@ static void stm32l4_stdclockconfig(void) { /* Check if the HSIRDY flag is the set in the CR */ - if ((getreg32(STM32L4_RCC_CR) & RCC_CR_HSIRDY) != 0) + if ((getreg32(STM32_RCC_CR) & RCC_CR_HSIRDY) != 0) { /* If so, then break-out with timeout > 0 */ @@ -628,17 +628,17 @@ static void stm32l4_stdclockconfig(void) } #endif -#if defined(STM32L4_BOARD_USEHSI) +#if defined(STM32_BOARD_USEHSI) /* Already set above */ -#elif defined(STM32L4_BOARD_USEMSI) +#elif defined(STM32_BOARD_USEMSI) /* Enable Internal Multi-Speed Clock (MSI) */ /* Wait until the MSI is either off or ready (or until a timeout elapsed) */ for (timeout = MSIRDY_TIMEOUT; timeout > 0; timeout--) { - if ((regval = getreg32(STM32L4_RCC_CR)), (regval & RCC_CR_MSIRDY) || + if ((regval = getreg32(STM32_RCC_CR)), (regval & RCC_CR_MSIRDY) || ~(regval & RCC_CR_MSION)) { /* If so, then break-out with timeout > 0 */ @@ -649,10 +649,10 @@ static void stm32l4_stdclockconfig(void) /* setting MSIRANGE */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval &= ~RCC_CR_MSIRANGE_MASK; - regval |= (STM32L4_BOARD_MSIRANGE | RCC_CR_MSION); /* Enable MSI and frequency */ - putreg32(regval, STM32L4_RCC_CR); + regval |= (STM32_BOARD_MSIRANGE | RCC_CR_MSION); /* Enable MSI and frequency */ + putreg32(regval, STM32_RCC_CR); /* Wait until the MSI is ready (or until a timeout elapsed) */ @@ -660,7 +660,7 @@ static void stm32l4_stdclockconfig(void) { /* Check if the MSIRDY flag is the set in the CR */ - if ((getreg32(STM32L4_RCC_CR) & RCC_CR_MSIRDY) != 0) + if ((getreg32(STM32_RCC_CR) & RCC_CR_MSIRDY) != 0) { /* If so, then break-out with timeout > 0 */ @@ -668,12 +668,12 @@ static void stm32l4_stdclockconfig(void) } } -#elif defined(STM32L4_BOARD_USEHSE) +#elif defined(STM32_BOARD_USEHSE) /* Enable External High-Speed Clock (HSE) */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_HSEON; /* Enable HSE */ - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Wait until the HSE is ready (or until a timeout elapsed) */ @@ -681,7 +681,7 @@ static void stm32l4_stdclockconfig(void) { /* Check if the HSERDY flag is the set in the CR */ - if ((getreg32(STM32L4_RCC_CR) & RCC_CR_HSERDY) != 0) + if ((getreg32(STM32_RCC_CR) & RCC_CR_HSERDY) != 0) { /* If so, then break-out with timeout > 0 */ @@ -690,7 +690,7 @@ static void stm32l4_stdclockconfig(void) } #else -# error stm32l4_stdclockconfig(), must have one of STM32L4_BOARD_USEHSI, STM32L4_BOARD_USEMSI, STM32L4_BOARD_USEHSE defined +# error stm32_stdclockconfig(), must have one of STM32_BOARD_USEHSI, STM32_BOARD_USEMSI, STM32_BOARD_USEHSE defined #endif @@ -705,154 +705,154 @@ static void stm32l4_stdclockconfig(void) #if 0 /* Ensure Power control is enabled before modifying it. */ - regval = getreg32(STM32L4_RCC_APB1ENR1); + regval = getreg32(STM32_RCC_APB1ENR1); regval |= RCC_APB1ENR1_PWREN; - putreg32(regval, STM32L4_RCC_APB1ENR1); + putreg32(regval, STM32_RCC_APB1ENR1); /* Select regulator voltage output Scale 1 mode to support system * frequencies up to 168 MHz. */ - regval = getreg32(STM32L4_PWR_CR); + regval = getreg32(STM32_PWR_CR); regval &= ~PWR_CR_VOS_MASK; regval |= PWR_CR_VOS_SCALE_1; - putreg32(regval, STM32L4_PWR_CR); + putreg32(regval, STM32_PWR_CR); #endif /* Set the HCLK source/divider */ - regval = getreg32(STM32L4_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_HPRE_MASK; - regval |= STM32L4_RCC_CFGR_HPRE; - putreg32(regval, STM32L4_RCC_CFGR); + regval |= STM32_RCC_CFGR_HPRE; + putreg32(regval, STM32_RCC_CFGR); /* Set the PCLK2 divider */ - regval = getreg32(STM32L4_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_PPRE2_MASK; - regval |= STM32L4_RCC_CFGR_PPRE2; - putreg32(regval, STM32L4_RCC_CFGR); + regval |= STM32_RCC_CFGR_PPRE2; + putreg32(regval, STM32_RCC_CFGR); /* Set the PCLK1 divider */ - regval = getreg32(STM32L4_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_PPRE1_MASK; - regval |= STM32L4_RCC_CFGR_PPRE1; - putreg32(regval, STM32L4_RCC_CFGR); + regval |= STM32_RCC_CFGR_PPRE1; + putreg32(regval, STM32_RCC_CFGR); /* Set the PLL source and main divider */ - regval = getreg32(STM32L4_RCC_PLLCFG); + regval = getreg32(STM32_RCC_PLLCFG); /* Configure Main PLL */ /* Set the PLL dividers and multipliers to configure the main PLL */ - regval = (STM32L4_PLLCFG_PLLM | STM32L4_PLLCFG_PLLN | - STM32L4_PLLCFG_PLLP | STM32L4_PLLCFG_PLLQ | - STM32L4_PLLCFG_PLLR); + regval = (STM32_PLLCFG_PLLM | STM32_PLLCFG_PLLN | + STM32_PLLCFG_PLLP | STM32_PLLCFG_PLLQ | + STM32_PLLCFG_PLLR); -#ifdef STM32L4_PLLCFG_PLLP_ENABLED +#ifdef STM32_PLLCFG_PLLP_ENABLED regval |= RCC_PLLCFG_PLLPEN; #endif -#ifdef STM32L4_PLLCFG_PLLQ_ENABLED +#ifdef STM32_PLLCFG_PLLQ_ENABLED regval |= RCC_PLLCFG_PLLQEN; #endif -#ifdef STM32L4_PLLCFG_PLLR_ENABLED +#ifdef STM32_PLLCFG_PLLR_ENABLED regval |= RCC_PLLCFG_PLLREN; #endif /* XXX The choice of clock source to PLL (all three) is independent - * of the sys clock source choice, review the STM32L4_BOARD_USEHSI + * of the sys clock source choice, review the STM32_BOARD_USEHSI * name; probably split it into two, one for PLL source and one * for sys clock source. */ -#ifdef STM32L4_BOARD_USEHSI +#ifdef STM32_BOARD_USEHSI regval |= RCC_PLLCFG_PLLSRC_HSI; -#elif defined(STM32L4_BOARD_USEMSI) +#elif defined(STM32_BOARD_USEMSI) regval |= RCC_PLLCFG_PLLSRC_MSI; -#else /* if STM32L4_BOARD_USEHSE */ +#else /* if STM32_BOARD_USEHSE */ regval |= RCC_PLLCFG_PLLSRC_HSE; #endif - putreg32(regval, STM32L4_RCC_PLLCFG); + putreg32(regval, STM32_RCC_PLLCFG); /* Enable the main PLL */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_PLLON; - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Wait until the PLL is ready */ - while ((getreg32(STM32L4_RCC_CR) & RCC_CR_PLLRDY) == 0) + while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLRDY) == 0) { } -#ifdef CONFIG_STM32L4_SAI1PLL +#ifdef CONFIG_STM32_SAI1PLL /* Configure SAI1 PLL */ - regval = getreg32(STM32L4_RCC_PLLSAI1CFG); + regval = getreg32(STM32_RCC_PLLSAI1CFG); /* Set the PLL dividers and multipliers to configure the SAI1 PLL */ - regval = (STM32L4_PLLSAI1CFG_PLLN | STM32L4_PLLSAI1CFG_PLLP - | STM32L4_PLLSAI1CFG_PLLQ | STM32L4_PLLSAI1CFG_PLLR); + regval = (STM32_PLLSAI1CFG_PLLN | STM32_PLLSAI1CFG_PLLP + | STM32_PLLSAI1CFG_PLLQ | STM32_PLLSAI1CFG_PLLR); -#ifdef STM32L4_PLLSAI1CFG_PLLP_ENABLED +#ifdef STM32_PLLSAI1CFG_PLLP_ENABLED regval |= RCC_PLLSAI1CFG_PLLPEN; #endif -#ifdef STM32L4_PLLSAI1CFG_PLLQ_ENABLED +#ifdef STM32_PLLSAI1CFG_PLLQ_ENABLED regval |= RCC_PLLSAI1CFG_PLLQEN; #endif -#ifdef STM32L4_PLLSAI1CFG_PLLR_ENABLED +#ifdef STM32_PLLSAI1CFG_PLLR_ENABLED regval |= RCC_PLLSAI1CFG_PLLREN; #endif - putreg32(regval, STM32L4_RCC_PLLSAI1CFG); + putreg32(regval, STM32_RCC_PLLSAI1CFG); /* Enable the SAI1 PLL */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_PLLSAI1ON; - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Wait until the PLL is ready */ - while ((getreg32(STM32L4_RCC_CR) & RCC_CR_PLLSAI1RDY) == 0) + while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLSAI1RDY) == 0) { } #endif -#ifdef CONFIG_STM32L4_SAI2PLL +#ifdef CONFIG_STM32_SAI2PLL /* Configure SAI2 PLL */ - regval = getreg32(STM32L4_RCC_PLLSAI2CFG); + regval = getreg32(STM32_RCC_PLLSAI2CFG); /* Set the PLL dividers and multipliers to configure the SAI2 PLL */ - regval = (STM32L4_PLLSAI2CFG_PLLN | STM32L4_PLLSAI2CFG_PLLP | - STM32L4_PLLSAI2CFG_PLLR); + regval = (STM32_PLLSAI2CFG_PLLN | STM32_PLLSAI2CFG_PLLP | + STM32_PLLSAI2CFG_PLLR); -#ifdef STM32L4_PLLSAI2CFG_PLLP_ENABLED +#ifdef STM32_PLLSAI2CFG_PLLP_ENABLED regval |= RCC_PLLSAI2CFG_PLLPEN; #endif -#ifdef STM32L4_PLLSAI2CFG_PLLR_ENABLED +#ifdef STM32_PLLSAI2CFG_PLLR_ENABLED regval |= RCC_PLLSAI2CFG_PLLREN; #endif - putreg32(regval, STM32L4_RCC_PLLSAI2CFG); + putreg32(regval, STM32_RCC_PLLSAI2CFG); /* Enable the SAI2 PLL */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_PLLSAI2ON; - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Wait until the PLL is ready */ - while ((getreg32(STM32L4_RCC_CR) & RCC_CR_PLLSAI2RDY) == 0) + while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLSAI2RDY) == 0) { } #endif @@ -861,35 +861,35 @@ static void stm32l4_stdclockconfig(void) * and 4 wait states */ -#ifdef CONFIG_STM32L4_FLASH_PREFETCH +#ifdef CONFIG_STM32_FLASH_PREFETCH regval = (FLASH_ACR_LATENCY_4 | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_PRFTEN); #else regval = (FLASH_ACR_LATENCY_4 | FLASH_ACR_ICEN | FLASH_ACR_DCEN); #endif - putreg32(regval, STM32L4_FLASH_ACR); + putreg32(regval, STM32_FLASH_ACR); /* Select the main PLL as system clock source */ - regval = getreg32(STM32L4_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_SW_MASK; regval |= RCC_CFGR_SW_PLL; - putreg32(regval, STM32L4_RCC_CFGR); + putreg32(regval, STM32_RCC_CFGR); /* Wait until the PLL source is used as the system clock source */ - while ((getreg32(STM32L4_RCC_CFGR) & RCC_CFGR_SWS_MASK) != + while ((getreg32(STM32_RCC_CFGR) & RCC_CFGR_SWS_MASK) != RCC_CFGR_SWS_PLL) { } -#if defined(CONFIG_STM32L4_IWDG) || defined(CONFIG_STM32L4_RTC_LSICLOCK) +#if defined(CONFIG_STM32_IWDG) || defined(CONFIG_STM32_RTC_LSICLOCK) /* Low speed internal clock source LSI */ - stm32l4_rcc_enablelsi(); + stm32_rcc_enablelsi(); #endif -#if defined(STM32L4_USE_LSE) +#if defined(STM32_USE_LSE) /* Low speed external clock source LSE * * TODO: There is another case where the LSE needs to @@ -901,7 +901,7 @@ static void stm32l4_stdclockconfig(void) * to alter the LSE parameters. */ - stm32l4_pwr_enableclk(true); + stm32_pwr_enableclk(true); /* XXX other LSE settings must be made before turning on the oscillator * and we need to ensure it is first off before doing so. @@ -912,16 +912,16 @@ static void stm32l4_stdclockconfig(void) * this for automatically trimming MSI, etc. */ - stm32l4_rcc_enablelse(); + stm32_rcc_enablelse(); -# if defined(STM32L4_BOARD_USEMSI) +# if defined(STM32_BOARD_USEMSI) /* Now that LSE is up, auto trim the MSI */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_MSIPLLEN; - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); # endif -#endif /* STM32L4_USE_LSE */ +#endif /* STM32_USE_LSE */ } } #endif @@ -939,10 +939,10 @@ static inline void rcc_enableperipherals(void) rcc_enableapb1(); rcc_enableapb2(); -#ifdef STM32L4_USE_HSI48 +#ifdef STM32_USE_HSI48 /* Enable HSI48 clocking to support USB transfers or RNG */ - stm32l4_enable_hsi48(STM32L4_HSI48_SYNCSRC); + stm32_enable_hsi48(STM32_HSI48_SYNCSRC); #endif } diff --git a/arch/arm/src/stm32l4/stm32l4x5xx_rcc.c b/arch/arm/src/stm32l4/stm32l4x5xx_rcc.c index b6c1903edd909..254efbeb45b00 100644 --- a/arch/arm/src/stm32l4/stm32l4x5xx_rcc.c +++ b/arch/arm/src/stm32l4/stm32l4x5xx_rcc.c @@ -74,33 +74,33 @@ static inline void rcc_reset(void) /* Enable the Internal High Speed clock (HSI) */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_HSION; - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Reset CFGR register */ - putreg32(0x00000000, STM32L4_RCC_CFGR); + putreg32(0x00000000, STM32_RCC_CFGR); /* Reset HSION, HSEON, CSSON and PLLON bits */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval &= ~(RCC_CR_HSION | RCC_CR_HSEON | RCC_CR_CSSON | RCC_CR_PLLON); - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Reset PLLCFGR register to reset default */ - putreg32(RCC_PLLCFG_RESET, STM32L4_RCC_PLLCFG); + putreg32(RCC_PLLCFG_RESET, STM32_RCC_PLLCFG); /* Reset HSEBYP bit */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval &= ~RCC_CR_HSEBYP; - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Disable all interrupts */ - putreg32(0x00000000, STM32L4_RCC_CIER); + putreg32(0x00000000, STM32_RCC_CIER); } /**************************************************************************** @@ -119,33 +119,33 @@ static inline void rcc_enableahb1(void) * selected AHB1 peripherals. */ - regval = getreg32(STM32L4_RCC_AHB1ENR); + regval = getreg32(STM32_RCC_AHB1ENR); -#ifdef CONFIG_STM32L4_DMA1 +#ifdef CONFIG_STM32_DMA1 /* DMA 1 clock enable */ regval |= RCC_AHB1ENR_DMA1EN; #endif -#ifdef CONFIG_STM32L4_DMA2 +#ifdef CONFIG_STM32_DMA2 /* DMA 2 clock enable */ regval |= RCC_AHB1ENR_DMA2EN; #endif -#ifdef CONFIG_STM32L4_CRC +#ifdef CONFIG_STM32_CRC /* CRC clock enable */ regval |= RCC_AHB1ENR_CRCEN; #endif -#ifdef CONFIG_STM32L4_TSC +#ifdef CONFIG_STM32_TSC /* TSC clock enable */ regval |= RCC_AHB1ENR_TSCEN; #endif - putreg32(regval, STM32L4_RCC_AHB1ENR); /* Enable peripherals */ + putreg32(regval, STM32_RCC_AHB1ENR); /* Enable peripherals */ } /**************************************************************************** @@ -164,55 +164,55 @@ static inline void rcc_enableahb2(void) * selected AHB2 peripherals. */ - regval = getreg32(STM32L4_RCC_AHB2ENR); + regval = getreg32(STM32_RCC_AHB2ENR); /* Enable GPIOA, GPIOB, .... GPIOH */ -#if STM32L4_NPORTS > 0 +#if STM32_NPORTS > 0 regval |= (RCC_AHB2ENR_GPIOAEN -#if STM32L4_NPORTS > 1 +#if STM32_NPORTS > 1 | RCC_AHB2ENR_GPIOBEN #endif -#if STM32L4_NPORTS > 2 +#if STM32_NPORTS > 2 | RCC_AHB2ENR_GPIOCEN #endif -#if STM32L4_NPORTS > 3 +#if STM32_NPORTS > 3 | RCC_AHB2ENR_GPIODEN #endif -#if STM32L4_NPORTS > 4 +#if STM32_NPORTS > 4 | RCC_AHB2ENR_GPIOEEN #endif -#if STM32L4_NPORTS > 5 +#if STM32_NPORTS > 5 | RCC_AHB2ENR_GPIOFEN #endif -#if STM32L4_NPORTS > 6 +#if STM32_NPORTS > 6 | RCC_AHB2ENR_GPIOGEN #endif -#if STM32L4_NPORTS > 7 +#if STM32_NPORTS > 7 | RCC_AHB2ENR_GPIOHEN #endif ); #endif -#ifdef CONFIG_STM32L4_OTGFS +#ifdef CONFIG_STM32_OTGFS /* USB OTG FS clock enable */ regval |= RCC_AHB2ENR_OTGFSEN; #endif -#if defined(CONFIG_STM32L4_ADC1) || defined(CONFIG_STM32L4_ADC2) || defined(CONFIG_STM32L4_ADC3) +#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) || defined(CONFIG_STM32_ADC3) /* ADC clock enable */ regval |= RCC_AHB2ENR_ADCEN; #endif -#ifdef CONFIG_STM32L4_RNG +#ifdef CONFIG_STM32_RNG /* Random number generator clock enable */ regval |= RCC_AHB2ENR_RNGEN; #endif - putreg32(regval, STM32L4_RCC_AHB2ENR); /* Enable peripherals */ + putreg32(regval, STM32_RCC_AHB2ENR); /* Enable peripherals */ } /**************************************************************************** @@ -231,21 +231,21 @@ static inline void rcc_enableahb3(void) * selected AHB3 peripherals. */ - regval = getreg32(STM32L4_RCC_AHB3ENR); + regval = getreg32(STM32_RCC_AHB3ENR); -#ifdef CONFIG_STM32L4_FSMC +#ifdef CONFIG_STM32_FSMC /* Flexible static memory controller module clock enable */ regval |= RCC_AHB3ENR_FSMCEN; #endif -#ifdef CONFIG_STM32L4_QSPI +#ifdef CONFIG_STM32_QSPI /* QuadSPI module clock enable */ regval |= RCC_AHB3ENR_QSPIEN; #endif - putreg32(regval, STM32L4_RCC_AHB3ENR); /* Enable peripherals */ + putreg32(regval, STM32_RCC_AHB3ENR); /* Enable peripherals */ } /**************************************************************************** @@ -264,99 +264,99 @@ static inline void rcc_enableapb1(void) * selected APB1 peripherals. */ - regval = getreg32(STM32L4_RCC_APB1ENR1); + regval = getreg32(STM32_RCC_APB1ENR1); -#ifdef CONFIG_STM32L4_TIM2 +#ifdef CONFIG_STM32_TIM2 /* TIM2 clock enable */ regval |= RCC_APB1ENR1_TIM2EN; #endif -#ifdef CONFIG_STM32L4_TIM3 +#ifdef CONFIG_STM32_TIM3 /* TIM3 clock enable */ regval |= RCC_APB1ENR1_TIM3EN; #endif -#ifdef CONFIG_STM32L4_TIM4 +#ifdef CONFIG_STM32_TIM4 /* TIM4 clock enable */ regval |= RCC_APB1ENR1_TIM4EN; #endif -#ifdef CONFIG_STM32L4_TIM5 +#ifdef CONFIG_STM32_TIM5 /* TIM5 clock enable */ regval |= RCC_APB1ENR1_TIM5EN; #endif -#ifdef CONFIG_STM32L4_TIM6 +#ifdef CONFIG_STM32_TIM6 /* TIM6 clock enable */ regval |= RCC_APB1ENR1_TIM6EN; #endif -#ifdef CONFIG_STM32L4_TIM7 +#ifdef CONFIG_STM32_TIM7 /* TIM7 clock enable */ regval |= RCC_APB1ENR1_TIM7EN; #endif -#ifdef CONFIG_STM32L4_SPI2 +#ifdef CONFIG_STM32_SPI2 /* SPI2 clock enable */ regval |= RCC_APB1ENR1_SPI2EN; #endif -#ifdef CONFIG_STM32L4_SPI3 +#ifdef CONFIG_STM32_SPI3 /* SPI3 clock enable */ regval |= RCC_APB1ENR1_SPI3EN; #endif -#ifdef CONFIG_STM32L4_USART2 +#ifdef CONFIG_STM32_USART2 /* USART 2 clock enable */ regval |= RCC_APB1ENR1_USART2EN; #endif -#ifdef CONFIG_STM32L4_USART3 +#ifdef CONFIG_STM32_USART3 /* USART3 clock enable */ regval |= RCC_APB1ENR1_USART3EN; #endif -#ifdef CONFIG_STM32L4_UART4 +#ifdef CONFIG_STM32_UART4 /* UART4 clock enable */ regval |= RCC_APB1ENR1_UART4EN; #endif -#ifdef CONFIG_STM32L4_UART5 +#ifdef CONFIG_STM32_UART5 /* UART5 clock enable */ regval |= RCC_APB1ENR1_UART5EN; #endif -#ifdef CONFIG_STM32L4_I2C1 +#ifdef CONFIG_STM32_I2C1 /* I2C1 clock enable */ regval |= RCC_APB1ENR1_I2C1EN; #endif -#ifdef CONFIG_STM32L4_I2C2 +#ifdef CONFIG_STM32_I2C2 /* I2C2 clock enable */ regval |= RCC_APB1ENR1_I2C2EN; #endif -#ifdef CONFIG_STM32L4_I2C3 +#ifdef CONFIG_STM32_I2C3 /* I2C3 clock enable */ regval |= RCC_APB1ENR1_I2C3EN; #endif -#ifdef CONFIG_STM32L4_CAN1 +#ifdef CONFIG_STM32_CAN1 /* CAN 1 clock enable */ regval |= RCC_APB1ENR1_CAN1EN; @@ -368,49 +368,49 @@ static inline void rcc_enableapb1(void) regval |= RCC_APB1ENR1_PWREN; -#if defined (CONFIG_STM32L4_DAC1) || defined(CONFIG_STM32L4_DAC2) +#if defined (CONFIG_STM32_DAC1) || defined(CONFIG_STM32_DAC2) /* DAC interface clock enable */ regval |= RCC_APB1ENR1_DAC1EN; #endif -#ifdef CONFIG_STM32L4_OPAMP +#ifdef CONFIG_STM32_OPAMP /* OPAMP clock enable */ regval |= RCC_APB1ENR1_OPAMPEN; #endif -#ifdef CONFIG_STM32L4_LPTIM1 +#ifdef CONFIG_STM32_LPTIM1 /* Low power timer 1 clock enable */ regval |= RCC_APB1ENR1_LPTIM1EN; #endif - putreg32(regval, STM32L4_RCC_APB1ENR1); /* Enable peripherals */ + putreg32(regval, STM32_RCC_APB1ENR1); /* Enable peripherals */ /* Second APB1 register */ - regval = getreg32(STM32L4_RCC_APB1ENR2); + regval = getreg32(STM32_RCC_APB1ENR2); -#ifdef CONFIG_STM32L4_LPUART1 +#ifdef CONFIG_STM32_LPUART1 /* Low power uart clock enable */ regval |= RCC_APB1ENR2_LPUART1EN; #endif -#ifdef CONFIG_STM32L4_SWPMI +#ifdef CONFIG_STM32_SWPMI /* Single-wire protocol master clock enable */ regval |= RCC_APB1ENR2_SWPMI1EN; #endif -#ifdef CONFIG_STM32L4_LPTIM2 +#ifdef CONFIG_STM32_LPTIM2 /* Low power timer 2 clock enable */ regval |= RCC_APB1ENR2_LPTIM2EN; #endif - putreg32(regval, STM32L4_RCC_APB1ENR2); /* Enable peripherals */ + putreg32(regval, STM32_RCC_APB1ENR2); /* Enable peripherals */ } /**************************************************************************** @@ -429,9 +429,9 @@ static inline void rcc_enableapb2(void) * selected APB2 peripherals. */ - regval = getreg32(STM32L4_RCC_APB2ENR); + regval = getreg32(STM32_RCC_APB2ENR); -#if defined(CONFIG_STM32L4_SYSCFG) || defined(CONFIG_STM32L4_COMP) +#if defined(CONFIG_STM32_SYSCFG) || defined(CONFIG_STM32_COMP) /* System configuration controller, comparators, and voltage reference * buffer clock enable */ @@ -439,79 +439,79 @@ static inline void rcc_enableapb2(void) regval |= RCC_APB2ENR_SYSCFGEN; #endif -#ifdef CONFIG_STM32L4_FIREWALL +#ifdef CONFIG_STM32_FIREWALL /* Firewall clock enable */ regval |= RCC_APB2ENR_FWEN; #endif -#ifdef CONFIG_STM32L4_SDMMC +#ifdef CONFIG_STM32_SDMMC /* SDMMC clock enable */ regval |= RCC_APB2ENR_SDMMCEN; #endif -#ifdef CONFIG_STM32L4_TIM1 +#ifdef CONFIG_STM32_TIM1 /* TIM1 clock enable */ regval |= RCC_APB2ENR_TIM1EN; #endif -#ifdef CONFIG_STM32L4_SPI1 +#ifdef CONFIG_STM32_SPI1 /* SPI1 clock enable */ regval |= RCC_APB2ENR_SPI1EN; #endif -#ifdef CONFIG_STM32L4_TIM8 +#ifdef CONFIG_STM32_TIM8 /* TIM8 clock enable */ regval |= RCC_APB2ENR_TIM8EN; #endif -#ifdef CONFIG_STM32L4_USART1 +#ifdef CONFIG_STM32_USART1 /* USART1 clock enable */ regval |= RCC_APB2ENR_USART1EN; #endif -#ifdef CONFIG_STM32L4_TIM15 +#ifdef CONFIG_STM32_TIM15 /* TIM15 clock enable */ regval |= RCC_APB2ENR_TIM15EN; #endif -#ifdef CONFIG_STM32L4_TIM16 +#ifdef CONFIG_STM32_TIM16 /* TIM16 clock enable */ regval |= RCC_APB2ENR_TIM16EN; #endif -#ifdef CONFIG_STM32L4_TIM17 +#ifdef CONFIG_STM32_TIM17 /* TIM17 clock enable */ regval |= RCC_APB2ENR_TIM17EN; #endif -#ifdef CONFIG_STM32L4_SAI1 +#ifdef CONFIG_STM32_SAI1 /* SAI1 clock enable */ regval |= RCC_APB2ENR_SAI1EN; #endif -#ifdef CONFIG_STM32L4_SAI2 +#ifdef CONFIG_STM32_SAI2 /* SAI2 clock enable */ regval |= RCC_APB2ENR_SAI2EN; #endif -#ifdef CONFIG_STM32L4_DFSDM1 +#ifdef CONFIG_STM32_DFSDM1 /* DFSDM clock enable */ regval |= RCC_APB2ENR_DFSDMEN; #endif - putreg32(regval, STM32L4_RCC_APB2ENR); /* Enable peripherals */ + putreg32(regval, STM32_RCC_APB2ENR); /* Enable peripherals */ } /**************************************************************************** @@ -531,57 +531,57 @@ static inline void rcc_enableccip(void) * will at least have a clock. */ - regval = getreg32(STM32L4_RCC_CCIPR); + regval = getreg32(STM32_RCC_CCIPR); -#if defined(STM32L4_I2C_USE_HSI16) -#ifdef CONFIG_STM32L4_I2C1 +#if defined(STM32_I2C_USE_HSI16) +#ifdef CONFIG_STM32_I2C1 /* Select HSI16 as I2C1 clock source. */ regval &= ~RCC_CCIPR_I2C1SEL_MASK; regval |= RCC_CCIPR_I2C1SEL_HSI; #endif -#ifdef CONFIG_STM32L4_I2C2 +#ifdef CONFIG_STM32_I2C2 /* Select HSI16 as I2C2 clock source. */ regval &= ~RCC_CCIPR_I2C2SEL_MASK; regval |= RCC_CCIPR_I2C2SEL_HSI; #endif -#ifdef CONFIG_STM32L4_I2C3 +#ifdef CONFIG_STM32_I2C3 /* Select HSI16 as I2C3 clock source. */ regval &= ~RCC_CCIPR_I2C3SEL_MASK; regval |= RCC_CCIPR_I2C3SEL_HSI; #endif -#endif /* STM32L4_I2C_USE_HSI16 */ +#endif /* STM32_I2C_USE_HSI16 */ -#if defined(STM32L4_USE_CLK48) +#if defined(STM32_USE_CLK48) /* XXX sanity if sdmmc1 or usb or rng, then we need to set the clk48 source - * and then we can also do away with STM32L4_USE_CLK48, and give better + * and then we can also do away with STM32_USE_CLK48, and give better * warning messages. */ regval &= ~RCC_CCIPR_CLK48SEL_MASK; - regval |= STM32L4_CLK48_SEL; + regval |= STM32_CLK48_SEL; #endif -#if defined(CONFIG_STM32L4_ADC1) || defined(CONFIG_STM32L4_ADC2) || defined(CONFIG_STM32L4_ADC3) +#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) || defined(CONFIG_STM32_ADC3) /* Select SYSCLK as ADC clock source */ regval &= ~RCC_CCIPR_ADCSEL_MASK; regval |= RCC_CCIPR_ADCSEL_SYSCLK; #endif -#ifdef CONFIG_STM32L4_DFSDM1 +#ifdef CONFIG_STM32_DFSDM1 /* Select SYSCLK as DFSDM clock source */ regval |= RCC_CCIPR_DFSDMSEL_SYSCLK; #endif - putreg32(regval, STM32L4_RCC_CCIPR); + putreg32(regval, STM32_RCC_CCIPR); } /**************************************************************************** - * Name: stm32l4_stdclockconfig + * Name: stm32_stdclockconfig * * Description: * Called to change to new clock based on settings in board.h @@ -590,18 +590,18 @@ static inline void rcc_enableccip(void) * power clocking modes! ****************************************************************************/ -#ifndef CONFIG_ARCH_BOARD_STM32L4_CUSTOM_CLOCKCONFIG -static void stm32l4_stdclockconfig(void) +#ifndef CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG +static void stm32_stdclockconfig(void) { uint32_t regval; volatile int32_t timeout; -#if defined(STM32L4_BOARD_USEHSI) || defined(STM32L4_I2C_USE_HSI16) +#if defined(STM32_BOARD_USEHSI) || defined(STM32_I2C_USE_HSI16) /* Enable Internal High-Speed Clock (HSI) */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_HSION; /* Enable HSI */ - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Wait until the HSI is ready (or until a timeout elapsed) */ @@ -609,7 +609,7 @@ static void stm32l4_stdclockconfig(void) { /* Check if the HSIRDY flag is the set in the CR */ - if ((getreg32(STM32L4_RCC_CR) & RCC_CR_HSIRDY) != 0) + if ((getreg32(STM32_RCC_CR) & RCC_CR_HSIRDY) != 0) { /* If so, then break-out with timeout > 0 */ @@ -618,17 +618,17 @@ static void stm32l4_stdclockconfig(void) } #endif -#if defined(STM32L4_BOARD_USEHSI) +#if defined(STM32_BOARD_USEHSI) /* Already set above */ -#elif defined(STM32L4_BOARD_USEMSI) +#elif defined(STM32_BOARD_USEMSI) /* Enable Internal Multi-Speed Clock (MSI) */ /* Wait until the MSI is either off or ready (or until a timeout elapsed) */ for (timeout = MSIRDY_TIMEOUT; timeout > 0; timeout--) { - if ((regval = getreg32(STM32L4_RCC_CR)), (regval & RCC_CR_MSIRDY) || + if ((regval = getreg32(STM32_RCC_CR)), (regval & RCC_CR_MSIRDY) || ~(regval & RCC_CR_MSION)) { /* If so, then break-out with timeout > 0 */ @@ -639,10 +639,10 @@ static void stm32l4_stdclockconfig(void) /* setting MSIRANGE */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval &= ~RCC_CR_MSIRANGE_MASK; - regval |= (STM32L4_BOARD_MSIRANGE | RCC_CR_MSION); /* Enable MSI and frequency */ - putreg32(regval, STM32L4_RCC_CR); + regval |= (STM32_BOARD_MSIRANGE | RCC_CR_MSION); /* Enable MSI and frequency */ + putreg32(regval, STM32_RCC_CR); /* Wait until the MSI is ready (or until a timeout elapsed) */ @@ -650,7 +650,7 @@ static void stm32l4_stdclockconfig(void) { /* Check if the MSIRDY flag is the set in the CR */ - if ((getreg32(STM32L4_RCC_CR) & RCC_CR_MSIRDY) != 0) + if ((getreg32(STM32_RCC_CR) & RCC_CR_MSIRDY) != 0) { /* If so, then break-out with timeout > 0 */ @@ -658,12 +658,12 @@ static void stm32l4_stdclockconfig(void) } } -#elif defined(STM32L4_BOARD_USEHSE) +#elif defined(STM32_BOARD_USEHSE) /* Enable External High-Speed Clock (HSE) */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_HSEON; /* Enable HSE */ - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Wait until the HSE is ready (or until a timeout elapsed) */ @@ -671,7 +671,7 @@ static void stm32l4_stdclockconfig(void) { /* Check if the HSERDY flag is the set in the CR */ - if ((getreg32(STM32L4_RCC_CR) & RCC_CR_HSERDY) != 0) + if ((getreg32(STM32_RCC_CR) & RCC_CR_HSERDY) != 0) { /* If so, then break-out with timeout > 0 */ @@ -680,7 +680,7 @@ static void stm32l4_stdclockconfig(void) } #else -# error stm32l4_stdclockconfig(), must have one of STM32L4_BOARD_USEHSI, STM32L4_BOARD_USEMSI, STM32L4_BOARD_USEHSE defined +# error stm32_stdclockconfig(), must have one of STM32_BOARD_USEHSI, STM32_BOARD_USEMSI, STM32_BOARD_USEHSE defined #endif @@ -695,154 +695,154 @@ static void stm32l4_stdclockconfig(void) #if 0 /* Ensure Power control is enabled before modifying it. */ - regval = getreg32(STM32L4_RCC_APB1ENR1); + regval = getreg32(STM32_RCC_APB1ENR1); regval |= RCC_APB1ENR1_PWREN; - putreg32(regval, STM32L4_RCC_APB1ENR1); + putreg32(regval, STM32_RCC_APB1ENR1); /* Select regulator voltage output Scale 1 mode to support system * frequencies up to 168 MHz. */ - regval = getreg32(STM32L4_PWR_CR); + regval = getreg32(STM32_PWR_CR); regval &= ~PWR_CR_VOS_MASK; regval |= PWR_CR_VOS_SCALE_1; - putreg32(regval, STM32L4_PWR_CR); + putreg32(regval, STM32_PWR_CR); #endif /* Set the HCLK source/divider */ - regval = getreg32(STM32L4_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_HPRE_MASK; - regval |= STM32L4_RCC_CFGR_HPRE; - putreg32(regval, STM32L4_RCC_CFGR); + regval |= STM32_RCC_CFGR_HPRE; + putreg32(regval, STM32_RCC_CFGR); /* Set the PCLK2 divider */ - regval = getreg32(STM32L4_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_PPRE2_MASK; - regval |= STM32L4_RCC_CFGR_PPRE2; - putreg32(regval, STM32L4_RCC_CFGR); + regval |= STM32_RCC_CFGR_PPRE2; + putreg32(regval, STM32_RCC_CFGR); /* Set the PCLK1 divider */ - regval = getreg32(STM32L4_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_PPRE1_MASK; - regval |= STM32L4_RCC_CFGR_PPRE1; - putreg32(regval, STM32L4_RCC_CFGR); + regval |= STM32_RCC_CFGR_PPRE1; + putreg32(regval, STM32_RCC_CFGR); /* Set the PLL source and main divider */ - regval = getreg32(STM32L4_RCC_PLLCFG); + regval = getreg32(STM32_RCC_PLLCFG); /* Configure Main PLL */ /* Set the PLL dividers and multipliers to configure the main PLL */ - regval = (STM32L4_PLLCFG_PLLM | STM32L4_PLLCFG_PLLN | - STM32L4_PLLCFG_PLLP | STM32L4_PLLCFG_PLLQ | - STM32L4_PLLCFG_PLLR); + regval = (STM32_PLLCFG_PLLM | STM32_PLLCFG_PLLN | + STM32_PLLCFG_PLLP | STM32_PLLCFG_PLLQ | + STM32_PLLCFG_PLLR); -#ifdef STM32L4_PLLCFG_PLLP_ENABLED +#ifdef STM32_PLLCFG_PLLP_ENABLED regval |= RCC_PLLCFG_PLLPEN; #endif -#ifdef STM32L4_PLLCFG_PLLQ_ENABLED +#ifdef STM32_PLLCFG_PLLQ_ENABLED regval |= RCC_PLLCFG_PLLQEN; #endif -#ifdef STM32L4_PLLCFG_PLLR_ENABLED +#ifdef STM32_PLLCFG_PLLR_ENABLED regval |= RCC_PLLCFG_PLLREN; #endif /* XXX The choice of clock source to PLL (all three) is independent - * of the sys clock source choice, review the STM32L4_BOARD_USEHSI + * of the sys clock source choice, review the STM32_BOARD_USEHSI * name; probably split it into two, one for PLL source and one * for sys clock source. */ -#ifdef STM32L4_BOARD_USEHSI +#ifdef STM32_BOARD_USEHSI regval |= RCC_PLLCFG_PLLSRC_HSI; -#elif defined(STM32L4_BOARD_USEMSI) +#elif defined(STM32_BOARD_USEMSI) regval |= RCC_PLLCFG_PLLSRC_MSI; -#else /* if STM32L4_BOARD_USEHSE */ +#else /* if STM32_BOARD_USEHSE */ regval |= RCC_PLLCFG_PLLSRC_HSE; #endif - putreg32(regval, STM32L4_RCC_PLLCFG); + putreg32(regval, STM32_RCC_PLLCFG); /* Enable the main PLL */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_PLLON; - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Wait until the PLL is ready */ - while ((getreg32(STM32L4_RCC_CR) & RCC_CR_PLLRDY) == 0) + while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLRDY) == 0) { } -#ifdef CONFIG_STM32L4_SAI1PLL +#ifdef CONFIG_STM32_SAI1PLL /* Configure SAI1 PLL */ - regval = getreg32(STM32L4_RCC_PLLSAI1CFG); + regval = getreg32(STM32_RCC_PLLSAI1CFG); /* Set the PLL dividers and multipliers to configure the SAI1 PLL */ - regval = (STM32L4_PLLSAI1CFG_PLLN | STM32L4_PLLSAI1CFG_PLLP - | STM32L4_PLLSAI1CFG_PLLQ | STM32L4_PLLSAI1CFG_PLLR); + regval = (STM32_PLLSAI1CFG_PLLN | STM32_PLLSAI1CFG_PLLP + | STM32_PLLSAI1CFG_PLLQ | STM32_PLLSAI1CFG_PLLR); -#ifdef STM32L4_PLLSAI1CFG_PLLP_ENABLED +#ifdef STM32_PLLSAI1CFG_PLLP_ENABLED regval |= RCC_PLLSAI1CFG_PLLPEN; #endif -#ifdef STM32L4_PLLSAI1CFG_PLLQ_ENABLED +#ifdef STM32_PLLSAI1CFG_PLLQ_ENABLED regval |= RCC_PLLSAI1CFG_PLLQEN; #endif -#ifdef STM32L4_PLLSAI1CFG_PLLR_ENABLED +#ifdef STM32_PLLSAI1CFG_PLLR_ENABLED regval |= RCC_PLLSAI1CFG_PLLREN; #endif - putreg32(regval, STM32L4_RCC_PLLSAI1CFG); + putreg32(regval, STM32_RCC_PLLSAI1CFG); /* Enable the SAI1 PLL */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_PLLSAI1ON; - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Wait until the PLL is ready */ - while ((getreg32(STM32L4_RCC_CR) & RCC_CR_PLLSAI1RDY) == 0) + while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLSAI1RDY) == 0) { } #endif -#ifdef CONFIG_STM32L4_SAI2PLL +#ifdef CONFIG_STM32_SAI2PLL /* Configure SAI2 PLL */ - regval = getreg32(STM32L4_RCC_PLLSAI2CFG); + regval = getreg32(STM32_RCC_PLLSAI2CFG); /* Set the PLL dividers and multipliers to configure the SAI2 PLL */ - regval = (STM32L4_PLLSAI2CFG_PLLN | STM32L4_PLLSAI2CFG_PLLP | - STM32L4_PLLSAI2CFG_PLLR); + regval = (STM32_PLLSAI2CFG_PLLN | STM32_PLLSAI2CFG_PLLP | + STM32_PLLSAI2CFG_PLLR); -#ifdef STM32L4_PLLSAI2CFG_PLLP_ENABLED +#ifdef STM32_PLLSAI2CFG_PLLP_ENABLED regval |= RCC_PLLSAI2CFG_PLLPEN; #endif -#ifdef STM32L4_PLLSAI2CFG_PLLR_ENABLED +#ifdef STM32_PLLSAI2CFG_PLLR_ENABLED regval |= RCC_PLLSAI2CFG_PLLREN; #endif - putreg32(regval, STM32L4_RCC_PLLSAI2CFG); + putreg32(regval, STM32_RCC_PLLSAI2CFG); /* Enable the SAI2 PLL */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_PLLSAI2ON; - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Wait until the PLL is ready */ - while ((getreg32(STM32L4_RCC_CR) & RCC_CR_PLLSAI2RDY) == 0) + while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLSAI2RDY) == 0) { } #endif @@ -851,35 +851,35 @@ static void stm32l4_stdclockconfig(void) * and 4 wait states */ -#ifdef CONFIG_STM32L4_FLASH_PREFETCH +#ifdef CONFIG_STM32_FLASH_PREFETCH regval = (FLASH_ACR_LATENCY_4 | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_PRFTEN); #else regval = (FLASH_ACR_LATENCY_4 | FLASH_ACR_ICEN | FLASH_ACR_DCEN); #endif - putreg32(regval, STM32L4_FLASH_ACR); + putreg32(regval, STM32_FLASH_ACR); /* Select the main PLL as system clock source */ - regval = getreg32(STM32L4_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_SW_MASK; regval |= RCC_CFGR_SW_PLL; - putreg32(regval, STM32L4_RCC_CFGR); + putreg32(regval, STM32_RCC_CFGR); /* Wait until the PLL source is used as the system clock source */ - while ((getreg32(STM32L4_RCC_CFGR) & RCC_CFGR_SWS_MASK) != + while ((getreg32(STM32_RCC_CFGR) & RCC_CFGR_SWS_MASK) != RCC_CFGR_SWS_PLL) { } -#if defined(CONFIG_STM32L4_IWDG) || defined(CONFIG_STM32L4_RTC_LSICLOCK) +#if defined(CONFIG_STM32_IWDG) || defined(CONFIG_STM32_RTC_LSICLOCK) /* Low speed internal clock source LSI */ - stm32l4_rcc_enablelsi(); + stm32_rcc_enablelsi(); #endif -#if defined(STM32L4_USE_LSE) +#if defined(STM32_USE_LSE) /* Low speed external clock source LSE * * TODO: There is another case where the LSE needs to @@ -891,7 +891,7 @@ static void stm32l4_stdclockconfig(void) * to alter the LSE parameters. */ - stm32l4_pwr_enableclk(true); + stm32_pwr_enableclk(true); /* XXX other LSE settings must be made before turning on the oscillator * and we need to ensure it is first off before doing so. @@ -902,16 +902,16 @@ static void stm32l4_stdclockconfig(void) * this for automatically trimming MSI, etc. */ - stm32l4_rcc_enablelse(); + stm32_rcc_enablelse(); -# if defined(STM32L4_BOARD_USEMSI) +# if defined(STM32_BOARD_USEMSI) /* Now that LSE is up, auto trim the MSI */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_MSIPLLEN; - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); # endif -#endif /* STM32L4_USE_LSE */ +#endif /* STM32_USE_LSE */ } } #endif diff --git a/arch/arm/src/stm32l4/stm32l4x6xx_dma.c b/arch/arm/src/stm32l4/stm32l4x6xx_dma.c index 355b3929c1ddc..3d9f0a7f91a9b 100644 --- a/arch/arm/src/stm32l4/stm32l4x6xx_dma.c +++ b/arch/arm/src/stm32l4/stm32l4x6xx_dma.c @@ -41,14 +41,14 @@ #include "sched/sched.h" #include "chip.h" #include "stm32l4_dma.h" -#include "stm32l4.h" +#include "stm32.h" /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ #define DMA1_NCHANNELS 7 -#if STM32L4_NDMA > 1 +#if STM32_NDMA > 1 # define DMA2_NCHANNELS 7 # define DMA_NCHANNELS (DMA1_NCHANNELS+DMA2_NCHANNELS) #else @@ -65,7 +65,7 @@ /* This structure describes one DMA channel */ -struct stm32l4_dma_s +struct stm32_dma_s { uint8_t chan; /* DMA channel number (0-6) */ uint8_t function; /* DMA peripheral connected to this channel (0-7) */ @@ -82,92 +82,92 @@ struct stm32l4_dma_s /* This array describes the state of each DMA */ -static struct stm32l4_dma_s g_dma[DMA_NCHANNELS] = +static struct stm32_dma_s g_dma[DMA_NCHANNELS] = { { .chan = 0, - .irq = STM32L4_IRQ_DMA1CH1, + .irq = STM32_IRQ_DMA1CH1, .sem = SEM_INITIALIZER(1), - .base = STM32L4_DMA1_BASE + STM32L4_DMACHAN_OFFSET(0), + .base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(0), }, { .chan = 1, - .irq = STM32L4_IRQ_DMA1CH2, + .irq = STM32_IRQ_DMA1CH2, .sem = SEM_INITIALIZER(1), - .base = STM32L4_DMA1_BASE + STM32L4_DMACHAN_OFFSET(1), + .base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(1), }, { .chan = 2, - .irq = STM32L4_IRQ_DMA1CH3, + .irq = STM32_IRQ_DMA1CH3, .sem = SEM_INITIALIZER(1), - .base = STM32L4_DMA1_BASE + STM32L4_DMACHAN_OFFSET(2), + .base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(2), }, { .chan = 3, - .irq = STM32L4_IRQ_DMA1CH4, + .irq = STM32_IRQ_DMA1CH4, .sem = SEM_INITIALIZER(1), - .base = STM32L4_DMA1_BASE + STM32L4_DMACHAN_OFFSET(3), + .base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(3), }, { .chan = 4, - .irq = STM32L4_IRQ_DMA1CH5, + .irq = STM32_IRQ_DMA1CH5, .sem = SEM_INITIALIZER(1), - .base = STM32L4_DMA1_BASE + STM32L4_DMACHAN_OFFSET(4), + .base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(4), }, { .chan = 5, - .irq = STM32L4_IRQ_DMA1CH6, + .irq = STM32_IRQ_DMA1CH6, .sem = SEM_INITIALIZER(1), - .base = STM32L4_DMA1_BASE + STM32L4_DMACHAN_OFFSET(5), + .base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(5), }, { .chan = 6, - .irq = STM32L4_IRQ_DMA1CH7, + .irq = STM32_IRQ_DMA1CH7, .sem = SEM_INITIALIZER(1), - .base = STM32L4_DMA1_BASE + STM32L4_DMACHAN_OFFSET(6), + .base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(6), }, -#if STM32L4_NDMA > 1 +#if STM32_NDMA > 1 { .chan = 0, - .irq = STM32L4_IRQ_DMA2CH1, + .irq = STM32_IRQ_DMA2CH1, .sem = SEM_INITIALIZER(1), - .base = STM32L4_DMA2_BASE + STM32L4_DMACHAN_OFFSET(0), + .base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(0), }, { .chan = 1, - .irq = STM32L4_IRQ_DMA2CH2, + .irq = STM32_IRQ_DMA2CH2, .sem = SEM_INITIALIZER(1), - .base = STM32L4_DMA2_BASE + STM32L4_DMACHAN_OFFSET(1), + .base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(1), }, { .chan = 2, - .irq = STM32L4_IRQ_DMA2CH3, + .irq = STM32_IRQ_DMA2CH3, .sem = SEM_INITIALIZER(1), - .base = STM32L4_DMA2_BASE + STM32L4_DMACHAN_OFFSET(2), + .base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(2), }, { .chan = 3, - .irq = STM32L4_IRQ_DMA2CH4, + .irq = STM32_IRQ_DMA2CH4, .sem = SEM_INITIALIZER(1), - .base = STM32L4_DMA2_BASE + STM32L4_DMACHAN_OFFSET(3), + .base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(3), }, { .chan = 4, - .irq = STM32L4_IRQ_DMA2CH5, + .irq = STM32_IRQ_DMA2CH5, .sem = SEM_INITIALIZER(1), - .base = STM32L4_DMA2_BASE + STM32L4_DMACHAN_OFFSET(4), + .base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(4), }, { .chan = 5, - .irq = STM32L4_IRQ_DMA2CH6, + .irq = STM32_IRQ_DMA2CH6, .sem = SEM_INITIALIZER(1), - .base = STM32L4_DMA2_BASE + STM32L4_DMACHAN_OFFSET(5), + .base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(5), }, { .chan = 6, - .irq = STM32L4_IRQ_DMA2CH7, + .irq = STM32_IRQ_DMA2CH7, .sem = SEM_INITIALIZER(1), - .base = STM32L4_DMA2_BASE + STM32L4_DMACHAN_OFFSET(6), + .base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(6), }, #endif }; @@ -182,7 +182,7 @@ static struct stm32l4_dma_s g_dma[DMA_NCHANNELS] = /* Get non-channel register from DMA1 or DMA2 */ -static inline uint32_t dmabase_getreg(struct stm32l4_dma_s *dmach, +static inline uint32_t dmabase_getreg(struct stm32_dma_s *dmach, uint32_t offset) { return getreg32(DMA_BASE(dmach->base) + offset); @@ -190,7 +190,7 @@ static inline uint32_t dmabase_getreg(struct stm32l4_dma_s *dmach, /* Write to non-channel register in DMA1 or DMA2 */ -static inline void dmabase_putreg(struct stm32l4_dma_s *dmach, +static inline void dmabase_putreg(struct stm32_dma_s *dmach, uint32_t offset, uint32_t value) { putreg32(value, DMA_BASE(dmach->base) + offset); @@ -198,7 +198,7 @@ static inline void dmabase_putreg(struct stm32l4_dma_s *dmach, /* Get channel register from DMA1 or DMA2 */ -static inline uint32_t dmachan_getreg(struct stm32l4_dma_s *dmach, +static inline uint32_t dmachan_getreg(struct stm32_dma_s *dmach, uint32_t offset) { return getreg32(dmach->base + offset); @@ -206,69 +206,69 @@ static inline uint32_t dmachan_getreg(struct stm32l4_dma_s *dmach, /* Write to channel register in DMA1 or DMA2 */ -static inline void dmachan_putreg(struct stm32l4_dma_s *dmach, +static inline void dmachan_putreg(struct stm32_dma_s *dmach, uint32_t offset, uint32_t value) { putreg32(value, dmach->base + offset); } /**************************************************************************** - * Name: stm32l4_dmachandisable + * Name: stm32_dmachandisable * * Description: * Disable the DMA channel * ****************************************************************************/ -static void stm32l4_dmachandisable(struct stm32l4_dma_s *dmach) +static void stm32_dmachandisable(struct stm32_dma_s *dmach) { uint32_t regval; /* Disable all interrupts at the DMA controller */ - regval = dmachan_getreg(dmach, STM32L4_DMACHAN_CCR_OFFSET); + regval = dmachan_getreg(dmach, STM32_DMACHAN_CCR_OFFSET); regval &= ~DMA_CCR_ALLINTS; /* Disable the DMA channel */ regval &= ~DMA_CCR_EN; - dmachan_putreg(dmach, STM32L4_DMACHAN_CCR_OFFSET, regval); + dmachan_putreg(dmach, STM32_DMACHAN_CCR_OFFSET, regval); /* Clear pending channel interrupts */ - dmabase_putreg(dmach, STM32L4_DMA_IFCR_OFFSET, + dmabase_putreg(dmach, STM32_DMA_IFCR_OFFSET, DMA_ISR_CHAN_MASK(dmach->chan)); } /**************************************************************************** - * Name: stm32l4_dmainterrupt + * Name: stm32_dmainterrupt * * Description: * DMA interrupt handler * ****************************************************************************/ -static int stm32l4_dmainterrupt(int irq, void *context, void *arg) +static int stm32_dmainterrupt(int irq, void *context, void *arg) { - struct stm32l4_dma_s *dmach; + struct stm32_dma_s *dmach; uint32_t isr; int chndx = 0; /* Get the channel structure from the interrupt number */ - if (irq >= STM32L4_IRQ_DMA1CH1 && irq <= STM32L4_IRQ_DMA1CH7) + if (irq >= STM32_IRQ_DMA1CH1 && irq <= STM32_IRQ_DMA1CH7) { - chndx = irq - STM32L4_IRQ_DMA1CH1; + chndx = irq - STM32_IRQ_DMA1CH1; } else -#if STM32L4_NDMA > 1 - if (irq >= STM32L4_IRQ_DMA2CH1 && irq <= STM32L4_IRQ_DMA2CH5) +#if STM32_NDMA > 1 + if (irq >= STM32_IRQ_DMA2CH1 && irq <= STM32_IRQ_DMA2CH5) { - chndx = irq - STM32L4_IRQ_DMA2CH1 + DMA1_NCHANNELS; + chndx = irq - STM32_IRQ_DMA2CH1 + DMA1_NCHANNELS; } - else if (irq >= STM32L4_IRQ_DMA2CH6 && irq <= STM32L4_IRQ_DMA2CH7) + else if (irq >= STM32_IRQ_DMA2CH6 && irq <= STM32_IRQ_DMA2CH7) { - chndx = irq - STM32L4_IRQ_DMA2CH6 + DMA1_NCHANNELS + 5; + chndx = irq - STM32_IRQ_DMA2CH6 + DMA1_NCHANNELS + 5; } #endif else @@ -280,7 +280,7 @@ static int stm32l4_dmainterrupt(int irq, void *context, void *arg) /* Get the interrupt status (for this channel only) */ - isr = dmabase_getreg(dmach, STM32L4_DMA_ISR_OFFSET) & + isr = dmabase_getreg(dmach, STM32_DMA_ISR_OFFSET) & DMA_ISR_CHAN_MASK(dmach->chan); /* Invoke the callback */ @@ -293,7 +293,7 @@ static int stm32l4_dmainterrupt(int irq, void *context, void *arg) /* Clear the interrupts we are handling */ - dmabase_putreg(dmach, STM32L4_DMA_IFCR_OFFSET, isr); + dmabase_putreg(dmach, STM32_DMA_IFCR_OFFSET, isr); return OK; } @@ -303,7 +303,7 @@ static int stm32l4_dmainterrupt(int irq, void *context, void *arg) ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_dmainitialize + * Name: stm32_dmainitialize * * Description: * Initialize the DMA subsystem @@ -315,7 +315,7 @@ static int stm32l4_dmainterrupt(int irq, void *context, void *arg) void weak_function arm_dma_initialize(void) { - struct stm32l4_dma_s *dmach; + struct stm32_dma_s *dmach; int chndx; /* Initialize each DMA channel */ @@ -326,11 +326,11 @@ void weak_function arm_dma_initialize(void) /* Attach DMA interrupt vectors */ - irq_attach(dmach->irq, stm32l4_dmainterrupt, NULL); + irq_attach(dmach->irq, stm32_dmainterrupt, NULL); /* Disable the DMA channel */ - stm32l4_dmachandisable(dmach); + stm32_dmachandisable(dmach); /* Enable the IRQ at the NVIC (still disabled at the DMA controller) */ @@ -339,7 +339,7 @@ void weak_function arm_dma_initialize(void) } /**************************************************************************** - * Name: stm32l4_dmachannel + * Name: stm32_dmachannel * * Description: * Allocate a DMA channel. This function gives the caller mutually @@ -348,10 +348,10 @@ void weak_function arm_dma_initialize(void) * channel cannot do DMA concurrently! See the DMACHAN_* definitions in * stm32l4_dma.h. * - * If the DMA channel is not available, then stm32l4_dmachannel() will wait + * If the DMA channel is not available, then stm32_dmachannel() will wait * until the holder of the channel relinquishes the channel by calling - * stm32l4_dmafree(). WARNING: If you have two devices sharing a DMA - * channel and the code never releases the channel, the stm32l4_dmachannel + * stm32_dmafree(). WARNING: If you have two devices sharing a DMA + * channel and the code never releases the channel, the stm32_dmachannel * call for the other will hang forever in this function! Don't let your * design do that! * @@ -375,12 +375,12 @@ void weak_function arm_dma_initialize(void) * ****************************************************************************/ -DMA_HANDLE stm32l4_dmachannel(unsigned int chndef) +DMA_HANDLE stm32_dmachannel(unsigned int chndef) { int ret; int chndx = (chndef & DMACHAN_SETTING_CHANNEL_MASK) >> DMACHAN_SETTING_CHANNEL_SHIFT; - struct stm32l4_dma_s *dmach = &g_dma[chndx]; + struct stm32_dma_s *dmach = &g_dma[chndx]; DEBUGASSERT(chndx < DMA_NCHANNELS); @@ -407,13 +407,13 @@ DMA_HANDLE stm32l4_dmachannel(unsigned int chndef) } /**************************************************************************** - * Name: stm32l4_dmafree + * Name: stm32_dmafree * * Description: * Release a DMA channel. If another thread is waiting for this DMA channel - * in a call to stm32l4_dmachannel, then this function will re-assign the + * in a call to stm32_dmachannel, then this function will re-assign the * DMA channel to that thread and wake it up. NOTE: The 'handle' used - * in this argument must NEVER be used again until stm32l4_dmachannel() is + * in this argument must NEVER be used again until stm32_dmachannel() is * called again to re-gain access to the channel. * * Returned Value: @@ -425,9 +425,9 @@ DMA_HANDLE stm32l4_dmachannel(unsigned int chndef) * ****************************************************************************/ -void stm32l4_dmafree(DMA_HANDLE handle) +void stm32_dmafree(DMA_HANDLE handle) { - struct stm32l4_dma_s *dmach = (struct stm32l4_dma_s *)handle; + struct stm32_dma_s *dmach = (struct stm32_dma_s *)handle; DEBUGASSERT(handle != NULL); @@ -437,17 +437,17 @@ void stm32l4_dmafree(DMA_HANDLE handle) } /**************************************************************************** - * Name: stm32l4_dmasetup + * Name: stm32_dmasetup * * Description: * Configure DMA before using * ****************************************************************************/ -void stm32l4_dmasetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr, +void stm32_dmasetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr, size_t ntransfers, uint32_t ccr) { - struct stm32l4_dma_s *dmach = (struct stm32l4_dma_s *)handle; + struct stm32_dma_s *dmach = (struct stm32_dma_s *)handle; uint32_t regval; DEBUGASSERT(handle != NULL); @@ -457,28 +457,28 @@ void stm32l4_dmasetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr, * disabled. */ - regval = dmachan_getreg(dmach, STM32L4_DMACHAN_CCR_OFFSET); + regval = dmachan_getreg(dmach, STM32_DMACHAN_CCR_OFFSET); regval &= ~(DMA_CCR_EN); - dmachan_putreg(dmach, STM32L4_DMACHAN_CCR_OFFSET, regval); + dmachan_putreg(dmach, STM32_DMACHAN_CCR_OFFSET, regval); /* Set the peripheral register address in the DMA_CPARx register. The data * will be moved from/to this address to/from the memory after the * peripheral event. */ - dmachan_putreg(dmach, STM32L4_DMACHAN_CPAR_OFFSET, paddr); + dmachan_putreg(dmach, STM32_DMACHAN_CPAR_OFFSET, paddr); /* Set the memory address in the DMA_CMARx register. The data will be * written to or read from this memory after the peripheral event. */ - dmachan_putreg(dmach, STM32L4_DMACHAN_CMAR_OFFSET, maddr); + dmachan_putreg(dmach, STM32_DMACHAN_CMAR_OFFSET, maddr); /* Configure the total number of data to be transferred in the DMA_CNDTRx * register. After each peripheral event, this value will be decremented. */ - dmachan_putreg(dmach, STM32L4_DMACHAN_CNDTR_OFFSET, ntransfers); + dmachan_putreg(dmach, STM32_DMACHAN_CNDTR_OFFSET, ntransfers); /* Configure the channel priority using the PL[1:0] bits in the DMA_CCRx * register. Configure data transfer direction, circular mode, peripheral @@ -486,7 +486,7 @@ void stm32l4_dmasetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr, * interrupt after half and/or full transfer in the DMA_CCRx register. */ - regval = dmachan_getreg(dmach, STM32L4_DMACHAN_CCR_OFFSET); + regval = dmachan_getreg(dmach, STM32_DMACHAN_CCR_OFFSET); regval &= ~(DMA_CCR_MEM2MEM | DMA_CCR_PL_MASK | DMA_CCR_MSIZE_MASK | DMA_CCR_PSIZE_MASK | DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC | DMA_CCR_DIR); @@ -494,32 +494,32 @@ void stm32l4_dmasetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr, DMA_CCR_PSIZE_MASK | DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC | DMA_CCR_DIR); regval |= ccr; - dmachan_putreg(dmach, STM32L4_DMACHAN_CCR_OFFSET, regval); + dmachan_putreg(dmach, STM32_DMACHAN_CCR_OFFSET, regval); /* define peripheral indicated in dmach->function */ - regval = dmabase_getreg(dmach, STM32L4_DMA_CSELR_OFFSET); + regval = dmabase_getreg(dmach, STM32_DMA_CSELR_OFFSET); regval &= ~(0x0f << (dmach->chan << 2)); regval |= (dmach->function << (dmach->chan << 2)); - dmabase_putreg(dmach, STM32L4_DMA_CSELR_OFFSET, regval); + dmabase_putreg(dmach, STM32_DMA_CSELR_OFFSET, regval); } /**************************************************************************** - * Name: stm32l4_dmastart + * Name: stm32_dmastart * * Description: * Start the DMA transfer * * Assumptions: - * - DMA handle allocated by stm32l4_dmachannel() + * - DMA handle allocated by stm32_dmachannel() * - No DMA in progress * ****************************************************************************/ -void stm32l4_dmastart(DMA_HANDLE handle, dma_callback_t callback, +void stm32_dmastart(DMA_HANDLE handle, dma_callback_t callback, void *arg, bool half) { - struct stm32l4_dma_s *dmach = (struct stm32l4_dma_s *)handle; + struct stm32_dma_s *dmach = (struct stm32_dma_s *)handle; uint32_t ccr; DEBUGASSERT(handle != NULL); @@ -534,7 +534,7 @@ void stm32l4_dmastart(DMA_HANDLE handle, dma_callback_t callback, * peripheral connected on the channel. */ - ccr = dmachan_getreg(dmach, STM32L4_DMACHAN_CCR_OFFSET); + ccr = dmachan_getreg(dmach, STM32_DMACHAN_CCR_OFFSET); ccr |= DMA_CCR_EN; /* In normal mode, interrupt at either half or full completion. In circular @@ -567,48 +567,48 @@ void stm32l4_dmastart(DMA_HANDLE handle, dma_callback_t callback, ccr |= (half ? DMA_CCR_HTIE : 0) | DMA_CCR_TCIE | DMA_CCR_TEIE; } - dmachan_putreg(dmach, STM32L4_DMACHAN_CCR_OFFSET, ccr); + dmachan_putreg(dmach, STM32_DMACHAN_CCR_OFFSET, ccr); } /**************************************************************************** - * Name: stm32l4_dmastop + * Name: stm32_dmastop * * Description: - * Cancel the DMA. After stm32l4_dmastop() is called, the DMA channel is - * reset and stm32l4_dmasetup() must be called before stm32l4_dmastart() + * Cancel the DMA. After stm32_dmastop() is called, the DMA channel is + * reset and stm32_dmasetup() must be called before stm32_dmastart() * can be called again * * Assumptions: - * - DMA handle allocated by stm32l4_dmachannel() + * - DMA handle allocated by stm32_dmachannel() * ****************************************************************************/ -void stm32l4_dmastop(DMA_HANDLE handle) +void stm32_dmastop(DMA_HANDLE handle) { - struct stm32l4_dma_s *dmach = (struct stm32l4_dma_s *)handle; - stm32l4_dmachandisable(dmach); + struct stm32_dma_s *dmach = (struct stm32_dma_s *)handle; + stm32_dmachandisable(dmach); } /**************************************************************************** - * Name: stm32l4_dmaresidual + * Name: stm32_dmaresidual * * Description: * Returns the number of bytes remaining to be transferred * * Assumptions: - * - DMA handle allocated by stm32l4_dmachannel() + * - DMA handle allocated by stm32_dmachannel() * ****************************************************************************/ -size_t stm32l4_dmaresidual(DMA_HANDLE handle) +size_t stm32_dmaresidual(DMA_HANDLE handle) { - struct stm32l4_dma_s *dmach = (struct stm32l4_dma_s *)handle; + struct stm32_dma_s *dmach = (struct stm32_dma_s *)handle; - return dmachan_getreg(dmach, STM32L4_DMACHAN_CNDTR_OFFSET); + return dmachan_getreg(dmach, STM32_DMACHAN_CNDTR_OFFSET); } /**************************************************************************** - * Name: stm32l4_dmacapable + * Name: stm32_dmacapable * * Description: * Check if the DMA controller can transfer data to/from given memory @@ -621,8 +621,8 @@ size_t stm32l4_dmaresidual(DMA_HANDLE handle) * ****************************************************************************/ -#ifdef CONFIG_STM32L4_DMACAPABLE -bool stm32l4_dmacapable(uint32_t maddr, uint32_t count, uint32_t ccr) +#ifdef CONFIG_STM32_DMACAPABLE +bool stm32_dmacapable(uint32_t maddr, uint32_t count, uint32_t ccr) { uint32_t transfer_size; uint32_t mend; @@ -667,22 +667,22 @@ bool stm32l4_dmacapable(uint32_t maddr, uint32_t count, uint32_t ccr) /* Verify that the transfer is to a memory region that supports DMA. */ - if ((maddr & STM32L4_REGION_MASK) != (mend & STM32L4_REGION_MASK)) + if ((maddr & STM32_REGION_MASK) != (mend & STM32_REGION_MASK)) { return false; } - switch (maddr & STM32L4_REGION_MASK) + switch (maddr & STM32_REGION_MASK) { - case STM32L4_PERIPH_BASE: - case STM32L4_FSMC_BASE: - case STM32L4_FSMC_BANK1: - case STM32L4_FSMC_BANK2: - case STM32L4_FSMC_BANK3: - case STM32L4_FSMC_BANK4: - case STM32L4_SRAM_BASE: - case STM32L4_SRAM2_BASE: - case STM32L4_CODE_BASE: + case STM32_PERIPH_BASE: + case STM32_FSMC_BASE: + case STM32_FSMC_BANK1: + case STM32_FSMC_BANK2: + case STM32_FSMC_BANK3: + case STM32_FSMC_BANK4: + case STM32_SRAM_BASE: + case STM32_SRAM2_BASE: + case STM32_CODE_BASE: /* All RAM and flash is supported */ @@ -698,63 +698,63 @@ bool stm32l4_dmacapable(uint32_t maddr, uint32_t count, uint32_t ccr) #endif /**************************************************************************** - * Name: stm32l4_dmasample + * Name: stm32_dmasample * * Description: * Sample DMA register contents * * Assumptions: - * - DMA handle allocated by stm32l4_dmachannel() + * - DMA handle allocated by stm32_dmachannel() * ****************************************************************************/ #ifdef CONFIG_DEBUG_DMA_INFO -void stm32l4_dmasample(DMA_HANDLE handle, struct stm32l4_dmaregs_s *regs) +void stm32_dmasample(DMA_HANDLE handle, struct stm32_dmaregs_s *regs) { - struct stm32l4_dma_s *dmach = (struct stm32l4_dma_s *)handle; + struct stm32_dma_s *dmach = (struct stm32_dma_s *)handle; irqstate_t flags; flags = enter_critical_section(); - regs->isr = dmabase_getreg(dmach, STM32L4_DMA_ISR_OFFSET); - regs->cselr = dmabase_getreg(dmach, STM32L4_DMA_CSELR_OFFSET); - regs->ccr = dmachan_getreg(dmach, STM32L4_DMACHAN_CCR_OFFSET); - regs->cndtr = dmachan_getreg(dmach, STM32L4_DMACHAN_CNDTR_OFFSET); - regs->cpar = dmachan_getreg(dmach, STM32L4_DMACHAN_CPAR_OFFSET); - regs->cmar = dmachan_getreg(dmach, STM32L4_DMACHAN_CMAR_OFFSET); + regs->isr = dmabase_getreg(dmach, STM32_DMA_ISR_OFFSET); + regs->cselr = dmabase_getreg(dmach, STM32_DMA_CSELR_OFFSET); + regs->ccr = dmachan_getreg(dmach, STM32_DMACHAN_CCR_OFFSET); + regs->cndtr = dmachan_getreg(dmach, STM32_DMACHAN_CNDTR_OFFSET); + regs->cpar = dmachan_getreg(dmach, STM32_DMACHAN_CPAR_OFFSET); + regs->cmar = dmachan_getreg(dmach, STM32_DMACHAN_CMAR_OFFSET); leave_critical_section(flags); } #endif /**************************************************************************** - * Name: stm32l4_dmadump + * Name: stm32_dmadump * * Description: * Dump previously sampled DMA register contents * * Assumptions: - * - DMA handle allocated by stm32l4_dmachannel() + * - DMA handle allocated by stm32_dmachannel() * ****************************************************************************/ #ifdef CONFIG_DEBUG_DMA_INFO -void stm32l4_dmadump(DMA_HANDLE handle, const struct stm32l4_dmaregs_s *regs, +void stm32_dmadump(DMA_HANDLE handle, const struct stm32_dmaregs_s *regs, const char *msg) { - struct stm32l4_dma_s *dmach = (struct stm32l4_dma_s *)handle; + struct stm32_dma_s *dmach = (struct stm32_dma_s *)handle; uint32_t dmabase = DMA_BASE(dmach->base); dmainfo("DMA Registers: %s\n", msg); dmainfo(" ISR[%08" PRIx32 "]: %08" PRIx32 "\n", - dmabase + STM32L4_DMA_ISR_OFFSET, regs->isr); + dmabase + STM32_DMA_ISR_OFFSET, regs->isr); dmainfo(" CSELR[%08" PRIx32 "]: %08" PRIx32 "\n", - dmabase + STM32L4_DMA_CSELR_OFFSET, regs->cselr); + dmabase + STM32_DMA_CSELR_OFFSET, regs->cselr); dmainfo(" CCR[%08" PRIx32 "]: %08" PRIx32 "\n", - dmach->base + STM32L4_DMACHAN_CCR_OFFSET, regs->ccr); + dmach->base + STM32_DMACHAN_CCR_OFFSET, regs->ccr); dmainfo(" CNDTR[%08" PRIx32 "]: %08" PRIx32 "\n", - dmach->base + STM32L4_DMACHAN_CNDTR_OFFSET, regs->cndtr); + dmach->base + STM32_DMACHAN_CNDTR_OFFSET, regs->cndtr); dmainfo(" CPAR[%08" PRIx32 "]: %08" PRIx32 "\n", - dmach->base + STM32L4_DMACHAN_CPAR_OFFSET, regs->cpar); + dmach->base + STM32_DMACHAN_CPAR_OFFSET, regs->cpar); dmainfo(" CMAR[%08" PRIx32 "]: %08" PRIx32 "\n", - dmach->base + STM32L4_DMACHAN_CMAR_OFFSET, regs->cmar); + dmach->base + STM32_DMACHAN_CMAR_OFFSET, regs->cmar); } #endif diff --git a/arch/arm/src/stm32l4/stm32l4x6xx_rcc.c b/arch/arm/src/stm32l4/stm32l4x6xx_rcc.c index 1673c9a2abd16..7e2aedd47365d 100644 --- a/arch/arm/src/stm32l4/stm32l4x6xx_rcc.c +++ b/arch/arm/src/stm32l4/stm32l4x6xx_rcc.c @@ -55,9 +55,9 @@ static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1, /* Determine if board wants to use HSI48 as 48 MHz oscillator. */ -#if defined(CONFIG_STM32L4_HAVE_HSI48) && defined(STM32L4_USE_CLK48) -# if STM32L4_CLK48_SEL == RCC_CCIPR_CLK48SEL_HSI48 -# define STM32L4_USE_HSI48 +#if defined(CONFIG_STM32_HAVE_HSI48) && defined(STM32_USE_CLK48) +# if STM32_CLK48_SEL == RCC_CCIPR_CLK48SEL_HSI48 +# define STM32_USE_HSI48 # endif #endif @@ -83,33 +83,33 @@ static inline void rcc_reset(void) /* Enable the Internal High Speed clock (HSI) */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_HSION; - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Reset CFGR register */ - putreg32(0x00000000, STM32L4_RCC_CFGR); + putreg32(0x00000000, STM32_RCC_CFGR); /* Reset HSION, HSEON, CSSON and PLLON bits */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval &= ~(RCC_CR_HSION | RCC_CR_HSEON | RCC_CR_CSSON | RCC_CR_PLLON); - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Reset PLLCFGR register to reset default */ - putreg32(RCC_PLLCFG_RESET, STM32L4_RCC_PLLCFG); + putreg32(RCC_PLLCFG_RESET, STM32_RCC_PLLCFG); /* Reset HSEBYP bit */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval &= ~RCC_CR_HSEBYP; - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Disable all interrupts */ - putreg32(0x00000000, STM32L4_RCC_CIER); + putreg32(0x00000000, STM32_RCC_CIER); } /**************************************************************************** @@ -128,39 +128,39 @@ static inline void rcc_enableahb1(void) * selected AHB1 peripherals. */ - regval = getreg32(STM32L4_RCC_AHB1ENR); + regval = getreg32(STM32_RCC_AHB1ENR); -#ifdef CONFIG_STM32L4_DMA1 +#ifdef CONFIG_STM32_DMA1 /* DMA 1 clock enable */ regval |= RCC_AHB1ENR_DMA1EN; #endif -#ifdef CONFIG_STM32L4_DMA2 +#ifdef CONFIG_STM32_DMA2 /* DMA 2 clock enable */ regval |= RCC_AHB1ENR_DMA2EN; #endif -#ifdef CONFIG_STM32L4_CRC +#ifdef CONFIG_STM32_CRC /* CRC clock enable */ regval |= RCC_AHB1ENR_CRCEN; #endif -#ifdef CONFIG_STM32L4_TSC +#ifdef CONFIG_STM32_TSC /* TSC clock enable */ regval |= RCC_AHB1ENR_TSCEN; #endif -#ifdef CONFIG_STM32L4_DMA2D +#ifdef CONFIG_STM32_DMA2D /* DMA2D clock enable */ regval |= RCC_AHB1ENR_DMA2DEN; #endif - putreg32(regval, STM32L4_RCC_AHB1ENR); /* Enable peripherals */ + putreg32(regval, STM32_RCC_AHB1ENR); /* Enable peripherals */ } /**************************************************************************** @@ -179,76 +179,76 @@ static inline void rcc_enableahb2(void) * selected AHB2 peripherals. */ - regval = getreg32(STM32L4_RCC_AHB2ENR); + regval = getreg32(STM32_RCC_AHB2ENR); /* Enable GPIOA, GPIOB, .... GPIOI */ -#if STM32L4_NPORTS > 0 +#if STM32_NPORTS > 0 regval |= (RCC_AHB2ENR_GPIOAEN -#if STM32L4_NPORTS > 1 +#if STM32_NPORTS > 1 | RCC_AHB2ENR_GPIOBEN #endif -#if STM32L4_NPORTS > 2 +#if STM32_NPORTS > 2 | RCC_AHB2ENR_GPIOCEN #endif -#if STM32L4_NPORTS > 3 +#if STM32_NPORTS > 3 | RCC_AHB2ENR_GPIODEN #endif -#if STM32L4_NPORTS > 4 +#if STM32_NPORTS > 4 | RCC_AHB2ENR_GPIOEEN #endif -#if STM32L4_NPORTS > 5 +#if STM32_NPORTS > 5 | RCC_AHB2ENR_GPIOFEN #endif -#if STM32L4_NPORTS > 6 +#if STM32_NPORTS > 6 | RCC_AHB2ENR_GPIOGEN #endif -#if STM32L4_NPORTS > 7 +#if STM32_NPORTS > 7 | RCC_AHB2ENR_GPIOHEN #endif -#if STM32L4_NPORTS > 8 +#if STM32_NPORTS > 8 | RCC_AHB2ENR_GPIOIEN #endif ); #endif -#ifdef CONFIG_STM32L4_OTGFS +#ifdef CONFIG_STM32_OTGFS /* USB OTG FS clock enable */ regval |= RCC_AHB2ENR_OTGFSEN; #endif -#if defined(CONFIG_STM32L4_ADC1) || defined(CONFIG_STM32L4_ADC2) || defined(CONFIG_STM32L4_ADC3) +#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) || defined(CONFIG_STM32_ADC3) /* ADC clock enable */ regval |= RCC_AHB2ENR_ADCEN; #endif -#ifdef CONFIG_STM32L4_DCMI +#ifdef CONFIG_STM32_DCMI /* Digital Camera interfaces clock enable */ regval |= RCC_AHB2ENR_DCMIEN; #endif -#ifdef CONFIG_STM32L4_AES +#ifdef CONFIG_STM32_AES /* Cryptographic modules clock enable */ regval |= RCC_AHB2ENR_AESEN; #endif -#ifdef CONFIG_STM32L4_HASH +#ifdef CONFIG_STM32_HASH /* HASH module clock enable */ regval |= RCC_AHB2ENR_HASHEN; #endif -#ifdef CONFIG_STM32L4_RNG +#ifdef CONFIG_STM32_RNG /* Random number generator clock enable */ regval |= RCC_AHB2ENR_RNGEN; #endif - putreg32(regval, STM32L4_RCC_AHB2ENR); /* Enable peripherals */ + putreg32(regval, STM32_RCC_AHB2ENR); /* Enable peripherals */ } /**************************************************************************** @@ -267,21 +267,21 @@ static inline void rcc_enableahb3(void) * selected AHB3 peripherals. */ - regval = getreg32(STM32L4_RCC_AHB3ENR); + regval = getreg32(STM32_RCC_AHB3ENR); -#ifdef CONFIG_STM32L4_FSMC +#ifdef CONFIG_STM32_FSMC /* Flexible static memory controller module clock enable */ regval |= RCC_AHB3ENR_FSMCEN; #endif -#ifdef CONFIG_STM32L4_QSPI +#ifdef CONFIG_STM32_QSPI /* QuadSPI module clock enable */ regval |= RCC_AHB3ENR_QSPIEN; #endif - putreg32(regval, STM32L4_RCC_AHB3ENR); /* Enable peripherals */ + putreg32(regval, STM32_RCC_AHB3ENR); /* Enable peripherals */ } /**************************************************************************** @@ -300,118 +300,118 @@ static inline void rcc_enableapb1(void) * selected APB1 peripherals. */ - regval = getreg32(STM32L4_RCC_APB1ENR1); + regval = getreg32(STM32_RCC_APB1ENR1); -#ifdef CONFIG_STM32L4_TIM2 +#ifdef CONFIG_STM32_TIM2 /* TIM2 clock enable */ regval |= RCC_APB1ENR1_TIM2EN; #endif -#ifdef CONFIG_STM32L4_TIM3 +#ifdef CONFIG_STM32_TIM3 /* TIM3 clock enable */ regval |= RCC_APB1ENR1_TIM3EN; #endif -#ifdef CONFIG_STM32L4_TIM4 +#ifdef CONFIG_STM32_TIM4 /* TIM4 clock enable */ regval |= RCC_APB1ENR1_TIM4EN; #endif -#ifdef CONFIG_STM32L4_TIM5 +#ifdef CONFIG_STM32_TIM5 /* TIM5 clock enable */ regval |= RCC_APB1ENR1_TIM5EN; #endif -#ifdef CONFIG_STM32L4_TIM6 +#ifdef CONFIG_STM32_TIM6 /* TIM6 clock enable */ regval |= RCC_APB1ENR1_TIM6EN; #endif -#ifdef CONFIG_STM32L4_TIM7 +#ifdef CONFIG_STM32_TIM7 /* TIM7 clock enable */ regval |= RCC_APB1ENR1_TIM7EN; #endif -#ifdef CONFIG_STM32L4_LCD +#ifdef CONFIG_STM32_LCD /* LCD clock enable */ regval |= RCC_APB1ENR1_LCDEN; #endif -#ifdef CONFIG_STM32L4_SPI2 +#ifdef CONFIG_STM32_SPI2 /* SPI2 clock enable */ regval |= RCC_APB1ENR1_SPI2EN; #endif -#ifdef CONFIG_STM32L4_SPI3 +#ifdef CONFIG_STM32_SPI3 /* SPI3 clock enable */ regval |= RCC_APB1ENR1_SPI3EN; #endif -#ifdef CONFIG_STM32L4_USART2 +#ifdef CONFIG_STM32_USART2 /* USART 2 clock enable */ regval |= RCC_APB1ENR1_USART2EN; #endif -#ifdef CONFIG_STM32L4_USART3 +#ifdef CONFIG_STM32_USART3 /* USART3 clock enable */ regval |= RCC_APB1ENR1_USART3EN; #endif -#ifdef CONFIG_STM32L4_UART4 +#ifdef CONFIG_STM32_UART4 /* UART4 clock enable */ regval |= RCC_APB1ENR1_UART4EN; #endif -#ifdef CONFIG_STM32L4_UART5 +#ifdef CONFIG_STM32_UART5 /* UART5 clock enable */ regval |= RCC_APB1ENR1_UART5EN; #endif -#ifdef CONFIG_STM32L4_I2C1 +#ifdef CONFIG_STM32_I2C1 /* I2C1 clock enable */ regval |= RCC_APB1ENR1_I2C1EN; #endif -#ifdef CONFIG_STM32L4_I2C2 +#ifdef CONFIG_STM32_I2C2 /* I2C2 clock enable */ regval |= RCC_APB1ENR1_I2C2EN; #endif -#ifdef CONFIG_STM32L4_I2C3 +#ifdef CONFIG_STM32_I2C3 /* I2C3 clock enable */ regval |= RCC_APB1ENR1_I2C3EN; #endif -#ifdef CONFIG_STM32L4_CAN1 +#ifdef CONFIG_STM32_CAN1 /* CAN 1 clock enable */ regval |= RCC_APB1ENR1_CAN1EN; #endif -#ifdef CONFIG_STM32L4_CAN2 +#ifdef CONFIG_STM32_CAN2 /* CAN 2 clock enable */ regval |= RCC_APB1ENR1_CAN2EN; #endif -#ifdef STM32L4_USE_HSI48 - if (STM32L4_HSI48_SYNCSRC != SYNCSRC_NONE) +#ifdef STM32_USE_HSI48 + if (STM32_HSI48_SYNCSRC != SYNCSRC_NONE) { /* Clock Recovery System clock enable */ @@ -425,55 +425,55 @@ static inline void rcc_enableapb1(void) regval |= RCC_APB1ENR1_PWREN; -#if defined (CONFIG_STM32L4_DAC1) || defined(CONFIG_STM32L4_DAC2) +#if defined (CONFIG_STM32_DAC1) || defined(CONFIG_STM32_DAC2) /* DAC interface clock enable */ regval |= RCC_APB1ENR1_DAC1EN; #endif -#ifdef CONFIG_STM32L4_OPAMP +#ifdef CONFIG_STM32_OPAMP /* OPAMP clock enable */ regval |= RCC_APB1ENR1_OPAMPEN; #endif -#ifdef CONFIG_STM32L4_LPTIM1 +#ifdef CONFIG_STM32_LPTIM1 /* Low power timer 1 clock enable */ regval |= RCC_APB1ENR1_LPTIM1EN; #endif - putreg32(regval, STM32L4_RCC_APB1ENR1); /* Enable peripherals */ + putreg32(regval, STM32_RCC_APB1ENR1); /* Enable peripherals */ /* Second APB1 register */ - regval = getreg32(STM32L4_RCC_APB1ENR2); + regval = getreg32(STM32_RCC_APB1ENR2); -#ifdef CONFIG_STM32L4_LPUART1 +#ifdef CONFIG_STM32_LPUART1 /* Low power uart clock enable */ regval |= RCC_APB1ENR2_LPUART1EN; #endif -#ifdef CONFIG_STM32L4_I2C4 +#ifdef CONFIG_STM32_I2C4 /* I2C4 clock enable */ regval |= RCC_APB1ENR2_I2C4EN; #endif -#ifdef CONFIG_STM32L4_SWPMI +#ifdef CONFIG_STM32_SWPMI /* Single-wire protocol master clock enable */ regval |= RCC_APB1ENR2_SWPMI1EN; #endif -#ifdef CONFIG_STM32L4_LPTIM2 +#ifdef CONFIG_STM32_LPTIM2 /* Low power timer 2 clock enable */ regval |= RCC_APB1ENR2_LPTIM2EN; #endif - putreg32(regval, STM32L4_RCC_APB1ENR2); /* Enable peripherals */ + putreg32(regval, STM32_RCC_APB1ENR2); /* Enable peripherals */ } /**************************************************************************** @@ -492,9 +492,9 @@ static inline void rcc_enableapb2(void) * selected APB2 peripherals. */ - regval = getreg32(STM32L4_RCC_APB2ENR); + regval = getreg32(STM32_RCC_APB2ENR); -#if defined(CONFIG_STM32L4_SYSCFG) || defined(CONFIG_STM32L4_COMP) +#if defined(CONFIG_STM32_SYSCFG) || defined(CONFIG_STM32_COMP) /* System configuration controller, comparators, and voltage reference * buffer clock enable */ @@ -502,79 +502,79 @@ static inline void rcc_enableapb2(void) regval |= RCC_APB2ENR_SYSCFGEN; #endif -#ifdef CONFIG_STM32L4_FIREWALL +#ifdef CONFIG_STM32_FIREWALL /* Firewall clock enable */ regval |= RCC_APB2ENR_FWEN; #endif -#ifdef CONFIG_STM32L4_SDMMC +#ifdef CONFIG_STM32_SDMMC /* SDMMC clock enable */ regval |= RCC_APB2ENR_SDMMCEN; #endif -#ifdef CONFIG_STM32L4_TIM1 +#ifdef CONFIG_STM32_TIM1 /* TIM1 clock enable */ regval |= RCC_APB2ENR_TIM1EN; #endif -#ifdef CONFIG_STM32L4_SPI1 +#ifdef CONFIG_STM32_SPI1 /* SPI1 clock enable */ regval |= RCC_APB2ENR_SPI1EN; #endif -#ifdef CONFIG_STM32L4_TIM8 +#ifdef CONFIG_STM32_TIM8 /* TIM8 clock enable */ regval |= RCC_APB2ENR_TIM8EN; #endif -#ifdef CONFIG_STM32L4_USART1 +#ifdef CONFIG_STM32_USART1 /* USART1 clock enable */ regval |= RCC_APB2ENR_USART1EN; #endif -#ifdef CONFIG_STM32L4_TIM15 +#ifdef CONFIG_STM32_TIM15 /* TIM15 clock enable */ regval |= RCC_APB2ENR_TIM15EN; #endif -#ifdef CONFIG_STM32L4_TIM16 +#ifdef CONFIG_STM32_TIM16 /* TIM16 clock enable */ regval |= RCC_APB2ENR_TIM16EN; #endif -#ifdef CONFIG_STM32L4_TIM17 +#ifdef CONFIG_STM32_TIM17 /* TIM17 clock enable */ regval |= RCC_APB2ENR_TIM17EN; #endif -#ifdef CONFIG_STM32L4_SAI1 +#ifdef CONFIG_STM32_SAI1 /* SAI1 clock enable */ regval |= RCC_APB2ENR_SAI1EN; #endif -#ifdef CONFIG_STM32L4_SAI2 +#ifdef CONFIG_STM32_SAI2 /* SAI2 clock enable */ regval |= RCC_APB2ENR_SAI2EN; #endif -#ifdef CONFIG_STM32L4_DFSDM1 +#ifdef CONFIG_STM32_DFSDM1 /* DFSDM clock enable */ regval |= RCC_APB2ENR_DFSDMEN; #endif - putreg32(regval, STM32L4_RCC_APB2ENR); /* Enable peripherals */ + putreg32(regval, STM32_RCC_APB2ENR); /* Enable peripherals */ } /**************************************************************************** @@ -594,72 +594,72 @@ static inline void rcc_enableccip(void) * will at least have a clock. */ - regval = getreg32(STM32L4_RCC_CCIPR); + regval = getreg32(STM32_RCC_CCIPR); -#if defined(STM32L4_I2C_USE_HSI16) -#ifdef CONFIG_STM32L4_I2C1 +#if defined(STM32_I2C_USE_HSI16) +#ifdef CONFIG_STM32_I2C1 /* Select HSI16 as I2C1 clock source. */ regval &= ~RCC_CCIPR_I2C1SEL_MASK; regval |= RCC_CCIPR_I2C1SEL_HSI; #endif -#ifdef CONFIG_STM32L4_I2C2 +#ifdef CONFIG_STM32_I2C2 /* Select HSI16 as I2C2 clock source. */ regval &= ~RCC_CCIPR_I2C2SEL_MASK; regval |= RCC_CCIPR_I2C2SEL_HSI; #endif -#ifdef CONFIG_STM32L4_I2C3 +#ifdef CONFIG_STM32_I2C3 /* Select HSI16 as I2C3 clock source. */ regval &= ~RCC_CCIPR_I2C3SEL_MASK; regval |= RCC_CCIPR_I2C3SEL_HSI; #endif -#endif /* STM32L4_I2C_USE_HSI16 */ +#endif /* STM32_I2C_USE_HSI16 */ -#if defined(STM32L4_USE_CLK48) +#if defined(STM32_USE_CLK48) /* XXX sanity if sdmmc1 or usb or rng, then we need to set the clk48 source - * and then we can also do away with STM32L4_USE_CLK48, and give better + * and then we can also do away with STM32_USE_CLK48, and give better * warning messages. */ regval &= ~RCC_CCIPR_CLK48SEL_MASK; - regval |= STM32L4_CLK48_SEL; + regval |= STM32_CLK48_SEL; #endif -#if defined(CONFIG_STM32L4_ADC1) || defined(CONFIG_STM32L4_ADC2) || defined(CONFIG_STM32L4_ADC3) +#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) || defined(CONFIG_STM32_ADC3) /* Select SYSCLK as ADC clock source */ regval &= ~RCC_CCIPR_ADCSEL_MASK; regval |= RCC_CCIPR_ADCSEL_SYSCLK; #endif -#ifdef CONFIG_STM32L4_DFSDM1 +#ifdef CONFIG_STM32_DFSDM1 /* Select SYSCLK as DFSDM clock source */ regval |= RCC_CCIPR_DFSDMSEL_SYSCLK; #endif - putreg32(regval, STM32L4_RCC_CCIPR); + putreg32(regval, STM32_RCC_CCIPR); /* I2C4 alone has their clock selection in CCIPR2 register. */ -#if defined(STM32L4_I2C_USE_HSI16) -#ifdef CONFIG_STM32L4_I2C4 - regval = getreg32(STM32L4_RCC_CCIPR2); +#if defined(STM32_I2C_USE_HSI16) +#ifdef CONFIG_STM32_I2C4 + regval = getreg32(STM32_RCC_CCIPR2); /* Select HSI16 as I2C4 clock source. */ regval &= ~RCC_CCIPR2_I2C4SEL_MASK; regval |= RCC_CCIPR2_I2C4SEL_HSI; - putreg32(regval, STM32L4_RCC_CCIPR2); + putreg32(regval, STM32_RCC_CCIPR2); #endif #endif } /**************************************************************************** - * Name: stm32l4_stdclockconfig + * Name: stm32_stdclockconfig * * Description: * Called to change to new clock based on settings in board.h @@ -668,8 +668,8 @@ static inline void rcc_enableccip(void) * power clocking modes! ****************************************************************************/ -#ifndef CONFIG_ARCH_BOARD_STM32L4_CUSTOM_CLOCKCONFIG -static void stm32l4_stdclockconfig(void) +#ifndef CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG +static void stm32_stdclockconfig(void) { uint32_t regval; volatile int32_t timeout; @@ -683,29 +683,29 @@ static void stm32l4_stdclockconfig(void) * and freq */ -#ifdef CONFIG_STM32L4_FLASH_PREFETCH +#ifdef CONFIG_STM32_FLASH_PREFETCH regval = (FLASH_ACR_LATENCY_4 | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_PRFTEN); #else regval = (FLASH_ACR_LATENCY_4 | FLASH_ACR_ICEN | FLASH_ACR_DCEN); #endif - putreg32(regval, STM32L4_FLASH_ACR); + putreg32(regval, STM32_FLASH_ACR); /* Wait until the requested number of wait states is set */ - while ((getreg32(STM32L4_FLASH_ACR) & FLASH_ACR_LATENCY_MASK) != + while ((getreg32(STM32_FLASH_ACR) & FLASH_ACR_LATENCY_MASK) != FLASH_ACR_LATENCY_4) { } /* Proceed to clock configuration */ -#if defined(STM32L4_BOARD_USEHSI) || defined(STM32L4_I2C_USE_HSI16) +#if defined(STM32_BOARD_USEHSI) || defined(STM32_I2C_USE_HSI16) /* Enable Internal High-Speed Clock (HSI) */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_HSION; /* Enable HSI */ - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Wait until the HSI is ready (or until a timeout elapsed) */ @@ -713,7 +713,7 @@ static void stm32l4_stdclockconfig(void) { /* Check if the HSIRDY flag is the set in the CR */ - if ((getreg32(STM32L4_RCC_CR) & RCC_CR_HSIRDY) != 0) + if ((getreg32(STM32_RCC_CR) & RCC_CR_HSIRDY) != 0) { /* If so, then break-out with timeout > 0 */ @@ -722,17 +722,17 @@ static void stm32l4_stdclockconfig(void) } #endif -#if defined(STM32L4_BOARD_USEHSI) +#if defined(STM32_BOARD_USEHSI) /* Already set above */ -#elif defined(STM32L4_BOARD_USEMSI) +#elif defined(STM32_BOARD_USEMSI) /* Enable Internal Multi-Speed Clock (MSI) */ /* Wait until the MSI is either off or ready (or until a timeout elapsed) */ for (timeout = MSIRDY_TIMEOUT; timeout > 0; timeout--) { - if ((regval = getreg32(STM32L4_RCC_CR)), (regval & RCC_CR_MSIRDY) || + if ((regval = getreg32(STM32_RCC_CR)), (regval & RCC_CR_MSIRDY) || ~(regval & RCC_CR_MSION)) { /* If so, then break-out with timeout > 0 */ @@ -743,18 +743,18 @@ static void stm32l4_stdclockconfig(void) /* Choose MSI frequency */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval &= ~RCC_CR_MSIRANGE_MASK; - regval |= (STM32L4_BOARD_MSIRANGE | RCC_CR_MSIRGSEL); - putreg32(regval, STM32L4_RCC_CR); + regval |= (STM32_BOARD_MSIRANGE | RCC_CR_MSIRGSEL); + putreg32(regval, STM32_RCC_CR); if (!(regval & RCC_CR_MSION)) { /* Enable MSI */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_MSION; - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Wait until the MSI is ready (or until a timeout elapsed) */ @@ -762,7 +762,7 @@ static void stm32l4_stdclockconfig(void) { /* Check if the MSIRDY flag is the set in the CR */ - if ((getreg32(STM32L4_RCC_CR) & RCC_CR_MSIRDY) != 0) + if ((getreg32(STM32_RCC_CR) & RCC_CR_MSIRDY) != 0) { /* If so, then break-out with timeout > 0 */ @@ -771,12 +771,12 @@ static void stm32l4_stdclockconfig(void) } } -#elif defined(STM32L4_BOARD_USEHSE) +#elif defined(STM32_BOARD_USEHSE) /* Enable External High-Speed Clock (HSE) */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_HSEON; /* Enable HSE */ - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Wait until the HSE is ready (or until a timeout elapsed) */ @@ -784,7 +784,7 @@ static void stm32l4_stdclockconfig(void) { /* Check if the HSERDY flag is the set in the CR */ - if ((getreg32(STM32L4_RCC_CR) & RCC_CR_HSERDY) != 0) + if ((getreg32(STM32_RCC_CR) & RCC_CR_HSERDY) != 0) { /* If so, then break-out with timeout > 0 */ @@ -793,7 +793,7 @@ static void stm32l4_stdclockconfig(void) } #else -# error stm32l4_stdclockconfig(), must have one of STM32L4_BOARD_USEHSI, STM32L4_BOARD_USEMSI, STM32L4_BOARD_USEHSE defined +# error stm32_stdclockconfig(), must have one of STM32_BOARD_USEHSI, STM32_BOARD_USEMSI, STM32_BOARD_USEHSE defined #endif @@ -804,7 +804,7 @@ static void stm32l4_stdclockconfig(void) if (timeout > 0) { - if (STM32L4_SYSCLK_FREQUENCY > 24000000ul) + if (STM32_SYSCLK_FREQUENCY > 24000000ul) { /* Select regulator voltage output Scale 1 mode to support system * frequencies up to 168 MHz. @@ -812,7 +812,7 @@ static void stm32l4_stdclockconfig(void) /* TODO: this seems to hang on STM32L476, at least for MSI@48MHz */ #if 0 - stm32l4_pwr_enableclk(true); + stm32_pwr_enableclk(true); stm32_pwr_setvos(1); #endif } @@ -822,198 +822,198 @@ static void stm32l4_stdclockconfig(void) * frequencies below 24 MHz */ - stm32l4_pwr_enableclk(true); + stm32_pwr_enableclk(true); stm32_pwr_setvos(2); } /* Set the HCLK source/divider */ - regval = getreg32(STM32L4_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_HPRE_MASK; - regval |= STM32L4_RCC_CFGR_HPRE; - putreg32(regval, STM32L4_RCC_CFGR); + regval |= STM32_RCC_CFGR_HPRE; + putreg32(regval, STM32_RCC_CFGR); /* Set the PCLK2 divider */ - regval = getreg32(STM32L4_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_PPRE2_MASK; - regval |= STM32L4_RCC_CFGR_PPRE2; - putreg32(regval, STM32L4_RCC_CFGR); + regval |= STM32_RCC_CFGR_PPRE2; + putreg32(regval, STM32_RCC_CFGR); /* Set the PCLK1 divider */ - regval = getreg32(STM32L4_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_PPRE1_MASK; - regval |= STM32L4_RCC_CFGR_PPRE1; - putreg32(regval, STM32L4_RCC_CFGR); + regval |= STM32_RCC_CFGR_PPRE1; + putreg32(regval, STM32_RCC_CFGR); -#ifndef STM32L4_BOARD_NOPLL +#ifndef STM32_BOARD_NOPLL /* Set the PLL source and main divider */ - regval = getreg32(STM32L4_RCC_PLLCFG); + regval = getreg32(STM32_RCC_PLLCFG); /* Configure Main PLL */ /* Set the PLL dividers and multipliers to configure the main PLL */ - regval = (STM32L4_PLLCFG_PLLM | STM32L4_PLLCFG_PLLN | - STM32L4_PLLCFG_PLLP | STM32L4_PLLCFG_PLLQ | - STM32L4_PLLCFG_PLLR); + regval = (STM32_PLLCFG_PLLM | STM32_PLLCFG_PLLN | + STM32_PLLCFG_PLLP | STM32_PLLCFG_PLLQ | + STM32_PLLCFG_PLLR); -#ifdef STM32L4_PLLCFG_PLLP_ENABLED +#ifdef STM32_PLLCFG_PLLP_ENABLED regval |= RCC_PLLCFG_PLLPEN; #endif -#ifdef STM32L4_PLLCFG_PLLQ_ENABLED +#ifdef STM32_PLLCFG_PLLQ_ENABLED regval |= RCC_PLLCFG_PLLQEN; #endif -#ifdef STM32L4_PLLCFG_PLLR_ENABLED +#ifdef STM32_PLLCFG_PLLR_ENABLED regval |= RCC_PLLCFG_PLLREN; #endif /* XXX The choice of clock source to PLL (all three) is independent - * of the sys clock source choice, review the STM32L4_BOARD_USEHSI + * of the sys clock source choice, review the STM32_BOARD_USEHSI * name; probably split it into two, one for PLL source and one * for sys clock source. */ -#ifdef STM32L4_BOARD_USEHSI +#ifdef STM32_BOARD_USEHSI regval |= RCC_PLLCFG_PLLSRC_HSI; -#elif defined(STM32L4_BOARD_USEMSI) +#elif defined(STM32_BOARD_USEMSI) regval |= RCC_PLLCFG_PLLSRC_MSI; -#else /* if STM32L4_BOARD_USEHSE */ +#else /* if STM32_BOARD_USEHSE */ regval |= RCC_PLLCFG_PLLSRC_HSE; #endif /* Use the main PLL as SYSCLK, so enable it first */ - putreg32(regval, STM32L4_RCC_PLLCFG); + putreg32(regval, STM32_RCC_PLLCFG); /* Enable the main PLL */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_PLLON; - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Wait until the PLL is ready */ - while ((getreg32(STM32L4_RCC_CR) & RCC_CR_PLLRDY) == 0) + while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLRDY) == 0) { } #endif -#ifdef CONFIG_STM32L4_SAI1PLL +#ifdef CONFIG_STM32_SAI1PLL /* Configure SAI1 PLL */ - regval = getreg32(STM32L4_RCC_PLLSAI1CFG); + regval = getreg32(STM32_RCC_PLLSAI1CFG); /* Set the PLL dividers and multipliers to configure the SAI1 PLL */ - regval = (STM32L4_PLLSAI1CFG_PLLN | STM32L4_PLLSAI1CFG_PLLP - | STM32L4_PLLSAI1CFG_PLLQ | STM32L4_PLLSAI1CFG_PLLR); + regval = (STM32_PLLSAI1CFG_PLLN | STM32_PLLSAI1CFG_PLLP + | STM32_PLLSAI1CFG_PLLQ | STM32_PLLSAI1CFG_PLLR); -#ifdef STM32L4_PLLSAI1CFG_PLLP_ENABLED +#ifdef STM32_PLLSAI1CFG_PLLP_ENABLED regval |= RCC_PLLSAI1CFG_PLLPEN; #endif -#ifdef STM32L4_PLLSAI1CFG_PLLQ_ENABLED +#ifdef STM32_PLLSAI1CFG_PLLQ_ENABLED regval |= RCC_PLLSAI1CFG_PLLQEN; #endif -#ifdef STM32L4_PLLSAI1CFG_PLLR_ENABLED +#ifdef STM32_PLLSAI1CFG_PLLR_ENABLED regval |= RCC_PLLSAI1CFG_PLLREN; #endif - putreg32(regval, STM32L4_RCC_PLLSAI1CFG); + putreg32(regval, STM32_RCC_PLLSAI1CFG); /* Enable the SAI1 PLL */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_PLLSAI1ON; - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Wait until the PLL is ready */ - while ((getreg32(STM32L4_RCC_CR) & RCC_CR_PLLSAI1RDY) == 0) + while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLSAI1RDY) == 0) { } #endif -#ifdef CONFIG_STM32L4_SAI2PLL +#ifdef CONFIG_STM32_SAI2PLL /* Configure SAI2 PLL */ - regval = getreg32(STM32L4_RCC_PLLSAI2CFG); + regval = getreg32(STM32_RCC_PLLSAI2CFG); /* Set the PLL dividers and multipliers to configure the SAI2 PLL */ - regval = (STM32L4_PLLSAI2CFG_PLLN | STM32L4_PLLSAI2CFG_PLLP | - STM32L4_PLLSAI2CFG_PLLR); + regval = (STM32_PLLSAI2CFG_PLLN | STM32_PLLSAI2CFG_PLLP | + STM32_PLLSAI2CFG_PLLR); -#ifdef STM32L4_PLLSAI2CFG_PLLP_ENABLED +#ifdef STM32_PLLSAI2CFG_PLLP_ENABLED regval |= RCC_PLLSAI2CFG_PLLPEN; #endif -#ifdef STM32L4_PLLSAI2CFG_PLLR_ENABLED +#ifdef STM32_PLLSAI2CFG_PLLR_ENABLED regval |= RCC_PLLSAI2CFG_PLLREN; #endif - putreg32(regval, STM32L4_RCC_PLLSAI2CFG); + putreg32(regval, STM32_RCC_PLLSAI2CFG); /* Enable the SAI2 PLL */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_PLLSAI2ON; - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Wait until the PLL is ready */ - while ((getreg32(STM32L4_RCC_CR) & RCC_CR_PLLSAI2RDY) == 0) + while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLSAI2RDY) == 0) { } #endif /* Select the system clock source */ - regval = getreg32(STM32L4_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_SW_MASK; -#ifndef STM32L4_BOARD_NOPLL +#ifndef STM32_BOARD_NOPLL regval |= RCC_CFGR_SW_PLL; -#elif STM32L4_BOARD_USEMSI +#elif STM32_BOARD_USEMSI regval |= RCC_CFGR_SW_MSI; -#elif STM32L4_BOARD_USEHSI +#elif STM32_BOARD_USEHSI regval |= RCC_CFGR_SW_HSI; -#elif STM32L4_BOARD_USEHSE +#elif STM32_BOARD_USEHSE regval |= RCC_CFGR_SW_HSE; #endif - putreg32(regval, STM32L4_RCC_CFGR); + putreg32(regval, STM32_RCC_CFGR); /* Wait until the PLL source is used as the system clock source */ - while ((getreg32(STM32L4_RCC_CFGR) & RCC_CFGR_SWS_MASK) != -#ifndef STM32L4_BOARD_NOPLL + while ((getreg32(STM32_RCC_CFGR) & RCC_CFGR_SWS_MASK) != +#ifndef STM32_BOARD_NOPLL RCC_CFGR_SWS_PLL -#elif STM32L4_BOARD_USEMSI +#elif STM32_BOARD_USEMSI RCC_CFGR_SWS_MSI -#elif STM32L4_BOARD_USEHSI +#elif STM32_BOARD_USEHSI RCC_CFGR_SWS_HSI -#elif STM32L4_BOARD_USEHSE +#elif STM32_BOARD_USEHSE RCC_CFGR_SWS_HSE #endif ) { } -#if defined(CONFIG_STM32L4_IWDG) || defined(CONFIG_STM32L4_RTC_LSICLOCK) +#if defined(CONFIG_STM32_IWDG) || defined(CONFIG_STM32_RTC_LSICLOCK) /* Low speed internal clock source LSI */ - stm32l4_rcc_enablelsi(); + stm32_rcc_enablelsi(); #endif -#if defined(STM32L4_BOARD_USEHSI) +#if defined(STM32_BOARD_USEHSI) /* Enable wake-up to HSI from Stop modes */ - regval = getreg32(STM32L4_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval |= RCC_CFGR_STOPWUCK_HSI; - putreg32(regval, STM32L4_RCC_CFGR); + putreg32(regval, STM32_RCC_CFGR); #endif -#if defined(STM32L4_USE_LSE) +#if defined(STM32_USE_LSE) /* Low speed external clock source LSE * * TODO: There is another case where the LSE needs to @@ -1025,7 +1025,7 @@ static void stm32l4_stdclockconfig(void) * to alter the LSE parameters. */ - stm32l4_pwr_enableclk(true); + stm32_pwr_enableclk(true); /* XXX other LSE settings must be made before turning on the oscillator * and we need to ensure it is first off before doing so. @@ -1036,16 +1036,16 @@ static void stm32l4_stdclockconfig(void) * this for automatically trimming MSI, etc. */ - stm32l4_rcc_enablelse(); + stm32_rcc_enablelse(); -# if defined(STM32L4_BOARD_USEMSI) +# if defined(STM32_BOARD_USEMSI) /* Now that LSE is up, auto trim the MSI */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_MSIPLLEN; - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); # endif -#endif /* STM32L4_USE_LSE */ +#endif /* STM32_USE_LSE */ } } #endif @@ -1063,10 +1063,10 @@ static inline void rcc_enableperipherals(void) rcc_enableapb1(); rcc_enableapb2(); -#ifdef STM32L4_USE_HSI48 +#ifdef STM32_USE_HSI48 /* Enable HSI48 clocking to support USB transfers or RNG */ - stm32l4_enable_hsi48(STM32L4_HSI48_SYNCSRC); + stm32_enable_hsi48(STM32_HSI48_SYNCSRC); #endif } diff --git a/arch/arm/src/stm32l4/stm32l4xrxx_dma.c b/arch/arm/src/stm32l4/stm32l4xrxx_dma.c index 38ecf403e11ac..0c7891e318751 100644 --- a/arch/arm/src/stm32l4/stm32l4xrxx_dma.c +++ b/arch/arm/src/stm32l4/stm32l4xrxx_dma.c @@ -45,23 +45,23 @@ * Pre-processor Definitions ****************************************************************************/ -#ifndef CONFIG_STM32L4_DMAMUX -# error "Configuration error, CONFIG_STM32L4_DMAMUX not defined!" +#ifndef CONFIG_STM32_DMAMUX +# error "Configuration error, CONFIG_STM32_DMAMUX not defined!" #endif -#ifndef CONFIG_STM32L4_DMAMUX1 -# error "Configuration error, CONFIG_STM32L4_DMAMUX1 not defined!" +#ifndef CONFIG_STM32_DMAMUX1 +# error "Configuration error, CONFIG_STM32_DMAMUX1 not defined!" #endif #define DMAMUX_NUM 1 #define DMA_CONTROLLERS 2 -#ifdef CONFIG_STM32L4_DMA1 +#ifdef CONFIG_STM32_DMA1 # define DMA1_NCHAN 7 #else # define DMA1_NCHAN 0 #endif -#ifdef CONFIG_STM32L4_DMA2 +#ifdef CONFIG_STM32_DMA2 # define DMA2_NCHAN 7 #else # define DMA2_NCHAN 0 @@ -82,20 +82,20 @@ /* This structure described one DMAMUX device */ -struct stm32l4_dmamux_s +struct stm32_dmamux_s { uint8_t id; /* DMAMUX id */ uint8_t nchan; /* DMAMUX channels */ uint32_t base; /* DMAMUX base address */ }; -typedef const struct stm32l4_dmamux_s *DMA_MUX; +typedef const struct stm32_dmamux_s *DMA_MUX; /* This structure describes one DMA controller */ -struct stm32l4_dma_s +struct stm32_dma_s { - uint8_t first; /* Offset in stm32l4_dmach_s array */ + uint8_t first; /* Offset in stm32_dmach_s array */ uint8_t nchan; /* Number of channels */ uint8_t dmamux_offset; /* DMAMUX channel offset */ uint32_t base; /* Base address */ @@ -104,7 +104,7 @@ struct stm32l4_dma_s /* This structure describes one DMA channel (DMA1, DMA2) */ -struct stm32l4_dmach_s +struct stm32_dmach_s { bool used; /* Channel in use */ uint8_t dmamux_req; /* Configured DMAMUX input request */ @@ -117,11 +117,11 @@ struct stm32l4_dmach_s void *arg; /* Argument passed to callback function */ }; -typedef struct stm32l4_dmach_s *DMA_CHANNEL; +typedef struct stm32_dmach_s *DMA_CHANNEL; /* DMA operations */ -struct stm32l4_dma_ops_s +struct stm32_dma_ops_s { /* Disable the DMA transfer */ @@ -152,12 +152,12 @@ struct stm32l4_dma_ops_s #ifdef CONFIG_DEBUG_DMA_INFO /* Sample the DMA registers */ - void (*dma_sample)(DMA_HANDLE handle, struct stm32l4_dmaregs_s *regs); + void (*dma_sample)(DMA_HANDLE handle, struct stm32_dmaregs_s *regs); /* Dump the DMA registers */ void (*dma_dump)(DMA_HANDLE handle, - const struct stm32l4_dmaregs_s *regs, + const struct stm32_dmaregs_s *regs, const char *msg); #endif }; @@ -166,20 +166,20 @@ struct stm32l4_dma_ops_s * Private Functions ****************************************************************************/ -#if defined(CONFIG_STM32L4_DMA1) || defined(CONFIG_STM32L4_DMA2) -static void stm32l4_dma12_disable(DMA_CHANNEL dmachan); -static int stm32l4_dma12_interrupt(int irq, void *context, void *arg); -static void stm32l4_dma12_setup(DMA_HANDLE handle, uint32_t paddr, +#if defined(CONFIG_STM32_DMA1) || defined(CONFIG_STM32_DMA2) +static void stm32_dma12_disable(DMA_CHANNEL dmachan); +static int stm32_dma12_interrupt(int irq, void *context, void *arg); +static void stm32_dma12_setup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr, size_t ntransfers, uint32_t ccr); -static void stm32l4_dma12_start(DMA_HANDLE handle, dma_callback_t callback, +static void stm32_dma12_start(DMA_HANDLE handle, dma_callback_t callback, void *arg, bool half); -static size_t stm32l4_dma12_residual(DMA_HANDLE handle); +static size_t stm32_dma12_residual(DMA_HANDLE handle); #ifdef CONFIG_DEBUG_DMA_INFO -static void stm32l4_dma12_sample(DMA_HANDLE handle, - struct stm32l4_dmaregs_s *regs); -static void stm32l4_dma12_dump(DMA_HANDLE handle, - const struct stm32l4_dmaregs_s *regs, +static void stm32_dma12_sample(DMA_HANDLE handle, + struct stm32_dmaregs_s *regs); +static void stm32_dma12_dump(DMA_HANDLE handle, + const struct stm32_dmaregs_s *regs, const char *msg); #endif #endif @@ -194,14 +194,14 @@ static void dmachan_putreg(DMA_CHANNEL dmachan, uint32_t offset, static void dmamux_putreg(DMA_MUX dmamux, uint32_t offset, uint32_t value); #ifdef CONFIG_DEBUG_DMA_INFO static uint32_t dmamux_getreg(DMA_MUX dmamux, uint32_t offset); -static void stm32l4_dmamux_sample(DMA_MUX dmamux, uint8_t chan, - struct stm32l4_dmaregs_s *regs); -static void stm32l4_dmamux_dump(DMA_MUX dmamux, uint8_t channel, - const struct stm32l4_dmaregs_s *regs); +static void stm32_dmamux_sample(DMA_MUX dmamux, uint8_t chan, + struct stm32_dmaregs_s *regs); +static void stm32_dmamux_dump(DMA_MUX dmamux, uint8_t channel, + const struct stm32_dmaregs_s *regs); #endif -static DMA_CHANNEL stm32l4_dma_channel_get(uint8_t channel, +static DMA_CHANNEL stm32_dma_channel_get(uint8_t channel, uint8_t controller); -static void stm32l4_gdma_limits_get(uint8_t controller, uint8_t *first, +static void stm32_gdma_limits_get(uint8_t controller, uint8_t *first, uint8_t *last); /**************************************************************************** @@ -210,20 +210,20 @@ static void stm32l4_gdma_limits_get(uint8_t controller, uint8_t *first, /* Operations specific to DMA controller */ -static const struct stm32l4_dma_ops_s g_dma_ops[DMA_CONTROLLERS] = +static const struct stm32_dma_ops_s g_dma_ops[DMA_CONTROLLERS] = { -#ifdef CONFIG_STM32L4_DMA1 +#ifdef CONFIG_STM32_DMA1 /* 0 - DMA1 */ { - .dma_disable = stm32l4_dma12_disable, - .dma_interrupt = stm32l4_dma12_interrupt, - .dma_setup = stm32l4_dma12_setup, - .dma_start = stm32l4_dma12_start, - .dma_residual = stm32l4_dma12_residual, + .dma_disable = stm32_dma12_disable, + .dma_interrupt = stm32_dma12_interrupt, + .dma_setup = stm32_dma12_setup, + .dma_start = stm32_dma12_start, + .dma_residual = stm32_dma12_residual, #ifdef CONFIG_DEBUG_DMA_INFO - .dma_sample = stm32l4_dma12_sample, - .dma_dump = stm32l4_dma12_dump, + .dma_sample = stm32_dma12_sample, + .dma_dump = stm32_dma12_dump, #endif }, #else @@ -232,18 +232,18 @@ static const struct stm32l4_dma_ops_s g_dma_ops[DMA_CONTROLLERS] = }, #endif -#ifdef CONFIG_STM32L4_DMA2 +#ifdef CONFIG_STM32_DMA2 /* 1 - DMA2 */ { - .dma_disable = stm32l4_dma12_disable, - .dma_interrupt = stm32l4_dma12_interrupt, - .dma_setup = stm32l4_dma12_setup, - .dma_start = stm32l4_dma12_start, - .dma_residual = stm32l4_dma12_residual, + .dma_disable = stm32_dma12_disable, + .dma_interrupt = stm32_dma12_interrupt, + .dma_setup = stm32_dma12_setup, + .dma_start = stm32_dma12_start, + .dma_residual = stm32_dma12_residual, #ifdef CONFIG_DEBUG_DMA_INFO - .dma_sample = stm32l4_dma12_sample, - .dma_dump = stm32l4_dma12_dump, + .dma_sample = stm32_dma12_sample, + .dma_dump = stm32_dma12_dump, #endif } #else @@ -255,23 +255,23 @@ static const struct stm32l4_dma_ops_s g_dma_ops[DMA_CONTROLLERS] = /* This array describes the state of DMAMUX controller */ -static const struct stm32l4_dmamux_s g_dmamux[DMAMUX_NUM] = +static const struct stm32_dmamux_s g_dmamux[DMAMUX_NUM] = { { .id = 1, .nchan = 14, /* 0-6 - DMA1, 7-13 - DMA2 */ - .base = STM32L4_DMAMUX1_BASE + .base = STM32_DMAMUX1_BASE } }; /* This array describes the state of each controller */ -static const struct stm32l4_dma_s g_dma[DMA_NCHANNELS] = +static const struct stm32_dma_s g_dma[DMA_NCHANNELS] = { /* 0 - DMA1 */ { - .base = STM32L4_DMA1_BASE, + .base = STM32_DMA1_BASE, .first = DMA1_FIRST, .nchan = DMA1_NCHAN, .dmamux = &g_dmamux[DMAMUX1], /* DMAMUX1 channels 0-6 */ @@ -281,7 +281,7 @@ static const struct stm32l4_dma_s g_dma[DMA_NCHANNELS] = /* 1 - DMA2 */ { - .base = STM32L4_DMA2_BASE, + .base = STM32_DMA2_BASE, .first = DMA2_FIRST, .nchan = DMA2_NCHAN, .dmamux = &g_dmamux[DMAMUX1], /* DMAMUX1 channels 7-13 */ @@ -291,125 +291,125 @@ static const struct stm32l4_dma_s g_dma[DMA_NCHANNELS] = /* This array describes the state of each DMA channel. */ -static struct stm32l4_dmach_s g_dmach[DMA_NCHANNELS] = +static struct stm32_dmach_s g_dmach[DMA_NCHANNELS] = { -#ifdef CONFIG_STM32L4_DMA1 +#ifdef CONFIG_STM32_DMA1 /* DMA1 */ { .ctrl = DMA1, .chan = 0, - .irq = STM32L4_IRQ_DMA1CH1, + .irq = STM32_IRQ_DMA1CH1, .shift = DMA_CHAN_SHIFT(0), - .base = STM32L4_DMA1_BASE + STM32L4_DMACHAN_OFFSET(0), + .base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(0), }, { .ctrl = DMA1, .chan = 1, - .irq = STM32L4_IRQ_DMA1CH2, + .irq = STM32_IRQ_DMA1CH2, .shift = DMA_CHAN_SHIFT(1), - .base = STM32L4_DMA1_BASE + STM32L4_DMACHAN_OFFSET(1), + .base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(1), }, { .ctrl = DMA1, .chan = 2, - .irq = STM32L4_IRQ_DMA1CH3, + .irq = STM32_IRQ_DMA1CH3, .shift = DMA_CHAN_SHIFT(2), - .base = STM32L4_DMA1_BASE + STM32L4_DMACHAN_OFFSET(2), + .base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(2), }, { .ctrl = DMA1, .chan = 3, - .irq = STM32L4_IRQ_DMA1CH4, + .irq = STM32_IRQ_DMA1CH4, .shift = DMA_CHAN_SHIFT(3), - .base = STM32L4_DMA1_BASE + STM32L4_DMACHAN_OFFSET(3), + .base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(3), }, { .ctrl = DMA1, .chan = 4, - .irq = STM32L4_IRQ_DMA1CH5, + .irq = STM32_IRQ_DMA1CH5, .shift = DMA_CHAN_SHIFT(4), - .base = STM32L4_DMA1_BASE + STM32L4_DMACHAN_OFFSET(4), + .base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(4), }, { .ctrl = DMA1, .chan = 5, - .irq = STM32L4_IRQ_DMA1CH6, + .irq = STM32_IRQ_DMA1CH6, .shift = DMA_CHAN_SHIFT(5), - .base = STM32L4_DMA1_BASE + STM32L4_DMACHAN_OFFSET(5), + .base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(5), }, { .ctrl = DMA1, .chan = 6, - .irq = STM32L4_IRQ_DMA1CH7, + .irq = STM32_IRQ_DMA1CH7, .shift = DMA_CHAN_SHIFT(6), - .base = STM32L4_DMA1_BASE + STM32L4_DMACHAN_OFFSET(6), + .base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(6), }, #endif -#ifdef CONFIG_STM32L4_DMA2 +#ifdef CONFIG_STM32_DMA2 /* DMA2 */ { .ctrl = DMA2, .chan = 0, - .irq = STM32L4_IRQ_DMA2CH1, + .irq = STM32_IRQ_DMA2CH1, .shift = DMA_CHAN_SHIFT(0), - .base = STM32L4_DMA2_BASE + STM32L4_DMACHAN_OFFSET(0), + .base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(0), }, { .ctrl = DMA2, .chan = 1, - .irq = STM32L4_IRQ_DMA2CH2, + .irq = STM32_IRQ_DMA2CH2, .shift = DMA_CHAN_SHIFT(1), - .base = STM32L4_DMA2_BASE + STM32L4_DMACHAN_OFFSET(1), + .base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(1), }, { .ctrl = DMA2, .chan = 2, - .irq = STM32L4_IRQ_DMA2CH3, + .irq = STM32_IRQ_DMA2CH3, .shift = DMA_CHAN_SHIFT(2), - .base = STM32L4_DMA2_BASE + STM32L4_DMACHAN_OFFSET(2), + .base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(2), }, { .ctrl = DMA2, .chan = 3, - .irq = STM32L4_IRQ_DMA2CH4, + .irq = STM32_IRQ_DMA2CH4, .shift = DMA_CHAN_SHIFT(3), - .base = STM32L4_DMA2_BASE + STM32L4_DMACHAN_OFFSET(3), + .base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(3), }, { .ctrl = DMA2, .chan = 4, - .irq = STM32L4_IRQ_DMA2CH5, + .irq = STM32_IRQ_DMA2CH5, .shift = DMA_CHAN_SHIFT(4), - .base = STM32L4_DMA2_BASE + STM32L4_DMACHAN_OFFSET(4), + .base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(4), }, { .ctrl = DMA2, .chan = 5, - .irq = STM32L4_IRQ_DMA2CH6, + .irq = STM32_IRQ_DMA2CH6, .shift = DMA_CHAN_SHIFT(5), - .base = STM32L4_DMA2_BASE + STM32L4_DMACHAN_OFFSET(5), + .base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(5), }, { .ctrl = DMA2, .chan = 6, - .irq = STM32L4_IRQ_DMA2CH7, + .irq = STM32_IRQ_DMA2CH7, .shift = DMA_CHAN_SHIFT(6), - .base = STM32L4_DMA2_BASE + STM32L4_DMACHAN_OFFSET(6), + .base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(6), }, #endif }; @@ -524,7 +524,7 @@ static uint32_t dmamux_getreg(DMA_MUX dmamux, uint32_t offset) #endif /**************************************************************************** - * Name: stm32l4_dma_channel_get + * Name: stm32_dma_channel_get * * Description: * Get the g_dmach table entry associated with a given DMA controller @@ -532,7 +532,7 @@ static uint32_t dmamux_getreg(DMA_MUX dmamux, uint32_t offset) * ****************************************************************************/ -static DMA_CHANNEL stm32l4_dma_channel_get(uint8_t channel, +static DMA_CHANNEL stm32_dma_channel_get(uint8_t channel, uint8_t controller) { uint8_t first = 0; @@ -540,7 +540,7 @@ static DMA_CHANNEL stm32l4_dma_channel_get(uint8_t channel, /* Get limits for g_dma array */ - stm32l4_gdma_limits_get(controller, &first, &nchan); + stm32_gdma_limits_get(controller, &first, &nchan); DEBUGASSERT(channel <= nchan); @@ -548,14 +548,14 @@ static DMA_CHANNEL stm32l4_dma_channel_get(uint8_t channel, } /**************************************************************************** - * Name: stm32l4_gdma_limits_get + * Name: stm32_gdma_limits_get * * Description: * Get g_dma array limits for a given DMA controller. * ****************************************************************************/ -static void stm32l4_gdma_limits_get(uint8_t controller, uint8_t *first, +static void stm32_gdma_limits_get(uint8_t controller, uint8_t *first, uint8_t *nchan) { DEBUGASSERT(first != NULL); @@ -571,17 +571,17 @@ static void stm32l4_gdma_limits_get(uint8_t controller, uint8_t *first, * DMA controller functions ****************************************************************************/ -#if defined(CONFIG_STM32L4_DMA1) || defined(CONFIG_STM32L4_DMA2) +#if defined(CONFIG_STM32_DMA1) || defined(CONFIG_STM32_DMA2) /**************************************************************************** - * Name: stm32l4_dma12_disable + * Name: stm32_dma12_disable * * Description: * Disable DMA channel (DMA1/DMA2) * ****************************************************************************/ -static void stm32l4_dma12_disable(DMA_CHANNEL dmachan) +static void stm32_dma12_disable(DMA_CHANNEL dmachan) { uint32_t regval; @@ -589,29 +589,29 @@ static void stm32l4_dma12_disable(DMA_CHANNEL dmachan) /* Disable all interrupts at the DMA controller */ - regval = dmachan_getreg(dmachan, STM32L4_DMACHAN_CCR_OFFSET); + regval = dmachan_getreg(dmachan, STM32_DMACHAN_CCR_OFFSET); regval &= ~DMA_CCR_ALLINTS; /* Disable the DMA channel */ regval &= ~DMA_CCR_EN; - dmachan_putreg(dmachan, STM32L4_DMACHAN_CCR_OFFSET, regval); + dmachan_putreg(dmachan, STM32_DMACHAN_CCR_OFFSET, regval); /* Clear pending channel interrupts */ - dmabase_putreg(dmachan, STM32L4_DMA_IFCR_OFFSET, + dmabase_putreg(dmachan, STM32_DMA_IFCR_OFFSET, DMA_ISR_CHAN_MASK(dmachan->chan)); } /**************************************************************************** - * Name: stm32l4_dma12_interrupt + * Name: stm32_dma12_interrupt * * Description: * DMA channel interrupt handler * ****************************************************************************/ -static int stm32l4_dma12_interrupt(int irq, void *context, void *arg) +static int stm32_dma12_interrupt(int irq, void *context, void *arg) { DMA_CHANNEL dmachan; uint32_t isr; @@ -623,22 +623,22 @@ static int stm32l4_dma12_interrupt(int irq, void *context, void *arg) if (0) { } -#ifdef CONFIG_STM32L4_DMA1 - else if (irq >= STM32L4_IRQ_DMA1CH1 && irq <= STM32L4_IRQ_DMA1CH7) +#ifdef CONFIG_STM32_DMA1 + else if (irq >= STM32_IRQ_DMA1CH1 && irq <= STM32_IRQ_DMA1CH7) { - channel = irq - STM32L4_IRQ_DMA1CH1; + channel = irq - STM32_IRQ_DMA1CH1; controller = DMA1; } #endif -#ifdef CONFIG_STM32L4_DMA2 - else if (irq >= STM32L4_IRQ_DMA2CH1 && irq <= STM32L4_IRQ_DMA2CH5) +#ifdef CONFIG_STM32_DMA2 + else if (irq >= STM32_IRQ_DMA2CH1 && irq <= STM32_IRQ_DMA2CH5) { - channel = irq - STM32L4_IRQ_DMA2CH1; + channel = irq - STM32_IRQ_DMA2CH1; controller = DMA2; } - else if (irq >= STM32L4_IRQ_DMA2CH6 && irq <= STM32L4_IRQ_DMA2CH7) + else if (irq >= STM32_IRQ_DMA2CH6 && irq <= STM32_IRQ_DMA2CH7) { - channel = irq - STM32L4_IRQ_DMA2CH6 + (6 - 1); + channel = irq - STM32_IRQ_DMA2CH6 + (6 - 1); controller = DMA2; } #endif @@ -650,11 +650,11 @@ static int stm32l4_dma12_interrupt(int irq, void *context, void *arg) /* Get the channel structure from the stream and controller numbers */ - dmachan = stm32l4_dma_channel_get(channel, controller); + dmachan = stm32_dma_channel_get(channel, controller); /* Get the interrupt status (for this channel only) */ - isr = dmabase_getreg(dmachan, STM32L4_DMA_ISR_OFFSET) & + isr = dmabase_getreg(dmachan, STM32_DMA_ISR_OFFSET) & DMA_ISR_CHAN_MASK(dmachan->chan); /* Invoke the callback */ @@ -667,20 +667,20 @@ static int stm32l4_dma12_interrupt(int irq, void *context, void *arg) /* Clear the interrupts we are handling */ - dmabase_putreg(dmachan, STM32L4_DMA_IFCR_OFFSET, isr); + dmabase_putreg(dmachan, STM32_DMA_IFCR_OFFSET, isr); return OK; } /**************************************************************************** - * Name: stm32l4_dma12_setup + * Name: stm32_dma12_setup * * Description: * Configure DMA before using * ****************************************************************************/ -static void stm32l4_dma12_setup(DMA_HANDLE handle, uint32_t paddr, +static void stm32_dma12_setup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr, size_t ntransfers, uint32_t ccr) { @@ -696,7 +696,7 @@ static void stm32l4_dma12_setup(DMA_HANDLE handle, uint32_t paddr, " ntransfers: %zd ccr: %08" PRIx32 "\n", paddr, maddr, ntransfers, ccr); -#ifdef CONFIG_STM32L4_DMACAPABLE +#ifdef CONFIG_STM32_DMACAPABLE DEBUGASSERT(g_dma_ops[dmachan->ctrl].dma_capable(maddr, ntransfers, ccr)); #endif @@ -704,28 +704,28 @@ static void stm32l4_dma12_setup(DMA_HANDLE handle, uint32_t paddr, * disabled. */ - regval = dmachan_getreg(dmachan, STM32L4_DMACHAN_CCR_OFFSET); + regval = dmachan_getreg(dmachan, STM32_DMACHAN_CCR_OFFSET); regval &= ~(DMA_CCR_EN); - dmachan_putreg(dmachan, STM32L4_DMACHAN_CCR_OFFSET, regval); + dmachan_putreg(dmachan, STM32_DMACHAN_CCR_OFFSET, regval); /* Set the peripheral register address in the DMA_CPARx register. The data * will be moved from/to this address to/from the memory after the * peripheral event. */ - dmachan_putreg(dmachan, STM32L4_DMACHAN_CPAR_OFFSET, paddr); + dmachan_putreg(dmachan, STM32_DMACHAN_CPAR_OFFSET, paddr); /* Set the memory address in the DMA_CMARx register. The data will be * written to or read from this memory after the peripheral event. */ - dmachan_putreg(dmachan, STM32L4_DMACHAN_CMAR_OFFSET, maddr); + dmachan_putreg(dmachan, STM32_DMACHAN_CMAR_OFFSET, maddr); /* Configure the total number of data to be transferred in the DMA_CNDTRx * register. After each peripheral event, this value will be decremented. */ - dmachan_putreg(dmachan, STM32L4_DMACHAN_CNDTR_OFFSET, ntransfers); + dmachan_putreg(dmachan, STM32_DMACHAN_CNDTR_OFFSET, ntransfers); /* Configure the channel priority using the PL[1:0] bits in the DMA_CCRx * register. Configure data transfer direction, circular mode, peripheral @@ -733,7 +733,7 @@ static void stm32l4_dma12_setup(DMA_HANDLE handle, uint32_t paddr, * after half and/or full transfer in the DMA_CCRx register. */ - regval = dmachan_getreg(dmachan, STM32L4_DMACHAN_CCR_OFFSET); + regval = dmachan_getreg(dmachan, STM32_DMACHAN_CCR_OFFSET); regval &= ~(DMA_CCR_MEM2MEM | DMA_CCR_PL_MASK | DMA_CCR_MSIZE_MASK | DMA_CCR_PSIZE_MASK | DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC | DMA_CCR_DIR); @@ -741,17 +741,17 @@ static void stm32l4_dma12_setup(DMA_HANDLE handle, uint32_t paddr, DMA_CCR_PSIZE_MASK | DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC | DMA_CCR_DIR); regval |= ccr; - dmachan_putreg(dmachan, STM32L4_DMACHAN_CCR_OFFSET, regval); + dmachan_putreg(dmachan, STM32_DMACHAN_CCR_OFFSET, regval); } /**************************************************************************** - * Name: stm32l4_dma12_start + * Name: stm32_dma12_start * * Description: * Start the standard DMA transfer ****************************************************************************/ -static void stm32l4_dma12_start(DMA_HANDLE handle, dma_callback_t callback, +static void stm32_dma12_start(DMA_HANDLE handle, dma_callback_t callback, void *arg, bool half) { DMA_CHANNEL dmachan = (DMA_CHANNEL)handle; @@ -769,7 +769,7 @@ static void stm32l4_dma12_start(DMA_HANDLE handle, dma_callback_t callback, * peripheral connected on the channel. */ - ccr = dmachan_getreg(dmachan, STM32L4_DMACHAN_CCR_OFFSET); + ccr = dmachan_getreg(dmachan, STM32_DMACHAN_CCR_OFFSET); ccr |= DMA_CCR_EN; /* In normal mode, interrupt at either half or full completion. In circular @@ -803,41 +803,41 @@ static void stm32l4_dma12_start(DMA_HANDLE handle, dma_callback_t callback, ccr |= (half ? DMA_CCR_HTIE : 0) | DMA_CCR_TCIE | DMA_CCR_TEIE; } - dmachan_putreg(dmachan, STM32L4_DMACHAN_CCR_OFFSET, ccr); + dmachan_putreg(dmachan, STM32_DMACHAN_CCR_OFFSET, ccr); } /**************************************************************************** - * Name: stm32l4_dma12_residual + * Name: stm32_dma12_residual ****************************************************************************/ -static size_t stm32l4_dma12_residual(DMA_HANDLE handle) +static size_t stm32_dma12_residual(DMA_HANDLE handle) { DMA_CHANNEL dmachan = (DMA_CHANNEL)handle; DEBUGASSERT(dmachan->ctrl == DMA1 || dmachan->ctrl == DMA2); - return dmachan_getreg(dmachan, STM32L4_DMACHAN_CNDTR_OFFSET); + return dmachan_getreg(dmachan, STM32_DMACHAN_CNDTR_OFFSET); } /**************************************************************************** - * Name: stm32l4_dma12_sample + * Name: stm32_dma12_sample ****************************************************************************/ #ifdef CONFIG_DEBUG_DMA_INFO -void stm32l4_dma12_sample(DMA_HANDLE handle, struct stm32l4_dmaregs_s *regs) +void stm32_dma12_sample(DMA_HANDLE handle, struct stm32_dmaregs_s *regs) { DMA_CHANNEL dmachan = (DMA_CHANNEL)handle; irqstate_t flags; flags = enter_critical_section(); - regs->isr = dmabase_getreg(dmachan, STM32L4_DMA_ISR_OFFSET); - regs->ccr = dmachan_getreg(dmachan, STM32L4_DMACHAN_CCR_OFFSET); - regs->cndtr = dmachan_getreg(dmachan, STM32L4_DMACHAN_CNDTR_OFFSET); - regs->cpar = dmachan_getreg(dmachan, STM32L4_DMACHAN_CPAR_OFFSET); - regs->cmar = dmachan_getreg(dmachan, STM32L4_DMACHAN_CMAR_OFFSET); + regs->isr = dmabase_getreg(dmachan, STM32_DMA_ISR_OFFSET); + regs->ccr = dmachan_getreg(dmachan, STM32_DMACHAN_CCR_OFFSET); + regs->cndtr = dmachan_getreg(dmachan, STM32_DMACHAN_CNDTR_OFFSET); + regs->cpar = dmachan_getreg(dmachan, STM32_DMACHAN_CPAR_OFFSET); + regs->cmar = dmachan_getreg(dmachan, STM32_DMACHAN_CMAR_OFFSET); - stm32l4_dmamux_sample(g_dma[dmachan->ctrl].dmamux, + stm32_dmamux_sample(g_dma[dmachan->ctrl].dmamux, dmachan->chan + g_dma[dmachan->ctrl].dmamux_offset, regs); @@ -846,12 +846,12 @@ void stm32l4_dma12_sample(DMA_HANDLE handle, struct stm32l4_dmaregs_s *regs) #endif /**************************************************************************** - * Name: stm32l4_dma12_dump + * Name: stm32_dma12_dump ****************************************************************************/ #ifdef CONFIG_DEBUG_DMA_INFO -static void stm32l4_dma12_dump(DMA_HANDLE handle, - const struct stm32l4_dmaregs_s *regs, +static void stm32_dma12_dump(DMA_HANDLE handle, + const struct stm32_dmaregs_s *regs, const char *msg) { DMA_CHANNEL dmachan = (DMA_CHANNEL)handle; @@ -864,71 +864,71 @@ static void stm32l4_dma12_dump(DMA_HANDLE handle, dmachan->ctrl + 1, msg); dmainfo(" ISR[%08" PRIx32 "]: %08" PRIx32 "\n", - dmabase + STM32L4_DMA_ISR_OFFSET, + dmabase + STM32_DMA_ISR_OFFSET, regs->isr); dmainfo(" CCR[%08" PRIx32 "]: %08" PRIx32 "\n", - dmachan->base + STM32L4_DMACHAN_CCR_OFFSET, + dmachan->base + STM32_DMACHAN_CCR_OFFSET, regs->ccr); dmainfo(" CNDTR[%08" PRIx32 "]: %08" PRIx32 "\n", - dmachan->base + STM32L4_DMACHAN_CNDTR_OFFSET, + dmachan->base + STM32_DMACHAN_CNDTR_OFFSET, regs->cndtr); dmainfo(" CPAR[%08" PRIx32 "]: %08" PRIx32 "\n", - dmachan->base + STM32L4_DMACHAN_CPAR_OFFSET, + dmachan->base + STM32_DMACHAN_CPAR_OFFSET, regs->cpar); dmainfo(" CMAR[%08" PRIx32 "]: %08" PRIx32 "\n", - dmachan->base + STM32L4_DMACHAN_CMAR_OFFSET, + dmachan->base + STM32_DMACHAN_CMAR_OFFSET, regs->cmar); - stm32l4_dmamux_dump(g_dma[dmachan->ctrl].dmamux, + stm32_dmamux_dump(g_dma[dmachan->ctrl].dmamux, dmachan->chan + g_dma[dmachan->ctrl].dmamux_offset, regs); } #endif -#endif /* CONFIG_STM32L4_DMA1 || CONFIG_STM32L4_DMA2 */ +#endif /* CONFIG_STM32_DMA1 || CONFIG_STM32_DMA2 */ /**************************************************************************** - * Name: stm32l4_dmamux_sample + * Name: stm32_dmamux_sample ****************************************************************************/ #ifdef CONFIG_DEBUG_DMA_INFO -static void stm32l4_dmamux_sample(DMA_MUX dmamux, uint8_t chan, - struct stm32l4_dmaregs_s *regs) +static void stm32_dmamux_sample(DMA_MUX dmamux, uint8_t chan, + struct stm32_dmaregs_s *regs) { - regs->dmamux.ccr = dmamux_getreg(dmamux, STM32L4_DMAMUX_CXCR_OFFSET(chan)); - regs->dmamux.csr = dmamux_getreg(dmamux, STM32L4_DMAMUX_CSR_OFFSET); - regs->dmamux.rg0cr = dmamux_getreg(dmamux, STM32L4_DMAMUX_RG0CR_OFFSET); - regs->dmamux.rg1cr = dmamux_getreg(dmamux, STM32L4_DMAMUX_RG1CR_OFFSET); - regs->dmamux.rg2cr = dmamux_getreg(dmamux, STM32L4_DMAMUX_RG2CR_OFFSET); - regs->dmamux.rg3cr = dmamux_getreg(dmamux, STM32L4_DMAMUX_RG3CR_OFFSET); - regs->dmamux.rgsr = dmamux_getreg(dmamux, STM32L4_DMAMUX_RGSR_OFFSET); + regs->dmamux.ccr = dmamux_getreg(dmamux, STM32_DMAMUX_CXCR_OFFSET(chan)); + regs->dmamux.csr = dmamux_getreg(dmamux, STM32_DMAMUX_CSR_OFFSET); + regs->dmamux.rg0cr = dmamux_getreg(dmamux, STM32_DMAMUX_RG0CR_OFFSET); + regs->dmamux.rg1cr = dmamux_getreg(dmamux, STM32_DMAMUX_RG1CR_OFFSET); + regs->dmamux.rg2cr = dmamux_getreg(dmamux, STM32_DMAMUX_RG2CR_OFFSET); + regs->dmamux.rg3cr = dmamux_getreg(dmamux, STM32_DMAMUX_RG3CR_OFFSET); + regs->dmamux.rgsr = dmamux_getreg(dmamux, STM32_DMAMUX_RGSR_OFFSET); } #endif /**************************************************************************** - * Name: stm32l4_dmamux_dump + * Name: stm32_dmamux_dump ****************************************************************************/ #ifdef CONFIG_DEBUG_DMA_INFO -static void stm32l4_dmamux_dump(DMA_MUX dmamux, uint8_t channel, - const struct stm32l4_dmaregs_s *regs) +static void stm32_dmamux_dump(DMA_MUX dmamux, uint8_t channel, + const struct stm32_dmaregs_s *regs) { dmainfo("DMAMUX%d CH=%d\n", dmamux->id, channel); dmainfo(" CCR[%08" PRIx32 "]: %08" PRIx32 "\n", - dmamux->base + STM32L4_DMAMUX_CXCR_OFFSET(channel), + dmamux->base + STM32_DMAMUX_CXCR_OFFSET(channel), regs->dmamux.ccr); dmainfo(" CSR[%08" PRIx32 "]: %08" PRIx32 "\n", - dmamux->base + STM32L4_DMAMUX_CSR_OFFSET, regs->dmamux.csr); + dmamux->base + STM32_DMAMUX_CSR_OFFSET, regs->dmamux.csr); dmainfo(" RG0CR[%08" PRIx32 "]: %08" PRIx32 "\n", - dmamux->base + STM32L4_DMAMUX_RG0CR_OFFSET, regs->dmamux.rg0cr); + dmamux->base + STM32_DMAMUX_RG0CR_OFFSET, regs->dmamux.rg0cr); dmainfo(" RG1CR[%08" PRIx32 "]: %08" PRIx32 "\n", - dmamux->base + STM32L4_DMAMUX_RG1CR_OFFSET, regs->dmamux.rg1cr); + dmamux->base + STM32_DMAMUX_RG1CR_OFFSET, regs->dmamux.rg1cr); dmainfo(" RG2CR[%08" PRIx32 "]: %08" PRIx32 "\n", - dmamux->base + STM32L4_DMAMUX_RG2CR_OFFSET, regs->dmamux.rg2cr); + dmamux->base + STM32_DMAMUX_RG2CR_OFFSET, regs->dmamux.rg2cr); dmainfo(" RG3CR[%08" PRIx32 "]: %08" PRIx32 "\n", - dmamux->base + STM32L4_DMAMUX_RG3CR_OFFSET, regs->dmamux.rg3cr); + dmamux->base + STM32_DMAMUX_RG3CR_OFFSET, regs->dmamux.rg3cr); dmainfo(" RGSR[%08" PRIx32 "]: %08" PRIx32 "\n", - dmamux->base + STM32L4_DMAMUX_RGSR_OFFSET, regs->dmamux.rgsr); + dmamux->base + STM32_DMAMUX_RGSR_OFFSET, regs->dmamux.rgsr); }; #endif @@ -987,7 +987,7 @@ void weak_function arm_dma_initialize(void) } /**************************************************************************** - * Name: stm32l4_dmachannel + * Name: stm32_dmachannel * * Description: * Allocate a DMA channel. This function gives the caller mutually @@ -1011,7 +1011,7 @@ void weak_function arm_dma_initialize(void) * ****************************************************************************/ -DMA_HANDLE stm32l4_dmachannel(unsigned int dmamap) +DMA_HANDLE stm32_dmachannel(unsigned int dmamap) { DMA_CHANNEL dmachan; uint8_t dmamux_req; @@ -1033,7 +1033,7 @@ DMA_HANDLE stm32l4_dmachannel(unsigned int dmamap) /* Get g_dma array limits for given controller */ - stm32l4_gdma_limits_get(controller, &first, &nchan); + stm32_gdma_limits_get(controller, &first, &nchan); /* Find available channel for given controller */ @@ -1077,13 +1077,13 @@ DMA_HANDLE stm32l4_dmachannel(unsigned int dmamap) } /**************************************************************************** - * Name: stm32l4_dmafree + * Name: stm32_dmafree * * Description: * Release a DMA channel and unmap DMAMUX if required. * * NOTE: The 'handle' used in this argument must NEVER be used again - * until stm32l4_dmachannel() is called again to re-gain access to the + * until stm32_dmachannel() is called again to re-gain access to the * channel. * * Returned Value: @@ -1095,7 +1095,7 @@ DMA_HANDLE stm32l4_dmachannel(unsigned int dmamap) * ****************************************************************************/ -void stm32l4_dmafree(DMA_HANDLE handle) +void stm32_dmafree(DMA_HANDLE handle) { DMA_CHANNEL dmachan = (DMA_CHANNEL)handle; uint8_t controller; @@ -1121,14 +1121,14 @@ void stm32l4_dmafree(DMA_HANDLE handle) } /**************************************************************************** - * Name: stm32l4_dmasetup + * Name: stm32_dmasetup * * Description: * Configure DMA before using * ****************************************************************************/ -void stm32l4_dmasetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr, +void stm32_dmasetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr, size_t ntransfers, uint32_t ccr) { DMA_CHANNEL dmachan = (DMA_CHANNEL)handle; @@ -1145,18 +1145,18 @@ void stm32l4_dmasetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr, } /**************************************************************************** - * Name: stm32l4_dmastart + * Name: stm32_dmastart * * Description: * Start the DMA transfer * * Assumptions: - * - DMA handle allocated by stm32l4_dmachannel() + * - DMA handle allocated by stm32_dmachannel() * - No DMA in progress * ****************************************************************************/ -void stm32l4_dmastart(DMA_HANDLE handle, dma_callback_t callback, void *arg, +void stm32_dmastart(DMA_HANDLE handle, dma_callback_t callback, void *arg, bool half) { DMA_CHANNEL dmachan = (DMA_CHANNEL)handle; @@ -1186,7 +1186,7 @@ void stm32l4_dmastart(DMA_HANDLE handle, dma_callback_t callback, void *arg, /* DMAMUX Set DMA channel source */ regval = dmachan->dmamux_req << DMAMUX_CCR_DMAREQID_SHIFT; - dmamux_putreg(dmamux, STM32L4_DMAMUX_CXCR_OFFSET(dmamux_chan), regval); + dmamux_putreg(dmamux, STM32_DMAMUX_CXCR_OFFSET(dmamux_chan), regval); /* Enable DMA channel */ @@ -1194,19 +1194,19 @@ void stm32l4_dmastart(DMA_HANDLE handle, dma_callback_t callback, void *arg, } /**************************************************************************** - * Name: stm32l4_dmastop + * Name: stm32_dmastop * * Description: - * Cancel the DMA. After stm32l4_dmastop() is called, the DMA channel is - * reset and stm32l4_dmasetup() must be called before stm32l4_dmastart() + * Cancel the DMA. After stm32_dmastop() is called, the DMA channel is + * reset and stm32_dmasetup() must be called before stm32_dmastart() * can be called again * * Assumptions: - * - DMA handle allocated by stm32l4_dmachannel() + * - DMA handle allocated by stm32_dmachannel() * ****************************************************************************/ -void stm32l4_dmastop(DMA_HANDLE handle) +void stm32_dmastop(DMA_HANDLE handle) { DMA_CHANNEL dmachan = (DMA_CHANNEL)handle; DMA_MUX dmamux; @@ -1231,21 +1231,21 @@ void stm32l4_dmastop(DMA_HANDLE handle) /* DMAMUX Clear DMA channel source */ - dmamux_putreg(dmamux, STM32L4_DMAMUX_CXCR_OFFSET(dmamux_chan), 0); + dmamux_putreg(dmamux, STM32_DMAMUX_CXCR_OFFSET(dmamux_chan), 0); } /**************************************************************************** - * Name: stm32l4_dmaresidual + * Name: stm32_dmaresidual * * Description: * Read the DMA bytes-remaining register. * * Assumptions: - * - DMA handle allocated by stm32l4_dmachannel() + * - DMA handle allocated by stm32_dmachannel() * ****************************************************************************/ -size_t stm32l4_dmaresidual(DMA_HANDLE handle) +size_t stm32_dmaresidual(DMA_HANDLE handle) { DMA_CHANNEL dmachan = (DMA_CHANNEL)handle; uint8_t controller; @@ -1261,7 +1261,7 @@ size_t stm32l4_dmaresidual(DMA_HANDLE handle) } /**************************************************************************** - * Name: stm32l4_dmacapable + * Name: stm32_dmacapable * * Description: * Check if the DMA controller can transfer data to/from given memory @@ -1277,8 +1277,8 @@ size_t stm32l4_dmaresidual(DMA_HANDLE handle) * ****************************************************************************/ -#ifdef CONFIG_STM32L4_DMACAPABLE -bool stm32l4_dmacapable(uint32_t maddr, uint32_t count, uint32_t ccr) +#ifdef CONFIG_STM32_DMACAPABLE +bool stm32_dmacapable(uint32_t maddr, uint32_t count, uint32_t ccr) { unsigned int msize_shift; uint32_t transfer_size; @@ -1322,23 +1322,23 @@ bool stm32l4_dmacapable(uint32_t maddr, uint32_t count, uint32_t ccr) mend = maddr + (count << msize_shift) - 1; - if ((maddr & STM32L4_REGION_MASK) != (mend & STM32L4_REGION_MASK)) + if ((maddr & STM32_REGION_MASK) != (mend & STM32_REGION_MASK)) { return false; } - switch (maddr & STM32L4_REGION_MASK) + switch (maddr & STM32_REGION_MASK) { - case STM32L4_PERIPH_BASE: - case STM32L4_FSMC_BASE: - case STM32L4_FSMC_BANK1: - case STM32L4_FSMC_BANK2: - case STM32L4_FSMC_BANK3: - case STM32L4_QSPI_BANK: - case STM32L4_SRAM_BASE: - case STM32L4_SRAM2_BASE: - case STM32L4_SRAM3_BASE: - case STM32L4_CODE_BASE: + case STM32_PERIPH_BASE: + case STM32_FSMC_BASE: + case STM32_FSMC_BANK1: + case STM32_FSMC_BANK2: + case STM32_FSMC_BANK3: + case STM32_QSPI_BANK: + case STM32_SRAM_BASE: + case STM32_SRAM2_BASE: + case STM32_SRAM3_BASE: + case STM32_CODE_BASE: /* All RAM and flash is supported */ @@ -1354,18 +1354,18 @@ bool stm32l4_dmacapable(uint32_t maddr, uint32_t count, uint32_t ccr) #endif /**************************************************************************** - * Name: stm32l4_dmasample + * Name: stm32_dmasample * * Description: * Sample DMA register contents * * Assumptions: - * - DMA handle allocated by stm32l4_dmachannel() + * - DMA handle allocated by stm32_dmachannel() * ****************************************************************************/ #ifdef CONFIG_DEBUG_DMA_INFO -void stm32l4_dmasample(DMA_HANDLE handle, struct stm32l4_dmaregs_s *regs) +void stm32_dmasample(DMA_HANDLE handle, struct stm32_dmaregs_s *regs) { DMA_CHANNEL dmachan = (DMA_CHANNEL)handle; uint8_t controller; @@ -1382,18 +1382,18 @@ void stm32l4_dmasample(DMA_HANDLE handle, struct stm32l4_dmaregs_s *regs) #endif /**************************************************************************** - * Name: stm32l4_dmadump + * Name: stm32_dmadump * * Description: * Dump previously sampled DMA register contents * * Assumptions: - * - DMA handle allocated by stm32l4_dmachannel() + * - DMA handle allocated by stm32_dmachannel() * ****************************************************************************/ #ifdef CONFIG_DEBUG_DMA_INFO -void stm32l4_dmadump(DMA_HANDLE handle, const struct stm32l4_dmaregs_s *regs, +void stm32_dmadump(DMA_HANDLE handle, const struct stm32_dmaregs_s *regs, const char *msg) { DMA_CHANNEL dmachan = (DMA_CHANNEL)handle; diff --git a/arch/arm/src/stm32l4/stm32l4xrxx_rcc.c b/arch/arm/src/stm32l4/stm32l4xrxx_rcc.c index 0add98c900356..e3a42befec099 100644 --- a/arch/arm/src/stm32l4/stm32l4xrxx_rcc.c +++ b/arch/arm/src/stm32l4/stm32l4xrxx_rcc.c @@ -55,9 +55,9 @@ static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1, /* Determine if board wants to use HSI48 as 48 MHz oscillator. */ -#if defined(CONFIG_STM32L4_HAVE_HSI48) && defined(STM32L4_USE_CLK48) -# if STM32L4_CLK48_SEL == RCC_CCIPR_CLK48SEL_HSI48 -# define STM32L4_USE_HSI48 +#if defined(CONFIG_STM32_HAVE_HSI48) && defined(STM32_USE_CLK48) +# if STM32_CLK48_SEL == RCC_CCIPR_CLK48SEL_HSI48 +# define STM32_USE_HSI48 # endif #endif @@ -83,33 +83,33 @@ static inline void rcc_reset(void) /* Enable the Internal High Speed clock (HSI) */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_HSION; - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Reset CFGR register */ - putreg32(0x00000000, STM32L4_RCC_CFGR); + putreg32(0x00000000, STM32_RCC_CFGR); /* Reset HSION, HSEON, CSSON and PLLON bits */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval &= ~(RCC_CR_HSION | RCC_CR_HSEON | RCC_CR_CSSON | RCC_CR_PLLON); - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Reset PLLCFGR register to reset default */ - putreg32(RCC_PLLCFG_RESET, STM32L4_RCC_PLLCFG); + putreg32(RCC_PLLCFG_RESET, STM32_RCC_PLLCFG); /* Reset HSEBYP bit */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval &= ~RCC_CR_HSEBYP; - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Disable all interrupts */ - putreg32(0x00000000, STM32L4_RCC_CIER); + putreg32(0x00000000, STM32_RCC_CIER); } /**************************************************************************** @@ -128,45 +128,45 @@ static inline void rcc_enableahb1(void) * selected AHB1 peripherals. */ - regval = getreg32(STM32L4_RCC_AHB1ENR); + regval = getreg32(STM32_RCC_AHB1ENR); -#ifdef CONFIG_STM32L4_DMAMUX1 +#ifdef CONFIG_STM32_DMAMUX1 /* DMAMUX 1 clock enable */ regval |= RCC_AHB1ENR_DMAMUX1EN; #endif -#ifdef CONFIG_STM32L4_DMA1 +#ifdef CONFIG_STM32_DMA1 /* DMA 1 clock enable */ regval |= RCC_AHB1ENR_DMA1EN; #endif -#ifdef CONFIG_STM32L4_DMA2 +#ifdef CONFIG_STM32_DMA2 /* DMA 2 clock enable */ regval |= RCC_AHB1ENR_DMA2EN; #endif -#ifdef CONFIG_STM32L4_CRC +#ifdef CONFIG_STM32_CRC /* CRC clock enable */ regval |= RCC_AHB1ENR_CRCEN; #endif -#ifdef CONFIG_STM32L4_TSC +#ifdef CONFIG_STM32_TSC /* TSC clock enable */ regval |= RCC_AHB1ENR_TSCEN; #endif -#ifdef CONFIG_STM32L4_DMA2D +#ifdef CONFIG_STM32_DMA2D /* DMA2D clock enable */ regval |= RCC_AHB1ENR_DMA2DEN; #endif - putreg32(regval, STM32L4_RCC_AHB1ENR); /* Enable peripherals */ + putreg32(regval, STM32_RCC_AHB1ENR); /* Enable peripherals */ } /**************************************************************************** @@ -185,82 +185,82 @@ static inline void rcc_enableahb2(void) * selected AHB2 peripherals. */ - regval = getreg32(STM32L4_RCC_AHB2ENR); + regval = getreg32(STM32_RCC_AHB2ENR); /* Enable GPIOA, GPIOB, .... GPIOI */ -#if STM32L4_NPORTS > 0 +#if STM32_NPORTS > 0 regval |= (RCC_AHB2ENR_GPIOAEN -#if STM32L4_NPORTS > 1 +#if STM32_NPORTS > 1 | RCC_AHB2ENR_GPIOBEN #endif -#if STM32L4_NPORTS > 2 +#if STM32_NPORTS > 2 | RCC_AHB2ENR_GPIOCEN #endif -#if STM32L4_NPORTS > 3 +#if STM32_NPORTS > 3 | RCC_AHB2ENR_GPIODEN #endif -#if STM32L4_NPORTS > 4 +#if STM32_NPORTS > 4 | RCC_AHB2ENR_GPIOEEN #endif -#if STM32L4_NPORTS > 5 +#if STM32_NPORTS > 5 | RCC_AHB2ENR_GPIOFEN #endif -#if STM32L4_NPORTS > 6 +#if STM32_NPORTS > 6 | RCC_AHB2ENR_GPIOGEN #endif -#if STM32L4_NPORTS > 7 +#if STM32_NPORTS > 7 | RCC_AHB2ENR_GPIOHEN #endif -#if STM32L4_NPORTS > 8 +#if STM32_NPORTS > 8 | RCC_AHB2ENR_GPIOIEN #endif ); #endif -#ifdef CONFIG_STM32L4_OTGFS +#ifdef CONFIG_STM32_OTGFS /* USB OTG FS clock enable */ regval |= RCC_AHB2ENR_OTGFSEN; #endif -#if defined(CONFIG_STM32L4_ADC1) +#if defined(CONFIG_STM32_ADC1) /* ADC clock enable */ regval |= RCC_AHB2ENR_ADCEN; #endif -#ifdef CONFIG_STM32L4_DCMI +#ifdef CONFIG_STM32_DCMI /* Digital Camera interfaces clock enable */ regval |= RCC_AHB2ENR_DCMIEN; #endif -#ifdef CONFIG_STM32L4_AES +#ifdef CONFIG_STM32_AES /* Cryptographic modules clock enable */ regval |= RCC_AHB2ENR_AESEN; #endif -#ifdef CONFIG_STM32L4_HASH +#ifdef CONFIG_STM32_HASH /* HASH module clock enable */ regval |= RCC_AHB2ENR_HASHEN; #endif -#ifdef CONFIG_STM32L4_RNG +#ifdef CONFIG_STM32_RNG /* Random number generator clock enable */ regval |= RCC_AHB2ENR_RNGEN; #endif -#ifdef CONFIG_STM32L4_SDMMC +#ifdef CONFIG_STM32_SDMMC /* SDMMC clock enable */ regval |= RCC_AHB2ENR_SDMMC1EN; #endif - putreg32(regval, STM32L4_RCC_AHB2ENR); /* Enable peripherals */ + putreg32(regval, STM32_RCC_AHB2ENR); /* Enable peripherals */ } /**************************************************************************** @@ -279,15 +279,15 @@ static inline void rcc_enableahb3(void) * selected AHB3 peripherals. */ - regval = getreg32(STM32L4_RCC_AHB3ENR); + regval = getreg32(STM32_RCC_AHB3ENR); -#ifdef CONFIG_STM32L4_FSMC +#ifdef CONFIG_STM32_FSMC /* Flexible static memory controller module clock enable */ regval |= RCC_AHB3ENR_FSMCEN; #endif - putreg32(regval, STM32L4_RCC_AHB3ENR); /* Enable peripherals */ + putreg32(regval, STM32_RCC_AHB3ENR); /* Enable peripherals */ } /**************************************************************************** @@ -306,106 +306,106 @@ static inline void rcc_enableapb1(void) * selected APB1 peripherals. */ - regval = getreg32(STM32L4_RCC_APB1ENR1); + regval = getreg32(STM32_RCC_APB1ENR1); -#ifdef CONFIG_STM32L4_TIM2 +#ifdef CONFIG_STM32_TIM2 /* TIM2 clock enable */ regval |= RCC_APB1ENR1_TIM2EN; #endif -#ifdef CONFIG_STM32L4_TIM3 +#ifdef CONFIG_STM32_TIM3 /* TIM3 clock enable */ regval |= RCC_APB1ENR1_TIM3EN; #endif -#ifdef CONFIG_STM32L4_TIM4 +#ifdef CONFIG_STM32_TIM4 /* TIM4 clock enable */ regval |= RCC_APB1ENR1_TIM4EN; #endif -#ifdef CONFIG_STM32L4_TIM5 +#ifdef CONFIG_STM32_TIM5 /* TIM5 clock enable */ regval |= RCC_APB1ENR1_TIM5EN; #endif -#ifdef CONFIG_STM32L4_TIM6 +#ifdef CONFIG_STM32_TIM6 /* TIM6 clock enable */ regval |= RCC_APB1ENR1_TIM6EN; #endif -#ifdef CONFIG_STM32L4_TIM7 +#ifdef CONFIG_STM32_TIM7 /* TIM7 clock enable */ regval |= RCC_APB1ENR1_TIM7EN; #endif -#ifdef CONFIG_STM32L4_SPI2 +#ifdef CONFIG_STM32_SPI2 /* SPI2 clock enable */ regval |= RCC_APB1ENR1_SPI2EN; #endif -#ifdef CONFIG_STM32L4_SPI3 +#ifdef CONFIG_STM32_SPI3 /* SPI3 clock enable */ regval |= RCC_APB1ENR1_SPI3EN; #endif -#ifdef CONFIG_STM32L4_USART2 +#ifdef CONFIG_STM32_USART2 /* USART 2 clock enable */ regval |= RCC_APB1ENR1_USART2EN; #endif -#ifdef CONFIG_STM32L4_USART3 +#ifdef CONFIG_STM32_USART3 /* USART3 clock enable */ regval |= RCC_APB1ENR1_USART3EN; #endif -#ifdef CONFIG_STM32L4_UART4 +#ifdef CONFIG_STM32_UART4 /* UART4 clock enable */ regval |= RCC_APB1ENR1_UART4EN; #endif -#ifdef CONFIG_STM32L4_UART5 +#ifdef CONFIG_STM32_UART5 /* UART5 clock enable */ regval |= RCC_APB1ENR1_UART5EN; #endif -#ifdef CONFIG_STM32L4_I2C1 +#ifdef CONFIG_STM32_I2C1 /* I2C1 clock enable */ regval |= RCC_APB1ENR1_I2C1EN; #endif -#ifdef CONFIG_STM32L4_I2C2 +#ifdef CONFIG_STM32_I2C2 /* I2C2 clock enable */ regval |= RCC_APB1ENR1_I2C2EN; #endif -#ifdef CONFIG_STM32L4_I2C3 +#ifdef CONFIG_STM32_I2C3 /* I2C3 clock enable */ regval |= RCC_APB1ENR1_I2C3EN; #endif -#ifdef CONFIG_STM32L4_CAN1 +#ifdef CONFIG_STM32_CAN1 /* CAN 1 clock enable */ regval |= RCC_APB1ENR1_CAN1EN; #endif -#ifdef STM32L4_USE_HSI48 - if (STM32L4_HSI48_SYNCSRC != SYNCSRC_NONE) +#ifdef STM32_USE_HSI48 + if (STM32_HSI48_SYNCSRC != SYNCSRC_NONE) { /* Clock Recovery System clock enable */ @@ -419,49 +419,49 @@ static inline void rcc_enableapb1(void) regval |= RCC_APB1ENR1_PWREN; -#if defined (CONFIG_STM32L4_DAC1) || defined(CONFIG_STM32L4_DAC2) +#if defined (CONFIG_STM32_DAC1) || defined(CONFIG_STM32_DAC2) /* DAC interface clock enable */ regval |= RCC_APB1ENR1_DAC1EN; #endif -#ifdef CONFIG_STM32L4_OPAMP +#ifdef CONFIG_STM32_OPAMP /* OPAMP clock enable */ regval |= RCC_APB1ENR1_OPAMPEN; #endif -#ifdef CONFIG_STM32L4_LPTIM1 +#ifdef CONFIG_STM32_LPTIM1 /* Low power timer 1 clock enable */ regval |= RCC_APB1ENR1_LPTIM1EN; #endif - putreg32(regval, STM32L4_RCC_APB1ENR1); /* Enable peripherals */ + putreg32(regval, STM32_RCC_APB1ENR1); /* Enable peripherals */ /* Second APB1 register */ - regval = getreg32(STM32L4_RCC_APB1ENR2); + regval = getreg32(STM32_RCC_APB1ENR2); -#ifdef CONFIG_STM32L4_LPUART1 +#ifdef CONFIG_STM32_LPUART1 /* Low power uart clock enable */ regval |= RCC_APB1ENR2_LPUART1EN; #endif -#ifdef CONFIG_STM32L4_I2C4 +#ifdef CONFIG_STM32_I2C4 /* I2C4 clock enable */ regval |= RCC_APB1ENR2_I2C4EN; #endif -#ifdef CONFIG_STM32L4_LPTIM2 +#ifdef CONFIG_STM32_LPTIM2 /* Low power timer 2 clock enable */ regval |= RCC_APB1ENR2_LPTIM2EN; #endif - putreg32(regval, STM32L4_RCC_APB1ENR2); /* Enable peripherals */ + putreg32(regval, STM32_RCC_APB1ENR2); /* Enable peripherals */ } /**************************************************************************** @@ -480,9 +480,9 @@ static inline void rcc_enableapb2(void) * selected APB2 peripherals. */ - regval = getreg32(STM32L4_RCC_APB2ENR); + regval = getreg32(STM32_RCC_APB2ENR); -#if defined(CONFIG_STM32L4_SYSCFG) || defined(CONFIG_STM32L4_COMP) +#if defined(CONFIG_STM32_SYSCFG) || defined(CONFIG_STM32_COMP) /* System configuration controller, comparators, and voltage reference * buffer clock enable */ @@ -490,73 +490,73 @@ static inline void rcc_enableapb2(void) regval |= RCC_APB2ENR_SYSCFGEN; #endif -#ifdef CONFIG_STM32L4_FIREWALL +#ifdef CONFIG_STM32_FIREWALL /* Firewall clock enable */ regval |= RCC_APB2ENR_FWEN; #endif -#ifdef CONFIG_STM32L4_TIM1 +#ifdef CONFIG_STM32_TIM1 /* TIM1 clock enable */ regval |= RCC_APB2ENR_TIM1EN; #endif -#ifdef CONFIG_STM32L4_SPI1 +#ifdef CONFIG_STM32_SPI1 /* SPI1 clock enable */ regval |= RCC_APB2ENR_SPI1EN; #endif -#ifdef CONFIG_STM32L4_TIM8 +#ifdef CONFIG_STM32_TIM8 /* TIM8 clock enable */ regval |= RCC_APB2ENR_TIM8EN; #endif -#ifdef CONFIG_STM32L4_USART1 +#ifdef CONFIG_STM32_USART1 /* USART1 clock enable */ regval |= RCC_APB2ENR_USART1EN; #endif -#ifdef CONFIG_STM32L4_TIM15 +#ifdef CONFIG_STM32_TIM15 /* TIM15 clock enable */ regval |= RCC_APB2ENR_TIM15EN; #endif -#ifdef CONFIG_STM32L4_TIM16 +#ifdef CONFIG_STM32_TIM16 /* TIM16 clock enable */ regval |= RCC_APB2ENR_TIM16EN; #endif -#ifdef CONFIG_STM32L4_TIM17 +#ifdef CONFIG_STM32_TIM17 /* TIM17 clock enable */ regval |= RCC_APB2ENR_TIM17EN; #endif -#ifdef CONFIG_STM32L4_SAI1 +#ifdef CONFIG_STM32_SAI1 /* SAI1 clock enable */ regval |= RCC_APB2ENR_SAI1EN; #endif -#ifdef CONFIG_STM32L4_SAI2 +#ifdef CONFIG_STM32_SAI2 /* SAI2 clock enable */ regval |= RCC_APB2ENR_SAI2EN; #endif -#ifdef CONFIG_STM32L4_DFSDM1 +#ifdef CONFIG_STM32_DFSDM1 /* DFSDM clock enable */ regval |= RCC_APB2ENR_DFSDMEN; #endif - putreg32(regval, STM32L4_RCC_APB2ENR); /* Enable peripherals */ + putreg32(regval, STM32_RCC_APB2ENR); /* Enable peripherals */ } /**************************************************************************** @@ -576,54 +576,54 @@ static inline void rcc_enableccip(void) * will at least have a clock. */ - regval = getreg32(STM32L4_RCC_CCIPR); + regval = getreg32(STM32_RCC_CCIPR); -#if defined(STM32L4_I2C_USE_HSI16) -#ifdef CONFIG_STM32L4_I2C1 +#if defined(STM32_I2C_USE_HSI16) +#ifdef CONFIG_STM32_I2C1 /* Select HSI16 as I2C1 clock source. */ regval &= ~RCC_CCIPR_I2C1SEL_MASK; regval |= RCC_CCIPR_I2C1SEL_HSI; #endif -#ifdef CONFIG_STM32L4_I2C2 +#ifdef CONFIG_STM32_I2C2 /* Select HSI16 as I2C2 clock source. */ regval &= ~RCC_CCIPR_I2C2SEL_MASK; regval |= RCC_CCIPR_I2C2SEL_HSI; #endif -#ifdef CONFIG_STM32L4_I2C3 +#ifdef CONFIG_STM32_I2C3 /* Select HSI16 as I2C3 clock source. */ regval &= ~RCC_CCIPR_I2C3SEL_MASK; regval |= RCC_CCIPR_I2C3SEL_HSI; #endif -#endif /* STM32L4_I2C_USE_HSI16 */ +#endif /* STM32_I2C_USE_HSI16 */ -#if defined(STM32L4_USE_CLK48) +#if defined(STM32_USE_CLK48) /* XXX sanity if sdmmc1 or usb or rng, then we need to set the clk48 source - * and then we can also do away with STM32L4_USE_CLK48, and give better + * and then we can also do away with STM32_USE_CLK48, and give better * warning messages. */ regval &= ~RCC_CCIPR_CLK48SEL_MASK; - regval |= STM32L4_CLK48_SEL; + regval |= STM32_CLK48_SEL; #endif -#if defined(CONFIG_STM32L4_ADC1) +#if defined(CONFIG_STM32_ADC1) /* Select SYSCLK as ADC clock source */ regval &= ~RCC_CCIPR_ADCSEL_MASK; regval |= RCC_CCIPR_ADCSEL_SYSCLK; #endif - putreg32(regval, STM32L4_RCC_CCIPR); + putreg32(regval, STM32_RCC_CCIPR); /* Some peripherals have their clock selection in CCIPR2 register. */ - regval = getreg32(STM32L4_RCC_CCIPR2); + regval = getreg32(STM32_RCC_CCIPR2); -#if defined(STM32L4_I2C_USE_HSI16) -#ifdef CONFIG_STM32L4_I2C4 +#if defined(STM32_I2C_USE_HSI16) +#ifdef CONFIG_STM32_I2C4 /* Select HSI16 as I2C4 clock source. */ regval &= ~RCC_CCIPR2_I2C4SEL_MASK; @@ -631,7 +631,7 @@ static inline void rcc_enableccip(void) #endif #endif -#ifdef CONFIG_STM32L4_DFSDM1 +#ifdef CONFIG_STM32_DFSDM1 /* Select SAI1 as DFSDM audio clock source. */ regval &= ~RCC_CCIPR2_ADFSDMSEL_MASK; @@ -642,11 +642,11 @@ static inline void rcc_enableccip(void) regval |= RCC_CCIPR2_DFSDMSEL_PCLK; #endif - putreg32(regval, STM32L4_RCC_CCIPR2); + putreg32(regval, STM32_RCC_CCIPR2); } /**************************************************************************** - * Name: stm32l4_stdclockconfig + * Name: stm32_stdclockconfig * * Description: * Called to change to new clock based on settings in board.h @@ -655,18 +655,18 @@ static inline void rcc_enableccip(void) * power clocking modes! ****************************************************************************/ -#ifndef CONFIG_ARCH_BOARD_STM32L4_CUSTOM_CLOCKCONFIG -static void stm32l4_stdclockconfig(void) +#ifndef CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG +static void stm32_stdclockconfig(void) { uint32_t regval; volatile int32_t timeout; -#if defined(STM32L4_BOARD_USEHSI) || defined(STM32L4_I2C_USE_HSI16) +#if defined(STM32_BOARD_USEHSI) || defined(STM32_I2C_USE_HSI16) /* Enable Internal High-Speed Clock (HSI) */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_HSION; /* Enable HSI */ - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Wait until the HSI is ready (or until a timeout elapsed) */ @@ -674,7 +674,7 @@ static void stm32l4_stdclockconfig(void) { /* Check if the HSIRDY flag is the set in the CR */ - if ((getreg32(STM32L4_RCC_CR) & RCC_CR_HSIRDY) != 0) + if ((getreg32(STM32_RCC_CR) & RCC_CR_HSIRDY) != 0) { /* If so, then break-out with timeout > 0 */ @@ -683,17 +683,17 @@ static void stm32l4_stdclockconfig(void) } #endif -#if defined(STM32L4_BOARD_USEHSI) +#if defined(STM32_BOARD_USEHSI) /* Already set above */ -#elif defined(STM32L4_BOARD_USEMSI) +#elif defined(STM32_BOARD_USEMSI) /* Enable Internal Multi-Speed Clock (MSI) */ /* Wait until the MSI is either off or ready (or until a timeout elapsed) */ for (timeout = MSIRDY_TIMEOUT; timeout > 0; timeout--) { - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); if ((regval & RCC_CR_MSIRDY) || ~(regval & RCC_CR_MSION)) { @@ -705,10 +705,10 @@ static void stm32l4_stdclockconfig(void) /* setting MSIRANGE */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval &= ~RCC_CR_MSIRANGE_MASK; - regval |= (STM32L4_BOARD_MSIRANGE | RCC_CR_MSION); /* Enable MSI and frequency */ - putreg32(regval, STM32L4_RCC_CR); + regval |= (STM32_BOARD_MSIRANGE | RCC_CR_MSION); /* Enable MSI and frequency */ + putreg32(regval, STM32_RCC_CR); /* Wait until the MSI is ready (or until a timeout elapsed) */ @@ -716,7 +716,7 @@ static void stm32l4_stdclockconfig(void) { /* Check if the MSIRDY flag is the set in the CR */ - if ((getreg32(STM32L4_RCC_CR) & RCC_CR_MSIRDY) != 0) + if ((getreg32(STM32_RCC_CR) & RCC_CR_MSIRDY) != 0) { /* If so, then break-out with timeout > 0 */ @@ -724,12 +724,12 @@ static void stm32l4_stdclockconfig(void) } } -#elif defined(STM32L4_BOARD_USEHSE) +#elif defined(STM32_BOARD_USEHSE) /* Enable External High-Speed Clock (HSE) */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_HSEON; /* Enable HSE */ - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Wait until the HSE is ready (or until a timeout elapsed) */ @@ -737,7 +737,7 @@ static void stm32l4_stdclockconfig(void) { /* Check if the HSERDY flag is the set in the CR */ - if ((getreg32(STM32L4_RCC_CR) & RCC_CR_HSERDY) != 0) + if ((getreg32(STM32_RCC_CR) & RCC_CR_HSERDY) != 0) { /* If so, then break-out with timeout > 0 */ @@ -746,7 +746,7 @@ static void stm32l4_stdclockconfig(void) } #else -# error stm32l4_stdclockconfig(), must have one of STM32L4_BOARD_USEHSI, STM32L4_BOARD_USEMSI, STM32L4_BOARD_USEHSE defined +# error stm32_stdclockconfig(), must have one of STM32_BOARD_USEHSI, STM32_BOARD_USEMSI, STM32_BOARD_USEHSE defined #endif @@ -760,9 +760,9 @@ static void stm32l4_stdclockconfig(void) #warning todo: regulator voltage according to clock freq /* Ensure Power control is enabled before modifying it. */ - regval = getreg32(STM32L4_RCC_APB1ENR1); + regval = getreg32(STM32_RCC_APB1ENR1); regval |= RCC_APB1ENR1_PWREN; - putreg32(regval, STM32L4_RCC_APB1ENR1); + putreg32(regval, STM32_RCC_APB1ENR1); /* Switch to Range 1 boost mode to support system frequencies up to * 120 MHz. @@ -772,147 +772,147 @@ static void stm32l4_stdclockconfig(void) * Range 2 is not supported. */ -#if STM32L4_SYSCLK_FREQUENCY > 80000000 || \ +#if STM32_SYSCLK_FREQUENCY > 80000000 || \ (defined(BOARD_MAX_PLL_FREQUENCY) && BOARD_MAX_PLL_FREQUENCY > 80000000) - regval = getreg32(STM32L4_PWR_CR5); + regval = getreg32(STM32_PWR_CR5); regval &= ~PWR_CR5_R1MODE; - putreg32(regval, STM32L4_PWR_CR5); + putreg32(regval, STM32_PWR_CR5); #endif /* Set the HCLK source/divider */ - regval = getreg32(STM32L4_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_HPRE_MASK; - regval |= STM32L4_RCC_CFGR_HPRE; - putreg32(regval, STM32L4_RCC_CFGR); + regval |= STM32_RCC_CFGR_HPRE; + putreg32(regval, STM32_RCC_CFGR); /* Set the PCLK2 divider */ - regval = getreg32(STM32L4_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_PPRE2_MASK; - regval |= STM32L4_RCC_CFGR_PPRE2; - putreg32(regval, STM32L4_RCC_CFGR); + regval |= STM32_RCC_CFGR_PPRE2; + putreg32(regval, STM32_RCC_CFGR); /* Set the PCLK1 divider */ - regval = getreg32(STM32L4_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_PPRE1_MASK; - regval |= STM32L4_RCC_CFGR_PPRE1; - putreg32(regval, STM32L4_RCC_CFGR); + regval |= STM32_RCC_CFGR_PPRE1; + putreg32(regval, STM32_RCC_CFGR); /* Set the PLL source and main divider */ - regval = getreg32(STM32L4_RCC_PLLCFG); + regval = getreg32(STM32_RCC_PLLCFG); /* Configure Main PLL */ /* Set the PLL dividers and multipliers to configure the main PLL */ - regval = (STM32L4_PLLCFG_PLLM | STM32L4_PLLCFG_PLLN | - STM32L4_PLLCFG_PLLP | STM32L4_PLLCFG_PLLQ | - STM32L4_PLLCFG_PLLR); + regval = (STM32_PLLCFG_PLLM | STM32_PLLCFG_PLLN | + STM32_PLLCFG_PLLP | STM32_PLLCFG_PLLQ | + STM32_PLLCFG_PLLR); -#ifdef STM32L4_PLLCFG_PLLP_ENABLED +#ifdef STM32_PLLCFG_PLLP_ENABLED regval |= RCC_PLLCFG_PLLPEN; #endif -#ifdef STM32L4_PLLCFG_PLLQ_ENABLED +#ifdef STM32_PLLCFG_PLLQ_ENABLED regval |= RCC_PLLCFG_PLLQEN; #endif -#ifdef STM32L4_PLLCFG_PLLR_ENABLED +#ifdef STM32_PLLCFG_PLLR_ENABLED regval |= RCC_PLLCFG_PLLREN; #endif /* XXX The choice of clock source to PLL (all three) is independent - * of the sys clock source choice, review the STM32L4_BOARD_USEHSI + * of the sys clock source choice, review the STM32_BOARD_USEHSI * name; probably split it into two, one for PLL source and one * for sys clock source. */ -#ifdef STM32L4_BOARD_USEHSI +#ifdef STM32_BOARD_USEHSI regval |= RCC_PLLCFG_PLLSRC_HSI; -#elif defined(STM32L4_BOARD_USEMSI) +#elif defined(STM32_BOARD_USEMSI) regval |= RCC_PLLCFG_PLLSRC_MSI; -#else /* if STM32L4_BOARD_USEHSE */ +#else /* if STM32_BOARD_USEHSE */ regval |= RCC_PLLCFG_PLLSRC_HSE; #endif - putreg32(regval, STM32L4_RCC_PLLCFG); + putreg32(regval, STM32_RCC_PLLCFG); /* Enable the main PLL */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_PLLON; - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Wait until the PLL is ready */ - while ((getreg32(STM32L4_RCC_CR) & RCC_CR_PLLRDY) == 0) + while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLRDY) == 0) { } -#ifdef CONFIG_STM32L4_SAI1PLL +#ifdef CONFIG_STM32_SAI1PLL /* Configure SAI1 PLL */ - regval = getreg32(STM32L4_RCC_PLLSAI1CFG); + regval = getreg32(STM32_RCC_PLLSAI1CFG); /* Set the PLL dividers and multipliers to configure the SAI1 PLL */ - regval = (STM32L4_PLLSAI1CFG_PLLN | STM32L4_PLLSAI1CFG_PLLP - | STM32L4_PLLSAI1CFG_PLLQ | STM32L4_PLLSAI1CFG_PLLR); + regval = (STM32_PLLSAI1CFG_PLLN | STM32_PLLSAI1CFG_PLLP + | STM32_PLLSAI1CFG_PLLQ | STM32_PLLSAI1CFG_PLLR); -#ifdef STM32L4_PLLSAI1CFG_PLLP_ENABLED +#ifdef STM32_PLLSAI1CFG_PLLP_ENABLED regval |= RCC_PLLSAI1CFG_PLLPEN; #endif -#ifdef STM32L4_PLLSAI1CFG_PLLQ_ENABLED +#ifdef STM32_PLLSAI1CFG_PLLQ_ENABLED regval |= RCC_PLLSAI1CFG_PLLQEN; #endif -#ifdef STM32L4_PLLSAI1CFG_PLLR_ENABLED +#ifdef STM32_PLLSAI1CFG_PLLR_ENABLED regval |= RCC_PLLSAI1CFG_PLLREN; #endif - putreg32(regval, STM32L4_RCC_PLLSAI1CFG); + putreg32(regval, STM32_RCC_PLLSAI1CFG); /* Enable the SAI1 PLL */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_PLLSAI1ON; - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Wait until the PLL is ready */ - while ((getreg32(STM32L4_RCC_CR) & RCC_CR_PLLSAI1RDY) == 0) + while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLSAI1RDY) == 0) { } #endif -#ifdef CONFIG_STM32L4_SAI2PLL +#ifdef CONFIG_STM32_SAI2PLL /* Configure SAI2 PLL */ - regval = getreg32(STM32L4_RCC_PLLSAI2CFG); + regval = getreg32(STM32_RCC_PLLSAI2CFG); /* Set the PLL dividers and multipliers to configure the SAI2 PLL */ - regval = (STM32L4_PLLSAI2CFG_PLLN | STM32L4_PLLSAI2CFG_PLLP | - STM32L4_PLLSAI2CFG_PLLR); + regval = (STM32_PLLSAI2CFG_PLLN | STM32_PLLSAI2CFG_PLLP | + STM32_PLLSAI2CFG_PLLR); -#ifdef STM32L4_PLLSAI2CFG_PLLP_ENABLED +#ifdef STM32_PLLSAI2CFG_PLLP_ENABLED regval |= RCC_PLLSAI2CFG_PLLPEN; #endif -#ifdef STM32L4_PLLSAI2CFG_PLLR_ENABLED +#ifdef STM32_PLLSAI2CFG_PLLR_ENABLED regval |= RCC_PLLSAI2CFG_PLLREN; #endif - putreg32(regval, STM32L4_RCC_PLLSAI2CFG); + putreg32(regval, STM32_RCC_PLLSAI2CFG); /* Enable the SAI2 PLL */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_PLLSAI2ON; - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Wait until the PLL is ready */ - while ((getreg32(STM32L4_RCC_CR) & RCC_CR_PLLSAI2RDY) == 0) + while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLSAI2RDY) == 0) { } #endif @@ -927,34 +927,34 @@ static void stm32l4_stdclockconfig(void) /* Enable FLASH prefetch, instruction cache and data cache */ -#ifdef CONFIG_STM32L4_FLASH_PREFETCH +#ifdef CONFIG_STM32_FLASH_PREFETCH regval |= (FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_PRFTEN); #else regval |= (FLASH_ACR_ICEN | FLASH_ACR_DCEN); #endif - putreg32(regval, STM32L4_FLASH_ACR); + putreg32(regval, STM32_FLASH_ACR); /* Select the main PLL as system clock source */ - regval = getreg32(STM32L4_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_SW_MASK; regval |= RCC_CFGR_SW_PLL; - putreg32(regval, STM32L4_RCC_CFGR); + putreg32(regval, STM32_RCC_CFGR); /* Wait until the PLL source is used as the system clock source */ - while ((getreg32(STM32L4_RCC_CFGR) & RCC_CFGR_SWS_MASK) != + while ((getreg32(STM32_RCC_CFGR) & RCC_CFGR_SWS_MASK) != RCC_CFGR_SWS_PLL) { } -#if defined(CONFIG_STM32L4_IWDG) || defined(CONFIG_STM32L4_RTC_LSICLOCK) +#if defined(CONFIG_STM32_IWDG) || defined(CONFIG_STM32_RTC_LSICLOCK) /* Low speed internal clock source LSI */ - stm32l4_rcc_enablelsi(); + stm32_rcc_enablelsi(); #endif -#if defined(STM32L4_USE_LSE) +#if defined(STM32_USE_LSE) /* Low speed external clock source LSE * * TODO: There is another case where the LSE needs to @@ -967,16 +967,16 @@ static void stm32l4_stdclockconfig(void) * this for automatically trimming MSI, etc. */ - stm32l4_rcc_enablelse(); + stm32_rcc_enablelse(); -# if defined(STM32L4_BOARD_USEMSI) +# if defined(STM32_BOARD_USEMSI) /* Now that LSE is up, auto trim the MSI */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_MSIPLLEN; - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); # endif -#endif /* STM32L4_USE_LSE */ +#endif /* STM32_USE_LSE */ } } #endif @@ -994,10 +994,10 @@ static inline void rcc_enableperipherals(void) rcc_enableapb1(); rcc_enableapb2(); -#ifdef STM32L4_USE_HSI48 +#ifdef STM32_USE_HSI48 /* Enable HSI48 clocking to support USB transfers or RNG */ - stm32l4_enable_hsi48(STM32L4_HSI48_SYNCSRC); + stm32_enable_hsi48(STM32_HSI48_SYNCSRC); #endif } diff --git a/arch/arm/src/stm32l5/CMakeLists.txt b/arch/arm/src/stm32l5/CMakeLists.txt index 18f0fdaf03cf9..cfd801d08ab3e 100644 --- a/arch/arm/src/stm32l5/CMakeLists.txt +++ b/arch/arm/src/stm32l5/CMakeLists.txt @@ -33,8 +33,6 @@ list( stm32l5_rcc.c stm32l5_serial.c stm32l5_start.c - stm32l5_waste.c - stm32l5_uid.c stm32l5_spi.c stm32l5_lse.c stm32l5_lsi.c @@ -61,8 +59,10 @@ endif() # Required chip type specific files -if(CONFIG_STM32L5_STM32L562XX) +if(CONFIG_STM32_STM32L562XX) list(APPEND SRCS stm32l562xx_rcc.c) endif() target_sources(arch PRIVATE ${SRCS}) + +add_subdirectory(${NUTTX_DIR}/arch/arm/src/common/stm32 stm32_common) diff --git a/arch/arm/src/stm32l5/Kconfig b/arch/arm/src/stm32l5/Kconfig index 4a7589a116ad5..1aa316fce613b 100644 --- a/arch/arm/src/stm32l5/Kconfig +++ b/arch/arm/src/stm32l5/Kconfig @@ -7,6 +7,15 @@ if ARCH_CHIP_STM32L5 comment "STM32L5 Configuration Options" +config STM32_L5_PERIPHERALS + bool + default y + select STM32_HAVE_RTC_SUBSECONDS + select STM32_HAVE_SPI1 + select STM32_HAVE_SPI2 + select STM32_HAVE_SPI3 + select STM32_HAVE_SYSCFG + choice prompt "STM32 L5 Chip Selection" default ARCH_CHIP_STM32L552ZE @@ -14,16 +23,16 @@ choice config ARCH_CHIP_STM32L552ZE bool "STM32L552ZE" - select STM32L5_STM32L562XX - select STM32L5_FLASH_CONFIG_E + select STM32_STM32L562XX + select STM32_FLASH_CONFIG_E select STM32L5_IO_CONFIG_Z ---help--- STM32 L5 Cortex M33, 512 Kb FLASH, 256 Kb SRAM config ARCH_CHIP_STM32L562QE bool "STM32L562QE" - select STM32L5_STM32L562XX - select STM32L5_FLASH_CONFIG_E + select STM32_STM32L562XX + select STM32_FLASH_CONFIG_E select STM32L5_IO_CONFIG_Q ---help--- STM32 L5 Cortex M33, 512 Kb FLASH, 256 Kb SRAM @@ -32,3243 +41,69 @@ endchoice # STM32 L5 Chip Selection # Chip families: -config STM32L5_STM32L562XX - # STM32L552 and STM32L562 devices documented in RM0439 +# STM32L552 and STM32L562 devices documented in RM0439 +config STM32_STM32L562XX bool default n select ARCH_HAVE_FPU - select STM32L5_HAVE_LPUART1 - select STM32L5_HAVE_USART1 - select STM32L5_HAVE_USART2 - select STM32L5_HAVE_USART3 - select STM32L5_HAVE_UART4 - select STM32L5_HAVE_UART5 - -choice - prompt "Override Flash Size Designator" - depends on ARCH_CHIP_STM32L5 - default STM32L5_FLASH_OVERRIDE_DEFAULT - ---help--- - STM32L5 series parts numbering (sans the package type) ends with a letter - that designates the FLASH size. - - Designator Size in KiB - 8 64 - B 128 - C 256 - E 512 - G 1024 - I 2048 - - This configuration option defaults to using the configuration based on that designator - or the default smaller size if there is no last character designator is present in the - STM32 Chip Selection. - - Examples: - If the STM32L576VE is chosen, the Flash configuration would be 'E', if a variant of - the part with a 1024 KiB Flash is released in the future one could simply select - the 'G' designator here. - - If an STM32L5xxx Series parts is chosen the default Flash configuration will be set - herein and can be changed. - -config STM32L5_FLASH_OVERRIDE_DEFAULT - bool "Default" - -config STM32L5_FLASH_OVERRIDE_8 - bool "8 64 KB" - -config STM32L5_FLASH_OVERRIDE_B - bool "B 128 KB" - -config STM32L5_FLASH_OVERRIDE_C - bool "C 256 KB" - -config STM32L5_FLASH_OVERRIDE_E - bool "E 512 KB" - -config STM32L5_FLASH_OVERRIDE_G - bool "G 1024 KB" - -config STM32L5_FLASH_OVERRIDE_I - bool "I 2048 KB" - -endchoice # "Override Flash Size Designator" - -# Flash configurations - -config STM32L5_FLASH_CONFIG_8 - bool - default n - depends on STM32L5_STM32L512XX - -config STM32L5_FLASH_CONFIG_B - bool - default n - depends on STM32L5_STM32L5X1 || STM32L5_STM32L5X3 - -config STM32L5_FLASH_CONFIG_C - bool - default n - depends on !STM32L5_STM32L596XX - -config STM32L5_FLASH_CONFIG_E - bool - default n + select STM32_HAVE_LPUART1 + select STM32_HAVE_USART1 + select STM32_HAVE_USART2 + select STM32_HAVE_USART3 + select STM32_HAVE_UART4 + select STM32_HAVE_UART5 -config STM32L5_FLASH_CONFIG_G - bool - default n - depends on STM32L5_STM32L5X5 || STM32L5_STM32L5X6 - -config STM32L5_FLASH_CONFIG_I - bool - default n - depends on STM32L5_STM32L5XR # Pin/package configurations config STM32L5_IO_CONFIG_K + # Package designator K bool default n config STM32L5_IO_CONFIG_T + # Package designator T bool default n config STM32L5_IO_CONFIG_C + # Package designator C bool default n config STM32L5_IO_CONFIG_R + # Package designator R bool default n config STM32L5_IO_CONFIG_J + # Package designator J bool default n config STM32L5_IO_CONFIG_M + # Package designator M bool default n config STM32L5_IO_CONFIG_V + # Package designator V bool default n config STM32L5_IO_CONFIG_Q + # Package designator Q bool default n config STM32L5_IO_CONFIG_Z + # Package designator Z bool default n config STM32L5_IO_CONFIG_A + # Package designator A bool default n -comment "STM32L5 SRAM2 Options" - -config STM32L5_SRAM2_HEAP - bool "SRAM2 is used for heap" - default n - select STM32L5_SRAM2_INIT - ---help--- - The STM32L5 SRAM2 region has special properties (power, protection, parity) - which may be used by the application for special purposes. But if these - special properties are not needed, it may be instead added to the heap for - use by malloc(). - NOTE: you must also select an appropriate number of memory regions in the - 'Memory Management' section. - -config STM32L5_SRAM2_INIT - bool "SRAM2 is initialized to zero" - default n - ---help--- - The STM32L5 SRAM2 region has parity checking. However, when the system - powers on, the memory is in an unknown state, and reads from uninitialized - memory can trigger parity faults from the random data. This can be - avoided by first writing to all locations to force the parity into a valid - state. - However, if the SRAM2 is being used for it's battery-backed capability, - this may be undesirable (because it will destroy the contents). In that - case, the board should handle the initialization itself at the appropriate - time. - -comment "STM32L5 Peripherals" - -menu "STM32L5 Peripheral Support" - -# These "hidden" settings determine is a peripheral option is available for the -# selection MCU - -config STM32L5_HAVE_LPUART1 - bool - default n - -config STM32L5_HAVE_USART1 - bool - default n - -config STM32L5_HAVE_USART2 - bool - default n - -config STM32L5_HAVE_USART3 - bool - default n - -config STM32L5_HAVE_UART4 - bool - default n - -config STM32L5_HAVE_UART5 - bool - default n - -# These "hidden" settings are the OR of individual peripheral selections -# indicating that the general capability is required. - -config STM32L5_SPI - bool - default n - -config STM32L5_USART - bool - default n - -# These are the peripheral selections proper - -comment "AHB1 Peripherals" - -comment "AHB2 Peripherals" - -comment "AHB3 Peripherals" - -comment "APB1 Peripherals" - -config STM32L5_PWR - bool "PWR" - default n - -config STM32L5_RTC - bool "RTC" - default n - -config STM32L5_SPI2 - bool "SPI2" - default n - select SPI - select STM32L5_SPI - -config STM32L5_SPI3 - bool "SPI3" - default n - select SPI - select STM32L5_SPI - -config STM32L5_LPUART1 - bool "LPUART1" - default n - depends on STM32L5_HAVE_LPUART1 - select ARCH_HAVE_SERIAL_TERMIOS - select STM32L5_USART - -config STM32L5_USART2 - bool "USART2" - default n - depends on STM32L5_HAVE_USART2 - select ARCH_HAVE_SERIAL_TERMIOS - select STM32L5_USART - -config STM32L5_USART3 - bool "USART3" - default n - depends on STM32L5_HAVE_USART3 - select ARCH_HAVE_SERIAL_TERMIOS - select STM32L5_USART - -config STM32L5_UART4 - bool "UART4" - default n - depends on STM32L5_HAVE_UART4 - select ARCH_HAVE_SERIAL_TERMIOS - select STM32L5_USART - -config STM32L5_UART5 - bool "UART5" - default n - depends on STM32L5_HAVE_UART5 - select ARCH_HAVE_SERIAL_TERMIOS - select STM32L5_USART - -comment "APB2 Peripherals" - -config STM32L5_SYSCFG - bool "SYSCFG" - default y - -config STM32L5_SPI1 - bool "SPI1" - default n - select SPI - select STM32L5_SPI - -config STM32L5_USART1 - bool "USART1" - default n - depends on STM32L5_HAVE_USART1 - select ARCH_HAVE_SERIAL_TERMIOS - select STM32L5_USART - -endmenu - -config STM32L5_SAI1PLL - bool "SAI1PLL" - default n - ---help--- - The STM32L5 has a separate PLL for the SAI1 block. - Set this true and provide configuration parameters in - board.h to use this PLL. - -config STM32L5_SAI2PLL - bool "SAI2PLL" - default n - depends on STM32L5_HAVE_SAI2 - ---help--- - The STM32L5 has a separate PLL for the SAI2 block. - Set this true and provide configuration parameters in - board.h to use this PLL. - -config STM32L5_FLASH_PREFETCH - bool "Enable FLASH Pre-fetch" - default y - ---help--- - Enable FLASH prefetch - -config STM32L5_DISABLE_IDLE_SLEEP_DURING_DEBUG - bool "Disable IDLE Sleep (WFI) in debug mode" - default n - ---help--- - In debug configuration, disables the WFI instruction in the IDLE loop - to prevent the JTAG from disconnecting. With some JTAG debuggers, such - as the ST-LINK2 with OpenOCD, if the ARM is put to sleep via the WFI - instruction, the debugger will disconnect, terminating the debug session. - -config ARCH_BOARD_STM32L5_CUSTOM_CLOCKCONFIG - bool "Custom clock configuration" - default n - ---help--- - Enables special, board-specific STM32 clock configuration. - -config STM32L5_HAVE_RTC_SUBSECONDS - bool - select ARCH_HAVE_RTC_SUBSECONDS - default y - -menu "RTC Configuration" - depends on STM32L5_RTC - -config STM32L5_RTC_MAGIC_REG - int "BKP register" - default 0 - range 0 31 - ---help--- - The BKP register used to store/check the Magic value to determine if - RTC is already setup - -config STM32L5_RTC_MAGIC - hex "RTC Magic 1" - default 0xfacefeed - ---help--- - Value used as Magic to determine if the RTC is already setup - -config STM32L5_RTC_MAGIC_TIME_SET - hex "RTC Magic 2" - default 0xf00dface - ---help--- - Value used as Magic to determine if the RTC has been setup and has - time set - -choice - prompt "RTC clock source" - default STM32L5_RTC_LSECLOCK - depends on STM32L5_RTC - -config STM32L5_RTC_LSECLOCK - bool "LSE clock" - ---help--- - Drive the RTC with the LSE clock - -config STM32L5_RTC_LSICLOCK - bool "LSI clock" - ---help--- - Drive the RTC with the LSI clock - -config STM32L5_RTC_HSECLOCK - bool "HSE clock" - ---help--- - Drive the RTC with the HSE clock, divided down to 1MHz. - -endchoice - -if STM32L5_RTC_LSECLOCK - -config STM32L5_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY - bool "Automatically boost the LSE oscillator drive capability level until it starts-up" - default n - ---help--- - This will cycle through the values from low to high. To avoid - damaging the crystal. We want to use the lowest setting that gets - the OSC running. See app note AN2867 - - 0 = Low drive capability (default) - 1 = Medium low drive capability - 2 = Medium high drive capability - 3 = High drive capability - -config STM32L5_RTC_LSECLOCK_START_DRV_CAPABILITY - int "LSE oscillator drive capability level at LSE start-up" - default 0 - range 0 3 - depends on !STM32L5_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY - ---help--- - 0 = Low drive capability (default) - 1 = Medium low drive capability - 2 = Medium high drive capability - 3 = High drive capability - -config STM32L5_RTC_LSECLOCK_LOWER_RUN_DRV_CAPABILITY - bool "Decrease LSE oscillator drive capability after LSE start-up" - default n - depends on !STM32L5_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY - ---help--- - The LSE oscillator drive capability can remain at the level used - during LSE start-up at run-time, or it can be reduced to the - 'Low drive capability' once the LSE started up successfully. - -endif # STM32L5_RTC_LSECLOCK - -endmenu # RTC Configuration - -menu "Timer Configuration" - -if SCHED_TICKLESS - -config STM32L5_ONESHOT - bool - default y - -config STM32L5_FREERUN - bool - default y - -config STM32L5_TICKLESS_ONESHOT - int "Tickless one-shot timer channel" - default 2 - range 1 8 - depends on STM32L5_ONESHOT - ---help--- - If the Tickless OS feature is enabled, then one clock must be - assigned to provide the one-shot timer needed by the OS. - -config STM32L5_TICKLESS_FREERUN - int "Tickless free-running timer channel" - default 5 - range 1 8 - depends on STM32L5_FREERUN - ---help--- - If the Tickless OS feature is enabled, then one clock must be - assigned to provide the free-running timer needed by the OS. - -endif # SCHED_TICKLESS - -if !SCHED_TICKLESS - -config STM32L5_ONESHOT - bool "TIM one-shot wrapper" - default n - ---help--- - Enable a wrapper around the low level timer/counter functions to - support one-shot timer. - -config STM32L5_FREERUN - bool "TIM free-running wrapper" - default n - ---help--- - Enable a wrapper around the low level timer/counter functions to - support a free-running timer. - -endif # !SCHED_TICKLESS - -config STM32L5_ONESHOT_MAXTIMERS - int "Maximum number of oneshot timers" - default 1 - range 1 8 - depends on STM32L5_ONESHOT - ---help--- - Determines the maximum number of oneshot timers that can be - supported. This setting pre-allocates some minimal support for each - of the timers and places an upper limit on the number of oneshot - timers that you can use. - -config STM32L5_LPTIM1_PWM - bool "LPTIM1 PWM" - default n - depends on STM32L5_LPTIM1 - select PWM - ---help--- - Reserve low-power timer 1 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32L5_LPTIM1 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32L5_LPTIM1_PWM - -choice - prompt "LPTIM1 clock source" - default STM32L5_LPTIM1_CLK_APB1 - -config STM32L5_LPTIM1_CLK_APB1 - bool "Clock LPTIM1 from APB1" - -config STM32L5_LPTIM1_CLK_LSE - bool "Clock LPTIM1 from LSE" - -config STM32L5_LPTIM1_CLK_LSI - bool "Clock LPTIM1 from LSI" - -config STM32L5_LPTIM1_CLK_HSI - bool "Clock LPTIM1 from HSI" -endchoice - -endif # STM32L5_LPTIM1_PWM - -config STM32L5_LPTIM2_PWM - bool "LPTIM2 PWM" - default n - depends on STM32L5_LPTIM2 - select PWM - ---help--- - Reserve low-power timer 2 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32L5_LPTIM2 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32L5_LPTIM2_PWM - -choice - prompt "LPTIM2 clock source" - default STM32L5_LPTIM2_CLK_APB1 - -config STM32L5_LPTIM2_CLK_APB1 - bool "Clock LPTIM2 from APB1" - -config STM32L5_LPTIM2_CLK_LSE - bool "Clock LPTIM2 from LSE" - -config STM32L5_LPTIM2_CLK_LSI - bool "Clock LPTIM2 from LSI" - -config STM32L5_LPTIM2_CLK_HSI - bool "Clock LPTIM2 from HSI" -endchoice - -endif # STM32L5_LPTIM2_PWM - -config STM32L5_TIM1_PWM - bool "TIM1 PWM" - default n - depends on STM32L5_TIM1 - select PWM - ---help--- - Reserve timer 1 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32L5_TIM1 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32L5_TIM1_PWM - -config STM32L5_TIM1_MODE - int "TIM1 Mode" - default 0 - range 0 4 - ---help--- - Specifies the timer mode. - -if STM32L5_PWM_MULTICHAN - -config STM32L5_TIM1_CHANNEL1 - bool "TIM1 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32L5_TIM1_CHANNEL1 - -config STM32L5_TIM1_CH1MODE - int "TIM1 Channel 1 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -config STM32L5_TIM1_CH1OUT - bool "TIM1 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -config STM32L5_TIM1_CH1NOUT - bool "TIM1 Channel 1 Complementary Output" - default n - depends on STM32L5_TIM1_CH1OUT - ---help--- - Enables channel 1 complementary output. - -endif # STM32L5_TIM1_CHANNEL1 - -config STM32L5_TIM1_CHANNEL2 - bool "TIM1 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32L5_TIM1_CHANNEL2 - -config STM32L5_TIM1_CH2MODE - int "TIM1 Channel 2 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -config STM32L5_TIM1_CH2OUT - bool "TIM1 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -config STM32L5_TIM1_CH2NOUT - bool "TIM1 Channel 2 Complemenrary Output" - default n - depends on STM32L5_TIM1_CH2OUT - ---help--- - Enables channel 2 complementary output. - -endif # STM32L5_TIM1_CHANNEL2 - -config STM32L5_TIM1_CHANNEL3 - bool "TIM1 Channel 3" - default n - ---help--- - Enables channel 3. - -if STM32L5_TIM1_CHANNEL3 - -config STM32L5_TIM1_CH3MODE - int "TIM1 Channel 3 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -config STM32L5_TIM1_CH3OUT - bool "TIM1 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -config STM32L5_TIM1_CH3NOUT - bool "TIM1 Channel 3 Complementary Output" - default n - depends on STM32L5_TIM1_CH3OUT - ---help--- - Enables channel 3 complementary output. - -endif # STM32L5_TIM1_CHANNEL3 - -config STM32L5_TIM1_CHANNEL5 - bool "TIM1 Channel 4" - default n - ---help--- - Enables channel 4. - -if STM32L5_TIM1_CHANNEL5 - -config STM32L5_TIM1_CH4MODE - int "TIM1 Channel 4 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -config STM32L5_TIM1_CH4OUT - bool "TIM1 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32L5_TIM1_CHANNEL5 - -endif # STM32L5_PWM_MULTICHAN - -if !STM32L5_PWM_MULTICHAN - -config STM32L5_TIM1_CHANNEL - int "TIM1 PWM Output Channel" - default 1 - range 1 4 - ---help--- - If TIM1 is enabled for PWM usage, you also need specifies the timer output - channel {1,..,4} - -config STM32L5_TIM1_CHMODE - int "TIM1 Channel Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -endif # !STM32L5_PWM_MULTICHAN - -endif # STM32L5_TIM1_PWM - -config STM32L5_TIM2_PWM - bool "TIM2 PWM" - default n - depends on STM32L5_TIM2 - select PWM - ---help--- - Reserve timer 2 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32L5_TIM2 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32L5_TIM2_PWM - -config STM32L5_TIM2_MODE - int "TIM2 Mode" - default 0 - range 0 4 - ---help--- - Specifies the timer mode. - -if STM32L5_PWM_MULTICHAN - -config STM32L5_TIM2_CHANNEL1 - bool "TIM2 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32L5_TIM2_CHANNEL1 - -config STM32L5_TIM2_CH1MODE - int "TIM2 Channel 1 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -config STM32L5_TIM2_CH1OUT - bool "TIM2 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32L5_TIM2_CHANNEL1 - -config STM32L5_TIM2_CHANNEL2 - bool "TIM2 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32L5_TIM2_CHANNEL2 - -config STM32L5_TIM2_CH2MODE - int "TIM2 Channel 2 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -config STM32L5_TIM2_CH2OUT - bool "TIM2 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32L5_TIM2_CHANNEL2 - -config STM32L5_TIM2_CHANNEL3 - bool "TIM2 Channel 3" - default n - ---help--- - Enables channel 3. - -if STM32L5_TIM2_CHANNEL3 - -config STM32L5_TIM2_CH3MODE - int "TIM2 Channel 3 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -config STM32L5_TIM2_CH3OUT - bool "TIM2 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -endif # STM32L5_TIM2_CHANNEL3 - -config STM32L5_TIM2_CHANNEL5 - bool "TIM2 Channel 4" - default n - ---help--- - Enables channel 4. - -if STM32L5_TIM2_CHANNEL5 - -config STM32L5_TIM2_CH4MODE - int "TIM2 Channel 4 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -config STM32L5_TIM2_CH4OUT - bool "TIM2 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32L5_TIM2_CHANNEL5 - -endif # STM32L5_PWM_MULTICHAN - -if !STM32L5_PWM_MULTICHAN - -config STM32L5_TIM2_CHANNEL - int "TIM2 PWM Output Channel" - default 1 - range 1 4 - ---help--- - If TIM2 is enabled for PWM usage, you also need specifies the timer output - channel {1,..,4} - -config STM32L5_TIM2_CHMODE - int "TIM2 Channel Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -endif # !STM32L5_PWM_MULTICHAN - -endif # STM32L5_TIM2_PWM - -config STM32L5_TIM3_PWM - bool "TIM3 PWM" - default n - depends on STM32L5_TIM3 - select PWM - ---help--- - Reserve timer 3 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32L5_TIM3 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32L5_TIM3_PWM - -config STM32L5_TIM3_MODE - int "TIM3 Mode" - default 0 - range 0 4 - ---help--- - Specifies the timer mode. - -if STM32L5_PWM_MULTICHAN - -config STM32L5_TIM3_CHANNEL1 - bool "TIM3 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32L5_TIM3_CHANNEL1 - -config STM32L5_TIM3_CH1MODE - int "TIM3 Channel 1 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -config STM32L5_TIM3_CH1OUT - bool "TIM3 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32L5_TIM3_CHANNEL1 - -config STM32L5_TIM3_CHANNEL2 - bool "TIM3 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32L5_TIM3_CHANNEL2 - -config STM32L5_TIM3_CH2MODE - int "TIM3 Channel 2 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -config STM32L5_TIM3_CH2OUT - bool "TIM3 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32L5_TIM3_CHANNEL2 - -config STM32L5_TIM3_CHANNEL3 - bool "TIM3 Channel 3" - default n - ---help--- - Enables channel 3. - -if STM32L5_TIM3_CHANNEL3 - -config STM32L5_TIM3_CH3MODE - int "TIM3 Channel 3 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -config STM32L5_TIM3_CH3OUT - bool "TIM3 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -endif # STM32L5_TIM3_CHANNEL3 - -config STM32L5_TIM3_CHANNEL5 - bool "TIM3 Channel 4" - default n - ---help--- - Enables channel 4. - -if STM32L5_TIM3_CHANNEL5 - -config STM32L5_TIM3_CH4MODE - int "TIM3 Channel 4 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -config STM32L5_TIM3_CH4OUT - bool "TIM3 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32L5_TIM3_CHANNEL5 - -endif # STM32L5_PWM_MULTICHAN - -if !STM32L5_PWM_MULTICHAN - -config STM32L5_TIM3_CHANNEL - int "TIM3 PWM Output Channel" - default 1 - range 1 4 - ---help--- - If TIM3 is enabled for PWM usage, you also need specifies the timer output - channel {1,..,4} - -config STM32L5_TIM3_CHMODE - int "TIM3 Channel Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -endif # !STM32L5_PWM_MULTICHAN - -endif # STM32L5_TIM3_PWM - -config STM32L5_TIM4_PWM - bool "TIM4 PWM" - default n - depends on STM32L5_TIM4 - select PWM - ---help--- - Reserve timer 4 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32L5_TIM4 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32L5_TIM4_PWM - -config STM32L5_TIM4_MODE - int "TIM4 Mode" - default 0 - range 0 4 - ---help--- - Specifies the timer mode. - -if STM32L5_PWM_MULTICHAN - -config STM32L5_TIM4_CHANNEL1 - bool "TIM4 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32L5_TIM4_CHANNEL1 - -config STM32L5_TIM4_CH1MODE - int "TIM4 Channel 1 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -config STM32L5_TIM4_CH1OUT - bool "TIM4 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32L5_TIM4_CHANNEL1 - -config STM32L5_TIM4_CHANNEL2 - bool "TIM4 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32L5_TIM4_CHANNEL2 - -config STM32L5_TIM4_CH2MODE - int "TIM4 Channel 2 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -config STM32L5_TIM4_CH2OUT - bool "TIM4 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32L5_TIM4_CHANNEL2 - -config STM32L5_TIM4_CHANNEL3 - bool "TIM4 Channel 3" - default n - ---help--- - Enables channel 3. - -if STM32L5_TIM4_CHANNEL3 - -config STM32L5_TIM4_CH3MODE - int "TIM4 Channel 3 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -config STM32L5_TIM4_CH3OUT - bool "TIM4 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -endif # STM32L5_TIM4_CHANNEL3 - -config STM32L5_TIM4_CHANNEL5 - bool "TIM4 Channel 4" - default n - ---help--- - Enables channel 4. - -if STM32L5_TIM4_CHANNEL5 - -config STM32L5_TIM4_CH4MODE - int "TIM4 Channel 4 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -config STM32L5_TIM4_CH4OUT - bool "TIM4 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32L5_TIM4_CHANNEL5 - -endif # STM32L5_PWM_MULTICHAN - -if !STM32L5_PWM_MULTICHAN - -config STM32L5_TIM4_CHANNEL - int "TIM4 PWM Output Channel" - default 1 - range 1 4 - ---help--- - If TIM4 is enabled for PWM usage, you also need specifies the timer output - channel {1,..,4} - -config STM32L5_TIM4_CHMODE - int "TIM4 Channel Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -endif # !STM32L5_PWM_MULTICHAN - -endif # STM32L5_TIM4_PWM - -config STM32L5_TIM5_PWM - bool "TIM5 PWM" - default n - depends on STM32L5_TIM5 - select PWM - ---help--- - Reserve timer 5 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32L5_TIM5 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32L5_TIM5_PWM - -config STM32L5_TIM5_MODE - int "TIM5 Mode" - default 0 - range 0 4 - ---help--- - Specifies the timer mode. - -if STM32L5_PWM_MULTICHAN - -config STM32L5_TIM5_CHANNEL1 - bool "TIM5 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32L5_TIM5_CHANNEL1 - -config STM32L5_TIM5_CH1MODE - int "TIM5 Channel 1 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -config STM32L5_TIM5_CH1OUT - bool "TIM5 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32L5_TIM5_CHANNEL1 - -config STM32L5_TIM5_CHANNEL2 - bool "TIM5 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32L5_TIM5_CHANNEL2 - -config STM32L5_TIM5_CH2MODE - int "TIM5 Channel 2 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -config STM32L5_TIM5_CH2OUT - bool "TIM5 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32L5_TIM5_CHANNEL2 - -config STM32L5_TIM5_CHANNEL3 - bool "TIM5 Channel 3" - default n - ---help--- - Enables channel 3. - -if STM32L5_TIM5_CHANNEL3 - -config STM32L5_TIM5_CH3MODE - int "TIM5 Channel 3 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -config STM32L5_TIM5_CH3OUT - bool "TIM5 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -endif # STM32L5_TIM5_CHANNEL3 - -config STM32L5_TIM5_CHANNEL5 - bool "TIM5 Channel 4" - default n - ---help--- - Enables channel 4. - -if STM32L5_TIM5_CHANNEL5 - -config STM32L5_TIM5_CH4MODE - int "TIM5 Channel 4 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -config STM32L5_TIM5_CH4OUT - bool "TIM5 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32L5_TIM5_CHANNEL5 - -endif # STM32L5_PWM_MULTICHAN - -if !STM32L5_PWM_MULTICHAN - -config STM32L5_TIM5_CHANNEL - int "TIM5 PWM Output Channel" - default 1 - range 1 4 - ---help--- - If TIM5 is enabled for PWM usage, you also need specifies the timer output - channel {1,..,4} - -config STM32L5_TIM5_CHMODE - int "TIM5 Channel Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -endif # !STM32L5_PWM_MULTICHAN - -endif # STM32L5_TIM5_PWM - -config STM32L5_TIM8_PWM - bool "TIM8 PWM" - default n - depends on STM32L5_TIM8 - select PWM - ---help--- - Reserve timer 8 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32L5_TIM8 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32L5_TIM8_PWM - -config STM32L5_TIM8_MODE - int "TIM8 Mode" - default 0 - range 0 4 - ---help--- - Specifies the timer mode. - -if STM32L5_PWM_MULTICHAN - -config STM32L5_TIM8_CHANNEL1 - bool "TIM8 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32L5_TIM8_CHANNEL1 - -config STM32L5_TIM8_CH1MODE - int "TIM8 Channel 1 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -config STM32L5_TIM8_CH1OUT - bool "TIM8 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -config STM32L5_TIM8_CH1NOUT - bool "TIM8 Channel 1 Complementary Output" - default n - depends on STM32L5_TIM8_CH1OUT - ---help--- - Enables channel 1 complementary output. - -endif # STM32L5_TIM8_CHANNEL1 - -config STM32L5_TIM8_CHANNEL2 - bool "TIM8 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32L5_TIM8_CHANNEL2 - -config STM32L5_TIM8_CH2MODE - int "TIM8 Channel 2 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -config STM32L5_TIM8_CH2OUT - bool "TIM8 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -config STM32L5_TIM8_CH2NOUT - bool "TIM8 Channel 2 Complementary Output" - default n - depends on STM32L5_TIM8_CH2OUT - ---help--- - Enables channel 2 complementary output. - -endif # STM32L5_TIM8_CHANNEL2 - -config STM32L5_TIM8_CHANNEL3 - bool "TIM8 Channel 3" - default n - ---help--- - Enables channel 3. - -if STM32L5_TIM8_CHANNEL3 - -config STM32L5_TIM8_CH3MODE - int "TIM8 Channel 3 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -config STM32L5_TIM8_CH3OUT - bool "TIM8 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -config STM32L5_TIM8_CH3NOUT - bool "TIM8 Channel 3 Complementary Output" - default n - depends on STM32L5_TIM8_CH3OUT - ---help--- - Enables channel 3 complementary output. - -endif # STM32L5_TIM8_CHANNEL3 - -config STM32L5_TIM8_CHANNEL5 - bool "TIM8 Channel 4" - default n - ---help--- - Enables channel 4. - -if STM32L5_TIM8_CHANNEL5 - -config STM32L5_TIM8_CH4MODE - int "TIM8 Channel 4 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -config STM32L5_TIM8_CH4OUT - bool "TIM8 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32L5_TIM8_CHANNEL5 - -endif # STM32L5_PWM_MULTICHAN - -if !STM32L5_PWM_MULTICHAN - -config STM32L5_TIM8_CHANNEL - int "TIM8 PWM Output Channel" - default 1 - range 1 4 - ---help--- - If TIM8 is enabled for PWM usage, you also need specifies the timer output - channel {1,..,4} - -config STM32L5_TIM8_CHMODE - int "TIM8 Channel Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -endif # !STM32L5_PWM_MULTICHAN - -endif # STM32L5_TIM8_PWM - -config STM32L5_TIM15_PWM - bool "TIM15 PWM" - default n - depends on STM32L5_TIM15 - select PWM - ---help--- - Reserve timer 15 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32L5_TIM15 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32L5_TIM15_PWM - -if STM32L5_PWM_MULTICHAN - -config STM32L5_TIM15_CHANNEL1 - bool "TIM15 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32L5_TIM15_CHANNEL1 - -config STM32L5_TIM15_CH1MODE - int "TIM15 Channel 1 Mode" - default 0 - range 0 3 - ---help--- - Specifies the channel mode. - -config STM32L5_TIM15_CH1OUT - bool "TIM15 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -config STM32L5_TIM15_CH1NOUT - bool "TIM15 Channel 1 Complementary Output" - default n - depends on STM32L5_TIM15_CH1OUT - ---help--- - Enables channel 1 complementary output. - -endif # STM32L5_TIM15_CHANNEL1 - -config STM32L5_TIM15_CHANNEL2 - bool "TIM15 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32L5_TIM15_CHANNEL2 - -config STM32L5_TIM15_CH2MODE - int "TIM15 Channel 2 Mode" - default 0 - range 0 3 - ---help--- - Specifies the channel mode. - -config STM32L5_TIM15_CH2OUT - bool "TIM15 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32L5_TIM15_CHANNEL2 - -endif # STM32L5_PWM_MULTICHAN - -if !STM32L5_PWM_MULTICHAN - -config STM32L5_TIM15_CHANNEL - int "TIM15 PWM Output Channel" - default 1 - range 1 2 - ---help--- - If TIM15 is enabled for PWM usage, you also need specifies the timer output - channel {1,2} - -config STM32L5_TIM15_CHMODE - int "TIM15 Channel Mode" - default 0 - range 0 3 - ---help--- - Specifies the channel mode. - -endif # !STM32L5_PWM_MULTICHAN - -endif # STM32L5_TIM15_PWM - -config STM32L5_TIM16_PWM - bool "TIM16 PWM" - default n - depends on STM32L5_TIM16 - select PWM - ---help--- - Reserve timer 16 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32L5_TIM16 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32L5_TIM16_PWM - -if STM32L5_PWM_MULTICHAN - -config STM32L5_TIM16_CHANNEL1 - bool "TIM16 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32L5_TIM16_CHANNEL1 - -config STM32L5_TIM16_CH1MODE - int "TIM16 Channel 1 Mode" - default 0 - range 0 1 - ---help--- - Specifies the channel mode. - -config STM32L5_TIM16_CH1OUT - bool "TIM16 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -config STM32L5_TIM16_CH1NOUT - bool "TIM16 Channel 1 Complementary Output" - default n - depends on STM32L5_TIM16_CH1OUT - ---help--- - Enables channel 1 complementary output. - -endif # STM32L5_TIM16_CHANNEL1 - -endif # STM32L5_PWM_MULTICHAN - -if !STM32L5_PWM_MULTICHAN - -config STM32L5_TIM16_CHANNEL - int "TIM16 PWM Output Channel" - default 1 - range 1 1 - ---help--- - If TIM16 is enabled for PWM usage, you also need specifies the timer output - channel {1} - -config STM32L5_TIM16_CHMODE - int "TIM16 Channel Mode" - default 0 - range 0 1 - ---help--- - Specifies the channel mode. - -endif # !STM32L5_PWM_MULTICHAN - -endif # STM32L5_TIM16_PWM - -config STM32L5_TIM17_PWM - bool "TIM17 PWM" - default n - depends on STM32L5_TIM17 - select PWM - ---help--- - Reserve timer 17 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32L5_TIM17 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32L5_TIM17_PWM - -if STM32L5_PWM_MULTICHAN - -config STM32L5_TIM17_CHANNEL1 - bool "TIM17 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32L5_TIM17_CHANNEL1 - -config STM32L5_TIM17_CH1MODE - int "TIM17 Channel 1 Mode" - default 0 - range 0 1 - ---help--- - Specifies the channel mode. - -config STM32L5_TIM17_CH1OUT - bool "TIM17 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -config STM32L5_TIM17_CH1NOUT - bool "TIM17 Channel 1 Complementary Output" - default n - depends on STM32L5_TIM17_CH1OUT - ---help--- - Enables channel 1 complementary output. - -endif # STM32L5_TIM17_CHANNEL1 - -endif # STM32L5_PWM_MULTICHAN - -if !STM32L5_PWM_MULTICHAN - -config STM32L5_TIM17_CHANNEL - int "TIM17 PWM Output Channel" - default 1 - range 1 1 - ---help--- - If TIM17 is enabled for PWM usage, you also need specifies the timer output - channel {1} - -config STM32L5_TIM17_CHMODE - int "TIM17 Channel Mode" - default 0 - range 0 1 - ---help--- - Specifies the channel mode. - -endif # !STM32L5_PWM_MULTICHAN - -endif # STM32L5_TIM17_PWM - -config STM32L5_PWM_MULTICHAN - bool "PWM Multiple Output Channels" - default n - depends on STM32L5_TIM1_PWM || STM32L5_TIM2_PWM || STM32L5_TIM3_PWM || STM32L5_TIM4_PWM || STM32L5_TIM5_PWM || STM32L5_TIM8_PWM || STM32L5_TIM15_PWM || STM32L5_TIM16_PWM || STM32L5_TIM17_PWM - ---help--- - Specifies that the PWM driver supports multiple output - channels per timer. - -config STM32L5_TIM1_ADC - bool "TIM1 ADC" - default n - depends on STM32L5_TIM1 && STM32L5_ADC - ---help--- - Reserve timer 1 for use by ADC - - Timer devices may be used for different purposes. If STM32L5_TIM1 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - -choice - prompt "Select TIM1 ADC channel" - default STM32L5_TIM1_ADC1 - depends on STM32L5_TIM1_ADC - -config STM32L5_TIM1_ADC1 - bool "TIM1 ADC channel 1" - depends on STM32L5_ADC1 - select STM32L5_HAVE_ADC1_TIMER - ---help--- - Reserve TIM1 to trigger ADC1 - -config STM32L5_TIM1_ADC2 - bool "TIM1 ADC channel 2" - depends on STM32L5_ADC2 - select STM32L5_HAVE_ADC2_TIMER - ---help--- - Reserve TIM1 to trigger ADC2 - -config STM32L5_TIM1_ADC3 - bool "TIM1 ADC channel 3" - depends on STM32L5_ADC3 - select STM32L5_HAVE_ADC3_TIMER - ---help--- - Reserve TIM1 to trigger ADC3 - -endchoice - -config STM32L5_TIM2_ADC - bool "TIM2 ADC" - default n - depends on STM32L5_TIM2 && STM32L5_ADC - ---help--- - Reserve timer 2 for use by ADC - - Timer devices may be used for different purposes. If STM32L5_TIM2 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - -choice - prompt "Select TIM2 ADC channel" - default STM32L5_TIM2_ADC1 - depends on STM32L5_TIM2_ADC - -config STM32L5_TIM2_ADC1 - bool "TIM2 ADC channel 1" - depends on STM32L5_ADC1 - select STM32L5_HAVE_ADC1_TIMER - ---help--- - Reserve TIM2 to trigger ADC1 - -config STM32L5_TIM2_ADC2 - bool "TIM2 ADC channel 2" - depends on STM32L5_ADC2 - select STM32L5_HAVE_ADC2_TIMER - ---help--- - Reserve TIM2 to trigger ADC2 - -config STM32L5_TIM2_ADC3 - bool "TIM2 ADC channel 3" - depends on STM32L5_ADC3 - select STM32L5_HAVE_ADC3_TIMER - ---help--- - Reserve TIM2 to trigger ADC3 - -endchoice - -config STM32L5_TIM3_ADC - bool "TIM3 ADC" - default n - depends on STM32L5_TIM3 && STM32L5_ADC - ---help--- - Reserve timer 3 for use by ADC - - Timer devices may be used for different purposes. If STM32L5_TIM3 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - -choice - prompt "Select TIM3 ADC channel" - default STM32L5_TIM3_ADC1 - depends on STM32L5_TIM3_ADC - -config STM32L5_TIM3_ADC1 - bool "TIM3 ADC channel 1" - depends on STM32L5_ADC1 - select STM32L5_HAVE_ADC1_TIMER - ---help--- - Reserve TIM3 to trigger ADC1 - -config STM32L5_TIM3_ADC2 - bool "TIM3 ADC channel 2" - depends on STM32L5_ADC2 - select STM32L5_HAVE_ADC2_TIMER - ---help--- - Reserve TIM3 to trigger ADC2 - -config STM32L5_TIM3_ADC3 - bool "TIM3 ADC channel 3" - depends on STM32L5_ADC3 - select STM32L5_HAVE_ADC3_TIMER - ---help--- - Reserve TIM3 to trigger ADC3 - -endchoice - -config STM32L5_TIM4_ADC - bool "TIM4 ADC" - default n - depends on STM32L5_TIM4 && STM32L5_ADC - ---help--- - Reserve timer 4 for use by ADC - - Timer devices may be used for different purposes. If STM32L5_TIM4 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - -choice - prompt "Select TIM4 ADC channel" - default STM32L5_TIM4_ADC1 - depends on STM32L5_TIM4_ADC - -config STM32L5_TIM4_ADC1 - bool "TIM4 ADC channel 1" - depends on STM32L5_ADC1 - select STM32L5_HAVE_ADC1_TIMER - ---help--- - Reserve TIM4 to trigger ADC1 - -config STM32L5_TIM4_ADC2 - bool "TIM4 ADC channel 2" - depends on STM32L5_ADC2 - select STM32L5_HAVE_ADC2_TIMER - ---help--- - Reserve TIM4 to trigger ADC2 - -config STM32L5_TIM4_ADC3 - bool "TIM4 ADC channel 3" - depends on STM32L5_ADC3 - select STM32L5_HAVE_ADC3_TIMER - ---help--- - Reserve TIM4 to trigger ADC3 - -endchoice - -config STM32L5_TIM6_ADC - bool "TIM6 ADC" - default n - depends on STM32L5_TIM6 && STM32L5_ADC - ---help--- - Reserve timer 6 for use by ADC - - Timer devices may be used for different purposes. If STM32L5_TIM6 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - -choice - prompt "Select TIM6 ADC channel" - default STM32L5_TIM6_ADC1 - depends on STM32L5_TIM6_ADC - -config STM32L5_TIM6_ADC1 - bool "TIM6 ADC channel 1" - depends on STM32L5_ADC1 - select STM32L5_HAVE_ADC1_TIMER - ---help--- - Reserve TIM6 to trigger ADC1 - -config STM32L5_TIM6_ADC2 - bool "TIM6 ADC channel 2" - depends on STM32L5_ADC2 - select STM32L5_HAVE_ADC2_TIMER - ---help--- - Reserve TIM6 to trigger ADC2 - -config STM32L5_TIM6_ADC3 - bool "TIM6 ADC channel 3" - depends on STM32L5_ADC3 - select STM32L5_HAVE_ADC3_TIMER - ---help--- - Reserve TIM6 to trigger ADC3 - -endchoice - -config STM32L5_TIM8_ADC - bool "TIM8 ADC" - default n - depends on STM32L5_TIM8 && STM32L5_ADC - ---help--- - Reserve timer 8 for use by ADC - - Timer devices may be used for different purposes. If STM32L5_TIM8 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - -choice - prompt "Select TIM8 ADC channel" - default STM32L5_TIM8_ADC1 - depends on STM32L5_TIM8_ADC - -config STM32L5_TIM8_ADC1 - bool "TIM8 ADC channel 1" - depends on STM32L5_ADC1 - select STM32L5_HAVE_ADC1_TIMER - ---help--- - Reserve TIM8 to trigger ADC1 - -config STM32L5_TIM8_ADC2 - bool "TIM8 ADC channel 2" - depends on STM32L5_ADC2 - select STM32L5_HAVE_ADC2_TIMER - ---help--- - Reserve TIM8 to trigger ADC2 - -config STM32L5_TIM8_ADC3 - bool "TIM8 ADC channel 3" - depends on STM32L5_ADC3 - select STM32L5_HAVE_ADC3_TIMER - ---help--- - Reserve TIM8 to trigger ADC3 - -endchoice - -config STM32L5_TIM15_ADC - bool "TIM15 ADC" - default n - depends on STM32L5_TIM15 && STM32L5_ADC - ---help--- - Reserve timer 15 for use by ADC - - Timer devices may be used for different purposes. If STM32L5_TIM15 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - -choice - prompt "Select TIM15 ADC channel" - default STM32L5_TIM15_ADC1 - depends on STM32L5_TIM15_ADC - -config STM32L5_TIM15_ADC1 - bool "TIM15 ADC channel 1" - depends on STM32L5_ADC1 - select STM32L5_HAVE_ADC1_TIMER - ---help--- - Reserve TIM15 to trigger ADC1 - -config STM32L5_TIM15_ADC2 - bool "TIM15 ADC channel 2" - depends on STM32L5_ADC2 - select STM32L5_HAVE_ADC2_TIMER - ---help--- - Reserve TIM15 to trigger ADC2 - -config STM32L5_TIM15_ADC3 - bool "TIM15 ADC channel 3" - depends on STM32L5_ADC3 - select STM32L5_HAVE_ADC3_TIMER - ---help--- - Reserve TIM15 to trigger ADC3 - -endchoice - -config STM32L5_HAVE_ADC1_TIMER - bool - -config STM32L5_HAVE_ADC2_TIMER - bool - -config STM32L5_HAVE_ADC3_TIMER - bool - -config STM32L5_ADC1_SAMPLE_FREQUENCY - int "ADC1 Sampling Frequency" - default 100 - depends on STM32L5_HAVE_ADC1_TIMER - ---help--- - ADC1 sampling frequency. Default: 100Hz - -config STM32L5_ADC1_TIMTRIG - int "ADC1 Timer Trigger" - default 0 - range 0 4 - depends on STM32L5_HAVE_ADC1_TIMER - ---help--- - Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO - -config STM32L5_ADC2_SAMPLE_FREQUENCY - int "ADC2 Sampling Frequency" - default 100 - depends on STM32L5_HAVE_ADC2_TIMER - ---help--- - ADC2 sampling frequency. Default: 100Hz - -config STM32L5_ADC2_TIMTRIG - int "ADC2 Timer Trigger" - default 0 - range 0 4 - depends on STM32L5_HAVE_ADC2_TIMER - ---help--- - Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO - -config STM32L5_ADC3_SAMPLE_FREQUENCY - int "ADC3 Sampling Frequency" - default 100 - depends on STM32L5_HAVE_ADC3_TIMER - ---help--- - ADC3 sampling frequency. Default: 100Hz - -config STM32L5_ADC3_TIMTRIG - int "ADC3 Timer Trigger" - default 0 - range 0 4 - depends on STM32L5_HAVE_ADC3_TIMER - ---help--- - Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO - -config STM32L5_TIM1_DAC - bool "TIM1 DAC" - default n - depends on STM32L5_TIM1 && STM32L5_DAC - ---help--- - Reserve timer 1 for use by DAC - - Timer devices may be used for different purposes. If STM32L5_TIM1 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -choice - prompt "Select TIM1 DAC channel" - default STM32L5_TIM1_DAC1 - depends on STM32L5_TIM1_DAC - -config STM32L5_TIM1_DAC1 - bool "TIM1 DAC channel 1" - ---help--- - Reserve TIM1 to trigger DAC1 - -config STM32L5_TIM1_DAC2 - bool "TIM1 DAC channel 2" - ---help--- - Reserve TIM1 to trigger DAC2 - -endchoice - -config STM32L5_TIM2_DAC - bool "TIM2 DAC" - default n - depends on STM32L5_TIM2 && STM32L5_DAC - ---help--- - Reserve timer 2 for use by DAC - - Timer devices may be used for different purposes. If STM32L5_TIM2 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -choice - prompt "Select TIM2 DAC channel" - default STM32L5_TIM2_DAC1 - depends on STM32L5_TIM2_DAC - -config STM32L5_TIM2_DAC1 - bool "TIM2 DAC channel 1" - ---help--- - Reserve TIM2 to trigger DAC1 - -config STM32L5_TIM2_DAC2 - bool "TIM2 DAC channel 2" - ---help--- - Reserve TIM2 to trigger DAC2 - -endchoice - -config STM32L5_TIM3_DAC - bool "TIM3 DAC" - default n - depends on STM32L5_TIM3 && STM32L5_DAC - ---help--- - Reserve timer 3 for use by DAC - - Timer devices may be used for different purposes. If STM32L5_TIM3 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -choice - prompt "Select TIM3 DAC channel" - default STM32L5_TIM3_DAC1 - depends on STM32L5_TIM3_DAC - -config STM32L5_TIM3_DAC1 - bool "TIM3 DAC channel 1" - ---help--- - Reserve TIM3 to trigger DAC1 - -config STM32L5_TIM3_DAC2 - bool "TIM3 DAC channel 2" - ---help--- - Reserve TIM3 to trigger DAC2 - -endchoice - -config STM32L5_TIM4_DAC - bool "TIM4 DAC" - default n - depends on STM32L5_TIM4 && STM32L5_DAC - ---help--- - Reserve timer 4 for use by DAC - - Timer devices may be used for different purposes. If STM32L5_TIM4 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -choice - prompt "Select TIM4 DAC channel" - default STM32L5_TIM4_DAC1 - depends on STM32L5_TIM4_DAC - -config STM32L5_TIM4_DAC1 - bool "TIM4 DAC channel 1" - ---help--- - Reserve TIM4 to trigger DAC1 - -config STM32L5_TIM4_DAC2 - bool "TIM4 DAC channel 2" - ---help--- - Reserve TIM4 to trigger DAC2 - -endchoice - -config STM32L5_TIM5_DAC - bool "TIM5 DAC" - default n - depends on STM32L5_TIM5 && STM32L5_DAC - ---help--- - Reserve timer 5 for use by DAC - - Timer devices may be used for different purposes. If STM32L5_TIM5 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -choice - prompt "Select TIM5 DAC channel" - default STM32L5_TIM5_DAC1 - depends on STM32L5_TIM5_DAC - -config STM32L5_TIM5_DAC1 - bool "TIM5 DAC channel 1" - ---help--- - Reserve TIM5 to trigger DAC1 - -config STM32L5_TIM5_DAC2 - bool "TIM5 DAC channel 2" - ---help--- - Reserve TIM5 to trigger DAC2 - -endchoice - -config STM32L5_TIM6_DAC - bool "TIM6 DAC" - default n - depends on STM32L5_TIM6 && STM32L5_DAC - ---help--- - Reserve timer 6 for use by DAC - - Timer devices may be used for different purposes. If STM32L5_TIM6 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -choice - prompt "Select TIM6 DAC channel" - default STM32L5_TIM6_DAC1 - depends on STM32L5_TIM6_DAC - -config STM32L5_TIM6_DAC1 - bool "TIM6 DAC channel 1" - ---help--- - Reserve TIM6 to trigger DAC1 - -config STM32L5_TIM6_DAC2 - bool "TIM6 DAC channel 2" - ---help--- - Reserve TIM6 to trigger DAC2 - -endchoice - -config STM32L5_TIM7_DAC - bool "TIM7 DAC" - default n - depends on STM32L5_TIM7 && STM32L5_DAC - ---help--- - Reserve timer 7 for use by DAC - - Timer devices may be used for different purposes. If STM32L5_TIM7 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -choice - prompt "Select TIM7 DAC channel" - default STM32L5_TIM7_DAC1 - depends on STM32L5_TIM7_DAC - -config STM32L5_TIM7_DAC1 - bool "TIM7 DAC channel 1" - ---help--- - Reserve TIM7 to trigger DAC1 - -config STM32L5_TIM7_DAC2 - bool "TIM7 DAC channel 2" - ---help--- - Reserve TIM7 to trigger DAC2 - -endchoice - -config STM32L5_TIM8_DAC - bool "TIM8 DAC" - default n - depends on STM32L5_TIM8 && STM32L5_DAC - ---help--- - Reserve timer 8 for use by DAC - - Timer devices may be used for different purposes. If STM32L5_TIM8 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -choice - prompt "Select TIM8 DAC channel" - default STM32L5_TIM8_DAC1 - depends on STM32L5_TIM8_DAC - -config STM32L5_TIM8_DAC1 - bool "TIM8 DAC channel 1" - ---help--- - Reserve TIM8 to trigger DAC1 - -config STM32L5_TIM8_DAC2 - bool "TIM8 DAC channel 2" - ---help--- - Reserve TIM8 to trigger DAC2 - -endchoice - -config STM32L5_TIM1_CAP - bool "TIM1 Capture" - default n - depends on STM32L5_HAVE_TIM1 - ---help--- - Reserve timer 1 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -config STM32L5_TIM2_CAP - bool "TIM2 Capture" - default n - depends on STM32L5_HAVE_TIM2 - ---help--- - Reserve timer 2 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -config STM32L5_TIM3_CAP - bool "TIM3 Capture" - default n - depends on STM32L5_HAVE_TIM3 - ---help--- - Reserve timer 3 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -config STM32L5_TIM4_CAP - bool "TIM4 Capture" - default n - depends on STM32L5_HAVE_TIM4 - ---help--- - Reserve timer 4 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -config STM32L5_TIM5_CAP - bool "TIM5 Capture" - default n - depends on STM32L5_HAVE_TIM5 - ---help--- - Reserve timer 5 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -config STM32L5_TIM8_CAP - bool "TIM8 Capture" - default n - depends on STM32L5_HAVE_TIM8 - ---help--- - Reserve timer 8 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -endmenu # Timer Configuration - -menu "ADC Configuration" - depends on STM32L5_ADC - -config STM32L5_ADC1_DMA - bool "ADC1 DMA" - depends on STM32L5_ADC1 - default n - ---help--- - If DMA is selected, then the ADC may be configured to support - DMA transfer, which is necessary if multiple channels are read - or if very high trigger frequencies are used. - -config STM32L5_ADC2_DMA - bool "ADC2 DMA" - depends on STM32L5_ADC2 - default n - ---help--- - If DMA is selected, then the ADC may be configured to support - DMA transfer, which is necessary if multiple channels are read - or if very high trigger frequencies are used. - -config STM32L5_ADC3_DMA - bool "ADC3 DMA" - depends on STM32L5_ADC3 - default n - ---help--- - If DMA is selected, then the ADC may be configured to support - DMA transfer, which is necessary if multiple channels are read - or if very high trigger frequencies are used. - -config STM32L5_ADC1_OUTPUT_DFSDM - bool "ADC1 output to DFSDM" - depends on STM32L5_ADC1 && STM32L5_DFSDM1 && (STM32L5_STM32L596XX || STM32L5_STM32L5XR) - default n - ---help--- - Route ADC1 output directly to DFSDM parallel inputs. - -config STM32L5_ADC2_OUTPUT_DFSDM - bool "ADC2 output to DFSDM" - depends on STM32L5_ADC2 && STM32L5_DFSDM1 && STM32L5_STM32L596XX - default n - ---help--- - Route ADC2 output directly to DFSDM parallel inputs. - -config STM32L5_ADC3_OUTPUT_DFSDM - bool "ADC3 output to DFSDM" - depends on STM32L5_ADC3 && STM32L5_DFSDM1 && STM32L5_STM32L596XX - default n - ---help--- - Route ADC3 output directly to DFSDM parallel inputs. - -endmenu - -menu "DAC Configuration" - depends on STM32L5_DAC - -config STM32L5_DAC1_DMA - bool "DAC1 DMA" - depends on STM32L5_DAC1 - default n - ---help--- - If DMA is selected, then a timer and output frequency must also be - provided to support the DMA transfer. The DMA transfer could be - supported by an EXTI trigger, but this feature is not currently - supported by the driver. - -if STM32L5_DAC1_DMA - -config STM32L5_DAC1_TIMER - int "DAC1 timer" - range 2 8 - -config STM32L5_DAC1_TIMER_FREQUENCY - int "DAC1 timer frequency" - default 100 - ---help--- - DAC1 output frequency. Default: 100Hz - -config STM32L5_DAC1_DMA_BUFFER_SIZE - int "DAC1 DMA buffer size" - default 1 - -endif - -config STM32L5_DAC1_OUTPUT_ADC - bool "DAC1 output to ADC" - depends on STM32L5_DAC1 - default n - ---help--- - Route DAC1 output to ADC input instead of external pin. - -config STM32L5_DAC2_DMA - bool "DAC2 DMA" - depends on STM32L5_DAC2 - default n - ---help--- - If DMA is selected, then a timer and output frequency must also be - provided to support the DMA transfer. The DMA transfer could be - supported by an EXTI trigger, but this feature is not currently - supported by the driver. - -if STM32L5_DAC2_DMA - -config STM32L5_DAC2_TIMER - int "DAC2 timer" - default 0 - range 2 8 - -config STM32L5_DAC2_TIMER_FREQUENCY - int "DAC2 timer frequency" - default 100 - ---help--- - DAC2 output frequency. Default: 100Hz - -config STM32L5_DAC2_DMA_BUFFER_SIZE - int "DAC2 DMA buffer size" - default 1 - -endif - -config STM32L5_DAC2_OUTPUT_ADC - bool "DAC2 output to ADC" - depends on STM32L5_DAC2 - default n - ---help--- - Route DAC2 output to ADC input instead of external pin. - -endmenu - -menu "DFSDM Configuration" - depends on STM32L5_DFSDM1 - -config STM32L5_DFSDM1_FLT0 - bool "DFSDM1 Filter 0" - default n - select STM32L5_DFSDM - -config STM32L5_DFSDM1_FLT1 - bool "DFSDM1 Filter 1" - default n - select STM32L5_DFSDM - -config STM32L5_DFSDM1_FLT2 - bool "DFSDM1 Filter 2" - default n - depends on !STM32L5_STM32L5X3 - select STM32L5_DFSDM - -config STM32L5_DFSDM1_FLT3 - bool "DFSDM1 Filter 3" - default n - depends on !STM32L5_STM32L5X3 - select STM32L5_DFSDM - -config STM32L5_DFSDM1_DMA - bool "DFSDM1 DMA" - depends on STM32L5_DFSDM - default n - ---help--- - If DMA is selected, then the DFSDM may be configured to support - DMA transfer, which is necessary if multiple channels are read - or if very high trigger frequencies are used. - -endmenu - -config STM32L5_SERIALDRIVER - bool - -config STM32L5_1WIREDRIVER - bool - -menu "[LP]U[S]ART Configuration" - depends on STM32L5_USART - -choice - prompt "LPUART1 Driver Configuration" - default STM32L5_LPUART1_SERIALDRIVER - depends on STM32L5_LPUART1 - -config STM32L5_LPUART1_SERIALDRIVER - bool "Standard serial driver" - select LPUART1_SERIALDRIVER - select STM32L5_SERIALDRIVER - -config STM32L5_LPUART1_1WIREDRIVER - bool "1-Wire driver" - select STM32L5_1WIREDRIVER - -endchoice # LPUART1 Driver Configuration - -if LPUART1_SERIALDRIVER - -config LPUART1_RS485 - bool "RS-485 on LPUART1" - default n - depends on STM32L5_LPUART1 - ---help--- - Enable RS-485 interface on LPUART1. Your board config will have to - provide GPIO_LPUART1_RS485_DIR pin definition. Currently it cannot be - used with LPUART1_RXDMA. - -config LPUART1_RS485_DIR_POLARITY - int "LPUART1 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on LPUART1_RS485 - ---help--- - Polarity of DIR pin for RS-485 on LPUART1. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config LPUART1_RXDMA - bool "LPUART1 Rx DMA" - default n - depends on STM32L5_LPUART1 && (STM32L5_DMA1 || STM32L5_DMA2 || STM32L5_DMAMUX) - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -endif # LPUART1_SERIALDRIVER - -choice - prompt "USART1 Driver Configuration" - default STM32L5_USART1_SERIALDRIVER - depends on STM32L5_USART1 - -config STM32L5_USART1_SERIALDRIVER - bool "Standard serial driver" - select USART1_SERIALDRIVER - select STM32L5_SERIALDRIVER - -config STM32L5_USART1_1WIREDRIVER - bool "1-Wire driver" - select STM32L5_1WIREDRIVER - -endchoice # USART1 Driver Configuration - -if USART1_SERIALDRIVER - -config USART1_RS485 - bool "RS-485 on USART1" - default n - depends on STM32L5_USART1 - ---help--- - Enable RS-485 interface on USART1. Your board config will have to - provide GPIO_USART1_RS485_DIR pin definition. Currently it cannot be - used with USART1_RXDMA. - -config USART1_RS485_DIR_POLARITY - int "USART1 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on USART1_RS485 - ---help--- - Polarity of DIR pin for RS-485 on USART1. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config USART1_RXDMA - bool "USART1 Rx DMA" - default n - depends on STM32L5_USART1 && (STM32L5_DMA1 || STM32L5_DMA2 || STM32L5_DMAMUX) - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -endif # USART1_SERIALDRIVER - -choice - prompt "USART2 Driver Configuration" - default STM32L5_USART2_SERIALDRIVER - depends on STM32L5_USART2 - -config STM32L5_USART2_SERIALDRIVER - bool "Standard serial driver" - select USART2_SERIALDRIVER - select STM32L5_SERIALDRIVER - -config STM32L5_USART2_1WIREDRIVER - bool "1-Wire driver" - select STM32L5_1WIREDRIVER - -endchoice # USART2 Driver Configuration - -if USART2_SERIALDRIVER - -config USART2_RS485 - bool "RS-485 on USART2" - default n - depends on STM32L5_USART2 - ---help--- - Enable RS-485 interface on USART2. Your board config will have to - provide GPIO_USART2_RS485_DIR pin definition. Currently it cannot be - used with USART2_RXDMA. - -config USART2_RS485_DIR_POLARITY - int "USART2 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on USART2_RS485 - ---help--- - Polarity of DIR pin for RS-485 on USART2. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config USART2_RXDMA - bool "USART2 Rx DMA" - default n - depends on STM32L5_USART2 && (STM32L5_DMA1 || STM32L5_DMAMUX) - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -endif # USART2_SERIALDRIVER - -choice - prompt "USART3 Driver Configuration" - default STM32L5_USART3_SERIALDRIVER - depends on STM32L5_USART3 - -config STM32L5_USART3_SERIALDRIVER - bool "Standard serial driver" - select USART3_SERIALDRIVER - select STM32L5_SERIALDRIVER - -config STM32L5_USART3_1WIREDRIVER - bool "1-Wire driver" - select STM32L5_1WIREDRIVER - -endchoice # USART3 Driver Configuration - -if USART3_SERIALDRIVER - -config USART3_RS485 - bool "RS-485 on USART3" - default n - depends on STM32L5_USART3 - ---help--- - Enable RS-485 interface on USART3. Your board config will have to - provide GPIO_USART3_RS485_DIR pin definition. Currently it cannot be - used with USART3_RXDMA. - -config USART3_RS485_DIR_POLARITY - int "USART3 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on USART3_RS485 - ---help--- - Polarity of DIR pin for RS-485 on USART3. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config USART3_RXDMA - bool "USART3 Rx DMA" - default n - depends on STM32L5_USART3 && (STM32L5_DMA1 || STM32L5_DMAMUX) - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -endif # USART3_SERIALDRIVER - -choice - prompt "UART4 Driver Configuration" - default STM32L5_UART4_SERIALDRIVER - depends on STM32L5_UART4 - -config STM32L5_UART4_SERIALDRIVER - bool "Standard serial driver" - select UART4_SERIALDRIVER - select STM32L5_SERIALDRIVER - -config STM32L5_UART4_1WIREDRIVER - bool "1-Wire driver" - select STM32L5_1WIREDRIVER - -endchoice # UART4 Driver Configuration - -if UART4_SERIALDRIVER - -config UART4_RS485 - bool "RS-485 on UART4" - default n - depends on STM32L5_UART4 - ---help--- - Enable RS-485 interface on UART4. Your board config will have to - provide GPIO_UART4_RS485_DIR pin definition. Currently it cannot be - used with UART4_RXDMA. - -config UART4_RS485_DIR_POLARITY - int "UART4 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on UART4_RS485 - ---help--- - Polarity of DIR pin for RS-485 on UART4. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config UART4_RXDMA - bool "UART4 Rx DMA" - default n - depends on STM32L5_UART4 && (STM32L5_DMA2 || STM32L5_DMAMUX) - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -endif # UART4_SERIALDRIVER - -choice - prompt "UART5 Driver Configuration" - default STM32L5_UART5_SERIALDRIVER - depends on STM32L5_UART5 - -config STM32L5_UART5_SERIALDRIVER - bool "Standard serial driver" - select UART5_SERIALDRIVER - select STM32L5_SERIALDRIVER - -config STM32L5_UART5_1WIREDRIVER - bool "1-Wire driver" - select STM32L5_1WIREDRIVER - -endchoice # UART5 Driver Configuration - -if UART5_SERIALDRIVER - -config UART5_RS485 - bool "RS-485 on UART5" - default n - depends on STM32L5_UART5 - ---help--- - Enable RS-485 interface on UART5. Your board config will have to - provide GPIO_UART5_RS485_DIR pin definition. Currently it cannot be - used with UART5_RXDMA. - -config UART5_RS485_DIR_POLARITY - int "UART5 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on UART5_RS485 - ---help--- - Polarity of DIR pin for RS-485 on UART5. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config UART5_RXDMA - bool "UART5 Rx DMA" - default n - depends on STM32L5_UART5 && (STM32L5_DMA2 || STM32L5_DMAMUX) - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -endif # UART5_SERIALDRIVER - -if STM32L5_SERIALDRIVER - -comment "Serial Driver Configuration" - -config STM32L5_SERIAL_RXDMA_BUFFER_SIZE - int "Rx DMA buffer size" - default 32 - depends on USART1_RXDMA || USART2_RXDMA || USART3_RXDMA || UART4_RXDMA || UART5_RXDMA - ---help--- - The DMA buffer size when using RX DMA to emulate a FIFO. - - When streaming data, the generic serial layer will be called - every time the FIFO receives half this number of bytes. - - Value given here will be rounded up to next multiple of 32 bytes. - -config STM32L5_SERIAL_DISABLE_REORDERING - bool "Disable reordering of ttySx devices." - depends on STM32L5_USART1 || STM32L5_USART2 || STM32L5_USART3 || STM32L5_UART4 || STM32L5_UART5 - default n - ---help--- - NuttX per default reorders the serial ports (/dev/ttySx) so that the - console is always on /dev/ttyS0. If more than one UART is in use this - can, however, have the side-effect that all port mappings - (hardware USART1 -> /dev/ttyS0) change if the console is moved to another - UART. This is in particular relevant if a project uses the USB console - in some boards and a serial console in other boards, but does not - want the side effect of having all serial port names change when just - the console is moved from serial to USB. - -config STM32L5_FLOWCONTROL_BROKEN - bool "Use Software UART RTS flow control" - depends on STM32L5_USART - default n - ---help--- - Enable UART RTS flow control using Software. Because STM - Current STM32 have broken HW based RTS behavior (they assert - nRTS after every byte received) Enable this setting workaround - this issue by using software based management of RTS - -config STM32L5_USART_BREAKS - bool "Add TIOxSBRK to support sending Breaks" - depends on STM32L5_USART - default n - ---help--- - Add TIOCxBRK routines to send a line break per the STM32 manual, the - break will be a pulse based on the value M. This is not a BSD compatible - break. - -config STM32L5_SERIALBRK_BSDCOMPAT - bool "Use GPIO To send Break" - depends on STM32L5_USART && STM32L5_USART_BREAKS - default n - ---help--- - Enable using GPIO on the TX pin to send a BSD compatible break: - TIOCSBRK will start the break and TIOCCBRK will end the break. - The current STM32L5 U[S]ARTS have no way to leave the break on - (TX=LOW) because software starts the break and then the hardware - automatically clears the break. This makes it difficult to send - a long break. - -config STM32L5_USART_SINGLEWIRE - bool "Single Wire Support" - default n - depends on STM32L5_USART - ---help--- - Enable single wire UART support. The option enables support for the - TIOCSSINGLEWIRE ioctl in the STM32L5 serial driver. - -config STM32L5_USART_INVERT - bool "Signal Invert Support" - default n - depends on STM32L5_USART - ---help--- - Enable signal inversion UART support. The option enables support for the - TIOCSINVERT ioctl in the STM32L5 serial driver. - -config STM32L5_USART_SWAP - bool "Swap RX/TX pins support" - default n - depends on STM32L5_USART - ---help--- - Enable RX/TX pin swapping support. The option enables support for the - TIOCSSWAP ioctl in the STM32L5 serial driver. - -if PM - -config STM32L5_PM_SERIAL_ACTIVITY - int "PM serial activity" - default 10 - ---help--- - PM activity reported to power management logic on every serial - interrupt. - -endif -endif # STM32L5_SERIALDRIVER - -endmenu # U[S]ART Configuration - -menu "SPI Configuration" - depends on STM32L5_SPI - -config STM32L5_SPI_INTERRUPTS - bool "Interrupt driver SPI" - default n - ---help--- - Select to enable interrupt driven SPI support. Non-interrupt-driven, - poll-waiting is recommended if the interrupt rate would be to high in - the interrupt driven case. - -config STM32L5_SPI_DMA - bool "SPI DMA" - default n - ---help--- - Use DMA to improve SPI transfer performance. Cannot be used with STM32L5_SPI_INTERRUPT. - -endmenu - -menu "I2C Configuration" - depends on STM32L5_I2C - -config STM32L5_I2C_DYNTIMEO - bool "Use dynamic timeouts" - default n - depends on STM32L5_I2C - -config STM32L5_I2C_DYNTIMEO_USECPERBYTE - int "Timeout Microseconds per Byte" - default 500 - depends on STM32L5_I2C_DYNTIMEO - -config STM32L5_I2C_DYNTIMEO_STARTSTOP - int "Timeout for Start/Stop (Milliseconds)" - default 1000 - depends on STM32L5_I2C_DYNTIMEO - -config STM32L5_I2CTIMEOSEC - int "Timeout seconds" - default 0 - depends on STM32L5_I2C - -config STM32L5_I2CTIMEOMS - int "Timeout Milliseconds" - default 500 - depends on STM32L5_I2C && !STM32L5_I2C_DYNTIMEO - -config STM32L5_I2CTIMEOTICKS - int "Timeout for Done and Stop (ticks)" - default 500 - depends on STM32L5_I2C && !STM32L5_I2C_DYNTIMEO - -endmenu - -menu "SD/MMC Configuration" - depends on STM32L5_SDMMC - -config STM32L5_SDMMC_XFRDEBUG - bool "SDMMC transfer debug" - depends on DEBUG_FS_INFO - default n - ---help--- - Enable special debug instrumentation analyze SDMMC data transfers. - This logic is as non-invasive as possible: It samples SDMMC - registers at key points in the data transfer and then dumps all of - the registers at the end of the transfer. If DEBUG_DMA is also - enabled, then DMA register will be collected as well. Requires also - DEBUG_FS and CONFIG_DEBUG_INFO. - -config STM32L5_SDMMC_DMA - bool "Support DMA data transfers" - default n - select SDIO_DMA - depends on STM32L5_DMA - ---help--- - Support DMA data transfers. - -menu "SDMMC1 Configuration" - depends on STM32L5_SDMMC1 - -config STM32L5_SDMMC1_DMAPRIO - hex "SDMMC1 DMA priority" - default 0x00001000 - ---help--- - Select SDMMC1 DMA priority. - - Options are: 0x00000000 low, 0x00001000 medium, - 0x00002000 high, 0x00003000 very high. Default: medium. - -config SDMMC1_WIDTH_D1_ONLY - bool "Use D1 only on SDMMC1" - default n - ---help--- - Select 1-bit transfer mode. Default: 4-bit transfer mode. - -endmenu # SDMMC1 Configuration -endmenu # SD/MMC Configuration - -menu "CAN driver configuration" - depends on STM32L5_CAN1 || STM32L5_CAN2 - -config STM32L5_CAN1_BAUD - int "CAN1 BAUD" - default 250000 - depends on STM32L5_CAN1 - ---help--- - CAN1 BAUD rate. Required if CONFIG_STM32L5_CAN1 is defined. - -config STM32L5_CAN2_BAUD - int "CAN2 BAUD" - default 250000 - depends on STM32L5_CAN2 - ---help--- - CAN2 BAUD rate. Required if CONFIG_STM32L5_CAN2 is defined. - -config STM32L5_CAN_TSEG1 - int "TSEG1 quanta" - default 6 - ---help--- - The number of CAN time quanta in segment 1. Default: 6 - -config STM32L5_CAN_TSEG2 - int "TSEG2 quanta" - default 7 - ---help--- - The number of CAN time quanta in segment 2. Default: 7 - -config STM32L5_CAN_REGDEBUG - bool "CAN Register level debug" - depends on DEBUG_CAN_INFO - default n - ---help--- - Output detailed register-level CAN device debug information. - Requires also CONFIG_DEBUG_CAN_INFO. - -endmenu - -menu "QEncoder Driver" - depends on SENSORS_QENCODER - depends on STM32L5_TIM1 || STM32L5_TIM2 || STM32L5_TIM3 || STM32L5_TIM4 || STM32L5_TIM5 || STM32L5_TIM8 - -config STM32L5_TIM1_QE - bool "TIM1" - default n - depends on STM32L5_TIM1 - ---help--- - Reserve TIM1 for use by QEncoder. - -if STM32L5_TIM1_QE - -config STM32L5_TIM1_QEPSC - int "TIM1 pulse prescaler" - default 1 - ---help--- - This prescaler divides the number of recorded encoder pulses, limiting the count rate at the expense of resolution. - -endif - -config STM32L5_TIM2_QE - bool "TIM2" - default n - depends on STM32L5_TIM2 - ---help--- - Reserve TIM2 for use by QEncoder. - -if STM32L5_TIM2_QE - -config STM32L5_TIM2_QEPSC - int "TIM2 pulse prescaler" - default 1 - ---help--- - This prescaler divides the number of recorded encoder pulses, limiting the count rate at the expense of resolution. - -endif - -config STM32L5_TIM3_QE - bool "TIM3" - default n - depends on STM32L5_TIM3 - ---help--- - Reserve TIM3 for use by QEncoder. - -if STM32L5_TIM3_QE - -config STM32L5_TIM3_QEPSC - int "TIM3 pulse prescaler" - default 1 - ---help--- - This prescaler divides the number of recorded encoder pulses, limiting the count rate at the expense of resolution. - -endif - -config STM32L5_TIM4_QE - bool "TIM4" - default n - depends on STM32L5_TIM4 - ---help--- - Reserve TIM4 for use by QEncoder. - -if STM32L5_TIM4_QE - -config STM32L5_TIM4_QEPSC - int "TIM4 pulse prescaler" - default 1 - ---help--- - This prescaler divides the number of recorded encoder pulses, limiting the count rate at the expense of resolution. - -endif - -config STM32L5_TIM5_QE - bool "TIM5" - default n - depends on STM32L5_TIM5 - ---help--- - Reserve TIM5 for use by QEncoder. - -if STM32L5_TIM5_QE - -config STM32L5_TIM5_QEPSC - int "TIM5 pulse prescaler" - default 1 - ---help--- - This prescaler divides the number of recorded encoder pulses, limiting the count rate at the expense of resolution. - -endif - -config STM32L5_TIM8_QE - bool "TIM8" - default n - depends on STM32L5_TIM8 - ---help--- - Reserve TIM8 for use by QEncoder. - -if STM32L5_TIM8_QE - -config STM32L5_TIM8_QEPSC - int "TIM8 pulse prescaler" - default 1 - ---help--- - This prescaler divides the number of recorded encoder pulses, limiting the count rate at the expense of resolution. - -endif - -config STM32L5_QENCODER_FILTER - bool "Enable filtering on STM32 QEncoder input" - default y - -choice - depends on STM32L5_QENCODER_FILTER - prompt "Input channel sampling frequency" - default STM32L5_QENCODER_SAMPLE_FDTS_4 - -config STM32L5_QENCODER_SAMPLE_FDTS - bool "fDTS" - -config STM32L5_QENCODER_SAMPLE_CKINT - bool "fCK_INT" - -config STM32L5_QENCODER_SAMPLE_FDTS_2 - bool "fDTS/2" - -config STM32L5_QENCODER_SAMPLE_FDTS_4 - bool "fDTS/4" - -config STM32L5_QENCODER_SAMPLE_FDTS_8 - bool "fDTS/8" - -config STM32L5_QENCODER_SAMPLE_FDTS_16 - bool "fDTS/16" - -config STM32L5_QENCODER_SAMPLE_FDTS_32 - bool "fDTS/32" - -endchoice - -choice - depends on STM32L5_QENCODER_FILTER - prompt "Input channel event count" - default STM32L5_QENCODER_SAMPLE_EVENT_6 - -config STM32L5_QENCODER_SAMPLE_EVENT_1 - depends on STM32L5_QENCODER_SAMPLE_FDTS - bool "1" - -config STM32L5_QENCODER_SAMPLE_EVENT_2 - depends on STM32L5_QENCODER_SAMPLE_CKINT - bool "2" - -config STM32L5_QENCODER_SAMPLE_EVENT_4 - depends on STM32L5_QENCODER_SAMPLE_CKINT - bool "4" - -config STM32L5_QENCODER_SAMPLE_EVENT_5 - depends on STM32L5_QENCODER_SAMPLE_FDTS_16 || STM32L5_QENCODER_SAMPLE_FDTS_32 - bool "5" - -config STM32L5_QENCODER_SAMPLE_EVENT_6 - depends on !STM32L5_QENCODER_SAMPLE_FDTS && !STM32L5_QENCODER_SAMPLE_CKINT - bool "6" - -config STM32L5_QENCODER_SAMPLE_EVENT_8 - depends on !STM32L5_QENCODER_SAMPLE_FDTS - bool "8" - -endchoice - -endmenu - -menu "SAI Configuration" - depends on STM32L5_SAI - -choice - prompt "Operation mode" - default STM32L5_SAI_DMA - ---help--- - Select the operation mode the SAI driver should use. - -config STM32L5_SAI_POLLING - bool "Polling" - ---help--- - The SAI registers are polled for events. - -config STM32L5_SAI_INTERRUPTS - bool "Interrupt" - ---help--- - Select to enable interrupt driven SAI support. - -config STM32L5_SAI_DMA - bool "DMA" - ---help--- - Use DMA to improve SAI transfer performance. - -endchoice # Operation mode - -choice - prompt "SAI1 synchronization enable" - default STM32L5_SAI1_BOTH_ASYNC - depends on STM32L5_SAI1_A && STM32L5_SAI1_B - ---help--- - Select the synchronization mode of the SAI sub-blocks - -config STM32L5_SAI1_BOTH_ASYNC - bool "Both asynchronous" - -config STM32L5_SAI1_A_SYNC_WITH_B - bool "Block A is synchronous with Block B" - -config STM32L5_SAI1_B_SYNC_WITH_A - bool "Block B is synchronous with Block A" - -endchoice # SAI1 synchronization enable - -choice - prompt "SAI2 synchronization enable" - default STM32L5_SAI2_BOTH_ASYNC - depends on STM32L5_SAI2_A && STM32L5_SAI2_B - ---help--- - Select the synchronization mode of the SAI sub-blocks - -config STM32L5_SAI2_BOTH_ASYNC - bool "Both asynchronous" - -config STM32L5_SAI2_A_SYNC_WITH_B - bool "Block A is synchronous with Block B" - -config STM32L5_SAI2_B_SYNC_WITH_A - bool "Block B is synchronous with Block A" - -endchoice # SAI2 synchronization enable - -endmenu - endif # ARCH_CHIP_STM32L5 diff --git a/arch/arm/src/stm32l5/Make.defs b/arch/arm/src/stm32l5/Make.defs index e9f17420e4ccf..b01e736c4c8f7 100644 --- a/arch/arm/src/stm32l5/Make.defs +++ b/arch/arm/src/stm32l5/Make.defs @@ -28,13 +28,14 @@ HEAD_ASRC = # Common ARM and Cortex-M4 files (copied from stm32/Make.defs) include armv8-m/Make.defs +include common/stm32/Make.defs # Required STM32L5 files CHIP_ASRCS = -CHIP_CSRCS = stm32l5_allocateheap.c stm32l5_exti_gpio.c stm32l5_gpio.c +CHIP_CSRCS += stm32l5_allocateheap.c stm32l5_exti_gpio.c stm32l5_gpio.c CHIP_CSRCS += stm32l5_irq.c stm32l5_lowputc.c stm32l5_rcc.c -CHIP_CSRCS += stm32l5_serial.c stm32l5_start.c stm32l5_waste.c stm32l5_uid.c +CHIP_CSRCS += stm32l5_serial.c stm32l5_start.c CHIP_CSRCS += stm32l5_spi.c stm32l5_lse.c stm32l5_lsi.c CHIP_CSRCS += stm32l5_pwr.c stm32l5_tim.c stm32l5_flash.c stm32l5_timerisr.c @@ -56,6 +57,6 @@ endif # Required chip type specific files -ifeq ($(CONFIG_STM32L5_STM32L562XX),y) +ifeq ($(CONFIG_STM32_STM32L562XX),y) CHIP_CSRCS += stm32l562xx_rcc.c endif diff --git a/arch/arm/src/stm32l5/chip.h b/arch/arm/src/stm32l5/chip.h index a8a0ea513909d..33c22b102cab3 100644 --- a/arch/arm/src/stm32l5/chip.h +++ b/arch/arm/src/stm32l5/chip.h @@ -48,6 +48,6 @@ * arch/stm32l5/chip.h header file. */ -#define ARMV8M_PERIPHERAL_INTERRUPTS STM32L5_IRQ_NEXTINTS +#define ARMV8M_PERIPHERAL_INTERRUPTS STM32_IRQ_NEXTINTS #endif /* __ARCH_ARM_SRC_STM32L5_CHIP_H */ diff --git a/arch/arm/src/stm32l5/hardware/stm32l562xx_rcc.h b/arch/arm/src/stm32l5/hardware/stm32l562xx_rcc.h index 9f1f886562999..64d4f7215e239 100644 --- a/arch/arm/src/stm32l5/hardware/stm32l562xx_rcc.h +++ b/arch/arm/src/stm32l5/hardware/stm32l562xx_rcc.h @@ -29,7 +29,7 @@ #include -#if defined(CONFIG_STM32L5_STM32L562XX) +#if defined(CONFIG_STM32_STM32L562XX) /**************************************************************************** * Pre-processor Definitions @@ -37,89 +37,89 @@ /* Register Offsets *********************************************************/ -#define STM32L5_RCC_CR_OFFSET 0x0000 /* Clock control register */ -#define STM32L5_RCC_ICSCR_OFFSET 0x0004 /* Internal clock sources calibration register */ -#define STM32L5_RCC_CFGR_OFFSET 0x0008 /* Clock configuration register */ -#define STM32L5_RCC_PLLCFG_OFFSET 0x000c /* PLL configuration register */ -#define STM32L5_RCC_PLLSAI1CFG_OFFSET 0x0010 /* PLLSAI1 configuration register */ -#define STM32L5_RCC_PLLSAI2CFG_OFFSET 0x0014 /* PLLSAI2 configuration register */ -#define STM32L5_RCC_CIER_OFFSET 0x0018 /* Clock interrupt enable register */ -#define STM32L5_RCC_CIFR_OFFSET 0x001c /* Clock interrupt flag register */ -#define STM32L5_RCC_CICR_OFFSET 0x0020 /* Clock interrupt clear register */ -#define STM32L5_RCC_AHB1RSTR_OFFSET 0x0028 /* AHB1 peripheral reset register */ -#define STM32L5_RCC_AHB2RSTR_OFFSET 0x002c /* AHB2 peripheral reset register */ -#define STM32L5_RCC_AHB3RSTR_OFFSET 0x0030 /* AHB3 peripheral reset register */ -#define STM32L5_RCC_APB1RSTR1_OFFSET 0x0038 /* APB1 Peripheral reset register 1 */ -#define STM32L5_RCC_APB1RSTR2_OFFSET 0x003c /* APB1 Peripheral reset register 2 */ -#define STM32L5_RCC_APB2RSTR_OFFSET 0x0040 /* APB2 Peripheral reset register */ -#define STM32L5_RCC_AHB1ENR_OFFSET 0x0048 /* AHB1 Peripheral Clock enable register */ -#define STM32L5_RCC_AHB2ENR_OFFSET 0x004c /* AHB2 Peripheral Clock enable register */ -#define STM32L5_RCC_AHB3ENR_OFFSET 0x0050 /* AHB3 Peripheral Clock enable register */ -#define STM32L5_RCC_APB1ENR1_OFFSET 0x0058 /* APB1 Peripheral Clock enable register 1 */ -#define STM32L5_RCC_APB1ENR2_OFFSET 0x005c /* APB1 Peripheral Clock enable register 2 */ -#define STM32L5_RCC_APB2ENR_OFFSET 0x0060 /* APB2 Peripheral Clock enable register */ -#define STM32L5_RCC_AHB1SMENR_OFFSET 0x0068 /* RCC AHB1 low power mode peripheral clock enable register */ -#define STM32L5_RCC_AHB2SMENR_OFFSET 0x006c /* RCC AHB2 low power mode peripheral clock enable register */ -#define STM32L5_RCC_AHB3SMENR_OFFSET 0x0070 /* RCC AHB3 low power mode peripheral clock enable register */ -#define STM32L5_RCC_APB1SMENR1_OFFSET 0x0078 /* RCC APB1 low power mode peripheral clock enable register 1 */ -#define STM32L5_RCC_APB1SMENR2_OFFSET 0x007c /* RCC APB1 low power mode peripheral clock enable register 2 */ -#define STM32L5_RCC_APB2SMENR_OFFSET 0x0080 /* RCC APB2 low power mode peripheral clock enable register */ -#define STM32L5_RCC_CCIPR_OFFSET 0x0088 /* Peripherals independent clock configuration register 1 */ -#define STM32L5_RCC_BDCR_OFFSET 0x0090 /* Backup domain control register */ -#define STM32L5_RCC_CSR_OFFSET 0x0094 /* Control/status register */ -#define STM32L5_RCC_CRRCR_OFFSET 0x0098 /* Clock recovery RC register */ -#define STM32L5_RCC_CCIPR2_OFFSET 0x009c /* Peripherals independent clock configuration register 2 */ -#define STM32L5_RCC_SECCFGR_OFFSET 0x00b8 /* Secure configuration register */ -#define STM32L5_RCC_SECSR_OFFSET 0x00bc /* Secure status register */ -#define STM32L5_RCC_AHB1SECSR_OFFSET 0x00e8 /* AHB1 security status register */ -#define STM32L5_RCC_AHB2SECSR_OFFSET 0x00ec /* AHB2 security status register */ -#define STM32L5_RCC_AHB3SECSR_OFFSET 0x00f0 /* AHB3 security status register */ -#define STM32L5_RCC_APB1SECSR1_OFFSET 0x00f8 /* APB1 security status register 1 */ -#define STM32L5_RCC_APB1SECSR2_OFFSET 0x00fc /* APB1 security status register 2 */ -#define STM32L5_RCC_APB2SECSR_OFFSET 0x0100 /* APB2 security status register */ +#define STM32_RCC_CR_OFFSET 0x0000 /* Clock control register */ +#define STM32_RCC_ICSCR_OFFSET 0x0004 /* Internal clock sources calibration register */ +#define STM32_RCC_CFGR_OFFSET 0x0008 /* Clock configuration register */ +#define STM32_RCC_PLLCFG_OFFSET 0x000c /* PLL configuration register */ +#define STM32_RCC_PLLSAI1CFG_OFFSET 0x0010 /* PLLSAI1 configuration register */ +#define STM32_RCC_PLLSAI2CFG_OFFSET 0x0014 /* PLLSAI2 configuration register */ +#define STM32_RCC_CIER_OFFSET 0x0018 /* Clock interrupt enable register */ +#define STM32_RCC_CIFR_OFFSET 0x001c /* Clock interrupt flag register */ +#define STM32_RCC_CICR_OFFSET 0x0020 /* Clock interrupt clear register */ +#define STM32_RCC_AHB1RSTR_OFFSET 0x0028 /* AHB1 peripheral reset register */ +#define STM32_RCC_AHB2RSTR_OFFSET 0x002c /* AHB2 peripheral reset register */ +#define STM32_RCC_AHB3RSTR_OFFSET 0x0030 /* AHB3 peripheral reset register */ +#define STM32_RCC_APB1RSTR1_OFFSET 0x0038 /* APB1 Peripheral reset register 1 */ +#define STM32_RCC_APB1RSTR2_OFFSET 0x003c /* APB1 Peripheral reset register 2 */ +#define STM32_RCC_APB2RSTR_OFFSET 0x0040 /* APB2 Peripheral reset register */ +#define STM32_RCC_AHB1ENR_OFFSET 0x0048 /* AHB1 Peripheral Clock enable register */ +#define STM32_RCC_AHB2ENR_OFFSET 0x004c /* AHB2 Peripheral Clock enable register */ +#define STM32_RCC_AHB3ENR_OFFSET 0x0050 /* AHB3 Peripheral Clock enable register */ +#define STM32_RCC_APB1ENR1_OFFSET 0x0058 /* APB1 Peripheral Clock enable register 1 */ +#define STM32_RCC_APB1ENR2_OFFSET 0x005c /* APB1 Peripheral Clock enable register 2 */ +#define STM32_RCC_APB2ENR_OFFSET 0x0060 /* APB2 Peripheral Clock enable register */ +#define STM32_RCC_AHB1SMENR_OFFSET 0x0068 /* RCC AHB1 low power mode peripheral clock enable register */ +#define STM32_RCC_AHB2SMENR_OFFSET 0x006c /* RCC AHB2 low power mode peripheral clock enable register */ +#define STM32_RCC_AHB3SMENR_OFFSET 0x0070 /* RCC AHB3 low power mode peripheral clock enable register */ +#define STM32_RCC_APB1SMENR1_OFFSET 0x0078 /* RCC APB1 low power mode peripheral clock enable register 1 */ +#define STM32_RCC_APB1SMENR2_OFFSET 0x007c /* RCC APB1 low power mode peripheral clock enable register 2 */ +#define STM32_RCC_APB2SMENR_OFFSET 0x0080 /* RCC APB2 low power mode peripheral clock enable register */ +#define STM32_RCC_CCIPR_OFFSET 0x0088 /* Peripherals independent clock configuration register 1 */ +#define STM32_RCC_BDCR_OFFSET 0x0090 /* Backup domain control register */ +#define STM32_RCC_CSR_OFFSET 0x0094 /* Control/status register */ +#define STM32_RCC_CRRCR_OFFSET 0x0098 /* Clock recovery RC register */ +#define STM32_RCC_CCIPR2_OFFSET 0x009c /* Peripherals independent clock configuration register 2 */ +#define STM32_RCC_SECCFGR_OFFSET 0x00b8 /* Secure configuration register */ +#define STM32_RCC_SECSR_OFFSET 0x00bc /* Secure status register */ +#define STM32_RCC_AHB1SECSR_OFFSET 0x00e8 /* AHB1 security status register */ +#define STM32_RCC_AHB2SECSR_OFFSET 0x00ec /* AHB2 security status register */ +#define STM32_RCC_AHB3SECSR_OFFSET 0x00f0 /* AHB3 security status register */ +#define STM32_RCC_APB1SECSR1_OFFSET 0x00f8 /* APB1 security status register 1 */ +#define STM32_RCC_APB1SECSR2_OFFSET 0x00fc /* APB1 security status register 2 */ +#define STM32_RCC_APB2SECSR_OFFSET 0x0100 /* APB2 security status register */ /* Register Addresses *******************************************************/ -#define STM32L5_RCC_CR (STM32L5_RCC_BASE + STM32L5_RCC_CR_OFFSET) -#define STM32L5_RCC_ICSCR (STM32L5_RCC_BASE + STM32L5_RCC_ICSCR_OFFSET) -#define STM32L5_RCC_CFGR (STM32L5_RCC_BASE + STM32L5_RCC_CFGR_OFFSET) -#define STM32L5_RCC_PLLCFG (STM32L5_RCC_BASE + STM32L5_RCC_PLLCFG_OFFSET) -#define STM32L5_RCC_PLLSAI1CFG (STM32L5_RCC_BASE + STM32L5_RCC_PLLSAI1CFG_OFFSET) -#define STM32L5_RCC_PLLSAI2CFG (STM32L5_RCC_BASE + STM32L5_RCC_PLLSAI2CFG_OFFSET) -#define STM32L5_RCC_CIER (STM32L5_RCC_BASE + STM32L5_RCC_CIER_OFFSET) -#define STM32L5_RCC_CIFR (STM32L5_RCC_BASE + STM32L5_RCC_CIFR_OFFSET) -#define STM32L5_RCC_CICR (STM32L5_RCC_BASE + STM32L5_RCC_CICR_OFFSET) -#define STM32L5_RCC_AHB1RSTR (STM32L5_RCC_BASE + STM32L5_RCC_AHB1RSTR_OFFSET) -#define STM32L5_RCC_AHB2RSTR (STM32L5_RCC_BASE + STM32L5_RCC_AHB2RSTR_OFFSET) -#define STM32L5_RCC_AHB3RSTR (STM32L5_RCC_BASE + STM32L5_RCC_AHB3RSTR_OFFSET) -#define STM32L5_RCC_APB1RSTR1 (STM32L5_RCC_BASE + STM32L5_RCC_APB1RSTR1_OFFSET) -#define STM32L5_RCC_APB1RSTR2 (STM32L5_RCC_BASE + STM32L5_RCC_APB1RSTR2_OFFSET) -#define STM32L5_RCC_APB2RSTR (STM32L5_RCC_BASE + STM32L5_RCC_APB2RSTR_OFFSET) -#define STM32L5_RCC_AHB1ENR (STM32L5_RCC_BASE + STM32L5_RCC_AHB1ENR_OFFSET) -#define STM32L5_RCC_AHB2ENR (STM32L5_RCC_BASE + STM32L5_RCC_AHB2ENR_OFFSET) -#define STM32L5_RCC_AHB3ENR (STM32L5_RCC_BASE + STM32L5_RCC_AHB3ENR_OFFSET) -#define STM32L5_RCC_APB1ENR1 (STM32L5_RCC_BASE + STM32L5_RCC_APB1ENR1_OFFSET) -#define STM32L5_RCC_APB1ENR2 (STM32L5_RCC_BASE + STM32L5_RCC_APB1ENR2_OFFSET) -#define STM32L5_RCC_APB2ENR (STM32L5_RCC_BASE + STM32L5_RCC_APB2ENR_OFFSET) -#define STM32L5_RCC_AHB1SMENR (STM32L5_RCC_BASE + STM32L5_RCC_AHB1SMENR_OFFSET) -#define STM32L5_RCC_AHB2SMENR (STM32L5_RCC_BASE + STM32L5_RCC_AHB2SMENR_OFFSET) -#define STM32L5_RCC_AHB3SMENR (STM32L5_RCC_BASE + STM32L5_RCC_AHB3SMENR_OFFSET) -#define STM32L5_RCC_APB1SMENR1 (STM32L5_RCC_BASE + STM32L5_RCC_APB1SMENR1_OFFSET) -#define STM32L5_RCC_APB1SMENR2 (STM32L5_RCC_BASE + STM32L5_RCC_APB1SMENR2_OFFSET) -#define STM32L5_RCC_APB2SMENR (STM32L5_RCC_BASE + STM32L5_RCC_APB2SMENR_OFFSET) -#define STM32L5_RCC_CCIPR (STM32L5_RCC_BASE + STM32L5_RCC_CCIPR_OFFSET) -#define STM32L5_RCC_BDCR (STM32L5_RCC_BASE + STM32L5_RCC_BDCR_OFFSET) -#define STM32L5_RCC_CSR (STM32L5_RCC_BASE + STM32L5_RCC_CSR_OFFSET) -#define STM32L5_RCC_CRRCR (STM32L5_RCC_BASE + STM32L5_RCC_CRRCR_OFFSET) -#define STM32L5_RCC_CCIPR2 (STM32L5_RCC_BASE + STM32L5_RCC_CCIPR2_OFFSET) -#define STM32L5_RCC_SECCFGR (STM32L5_RCC_BASE + STM32L5_RCC_SECCFGR_OFFSET) -#define STM32L5_RCC_SECSR (STM32L5_RCC_BASE + STM32L5_RCC_SECSR_OFFSET) -#define STM32L5_RCC_AHB1SECSR (STM32L5_RCC_BASE + STM32L5_RCC_AHB1SECSR_OFFSET) -#define STM32L5_RCC_AHB2SECSR (STM32L5_RCC_BASE + STM32L5_RCC_AHB2SECSR_OFFSET) -#define STM32L5_RCC_AHB3SECSR (STM32L5_RCC_BASE + STM32L5_RCC_AHB3SECSR_OFFSET) -#define STM32L5_RCC_APB1SECSR1 (STM32L5_RCC_BASE + STM32L5_RCC_APB1SECSR1_OFFSET) -#define STM32L5_RCC_APB1SECSR2 (STM32L5_RCC_BASE + STM32L5_RCC_APB1SECSR2_OFFSET) -#define STM32L5_RCC_APB2SECSR (STM32L5_RCC_BASE + STM32L5_RCC_APB2SECSR_OFFSET) +#define STM32_RCC_CR (STM32_RCC_BASE + STM32_RCC_CR_OFFSET) +#define STM32_RCC_ICSCR (STM32_RCC_BASE + STM32_RCC_ICSCR_OFFSET) +#define STM32_RCC_CFGR (STM32_RCC_BASE + STM32_RCC_CFGR_OFFSET) +#define STM32_RCC_PLLCFG (STM32_RCC_BASE + STM32_RCC_PLLCFG_OFFSET) +#define STM32_RCC_PLLSAI1CFG (STM32_RCC_BASE + STM32_RCC_PLLSAI1CFG_OFFSET) +#define STM32_RCC_PLLSAI2CFG (STM32_RCC_BASE + STM32_RCC_PLLSAI2CFG_OFFSET) +#define STM32_RCC_CIER (STM32_RCC_BASE + STM32_RCC_CIER_OFFSET) +#define STM32_RCC_CIFR (STM32_RCC_BASE + STM32_RCC_CIFR_OFFSET) +#define STM32_RCC_CICR (STM32_RCC_BASE + STM32_RCC_CICR_OFFSET) +#define STM32_RCC_AHB1RSTR (STM32_RCC_BASE + STM32_RCC_AHB1RSTR_OFFSET) +#define STM32_RCC_AHB2RSTR (STM32_RCC_BASE + STM32_RCC_AHB2RSTR_OFFSET) +#define STM32_RCC_AHB3RSTR (STM32_RCC_BASE + STM32_RCC_AHB3RSTR_OFFSET) +#define STM32_RCC_APB1RSTR1 (STM32_RCC_BASE + STM32_RCC_APB1RSTR1_OFFSET) +#define STM32_RCC_APB1RSTR2 (STM32_RCC_BASE + STM32_RCC_APB1RSTR2_OFFSET) +#define STM32_RCC_APB2RSTR (STM32_RCC_BASE + STM32_RCC_APB2RSTR_OFFSET) +#define STM32_RCC_AHB1ENR (STM32_RCC_BASE + STM32_RCC_AHB1ENR_OFFSET) +#define STM32_RCC_AHB2ENR (STM32_RCC_BASE + STM32_RCC_AHB2ENR_OFFSET) +#define STM32_RCC_AHB3ENR (STM32_RCC_BASE + STM32_RCC_AHB3ENR_OFFSET) +#define STM32_RCC_APB1ENR1 (STM32_RCC_BASE + STM32_RCC_APB1ENR1_OFFSET) +#define STM32_RCC_APB1ENR2 (STM32_RCC_BASE + STM32_RCC_APB1ENR2_OFFSET) +#define STM32_RCC_APB2ENR (STM32_RCC_BASE + STM32_RCC_APB2ENR_OFFSET) +#define STM32_RCC_AHB1SMENR (STM32_RCC_BASE + STM32_RCC_AHB1SMENR_OFFSET) +#define STM32_RCC_AHB2SMENR (STM32_RCC_BASE + STM32_RCC_AHB2SMENR_OFFSET) +#define STM32_RCC_AHB3SMENR (STM32_RCC_BASE + STM32_RCC_AHB3SMENR_OFFSET) +#define STM32_RCC_APB1SMENR1 (STM32_RCC_BASE + STM32_RCC_APB1SMENR1_OFFSET) +#define STM32_RCC_APB1SMENR2 (STM32_RCC_BASE + STM32_RCC_APB1SMENR2_OFFSET) +#define STM32_RCC_APB2SMENR (STM32_RCC_BASE + STM32_RCC_APB2SMENR_OFFSET) +#define STM32_RCC_CCIPR (STM32_RCC_BASE + STM32_RCC_CCIPR_OFFSET) +#define STM32_RCC_BDCR (STM32_RCC_BASE + STM32_RCC_BDCR_OFFSET) +#define STM32_RCC_CSR (STM32_RCC_BASE + STM32_RCC_CSR_OFFSET) +#define STM32_RCC_CRRCR (STM32_RCC_BASE + STM32_RCC_CRRCR_OFFSET) +#define STM32_RCC_CCIPR2 (STM32_RCC_BASE + STM32_RCC_CCIPR2_OFFSET) +#define STM32_RCC_SECCFGR (STM32_RCC_BASE + STM32_RCC_SECCFGR_OFFSET) +#define STM32_RCC_SECSR (STM32_RCC_BASE + STM32_RCC_SECSR_OFFSET) +#define STM32_RCC_AHB1SECSR (STM32_RCC_BASE + STM32_RCC_AHB1SECSR_OFFSET) +#define STM32_RCC_AHB2SECSR (STM32_RCC_BASE + STM32_RCC_AHB2SECSR_OFFSET) +#define STM32_RCC_AHB3SECSR (STM32_RCC_BASE + STM32_RCC_AHB3SECSR_OFFSET) +#define STM32_RCC_APB1SECSR1 (STM32_RCC_BASE + STM32_RCC_APB1SECSR1_OFFSET) +#define STM32_RCC_APB1SECSR2 (STM32_RCC_BASE + STM32_RCC_APB1SECSR2_OFFSET) +#define STM32_RCC_APB2SECSR (STM32_RCC_BASE + STM32_RCC_APB2SECSR_OFFSET) /* Register Bitfield Definitions ********************************************/ @@ -865,5 +865,5 @@ # define RCC_CCIPR2_OSPISEL_MSI (1 << RCC_CCIPR2_OSPISEL_SHIFT) # define RCC_CCIPR2_OSPISEL_PLL48M1CLK (2 << RCC_CCIPR2_OSPISEL_SHIFT) -#endif /* CONFIG_STM32L5_STM32L562XX */ +#endif /* CONFIG_STM32_STM32L562XX */ #endif /* __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32L562XX_RCC_H */ diff --git a/arch/arm/src/stm32l5/hardware/stm32l562xx_syscfg.h b/arch/arm/src/stm32l5/hardware/stm32l562xx_syscfg.h index db365f949741f..9d900a32adf54 100644 --- a/arch/arm/src/stm32l5/hardware/stm32l562xx_syscfg.h +++ b/arch/arm/src/stm32l5/hardware/stm32l562xx_syscfg.h @@ -30,7 +30,7 @@ #include #include "chip.h" -#if defined(CONFIG_STM32L5_STM32L562XX) +#if defined(CONFIG_STM32_STM32L562XX) /**************************************************************************** * Pre-processor Definitions @@ -38,31 +38,31 @@ /* Register Offsets *********************************************************/ -#define STM32L5_SYSCFG_SECCFGR_OFFSET 0x0000 /* SYSCFG secure configuration register */ -#define STM32L5_SYSCFG_CFGR1_OFFSET 0x0004 /* SYSCFG configuration register 1 */ -#define STM32L5_SYSCFG_FPUIMR_OFFSET 0x0008 /* SYSCFG FPU interrupt mask register */ -#define STM32L5_SYSCFG_CNSLCKR_OFFSET 0x000c /* SYSCFG CPU non-secure lock register */ -#define STM32L5_SYSCFG_CSLCKR_OFFSET 0x0010 /* SYSCFG CPU secure lock register */ -#define STM32L5_SYSCFG_CFGR2_OFFSET 0x0014 /* SYSCFG configuration register 2 */ -#define STM32L5_SYSCFG_SCSR_OFFSET 0x0018 /* SYSCFG SRAM2 control and status register */ -#define STM32L5_SYSCFG_SKR_OFFSET 0x001c /* SYSCFG SRAM2 key register */ -#define STM32L5_SYSCFG_SWPR_OFFSET 0x0020 /* SYSCFG SRAM2 write protection register */ -#define STM32L5_SYSCFG_SWPR2_OFFSET 0x0024 /* SYSCFG SRAM2 write protection register 2 */ -#define STM32L5_SYSCFG_RSSCMDR_OFFSET 0x002c /* SYSCFG RSS command register */ +#define STM32_SYSCFG_SECCFGR_OFFSET 0x0000 /* SYSCFG secure configuration register */ +#define STM32_SYSCFG_CFGR1_OFFSET 0x0004 /* SYSCFG configuration register 1 */ +#define STM32_SYSCFG_FPUIMR_OFFSET 0x0008 /* SYSCFG FPU interrupt mask register */ +#define STM32_SYSCFG_CNSLCKR_OFFSET 0x000c /* SYSCFG CPU non-secure lock register */ +#define STM32_SYSCFG_CSLCKR_OFFSET 0x0010 /* SYSCFG CPU secure lock register */ +#define STM32_SYSCFG_CFGR2_OFFSET 0x0014 /* SYSCFG configuration register 2 */ +#define STM32_SYSCFG_SCSR_OFFSET 0x0018 /* SYSCFG SRAM2 control and status register */ +#define STM32_SYSCFG_SKR_OFFSET 0x001c /* SYSCFG SRAM2 key register */ +#define STM32_SYSCFG_SWPR_OFFSET 0x0020 /* SYSCFG SRAM2 write protection register */ +#define STM32_SYSCFG_SWPR2_OFFSET 0x0024 /* SYSCFG SRAM2 write protection register 2 */ +#define STM32_SYSCFG_RSSCMDR_OFFSET 0x002c /* SYSCFG RSS command register */ /* Register Addresses *******************************************************/ -#define STM32L5_SYSCFG_SECCFGR (STM32L5_SYSCFG_BASE + STM32L5_SYSCFG_SECCFGR_OFFSET) -#define STM32L5_SYSCFG_CFGR1 (STM32L5_SYSCFG_BASE + STM32L5_SYSCFG_CFGR1_OFFSET) -#define STM32L5_SYSCFG_FPUIMR (STM32L5_SYSCFG_BASE + STM32L5_SYSCFG_FPUIMR_OFFSET) -#define STM32L5_SYSCFG_CNSLCKR (STM32L5_SYSCFG_BASE + STM32L5_SYSCFG_CNSLCKR_OFFSET) -#define STM32L5_SYSCFG_CSLCKR (STM32L5_SYSCFG_BASE + STM32L5_SYSCFG_CSLCKR_OFFSET) -#define STM32L5_SYSCFG_CFGR2 (STM32L5_SYSCFG_BASE + STM32L5_SYSCFG_CFGR2_OFFSET) -#define STM32L5_SYSCFG_SCSR (STM32L5_SYSCFG_BASE + STM32L5_SYSCFG_SCSR_OFFSET) -#define STM32L5_SYSCFG_SKR (STM32L5_SYSCFG_BASE + STM32L5_SYSCFG_SKR_OFFSET) -#define STM32L5_SYSCFG_SWPR (STM32L5_SYSCFG_BASE + STM32L5_SYSCFG_SWPR_OFFSET) -#define STM32L5_SYSCFG_SWPR2 (STM32L5_SYSCFG_BASE + STM32L5_SYSCFG_SWPR2_OFFSET) -#define STM32L5_SYSCFG_RSSCMDR (STM32L5_SYSCFG_BASE + STM32L5_SYSCFG_RSSCMDR_OFFSET) +#define STM32_SYSCFG_SECCFGR (STM32_SYSCFG_BASE + STM32_SYSCFG_SECCFGR_OFFSET) +#define STM32_SYSCFG_CFGR1 (STM32_SYSCFG_BASE + STM32_SYSCFG_CFGR1_OFFSET) +#define STM32_SYSCFG_FPUIMR (STM32_SYSCFG_BASE + STM32_SYSCFG_FPUIMR_OFFSET) +#define STM32_SYSCFG_CNSLCKR (STM32_SYSCFG_BASE + STM32_SYSCFG_CNSLCKR_OFFSET) +#define STM32_SYSCFG_CSLCKR (STM32_SYSCFG_BASE + STM32_SYSCFG_CSLCKR_OFFSET) +#define STM32_SYSCFG_CFGR2 (STM32_SYSCFG_BASE + STM32_SYSCFG_CFGR2_OFFSET) +#define STM32_SYSCFG_SCSR (STM32_SYSCFG_BASE + STM32_SYSCFG_SCSR_OFFSET) +#define STM32_SYSCFG_SKR (STM32_SYSCFG_BASE + STM32_SYSCFG_SKR_OFFSET) +#define STM32_SYSCFG_SWPR (STM32_SYSCFG_BASE + STM32_SYSCFG_SWPR_OFFSET) +#define STM32_SYSCFG_SWPR2 (STM32_SYSCFG_BASE + STM32_SYSCFG_SWPR2_OFFSET) +#define STM32_SYSCFG_RSSCMDR (STM32_SYSCFG_BASE + STM32_SYSCFG_RSSCMDR_OFFSET) /* Register Bitfield Definitions ********************************************/ @@ -133,5 +133,5 @@ #define SYSCFG_RSSCMDR_SHIFT 0 #define SYSCFG_RSSCMDR_MASK (0xFFFF << SYSCFG_RSSCMDR_SHIFT) -#endif /* CONFIG_STM32L5_STM32L562XX */ +#endif /* CONFIG_STM32_STM32L562XX */ #endif /* __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32L562XX_SYSCFG_H */ diff --git a/arch/arm/src/stm32l5/hardware/stm32l5_exti.h b/arch/arm/src/stm32l5/hardware/stm32l5_exti.h index b321ad3f4cc7f..c7ecf0f23cb58 100644 --- a/arch/arm/src/stm32l5/hardware/stm32l5_exti.h +++ b/arch/arm/src/stm32l5/hardware/stm32l5_exti.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32L5_EXTI_H -#define __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32L5_EXTI_H +#ifndef __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32_EXTI_H +#define __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32_EXTI_H /**************************************************************************** * Included Files @@ -36,55 +36,55 @@ /* Register Offsets *********************************************************/ -#define STM32L5_EXTI_RTSR1_OFFSET 0x0000 /* Rising Trigger Selection 1 */ -#define STM32L5_EXTI_FTSR1_OFFSET 0x0004 /* Falling Trigger Selection 1 */ -#define STM32L5_EXTI_SWIER1_OFFSET 0x0008 /* Software Interrupt Event 1 */ -#define STM32L5_EXTI_RPR1_OFFSET 0x000c /* Rising Edge Pending 1 */ -#define STM32L5_EXTI_FPR1_OFFSET 0x0010 /* Falling Edge Pending 1 */ -#define STM32L5_EXTI_SECCFGR1_OFFSET 0x0014 /* Security Configuration 1 */ -#define STM32L5_EXTI_PRIVCFGR1_OFFSET 0x0018 /* Privilege Configuration 1 */ -#define STM32L5_EXTI_RTSR2_OFFSET 0x0020 /* Rising Trigger Selection 2 */ -#define STM32L5_EXTI_FTSR2_OFFSET 0x0024 /* Falling Trigger Selection 2 */ -#define STM32L5_EXTI_SWIER2_OFFSET 0x0028 /* Software Interrupt Event 2 */ -#define STM32L5_EXTI_RPR2_OFFSET 0x002c /* Rising Edge Pending 2 */ -#define STM32L5_EXTI_FPR2_OFFSET 0x0030 /* Falling Edge Pending 2 */ -#define STM32L5_EXTI_SECCFGR2_OFFSET 0x0034 /* Security Configuration 2 */ -#define STM32L5_EXTI_PRIVCFGR2_OFFSET 0x0038 /* Privilege Configuration 2 */ -#define STM32L5_EXTI_EXTICR1_OFFSET 0x0060 /* External Interrupt Selection 1 */ -#define STM32L5_EXTI_EXTICR2_OFFSET 0x0060 /* External Interrupt Selection 2 */ -#define STM32L5_EXTI_EXTICR3_OFFSET 0x0060 /* External Interrupt Selection 3 */ -#define STM32L5_EXTI_EXTICR4_OFFSET 0x0060 /* External Interrupt Selection 4 */ -#define STM32L5_EXTI_LOCKR_OFFSET 0x0070 /* Lock */ -#define STM32L5_EXTI_IMR1_OFFSET 0x0080 /* CPU Wakeup with Interrupt Mask 1 */ -#define STM32L5_EXTI_EMR1_OFFSET 0x0084 /* CPU Wakeup with Event Mask 1 */ -#define STM32L5_EXTI_IMR2_OFFSET 0x0090 /* CPU Wakeup with Interrupt Mask 2 */ -#define STM32L5_EXTI_EMR2_OFFSET 0x0094 /* CPU Wakeup with Event Mask 2 */ +#define STM32_EXTI_RTSR1_OFFSET 0x0000 /* Rising Trigger Selection 1 */ +#define STM32_EXTI_FTSR1_OFFSET 0x0004 /* Falling Trigger Selection 1 */ +#define STM32_EXTI_SWIER1_OFFSET 0x0008 /* Software Interrupt Event 1 */ +#define STM32_EXTI_RPR1_OFFSET 0x000c /* Rising Edge Pending 1 */ +#define STM32_EXTI_FPR1_OFFSET 0x0010 /* Falling Edge Pending 1 */ +#define STM32_EXTI_SECCFGR1_OFFSET 0x0014 /* Security Configuration 1 */ +#define STM32_EXTI_PRIVCFGR1_OFFSET 0x0018 /* Privilege Configuration 1 */ +#define STM32_EXTI_RTSR2_OFFSET 0x0020 /* Rising Trigger Selection 2 */ +#define STM32_EXTI_FTSR2_OFFSET 0x0024 /* Falling Trigger Selection 2 */ +#define STM32_EXTI_SWIER2_OFFSET 0x0028 /* Software Interrupt Event 2 */ +#define STM32_EXTI_RPR2_OFFSET 0x002c /* Rising Edge Pending 2 */ +#define STM32_EXTI_FPR2_OFFSET 0x0030 /* Falling Edge Pending 2 */ +#define STM32_EXTI_SECCFGR2_OFFSET 0x0034 /* Security Configuration 2 */ +#define STM32_EXTI_PRIVCFGR2_OFFSET 0x0038 /* Privilege Configuration 2 */ +#define STM32_EXTI_EXTICR1_OFFSET 0x0060 /* External Interrupt Selection 1 */ +#define STM32_EXTI_EXTICR2_OFFSET 0x0060 /* External Interrupt Selection 2 */ +#define STM32_EXTI_EXTICR3_OFFSET 0x0060 /* External Interrupt Selection 3 */ +#define STM32_EXTI_EXTICR4_OFFSET 0x0060 /* External Interrupt Selection 4 */ +#define STM32_EXTI_LOCKR_OFFSET 0x0070 /* Lock */ +#define STM32_EXTI_IMR1_OFFSET 0x0080 /* CPU Wakeup with Interrupt Mask 1 */ +#define STM32_EXTI_EMR1_OFFSET 0x0084 /* CPU Wakeup with Event Mask 1 */ +#define STM32_EXTI_IMR2_OFFSET 0x0090 /* CPU Wakeup with Interrupt Mask 2 */ +#define STM32_EXTI_EMR2_OFFSET 0x0094 /* CPU Wakeup with Event Mask 2 */ /* Register Addresses *******************************************************/ -#define STM32L5_EXTI_RTSR1 (STM32L5_EXTI_BASE + STM32L5_EXTI_RTSR1_OFFSET) -#define STM32L5_EXTI_FTSR1 (STM32L5_EXTI_BASE + STM32L5_EXTI_FTSR1_OFFSET) -#define STM32L5_EXTI_SWIER1 (STM32L5_EXTI_BASE + STM32L5_EXTI_SWIER1_OFFSET) -#define STM32L5_EXTI_RPR1 (STM32L5_EXTI_BASE + STM32L5_EXTI_RPR1_OFFSET) -#define STM32L5_EXTI_FPR1 (STM32L5_EXTI_BASE + STM32L5_EXTI_FPR1_OFFSET) -#define STM32L5_EXTI_SECCFGR1 (STM32L5_EXTI_BASE + STM32L5_EXTI_SECCFGR1_OFFSET) -#define STM32L5_EXTI_PRIVCFGR1 (STM32L5_EXTI_BASE + STM32L5_EXTI_PRIVCFGR1_OFFSET) -#define STM32L5_EXTI_RTSR2 (STM32L5_EXTI_BASE + STM32L5_EXTI_RTSR2_OFFSET) -#define STM32L5_EXTI_FTSR2 (STM32L5_EXTI_BASE + STM32L5_EXTI_FTSR2_OFFSET) -#define STM32L5_EXTI_SWIER2 (STM32L5_EXTI_BASE + STM32L5_EXTI_SWIER2_OFFSET) -#define STM32L5_EXTI_RPR2 (STM32L5_EXTI_BASE + STM32L5_EXTI_RPR2_OFFSET) -#define STM32L5_EXTI_FPR2 (STM32L5_EXTI_BASE + STM32L5_EXTI_FPR2_OFFSET) -#define STM32L5_EXTI_SECCFGR2 (STM32L5_EXTI_BASE + STM32L5_EXTI_SECCFGR2_OFFSET) -#define STM32L5_EXTI_PRIVCFGR2 (STM32L5_EXTI_BASE + STM32L5_EXTI_PRIVCFGR2_OFFSET) -#define STM32L5_EXTI_EXTICR1 (STM32L5_EXTI_BASE + STM32L5_EXTI_EXTICR1_OFFSET) -#define STM32L5_EXTI_EXTICR2 (STM32L5_EXTI_BASE + STM32L5_EXTI_EXTICR2_OFFSET) -#define STM32L5_EXTI_EXTICR3 (STM32L5_EXTI_BASE + STM32L5_EXTI_EXTICR3_OFFSET) -#define STM32L5_EXTI_EXTICR4 (STM32L5_EXTI_BASE + STM32L5_EXTI_EXTICR4_OFFSET) -#define STM32L5_EXTI_LOCKR (STM32L5_EXTI_BASE + STM32L5_EXTI_LOCKR_OFFSET) -#define STM32L5_EXTI_IMR1 (STM32L5_EXTI_BASE + STM32L5_EXTI_IMR1_OFFSET) -#define STM32L5_EXTI_EMR1 (STM32L5_EXTI_BASE + STM32L5_EXTI_EMR1_OFFSET) -#define STM32L5_EXTI_IMR2 (STM32L5_EXTI_BASE + STM32L5_EXTI_IMR2_OFFSET) -#define STM32L5_EXTI_EMR2 (STM32L5_EXTI_BASE + STM32L5_EXTI_EMR2_OFFSET) +#define STM32_EXTI_RTSR1 (STM32_EXTI_BASE + STM32_EXTI_RTSR1_OFFSET) +#define STM32_EXTI_FTSR1 (STM32_EXTI_BASE + STM32_EXTI_FTSR1_OFFSET) +#define STM32_EXTI_SWIER1 (STM32_EXTI_BASE + STM32_EXTI_SWIER1_OFFSET) +#define STM32_EXTI_RPR1 (STM32_EXTI_BASE + STM32_EXTI_RPR1_OFFSET) +#define STM32_EXTI_FPR1 (STM32_EXTI_BASE + STM32_EXTI_FPR1_OFFSET) +#define STM32_EXTI_SECCFGR1 (STM32_EXTI_BASE + STM32_EXTI_SECCFGR1_OFFSET) +#define STM32_EXTI_PRIVCFGR1 (STM32_EXTI_BASE + STM32_EXTI_PRIVCFGR1_OFFSET) +#define STM32_EXTI_RTSR2 (STM32_EXTI_BASE + STM32_EXTI_RTSR2_OFFSET) +#define STM32_EXTI_FTSR2 (STM32_EXTI_BASE + STM32_EXTI_FTSR2_OFFSET) +#define STM32_EXTI_SWIER2 (STM32_EXTI_BASE + STM32_EXTI_SWIER2_OFFSET) +#define STM32_EXTI_RPR2 (STM32_EXTI_BASE + STM32_EXTI_RPR2_OFFSET) +#define STM32_EXTI_FPR2 (STM32_EXTI_BASE + STM32_EXTI_FPR2_OFFSET) +#define STM32_EXTI_SECCFGR2 (STM32_EXTI_BASE + STM32_EXTI_SECCFGR2_OFFSET) +#define STM32_EXTI_PRIVCFGR2 (STM32_EXTI_BASE + STM32_EXTI_PRIVCFGR2_OFFSET) +#define STM32_EXTI_EXTICR1 (STM32_EXTI_BASE + STM32_EXTI_EXTICR1_OFFSET) +#define STM32_EXTI_EXTICR2 (STM32_EXTI_BASE + STM32_EXTI_EXTICR2_OFFSET) +#define STM32_EXTI_EXTICR3 (STM32_EXTI_BASE + STM32_EXTI_EXTICR3_OFFSET) +#define STM32_EXTI_EXTICR4 (STM32_EXTI_BASE + STM32_EXTI_EXTICR4_OFFSET) +#define STM32_EXTI_LOCKR (STM32_EXTI_BASE + STM32_EXTI_LOCKR_OFFSET) +#define STM32_EXTI_IMR1 (STM32_EXTI_BASE + STM32_EXTI_IMR1_OFFSET) +#define STM32_EXTI_EMR1 (STM32_EXTI_BASE + STM32_EXTI_EMR1_OFFSET) +#define STM32_EXTI_IMR2 (STM32_EXTI_BASE + STM32_EXTI_IMR2_OFFSET) +#define STM32_EXTI_EMR2 (STM32_EXTI_BASE + STM32_EXTI_EMR2_OFFSET) /* Register Bitfield Definitions ********************************************/ @@ -118,4 +118,4 @@ #define EXTI2_UCPD1 (1 << 9) /* EXTI line 41: UCPD1 wakeup */ #define EXTI2_LPTIM3 (1 << 10) /* EXTI line 42: LPTIM3 wakeup */ -#endif /* __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32L5_EXTI_H */ +#endif /* __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32_EXTI_H */ diff --git a/arch/arm/src/stm32l5/hardware/stm32l5_flash.h b/arch/arm/src/stm32l5/hardware/stm32l5_flash.h index 3f9c343e0e7f7..ba67ec89f81b7 100644 --- a/arch/arm/src/stm32l5/hardware/stm32l5_flash.h +++ b/arch/arm/src/stm32l5/hardware/stm32l5_flash.h @@ -35,10 +35,10 @@ /* Flash size is known from the chip selection: * - * When CONFIG_STM32L5_FLASH_OVERRIDE_DEFAULT is set the - * CONFIG_STM32L5_FLASH_CONFIG_x selects the default FLASH size based on + * When CONFIG_STM32_FLASH_OVERRIDE_DEFAULT is set the + * CONFIG_STM32_FLASH_CONFIG_x selects the default FLASH size based on * the chip part number. This value can be overridden with - * CONFIG_STM32L5_FLASH_OVERRIDE_x + * CONFIG_STM32_FLASH_OVERRIDE_x * * Parts STM32L552xC and STM32L562xC have 256Kb of FLASH * Parts STM32L552xE and STM32L562xE have 512Kb of FLASH @@ -46,114 +46,114 @@ * N.B. Only Single bank mode is supported */ -#if !defined(CONFIG_STM32L5_FLASH_OVERRIDE_DEFAULT) && \ - !defined(CONFIG_STM32L5_FLASH_OVERRIDE_C) && \ - !defined(CONFIG_STM32L5_FLASH_OVERRIDE_E) && \ - !defined(CONFIG_STM32L5_FLASH_CONFIG_C) && \ - !defined(CONFIG_STM32L5_FLASH_CONFIG_E) -# define CONFIG_STM32L5_FLASH_OVERRIDE_E +#if !defined(CONFIG_STM32_FLASH_OVERRIDE_DEFAULT) && \ + !defined(CONFIG_STM32_FLASH_OVERRIDE_C) && \ + !defined(CONFIG_STM32_FLASH_OVERRIDE_E) && \ + !defined(CONFIG_STM32_FLASH_CONFIG_C) && \ + !defined(CONFIG_STM32_FLASH_CONFIG_E) +# define CONFIG_STM32_FLASH_OVERRIDE_E # warning "Flash size not defined defaulting to 512KiB (E)" #endif /* Override of the Flash has been chosen */ -#if !defined(CONFIG_STM32L5_FLASH_OVERRIDE_DEFAULT) -# undef CONFIG_STM32L5_FLASH_CONFIG_C -# undef CONFIG_STM32L5_FLASH_CONFIG_E -# if defined(CONFIG_STM32L5_FLASH_OVERRIDE_C) -# define CONFIG_STM32L5_FLASH_CONFIG_C -# elif defined(CONFIG_STM32L5_FLASH_OVERRIDE_E) -# define CONFIG_STM32L5_FLASH_CONFIG_E +#if !defined(CONFIG_STM32_FLASH_OVERRIDE_DEFAULT) +# undef CONFIG_STM32_FLASH_CONFIG_C +# undef CONFIG_STM32_FLASH_CONFIG_E +# if defined(CONFIG_STM32_FLASH_OVERRIDE_C) +# define CONFIG_STM32_FLASH_CONFIG_C +# elif defined(CONFIG_STM32_FLASH_OVERRIDE_E) +# define CONFIG_STM32_FLASH_CONFIG_E # endif #endif /* Define the valid configuration */ -#if defined(CONFIG_STM32L5_FLASH_CONFIG_C) /* 256 kB */ -# define STM32L5_FLASH_NPAGES 64 -# define STM32L5_FLASH_PAGESIZE 4096 -#elif defined(CONFIG_STM32L5_FLASH_CONFIG_E) /* 512 kB */ -# define STM32L5_FLASH_NPAGES 128 -# define STM32L5_FLASH_PAGESIZE 4096 +#if defined(CONFIG_STM32_FLASH_CONFIG_C) /* 256 kB */ +# define STM32_FLASH_NPAGES 64 +# define STM32_FLASH_PAGESIZE 4096 +#elif defined(CONFIG_STM32_FLASH_CONFIG_E) /* 512 kB */ +# define STM32_FLASH_NPAGES 128 +# define STM32_FLASH_PAGESIZE 4096 #else # error "unknown flash configuration!" #endif -#ifdef STM32L5_FLASH_PAGESIZE -# define STM32L5_FLASH_SIZE (STM32L5_FLASH_NPAGES * STM32L5_FLASH_PAGESIZE) +#ifdef STM32_FLASH_PAGESIZE +# define STM32_FLASH_SIZE (STM32_FLASH_NPAGES * STM32_FLASH_PAGESIZE) #endif /* Register Offsets *********************************************************/ -#define STM32L5_FLASH_ACR_OFFSET 0x0000 -#define STM32L5_FLASH_PDKEYR_OFFSET 0x0004 -#define STM32L5_FLASH_NSKEYR_OFFSET 0x0008 -#define STM32L5_FLASH_SECKEYR_OFFSET 0x000c -#define STM32L5_FLASH_OPTKEYR_OFFSET 0x0010 -#define STM32L5_FLASH_LVEKEYR_OFFSET 0x0014 -#define STM32L5_FLASH_NSSR_OFFSET 0x0020 -#define STM32L5_FLASH_SECSR_OFFSET 0x0024 -#define STM32L5_FLASH_NSCR_OFFSET 0x0028 -#define STM32L5_FLASH_SECCR_OFFSET 0x002c -#define STM32L5_FLASH_ECCR_OFFSET 0x0030 -#define STM32L5_FLASH_OPTR_OFFSET 0x0040 -#define STM32L5_FLASH_NSBOOTADDR0R_OFFSET 0x0044 -#define STM32L5_FLASH_NSBOOTADDR1R_OFFSET 0x0048 -#define STM32L5_FLASH_SECBOOTADDR0R_OFFSET 0x004c -#define STM32L5_FLASH_SECWM1R1_OFFSET 0x0050 -#define STM32L5_FLASH_SECWM1R2_OFFSET 0x0054 -#define STM32L5_FLASH_WRP1AR_OFFSET 0x0058 -#define STM32L5_FLASH_WRP1BR_OFFSET 0x005c -#define STM32L5_FLASH_SECWM2R1_OFFSET 0x0060 -#define STM32L5_FLASH_SECWM2R2_OFFSET 0x0064 -#define STM32L5_FLASH_WRP2AR_OFFSET 0x0068 -#define STM32L5_FLASH_WRP2BR_OFFSET 0x006c -#define STM32L5_FLASH_SECBB1R1_OFFSET 0x0080 -#define STM32L5_FLASH_SECBB1R2_OFFSET 0x0084 -#define STM32L5_FLASH_SECBB1R3_OFFSET 0x0088 -#define STM32L5_FLASH_SECBB1R4_OFFSET 0x008c -#define STM32L5_FLASH_SECBB2R1_OFFSET 0x00a0 -#define STM32L5_FLASH_SECBB2R2_OFFSET 0x00a4 -#define STM32L5_FLASH_SECBB2R3_OFFSET 0x00a8 -#define STM32L5_FLASH_SECBB2R4_OFFSET 0x00ac -#define STM32L5_FLASH_SECHDPCR_OFFSET 0x00c0 -#define STM32L5_FLASH_PRIVCFGR_OFFSET 0x00c4 +#define STM32_FLASH_ACR_OFFSET 0x0000 +#define STM32_FLASH_PDKEYR_OFFSET 0x0004 +#define STM32_FLASH_NSKEYR_OFFSET 0x0008 +#define STM32_FLASH_SECKEYR_OFFSET 0x000c +#define STM32_FLASH_OPTKEYR_OFFSET 0x0010 +#define STM32_FLASH_LVEKEYR_OFFSET 0x0014 +#define STM32_FLASH_NSSR_OFFSET 0x0020 +#define STM32_FLASH_SECSR_OFFSET 0x0024 +#define STM32_FLASH_NSCR_OFFSET 0x0028 +#define STM32_FLASH_SECCR_OFFSET 0x002c +#define STM32_FLASH_ECCR_OFFSET 0x0030 +#define STM32_FLASH_OPTR_OFFSET 0x0040 +#define STM32_FLASH_NSBOOTADDR0R_OFFSET 0x0044 +#define STM32_FLASH_NSBOOTADDR1R_OFFSET 0x0048 +#define STM32_FLASH_SECBOOTADDR0R_OFFSET 0x004c +#define STM32_FLASH_SECWM1R1_OFFSET 0x0050 +#define STM32_FLASH_SECWM1R2_OFFSET 0x0054 +#define STM32_FLASH_WRP1AR_OFFSET 0x0058 +#define STM32_FLASH_WRP1BR_OFFSET 0x005c +#define STM32_FLASH_SECWM2R1_OFFSET 0x0060 +#define STM32_FLASH_SECWM2R2_OFFSET 0x0064 +#define STM32_FLASH_WRP2AR_OFFSET 0x0068 +#define STM32_FLASH_WRP2BR_OFFSET 0x006c +#define STM32_FLASH_SECBB1R1_OFFSET 0x0080 +#define STM32_FLASH_SECBB1R2_OFFSET 0x0084 +#define STM32_FLASH_SECBB1R3_OFFSET 0x0088 +#define STM32_FLASH_SECBB1R4_OFFSET 0x008c +#define STM32_FLASH_SECBB2R1_OFFSET 0x00a0 +#define STM32_FLASH_SECBB2R2_OFFSET 0x00a4 +#define STM32_FLASH_SECBB2R3_OFFSET 0x00a8 +#define STM32_FLASH_SECBB2R4_OFFSET 0x00ac +#define STM32_FLASH_SECHDPCR_OFFSET 0x00c0 +#define STM32_FLASH_PRIVCFGR_OFFSET 0x00c4 /* Register Addresses *******************************************************/ -#define STM32L5_FLASH_ACR (STM32L5_FLASHIF_BASE + STM32L5_FLASH_ACR_OFFSET) -#define STM32L5_FLASH_PDKEYR (STM32L5_FLASHIF_BASE + STM32L5_FLASH_PDKEYR_OFFSET) -#define STM32L5_FLASH_NSKEYR (STM32L5_FLASHIF_BASE + STM32L5_FLASH_NSKEYR_OFFSET) -#define STM32L5_FLASH_SECKEYR (STM32L5_FLASHIF_BASE + STM32L5_FLASH_SECKEYR_OFFSET) -#define STM32L5_FLASH_OPTKEYR (STM32L5_FLASHIF_BASE + STM32L5_FLASH_OPTKEYR_OFFSET) -#define STM32L5_FLASH_LVEKEYR (STM32L5_FLASHIF_BASE + STM32L5_FLASH_LVEKEYR_OFFSET) -#define STM32L5_FLASH_NSSR (STM32L5_FLASHIF_BASE + STM32L5_FLASH_NSSR_OFFSET) -#define STM32L5_FLASH_SECSR (STM32L5_FLASHIF_BASE + STM32L5_FLASH_SECSR_OFFSET) -#define STM32L5_FLASH_NSCR (STM32L5_FLASHIF_BASE + STM32L5_FLASH_NSCR_OFFSET) -#define STM32L5_FLASH_SECCR (STM32L5_FLASHIF_BASE + STM32L5_FLASH_SECCR_OFFSET) -#define STM32L5_FLASH_ECCR (STM32L5_FLASHIF_BASE + STM32L5_FLASH_ECCR_OFFSET) -#define STM32L5_FLASH_OPTR (STM32L5_FLASHIF_BASE + STM32L5_FLASH_OPTR_OFFSET) -#define STM32L5_FLASH_NSBOOTADDR0R (STM32L5_FLASHIF_BASE + STM32L5_FLASH_NSBOOTADDR0R_OFFSET) -#define STM32L5_FLASH_NSBOOTADDR1R (STM32L5_FLASHIF_BASE + STM32L5_FLASH_NSBOOTADDR1R_OFFSET) -#define STM32L5_FLASH_SECBOOTADDR0R (STM32L5_FLASHIF_BASE + STM32L5_FLASH_SECBOOTADDR0R_OFFSET) -#define STM32L5_FLASH_SECWM1R1 (STM32L5_FLASHIF_BASE + STM32L5_FLASH_SECWM1R1_OFFSET) -#define STM32L5_FLASH_SECWM1R2 (STM32L5_FLASHIF_BASE + STM32L5_FLASH_SECWM1R2_OFFSET) -#define STM32L5_FLASH_WRP1AR (STM32L5_FLASHIF_BASE + STM32L5_FLASH_WRP1AR_OFFSET) -#define STM32L5_FLASH_WRP1BR (STM32L5_FLASHIF_BASE + STM32L5_FLASH_WRP1BR_OFFSET) -#define STM32L5_FLASH_SECWM2R1 (STM32L5_FLASHIF_BASE + STM32L5_FLASH_SECWM2R1_OFFSET) -#define STM32L5_FLASH_SECWM2R2 (STM32L5_FLASHIF_BASE + STM32L5_FLASH_SECWM2R2_OFFSET) -#define STM32L5_FLASH_WRP2AR (STM32L5_FLASHIF_BASE + STM32L5_FLASH_WRP2AR_OFFSET) -#define STM32L5_FLASH_WRP2BR (STM32L5_FLASHIF_BASE + STM32L5_FLASH_WRP2BR_OFFSET) -#define STM32L5_FLASH_SECBB1R1 (STM32L5_FLASHIF_BASE + STM32L5_FLASH_SECBB1R1_OFFSET) -#define STM32L5_FLASH_SECBB1R2 (STM32L5_FLASHIF_BASE + STM32L5_FLASH_SECBB1R2_OFFSET) -#define STM32L5_FLASH_SECBB1R3 (STM32L5_FLASHIF_BASE + STM32L5_FLASH_SECBB1R3_OFFSET) -#define STM32L5_FLASH_SECBB1R4 (STM32L5_FLASHIF_BASE + STM32L5_FLASH_SECBB1R4_OFFSET) -#define STM32L5_FLASH_SECBB2R1 (STM32L5_FLASHIF_BASE + STM32L5_FLASH_SECBB2R1_OFFSET) -#define STM32L5_FLASH_SECBB2R2 (STM32L5_FLASHIF_BASE + STM32L5_FLASH_SECBB2R2_OFFSET) -#define STM32L5_FLASH_SECBB2R3 (STM32L5_FLASHIF_BASE + STM32L5_FLASH_SECBB2R3_OFFSET) -#define STM32L5_FLASH_SECBB2R4 (STM32L5_FLASHIF_BASE + STM32L5_FLASH_SECBB2R4_OFFSET) -#define STM32L5_FLASH_SECHDPCR (STM32L5_FLASHIF_BASE + STM32L5_FLASH_SECHDPCR_OFFSET) -#define STM32L5_FLASH_PRIVCFGR (STM32L5_FLASHIF_BASE + STM32L5_FLASH_PRIVCFGR_OFFSET) +#define STM32_FLASH_ACR (STM32_FLASHIF_BASE + STM32_FLASH_ACR_OFFSET) +#define STM32_FLASH_PDKEYR (STM32_FLASHIF_BASE + STM32_FLASH_PDKEYR_OFFSET) +#define STM32_FLASH_NSKEYR (STM32_FLASHIF_BASE + STM32_FLASH_NSKEYR_OFFSET) +#define STM32_FLASH_SECKEYR (STM32_FLASHIF_BASE + STM32_FLASH_SECKEYR_OFFSET) +#define STM32_FLASH_OPTKEYR (STM32_FLASHIF_BASE + STM32_FLASH_OPTKEYR_OFFSET) +#define STM32_FLASH_LVEKEYR (STM32_FLASHIF_BASE + STM32_FLASH_LVEKEYR_OFFSET) +#define STM32_FLASH_NSSR (STM32_FLASHIF_BASE + STM32_FLASH_NSSR_OFFSET) +#define STM32_FLASH_SECSR (STM32_FLASHIF_BASE + STM32_FLASH_SECSR_OFFSET) +#define STM32_FLASH_NSCR (STM32_FLASHIF_BASE + STM32_FLASH_NSCR_OFFSET) +#define STM32_FLASH_SECCR (STM32_FLASHIF_BASE + STM32_FLASH_SECCR_OFFSET) +#define STM32_FLASH_ECCR (STM32_FLASHIF_BASE + STM32_FLASH_ECCR_OFFSET) +#define STM32_FLASH_OPTR (STM32_FLASHIF_BASE + STM32_FLASH_OPTR_OFFSET) +#define STM32_FLASH_NSBOOTADDR0R (STM32_FLASHIF_BASE + STM32_FLASH_NSBOOTADDR0R_OFFSET) +#define STM32_FLASH_NSBOOTADDR1R (STM32_FLASHIF_BASE + STM32_FLASH_NSBOOTADDR1R_OFFSET) +#define STM32_FLASH_SECBOOTADDR0R (STM32_FLASHIF_BASE + STM32_FLASH_SECBOOTADDR0R_OFFSET) +#define STM32_FLASH_SECWM1R1 (STM32_FLASHIF_BASE + STM32_FLASH_SECWM1R1_OFFSET) +#define STM32_FLASH_SECWM1R2 (STM32_FLASHIF_BASE + STM32_FLASH_SECWM1R2_OFFSET) +#define STM32_FLASH_WRP1AR (STM32_FLASHIF_BASE + STM32_FLASH_WRP1AR_OFFSET) +#define STM32_FLASH_WRP1BR (STM32_FLASHIF_BASE + STM32_FLASH_WRP1BR_OFFSET) +#define STM32_FLASH_SECWM2R1 (STM32_FLASHIF_BASE + STM32_FLASH_SECWM2R1_OFFSET) +#define STM32_FLASH_SECWM2R2 (STM32_FLASHIF_BASE + STM32_FLASH_SECWM2R2_OFFSET) +#define STM32_FLASH_WRP2AR (STM32_FLASHIF_BASE + STM32_FLASH_WRP2AR_OFFSET) +#define STM32_FLASH_WRP2BR (STM32_FLASHIF_BASE + STM32_FLASH_WRP2BR_OFFSET) +#define STM32_FLASH_SECBB1R1 (STM32_FLASHIF_BASE + STM32_FLASH_SECBB1R1_OFFSET) +#define STM32_FLASH_SECBB1R2 (STM32_FLASHIF_BASE + STM32_FLASH_SECBB1R2_OFFSET) +#define STM32_FLASH_SECBB1R3 (STM32_FLASHIF_BASE + STM32_FLASH_SECBB1R3_OFFSET) +#define STM32_FLASH_SECBB1R4 (STM32_FLASHIF_BASE + STM32_FLASH_SECBB1R4_OFFSET) +#define STM32_FLASH_SECBB2R1 (STM32_FLASHIF_BASE + STM32_FLASH_SECBB2R1_OFFSET) +#define STM32_FLASH_SECBB2R2 (STM32_FLASHIF_BASE + STM32_FLASH_SECBB2R2_OFFSET) +#define STM32_FLASH_SECBB2R3 (STM32_FLASHIF_BASE + STM32_FLASH_SECBB2R3_OFFSET) +#define STM32_FLASH_SECBB2R4 (STM32_FLASHIF_BASE + STM32_FLASH_SECBB2R4_OFFSET) +#define STM32_FLASH_SECHDPCR (STM32_FLASHIF_BASE + STM32_FLASH_SECHDPCR_OFFSET) +#define STM32_FLASH_PRIVCFGR (STM32_FLASHIF_BASE + STM32_FLASH_PRIVCFGR_OFFSET) /* Register Bitfield Definitions ********************************************/ diff --git a/arch/arm/src/stm32l5/hardware/stm32l5_gpio.h b/arch/arm/src/stm32l5/hardware/stm32l5_gpio.h index 0037ae1ad08d3..d5b62cbf07ade 100644 --- a/arch/arm/src/stm32l5/hardware/stm32l5_gpio.h +++ b/arch/arm/src/stm32l5/hardware/stm32l5_gpio.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32L5_GPIO_H -#define __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32L5_GPIO_H +#ifndef __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32_GPIO_H +#define __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32_GPIO_H /**************************************************************************** * Included Files @@ -36,154 +36,154 @@ /* Register Offsets *********************************************************/ -#define STM32L5_GPIO_MODER_OFFSET 0x0000 /* GPIO port mode register */ -#define STM32L5_GPIO_OTYPER_OFFSET 0x0004 /* GPIO port output type register */ -#define STM32L5_GPIO_OSPEED_OFFSET 0x0008 /* GPIO port output speed register */ -#define STM32L5_GPIO_PUPDR_OFFSET 0x000c /* GPIO port pull-up/pull-down register */ -#define STM32L5_GPIO_IDR_OFFSET 0x0010 /* GPIO port input data register */ -#define STM32L5_GPIO_ODR_OFFSET 0x0014 /* GPIO port output data register */ -#define STM32L5_GPIO_BSRR_OFFSET 0x0018 /* GPIO port bit set/reset register */ -#define STM32L5_GPIO_LCKR_OFFSET 0x001c /* GPIO port configuration lock register */ -#define STM32L5_GPIO_AFRL_OFFSET 0x0020 /* GPIO alternate function low register */ -#define STM32L5_GPIO_AFRH_OFFSET 0x0024 /* GPIO alternate function high register */ -#define STM32L5_GPIO_BRR_OFFSET 0x0028 /* GPIO port bit reset register */ -#define STM32L5_GPIO_SECCFGR_OFFSET 0x0030 /* GPIO secure configuration register */ +#define STM32_GPIO_MODER_OFFSET 0x0000 /* GPIO port mode register */ +#define STM32_GPIO_OTYPER_OFFSET 0x0004 /* GPIO port output type register */ +#define STM32_GPIO_OSPEED_OFFSET 0x0008 /* GPIO port output speed register */ +#define STM32_GPIO_PUPDR_OFFSET 0x000c /* GPIO port pull-up/pull-down register */ +#define STM32_GPIO_IDR_OFFSET 0x0010 /* GPIO port input data register */ +#define STM32_GPIO_ODR_OFFSET 0x0014 /* GPIO port output data register */ +#define STM32_GPIO_BSRR_OFFSET 0x0018 /* GPIO port bit set/reset register */ +#define STM32_GPIO_LCKR_OFFSET 0x001c /* GPIO port configuration lock register */ +#define STM32_GPIO_AFRL_OFFSET 0x0020 /* GPIO alternate function low register */ +#define STM32_GPIO_AFRH_OFFSET 0x0024 /* GPIO alternate function high register */ +#define STM32_GPIO_BRR_OFFSET 0x0028 /* GPIO port bit reset register */ +#define STM32_GPIO_SECCFGR_OFFSET 0x0030 /* GPIO secure configuration register */ /* Register Addresses *******************************************************/ -#if STM32L5_NPORTS > 0 -# define STM32L5_GPIOA_MODER (STM32L5_GPIOA_BASE + STM32L5_GPIO_MODER_OFFSET) -# define STM32L5_GPIOA_OTYPER (STM32L5_GPIOA_BASE + STM32L5_GPIO_OTYPER_OFFSET) -# define STM32L5_GPIOA_OSPEED (STM32L5_GPIOA_BASE + STM32L5_GPIO_OSPEED_OFFSET) -# define STM32L5_GPIOA_PUPDR (STM32L5_GPIOA_BASE + STM32L5_GPIO_PUPDR_OFFSET) -# define STM32L5_GPIOA_IDR (STM32L5_GPIOA_BASE + STM32L5_GPIO_IDR_OFFSET) -# define STM32L5_GPIOA_ODR (STM32L5_GPIOA_BASE + STM32L5_GPIO_ODR_OFFSET) -# define STM32L5_GPIOA_BSRR (STM32L5_GPIOA_BASE + STM32L5_GPIO_BSRR_OFFSET) -# define STM32L5_GPIOA_LCKR (STM32L5_GPIOA_BASE + STM32L5_GPIO_LCKR_OFFSET) -# define STM32L5_GPIOA_AFRL (STM32L5_GPIOA_BASE + STM32L5_GPIO_AFRL_OFFSET) -# define STM32L5_GPIOA_AFRH (STM32L5_GPIOA_BASE + STM32L5_GPIO_AFRH_OFFSET) -# define STM32L5_GPIOA_BRR (STM32L5_GPIOA_BASE + STM32L5_GPIO_BRR_OFFSET) -# define STM32L5_GPIOA_SECCFGR (STM32L5_GPIOA_BASE + STM32L5_GPIO_SECCFGR_OFFSET) +#if STM32_NPORTS > 0 +# define STM32_GPIOA_MODER (STM32_GPIOA_BASE + STM32_GPIO_MODER_OFFSET) +# define STM32_GPIOA_OTYPER (STM32_GPIOA_BASE + STM32_GPIO_OTYPER_OFFSET) +# define STM32_GPIOA_OSPEED (STM32_GPIOA_BASE + STM32_GPIO_OSPEED_OFFSET) +# define STM32_GPIOA_PUPDR (STM32_GPIOA_BASE + STM32_GPIO_PUPDR_OFFSET) +# define STM32_GPIOA_IDR (STM32_GPIOA_BASE + STM32_GPIO_IDR_OFFSET) +# define STM32_GPIOA_ODR (STM32_GPIOA_BASE + STM32_GPIO_ODR_OFFSET) +# define STM32_GPIOA_BSRR (STM32_GPIOA_BASE + STM32_GPIO_BSRR_OFFSET) +# define STM32_GPIOA_LCKR (STM32_GPIOA_BASE + STM32_GPIO_LCKR_OFFSET) +# define STM32_GPIOA_AFRL (STM32_GPIOA_BASE + STM32_GPIO_AFRL_OFFSET) +# define STM32_GPIOA_AFRH (STM32_GPIOA_BASE + STM32_GPIO_AFRH_OFFSET) +# define STM32_GPIOA_BRR (STM32_GPIOA_BASE + STM32_GPIO_BRR_OFFSET) +# define STM32_GPIOA_SECCFGR (STM32_GPIOA_BASE + STM32_GPIO_SECCFGR_OFFSET) #endif -#if STM32L5_NPORTS > 1 -# define STM32L5_GPIOB_MODER (STM32L5_GPIOB_BASE + STM32L5_GPIO_MODER_OFFSET) -# define STM32L5_GPIOB_OTYPER (STM32L5_GPIOB_BASE + STM32L5_GPIO_OTYPER_OFFSET) -# define STM32L5_GPIOB_OSPEED (STM32L5_GPIOB_BASE + STM32L5_GPIO_OSPEED_OFFSET) -# define STM32L5_GPIOB_PUPDR (STM32L5_GPIOB_BASE + STM32L5_GPIO_PUPDR_OFFSET) -# define STM32L5_GPIOB_IDR (STM32L5_GPIOB_BASE + STM32L5_GPIO_IDR_OFFSET) -# define STM32L5_GPIOB_ODR (STM32L5_GPIOB_BASE + STM32L5_GPIO_ODR_OFFSET) -# define STM32L5_GPIOB_BSRR (STM32L5_GPIOB_BASE + STM32L5_GPIO_BSRR_OFFSET) -# define STM32L5_GPIOB_LCKR (STM32L5_GPIOB_BASE + STM32L5_GPIO_LCKR_OFFSET) -# define STM32L5_GPIOB_AFRL (STM32L5_GPIOB_BASE + STM32L5_GPIO_AFRL_OFFSET) -# define STM32L5_GPIOB_AFRH (STM32L5_GPIOB_BASE + STM32L5_GPIO_AFRH_OFFSET) -# define STM32L5_GPIOB_BRR (STM32L5_GPIOB_BASE + STM32L5_GPIO_BRR_OFFSET) -# define STM32L5_GPIOB_SECCFGR (STM32L5_GPIOB_BASE + STM32L5_GPIO_SECCFGR_OFFSET) +#if STM32_NPORTS > 1 +# define STM32_GPIOB_MODER (STM32_GPIOB_BASE + STM32_GPIO_MODER_OFFSET) +# define STM32_GPIOB_OTYPER (STM32_GPIOB_BASE + STM32_GPIO_OTYPER_OFFSET) +# define STM32_GPIOB_OSPEED (STM32_GPIOB_BASE + STM32_GPIO_OSPEED_OFFSET) +# define STM32_GPIOB_PUPDR (STM32_GPIOB_BASE + STM32_GPIO_PUPDR_OFFSET) +# define STM32_GPIOB_IDR (STM32_GPIOB_BASE + STM32_GPIO_IDR_OFFSET) +# define STM32_GPIOB_ODR (STM32_GPIOB_BASE + STM32_GPIO_ODR_OFFSET) +# define STM32_GPIOB_BSRR (STM32_GPIOB_BASE + STM32_GPIO_BSRR_OFFSET) +# define STM32_GPIOB_LCKR (STM32_GPIOB_BASE + STM32_GPIO_LCKR_OFFSET) +# define STM32_GPIOB_AFRL (STM32_GPIOB_BASE + STM32_GPIO_AFRL_OFFSET) +# define STM32_GPIOB_AFRH (STM32_GPIOB_BASE + STM32_GPIO_AFRH_OFFSET) +# define STM32_GPIOB_BRR (STM32_GPIOB_BASE + STM32_GPIO_BRR_OFFSET) +# define STM32_GPIOB_SECCFGR (STM32_GPIOB_BASE + STM32_GPIO_SECCFGR_OFFSET) #endif -#if STM32L5_NPORTS > 2 -# define STM32L5_GPIOC_MODER (STM32L5_GPIOC_BASE + STM32L5_GPIO_MODER_OFFSET) -# define STM32L5_GPIOC_OTYPER (STM32L5_GPIOC_BASE + STM32L5_GPIO_OTYPER_OFFSET) -# define STM32L5_GPIOC_OSPEED (STM32L5_GPIOC_BASE + STM32L5_GPIO_OSPEED_OFFSET) -# define STM32L5_GPIOC_PUPDR (STM32L5_GPIOC_BASE + STM32L5_GPIO_PUPDR_OFFSET) -# define STM32L5_GPIOC_IDR (STM32L5_GPIOC_BASE + STM32L5_GPIO_IDR_OFFSET) -# define STM32L5_GPIOC_ODR (STM32L5_GPIOC_BASE + STM32L5_GPIO_ODR_OFFSET) -# define STM32L5_GPIOC_BSRR (STM32L5_GPIOC_BASE + STM32L5_GPIO_BSRR_OFFSET) -# define STM32L5_GPIOC_LCKR (STM32L5_GPIOC_BASE + STM32L5_GPIO_LCKR_OFFSET) -# define STM32L5_GPIOC_AFRL (STM32L5_GPIOC_BASE + STM32L5_GPIO_AFRL_OFFSET) -# define STM32L5_GPIOC_AFRH (STM32L5_GPIOC_BASE + STM32L5_GPIO_AFRH_OFFSET) -# define STM32L5_GPIOC_BRR (STM32L5_GPIOC_BASE + STM32L5_GPIO_BRR_OFFSET) -# define STM32L5_GPIOC_SECCFGR (STM32L5_GPIOC_BASE + STM32L5_GPIO_SECCFGR_OFFSET) +#if STM32_NPORTS > 2 +# define STM32_GPIOC_MODER (STM32_GPIOC_BASE + STM32_GPIO_MODER_OFFSET) +# define STM32_GPIOC_OTYPER (STM32_GPIOC_BASE + STM32_GPIO_OTYPER_OFFSET) +# define STM32_GPIOC_OSPEED (STM32_GPIOC_BASE + STM32_GPIO_OSPEED_OFFSET) +# define STM32_GPIOC_PUPDR (STM32_GPIOC_BASE + STM32_GPIO_PUPDR_OFFSET) +# define STM32_GPIOC_IDR (STM32_GPIOC_BASE + STM32_GPIO_IDR_OFFSET) +# define STM32_GPIOC_ODR (STM32_GPIOC_BASE + STM32_GPIO_ODR_OFFSET) +# define STM32_GPIOC_BSRR (STM32_GPIOC_BASE + STM32_GPIO_BSRR_OFFSET) +# define STM32_GPIOC_LCKR (STM32_GPIOC_BASE + STM32_GPIO_LCKR_OFFSET) +# define STM32_GPIOC_AFRL (STM32_GPIOC_BASE + STM32_GPIO_AFRL_OFFSET) +# define STM32_GPIOC_AFRH (STM32_GPIOC_BASE + STM32_GPIO_AFRH_OFFSET) +# define STM32_GPIOC_BRR (STM32_GPIOC_BASE + STM32_GPIO_BRR_OFFSET) +# define STM32_GPIOC_SECCFGR (STM32_GPIOC_BASE + STM32_GPIO_SECCFGR_OFFSET) #endif -#if STM32L5_NPORTS > 3 -# define STM32L5_GPIOD_MODER (STM32L5_GPIOD_BASE + STM32L5_GPIO_MODER_OFFSET) -# define STM32L5_GPIOD_OTYPER (STM32L5_GPIOD_BASE + STM32L5_GPIO_OTYPER_OFFSET) -# define STM32L5_GPIOD_OSPEED (STM32L5_GPIOD_BASE + STM32L5_GPIO_OSPEED_OFFSET) -# define STM32L5_GPIOD_PUPDR (STM32L5_GPIOD_BASE + STM32L5_GPIO_PUPDR_OFFSET) -# define STM32L5_GPIOD_IDR (STM32L5_GPIOD_BASE + STM32L5_GPIO_IDR_OFFSET) -# define STM32L5_GPIOD_ODR (STM32L5_GPIOD_BASE + STM32L5_GPIO_ODR_OFFSET) -# define STM32L5_GPIOD_BSRR (STM32L5_GPIOD_BASE + STM32L5_GPIO_BSRR_OFFSET) -# define STM32L5_GPIOD_LCKR (STM32L5_GPIOD_BASE + STM32L5_GPIO_LCKR_OFFSET) -# define STM32L5_GPIOD_AFRL (STM32L5_GPIOD_BASE + STM32L5_GPIO_AFRL_OFFSET) -# define STM32L5_GPIOD_AFRH (STM32L5_GPIOD_BASE + STM32L5_GPIO_AFRH_OFFSET) -# define STM32L5_GPIOD_BRR (STM32L5_GPIOD_BASE + STM32L5_GPIO_BRR_OFFSET) -# define STM32L5_GPIOD_SECCFGR (STM32L5_GPIOD_BASE + STM32L5_GPIO_SECCFGR_OFFSET) +#if STM32_NPORTS > 3 +# define STM32_GPIOD_MODER (STM32_GPIOD_BASE + STM32_GPIO_MODER_OFFSET) +# define STM32_GPIOD_OTYPER (STM32_GPIOD_BASE + STM32_GPIO_OTYPER_OFFSET) +# define STM32_GPIOD_OSPEED (STM32_GPIOD_BASE + STM32_GPIO_OSPEED_OFFSET) +# define STM32_GPIOD_PUPDR (STM32_GPIOD_BASE + STM32_GPIO_PUPDR_OFFSET) +# define STM32_GPIOD_IDR (STM32_GPIOD_BASE + STM32_GPIO_IDR_OFFSET) +# define STM32_GPIOD_ODR (STM32_GPIOD_BASE + STM32_GPIO_ODR_OFFSET) +# define STM32_GPIOD_BSRR (STM32_GPIOD_BASE + STM32_GPIO_BSRR_OFFSET) +# define STM32_GPIOD_LCKR (STM32_GPIOD_BASE + STM32_GPIO_LCKR_OFFSET) +# define STM32_GPIOD_AFRL (STM32_GPIOD_BASE + STM32_GPIO_AFRL_OFFSET) +# define STM32_GPIOD_AFRH (STM32_GPIOD_BASE + STM32_GPIO_AFRH_OFFSET) +# define STM32_GPIOD_BRR (STM32_GPIOD_BASE + STM32_GPIO_BRR_OFFSET) +# define STM32_GPIOD_SECCFGR (STM32_GPIOD_BASE + STM32_GPIO_SECCFGR_OFFSET) #endif -#if STM32L5_NPORTS > 4 -# define STM32L5_GPIOE_MODER (STM32L5_GPIOE_BASE + STM32L5_GPIO_MODER_OFFSET) -# define STM32L5_GPIOE_OTYPER (STM32L5_GPIOE_BASE + STM32L5_GPIO_OTYPER_OFFSET) -# define STM32L5_GPIOE_OSPEED (STM32L5_GPIOE_BASE + STM32L5_GPIO_OSPEED_OFFSET) -# define STM32L5_GPIOE_PUPDR (STM32L5_GPIOE_BASE + STM32L5_GPIO_PUPDR_OFFSET) -# define STM32L5_GPIOE_IDR (STM32L5_GPIOE_BASE + STM32L5_GPIO_IDR_OFFSET) -# define STM32L5_GPIOE_ODR (STM32L5_GPIOE_BASE + STM32L5_GPIO_ODR_OFFSET) -# define STM32L5_GPIOE_BSRR (STM32L5_GPIOE_BASE + STM32L5_GPIO_BSRR_OFFSET) -# define STM32L5_GPIOE_LCKR (STM32L5_GPIOE_BASE + STM32L5_GPIO_LCKR_OFFSET) -# define STM32L5_GPIOE_AFRL (STM32L5_GPIOE_BASE + STM32L5_GPIO_AFRL_OFFSET) -# define STM32L5_GPIOE_AFRH (STM32L5_GPIOE_BASE + STM32L5_GPIO_AFRH_OFFSET) -# define STM32L5_GPIOE_BRR (STM32L5_GPIOE_BASE + STM32L5_GPIO_BRR_OFFSET) -# define STM32L5_GPIOE_SECCFGR (STM32L5_GPIOE_BASE + STM32L5_GPIO_SECCFGR_OFFSET) +#if STM32_NPORTS > 4 +# define STM32_GPIOE_MODER (STM32_GPIOE_BASE + STM32_GPIO_MODER_OFFSET) +# define STM32_GPIOE_OTYPER (STM32_GPIOE_BASE + STM32_GPIO_OTYPER_OFFSET) +# define STM32_GPIOE_OSPEED (STM32_GPIOE_BASE + STM32_GPIO_OSPEED_OFFSET) +# define STM32_GPIOE_PUPDR (STM32_GPIOE_BASE + STM32_GPIO_PUPDR_OFFSET) +# define STM32_GPIOE_IDR (STM32_GPIOE_BASE + STM32_GPIO_IDR_OFFSET) +# define STM32_GPIOE_ODR (STM32_GPIOE_BASE + STM32_GPIO_ODR_OFFSET) +# define STM32_GPIOE_BSRR (STM32_GPIOE_BASE + STM32_GPIO_BSRR_OFFSET) +# define STM32_GPIOE_LCKR (STM32_GPIOE_BASE + STM32_GPIO_LCKR_OFFSET) +# define STM32_GPIOE_AFRL (STM32_GPIOE_BASE + STM32_GPIO_AFRL_OFFSET) +# define STM32_GPIOE_AFRH (STM32_GPIOE_BASE + STM32_GPIO_AFRH_OFFSET) +# define STM32_GPIOE_BRR (STM32_GPIOE_BASE + STM32_GPIO_BRR_OFFSET) +# define STM32_GPIOE_SECCFGR (STM32_GPIOE_BASE + STM32_GPIO_SECCFGR_OFFSET) #endif -#if STM32L5_NPORTS > 5 -# define STM32L5_GPIOF_MODER (STM32L5_GPIOF_BASE + STM32L5_GPIO_MODER_OFFSET) -# define STM32L5_GPIOF_OTYPER (STM32L5_GPIOF_BASE + STM32L5_GPIO_OTYPER_OFFSET) -# define STM32L5_GPIOF_OSPEED (STM32L5_GPIOF_BASE + STM32L5_GPIO_OSPEED_OFFSET) -# define STM32L5_GPIOF_PUPDR (STM32L5_GPIOF_BASE + STM32L5_GPIO_PUPDR_OFFSET) -# define STM32L5_GPIOF_IDR (STM32L5_GPIOF_BASE + STM32L5_GPIO_IDR_OFFSET) -# define STM32L5_GPIOF_ODR (STM32L5_GPIOF_BASE + STM32L5_GPIO_ODR_OFFSET) -# define STM32L5_GPIOF_BSRR (STM32L5_GPIOF_BASE + STM32L5_GPIO_BSRR_OFFSET) -# define STM32L5_GPIOF_LCKR (STM32L5_GPIOF_BASE + STM32L5_GPIO_LCKR_OFFSET) -# define STM32L5_GPIOF_AFRL (STM32L5_GPIOF_BASE + STM32L5_GPIO_AFRL_OFFSET) -# define STM32L5_GPIOF_AFRH (STM32L5_GPIOF_BASE + STM32L5_GPIO_AFRH_OFFSET) -# define STM32L5_GPIOF_BRR (STM32L5_GPIOF_BASE + STM32L5_GPIO_BRR_OFFSET) -# define STM32L5_GPIOF_SECCFGR (STM32L5_GPIOF_BASE + STM32L5_GPIO_SECCFGR_OFFSET) +#if STM32_NPORTS > 5 +# define STM32_GPIOF_MODER (STM32_GPIOF_BASE + STM32_GPIO_MODER_OFFSET) +# define STM32_GPIOF_OTYPER (STM32_GPIOF_BASE + STM32_GPIO_OTYPER_OFFSET) +# define STM32_GPIOF_OSPEED (STM32_GPIOF_BASE + STM32_GPIO_OSPEED_OFFSET) +# define STM32_GPIOF_PUPDR (STM32_GPIOF_BASE + STM32_GPIO_PUPDR_OFFSET) +# define STM32_GPIOF_IDR (STM32_GPIOF_BASE + STM32_GPIO_IDR_OFFSET) +# define STM32_GPIOF_ODR (STM32_GPIOF_BASE + STM32_GPIO_ODR_OFFSET) +# define STM32_GPIOF_BSRR (STM32_GPIOF_BASE + STM32_GPIO_BSRR_OFFSET) +# define STM32_GPIOF_LCKR (STM32_GPIOF_BASE + STM32_GPIO_LCKR_OFFSET) +# define STM32_GPIOF_AFRL (STM32_GPIOF_BASE + STM32_GPIO_AFRL_OFFSET) +# define STM32_GPIOF_AFRH (STM32_GPIOF_BASE + STM32_GPIO_AFRH_OFFSET) +# define STM32_GPIOF_BRR (STM32_GPIOF_BASE + STM32_GPIO_BRR_OFFSET) +# define STM32_GPIOF_SECCFGR (STM32_GPIOF_BASE + STM32_GPIO_SECCFGR_OFFSET) #endif -#if STM32L5_NPORTS > 6 -# define STM32L5_GPIOG_MODER (STM32L5_GPIOG_BASE + STM32L5_GPIO_MODER_OFFSET) -# define STM32L5_GPIOG_OTYPER (STM32L5_GPIOG_BASE + STM32L5_GPIO_OTYPER_OFFSET) -# define STM32L5_GPIOG_OSPEED (STM32L5_GPIOG_BASE + STM32L5_GPIO_OSPEED_OFFSET) -# define STM32L5_GPIOG_PUPDR (STM32L5_GPIOG_BASE + STM32L5_GPIO_PUPDR_OFFSET) -# define STM32L5_GPIOG_IDR (STM32L5_GPIOG_BASE + STM32L5_GPIO_IDR_OFFSET) -# define STM32L5_GPIOG_ODR (STM32L5_GPIOG_BASE + STM32L5_GPIO_ODR_OFFSET) -# define STM32L5_GPIOG_BSRR (STM32L5_GPIOG_BASE + STM32L5_GPIO_BSRR_OFFSET) -# define STM32L5_GPIOG_LCKR (STM32L5_GPIOG_BASE + STM32L5_GPIO_LCKR_OFFSET) -# define STM32L5_GPIOG_AFRL (STM32L5_GPIOG_BASE + STM32L5_GPIO_AFRL_OFFSET) -# define STM32L5_GPIOG_AFRH (STM32L5_GPIOG_BASE + STM32L5_GPIO_AFRH_OFFSET) -# define STM32L5_GPIOG_BRR (STM32L5_GPIOG_BASE + STM32L5_GPIO_BRR_OFFSET) -# define STM32L5_GPIOG_SECCFGR (STM32L5_GPIOG_BASE + STM32L5_GPIO_SECCFGR_OFFSET) +#if STM32_NPORTS > 6 +# define STM32_GPIOG_MODER (STM32_GPIOG_BASE + STM32_GPIO_MODER_OFFSET) +# define STM32_GPIOG_OTYPER (STM32_GPIOG_BASE + STM32_GPIO_OTYPER_OFFSET) +# define STM32_GPIOG_OSPEED (STM32_GPIOG_BASE + STM32_GPIO_OSPEED_OFFSET) +# define STM32_GPIOG_PUPDR (STM32_GPIOG_BASE + STM32_GPIO_PUPDR_OFFSET) +# define STM32_GPIOG_IDR (STM32_GPIOG_BASE + STM32_GPIO_IDR_OFFSET) +# define STM32_GPIOG_ODR (STM32_GPIOG_BASE + STM32_GPIO_ODR_OFFSET) +# define STM32_GPIOG_BSRR (STM32_GPIOG_BASE + STM32_GPIO_BSRR_OFFSET) +# define STM32_GPIOG_LCKR (STM32_GPIOG_BASE + STM32_GPIO_LCKR_OFFSET) +# define STM32_GPIOG_AFRL (STM32_GPIOG_BASE + STM32_GPIO_AFRL_OFFSET) +# define STM32_GPIOG_AFRH (STM32_GPIOG_BASE + STM32_GPIO_AFRH_OFFSET) +# define STM32_GPIOG_BRR (STM32_GPIOG_BASE + STM32_GPIO_BRR_OFFSET) +# define STM32_GPIOG_SECCFGR (STM32_GPIOG_BASE + STM32_GPIO_SECCFGR_OFFSET) #endif -#if STM32L5_NPORTS > 7 -# define STM32L5_GPIOH_MODER (STM32L5_GPIOH_BASE + STM32L5_GPIO_MODER_OFFSET) -# define STM32L5_GPIOH_OTYPER (STM32L5_GPIOH_BASE + STM32L5_GPIO_OTYPER_OFFSET) -# define STM32L5_GPIOH_OSPEED (STM32L5_GPIOH_BASE + STM32L5_GPIO_OSPEED_OFFSET) -# define STM32L5_GPIOH_PUPDR (STM32L5_GPIOH_BASE + STM32L5_GPIO_PUPDR_OFFSET) -# define STM32L5_GPIOH_IDR (STM32L5_GPIOH_BASE + STM32L5_GPIO_IDR_OFFSET) -# define STM32L5_GPIOH_ODR (STM32L5_GPIOH_BASE + STM32L5_GPIO_ODR_OFFSET) -# define STM32L5_GPIOH_BSRR (STM32L5_GPIOH_BASE + STM32L5_GPIO_BSRR_OFFSET) -# define STM32L5_GPIOH_LCKR (STM32L5_GPIOH_BASE + STM32L5_GPIO_LCKR_OFFSET) -# define STM32L5_GPIOH_AFRL (STM32L5_GPIOH_BASE + STM32L5_GPIO_AFRL_OFFSET) -# define STM32L5_GPIOH_AFRH (STM32L5_GPIOH_BASE + STM32L5_GPIO_AFRH_OFFSET) -# define STM32L5_GPIOH_BRR (STM32L5_GPIOH_BASE + STM32L5_GPIO_BRR_OFFSET) -# define STM32L5_GPIOH_SECCFGR (STM32L5_GPIOH_BASE + STM32L5_GPIO_SECCFGR_OFFSET) +#if STM32_NPORTS > 7 +# define STM32_GPIOH_MODER (STM32_GPIOH_BASE + STM32_GPIO_MODER_OFFSET) +# define STM32_GPIOH_OTYPER (STM32_GPIOH_BASE + STM32_GPIO_OTYPER_OFFSET) +# define STM32_GPIOH_OSPEED (STM32_GPIOH_BASE + STM32_GPIO_OSPEED_OFFSET) +# define STM32_GPIOH_PUPDR (STM32_GPIOH_BASE + STM32_GPIO_PUPDR_OFFSET) +# define STM32_GPIOH_IDR (STM32_GPIOH_BASE + STM32_GPIO_IDR_OFFSET) +# define STM32_GPIOH_ODR (STM32_GPIOH_BASE + STM32_GPIO_ODR_OFFSET) +# define STM32_GPIOH_BSRR (STM32_GPIOH_BASE + STM32_GPIO_BSRR_OFFSET) +# define STM32_GPIOH_LCKR (STM32_GPIOH_BASE + STM32_GPIO_LCKR_OFFSET) +# define STM32_GPIOH_AFRL (STM32_GPIOH_BASE + STM32_GPIO_AFRL_OFFSET) +# define STM32_GPIOH_AFRH (STM32_GPIOH_BASE + STM32_GPIO_AFRH_OFFSET) +# define STM32_GPIOH_BRR (STM32_GPIOH_BASE + STM32_GPIO_BRR_OFFSET) +# define STM32_GPIOH_SECCFGR (STM32_GPIOH_BASE + STM32_GPIO_SECCFGR_OFFSET) #endif -#if STM32L5_NPORTS > 8 -# define STM32L5_GPIOI_MODER (STM32L5_GPIOI_BASE + STM32L5_GPIO_MODER_OFFSET) -# define STM32L5_GPIOI_OTYPER (STM32L5_GPIOI_BASE + STM32L5_GPIO_OTYPER_OFFSET) -# define STM32L5_GPIOI_OSPEED (STM32L5_GPIOI_BASE + STM32L5_GPIO_OSPEED_OFFSET) -# define STM32L5_GPIOI_PUPDR (STM32L5_GPIOI_BASE + STM32L5_GPIO_PUPDR_OFFSET) -# define STM32L5_GPIOI_IDR (STM32L5_GPIOI_BASE + STM32L5_GPIO_IDR_OFFSET) -# define STM32L5_GPIOI_ODR (STM32L5_GPIOI_BASE + STM32L5_GPIO_ODR_OFFSET) -# define STM32L5_GPIOI_BSRR (STM32L5_GPIOI_BASE + STM32L5_GPIO_BSRR_OFFSET) -# define STM32L5_GPIOI_LCKR (STM32L5_GPIOI_BASE + STM32L5_GPIO_LCKR_OFFSET) -# define STM32L5_GPIOI_AFRL (STM32L5_GPIOI_BASE + STM32L5_GPIO_AFRL_OFFSET) -# define STM32L5_GPIOI_AFRH (STM32L5_GPIOI_BASE + STM32L5_GPIO_AFRH_OFFSET) -# define STM32L5_GPIOI_BRR (STM32L5_GPIOI_BASE + STM32L5_GPIO_BRR_OFFSET) -# define STM32L5_GPIOI_SECCFGR (STM32L5_GPIOI_BASE + STM32L5_GPIO_SECCFGR_OFFSET) +#if STM32_NPORTS > 8 +# define STM32_GPIOI_MODER (STM32_GPIOI_BASE + STM32_GPIO_MODER_OFFSET) +# define STM32_GPIOI_OTYPER (STM32_GPIOI_BASE + STM32_GPIO_OTYPER_OFFSET) +# define STM32_GPIOI_OSPEED (STM32_GPIOI_BASE + STM32_GPIO_OSPEED_OFFSET) +# define STM32_GPIOI_PUPDR (STM32_GPIOI_BASE + STM32_GPIO_PUPDR_OFFSET) +# define STM32_GPIOI_IDR (STM32_GPIOI_BASE + STM32_GPIO_IDR_OFFSET) +# define STM32_GPIOI_ODR (STM32_GPIOI_BASE + STM32_GPIO_ODR_OFFSET) +# define STM32_GPIOI_BSRR (STM32_GPIOI_BASE + STM32_GPIO_BSRR_OFFSET) +# define STM32_GPIOI_LCKR (STM32_GPIOI_BASE + STM32_GPIO_LCKR_OFFSET) +# define STM32_GPIOI_AFRL (STM32_GPIOI_BASE + STM32_GPIO_AFRL_OFFSET) +# define STM32_GPIOI_AFRH (STM32_GPIOI_BASE + STM32_GPIO_AFRH_OFFSET) +# define STM32_GPIOI_BRR (STM32_GPIOI_BASE + STM32_GPIO_BRR_OFFSET) +# define STM32_GPIOI_SECCFGR (STM32_GPIOI_BASE + STM32_GPIO_SECCFGR_OFFSET) #endif /* Register Bitfield Definitions ********************************************/ @@ -386,4 +386,4 @@ #define GPIO_SECCFGR_SET(n) (1 << (n)) -#endif /* __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32L5_GPIO_H */ +#endif /* __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32_GPIO_H */ diff --git a/arch/arm/src/stm32l5/hardware/stm32l5_memorymap.h b/arch/arm/src/stm32l5/hardware/stm32l5_memorymap.h index 4fefb89201fed..302e8426cb9b6 100644 --- a/arch/arm/src/stm32l5/hardware/stm32l5_memorymap.h +++ b/arch/arm/src/stm32l5/hardware/stm32l5_memorymap.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32L5_MEMORYMAP_H -#define __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32L5_MEMORYMAP_H +#ifndef __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32_MEMORYMAP_H +#define __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32_MEMORYMAP_H /**************************************************************************** * Pre-processor Definitions @@ -29,127 +29,127 @@ /* STM32L5XXX Address Blocks ************************************************/ -#define STM32L5_CODE_BASE 0x00000000 /* 0x00000000-0x1fffffff: 512Mb code block */ -#define STM32L5_SRAM_BASE 0x20000000 /* 0x20000000-0x3fffffff: 512Mb sram block (48k to 256k) */ -#define STM32L5_PERIPH_BASE 0x40000000 /* 0x40000000-0x5fffffff: 512Mb peripheral block */ -#define STM32L5_FSMC_BASE12 0x60000000 /* 0x60000000-0x7fffffff: 512Mb FSMC bank1&2 block */ -# define STM32L5_FMC_BANK1 0x60000000 /* 0x60000000-0x6fffffff: 256Mb NOR/SRAM */ -#define STM32L5_FSMC_BASE34 0x80000000 /* 0x80000000-0x8fffffff: 512Mb FSMC bank3 / QSPI block */ -# define STM32L5_FMC_BANK3 0x80000000 /* 0x80000000-0x8fffffff: 256Mb NAND FLASH */ -# define STM32L5_OCTOSPI1_BANK 0x90000000 /* 0x90000000-0x9fffffff: 256Mb QUADSPI */ -#define STM32L5_CORTEX_BASE 0xE0000000 /* 0xe0000000-0xffffffff: 512Mb Cortex-M4 block */ +#define STM32_CODE_BASE 0x00000000 /* 0x00000000-0x1fffffff: 512Mb code block */ +#define STM32_SRAM_BASE 0x20000000 /* 0x20000000-0x3fffffff: 512Mb sram block (48k to 256k) */ +#define STM32_PERIPH_BASE 0x40000000 /* 0x40000000-0x5fffffff: 512Mb peripheral block */ +#define STM32_FSMC_BASE12 0x60000000 /* 0x60000000-0x7fffffff: 512Mb FSMC bank1&2 block */ +# define STM32_FMC_BANK1 0x60000000 /* 0x60000000-0x6fffffff: 256Mb NOR/SRAM */ +#define STM32_FSMC_BASE34 0x80000000 /* 0x80000000-0x8fffffff: 512Mb FSMC bank3 / QSPI block */ +# define STM32_FMC_BANK3 0x80000000 /* 0x80000000-0x8fffffff: 256Mb NAND FLASH */ +# define STM32_OCTOSPI1_BANK 0x90000000 /* 0x90000000-0x9fffffff: 256Mb QUADSPI */ +#define STM32_CORTEX_BASE 0xE0000000 /* 0xe0000000-0xffffffff: 512Mb Cortex-M4 block */ -#define STM32L5_REGION_MASK 0xF0000000 -#define STM32L5_IS_SRAM(a) ((((uint32_t)(a)) & STM32L5_REGION_MASK) == STM32L5_SRAM_BASE) -#define STM32L5_IS_EXTSRAM(a) ((((uint32_t)(a)) & STM32L5_REGION_MASK) == STM32L5_FMC_BANK1) +#define STM32_REGION_MASK 0xF0000000 +#define STM32_IS_SRAM(a) ((((uint32_t)(a)) & STM32_REGION_MASK) == STM32_SRAM_BASE) +#define STM32_IS_EXTSRAM(a) ((((uint32_t)(a)) & STM32_REGION_MASK) == STM32_FMC_BANK1) /* Code Base Addresses ******************************************************/ -#define STM32L5_BOOT_BASE 0x00000000 /* 0x00000000-0x000fffff: Aliased boot memory */ -#define STM32L5_FLASH_BASE 0x08000000 /* 0x08000000-0x0807ffff: FLASH memory */ -#define STM32L5_SRAM1_BASE 0x20000000 /* 0x20000000-0x2002ffff: 192k SRAM1 */ -#define STM32L5_SRAM2_BASE 0x20030000 /* 0x20030000-0x2003ffff: 64k SRAM2 */ +#define STM32_BOOT_BASE 0x00000000 /* 0x00000000-0x000fffff: Aliased boot memory */ +#define STM32_FLASH_BASE 0x08000000 /* 0x08000000-0x0807ffff: FLASH memory */ +#define STM32_SRAM1_BASE 0x20000000 /* 0x20000000-0x2002ffff: 192k SRAM1 */ +#define STM32_SRAM2_BASE 0x20030000 /* 0x20030000-0x2003ffff: 64k SRAM2 */ /* System Memory Addresses **************************************************/ -#define STM32L5_SYSMEM_UID 0x0BFA0590 /* The 96-bit unique device identifier */ -#define STM32L5_SYSMEM_FSIZE 0x0BFA05E0 /* Size of Flash memory in Kbytes. */ -#define STM32L5_SYSMEM_PACKAGE 0x0BFA0500 /* Indicates the device's package type. */ +#define STM32_SYSMEM_UID 0x0BFA0590 /* The 96-bit unique device identifier */ +#define STM32_SYSMEM_FSIZE 0x0BFA05E0 /* Size of Flash memory in Kbytes. */ +#define STM32_SYSMEM_PACKAGE 0x0BFA0500 /* Indicates the device's package type. */ /* Peripheral Base Addresses ************************************************/ -#define STM32L5_APB1_BASE 0x40000000 /* 0x40000000-0x4000dfff: APB1 */ -#define STM32L5_APB2_BASE 0x40010000 /* 0x40010000-0x400167ff: APB2 */ -#define STM32L5_AHB1_BASE 0x40020000 /* 0x40020000-0x400333ff: AHB1 */ -#define STM32L5_AHB2_BASE 0x42020000 /* 0x42020000-0x420c83ff: AHB2 */ -#define STM32L5_AHB3_BASE 0x44020000 /* 0x44020000-0x440213ff: AHB3 */ +#define STM32_APB1_BASE 0x40000000 /* 0x40000000-0x4000dfff: APB1 */ +#define STM32_APB2_BASE 0x40010000 /* 0x40010000-0x400167ff: APB2 */ +#define STM32_AHB1_BASE 0x40020000 /* 0x40020000-0x400333ff: AHB1 */ +#define STM32_AHB2_BASE 0x42020000 /* 0x42020000-0x420c83ff: AHB2 */ +#define STM32_AHB3_BASE 0x44020000 /* 0x44020000-0x440213ff: AHB3 */ /* APB1 Base Addresses ******************************************************/ -#define STM32L5_UCPD1_BASE 0x4000DC00 -#define STM32L5_USB_SRAM_BASE 0x4000D800 -#define STM32L5_USB_FS_BASE 0x4000D400 -#define STM32L5_FDCAN_RAM_BASE 0x4000AC00 -#define STM32L5_FDCAN1_BASE 0x4000A400 -#define STM32L5_LPTIM3_BASE 0x40009800 -#define STM32L5_LPTIM2_BASE 0x40009400 -#define STM32L5_I2C4_BASE 0x40008400 -#define STM32L5_LPUART1_BASE 0x40008000 -#define STM32L5_LPTIM1_BASE 0x40007C00 -#define STM32L5_OPAMP_BASE 0x40007800 -#define STM32L5_DAC_BASE 0x40007400 -#define STM32L5_PWR_BASE 0x40007000 -#define STM32L5_CRS_BASE 0x40006000 -#define STM32L5_I2C3_BASE 0x40005C00 -#define STM32L5_I2C2_BASE 0x40005800 -#define STM32L5_I2C1_BASE 0x40005400 -#define STM32L5_UART5_BASE 0x40005000 -#define STM32L5_UART4_BASE 0x40004C00 -#define STM32L5_USART3_BASE 0x40004800 -#define STM32L5_USART2_BASE 0x40004400 -#define STM32L5_SPI3_BASE 0x40003C00 -#define STM32L5_SPI2_BASE 0x40003800 -#define STM32L5_TAMP_BASE 0x40003400 -#define STM32L5_IWDG_BASE 0x40003000 -#define STM32L5_WWDG_BASE 0x40002C00 -#define STM32L5_RTC_BASE 0x40002800 -#define STM32L5_TIM7_BASE 0x40001400 -#define STM32L5_TIM6_BASE 0x40001000 -#define STM32L5_TIM5_BASE 0x40000C00 -#define STM32L5_TIM4_BASE 0x40000800 -#define STM32L5_TIM3_BASE 0x40000400 -#define STM32L5_TIM2_BASE 0x40000000 +#define STM32_UCPD1_BASE 0x4000DC00 +#define STM32_USB_SRAM_BASE 0x4000D800 +#define STM32_USB_FS_BASE 0x4000D400 +#define STM32_FDCAN_RAM_BASE 0x4000AC00 +#define STM32_FDCAN1_BASE 0x4000A400 +#define STM32_LPTIM3_BASE 0x40009800 +#define STM32_LPTIM2_BASE 0x40009400 +#define STM32_I2C4_BASE 0x40008400 +#define STM32_LPUART1_BASE 0x40008000 +#define STM32_LPTIM1_BASE 0x40007C00 +#define STM32_OPAMP_BASE 0x40007800 +#define STM32_DAC_BASE 0x40007400 +#define STM32_PWR_BASE 0x40007000 +#define STM32_CRS_BASE 0x40006000 +#define STM32_I2C3_BASE 0x40005C00 +#define STM32_I2C2_BASE 0x40005800 +#define STM32_I2C1_BASE 0x40005400 +#define STM32_UART5_BASE 0x40005000 +#define STM32_UART4_BASE 0x40004C00 +#define STM32_USART3_BASE 0x40004800 +#define STM32_USART2_BASE 0x40004400 +#define STM32_SPI3_BASE 0x40003C00 +#define STM32_SPI2_BASE 0x40003800 +#define STM32_TAMP_BASE 0x40003400 +#define STM32_IWDG_BASE 0x40003000 +#define STM32_WWDG_BASE 0x40002C00 +#define STM32_RTC_BASE 0x40002800 +#define STM32_TIM7_BASE 0x40001400 +#define STM32_TIM6_BASE 0x40001000 +#define STM32_TIM5_BASE 0x40000C00 +#define STM32_TIM4_BASE 0x40000800 +#define STM32_TIM3_BASE 0x40000400 +#define STM32_TIM2_BASE 0x40000000 /* APB2 Base Addresses ******************************************************/ -#define STM32L5_DFSDM1_BASE 0x40016000 -#define STM32L5_SAI2_BASE 0x40015800 -#define STM32L5_SAI1_BASE 0x40015400 -#define STM32L5_TIM17_BASE 0x40014800 -#define STM32L5_TIM16_BASE 0x40014400 -#define STM32L5_TIM15_BASE 0x40014000 -#define STM32L5_USART1_BASE 0x40013800 -#define STM32L5_TIM8_BASE 0x40013400 -#define STM32L5_SPI1_BASE 0x40013000 -#define STM32L5_TIM1_BASE 0x40012C00 -#define STM32L5_COMP_BASE 0x40010200 -#define STM32L5_VREFBUF_BASE 0x40010100 -#define STM32L5_SYSCFG_BASE 0x40010000 +#define STM32_DFSDM1_BASE 0x40016000 +#define STM32_SAI2_BASE 0x40015800 +#define STM32_SAI1_BASE 0x40015400 +#define STM32_TIM17_BASE 0x40014800 +#define STM32_TIM16_BASE 0x40014400 +#define STM32_TIM15_BASE 0x40014000 +#define STM32_USART1_BASE 0x40013800 +#define STM32_TIM8_BASE 0x40013400 +#define STM32_SPI1_BASE 0x40013000 +#define STM32_TIM1_BASE 0x40012C00 +#define STM32_COMP_BASE 0x40010200 +#define STM32_VREFBUF_BASE 0x40010100 +#define STM32_SYSCFG_BASE 0x40010000 /* AHB1 Base Addresses ******************************************************/ -#define STM32L5_GTZC_BASE 0x40032400 -#define STM32L5_ICACHE_BASE 0x40030400 -#define STM32L5_EXTI_BASE 0x4002F400 -#define STM32L5_TSC_BASE 0x40024000 -#define STM32L5_CRC_BASE 0x40023000 -#define STM32L5_FLASHIF_BASE 0x40022000 -#define STM32L5_RCC_BASE 0x40021000 -#define STM32L5_DMAMUX1_BASE 0x40020800 -#define STM32L5_DMA2_BASE 0x40020400 -#define STM32L5_DMA1_BASE 0x40020000 +#define STM32_GTZC_BASE 0x40032400 +#define STM32_ICACHE_BASE 0x40030400 +#define STM32_EXTI_BASE 0x4002F400 +#define STM32_TSC_BASE 0x40024000 +#define STM32_CRC_BASE 0x40023000 +#define STM32_FLASHIF_BASE 0x40022000 +#define STM32_RCC_BASE 0x40021000 +#define STM32_DMAMUX1_BASE 0x40020800 +#define STM32_DMA2_BASE 0x40020400 +#define STM32_DMA1_BASE 0x40020000 /* AHB2 Base Addresses ******************************************************/ -#define STM32L5_SDMMC1_BASE 0x420C8000 -#define STM32L5_OTFDEC1_BASE 0x420C5000 -#define STM32L5_PKA_BASE 0x420C2000 -#define STM32L5_RNG_BASE 0x420C0800 -#define STM32L5_HASH_BASE 0x420C0400 -#define STM32L5_AES_BASE 0x420C0000 -#define STM32L5_ADC_BASE 0x42028000 -#define STM32L5_GPIOH_BASE 0x42021C00 -#define STM32L5_GPIOG_BASE 0x42021800 -#define STM32L5_GPIOF_BASE 0x42021400 -#define STM32L5_GPIOE_BASE 0x42021000 -#define STM32L5_GPIOD_BASE 0x42020c00 -#define STM32L5_GPIOC_BASE 0x42020800 -#define STM32L5_GPIOB_BASE 0x42020400 -#define STM32L5_GPIOA_BASE 0x42020000 +#define STM32_SDMMC1_BASE 0x420C8000 +#define STM32_OTFDEC1_BASE 0x420C5000 +#define STM32_PKA_BASE 0x420C2000 +#define STM32_RNG_BASE 0x420C0800 +#define STM32_HASH_BASE 0x420C0400 +#define STM32_AES_BASE 0x420C0000 +#define STM32_ADC_BASE 0x42028000 +#define STM32_GPIOH_BASE 0x42021C00 +#define STM32_GPIOG_BASE 0x42021800 +#define STM32_GPIOF_BASE 0x42021400 +#define STM32_GPIOE_BASE 0x42021000 +#define STM32_GPIOD_BASE 0x42020c00 +#define STM32_GPIOC_BASE 0x42020800 +#define STM32_GPIOB_BASE 0x42020400 +#define STM32_GPIOA_BASE 0x42020000 /* AHB2 Base Addresses ******************************************************/ -#define STM32L5_OCTOSPI1_BASE 0x44021000 -#define STM32L5_FMC_BASE 0x44020000 +#define STM32_OCTOSPI1_BASE 0x44021000 +#define STM32_FMC_BASE 0x44020000 -#endif /* __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32L5_MEMORYMAP_H */ +#endif /* __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32_MEMORYMAP_H */ diff --git a/arch/arm/src/stm32l5/hardware/stm32l5_pinmap.h b/arch/arm/src/stm32l5/hardware/stm32l5_pinmap.h index ee73d99996329..6b5c68f40679b 100644 --- a/arch/arm/src/stm32l5/hardware/stm32l5_pinmap.h +++ b/arch/arm/src/stm32l5/hardware/stm32l5_pinmap.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32L5_PINMAP_H -#define __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32L5_PINMAP_H +#ifndef __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32_PINMAP_H +#define __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32_PINMAP_H /**************************************************************************** * Included Files @@ -30,10 +30,10 @@ #include #include "chip.h" -#if defined(CONFIG_STM32L5_STM32L562XX) +#if defined(CONFIG_STM32_STM32L562XX) # include "hardware/stm32l562xx_pinmap.h" #else # error "Unsupported STM32 L5 pin map" #endif -#endif /* __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32L5_PINMAP_H */ +#endif /* __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32_PINMAP_H */ diff --git a/arch/arm/src/stm32l5/hardware/stm32l5_pwr.h b/arch/arm/src/stm32l5/hardware/stm32l5_pwr.h index 44cbde1b5985e..f00af0dd57705 100644 --- a/arch/arm/src/stm32l5/hardware/stm32l5_pwr.h +++ b/arch/arm/src/stm32l5/hardware/stm32l5_pwr.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32L5_PWR_H -#define __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32L5_PWR_H +#ifndef __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32_PWR_H +#define __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32_PWR_H /**************************************************************************** * Included Files @@ -36,59 +36,59 @@ /* Register Offsets *********************************************************/ -#define STM32L5_PWR_CR1_OFFSET 0x0000 /* Power control register 1 */ -#define STM32L5_PWR_CR2_OFFSET 0x0004 /* Power control register 2 */ -#define STM32L5_PWR_CR3_OFFSET 0x0008 /* Power control register 3 */ -#define STM32L5_PWR_CR4_OFFSET 0x000C /* Power control register 4 */ -#define STM32L5_PWR_SR1_OFFSET 0x0010 /* Power status register 1 */ -#define STM32L5_PWR_SR2_OFFSET 0x0014 /* Power status register 2 */ -#define STM32L5_PWR_SCR_OFFSET 0x0018 /* Power status clear register */ -#define STM32L5_PWR_PUCRA_OFFSET 0x0020 /* Power Port A pull-up control register */ -#define STM32L5_PWR_PDCRA_OFFSET 0x0024 /* Power Port A pull-down control register */ -#define STM32L5_PWR_PUCRB_OFFSET 0x0028 /* Power Port B pull-up control register */ -#define STM32L5_PWR_PDCRB_OFFSET 0x002C /* Power Port B pull-down control register */ -#define STM32L5_PWR_PUCRC_OFFSET 0x0030 /* Power Port C pull-up control register */ -#define STM32L5_PWR_PDCRC_OFFSET 0x0034 /* Power Port C pull-down control register */ -#define STM32L5_PWR_PUCRD_OFFSET 0x0038 /* Power Port D pull-up control register */ -#define STM32L5_PWR_PDCRD_OFFSET 0x003C /* Power Port D pull-down control register */ -#define STM32L5_PWR_PUCRE_OFFSET 0x0040 /* Power Port E pull-up control register */ -#define STM32L5_PWR_PDCRE_OFFSET 0x0044 /* Power Port E pull-down control register */ -#define STM32L5_PWR_PUCRF_OFFSET 0x0048 /* Power Port F pull-up control register */ -#define STM32L5_PWR_PDCRF_OFFSET 0x004C /* Power Port F pull-down control register */ -#define STM32L5_PWR_PUCRG_OFFSET 0x0050 /* Power Port G pull-up control register */ -#define STM32L5_PWR_PDCRG_OFFSET 0x0054 /* Power Port G pull-down control register */ -#define STM32L5_PWR_PUCRH_OFFSET 0x0058 /* Power Port H pull-up control register */ -#define STM32L5_PWR_PDCRH_OFFSET 0x005C /* Power Port H pull-down control register */ -#define STM32L5_PWR_SECCFGR_OFFSET 0x0078 /* Power secure configuration register */ -#define STM32L5_PWR_PRIVCFGR_OFFSET 0x0078 /* Power privilege configuration register */ +#define STM32_PWR_CR1_OFFSET 0x0000 /* Power control register 1 */ +#define STM32_PWR_CR2_OFFSET 0x0004 /* Power control register 2 */ +#define STM32_PWR_CR3_OFFSET 0x0008 /* Power control register 3 */ +#define STM32_PWR_CR4_OFFSET 0x000C /* Power control register 4 */ +#define STM32_PWR_SR1_OFFSET 0x0010 /* Power status register 1 */ +#define STM32_PWR_SR2_OFFSET 0x0014 /* Power status register 2 */ +#define STM32_PWR_SCR_OFFSET 0x0018 /* Power status clear register */ +#define STM32_PWR_PUCRA_OFFSET 0x0020 /* Power Port A pull-up control register */ +#define STM32_PWR_PDCRA_OFFSET 0x0024 /* Power Port A pull-down control register */ +#define STM32_PWR_PUCRB_OFFSET 0x0028 /* Power Port B pull-up control register */ +#define STM32_PWR_PDCRB_OFFSET 0x002C /* Power Port B pull-down control register */ +#define STM32_PWR_PUCRC_OFFSET 0x0030 /* Power Port C pull-up control register */ +#define STM32_PWR_PDCRC_OFFSET 0x0034 /* Power Port C pull-down control register */ +#define STM32_PWR_PUCRD_OFFSET 0x0038 /* Power Port D pull-up control register */ +#define STM32_PWR_PDCRD_OFFSET 0x003C /* Power Port D pull-down control register */ +#define STM32_PWR_PUCRE_OFFSET 0x0040 /* Power Port E pull-up control register */ +#define STM32_PWR_PDCRE_OFFSET 0x0044 /* Power Port E pull-down control register */ +#define STM32_PWR_PUCRF_OFFSET 0x0048 /* Power Port F pull-up control register */ +#define STM32_PWR_PDCRF_OFFSET 0x004C /* Power Port F pull-down control register */ +#define STM32_PWR_PUCRG_OFFSET 0x0050 /* Power Port G pull-up control register */ +#define STM32_PWR_PDCRG_OFFSET 0x0054 /* Power Port G pull-down control register */ +#define STM32_PWR_PUCRH_OFFSET 0x0058 /* Power Port H pull-up control register */ +#define STM32_PWR_PDCRH_OFFSET 0x005C /* Power Port H pull-down control register */ +#define STM32_PWR_SECCFGR_OFFSET 0x0078 /* Power secure configuration register */ +#define STM32_PWR_PRIVCFGR_OFFSET 0x0078 /* Power privilege configuration register */ /* Register Addresses *******************************************************/ -#define STM32L5_PWR_CR1 (STM32L5_PWR_BASE + STM32L5_PWR_CR1_OFFSET) -#define STM32L5_PWR_CR2 (STM32L5_PWR_BASE + STM32L5_PWR_CR2_OFFSET) -#define STM32L5_PWR_CR3 (STM32L5_PWR_BASE + STM32L5_PWR_CR3_OFFSET) -#define STM32L5_PWR_CR4 (STM32L5_PWR_BASE + STM32L5_PWR_CR4_OFFSET) -#define STM32L5_PWR_SR1 (STM32L5_PWR_BASE + STM32L5_PWR_SR1_OFFSET) -#define STM32L5_PWR_SR2 (STM32L5_PWR_BASE + STM32L5_PWR_SR2_OFFSET) -#define STM32L5_PWR_SCR (STM32L5_PWR_BASE + STM32L5_PWR_SCR_OFFSET) -#define STM32L5_PWR_PUCRA (STM32L5_PWR_BASE + STM32L5_PWR_PUCRA_OFFSET) -#define STM32L5_PWR_PDCRA (STM32L5_PWR_BASE + STM32L5_PWR_PDCRA_OFFSET) -#define STM32L5_PWR_PUCRB (STM32L5_PWR_BASE + STM32L5_PWR_PUCRB_OFFSET) -#define STM32L5_PWR_PDCRB (STM32L5_PWR_BASE + STM32L5_PWR_PDCRB_OFFSET) -#define STM32L5_PWR_PUCRC (STM32L5_PWR_BASE + STM32L5_PWR_PUCRC_OFFSET) -#define STM32L5_PWR_PDCRC (STM32L5_PWR_BASE + STM32L5_PWR_PDCRC_OFFSET) -#define STM32L5_PWR_PUCRD (STM32L5_PWR_BASE + STM32L5_PWR_PUCRD_OFFSET) -#define STM32L5_PWR_PDCRD (STM32L5_PWR_BASE + STM32L5_PWR_PDCRD_OFFSET) -#define STM32L5_PWR_PUCRE (STM32L5_PWR_BASE + STM32L5_PWR_PUCRE_OFFSET) -#define STM32L5_PWR_PDCRE (STM32L5_PWR_BASE + STM32L5_PWR_PDCRE_OFFSET) -#define STM32L5_PWR_PUCRF (STM32L5_PWR_BASE + STM32L5_PWR_PUCRF_OFFSET) -#define STM32L5_PWR_PDCRF (STM32L5_PWR_BASE + STM32L5_PWR_PDCRF_OFFSET) -#define STM32L5_PWR_PUCRG (STM32L5_PWR_BASE + STM32L5_PWR_PUCRG_OFFSET) -#define STM32L5_PWR_PDCRG (STM32L5_PWR_BASE + STM32L5_PWR_PDCRG_OFFSET) -#define STM32L5_PWR_PUCRH (STM32L5_PWR_BASE + STM32L5_PWR_PUCRH_OFFSET) -#define STM32L5_PWR_PDCRH (STM32L5_PWR_BASE + STM32L5_PWR_PDCRH_OFFSET) -#define STM32L5_PWR_SECCFGR (STM32L5_PWR_BASE + STM32L5_PWR_SECCFGR_OFFSET) -#define STM32L5_PWR_PRIVCFGR (STM32L5_PWR_BASE + STM32L5_PWR_PRIVCFGR_OFFSET) +#define STM32_PWR_CR1 (STM32_PWR_BASE + STM32_PWR_CR1_OFFSET) +#define STM32_PWR_CR2 (STM32_PWR_BASE + STM32_PWR_CR2_OFFSET) +#define STM32_PWR_CR3 (STM32_PWR_BASE + STM32_PWR_CR3_OFFSET) +#define STM32_PWR_CR4 (STM32_PWR_BASE + STM32_PWR_CR4_OFFSET) +#define STM32_PWR_SR1 (STM32_PWR_BASE + STM32_PWR_SR1_OFFSET) +#define STM32_PWR_SR2 (STM32_PWR_BASE + STM32_PWR_SR2_OFFSET) +#define STM32_PWR_SCR (STM32_PWR_BASE + STM32_PWR_SCR_OFFSET) +#define STM32_PWR_PUCRA (STM32_PWR_BASE + STM32_PWR_PUCRA_OFFSET) +#define STM32_PWR_PDCRA (STM32_PWR_BASE + STM32_PWR_PDCRA_OFFSET) +#define STM32_PWR_PUCRB (STM32_PWR_BASE + STM32_PWR_PUCRB_OFFSET) +#define STM32_PWR_PDCRB (STM32_PWR_BASE + STM32_PWR_PDCRB_OFFSET) +#define STM32_PWR_PUCRC (STM32_PWR_BASE + STM32_PWR_PUCRC_OFFSET) +#define STM32_PWR_PDCRC (STM32_PWR_BASE + STM32_PWR_PDCRC_OFFSET) +#define STM32_PWR_PUCRD (STM32_PWR_BASE + STM32_PWR_PUCRD_OFFSET) +#define STM32_PWR_PDCRD (STM32_PWR_BASE + STM32_PWR_PDCRD_OFFSET) +#define STM32_PWR_PUCRE (STM32_PWR_BASE + STM32_PWR_PUCRE_OFFSET) +#define STM32_PWR_PDCRE (STM32_PWR_BASE + STM32_PWR_PDCRE_OFFSET) +#define STM32_PWR_PUCRF (STM32_PWR_BASE + STM32_PWR_PUCRF_OFFSET) +#define STM32_PWR_PDCRF (STM32_PWR_BASE + STM32_PWR_PDCRF_OFFSET) +#define STM32_PWR_PUCRG (STM32_PWR_BASE + STM32_PWR_PUCRG_OFFSET) +#define STM32_PWR_PDCRG (STM32_PWR_BASE + STM32_PWR_PDCRG_OFFSET) +#define STM32_PWR_PUCRH (STM32_PWR_BASE + STM32_PWR_PUCRH_OFFSET) +#define STM32_PWR_PDCRH (STM32_PWR_BASE + STM32_PWR_PDCRH_OFFSET) +#define STM32_PWR_SECCFGR (STM32_PWR_BASE + STM32_PWR_SECCFGR_OFFSET) +#define STM32_PWR_PRIVCFGR (STM32_PWR_BASE + STM32_PWR_PRIVCFGR_OFFSET) /* Register Bitfield Definitions ********************************************/ @@ -214,4 +214,4 @@ #define PWR_PRIVCFGR_PRIV (1 << 0) /* Bit 0: Privilege protection */ -#endif /* __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32L5_PWR_H */ +#endif /* __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32_PWR_H */ diff --git a/arch/arm/src/stm32l5/hardware/stm32l5_spi.h b/arch/arm/src/stm32l5/hardware/stm32l5_spi.h index 91b92dc5a6a65..1e8eba96ff992 100644 --- a/arch/arm/src/stm32l5/hardware/stm32l5_spi.h +++ b/arch/arm/src/stm32l5/hardware/stm32l5_spi.h @@ -36,52 +36,52 @@ /* Maximum allowed speed as per specifications for all SPIs */ -#if defined(CONFIG_STM32L5_STM32L562XX) -# define STM32L5_SPI_CLK_MAX 55000000UL +#if defined(CONFIG_STM32_STM32L562XX) +# define STM32_SPI_CLK_MAX 55000000UL #else # error "Unsupported STM32 L5 chip" #endif /* Register Offsets *********************************************************/ -#define STM32L5_SPI_CR1_OFFSET 0x0000 /* SPI Control Register 1 (16-bit) */ -#define STM32L5_SPI_CR2_OFFSET 0x0004 /* SPI control register 2 (16-bit) */ -#define STM32L5_SPI_SR_OFFSET 0x0008 /* SPI status register (16-bit) */ -#define STM32L5_SPI_DR_OFFSET 0x000c /* SPI data register (16-bit) */ -#define STM32L5_SPI_CRCPR_OFFSET 0x0010 /* SPI CRC polynomial register (16-bit) */ -#define STM32L5_SPI_RXCRCR_OFFSET 0x0014 /* SPI Rx CRC register (16-bit) */ -#define STM32L5_SPI_TXCRCR_OFFSET 0x0018 /* SPI Tx CRC register (16-bit) */ +#define STM32_SPI_CR1_OFFSET 0x0000 /* SPI Control Register 1 (16-bit) */ +#define STM32_SPI_CR2_OFFSET 0x0004 /* SPI control register 2 (16-bit) */ +#define STM32_SPI_SR_OFFSET 0x0008 /* SPI status register (16-bit) */ +#define STM32_SPI_DR_OFFSET 0x000c /* SPI data register (16-bit) */ +#define STM32_SPI_CRCPR_OFFSET 0x0010 /* SPI CRC polynomial register (16-bit) */ +#define STM32_SPI_RXCRCR_OFFSET 0x0014 /* SPI Rx CRC register (16-bit) */ +#define STM32_SPI_TXCRCR_OFFSET 0x0018 /* SPI Tx CRC register (16-bit) */ /* Register Addresses *******************************************************/ -#if STM32L5_NSPI > 0 -# define STM32L5_SPI1_CR1 (STM32L5_SPI1_BASE + STM32L5_SPI_CR1_OFFSET) -# define STM32L5_SPI1_CR2 (STM32L5_SPI1_BASE + STM32L5_SPI_CR2_OFFSET) -# define STM32L5_SPI1_SR (STM32L5_SPI1_BASE + STM32L5_SPI_SR_OFFSET) -# define STM32L5_SPI1_DR (STM32L5_SPI1_BASE + STM32L5_SPI_DR_OFFSET) -# define STM32L5_SPI1_CRCPR (STM32L5_SPI1_BASE + STM32L5_SPI_CRCPR_OFFSET) -# define STM32L5_SPI1_RXCRCR (STM32L5_SPI1_BASE + STM32L5_SPI_RXCRCR_OFFSET) -# define STM32L5_SPI1_TXCRCR (STM32L5_SPI1_BASE + STM32L5_SPI_TXCRCR_OFFSET) +#if STM32_NSPI > 0 +# define STM32_SPI1_CR1 (STM32_SPI1_BASE + STM32_SPI_CR1_OFFSET) +# define STM32_SPI1_CR2 (STM32_SPI1_BASE + STM32_SPI_CR2_OFFSET) +# define STM32_SPI1_SR (STM32_SPI1_BASE + STM32_SPI_SR_OFFSET) +# define STM32_SPI1_DR (STM32_SPI1_BASE + STM32_SPI_DR_OFFSET) +# define STM32_SPI1_CRCPR (STM32_SPI1_BASE + STM32_SPI_CRCPR_OFFSET) +# define STM32_SPI1_RXCRCR (STM32_SPI1_BASE + STM32_SPI_RXCRCR_OFFSET) +# define STM32_SPI1_TXCRCR (STM32_SPI1_BASE + STM32_SPI_TXCRCR_OFFSET) #endif -#if STM32L5_NSPI > 1 -# define STM32L5_SPI2_CR1 (STM32L5_SPI2_BASE + STM32L5_SPI_CR1_OFFSET) -# define STM32L5_SPI2_CR2 (STM32L5_SPI2_BASE + STM32L5_SPI_CR2_OFFSET) -# define STM32L5_SPI2_SR (STM32L5_SPI2_BASE + STM32L5_SPI_SR_OFFSET) -# define STM32L5_SPI2_DR (STM32L5_SPI2_BASE + STM32L5_SPI_DR_OFFSET) -# define STM32L5_SPI2_CRCPR (STM32L5_SPI2_BASE + STM32L5_SPI_CRCPR_OFFSET) -# define STM32L5_SPI2_RXCRCR (STM32L5_SPI2_BASE + STM32L5_SPI_RXCRCR_OFFSET) -# define STM32L5_SPI2_TXCRCR (STM32L5_SPI2_BASE + STM32L5_SPI_TXCRCR_OFFSET) +#if STM32_NSPI > 1 +# define STM32_SPI2_CR1 (STM32_SPI2_BASE + STM32_SPI_CR1_OFFSET) +# define STM32_SPI2_CR2 (STM32_SPI2_BASE + STM32_SPI_CR2_OFFSET) +# define STM32_SPI2_SR (STM32_SPI2_BASE + STM32_SPI_SR_OFFSET) +# define STM32_SPI2_DR (STM32_SPI2_BASE + STM32_SPI_DR_OFFSET) +# define STM32_SPI2_CRCPR (STM32_SPI2_BASE + STM32_SPI_CRCPR_OFFSET) +# define STM32_SPI2_RXCRCR (STM32_SPI2_BASE + STM32_SPI_RXCRCR_OFFSET) +# define STM32_SPI2_TXCRCR (STM32_SPI2_BASE + STM32_SPI_TXCRCR_OFFSET) #endif -#if STM32L5_NSPI > 2 -# define STM32L5_SPI3_CR1 (STM32L5_SPI3_BASE + STM32L5_SPI_CR1_OFFSET) -# define STM32L5_SPI3_CR2 (STM32L5_SPI3_BASE + STM32L5_SPI_CR2_OFFSET) -# define STM32L5_SPI3_SR (STM32L5_SPI3_BASE + STM32L5_SPI_SR_OFFSET) -# define STM32L5_SPI3_DR (STM32L5_SPI3_BASE + STM32L5_SPI_DR_OFFSET) -# define STM32L5_SPI3_CRCPR (STM32L5_SPI3_BASE + STM32L5_SPI_CRCPR_OFFSET) -# define STM32L5_SPI3_RXCRCR (STM32L5_SPI3_BASE + STM32L5_SPI_RXCRCR_OFFSET) -# define STM32L5_SPI3_TXCRCR (STM32L5_SPI3_BASE + STM32L5_SPI_TXCRCR_OFFSET) +#if STM32_NSPI > 2 +# define STM32_SPI3_CR1 (STM32_SPI3_BASE + STM32_SPI_CR1_OFFSET) +# define STM32_SPI3_CR2 (STM32_SPI3_BASE + STM32_SPI_CR2_OFFSET) +# define STM32_SPI3_SR (STM32_SPI3_BASE + STM32_SPI_SR_OFFSET) +# define STM32_SPI3_DR (STM32_SPI3_BASE + STM32_SPI_DR_OFFSET) +# define STM32_SPI3_CRCPR (STM32_SPI3_BASE + STM32_SPI_CRCPR_OFFSET) +# define STM32_SPI3_RXCRCR (STM32_SPI3_BASE + STM32_SPI_RXCRCR_OFFSET) +# define STM32_SPI3_TXCRCR (STM32_SPI3_BASE + STM32_SPI_TXCRCR_OFFSET) #endif /* Register Bitfield Definitions ********************************************/ diff --git a/arch/arm/src/stm32l5/hardware/stm32l5_syscfg.h b/arch/arm/src/stm32l5/hardware/stm32l5_syscfg.h index c7ad32505500f..dfd8a438db582 100644 --- a/arch/arm/src/stm32l5/hardware/stm32l5_syscfg.h +++ b/arch/arm/src/stm32l5/hardware/stm32l5_syscfg.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32L5_SYSCFG_H -#define __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32L5_SYSCFG_H +#ifndef __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32_SYSCFG_H +#define __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32_SYSCFG_H /**************************************************************************** * Included Files @@ -30,10 +30,10 @@ #include #include "chip.h" -#if defined(CONFIG_STM32L5_STM32L562XX) +#if defined(CONFIG_STM32_STM32L562XX) # include "hardware/stm32l562xx_syscfg.h" #else # error "Unsupported STM32 L5 chip" #endif -#endif /* __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32L5_SYSCFG_H */ +#endif /* __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32_SYSCFG_H */ diff --git a/arch/arm/src/stm32l5/hardware/stm32l5_tim.h b/arch/arm/src/stm32l5/hardware/stm32l5_tim.h index 1e99dba009a77..c490bd032aba2 100644 --- a/arch/arm/src/stm32l5/hardware/stm32l5_tim.h +++ b/arch/arm/src/stm32l5/hardware/stm32l5_tim.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32L5_TIM_H -#define __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32L5_TIM_H +#ifndef __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32_TIM_H +#define __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32_TIM_H /**************************************************************************** * Pre-processor Definitions @@ -31,14 +31,14 @@ /* Basic Timers - TIM6 and TIM7 */ -#define STM32L5_BTIM_CR1_OFFSET 0x0000 /* Control register 1 (16-bit) */ -#define STM32L5_BTIM_CR2_OFFSET 0x0004 /* Control register 2 (16-bit) */ -#define STM32L5_BTIM_DIER_OFFSET 0x000c /* DMA/Interrupt enable register (16-bit) */ -#define STM32L5_BTIM_SR_OFFSET 0x0010 /* Status register (16-bit) */ -#define STM32L5_BTIM_EGR_OFFSET 0x0014 /* Event generation register (16-bit) */ -#define STM32L5_BTIM_CNT_OFFSET 0x0024 /* Counter (16-bit) */ -#define STM32L5_BTIM_PSC_OFFSET 0x0028 /* Prescaler (16-bit) */ -#define STM32L5_BTIM_ARR_OFFSET 0x002c /* Auto-reload register (16-bit) */ +#define STM32_BTIM_CR1_OFFSET 0x0000 /* Control register 1 (16-bit) */ +#define STM32_BTIM_CR2_OFFSET 0x0004 /* Control register 2 (16-bit) */ +#define STM32_BTIM_DIER_OFFSET 0x000c /* DMA/Interrupt enable register (16-bit) */ +#define STM32_BTIM_SR_OFFSET 0x0010 /* Status register (16-bit) */ +#define STM32_BTIM_EGR_OFFSET 0x0014 /* Event generation register (16-bit) */ +#define STM32_BTIM_CNT_OFFSET 0x0024 /* Counter (16-bit) */ +#define STM32_BTIM_PSC_OFFSET 0x0028 /* Prescaler (16-bit) */ +#define STM32_BTIM_ARR_OFFSET 0x002c /* Auto-reload register (16-bit) */ /* 16-/32-bit General Timers - TIM2, TIM3, TIM4, TIM5, and TIM15-17. * TIM3 and 4 are 16-bit. @@ -46,119 +46,119 @@ * TIM15, 16 and 17 are 16-bit. */ -#define STM32L5_GTIM_CR1_OFFSET 0x0000 /* Control register 1 (16-bit) */ -#define STM32L5_GTIM_CR2_OFFSET 0x0004 /* Control register 2 (16-bit) */ -#define STM32L5_GTIM_SMCR_OFFSET 0x0008 /* Slave mode control register (16-bit, TIM2-5,15 only) */ -#define STM32L5_GTIM_DIER_OFFSET 0x000c /* DMA/Interrupt enable register (16-bit) */ -#define STM32L5_GTIM_SR_OFFSET 0x0010 /* Status register (16-bit) */ -#define STM32L5_GTIM_EGR_OFFSET 0x0014 /* Event generation register (16-bit) */ -#define STM32L5_GTIM_CCMR1_OFFSET 0x0018 /* Capture/compare mode register 1 (32-bit) */ -#define STM32L5_GTIM_CCMR2_OFFSET 0x001c /* Capture/compare mode register 2 (32-bit, TIM2-5 only) */ -#define STM32L5_GTIM_CCER_OFFSET 0x0020 /* Capture/compare enable register (16-bit) */ -#define STM32L5_GTIM_CNT_OFFSET 0x0024 /* Counter (16-bit or 32-bit TIM2/5) */ -#define STM32L5_GTIM_PSC_OFFSET 0x0028 /* Prescaler (16-bit) */ -#define STM32L5_GTIM_ARR_OFFSET 0x002c /* Auto-reload register (16-bit or 32-bit TIM2/5) */ -#define STM32L5_GTIM_CCR1_OFFSET 0x0034 /* Capture/compare register 1 (16-bit or 32-bit TIM2/5) */ -#define STM32L5_GTIM_CCR2_OFFSET 0x0038 /* Capture/compare register 2 (16-bit TIM2-5,15 only or 32-bit TIM2/5) */ -#define STM32L5_GTIM_CCR3_OFFSET 0x003c /* Capture/compare register 3 (16-bit TIM2-5 only or 32-bit TIM2/5) */ -#define STM32L5_GTIM_CCR4_OFFSET 0x0040 /* Capture/compare register 4 (16-bit TIM2-5 only or 32-bit TIM2/5) */ -#define STM32L5_GTIM_DCR_OFFSET 0x0048 /* DMA control register (16-bit) */ -#define STM32L5_GTIM_DMAR_OFFSET 0x004c /* DMA address for burst mode (16-bit) */ -#define STM32L5_GTIM_OR1_OFFSET 0x0050 /* Option register 1 */ -#define STM32L5_GTIM_OR2_OFFSET 0x0060 /* Option register 2 */ +#define STM32_GTIM_CR1_OFFSET 0x0000 /* Control register 1 (16-bit) */ +#define STM32_GTIM_CR2_OFFSET 0x0004 /* Control register 2 (16-bit) */ +#define STM32_GTIM_SMCR_OFFSET 0x0008 /* Slave mode control register (16-bit, TIM2-5,15 only) */ +#define STM32_GTIM_DIER_OFFSET 0x000c /* DMA/Interrupt enable register (16-bit) */ +#define STM32_GTIM_SR_OFFSET 0x0010 /* Status register (16-bit) */ +#define STM32_GTIM_EGR_OFFSET 0x0014 /* Event generation register (16-bit) */ +#define STM32_GTIM_CCMR1_OFFSET 0x0018 /* Capture/compare mode register 1 (32-bit) */ +#define STM32_GTIM_CCMR2_OFFSET 0x001c /* Capture/compare mode register 2 (32-bit, TIM2-5 only) */ +#define STM32_GTIM_CCER_OFFSET 0x0020 /* Capture/compare enable register (16-bit) */ +#define STM32_GTIM_CNT_OFFSET 0x0024 /* Counter (16-bit or 32-bit TIM2/5) */ +#define STM32_GTIM_PSC_OFFSET 0x0028 /* Prescaler (16-bit) */ +#define STM32_GTIM_ARR_OFFSET 0x002c /* Auto-reload register (16-bit or 32-bit TIM2/5) */ +#define STM32_GTIM_CCR1_OFFSET 0x0034 /* Capture/compare register 1 (16-bit or 32-bit TIM2/5) */ +#define STM32_GTIM_CCR2_OFFSET 0x0038 /* Capture/compare register 2 (16-bit TIM2-5,15 only or 32-bit TIM2/5) */ +#define STM32_GTIM_CCR3_OFFSET 0x003c /* Capture/compare register 3 (16-bit TIM2-5 only or 32-bit TIM2/5) */ +#define STM32_GTIM_CCR4_OFFSET 0x0040 /* Capture/compare register 4 (16-bit TIM2-5 only or 32-bit TIM2/5) */ +#define STM32_GTIM_DCR_OFFSET 0x0048 /* DMA control register (16-bit) */ +#define STM32_GTIM_DMAR_OFFSET 0x004c /* DMA address for burst mode (16-bit) */ +#define STM32_GTIM_OR1_OFFSET 0x0050 /* Option register 1 */ +#define STM32_GTIM_OR2_OFFSET 0x0060 /* Option register 2 */ /* TIM15, 16, and 17 only. */ -#define STM32L5_GTIM_RCR_OFFSET 0x0030 /* Repetition counter register (TIM16/TIM17) */ -#define STM32L5_GTIM_BDTR_OFFSET 0x0044 /* Break and dead-time register (TIM16/TIM17) */ +#define STM32_GTIM_RCR_OFFSET 0x0030 /* Repetition counter register (TIM16/TIM17) */ +#define STM32_GTIM_BDTR_OFFSET 0x0044 /* Break and dead-time register (TIM16/TIM17) */ /* Advanced Timers - TIM1 and TIM8 */ -#define STM32L5_ATIM_CR1_OFFSET 0x0000 /* Control register 1 (16-bit) */ -#define STM32L5_ATIM_CR2_OFFSET 0x0004 /* Control register 2 (16-bit*) */ -#define STM32L5_ATIM_SMCR_OFFSET 0x0008 /* Slave mode control register (16-bit) */ -#define STM32L5_ATIM_DIER_OFFSET 0x000c /* DMA/Interrupt enable register (16-bit) */ -#define STM32L5_ATIM_SR_OFFSET 0x0010 /* Status register (16-bit*) */ -#define STM32L5_ATIM_EGR_OFFSET 0x0014 /* Event generation register (16-bit) */ -#define STM32L5_ATIM_CCMR1_OFFSET 0x0018 /* Capture/compare mode register 1 (16-bit*) */ -#define STM32L5_ATIM_CCMR2_OFFSET 0x001c /* Capture/compare mode register 2 (16-bit*) */ -#define STM32L5_ATIM_CCER_OFFSET 0x0020 /* Capture/compare enable register (16-bit*) */ -#define STM32L5_ATIM_CNT_OFFSET 0x0024 /* Counter (16-bit) */ -#define STM32L5_ATIM_PSC_OFFSET 0x0028 /* Prescaler (16-bit) */ -#define STM32L5_ATIM_ARR_OFFSET 0x002c /* Auto-reload register (16-bit) */ -#define STM32L5_ATIM_RCR_OFFSET 0x0030 /* Repetition counter register (16-bit) */ -#define STM32L5_ATIM_CCR1_OFFSET 0x0034 /* Capture/compare register 1 (16-bit) */ -#define STM32L5_ATIM_CCR2_OFFSET 0x0038 /* Capture/compare register 2 (16-bit) */ -#define STM32L5_ATIM_CCR3_OFFSET 0x003c /* Capture/compare register 3 (16-bit) */ -#define STM32L5_ATIM_CCR4_OFFSET 0x0040 /* Capture/compare register 4 (16-bit) */ -#define STM32L5_ATIM_BDTR_OFFSET 0x0044 /* Break and dead-time register (16-bit*) */ -#define STM32L5_ATIM_DCR_OFFSET 0x0048 /* DMA control register (16-bit) */ -#define STM32L5_ATIM_DMAR_OFFSET 0x004c /* DMA address for burst mode (16-bit) */ -#define STM32L5_ATIM_OR1_OFFSET 0x0050 /* Timer option register 1 */ -#define STM32L5_ATIM_CCMR3_OFFSET 0x0054 /* Capture/compare mode register 3 (32-bit) */ -#define STM32L5_ATIM_CCR5_OFFSET 0x0058 /* Capture/compare register 4 (16-bit) */ -#define STM32L5_ATIM_CCR6_OFFSET 0x005c /* Capture/compare register 4 (32-bit) */ -#define STM32L5_ATIM_OR2_OFFSET 0x0050 /* Timer option register 2 */ -#define STM32L5_ATIM_OR3_OFFSET 0x0050 /* Timer option register 3 */ +#define STM32_ATIM_CR1_OFFSET 0x0000 /* Control register 1 (16-bit) */ +#define STM32_ATIM_CR2_OFFSET 0x0004 /* Control register 2 (16-bit*) */ +#define STM32_ATIM_SMCR_OFFSET 0x0008 /* Slave mode control register (16-bit) */ +#define STM32_ATIM_DIER_OFFSET 0x000c /* DMA/Interrupt enable register (16-bit) */ +#define STM32_ATIM_SR_OFFSET 0x0010 /* Status register (16-bit*) */ +#define STM32_ATIM_EGR_OFFSET 0x0014 /* Event generation register (16-bit) */ +#define STM32_ATIM_CCMR1_OFFSET 0x0018 /* Capture/compare mode register 1 (16-bit*) */ +#define STM32_ATIM_CCMR2_OFFSET 0x001c /* Capture/compare mode register 2 (16-bit*) */ +#define STM32_ATIM_CCER_OFFSET 0x0020 /* Capture/compare enable register (16-bit*) */ +#define STM32_ATIM_CNT_OFFSET 0x0024 /* Counter (16-bit) */ +#define STM32_ATIM_PSC_OFFSET 0x0028 /* Prescaler (16-bit) */ +#define STM32_ATIM_ARR_OFFSET 0x002c /* Auto-reload register (16-bit) */ +#define STM32_ATIM_RCR_OFFSET 0x0030 /* Repetition counter register (16-bit) */ +#define STM32_ATIM_CCR1_OFFSET 0x0034 /* Capture/compare register 1 (16-bit) */ +#define STM32_ATIM_CCR2_OFFSET 0x0038 /* Capture/compare register 2 (16-bit) */ +#define STM32_ATIM_CCR3_OFFSET 0x003c /* Capture/compare register 3 (16-bit) */ +#define STM32_ATIM_CCR4_OFFSET 0x0040 /* Capture/compare register 4 (16-bit) */ +#define STM32_ATIM_BDTR_OFFSET 0x0044 /* Break and dead-time register (16-bit*) */ +#define STM32_ATIM_DCR_OFFSET 0x0048 /* DMA control register (16-bit) */ +#define STM32_ATIM_DMAR_OFFSET 0x004c /* DMA address for burst mode (16-bit) */ +#define STM32_ATIM_OR1_OFFSET 0x0050 /* Timer option register 1 */ +#define STM32_ATIM_CCMR3_OFFSET 0x0054 /* Capture/compare mode register 3 (32-bit) */ +#define STM32_ATIM_CCR5_OFFSET 0x0058 /* Capture/compare register 4 (16-bit) */ +#define STM32_ATIM_CCR6_OFFSET 0x005c /* Capture/compare register 4 (32-bit) */ +#define STM32_ATIM_OR2_OFFSET 0x0050 /* Timer option register 2 */ +#define STM32_ATIM_OR3_OFFSET 0x0050 /* Timer option register 3 */ /* Register Addresses *******************************************************/ /* Advanced Timers - TIM1 and TIM8 */ -#define STM32L5_TIM1_CR1 (STM32L5_TIM1_BASE + STM32L5_ATIM_CR1_OFFSET) -#define STM32L5_TIM1_CR2 (STM32L5_TIM1_BASE + STM32L5_ATIM_CR2_OFFSET) -#define STM32L5_TIM1_SMCR (STM32L5_TIM1_BASE + STM32L5_ATIM_SMCR_OFFSET) -#define STM32L5_TIM1_DIER (STM32L5_TIM1_BASE + STM32L5_ATIM_DIER_OFFSET) -#define STM32L5_TIM1_SR (STM32L5_TIM1_BASE + STM32L5_ATIM_SR_OFFSET) -#define STM32L5_TIM1_EGR (STM32L5_TIM1_BASE + STM32L5_ATIM_EGR_OFFSET) -#define STM32L5_TIM1_CCMR1 (STM32L5_TIM1_BASE + STM32L5_ATIM_CCMR1_OFFSET) -#define STM32L5_TIM1_CCMR2 (STM32L5_TIM1_BASE + STM32L5_ATIM_CCMR2_OFFSET) -#define STM32L5_TIM1_CCER (STM32L5_TIM1_BASE + STM32L5_ATIM_CCER_OFFSET) -#define STM32L5_TIM1_CNT (STM32L5_TIM1_BASE + STM32L5_ATIM_CNT_OFFSET) -#define STM32L5_TIM1_PSC (STM32L5_TIM1_BASE + STM32L5_ATIM_PSC_OFFSET) -#define STM32L5_TIM1_ARR (STM32L5_TIM1_BASE + STM32L5_ATIM_ARR_OFFSET) -#define STM32L5_TIM1_RCR (STM32L5_TIM1_BASE + STM32L5_ATIM_RCR_OFFSET) -#define STM32L5_TIM1_CCR1 (STM32L5_TIM1_BASE + STM32L5_ATIM_CCR1_OFFSET) -#define STM32L5_TIM1_CCR2 (STM32L5_TIM1_BASE + STM32L5_ATIM_CCR2_OFFSET) -#define STM32L5_TIM1_CCR3 (STM32L5_TIM1_BASE + STM32L5_ATIM_CCR3_OFFSET) -#define STM32L5_TIM1_CCR4 (STM32L5_TIM1_BASE + STM32L5_ATIM_CCR4_OFFSET) -#define STM32L5_TIM1_BDTR (STM32L5_TIM1_BASE + STM32L5_ATIM_BDTR_OFFSET) -#define STM32L5_TIM1_DCR (STM32L5_TIM1_BASE + STM32L5_ATIM_DCR_OFFSET) -#define STM32L5_TIM1_DMAR (STM32L5_TIM1_BASE + STM32L5_ATIM_DMAR_OFFSET) -#define STM32L5_TIM1_OR1 (STM32L5_TIM1_BASE + STM32L5_ATIM_OR1_OFFSET) -#define STM32L5_TIM1_CCMR3 (STM32L5_TIM1_BASE + STM32L5_ATIM_CCMR3_OFFSET) -#define STM32L5_TIM1_CCR5 (STM32L5_TIM1_BASE + STM32L5_ATIM_CCR5_OFFSET) -#define STM32L5_TIM1_CCR6 (STM32L5_TIM1_BASE + STM32L5_ATIM_CCR6_OFFSET) -#define STM32L5_TIM1_OR2 (STM32L5_TIM1_BASE + STM32L5_ATIM_OR2_OFFSET) -#define STM32L5_TIM1_OR3 (STM32L5_TIM1_BASE + STM32L5_ATIM_OR3_OFFSET) - -#define STM32L5_TIM8_CR1 (STM32L5_TIM8_BASE + STM32L5_ATIM_CR1_OFFSET) -#define STM32L5_TIM8_CR2 (STM32L5_TIM8_BASE + STM32L5_ATIM_CR2_OFFSET) -#define STM32L5_TIM8_SMCR (STM32L5_TIM8_BASE + STM32L5_ATIM_SMCR_OFFSET) -#define STM32L5_TIM8_DIER (STM32L5_TIM8_BASE + STM32L5_ATIM_DIER_OFFSET) -#define STM32L5_TIM8_SR (STM32L5_TIM8_BASE + STM32L5_ATIM_SR_OFFSET) -#define STM32L5_TIM8_EGR (STM32L5_TIM8_BASE + STM32L5_ATIM_EGR_OFFSET) -#define STM32L5_TIM8_CCMR1 (STM32L5_TIM8_BASE + STM32L5_ATIM_CCMR1_OFFSET) -#define STM32L5_TIM8_CCMR2 (STM32L5_TIM8_BASE + STM32L5_ATIM_CCMR2_OFFSET) -#define STM32L5_TIM8_CCER (STM32L5_TIM8_BASE + STM32L5_ATIM_CCER_OFFSET) -#define STM32L5_TIM8_CNT (STM32L5_TIM8_BASE + STM32L5_ATIM_CNT_OFFSET) -#define STM32L5_TIM8_PSC (STM32L5_TIM8_BASE + STM32L5_ATIM_PSC_OFFSET) -#define STM32L5_TIM8_ARR (STM32L5_TIM8_BASE + STM32L5_ATIM_ARR_OFFSET) -#define STM32L5_TIM8_RCR (STM32L5_TIM8_BASE + STM32L5_ATIM_RCR_OFFSET) -#define STM32L5_TIM8_CCR1 (STM32L5_TIM8_BASE + STM32L5_ATIM_CCR1_OFFSET) -#define STM32L5_TIM8_CCR2 (STM32L5_TIM8_BASE + STM32L5_ATIM_CCR2_OFFSET) -#define STM32L5_TIM8_CCR3 (STM32L5_TIM8_BASE + STM32L5_ATIM_CCR3_OFFSET) -#define STM32L5_TIM8_CCR4 (STM32L5_TIM8_BASE + STM32L5_ATIM_CCR4_OFFSET) -#define STM32L5_TIM8_BDTR (STM32L5_TIM8_BASE + STM32L5_ATIM_BDTR_OFFSET) -#define STM32L5_TIM8_DCR (STM32L5_TIM8_BASE + STM32L5_ATIM_DCR_OFFSET) -#define STM32L5_TIM8_DMAR (STM32L5_TIM8_BASE + STM32L5_ATIM_DMAR_OFFSET) -#define STM32L5_TIM8_OR1 (STM32L5_TIM8_BASE + STM32L5_ATIM_OR1_OFFSET) -#define STM32L5_TIM8_CCMR3 (STM32L5_TIM8_BASE + STM32L5_ATIM_CCMR3_OFFSET) -#define STM32L5_TIM8_CCR5 (STM32L5_TIM8_BASE + STM32L5_ATIM_CCR5_OFFSET) -#define STM32L5_TIM8_CCR6 (STM32L5_TIM8_BASE + STM32L5_ATIM_CCR6_OFFSET) -#define STM32L5_TIM8_OR2 (STM32L5_TIM8_BASE + STM32L5_ATIM_OR2_OFFSET) -#define STM32L5_TIM8_OR3 (STM32L5_TIM8_BASE + STM32L5_ATIM_OR3_OFFSET) +#define STM32_TIM1_CR1 (STM32_TIM1_BASE + STM32_ATIM_CR1_OFFSET) +#define STM32_TIM1_CR2 (STM32_TIM1_BASE + STM32_ATIM_CR2_OFFSET) +#define STM32_TIM1_SMCR (STM32_TIM1_BASE + STM32_ATIM_SMCR_OFFSET) +#define STM32_TIM1_DIER (STM32_TIM1_BASE + STM32_ATIM_DIER_OFFSET) +#define STM32_TIM1_SR (STM32_TIM1_BASE + STM32_ATIM_SR_OFFSET) +#define STM32_TIM1_EGR (STM32_TIM1_BASE + STM32_ATIM_EGR_OFFSET) +#define STM32_TIM1_CCMR1 (STM32_TIM1_BASE + STM32_ATIM_CCMR1_OFFSET) +#define STM32_TIM1_CCMR2 (STM32_TIM1_BASE + STM32_ATIM_CCMR2_OFFSET) +#define STM32_TIM1_CCER (STM32_TIM1_BASE + STM32_ATIM_CCER_OFFSET) +#define STM32_TIM1_CNT (STM32_TIM1_BASE + STM32_ATIM_CNT_OFFSET) +#define STM32_TIM1_PSC (STM32_TIM1_BASE + STM32_ATIM_PSC_OFFSET) +#define STM32_TIM1_ARR (STM32_TIM1_BASE + STM32_ATIM_ARR_OFFSET) +#define STM32_TIM1_RCR (STM32_TIM1_BASE + STM32_ATIM_RCR_OFFSET) +#define STM32_TIM1_CCR1 (STM32_TIM1_BASE + STM32_ATIM_CCR1_OFFSET) +#define STM32_TIM1_CCR2 (STM32_TIM1_BASE + STM32_ATIM_CCR2_OFFSET) +#define STM32_TIM1_CCR3 (STM32_TIM1_BASE + STM32_ATIM_CCR3_OFFSET) +#define STM32_TIM1_CCR4 (STM32_TIM1_BASE + STM32_ATIM_CCR4_OFFSET) +#define STM32_TIM1_BDTR (STM32_TIM1_BASE + STM32_ATIM_BDTR_OFFSET) +#define STM32_TIM1_DCR (STM32_TIM1_BASE + STM32_ATIM_DCR_OFFSET) +#define STM32_TIM1_DMAR (STM32_TIM1_BASE + STM32_ATIM_DMAR_OFFSET) +#define STM32_TIM1_OR1 (STM32_TIM1_BASE + STM32_ATIM_OR1_OFFSET) +#define STM32_TIM1_CCMR3 (STM32_TIM1_BASE + STM32_ATIM_CCMR3_OFFSET) +#define STM32_TIM1_CCR5 (STM32_TIM1_BASE + STM32_ATIM_CCR5_OFFSET) +#define STM32_TIM1_CCR6 (STM32_TIM1_BASE + STM32_ATIM_CCR6_OFFSET) +#define STM32_TIM1_OR2 (STM32_TIM1_BASE + STM32_ATIM_OR2_OFFSET) +#define STM32_TIM1_OR3 (STM32_TIM1_BASE + STM32_ATIM_OR3_OFFSET) + +#define STM32_TIM8_CR1 (STM32_TIM8_BASE + STM32_ATIM_CR1_OFFSET) +#define STM32_TIM8_CR2 (STM32_TIM8_BASE + STM32_ATIM_CR2_OFFSET) +#define STM32_TIM8_SMCR (STM32_TIM8_BASE + STM32_ATIM_SMCR_OFFSET) +#define STM32_TIM8_DIER (STM32_TIM8_BASE + STM32_ATIM_DIER_OFFSET) +#define STM32_TIM8_SR (STM32_TIM8_BASE + STM32_ATIM_SR_OFFSET) +#define STM32_TIM8_EGR (STM32_TIM8_BASE + STM32_ATIM_EGR_OFFSET) +#define STM32_TIM8_CCMR1 (STM32_TIM8_BASE + STM32_ATIM_CCMR1_OFFSET) +#define STM32_TIM8_CCMR2 (STM32_TIM8_BASE + STM32_ATIM_CCMR2_OFFSET) +#define STM32_TIM8_CCER (STM32_TIM8_BASE + STM32_ATIM_CCER_OFFSET) +#define STM32_TIM8_CNT (STM32_TIM8_BASE + STM32_ATIM_CNT_OFFSET) +#define STM32_TIM8_PSC (STM32_TIM8_BASE + STM32_ATIM_PSC_OFFSET) +#define STM32_TIM8_ARR (STM32_TIM8_BASE + STM32_ATIM_ARR_OFFSET) +#define STM32_TIM8_RCR (STM32_TIM8_BASE + STM32_ATIM_RCR_OFFSET) +#define STM32_TIM8_CCR1 (STM32_TIM8_BASE + STM32_ATIM_CCR1_OFFSET) +#define STM32_TIM8_CCR2 (STM32_TIM8_BASE + STM32_ATIM_CCR2_OFFSET) +#define STM32_TIM8_CCR3 (STM32_TIM8_BASE + STM32_ATIM_CCR3_OFFSET) +#define STM32_TIM8_CCR4 (STM32_TIM8_BASE + STM32_ATIM_CCR4_OFFSET) +#define STM32_TIM8_BDTR (STM32_TIM8_BASE + STM32_ATIM_BDTR_OFFSET) +#define STM32_TIM8_DCR (STM32_TIM8_BASE + STM32_ATIM_DCR_OFFSET) +#define STM32_TIM8_DMAR (STM32_TIM8_BASE + STM32_ATIM_DMAR_OFFSET) +#define STM32_TIM8_OR1 (STM32_TIM8_BASE + STM32_ATIM_OR1_OFFSET) +#define STM32_TIM8_CCMR3 (STM32_TIM8_BASE + STM32_ATIM_CCMR3_OFFSET) +#define STM32_TIM8_CCR5 (STM32_TIM8_BASE + STM32_ATIM_CCR5_OFFSET) +#define STM32_TIM8_CCR6 (STM32_TIM8_BASE + STM32_ATIM_CCR6_OFFSET) +#define STM32_TIM8_OR2 (STM32_TIM8_BASE + STM32_ATIM_OR2_OFFSET) +#define STM32_TIM8_OR3 (STM32_TIM8_BASE + STM32_ATIM_OR3_OFFSET) /* 16-/32-bit General Timers - TIM2, TIM3, TIM4, TIM5, and TIM15-17. * TIM3 and 4 are 16-bit. @@ -166,154 +166,154 @@ * TIM15, 16 and 17 are 16-bit. */ -#define STM32L5_TIM2_CR1 (STM32L5_TIM2_BASE + STM32L5_GTIM_CR1_OFFSET) -#define STM32L5_TIM2_CR2 (STM32L5_TIM2_BASE + STM32L5_GTIM_CR2_OFFSET) -#define STM32L5_TIM2_SMCR (STM32L5_TIM2_BASE + STM32L5_GTIM_SMCR_OFFSET) -#define STM32L5_TIM2_DIER (STM32L5_TIM2_BASE + STM32L5_GTIM_DIER_OFFSET) -#define STM32L5_TIM2_SR (STM32L5_TIM2_BASE + STM32L5_GTIM_SR_OFFSET) -#define STM32L5_TIM2_EGR (STM32L5_TIM2_BASE + STM32L5_GTIM_EGR_OFFSET) -#define STM32L5_TIM2_CCMR1 (STM32L5_TIM2_BASE + STM32L5_GTIM_CCMR1_OFFSET) -#define STM32L5_TIM2_CCMR2 (STM32L5_TIM2_BASE + STM32L5_GTIM_CCMR2_OFFSET) -#define STM32L5_TIM2_CCER (STM32L5_TIM2_BASE + STM32L5_GTIM_CCER_OFFSET) -#define STM32L5_TIM2_CNT (STM32L5_TIM2_BASE + STM32L5_GTIM_CNT_OFFSET) -#define STM32L5_TIM2_PSC (STM32L5_TIM2_BASE + STM32L5_GTIM_PSC_OFFSET) -#define STM32L5_TIM2_ARR (STM32L5_TIM2_BASE + STM32L5_GTIM_ARR_OFFSET) -#define STM32L5_TIM2_CCR1 (STM32L5_TIM2_BASE + STM32L5_GTIM_CCR1_OFFSET) -#define STM32L5_TIM2_CCR2 (STM32L5_TIM2_BASE + STM32L5_GTIM_CCR2_OFFSET) -#define STM32L5_TIM2_CCR3 (STM32L5_TIM2_BASE + STM32L5_GTIM_CCR3_OFFSET) -#define STM32L5_TIM2_CCR4 (STM32L5_TIM2_BASE + STM32L5_GTIM_CCR4_OFFSET) -#define STM32L5_TIM2_DCR (STM32L5_TIM2_BASE + STM32L5_GTIM_DCR_OFFSET) -#define STM32L5_TIM2_DMAR (STM32L5_TIM2_BASE + STM32L5_GTIM_DMAR_OFFSET) -#define STM32L5_TIM2_OR (STM32L5_TIM2_BASE + STM32L5_GTIM_OR_OFFSET) - -#define STM32L5_TIM3_CR1 (STM32L5_TIM3_BASE + STM32L5_GTIM_CR1_OFFSET) -#define STM32L5_TIM3_CR2 (STM32L5_TIM3_BASE + STM32L5_GTIM_CR2_OFFSET) -#define STM32L5_TIM3_SMCR (STM32L5_TIM3_BASE + STM32L5_GTIM_SMCR_OFFSET) -#define STM32L5_TIM3_DIER (STM32L5_TIM3_BASE + STM32L5_GTIM_DIER_OFFSET) -#define STM32L5_TIM3_SR (STM32L5_TIM3_BASE + STM32L5_GTIM_SR_OFFSET) -#define STM32L5_TIM3_EGR (STM32L5_TIM3_BASE + STM32L5_GTIM_EGR_OFFSET) -#define STM32L5_TIM3_CCMR1 (STM32L5_TIM3_BASE + STM32L5_GTIM_CCMR1_OFFSET) -#define STM32L5_TIM3_CCMR2 (STM32L5_TIM3_BASE + STM32L5_GTIM_CCMR2_OFFSET) -#define STM32L5_TIM3_CCER (STM32L5_TIM3_BASE + STM32L5_GTIM_CCER_OFFSET) -#define STM32L5_TIM3_CNT (STM32L5_TIM3_BASE + STM32L5_GTIM_CNT_OFFSET) -#define STM32L5_TIM3_PSC (STM32L5_TIM3_BASE + STM32L5_GTIM_PSC_OFFSET) -#define STM32L5_TIM3_ARR (STM32L5_TIM3_BASE + STM32L5_GTIM_ARR_OFFSET) -#define STM32L5_TIM3_CCR1 (STM32L5_TIM3_BASE + STM32L5_GTIM_CCR1_OFFSET) -#define STM32L5_TIM3_CCR2 (STM32L5_TIM3_BASE + STM32L5_GTIM_CCR2_OFFSET) -#define STM32L5_TIM3_CCR3 (STM32L5_TIM3_BASE + STM32L5_GTIM_CCR3_OFFSET) -#define STM32L5_TIM3_CCR4 (STM32L5_TIM3_BASE + STM32L5_GTIM_CCR4_OFFSET) -#define STM32L5_TIM3_DCR (STM32L5_TIM3_BASE + STM32L5_GTIM_DCR_OFFSET) -#define STM32L5_TIM3_DMAR (STM32L5_TIM3_BASE + STM32L5_GTIM_DMAR_OFFSET) - -#define STM32L5_TIM4_CR1 (STM32L5_TIM4_BASE + STM32L5_GTIM_CR1_OFFSET) -#define STM32L5_TIM4_CR2 (STM32L5_TIM4_BASE + STM32L5_GTIM_CR2_OFFSET) -#define STM32L5_TIM4_SMCR (STM32L5_TIM4_BASE + STM32L5_GTIM_SMCR_OFFSET) -#define STM32L5_TIM4_DIER (STM32L5_TIM4_BASE + STM32L5_GTIM_DIER_OFFSET) -#define STM32L5_TIM4_SR (STM32L5_TIM4_BASE + STM32L5_GTIM_SR_OFFSET) -#define STM32L5_TIM4_EGR (STM32L5_TIM4_BASE + STM32L5_GTIM_EGR_OFFSET) -#define STM32L5_TIM4_CCMR1 (STM32L5_TIM4_BASE + STM32L5_GTIM_CCMR1_OFFSET) -#define STM32L5_TIM4_CCMR2 (STM32L5_TIM4_BASE + STM32L5_GTIM_CCMR2_OFFSET) -#define STM32L5_TIM4_CCER (STM32L5_TIM4_BASE + STM32L5_GTIM_CCER_OFFSET) -#define STM32L5_TIM4_CNT (STM32L5_TIM4_BASE + STM32L5_GTIM_CNT_OFFSET) -#define STM32L5_TIM4_PSC (STM32L5_TIM4_BASE + STM32L5_GTIM_PSC_OFFSET) -#define STM32L5_TIM4_ARR (STM32L5_TIM4_BASE + STM32L5_GTIM_ARR_OFFSET) -#define STM32L5_TIM4_CCR1 (STM32L5_TIM4_BASE + STM32L5_GTIM_CCR1_OFFSET) -#define STM32L5_TIM4_CCR2 (STM32L5_TIM4_BASE + STM32L5_GTIM_CCR2_OFFSET) -#define STM32L5_TIM4_CCR3 (STM32L5_TIM4_BASE + STM32L5_GTIM_CCR3_OFFSET) -#define STM32L5_TIM4_CCR4 (STM32L5_TIM4_BASE + STM32L5_GTIM_CCR4_OFFSET) -#define STM32L5_TIM4_DCR (STM32L5_TIM4_BASE + STM32L5_GTIM_DCR_OFFSET) -#define STM32L5_TIM4_DMAR (STM32L5_TIM4_BASE + STM32L5_GTIM_DMAR_OFFSET) - -#define STM32L5_TIM5_CR1 (STM32L5_TIM5_BASE + STM32L5_GTIM_CR1_OFFSET) -#define STM32L5_TIM5_CR2 (STM32L5_TIM5_BASE + STM32L5_GTIM_CR2_OFFSET) -#define STM32L5_TIM5_SMCR (STM32L5_TIM5_BASE + STM32L5_GTIM_SMCR_OFFSET) -#define STM32L5_TIM5_DIER (STM32L5_TIM5_BASE + STM32L5_GTIM_DIER_OFFSET) -#define STM32L5_TIM5_SR (STM32L5_TIM5_BASE + STM32L5_GTIM_SR_OFFSET) -#define STM32L5_TIM5_EGR (STM32L5_TIM5_BASE + STM32L5_GTIM_EGR_OFFSET) -#define STM32L5_TIM5_CCMR1 (STM32L5_TIM5_BASE + STM32L5_GTIM_CCMR1_OFFSET) -#define STM32L5_TIM5_CCMR2 (STM32L5_TIM5_BASE + STM32L5_GTIM_CCMR2_OFFSET) -#define STM32L5_TIM5_CCER (STM32L5_TIM5_BASE + STM32L5_GTIM_CCER_OFFSET) -#define STM32L5_TIM5_CNT (STM32L5_TIM5_BASE + STM32L5_GTIM_CNT_OFFSET) -#define STM32L5_TIM5_PSC (STM32L5_TIM5_BASE + STM32L5_GTIM_PSC_OFFSET) -#define STM32L5_TIM5_ARR (STM32L5_TIM5_BASE + STM32L5_GTIM_ARR_OFFSET) -#define STM32L5_TIM5_CCR1 (STM32L5_TIM5_BASE + STM32L5_GTIM_CCR1_OFFSET) -#define STM32L5_TIM5_CCR2 (STM32L5_TIM5_BASE + STM32L5_GTIM_CCR2_OFFSET) -#define STM32L5_TIM5_CCR3 (STM32L5_TIM5_BASE + STM32L5_GTIM_CCR3_OFFSET) -#define STM32L5_TIM5_CCR4 (STM32L5_TIM5_BASE + STM32L5_GTIM_CCR4_OFFSET) -#define STM32L5_TIM5_DCR (STM32L5_TIM5_BASE + STM32L5_GTIM_DCR_OFFSET) -#define STM32L5_TIM5_DMAR (STM32L5_TIM5_BASE + STM32L5_GTIM_DMAR_OFFSET) -#define STM32L5_TIM5_OR (STM32L5_TIM5_BASE + STM32L5_GTIM_OR_OFFSET) - -#define STM32L5_TIM15_CR1 (STM32L5_TIM15_BASE + STM32L5_GTIM_CR1_OFFSET) -#define STM32L5_TIM15_CR2 (STM32L5_TIM15_BASE + STM32L5_GTIM_CR2_OFFSET) -#define STM32L5_TIM15_SMCR (STM32L5_TIM15_BASE + STM32L5_GTIM_SMCR_OFFSET) -#define STM32L5_TIM15_DIER (STM32L5_TIM15_BASE + STM32L5_GTIM_DIER_OFFSET) -#define STM32L5_TIM15_SR (STM32L5_TIM15_BASE + STM32L5_GTIM_SR_OFFSET) -#define STM32L5_TIM15_EGR (STM32L5_TIM15_BASE + STM32L5_GTIM_EGR_OFFSET) -#define STM32L5_TIM15_CCMR1 (STM32L5_TIM15_BASE + STM32L5_GTIM_CCMR1_OFFSET) -#define STM32L5_TIM15_CCER (STM32L5_TIM15_BASE + STM32L5_GTIM_CCER_OFFSET) -#define STM32L5_TIM15_CNT (STM32L5_TIM15_BASE + STM32L5_GTIM_CNT_OFFSET) -#define STM32L5_TIM15_PSC (STM32L5_TIM15_BASE + STM32L5_GTIM_PSC_OFFSET) -#define STM32L5_TIM15_ARR (STM32L5_TIM15_BASE + STM32L5_GTIM_ARR_OFFSET) -#define STM32L5_TIM15_RCR (STM32L5_TIM15_BASE + STM32L5_GTIM_RCR_OFFSET) -#define STM32L5_TIM15_CCR1 (STM32L5_TIM15_BASE + STM32L5_GTIM_CCR1_OFFSET) -#define STM32L5_TIM15_CCR2 (STM32L5_TIM15_BASE + STM32L5_GTIM_CCR2_OFFSET) -#define STM32L5_TIM15_BDTR (STM32L5_TIM15_BASE + STM32L5_GTIM_BDTR_OFFSET) -#define STM32L5_TIM15_DCR (STM32L5_TIM15_BASE + STM32L5_GTIM_DCR_OFFSET) -#define STM32L5_TIM15_DMAR (STM32L5_TIM15_BASE + STM32L5_GTIM_DMAR_OFFSET) - -#define STM32L5_TIM16_CR1 (STM32L5_TIM16_BASE + STM32L5_GTIM_CR1_OFFSET) -#define STM32L5_TIM16_CR2 (STM32L5_TIM16_BASE + STM32L5_GTIM_CR2_OFFSET) -#define STM32L5_TIM16_DIER (STM32L5_TIM16_BASE + STM32L5_GTIM_DIER_OFFSET) -#define STM32L5_TIM16_SR (STM32L5_TIM16_BASE + STM32L5_GTIM_SR_OFFSET) -#define STM32L5_TIM16_EGR (STM32L5_TIM16_BASE + STM32L5_GTIM_EGR_OFFSET) -#define STM32L5_TIM16_CCMR1 (STM32L5_TIM16_BASE + STM32L5_GTIM_CCMR1_OFFSET) -#define STM32L5_TIM16_CCER (STM32L5_TIM16_BASE + STM32L5_GTIM_CCER_OFFSET) -#define STM32L5_TIM16_CNT (STM32L5_TIM16_BASE + STM32L5_GTIM_CNT_OFFSET) -#define STM32L5_TIM16_PSC (STM32L5_TIM16_BASE + STM32L5_GTIM_PSC_OFFSET) -#define STM32L5_TIM16_ARR (STM32L5_TIM16_BASE + STM32L5_GTIM_ARR_OFFSET) -#define STM32L5_TIM16_RCR (STM32L5_TIM16_BASE + STM32L5_GTIM_RCR_OFFSET) -#define STM32L5_TIM16_CCR1 (STM32L5_TIM16_BASE + STM32L5_GTIM_CCR1_OFFSET) -#define STM32L5_TIM16_BDTR (STM32L5_TIM16_BASE + STM32L5_GTIM_BDTR_OFFSET) -#define STM32L5_TIM16_DCR (STM32L5_TIM16_BASE + STM32L5_GTIM_DCR_OFFSET) -#define STM32L5_TIM16_DMAR (STM32L5_TIM16_BASE + STM32L5_GTIM_DMAR_OFFSET) -#define STM32L5_TIM16_OR (STM32L5_TIM16_BASE + STM32L5_GTIM_OR_OFFSET) - -#define STM32L5_TIM17_CR1 (STM32L5_TIM17_BASE + STM32L5_GTIM_CR1_OFFSET) -#define STM32L5_TIM17_CR2 (STM32L5_TIM17_BASE + STM32L5_GTIM_CR2_OFFSET) -#define STM32L5_TIM17_DIER (STM32L5_TIM17_BASE + STM32L5_GTIM_DIER_OFFSET) -#define STM32L5_TIM17_SR (STM32L5_TIM17_BASE + STM32L5_GTIM_SR_OFFSET) -#define STM32L5_TIM17_EGR (STM32L5_TIM17_BASE + STM32L5_GTIM_EGR_OFFSET) -#define STM32L5_TIM17_CCMR1 (STM32L5_TIM17_BASE + STM32L5_GTIM_CCMR1_OFFSET) -#define STM32L5_TIM17_CCER (STM32L5_TIM17_BASE + STM32L5_GTIM_CCER_OFFSET) -#define STM32L5_TIM17_CNT (STM32L5_TIM17_BASE + STM32L5_GTIM_CNT_OFFSET) -#define STM32L5_TIM17_PSC (STM32L5_TIM17_BASE + STM32L5_GTIM_PSC_OFFSET) -#define STM32L5_TIM17_ARR (STM32L5_TIM17_BASE + STM32L5_GTIM_ARR_OFFSET) -#define STM32L5_TIM17_RCR (STM32L5_TIM17_BASE + STM32L5_GTIM_RCR_OFFSET) -#define STM32L5_TIM17_CCR1 (STM32L5_TIM17_BASE + STM32L5_GTIM_CCR1_OFFSET) -#define STM32L5_TIM17_BDTR (STM32L5_TIM17_BASE + STM32L5_GTIM_BDTR_OFFSET) -#define STM32L5_TIM17_DCR (STM32L5_TIM17_BASE + STM32L5_GTIM_DCR_OFFSET) -#define STM32L5_TIM17_DMAR (STM32L5_TIM17_BASE + STM32L5_GTIM_DMAR_OFFSET) +#define STM32_TIM2_CR1 (STM32_TIM2_BASE + STM32_GTIM_CR1_OFFSET) +#define STM32_TIM2_CR2 (STM32_TIM2_BASE + STM32_GTIM_CR2_OFFSET) +#define STM32_TIM2_SMCR (STM32_TIM2_BASE + STM32_GTIM_SMCR_OFFSET) +#define STM32_TIM2_DIER (STM32_TIM2_BASE + STM32_GTIM_DIER_OFFSET) +#define STM32_TIM2_SR (STM32_TIM2_BASE + STM32_GTIM_SR_OFFSET) +#define STM32_TIM2_EGR (STM32_TIM2_BASE + STM32_GTIM_EGR_OFFSET) +#define STM32_TIM2_CCMR1 (STM32_TIM2_BASE + STM32_GTIM_CCMR1_OFFSET) +#define STM32_TIM2_CCMR2 (STM32_TIM2_BASE + STM32_GTIM_CCMR2_OFFSET) +#define STM32_TIM2_CCER (STM32_TIM2_BASE + STM32_GTIM_CCER_OFFSET) +#define STM32_TIM2_CNT (STM32_TIM2_BASE + STM32_GTIM_CNT_OFFSET) +#define STM32_TIM2_PSC (STM32_TIM2_BASE + STM32_GTIM_PSC_OFFSET) +#define STM32_TIM2_ARR (STM32_TIM2_BASE + STM32_GTIM_ARR_OFFSET) +#define STM32_TIM2_CCR1 (STM32_TIM2_BASE + STM32_GTIM_CCR1_OFFSET) +#define STM32_TIM2_CCR2 (STM32_TIM2_BASE + STM32_GTIM_CCR2_OFFSET) +#define STM32_TIM2_CCR3 (STM32_TIM2_BASE + STM32_GTIM_CCR3_OFFSET) +#define STM32_TIM2_CCR4 (STM32_TIM2_BASE + STM32_GTIM_CCR4_OFFSET) +#define STM32_TIM2_DCR (STM32_TIM2_BASE + STM32_GTIM_DCR_OFFSET) +#define STM32_TIM2_DMAR (STM32_TIM2_BASE + STM32_GTIM_DMAR_OFFSET) +#define STM32_TIM2_OR (STM32_TIM2_BASE + STM32_GTIM_OR_OFFSET) + +#define STM32_TIM3_CR1 (STM32_TIM3_BASE + STM32_GTIM_CR1_OFFSET) +#define STM32_TIM3_CR2 (STM32_TIM3_BASE + STM32_GTIM_CR2_OFFSET) +#define STM32_TIM3_SMCR (STM32_TIM3_BASE + STM32_GTIM_SMCR_OFFSET) +#define STM32_TIM3_DIER (STM32_TIM3_BASE + STM32_GTIM_DIER_OFFSET) +#define STM32_TIM3_SR (STM32_TIM3_BASE + STM32_GTIM_SR_OFFSET) +#define STM32_TIM3_EGR (STM32_TIM3_BASE + STM32_GTIM_EGR_OFFSET) +#define STM32_TIM3_CCMR1 (STM32_TIM3_BASE + STM32_GTIM_CCMR1_OFFSET) +#define STM32_TIM3_CCMR2 (STM32_TIM3_BASE + STM32_GTIM_CCMR2_OFFSET) +#define STM32_TIM3_CCER (STM32_TIM3_BASE + STM32_GTIM_CCER_OFFSET) +#define STM32_TIM3_CNT (STM32_TIM3_BASE + STM32_GTIM_CNT_OFFSET) +#define STM32_TIM3_PSC (STM32_TIM3_BASE + STM32_GTIM_PSC_OFFSET) +#define STM32_TIM3_ARR (STM32_TIM3_BASE + STM32_GTIM_ARR_OFFSET) +#define STM32_TIM3_CCR1 (STM32_TIM3_BASE + STM32_GTIM_CCR1_OFFSET) +#define STM32_TIM3_CCR2 (STM32_TIM3_BASE + STM32_GTIM_CCR2_OFFSET) +#define STM32_TIM3_CCR3 (STM32_TIM3_BASE + STM32_GTIM_CCR3_OFFSET) +#define STM32_TIM3_CCR4 (STM32_TIM3_BASE + STM32_GTIM_CCR4_OFFSET) +#define STM32_TIM3_DCR (STM32_TIM3_BASE + STM32_GTIM_DCR_OFFSET) +#define STM32_TIM3_DMAR (STM32_TIM3_BASE + STM32_GTIM_DMAR_OFFSET) + +#define STM32_TIM4_CR1 (STM32_TIM4_BASE + STM32_GTIM_CR1_OFFSET) +#define STM32_TIM4_CR2 (STM32_TIM4_BASE + STM32_GTIM_CR2_OFFSET) +#define STM32_TIM4_SMCR (STM32_TIM4_BASE + STM32_GTIM_SMCR_OFFSET) +#define STM32_TIM4_DIER (STM32_TIM4_BASE + STM32_GTIM_DIER_OFFSET) +#define STM32_TIM4_SR (STM32_TIM4_BASE + STM32_GTIM_SR_OFFSET) +#define STM32_TIM4_EGR (STM32_TIM4_BASE + STM32_GTIM_EGR_OFFSET) +#define STM32_TIM4_CCMR1 (STM32_TIM4_BASE + STM32_GTIM_CCMR1_OFFSET) +#define STM32_TIM4_CCMR2 (STM32_TIM4_BASE + STM32_GTIM_CCMR2_OFFSET) +#define STM32_TIM4_CCER (STM32_TIM4_BASE + STM32_GTIM_CCER_OFFSET) +#define STM32_TIM4_CNT (STM32_TIM4_BASE + STM32_GTIM_CNT_OFFSET) +#define STM32_TIM4_PSC (STM32_TIM4_BASE + STM32_GTIM_PSC_OFFSET) +#define STM32_TIM4_ARR (STM32_TIM4_BASE + STM32_GTIM_ARR_OFFSET) +#define STM32_TIM4_CCR1 (STM32_TIM4_BASE + STM32_GTIM_CCR1_OFFSET) +#define STM32_TIM4_CCR2 (STM32_TIM4_BASE + STM32_GTIM_CCR2_OFFSET) +#define STM32_TIM4_CCR3 (STM32_TIM4_BASE + STM32_GTIM_CCR3_OFFSET) +#define STM32_TIM4_CCR4 (STM32_TIM4_BASE + STM32_GTIM_CCR4_OFFSET) +#define STM32_TIM4_DCR (STM32_TIM4_BASE + STM32_GTIM_DCR_OFFSET) +#define STM32_TIM4_DMAR (STM32_TIM4_BASE + STM32_GTIM_DMAR_OFFSET) + +#define STM32_TIM5_CR1 (STM32_TIM5_BASE + STM32_GTIM_CR1_OFFSET) +#define STM32_TIM5_CR2 (STM32_TIM5_BASE + STM32_GTIM_CR2_OFFSET) +#define STM32_TIM5_SMCR (STM32_TIM5_BASE + STM32_GTIM_SMCR_OFFSET) +#define STM32_TIM5_DIER (STM32_TIM5_BASE + STM32_GTIM_DIER_OFFSET) +#define STM32_TIM5_SR (STM32_TIM5_BASE + STM32_GTIM_SR_OFFSET) +#define STM32_TIM5_EGR (STM32_TIM5_BASE + STM32_GTIM_EGR_OFFSET) +#define STM32_TIM5_CCMR1 (STM32_TIM5_BASE + STM32_GTIM_CCMR1_OFFSET) +#define STM32_TIM5_CCMR2 (STM32_TIM5_BASE + STM32_GTIM_CCMR2_OFFSET) +#define STM32_TIM5_CCER (STM32_TIM5_BASE + STM32_GTIM_CCER_OFFSET) +#define STM32_TIM5_CNT (STM32_TIM5_BASE + STM32_GTIM_CNT_OFFSET) +#define STM32_TIM5_PSC (STM32_TIM5_BASE + STM32_GTIM_PSC_OFFSET) +#define STM32_TIM5_ARR (STM32_TIM5_BASE + STM32_GTIM_ARR_OFFSET) +#define STM32_TIM5_CCR1 (STM32_TIM5_BASE + STM32_GTIM_CCR1_OFFSET) +#define STM32_TIM5_CCR2 (STM32_TIM5_BASE + STM32_GTIM_CCR2_OFFSET) +#define STM32_TIM5_CCR3 (STM32_TIM5_BASE + STM32_GTIM_CCR3_OFFSET) +#define STM32_TIM5_CCR4 (STM32_TIM5_BASE + STM32_GTIM_CCR4_OFFSET) +#define STM32_TIM5_DCR (STM32_TIM5_BASE + STM32_GTIM_DCR_OFFSET) +#define STM32_TIM5_DMAR (STM32_TIM5_BASE + STM32_GTIM_DMAR_OFFSET) +#define STM32_TIM5_OR (STM32_TIM5_BASE + STM32_GTIM_OR_OFFSET) + +#define STM32_TIM15_CR1 (STM32_TIM15_BASE + STM32_GTIM_CR1_OFFSET) +#define STM32_TIM15_CR2 (STM32_TIM15_BASE + STM32_GTIM_CR2_OFFSET) +#define STM32_TIM15_SMCR (STM32_TIM15_BASE + STM32_GTIM_SMCR_OFFSET) +#define STM32_TIM15_DIER (STM32_TIM15_BASE + STM32_GTIM_DIER_OFFSET) +#define STM32_TIM15_SR (STM32_TIM15_BASE + STM32_GTIM_SR_OFFSET) +#define STM32_TIM15_EGR (STM32_TIM15_BASE + STM32_GTIM_EGR_OFFSET) +#define STM32_TIM15_CCMR1 (STM32_TIM15_BASE + STM32_GTIM_CCMR1_OFFSET) +#define STM32_TIM15_CCER (STM32_TIM15_BASE + STM32_GTIM_CCER_OFFSET) +#define STM32_TIM15_CNT (STM32_TIM15_BASE + STM32_GTIM_CNT_OFFSET) +#define STM32_TIM15_PSC (STM32_TIM15_BASE + STM32_GTIM_PSC_OFFSET) +#define STM32_TIM15_ARR (STM32_TIM15_BASE + STM32_GTIM_ARR_OFFSET) +#define STM32_TIM15_RCR (STM32_TIM15_BASE + STM32_GTIM_RCR_OFFSET) +#define STM32_TIM15_CCR1 (STM32_TIM15_BASE + STM32_GTIM_CCR1_OFFSET) +#define STM32_TIM15_CCR2 (STM32_TIM15_BASE + STM32_GTIM_CCR2_OFFSET) +#define STM32_TIM15_BDTR (STM32_TIM15_BASE + STM32_GTIM_BDTR_OFFSET) +#define STM32_TIM15_DCR (STM32_TIM15_BASE + STM32_GTIM_DCR_OFFSET) +#define STM32_TIM15_DMAR (STM32_TIM15_BASE + STM32_GTIM_DMAR_OFFSET) + +#define STM32_TIM16_CR1 (STM32_TIM16_BASE + STM32_GTIM_CR1_OFFSET) +#define STM32_TIM16_CR2 (STM32_TIM16_BASE + STM32_GTIM_CR2_OFFSET) +#define STM32_TIM16_DIER (STM32_TIM16_BASE + STM32_GTIM_DIER_OFFSET) +#define STM32_TIM16_SR (STM32_TIM16_BASE + STM32_GTIM_SR_OFFSET) +#define STM32_TIM16_EGR (STM32_TIM16_BASE + STM32_GTIM_EGR_OFFSET) +#define STM32_TIM16_CCMR1 (STM32_TIM16_BASE + STM32_GTIM_CCMR1_OFFSET) +#define STM32_TIM16_CCER (STM32_TIM16_BASE + STM32_GTIM_CCER_OFFSET) +#define STM32_TIM16_CNT (STM32_TIM16_BASE + STM32_GTIM_CNT_OFFSET) +#define STM32_TIM16_PSC (STM32_TIM16_BASE + STM32_GTIM_PSC_OFFSET) +#define STM32_TIM16_ARR (STM32_TIM16_BASE + STM32_GTIM_ARR_OFFSET) +#define STM32_TIM16_RCR (STM32_TIM16_BASE + STM32_GTIM_RCR_OFFSET) +#define STM32_TIM16_CCR1 (STM32_TIM16_BASE + STM32_GTIM_CCR1_OFFSET) +#define STM32_TIM16_BDTR (STM32_TIM16_BASE + STM32_GTIM_BDTR_OFFSET) +#define STM32_TIM16_DCR (STM32_TIM16_BASE + STM32_GTIM_DCR_OFFSET) +#define STM32_TIM16_DMAR (STM32_TIM16_BASE + STM32_GTIM_DMAR_OFFSET) +#define STM32_TIM16_OR (STM32_TIM16_BASE + STM32_GTIM_OR_OFFSET) + +#define STM32_TIM17_CR1 (STM32_TIM17_BASE + STM32_GTIM_CR1_OFFSET) +#define STM32_TIM17_CR2 (STM32_TIM17_BASE + STM32_GTIM_CR2_OFFSET) +#define STM32_TIM17_DIER (STM32_TIM17_BASE + STM32_GTIM_DIER_OFFSET) +#define STM32_TIM17_SR (STM32_TIM17_BASE + STM32_GTIM_SR_OFFSET) +#define STM32_TIM17_EGR (STM32_TIM17_BASE + STM32_GTIM_EGR_OFFSET) +#define STM32_TIM17_CCMR1 (STM32_TIM17_BASE + STM32_GTIM_CCMR1_OFFSET) +#define STM32_TIM17_CCER (STM32_TIM17_BASE + STM32_GTIM_CCER_OFFSET) +#define STM32_TIM17_CNT (STM32_TIM17_BASE + STM32_GTIM_CNT_OFFSET) +#define STM32_TIM17_PSC (STM32_TIM17_BASE + STM32_GTIM_PSC_OFFSET) +#define STM32_TIM17_ARR (STM32_TIM17_BASE + STM32_GTIM_ARR_OFFSET) +#define STM32_TIM17_RCR (STM32_TIM17_BASE + STM32_GTIM_RCR_OFFSET) +#define STM32_TIM17_CCR1 (STM32_TIM17_BASE + STM32_GTIM_CCR1_OFFSET) +#define STM32_TIM17_BDTR (STM32_TIM17_BASE + STM32_GTIM_BDTR_OFFSET) +#define STM32_TIM17_DCR (STM32_TIM17_BASE + STM32_GTIM_DCR_OFFSET) +#define STM32_TIM17_DMAR (STM32_TIM17_BASE + STM32_GTIM_DMAR_OFFSET) /* Basic Timers - TIM6 and TIM7 */ -#define STM32L5_TIM6_CR1 (STM32L5_TIM6_BASE + STM32L5_BTIM_CR1_OFFSET) -#define STM32L5_TIM6_CR2 (STM32L5_TIM6_BASE + STM32L5_BTIM_CR2_OFFSET) -#define STM32L5_TIM6_DIER (STM32L5_TIM6_BASE + STM32L5_BTIM_DIER_OFFSET) -#define STM32L5_TIM6_SR (STM32L5_TIM6_BASE + STM32L5_BTIM_SR_OFFSET) -#define STM32L5_TIM6_EGR (STM32L5_TIM6_BASE + STM32L5_BTIM_EGR_OFFSET) -#define STM32L5_TIM6_CNT (STM32L5_TIM6_BASE + STM32L5_BTIM_CNT_OFFSET) -#define STM32L5_TIM6_PSC (STM32L5_TIM6_BASE + STM32L5_BTIM_PSC_OFFSET) -#define STM32L5_TIM6_ARR (STM32L5_TIM6_BASE + STM32L5_BTIM_ARR_OFFSET) - -#define STM32L5_TIM7_CR1 (STM32L5_TIM7_BASE + STM32L5_BTIM_CR1_OFFSET) -#define STM32L5_TIM7_CR2 (STM32L5_TIM7_BASE + STM32L5_BTIM_CR2_OFFSET) -#define STM32L5_TIM7_DIER (STM32L5_TIM7_BASE + STM32L5_BTIM_DIER_OFFSET) -#define STM32L5_TIM7_SR (STM32L5_TIM7_BASE + STM32L5_BTIM_SR_OFFSET) -#define STM32L5_TIM7_EGR (STM32L5_TIM7_BASE + STM32L5_BTIM_EGR_OFFSET) -#define STM32L5_TIM7_CNT (STM32L5_TIM7_BASE + STM32L5_BTIM_CNT_OFFSET) -#define STM32L5_TIM7_PSC (STM32L5_TIM7_BASE + STM32L5_BTIM_PSC_OFFSET) -#define STM32L5_TIM7_ARR (STM32L5_TIM7_BASE + STM32L5_BTIM_ARR_OFFSET) +#define STM32_TIM6_CR1 (STM32_TIM6_BASE + STM32_BTIM_CR1_OFFSET) +#define STM32_TIM6_CR2 (STM32_TIM6_BASE + STM32_BTIM_CR2_OFFSET) +#define STM32_TIM6_DIER (STM32_TIM6_BASE + STM32_BTIM_DIER_OFFSET) +#define STM32_TIM6_SR (STM32_TIM6_BASE + STM32_BTIM_SR_OFFSET) +#define STM32_TIM6_EGR (STM32_TIM6_BASE + STM32_BTIM_EGR_OFFSET) +#define STM32_TIM6_CNT (STM32_TIM6_BASE + STM32_BTIM_CNT_OFFSET) +#define STM32_TIM6_PSC (STM32_TIM6_BASE + STM32_BTIM_PSC_OFFSET) +#define STM32_TIM6_ARR (STM32_TIM6_BASE + STM32_BTIM_ARR_OFFSET) + +#define STM32_TIM7_CR1 (STM32_TIM7_BASE + STM32_BTIM_CR1_OFFSET) +#define STM32_TIM7_CR2 (STM32_TIM7_BASE + STM32_BTIM_CR2_OFFSET) +#define STM32_TIM7_DIER (STM32_TIM7_BASE + STM32_BTIM_DIER_OFFSET) +#define STM32_TIM7_SR (STM32_TIM7_BASE + STM32_BTIM_SR_OFFSET) +#define STM32_TIM7_EGR (STM32_TIM7_BASE + STM32_BTIM_EGR_OFFSET) +#define STM32_TIM7_CNT (STM32_TIM7_BASE + STM32_BTIM_CNT_OFFSET) +#define STM32_TIM7_PSC (STM32_TIM7_BASE + STM32_BTIM_PSC_OFFSET) +#define STM32_TIM7_ARR (STM32_TIM7_BASE + STM32_BTIM_ARR_OFFSET) /* Register Bitfield Definitions ********************************************/ @@ -1059,4 +1059,4 @@ #define BTIM_EGR_UG (1 << 0) /* Bit 0: Update generation */ -#endif /* __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32L5_TIM_H */ +#endif /* __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32_TIM_H */ diff --git a/arch/arm/src/stm32l5/hardware/stm32l5_uart.h b/arch/arm/src/stm32l5/hardware/stm32l5_uart.h index b987bc439211e..14113ce50dbe8 100644 --- a/arch/arm/src/stm32l5/hardware/stm32l5_uart.h +++ b/arch/arm/src/stm32l5/hardware/stm32l5_uart.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32L5_UART_H -#define __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32L5_UART_H +#ifndef __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32_UART_H +#define __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32_UART_H /**************************************************************************** * Included Files @@ -37,94 +37,94 @@ /* Register Offsets *********************************************************/ -#define STM32L5_USART_CR1_OFFSET 0x0000 /* Control register 1 */ -#define STM32L5_USART_CR2_OFFSET 0x0004 /* Control register 2 */ -#define STM32L5_USART_CR3_OFFSET 0x0008 /* Control register 3 */ -#define STM32L5_USART_BRR_OFFSET 0x000c /* Baud Rate register */ -#define STM32L5_USART_GTPR_OFFSET 0x0010 /* Guard time and prescaler register */ -#define STM32L5_USART_RTOR_OFFSET 0x0014 /* Receiver timeout register */ -#define STM32L5_USART_RQR_OFFSET 0x0018 /* Request register */ -#define STM32L5_USART_ISR_OFFSET 0x001c /* Interrupt and status register */ -#define STM32L5_USART_ICR_OFFSET 0x0020 /* Interrupt flag clear register */ -#define STM32L5_USART_RDR_OFFSET 0x0024 /* Receive Data register */ -#define STM32L5_USART_TDR_OFFSET 0x0028 /* Transmit Data register */ -#define STM32L5_USART_PRESC_OFFSET 0x002c /* Prescaler register */ +#define STM32_USART_CR1_OFFSET 0x0000 /* Control register 1 */ +#define STM32_USART_CR2_OFFSET 0x0004 /* Control register 2 */ +#define STM32_USART_CR3_OFFSET 0x0008 /* Control register 3 */ +#define STM32_USART_BRR_OFFSET 0x000c /* Baud Rate register */ +#define STM32_USART_GTPR_OFFSET 0x0010 /* Guard time and prescaler register */ +#define STM32_USART_RTOR_OFFSET 0x0014 /* Receiver timeout register */ +#define STM32_USART_RQR_OFFSET 0x0018 /* Request register */ +#define STM32_USART_ISR_OFFSET 0x001c /* Interrupt and status register */ +#define STM32_USART_ICR_OFFSET 0x0020 /* Interrupt flag clear register */ +#define STM32_USART_RDR_OFFSET 0x0024 /* Receive Data register */ +#define STM32_USART_TDR_OFFSET 0x0028 /* Transmit Data register */ +#define STM32_USART_PRESC_OFFSET 0x002c /* Prescaler register */ /* Register Addresses *******************************************************/ -#if STM32L5_NUSART > 0 -# define STM32L5_USART1_CR1 (STM32L5_USART1_BASE + STM32L5_USART_CR1_OFFSET) -# define STM32L5_USART1_CR2 (STM32L5_USART1_BASE + STM32L5_USART_CR2_OFFSET) -# define STM32L5_USART1_CR3 (STM32L5_USART1_BASE + STM32L5_USART_CR3_OFFSET) -# define STM32L5_USART1_BRR (STM32L5_USART1_BASE + STM32L5_USART_BRR_OFFSET) -# define STM32L5_USART1_GTPR (STM32L5_USART1_BASE + STM32L5_USART_GTPR_OFFSET) -# define STM32L5_USART1_RTOR (STM32L5_USART1_BASE + STM32L5_USART_RTOR_OFFSET) -# define STM32L5_USART1_RQR (STM32L5_USART1_BASE + STM32L5_USART_RQR_OFFSET) -# define STM32L5_USART1_ISR (STM32L5_USART1_BASE + STM32L5_USART_ISR_OFFSET) -# define STM32L5_USART1_ICR (STM32L5_USART1_BASE + STM32L5_USART_ICR_OFFSET) -# define STM32L5_USART1_RDR (STM32L5_USART1_BASE + STM32L5_USART_RDR_OFFSET) -# define STM32L5_USART1_TDR (STM32L5_USART1_BASE + STM32L5_USART_TDR_OFFSET) -# define STM32L5_USART1_PRESC (STM32L5_USART1_BASE + STM32L5_USART_PRESC_OFFSET) +#if STM32_NUSART > 0 +# define STM32_USART1_CR1 (STM32_USART1_BASE + STM32_USART_CR1_OFFSET) +# define STM32_USART1_CR2 (STM32_USART1_BASE + STM32_USART_CR2_OFFSET) +# define STM32_USART1_CR3 (STM32_USART1_BASE + STM32_USART_CR3_OFFSET) +# define STM32_USART1_BRR (STM32_USART1_BASE + STM32_USART_BRR_OFFSET) +# define STM32_USART1_GTPR (STM32_USART1_BASE + STM32_USART_GTPR_OFFSET) +# define STM32_USART1_RTOR (STM32_USART1_BASE + STM32_USART_RTOR_OFFSET) +# define STM32_USART1_RQR (STM32_USART1_BASE + STM32_USART_RQR_OFFSET) +# define STM32_USART1_ISR (STM32_USART1_BASE + STM32_USART_ISR_OFFSET) +# define STM32_USART1_ICR (STM32_USART1_BASE + STM32_USART_ICR_OFFSET) +# define STM32_USART1_RDR (STM32_USART1_BASE + STM32_USART_RDR_OFFSET) +# define STM32_USART1_TDR (STM32_USART1_BASE + STM32_USART_TDR_OFFSET) +# define STM32_USART1_PRESC (STM32_USART1_BASE + STM32_USART_PRESC_OFFSET) #endif -#if STM32L5_NUSART > 1 -# define STM32L5_USART2_CR1 (STM32L5_USART2_BASE + STM32L5_USART_CR1_OFFSET) -# define STM32L5_USART2_CR2 (STM32L5_USART2_BASE + STM32L5_USART_CR2_OFFSET) -# define STM32L5_USART2_CR3 (STM32L5_USART2_BASE + STM32L5_USART_CR3_OFFSET) -# define STM32L5_USART2_BRR (STM32L5_USART2_BASE + STM32L5_USART_BRR_OFFSET) -# define STM32L5_USART2_GTPR (STM32L5_USART2_BASE + STM32L5_USART_GTPR_OFFSET) -# define STM32L5_USART2_RTOR (STM32L5_USART2_BASE + STM32L5_USART_RTOR_OFFSET) -# define STM32L5_USART2_RQR (STM32L5_USART2_BASE + STM32L5_USART_RQR_OFFSET) -# define STM32L5_USART2_ISR (STM32L5_USART2_BASE + STM32L5_USART_ISR_OFFSET) -# define STM32L5_USART2_ICR (STM32L5_USART2_BASE + STM32L5_USART_ICR_OFFSET) -# define STM32L5_USART2_RDR (STM32L5_USART2_BASE + STM32L5_USART_RDR_OFFSET) -# define STM32L5_USART2_TDR (STM32L5_USART2_BASE + STM32L5_USART_TDR_OFFSET) -# define STM32L5_USART2_PRESC (STM32L5_USART2_BASE + STM32L5_USART_PRESC_OFFSET) +#if STM32_NUSART > 1 +# define STM32_USART2_CR1 (STM32_USART2_BASE + STM32_USART_CR1_OFFSET) +# define STM32_USART2_CR2 (STM32_USART2_BASE + STM32_USART_CR2_OFFSET) +# define STM32_USART2_CR3 (STM32_USART2_BASE + STM32_USART_CR3_OFFSET) +# define STM32_USART2_BRR (STM32_USART2_BASE + STM32_USART_BRR_OFFSET) +# define STM32_USART2_GTPR (STM32_USART2_BASE + STM32_USART_GTPR_OFFSET) +# define STM32_USART2_RTOR (STM32_USART2_BASE + STM32_USART_RTOR_OFFSET) +# define STM32_USART2_RQR (STM32_USART2_BASE + STM32_USART_RQR_OFFSET) +# define STM32_USART2_ISR (STM32_USART2_BASE + STM32_USART_ISR_OFFSET) +# define STM32_USART2_ICR (STM32_USART2_BASE + STM32_USART_ICR_OFFSET) +# define STM32_USART2_RDR (STM32_USART2_BASE + STM32_USART_RDR_OFFSET) +# define STM32_USART2_TDR (STM32_USART2_BASE + STM32_USART_TDR_OFFSET) +# define STM32_USART2_PRESC (STM32_USART2_BASE + STM32_USART_PRESC_OFFSET) #endif -#if STM32L5_NUSART > 2 -# define STM32L5_USART3_CR1 (STM32L5_USART3_BASE + STM32L5_USART_CR1_OFFSET) -# define STM32L5_USART3_CR2 (STM32L5_USART3_BASE + STM32L5_USART_CR2_OFFSET) -# define STM32L5_USART3_CR3 (STM32L5_USART3_BASE + STM32L5_USART_CR3_OFFSET) -# define STM32L5_USART3_BRR (STM32L5_USART3_BASE + STM32L5_USART_BRR_OFFSET) -# define STM32L5_USART3_GTPR (STM32L5_USART3_BASE + STM32L5_USART_GTPR_OFFSET) -# define STM32L5_USART3_RTOR (STM32L5_USART3_BASE + STM32L5_USART_RTOR_OFFSET) -# define STM32L5_USART3_RQR (STM32L5_USART3_BASE + STM32L5_USART_RQR_OFFSET) -# define STM32L5_USART3_ISR (STM32L5_USART3_BASE + STM32L5_USART_ISR_OFFSET) -# define STM32L5_USART3_ICR (STM32L5_USART3_BASE + STM32L5_USART_ICR_OFFSET) -# define STM32L5_USART3_RDR (STM32L5_USART3_BASE + STM32L5_USART_RDR_OFFSET) -# define STM32L5_USART3_TDR (STM32L5_USART3_BASE + STM32L5_USART_TDR_OFFSET) -# define STM32L5_USART3_PRESC (STM32L5_USART3_BASE + STM32L5_USART_PRESC_OFFSET) +#if STM32_NUSART > 2 +# define STM32_USART3_CR1 (STM32_USART3_BASE + STM32_USART_CR1_OFFSET) +# define STM32_USART3_CR2 (STM32_USART3_BASE + STM32_USART_CR2_OFFSET) +# define STM32_USART3_CR3 (STM32_USART3_BASE + STM32_USART_CR3_OFFSET) +# define STM32_USART3_BRR (STM32_USART3_BASE + STM32_USART_BRR_OFFSET) +# define STM32_USART3_GTPR (STM32_USART3_BASE + STM32_USART_GTPR_OFFSET) +# define STM32_USART3_RTOR (STM32_USART3_BASE + STM32_USART_RTOR_OFFSET) +# define STM32_USART3_RQR (STM32_USART3_BASE + STM32_USART_RQR_OFFSET) +# define STM32_USART3_ISR (STM32_USART3_BASE + STM32_USART_ISR_OFFSET) +# define STM32_USART3_ICR (STM32_USART3_BASE + STM32_USART_ICR_OFFSET) +# define STM32_USART3_RDR (STM32_USART3_BASE + STM32_USART_RDR_OFFSET) +# define STM32_USART3_TDR (STM32_USART3_BASE + STM32_USART_TDR_OFFSET) +# define STM32_USART3_PRESC (STM32_USART3_BASE + STM32_USART_PRESC_OFFSET) #endif -#if STM32L5_NUSART > 3 -# define STM32L5_UART4_CR1 (STM32L5_UART4_BASE + STM32L5_USART_CR1_OFFSET) -# define STM32L5_UART4_CR2 (STM32L5_UART4_BASE + STM32L5_USART_CR2_OFFSET) -# define STM32L5_UART4_CR3 (STM32L5_UART4_BASE + STM32L5_USART_CR3_OFFSET) -# define STM32L5_UART4_BRR (STM32L5_UART4_BASE + STM32L5_USART_BRR_OFFSET) -# define STM32L5_UART4_GTPR (STM32L5_UART4_BASE + STM32L5_USART_GTPR_OFFSET) -# define STM32L5_UART4_RTOR (STM32L5_UART4_BASE + STM32L5_USART_RTOR_OFFSET) -# define STM32L5_UART4_RQR (STM32L5_UART4_BASE + STM32L5_USART_RQR_OFFSET) -# define STM32L5_UART4_ISR (STM32L5_UART4_BASE + STM32L5_USART_ISR_OFFSET) -# define STM32L5_UART4_ICR (STM32L5_UART4_BASE + STM32L5_USART_ICR_OFFSET) -# define STM32L5_UART4_RDR (STM32L5_UART4_BASE + STM32L5_USART_RDR_OFFSET) -# define STM32L5_UART4_TDR (STM32L5_UART4_BASE + STM32L5_USART_TDR_OFFSET) -# define STM32L5_UART4_PRESC (STM32L5_UART4_BASE + STM32L5_USART_PRESC_OFFSET) +#if STM32_NUSART > 3 +# define STM32_UART4_CR1 (STM32_UART4_BASE + STM32_USART_CR1_OFFSET) +# define STM32_UART4_CR2 (STM32_UART4_BASE + STM32_USART_CR2_OFFSET) +# define STM32_UART4_CR3 (STM32_UART4_BASE + STM32_USART_CR3_OFFSET) +# define STM32_UART4_BRR (STM32_UART4_BASE + STM32_USART_BRR_OFFSET) +# define STM32_UART4_GTPR (STM32_UART4_BASE + STM32_USART_GTPR_OFFSET) +# define STM32_UART4_RTOR (STM32_UART4_BASE + STM32_USART_RTOR_OFFSET) +# define STM32_UART4_RQR (STM32_UART4_BASE + STM32_USART_RQR_OFFSET) +# define STM32_UART4_ISR (STM32_UART4_BASE + STM32_USART_ISR_OFFSET) +# define STM32_UART4_ICR (STM32_UART4_BASE + STM32_USART_ICR_OFFSET) +# define STM32_UART4_RDR (STM32_UART4_BASE + STM32_USART_RDR_OFFSET) +# define STM32_UART4_TDR (STM32_UART4_BASE + STM32_USART_TDR_OFFSET) +# define STM32_UART4_PRESC (STM32_UART4_BASE + STM32_USART_PRESC_OFFSET) #endif -#if STM32L5_NUSART > 4 -# define STM32L5_UART5_CR1 (STM32L5_UART5_BASE + STM32L5_USART_CR1_OFFSET) -# define STM32L5_UART5_CR2 (STM32L5_UART5_BASE + STM32L5_USART_CR2_OFFSET) -# define STM32L5_UART5_CR3 (STM32L5_UART5_BASE + STM32L5_USART_CR3_OFFSET) -# define STM32L5_UART5_BRR (STM32L5_UART5_BASE + STM32L5_USART_BRR_OFFSET) -# define STM32L5_UART5_GTPR (STM32L5_UART5_BASE + STM32L5_USART_GTPR_OFFSET) -# define STM32L5_UART5_RTOR (STM32L5_UART5_BASE + STM32L5_USART_RTOR_OFFSET) -# define STM32L5_UART5_RQR (STM32L5_UART5_BASE + STM32L5_USART_RQR_OFFSET) -# define STM32L5_UART5_ISR (STM32L5_UART5_BASE + STM32L5_USART_ISR_OFFSET) -# define STM32L5_UART5_ICR (STM32L5_UART5_BASE + STM32L5_USART_ICR_OFFSET) -# define STM32L5_UART5_RDR (STM32L5_UART5_BASE + STM32L5_USART_RDR_OFFSET) -# define STM32L5_UART5_TDR (STM32L5_UART5_BASE + STM32L5_USART_TDR_OFFSET) -# define STM32L5_UART5_PRESC (STM32L5_UART5_BASE + STM32L5_USART_PRESC_OFFSET) +#if STM32_NUSART > 4 +# define STM32_UART5_CR1 (STM32_UART5_BASE + STM32_USART_CR1_OFFSET) +# define STM32_UART5_CR2 (STM32_UART5_BASE + STM32_USART_CR2_OFFSET) +# define STM32_UART5_CR3 (STM32_UART5_BASE + STM32_USART_CR3_OFFSET) +# define STM32_UART5_BRR (STM32_UART5_BASE + STM32_USART_BRR_OFFSET) +# define STM32_UART5_GTPR (STM32_UART5_BASE + STM32_USART_GTPR_OFFSET) +# define STM32_UART5_RTOR (STM32_UART5_BASE + STM32_USART_RTOR_OFFSET) +# define STM32_UART5_RQR (STM32_UART5_BASE + STM32_USART_RQR_OFFSET) +# define STM32_UART5_ISR (STM32_UART5_BASE + STM32_USART_ISR_OFFSET) +# define STM32_UART5_ICR (STM32_UART5_BASE + STM32_USART_ICR_OFFSET) +# define STM32_UART5_RDR (STM32_UART5_BASE + STM32_USART_RDR_OFFSET) +# define STM32_UART5_TDR (STM32_UART5_BASE + STM32_USART_TDR_OFFSET) +# define STM32_UART5_PRESC (STM32_UART5_BASE + STM32_USART_PRESC_OFFSET) #endif /* Register Bitfield Definitions ********************************************/ @@ -306,4 +306,4 @@ * Public Data ****************************************************************************/ -#endif /* __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32L5_UART_H */ +#endif /* __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32_UART_H */ diff --git a/arch/arm/src/stm32l5/stm32.h b/arch/arm/src/stm32l5/stm32.h new file mode 100644 index 0000000000000..9ce64f1178564 --- /dev/null +++ b/arch/arm/src/stm32l5/stm32.h @@ -0,0 +1,50 @@ +/**************************************************************************** + * arch/arm/src/stm32l5/stm32.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32L5_STM32_H +#define __ARCH_ARM_SRC_STM32L5_STM32_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include +#include + +#include "arm_internal.h" + +/* Peripherals **************************************************************/ + +#include "chip.h" +#include "stm32l5_dbgmcu.h" +#include "stm32l5_flash.h" +#include "stm32l5_gpio.h" +#include "stm32l5_pwr.h" +#include "stm32l5_rcc.h" +#include "stm32l5_spi.h" +#include "stm32l5_tim.h" +#include "stm32l5_uart.h" +#include "stm32l5_lowputc.h" + +#endif /* __ARCH_ARM_SRC_STM32L5_STM32_H */ diff --git a/arch/arm/src/stm32l5/stm32l5.h b/arch/arm/src/stm32l5/stm32l5.h deleted file mode 100644 index 7cedda9b78c90..0000000000000 --- a/arch/arm/src/stm32l5/stm32l5.h +++ /dev/null @@ -1,50 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32l5/stm32l5.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32L5_STM32L5_H -#define __ARCH_ARM_SRC_STM32L5_STM32L5_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include -#include -#include - -#include "arm_internal.h" - -/* Peripherals **************************************************************/ - -#include "chip.h" -#include "stm32l5_dbgmcu.h" -#include "stm32l5_flash.h" -#include "stm32l5_gpio.h" -#include "stm32l5_pwr.h" -#include "stm32l5_rcc.h" -#include "stm32l5_spi.h" -#include "stm32l5_tim.h" -#include "stm32l5_uart.h" -#include "stm32l5_lowputc.h" - -#endif /* __ARCH_ARM_SRC_STM32L5_STM32L5_H */ diff --git a/arch/arm/src/stm32l5/stm32l562xx_rcc.c b/arch/arm/src/stm32l5/stm32l562xx_rcc.c index b1f582519e6ec..7de591b215d8f 100644 --- a/arch/arm/src/stm32l5/stm32l562xx_rcc.c +++ b/arch/arm/src/stm32l5/stm32l562xx_rcc.c @@ -56,13 +56,13 @@ static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1, /* HSE divisor to yield ~1MHz RTC clock */ -#define HSE_DIVISOR (STM32L5_HSE_FREQUENCY + 500000) / 1000000 +#define HSE_DIVISOR (STM32_HSE_FREQUENCY + 500000) / 1000000 /* Determine if board wants to use HSI48 as 48 MHz oscillator. */ -#if defined(CONFIG_STM32L5_HAVE_HSI48) && defined(STM32L5_USE_CLK48) -# if STM32L5_CLK48_SEL == RCC_CCIPR_CLK48SEL_HSI48 -# define STM32L5_USE_HSI48 +#if defined(CONFIG_STM32_HAVE_HSI48) && defined(STM32_USE_CLK48) +# if STM32_CLK48_SEL == RCC_CCIPR_CLK48SEL_HSI48 +# define STM32_USE_HSI48 # endif #endif @@ -90,51 +90,51 @@ static inline void rcc_enableahb1(void) * selected AHB1 peripherals. */ - regval = getreg32(STM32L5_RCC_AHB1ENR); + regval = getreg32(STM32_RCC_AHB1ENR); -#ifdef CONFIG_STM32L5_DMA1 +#ifdef CONFIG_STM32_DMA1 /* DMA 1 clock enable */ regval |= RCC_AHB1ENR_DMA1EN; #endif -#ifdef CONFIG_STM32L5_DMA2 +#ifdef CONFIG_STM32_DMA2 /* DMA 2 clock enable */ regval |= RCC_AHB1ENR_DMA2EN; #endif -#ifdef CONFIG_STM32L5_DMAMUX1 +#ifdef CONFIG_STM32_DMAMUX1 /* DMAMUX1 clock enable */ regval |= RCC_AHB1ENR_DMAMUX1EN; #endif -#ifdef CONFIG_STM32L5_FLASHEN +#ifdef CONFIG_STM32_FLASHEN /* Flash memory interface clock enable */ regval |= RCC_AHB1ENR_FLASHEN; #endif -#ifdef CONFIG_STM32L5_CRC +#ifdef CONFIG_STM32_CRC /* CRC clock enable */ regval |= RCC_AHB1ENR_CRCEN; #endif -#ifdef CONFIG_STM32L5_TSC +#ifdef CONFIG_STM32_TSC /* TSC clock enable */ regval |= RCC_AHB1ENR_TSCEN; #endif -#ifdef CONFIG_STM32L5_GTZCEN +#ifdef CONFIG_STM32_GTZCEN /* TSC clock enable */ regval |= RCC_AHB1ENR_GTZEN; #endif - putreg32(regval, STM32L5_RCC_AHB1ENR); /* Enable peripherals */ + putreg32(regval, STM32_RCC_AHB1ENR); /* Enable peripherals */ } /**************************************************************************** @@ -153,79 +153,79 @@ static inline void rcc_enableahb2(void) * selected AHB2 peripherals. */ - regval = getreg32(STM32L5_RCC_AHB2ENR); + regval = getreg32(STM32_RCC_AHB2ENR); /* Enable GPIOA, GPIOB, .... GPIOH */ -#if STM32L5_NPORTS > 0 +#if STM32_NPORTS > 0 regval |= (RCC_AHB2ENR_GPIOAEN -#if STM32L5_NPORTS > 1 +#if STM32_NPORTS > 1 | RCC_AHB2ENR_GPIOBEN #endif -#if STM32L5_NPORTS > 2 +#if STM32_NPORTS > 2 | RCC_AHB2ENR_GPIOCEN #endif -#if STM32L5_NPORTS > 3 +#if STM32_NPORTS > 3 | RCC_AHB2ENR_GPIODEN #endif -#if STM32L5_NPORTS > 4 +#if STM32_NPORTS > 4 | RCC_AHB2ENR_GPIOEEN #endif -#if STM32L5_NPORTS > 5 +#if STM32_NPORTS > 5 | RCC_AHB2ENR_GPIOFEN #endif -#if STM32L5_NPORTS > 6 +#if STM32_NPORTS > 6 | RCC_AHB2ENR_GPIOGEN #endif -#if STM32L5_NPORTS > 7 +#if STM32_NPORTS > 7 | RCC_AHB2ENR_GPIOHEN #endif ); #endif -#if defined(CONFIG_STM32L5_ADC) +#if defined(CONFIG_STM32_ADC) /* ADC clock enable */ regval |= RCC_AHB2ENR_ADCEN; #endif -#ifdef CONFIG_STM32L5_AES +#ifdef CONFIG_STM32_AES /* Cryptographic modules clock enable */ regval |= RCC_AHB2ENR_AESEN; #endif -#ifdef CONFIG_STM32L5_HASH +#ifdef CONFIG_STM32_HASH /* Hash module enable */ regval |= RCC_AHB2ENR_HASHEN #endif -#ifdef CONFIG_STM32L5_RNG +#ifdef CONFIG_STM32_RNG /* Random number generator clock enable */ regval |= RCC_AHB2ENR_RNGEN; #endif -#ifdef CONFIG_STM32L5_PKAEN +#ifdef CONFIG_STM32_PKAEN /* Public Key Accelerator clock enable */ regval |= RCC_AHB2ENR_PKAEN; #endif -#ifdef CONFIG_STM32L5_OTFDEC1EN +#ifdef CONFIG_STM32_OTFDEC1EN /* On-the-fly-decryption module clock enable */ regval |= RCC_AHB2ENR_OTFDEC1EN; #endif -#ifdef CONFIG_STM32L5_SDMMC1EN +#ifdef CONFIG_STM32_SDMMC1EN /* SDMMC1 clock enable */ regval |= RCC_AHB2ENR_SDMMC1EN; #endif - putreg32(regval, STM32L5_RCC_AHB2ENR); /* Enable peripherals */ + putreg32(regval, STM32_RCC_AHB2ENR); /* Enable peripherals */ } /**************************************************************************** @@ -244,21 +244,21 @@ static inline void rcc_enableahb3(void) * selected AHB3 peripherals. */ - regval = getreg32(STM32L5_RCC_AHB3ENR); + regval = getreg32(STM32_RCC_AHB3ENR); -#ifdef CONFIG_STM32L5_FMC +#ifdef CONFIG_STM32_FMC /* Flexible memory controller clock enable */ regval |= RCC_AHB3ENR_FMCEN; #endif -#ifdef CONFIG_STM32L5_OCTOSPI1 +#ifdef CONFIG_STM32_OCTOSPI1 /* OCTOSPI1 module clock enable */ regval |= RCC_AHB3ENR_OSPI1EN; #endif - putreg32(regval, STM32L5_RCC_AHB3ENR); /* Enable peripherals */ + putreg32(regval, STM32_RCC_AHB3ENR); /* Enable peripherals */ } /**************************************************************************** @@ -277,112 +277,112 @@ static inline void rcc_enableapb1(void) * selected APB1 peripherals. */ - regval = getreg32(STM32L5_RCC_APB1ENR1); + regval = getreg32(STM32_RCC_APB1ENR1); -#ifdef CONFIG_STM32L5_TIM2 +#ifdef CONFIG_STM32_TIM2 /* TIM2 clock enable */ regval |= RCC_APB1ENR1_TIM2EN; #endif -#ifdef CONFIG_STM32L5_TIM3 +#ifdef CONFIG_STM32_TIM3 /* TIM3 clock enable */ regval |= RCC_APB1ENR1_TIM3EN; #endif -#ifdef CONFIG_STM32L5_TIM4 +#ifdef CONFIG_STM32_TIM4 /* TIM4 clock enable */ regval |= RCC_APB1ENR1_TIM4EN; #endif -#ifdef CONFIG_STM32L5_TIM5 +#ifdef CONFIG_STM32_TIM5 /* TIM5 clock enable */ regval |= RCC_APB1ENR1_TIM5EN; #endif -#ifdef CONFIG_STM32L5_TIM6 +#ifdef CONFIG_STM32_TIM6 /* TIM6 clock enable */ regval |= RCC_APB1ENR1_TIM6EN; #endif -#ifdef CONFIG_STM32L5_TIM7 +#ifdef CONFIG_STM32_TIM7 /* TIM7 clock enable */ regval |= RCC_APB1ENR1_TIM7EN; #endif -#ifdef CONFIG_STM32L5_RTC +#ifdef CONFIG_STM32_RTC /* RTC APB clock enable */ regval |= RCC_APB1ENR1_RTCAPBEN; #endif -#ifdef CONFIG_STM32L5_WWDGEN +#ifdef CONFIG_STM32_WWDGEN /* Windowed Watchdog clock enable */ regval |= RCC_APB1ENR1_WWDGEN; #endif -#ifdef CONFIG_STM32L5_SPI2 +#ifdef CONFIG_STM32_SPI2 /* SPI2 clock enable */ regval |= RCC_APB1ENR1_SPI2EN; #endif -#ifdef CONFIG_STM32L5_SPI3 +#ifdef CONFIG_STM32_SPI3 /* SPI3 clock enable */ regval |= RCC_APB1ENR1_SPI3EN; #endif -#ifdef CONFIG_STM32L5_USART2 +#ifdef CONFIG_STM32_USART2 /* USART 2 clock enable */ regval |= RCC_APB1ENR1_USART2EN; #endif -#ifdef CONFIG_STM32L5_USART3 +#ifdef CONFIG_STM32_USART3 /* USART3 clock enable */ regval |= RCC_APB1ENR1_USART3EN; #endif -#ifdef CONFIG_STM32L5_UART4 +#ifdef CONFIG_STM32_UART4 /* UART4 clock enable */ regval |= RCC_APB1ENR1_UART4EN; #endif -#ifdef CONFIG_STM32L5_UART5 +#ifdef CONFIG_STM32_UART5 /* UART5 clock enable */ regval |= RCC_APB1ENR1_UART5EN; #endif -#ifdef CONFIG_STM32L5_I2C1 +#ifdef CONFIG_STM32_I2C1 /* I2C1 clock enable */ regval |= RCC_APB1ENR1_I2C1EN; #endif -#ifdef CONFIG_STM32L5_I2C2 +#ifdef CONFIG_STM32_I2C2 /* I2C2 clock enable */ regval |= RCC_APB1ENR1_I2C2EN; #endif -#ifdef CONFIG_STM32L5_I2C3 +#ifdef CONFIG_STM32_I2C3 /* I2C3 clock enable */ regval |= RCC_APB1ENR1_I2C3EN; #endif -#ifdef STM32L5_USE_HSI48 - if (STM32L5_HSI48_SYNCSRC != SYNCSRC_NONE) +#ifdef STM32_USE_HSI48 + if (STM32_HSI48_SYNCSRC != SYNCSRC_NONE) { /* Clock Recovery System clock enable */ @@ -396,73 +396,73 @@ static inline void rcc_enableapb1(void) regval |= RCC_APB1ENR1_PWREN; -#if defined (CONFIG_STM32L5_DAC1) +#if defined (CONFIG_STM32_DAC1) /* DAC1 interface clock enable */ regval |= RCC_APB1ENR1_DAC1EN; #endif -#ifdef CONFIG_STM32L5_OPAMP +#ifdef CONFIG_STM32_OPAMP /* OPAMP clock enable */ regval |= RCC_APB1ENR1_OPAMPEN; #endif -#ifdef CONFIG_STM32L5_LPTIM1 +#ifdef CONFIG_STM32_LPTIM1 /* Low power timer 1 clock enable */ regval |= RCC_APB1ENR1_LPTIM1EN; #endif - putreg32(regval, STM32L5_RCC_APB1ENR1); /* Enable peripherals */ + putreg32(regval, STM32_RCC_APB1ENR1); /* Enable peripherals */ /* Second APB1 register */ - regval = getreg32(STM32L5_RCC_APB1ENR2); + regval = getreg32(STM32_RCC_APB1ENR2); -#ifdef CONFIG_STM32L5_LPUART1 +#ifdef CONFIG_STM32_LPUART1 /* Low power uart clock enable */ regval |= RCC_APB1ENR2_LPUART1EN; #endif -#ifdef CONFIG_STM32L5_I2C4 +#ifdef CONFIG_STM32_I2C4 /* I2C4 clock enable */ regval |= RCC_APB1ENR2_I2C4EN; #endif -#ifdef CONFIG_STM32L5_LPTIM2 +#ifdef CONFIG_STM32_LPTIM2 /* Low power timer 2 clock enable */ regval |= RCC_APB1ENR2_LPTIM2EN; #endif -#ifdef CONFIG_STM32L5_LPTIM3 +#ifdef CONFIG_STM32_LPTIM3 /* Low power timer 3 clock enable */ regval |= RCC_APB1ENR2_LPTIM3EN; #endif -#ifdef CONFIG_STM32L5_FDCAN1 +#ifdef CONFIG_STM32_FDCAN1 /* FDCAN1 clock enable */ regval |= RCC_APB1ENR2_FDCAN1EN; #endif -#ifdef CONFIG_STM32L5_USBFS +#ifdef CONFIG_STM32_USBFS /* USB FS clock enable */ regval |= RCC_APB1ENR2_USBFSEN; #endif -#ifdef CONFIG_STM32L5_UCPD1 +#ifdef CONFIG_STM32_UCPD1 /* UCPD1 clock enable */ regval |= RCC_APB1ENR2_UCPD1EN; #endif - putreg32(regval, STM32L5_RCC_APB1ENR2); /* Enable peripherals */ + putreg32(regval, STM32_RCC_APB1ENR2); /* Enable peripherals */ } /**************************************************************************** @@ -481,9 +481,9 @@ static inline void rcc_enableapb2(void) * selected APB2 peripherals. */ - regval = getreg32(STM32L5_RCC_APB2ENR); + regval = getreg32(STM32_RCC_APB2ENR); -#if defined(CONFIG_STM32L5_SYSCFG) || defined(CONFIG_STM32L5_COMP) +#if defined(CONFIG_STM32_SYSCFG) || defined(CONFIG_STM32_COMP) /* System configuration controller, comparators, and voltage reference * buffer clock enable */ @@ -491,67 +491,67 @@ static inline void rcc_enableapb2(void) regval |= RCC_APB2ENR_SYSCFGEN; #endif -#ifdef CONFIG_STM32L5_TIM1 +#ifdef CONFIG_STM32_TIM1 /* TIM1 clock enable */ regval |= RCC_APB2ENR_TIM1EN; #endif -#ifdef CONFIG_STM32L5_SPI1 +#ifdef CONFIG_STM32_SPI1 /* SPI1 clock enable */ regval |= RCC_APB2ENR_SPI1EN; #endif -#ifdef CONFIG_STM32L5_TIM8 +#ifdef CONFIG_STM32_TIM8 /* TIM8 clock enable */ regval |= RCC_APB2ENR_TIM8EN; #endif -#ifdef CONFIG_STM32L5_USART1 +#ifdef CONFIG_STM32_USART1 /* USART1 clock enable */ regval |= RCC_APB2ENR_USART1EN; #endif -#ifdef CONFIG_STM32L5_TIM15 +#ifdef CONFIG_STM32_TIM15 /* TIM15 clock enable */ regval |= RCC_APB2ENR_TIM15EN; #endif -#ifdef CONFIG_STM32L5_TIM16 +#ifdef CONFIG_STM32_TIM16 /* TIM16 clock enable */ regval |= RCC_APB2ENR_TIM16EN; #endif -#ifdef CONFIG_STM32L5_TIM17 +#ifdef CONFIG_STM32_TIM17 /* TIM17 clock enable */ regval |= RCC_APB2ENR_TIM17EN; #endif -#ifdef CONFIG_STM32L5_SAI1 +#ifdef CONFIG_STM32_SAI1 /* SAI1 clock enable */ regval |= RCC_APB2ENR_SAI1EN; #endif -#ifdef CONFIG_STM32L5_SAI2 +#ifdef CONFIG_STM32_SAI2 /* SAI2 clock enable */ regval |= RCC_APB2ENR_SAI2EN; #endif -#ifdef CONFIG_STM32L5_DFSDM1 +#ifdef CONFIG_STM32_DFSDM1 /* DFSDM clock enable */ regval |= RCC_APB2ENR_DFSDMEN; #endif - putreg32(regval, STM32L5_RCC_APB2ENR); /* Enable peripherals */ + putreg32(regval, STM32_RCC_APB2ENR); /* Enable peripherals */ } /**************************************************************************** @@ -575,10 +575,10 @@ static inline void rcc_enableccip(void) ****************************************************************************/ /**************************************************************************** - * Name: stm32l5_rcc_enableperipherals + * Name: stm32_rcc_enableperipherals ****************************************************************************/ -void stm32l5_rcc_enableperipherals(void) +void stm32_rcc_enableperipherals(void) { rcc_enableccip(); rcc_enableahb1(); @@ -589,7 +589,7 @@ void stm32l5_rcc_enableperipherals(void) } /**************************************************************************** - * Name: stm32l5_stdclockconfig + * Name: stm32_stdclockconfig * * Description: * Called to change to new clock based on settings in board.h @@ -598,18 +598,18 @@ void stm32l5_rcc_enableperipherals(void) * power clocking modes! ****************************************************************************/ -#ifndef CONFIG_ARCH_BOARD_STM32L5_CUSTOM_CLOCKCONFIG -void stm32l5_stdclockconfig(void) +#ifndef CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG +void stm32_stdclockconfig(void) { uint32_t regval; volatile int32_t timeout; -#if defined(STM32L5_BOARD_USEHSI) || defined(STM32L5_I2C_USE_HSI16) +#if defined(STM32_BOARD_USEHSI) || defined(STM32_I2C_USE_HSI16) /* Enable Internal High-Speed Clock (HSI) */ - regval = getreg32(STM32L5_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_HSION; /* Enable HSI */ - putreg32(regval, STM32L5_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Wait until the HSI is ready (or until a timeout elapsed) */ @@ -617,7 +617,7 @@ void stm32l5_stdclockconfig(void) { /* Check if the HSIRDY flag is the set in the CR */ - if ((getreg32(STM32L5_RCC_CR) & RCC_CR_HSIRDY) != 0) + if ((getreg32(STM32_RCC_CR) & RCC_CR_HSIRDY) != 0) { /* If so, then break-out with timeout > 0 */ @@ -626,17 +626,17 @@ void stm32l5_stdclockconfig(void) } #endif -#if defined(STM32L5_BOARD_USEHSI) +#if defined(STM32_BOARD_USEHSI) /* Already set above */ -#elif defined(STM32L5_BOARD_USEMSI) +#elif defined(STM32_BOARD_USEMSI) /* Enable Internal Multi-Speed Clock (MSI) */ /* Wait until the MSI is either off or ready (or until a timeout elapsed) */ for (timeout = MSIRDY_TIMEOUT; timeout > 0; timeout--) { - if ((regval = getreg32(STM32L5_RCC_CR)), + if ((regval = getreg32(STM32_RCC_CR)), (regval & RCC_CR_MSIRDY) || ~(regval & RCC_CR_MSION)) { /* If so, then break-out with timeout > 0 */ @@ -647,9 +647,9 @@ void stm32l5_stdclockconfig(void) /* setting MSIRANGE */ - regval = getreg32(STM32L5_RCC_CR); - regval |= (STM32L5_BOARD_MSIRANGE | RCC_CR_MSION); /* Enable MSI and frequency */ - putreg32(regval, STM32L5_RCC_CR); + regval = getreg32(STM32_RCC_CR); + regval |= (STM32_BOARD_MSIRANGE | RCC_CR_MSION); /* Enable MSI and frequency */ + putreg32(regval, STM32_RCC_CR); /* Wait until the MSI is ready (or until a timeout elapsed) */ @@ -657,7 +657,7 @@ void stm32l5_stdclockconfig(void) { /* Check if the MSIRDY flag is the set in the CR */ - if ((getreg32(STM32L5_RCC_CR) & RCC_CR_MSIRDY) != 0) + if ((getreg32(STM32_RCC_CR) & RCC_CR_MSIRDY) != 0) { /* If so, then break-out with timeout > 0 */ @@ -665,12 +665,12 @@ void stm32l5_stdclockconfig(void) } } -#elif defined(STM32L5_BOARD_USEHSE) +#elif defined(STM32_BOARD_USEHSE) /* Enable External High-Speed Clock (HSE) */ - regval = getreg32(STM32L5_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_HSEON; /* Enable HSE */ - putreg32(regval, STM32L5_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Wait until the HSE is ready (or until a timeout elapsed) */ @@ -678,7 +678,7 @@ void stm32l5_stdclockconfig(void) { /* Check if the HSERDY flag is the set in the CR */ - if ((getreg32(STM32L5_RCC_CR) & RCC_CR_HSERDY) != 0) + if ((getreg32(STM32_RCC_CR) & RCC_CR_HSERDY) != 0) { /* If so, then break-out with timeout > 0 */ @@ -687,7 +687,7 @@ void stm32l5_stdclockconfig(void) } #else -# error stm32l5_stdclockconfig(), must have one of STM32L5_BOARD_USEHSI, STM32L5_BOARD_USEMSI, STM32L5_BOARD_USEHSE defined +# error stm32_stdclockconfig(), must have one of STM32_BOARD_USEHSI, STM32_BOARD_USEMSI, STM32_BOARD_USEHSE defined #endif @@ -704,18 +704,18 @@ void stm32l5_stdclockconfig(void) /* Ensure Power control is enabled before modifying it. */ - stm32l5_pwr_enableclk(true); + stm32_pwr_enableclk(true); /* Select correct main regulator range */ - regval = getreg32(STM32L5_PWR_CR1); + regval = getreg32(STM32_PWR_CR1); regval &= ~PWR_CR1_VOS_MASK; - if (STM32L5_SYSCLK_FREQUENCY > 80000000) + if (STM32_SYSCLK_FREQUENCY > 80000000) { regval |= PWR_CR1_VOS_RANGE0; } - else if (STM32L5_SYSCLK_FREQUENCY > 26000000) + else if (STM32_SYSCLK_FREQUENCY > 26000000) { regval |= PWR_CR1_VOS_RANGE1; } @@ -724,157 +724,157 @@ void stm32l5_stdclockconfig(void) regval |= PWR_CR1_VOS_RANGE0; } - putreg32(regval, STM32L5_PWR_CR1); + putreg32(regval, STM32_PWR_CR1); /* Wait for voltage regulator to stabilize */ - while (getreg32(STM32L5_PWR_SR2) & PWR_SR2_VOSF) + while (getreg32(STM32_PWR_SR2) & PWR_SR2_VOSF) { } /* Set the HCLK source/divider */ - regval = getreg32(STM32L5_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_HPRE_MASK; - regval |= STM32L5_RCC_CFGR_HPRE; - putreg32(regval, STM32L5_RCC_CFGR); + regval |= STM32_RCC_CFGR_HPRE; + putreg32(regval, STM32_RCC_CFGR); /* Set the PCLK2 divider */ - regval = getreg32(STM32L5_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_PPRE2_MASK; - regval |= STM32L5_RCC_CFGR_PPRE2; - putreg32(regval, STM32L5_RCC_CFGR); + regval |= STM32_RCC_CFGR_PPRE2; + putreg32(regval, STM32_RCC_CFGR); /* Set the PCLK1 divider */ - regval = getreg32(STM32L5_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_PPRE1_MASK; - regval |= STM32L5_RCC_CFGR_PPRE1; - putreg32(regval, STM32L5_RCC_CFGR); + regval |= STM32_RCC_CFGR_PPRE1; + putreg32(regval, STM32_RCC_CFGR); -#ifdef CONFIG_STM32L5_RTC_HSECLOCK +#ifdef CONFIG_STM32_RTC_HSECLOCK /* Set the RTC clock divisor */ - regval = getreg32(STM32L5_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_RTCPRE_MASK; regval |= RCC_CFGR_RTCPRE(HSE_DIVISOR); - putreg32(regval, STM32L5_RCC_CFGR); + putreg32(regval, STM32_RCC_CFGR); #endif /* Set the PLL source and main divider */ - regval = getreg32(STM32L5_RCC_PLLCFG); + regval = getreg32(STM32_RCC_PLLCFG); /* Configure Main PLL */ /* Set the PLL dividers and multipliers to configure the main PLL */ - regval = (STM32L5_PLLCFG_PLLM | STM32L5_PLLCFG_PLLN | - STM32L5_PLLCFG_PLLP | STM32L5_PLLCFG_PLLQ | - STM32L5_PLLCFG_PLLR); + regval = (STM32_PLLCFG_PLLM | STM32_PLLCFG_PLLN | + STM32_PLLCFG_PLLP | STM32_PLLCFG_PLLQ | + STM32_PLLCFG_PLLR); -#ifdef STM32L5_PLLCFG_PLLP_ENABLED +#ifdef STM32_PLLCFG_PLLP_ENABLED regval |= RCC_PLLCFG_PLLPEN; #endif -#ifdef STM32L5_PLLCFG_PLLQ_ENABLED +#ifdef STM32_PLLCFG_PLLQ_ENABLED regval |= RCC_PLLCFG_PLLQEN; #endif -#ifdef STM32L5_PLLCFG_PLLR_ENABLED +#ifdef STM32_PLLCFG_PLLR_ENABLED regval |= RCC_PLLCFG_PLLREN; #endif /* XXX The choice of clock source to PLL (all three) is independent - * of the sys clock source choice, review the STM32L5_BOARD_USEHSI + * of the sys clock source choice, review the STM32_BOARD_USEHSI * name; probably split it into two, one for PLL source and one * for sys clock source. */ -#ifdef STM32L5_BOARD_USEHSI +#ifdef STM32_BOARD_USEHSI regval |= RCC_PLLCFG_PLLSRC_HSI16; -#elif defined(STM32L5_BOARD_USEMSI) +#elif defined(STM32_BOARD_USEMSI) regval |= RCC_PLLCFG_PLLSRC_MSI; -#else /* if STM32L5_BOARD_USEHSE */ +#else /* if STM32_BOARD_USEHSE */ regval |= RCC_PLLCFG_PLLSRC_HSE; #endif - putreg32(regval, STM32L5_RCC_PLLCFG); + putreg32(regval, STM32_RCC_PLLCFG); /* Enable the main PLL */ - regval = getreg32(STM32L5_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_PLLON; - putreg32(regval, STM32L5_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Wait until the PLL is ready */ - while ((getreg32(STM32L5_RCC_CR) & RCC_CR_PLLRDY) == 0) + while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLRDY) == 0) { } -#ifdef CONFIG_STM32L5_SAI1PLL +#ifdef CONFIG_STM32_SAI1PLL /* Configure SAI1 PLL */ - regval = getreg32(STM32L5_RCC_PLLSAI1CFG); + regval = getreg32(STM32_RCC_PLLSAI1CFG); /* Set the PLL dividers and multipliers to configure the SAI1 PLL */ - regval = (STM32L5_PLLSAI1CFG_PLLN | STM32L5_PLLSAI1CFG_PLLP - | STM32L5_PLLSAI1CFG_PLLQ | STM32L5_PLLSAI1CFG_PLLR); + regval = (STM32_PLLSAI1CFG_PLLN | STM32_PLLSAI1CFG_PLLP + | STM32_PLLSAI1CFG_PLLQ | STM32_PLLSAI1CFG_PLLR); -#ifdef STM32L5_PLLSAI1CFG_PLLP_ENABLED +#ifdef STM32_PLLSAI1CFG_PLLP_ENABLED regval |= RCC_PLLSAI1CFG_PLLPEN; #endif -#ifdef STM32L5_PLLSAI1CFG_PLLQ_ENABLED +#ifdef STM32_PLLSAI1CFG_PLLQ_ENABLED regval |= RCC_PLLSAI1CFG_PLLQEN; #endif -#ifdef STM32L5_PLLSAI1CFG_PLLR_ENABLED +#ifdef STM32_PLLSAI1CFG_PLLR_ENABLED regval |= RCC_PLLSAI1CFG_PLLREN; #endif - putreg32(regval, STM32L5_RCC_PLLSAI1CFG); + putreg32(regval, STM32_RCC_PLLSAI1CFG); /* Enable the SAI1 PLL */ - regval = getreg32(STM32L5_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_PLLSAI1ON; - putreg32(regval, STM32L5_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Wait until the PLL is ready */ - while ((getreg32(STM32L5_RCC_CR) & RCC_CR_PLLSAI1RDY) == 0) + while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLSAI1RDY) == 0) { } #endif -#ifdef CONFIG_STM32L5_SAI2PLL +#ifdef CONFIG_STM32_SAI2PLL /* Configure SAI2 PLL */ - regval = getreg32(STM32L5_RCC_PLLSAI2CFG); + regval = getreg32(STM32_RCC_PLLSAI2CFG); /* Set the PLL dividers and multipliers to configure the SAI2 PLL */ - regval = (STM32L5_PLLSAI2CFG_PLLN | STM32L5_PLLSAI2CFG_PLLP | - STM32L5_PLLSAI2CFG_PLLR); + regval = (STM32_PLLSAI2CFG_PLLN | STM32_PLLSAI2CFG_PLLP | + STM32_PLLSAI2CFG_PLLR); -#ifdef STM32L5_PLLSAI2CFG_PLLP_ENABLED +#ifdef STM32_PLLSAI2CFG_PLLP_ENABLED regval |= RCC_PLLSAI2CFG_PLLPEN; #endif -#ifdef STM32L5_PLLSAI2CFG_PLLR_ENABLED +#ifdef STM32_PLLSAI2CFG_PLLR_ENABLED regval |= RCC_PLLSAI2CFG_PLLREN; #endif - putreg32(regval, STM32L5_RCC_PLLSAI2CFG); + putreg32(regval, STM32_RCC_PLLSAI2CFG); /* Enable the SAI2 PLL */ - regval = getreg32(STM32L5_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_PLLSAI2ON; - putreg32(regval, STM32L5_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Wait until the PLL is ready */ - while ((getreg32(STM32L5_RCC_CR) & RCC_CR_PLLSAI2RDY) == 0) + while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLSAI2RDY) == 0) { } #endif @@ -882,29 +882,29 @@ void stm32l5_stdclockconfig(void) /* Enable FLASH 5 wait states */ regval = FLASH_ACR_LATENCY_5; - putreg32(regval, STM32L5_FLASH_ACR); + putreg32(regval, STM32_FLASH_ACR); /* Select the main PLL as system clock source */ - regval = getreg32(STM32L5_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_SW_MASK; regval |= RCC_CFGR_SW_PLL; - putreg32(regval, STM32L5_RCC_CFGR); + putreg32(regval, STM32_RCC_CFGR); /* Wait until the PLL source is used as the system clock source */ - while ((getreg32(STM32L5_RCC_CFGR) & RCC_CFGR_SWS_MASK) != + while ((getreg32(STM32_RCC_CFGR) & RCC_CFGR_SWS_MASK) != RCC_CFGR_SWS_PLL) { } -#if defined(CONFIG_STM32L5_IWDG) || defined(CONFIG_STM32L5_RTC_LSICLOCK) +#if defined(CONFIG_STM32_IWDG) || defined(CONFIG_STM32_RTC_LSICLOCK) /* Low speed internal clock source LSI */ - stm32l5_rcc_enablelsi(); + stm32_rcc_enablelsi(); #endif -#if defined(STM32L5_USE_LSE) +#if defined(STM32_USE_LSE) /* Low speed external clock source LSE * * TODO: There is another case where the LSE needs to @@ -916,7 +916,7 @@ void stm32l5_stdclockconfig(void) * to alter the LSE parameters. */ - stm32l5_pwr_enableclk(true); + stm32_pwr_enableclk(true); /* XXX other LSE settings must be made before turning on the oscillator * and we need to ensure it is first off before doing so. @@ -927,16 +927,16 @@ void stm32l5_stdclockconfig(void) * this for automatically trimming MSI, etc. */ - stm32l5_rcc_enablelse(); + stm32_rcc_enablelse(); -# if defined(STM32L5_BOARD_USEMSI) +# if defined(STM32_BOARD_USEMSI) /* Now that LSE is up, auto trim the MSI */ - regval = getreg32(STM32L5_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_MSIPLLEN; - putreg32(regval, STM32L5_RCC_CR); + putreg32(regval, STM32_RCC_CR); # endif -#endif /* STM32L5_USE_LSE */ +#endif /* STM32_USE_LSE */ } } #endif diff --git a/arch/arm/src/stm32l5/stm32l5_allocateheap.c b/arch/arm/src/stm32l5/stm32l5_allocateheap.c index 8809fc4a2004f..2be31186e6c77 100644 --- a/arch/arm/src/stm32l5/stm32l5_allocateheap.c +++ b/arch/arm/src/stm32l5/stm32l5_allocateheap.c @@ -60,8 +60,8 @@ * FSMC. In order to use FSMC SRAM, the following additional things need to * be present in the NuttX configuration file: * - * CONFIG_STM32L5_FSMC=y : Enables the FSMC - * CONFIG_STM32L5_FSMC_SRAM=y : Indicates that SRAM is available via the + * CONFIG_STM32_FSMC=y : Enables the FSMC + * CONFIG_STM32_FSMC_SRAM=y : Indicates that SRAM is available via the * FSMC (as opposed to an LCD or FLASH). * CONFIG_HEAP2_BASE : The base address of the SRAM in the FSMC * address space @@ -71,8 +71,8 @@ * include the additional regions. */ -#ifndef CONFIG_STM32L5_FSMC -# undef CONFIG_STM32L5_FSMC_SRAM +#ifndef CONFIG_STM32_FSMC +# undef CONFIG_STM32_FSMC_SRAM #endif /* STM32L5[7,8]6xx have 128 Kib in two banks, both accessible to DMA: @@ -96,19 +96,19 @@ /* Set the range of system SRAM */ -#define SRAM1_START STM32L5_SRAM_BASE -#define SRAM1_END (SRAM1_START + STM32L5_SRAM1_SIZE) +#define SRAM1_START STM32_SRAM_BASE +#define SRAM1_END (SRAM1_START + STM32_SRAM1_SIZE) /* Set the range of SRAM2 as well, requires a second memory region */ -#define SRAM2_START STM32L5_SRAM2_BASE -#define SRAM2_END (SRAM2_START + STM32L5_SRAM2_SIZE) +#define SRAM2_START STM32_SRAM2_BASE +#define SRAM2_END (SRAM2_START + STM32_SRAM2_SIZE) /* Set the range of SRAM3, requiring a third memory region */ -#ifdef STM32L5_SRAM3_SIZE -# define SRAM3_START STM32L5_SRAM3_BASE -# define SRAM3_END (SRAM3_START + STM32L5_SRAM3_SIZE) +#ifdef STM32_SRAM3_SIZE +# define SRAM3_START STM32_SRAM3_BASE +# define SRAM3_END (SRAM3_START + STM32_SRAM3_SIZE) #endif /* Some sanity checking. If multiple memory regions are defined, verify @@ -116,15 +116,15 @@ * that we have been asked to add to the heap. */ -#if CONFIG_MM_REGIONS < defined(CONFIG_STM32L5_SRAM2_HEAP) + \ - defined(CONFIG_STM32L5_SRAM3_HEAP) + \ - defined(CONFIG_STM32L5_FSMC_SRAM_HEAP) + 1 +#if CONFIG_MM_REGIONS < defined(CONFIG_STM32_SRAM2_HEAP) + \ + defined(CONFIG_STM32_SRAM3_HEAP) + \ + defined(CONFIG_STM32_FSMC_SRAM_HEAP) + 1 # error "You need more memory manager regions to support selected heap components" #endif -#if CONFIG_MM_REGIONS > defined(CONFIG_STM32L5_SRAM2_HEAP) + \ - defined(CONFIG_STM32L5_SRAM3_HEAP) + \ - defined(CONFIG_STM32L5_FSMC_SRAM_HEAP) + 1 +#if CONFIG_MM_REGIONS > defined(CONFIG_STM32_SRAM2_HEAP) + \ + defined(CONFIG_STM32_SRAM3_HEAP) + \ + defined(CONFIG_STM32_FSMC_SRAM_HEAP) + 1 # warning "CONFIG_MM_REGIONS large enough but I do not know what some of the region(s) are" #endif @@ -133,10 +133,10 @@ * configuration (as CONFIG_HEAP2_BASE and CONFIG_HEAP2_SIZE). */ -#ifdef CONFIG_STM32L5_FSMC_SRAM +#ifdef CONFIG_STM32_FSMC_SRAM # if !defined(CONFIG_HEAP2_BASE) || !defined(CONFIG_HEAP2_SIZE) # error "CONFIG_HEAP2_BASE and CONFIG_HEAP2_SIZE must be provided" -# undef CONFIG_STM32L5_FSMC_SRAM +# undef CONFIG_STM32_FSMC_SRAM # endif #endif @@ -240,7 +240,7 @@ void up_allocate_heap(void **heap_start, size_t *heap_size) /* Allow user-mode access to the user heap memory */ - stm32l5_mpu_uheap((uintptr_t)ubase, usize); + stm32_mpu_uheap((uintptr_t)ubase, usize); #else /* Return the heap settings */ @@ -312,13 +312,13 @@ void up_allocate_kheap(void **heap_start, size_t *heap_size) #if CONFIG_MM_REGIONS > 1 void arm_addregion(void) { -#ifdef CONFIG_STM32L5_SRAM2_HEAP +#ifdef CONFIG_STM32_SRAM2_HEAP #if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP) /* Allow user-mode access to the SRAM2 heap */ - stm32l5_mpu_uheap((uintptr_t)SRAM2_START, SRAM2_END - SRAM2_START); + stm32_mpu_uheap((uintptr_t)SRAM2_START, SRAM2_END - SRAM2_START); #endif @@ -332,13 +332,13 @@ void arm_addregion(void) #endif /* SRAM2 */ -#ifdef CONFIG_STM32L5_SRAM3_HEAP +#ifdef CONFIG_STM32_SRAM3_HEAP #if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP) /* Allow user-mode access to the SRAM3 heap */ - stm32l5_mpu_uheap((uintptr_t)SRAM3_START, SRAM3_END - SRAM3_START); + stm32_mpu_uheap((uintptr_t)SRAM3_START, SRAM3_END - SRAM3_START); #endif @@ -352,12 +352,12 @@ void arm_addregion(void) #endif /* SRAM3 */ -#ifdef CONFIG_STM32L5_FSMC_SRAM_HEAP +#ifdef CONFIG_STM32_FSMC_SRAM_HEAP #if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP) /* Allow user-mode access to the FSMC SRAM user heap memory */ - stm32l5_mpu_uheap((uintptr_t)CONFIG_HEAP2_BASE, CONFIG_HEAP2_SIZE); + stm32_mpu_uheap((uintptr_t)CONFIG_HEAP2_BASE, CONFIG_HEAP2_SIZE); #endif diff --git a/arch/arm/src/stm32l5/stm32l5_dbgmcu.h b/arch/arm/src/stm32l5/stm32l5_dbgmcu.h index a6b73b00ad561..ef826e158781e 100644 --- a/arch/arm/src/stm32l5/stm32l5_dbgmcu.h +++ b/arch/arm/src/stm32l5/stm32l5_dbgmcu.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32L5_STM32L5_DBGMCU_H -#define __ARCH_ARM_SRC_STM32L5_STM32L5_DBGMCU_H +#ifndef __ARCH_ARM_SRC_STM32L5_STM32_DBGMCU_H +#define __ARCH_ARM_SRC_STM32L5_STM32_DBGMCU_H /**************************************************************************** * Included Files @@ -31,10 +31,10 @@ #include "chip.h" -#if defined(CONFIG_STM32L5_STM32L562XX) +#if defined(CONFIG_STM32_STM32L562XX) # include "hardware/stm32l562xx_dbgmcu.h" #else # error "Unsupported STM32L5 chip" #endif -#endif /* __ARCH_ARM_SRC_STM32L5_STM32L5_DBGMCU_H */ +#endif /* __ARCH_ARM_SRC_STM32L5_STM32_DBGMCU_H */ diff --git a/arch/arm/src/stm32l5/stm32l5_dumpgpio.c b/arch/arm/src/stm32l5/stm32l5_dumpgpio.c index 0c79a6cc60d49..cf5760c43f65a 100644 --- a/arch/arm/src/stm32l5/stm32l5_dumpgpio.c +++ b/arch/arm/src/stm32l5/stm32l5_dumpgpio.c @@ -50,31 +50,31 @@ /* Port letters for prettier debug output */ -static const char g_portchar[STM32L5_NPORTS] = +static const char g_portchar[STM32_NPORTS] = { -#if STM32L5_NPORTS > 11 +#if STM32_NPORTS > 11 # error "Additional support required for this number of GPIOs" -#elif STM32L5_NPORTS > 10 +#elif STM32_NPORTS > 10 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 'I', 'J', 'K' -#elif STM32L5_NPORTS > 9 +#elif STM32_NPORTS > 9 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 'I', 'J' -#elif STM32L5_NPORTS > 8 +#elif STM32_NPORTS > 8 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 'I' -#elif STM32L5_NPORTS > 7 +#elif STM32_NPORTS > 7 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H' -#elif STM32L5_NPORTS > 6 +#elif STM32_NPORTS > 6 'A', 'B', 'C', 'D', 'E', 'F', 'G' -#elif STM32L5_NPORTS > 5 +#elif STM32_NPORTS > 5 'A', 'B', 'C', 'D', 'E', 'F' -#elif STM32L5_NPORTS > 4 +#elif STM32_NPORTS > 4 'A', 'B', 'C', 'D', 'E' -#elif STM32L5_NPORTS > 3 +#elif STM32_NPORTS > 3 'A', 'B', 'C', 'D' -#elif STM32L5_NPORTS > 2 +#elif STM32_NPORTS > 2 'A', 'B', 'C' -#elif STM32L5_NPORTS > 1 +#elif STM32_NPORTS > 1 'A', 'B' -#elif STM32L5_NPORTS > 0 +#elif STM32_NPORTS > 0 'A' #else # error "Bad number of GPIOs" @@ -86,14 +86,14 @@ static const char g_portchar[STM32L5_NPORTS] = ****************************************************************************/ /**************************************************************************** - * Function: stm32l5_dumpgpio + * Function: stm32_dumpgpio * * Description: * Dump all GPIO registers associated with the provided base address * ****************************************************************************/ -int stm32l5_dumpgpio(uint32_t pinset, const char *msg) +int stm32_dumpgpio(uint32_t pinset, const char *msg) { irqstate_t flags; uint32_t base; @@ -108,33 +108,33 @@ int stm32l5_dumpgpio(uint32_t pinset, const char *msg) flags = enter_critical_section(); - DEBUGASSERT(port < STM32L5_NPORTS); + DEBUGASSERT(port < STM32_NPORTS); _info("GPIO%c pinset: %08" PRIx32 " base: %08" PRIx32 " -- %s\n", g_portchar[port], pinset, base, msg); - if ((getreg32(STM32L5_RCC_AHB2ENR) & RCC_AHB2ENR_GPIOEN(port)) != 0) + if ((getreg32(STM32_RCC_AHB2ENR) & RCC_AHB2ENR_GPIOEN(port)) != 0) { _info(" MODE: %08" PRIx32 " OTYPE: %04" PRIx32 " OSPEED: %08" PRIx32 " PUPDR: %08" PRIx32 "\n", - getreg32(base + STM32L5_GPIO_MODER_OFFSET), - getreg32(base + STM32L5_GPIO_OTYPER_OFFSET), - getreg32(base + STM32L5_GPIO_OSPEED_OFFSET), - getreg32(base + STM32L5_GPIO_PUPDR_OFFSET)); + getreg32(base + STM32_GPIO_MODER_OFFSET), + getreg32(base + STM32_GPIO_OTYPER_OFFSET), + getreg32(base + STM32_GPIO_OSPEED_OFFSET), + getreg32(base + STM32_GPIO_PUPDR_OFFSET)); _info(" IDR: %04" PRIx32 " ODR: %04" PRIx32 " BSRR: %08" PRIx32 " LCKR: %04" PRIx32 "\n", - getreg32(base + STM32L5_GPIO_IDR_OFFSET), - getreg32(base + STM32L5_GPIO_ODR_OFFSET), - getreg32(base + STM32L5_GPIO_BSRR_OFFSET), - getreg32(base + STM32L5_GPIO_LCKR_OFFSET)); + getreg32(base + STM32_GPIO_IDR_OFFSET), + getreg32(base + STM32_GPIO_ODR_OFFSET), + getreg32(base + STM32_GPIO_BSRR_OFFSET), + getreg32(base + STM32_GPIO_LCKR_OFFSET)); _info(" AFRH: %08" PRIx32 " AFRL: %08" PRIx32 "\n", - getreg32(base + STM32L5_GPIO_AFRH_OFFSET), - getreg32(base + STM32L5_GPIO_AFRL_OFFSET)); + getreg32(base + STM32_GPIO_AFRH_OFFSET), + getreg32(base + STM32_GPIO_AFRL_OFFSET)); } else { _info(" GPIO%c not enabled: AHB2ENR: %08" PRIx32 "\n", - g_portchar[port], getreg32(STM32L5_RCC_AHB2ENR)); + g_portchar[port], getreg32(STM32_RCC_AHB2ENR)); } leave_critical_section(flags); diff --git a/arch/arm/src/stm32l5/stm32l5_exti.h b/arch/arm/src/stm32l5/stm32l5_exti.h index 7093f76a75edc..8d8eab5c8fc14 100644 --- a/arch/arm/src/stm32l5/stm32l5_exti.h +++ b/arch/arm/src/stm32l5/stm32l5_exti.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32L5_STM32L5_EXTI_H -#define __ARCH_ARM_SRC_STM32L5_STM32L5_EXTI_H +#ifndef __ARCH_ARM_SRC_STM32L5_STM32_EXTI_H +#define __ARCH_ARM_SRC_STM32L5_STM32_EXTI_H /**************************************************************************** * Included Files @@ -54,7 +54,7 @@ extern "C" ****************************************************************************/ /**************************************************************************** - * Name: stm32l5_gpiosetevent + * Name: stm32_gpiosetevent * * Description: * Sets/clears GPIO based event and interrupt triggers. @@ -73,11 +73,11 @@ extern "C" * ****************************************************************************/ -int stm32l5_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, +int stm32_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, bool event, xcpt_t func, void *arg); /**************************************************************************** - * Name: stm32l5_exti_alarm + * Name: stm32_exti_alarm * * Description: * Sets/clears EXTI alarm interrupt. @@ -95,12 +95,12 @@ int stm32l5_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, ****************************************************************************/ #ifdef CONFIG_RTC_ALARM -int stm32l5_exti_alarm(bool risingedge, bool fallingedge, bool event, +int stm32_exti_alarm(bool risingedge, bool fallingedge, bool event, xcpt_t func, void *arg); #endif /**************************************************************************** - * Name: stm32l5_exti_wakeup + * Name: stm32_exti_wakeup * * Description: * Sets/clears EXTI wakeup interrupt. @@ -118,12 +118,12 @@ int stm32l5_exti_alarm(bool risingedge, bool fallingedge, bool event, ****************************************************************************/ #ifdef CONFIG_RTC_PERIODIC -int stm32l5_exti_wakeup(bool risingedge, bool fallingedge, bool event, +int stm32_exti_wakeup(bool risingedge, bool fallingedge, bool event, xcpt_t func, void *arg); #endif /**************************************************************************** - * Name: stm32l5_exti_comp + * Name: stm32_exti_comp * * Description: * Sets/clears comparator based events and interrupt triggers. @@ -141,8 +141,8 @@ int stm32l5_exti_wakeup(bool risingedge, bool fallingedge, bool event, * ****************************************************************************/ -#ifdef CONFIG_STM32L5_COMP -int stm32l5_exti_comp(int cmp, bool risingedge, bool fallingedge, +#ifdef CONFIG_STM32_COMP +int stm32_exti_comp(int cmp, bool risingedge, bool fallingedge, bool event, xcpt_t func, void *arg); #endif @@ -152,4 +152,4 @@ int stm32l5_exti_comp(int cmp, bool risingedge, bool fallingedge, #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32L5_STM32L5_EXTI_H */ +#endif /* __ARCH_ARM_SRC_STM32L5_STM32_EXTI_H */ diff --git a/arch/arm/src/stm32l5/stm32l5_exti_gpio.c b/arch/arm/src/stm32l5/stm32l5_exti_gpio.c index cc632e2df5ad9..10e1099e0ec88 100644 --- a/arch/arm/src/stm32l5/stm32l5_exti_gpio.c +++ b/arch/arm/src/stm32l5/stm32l5_exti_gpio.c @@ -67,18 +67,18 @@ static struct gpio_callback_s g_gpio_handlers[16]; * Interrupt Service Routine - Dispatcher ****************************************************************************/ -static int stm32l5_exti0_15_isr(int irq, void *context, void *arg) +static int stm32_exti0_15_isr(int irq, void *context, void *arg) { int ret = OK; int exti; - exti = irq - STM32L5_IRQ_EXTI0; + exti = irq - STM32_IRQ_EXTI0; DEBUGASSERT((exti >= 0) && (exti <= 15)); /* Clear the pending interrupt for both rising and falling edges. */ - putreg32(0x0001 << exti, STM32L5_EXTI_RPR1); - putreg32(0x0001 << exti, STM32L5_EXTI_FPR1); + putreg32(0x0001 << exti, STM32_EXTI_RPR1); + putreg32(0x0001 << exti, STM32_EXTI_FPR1); /* And dispatch the interrupt to the handler */ @@ -98,7 +98,7 @@ static int stm32l5_exti0_15_isr(int irq, void *context, void *arg) ****************************************************************************/ /**************************************************************************** - * Name: stm32l5_gpiosetevent + * Name: stm32_gpiosetevent * * Description: * Sets/clears GPIO based event and interrupt triggers. @@ -120,12 +120,12 @@ static int stm32l5_exti0_15_isr(int irq, void *context, void *arg) * ****************************************************************************/ -int stm32l5_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, +int stm32_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, bool event, xcpt_t func, void *arg) { uint32_t pin = pinset & GPIO_PIN_MASK; uint32_t exti = 1 << pin; - int irq = STM32L5_IRQ_EXTI0 + pin; + int irq = STM32_IRQ_EXTI0 + pin; g_gpio_handlers[pin].callback = func; g_gpio_handlers[pin].arg = arg; @@ -134,7 +134,7 @@ int stm32l5_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, if (func) { - irq_attach(irq, stm32l5_exti0_15_isr, NULL); + irq_attach(irq, stm32_exti0_15_isr, NULL); up_enable_irq(irq); } else @@ -151,23 +151,23 @@ int stm32l5_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, pinset |= GPIO_EXTI; } - stm32l5_configgpio(pinset); + stm32_configgpio(pinset); /* Configure rising/falling edges */ - modifyreg32(STM32L5_EXTI_RTSR1, + modifyreg32(STM32_EXTI_RTSR1, risingedge ? 0 : exti, risingedge ? exti : 0); - modifyreg32(STM32L5_EXTI_FTSR1, + modifyreg32(STM32_EXTI_FTSR1, fallingedge ? 0 : exti, fallingedge ? exti : 0); /* Enable Events and Interrupts */ - modifyreg32(STM32L5_EXTI_EMR1, + modifyreg32(STM32_EXTI_EMR1, event ? 0 : exti, event ? exti : 0); - modifyreg32(STM32L5_EXTI_IMR1, + modifyreg32(STM32_EXTI_IMR1, func ? 0 : exti, func ? exti : 0); diff --git a/arch/arm/src/stm32l5/stm32l5_flash.c b/arch/arm/src/stm32l5/stm32l5_flash.c index 62f7f86370582..78d9e669f16fb 100644 --- a/arch/arm/src/stm32l5/stm32l5_flash.c +++ b/arch/arm/src/stm32l5/stm32l5_flash.c @@ -46,15 +46,15 @@ #include #include "stm32l5_rcc.h" -#include "stm32l5_waste.h" +#include "stm32_waste.h" #include "stm32l5_flash.h" #include "arm_internal.h" -#if !defined(CONFIG_STM32L5_STM32L562XX) +#if !defined(CONFIG_STM32_STM32L562XX) # error "Unrecognized STM32 chip" #endif -#if !defined(CONFIG_STM32L5_FLASH_OVERRIDE_DEFAULT) +#if !defined(CONFIG_STM32_FLASH_OVERRIDE_DEFAULT) # warning "Flash Configuration has been overridden - make sure it is correct" #endif @@ -69,7 +69,7 @@ #define OPTBYTES_KEY1 0x08192A3B #define OPTBYTES_KEY2 0x4C5D6E7F -#define FLASH_PAGE_SIZE STM32L5_FLASH_PAGESIZE +#define FLASH_PAGE_SIZE STM32_FLASH_PAGESIZE #define FLASH_PAGE_WORDS (FLASH_PAGE_SIZE / 4) #define FLASH_PAGE_MASK (FLASH_PAGE_SIZE - 1) #if FLASH_PAGE_SIZE == 2048 @@ -79,7 +79,7 @@ #elif FLASH_PAGE_SIZE == 8192 # define FLASH_PAGE_SHIFT (13) /* 2**13 = 8192B */ #else -# error Unsupported STM32L5_FLASH_PAGESIZE +# error Unsupported STM32_FLASH_PAGESIZE #endif #define FLASH_BYTE2PAGE(o) ((o) >> FLASH_PAGE_SHIFT) @@ -105,35 +105,35 @@ static uint32_t g_page_buffer[FLASH_PAGE_WORDS]; static void flash_unlock(void) { - while (getreg32(STM32L5_FLASH_NSSR) & FLASH_SR_BSY) + while (getreg32(STM32_FLASH_NSSR) & FLASH_SR_BSY) { - stm32l5_waste(); + stm32_waste(); } - if (getreg32(STM32L5_FLASH_NSCR) & FLASH_CR_LOCK) + if (getreg32(STM32_FLASH_NSCR) & FLASH_CR_LOCK) { /* Unlock sequence */ - putreg32(FLASH_KEY1, STM32L5_FLASH_NSKEYR); - putreg32(FLASH_KEY2, STM32L5_FLASH_NSKEYR); + putreg32(FLASH_KEY1, STM32_FLASH_NSKEYR); + putreg32(FLASH_KEY2, STM32_FLASH_NSKEYR); } } static void flash_lock(void) { - modifyreg32(STM32L5_FLASH_NSCR, 0, FLASH_CR_LOCK); + modifyreg32(STM32_FLASH_NSCR, 0, FLASH_CR_LOCK); } static void flash_optbytes_unlock(void) { flash_unlock(); - if (getreg32(STM32L5_FLASH_NSCR) & FLASH_CR_OPTLOCK) + if (getreg32(STM32_FLASH_NSCR) & FLASH_CR_OPTLOCK) { /* Unlock Option Bytes sequence */ - putreg32(OPTBYTES_KEY1, STM32L5_FLASH_OPTKEYR); - putreg32(OPTBYTES_KEY2, STM32L5_FLASH_OPTKEYR); + putreg32(OPTBYTES_KEY1, STM32_FLASH_OPTKEYR); + putreg32(OPTBYTES_KEY2, STM32_FLASH_OPTKEYR); } } @@ -150,30 +150,30 @@ static inline void flash_erase(size_t page) { finfo("erase page %u\n", page); - modifyreg32(STM32L5_FLASH_NSCR, 0, FLASH_CR_PAGE_ERASE); - modifyreg32(STM32L5_FLASH_NSCR, FLASH_CR_PNB_MASK, FLASH_CR_PNB(page)); - modifyreg32(STM32L5_FLASH_NSCR, 0, FLASH_CR_START); + modifyreg32(STM32_FLASH_NSCR, 0, FLASH_CR_PAGE_ERASE); + modifyreg32(STM32_FLASH_NSCR, FLASH_CR_PNB_MASK, FLASH_CR_PNB(page)); + modifyreg32(STM32_FLASH_NSCR, 0, FLASH_CR_START); - while (getreg32(STM32L5_FLASH_NSSR) & FLASH_SR_BSY) + while (getreg32(STM32_FLASH_NSSR) & FLASH_SR_BSY) { - stm32l5_waste(); + stm32_waste(); } - modifyreg32(STM32L5_FLASH_NSCR, FLASH_CR_PAGE_ERASE, 0); + modifyreg32(STM32_FLASH_NSCR, FLASH_CR_PAGE_ERASE, 0); } /**************************************************************************** * Public Functions ****************************************************************************/ -void stm32l5_flash_unlock(void) +void stm32_flash_unlock(void) { nxmutex_lock(&g_lock); flash_unlock(); nxmutex_unlock(&g_lock); } -void stm32l5_flash_lock(void) +void stm32_flash_lock(void) { nxmutex_lock(&g_lock); flash_lock(); @@ -181,7 +181,7 @@ void stm32l5_flash_lock(void) } /**************************************************************************** - * Name: stm32l5_flash_user_optbytes + * Name: stm32_flash_user_optbytes * * Description: * Modify the contents of the user option bytes (USR OPT) on the flash. @@ -197,7 +197,7 @@ void stm32l5_flash_lock(void) * ****************************************************************************/ -uint32_t stm32l5_flash_user_optbytes(uint32_t clrbits, uint32_t setbits) +uint32_t stm32_flash_user_optbytes(uint32_t clrbits, uint32_t setbits) { uint32_t regval; @@ -214,22 +214,22 @@ uint32_t stm32l5_flash_user_optbytes(uint32_t clrbits, uint32_t setbits) /* Modify Option Bytes in register. */ - regval = getreg32(STM32L5_FLASH_OPTR); + regval = getreg32(STM32_FLASH_OPTR); finfo("Flash option bytes before: 0x%x\n", (unsigned)regval); regval = (regval & ~clrbits) | setbits; - putreg32(regval, STM32L5_FLASH_OPTR); + putreg32(regval, STM32_FLASH_OPTR); finfo("Flash option bytes after: 0x%x\n", (unsigned)regval); /* Start Option Bytes programming and wait for completion. */ - modifyreg32(STM32L5_FLASH_NSCR, 0, FLASH_CR_OPTSTRT); + modifyreg32(STM32_FLASH_NSCR, 0, FLASH_CR_OPTSTRT); - while (getreg32(STM32L5_FLASH_NSSR) & FLASH_SR_BSY) + while (getreg32(STM32_FLASH_NSSR) & FLASH_SR_BSY) { - stm32l5_waste(); + stm32_waste(); } flash_optbytes_lock(); @@ -240,42 +240,42 @@ uint32_t stm32l5_flash_user_optbytes(uint32_t clrbits, uint32_t setbits) size_t up_progmem_pagesize(size_t page) { - return STM32L5_FLASH_PAGESIZE; + return STM32_FLASH_PAGESIZE; } size_t up_progmem_erasesize(size_t block) { - return STM32L5_FLASH_PAGESIZE; + return STM32_FLASH_PAGESIZE; } ssize_t up_progmem_getpage(size_t addr) { - if (addr >= STM32L5_FLASH_BASE) + if (addr >= STM32_FLASH_BASE) { - addr -= STM32L5_FLASH_BASE; + addr -= STM32_FLASH_BASE; } - if (addr >= STM32L5_FLASH_SIZE) + if (addr >= STM32_FLASH_SIZE) { return -EFAULT; } - return addr / STM32L5_FLASH_PAGESIZE; + return addr / STM32_FLASH_PAGESIZE; } size_t up_progmem_getaddress(size_t page) { - if (page >= STM32L5_FLASH_NPAGES) + if (page >= STM32_FLASH_NPAGES) { return SIZE_MAX; } - return page * STM32L5_FLASH_PAGESIZE + STM32L5_FLASH_BASE; + return page * STM32_FLASH_PAGESIZE + STM32_FLASH_BASE; } size_t up_progmem_neraseblocks(void) { - return STM32L5_FLASH_NPAGES; + return STM32_FLASH_NPAGES; } bool up_progmem_isuniform(void) @@ -285,7 +285,7 @@ bool up_progmem_isuniform(void) ssize_t up_progmem_eraseblock(size_t block) { - if (block >= STM32L5_FLASH_NPAGES) + if (block >= STM32_FLASH_NPAGES) { return -EFAULT; } @@ -318,7 +318,7 @@ ssize_t up_progmem_ispageerased(size_t page) size_t count; size_t bwritten = 0; - if (page >= STM32L5_FLASH_NPAGES) + if (page >= STM32_FLASH_NPAGES) { return -EFAULT; } @@ -351,12 +351,12 @@ ssize_t up_progmem_write(size_t addr, const void *buf, size_t buflen) /* Check for valid address range. */ offset = addr; - if (addr >= STM32L5_FLASH_BASE) + if (addr >= STM32_FLASH_BASE) { - offset -= STM32L5_FLASH_BASE; + offset -= STM32_FLASH_BASE; } - if (offset + buflen > STM32L5_FLASH_SIZE) + if (offset + buflen > STM32_FLASH_SIZE) { return -EFAULT; } @@ -422,23 +422,23 @@ ssize_t up_progmem_write(size_t addr, const void *buf, size_t buflen) /* Write the page. Must be with double-words. */ - modifyreg32(STM32L5_FLASH_NSCR, 0, FLASH_CR_PG); + modifyreg32(STM32_FLASH_NSCR, 0, FLASH_CR_PG); for (i = 0; i < FLASH_PAGE_WORDS; i += 2) { *dest++ = *src++; *dest++ = *src++; - while (getreg32(STM32L5_FLASH_NSSR) & FLASH_SR_BSY) + while (getreg32(STM32_FLASH_NSSR) & FLASH_SR_BSY) { - stm32l5_waste(); + stm32_waste(); } /* Verify */ - if (getreg32(STM32L5_FLASH_NSSR) & FLASH_SR_WRITE_PROTECTION_ERROR) + if (getreg32(STM32_FLASH_NSSR) & FLASH_SR_WRITE_PROTECTION_ERROR) { - modifyreg32(STM32L5_FLASH_NSCR, FLASH_CR_PG, 0); + modifyreg32(STM32_FLASH_NSCR, FLASH_CR_PG, 0); ret = -EROFS; goto out; } @@ -446,13 +446,13 @@ ssize_t up_progmem_write(size_t addr, const void *buf, size_t buflen) if (getreg32(dest - 1) != *(src - 1) || getreg32(dest - 2) != *(src - 2)) { - modifyreg32(STM32L5_FLASH_NSCR, FLASH_CR_PG, 0); + modifyreg32(STM32_FLASH_NSCR, FLASH_CR_PG, 0); ret = -EIO; goto out; } } - modifyreg32(STM32L5_FLASH_NSCR, FLASH_CR_PG, 0); + modifyreg32(STM32_FLASH_NSCR, FLASH_CR_PG, 0); /* Adjust pointers and counts for the next time through the loop */ @@ -473,8 +473,8 @@ ssize_t up_progmem_write(size_t addr, const void *buf, size_t buflen) if (ret != OK) { ferr("flash write error: %d, status: 0x%x\n", ret, - (unsigned)getreg32(STM32L5_FLASH_NSSR)); - modifyreg32(STM32L5_FLASH_NSSR, 0, FLASH_SR_ALLERRS); + (unsigned)getreg32(STM32_FLASH_NSSR)); + modifyreg32(STM32_FLASH_NSSR, 0, FLASH_SR_ALLERRS); } flash_lock(); diff --git a/arch/arm/src/stm32l5/stm32l5_flash.h b/arch/arm/src/stm32l5/stm32l5_flash.h index 0a3f7076c9044..4f0223c3ac853 100644 --- a/arch/arm/src/stm32l5/stm32l5_flash.h +++ b/arch/arm/src/stm32l5/stm32l5_flash.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32L5_STM32L5_FLASH_H -#define __ARCH_ARM_SRC_STM32L5_STM32L5_FLASH_H +#ifndef __ARCH_ARM_SRC_STM32L5_STM32_FLASH_H +#define __ARCH_ARM_SRC_STM32L5_STM32_FLASH_H /**************************************************************************** * Included Files @@ -34,11 +34,11 @@ * Public Function Prototypes ****************************************************************************/ -void stm32l5_flash_lock(void); -void stm32l5_flash_unlock(void); +void stm32_flash_lock(void); +void stm32_flash_unlock(void); /**************************************************************************** - * Name: stm32l5_flash_user_optbytes + * Name: stm32_flash_user_optbytes * * Description: * Modify the contents of the user option bytes (USR OPT) on the flash. @@ -54,6 +54,6 @@ void stm32l5_flash_unlock(void); * ****************************************************************************/ -uint32_t stm32l5_flash_user_optbytes(uint32_t clrbits, uint32_t setbits); +uint32_t stm32_flash_user_optbytes(uint32_t clrbits, uint32_t setbits); -#endif /* __ARCH_ARM_SRC_STM32L5_STM32L5_FLASH_H */ +#endif /* __ARCH_ARM_SRC_STM32L5_STM32_FLASH_H */ diff --git a/arch/arm/src/stm32l5/stm32l5_gpio.c b/arch/arm/src/stm32l5/stm32l5_gpio.c index 581a5b6bfc0fc..297a5deb18287 100644 --- a/arch/arm/src/stm32l5/stm32l5_gpio.c +++ b/arch/arm/src/stm32l5/stm32l5_gpio.c @@ -54,31 +54,31 @@ static spinlock_t g_configgpio_lock = SP_UNLOCKED; /* Base addresses for each GPIO block */ -const uint32_t g_gpiobase[STM32L5_NPORTS] = +const uint32_t g_gpiobase[STM32_NPORTS] = { -#if STM32L5_NPORTS > 0 - STM32L5_GPIOA_BASE, +#if STM32_NPORTS > 0 + STM32_GPIOA_BASE, #endif -#if STM32L5_NPORTS > 1 - STM32L5_GPIOB_BASE, +#if STM32_NPORTS > 1 + STM32_GPIOB_BASE, #endif -#if STM32L5_NPORTS > 2 - STM32L5_GPIOC_BASE, +#if STM32_NPORTS > 2 + STM32_GPIOC_BASE, #endif -#if STM32L5_NPORTS > 3 - STM32L5_GPIOD_BASE, +#if STM32_NPORTS > 3 + STM32_GPIOD_BASE, #endif -#if STM32L5_NPORTS > 4 - STM32L5_GPIOE_BASE, +#if STM32_NPORTS > 4 + STM32_GPIOE_BASE, #endif -#if STM32L5_NPORTS > 5 - STM32L5_GPIOF_BASE, +#if STM32_NPORTS > 5 + STM32_GPIOF_BASE, #endif -#if STM32L5_NPORTS > 6 - STM32L5_GPIOG_BASE, +#if STM32_NPORTS > 6 + STM32_GPIOG_BASE, #endif -#if STM32L5_NPORTS > 7 - STM32L5_GPIOH_BASE, +#if STM32_NPORTS > 7 + STM32_GPIOH_BASE, #endif }; @@ -91,13 +91,13 @@ const uint32_t g_gpiobase[STM32L5_NPORTS] = ****************************************************************************/ /**************************************************************************** - * Function: stm32l5_gpioinit + * Function: stm32_gpioinit * * Description: * Based on configuration within the .config file, it does: * - Remaps positions of alternative functions. * - * Typically called from stm32l5_start(). + * Typically called from stm32_start(). * * Assumptions: * This function is called early in the initialization sequence so that @@ -105,17 +105,17 @@ const uint32_t g_gpiobase[STM32L5_NPORTS] = * ****************************************************************************/ -void stm32l5_gpioinit(void) +void stm32_gpioinit(void) { } /**************************************************************************** - * Name: stm32l5_configgpio + * Name: stm32_configgpio * * Description: * Configure a GPIO pin based on bit-encoded description of the pin. * Once it is configured as Alternative (GPIO_ALT|GPIO_CNF_AFPP|...) - * function, it must be unconfigured with stm32l5_unconfiggpio() with + * function, it must be unconfigured with stm32_unconfiggpio() with * the same cfgset first before it can be set to non-alternative function. * * Returned Value: @@ -126,7 +126,7 @@ void stm32l5_gpioinit(void) * To-Do: Auto Power Enable ****************************************************************************/ -int stm32l5_configgpio(uint32_t cfgset) +int stm32_configgpio(uint32_t cfgset) { uintptr_t base; uint32_t regval; @@ -141,7 +141,7 @@ int stm32l5_configgpio(uint32_t cfgset) /* Verify that this hardware supports the select GPIO port */ port = (cfgset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; - if (port >= STM32L5_NPORTS) + if (port >= STM32_NPORTS) { return -EINVAL; } @@ -169,7 +169,7 @@ int stm32l5_configgpio(uint32_t cfgset) /* Set the initial output value */ - stm32l5_gpiowrite(cfgset, (cfgset & GPIO_OUTPUT_SET) != 0); + stm32_gpiowrite(cfgset, (cfgset & GPIO_OUTPUT_SET) != 0); pinmode = GPIO_MODER_OUTPUT; break; @@ -190,10 +190,10 @@ int stm32l5_configgpio(uint32_t cfgset) /* Now apply the configuration to the mode register */ - regval = getreg32(base + STM32L5_GPIO_MODER_OFFSET); + regval = getreg32(base + STM32_GPIO_MODER_OFFSET); regval &= ~GPIO_MODER_MASK(pin); regval |= ((uint32_t)pinmode << GPIO_MODER_SHIFT(pin)); - putreg32(regval, base + STM32L5_GPIO_MODER_OFFSET); + putreg32(regval, base + STM32_GPIO_MODER_OFFSET); /* Set up the pull-up/pull-down configuration (all but analog pins) */ @@ -216,10 +216,10 @@ int stm32l5_configgpio(uint32_t cfgset) } } - regval = getreg32(base + STM32L5_GPIO_PUPDR_OFFSET); + regval = getreg32(base + STM32_GPIO_PUPDR_OFFSET); regval &= ~GPIO_PUPDR_MASK(pin); regval |= (setting << GPIO_PUPDR_SHIFT(pin)); - putreg32(regval, base + STM32L5_GPIO_PUPDR_OFFSET); + putreg32(regval, base + STM32_GPIO_PUPDR_OFFSET); /* Set the alternate function (Only alternate function pins) */ @@ -234,12 +234,12 @@ int stm32l5_configgpio(uint32_t cfgset) if (pin < 8) { - regoffset = STM32L5_GPIO_AFRL_OFFSET; + regoffset = STM32_GPIO_AFRL_OFFSET; pos = pin; } else { - regoffset = STM32L5_GPIO_AFRH_OFFSET; + regoffset = STM32_GPIO_AFRH_OFFSET; pos = pin - 8; } @@ -277,14 +277,14 @@ int stm32l5_configgpio(uint32_t cfgset) setting = 0; } - regval = getreg32(base + STM32L5_GPIO_OSPEED_OFFSET); + regval = getreg32(base + STM32_GPIO_OSPEED_OFFSET); regval &= ~GPIO_OSPEED_MASK(pin); regval |= (setting << GPIO_OSPEED_SHIFT(pin)); - putreg32(regval, base + STM32L5_GPIO_OSPEED_OFFSET); + putreg32(regval, base + STM32_GPIO_OSPEED_OFFSET); /* Set push-pull/open-drain (Only outputs and alternate function pins) */ - regval = getreg32(base + STM32L5_GPIO_OTYPER_OFFSET); + regval = getreg32(base + STM32_GPIO_OTYPER_OFFSET); setting = GPIO_OTYPER_OD(pin); if ((pinmode == GPIO_MODER_OUTPUT || pinmode == GPIO_MODER_ALT) && @@ -297,14 +297,14 @@ int stm32l5_configgpio(uint32_t cfgset) regval &= ~setting; } - putreg32(regval, base + STM32L5_GPIO_OTYPER_OFFSET); + putreg32(regval, base + STM32_GPIO_OTYPER_OFFSET); spin_unlock_irqrestore(&g_configgpio_lock, flags); return OK; } /**************************************************************************** - * Name: stm32l5_unconfiggpio + * Name: stm32_unconfiggpio * * Description: * Unconfigure a GPIO pin based on bit-encoded description of the pin, set @@ -324,7 +324,7 @@ int stm32l5_configgpio(uint32_t cfgset) * To-Do: Auto Power Disable ****************************************************************************/ -int stm32l5_unconfiggpio(uint32_t cfgset) +int stm32_unconfiggpio(uint32_t cfgset) { /* Reuse port and pin number and set it to default HiZ INPUT */ @@ -333,18 +333,18 @@ int stm32l5_unconfiggpio(uint32_t cfgset) /* To-Do: Mark its unuse for automatic power saving options */ - return stm32l5_configgpio(cfgset); + return stm32_configgpio(cfgset); } /**************************************************************************** - * Name: stm32l5_gpiowrite + * Name: stm32_gpiowrite * * Description: * Write one or zero to the selected GPIO pin * ****************************************************************************/ -void stm32l5_gpiowrite(uint32_t pinset, bool value) +void stm32_gpiowrite(uint32_t pinset, bool value) { uint32_t base; uint32_t bit; @@ -352,7 +352,7 @@ void stm32l5_gpiowrite(uint32_t pinset, bool value) unsigned int pin; port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; - if (port < STM32L5_NPORTS) + if (port < STM32_NPORTS) { /* Get the port base address */ @@ -373,26 +373,26 @@ void stm32l5_gpiowrite(uint32_t pinset, bool value) bit = GPIO_BSRR_RESET(pin); } - putreg32(bit, base + STM32L5_GPIO_BSRR_OFFSET); + putreg32(bit, base + STM32_GPIO_BSRR_OFFSET); } } /**************************************************************************** - * Name: stm32l5_gpioread + * Name: stm32_gpioread * * Description: * Read one or zero from the selected GPIO pin * ****************************************************************************/ -bool stm32l5_gpioread(uint32_t pinset) +bool stm32_gpioread(uint32_t pinset) { uint32_t base; unsigned int port; unsigned int pin; port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; - if (port < STM32L5_NPORTS) + if (port < STM32_NPORTS) { /* Get the port base address */ @@ -401,7 +401,7 @@ bool stm32l5_gpioread(uint32_t pinset) /* Get the pin number and return the input state of that pin */ pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT; - return ((getreg32(base + STM32L5_GPIO_IDR_OFFSET) & (1 << pin)) != 0); + return ((getreg32(base + STM32_GPIO_IDR_OFFSET) & (1 << pin)) != 0); } return 0; diff --git a/arch/arm/src/stm32l5/stm32l5_gpio.h b/arch/arm/src/stm32l5/stm32l5_gpio.h index e14436202a596..05eb5396392c8 100644 --- a/arch/arm/src/stm32l5/stm32l5_gpio.h +++ b/arch/arm/src/stm32l5/stm32l5_gpio.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32L5_STM32L5_GPIO_H -#define __ARCH_ARM_SRC_STM32L5_STM32L5_GPIO_H +#ifndef __ARCH_ARM_SRC_STM32L5_STM32_GPIO_H +#define __ARCH_ARM_SRC_STM32L5_STM32_GPIO_H /**************************************************************************** * Included Files @@ -39,7 +39,7 @@ #include "chip.h" -#if defined(CONFIG_STM32L5_STM32L562XX) +#if defined(CONFIG_STM32_STM32L562XX) # include "hardware/stm32l5_gpio.h" #else # error "Unsupported STM32L5 chip" @@ -49,7 +49,7 @@ * Pre-Processor Declarations ****************************************************************************/ -/* Bit-encoded input to stm32l5_configgpio() */ +/* Bit-encoded input to stm32_configgpio() */ /* Each port bit of the general-purpose I/O (GPIO) ports can be individually * configured by software in several modes: @@ -241,19 +241,19 @@ extern "C" /* Base addresses for each GPIO block */ -EXTERN const uint32_t g_gpiobase[STM32L5_NPORTS]; +EXTERN const uint32_t g_gpiobase[STM32_NPORTS]; /**************************************************************************** * Public Function Prototypes ****************************************************************************/ /**************************************************************************** - * Name: stm32l5_configgpio + * Name: stm32_configgpio * * Description: * Configure a GPIO pin based on bit-encoded description of the pin. * Once it is configured as Alternative (GPIO_ALT|GPIO_CNF_AFPP|...) - * function, it must be unconfigured with stm32l5_unconfiggpio() with + * function, it must be unconfigured with stm32_unconfiggpio() with * the same cfgset first before it can be set to non-alternative function. * * Returned Value: @@ -262,10 +262,10 @@ EXTERN const uint32_t g_gpiobase[STM32L5_NPORTS]; * ****************************************************************************/ -int stm32l5_configgpio(uint32_t cfgset); +int stm32_configgpio(uint32_t cfgset); /**************************************************************************** - * Name: stm32l5_unconfiggpio + * Name: stm32_unconfiggpio * * Description: * Unconfigure a GPIO pin based on bit-encoded description of the pin, set @@ -284,30 +284,30 @@ int stm32l5_configgpio(uint32_t cfgset); * ****************************************************************************/ -int stm32l5_unconfiggpio(uint32_t cfgset); +int stm32_unconfiggpio(uint32_t cfgset); /**************************************************************************** - * Name: stm32l5_gpiowrite + * Name: stm32_gpiowrite * * Description: * Write one or zero to the selected GPIO pin * ****************************************************************************/ -void stm32l5_gpiowrite(uint32_t pinset, bool value); +void stm32_gpiowrite(uint32_t pinset, bool value); /**************************************************************************** - * Name: stm32l5_gpioread + * Name: stm32_gpioread * * Description: * Read one or zero from the selected GPIO pin * ****************************************************************************/ -bool stm32l5_gpioread(uint32_t pinset); +bool stm32_gpioread(uint32_t pinset); /**************************************************************************** - * Name: stm32l5_gpiosetevent + * Name: stm32_gpiosetevent * * Description: * Sets/clears GPIO based event and interrupt triggers. @@ -326,11 +326,11 @@ bool stm32l5_gpioread(uint32_t pinset); * ****************************************************************************/ -int stm32l5_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, +int stm32_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, bool event, xcpt_t func, void *arg); /**************************************************************************** - * Function: stm32l5_dumpgpio + * Function: stm32_dumpgpio * * Description: * Dump all GPIO registers associated with the provided base address @@ -338,23 +338,23 @@ int stm32l5_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, ****************************************************************************/ #ifdef CONFIG_DEBUG_FEATURES -int stm32l5_dumpgpio(uint32_t pinset, const char *msg); +int stm32_dumpgpio(uint32_t pinset, const char *msg); #else -# define stm32l5_dumpgpio(p,m) +# define stm32_dumpgpio(p,m) #endif /**************************************************************************** - * Function: stm32l5_gpioinit + * Function: stm32_gpioinit * * Description: * Based on configuration within the .config file, it does: * - Remaps positions of alternative functions. * - * Typically called from stm32l5_start(). + * Typically called from stm32_start(). * ****************************************************************************/ -void stm32l5_gpioinit(void); +void stm32_gpioinit(void); #undef EXTERN #if defined(__cplusplus) @@ -362,4 +362,4 @@ void stm32l5_gpioinit(void); #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32L5_STM32L5_GPIO_H */ +#endif /* __ARCH_ARM_SRC_STM32L5_STM32_GPIO_H */ diff --git a/arch/arm/src/stm32l5/stm32l5_idle.c b/arch/arm/src/stm32l5/stm32l5_idle.c index 99d9448c1a0cf..2c259c32df53a 100644 --- a/arch/arm/src/stm32l5/stm32l5_idle.c +++ b/arch/arm/src/stm32l5/stm32l5_idle.c @@ -92,7 +92,7 @@ void up_idle(void) /* Sleep until an interrupt occurs to save power. */ -#if !(defined(CONFIG_DEBUG_SYMBOLS) && defined(CONFIG_STM32L5_DISABLE_IDLE_SLEEP_DURING_DEBUG)) +#if !(defined(CONFIG_DEBUG_SYMBOLS) && defined(CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG)) BEGIN_IDLE(); asm("WFI"); END_IDLE(); diff --git a/arch/arm/src/stm32l5/stm32l5_irq.c b/arch/arm/src/stm32l5/stm32l5_irq.c index 757b7315fff41..46195910a0c5f 100644 --- a/arch/arm/src/stm32l5/stm32l5_irq.c +++ b/arch/arm/src/stm32l5/stm32l5_irq.c @@ -38,7 +38,7 @@ #include "nvic.h" #include "ram_vectors.h" #include "arm_internal.h" -#include "stm32l5.h" +#include "stm32.h" /**************************************************************************** * Pre-processor Definitions @@ -64,7 +64,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32l5_dumpnvic + * Name: stm32_dumpnvic * * Description: * Dump some interesting NVIC registers @@ -72,7 +72,7 @@ ****************************************************************************/ #if defined(CONFIG_DEBUG_IRQ_INFO) -static void stm32l5_dumpnvic(const char *msg, int irq) +static void stm32_dumpnvic(const char *msg, int irq) { irqstate_t flags; @@ -112,11 +112,11 @@ static void stm32l5_dumpnvic(const char *msg, int irq) leave_critical_section(flags); } #else -# define stm32l5_dumpnvic(msg, irq) +# define stm32_dumpnvic(msg, irq) #endif /**************************************************************************** - * Name: stm32l5_nmi, stm32l5_pendsv, stm32l5_pendsv, stm32l5_reserved + * Name: stm32_nmi, stm32_pendsv, stm32_pendsv, stm32_reserved * * Description: * Handlers for various exceptions. None are handled and all are fatal @@ -126,7 +126,7 @@ static void stm32l5_dumpnvic(const char *msg, int irq) ****************************************************************************/ #ifdef CONFIG_DEBUG_FEATURES -static int stm32l5_nmi(int irq, void *context, void *arg) +static int stm32_nmi(int irq, void *context, void *arg) { up_irq_save(); _err("PANIC!!! NMI received\n"); @@ -134,7 +134,7 @@ static int stm32l5_nmi(int irq, void *context, void *arg) return 0; } -static int stm32l5_pendsv(int irq, void *context, void *arg) +static int stm32_pendsv(int irq, void *context, void *arg) { up_irq_save(); _err("PANIC!!! PendSV received\n"); @@ -142,7 +142,7 @@ static int stm32l5_pendsv(int irq, void *context, void *arg) return 0; } -static int stm32l5_reserved(int irq, void *context, void *arg) +static int stm32_reserved(int irq, void *context, void *arg) { up_irq_save(); _err("PANIC!!! Reserved interrupt\n"); @@ -152,7 +152,7 @@ static int stm32l5_reserved(int irq, void *context, void *arg) #endif /**************************************************************************** - * Name: stm32l5_prioritize_syscall + * Name: stm32_prioritize_syscall * * Description: * Set the priority of an exception. This function may be needed @@ -160,7 +160,7 @@ static int stm32l5_reserved(int irq, void *context, void *arg) * ****************************************************************************/ -static inline void stm32l5_prioritize_syscall(int priority) +static inline void stm32_prioritize_syscall(int priority) { uint32_t regval; @@ -173,7 +173,7 @@ static inline void stm32l5_prioritize_syscall(int priority) } /**************************************************************************** - * Name: stm32l5_irqinfo + * Name: stm32_irqinfo * * Description: * Given an IRQ number, provide the register and bit setting to enable or @@ -181,18 +181,18 @@ static inline void stm32l5_prioritize_syscall(int priority) * ****************************************************************************/ -static int stm32l5_irqinfo(int irq, uintptr_t *regaddr, uint32_t *bit, +static int stm32_irqinfo(int irq, uintptr_t *regaddr, uint32_t *bit, uintptr_t offset) { int n; - DEBUGASSERT(irq >= STM32L5_IRQ_NMI && irq < NR_IRQS); + DEBUGASSERT(irq >= STM32_IRQ_NMI && irq < NR_IRQS); /* Check for external interrupt */ - if (irq >= STM32L5_IRQ_FIRST) + if (irq >= STM32_IRQ_FIRST) { - n = irq - STM32L5_IRQ_FIRST; + n = irq - STM32_IRQ_FIRST; *regaddr = NVIC_IRQ_ENABLE(n) + offset; *bit = (uint32_t)1 << (n & 0x1f); } @@ -202,19 +202,19 @@ static int stm32l5_irqinfo(int irq, uintptr_t *regaddr, uint32_t *bit, else { *regaddr = NVIC_SYSHCON; - if (irq == STM32L5_IRQ_MEMFAULT) + if (irq == STM32_IRQ_MEMFAULT) { *bit = NVIC_SYSHCON_MEMFAULTENA; } - else if (irq == STM32L5_IRQ_BUSFAULT) + else if (irq == STM32_IRQ_BUSFAULT) { *bit = NVIC_SYSHCON_BUSFAULTENA; } - else if (irq == STM32L5_IRQ_USAGEFAULT) + else if (irq == STM32_IRQ_USAGEFAULT) { *bit = NVIC_SYSHCON_USGFAULTENA; } - else if (irq == STM32L5_IRQ_SYSTICK) + else if (irq == STM32_IRQ_SYSTICK) { *regaddr = NVIC_SYSTICK_CTRL; *bit = NVIC_SYSTICK_CTRL_ENABLE; @@ -244,7 +244,7 @@ void up_irqinitialize(void) /* Disable all interrupts */ - for (i = 0; i < NR_IRQS - STM32L5_IRQ_FIRST; i += 32) + for (i = 0; i < NR_IRQS - STM32_IRQ_FIRST; i += 32) { putreg32(0xffffffff, NVIC_IRQ_CLEAR(i)); } @@ -298,44 +298,44 @@ void up_irqinitialize(void) * under certain conditions. */ - irq_attach(STM32L5_IRQ_SVCALL, arm_svcall, NULL); - irq_attach(STM32L5_IRQ_HARDFAULT, arm_hardfault, NULL); + irq_attach(STM32_IRQ_SVCALL, arm_svcall, NULL); + irq_attach(STM32_IRQ_HARDFAULT, arm_hardfault, NULL); /* Set the priority of the SVCall interrupt */ #ifdef CONFIG_ARCH_IRQPRIO - /* up_prioritize_irq(STM32L5_IRQ_PENDSV, NVIC_SYSH_PRIORITY_MIN); */ + /* up_prioritize_irq(STM32_IRQ_PENDSV, NVIC_SYSH_PRIORITY_MIN); */ #endif - stm32l5_prioritize_syscall(NVIC_SYSH_SVCALL_PRIORITY); + stm32_prioritize_syscall(NVIC_SYSH_SVCALL_PRIORITY); /* If the MPU is enabled, then attach and enable the Memory Management * Fault handler. */ #ifdef CONFIG_ARM_MPU - irq_attach(STM32L5_IRQ_MEMFAULT, arm_memfault, NULL); - up_enable_irq(STM32L5_IRQ_MEMFAULT); + irq_attach(STM32_IRQ_MEMFAULT, arm_memfault, NULL); + up_enable_irq(STM32_IRQ_MEMFAULT); #endif /* Attach all other processor exceptions (except reset and sys tick) */ #ifdef CONFIG_DEBUG_FEATURES - irq_attach(STM32L5_IRQ_NMI, stm32l5_nmi, NULL); + irq_attach(STM32_IRQ_NMI, stm32_nmi, NULL); #ifndef CONFIG_ARM_MPU - irq_attach(STM32L5_IRQ_MEMFAULT, arm_memfault, NULL); + irq_attach(STM32_IRQ_MEMFAULT, arm_memfault, NULL); #endif - irq_attach(STM32L5_IRQ_BUSFAULT, arm_busfault, NULL); - irq_attach(STM32L5_IRQ_USAGEFAULT, arm_usagefault, NULL); - irq_attach(STM32L5_IRQ_PENDSV, stm32l5_pendsv, NULL); + irq_attach(STM32_IRQ_BUSFAULT, arm_busfault, NULL); + irq_attach(STM32_IRQ_USAGEFAULT, arm_usagefault, NULL); + irq_attach(STM32_IRQ_PENDSV, stm32_pendsv, NULL); arm_enable_dbgmonitor(); - irq_attach(STM32L5_IRQ_DBGMONITOR, arm_dbgmonitor, NULL); - irq_attach(STM32L5_IRQ_RESERVED, stm32l5_reserved, NULL); + irq_attach(STM32_IRQ_DBGMONITOR, arm_dbgmonitor, NULL); + irq_attach(STM32_IRQ_RESERVED, stm32_reserved, NULL); #endif - stm32l5_dumpnvic("initial", NR_IRQS); + stm32_dumpnvic("initial", NR_IRQS); #ifndef CONFIG_SUPPRESS_INTERRUPTS @@ -360,7 +360,7 @@ void up_disable_irq(int irq) uint32_t regval; uint32_t bit; - if (stm32l5_irqinfo(irq, ®addr, &bit, NVIC_CLRENA_OFFSET) == 0) + if (stm32_irqinfo(irq, ®addr, &bit, NVIC_CLRENA_OFFSET) == 0) { /* Modify the appropriate bit in the register to disable the interrupt. * For normal interrupts, we need to set the bit in the associated @@ -368,7 +368,7 @@ void up_disable_irq(int irq) * clear the bit in the System Handler Control and State Register. */ - if (irq >= STM32L5_IRQ_FIRST) + if (irq >= STM32_IRQ_FIRST) { putreg32(bit, regaddr); } @@ -395,7 +395,7 @@ void up_enable_irq(int irq) uint32_t regval; uint32_t bit; - if (stm32l5_irqinfo(irq, ®addr, &bit, NVIC_ENA_OFFSET) == 0) + if (stm32_irqinfo(irq, ®addr, &bit, NVIC_ENA_OFFSET) == 0) { /* Modify the appropriate bit in the register to enable the interrupt. * For normal interrupts, we need to set the bit in the associated @@ -403,7 +403,7 @@ void up_enable_irq(int irq) * set the bit in the System Handler Control and State Register. */ - if (irq >= STM32L5_IRQ_FIRST) + if (irq >= STM32_IRQ_FIRST) { putreg32(bit, regaddr); } @@ -446,10 +446,10 @@ int up_prioritize_irq(int irq, int priority) uint32_t regval; int shift; - DEBUGASSERT(irq >= STM32L5_IRQ_MEMFAULT && irq < NR_IRQS && + DEBUGASSERT(irq >= STM32_IRQ_MEMFAULT && irq < NR_IRQS && (unsigned)priority <= NVIC_SYSH_PRIORITY_MIN); - if (irq < STM32L5_IRQ_FIRST) + if (irq < STM32_IRQ_FIRST) { /* NVIC_SYSH_PRIORITY() maps {0..15} to one of three priority * registers (0-3 are invalid) @@ -462,7 +462,7 @@ int up_prioritize_irq(int irq, int priority) { /* NVIC_IRQ_PRIORITY() maps {0..} to one of many priority registers */ - irq -= STM32L5_IRQ_FIRST; + irq -= STM32_IRQ_FIRST; regaddr = NVIC_IRQ_PRIORITY(irq); } @@ -472,7 +472,7 @@ int up_prioritize_irq(int irq, int priority) regval |= (priority << shift); putreg32(regval, regaddr); - stm32l5_dumpnvic("prioritize", irq); + stm32_dumpnvic("prioritize", irq); return OK; } #endif diff --git a/arch/arm/src/stm32l5/stm32l5_lowputc.c b/arch/arm/src/stm32l5/stm32l5_lowputc.c index bcc1075c80ace..d10ce831abf3b 100644 --- a/arch/arm/src/stm32l5/stm32l5_lowputc.c +++ b/arch/arm/src/stm32l5/stm32l5_lowputc.c @@ -33,7 +33,7 @@ #include "arm_internal.h" #include "chip.h" -#include "stm32l5.h" +#include "stm32.h" #include "stm32l5_rcc.h" #include "stm32l5_gpio.h" #include "stm32l5_uart.h" @@ -46,127 +46,127 @@ #ifdef HAVE_CONSOLE # if defined(CONFIG_LPUART1_SERIAL_CONSOLE) -# define STM32L5_CONSOLE_BASE STM32L5_LPUART1_BASE -# define STM32L5_APBCLOCK STM32L5_PCLK1_FREQUENCY -# define STM32L5_CONSOLE_APBREG STM32L5_RCC_APB1ENR2 -# define STM32L5_CONSOLE_APBEN RCC_APB1ENR2_LPUART1EN -# define STM32L5_CONSOLE_BAUD CONFIG_LPUART1_BAUD -# define STM32L5_CONSOLE_BITS CONFIG_LPUART1_BITS -# define STM32L5_CONSOLE_PARITY CONFIG_LPUART1_PARITY -# define STM32L5_CONSOLE_2STOP CONFIG_LPUART1_2STOP -# define STM32L5_CONSOLE_TX GPIO_LPUART1_TX -# define STM32L5_CONSOLE_RX GPIO_LPUART1_RX +# define STM32_CONSOLE_BASE STM32_LPUART1_BASE +# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY +# define STM32_CONSOLE_APBREG STM32_RCC_APB1ENR2 +# define STM32_CONSOLE_APBEN RCC_APB1ENR2_LPUART1EN +# define STM32_CONSOLE_BAUD CONFIG_LPUART1_BAUD +# define STM32_CONSOLE_BITS CONFIG_LPUART1_BITS +# define STM32_CONSOLE_PARITY CONFIG_LPUART1_PARITY +# define STM32_CONSOLE_2STOP CONFIG_LPUART1_2STOP +# define STM32_CONSOLE_TX GPIO_LPUART1_TX +# define STM32_CONSOLE_RX GPIO_LPUART1_RX # ifdef CONFIG_LPUART1_RS485 -# define STM32L5_CONSOLE_RS485_DIR GPIO_LPUART1_RS485_DIR +# define STM32_CONSOLE_RS485_DIR GPIO_LPUART1_RS485_DIR # if (CONFIG_LPUART1_RS485_DIR_POLARITY == 0) -# define STM32L5_CONSOLE_RS485_DIR_POLARITY false +# define STM32_CONSOLE_RS485_DIR_POLARITY false # else -# define STM32L5_CONSOLE_RS485_DIR_POLARITY true +# define STM32_CONSOLE_RS485_DIR_POLARITY true # endif # endif # elif defined(CONFIG_USART1_SERIAL_CONSOLE) -# define STM32L5_CONSOLE_BASE STM32L5_USART1_BASE -# define STM32L5_APBCLOCK STM32L5_PCLK2_FREQUENCY -# define STM32L5_CONSOLE_APBREG STM32L5_RCC_APB2ENR -# define STM32L5_CONSOLE_APBEN RCC_APB2ENR_USART1EN -# define STM32L5_CONSOLE_BAUD CONFIG_USART1_BAUD -# define STM32L5_CONSOLE_BITS CONFIG_USART1_BITS -# define STM32L5_CONSOLE_PARITY CONFIG_USART1_PARITY -# define STM32L5_CONSOLE_2STOP CONFIG_USART1_2STOP -# define STM32L5_CONSOLE_TX GPIO_USART1_TX -# define STM32L5_CONSOLE_RX GPIO_USART1_RX +# define STM32_CONSOLE_BASE STM32_USART1_BASE +# define STM32_APBCLOCK STM32_PCLK2_FREQUENCY +# define STM32_CONSOLE_APBREG STM32_RCC_APB2ENR +# define STM32_CONSOLE_APBEN RCC_APB2ENR_USART1EN +# define STM32_CONSOLE_BAUD CONFIG_USART1_BAUD +# define STM32_CONSOLE_BITS CONFIG_USART1_BITS +# define STM32_CONSOLE_PARITY CONFIG_USART1_PARITY +# define STM32_CONSOLE_2STOP CONFIG_USART1_2STOP +# define STM32_CONSOLE_TX GPIO_USART1_TX +# define STM32_CONSOLE_RX GPIO_USART1_RX # ifdef CONFIG_USART1_RS485 -# define STM32L5_CONSOLE_RS485_DIR GPIO_USART1_RS485_DIR +# define STM32_CONSOLE_RS485_DIR GPIO_USART1_RS485_DIR # if (CONFIG_USART1_RS485_DIR_POLARITY == 0) -# define STM32L5_CONSOLE_RS485_DIR_POLARITY false +# define STM32_CONSOLE_RS485_DIR_POLARITY false # else -# define STM32L5_CONSOLE_RS485_DIR_POLARITY true +# define STM32_CONSOLE_RS485_DIR_POLARITY true # endif # endif # elif defined(CONFIG_USART2_SERIAL_CONSOLE) -# define STM32L5_CONSOLE_BASE STM32L5_USART2_BASE -# define STM32L5_APBCLOCK STM32L5_PCLK1_FREQUENCY -# define STM32L5_CONSOLE_APBREG STM32L5_RCC_APB1ENR1 -# define STM32L5_CONSOLE_APBEN RCC_APB1ENR1_USART2EN -# define STM32L5_CONSOLE_BAUD CONFIG_USART2_BAUD -# define STM32L5_CONSOLE_BITS CONFIG_USART2_BITS -# define STM32L5_CONSOLE_PARITY CONFIG_USART2_PARITY -# define STM32L5_CONSOLE_2STOP CONFIG_USART2_2STOP -# define STM32L5_CONSOLE_TX GPIO_USART2_TX -# define STM32L5_CONSOLE_RX GPIO_USART2_RX +# define STM32_CONSOLE_BASE STM32_USART2_BASE +# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY +# define STM32_CONSOLE_APBREG STM32_RCC_APB1ENR1 +# define STM32_CONSOLE_APBEN RCC_APB1ENR1_USART2EN +# define STM32_CONSOLE_BAUD CONFIG_USART2_BAUD +# define STM32_CONSOLE_BITS CONFIG_USART2_BITS +# define STM32_CONSOLE_PARITY CONFIG_USART2_PARITY +# define STM32_CONSOLE_2STOP CONFIG_USART2_2STOP +# define STM32_CONSOLE_TX GPIO_USART2_TX +# define STM32_CONSOLE_RX GPIO_USART2_RX # ifdef CONFIG_USART2_RS485 -# define STM32L5_CONSOLE_RS485_DIR GPIO_USART2_RS485_DIR +# define STM32_CONSOLE_RS485_DIR GPIO_USART2_RS485_DIR # if (CONFIG_USART2_RS485_DIR_POLARITY == 0) -# define STM32L5_CONSOLE_RS485_DIR_POLARITY false +# define STM32_CONSOLE_RS485_DIR_POLARITY false # else -# define STM32L5_CONSOLE_RS485_DIR_POLARITY true +# define STM32_CONSOLE_RS485_DIR_POLARITY true # endif # endif # elif defined(CONFIG_USART3_SERIAL_CONSOLE) -# define STM32L5_CONSOLE_BASE STM32L5_USART3_BASE -# define STM32L5_APBCLOCK STM32L5_PCLK1_FREQUENCY -# define STM32L5_CONSOLE_APBREG STM32L5_RCC_APB1ENR1 -# define STM32L5_CONSOLE_APBEN RCC_APB1ENR1_USART3EN -# define STM32L5_CONSOLE_BAUD CONFIG_USART3_BAUD -# define STM32L5_CONSOLE_BITS CONFIG_USART3_BITS -# define STM32L5_CONSOLE_PARITY CONFIG_USART3_PARITY -# define STM32L5_CONSOLE_2STOP CONFIG_USART3_2STOP -# define STM32L5_CONSOLE_TX GPIO_USART3_TX -# define STM32L5_CONSOLE_RX GPIO_USART3_RX +# define STM32_CONSOLE_BASE STM32_USART3_BASE +# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY +# define STM32_CONSOLE_APBREG STM32_RCC_APB1ENR1 +# define STM32_CONSOLE_APBEN RCC_APB1ENR1_USART3EN +# define STM32_CONSOLE_BAUD CONFIG_USART3_BAUD +# define STM32_CONSOLE_BITS CONFIG_USART3_BITS +# define STM32_CONSOLE_PARITY CONFIG_USART3_PARITY +# define STM32_CONSOLE_2STOP CONFIG_USART3_2STOP +# define STM32_CONSOLE_TX GPIO_USART3_TX +# define STM32_CONSOLE_RX GPIO_USART3_RX # ifdef CONFIG_USART3_RS485 -# define STM32L5_CONSOLE_RS485_DIR GPIO_USART3_RS485_DIR +# define STM32_CONSOLE_RS485_DIR GPIO_USART3_RS485_DIR # if (CONFIG_USART3_RS485_DIR_POLARITY == 0) -# define STM32L5_CONSOLE_RS485_DIR_POLARITY false +# define STM32_CONSOLE_RS485_DIR_POLARITY false # else -# define STM32L5_CONSOLE_RS485_DIR_POLARITY true +# define STM32_CONSOLE_RS485_DIR_POLARITY true # endif # endif # elif defined(CONFIG_UART4_SERIAL_CONSOLE) -# define STM32L5_CONSOLE_BASE STM32L5_UART4_BASE -# define STM32L5_APBCLOCK STM32L5_PCLK1_FREQUENCY -# define STM32L5_CONSOLE_APBREG STM32L5_RCC_APB1ENR1 -# define STM32L5_CONSOLE_APBEN RCC_APB1ENR1_UART4EN -# define STM32L5_CONSOLE_BAUD CONFIG_UART4_BAUD -# define STM32L5_CONSOLE_BITS CONFIG_UART4_BITS -# define STM32L5_CONSOLE_PARITY CONFIG_UART4_PARITY -# define STM32L5_CONSOLE_2STOP CONFIG_UART4_2STOP -# define STM32L5_CONSOLE_TX GPIO_UART4_TX -# define STM32L5_CONSOLE_RX GPIO_UART4_RX +# define STM32_CONSOLE_BASE STM32_UART4_BASE +# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY +# define STM32_CONSOLE_APBREG STM32_RCC_APB1ENR1 +# define STM32_CONSOLE_APBEN RCC_APB1ENR1_UART4EN +# define STM32_CONSOLE_BAUD CONFIG_UART4_BAUD +# define STM32_CONSOLE_BITS CONFIG_UART4_BITS +# define STM32_CONSOLE_PARITY CONFIG_UART4_PARITY +# define STM32_CONSOLE_2STOP CONFIG_UART4_2STOP +# define STM32_CONSOLE_TX GPIO_UART4_TX +# define STM32_CONSOLE_RX GPIO_UART4_RX # ifdef CONFIG_UART4_RS485 -# define STM32L5_CONSOLE_RS485_DIR GPIO_UART4_RS485_DIR +# define STM32_CONSOLE_RS485_DIR GPIO_UART4_RS485_DIR # if (CONFIG_UART4_RS485_DIR_POLARITY == 0) -# define STM32L5_CONSOLE_RS485_DIR_POLARITY false +# define STM32_CONSOLE_RS485_DIR_POLARITY false # else -# define STM32L5_CONSOLE_RS485_DIR_POLARITY true +# define STM32_CONSOLE_RS485_DIR_POLARITY true # endif # endif # elif defined(CONFIG_UART5_SERIAL_CONSOLE) -# define STM32L5_CONSOLE_BASE STM32L5_UART5_BASE -# define STM32L5_APBCLOCK STM32L5_PCLK1_FREQUENCY -# define STM32L5_CONSOLE_APBREG STM32L5_RCC_APB1ENR1 -# define STM32L5_CONSOLE_APBEN RCC_APB1ENR1_UART5EN -# define STM32L5_CONSOLE_BAUD CONFIG_UART5_BAUD -# define STM32L5_CONSOLE_BITS CONFIG_UART5_BITS -# define STM32L5_CONSOLE_PARITY CONFIG_UART5_PARITY -# define STM32L5_CONSOLE_2STOP CONFIG_UART5_2STOP -# define STM32L5_CONSOLE_TX GPIO_UART5_TX -# define STM32L5_CONSOLE_RX GPIO_UART5_RX +# define STM32_CONSOLE_BASE STM32_UART5_BASE +# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY +# define STM32_CONSOLE_APBREG STM32_RCC_APB1ENR1 +# define STM32_CONSOLE_APBEN RCC_APB1ENR1_UART5EN +# define STM32_CONSOLE_BAUD CONFIG_UART5_BAUD +# define STM32_CONSOLE_BITS CONFIG_UART5_BITS +# define STM32_CONSOLE_PARITY CONFIG_UART5_PARITY +# define STM32_CONSOLE_2STOP CONFIG_UART5_2STOP +# define STM32_CONSOLE_TX GPIO_UART5_TX +# define STM32_CONSOLE_RX GPIO_UART5_RX # ifdef CONFIG_UART5_RS485 -# define STM32L5_CONSOLE_RS485_DIR GPIO_UART5_RS485_DIR +# define STM32_CONSOLE_RS485_DIR GPIO_UART5_RS485_DIR # if (CONFIG_UART5_RS485_DIR_POLARITY == 0) -# define STM32L5_CONSOLE_RS485_DIR_POLARITY false +# define STM32_CONSOLE_RS485_DIR_POLARITY false # else -# define STM32L5_CONSOLE_RS485_DIR_POLARITY true +# define STM32_CONSOLE_RS485_DIR_POLARITY true # endif # endif # endif /* CR1 settings */ -# if STM32L5_CONSOLE_BITS == 9 +# if STM32_CONSOLE_BITS == 9 # define USART_CR1_M0_VALUE USART_CR1_M0 # define USART_CR1_M1_VALUE 0 -# elif STM32L5_CONSOLE_BITS == 7 +# elif STM32_CONSOLE_BITS == 7 # define USART_CR1_M0_VALUE 0 # define USART_CR1_M1_VALUE USART_CR1_M1 # else /* 8 bits */ @@ -174,9 +174,9 @@ # define USART_CR1_M1_VALUE 0 # endif -# if STM32L5_CONSOLE_PARITY == 1 /* odd parity */ +# if STM32_CONSOLE_PARITY == 1 /* odd parity */ # define USART_CR1_PARITY_VALUE (USART_CR1_PCE|USART_CR1_PS) -# elif STM32L5_CONSOLE_PARITY == 2 /* even parity */ +# elif STM32_CONSOLE_PARITY == 2 /* even parity */ # define USART_CR1_PARITY_VALUE USART_CR1_PCE # else /* no parity */ # define USART_CR1_PARITY_VALUE 0 @@ -192,7 +192,7 @@ /* CR2 settings */ -# if STM32L5_CONSOLE_2STOP != 0 +# if STM32_CONSOLE_2STOP != 0 # define USART_CR2_STOP2_VALUE USART_CR2_STOP2 # else # define USART_CR2_STOP2_VALUE 0 @@ -232,8 +232,8 @@ * LPUARTDIV must be in range [0x300, 0xFFFFF]. */ -# define STM32L5_BRR_VALUE \ - ((((uint64_t)STM32L5_APBCLOCK << 8) + (STM32L5_CONSOLE_BAUD >> 1)) / STM32L5_CONSOLE_BAUD) +# define STM32_BRR_VALUE \ + ((((uint64_t)STM32_APBCLOCK << 8) + (STM32_CONSOLE_BAUD >> 1)) / STM32_CONSOLE_BAUD) # else @@ -249,19 +249,19 @@ * UARTDIV = 2 * fCK / baud */ -# define STM32L5_USARTDIV8 \ - (((STM32L5_APBCLOCK << 1) + (STM32L5_CONSOLE_BAUD >> 1)) / STM32L5_CONSOLE_BAUD) -# define STM32L5_USARTDIV16 \ - ((STM32L5_APBCLOCK + (STM32L5_CONSOLE_BAUD >> 1)) / STM32L5_CONSOLE_BAUD) +# define STM32_USARTDIV8 \ + (((STM32_APBCLOCK << 1) + (STM32_CONSOLE_BAUD >> 1)) / STM32_CONSOLE_BAUD) +# define STM32_USARTDIV16 \ + ((STM32_APBCLOCK + (STM32_CONSOLE_BAUD >> 1)) / STM32_CONSOLE_BAUD) /* Use oversamply by 8 only if the divisor is small. But what is small? */ -# if STM32L5_USARTDIV8 > 2000 -# define STM32L5_BRR_VALUE STM32L5_USARTDIV16 +# if STM32_USARTDIV8 > 2000 +# define STM32_BRR_VALUE STM32_USARTDIV16 # else # define USE_OVER8 1 -# define STM32L5_BRR_VALUE \ - ((STM32L5_USARTDIV8 & 0xfff0) | ((STM32L5_USARTDIV8 & 0x000f) >> 1)) +# define STM32_BRR_VALUE \ + ((STM32_USARTDIV8 & 0xfff0) | ((STM32_USARTDIV8 & 0x000f) >> 1)) # endif # endif /* CONFIG_LPUART1_SERIAL_CONSOLE */ @@ -305,29 +305,29 @@ void arm_lowputc(char ch) #ifdef HAVE_CONSOLE /* Wait until the TX data register is empty */ - while ((getreg32(STM32L5_CONSOLE_BASE + STM32L5_USART_ISR_OFFSET) & + while ((getreg32(STM32_CONSOLE_BASE + STM32_USART_ISR_OFFSET) & USART_ISR_TXE) == 0); -#ifdef STM32L5_CONSOLE_RS485_DIR - stm32l5_gpiowrite(STM32L5_CONSOLE_RS485_DIR, - STM32L5_CONSOLE_RS485_DIR_POLARITY); +#ifdef STM32_CONSOLE_RS485_DIR + stm32_gpiowrite(STM32_CONSOLE_RS485_DIR, + STM32_CONSOLE_RS485_DIR_POLARITY); #endif /* Then send the character */ - putreg32((uint32_t)ch, STM32L5_CONSOLE_BASE + STM32L5_USART_TDR_OFFSET); + putreg32((uint32_t)ch, STM32_CONSOLE_BASE + STM32_USART_TDR_OFFSET); -#ifdef STM32L5_CONSOLE_RS485_DIR - while ((getreg32(STM32L5_CONSOLE_BASE + STM32L5_USART_ISR_OFFSET) & +#ifdef STM32_CONSOLE_RS485_DIR + while ((getreg32(STM32_CONSOLE_BASE + STM32_USART_ISR_OFFSET) & USART_ISR_TC) == 0); - stm32l5_gpiowrite(STM32L5_CONSOLE_RS485_DIR, - !STM32L5_CONSOLE_RS485_DIR_POLARITY); + stm32_gpiowrite(STM32_CONSOLE_RS485_DIR, + !STM32_CONSOLE_RS485_DIR_POLARITY); #endif #endif /* HAVE_CONSOLE */ } /**************************************************************************** - * Name: stm32l5_lowsetup + * Name: stm32_lowsetup * * Description: * This performs basic initialization of the USART used for the serial @@ -336,7 +336,7 @@ void arm_lowputc(char ch) * ****************************************************************************/ -void stm32l5_lowsetup(void) +void stm32_lowsetup(void) { #if defined(HAVE_UART) #if defined(HAVE_CONSOLE) && !defined(CONFIG_SUPPRESS_UART_CONFIG) @@ -346,26 +346,26 @@ void stm32l5_lowsetup(void) #if defined(HAVE_CONSOLE) /* Enable USART APB1/2 clock */ - modifyreg32(STM32L5_CONSOLE_APBREG, 0, STM32L5_CONSOLE_APBEN); + modifyreg32(STM32_CONSOLE_APBREG, 0, STM32_CONSOLE_APBEN); #endif /* Enable the console USART and configure GPIO pins needed for rx/tx. * * NOTE: Clocking for selected U[S]ARTs was already provided in - * stm32l5_rcc.c + * stm32_rcc.c */ -#ifdef STM32L5_CONSOLE_TX - stm32l5_configgpio(STM32L5_CONSOLE_TX); +#ifdef STM32_CONSOLE_TX + stm32_configgpio(STM32_CONSOLE_TX); #endif -#ifdef STM32L5_CONSOLE_RX - stm32l5_configgpio(STM32L5_CONSOLE_RX); +#ifdef STM32_CONSOLE_RX + stm32_configgpio(STM32_CONSOLE_RX); #endif -#ifdef STM32L5_CONSOLE_RS485_DIR - stm32l5_configgpio(STM32L5_CONSOLE_RS485_DIR); - stm32l5_gpiowrite(STM32L5_CONSOLE_RS485_DIR, - !STM32L5_CONSOLE_RS485_DIR_POLARITY); +#ifdef STM32_CONSOLE_RS485_DIR + stm32_configgpio(STM32_CONSOLE_RS485_DIR); + stm32_gpiowrite(STM32_CONSOLE_RS485_DIR, + !STM32_CONSOLE_RS485_DIR_POLARITY); #endif /* Enable and configure the selected console device */ @@ -373,42 +373,42 @@ void stm32l5_lowsetup(void) #if defined(HAVE_CONSOLE) && !defined(CONFIG_SUPPRESS_UART_CONFIG) /* Configure CR2 */ - cr = getreg32(STM32L5_CONSOLE_BASE + STM32L5_USART_CR2_OFFSET); + cr = getreg32(STM32_CONSOLE_BASE + STM32_USART_CR2_OFFSET); cr &= ~USART_CR2_CLRBITS; cr |= USART_CR2_SETBITS; - putreg32(cr, STM32L5_CONSOLE_BASE + STM32L5_USART_CR2_OFFSET); + putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR2_OFFSET); /* Configure CR1 */ - cr = getreg32(STM32L5_CONSOLE_BASE + STM32L5_USART_CR1_OFFSET); + cr = getreg32(STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET); cr &= ~USART_CR1_CLRBITS; cr |= USART_CR1_SETBITS; - putreg32(cr, STM32L5_CONSOLE_BASE + STM32L5_USART_CR1_OFFSET); + putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET); /* Configure CR3 */ - cr = getreg32(STM32L5_CONSOLE_BASE + STM32L5_USART_CR3_OFFSET); + cr = getreg32(STM32_CONSOLE_BASE + STM32_USART_CR3_OFFSET); cr &= ~USART_CR3_CLRBITS; cr |= USART_CR3_SETBITS; - putreg32(cr, STM32L5_CONSOLE_BASE + STM32L5_USART_CR3_OFFSET); + putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR3_OFFSET); /* Configure the USART Baud Rate */ - putreg32(STM32L5_BRR_VALUE, - STM32L5_CONSOLE_BASE + STM32L5_USART_BRR_OFFSET); + putreg32(STM32_BRR_VALUE, + STM32_CONSOLE_BASE + STM32_USART_BRR_OFFSET); /* Select oversampling by 8 */ - cr = getreg32(STM32L5_CONSOLE_BASE + STM32L5_USART_CR1_OFFSET); + cr = getreg32(STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET); #ifdef USE_OVER8 cr |= USART_CR1_OVER8; - putreg32(cr, STM32L5_CONSOLE_BASE + STM32L5_USART_CR1_OFFSET); + putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET); #endif /* Enable Rx, Tx, and the USART */ cr |= (USART_CR1_UE | USART_CR1_TE | USART_CR1_RE); - putreg32(cr, STM32L5_CONSOLE_BASE + STM32L5_USART_CR1_OFFSET); + putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET); #endif /* HAVE_CONSOLE && !CONFIG_SUPPRESS_UART_CONFIG */ #endif /* HAVE_UART */ diff --git a/arch/arm/src/stm32l5/stm32l5_lowputc.h b/arch/arm/src/stm32l5/stm32l5_lowputc.h index 29e808377c34e..0f8de0670dfd1 100644 --- a/arch/arm/src/stm32l5/stm32l5_lowputc.h +++ b/arch/arm/src/stm32l5/stm32l5_lowputc.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32L5_STM32L5_LOWPUTC_H -#define __ARCH_ARM_SRC_STM32L5_STM32L5_LOWPUTC_H +#ifndef __ARCH_ARM_SRC_STM32L5_STM32_LOWPUTC_H +#define __ARCH_ARM_SRC_STM32L5_STM32_LOWPUTC_H /**************************************************************************** * Included Files @@ -47,7 +47,7 @@ extern "C" #endif /**************************************************************************** - * Name: stm32l5_lowsetup + * Name: stm32_lowsetup * * Description: * Called at the very beginning of _start. Performs low level @@ -55,7 +55,7 @@ extern "C" * ****************************************************************************/ -void stm32l5_lowsetup(void); +void stm32_lowsetup(void); #undef EXTERN #if defined(__cplusplus) @@ -63,4 +63,4 @@ void stm32l5_lowsetup(void); #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32L5_STM32L5_LOWPUTC_H */ +#endif /* __ARCH_ARM_SRC_STM32L5_STM32_LOWPUTC_H */ diff --git a/arch/arm/src/stm32l5/stm32l5_lse.c b/arch/arm/src/stm32l5/stm32l5_lse.c index b990134a4f783..88a4c676ea101 100644 --- a/arch/arm/src/stm32l5/stm32l5_lse.c +++ b/arch/arm/src/stm32l5/stm32l5_lse.c @@ -31,7 +31,7 @@ #include "arm_internal.h" #include "stm32l5_pwr.h" #include "stm32l5_rcc.h" -#include "stm32l5_waste.h" +#include "stm32_waste.h" /**************************************************************************** * Pre-processor Definitions @@ -42,9 +42,9 @@ static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1, #define LSERDY_TIMEOUT (500 * CONFIG_BOARD_LOOPSPERMSEC) -#ifdef CONFIG_STM32L5_RTC_LSECLOCK_START_DRV_CAPABILITY -# if CONFIG_STM32L5_RTC_LSECLOCK_START_DRV_CAPABILITY < 0 || \ - CONFIG_STM32L5_RTC_LSECLOCK_START_DRV_CAPABILITY > 3 +#ifdef CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY +# if CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY < 0 || \ + CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY > 3 # error "Invalid LSE drive capability setting" # endif #endif @@ -53,7 +53,7 @@ static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1, * Private Data ****************************************************************************/ -#ifdef CONFIG_STM32L5_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY +#ifdef CONFIG_STM32_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY static const uint32_t drives[4] = { RCC_BDCR_LSEDRV_LOW, @@ -68,19 +68,19 @@ static const uint32_t drives[4] = ****************************************************************************/ /**************************************************************************** - * Name: stm32l5_rcc_enablelse + * Name: stm32_rcc_enablelse * * Description: * Enable the External Low-Speed (LSE) oscillator and the LSE system clock. * ****************************************************************************/ -void stm32l5_rcc_enablelse(void) +void stm32_rcc_enablelse(void) { bool writable; uint32_t regval; volatile int32_t timeout; -#ifdef CONFIG_STM32L5_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY +#ifdef CONFIG_STM32_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY volatile int32_t drive = 0; #endif @@ -88,7 +88,7 @@ void stm32l5_rcc_enablelse(void) * clock are already running. */ - regval = getreg32(STM32L5_RCC_BDCR); + regval = getreg32(STM32_RCC_BDCR); if ((regval & (RCC_BDCR_LSEON | RCC_BDCR_LSERDY | RCC_BDCR_LSESYSEN | RCC_BDCR_LSESYSEN)) != @@ -100,7 +100,7 @@ void stm32l5_rcc_enablelse(void) * the PWR CR register before to configuring the LSE. */ - writable = stm32l5_pwr_enablebkp(true); + writable = stm32_pwr_enablebkp(true); /* Enable the External Low-Speed (LSE) oscillator by setting the LSEON * bit the RCC BDCR register. @@ -108,28 +108,28 @@ void stm32l5_rcc_enablelse(void) regval |= RCC_BDCR_LSEON; -#ifdef CONFIG_STM32L5_RTC_LSECLOCK_START_DRV_CAPABILITY +#ifdef CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY /* Set start-up drive capability for LSE oscillator. LSE must be OFF * to change drive strength. */ regval &= ~(RCC_BDCR_LSEDRV_MASK | RCC_BDCR_LSEON); - regval |= CONFIG_STM32L5_RTC_LSECLOCK_START_DRV_CAPABILITY << + regval |= CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY << RCC_BDCR_LSEDRV_SHIFT; - putreg32(regval, STM32L5_RCC_BDCR); + putreg32(regval, STM32_RCC_BDCR); regval |= RCC_BDCR_LSEON; #endif -#ifdef CONFIG_STM32L5_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY +#ifdef CONFIG_STM32_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY do { regval &= ~(RCC_BDCR_LSEDRV_MASK | RCC_BDCR_LSEON); regval |= drives[drive++]; - putreg32(regval, STM32L5_RCC_BDCR); + putreg32(regval, STM32_RCC_BDCR); regval |= RCC_BDCR_LSEON; #endif - putreg32(regval, STM32L5_RCC_BDCR); + putreg32(regval, STM32_RCC_BDCR); /* Wait for the LSE clock to be ready (or until a timeout elapsed) */ @@ -138,7 +138,7 @@ void stm32l5_rcc_enablelse(void) { /* Check if the LSERDY flag is the set in the BDCR */ - regval = getreg32(STM32L5_RCC_BDCR); + regval = getreg32(STM32_RCC_BDCR); if (regval & RCC_BDCR_LSERDY) { @@ -148,7 +148,7 @@ void stm32l5_rcc_enablelse(void) } } -#ifdef CONFIG_STM32L5_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY +#ifdef CONFIG_STM32_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY if (timeout != 0) { break; @@ -166,28 +166,28 @@ void stm32l5_rcc_enablelse(void) regval |= RCC_BDCR_LSESYSEN; - putreg32(regval, STM32L5_RCC_BDCR); + putreg32(regval, STM32_RCC_BDCR); /* Wait for the LSE system clock to be ready */ - while (!((regval = getreg32(STM32L5_RCC_BDCR)) & + while (!((regval = getreg32(STM32_RCC_BDCR)) & RCC_BDCR_LSESYSRDY)) { - stm32l5_waste(); + stm32_waste(); } } -#ifdef CONFIG_STM32L5_RTC_LSECLOCK_LOWER_RUN_DRV_CAPABILITY +#ifdef CONFIG_STM32_RTC_LSECLOCK_LOWER_RUN_DRV_CAPABILITY /* Set running drive capability for LSE oscillator. */ regval &= ~RCC_BDCR_LSEDRV_MASK; regval |= RCC_BDCR_LSEDRV_LOW << RCC_BDCR_LSEDRV_SHIFT; - putreg32(regval, STM32L5_RCC_BDCR); + putreg32(regval, STM32_RCC_BDCR); #endif /* Disable backup domain access if it was disabled on entry */ - stm32l5_pwr_enablebkp(writable); + stm32_pwr_enablebkp(writable); } } diff --git a/arch/arm/src/stm32l5/stm32l5_lsi.c b/arch/arm/src/stm32l5/stm32l5_lsi.c index 507e7a1a8b2d5..6d57b07aac4ae 100644 --- a/arch/arm/src/stm32l5/stm32l5_lsi.c +++ b/arch/arm/src/stm32l5/stm32l5_lsi.c @@ -33,41 +33,41 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32l5_rcc_enablelsi + * Name: stm32_rcc_enablelsi * * Description: * Enable the Internal Low-Speed (LSI) RC Oscillator. * ****************************************************************************/ -void stm32l5_rcc_enablelsi(void) +void stm32_rcc_enablelsi(void) { /* Enable the Internal Low-Speed (LSI) RC Oscillator by setting the LSION * bit the RCC CSR register. */ - modifyreg32(STM32L5_RCC_CSR, 0, RCC_CSR_LSION); + modifyreg32(STM32_RCC_CSR, 0, RCC_CSR_LSION); /* Wait for the internal LSI oscillator to be stable. */ - while ((getreg32(STM32L5_RCC_CSR) & RCC_CSR_LSIRDY) == 0); + while ((getreg32(STM32_RCC_CSR) & RCC_CSR_LSIRDY) == 0); } /**************************************************************************** - * Name: stm32l5_rcc_disablelsi + * Name: stm32_rcc_disablelsi * * Description: * Disable the Internal Low-Speed (LSI) RC Oscillator. * ****************************************************************************/ -void stm32l5_rcc_disablelsi(void) +void stm32_rcc_disablelsi(void) { /* Enable the Internal Low-Speed (LSI) RC Oscillator by setting the LSION * bit the RCC CSR register. */ - modifyreg32(STM32L5_RCC_CSR, RCC_CSR_LSION, 0); + modifyreg32(STM32_RCC_CSR, RCC_CSR_LSION, 0); /* LSIRDY should go low after 3 LSI clock cycles */ } diff --git a/arch/arm/src/stm32l5/stm32l5_mpuinit.c b/arch/arm/src/stm32l5/stm32l5_mpuinit.c index 94d42c795aefa..2c70971fdded1 100644 --- a/arch/arm/src/stm32l5/stm32l5_mpuinit.c +++ b/arch/arm/src/stm32l5/stm32l5_mpuinit.c @@ -41,7 +41,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32l5_mpuinitialize + * Name: stm32_mpuinitialize * * Description: * Configure the MPU to permit user-space access to only restricted SAM3U @@ -49,7 +49,7 @@ * ****************************************************************************/ -void stm32l5_mpuinitialize(void) +void stm32_mpuinitialize(void) { uintptr_t datastart = MIN(USERSPACE->us_datastart, USERSPACE->us_bssstart); uintptr_t dataend = MAX(USERSPACE->us_dataend, USERSPACE->us_bssend); @@ -74,7 +74,7 @@ void stm32l5_mpuinitialize(void) } /**************************************************************************** - * Name: stm32l5_mpu_uheap + * Name: stm32_mpu_uheap * * Description: * Map the user-heap region. @@ -83,7 +83,7 @@ void stm32l5_mpuinitialize(void) * ****************************************************************************/ -void stm32l5_mpu_uheap(uintptr_t start, size_t size) +void stm32_mpu_uheap(uintptr_t start, size_t size) { mpu_user_intsram(start, size); } diff --git a/arch/arm/src/stm32l5/stm32l5_mpuinit.h b/arch/arm/src/stm32l5/stm32l5_mpuinit.h index 94ee60dc2855b..7eee119c5793e 100644 --- a/arch/arm/src/stm32l5/stm32l5_mpuinit.h +++ b/arch/arm/src/stm32l5/stm32l5_mpuinit.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32L5_STM32L5_MPUINIT_H -#define __ARCH_ARM_SRC_STM32L5_STM32L5_MPUINIT_H +#ifndef __ARCH_ARM_SRC_STM32L5_STM32_MPUINIT_H +#define __ARCH_ARM_SRC_STM32L5_STM32_MPUINIT_H /**************************************************************************** * Included Files @@ -34,7 +34,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32l5_mpuinitialize + * Name: stm32_mpuinitialize * * Description: * Configure the MPU to permit user-space access to only unrestricted MCU @@ -43,13 +43,13 @@ ****************************************************************************/ #ifdef CONFIG_BUILD_PROTECTED -void stm32l5_mpuinitialize(void); +void stm32_mpuinitialize(void); #else -# define stm32l5_mpuinitialize() +# define stm32_mpuinitialize() #endif /**************************************************************************** - * Name: stm32l5_mpu_uheap + * Name: stm32_mpu_uheap * * Description: * Map the user heap region. @@ -57,9 +57,9 @@ void stm32l5_mpuinitialize(void); ****************************************************************************/ #ifdef CONFIG_BUILD_PROTECTED -void stm32l5_mpu_uheap(uintptr_t start, size_t size); +void stm32_mpu_uheap(uintptr_t start, size_t size); #else -# define stm32l5_mpu_uheap(start,size) +# define stm32_mpu_uheap(start,size) #endif -#endif /* __ARCH_ARM_SRC_STM32L5_STM32L5_MPUINIT_H */ +#endif /* __ARCH_ARM_SRC_STM32L5_STM32_MPUINIT_H */ diff --git a/arch/arm/src/stm32l5/stm32l5_pwr.c b/arch/arm/src/stm32l5/stm32l5_pwr.c index 925be6f7c9006..90ac2900f6bf8 100644 --- a/arch/arm/src/stm32l5/stm32l5_pwr.c +++ b/arch/arm/src/stm32l5/stm32l5_pwr.c @@ -39,14 +39,14 @@ * Private Functions ****************************************************************************/ -static inline uint16_t stm32l5_pwr_getreg(uint8_t offset) +static inline uint16_t stm32_pwr_getreg(uint8_t offset) { - return (uint16_t)getreg32(STM32L5_PWR_BASE + (uint32_t)offset); + return (uint16_t)getreg32(STM32_PWR_BASE + (uint32_t)offset); } -static inline void stm32l5_pwr_putreg(uint8_t offset, uint16_t value) +static inline void stm32_pwr_putreg(uint8_t offset, uint16_t value) { - putreg32((uint32_t)value, STM32L5_PWR_BASE + (uint32_t)offset); + putreg32((uint32_t)value, STM32_PWR_BASE + (uint32_t)offset); } /**************************************************************************** @@ -70,12 +70,12 @@ static inline void stm32l5_pwr_putreg(uint8_t offset, uint16_t value) * ****************************************************************************/ -bool stm32l5_pwr_enableclk(bool enable) +bool stm32_pwr_enableclk(bool enable) { uint32_t regval; bool wasenabled; - regval = getreg32(STM32L5_RCC_APB1ENR1); + regval = getreg32(STM32_RCC_APB1ENR1); wasenabled = ((regval & RCC_APB1ENR1_PWREN) != 0); /* Power interface clock enable. */ @@ -85,21 +85,21 @@ bool stm32l5_pwr_enableclk(bool enable) /* Disable power interface clock */ regval &= ~RCC_APB1ENR1_PWREN; - putreg32(regval, STM32L5_RCC_APB1ENR1); + putreg32(regval, STM32_RCC_APB1ENR1); } else if (!wasenabled && enable) { /* Enable power interface clock */ regval |= RCC_APB1ENR1_PWREN; - putreg32(regval, STM32L5_RCC_APB1ENR1); + putreg32(regval, STM32_RCC_APB1ENR1); } return wasenabled; } /**************************************************************************** - * Name: stm32l5_pwr_enablebkp + * Name: stm32_pwr_enablebkp * * Description: * Enables access to the backup domain (RTC registers, RTC backup data @@ -113,14 +113,14 @@ bool stm32l5_pwr_enableclk(bool enable) * ****************************************************************************/ -bool stm32l5_pwr_enablebkp(bool writable) +bool stm32_pwr_enablebkp(bool writable) { uint16_t regval; bool waswritable; /* Get the current state of the STM32L5 PWR control register 1 */ - regval = stm32l5_pwr_getreg(STM32L5_PWR_CR1_OFFSET); + regval = stm32_pwr_getreg(STM32_PWR_CR1_OFFSET); waswritable = ((regval & PWR_CR1_DBP) != 0); /* Enable or disable the ability to write */ @@ -130,14 +130,14 @@ bool stm32l5_pwr_enablebkp(bool writable) /* Disable backup domain access */ regval &= ~PWR_CR1_DBP; - stm32l5_pwr_putreg(STM32L5_PWR_CR1_OFFSET, regval); + stm32_pwr_putreg(STM32_PWR_CR1_OFFSET, regval); } else if (!waswritable && writable) { /* Enable backup domain access */ regval |= PWR_CR1_DBP; - stm32l5_pwr_putreg(STM32L5_PWR_CR1_OFFSET, regval); + stm32_pwr_putreg(STM32_PWR_CR1_OFFSET, regval); /* Enable does not happen right away */ @@ -148,7 +148,7 @@ bool stm32l5_pwr_enablebkp(bool writable) } /**************************************************************************** - * Name: stm32l5_pwr_enableusv + * Name: stm32_pwr_enableusv * * Description: * Enables or disables the USB Supply Valid monitoring. Setting this bit @@ -163,23 +163,23 @@ bool stm32l5_pwr_enablebkp(bool writable) * ****************************************************************************/ -bool stm32l5_pwr_enableusv(bool set) +bool stm32_pwr_enableusv(bool set) { uint32_t regval; bool was_set; bool was_clk_enabled; - regval = getreg32(STM32L5_RCC_APB1ENR1); + regval = getreg32(STM32_RCC_APB1ENR1); was_clk_enabled = ((regval & RCC_APB1ENR1_PWREN) != 0); if (!was_clk_enabled) { - stm32l5_pwr_enableclk(true); + stm32_pwr_enableclk(true); } /* Get the current state of the STM32L5 PWR control register 2 */ - regval = stm32l5_pwr_getreg(STM32L5_PWR_CR2_OFFSET); + regval = stm32_pwr_getreg(STM32_PWR_CR2_OFFSET); was_set = ((regval & PWR_CR2_USV) != 0); /* Enable or disable the ability to write */ @@ -189,26 +189,26 @@ bool stm32l5_pwr_enableusv(bool set) /* Disable the Vddusb monitoring */ regval &= ~PWR_CR2_USV; - stm32l5_pwr_putreg(STM32L5_PWR_CR2_OFFSET, regval); + stm32_pwr_putreg(STM32_PWR_CR2_OFFSET, regval); } else if (!was_set && set) { /* Enable the Vddusb monitoring */ regval |= PWR_CR2_USV; - stm32l5_pwr_putreg(STM32L5_PWR_CR2_OFFSET, regval); + stm32_pwr_putreg(STM32_PWR_CR2_OFFSET, regval); } if (!was_clk_enabled) { - stm32l5_pwr_enableclk(false); + stm32_pwr_enableclk(false); } return was_set; } /**************************************************************************** - * Name: stm32l5_pwr_vddio2_valid + * Name: stm32_pwr_vddio2_valid * * Description: * Report that the Vddio2 independent I/Os supply voltage is valid or not. @@ -223,23 +223,23 @@ bool stm32l5_pwr_enableusv(bool set) * ****************************************************************************/ -bool stm32l5_pwr_vddio2_valid(bool set) +bool stm32_pwr_vddio2_valid(bool set) { uint32_t regval; bool was_set; bool was_clk_enabled; - regval = getreg32(STM32L5_RCC_APB1ENR1); + regval = getreg32(STM32_RCC_APB1ENR1); was_clk_enabled = ((regval & RCC_APB1ENR1_PWREN) != 0); if (!was_clk_enabled) { - stm32l5_pwr_enableclk(true); + stm32_pwr_enableclk(true); } /* Get the current state of the STM32L5 PWR control register 2 */ - regval = stm32l5_pwr_getreg(STM32L5_PWR_CR2_OFFSET); + regval = stm32_pwr_getreg(STM32_PWR_CR2_OFFSET); was_set = ((regval & PWR_CR2_IOSV) != 0); /* Enable or disable the ability to write */ @@ -249,19 +249,19 @@ bool stm32l5_pwr_vddio2_valid(bool set) /* Reset the Vddio2 independent I/O supply valid bit. */ regval &= ~PWR_CR2_IOSV; - stm32l5_pwr_putreg(STM32L5_PWR_CR2_OFFSET, regval); + stm32_pwr_putreg(STM32_PWR_CR2_OFFSET, regval); } else if (!was_set && set) { /* Set the Vddio2 independent I/O supply valid bit. */ regval |= PWR_CR2_IOSV; - stm32l5_pwr_putreg(STM32L5_PWR_CR2_OFFSET, regval); + stm32_pwr_putreg(STM32_PWR_CR2_OFFSET, regval); } if (!was_clk_enabled) { - stm32l5_pwr_enableclk(false); + stm32_pwr_enableclk(false); } return was_set; diff --git a/arch/arm/src/stm32l5/stm32l5_pwr.h b/arch/arm/src/stm32l5/stm32l5_pwr.h index 611eaf8e001cb..4a7f5c33df224 100644 --- a/arch/arm/src/stm32l5/stm32l5_pwr.h +++ b/arch/arm/src/stm32l5/stm32l5_pwr.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32L5_STM32L5_PWR_H -#define __ARCH_ARM_SRC_STM32L5_STM32L5_PWR_H +#ifndef __ARCH_ARM_SRC_STM32L5_STM32_PWR_H +#define __ARCH_ARM_SRC_STM32L5_STM32_PWR_H /**************************************************************************** * Included Files @@ -70,10 +70,10 @@ extern "C" * ****************************************************************************/ -bool stm32l5_pwr_enableclk(bool enable); +bool stm32_pwr_enableclk(bool enable); /**************************************************************************** - * Name: stm32l5_pwr_enablebkp + * Name: stm32_pwr_enablebkp * * Description: * Enables access to the backup domain (RTC registers, RTC backup data @@ -87,10 +87,10 @@ bool stm32l5_pwr_enableclk(bool enable); * ****************************************************************************/ -bool stm32l5_pwr_enablebkp(bool writable); +bool stm32_pwr_enablebkp(bool writable); /**************************************************************************** - * Name: stm32l5_pwr_enableusv + * Name: stm32_pwr_enableusv * * Description: * Enables or disables the USB Supply Valid monitoring. Setting this bit @@ -105,10 +105,10 @@ bool stm32l5_pwr_enablebkp(bool writable); * ****************************************************************************/ -bool stm32l5_pwr_enableusv(bool set); +bool stm32_pwr_enableusv(bool set); /**************************************************************************** - * Name: stm32l5_pwr_vddio2_valid + * Name: stm32_pwr_vddio2_valid * * Description: * Report that the Vddio2 independent I/Os supply voltage is valid or not. @@ -123,7 +123,7 @@ bool stm32l5_pwr_enableusv(bool set); * ****************************************************************************/ -bool stm32l5_pwr_vddio2_valid(bool set); +bool stm32_pwr_vddio2_valid(bool set); #undef EXTERN #if defined(__cplusplus) @@ -131,4 +131,4 @@ bool stm32l5_pwr_vddio2_valid(bool set); #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32L5_STM32L5_PWR_H */ +#endif /* __ARCH_ARM_SRC_STM32L5_STM32_PWR_H */ diff --git a/arch/arm/src/stm32l5/stm32l5_rcc.c b/arch/arm/src/stm32l5/stm32l5_rcc.c index c2f6421d7cce5..bf74e79a0c4c6 100644 --- a/arch/arm/src/stm32l5/stm32l5_rcc.c +++ b/arch/arm/src/stm32l5/stm32l5_rcc.c @@ -37,8 +37,8 @@ #include "chip.h" #include "stm32l5_rcc.h" #include "stm32l5_flash.h" -#include "stm32l5.h" -#include "stm32l5_waste.h" +#include "stm32.h" +#include "stm32_waste.h" /**************************************************************************** * Pre-processor Definitions @@ -83,52 +83,52 @@ static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1, * ****************************************************************************/ -#if defined(CONFIG_STM32L5_PWR) && defined(CONFIG_STM32L5_RTC) +#if defined(CONFIG_STM32_PWR) && defined(CONFIG_STM32_RTC) static inline void rcc_resetbkp(void) { bool init_stat; /* Check if the RTC is already configured */ - init_stat = stm32l5_rtc_is_initialized(); + init_stat = stm32_rtc_is_initialized(); if (!init_stat) { - uint32_t bkregs[STM32L5_RTC_BKCOUNT]; + uint32_t bkregs[STM32_RTC_BKCOUNT]; int i; /* Backup backup-registers before RTC reset. */ - for (i = 0; i < STM32L5_RTC_BKCOUNT; i++) + for (i = 0; i < STM32_RTC_BKCOUNT; i++) { - bkregs[i] = getreg32(STM32L5_RTC_BKR(i)); + bkregs[i] = getreg32(STM32_RTC_BKR(i)); } /* Enable write access to the backup domain (RTC registers, RTC * backup data registers and backup SRAM). */ - stm32l5_pwr_enablebkp(true); + stm32_pwr_enablebkp(true); /* We might be changing RTCSEL - to ensure such changes work, we must * reset the backup domain (having backed up the RTC_MAGIC token) */ - modifyreg32(STM32L5_RCC_BDCR, 0, RCC_BDCR_BDRST); - modifyreg32(STM32L5_RCC_BDCR, RCC_BDCR_BDRST, 0); + modifyreg32(STM32_RCC_BDCR, 0, RCC_BDCR_BDRST); + modifyreg32(STM32_RCC_BDCR, RCC_BDCR_BDRST, 0); /* Restore backup-registers, except RTC related. */ - for (i = 0; i < STM32L5_RTC_BKCOUNT; i++) + for (i = 0; i < STM32_RTC_BKCOUNT; i++) { - if (RTC_MAGIC_REG == STM32L5_RTC_BKR(i)) + if (RTC_MAGIC_REG == STM32_RTC_BKR(i)) { continue; } - putreg32(bkregs[i], STM32L5_RTC_BKR(i)); + putreg32(bkregs[i], STM32_RTC_BKR(i)); } - stm32l5_pwr_enablebkp(false); + stm32_pwr_enablebkp(false); } } #else @@ -148,9 +148,9 @@ static inline void rcc_resetbkp(void) * and enable peripheral clocking for all peripherals enabled in the NuttX * configuration file. * - * If CONFIG_ARCH_BOARD_STM32L5_CUSTOM_CLOCKCONFIG is defined, then + * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then * clocking will be enabled by an externally provided, board-specific - * function called stm32l5_board_clockconfig(). + * function called stm32_board_clockconfig(). * * Input Parameters * None @@ -160,7 +160,7 @@ static inline void rcc_resetbkp(void) * ****************************************************************************/ -void stm32l5_clockconfig(void) +void stm32_clockconfig(void) { #if 0 /* Make sure that we are starting in the reset state */ @@ -171,11 +171,11 @@ void stm32l5_clockconfig(void) rcc_resetbkp(); #endif -#if defined(CONFIG_ARCH_BOARD_STM32L5_CUSTOM_CLOCKCONFIG) +#if defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) /* Invoke Board Custom Clock Configuration */ - stm32l5_board_clockconfig(); + stm32_board_clockconfig(); #else @@ -183,13 +183,13 @@ void stm32l5_clockconfig(void) * board.h */ - stm32l5_stdclockconfig(); + stm32_stdclockconfig(); #endif /* Enable peripheral clocking */ - stm32l5_rcc_enableperipherals(); + stm32_rcc_enableperipherals(); } /**************************************************************************** @@ -202,12 +202,12 @@ void stm32l5_clockconfig(void) * re-enable/re-start the PLL * * This function performs a subset of the operations performed by - * stm32l5_clockconfig() + * stm32_clockconfig() * reset the currently enabled peripheral clocks. * - * If CONFIG_ARCH_BOARD_STM32L5_CUSTOM_CLOCKCONFIG is defined, then + * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then * clocking will be enabled by an externally provided, board-specific - * function called stm32l5_board_clockconfig(). + * function called stm32_board_clockconfig(). * * Input Parameters * None @@ -218,13 +218,13 @@ void stm32l5_clockconfig(void) ****************************************************************************/ #ifdef CONFIG_PM -void stm32l5_clockenable(void) +void stm32_clockenable(void) { -#if defined(CONFIG_ARCH_BOARD_STM32L5_CUSTOM_CLOCKCONFIG) +#if defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) /* Invoke Board Custom Clock Configuration */ - stm32l5_board_clockconfig(); + stm32_board_clockconfig(); #else @@ -232,7 +232,7 @@ void stm32l5_clockenable(void) * board.h */ - stm32l5_stdclockconfig(); + stm32_stdclockconfig(); #endif } diff --git a/arch/arm/src/stm32l5/stm32l5_rcc.h b/arch/arm/src/stm32l5/stm32l5_rcc.h index b756d9656d02e..efa70a2ef9275 100644 --- a/arch/arm/src/stm32l5/stm32l5_rcc.h +++ b/arch/arm/src/stm32l5/stm32l5_rcc.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32L5_STM32L5_RCC_H -#define __ARCH_ARM_SRC_STM32L5_STM32L5_RCC_H +#ifndef __ARCH_ARM_SRC_STM32L5_STM32_RCC_H +#define __ARCH_ARM_SRC_STM32L5_STM32_RCC_H /**************************************************************************** * Included Files @@ -32,7 +32,7 @@ #include "arm_internal.h" #include "chip.h" -#if defined(CONFIG_STM32L5_STM32L562XX) +#if defined(CONFIG_STM32_STM32L562XX) # include "hardware/stm32l562xx_rcc.h" #else # error "Unsupported STM32L5 chip" @@ -58,7 +58,7 @@ extern "C" ****************************************************************************/ /**************************************************************************** - * Name: stm32l5_mcoconfig + * Name: stm32_mcoconfig * * Description: * Selects the clock source to output on MC pin (PA8) for stm32l562xx @@ -75,16 +75,16 @@ extern "C" * ****************************************************************************/ -static inline void stm32l5_mcoconfig(uint32_t source) +static inline void stm32_mcoconfig(uint32_t source) { uint32_t regval; /* Set MCO source */ - regval = getreg32(STM32L5_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~(RCC_CFGR_MCOSEL_MASK); regval |= (source & RCC_CFGR_MCOSEL_MASK); - putreg32(regval, STM32L5_RCC_CFGR); + putreg32(regval, STM32_RCC_CFGR); } /**************************************************************************** @@ -92,7 +92,7 @@ static inline void stm32l5_mcoconfig(uint32_t source) ****************************************************************************/ /**************************************************************************** - * Name: stm32l5_clockconfig + * Name: stm32_clockconfig * * Description: * Called to establish the clock settings based on the values in board.h. @@ -100,9 +100,9 @@ static inline void stm32l5_mcoconfig(uint32_t source) * and enable peripheral clocking for all periperipherals enabled in the * NuttX configuration file. * - * If CONFIG_ARCH_BOARD_STM32L5_CUSTOM_CLOCKCONFIG is defined, then + * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then * clocking will be enabled by an externally provided, board-specific - * function called stm32l5_board_clockconfig(). + * function called stm32_board_clockconfig(). * * Input Parameters: * None @@ -112,10 +112,10 @@ static inline void stm32l5_mcoconfig(uint32_t source) * ****************************************************************************/ -void stm32l5_clockconfig(void); +void stm32_clockconfig(void); /**************************************************************************** - * Name: stm32l5_board_clockconfig + * Name: stm32_board_clockconfig * * Description: * Any STM32L5 board may replace the "standard" board clock configuration @@ -123,12 +123,12 @@ void stm32l5_clockconfig(void); * ****************************************************************************/ -#ifdef CONFIG_ARCH_BOARD_STM32L5_CUSTOM_CLOCKCONFIG -void stm32l5_board_clockconfig(void); +#ifdef CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG +void stm32_board_clockconfig(void); #endif /**************************************************************************** - * Name: stm32l5_stdclockconfig + * Name: stm32_stdclockconfig * * Description: * The standard logic to configure the clocks based on settings in board.h. @@ -138,12 +138,12 @@ void stm32l5_board_clockconfig(void); * ****************************************************************************/ -#ifndef CONFIG_ARCH_BOARD_STM32L5_CUSTOM_CLOCKCONFIG -void stm32l5_stdclockconfig(void); +#ifndef CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG +void stm32_stdclockconfig(void); #endif /**************************************************************************** - * Name: stm32l5_clockenable + * Name: stm32_clockenable * * Description: * Re-enable the clock and restore the clock settings based on settings in @@ -152,12 +152,12 @@ void stm32l5_stdclockconfig(void); * re-enable/re-start the PLL * * This function performs a subset of the operations performed by - * stm32l5_clockconfig(): It does not reset any devices, and it does not + * stm32_clockconfig(): It does not reset any devices, and it does not * reset the currently enabled peripheral clocks. * - * If CONFIG_ARCH_BOARD_STM32L5_CUSTOM_CLOCKCONFIG is defined, then + * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then * clocking will be enabled by an externally provided, board-specific - * function called stm32l5_board_clockconfig(). + * function called stm32_board_clockconfig(). * * Input Parameters: * None @@ -168,11 +168,11 @@ void stm32l5_stdclockconfig(void); ****************************************************************************/ #ifdef CONFIG_PM -void stm32l5_clockenable(void); +void stm32_clockenable(void); #endif /**************************************************************************** - * Name: stm32l5_rcc_enablelse + * Name: stm32_rcc_enablelse * * Description: * Enable the External Low-Speed (LSE) Oscillator. @@ -185,30 +185,30 @@ void stm32l5_clockenable(void); * ****************************************************************************/ -void stm32l5_rcc_enablelse(void); +void stm32_rcc_enablelse(void); /**************************************************************************** - * Name: stm32l5_rcc_enablelsi + * Name: stm32_rcc_enablelsi * * Description: * Enable the Internal Low-Speed (LSI) RC Oscillator. * ****************************************************************************/ -void stm32l5_rcc_enablelsi(void); +void stm32_rcc_enablelsi(void); /**************************************************************************** - * Name: stm32l5_rcc_disablelsi + * Name: stm32_rcc_disablelsi * * Description: * Disable the Internal Low-Speed (LSI) RC Oscillator. * ****************************************************************************/ -void stm32l5_rcc_disablelsi(void); +void stm32_rcc_disablelsi(void); /**************************************************************************** - * Name: stm32l5_rcc_enableperipherals + * Name: stm32_rcc_enableperipherals * * Description: * Enable all the chip peripherals according to configuration. This is @@ -217,11 +217,11 @@ void stm32l5_rcc_disablelsi(void); * ****************************************************************************/ -void stm32l5_rcc_enableperipherals(void); +void stm32_rcc_enableperipherals(void); #undef EXTERN #if defined(__cplusplus) } #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32L5_STM32L5_RCC_H */ +#endif /* __ARCH_ARM_SRC_STM32L5_STM32_RCC_H */ diff --git a/arch/arm/src/stm32l5/stm32l5_serial.c b/arch/arm/src/stm32l5/stm32l5_serial.c index 514c57477d5d4..9e994dfb0c312 100644 --- a/arch/arm/src/stm32l5/stm32l5_serial.c +++ b/arch/arm/src/stm32l5/stm32l5_serial.c @@ -82,14 +82,14 @@ */ # if defined(CONFIG_USART2_RXDMA) || defined(CONFIG_USART3_RXDMA) -# if !defined(CONFIG_STM32L5_DMA1) && !defined(CONFIG_STM32L5_DMAMUX) -# error STM32L5 USART2/3 receive DMA requires CONFIG_STM32L5_DMA1 +# if !defined(CONFIG_STM32_DMA1) && !defined(CONFIG_STM32_DMAMUX) +# error STM32L5 USART2/3 receive DMA requires CONFIG_STM32_DMA1 # endif # endif # if defined(CONFIG_UART4_RXDMA) || defined(CONFIG_UART5_RXDMA) -# if !defined(CONFIG_STM32L5_DMA2) && !defined(CONFIG_STM32L5_DMAMUX) -# error STM32L5 UART4/5 receive DMA requires CONFIG_STM32L5_DMA2 +# if !defined(CONFIG_STM32_DMA2) && !defined(CONFIG_STM32_DMAMUX) +# error STM32L5 UART4/5 receive DMA requires CONFIG_STM32_DMA2 # endif # endif @@ -116,7 +116,7 @@ /* UART2-5 have no alternate channels without DMAMUX */ -# ifndef CONFIG_STM32L5_HAVE_DMAMUX +# ifndef CONFIG_STM32_HAVE_DMAMUX # define DMAMAP_USART2_RX DMACHAN_USART2_RX # define DMAMAP_USART3_RX DMACHAN_USART3_RX # define DMAMAP_UART4_RX DMACHAN_UART4_RX @@ -149,11 +149,11 @@ * can be individually invalidated. */ -# if !defined(CONFIG_STM32L5_SERIAL_RXDMA_BUFFER_SIZE) || \ - CONFIG_STM32L5_SERIAL_RXDMA_BUFFER_SIZE == 0 +# if !defined(CONFIG_STM32_SERIAL_RXDMA_BUFFER_SIZE) || \ + CONFIG_STM32_SERIAL_RXDMA_BUFFER_SIZE == 0 # define RXDMA_BUFFER_SIZE 32 # else -# define RXDMA_BUFFER_SIZE ((CONFIG_STM32L5_SERIAL_RXDMA_BUFFER_SIZE + 31) & ~31) +# define RXDMA_BUFFER_SIZE ((CONFIG_STM32_SERIAL_RXDMA_BUFFER_SIZE + 31) & ~31) # endif /* DMA priority */ @@ -185,8 +185,8 @@ /* Power management definitions */ -#if defined(CONFIG_PM) && !defined(CONFIG_STM32L5_PM_SERIAL_ACTIVITY) -# define CONFIG_STM32L5_PM_SERIAL_ACTIVITY 10 +#if defined(CONFIG_PM) && !defined(CONFIG_STM32_PM_SERIAL_ACTIVITY) +# define CONFIG_STM32_PM_SERIAL_ACTIVITY 10 #endif /* Keep track if a Break was set @@ -200,7 +200,7 @@ * See stm32l5serial_restoreusartint where the masking is done. */ -#ifdef CONFIG_STM32L5_SERIALBRK_BSDCOMPAT +#ifdef CONFIG_STM32_SERIALBRK_BSDCOMPAT # define USART_CR1_IE_BREAK_INPROGRESS_SHFTS 15 # define USART_CR1_IE_BREAK_INPROGRESS (1 << USART_CR1_IE_BREAK_INPROGRESS_SHFTS) #endif @@ -212,7 +212,7 @@ * Private Types ****************************************************************************/ -struct stm32l5_serial_s +struct stm32_serial_s { struct uart_dev_s dev; /* Generic UART device */ uint16_t ie; /* Saved interrupt mask bits value */ @@ -327,9 +327,9 @@ static int stm32l5serial_dmasetup(struct uart_dev_s *dev); static void stm32l5serial_dmashutdown(struct uart_dev_s *dev); static int stm32l5serial_dmareceive(struct uart_dev_s *dev, unsigned int *status); -static void stm32l5serial_dmareenable(struct stm32l5_serial_s *priv); +static void stm32l5serial_dmareenable(struct stm32_serial_s *priv); #ifdef CONFIG_SERIAL_IFLOWCONTROL -static bool stm32l5serial_dmaiflowrestart(struct stm32l5_serial_s *priv); +static bool stm32l5serial_dmaiflowrestart(struct stm32_serial_s *priv); #endif static void stm32l5serial_dmarxint(struct uart_dev_s *dev, bool enable); static bool stm32l5serial_dmarxavailable(struct uart_dev_s *dev); @@ -395,7 +395,7 @@ static const struct uart_ops_s g_uart_dma_ops = /* I/O buffers */ -#ifdef CONFIG_STM32L5_LPUART1_SERIALDRIVER +#ifdef CONFIG_STM32_LPUART1_SERIALDRIVER static char g_lpuart1rxbuffer[CONFIG_LPUART1_RXBUFSIZE]; static char g_lpuart1txbuffer[CONFIG_LPUART1_TXBUFSIZE]; # ifdef CONFIG_LPUART1_RXDMA @@ -403,7 +403,7 @@ static char g_lpuart1rxfifo[RXDMA_BUFFER_SIZE]; # endif #endif -#ifdef CONFIG_STM32L5_USART1_SERIALDRIVER +#ifdef CONFIG_STM32_USART1_SERIALDRIVER static char g_usart1rxbuffer[CONFIG_USART1_RXBUFSIZE]; static char g_usart1txbuffer[CONFIG_USART1_TXBUFSIZE]; # ifdef CONFIG_USART1_RXDMA @@ -411,7 +411,7 @@ static char g_usart1rxfifo[RXDMA_BUFFER_SIZE]; # endif #endif -#ifdef CONFIG_STM32L5_USART2_SERIALDRIVER +#ifdef CONFIG_STM32_USART2_SERIALDRIVER static char g_usart2rxbuffer[CONFIG_USART2_RXBUFSIZE]; static char g_usart2txbuffer[CONFIG_USART2_TXBUFSIZE]; # ifdef CONFIG_USART2_RXDMA @@ -419,7 +419,7 @@ static char g_usart2rxfifo[RXDMA_BUFFER_SIZE]; # endif #endif -#ifdef CONFIG_STM32L5_USART3_SERIALDRIVER +#ifdef CONFIG_STM32_USART3_SERIALDRIVER static char g_usart3rxbuffer[CONFIG_USART3_RXBUFSIZE]; static char g_usart3txbuffer[CONFIG_USART3_TXBUFSIZE]; # ifdef CONFIG_USART3_RXDMA @@ -427,7 +427,7 @@ static char g_usart3rxfifo[RXDMA_BUFFER_SIZE]; # endif #endif -#ifdef CONFIG_STM32L5_UART4_SERIALDRIVER +#ifdef CONFIG_STM32_UART4_SERIALDRIVER static char g_uart4rxbuffer[CONFIG_UART4_RXBUFSIZE]; static char g_uart4txbuffer[CONFIG_UART4_TXBUFSIZE]; # ifdef CONFIG_UART4_RXDMA @@ -435,7 +435,7 @@ static char g_uart4rxfifo[RXDMA_BUFFER_SIZE]; # endif #endif -#ifdef CONFIG_STM32L5_UART5_SERIALDRIVER +#ifdef CONFIG_STM32_UART5_SERIALDRIVER static char g_uart5rxbuffer[CONFIG_UART5_RXBUFSIZE]; static char g_uart5txbuffer[CONFIG_UART5_TXBUFSIZE]; # ifdef CONFIG_UART5_RXDMA @@ -445,8 +445,8 @@ static char g_uart5rxfifo[RXDMA_BUFFER_SIZE]; /* This describes the state of the STM32 USART1 ports. */ -#ifdef CONFIG_STM32L5_LPUART1_SERIALDRIVER -static struct stm32l5_serial_s g_lpuart1priv = +#ifdef CONFIG_STM32_LPUART1_SERIALDRIVER +static struct stm32_serial_s g_lpuart1priv = { .dev = { @@ -471,13 +471,13 @@ static struct stm32l5_serial_s g_lpuart1priv = .priv = &g_lpuart1priv, }, - .irq = STM32L5_IRQ_LPUART1, + .irq = STM32_IRQ_LPUART1, .parity = CONFIG_LPUART1_PARITY, .bits = CONFIG_LPUART1_BITS, .stopbits2 = CONFIG_LPUART1_2STOP, .baud = CONFIG_LPUART1_BAUD, - .apbclock = STM32L5_PCLK1_FREQUENCY, - .usartbase = STM32L5_LPUART1_BASE, + .apbclock = STM32_PCLK1_FREQUENCY, + .usartbase = STM32_LPUART1_BASE, .tx_gpio = GPIO_LPUART1_TX, .rx_gpio = GPIO_LPUART1_RX, # if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_LPUART1_OFLOWCONTROL) @@ -505,8 +505,8 @@ static struct stm32l5_serial_s g_lpuart1priv = }; #endif -#ifdef CONFIG_STM32L5_USART1_SERIALDRIVER -static struct stm32l5_serial_s g_usart1priv = +#ifdef CONFIG_STM32_USART1_SERIALDRIVER +static struct stm32_serial_s g_usart1priv = { .dev = { @@ -531,13 +531,13 @@ static struct stm32l5_serial_s g_usart1priv = .priv = &g_usart1priv, }, - .irq = STM32L5_IRQ_USART1, + .irq = STM32_IRQ_USART1, .parity = CONFIG_USART1_PARITY, .bits = CONFIG_USART1_BITS, .stopbits2 = CONFIG_USART1_2STOP, .baud = CONFIG_USART1_BAUD, - .apbclock = STM32L5_PCLK2_FREQUENCY, - .usartbase = STM32L5_USART1_BASE, + .apbclock = STM32_PCLK2_FREQUENCY, + .usartbase = STM32_USART1_BASE, .tx_gpio = GPIO_USART1_TX, .rx_gpio = GPIO_USART1_RX, # if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_USART1_OFLOWCONTROL) @@ -567,8 +567,8 @@ static struct stm32l5_serial_s g_usart1priv = /* This describes the state of the STM32 USART2 port. */ -#ifdef CONFIG_STM32L5_USART2_SERIALDRIVER -static struct stm32l5_serial_s g_usart2priv = +#ifdef CONFIG_STM32_USART2_SERIALDRIVER +static struct stm32_serial_s g_usart2priv = { .dev = { @@ -593,13 +593,13 @@ static struct stm32l5_serial_s g_usart2priv = .priv = &g_usart2priv, }, - .irq = STM32L5_IRQ_USART2, + .irq = STM32_IRQ_USART2, .parity = CONFIG_USART2_PARITY, .bits = CONFIG_USART2_BITS, .stopbits2 = CONFIG_USART2_2STOP, .baud = CONFIG_USART2_BAUD, - .apbclock = STM32L5_PCLK1_FREQUENCY, - .usartbase = STM32L5_USART2_BASE, + .apbclock = STM32_PCLK1_FREQUENCY, + .usartbase = STM32_USART2_BASE, .tx_gpio = GPIO_USART2_TX, .rx_gpio = GPIO_USART2_RX, # if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_USART2_OFLOWCONTROL) @@ -629,8 +629,8 @@ static struct stm32l5_serial_s g_usart2priv = /* This describes the state of the STM32 USART3 port. */ -#ifdef CONFIG_STM32L5_USART3_SERIALDRIVER -static struct stm32l5_serial_s g_usart3priv = +#ifdef CONFIG_STM32_USART3_SERIALDRIVER +static struct stm32_serial_s g_usart3priv = { .dev = { @@ -655,13 +655,13 @@ static struct stm32l5_serial_s g_usart3priv = .priv = &g_usart3priv, }, - .irq = STM32L5_IRQ_USART3, + .irq = STM32_IRQ_USART3, .parity = CONFIG_USART3_PARITY, .bits = CONFIG_USART3_BITS, .stopbits2 = CONFIG_USART3_2STOP, .baud = CONFIG_USART3_BAUD, - .apbclock = STM32L5_PCLK1_FREQUENCY, - .usartbase = STM32L5_USART3_BASE, + .apbclock = STM32_PCLK1_FREQUENCY, + .usartbase = STM32_USART3_BASE, .tx_gpio = GPIO_USART3_TX, .rx_gpio = GPIO_USART3_RX, # if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_USART3_OFLOWCONTROL) @@ -691,8 +691,8 @@ static struct stm32l5_serial_s g_usart3priv = /* This describes the state of the STM32 UART4 port. */ -#ifdef CONFIG_STM32L5_UART4_SERIALDRIVER -static struct stm32l5_serial_s g_uart4priv = +#ifdef CONFIG_STM32_UART4_SERIALDRIVER +static struct stm32_serial_s g_uart4priv = { .dev = { @@ -717,7 +717,7 @@ static struct stm32l5_serial_s g_uart4priv = .priv = &g_uart4priv, }, - .irq = STM32L5_IRQ_UART4, + .irq = STM32_IRQ_UART4, .parity = CONFIG_UART4_PARITY, .bits = CONFIG_UART4_BITS, .stopbits2 = CONFIG_UART4_2STOP, @@ -730,8 +730,8 @@ static struct stm32l5_serial_s g_uart4priv = .rts_gpio = GPIO_UART4_RTS, # endif .baud = CONFIG_UART4_BAUD, - .apbclock = STM32L5_PCLK1_FREQUENCY, - .usartbase = STM32L5_UART4_BASE, + .apbclock = STM32_PCLK1_FREQUENCY, + .usartbase = STM32_UART4_BASE, .tx_gpio = GPIO_UART4_TX, .rx_gpio = GPIO_UART4_RX, # ifdef CONFIG_UART4_RXDMA @@ -753,8 +753,8 @@ static struct stm32l5_serial_s g_uart4priv = /* This describes the state of the STM32 UART5 port. */ -#ifdef CONFIG_STM32L5_UART5_SERIALDRIVER -static struct stm32l5_serial_s g_uart5priv = +#ifdef CONFIG_STM32_UART5_SERIALDRIVER +static struct stm32_serial_s g_uart5priv = { .dev = { @@ -779,7 +779,7 @@ static struct stm32l5_serial_s g_uart5priv = .priv = &g_uart5priv, }, - .irq = STM32L5_IRQ_UART5, + .irq = STM32_IRQ_UART5, .parity = CONFIG_UART5_PARITY, .bits = CONFIG_UART5_BITS, .stopbits2 = CONFIG_UART5_2STOP, @@ -792,8 +792,8 @@ static struct stm32l5_serial_s g_uart5priv = .rts_gpio = GPIO_UART5_RTS, # endif .baud = CONFIG_UART5_BAUD, - .apbclock = STM32L5_PCLK1_FREQUENCY, - .usartbase = STM32L5_UART5_BASE, + .apbclock = STM32_PCLK1_FREQUENCY, + .usartbase = STM32_UART5_BASE, .tx_gpio = GPIO_UART5_TX, .rx_gpio = GPIO_UART5_RX, # ifdef CONFIG_UART5_RXDMA @@ -815,25 +815,25 @@ static struct stm32l5_serial_s g_uart5priv = /* This table lets us iterate over the configured USARTs */ -static struct stm32l5_serial_s * const - g_uart_devs[STM32L5_NLPUART + STM32L5_NUSART + STM32L5_NUART] = +static struct stm32_serial_s * const + g_uart_devs[STM32_NLPUART + STM32_NUSART + STM32_NUART] = { -#ifdef CONFIG_STM32L5_LPUART1_SERIALDRIVER +#ifdef CONFIG_STM32_LPUART1_SERIALDRIVER [0] = &g_lpuart1priv, #endif -#ifdef CONFIG_STM32L5_USART1_SERIALDRIVER +#ifdef CONFIG_STM32_USART1_SERIALDRIVER [1] = &g_usart1priv, #endif -#ifdef CONFIG_STM32L5_USART2_SERIALDRIVER +#ifdef CONFIG_STM32_USART2_SERIALDRIVER [2] = &g_usart2priv, #endif -#ifdef CONFIG_STM32L5_USART3_SERIALDRIVER +#ifdef CONFIG_STM32_USART3_SERIALDRIVER [3] = &g_usart3priv, #endif -#ifdef CONFIG_STM32L5_UART4_SERIALDRIVER +#ifdef CONFIG_STM32_UART4_SERIALDRIVER [4] = &g_uart4priv, #endif -#ifdef CONFIG_STM32L5_UART5_SERIALDRIVER +#ifdef CONFIG_STM32_UART5_SERIALDRIVER [5] = &g_uart5priv, #endif }; @@ -862,7 +862,7 @@ static struct serialpm_s g_serialpm = ****************************************************************************/ static inline -uint32_t stm32l5serial_getreg(struct stm32l5_serial_s *priv, int offset) +uint32_t stm32l5serial_getreg(struct stm32_serial_s *priv, int offset) { return getreg32(priv->usartbase + offset); } @@ -872,7 +872,7 @@ uint32_t stm32l5serial_getreg(struct stm32l5_serial_s *priv, int offset) ****************************************************************************/ static inline -void stm32l5serial_putreg(struct stm32l5_serial_s *priv, +void stm32l5serial_putreg(struct stm32_serial_s *priv, int offset, uint32_t value) { putreg32(value, priv->usartbase + offset); @@ -883,7 +883,7 @@ void stm32l5serial_putreg(struct stm32l5_serial_s *priv, ****************************************************************************/ static inline -void stm32l5serial_setusartint(struct stm32l5_serial_s *priv, +void stm32l5serial_setusartint(struct stm32_serial_s *priv, uint16_t ie) { uint32_t cr; @@ -896,22 +896,22 @@ void stm32l5serial_setusartint(struct stm32l5_serial_s *priv, * above) */ - cr = stm32l5serial_getreg(priv, STM32L5_USART_CR1_OFFSET); + cr = stm32l5serial_getreg(priv, STM32_USART_CR1_OFFSET); cr &= ~(USART_CR1_USED_INTS); cr |= (ie & (USART_CR1_USED_INTS)); - stm32l5serial_putreg(priv, STM32L5_USART_CR1_OFFSET, cr); + stm32l5serial_putreg(priv, STM32_USART_CR1_OFFSET, cr); - cr = stm32l5serial_getreg(priv, STM32L5_USART_CR3_OFFSET); + cr = stm32l5serial_getreg(priv, STM32_USART_CR3_OFFSET); cr &= ~USART_CR3_EIE; cr |= (ie & USART_CR3_EIE); - stm32l5serial_putreg(priv, STM32L5_USART_CR3_OFFSET, cr); + stm32l5serial_putreg(priv, STM32_USART_CR3_OFFSET, cr); } /**************************************************************************** * Name: up_restoreusartint ****************************************************************************/ -static void stm32l5serial_restoreusartint(struct stm32l5_serial_s *priv, +static void stm32l5serial_restoreusartint(struct stm32_serial_s *priv, uint16_t ie) { irqstate_t flags; @@ -927,7 +927,7 @@ static void stm32l5serial_restoreusartint(struct stm32l5_serial_s *priv, * Name: stm32l5serial_disableusartint ****************************************************************************/ -static void stm32l5serial_disableusartint(struct stm32l5_serial_s *priv, +static void stm32l5serial_disableusartint(struct stm32_serial_s *priv, uint16_t *ie) { irqstate_t flags; @@ -959,8 +959,8 @@ static void stm32l5serial_disableusartint(struct stm32l5_serial_s *priv, * USART_CR3_CTSIE USART_ISR_CTS CTS flag (not used) */ - cr1 = stm32l5serial_getreg(priv, STM32L5_USART_CR1_OFFSET); - cr3 = stm32l5serial_getreg(priv, STM32L5_USART_CR3_OFFSET); + cr1 = stm32l5serial_getreg(priv, STM32_USART_CR1_OFFSET); + cr3 = stm32l5serial_getreg(priv, STM32_USART_CR3_OFFSET); /* Return the current interrupt mask value for the used interrupts. * Notice that this depends on the fact that none of the used interrupt @@ -988,11 +988,11 @@ static void stm32l5serial_disableusartint(struct stm32l5_serial_s *priv, ****************************************************************************/ #ifdef SERIAL_HAVE_DMA -static int stm32l5serial_dmanextrx(struct stm32l5_serial_s *priv) +static int stm32l5serial_dmanextrx(struct stm32_serial_s *priv) { size_t dmaresidual; - dmaresidual = stm32l5_dmaresidual(priv->rxdma); + dmaresidual = stm32_dmaresidual(priv->rxdma); return (RXDMA_BUFFER_SIZE - (int)dmaresidual); } @@ -1009,8 +1009,8 @@ static int stm32l5serial_dmanextrx(struct stm32l5_serial_s *priv) #ifndef CONFIG_SUPPRESS_UART_CONFIG static void stm32l5serial_setformat(struct uart_dev_s *dev) { - struct stm32l5_serial_s *priv = - (struct stm32l5_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; uint32_t regval; /* This first implementation is for U[S]ARTs that support oversampling @@ -1021,21 +1021,21 @@ static void stm32l5serial_setformat(struct uart_dev_s *dev) uint32_t cr1; uint32_t brr; -#ifdef CONFIG_STM32L5_LPUART1_SERIALDRIVER - if (priv->usartbase == STM32L5_LPUART1_BASE) +#ifdef CONFIG_STM32_LPUART1_SERIALDRIVER + if (priv->usartbase == STM32_LPUART1_BASE) { /* LPUART BRR = 256 * fCK / baud */ brr = (((uint64_t)priv->apbclock << 8) + (priv->baud >> 1)) / priv->baud; - stm32l5serial_putreg(priv, STM32L5_USART_BRR_OFFSET, brr); + stm32l5serial_putreg(priv, STM32_USART_BRR_OFFSET, brr); } else #endif { usartdiv8 = ((priv->apbclock << 1) + (priv->baud >> 1)) / priv->baud; - cr1 = stm32l5serial_getreg(priv, STM32L5_USART_CR1_OFFSET); + cr1 = stm32l5serial_getreg(priv, STM32_USART_CR1_OFFSET); if (usartdiv8 > 2000) { brr = (usartdiv8 + 1) >> 1; @@ -1048,13 +1048,13 @@ static void stm32l5serial_setformat(struct uart_dev_s *dev) cr1 |= USART_CR1_OVER8; } - stm32l5serial_putreg(priv, STM32L5_USART_CR1_OFFSET, cr1); - stm32l5serial_putreg(priv, STM32L5_USART_BRR_OFFSET, brr); + stm32l5serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1); + stm32l5serial_putreg(priv, STM32_USART_BRR_OFFSET, brr); } /* Configure parity mode */ - regval = stm32l5serial_getreg(priv, STM32L5_USART_CR1_OFFSET); + regval = stm32l5serial_getreg(priv, STM32_USART_CR1_OFFSET); regval &= ~(USART_CR1_PCE | USART_CR1_PS | USART_CR1_M0 | USART_CR1_M1); if (priv->parity == 1) /* Odd parity */ @@ -1092,11 +1092,11 @@ static void stm32l5serial_setformat(struct uart_dev_s *dev) * 1 start, 8 data (no parity), n stop. */ - stm32l5serial_putreg(priv, STM32L5_USART_CR1_OFFSET, regval); + stm32l5serial_putreg(priv, STM32_USART_CR1_OFFSET, regval); /* Configure STOP bits */ - regval = stm32l5serial_getreg(priv, STM32L5_USART_CR2_OFFSET); + regval = stm32l5serial_getreg(priv, STM32_USART_CR2_OFFSET); regval &= ~(USART_CR2_STOP_MASK); if (priv->stopbits2) @@ -1104,14 +1104,14 @@ static void stm32l5serial_setformat(struct uart_dev_s *dev) regval |= USART_CR2_STOP2; } - stm32l5serial_putreg(priv, STM32L5_USART_CR2_OFFSET, regval); + stm32l5serial_putreg(priv, STM32_USART_CR2_OFFSET, regval); /* Configure hardware flow control */ - regval = stm32l5serial_getreg(priv, STM32L5_USART_CR3_OFFSET); + regval = stm32l5serial_getreg(priv, STM32_USART_CR3_OFFSET); regval &= ~(USART_CR3_CTSE | USART_CR3_RTSE); -#if defined(CONFIG_SERIAL_IFLOWCONTROL) && !defined(CONFIG_STM32L5_FLOWCONTROL_BROKEN) +#if defined(CONFIG_SERIAL_IFLOWCONTROL) && !defined(CONFIG_STM32_FLOWCONTROL_BROKEN) if (priv->iflow && (priv->rts_gpio != 0)) { regval |= USART_CR3_RTSE; @@ -1125,7 +1125,7 @@ static void stm32l5serial_setformat(struct uart_dev_s *dev) } #endif - stm32l5serial_putreg(priv, STM32L5_USART_CR3_OFFSET, regval); + stm32l5serial_putreg(priv, STM32_USART_CR3_OFFSET, regval); } #endif /* CONFIG_SUPPRESS_UART_CONFIG */ @@ -1140,7 +1140,7 @@ static void stm32l5serial_setformat(struct uart_dev_s *dev) #ifdef CONFIG_PM static void stm32l5serial_setsuspend(struct uart_dev_s *dev, bool suspend) { - struct stm32l5_serial_s *priv = (struct stm32l5_serial_s *)dev->priv; + struct stm32_serial_s *priv = (struct stm32_serial_s *)dev->priv; #ifdef SERIAL_HAVE_DMA bool dmarestored = false; #endif @@ -1159,7 +1159,7 @@ static void stm32l5serial_setsuspend(struct uart_dev_s *dev, bool suspend) { /* Force RTS high to prevent further Rx. */ - stm32l5_configgpio((priv->rts_gpio & ~GPIO_MODE_MASK) + stm32_configgpio((priv->rts_gpio & ~GPIO_MODE_MASK) | (GPIO_OUTPUT | GPIO_OUTPUT_SET)); } #endif @@ -1170,7 +1170,7 @@ static void stm32l5serial_setsuspend(struct uart_dev_s *dev, bool suspend) /* Wait last Tx to complete. */ - while ((stm32l5serial_getreg(priv, STM32L5_USART_ISR_OFFSET) & + while ((stm32l5serial_getreg(priv, STM32_USART_ISR_OFFSET) & USART_ISR_TC) == 0); #ifdef SERIAL_HAVE_DMA @@ -1188,7 +1188,7 @@ static void stm32l5serial_setsuspend(struct uart_dev_s *dev, bool suspend) { /* Suspend Rx DMA. */ - stm32l5_dmastop(priv->rxdma); + stm32_dmastop(priv->rxdma); priv->rxdmasusp = true; } } @@ -1229,7 +1229,7 @@ static void stm32l5serial_setsuspend(struct uart_dev_s *dev, bool suspend) { /* Restore peripheral RTS control. */ - stm32l5_configgpio(priv->rts_gpio); + stm32_configgpio(priv->rts_gpio); } #endif } @@ -1276,9 +1276,9 @@ static void stm32l5serial_pm_setsuspend(bool suspend) g_serialpm.serial_suspended = suspend; - for (n = 0; n < STM32L5_NLPUART + STM32L5_NUSART + STM32L5_NUART; n++) + for (n = 0; n < STM32_NLPUART + STM32_NUSART + STM32_NUART; n++) { - struct stm32l5_serial_s *priv = g_uart_devs[n]; + struct stm32_serial_s *priv = g_uart_devs[n]; if (!priv || !priv->initialized) { @@ -1304,8 +1304,8 @@ static void stm32l5serial_pm_setsuspend(bool suspend) static void stm32l5serial_setapbclock(struct uart_dev_s *dev, bool on) { - struct stm32l5_serial_s *priv = - (struct stm32l5_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; uint32_t rcc_en; uint32_t regaddr; @@ -1315,40 +1315,40 @@ static void stm32l5serial_setapbclock(struct uart_dev_s *dev, bool on) { default: return; -#ifdef CONFIG_STM32L5_LPUART1_SERIALDRIVER - case STM32L5_LPUART1_BASE: +#ifdef CONFIG_STM32_LPUART1_SERIALDRIVER + case STM32_LPUART1_BASE: rcc_en = RCC_APB1ENR2_LPUART1EN; - regaddr = STM32L5_RCC_APB1ENR2; + regaddr = STM32_RCC_APB1ENR2; break; #endif -#ifdef CONFIG_STM32L5_USART1_SERIALDRIVER - case STM32L5_USART1_BASE: +#ifdef CONFIG_STM32_USART1_SERIALDRIVER + case STM32_USART1_BASE: rcc_en = RCC_APB2ENR_USART1EN; - regaddr = STM32L5_RCC_APB2ENR; + regaddr = STM32_RCC_APB2ENR; break; #endif -#ifdef CONFIG_STM32L5_USART2_SERIALDRIVER - case STM32L5_USART2_BASE: +#ifdef CONFIG_STM32_USART2_SERIALDRIVER + case STM32_USART2_BASE: rcc_en = RCC_APB1ENR1_USART2EN; - regaddr = STM32L5_RCC_APB1ENR1; + regaddr = STM32_RCC_APB1ENR1; break; #endif -#ifdef CONFIG_STM32L5_USART3_SERIALDRIVER - case STM32L5_USART3_BASE: +#ifdef CONFIG_STM32_USART3_SERIALDRIVER + case STM32_USART3_BASE: rcc_en = RCC_APB1ENR1_USART3EN; - regaddr = STM32L5_RCC_APB1ENR1; + regaddr = STM32_RCC_APB1ENR1; break; #endif -#ifdef CONFIG_STM32L5_UART4_SERIALDRIVER - case STM32L5_UART4_BASE: +#ifdef CONFIG_STM32_UART4_SERIALDRIVER + case STM32_UART4_BASE: rcc_en = RCC_APB1ENR1_UART4EN; - regaddr = STM32L5_RCC_APB1ENR1; + regaddr = STM32_RCC_APB1ENR1; break; #endif -#ifdef CONFIG_STM32L5_UART5_SERIALDRIVER - case STM32L5_UART5_BASE: +#ifdef CONFIG_STM32_UART5_SERIALDRIVER + case STM32_UART5_BASE: rcc_en = RCC_APB1ENR1_UART5EN; - regaddr = STM32L5_RCC_APB1ENR1; + regaddr = STM32_RCC_APB1ENR1; break; #endif } @@ -1376,14 +1376,14 @@ static void stm32l5serial_setapbclock(struct uart_dev_s *dev, bool on) static int stm32l5serial_setup(struct uart_dev_s *dev) { - struct stm32l5_serial_s *priv = - (struct stm32l5_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; #ifndef CONFIG_SUPPRESS_UART_CONFIG uint32_t regval; /* Note: The logic here depends on the fact that that the USART module - * was enabled in stm32l5_lowsetup(). + * was enabled in stm32_lowsetup(). */ /* Enable USART APB1/2 clock */ @@ -1394,18 +1394,18 @@ static int stm32l5serial_setup(struct uart_dev_s *dev) if (priv->tx_gpio != 0) { - stm32l5_configgpio(priv->tx_gpio); + stm32_configgpio(priv->tx_gpio); } if (priv->rx_gpio != 0) { - stm32l5_configgpio(priv->rx_gpio); + stm32_configgpio(priv->rx_gpio); } #ifdef CONFIG_SERIAL_OFLOWCONTROL if (priv->cts_gpio != 0) { - stm32l5_configgpio(priv->cts_gpio); + stm32_configgpio(priv->cts_gpio); } #endif @@ -1414,20 +1414,20 @@ static int stm32l5serial_setup(struct uart_dev_s *dev) { uint32_t config = priv->rts_gpio; -#ifdef CONFIG_STM32L5_FLOWCONTROL_BROKEN +#ifdef CONFIG_STM32_FLOWCONTROL_BROKEN /* Instead of letting hw manage this pin, we will bitbang */ config = (config & ~GPIO_MODE_MASK) | GPIO_OUTPUT; #endif - stm32l5_configgpio(config); + stm32_configgpio(config); } #endif #ifdef HAVE_RS485 if (priv->rs485_dir_gpio != 0) { - stm32l5_configgpio(priv->rs485_dir_gpio); - stm32l5_gpiowrite(priv->rs485_dir_gpio, !priv->rs485_dir_polarity); + stm32_configgpio(priv->rs485_dir_gpio); + stm32_gpiowrite(priv->rs485_dir_gpio, !priv->rs485_dir_polarity); } #endif @@ -1435,7 +1435,7 @@ static int stm32l5serial_setup(struct uart_dev_s *dev) /* Clear STOP, CLKEN, CPOL, CPHA, LBCL, and interrupt enable bits */ - regval = stm32l5serial_getreg(priv, STM32L5_USART_CR2_OFFSET); + regval = stm32l5serial_getreg(priv, STM32_USART_CR2_OFFSET); regval &= ~(USART_CR2_STOP_MASK | USART_CR2_CLKEN | USART_CR2_CPOL | USART_CR2_CPHA | USART_CR2_LBCL | USART_CR2_LBDIE); @@ -1446,26 +1446,26 @@ static int stm32l5serial_setup(struct uart_dev_s *dev) regval |= USART_CR2_STOP2; } - stm32l5serial_putreg(priv, STM32L5_USART_CR2_OFFSET, regval); + stm32l5serial_putreg(priv, STM32_USART_CR2_OFFSET, regval); /* Configure CR1 */ /* Clear TE, REm and all interrupt enable bits */ - regval = stm32l5serial_getreg(priv, STM32L5_USART_CR1_OFFSET); + regval = stm32l5serial_getreg(priv, STM32_USART_CR1_OFFSET); regval &= ~(USART_CR1_TE | USART_CR1_RE | USART_CR1_ALLINTS); - stm32l5serial_putreg(priv, STM32L5_USART_CR1_OFFSET, regval); + stm32l5serial_putreg(priv, STM32_USART_CR1_OFFSET, regval); /* Configure CR3 */ /* Clear CTSE, RTSE, and all interrupt enable bits */ - regval = stm32l5serial_getreg(priv, STM32L5_USART_CR3_OFFSET); + regval = stm32l5serial_getreg(priv, STM32_USART_CR3_OFFSET); regval &= ~(USART_CR3_CTSIE | USART_CR3_CTSE | USART_CR3_RTSE | USART_CR3_EIE); - stm32l5serial_putreg(priv, STM32L5_USART_CR3_OFFSET, regval); + stm32l5serial_putreg(priv, STM32_USART_CR3_OFFSET, regval); /* Configure the USART line format and speed. */ @@ -1473,9 +1473,9 @@ static int stm32l5serial_setup(struct uart_dev_s *dev) /* Enable Rx, Tx, and the USART */ - regval = stm32l5serial_getreg(priv, STM32L5_USART_CR1_OFFSET); + regval = stm32l5serial_getreg(priv, STM32_USART_CR1_OFFSET); regval |= (USART_CR1_UE | USART_CR1_TE | USART_CR1_RE); - stm32l5serial_putreg(priv, STM32L5_USART_CR1_OFFSET, regval); + stm32l5serial_putreg(priv, STM32_USART_CR1_OFFSET, regval); #endif /* CONFIG_SUPPRESS_UART_CONFIG */ @@ -1502,8 +1502,8 @@ static int stm32l5serial_setup(struct uart_dev_s *dev) #ifdef SERIAL_HAVE_DMA static int stm32l5serial_dmasetup(struct uart_dev_s *dev) { - struct stm32l5_serial_s *priv = - (struct stm32l5_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; int result; uint32_t regval; @@ -1520,15 +1520,15 @@ static int stm32l5serial_dmasetup(struct uart_dev_s *dev) /* Acquire the DMA channel. This should always succeed. */ - priv->rxdma = stm32l5_dmachannel(priv->rxdma_channel); + priv->rxdma = stm32_dmachannel(priv->rxdma_channel); #ifdef CONFIG_SERIAL_IFLOWCONTROL if (priv->iflow) { /* Configure for non-circular DMA reception into the RX FIFO */ - stm32l5_dmasetup(priv->rxdma, - priv->usartbase + STM32L5_USART_RDR_OFFSET, + stm32_dmasetup(priv->rxdma, + priv->usartbase + STM32_USART_RDR_OFFSET, (uint32_t)priv->rxfifo, RXDMA_BUFFER_SIZE, SERIAL_DMA_IFLOW_CONTROL_WORD); @@ -1538,8 +1538,8 @@ static int stm32l5serial_dmasetup(struct uart_dev_s *dev) { /* Configure for circular DMA reception into the RX FIFO */ - stm32l5_dmasetup(priv->rxdma, - priv->usartbase + STM32L5_USART_RDR_OFFSET, + stm32_dmasetup(priv->rxdma, + priv->usartbase + STM32_USART_RDR_OFFSET, (uint32_t)priv->rxfifo, RXDMA_BUFFER_SIZE, SERIAL_DMA_CONTROL_WORD); @@ -1553,9 +1553,9 @@ static int stm32l5serial_dmasetup(struct uart_dev_s *dev) /* Enable receive DMA for the UART */ - regval = stm32l5serial_getreg(priv, STM32L5_USART_CR3_OFFSET); + regval = stm32l5serial_getreg(priv, STM32_USART_CR3_OFFSET); regval |= USART_CR3_DMAR; - stm32l5serial_putreg(priv, STM32L5_USART_CR3_OFFSET, regval); + stm32l5serial_putreg(priv, STM32_USART_CR3_OFFSET, regval); #ifdef CONFIG_SERIAL_IFLOWCONTROL if (priv->iflow) @@ -1565,7 +1565,7 @@ static int stm32l5serial_dmasetup(struct uart_dev_s *dev) * in and DMA transfer is stopped. */ - stm32l5_dmastart(priv->rxdma, stm32l5serial_dmarxcallback, + stm32_dmastart(priv->rxdma, stm32l5serial_dmarxcallback, (void *)priv, false); } else @@ -1576,7 +1576,7 @@ static int stm32l5serial_dmasetup(struct uart_dev_s *dev) * worth of time to claim bytes before they are overwritten. */ - stm32l5_dmastart(priv->rxdma, stm32l5serial_dmarxcallback, + stm32_dmastart(priv->rxdma, stm32l5serial_dmarxcallback, (void *)priv, true); } @@ -1595,8 +1595,8 @@ static int stm32l5serial_dmasetup(struct uart_dev_s *dev) static void stm32l5serial_shutdown(struct uart_dev_s *dev) { - struct stm32l5_serial_s *priv = - (struct stm32l5_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; uint32_t regval; /* Mark device as uninitialized. */ @@ -1613,9 +1613,9 @@ static void stm32l5serial_shutdown(struct uart_dev_s *dev) /* Disable Rx, Tx, and the UART */ - regval = stm32l5serial_getreg(priv, STM32L5_USART_CR1_OFFSET); + regval = stm32l5serial_getreg(priv, STM32_USART_CR1_OFFSET); regval &= ~(USART_CR1_UE | USART_CR1_TE | USART_CR1_RE); - stm32l5serial_putreg(priv, STM32L5_USART_CR1_OFFSET, regval); + stm32l5serial_putreg(priv, STM32_USART_CR1_OFFSET, regval); /* Release pins. "If the serial-attached device is powered down, the TX * pin causes back-powering, potentially confusing the device to the point @@ -1627,32 +1627,32 @@ static void stm32l5serial_shutdown(struct uart_dev_s *dev) if (priv->tx_gpio != 0) { - stm32l5_unconfiggpio(priv->tx_gpio); + stm32_unconfiggpio(priv->tx_gpio); } if (priv->rx_gpio != 0) { - stm32l5_unconfiggpio(priv->rx_gpio); + stm32_unconfiggpio(priv->rx_gpio); } #ifdef CONFIG_SERIAL_OFLOWCONTROL if (priv->cts_gpio != 0) { - stm32l5_unconfiggpio(priv->cts_gpio); + stm32_unconfiggpio(priv->cts_gpio); } #endif #ifdef CONFIG_SERIAL_IFLOWCONTROL if (priv->rts_gpio != 0) { - stm32l5_unconfiggpio(priv->rts_gpio); + stm32_unconfiggpio(priv->rts_gpio); } #endif #ifdef HAVE_RS485 if (priv->rs485_dir_gpio != 0) { - stm32l5_unconfiggpio(priv->rs485_dir_gpio); + stm32_unconfiggpio(priv->rs485_dir_gpio); } #endif } @@ -1669,8 +1669,8 @@ static void stm32l5serial_shutdown(struct uart_dev_s *dev) #ifdef SERIAL_HAVE_DMA static void stm32l5serial_dmashutdown(struct uart_dev_s *dev) { - struct stm32l5_serial_s *priv = - (struct stm32l5_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; /* Perform the normal UART shutdown */ @@ -1678,11 +1678,11 @@ static void stm32l5serial_dmashutdown(struct uart_dev_s *dev) /* Stop the DMA channel */ - stm32l5_dmastop(priv->rxdma); + stm32_dmastop(priv->rxdma); /* Release the DMA channel */ - stm32l5_dmafree(priv->rxdma); + stm32_dmafree(priv->rxdma); priv->rxdma = NULL; } #endif @@ -1705,8 +1705,8 @@ static void stm32l5serial_dmashutdown(struct uart_dev_s *dev) static int stm32l5serial_attach(struct uart_dev_s *dev) { - struct stm32l5_serial_s *priv = - (struct stm32l5_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; int ret; /* Attach and enable the IRQ */ @@ -1737,8 +1737,8 @@ static int stm32l5serial_attach(struct uart_dev_s *dev) static void stm32l5serial_detach(struct uart_dev_s *dev) { - struct stm32l5_serial_s *priv = - (struct stm32l5_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; up_disable_irq(priv->irq); irq_detach(priv->irq); } @@ -1757,7 +1757,7 @@ static void stm32l5serial_detach(struct uart_dev_s *dev) static int stm32l5serial_interrupt(int irq, void *context, void *arg) { - struct stm32l5_serial_s *priv = (struct stm32l5_serial_s *)arg; + struct stm32_serial_s *priv = (struct stm32_serial_s *)arg; int passes; bool handled; @@ -1765,8 +1765,8 @@ static int stm32l5serial_interrupt(int irq, void *context, void *arg) /* Report serial activity to the power management logic */ -#if defined(CONFIG_PM) && CONFIG_STM32L5_PM_SERIAL_ACTIVITY > 0 - pm_activity(PM_IDLE_DOMAIN, CONFIG_STM32L5_PM_SERIAL_ACTIVITY); +#if defined(CONFIG_PM) && CONFIG_STM32_PM_SERIAL_ACTIVITY > 0 + pm_activity(PM_IDLE_DOMAIN, CONFIG_STM32_PM_SERIAL_ACTIVITY); #endif /* Loop until there are no characters to be transferred or, @@ -1780,7 +1780,7 @@ static int stm32l5serial_interrupt(int irq, void *context, void *arg) /* Get the masked USART status word. */ - priv->sr = stm32l5serial_getreg(priv, STM32L5_USART_ISR_OFFSET); + priv->sr = stm32l5serial_getreg(priv, STM32_USART_ISR_OFFSET); /* USART interrupts: * @@ -1817,7 +1817,7 @@ static int stm32l5serial_interrupt(int irq, void *context, void *arg) (priv->ie & USART_CR1_TCIE) != 0 && (priv->ie & USART_CR1_TXEIE) == 0) { - stm32l5_gpiowrite(priv->rs485_dir_gpio, !priv->rs485_dir_polarity); + stm32_gpiowrite(priv->rs485_dir_gpio, !priv->rs485_dir_polarity); stm32l5serial_restoreusartint(priv, priv->ie & ~USART_CR1_TCIE); } #endif @@ -1847,7 +1847,7 @@ static int stm32l5serial_interrupt(int irq, void *context, void *arg) * interrupt clear register (ICR). */ - stm32l5serial_putreg(priv, STM32L5_USART_ICR_OFFSET, + stm32l5serial_putreg(priv, STM32_USART_ICR_OFFSET, (USART_ICR_NCF | USART_ICR_ORECF | USART_ICR_FECF)); } @@ -1883,8 +1883,8 @@ static int stm32l5serial_ioctl(struct file *filep, int cmd, struct uart_dev_s *dev = inode->i_private; #endif #if defined(CONFIG_SERIAL_TERMIOS) - struct stm32l5_serial_s *priv = - (struct stm32l5_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; #endif int ret = OK; @@ -1893,9 +1893,9 @@ static int stm32l5serial_ioctl(struct file *filep, int cmd, #ifdef CONFIG_SERIAL_TIOCSERGSTRUCT case TIOCSERGSTRUCT: { - struct stm32l5_serial_s *user; + struct stm32_serial_s *user; - user = (struct stm32l5_serial_s *)arg; + user = (struct stm32_serial_s *)arg; if (!user) { @@ -1903,13 +1903,13 @@ static int stm32l5serial_ioctl(struct file *filep, int cmd, } else { - memcpy(user, dev, sizeof(struct stm32l5_serial_s)); + memcpy(user, dev, sizeof(struct stm32_serial_s)); } } break; #endif -#ifdef CONFIG_STM32L5_USART_SINGLEWIRE +#ifdef CONFIG_STM32_USART_SINGLEWIRE case TIOCSSINGLEWIRE: { uint32_t cr1; @@ -1920,19 +1920,19 @@ static int stm32l5serial_ioctl(struct file *filep, int cmd, /* Get the original state of UE */ - cr1 = stm32l5serial_getreg(priv, STM32L5_USART_CR1_OFFSET); + cr1 = stm32l5serial_getreg(priv, STM32_USART_CR1_OFFSET); cr1_ue = cr1 & USART_CR1_UE; cr1 &= ~USART_CR1_UE; /* Disable UE, HDSEL can only be written when UE=0 */ - stm32l5serial_putreg(priv, STM32L5_USART_CR1_OFFSET, cr1); + stm32l5serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1); /* Change the TX port to be open-drain/push-pull and enable/disable * half-duplex mode. */ - uint32_t cr = stm32l5serial_getreg(priv, STM32L5_USART_CR3_OFFSET); + uint32_t cr = stm32l5serial_getreg(priv, STM32_USART_CR3_OFFSET); if ((arg & SER_SINGLEWIRE_ENABLED) != 0) { @@ -1958,7 +1958,7 @@ static int stm32l5serial_ioctl(struct file *filep, int cmd, if (priv->tx_gpio != 0) { - stm32l5_configgpio((priv->tx_gpio & + stm32_configgpio((priv->tx_gpio & ~(GPIO_PUPD_MASK | GPIO_OPENDRAIN)) | gpio_val); } @@ -1969,7 +1969,7 @@ static int stm32l5serial_ioctl(struct file *filep, int cmd, { if (priv->tx_gpio != 0) { - stm32l5_configgpio((priv->tx_gpio & + stm32_configgpio((priv->tx_gpio & ~(GPIO_PUPD_MASK | GPIO_OPENDRAIN)) | GPIO_PUSHPULL); } @@ -1977,17 +1977,17 @@ static int stm32l5serial_ioctl(struct file *filep, int cmd, cr &= ~USART_CR3_HDSEL; } - stm32l5serial_putreg(priv, STM32L5_USART_CR3_OFFSET, cr); + stm32l5serial_putreg(priv, STM32_USART_CR3_OFFSET, cr); /* Re-enable UE if appropriate */ - stm32l5serial_putreg(priv, STM32L5_USART_CR1_OFFSET, cr1 | cr1_ue); + stm32l5serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1 | cr1_ue); leave_critical_section(flags); } break; #endif -#ifdef CONFIG_STM32L5_USART_INVERT +#ifdef CONFIG_STM32_USART_INVERT case TIOCSINVERT: { uint32_t cr1; @@ -1998,17 +1998,17 @@ static int stm32l5serial_ioctl(struct file *filep, int cmd, /* Get the original state of UE */ - cr1 = stm32l5serial_getreg(priv, STM32L5_USART_CR1_OFFSET); + cr1 = stm32l5serial_getreg(priv, STM32_USART_CR1_OFFSET); cr1_ue = cr1 & USART_CR1_UE; cr1 &= ~USART_CR1_UE; /* Disable UE, {R,T}XINV can only be written when UE=0 */ - stm32l5serial_putreg(priv, STM32L5_USART_CR1_OFFSET, cr1); + stm32l5serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1); /* Enable/disable signal inversion. */ - uint32_t cr = stm32l5serial_getreg(priv, STM32L5_USART_CR2_OFFSET); + uint32_t cr = stm32l5serial_getreg(priv, STM32_USART_CR2_OFFSET); if (arg & SER_INVERT_ENABLED_RX) { @@ -2028,17 +2028,17 @@ static int stm32l5serial_ioctl(struct file *filep, int cmd, cr &= ~USART_CR2_TXINV; } - stm32l5serial_putreg(priv, STM32L5_USART_CR2_OFFSET, cr); + stm32l5serial_putreg(priv, STM32_USART_CR2_OFFSET, cr); /* Re-enable UE if appropriate */ - stm32l5serial_putreg(priv, STM32L5_USART_CR1_OFFSET, cr1 | cr1_ue); + stm32l5serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1 | cr1_ue); leave_critical_section(flags); } break; #endif -#ifdef CONFIG_STM32L5_USART_SWAP +#ifdef CONFIG_STM32_USART_SWAP case TIOCSSWAP: { uint32_t cr1; @@ -2049,17 +2049,17 @@ static int stm32l5serial_ioctl(struct file *filep, int cmd, /* Get the original state of UE */ - cr1 = stm32l5serial_getreg(priv, STM32L5_USART_CR1_OFFSET); + cr1 = stm32l5serial_getreg(priv, STM32_USART_CR1_OFFSET); cr1_ue = cr1 & USART_CR1_UE; cr1 &= ~USART_CR1_UE; /* Disable UE, SWAP can only be written when UE=0 */ - stm32l5serial_putreg(priv, STM32L5_USART_CR1_OFFSET, cr1); + stm32l5serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1); /* Enable/disable Swap mode. */ - uint32_t cr = stm32l5serial_getreg(priv, STM32L5_USART_CR2_OFFSET); + uint32_t cr = stm32l5serial_getreg(priv, STM32_USART_CR2_OFFSET); if (arg == SER_SWAP_ENABLED) { @@ -2070,11 +2070,11 @@ static int stm32l5serial_ioctl(struct file *filep, int cmd, cr &= ~USART_CR2_SWAP; } - stm32l5serial_putreg(priv, STM32L5_USART_CR2_OFFSET, cr); + stm32l5serial_putreg(priv, STM32_USART_CR2_OFFSET, cr); /* Re-enable UE if appropriate */ - stm32l5serial_putreg(priv, STM32L5_USART_CR1_OFFSET, cr1 | cr1_ue); + stm32l5serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1 | cr1_ue); leave_critical_section(flags); } break; @@ -2175,8 +2175,8 @@ static int stm32l5serial_ioctl(struct file *filep, int cmd, break; #endif /* CONFIG_SERIAL_TERMIOS */ -#ifdef CONFIG_STM32L5_USART_BREAKS -# ifdef CONFIG_STM32L5_SERIALBRK_BSDCOMPAT +#ifdef CONFIG_STM32_USART_BREAKS +# ifdef CONFIG_STM32_SERIALBRK_BSDCOMPAT case TIOCSBRK: /* BSD compatibility: Turn break on, unconditionally */ { irqstate_t flags; @@ -2195,7 +2195,7 @@ static int stm32l5serial_ioctl(struct file *filep, int cmd, { uint32_t tx_break = GPIO_OUTPUT | (~(GPIO_MODE_MASK | GPIO_OUTPUT_SET) & priv->tx_gpio); - stm32l5_configgpio(tx_break); + stm32_configgpio(tx_break); } leave_critical_section(flags); @@ -2212,7 +2212,7 @@ static int stm32l5serial_ioctl(struct file *filep, int cmd, if (priv->tx_gpio != 0) { - stm32l5_configgpio(priv->tx_gpio); + stm32_configgpio(priv->tx_gpio); } priv->ie &= ~USART_CR1_IE_BREAK_INPROGRESS; @@ -2231,8 +2231,8 @@ static int stm32l5serial_ioctl(struct file *filep, int cmd, irqstate_t flags; flags = enter_critical_section(); - cr1 = stm32l5serial_getreg(priv, STM32L5_USART_CR1_OFFSET); - stm32l5serial_putreg(priv, STM32L5_USART_CR1_OFFSET, + cr1 = stm32l5serial_getreg(priv, STM32_USART_CR1_OFFSET); + stm32l5serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1 | USART_CR1_SBK); leave_critical_section(flags); } @@ -2244,8 +2244,8 @@ static int stm32l5serial_ioctl(struct file *filep, int cmd, irqstate_t flags; flags = enter_critical_section(); - cr1 = stm32l5serial_getreg(priv, STM32L5_USART_CR1_OFFSET); - stm32l5serial_putreg(priv, STM32L5_USART_CR1_OFFSET, + cr1 = stm32l5serial_getreg(priv, STM32_USART_CR1_OFFSET); + stm32l5serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1 & ~USART_CR1_SBK); leave_critical_section(flags); } @@ -2275,13 +2275,13 @@ static int stm32l5serial_ioctl(struct file *filep, int cmd, static int stm32l5serial_receive(struct uart_dev_s *dev, unsigned int *status) { - struct stm32l5_serial_s *priv = - (struct stm32l5_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; uint32_t rdr; /* Get the Rx byte */ - rdr = stm32l5serial_getreg(priv, STM32L5_USART_RDR_OFFSET); + rdr = stm32l5serial_getreg(priv, STM32_USART_RDR_OFFSET); /* Get the Rx byte plux error information. Return those in status */ @@ -2305,8 +2305,8 @@ static int stm32l5serial_receive(struct uart_dev_s *dev, #ifndef SERIAL_HAVE_ONLY_DMA static void stm32l5serial_rxint(struct uart_dev_s *dev, bool enable) { - struct stm32l5_serial_s *priv = - (struct stm32l5_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; irqstate_t flags; uint16_t ie; @@ -2365,10 +2365,10 @@ static void stm32l5serial_rxint(struct uart_dev_s *dev, bool enable) #ifndef SERIAL_HAVE_ONLY_DMA static bool stm32l5serial_rxavailable(struct uart_dev_s *dev) { - struct stm32l5_serial_s *priv = - (struct stm32l5_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; - return ((stm32l5serial_getreg(priv, STM32L5_USART_ISR_OFFSET) & + return ((stm32l5serial_getreg(priv, STM32_USART_ISR_OFFSET) & USART_ISR_RXNE) != 0); } #endif @@ -2400,16 +2400,16 @@ static bool stm32l5serial_rxavailable(struct uart_dev_s *dev) static bool stm32l5serial_rxflowcontrol(struct uart_dev_s *dev, unsigned int nbuffered, bool upper) { - struct stm32l5_serial_s *priv = - (struct stm32l5_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; #if defined(CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS) && \ - defined(CONFIG_STM32L5_FLOWCONTROL_BROKEN) + defined(CONFIG_STM32_FLOWCONTROL_BROKEN) if (priv->iflow && (priv->rts_gpio != 0)) { /* Assert/de-assert nRTS set it high resume/stop sending */ - stm32l5_gpiowrite(priv->rts_gpio, upper); + stm32_gpiowrite(priv->rts_gpio, upper); if (upper) { @@ -2484,8 +2484,8 @@ static bool stm32l5serial_rxflowcontrol(struct uart_dev_s *dev, static int stm32l5serial_dmareceive(struct uart_dev_s *dev, unsigned int *status) { - struct stm32l5_serial_s *priv = - (struct stm32l5_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; int c = 0; if (stm32l5serial_dmanextrx(priv) != priv->rxdmanext) @@ -2523,15 +2523,15 @@ static int stm32l5serial_dmareceive(struct uart_dev_s *dev, ****************************************************************************/ #if defined(SERIAL_HAVE_DMA) -static void stm32l5serial_dmareenable(struct stm32l5_serial_s *priv) +static void stm32l5serial_dmareenable(struct stm32_serial_s *priv) { #ifdef CONFIG_SERIAL_IFLOWCONTROL if (priv->iflow) { /* Configure for non-circular DMA reception into the RX FIFO */ - stm32l5_dmasetup(priv->rxdma, - priv->usartbase + STM32L5_USART_RDR_OFFSET, + stm32_dmasetup(priv->rxdma, + priv->usartbase + STM32_USART_RDR_OFFSET, (uint32_t)priv->rxfifo, RXDMA_BUFFER_SIZE, SERIAL_DMA_IFLOW_CONTROL_WORD); @@ -2541,8 +2541,8 @@ static void stm32l5serial_dmareenable(struct stm32l5_serial_s *priv) { /* Configure for circular DMA reception into the RX FIFO */ - stm32l5_dmasetup(priv->rxdma, - priv->usartbase + STM32L5_USART_RDR_OFFSET, + stm32_dmasetup(priv->rxdma, + priv->usartbase + STM32_USART_RDR_OFFSET, (uint32_t)priv->rxfifo, RXDMA_BUFFER_SIZE, SERIAL_DMA_CONTROL_WORD); @@ -2562,7 +2562,7 @@ static void stm32l5serial_dmareenable(struct stm32l5_serial_s *priv) * in and DMA transfer is stopped. */ - stm32l5_dmastart(priv->rxdma, stm32l5serial_dmarxcallback, + stm32_dmastart(priv->rxdma, stm32l5serial_dmarxcallback, (void *)priv, false); } else @@ -2573,7 +2573,7 @@ static void stm32l5serial_dmareenable(struct stm32l5_serial_s *priv) * worth of time to claim bytes before they are overwritten. */ - stm32l5_dmastart(priv->rxdma, stm32l5serial_dmarxcallback, + stm32_dmastart(priv->rxdma, stm32l5serial_dmarxcallback, (void *)priv, true); } @@ -2594,7 +2594,7 @@ static void stm32l5serial_dmareenable(struct stm32l5_serial_s *priv) ****************************************************************************/ #if defined(SERIAL_HAVE_DMA) && defined(CONFIG_SERIAL_IFLOWCONTROL) -static bool stm32l5serial_dmaiflowrestart(struct stm32l5_serial_s *priv) +static bool stm32l5serial_dmaiflowrestart(struct stm32_serial_s *priv) { if (!priv->rxenable) { @@ -2645,8 +2645,8 @@ static bool stm32l5serial_dmaiflowrestart(struct stm32l5_serial_s *priv) #ifdef SERIAL_HAVE_DMA static void stm32l5serial_dmarxint(struct uart_dev_s *dev, bool enable) { - struct stm32l5_serial_s *priv = - (struct stm32l5_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; /* En/disable DMA reception. * @@ -2680,8 +2680,8 @@ static void stm32l5serial_dmarxint(struct uart_dev_s *dev, bool enable) #ifdef SERIAL_HAVE_DMA static bool stm32l5serial_dmarxavailable(struct uart_dev_s *dev) { - struct stm32l5_serial_s *priv = - (struct stm32l5_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; /* Compare our receive pointer to the current DMA pointer, if they * do not match, then there are bytes to be received. @@ -2701,17 +2701,17 @@ static bool stm32l5serial_dmarxavailable(struct uart_dev_s *dev) static void stm32l5serial_send(struct uart_dev_s *dev, int ch) { - struct stm32l5_serial_s *priv = - (struct stm32l5_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; #ifdef HAVE_RS485 if (priv->rs485_dir_gpio != 0) { - stm32l5_gpiowrite(priv->rs485_dir_gpio, priv->rs485_dir_polarity); + stm32_gpiowrite(priv->rs485_dir_gpio, priv->rs485_dir_polarity); } #endif - stm32l5serial_putreg(priv, STM32L5_USART_TDR_OFFSET, (uint32_t)ch); + stm32l5serial_putreg(priv, STM32_USART_TDR_OFFSET, (uint32_t)ch); } /**************************************************************************** @@ -2724,8 +2724,8 @@ static void stm32l5serial_send(struct uart_dev_s *dev, int ch) static void stm32l5serial_txint(struct uart_dev_s *dev, bool enable) { - struct stm32l5_serial_s *priv = - (struct stm32l5_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; irqstate_t flags; /* USART transmit interrupts: @@ -2756,7 +2756,7 @@ static void stm32l5serial_txint(struct uart_dev_s *dev, bool enable) } # endif -# ifdef CONFIG_STM32L5_SERIALBRK_BSDCOMPAT +# ifdef CONFIG_STM32_SERIALBRK_BSDCOMPAT if (priv->ie & USART_CR1_IE_BREAK_INPROGRESS) { leave_critical_section(flags); @@ -2793,10 +2793,10 @@ static void stm32l5serial_txint(struct uart_dev_s *dev, bool enable) static bool stm32l5serial_txready(struct uart_dev_s *dev) { - struct stm32l5_serial_s *priv = - (struct stm32l5_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; - return ((stm32l5serial_getreg(priv, STM32L5_USART_ISR_OFFSET) & + return ((stm32l5serial_getreg(priv, STM32_USART_ISR_OFFSET) & USART_ISR_TXE) != 0); } @@ -2813,7 +2813,7 @@ static bool stm32l5serial_txready(struct uart_dev_s *dev) static void stm32l5serial_dmarxcallback(DMA_HANDLE handle, uint8_t status, void *arg) { - struct stm32l5_serial_s *priv = (struct stm32l5_serial_s *)arg; + struct stm32_serial_s *priv = (struct stm32_serial_s *)arg; if (priv->rxenable && stm32l5serial_dmarxavailable(&priv->dev)) { @@ -2838,11 +2838,11 @@ static void stm32l5serial_dmarxcallback(DMA_HANDLE handle, uint8_t status, * will release Rx DMA. */ - priv->sr = stm32l5serial_getreg(priv, STM32L5_USART_ISR_OFFSET); + priv->sr = stm32l5serial_getreg(priv, STM32_USART_ISR_OFFSET); if ((priv->sr & (USART_ISR_ORE | USART_ISR_NF | USART_ISR_FE)) != 0) { - stm32l5serial_putreg(priv, STM32L5_USART_ICR_OFFSET, + stm32l5serial_putreg(priv, STM32_USART_ICR_OFFSET, (USART_ICR_NCF | USART_ICR_ORECF | USART_ICR_FECF)); } @@ -2971,16 +2971,16 @@ static int stm32l5serial_pmprepare(struct pm_callback_s *cb, int domain, * buffers. */ - stm32l5_serial_dma_poll(); + stm32_serial_dma_poll(); #endif /* Check if any of the active ports have data pending on Tx/Rx * buffers. */ - for (n = 0; n < STM32L5_NLPUART + STM32L5_NUSART + STM32L5_NUART; n++) + for (n = 0; n < STM32_NLPUART + STM32_NUSART + STM32_NUART; n++) { - struct stm32l5_serial_s *priv = g_uart_devs[n]; + struct stm32_serial_s *priv = g_uart_devs[n]; if (!priv || !priv->initialized) { @@ -3048,7 +3048,7 @@ void arm_earlyserialinit(void) /* Disable all USART interrupts */ - for (i = 0; i < STM32L5_NLPUART + STM32L5_NUSART + STM32L5_NUART; i++) + for (i = 0; i < STM32_NLPUART + STM32_NUSART + STM32_NUART; i++) { if (g_uart_devs[i]) { @@ -3097,7 +3097,7 @@ void arm_serialinit(void) #if CONSOLE_UART > 0 uart_register("/dev/console", &g_uart_devs[CONSOLE_UART - 1]->dev); -#ifndef CONFIG_STM32L5_SERIAL_DISABLE_REORDERING +#ifndef CONFIG_STM32_SERIAL_DISABLE_REORDERING /* If not disabled, register the console UART to ttyS0 and exclude * it from initializing it further down */ @@ -3117,7 +3117,7 @@ void arm_serialinit(void) strlcpy(devname, "/dev/ttySx", sizeof(devname)); - for (i = 0; i < STM32L5_NLPUART + STM32L5_NUSART + STM32L5_NUART; i++) + for (i = 0; i < STM32_NLPUART + STM32_NUSART + STM32_NUART; i++) { /* Don't create a device for non-configured ports. */ @@ -3126,7 +3126,7 @@ void arm_serialinit(void) continue; } -#ifndef CONFIG_STM32L5_SERIAL_DISABLE_REORDERING +#ifndef CONFIG_STM32_SERIAL_DISABLE_REORDERING /* Don't create a device for the console - we did that above */ if (g_uart_devs[i]->dev.isconsole) @@ -3144,7 +3144,7 @@ void arm_serialinit(void) } /**************************************************************************** - * Name: stm32l5_serial_dma_poll + * Name: stm32_serial_dma_poll * * Description: * Checks receive DMA buffers for received bytes that have not accumulated @@ -3155,7 +3155,7 @@ void arm_serialinit(void) ****************************************************************************/ #ifdef SERIAL_HAVE_DMA -void stm32l5_serial_dma_poll(void) +void stm32_serial_dma_poll(void) { irqstate_t flags; @@ -3218,7 +3218,7 @@ void stm32l5_serial_dma_poll(void) void up_putc(int ch) { #if CONSOLE_UART > 0 - struct stm32l5_serial_s *priv = g_uart_devs[CONSOLE_UART - 1]; + struct stm32_serial_s *priv = g_uart_devs[CONSOLE_UART - 1]; uint16_t ie; stm32l5serial_disableusartint(priv, &ie); diff --git a/arch/arm/src/stm32l5/stm32l5_spi.c b/arch/arm/src/stm32l5/stm32l5_spi.c index 80f3005edea37..87c822ee87a0b 100644 --- a/arch/arm/src/stm32l5/stm32l5_spi.c +++ b/arch/arm/src/stm32l5/stm32l5_spi.c @@ -21,22 +21,22 @@ ****************************************************************************/ /**************************************************************************** - * The external functions, stm32l5_spi1/2/3select and stm32l5_spi1/2/3status + * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status * must be provided by board-specific logic. They are implementations of the * select and status methods of the SPI interface defined by struct spi_ops_s * (see include/nuttx/spi/spi.h). All other methods (including - * stm32l5_spibus_initialize()) are provided by common STM32 logic. To use + * stm32_spibus_initialize()) are provided by common STM32 logic. To use * this common SPI logic on your board: * - * 1. Provide logic in stm32l5_board_initialize() to configure SPI chip + * 1. Provide logic in stm32_board_initialize() to configure SPI chip * select pins. - * 2. Provide stm32l5_spi1/2/3select() and stm32l5_spi1/2/3status() + * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() * functions in your board-specific logic. These functions will perform * chip selection and status operations using GPIOs in the way your board * is configured. - * 3. Add a calls to stm32l5_spibus_initialize() in your low level + * 3. Add a calls to stm32_spibus_initialize() in your low level * application initialization logic - * 4. The handle returned by stm32l5_spibus_initialize() may then be used to + * 4. The handle returned by stm32_spibus_initialize() may then be used to * bind the SPI driver to higher level logic (e.g., calling * mmcsd_spislotinitialize(), for example, will bind the SPI driver to * the SPI MMC/SD driver). @@ -74,17 +74,17 @@ #include "arm_internal.h" #include "chip.h" -#include "stm32l5.h" +#include "stm32.h" #include "stm32l5_gpio.h" -#ifdef CONFIG_STM32L5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA # include "stm32l5_dma.h" #endif #include "stm32l5_spi.h" #include -#if defined(CONFIG_STM32L5_SPI1) || defined(CONFIG_STM32L5_SPI2) || \ - defined(CONFIG_STM32L5_SPI3) +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || \ + defined(CONFIG_STM32_SPI3) /**************************************************************************** * Pre-processor Definitions @@ -94,19 +94,19 @@ /* SPI interrupts */ -#ifdef CONFIG_STM32L5_SPI_INTERRUPTS +#ifdef CONFIG_STM32_SPI_INTERRUPTS # error "Interrupt driven SPI not yet supported" #endif /* Can't have both interrupt driven SPI and SPI DMA */ -#if defined(CONFIG_STM32L5_SPI_INTERRUPTS) && defined(CONFIG_STM32L5_SPI_DMA) +#if defined(CONFIG_STM32_SPI_INTERRUPTS) && defined(CONFIG_STM32_SPI_DMA) # error "Cannot enable both interrupt mode and DMA mode for SPI" #endif /* SPI DMA priority */ -#ifdef CONFIG_STM32L5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA # if defined(CONFIG_SPI_DMAPRIO) # define SPI_DMA_PRIO CONFIG_SPI_DMAPRIO @@ -135,15 +135,15 @@ * Private Types ****************************************************************************/ -struct stm32l5_spidev_s +struct stm32_spidev_s { struct spi_dev_s spidev; /* Externally visible part of the SPI interface */ uint32_t spibase; /* SPIn base address */ uint32_t spiclock; /* Clocking for the SPI module */ -#ifdef CONFIG_STM32L5_SPI_INTERRUPTS +#ifdef CONFIG_STM32_SPI_INTERRUPTS uint8_t spiirq; /* SPI IRQ number */ #endif -#ifdef CONFIG_STM32L5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA volatile uint8_t rxresult; /* Result of the RX DMA */ volatile uint8_t txresult; /* Result of the RX DMA */ #ifdef CONFIG_SPI_TRIGGER @@ -176,34 +176,34 @@ struct stm32l5_spidev_s /* Helpers */ -static inline uint16_t spi_getreg(struct stm32l5_spidev_s *priv, +static inline uint16_t spi_getreg(struct stm32_spidev_s *priv, uint8_t offset); -static inline void spi_putreg(struct stm32l5_spidev_s *priv, +static inline void spi_putreg(struct stm32_spidev_s *priv, uint8_t offset, uint16_t value); -static inline uint16_t spi_readword(struct stm32l5_spidev_s *priv); -static inline void spi_writeword(struct stm32l5_spidev_s *priv, +static inline uint16_t spi_readword(struct stm32_spidev_s *priv); +static inline void spi_writeword(struct stm32_spidev_s *priv, uint16_t byte); -static inline bool spi_16bitmode(struct stm32l5_spidev_s *priv); +static inline bool spi_16bitmode(struct stm32_spidev_s *priv); /* DMA support */ -#ifdef CONFIG_STM32L5_SPI_DMA -static void spi_dmarxwait(struct stm32l5_spidev_s *priv); -static void spi_dmatxwait(struct stm32l5_spidev_s *priv); -static inline void spi_dmarxwakeup(struct stm32l5_spidev_s *priv); -static inline void spi_dmatxwakeup(struct stm32l5_spidev_s *priv); +#ifdef CONFIG_STM32_SPI_DMA +static void spi_dmarxwait(struct stm32_spidev_s *priv); +static void spi_dmatxwait(struct stm32_spidev_s *priv); +static inline void spi_dmarxwakeup(struct stm32_spidev_s *priv); +static inline void spi_dmatxwakeup(struct stm32_spidev_s *priv); static void spi_dmarxcallback(DMA_HANDLE handle, uint8_t isr, void *arg); static void spi_dmatxcallback(DMA_HANDLE handle, uint8_t isr, void *arg); -static void spi_dmarxsetup(struct stm32l5_spidev_s *priv, +static void spi_dmarxsetup(struct stm32_spidev_s *priv, void *rxbuffer, void *rxdummy, size_t nwords); -static void spi_dmatxsetup(struct stm32l5_spidev_s *priv, +static void spi_dmatxsetup(struct stm32_spidev_s *priv, const void *txbuffer, const void *txdummy, size_t nwords); -static inline void spi_dmarxstart(struct stm32l5_spidev_s *priv); -static inline void spi_dmatxstart(struct stm32l5_spidev_s *priv); +static inline void spi_dmarxstart(struct stm32_spidev_s *priv); +static inline void spi_dmatxstart(struct stm32_spidev_s *priv); #endif /* SPI methods */ @@ -234,7 +234,7 @@ static void spi_recvblock(struct spi_dev_s *dev, /* Initialization */ -static void spi_bus_initialize(struct stm32l5_spidev_s *priv); +static void spi_bus_initialize(struct stm32_spidev_s *priv); /* PM interface */ @@ -247,20 +247,20 @@ static int spi_pm_prepare(struct pm_callback_s *cb, int domain, * Private Data ****************************************************************************/ -#ifdef CONFIG_STM32L5_SPI1 +#ifdef CONFIG_STM32_SPI1 static const struct spi_ops_s g_spi1ops = { .lock = spi_lock, - .select = stm32l5_spi1select, + .select = stm32_spi1select, .setfrequency = spi_setfrequency, .setmode = spi_setmode, .setbits = spi_setbits, #ifdef CONFIG_SPI_HWFEATURES .hwfeatures = spi_hwfeatures, #endif - .status = stm32l5_spi1status, + .status = stm32_spi1status, #ifdef CONFIG_SPI_CMDDATA - .cmddata = stm32l5_spi1cmddata, + .cmddata = stm32_spi1cmddata, #endif .send = spi_send, #ifdef CONFIG_SPI_EXCHANGE @@ -273,24 +273,24 @@ static const struct spi_ops_s g_spi1ops = .trigger = spi_trigger, #endif #ifdef CONFIG_SPI_CALLBACK - .registercallback = stm32l5_spi1register, /* Provided externally */ + .registercallback = stm32_spi1register, /* Provided externally */ #else .registercallback = 0, /* Not implemented */ #endif }; -static struct stm32l5_spidev_s g_spi1dev = +static struct stm32_spidev_s g_spi1dev = { .spidev = { .ops = &g_spi1ops, }, - .spibase = STM32L5_SPI1_BASE, - .spiclock = STM32L5_PCLK2_FREQUENCY, -#ifdef CONFIG_STM32L5_SPI_INTERRUPTS - .spiirq = STM32L5_IRQ_SPI1, + .spibase = STM32_SPI1_BASE, + .spiclock = STM32_PCLK2_FREQUENCY, +#ifdef CONFIG_STM32_SPI_INTERRUPTS + .spiirq = STM32_IRQ_SPI1, #endif -#ifdef CONFIG_STM32L5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA /* lines must be configured in board.h */ .rxch = DMACHAN_SPI1_RX, @@ -305,20 +305,20 @@ static struct stm32l5_spidev_s g_spi1dev = }; #endif -#ifdef CONFIG_STM32L5_SPI2 +#ifdef CONFIG_STM32_SPI2 static const struct spi_ops_s g_spi2ops = { .lock = spi_lock, - .select = stm32l5_spi2select, + .select = stm32_spi2select, .setfrequency = spi_setfrequency, .setmode = spi_setmode, .setbits = spi_setbits, #ifdef CONFIG_SPI_HWFEATURES .hwfeatures = spi_hwfeatures, #endif - .status = stm32l5_spi2status, + .status = stm32_spi2status, #ifdef CONFIG_SPI_CMDDATA - .cmddata = stm32l5_spi2cmddata, + .cmddata = stm32_spi2cmddata, #endif .send = spi_send, #ifdef CONFIG_SPI_EXCHANGE @@ -331,24 +331,24 @@ static const struct spi_ops_s g_spi2ops = .trigger = spi_trigger, #endif #ifdef CONFIG_SPI_CALLBACK - .registercallback = stm32l5_spi2register, /* provided externally */ + .registercallback = stm32_spi2register, /* provided externally */ #else .registercallback = 0, /* not implemented */ #endif }; -static struct stm32l5_spidev_s g_spi2dev = +static struct stm32_spidev_s g_spi2dev = { .spidev = { .ops = &g_spi2ops, }, - .spibase = STM32L5_SPI2_BASE, - .spiclock = STM32L5_PCLK1_FREQUENCY, -#ifdef CONFIG_STM32L5_SPI_INTERRUPTS - .spiirq = STM32L5_IRQ_SPI2, + .spibase = STM32_SPI2_BASE, + .spiclock = STM32_PCLK1_FREQUENCY, +#ifdef CONFIG_STM32_SPI_INTERRUPTS + .spiirq = STM32_IRQ_SPI2, #endif -#ifdef CONFIG_STM32L5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA .rxch = DMACHAN_SPI2_RX, .txch = DMACHAN_SPI2_TX, .rxsem = SEM_INITIALIZER(0), @@ -361,20 +361,20 @@ static struct stm32l5_spidev_s g_spi2dev = }; #endif -#ifdef CONFIG_STM32L5_SPI3 +#ifdef CONFIG_STM32_SPI3 static const struct spi_ops_s g_spi3ops = { .lock = spi_lock, - .select = stm32l5_spi3select, + .select = stm32_spi3select, .setfrequency = spi_setfrequency, .setmode = spi_setmode, .setbits = spi_setbits, #ifdef CONFIG_SPI_HWFEATURES .hwfeatures = spi_hwfeatures, #endif - .status = stm32l5_spi3status, + .status = stm32_spi3status, #ifdef CONFIG_SPI_CMDDATA - .cmddata = stm32l5_spi3cmddata, + .cmddata = stm32_spi3cmddata, #endif .send = spi_send, #ifdef CONFIG_SPI_EXCHANGE @@ -387,24 +387,24 @@ static const struct spi_ops_s g_spi3ops = .trigger = spi_trigger, #endif #ifdef CONFIG_SPI_CALLBACK - .registercallback = stm32l5_spi3register, /* provided externally */ + .registercallback = stm32_spi3register, /* provided externally */ #else .registercallback = 0, /* not implemented */ #endif }; -static struct stm32l5_spidev_s g_spi3dev = +static struct stm32_spidev_s g_spi3dev = { .spidev = { .ops = &g_spi3ops, }, - .spibase = STM32L5_SPI3_BASE, - .spiclock = STM32L5_PCLK1_FREQUENCY, -#ifdef CONFIG_STM32L5_SPI_INTERRUPTS - .spiirq = STM32L5_IRQ_SPI3, + .spibase = STM32_SPI3_BASE, + .spiclock = STM32_PCLK1_FREQUENCY, +#ifdef CONFIG_STM32_SPI_INTERRUPTS + .spiirq = STM32_IRQ_SPI3, #endif -#ifdef CONFIG_STM32L5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA .rxch = DMACHAN_SPI3_RX, .txch = DMACHAN_SPI3_TX, .rxsem = SEM_INITIALIZER(0), @@ -436,7 +436,7 @@ static struct stm32l5_spidev_s g_spi3dev = * ****************************************************************************/ -static inline uint16_t spi_getreg(struct stm32l5_spidev_s *priv, +static inline uint16_t spi_getreg(struct stm32_spidev_s *priv, uint8_t offset) { return getreg16(priv->spibase + offset); @@ -458,7 +458,7 @@ static inline uint16_t spi_getreg(struct stm32l5_spidev_s *priv, * ****************************************************************************/ -static inline void spi_putreg(struct stm32l5_spidev_s *priv, +static inline void spi_putreg(struct stm32_spidev_s *priv, uint8_t offset, uint16_t value) { putreg16(value, priv->spibase + offset); @@ -479,7 +479,7 @@ static inline void spi_putreg(struct stm32l5_spidev_s *priv, * ****************************************************************************/ -static inline uint8_t spi_getreg8(struct stm32l5_spidev_s *priv, +static inline uint8_t spi_getreg8(struct stm32_spidev_s *priv, uint8_t offset) { return getreg8(priv->spibase + offset); @@ -498,7 +498,7 @@ static inline uint8_t spi_getreg8(struct stm32l5_spidev_s *priv, * ****************************************************************************/ -static inline void spi_putreg8(struct stm32l5_spidev_s *priv, +static inline void spi_putreg8(struct stm32_spidev_s *priv, uint8_t offset, uint8_t value) { putreg8(value, priv->spibase + offset); @@ -518,15 +518,15 @@ static inline void spi_putreg8(struct stm32l5_spidev_s *priv, * ****************************************************************************/ -static inline uint16_t spi_readword(struct stm32l5_spidev_s *priv) +static inline uint16_t spi_readword(struct stm32_spidev_s *priv) { /* Wait until the receive buffer is not empty */ - while ((spi_getreg(priv, STM32L5_SPI_SR_OFFSET) & SPI_SR_RXNE) == 0); + while ((spi_getreg(priv, STM32_SPI_SR_OFFSET) & SPI_SR_RXNE) == 0); /* Then return the received byte */ - return spi_getreg(priv, STM32L5_SPI_DR_OFFSET); + return spi_getreg(priv, STM32_SPI_DR_OFFSET); } /**************************************************************************** @@ -543,15 +543,15 @@ static inline uint16_t spi_readword(struct stm32l5_spidev_s *priv) * ****************************************************************************/ -static inline uint8_t spi_readbyte(struct stm32l5_spidev_s *priv) +static inline uint8_t spi_readbyte(struct stm32_spidev_s *priv) { /* Wait until the receive buffer is not empty */ - while ((spi_getreg(priv, STM32L5_SPI_SR_OFFSET) & SPI_SR_RXNE) == 0); + while ((spi_getreg(priv, STM32_SPI_SR_OFFSET) & SPI_SR_RXNE) == 0); /* Then return the received byte */ - return spi_getreg8(priv, STM32L5_SPI_DR_OFFSET); + return spi_getreg8(priv, STM32_SPI_DR_OFFSET); } /**************************************************************************** @@ -569,16 +569,16 @@ static inline uint8_t spi_readbyte(struct stm32l5_spidev_s *priv) * ****************************************************************************/ -static inline void spi_writeword(struct stm32l5_spidev_s *priv, +static inline void spi_writeword(struct stm32_spidev_s *priv, uint16_t word) { /* Wait until the transmit buffer is empty */ - while ((spi_getreg(priv, STM32L5_SPI_SR_OFFSET) & SPI_SR_TXE) == 0); + while ((spi_getreg(priv, STM32_SPI_SR_OFFSET) & SPI_SR_TXE) == 0); /* Then send the byte */ - spi_putreg(priv, STM32L5_SPI_DR_OFFSET, word); + spi_putreg(priv, STM32_SPI_DR_OFFSET, word); } /**************************************************************************** @@ -596,16 +596,16 @@ static inline void spi_writeword(struct stm32l5_spidev_s *priv, * ****************************************************************************/ -static inline void spi_writebyte(struct stm32l5_spidev_s *priv, +static inline void spi_writebyte(struct stm32_spidev_s *priv, uint8_t byte) { /* Wait until the transmit buffer is empty */ - while ((spi_getreg(priv, STM32L5_SPI_SR_OFFSET) & SPI_SR_TXE) == 0); + while ((spi_getreg(priv, STM32_SPI_SR_OFFSET) & SPI_SR_TXE) == 0); /* Then send the byte */ - spi_putreg8(priv, STM32L5_SPI_DR_OFFSET, byte); + spi_putreg8(priv, STM32_SPI_DR_OFFSET, byte); } /**************************************************************************** @@ -622,7 +622,7 @@ static inline void spi_writebyte(struct stm32l5_spidev_s *priv, * ****************************************************************************/ -static inline bool spi_16bitmode(struct stm32l5_spidev_s *priv) +static inline bool spi_16bitmode(struct stm32_spidev_s *priv) { return (priv->nbits > 8); } @@ -635,8 +635,8 @@ static inline bool spi_16bitmode(struct stm32l5_spidev_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32L5_SPI_DMA -static void spi_dmarxwait(struct stm32l5_spidev_s *priv) +#ifdef CONFIG_STM32_SPI_DMA +static void spi_dmarxwait(struct stm32_spidev_s *priv) { int ret; @@ -666,8 +666,8 @@ static void spi_dmarxwait(struct stm32l5_spidev_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32L5_SPI_DMA -static void spi_dmatxwait(struct stm32l5_spidev_s *priv) +#ifdef CONFIG_STM32_SPI_DMA +static void spi_dmatxwait(struct stm32_spidev_s *priv) { int ret; @@ -697,8 +697,8 @@ static void spi_dmatxwait(struct stm32l5_spidev_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32L5_SPI_DMA -static inline void spi_dmarxwakeup(struct stm32l5_spidev_s *priv) +#ifdef CONFIG_STM32_SPI_DMA +static inline void spi_dmarxwakeup(struct stm32_spidev_s *priv) { nxsem_post(&priv->rxsem); } @@ -712,8 +712,8 @@ static inline void spi_dmarxwakeup(struct stm32l5_spidev_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32L5_SPI_DMA -static inline void spi_dmatxwakeup(struct stm32l5_spidev_s *priv) +#ifdef CONFIG_STM32_SPI_DMA +static inline void spi_dmatxwakeup(struct stm32_spidev_s *priv) { nxsem_post(&priv->txsem); } @@ -727,10 +727,10 @@ static inline void spi_dmatxwakeup(struct stm32l5_spidev_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32L5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_dmarxcallback(DMA_HANDLE handle, uint8_t isr, void *arg) { - struct stm32l5_spidev_s *priv = (struct stm32l5_spidev_s *)arg; + struct stm32_spidev_s *priv = (struct stm32_spidev_s *)arg; /* Wake-up the SPI driver */ @@ -747,10 +747,10 @@ static void spi_dmarxcallback(DMA_HANDLE handle, uint8_t isr, void *arg) * ****************************************************************************/ -#ifdef CONFIG_STM32L5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_dmatxcallback(DMA_HANDLE handle, uint8_t isr, void *arg) { - struct stm32l5_spidev_s *priv = (struct stm32l5_spidev_s *)arg; + struct stm32_spidev_s *priv = (struct stm32_spidev_s *)arg; /* Wake-up the SPI driver */ @@ -767,8 +767,8 @@ static void spi_dmatxcallback(DMA_HANDLE handle, uint8_t isr, void *arg) * ****************************************************************************/ -#ifdef CONFIG_STM32L5_SPI_DMA -static void spi_dmarxsetup(struct stm32l5_spidev_s *priv, +#ifdef CONFIG_STM32_SPI_DMA +static void spi_dmarxsetup(struct stm32_spidev_s *priv, void *rxbuffer, void *rxdummy, size_t nwords) { @@ -805,7 +805,7 @@ static void spi_dmarxsetup(struct stm32l5_spidev_s *priv, /* Configure the RX DMA */ - stm32l5_dmasetup(priv->rxdma, priv->spibase + STM32L5_SPI_DR_OFFSET, + stm32_dmasetup(priv->rxdma, priv->spibase + STM32_SPI_DR_OFFSET, (uint32_t)rxbuffer, nwords, priv->rxccr); } #endif @@ -818,8 +818,8 @@ static void spi_dmarxsetup(struct stm32l5_spidev_s *priv, * ****************************************************************************/ -#ifdef CONFIG_STM32L5_SPI_DMA -static void spi_dmatxsetup(struct stm32l5_spidev_s *priv, +#ifdef CONFIG_STM32_SPI_DMA +static void spi_dmatxsetup(struct stm32_spidev_s *priv, const void *txbuffer, const void *txdummy, size_t nwords) { @@ -856,7 +856,7 @@ static void spi_dmatxsetup(struct stm32l5_spidev_s *priv, /* Setup the TX DMA */ - stm32l5_dmasetup(priv->txdma, priv->spibase + STM32L5_SPI_DR_OFFSET, + stm32_dmasetup(priv->txdma, priv->spibase + STM32_SPI_DR_OFFSET, (uint32_t)txbuffer, nwords, priv->txccr); } #endif @@ -869,11 +869,11 @@ static void spi_dmatxsetup(struct stm32l5_spidev_s *priv, * ****************************************************************************/ -#ifdef CONFIG_STM32L5_SPI_DMA -static inline void spi_dmarxstart(struct stm32l5_spidev_s *priv) +#ifdef CONFIG_STM32_SPI_DMA +static inline void spi_dmarxstart(struct stm32_spidev_s *priv) { priv->rxresult = 0; - stm32l5_dmastart(priv->rxdma, spi_dmarxcallback, priv, false); + stm32_dmastart(priv->rxdma, spi_dmarxcallback, priv, false); } #endif @@ -885,11 +885,11 @@ static inline void spi_dmarxstart(struct stm32l5_spidev_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32L5_SPI_DMA -static inline void spi_dmatxstart(struct stm32l5_spidev_s *priv) +#ifdef CONFIG_STM32_SPI_DMA +static inline void spi_dmatxstart(struct stm32_spidev_s *priv) { priv->txresult = 0; - stm32l5_dmastart(priv->txdma, spi_dmatxcallback, priv, false); + stm32_dmastart(priv->txdma, spi_dmatxcallback, priv, false); } #endif @@ -909,7 +909,7 @@ static inline void spi_dmatxstart(struct stm32l5_spidev_s *priv) * ****************************************************************************/ -static void spi_modifycr(uint32_t addr, struct stm32l5_spidev_s *priv, +static void spi_modifycr(uint32_t addr, struct stm32_spidev_s *priv, uint16_t setbits, uint16_t clrbits) { uint16_t cr; @@ -943,7 +943,7 @@ static void spi_modifycr(uint32_t addr, struct stm32l5_spidev_s *priv, static int spi_lock(struct spi_dev_s *dev, bool lock) { - struct stm32l5_spidev_s *priv = (struct stm32l5_spidev_s *)dev; + struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev; int ret; if (lock) @@ -979,15 +979,15 @@ static int spi_lock(struct spi_dev_s *dev, bool lock) static uint32_t spi_setfrequency(struct spi_dev_s *dev, uint32_t frequency) { - struct stm32l5_spidev_s *priv = (struct stm32l5_spidev_s *)dev; + struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev; uint16_t setbits; uint32_t actual; - /* Limit to max possible (if STM32L5_SPI_CLK_MAX is defined in board.h) */ + /* Limit to max possible (if STM32_SPI_CLK_MAX is defined in board.h) */ - if (frequency > STM32L5_SPI_CLK_MAX) + if (frequency > STM32_SPI_CLK_MAX) { - frequency = STM32L5_SPI_CLK_MAX; + frequency = STM32_SPI_CLK_MAX; } /* Has the frequency changed? */ @@ -1053,9 +1053,9 @@ static uint32_t spi_setfrequency(struct spi_dev_s *dev, actual = priv->spiclock >> 8; } - spi_modifycr(STM32L5_SPI_CR1_OFFSET, priv, 0, SPI_CR1_SPE); - spi_modifycr(STM32L5_SPI_CR1_OFFSET, priv, setbits, SPI_CR1_BR_MASK); - spi_modifycr(STM32L5_SPI_CR1_OFFSET, priv, SPI_CR1_SPE, 0); + spi_modifycr(STM32_SPI_CR1_OFFSET, priv, 0, SPI_CR1_SPE); + spi_modifycr(STM32_SPI_CR1_OFFSET, priv, setbits, SPI_CR1_BR_MASK); + spi_modifycr(STM32_SPI_CR1_OFFSET, priv, SPI_CR1_SPE, 0); /* Save the frequency selection so that subsequent reconfigurations * will be faster. @@ -1087,7 +1087,7 @@ static uint32_t spi_setfrequency(struct spi_dev_s *dev, static void spi_setmode(struct spi_dev_s *dev, enum spi_mode_e mode) { - struct stm32l5_spidev_s *priv = (struct stm32l5_spidev_s *)dev; + struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev; uint16_t setbits; uint16_t clrbits; @@ -1125,9 +1125,9 @@ static void spi_setmode(struct spi_dev_s *dev, enum spi_mode_e mode) return; } - spi_modifycr(STM32L5_SPI_CR1_OFFSET, priv, 0, SPI_CR1_SPE); - spi_modifycr(STM32L5_SPI_CR1_OFFSET, priv, setbits, clrbits); - spi_modifycr(STM32L5_SPI_CR1_OFFSET, priv, SPI_CR1_SPE, 0); + spi_modifycr(STM32_SPI_CR1_OFFSET, priv, 0, SPI_CR1_SPE); + spi_modifycr(STM32_SPI_CR1_OFFSET, priv, setbits, clrbits); + spi_modifycr(STM32_SPI_CR1_OFFSET, priv, SPI_CR1_SPE, 0); /* Save the mode so that subsequent re-configurations will be * faster @@ -1155,7 +1155,7 @@ static void spi_setmode(struct spi_dev_s *dev, enum spi_mode_e mode) static void spi_setbits(struct spi_dev_s *dev, int nbits) { - struct stm32l5_spidev_s *priv = (struct stm32l5_spidev_s *)dev; + struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev; uint16_t setbits; uint16_t clrbits; int savbits = nbits; @@ -1192,9 +1192,9 @@ static void spi_setbits(struct spi_dev_s *dev, int nbits) clrbits |= SPI_CR2_FRXTH; /* RX FIFO Threshold = 2 bytes */ } - spi_modifycr(STM32L5_SPI_CR1_OFFSET, priv, 0, SPI_CR1_SPE); - spi_modifycr(STM32L5_SPI_CR2_OFFSET, priv, setbits, clrbits); - spi_modifycr(STM32L5_SPI_CR1_OFFSET, priv, SPI_CR1_SPE, 0); + spi_modifycr(STM32_SPI_CR1_OFFSET, priv, 0, SPI_CR1_SPE); + spi_modifycr(STM32_SPI_CR2_OFFSET, priv, setbits, clrbits); + spi_modifycr(STM32_SPI_CR1_OFFSET, priv, SPI_CR1_SPE, 0); /* Save the selection so the subsequence re-configurations will be * faster @@ -1225,7 +1225,7 @@ static int spi_hwfeatures(struct spi_dev_s *dev, spi_hwfeatures_t features) { #if defined(CONFIG_SPI_BITORDER) || defined(CONFIG_SPI_TRIGGER) - struct stm32l5_spidev_s *priv = (struct stm32l5_spidev_s *)dev; + struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev; #endif #ifdef CONFIG_SPI_BITORDER @@ -1247,9 +1247,9 @@ static int spi_hwfeatures(struct spi_dev_s *dev, clrbits = SPI_CR1_LSBFIRST; } - spi_modifycr(STM32L5_SPI_CR1_OFFSET, priv, 0, SPI_CR1_SPE); - spi_modifycr(STM32L5_SPI_CR1_OFFSET, priv, setbits, clrbits); - spi_modifycr(STM32L5_SPI_CR1_OFFSET, priv, SPI_CR1_SPE, 0); + spi_modifycr(STM32_SPI_CR1_OFFSET, priv, 0, SPI_CR1_SPE); + spi_modifycr(STM32_SPI_CR1_OFFSET, priv, setbits, clrbits); + spi_modifycr(STM32_SPI_CR1_OFFSET, priv, SPI_CR1_SPE, 0); features &= ~HWFEAT_LSBFIRST; #endif @@ -1289,7 +1289,7 @@ static int spi_hwfeatures(struct spi_dev_s *dev, static uint32_t spi_send(struct spi_dev_s *dev, uint32_t wd) { - struct stm32l5_spidev_s *priv = (struct stm32l5_spidev_s *)dev; + struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev; uint32_t regval; uint32_t ret; @@ -1315,7 +1315,7 @@ static uint32_t spi_send(struct spi_dev_s *dev, uint32_t wd) * flags). */ - regval = spi_getreg(priv, STM32L5_SPI_SR_OFFSET); + regval = spi_getreg(priv, STM32_SPI_SR_OFFSET); if (spi_16bitmode(priv)) { @@ -1353,8 +1353,8 @@ static uint32_t spi_send(struct spi_dev_s *dev, uint32_t wd) * ****************************************************************************/ -#if !defined(CONFIG_STM32L5_SPI_DMA) || defined(CONFIG_STM32L5_DMACAPABLE) -#if !defined(CONFIG_STM32L5_SPI_DMA) +#if !defined(CONFIG_STM32_SPI_DMA) || defined(CONFIG_STM32_DMACAPABLE) +#if !defined(CONFIG_STM32_SPI_DMA) static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, void *rxbuffer, size_t nwords) #else @@ -1363,7 +1363,7 @@ static void spi_exchange_nodma(struct spi_dev_s *dev, void *rxbuffer, size_t nwords) #endif { - struct stm32l5_spidev_s *priv = (struct stm32l5_spidev_s *)dev; + struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev; DEBUGASSERT(priv && priv->spibase); spiinfo("txbuffer=%p rxbuffer=%p nwords=%d\n", txbuffer, rxbuffer, nwords); @@ -1437,7 +1437,7 @@ static void spi_exchange_nodma(struct spi_dev_s *dev, } } } -#endif /* !CONFIG_STM32L5_SPI_DMA || CONFIG_STM32L5_DMACAPABLE */ +#endif /* !CONFIG_STM32_SPI_DMA || CONFIG_STM32_DMACAPABLE */ /**************************************************************************** * Name: spi_exchange (with DMA capability) @@ -1460,17 +1460,17 @@ static void spi_exchange_nodma(struct spi_dev_s *dev, * ****************************************************************************/ -#ifdef CONFIG_STM32L5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, void *rxbuffer, size_t nwords) { - struct stm32l5_spidev_s *priv = (struct stm32l5_spidev_s *)dev; + struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev; -#ifdef CONFIG_STM32L5_DMACAPABLE +#ifdef CONFIG_STM32_DMACAPABLE if ((txbuffer && - !stm32l5_dmacapable((uint32_t)txbuffer, nwords, priv->txccr)) || + !stm32_dmacapable((uint32_t)txbuffer, nwords, priv->txccr)) || (rxbuffer && - !stm32l5_dmacapable((uint32_t)rxbuffer, nwords, priv->rxccr))) + !stm32_dmacapable((uint32_t)rxbuffer, nwords, priv->rxccr))) { /* Unsupported memory region, fall back to non-DMA method. */ @@ -1524,7 +1524,7 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, #endif } } -#endif /* CONFIG_STM32L5_SPI_DMA */ +#endif /* CONFIG_STM32_SPI_DMA */ /**************************************************************************** * Name: spi_trigger @@ -1545,7 +1545,7 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, #ifdef CONFIG_SPI_TRIGGER static int spi_trigger(struct spi_dev_s *dev) { -#ifdef CONFIG_STM32L5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev; if (!priv->trigarmed) @@ -1654,9 +1654,9 @@ static void spi_recvblock(struct spi_dev_s *dev, void *rxbuffer, static int spi_pm_prepare(struct pm_callback_s *cb, int domain, enum pm_state_e pmstate) { - struct stm32l5_spidev_s *priv = - (struct stm32l5_spidev_s *)((char *)cb - - offsetof(struct stm32l5_spidev_s, pm_cb)); + struct stm32_spidev_s *priv = + (struct stm32_spidev_s *)((char *)cb - + offsetof(struct stm32_spidev_s, pm_cb)); /* Logic to prepare for a reduced power state goes here. */ @@ -1707,7 +1707,7 @@ static int spi_pm_prepare(struct pm_callback_s *cb, int domain, * ****************************************************************************/ -static void spi_bus_initialize(struct stm32l5_spidev_s *priv) +static void spi_bus_initialize(struct stm32_spidev_s *priv) { uint16_t setbits; uint16_t clrbits; @@ -1730,11 +1730,11 @@ static void spi_bus_initialize(struct stm32l5_spidev_s *priv) SPI_CR1_BR_MASK | SPI_CR1_LSBFIRST | SPI_CR1_RXONLY | SPI_CR1_BIDIOE | SPI_CR1_BIDIMODE; setbits = SPI_CR1_MSTR | SPI_CR1_SSI | SPI_CR1_SSM; - spi_modifycr(STM32L5_SPI_CR1_OFFSET, priv, setbits, clrbits); + spi_modifycr(STM32_SPI_CR1_OFFSET, priv, setbits, clrbits); clrbits = SPI_CR2_DS_MASK; setbits = SPI_CR2_DS_8BIT | SPI_CR2_FRXTH; /* FRXTH must be high in 8-bit mode */ - spi_modifycr(STM32L5_SPI_CR2_OFFSET, priv, setbits, clrbits); + spi_modifycr(STM32_SPI_CR2_OFFSET, priv, setbits, clrbits); priv->frequency = 0; priv->nbits = 8; @@ -1746,30 +1746,30 @@ static void spi_bus_initialize(struct stm32l5_spidev_s *priv) /* CRCPOLY configuration */ - spi_putreg(priv, STM32L5_SPI_CRCPR_OFFSET, 7); + spi_putreg(priv, STM32_SPI_CRCPR_OFFSET, 7); -#ifdef CONFIG_STM32L5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA /* Get DMA channels. - * NOTE: stm32l5_dmachannel() will always assign the DMA channel. - * If the channel is not available, then stm32l5_dmachannel() will + * NOTE: stm32_dmachannel() will always assign the DMA channel. + * If the channel is not available, then stm32_dmachannel() will * block and wait until the channel becomes available. * WARNING: If you have another device sharing a DMA channel with SPI and * the code never releases that channel, then the call to - * stm32l5_dmachannel() will hang forever in this function! + * stm32_dmachannel() will hang forever in this function! * Don't let your design do that! */ - priv->rxdma = stm32l5_dmachannel(priv->rxch); - priv->txdma = stm32l5_dmachannel(priv->txch); + priv->rxdma = stm32_dmachannel(priv->rxch); + priv->txdma = stm32_dmachannel(priv->txch); DEBUGASSERT(priv->rxdma && priv->txdma); - spi_modifycr(STM32L5_SPI_CR2_OFFSET, priv, + spi_modifycr(STM32_SPI_CR2_OFFSET, priv, SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN, 0); #endif /* Enable spi */ - spi_modifycr(STM32L5_SPI_CR1_OFFSET, priv, SPI_CR1_SPE, 0); + spi_modifycr(STM32_SPI_CR1_OFFSET, priv, SPI_CR1_SPE, 0); #ifdef CONFIG_PM /* Register to receive power management callbacks */ @@ -1785,7 +1785,7 @@ static void spi_bus_initialize(struct stm32l5_spidev_s *priv) ****************************************************************************/ /**************************************************************************** - * Name: stm32l5_spibus_initialize + * Name: stm32_spibus_initialize * * Description: * Initialize the selected SPI bus @@ -1798,13 +1798,13 @@ static void spi_bus_initialize(struct stm32l5_spidev_s *priv) * ****************************************************************************/ -struct spi_dev_s *stm32l5_spibus_initialize(int bus) +struct spi_dev_s *stm32_spibus_initialize(int bus) { - struct stm32l5_spidev_s *priv = NULL; + struct stm32_spidev_s *priv = NULL; irqstate_t flags = enter_critical_section(); -#ifdef CONFIG_STM32L5_SPI1 +#ifdef CONFIG_STM32_SPI1 if (bus == 1) { /* Select SPI1 */ @@ -1817,9 +1817,9 @@ struct spi_dev_s *stm32l5_spibus_initialize(int bus) { /* Configure SPI1 pins: SCK, MISO, and MOSI */ - stm32l5_configgpio(GPIO_SPI1_SCK); - stm32l5_configgpio(GPIO_SPI1_MISO); - stm32l5_configgpio(GPIO_SPI1_MOSI); + stm32_configgpio(GPIO_SPI1_SCK); + stm32_configgpio(GPIO_SPI1_MISO); + stm32_configgpio(GPIO_SPI1_MOSI); /* Set up default configuration: Master, 8-bit, etc. */ @@ -1829,7 +1829,7 @@ struct spi_dev_s *stm32l5_spibus_initialize(int bus) } else #endif -#ifdef CONFIG_STM32L5_SPI2 +#ifdef CONFIG_STM32_SPI2 if (bus == 2) { /* Select SPI2 */ @@ -1842,9 +1842,9 @@ struct spi_dev_s *stm32l5_spibus_initialize(int bus) { /* Configure SPI2 pins: SCK, MISO, and MOSI */ - stm32l5_configgpio(GPIO_SPI2_SCK); - stm32l5_configgpio(GPIO_SPI2_MISO); - stm32l5_configgpio(GPIO_SPI2_MOSI); + stm32_configgpio(GPIO_SPI2_SCK); + stm32_configgpio(GPIO_SPI2_MISO); + stm32_configgpio(GPIO_SPI2_MOSI); /* Set up default configuration: Master, 8-bit, etc. */ @@ -1854,7 +1854,7 @@ struct spi_dev_s *stm32l5_spibus_initialize(int bus) } else #endif -#ifdef CONFIG_STM32L5_SPI3 +#ifdef CONFIG_STM32_SPI3 if (bus == 3) { /* Select SPI3 */ @@ -1867,9 +1867,9 @@ struct spi_dev_s *stm32l5_spibus_initialize(int bus) { /* Configure SPI3 pins: SCK, MISO, and MOSI */ - stm32l5_configgpio(GPIO_SPI3_SCK); - stm32l5_configgpio(GPIO_SPI3_MISO); - stm32l5_configgpio(GPIO_SPI3_MOSI); + stm32_configgpio(GPIO_SPI3_SCK); + stm32_configgpio(GPIO_SPI3_MISO); + stm32_configgpio(GPIO_SPI3_MOSI); /* Set up default configuration: Master, 8-bit, etc. */ @@ -1887,4 +1887,4 @@ struct spi_dev_s *stm32l5_spibus_initialize(int bus) return (struct spi_dev_s *)priv; } -#endif /* CONFIG_STM32L5_SPI1 || CONFIG_STM32L5_SPI2 || CONFIG_STM32L5_SPI3 */ +#endif /* CONFIG_STM32_SPI1 || CONFIG_STM32_SPI2 || CONFIG_STM32_SPI3 */ diff --git a/arch/arm/src/stm32l5/stm32l5_spi.h b/arch/arm/src/stm32l5/stm32l5_spi.h index c13661243a8a1..48b2537d370a5 100644 --- a/arch/arm/src/stm32l5/stm32l5_spi.h +++ b/arch/arm/src/stm32l5/stm32l5_spi.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32L5_STM32L5_SPI_H -#define __ARCH_ARM_SRC_STM32L5_STM32L5_SPI_H +#ifndef __ARCH_ARM_SRC_STM32L5_STM32_SPI_H +#define __ARCH_ARM_SRC_STM32L5_STM32_SPI_H /**************************************************************************** * Included Files @@ -58,7 +58,7 @@ struct spi_dev_s; ****************************************************************************/ /**************************************************************************** - * Name: stm32l5_spibus_initialize + * Name: stm32_spibus_initialize * * Description: * Initialize the selected SPI bus @@ -71,62 +71,62 @@ struct spi_dev_s; * ****************************************************************************/ -struct spi_dev_s *stm32l5_spibus_initialize(int bus); +struct spi_dev_s *stm32_spibus_initialize(int bus); /**************************************************************************** - * Name: stm32l5_spi1/2/...select and stm32l5_spi1/2/...status + * Name: stm32_spi1/2/...select and stm32_spi1/2/...status * * Description: - * The external functions, stm32l5_spi1/2/...select, - * stm32l5_spi1/2/...status, and stm32l5_spi1/2/...cmddata must be provided + * The external functions, stm32_spi1/2/...select, + * stm32_spi1/2/...status, and stm32_spi1/2/...cmddata must be provided * by board-specific logic. These are implementations of the select, * status, and cmddata methods of the SPI interface defined by struct * spi_ops_s (see include/nuttx/spi/spi.h). All other methods (including - * stm32l5_spibus_initialize()) are provided by common STM32 logic. To use + * stm32_spibus_initialize()) are provided by common STM32 logic. To use * this common SPI logic on your board: * - * 1. Provide logic in stm32l5_board_initialize() to configure SPI chip + * 1. Provide logic in stm32_board_initialize() to configure SPI chip * select pins. - * 2. Provide stm32l5_spi1/2/...select() and stm32l5_spi1/2/...status() + * 2. Provide stm32_spi1/2/...select() and stm32_spi1/2/...status() * functions in your board-specific logic. These functions will perform * chip selection and status operations using GPIOs in the way your * board is configured. * 3. If CONFIG_SPI_CMDDATA is defined in your NuttX configuration file, - * then provide stm32l5_spi1/2/...cmddata() functions in your + * then provide stm32_spi1/2/...cmddata() functions in your * board-specific logic. These functions will perform cmd/data * selection operations using GPIOs in the way your board is configured. - * 4. Add a calls to stm32l5_spibus_initialize() in your low level + * 4. Add a calls to stm32_spibus_initialize() in your low level * application initialization logic - * 5. The handle returned by stm32l5_spibus_initialize() may then be used + * 5. The handle returned by stm32_spibus_initialize() may then be used * to bind the SPI driver to higher level logic (e.g., calling * mmcsd_spislotinitialize(), for example, will bind the SPI driver to * the SPI MMC/SD driver). * ****************************************************************************/ -#ifdef CONFIG_STM32L5_SPI1 -void stm32l5_spi1select(struct spi_dev_s *dev, uint32_t devid, +#ifdef CONFIG_STM32_SPI1 +void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, bool selected); -uint8_t stm32l5_spi1status(struct spi_dev_s *dev, uint32_t devid); -int stm32l5_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); +uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid); +int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); #endif -#ifdef CONFIG_STM32L5_SPI2 -void stm32l5_spi2select(struct spi_dev_s *dev, uint32_t devid, +#ifdef CONFIG_STM32_SPI2 +void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid, bool selected); -uint8_t stm32l5_spi2status(struct spi_dev_s *dev, uint32_t devid); -int stm32l5_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); +uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid); +int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); #endif -#ifdef CONFIG_STM32L5_SPI3 -void stm32l5_spi3select(struct spi_dev_s *dev, uint32_t devid, +#ifdef CONFIG_STM32_SPI3 +void stm32_spi3select(struct spi_dev_s *dev, uint32_t devid, bool selected); -uint8_t stm32l5_spi3status(struct spi_dev_s *dev, uint32_t devid); -int stm32l5_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); +uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid); +int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); #endif /**************************************************************************** - * Name: stm32l5_spi1/2/...register + * Name: stm32_spi1/2/...register * * Description: * If the board supports a card detect callback to inform the SPI-based @@ -146,20 +146,20 @@ int stm32l5_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); ****************************************************************************/ #ifdef CONFIG_SPI_CALLBACK -#ifdef CONFIG_STM32L5_SPI1 -int stm32l5_spi1register(struct spi_dev_s *dev, +#ifdef CONFIG_STM32_SPI1 +int stm32_spi1register(struct spi_dev_s *dev, spi_mediachange_t callback, void *arg); #endif -#ifdef CONFIG_STM32L5_SPI2 -int stm32l5_spi2register(struct spi_dev_s *dev, +#ifdef CONFIG_STM32_SPI2 +int stm32_spi2register(struct spi_dev_s *dev, spi_mediachange_t callback, void *arg); #endif -#ifdef CONFIG_STM32L5_SPI3 -int stm32l5_spi3register(struct spi_dev_s *dev, +#ifdef CONFIG_STM32_SPI3 +int stm32_spi3register(struct spi_dev_s *dev, spi_mediachange_t callback, void *arg); #endif @@ -171,4 +171,4 @@ int stm32l5_spi3register(struct spi_dev_s *dev, #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32L5_STM32L5_SPI_H */ +#endif /* __ARCH_ARM_SRC_STM32L5_STM32_SPI_H */ diff --git a/arch/arm/src/stm32l5/stm32l5_start.c b/arch/arm/src/stm32l5/stm32l5_start.c index 94e500d149a16..45d63d4f1b605 100644 --- a/arch/arm/src/stm32l5/stm32l5_start.c +++ b/arch/arm/src/stm32l5/stm32l5_start.c @@ -36,7 +36,7 @@ #include "arm_internal.h" #include "nvic.h" -#include "stm32l5.h" +#include "stm32.h" #include "stm32l5_gpio.h" #include "stm32l5_userspace.h" #include "stm32l5_start.h" @@ -62,8 +62,8 @@ * 0x2003:ffff - End of internal SRAM2 */ -#define SRAM2_START STM32L5_SRAM2_BASE -#define SRAM2_END (SRAM2_START + STM32L5_SRAM2_SIZE) +#define SRAM2_START STM32_SRAM2_BASE +#define SRAM2_END (SRAM2_START + STM32_SRAM2_SIZE) #define HEAP_BASE ((uintptr_t)_ebss + CONFIG_IDLETHREAD_STACKSIZE) @@ -131,7 +131,7 @@ void __start(void) ("sub r10, sp, %0" : : "r" (CONFIG_IDLETHREAD_STACKSIZE - 64) :); #endif -#ifdef CONFIG_STM32L5_SRAM2_INIT +#ifdef CONFIG_STM32_SRAM2_INIT /* The SRAM2 region is parity checked, but upon power up, it will be in * a random state and probably invalid with respect to parity, potentially * generating faults if accessed. If elected, we will write zeros to the @@ -151,10 +151,10 @@ void __start(void) /* Configure the UART so that we can get debug output as soon as possible */ - stm32l5_clockconfig(); + stm32_clockconfig(); arm_fpuconfig(); - stm32l5_lowsetup(); - stm32l5_gpioinit(); + stm32_lowsetup(); + stm32_gpioinit(); showprogress('A'); /* Clear .bss. We'll do this inline (vs. calling memset) just to be @@ -205,13 +205,13 @@ void __start(void) */ #ifdef CONFIG_BUILD_PROTECTED - stm32l5_userspace(); + stm32_userspace(); showprogress('E'); #endif /* Initialize onboard resources */ - stm32l5_board_initialize(); + stm32_board_initialize(); showprogress('F'); /* Then start NuttX */ diff --git a/arch/arm/src/stm32l5/stm32l5_start.h b/arch/arm/src/stm32l5/stm32l5_start.h index 11f34ab293a00..90860b8b5ccc7 100644 --- a/arch/arm/src/stm32l5/stm32l5_start.h +++ b/arch/arm/src/stm32l5/stm32l5_start.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32L5_STM32L5_START_H -#define __ARCH_ARM_SRC_STM32L5_STM32L5_START_H +#ifndef __ARCH_ARM_SRC_STM32L5_STM32_START_H +#define __ARCH_ARM_SRC_STM32L5_STM32_START_H /**************************************************************************** * Included Files @@ -32,7 +32,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32l5_board_initialize + * Name: stm32_board_initialize * * Description: * All STM32L5 architectures must provide the following entry point. This @@ -42,6 +42,6 @@ * ****************************************************************************/ -void stm32l5_board_initialize(void); +void stm32_board_initialize(void); -#endif /* __ARCH_ARM_SRC_STM32L5_STM32L5_START_H */ +#endif /* __ARCH_ARM_SRC_STM32L5_STM32_START_H */ diff --git a/arch/arm/src/stm32l5/stm32l5_tim.c b/arch/arm/src/stm32l5/stm32l5_tim.c index a53bf043a3400..dc176524d9fa6 100644 --- a/arch/arm/src/stm32l5/stm32l5_tim.c +++ b/arch/arm/src/stm32l5/stm32l5_tim.c @@ -40,7 +40,7 @@ #include "chip.h" #include "arm_internal.h" -#include "stm32l5.h" +#include "stm32.h" #include "stm32l5_gpio.h" #include "stm32l5_tim.h" @@ -54,137 +54,137 @@ * include: * * - To generate modulated outputs for such things as motor control. If - * CONFIG_STM32L5_TIMn is defined then the CONFIG_STM32L5_TIMn_PWM may also + * CONFIG_STM32_TIMn is defined then the CONFIG_STM32_TIMn_PWM may also * be defined to indicate that the timer is intended to be used for pulsed * output modulation. * - * - To control periodic ADC input sampling. If CONFIG_STM32L5_TIMn is - * defined then CONFIG_STM32L5_TIMn_ADC may also be defined to indicate + * - To control periodic ADC input sampling. If CONFIG_STM32_TIMn is + * defined then CONFIG_STM32_TIMn_ADC may also be defined to indicate * that timer "n" is intended to be used for that purpose. * - * - To control periodic DAC outputs. If CONFIG_STM32L5_TIMn is defined then - * CONFIG_STM32L5_TIMn_DAC may also be defined to indicate that timer "n" + * - To control periodic DAC outputs. If CONFIG_STM32_TIMn is defined then + * CONFIG_STM32_TIMn_DAC may also be defined to indicate that timer "n" * is intended to be used for that purpose. * - * - To use a Quadrature Encoder. If CONFIG_STM32L5_TIMn is defined then - * CONFIG_STM32L5_TIMn_QE may also be defined to indicate that timer "n" + * - To use a Quadrature Encoder. If CONFIG_STM32_TIMn is defined then + * CONFIG_STM32_TIMn_QE may also be defined to indicate that timer "n" * is intended to be used for that purpose. * * In any of these cases, the timer will not be used by this timer module. */ -#if defined(CONFIG_STM32L5_TIM1_PWM) || defined (CONFIG_STM32L5_TIM1_ADC) || \ - defined(CONFIG_STM32L5_TIM1_DAC) || defined(CONFIG_STM32L5_TIM1_QE) -# undef CONFIG_STM32L5_TIM1 +#if defined(CONFIG_STM32_TIM1_PWM) || defined (CONFIG_STM32_TIM1_ADC) || \ + defined(CONFIG_STM32_TIM1_DAC) || defined(CONFIG_STM32_TIM1_QE) +# undef CONFIG_STM32_TIM1 #endif -#if defined(CONFIG_STM32L5_TIM2_PWM) || defined (CONFIG_STM32L5_TIM2_ADC) || \ - defined(CONFIG_STM32L5_TIM2_DAC) || defined(CONFIG_STM32L5_TIM2_QE) -# undef CONFIG_STM32L5_TIM2 +#if defined(CONFIG_STM32_TIM2_PWM) || defined (CONFIG_STM32_TIM2_ADC) || \ + defined(CONFIG_STM32_TIM2_DAC) || defined(CONFIG_STM32_TIM2_QE) +# undef CONFIG_STM32_TIM2 #endif -#if defined(CONFIG_STM32L5_TIM3_PWM) || defined (CONFIG_STM32L5_TIM3_ADC) || \ - defined(CONFIG_STM32L5_TIM3_DAC) || defined(CONFIG_STM32L5_TIM3_QE) -# undef CONFIG_STM32L5_TIM3 +#if defined(CONFIG_STM32_TIM3_PWM) || defined (CONFIG_STM32_TIM3_ADC) || \ + defined(CONFIG_STM32_TIM3_DAC) || defined(CONFIG_STM32_TIM3_QE) +# undef CONFIG_STM32_TIM3 #endif -#if defined(CONFIG_STM32L5_TIM4_PWM) || defined (CONFIG_STM32L5_TIM4_ADC) || \ - defined(CONFIG_STM32L5_TIM4_DAC) || defined(CONFIG_STM32L5_TIM4_QE) -# undef CONFIG_STM32L5_TIM4 +#if defined(CONFIG_STM32_TIM4_PWM) || defined (CONFIG_STM32_TIM4_ADC) || \ + defined(CONFIG_STM32_TIM4_DAC) || defined(CONFIG_STM32_TIM4_QE) +# undef CONFIG_STM32_TIM4 #endif -#if defined(CONFIG_STM32L5_TIM5_PWM) || defined (CONFIG_STM32L5_TIM5_ADC) || \ - defined(CONFIG_STM32L5_TIM5_DAC) || defined(CONFIG_STM32L5_TIM5_QE) -# undef CONFIG_STM32L5_TIM5 +#if defined(CONFIG_STM32_TIM5_PWM) || defined (CONFIG_STM32_TIM5_ADC) || \ + defined(CONFIG_STM32_TIM5_DAC) || defined(CONFIG_STM32_TIM5_QE) +# undef CONFIG_STM32_TIM5 #endif -#if defined(CONFIG_STM32L5_TIM6_PWM) || defined (CONFIG_STM32L5_TIM6_ADC) || \ - defined(CONFIG_STM32L5_TIM6_DAC) || defined(CONFIG_STM32L5_TIM6_QE) -# undef CONFIG_STM32L5_TIM6 +#if defined(CONFIG_STM32_TIM6_PWM) || defined (CONFIG_STM32_TIM6_ADC) || \ + defined(CONFIG_STM32_TIM6_DAC) || defined(CONFIG_STM32_TIM6_QE) +# undef CONFIG_STM32_TIM6 #endif -#if defined(CONFIG_STM32L5_TIM7_PWM) || defined (CONFIG_STM32L5_TIM7_ADC) || \ - defined(CONFIG_STM32L5_TIM7_DAC) || defined(CONFIG_STM32L5_TIM7_QE) -# undef CONFIG_STM32L5_TIM7 +#if defined(CONFIG_STM32_TIM7_PWM) || defined (CONFIG_STM32_TIM7_ADC) || \ + defined(CONFIG_STM32_TIM7_DAC) || defined(CONFIG_STM32_TIM7_QE) +# undef CONFIG_STM32_TIM7 #endif -#if defined(CONFIG_STM32L5_TIM8_PWM) || defined (CONFIG_STM32L5_TIM8_ADC) || \ - defined(CONFIG_STM32L5_TIM8_DAC) || defined(CONFIG_STM32L5_TIM8_QE) -# undef CONFIG_STM32L5_TIM8 +#if defined(CONFIG_STM32_TIM8_PWM) || defined (CONFIG_STM32_TIM8_ADC) || \ + defined(CONFIG_STM32_TIM8_DAC) || defined(CONFIG_STM32_TIM8_QE) +# undef CONFIG_STM32_TIM8 #endif -#if defined(CONFIG_STM32L5_TIM15_PWM) || defined (CONFIG_STM32L5_TIM15_ADC) || \ - defined(CONFIG_STM32L5_TIM15_DAC) || defined(CONFIG_STM32L5_TIM15_QE) -# undef CONFIG_STM32L5_TIM15 +#if defined(CONFIG_STM32_TIM15_PWM) || defined (CONFIG_STM32_TIM15_ADC) || \ + defined(CONFIG_STM32_TIM15_DAC) || defined(CONFIG_STM32_TIM15_QE) +# undef CONFIG_STM32_TIM15 #endif -#if defined(CONFIG_STM32L5_TIM16_PWM) || defined (CONFIG_STM32L5_TIM16_ADC) || \ - defined(CONFIG_STM32L5_TIM16_DAC) || defined(CONFIG_STM32L5_TIM16_QE) -# undef CONFIG_STM32L5_TIM16 +#if defined(CONFIG_STM32_TIM16_PWM) || defined (CONFIG_STM32_TIM16_ADC) || \ + defined(CONFIG_STM32_TIM16_DAC) || defined(CONFIG_STM32_TIM16_QE) +# undef CONFIG_STM32_TIM16 #endif -#if defined(CONFIG_STM32L5_TIM17_PWM) || defined (CONFIG_STM32L5_TIM17_ADC) || \ - defined(CONFIG_STM32L5_TIM17_DAC) || defined(CONFIG_STM32L5_TIM17_QE) -# undef CONFIG_STM32L5_TIM17 +#if defined(CONFIG_STM32_TIM17_PWM) || defined (CONFIG_STM32_TIM17_ADC) || \ + defined(CONFIG_STM32_TIM17_DAC) || defined(CONFIG_STM32_TIM17_QE) +# undef CONFIG_STM32_TIM17 #endif -#if defined(CONFIG_STM32L5_TIM1) +#if defined(CONFIG_STM32_TIM1) # if defined(GPIO_TIM1_CH1OUT) ||defined(GPIO_TIM1_CH2OUT)||\ defined(GPIO_TIM1_CH3OUT) ||defined(GPIO_TIM1_CH4OUT) # define HAVE_TIM1_GPIOCONFIG 1 #endif #endif -#if defined(CONFIG_STM32L5_TIM2) +#if defined(CONFIG_STM32_TIM2) # if defined(GPIO_TIM2_CH1OUT) ||defined(GPIO_TIM2_CH2OUT)||\ defined(GPIO_TIM2_CH3OUT) ||defined(GPIO_TIM2_CH4OUT) # define HAVE_TIM2_GPIOCONFIG 1 #endif #endif -#if defined(CONFIG_STM32L5_TIM3) +#if defined(CONFIG_STM32_TIM3) # if defined(GPIO_TIM3_CH1OUT) ||defined(GPIO_TIM3_CH2OUT)||\ defined(GPIO_TIM3_CH3OUT) ||defined(GPIO_TIM3_CH4OUT) # define HAVE_TIM3_GPIOCONFIG 1 #endif #endif -#if defined(CONFIG_STM32L5_TIM4) +#if defined(CONFIG_STM32_TIM4) # if defined(GPIO_TIM4_CH1OUT) ||defined(GPIO_TIM4_CH2OUT)||\ defined(GPIO_TIM4_CH3OUT) ||defined(GPIO_TIM4_CH4OUT) # define HAVE_TIM4_GPIOCONFIG 1 #endif #endif -#if defined(CONFIG_STM32L5_TIM5) +#if defined(CONFIG_STM32_TIM5) # if defined(GPIO_TIM5_CH1OUT) ||defined(GPIO_TIM5_CH2OUT)||\ defined(GPIO_TIM5_CH3OUT) ||defined(GPIO_TIM5_CH4OUT) # define HAVE_TIM5_GPIOCONFIG 1 #endif #endif -#if defined(CONFIG_STM32L5_TIM8) +#if defined(CONFIG_STM32_TIM8) # if defined(GPIO_TIM8_CH1OUT) ||defined(GPIO_TIM8_CH2OUT)||\ defined(GPIO_TIM8_CH3OUT) ||defined(GPIO_TIM8_CH4OUT) # define HAVE_TIM8_GPIOCONFIG 1 #endif #endif -#if defined(CONFIG_STM32L5_TIM15) +#if defined(CONFIG_STM32_TIM15) # if defined(GPIO_TIM15_CH1OUT) ||defined(GPIO_TIM15_CH2OUT)||\ defined(GPIO_TIM15_CH3OUT) ||defined(GPIO_TIM15_CH4OUT) # define HAVE_TIM15_GPIOCONFIG 1 #endif #endif -#if defined(CONFIG_STM32L5_TIM16) +#if defined(CONFIG_STM32_TIM16) # if defined(GPIO_TIM16_CH1OUT) ||defined(GPIO_TIM16_CH2OUT)||\ defined(GPIO_TIM16_CH3OUT) ||defined(GPIO_TIM16_CH4OUT) # define HAVE_TIM16_GPIOCONFIG 1 #endif #endif -#if defined(CONFIG_STM32L5_TIM17) +#if defined(CONFIG_STM32_TIM17) # if defined(GPIO_TIM17_CH1OUT) ||defined(GPIO_TIM17_CH2OUT)||\ defined(GPIO_TIM17_CH3OUT) ||defined(GPIO_TIM17_CH4OUT) # define HAVE_TIM17_GPIOCONFIG 1 @@ -195,12 +195,12 @@ * intended for some other purpose. */ -#if defined(CONFIG_STM32L5_TIM1) || defined(CONFIG_STM32L5_TIM2) || \ - defined(CONFIG_STM32L5_TIM3) || defined(CONFIG_STM32L5_TIM4) || \ - defined(CONFIG_STM32L5_TIM5) || defined(CONFIG_STM32L5_TIM6) || \ - defined(CONFIG_STM32L5_TIM7) || defined(CONFIG_STM32L5_TIM8) || \ - defined(CONFIG_STM32L5_TIM15) || defined(CONFIG_STM32L5_TIM16) || \ - defined(CONFIG_STM32L5_TIM17) +#if defined(CONFIG_STM32_TIM1) || defined(CONFIG_STM32_TIM2) || \ + defined(CONFIG_STM32_TIM3) || defined(CONFIG_STM32_TIM4) || \ + defined(CONFIG_STM32_TIM5) || defined(CONFIG_STM32_TIM6) || \ + defined(CONFIG_STM32_TIM7) || defined(CONFIG_STM32_TIM8) || \ + defined(CONFIG_STM32_TIM15) || defined(CONFIG_STM32_TIM16) || \ + defined(CONFIG_STM32_TIM17) /**************************************************************************** * Private Types @@ -208,10 +208,10 @@ /* TIM Device Structure */ -struct stm32l5_tim_priv_s +struct stm32_tim_priv_s { - const struct stm32l5_tim_ops_s *ops; - enum stm32l5_tim_mode_e mode; + const struct stm32_tim_ops_s *ops; + enum stm32_tim_mode_e mode; uint32_t base; /* TIMn base address */ }; @@ -221,181 +221,181 @@ struct stm32l5_tim_priv_s /* Register helpers */ -static inline uint16_t stm32l5_getreg16(struct stm32l5_tim_dev_s *dev, +static inline uint16_t stm32_getreg16(struct stm32_tim_dev_s *dev, uint8_t offset); -static inline void stm32l5_putreg16(struct stm32l5_tim_dev_s *dev, +static inline void stm32_putreg16(struct stm32_tim_dev_s *dev, uint8_t offset, uint16_t value); -static inline void stm32l5_modifyreg16(struct stm32l5_tim_dev_s *dev, +static inline void stm32_modifyreg16(struct stm32_tim_dev_s *dev, uint8_t offset, uint16_t clearbits, uint16_t setbits); -static inline uint32_t stm32l5_getreg32(struct stm32l5_tim_dev_s *dev, +static inline uint32_t stm32_getreg32(struct stm32_tim_dev_s *dev, uint8_t offset); -static inline void stm32l5_putreg32(struct stm32l5_tim_dev_s *dev, +static inline void stm32_putreg32(struct stm32_tim_dev_s *dev, uint8_t offset, uint32_t value); /* Timer helpers */ -static void stm32l5_tim_reload_counter(struct stm32l5_tim_dev_s *dev); -static void stm32l5_tim_enable(struct stm32l5_tim_dev_s *dev); -static void stm32l5_tim_disable(struct stm32l5_tim_dev_s *dev); -static void stm32l5_tim_reset(struct stm32l5_tim_dev_s *dev); +static void stm32_tim_reload_counter(struct stm32_tim_dev_s *dev); +static void stm32_tim_enable(struct stm32_tim_dev_s *dev); +static void stm32_tim_disable(struct stm32_tim_dev_s *dev); +static void stm32_tim_reset(struct stm32_tim_dev_s *dev); #if defined(HAVE_TIM1_GPIOCONFIG) || defined(HAVE_TIM2_GPIOCONFIG) || \ defined(HAVE_TIM3_GPIOCONFIG) || defined(HAVE_TIM4_GPIOCONFIG) || \ defined(HAVE_TIM5_GPIOCONFIG) || defined(HAVE_TIM8_GPIOCONFIG) || \ defined(HAVE_TIM15_GPIOCONFIG) || defined(HAVE_TIM16_GPIOCONFIG) || \ defined(HAVE_TIM17_GPIOCONFIG) -static void stm32l5_tim_gpioconfig(uint32_t cfg, - enum stm32l5_tim_channel_e mode); +static void stm32_tim_gpioconfig(uint32_t cfg, + enum stm32_tim_channel_e mode); #endif /* Timer methods */ -static int stm32l5_tim_setmode(struct stm32l5_tim_dev_s *dev, - enum stm32l5_tim_mode_e mode); -static int stm32l5_tim_setclock(struct stm32l5_tim_dev_s *dev, +static int stm32_tim_setmode(struct stm32_tim_dev_s *dev, + enum stm32_tim_mode_e mode); +static int stm32_tim_setclock(struct stm32_tim_dev_s *dev, uint32_t freq); -static uint32_t stm32l5_tim_getclock(struct stm32l5_tim_dev_s *dev); -static void stm32l5_tim_setperiod(struct stm32l5_tim_dev_s *dev, +static uint32_t stm32_tim_getclock(struct stm32_tim_dev_s *dev); +static void stm32_tim_setperiod(struct stm32_tim_dev_s *dev, uint32_t period); -static uint32_t stm32l5_tim_getperiod(struct stm32l5_tim_dev_s *dev); -static uint32_t stm32l5_tim_getcounter(struct stm32l5_tim_dev_s *dev); -static int stm32l5_tim_setchannel(struct stm32l5_tim_dev_s *dev, +static uint32_t stm32_tim_getperiod(struct stm32_tim_dev_s *dev); +static uint32_t stm32_tim_getcounter(struct stm32_tim_dev_s *dev); +static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, uint8_t channel, - enum stm32l5_tim_channel_e mode); -static int stm32l5_tim_setcompare(struct stm32l5_tim_dev_s *dev, + enum stm32_tim_channel_e mode); +static int stm32_tim_setcompare(struct stm32_tim_dev_s *dev, uint8_t channel, uint32_t compare); -static int stm32l5_tim_getcapture(struct stm32l5_tim_dev_s *dev, +static int stm32_tim_getcapture(struct stm32_tim_dev_s *dev, uint8_t channel); -static int stm32l5_tim_setisr(struct stm32l5_tim_dev_s *dev, +static int stm32_tim_setisr(struct stm32_tim_dev_s *dev, xcpt_t handler, void *arg, int source); -static void stm32l5_tim_enableint(struct stm32l5_tim_dev_s *dev, +static void stm32_tim_enableint(struct stm32_tim_dev_s *dev, int source); -static void stm32l5_tim_disableint(struct stm32l5_tim_dev_s *dev, +static void stm32_tim_disableint(struct stm32_tim_dev_s *dev, int source); -static void stm32l5_tim_ackint(struct stm32l5_tim_dev_s *dev, +static void stm32_tim_ackint(struct stm32_tim_dev_s *dev, int source); -static int stm32l5_tim_checkint(struct stm32l5_tim_dev_s *dev, +static int stm32_tim_checkint(struct stm32_tim_dev_s *dev, int source); /**************************************************************************** * Private Data ****************************************************************************/ -static const struct stm32l5_tim_ops_s stm32l5_tim_ops = +static const struct stm32_tim_ops_s stm32_tim_ops = { - .enable = stm32l5_tim_enable, - .disable = stm32l5_tim_disable, - .setmode = stm32l5_tim_setmode, - .setclock = stm32l5_tim_setclock, - .getclock = stm32l5_tim_getclock, - .setperiod = stm32l5_tim_setperiod, - .getperiod = stm32l5_tim_getperiod, - .getcounter = stm32l5_tim_getcounter, - .setchannel = stm32l5_tim_setchannel, - .setcompare = stm32l5_tim_setcompare, - .getcapture = stm32l5_tim_getcapture, - .setisr = stm32l5_tim_setisr, - .enableint = stm32l5_tim_enableint, - .disableint = stm32l5_tim_disableint, - .ackint = stm32l5_tim_ackint, - .checkint = stm32l5_tim_checkint, + .enable = stm32_tim_enable, + .disable = stm32_tim_disable, + .setmode = stm32_tim_setmode, + .setclock = stm32_tim_setclock, + .getclock = stm32_tim_getclock, + .setperiod = stm32_tim_setperiod, + .getperiod = stm32_tim_getperiod, + .getcounter = stm32_tim_getcounter, + .setchannel = stm32_tim_setchannel, + .setcompare = stm32_tim_setcompare, + .getcapture = stm32_tim_getcapture, + .setisr = stm32_tim_setisr, + .enableint = stm32_tim_enableint, + .disableint = stm32_tim_disableint, + .ackint = stm32_tim_ackint, + .checkint = stm32_tim_checkint, }; -#ifdef CONFIG_STM32L5_TIM1 -struct stm32l5_tim_priv_s stm32l5_tim1_priv = +#ifdef CONFIG_STM32_TIM1 +struct stm32_tim_priv_s stm32_tim1_priv = { - .ops = &stm32l5_tim_ops, - .mode = STM32L5_TIM_MODE_UNUSED, - .base = STM32L5_TIM1_BASE, + .ops = &stm32_tim_ops, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM1_BASE, }; #endif -#ifdef CONFIG_STM32L5_TIM2 -struct stm32l5_tim_priv_s stm32l5_tim2_priv = +#ifdef CONFIG_STM32_TIM2 +struct stm32_tim_priv_s stm32_tim2_priv = { - .ops = &stm32l5_tim_ops, - .mode = STM32L5_TIM_MODE_UNUSED, - .base = STM32L5_TIM2_BASE, + .ops = &stm32_tim_ops, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM2_BASE, }; #endif -#ifdef CONFIG_STM32L5_TIM3 -struct stm32l5_tim_priv_s stm32l5_tim3_priv = +#ifdef CONFIG_STM32_TIM3 +struct stm32_tim_priv_s stm32_tim3_priv = { - .ops = &stm32l5_tim_ops, - .mode = STM32L5_TIM_MODE_UNUSED, - .base = STM32L5_TIM3_BASE, + .ops = &stm32_tim_ops, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM3_BASE, }; #endif -#ifdef CONFIG_STM32L5_TIM4 -struct stm32l5_tim_priv_s stm32l5_tim4_priv = +#ifdef CONFIG_STM32_TIM4 +struct stm32_tim_priv_s stm32_tim4_priv = { - .ops = &stm32l5_tim_ops, - .mode = STM32L5_TIM_MODE_UNUSED, - .base = STM32L5_TIM4_BASE, + .ops = &stm32_tim_ops, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM4_BASE, }; #endif -#ifdef CONFIG_STM32L5_TIM5 -struct stm32l5_tim_priv_s stm32l5_tim5_priv = +#ifdef CONFIG_STM32_TIM5 +struct stm32_tim_priv_s stm32_tim5_priv = { - .ops = &stm32l5_tim_ops, - .mode = STM32L5_TIM_MODE_UNUSED, - .base = STM32L5_TIM5_BASE, + .ops = &stm32_tim_ops, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM5_BASE, }; #endif -#ifdef CONFIG_STM32L5_TIM6 -struct stm32l5_tim_priv_s stm32l5_tim6_priv = +#ifdef CONFIG_STM32_TIM6 +struct stm32_tim_priv_s stm32_tim6_priv = { - .ops = &stm32l5_tim_ops, - .mode = STM32L5_TIM_MODE_UNUSED, - .base = STM32L5_TIM6_BASE, + .ops = &stm32_tim_ops, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM6_BASE, }; #endif -#ifdef CONFIG_STM32L5_TIM7 -struct stm32l5_tim_priv_s stm32l5_tim7_priv = +#ifdef CONFIG_STM32_TIM7 +struct stm32_tim_priv_s stm32_tim7_priv = { - .ops = &stm32l5_tim_ops, - .mode = STM32L5_TIM_MODE_UNUSED, - .base = STM32L5_TIM7_BASE, + .ops = &stm32_tim_ops, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM7_BASE, }; #endif -#ifdef CONFIG_STM32L5_TIM8 -struct stm32l5_tim_priv_s stm32l5_tim8_priv = +#ifdef CONFIG_STM32_TIM8 +struct stm32_tim_priv_s stm32_tim8_priv = { - .ops = &stm32l5_tim_ops, - .mode = STM32L5_TIM_MODE_UNUSED, - .base = STM32L5_TIM8_BASE, + .ops = &stm32_tim_ops, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM8_BASE, }; #endif -#ifdef CONFIG_STM32L5_TIM15 -struct stm32l5_tim_priv_s stm32l5_tim15_priv = +#ifdef CONFIG_STM32_TIM15 +struct stm32_tim_priv_s stm32_tim15_priv = { - .ops = &stm32l5_tim_ops, - .mode = STM32L5_TIM_MODE_UNUSED, - .base = STM32L5_TIM15_BASE, + .ops = &stm32_tim_ops, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM15_BASE, }; #endif -#ifdef CONFIG_STM32L5_TIM16 -struct stm32l5_tim_priv_s stm32l5_tim16_priv = +#ifdef CONFIG_STM32_TIM16 +struct stm32_tim_priv_s stm32_tim16_priv = { - .ops = &stm32l5_tim_ops, - .mode = STM32L5_TIM_MODE_UNUSED, - .base = STM32L5_TIM16_BASE, + .ops = &stm32_tim_ops, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM16_BASE, }; #endif -#ifdef CONFIG_STM32L5_TIM17 -struct stm32l5_tim_priv_s stm32l5_tim17_priv = +#ifdef CONFIG_STM32_TIM17 +struct stm32_tim_priv_s stm32_tim17_priv = { - .ops = &stm32l5_tim_ops, - .mode = STM32L5_TIM_MODE_UNUSED, - .base = STM32L5_TIM17_BASE, + .ops = &stm32_tim_ops, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM17_BASE, }; #endif @@ -404,51 +404,51 @@ struct stm32l5_tim_priv_s stm32l5_tim17_priv = ****************************************************************************/ /**************************************************************************** - * Name: stm32l5_getreg16 + * Name: stm32_getreg16 * * Description: * Get a 16-bit register value by offset * ****************************************************************************/ -static inline uint16_t stm32l5_getreg16(struct stm32l5_tim_dev_s *dev, +static inline uint16_t stm32_getreg16(struct stm32_tim_dev_s *dev, uint8_t offset) { - return getreg16(((struct stm32l5_tim_priv_s *)dev)->base + offset); + return getreg16(((struct stm32_tim_priv_s *)dev)->base + offset); } /**************************************************************************** - * Name: stm32l5_putreg16 + * Name: stm32_putreg16 * * Description: * Put a 16-bit register value by offset * ****************************************************************************/ -static inline void stm32l5_putreg16(struct stm32l5_tim_dev_s *dev, +static inline void stm32_putreg16(struct stm32_tim_dev_s *dev, uint8_t offset, uint16_t value) { - putreg16(value, ((struct stm32l5_tim_priv_s *)dev)->base + offset); + putreg16(value, ((struct stm32_tim_priv_s *)dev)->base + offset); } /**************************************************************************** - * Name: stm32l5_modifyreg16 + * Name: stm32_modifyreg16 * * Description: * Modify a 16-bit register value by offset * ****************************************************************************/ -static inline void stm32l5_modifyreg16(struct stm32l5_tim_dev_s *dev, +static inline void stm32_modifyreg16(struct stm32_tim_dev_s *dev, uint8_t offset, uint16_t clearbits, uint16_t setbits) { - modifyreg16(((struct stm32l5_tim_priv_s *)dev)->base + offset, clearbits, + modifyreg16(((struct stm32_tim_priv_s *)dev)->base + offset, clearbits, setbits); } /**************************************************************************** - * Name: stm32l5_getreg32 + * Name: stm32_getreg32 * * Description: * Get a 32-bit register value by offset. This applies only for the @@ -456,14 +456,14 @@ static inline void stm32l5_modifyreg16(struct stm32l5_tim_dev_s *dev, * ****************************************************************************/ -static inline uint32_t stm32l5_getreg32(struct stm32l5_tim_dev_s *dev, +static inline uint32_t stm32_getreg32(struct stm32_tim_dev_s *dev, uint8_t offset) { - return getreg32(((struct stm32l5_tim_priv_s *)dev)->base + offset); + return getreg32(((struct stm32_tim_priv_s *)dev)->base + offset); } /**************************************************************************** - * Name: stm32l5_putreg32 + * Name: stm32_putreg32 * * Description: * Put a 32-bit register value by offset. This applies only for the @@ -471,48 +471,48 @@ static inline uint32_t stm32l5_getreg32(struct stm32l5_tim_dev_s *dev, * ****************************************************************************/ -static inline void stm32l5_putreg32(struct stm32l5_tim_dev_s *dev, +static inline void stm32_putreg32(struct stm32_tim_dev_s *dev, uint8_t offset, uint32_t value) { - putreg32(value, ((struct stm32l5_tim_priv_s *)dev)->base + offset); + putreg32(value, ((struct stm32_tim_priv_s *)dev)->base + offset); } /**************************************************************************** - * Name: stm32l5_tim_reload_counter + * Name: stm32_tim_reload_counter ****************************************************************************/ -static void stm32l5_tim_reload_counter(struct stm32l5_tim_dev_s *dev) +static void stm32_tim_reload_counter(struct stm32_tim_dev_s *dev) { - uint16_t val = stm32l5_getreg16(dev, STM32L5_GTIM_EGR_OFFSET); + uint16_t val = stm32_getreg16(dev, STM32_GTIM_EGR_OFFSET); val |= GTIM_EGR_UG; - stm32l5_putreg16(dev, STM32L5_GTIM_EGR_OFFSET, val); + stm32_putreg16(dev, STM32_GTIM_EGR_OFFSET, val); } /**************************************************************************** - * Name: stm32l5_tim_enable + * Name: stm32_tim_enable ****************************************************************************/ -static void stm32l5_tim_enable(struct stm32l5_tim_dev_s *dev) +static void stm32_tim_enable(struct stm32_tim_dev_s *dev) { - uint16_t val = stm32l5_getreg16(dev, STM32L5_GTIM_CR1_OFFSET); + uint16_t val = stm32_getreg16(dev, STM32_GTIM_CR1_OFFSET); val |= GTIM_CR1_CEN; - stm32l5_tim_reload_counter(dev); - stm32l5_putreg16(dev, STM32L5_GTIM_CR1_OFFSET, val); + stm32_tim_reload_counter(dev); + stm32_putreg16(dev, STM32_GTIM_CR1_OFFSET, val); } /**************************************************************************** - * Name: stm32l5_tim_disable + * Name: stm32_tim_disable ****************************************************************************/ -static void stm32l5_tim_disable(struct stm32l5_tim_dev_s *dev) +static void stm32_tim_disable(struct stm32_tim_dev_s *dev) { - uint16_t val = stm32l5_getreg16(dev, STM32L5_GTIM_CR1_OFFSET); + uint16_t val = stm32_getreg16(dev, STM32_GTIM_CR1_OFFSET); val &= ~GTIM_CR1_CEN; - stm32l5_putreg16(dev, STM32L5_GTIM_CR1_OFFSET, val); + stm32_putreg16(dev, STM32_GTIM_CR1_OFFSET, val); } /**************************************************************************** - * Name: stm32l5_tim_reset + * Name: stm32_tim_reset * * Description: * Reset timer into system default state, but do not affect output/input @@ -520,14 +520,14 @@ static void stm32l5_tim_disable(struct stm32l5_tim_dev_s *dev) * ****************************************************************************/ -static void stm32l5_tim_reset(struct stm32l5_tim_dev_s *dev) +static void stm32_tim_reset(struct stm32_tim_dev_s *dev) { - ((struct stm32l5_tim_priv_s *)dev)->mode = STM32L5_TIM_MODE_DISABLED; - stm32l5_tim_disable(dev); + ((struct stm32_tim_priv_s *)dev)->mode = STM32_TIM_MODE_DISABLED; + stm32_tim_disable(dev); } /**************************************************************************** - * Name: stm32l5_tim_gpioconfig + * Name: stm32_tim_gpioconfig ****************************************************************************/ #if defined(HAVE_TIM1_GPIOCONFIG) || defined(HAVE_TIM2_GPIOCONFIG) || \ @@ -535,28 +535,28 @@ static void stm32l5_tim_reset(struct stm32l5_tim_dev_s *dev) defined(HAVE_TIM5_GPIOCONFIG) || defined(HAVE_TIM8_GPIOCONFIG) || \ defined(HAVE_TIM15_GPIOCONFIG) || defined(HAVE_TIM16_GPIOCONFIG) || \ defined(HAVE_TIM17_GPIOCONFIG) -static void stm32l5_tim_gpioconfig(uint32_t cfg, - enum stm32l5_tim_channel_e mode) +static void stm32_tim_gpioconfig(uint32_t cfg, + enum stm32_tim_channel_e mode) { /* TODO: Add support for input capture and bipolar dual outputs for TIM8 */ - if (mode & STM32L5_TIM_CH_MODE_MASK) + if (mode & STM32_TIM_CH_MODE_MASK) { - stm32l5_configgpio(cfg); + stm32_configgpio(cfg); } else { - stm32l5_unconfiggpio(cfg); + stm32_unconfiggpio(cfg); } } #endif /**************************************************************************** - * Name: stm32l5_tim_setmode + * Name: stm32_tim_setmode ****************************************************************************/ -static int stm32l5_tim_setmode(struct stm32l5_tim_dev_s *dev, - enum stm32l5_tim_mode_e mode) +static int stm32_tim_setmode(struct stm32_tim_dev_s *dev, + enum stm32_tim_mode_e mode) { uint16_t val = GTIM_CR1_CEN | GTIM_CR1_ARPE; @@ -566,13 +566,13 @@ static int stm32l5_tim_setmode(struct stm32l5_tim_dev_s *dev, * disable it, simply set its clock to valid frequency or zero. */ -#if STM32L5_NBTIM > 0 - if (((struct stm32l5_tim_priv_s *)dev)->base == STM32L5_TIM6_BASE +#if STM32_NBTIM > 0 + if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM6_BASE #endif -#if STM32L5_NBTIM > 1 - || ((struct stm32l5_tim_priv_s *)dev)->base == STM32L5_TIM7_BASE +#if STM32_NBTIM > 1 + || ((struct stm32_tim_priv_s *)dev)->base == STM32_TIM7_BASE #endif -#if STM32L5_NBTIM > 0 +#if STM32_NBTIM > 0 ) { return -EINVAL; @@ -581,19 +581,19 @@ static int stm32l5_tim_setmode(struct stm32l5_tim_dev_s *dev, /* Decode operational modes */ - switch (mode & STM32L5_TIM_MODE_MASK) + switch (mode & STM32_TIM_MODE_MASK) { - case STM32L5_TIM_MODE_DISABLED: + case STM32_TIM_MODE_DISABLED: val = 0; break; - case STM32L5_TIM_MODE_DOWN: + case STM32_TIM_MODE_DOWN: val |= GTIM_CR1_DIR; - case STM32L5_TIM_MODE_UP: + case STM32_TIM_MODE_UP: break; - case STM32L5_TIM_MODE_UPDOWN: + case STM32_TIM_MODE_UPDOWN: val |= GTIM_CR1_CENTER1; /* Our default: Interrupts are generated on compare, when counting @@ -602,7 +602,7 @@ static int stm32l5_tim_setmode(struct stm32l5_tim_dev_s *dev, break; - case STM32L5_TIM_MODE_PULSE: + case STM32_TIM_MODE_PULSE: val |= GTIM_CR1_OPM; break; @@ -610,16 +610,16 @@ static int stm32l5_tim_setmode(struct stm32l5_tim_dev_s *dev, return -EINVAL; } - stm32l5_tim_reload_counter(dev); - stm32l5_putreg16(dev, STM32L5_GTIM_CR1_OFFSET, val); + stm32_tim_reload_counter(dev); + stm32_putreg16(dev, STM32_GTIM_CR1_OFFSET, val); -#if STM32L5_NATIM > 0 +#if STM32_NATIM > 0 /* Advanced registers require Main Output Enable */ - if (((struct stm32l5_tim_priv_s *)dev)->base == STM32L5_TIM1_BASE || - ((struct stm32l5_tim_priv_s *)dev)->base == STM32L5_TIM8_BASE) + if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM1_BASE || + ((struct stm32_tim_priv_s *)dev)->base == STM32_TIM8_BASE) { - stm32l5_modifyreg16(dev, STM32L5_ATIM_BDTR_OFFSET, 0, ATIM_BDTR_MOE); + stm32_modifyreg16(dev, STM32_ATIM_BDTR_OFFSET, 0, ATIM_BDTR_MOE); } #endif @@ -627,10 +627,10 @@ static int stm32l5_tim_setmode(struct stm32l5_tim_dev_s *dev, } /**************************************************************************** - * Name: stm32l5_tim_setclock + * Name: stm32_tim_setclock ****************************************************************************/ -static int stm32l5_tim_setclock(struct stm32l5_tim_dev_s *dev, +static int stm32_tim_setclock(struct stm32_tim_dev_s *dev, uint32_t freq) { uint32_t freqin; @@ -642,7 +642,7 @@ static int stm32l5_tim_setclock(struct stm32l5_tim_dev_s *dev, if (freq == 0) { - stm32l5_tim_disable(dev); + stm32_tim_disable(dev); return 0; } @@ -652,69 +652,69 @@ static int stm32l5_tim_setclock(struct stm32l5_tim_dev_s *dev, * must be defined in the board.h header file. */ - switch (((struct stm32l5_tim_priv_s *)dev)->base) + switch (((struct stm32_tim_priv_s *)dev)->base) { -#ifdef CONFIG_STM32L5_TIM1 - case STM32L5_TIM1_BASE: +#ifdef CONFIG_STM32_TIM1 + case STM32_TIM1_BASE: freqin = BOARD_TIM1_FREQUENCY; break; #endif -#ifdef CONFIG_STM32L5_TIM2 - case STM32L5_TIM2_BASE: +#ifdef CONFIG_STM32_TIM2 + case STM32_TIM2_BASE: freqin = BOARD_TIM2_FREQUENCY; break; #endif -#ifdef CONFIG_STM32L5_TIM3 - case STM32L5_TIM3_BASE: +#ifdef CONFIG_STM32_TIM3 + case STM32_TIM3_BASE: freqin = BOARD_TIM3_FREQUENCY; break; #endif -#ifdef CONFIG_STM32L5_TIM4 - case STM32L5_TIM4_BASE: +#ifdef CONFIG_STM32_TIM4 + case STM32_TIM4_BASE: freqin = BOARD_TIM4_FREQUENCY; break; #endif -#ifdef CONFIG_STM32L5_TIM5 - case STM32L5_TIM5_BASE: +#ifdef CONFIG_STM32_TIM5 + case STM32_TIM5_BASE: freqin = BOARD_TIM5_FREQUENCY; break; #endif -#ifdef CONFIG_STM32L5_TIM6 - case STM32L5_TIM6_BASE: +#ifdef CONFIG_STM32_TIM6 + case STM32_TIM6_BASE: freqin = BOARD_TIM6_FREQUENCY; break; #endif -#ifdef CONFIG_STM32L5_TIM7 - case STM32L5_TIM7_BASE: +#ifdef CONFIG_STM32_TIM7 + case STM32_TIM7_BASE: freqin = BOARD_TIM7_FREQUENCY; break; #endif -#ifdef CONFIG_STM32L5_TIM8 - case STM32L5_TIM8_BASE: +#ifdef CONFIG_STM32_TIM8 + case STM32_TIM8_BASE: freqin = BOARD_TIM8_FREQUENCY; break; #endif -#ifdef CONFIG_STM32L5_TIM15 - case STM32L5_TIM15_BASE: +#ifdef CONFIG_STM32_TIM15 + case STM32_TIM15_BASE: freqin = BOARD_TIM15_FREQUENCY; break; #endif -#ifdef CONFIG_STM32L5_TIM16 - case STM32L5_TIM16_BASE: +#ifdef CONFIG_STM32_TIM16 + case STM32_TIM16_BASE: freqin = BOARD_TIM16_FREQUENCY; break; #endif -#ifdef CONFIG_STM32L5_TIM17 - case STM32L5_TIM17_BASE: +#ifdef CONFIG_STM32_TIM17 + case STM32_TIM17_BASE: freqin = BOARD_TIM17_FREQUENCY; break; #endif @@ -745,17 +745,17 @@ static int stm32l5_tim_setclock(struct stm32l5_tim_dev_s *dev, prescaler = 0xffff; } - stm32l5_putreg16(dev, STM32L5_GTIM_PSC_OFFSET, prescaler); - stm32l5_tim_enable(dev); + stm32_putreg16(dev, STM32_GTIM_PSC_OFFSET, prescaler); + stm32_tim_enable(dev); return prescaler; } /**************************************************************************** - * Name: stm32l5_tim_getclock + * Name: stm32_tim_getclock ****************************************************************************/ -static uint32_t stm32l5_tim_getclock(struct stm32l5_tim_dev_s *dev) +static uint32_t stm32_tim_getclock(struct stm32_tim_dev_s *dev) { uint32_t freqin; uint32_t clock; @@ -767,67 +767,67 @@ static uint32_t stm32l5_tim_getclock(struct stm32l5_tim_dev_s *dev) * must be defined in the board.h header file. */ - switch (((struct stm32l5_tim_priv_s *)dev)->base) + switch (((struct stm32_tim_priv_s *)dev)->base) { -#ifdef CONFIG_STM32L5_TIM1 - case STM32L5_TIM1_BASE: +#ifdef CONFIG_STM32_TIM1 + case STM32_TIM1_BASE: freqin = BOARD_TIM1_FREQUENCY; break; #endif -#ifdef CONFIG_STM32L5_TIM2 - case STM32L5_TIM2_BASE: +#ifdef CONFIG_STM32_TIM2 + case STM32_TIM2_BASE: freqin = BOARD_TIM2_FREQUENCY; break; #endif -#ifdef CONFIG_STM32L5_TIM3 - case STM32L5_TIM3_BASE: +#ifdef CONFIG_STM32_TIM3 + case STM32_TIM3_BASE: freqin = BOARD_TIM3_FREQUENCY; break; #endif -#ifdef CONFIG_STM32L5_TIM4 - case STM32L5_TIM4_BASE: +#ifdef CONFIG_STM32_TIM4 + case STM32_TIM4_BASE: freqin = BOARD_TIM4_FREQUENCY; break; #endif -#ifdef CONFIG_STM32L5_TIM5 - case STM32L5_TIM5_BASE: +#ifdef CONFIG_STM32_TIM5 + case STM32_TIM5_BASE: freqin = BOARD_TIM5_FREQUENCY; break; #endif -#ifdef CONFIG_STM32L5_TIM6 - case STM32L5_TIM6_BASE: +#ifdef CONFIG_STM32_TIM6 + case STM32_TIM6_BASE: freqin = BOARD_TIM6_FREQUENCY; break; #endif -#ifdef CONFIG_STM32L5_TIM7 - case STM32L5_TIM7_BASE: +#ifdef CONFIG_STM32_TIM7 + case STM32_TIM7_BASE: freqin = BOARD_TIM7_FREQUENCY; break; #endif -#ifdef CONFIG_STM32L5_TIM8 - case STM32L5_TIM8_BASE: +#ifdef CONFIG_STM32_TIM8 + case STM32_TIM8_BASE: freqin = BOARD_TIM8_FREQUENCY; break; #endif -#ifdef CONFIG_STM32L5_TIM15 - case STM32L5_TIM15_BASE: +#ifdef CONFIG_STM32_TIM15 + case STM32_TIM15_BASE: freqin = BOARD_TIM15_FREQUENCY; break; #endif -#ifdef CONFIG_STM32L5_TIM16 - case STM32L5_TIM16_BASE: +#ifdef CONFIG_STM32_TIM16 + case STM32_TIM16_BASE: freqin = BOARD_TIM16_FREQUENCY; break; #endif -#ifdef CONFIG_STM32L5_TIM17 - case STM32L5_TIM17_BASE: +#ifdef CONFIG_STM32_TIM17 + case STM32_TIM17_BASE: freqin = BOARD_TIM17_FREQUENCY; break; #endif @@ -837,52 +837,52 @@ static uint32_t stm32l5_tim_getclock(struct stm32l5_tim_dev_s *dev) /* From chip datasheet, at page 1179. */ - clock = freqin / (stm32l5_getreg16(dev, STM32L5_GTIM_PSC_OFFSET) + 1); + clock = freqin / (stm32_getreg16(dev, STM32_GTIM_PSC_OFFSET) + 1); return clock; } /**************************************************************************** - * Name: stm32l5_tim_setperiod + * Name: stm32_tim_setperiod ****************************************************************************/ -static void stm32l5_tim_setperiod(struct stm32l5_tim_dev_s *dev, +static void stm32_tim_setperiod(struct stm32_tim_dev_s *dev, uint32_t period) { DEBUGASSERT(dev != NULL); - stm32l5_putreg32(dev, STM32L5_GTIM_ARR_OFFSET, period); + stm32_putreg32(dev, STM32_GTIM_ARR_OFFSET, period); } /**************************************************************************** - * Name: stm32l5_tim_getperiod + * Name: stm32_tim_getperiod ****************************************************************************/ -static uint32_t stm32l5_tim_getperiod (struct stm32l5_tim_dev_s *dev) +static uint32_t stm32_tim_getperiod (struct stm32_tim_dev_s *dev) { DEBUGASSERT(dev != NULL); - return stm32l5_getreg32 (dev, STM32L5_GTIM_ARR_OFFSET); + return stm32_getreg32 (dev, STM32_GTIM_ARR_OFFSET); } /**************************************************************************** - * Name: stm32l5_tim_getcounter + * Name: stm32_tim_getcounter ****************************************************************************/ -static uint32_t stm32l5_tim_getcounter(struct stm32l5_tim_dev_s *dev) +static uint32_t stm32_tim_getcounter(struct stm32_tim_dev_s *dev) { DEBUGASSERT(dev != NULL); - uint32_t counter = stm32l5_getreg32(dev, STM32L5_GTIM_CNT_OFFSET); + uint32_t counter = stm32_getreg32(dev, STM32_GTIM_CNT_OFFSET); /* In datasheet page 988, there is a useless bit named UIFCPY in TIMx_CNT. * reset it it result when not TIM2 or TIM5. */ -#if defined(CONFIG_STM32L5_TIM2) || defined(CONFIG_STM32L5_TIM5) - switch (((struct stm32l5_tim_priv_s *)dev)->base) +#if defined(CONFIG_STM32_TIM2) || defined(CONFIG_STM32_TIM5) + switch (((struct stm32_tim_priv_s *)dev)->base) { -#ifdef CONFIG_STM32L5_TIM2 - case STM32L5_TIM2_BASE: +#ifdef CONFIG_STM32_TIM2 + case STM32_TIM2_BASE: #endif -#ifdef CONFIG_STM32L5_TIM5 - case STM32L5_TIM5_BASE: +#ifdef CONFIG_STM32_TIM5 + case STM32_TIM5_BASE: #endif return counter; @@ -895,18 +895,18 @@ static uint32_t stm32l5_tim_getcounter(struct stm32l5_tim_dev_s *dev) } /**************************************************************************** - * Name: stm32l5_tim_setchannel + * Name: stm32_tim_setchannel ****************************************************************************/ -static int stm32l5_tim_setchannel(struct stm32l5_tim_dev_s *dev, +static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, uint8_t channel, - enum stm32l5_tim_channel_e mode) + enum stm32_tim_channel_e mode) { uint16_t ccmr_orig = 0; uint16_t ccmr_val = 0; uint16_t ccmr_mask = 0xff; uint16_t ccer_val; - uint8_t ccmr_offset = STM32L5_GTIM_CCMR1_OFFSET; + uint8_t ccmr_offset = STM32_GTIM_CCMR1_OFFSET; DEBUGASSERT(dev != NULL); @@ -919,7 +919,7 @@ static int stm32l5_tim_setchannel(struct stm32l5_tim_dev_s *dev, /* Assume that channel is disabled and polarity is active high */ - ccer_val = stm32l5_getreg16(dev, STM32L5_GTIM_CCER_OFFSET); + ccer_val = stm32_getreg16(dev, STM32_GTIM_CCER_OFFSET); ccer_val &= ~((GTIM_CCER_CC1P | GTIM_CCER_CC1E) << GTIM_CCER_CCXBASE(channel)); @@ -927,13 +927,13 @@ static int stm32l5_tim_setchannel(struct stm32l5_tim_dev_s *dev, * disable it, simply set its clock to valid frequency or zero. */ -#if STM32L5_NBTIM > 0 - if (((struct stm32l5_tim_priv_s *)dev)->base == STM32L5_TIM6_BASE +#if STM32_NBTIM > 0 + if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM6_BASE #endif -#if STM32L5_NBTIM > 1 - || ((struct stm32l5_tim_priv_s *)dev)->base == STM32L5_TIM7_BASE +#if STM32_NBTIM > 1 + || ((struct stm32_tim_priv_s *)dev)->base == STM32_TIM7_BASE #endif -#if STM32L5_NBTIM > 0 +#if STM32_NBTIM > 0 ) { return -EINVAL; @@ -942,12 +942,12 @@ static int stm32l5_tim_setchannel(struct stm32l5_tim_dev_s *dev, /* Decode configuration */ - switch (mode & STM32L5_TIM_CH_MODE_MASK) + switch (mode & STM32_TIM_CH_MODE_MASK) { - case STM32L5_TIM_CH_DISABLED: + case STM32_TIM_CH_DISABLED: break; - case STM32L5_TIM_CH_OUTPWM: + case STM32_TIM_CH_OUTPWM: ccmr_val = (GTIM_CCMR_MODE_PWM1 << GTIM_CCMR1_OC1M_SHIFT) + GTIM_CCMR1_OC1PE; ccer_val |= GTIM_CCER_CC1E << GTIM_CCER_CCXBASE(channel); @@ -959,7 +959,7 @@ static int stm32l5_tim_setchannel(struct stm32l5_tim_dev_s *dev, /* Set polarity */ - if (mode & STM32L5_TIM_CH_POLARITY_NEG) + if (mode & STM32_TIM_CH_POLARITY_NEG) { ccer_val |= GTIM_CCER_CC1P << GTIM_CCER_CCXBASE(channel); } @@ -974,44 +974,44 @@ static int stm32l5_tim_setchannel(struct stm32l5_tim_dev_s *dev, if (channel > 1) { - ccmr_offset = STM32L5_GTIM_CCMR2_OFFSET; + ccmr_offset = STM32_GTIM_CCMR2_OFFSET; } - ccmr_orig = stm32l5_getreg16(dev, ccmr_offset); + ccmr_orig = stm32_getreg16(dev, ccmr_offset); ccmr_orig &= ~ccmr_mask; ccmr_orig |= ccmr_val; - stm32l5_putreg16(dev, ccmr_offset, ccmr_orig); - stm32l5_putreg16(dev, STM32L5_GTIM_CCER_OFFSET, ccer_val); + stm32_putreg16(dev, ccmr_offset, ccmr_orig); + stm32_putreg16(dev, STM32_GTIM_CCER_OFFSET, ccer_val); /* set GPIO */ - switch (((struct stm32l5_tim_priv_s *)dev)->base) + switch (((struct stm32_tim_priv_s *)dev)->base) { -#ifdef CONFIG_STM32L5_TIM1 - case STM32L5_TIM1_BASE: +#ifdef CONFIG_STM32_TIM1 + case STM32_TIM1_BASE: switch (channel) { #if defined(GPIO_TIM1_CH1OUT) case 0: - stm32l5_tim_gpioconfig(GPIO_TIM1_CH1OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM1_CH1OUT, mode); break; #endif #if defined(GPIO_TIM1_CH2OUT) case 1: - stm32l5_tim_gpioconfig(GPIO_TIM1_CH2OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM1_CH2OUT, mode); break; #endif #if defined(GPIO_TIM1_CH3OUT) case 2: - stm32l5_tim_gpioconfig(GPIO_TIM1_CH3OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM1_CH3OUT, mode); break; #endif #if defined(GPIO_TIM1_CH4OUT) case 3: - stm32l5_tim_gpioconfig(GPIO_TIM1_CH4OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM1_CH4OUT, mode); break; #endif @@ -1020,31 +1020,31 @@ static int stm32l5_tim_setchannel(struct stm32l5_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32L5_TIM2 - case STM32L5_TIM2_BASE: +#ifdef CONFIG_STM32_TIM2 + case STM32_TIM2_BASE: switch (channel) { #if defined(GPIO_TIM2_CH1OUT) case 0: - stm32l5_tim_gpioconfig(GPIO_TIM2_CH1OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM2_CH1OUT, mode); break; #endif #if defined(GPIO_TIM2_CH2OUT) case 1: - stm32l5_tim_gpioconfig(GPIO_TIM2_CH2OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM2_CH2OUT, mode); break; #endif #if defined(GPIO_TIM2_CH3OUT) case 2: - stm32l5_tim_gpioconfig(GPIO_TIM2_CH3OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM2_CH3OUT, mode); break; #endif #if defined(GPIO_TIM2_CH4OUT) case 3: - stm32l5_tim_gpioconfig(GPIO_TIM2_CH4OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM2_CH4OUT, mode); break; #endif @@ -1053,31 +1053,31 @@ static int stm32l5_tim_setchannel(struct stm32l5_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32L5_TIM3 - case STM32L5_TIM3_BASE: +#ifdef CONFIG_STM32_TIM3 + case STM32_TIM3_BASE: switch (channel) { #if defined(GPIO_TIM3_CH1OUT) case 0: - stm32l5_tim_gpioconfig(GPIO_TIM3_CH1OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM3_CH1OUT, mode); break; #endif #if defined(GPIO_TIM3_CH2OUT) case 1: - stm32l5_tim_gpioconfig(GPIO_TIM3_CH2OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM3_CH2OUT, mode); break; #endif #if defined(GPIO_TIM3_CH3OUT) case 2: - stm32l5_tim_gpioconfig(GPIO_TIM3_CH3OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM3_CH3OUT, mode); break; #endif #if defined(GPIO_TIM3_CH4OUT) case 3: - stm32l5_tim_gpioconfig(GPIO_TIM3_CH4OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM3_CH4OUT, mode); break; #endif @@ -1086,30 +1086,30 @@ static int stm32l5_tim_setchannel(struct stm32l5_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32L5_TIM4 - case STM32L5_TIM4_BASE: +#ifdef CONFIG_STM32_TIM4 + case STM32_TIM4_BASE: switch (channel) { #if defined(GPIO_TIM4_CH1OUT) case 0: - stm32l5_tim_gpioconfig(GPIO_TIM4_CH1OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM4_CH1OUT, mode); break; #endif #if defined(GPIO_TIM4_CH2OUT) case 1: - stm32l5_tim_gpioconfig(GPIO_TIM4_CH2OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM4_CH2OUT, mode); break; #endif #if defined(GPIO_TIM4_CH3OUT) case 2: - stm32l5_tim_gpioconfig(GPIO_TIM4_CH3OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM4_CH3OUT, mode); break; #endif #if defined(GPIO_TIM4_CH4OUT) case 3: - stm32l5_tim_gpioconfig(GPIO_TIM4_CH4OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM4_CH4OUT, mode); break; #endif @@ -1118,31 +1118,31 @@ static int stm32l5_tim_setchannel(struct stm32l5_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32L5_TIM5 - case STM32L5_TIM5_BASE: +#ifdef CONFIG_STM32_TIM5 + case STM32_TIM5_BASE: switch (channel) { #if defined(GPIO_TIM5_CH1OUT) case 0: - stm32l5_tim_gpioconfig(GPIO_TIM5_CH1OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM5_CH1OUT, mode); break; #endif #if defined(GPIO_TIM5_CH2OUT) case 1: - stm32l5_tim_gpioconfig(GPIO_TIM5_CH2OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM5_CH2OUT, mode); break; #endif #if defined(GPIO_TIM5_CH3OUT) case 2: - stm32l5_tim_gpioconfig(GPIO_TIM5_CH3OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM5_CH3OUT, mode); break; #endif #if defined(GPIO_TIM5_CH4OUT) case 3: - stm32l5_tim_gpioconfig(GPIO_TIM5_CH4OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM5_CH4OUT, mode); break; #endif @@ -1151,31 +1151,31 @@ static int stm32l5_tim_setchannel(struct stm32l5_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32L5_TIM8 - case STM32L5_TIM8_BASE: +#ifdef CONFIG_STM32_TIM8 + case STM32_TIM8_BASE: switch (channel) { #if defined(GPIO_TIM8_CH1OUT) case 0: - stm32l5_tim_gpioconfig(GPIO_TIM8_CH1OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM8_CH1OUT, mode); break; #endif #if defined(GPIO_TIM8_CH2OUT) case 1: - stm32l5_tim_gpioconfig(GPIO_TIM8_CH2OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM8_CH2OUT, mode); break; #endif #if defined(GPIO_TIM8_CH3OUT) case 2: - stm32l5_tim_gpioconfig(GPIO_TIM8_CH3OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM8_CH3OUT, mode); break; #endif #if defined(GPIO_TIM8_CH4OUT) case 3: - stm32l5_tim_gpioconfig(GPIO_TIM8_CH4OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM8_CH4OUT, mode); break; #endif @@ -1184,31 +1184,31 @@ static int stm32l5_tim_setchannel(struct stm32l5_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32L5_TIM15 - case STM32L5_TIM15_BASE: +#ifdef CONFIG_STM32_TIM15 + case STM32_TIM15_BASE: switch (channel) { #if defined(GPIO_TIM15_CH1OUT) case 0: - stm32l5_tim_gpioconfig(GPIO_TIM15_CH1OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM15_CH1OUT, mode); break; #endif #if defined(GPIO_TIM15_CH2OUT) case 1: - stm32l5_tim_gpioconfig(GPIO_TIM15_CH2OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM15_CH2OUT, mode); break; #endif #if defined(GPIO_TIM15_CH3OUT) case 2: - stm32l5_tim_gpioconfig(GPIO_TIM15_CH3OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM15_CH3OUT, mode); break; #endif #if defined(GPIO_TIM15_CH4OUT) case 3: - stm32l5_tim_gpioconfig(GPIO_TIM15_CH4OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM15_CH4OUT, mode); break; #endif @@ -1217,31 +1217,31 @@ static int stm32l5_tim_setchannel(struct stm32l5_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32L5_TIM16 - case STM32L5_TIM16_BASE: +#ifdef CONFIG_STM32_TIM16 + case STM32_TIM16_BASE: switch (channel) { #if defined(GPIO_TIM16_CH1OUT) case 0: - stm32l5_tim_gpioconfig(GPIO_TIM16_CH1OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM16_CH1OUT, mode); break; #endif #if defined(GPIO_TIM16_CH2OUT) case 1: - stm32l5_tim_gpioconfig(GPIO_TIM16_CH2OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM16_CH2OUT, mode); break; #endif #if defined(GPIO_TIM16_CH3OUT) case 2: - stm32l5_tim_gpioconfig(GPIO_TIM16_CH3OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM16_CH3OUT, mode); break; #endif #if defined(GPIO_TIM16_CH4OUT) case 3: - stm32l5_tim_gpioconfig(GPIO_TIM16_CH4OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM16_CH4OUT, mode); break; #endif @@ -1250,31 +1250,31 @@ static int stm32l5_tim_setchannel(struct stm32l5_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32L5_TIM17 - case STM32L5_TIM17_BASE: +#ifdef CONFIG_STM32_TIM17 + case STM32_TIM17_BASE: switch (channel) { #if defined(GPIO_TIM17_CH1OUT) case 0: - stm32l5_tim_gpioconfig(GPIO_TIM17_CH1OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM17_CH1OUT, mode); break; #endif #if defined(GPIO_TIM17_CH2OUT) case 1: - stm32l5_tim_gpioconfig(GPIO_TIM17_CH2OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM17_CH2OUT, mode); break; #endif #if defined(GPIO_TIM17_CH3OUT) case 2: - stm32l5_tim_gpioconfig(GPIO_TIM17_CH3OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM17_CH3OUT, mode); break; #endif #if defined(GPIO_TIM17_CH4OUT) case 3: - stm32l5_tim_gpioconfig(GPIO_TIM17_CH4OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM17_CH4OUT, mode); break; #endif @@ -1292,10 +1292,10 @@ static int stm32l5_tim_setchannel(struct stm32l5_tim_dev_s *dev, } /**************************************************************************** - * Name: stm32l5_tim_setcompare + * Name: stm32_tim_setcompare ****************************************************************************/ -static int stm32l5_tim_setcompare(struct stm32l5_tim_dev_s *dev, +static int stm32_tim_setcompare(struct stm32_tim_dev_s *dev, uint8_t channel, uint32_t compare) { DEBUGASSERT(dev != NULL); @@ -1303,19 +1303,19 @@ static int stm32l5_tim_setcompare(struct stm32l5_tim_dev_s *dev, switch (channel) { case 1: - stm32l5_putreg32(dev, STM32L5_GTIM_CCR1_OFFSET, compare); + stm32_putreg32(dev, STM32_GTIM_CCR1_OFFSET, compare); break; case 2: - stm32l5_putreg32(dev, STM32L5_GTIM_CCR2_OFFSET, compare); + stm32_putreg32(dev, STM32_GTIM_CCR2_OFFSET, compare); break; case 3: - stm32l5_putreg32(dev, STM32L5_GTIM_CCR3_OFFSET, compare); + stm32_putreg32(dev, STM32_GTIM_CCR3_OFFSET, compare); break; case 4: - stm32l5_putreg32(dev, STM32L5_GTIM_CCR4_OFFSET, compare); + stm32_putreg32(dev, STM32_GTIM_CCR4_OFFSET, compare); break; default: @@ -1326,10 +1326,10 @@ static int stm32l5_tim_setcompare(struct stm32l5_tim_dev_s *dev, } /**************************************************************************** - * Name: stm32l5_tim_getcapture + * Name: stm32_tim_getcapture ****************************************************************************/ -static int stm32l5_tim_getcapture(struct stm32l5_tim_dev_s *dev, +static int stm32_tim_getcapture(struct stm32_tim_dev_s *dev, uint8_t channel) { DEBUGASSERT(dev != NULL); @@ -1337,26 +1337,26 @@ static int stm32l5_tim_getcapture(struct stm32l5_tim_dev_s *dev, switch (channel) { case 1: - return stm32l5_getreg32(dev, STM32L5_GTIM_CCR1_OFFSET); + return stm32_getreg32(dev, STM32_GTIM_CCR1_OFFSET); case 2: - return stm32l5_getreg32(dev, STM32L5_GTIM_CCR2_OFFSET); + return stm32_getreg32(dev, STM32_GTIM_CCR2_OFFSET); case 3: - return stm32l5_getreg32(dev, STM32L5_GTIM_CCR3_OFFSET); + return stm32_getreg32(dev, STM32_GTIM_CCR3_OFFSET); case 4: - return stm32l5_getreg32(dev, STM32L5_GTIM_CCR4_OFFSET); + return stm32_getreg32(dev, STM32_GTIM_CCR4_OFFSET); } return -EINVAL; } /**************************************************************************** - * Name: stm32l5_tim_setisr + * Name: stm32_tim_setisr ****************************************************************************/ -static int stm32l5_tim_setisr(struct stm32l5_tim_dev_s *dev, +static int stm32_tim_setisr(struct stm32_tim_dev_s *dev, xcpt_t handler, void *arg, int source) { int vectorno; @@ -1364,69 +1364,69 @@ static int stm32l5_tim_setisr(struct stm32l5_tim_dev_s *dev, DEBUGASSERT(dev != NULL); DEBUGASSERT(source == 0); - switch (((struct stm32l5_tim_priv_s *)dev)->base) + switch (((struct stm32_tim_priv_s *)dev)->base) { -#ifdef CONFIG_STM32L5_TIM1 - case STM32L5_TIM1_BASE: - vectorno = STM32L5_IRQ_TIM1UP; +#ifdef CONFIG_STM32_TIM1 + case STM32_TIM1_BASE: + vectorno = STM32_IRQ_TIM1UP; break; #endif -#ifdef CONFIG_STM32L5_TIM2 - case STM32L5_TIM2_BASE: - vectorno = STM32L5_IRQ_TIM2; +#ifdef CONFIG_STM32_TIM2 + case STM32_TIM2_BASE: + vectorno = STM32_IRQ_TIM2; break; #endif -#ifdef CONFIG_STM32L5_TIM3 - case STM32L5_TIM3_BASE: - vectorno = STM32L5_IRQ_TIM3; +#ifdef CONFIG_STM32_TIM3 + case STM32_TIM3_BASE: + vectorno = STM32_IRQ_TIM3; break; #endif -#ifdef CONFIG_STM32L5_TIM4 - case STM32L5_TIM4_BASE: - vectorno = STM32L5_IRQ_TIM4; +#ifdef CONFIG_STM32_TIM4 + case STM32_TIM4_BASE: + vectorno = STM32_IRQ_TIM4; break; #endif -#ifdef CONFIG_STM32L5_TIM5 - case STM32L5_TIM5_BASE: - vectorno = STM32L5_IRQ_TIM5; +#ifdef CONFIG_STM32_TIM5 + case STM32_TIM5_BASE: + vectorno = STM32_IRQ_TIM5; break; #endif -#ifdef CONFIG_STM32L5_TIM6 - case STM32L5_TIM6_BASE: - vectorno = STM32L5_IRQ_TIM6; +#ifdef CONFIG_STM32_TIM6 + case STM32_TIM6_BASE: + vectorno = STM32_IRQ_TIM6; break; #endif -#ifdef CONFIG_STM32L5_TIM7 - case STM32L5_TIM7_BASE: - vectorno = STM32L5_IRQ_TIM7; +#ifdef CONFIG_STM32_TIM7 + case STM32_TIM7_BASE: + vectorno = STM32_IRQ_TIM7; break; #endif -#ifdef CONFIG_STM32L5_TIM8 - case STM32L5_TIM8_BASE: - vectorno = STM32L5_IRQ_TIM8UP; +#ifdef CONFIG_STM32_TIM8 + case STM32_TIM8_BASE: + vectorno = STM32_IRQ_TIM8UP; break; #endif -#ifdef CONFIG_STM32L5_TIM15 - case STM32L5_TIM15_BASE: - vectorno = STM32L5_IRQ_TIM15; +#ifdef CONFIG_STM32_TIM15 + case STM32_TIM15_BASE: + vectorno = STM32_IRQ_TIM15; break; #endif -#ifdef CONFIG_STM32L5_TIM16 - case STM32L5_TIM16_BASE: - vectorno = STM32L5_IRQ_TIM16; +#ifdef CONFIG_STM32_TIM16 + case STM32_TIM16_BASE: + vectorno = STM32_IRQ_TIM16; break; #endif -#ifdef CONFIG_STM32L5_TIM17 - case STM32L5_TIM17_BASE: - vectorno = STM32L5_IRQ_TIM17; +#ifdef CONFIG_STM32_TIM17 + case STM32_TIM17_BASE: + vectorno = STM32_IRQ_TIM17; break; #endif @@ -1452,44 +1452,44 @@ static int stm32l5_tim_setisr(struct stm32l5_tim_dev_s *dev, } /**************************************************************************** - * Name: stm32l5_tim_enableint + * Name: stm32_tim_enableint ****************************************************************************/ -static void stm32l5_tim_enableint(struct stm32l5_tim_dev_s *dev, +static void stm32_tim_enableint(struct stm32_tim_dev_s *dev, int source) { DEBUGASSERT(dev != NULL); - stm32l5_modifyreg16(dev, STM32L5_GTIM_DIER_OFFSET, 0, GTIM_DIER_UIE); + stm32_modifyreg16(dev, STM32_GTIM_DIER_OFFSET, 0, GTIM_DIER_UIE); } /**************************************************************************** - * Name: stm32l5_tim_disableint + * Name: stm32_tim_disableint ****************************************************************************/ -static void stm32l5_tim_disableint(struct stm32l5_tim_dev_s *dev, +static void stm32_tim_disableint(struct stm32_tim_dev_s *dev, int source) { DEBUGASSERT(dev != NULL); - stm32l5_modifyreg16(dev, STM32L5_GTIM_DIER_OFFSET, GTIM_DIER_UIE, 0); + stm32_modifyreg16(dev, STM32_GTIM_DIER_OFFSET, GTIM_DIER_UIE, 0); } /**************************************************************************** - * Name: stm32l5_tim_ackint + * Name: stm32_tim_ackint ****************************************************************************/ -static void stm32l5_tim_ackint(struct stm32l5_tim_dev_s *dev, int source) +static void stm32_tim_ackint(struct stm32_tim_dev_s *dev, int source) { - stm32l5_putreg16(dev, STM32L5_GTIM_SR_OFFSET, ~GTIM_SR_UIF); + stm32_putreg16(dev, STM32_GTIM_SR_OFFSET, ~GTIM_SR_UIF); } /**************************************************************************** - * Name: stm32l5_tim_checkint + * Name: stm32_tim_checkint ****************************************************************************/ -static int stm32l5_tim_checkint(struct stm32l5_tim_dev_s *dev, +static int stm32_tim_checkint(struct stm32_tim_dev_s *dev, int source) { - uint16_t regval = stm32l5_getreg16(dev, STM32L5_GTIM_SR_OFFSET); + uint16_t regval = stm32_getreg16(dev, STM32_GTIM_SR_OFFSET); return (regval & GTIM_SR_UIF) ? 1 : 0; } @@ -1498,90 +1498,90 @@ static int stm32l5_tim_checkint(struct stm32l5_tim_dev_s *dev, ****************************************************************************/ /**************************************************************************** - * Name: stm32l5_tim_init + * Name: stm32_tim_init ****************************************************************************/ -struct stm32l5_tim_dev_s *stm32l5_tim_init(int timer) +struct stm32_tim_dev_s *stm32_tim_init(int timer) { - struct stm32l5_tim_dev_s *dev = NULL; + struct stm32_tim_dev_s *dev = NULL; /* Get structure and enable power */ switch (timer) { -#ifdef CONFIG_STM32L5_TIM1 +#ifdef CONFIG_STM32_TIM1 case 1: - dev = (struct stm32l5_tim_dev_s *)&stm32l5_tim1_priv; - modifyreg32(STM32L5_RCC_APB2ENR, 0, RCC_APB2ENR_TIM1EN); + dev = (struct stm32_tim_dev_s *)&stm32_tim1_priv; + modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM1EN); break; #endif -#ifdef CONFIG_STM32L5_TIM2 +#ifdef CONFIG_STM32_TIM2 case 2: - dev = (struct stm32l5_tim_dev_s *)&stm32l5_tim2_priv; - modifyreg32(STM32L5_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM2EN); + dev = (struct stm32_tim_dev_s *)&stm32_tim2_priv; + modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM2EN); break; #endif -#ifdef CONFIG_STM32L5_TIM3 +#ifdef CONFIG_STM32_TIM3 case 3: - dev = (struct stm32l5_tim_dev_s *)&stm32l5_tim3_priv; - modifyreg32(STM32L5_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM3EN); + dev = (struct stm32_tim_dev_s *)&stm32_tim3_priv; + modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM3EN); break; #endif -#ifdef CONFIG_STM32L5_TIM4 +#ifdef CONFIG_STM32_TIM4 case 4: - dev = (struct stm32l5_tim_dev_s *)&stm32l5_tim4_priv; - modifyreg32(STM32L5_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM4EN); + dev = (struct stm32_tim_dev_s *)&stm32_tim4_priv; + modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM4EN); break; #endif -#ifdef CONFIG_STM32L5_TIM5 +#ifdef CONFIG_STM32_TIM5 case 5: - dev = (struct stm32l5_tim_dev_s *)&stm32l5_tim5_priv; - modifyreg32(STM32L5_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM5EN); + dev = (struct stm32_tim_dev_s *)&stm32_tim5_priv; + modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM5EN); break; #endif -#ifdef CONFIG_STM32L5_TIM6 +#ifdef CONFIG_STM32_TIM6 case 6: - dev = (struct stm32l5_tim_dev_s *)&stm32l5_tim6_priv; - modifyreg32(STM32L5_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM6EN); + dev = (struct stm32_tim_dev_s *)&stm32_tim6_priv; + modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM6EN); break; #endif -#ifdef CONFIG_STM32L5_TIM7 +#ifdef CONFIG_STM32_TIM7 case 7: - dev = (struct stm32l5_tim_dev_s *)&stm32l5_tim7_priv; - modifyreg32(STM32L5_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM7EN); + dev = (struct stm32_tim_dev_s *)&stm32_tim7_priv; + modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM7EN); break; #endif -#ifdef CONFIG_STM32L5_TIM8 +#ifdef CONFIG_STM32_TIM8 case 8: - dev = (struct stm32l5_tim_dev_s *)&stm32l5_tim8_priv; - modifyreg32(STM32L5_RCC_APB2ENR, 0, RCC_APB2ENR_TIM8EN); + dev = (struct stm32_tim_dev_s *)&stm32_tim8_priv; + modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM8EN); break; #endif -#ifdef CONFIG_STM32L5_TIM15 +#ifdef CONFIG_STM32_TIM15 case 15: - dev = (struct stm32l5_tim_dev_s *)&stm32l5_tim15_priv; - modifyreg32(STM32L5_RCC_APB2ENR, 0, RCC_APB2ENR_TIM15EN); + dev = (struct stm32_tim_dev_s *)&stm32_tim15_priv; + modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM15EN); break; #endif -#ifdef CONFIG_STM32L5_TIM16 +#ifdef CONFIG_STM32_TIM16 case 16: - dev = (struct stm32l5_tim_dev_s *)&stm32l5_tim16_priv; - modifyreg32(STM32L5_RCC_APB2ENR, 0, RCC_APB2ENR_TIM16EN); + dev = (struct stm32_tim_dev_s *)&stm32_tim16_priv; + modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM16EN); break; #endif -#ifdef CONFIG_STM32L5_TIM17 +#ifdef CONFIG_STM32_TIM17 case 17: - dev = (struct stm32l5_tim_dev_s *)&stm32l5_tim17_priv; - modifyreg32(STM32L5_RCC_APB2ENR, 0, RCC_APB2ENR_TIM17EN); + dev = (struct stm32_tim_dev_s *)&stm32_tim17_priv; + modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM17EN); break; #endif @@ -1591,93 +1591,93 @@ struct stm32l5_tim_dev_s *stm32l5_tim_init(int timer) /* Is device already allocated */ - if (((struct stm32l5_tim_priv_s *)dev)->mode != STM32L5_TIM_MODE_UNUSED) + if (((struct stm32_tim_priv_s *)dev)->mode != STM32_TIM_MODE_UNUSED) { return NULL; } - stm32l5_tim_reset(dev); + stm32_tim_reset(dev); return dev; } /**************************************************************************** - * Name: stm32l5_tim_deinit + * Name: stm32_tim_deinit * * TODO: Detach interrupts, and close down all TIM Channels * ****************************************************************************/ -int stm32l5_tim_deinit(struct stm32l5_tim_dev_s *dev) +int stm32_tim_deinit(struct stm32_tim_dev_s *dev) { DEBUGASSERT(dev != NULL); /* Disable power */ - switch (((struct stm32l5_tim_priv_s *)dev)->base) + switch (((struct stm32_tim_priv_s *)dev)->base) { -#ifdef CONFIG_STM32L5_TIM1 - case STM32L5_TIM1_BASE: - modifyreg32(STM32L5_RCC_APB2ENR, RCC_APB2ENR_TIM1EN, 0); +#ifdef CONFIG_STM32_TIM1 + case STM32_TIM1_BASE: + modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM1EN, 0); break; #endif -#ifdef CONFIG_STM32L5_TIM2 - case STM32L5_TIM2_BASE: - modifyreg32(STM32L5_RCC_APB1ENR1, RCC_APB1ENR1_TIM2EN, 0); +#ifdef CONFIG_STM32_TIM2 + case STM32_TIM2_BASE: + modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM2EN, 0); break; #endif -#ifdef CONFIG_STM32L5_TIM3 - case STM32L5_TIM3_BASE: - modifyreg32(STM32L5_RCC_APB1ENR1, RCC_APB1ENR1_TIM3EN, 0); +#ifdef CONFIG_STM32_TIM3 + case STM32_TIM3_BASE: + modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM3EN, 0); break; #endif -#ifdef CONFIG_STM32L5_TIM4 - case STM32L5_TIM4_BASE: - modifyreg32(STM32L5_RCC_APB1ENR1, RCC_APB1ENR1_TIM4EN, 0); +#ifdef CONFIG_STM32_TIM4 + case STM32_TIM4_BASE: + modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM4EN, 0); break; #endif -#ifdef CONFIG_STM32L5_TIM5 - case STM32L5_TIM5_BASE: - modifyreg32(STM32L5_RCC_APB1ENR1, RCC_APB1ENR1_TIM5EN, 0); +#ifdef CONFIG_STM32_TIM5 + case STM32_TIM5_BASE: + modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM5EN, 0); break; #endif -#ifdef CONFIG_STM32L5_TIM6 - case STM32L5_TIM6_BASE: - modifyreg32(STM32L5_RCC_APB1ENR1, RCC_APB1ENR1_TIM6EN, 0); +#ifdef CONFIG_STM32_TIM6 + case STM32_TIM6_BASE: + modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM6EN, 0); break; #endif -#ifdef CONFIG_STM32L5_TIM7 - case STM32L5_TIM7_BASE: - modifyreg32(STM32L5_RCC_APB1ENR1, RCC_APB1ENR1_TIM7EN, 0); +#ifdef CONFIG_STM32_TIM7 + case STM32_TIM7_BASE: + modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM7EN, 0); break; #endif -#ifdef CONFIG_STM32L5_TIM8 - case STM32L5_TIM8_BASE: - modifyreg32(STM32L5_RCC_APB2ENR, RCC_APB2ENR_TIM8EN, 0); +#ifdef CONFIG_STM32_TIM8 + case STM32_TIM8_BASE: + modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM8EN, 0); break; #endif -#ifdef CONFIG_STM32L5_TIM15 - case STM32L5_TIM15_BASE: - modifyreg32(STM32L5_RCC_APB2ENR, RCC_APB2ENR_TIM15EN, 0); +#ifdef CONFIG_STM32_TIM15 + case STM32_TIM15_BASE: + modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM15EN, 0); break; #endif -#ifdef CONFIG_STM32L5_TIM16 - case STM32L5_TIM16_BASE: - modifyreg32(STM32L5_RCC_APB2ENR, RCC_APB2ENR_TIM16EN, 0); +#ifdef CONFIG_STM32_TIM16 + case STM32_TIM16_BASE: + modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM16EN, 0); break; #endif -#ifdef CONFIG_STM32L5_TIM17 - case STM32L5_TIM17_BASE: - modifyreg32(STM32L5_RCC_APB2ENR, RCC_APB2ENR_TIM17EN, 0); +#ifdef CONFIG_STM32_TIM17 + case STM32_TIM17_BASE: + modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM17EN, 0); break; #endif @@ -1687,9 +1687,9 @@ int stm32l5_tim_deinit(struct stm32l5_tim_dev_s *dev) /* Mark it as free */ - ((struct stm32l5_tim_priv_s *)dev)->mode = STM32L5_TIM_MODE_UNUSED; + ((struct stm32_tim_priv_s *)dev)->mode = STM32_TIM_MODE_UNUSED; return OK; } -#endif /* defined(CONFIG_STM32L5_TIM1 || ... || TIM17) */ +#endif /* defined(CONFIG_STM32_TIM1 || ... || TIM17) */ diff --git a/arch/arm/src/stm32l5/stm32l5_tim.h b/arch/arm/src/stm32l5/stm32l5_tim.h index f114ff9c6183c..10218a23018a2 100644 --- a/arch/arm/src/stm32l5/stm32l5_tim.h +++ b/arch/arm/src/stm32l5/stm32l5_tim.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32L5_STM32L5_TIM_H -#define __ARCH_ARM_SRC_STM32L5_STM32L5_TIM_H +#ifndef __ARCH_ARM_SRC_STM32L5_STM32_TIM_H +#define __ARCH_ARM_SRC_STM32L5_STM32_TIM_H /**************************************************************************** * Included Files @@ -38,20 +38,20 @@ /* Helpers ******************************************************************/ -#define STM32L5_TIM_SETMODE(d,mode) ((d)->ops->setmode(d,mode)) -#define STM32L5_TIM_SETCLOCK(d,freq) ((d)->ops->setclock(d,freq)) -#define STM32L5_TIM_GETCLOCK(d) ((d)->ops->getclock(d)) -#define STM32L5_TIM_SETPERIOD(d,period) ((d)->ops->setperiod(d,period)) -#define STM32L5_TIM_GETPERIOD(d) ((d)->ops->getperiod(d)) -#define STM32L5_TIM_GETCOUNTER(d) ((d)->ops->getcounter(d)) -#define STM32L5_TIM_SETCHANNEL(d,ch,mode) ((d)->ops->setchannel(d,ch,mode)) -#define STM32L5_TIM_SETCOMPARE(d,ch,comp) ((d)->ops->setcompare(d,ch,comp)) -#define STM32L5_TIM_GETCAPTURE(d,ch) ((d)->ops->getcapture(d,ch)) -#define STM32L5_TIM_SETISR(d,hnd,arg,s) ((d)->ops->setisr(d,hnd,arg,s)) -#define STM32L5_TIM_ENABLEINT(d,s) ((d)->ops->enableint(d,s)) -#define STM32L5_TIM_DISABLEINT(d,s) ((d)->ops->disableint(d,s)) -#define STM32L5_TIM_ACKINT(d,s) ((d)->ops->ackint(d,s)) -#define STM32L5_TIM_CHECKINT(d,s) ((d)->ops->checkint(d,s)) +#define STM32_TIM_SETMODE(d,mode) ((d)->ops->setmode(d,mode)) +#define STM32_TIM_SETCLOCK(d,freq) ((d)->ops->setclock(d,freq)) +#define STM32_TIM_GETCLOCK(d) ((d)->ops->getclock(d)) +#define STM32_TIM_SETPERIOD(d,period) ((d)->ops->setperiod(d,period)) +#define STM32_TIM_GETPERIOD(d) ((d)->ops->getperiod(d)) +#define STM32_TIM_GETCOUNTER(d) ((d)->ops->getcounter(d)) +#define STM32_TIM_SETCHANNEL(d,ch,mode) ((d)->ops->setchannel(d,ch,mode)) +#define STM32_TIM_SETCOMPARE(d,ch,comp) ((d)->ops->setcompare(d,ch,comp)) +#define STM32_TIM_GETCAPTURE(d,ch) ((d)->ops->getcapture(d,ch)) +#define STM32_TIM_SETISR(d,hnd,arg,s) ((d)->ops->setisr(d,hnd,arg,s)) +#define STM32_TIM_ENABLEINT(d,s) ((d)->ops->enableint(d,s)) +#define STM32_TIM_DISABLEINT(d,s) ((d)->ops->disableint(d,s)) +#define STM32_TIM_ACKINT(d,s) ((d)->ops->ackint(d,s)) +#define STM32_TIM_CHECKINT(d,s) ((d)->ops->checkint(d,s)) #define STM32_TIM_ENABLE(d) ((d)->ops->enable(d)) #define STM32_TIM_DISABLE(d) ((d)->ops->disable(d)) @@ -72,43 +72,43 @@ extern "C" /* TIM Device Structure */ -struct stm32l5_tim_dev_s +struct stm32_tim_dev_s { - struct stm32l5_tim_ops_s *ops; + struct stm32_tim_ops_s *ops; }; /* TIM Modes of Operation */ -enum stm32l5_tim_mode_e +enum stm32_tim_mode_e { - STM32L5_TIM_MODE_UNUSED = -1, + STM32_TIM_MODE_UNUSED = -1, /* One of the following */ - STM32L5_TIM_MODE_MASK = 0x0310, - STM32L5_TIM_MODE_DISABLED = 0x0000, - STM32L5_TIM_MODE_UP = 0x0100, - STM32L5_TIM_MODE_DOWN = 0x0110, - STM32L5_TIM_MODE_UPDOWN = 0x0200, - STM32L5_TIM_MODE_PULSE = 0x0300, + STM32_TIM_MODE_MASK = 0x0310, + STM32_TIM_MODE_DISABLED = 0x0000, + STM32_TIM_MODE_UP = 0x0100, + STM32_TIM_MODE_DOWN = 0x0110, + STM32_TIM_MODE_UPDOWN = 0x0200, + STM32_TIM_MODE_PULSE = 0x0300, /* One of the following */ - STM32L5_TIM_MODE_CK_INT = 0x0000, + STM32_TIM_MODE_CK_INT = 0x0000, #if 0 - STM32L5_TIM_MODE_CK_INT_TRIG = 0x0400, - STM32L5_TIM_MODE_CK_EXT = 0x0800, - STM32L5_TIM_MODE_CK_EXT_TRIG = 0x0c00, + STM32_TIM_MODE_CK_INT_TRIG = 0x0400, + STM32_TIM_MODE_CK_EXT = 0x0800, + STM32_TIM_MODE_CK_EXT_TRIG = 0x0c00, #endif /* Clock sources, OR'ed with CK_EXT */ #if 0 - STM32L5_TIM_MODE_CK_CHINVALID = 0x0000, - STM32L5_TIM_MODE_CK_CH1 = 0x0001, - STM32L5_TIM_MODE_CK_CH2 = 0x0002, - STM32L5_TIM_MODE_CK_CH3 = 0x0003, - STM32L5_TIM_MODE_CK_CH4 = 0x0004 + STM32_TIM_MODE_CK_CHINVALID = 0x0000, + STM32_TIM_MODE_CK_CH1 = 0x0001, + STM32_TIM_MODE_CK_CH2 = 0x0002, + STM32_TIM_MODE_CK_CH3 = 0x0003, + STM32_TIM_MODE_CK_CH4 = 0x0004 #endif /* Todo: external trigger block */ @@ -116,67 +116,67 @@ enum stm32l5_tim_mode_e /* TIM Channel Modes */ -enum stm32l5_tim_channel_e +enum stm32_tim_channel_e { - STM32L5_TIM_CH_DISABLED = 0x00, + STM32_TIM_CH_DISABLED = 0x00, /* Common configuration */ - STM32L5_TIM_CH_POLARITY_POS = 0x00, - STM32L5_TIM_CH_POLARITY_NEG = 0x01, + STM32_TIM_CH_POLARITY_POS = 0x00, + STM32_TIM_CH_POLARITY_NEG = 0x01, /* MODES: */ - STM32L5_TIM_CH_MODE_MASK = 0x06, + STM32_TIM_CH_MODE_MASK = 0x06, /* Output Compare Modes */ - STM32L5_TIM_CH_OUTPWM = 0x04, /* Enable standard PWM mode, active high when counter < compare */ + STM32_TIM_CH_OUTPWM = 0x04, /* Enable standard PWM mode, active high when counter < compare */ #if 0 - STM32L5_TIM_CH_OUTCOMPARE = 0x06, + STM32_TIM_CH_OUTCOMPARE = 0x06, #endif /* TODO other modes ... as PWM capture, ENCODER and Hall Sensor */ #if 0 - STM32L5_TIM_CH_INCAPTURE = 0x10, - STM32L5_TIM_CH_INPWM = 0x20 - STM32L5_TIM_CH_DRIVE_OC = open collector mode + STM32_TIM_CH_INCAPTURE = 0x10, + STM32_TIM_CH_INPWM = 0x20 + STM32_TIM_CH_DRIVE_OC = open collector mode #endif }; /* TIM Operations */ -struct stm32l5_tim_ops_s +struct stm32_tim_ops_s { /* Basic Timers */ - void (*enable)(struct stm32l5_tim_dev_s *dev); - void (*disable)(struct stm32l5_tim_dev_s *dev); - int (*setmode)(struct stm32l5_tim_dev_s *dev, - enum stm32l5_tim_mode_e mode); - int (*setclock)(struct stm32l5_tim_dev_s *dev, uint32_t freq); - uint32_t (*getclock)(struct stm32l5_tim_dev_s *dev); - void (*setperiod)(struct stm32l5_tim_dev_s *dev, uint32_t period); - uint32_t (*getperiod)(struct stm32l5_tim_dev_s *dev); - uint32_t (*getcounter)(struct stm32l5_tim_dev_s *dev); + void (*enable)(struct stm32_tim_dev_s *dev); + void (*disable)(struct stm32_tim_dev_s *dev); + int (*setmode)(struct stm32_tim_dev_s *dev, + enum stm32_tim_mode_e mode); + int (*setclock)(struct stm32_tim_dev_s *dev, uint32_t freq); + uint32_t (*getclock)(struct stm32_tim_dev_s *dev); + void (*setperiod)(struct stm32_tim_dev_s *dev, uint32_t period); + uint32_t (*getperiod)(struct stm32_tim_dev_s *dev); + uint32_t (*getcounter)(struct stm32_tim_dev_s *dev); /* General and Advanced Timers Adds */ - int (*setchannel)(struct stm32l5_tim_dev_s *dev, uint8_t channel, - enum stm32l5_tim_channel_e mode); - int (*setcompare)(struct stm32l5_tim_dev_s *dev, uint8_t channel, + int (*setchannel)(struct stm32_tim_dev_s *dev, uint8_t channel, + enum stm32_tim_channel_e mode); + int (*setcompare)(struct stm32_tim_dev_s *dev, uint8_t channel, uint32_t compare); - int (*getcapture)(struct stm32l5_tim_dev_s *dev, uint8_t channel); + int (*getcapture)(struct stm32_tim_dev_s *dev, uint8_t channel); /* Timer interrupts */ - int (*setisr)(struct stm32l5_tim_dev_s *dev, + int (*setisr)(struct stm32_tim_dev_s *dev, xcpt_t handler, void *arg, int source); - void (*enableint)(struct stm32l5_tim_dev_s *dev, int source); - void (*disableint)(struct stm32l5_tim_dev_s *dev, int source); - void (*ackint)(struct stm32l5_tim_dev_s *dev, int source); - int (*checkint)(struct stm32l5_tim_dev_s *dev, int source); + void (*enableint)(struct stm32_tim_dev_s *dev, int source); + void (*disableint)(struct stm32_tim_dev_s *dev, int source); + void (*ackint)(struct stm32_tim_dev_s *dev, int source); + int (*checkint)(struct stm32_tim_dev_s *dev, int source); }; /**************************************************************************** @@ -185,14 +185,14 @@ struct stm32l5_tim_ops_s /* Power-up timer and get its structure */ -struct stm32l5_tim_dev_s *stm32l5_tim_init(int timer); +struct stm32_tim_dev_s *stm32_tim_init(int timer); /* Power-down timer, mark it as unused */ -int stm32l5_tim_deinit(struct stm32l5_tim_dev_s *dev); +int stm32_tim_deinit(struct stm32_tim_dev_s *dev); /**************************************************************************** - * Name: stm32l5_timer_initialize + * Name: stm32_timer_initialize * * Description: * Bind the configuration timer to a timer lower half instance and @@ -210,7 +210,7 @@ int stm32l5_tim_deinit(struct stm32l5_tim_dev_s *dev); ****************************************************************************/ #ifdef CONFIG_TIMER -int stm32l5_timer_initialize(const char *devpath, int timer); +int stm32_timer_initialize(const char *devpath, int timer); #endif #undef EXTERN @@ -219,4 +219,4 @@ int stm32l5_timer_initialize(const char *devpath, int timer); #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32L5_STM32L5_TIM_H */ +#endif /* __ARCH_ARM_SRC_STM32L5_STM32_TIM_H */ diff --git a/arch/arm/src/stm32l5/stm32l5_tim_lowerhalf.c b/arch/arm/src/stm32l5/stm32l5_tim_lowerhalf.c index 0d21c17b04906..789b50c7bdc61 100644 --- a/arch/arm/src/stm32l5/stm32l5_tim_lowerhalf.c +++ b/arch/arm/src/stm32l5/stm32l5_tim_lowerhalf.c @@ -41,28 +41,28 @@ #include "stm32l5_tim.h" #if defined(CONFIG_TIMER) && \ - (defined(CONFIG_STM32L5_TIM1) || defined(CONFIG_STM32L5_TIM2) || \ - defined(CONFIG_STM32L5_TIM3) || defined(CONFIG_STM32L5_TIM4) || \ - defined(CONFIG_STM32L5_TIM5) || defined(CONFIG_STM32L5_TIM6) || \ - defined(CONFIG_STM32L5_TIM7) || defined(CONFIG_STM32L5_TIM8) || \ - defined(CONFIG_STM32L5_TIM15) || defined(CONFIG_STM32L5_TIM16) || \ - defined(CONFIG_STM32L5_TIM17)) + (defined(CONFIG_STM32_TIM1) || defined(CONFIG_STM32_TIM2) || \ + defined(CONFIG_STM32_TIM3) || defined(CONFIG_STM32_TIM4) || \ + defined(CONFIG_STM32_TIM5) || defined(CONFIG_STM32_TIM6) || \ + defined(CONFIG_STM32_TIM7) || defined(CONFIG_STM32_TIM8) || \ + defined(CONFIG_STM32_TIM15) || defined(CONFIG_STM32_TIM16) || \ + defined(CONFIG_STM32_TIM17)) /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ -#define STM32L5_TIM1_RES 16 -#define STM32L5_TIM2_RES 32 -#define STM32L5_TIM3_RES 16 -#define STM32L5_TIM4_RES 16 -#define STM32L5_TIM5_RES 32 -#define STM32L5_TIM6_RES 16 -#define STM32L5_TIM7_RES 16 -#define STM32L5_TIM8_RES 16 -#define STM32L5_TIM15_RES 16 -#define STM32L5_TIM16_RES 16 -#define STM32L5_TIM17_RES 16 +#define STM32_TIM1_RES 16 +#define STM32_TIM2_RES 32 +#define STM32_TIM3_RES 16 +#define STM32_TIM4_RES 16 +#define STM32_TIM5_RES 32 +#define STM32_TIM6_RES 16 +#define STM32_TIM7_RES 16 +#define STM32_TIM8_RES 16 +#define STM32_TIM15_RES 16 +#define STM32_TIM16_RES 16 +#define STM32_TIM17_RES 16 /**************************************************************************** * Private Types @@ -73,10 +73,10 @@ * timer_lowerhalf_s structure. */ -struct stm32l5_lowerhalf_s +struct stm32_lowerhalf_s { const struct timer_ops_s *ops; /* Lower half operations */ - struct stm32l5_tim_dev_s *tim; /* stm32 timer driver */ + struct stm32_tim_dev_s *tim; /* stm32 timer driver */ tccb_t callback; /* Current upper half interrupt callback */ void *arg; /* Argument passed to upper half callback */ bool started; /* True: Timer has been started */ @@ -89,17 +89,17 @@ struct stm32l5_lowerhalf_s /* Interrupt handling *******************************************************/ -static int stm32l5_timer_handler(int irq, void *context, void *arg); +static int stm32_timer_handler(int irq, void *context, void *arg); /* "Lower half" driver methods **********************************************/ -static int stm32l5_start(struct timer_lowerhalf_s *lower); -static int stm32l5_stop(struct timer_lowerhalf_s *lower); -static int stm32l5_getstatus(struct timer_lowerhalf_s *lower, +static int stm32_start(struct timer_lowerhalf_s *lower); +static int stm32_stop(struct timer_lowerhalf_s *lower); +static int stm32_getstatus(struct timer_lowerhalf_s *lower, struct timer_status_s *status); -static int stm32l5_settimeout(struct timer_lowerhalf_s *lower, +static int stm32_settimeout(struct timer_lowerhalf_s *lower, uint32_t timeout); -static void stm32l5_setcallback(struct timer_lowerhalf_s *lower, +static void stm32_setcallback(struct timer_lowerhalf_s *lower, tccb_t callback, void *arg); /**************************************************************************** @@ -110,99 +110,99 @@ static void stm32l5_setcallback(struct timer_lowerhalf_s *lower, static const struct timer_ops_s g_timer_ops = { - .start = stm32l5_start, - .stop = stm32l5_stop, - .getstatus = stm32l5_getstatus, - .settimeout = stm32l5_settimeout, - .setcallback = stm32l5_setcallback, + .start = stm32_start, + .stop = stm32_stop, + .getstatus = stm32_getstatus, + .settimeout = stm32_settimeout, + .setcallback = stm32_setcallback, .ioctl = NULL, }; -#ifdef CONFIG_STM32L5_TIM1 -static struct stm32l5_lowerhalf_s g_tim1_lowerhalf = +#ifdef CONFIG_STM32_TIM1 +static struct stm32_lowerhalf_s g_tim1_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32L5_TIM1_RES, + .resolution = STM32_TIM1_RES, }; #endif -#ifdef CONFIG_STM32L5_TIM2 -static struct stm32l5_lowerhalf_s g_tim2_lowerhalf = +#ifdef CONFIG_STM32_TIM2 +static struct stm32_lowerhalf_s g_tim2_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32L5_TIM2_RES, + .resolution = STM32_TIM2_RES, }; #endif -#ifdef CONFIG_STM32L5_TIM3 -static struct stm32l5_lowerhalf_s g_tim3_lowerhalf = +#ifdef CONFIG_STM32_TIM3 +static struct stm32_lowerhalf_s g_tim3_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32L5_TIM3_RES, + .resolution = STM32_TIM3_RES, }; #endif -#ifdef CONFIG_STM32L5_TIM4 -static struct stm32l5_lowerhalf_s g_tim4_lowerhalf = +#ifdef CONFIG_STM32_TIM4 +static struct stm32_lowerhalf_s g_tim4_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32L5_TIM4_RES, + .resolution = STM32_TIM4_RES, }; #endif -#ifdef CONFIG_STM32L5_TIM5 -static struct stm32l5_lowerhalf_s g_tim5_lowerhalf = +#ifdef CONFIG_STM32_TIM5 +static struct stm32_lowerhalf_s g_tim5_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32L5_TIM5_RES, + .resolution = STM32_TIM5_RES, }; #endif -#ifdef CONFIG_STM32L5_TIM6 -static struct stm32l5_lowerhalf_s g_tim6_lowerhalf = +#ifdef CONFIG_STM32_TIM6 +static struct stm32_lowerhalf_s g_tim6_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32L5_TIM6_RES, + .resolution = STM32_TIM6_RES, }; #endif -#ifdef CONFIG_STM32L5_TIM7 -static struct stm32l5_lowerhalf_s g_tim7_lowerhalf = +#ifdef CONFIG_STM32_TIM7 +static struct stm32_lowerhalf_s g_tim7_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32L5_TIM7_RES, + .resolution = STM32_TIM7_RES, }; #endif -#ifdef CONFIG_STM32L5_TIM8 -static struct stm32l5_lowerhalf_s g_tim8_lowerhalf = +#ifdef CONFIG_STM32_TIM8 +static struct stm32_lowerhalf_s g_tim8_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32L5_TIM8_RES, + .resolution = STM32_TIM8_RES, }; #endif -#ifdef CONFIG_STM32L5_TIM15 -static struct stm32l5_lowerhalf_s g_tim15_lowerhalf = +#ifdef CONFIG_STM32_TIM15 +static struct stm32_lowerhalf_s g_tim15_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32L5_TIM15_RES, + .resolution = STM32_TIM15_RES, }; #endif -#ifdef CONFIG_STM32L5_TIM16 -static struct stm32l5_lowerhalf_s g_tim16_lowerhalf = +#ifdef CONFIG_STM32_TIM16 +static struct stm32_lowerhalf_s g_tim16_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32L5_TIM16_RES, + .resolution = STM32_TIM16_RES, }; #endif -#ifdef CONFIG_STM32L5_TIM17 -static struct stm32l5_lowerhalf_s g_tim17_lowerhalf = +#ifdef CONFIG_STM32_TIM17 +static struct stm32_lowerhalf_s g_tim17_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32L5_TIM17_RES, + .resolution = STM32_TIM17_RES, }; #endif @@ -211,7 +211,7 @@ static struct stm32l5_lowerhalf_s g_tim17_lowerhalf = ****************************************************************************/ /**************************************************************************** - * Name: stm32l5_timer_handler + * Name: stm32_timer_handler * * Description: * timer interrupt handler @@ -222,31 +222,31 @@ static struct stm32l5_lowerhalf_s g_tim17_lowerhalf = * ****************************************************************************/ -static int stm32l5_timer_handler(int irq, void *context, void *arg) +static int stm32_timer_handler(int irq, void *context, void *arg) { - struct stm32l5_lowerhalf_s *lower = - (struct stm32l5_lowerhalf_s *)arg; + struct stm32_lowerhalf_s *lower = + (struct stm32_lowerhalf_s *)arg; uint32_t next_interval_us = 0; - STM32L5_TIM_ACKINT(lower->tim, 0); + STM32_TIM_ACKINT(lower->tim, 0); if (lower->callback(&next_interval_us, lower->arg)) { if (next_interval_us > 0) { - STM32L5_TIM_SETPERIOD(lower->tim, next_interval_us); + STM32_TIM_SETPERIOD(lower->tim, next_interval_us); } } else { - stm32l5_stop((struct timer_lowerhalf_s *)lower); + stm32_stop((struct timer_lowerhalf_s *)lower); } return OK; } /**************************************************************************** - * Name: stm32l5_start + * Name: stm32_start * * Description: * Start the timer, resetting the time to the current timeout, @@ -260,19 +260,19 @@ static int stm32l5_timer_handler(int irq, void *context, void *arg) * ****************************************************************************/ -static int stm32l5_start(struct timer_lowerhalf_s *lower) +static int stm32_start(struct timer_lowerhalf_s *lower) { - struct stm32l5_lowerhalf_s *priv = - (struct stm32l5_lowerhalf_s *)lower; + struct stm32_lowerhalf_s *priv = + (struct stm32_lowerhalf_s *)lower; if (!priv->started) { - STM32L5_TIM_SETMODE(priv->tim, STM32L5_TIM_MODE_UP); + STM32_TIM_SETMODE(priv->tim, STM32_TIM_MODE_UP); if (priv->callback != NULL) { - STM32L5_TIM_SETISR(priv->tim, stm32l5_timer_handler, priv, 0); - STM32L5_TIM_ENABLEINT(priv->tim, 0); + STM32_TIM_SETISR(priv->tim, stm32_timer_handler, priv, 0); + STM32_TIM_ENABLEINT(priv->tim, 0); } priv->started = true; @@ -285,7 +285,7 @@ static int stm32l5_start(struct timer_lowerhalf_s *lower) } /**************************************************************************** - * Name: stm32l5_stop + * Name: stm32_stop * * Description: * Stop the timer @@ -299,16 +299,16 @@ static int stm32l5_start(struct timer_lowerhalf_s *lower) * ****************************************************************************/ -static int stm32l5_stop(struct timer_lowerhalf_s *lower) +static int stm32_stop(struct timer_lowerhalf_s *lower) { - struct stm32l5_lowerhalf_s *priv = - (struct stm32l5_lowerhalf_s *)lower; + struct stm32_lowerhalf_s *priv = + (struct stm32_lowerhalf_s *)lower; if (priv->started) { - STM32L5_TIM_SETMODE(priv->tim, STM32L5_TIM_MODE_DISABLED); - STM32L5_TIM_DISABLEINT(priv->tim, 0); - STM32L5_TIM_SETISR(priv->tim, NULL, NULL, 0); + STM32_TIM_SETMODE(priv->tim, STM32_TIM_MODE_DISABLED); + STM32_TIM_DISABLEINT(priv->tim, 0); + STM32_TIM_SETISR(priv->tim, NULL, NULL, 0); priv->started = false; return OK; } @@ -319,7 +319,7 @@ static int stm32l5_stop(struct timer_lowerhalf_s *lower) } /**************************************************************************** - * Name: stm32l5_getstatus + * Name: stm32_getstatus * * Description: * get timer status @@ -334,11 +334,11 @@ static int stm32l5_stop(struct timer_lowerhalf_s *lower) * ****************************************************************************/ -static int stm32l5_getstatus(struct timer_lowerhalf_s *lower, +static int stm32_getstatus(struct timer_lowerhalf_s *lower, struct timer_status_s *status) { - struct stm32l5_lowerhalf_s *priv = - (struct stm32l5_lowerhalf_s *)lower; + struct stm32_lowerhalf_s *priv = + (struct stm32_lowerhalf_s *)lower; uint64_t maxtimeout; uint32_t timeout; uint32_t clock; @@ -363,8 +363,8 @@ static int stm32l5_getstatus(struct timer_lowerhalf_s *lower, /* Get timeout */ maxtimeout = (1 << priv->resolution) - 1; - clock = STM32L5_TIM_GETCLOCK(priv->tim); - period = STM32L5_TIM_GETPERIOD(priv->tim); + clock = STM32_TIM_GETCLOCK(priv->tim); + period = STM32_TIM_GETPERIOD(priv->tim); if (clock == 1000000) { @@ -380,13 +380,13 @@ static int stm32l5_getstatus(struct timer_lowerhalf_s *lower, /* Get the time remaining until the timer expires (in microseconds) */ clock_factor = (clock == 1000000) ? 1 : (clock / 1000000); - status->timeleft = (timeout - STM32L5_TIM_GETCOUNTER(priv->tim)) * + status->timeleft = (timeout - STM32_TIM_GETCOUNTER(priv->tim)) * clock_factor; return OK; } /**************************************************************************** - * Name: stm32l5_settimeout + * Name: stm32_settimeout * * Description: * Set a new timeout value (and reset the timer) @@ -401,11 +401,11 @@ static int stm32l5_getstatus(struct timer_lowerhalf_s *lower, * ****************************************************************************/ -static int stm32l5_settimeout(struct timer_lowerhalf_s *lower, +static int stm32_settimeout(struct timer_lowerhalf_s *lower, uint32_t timeout) { - struct stm32l5_lowerhalf_s *priv = - (struct stm32l5_lowerhalf_s *)lower; + struct stm32_lowerhalf_s *priv = + (struct stm32_lowerhalf_s *)lower; uint64_t maxtimeout; if (priv->started) @@ -417,20 +417,20 @@ static int stm32l5_settimeout(struct timer_lowerhalf_s *lower, if (timeout > maxtimeout) { uint64_t freq = (maxtimeout * 1000000) / timeout; - STM32L5_TIM_SETCLOCK(priv->tim, freq); - STM32L5_TIM_SETPERIOD(priv->tim, maxtimeout); + STM32_TIM_SETCLOCK(priv->tim, freq); + STM32_TIM_SETPERIOD(priv->tim, maxtimeout); } else { - STM32L5_TIM_SETCLOCK(priv->tim, 1000000); - STM32L5_TIM_SETPERIOD(priv->tim, timeout); + STM32_TIM_SETCLOCK(priv->tim, 1000000); + STM32_TIM_SETPERIOD(priv->tim, timeout); } return OK; } /**************************************************************************** - * Name: stm32l5_sethandler + * Name: stm32_sethandler * * Description: * Call this user provided timeout handler. @@ -449,11 +449,11 @@ static int stm32l5_settimeout(struct timer_lowerhalf_s *lower, * ****************************************************************************/ -static void stm32l5_setcallback(struct timer_lowerhalf_s *lower, +static void stm32_setcallback(struct timer_lowerhalf_s *lower, tccb_t callback, void *arg) { - struct stm32l5_lowerhalf_s *priv = - (struct stm32l5_lowerhalf_s *)lower; + struct stm32_lowerhalf_s *priv = + (struct stm32_lowerhalf_s *)lower; irqstate_t flags = enter_critical_section(); /* Save the new callback */ @@ -463,13 +463,13 @@ static void stm32l5_setcallback(struct timer_lowerhalf_s *lower, if (callback != NULL && priv->started) { - STM32L5_TIM_SETISR(priv->tim, stm32l5_timer_handler, priv, 0); - STM32L5_TIM_ENABLEINT(priv->tim, 0); + STM32_TIM_SETISR(priv->tim, stm32_timer_handler, priv, 0); + STM32_TIM_ENABLEINT(priv->tim, 0); } else { - STM32L5_TIM_DISABLEINT(priv->tim, 0); - STM32L5_TIM_SETISR(priv->tim, NULL, NULL, 0); + STM32_TIM_DISABLEINT(priv->tim, 0); + STM32_TIM_SETISR(priv->tim, NULL, NULL, 0); } leave_critical_section(flags); @@ -480,7 +480,7 @@ static void stm32l5_setcallback(struct timer_lowerhalf_s *lower, ****************************************************************************/ /**************************************************************************** - * Name: stm32l5_timer_initialize + * Name: stm32_timer_initialize * * Description: * Bind the configuration timer to a timer lower half instance and @@ -497,72 +497,72 @@ static void stm32l5_setcallback(struct timer_lowerhalf_s *lower, * ****************************************************************************/ -int stm32l5_timer_initialize(const char *devpath, int timer) +int stm32_timer_initialize(const char *devpath, int timer) { - struct stm32l5_lowerhalf_s *lower; + struct stm32_lowerhalf_s *lower; switch (timer) { -#ifdef CONFIG_STM32L5_TIM1 +#ifdef CONFIG_STM32_TIM1 case 1: lower = &g_tim1_lowerhalf; break; #endif -#ifdef CONFIG_STM32L5_TIM2 +#ifdef CONFIG_STM32_TIM2 case 2: lower = &g_tim2_lowerhalf; break; #endif -#ifdef CONFIG_STM32L5_TIM3 +#ifdef CONFIG_STM32_TIM3 case 3: lower = &g_tim3_lowerhalf; break; #endif -#ifdef CONFIG_STM32L5_TIM4 +#ifdef CONFIG_STM32_TIM4 case 4: lower = &g_tim4_lowerhalf; break; #endif -#ifdef CONFIG_STM32L5_TIM5 +#ifdef CONFIG_STM32_TIM5 case 5: lower = &g_tim5_lowerhalf; break; #endif -#ifdef CONFIG_STM32L5_TIM6 +#ifdef CONFIG_STM32_TIM6 case 6: lower = &g_tim6_lowerhalf; break; #endif -#ifdef CONFIG_STM32L5_TIM7 +#ifdef CONFIG_STM32_TIM7 case 7: lower = &g_tim7_lowerhalf; break; #endif -#ifdef CONFIG_STM32L5_TIM8 +#ifdef CONFIG_STM32_TIM8 case 8: lower = &g_tim8_lowerhalf; break; #endif -#ifdef CONFIG_STM32L5_TIM15 +#ifdef CONFIG_STM32_TIM15 case 15: lower = &g_tim15_lowerhalf; break; #endif -#ifdef CONFIG_STM32L5_TIM16 +#ifdef CONFIG_STM32_TIM16 case 16: lower = &g_tim16_lowerhalf; break; #endif -#ifdef CONFIG_STM32L5_TIM17 +#ifdef CONFIG_STM32_TIM17 case 17: lower = &g_tim17_lowerhalf; break; @@ -576,7 +576,7 @@ int stm32l5_timer_initialize(const char *devpath, int timer) lower->started = false; lower->callback = NULL; - lower->tim = stm32l5_tim_init(timer); + lower->tim = stm32_tim_init(timer); if (lower->tim == NULL) { diff --git a/arch/arm/src/stm32l5/stm32l5_timerisr.c b/arch/arm/src/stm32l5/stm32l5_timerisr.c index 4ee9481fb829d..0415a3ece422a 100644 --- a/arch/arm/src/stm32l5/stm32l5_timerisr.c +++ b/arch/arm/src/stm32l5/stm32l5_timerisr.c @@ -37,7 +37,7 @@ #include "clock/clock.h" #include "arm_internal.h" #include "chip.h" -#include "stm32l5.h" +#include "stm32.h" /**************************************************************************** * Pre-processor Definitions @@ -58,12 +58,12 @@ * And I don't know now to re-configure it yet */ -#undef CONFIG_STM32L5_SYSTICK_HCLKd8 +#undef CONFIG_STM32_SYSTICK_HCLKd8 -#ifdef CONFIG_STM32L5_SYSTICK_HCLKd8 -# define SYSTICK_RELOAD ((STM32L5_HCLK_FREQUENCY / 8 / CLK_TCK) - 1) +#ifdef CONFIG_STM32_SYSTICK_HCLKd8 +# define SYSTICK_RELOAD ((STM32_HCLK_FREQUENCY / 8 / CLK_TCK) - 1) #else -# define SYSTICK_RELOAD ((STM32L5_HCLK_FREQUENCY / CLK_TCK) - 1) +# define SYSTICK_RELOAD ((STM32_HCLK_FREQUENCY / CLK_TCK) - 1) #endif /* The size of the reload field is 24 bits. Verify that the reload value @@ -79,7 +79,7 @@ ****************************************************************************/ /**************************************************************************** - * Function: stm32l5_timerisr + * Function: stm32_timerisr * * Description: * The timer ISR will perform a variety of services for various portions @@ -87,7 +87,7 @@ * ****************************************************************************/ -static int stm32l5_timerisr(int irq, uint32_t *regs, void *arg) +static int stm32_timerisr(int irq, uint32_t *regs, void *arg) { /* Process timer interrupt */ @@ -123,7 +123,7 @@ void up_timer_initialize(void) #if 0 /* Does not work. Comes up with HCLK source and I can't change it */ regval = getreg32(NVIC_SYSTICK_CTRL); -#ifdef CONFIG_STM32L5_SYSTICK_HCLKd8 +#ifdef CONFIG_STM32_SYSTICK_HCLKd8 regval &= ~NVIC_SYSTICK_CTRL_CLKSOURCE; #else regval |= NVIC_SYSTICK_CTRL_CLKSOURCE; @@ -137,7 +137,7 @@ void up_timer_initialize(void) /* Attach the timer interrupt vector */ - irq_attach(STM32L5_IRQ_SYSTICK, (xcpt_t)stm32l5_timerisr, NULL); + irq_attach(STM32_IRQ_SYSTICK, (xcpt_t)stm32_timerisr, NULL); /* Enable SysTick interrupts */ @@ -146,5 +146,5 @@ void up_timer_initialize(void) /* And enable the timer interrupt */ - up_enable_irq(STM32L5_IRQ_SYSTICK); + up_enable_irq(STM32_IRQ_SYSTICK); } diff --git a/arch/arm/src/stm32l5/stm32l5_uart.h b/arch/arm/src/stm32l5/stm32l5_uart.h index 07fb79ab2bc31..44d48120bdb45 100644 --- a/arch/arm/src/stm32l5/stm32l5_uart.h +++ b/arch/arm/src/stm32l5/stm32l5_uart.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_STC_STM32L5_STM32L5_UART_H -#define __ARCH_ARM_STC_STM32L5_STM32L5_UART_H +#ifndef __ARCH_ARM_SRC_STM32L5_STM32_UART_H +#define __ARCH_ARM_SRC_STM32L5_STM32_UART_H /**************************************************************************** * Included Files @@ -32,7 +32,7 @@ #include "chip.h" -#if defined(CONFIG_STM32L5_STM32L562XX) +#if defined(CONFIG_STM32_STM32L562XX) # include "hardware/stm32l5_uart.h" #else # error "Unsupported STM32L5 chip" @@ -46,63 +46,63 @@ * device. */ -#if !defined(CONFIG_STM32L5_HAVE_UART5) -# undef CONFIG_STM32L5_UART5 +#if !defined(CONFIG_STM32_HAVE_UART5) +# undef CONFIG_STM32_UART5 #endif -#if !defined(CONFIG_STM32L5_HAVE_UART4) -# undef CONFIG_STM32L5_UART4 +#if !defined(CONFIG_STM32_HAVE_UART4) +# undef CONFIG_STM32_UART4 #endif -#if !defined(CONFIG_STM32L5_HAVE_USART3) -# undef CONFIG_STM32L5_USART3 +#if !defined(CONFIG_STM32_HAVE_USART3) +# undef CONFIG_STM32_USART3 #endif -#if !defined(CONFIG_STM32L5_HAVE_USART2) -# undef CONFIG_STM32L5_USART2 +#if !defined(CONFIG_STM32_HAVE_USART2) +# undef CONFIG_STM32_USART2 #endif -#if !defined(CONFIG_STM32L5_HAVE_USART1) -# undef CONFIG_STM32L5_USART1 +#if !defined(CONFIG_STM32_HAVE_USART1) +# undef CONFIG_STM32_USART1 #endif -#if !defined(CONFIG_STM32L5_HAVE_LPUART1) -# undef CONFIG_STM32L5_LPUART1 +#if !defined(CONFIG_STM32_HAVE_LPUART1) +# undef CONFIG_STM32_LPUART1 #endif /* Sanity checks */ -#if !defined(CONFIG_STM32L5_LPUART1) -# undef CONFIG_STM32L5_LPUART1_SERIALDRIVER -# undef CONFIG_STM32L5_LPUART1_1WIREDRIVER +#if !defined(CONFIG_STM32_LPUART1) +# undef CONFIG_STM32_LPUART1_SERIALDRIVER +# undef CONFIG_STM32_LPUART1_1WIREDRIVER #endif -#if !defined(CONFIG_STM32L5_USART1) -# undef CONFIG_STM32L5_USART1_SERIALDRIVER -# undef CONFIG_STM32L5_USART1_1WIREDRIVER +#if !defined(CONFIG_STM32_USART1) +# undef CONFIG_STM32_USART1_SERIALDRIVER +# undef CONFIG_STM32_USART1_1WIREDRIVER #endif -#if !defined(CONFIG_STM32L5_USART2) -# undef CONFIG_STM32L5_USART2_SERIALDRIVER -# undef CONFIG_STM32L5_USART2_1WIREDRIVER +#if !defined(CONFIG_STM32_USART2) +# undef CONFIG_STM32_USART2_SERIALDRIVER +# undef CONFIG_STM32_USART2_1WIREDRIVER #endif -#if !defined(CONFIG_STM32L5_USART3) -# undef CONFIG_STM32L5_USART3_SERIALDRIVER -# undef CONFIG_STM32L5_USART3_1WIREDRIVER +#if !defined(CONFIG_STM32_USART3) +# undef CONFIG_STM32_USART3_SERIALDRIVER +# undef CONFIG_STM32_USART3_1WIREDRIVER #endif -#if !defined(CONFIG_STM32L5_UART4) -# undef CONFIG_STM32L5_UART4_SERIALDRIVER -# undef CONFIG_STM32L5_UART4_1WIREDRIVER +#if !defined(CONFIG_STM32_UART4) +# undef CONFIG_STM32_UART4_SERIALDRIVER +# undef CONFIG_STM32_UART4_1WIREDRIVER #endif -#if !defined(CONFIG_STM32L5_UART5) -# undef CONFIG_STM32L5_UART5_SERIALDRIVER -# undef CONFIG_STM32L5_UART5_1WIREDRIVER +#if !defined(CONFIG_STM32_UART5) +# undef CONFIG_STM32_UART5_SERIALDRIVER +# undef CONFIG_STM32_UART5_1WIREDRIVER #endif /* Is there a USART enabled? */ -#if defined(CONFIG_STM32L5_LPUART1) || defined(CONFIG_STM32L5_USART1) || \ - defined(CONFIG_STM32L5_USART2) || defined(CONFIG_STM32L5_USART3) || \ - defined(CONFIG_STM32L5_UART4) || defined(CONFIG_STM32L5_UART5) +#if defined(CONFIG_STM32_LPUART1) || defined(CONFIG_STM32_USART1) || \ + defined(CONFIG_STM32_USART2) || defined(CONFIG_STM32_USART3) || \ + defined(CONFIG_STM32_UART4) || defined(CONFIG_STM32_UART5) # define HAVE_UART 1 #endif /* Is there a serial console? */ -#if defined(CONFIG_LPUART1_SERIAL_CONSOLE) && defined(CONFIG_STM32L5_LPUART1_SERIALDRIVER) +#if defined(CONFIG_LPUART1_SERIAL_CONSOLE) && defined(CONFIG_STM32_LPUART1_SERIALDRIVER) # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE @@ -110,7 +110,7 @@ # undef CONFIG_UART5_SERIAL_CONSOLE # define CONSOLE_UART 1 # define HAVE_CONSOLE 1 -#elif defined(CONFIG_USART1_SERIAL_CONSOLE) && defined(CONFIG_STM32L5_USART1_SERIALDRIVER) +#elif defined(CONFIG_USART1_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART1_SERIALDRIVER) # undef CONFIG_LPUART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE @@ -118,28 +118,28 @@ # undef CONFIG_UART5_SERIAL_CONSOLE # define CONSOLE_UART 2 # define HAVE_CONSOLE 1 -#elif defined(CONFIG_USART2_SERIAL_CONSOLE) && defined(CONFIG_STM32L5_USART2_SERIALDRIVER) +#elif defined(CONFIG_USART2_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART2_SERIALDRIVER) # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE # undef CONFIG_UART4_SERIAL_CONSOLE # undef CONFIG_UART5_SERIAL_CONSOLE # define CONSOLE_UART 3 # define HAVE_CONSOLE 1 -#elif defined(CONFIG_USART3_SERIAL_CONSOLE) && defined(CONFIG_STM32L5_USART3_SERIALDRIVER) +#elif defined(CONFIG_USART3_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART3_SERIALDRIVER) # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # undef CONFIG_UART4_SERIAL_CONSOLE # undef CONFIG_UART5_SERIAL_CONSOLE # define CONSOLE_UART 4 # define HAVE_CONSOLE 1 -#elif defined(CONFIG_UART4_SERIAL_CONSOLE) && defined(CONFIG_STM32L5_UART4_SERIALDRIVER) +#elif defined(CONFIG_UART4_SERIAL_CONSOLE) && defined(CONFIG_STM32_UART4_SERIALDRIVER) # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE # undef CONFIG_UART5_SERIAL_CONSOLE # define CONSOLE_UART 5 # define HAVE_CONSOLE 1 -#elif defined(CONFIG_UART5_SERIAL_CONSOLE) && defined(CONFIG_STM32L5_UART5_SERIALDRIVER) +#elif defined(CONFIG_UART5_SERIAL_CONSOLE) && defined(CONFIG_STM32_UART5_SERIALDRIVER) # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE @@ -170,27 +170,27 @@ /* Disable the DMA configuration on all unused USARTs */ -#ifndef CONFIG_STM32L5_LPUART1_SERIALDRIVER +#ifndef CONFIG_STM32_LPUART1_SERIALDRIVER # undef CONFIG_LPUART1_RXDMA #endif -#ifndef CONFIG_STM32L5_USART1_SERIALDRIVER +#ifndef CONFIG_STM32_USART1_SERIALDRIVER # undef CONFIG_USART1_RXDMA #endif -#ifndef CONFIG_STM32L5_USART2_SERIALDRIVER +#ifndef CONFIG_STM32_USART2_SERIALDRIVER # undef CONFIG_USART2_RXDMA #endif -#ifndef CONFIG_STM32L5_USART3_SERIALDRIVER +#ifndef CONFIG_STM32_USART3_SERIALDRIVER # undef CONFIG_USART3_RXDMA #endif -#ifndef CONFIG_STM32L5_UART4_SERIALDRIVER +#ifndef CONFIG_STM32_UART4_SERIALDRIVER # undef CONFIG_UART4_RXDMA #endif -#ifndef CONFIG_STM32L5_UART5_SERIALDRIVER +#ifndef CONFIG_STM32_UART5_SERIALDRIVER # undef CONFIG_UART5_RXDMA #endif @@ -223,17 +223,17 @@ /* Is DMA used on all (enabled) USARTs */ #define SERIAL_HAVE_ONLY_DMA 1 -#if defined(CONFIG_STM32L5_LPUART1_SERIALDRIVER) && !defined(CONFIG_LPUART1_RXDMA) +#if defined(CONFIG_STM32_LPUART1_SERIALDRIVER) && !defined(CONFIG_LPUART1_RXDMA) # undef SERIAL_HAVE_ONLY_DMA -#elif defined(CONFIG_STM32L5_USART1_SERIALDRIVER) && !defined(CONFIG_USART1_RXDMA) +#elif defined(CONFIG_STM32_USART1_SERIALDRIVER) && !defined(CONFIG_USART1_RXDMA) # undef SERIAL_HAVE_ONLY_DMA -#elif defined(CONFIG_STM32L5_USART2_SERIALDRIVER) && !defined(CONFIG_USART2_RXDMA) +#elif defined(CONFIG_STM32_USART2_SERIALDRIVER) && !defined(CONFIG_USART2_RXDMA) # undef SERIAL_HAVE_ONLY_DMA -#elif defined(CONFIG_STM32L5_USART3_SERIALDRIVER) && !defined(CONFIG_USART3_RXDMA) +#elif defined(CONFIG_STM32_USART3_SERIALDRIVER) && !defined(CONFIG_USART3_RXDMA) # undef SERIAL_HAVE_ONLY_DMA -#elif defined(CONFIG_STM32L5_UART4_SERIALDRIVER) && !defined(CONFIG_UART4_RXDMA) +#elif defined(CONFIG_STM32_UART4_SERIALDRIVER) && !defined(CONFIG_UART4_RXDMA) # undef SERIAL_HAVE_ONLY_DMA -#elif defined(CONFIG_STM32L5_UART5_SERIALDRIVER) && !defined(CONFIG_UART5_RXDMA) +#elif defined(CONFIG_STM32_UART5_SERIALDRIVER) && !defined(CONFIG_UART5_RXDMA) # undef SERIAL_HAVE_ONLY_DMA #endif @@ -275,7 +275,7 @@ extern "C" ****************************************************************************/ /**************************************************************************** - * Name: stm32l5_serial_dma_poll + * Name: stm32_serial_dma_poll * * Description: * Must be called periodically if any STM32 UART is configured for DMA. @@ -288,7 +288,7 @@ extern "C" ****************************************************************************/ #ifdef SERIAL_HAVE_DMA -void stm32l5_serial_dma_poll(void); +void stm32_serial_dma_poll(void); #endif #undef EXTERN @@ -297,4 +297,4 @@ void stm32l5_serial_dma_poll(void); #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_STC_STM32L5_STM32L5_UART_H */ +#endif /* __ARCH_ARM_SRC_STM32L5_STM32_UART_H */ diff --git a/arch/arm/src/stm32l5/stm32l5_uid.c b/arch/arm/src/stm32l5/stm32l5_uid.c deleted file mode 100644 index e8242cd559faf..0000000000000 --- a/arch/arm/src/stm32l5/stm32l5_uid.c +++ /dev/null @@ -1,48 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32l5/stm32l5_uid.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "hardware/stm32l5_memorymap.h" -#include "stm32l5_uid.h" - -#ifdef STM32L5_SYSMEM_UID - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -void stm32l5_get_uniqueid(uint8_t uniqueid[12]) -{ - int i; - - for (i = 0; i < 12; i++) - { - uniqueid[i] = *((uint8_t *)(STM32L5_SYSMEM_UID) + i); - } -} - -#endif /* STM32L5_SYSMEM_UID */ diff --git a/arch/arm/src/stm32l5/stm32l5_uid.h b/arch/arm/src/stm32l5/stm32l5_uid.h deleted file mode 100644 index 6113ef1edd0de..0000000000000 --- a/arch/arm/src/stm32l5/stm32l5_uid.h +++ /dev/null @@ -1,38 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32l5/stm32l5_uid.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32L5_STM32L5_UID_H -#define __ARCH_ARM_SRC_STM32L5_STM32L5_UID_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -void stm32l5_get_uniqueid(uint8_t uniqueid[12]); - -#endif /* __ARCH_ARM_SRC_STM32L5_STM32L5_UID_H */ diff --git a/arch/arm/src/stm32l5/stm32l5_userspace.c b/arch/arm/src/stm32l5/stm32l5_userspace.c index 7b97d5b6b64d7..bd7d6944ab8d6 100644 --- a/arch/arm/src/stm32l5/stm32l5_userspace.c +++ b/arch/arm/src/stm32l5/stm32l5_userspace.c @@ -41,7 +41,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32l5_userspace + * Name: stm32_userspace * * Description: * For the case of the separate user-/kernel-space build, perform whatever @@ -51,7 +51,7 @@ * ****************************************************************************/ -void stm32l5_userspace(void) +void stm32_userspace(void) { uint8_t *src; uint8_t *dest; @@ -87,7 +87,7 @@ void stm32l5_userspace(void) /* Configure the MPU to permit user-space access to its FLASH and RAM */ - stm32l5_mpuinitialize(); + stm32_mpuinitialize(); } #endif /* CONFIG_BUILD_PROTECTED */ diff --git a/arch/arm/src/stm32l5/stm32l5_userspace.h b/arch/arm/src/stm32l5/stm32l5_userspace.h index 0e6d63d68a69e..bbde34cefc392 100644 --- a/arch/arm/src/stm32l5/stm32l5_userspace.h +++ b/arch/arm/src/stm32l5/stm32l5_userspace.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32L5_STM32L5_USERSPACE_H -#define __ARCH_ARM_SRC_STM32L5_STM32L5_USERSPACE_H +#ifndef __ARCH_ARM_SRC_STM32L5_STM32_USERSPACE_H +#define __ARCH_ARM_SRC_STM32L5_STM32_USERSPACE_H /**************************************************************************** * Included Files @@ -34,7 +34,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32l5_userspace + * Name: stm32_userspace * * Description: * For the case of the separate user-/kernel-space build, perform whatever @@ -45,7 +45,7 @@ ****************************************************************************/ #ifdef CONFIG_BUILD_PROTECTED -void stm32l5_userspace(void); +void stm32_userspace(void); #endif -#endif /* __ARCH_ARM_SRC_STM32L5_STM32L5_USERSPACE_H */ +#endif /* __ARCH_ARM_SRC_STM32L5_STM32_USERSPACE_H */ diff --git a/arch/arm/src/stm32l5/stm32l5_waste.c b/arch/arm/src/stm32l5/stm32l5_waste.c deleted file mode 100644 index 7a6a60bc8e64b..0000000000000 --- a/arch/arm/src/stm32l5/stm32l5_waste.c +++ /dev/null @@ -1,44 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32l5/stm32l5_waste.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include -#include "stm32l5_waste.h" - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -uint32_t idle_wastecounter = 0; - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -void stm32l5_waste(void) -{ - idle_wastecounter++; -} diff --git a/arch/arm/src/stm32l5/stm32l5_waste.h b/arch/arm/src/stm32l5/stm32l5_waste.h deleted file mode 100644 index e9fe2209dfc37..0000000000000 --- a/arch/arm/src/stm32l5/stm32l5_waste.h +++ /dev/null @@ -1,66 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32l5/stm32l5_waste.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32L5_STM32L5_WASTE_H -#define __ARCH_ARM_SRC_STM32L5_STM32L5_WASTE_H - -/* Waste CPU Time */ - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#ifndef __ASSEMBLY__ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/* Waste CPU Time - * - * stm32l5_waste() is the logic that will be executed when portions of kernel - * or user-app is polling some register or similar, waiting for desired - * status. This time is wasted away. This function offers a measure of badly - * written piece of software or some undesired behavior. - * - * At the same time this function adds to some IDLE time which portion - * cannot be used for other purposes (yet). - */ - -void stm32l5_waste(void); - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32L5_STM32L5_WASTE_H */ diff --git a/arch/arm/src/stm32n6/CMakeLists.txt b/arch/arm/src/stm32n6/CMakeLists.txt index afb34a68903ba..cd2b788424dfa 100644 --- a/arch/arm/src/stm32n6/CMakeLists.txt +++ b/arch/arm/src/stm32n6/CMakeLists.txt @@ -39,13 +39,13 @@ if(NOT CONFIG_ARCH_IDLE_CUSTOM) list(APPEND SRCS stm32_idle.c) endif() -if(CONFIG_STM32N6_USART) +if(CONFIG_STM32_USART) list(APPEND SRCS stm32_serial.c) endif() # Chip-specific RCC -if(CONFIG_STM32N6_STM32N6XXXX) +if(CONFIG_STM32_STM32N6XXXX) list(APPEND SRCS stm32n6xx_rcc.c) endif() diff --git a/arch/arm/src/stm32n6/Kconfig b/arch/arm/src/stm32n6/Kconfig index 2e362795f5c79..b90a6b0663c17 100644 --- a/arch/arm/src/stm32n6/Kconfig +++ b/arch/arm/src/stm32n6/Kconfig @@ -1,27 +1,18 @@ -# arch/arm/src/stm32n6/Kconfig # -# SPDX-License-Identifier: Apache-2.0 +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. # -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. if ARCH_CHIP_STM32N6 comment "STM32N6 Configuration Options" -config STM32N6_STM32N6XXXX +config STM32_N6_PERIPHERALS + bool + default y + select STM32_HAVE_USART1 + +config STM32_STM32N6XXXX bool default y @@ -32,78 +23,8 @@ choice config ARCH_CHIP_STM32N657X0 bool "STM32N657X0" - select STM32N6_STM32N6XXXX + select STM32_STM32N6XXXX endchoice -menu "STM32N6 Peripheral Selection" - -config STM32N6_USART1 - bool "USART1" - default n - select STM32N6_USART - select USART1_SERIALDRIVER - select STM32N6_USART1_SERIALDRIVER - select ARCH_HAVE_SERIAL_TERMIOS - -config STM32N6_USART1_SERIALDRIVER - bool - default n - -config STM32N6_USART - bool - -if STM32N6_USART - -config STM32N6_SERIAL_DISABLE_REORDERING - bool "Disable reordering of ttySx devices." - depends on STM32N6_USART1 - default n - ---help--- - NuttX per default reorders the serial ports (/dev/ttySx) so that the - console is always on /dev/ttyS0. If more than one UART is in use this - can, however, have the side-effect that all port mappings - (hardware USART1 -> /dev/ttyS0) change if the console is moved to - another UART. This option disables that reordering so port names - stay stable when the console is moved. - -config STM32N6_FLOWCONTROL_BROKEN - bool "Use Software UART RTS flow control" - default n - ---help--- - Enable this option to use software RTS flow control rather than - the hardware RTS line. Useful in cases where the silicon RTS - behaviour does not match the application's needs. - -config STM32N6_SERIALBRK_BSDCOMPAT - bool "Use GPIO to send Break" - default n - ---help--- - Enable this option to send break by reconfiguring TX as a GPIO - held low for the requested duration, matching BSD-compatible - semantics. - -config STM32N6_PM_SERIAL_ACTIVITY - int "PM serial activity" - default 10 - ---help--- - PM activity reported to power management logic on every serial - interrupt. - -endif # STM32N6_USART - -if USART1_SERIALDRIVER - -config USART1_UNCONFIG_RX_ON_CLOSE - bool "Unconfigure USART1 RX pin on close" - default n - -config USART1_UNCONFIG_TX_ON_CLOSE - bool "Unconfigure USART1 TX pin on close" - default n - -endif # USART1_SERIALDRIVER - -endmenu - endif # ARCH_CHIP_STM32N6 diff --git a/arch/arm/src/stm32n6/Make.defs b/arch/arm/src/stm32n6/Make.defs index cecd24bbf69b7..7be078fc1ef00 100644 --- a/arch/arm/src/stm32n6/Make.defs +++ b/arch/arm/src/stm32n6/Make.defs @@ -38,7 +38,7 @@ ifneq ($(CONFIG_ARCH_IDLE_CUSTOM),y) CHIP_CSRCS += stm32_idle.c endif -ifeq ($(CONFIG_STM32N6_USART),y) +ifeq ($(CONFIG_STM32_USART),y) CHIP_CSRCS += stm32_serial.c endif diff --git a/arch/arm/src/stm32n6/stm32_gpio.c b/arch/arm/src/stm32n6/stm32_gpio.c index 4127545303266..c22839ad7812a 100644 --- a/arch/arm/src/stm32n6/stm32_gpio.c +++ b/arch/arm/src/stm32n6/stm32_gpio.c @@ -55,7 +55,7 @@ static spinlock_t g_configgpio_lock = SP_UNLOCKED; * 8-11). Note that there is no GPIOI-M on this chip. */ -const uint32_t g_gpiobase[STM32N6_NPORTS] = +const uint32_t g_gpiobase[STM32_NPORTS] = { STM32_GPIOA_BASE, /* Port A - index 0 */ STM32_GPIOB_BASE, /* Port B - index 1 */ @@ -110,7 +110,7 @@ int stm32_configgpio(uint32_t cfgset) /* Verify that this hardware supports the select GPIO port */ port = (cfgset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; - if (port >= STM32N6_NPORTS) + if (port >= STM32_NPORTS) { return -EINVAL; } @@ -318,7 +318,7 @@ void stm32_gpiowrite(uint32_t pinset, bool value) unsigned int pin; port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; - if (port < STM32N6_NPORTS) + if (port < STM32_NPORTS) { /* Get the port base address */ @@ -358,7 +358,7 @@ bool stm32_gpioread(uint32_t pinset) unsigned int pin; port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; - if (port < STM32N6_NPORTS) + if (port < STM32_NPORTS) { /* Get the port base address */ diff --git a/arch/arm/src/stm32n6/stm32_gpio.h b/arch/arm/src/stm32n6/stm32_gpio.h index 4c32f43d43c2d..64ad271b3f1a4 100644 --- a/arch/arm/src/stm32n6/stm32_gpio.h +++ b/arch/arm/src/stm32n6/stm32_gpio.h @@ -243,7 +243,7 @@ extern "C" /* Base addresses for each GPIO block */ -EXTERN const uint32_t g_gpiobase[STM32N6_NPORTS]; +EXTERN const uint32_t g_gpiobase[STM32_NPORTS]; /**************************************************************************** * Public Function Prototypes diff --git a/arch/arm/src/stm32n6/stm32_serial.c b/arch/arm/src/stm32n6/stm32_serial.c index 220a34dc3acb6..7b053b9820f03 100644 --- a/arch/arm/src/stm32n6/stm32_serial.c +++ b/arch/arm/src/stm32n6/stm32_serial.c @@ -62,8 +62,8 @@ /* Power management definitions */ -#if defined(CONFIG_PM) && !defined(CONFIG_STM32N6_PM_SERIAL_ACTIVITY) -# define CONFIG_STM32N6_PM_SERIAL_ACTIVITY 10 +#if defined(CONFIG_PM) && !defined(CONFIG_STM32_PM_SERIAL_ACTIVITY) +# define CONFIG_STM32_PM_SERIAL_ACTIVITY 10 #endif /* USART Unconfigure bits */ @@ -82,7 +82,7 @@ * See stm32serial_restoreusartint where the masking is done. */ -#ifdef CONFIG_STM32N6_SERIALBRK_BSDCOMPAT +#ifdef CONFIG_STM32_SERIALBRK_BSDCOMPAT # define USART_CR1_IE_BREAK_INPROGRESS_SHFTS 15 # define USART_CR1_IE_BREAK_INPROGRESS (1 << USART_CR1_IE_BREAK_INPROGRESS_SHFTS) #endif @@ -210,14 +210,14 @@ static const struct uart_ops_s g_uart_ops = /* I/O buffers */ -#ifdef CONFIG_STM32N6_USART1_SERIALDRIVER +#ifdef CONFIG_STM32_USART1_SERIALDRIVER static char g_usart1rxbuffer[CONFIG_USART1_RXBUFSIZE]; static char g_usart1txbuffer[CONFIG_USART1_TXBUFSIZE]; #endif /* This describes the state of the STM32N6 USART1 port. */ -#ifdef CONFIG_STM32N6_USART1_SERIALDRIVER +#ifdef CONFIG_STM32_USART1_SERIALDRIVER static struct stm32_serial_s g_usart1priv = { .dev = @@ -274,9 +274,9 @@ static struct stm32_serial_s g_usart1priv = /* This table lets us iterate over the configured USARTs */ static struct stm32_serial_s * const - g_uart_devs[STM32N6_NUSART] = + g_uart_devs[STM32_NUSART] = { -#ifdef CONFIG_STM32N6_USART1_SERIALDRIVER +#ifdef CONFIG_STM32_USART1_SERIALDRIVER [0] = &g_usart1priv, #endif }; @@ -542,7 +542,7 @@ static void stm32serial_setformat(struct uart_dev_s *dev) regval = stm32serial_getreg(priv, STM32_USART_CR3_OFFSET); regval &= ~(USART_CR3_CTSE | USART_CR3_RTSE); -#if defined(CONFIG_SERIAL_IFLOWCONTROL) && !defined(CONFIG_STM32N6_FLOWCONTROL_BROKEN) +#if defined(CONFIG_SERIAL_IFLOWCONTROL) && !defined(CONFIG_STM32_FLOWCONTROL_BROKEN) if (priv->iflow && (priv->rts_gpio != 0)) { regval |= USART_CR3_RTSE; @@ -639,7 +639,7 @@ static void stm32serial_pm_setsuspend(bool suspend) g_serialpm.serial_suspended = suspend; - for (n = 0; n < STM32N6_NUSART; n++) + for (n = 0; n < STM32_NUSART; n++) { struct stm32_serial_s *priv = g_uart_devs[n]; @@ -679,7 +679,7 @@ static void stm32serial_setapbclock(struct uart_dev_s *dev, bool on) { default: return; -#ifdef CONFIG_STM32N6_USART1_SERIALDRIVER +#ifdef CONFIG_STM32_USART1_SERIALDRIVER case STM32_USART1_BASE: rcc_en = RCC_APB2ENR_USART1EN; regaddr_set = STM32_RCC_APB2ENSR; @@ -752,7 +752,7 @@ static int stm32serial_setup(struct uart_dev_s *dev) { uint32_t config = priv->rts_gpio; -#ifdef CONFIG_STM32N6_FLOWCONTROL_BROKEN +#ifdef CONFIG_STM32_FLOWCONTROL_BROKEN /* Instead of letting hw manage this pin, we will bitbang */ config = (config & ~GPIO_MODE_MASK) | GPIO_OUTPUT; @@ -967,8 +967,8 @@ static int stm32serial_interrupt(int irq, void *context, void *arg) /* Report serial activity to the power management logic */ -#if defined(CONFIG_PM) && CONFIG_STM32N6_PM_SERIAL_ACTIVITY > 0 - pm_activity(PM_IDLE_DOMAIN, CONFIG_STM32N6_PM_SERIAL_ACTIVITY); +#if defined(CONFIG_PM) && CONFIG_STM32_PM_SERIAL_ACTIVITY > 0 + pm_activity(PM_IDLE_DOMAIN, CONFIG_STM32_PM_SERIAL_ACTIVITY); #endif /* Loop until there are no characters to be transferred or, @@ -1321,7 +1321,7 @@ static bool stm32serial_rxflowcontrol(struct uart_dev_s *dev, (struct stm32_serial_s *)dev->priv; #if defined(CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS) && \ - defined(CONFIG_STM32N6_FLOWCONTROL_BROKEN) + defined(CONFIG_STM32_FLOWCONTROL_BROKEN) if (priv->iflow && (priv->rts_gpio != 0)) { /* Assert/de-assert nRTS set it high resume/stop sending */ @@ -1434,7 +1434,7 @@ static void stm32serial_txint(struct uart_dev_s *dev, bool enable) #ifndef CONFIG_SUPPRESS_SERIAL_INTS uint16_t ie = priv->ie | USART_CR1_TXEIE; -# ifdef CONFIG_STM32N6_SERIALBRK_BSDCOMPAT +# ifdef CONFIG_STM32_SERIALBRK_BSDCOMPAT if (priv->ie & USART_CR1_IE_BREAK_INPROGRESS) { leave_critical_section(flags); @@ -1559,7 +1559,7 @@ static int stm32serial_pmprepare(struct pm_callback_s *cb, int domain, * buffers. */ - for (n = 0; n < STM32N6_NUSART; n++) + for (n = 0; n < STM32_NUSART; n++) { struct stm32_serial_s *priv = g_uart_devs[n]; @@ -1629,7 +1629,7 @@ void arm_earlyserialinit(void) /* Disable all USART interrupts */ - for (i = 0; i < STM32N6_NUSART; i++) + for (i = 0; i < STM32_NUSART; i++) { if (g_uart_devs[i]) { @@ -1679,7 +1679,7 @@ void arm_serialinit(void) #if CONSOLE_UART > 0 uart_register("/dev/console", &g_uart_devs[CONSOLE_UART - 1]->dev); -#ifndef CONFIG_STM32N6_SERIAL_DISABLE_REORDERING +#ifndef CONFIG_STM32_SERIAL_DISABLE_REORDERING /* If not disabled, register the console UART to ttyS0 and exclude * it from initializing it further down */ @@ -1694,7 +1694,7 @@ void arm_serialinit(void) strlcpy(devname, "/dev/ttySx", sizeof(devname)); - for (i = 0; i < STM32N6_NUSART; i++) + for (i = 0; i < STM32_NUSART; i++) { /* Don't create a device for non-configured ports. */ @@ -1703,7 +1703,7 @@ void arm_serialinit(void) continue; } -#ifndef CONFIG_STM32N6_SERIAL_DISABLE_REORDERING +#ifndef CONFIG_STM32_SERIAL_DISABLE_REORDERING /* Don't create a device for the console - we did that above */ if (g_uart_devs[i]->dev.isconsole) diff --git a/arch/arm/src/stm32n6/stm32_start.c b/arch/arm/src/stm32n6/stm32_start.c index 3c7664921bb21..c0f29e74371d7 100644 --- a/arch/arm/src/stm32n6/stm32_start.c +++ b/arch/arm/src/stm32n6/stm32_start.c @@ -205,7 +205,7 @@ void __start_c(void) STM32_RCC_BUSLPENSR); putreg32(RCC_MEMLPENR_ALLAXISRAM | RCC_MEMLPENR_CACHEAXIRAMLPEN, STM32_RCC_MEMLPENSR); -#ifdef CONFIG_STM32N6_USART1 +#ifdef CONFIG_STM32_USART1 putreg32(RCC_APB2LPENR_USART1LPEN, STM32_RCC_APB2LPENSR); #endif @@ -233,7 +233,7 @@ void __start_c(void) (void)getreg32(STM32_SYSCFG_VDDCCCR); -#ifdef CONFIG_STM32N6_USART1 +#ifdef CONFIG_STM32_USART1 /* Route USART1's kernel clock to HSI so the BRR computation is * independent of any later SYSCLK changes. */ diff --git a/arch/arm/src/stm32n6/stm32_uart.h b/arch/arm/src/stm32n6/stm32_uart.h index 2726f7fffaf25..248e3f7d0af3e 100644 --- a/arch/arm/src/stm32n6/stm32_uart.h +++ b/arch/arm/src/stm32n6/stm32_uart.h @@ -40,20 +40,20 @@ /* Sanity checks */ -#if !defined(CONFIG_STM32N6_USART1) -# undef CONFIG_STM32N6_USART1_SERIALDRIVER -# undef CONFIG_STM32N6_USART1_1WIREDRIVER +#if !defined(CONFIG_STM32_USART1) +# undef CONFIG_STM32_USART1_SERIALDRIVER +# undef CONFIG_STM32_USART1_1WIREDRIVER #endif /* Is there a USART enabled? */ -#if defined(CONFIG_STM32N6_USART1) +#if defined(CONFIG_STM32_USART1) # define HAVE_UART 1 #endif /* Is there a serial console? */ -#if defined(CONFIG_USART1_SERIAL_CONSOLE) && defined(CONFIG_STM32N6_USART1_SERIALDRIVER) +#if defined(CONFIG_USART1_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART1_SERIALDRIVER) # define CONSOLE_UART 1 # define HAVE_CONSOLE 1 #else diff --git a/arch/arm/src/stm32n6/stm32n6xx_rcc.c b/arch/arm/src/stm32n6/stm32n6xx_rcc.c index e1615178a7652..e6ec3cad06790 100644 --- a/arch/arm/src/stm32n6/stm32n6xx_rcc.c +++ b/arch/arm/src/stm32n6/stm32n6xx_rcc.c @@ -93,7 +93,7 @@ static inline void rcc_enableapb2(void) { uint32_t regval = 0; -#ifdef CONFIG_STM32N6_USART1 +#ifdef CONFIG_STM32_USART1 regval |= RCC_APB2ENR_USART1EN; #endif diff --git a/arch/arm/src/stm32u5/CMakeLists.txt b/arch/arm/src/stm32u5/CMakeLists.txt index 73e7173695091..70f5a875c1306 100644 --- a/arch/arm/src/stm32u5/CMakeLists.txt +++ b/arch/arm/src/stm32u5/CMakeLists.txt @@ -30,8 +30,6 @@ set(SRCS stm32_i2c.c stm32_serial.c stm32_start.c - stm32_waste.c - stm32_uid.c stm32_spi.c stm32_lse.c stm32_lsi.c @@ -62,3 +60,5 @@ if(CONFIG_USBDEV) endif() target_sources(arch PRIVATE ${SRCS}) + +add_subdirectory(${NUTTX_DIR}/arch/arm/src/common/stm32 stm32_common) diff --git a/arch/arm/src/stm32u5/Kconfig b/arch/arm/src/stm32u5/Kconfig index 0a6b6cff64f4f..ddd50dece4b7e 100644 --- a/arch/arm/src/stm32u5/Kconfig +++ b/arch/arm/src/stm32u5/Kconfig @@ -7,6 +7,65 @@ if ARCH_CHIP_STM32U5 comment "STM32U5 Configuration Options" +config STM32_U5_PERIPHERALS + bool + default y + select STM32_HAVE_COMP + select STM32_HAVE_CRS + select STM32_HAVE_DAC1 + select STM32_HAVE_DMA2D + select STM32_HAVE_FMAC + select STM32_HAVE_FSMC + select STM32_HAVE_HASH + select STM32_HAVE_I2C1 + select STM32_HAVE_I2C2 + select STM32_HAVE_I2C3 + select STM32_HAVE_I2C4 + select STM32_HAVE_LPTIM1 + select STM32_HAVE_LPUART1 + select STM32_HAVE_OTGFS if STM32_STM32U535XX || CONFIG_STM32_STM32U545XX || STM32_STM32U575XX || STM32_STM32U585XX + select STM32_HAVE_RNG + select STM32_HAVE_SAI1 + select STM32_HAVE_SAI2 + select STM32_HAVE_SDMMC1 + select STM32_HAVE_SDMMC2 + select STM32_HAVE_SPI1 + select STM32_HAVE_SPI2 + select STM32_HAVE_SPI3 + select STM32_HAVE_SYSCFG + select STM32_HAVE_TSC + select STM32_HAVE_UART4 + select STM32_HAVE_UART5 + select STM32_HAVE_USART1 + select STM32_HAVE_USART2 + select STM32_HAVE_USART3 + select STM32_HAVE_GPADMA1 + select STM32_HAVE_MDF1 + select STM32_HAVE_FLASH + select STM32_HAVE_RAMCFG + select STM32_HAVE_GTZC1 + select STM32_HAVE_GTZC2 + select STM32_HAVE_DCACHE1 + select STM32_HAVE_SRAM1 + select STM32_HAVE_SRAM2 + select STM32_HAVE_SRAM3 + select STM32_HAVE_SRAM5 + select STM32_HAVE_DCMI_PSSI + select STM32_HAVE_PKA + select STM32_HAVE_SAES + select STM32_HAVE_OCTOSPIM + select STM32_HAVE_OTFDEC1 + select STM32_HAVE_OTFDEC2 + select STM32_HAVE_OCTOSPI1 + select STM32_HAVE_OCTOSPI2 + select STM32_HAVE_LPGPIO1 + select STM32_HAVE_LPDMA1 + select STM32_HAVE_ADF1 + select STM32_HAVE_UCPD1 + select STM32_HAVE_VREF + select STM32_HAVE_RTCAPB + select STM32_HAVE_IP_WDG_M3M4_V1 + choice prompt "STM32 U5 Chip Selection" default ARCH_CHIP_STM32U585AI @@ -14,15 +73,15 @@ choice config ARCH_CHIP_STM32U585AI bool "STM32U585AI" - select STM32U5_STM32U585XX - select STM32U5_FLASH_CONFIG_I + select STM32_STM32U585XX + select STM32_FLASH_CONFIG_I select STM32U5_IO_CONFIG_A ---help--- STM32 U5 Cortex M33, 2048 Kb FLASH, 768 Kb SRAM config ARCH_CHIP_STM32U5A5ZJT bool "STM32U5A5ZJT" - select STM32U5_STM32U5A5XX + select STM32_STM32U5A5XX select STM32U5_IO_CONFIG_A ---help--- STM32 U5 Cortex M33, 4096 Kb FLASH, 2500 Kb SRAM, tqfp144 @@ -31,3551 +90,115 @@ endchoice # STM32 U5 Chip Selection # Chip families: -config STM32U5_STM32U5A5XX - # STM32U575 and STM32U585 devices documented in RM0456 +# STM32U575 and STM32U585 devices documented in RM0456 +config STM32_STM32U5A5XX bool default n select ARCH_HAVE_FPU - select STM32U5_HAVE_LPUART1 - select STM32U5_HAVE_USART1 - select STM32U5_HAVE_USART2 - select STM32U5_HAVE_USART3 - select STM32U5_HAVE_UART4 - select STM32U5_HAVE_UART5 - -config STM32U5_STM32U585XX - # STM32U575 and STM32U585 devices documented in RM0456 + select STM32_HAVE_AES + select STM32_HAVE_CORDIC + select STM32_HAVE_IP_AES_M3M4_V1 + select STM32_HAVE_IP_CORDIC_M3M4_V1 + select STM32_HAVE_LPUART1 + select STM32_HAVE_USART1 + select STM32_HAVE_USART2 + select STM32_HAVE_USART3 + select STM32_HAVE_UART4 + select STM32_HAVE_UART5 + select STM32_HAVE_FDCAN1 + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM3 + select STM32_HAVE_TIM4 + select STM32_HAVE_TIM5 + select STM32_HAVE_TIM6 + select STM32_HAVE_TIM7 + select STM32_HAVE_TIM8 + select STM32_HAVE_TIM15 + select STM32_HAVE_TIM16 + select STM32_HAVE_TIM17 + select STM32_HAVE_I2C5 + select STM32_HAVE_I2C6 + +# STM32U575 and STM32U585 devices documented in RM0456 +config STM32_STM32U585XX bool default n select ARCH_HAVE_FPU - select STM32U5_HAVE_LPUART1 - select STM32U5_HAVE_USART1 - select STM32U5_HAVE_USART2 - select STM32U5_HAVE_USART3 - select STM32U5_HAVE_UART4 - select STM32U5_HAVE_UART5 - -choice - prompt "Override Flash Size Designator" - depends on ARCH_CHIP_STM32U5 - default STM32U5_FLASH_OVERRIDE_DEFAULT - ---help--- - STM32U5 series parts numbering (sans the package type) ends with a letter - that designates the FLASH size. - - Designator Size in KiB - 8 64 - B 128 - C 256 - E 512 - G 1024 - I 2048 - - This configuration option defaults to using the configuration based on that designator - or the default smaller size if there is no last character designator is present in the - STM32 Chip Selection. - - Examples: - If the STM32U585AI is chosen, the Flash configuration would be 'I', if a variant of - the part with a 1024 KiB Flash is released in the future one could simply select - the 'G' designator here. - - If an STM32U5xxx Series parts is chosen the default Flash configuration will be set - herein and can be changed. - -config STM32U5_FLASH_OVERRIDE_DEFAULT - bool "Default" - -config STM32U5_FLASH_OVERRIDE_8 - bool "8 64 KB" - -config STM32U5_FLASH_OVERRIDE_B - bool "B 128 KB" - -config STM32U5_FLASH_OVERRIDE_C - bool "C 256 KB" - -config STM32U5_FLASH_OVERRIDE_E - bool "E 512 KB" - -config STM32U5_FLASH_OVERRIDE_G - bool "G 1024 KB" - -config STM32U5_FLASH_OVERRIDE_I - bool "I 2048 KB" - -endchoice # "Override Flash Size Designator" - -# Flash configurations - -config STM32U5_FLASH_CONFIG_8 - bool - default n - -config STM32U5_FLASH_CONFIG_B - bool - default n - -config STM32U5_FLASH_CONFIG_C - bool - default n - -config STM32U5_FLASH_CONFIG_E - bool - default n - -config STM32U5_FLASH_CONFIG_G - bool - default n + select STM32_HAVE_AES + select STM32_HAVE_CORDIC + select STM32_HAVE_IP_AES_M3M4_V1 + select STM32_HAVE_IP_CORDIC_M3M4_V1 + select STM32_HAVE_LPUART1 + select STM32_HAVE_USART1 + select STM32_HAVE_USART2 + select STM32_HAVE_USART3 + select STM32_HAVE_UART4 + select STM32_HAVE_UART5 + select STM32_HAVE_FDCAN1 + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM3 + select STM32_HAVE_TIM4 + select STM32_HAVE_TIM5 + select STM32_HAVE_TIM6 + select STM32_HAVE_TIM7 + select STM32_HAVE_TIM8 + select STM32_HAVE_TIM15 + select STM32_HAVE_TIM16 + select STM32_HAVE_TIM17 -config STM32U5_FLASH_CONFIG_I - bool - default n # Pin/package configurations config STM32U5_IO_CONFIG_K + # Package designator K bool default n config STM32U5_IO_CONFIG_T + # Package designator T bool default n config STM32U5_IO_CONFIG_C + # Package designator C bool default n config STM32U5_IO_CONFIG_R + # Package designator R bool default n config STM32U5_IO_CONFIG_J + # Package designator J bool default n config STM32U5_IO_CONFIG_M + # Package designator M bool default n config STM32U5_IO_CONFIG_V + # Package designator V bool default n config STM32U5_IO_CONFIG_Q + # Package designator Q bool default n config STM32U5_IO_CONFIG_Z + # Package designator Z bool default n config STM32U5_IO_CONFIG_A + # Package designator A bool default n -comment "STM32U5 Peripherals" - -menu "STM32U5 Peripheral Support" - -# These "hidden" settings determine is a peripheral option is available for the -# selection MCU - -config STM32U5_HAVE_LPUART1 - bool - default n - -config STM32U5_HAVE_USART1 - bool - default n - -config STM32U5_HAVE_USART2 - bool - default n - -config STM32U5_HAVE_USART3 - bool - default n - -config STM32U5_HAVE_UART4 - bool - default n - -config STM32U5_HAVE_UART5 - bool - default n - -# These "hidden" settings are the OR of individual peripheral selections -# indicating that the general capability is required. - -config STM32U5_SPI - bool - default n - -config STM32U5_PWM - bool - default n - -config STM32U5_USART - bool - default n - -# These are the peripheral selections proper - -comment "AHB1 Peripherals" - -config STM32U5_GPADMA1 - bool "GPADMA1" - default n - -config STM32U5_CORDIC - bool "CORDIC" - default n - -config STM32U5_FMAC - bool "FMAC" - default n - -config STM32U5_MDF1 - bool "MDF1" - default n - -config STM32U5_FLASH - bool "FLASH" - default n - -config STM32U5_CRC - bool "CRC" - default n - -config STM32U5_TSC - bool "TSC" - default n - -config STM32U5_RAMCFG - bool "RAMCFG" - default n - -config STM32U5_DMA2D - bool "DMA2D" - default n - -config STM32U5_GTZC1 - bool "GTZC1" - default n - -config STM32U5_BKPSRAM - bool "BKPSRAM" - default n - -config STM32U5_DCACHE1 - bool "DCACHE1" - default n - -config STM32U5_SRAM1 - bool "SRAM1" - default y - -config STM32U5_SRAM2 - bool "SRAM2" - default n - -config STM32U5_SRAM3 - bool "SRAM3" - default n - depends on STM32U5_STM32U575XX || STM32U5_STM32U585XX || STM32U5_STM32U59XX || STM32U5_STM32U59AXX || \ - STM32U5_STM32U5A5XX || STM32U5_STM32U5A9XX - -config STM32U5_SRAM5 - bool "SRAM5" - default n - depends on STM32U5_STM32U575XX || STM32U5_STM32U585XX || STM32U5_STM32U59XX || STM32U5_STM32U59AXX || \ - STM32U5_STM32U5A5XX || STM32U5_STM32U5A9XX - -comment "SRAM Options" - -config STM32U5_SRAM2_HEAP - bool "SRAM2 is used for heap" - default n - depends on STM32U5_SRAM2 - select STM32U5_SRAM2_INIT - ---help--- - The STM32U5 SRAM2 region has special properties (power, protection, parity) - which may be used by the application for special purposes. But if these - special properties are not needed, it may be instead added to the heap for - use by malloc(). - NOTE: you must also select an appropriate number of memory regions in the - 'Memory Management' section. - -config STM32U5_SRAM2_INIT - bool "SRAM2 is initialized to zero" - default n - depends on STM32U5_SRAM2 - ---help--- - The STM32U5 SRAM2 region has parity checking. However, when the system - powers on, the memory is in an unknown state, and reads from uninitialized - memory can trigger parity faults from the random data. This can be - avoided by first writing to all locations to force the parity into a valid - state. - However, if the SRAM2 is being used for it's battery-backed capability, - this may be undesirable (because it will destroy the contents). In that - case, the board should handle the initialization itself at the appropriate - time. - -config STM32U5_SRAM3_HEAP - bool "SRAM3 is used for heap" - depends on STM32U5_SRAM3 - default n - -config STM32U5_SRAM5_HEAP - bool "SRAM5 is used for heap" - depends on STM32U5_SRAM5 - default n - -comment "AHB2 Peripherals" - -config STM32U5_ADC1 - bool "ADC1" - default n - -config STM32U5_DCMI_PSSI - bool "DCMI_PSSI" - default n - -config STM32U5_OTGFS - bool "OTG FS" - depends on STM32U5_STM32U535XX || CONFIG_STM32U5_STM32U545XX || STM32U5_STM32U575XX || STM32U5_STM32U585XX - default n - -config STM32U5_OTGHS - bool "OTG HS" - depends on STM32U5_STM32U59XX || STM32U5_STM32U59AXX || STM32U5_STM32U5A5XX || STM32U5_STM32U5A9XX - default n - -config STM32U5_AES - bool "AES" - default n - -config STM32U5_HASH - bool "HASH" - default n - -config STM32U5_RNG - bool "RNG" - default n - -config STM32U5_PKA - bool "PKA" - default n - -config STM32U5_SAES - bool "SAES" - default n - -config STM32U5_OCTOSPIM - bool "OCTOSPIM" - default n - -config STM32U5_OTFDEC1 - bool "OTFDEC1" - default n - -config STM32U5_OTFDEC2 - bool "OTFDEC2" - default n - -config STM32U5_SDMMC1 - bool "SDMMC1" - default n - -config STM32U5_SDMMC2 - bool "SDMMC2" - default n - -config STM32U5_FSMC - bool "FSMC" - default n - -config STM32U5_OCTOSPI1 - bool "OCTOSPI1" - default n - -config STM32U5_OCTOSPI2 - bool "OCTOSPI2" - default n - -comment "AHB3 Peripherals" - -config STM32U5_LPGPIO1 - bool "LPGPIO1" - default n - -config STM32U5_PWR - bool "PWR" - default n - -config STM32U5_ADC4 - bool "ADC4" - default n - -config STM32U5_DAC1 - bool "DAC1" - default n - -config STM32U5_LPDMA1 - bool "LPDMA1" - default n - -config STM32U5_ADF1 - bool "ADF1" - default n - -config STM32U5_GTZC2 - bool "GTZC2" - default n - -comment "APB1 Peripherals" - -config STM32U5_TIM2 - bool "TIM2" - default n - -config STM32U5_TIM3 - bool "TIM3" - default n - -config STM32U5_TIM4 - bool "TIM4" - default n - -config STM32U5_TIM5 - bool "TIM5" - default n - -config STM32U5_TIM6 - bool "TIM6" - default n - -config STM32U5_TIM7 - bool "TIM7" - default n - -config STM32U5_WWDG - bool "WWDG" - default n - -config STM32U5_SPI2 - bool "SPI2" - default n - select SPI - select STM32U5_SPI - -config STM32U5_USART2 - bool "USART2" - default n - select ARCH_HAVE_SERIAL_TERMIOS - select STM32U5_USART - -config STM32U5_USART3 - bool "USART3" - default n - select ARCH_HAVE_SERIAL_TERMIOS - select STM32U5_USART - -config STM32U5_UART4 - bool "UART4" - default n - select ARCH_HAVE_SERIAL_TERMIOS - select STM32U5_USART - -config STM32U5_UART5 - bool "UART5" - default n - select ARCH_HAVE_SERIAL_TERMIOS - select STM32U5_USART - -config STM32U5_I2C1 - bool "I2C1" - default n - select STM32U5_I2C - -config STM32U5_I2C2 - bool "I2C2" - default n - select STM32U5_I2C - -config STM32U5_I2C3 - bool "I2C3" - default n - select STM32U5_I2C - -config STM32U5_I2C4 - bool "I2C4" - default n - select STM32U5_I2C - -config STM32U5_I2C5 - bool "I2C5" - depends on STM32U5_STM32U59XX || STM32U5_STM32U59AXX || STM32U5_STM32U5A5XX || STM32U5_STM32U5A9XX - default n - select STM32U5_I2C - -config STM32U5_I2C6 - bool "I2C6" - depends on STM32U5_STM32U59XX || STM32U5_STM32U59AXX || STM32U5_STM32U5A5XX || STM32U5_STM32U5A9XX - default n - select STM32U5_I2C - -config STM32U5_CRS - bool "CRS" - default n - -config STM32U5_LPTIM2 - bool "LPTIM2" - default n - -config STM32U5_FDCAN1 - bool "FDCAN1" - default n - -config STM32U5_UCPD1 - bool "UCPD1" - default n - -comment "APB2 Peripherals" - -config STM32U5_TIM1 - bool "TIM1" - default n - -config STM32U5_SPI1 - bool "SPI1" - default n - select SPI - select STM32U5_SPI - -config STM32U5_TIM8 - bool "TIM8" - default n - -config STM32U5_USART1 - bool "USART1" - default n - select ARCH_HAVE_SERIAL_TERMIOS - select STM32U5_USART - -config STM32U5_TIM15 - bool "TIM15" - default n - -config STM32U5_TIM16 - bool "TIM16" - default n - -config STM32U5_TIM17 - bool "TIM17" - default n - -config STM32U5_SAI1 - bool "SAI1" - default n - -config STM32U5_SAI2 - bool "SAI2" - default n - -comment "APB3 Peripherals" - -config STM32U5_SYSCFG - bool "SYSCFG" - default y - -config STM32U5_SPI3 - bool "SPI3" - default n - select SPI - select STM32U5_SPI - -config STM32U5_LPUART1 - bool "LPUART1" - default n - select ARCH_HAVE_SERIAL_TERMIOS - select STM32U5_USART - -config STM32U5_LPTIM1 - bool "LPTIM1" - default n - -config STM32U5_LPTIM3 - bool "LPTIM3" - default n - -config STM32U5_LPTIM4 - bool "LPTIM4" - default n - -config STM32U5_OPAMP - bool "OPAMP" - default n - -config STM32U5_COMP - bool "COMP" - default n - -config STM32U5_VREF - bool "VREF" - default n - -config STM32U5_RTCAPB - bool "RTCAPB" - default n - -endmenu - -config STM32U5_SAI1PLL - bool "SAI1PLL" - default n - ---help--- - The STM32U5 has a separate PLL for the SAI1 block. - Set this true and provide configuration parameters in - board.h to use this PLL. - -config STM32U5_SAI2PLL - bool "SAI2PLL" - default n - depends on STM32U5_HAVE_SAI2 - ---help--- - The STM32U5 has a separate PLL for the SAI2 block. - Set this true and provide configuration parameters in - board.h to use this PLL. - -config STM32U5_FLASH_PREFETCH - bool "Enable FLASH Pre-fetch" - default y - ---help--- - Enable FLASH prefetch - -config STM32U5_DISABLE_IDLE_SLEEP_DURING_DEBUG - bool "Disable IDLE Sleep (WFI) in debug mode" - default n - ---help--- - In debug configuration, disables the WFI instruction in the IDLE loop - to prevent the JTAG from disconnecting. With some JTAG debuggers, such - as the ST-LINK2 with OpenOCD, if the ARM is put to sleep via the WFI - instruction, the debugger will disconnect, terminating the debug session. - -config ARCH_BOARD_STM32U5_CUSTOM_CLOCKCONFIG - bool "Custom clock configuration" - default n - ---help--- - Enables special, board-specific STM32 clock configuration. - -menu "RTC Configuration" - depends on STM32U5_RTC - -config STM32U5_RTC_MAGIC_REG - int "BKP register" - default 0 - range 0 31 - ---help--- - The BKP register used to store/check the Magic value to determine if - RTC is already setup - -config STM32U5_RTC_MAGIC - hex "RTC Magic 1" - default 0xfacefeed - ---help--- - Value used as Magic to determine if the RTC is already setup - -config STM32U5_RTC_MAGIC_TIME_SET - hex "RTC Magic 2" - default 0xf00dface - ---help--- - Value used as Magic to determine if the RTC has been setup and has - time set - -choice - prompt "RTC clock source" - default STM32U5_RTC_LSECLOCK - depends on STM32U5_RTC - -config STM32U5_RTC_LSECLOCK - bool "LSE clock" - ---help--- - Drive the RTC with the LSE clock - -config STM32U5_RTC_LSICLOCK - bool "LSI clock" - ---help--- - Drive the RTC with the LSI clock - -config STM32U5_RTC_HSECLOCK - bool "HSE clock" - ---help--- - Drive the RTC with the HSE clock, divided down to 1MHz. - -endchoice - -if STM32U5_RTC_LSECLOCK - -config STM32U5_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY - bool "Automatically boost the LSE oscillator drive capability level until it starts-up" - default n - ---help--- - This will cycle through the values from low to high. To avoid - damaging the crystal. We want to use the lowest setting that gets - the OSC running. See app note AN2867 - - 0 = Low drive capability (default) - 1 = Medium low drive capability - 2 = Medium high drive capability - 3 = High drive capability - -config STM32U5_RTC_LSECLOCK_START_DRV_CAPABILITY - int "LSE oscillator drive capability level at LSE start-up" - default 0 - range 0 3 - depends on !STM32U5_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY - ---help--- - 0 = Low drive capability (default) - 1 = Medium low drive capability - 2 = Medium high drive capability - 3 = High drive capability - -config STM32U5_RTC_LSECLOCK_LOWER_RUN_DRV_CAPABILITY - bool "Decrease LSE oscillator drive capability after LSE start-up" - default n - depends on !STM32U5_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY - ---help--- - The LSE oscillator drive capability can remain at the level used - during LSE start-up at run-time, or it can be reduced to the - 'Low drive capability' once the LSE started up successfully. - -endif # STM32U5_RTC_LSECLOCK - -endmenu # RTC Configuration - -menu "Timer Configuration" - -if SCHED_TICKLESS - -config STM32U5_ONESHOT - bool - default y - -config STM32U5_FREERUN - bool - default y - -config STM32U5_TICKLESS_ONESHOT - int "Tickless one-shot timer channel" - default 2 - range 1 8 - depends on STM32U5_ONESHOT - ---help--- - If the Tickless OS feature is enabled, then one clock must be - assigned to provide the one-shot timer needed by the OS. - -config STM32U5_TICKLESS_FREERUN - int "Tickless free-running timer channel" - default 5 - range 1 8 - depends on STM32U5_FREERUN - ---help--- - If the Tickless OS feature is enabled, then one clock must be - assigned to provide the free-running timer needed by the OS. - -endif # SCHED_TICKLESS - -if !SCHED_TICKLESS - -config STM32U5_ONESHOT - bool "TIM one-shot wrapper" - default n - ---help--- - Enable a wrapper around the low level timer/counter functions to - support one-shot timer. - -config STM32U5_FREERUN - bool "TIM free-running wrapper" - default n - ---help--- - Enable a wrapper around the low level timer/counter functions to - support a free-running timer. - -endif # !SCHED_TICKLESS - -config STM32U5_ONESHOT_MAXTIMERS - int "Maximum number of oneshot timers" - default 1 - range 1 8 - depends on STM32U5_ONESHOT - ---help--- - Determines the maximum number of oneshot timers that can be - supported. This setting pre-allocates some minimal support for each - of the timers and places an upper limit on the number of oneshot - timers that you can use. - -config STM32U5_LPTIM1_PWM - bool "LPTIM1 PWM" - default n - depends on STM32U5_LPTIM1 - select PWM - ---help--- - Reserve low-power timer 1 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32U5_LPTIM1 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32U5_LPTIM1_PWM - -choice - prompt "LPTIM1 clock source" - default STM32U5_LPTIM1_CLK_APB1 - -config STM32U5_LPTIM1_CLK_APB1 - bool "Clock LPTIM1 from APB1" - -config STM32U5_LPTIM1_CLK_LSE - bool "Clock LPTIM1 from LSE" - -config STM32U5_LPTIM1_CLK_LSI - bool "Clock LPTIM1 from LSI" - -config STM32U5_LPTIM1_CLK_HSI - bool "Clock LPTIM1 from HSI" -endchoice - -endif # STM32U5_LPTIM1_PWM - -config STM32U5_LPTIM2_PWM - bool "LPTIM2 PWM" - default n - depends on STM32U5_LPTIM2 - select PWM - ---help--- - Reserve low-power timer 2 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32U5_LPTIM2 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32U5_LPTIM2_PWM - -choice - prompt "LPTIM2 clock source" - default STM32U5_LPTIM2_CLK_APB1 - -config STM32U5_LPTIM2_CLK_APB1 - bool "Clock LPTIM2 from APB1" - -config STM32U5_LPTIM2_CLK_LSE - bool "Clock LPTIM2 from LSE" - -config STM32U5_LPTIM2_CLK_LSI - bool "Clock LPTIM2 from LSI" - -config STM32U5_LPTIM2_CLK_HSI - bool "Clock LPTIM2 from HSI" -endchoice - -endif # STM32U5_LPTIM2_PWM - -config STM32U5_TIM1_PWM - bool "TIM1 PWM" - default n - depends on STM32U5_TIM1 - select STM32U5_PWM - ---help--- - Reserve timer 1 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32U5_TIM1 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32U5_TIM1_PWM - -config STM32U5_TIM1_MODE - int "TIM1 Mode" - default 0 - range 0 4 - ---help--- - Specifies the timer mode. - -if STM32U5_PWM_MULTICHAN - -config STM32U5_TIM1_CHANNEL1 - bool "TIM1 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32U5_TIM1_CHANNEL1 - -config STM32U5_TIM1_CH1MODE - int "TIM1 Channel 1 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -config STM32U5_TIM1_CH1OUT - bool "TIM1 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -config STM32U5_TIM1_CH1NOUT - bool "TIM1 Channel 1 Complementary Output" - default n - depends on STM32U5_TIM1_CH1OUT - ---help--- - Enables channel 1 complementary output. - -endif # STM32U5_TIM1_CHANNEL1 - -config STM32U5_TIM1_CHANNEL2 - bool "TIM1 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32U5_TIM1_CHANNEL2 - -config STM32U5_TIM1_CH2MODE - int "TIM1 Channel 2 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -config STM32U5_TIM1_CH2OUT - bool "TIM1 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -config STM32U5_TIM1_CH2NOUT - bool "TIM1 Channel 2 Complemenrary Output" - default n - depends on STM32U5_TIM1_CH2OUT - ---help--- - Enables channel 2 complementary output. - -endif # STM32U5_TIM1_CHANNEL2 - -config STM32U5_TIM1_CHANNEL3 - bool "TIM1 Channel 3" - default n - ---help--- - Enables channel 3. - -if STM32U5_TIM1_CHANNEL3 - -config STM32U5_TIM1_CH3MODE - int "TIM1 Channel 3 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -config STM32U5_TIM1_CH3OUT - bool "TIM1 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -config STM32U5_TIM1_CH3NOUT - bool "TIM1 Channel 3 Complementary Output" - default n - depends on STM32U5_TIM1_CH3OUT - ---help--- - Enables channel 3 complementary output. - -endif # STM32U5_TIM1_CHANNEL3 - -config STM32U5_TIM1_CHANNEL5 - bool "TIM1 Channel 4" - default n - ---help--- - Enables channel 4. - -if STM32U5_TIM1_CHANNEL5 - -config STM32U5_TIM1_CH4MODE - int "TIM1 Channel 4 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -config STM32U5_TIM1_CH4OUT - bool "TIM1 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32U5_TIM1_CHANNEL5 - -endif # STM32U5_PWM_MULTICHAN - -if !STM32U5_PWM_MULTICHAN - -config STM32U5_TIM1_CHANNEL - int "TIM1 PWM Output Channel" - default 1 - range 1 4 - ---help--- - If TIM1 is enabled for PWM usage, you also need specifies the timer output - channel {1,..,4} - -config STM32U5_TIM1_CHMODE - int "TIM1 Channel Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -endif # !STM32U5_PWM_MULTICHAN - -endif # STM32U5_TIM1_PWM - -config STM32U5_TIM2_PWM - bool "TIM2 PWM" - default n - depends on STM32U5_TIM2 - select STM32U5_PWM - ---help--- - Reserve timer 2 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32U5_TIM2 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32U5_TIM2_PWM - -config STM32U5_TIM2_MODE - int "TIM2 Mode" - default 0 - range 0 4 - ---help--- - Specifies the timer mode. - -if STM32U5_PWM_MULTICHAN - -config STM32U5_TIM2_CHANNEL1 - bool "TIM2 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32U5_TIM2_CHANNEL1 - -config STM32U5_TIM2_CH1MODE - int "TIM2 Channel 1 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -config STM32U5_TIM2_CH1OUT - bool "TIM2 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32U5_TIM2_CHANNEL1 - -config STM32U5_TIM2_CHANNEL2 - bool "TIM2 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32U5_TIM2_CHANNEL2 - -config STM32U5_TIM2_CH2MODE - int "TIM2 Channel 2 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -config STM32U5_TIM2_CH2OUT - bool "TIM2 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32U5_TIM2_CHANNEL2 - -config STM32U5_TIM2_CHANNEL3 - bool "TIM2 Channel 3" - default n - ---help--- - Enables channel 3. - -if STM32U5_TIM2_CHANNEL3 - -config STM32U5_TIM2_CH3MODE - int "TIM2 Channel 3 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -config STM32U5_TIM2_CH3OUT - bool "TIM2 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -endif # STM32U5_TIM2_CHANNEL3 - -config STM32U5_TIM2_CHANNEL5 - bool "TIM2 Channel 4" - default n - ---help--- - Enables channel 4. - -if STM32U5_TIM2_CHANNEL5 - -config STM32U5_TIM2_CH4MODE - int "TIM2 Channel 4 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -config STM32U5_TIM2_CH4OUT - bool "TIM2 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32U5_TIM2_CHANNEL5 - -endif # STM32U5_PWM_MULTICHAN - -if !STM32U5_PWM_MULTICHAN - -config STM32U5_TIM2_CHANNEL - int "TIM2 PWM Output Channel" - default 1 - range 1 4 - ---help--- - If TIM2 is enabled for PWM usage, you also need specifies the timer output - channel {1,..,4} - -config STM32U5_TIM2_CHMODE - int "TIM2 Channel Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -endif # !STM32U5_PWM_MULTICHAN - -endif # STM32U5_TIM2_PWM - -config STM32U5_TIM3_PWM - bool "TIM3 PWM" - default n - depends on STM32U5_TIM3 - select STM32U5_PWM - ---help--- - Reserve timer 3 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32U5_TIM3 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32U5_TIM3_PWM - -config STM32U5_TIM3_MODE - int "TIM3 Mode" - default 0 - range 0 4 - ---help--- - Specifies the timer mode. - -if STM32U5_PWM_MULTICHAN - -config STM32U5_TIM3_CHANNEL1 - bool "TIM3 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32U5_TIM3_CHANNEL1 - -config STM32U5_TIM3_CH1MODE - int "TIM3 Channel 1 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -config STM32U5_TIM3_CH1OUT - bool "TIM3 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32U5_TIM3_CHANNEL1 - -config STM32U5_TIM3_CHANNEL2 - bool "TIM3 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32U5_TIM3_CHANNEL2 - -config STM32U5_TIM3_CH2MODE - int "TIM3 Channel 2 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -config STM32U5_TIM3_CH2OUT - bool "TIM3 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32U5_TIM3_CHANNEL2 - -config STM32U5_TIM3_CHANNEL3 - bool "TIM3 Channel 3" - default n - ---help--- - Enables channel 3. - -if STM32U5_TIM3_CHANNEL3 - -config STM32U5_TIM3_CH3MODE - int "TIM3 Channel 3 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -config STM32U5_TIM3_CH3OUT - bool "TIM3 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -endif # STM32U5_TIM3_CHANNEL3 - -config STM32U5_TIM3_CHANNEL5 - bool "TIM3 Channel 4" - default n - ---help--- - Enables channel 4. - -if STM32U5_TIM3_CHANNEL5 - -config STM32U5_TIM3_CH4MODE - int "TIM3 Channel 4 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -config STM32U5_TIM3_CH4OUT - bool "TIM3 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32U5_TIM3_CHANNEL5 - -endif # STM32U5_PWM_MULTICHAN - -if !STM32U5_PWM_MULTICHAN - -config STM32U5_TIM3_CHANNEL - int "TIM3 PWM Output Channel" - default 1 - range 1 4 - ---help--- - If TIM3 is enabled for PWM usage, you also need specifies the timer output - channel {1,..,4} - -config STM32U5_TIM3_CHMODE - int "TIM3 Channel Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -endif # !STM32U5_PWM_MULTICHAN - -endif # STM32U5_TIM3_PWM - -config STM32U5_TIM4_PWM - bool "TIM4 PWM" - default n - depends on STM32U5_TIM4 - select STM32U5_PWM - ---help--- - Reserve timer 4 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32U5_TIM4 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32U5_TIM4_PWM - -config STM32U5_TIM4_MODE - int "TIM4 Mode" - default 0 - range 0 4 - ---help--- - Specifies the timer mode. - -if STM32U5_PWM_MULTICHAN - -config STM32U5_TIM4_CHANNEL1 - bool "TIM4 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32U5_TIM4_CHANNEL1 - -config STM32U5_TIM4_CH1MODE - int "TIM4 Channel 1 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -config STM32U5_TIM4_CH1OUT - bool "TIM4 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32U5_TIM4_CHANNEL1 - -config STM32U5_TIM4_CHANNEL2 - bool "TIM4 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32U5_TIM4_CHANNEL2 - -config STM32U5_TIM4_CH2MODE - int "TIM4 Channel 2 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -config STM32U5_TIM4_CH2OUT - bool "TIM4 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32U5_TIM4_CHANNEL2 - -config STM32U5_TIM4_CHANNEL3 - bool "TIM4 Channel 3" - default n - ---help--- - Enables channel 3. - -if STM32U5_TIM4_CHANNEL3 - -config STM32U5_TIM4_CH3MODE - int "TIM4 Channel 3 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -config STM32U5_TIM4_CH3OUT - bool "TIM4 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -endif # STM32U5_TIM4_CHANNEL3 - -config STM32U5_TIM4_CHANNEL5 - bool "TIM4 Channel 4" - default n - ---help--- - Enables channel 4. - -if STM32U5_TIM4_CHANNEL5 - -config STM32U5_TIM4_CH4MODE - int "TIM4 Channel 4 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -config STM32U5_TIM4_CH4OUT - bool "TIM4 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32U5_TIM4_CHANNEL5 - -endif # STM32U5_PWM_MULTICHAN - -if !STM32U5_PWM_MULTICHAN - -config STM32U5_TIM4_CHANNEL - int "TIM4 PWM Output Channel" - default 1 - range 1 4 - ---help--- - If TIM4 is enabled for PWM usage, you also need specifies the timer output - channel {1,..,4} - -config STM32U5_TIM4_CHMODE - int "TIM4 Channel Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -endif # !STM32U5_PWM_MULTICHAN - -endif # STM32U5_TIM4_PWM - -config STM32U5_TIM5_PWM - bool "TIM5 PWM" - default n - depends on STM32U5_TIM5 - select STM32U5_PWM - ---help--- - Reserve timer 5 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32U5_TIM5 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32U5_TIM5_PWM - -config STM32U5_TIM5_MODE - int "TIM5 Mode" - default 0 - range 0 4 - ---help--- - Specifies the timer mode. - -if STM32U5_PWM_MULTICHAN - -config STM32U5_TIM5_CHANNEL1 - bool "TIM5 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32U5_TIM5_CHANNEL1 - -config STM32U5_TIM5_CH1MODE - int "TIM5 Channel 1 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -config STM32U5_TIM5_CH1OUT - bool "TIM5 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32U5_TIM5_CHANNEL1 - -config STM32U5_TIM5_CHANNEL2 - bool "TIM5 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32U5_TIM5_CHANNEL2 - -config STM32U5_TIM5_CH2MODE - int "TIM5 Channel 2 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -config STM32U5_TIM5_CH2OUT - bool "TIM5 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32U5_TIM5_CHANNEL2 - -config STM32U5_TIM5_CHANNEL3 - bool "TIM5 Channel 3" - default n - ---help--- - Enables channel 3. - -if STM32U5_TIM5_CHANNEL3 - -config STM32U5_TIM5_CH3MODE - int "TIM5 Channel 3 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -config STM32U5_TIM5_CH3OUT - bool "TIM5 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -endif # STM32U5_TIM5_CHANNEL3 - -config STM32U5_TIM5_CHANNEL5 - bool "TIM5 Channel 4" - default n - ---help--- - Enables channel 4. - -if STM32U5_TIM5_CHANNEL5 - -config STM32U5_TIM5_CH4MODE - int "TIM5 Channel 4 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -config STM32U5_TIM5_CH4OUT - bool "TIM5 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32U5_TIM5_CHANNEL5 - -endif # STM32U5_PWM_MULTICHAN - -if !STM32U5_PWM_MULTICHAN - -config STM32U5_TIM5_CHANNEL - int "TIM5 PWM Output Channel" - default 1 - range 1 4 - ---help--- - If TIM5 is enabled for PWM usage, you also need specifies the timer output - channel {1,..,4} - -config STM32U5_TIM5_CHMODE - int "TIM5 Channel Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -endif # !STM32U5_PWM_MULTICHAN - -endif # STM32U5_TIM5_PWM - -config STM32U5_TIM8_PWM - bool "TIM8 PWM" - default n - depends on STM32U5_TIM8 - select STM32U5_PWM - ---help--- - Reserve timer 8 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32U5_TIM8 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32U5_TIM8_PWM - -config STM32U5_TIM8_MODE - int "TIM8 Mode" - default 0 - range 0 4 - ---help--- - Specifies the timer mode. - -if STM32U5_PWM_MULTICHAN - -config STM32U5_TIM8_CHANNEL1 - bool "TIM8 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32U5_TIM8_CHANNEL1 - -config STM32U5_TIM8_CH1MODE - int "TIM8 Channel 1 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -config STM32U5_TIM8_CH1OUT - bool "TIM8 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -config STM32U5_TIM8_CH1NOUT - bool "TIM8 Channel 1 Complementary Output" - default n - depends on STM32U5_TIM8_CH1OUT - ---help--- - Enables channel 1 complementary output. - -endif # STM32U5_TIM8_CHANNEL1 - -config STM32U5_TIM8_CHANNEL2 - bool "TIM8 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32U5_TIM8_CHANNEL2 - -config STM32U5_TIM8_CH2MODE - int "TIM8 Channel 2 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -config STM32U5_TIM8_CH2OUT - bool "TIM8 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -config STM32U5_TIM8_CH2NOUT - bool "TIM8 Channel 2 Complementary Output" - default n - depends on STM32U5_TIM8_CH2OUT - ---help--- - Enables channel 2 complementary output. - -endif # STM32U5_TIM8_CHANNEL2 - -config STM32U5_TIM8_CHANNEL3 - bool "TIM8 Channel 3" - default n - ---help--- - Enables channel 3. - -if STM32U5_TIM8_CHANNEL3 - -config STM32U5_TIM8_CH3MODE - int "TIM8 Channel 3 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -config STM32U5_TIM8_CH3OUT - bool "TIM8 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -config STM32U5_TIM8_CH3NOUT - bool "TIM8 Channel 3 Complementary Output" - default n - depends on STM32U5_TIM8_CH3OUT - ---help--- - Enables channel 3 complementary output. - -endif # STM32U5_TIM8_CHANNEL3 - -config STM32U5_TIM8_CHANNEL5 - bool "TIM8 Channel 4" - default n - ---help--- - Enables channel 4. - -if STM32U5_TIM8_CHANNEL5 - -config STM32U5_TIM8_CH4MODE - int "TIM8 Channel 4 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -config STM32U5_TIM8_CH4OUT - bool "TIM8 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32U5_TIM8_CHANNEL5 - -endif # STM32U5_PWM_MULTICHAN - -if !STM32U5_PWM_MULTICHAN - -config STM32U5_TIM8_CHANNEL - int "TIM8 PWM Output Channel" - default 1 - range 1 4 - ---help--- - If TIM8 is enabled for PWM usage, you also need specifies the timer output - channel {1,..,4} - -config STM32U5_TIM8_CHMODE - int "TIM8 Channel Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -endif # !STM32U5_PWM_MULTICHAN - -endif # STM32U5_TIM8_PWM - -config STM32U5_TIM15_PWM - bool "TIM15 PWM" - default n - depends on STM32U5_TIM15 - select STM32U5_PWM - ---help--- - Reserve timer 15 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32U5_TIM15 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32U5_TIM15_PWM - -if STM32U5_PWM_MULTICHAN - -config STM32U5_TIM15_CHANNEL1 - bool "TIM15 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32U5_TIM15_CHANNEL1 - -config STM32U5_TIM15_CH1MODE - int "TIM15 Channel 1 Mode" - default 0 - range 0 3 - ---help--- - Specifies the channel mode. - -config STM32U5_TIM15_CH1OUT - bool "TIM15 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -config STM32U5_TIM15_CH1NOUT - bool "TIM15 Channel 1 Complementary Output" - default n - depends on STM32U5_TIM15_CH1OUT - ---help--- - Enables channel 1 complementary output. - -endif # STM32U5_TIM15_CHANNEL1 - -config STM32U5_TIM15_CHANNEL2 - bool "TIM15 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32U5_TIM15_CHANNEL2 - -config STM32U5_TIM15_CH2MODE - int "TIM15 Channel 2 Mode" - default 0 - range 0 3 - ---help--- - Specifies the channel mode. - -config STM32U5_TIM15_CH2OUT - bool "TIM15 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32U5_TIM15_CHANNEL2 - -endif # STM32U5_PWM_MULTICHAN - -if !STM32U5_PWM_MULTICHAN - -config STM32U5_TIM15_CHANNEL - int "TIM15 PWM Output Channel" - default 1 - range 1 2 - ---help--- - If TIM15 is enabled for PWM usage, you also need specifies the timer output - channel {1,2} - -config STM32U5_TIM15_CHMODE - int "TIM15 Channel Mode" - default 0 - range 0 3 - ---help--- - Specifies the channel mode. - -endif # !STM32U5_PWM_MULTICHAN - -endif # STM32U5_TIM15_PWM - -config STM32U5_TIM16_PWM - bool "TIM16 PWM" - default n - depends on STM32U5_TIM16 - select STM32U5_PWM - ---help--- - Reserve timer 16 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32U5_TIM16 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32U5_TIM16_PWM - -if STM32U5_PWM_MULTICHAN - -config STM32U5_TIM16_CHANNEL1 - bool "TIM16 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32U5_TIM16_CHANNEL1 - -config STM32U5_TIM16_CH1MODE - int "TIM16 Channel 1 Mode" - default 0 - range 0 1 - ---help--- - Specifies the channel mode. - -config STM32U5_TIM16_CH1OUT - bool "TIM16 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -config STM32U5_TIM16_CH1NOUT - bool "TIM16 Channel 1 Complementary Output" - default n - depends on STM32U5_TIM16_CH1OUT - ---help--- - Enables channel 1 complementary output. - -endif # STM32U5_TIM16_CHANNEL1 - -endif # STM32U5_PWM_MULTICHAN - -if !STM32U5_PWM_MULTICHAN - -config STM32U5_TIM16_CHANNEL - int "TIM16 PWM Output Channel" - default 1 - range 1 1 - ---help--- - If TIM16 is enabled for PWM usage, you also need specifies the timer output - channel {1} - -config STM32U5_TIM16_CHMODE - int "TIM16 Channel Mode" - default 0 - range 0 1 - ---help--- - Specifies the channel mode. - -endif # !STM32U5_PWM_MULTICHAN - -endif # STM32U5_TIM16_PWM - -config STM32U5_TIM17_PWM - bool "TIM17 PWM" - default n - depends on STM32U5_TIM17 - select STM32U5_PWM - ---help--- - Reserve timer 17 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32U5_TIM17 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32U5_TIM17_PWM - -if STM32U5_PWM_MULTICHAN - -config STM32U5_TIM17_CHANNEL1 - bool "TIM17 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32U5_TIM17_CHANNEL1 - -config STM32U5_TIM17_CH1MODE - int "TIM17 Channel 1 Mode" - default 0 - range 0 1 - ---help--- - Specifies the channel mode. - -config STM32U5_TIM17_CH1OUT - bool "TIM17 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -config STM32U5_TIM17_CH1NOUT - bool "TIM17 Channel 1 Complementary Output" - default n - depends on STM32U5_TIM17_CH1OUT - ---help--- - Enables channel 1 complementary output. - -endif # STM32U5_TIM17_CHANNEL1 - -endif # STM32U5_PWM_MULTICHAN - -if !STM32U5_PWM_MULTICHAN - -config STM32U5_TIM17_CHANNEL - int "TIM17 PWM Output Channel" - default 1 - range 1 1 - ---help--- - If TIM17 is enabled for PWM usage, you also need specifies the timer output - channel {1} - -config STM32U5_TIM17_CHMODE - int "TIM17 Channel Mode" - default 0 - range 0 1 - ---help--- - Specifies the channel mode. - -endif # !STM32U5_PWM_MULTICHAN - -endif # STM32U5_TIM17_PWM - -config STM32U5_PWM_MULTICHAN - bool "PWM Multiple Output Channels" - default n - depends on STM32U5_PWM - ---help--- - Specifies that the PWM driver supports multiple output - channels per timer. - -config STM32U5_TIM1_ADC - bool "TIM1 ADC" - default n - depends on STM32U5_TIM1 && STM32U5_ADC - ---help--- - Reserve timer 1 for use by ADC - - Timer devices may be used for different purposes. If STM32U5_TIM1 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - -choice - prompt "Select TIM1 ADC channel" - default STM32U5_TIM1_ADC1 - depends on STM32U5_TIM1_ADC - -config STM32U5_TIM1_ADC1 - bool "TIM1 ADC channel 1" - depends on STM32U5_ADC1 - select STM32U5_HAVE_ADC1_TIMER - ---help--- - Reserve TIM1 to trigger ADC1 - -config STM32U5_TIM1_ADC2 - bool "TIM1 ADC channel 2" - depends on STM32U5_ADC2 - select STM32U5_HAVE_ADC2_TIMER - ---help--- - Reserve TIM1 to trigger ADC2 - -config STM32U5_TIM1_ADC3 - bool "TIM1 ADC channel 3" - depends on STM32U5_ADC3 - select STM32U5_HAVE_ADC3_TIMER - ---help--- - Reserve TIM1 to trigger ADC3 - -endchoice - -config STM32U5_TIM2_ADC - bool "TIM2 ADC" - default n - depends on STM32U5_TIM2 && STM32U5_ADC - ---help--- - Reserve timer 2 for use by ADC - - Timer devices may be used for different purposes. If STM32U5_TIM2 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - -choice - prompt "Select TIM2 ADC channel" - default STM32U5_TIM2_ADC1 - depends on STM32U5_TIM2_ADC - -config STM32U5_TIM2_ADC1 - bool "TIM2 ADC channel 1" - depends on STM32U5_ADC1 - select STM32U5_HAVE_ADC1_TIMER - ---help--- - Reserve TIM2 to trigger ADC1 - -config STM32U5_TIM2_ADC2 - bool "TIM2 ADC channel 2" - depends on STM32U5_ADC2 - select STM32U5_HAVE_ADC2_TIMER - ---help--- - Reserve TIM2 to trigger ADC2 - -config STM32U5_TIM2_ADC3 - bool "TIM2 ADC channel 3" - depends on STM32U5_ADC3 - select STM32U5_HAVE_ADC3_TIMER - ---help--- - Reserve TIM2 to trigger ADC3 - -endchoice - -config STM32U5_TIM3_ADC - bool "TIM3 ADC" - default n - depends on STM32U5_TIM3 && STM32U5_ADC - ---help--- - Reserve timer 3 for use by ADC - - Timer devices may be used for different purposes. If STM32U5_TIM3 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - -choice - prompt "Select TIM3 ADC channel" - default STM32U5_TIM3_ADC1 - depends on STM32U5_TIM3_ADC - -config STM32U5_TIM3_ADC1 - bool "TIM3 ADC channel 1" - depends on STM32U5_ADC1 - select STM32U5_HAVE_ADC1_TIMER - ---help--- - Reserve TIM3 to trigger ADC1 - -config STM32U5_TIM3_ADC2 - bool "TIM3 ADC channel 2" - depends on STM32U5_ADC2 - select STM32U5_HAVE_ADC2_TIMER - ---help--- - Reserve TIM3 to trigger ADC2 - -config STM32U5_TIM3_ADC3 - bool "TIM3 ADC channel 3" - depends on STM32U5_ADC3 - select STM32U5_HAVE_ADC3_TIMER - ---help--- - Reserve TIM3 to trigger ADC3 - -endchoice - -config STM32U5_TIM4_ADC - bool "TIM4 ADC" - default n - depends on STM32U5_TIM4 && STM32U5_ADC - ---help--- - Reserve timer 4 for use by ADC - - Timer devices may be used for different purposes. If STM32U5_TIM4 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - -choice - prompt "Select TIM4 ADC channel" - default STM32U5_TIM4_ADC1 - depends on STM32U5_TIM4_ADC - -config STM32U5_TIM4_ADC1 - bool "TIM4 ADC channel 1" - depends on STM32U5_ADC1 - select STM32U5_HAVE_ADC1_TIMER - ---help--- - Reserve TIM4 to trigger ADC1 - -config STM32U5_TIM4_ADC2 - bool "TIM4 ADC channel 2" - depends on STM32U5_ADC2 - select STM32U5_HAVE_ADC2_TIMER - ---help--- - Reserve TIM4 to trigger ADC2 - -config STM32U5_TIM4_ADC3 - bool "TIM4 ADC channel 3" - depends on STM32U5_ADC3 - select STM32U5_HAVE_ADC3_TIMER - ---help--- - Reserve TIM4 to trigger ADC3 - -endchoice - -config STM32U5_TIM6_ADC - bool "TIM6 ADC" - default n - depends on STM32U5_TIM6 && STM32U5_ADC - ---help--- - Reserve timer 6 for use by ADC - - Timer devices may be used for different purposes. If STM32U5_TIM6 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - -choice - prompt "Select TIM6 ADC channel" - default STM32U5_TIM6_ADC1 - depends on STM32U5_TIM6_ADC - -config STM32U5_TIM6_ADC1 - bool "TIM6 ADC channel 1" - depends on STM32U5_ADC1 - select STM32U5_HAVE_ADC1_TIMER - ---help--- - Reserve TIM6 to trigger ADC1 - -config STM32U5_TIM6_ADC2 - bool "TIM6 ADC channel 2" - depends on STM32U5_ADC2 - select STM32U5_HAVE_ADC2_TIMER - ---help--- - Reserve TIM6 to trigger ADC2 - -config STM32U5_TIM6_ADC3 - bool "TIM6 ADC channel 3" - depends on STM32U5_ADC3 - select STM32U5_HAVE_ADC3_TIMER - ---help--- - Reserve TIM6 to trigger ADC3 - -endchoice - -config STM32U5_TIM8_ADC - bool "TIM8 ADC" - default n - depends on STM32U5_TIM8 && STM32U5_ADC - ---help--- - Reserve timer 8 for use by ADC - - Timer devices may be used for different purposes. If STM32U5_TIM8 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - -choice - prompt "Select TIM8 ADC channel" - default STM32U5_TIM8_ADC1 - depends on STM32U5_TIM8_ADC - -config STM32U5_TIM8_ADC1 - bool "TIM8 ADC channel 1" - depends on STM32U5_ADC1 - select STM32U5_HAVE_ADC1_TIMER - ---help--- - Reserve TIM8 to trigger ADC1 - -config STM32U5_TIM8_ADC2 - bool "TIM8 ADC channel 2" - depends on STM32U5_ADC2 - select STM32U5_HAVE_ADC2_TIMER - ---help--- - Reserve TIM8 to trigger ADC2 - -config STM32U5_TIM8_ADC3 - bool "TIM8 ADC channel 3" - depends on STM32U5_ADC3 - select STM32U5_HAVE_ADC3_TIMER - ---help--- - Reserve TIM8 to trigger ADC3 - -endchoice - -config STM32U5_TIM15_ADC - bool "TIM15 ADC" - default n - depends on STM32U5_TIM15 && STM32U5_ADC - ---help--- - Reserve timer 15 for use by ADC - - Timer devices may be used for different purposes. If STM32U5_TIM15 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - -choice - prompt "Select TIM15 ADC channel" - default STM32U5_TIM15_ADC1 - depends on STM32U5_TIM15_ADC - -config STM32U5_TIM15_ADC1 - bool "TIM15 ADC channel 1" - depends on STM32U5_ADC1 - select STM32U5_HAVE_ADC1_TIMER - ---help--- - Reserve TIM15 to trigger ADC1 - -config STM32U5_TIM15_ADC2 - bool "TIM15 ADC channel 2" - depends on STM32U5_ADC2 - select STM32U5_HAVE_ADC2_TIMER - ---help--- - Reserve TIM15 to trigger ADC2 - -config STM32U5_TIM15_ADC3 - bool "TIM15 ADC channel 3" - depends on STM32U5_ADC3 - select STM32U5_HAVE_ADC3_TIMER - ---help--- - Reserve TIM15 to trigger ADC3 - -endchoice - -config STM32U5_HAVE_ADC1_TIMER - bool - -config STM32U5_HAVE_ADC2_TIMER - bool - -config STM32U5_HAVE_ADC3_TIMER - bool - -config STM32U5_ADC1_SAMPLE_FREQUENCY - int "ADC1 Sampling Frequency" - default 100 - depends on STM32U5_HAVE_ADC1_TIMER - ---help--- - ADC1 sampling frequency. Default: 100Hz - -config STM32U5_ADC1_TIMTRIG - int "ADC1 Timer Trigger" - default 0 - range 0 4 - depends on STM32U5_HAVE_ADC1_TIMER - ---help--- - Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO - -config STM32U5_ADC2_SAMPLE_FREQUENCY - int "ADC2 Sampling Frequency" - default 100 - depends on STM32U5_HAVE_ADC2_TIMER - ---help--- - ADC2 sampling frequency. Default: 100Hz - -config STM32U5_ADC2_TIMTRIG - int "ADC2 Timer Trigger" - default 0 - range 0 4 - depends on STM32U5_HAVE_ADC2_TIMER - ---help--- - Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO - -config STM32U5_ADC3_SAMPLE_FREQUENCY - int "ADC3 Sampling Frequency" - default 100 - depends on STM32U5_HAVE_ADC3_TIMER - ---help--- - ADC3 sampling frequency. Default: 100Hz - -config STM32U5_ADC3_TIMTRIG - int "ADC3 Timer Trigger" - default 0 - range 0 4 - depends on STM32U5_HAVE_ADC3_TIMER - ---help--- - Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO - -config STM32U5_TIM1_DAC - bool "TIM1 DAC" - default n - depends on STM32U5_TIM1 && STM32U5_DAC - ---help--- - Reserve timer 1 for use by DAC - - Timer devices may be used for different purposes. If STM32U5_TIM1 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -choice - prompt "Select TIM1 DAC channel" - default STM32U5_TIM1_DAC1 - depends on STM32U5_TIM1_DAC - -config STM32U5_TIM1_DAC1 - bool "TIM1 DAC channel 1" - ---help--- - Reserve TIM1 to trigger DAC1 - -config STM32U5_TIM1_DAC2 - bool "TIM1 DAC channel 2" - ---help--- - Reserve TIM1 to trigger DAC2 - -endchoice - -config STM32U5_TIM2_DAC - bool "TIM2 DAC" - default n - depends on STM32U5_TIM2 && STM32U5_DAC - ---help--- - Reserve timer 2 for use by DAC - - Timer devices may be used for different purposes. If STM32U5_TIM2 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -choice - prompt "Select TIM2 DAC channel" - default STM32U5_TIM2_DAC1 - depends on STM32U5_TIM2_DAC - -config STM32U5_TIM2_DAC1 - bool "TIM2 DAC channel 1" - ---help--- - Reserve TIM2 to trigger DAC1 - -config STM32U5_TIM2_DAC2 - bool "TIM2 DAC channel 2" - ---help--- - Reserve TIM2 to trigger DAC2 - -endchoice - -config STM32U5_TIM3_DAC - bool "TIM3 DAC" - default n - depends on STM32U5_TIM3 && STM32U5_DAC - ---help--- - Reserve timer 3 for use by DAC - - Timer devices may be used for different purposes. If STM32U5_TIM3 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -choice - prompt "Select TIM3 DAC channel" - default STM32U5_TIM3_DAC1 - depends on STM32U5_TIM3_DAC - -config STM32U5_TIM3_DAC1 - bool "TIM3 DAC channel 1" - ---help--- - Reserve TIM3 to trigger DAC1 - -config STM32U5_TIM3_DAC2 - bool "TIM3 DAC channel 2" - ---help--- - Reserve TIM3 to trigger DAC2 - -endchoice - -config STM32U5_TIM4_DAC - bool "TIM4 DAC" - default n - depends on STM32U5_TIM4 && STM32U5_DAC - ---help--- - Reserve timer 4 for use by DAC - - Timer devices may be used for different purposes. If STM32U5_TIM4 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -choice - prompt "Select TIM4 DAC channel" - default STM32U5_TIM4_DAC1 - depends on STM32U5_TIM4_DAC - -config STM32U5_TIM4_DAC1 - bool "TIM4 DAC channel 1" - ---help--- - Reserve TIM4 to trigger DAC1 - -config STM32U5_TIM4_DAC2 - bool "TIM4 DAC channel 2" - ---help--- - Reserve TIM4 to trigger DAC2 - -endchoice - -config STM32U5_TIM5_DAC - bool "TIM5 DAC" - default n - depends on STM32U5_TIM5 && STM32U5_DAC - ---help--- - Reserve timer 5 for use by DAC - - Timer devices may be used for different purposes. If STM32U5_TIM5 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -choice - prompt "Select TIM5 DAC channel" - default STM32U5_TIM5_DAC1 - depends on STM32U5_TIM5_DAC - -config STM32U5_TIM5_DAC1 - bool "TIM5 DAC channel 1" - ---help--- - Reserve TIM5 to trigger DAC1 - -config STM32U5_TIM5_DAC2 - bool "TIM5 DAC channel 2" - ---help--- - Reserve TIM5 to trigger DAC2 - -endchoice - -config STM32U5_TIM6_DAC - bool "TIM6 DAC" - default n - depends on STM32U5_TIM6 && STM32U5_DAC - ---help--- - Reserve timer 6 for use by DAC - - Timer devices may be used for different purposes. If STM32U5_TIM6 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -choice - prompt "Select TIM6 DAC channel" - default STM32U5_TIM6_DAC1 - depends on STM32U5_TIM6_DAC - -config STM32U5_TIM6_DAC1 - bool "TIM6 DAC channel 1" - ---help--- - Reserve TIM6 to trigger DAC1 - -config STM32U5_TIM6_DAC2 - bool "TIM6 DAC channel 2" - ---help--- - Reserve TIM6 to trigger DAC2 - -endchoice - -config STM32U5_TIM7_DAC - bool "TIM7 DAC" - default n - depends on STM32U5_TIM7 && STM32U5_DAC - ---help--- - Reserve timer 7 for use by DAC - - Timer devices may be used for different purposes. If STM32U5_TIM7 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -choice - prompt "Select TIM7 DAC channel" - default STM32U5_TIM7_DAC1 - depends on STM32U5_TIM7_DAC - -config STM32U5_TIM7_DAC1 - bool "TIM7 DAC channel 1" - ---help--- - Reserve TIM7 to trigger DAC1 - -config STM32U5_TIM7_DAC2 - bool "TIM7 DAC channel 2" - ---help--- - Reserve TIM7 to trigger DAC2 - -endchoice - -config STM32U5_TIM8_DAC - bool "TIM8 DAC" - default n - depends on STM32U5_TIM8 && STM32U5_DAC - ---help--- - Reserve timer 8 for use by DAC - - Timer devices may be used for different purposes. If STM32U5_TIM8 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -choice - prompt "Select TIM8 DAC channel" - default STM32U5_TIM8_DAC1 - depends on STM32U5_TIM8_DAC - -config STM32U5_TIM8_DAC1 - bool "TIM8 DAC channel 1" - ---help--- - Reserve TIM8 to trigger DAC1 - -config STM32U5_TIM8_DAC2 - bool "TIM8 DAC channel 2" - ---help--- - Reserve TIM8 to trigger DAC2 - -endchoice - -config STM32U5_TIM1_CAP - bool "TIM1 Capture" - default n - depends on STM32U5_HAVE_TIM1 - ---help--- - Reserve timer 1 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -config STM32U5_TIM2_CAP - bool "TIM2 Capture" - default n - depends on STM32U5_HAVE_TIM2 - ---help--- - Reserve timer 2 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -config STM32U5_TIM3_CAP - bool "TIM3 Capture" - default n - depends on STM32U5_HAVE_TIM3 - ---help--- - Reserve timer 3 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -config STM32U5_TIM4_CAP - bool "TIM4 Capture" - default n - depends on STM32U5_HAVE_TIM4 - ---help--- - Reserve timer 4 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -config STM32U5_TIM5_CAP - bool "TIM5 Capture" - default n - depends on STM32U5_HAVE_TIM5 - ---help--- - Reserve timer 5 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -config STM32U5_TIM8_CAP - bool "TIM8 Capture" - default n - depends on STM32U5_HAVE_TIM8 - ---help--- - Reserve timer 8 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -endmenu # Timer Configuration - -menu "ADC Configuration" - depends on STM32U5_ADC - -config STM32U5_ADC1_DMA - bool "ADC1 DMA" - depends on STM32U5_ADC1 - default n - ---help--- - If DMA is selected, then the ADC may be configured to support - DMA transfer, which is necessary if multiple channels are read - or if very high trigger frequencies are used. - -config STM32U5_ADC2_DMA - bool "ADC2 DMA" - depends on STM32U5_ADC2 - default n - ---help--- - If DMA is selected, then the ADC may be configured to support - DMA transfer, which is necessary if multiple channels are read - or if very high trigger frequencies are used. - -config STM32U5_ADC3_DMA - bool "ADC3 DMA" - depends on STM32U5_ADC3 - default n - ---help--- - If DMA is selected, then the ADC may be configured to support - DMA transfer, which is necessary if multiple channels are read - or if very high trigger frequencies are used. - -config STM32U5_ADC1_OUTPUT_DFSDM - bool "ADC1 output to DFSDM" - depends on STM32U5_ADC1 && STM32U5_DFSDM1 && (STM32U5_STM32U596XX || STM32U5_STM32U5XR) - default n - ---help--- - Route ADC1 output directly to DFSDM parallel inputs. - -config STM32U5_ADC2_OUTPUT_DFSDM - bool "ADC2 output to DFSDM" - depends on STM32U5_ADC2 && STM32U5_DFSDM1 && STM32U5_STM32U596XX - default n - ---help--- - Route ADC2 output directly to DFSDM parallel inputs. - -config STM32U5_ADC3_OUTPUT_DFSDM - bool "ADC3 output to DFSDM" - depends on STM32U5_ADC3 && STM32U5_DFSDM1 && STM32U5_STM32U596XX - default n - ---help--- - Route ADC3 output directly to DFSDM parallel inputs. - -endmenu - -menu "DAC Configuration" - depends on STM32U5_DAC - -config STM32U5_DAC1_DMA - bool "DAC1 DMA" - depends on STM32U5_DAC1 - default n - ---help--- - If DMA is selected, then a timer and output frequency must also be - provided to support the DMA transfer. The DMA transfer could be - supported by an EXTI trigger, but this feature is not currently - supported by the driver. - -if STM32U5_DAC1_DMA - -config STM32U5_DAC1_TIMER - int "DAC1 timer" - range 2 8 - -config STM32U5_DAC1_TIMER_FREQUENCY - int "DAC1 timer frequency" - default 100 - ---help--- - DAC1 output frequency. Default: 100Hz - -config STM32U5_DAC1_DMA_BUFFER_SIZE - int "DAC1 DMA buffer size" - default 1 - -endif - -config STM32U5_DAC1_OUTPUT_ADC - bool "DAC1 output to ADC" - depends on STM32U5_DAC1 - default n - ---help--- - Route DAC1 output to ADC input instead of external pin. - -config STM32U5_DAC2_DMA - bool "DAC2 DMA" - depends on STM32U5_DAC2 - default n - ---help--- - If DMA is selected, then a timer and output frequency must also be - provided to support the DMA transfer. The DMA transfer could be - supported by an EXTI trigger, but this feature is not currently - supported by the driver. - -if STM32U5_DAC2_DMA - -config STM32U5_DAC2_TIMER - int "DAC2 timer" - default 0 - range 2 8 - -config STM32U5_DAC2_TIMER_FREQUENCY - int "DAC2 timer frequency" - default 100 - ---help--- - DAC2 output frequency. Default: 100Hz - -config STM32U5_DAC2_DMA_BUFFER_SIZE - int "DAC2 DMA buffer size" - default 1 - -endif - -config STM32U5_DAC2_OUTPUT_ADC - bool "DAC2 output to ADC" - depends on STM32U5_DAC2 - default n - ---help--- - Route DAC2 output to ADC input instead of external pin. - -endmenu - -menu "DFSDM Configuration" - depends on STM32U5_DFSDM1 - -config STM32U5_DFSDM1_FLT0 - bool "DFSDM1 Filter 0" - default n - select STM32U5_DFSDM - -config STM32U5_DFSDM1_FLT1 - bool "DFSDM1 Filter 1" - default n - select STM32U5_DFSDM - -config STM32U5_DFSDM1_FLT2 - bool "DFSDM1 Filter 2" - default n - depends on !STM32U5_STM32U5X3 - select STM32U5_DFSDM - -config STM32U5_DFSDM1_FLT3 - bool "DFSDM1 Filter 3" - default n - depends on !STM32U5_STM32U5X3 - select STM32U5_DFSDM - -config STM32U5_DFSDM1_DMA - bool "DFSDM1 DMA" - depends on STM32U5_DFSDM - default n - ---help--- - If DMA is selected, then the DFSDM may be configured to support - DMA transfer, which is necessary if multiple channels are read - or if very high trigger frequencies are used. - -endmenu - -config STM32U5_SERIALDRIVER - bool - -config STM32U5_1WIREDRIVER - bool - -menu "[LP]U[S]ART Configuration" - depends on STM32U5_USART - -choice - prompt "LPUART1 Driver Configuration" - default STM32U5_LPUART1_SERIALDRIVER - depends on STM32U5_LPUART1 - -config STM32U5_LPUART1_SERIALDRIVER - bool "Standard serial driver" - select LPUART1_SERIALDRIVER - select STM32U5_SERIALDRIVER - -config STM32U5_LPUART1_1WIREDRIVER - bool "1-Wire driver" - select STM32U5_1WIREDRIVER - -endchoice # LPUART1 Driver Configuration - -if LPUART1_SERIALDRIVER - -config LPUART1_RS485 - bool "RS-485 on LPUART1" - default n - depends on STM32U5_LPUART1 - ---help--- - Enable RS-485 interface on LPUART1. Your board config will have to - provide GPIO_LPUART1_RS485_DIR pin definition. Currently it cannot be - used with LPUART1_RXDMA. - -config LPUART1_RS485_DIR_POLARITY - int "LPUART1 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on LPUART1_RS485 - ---help--- - Polarity of DIR pin for RS-485 on LPUART1. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config LPUART1_RXDMA - bool "LPUART1 Rx DMA" - default n - depends on STM32U5_LPUART1 && (STM32U5_DMA1 || STM32U5_DMA2 || STM32U5_DMAMUX) - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -endif # LPUART1_SERIALDRIVER - -choice - prompt "USART1 Driver Configuration" - default STM32U5_USART1_SERIALDRIVER - depends on STM32U5_USART1 - -config STM32U5_USART1_SERIALDRIVER - bool "Standard serial driver" - select USART1_SERIALDRIVER - select STM32U5_SERIALDRIVER - -config STM32U5_USART1_1WIREDRIVER - bool "1-Wire driver" - select STM32U5_1WIREDRIVER - -endchoice # USART1 Driver Configuration - -if USART1_SERIALDRIVER - -config USART1_RS485 - bool "RS-485 on USART1" - default n - depends on STM32U5_USART1 - ---help--- - Enable RS-485 interface on USART1. Your board config will have to - provide GPIO_USART1_RS485_DIR pin definition. Currently it cannot be - used with USART1_RXDMA. - -config USART1_RS485_DIR_POLARITY - int "USART1 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on USART1_RS485 - ---help--- - Polarity of DIR pin for RS-485 on USART1. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config USART1_RXDMA - bool "USART1 Rx DMA" - default n - depends on STM32U5_USART1 && (STM32U5_DMA1 || STM32U5_DMA2 || STM32U5_DMAMUX) - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -endif # USART1_SERIALDRIVER - -choice - prompt "USART2 Driver Configuration" - default STM32U5_USART2_SERIALDRIVER - depends on STM32U5_USART2 - -config STM32U5_USART2_SERIALDRIVER - bool "Standard serial driver" - select USART2_SERIALDRIVER - select STM32U5_SERIALDRIVER - -config STM32U5_USART2_1WIREDRIVER - bool "1-Wire driver" - select STM32U5_1WIREDRIVER - -endchoice # USART2 Driver Configuration - -if USART2_SERIALDRIVER - -config USART2_RS485 - bool "RS-485 on USART2" - default n - depends on STM32U5_USART2 - ---help--- - Enable RS-485 interface on USART2. Your board config will have to - provide GPIO_USART2_RS485_DIR pin definition. Currently it cannot be - used with USART2_RXDMA. - -config USART2_RS485_DIR_POLARITY - int "USART2 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on USART2_RS485 - ---help--- - Polarity of DIR pin for RS-485 on USART2. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config USART2_RXDMA - bool "USART2 Rx DMA" - default n - depends on STM32U5_USART2 && (STM32U5_DMA1 || STM32U5_DMAMUX) - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -endif # USART2_SERIALDRIVER - -choice - prompt "USART3 Driver Configuration" - default STM32U5_USART3_SERIALDRIVER - depends on STM32U5_USART3 - -config STM32U5_USART3_SERIALDRIVER - bool "Standard serial driver" - select USART3_SERIALDRIVER - select STM32U5_SERIALDRIVER - -config STM32U5_USART3_1WIREDRIVER - bool "1-Wire driver" - select STM32U5_1WIREDRIVER - -endchoice # USART3 Driver Configuration - -if USART3_SERIALDRIVER - -config USART3_RS485 - bool "RS-485 on USART3" - default n - depends on STM32U5_USART3 - ---help--- - Enable RS-485 interface on USART3. Your board config will have to - provide GPIO_USART3_RS485_DIR pin definition. Currently it cannot be - used with USART3_RXDMA. - -config USART3_RS485_DIR_POLARITY - int "USART3 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on USART3_RS485 - ---help--- - Polarity of DIR pin for RS-485 on USART3. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config USART3_RXDMA - bool "USART3 Rx DMA" - default n - depends on STM32U5_USART3 && (STM32U5_DMA1 || STM32U5_DMAMUX) - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -endif # USART3_SERIALDRIVER - -choice - prompt "UART4 Driver Configuration" - default STM32U5_UART4_SERIALDRIVER - depends on STM32U5_UART4 - -config STM32U5_UART4_SERIALDRIVER - bool "Standard serial driver" - select UART4_SERIALDRIVER - select STM32U5_SERIALDRIVER - -config STM32U5_UART4_1WIREDRIVER - bool "1-Wire driver" - select STM32U5_1WIREDRIVER - -endchoice # UART4 Driver Configuration - -if UART4_SERIALDRIVER - -config UART4_RS485 - bool "RS-485 on UART4" - default n - depends on STM32U5_UART4 - ---help--- - Enable RS-485 interface on UART4. Your board config will have to - provide GPIO_UART4_RS485_DIR pin definition. Currently it cannot be - used with UART4_RXDMA. - -config UART4_RS485_DIR_POLARITY - int "UART4 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on UART4_RS485 - ---help--- - Polarity of DIR pin for RS-485 on UART4. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config UART4_RXDMA - bool "UART4 Rx DMA" - default n - depends on STM32U5_UART4 && (STM32U5_DMA2 || STM32U5_DMAMUX) - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -endif # UART4_SERIALDRIVER - -choice - prompt "UART5 Driver Configuration" - default STM32U5_UART5_SERIALDRIVER - depends on STM32U5_UART5 - -config STM32U5_UART5_SERIALDRIVER - bool "Standard serial driver" - select UART5_SERIALDRIVER - select STM32U5_SERIALDRIVER - -config STM32U5_UART5_1WIREDRIVER - bool "1-Wire driver" - select STM32U5_1WIREDRIVER - -endchoice # UART5 Driver Configuration - -if UART5_SERIALDRIVER - -config UART5_RS485 - bool "RS-485 on UART5" - default n - depends on STM32U5_UART5 - ---help--- - Enable RS-485 interface on UART5. Your board config will have to - provide GPIO_UART5_RS485_DIR pin definition. Currently it cannot be - used with UART5_RXDMA. - -config UART5_RS485_DIR_POLARITY - int "UART5 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on UART5_RS485 - ---help--- - Polarity of DIR pin for RS-485 on UART5. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config UART5_RXDMA - bool "UART5 Rx DMA" - default n - depends on STM32U5_UART5 && (STM32U5_DMA2 || STM32U5_DMAMUX) - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -endif # UART5_SERIALDRIVER - -if STM32U5_SERIALDRIVER - -comment "Serial Driver Configuration" - -config STM32U5_SERIAL_RXDMA_BUFFER_SIZE - int "Rx DMA buffer size" - default 32 - depends on USART1_RXDMA || USART2_RXDMA || USART3_RXDMA || UART4_RXDMA || UART5_RXDMA - ---help--- - The DMA buffer size when using RX DMA to emulate a FIFO. - - When streaming data, the generic serial layer will be called - every time the FIFO receives half this number of bytes. - - Value given here will be rounded up to next multiple of 32 bytes. - -config STM32U5_SERIAL_DISABLE_REORDERING - bool "Disable reordering of ttySx devices." - depends on STM32U5_USART1 || STM32U5_USART2 || STM32U5_USART3 || STM32U5_UART4 || STM32U5_UART5 - default n - ---help--- - NuttX per default reorders the serial ports (/dev/ttySx) so that the - console is always on /dev/ttyS0. If more than one UART is in use this - can, however, have the side-effect that all port mappings - (hardware USART1 -> /dev/ttyS0) change if the console is moved to another - UART. This is in particular relevant if a project uses the USB console - in some boards and a serial console in other boards, but does not - want the side effect of having all serial port names change when just - the console is moved from serial to USB. - -config STM32U5_FLOWCONTROL_BROKEN - bool "Use Software UART RTS flow control" - depends on STM32U5_USART - default n - ---help--- - Enable UART RTS flow control using Software. Because STM - Current STM32 have broken HW based RTS behavior (they assert - nRTS after every byte received) Enable this setting workaround - this issue by using software based management of RTS - -config STM32U5_USART_BREAKS - bool "Add TIOxSBRK to support sending Breaks" - depends on STM32U5_USART - default n - ---help--- - Add TIOCxBRK routines to send a line break per the STM32 manual, the - break will be a pulse based on the value M. This is not a BSD compatible - break. - -config STM32U5_SERIALBRK_BSDCOMPAT - bool "Use GPIO To send Break" - depends on STM32U5_USART && STM32U5_USART_BREAKS - default n - ---help--- - Enable using GPIO on the TX pin to send a BSD compatible break: - TIOCSBRK will start the break and TIOCCBRK will end the break. - The current STM32U5 U[S]ARTS have no way to leave the break on - (TX=LOW) because software starts the break and then the hardware - automatically clears the break. This makes it difficult to send - a long break. - -config STM32U5_USART_SINGLEWIRE - bool "Single Wire Support" - default n - depends on STM32U5_USART - ---help--- - Enable single wire UART support. The option enables support for the - TIOCSSINGLEWIRE ioctl in the STM32U5 serial driver. - -config STM32U5_USART_INVERT - bool "Signal Invert Support" - default n - depends on STM32U5_USART - ---help--- - Enable signal inversion UART support. The option enables support for the - TIOCSINVERT ioctl in the STM32U5 serial driver. - -config STM32U5_USART_SWAP - bool "Swap RX/TX pins support" - default n - depends on STM32U5_USART - ---help--- - Enable RX/TX pin swapping support. The option enables support for the - TIOCSSWAP ioctl in the STM32U5 serial driver. - -if PM - -config STM32U5_PM_SERIAL_ACTIVITY - int "PM serial activity" - default 10 - ---help--- - PM activity reported to power management logic on every serial - interrupt. - -endif -endif # STM32U5_SERIALDRIVER - -endmenu # U[S]ART Configuration - -menu "SPI Configuration" - depends on STM32U5_SPI - -config STM32U5_SPI_INTERRUPTS - bool "Interrupt driver SPI" - default n - ---help--- - Select to enable interrupt driven SPI support. Non-interrupt-driven, - poll-waiting is recommended if the interrupt rate would be to high in - the interrupt driven case. - -config STM32U5_SPI_DMA - bool "SPI DMA" - default n - ---help--- - Use DMA to improve SPI transfer performance. Cannot be used with STM32U5_SPI_INTERRUPT. - -endmenu - -config STM32U5_I2C - bool - default n - -menu "I2C Configuration" - depends on STM32U5_I2C - -config STM32U5_I2C_DYNTIMEO - bool "Use dynamic timeouts" - default n - depends on STM32U5_I2C - -config STM32U5_I2C_DYNTIMEO_USECPERBYTE - int "Timeout Microseconds per Byte" - default 500 - depends on STM32U5_I2C_DYNTIMEO - -config STM32U5_I2C_DYNTIMEO_STARTSTOP - int "Timeout for Start/Stop (Milliseconds)" - default 1000 - depends on STM32U5_I2C_DYNTIMEO - -config STM32U5_I2CTIMEOSEC - int "Timeout seconds" - default 0 - depends on STM32U5_I2C - -config STM32U5_I2CTIMEOMS - int "Timeout Milliseconds" - default 500 - depends on STM32U5_I2C && !STM32U5_I2C_DYNTIMEO - -config STM32U5_I2CTIMEOTICKS - int "Timeout for Done and Stop (ticks)" - default 500 - depends on STM32U5_I2C && !STM32U5_I2C_DYNTIMEO - -endmenu - -menu "SD/MMC Configuration" - depends on STM32U5_SDMMC - -config STM32U5_SDMMC_XFRDEBUG - bool "SDMMC transfer debug" - depends on DEBUG_FS_INFO - default n - ---help--- - Enable special debug instrumentation analyze SDMMC data transfers. - This logic is as non-invasive as possible: It samples SDMMC - registers at key points in the data transfer and then dumps all of - the registers at the end of the transfer. If DEBUG_DMA is also - enabled, then DMA register will be collected as well. Requires also - DEBUG_FS and CONFIG_DEBUG_INFO. - -config STM32U5_SDMMC_DMA - bool "Support DMA data transfers" - default n - select SDIO_DMA - depends on STM32U5_DMA - ---help--- - Support DMA data transfers. - -menu "SDMMC1 Configuration" - depends on STM32U5_SDMMC1 - -config STM32U5_SDMMC1_DMAPRIO - hex "SDMMC1 DMA priority" - default 0x00001000 - ---help--- - Select SDMMC1 DMA priority. - - Options are: 0x00000000 low, 0x00001000 medium, - 0x00002000 high, 0x00003000 very high. Default: medium. - -config SDMMC1_WIDTH_D1_ONLY - bool "Use D1 only on SDMMC1" - default n - ---help--- - Select 1-bit transfer mode. Default: 4-bit transfer mode. - -endmenu # SDMMC1 Configuration -endmenu # SD/MMC Configuration - -menu "CAN driver configuration" - depends on STM32U5_CAN1 || STM32U5_CAN2 - -config STM32U5_CAN1_BAUD - int "CAN1 BAUD" - default 250000 - depends on STM32U5_CAN1 - ---help--- - CAN1 BAUD rate. Required if CONFIG_STM32U5_CAN1 is defined. - -config STM32U5_CAN2_BAUD - int "CAN2 BAUD" - default 250000 - depends on STM32U5_CAN2 - ---help--- - CAN2 BAUD rate. Required if CONFIG_STM32U5_CAN2 is defined. - -config STM32U5_CAN_TSEG1 - int "TSEG1 quanta" - default 6 - ---help--- - The number of CAN time quanta in segment 1. Default: 6 - -config STM32U5_CAN_TSEG2 - int "TSEG2 quanta" - default 7 - ---help--- - The number of CAN time quanta in segment 2. Default: 7 - -config STM32U5_CAN_REGDEBUG - bool "CAN Register level debug" - depends on DEBUG_CAN_INFO - default n - ---help--- - Output detailed register-level CAN device debug information. - Requires also CONFIG_DEBUG_CAN_INFO. - -endmenu - -menu "QEncoder Driver" - depends on SENSORS_QENCODER - depends on STM32U5_TIM1 || STM32U5_TIM2 || STM32U5_TIM3 || STM32U5_TIM4 || STM32U5_TIM5 || STM32U5_TIM8 - -config STM32U5_TIM1_QE - bool "TIM1" - default n - depends on STM32U5_TIM1 - ---help--- - Reserve TIM1 for use by QEncoder. - -if STM32U5_TIM1_QE - -config STM32U5_TIM1_QEPSC - int "TIM1 pulse prescaler" - default 1 - ---help--- - This prescaler divides the number of recorded encoder pulses, limiting the count rate at the expense of resolution. - -endif - -config STM32U5_TIM2_QE - bool "TIM2" - default n - depends on STM32U5_TIM2 - ---help--- - Reserve TIM2 for use by QEncoder. - -if STM32U5_TIM2_QE - -config STM32U5_TIM2_QEPSC - int "TIM2 pulse prescaler" - default 1 - ---help--- - This prescaler divides the number of recorded encoder pulses, limiting the count rate at the expense of resolution. - -endif - -config STM32U5_TIM3_QE - bool "TIM3" - default n - depends on STM32U5_TIM3 - ---help--- - Reserve TIM3 for use by QEncoder. - -if STM32U5_TIM3_QE - -config STM32U5_TIM3_QEPSC - int "TIM3 pulse prescaler" - default 1 - ---help--- - This prescaler divides the number of recorded encoder pulses, limiting the count rate at the expense of resolution. - -endif - -config STM32U5_TIM4_QE - bool "TIM4" - default n - depends on STM32U5_TIM4 - ---help--- - Reserve TIM4 for use by QEncoder. - -if STM32U5_TIM4_QE - -config STM32U5_TIM4_QEPSC - int "TIM4 pulse prescaler" - default 1 - ---help--- - This prescaler divides the number of recorded encoder pulses, limiting the count rate at the expense of resolution. - -endif - -config STM32U5_TIM5_QE - bool "TIM5" - default n - depends on STM32U5_TIM5 - ---help--- - Reserve TIM5 for use by QEncoder. - -if STM32U5_TIM5_QE - -config STM32U5_TIM5_QEPSC - int "TIM5 pulse prescaler" - default 1 - ---help--- - This prescaler divides the number of recorded encoder pulses, limiting the count rate at the expense of resolution. - -endif - -config STM32U5_TIM8_QE - bool "TIM8" - default n - depends on STM32U5_TIM8 - ---help--- - Reserve TIM8 for use by QEncoder. - -if STM32U5_TIM8_QE - -config STM32U5_TIM8_QEPSC - int "TIM8 pulse prescaler" - default 1 - ---help--- - This prescaler divides the number of recorded encoder pulses, limiting the count rate at the expense of resolution. - -endif - -config STM32U5_QENCODER_FILTER - bool "Enable filtering on STM32 QEncoder input" - default y - -choice - depends on STM32U5_QENCODER_FILTER - prompt "Input channel sampling frequency" - default STM32U5_QENCODER_SAMPLE_FDTS_4 - -config STM32U5_QENCODER_SAMPLE_FDTS - bool "fDTS" - -config STM32U5_QENCODER_SAMPLE_CKINT - bool "fCK_INT" - -config STM32U5_QENCODER_SAMPLE_FDTS_2 - bool "fDTS/2" - -config STM32U5_QENCODER_SAMPLE_FDTS_4 - bool "fDTS/4" - -config STM32U5_QENCODER_SAMPLE_FDTS_8 - bool "fDTS/8" - -config STM32U5_QENCODER_SAMPLE_FDTS_16 - bool "fDTS/16" - -config STM32U5_QENCODER_SAMPLE_FDTS_32 - bool "fDTS/32" - -endchoice - -choice - depends on STM32U5_QENCODER_FILTER - prompt "Input channel event count" - default STM32U5_QENCODER_SAMPLE_EVENT_6 - -config STM32U5_QENCODER_SAMPLE_EVENT_1 - depends on STM32U5_QENCODER_SAMPLE_FDTS - bool "1" - -config STM32U5_QENCODER_SAMPLE_EVENT_2 - depends on STM32U5_QENCODER_SAMPLE_CKINT - bool "2" - -config STM32U5_QENCODER_SAMPLE_EVENT_4 - depends on STM32U5_QENCODER_SAMPLE_CKINT - bool "4" - -config STM32U5_QENCODER_SAMPLE_EVENT_5 - depends on STM32U5_QENCODER_SAMPLE_FDTS_16 || STM32U5_QENCODER_SAMPLE_FDTS_32 - bool "5" - -config STM32U5_QENCODER_SAMPLE_EVENT_6 - depends on !STM32U5_QENCODER_SAMPLE_FDTS && !STM32U5_QENCODER_SAMPLE_CKINT - bool "6" - -config STM32U5_QENCODER_SAMPLE_EVENT_8 - depends on !STM32U5_QENCODER_SAMPLE_FDTS - bool "8" - -endchoice - -endmenu - -menu "SAI Configuration" - depends on STM32U5_SAI - -choice - prompt "Operation mode" - default STM32U5_SAI_DMA - ---help--- - Select the operation mode the SAI driver should use. - -config STM32U5_SAI_POLLING - bool "Polling" - ---help--- - The SAI registers are polled for events. - -config STM32U5_SAI_INTERRUPTS - bool "Interrupt" - ---help--- - Select to enable interrupt driven SAI support. - -config STM32U5_SAI_DMA - bool "DMA" - ---help--- - Use DMA to improve SAI transfer performance. - -endchoice # Operation mode - -choice - prompt "SAI1 synchronization enable" - default STM32U5_SAI1_BOTH_ASYNC - depends on STM32U5_SAI1_A && STM32U5_SAI1_B - ---help--- - Select the synchronization mode of the SAI sub-blocks - -config STM32U5_SAI1_BOTH_ASYNC - bool "Both asynchronous" - -config STM32U5_SAI1_A_SYNC_WITH_B - bool "Block A is synchronous with Block B" - -config STM32U5_SAI1_B_SYNC_WITH_A - bool "Block B is synchronous with Block A" - -endchoice # SAI1 synchronization enable - -choice - prompt "SAI2 synchronization enable" - default STM32U5_SAI2_BOTH_ASYNC - depends on STM32U5_SAI2_A && STM32U5_SAI2_B - ---help--- - Select the synchronization mode of the SAI sub-blocks - -config STM32U5_SAI2_BOTH_ASYNC - bool "Both asynchronous" - -config STM32U5_SAI2_A_SYNC_WITH_B - bool "Block A is synchronous with Block B" - -config STM32U5_SAI2_B_SYNC_WITH_A - bool "Block B is synchronous with Block A" - -endchoice # SAI2 synchronization enable - -endmenu - endif # ARCH_CHIP_STM32U5 diff --git a/arch/arm/src/stm32u5/Make.defs b/arch/arm/src/stm32u5/Make.defs index 5247b22d5d5e5..a884bf0cbf33a 100644 --- a/arch/arm/src/stm32u5/Make.defs +++ b/arch/arm/src/stm32u5/Make.defs @@ -28,13 +28,14 @@ HEAD_ASRC = # Common ARM and Cortex-M4 files (copied from stm32/Make.defs) include armv8-m/Make.defs +include common/stm32/Make.defs # Required STM32U5 files CHIP_ASRCS = -CHIP_CSRCS = stm32_allocateheap.c stm32_exti_gpio.c stm32_gpio.c +CHIP_CSRCS += stm32_allocateheap.c stm32_exti_gpio.c stm32_gpio.c CHIP_CSRCS += stm32_irq.c stm32_lowputc.c stm32_rcc.c stm32_i2c.c -CHIP_CSRCS += stm32_serial.c stm32_start.c stm32_waste.c stm32_uid.c +CHIP_CSRCS += stm32_serial.c stm32_start.c CHIP_CSRCS += stm32_spi.c stm32_lse.c stm32_lsi.c stm32u5xx_rcc.c CHIP_CSRCS += stm32_pwr.c stm32_tim.c stm32_flash.c stm32_timerisr.c diff --git a/arch/arm/src/stm32u5/hardware/stm32_flash.h b/arch/arm/src/stm32u5/hardware/stm32_flash.h index 8d201546ad19a..9377ee243f208 100644 --- a/arch/arm/src/stm32u5/hardware/stm32_flash.h +++ b/arch/arm/src/stm32u5/hardware/stm32_flash.h @@ -35,39 +35,39 @@ /* Flash size is known from the chip selection: * - * When CONFIG_STM32U5_FLASH_OVERRIDE_DEFAULT is set the - * CONFIG_STM32U5_FLASH_CONFIG_x selects the default FLASH size based on + * When CONFIG_STM32_FLASH_OVERRIDE_DEFAULT is set the + * CONFIG_STM32_FLASH_CONFIG_x selects the default FLASH size based on * the chip part number. This value can be overridden with - * CONFIG_STM32U5_FLASH_OVERRIDE_x + * CONFIG_STM32_FLASH_OVERRIDE_x * * Parts STM32U585 and STM32U575 have 2048Kb of FLASH */ #if defined(CONFIG_ARCH_CHIP_STM32U585AI) -# if !defined(CONFIG_STM32U5_FLASH_OVERRIDE_DEFAULT) && \ - !defined(CONFIG_STM32U5_FLASH_OVERRIDE_C) && \ - !defined(CONFIG_STM32U5_FLASH_OVERRIDE_E) && \ - !defined(CONFIG_STM32U5_FLASH_CONFIG_C) && \ - !defined(CONFIG_STM32U5_FLASH_CONFIG_E) -# define CONFIG_STM32U5_FLASH_OVERRIDE_E +# if !defined(CONFIG_STM32_FLASH_OVERRIDE_DEFAULT) && \ + !defined(CONFIG_STM32_FLASH_OVERRIDE_C) && \ + !defined(CONFIG_STM32_FLASH_OVERRIDE_E) && \ + !defined(CONFIG_STM32_FLASH_CONFIG_C) && \ + !defined(CONFIG_STM32_FLASH_CONFIG_E) +# define CONFIG_STM32_FLASH_OVERRIDE_E # warning "Flash size not defined defaulting to 512KiB (E)" # endif /* Override of the Flash has been chosen */ -# if !defined(CONFIG_STM32U5_FLASH_OVERRIDE_DEFAULT) -# undef CONFIG_STM32U5_FLASH_CONFIG_C -# undef CONFIG_STM32U5_FLASH_CONFIG_E -# if defined(CONFIG_STM32U5_FLASH_OVERRIDE_C) -# define CONFIG_STM32U5_FLASH_CONFIG_C -# elif defined(CONFIG_STM32U5_FLASH_OVERRIDE_E) -# define CONFIG_STM32U5_FLASH_CONFIG_E +# if !defined(CONFIG_STM32_FLASH_OVERRIDE_DEFAULT) +# undef CONFIG_STM32_FLASH_CONFIG_C +# undef CONFIG_STM32_FLASH_CONFIG_E +# if defined(CONFIG_STM32_FLASH_OVERRIDE_C) +# define CONFIG_STM32_FLASH_CONFIG_C +# elif defined(CONFIG_STM32_FLASH_OVERRIDE_E) +# define CONFIG_STM32_FLASH_CONFIG_E # endif # endif /* Define the valid configuration */ -# if defined(CONFIG_STM32U5_FLASH_CONFIG_I) /* 2048 kB */ +# if defined(CONFIG_STM32_FLASH_CONFIG_I) /* 2048 kB */ # define STM32_FLASH_NPAGES 256 # define STM32_FLASH_PAGESIZE 8192 # else @@ -79,7 +79,7 @@ # define STM32_FLASH_SIZE (STM32_FLASH_NPAGES * STM32_FLASH_PAGESIZE) #endif -#if defined(CONFIG_STM32U5_STM32U5A5XX) +#if defined(CONFIG_STM32_STM32U5A5XX) # define STM32_FLASH_NPAGES 512 # define STM32_FLASH_PAGESIZE 8192 # define STM32_FLASH_SIZE (STM32_FLASH_NPAGES * STM32_FLASH_PAGESIZE) diff --git a/arch/arm/src/stm32u5/hardware/stm32_memorymap.h b/arch/arm/src/stm32u5/hardware/stm32_memorymap.h index 616cb5e855e4a..fde84791f9b5f 100644 --- a/arch/arm/src/stm32u5/hardware/stm32_memorymap.h +++ b/arch/arm/src/stm32u5/hardware/stm32_memorymap.h @@ -40,18 +40,18 @@ #define STM32_CORTEX_BASE 0xE0000000 /* 0xe0000000-0xffffffff: 512Mb Cortex-M4 block */ #define STM32_REGION_MASK 0xF0000000 -#define STM32_IS_SRAM(a) ((((uint32_t)(a)) & STM32U5_REGION_MASK) == STM32U5_SRAM_BASE) -#define STM32_IS_EXTSRAM(a) ((((uint32_t)(a)) & STM32U5_REGION_MASK) == STM32U5_FMC_BANK1) +#define STM32_IS_SRAM(a) ((((uint32_t)(a)) & STM32_REGION_MASK) == STM32_SRAM_BASE) +#define STM32_IS_EXTSRAM(a) ((((uint32_t)(a)) & STM32_REGION_MASK) == STM32_FMC_BANK1) /* Code Base Addresses ******************************************************/ -#if defined(CONFIG_STM32U5_STM32U535XX) || defined(CONFIG_STM32U5_STM32U545XX) +#if defined(CONFIG_STM32_STM32U535XX) || defined(CONFIG_STM32_STM32U545XX) # define STM32_BOOT_BASE 0x00000000 /* 0x00000000-0x000fffff: Aliased boot memory */ # define STM32_FLASH_BASE 0x08000000 /* 0x08000000-0x081fffff: FLASH memory */ # define STM32_SRAM1_BASE 0x20000000 /* 0x20000000-0x2002ffff: 192k SRAM1 */ # define STM32_SRAM2_BASE 0x20030000 /* 0x20030000-0x2003ffff: 64k SRAM2 */ -#elif defined(CONFIG_STM32U5_STM32U575XX) || defined(CONFIG_STM32U5_STM32U585XX) +#elif defined(CONFIG_STM32_STM32U575XX) || defined(CONFIG_STM32_STM32U585XX) # define STM32_BOOT_BASE 0x00000000 /* 0x00000000-0x000fffff: Aliased boot memory */ # define STM32_FLASH_BASE 0x08000000 /* 0x08000000-0x081fffff: FLASH memory */ @@ -59,8 +59,8 @@ # define STM32_SRAM2_BASE 0x20030000 /* 0x20030000-0x2003ffff: 64k SRAM2 */ # define STM32_SRAM3_BASE 0x20040000 /* 0x20040000-0x200bffff: 512k SRAM3 */ -#elif defined(CONFIG_STM32U5_STM32U59XX) || defined(CONFIG_STM32U5_STM32U59AXX) || \ - defined(CONFIG_STM32U5_STM32U5A5XX) || defined(CONFIG_STM32U5_STM32U5A9XX) +#elif defined(CONFIG_STM32_STM32U59XX) || defined(CONFIG_STM32_STM32U59AXX) || \ + defined(CONFIG_STM32_STM32U5A5XX) || defined(CONFIG_STM32_STM32U5A9XX) # define STM32_BOOT_BASE 0x00000000 /* 0x00000000-0x000fffff: Aliased boot memory */ # define STM32_FLASH_BASE 0x08000000 /* 0x08000000-0x081fffff: FLASH memory */ diff --git a/arch/arm/src/stm32u5/hardware/stm32_pinmap.h b/arch/arm/src/stm32u5/hardware/stm32_pinmap.h index b289ebb0c4288..fd74182601256 100644 --- a/arch/arm/src/stm32u5/hardware/stm32_pinmap.h +++ b/arch/arm/src/stm32u5/hardware/stm32_pinmap.h @@ -30,7 +30,7 @@ #include #include "chip.h" -#if defined(CONFIG_STM32U5_STM32U585XX) || defined(CONFIG_STM32U5_STM32U5A5XX) +#if defined(CONFIG_STM32_STM32U585XX) || defined(CONFIG_STM32_STM32U5A5XX) # include "hardware/stm32u5xx_pinmap.h" #else # error "Unsupported STM32U5 pin map" diff --git a/arch/arm/src/stm32u5/hardware/stm32_spi.h b/arch/arm/src/stm32u5/hardware/stm32_spi.h index b13c066423465..79ff49f92d129 100644 --- a/arch/arm/src/stm32u5/hardware/stm32_spi.h +++ b/arch/arm/src/stm32u5/hardware/stm32_spi.h @@ -30,10 +30,10 @@ #include #include "chip.h" -#if defined(CONFIG_STM32U5_STM32U535XX) || defined(CONFIG_STM32U5_STM32U545XX) || \ - defined(CONFIG_STM32U5_STM32U575XX) || defined(CONFIG_STM32U5_STM32U585XX) || \ - defined(CONFIG_STM32U5_STM32U59XX) || defined(CONFIG_STM32U5_STM32U59AXX) || \ - defined(CONFIG_STM32U5_STM32U5A5XX) || defined(CONFIG_STM32U5_STM32U5A9XX) +#if defined(CONFIG_STM32_STM32U535XX) || defined(CONFIG_STM32_STM32U545XX) || \ + defined(CONFIG_STM32_STM32U575XX) || defined(CONFIG_STM32_STM32U585XX) || \ + defined(CONFIG_STM32_STM32U59XX) || defined(CONFIG_STM32_STM32U59AXX) || \ + defined(CONFIG_STM32_STM32U5A5XX) || defined(CONFIG_STM32_STM32U5A9XX) # include "hardware/stm32u5xx_spi.h" #else # error "Unsupported STM32U5 chip" diff --git a/arch/arm/src/stm32u5/hardware/stm32_syscfg.h b/arch/arm/src/stm32u5/hardware/stm32_syscfg.h index 120cbc4f58ea2..e79236a1fce42 100644 --- a/arch/arm/src/stm32u5/hardware/stm32_syscfg.h +++ b/arch/arm/src/stm32u5/hardware/stm32_syscfg.h @@ -30,7 +30,7 @@ #include #include "chip.h" -#if defined(CONFIG_STM32U5_STM32U585XX) || defined(CONFIG_STM32U5_STM32U5A5XX) +#if defined(CONFIG_STM32_STM32U585XX) || defined(CONFIG_STM32_STM32U5A5XX) # include "hardware/stm32u5xx_syscfg.h" #else # error "Unsupported STM32U5 chip" diff --git a/arch/arm/src/stm32u5/hardware/stm32_tim.h b/arch/arm/src/stm32u5/hardware/stm32_tim.h index d9adc748102f6..e180a60d773a3 100644 --- a/arch/arm/src/stm32u5/hardware/stm32_tim.h +++ b/arch/arm/src/stm32u5/hardware/stm32_tim.h @@ -31,14 +31,14 @@ /* Basic Timers - TIM6 and TIM7 */ -#define STM32U5_BTIM_CR1_OFFSET 0x0000 /* Control register 1 (16-bit) */ -#define STM32U5_BTIM_CR2_OFFSET 0x0004 /* Control register 2 (16-bit) */ -#define STM32U5_BTIM_DIER_OFFSET 0x000c /* DMA/Interrupt enable register (16-bit) */ -#define STM32U5_BTIM_SR_OFFSET 0x0010 /* Status register (16-bit) */ -#define STM32U5_BTIM_EGR_OFFSET 0x0014 /* Event generation register (16-bit) */ -#define STM32U5_BTIM_CNT_OFFSET 0x0024 /* Counter (16-bit) */ -#define STM32U5_BTIM_PSC_OFFSET 0x0028 /* Prescaler (16-bit) */ -#define STM32U5_BTIM_ARR_OFFSET 0x002c /* Auto-reload register (16-bit) */ +#define STM32_BTIM_CR1_OFFSET 0x0000 /* Control register 1 (16-bit) */ +#define STM32_BTIM_CR2_OFFSET 0x0004 /* Control register 2 (16-bit) */ +#define STM32_BTIM_DIER_OFFSET 0x000c /* DMA/Interrupt enable register (16-bit) */ +#define STM32_BTIM_SR_OFFSET 0x0010 /* Status register (16-bit) */ +#define STM32_BTIM_EGR_OFFSET 0x0014 /* Event generation register (16-bit) */ +#define STM32_BTIM_CNT_OFFSET 0x0024 /* Counter (16-bit) */ +#define STM32_BTIM_PSC_OFFSET 0x0028 /* Prescaler (16-bit) */ +#define STM32_BTIM_ARR_OFFSET 0x002c /* Auto-reload register (16-bit) */ /* 16-/32-bit General Timers - TIM2, TIM3, TIM4, TIM5, and TIM15-17. * TIM3 and 4 are 16-bit. @@ -46,119 +46,119 @@ * TIM15, 16 and 17 are 16-bit. */ -#define STM32U5_GTIM_CR1_OFFSET 0x0000 /* Control register 1 (16-bit) */ -#define STM32U5_GTIM_CR2_OFFSET 0x0004 /* Control register 2 (16-bit) */ -#define STM32U5_GTIM_SMCR_OFFSET 0x0008 /* Slave mode control register (16-bit, TIM2-5,15 only) */ -#define STM32U5_GTIM_DIER_OFFSET 0x000c /* DMA/Interrupt enable register (16-bit) */ -#define STM32U5_GTIM_SR_OFFSET 0x0010 /* Status register (16-bit) */ -#define STM32U5_GTIM_EGR_OFFSET 0x0014 /* Event generation register (16-bit) */ -#define STM32U5_GTIM_CCMR1_OFFSET 0x0018 /* Capture/compare mode register 1 (32-bit) */ -#define STM32U5_GTIM_CCMR2_OFFSET 0x001c /* Capture/compare mode register 2 (32-bit, TIM2-5 only) */ -#define STM32U5_GTIM_CCER_OFFSET 0x0020 /* Capture/compare enable register (16-bit) */ -#define STM32U5_GTIM_CNT_OFFSET 0x0024 /* Counter (16-bit or 32-bit TIM2/5) */ -#define STM32U5_GTIM_PSC_OFFSET 0x0028 /* Prescaler (16-bit) */ -#define STM32U5_GTIM_ARR_OFFSET 0x002c /* Auto-reload register (16-bit or 32-bit TIM2/5) */ -#define STM32U5_GTIM_CCR1_OFFSET 0x0034 /* Capture/compare register 1 (16-bit or 32-bit TIM2/5) */ -#define STM32U5_GTIM_CCR2_OFFSET 0x0038 /* Capture/compare register 2 (16-bit TIM2-5,15 only or 32-bit TIM2/5) */ -#define STM32U5_GTIM_CCR3_OFFSET 0x003c /* Capture/compare register 3 (16-bit TIM2-5 only or 32-bit TIM2/5) */ -#define STM32U5_GTIM_CCR4_OFFSET 0x0040 /* Capture/compare register 4 (16-bit TIM2-5 only or 32-bit TIM2/5) */ -#define STM32U5_GTIM_DCR_OFFSET 0x0048 /* DMA control register (16-bit) */ -#define STM32U5_GTIM_DMAR_OFFSET 0x004c /* DMA address for burst mode (16-bit) */ -#define STM32U5_GTIM_OR1_OFFSET 0x0050 /* Option register 1 */ -#define STM32U5_GTIM_OR2_OFFSET 0x0060 /* Option register 2 */ +#define STM32_GTIM_CR1_OFFSET 0x0000 /* Control register 1 (16-bit) */ +#define STM32_GTIM_CR2_OFFSET 0x0004 /* Control register 2 (16-bit) */ +#define STM32_GTIM_SMCR_OFFSET 0x0008 /* Slave mode control register (16-bit, TIM2-5,15 only) */ +#define STM32_GTIM_DIER_OFFSET 0x000c /* DMA/Interrupt enable register (16-bit) */ +#define STM32_GTIM_SR_OFFSET 0x0010 /* Status register (16-bit) */ +#define STM32_GTIM_EGR_OFFSET 0x0014 /* Event generation register (16-bit) */ +#define STM32_GTIM_CCMR1_OFFSET 0x0018 /* Capture/compare mode register 1 (32-bit) */ +#define STM32_GTIM_CCMR2_OFFSET 0x001c /* Capture/compare mode register 2 (32-bit, TIM2-5 only) */ +#define STM32_GTIM_CCER_OFFSET 0x0020 /* Capture/compare enable register (16-bit) */ +#define STM32_GTIM_CNT_OFFSET 0x0024 /* Counter (16-bit or 32-bit TIM2/5) */ +#define STM32_GTIM_PSC_OFFSET 0x0028 /* Prescaler (16-bit) */ +#define STM32_GTIM_ARR_OFFSET 0x002c /* Auto-reload register (16-bit or 32-bit TIM2/5) */ +#define STM32_GTIM_CCR1_OFFSET 0x0034 /* Capture/compare register 1 (16-bit or 32-bit TIM2/5) */ +#define STM32_GTIM_CCR2_OFFSET 0x0038 /* Capture/compare register 2 (16-bit TIM2-5,15 only or 32-bit TIM2/5) */ +#define STM32_GTIM_CCR3_OFFSET 0x003c /* Capture/compare register 3 (16-bit TIM2-5 only or 32-bit TIM2/5) */ +#define STM32_GTIM_CCR4_OFFSET 0x0040 /* Capture/compare register 4 (16-bit TIM2-5 only or 32-bit TIM2/5) */ +#define STM32_GTIM_DCR_OFFSET 0x0048 /* DMA control register (16-bit) */ +#define STM32_GTIM_DMAR_OFFSET 0x004c /* DMA address for burst mode (16-bit) */ +#define STM32_GTIM_OR1_OFFSET 0x0050 /* Option register 1 */ +#define STM32_GTIM_OR2_OFFSET 0x0060 /* Option register 2 */ /* TIM15, 16, and 17 only. */ -#define STM32U5_GTIM_RCR_OFFSET 0x0030 /* Repetition counter register (TIM16/TIM17) */ -#define STM32U5_GTIM_BDTR_OFFSET 0x0044 /* Break and dead-time register (TIM16/TIM17) */ +#define STM32_GTIM_RCR_OFFSET 0x0030 /* Repetition counter register (TIM16/TIM17) */ +#define STM32_GTIM_BDTR_OFFSET 0x0044 /* Break and dead-time register (TIM16/TIM17) */ /* Advanced Timers - TIM1 and TIM8 */ -#define STM32U5_ATIM_CR1_OFFSET 0x0000 /* Control register 1 (16-bit) */ -#define STM32U5_ATIM_CR2_OFFSET 0x0004 /* Control register 2 (16-bit*) */ -#define STM32U5_ATIM_SMCR_OFFSET 0x0008 /* Slave mode control register (16-bit) */ -#define STM32U5_ATIM_DIER_OFFSET 0x000c /* DMA/Interrupt enable register (16-bit) */ -#define STM32U5_ATIM_SR_OFFSET 0x0010 /* Status register (16-bit*) */ -#define STM32U5_ATIM_EGR_OFFSET 0x0014 /* Event generation register (16-bit) */ -#define STM32U5_ATIM_CCMR1_OFFSET 0x0018 /* Capture/compare mode register 1 (16-bit*) */ -#define STM32U5_ATIM_CCMR2_OFFSET 0x001c /* Capture/compare mode register 2 (16-bit*) */ -#define STM32U5_ATIM_CCER_OFFSET 0x0020 /* Capture/compare enable register (16-bit*) */ -#define STM32U5_ATIM_CNT_OFFSET 0x0024 /* Counter (16-bit) */ -#define STM32U5_ATIM_PSC_OFFSET 0x0028 /* Prescaler (16-bit) */ -#define STM32U5_ATIM_ARR_OFFSET 0x002c /* Auto-reload register (16-bit) */ -#define STM32U5_ATIM_RCR_OFFSET 0x0030 /* Repetition counter register (16-bit) */ -#define STM32U5_ATIM_CCR1_OFFSET 0x0034 /* Capture/compare register 1 (16-bit) */ -#define STM32U5_ATIM_CCR2_OFFSET 0x0038 /* Capture/compare register 2 (16-bit) */ -#define STM32U5_ATIM_CCR3_OFFSET 0x003c /* Capture/compare register 3 (16-bit) */ -#define STM32U5_ATIM_CCR4_OFFSET 0x0040 /* Capture/compare register 4 (16-bit) */ -#define STM32U5_ATIM_BDTR_OFFSET 0x0044 /* Break and dead-time register (16-bit*) */ -#define STM32U5_ATIM_DCR_OFFSET 0x0048 /* DMA control register (16-bit) */ -#define STM32U5_ATIM_DMAR_OFFSET 0x004c /* DMA address for burst mode (16-bit) */ -#define STM32U5_ATIM_OR1_OFFSET 0x0050 /* Timer option register 1 */ -#define STM32U5_ATIM_CCMR3_OFFSET 0x0054 /* Capture/compare mode register 3 (32-bit) */ -#define STM32U5_ATIM_CCR5_OFFSET 0x0058 /* Capture/compare register 4 (16-bit) */ -#define STM32U5_ATIM_CCR6_OFFSET 0x005c /* Capture/compare register 4 (32-bit) */ -#define STM32U5_ATIM_OR2_OFFSET 0x0050 /* Timer option register 2 */ -#define STM32U5_ATIM_OR3_OFFSET 0x0050 /* Timer option register 3 */ +#define STM32_ATIM_CR1_OFFSET 0x0000 /* Control register 1 (16-bit) */ +#define STM32_ATIM_CR2_OFFSET 0x0004 /* Control register 2 (16-bit*) */ +#define STM32_ATIM_SMCR_OFFSET 0x0008 /* Slave mode control register (16-bit) */ +#define STM32_ATIM_DIER_OFFSET 0x000c /* DMA/Interrupt enable register (16-bit) */ +#define STM32_ATIM_SR_OFFSET 0x0010 /* Status register (16-bit*) */ +#define STM32_ATIM_EGR_OFFSET 0x0014 /* Event generation register (16-bit) */ +#define STM32_ATIM_CCMR1_OFFSET 0x0018 /* Capture/compare mode register 1 (16-bit*) */ +#define STM32_ATIM_CCMR2_OFFSET 0x001c /* Capture/compare mode register 2 (16-bit*) */ +#define STM32_ATIM_CCER_OFFSET 0x0020 /* Capture/compare enable register (16-bit*) */ +#define STM32_ATIM_CNT_OFFSET 0x0024 /* Counter (16-bit) */ +#define STM32_ATIM_PSC_OFFSET 0x0028 /* Prescaler (16-bit) */ +#define STM32_ATIM_ARR_OFFSET 0x002c /* Auto-reload register (16-bit) */ +#define STM32_ATIM_RCR_OFFSET 0x0030 /* Repetition counter register (16-bit) */ +#define STM32_ATIM_CCR1_OFFSET 0x0034 /* Capture/compare register 1 (16-bit) */ +#define STM32_ATIM_CCR2_OFFSET 0x0038 /* Capture/compare register 2 (16-bit) */ +#define STM32_ATIM_CCR3_OFFSET 0x003c /* Capture/compare register 3 (16-bit) */ +#define STM32_ATIM_CCR4_OFFSET 0x0040 /* Capture/compare register 4 (16-bit) */ +#define STM32_ATIM_BDTR_OFFSET 0x0044 /* Break and dead-time register (16-bit*) */ +#define STM32_ATIM_DCR_OFFSET 0x0048 /* DMA control register (16-bit) */ +#define STM32_ATIM_DMAR_OFFSET 0x004c /* DMA address for burst mode (16-bit) */ +#define STM32_ATIM_OR1_OFFSET 0x0050 /* Timer option register 1 */ +#define STM32_ATIM_CCMR3_OFFSET 0x0054 /* Capture/compare mode register 3 (32-bit) */ +#define STM32_ATIM_CCR5_OFFSET 0x0058 /* Capture/compare register 4 (16-bit) */ +#define STM32_ATIM_CCR6_OFFSET 0x005c /* Capture/compare register 4 (32-bit) */ +#define STM32_ATIM_OR2_OFFSET 0x0050 /* Timer option register 2 */ +#define STM32_ATIM_OR3_OFFSET 0x0050 /* Timer option register 3 */ /* Register Addresses *******************************************************/ /* Advanced Timers - TIM1 and TIM8 */ -#define STM32U5_TIM1_CR1 (STM32U5_TIM1_BASE + STM32U5_ATIM_CR1_OFFSET) -#define STM32U5_TIM1_CR2 (STM32U5_TIM1_BASE + STM32U5_ATIM_CR2_OFFSET) -#define STM32U5_TIM1_SMCR (STM32U5_TIM1_BASE + STM32U5_ATIM_SMCR_OFFSET) -#define STM32U5_TIM1_DIER (STM32U5_TIM1_BASE + STM32U5_ATIM_DIER_OFFSET) -#define STM32U5_TIM1_SR (STM32U5_TIM1_BASE + STM32U5_ATIM_SR_OFFSET) -#define STM32U5_TIM1_EGR (STM32U5_TIM1_BASE + STM32U5_ATIM_EGR_OFFSET) -#define STM32U5_TIM1_CCMR1 (STM32U5_TIM1_BASE + STM32U5_ATIM_CCMR1_OFFSET) -#define STM32U5_TIM1_CCMR2 (STM32U5_TIM1_BASE + STM32U5_ATIM_CCMR2_OFFSET) -#define STM32U5_TIM1_CCER (STM32U5_TIM1_BASE + STM32U5_ATIM_CCER_OFFSET) -#define STM32U5_TIM1_CNT (STM32U5_TIM1_BASE + STM32U5_ATIM_CNT_OFFSET) -#define STM32U5_TIM1_PSC (STM32U5_TIM1_BASE + STM32U5_ATIM_PSC_OFFSET) -#define STM32U5_TIM1_ARR (STM32U5_TIM1_BASE + STM32U5_ATIM_ARR_OFFSET) -#define STM32U5_TIM1_RCR (STM32U5_TIM1_BASE + STM32U5_ATIM_RCR_OFFSET) -#define STM32U5_TIM1_CCR1 (STM32U5_TIM1_BASE + STM32U5_ATIM_CCR1_OFFSET) -#define STM32U5_TIM1_CCR2 (STM32U5_TIM1_BASE + STM32U5_ATIM_CCR2_OFFSET) -#define STM32U5_TIM1_CCR3 (STM32U5_TIM1_BASE + STM32U5_ATIM_CCR3_OFFSET) -#define STM32U5_TIM1_CCR4 (STM32U5_TIM1_BASE + STM32U5_ATIM_CCR4_OFFSET) -#define STM32U5_TIM1_BDTR (STM32U5_TIM1_BASE + STM32U5_ATIM_BDTR_OFFSET) -#define STM32U5_TIM1_DCR (STM32U5_TIM1_BASE + STM32U5_ATIM_DCR_OFFSET) -#define STM32U5_TIM1_DMAR (STM32U5_TIM1_BASE + STM32U5_ATIM_DMAR_OFFSET) -#define STM32U5_TIM1_OR1 (STM32U5_TIM1_BASE + STM32U5_ATIM_OR1_OFFSET) -#define STM32U5_TIM1_CCMR3 (STM32U5_TIM1_BASE + STM32U5_ATIM_CCMR3_OFFSET) -#define STM32U5_TIM1_CCR5 (STM32U5_TIM1_BASE + STM32U5_ATIM_CCR5_OFFSET) -#define STM32U5_TIM1_CCR6 (STM32U5_TIM1_BASE + STM32U5_ATIM_CCR6_OFFSET) -#define STM32U5_TIM1_OR2 (STM32U5_TIM1_BASE + STM32U5_ATIM_OR2_OFFSET) -#define STM32U5_TIM1_OR3 (STM32U5_TIM1_BASE + STM32U5_ATIM_OR3_OFFSET) - -#define STM32U5_TIM8_CR1 (STM32U5_TIM8_BASE + STM32U5_ATIM_CR1_OFFSET) -#define STM32U5_TIM8_CR2 (STM32U5_TIM8_BASE + STM32U5_ATIM_CR2_OFFSET) -#define STM32U5_TIM8_SMCR (STM32U5_TIM8_BASE + STM32U5_ATIM_SMCR_OFFSET) -#define STM32U5_TIM8_DIER (STM32U5_TIM8_BASE + STM32U5_ATIM_DIER_OFFSET) -#define STM32U5_TIM8_SR (STM32U5_TIM8_BASE + STM32U5_ATIM_SR_OFFSET) -#define STM32U5_TIM8_EGR (STM32U5_TIM8_BASE + STM32U5_ATIM_EGR_OFFSET) -#define STM32U5_TIM8_CCMR1 (STM32U5_TIM8_BASE + STM32U5_ATIM_CCMR1_OFFSET) -#define STM32U5_TIM8_CCMR2 (STM32U5_TIM8_BASE + STM32U5_ATIM_CCMR2_OFFSET) -#define STM32U5_TIM8_CCER (STM32U5_TIM8_BASE + STM32U5_ATIM_CCER_OFFSET) -#define STM32U5_TIM8_CNT (STM32U5_TIM8_BASE + STM32U5_ATIM_CNT_OFFSET) -#define STM32U5_TIM8_PSC (STM32U5_TIM8_BASE + STM32U5_ATIM_PSC_OFFSET) -#define STM32U5_TIM8_ARR (STM32U5_TIM8_BASE + STM32U5_ATIM_ARR_OFFSET) -#define STM32U5_TIM8_RCR (STM32U5_TIM8_BASE + STM32U5_ATIM_RCR_OFFSET) -#define STM32U5_TIM8_CCR1 (STM32U5_TIM8_BASE + STM32U5_ATIM_CCR1_OFFSET) -#define STM32U5_TIM8_CCR2 (STM32U5_TIM8_BASE + STM32U5_ATIM_CCR2_OFFSET) -#define STM32U5_TIM8_CCR3 (STM32U5_TIM8_BASE + STM32U5_ATIM_CCR3_OFFSET) -#define STM32U5_TIM8_CCR4 (STM32U5_TIM8_BASE + STM32U5_ATIM_CCR4_OFFSET) -#define STM32U5_TIM8_BDTR (STM32U5_TIM8_BASE + STM32U5_ATIM_BDTR_OFFSET) -#define STM32U5_TIM8_DCR (STM32U5_TIM8_BASE + STM32U5_ATIM_DCR_OFFSET) -#define STM32U5_TIM8_DMAR (STM32U5_TIM8_BASE + STM32U5_ATIM_DMAR_OFFSET) -#define STM32U5_TIM8_OR1 (STM32U5_TIM8_BASE + STM32U5_ATIM_OR1_OFFSET) -#define STM32U5_TIM8_CCMR3 (STM32U5_TIM8_BASE + STM32U5_ATIM_CCMR3_OFFSET) -#define STM32U5_TIM8_CCR5 (STM32U5_TIM8_BASE + STM32U5_ATIM_CCR5_OFFSET) -#define STM32U5_TIM8_CCR6 (STM32U5_TIM8_BASE + STM32U5_ATIM_CCR6_OFFSET) -#define STM32U5_TIM8_OR2 (STM32U5_TIM8_BASE + STM32U5_ATIM_OR2_OFFSET) -#define STM32U5_TIM8_OR3 (STM32U5_TIM8_BASE + STM32U5_ATIM_OR3_OFFSET) +#define STM32_TIM1_CR1 (STM32_TIM1_BASE + STM32_ATIM_CR1_OFFSET) +#define STM32_TIM1_CR2 (STM32_TIM1_BASE + STM32_ATIM_CR2_OFFSET) +#define STM32_TIM1_SMCR (STM32_TIM1_BASE + STM32_ATIM_SMCR_OFFSET) +#define STM32_TIM1_DIER (STM32_TIM1_BASE + STM32_ATIM_DIER_OFFSET) +#define STM32_TIM1_SR (STM32_TIM1_BASE + STM32_ATIM_SR_OFFSET) +#define STM32_TIM1_EGR (STM32_TIM1_BASE + STM32_ATIM_EGR_OFFSET) +#define STM32_TIM1_CCMR1 (STM32_TIM1_BASE + STM32_ATIM_CCMR1_OFFSET) +#define STM32_TIM1_CCMR2 (STM32_TIM1_BASE + STM32_ATIM_CCMR2_OFFSET) +#define STM32_TIM1_CCER (STM32_TIM1_BASE + STM32_ATIM_CCER_OFFSET) +#define STM32_TIM1_CNT (STM32_TIM1_BASE + STM32_ATIM_CNT_OFFSET) +#define STM32_TIM1_PSC (STM32_TIM1_BASE + STM32_ATIM_PSC_OFFSET) +#define STM32_TIM1_ARR (STM32_TIM1_BASE + STM32_ATIM_ARR_OFFSET) +#define STM32_TIM1_RCR (STM32_TIM1_BASE + STM32_ATIM_RCR_OFFSET) +#define STM32_TIM1_CCR1 (STM32_TIM1_BASE + STM32_ATIM_CCR1_OFFSET) +#define STM32_TIM1_CCR2 (STM32_TIM1_BASE + STM32_ATIM_CCR2_OFFSET) +#define STM32_TIM1_CCR3 (STM32_TIM1_BASE + STM32_ATIM_CCR3_OFFSET) +#define STM32_TIM1_CCR4 (STM32_TIM1_BASE + STM32_ATIM_CCR4_OFFSET) +#define STM32_TIM1_BDTR (STM32_TIM1_BASE + STM32_ATIM_BDTR_OFFSET) +#define STM32_TIM1_DCR (STM32_TIM1_BASE + STM32_ATIM_DCR_OFFSET) +#define STM32_TIM1_DMAR (STM32_TIM1_BASE + STM32_ATIM_DMAR_OFFSET) +#define STM32_TIM1_OR1 (STM32_TIM1_BASE + STM32_ATIM_OR1_OFFSET) +#define STM32_TIM1_CCMR3 (STM32_TIM1_BASE + STM32_ATIM_CCMR3_OFFSET) +#define STM32_TIM1_CCR5 (STM32_TIM1_BASE + STM32_ATIM_CCR5_OFFSET) +#define STM32_TIM1_CCR6 (STM32_TIM1_BASE + STM32_ATIM_CCR6_OFFSET) +#define STM32_TIM1_OR2 (STM32_TIM1_BASE + STM32_ATIM_OR2_OFFSET) +#define STM32_TIM1_OR3 (STM32_TIM1_BASE + STM32_ATIM_OR3_OFFSET) + +#define STM32_TIM8_CR1 (STM32_TIM8_BASE + STM32_ATIM_CR1_OFFSET) +#define STM32_TIM8_CR2 (STM32_TIM8_BASE + STM32_ATIM_CR2_OFFSET) +#define STM32_TIM8_SMCR (STM32_TIM8_BASE + STM32_ATIM_SMCR_OFFSET) +#define STM32_TIM8_DIER (STM32_TIM8_BASE + STM32_ATIM_DIER_OFFSET) +#define STM32_TIM8_SR (STM32_TIM8_BASE + STM32_ATIM_SR_OFFSET) +#define STM32_TIM8_EGR (STM32_TIM8_BASE + STM32_ATIM_EGR_OFFSET) +#define STM32_TIM8_CCMR1 (STM32_TIM8_BASE + STM32_ATIM_CCMR1_OFFSET) +#define STM32_TIM8_CCMR2 (STM32_TIM8_BASE + STM32_ATIM_CCMR2_OFFSET) +#define STM32_TIM8_CCER (STM32_TIM8_BASE + STM32_ATIM_CCER_OFFSET) +#define STM32_TIM8_CNT (STM32_TIM8_BASE + STM32_ATIM_CNT_OFFSET) +#define STM32_TIM8_PSC (STM32_TIM8_BASE + STM32_ATIM_PSC_OFFSET) +#define STM32_TIM8_ARR (STM32_TIM8_BASE + STM32_ATIM_ARR_OFFSET) +#define STM32_TIM8_RCR (STM32_TIM8_BASE + STM32_ATIM_RCR_OFFSET) +#define STM32_TIM8_CCR1 (STM32_TIM8_BASE + STM32_ATIM_CCR1_OFFSET) +#define STM32_TIM8_CCR2 (STM32_TIM8_BASE + STM32_ATIM_CCR2_OFFSET) +#define STM32_TIM8_CCR3 (STM32_TIM8_BASE + STM32_ATIM_CCR3_OFFSET) +#define STM32_TIM8_CCR4 (STM32_TIM8_BASE + STM32_ATIM_CCR4_OFFSET) +#define STM32_TIM8_BDTR (STM32_TIM8_BASE + STM32_ATIM_BDTR_OFFSET) +#define STM32_TIM8_DCR (STM32_TIM8_BASE + STM32_ATIM_DCR_OFFSET) +#define STM32_TIM8_DMAR (STM32_TIM8_BASE + STM32_ATIM_DMAR_OFFSET) +#define STM32_TIM8_OR1 (STM32_TIM8_BASE + STM32_ATIM_OR1_OFFSET) +#define STM32_TIM8_CCMR3 (STM32_TIM8_BASE + STM32_ATIM_CCMR3_OFFSET) +#define STM32_TIM8_CCR5 (STM32_TIM8_BASE + STM32_ATIM_CCR5_OFFSET) +#define STM32_TIM8_CCR6 (STM32_TIM8_BASE + STM32_ATIM_CCR6_OFFSET) +#define STM32_TIM8_OR2 (STM32_TIM8_BASE + STM32_ATIM_OR2_OFFSET) +#define STM32_TIM8_OR3 (STM32_TIM8_BASE + STM32_ATIM_OR3_OFFSET) /* 16-/32-bit General Timers - TIM2, TIM3, TIM4, TIM5, and TIM15-17. * TIM3 and 4 are 16-bit. @@ -166,154 +166,154 @@ * TIM15, 16 and 17 are 16-bit. */ -#define STM32U5_TIM2_CR1 (STM32U5_TIM2_BASE + STM32U5_GTIM_CR1_OFFSET) -#define STM32U5_TIM2_CR2 (STM32U5_TIM2_BASE + STM32U5_GTIM_CR2_OFFSET) -#define STM32U5_TIM2_SMCR (STM32U5_TIM2_BASE + STM32U5_GTIM_SMCR_OFFSET) -#define STM32U5_TIM2_DIER (STM32U5_TIM2_BASE + STM32U5_GTIM_DIER_OFFSET) -#define STM32U5_TIM2_SR (STM32U5_TIM2_BASE + STM32U5_GTIM_SR_OFFSET) -#define STM32U5_TIM2_EGR (STM32U5_TIM2_BASE + STM32U5_GTIM_EGR_OFFSET) -#define STM32U5_TIM2_CCMR1 (STM32U5_TIM2_BASE + STM32U5_GTIM_CCMR1_OFFSET) -#define STM32U5_TIM2_CCMR2 (STM32U5_TIM2_BASE + STM32U5_GTIM_CCMR2_OFFSET) -#define STM32U5_TIM2_CCER (STM32U5_TIM2_BASE + STM32U5_GTIM_CCER_OFFSET) -#define STM32U5_TIM2_CNT (STM32U5_TIM2_BASE + STM32U5_GTIM_CNT_OFFSET) -#define STM32U5_TIM2_PSC (STM32U5_TIM2_BASE + STM32U5_GTIM_PSC_OFFSET) -#define STM32U5_TIM2_ARR (STM32U5_TIM2_BASE + STM32U5_GTIM_ARR_OFFSET) -#define STM32U5_TIM2_CCR1 (STM32U5_TIM2_BASE + STM32U5_GTIM_CCR1_OFFSET) -#define STM32U5_TIM2_CCR2 (STM32U5_TIM2_BASE + STM32U5_GTIM_CCR2_OFFSET) -#define STM32U5_TIM2_CCR3 (STM32U5_TIM2_BASE + STM32U5_GTIM_CCR3_OFFSET) -#define STM32U5_TIM2_CCR4 (STM32U5_TIM2_BASE + STM32U5_GTIM_CCR4_OFFSET) -#define STM32U5_TIM2_DCR (STM32U5_TIM2_BASE + STM32U5_GTIM_DCR_OFFSET) -#define STM32U5_TIM2_DMAR (STM32U5_TIM2_BASE + STM32U5_GTIM_DMAR_OFFSET) -#define STM32U5_TIM2_OR (STM32U5_TIM2_BASE + STM32U5_GTIM_OR_OFFSET) - -#define STM32U5_TIM3_CR1 (STM32U5_TIM3_BASE + STM32U5_GTIM_CR1_OFFSET) -#define STM32U5_TIM3_CR2 (STM32U5_TIM3_BASE + STM32U5_GTIM_CR2_OFFSET) -#define STM32U5_TIM3_SMCR (STM32U5_TIM3_BASE + STM32U5_GTIM_SMCR_OFFSET) -#define STM32U5_TIM3_DIER (STM32U5_TIM3_BASE + STM32U5_GTIM_DIER_OFFSET) -#define STM32U5_TIM3_SR (STM32U5_TIM3_BASE + STM32U5_GTIM_SR_OFFSET) -#define STM32U5_TIM3_EGR (STM32U5_TIM3_BASE + STM32U5_GTIM_EGR_OFFSET) -#define STM32U5_TIM3_CCMR1 (STM32U5_TIM3_BASE + STM32U5_GTIM_CCMR1_OFFSET) -#define STM32U5_TIM3_CCMR2 (STM32U5_TIM3_BASE + STM32U5_GTIM_CCMR2_OFFSET) -#define STM32U5_TIM3_CCER (STM32U5_TIM3_BASE + STM32U5_GTIM_CCER_OFFSET) -#define STM32U5_TIM3_CNT (STM32U5_TIM3_BASE + STM32U5_GTIM_CNT_OFFSET) -#define STM32U5_TIM3_PSC (STM32U5_TIM3_BASE + STM32U5_GTIM_PSC_OFFSET) -#define STM32U5_TIM3_ARR (STM32U5_TIM3_BASE + STM32U5_GTIM_ARR_OFFSET) -#define STM32U5_TIM3_CCR1 (STM32U5_TIM3_BASE + STM32U5_GTIM_CCR1_OFFSET) -#define STM32U5_TIM3_CCR2 (STM32U5_TIM3_BASE + STM32U5_GTIM_CCR2_OFFSET) -#define STM32U5_TIM3_CCR3 (STM32U5_TIM3_BASE + STM32U5_GTIM_CCR3_OFFSET) -#define STM32U5_TIM3_CCR4 (STM32U5_TIM3_BASE + STM32U5_GTIM_CCR4_OFFSET) -#define STM32U5_TIM3_DCR (STM32U5_TIM3_BASE + STM32U5_GTIM_DCR_OFFSET) -#define STM32U5_TIM3_DMAR (STM32U5_TIM3_BASE + STM32U5_GTIM_DMAR_OFFSET) - -#define STM32U5_TIM4_CR1 (STM32U5_TIM4_BASE + STM32U5_GTIM_CR1_OFFSET) -#define STM32U5_TIM4_CR2 (STM32U5_TIM4_BASE + STM32U5_GTIM_CR2_OFFSET) -#define STM32U5_TIM4_SMCR (STM32U5_TIM4_BASE + STM32U5_GTIM_SMCR_OFFSET) -#define STM32U5_TIM4_DIER (STM32U5_TIM4_BASE + STM32U5_GTIM_DIER_OFFSET) -#define STM32U5_TIM4_SR (STM32U5_TIM4_BASE + STM32U5_GTIM_SR_OFFSET) -#define STM32U5_TIM4_EGR (STM32U5_TIM4_BASE + STM32U5_GTIM_EGR_OFFSET) -#define STM32U5_TIM4_CCMR1 (STM32U5_TIM4_BASE + STM32U5_GTIM_CCMR1_OFFSET) -#define STM32U5_TIM4_CCMR2 (STM32U5_TIM4_BASE + STM32U5_GTIM_CCMR2_OFFSET) -#define STM32U5_TIM4_CCER (STM32U5_TIM4_BASE + STM32U5_GTIM_CCER_OFFSET) -#define STM32U5_TIM4_CNT (STM32U5_TIM4_BASE + STM32U5_GTIM_CNT_OFFSET) -#define STM32U5_TIM4_PSC (STM32U5_TIM4_BASE + STM32U5_GTIM_PSC_OFFSET) -#define STM32U5_TIM4_ARR (STM32U5_TIM4_BASE + STM32U5_GTIM_ARR_OFFSET) -#define STM32U5_TIM4_CCR1 (STM32U5_TIM4_BASE + STM32U5_GTIM_CCR1_OFFSET) -#define STM32U5_TIM4_CCR2 (STM32U5_TIM4_BASE + STM32U5_GTIM_CCR2_OFFSET) -#define STM32U5_TIM4_CCR3 (STM32U5_TIM4_BASE + STM32U5_GTIM_CCR3_OFFSET) -#define STM32U5_TIM4_CCR4 (STM32U5_TIM4_BASE + STM32U5_GTIM_CCR4_OFFSET) -#define STM32U5_TIM4_DCR (STM32U5_TIM4_BASE + STM32U5_GTIM_DCR_OFFSET) -#define STM32U5_TIM4_DMAR (STM32U5_TIM4_BASE + STM32U5_GTIM_DMAR_OFFSET) - -#define STM32U5_TIM5_CR1 (STM32U5_TIM5_BASE + STM32U5_GTIM_CR1_OFFSET) -#define STM32U5_TIM5_CR2 (STM32U5_TIM5_BASE + STM32U5_GTIM_CR2_OFFSET) -#define STM32U5_TIM5_SMCR (STM32U5_TIM5_BASE + STM32U5_GTIM_SMCR_OFFSET) -#define STM32U5_TIM5_DIER (STM32U5_TIM5_BASE + STM32U5_GTIM_DIER_OFFSET) -#define STM32U5_TIM5_SR (STM32U5_TIM5_BASE + STM32U5_GTIM_SR_OFFSET) -#define STM32U5_TIM5_EGR (STM32U5_TIM5_BASE + STM32U5_GTIM_EGR_OFFSET) -#define STM32U5_TIM5_CCMR1 (STM32U5_TIM5_BASE + STM32U5_GTIM_CCMR1_OFFSET) -#define STM32U5_TIM5_CCMR2 (STM32U5_TIM5_BASE + STM32U5_GTIM_CCMR2_OFFSET) -#define STM32U5_TIM5_CCER (STM32U5_TIM5_BASE + STM32U5_GTIM_CCER_OFFSET) -#define STM32U5_TIM5_CNT (STM32U5_TIM5_BASE + STM32U5_GTIM_CNT_OFFSET) -#define STM32U5_TIM5_PSC (STM32U5_TIM5_BASE + STM32U5_GTIM_PSC_OFFSET) -#define STM32U5_TIM5_ARR (STM32U5_TIM5_BASE + STM32U5_GTIM_ARR_OFFSET) -#define STM32U5_TIM5_CCR1 (STM32U5_TIM5_BASE + STM32U5_GTIM_CCR1_OFFSET) -#define STM32U5_TIM5_CCR2 (STM32U5_TIM5_BASE + STM32U5_GTIM_CCR2_OFFSET) -#define STM32U5_TIM5_CCR3 (STM32U5_TIM5_BASE + STM32U5_GTIM_CCR3_OFFSET) -#define STM32U5_TIM5_CCR4 (STM32U5_TIM5_BASE + STM32U5_GTIM_CCR4_OFFSET) -#define STM32U5_TIM5_DCR (STM32U5_TIM5_BASE + STM32U5_GTIM_DCR_OFFSET) -#define STM32U5_TIM5_DMAR (STM32U5_TIM5_BASE + STM32U5_GTIM_DMAR_OFFSET) -#define STM32U5_TIM5_OR (STM32U5_TIM5_BASE + STM32U5_GTIM_OR_OFFSET) - -#define STM32U5_TIM15_CR1 (STM32U5_TIM15_BASE + STM32U5_GTIM_CR1_OFFSET) -#define STM32U5_TIM15_CR2 (STM32U5_TIM15_BASE + STM32U5_GTIM_CR2_OFFSET) -#define STM32U5_TIM15_SMCR (STM32U5_TIM15_BASE + STM32U5_GTIM_SMCR_OFFSET) -#define STM32U5_TIM15_DIER (STM32U5_TIM15_BASE + STM32U5_GTIM_DIER_OFFSET) -#define STM32U5_TIM15_SR (STM32U5_TIM15_BASE + STM32U5_GTIM_SR_OFFSET) -#define STM32U5_TIM15_EGR (STM32U5_TIM15_BASE + STM32U5_GTIM_EGR_OFFSET) -#define STM32U5_TIM15_CCMR1 (STM32U5_TIM15_BASE + STM32U5_GTIM_CCMR1_OFFSET) -#define STM32U5_TIM15_CCER (STM32U5_TIM15_BASE + STM32U5_GTIM_CCER_OFFSET) -#define STM32U5_TIM15_CNT (STM32U5_TIM15_BASE + STM32U5_GTIM_CNT_OFFSET) -#define STM32U5_TIM15_PSC (STM32U5_TIM15_BASE + STM32U5_GTIM_PSC_OFFSET) -#define STM32U5_TIM15_ARR (STM32U5_TIM15_BASE + STM32U5_GTIM_ARR_OFFSET) -#define STM32U5_TIM15_RCR (STM32U5_TIM15_BASE + STM32U5_GTIM_RCR_OFFSET) -#define STM32U5_TIM15_CCR1 (STM32U5_TIM15_BASE + STM32U5_GTIM_CCR1_OFFSET) -#define STM32U5_TIM15_CCR2 (STM32U5_TIM15_BASE + STM32U5_GTIM_CCR2_OFFSET) -#define STM32U5_TIM15_BDTR (STM32U5_TIM15_BASE + STM32U5_GTIM_BDTR_OFFSET) -#define STM32U5_TIM15_DCR (STM32U5_TIM15_BASE + STM32U5_GTIM_DCR_OFFSET) -#define STM32U5_TIM15_DMAR (STM32U5_TIM15_BASE + STM32U5_GTIM_DMAR_OFFSET) - -#define STM32U5_TIM16_CR1 (STM32U5_TIM16_BASE + STM32U5_GTIM_CR1_OFFSET) -#define STM32U5_TIM16_CR2 (STM32U5_TIM16_BASE + STM32U5_GTIM_CR2_OFFSET) -#define STM32U5_TIM16_DIER (STM32U5_TIM16_BASE + STM32U5_GTIM_DIER_OFFSET) -#define STM32U5_TIM16_SR (STM32U5_TIM16_BASE + STM32U5_GTIM_SR_OFFSET) -#define STM32U5_TIM16_EGR (STM32U5_TIM16_BASE + STM32U5_GTIM_EGR_OFFSET) -#define STM32U5_TIM16_CCMR1 (STM32U5_TIM16_BASE + STM32U5_GTIM_CCMR1_OFFSET) -#define STM32U5_TIM16_CCER (STM32U5_TIM16_BASE + STM32U5_GTIM_CCER_OFFSET) -#define STM32U5_TIM16_CNT (STM32U5_TIM16_BASE + STM32U5_GTIM_CNT_OFFSET) -#define STM32U5_TIM16_PSC (STM32U5_TIM16_BASE + STM32U5_GTIM_PSC_OFFSET) -#define STM32U5_TIM16_ARR (STM32U5_TIM16_BASE + STM32U5_GTIM_ARR_OFFSET) -#define STM32U5_TIM16_RCR (STM32U5_TIM16_BASE + STM32U5_GTIM_RCR_OFFSET) -#define STM32U5_TIM16_CCR1 (STM32U5_TIM16_BASE + STM32U5_GTIM_CCR1_OFFSET) -#define STM32U5_TIM16_BDTR (STM32U5_TIM16_BASE + STM32U5_GTIM_BDTR_OFFSET) -#define STM32U5_TIM16_DCR (STM32U5_TIM16_BASE + STM32U5_GTIM_DCR_OFFSET) -#define STM32U5_TIM16_DMAR (STM32U5_TIM16_BASE + STM32U5_GTIM_DMAR_OFFSET) -#define STM32U5_TIM16_OR (STM32U5_TIM16_BASE + STM32U5_GTIM_OR_OFFSET) - -#define STM32U5_TIM17_CR1 (STM32U5_TIM17_BASE + STM32U5_GTIM_CR1_OFFSET) -#define STM32U5_TIM17_CR2 (STM32U5_TIM17_BASE + STM32U5_GTIM_CR2_OFFSET) -#define STM32U5_TIM17_DIER (STM32U5_TIM17_BASE + STM32U5_GTIM_DIER_OFFSET) -#define STM32U5_TIM17_SR (STM32U5_TIM17_BASE + STM32U5_GTIM_SR_OFFSET) -#define STM32U5_TIM17_EGR (STM32U5_TIM17_BASE + STM32U5_GTIM_EGR_OFFSET) -#define STM32U5_TIM17_CCMR1 (STM32U5_TIM17_BASE + STM32U5_GTIM_CCMR1_OFFSET) -#define STM32U5_TIM17_CCER (STM32U5_TIM17_BASE + STM32U5_GTIM_CCER_OFFSET) -#define STM32U5_TIM17_CNT (STM32U5_TIM17_BASE + STM32U5_GTIM_CNT_OFFSET) -#define STM32U5_TIM17_PSC (STM32U5_TIM17_BASE + STM32U5_GTIM_PSC_OFFSET) -#define STM32U5_TIM17_ARR (STM32U5_TIM17_BASE + STM32U5_GTIM_ARR_OFFSET) -#define STM32U5_TIM17_RCR (STM32U5_TIM17_BASE + STM32U5_GTIM_RCR_OFFSET) -#define STM32U5_TIM17_CCR1 (STM32U5_TIM17_BASE + STM32U5_GTIM_CCR1_OFFSET) -#define STM32U5_TIM17_BDTR (STM32U5_TIM17_BASE + STM32U5_GTIM_BDTR_OFFSET) -#define STM32U5_TIM17_DCR (STM32U5_TIM17_BASE + STM32U5_GTIM_DCR_OFFSET) -#define STM32U5_TIM17_DMAR (STM32U5_TIM17_BASE + STM32U5_GTIM_DMAR_OFFSET) +#define STM32_TIM2_CR1 (STM32_TIM2_BASE + STM32_GTIM_CR1_OFFSET) +#define STM32_TIM2_CR2 (STM32_TIM2_BASE + STM32_GTIM_CR2_OFFSET) +#define STM32_TIM2_SMCR (STM32_TIM2_BASE + STM32_GTIM_SMCR_OFFSET) +#define STM32_TIM2_DIER (STM32_TIM2_BASE + STM32_GTIM_DIER_OFFSET) +#define STM32_TIM2_SR (STM32_TIM2_BASE + STM32_GTIM_SR_OFFSET) +#define STM32_TIM2_EGR (STM32_TIM2_BASE + STM32_GTIM_EGR_OFFSET) +#define STM32_TIM2_CCMR1 (STM32_TIM2_BASE + STM32_GTIM_CCMR1_OFFSET) +#define STM32_TIM2_CCMR2 (STM32_TIM2_BASE + STM32_GTIM_CCMR2_OFFSET) +#define STM32_TIM2_CCER (STM32_TIM2_BASE + STM32_GTIM_CCER_OFFSET) +#define STM32_TIM2_CNT (STM32_TIM2_BASE + STM32_GTIM_CNT_OFFSET) +#define STM32_TIM2_PSC (STM32_TIM2_BASE + STM32_GTIM_PSC_OFFSET) +#define STM32_TIM2_ARR (STM32_TIM2_BASE + STM32_GTIM_ARR_OFFSET) +#define STM32_TIM2_CCR1 (STM32_TIM2_BASE + STM32_GTIM_CCR1_OFFSET) +#define STM32_TIM2_CCR2 (STM32_TIM2_BASE + STM32_GTIM_CCR2_OFFSET) +#define STM32_TIM2_CCR3 (STM32_TIM2_BASE + STM32_GTIM_CCR3_OFFSET) +#define STM32_TIM2_CCR4 (STM32_TIM2_BASE + STM32_GTIM_CCR4_OFFSET) +#define STM32_TIM2_DCR (STM32_TIM2_BASE + STM32_GTIM_DCR_OFFSET) +#define STM32_TIM2_DMAR (STM32_TIM2_BASE + STM32_GTIM_DMAR_OFFSET) +#define STM32_TIM2_OR (STM32_TIM2_BASE + STM32_GTIM_OR_OFFSET) + +#define STM32_TIM3_CR1 (STM32_TIM3_BASE + STM32_GTIM_CR1_OFFSET) +#define STM32_TIM3_CR2 (STM32_TIM3_BASE + STM32_GTIM_CR2_OFFSET) +#define STM32_TIM3_SMCR (STM32_TIM3_BASE + STM32_GTIM_SMCR_OFFSET) +#define STM32_TIM3_DIER (STM32_TIM3_BASE + STM32_GTIM_DIER_OFFSET) +#define STM32_TIM3_SR (STM32_TIM3_BASE + STM32_GTIM_SR_OFFSET) +#define STM32_TIM3_EGR (STM32_TIM3_BASE + STM32_GTIM_EGR_OFFSET) +#define STM32_TIM3_CCMR1 (STM32_TIM3_BASE + STM32_GTIM_CCMR1_OFFSET) +#define STM32_TIM3_CCMR2 (STM32_TIM3_BASE + STM32_GTIM_CCMR2_OFFSET) +#define STM32_TIM3_CCER (STM32_TIM3_BASE + STM32_GTIM_CCER_OFFSET) +#define STM32_TIM3_CNT (STM32_TIM3_BASE + STM32_GTIM_CNT_OFFSET) +#define STM32_TIM3_PSC (STM32_TIM3_BASE + STM32_GTIM_PSC_OFFSET) +#define STM32_TIM3_ARR (STM32_TIM3_BASE + STM32_GTIM_ARR_OFFSET) +#define STM32_TIM3_CCR1 (STM32_TIM3_BASE + STM32_GTIM_CCR1_OFFSET) +#define STM32_TIM3_CCR2 (STM32_TIM3_BASE + STM32_GTIM_CCR2_OFFSET) +#define STM32_TIM3_CCR3 (STM32_TIM3_BASE + STM32_GTIM_CCR3_OFFSET) +#define STM32_TIM3_CCR4 (STM32_TIM3_BASE + STM32_GTIM_CCR4_OFFSET) +#define STM32_TIM3_DCR (STM32_TIM3_BASE + STM32_GTIM_DCR_OFFSET) +#define STM32_TIM3_DMAR (STM32_TIM3_BASE + STM32_GTIM_DMAR_OFFSET) + +#define STM32_TIM4_CR1 (STM32_TIM4_BASE + STM32_GTIM_CR1_OFFSET) +#define STM32_TIM4_CR2 (STM32_TIM4_BASE + STM32_GTIM_CR2_OFFSET) +#define STM32_TIM4_SMCR (STM32_TIM4_BASE + STM32_GTIM_SMCR_OFFSET) +#define STM32_TIM4_DIER (STM32_TIM4_BASE + STM32_GTIM_DIER_OFFSET) +#define STM32_TIM4_SR (STM32_TIM4_BASE + STM32_GTIM_SR_OFFSET) +#define STM32_TIM4_EGR (STM32_TIM4_BASE + STM32_GTIM_EGR_OFFSET) +#define STM32_TIM4_CCMR1 (STM32_TIM4_BASE + STM32_GTIM_CCMR1_OFFSET) +#define STM32_TIM4_CCMR2 (STM32_TIM4_BASE + STM32_GTIM_CCMR2_OFFSET) +#define STM32_TIM4_CCER (STM32_TIM4_BASE + STM32_GTIM_CCER_OFFSET) +#define STM32_TIM4_CNT (STM32_TIM4_BASE + STM32_GTIM_CNT_OFFSET) +#define STM32_TIM4_PSC (STM32_TIM4_BASE + STM32_GTIM_PSC_OFFSET) +#define STM32_TIM4_ARR (STM32_TIM4_BASE + STM32_GTIM_ARR_OFFSET) +#define STM32_TIM4_CCR1 (STM32_TIM4_BASE + STM32_GTIM_CCR1_OFFSET) +#define STM32_TIM4_CCR2 (STM32_TIM4_BASE + STM32_GTIM_CCR2_OFFSET) +#define STM32_TIM4_CCR3 (STM32_TIM4_BASE + STM32_GTIM_CCR3_OFFSET) +#define STM32_TIM4_CCR4 (STM32_TIM4_BASE + STM32_GTIM_CCR4_OFFSET) +#define STM32_TIM4_DCR (STM32_TIM4_BASE + STM32_GTIM_DCR_OFFSET) +#define STM32_TIM4_DMAR (STM32_TIM4_BASE + STM32_GTIM_DMAR_OFFSET) + +#define STM32_TIM5_CR1 (STM32_TIM5_BASE + STM32_GTIM_CR1_OFFSET) +#define STM32_TIM5_CR2 (STM32_TIM5_BASE + STM32_GTIM_CR2_OFFSET) +#define STM32_TIM5_SMCR (STM32_TIM5_BASE + STM32_GTIM_SMCR_OFFSET) +#define STM32_TIM5_DIER (STM32_TIM5_BASE + STM32_GTIM_DIER_OFFSET) +#define STM32_TIM5_SR (STM32_TIM5_BASE + STM32_GTIM_SR_OFFSET) +#define STM32_TIM5_EGR (STM32_TIM5_BASE + STM32_GTIM_EGR_OFFSET) +#define STM32_TIM5_CCMR1 (STM32_TIM5_BASE + STM32_GTIM_CCMR1_OFFSET) +#define STM32_TIM5_CCMR2 (STM32_TIM5_BASE + STM32_GTIM_CCMR2_OFFSET) +#define STM32_TIM5_CCER (STM32_TIM5_BASE + STM32_GTIM_CCER_OFFSET) +#define STM32_TIM5_CNT (STM32_TIM5_BASE + STM32_GTIM_CNT_OFFSET) +#define STM32_TIM5_PSC (STM32_TIM5_BASE + STM32_GTIM_PSC_OFFSET) +#define STM32_TIM5_ARR (STM32_TIM5_BASE + STM32_GTIM_ARR_OFFSET) +#define STM32_TIM5_CCR1 (STM32_TIM5_BASE + STM32_GTIM_CCR1_OFFSET) +#define STM32_TIM5_CCR2 (STM32_TIM5_BASE + STM32_GTIM_CCR2_OFFSET) +#define STM32_TIM5_CCR3 (STM32_TIM5_BASE + STM32_GTIM_CCR3_OFFSET) +#define STM32_TIM5_CCR4 (STM32_TIM5_BASE + STM32_GTIM_CCR4_OFFSET) +#define STM32_TIM5_DCR (STM32_TIM5_BASE + STM32_GTIM_DCR_OFFSET) +#define STM32_TIM5_DMAR (STM32_TIM5_BASE + STM32_GTIM_DMAR_OFFSET) +#define STM32_TIM5_OR (STM32_TIM5_BASE + STM32_GTIM_OR_OFFSET) + +#define STM32_TIM15_CR1 (STM32_TIM15_BASE + STM32_GTIM_CR1_OFFSET) +#define STM32_TIM15_CR2 (STM32_TIM15_BASE + STM32_GTIM_CR2_OFFSET) +#define STM32_TIM15_SMCR (STM32_TIM15_BASE + STM32_GTIM_SMCR_OFFSET) +#define STM32_TIM15_DIER (STM32_TIM15_BASE + STM32_GTIM_DIER_OFFSET) +#define STM32_TIM15_SR (STM32_TIM15_BASE + STM32_GTIM_SR_OFFSET) +#define STM32_TIM15_EGR (STM32_TIM15_BASE + STM32_GTIM_EGR_OFFSET) +#define STM32_TIM15_CCMR1 (STM32_TIM15_BASE + STM32_GTIM_CCMR1_OFFSET) +#define STM32_TIM15_CCER (STM32_TIM15_BASE + STM32_GTIM_CCER_OFFSET) +#define STM32_TIM15_CNT (STM32_TIM15_BASE + STM32_GTIM_CNT_OFFSET) +#define STM32_TIM15_PSC (STM32_TIM15_BASE + STM32_GTIM_PSC_OFFSET) +#define STM32_TIM15_ARR (STM32_TIM15_BASE + STM32_GTIM_ARR_OFFSET) +#define STM32_TIM15_RCR (STM32_TIM15_BASE + STM32_GTIM_RCR_OFFSET) +#define STM32_TIM15_CCR1 (STM32_TIM15_BASE + STM32_GTIM_CCR1_OFFSET) +#define STM32_TIM15_CCR2 (STM32_TIM15_BASE + STM32_GTIM_CCR2_OFFSET) +#define STM32_TIM15_BDTR (STM32_TIM15_BASE + STM32_GTIM_BDTR_OFFSET) +#define STM32_TIM15_DCR (STM32_TIM15_BASE + STM32_GTIM_DCR_OFFSET) +#define STM32_TIM15_DMAR (STM32_TIM15_BASE + STM32_GTIM_DMAR_OFFSET) + +#define STM32_TIM16_CR1 (STM32_TIM16_BASE + STM32_GTIM_CR1_OFFSET) +#define STM32_TIM16_CR2 (STM32_TIM16_BASE + STM32_GTIM_CR2_OFFSET) +#define STM32_TIM16_DIER (STM32_TIM16_BASE + STM32_GTIM_DIER_OFFSET) +#define STM32_TIM16_SR (STM32_TIM16_BASE + STM32_GTIM_SR_OFFSET) +#define STM32_TIM16_EGR (STM32_TIM16_BASE + STM32_GTIM_EGR_OFFSET) +#define STM32_TIM16_CCMR1 (STM32_TIM16_BASE + STM32_GTIM_CCMR1_OFFSET) +#define STM32_TIM16_CCER (STM32_TIM16_BASE + STM32_GTIM_CCER_OFFSET) +#define STM32_TIM16_CNT (STM32_TIM16_BASE + STM32_GTIM_CNT_OFFSET) +#define STM32_TIM16_PSC (STM32_TIM16_BASE + STM32_GTIM_PSC_OFFSET) +#define STM32_TIM16_ARR (STM32_TIM16_BASE + STM32_GTIM_ARR_OFFSET) +#define STM32_TIM16_RCR (STM32_TIM16_BASE + STM32_GTIM_RCR_OFFSET) +#define STM32_TIM16_CCR1 (STM32_TIM16_BASE + STM32_GTIM_CCR1_OFFSET) +#define STM32_TIM16_BDTR (STM32_TIM16_BASE + STM32_GTIM_BDTR_OFFSET) +#define STM32_TIM16_DCR (STM32_TIM16_BASE + STM32_GTIM_DCR_OFFSET) +#define STM32_TIM16_DMAR (STM32_TIM16_BASE + STM32_GTIM_DMAR_OFFSET) +#define STM32_TIM16_OR (STM32_TIM16_BASE + STM32_GTIM_OR_OFFSET) + +#define STM32_TIM17_CR1 (STM32_TIM17_BASE + STM32_GTIM_CR1_OFFSET) +#define STM32_TIM17_CR2 (STM32_TIM17_BASE + STM32_GTIM_CR2_OFFSET) +#define STM32_TIM17_DIER (STM32_TIM17_BASE + STM32_GTIM_DIER_OFFSET) +#define STM32_TIM17_SR (STM32_TIM17_BASE + STM32_GTIM_SR_OFFSET) +#define STM32_TIM17_EGR (STM32_TIM17_BASE + STM32_GTIM_EGR_OFFSET) +#define STM32_TIM17_CCMR1 (STM32_TIM17_BASE + STM32_GTIM_CCMR1_OFFSET) +#define STM32_TIM17_CCER (STM32_TIM17_BASE + STM32_GTIM_CCER_OFFSET) +#define STM32_TIM17_CNT (STM32_TIM17_BASE + STM32_GTIM_CNT_OFFSET) +#define STM32_TIM17_PSC (STM32_TIM17_BASE + STM32_GTIM_PSC_OFFSET) +#define STM32_TIM17_ARR (STM32_TIM17_BASE + STM32_GTIM_ARR_OFFSET) +#define STM32_TIM17_RCR (STM32_TIM17_BASE + STM32_GTIM_RCR_OFFSET) +#define STM32_TIM17_CCR1 (STM32_TIM17_BASE + STM32_GTIM_CCR1_OFFSET) +#define STM32_TIM17_BDTR (STM32_TIM17_BASE + STM32_GTIM_BDTR_OFFSET) +#define STM32_TIM17_DCR (STM32_TIM17_BASE + STM32_GTIM_DCR_OFFSET) +#define STM32_TIM17_DMAR (STM32_TIM17_BASE + STM32_GTIM_DMAR_OFFSET) /* Basic Timers - TIM6 and TIM7 */ -#define STM32U5_TIM6_CR1 (STM32U5_TIM6_BASE + STM32U5_BTIM_CR1_OFFSET) -#define STM32U5_TIM6_CR2 (STM32U5_TIM6_BASE + STM32U5_BTIM_CR2_OFFSET) -#define STM32U5_TIM6_DIER (STM32U5_TIM6_BASE + STM32U5_BTIM_DIER_OFFSET) -#define STM32U5_TIM6_SR (STM32U5_TIM6_BASE + STM32U5_BTIM_SR_OFFSET) -#define STM32U5_TIM6_EGR (STM32U5_TIM6_BASE + STM32U5_BTIM_EGR_OFFSET) -#define STM32U5_TIM6_CNT (STM32U5_TIM6_BASE + STM32U5_BTIM_CNT_OFFSET) -#define STM32U5_TIM6_PSC (STM32U5_TIM6_BASE + STM32U5_BTIM_PSC_OFFSET) -#define STM32U5_TIM6_ARR (STM32U5_TIM6_BASE + STM32U5_BTIM_ARR_OFFSET) - -#define STM32U5_TIM7_CR1 (STM32U5_TIM7_BASE + STM32U5_BTIM_CR1_OFFSET) -#define STM32U5_TIM7_CR2 (STM32U5_TIM7_BASE + STM32U5_BTIM_CR2_OFFSET) -#define STM32U5_TIM7_DIER (STM32U5_TIM7_BASE + STM32U5_BTIM_DIER_OFFSET) -#define STM32U5_TIM7_SR (STM32U5_TIM7_BASE + STM32U5_BTIM_SR_OFFSET) -#define STM32U5_TIM7_EGR (STM32U5_TIM7_BASE + STM32U5_BTIM_EGR_OFFSET) -#define STM32U5_TIM7_CNT (STM32U5_TIM7_BASE + STM32U5_BTIM_CNT_OFFSET) -#define STM32U5_TIM7_PSC (STM32U5_TIM7_BASE + STM32U5_BTIM_PSC_OFFSET) -#define STM32U5_TIM7_ARR (STM32U5_TIM7_BASE + STM32U5_BTIM_ARR_OFFSET) +#define STM32_TIM6_CR1 (STM32_TIM6_BASE + STM32_BTIM_CR1_OFFSET) +#define STM32_TIM6_CR2 (STM32_TIM6_BASE + STM32_BTIM_CR2_OFFSET) +#define STM32_TIM6_DIER (STM32_TIM6_BASE + STM32_BTIM_DIER_OFFSET) +#define STM32_TIM6_SR (STM32_TIM6_BASE + STM32_BTIM_SR_OFFSET) +#define STM32_TIM6_EGR (STM32_TIM6_BASE + STM32_BTIM_EGR_OFFSET) +#define STM32_TIM6_CNT (STM32_TIM6_BASE + STM32_BTIM_CNT_OFFSET) +#define STM32_TIM6_PSC (STM32_TIM6_BASE + STM32_BTIM_PSC_OFFSET) +#define STM32_TIM6_ARR (STM32_TIM6_BASE + STM32_BTIM_ARR_OFFSET) + +#define STM32_TIM7_CR1 (STM32_TIM7_BASE + STM32_BTIM_CR1_OFFSET) +#define STM32_TIM7_CR2 (STM32_TIM7_BASE + STM32_BTIM_CR2_OFFSET) +#define STM32_TIM7_DIER (STM32_TIM7_BASE + STM32_BTIM_DIER_OFFSET) +#define STM32_TIM7_SR (STM32_TIM7_BASE + STM32_BTIM_SR_OFFSET) +#define STM32_TIM7_EGR (STM32_TIM7_BASE + STM32_BTIM_EGR_OFFSET) +#define STM32_TIM7_CNT (STM32_TIM7_BASE + STM32_BTIM_CNT_OFFSET) +#define STM32_TIM7_PSC (STM32_TIM7_BASE + STM32_BTIM_PSC_OFFSET) +#define STM32_TIM7_ARR (STM32_TIM7_BASE + STM32_BTIM_ARR_OFFSET) /* Register Bitfield Definitions ********************************************/ diff --git a/arch/arm/src/stm32u5/hardware/stm32u5xx_rcc.h b/arch/arm/src/stm32u5/hardware/stm32u5xx_rcc.h index a106a9e574c6e..f78e13bfccdc5 100644 --- a/arch/arm/src/stm32u5/hardware/stm32u5xx_rcc.h +++ b/arch/arm/src/stm32u5/hardware/stm32u5xx_rcc.h @@ -29,10 +29,10 @@ #include -#if defined(CONFIG_STM32U5_STM32U535XX) || defined(CONFIG_STM32U5_STM32U545XX) || \ - defined(CONFIG_STM32U5_STM32U575XX) || defined(CONFIG_STM32U5_STM32U585XX) || \ - defined(CONFIG_STM32U5_STM32U59XX) || defined(CONFIG_STM32U5_STM32U59AXX) || \ - defined(CONFIG_STM32U5_STM32U5A5XX) || defined(CONFIG_STM32U5_STM32U5A9XX) +#if defined(CONFIG_STM32_STM32U535XX) || defined(CONFIG_STM32_STM32U545XX) || \ + defined(CONFIG_STM32_STM32U575XX) || defined(CONFIG_STM32_STM32U585XX) || \ + defined(CONFIG_STM32_STM32U59XX) || defined(CONFIG_STM32_STM32U59AXX) || \ + defined(CONFIG_STM32_STM32U5A5XX) || defined(CONFIG_STM32_STM32U5A9XX) /**************************************************************************** * Pre-processor Definitions @@ -1254,5 +1254,5 @@ # define RCC_CCIPR2_OSPISEL_MSI (1 << RCC_CCIPR2_OSPISEL_SHIFT) # define RCC_CCIPR2_OSPISEL_PLL48M1CLK (2 << RCC_CCIPR2_OSPISEL_SHIFT) -#endif /* CONFIG_STM32U5_STM32U5XX */ +#endif /* CONFIG_STM32_STM32U5XX */ #endif /* __ARCH_ARM_SRC_STM32U5_HARDWARE_STM32U5XX_RCC_H */ diff --git a/arch/arm/src/stm32u5/hardware/stm32u5xx_spi.h b/arch/arm/src/stm32u5/hardware/stm32u5xx_spi.h index e7d98a97aec2d..e79a2bf2daa90 100644 --- a/arch/arm/src/stm32u5/hardware/stm32u5xx_spi.h +++ b/arch/arm/src/stm32u5/hardware/stm32u5xx_spi.h @@ -29,10 +29,10 @@ #include -#if defined(CONFIG_STM32U5_STM32U535XX) || defined(CONFIG_STM32U5_STM32U545XX) || \ - defined(CONFIG_STM32U5_STM32U575XX) || defined(CONFIG_STM32U5_STM32U585XX) || \ - defined(CONFIG_STM32U5_STM32U59XX) || defined(CONFIG_STM32U5_STM32U59AXX) || \ - defined(CONFIG_STM32U5_STM32U5A5XX) || defined(CONFIG_STM32U5_STM32U5A9XX) +#if defined(CONFIG_STM32_STM32U535XX) || defined(CONFIG_STM32_STM32U545XX) || \ + defined(CONFIG_STM32_STM32U575XX) || defined(CONFIG_STM32_STM32U585XX) || \ + defined(CONFIG_STM32_STM32U59XX) || defined(CONFIG_STM32_STM32U59AXX) || \ + defined(CONFIG_STM32_STM32U5A5XX) || defined(CONFIG_STM32_STM32U5A9XX) /**************************************************************************** * Pre-processor Definitions @@ -408,5 +408,5 @@ #define SPI_UDRDR_UDRDR_MASK (0xffff << SPI_UDRDR_UDRDR_SHIFT) /* Bits 16-31: read zero */ -#endif /* CONFIG_STM32U5_STM32U5XX ... */ +#endif /* CONFIG_STM32_STM32U5XX ... */ #endif /* __ARCH_ARM_SRC_STM32U5_HARDWARE_STM32U5XX_SPI_H */ diff --git a/arch/arm/src/stm32u5/hardware/stm32u5xx_syscfg.h b/arch/arm/src/stm32u5/hardware/stm32u5xx_syscfg.h index 56fc25f062412..3cb7aec33dcc3 100644 --- a/arch/arm/src/stm32u5/hardware/stm32u5xx_syscfg.h +++ b/arch/arm/src/stm32u5/hardware/stm32u5xx_syscfg.h @@ -30,10 +30,10 @@ #include #include "chip.h" -#if defined(CONFIG_STM32U5_STM32U535XX) || defined(CONFIG_STM32U5_STM32U545XX) || \ - defined(CONFIG_STM32U5_STM32U575XX) || defined(CONFIG_STM32U5_STM32U585XX) || \ - defined(CONFIG_STM32U5_STM32U59XX) || defined(CONFIG_STM32U5_STM32U59AXX) || \ - defined(CONFIG_STM32U5_STM32U5A5XX) || defined(CONFIG_STM32U5_STM32U5A9XX) +#if defined(CONFIG_STM32_STM32U535XX) || defined(CONFIG_STM32_STM32U545XX) || \ + defined(CONFIG_STM32_STM32U575XX) || defined(CONFIG_STM32_STM32U585XX) || \ + defined(CONFIG_STM32_STM32U59XX) || defined(CONFIG_STM32_STM32U59AXX) || \ + defined(CONFIG_STM32_STM32U5A5XX) || defined(CONFIG_STM32_STM32U5A9XX) /**************************************************************************** * Pre-processor Definitions @@ -41,31 +41,31 @@ /* Register Offsets *********************************************************/ -#define STM32U5_SYSCFG_SECCFGR_OFFSET 0x0000 /* SYSCFG secure configuration register */ -#define STM32U5_SYSCFG_CFGR1_OFFSET 0x0004 /* SYSCFG configuration register 1 */ -#define STM32U5_SYSCFG_FPUIMR_OFFSET 0x0008 /* SYSCFG FPU interrupt mask register */ -#define STM32U5_SYSCFG_CNSLCKR_OFFSET 0x000c /* SYSCFG CPU non-secure lock register */ -#define STM32U5_SYSCFG_CSLCKR_OFFSET 0x0010 /* SYSCFG CPU secure lock register */ -#define STM32U5_SYSCFG_CFGR2_OFFSET 0x0014 /* SYSCFG configuration register 2 */ -#define STM32U5_SYSCFG_SCSR_OFFSET 0x0018 /* SYSCFG SRAM2 control and status register */ -#define STM32U5_SYSCFG_SKR_OFFSET 0x001c /* SYSCFG SRAM2 key register */ -#define STM32U5_SYSCFG_SWPR_OFFSET 0x0020 /* SYSCFG SRAM2 write protection register */ -#define STM32U5_SYSCFG_SWPR2_OFFSET 0x0024 /* SYSCFG SRAM2 write protection register 2 */ -#define STM32U5_SYSCFG_RSSCMDR_OFFSET 0x002c /* SYSCFG RSS command register */ +#define STM32_SYSCFG_SECCFGR_OFFSET 0x0000 /* SYSCFG secure configuration register */ +#define STM32_SYSCFG_CFGR1_OFFSET 0x0004 /* SYSCFG configuration register 1 */ +#define STM32_SYSCFG_FPUIMR_OFFSET 0x0008 /* SYSCFG FPU interrupt mask register */ +#define STM32_SYSCFG_CNSLCKR_OFFSET 0x000c /* SYSCFG CPU non-secure lock register */ +#define STM32_SYSCFG_CSLCKR_OFFSET 0x0010 /* SYSCFG CPU secure lock register */ +#define STM32_SYSCFG_CFGR2_OFFSET 0x0014 /* SYSCFG configuration register 2 */ +#define STM32_SYSCFG_SCSR_OFFSET 0x0018 /* SYSCFG SRAM2 control and status register */ +#define STM32_SYSCFG_SKR_OFFSET 0x001c /* SYSCFG SRAM2 key register */ +#define STM32_SYSCFG_SWPR_OFFSET 0x0020 /* SYSCFG SRAM2 write protection register */ +#define STM32_SYSCFG_SWPR2_OFFSET 0x0024 /* SYSCFG SRAM2 write protection register 2 */ +#define STM32_SYSCFG_RSSCMDR_OFFSET 0x002c /* SYSCFG RSS command register */ /* Register Addresses *******************************************************/ -#define STM32U5_SYSCFG_SECCFGR (STM32U5_SYSCFG_BASE + STM32U5_SYSCFG_SECCFGR_OFFSET) -#define STM32U5_SYSCFG_CFGR1 (STM32U5_SYSCFG_BASE + STM32U5_SYSCFG_CFGR1_OFFSET) -#define STM32U5_SYSCFG_FPUIMR (STM32U5_SYSCFG_BASE + STM32U5_SYSCFG_FPUIMR_OFFSET) -#define STM32U5_SYSCFG_CNSLCKR (STM32U5_SYSCFG_BASE + STM32U5_SYSCFG_CNSLCKR_OFFSET) -#define STM32U5_SYSCFG_CSLCKR (STM32U5_SYSCFG_BASE + STM32U5_SYSCFG_CSLCKR_OFFSET) -#define STM32U5_SYSCFG_CFGR2 (STM32U5_SYSCFG_BASE + STM32U5_SYSCFG_CFGR2_OFFSET) -#define STM32U5_SYSCFG_SCSR (STM32U5_SYSCFG_BASE + STM32U5_SYSCFG_SCSR_OFFSET) -#define STM32U5_SYSCFG_SKR (STM32U5_SYSCFG_BASE + STM32U5_SYSCFG_SKR_OFFSET) -#define STM32U5_SYSCFG_SWPR (STM32U5_SYSCFG_BASE + STM32U5_SYSCFG_SWPR_OFFSET) -#define STM32U5_SYSCFG_SWPR2 (STM32U5_SYSCFG_BASE + STM32U5_SYSCFG_SWPR2_OFFSET) -#define STM32U5_SYSCFG_RSSCMDR (STM32U5_SYSCFG_BASE + STM32U5_SYSCFG_RSSCMDR_OFFSET) +#define STM32_SYSCFG_SECCFGR (STM32_SYSCFG_BASE + STM32_SYSCFG_SECCFGR_OFFSET) +#define STM32_SYSCFG_CFGR1 (STM32_SYSCFG_BASE + STM32_SYSCFG_CFGR1_OFFSET) +#define STM32_SYSCFG_FPUIMR (STM32_SYSCFG_BASE + STM32_SYSCFG_FPUIMR_OFFSET) +#define STM32_SYSCFG_CNSLCKR (STM32_SYSCFG_BASE + STM32_SYSCFG_CNSLCKR_OFFSET) +#define STM32_SYSCFG_CSLCKR (STM32_SYSCFG_BASE + STM32_SYSCFG_CSLCKR_OFFSET) +#define STM32_SYSCFG_CFGR2 (STM32_SYSCFG_BASE + STM32_SYSCFG_CFGR2_OFFSET) +#define STM32_SYSCFG_SCSR (STM32_SYSCFG_BASE + STM32_SYSCFG_SCSR_OFFSET) +#define STM32_SYSCFG_SKR (STM32_SYSCFG_BASE + STM32_SYSCFG_SKR_OFFSET) +#define STM32_SYSCFG_SWPR (STM32_SYSCFG_BASE + STM32_SYSCFG_SWPR_OFFSET) +#define STM32_SYSCFG_SWPR2 (STM32_SYSCFG_BASE + STM32_SYSCFG_SWPR2_OFFSET) +#define STM32_SYSCFG_RSSCMDR (STM32_SYSCFG_BASE + STM32_SYSCFG_RSSCMDR_OFFSET) /* Register Bitfield Definitions ********************************************/ @@ -136,5 +136,5 @@ #define SYSCFG_RSSCMDR_SHIFT 0 #define SYSCFG_RSSCMDR_MASK (0xFFFF << SYSCFG_RSSCMDR_SHIFT) -#endif /* CONFIG_STM32U5_STM32U5XX ... */ +#endif /* CONFIG_STM32_STM32U5XX ... */ #endif /* __ARCH_ARM_SRC_STM32U5_HARDWARE_STM32U5XX_SYSCFG_H */ diff --git a/arch/arm/src/stm32u5/stm32_allocateheap.c b/arch/arm/src/stm32u5/stm32_allocateheap.c index ee0220c16d893..96785ea2182d4 100644 --- a/arch/arm/src/stm32u5/stm32_allocateheap.c +++ b/arch/arm/src/stm32u5/stm32_allocateheap.c @@ -60,8 +60,8 @@ * FSMC. In order to use FSMC SRAM, the following additional things need to * be present in the NuttX configuration file: * - * CONFIG_STM32U5_FSMC=y : Enables the FSMC - * CONFIG_STM32U5_FSMC_SRAM=y : Indicates that SRAM is available via the + * CONFIG_STM32_FSMC=y : Enables the FSMC + * CONFIG_STM32_FSMC_SRAM=y : Indicates that SRAM is available via the * FSMC (as opposed to an LCD or FLASH). * CONFIG_HEAP2_BASE : The base address of the SRAM in the FSMC * address space @@ -71,8 +71,8 @@ * include the additional regions. */ -#ifndef CONFIG_STM32U5_FSMC -# undef CONFIG_STM32U5_FSMC_SRAM +#ifndef CONFIG_STM32_FSMC +# undef CONFIG_STM32_FSMC_SRAM #endif /* STM32U5[7,8]6xx have 128 Kib in two banks, both accessible to DMA: @@ -121,17 +121,17 @@ * that we have been asked to add to the heap. */ -#if CONFIG_MM_REGIONS < defined(CONFIG_STM32U5_SRAM2_HEAP) + \ - defined(CONFIG_STM32U5_SRAM3_HEAP) + \ - defined(CONFIG_STM32U5_SRAM5_HEAP) + \ - defined(CONFIG_STM32U5_FSMC_SRAM_HEAP) + 1 +#if CONFIG_MM_REGIONS < defined(CONFIG_STM32_SRAM2_HEAP) + \ + defined(CONFIG_STM32_SRAM3_HEAP) + \ + defined(CONFIG_STM32_SRAM5_HEAP) + \ + defined(CONFIG_STM32_FSMC_SRAM_HEAP) + 1 # error "You need more memory manager regions to support selected heap components" #endif -#if CONFIG_MM_REGIONS > defined(CONFIG_STM32U5_SRAM2_HEAP) + \ - defined(CONFIG_STM32U5_SRAM3_HEAP) + \ - defined(CONFIG_STM32U5_SRAM5_HEAP) + \ - defined(CONFIG_STM32U5_FSMC_SRAM_HEAP) + 1 +#if CONFIG_MM_REGIONS > defined(CONFIG_STM32_SRAM2_HEAP) + \ + defined(CONFIG_STM32_SRAM3_HEAP) + \ + defined(CONFIG_STM32_SRAM5_HEAP) + \ + defined(CONFIG_STM32_FSMC_SRAM_HEAP) + 1 # warning "CONFIG_MM_REGIONS large enough but I do not know what some of the region(s) are" #endif @@ -140,10 +140,10 @@ * configuration (as CONFIG_HEAP2_BASE and CONFIG_HEAP2_SIZE). */ -#ifdef CONFIG_STM32U5_FSMC_SRAM +#ifdef CONFIG_STM32_FSMC_SRAM # if !defined(CONFIG_HEAP2_BASE) || !defined(CONFIG_HEAP2_SIZE) # error "CONFIG_HEAP2_BASE and CONFIG_HEAP2_SIZE must be provided" -# undef CONFIG_STM32U5_FSMC_SRAM +# undef CONFIG_STM32_FSMC_SRAM # endif #endif @@ -319,7 +319,7 @@ void up_allocate_kheap(void **heap_start, size_t *heap_size) #if CONFIG_MM_REGIONS > 1 void arm_addregion(void) { -#ifdef CONFIG_STM32U5_SRAM2_HEAP +#ifdef CONFIG_STM32_SRAM2_HEAP # if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP) @@ -339,7 +339,7 @@ void arm_addregion(void) #endif /* SRAM2 */ -#ifdef CONFIG_STM32U5_SRAM3_HEAP +#ifdef CONFIG_STM32_SRAM3_HEAP # if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP) @@ -359,7 +359,7 @@ void arm_addregion(void) #endif /* SRAM3 */ -#ifdef CONFIG_STM32U5_SRAM5_HEAP +#ifdef CONFIG_STM32_SRAM5_HEAP # if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP) @@ -379,7 +379,7 @@ void arm_addregion(void) #endif /* SRAM5 */ -#ifdef CONFIG_STM32U5_FSMC_SRAM_HEAP +#ifdef CONFIG_STM32_FSMC_SRAM_HEAP # if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP) /* Allow user-mode access to the FSMC SRAM user heap memory */ diff --git a/arch/arm/src/stm32u5/stm32_dbgmcu.h b/arch/arm/src/stm32u5/stm32_dbgmcu.h index 0db98b7196c33..7997e386cbcfa 100644 --- a/arch/arm/src/stm32u5/stm32_dbgmcu.h +++ b/arch/arm/src/stm32u5/stm32_dbgmcu.h @@ -31,7 +31,7 @@ #include "chip.h" -#if defined(CONFIG_STM32U5_STM32U585XX) || defined(CONFIG_STM32U5_STM32U5A5XX) +#if defined(CONFIG_STM32_STM32U585XX) || defined(CONFIG_STM32_STM32U5A5XX) # include "hardware/stm32u5xx_dbgmcu.h" #else # error "Unsupported STM32U5 chip" diff --git a/arch/arm/src/stm32u5/stm32_exti.h b/arch/arm/src/stm32u5/stm32_exti.h index dd31b1946ef91..6693179b0b535 100644 --- a/arch/arm/src/stm32u5/stm32_exti.h +++ b/arch/arm/src/stm32u5/stm32_exti.h @@ -141,7 +141,7 @@ int stm32_exti_wakeup(bool risingedge, bool fallingedge, bool event, * ****************************************************************************/ -#ifdef CONFIG_STM32U5_COMP +#ifdef CONFIG_STM32_COMP int stm32_exti_comp(int cmp, bool risingedge, bool fallingedge, bool event, xcpt_t func, void *arg); #endif diff --git a/arch/arm/src/stm32u5/stm32_flash.c b/arch/arm/src/stm32u5/stm32_flash.c index 586b315456178..526ba889c0599 100644 --- a/arch/arm/src/stm32u5/stm32_flash.c +++ b/arch/arm/src/stm32u5/stm32_flash.c @@ -50,13 +50,13 @@ #include "stm32_flash.h" #include "arm_internal.h" -#if !defined(CONFIG_STM32U5_STM32U585XX) -#elif !defined(CONFIG_STM32U5_STM32U5A5XX) +#if !defined(CONFIG_STM32_STM32U585XX) +#elif !defined(CONFIG_STM32_STM32U5A5XX) #else # error "Unrecognized STM32 chip" #endif -#if !defined(CONFIG_STM32U5_FLASH_OVERRIDE_DEFAULT) +#if !defined(CONFIG_STM32_FLASH_OVERRIDE_DEFAULT) # warning "Flash Configuration has been overridden - make sure it is correct" #endif diff --git a/arch/arm/src/stm32u5/stm32_gpio.h b/arch/arm/src/stm32u5/stm32_gpio.h index ad41d5f41b571..5f37922b48239 100644 --- a/arch/arm/src/stm32u5/stm32_gpio.h +++ b/arch/arm/src/stm32u5/stm32_gpio.h @@ -39,7 +39,7 @@ #include "chip.h" -#if defined(CONFIG_STM32U5_STM32U585XX) || defined(CONFIG_STM32U5_STM32U5A5XX) +#if defined(CONFIG_STM32_STM32U585XX) || defined(CONFIG_STM32_STM32U5A5XX) # include "hardware/stm32_gpio.h" #else # error "Unsupported STM32U5 chip" diff --git a/arch/arm/src/stm32u5/stm32_i2c.c b/arch/arm/src/stm32u5/stm32_i2c.c index 5ce0991788563..2f99e55a86fff 100644 --- a/arch/arm/src/stm32u5/stm32_i2c.c +++ b/arch/arm/src/stm32u5/stm32_i2c.c @@ -172,28 +172,28 @@ * * To use this driver, enable the following configuration variable: * - * CONFIG_STM32U5_I2C + * CONFIG_STM32_I2C * * and one or more interfaces: * - * CONFIG_STM32U5_I2C1 - * CONFIG_STM32U5_I2C2 - * CONFIG_STM32U5_I2C3 - * CONFIG_STM32U5_I2C4 + * CONFIG_STM32_I2C1 + * CONFIG_STM32_I2C2 + * CONFIG_STM32_I2C3 + * CONFIG_STM32_I2C4 * * To configure the ISR timeout using fixed values - * (CONFIG_STM32U5_I2C_DYNTIMEO=n): + * (CONFIG_STM32_I2C_DYNTIMEO=n): * - * CONFIG_STM32U5_I2CTIMEOSEC (Timeout in seconds) - * CONFIG_STM32U5_I2CTIMEOMS (Timeout in milliseconds) - * CONFIG_STM32U5_I2CTIMEOTICKS (Timeout in ticks) + * CONFIG_STM32_I2CTIMEOSEC (Timeout in seconds) + * CONFIG_STM32_I2CTIMEOMS (Timeout in milliseconds) + * CONFIG_STM32_I2CTIMEOTICKS (Timeout in ticks) * * To configure the ISR timeout using dynamic values - * (CONFIG_STM32U5_I2C_DYNTIMEO=y): + * (CONFIG_STM32_I2C_DYNTIMEO=y): * - * CONFIG_STM32U5_I2C_DYNTIMEO_USECPERBYTE + * CONFIG_STM32_I2C_DYNTIMEO_USECPERBYTE * (Timeout in microseconds per byte) - * CONFIG_STM32U5_I2C_DYNTIMEO_STARTSTOP + * CONFIG_STM32_I2C_DYNTIMEO_STARTSTOP * (Timeout for start/stop inmilliseconds) * * Debugging output enabled with: @@ -273,8 +273,8 @@ /* At least one I2C peripheral must be enabled */ -#if defined(CONFIG_STM32U5_I2C1) || defined(CONFIG_STM32U5_I2C2) || \ - defined(CONFIG_STM32U5_I2C3) || defined(CONFIG_STM32U5_I2C4) +#if defined(CONFIG_STM32_I2C1) || defined(CONFIG_STM32_I2C2) || \ + defined(CONFIG_STM32_I2C3) || defined(CONFIG_STM32_I2C4) /**************************************************************************** * Pre-processor Definitions @@ -286,25 +286,25 @@ /* Interrupt wait timeout in seconds and milliseconds */ -#if !defined(CONFIG_STM32U5_I2CTIMEOSEC) && !defined(CONFIG_STM32U5_I2CTIMEOMS) -# define CONFIG_STM32U5_I2CTIMEOSEC 0 -# define CONFIG_STM32U5_I2CTIMEOMS 500 /* Default is 500 milliseconds */ +#if !defined(CONFIG_STM32_I2CTIMEOSEC) && !defined(CONFIG_STM32_I2CTIMEOMS) +# define CONFIG_STM32_I2CTIMEOSEC 0 +# define CONFIG_STM32_I2CTIMEOMS 500 /* Default is 500 milliseconds */ # warning "Using Default 500 Ms Timeout" -#elif !defined(CONFIG_STM32U5_I2CTIMEOSEC) -# define CONFIG_STM32U5_I2CTIMEOSEC 0 /* User provided milliseconds */ -#elif !defined(CONFIG_STM32U5_I2CTIMEOMS) -# define CONFIG_STM32U5_I2CTIMEOMS 0 /* User provided seconds */ +#elif !defined(CONFIG_STM32_I2CTIMEOSEC) +# define CONFIG_STM32_I2CTIMEOSEC 0 /* User provided milliseconds */ +#elif !defined(CONFIG_STM32_I2CTIMEOMS) +# define CONFIG_STM32_I2CTIMEOMS 0 /* User provided seconds */ #endif /* Interrupt wait time timeout in system timer ticks */ -#ifndef CONFIG_STM32U5_I2CTIMEOTICKS -# define CONFIG_STM32U5_I2CTIMEOTICKS \ - (SEC2TICK(CONFIG_STM32U5_I2CTIMEOSEC) + MSEC2TICK(CONFIG_STM32U5_I2CTIMEOMS)) +#ifndef CONFIG_STM32_I2CTIMEOTICKS +# define CONFIG_STM32_I2CTIMEOTICKS \ + (SEC2TICK(CONFIG_STM32_I2CTIMEOSEC) + MSEC2TICK(CONFIG_STM32_I2CTIMEOMS)) #endif -#ifndef CONFIG_STM32U5_I2C_DYNTIMEO_STARTSTOP -# define CONFIG_STM32U5_I2C_DYNTIMEO_STARTSTOP TICK2USEC(CONFIG_STM32U5_I2CTIMEOTICKS) +#ifndef CONFIG_STM32_I2C_DYNTIMEO_STARTSTOP +# define CONFIG_STM32_I2C_DYNTIMEO_STARTSTOP TICK2USEC(CONFIG_STM32_I2CTIMEOTICKS) #endif /* Macros to convert a I2C pin to a GPIO output */ @@ -472,9 +472,9 @@ static inline void stm32_i2c_modifyreg32(struct stm32_i2c_priv_s *priv, uint8_t offset, uint32_t clearbits, uint32_t setbits); -#ifdef CONFIG_STM32U5_I2C_DYNTIMEO +#ifdef CONFIG_STM32_I2C_DYNTIMEO static uint32_t stm32_i2c_toticks(int msgc, struct i2c_msg_s *msgs); -#endif /* CONFIG_STM32U5_I2C_DYNTIMEO */ +#endif /* CONFIG_STM32_I2C_DYNTIMEO */ static inline int stm32_i2c_sem_waitdone(struct stm32_i2c_priv_s *priv); static inline @@ -518,7 +518,7 @@ static int stm32_i2c_pm_prepare(struct pm_callback_s *cb, int domain, * Private Data ****************************************************************************/ -#ifdef CONFIG_STM32U5_I2C1 +#ifdef CONFIG_STM32_I2C1 static const struct stm32_i2c_config_s stm32_i2c1_config = { .base = STM32_I2C1_BASE, @@ -554,7 +554,7 @@ static struct stm32_i2c_priv_s stm32_i2c1_priv = }; #endif -#ifdef CONFIG_STM32U5_I2C2 +#ifdef CONFIG_STM32_I2C2 static const struct stm32_i2c_config_s stm32_i2c2_config = { .base = STM32_I2C2_BASE, @@ -590,7 +590,7 @@ static struct stm32_i2c_priv_s stm32_i2c2_priv = }; #endif -#ifdef CONFIG_STM32U5_I2C3 +#ifdef CONFIG_STM32_I2C3 static const struct stm32_i2c_config_s stm32_i2c3_config = { .base = STM32_I2C3_BASE, @@ -626,7 +626,7 @@ static struct stm32_i2c_priv_s stm32_i2c3_priv = }; #endif -#ifdef CONFIG_STM32U5_I2C4 +#ifdef CONFIG_STM32_I2C4 static const struct stm32_i2c_config_s stm32_i2c4_config = { .base = STM32_I2C4_BASE, @@ -759,7 +759,7 @@ void stm32_i2c_modifyreg32(struct stm32_i2c_priv_s *priv, * ****************************************************************************/ -#ifdef CONFIG_STM32U5_I2C_DYNTIMEO +#ifdef CONFIG_STM32_I2C_DYNTIMEO static uint32_t stm32_i2c_toticks(int msgc, struct i2c_msg_s *msgs) { size_t bytecount = 0; @@ -776,7 +776,7 @@ static uint32_t stm32_i2c_toticks(int msgc, struct i2c_msg_s *msgs) * factor. */ - return USEC2TICK(CONFIG_STM32U5_I2C_DYNTIMEO_USECPERBYTE * bytecount); + return USEC2TICK(CONFIG_STM32_I2C_DYNTIMEO_USECPERBYTE * bytecount); } #endif @@ -834,12 +834,12 @@ int stm32_i2c_sem_waitdone(struct stm32_i2c_priv_s *priv) { /* Wait until either the transfer is complete or the timeout expires */ -#ifdef CONFIG_STM32U5_I2C_DYNTIMEO +#ifdef CONFIG_STM32_I2C_DYNTIMEO ret = nxsem_tickwait_uninterruptible(&priv->sem_isr, stm32_i2c_toticks(priv->msgc, priv->msgv)); #else ret = nxsem_tickwait_uninterruptible(&priv->sem_isr, - CONFIG_STM32U5_I2CTIMEOTICKS); + CONFIG_STM32_I2CTIMEOTICKS); #endif if (ret < 0) { @@ -878,10 +878,10 @@ int stm32_i2c_sem_waitdone(struct stm32_i2c_priv_s *priv) /* Get the timeout value */ -#ifdef CONFIG_STM32U5_I2C_DYNTIMEO +#ifdef CONFIG_STM32_I2C_DYNTIMEO timeout = stm32_i2c_toticks(priv->msgc, priv->msgv); #else - timeout = CONFIG_STM32U5_I2CTIMEOTICKS; + timeout = CONFIG_STM32_I2CTIMEOTICKS; #endif /* Signal the interrupt handler that we are waiting. NOTE: Interrupts @@ -1023,10 +1023,10 @@ void stm32_i2c_sem_waitstop(struct stm32_i2c_priv_s *priv) /* Select a timeout */ -#ifdef CONFIG_STM32U5_I2C_DYNTIMEO - timeout = USEC2TICK(CONFIG_STM32U5_I2C_DYNTIMEO_STARTSTOP); +#ifdef CONFIG_STM32_I2C_DYNTIMEO + timeout = USEC2TICK(CONFIG_STM32_I2C_DYNTIMEO_STARTSTOP); #else - timeout = CONFIG_STM32U5_I2CTIMEOTICKS; + timeout = CONFIG_STM32_I2CTIMEOTICKS; #endif /* Wait as stop might still be in progress */ @@ -2367,7 +2367,7 @@ static int stm32_i2c_init(struct stm32_i2c_priv_s *priv) /* Enable power and reset the peripheral */ -#ifdef CONFIG_STM32U5_I2C4 +#ifdef CONFIG_STM32_I2C4 if (priv->config->base == STM32_I2C4_BASE) { modifyreg32(STM32_RCC_APB1ENR2, 0, priv->config->clk_bit); @@ -2452,7 +2452,7 @@ static int stm32_i2c_deinit(struct stm32_i2c_priv_s *priv) /* Disable clocking */ -#ifdef CONFIG_STM32U5_I2C4 +#ifdef CONFIG_STM32_I2C4 if (priv->config->base == STM32_I2C4_BASE) { modifyreg32(STM32_RCC_APB1ENR2, priv->config->clk_bit, 0); @@ -2957,22 +2957,22 @@ struct i2c_master_s *stm32_i2cbus_initialize(int port) switch (port) { -#ifdef CONFIG_STM32U5_I2C1 +#ifdef CONFIG_STM32_I2C1 case 1: priv = (struct stm32_i2c_priv_s *)&stm32_i2c1_priv; break; #endif -#ifdef CONFIG_STM32U5_I2C2 +#ifdef CONFIG_STM32_I2C2 case 2: priv = (struct stm32_i2c_priv_s *)&stm32_i2c2_priv; break; #endif -#ifdef CONFIG_STM32U5_I2C3 +#ifdef CONFIG_STM32_I2C3 case 3: priv = (struct stm32_i2c_priv_s *)&stm32_i2c3_priv; break; #endif -#ifdef CONFIG_STM32U5_I2C4 +#ifdef CONFIG_STM32_I2C4 case 4: priv = (struct stm32_i2c_priv_s *)&stm32_i2c4_priv; break; @@ -3058,4 +3058,4 @@ int stm32_i2cbus_uninitialize(struct i2c_master_s *dev) return OK; } -#endif /* CONFIG_STM32U5_I2C1 || CONFIG_STM32U5_I2C2 || CONFIG_STM32U5_I2C3 || CONFIG_STM32U5_I2C4 */ +#endif /* CONFIG_STM32_I2C1 || CONFIG_STM32_I2C2 || CONFIG_STM32_I2C3 || CONFIG_STM32_I2C4 */ diff --git a/arch/arm/src/stm32u5/stm32_i2c.h b/arch/arm/src/stm32u5/stm32_i2c.h index 5f31f8995ac6e..f34cf0166eb29 100644 --- a/arch/arm/src/stm32u5/stm32_i2c.h +++ b/arch/arm/src/stm32u5/stm32_i2c.h @@ -41,10 +41,10 @@ * seconds per byte value must be provided as well. */ -#ifdef CONFIG_STM32U5_I2C_DYNTIMEO -# if CONFIG_STM32U5_I2C_DYNTIMEO_USECPERBYTE < 1 -# warning "Ignoring CONFIG_STM32U5_I2C_DYNTIMEO because of CONFIG_STM32U5_I2C_DYNTIMEO_USECPERBYTE" -# undef CONFIG_STM32U5_I2C_DYNTIMEO +#ifdef CONFIG_STM32_I2C_DYNTIMEO +# if CONFIG_STM32_I2C_DYNTIMEO_USECPERBYTE < 1 +# warning "Ignoring CONFIG_STM32_I2C_DYNTIMEO because of CONFIG_STM32_I2C_DYNTIMEO_USECPERBYTE" +# undef CONFIG_STM32_I2C_DYNTIMEO # endif #endif diff --git a/arch/arm/src/stm32u5/stm32_idle.c b/arch/arm/src/stm32u5/stm32_idle.c index 08a5d61d44c8c..f84145eca7175 100644 --- a/arch/arm/src/stm32u5/stm32_idle.c +++ b/arch/arm/src/stm32u5/stm32_idle.c @@ -92,7 +92,7 @@ void up_idle(void) /* Sleep until an interrupt occurs to save power. */ -#if !(defined(CONFIG_DEBUG_SYMBOLS) && defined(CONFIG_STM32U5_DISABLE_IDLE_SLEEP_DURING_DEBUG)) +#if !(defined(CONFIG_DEBUG_SYMBOLS) && defined(CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG)) BEGIN_IDLE(); asm("WFI"); END_IDLE(); diff --git a/arch/arm/src/stm32u5/stm32_lse.c b/arch/arm/src/stm32u5/stm32_lse.c index 70438d4e8b0c3..ebac02e6c54fb 100644 --- a/arch/arm/src/stm32u5/stm32_lse.c +++ b/arch/arm/src/stm32u5/stm32_lse.c @@ -42,9 +42,9 @@ static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1, #define LSERDY_TIMEOUT (500 * CONFIG_BOARD_LOOPSPERMSEC) -#ifdef CONFIG_STM32U5_RTC_LSECLOCK_START_DRV_CAPABILITY -# if CONFIG_STM32U5_RTC_LSECLOCK_START_DRV_CAPABILITY < 0 || \ - CONFIG_STM32U5_RTC_LSECLOCK_START_DRV_CAPABILITY > 3 +#ifdef CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY +# if CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY < 0 || \ + CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY > 3 # error "Invalid LSE drive capability setting" # endif #endif @@ -53,7 +53,7 @@ static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1, * Private Data ****************************************************************************/ -#ifdef CONFIG_STM32U5_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY +#ifdef CONFIG_STM32_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY static const uint32_t drives[4] = { RCC_BDCR_LSEDRV_LOW, @@ -80,7 +80,7 @@ void stm32_rcc_enablelse(void) bool writable; uint32_t regval; volatile int32_t timeout; -#ifdef CONFIG_STM32U5_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY +#ifdef CONFIG_STM32_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY volatile int32_t drive = 0; #endif @@ -108,19 +108,19 @@ void stm32_rcc_enablelse(void) regval |= RCC_BDCR_LSEON; -#ifdef CONFIG_STM32U5_RTC_LSECLOCK_START_DRV_CAPABILITY +#ifdef CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY /* Set start-up drive capability for LSE oscillator. LSE must be OFF * to change drive strength. */ regval &= ~(RCC_BDCR_LSEDRV_MASK | RCC_BDCR_LSEON); - regval |= CONFIG_STM32U5_RTC_LSECLOCK_START_DRV_CAPABILITY << + regval |= CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY << RCC_BDCR_LSEDRV_SHIFT; putreg32(regval, STM32_RCC_BDCR); regval |= RCC_BDCR_LSEON; #endif -#ifdef CONFIG_STM32U5_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY +#ifdef CONFIG_STM32_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY do { regval &= ~(RCC_BDCR_LSEDRV_MASK | RCC_BDCR_LSEON); @@ -148,7 +148,7 @@ void stm32_rcc_enablelse(void) } } -#ifdef CONFIG_STM32U5_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY +#ifdef CONFIG_STM32_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY if (timeout != 0) { break; @@ -177,7 +177,7 @@ void stm32_rcc_enablelse(void) } } -#ifdef CONFIG_STM32U5_RTC_LSECLOCK_LOWER_RUN_DRV_CAPABILITY +#ifdef CONFIG_STM32_RTC_LSECLOCK_LOWER_RUN_DRV_CAPABILITY /* Set running drive capability for LSE oscillator. */ diff --git a/arch/arm/src/stm32u5/stm32_rcc.c b/arch/arm/src/stm32u5/stm32_rcc.c index aa334d993051d..2e7ac13bb44c5 100644 --- a/arch/arm/src/stm32u5/stm32_rcc.c +++ b/arch/arm/src/stm32u5/stm32_rcc.c @@ -83,7 +83,7 @@ static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1, * ****************************************************************************/ -#if defined(CONFIG_STM32U5_PWR) && defined(CONFIG_STM32U5_RTC) +#if defined(CONFIG_STM32_PWR) && defined(CONFIG_STM32_RTC) static inline void rcc_resetbkp(void) { bool init_stat; @@ -93,14 +93,14 @@ static inline void rcc_resetbkp(void) init_stat = stm32_rtc_is_initialized(); if (!init_stat) { - uint32_t bkregs[STM32U5_RTC_BKCOUNT]; + uint32_t bkregs[STM32_RTC_BKCOUNT]; int i; /* Backup backup-registers before RTC reset. */ - for (i = 0; i < STM32U5_RTC_BKCOUNT; i++) + for (i = 0; i < STM32_RTC_BKCOUNT; i++) { - bkregs[i] = getreg32(STM32U5_RTC_BKR(i)); + bkregs[i] = getreg32(STM32_RTC_BKR(i)); } /* Enable write access to the backup domain (RTC registers, RTC @@ -113,19 +113,19 @@ static inline void rcc_resetbkp(void) * reset the backup domain (having backed up the RTC_MAGIC token) */ - modifyreg32(STM32U5_RCC_BDCR, 0, RCC_BDCR_BDRST); - modifyreg32(STM32U5_RCC_BDCR, RCC_BDCR_BDRST, 0); + modifyreg32(STM32_RCC_BDCR, 0, RCC_BDCR_BDRST); + modifyreg32(STM32_RCC_BDCR, RCC_BDCR_BDRST, 0); /* Restore backup-registers, except RTC related. */ - for (i = 0; i < STM32U5_RTC_BKCOUNT; i++) + for (i = 0; i < STM32_RTC_BKCOUNT; i++) { - if (RTC_MAGIC_REG == STM32U5_RTC_BKR(i)) + if (RTC_MAGIC_REG == STM32_RTC_BKR(i)) { continue; } - putreg32(bkregs[i], STM32U5_RTC_BKR(i)); + putreg32(bkregs[i], STM32_RTC_BKR(i)); } stm32_pwr_enablebkp(false); @@ -148,7 +148,7 @@ static inline void rcc_resetbkp(void) * and enable peripheral clocking for all peripherals enabled in the NuttX * configuration file. * - * If CONFIG_ARCH_BOARD_STM32U5_CUSTOM_CLOCKCONFIG is defined, then + * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then * clocking will be enabled by an externally provided, board-specific * function called stm32_board_clockconfig(). * @@ -171,7 +171,7 @@ void stm32_clockconfig(void) rcc_resetbkp(); #endif -#if defined(CONFIG_ARCH_BOARD_STM32U5_CUSTOM_CLOCKCONFIG) +#if defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) /* Invoke Board Custom Clock Configuration */ @@ -205,7 +205,7 @@ void stm32_clockconfig(void) * stm32_clockconfig() * reset the currently enabled peripheral clocks. * - * If CONFIG_ARCH_BOARD_STM32U5_CUSTOM_CLOCKCONFIG is defined, then + * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then * clocking will be enabled by an externally provided, board-specific * function called stm32_board_clockconfig(). * @@ -220,7 +220,7 @@ void stm32_clockconfig(void) #ifdef CONFIG_PM void stm32_clockenable(void) { -#if defined(CONFIG_ARCH_BOARD_STM32U5_CUSTOM_CLOCKCONFIG) +#if defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) /* Invoke Board Custom Clock Configuration */ diff --git a/arch/arm/src/stm32u5/stm32_rcc.h b/arch/arm/src/stm32u5/stm32_rcc.h index b788f167de9f0..ae75e4a235666 100644 --- a/arch/arm/src/stm32u5/stm32_rcc.h +++ b/arch/arm/src/stm32u5/stm32_rcc.h @@ -32,7 +32,7 @@ #include "arm_internal.h" #include "chip.h" -#if defined(CONFIG_STM32U5_STM32U585XX) || defined(CONFIG_STM32U5_STM32U5A5XX) +#if defined(CONFIG_STM32_STM32U585XX) || defined(CONFIG_STM32_STM32U5A5XX) # include "hardware/stm32u5xx_rcc.h" #else # error "Unsupported STM32U5 chip" @@ -97,7 +97,7 @@ static inline void stm32_mcoconfig(uint32_t source) * and enable peripheral clocking for all periperipherals enabled in the * NuttX configuration file. * - * If CONFIG_ARCH_BOARD_STM32U5_CUSTOM_CLOCKCONFIG is defined, then + * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then * clocking will be enabled by an externally provided, board-specific * function called stm32_board_clockconfig(). * @@ -120,7 +120,7 @@ void stm32_clockconfig(void); * ****************************************************************************/ -#ifdef CONFIG_ARCH_BOARD_STM32U5_CUSTOM_CLOCKCONFIG +#ifdef CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG void stm32_board_clockconfig(void); #endif @@ -135,7 +135,7 @@ void stm32_board_clockconfig(void); * ****************************************************************************/ -#ifndef CONFIG_ARCH_BOARD_STM32U5_CUSTOM_CLOCKCONFIG +#ifndef CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG void stm32_stdclockconfig(void); #endif @@ -152,7 +152,7 @@ void stm32_stdclockconfig(void); * stm32_clockconfig(): It does not reset any devices, and it does not * reset the currently enabled peripheral clocks. * - * If CONFIG_ARCH_BOARD_STM32U5_CUSTOM_CLOCKCONFIG is defined, then + * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then * clocking will be enabled by an externally provided, board-specific * function called stm32_board_clockconfig(). * diff --git a/arch/arm/src/stm32u5/stm32_serial.c b/arch/arm/src/stm32u5/stm32_serial.c index a5aea799e9657..13d539fdb787d 100644 --- a/arch/arm/src/stm32u5/stm32_serial.c +++ b/arch/arm/src/stm32u5/stm32_serial.c @@ -82,14 +82,14 @@ */ # if defined(CONFIG_USART2_RXDMA) || defined(CONFIG_USART3_RXDMA) -# if !defined(CONFIG_STM32U5_DMA1) && !defined(CONFIG_STM32U5_DMAMUX) -# error STM32U5 USART2/3 receive DMA requires CONFIG_STM32U5_DMA1 +# if !defined(CONFIG_STM32_DMA1) && !defined(CONFIG_STM32_DMAMUX) +# error STM32U5 USART2/3 receive DMA requires CONFIG_STM32_DMA1 # endif # endif # if defined(CONFIG_UART4_RXDMA) || defined(CONFIG_UART5_RXDMA) -# if !defined(CONFIG_STM32U5_DMA2) && !defined(CONFIG_STM32U5_DMAMUX) -# error STM32U5 UART4/5 receive DMA requires CONFIG_STM32U5_DMA2 +# if !defined(CONFIG_STM32_DMA2) && !defined(CONFIG_STM32_DMAMUX) +# error STM32U5 UART4/5 receive DMA requires CONFIG_STM32_DMA2 # endif # endif @@ -116,7 +116,7 @@ /* UART2-5 have no alternate channels without DMAMUX */ -# ifndef CONFIG_STM32U5_HAVE_DMAMUX +# ifndef CONFIG_STM32_HAVE_DMAMUX # define DMAMAP_USART2_RX DMACHAN_USART2_RX # define DMAMAP_USART3_RX DMACHAN_USART3_RX # define DMAMAP_UART4_RX DMACHAN_UART4_RX @@ -149,11 +149,11 @@ * can be individually invalidated. */ -# if !defined(CONFIG_STM32U5_SERIAL_RXDMA_BUFFER_SIZE) || \ - CONFIG_STM32U5_SERIAL_RXDMA_BUFFER_SIZE == 0 +# if !defined(CONFIG_STM32_SERIAL_RXDMA_BUFFER_SIZE) || \ + CONFIG_STM32_SERIAL_RXDMA_BUFFER_SIZE == 0 # define RXDMA_BUFFER_SIZE 32 # else -# define RXDMA_BUFFER_SIZE ((CONFIG_STM32U5_SERIAL_RXDMA_BUFFER_SIZE + 31) & ~31) +# define RXDMA_BUFFER_SIZE ((CONFIG_STM32_SERIAL_RXDMA_BUFFER_SIZE + 31) & ~31) # endif /* DMA priority */ @@ -185,8 +185,8 @@ /* Power management definitions */ -#if defined(CONFIG_PM) && !defined(CONFIG_STM32U5_PM_SERIAL_ACTIVITY) -# define CONFIG_STM32U5_PM_SERIAL_ACTIVITY 10 +#if defined(CONFIG_PM) && !defined(CONFIG_STM32_PM_SERIAL_ACTIVITY) +# define CONFIG_STM32_PM_SERIAL_ACTIVITY 10 #endif /* Keep track if a Break was set @@ -200,7 +200,7 @@ * See stm32serial_restoreusartint where the masking is done. */ -#ifdef CONFIG_STM32U5_SERIALBRK_BSDCOMPAT +#ifdef CONFIG_STM32_SERIALBRK_BSDCOMPAT # define USART_CR1_IE_BREAK_INPROGRESS_SHFTS 15 # define USART_CR1_IE_BREAK_INPROGRESS (1 << USART_CR1_IE_BREAK_INPROGRESS_SHFTS) #endif @@ -395,7 +395,7 @@ static const struct uart_ops_s g_uart_dma_ops = /* I/O buffers */ -#ifdef CONFIG_STM32U5_LPUART1_SERIALDRIVER +#ifdef CONFIG_STM32_LPUART1_SERIALDRIVER static char g_lpuart1rxbuffer[CONFIG_LPUART1_RXBUFSIZE]; static char g_lpuart1txbuffer[CONFIG_LPUART1_TXBUFSIZE]; # ifdef CONFIG_LPUART1_RXDMA @@ -403,7 +403,7 @@ static char g_lpuart1rxfifo[RXDMA_BUFFER_SIZE]; # endif #endif -#ifdef CONFIG_STM32U5_USART1_SERIALDRIVER +#ifdef CONFIG_STM32_USART1_SERIALDRIVER static char g_usart1rxbuffer[CONFIG_USART1_RXBUFSIZE]; static char g_usart1txbuffer[CONFIG_USART1_TXBUFSIZE]; # ifdef CONFIG_USART1_RXDMA @@ -411,7 +411,7 @@ static char g_usart1rxfifo[RXDMA_BUFFER_SIZE]; # endif #endif -#ifdef CONFIG_STM32U5_USART2_SERIALDRIVER +#ifdef CONFIG_STM32_USART2_SERIALDRIVER static char g_usart2rxbuffer[CONFIG_USART2_RXBUFSIZE]; static char g_usart2txbuffer[CONFIG_USART2_TXBUFSIZE]; # ifdef CONFIG_USART2_RXDMA @@ -419,7 +419,7 @@ static char g_usart2rxfifo[RXDMA_BUFFER_SIZE]; # endif #endif -#ifdef CONFIG_STM32U5_USART3_SERIALDRIVER +#ifdef CONFIG_STM32_USART3_SERIALDRIVER static char g_usart3rxbuffer[CONFIG_USART3_RXBUFSIZE]; static char g_usart3txbuffer[CONFIG_USART3_TXBUFSIZE]; # ifdef CONFIG_USART3_RXDMA @@ -427,7 +427,7 @@ static char g_usart3rxfifo[RXDMA_BUFFER_SIZE]; # endif #endif -#ifdef CONFIG_STM32U5_UART4_SERIALDRIVER +#ifdef CONFIG_STM32_UART4_SERIALDRIVER static char g_uart4rxbuffer[CONFIG_UART4_RXBUFSIZE]; static char g_uart4txbuffer[CONFIG_UART4_TXBUFSIZE]; # ifdef CONFIG_UART4_RXDMA @@ -435,7 +435,7 @@ static char g_uart4rxfifo[RXDMA_BUFFER_SIZE]; # endif #endif -#ifdef CONFIG_STM32U5_UART5_SERIALDRIVER +#ifdef CONFIG_STM32_UART5_SERIALDRIVER static char g_uart5rxbuffer[CONFIG_UART5_RXBUFSIZE]; static char g_uart5txbuffer[CONFIG_UART5_TXBUFSIZE]; # ifdef CONFIG_UART5_RXDMA @@ -445,7 +445,7 @@ static char g_uart5rxfifo[RXDMA_BUFFER_SIZE]; /* This describes the state of the STM32 USART1 ports. */ -#ifdef CONFIG_STM32U5_LPUART1_SERIALDRIVER +#ifdef CONFIG_STM32_LPUART1_SERIALDRIVER static struct stm32_serial_s g_lpuart1priv = { .dev = @@ -505,7 +505,7 @@ static struct stm32_serial_s g_lpuart1priv = }; #endif -#ifdef CONFIG_STM32U5_USART1_SERIALDRIVER +#ifdef CONFIG_STM32_USART1_SERIALDRIVER static struct stm32_serial_s g_usart1priv = { .dev = @@ -567,7 +567,7 @@ static struct stm32_serial_s g_usart1priv = /* This describes the state of the STM32 USART2 port. */ -#ifdef CONFIG_STM32U5_USART2_SERIALDRIVER +#ifdef CONFIG_STM32_USART2_SERIALDRIVER static struct stm32_serial_s g_usart2priv = { .dev = @@ -629,7 +629,7 @@ static struct stm32_serial_s g_usart2priv = /* This describes the state of the STM32 USART3 port. */ -#ifdef CONFIG_STM32U5_USART3_SERIALDRIVER +#ifdef CONFIG_STM32_USART3_SERIALDRIVER static struct stm32_serial_s g_usart3priv = { .dev = @@ -691,7 +691,7 @@ static struct stm32_serial_s g_usart3priv = /* This describes the state of the STM32 UART4 port. */ -#ifdef CONFIG_STM32U5_UART4_SERIALDRIVER +#ifdef CONFIG_STM32_UART4_SERIALDRIVER static struct stm32_serial_s g_uart4priv = { .dev = @@ -753,7 +753,7 @@ static struct stm32_serial_s g_uart4priv = /* This describes the state of the STM32 UART5 port. */ -#ifdef CONFIG_STM32U5_UART5_SERIALDRIVER +#ifdef CONFIG_STM32_UART5_SERIALDRIVER static struct stm32_serial_s g_uart5priv = { .dev = @@ -818,22 +818,22 @@ static struct stm32_serial_s g_uart5priv = static struct stm32_serial_s * const g_uart_devs[STM32_NLPUART + STM32_NUSART + STM32_NUART] = { -#ifdef CONFIG_STM32U5_LPUART1_SERIALDRIVER +#ifdef CONFIG_STM32_LPUART1_SERIALDRIVER [0] = &g_lpuart1priv, #endif -#ifdef CONFIG_STM32U5_USART1_SERIALDRIVER +#ifdef CONFIG_STM32_USART1_SERIALDRIVER [1] = &g_usart1priv, #endif -#ifdef CONFIG_STM32U5_USART2_SERIALDRIVER +#ifdef CONFIG_STM32_USART2_SERIALDRIVER [2] = &g_usart2priv, #endif -#ifdef CONFIG_STM32U5_USART3_SERIALDRIVER +#ifdef CONFIG_STM32_USART3_SERIALDRIVER [3] = &g_usart3priv, #endif -#ifdef CONFIG_STM32U5_UART4_SERIALDRIVER +#ifdef CONFIG_STM32_UART4_SERIALDRIVER [4] = &g_uart4priv, #endif -#ifdef CONFIG_STM32U5_UART5_SERIALDRIVER +#ifdef CONFIG_STM32_UART5_SERIALDRIVER [5] = &g_uart5priv, #endif }; @@ -1125,7 +1125,7 @@ static void stm32serial_setformat(struct uart_dev_s *dev) regval = stm32serial_getreg(priv, STM32_USART_CR3_OFFSET); regval &= ~(USART_CR3_CTSE | USART_CR3_RTSE); -#if defined(CONFIG_SERIAL_IFLOWCONTROL) && !defined(CONFIG_STM32U5_FLOWCONTROL_BROKEN) +#if defined(CONFIG_SERIAL_IFLOWCONTROL) && !defined(CONFIG_STM32_FLOWCONTROL_BROKEN) if (priv->iflow && (priv->rts_gpio != 0)) { regval |= USART_CR3_RTSE; @@ -1329,37 +1329,37 @@ static void stm32serial_setapbclock(struct uart_dev_s *dev, bool on) { default: return; -#ifdef CONFIG_STM32U5_LPUART1_SERIALDRIVER +#ifdef CONFIG_STM32_LPUART1_SERIALDRIVER case STM32_LPUART1_BASE: rcc_en = RCC_APB1ENR2_LPUART1EN; regaddr = STM32_RCC_APB1ENR2; break; #endif -#ifdef CONFIG_STM32U5_USART1_SERIALDRIVER +#ifdef CONFIG_STM32_USART1_SERIALDRIVER case STM32_USART1_BASE: rcc_en = RCC_APB2ENR_USART1EN; regaddr = STM32_RCC_APB2ENR; break; #endif -#ifdef CONFIG_STM32U5_USART2_SERIALDRIVER +#ifdef CONFIG_STM32_USART2_SERIALDRIVER case STM32_USART2_BASE: rcc_en = RCC_APB1ENR1_USART2EN; regaddr = STM32_RCC_APB1ENR1; break; #endif -#ifdef CONFIG_STM32U5_USART3_SERIALDRIVER +#ifdef CONFIG_STM32_USART3_SERIALDRIVER case STM32_USART3_BASE: rcc_en = RCC_APB1ENR1_USART3EN; regaddr = STM32_RCC_APB1ENR1; break; #endif -#ifdef CONFIG_STM32U5_UART4_SERIALDRIVER +#ifdef CONFIG_STM32_UART4_SERIALDRIVER case STM32_UART4_BASE: rcc_en = RCC_APB1ENR1_UART4EN; regaddr = STM32_RCC_APB1ENR1; break; #endif -#ifdef CONFIG_STM32U5_UART5_SERIALDRIVER +#ifdef CONFIG_STM32_UART5_SERIALDRIVER case STM32_UART5_BASE: rcc_en = RCC_APB1ENR1_UART5EN; regaddr = STM32_RCC_APB1ENR1; @@ -1428,7 +1428,7 @@ static int stm32serial_setup(struct uart_dev_s *dev) { uint32_t config = priv->rts_gpio; -#ifdef CONFIG_STM32U5_FLOWCONTROL_BROKEN +#ifdef CONFIG_STM32_FLOWCONTROL_BROKEN /* Instead of letting hw manage this pin, we will bitbang */ config = (config & ~GPIO_MODE_MASK) | GPIO_OUTPUT; @@ -1779,8 +1779,8 @@ static int stm32serial_interrupt(int irq, void *context, void *arg) /* Report serial activity to the power management logic */ -#if defined(CONFIG_PM) && CONFIG_STM32U5_PM_SERIAL_ACTIVITY > 0 - pm_activity(PM_IDLE_DOMAIN, CONFIG_STM32U5_PM_SERIAL_ACTIVITY); +#if defined(CONFIG_PM) && CONFIG_STM32_PM_SERIAL_ACTIVITY > 0 + pm_activity(PM_IDLE_DOMAIN, CONFIG_STM32_PM_SERIAL_ACTIVITY); #endif /* Loop until there are no characters to be transferred or, @@ -1923,7 +1923,7 @@ static int stm32serial_ioctl(struct file *filep, int cmd, break; #endif -#ifdef CONFIG_STM32U5_USART_SINGLEWIRE +#ifdef CONFIG_STM32_USART_SINGLEWIRE case TIOCSSINGLEWIRE: { uint32_t cr1; @@ -2001,7 +2001,7 @@ static int stm32serial_ioctl(struct file *filep, int cmd, break; #endif -#ifdef CONFIG_STM32U5_USART_INVERT +#ifdef CONFIG_STM32_USART_INVERT case TIOCSINVERT: { uint32_t cr1; @@ -2052,7 +2052,7 @@ static int stm32serial_ioctl(struct file *filep, int cmd, break; #endif -#ifdef CONFIG_STM32U5_USART_SWAP +#ifdef CONFIG_STM32_USART_SWAP case TIOCSSWAP: { uint32_t cr1; @@ -2189,8 +2189,8 @@ static int stm32serial_ioctl(struct file *filep, int cmd, break; #endif /* CONFIG_SERIAL_TERMIOS */ -#ifdef CONFIG_STM32U5_USART_BREAKS -# ifdef CONFIG_STM32U5_SERIALBRK_BSDCOMPAT +#ifdef CONFIG_STM32_USART_BREAKS +# ifdef CONFIG_STM32_SERIALBRK_BSDCOMPAT case TIOCSBRK: /* BSD compatibility: Turn break on, unconditionally */ { irqstate_t flags; @@ -2418,7 +2418,7 @@ static bool stm32serial_rxflowcontrol(struct uart_dev_s *dev, (struct stm32_serial_s *)dev->priv; #if defined(CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS) && \ - defined(CONFIG_STM32U5_FLOWCONTROL_BROKEN) + defined(CONFIG_STM32_FLOWCONTROL_BROKEN) if (priv->iflow && (priv->rts_gpio != 0)) { /* Assert/de-assert nRTS set it high resume/stop sending */ @@ -2770,7 +2770,7 @@ static void stm32serial_txint(struct uart_dev_s *dev, bool enable) } # endif -# ifdef CONFIG_STM32U5_SERIALBRK_BSDCOMPAT +# ifdef CONFIG_STM32_SERIALBRK_BSDCOMPAT if (priv->ie & USART_CR1_IE_BREAK_INPROGRESS) { leave_critical_section(flags); @@ -3111,7 +3111,7 @@ void arm_serialinit(void) #if CONSOLE_UART > 0 uart_register("/dev/console", &g_uart_devs[CONSOLE_UART - 1]->dev); -#ifndef CONFIG_STM32U5_SERIAL_DISABLE_REORDERING +#ifndef CONFIG_STM32_SERIAL_DISABLE_REORDERING /* If not disabled, register the console UART to ttyS0 and exclude * it from initializing it further down */ @@ -3140,7 +3140,7 @@ void arm_serialinit(void) continue; } -#ifndef CONFIG_STM32U5_SERIAL_DISABLE_REORDERING +#ifndef CONFIG_STM32_SERIAL_DISABLE_REORDERING /* Don't create a device for the console - we did that above */ if (g_uart_devs[i]->dev.isconsole) diff --git a/arch/arm/src/stm32u5/stm32_spi.c b/arch/arm/src/stm32u5/stm32_spi.c index bf4ded9c9011f..82ceb35c60d81 100644 --- a/arch/arm/src/stm32u5/stm32_spi.c +++ b/arch/arm/src/stm32u5/stm32_spi.c @@ -74,8 +74,8 @@ #include "stm32_gpio.h" #include "stm32_spi.h" -#if defined(CONFIG_STM32U5_SPI1) || defined(CONFIG_STM32U5_SPI2) || \ - defined(CONFIG_STM32U5_SPI3) +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || \ + defined(CONFIG_STM32_SPI3) /**************************************************************************** * Pre-processor Definitions @@ -85,19 +85,19 @@ /* SPI interrupts */ -#ifdef CONFIG_STM32U5_SPI_INTERRUPTS +#ifdef CONFIG_STM32_SPI_INTERRUPTS # error "Interrupt driven SPI not yet supported" #endif /* Can't have both interrupt driven SPI and SPI DMA */ -#if defined(CONFIG_STM32U5_SPI_INTERRUPTS) && defined(CONFIG_STM32U5_SPI_DMA) +#if defined(CONFIG_STM32_SPI_INTERRUPTS) && defined(CONFIG_STM32_SPI_DMA) # error "Cannot enable both interrupt mode and DMA mode for SPI" #endif /* SPI DMA priority */ -#ifdef CONFIG_STM32U5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA # if defined(CONFIG_SPI_DMAPRIO) # define SPI_DMA_PRIO CONFIG_SPI_DMAPRIO @@ -135,21 +135,21 @@ # define SPIDMA_BUF_ALIGN # endif -# if defined(CONFIG_STM32U5_SPI1_DMA_BUFFER) && \ - CONFIG_STM32U5_SPI1_DMA_BUFFER > 0 -# define SPI1_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32U5_SPI1_DMA_BUFFER) +# if defined(CONFIG_STM32_SPI1_DMA_BUFFER) && \ + CONFIG_STM32_SPI1_DMA_BUFFER > 0 +# define SPI1_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32_SPI1_DMA_BUFFER) # define SPI1_DMABUFSIZE_ALGN SPIDMA_BUF_ALIGN # endif -# if defined(CONFIG_STM32U5_SPI2_DMA_BUFFER) && \ - CONFIG_STM32U5_SPI2_DMA_BUFFER > 0 -# define SPI2_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32U5_SPI2_DMA_BUFFER) +# if defined(CONFIG_STM32_SPI2_DMA_BUFFER) && \ + CONFIG_STM32_SPI2_DMA_BUFFER > 0 +# define SPI2_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32_SPI2_DMA_BUFFER) # define SPI2_DMABUFSIZE_ALGN SPIDMA_BUF_ALIGN # endif -# if defined(CONFIG_STM32U5_SPI3_DMA_BUFFER) && \ - CONFIG_STM32U5_SPI3_DMA_BUFFER > 0 -# define SPI3_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32U5_SPI3_DMA_BUFFER) +# if defined(CONFIG_STM32_SPI3_DMA_BUFFER) && \ + CONFIG_STM32_SPI3_DMA_BUFFER > 0 +# define SPI3_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32_SPI3_DMA_BUFFER) # define SPI3_DMABUFSIZE_ALGN SPIDMA_BUF_ALIGN # endif @@ -160,15 +160,15 @@ * - support for all kernel clock configuration */ -#if defined(CONFIG_STM32U5_SPI1) +#if defined(CONFIG_STM32_SPI1) # define SPI1_KERNEL_CLOCK_FREQ STM32_PCLK2_FREQUENCY #endif -#if defined(CONFIG_STM32U5_SPI2) +#if defined(CONFIG_STM32_SPI2) # define SPI2_KERNEL_CLOCK_FREQ STM32_PCLK1_FREQUENCY #endif -#if defined(CONFIG_STM32U5_SPI3) +#if defined(CONFIG_STM32_SPI3) # define SPI3_KERNEL_CLOCK_FREQ STM32_PCLK3_FREQUENCY #endif @@ -190,7 +190,7 @@ struct stm32_spidev_s uint32_t spibase; /* SPIn base address */ uint32_t spiclock; /* Clocking for the SPI module */ uint8_t spiirq; /* SPI IRQ number */ -#ifdef CONFIG_STM32U5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA volatile uint8_t rxresult; /* Result of the RX DMA */ volatile uint8_t txresult; /* Result of the RX DMA */ #ifdef CONFIG_SPI_TRIGGER @@ -240,7 +240,7 @@ static inline void spi_dumpregs(struct stm32_spidev_s *priv); /* DMA support */ -#ifdef CONFIG_STM32U5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static int spi_dmarxwait(struct stm32_spidev_s *priv); static int spi_dmatxwait(struct stm32_spidev_s *priv); static inline void spi_dmarxwakeup(struct stm32_spidev_s *priv); @@ -306,7 +306,7 @@ static int spi_pm_prepare(struct pm_callback_s *cb, int domain, * Private Data ****************************************************************************/ -#ifdef CONFIG_STM32U5_SPI1 +#ifdef CONFIG_STM32_SPI1 static const struct spi_ops_s g_sp1iops = { .lock = spi_lock, @@ -355,7 +355,7 @@ static struct stm32_spidev_s g_spi1dev = .spibase = STM32_SPI1_BASE, .spiclock = SPI1_KERNEL_CLOCK_FREQ, .spiirq = STM32_IRQ_SPI1, -#ifdef CONFIG_STM32U5_SPI1_DMA +#ifdef CONFIG_STM32_SPI1_DMA .rxch = DMAMAP_SPI1_RX, .txch = DMAMAP_SPI1_TX, # if defined(SPI1_DMABUFSIZE_ADJUSTED) @@ -370,15 +370,15 @@ static struct stm32_spidev_s g_spi1dev = #ifdef CONFIG_PM .pm_cb.prepare = spi_pm_prepare, #endif -#ifdef CONFIG_STM32U5_SPI1_COMMTYPE - .config = CONFIG_STM32U5_SPI1_COMMTYPE, +#ifdef CONFIG_STM32_SPI1_COMMTYPE + .config = CONFIG_STM32_SPI1_COMMTYPE, #else .config = FULL_DUPLEX, #endif }; -#endif /* CONFIG_STM32U5_SPI1 */ +#endif /* CONFIG_STM32_SPI1 */ -#ifdef CONFIG_STM32U5_SPI2 +#ifdef CONFIG_STM32_SPI2 static const struct spi_ops_s g_sp2iops = { .lock = spi_lock, @@ -427,7 +427,7 @@ static struct stm32_spidev_s g_spi2dev = .spibase = STM32_SPI2_BASE, .spiclock = SPI2_KERNEL_CLOCK_FREQ, .spiirq = STM32_IRQ_SPI2, -#ifdef CONFIG_STM32U5_SPI2_DMA +#ifdef CONFIG_STM32_SPI2_DMA .rxch = DMAMAP_SPI2_RX, .txch = DMAMAP_SPI2_TX, # if defined(SPI2_DMABUFSIZE_ADJUSTED) @@ -442,15 +442,15 @@ static struct stm32_spidev_s g_spi2dev = #ifdef CONFIG_PM .pm_cb.prepare = spi_pm_prepare, #endif -#ifdef CONFIG_STM32U5_SPI2_COMMTYPE - .config = CONFIG_STM32U5_SPI2_COMMTYPE, +#ifdef CONFIG_STM32_SPI2_COMMTYPE + .config = CONFIG_STM32_SPI2_COMMTYPE, #else .config = FULL_DUPLEX, #endif }; -#endif /* CONFIG_STM32U5_SPI2 */ +#endif /* CONFIG_STM32_SPI2 */ -#ifdef CONFIG_STM32U5_SPI3 +#ifdef CONFIG_STM32_SPI3 static const struct spi_ops_s g_sp3iops = { .lock = spi_lock, @@ -499,7 +499,7 @@ static struct stm32_spidev_s g_spi3dev = .spibase = STM32_SPI3_BASE, .spiclock = SPI3_KERNEL_CLOCK_FREQ, .spiirq = STM32_IRQ_SPI3, -#ifdef CONFIG_STM32U5_SPI3_DMA +#ifdef CONFIG_STM32_SPI3_DMA .rxch = DMAMAP_SPI3_RX, .txch = DMAMAP_SPI3_TX, # if defined(SPI3_DMABUFSIZE_ADJUSTED) @@ -514,13 +514,13 @@ static struct stm32_spidev_s g_spi3dev = #ifdef CONFIG_PM .pm_cb.prepare = spi_pm_prepare, #endif -#ifdef CONFIG_STM32U5_SPI3_COMMTYPE - .config = CONFIG_STM32U5_SPI3_COMMTYPE, +#ifdef CONFIG_STM32_SPI3_COMMTYPE + .config = CONFIG_STM32_SPI3_COMMTYPE, #else .config = FULL_DUPLEX, #endif }; -#endif /* CONFIG_STM32U5_SPI3 */ +#endif /* CONFIG_STM32_SPI3 */ /**************************************************************************** * Private Functions @@ -840,7 +840,7 @@ static int spi_interrupt(int irq, void *context, void *arg) spi_modifyreg(priv, STM32_SPI_IER_OFFSET, SPI_IER_EOTIE, 0); /* Set result and release wait semaphore */ -#ifdef CONFIG_STM32U5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA priv->txresult = 0x80; nxsem_post(&priv->txsem); #endif @@ -857,7 +857,7 @@ static int spi_interrupt(int irq, void *context, void *arg) * ****************************************************************************/ -#ifdef CONFIG_STM32U5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static int spi_dmarxwait(struct stm32_spidev_s *priv) { int ret; @@ -897,7 +897,7 @@ static int spi_dmarxwait(struct stm32_spidev_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32U5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static int spi_dmatxwait(struct stm32_spidev_s *priv) { int ret; @@ -946,7 +946,7 @@ static int spi_dmatxwait(struct stm32_spidev_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32U5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static inline void spi_dmarxwakeup(struct stm32_spidev_s *priv) { nxsem_post(&priv->rxsem); @@ -961,7 +961,7 @@ static inline void spi_dmarxwakeup(struct stm32_spidev_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32U5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_dmarxcallback(DMA_HANDLE handle, uint8_t isr, void *arg) { struct stm32_spidev_s *priv = (struct stm32_spidev_s *)arg; @@ -981,7 +981,7 @@ static void spi_dmarxcallback(DMA_HANDLE handle, uint8_t isr, void *arg) * ****************************************************************************/ -#ifdef CONFIG_STM32U5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_dmarxsetup(struct stm32_spidev_s *priv, void *rxbuffer, void *rxdummy, size_t nwords, stm32_dmacfg_t *dmacfg) @@ -1043,7 +1043,7 @@ static void spi_dmarxsetup(struct stm32_spidev_s *priv, * ****************************************************************************/ -#ifdef CONFIG_STM32U5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_dmatxsetup(struct stm32_spidev_s *priv, const void *txbuffer, const void *txdummy, size_t nwords, stm32_dmacfg_t *dmacfg) @@ -1103,7 +1103,7 @@ static void spi_dmatxsetup(struct stm32_spidev_s *priv, * ****************************************************************************/ -#ifdef CONFIG_STM32U5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_dmarxstart(struct stm32_spidev_s *priv) { /* Can't receive in tx only mode */ @@ -1127,7 +1127,7 @@ static void spi_dmarxstart(struct stm32_spidev_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32U5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_dmatxstart(struct stm32_spidev_s *priv) { /* Can't transmit in rx only mode */ @@ -1662,9 +1662,9 @@ static uint32_t spi_send(struct spi_dev_s *dev, uint32_t wd) * ****************************************************************************/ -#if !defined(CONFIG_STM32U5_SPI_DMA) || defined(CONFIG_STM32U5_DMACAPABLE) || \ - defined(CONFIG_STM32U5_SPI_DMATHRESHOLD) -#if !defined(CONFIG_STM32U5_SPI_DMA) +#if !defined(CONFIG_STM32_SPI_DMA) || defined(CONFIG_STM32_DMACAPABLE) || \ + defined(CONFIG_STM32_SPI_DMATHRESHOLD) +#if !defined(CONFIG_STM32_SPI_DMA) static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, void *rxbuffer, size_t nwords) #else @@ -1753,8 +1753,8 @@ static void spi_exchange_nodma(struct spi_dev_s *dev, } } -#endif /* !CONFIG_STM32U5_SPI_DMA || CONFIG_STM32U5_DMACAPABLE || - * CONFIG_STM32U5_SPI_DMATHRESHOLD +#endif /* !CONFIG_STM32_SPI_DMA || CONFIG_STM32_DMACAPABLE || + * CONFIG_STM32_SPI_DMATHRESHOLD */ /**************************************************************************** @@ -1778,7 +1778,7 @@ static void spi_exchange_nodma(struct spi_dev_s *dev, * ****************************************************************************/ -#ifdef CONFIG_STM32U5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, void *rxbuffer, size_t nwords) { @@ -1796,12 +1796,12 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, size_t nbytes = (priv->nbits > 8) ? nwords << 1 : nwords; -#ifdef CONFIG_STM32U5_SPI_DMATHRESHOLD +#ifdef CONFIG_STM32_SPI_DMATHRESHOLD /* If this is a small SPI transfer, then let spi_exchange_nodma() do the * work. */ - if (nbytes <= CONFIG_STM32U5_SPI_DMATHRESHOLD) + if (nbytes <= CONFIG_STM32_SPI_DMATHRESHOLD) { spi_exchange_nodma(dev, txbuffer, rxbuffer, nwords); return; @@ -1865,7 +1865,7 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, spi_dmatxsetup(priv, txbuffer, &txdummy, nwords, &txdmacfg); spi_dmarxsetup(priv, rxbuffer, (uint16_t *)rxdummy, nwords, &rxdmacfg); -#ifdef CONFIG_STM32U5_DMACAPABLE +#ifdef CONFIG_STM32_DMACAPABLE /* Test for DMA capability of only callers buffers, internal buffers are * guaranteed capable. @@ -1995,7 +1995,7 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, priv->trigarmed = false; #endif } -#endif /* CONFIG_STM32U5_SPI_DMA */ +#endif /* CONFIG_STM32_SPI_DMA */ /**************************************************************************** * Name: spi_trigger @@ -2016,7 +2016,7 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, #ifdef CONFIG_SPI_TRIGGER static int spi_trigger(struct spi_dev_s *dev) { -#ifdef CONFIG_STM32U5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev; if (!priv->trigarmed) @@ -2250,7 +2250,7 @@ static void spi_bus_initialize(struct stm32_spidev_s *priv) spi_putreg(priv, STM32_SPI_CRCPOLY_OFFSET, 7); -#ifdef CONFIG_STM32U5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA /* Get DMA channels. NOTE: stm32_dmachannel() will always assign the DMA * channel. If the channel is not available, then stm32_dmachannel() will * block and wait until the channel becomes available. WARNING: If you @@ -2332,7 +2332,7 @@ struct spi_dev_s *stm32_spibus_initialize(int bus) struct stm32_spidev_s *priv = NULL; irqstate_t flags = enter_critical_section(); -#ifdef CONFIG_STM32U5_SPI1 +#ifdef CONFIG_STM32_SPI1 if (bus == 1) { /* Select SPI1 */ @@ -2357,7 +2357,7 @@ struct spi_dev_s *stm32_spibus_initialize(int bus) } else #endif -#ifdef CONFIG_STM32U5_SPI2 +#ifdef CONFIG_STM32_SPI2 if (bus == 2) { /* Select SPI2 */ @@ -2382,7 +2382,7 @@ struct spi_dev_s *stm32_spibus_initialize(int bus) } else #endif -#ifdef CONFIG_STM32U5_SPI3 +#ifdef CONFIG_STM32_SPI3 if (bus == 3) { /* Select SPI3 */ @@ -2415,5 +2415,5 @@ struct spi_dev_s *stm32_spibus_initialize(int bus) return (struct spi_dev_s *)priv; } -#endif /* CONFIG_STM32U5_SPI1 || CONFIG_STM32U5_SPI2 || CONFIG_STM32U5_SPI3 +#endif /* CONFIG_STM32_SPI1 || CONFIG_STM32_SPI2 || CONFIG_STM32_SPI3 */ diff --git a/arch/arm/src/stm32u5/stm32_spi.h b/arch/arm/src/stm32u5/stm32_spi.h index 9734b18924feb..485b6a5a9a1bb 100644 --- a/arch/arm/src/stm32u5/stm32_spi.h +++ b/arch/arm/src/stm32u5/stm32_spi.h @@ -114,21 +114,21 @@ struct spi_slave_ctrlr_s *stm32_spi_slave_initialize(int bus); * ****************************************************************************/ -#ifdef CONFIG_STM32U5_SPI1 +#ifdef CONFIG_STM32_SPI1 void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, bool selected); uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid); int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); #endif -#ifdef CONFIG_STM32U5_SPI2 +#ifdef CONFIG_STM32_SPI2 void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid, bool selected); uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid); int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); #endif -#ifdef CONFIG_STM32U5_SPI3 +#ifdef CONFIG_STM32_SPI3 void stm32_spi3select(struct spi_dev_s *dev, uint32_t devid, bool selected); uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid); @@ -156,17 +156,17 @@ int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); ****************************************************************************/ #ifdef CONFIG_SPI_CALLBACK -#ifdef CONFIG_STM32U5_SPI1 +#ifdef CONFIG_STM32_SPI1 int stm32_spi1register(struct spi_dev_s *dev, spi_mediachange_t callback, void *arg); #endif -#ifdef CONFIG_STM32U5_SPI2 +#ifdef CONFIG_STM32_SPI2 int stm32_spi2register(struct spi_dev_s *dev, spi_mediachange_t callback, void *arg); #endif -#ifdef CONFIG_STM32U5_SPI3 +#ifdef CONFIG_STM32_SPI3 int stm32_spi3register(struct spi_dev_s *dev, spi_mediachange_t callback, void *arg); #endif diff --git a/arch/arm/src/stm32u5/stm32_start.c b/arch/arm/src/stm32u5/stm32_start.c index ee12901462fd9..87609e5c881d2 100644 --- a/arch/arm/src/stm32u5/stm32_start.c +++ b/arch/arm/src/stm32u5/stm32_start.c @@ -131,7 +131,7 @@ void __start(void) ("sub r10, sp, %0" : : "r" (CONFIG_IDLETHREAD_STACKSIZE - 64) :); #endif -#ifdef CONFIG_STM32U5_SRAM2_INIT +#ifdef CONFIG_STM32_SRAM2_INIT /* The SRAM2 region is parity checked, but upon power up, it will be in * a random state and probably invalid with respect to parity, potentially * generating faults if accessed. If elected, we will write zeros to the diff --git a/arch/arm/src/stm32u5/stm32_tim.c b/arch/arm/src/stm32u5/stm32_tim.c index 5e15c461d1872..66879e72e8a2a 100644 --- a/arch/arm/src/stm32u5/stm32_tim.c +++ b/arch/arm/src/stm32u5/stm32_tim.c @@ -54,137 +54,137 @@ * include: * * - To generate modulated outputs for such things as motor control. If - * CONFIG_STM32U5_TIMn is defined then the CONFIG_STM32U5_TIMn_PWM may also + * CONFIG_STM32_TIMn is defined then the CONFIG_STM32_TIMn_PWM may also * be defined to indicate that the timer is intended to be used for pulsed * output modulation. * - * - To control periodic ADC input sampling. If CONFIG_STM32U5_TIMn is - * defined then CONFIG_STM32U5_TIMn_ADC may also be defined to indicate + * - To control periodic ADC input sampling. If CONFIG_STM32_TIMn is + * defined then CONFIG_STM32_TIMn_ADC may also be defined to indicate * that timer "n" is intended to be used for that purpose. * - * - To control periodic DAC outputs. If CONFIG_STM32U5_TIMn is defined then - * CONFIG_STM32U5_TIMn_DAC may also be defined to indicate that timer "n" + * - To control periodic DAC outputs. If CONFIG_STM32_TIMn is defined then + * CONFIG_STM32_TIMn_DAC may also be defined to indicate that timer "n" * is intended to be used for that purpose. * - * - To use a Quadrature Encoder. If CONFIG_STM32U5_TIMn is defined then - * CONFIG_STM32U5_TIMn_QE may also be defined to indicate that timer "n" + * - To use a Quadrature Encoder. If CONFIG_STM32_TIMn is defined then + * CONFIG_STM32_TIMn_QE may also be defined to indicate that timer "n" * is intended to be used for that purpose. * * In any of these cases, the timer will not be used by this timer module. */ -#if defined(CONFIG_STM32U5_TIM1_PWM) || defined (CONFIG_STM32U5_TIM1_ADC) || \ - defined(CONFIG_STM32U5_TIM1_DAC) || defined(CONFIG_STM32U5_TIM1_QE) -# undef CONFIG_STM32U5_TIM1 +#if defined(CONFIG_STM32_TIM1_PWM) || defined (CONFIG_STM32_TIM1_ADC) || \ + defined(CONFIG_STM32_TIM1_DAC) || defined(CONFIG_STM32_TIM1_QE) +# undef CONFIG_STM32_TIM1 #endif -#if defined(CONFIG_STM32U5_TIM2_PWM) || defined (CONFIG_STM32U5_TIM2_ADC) || \ - defined(CONFIG_STM32U5_TIM2_DAC) || defined(CONFIG_STM32U5_TIM2_QE) -# undef CONFIG_STM32U5_TIM2 +#if defined(CONFIG_STM32_TIM2_PWM) || defined (CONFIG_STM32_TIM2_ADC) || \ + defined(CONFIG_STM32_TIM2_DAC) || defined(CONFIG_STM32_TIM2_QE) +# undef CONFIG_STM32_TIM2 #endif -#if defined(CONFIG_STM32U5_TIM3_PWM) || defined (CONFIG_STM32U5_TIM3_ADC) || \ - defined(CONFIG_STM32U5_TIM3_DAC) || defined(CONFIG_STM32U5_TIM3_QE) -# undef CONFIG_STM32U5_TIM3 +#if defined(CONFIG_STM32_TIM3_PWM) || defined (CONFIG_STM32_TIM3_ADC) || \ + defined(CONFIG_STM32_TIM3_DAC) || defined(CONFIG_STM32_TIM3_QE) +# undef CONFIG_STM32_TIM3 #endif -#if defined(CONFIG_STM32U5_TIM4_PWM) || defined (CONFIG_STM32U5_TIM4_ADC) || \ - defined(CONFIG_STM32U5_TIM4_DAC) || defined(CONFIG_STM32U5_TIM4_QE) -# undef CONFIG_STM32U5_TIM4 +#if defined(CONFIG_STM32_TIM4_PWM) || defined (CONFIG_STM32_TIM4_ADC) || \ + defined(CONFIG_STM32_TIM4_DAC) || defined(CONFIG_STM32_TIM4_QE) +# undef CONFIG_STM32_TIM4 #endif -#if defined(CONFIG_STM32U5_TIM5_PWM) || defined (CONFIG_STM32U5_TIM5_ADC) || \ - defined(CONFIG_STM32U5_TIM5_DAC) || defined(CONFIG_STM32U5_TIM5_QE) -# undef CONFIG_STM32U5_TIM5 +#if defined(CONFIG_STM32_TIM5_PWM) || defined (CONFIG_STM32_TIM5_ADC) || \ + defined(CONFIG_STM32_TIM5_DAC) || defined(CONFIG_STM32_TIM5_QE) +# undef CONFIG_STM32_TIM5 #endif -#if defined(CONFIG_STM32U5_TIM6_PWM) || defined (CONFIG_STM32U5_TIM6_ADC) || \ - defined(CONFIG_STM32U5_TIM6_DAC) || defined(CONFIG_STM32U5_TIM6_QE) -# undef CONFIG_STM32U5_TIM6 +#if defined(CONFIG_STM32_TIM6_PWM) || defined (CONFIG_STM32_TIM6_ADC) || \ + defined(CONFIG_STM32_TIM6_DAC) || defined(CONFIG_STM32_TIM6_QE) +# undef CONFIG_STM32_TIM6 #endif -#if defined(CONFIG_STM32U5_TIM7_PWM) || defined (CONFIG_STM32U5_TIM7_ADC) || \ - defined(CONFIG_STM32U5_TIM7_DAC) || defined(CONFIG_STM32U5_TIM7_QE) -# undef CONFIG_STM32U5_TIM7 +#if defined(CONFIG_STM32_TIM7_PWM) || defined (CONFIG_STM32_TIM7_ADC) || \ + defined(CONFIG_STM32_TIM7_DAC) || defined(CONFIG_STM32_TIM7_QE) +# undef CONFIG_STM32_TIM7 #endif -#if defined(CONFIG_STM32U5_TIM8_PWM) || defined (CONFIG_STM32U5_TIM8_ADC) || \ - defined(CONFIG_STM32U5_TIM8_DAC) || defined(CONFIG_STM32U5_TIM8_QE) -# undef CONFIG_STM32U5_TIM8 +#if defined(CONFIG_STM32_TIM8_PWM) || defined (CONFIG_STM32_TIM8_ADC) || \ + defined(CONFIG_STM32_TIM8_DAC) || defined(CONFIG_STM32_TIM8_QE) +# undef CONFIG_STM32_TIM8 #endif -#if defined(CONFIG_STM32U5_TIM15_PWM) || defined (CONFIG_STM32U5_TIM15_ADC) || \ - defined(CONFIG_STM32U5_TIM15_DAC) || defined(CONFIG_STM32U5_TIM15_QE) -# undef CONFIG_STM32U5_TIM15 +#if defined(CONFIG_STM32_TIM15_PWM) || defined (CONFIG_STM32_TIM15_ADC) || \ + defined(CONFIG_STM32_TIM15_DAC) || defined(CONFIG_STM32_TIM15_QE) +# undef CONFIG_STM32_TIM15 #endif -#if defined(CONFIG_STM32U5_TIM16_PWM) || defined (CONFIG_STM32U5_TIM16_ADC) || \ - defined(CONFIG_STM32U5_TIM16_DAC) || defined(CONFIG_STM32U5_TIM16_QE) -# undef CONFIG_STM32U5_TIM16 +#if defined(CONFIG_STM32_TIM16_PWM) || defined (CONFIG_STM32_TIM16_ADC) || \ + defined(CONFIG_STM32_TIM16_DAC) || defined(CONFIG_STM32_TIM16_QE) +# undef CONFIG_STM32_TIM16 #endif -#if defined(CONFIG_STM32U5_TIM17_PWM) || defined (CONFIG_STM32U5_TIM17_ADC) || \ - defined(CONFIG_STM32U5_TIM17_DAC) || defined(CONFIG_STM32U5_TIM17_QE) -# undef CONFIG_STM32U5_TIM17 +#if defined(CONFIG_STM32_TIM17_PWM) || defined (CONFIG_STM32_TIM17_ADC) || \ + defined(CONFIG_STM32_TIM17_DAC) || defined(CONFIG_STM32_TIM17_QE) +# undef CONFIG_STM32_TIM17 #endif -#if defined(CONFIG_STM32U5_TIM1) +#if defined(CONFIG_STM32_TIM1) # if defined(GPIO_TIM1_CH1OUT) ||defined(GPIO_TIM1_CH2OUT)||\ defined(GPIO_TIM1_CH3OUT) ||defined(GPIO_TIM1_CH4OUT) # define HAVE_TIM1_GPIOCONFIG 1 #endif #endif -#if defined(CONFIG_STM32U5_TIM2) +#if defined(CONFIG_STM32_TIM2) # if defined(GPIO_TIM2_CH1OUT) ||defined(GPIO_TIM2_CH2OUT)||\ defined(GPIO_TIM2_CH3OUT) ||defined(GPIO_TIM2_CH4OUT) # define HAVE_TIM2_GPIOCONFIG 1 #endif #endif -#if defined(CONFIG_STM32U5_TIM3) +#if defined(CONFIG_STM32_TIM3) # if defined(GPIO_TIM3_CH1OUT) ||defined(GPIO_TIM3_CH2OUT)||\ defined(GPIO_TIM3_CH3OUT) ||defined(GPIO_TIM3_CH4OUT) # define HAVE_TIM3_GPIOCONFIG 1 #endif #endif -#if defined(CONFIG_STM32U5_TIM4) +#if defined(CONFIG_STM32_TIM4) # if defined(GPIO_TIM4_CH1OUT) ||defined(GPIO_TIM4_CH2OUT)||\ defined(GPIO_TIM4_CH3OUT) ||defined(GPIO_TIM4_CH4OUT) # define HAVE_TIM4_GPIOCONFIG 1 #endif #endif -#if defined(CONFIG_STM32U5_TIM5) +#if defined(CONFIG_STM32_TIM5) # if defined(GPIO_TIM5_CH1OUT) ||defined(GPIO_TIM5_CH2OUT)||\ defined(GPIO_TIM5_CH3OUT) ||defined(GPIO_TIM5_CH4OUT) # define HAVE_TIM5_GPIOCONFIG 1 #endif #endif -#if defined(CONFIG_STM32U5_TIM8) +#if defined(CONFIG_STM32_TIM8) # if defined(GPIO_TIM8_CH1OUT) ||defined(GPIO_TIM8_CH2OUT)||\ defined(GPIO_TIM8_CH3OUT) ||defined(GPIO_TIM8_CH4OUT) # define HAVE_TIM8_GPIOCONFIG 1 #endif #endif -#if defined(CONFIG_STM32U5_TIM15) +#if defined(CONFIG_STM32_TIM15) # if defined(GPIO_TIM15_CH1OUT) ||defined(GPIO_TIM15_CH2OUT)||\ defined(GPIO_TIM15_CH3OUT) ||defined(GPIO_TIM15_CH4OUT) # define HAVE_TIM15_GPIOCONFIG 1 #endif #endif -#if defined(CONFIG_STM32U5_TIM16) +#if defined(CONFIG_STM32_TIM16) # if defined(GPIO_TIM16_CH1OUT) ||defined(GPIO_TIM16_CH2OUT)||\ defined(GPIO_TIM16_CH3OUT) ||defined(GPIO_TIM16_CH4OUT) # define HAVE_TIM16_GPIOCONFIG 1 #endif #endif -#if defined(CONFIG_STM32U5_TIM17) +#if defined(CONFIG_STM32_TIM17) # if defined(GPIO_TIM17_CH1OUT) ||defined(GPIO_TIM17_CH2OUT)||\ defined(GPIO_TIM17_CH3OUT) ||defined(GPIO_TIM17_CH4OUT) # define HAVE_TIM17_GPIOCONFIG 1 @@ -195,12 +195,12 @@ * intended for some other purpose. */ -#if defined(CONFIG_STM32U5_TIM1) || defined(CONFIG_STM32U5_TIM2) || \ - defined(CONFIG_STM32U5_TIM3) || defined(CONFIG_STM32U5_TIM4) || \ - defined(CONFIG_STM32U5_TIM5) || defined(CONFIG_STM32U5_TIM6) || \ - defined(CONFIG_STM32U5_TIM7) || defined(CONFIG_STM32U5_TIM8) || \ - defined(CONFIG_STM32U5_TIM15) || defined(CONFIG_STM32U5_TIM16) || \ - defined(CONFIG_STM32U5_TIM17) +#if defined(CONFIG_STM32_TIM1) || defined(CONFIG_STM32_TIM2) || \ + defined(CONFIG_STM32_TIM3) || defined(CONFIG_STM32_TIM4) || \ + defined(CONFIG_STM32_TIM5) || defined(CONFIG_STM32_TIM6) || \ + defined(CONFIG_STM32_TIM7) || defined(CONFIG_STM32_TIM8) || \ + defined(CONFIG_STM32_TIM15) || defined(CONFIG_STM32_TIM16) || \ + defined(CONFIG_STM32_TIM17) /**************************************************************************** * Private Types @@ -301,101 +301,101 @@ static const struct stm32_tim_ops_s stm32_tim_ops = .checkint = stm32_tim_checkint, }; -#ifdef CONFIG_STM32U5_TIM1 +#ifdef CONFIG_STM32_TIM1 struct stm32_tim_priv_s stm32_tim1_priv = { .ops = &stm32_tim_ops, - .mode = STM32U5_TIM_MODE_UNUSED, - .base = STM32U5_TIM1_BASE, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM1_BASE, }; #endif -#ifdef CONFIG_STM32U5_TIM2 +#ifdef CONFIG_STM32_TIM2 struct stm32_tim_priv_s stm32_tim2_priv = { .ops = &stm32_tim_ops, - .mode = STM32U5_TIM_MODE_UNUSED, - .base = STM32U5_TIM2_BASE, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM2_BASE, }; #endif -#ifdef CONFIG_STM32U5_TIM3 +#ifdef CONFIG_STM32_TIM3 struct stm32_tim_priv_s stm32_tim3_priv = { .ops = &stm32_tim_ops, - .mode = STM32U5_TIM_MODE_UNUSED, - .base = STM32U5_TIM3_BASE, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM3_BASE, }; #endif -#ifdef CONFIG_STM32U5_TIM4 +#ifdef CONFIG_STM32_TIM4 struct stm32_tim_priv_s stm32_tim4_priv = { .ops = &stm32_tim_ops, - .mode = STM32U5_TIM_MODE_UNUSED, - .base = STM32U5_TIM4_BASE, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM4_BASE, }; #endif -#ifdef CONFIG_STM32U5_TIM5 +#ifdef CONFIG_STM32_TIM5 struct stm32_tim_priv_s stm32_tim5_priv = { .ops = &stm32_tim_ops, - .mode = STM32U5_TIM_MODE_UNUSED, - .base = STM32U5_TIM5_BASE, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM5_BASE, }; #endif -#ifdef CONFIG_STM32U5_TIM6 +#ifdef CONFIG_STM32_TIM6 struct stm32_tim_priv_s stm32_tim6_priv = { .ops = &stm32_tim_ops, - .mode = STM32U5_TIM_MODE_UNUSED, - .base = STM32U5_TIM6_BASE, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM6_BASE, }; #endif -#ifdef CONFIG_STM32U5_TIM7 +#ifdef CONFIG_STM32_TIM7 struct stm32_tim_priv_s stm32_tim7_priv = { .ops = &stm32_tim_ops, - .mode = STM32U5_TIM_MODE_UNUSED, - .base = STM32U5_TIM7_BASE, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM7_BASE, }; #endif -#ifdef CONFIG_STM32U5_TIM8 +#ifdef CONFIG_STM32_TIM8 struct stm32_tim_priv_s stm32_tim8_priv = { .ops = &stm32_tim_ops, - .mode = STM32U5_TIM_MODE_UNUSED, - .base = STM32U5_TIM8_BASE, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM8_BASE, }; #endif -#ifdef CONFIG_STM32U5_TIM15 +#ifdef CONFIG_STM32_TIM15 struct stm32_tim_priv_s stm32_tim15_priv = { .ops = &stm32_tim_ops, - .mode = STM32U5_TIM_MODE_UNUSED, - .base = STM32U5_TIM15_BASE, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM15_BASE, }; #endif -#ifdef CONFIG_STM32U5_TIM16 +#ifdef CONFIG_STM32_TIM16 struct stm32_tim_priv_s stm32_tim16_priv = { .ops = &stm32_tim_ops, - .mode = STM32U5_TIM_MODE_UNUSED, - .base = STM32U5_TIM16_BASE, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM16_BASE, }; #endif -#ifdef CONFIG_STM32U5_TIM17 +#ifdef CONFIG_STM32_TIM17 struct stm32_tim_priv_s stm32_tim17_priv = { .ops = &stm32_tim_ops, - .mode = STM32U5_TIM_MODE_UNUSED, - .base = STM32U5_TIM17_BASE, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM17_BASE, }; #endif @@ -483,9 +483,9 @@ static inline void stm32_putreg32(struct stm32_tim_dev_s *dev, static void stm32_tim_reload_counter(struct stm32_tim_dev_s *dev) { - uint16_t val = stm32_getreg16(dev, STM32U5_GTIM_EGR_OFFSET); + uint16_t val = stm32_getreg16(dev, STM32_GTIM_EGR_OFFSET); val |= GTIM_EGR_UG; - stm32_putreg16(dev, STM32U5_GTIM_EGR_OFFSET, val); + stm32_putreg16(dev, STM32_GTIM_EGR_OFFSET, val); } /**************************************************************************** @@ -494,10 +494,10 @@ static void stm32_tim_reload_counter(struct stm32_tim_dev_s *dev) static void stm32_tim_enable(struct stm32_tim_dev_s *dev) { - uint16_t val = stm32_getreg16(dev, STM32U5_GTIM_CR1_OFFSET); + uint16_t val = stm32_getreg16(dev, STM32_GTIM_CR1_OFFSET); val |= GTIM_CR1_CEN; stm32_tim_reload_counter(dev); - stm32_putreg16(dev, STM32U5_GTIM_CR1_OFFSET, val); + stm32_putreg16(dev, STM32_GTIM_CR1_OFFSET, val); } /**************************************************************************** @@ -506,9 +506,9 @@ static void stm32_tim_enable(struct stm32_tim_dev_s *dev) static void stm32_tim_disable(struct stm32_tim_dev_s *dev) { - uint16_t val = stm32_getreg16(dev, STM32U5_GTIM_CR1_OFFSET); + uint16_t val = stm32_getreg16(dev, STM32_GTIM_CR1_OFFSET); val &= ~GTIM_CR1_CEN; - stm32_putreg16(dev, STM32U5_GTIM_CR1_OFFSET, val); + stm32_putreg16(dev, STM32_GTIM_CR1_OFFSET, val); } /**************************************************************************** @@ -522,7 +522,7 @@ static void stm32_tim_disable(struct stm32_tim_dev_s *dev) static void stm32_tim_reset(struct stm32_tim_dev_s *dev) { - ((struct stm32_tim_priv_s *)dev)->mode = STM32U5_TIM_MODE_DISABLED; + ((struct stm32_tim_priv_s *)dev)->mode = STM32_TIM_MODE_DISABLED; stm32_tim_disable(dev); } @@ -540,7 +540,7 @@ static void stm32_tim_gpioconfig(uint32_t cfg, { /* TODO: Add support for input capture and bipolar dual outputs for TIM8 */ - if (mode & STM32U5_TIM_CH_MODE_MASK) + if (mode & STM32_TIM_CH_MODE_MASK) { stm32_configgpio(cfg); } @@ -566,13 +566,13 @@ static int stm32_tim_setmode(struct stm32_tim_dev_s *dev, * disable it, simply set its clock to valid frequency or zero. */ -#if STM32U5_NBTIM > 0 - if (((struct stm32_tim_priv_s *)dev)->base == STM32U5_TIM6_BASE +#if STM32_NBTIM > 0 + if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM6_BASE #endif -#if STM32U5_NBTIM > 1 - || ((struct stm32_tim_priv_s *)dev)->base == STM32U5_TIM7_BASE +#if STM32_NBTIM > 1 + || ((struct stm32_tim_priv_s *)dev)->base == STM32_TIM7_BASE #endif -#if STM32U5_NBTIM > 0 +#if STM32_NBTIM > 0 ) { return -EINVAL; @@ -581,19 +581,19 @@ static int stm32_tim_setmode(struct stm32_tim_dev_s *dev, /* Decode operational modes */ - switch (mode & STM32U5_TIM_MODE_MASK) + switch (mode & STM32_TIM_MODE_MASK) { - case STM32U5_TIM_MODE_DISABLED: + case STM32_TIM_MODE_DISABLED: val = 0; break; - case STM32U5_TIM_MODE_DOWN: + case STM32_TIM_MODE_DOWN: val |= GTIM_CR1_DIR; - case STM32U5_TIM_MODE_UP: + case STM32_TIM_MODE_UP: break; - case STM32U5_TIM_MODE_UPDOWN: + case STM32_TIM_MODE_UPDOWN: val |= GTIM_CR1_CENTER1; /* Our default: Interrupts are generated on compare, when counting @@ -602,7 +602,7 @@ static int stm32_tim_setmode(struct stm32_tim_dev_s *dev, break; - case STM32U5_TIM_MODE_PULSE: + case STM32_TIM_MODE_PULSE: val |= GTIM_CR1_OPM; break; @@ -611,15 +611,15 @@ static int stm32_tim_setmode(struct stm32_tim_dev_s *dev, } stm32_tim_reload_counter(dev); - stm32_putreg16(dev, STM32U5_GTIM_CR1_OFFSET, val); + stm32_putreg16(dev, STM32_GTIM_CR1_OFFSET, val); -#if STM32U5_NATIM > 0 +#if STM32_NATIM > 0 /* Advanced registers require Main Output Enable */ - if (((struct stm32_tim_priv_s *)dev)->base == STM32U5_TIM1_BASE || - ((struct stm32_tim_priv_s *)dev)->base == STM32U5_TIM8_BASE) + if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM1_BASE || + ((struct stm32_tim_priv_s *)dev)->base == STM32_TIM8_BASE) { - stm32_modifyreg16(dev, STM32U5_ATIM_BDTR_OFFSET, 0, ATIM_BDTR_MOE); + stm32_modifyreg16(dev, STM32_ATIM_BDTR_OFFSET, 0, ATIM_BDTR_MOE); } #endif @@ -654,67 +654,67 @@ static int stm32_tim_setclock(struct stm32_tim_dev_s *dev, switch (((struct stm32_tim_priv_s *)dev)->base) { -#ifdef CONFIG_STM32U5_TIM1 - case STM32U5_TIM1_BASE: +#ifdef CONFIG_STM32_TIM1 + case STM32_TIM1_BASE: freqin = BOARD_TIM1_FREQUENCY; break; #endif -#ifdef CONFIG_STM32U5_TIM2 - case STM32U5_TIM2_BASE: +#ifdef CONFIG_STM32_TIM2 + case STM32_TIM2_BASE: freqin = BOARD_TIM2_FREQUENCY; break; #endif -#ifdef CONFIG_STM32U5_TIM3 - case STM32U5_TIM3_BASE: +#ifdef CONFIG_STM32_TIM3 + case STM32_TIM3_BASE: freqin = BOARD_TIM3_FREQUENCY; break; #endif -#ifdef CONFIG_STM32U5_TIM4 - case STM32U5_TIM4_BASE: +#ifdef CONFIG_STM32_TIM4 + case STM32_TIM4_BASE: freqin = BOARD_TIM4_FREQUENCY; break; #endif -#ifdef CONFIG_STM32U5_TIM5 - case STM32U5_TIM5_BASE: +#ifdef CONFIG_STM32_TIM5 + case STM32_TIM5_BASE: freqin = BOARD_TIM5_FREQUENCY; break; #endif -#ifdef CONFIG_STM32U5_TIM6 - case STM32U5_TIM6_BASE: +#ifdef CONFIG_STM32_TIM6 + case STM32_TIM6_BASE: freqin = BOARD_TIM6_FREQUENCY; break; #endif -#ifdef CONFIG_STM32U5_TIM7 - case STM32U5_TIM7_BASE: +#ifdef CONFIG_STM32_TIM7 + case STM32_TIM7_BASE: freqin = BOARD_TIM7_FREQUENCY; break; #endif -#ifdef CONFIG_STM32U5_TIM8 - case STM32U5_TIM8_BASE: +#ifdef CONFIG_STM32_TIM8 + case STM32_TIM8_BASE: freqin = BOARD_TIM8_FREQUENCY; break; #endif -#ifdef CONFIG_STM32U5_TIM15 - case STM32U5_TIM15_BASE: +#ifdef CONFIG_STM32_TIM15 + case STM32_TIM15_BASE: freqin = BOARD_TIM15_FREQUENCY; break; #endif -#ifdef CONFIG_STM32U5_TIM16 - case STM32U5_TIM16_BASE: +#ifdef CONFIG_STM32_TIM16 + case STM32_TIM16_BASE: freqin = BOARD_TIM16_FREQUENCY; break; #endif -#ifdef CONFIG_STM32U5_TIM17 - case STM32U5_TIM17_BASE: +#ifdef CONFIG_STM32_TIM17 + case STM32_TIM17_BASE: freqin = BOARD_TIM17_FREQUENCY; break; #endif @@ -745,7 +745,7 @@ static int stm32_tim_setclock(struct stm32_tim_dev_s *dev, prescaler = 0xffff; } - stm32_putreg16(dev, STM32U5_GTIM_PSC_OFFSET, prescaler); + stm32_putreg16(dev, STM32_GTIM_PSC_OFFSET, prescaler); stm32_tim_enable(dev); return prescaler; @@ -769,65 +769,65 @@ static uint32_t stm32_tim_getclock(struct stm32_tim_dev_s *dev) switch (((struct stm32_tim_priv_s *)dev)->base) { -#ifdef CONFIG_STM32U5_TIM1 - case STM32U5_TIM1_BASE: +#ifdef CONFIG_STM32_TIM1 + case STM32_TIM1_BASE: freqin = BOARD_TIM1_FREQUENCY; break; #endif -#ifdef CONFIG_STM32U5_TIM2 - case STM32U5_TIM2_BASE: +#ifdef CONFIG_STM32_TIM2 + case STM32_TIM2_BASE: freqin = BOARD_TIM2_FREQUENCY; break; #endif -#ifdef CONFIG_STM32U5_TIM3 - case STM32U5_TIM3_BASE: +#ifdef CONFIG_STM32_TIM3 + case STM32_TIM3_BASE: freqin = BOARD_TIM3_FREQUENCY; break; #endif -#ifdef CONFIG_STM32U5_TIM4 - case STM32U5_TIM4_BASE: +#ifdef CONFIG_STM32_TIM4 + case STM32_TIM4_BASE: freqin = BOARD_TIM4_FREQUENCY; break; #endif -#ifdef CONFIG_STM32U5_TIM5 - case STM32U5_TIM5_BASE: +#ifdef CONFIG_STM32_TIM5 + case STM32_TIM5_BASE: freqin = BOARD_TIM5_FREQUENCY; break; #endif -#ifdef CONFIG_STM32U5_TIM6 - case STM32U5_TIM6_BASE: +#ifdef CONFIG_STM32_TIM6 + case STM32_TIM6_BASE: freqin = BOARD_TIM6_FREQUENCY; break; #endif -#ifdef CONFIG_STM32U5_TIM7 - case STM32U5_TIM7_BASE: +#ifdef CONFIG_STM32_TIM7 + case STM32_TIM7_BASE: freqin = BOARD_TIM7_FREQUENCY; break; #endif -#ifdef CONFIG_STM32U5_TIM8 - case STM32U5_TIM8_BASE: +#ifdef CONFIG_STM32_TIM8 + case STM32_TIM8_BASE: freqin = BOARD_TIM8_FREQUENCY; break; #endif -#ifdef CONFIG_STM32U5_TIM15 - case STM32U5_TIM15_BASE: +#ifdef CONFIG_STM32_TIM15 + case STM32_TIM15_BASE: freqin = BOARD_TIM15_FREQUENCY; break; #endif -#ifdef CONFIG_STM32U5_TIM16 - case STM32U5_TIM16_BASE: +#ifdef CONFIG_STM32_TIM16 + case STM32_TIM16_BASE: freqin = BOARD_TIM16_FREQUENCY; break; #endif -#ifdef CONFIG_STM32U5_TIM17 - case STM32U5_TIM17_BASE: +#ifdef CONFIG_STM32_TIM17 + case STM32_TIM17_BASE: freqin = BOARD_TIM17_FREQUENCY; break; #endif @@ -837,7 +837,7 @@ static uint32_t stm32_tim_getclock(struct stm32_tim_dev_s *dev) /* From chip datasheet, at page 1179. */ - clock = freqin / (stm32_getreg16(dev, STM32U5_GTIM_PSC_OFFSET) + 1); + clock = freqin / (stm32_getreg16(dev, STM32_GTIM_PSC_OFFSET) + 1); return clock; } @@ -849,7 +849,7 @@ static void stm32_tim_setperiod(struct stm32_tim_dev_s *dev, uint32_t period) { DEBUGASSERT(dev != NULL); - stm32_putreg32(dev, STM32U5_GTIM_ARR_OFFSET, period); + stm32_putreg32(dev, STM32_GTIM_ARR_OFFSET, period); } /**************************************************************************** @@ -859,7 +859,7 @@ static void stm32_tim_setperiod(struct stm32_tim_dev_s *dev, static uint32_t stm32_tim_getperiod (struct stm32_tim_dev_s *dev) { DEBUGASSERT(dev != NULL); - return stm32_getreg32 (dev, STM32U5_GTIM_ARR_OFFSET); + return stm32_getreg32 (dev, STM32_GTIM_ARR_OFFSET); } /**************************************************************************** @@ -869,20 +869,20 @@ static uint32_t stm32_tim_getperiod (struct stm32_tim_dev_s *dev) static uint32_t stm32_tim_getcounter(struct stm32_tim_dev_s *dev) { DEBUGASSERT(dev != NULL); - uint32_t counter = stm32_getreg32(dev, STM32U5_GTIM_CNT_OFFSET); + uint32_t counter = stm32_getreg32(dev, STM32_GTIM_CNT_OFFSET); /* In datasheet page 988, there is a useless bit named UIFCPY in TIMx_CNT. * reset it it result when not TIM2 or TIM5. */ -#if defined(CONFIG_STM32U5_TIM2) || defined(CONFIG_STM32U5_TIM5) +#if defined(CONFIG_STM32_TIM2) || defined(CONFIG_STM32_TIM5) switch (((struct stm32_tim_priv_s *)dev)->base) { -#ifdef CONFIG_STM32U5_TIM2 - case STM32U5_TIM2_BASE: +#ifdef CONFIG_STM32_TIM2 + case STM32_TIM2_BASE: #endif -#ifdef CONFIG_STM32U5_TIM5 - case STM32U5_TIM5_BASE: +#ifdef CONFIG_STM32_TIM5 + case STM32_TIM5_BASE: #endif return counter; @@ -906,7 +906,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, uint16_t ccmr_val = 0; uint16_t ccmr_mask = 0xff; uint16_t ccer_val; - uint8_t ccmr_offset = STM32U5_GTIM_CCMR1_OFFSET; + uint8_t ccmr_offset = STM32_GTIM_CCMR1_OFFSET; DEBUGASSERT(dev != NULL); @@ -919,7 +919,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, /* Assume that channel is disabled and polarity is active high */ - ccer_val = stm32_getreg16(dev, STM32U5_GTIM_CCER_OFFSET); + ccer_val = stm32_getreg16(dev, STM32_GTIM_CCER_OFFSET); ccer_val &= ~((GTIM_CCER_CC1P | GTIM_CCER_CC1E) << GTIM_CCER_CCXBASE(channel)); @@ -927,13 +927,13 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, * disable it, simply set its clock to valid frequency or zero. */ -#if STM32U5_NBTIM > 0 - if (((struct stm32_tim_priv_s *)dev)->base == STM32U5_TIM6_BASE +#if STM32_NBTIM > 0 + if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM6_BASE #endif -#if STM32U5_NBTIM > 1 - || ((struct stm32_tim_priv_s *)dev)->base == STM32U5_TIM7_BASE +#if STM32_NBTIM > 1 + || ((struct stm32_tim_priv_s *)dev)->base == STM32_TIM7_BASE #endif -#if STM32U5_NBTIM > 0 +#if STM32_NBTIM > 0 ) { return -EINVAL; @@ -942,12 +942,12 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, /* Decode configuration */ - switch (mode & STM32U5_TIM_CH_MODE_MASK) + switch (mode & STM32_TIM_CH_MODE_MASK) { - case STM32U5_TIM_CH_DISABLED: + case STM32_TIM_CH_DISABLED: break; - case STM32U5_TIM_CH_OUTPWM: + case STM32_TIM_CH_OUTPWM: ccmr_val = (GTIM_CCMR_MODE_PWM1 << GTIM_CCMR1_OC1M_SHIFT) + GTIM_CCMR1_OC1PE; ccer_val |= GTIM_CCER_CC1E << GTIM_CCER_CCXBASE(channel); @@ -959,7 +959,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, /* Set polarity */ - if (mode & STM32U5_TIM_CH_POLARITY_NEG) + if (mode & STM32_TIM_CH_POLARITY_NEG) { ccer_val |= GTIM_CCER_CC1P << GTIM_CCER_CCXBASE(channel); } @@ -974,21 +974,21 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, if (channel > 1) { - ccmr_offset = STM32U5_GTIM_CCMR2_OFFSET; + ccmr_offset = STM32_GTIM_CCMR2_OFFSET; } ccmr_orig = stm32_getreg16(dev, ccmr_offset); ccmr_orig &= ~ccmr_mask; ccmr_orig |= ccmr_val; stm32_putreg16(dev, ccmr_offset, ccmr_orig); - stm32_putreg16(dev, STM32U5_GTIM_CCER_OFFSET, ccer_val); + stm32_putreg16(dev, STM32_GTIM_CCER_OFFSET, ccer_val); /* set GPIO */ switch (((struct stm32_tim_priv_s *)dev)->base) { -#ifdef CONFIG_STM32U5_TIM1 - case STM32U5_TIM1_BASE: +#ifdef CONFIG_STM32_TIM1 + case STM32_TIM1_BASE: switch (channel) { #if defined(GPIO_TIM1_CH1OUT) @@ -1020,8 +1020,8 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32U5_TIM2 - case STM32U5_TIM2_BASE: +#ifdef CONFIG_STM32_TIM2 + case STM32_TIM2_BASE: switch (channel) { #if defined(GPIO_TIM2_CH1OUT) @@ -1053,8 +1053,8 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32U5_TIM3 - case STM32U5_TIM3_BASE: +#ifdef CONFIG_STM32_TIM3 + case STM32_TIM3_BASE: switch (channel) { #if defined(GPIO_TIM3_CH1OUT) @@ -1086,8 +1086,8 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32U5_TIM4 - case STM32U5_TIM4_BASE: +#ifdef CONFIG_STM32_TIM4 + case STM32_TIM4_BASE: switch (channel) { #if defined(GPIO_TIM4_CH1OUT) @@ -1118,8 +1118,8 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32U5_TIM5 - case STM32U5_TIM5_BASE: +#ifdef CONFIG_STM32_TIM5 + case STM32_TIM5_BASE: switch (channel) { #if defined(GPIO_TIM5_CH1OUT) @@ -1151,8 +1151,8 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32U5_TIM8 - case STM32U5_TIM8_BASE: +#ifdef CONFIG_STM32_TIM8 + case STM32_TIM8_BASE: switch (channel) { #if defined(GPIO_TIM8_CH1OUT) @@ -1184,8 +1184,8 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32U5_TIM15 - case STM32U5_TIM15_BASE: +#ifdef CONFIG_STM32_TIM15 + case STM32_TIM15_BASE: switch (channel) { #if defined(GPIO_TIM15_CH1OUT) @@ -1217,8 +1217,8 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32U5_TIM16 - case STM32U5_TIM16_BASE: +#ifdef CONFIG_STM32_TIM16 + case STM32_TIM16_BASE: switch (channel) { #if defined(GPIO_TIM16_CH1OUT) @@ -1250,8 +1250,8 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32U5_TIM17 - case STM32U5_TIM17_BASE: +#ifdef CONFIG_STM32_TIM17 + case STM32_TIM17_BASE: switch (channel) { #if defined(GPIO_TIM17_CH1OUT) @@ -1303,19 +1303,19 @@ static int stm32_tim_setcompare(struct stm32_tim_dev_s *dev, switch (channel) { case 1: - stm32_putreg32(dev, STM32U5_GTIM_CCR1_OFFSET, compare); + stm32_putreg32(dev, STM32_GTIM_CCR1_OFFSET, compare); break; case 2: - stm32_putreg32(dev, STM32U5_GTIM_CCR2_OFFSET, compare); + stm32_putreg32(dev, STM32_GTIM_CCR2_OFFSET, compare); break; case 3: - stm32_putreg32(dev, STM32U5_GTIM_CCR3_OFFSET, compare); + stm32_putreg32(dev, STM32_GTIM_CCR3_OFFSET, compare); break; case 4: - stm32_putreg32(dev, STM32U5_GTIM_CCR4_OFFSET, compare); + stm32_putreg32(dev, STM32_GTIM_CCR4_OFFSET, compare); break; default: @@ -1337,16 +1337,16 @@ static int stm32_tim_getcapture(struct stm32_tim_dev_s *dev, switch (channel) { case 1: - return stm32_getreg32(dev, STM32U5_GTIM_CCR1_OFFSET); + return stm32_getreg32(dev, STM32_GTIM_CCR1_OFFSET); case 2: - return stm32_getreg32(dev, STM32U5_GTIM_CCR2_OFFSET); + return stm32_getreg32(dev, STM32_GTIM_CCR2_OFFSET); case 3: - return stm32_getreg32(dev, STM32U5_GTIM_CCR3_OFFSET); + return stm32_getreg32(dev, STM32_GTIM_CCR3_OFFSET); case 4: - return stm32_getreg32(dev, STM32U5_GTIM_CCR4_OFFSET); + return stm32_getreg32(dev, STM32_GTIM_CCR4_OFFSET); } return -EINVAL; @@ -1366,67 +1366,67 @@ static int stm32_tim_setisr(struct stm32_tim_dev_s *dev, switch (((struct stm32_tim_priv_s *)dev)->base) { -#ifdef CONFIG_STM32U5_TIM1 - case STM32U5_TIM1_BASE: - vectorno = STM32U5_IRQ_TIM1UP; +#ifdef CONFIG_STM32_TIM1 + case STM32_TIM1_BASE: + vectorno = STM32_IRQ_TIM1UP; break; #endif -#ifdef CONFIG_STM32U5_TIM2 - case STM32U5_TIM2_BASE: - vectorno = STM32U5_IRQ_TIM2; +#ifdef CONFIG_STM32_TIM2 + case STM32_TIM2_BASE: + vectorno = STM32_IRQ_TIM2; break; #endif -#ifdef CONFIG_STM32U5_TIM3 - case STM32U5_TIM3_BASE: - vectorno = STM32U5_IRQ_TIM3; +#ifdef CONFIG_STM32_TIM3 + case STM32_TIM3_BASE: + vectorno = STM32_IRQ_TIM3; break; #endif -#ifdef CONFIG_STM32U5_TIM4 - case STM32U5_TIM4_BASE: - vectorno = STM32U5_IRQ_TIM4; +#ifdef CONFIG_STM32_TIM4 + case STM32_TIM4_BASE: + vectorno = STM32_IRQ_TIM4; break; #endif -#ifdef CONFIG_STM32U5_TIM5 - case STM32U5_TIM5_BASE: - vectorno = STM32U5_IRQ_TIM5; +#ifdef CONFIG_STM32_TIM5 + case STM32_TIM5_BASE: + vectorno = STM32_IRQ_TIM5; break; #endif -#ifdef CONFIG_STM32U5_TIM6 - case STM32U5_TIM6_BASE: - vectorno = STM32U5_IRQ_TIM6; +#ifdef CONFIG_STM32_TIM6 + case STM32_TIM6_BASE: + vectorno = STM32_IRQ_TIM6; break; #endif -#ifdef CONFIG_STM32U5_TIM7 - case STM32U5_TIM7_BASE: - vectorno = STM32U5_IRQ_TIM7; +#ifdef CONFIG_STM32_TIM7 + case STM32_TIM7_BASE: + vectorno = STM32_IRQ_TIM7; break; #endif -#ifdef CONFIG_STM32U5_TIM8 - case STM32U5_TIM8_BASE: - vectorno = STM32U5_IRQ_TIM8UP; +#ifdef CONFIG_STM32_TIM8 + case STM32_TIM8_BASE: + vectorno = STM32_IRQ_TIM8UP; break; #endif -#ifdef CONFIG_STM32U5_TIM15 - case STM32U5_TIM15_BASE: - vectorno = STM32U5_IRQ_TIM15; +#ifdef CONFIG_STM32_TIM15 + case STM32_TIM15_BASE: + vectorno = STM32_IRQ_TIM15; break; #endif -#ifdef CONFIG_STM32U5_TIM16 - case STM32U5_TIM16_BASE: - vectorno = STM32U5_IRQ_TIM16; +#ifdef CONFIG_STM32_TIM16 + case STM32_TIM16_BASE: + vectorno = STM32_IRQ_TIM16; break; #endif -#ifdef CONFIG_STM32U5_TIM17 - case STM32U5_TIM17_BASE: - vectorno = STM32U5_IRQ_TIM17; +#ifdef CONFIG_STM32_TIM17 + case STM32_TIM17_BASE: + vectorno = STM32_IRQ_TIM17; break; #endif @@ -1459,7 +1459,7 @@ static void stm32_tim_enableint(struct stm32_tim_dev_s *dev, int source) { DEBUGASSERT(dev != NULL); - stm32_modifyreg16(dev, STM32U5_GTIM_DIER_OFFSET, 0, GTIM_DIER_UIE); + stm32_modifyreg16(dev, STM32_GTIM_DIER_OFFSET, 0, GTIM_DIER_UIE); } /**************************************************************************** @@ -1470,7 +1470,7 @@ static void stm32_tim_disableint(struct stm32_tim_dev_s *dev, int source) { DEBUGASSERT(dev != NULL); - stm32_modifyreg16(dev, STM32U5_GTIM_DIER_OFFSET, GTIM_DIER_UIE, 0); + stm32_modifyreg16(dev, STM32_GTIM_DIER_OFFSET, GTIM_DIER_UIE, 0); } /**************************************************************************** @@ -1479,7 +1479,7 @@ static void stm32_tim_disableint(struct stm32_tim_dev_s *dev, static void stm32_tim_ackint(struct stm32_tim_dev_s *dev, int source) { - stm32_putreg16(dev, STM32U5_GTIM_SR_OFFSET, ~GTIM_SR_UIF); + stm32_putreg16(dev, STM32_GTIM_SR_OFFSET, ~GTIM_SR_UIF); } /**************************************************************************** @@ -1489,7 +1489,7 @@ static void stm32_tim_ackint(struct stm32_tim_dev_s *dev, int source) static int stm32_tim_checkint(struct stm32_tim_dev_s *dev, int source) { - uint16_t regval = stm32_getreg16(dev, STM32U5_GTIM_SR_OFFSET); + uint16_t regval = stm32_getreg16(dev, STM32_GTIM_SR_OFFSET); return (regval & GTIM_SR_UIF) ? 1 : 0; } @@ -1509,79 +1509,79 @@ struct stm32_tim_dev_s *stm32_tim_init(int timer) switch (timer) { -#ifdef CONFIG_STM32U5_TIM1 +#ifdef CONFIG_STM32_TIM1 case 1: dev = (struct stm32_tim_dev_s *)&stm32_tim1_priv; - modifyreg32(STM32U5_RCC_APB2ENR, 0, RCC_APB2ENR_TIM1EN); + modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM1EN); break; #endif -#ifdef CONFIG_STM32U5_TIM2 +#ifdef CONFIG_STM32_TIM2 case 2: dev = (struct stm32_tim_dev_s *)&stm32_tim2_priv; - modifyreg32(STM32U5_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM2EN); + modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM2EN); break; #endif -#ifdef CONFIG_STM32U5_TIM3 +#ifdef CONFIG_STM32_TIM3 case 3: dev = (struct stm32_tim_dev_s *)&stm32_tim3_priv; - modifyreg32(STM32U5_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM3EN); + modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM3EN); break; #endif -#ifdef CONFIG_STM32U5_TIM4 +#ifdef CONFIG_STM32_TIM4 case 4: dev = (struct stm32_tim_dev_s *)&stm32_tim4_priv; - modifyreg32(STM32U5_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM4EN); + modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM4EN); break; #endif -#ifdef CONFIG_STM32U5_TIM5 +#ifdef CONFIG_STM32_TIM5 case 5: dev = (struct stm32_tim_dev_s *)&stm32_tim5_priv; - modifyreg32(STM32U5_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM5EN); + modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM5EN); break; #endif -#ifdef CONFIG_STM32U5_TIM6 +#ifdef CONFIG_STM32_TIM6 case 6: dev = (struct stm32_tim_dev_s *)&stm32_tim6_priv; - modifyreg32(STM32U5_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM6EN); + modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM6EN); break; #endif -#ifdef CONFIG_STM32U5_TIM7 +#ifdef CONFIG_STM32_TIM7 case 7: dev = (struct stm32_tim_dev_s *)&stm32_tim7_priv; - modifyreg32(STM32U5_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM7EN); + modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM7EN); break; #endif -#ifdef CONFIG_STM32U5_TIM8 +#ifdef CONFIG_STM32_TIM8 case 8: dev = (struct stm32_tim_dev_s *)&stm32_tim8_priv; - modifyreg32(STM32U5_RCC_APB2ENR, 0, RCC_APB2ENR_TIM8EN); + modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM8EN); break; #endif -#ifdef CONFIG_STM32U5_TIM15 +#ifdef CONFIG_STM32_TIM15 case 15: dev = (struct stm32_tim_dev_s *)&stm32_tim15_priv; - modifyreg32(STM32U5_RCC_APB2ENR, 0, RCC_APB2ENR_TIM15EN); + modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM15EN); break; #endif -#ifdef CONFIG_STM32U5_TIM16 +#ifdef CONFIG_STM32_TIM16 case 16: dev = (struct stm32_tim_dev_s *)&stm32_tim16_priv; - modifyreg32(STM32U5_RCC_APB2ENR, 0, RCC_APB2ENR_TIM16EN); + modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM16EN); break; #endif -#ifdef CONFIG_STM32U5_TIM17 +#ifdef CONFIG_STM32_TIM17 case 17: dev = (struct stm32_tim_dev_s *)&stm32_tim17_priv; - modifyreg32(STM32U5_RCC_APB2ENR, 0, RCC_APB2ENR_TIM17EN); + modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM17EN); break; #endif @@ -1591,7 +1591,7 @@ struct stm32_tim_dev_s *stm32_tim_init(int timer) /* Is device already allocated */ - if (((struct stm32_tim_priv_s *)dev)->mode != STM32U5_TIM_MODE_UNUSED) + if (((struct stm32_tim_priv_s *)dev)->mode != STM32_TIM_MODE_UNUSED) { return NULL; } @@ -1616,68 +1616,68 @@ int stm32_tim_deinit(struct stm32_tim_dev_s *dev) switch (((struct stm32_tim_priv_s *)dev)->base) { -#ifdef CONFIG_STM32U5_TIM1 - case STM32U5_TIM1_BASE: - modifyreg32(STM32U5_RCC_APB2ENR, RCC_APB2ENR_TIM1EN, 0); +#ifdef CONFIG_STM32_TIM1 + case STM32_TIM1_BASE: + modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM1EN, 0); break; #endif -#ifdef CONFIG_STM32U5_TIM2 - case STM32U5_TIM2_BASE: - modifyreg32(STM32U5_RCC_APB1ENR1, RCC_APB1ENR1_TIM2EN, 0); +#ifdef CONFIG_STM32_TIM2 + case STM32_TIM2_BASE: + modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM2EN, 0); break; #endif -#ifdef CONFIG_STM32U5_TIM3 - case STM32U5_TIM3_BASE: - modifyreg32(STM32U5_RCC_APB1ENR1, RCC_APB1ENR1_TIM3EN, 0); +#ifdef CONFIG_STM32_TIM3 + case STM32_TIM3_BASE: + modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM3EN, 0); break; #endif -#ifdef CONFIG_STM32U5_TIM4 - case STM32U5_TIM4_BASE: - modifyreg32(STM32U5_RCC_APB1ENR1, RCC_APB1ENR1_TIM4EN, 0); +#ifdef CONFIG_STM32_TIM4 + case STM32_TIM4_BASE: + modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM4EN, 0); break; #endif -#ifdef CONFIG_STM32U5_TIM5 - case STM32U5_TIM5_BASE: - modifyreg32(STM32U5_RCC_APB1ENR1, RCC_APB1ENR1_TIM5EN, 0); +#ifdef CONFIG_STM32_TIM5 + case STM32_TIM5_BASE: + modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM5EN, 0); break; #endif -#ifdef CONFIG_STM32U5_TIM6 - case STM32U5_TIM6_BASE: - modifyreg32(STM32U5_RCC_APB1ENR1, RCC_APB1ENR1_TIM6EN, 0); +#ifdef CONFIG_STM32_TIM6 + case STM32_TIM6_BASE: + modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM6EN, 0); break; #endif -#ifdef CONFIG_STM32U5_TIM7 - case STM32U5_TIM7_BASE: - modifyreg32(STM32U5_RCC_APB1ENR1, RCC_APB1ENR1_TIM7EN, 0); +#ifdef CONFIG_STM32_TIM7 + case STM32_TIM7_BASE: + modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM7EN, 0); break; #endif -#ifdef CONFIG_STM32U5_TIM8 - case STM32U5_TIM8_BASE: - modifyreg32(STM32U5_RCC_APB2ENR, RCC_APB2ENR_TIM8EN, 0); +#ifdef CONFIG_STM32_TIM8 + case STM32_TIM8_BASE: + modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM8EN, 0); break; #endif -#ifdef CONFIG_STM32U5_TIM15 - case STM32U5_TIM15_BASE: - modifyreg32(STM32U5_RCC_APB2ENR, RCC_APB2ENR_TIM15EN, 0); +#ifdef CONFIG_STM32_TIM15 + case STM32_TIM15_BASE: + modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM15EN, 0); break; #endif -#ifdef CONFIG_STM32U5_TIM16 - case STM32U5_TIM16_BASE: - modifyreg32(STM32U5_RCC_APB2ENR, RCC_APB2ENR_TIM16EN, 0); +#ifdef CONFIG_STM32_TIM16 + case STM32_TIM16_BASE: + modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM16EN, 0); break; #endif -#ifdef CONFIG_STM32U5_TIM17 - case STM32U5_TIM17_BASE: - modifyreg32(STM32U5_RCC_APB2ENR, RCC_APB2ENR_TIM17EN, 0); +#ifdef CONFIG_STM32_TIM17 + case STM32_TIM17_BASE: + modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM17EN, 0); break; #endif @@ -1687,9 +1687,9 @@ int stm32_tim_deinit(struct stm32_tim_dev_s *dev) /* Mark it as free */ - ((struct stm32_tim_priv_s *)dev)->mode = STM32U5_TIM_MODE_UNUSED; + ((struct stm32_tim_priv_s *)dev)->mode = STM32_TIM_MODE_UNUSED; return OK; } -#endif /* defined(CONFIG_STM32U5_TIM1 || ... || TIM17) */ +#endif /* defined(CONFIG_STM32_TIM1 || ... || TIM17) */ diff --git a/arch/arm/src/stm32u5/stm32_tim.h b/arch/arm/src/stm32u5/stm32_tim.h index e043e98f0e0b3..f61751552dd49 100644 --- a/arch/arm/src/stm32u5/stm32_tim.h +++ b/arch/arm/src/stm32u5/stm32_tim.h @@ -38,20 +38,20 @@ /* Helpers ******************************************************************/ -#define STM32U5_TIM_SETMODE(d,mode) ((d)->ops->setmode(d,mode)) -#define STM32U5_TIM_SETCLOCK(d,freq) ((d)->ops->setclock(d,freq)) -#define STM32U5_TIM_GETCLOCK(d) ((d)->ops->getclock(d)) -#define STM32U5_TIM_SETPERIOD(d,period) ((d)->ops->setperiod(d,period)) -#define STM32U5_TIM_GETPERIOD(d) ((d)->ops->getperiod(d)) -#define STM32U5_TIM_GETCOUNTER(d) ((d)->ops->getcounter(d)) -#define STM32U5_TIM_SETCHANNEL(d,ch,mode) ((d)->ops->setchannel(d,ch,mode)) -#define STM32U5_TIM_SETCOMPARE(d,ch,comp) ((d)->ops->setcompare(d,ch,comp)) -#define STM32U5_TIM_GETCAPTURE(d,ch) ((d)->ops->getcapture(d,ch)) -#define STM32U5_TIM_SETISR(d,hnd,arg,s) ((d)->ops->setisr(d,hnd,arg,s)) -#define STM32U5_TIM_ENABLEINT(d,s) ((d)->ops->enableint(d,s)) -#define STM32U5_TIM_DISABLEINT(d,s) ((d)->ops->disableint(d,s)) -#define STM32U5_TIM_ACKINT(d,s) ((d)->ops->ackint(d,s)) -#define STM32U5_TIM_CHECKINT(d,s) ((d)->ops->checkint(d,s)) +#define STM32_TIM_SETMODE(d,mode) ((d)->ops->setmode(d,mode)) +#define STM32_TIM_SETCLOCK(d,freq) ((d)->ops->setclock(d,freq)) +#define STM32_TIM_GETCLOCK(d) ((d)->ops->getclock(d)) +#define STM32_TIM_SETPERIOD(d,period) ((d)->ops->setperiod(d,period)) +#define STM32_TIM_GETPERIOD(d) ((d)->ops->getperiod(d)) +#define STM32_TIM_GETCOUNTER(d) ((d)->ops->getcounter(d)) +#define STM32_TIM_SETCHANNEL(d,ch,mode) ((d)->ops->setchannel(d,ch,mode)) +#define STM32_TIM_SETCOMPARE(d,ch,comp) ((d)->ops->setcompare(d,ch,comp)) +#define STM32_TIM_GETCAPTURE(d,ch) ((d)->ops->getcapture(d,ch)) +#define STM32_TIM_SETISR(d,hnd,arg,s) ((d)->ops->setisr(d,hnd,arg,s)) +#define STM32_TIM_ENABLEINT(d,s) ((d)->ops->enableint(d,s)) +#define STM32_TIM_DISABLEINT(d,s) ((d)->ops->disableint(d,s)) +#define STM32_TIM_ACKINT(d,s) ((d)->ops->ackint(d,s)) +#define STM32_TIM_CHECKINT(d,s) ((d)->ops->checkint(d,s)) #define STM32_TIM_ENABLE(d) ((d)->ops->enable(d)) #define STM32_TIM_DISABLE(d) ((d)->ops->disable(d)) @@ -81,34 +81,34 @@ struct stm32_tim_dev_s enum stm32_tim_mode_e { - STM32U5_TIM_MODE_UNUSED = -1, + STM32_TIM_MODE_UNUSED = -1, /* One of the following */ - STM32U5_TIM_MODE_MASK = 0x0310, - STM32U5_TIM_MODE_DISABLED = 0x0000, - STM32U5_TIM_MODE_UP = 0x0100, - STM32U5_TIM_MODE_DOWN = 0x0110, - STM32U5_TIM_MODE_UPDOWN = 0x0200, - STM32U5_TIM_MODE_PULSE = 0x0300, + STM32_TIM_MODE_MASK = 0x0310, + STM32_TIM_MODE_DISABLED = 0x0000, + STM32_TIM_MODE_UP = 0x0100, + STM32_TIM_MODE_DOWN = 0x0110, + STM32_TIM_MODE_UPDOWN = 0x0200, + STM32_TIM_MODE_PULSE = 0x0300, /* One of the following */ - STM32U5_TIM_MODE_CK_INT = 0x0000, + STM32_TIM_MODE_CK_INT = 0x0000, #if 0 - STM32U5_TIM_MODE_CK_INT_TRIG = 0x0400, - STM32U5_TIM_MODE_CK_EXT = 0x0800, - STM32U5_TIM_MODE_CK_EXT_TRIG = 0x0c00, + STM32_TIM_MODE_CK_INT_TRIG = 0x0400, + STM32_TIM_MODE_CK_EXT = 0x0800, + STM32_TIM_MODE_CK_EXT_TRIG = 0x0c00, #endif /* Clock sources, OR'ed with CK_EXT */ #if 0 - STM32U5_TIM_MODE_CK_CHINVALID = 0x0000, - STM32U5_TIM_MODE_CK_CH1 = 0x0001, - STM32U5_TIM_MODE_CK_CH2 = 0x0002, - STM32U5_TIM_MODE_CK_CH3 = 0x0003, - STM32U5_TIM_MODE_CK_CH4 = 0x0004 + STM32_TIM_MODE_CK_CHINVALID = 0x0000, + STM32_TIM_MODE_CK_CH1 = 0x0001, + STM32_TIM_MODE_CK_CH2 = 0x0002, + STM32_TIM_MODE_CK_CH3 = 0x0003, + STM32_TIM_MODE_CK_CH4 = 0x0004 #endif /* Todo: external trigger block */ @@ -118,22 +118,22 @@ enum stm32_tim_mode_e enum stm32_tim_channel_e { - STM32U5_TIM_CH_DISABLED = 0x00, + STM32_TIM_CH_DISABLED = 0x00, /* Common configuration */ - STM32U5_TIM_CH_POLARITY_POS = 0x00, - STM32U5_TIM_CH_POLARITY_NEG = 0x01, + STM32_TIM_CH_POLARITY_POS = 0x00, + STM32_TIM_CH_POLARITY_NEG = 0x01, /* MODES: */ - STM32U5_TIM_CH_MODE_MASK = 0x06, + STM32_TIM_CH_MODE_MASK = 0x06, /* Output Compare Modes */ - STM32U5_TIM_CH_OUTPWM = 0x04, /* Enable standard PWM mode, active high when counter < compare */ + STM32_TIM_CH_OUTPWM = 0x04, /* Enable standard PWM mode, active high when counter < compare */ #if 0 - STM32U5_TIM_CH_OUTCOMPARE = 0x06, + STM32_TIM_CH_OUTCOMPARE = 0x06, #endif /* TODO other modes ... as PWM capture, ENCODER and Hall Sensor */ diff --git a/arch/arm/src/stm32u5/stm32_tim_lowerhalf.c b/arch/arm/src/stm32u5/stm32_tim_lowerhalf.c index 92e5739a23329..a564a8af52538 100644 --- a/arch/arm/src/stm32u5/stm32_tim_lowerhalf.c +++ b/arch/arm/src/stm32u5/stm32_tim_lowerhalf.c @@ -41,28 +41,28 @@ #include "stm32_tim.h" #if defined(CONFIG_TIMER) && \ - (defined(CONFIG_STM32U5_TIM1) || defined(CONFIG_STM32U5_TIM2) || \ - defined(CONFIG_STM32U5_TIM3) || defined(CONFIG_STM32U5_TIM4) || \ - defined(CONFIG_STM32U5_TIM5) || defined(CONFIG_STM32U5_TIM6) || \ - defined(CONFIG_STM32U5_TIM7) || defined(CONFIG_STM32U5_TIM8) || \ - defined(CONFIG_STM32U5_TIM15) || defined(CONFIG_STM32U5_TIM16) || \ - defined(CONFIG_STM32U5_TIM17)) + (defined(CONFIG_STM32_TIM1) || defined(CONFIG_STM32_TIM2) || \ + defined(CONFIG_STM32_TIM3) || defined(CONFIG_STM32_TIM4) || \ + defined(CONFIG_STM32_TIM5) || defined(CONFIG_STM32_TIM6) || \ + defined(CONFIG_STM32_TIM7) || defined(CONFIG_STM32_TIM8) || \ + defined(CONFIG_STM32_TIM15) || defined(CONFIG_STM32_TIM16) || \ + defined(CONFIG_STM32_TIM17)) /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ -#define STM32U5_TIM1_RES 16 -#define STM32U5_TIM2_RES 32 -#define STM32U5_TIM3_RES 16 -#define STM32U5_TIM4_RES 16 -#define STM32U5_TIM5_RES 32 -#define STM32U5_TIM6_RES 16 -#define STM32U5_TIM7_RES 16 -#define STM32U5_TIM8_RES 16 -#define STM32U5_TIM15_RES 16 -#define STM32U5_TIM16_RES 16 -#define STM32U5_TIM17_RES 16 +#define STM32_TIM1_RES 16 +#define STM32_TIM2_RES 32 +#define STM32_TIM3_RES 16 +#define STM32_TIM4_RES 16 +#define STM32_TIM5_RES 32 +#define STM32_TIM6_RES 16 +#define STM32_TIM7_RES 16 +#define STM32_TIM8_RES 16 +#define STM32_TIM15_RES 16 +#define STM32_TIM16_RES 16 +#define STM32_TIM17_RES 16 /**************************************************************************** * Private Types @@ -118,91 +118,91 @@ static const struct timer_ops_s g_timer_ops = .ioctl = NULL, }; -#ifdef CONFIG_STM32U5_TIM1 +#ifdef CONFIG_STM32_TIM1 static struct stm32_lowerhalf_s g_tim1_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32U5_TIM1_RES, + .resolution = STM32_TIM1_RES, }; #endif -#ifdef CONFIG_STM32U5_TIM2 +#ifdef CONFIG_STM32_TIM2 static struct stm32_lowerhalf_s g_tim2_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32U5_TIM2_RES, + .resolution = STM32_TIM2_RES, }; #endif -#ifdef CONFIG_STM32U5_TIM3 +#ifdef CONFIG_STM32_TIM3 static struct stm32_lowerhalf_s g_tim3_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32U5_TIM3_RES, + .resolution = STM32_TIM3_RES, }; #endif -#ifdef CONFIG_STM32U5_TIM4 +#ifdef CONFIG_STM32_TIM4 static struct stm32_lowerhalf_s g_tim4_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32U5_TIM4_RES, + .resolution = STM32_TIM4_RES, }; #endif -#ifdef CONFIG_STM32U5_TIM5 +#ifdef CONFIG_STM32_TIM5 static struct stm32_lowerhalf_s g_tim5_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32U5_TIM5_RES, + .resolution = STM32_TIM5_RES, }; #endif -#ifdef CONFIG_STM32U5_TIM6 +#ifdef CONFIG_STM32_TIM6 static struct stm32_lowerhalf_s g_tim6_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32U5_TIM6_RES, + .resolution = STM32_TIM6_RES, }; #endif -#ifdef CONFIG_STM32U5_TIM7 +#ifdef CONFIG_STM32_TIM7 static struct stm32_lowerhalf_s g_tim7_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32U5_TIM7_RES, + .resolution = STM32_TIM7_RES, }; #endif -#ifdef CONFIG_STM32U5_TIM8 +#ifdef CONFIG_STM32_TIM8 static struct stm32_lowerhalf_s g_tim8_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32U5_TIM8_RES, + .resolution = STM32_TIM8_RES, }; #endif -#ifdef CONFIG_STM32U5_TIM15 +#ifdef CONFIG_STM32_TIM15 static struct stm32_lowerhalf_s g_tim15_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32U5_TIM15_RES, + .resolution = STM32_TIM15_RES, }; #endif -#ifdef CONFIG_STM32U5_TIM16 +#ifdef CONFIG_STM32_TIM16 static struct stm32_lowerhalf_s g_tim16_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32U5_TIM16_RES, + .resolution = STM32_TIM16_RES, }; #endif -#ifdef CONFIG_STM32U5_TIM17 +#ifdef CONFIG_STM32_TIM17 static struct stm32_lowerhalf_s g_tim17_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32U5_TIM17_RES, + .resolution = STM32_TIM17_RES, }; #endif @@ -228,13 +228,13 @@ static int stm32_timer_handler(int irq, void *context, void *arg) (struct stm32_lowerhalf_s *)arg; uint32_t next_interval_us = 0; - STM32U5_TIM_ACKINT(lower->tim, 0); + STM32_TIM_ACKINT(lower->tim, 0); if (lower->callback(&next_interval_us, lower->arg)) { if (next_interval_us > 0) { - STM32U5_TIM_SETPERIOD(lower->tim, next_interval_us); + STM32_TIM_SETPERIOD(lower->tim, next_interval_us); } } else @@ -267,12 +267,12 @@ static int stm32_start(struct timer_lowerhalf_s *lower) if (!priv->started) { - STM32U5_TIM_SETMODE(priv->tim, STM32U5_TIM_MODE_UP); + STM32_TIM_SETMODE(priv->tim, STM32_TIM_MODE_UP); if (priv->callback != NULL) { - STM32U5_TIM_SETISR(priv->tim, stm32_timer_handler, priv, 0); - STM32U5_TIM_ENABLEINT(priv->tim, 0); + STM32_TIM_SETISR(priv->tim, stm32_timer_handler, priv, 0); + STM32_TIM_ENABLEINT(priv->tim, 0); } priv->started = true; @@ -306,9 +306,9 @@ static int stm32_stop(struct timer_lowerhalf_s *lower) if (priv->started) { - STM32U5_TIM_SETMODE(priv->tim, STM32U5_TIM_MODE_DISABLED); - STM32U5_TIM_DISABLEINT(priv->tim, 0); - STM32U5_TIM_SETISR(priv->tim, NULL, NULL, 0); + STM32_TIM_SETMODE(priv->tim, STM32_TIM_MODE_DISABLED); + STM32_TIM_DISABLEINT(priv->tim, 0); + STM32_TIM_SETISR(priv->tim, NULL, NULL, 0); priv->started = false; return OK; } @@ -363,8 +363,8 @@ static int stm32_getstatus(struct timer_lowerhalf_s *lower, /* Get timeout */ maxtimeout = (1 << priv->resolution) - 1; - clock = STM32U5_TIM_GETCLOCK(priv->tim); - period = STM32U5_TIM_GETPERIOD(priv->tim); + clock = STM32_TIM_GETCLOCK(priv->tim); + period = STM32_TIM_GETPERIOD(priv->tim); if (clock == 1000000) { @@ -380,7 +380,7 @@ static int stm32_getstatus(struct timer_lowerhalf_s *lower, /* Get the time remaining until the timer expires (in microseconds) */ clock_factor = (clock == 1000000) ? 1 : (clock / 1000000); - status->timeleft = (timeout - STM32U5_TIM_GETCOUNTER(priv->tim)) * + status->timeleft = (timeout - STM32_TIM_GETCOUNTER(priv->tim)) * clock_factor; return OK; } @@ -417,13 +417,13 @@ static int stm32_settimeout(struct timer_lowerhalf_s *lower, if (timeout > maxtimeout) { uint64_t freq = (maxtimeout * 1000000) / timeout; - STM32U5_TIM_SETCLOCK(priv->tim, freq); - STM32U5_TIM_SETPERIOD(priv->tim, maxtimeout); + STM32_TIM_SETCLOCK(priv->tim, freq); + STM32_TIM_SETPERIOD(priv->tim, maxtimeout); } else { - STM32U5_TIM_SETCLOCK(priv->tim, 1000000); - STM32U5_TIM_SETPERIOD(priv->tim, timeout); + STM32_TIM_SETCLOCK(priv->tim, 1000000); + STM32_TIM_SETPERIOD(priv->tim, timeout); } return OK; @@ -463,13 +463,13 @@ static void stm32_setcallback(struct timer_lowerhalf_s *lower, if (callback != NULL && priv->started) { - STM32U5_TIM_SETISR(priv->tim, stm32_timer_handler, priv, 0); - STM32U5_TIM_ENABLEINT(priv->tim, 0); + STM32_TIM_SETISR(priv->tim, stm32_timer_handler, priv, 0); + STM32_TIM_ENABLEINT(priv->tim, 0); } else { - STM32U5_TIM_DISABLEINT(priv->tim, 0); - STM32U5_TIM_SETISR(priv->tim, NULL, NULL, 0); + STM32_TIM_DISABLEINT(priv->tim, 0); + STM32_TIM_SETISR(priv->tim, NULL, NULL, 0); } leave_critical_section(flags); @@ -503,66 +503,66 @@ int stm32_timer_initialize(const char *devpath, int timer) switch (timer) { -#ifdef CONFIG_STM32U5_TIM1 +#ifdef CONFIG_STM32_TIM1 case 1: lower = &g_tim1_lowerhalf; break; #endif -#ifdef CONFIG_STM32U5_TIM2 +#ifdef CONFIG_STM32_TIM2 case 2: lower = &g_tim2_lowerhalf; break; #endif -#ifdef CONFIG_STM32U5_TIM3 +#ifdef CONFIG_STM32_TIM3 case 3: lower = &g_tim3_lowerhalf; break; #endif -#ifdef CONFIG_STM32U5_TIM4 +#ifdef CONFIG_STM32_TIM4 case 4: lower = &g_tim4_lowerhalf; break; #endif -#ifdef CONFIG_STM32U5_TIM5 +#ifdef CONFIG_STM32_TIM5 case 5: lower = &g_tim5_lowerhalf; break; #endif -#ifdef CONFIG_STM32U5_TIM6 +#ifdef CONFIG_STM32_TIM6 case 6: lower = &g_tim6_lowerhalf; break; #endif -#ifdef CONFIG_STM32U5_TIM7 +#ifdef CONFIG_STM32_TIM7 case 7: lower = &g_tim7_lowerhalf; break; #endif -#ifdef CONFIG_STM32U5_TIM8 +#ifdef CONFIG_STM32_TIM8 case 8: lower = &g_tim8_lowerhalf; break; #endif -#ifdef CONFIG_STM32U5_TIM15 +#ifdef CONFIG_STM32_TIM15 case 15: lower = &g_tim15_lowerhalf; break; #endif -#ifdef CONFIG_STM32U5_TIM16 +#ifdef CONFIG_STM32_TIM16 case 16: lower = &g_tim16_lowerhalf; break; #endif -#ifdef CONFIG_STM32U5_TIM17 +#ifdef CONFIG_STM32_TIM17 case 17: lower = &g_tim17_lowerhalf; break; diff --git a/arch/arm/src/stm32u5/stm32_timerisr.c b/arch/arm/src/stm32u5/stm32_timerisr.c index 5cd2f7175dddf..3c6aee942223a 100644 --- a/arch/arm/src/stm32u5/stm32_timerisr.c +++ b/arch/arm/src/stm32u5/stm32_timerisr.c @@ -58,9 +58,9 @@ * And I don't know now to re-configure it yet */ -#undef CONFIG_STM32U5_SYSTICK_HCLKd8 +#undef CONFIG_STM32_SYSTICK_HCLKd8 -#ifdef CONFIG_STM32U5_SYSTICK_HCLKd8 +#ifdef CONFIG_STM32_SYSTICK_HCLKd8 # define SYSTICK_RELOAD ((STM32_HCLK_FREQUENCY / 8 / CLK_TCK) - 1) #else # define SYSTICK_RELOAD ((STM32_HCLK_FREQUENCY / CLK_TCK) - 1) @@ -123,7 +123,7 @@ void up_timer_initialize(void) #if 0 /* Does not work. Comes up with HCLK source and I can't change it */ regval = getreg32(NVIC_SYSTICK_CTRL); -#ifdef CONFIG_STM32U5_SYSTICK_HCLKd8 +#ifdef CONFIG_STM32_SYSTICK_HCLKd8 regval &= ~NVIC_SYSTICK_CTRL_CLKSOURCE; #else regval |= NVIC_SYSTICK_CTRL_CLKSOURCE; diff --git a/arch/arm/src/stm32u5/stm32_uart.h b/arch/arm/src/stm32u5/stm32_uart.h index 198ef1e36a050..0a06e0798d6ef 100644 --- a/arch/arm/src/stm32u5/stm32_uart.h +++ b/arch/arm/src/stm32u5/stm32_uart.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_STC_STM32U5_STM32_UART_H -#define __ARCH_ARM_STC_STM32U5_STM32_UART_H +#ifndef __ARCH_ARM_SRC_STM32U5_STM32_UART_H +#define __ARCH_ARM_SRC_STM32U5_STM32_UART_H /**************************************************************************** * Included Files @@ -32,7 +32,7 @@ #include "chip.h" -#if defined(CONFIG_STM32U5_STM32U585XX) || defined(CONFIG_STM32U5_STM32U5A5XX) +#if defined(CONFIG_STM32_STM32U585XX) || defined(CONFIG_STM32_STM32U5A5XX) # include "hardware/stm32_uart.h" #else # error "Unsupported STM32U5 chip" @@ -46,63 +46,63 @@ * device. */ -#if !defined(CONFIG_STM32U5_HAVE_UART5) -# undef CONFIG_STM32U5_UART5 +#if !defined(CONFIG_STM32_HAVE_UART5) +# undef CONFIG_STM32_UART5 #endif -#if !defined(CONFIG_STM32U5_HAVE_UART4) -# undef CONFIG_STM32U5_UART4 +#if !defined(CONFIG_STM32_HAVE_UART4) +# undef CONFIG_STM32_UART4 #endif -#if !defined(CONFIG_STM32U5_HAVE_USART3) -# undef CONFIG_STM32U5_USART3 +#if !defined(CONFIG_STM32_HAVE_USART3) +# undef CONFIG_STM32_USART3 #endif -#if !defined(CONFIG_STM32U5_HAVE_USART2) -# undef CONFIG_STM32U5_USART2 +#if !defined(CONFIG_STM32_HAVE_USART2) +# undef CONFIG_STM32_USART2 #endif -#if !defined(CONFIG_STM32U5_HAVE_USART1) -# undef CONFIG_STM32U5_USART1 +#if !defined(CONFIG_STM32_HAVE_USART1) +# undef CONFIG_STM32_USART1 #endif -#if !defined(CONFIG_STM32U5_HAVE_LPUART1) -# undef CONFIG_STM32U5_LPUART1 +#if !defined(CONFIG_STM32_HAVE_LPUART1) +# undef CONFIG_STM32_LPUART1 #endif /* Sanity checks */ -#if !defined(CONFIG_STM32U5_LPUART1) -# undef CONFIG_STM32U5_LPUART1_SERIALDRIVER -# undef CONFIG_STM32U5_LPUART1_1WIREDRIVER +#if !defined(CONFIG_STM32_LPUART1) +# undef CONFIG_STM32_LPUART1_SERIALDRIVER +# undef CONFIG_STM32_LPUART1_1WIREDRIVER #endif -#if !defined(CONFIG_STM32U5_USART1) -# undef CONFIG_STM32U5_USART1_SERIALDRIVER -# undef CONFIG_STM32U5_USART1_1WIREDRIVER +#if !defined(CONFIG_STM32_USART1) +# undef CONFIG_STM32_USART1_SERIALDRIVER +# undef CONFIG_STM32_USART1_1WIREDRIVER #endif -#if !defined(CONFIG_STM32U5_USART2) -# undef CONFIG_STM32U5_USART2_SERIALDRIVER -# undef CONFIG_STM32U5_USART2_1WIREDRIVER +#if !defined(CONFIG_STM32_USART2) +# undef CONFIG_STM32_USART2_SERIALDRIVER +# undef CONFIG_STM32_USART2_1WIREDRIVER #endif -#if !defined(CONFIG_STM32U5_USART3) -# undef CONFIG_STM32U5_USART3_SERIALDRIVER -# undef CONFIG_STM32U5_USART3_1WIREDRIVER +#if !defined(CONFIG_STM32_USART3) +# undef CONFIG_STM32_USART3_SERIALDRIVER +# undef CONFIG_STM32_USART3_1WIREDRIVER #endif -#if !defined(CONFIG_STM32U5_UART4) -# undef CONFIG_STM32U5_UART4_SERIALDRIVER -# undef CONFIG_STM32U5_UART4_1WIREDRIVER +#if !defined(CONFIG_STM32_UART4) +# undef CONFIG_STM32_UART4_SERIALDRIVER +# undef CONFIG_STM32_UART4_1WIREDRIVER #endif -#if !defined(CONFIG_STM32U5_UART5) -# undef CONFIG_STM32U5_UART5_SERIALDRIVER -# undef CONFIG_STM32U5_UART5_1WIREDRIVER +#if !defined(CONFIG_STM32_UART5) +# undef CONFIG_STM32_UART5_SERIALDRIVER +# undef CONFIG_STM32_UART5_1WIREDRIVER #endif /* Is there a USART enabled? */ -#if defined(CONFIG_STM32U5_LPUART1) || defined(CONFIG_STM32U5_USART1) || \ - defined(CONFIG_STM32U5_USART2) || defined(CONFIG_STM32U5_USART3) || \ - defined(CONFIG_STM32U5_UART4) || defined(CONFIG_STM32U5_UART5) +#if defined(CONFIG_STM32_LPUART1) || defined(CONFIG_STM32_USART1) || \ + defined(CONFIG_STM32_USART2) || defined(CONFIG_STM32_USART3) || \ + defined(CONFIG_STM32_UART4) || defined(CONFIG_STM32_UART5) # define HAVE_UART 1 #endif /* Is there a serial console? */ -#if defined(CONFIG_LPUART1_SERIAL_CONSOLE) && defined(CONFIG_STM32U5_LPUART1_SERIALDRIVER) +#if defined(CONFIG_LPUART1_SERIAL_CONSOLE) && defined(CONFIG_STM32_LPUART1_SERIALDRIVER) # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE @@ -110,7 +110,7 @@ # undef CONFIG_UART5_SERIAL_CONSOLE # define CONSOLE_UART 1 # define HAVE_CONSOLE 1 -#elif defined(CONFIG_USART1_SERIAL_CONSOLE) && defined(CONFIG_STM32U5_USART1_SERIALDRIVER) +#elif defined(CONFIG_USART1_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART1_SERIALDRIVER) # undef CONFIG_LPUART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE @@ -118,28 +118,28 @@ # undef CONFIG_UART5_SERIAL_CONSOLE # define CONSOLE_UART 2 # define HAVE_CONSOLE 1 -#elif defined(CONFIG_USART2_SERIAL_CONSOLE) && defined(CONFIG_STM32U5_USART2_SERIALDRIVER) +#elif defined(CONFIG_USART2_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART2_SERIALDRIVER) # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE # undef CONFIG_UART4_SERIAL_CONSOLE # undef CONFIG_UART5_SERIAL_CONSOLE # define CONSOLE_UART 3 # define HAVE_CONSOLE 1 -#elif defined(CONFIG_USART3_SERIAL_CONSOLE) && defined(CONFIG_STM32U5_USART3_SERIALDRIVER) +#elif defined(CONFIG_USART3_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART3_SERIALDRIVER) # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # undef CONFIG_UART4_SERIAL_CONSOLE # undef CONFIG_UART5_SERIAL_CONSOLE # define CONSOLE_UART 4 # define HAVE_CONSOLE 1 -#elif defined(CONFIG_UART4_SERIAL_CONSOLE) && defined(CONFIG_STM32U5_UART4_SERIALDRIVER) +#elif defined(CONFIG_UART4_SERIAL_CONSOLE) && defined(CONFIG_STM32_UART4_SERIALDRIVER) # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE # undef CONFIG_UART5_SERIAL_CONSOLE # define CONSOLE_UART 5 # define HAVE_CONSOLE 1 -#elif defined(CONFIG_UART5_SERIAL_CONSOLE) && defined(CONFIG_STM32U5_UART5_SERIALDRIVER) +#elif defined(CONFIG_UART5_SERIAL_CONSOLE) && defined(CONFIG_STM32_UART5_SERIALDRIVER) # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE @@ -170,27 +170,27 @@ /* Disable the DMA configuration on all unused USARTs */ -#ifndef CONFIG_STM32U5_LPUART1_SERIALDRIVER +#ifndef CONFIG_STM32_LPUART1_SERIALDRIVER # undef CONFIG_LPUART1_RXDMA #endif -#ifndef CONFIG_STM32U5_USART1_SERIALDRIVER +#ifndef CONFIG_STM32_USART1_SERIALDRIVER # undef CONFIG_USART1_RXDMA #endif -#ifndef CONFIG_STM32U5_USART2_SERIALDRIVER +#ifndef CONFIG_STM32_USART2_SERIALDRIVER # undef CONFIG_USART2_RXDMA #endif -#ifndef CONFIG_STM32U5_USART3_SERIALDRIVER +#ifndef CONFIG_STM32_USART3_SERIALDRIVER # undef CONFIG_USART3_RXDMA #endif -#ifndef CONFIG_STM32U5_UART4_SERIALDRIVER +#ifndef CONFIG_STM32_UART4_SERIALDRIVER # undef CONFIG_UART4_RXDMA #endif -#ifndef CONFIG_STM32U5_UART5_SERIALDRIVER +#ifndef CONFIG_STM32_UART5_SERIALDRIVER # undef CONFIG_UART5_RXDMA #endif @@ -223,17 +223,17 @@ /* Is DMA used on all (enabled) USARTs */ #define SERIAL_HAVE_ONLY_DMA 1 -#if defined(CONFIG_STM32U5_LPUART1_SERIALDRIVER) && !defined(CONFIG_LPUART1_RXDMA) +#if defined(CONFIG_STM32_LPUART1_SERIALDRIVER) && !defined(CONFIG_LPUART1_RXDMA) # undef SERIAL_HAVE_ONLY_DMA -#elif defined(CONFIG_STM32U5_USART1_SERIALDRIVER) && !defined(CONFIG_USART1_RXDMA) +#elif defined(CONFIG_STM32_USART1_SERIALDRIVER) && !defined(CONFIG_USART1_RXDMA) # undef SERIAL_HAVE_ONLY_DMA -#elif defined(CONFIG_STM32U5_USART2_SERIALDRIVER) && !defined(CONFIG_USART2_RXDMA) +#elif defined(CONFIG_STM32_USART2_SERIALDRIVER) && !defined(CONFIG_USART2_RXDMA) # undef SERIAL_HAVE_ONLY_DMA -#elif defined(CONFIG_STM32U5_USART3_SERIALDRIVER) && !defined(CONFIG_USART3_RXDMA) +#elif defined(CONFIG_STM32_USART3_SERIALDRIVER) && !defined(CONFIG_USART3_RXDMA) # undef SERIAL_HAVE_ONLY_DMA -#elif defined(CONFIG_STM32U5_UART4_SERIALDRIVER) && !defined(CONFIG_UART4_RXDMA) +#elif defined(CONFIG_STM32_UART4_SERIALDRIVER) && !defined(CONFIG_UART4_RXDMA) # undef SERIAL_HAVE_ONLY_DMA -#elif defined(CONFIG_STM32U5_UART5_SERIALDRIVER) && !defined(CONFIG_UART5_RXDMA) +#elif defined(CONFIG_STM32_UART5_SERIALDRIVER) && !defined(CONFIG_UART5_RXDMA) # undef SERIAL_HAVE_ONLY_DMA #endif @@ -297,4 +297,4 @@ void stm32_serial_dma_poll(void); #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_STC_STM32U5_STM32_UART_H */ +#endif /* __ARCH_ARM_SRC_STM32U5_STM32_UART_H */ diff --git a/arch/arm/src/stm32u5/stm32_uid.c b/arch/arm/src/stm32u5/stm32_uid.c deleted file mode 100644 index 55b3aa8e82a53..0000000000000 --- a/arch/arm/src/stm32u5/stm32_uid.c +++ /dev/null @@ -1,48 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32u5/stm32_uid.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "hardware/stm32_memorymap.h" -#include "stm32_uid.h" - -#ifdef STM32U5_SYSMEM_UID - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -void stm32_get_uniqueid(uint8_t uniqueid[12]) -{ - int i; - - for (i = 0; i < 12; i++) - { - uniqueid[i] = *((uint8_t *)(STM32U5_SYSMEM_UID) + i); - } -} - -#endif /* STM32U5_SYSMEM_UID */ diff --git a/arch/arm/src/stm32u5/stm32_uid.h b/arch/arm/src/stm32u5/stm32_uid.h deleted file mode 100644 index f306f2759a98a..0000000000000 --- a/arch/arm/src/stm32u5/stm32_uid.h +++ /dev/null @@ -1,38 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32u5/stm32_uid.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32U5_STM32_UID_H -#define __ARCH_ARM_SRC_STM32U5_STM32_UID_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -void stm32_get_uniqueid(uint8_t uniqueid[12]); - -#endif /* __ARCH_ARM_SRC_STM32U5_STM32_UID_H */ diff --git a/arch/arm/src/stm32u5/stm32_waste.c b/arch/arm/src/stm32u5/stm32_waste.c deleted file mode 100644 index da56c6755eec1..0000000000000 --- a/arch/arm/src/stm32u5/stm32_waste.c +++ /dev/null @@ -1,44 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32u5/stm32_waste.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include -#include "stm32_waste.h" - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -uint32_t idle_wastecounter = 0; - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -void stm32_waste(void) -{ - idle_wastecounter++; -} diff --git a/arch/arm/src/stm32u5/stm32_waste.h b/arch/arm/src/stm32u5/stm32_waste.h deleted file mode 100644 index ab5a5c8a89bc8..0000000000000 --- a/arch/arm/src/stm32u5/stm32_waste.h +++ /dev/null @@ -1,66 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32u5/stm32_waste.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32U5_STM32_WASTE_H -#define __ARCH_ARM_SRC_STM32U5_STM32_WASTE_H - -/* Waste CPU Time */ - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#ifndef __ASSEMBLY__ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/* Waste CPU Time - * - * stm32_waste() is the logic that will be executed when portions of kernel - * or user-app is polling some register or similar, waiting for desired - * status. This time is wasted away. This function offers a measure of badly - * written piece of software or some undesired behavior. - * - * At the same time this function adds to some IDLE time which portion - * cannot be used for other purposes (yet). - */ - -void stm32_waste(void); - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32U5_STM32_WASTE_H */ diff --git a/arch/arm/src/stm32u5/stm32u5xx_rcc.c b/arch/arm/src/stm32u5/stm32u5xx_rcc.c index 3fb5798bd7fca..b9017ae455ad1 100644 --- a/arch/arm/src/stm32u5/stm32u5xx_rcc.c +++ b/arch/arm/src/stm32u5/stm32u5xx_rcc.c @@ -60,7 +60,7 @@ static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1, /* Determine if board wants to use HSI48 as 48 MHz oscillator. */ -#if defined(CONFIG_STM32U5_HAVE_HSI48) && defined(STM32_USE_CLK48) +#if defined(CONFIG_STM32_HAVE_HSI48) && defined(STM32_USE_CLK48) # if STM32_CLK48_SEL == RCC_CCIPR_CLK48SEL_HSI48 # define STM32_USE_HSI48 # endif @@ -92,55 +92,55 @@ static inline void rcc_enableahb1(void) regval = getreg32(STM32_RCC_AHB1ENR); -#ifdef CONFIG_STM32U5_GPDMA1 +#ifdef CONFIG_STM32_GPDMA1 regval |= RCC_AHB1ENR_GPDMA1EN; #endif -#ifdef CONFIG_STM32U5_CORDIC +#ifdef CONFIG_STM32_CORDIC regval |= RCC_AHB1ENR_CORDIC; #endif -#ifdef CONFIG_STM32U5_FMAC +#ifdef CONFIG_STM32_FMAC regval |= RCC_AHB1ENR_FMACEN; #endif -#ifdef CONFIG_STM32U5_MDF1 +#ifdef CONFIG_STM32_MDF1 regval |= RCC_AHB1ENR_MDF1EN; #endif -#ifdef CONFIG_STM32U5_FLASH +#ifdef CONFIG_STM32_FLASH regval |= RCC_AHB1ENR_FLASHEN; #endif -#ifdef CONFIG_STM32U5_CRC +#ifdef CONFIG_STM32_CRC regval |= RCC_AHB1ENR_CRCEN; #endif -#ifdef CONFIG_STM32U5_TSC +#ifdef CONFIG_STM32_TSC regval |= RCC_AHB1ENR_TSCEN; #endif -#ifdef CONFIG_STM32U5_RAMCFG +#ifdef CONFIG_STM32_RAMCFG regval |= RCC_AHB1ENR_RAMCFGEN; #endif -#ifdef CONFIG_STM32U5_DMA2D +#ifdef CONFIG_STM32_DMA2D regval |= RCC_AHB1ENR_DMA2DEN; #endif -#ifdef CONFIG_STM32U5_GTZC1 +#ifdef CONFIG_STM32_GTZC1 regval |= RCC_AHB1ENR_GTZC1EN; #endif -#ifdef CONFIG_STM32U5_BKPSRAM +#ifdef CONFIG_STM32_BKPSRAM regval |= RCC_AHB1ENR_BKPSRAMEN; #endif -#ifdef CONFIG_STM32U5_DCACHE1 +#ifdef CONFIG_STM32_DCACHE1 regval |= RCC_AHB1ENR_DCACHE1EN; #endif -#ifdef CONFIG_STM32U5_SRAM1 +#ifdef CONFIG_STM32_SRAM1 regval |= RCC_AHB1ENR_SRAM1EN; #endif @@ -194,67 +194,67 @@ static inline void rcc_enableahb2(void) ); #endif -#if defined(CONFIG_STM32U5_ADC1) +#if defined(CONFIG_STM32_ADC1) regval |= RCC_AHB2ENR1_ADC1EN; #endif -#if defined(CONFIG_STM32U5_DCMI_PSSI) +#if defined(CONFIG_STM32_DCMI_PSSI) regval |= RCC_AHB2ENR1_DCMI_PSSIEN; #endif -#ifdef CONFIG_STM32U5_OTGHS +#ifdef CONFIG_STM32_OTGHS regval |= RCC_AHB2ENR1_OTGEN; #endif -#ifdef CONFIG_STM32U5_OTGHS +#ifdef CONFIG_STM32_OTGHS regval |= RCC_AHB2ENR1_OTGPHYEN; #endif -#ifdef CONFIG_STM32U5_AES +#ifdef CONFIG_STM32_AES regval |= RCC_AHB2ENR1_AESEN; #endif -#ifdef CONFIG_STM32U5_HASH +#ifdef CONFIG_STM32_HASH regval |= RCC_AHB2ENR1_HASHEN #endif -#ifdef CONFIG_STM32U5_RNG +#ifdef CONFIG_STM32_RNG regval |= RCC_AHB2ENR1_RNGEN; #endif -#ifdef CONFIG_STM32U5_PKA +#ifdef CONFIG_STM32_PKA regval |= RCC_AHB2ENR_PKAEN; #endif -#ifdef CONFIG_STM32U5_SAES +#ifdef CONFIG_STM32_SAES regval |= RCC_AHB2ENR1_SAES; #endif -#ifdef CONFIG_STM32U5_OCTOSPIM +#ifdef CONFIG_STM32_OCTOSPIM regval |= RCC_AHB2ENR1_OCTOSPIM; #endif -#ifdef CONFIG_STM32U5_OTFDEC1 +#ifdef CONFIG_STM32_OTFDEC1 regval |= RCC_AHB2ENR1_OTFDEC1; #endif -#ifdef CONFIG_STM32U5_OTFDEC2 +#ifdef CONFIG_STM32_OTFDEC2 regval |= RCC_AHB2ENR1_OTFDEC2; #endif -#ifdef CONFIG_STM32U5_SDMMC1EN +#ifdef CONFIG_STM32_SDMMC1EN regval |= RCC_AHB2ENR1_SDMMC1EN; #endif -#ifdef CONFIG_STM32U5_SDMMC2EN +#ifdef CONFIG_STM32_SDMMC2EN regval |= RCC_AHB2ENR1_SDMMC2EN; #endif -#ifdef CONFIG_STM32U5_SRAM2 +#ifdef CONFIG_STM32_SRAM2 regval |= RCC_AHB2ENR1_SRAM2EN; #endif -#ifdef CONFIG_STM32U5_SRAM3 +#ifdef CONFIG_STM32_SRAM3 regval |= RCC_AHB2ENR1_SRAM3EN; #endif @@ -262,19 +262,19 @@ static inline void rcc_enableahb2(void) regval = getreg32(STM32_RCC_AHB2ENR2); -#ifdef CONFIG_STM32U5_FSMC +#ifdef CONFIG_STM32_FSMC regval |= RCC_AHB2ENR2_FSMCEN; #endif -#ifdef CONFIG_STM32U5_OCTOSPI1 +#ifdef CONFIG_STM32_OCTOSPI1 regval |= RCC_AHB2ENR2_OCTOSPI1EN; #endif -#ifdef CONFIG_STM32U5_OCTOSPI2 +#ifdef CONFIG_STM32_OCTOSPI2 regval |= RCC_AHB2ENR2_OCTOSPI2EN; #endif -#ifdef CONFIG_STM32U5_SRAM5 +#ifdef CONFIG_STM32_SRAM5 regval |= RCC_AHB2ENR2_SRAM5EN; #endif @@ -299,35 +299,35 @@ static inline void rcc_enableahb3(void) regval = getreg32(STM32_RCC_AHB3ENR); -#ifdef CONFIG_STM32U5_LPGPIO1 +#ifdef CONFIG_STM32_LPGPIO1 regval |= RCC_AHB3ENR_LPGPIO1EN; #endif -#ifdef CONFIG_STM32U5_PWR +#ifdef CONFIG_STM32_PWR regval |= RCC_AHB3ENR_PWREN; #endif -#ifdef CONFIG_STM32U5_ADC4 +#ifdef CONFIG_STM32_ADC4 regval |= RCC_AHB3ENR_ADC4EN; #endif -#ifdef CONFIG_STM32U5_DAC1 +#ifdef CONFIG_STM32_DAC1 regval |= RCC_AHB3ENR_DAC1EN; #endif -#ifdef CONFIG_STM32U5_LPDMA1 +#ifdef CONFIG_STM32_LPDMA1 regval |= RCC_AHB3ENR_LPDMA1EN; #endif -#ifdef CONFIG_STM32U5_ADF1 +#ifdef CONFIG_STM32_ADF1 regval |= RCC_AHB3ENR_ADF1EN; #endif -#ifdef CONFIG_STM32U5_GTZC2 +#ifdef CONFIG_STM32_GTZC2 regval |= RCC_AHB3ENR_GTZC2EN; #endif -#ifdef CONFIG_STM32U5_SRAM4 +#ifdef CONFIG_STM32_SRAM4 regval |= RCC_AHB3ENR_SRAM4EN; #endif @@ -352,63 +352,63 @@ static inline void rcc_enableapb1(void) regval = getreg32(STM32_RCC_APB1ENR1); -#ifdef CONFIG_STM32U5_TIM2 +#ifdef CONFIG_STM32_TIM2 regval |= RCC_APB1ENR1_TIM2EN; #endif -#ifdef CONFIG_STM32U5_TIM3 +#ifdef CONFIG_STM32_TIM3 regval |= RCC_APB1ENR1_TIM3EN; #endif -#ifdef CONFIG_STM32U5_TIM4 +#ifdef CONFIG_STM32_TIM4 regval |= RCC_APB1ENR1_TIM4EN; #endif -#ifdef CONFIG_STM32U5_TIM5 +#ifdef CONFIG_STM32_TIM5 regval |= RCC_APB1ENR1_TIM5EN; #endif -#ifdef CONFIG_STM32U5_TIM6 +#ifdef CONFIG_STM32_TIM6 regval |= RCC_APB1ENR1_TIM6EN; #endif -#ifdef CONFIG_STM32U5_TIM7 +#ifdef CONFIG_STM32_TIM7 regval |= RCC_APB1ENR1_TIM7EN; #endif -#ifdef CONFIG_STM32U5_WWDG +#ifdef CONFIG_STM32_WWDG regval |= RCC_APB1ENR1_WWDGEN; #endif -#ifdef CONFIG_STM32U5_SPI2 +#ifdef CONFIG_STM32_SPI2 regval |= RCC_APB1ENR1_SPI2EN; #endif -#ifdef CONFIG_STM32U5_USART2 +#ifdef CONFIG_STM32_USART2 regval |= RCC_APB1ENR1_USART2EN; #endif -#ifdef CONFIG_STM32U5_USART3 +#ifdef CONFIG_STM32_USART3 regval |= RCC_APB1ENR1_USART3EN; #endif -#ifdef CONFIG_STM32U5_UART4 +#ifdef CONFIG_STM32_UART4 regval |= RCC_APB1ENR1_UART4EN; #endif -#ifdef CONFIG_STM32U5_UART5 +#ifdef CONFIG_STM32_UART5 regval |= RCC_APB1ENR1_UART5EN; #endif -#ifdef CONFIG_STM32U5_I2C1 +#ifdef CONFIG_STM32_I2C1 regval |= RCC_APB1ENR1_I2C1EN; #endif -#ifdef CONFIG_STM32U5_I2C2 +#ifdef CONFIG_STM32_I2C2 regval |= RCC_APB1ENR1_I2C2EN; #endif -#ifdef CONFIG_STM32U5_CRS +#ifdef CONFIG_STM32_CRS regval |= RCC_APB1ENR1_CRSEN; #endif @@ -418,19 +418,19 @@ static inline void rcc_enableapb1(void) regval = getreg32(STM32_RCC_APB1ENR2); -#ifdef CONFIG_STM32U5_I2C4 +#ifdef CONFIG_STM32_I2C4 regval |= RCC_APB1ENR2_I2C4EN; #endif -#ifdef CONFIG_STM32U5_LPTIM2 +#ifdef CONFIG_STM32_LPTIM2 regval |= RCC_APB1ENR2_LPTIM2EN; #endif -#ifdef CONFIG_STM32U5_FDCAN1 +#ifdef CONFIG_STM32_FDCAN1 regval |= RCC_APB1ENR2_FDCAN1EN; #endif -#ifdef CONFIG_STM32U5_UCPD1 +#ifdef CONFIG_STM32_UCPD1 regval |= RCC_APB1ENR2_UCPD1EN; #endif @@ -455,39 +455,39 @@ static inline void rcc_enableapb2(void) regval = getreg32(STM32_RCC_APB2ENR); -#ifdef CONFIG_STM32U5_TIM1 +#ifdef CONFIG_STM32_TIM1 regval |= RCC_APB2ENR_TIM1EN; #endif -#ifdef CONFIG_STM32U5_SPI1 +#ifdef CONFIG_STM32_SPI1 regval |= RCC_APB2ENR_SPI1EN; #endif -#ifdef CONFIG_STM32U5_TIM8 +#ifdef CONFIG_STM32_TIM8 regval |= RCC_APB2ENR_TIM8EN; #endif -#ifdef CONFIG_STM32U5_USART1 +#ifdef CONFIG_STM32_USART1 regval |= RCC_APB2ENR_USART1EN; #endif -#ifdef CONFIG_STM32U5_TIM15 +#ifdef CONFIG_STM32_TIM15 regval |= RCC_APB2ENR_TIM15EN; #endif -#ifdef CONFIG_STM32U5_TIM16 +#ifdef CONFIG_STM32_TIM16 regval |= RCC_APB2ENR_TIM16EN; #endif -#ifdef CONFIG_STM32U5_TIM17 +#ifdef CONFIG_STM32_TIM17 regval |= RCC_APB2ENR_TIM17EN; #endif -#ifdef CONFIG_STM32U5_SAI1 +#ifdef CONFIG_STM32_SAI1 regval |= RCC_APB2ENR_SAI1EN; #endif -#ifdef CONFIG_STM32U5_SAI2 +#ifdef CONFIG_STM32_SAI2 regval |= RCC_APB2ENR_SAI2EN; #endif @@ -512,47 +512,47 @@ static inline void rcc_enableapb3(void) regval = getreg32(STM32_RCC_APB3ENR); -#ifdef CONFIG_STM32U5_SYSCFG +#ifdef CONFIG_STM32_SYSCFG regval |= RCC_APB3ENR_SYSCFGEN; #endif -#ifdef CONFIG_STM32U5_SPI3 +#ifdef CONFIG_STM32_SPI3 regval |= RCC_APB3ENR_SPI3EN; #endif -#ifdef CONFIG_STM32U5_LPUART1 +#ifdef CONFIG_STM32_LPUART1 regval |= RCC_APB3ENR_LPUART1EN; #endif -#ifdef CONFIG_STM32U5_I2C3EN +#ifdef CONFIG_STM32_I2C3EN regval |= RCC_APB3ENR_I2C3EN; #endif -#ifdef CONFIG_STM32U5_LPTIM1 +#ifdef CONFIG_STM32_LPTIM1 regval |= RCC_APB3ENR_LPTIM1EN; #endif -#ifdef CONFIG_STM32U5_LPTIM3 +#ifdef CONFIG_STM32_LPTIM3 regval |= RCC_APB3ENR_LPTIM3EN; #endif -#ifdef CONFIG_STM32U5_LPTIM4 +#ifdef CONFIG_STM32_LPTIM4 regval |= RCC_APB3ENR_LPTIM4EN; #endif -#ifdef CONFIG_STM32U5_OPAMP +#ifdef CONFIG_STM32_OPAMP regval |= RCC_APB3ENR_OPAMPEN; #endif -#ifdef CONFIG_STM32U5_COMP +#ifdef CONFIG_STM32_COMP regval |= RCC_APB3ENR_COMPEN; #endif -#ifdef CONFIG_STM32U5_VREF +#ifdef CONFIG_STM32_VREF regval |= RCC_APB3ENR_VREFEN; #endif -#ifdef CONFIG_STM32U5_RTCAPB +#ifdef CONFIG_STM32_RTCAPB regval |= RCC_APB3ENR_RTCAPBEN; #endif @@ -604,7 +604,7 @@ void stm32_rcc_enableperipherals(void) * power clocking modes! ****************************************************************************/ -#ifndef CONFIG_ARCH_BOARD_STM32U5_CUSTOM_CLOCKCONFIG +#ifndef CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG void stm32_stdclockconfig(void) { uint32_t regval; @@ -742,9 +742,9 @@ void stm32_stdclockconfig(void) regval |= STM32_RCC_CFGR3_PPRE3; putreg32(regval, STM32_RCC_CFGR3); -#ifdef CONFIG_STM32U5_RTC_HSECLOCK +#ifdef CONFIG_STM32_RTC_HSECLOCK -# error stm32_stdclockconfig() currently doesn not support CONFIG_STM32U5_RTC_HSECLOCK +# error stm32_stdclockconfig() currently doesn not support CONFIG_STM32_RTC_HSECLOCK #endif @@ -799,7 +799,7 @@ void stm32_stdclockconfig(void) { } -#if defined(CONFIG_STM32U5_IWDG) || defined(CONFIG_STM32U5_RTC_LSICLOCK) +#if defined(CONFIG_STM32_IWDG) || defined(CONFIG_STM32_RTC_LSICLOCK) /* Low speed internal clock source LSI */ stm32_rcc_enablelsi(); diff --git a/arch/arm/src/stm32wb/CMakeLists.txt b/arch/arm/src/stm32wb/CMakeLists.txt index 79f82cf8573c4..03f9157eed58e 100644 --- a/arch/arm/src/stm32wb/CMakeLists.txt +++ b/arch/arm/src/stm32wb/CMakeLists.txt @@ -33,13 +33,11 @@ set(SRCS stm32wb_serial.c stm32wb_i2c.c stm32wb_start.c - stm32wb_waste.c stm32wb_rcc_lse.c stm32wb_rcc_lsi.c stm32wb_pwr.c stm32wb_tim.c - stm32wb_flash.c - stm32wb_uid.c) + stm32wb_flash.c) if(NOT CONFIG_ARCH_IDLE_CUSTOM) list(APPEND SRCS stm32wb_idle.c) @@ -55,11 +53,11 @@ else() list(APPEND SRCS stm32wb_tickless.c) endif() -if(CONFIG_STM32WB_ONESHOT) +if(CONFIG_STM32_ONESHOT) list(APPEND SRCS stm32wb_oneshot.c stm32wb_oneshot_lowerhalf.c) endif() -if(CONFIG_STM32WB_FREERUN) +if(CONFIG_STM32_FREERUN) list(APPEND SRCS stm32wb_freerun.c) endif() @@ -67,11 +65,11 @@ if(CONFIG_BUILD_PROTECTED) list(APPEND SRCS stm32wb_userspace.c stm32wb_mpuinit.c) endif() -if(CONFIG_STM32WB_HAVE_HSI48) +if(CONFIG_STM32_HAVE_HSI48) list(APPEND SRCS stm32wb_rcc_hsi48.c) endif() -if(CONFIG_STM32WB_DMA) +if(CONFIG_STM32_DMA) list(APPEND SRCS stm32wb_dma.c) endif() @@ -84,11 +82,11 @@ if(CONFIG_PM) endif() endif() -if(CONFIG_STM32WB_PWR) +if(CONFIG_STM32_PWR) list(APPEND SRCS stm32wb_exti_pwr.c) endif() -if(CONFIG_STM32WB_RTC) +if(CONFIG_STM32_RTC) if(CONFIG_RTC_ALARM) list(APPEND SRCS stm32wb_exti_alarm.c) endif() @@ -100,15 +98,15 @@ if(CONFIG_STM32WB_RTC) endif() endif() -if(CONFIG_STM32WB_IPCC) +if(CONFIG_STM32_IPCC) list(APPEND SRCS stm32wb_ipcc.c) endif() -if(CONFIG_STM32WB_MBOX) +if(CONFIG_STM32_MBOX) list(APPEND SRCS stm32wb_mbox.c) endif() -if(CONFIG_STM32WB_BLE) +if(CONFIG_STM32_BLE) list(APPEND SRCS stm32wb_blehci.c) endif() @@ -117,3 +115,5 @@ if(CONFIG_DEBUG_FEATURES) endif() target_sources(arch PRIVATE ${SRCS}) + +add_subdirectory(${NUTTX_DIR}/arch/arm/src/common/stm32 stm32_common) diff --git a/arch/arm/src/stm32wb/Kconfig b/arch/arm/src/stm32wb/Kconfig index aba177dfed921..107f025ac2dfa 100644 --- a/arch/arm/src/stm32wb/Kconfig +++ b/arch/arm/src/stm32wb/Kconfig @@ -7,6 +7,22 @@ if ARCH_CHIP_STM32WB comment "STM32WB Configuration Options" +config STM32_WB_PERIPHERALS + bool + default ARCH_CHIP_STM32WB + select STM32_HAVE_BLE + select STM32_HAVE_DMA1 + select STM32_HAVE_MBOX + select STM32_HAVE_SRAM2A + select STM32_HAVE_SRAM2B + select STM32_HAVE_I2C1 + select STM32_HAVE_LPTIM1 + select STM32_HAVE_LPUART1 if STM32_HAVE_LPUART + select STM32_HAVE_RTC_SUBSECONDS + select STM32_HAVE_SPI1 + select STM32_HAVE_SYSCFG + select STM32_HAVE_USART1 + choice prompt "STM32 WB Chip Selection" default ARCH_CHIP_STM32WB55RG @@ -14,129 +30,129 @@ choice config ARCH_CHIP_STM32WB10CC bool "STM32WB10CC" - select STM32WB_STM32WB10 + select STM32_STM32WB10 select STM32WB_IO_CONFIG_C - select STM32WB_FLASH_CONFIG_C_320 + select STM32_FLASH_CONFIG_C_320 ---help--- STM32 WB Cortex M4, 320 Kb FLASH, 12+32+4 Kb SRAM config ARCH_CHIP_STM32WB15CC bool "STM32WB15CC" - select STM32WB_STM32WB15 + select STM32_STM32WB15 select STM32WB_IO_CONFIG_C - select STM32WB_FLASH_CONFIG_C_320 + select STM32_FLASH_CONFIG_C_320 ---help--- STM32 WB Cortex M4, 320 Kb FLASH, 12+32+4 Kb SRAM config ARCH_CHIP_STM32WB30CE bool "STM32WB30CE" - select STM32WB_STM32WB30 + select STM32_STM32WB30 select STM32WB_IO_CONFIG_C - select STM32WB_FLASH_CONFIG_E_512 + select STM32_FLASH_CONFIG_E ---help--- STM32 WB Cortex M4, 512 Kb FLASH, 32+32+32 Kb SRAM config ARCH_CHIP_STM32WB50CG bool "STM32WB50CG" - select STM32WB_STM32WB50 + select STM32_STM32WB50 select STM32WB_IO_CONFIG_C - select STM32WB_FLASH_CONFIG_G_1024 + select STM32_FLASH_CONFIG_G ---help--- STM32 WB Cortex M4, 1024 Kb FLASH, 64+32+32 Kb SRAM config ARCH_CHIP_STM32WB35CC bool "STM32WB35CC" - select STM32WB_STM32WB35 + select STM32_STM32WB35 select STM32WB_IO_CONFIG_C - select STM32WB_FLASH_CONFIG_C_256 + select STM32_FLASH_CONFIG_C ---help--- STM32 WB Cortex M4, 256 Kb FLASH, 32+32+32 Kb SRAM config ARCH_CHIP_STM32WB35CE bool "STM32WB35CE" - select STM32WB_STM32WB35 + select STM32_STM32WB35 select STM32WB_IO_CONFIG_C - select STM32WB_FLASH_CONFIG_E_512 + select STM32_FLASH_CONFIG_E ---help--- STM32 WB Cortex M4, 512 Kb FLASH, 32+32+32 Kb SRAM config ARCH_CHIP_STM32WB55CC bool "STM32WB55CC" - select STM32WB_STM32WB55 + select STM32_STM32WB55 select STM32WB_IO_CONFIG_C - select STM32WB_FLASH_CONFIG_C_256 + select STM32_FLASH_CONFIG_C ---help--- STM32 WB Cortex M4, 256 Kb FLASH, 64+32+32 Kb SRAM config ARCH_CHIP_STM32WB55RC bool "STM32WB55RC" - select STM32WB_STM32WB55 + select STM32_STM32WB55 select STM32WB_IO_CONFIG_R - select STM32WB_FLASH_CONFIG_C_256 + select STM32_FLASH_CONFIG_C ---help--- STM32 WB Cortex M4, 256 Kb FLASH, 64+32+32 Kb SRAM config ARCH_CHIP_STM32WB55VC bool "STM32WB55VC" - select STM32WB_STM32WB55 + select STM32_STM32WB55 select STM32WB_IO_CONFIG_V - select STM32WB_FLASH_CONFIG_C_256 + select STM32_FLASH_CONFIG_C ---help--- STM32 WB Cortex M4, 256 Kb FLASH, 64+32+32 Kb SRAM config ARCH_CHIP_STM32WB55CE bool "STM32WB55CE" - select STM32WB_STM32WB55 + select STM32_STM32WB55 select STM32WB_IO_CONFIG_C - select STM32WB_FLASH_CONFIG_E_512 + select STM32_FLASH_CONFIG_E ---help--- STM32 WB Cortex M4, 512 Kb FLASH, 192+32+32 Kb SRAM config ARCH_CHIP_STM32WB55RE bool "STM32WB55RE" - select STM32WB_STM32WB55 + select STM32_STM32WB55 select STM32WB_IO_CONFIG_R - select STM32WB_FLASH_CONFIG_E_512 + select STM32_FLASH_CONFIG_E ---help--- STM32 WB Cortex M4, 512 Kb FLASH, 192+32+32 Kb SRAM config ARCH_CHIP_STM32WB55VE bool "STM32WB55VE" - select STM32WB_STM32WB55 + select STM32_STM32WB55 select STM32WB_IO_CONFIG_V - select STM32WB_FLASH_CONFIG_E_512 + select STM32_FLASH_CONFIG_E ---help--- STM32 WB Cortex M4, 512 Kb FLASH, 192+32+32 Kb SRAM config ARCH_CHIP_STM32WB55VY bool "STM32WB55VY" - select STM32WB_STM32WB55 + select STM32_STM32WB55 select STM32WB_IO_CONFIG_V - select STM32WB_FLASH_CONFIG_Y_640 + select STM32_FLASH_CONFIG_Y ---help--- STM32 WB Cortex M4, 640 Kb FLASH, 192+32+32 Kb SRAM config ARCH_CHIP_STM32WB55CG bool "STM32WB55CG" - select STM32WB_STM32WB55 + select STM32_STM32WB55 select STM32WB_IO_CONFIG_C - select STM32WB_FLASH_CONFIG_G_1024 + select STM32_FLASH_CONFIG_G ---help--- STM32 WB Cortex M4, 1024 Kb FLASH, 192+32+32 Kb SRAM config ARCH_CHIP_STM32WB55RG bool "STM32WB55RG" - select STM32WB_STM32WB55 + select STM32_STM32WB55 select STM32WB_IO_CONFIG_R - select STM32WB_FLASH_CONFIG_G_1024 + select STM32_FLASH_CONFIG_G ---help--- STM32 WB Cortex M4, 1024 Kb FLASH, 192+32+32 Kb SRAM config ARCH_CHIP_STM32WB55VG bool "STM32WB55VG" - select STM32WB_STM32WB55 + select STM32_STM32WB55 select STM32WB_IO_CONFIG_V - select STM32WB_FLASH_CONFIG_G_1024 + select STM32_FLASH_CONFIG_G ---help--- STM32 WB Cortex M4, 1024 Kb FLASH, 192+32+32 Kb SRAM @@ -144,137 +160,82 @@ endchoice # STM32 WB Chip Selection # Chip product lines -config STM32WB_STM32WB10 +config STM32_STM32WB10 # STM32WB10 Value Line bool default n - select STM32WB_HAVE_TSC + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 + select STM32_HAVE_TSC -config STM32WB_STM32WB15 +config STM32_STM32WB15 # STM32WB15 Standard Line bool default n - select STM32WB_HAVE_TSC - select STM32WB_HAVE_LPUART - select STM32WB_HAVE_SMPS if !ARCH_CHIP_STM32WB15CCUXE + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 + select STM32_HAVE_TSC + select STM32_HAVE_LPUART + select STM32_HAVE_SMPS if !ARCH_CHIP_STM32WB15CCUXE -config STM32WB_STM32WB30 +config STM32_STM32WB30 # STM32WB30 Value Line bool default n - select STM32WB_HAVE_HSI48 - select STM32WB_HAVE_TIM16 - select STM32WB_HAVE_TIM17 + select STM32_HAVE_HSI48 + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM16 + select STM32_HAVE_TIM17 -config STM32WB_STM32WB50 +config STM32_STM32WB50 # STM32WB50 Value Line bool default n - select STM32WB_HAVE_HSI48 - select STM32WB_HAVE_TIM16 - select STM32WB_HAVE_TIM17 + select STM32_HAVE_HSI48 + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM16 + select STM32_HAVE_TIM17 -config STM32WB_STM32WB35 +config STM32_STM32WB35 # STM32WB35 Standard Line bool default n - select STM32WB_HAVE_HSI48 - select STM32WB_HAVE_DMA2 - select STM32WB_HAVE_TIM16 - select STM32WB_HAVE_TIM17 - select STM32WB_HAVE_I2C3 - select STM32WB_HAVE_QSPI - select STM32WB_HAVE_USB - select STM32WB_HAVE_SAI - select STM32WB_HAVE_COMP - select STM32WB_HAVE_SMPS - -config STM32WB_STM32WB55 + select STM32_HAVE_HSI48 + select STM32_HAVE_DMA2 + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM16 + select STM32_HAVE_TIM17 + select STM32_HAVE_I2C3 + select STM32_HAVE_QSPI + select STM32_HAVE_USB + select STM32_HAVE_SAI + select STM32_HAVE_COMP + select STM32_HAVE_SMPS + +config STM32_STM32WB55 # STM32WB55 Standard Line bool default n - select STM32WB_HAVE_HSI48 - select STM32WB_HAVE_DMA2 - select STM32WB_HAVE_TIM16 - select STM32WB_HAVE_TIM17 - select STM32WB_HAVE_I2C3 - select STM32WB_HAVE_SPI2 if STM32WB_IO_CONFIG_R || STM32WB_IO_CONFIG_V - select STM32WB_HAVE_QSPI - select STM32WB_HAVE_USB - select STM32WB_HAVE_SAI - select STM32WB_HAVE_COMP - select STM32WB_HAVE_LPUART - select STM32WB_HAVE_TSC if STM32WB_IO_CONFIG_R || STM32WB_IO_CONFIG_V - select STM32WB_HAVE_LCD - select STM32WB_HAVE_SMPS - -choice - prompt "Override Flash Size Designator" - depends on ARCH_CHIP_STM32WB - default STM32WB_FLASH_OVERRIDE_DEFAULT - ---help--- - STM32WB series parts numbering (sans the package type) ends with a letter - that designates the FLASH size. - - Designator Size in KiB - C 256 or 320 - E 512 - Y 640 - G 1024 - - This configuration option defaults to using the configuration based on that designator - or the default smaller size if there is no last character designator is present in the - STM32WB Chip Selection. - - Examples: - If the STM32WB55RG is chosen, the Flash configuration would be 'G', if a variant of - the part with a 2048 KiB Flash is released in the future one could simply select - the 'I' designator here. - - If an STM32WB Series parts is chosen the default Flash configuration will be set - herein and can be changed. - -config STM32WB_FLASH_OVERRIDE_DEFAULT - bool "Default" - -config STM32WB_FLASH_OVERRIDE_C_256 - bool "C 256 KB" - -config STM32WB_FLASH_OVERRIDE_C_320 - bool "C 320 KB" - -config STM32WB_FLASH_OVERRIDE_E_512 - bool "E 512 KB" - -config STM32WB_FLASH_OVERRIDE_Y_640 - bool "Y 640 KB" - -config STM32WB_FLASH_OVERRIDE_G_1024 - bool "G 1024 KB" - -endchoice # "Override Flash Size Designator" - -# Flash configurations - -config STM32WB_FLASH_CONFIG_C_256 - bool - default n - -config STM32WB_FLASH_CONFIG_C_320 - bool - default n - -config STM32WB_FLASH_CONFIG_E_512 - bool - default n - -config STM32WB_FLASH_CONFIG_Y_640 - bool - default n + select STM32_HAVE_HSI48 + select STM32_HAVE_DMA2 + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM16 + select STM32_HAVE_TIM17 + select STM32_HAVE_I2C3 + select STM32_HAVE_SPI2 if STM32WB_IO_CONFIG_R || STM32WB_IO_CONFIG_V + select STM32_HAVE_QSPI + select STM32_HAVE_USB + select STM32_HAVE_SAI + select STM32_HAVE_COMP + select STM32_HAVE_LPUART + select STM32_HAVE_TSC if STM32WB_IO_CONFIG_R || STM32WB_IO_CONFIG_V + select STM32_HAVE_LCD + select STM32_HAVE_SMPS -config STM32WB_FLASH_CONFIG_G_1024 - bool - default n # Pin/package configurations @@ -282,13 +243,13 @@ config STM32WB_IO_CONFIG_C # UFQFPN48 package bool default n - select STM32WB_GPIO_HAVE_PORTE + select STM32_GPIO_HAVE_PORTE config STM32WB_IO_CONFIG_C_48E # UFQFPN48E package bool default n - select STM32WB_GPIO_HAVE_PORTE + select STM32_GPIO_HAVE_PORTE config STM32WB_IO_CONFIG_C_49 # WLCSP49 package @@ -299,889 +260,14 @@ config STM32WB_IO_CONFIG_R # VFQFPN68 package bool default n - select STM32WB_GPIO_HAVE_PORTD - select STM32WB_GPIO_HAVE_PORTE + select STM32_GPIO_HAVE_PORTD + select STM32_GPIO_HAVE_PORTE config STM32WB_IO_CONFIG_V # WLCSP100 and UFBGA129 packages bool default n - select STM32WB_GPIO_HAVE_PORTD - select STM32WB_GPIO_HAVE_PORTE - -comment "STM32WB SRAM2a and SRAM2b Options" - -config STM32WB_SRAM2A_HEAP - bool "SRAM2a is used for heap" - default n - -config STM32WB_SRAM2A_USER_BASE_OFFSET - int "SRAM2a user application base offset" - default 2048 - range 0 32768 - depends on STM32WB_SRAM2A_HEAP - ---help--- - The beginning part of the SRAM2a memory can be used by RF stack. The - available space for the user application can be obtained from the - release notes for STM32WB coprocessor wireless binaries. - -config STM32WB_SRAM2A_USER_SIZE - int "SRAM2a user application size" - default 8192 - range 0 32768 - depends on STM32WB_SRAM2A_HEAP - ---help--- - The ending part of the SRAM2a memory contains a secure section, which - cannot be read nor written by CPU1. The secure start address for the - SRAM2a memory can be read from the SBRSA option byte. When CPU2 update - support required, there must be some free sectors just below the secure - memory to support CPU2 firmware updates requiring more sectors to be - secure. - -config STM32WB_SRAM2A_INIT - bool "SRAM2a is initialized to zero" - default y - depends on STM32WB_SRAM2A_HEAP - ---help--- - The STM32WB SRAM2a region has parity checking. However, when the system - powers on, the memory is in an unknown state, and reads from uninitialized - memory can trigger parity faults from the random data. This can be - avoided by first writing to all locations to force the parity into a valid - state. - However, if the SRAM2a is being retained in Standby mode, this may be - undesirable (because it will destroy the contents). In that case, the board - should handle the initialization itself at the appropriate time. - -config STM32WB_SRAM2B_HEAP - bool "SRAM2b is used for heap" - default n - -config STM32WB_SRAM2B_USER_SIZE - int "SRAM2b user application size" - default 32768 - range 0 32768 - depends on STM32WB_SRAM2B_HEAP - ---help--- - For any CPU2 firmware supporting the BLE protocol the ending part of - the SRAM2b memory contains a secure section, which cannot be read nor - written by CPU1. The secure start address for the SRAM2b memory can be - read from the SNBRSA option byte. When CPU2 update support required, - there must be some free sectors just below the secure memory to support - CPU2 firmware updates requiring more sectors to be secure. The SRAM2b - memory is all secure for any CPU2 firmware supporting the Thread protocol. - -config STM32WB_SRAM2B_INIT - bool "SRAM2b is initialized to zero" - default y - depends on STM32WB_SRAM2B_HEAP - ---help--- - The STM32WB SRAM2b region has parity checking. However, when the system - powers on, the memory is in an unknown state, and reads from uninitialized - memory can trigger parity faults from the random data. This can be - avoided by first writing to all locations to force the parity into a valid - state. - -comment "STM32WB Peripherals" - -menu "STM32WB Peripheral Support" - -# These "hidden" settings determine whether a peripheral option is available -# for the selected MCU - -config STM32WB_GPIO_HAVE_PORTD - bool - default n - -config STM32WB_GPIO_HAVE_PORTE - bool - default n - -config STM32WB_HAVE_COMP - bool - default n - -config STM32WB_HAVE_LPUART - bool - default n - -config STM32WB_HAVE_DMA2 - bool - default n - -config STM32WB_HAVE_TIM16 - bool - default n - -config STM32WB_HAVE_TIM17 - bool - default n - -config STM32WB_HAVE_SPI2 - bool - default n - -config STM32WB_HAVE_I2C3 - bool - default n - -config STM32WB_HAVE_SAI - bool - default n - -config STM32WB_HAVE_LCD - bool - default n - -config STM32WB_HAVE_TSC - bool - default n - -config STM32WB_HAVE_USB - bool - default n - -config STM32WB_HAVE_QSPI - bool - default n - -config STM32WB_HAVE_SMPS - bool - default n - -# These are the peripheral selections proper - -config STM32WB_RTC - bool "RTC" - default n - select RTC - -# These "hidden" settings are the OR of individual peripheral selections -# indicating that the general capability is required. - -config STM32WB_ADC - bool - default n - -config STM32WB_DMAMUX - bool - default n - -config STM32WB_DMA - bool - default n - select STM32WB_DMAMUX - -config STM32WB_IPCC - bool - default n - -config STM32WB_I2C - bool - default n - -config STM32WB_SAI - bool - default n - -config STM32WB_SPI - bool - default n - -config STM32WB_USART - bool - default n - -config STM32WB_LPTIM - bool - default n - -# These are the peripheral selections proper - -comment "AHB1 Peripherals" - -config STM32WB_DMA1 - bool "DMA1" - default n - select ARCH_DMA - select STM32WB_DMA - -config STM32WB_DMA2 - bool "DMA2" - default n - depends on STM32WB_HAVE_DMA2 - select ARCH_DMA - select STM32WB_DMA - -config STM32WB_CRC - bool "CRC" - default n - -comment "APB1 Peripherals" - -config STM32WB_PWR - bool "PWR" - default n - -config STM32WB_TIM2 - bool "TIM2" - default n - -config STM32WB_SPI2 - bool "SPI2" - default n - depends on STM32WB_HAVE_SPI2 - select SPI - select STM32WB_SPI - -config STM32WB_LPTIM1 - bool "LPTIM1" - default n - select STM32WB_LPTIM - -config STM32WB_LPTIM2 - bool "LPTIM2" - default n - select STM32WB_LPTIM - -config STM32WB_LPUART1 - bool "LPUART1" - default n - depends on STM32WB_HAVE_LPUART - select ARCH_HAVE_SERIAL_TERMIOS - select ARCH_HAVE_LPUART1 - select STM32WB_USART - -config STM32WB_I2C1 - bool "I2C1" - default n - select I2C - select STM32WB_I2C - -config STM32WB_I2C3 - bool "I2C3" - default n - depends on STM32WB_HAVE_I2C3 - select I2C - select STM32WB_I2C - -comment "APB2 Peripherals" - -config STM32WB_SYSCFG - bool "SYSCFG" - default y - -config STM32WB_TIM1 - bool "TIM1" - default n - -config STM32WB_SPI1 - bool "SPI1" - default n - select SPI - select STM32WB_SPI - -config STM32WB_USART1 - bool "USART1" - default n - select ARCH_HAVE_SERIAL_TERMIOS - select STM32WB_USART - -config STM32WB_TIM16 - bool "TIM16" - default n - depends on STM32WB_HAVE_TIM16 - -config STM32WB_TIM17 - bool "TIM17" - default n - depends on STM32WB_HAVE_TIM17 - -endmenu - -config STM32WB_FLASH_PREFETCH - bool "Enable FLASH Pre-fetch" - default y - ---help--- - Enable FLASH prefetch - -config STM32WB_DISABLE_IDLE_SLEEP_DURING_DEBUG - bool "Disable IDLE Sleep (WFI) in debug mode" - default n - ---help--- - In debug configuration, disables the WFI instruction in the IDLE loop - to prevent the JTAG from disconnecting. With some JTAG debuggers, such - as the ST-LINK2 with OpenOCD, if the ARM is put to sleep via the WFI - instruction, the debugger will disconnect, terminating the debug session. - -config ARCH_BOARD_STM32WB_CUSTOM_CLOCKCONFIG - bool "Custom clock configuration" - default n - ---help--- - Enables special, board-specific STM32WB clock configuration. - -config STM32WB_HAVE_RTC_SUBSECONDS - bool - select ARCH_HAVE_RTC_SUBSECONDS - default y - -menu "RTC Configuration" - depends on STM32WB_RTC - -config STM32WB_RTC_MAGIC_REG - int "BKP register" - default 0 - range 0 31 - ---help--- - The BKP register used to store/check the Magic value to determine if - RTC is already setup - -config STM32WB_RTC_MAGIC - hex "RTC Magic 1" - default 0xfacefeed - ---help--- - Value used as Magic to determine if the RTC is already setup - -config STM32WB_RTC_MAGIC_TIME_SET - hex "RTC Magic 2" - default 0xf00dface - ---help--- - Value used as Magic to determine if the RTC has been setup and has - time set - -choice - prompt "RTC clock source" - default STM32WB_RTC_LSECLOCK - depends on STM32WB_RTC - -config STM32WB_RTC_LSECLOCK - bool "LSE clock" - ---help--- - Drive the RTC with the LSE clock - -config STM32WB_RTC_LSICLOCK - bool "LSI clock" - ---help--- - Drive the RTC with the LSI clock - -config STM32WB_RTC_HSECLOCK - bool "HSE clock" - ---help--- - Drive the RTC with the HSE clock, divided down to 1MHz. - -endchoice - -if STM32WB_RTC_LSECLOCK - -config STM32WB_RTC_LSECLOCK_START_DRV_CAPABILITY - int "LSE oscillator drive capability level at LSE start-up" - default 0 - range 0 3 - ---help--- - 0 = Low drive capability (default) - 1 = Medium low drive capability - 2 = Medium high drive capability - 3 = High drive capability - -config STM32WB_RTC_LSECLOCK_RUN_DRV_CAPABILITY - int "LSE oscillator drive capability level after LSE start-up" - default 0 - range 0 3 - ---help--- - 0 = Low drive capability (default) - 1 = Medium low drive capability - 2 = Medium high drive capability - 3 = High drive capability - -endif # STM32WB_RTC_LSECLOCK - -endmenu # RTC Configuration - -menu "Timer Configuration" - -if SCHED_TICKLESS - -config STM32WB_TICKLESS_TIMER - int "Tickless hardware timer" - default 2 - range 1 17 - ---help--- - If the Tickless OS feature is enabled, then one clock must be - assigned to provided the timer needed by the OS. - -config STM32WB_TICKLESS_CHANNEL - int "Tickless timer channel" - default 1 - range 1 4 - ---help--- - If the Tickless OS feature is enabled, the one clock must be - assigned to provided the free-running timer needed by the OS - and one channel on that clock is needed to handle intervals. - -endif # SCHED_TICKLESS - -config STM32WB_ONESHOT - bool "TIM one-shot wrapper" - default n - ---help--- - Enable a wrapper around the low level timer/counter functions to - support one-shot timer. - -config STM32WB_FREERUN - bool "TIM free-running wrapper" - default n - ---help--- - Enable a wrapper around the low level timer/counter functions to - support a free-running timer. - -config STM32WB_ONESHOT_MAXTIMERS - int "Maximum number of oneshot timers" - default 1 - range 1 8 - depends on STM32WB_ONESHOT - ---help--- - Determines the maximum number of oneshot timers that can be - supported. This setting pre-allocates some minimal support for each - of the timers and places an upper limit on the number of oneshot - timers that you can use. - -endmenu # Timer Configuration - -config STM32WB_SERIALDRIVER - bool - -menu "[LP]U[S]ART Configuration" - depends on STM32WB_LPUART1 || STM32WB_USART1 - -choice - prompt "LPUART1 Driver Configuration" - default STM32WB_LPUART1_SERIALDRIVER - depends on STM32WB_LPUART1 - -config STM32WB_LPUART1_SERIALDRIVER - bool "Standard serial driver" - select LPUART1_SERIALDRIVER - select STM32WB_SERIALDRIVER - -endchoice # LPUART1 Driver Configuration - -if LPUART1_SERIALDRIVER - -config LPUART1_RS485 - bool "RS-485 on LPUART1" - default n - depends on STM32WB_LPUART1 - ---help--- - Enable RS-485 interface on LPUART1. Your board config will have to - provide GPIO_LPUART1_RS485_DIR pin definition. Currently it cannot be - used with LPUART1_RXDMA. - -config LPUART1_RS485_DIR_POLARITY - int "LPUART1 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on LPUART1_RS485 - ---help--- - Polarity of DIR pin for RS-485 on LPUART1. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config LPUART1_RXDMA - bool "LPUART1 Rx DMA" - default n - depends on STM32WB_LPUART1 && STM32WB_DMA - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -endif # LPUART1_SERIALDRIVER - -choice - prompt "USART1 Driver Configuration" - default STM32WB_USART1_SERIALDRIVER - depends on STM32WB_USART1 - -config STM32WB_USART1_SERIALDRIVER - bool "Standard serial driver" - select USART1_SERIALDRIVER - select STM32WB_SERIALDRIVER - -endchoice # USART1 Driver Configuration - -if USART1_SERIALDRIVER - -config USART1_RS485 - bool "RS-485 on USART1" - default n - depends on STM32WB_USART1 - ---help--- - Enable RS-485 interface on USART1. Your board config will have to - provide GPIO_USART1_RS485_DIR pin definition. Currently it cannot be - used with USART1_RXDMA. - -config USART1_RS485_DIR_POLARITY - int "USART1 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on USART1_RS485 - ---help--- - Polarity of DIR pin for RS-485 on USART1. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config USART1_RXDMA - bool "USART1 Rx DMA" - default n - depends on STM32WB_USART1 && STM32WB_DMA - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -endif # USART1_SERIALDRIVER - -if STM32WB_SERIALDRIVER - -comment "Serial Driver Configuration" - -config STM32WB_SERIAL_RXDMA_BUFFER_SIZE - int "Rx DMA buffer size" - default 32 - depends on USART1_RXDMA - ---help--- - The DMA buffer size when using RX DMA to emulate a FIFO. - - When streaming data, the generic serial layer will be called - every time the FIFO receives half this number of bytes. - - Value given here will be rounded up to next multiple of 32 bytes. - -config STM32WB_SERIAL_DISABLE_REORDERING - bool "Disable reordering of ttySx devices." - depends on STM32WB_USART1 - default n - ---help--- - NuttX per default reorders the serial ports (/dev/ttySx) so that the - console is always on /dev/ttyS0. If more than one UART is in use this - can, however, have the side-effect that all port mappings - (hardware USART1 -> /dev/ttyS0) change if the console is moved to another - UART. This is in particular relevant if a project uses the USB console - in some boards and a serial console in other boards, but does not - want the side effect of having all serial port names change when just - the console is moved from serial to USB. - -config STM32WB_FLOWCONTROL_BROKEN - bool "Use Software UART RTS flow control" - depends on STM32WB_USART1 - default n - ---help--- - Enable UART RTS flow control using Software. Because STM - Current STM32WB have broken HW based RTS behavior (they assert - nRTS after every byte received) Enable this setting workaround - this issue by using software based management of RTS - -config STM32WB_USART_BREAKS - bool "Add TIOxSBRK to support sending Breaks" - depends on STM32WB_USART1 - default n - ---help--- - Add TIOCxBRK routines to send a line break per the STM32WB manual, the - break will be a pulse based on the value M. This is not a BSD compatible - break. - -config STM32WB_SERIALBRK_BSDCOMPAT - bool "Use GPIO To send Break" - depends on STM32WB_USART1 && STM32WB_USART_BREAKS - default n - ---help--- - Enable using GPIO on the TX pin to send a BSD compatible break: - TIOCSBRK will start the break and TIOCCBRK will end the break. - The current STM32WB U[S]ARTS have no way to leave the break on - (TX=LOW) because software starts the break and then the hardware - automatically clears the break. This makes it difficult to send - a long break. - -config STM32WB_USART_SINGLEWIRE - bool "Single Wire Support" - default n - depends on STM32WB_USART1 - ---help--- - Enable single wire UART support. The option enables support for the - TIOCSSINGLEWIRE ioctl in the STM32WB serial driver. - -config STM32WB_USART_INVERT - bool "Signal Invert Support" - default n - depends on STM32WB_USART1 - ---help--- - Enable signal inversion UART support. The option enables support for the - TIOCSINVERT ioctl in the STM32WB serial driver. - -config STM32WB_USART_SWAP - bool "Swap RX/TX pins support" - default n - depends on STM32WB_USART1 - ---help--- - Enable RX/TX pin swapping support. The option enables support for the - TIOCSSWAP ioctl in the STM32WB serial driver. - -if PM - -config STM32WB_PM_SERIAL_ACTIVITY - int "PM serial activity" - default 10 - ---help--- - PM activity reported to power management logic on every serial - interrupt. - -endif - -endif # STM32WB_SERIALDRIVER - -endmenu # [LP]U[S]ART Configuration - -menu "SPI Configuration" - depends on STM32WB_SPI1 || STM32WB_SPI2 - -config STM32WB_SPI_INTERRUPTS - bool "Interrupt driver SPI" - default n - ---help--- - Select to enable interrupt driven SPI support. Non-interrupt-driven, - poll-waiting is recommended if the interrupt rate would be to high in - the interrupt driven case. - -config STM32WB_SPI_DMA - bool "SPI DMA" - depends on STM32WB_DMA - default n - ---help--- - Use DMA to improve SPI transfer performance. Cannot be used with STM32WB_SPI_INTERRUPT. - -endmenu - -config STM32WB_MBOX - bool - default n - select STM32WB_IPCC - -menuconfig STM32WB_BLE - bool "BLE" - default n - select STM32WB_MBOX - ---help--- - Enable BLE support. - -if STM32WB_BLE - -config STM32WB_BLE_C2HOST - bool "Enable CPU2 HOST stack" - default n - ---help--- - The full stack version of CPU2 firmware allows to enable CPU2 HOST stack and - control it using vendor ACL protocol. However, it is not expected to enable - this option in the current implementation. - -config STM32WB_BLE_MAX_CONN - int "Maximum BLE simultaneous connections" - range 1 8 - default 2 - -config STM32WB_BLE_GATT_MAX_ATTR_NUM - int "GATT attributes max count" - range 9 255 - default 64 - -config STM32WB_BLE_GATT_MAX_SVC_NUM - int "GATT services max count" - range 2 64 - default 8 - -config STM32WB_BLE_GATT_ATTR_BUF_SIZE - int "GATT attributes storage buf size" - default 1344 - ---help--- - Size of the storage area for attribute values. Hardcoded in CPU2 firmware. - -config STM32WB_BLE_DLE - bool "Support Data Length Extension (DLE)" - default y - -config STM32WB_BLE_MAX_ATT_MTU - int "Maximum supported attribute MTU" - range 23 512 - default 156 - -config STM32WB_BLE_SLAVE_SCA - int "Sleep clock accuracy in slave mode [PPM]" - default 500 - ---help--- - Sleep clock accuracy (ppm value) in slave mode. - -choice - prompt "Sleep clock accuracy in master mode" - default STM32WB_BLE_MASTER_SCA_0 - ---help--- - Sleep clock accuracy in master mode. - -config STM32WB_BLE_MASTER_SCA_0 - bool "251-500 ppm" - -config STM32WB_BLE_MASTER_SCA_1 - bool "151-250 ppm" - -config STM32WB_BLE_MASTER_SCA_2 - bool "101-150 ppm" - -config STM32WB_BLE_MASTER_SCA_3 - bool "76-100 ppm" - -config STM32WB_BLE_MASTER_SCA_4 - bool "51-75 ppm" - -config STM32WB_BLE_MASTER_SCA_5 - bool "31-50 ppm" - -config STM32WB_BLE_MASTER_SCA_6 - bool "21-30 ppm" - -config STM32WB_BLE_MASTER_SCA_7 - bool "0-20 ppm" - -endchoice # Sleep clock accuracy in master mode - -config STM32WB_BLE_MASTER_SCA - int - default 7 if STM32WB_BLE_MASTER_SCA_7 - default 6 if STM32WB_BLE_MASTER_SCA_6 - default 5 if STM32WB_BLE_MASTER_SCA_5 - default 4 if STM32WB_BLE_MASTER_SCA_4 - default 3 if STM32WB_BLE_MASTER_SCA_3 - default 2 if STM32WB_BLE_MASTER_SCA_2 - default 1 if STM32WB_BLE_MASTER_SCA_1 - default 0 - -choice - prompt "Low speed clock source" - default STM32WB_BLE_LS_CLK_SRC_LSE - ---help--- - Low speed 32 kHz clock source. - -config STM32WB_BLE_LS_CLK_SRC_LSE - bool "LSE" - -config STM32WB_BLE_LS_CLK_SRC_HSE - bool "HSE" - -endchoice # Low speed clock source - -config STM32WB_BLE_LS_CLK_SRC - int - default 1 if STM32WB_BLE_LS_CLKSRC_HSE - default 0 - -config STM32WB_BLE_MAX_CONN_EVT_LENGTH - hex "Max connection event length" - default 0xffffffff - ---help--- - Maximum duration of a slave connection event in units of 625/256us (~2.44us). - -config STM32WB_BLE_HSE_STARTUP - hex "HSE startup time" - default 0x148 - ---help--- - HSE startup time in units of 625/256us (~2.44us). - -config STM32WB_BLE_VITERBI - bool "Enable Viterbi algorithm" - default y - ---help--- - Enable Viterbi algorithm implementation - -config STM32WB_BLE_MAX_INITOR_COC_NUM - int "Max number of connection-oriented channels" - range 0 64 - default 32 - ---help--- - Maximum number of connection-oriented channels in initiator mode. - -config STM32WB_BLE_SVC_CHANGED_CHAR - bool "Enable service changed characteristic" - default n - -config STM32WB_BLE_WRITABLE_DEVICE_NAME - bool "Writable device name" - default y - -config STM32WB_BLE_CHAN_SEL_ALG2 - bool "Enable channel selection algorithm 2" - default n - -choice - prompt "Power class" - default STM32WB_BLE_POWER_CLASS_2_3 - -config STM32WB_BLE_POWER_CLASS_2_3 - bool "Power Class 2-3" - -config STM32WB_BLE_POWER_CLASS_1 - bool "Power Class 1" - -endchoice # Power class - -config STM32WB_BLE_MIN_TX_POWER - int "Minimum transmit power [dBm]" - range -127 20 - default 0 - -config STM32WB_BLE_MAX_TX_POWER - int "Maximum transmit power [dBm]" - range -127 20 - default 0 - -choice - prompt "AGC RSSI model" - default STM32WB_BLE_AGC_RSSI_LEGACY - -config STM32WB_BLE_AGC_RSSI_LEGACY - bool "AGC RSSI Legacy" - -config STM32WB_BLE_AGC_RSSI_IMPROVED - bool "AGC RSSI Improved" - -endchoice # AGC RSSI model - -config STM32WB_BLE_ADVERTISING - bool "Support advertising" - default y - -config STM32WB_BLE_SCANNING - bool "Support scanning" - default y - -config STM32WB_BLE_LE_2M_PHY - bool "Support LE 2M PHY" - default y - -config STM32WB_BLE_LE_CODED_PHY - bool "Support LE Coded PHY" - default STM32WB_STM32WB15 || STM32WB_STM32WB35 || STM32WB_STM32WB55 - depends on STM32WB_STM32WB15 || STM32WB_STM32WB35 || STM32WB_STM32WB55 - -config STM32WB_BLE_FICR_STATIC_ADDR - bool "Configure factory generated static random address" - default n - -config STM32WB_BLE_PUB_ADDR - hex "Configure BT public address" - default 0x0000000000 - -endif # STM32WB_BLE - -if STM32WB_MBOX - -config STM32WB_MBOX_TX_CMD_QUEUE_LEN - int "Mailbox TX command queue length" - default 2 - -config STM32WB_MBOX_RX_EVT_QUEUE_LEN - int "Mailbox RX event queue length" - default 5 - -endif # STM32WB_MBOX + select STM32_GPIO_HAVE_PORTD + select STM32_GPIO_HAVE_PORTE endif # ARCH_CHIP_STM32WB diff --git a/arch/arm/src/stm32wb/Make.defs b/arch/arm/src/stm32wb/Make.defs index a8ff0d7afa91d..5a4bdcdb88e24 100644 --- a/arch/arm/src/stm32wb/Make.defs +++ b/arch/arm/src/stm32wb/Make.defs @@ -26,15 +26,16 @@ # Common ARM and Cortex-M4 files (copied from stm32/Make.defs) include armv7-m/Make.defs +include common/stm32/Make.defs # Required STM32WB files -CHIP_CSRCS = stm32wb_allocateheap.c stm32wb_exti_gpio.c stm32wb_gpio.c +CHIP_CSRCS += stm32wb_allocateheap.c stm32wb_exti_gpio.c stm32wb_gpio.c CHIP_CSRCS += stm32wb_irq.c stm32wb_lowputc.c stm32wb_rcc.c stm32wb_spi.c -CHIP_CSRCS += stm32wb_serial.c stm32wb_i2c.c stm32wb_start.c stm32wb_waste.c +CHIP_CSRCS += stm32wb_serial.c stm32wb_i2c.c stm32wb_start.c CHIP_CSRCS += stm32wb_rcc_lse.c stm32wb_rcc_lsi.c CHIP_CSRCS += stm32wb_pwr.c stm32wb_tim.c -CHIP_CSRCS += stm32wb_flash.c stm32wb_uid.c +CHIP_CSRCS += stm32wb_flash.c ifneq ($(CONFIG_ARCH_IDLE_CUSTOM),y) CHIP_CSRCS += stm32wb_idle.c @@ -50,11 +51,11 @@ else CHIP_CSRCS += stm32wb_tickless.c endif -ifeq ($(CONFIG_STM32WB_ONESHOT),y) +ifeq ($(CONFIG_STM32_ONESHOT),y) CHIP_CSRCS += stm32wb_oneshot.c stm32wb_oneshot_lowerhalf.c endif -ifeq ($(CONFIG_STM32WB_FREERUN),y) +ifeq ($(CONFIG_STM32_FREERUN),y) CHIP_CSRCS += stm32wb_freerun.c endif @@ -62,11 +63,11 @@ ifeq ($(CONFIG_BUILD_PROTECTED),y) CHIP_CSRCS += stm32wb_userspace.c stm32wb_mpuinit.c endif -ifeq ($(CONFIG_STM32WB_HAVE_HSI48),y) +ifeq ($(CONFIG_STM32_HAVE_HSI48),y) CHIP_CSRCS += stm32wb_rcc_hsi48.c endif -ifeq ($(CONFIG_STM32WB_DMA),y) +ifeq ($(CONFIG_STM32_DMA),y) CHIP_CSRCS += stm32wb_dma.c endif @@ -79,11 +80,11 @@ CHIP_CSRCS += stm32wb_pminitialize.c endif endif -ifeq ($(CONFIG_STM32WB_PWR),y) +ifeq ($(CONFIG_STM32_PWR),y) CHIP_CSRCS += stm32wb_exti_pwr.c endif -ifeq ($(CONFIG_STM32WB_RTC),y) +ifeq ($(CONFIG_STM32_RTC),y) ifeq ($(CONFIG_RTC_ALARM),y) CHIP_CSRCS += stm32wb_exti_alarm.c endif @@ -95,15 +96,15 @@ CHIP_CSRCS += stm32wb_rtc.c stm32wb_rtc_lowerhalf.c endif endif -ifeq ($(CONFIG_STM32WB_IPCC),y) +ifeq ($(CONFIG_STM32_IPCC),y) CHIP_CSRCS += stm32wb_ipcc.c endif -ifeq ($(CONFIG_STM32WB_MBOX),y) +ifeq ($(CONFIG_STM32_MBOX),y) CHIP_CSRCS += stm32wb_mbox.c endif -ifeq ($(CONFIG_STM32WB_BLE),y) +ifeq ($(CONFIG_STM32_BLE),y) CHIP_CSRCS += stm32wb_blehci.c endif diff --git a/arch/arm/src/stm32wb/chip.h b/arch/arm/src/stm32wb/chip.h index 1c263402e683c..cddd9871d0351 100644 --- a/arch/arm/src/stm32wb/chip.h +++ b/arch/arm/src/stm32wb/chip.h @@ -49,7 +49,7 @@ * arch/stm32wb/chip.h header file. */ -#define ARMV7M_PERIPHERAL_INTERRUPTS STM32WB_IRQ_NEXTINTS +#define ARMV7M_PERIPHERAL_INTERRUPTS STM32_IRQ_NEXTINTS /* Cache line sizes (in bytes) for the STM32WB */ diff --git a/arch/arm/src/stm32wb/hardware/stm32wb_crs.h b/arch/arm/src/stm32wb/hardware/stm32wb_crs.h index fcac2dde6db3f..c47e5d34f5564 100644 --- a/arch/arm/src/stm32wb/hardware/stm32wb_crs.h +++ b/arch/arm/src/stm32wb/hardware/stm32wb_crs.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32WB_CRS_H -#define __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32WB_CRS_H +#ifndef __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32_CRS_H +#define __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32_CRS_H /**************************************************************************** * Pre-processor Definitions @@ -29,17 +29,17 @@ /* Register Offsets *********************************************************/ -#define STM32WB_CRS_CR_OFFSET 0x0000 /* CRS control register */ -#define STM32WB_CRS_CFGR_OFFSET 0x0004 /* CRS configuration register */ -#define STM32WB_CRS_ISR_OFFSET 0x0008 /* CRS interrupt and status register */ -#define STM32WB_CRS_ICR_OFFSET 0x000c /* CRS interrupt flag clear register */ +#define STM32_CRS_CR_OFFSET 0x0000 /* CRS control register */ +#define STM32_CRS_CFGR_OFFSET 0x0004 /* CRS configuration register */ +#define STM32_CRS_ISR_OFFSET 0x0008 /* CRS interrupt and status register */ +#define STM32_CRS_ICR_OFFSET 0x000c /* CRS interrupt flag clear register */ /* Register Addresses *******************************************************/ -#define STM32WB_CRS_CR (STM32WB_CRS_BASE + STM32WB_CRS_CR_OFFSET) -#define STM32WB_CRS_CFGR (STM32WB_CRS_BASE + STM32WB_CRS_CFGR_OFFSET) -#define STM32WB_CRS_ISR (STM32WB_CRS_BASE + STM32WB_CRS_ISR_OFFSET) -#define STM32WB_CRS_ICR (STM32WB_CRS_BASE + STM32WB_CRS_ICR_OFFSET) +#define STM32_CRS_CR (STM32_CRS_BASE + STM32_CRS_CR_OFFSET) +#define STM32_CRS_CFGR (STM32_CRS_BASE + STM32_CRS_CFGR_OFFSET) +#define STM32_CRS_ISR (STM32_CRS_BASE + STM32_CRS_ISR_OFFSET) +#define STM32_CRS_ICR (STM32_CRS_BASE + STM32_CRS_ICR_OFFSET) /* Register Bitfield Definitions ********************************************/ @@ -102,4 +102,4 @@ #define CRS_ICR_ERRC (1 << 2) /* Bit 2: Error clear flag */ #define CRS_ICR_ESYNCC (1 << 3) /* Bit 3: Expected SYNC clear flag */ -#endif /* __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32WB_CRS_H */ +#endif /* __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32_CRS_H */ diff --git a/arch/arm/src/stm32wb/hardware/stm32wb_dma.h b/arch/arm/src/stm32wb/hardware/stm32wb_dma.h index dfd6e1050dbfe..83611ce75b246 100644 --- a/arch/arm/src/stm32wb/hardware/stm32wb_dma.h +++ b/arch/arm/src/stm32wb/hardware/stm32wb_dma.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32WB_DMA_H -#define __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32WB_DMA_H +#ifndef __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32_DMA_H +#define __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32_DMA_H /**************************************************************************** * Included Files @@ -41,139 +41,139 @@ /* Register Offsets *********************************************************/ -#define STM32WB_DMA_ISR_OFFSET 0x0000 /* DMA interrupt status register */ -#define STM32WB_DMA_IFCR_OFFSET 0x0004 /* DMA interrupt flag clear register */ - -#define STM32WB_DMACHAN_OFFSET(n) (0x0014 * (n)) -#define STM32WB_DMACHAN1_OFFSET 0x0000 -#define STM32WB_DMACHAN2_OFFSET 0x0014 -#define STM32WB_DMACHAN3_OFFSET 0x0028 -#define STM32WB_DMACHAN4_OFFSET 0x003c -#define STM32WB_DMACHAN5_OFFSET 0x0050 -#define STM32WB_DMACHAN6_OFFSET 0x0064 -#define STM32WB_DMACHAN7_OFFSET 0x0078 - -#define STM32WB_DMACHAN_CCR_OFFSET 0x0008 /* DMA channel configuration register */ -#define STM32WB_DMACHAN_CNDTR_OFFSET 0x000c /* DMA channel number of data register */ -#define STM32WB_DMACHAN_CPAR_OFFSET 0x0010 /* DMA channel peripheral address register */ -#define STM32WB_DMACHAN_CMAR_OFFSET 0x0014 /* DMA channel memory address register */ - -#define STM32WB_DMA_CCR_OFFSET(n) (STM32WB_DMACHAN_CCR_OFFSET + STM32WB_DMACHAN_OFFSET(n)) -#define STM32WB_DMA_CNDTR_OFFSET(n) (STM32WB_DMACHAN_CNDTR_OFFSET + STM32WB_DMACHAN_OFFSET(n)) -#define STM32WB_DMA_CPAR_OFFSET(n) (STM32WB_DMACHAN_CPAR_OFFSET + STM32WB_DMACHAN_OFFSET(n)) -#define STM32WB_DMA_CMAR_OFFSET(n) (STM32WB_DMACHAN_CMAR_OFFSET + STM32WB_DMACHAN_OFFSET(n)) - -#define STM32WB_DMA_CCR1_OFFSET 0x0008 /* DMA channel 1 configuration register */ -#define STM32WB_DMA_CCR2_OFFSET 0x001c /* DMA channel 2 configuration register */ -#define STM32WB_DMA_CCR3_OFFSET 0x0030 /* DMA channel 3 configuration register */ -#define STM32WB_DMA_CCR4_OFFSET 0x0044 /* DMA channel 4 configuration register */ -#define STM32WB_DMA_CCR5_OFFSET 0x0058 /* DMA channel 5 configuration register */ -#define STM32WB_DMA_CCR6_OFFSET 0x006c /* DMA channel 6 configuration register */ -#define STM32WB_DMA_CCR7_OFFSET 0x0080 /* DMA channel 7 configuration register */ - -#define STM32WB_DMA_CNDTR1_OFFSET 0x000c /* DMA channel 1 number of data register */ -#define STM32WB_DMA_CNDTR2_OFFSET 0x0020 /* DMA channel 2 number of data register */ -#define STM32WB_DMA_CNDTR3_OFFSET 0x0034 /* DMA channel 3 number of data register */ -#define STM32WB_DMA_CNDTR4_OFFSET 0x0048 /* DMA channel 4 number of data register */ -#define STM32WB_DMA_CNDTR5_OFFSET 0x005c /* DMA channel 5 number of data register */ -#define STM32WB_DMA_CNDTR6_OFFSET 0x0070 /* DMA channel 6 number of data register */ -#define STM32WB_DMA_CNDTR7_OFFSET 0x0084 /* DMA channel 7 number of data register */ - -#define STM32WB_DMA_CPAR1_OFFSET 0x0010 /* DMA channel 1 peripheral address register */ -#define STM32WB_DMA_CPAR2_OFFSET 0x0024 /* DMA channel 2 peripheral address register */ -#define STM32WB_DMA_CPAR3_OFFSET 0x0038 /* DMA channel 3 peripheral address register */ -#define STM32WB_DMA_CPAR4_OFFSET 0x004c /* DMA channel 4 peripheral address register */ -#define STM32WB_DMA_CPAR5_OFFSET 0x0060 /* DMA channel 5 peripheral address register */ -#define STM32WB_DMA_CPAR6_OFFSET 0x0074 /* DMA channel 6 peripheral address register */ -#define STM32WB_DMA_CPAR7_OFFSET 0x0088 /* DMA channel 7 peripheral address register */ - -#define STM32WB_DMA_CMAR1_OFFSET 0x0014 /* DMA channel 1 memory address register */ -#define STM32WB_DMA_CMAR2_OFFSET 0x0028 /* DMA channel 2 memory address register */ -#define STM32WB_DMA_CMAR3_OFFSET 0x003c /* DMA channel 3 memory address register */ -#define STM32WB_DMA_CMAR4_OFFSET 0x0050 /* DMA channel 4 memory address register */ -#define STM32WB_DMA_CMAR5_OFFSET 0x0064 /* DMA channel 5 memory address register */ -#define STM32WB_DMA_CMAR6_OFFSET 0x0078 /* DMA channel 6 memory address register */ -#define STM32WB_DMA_CMAR7_OFFSET 0x008c /* DMA channel 7 memory address register */ +#define STM32_DMA_ISR_OFFSET 0x0000 /* DMA interrupt status register */ +#define STM32_DMA_IFCR_OFFSET 0x0004 /* DMA interrupt flag clear register */ + +#define STM32_DMACHAN_OFFSET(n) (0x0014 * (n)) +#define STM32_DMACHAN1_OFFSET 0x0000 +#define STM32_DMACHAN2_OFFSET 0x0014 +#define STM32_DMACHAN3_OFFSET 0x0028 +#define STM32_DMACHAN4_OFFSET 0x003c +#define STM32_DMACHAN5_OFFSET 0x0050 +#define STM32_DMACHAN6_OFFSET 0x0064 +#define STM32_DMACHAN7_OFFSET 0x0078 + +#define STM32_DMACHAN_CCR_OFFSET 0x0008 /* DMA channel configuration register */ +#define STM32_DMACHAN_CNDTR_OFFSET 0x000c /* DMA channel number of data register */ +#define STM32_DMACHAN_CPAR_OFFSET 0x0010 /* DMA channel peripheral address register */ +#define STM32_DMACHAN_CMAR_OFFSET 0x0014 /* DMA channel memory address register */ + +#define STM32_DMA_CCR_OFFSET(n) (STM32_DMACHAN_CCR_OFFSET + STM32_DMACHAN_OFFSET(n)) +#define STM32_DMA_CNDTR_OFFSET(n) (STM32_DMACHAN_CNDTR_OFFSET + STM32_DMACHAN_OFFSET(n)) +#define STM32_DMA_CPAR_OFFSET(n) (STM32_DMACHAN_CPAR_OFFSET + STM32_DMACHAN_OFFSET(n)) +#define STM32_DMA_CMAR_OFFSET(n) (STM32_DMACHAN_CMAR_OFFSET + STM32_DMACHAN_OFFSET(n)) + +#define STM32_DMA_CCR1_OFFSET 0x0008 /* DMA channel 1 configuration register */ +#define STM32_DMA_CCR2_OFFSET 0x001c /* DMA channel 2 configuration register */ +#define STM32_DMA_CCR3_OFFSET 0x0030 /* DMA channel 3 configuration register */ +#define STM32_DMA_CCR4_OFFSET 0x0044 /* DMA channel 4 configuration register */ +#define STM32_DMA_CCR5_OFFSET 0x0058 /* DMA channel 5 configuration register */ +#define STM32_DMA_CCR6_OFFSET 0x006c /* DMA channel 6 configuration register */ +#define STM32_DMA_CCR7_OFFSET 0x0080 /* DMA channel 7 configuration register */ + +#define STM32_DMA_CNDTR1_OFFSET 0x000c /* DMA channel 1 number of data register */ +#define STM32_DMA_CNDTR2_OFFSET 0x0020 /* DMA channel 2 number of data register */ +#define STM32_DMA_CNDTR3_OFFSET 0x0034 /* DMA channel 3 number of data register */ +#define STM32_DMA_CNDTR4_OFFSET 0x0048 /* DMA channel 4 number of data register */ +#define STM32_DMA_CNDTR5_OFFSET 0x005c /* DMA channel 5 number of data register */ +#define STM32_DMA_CNDTR6_OFFSET 0x0070 /* DMA channel 6 number of data register */ +#define STM32_DMA_CNDTR7_OFFSET 0x0084 /* DMA channel 7 number of data register */ + +#define STM32_DMA_CPAR1_OFFSET 0x0010 /* DMA channel 1 peripheral address register */ +#define STM32_DMA_CPAR2_OFFSET 0x0024 /* DMA channel 2 peripheral address register */ +#define STM32_DMA_CPAR3_OFFSET 0x0038 /* DMA channel 3 peripheral address register */ +#define STM32_DMA_CPAR4_OFFSET 0x004c /* DMA channel 4 peripheral address register */ +#define STM32_DMA_CPAR5_OFFSET 0x0060 /* DMA channel 5 peripheral address register */ +#define STM32_DMA_CPAR6_OFFSET 0x0074 /* DMA channel 6 peripheral address register */ +#define STM32_DMA_CPAR7_OFFSET 0x0088 /* DMA channel 7 peripheral address register */ + +#define STM32_DMA_CMAR1_OFFSET 0x0014 /* DMA channel 1 memory address register */ +#define STM32_DMA_CMAR2_OFFSET 0x0028 /* DMA channel 2 memory address register */ +#define STM32_DMA_CMAR3_OFFSET 0x003c /* DMA channel 3 memory address register */ +#define STM32_DMA_CMAR4_OFFSET 0x0050 /* DMA channel 4 memory address register */ +#define STM32_DMA_CMAR5_OFFSET 0x0064 /* DMA channel 5 memory address register */ +#define STM32_DMA_CMAR6_OFFSET 0x0078 /* DMA channel 6 memory address register */ +#define STM32_DMA_CMAR7_OFFSET 0x008c /* DMA channel 7 memory address register */ /* Register Addresses *******************************************************/ -#define STM32WB_DMA1_ISRC (STM32WB_DMA1_BASE + STM32WB_DMA_ISR_OFFSET) -#define STM32WB_DMA1_IFCR (STM32WB_DMA1_BASE + STM32WB_DMA_IFCR_OFFSET) - -#define STM32WB_DMA1_CCR(n) (STM32WB_DMA1_BASE + STM32WB_DMA_CCR_OFFSET(n)) -#define STM32WB_DMA1_CCR1 (STM32WB_DMA1_BASE + STM32WB_DMA_CCR1_OFFSET) -#define STM32WB_DMA1_CCR2 (STM32WB_DMA1_BASE + STM32WB_DMA_CCR2_OFFSET) -#define STM32WB_DMA1_CCR3 (STM32WB_DMA1_BASE + STM32WB_DMA_CCR3_OFFSET) -#define STM32WB_DMA1_CCR4 (STM32WB_DMA1_BASE + STM32WB_DMA_CCR4_OFFSET) -#define STM32WB_DMA1_CCR5 (STM32WB_DMA1_BASE + STM32WB_DMA_CCR5_OFFSET) -#define STM32WB_DMA1_CCR6 (STM32WB_DMA1_BASE + STM32WB_DMA_CCR6_OFFSET) -#define STM32WB_DMA1_CCR7 (STM32WB_DMA1_BASE + STM32WB_DMA_CCR7_OFFSET) - -#define STM32WB_DMA1_CNDTR(n) (STM32WB_DMA1_BASE + STM32WB_DMA_CNDTR_OFFSET(n)) -#define STM32WB_DMA1_CNDTR1 (STM32WB_DMA1_BASE + STM32WB_DMA_CNDTR1_OFFSET) -#define STM32WB_DMA1_CNDTR2 (STM32WB_DMA1_BASE + STM32WB_DMA_CNDTR2_OFFSET) -#define STM32WB_DMA1_CNDTR3 (STM32WB_DMA1_BASE + STM32WB_DMA_CNDTR3_OFFSET) -#define STM32WB_DMA1_CNDTR4 (STM32WB_DMA1_BASE + STM32WB_DMA_CNDTR4_OFFSET) -#define STM32WB_DMA1_CNDTR5 (STM32WB_DMA1_BASE + STM32WB_DMA_CNDTR5_OFFSET) -#define STM32WB_DMA1_CNDTR6 (STM32WB_DMA1_BASE + STM32WB_DMA_CNDTR6_OFFSET) -#define STM32WB_DMA1_CNDTR7 (STM32WB_DMA1_BASE + STM32WB_DMA_CNDTR7_OFFSET) - -#define STM32WB_DMA1_CPAR(n) (STM32WB_DMA1_BASE + STM32WB_DMA_CPAR_OFFSET(n)) -#define STM32WB_DMA1_CPAR1 (STM32WB_DMA1_BASE + STM32WB_DMA_CPAR1_OFFSET) -#define STM32WB_DMA1_CPAR2 (STM32WB_DMA1_BASE + STM32WB_DMA_CPAR2_OFFSET) -#define STM32WB_DMA1_CPAR3 (STM32WB_DMA1_BASE + STM32WB_DMA_CPAR3_OFFSET) -#define STM32WB_DMA1_CPAR4 (STM32WB_DMA1_BASE + STM32WB_DMA_CPAR4_OFFSET) -#define STM32WB_DMA1_CPAR5 (STM32WB_DMA1_BASE + STM32WB_DMA_CPAR5_OFFSET) -#define STM32WB_DMA1_CPAR6 (STM32WB_DMA1_BASE + STM32WB_DMA_CPAR6_OFFSET) -#define STM32WB_DMA1_CPAR7 (STM32WB_DMA1_BASE + STM32WB_DMA_CPAR7_OFFSET) - -#define STM32WB_DMA1_CMAR(n) (STM32WB_DMA1_BASE + STM32WB_DMA_CMAR_OFFSET(n)) -#define STM32WB_DMA1_CMAR1 (STM32WB_DMA1_BASE + STM32WB_DMA_CMAR1_OFFSET) -#define STM32WB_DMA1_CMAR2 (STM32WB_DMA1_BASE + STM32WB_DMA_CMAR2_OFFSET) -#define STM32WB_DMA1_CMAR3 (STM32WB_DMA1_BASE + STM32WB_DMA_CMAR3_OFFSET) -#define STM32WB_DMA1_CMAR4 (STM32WB_DMA1_BASE + STM32WB_DMA_CMAR4_OFFSET) -#define STM32WB_DMA1_CMAR5 (STM32WB_DMA1_BASE + STM32WB_DMA_CMAR5_OFFSET) -#define STM32WB_DMA1_CMAR6 (STM32WB_DMA1_BASE + STM32WB_DMA_CMAR6_OFFSET) -#define STM32WB_DMA1_CMAR7 (STM32WB_DMA1_BASE + STM32WB_DMA_CMAR7_OFFSET) - -#define STM32WB_DMA2_ISRC (STM32WB_DMA2_BASE + STM32WB_DMA_ISR_OFFSET) -#define STM32WB_DMA2_IFCR (STM32WB_DMA2_BASE + STM32WB_DMA_IFCR_OFFSET) - -#define STM32WB_DMA2_CCR(n) (STM32WB_DMA2_BASE + STM32WB_DMA_CCR_OFFSET(n)) -#define STM32WB_DMA2_CCR1 (STM32WB_DMA2_BASE + STM32WB_DMA_CCR1_OFFSET) -#define STM32WB_DMA2_CCR2 (STM32WB_DMA2_BASE + STM32WB_DMA_CCR2_OFFSET) -#define STM32WB_DMA2_CCR3 (STM32WB_DMA2_BASE + STM32WB_DMA_CCR3_OFFSET) -#define STM32WB_DMA2_CCR4 (STM32WB_DMA2_BASE + STM32WB_DMA_CCR4_OFFSET) -#define STM32WB_DMA2_CCR5 (STM32WB_DMA2_BASE + STM32WB_DMA_CCR5_OFFSET) -#define STM32WB_DMA2_CCR6 (STM32WB_DMA2_BASE + STM32WB_DMA_CCR6_OFFSET) -#define STM32WB_DMA2_CCR7 (STM32WB_DMA2_BASE + STM32WB_DMA_CCR7_OFFSET) - -#define STM32WB_DMA2_CNDTR(n) (STM32WB_DMA2_BASE + STM32WB_DMA_CNDTR_OFFSET(n)) -#define STM32WB_DMA2_CNDTR1 (STM32WB_DMA2_BASE + STM32WB_DMA_CNDTR1_OFFSET) -#define STM32WB_DMA2_CNDTR2 (STM32WB_DMA2_BASE + STM32WB_DMA_CNDTR2_OFFSET) -#define STM32WB_DMA2_CNDTR3 (STM32WB_DMA2_BASE + STM32WB_DMA_CNDTR3_OFFSET) -#define STM32WB_DMA2_CNDTR4 (STM32WB_DMA2_BASE + STM32WB_DMA_CNDTR4_OFFSET) -#define STM32WB_DMA2_CNDTR5 (STM32WB_DMA2_BASE + STM32WB_DMA_CNDTR5_OFFSET) -#define STM32WB_DMA2_CNDTR6 (STM32WB_DMA2_BASE + STM32WB_DMA_CNDTR6_OFFSET) -#define STM32WB_DMA2_CNDTR7 (STM32WB_DMA2_BASE + STM32WB_DMA_CNDTR7_OFFSET) - -#define STM32WB_DMA2_CPAR(n) (STM32WB_DMA2_BASE + STM32WB_DMA_CPAR_OFFSET(n)) -#define STM32WB_DMA2_CPAR1 (STM32WB_DMA2_BASE + STM32WB_DMA_CPAR1_OFFSET) -#define STM32WB_DMA2_CPAR2 (STM32WB_DMA2_BASE + STM32WB_DMA_CPAR2_OFFSET) -#define STM32WB_DMA2_CPAR3 (STM32WB_DMA2_BASE + STM32WB_DMA_CPAR3_OFFSET) -#define STM32WB_DMA2_CPAR4 (STM32WB_DMA2_BASE + STM32WB_DMA_CPAR4_OFFSET) -#define STM32WB_DMA2_CPAR5 (STM32WB_DMA2_BASE + STM32WB_DMA_CPAR5_OFFSET) -#define STM32WB_DMA2_CPAR6 (STM32WB_DMA2_BASE + STM32WB_DMA_CPAR6_OFFSET) -#define STM32WB_DMA2_CPAR7 (STM32WB_DMA2_BASE + STM32WB_DMA_CPAR7_OFFSET) - -#define STM32WB_DMA2_CMAR(n) (STM32WB_DMA2_BASE + STM32WB_DMA_CMAR_OFFSET(n)) -#define STM32WB_DMA2_CMAR1 (STM32WB_DMA2_BASE + STM32WB_DMA_CMAR1_OFFSET) -#define STM32WB_DMA2_CMAR2 (STM32WB_DMA2_BASE + STM32WB_DMA_CMAR2_OFFSET) -#define STM32WB_DMA2_CMAR3 (STM32WB_DMA2_BASE + STM32WB_DMA_CMAR3_OFFSET) -#define STM32WB_DMA2_CMAR4 (STM32WB_DMA2_BASE + STM32WB_DMA_CMAR4_OFFSET) -#define STM32WB_DMA2_CMAR5 (STM32WB_DMA2_BASE + STM32WB_DMA_CMAR5_OFFSET) -#define STM32WB_DMA2_CMAR6 (STM32WB_DMA2_BASE + STM32WB_DMA_CMAR6_OFFSET) -#define STM32WB_DMA2_CMAR7 (STM32WB_DMA2_BASE + STM32WB_DMA_CMAR7_OFFSET) +#define STM32_DMA1_ISRC (STM32_DMA1_BASE + STM32_DMA_ISR_OFFSET) +#define STM32_DMA1_IFCR (STM32_DMA1_BASE + STM32_DMA_IFCR_OFFSET) + +#define STM32_DMA1_CCR(n) (STM32_DMA1_BASE + STM32_DMA_CCR_OFFSET(n)) +#define STM32_DMA1_CCR1 (STM32_DMA1_BASE + STM32_DMA_CCR1_OFFSET) +#define STM32_DMA1_CCR2 (STM32_DMA1_BASE + STM32_DMA_CCR2_OFFSET) +#define STM32_DMA1_CCR3 (STM32_DMA1_BASE + STM32_DMA_CCR3_OFFSET) +#define STM32_DMA1_CCR4 (STM32_DMA1_BASE + STM32_DMA_CCR4_OFFSET) +#define STM32_DMA1_CCR5 (STM32_DMA1_BASE + STM32_DMA_CCR5_OFFSET) +#define STM32_DMA1_CCR6 (STM32_DMA1_BASE + STM32_DMA_CCR6_OFFSET) +#define STM32_DMA1_CCR7 (STM32_DMA1_BASE + STM32_DMA_CCR7_OFFSET) + +#define STM32_DMA1_CNDTR(n) (STM32_DMA1_BASE + STM32_DMA_CNDTR_OFFSET(n)) +#define STM32_DMA1_CNDTR1 (STM32_DMA1_BASE + STM32_DMA_CNDTR1_OFFSET) +#define STM32_DMA1_CNDTR2 (STM32_DMA1_BASE + STM32_DMA_CNDTR2_OFFSET) +#define STM32_DMA1_CNDTR3 (STM32_DMA1_BASE + STM32_DMA_CNDTR3_OFFSET) +#define STM32_DMA1_CNDTR4 (STM32_DMA1_BASE + STM32_DMA_CNDTR4_OFFSET) +#define STM32_DMA1_CNDTR5 (STM32_DMA1_BASE + STM32_DMA_CNDTR5_OFFSET) +#define STM32_DMA1_CNDTR6 (STM32_DMA1_BASE + STM32_DMA_CNDTR6_OFFSET) +#define STM32_DMA1_CNDTR7 (STM32_DMA1_BASE + STM32_DMA_CNDTR7_OFFSET) + +#define STM32_DMA1_CPAR(n) (STM32_DMA1_BASE + STM32_DMA_CPAR_OFFSET(n)) +#define STM32_DMA1_CPAR1 (STM32_DMA1_BASE + STM32_DMA_CPAR1_OFFSET) +#define STM32_DMA1_CPAR2 (STM32_DMA1_BASE + STM32_DMA_CPAR2_OFFSET) +#define STM32_DMA1_CPAR3 (STM32_DMA1_BASE + STM32_DMA_CPAR3_OFFSET) +#define STM32_DMA1_CPAR4 (STM32_DMA1_BASE + STM32_DMA_CPAR4_OFFSET) +#define STM32_DMA1_CPAR5 (STM32_DMA1_BASE + STM32_DMA_CPAR5_OFFSET) +#define STM32_DMA1_CPAR6 (STM32_DMA1_BASE + STM32_DMA_CPAR6_OFFSET) +#define STM32_DMA1_CPAR7 (STM32_DMA1_BASE + STM32_DMA_CPAR7_OFFSET) + +#define STM32_DMA1_CMAR(n) (STM32_DMA1_BASE + STM32_DMA_CMAR_OFFSET(n)) +#define STM32_DMA1_CMAR1 (STM32_DMA1_BASE + STM32_DMA_CMAR1_OFFSET) +#define STM32_DMA1_CMAR2 (STM32_DMA1_BASE + STM32_DMA_CMAR2_OFFSET) +#define STM32_DMA1_CMAR3 (STM32_DMA1_BASE + STM32_DMA_CMAR3_OFFSET) +#define STM32_DMA1_CMAR4 (STM32_DMA1_BASE + STM32_DMA_CMAR4_OFFSET) +#define STM32_DMA1_CMAR5 (STM32_DMA1_BASE + STM32_DMA_CMAR5_OFFSET) +#define STM32_DMA1_CMAR6 (STM32_DMA1_BASE + STM32_DMA_CMAR6_OFFSET) +#define STM32_DMA1_CMAR7 (STM32_DMA1_BASE + STM32_DMA_CMAR7_OFFSET) + +#define STM32_DMA2_ISRC (STM32_DMA2_BASE + STM32_DMA_ISR_OFFSET) +#define STM32_DMA2_IFCR (STM32_DMA2_BASE + STM32_DMA_IFCR_OFFSET) + +#define STM32_DMA2_CCR(n) (STM32_DMA2_BASE + STM32_DMA_CCR_OFFSET(n)) +#define STM32_DMA2_CCR1 (STM32_DMA2_BASE + STM32_DMA_CCR1_OFFSET) +#define STM32_DMA2_CCR2 (STM32_DMA2_BASE + STM32_DMA_CCR2_OFFSET) +#define STM32_DMA2_CCR3 (STM32_DMA2_BASE + STM32_DMA_CCR3_OFFSET) +#define STM32_DMA2_CCR4 (STM32_DMA2_BASE + STM32_DMA_CCR4_OFFSET) +#define STM32_DMA2_CCR5 (STM32_DMA2_BASE + STM32_DMA_CCR5_OFFSET) +#define STM32_DMA2_CCR6 (STM32_DMA2_BASE + STM32_DMA_CCR6_OFFSET) +#define STM32_DMA2_CCR7 (STM32_DMA2_BASE + STM32_DMA_CCR7_OFFSET) + +#define STM32_DMA2_CNDTR(n) (STM32_DMA2_BASE + STM32_DMA_CNDTR_OFFSET(n)) +#define STM32_DMA2_CNDTR1 (STM32_DMA2_BASE + STM32_DMA_CNDTR1_OFFSET) +#define STM32_DMA2_CNDTR2 (STM32_DMA2_BASE + STM32_DMA_CNDTR2_OFFSET) +#define STM32_DMA2_CNDTR3 (STM32_DMA2_BASE + STM32_DMA_CNDTR3_OFFSET) +#define STM32_DMA2_CNDTR4 (STM32_DMA2_BASE + STM32_DMA_CNDTR4_OFFSET) +#define STM32_DMA2_CNDTR5 (STM32_DMA2_BASE + STM32_DMA_CNDTR5_OFFSET) +#define STM32_DMA2_CNDTR6 (STM32_DMA2_BASE + STM32_DMA_CNDTR6_OFFSET) +#define STM32_DMA2_CNDTR7 (STM32_DMA2_BASE + STM32_DMA_CNDTR7_OFFSET) + +#define STM32_DMA2_CPAR(n) (STM32_DMA2_BASE + STM32_DMA_CPAR_OFFSET(n)) +#define STM32_DMA2_CPAR1 (STM32_DMA2_BASE + STM32_DMA_CPAR1_OFFSET) +#define STM32_DMA2_CPAR2 (STM32_DMA2_BASE + STM32_DMA_CPAR2_OFFSET) +#define STM32_DMA2_CPAR3 (STM32_DMA2_BASE + STM32_DMA_CPAR3_OFFSET) +#define STM32_DMA2_CPAR4 (STM32_DMA2_BASE + STM32_DMA_CPAR4_OFFSET) +#define STM32_DMA2_CPAR5 (STM32_DMA2_BASE + STM32_DMA_CPAR5_OFFSET) +#define STM32_DMA2_CPAR6 (STM32_DMA2_BASE + STM32_DMA_CPAR6_OFFSET) +#define STM32_DMA2_CPAR7 (STM32_DMA2_BASE + STM32_DMA_CPAR7_OFFSET) + +#define STM32_DMA2_CMAR(n) (STM32_DMA2_BASE + STM32_DMA_CMAR_OFFSET(n)) +#define STM32_DMA2_CMAR1 (STM32_DMA2_BASE + STM32_DMA_CMAR1_OFFSET) +#define STM32_DMA2_CMAR2 (STM32_DMA2_BASE + STM32_DMA_CMAR2_OFFSET) +#define STM32_DMA2_CMAR3 (STM32_DMA2_BASE + STM32_DMA_CMAR3_OFFSET) +#define STM32_DMA2_CMAR4 (STM32_DMA2_BASE + STM32_DMA_CMAR4_OFFSET) +#define STM32_DMA2_CMAR5 (STM32_DMA2_BASE + STM32_DMA_CMAR5_OFFSET) +#define STM32_DMA2_CMAR6 (STM32_DMA2_BASE + STM32_DMA_CMAR6_OFFSET) +#define STM32_DMA2_CMAR7 (STM32_DMA2_BASE + STM32_DMA_CMAR7_OFFSET) /* Register Bitfield Definitions ********************************************/ @@ -273,4 +273,4 @@ /* NOTE: DMA channel mapping is done through DMAMUX1. */ -#endif /* __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32WB_DMA_H */ +#endif /* __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32_DMA_H */ diff --git a/arch/arm/src/stm32wb/hardware/stm32wb_dmamux.h b/arch/arm/src/stm32wb/hardware/stm32wb_dmamux.h index f4a8b5d47c9e2..ee482f157df13 100644 --- a/arch/arm/src/stm32wb/hardware/stm32wb_dmamux.h +++ b/arch/arm/src/stm32wb/hardware/stm32wb_dmamux.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32WB_DMAMUX_H -#define __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32WB_DMAMUX_H +#ifndef __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32_DMAMUX_H +#define __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32_DMAMUX_H /**************************************************************************** * Included Files @@ -39,64 +39,65 @@ /* Register Offsets *********************************************************/ -#define STM32WB_DMAMUX_CXCR_OFFSET(x) (0x0000 + 0x0004 * (x)) /* DMAMUX1 request line multiplexer channel x configuration register */ -#define STM32WB_DMAMUX_C0CR_OFFSET STM32WB_DMAMUX_CXCR_OFFSET(0) -#define STM32WB_DMAMUX_C1CR_OFFSET STM32WB_DMAMUX_CXCR_OFFSET(1) -#define STM32WB_DMAMUX_C2CR_OFFSET STM32WB_DMAMUX_CXCR_OFFSET(2) -#define STM32WB_DMAMUX_C3CR_OFFSET STM32WB_DMAMUX_CXCR_OFFSET(3) -#define STM32WB_DMAMUX_C4CR_OFFSET STM32WB_DMAMUX_CXCR_OFFSET(4) -#define STM32WB_DMAMUX_C5CR_OFFSET STM32WB_DMAMUX_CXCR_OFFSET(5) -#define STM32WB_DMAMUX_C6CR_OFFSET STM32WB_DMAMUX_CXCR_OFFSET(6) -#define STM32WB_DMAMUX_C7CR_OFFSET STM32WB_DMAMUX_CXCR_OFFSET(7) -#define STM32WB_DMAMUX_C8CR_OFFSET STM32WB_DMAMUX_CXCR_OFFSET(8) -#define STM32WB_DMAMUX_C9CR_OFFSET STM32WB_DMAMUX_CXCR_OFFSET(9) -#define STM32WB_DMAMUX_C10CR_OFFSET STM32WB_DMAMUX_CXCR_OFFSET(10) -#define STM32WB_DMAMUX_C11CR_OFFSET STM32WB_DMAMUX_CXCR_OFFSET(11) -#define STM32WB_DMAMUX_C12CR_OFFSET STM32WB_DMAMUX_CXCR_OFFSET(12) -#define STM32WB_DMAMUX_C13CR_OFFSET STM32WB_DMAMUX_CXCR_OFFSET(13) - /* 0x034-0x07C: Reserved */ -#define STM32WB_DMAMUX_CSR_OFFSET 0x0080 /* DMAMUX1 request line multiplexer interrupt channel status register */ -#define STM32WB_DMAMUX_CFR_OFFSET 0x0084 /* DMAMUX1 request line multiplexer interrupt clear flag register */ - /* 0x088-0x0FC: Reserved */ - -#define STM32WB_DMAMUX_RGXCR_OFFSET(x) (0x0100 + 0x004 * (x)) /* DMAMUX1 request generator channel x configuration register */ -#define STM32WB_DMAMUX_RG0CR_OFFSET STM32WB_DMAMUX_RGXCR_OFFSET(0) -#define STM32WB_DMAMUX_RG1CR_OFFSET STM32WB_DMAMUX_RGXCR_OFFSET(1) -#define STM32WB_DMAMUX_RG2CR_OFFSET STM32WB_DMAMUX_RGXCR_OFFSET(2) -#define STM32WB_DMAMUX_RG3CR_OFFSET STM32WB_DMAMUX_RGXCR_OFFSET(3) -#define STM32WB_DMAMUX_RGSR_OFFSET 0x0140 /* DMAMUX1 request generator interrupt status register */ -#define STM32WB_DMAMUX_RGCFR_OFFSET 0x0144 /* DMAMUX1 request generator interrupt clear flag register */ - /* 0x148-0x3fc: Reserved */ +#define STM32_DMAMUX_CXCR_OFFSET(x) (0x0000 + 0x0004 * (x)) /* DMAMUX1 request line multiplexer channel x configuration register */ +#define STM32_DMAMUX_C0CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(0) +#define STM32_DMAMUX_C1CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(1) +#define STM32_DMAMUX_C2CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(2) +#define STM32_DMAMUX_C3CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(3) +#define STM32_DMAMUX_C4CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(4) +#define STM32_DMAMUX_C5CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(5) +#define STM32_DMAMUX_C6CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(6) +#define STM32_DMAMUX_C7CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(7) +#define STM32_DMAMUX_C8CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(8) +#define STM32_DMAMUX_C9CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(9) +#define STM32_DMAMUX_C10CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(10) +#define STM32_DMAMUX_C11CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(11) +#define STM32_DMAMUX_C12CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(12) +#define STM32_DMAMUX_C13CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(13) +/* 0x034-0x07C: Reserved */ + +#define STM32_DMAMUX_CSR_OFFSET 0x0080 /* DMAMUX1 request line multiplexer interrupt channel status register */ +#define STM32_DMAMUX_CFR_OFFSET 0x0084 /* DMAMUX1 request line multiplexer interrupt clear flag register */ + /* 0x088-0x0FC: Reserved */ + +#define STM32_DMAMUX_RGXCR_OFFSET(x) (0x0100 + 0x004 * (x)) /* DMAMUX1 request generator channel x configuration register */ +#define STM32_DMAMUX_RG0CR_OFFSET STM32_DMAMUX_RGXCR_OFFSET(0) +#define STM32_DMAMUX_RG1CR_OFFSET STM32_DMAMUX_RGXCR_OFFSET(1) +#define STM32_DMAMUX_RG2CR_OFFSET STM32_DMAMUX_RGXCR_OFFSET(2) +#define STM32_DMAMUX_RG3CR_OFFSET STM32_DMAMUX_RGXCR_OFFSET(3) +#define STM32_DMAMUX_RGSR_OFFSET 0x0140 /* DMAMUX1 request generator interrupt status register */ +#define STM32_DMAMUX_RGCFR_OFFSET 0x0144 /* DMAMUX1 request generator interrupt clear flag register */ + /* 0x148-0x3fc: Reserved */ /* Register Addresses *******************************************************/ -#define STM32WB_DMAMUX1_CXCR(x) (STM32WB_DMAMUX1_BASE + STM32WB_DMAMUX_CXCR_OFFSET(x)) -#define STM32WB_DMAMUX1_C0CR (STM32WB_DMAMUX1_BASE + STM32WB_DMAMUX_C0CR_OFFSET) -#define STM32WB_DMAMUX1_C1CR (STM32WB_DMAMUX1_BASE + STM32WB_DMAMUX_C1CR_OFFSET) -#define STM32WB_DMAMUX1_C2CR (STM32WB_DMAMUX1_BASE + STM32WB_DMAMUX_C2CR_OFFSET) -#define STM32WB_DMAMUX1_C3CR (STM32WB_DMAMUX1_BASE + STM32WB_DMAMUX_C3CR_OFFSET) -#define STM32WB_DMAMUX1_C4CR (STM32WB_DMAMUX1_BASE + STM32WB_DMAMUX_C4CR_OFFSET) -#define STM32WB_DMAMUX1_C5CR (STM32WB_DMAMUX1_BASE + STM32WB_DMAMUX_C5CR_OFFSET) -#define STM32WB_DMAMUX1_C6CR (STM32WB_DMAMUX1_BASE + STM32WB_DMAMUX_C6CR_OFFSET) -#define STM32WB_DMAMUX1_C7CR (STM32WB_DMAMUX1_BASE + STM32WB_DMAMUX_C7CR_OFFSET) -#define STM32WB_DMAMUX1_C8CR (STM32WB_DMAMUX1_BASE + STM32WB_DMAMUX_C8CR_OFFSET) -#define STM32WB_DMAMUX1_C9CR (STM32WB_DMAMUX1_BASE + STM32WB_DMAMUX_C9CR_OFFSET) -#define STM32WB_DMAMUX1_C10CR (STM32WB_DMAMUX1_BASE + STM32WB_DMAMUX_C10CR_OFFSET) -#define STM32WB_DMAMUX1_C11CR (STM32WB_DMAMUX1_BASE + STM32WB_DMAMUX_C11CR_OFFSET) -#define STM32WB_DMAMUX1_C12CR (STM32WB_DMAMUX1_BASE + STM32WB_DMAMUX_C12CR_OFFSET) -#define STM32WB_DMAMUX1_C13CR (STM32WB_DMAMUX1_BASE + STM32WB_DMAMUX_C13CR_OFFSET) - -#define STM32WB_DMAMUX1_CSR (STM32WB_DMAMUX1_BASE + STM32WB_DMAMUX_CSR_OFFSET) -#define STM32WB_DMAMUX1_CFR (STM32WB_DMAMUX1_BASE + STM32WB_DMAMUX_CFR_OFFSET) - -#define STM32WB_DMAMUX1_RGXCR(x) (STM32WB_DMAMUX1_BASE + STM32WB_DMAMUX_RGXCR_OFFSET(x)) -#define STM32WB_DMAMUX1_RG0CR (STM32WB_DMAMUX1_BASE + STM32WB_DMAMUX_RG0CR_OFFSET) -#define STM32WB_DMAMUX1_RG1CR (STM32WB_DMAMUX1_BASE + STM32WB_DMAMUX_RG1CR_OFFSET) -#define STM32WB_DMAMUX1_RG2CR (STM32WB_DMAMUX1_BASE + STM32WB_DMAMUX_RG2CR_OFFSET) -#define STM32WB_DMAMUX1_RG3CR (STM32WB_DMAMUX1_BASE + STM32WB_DMAMUX_RG3CR_OFFSET) - -#define STM32WB_DMAMUX1_RGSR (STM32WB_DMAMUX1_BASE + STM32WB_DMAMUX_RGSR_OFFSET) -#define STM32WB_DMAMUX1_RGCFR (STM32WB_DMAMUX1_BASE + STM32WB_DMAMUX_RGCFR_OFFSET) +#define STM32_DMAMUX1_CXCR(x) (STM32_DMAMUX1_BASE + STM32_DMAMUX_CXCR_OFFSET(x)) +#define STM32_DMAMUX1_C0CR (STM32_DMAMUX1_BASE + STM32_DMAMUX_C0CR_OFFSET) +#define STM32_DMAMUX1_C1CR (STM32_DMAMUX1_BASE + STM32_DMAMUX_C1CR_OFFSET) +#define STM32_DMAMUX1_C2CR (STM32_DMAMUX1_BASE + STM32_DMAMUX_C2CR_OFFSET) +#define STM32_DMAMUX1_C3CR (STM32_DMAMUX1_BASE + STM32_DMAMUX_C3CR_OFFSET) +#define STM32_DMAMUX1_C4CR (STM32_DMAMUX1_BASE + STM32_DMAMUX_C4CR_OFFSET) +#define STM32_DMAMUX1_C5CR (STM32_DMAMUX1_BASE + STM32_DMAMUX_C5CR_OFFSET) +#define STM32_DMAMUX1_C6CR (STM32_DMAMUX1_BASE + STM32_DMAMUX_C6CR_OFFSET) +#define STM32_DMAMUX1_C7CR (STM32_DMAMUX1_BASE + STM32_DMAMUX_C7CR_OFFSET) +#define STM32_DMAMUX1_C8CR (STM32_DMAMUX1_BASE + STM32_DMAMUX_C8CR_OFFSET) +#define STM32_DMAMUX1_C9CR (STM32_DMAMUX1_BASE + STM32_DMAMUX_C9CR_OFFSET) +#define STM32_DMAMUX1_C10CR (STM32_DMAMUX1_BASE + STM32_DMAMUX_C10CR_OFFSET) +#define STM32_DMAMUX1_C11CR (STM32_DMAMUX1_BASE + STM32_DMAMUX_C11CR_OFFSET) +#define STM32_DMAMUX1_C12CR (STM32_DMAMUX1_BASE + STM32_DMAMUX_C12CR_OFFSET) +#define STM32_DMAMUX1_C13CR (STM32_DMAMUX1_BASE + STM32_DMAMUX_C13CR_OFFSET) + +#define STM32_DMAMUX1_CSR (STM32_DMAMUX1_BASE + STM32_DMAMUX_CSR_OFFSET) +#define STM32_DMAMUX1_CFR (STM32_DMAMUX1_BASE + STM32_DMAMUX_CFR_OFFSET) + +#define STM32_DMAMUX1_RGXCR(x) (STM32_DMAMUX1_BASE + STM32_DMAMUX_RGXCR_OFFSET(x)) +#define STM32_DMAMUX1_RG0CR (STM32_DMAMUX1_BASE + STM32_DMAMUX_RG0CR_OFFSET) +#define STM32_DMAMUX1_RG1CR (STM32_DMAMUX1_BASE + STM32_DMAMUX_RG1CR_OFFSET) +#define STM32_DMAMUX1_RG2CR (STM32_DMAMUX1_BASE + STM32_DMAMUX_RG2CR_OFFSET) +#define STM32_DMAMUX1_RG3CR (STM32_DMAMUX1_BASE + STM32_DMAMUX_RG3CR_OFFSET) + +#define STM32_DMAMUX1_RGSR (STM32_DMAMUX1_BASE + STM32_DMAMUX_RGSR_OFFSET) +#define STM32_DMAMUX1_RGCFR (STM32_DMAMUX1_BASE + STM32_DMAMUX_RGCFR_OFFSET) /* Register Bitfield Definitions ********************************************/ @@ -283,4 +284,4 @@ #define DMAMAP_AES2_OUT_0 DMAMAP_MAP(DMA1, DMAMUX1_AES2_OUT) #define DMAMAP_AES2_OUT_1 DMAMAP_MAP(DMA2, DMAMUX1_AES2_OUT) -#endif /* __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32WB_DMAMUX_H */ +#endif /* __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32_DMAMUX_H */ diff --git a/arch/arm/src/stm32wb/hardware/stm32wb_exti.h b/arch/arm/src/stm32wb/hardware/stm32wb_exti.h index 1169438501b3d..959c7e682c5b1 100644 --- a/arch/arm/src/stm32wb/hardware/stm32wb_exti.h +++ b/arch/arm/src/stm32wb/hardware/stm32wb_exti.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32WB_EXTI_H -#define __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32WB_EXTI_H +#ifndef __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32_EXTI_H +#define __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32_EXTI_H /**************************************************************************** * Included Files @@ -36,41 +36,41 @@ /* Register Offsets *********************************************************/ -#define STM32WB_EXTI_RTSR1_OFFSET 0x0000 /* Rising trigger selection register 1 */ -#define STM32WB_EXTI_FTSR1_OFFSET 0x0004 /* Falling trigger selection register 1 */ -#define STM32WB_EXTI_SWIER1_OFFSET 0x0008 /* Software interrupt event register 1 */ -#define STM32WB_EXTI_PR1_OFFSET 0x000c /* Pending register 1 */ -#define STM32WB_EXTI_RTSR2_OFFSET 0x0020 /* Rising trigger selection register 2 */ -#define STM32WB_EXTI_FTSR2_OFFSET 0x0024 /* Falling trigger selection register 2 */ -#define STM32WB_EXTI_SWIER2_OFFSET 0x0028 /* Software interrupt event register 2 */ -#define STM32WB_EXTI_PR2_OFFSET 0x002c /* Pending register 2 */ -#define STM32WB_EXTI_C1IMR1_OFFSET 0x0080 /* CPU1 wakeup with interrupt mask register 1 */ -#define STM32WB_EXTI_C1EMR1_OFFSET 0x0084 /* CPU1 wakeup with event mask register 1 */ -#define STM32WB_EXTI_C1IMR2_OFFSET 0x0090 /* CPU1 wakeup with interrupt mask register 2 */ -#define STM32WB_EXTI_C1EMR2_OFFSET 0x0094 /* CPU1 wakeup with event mask register 2 */ -#define STM32WB_EXTI_C2IMR1_OFFSET 0x00c0 /* CPU2 wakeup with interrupt mask register 1 */ -#define STM32WB_EXTI_C2EMR1_OFFSET 0x00c4 /* CPU2 wakeup with event mask register 1 */ -#define STM32WB_EXTI_C2IMR2_OFFSET 0x00d0 /* CPU2 wakeup with interrupt mask register 2 */ -#define STM32WB_EXTI_C2EMR2_OFFSET 0x00d4 /* CPU2 wakeup with event mask register 2 */ +#define STM32_EXTI_RTSR1_OFFSET 0x0000 /* Rising trigger selection register 1 */ +#define STM32_EXTI_FTSR1_OFFSET 0x0004 /* Falling trigger selection register 1 */ +#define STM32_EXTI_SWIER1_OFFSET 0x0008 /* Software interrupt event register 1 */ +#define STM32_EXTI_PR1_OFFSET 0x000c /* Pending register 1 */ +#define STM32_EXTI_RTSR2_OFFSET 0x0020 /* Rising trigger selection register 2 */ +#define STM32_EXTI_FTSR2_OFFSET 0x0024 /* Falling trigger selection register 2 */ +#define STM32_EXTI_SWIER2_OFFSET 0x0028 /* Software interrupt event register 2 */ +#define STM32_EXTI_PR2_OFFSET 0x002c /* Pending register 2 */ +#define STM32_EXTI_C1IMR1_OFFSET 0x0080 /* CPU1 wakeup with interrupt mask register 1 */ +#define STM32_EXTI_C1EMR1_OFFSET 0x0084 /* CPU1 wakeup with event mask register 1 */ +#define STM32_EXTI_C1IMR2_OFFSET 0x0090 /* CPU1 wakeup with interrupt mask register 2 */ +#define STM32_EXTI_C1EMR2_OFFSET 0x0094 /* CPU1 wakeup with event mask register 2 */ +#define STM32_EXTI_C2IMR1_OFFSET 0x00c0 /* CPU2 wakeup with interrupt mask register 1 */ +#define STM32_EXTI_C2EMR1_OFFSET 0x00c4 /* CPU2 wakeup with event mask register 1 */ +#define STM32_EXTI_C2IMR2_OFFSET 0x00d0 /* CPU2 wakeup with interrupt mask register 2 */ +#define STM32_EXTI_C2EMR2_OFFSET 0x00d4 /* CPU2 wakeup with event mask register 2 */ /* Register Addresses *******************************************************/ -#define STM32WB_EXTI_RTSR1 (STM32WB_EXTI_BASE + STM32WB_EXTI_RTSR1_OFFSET) -#define STM32WB_EXTI_FTSR1 (STM32WB_EXTI_BASE + STM32WB_EXTI_FTSR1_OFFSET) -#define STM32WB_EXTI_SWIER1 (STM32WB_EXTI_BASE + STM32WB_EXTI_SWIER1_OFFSET) -#define STM32WB_EXTI_PR1 (STM32WB_EXTI_BASE + STM32WB_EXTI_PR1_OFFSET) -#define STM32WB_EXTI_RTSR2 (STM32WB_EXTI_BASE + STM32WB_EXTI_RTSR2_OFFSET) -#define STM32WB_EXTI_FTSR2 (STM32WB_EXTI_BASE + STM32WB_EXTI_FTSR2_OFFSET) -#define STM32WB_EXTI_SWIER2 (STM32WB_EXTI_BASE + STM32WB_EXTI_SWIER2_OFFSET) -#define STM32WB_EXTI_PR2 (STM32WB_EXTI_BASE + STM32WB_EXTI_PR2_OFFSET) -#define STM32WB_EXTI_C1IMR1 (STM32WB_EXTI_BASE + STM32WB_EXTI_C1IMR1_OFFSET) -#define STM32WB_EXTI_C1EMR1 (STM32WB_EXTI_BASE + STM32WB_EXTI_C1EMR1_OFFSET) -#define STM32WB_EXTI_C1IMR2 (STM32WB_EXTI_BASE + STM32WB_EXTI_C1IMR2_OFFSET) -#define STM32WB_EXTI_C1EMR2 (STM32WB_EXTI_BASE + STM32WB_EXTI_C1EMR2_OFFSET) -#define STM32WB_EXTI_C2IMR1 (STM32WB_EXTI_BASE + STM32WB_EXTI_C2IMR1_OFFSET) -#define STM32WB_EXTI_C2EMR1 (STM32WB_EXTI_BASE + STM32WB_EXTI_C2EMR1_OFFSET) -#define STM32WB_EXTI_C2IMR2 (STM32WB_EXTI_BASE + STM32WB_EXTI_C2IMR2_OFFSET) -#define STM32WB_EXTI_C2EMR2 (STM32WB_EXTI_BASE + STM32WB_EXTI_C2EMR2_OFFSET) +#define STM32_EXTI_RTSR1 (STM32_EXTI_BASE + STM32_EXTI_RTSR1_OFFSET) +#define STM32_EXTI_FTSR1 (STM32_EXTI_BASE + STM32_EXTI_FTSR1_OFFSET) +#define STM32_EXTI_SWIER1 (STM32_EXTI_BASE + STM32_EXTI_SWIER1_OFFSET) +#define STM32_EXTI_PR1 (STM32_EXTI_BASE + STM32_EXTI_PR1_OFFSET) +#define STM32_EXTI_RTSR2 (STM32_EXTI_BASE + STM32_EXTI_RTSR2_OFFSET) +#define STM32_EXTI_FTSR2 (STM32_EXTI_BASE + STM32_EXTI_FTSR2_OFFSET) +#define STM32_EXTI_SWIER2 (STM32_EXTI_BASE + STM32_EXTI_SWIER2_OFFSET) +#define STM32_EXTI_PR2 (STM32_EXTI_BASE + STM32_EXTI_PR2_OFFSET) +#define STM32_EXTI_C1IMR1 (STM32_EXTI_BASE + STM32_EXTI_C1IMR1_OFFSET) +#define STM32_EXTI_C1EMR1 (STM32_EXTI_BASE + STM32_EXTI_C1EMR1_OFFSET) +#define STM32_EXTI_C1IMR2 (STM32_EXTI_BASE + STM32_EXTI_C1IMR2_OFFSET) +#define STM32_EXTI_C1EMR2 (STM32_EXTI_BASE + STM32_EXTI_C1EMR2_OFFSET) +#define STM32_EXTI_C2IMR1 (STM32_EXTI_BASE + STM32_EXTI_C2IMR1_OFFSET) +#define STM32_EXTI_C2EMR1 (STM32_EXTI_BASE + STM32_EXTI_C2EMR1_OFFSET) +#define STM32_EXTI_C2IMR2 (STM32_EXTI_BASE + STM32_EXTI_C2IMR2_OFFSET) +#define STM32_EXTI_C2EMR2 (STM32_EXTI_BASE + STM32_EXTI_C2EMR2_OFFSET) /* Register Bitfield Definitions ********************************************/ @@ -167,4 +167,4 @@ #define EXTI_C2EMR2_EM(n) (1 << ((n) & 31)) /* CPU2 Event mask on line n = 40, 41 */ #define EXTI_C2EMR2_MASK 0x00000300 -#endif /* __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32WB_EXTI_H */ +#endif /* __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32_EXTI_H */ diff --git a/arch/arm/src/stm32wb/hardware/stm32wb_flash.h b/arch/arm/src/stm32wb/hardware/stm32wb_flash.h index 8f2fe45b9dd27..ee55e17fd9acd 100644 --- a/arch/arm/src/stm32wb/hardware/stm32wb_flash.h +++ b/arch/arm/src/stm32wb/hardware/stm32wb_flash.h @@ -35,10 +35,10 @@ /* Flash size is known from the chip selection: * - * When CONFIG_STM32WB_FLASH_OVERRIDE_DEFAULT is set the - * CONFIG_STM32WB_FLASH_CONFIG_x selects the default FLASH size based on + * When CONFIG_STM32_FLASH_OVERRIDE_DEFAULT is set the + * CONFIG_STM32_FLASH_CONFIG_x selects the default FLASH size based on * the chip part number. This value can be overridden with - * CONFIG_STM32WB_FLASH_OVERRIDE_x + * CONFIG_STM32_FLASH_OVERRIDE_x * * Parts STM32WB3xxC have 256Kb of FLASH * Parts STM32WB5xxC have 256Kb of FLASH @@ -50,104 +50,104 @@ * N.B. Only Single bank mode is supported */ -#if !defined(CONFIG_STM32WB_FLASH_OVERRIDE_DEFAULT) && \ - !defined(CONFIG_STM32WB_FLASH_OVERRIDE_C_256) && \ - !defined(CONFIG_STM32WB_FLASH_OVERRIDE_C_320) && \ - !defined(CONFIG_STM32WB_FLASH_OVERRIDE_E_512) && \ - !defined(CONFIG_STM32WB_FLASH_OVERRIDE_Y_640) && \ - !defined(CONFIG_STM32WB_FLASH_OVERRIDE_G_1024) && \ - !defined(CONFIG_STM32WB_FLASH_CONFIG_C_256) && \ - !defined(CONFIG_STM32WB_FLASH_CONFIG_C_320) && \ - !defined(CONFIG_STM32WB_FLASH_CONFIG_E_512) && \ - !defined(CONFIG_STM32WB_FLASH_CONFIG_Y_640) && \ - !defined(CONFIG_STM32WB_FLASH_CONFIG_G_1024) +#if !defined(CONFIG_STM32_FLASH_OVERRIDE_DEFAULT) && \ + !defined(CONFIG_STM32_FLASH_OVERRIDE_C) && \ + !defined(CONFIG_STM32_FLASH_OVERRIDE_C_320) && \ + !defined(CONFIG_STM32_FLASH_OVERRIDE_E) && \ + !defined(CONFIG_STM32_FLASH_OVERRIDE_Y) && \ + !defined(CONFIG_STM32_FLASH_OVERRIDE_G) && \ + !defined(CONFIG_STM32_FLASH_CONFIG_C) && \ + !defined(CONFIG_STM32_FLASH_CONFIG_C_320) && \ + !defined(CONFIG_STM32_FLASH_CONFIG_E) && \ + !defined(CONFIG_STM32_FLASH_CONFIG_Y) && \ + !defined(CONFIG_STM32_FLASH_CONFIG_G) # error "Flash size not defined" #endif /* Override of the Flash has been chosen */ -#if !defined(CONFIG_STM32WB_FLASH_OVERRIDE_DEFAULT) -# undef CONFIG_STM32WB_FLASH_CONFIG_C_256 -# undef CONFIG_STM32WB_FLASH_CONFIG_C_320 -# undef CONFIG_STM32WB_FLASH_CONFIG_E_512 -# undef CONFIG_STM32WB_FLASH_CONFIG_Y_640 -# undef CONFIG_STM32WB_FLASH_CONFIG_G_1024 -# if defined(CONFIG_STM32WB_FLASH_OVERRIDE_C_256) -# define CONFIG_STM32WB_FLASH_CONFIG_C_256 -# elif defined(CONFIG_STM32WB_FLASH_OVERRIDE_C_320) -# define CONFIG_STM32WB_FLASH_CONFIG_C_320 -# elif defined(CONFIG_STM32WB_FLASH_OVERRIDE_E_512) -# define CONFIG_STM32WB_FLASH_CONFIG_E_512 -# elif defined(CONFIG_STM32WB_FLASH_OVERRIDE_Y_640) -# define CONFIG_STM32WB_FLASH_CONFIG_Y_640 -# elif defined(CONFIG_STM32WB_FLASH_OVERRIDE_G_1024) -# define CONFIG_STM32WB_FLASH_CONFIG_G_1024 +#if !defined(CONFIG_STM32_FLASH_OVERRIDE_DEFAULT) +# undef CONFIG_STM32_FLASH_CONFIG_C +# undef CONFIG_STM32_FLASH_CONFIG_C_320 +# undef CONFIG_STM32_FLASH_CONFIG_E +# undef CONFIG_STM32_FLASH_CONFIG_Y +# undef CONFIG_STM32_FLASH_CONFIG_G +# if defined(CONFIG_STM32_FLASH_OVERRIDE_C) +# define CONFIG_STM32_FLASH_CONFIG_C +# elif defined(CONFIG_STM32_FLASH_OVERRIDE_C_320) +# define CONFIG_STM32_FLASH_CONFIG_C_320 +# elif defined(CONFIG_STM32_FLASH_OVERRIDE_E) +# define CONFIG_STM32_FLASH_CONFIG_E +# elif defined(CONFIG_STM32_FLASH_OVERRIDE_Y) +# define CONFIG_STM32_FLASH_CONFIG_Y +# elif defined(CONFIG_STM32_FLASH_OVERRIDE_G) +# define CONFIG_STM32_FLASH_CONFIG_G # endif #endif /* Define the valid configuration */ -#define STM32WB_FLASH_PAGESIZE 4096 - -#if defined(CONFIG_STM32WB_FLASH_CONFIG_C_256) /* 256 kB */ -# define STM32WB_FLASH_NPAGES 64 -#elif defined(CONFIG_STM32WB_FLASH_CONFIG_C_320) /* 320 kB */ -# define STM32WB_FLASH_NPAGES 80 -#elif defined(CONFIG_STM32WB_FLASH_CONFIG_E_512) /* 512 kB */ -# define STM32WB_FLASH_NPAGES 128 -#elif defined(CONFIG_STM32WB_FLASH_CONFIG_Y_640) /* 640 kB */ -# define STM32WB_FLASH_NPAGES 160 -#elif defined(CONFIG_STM32WB_FLASH_CONFIG_G_1024) /* 1 MB */ -# define STM32WB_FLASH_NPAGES 256 +#define STM32_FLASH_PAGESIZE 4096 + +#if defined(CONFIG_STM32_FLASH_CONFIG_C) /* 256 kB */ +# define STM32_FLASH_NPAGES 64 +#elif defined(CONFIG_STM32_FLASH_CONFIG_C_320) /* 320 kB */ +# define STM32_FLASH_NPAGES 80 +#elif defined(CONFIG_STM32_FLASH_CONFIG_E) /* 512 kB */ +# define STM32_FLASH_NPAGES 128 +#elif defined(CONFIG_STM32_FLASH_CONFIG_Y) /* 640 kB */ +# define STM32_FLASH_NPAGES 160 +#elif defined(CONFIG_STM32_FLASH_CONFIG_G) /* 1 MB */ +# define STM32_FLASH_NPAGES 256 #else # error "Unknown flash configuration!" #endif -#define STM32WB_FLASH_SIZE (STM32WB_FLASH_NPAGES * STM32WB_FLASH_PAGESIZE) +#define STM32_FLASH_SIZE (STM32_FLASH_NPAGES * STM32_FLASH_PAGESIZE) /* Register Offsets *********************************************************/ -#define STM32WB_FLASH_ACR_OFFSET 0x0000 /* Flash Access Control Register */ -#define STM32WB_FLASH_KEYR_OFFSET 0x0008 /* Flash Key Register */ -#define STM32WB_FLASH_OPTKEYR_OFFSET 0x000c /* Flash Option Key Register */ -#define STM32WB_FLASH_SR_OFFSET 0x0010 /* Flash Status Register */ -#define STM32WB_FLASH_CR_OFFSET 0x0014 /* Flash Control Register */ -#define STM32WB_FLASH_ECCR_OFFSET 0x0018 /* Flash ECC Register */ -#define STM32WB_FLASH_OPTR_OFFSET 0x0020 /* Flash Option Register */ -#define STM32WB_FLASH_PCROP1ASR_OFFSET 0x0024 /* Flash PCROP zone A Start address Register */ -#define STM32WB_FLASH_PCROP1AER_OFFSET 0x0028 /* Flash PCROP zone A End address Register */ -#define STM32WB_FLASH_WRP1AR_OFFSET 0x002c /* Flash WRP area A Address Register */ -#define STM32WB_FLASH_WRP1BR_OFFSET 0x0030 /* Flash WRP area B Address Register */ -#define STM32WB_FLASH_PCROP1BSR_OFFSET 0x0034 /* Flash PCROP zone B Start address Register */ -#define STM32WB_FLASH_PCROP1BER_OFFSET 0x0038 /* Flash PCROP zone B End address Register */ -#define STM32WB_FLASH_IPCCBR_OFFSET 0x003C /* Flash IPCC mailbox data buffer address Register */ -#define STM32WB_FLASH_C2ACR_OFFSET 0x005C /* CPU2 flash Access Control Register */ -#define STM32WB_FLASH_C2SR_OFFSET 0x0060 /* CPU2 flash Status Register */ -#define STM32WB_FLASH_C2CR_OFFSET 0x0064 /* CPU2 flash Control Register */ -#define STM32WB_FLASH_SFR_OFFSET 0x0080 /* Secure Flash start address Register */ -#define STM32WB_FLASH_SRRVR_OFFSET 0x0084 /* SRAM2 start address and CPU2 Reset Vector Register */ +#define STM32_FLASH_ACR_OFFSET 0x0000 /* Flash Access Control Register */ +#define STM32_FLASH_KEYR_OFFSET 0x0008 /* Flash Key Register */ +#define STM32_FLASH_OPTKEYR_OFFSET 0x000c /* Flash Option Key Register */ +#define STM32_FLASH_SR_OFFSET 0x0010 /* Flash Status Register */ +#define STM32_FLASH_CR_OFFSET 0x0014 /* Flash Control Register */ +#define STM32_FLASH_ECCR_OFFSET 0x0018 /* Flash ECC Register */ +#define STM32_FLASH_OPTR_OFFSET 0x0020 /* Flash Option Register */ +#define STM32_FLASH_PCROP1ASR_OFFSET 0x0024 /* Flash PCROP zone A Start address Register */ +#define STM32_FLASH_PCROP1AER_OFFSET 0x0028 /* Flash PCROP zone A End address Register */ +#define STM32_FLASH_WRP1AR_OFFSET 0x002c /* Flash WRP area A Address Register */ +#define STM32_FLASH_WRP1BR_OFFSET 0x0030 /* Flash WRP area B Address Register */ +#define STM32_FLASH_PCROP1BSR_OFFSET 0x0034 /* Flash PCROP zone B Start address Register */ +#define STM32_FLASH_PCROP1BER_OFFSET 0x0038 /* Flash PCROP zone B End address Register */ +#define STM32_FLASH_IPCCBR_OFFSET 0x003C /* Flash IPCC mailbox data buffer address Register */ +#define STM32_FLASH_C2ACR_OFFSET 0x005C /* CPU2 flash Access Control Register */ +#define STM32_FLASH_C2SR_OFFSET 0x0060 /* CPU2 flash Status Register */ +#define STM32_FLASH_C2CR_OFFSET 0x0064 /* CPU2 flash Control Register */ +#define STM32_FLASH_SFR_OFFSET 0x0080 /* Secure Flash start address Register */ +#define STM32_FLASH_SRRVR_OFFSET 0x0084 /* SRAM2 start address and CPU2 Reset Vector Register */ /* Register Addresses *******************************************************/ -#define STM32WB_FLASH_ACR (STM32WB_FLASHREG_BASE + STM32WB_FLASH_ACR_OFFSET) -#define STM32WB_FLASH_KEYR (STM32WB_FLASHREG_BASE + STM32WB_FLASH_KEYR_OFFSET) -#define STM32WB_FLASH_OPTKEYR (STM32WB_FLASHREG_BASE + STM32WB_FLASH_OPTKEYR_OFFSET) -#define STM32WB_FLASH_SR (STM32WB_FLASHREG_BASE + STM32WB_FLASH_SR_OFFSET) -#define STM32WB_FLASH_CR (STM32WB_FLASHREG_BASE + STM32WB_FLASH_CR_OFFSET) -#define STM32WB_FLASH_ECCR (STM32WB_FLASHREG_BASE + STM32WB_FLASH_ECCR_OFFSET) -#define STM32WB_FLASH_OPTR (STM32WB_FLASHREG_BASE + STM32WB_FLASH_OPTR_OFFSET) -#define STM32WB_FLASH_PCROP1ASR (STM32WB_FLASHREG_BASE + STM32WB_FLASH_PCROP1ASR_OFFSET) -#define STM32WB_FLASH_PCROP1AER (STM32WB_FLASHREG_BASE + STM32WB_FLASH_PCROP1AER_OFFSET) -#define STM32WB_FLASH_WRP1AR (STM32WB_FLASHREG_BASE + STM32WB_FLASH_WRP1AR_OFFSET) -#define STM32WB_FLASH_WRP1BR (STM32WB_FLASHREG_BASE + STM32WB_FLASH_WRP1BR_OFFSET) -#define STM32WB_FLASH_PCROP1BSR (STM32WB_FLASHREG_BASE + STM32WB_FLASH_PCROP1BSR_OFFSET) -#define STM32WB_FLASH_PCROP1BER (STM32WB_FLASHREG_BASE + STM32WB_FLASH_PCROP1BER_OFFSET) -#define STM32WB_FLASH_IPCCBR (STM32WB_FLASHREG_BASE + STM32WB_FLASH_IPCCBR_OFFSET) -#define STM32WB_FLASH_C2ACR (STM32WB_FLASHREG_BASE + STM32WB_FLASH_C2ACR_OFFSET) -#define STM32WB_FLASH_C2SR (STM32WB_FLASHREG_BASE + STM32WB_FLASH_C2SR_OFFSET) -#define STM32WB_FLASH_C2CR (STM32WB_FLASHREG_BASE + STM32WB_FLASH_C2CR_OFFSET) -#define STM32WB_FLASH_SFR (STM32WB_FLASHREG_BASE + STM32WB_FLASH_SFR_OFFSET) -#define STM32WB_FLASH_SRRVR (STM32WB_FLASHREG_BASE + STM32WB_FLASH_SRRVR_OFFSET) +#define STM32_FLASH_ACR (STM32_FLASHREG_BASE + STM32_FLASH_ACR_OFFSET) +#define STM32_FLASH_KEYR (STM32_FLASHREG_BASE + STM32_FLASH_KEYR_OFFSET) +#define STM32_FLASH_OPTKEYR (STM32_FLASHREG_BASE + STM32_FLASH_OPTKEYR_OFFSET) +#define STM32_FLASH_SR (STM32_FLASHREG_BASE + STM32_FLASH_SR_OFFSET) +#define STM32_FLASH_CR (STM32_FLASHREG_BASE + STM32_FLASH_CR_OFFSET) +#define STM32_FLASH_ECCR (STM32_FLASHREG_BASE + STM32_FLASH_ECCR_OFFSET) +#define STM32_FLASH_OPTR (STM32_FLASHREG_BASE + STM32_FLASH_OPTR_OFFSET) +#define STM32_FLASH_PCROP1ASR (STM32_FLASHREG_BASE + STM32_FLASH_PCROP1ASR_OFFSET) +#define STM32_FLASH_PCROP1AER (STM32_FLASHREG_BASE + STM32_FLASH_PCROP1AER_OFFSET) +#define STM32_FLASH_WRP1AR (STM32_FLASHREG_BASE + STM32_FLASH_WRP1AR_OFFSET) +#define STM32_FLASH_WRP1BR (STM32_FLASHREG_BASE + STM32_FLASH_WRP1BR_OFFSET) +#define STM32_FLASH_PCROP1BSR (STM32_FLASHREG_BASE + STM32_FLASH_PCROP1BSR_OFFSET) +#define STM32_FLASH_PCROP1BER (STM32_FLASHREG_BASE + STM32_FLASH_PCROP1BER_OFFSET) +#define STM32_FLASH_IPCCBR (STM32_FLASHREG_BASE + STM32_FLASH_IPCCBR_OFFSET) +#define STM32_FLASH_C2ACR (STM32_FLASHREG_BASE + STM32_FLASH_C2ACR_OFFSET) +#define STM32_FLASH_C2SR (STM32_FLASHREG_BASE + STM32_FLASH_C2SR_OFFSET) +#define STM32_FLASH_C2CR (STM32_FLASHREG_BASE + STM32_FLASH_C2CR_OFFSET) +#define STM32_FLASH_SFR (STM32_FLASHREG_BASE + STM32_FLASH_SFR_OFFSET) +#define STM32_FLASH_SRRVR (STM32_FLASHREG_BASE + STM32_FLASH_SRRVR_OFFSET) /* Register Bitfield Definitions ********************************************/ diff --git a/arch/arm/src/stm32wb/hardware/stm32wb_gpio.h b/arch/arm/src/stm32wb/hardware/stm32wb_gpio.h index cc3b862168732..180972f07a7bb 100644 --- a/arch/arm/src/stm32wb/hardware/stm32wb_gpio.h +++ b/arch/arm/src/stm32wb/hardware/stm32wb_gpio.h @@ -29,93 +29,93 @@ /* Register Offsets *********************************************************/ -#define STM32WB_GPIO_MODER_OFFSET 0x0000 /* GPIO port mode register */ -#define STM32WB_GPIO_OTYPER_OFFSET 0x0004 /* GPIO port output type register */ -#define STM32WB_GPIO_OSPEED_OFFSET 0x0008 /* GPIO port output speed register */ -#define STM32WB_GPIO_PUPDR_OFFSET 0x000c /* GPIO port pull-up/pull-down register */ -#define STM32WB_GPIO_IDR_OFFSET 0x0010 /* GPIO port input data register */ -#define STM32WB_GPIO_ODR_OFFSET 0x0014 /* GPIO port output data register */ -#define STM32WB_GPIO_BSRR_OFFSET 0x0018 /* GPIO port bit set/reset register */ -#define STM32WB_GPIO_LCKR_OFFSET 0x001c /* GPIO port configuration lock register */ -#define STM32WB_GPIO_AFRL_OFFSET 0x0020 /* GPIO alternate function low register */ -#define STM32WB_GPIO_AFRH_OFFSET 0x0024 /* GPIO alternate function high register */ -#define STM32WB_GPIO_BRR_OFFSET 0x0028 /* GPIO port bit reset register */ +#define STM32_GPIO_MODER_OFFSET 0x0000 /* GPIO port mode register */ +#define STM32_GPIO_OTYPER_OFFSET 0x0004 /* GPIO port output type register */ +#define STM32_GPIO_OSPEED_OFFSET 0x0008 /* GPIO port output speed register */ +#define STM32_GPIO_PUPDR_OFFSET 0x000c /* GPIO port pull-up/pull-down register */ +#define STM32_GPIO_IDR_OFFSET 0x0010 /* GPIO port input data register */ +#define STM32_GPIO_ODR_OFFSET 0x0014 /* GPIO port output data register */ +#define STM32_GPIO_BSRR_OFFSET 0x0018 /* GPIO port bit set/reset register */ +#define STM32_GPIO_LCKR_OFFSET 0x001c /* GPIO port configuration lock register */ +#define STM32_GPIO_AFRL_OFFSET 0x0020 /* GPIO alternate function low register */ +#define STM32_GPIO_AFRH_OFFSET 0x0024 /* GPIO alternate function high register */ +#define STM32_GPIO_BRR_OFFSET 0x0028 /* GPIO port bit reset register */ /* Register Addresses *******************************************************/ -#define STM32WB_GPIOA_MODER (STM32WB_GPIOA_BASE + STM32WB_GPIO_MODER_OFFSET) -#define STM32WB_GPIOA_OTYPER (STM32WB_GPIOA_BASE + STM32WB_GPIO_OTYPER_OFFSET) -#define STM32WB_GPIOA_OSPEED (STM32WB_GPIOA_BASE + STM32WB_GPIO_OSPEED_OFFSET) -#define STM32WB_GPIOA_PUPDR (STM32WB_GPIOA_BASE + STM32WB_GPIO_PUPDR_OFFSET) -#define STM32WB_GPIOA_IDR (STM32WB_GPIOA_BASE + STM32WB_GPIO_IDR_OFFSET) -#define STM32WB_GPIOA_ODR (STM32WB_GPIOA_BASE + STM32WB_GPIO_ODR_OFFSET) -#define STM32WB_GPIOA_BSRR (STM32WB_GPIOA_BASE + STM32WB_GPIO_BSRR_OFFSET) -#define STM32WB_GPIOA_LCKR (STM32WB_GPIOA_BASE + STM32WB_GPIO_LCKR_OFFSET) -#define STM32WB_GPIOA_AFRL (STM32WB_GPIOA_BASE + STM32WB_GPIO_AFRL_OFFSET) -#define STM32WB_GPIOA_AFRH (STM32WB_GPIOA_BASE + STM32WB_GPIO_AFRH_OFFSET) -#define STM32WB_GPIOA_BRR (STM32WB_GPIOA_BASE + STM32WB_GPIO_BRR_OFFSET) - -#define STM32WB_GPIOB_MODER (STM32WB_GPIOB_BASE + STM32WB_GPIO_MODER_OFFSET) -#define STM32WB_GPIOB_OTYPER (STM32WB_GPIOB_BASE + STM32WB_GPIO_OTYPER_OFFSET) -#define STM32WB_GPIOB_OSPEED (STM32WB_GPIOB_BASE + STM32WB_GPIO_OSPEED_OFFSET) -#define STM32WB_GPIOB_PUPDR (STM32WB_GPIOB_BASE + STM32WB_GPIO_PUPDR_OFFSET) -#define STM32WB_GPIOB_IDR (STM32WB_GPIOB_BASE + STM32WB_GPIO_IDR_OFFSET) -#define STM32WB_GPIOB_ODR (STM32WB_GPIOB_BASE + STM32WB_GPIO_ODR_OFFSET) -#define STM32WB_GPIOB_BSRR (STM32WB_GPIOB_BASE + STM32WB_GPIO_BSRR_OFFSET) -#define STM32WB_GPIOB_LCKR (STM32WB_GPIOB_BASE + STM32WB_GPIO_LCKR_OFFSET) -#define STM32WB_GPIOB_AFRL (STM32WB_GPIOB_BASE + STM32WB_GPIO_AFRL_OFFSET) -#define STM32WB_GPIOB_AFRH (STM32WB_GPIOB_BASE + STM32WB_GPIO_AFRH_OFFSET) -#define STM32WB_GPIOB_BRR (STM32WB_GPIOB_BASE + STM32WB_GPIO_BRR_OFFSET) - -#define STM32WB_GPIOC_MODER (STM32WB_GPIOC_BASE + STM32WB_GPIO_MODER_OFFSET) -#define STM32WB_GPIOC_OTYPER (STM32WB_GPIOC_BASE + STM32WB_GPIO_OTYPER_OFFSET) -#define STM32WB_GPIOC_OSPEED (STM32WB_GPIOC_BASE + STM32WB_GPIO_OSPEED_OFFSET) -#define STM32WB_GPIOC_PUPDR (STM32WB_GPIOC_BASE + STM32WB_GPIO_PUPDR_OFFSET) -#define STM32WB_GPIOC_IDR (STM32WB_GPIOC_BASE + STM32WB_GPIO_IDR_OFFSET) -#define STM32WB_GPIOC_ODR (STM32WB_GPIOC_BASE + STM32WB_GPIO_ODR_OFFSET) -#define STM32WB_GPIOC_BSRR (STM32WB_GPIOC_BASE + STM32WB_GPIO_BSRR_OFFSET) -#define STM32WB_GPIOC_LCKR (STM32WB_GPIOC_BASE + STM32WB_GPIO_LCKR_OFFSET) -#define STM32WB_GPIOC_AFRL (STM32WB_GPIOC_BASE + STM32WB_GPIO_AFRL_OFFSET) -#define STM32WB_GPIOC_AFRH (STM32WB_GPIOC_BASE + STM32WB_GPIO_AFRH_OFFSET) -#define STM32WB_GPIOC_BRR (STM32WB_GPIOC_BASE + STM32WB_GPIO_BRR_OFFSET) - -#if defined(CONFIG_STM32WB_GPIO_HAVE_PORTD) -# define STM32WB_GPIOD_MODER (STM32WB_GPIOD_BASE + STM32WB_GPIO_MODER_OFFSET) -# define STM32WB_GPIOD_OTYPER (STM32WB_GPIOD_BASE + STM32WB_GPIO_OTYPER_OFFSET) -# define STM32WB_GPIOD_OSPEED (STM32WB_GPIOD_BASE + STM32WB_GPIO_OSPEED_OFFSET) -# define STM32WB_GPIOD_PUPDR (STM32WB_GPIOD_BASE + STM32WB_GPIO_PUPDR_OFFSET) -# define STM32WB_GPIOD_IDR (STM32WB_GPIOD_BASE + STM32WB_GPIO_IDR_OFFSET) -# define STM32WB_GPIOD_ODR (STM32WB_GPIOD_BASE + STM32WB_GPIO_ODR_OFFSET) -# define STM32WB_GPIOD_BSRR (STM32WB_GPIOD_BASE + STM32WB_GPIO_BSRR_OFFSET) -# define STM32WB_GPIOD_LCKR (STM32WB_GPIOD_BASE + STM32WB_GPIO_LCKR_OFFSET) -# define STM32WB_GPIOD_AFRL (STM32WB_GPIOD_BASE + STM32WB_GPIO_AFRL_OFFSET) -# define STM32WB_GPIOD_AFRH (STM32WB_GPIOD_BASE + STM32WB_GPIO_AFRH_OFFSET) -# define STM32WB_GPIOD_BRR (STM32WB_GPIOD_BASE + STM32WB_GPIO_BRR_OFFSET) +#define STM32_GPIOA_MODER (STM32_GPIOA_BASE + STM32_GPIO_MODER_OFFSET) +#define STM32_GPIOA_OTYPER (STM32_GPIOA_BASE + STM32_GPIO_OTYPER_OFFSET) +#define STM32_GPIOA_OSPEED (STM32_GPIOA_BASE + STM32_GPIO_OSPEED_OFFSET) +#define STM32_GPIOA_PUPDR (STM32_GPIOA_BASE + STM32_GPIO_PUPDR_OFFSET) +#define STM32_GPIOA_IDR (STM32_GPIOA_BASE + STM32_GPIO_IDR_OFFSET) +#define STM32_GPIOA_ODR (STM32_GPIOA_BASE + STM32_GPIO_ODR_OFFSET) +#define STM32_GPIOA_BSRR (STM32_GPIOA_BASE + STM32_GPIO_BSRR_OFFSET) +#define STM32_GPIOA_LCKR (STM32_GPIOA_BASE + STM32_GPIO_LCKR_OFFSET) +#define STM32_GPIOA_AFRL (STM32_GPIOA_BASE + STM32_GPIO_AFRL_OFFSET) +#define STM32_GPIOA_AFRH (STM32_GPIOA_BASE + STM32_GPIO_AFRH_OFFSET) +#define STM32_GPIOA_BRR (STM32_GPIOA_BASE + STM32_GPIO_BRR_OFFSET) + +#define STM32_GPIOB_MODER (STM32_GPIOB_BASE + STM32_GPIO_MODER_OFFSET) +#define STM32_GPIOB_OTYPER (STM32_GPIOB_BASE + STM32_GPIO_OTYPER_OFFSET) +#define STM32_GPIOB_OSPEED (STM32_GPIOB_BASE + STM32_GPIO_OSPEED_OFFSET) +#define STM32_GPIOB_PUPDR (STM32_GPIOB_BASE + STM32_GPIO_PUPDR_OFFSET) +#define STM32_GPIOB_IDR (STM32_GPIOB_BASE + STM32_GPIO_IDR_OFFSET) +#define STM32_GPIOB_ODR (STM32_GPIOB_BASE + STM32_GPIO_ODR_OFFSET) +#define STM32_GPIOB_BSRR (STM32_GPIOB_BASE + STM32_GPIO_BSRR_OFFSET) +#define STM32_GPIOB_LCKR (STM32_GPIOB_BASE + STM32_GPIO_LCKR_OFFSET) +#define STM32_GPIOB_AFRL (STM32_GPIOB_BASE + STM32_GPIO_AFRL_OFFSET) +#define STM32_GPIOB_AFRH (STM32_GPIOB_BASE + STM32_GPIO_AFRH_OFFSET) +#define STM32_GPIOB_BRR (STM32_GPIOB_BASE + STM32_GPIO_BRR_OFFSET) + +#define STM32_GPIOC_MODER (STM32_GPIOC_BASE + STM32_GPIO_MODER_OFFSET) +#define STM32_GPIOC_OTYPER (STM32_GPIOC_BASE + STM32_GPIO_OTYPER_OFFSET) +#define STM32_GPIOC_OSPEED (STM32_GPIOC_BASE + STM32_GPIO_OSPEED_OFFSET) +#define STM32_GPIOC_PUPDR (STM32_GPIOC_BASE + STM32_GPIO_PUPDR_OFFSET) +#define STM32_GPIOC_IDR (STM32_GPIOC_BASE + STM32_GPIO_IDR_OFFSET) +#define STM32_GPIOC_ODR (STM32_GPIOC_BASE + STM32_GPIO_ODR_OFFSET) +#define STM32_GPIOC_BSRR (STM32_GPIOC_BASE + STM32_GPIO_BSRR_OFFSET) +#define STM32_GPIOC_LCKR (STM32_GPIOC_BASE + STM32_GPIO_LCKR_OFFSET) +#define STM32_GPIOC_AFRL (STM32_GPIOC_BASE + STM32_GPIO_AFRL_OFFSET) +#define STM32_GPIOC_AFRH (STM32_GPIOC_BASE + STM32_GPIO_AFRH_OFFSET) +#define STM32_GPIOC_BRR (STM32_GPIOC_BASE + STM32_GPIO_BRR_OFFSET) + +#if defined(CONFIG_STM32_GPIO_HAVE_PORTD) +# define STM32_GPIOD_MODER (STM32_GPIOD_BASE + STM32_GPIO_MODER_OFFSET) +# define STM32_GPIOD_OTYPER (STM32_GPIOD_BASE + STM32_GPIO_OTYPER_OFFSET) +# define STM32_GPIOD_OSPEED (STM32_GPIOD_BASE + STM32_GPIO_OSPEED_OFFSET) +# define STM32_GPIOD_PUPDR (STM32_GPIOD_BASE + STM32_GPIO_PUPDR_OFFSET) +# define STM32_GPIOD_IDR (STM32_GPIOD_BASE + STM32_GPIO_IDR_OFFSET) +# define STM32_GPIOD_ODR (STM32_GPIOD_BASE + STM32_GPIO_ODR_OFFSET) +# define STM32_GPIOD_BSRR (STM32_GPIOD_BASE + STM32_GPIO_BSRR_OFFSET) +# define STM32_GPIOD_LCKR (STM32_GPIOD_BASE + STM32_GPIO_LCKR_OFFSET) +# define STM32_GPIOD_AFRL (STM32_GPIOD_BASE + STM32_GPIO_AFRL_OFFSET) +# define STM32_GPIOD_AFRH (STM32_GPIOD_BASE + STM32_GPIO_AFRH_OFFSET) +# define STM32_GPIOD_BRR (STM32_GPIOD_BASE + STM32_GPIO_BRR_OFFSET) #endif -#if defined(CONFIG_STM32WB_GPIO_HAVE_PORTE) -# define STM32WB_GPIOE_MODER (STM32WB_GPIOE_BASE + STM32WB_GPIO_MODER_OFFSET) -# define STM32WB_GPIOE_OTYPER (STM32WB_GPIOE_BASE + STM32WB_GPIO_OTYPER_OFFSET) -# define STM32WB_GPIOE_OSPEED (STM32WB_GPIOE_BASE + STM32WB_GPIO_OSPEED_OFFSET) -# define STM32WB_GPIOE_PUPDR (STM32WB_GPIOE_BASE + STM32WB_GPIO_PUPDR_OFFSET) -# define STM32WB_GPIOE_IDR (STM32WB_GPIOE_BASE + STM32WB_GPIO_IDR_OFFSET) -# define STM32WB_GPIOE_ODR (STM32WB_GPIOE_BASE + STM32WB_GPIO_ODR_OFFSET) -# define STM32WB_GPIOE_BSRR (STM32WB_GPIOE_BASE + STM32WB_GPIO_BSRR_OFFSET) -# define STM32WB_GPIOE_LCKR (STM32WB_GPIOE_BASE + STM32WB_GPIO_LCKR_OFFSET) -# define STM32WB_GPIOE_AFRL (STM32WB_GPIOE_BASE + STM32WB_GPIO_AFRL_OFFSET) -# define STM32WB_GPIOE_BRR (STM32WB_GPIOE_BASE + STM32WB_GPIO_BRR_OFFSET) +#if defined(CONFIG_STM32_GPIO_HAVE_PORTE) +# define STM32_GPIOE_MODER (STM32_GPIOE_BASE + STM32_GPIO_MODER_OFFSET) +# define STM32_GPIOE_OTYPER (STM32_GPIOE_BASE + STM32_GPIO_OTYPER_OFFSET) +# define STM32_GPIOE_OSPEED (STM32_GPIOE_BASE + STM32_GPIO_OSPEED_OFFSET) +# define STM32_GPIOE_PUPDR (STM32_GPIOE_BASE + STM32_GPIO_PUPDR_OFFSET) +# define STM32_GPIOE_IDR (STM32_GPIOE_BASE + STM32_GPIO_IDR_OFFSET) +# define STM32_GPIOE_ODR (STM32_GPIOE_BASE + STM32_GPIO_ODR_OFFSET) +# define STM32_GPIOE_BSRR (STM32_GPIOE_BASE + STM32_GPIO_BSRR_OFFSET) +# define STM32_GPIOE_LCKR (STM32_GPIOE_BASE + STM32_GPIO_LCKR_OFFSET) +# define STM32_GPIOE_AFRL (STM32_GPIOE_BASE + STM32_GPIO_AFRL_OFFSET) +# define STM32_GPIOE_BRR (STM32_GPIOE_BASE + STM32_GPIO_BRR_OFFSET) #endif -#define STM32WB_GPIOH_MODER (STM32WB_GPIOH_BASE + STM32WB_GPIO_MODER_OFFSET) -#define STM32WB_GPIOH_OTYPER (STM32WB_GPIOH_BASE + STM32WB_GPIO_OTYPER_OFFSET) -#define STM32WB_GPIOH_OSPEED (STM32WB_GPIOH_BASE + STM32WB_GPIO_OSPEED_OFFSET) -#define STM32WB_GPIOH_PUPDR (STM32WB_GPIOH_BASE + STM32WB_GPIO_PUPDR_OFFSET) -#define STM32WB_GPIOH_IDR (STM32WB_GPIOH_BASE + STM32WB_GPIO_IDR_OFFSET) -#define STM32WB_GPIOH_ODR (STM32WB_GPIOH_BASE + STM32WB_GPIO_ODR_OFFSET) -#define STM32WB_GPIOH_BSRR (STM32WB_GPIOH_BASE + STM32WB_GPIO_BSRR_OFFSET) -#define STM32WB_GPIOH_LCKR (STM32WB_GPIOH_BASE + STM32WB_GPIO_LCKR_OFFSET) -#define STM32WB_GPIOH_AFRL (STM32WB_GPIOH_BASE + STM32WB_GPIO_AFRL_OFFSET) -#define STM32WB_GPIOH_BRR (STM32WB_GPIOH_BASE + STM32WB_GPIO_BRR_OFFSET) +#define STM32_GPIOH_MODER (STM32_GPIOH_BASE + STM32_GPIO_MODER_OFFSET) +#define STM32_GPIOH_OTYPER (STM32_GPIOH_BASE + STM32_GPIO_OTYPER_OFFSET) +#define STM32_GPIOH_OSPEED (STM32_GPIOH_BASE + STM32_GPIO_OSPEED_OFFSET) +#define STM32_GPIOH_PUPDR (STM32_GPIOH_BASE + STM32_GPIO_PUPDR_OFFSET) +#define STM32_GPIOH_IDR (STM32_GPIOH_BASE + STM32_GPIO_IDR_OFFSET) +#define STM32_GPIOH_ODR (STM32_GPIOH_BASE + STM32_GPIO_ODR_OFFSET) +#define STM32_GPIOH_BSRR (STM32_GPIOH_BASE + STM32_GPIO_BSRR_OFFSET) +#define STM32_GPIOH_LCKR (STM32_GPIOH_BASE + STM32_GPIO_LCKR_OFFSET) +#define STM32_GPIOH_AFRL (STM32_GPIOH_BASE + STM32_GPIO_AFRL_OFFSET) +#define STM32_GPIOH_BRR (STM32_GPIOH_BASE + STM32_GPIO_BRR_OFFSET) /* Register Bitfield Definitions ********************************************/ diff --git a/arch/arm/src/stm32wb/hardware/stm32wb_i2c.h b/arch/arm/src/stm32wb/hardware/stm32wb_i2c.h index 0e86bb6467542..a16c5a97dffe8 100644 --- a/arch/arm/src/stm32wb/hardware/stm32wb_i2c.h +++ b/arch/arm/src/stm32wb/hardware/stm32wb_i2c.h @@ -29,44 +29,44 @@ /* Register Offsets *********************************************************/ -#define STM32WB_I2C_CR1_OFFSET 0x0000 /* Control register 1 (32-bit) */ -#define STM32WB_I2C_CR2_OFFSET 0x0004 /* Control register 2 (32-bit) */ -#define STM32WB_I2C_OAR1_OFFSET 0x0008 /* Own address register 1 (16-bit) */ -#define STM32WB_I2C_OAR2_OFFSET 0x000c /* Own address register 2 (16-bit) */ -#define STM32WB_I2C_TIMINGR_OFFSET 0x0010 /* Timing register */ -#define STM32WB_I2C_TIMEOUTR_OFFSET 0x0014 /* Timeout register */ -#define STM32WB_I2C_ISR_OFFSET 0x0018 /* Interrupt and Status register */ -#define STM32WB_I2C_ICR_OFFSET 0x001c /* Interrupt clear register */ -#define STM32WB_I2C_PECR_OFFSET 0x0020 /* Packet error checking register */ -#define STM32WB_I2C_RXDR_OFFSET 0x0024 /* Receive data register */ -#define STM32WB_I2C_TXDR_OFFSET 0x0028 /* Transmit data register */ +#define STM32_I2C_CR1_OFFSET 0x0000 /* Control register 1 (32-bit) */ +#define STM32_I2C_CR2_OFFSET 0x0004 /* Control register 2 (32-bit) */ +#define STM32_I2C_OAR1_OFFSET 0x0008 /* Own address register 1 (16-bit) */ +#define STM32_I2C_OAR2_OFFSET 0x000c /* Own address register 2 (16-bit) */ +#define STM32_I2C_TIMINGR_OFFSET 0x0010 /* Timing register */ +#define STM32_I2C_TIMEOUTR_OFFSET 0x0014 /* Timeout register */ +#define STM32_I2C_ISR_OFFSET 0x0018 /* Interrupt and Status register */ +#define STM32_I2C_ICR_OFFSET 0x001c /* Interrupt clear register */ +#define STM32_I2C_PECR_OFFSET 0x0020 /* Packet error checking register */ +#define STM32_I2C_RXDR_OFFSET 0x0024 /* Receive data register */ +#define STM32_I2C_TXDR_OFFSET 0x0028 /* Transmit data register */ /* Register Addresses *******************************************************/ -#define STM32WB_I2C1_CR1 (STM32WB_I2C1_BASE + STM32WB_I2C_CR1_OFFSET) -#define STM32WB_I2C1_CR2 (STM32WB_I2C1_BASE + STM32WB_I2C_CR2_OFFSET) -#define STM32WB_I2C1_OAR1 (STM32WB_I2C1_BASE + STM32WB_I2C_OAR1_OFFSET) -#define STM32WB_I2C1_OAR2 (STM32WB_I2C1_BASE + STM32WB_I2C_OAR2_OFFSET) -#define STM32WB_I2C1_TIMINGR (STM32WB_I2C1_BASE + STM32WB_I2C_TIMINGR_OFFSET) -#define STM32WB_I2C1_TIMEOUTR (STM32WB_I2C1_BASE + STM32WB_I2C_TIMEOUTR_OFFSET) -#define STM32WB_I2C1_ISR (STM32WB_I2C1_BASE + STM32WB_I2C_ISR_OFFSET) -#define STM32WB_I2C1_ICR (STM32WB_I2C1_BASE + STM32WB_I2C_ICR_OFFSET) -#define STM32WB_I2C1_PECR (STM32WB_I2C1_BASE + STM32WB_I2C_PECR_OFFSET) -#define STM32WB_I2C1_RXDR (STM32WB_I2C1_BASE + STM32WB_I2C_RXDR_OFFSET) -#define STM32WB_I2C1_TXDR (STM32WB_I2C1_BASE + STM32WB_I2C_TXDR_OFFSET) - -#ifdef CONFIG_STM32WB_HAVE_I2C3 -# define STM32WB_I2C3_CR1 (STM32WB_I2C3_BASE + STM32WB_I2C_CR1_OFFSET) -# define STM32WB_I2C3_CR2 (STM32WB_I2C3_BASE + STM32WB_I2C_CR2_OFFSET) -# define STM32WB_I2C3_OAR1 (STM32WB_I2C3_BASE + STM32WB_I2C_OAR1_OFFSET) -# define STM32WB_I2C3_OAR2 (STM32WB_I2C3_BASE + STM32WB_I2C_OAR2_OFFSET) -# define STM32WB_I2C3_TIMINGR (STM32WB_I2C3_BASE + STM32WB_I2C_TIMINGR_OFFSET) -# define STM32WB_I2C3_TIMEOUTR (STM32WB_I2C3_BASE + STM32WB_I2C_TIMEOUTR_OFFSET) -# define STM32WB_I2C3_ISR (STM32WB_I2C3_BASE + STM32WB_I2C_ISR_OFFSET) -# define STM32WB_I2C3_ICR (STM32WB_I2C3_BASE + STM32WB_I2C_ICR_OFFSET) -# define STM32WB_I2C3_PECR (STM32WB_I2C3_BASE + STM32WB_I2C_PECR_OFFSET) -# define STM32WB_I2C3_RXDR (STM32WB_I2C3_BASE + STM32WB_I2C_RXDR_OFFSET) -# define STM32WB_I2C3_TXDR (STM32WB_I2C3_BASE + STM32WB_I2C_TXDR_OFFSET) +#define STM32_I2C1_CR1 (STM32_I2C1_BASE + STM32_I2C_CR1_OFFSET) +#define STM32_I2C1_CR2 (STM32_I2C1_BASE + STM32_I2C_CR2_OFFSET) +#define STM32_I2C1_OAR1 (STM32_I2C1_BASE + STM32_I2C_OAR1_OFFSET) +#define STM32_I2C1_OAR2 (STM32_I2C1_BASE + STM32_I2C_OAR2_OFFSET) +#define STM32_I2C1_TIMINGR (STM32_I2C1_BASE + STM32_I2C_TIMINGR_OFFSET) +#define STM32_I2C1_TIMEOUTR (STM32_I2C1_BASE + STM32_I2C_TIMEOUTR_OFFSET) +#define STM32_I2C1_ISR (STM32_I2C1_BASE + STM32_I2C_ISR_OFFSET) +#define STM32_I2C1_ICR (STM32_I2C1_BASE + STM32_I2C_ICR_OFFSET) +#define STM32_I2C1_PECR (STM32_I2C1_BASE + STM32_I2C_PECR_OFFSET) +#define STM32_I2C1_RXDR (STM32_I2C1_BASE + STM32_I2C_RXDR_OFFSET) +#define STM32_I2C1_TXDR (STM32_I2C1_BASE + STM32_I2C_TXDR_OFFSET) + +#ifdef CONFIG_STM32_HAVE_I2C3 +# define STM32_I2C3_CR1 (STM32_I2C3_BASE + STM32_I2C_CR1_OFFSET) +# define STM32_I2C3_CR2 (STM32_I2C3_BASE + STM32_I2C_CR2_OFFSET) +# define STM32_I2C3_OAR1 (STM32_I2C3_BASE + STM32_I2C_OAR1_OFFSET) +# define STM32_I2C3_OAR2 (STM32_I2C3_BASE + STM32_I2C_OAR2_OFFSET) +# define STM32_I2C3_TIMINGR (STM32_I2C3_BASE + STM32_I2C_TIMINGR_OFFSET) +# define STM32_I2C3_TIMEOUTR (STM32_I2C3_BASE + STM32_I2C_TIMEOUTR_OFFSET) +# define STM32_I2C3_ISR (STM32_I2C3_BASE + STM32_I2C_ISR_OFFSET) +# define STM32_I2C3_ICR (STM32_I2C3_BASE + STM32_I2C_ICR_OFFSET) +# define STM32_I2C3_PECR (STM32_I2C3_BASE + STM32_I2C_PECR_OFFSET) +# define STM32_I2C3_RXDR (STM32_I2C3_BASE + STM32_I2C_RXDR_OFFSET) +# define STM32_I2C3_TXDR (STM32_I2C3_BASE + STM32_I2C_TXDR_OFFSET) #endif /* Register Bitfield Definitions ********************************************/ diff --git a/arch/arm/src/stm32wb/hardware/stm32wb_ipcc.h b/arch/arm/src/stm32wb/hardware/stm32wb_ipcc.h index 6e1d597ff1c1b..949850d2eca05 100644 --- a/arch/arm/src/stm32wb/hardware/stm32wb_ipcc.h +++ b/arch/arm/src/stm32wb/hardware/stm32wb_ipcc.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32WB_IPCC_H -#define __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32WB_IPCC_H +#ifndef __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32_IPCC_H +#define __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32_IPCC_H /**************************************************************************** * Pre-processor Definitions @@ -29,25 +29,25 @@ /* Register Offsets *********************************************************/ -#define STM32WB_IPCC_C1CR_OFFSET 0x0000 /* CPU1 control register */ -#define STM32WB_IPCC_C1MR_OFFSET 0x0004 /* CPU1 mask register */ -#define STM32WB_IPCC_C1SCR_OFFSET 0x0008 /* CPU1 status set/clear register */ -#define STM32WB_IPCC_C1TOC2SR_OFFSET 0x000c /* CPU1 to CPU2 status register */ -#define STM32WB_IPCC_C2CR_OFFSET 0x0010 /* CPU2 control register */ -#define STM32WB_IPCC_C2MR_OFFSET 0x0014 /* CPU2 mask register */ -#define STM32WB_IPCC_C2SCR_OFFSET 0x0018 /* CPU2 status set/clear register */ -#define STM32WB_IPCC_C2TOC1SR_OFFSET 0x001c /* CPU2 to CPU1 status register */ +#define STM32_IPCC_C1CR_OFFSET 0x0000 /* CPU1 control register */ +#define STM32_IPCC_C1MR_OFFSET 0x0004 /* CPU1 mask register */ +#define STM32_IPCC_C1SCR_OFFSET 0x0008 /* CPU1 status set/clear register */ +#define STM32_IPCC_C1TOC2SR_OFFSET 0x000c /* CPU1 to CPU2 status register */ +#define STM32_IPCC_C2CR_OFFSET 0x0010 /* CPU2 control register */ +#define STM32_IPCC_C2MR_OFFSET 0x0014 /* CPU2 mask register */ +#define STM32_IPCC_C2SCR_OFFSET 0x0018 /* CPU2 status set/clear register */ +#define STM32_IPCC_C2TOC1SR_OFFSET 0x001c /* CPU2 to CPU1 status register */ /* Register Addresses *******************************************************/ -#define STM32WB_IPCC_C1CR (STM32WB_IPCC_BASE + STM32WB_IPCC_C1CR_OFFSET) -#define STM32WB_IPCC_C1MR (STM32WB_IPCC_BASE + STM32WB_IPCC_C1MR_OFFSET) -#define STM32WB_IPCC_C1SCR (STM32WB_IPCC_BASE + STM32WB_IPCC_C1SCR_OFFSET) -#define STM32WB_IPCC_C1TOC2SR (STM32WB_IPCC_BASE + STM32WB_IPCC_C1TOC2SR_OFFSET) -#define STM32WB_IPCC_C2CR (STM32WB_IPCC_BASE + STM32WB_IPCC_C2CR_OFFSET) -#define STM32WB_IPCC_C2MR (STM32WB_IPCC_BASE + STM32WB_IPCC_C2MR_OFFSET) -#define STM32WB_IPCC_C2SCR (STM32WB_IPCC_BASE + STM32WB_IPCC_C2SCR_OFFSET) -#define STM32WB_IPCC_C2TOC1SR (STM32WB_IPCC_BASE + STM32WB_IPCC_C2TOC1SR_OFFSET) +#define STM32_IPCC_C1CR (STM32_IPCC_BASE + STM32_IPCC_C1CR_OFFSET) +#define STM32_IPCC_C1MR (STM32_IPCC_BASE + STM32_IPCC_C1MR_OFFSET) +#define STM32_IPCC_C1SCR (STM32_IPCC_BASE + STM32_IPCC_C1SCR_OFFSET) +#define STM32_IPCC_C1TOC2SR (STM32_IPCC_BASE + STM32_IPCC_C1TOC2SR_OFFSET) +#define STM32_IPCC_C2CR (STM32_IPCC_BASE + STM32_IPCC_C2CR_OFFSET) +#define STM32_IPCC_C2MR (STM32_IPCC_BASE + STM32_IPCC_C2MR_OFFSET) +#define STM32_IPCC_C2SCR (STM32_IPCC_BASE + STM32_IPCC_C2SCR_OFFSET) +#define STM32_IPCC_C2TOC1SR (STM32_IPCC_BASE + STM32_IPCC_C2TOC1SR_OFFSET) /* Register Bitfield Definitions ********************************************/ @@ -113,4 +113,4 @@ #define IPCC_C2TOC1SR_MASK (0x3f << IPCC_C2TOC1SR_SHIFT) #define IPCC_C2TOC1SR_BIT(n) (1 << (IPCC_C2TOC1SR_SHIFT + (n) - 1)) /* Channel n = 1..6 */ -#endif /* __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32WB_IPCC_H */ +#endif /* __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32_IPCC_H */ diff --git a/arch/arm/src/stm32wb/hardware/stm32wb_memorymap.h b/arch/arm/src/stm32wb/hardware/stm32wb_memorymap.h index 58d3d249b66be..03523f9b1206c 100644 --- a/arch/arm/src/stm32wb/hardware/stm32wb_memorymap.h +++ b/arch/arm/src/stm32wb/hardware/stm32wb_memorymap.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32WB_MEMORYMAP_H -#define __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32WB_MEMORYMAP_H +#ifndef __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32_MEMORYMAP_H +#define __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32_MEMORYMAP_H /**************************************************************************** * Pre-processor Definitions @@ -29,33 +29,33 @@ /* STM32WBXXX Address Blocks ************************************************/ -#define STM32WB_CODE_BASE 0x00000000 /* 0x00000000-0x1fffffff: 512Mb code block */ -#define STM32WB_SRAM_BASE 0x20000000 /* 0x20000000-0x2003ffff: 256k RAM block */ -#define STM32WB_PERIPH_BASE 0x40000000 /* Peripheral base address */ -#define STM32WB_CORTEX_BASE 0xe0000000 /* 0xe0000000-0xffffffff: 512Mb Cortex-M4 block */ +#define STM32_CODE_BASE 0x00000000 /* 0x00000000-0x1fffffff: 512Mb code block */ +#define STM32_SRAM_BASE 0x20000000 /* 0x20000000-0x2003ffff: 256k RAM block */ +#define STM32_PERIPH_BASE 0x40000000 /* Peripheral base address */ +#define STM32_CORTEX_BASE 0xe0000000 /* 0xe0000000-0xffffffff: 512Mb Cortex-M4 block */ /* Code Base Addresses ******************************************************/ -#define STM32WB_BOOT_BASE 0x00000000 /* 0x00000000-0x000fffff: Aliased boot memory */ -#define STM32WB_FLASH_BASE 0x08000000 /* 0x08000000-0x080fffff: FLASH memory */ -#define STM32WB_FLASH_MASK 0xf8000000 /* Test if addr in FLASH */ -#define STM32WB_SRAM1_BASE 0x20000000 /* 0x20000000-0x2002ffff: 192к RAM1 block */ -#define STM32WB_SRAM2A_BASE 0x20030000 /* 0x20030000-0x20037fff: 32k RAM2a block */ -#define STM32WB_SRAM2B_BASE 0x20038000 /* 0x20038000-0x2003ffff: 32k RAM2b block */ +#define STM32_BOOT_BASE 0x00000000 /* 0x00000000-0x000fffff: Aliased boot memory */ +#define STM32_FLASH_BASE 0x08000000 /* 0x08000000-0x080fffff: FLASH memory */ +#define STM32_FLASH_MASK 0xf8000000 /* Test if addr in FLASH */ +#define STM32_SRAM1_BASE 0x20000000 /* 0x20000000-0x2002ffff: 192к RAM1 block */ +#define STM32_SRAM2A_BASE 0x20030000 /* 0x20030000-0x20037fff: 32k RAM2a block */ +#define STM32_SRAM2B_BASE 0x20038000 /* 0x20038000-0x2003ffff: 32k RAM2b block */ -#define STM32WB_SYSMEM_BASE 0x1fff0000 /* 0x1fff0000-0x20006fff: System memory */ -#define STM32WB_OTP_BASE 0x1fff7000 /* 0x1fff7000-0x1fff73ff: OTP memory */ -#define STM32WB_OPTION_BASE 0x1fff8000 /* 0x1fff8000-0x1fff8fff: Option bytes */ +#define STM32_SYSMEM_BASE 0x1fff0000 /* 0x1fff0000-0x20006fff: System memory */ +#define STM32_OTP_BASE 0x1fff7000 /* 0x1fff7000-0x1fff73ff: OTP memory */ +#define STM32_OPTION_BASE 0x1fff8000 /* 0x1fff8000-0x1fff8fff: Option bytes */ /* System Memory Addresses **************************************************/ -#define STM32WB_SYSMEM_UID 0x1fff7590 /* The 96-bit unique device identifier */ -#define STM32WB_SYSMEM_FSIZE 0x1fff75e0 /* This bitfield indicates the size of +#define STM32_SYSMEM_UID 0x1fff7590 /* The 96-bit unique device identifier */ +#define STM32_SYSMEM_FSIZE 0x1fff75e0 /* This bitfield indicates the size of * the device Flash memory expressed in * Kbytes. Example: 0x0400 corresponds * to 1024 Kbytes. */ -#define STM32WB_SYSMEM_PACKAGE 0x1fff7500 /* This bitfield indicates the package +#define STM32_SYSMEM_PACKAGE 0x1fff7500 /* This bitfield indicates the package * type. 5 LSB corresponds to: * 0x11: WLCSP100 / UFBGA129 * 0x13: VFQFPN68 @@ -64,96 +64,96 @@ /* SRAM Base Addresses ******************************************************/ -#define STM32WB_SRAMBB_BASE 0x22000000 /* 0x22000000-0x227fffff: SRAM bit-band region */ +#define STM32_SRAMBB_BASE 0x22000000 /* 0x22000000-0x227fffff: SRAM bit-band region */ /* Peripheral Base Addresses ************************************************/ -#define STM32WB_APB1_BASE 0x40000000 /* 0x40000000-0x400097ff: APB1 */ - /* 0x40009800-0x4000ffff: Reserved */ -#define STM32WB_APB2_BASE 0x40010000 /* 0x40010000-0x400157ff: APB2 */ - /* 0x40015800-0x4001ffff: Reserved */ -#define STM32WB_AHB1_BASE 0x40020000 /* 0x40020000-0x400243ff: AHB1 */ - /* 0x40024400-0x47ffffff: Reserved */ -#define STM32WB_AHB2_BASE 0x48000000 /* 0x48000000-0x500603ff: AHB2 */ - /* 0x50060400-0x57ffffff: Reserved */ -#define STM32WB_AHB4_BASE 0x58000000 /* 0x58000000-0x580043ff: AHB4 */ - /* 0x58004400-0x5fffffff: Reserved */ -#define STM32WB_APB3_BASE 0x60000000 /* 0x60000000-0x60001fff: APB3 */ - /* 0x60002000-0x8fffffff: Reserved */ -#define STM32WB_AHB3_BASE 0x90000000 /* 0x90000000-0xA00013ff: AHB3 */ +#define STM32_APB1_BASE 0x40000000 /* 0x40000000-0x400097ff: APB1 */ + /* 0x40009800-0x4000ffff: Reserved */ +#define STM32_APB2_BASE 0x40010000 /* 0x40010000-0x400157ff: APB2 */ + /* 0x40015800-0x4001ffff: Reserved */ +#define STM32_AHB1_BASE 0x40020000 /* 0x40020000-0x400243ff: AHB1 */ + /* 0x40024400-0x47ffffff: Reserved */ +#define STM32_AHB2_BASE 0x48000000 /* 0x48000000-0x500603ff: AHB2 */ + /* 0x50060400-0x57ffffff: Reserved */ +#define STM32_AHB4_BASE 0x58000000 /* 0x58000000-0x580043ff: AHB4 */ + /* 0x58004400-0x5fffffff: Reserved */ +#define STM32_APB3_BASE 0x60000000 /* 0x60000000-0x60001fff: APB3 */ + /* 0x60002000-0x8fffffff: Reserved */ +#define STM32_AHB3_BASE 0x90000000 /* 0x90000000-0xA00013ff: AHB3 */ /* APB1 Base Addresses ******************************************************/ -#define STM32WB_TIM2_BASE 0x40000000 -#define STM32WB_LCD_BASE 0x40002400 -#define STM32WB_RTC_BASE 0x40002800 -#define STM32WB_WWDG_BASE 0x40002c00 -#define STM32WB_IWDG_BASE 0x40003000 -#define STM32WB_SPI2_BASE 0x40003800 -#define STM32WB_I2C1_BASE 0x40005400 -#define STM32WB_I2C3_BASE 0x40005c00 -#define STM32WB_CRS_BASE 0x40006000 -#define STM32WB_USB1_BASE 0x40006800 -#define STM32WB_USB1_PMAADDR 0x40006c00 -#define STM32WB_LPTIM1_BASE 0x40007c00 -#define STM32WB_LPUART1_BASE 0x40008000 -#define STM32WB_LPTIM2_BASE 0x40009400 +#define STM32_TIM2_BASE 0x40000000 +#define STM32_LCD_BASE 0x40002400 +#define STM32_RTC_BASE 0x40002800 +#define STM32_WWDG_BASE 0x40002c00 +#define STM32_IWDG_BASE 0x40003000 +#define STM32_SPI2_BASE 0x40003800 +#define STM32_I2C1_BASE 0x40005400 +#define STM32_I2C3_BASE 0x40005c00 +#define STM32_CRS_BASE 0x40006000 +#define STM32_USB1_BASE 0x40006800 +#define STM32_USB1_PMAADDR 0x40006c00 +#define STM32_LPTIM1_BASE 0x40007c00 +#define STM32_LPUART1_BASE 0x40008000 +#define STM32_LPTIM2_BASE 0x40009400 /* APB2 Base Addresses ******************************************************/ -#define STM32WB_SYSCFG_BASE 0x40010000 -#define STM32WB_VREFBUF_BASE 0x40010030 -#define STM32WB_COMP1_BASE 0x40010200 -#define STM32WB_COMP2_BASE 0x40010204 -#define STM32WB_TIM1_BASE 0x40012c00 -#define STM32WB_SPI1_BASE 0x40013000 -#define STM32WB_USART1_BASE 0x40013800 -#define STM32WB_TIM16_BASE 0x40014400 -#define STM32WB_TIM17_BASE 0x40014800 -#define STM32WB_SAI1_BASE 0x40015400 +#define STM32_SYSCFG_BASE 0x40010000 +#define STM32_VREFBUF_BASE 0x40010030 +#define STM32_COMP1_BASE 0x40010200 +#define STM32_COMP2_BASE 0x40010204 +#define STM32_TIM1_BASE 0x40012c00 +#define STM32_SPI1_BASE 0x40013000 +#define STM32_USART1_BASE 0x40013800 +#define STM32_TIM16_BASE 0x40014400 +#define STM32_TIM17_BASE 0x40014800 +#define STM32_SAI1_BASE 0x40015400 /* AHB1 Base Addresses ******************************************************/ -#define STM32WB_DMA1_BASE 0x40020000 -#define STM32WB_DMA2_BASE 0x40020400 -#define STM32WB_DMAMUX1_BASE 0x40020800 -#define STM32WB_CRC_BASE 0x40023000 -#define STM32WB_TSC_BASE 0x40024000 +#define STM32_DMA1_BASE 0x40020000 +#define STM32_DMA2_BASE 0x40020400 +#define STM32_DMAMUX1_BASE 0x40020800 +#define STM32_CRC_BASE 0x40023000 +#define STM32_TSC_BASE 0x40024000 /* AHB2 Base Addresses ******************************************************/ -#define STM32WB_GPIOA_BASE 0x48000000 -#define STM32WB_GPIOB_BASE 0x48000400 -#define STM32WB_GPIOC_BASE 0x48000800 -#define STM32WB_GPIOD_BASE 0x48000c00 -#define STM32WB_GPIOE_BASE 0x48001000 -#define STM32WB_GPIOH_BASE 0x48001c00 -#define STM32WB_ADC1_BASE 0x50040000 -#define STM32WB_AES1_BASE 0x50060000 +#define STM32_GPIOA_BASE 0x48000000 +#define STM32_GPIOB_BASE 0x48000400 +#define STM32_GPIOC_BASE 0x48000800 +#define STM32_GPIOD_BASE 0x48000c00 +#define STM32_GPIOE_BASE 0x48001000 +#define STM32_GPIOH_BASE 0x48001c00 +#define STM32_ADC1_BASE 0x50040000 +#define STM32_AES1_BASE 0x50060000 /* AHB4 Base Addresses ******************************************************/ -#define STM32WB_RCC_BASE 0x58000000 -#define STM32WB_PWR_BASE 0x58000400 -#define STM32WB_EXTI_BASE 0x58000800 -#define STM32WB_IPCC_BASE 0x58000c00 -#define STM32WB_RNG_BASE 0x58001000 -#define STM32WB_HSEM_BASE 0x58001400 -#define STM32WB_AES2_BASE 0x58001800 -#define STM32WB_PKA_BASE 0x58002000 -#define STM32WB_FLASHREG_BASE 0x58004000 +#define STM32_RCC_BASE 0x58000000 +#define STM32_PWR_BASE 0x58000400 +#define STM32_EXTI_BASE 0x58000800 +#define STM32_IPCC_BASE 0x58000c00 +#define STM32_RNG_BASE 0x58001000 +#define STM32_HSEM_BASE 0x58001400 +#define STM32_AES2_BASE 0x58001800 +#define STM32_PKA_BASE 0x58002000 +#define STM32_FLASHREG_BASE 0x58004000 /* APB3 Base Addresses ******************************************************/ -#define STM32WB_BLE_BASE 0x60000000 -#define STM32WB_RADIO_BASE 0x60000400 -#define STM32WB_802154_BASE 0x60001000 +#define STM32_BLE_BASE 0x60000000 +#define STM32_RADIO_BASE 0x60000400 +#define STM32_802154_BASE 0x60001000 /* AHB3 Base Addresses ******************************************************/ -#define STM32WB_QSPI_BASE 0x90000000 -#define STM32WB_QSPI_BANK 0x90000000 /* 0x90000000-0x9fffffff: 256Mb QSPI memory mapping */ -#define STM32WB_QSPIREF_BASE 0xa0001000 +#define STM32_QSPI_BASE 0x90000000 +#define STM32_QSPI_BANK 0x90000000 /* 0x90000000-0x9fffffff: 256Mb QSPI memory mapping */ +#define STM32_QSPIREF_BASE 0xa0001000 /* Cortex-M4 Base Addresses *************************************************/ @@ -161,7 +161,7 @@ * this address range */ -#define STM32WB_SCS_BASE 0xe000e000 -#define STM32WB_DEBUGMCU_BASE 0xe0042000 +#define STM32_SCS_BASE 0xe000e000 +#define STM32_DEBUGMCU_BASE 0xe0042000 -#endif /* __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32WB_MEMORYMAP_H */ +#endif /* __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32_MEMORYMAP_H */ diff --git a/arch/arm/src/stm32wb/hardware/stm32wb_pinmap.h b/arch/arm/src/stm32wb/hardware/stm32wb_pinmap.h index 5b364b571643f..ebe67f6d6bdf9 100644 --- a/arch/arm/src/stm32wb/hardware/stm32wb_pinmap.h +++ b/arch/arm/src/stm32wb/hardware/stm32wb_pinmap.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32WB_PINMAP_H -#define __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32WB_PINMAP_H +#ifndef __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32_PINMAP_H +#define __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32_PINMAP_H /**************************************************************************** * Included Files @@ -30,12 +30,12 @@ #include #include "chip.h" -#if defined(CONFIG_STM32WB_STM32WB10) || defined(CONFIG_STM32WB_STM32WB15) || \ - defined(CONFIG_STM32WB_STM32WB30) || defined(CONFIG_STM32WB_STM32WB35) || \ - defined(CONFIG_STM32WB_STM32WB50) || defined(CONFIG_STM32WB_STM32WB55) +#if defined(CONFIG_STM32_STM32WB10) || defined(CONFIG_STM32_STM32WB15) || \ + defined(CONFIG_STM32_STM32WB30) || defined(CONFIG_STM32_STM32WB35) || \ + defined(CONFIG_STM32_STM32WB50) || defined(CONFIG_STM32_STM32WB55) # include "hardware/stm32wbxx_pinmap.h" #else # error "Unsupported STM32WB Pin map" #endif -#endif /* __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32WB_PINMAP_H */ +#endif /* __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32_PINMAP_H */ diff --git a/arch/arm/src/stm32wb/hardware/stm32wb_pwr.h b/arch/arm/src/stm32wb/hardware/stm32wb_pwr.h index 8e161735c05cf..6083a1c8a0b46 100644 --- a/arch/arm/src/stm32wb/hardware/stm32wb_pwr.h +++ b/arch/arm/src/stm32wb/hardware/stm32wb_pwr.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32WB_PWR_H -#define __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32WB_PWR_H +#ifndef __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32_PWR_H +#define __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32_PWR_H /**************************************************************************** * Included Files @@ -36,54 +36,54 @@ /* Register Offsets *********************************************************/ -#define STM32WB_PWR_CR1_OFFSET 0x0000 /* Power control register 1 */ -#define STM32WB_PWR_CR2_OFFSET 0x0004 /* Power control register 2 */ -#define STM32WB_PWR_CR3_OFFSET 0x0008 /* Power control register 3 */ -#define STM32WB_PWR_CR4_OFFSET 0x000C /* Power control register 4 */ -#define STM32WB_PWR_SR1_OFFSET 0x0010 /* Power status register 1 */ -#define STM32WB_PWR_SR2_OFFSET 0x0014 /* Power status register 2 */ -#define STM32WB_PWR_SCR_OFFSET 0x0018 /* Power status clear register */ -#define STM32WB_PWR_CR5_OFFSET 0x001C /* Power control register 5 */ -#define STM32WB_PWR_PUCRA_OFFSET 0x0020 /* Power Port A pull-up control register */ -#define STM32WB_PWR_PDCRA_OFFSET 0x0024 /* Power Port A pull-down control register */ -#define STM32WB_PWR_PUCRB_OFFSET 0x0028 /* Power Port B pull-up control register */ -#define STM32WB_PWR_PDCRB_OFFSET 0x002C /* Power Port B pull-down control register */ -#define STM32WB_PWR_PUCRC_OFFSET 0x0030 /* Power Port C pull-up control register */ -#define STM32WB_PWR_PDCRC_OFFSET 0x0034 /* Power Port C pull-down control register */ -#define STM32WB_PWR_PUCRD_OFFSET 0x0038 /* Power Port D pull-up control register */ -#define STM32WB_PWR_PDCRD_OFFSET 0x003C /* Power Port D pull-down control register */ -#define STM32WB_PWR_PUCRE_OFFSET 0x0040 /* Power Port E pull-up control register */ -#define STM32WB_PWR_PUCRH_OFFSET 0x0058 /* Power Port H pull-up control register */ -#define STM32WB_PWR_PDCRH_OFFSET 0x005C /* Power Port H pull-down control register */ -#define STM32WB_PWR_C2CR1_OFFSET 0x0080 /* CPU2 control register 1 */ -#define STM32WB_PWR_C2CR3_OFFSET 0x0084 /* CPU2 control register 3 */ -#define STM32WB_PWR_EXTSCR_OFFSET 0x0088 /* Extended status and status clear register */ +#define STM32_PWR_CR1_OFFSET 0x0000 /* Power control register 1 */ +#define STM32_PWR_CR2_OFFSET 0x0004 /* Power control register 2 */ +#define STM32_PWR_CR3_OFFSET 0x0008 /* Power control register 3 */ +#define STM32_PWR_CR4_OFFSET 0x000C /* Power control register 4 */ +#define STM32_PWR_SR1_OFFSET 0x0010 /* Power status register 1 */ +#define STM32_PWR_SR2_OFFSET 0x0014 /* Power status register 2 */ +#define STM32_PWR_SCR_OFFSET 0x0018 /* Power status clear register */ +#define STM32_PWR_CR5_OFFSET 0x001C /* Power control register 5 */ +#define STM32_PWR_PUCRA_OFFSET 0x0020 /* Power Port A pull-up control register */ +#define STM32_PWR_PDCRA_OFFSET 0x0024 /* Power Port A pull-down control register */ +#define STM32_PWR_PUCRB_OFFSET 0x0028 /* Power Port B pull-up control register */ +#define STM32_PWR_PDCRB_OFFSET 0x002C /* Power Port B pull-down control register */ +#define STM32_PWR_PUCRC_OFFSET 0x0030 /* Power Port C pull-up control register */ +#define STM32_PWR_PDCRC_OFFSET 0x0034 /* Power Port C pull-down control register */ +#define STM32_PWR_PUCRD_OFFSET 0x0038 /* Power Port D pull-up control register */ +#define STM32_PWR_PDCRD_OFFSET 0x003C /* Power Port D pull-down control register */ +#define STM32_PWR_PUCRE_OFFSET 0x0040 /* Power Port E pull-up control register */ +#define STM32_PWR_PUCRH_OFFSET 0x0058 /* Power Port H pull-up control register */ +#define STM32_PWR_PDCRH_OFFSET 0x005C /* Power Port H pull-down control register */ +#define STM32_PWR_C2CR1_OFFSET 0x0080 /* CPU2 control register 1 */ +#define STM32_PWR_C2CR3_OFFSET 0x0084 /* CPU2 control register 3 */ +#define STM32_PWR_EXTSCR_OFFSET 0x0088 /* Extended status and status clear register */ /* Register Addresses *******************************************************/ -#define STM32WB_PWR_CR1 (STM32WB_PWR_BASE + STM32WB_PWR_CR1_OFFSET) -#define STM32WB_PWR_CR2 (STM32WB_PWR_BASE + STM32WB_PWR_CR2_OFFSET) -#define STM32WB_PWR_CR3 (STM32WB_PWR_BASE + STM32WB_PWR_CR3_OFFSET) -#define STM32WB_PWR_CR4 (STM32WB_PWR_BASE + STM32WB_PWR_CR4_OFFSET) -#define STM32WB_PWR_SR1 (STM32WB_PWR_BASE + STM32WB_PWR_SR1_OFFSET) -#define STM32WB_PWR_SR2 (STM32WB_PWR_BASE + STM32WB_PWR_SR2_OFFSET) -#define STM32WB_PWR_SCR (STM32WB_PWR_BASE + STM32WB_PWR_SCR_OFFSET) -#define STM32WB_PWR_CR5 (STM32WB_PWR_BASE + STM32WB_PWR_CR5_OFFSET) -#define STM32WB_PWR_PUCRA (STM32WB_PWR_BASE + STM32WB_PWR_PUCRA_OFFSET) -#define STM32WB_PWR_PDCRA (STM32WB_PWR_BASE + STM32WB_PWR_PDCRA_OFFSET) -#define STM32WB_PWR_PUCRB (STM32WB_PWR_BASE + STM32WB_PWR_PUCRB_OFFSET) -#define STM32WB_PWR_PDCRB (STM32WB_PWR_BASE + STM32WB_PWR_PDCRB_OFFSET) -#define STM32WB_PWR_PUCRC (STM32WB_PWR_BASE + STM32WB_PWR_PUCRC_OFFSET) -#define STM32WB_PWR_PDCRC (STM32WB_PWR_BASE + STM32WB_PWR_PDCRC_OFFSET) -#define STM32WB_PWR_PUCRD (STM32WB_PWR_BASE + STM32WB_PWR_PUCRD_OFFSET) -#define STM32WB_PWR_PDCRD (STM32WB_PWR_BASE + STM32WB_PWR_PDCRD_OFFSET) -#define STM32WB_PWR_PUCRE (STM32WB_PWR_BASE + STM32WB_PWR_PUCRE_OFFSET) -#define STM32WB_PWR_PDCRE (STM32WB_PWR_BASE + STM32WB_PWR_PDCRE_OFFSET) -#define STM32WB_PWR_PUCRH (STM32WB_PWR_BASE + STM32WB_PWR_PUCRH_OFFSET) -#define STM32WB_PWR_PDCRH (STM32WB_PWR_BASE + STM32WB_PWR_PDCRH_OFFSET) -#define STM32WB_PWR_C2CR1 (STM32WB_PWR_BASE + STM32WB_PWR_C2CR1_OFFSET) -#define STM32WB_PWR_C2CR3 (STM32WB_PWR_BASE + STM32WB_PWR_C2CR3_OFFSET) -#define STM32WB_PWR_EXTSCR (STM32WB_PWR_BASE + STM32WB_PWR_EXTSCR_OFFSET) +#define STM32_PWR_CR1 (STM32_PWR_BASE + STM32_PWR_CR1_OFFSET) +#define STM32_PWR_CR2 (STM32_PWR_BASE + STM32_PWR_CR2_OFFSET) +#define STM32_PWR_CR3 (STM32_PWR_BASE + STM32_PWR_CR3_OFFSET) +#define STM32_PWR_CR4 (STM32_PWR_BASE + STM32_PWR_CR4_OFFSET) +#define STM32_PWR_SR1 (STM32_PWR_BASE + STM32_PWR_SR1_OFFSET) +#define STM32_PWR_SR2 (STM32_PWR_BASE + STM32_PWR_SR2_OFFSET) +#define STM32_PWR_SCR (STM32_PWR_BASE + STM32_PWR_SCR_OFFSET) +#define STM32_PWR_CR5 (STM32_PWR_BASE + STM32_PWR_CR5_OFFSET) +#define STM32_PWR_PUCRA (STM32_PWR_BASE + STM32_PWR_PUCRA_OFFSET) +#define STM32_PWR_PDCRA (STM32_PWR_BASE + STM32_PWR_PDCRA_OFFSET) +#define STM32_PWR_PUCRB (STM32_PWR_BASE + STM32_PWR_PUCRB_OFFSET) +#define STM32_PWR_PDCRB (STM32_PWR_BASE + STM32_PWR_PDCRB_OFFSET) +#define STM32_PWR_PUCRC (STM32_PWR_BASE + STM32_PWR_PUCRC_OFFSET) +#define STM32_PWR_PDCRC (STM32_PWR_BASE + STM32_PWR_PDCRC_OFFSET) +#define STM32_PWR_PUCRD (STM32_PWR_BASE + STM32_PWR_PUCRD_OFFSET) +#define STM32_PWR_PDCRD (STM32_PWR_BASE + STM32_PWR_PDCRD_OFFSET) +#define STM32_PWR_PUCRE (STM32_PWR_BASE + STM32_PWR_PUCRE_OFFSET) +#define STM32_PWR_PDCRE (STM32_PWR_BASE + STM32_PWR_PDCRE_OFFSET) +#define STM32_PWR_PUCRH (STM32_PWR_BASE + STM32_PWR_PUCRH_OFFSET) +#define STM32_PWR_PDCRH (STM32_PWR_BASE + STM32_PWR_PDCRH_OFFSET) +#define STM32_PWR_C2CR1 (STM32_PWR_BASE + STM32_PWR_C2CR1_OFFSET) +#define STM32_PWR_C2CR3 (STM32_PWR_BASE + STM32_PWR_C2CR3_OFFSET) +#define STM32_PWR_EXTSCR (STM32_PWR_BASE + STM32_PWR_EXTSCR_OFFSET) /* Register Bitfield Definitions ********************************************/ @@ -323,4 +323,4 @@ #define PWR_EXTSCR_C1DS (1 << 14) /* Bit 14: CPU1 deepsleep mode */ #define PWR_EXTSCR_C2DS (1 << 15) /* Bit 15: CPU2 deepsleep mode */ -#endif /* __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32WB_PWR_H */ +#endif /* __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32_PWR_H */ diff --git a/arch/arm/src/stm32wb/hardware/stm32wb_rcc.h b/arch/arm/src/stm32wb/hardware/stm32wb_rcc.h index 2f861e3fed2d2..3c22fdb4251ab 100644 --- a/arch/arm/src/stm32wb/hardware/stm32wb_rcc.h +++ b/arch/arm/src/stm32wb/hardware/stm32wb_rcc.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32WB_RCC_H -#define __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32WB_RCC_H +#ifndef __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32_RCC_H +#define __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32_RCC_H /**************************************************************************** * Included Files @@ -35,105 +35,105 @@ /* Register Offsets *********************************************************/ -#define STM32WB_RCC_CR_OFFSET 0x0000 /* Clock control register */ -#define STM32WB_RCC_ICSCR_OFFSET 0x0004 /* Internal clock sources calibration register */ -#define STM32WB_RCC_CFGR_OFFSET 0x0008 /* Clock configuration register */ -#define STM32WB_RCC_PLLCFG_OFFSET 0x000c /* PLL configuration register */ -#define STM32WB_RCC_PLLSAI1CFG_OFFSET 0x0010 /* PLLSAI1 configuration register */ -#define STM32WB_RCC_CIER_OFFSET 0x0018 /* Clock interrupt enable register */ -#define STM32WB_RCC_CIFR_OFFSET 0x001c /* Clock interrupt flag register */ -#define STM32WB_RCC_CICR_OFFSET 0x0020 /* Clock interrupt clear register */ -#define STM32WB_RCC_SMPSCR_OFFSET 0x0024 /* Step-down converter control register */ -#define STM32WB_RCC_AHB1RSTR_OFFSET 0x0028 /* AHB1 peripheral reset register */ -#define STM32WB_RCC_AHB2RSTR_OFFSET 0x002c /* AHB2 peripheral reset register */ -#define STM32WB_RCC_AHB3RSTR_OFFSET 0x0030 /* AHB3 peripheral reset register */ -#define STM32WB_RCC_APB1RSTR1_OFFSET 0x0038 /* APB1 Peripheral reset register 1 */ -#define STM32WB_RCC_APB1RSTR2_OFFSET 0x003c /* APB1 Peripheral reset register 2 */ -#define STM32WB_RCC_APB2RSTR_OFFSET 0x0040 /* APB2 Peripheral reset register */ -#define STM32WB_RCC_APB3RSTR_OFFSET 0x0044 /* APB3 Peripheral reset register */ -#define STM32WB_RCC_AHB1ENR_OFFSET 0x0048 /* AHB1 Peripheral Clock enable register */ -#define STM32WB_RCC_AHB2ENR_OFFSET 0x004c /* AHB2 Peripheral Clock enable register */ -#define STM32WB_RCC_AHB3ENR_OFFSET 0x0050 /* AHB3 Peripheral Clock enable register */ -#define STM32WB_RCC_APB1ENR1_OFFSET 0x0058 /* APB1 Peripheral Clock enable register 1 */ -#define STM32WB_RCC_APB1ENR2_OFFSET 0x005c /* APB1 Peripheral Clock enable register 2 */ -#define STM32WB_RCC_APB2ENR_OFFSET 0x0060 /* APB2 Peripheral Clock enable register */ -#define STM32WB_RCC_AHB1SMENR_OFFSET 0x0068 /* AHB1 clock enable in sleep and stop modes register */ -#define STM32WB_RCC_AHB2SMENR_OFFSET 0x006c /* AHB2 clock enable in sleep and stop modes register */ -#define STM32WB_RCC_AHB3SMENR_OFFSET 0x0070 /* AHB3 clock enable in sleep and stop modes register */ -#define STM32WB_RCC_APB1SMENR1_OFFSET 0x0078 /* APB1 clock enable in sleep and stop modes register 1 */ -#define STM32WB_RCC_APB1SMENR2_OFFSET 0x007c /* APB1 clock enable in sleep and stop modes register 2 */ -#define STM32WB_RCC_APB2SMENR_OFFSET 0x0080 /* APB2 clock enable in sleep and stop modes register */ -#define STM32WB_RCC_CCIPR_OFFSET 0x0088 /* Peripherals independent clock configuration register */ -#define STM32WB_RCC_BDCR_OFFSET 0x0090 /* Backup domain control register */ -#define STM32WB_RCC_CSR_OFFSET 0x0094 /* Control/status register */ -#define STM32WB_RCC_CRRCR_OFFSET 0x0098 /* Clock recovery RC register */ -#define STM32WB_RCC_HSECR_OFFSET 0x009c /* Clock HSE register */ -#define STM32WB_RCC_EXTCFGR_OFFSET 0x0108 /* Extended clock recovery register */ -#define STM32WB_RCC_C2AHB1ENR_OFFSET 0x0148 /* CPU2 AHB1 Peripheral Clock enable register */ -#define STM32WB_RCC_C2AHB2ENR_OFFSET 0x014c /* CPU2 AHB2 Peripheral Clock enable register */ -#define STM32WB_RCC_C2AHB3ENR_OFFSET 0x0150 /* CPU2 AHB3 Peripheral Clock enable register */ -#define STM32WB_RCC_C2APB1ENR1_OFFSET 0x0158 /* CPU2 APB1 Peripheral Clock enable register 1 */ -#define STM32WB_RCC_C2APB1ENR2_OFFSET 0x015c /* CPU2 APB1 Peripheral Clock enable register 2 */ -#define STM32WB_RCC_C2APB2ENR_OFFSET 0x0160 /* CPU2 APB2 Peripheral Clock enable register */ -#define STM32WB_RCC_C2APB3ENR_OFFSET 0x0164 /* CPU2 APB3 Peripheral Clock enable register */ -#define STM32WB_RCC_C2AHB1SMENR_OFFSET 0x0168 /* CPU2 AHB1 clock enable in sleep and stop modes register */ -#define STM32WB_RCC_C2AHB2SMENR_OFFSET 0x016c /* CPU2 AHB2 clock enable in sleep and stop modes register */ -#define STM32WB_RCC_C2AHB3SMENR_OFFSET 0x0170 /* CPU2 AHB3 clock enable in sleep and stop modes register */ -#define STM32WB_RCC_C2APB1SMENR1_OFFSET 0x0178 /* CPU2 APB1 clock enable in sleep and stop modes register 1 */ -#define STM32WB_RCC_C2APB1SMENR2_OFFSET 0x017c /* CPU2 APB1 clock enable in sleep and stop modes register 2 */ -#define STM32WB_RCC_C2APB2SMENR_OFFSET 0x0180 /* CPU2 APB2 clock enable in sleep and stop modes register */ -#define STM32WB_RCC_C2APB3SMENR_OFFSET 0x0184 /* CPU2 APB3 clock enable in sleep and stop modes register */ +#define STM32_RCC_CR_OFFSET 0x0000 /* Clock control register */ +#define STM32_RCC_ICSCR_OFFSET 0x0004 /* Internal clock sources calibration register */ +#define STM32_RCC_CFGR_OFFSET 0x0008 /* Clock configuration register */ +#define STM32_RCC_PLLCFG_OFFSET 0x000c /* PLL configuration register */ +#define STM32_RCC_PLLSAI1CFG_OFFSET 0x0010 /* PLLSAI1 configuration register */ +#define STM32_RCC_CIER_OFFSET 0x0018 /* Clock interrupt enable register */ +#define STM32_RCC_CIFR_OFFSET 0x001c /* Clock interrupt flag register */ +#define STM32_RCC_CICR_OFFSET 0x0020 /* Clock interrupt clear register */ +#define STM32_RCC_SMPSCR_OFFSET 0x0024 /* Step-down converter control register */ +#define STM32_RCC_AHB1RSTR_OFFSET 0x0028 /* AHB1 peripheral reset register */ +#define STM32_RCC_AHB2RSTR_OFFSET 0x002c /* AHB2 peripheral reset register */ +#define STM32_RCC_AHB3RSTR_OFFSET 0x0030 /* AHB3 peripheral reset register */ +#define STM32_RCC_APB1RSTR1_OFFSET 0x0038 /* APB1 Peripheral reset register 1 */ +#define STM32_RCC_APB1RSTR2_OFFSET 0x003c /* APB1 Peripheral reset register 2 */ +#define STM32_RCC_APB2RSTR_OFFSET 0x0040 /* APB2 Peripheral reset register */ +#define STM32_RCC_APB3RSTR_OFFSET 0x0044 /* APB3 Peripheral reset register */ +#define STM32_RCC_AHB1ENR_OFFSET 0x0048 /* AHB1 Peripheral Clock enable register */ +#define STM32_RCC_AHB2ENR_OFFSET 0x004c /* AHB2 Peripheral Clock enable register */ +#define STM32_RCC_AHB3ENR_OFFSET 0x0050 /* AHB3 Peripheral Clock enable register */ +#define STM32_RCC_APB1ENR1_OFFSET 0x0058 /* APB1 Peripheral Clock enable register 1 */ +#define STM32_RCC_APB1ENR2_OFFSET 0x005c /* APB1 Peripheral Clock enable register 2 */ +#define STM32_RCC_APB2ENR_OFFSET 0x0060 /* APB2 Peripheral Clock enable register */ +#define STM32_RCC_AHB1SMENR_OFFSET 0x0068 /* AHB1 clock enable in sleep and stop modes register */ +#define STM32_RCC_AHB2SMENR_OFFSET 0x006c /* AHB2 clock enable in sleep and stop modes register */ +#define STM32_RCC_AHB3SMENR_OFFSET 0x0070 /* AHB3 clock enable in sleep and stop modes register */ +#define STM32_RCC_APB1SMENR1_OFFSET 0x0078 /* APB1 clock enable in sleep and stop modes register 1 */ +#define STM32_RCC_APB1SMENR2_OFFSET 0x007c /* APB1 clock enable in sleep and stop modes register 2 */ +#define STM32_RCC_APB2SMENR_OFFSET 0x0080 /* APB2 clock enable in sleep and stop modes register */ +#define STM32_RCC_CCIPR_OFFSET 0x0088 /* Peripherals independent clock configuration register */ +#define STM32_RCC_BDCR_OFFSET 0x0090 /* Backup domain control register */ +#define STM32_RCC_CSR_OFFSET 0x0094 /* Control/status register */ +#define STM32_RCC_CRRCR_OFFSET 0x0098 /* Clock recovery RC register */ +#define STM32_RCC_HSECR_OFFSET 0x009c /* Clock HSE register */ +#define STM32_RCC_EXTCFGR_OFFSET 0x0108 /* Extended clock recovery register */ +#define STM32_RCC_C2AHB1ENR_OFFSET 0x0148 /* CPU2 AHB1 Peripheral Clock enable register */ +#define STM32_RCC_C2AHB2ENR_OFFSET 0x014c /* CPU2 AHB2 Peripheral Clock enable register */ +#define STM32_RCC_C2AHB3ENR_OFFSET 0x0150 /* CPU2 AHB3 Peripheral Clock enable register */ +#define STM32_RCC_C2APB1ENR1_OFFSET 0x0158 /* CPU2 APB1 Peripheral Clock enable register 1 */ +#define STM32_RCC_C2APB1ENR2_OFFSET 0x015c /* CPU2 APB1 Peripheral Clock enable register 2 */ +#define STM32_RCC_C2APB2ENR_OFFSET 0x0160 /* CPU2 APB2 Peripheral Clock enable register */ +#define STM32_RCC_C2APB3ENR_OFFSET 0x0164 /* CPU2 APB3 Peripheral Clock enable register */ +#define STM32_RCC_C2AHB1SMENR_OFFSET 0x0168 /* CPU2 AHB1 clock enable in sleep and stop modes register */ +#define STM32_RCC_C2AHB2SMENR_OFFSET 0x016c /* CPU2 AHB2 clock enable in sleep and stop modes register */ +#define STM32_RCC_C2AHB3SMENR_OFFSET 0x0170 /* CPU2 AHB3 clock enable in sleep and stop modes register */ +#define STM32_RCC_C2APB1SMENR1_OFFSET 0x0178 /* CPU2 APB1 clock enable in sleep and stop modes register 1 */ +#define STM32_RCC_C2APB1SMENR2_OFFSET 0x017c /* CPU2 APB1 clock enable in sleep and stop modes register 2 */ +#define STM32_RCC_C2APB2SMENR_OFFSET 0x0180 /* CPU2 APB2 clock enable in sleep and stop modes register */ +#define STM32_RCC_C2APB3SMENR_OFFSET 0x0184 /* CPU2 APB3 clock enable in sleep and stop modes register */ /* Register Addresses *******************************************************/ -#define STM32WB_RCC_CR (STM32WB_RCC_BASE + STM32WB_RCC_CR_OFFSET) -#define STM32WB_RCC_ICSCR (STM32WB_RCC_BASE + STM32WB_RCC_ICSCR_OFFSET) -#define STM32WB_RCC_CFGR (STM32WB_RCC_BASE + STM32WB_RCC_CFGR_OFFSET) -#define STM32WB_RCC_PLLCFG (STM32WB_RCC_BASE + STM32WB_RCC_PLLCFG_OFFSET) -#define STM32WB_RCC_PLLSAI1CFG (STM32WB_RCC_BASE + STM32WB_RCC_PLLSAI1CFG_OFFSET) -#define STM32WB_RCC_CIER (STM32WB_RCC_BASE + STM32WB_RCC_CIER_OFFSET) -#define STM32WB_RCC_CIFR (STM32WB_RCC_BASE + STM32WB_RCC_CIFR_OFFSET) -#define STM32WB_RCC_CICR (STM32WB_RCC_BASE + STM32WB_RCC_CICR_OFFSET) -#define STM32WB_RCC_SMPSCR (STM32WB_RCC_BASE + STM32WB_RCC_SMPSCR_OFFSET) -#define STM32WB_RCC_AHB1RSTR (STM32WB_RCC_BASE + STM32WB_RCC_AHB1RSTR_OFFSET) -#define STM32WB_RCC_AHB2RSTR (STM32WB_RCC_BASE + STM32WB_RCC_AHB2RSTR_OFFSET) -#define STM32WB_RCC_AHB3RSTR (STM32WB_RCC_BASE + STM32WB_RCC_AHB3RSTR_OFFSET) -#define STM32WB_RCC_APB1RSTR1 (STM32WB_RCC_BASE + STM32WB_RCC_APB1RSTR1_OFFSET) -#define STM32WB_RCC_APB1RSTR2 (STM32WB_RCC_BASE + STM32WB_RCC_APB1RSTR2_OFFSET) -#define STM32WB_RCC_APB2RSTR (STM32WB_RCC_BASE + STM32WB_RCC_APB2RSTR_OFFSET) -#define STM32WB_RCC_APB3RSTR (STM32WB_RCC_BASE + STM32WB_RCC_APB3RSTR_OFFSET) -#define STM32WB_RCC_AHB1ENR (STM32WB_RCC_BASE + STM32WB_RCC_AHB1ENR_OFFSET) -#define STM32WB_RCC_AHB2ENR (STM32WB_RCC_BASE + STM32WB_RCC_AHB2ENR_OFFSET) -#define STM32WB_RCC_AHB3ENR (STM32WB_RCC_BASE + STM32WB_RCC_AHB3ENR_OFFSET) -#define STM32WB_RCC_APB1ENR1 (STM32WB_RCC_BASE + STM32WB_RCC_APB1ENR1_OFFSET) -#define STM32WB_RCC_APB1ENR2 (STM32WB_RCC_BASE + STM32WB_RCC_APB1ENR2_OFFSET) -#define STM32WB_RCC_APB2ENR (STM32WB_RCC_BASE + STM32WB_RCC_APB2ENR_OFFSET) -#define STM32WB_RCC_AHB1SMENR (STM32WB_RCC_BASE + STM32WB_RCC_AHB1SMENR_OFFSET) -#define STM32WB_RCC_AHB2SMENR (STM32WB_RCC_BASE + STM32WB_RCC_AHB2SMENR_OFFSET) -#define STM32WB_RCC_AHB3SMENR (STM32WB_RCC_BASE + STM32WB_RCC_AHB3SMENR_OFFSET) -#define STM32WB_RCC_APB1SMENR1 (STM32WB_RCC_BASE + STM32WB_RCC_APB1SMENR1_OFFSET) -#define STM32WB_RCC_APB1SMENR2 (STM32WB_RCC_BASE + STM32WB_RCC_APB1SMENR2_OFFSET) -#define STM32WB_RCC_APB2SMENR (STM32WB_RCC_BASE + STM32WB_RCC_APB2SMENR_OFFSET) -#define STM32WB_RCC_CCIPR (STM32WB_RCC_BASE + STM32WB_RCC_CCIPR_OFFSET) -#define STM32WB_RCC_BDCR (STM32WB_RCC_BASE + STM32WB_RCC_BDCR_OFFSET) -#define STM32WB_RCC_CSR (STM32WB_RCC_BASE + STM32WB_RCC_CSR_OFFSET) -#define STM32WB_RCC_CRRCR (STM32WB_RCC_BASE + STM32WB_RCC_CRRCR_OFFSET) -#define STM32WB_RCC_HSECR (STM32WB_RCC_BASE + STM32WB_RCC_HSECR_OFFSET) -#define STM32WB_RCC_EXTCFGR (STM32WB_RCC_BASE + STM32WB_RCC_EXTCFGR_OFFSET) -#define STM32WB_RCC_C2AHB1ENR (STM32WB_RCC_BASE + STM32WB_RCC_C2AHB1ENR_OFFSET) -#define STM32WB_RCC_C2AHB2ENR (STM32WB_RCC_BASE + STM32WB_RCC_C2AHB2ENR_OFFSET) -#define STM32WB_RCC_C2AHB3ENR (STM32WB_RCC_BASE + STM32WB_RCC_C2AHB3ENR_OFFSET) -#define STM32WB_RCC_C2APB1ENR1 (STM32WB_RCC_BASE + STM32WB_RCC_C2APB1ENR1_OFFSET) -#define STM32WB_RCC_C2APB1ENR2 (STM32WB_RCC_BASE + STM32WB_RCC_C2APB1ENR2_OFFSET) -#define STM32WB_RCC_C2APB2ENR (STM32WB_RCC_BASE + STM32WB_RCC_C2APB2ENR_OFFSET) -#define STM32WB_RCC_C2APB3ENR (STM32WB_RCC_BASE + STM32WB_RCC_C2APB3ENR_OFFSET) -#define STM32WB_RCC_C2AHB1SMENR (STM32WB_RCC_BASE + STM32WB_RCC_C2AHB1SMENR_OFFSET) -#define STM32WB_RCC_C2AHB2SMENR (STM32WB_RCC_BASE + STM32WB_RCC_C2AHB2SMENR_OFFSET) -#define STM32WB_RCC_C2AHB3SMENR (STM32WB_RCC_BASE + STM32WB_RCC_C2AHB3SMENR_OFFSET) -#define STM32WB_RCC_C2APB1SMENR1 (STM32WB_RCC_BASE + STM32WB_RCC_C2APB1SMENR1_OFFSET) -#define STM32WB_RCC_C2APB1SMENR2 (STM32WB_RCC_BASE + STM32WB_RCC_C2APB1SMENR2_OFFSET) -#define STM32WB_RCC_C2APB2SMENR (STM32WB_RCC_BASE + STM32WB_RCC_C2APB2SMENR_OFFSET) -#define STM32WB_RCC_C2APB3SMENR (STM32WB_RCC_BASE + STM32WB_RCC_C2APB3SMENR_OFFSET) +#define STM32_RCC_CR (STM32_RCC_BASE + STM32_RCC_CR_OFFSET) +#define STM32_RCC_ICSCR (STM32_RCC_BASE + STM32_RCC_ICSCR_OFFSET) +#define STM32_RCC_CFGR (STM32_RCC_BASE + STM32_RCC_CFGR_OFFSET) +#define STM32_RCC_PLLCFG (STM32_RCC_BASE + STM32_RCC_PLLCFG_OFFSET) +#define STM32_RCC_PLLSAI1CFG (STM32_RCC_BASE + STM32_RCC_PLLSAI1CFG_OFFSET) +#define STM32_RCC_CIER (STM32_RCC_BASE + STM32_RCC_CIER_OFFSET) +#define STM32_RCC_CIFR (STM32_RCC_BASE + STM32_RCC_CIFR_OFFSET) +#define STM32_RCC_CICR (STM32_RCC_BASE + STM32_RCC_CICR_OFFSET) +#define STM32_RCC_SMPSCR (STM32_RCC_BASE + STM32_RCC_SMPSCR_OFFSET) +#define STM32_RCC_AHB1RSTR (STM32_RCC_BASE + STM32_RCC_AHB1RSTR_OFFSET) +#define STM32_RCC_AHB2RSTR (STM32_RCC_BASE + STM32_RCC_AHB2RSTR_OFFSET) +#define STM32_RCC_AHB3RSTR (STM32_RCC_BASE + STM32_RCC_AHB3RSTR_OFFSET) +#define STM32_RCC_APB1RSTR1 (STM32_RCC_BASE + STM32_RCC_APB1RSTR1_OFFSET) +#define STM32_RCC_APB1RSTR2 (STM32_RCC_BASE + STM32_RCC_APB1RSTR2_OFFSET) +#define STM32_RCC_APB2RSTR (STM32_RCC_BASE + STM32_RCC_APB2RSTR_OFFSET) +#define STM32_RCC_APB3RSTR (STM32_RCC_BASE + STM32_RCC_APB3RSTR_OFFSET) +#define STM32_RCC_AHB1ENR (STM32_RCC_BASE + STM32_RCC_AHB1ENR_OFFSET) +#define STM32_RCC_AHB2ENR (STM32_RCC_BASE + STM32_RCC_AHB2ENR_OFFSET) +#define STM32_RCC_AHB3ENR (STM32_RCC_BASE + STM32_RCC_AHB3ENR_OFFSET) +#define STM32_RCC_APB1ENR1 (STM32_RCC_BASE + STM32_RCC_APB1ENR1_OFFSET) +#define STM32_RCC_APB1ENR2 (STM32_RCC_BASE + STM32_RCC_APB1ENR2_OFFSET) +#define STM32_RCC_APB2ENR (STM32_RCC_BASE + STM32_RCC_APB2ENR_OFFSET) +#define STM32_RCC_AHB1SMENR (STM32_RCC_BASE + STM32_RCC_AHB1SMENR_OFFSET) +#define STM32_RCC_AHB2SMENR (STM32_RCC_BASE + STM32_RCC_AHB2SMENR_OFFSET) +#define STM32_RCC_AHB3SMENR (STM32_RCC_BASE + STM32_RCC_AHB3SMENR_OFFSET) +#define STM32_RCC_APB1SMENR1 (STM32_RCC_BASE + STM32_RCC_APB1SMENR1_OFFSET) +#define STM32_RCC_APB1SMENR2 (STM32_RCC_BASE + STM32_RCC_APB1SMENR2_OFFSET) +#define STM32_RCC_APB2SMENR (STM32_RCC_BASE + STM32_RCC_APB2SMENR_OFFSET) +#define STM32_RCC_CCIPR (STM32_RCC_BASE + STM32_RCC_CCIPR_OFFSET) +#define STM32_RCC_BDCR (STM32_RCC_BASE + STM32_RCC_BDCR_OFFSET) +#define STM32_RCC_CSR (STM32_RCC_BASE + STM32_RCC_CSR_OFFSET) +#define STM32_RCC_CRRCR (STM32_RCC_BASE + STM32_RCC_CRRCR_OFFSET) +#define STM32_RCC_HSECR (STM32_RCC_BASE + STM32_RCC_HSECR_OFFSET) +#define STM32_RCC_EXTCFGR (STM32_RCC_BASE + STM32_RCC_EXTCFGR_OFFSET) +#define STM32_RCC_C2AHB1ENR (STM32_RCC_BASE + STM32_RCC_C2AHB1ENR_OFFSET) +#define STM32_RCC_C2AHB2ENR (STM32_RCC_BASE + STM32_RCC_C2AHB2ENR_OFFSET) +#define STM32_RCC_C2AHB3ENR (STM32_RCC_BASE + STM32_RCC_C2AHB3ENR_OFFSET) +#define STM32_RCC_C2APB1ENR1 (STM32_RCC_BASE + STM32_RCC_C2APB1ENR1_OFFSET) +#define STM32_RCC_C2APB1ENR2 (STM32_RCC_BASE + STM32_RCC_C2APB1ENR2_OFFSET) +#define STM32_RCC_C2APB2ENR (STM32_RCC_BASE + STM32_RCC_C2APB2ENR_OFFSET) +#define STM32_RCC_C2APB3ENR (STM32_RCC_BASE + STM32_RCC_C2APB3ENR_OFFSET) +#define STM32_RCC_C2AHB1SMENR (STM32_RCC_BASE + STM32_RCC_C2AHB1SMENR_OFFSET) +#define STM32_RCC_C2AHB2SMENR (STM32_RCC_BASE + STM32_RCC_C2AHB2SMENR_OFFSET) +#define STM32_RCC_C2AHB3SMENR (STM32_RCC_BASE + STM32_RCC_C2AHB3SMENR_OFFSET) +#define STM32_RCC_C2APB1SMENR1 (STM32_RCC_BASE + STM32_RCC_C2APB1SMENR1_OFFSET) +#define STM32_RCC_C2APB1SMENR2 (STM32_RCC_BASE + STM32_RCC_C2APB1SMENR2_OFFSET) +#define STM32_RCC_C2APB2SMENR (STM32_RCC_BASE + STM32_RCC_C2APB2SMENR_OFFSET) +#define STM32_RCC_C2APB3SMENR (STM32_RCC_BASE + STM32_RCC_C2APB3SMENR_OFFSET) /* Register Bitfield Definitions ********************************************/ @@ -876,4 +876,4 @@ #define RCC_C2APB3ENR_BLEEN (1 << 0) /* Bit 0: CPU2 LPUART1 enable in sleep and stop modes */ #define RCC_C2APB3ENR_802EN (1 << 1) /* Bit 1: CPU2 LPTIM2 enable in sleep and stop modes */ -#endif /* __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32WB_RCC_H */ +#endif /* __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32_RCC_H */ diff --git a/arch/arm/src/stm32wb/hardware/stm32wb_rtc.h b/arch/arm/src/stm32wb/hardware/stm32wb_rtc.h index b02dfbcd959b9..d204aae5ddc75 100644 --- a/arch/arm/src/stm32wb/hardware/stm32wb_rtc.h +++ b/arch/arm/src/stm32wb/hardware/stm32wb_rtc.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32WB_RTCC_H -#define __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32WB_RTCC_H +#ifndef __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32_RTCC_H +#define __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32_RTCC_H /**************************************************************************** * Pre-processor Definitions @@ -29,93 +29,93 @@ /* Register Offsets *********************************************************/ -#define STM32WB_RTC_TR_OFFSET 0x0000 /* RTC time register */ -#define STM32WB_RTC_DR_OFFSET 0x0004 /* RTC date register */ -#define STM32WB_RTC_CR_OFFSET 0x0008 /* RTC control register */ -#define STM32WB_RTC_ISR_OFFSET 0x000c /* RTC initialization and status register */ -#define STM32WB_RTC_PRER_OFFSET 0x0010 /* RTC prescaler register */ -#define STM32WB_RTC_WUTR_OFFSET 0x0014 /* RTC wakeup timer register */ -#define STM32WB_RTC_ALRMAR_OFFSET 0x001c /* RTC alarm A register */ -#define STM32WB_RTC_ALRMBR_OFFSET 0x0020 /* RTC alarm B register */ -#define STM32WB_RTC_WPR_OFFSET 0x0024 /* RTC write protection register */ -#define STM32WB_RTC_SSR_OFFSET 0x0028 /* RTC sub second register */ -#define STM32WB_RTC_SHIFTR_OFFSET 0x002c /* RTC shift control register */ -#define STM32WB_RTC_TSTR_OFFSET 0x0030 /* RTC time stamp time register */ -#define STM32WB_RTC_TSDR_OFFSET 0x0034 /* RTC time stamp date register */ -#define STM32WB_RTC_TSSSR_OFFSET 0x0038 /* RTC timestamp sub second register */ -#define STM32WB_RTC_CALR_OFFSET 0x003c /* RTC calibration register */ -#define STM32WB_RTC_TAMPCR_OFFSET 0x0040 /* RTC tamper configuration register */ -#define STM32WB_RTC_ALRMASSR_OFFSET 0x0044 /* RTC alarm A sub second register */ -#define STM32WB_RTC_ALRMBSSR_OFFSET 0x0048 /* RTC alarm B sub second register */ -#define STM32WB_RTC_OR_OFFSET 0x004c /* RTC option register */ - -#define STM32WB_RTC_BKPR_OFFSET(n) (0x0050 + ((n) << 2)) -#define STM32WB_RTC_BKP0R_OFFSET 0x0050 /* RTC backup register 0 */ -#define STM32WB_RTC_BKP1R_OFFSET 0x0054 /* RTC backup register 1 */ -#define STM32WB_RTC_BKP2R_OFFSET 0x0058 /* RTC backup register 2 */ -#define STM32WB_RTC_BKP3R_OFFSET 0x005c /* RTC backup register 3 */ -#define STM32WB_RTC_BKP4R_OFFSET 0x0060 /* RTC backup register 4 */ -#define STM32WB_RTC_BKP5R_OFFSET 0x0064 /* RTC backup register 5 */ -#define STM32WB_RTC_BKP6R_OFFSET 0x0068 /* RTC backup register 6 */ -#define STM32WB_RTC_BKP7R_OFFSET 0x006c /* RTC backup register 7 */ -#define STM32WB_RTC_BKP8R_OFFSET 0x0070 /* RTC backup register 8 */ -#define STM32WB_RTC_BKP9R_OFFSET 0x0074 /* RTC backup register 9 */ -#define STM32WB_RTC_BKP10R_OFFSET 0x0078 /* RTC backup register 10 */ -#define STM32WB_RTC_BKP11R_OFFSET 0x007c /* RTC backup register 11 */ -#define STM32WB_RTC_BKP12R_OFFSET 0x0080 /* RTC backup register 12 */ -#define STM32WB_RTC_BKP13R_OFFSET 0x0084 /* RTC backup register 13 */ -#define STM32WB_RTC_BKP14R_OFFSET 0x0088 /* RTC backup register 14 */ -#define STM32WB_RTC_BKP15R_OFFSET 0x008c /* RTC backup register 15 */ -#define STM32WB_RTC_BKP16R_OFFSET 0x0090 /* RTC backup register 16 */ -#define STM32WB_RTC_BKP17R_OFFSET 0x0094 /* RTC backup register 17 */ -#define STM32WB_RTC_BKP18R_OFFSET 0x0098 /* RTC backup register 18 */ -#define STM32WB_RTC_BKP19R_OFFSET 0x009c /* RTC backup register 19 */ +#define STM32_RTC_TR_OFFSET 0x0000 /* RTC time register */ +#define STM32_RTC_DR_OFFSET 0x0004 /* RTC date register */ +#define STM32_RTC_CR_OFFSET 0x0008 /* RTC control register */ +#define STM32_RTC_ISR_OFFSET 0x000c /* RTC initialization and status register */ +#define STM32_RTC_PRER_OFFSET 0x0010 /* RTC prescaler register */ +#define STM32_RTC_WUTR_OFFSET 0x0014 /* RTC wakeup timer register */ +#define STM32_RTC_ALRMAR_OFFSET 0x001c /* RTC alarm A register */ +#define STM32_RTC_ALRMBR_OFFSET 0x0020 /* RTC alarm B register */ +#define STM32_RTC_WPR_OFFSET 0x0024 /* RTC write protection register */ +#define STM32_RTC_SSR_OFFSET 0x0028 /* RTC sub second register */ +#define STM32_RTC_SHIFTR_OFFSET 0x002c /* RTC shift control register */ +#define STM32_RTC_TSTR_OFFSET 0x0030 /* RTC time stamp time register */ +#define STM32_RTC_TSDR_OFFSET 0x0034 /* RTC time stamp date register */ +#define STM32_RTC_TSSSR_OFFSET 0x0038 /* RTC timestamp sub second register */ +#define STM32_RTC_CALR_OFFSET 0x003c /* RTC calibration register */ +#define STM32_RTC_TAMPCR_OFFSET 0x0040 /* RTC tamper configuration register */ +#define STM32_RTC_ALRMASSR_OFFSET 0x0044 /* RTC alarm A sub second register */ +#define STM32_RTC_ALRMBSSR_OFFSET 0x0048 /* RTC alarm B sub second register */ +#define STM32_RTC_OR_OFFSET 0x004c /* RTC option register */ + +#define STM32_RTC_BKPR_OFFSET(n) (0x0050 + ((n) << 2)) +#define STM32_RTC_BKP0R_OFFSET 0x0050 /* RTC backup register 0 */ +#define STM32_RTC_BKP1R_OFFSET 0x0054 /* RTC backup register 1 */ +#define STM32_RTC_BKP2R_OFFSET 0x0058 /* RTC backup register 2 */ +#define STM32_RTC_BKP3R_OFFSET 0x005c /* RTC backup register 3 */ +#define STM32_RTC_BKP4R_OFFSET 0x0060 /* RTC backup register 4 */ +#define STM32_RTC_BKP5R_OFFSET 0x0064 /* RTC backup register 5 */ +#define STM32_RTC_BKP6R_OFFSET 0x0068 /* RTC backup register 6 */ +#define STM32_RTC_BKP7R_OFFSET 0x006c /* RTC backup register 7 */ +#define STM32_RTC_BKP8R_OFFSET 0x0070 /* RTC backup register 8 */ +#define STM32_RTC_BKP9R_OFFSET 0x0074 /* RTC backup register 9 */ +#define STM32_RTC_BKP10R_OFFSET 0x0078 /* RTC backup register 10 */ +#define STM32_RTC_BKP11R_OFFSET 0x007c /* RTC backup register 11 */ +#define STM32_RTC_BKP12R_OFFSET 0x0080 /* RTC backup register 12 */ +#define STM32_RTC_BKP13R_OFFSET 0x0084 /* RTC backup register 13 */ +#define STM32_RTC_BKP14R_OFFSET 0x0088 /* RTC backup register 14 */ +#define STM32_RTC_BKP15R_OFFSET 0x008c /* RTC backup register 15 */ +#define STM32_RTC_BKP16R_OFFSET 0x0090 /* RTC backup register 16 */ +#define STM32_RTC_BKP17R_OFFSET 0x0094 /* RTC backup register 17 */ +#define STM32_RTC_BKP18R_OFFSET 0x0098 /* RTC backup register 18 */ +#define STM32_RTC_BKP19R_OFFSET 0x009c /* RTC backup register 19 */ /* Register Addresses *******************************************************/ -#define STM32WB_RTC_TR (STM32WB_RTC_BASE + STM32WB_RTC_TR_OFFSET) -#define STM32WB_RTC_DR (STM32WB_RTC_BASE + STM32WB_RTC_DR_OFFSET) -#define STM32WB_RTC_CR (STM32WB_RTC_BASE + STM32WB_RTC_CR_OFFSET) -#define STM32WB_RTC_ISR (STM32WB_RTC_BASE + STM32WB_RTC_ISR_OFFSET) -#define STM32WB_RTC_PRER (STM32WB_RTC_BASE + STM32WB_RTC_PRER_OFFSET) -#define STM32WB_RTC_WUTR (STM32WB_RTC_BASE + STM32WB_RTC_WUTR_OFFSET) -#define STM32WB_RTC_ALRMAR (STM32WB_RTC_BASE + STM32WB_RTC_ALRMAR_OFFSET) -#define STM32WB_RTC_ALRMBR (STM32WB_RTC_BASE + STM32WB_RTC_ALRMBR_OFFSET) -#define STM32WB_RTC_WPR (STM32WB_RTC_BASE + STM32WB_RTC_WPR_OFFSET) -#define STM32WB_RTC_SSR (STM32WB_RTC_BASE + STM32WB_RTC_SSR_OFFSET) -#define STM32WB_RTC_SHIFTR (STM32WB_RTC_BASE + STM32WB_RTC_SHIFTR_OFFSET) -#define STM32WB_RTC_TSTR (STM32WB_RTC_BASE + STM32WB_RTC_TSTR_OFFSET) -#define STM32WB_RTC_TSDR (STM32WB_RTC_BASE + STM32WB_RTC_TSDR_OFFSET) -#define STM32WB_RTC_TSSSR (STM32WB_RTC_BASE + STM32WB_RTC_TSSSR_OFFSET) -#define STM32WB_RTC_CALR (STM32WB_RTC_BASE + STM32WB_RTC_CALR_OFFSET) -#define STM32WB_RTC_TAMPCR (STM32WB_RTC_BASE + STM32WB_RTC_TAMPCR_OFFSET) -#define STM32WB_RTC_ALRMASSR (STM32WB_RTC_BASE + STM32WB_RTC_ALRMASSR_OFFSET) -#define STM32WB_RTC_ALRMBSSR (STM32WB_RTC_BASE + STM32WB_RTC_ALRMBSSR_OFFSET) -#define STM32WB_RTC_OR (STM32WB_RTC_BASE + STM32WB_RTC_OR_OFFSET) - -#define STM32WB_RTC_BKPR(n) (STM32WB_RTC_BASE + STM32WB_RTC_BKPR_OFFSET(n)) -#define STM32WB_RTC_BKP0R (STM32WB_RTC_BASE + STM32WB_RTC_BKP0R_OFFSET) -#define STM32WB_RTC_BKP1R (STM32WB_RTC_BASE + STM32WB_RTC_BKP1R_OFFSET) -#define STM32WB_RTC_BKP2R (STM32WB_RTC_BASE + STM32WB_RTC_BKP2R_OFFSET) -#define STM32WB_RTC_BKP3R (STM32WB_RTC_BASE + STM32WB_RTC_BKP3R_OFFSET) -#define STM32WB_RTC_BKP4R (STM32WB_RTC_BASE + STM32WB_RTC_BKP4R_OFFSET) -#define STM32WB_RTC_BKP5R (STM32WB_RTC_BASE + STM32WB_RTC_BKP5R_OFFSET) -#define STM32WB_RTC_BKP6R (STM32WB_RTC_BASE + STM32WB_RTC_BKP6R_OFFSET) -#define STM32WB_RTC_BKP7R (STM32WB_RTC_BASE + STM32WB_RTC_BKP7R_OFFSET) -#define STM32WB_RTC_BKP8R (STM32WB_RTC_BASE + STM32WB_RTC_BKP8R_OFFSET) -#define STM32WB_RTC_BKP9R (STM32WB_RTC_BASE + STM32WB_RTC_BKP9R_OFFSET) -#define STM32WB_RTC_BKP10R (STM32WB_RTC_BASE + STM32WB_RTC_BKP10R_OFFSET) -#define STM32WB_RTC_BKP11R (STM32WB_RTC_BASE + STM32WB_RTC_BKP11R_OFFSET) -#define STM32WB_RTC_BKP12R (STM32WB_RTC_BASE + STM32WB_RTC_BKP12R_OFFSET) -#define STM32WB_RTC_BKP13R (STM32WB_RTC_BASE + STM32WB_RTC_BKP13R_OFFSET) -#define STM32WB_RTC_BKP14R (STM32WB_RTC_BASE + STM32WB_RTC_BKP14R_OFFSET) -#define STM32WB_RTC_BKP15R (STM32WB_RTC_BASE + STM32WB_RTC_BKP15R_OFFSET) -#define STM32WB_RTC_BKP16R (STM32WB_RTC_BASE + STM32WB_RTC_BKP16R_OFFSET) -#define STM32WB_RTC_BKP17R (STM32WB_RTC_BASE + STM32WB_RTC_BKP17R_OFFSET) -#define STM32WB_RTC_BKP18R (STM32WB_RTC_BASE + STM32WB_RTC_BKP18R_OFFSET) -#define STM32WB_RTC_BKP19R (STM32WB_RTC_BASE + STM32WB_RTC_BKP19R_OFFSET) - -# define STM32WB_RTC_BKCOUNT 20 +#define STM32_RTC_TR (STM32_RTC_BASE + STM32_RTC_TR_OFFSET) +#define STM32_RTC_DR (STM32_RTC_BASE + STM32_RTC_DR_OFFSET) +#define STM32_RTC_CR (STM32_RTC_BASE + STM32_RTC_CR_OFFSET) +#define STM32_RTC_ISR (STM32_RTC_BASE + STM32_RTC_ISR_OFFSET) +#define STM32_RTC_PRER (STM32_RTC_BASE + STM32_RTC_PRER_OFFSET) +#define STM32_RTC_WUTR (STM32_RTC_BASE + STM32_RTC_WUTR_OFFSET) +#define STM32_RTC_ALRMAR (STM32_RTC_BASE + STM32_RTC_ALRMAR_OFFSET) +#define STM32_RTC_ALRMBR (STM32_RTC_BASE + STM32_RTC_ALRMBR_OFFSET) +#define STM32_RTC_WPR (STM32_RTC_BASE + STM32_RTC_WPR_OFFSET) +#define STM32_RTC_SSR (STM32_RTC_BASE + STM32_RTC_SSR_OFFSET) +#define STM32_RTC_SHIFTR (STM32_RTC_BASE + STM32_RTC_SHIFTR_OFFSET) +#define STM32_RTC_TSTR (STM32_RTC_BASE + STM32_RTC_TSTR_OFFSET) +#define STM32_RTC_TSDR (STM32_RTC_BASE + STM32_RTC_TSDR_OFFSET) +#define STM32_RTC_TSSSR (STM32_RTC_BASE + STM32_RTC_TSSSR_OFFSET) +#define STM32_RTC_CALR (STM32_RTC_BASE + STM32_RTC_CALR_OFFSET) +#define STM32_RTC_TAMPCR (STM32_RTC_BASE + STM32_RTC_TAMPCR_OFFSET) +#define STM32_RTC_ALRMASSR (STM32_RTC_BASE + STM32_RTC_ALRMASSR_OFFSET) +#define STM32_RTC_ALRMBSSR (STM32_RTC_BASE + STM32_RTC_ALRMBSSR_OFFSET) +#define STM32_RTC_OR (STM32_RTC_BASE + STM32_RTC_OR_OFFSET) + +#define STM32_RTC_BKPR(n) (STM32_RTC_BASE + STM32_RTC_BKPR_OFFSET(n)) +#define STM32_RTC_BKP0R (STM32_RTC_BASE + STM32_RTC_BKP0R_OFFSET) +#define STM32_RTC_BKP1R (STM32_RTC_BASE + STM32_RTC_BKP1R_OFFSET) +#define STM32_RTC_BKP2R (STM32_RTC_BASE + STM32_RTC_BKP2R_OFFSET) +#define STM32_RTC_BKP3R (STM32_RTC_BASE + STM32_RTC_BKP3R_OFFSET) +#define STM32_RTC_BKP4R (STM32_RTC_BASE + STM32_RTC_BKP4R_OFFSET) +#define STM32_RTC_BKP5R (STM32_RTC_BASE + STM32_RTC_BKP5R_OFFSET) +#define STM32_RTC_BKP6R (STM32_RTC_BASE + STM32_RTC_BKP6R_OFFSET) +#define STM32_RTC_BKP7R (STM32_RTC_BASE + STM32_RTC_BKP7R_OFFSET) +#define STM32_RTC_BKP8R (STM32_RTC_BASE + STM32_RTC_BKP8R_OFFSET) +#define STM32_RTC_BKP9R (STM32_RTC_BASE + STM32_RTC_BKP9R_OFFSET) +#define STM32_RTC_BKP10R (STM32_RTC_BASE + STM32_RTC_BKP10R_OFFSET) +#define STM32_RTC_BKP11R (STM32_RTC_BASE + STM32_RTC_BKP11R_OFFSET) +#define STM32_RTC_BKP12R (STM32_RTC_BASE + STM32_RTC_BKP12R_OFFSET) +#define STM32_RTC_BKP13R (STM32_RTC_BASE + STM32_RTC_BKP13R_OFFSET) +#define STM32_RTC_BKP14R (STM32_RTC_BASE + STM32_RTC_BKP14R_OFFSET) +#define STM32_RTC_BKP15R (STM32_RTC_BASE + STM32_RTC_BKP15R_OFFSET) +#define STM32_RTC_BKP16R (STM32_RTC_BASE + STM32_RTC_BKP16R_OFFSET) +#define STM32_RTC_BKP17R (STM32_RTC_BASE + STM32_RTC_BKP17R_OFFSET) +#define STM32_RTC_BKP18R (STM32_RTC_BASE + STM32_RTC_BKP18R_OFFSET) +#define STM32_RTC_BKP19R (STM32_RTC_BASE + STM32_RTC_BKP19R_OFFSET) + +# define STM32_RTC_BKCOUNT 20 /* Register Bitfield Definitions ********************************************/ @@ -387,4 +387,4 @@ # define RTC_OR_OUTRMP_PC13 (0 << 1) /* 0: Alarm/calibration output on PC13 */ # define RTC_OR_OUTRMP_PB2PC13 (1 << 1) /* 1: Alarm/calibration output on PB2 or PC13 */ -#endif /* __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32WB_RTCC_H */ +#endif /* __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32_RTCC_H */ diff --git a/arch/arm/src/stm32wb/hardware/stm32wb_spi.h b/arch/arm/src/stm32wb/hardware/stm32wb_spi.h index 62851ed763479..fd433817a3d02 100644 --- a/arch/arm/src/stm32wb/hardware/stm32wb_spi.h +++ b/arch/arm/src/stm32wb/hardware/stm32wb_spi.h @@ -36,36 +36,36 @@ /* Maximum allowed speed as per specifications for all SPIs */ -#define STM32WB_SPI_CLK_MAX 32000000ul +#define STM32_SPI_CLK_MAX 32000000ul /* Register Offsets *********************************************************/ -#define STM32WB_SPI_CR1_OFFSET 0x0000 /* SPI Control Register 1 (16-bit) */ -#define STM32WB_SPI_CR2_OFFSET 0x0004 /* SPI control register 2 (16-bit) */ -#define STM32WB_SPI_SR_OFFSET 0x0008 /* SPI status register (16-bit) */ -#define STM32WB_SPI_DR_OFFSET 0x000c /* SPI data register (16-bit) */ -#define STM32WB_SPI_CRCPR_OFFSET 0x0010 /* SPI CRC polynomial register (16-bit) */ -#define STM32WB_SPI_RXCRCR_OFFSET 0x0014 /* SPI Rx CRC register (16-bit) */ -#define STM32WB_SPI_TXCRCR_OFFSET 0x0018 /* SPI Tx CRC register (16-bit) */ +#define STM32_SPI_CR1_OFFSET 0x0000 /* SPI Control Register 1 (16-bit) */ +#define STM32_SPI_CR2_OFFSET 0x0004 /* SPI control register 2 (16-bit) */ +#define STM32_SPI_SR_OFFSET 0x0008 /* SPI status register (16-bit) */ +#define STM32_SPI_DR_OFFSET 0x000c /* SPI data register (16-bit) */ +#define STM32_SPI_CRCPR_OFFSET 0x0010 /* SPI CRC polynomial register (16-bit) */ +#define STM32_SPI_RXCRCR_OFFSET 0x0014 /* SPI Rx CRC register (16-bit) */ +#define STM32_SPI_TXCRCR_OFFSET 0x0018 /* SPI Tx CRC register (16-bit) */ /* Register Addresses *******************************************************/ -#define STM32WB_SPI1_CR1 (STM32WB_SPI1_BASE + STM32WB_SPI_CR1_OFFSET) -#define STM32WB_SPI1_CR2 (STM32WB_SPI1_BASE + STM32WB_SPI_CR2_OFFSET) -#define STM32WB_SPI1_SR (STM32WB_SPI1_BASE + STM32WB_SPI_SR_OFFSET) -#define STM32WB_SPI1_DR (STM32WB_SPI1_BASE + STM32WB_SPI_DR_OFFSET) -#define STM32WB_SPI1_CRCPR (STM32WB_SPI1_BASE + STM32WB_SPI_CRCPR_OFFSET) -#define STM32WB_SPI1_RXCRCR (STM32WB_SPI1_BASE + STM32WB_SPI_RXCRCR_OFFSET) -#define STM32WB_SPI1_TXCRCR (STM32WB_SPI1_BASE + STM32WB_SPI_TXCRCR_OFFSET) - -#if CONFIG_STM32WB_HAVE_SPI2 -# define STM32WB_SPI2_CR1 (STM32WB_SPI2_BASE + STM32WB_SPI_CR1_OFFSET) -# define STM32WB_SPI2_CR2 (STM32WB_SPI2_BASE + STM32WB_SPI_CR2_OFFSET) -# define STM32WB_SPI2_SR (STM32WB_SPI2_BASE + STM32WB_SPI_SR_OFFSET) -# define STM32WB_SPI2_DR (STM32WB_SPI2_BASE + STM32WB_SPI_DR_OFFSET) -# define STM32WB_SPI2_CRCPR (STM32WB_SPI2_BASE + STM32WB_SPI_CRCPR_OFFSET) -# define STM32WB_SPI2_RXCRCR (STM32WB_SPI2_BASE + STM32WB_SPI_RXCRCR_OFFSET) -# define STM32WB_SPI2_TXCRCR (STM32WB_SPI2_BASE + STM32WB_SPI_TXCRCR_OFFSET) +#define STM32_SPI1_CR1 (STM32_SPI1_BASE + STM32_SPI_CR1_OFFSET) +#define STM32_SPI1_CR2 (STM32_SPI1_BASE + STM32_SPI_CR2_OFFSET) +#define STM32_SPI1_SR (STM32_SPI1_BASE + STM32_SPI_SR_OFFSET) +#define STM32_SPI1_DR (STM32_SPI1_BASE + STM32_SPI_DR_OFFSET) +#define STM32_SPI1_CRCPR (STM32_SPI1_BASE + STM32_SPI_CRCPR_OFFSET) +#define STM32_SPI1_RXCRCR (STM32_SPI1_BASE + STM32_SPI_RXCRCR_OFFSET) +#define STM32_SPI1_TXCRCR (STM32_SPI1_BASE + STM32_SPI_TXCRCR_OFFSET) + +#if CONFIG_STM32_HAVE_SPI2 +# define STM32_SPI2_CR1 (STM32_SPI2_BASE + STM32_SPI_CR1_OFFSET) +# define STM32_SPI2_CR2 (STM32_SPI2_BASE + STM32_SPI_CR2_OFFSET) +# define STM32_SPI2_SR (STM32_SPI2_BASE + STM32_SPI_SR_OFFSET) +# define STM32_SPI2_DR (STM32_SPI2_BASE + STM32_SPI_DR_OFFSET) +# define STM32_SPI2_CRCPR (STM32_SPI2_BASE + STM32_SPI_CRCPR_OFFSET) +# define STM32_SPI2_RXCRCR (STM32_SPI2_BASE + STM32_SPI_RXCRCR_OFFSET) +# define STM32_SPI2_TXCRCR (STM32_SPI2_BASE + STM32_SPI_TXCRCR_OFFSET) #endif /* Register Bitfield Definitions ********************************************/ diff --git a/arch/arm/src/stm32wb/hardware/stm32wb_syscfg.h b/arch/arm/src/stm32wb/hardware/stm32wb_syscfg.h index a4cfa546324b4..59ffc5b527b78 100644 --- a/arch/arm/src/stm32wb/hardware/stm32wb_syscfg.h +++ b/arch/arm/src/stm32wb/hardware/stm32wb_syscfg.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32WB_SYSCFG_H -#define __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32WB_SYSCFG_H +#ifndef __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32_SYSCFG_H +#define __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32_SYSCFG_H /**************************************************************************** * Included Files @@ -35,42 +35,42 @@ /* Register Offsets *********************************************************/ -#define STM32WB_SYSCFG_MEMRMP_OFFSET 0x0000 /* SYSCFG memory remap register */ -#define STM32WB_SYSCFG_CFGR1_OFFSET 0x0004 /* SYSCFG configuration register 1 */ +#define STM32_SYSCFG_MEMRMP_OFFSET 0x0000 /* SYSCFG memory remap register */ +#define STM32_SYSCFG_CFGR1_OFFSET 0x0004 /* SYSCFG configuration register 1 */ -#define STM32WB_SYSCFG_EXTICR_OFFSET(p) (0x0008 + ((p) & 0x0c)) /* Pin p = 0..15 */ +#define STM32_SYSCFG_EXTICR_OFFSET(p) (0x0008 + ((p) & 0x0c)) /* Pin p = 0..15 */ -#define STM32WB_SYSCFG_EXTICR1_OFFSET 0x0008 /* SYSCFG external interrupt configuration register 1 */ -#define STM32WB_SYSCFG_EXTICR2_OFFSET 0x000c /* SYSCFG external interrupt configuration register 2 */ -#define STM32WB_SYSCFG_EXTICR3_OFFSET 0x0010 /* SYSCFG external interrupt configuration register 3 */ -#define STM32WB_SYSCFG_EXTICR4_OFFSET 0x0014 /* SYSCFG external interrupt configuration register 4 */ +#define STM32_SYSCFG_EXTICR1_OFFSET 0x0008 /* SYSCFG external interrupt configuration register 1 */ +#define STM32_SYSCFG_EXTICR2_OFFSET 0x000c /* SYSCFG external interrupt configuration register 2 */ +#define STM32_SYSCFG_EXTICR3_OFFSET 0x0010 /* SYSCFG external interrupt configuration register 3 */ +#define STM32_SYSCFG_EXTICR4_OFFSET 0x0014 /* SYSCFG external interrupt configuration register 4 */ -#define STM32WB_SYSCFG_SCSR_OFFSET 0x0018 /* SYSCFG SRAM2 control and status register */ -#define STM32WB_SYSCFG_CFGR2_OFFSET 0x001c /* SYSCFG configuration register 2 */ -#define STM32WB_SYSCFG_SWPR1_OFFSET 0x0020 /* SYSCFG SRAM2 write protection register 1 */ -#define STM32WB_SYSCFG_SKR_OFFSET 0x0024 /* SYSCFG SRAM2 key register */ -#define STM32WB_SYSCFG_SWPR2_OFFSET 0x0028 /* SYSCFG SRAM2 write protection register 2 */ +#define STM32_SYSCFG_SCSR_OFFSET 0x0018 /* SYSCFG SRAM2 control and status register */ +#define STM32_SYSCFG_CFGR2_OFFSET 0x001c /* SYSCFG configuration register 2 */ +#define STM32_SYSCFG_SWPR1_OFFSET 0x0020 /* SYSCFG SRAM2 write protection register 1 */ +#define STM32_SYSCFG_SKR_OFFSET 0x0024 /* SYSCFG SRAM2 key register */ +#define STM32_SYSCFG_SWPR2_OFFSET 0x0028 /* SYSCFG SRAM2 write protection register 2 */ -#define STM32WB_SYSCFG_IMR1_OFFSET 0x0100 /* SYSCFG Interrupt mask register 1 */ -#define STM32WB_SYSCFG_IMR2_OFFSET 0x0104 /* SYSCFG Interrupt mask register 2 */ -#define STM32WB_SYSCFG_C2IMR1_OFFSET 0x0108 /* SYSCFG CPU2 Interrupt mask register 1 */ -#define STM32WB_SYSCFG_C2IMR2_OFFSET 0x010c /* SYSCFG CPU2 Interrupt mask register 2 */ -#define STM32WB_SYSCFG_SIPCR_OFFSET 0x0110 /* SYSCFG Secure IP control register */ +#define STM32_SYSCFG_IMR1_OFFSET 0x0100 /* SYSCFG Interrupt mask register 1 */ +#define STM32_SYSCFG_IMR2_OFFSET 0x0104 /* SYSCFG Interrupt mask register 2 */ +#define STM32_SYSCFG_C2IMR1_OFFSET 0x0108 /* SYSCFG CPU2 Interrupt mask register 1 */ +#define STM32_SYSCFG_C2IMR2_OFFSET 0x010c /* SYSCFG CPU2 Interrupt mask register 2 */ +#define STM32_SYSCFG_SIPCR_OFFSET 0x0110 /* SYSCFG Secure IP control register */ /* Register Addresses *******************************************************/ -#define STM32WB_SYSCFG_MEMRMP (STM32WB_SYSCFG_BASE + STM32WB_SYSCFG_MEMRMP_OFFSET) -#define STM32WB_SYSCFG_CFGR1 (STM32WB_SYSCFG_BASE + STM32WB_SYSCFG_CFGR1_OFFSET) -#define STM32WB_SYSCFG_EXTICR(p) (STM32WB_SYSCFG_BASE + STM32WB_SYSCFG_EXTICR_OFFSET(p)) -#define STM32WB_SYSCFG_EXTICR1 (STM32WB_SYSCFG_BASE + STM32WB_SYSCFG_EXTICR1_OFFSET) -#define STM32WB_SYSCFG_EXTICR2 (STM32WB_SYSCFG_BASE + STM32WB_SYSCFG_EXTICR2_OFFSET) -#define STM32WB_SYSCFG_EXTICR3 (STM32WB_SYSCFG_BASE + STM32WB_SYSCFG_EXTICR3_OFFSET) -#define STM32WB_SYSCFG_EXTICR4 (STM32WB_SYSCFG_BASE + STM32WB_SYSCFG_EXTICR4_OFFSET) -#define STM32WB_SYSCFG_SCSR (STM32WB_SYSCFG_BASE + STM32WB_SYSCFG_SCSR_OFFSET) -#define STM32WB_SYSCFG_CFGR2 (STM32WB_SYSCFG_BASE + STM32WB_SYSCFG_CFGR2_OFFSET) -#define STM32WB_SYSCFG_SWPR1 (STM32WB_SYSCFG_BASE + STM32WB_SYSCFG_SWPR1_OFFSET) -#define STM32WB_SYSCFG_SKR (STM32WB_SYSCFG_BASE + STM32WB_SYSCFG_SKR_OFFSET) -#define STM32WB_SYSCFG_SWPR2 (STM32WB_SYSCFG_BASE + STM32WB_SYSCFG_SWPR2_OFFSET) +#define STM32_SYSCFG_MEMRMP (STM32_SYSCFG_BASE + STM32_SYSCFG_MEMRMP_OFFSET) +#define STM32_SYSCFG_CFGR1 (STM32_SYSCFG_BASE + STM32_SYSCFG_CFGR1_OFFSET) +#define STM32_SYSCFG_EXTICR(p) (STM32_SYSCFG_BASE + STM32_SYSCFG_EXTICR_OFFSET(p)) +#define STM32_SYSCFG_EXTICR1 (STM32_SYSCFG_BASE + STM32_SYSCFG_EXTICR1_OFFSET) +#define STM32_SYSCFG_EXTICR2 (STM32_SYSCFG_BASE + STM32_SYSCFG_EXTICR2_OFFSET) +#define STM32_SYSCFG_EXTICR3 (STM32_SYSCFG_BASE + STM32_SYSCFG_EXTICR3_OFFSET) +#define STM32_SYSCFG_EXTICR4 (STM32_SYSCFG_BASE + STM32_SYSCFG_EXTICR4_OFFSET) +#define STM32_SYSCFG_SCSR (STM32_SYSCFG_BASE + STM32_SYSCFG_SCSR_OFFSET) +#define STM32_SYSCFG_CFGR2 (STM32_SYSCFG_BASE + STM32_SYSCFG_CFGR2_OFFSET) +#define STM32_SYSCFG_SWPR1 (STM32_SYSCFG_BASE + STM32_SYSCFG_SWPR1_OFFSET) +#define STM32_SYSCFG_SKR (STM32_SYSCFG_BASE + STM32_SYSCFG_SKR_OFFSET) +#define STM32_SYSCFG_SWPR2 (STM32_SYSCFG_BASE + STM32_SYSCFG_SWPR2_OFFSET) /* Register Bitfield Definitions ********************************************/ @@ -226,4 +226,4 @@ #define SYSCFG_SIPCR_SPKA (1 << 2) /* Bit 2: PKA Security enable */ #define SYSCFG_SIPCR_SRNG (1 << 3) /* Bit 3: RNG Security enable */ -#endif /* __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32WB_SYSCFG_H */ +#endif /* __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32_SYSCFG_H */ diff --git a/arch/arm/src/stm32wb/hardware/stm32wb_tim.h b/arch/arm/src/stm32wb/hardware/stm32wb_tim.h index 6e646a6dc2f75..e4936d2ac8bc0 100644 --- a/arch/arm/src/stm32wb/hardware/stm32wb_tim.h +++ b/arch/arm/src/stm32wb/hardware/stm32wb_tim.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32WB_TIM_H -#define __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32WB_TIM_H +#ifndef __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32_TIM_H +#define __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32_TIM_H /**************************************************************************** * Pre-processor Definitions @@ -29,150 +29,150 @@ /* Register Offsets *********************************************************/ -#define STM32WB_TIM_CR1_OFFSET 0x0000 /* Control register 1 */ -#define STM32WB_TIM_CR2_OFFSET 0x0004 /* Control register 2 */ -#define STM32WB_TIM_SMCR_OFFSET 0x0008 /* Slave mode control register (TIM1, TIM2) */ -#define STM32WB_TIM_DIER_OFFSET 0x000c /* DMA / Interrupt enable register */ -#define STM32WB_TIM_SR_OFFSET 0x0010 /* Status register */ -#define STM32WB_TIM_EGR_OFFSET 0x0014 /* Event generation register */ -#define STM32WB_TIM_CCMR1_OFFSET 0x0018 /* Capture/compare mode register 1 */ -#define STM32WB_TIM_CCMR2_OFFSET 0x001c /* Capture/compare mode register 2 (TIM1, TIM2) */ -#define STM32WB_TIM_CCER_OFFSET 0x0020 /* Capture/compare enable register */ -#define STM32WB_TIM_CNT_OFFSET 0x0024 /* Counter */ -#define STM32WB_TIM_PSC_OFFSET 0x0028 /* Prescaler */ -#define STM32WB_TIM_ARR_OFFSET 0x002c /* Auto-reload register */ -#define STM32WB_TIM_RCR_OFFSET 0x0030 /* Repetition counter register (TIM1, TIM16/TIM17) */ -#define STM32WB_TIM_CCR1_OFFSET 0x0034 /* Capture/compare register 1 */ -#define STM32WB_TIM_CCR2_OFFSET 0x0038 /* Capture/compare register 2 (TIM1, TIM2) */ -#define STM32WB_TIM_CCR3_OFFSET 0x003c /* Capture/compare register 3 (TIM1, TIM2) */ -#define STM32WB_TIM_CCR4_OFFSET 0x0040 /* Capture/compare register 4 (TIM1, TIM2) */ -#define STM32WB_TIM_BDTR_OFFSET 0x0044 /* Break and dead-time register (TIM1, TIM16/17) */ -#define STM32WB_TIM_DCR_OFFSET 0x0048 /* DMA control register */ -#define STM32WB_TIM_DMAR_OFFSET 0x004c /* DMA address for burst mode */ -#define STM32WB_TIM_OR1_OFFSET 0x0050 /* Option register 1 */ -#define STM32WB_TIM_CCMR3_OFFSET 0x0054 /* Capture/compare mode register 3 (TIM1) */ -#define STM32WB_TIM_CCR5_OFFSET 0x0058 /* Capture/compare register 5 (TIM1) */ -#define STM32WB_TIM_CCR6_OFFSET 0x005C /* Capture/compare register 6 (TIM1) */ -#define STM32WB_TIM_AF1_OFFSET 0x0060 /* Alternate function register 1 */ -#define STM32WB_TIM_AF2_OFFSET 0x0064 /* Alternate function register 2 (TIM1) */ -#define STM32WB_TIM_TISEL_OFFSET 0x0068 /* Input selector register */ +#define STM32_TIM_CR1_OFFSET 0x0000 /* Control register 1 */ +#define STM32_TIM_CR2_OFFSET 0x0004 /* Control register 2 */ +#define STM32_TIM_SMCR_OFFSET 0x0008 /* Slave mode control register (TIM1, TIM2) */ +#define STM32_TIM_DIER_OFFSET 0x000c /* DMA / Interrupt enable register */ +#define STM32_TIM_SR_OFFSET 0x0010 /* Status register */ +#define STM32_TIM_EGR_OFFSET 0x0014 /* Event generation register */ +#define STM32_TIM_CCMR1_OFFSET 0x0018 /* Capture/compare mode register 1 */ +#define STM32_TIM_CCMR2_OFFSET 0x001c /* Capture/compare mode register 2 (TIM1, TIM2) */ +#define STM32_TIM_CCER_OFFSET 0x0020 /* Capture/compare enable register */ +#define STM32_TIM_CNT_OFFSET 0x0024 /* Counter */ +#define STM32_TIM_PSC_OFFSET 0x0028 /* Prescaler */ +#define STM32_TIM_ARR_OFFSET 0x002c /* Auto-reload register */ +#define STM32_TIM_RCR_OFFSET 0x0030 /* Repetition counter register (TIM1, TIM16/TIM17) */ +#define STM32_TIM_CCR1_OFFSET 0x0034 /* Capture/compare register 1 */ +#define STM32_TIM_CCR2_OFFSET 0x0038 /* Capture/compare register 2 (TIM1, TIM2) */ +#define STM32_TIM_CCR3_OFFSET 0x003c /* Capture/compare register 3 (TIM1, TIM2) */ +#define STM32_TIM_CCR4_OFFSET 0x0040 /* Capture/compare register 4 (TIM1, TIM2) */ +#define STM32_TIM_BDTR_OFFSET 0x0044 /* Break and dead-time register (TIM1, TIM16/17) */ +#define STM32_TIM_DCR_OFFSET 0x0048 /* DMA control register */ +#define STM32_TIM_DMAR_OFFSET 0x004c /* DMA address for burst mode */ +#define STM32_TIM_OR1_OFFSET 0x0050 /* Option register 1 */ +#define STM32_TIM_CCMR3_OFFSET 0x0054 /* Capture/compare mode register 3 (TIM1) */ +#define STM32_TIM_CCR5_OFFSET 0x0058 /* Capture/compare register 5 (TIM1) */ +#define STM32_TIM_CCR6_OFFSET 0x005C /* Capture/compare register 6 (TIM1) */ +#define STM32_TIM_AF1_OFFSET 0x0060 /* Alternate function register 1 */ +#define STM32_TIM_AF2_OFFSET 0x0064 /* Alternate function register 2 (TIM1) */ +#define STM32_TIM_TISEL_OFFSET 0x0068 /* Input selector register */ /* Register Addresses *******************************************************/ /* Advanced Timer TIM1 */ -#define STM32WB_TIM1_CR1 (STM32WB_TIM1_BASE + STM32WB_TIM_CR1_OFFSET) -#define STM32WB_TIM1_CR2 (STM32WB_TIM1_BASE + STM32WB_TIM_CR2_OFFSET) -#define STM32WB_TIM1_SMCR (STM32WB_TIM1_BASE + STM32WB_TIM_SMCR_OFFSET) -#define STM32WB_TIM1_DIER (STM32WB_TIM1_BASE + STM32WB_TIM_DIER_OFFSET) -#define STM32WB_TIM1_SR (STM32WB_TIM1_BASE + STM32WB_TIM_SR_OFFSET) -#define STM32WB_TIM1_EGR (STM32WB_TIM1_BASE + STM32WB_TIM_EGR_OFFSET) -#define STM32WB_TIM1_CCMR1 (STM32WB_TIM1_BASE + STM32WB_TIM_CCMR1_OFFSET) -#define STM32WB_TIM1_CCMR2 (STM32WB_TIM1_BASE + STM32WB_TIM_CCMR2_OFFSET) -#define STM32WB_TIM1_CCER (STM32WB_TIM1_BASE + STM32WB_TIM_CCER_OFFSET) -#define STM32WB_TIM1_CNT (STM32WB_TIM1_BASE + STM32WB_TIM_CNT_OFFSET) -#define STM32WB_TIM1_PSC (STM32WB_TIM1_BASE + STM32WB_TIM_PSC_OFFSET) -#define STM32WB_TIM1_ARR (STM32WB_TIM1_BASE + STM32WB_TIM_ARR_OFFSET) -#define STM32WB_TIM1_RCR (STM32WB_TIM1_BASE + STM32WB_TIM_RCR_OFFSET) -#define STM32WB_TIM1_CCR1 (STM32WB_TIM1_BASE + STM32WB_TIM_CCR1_OFFSET) -#define STM32WB_TIM1_CCR2 (STM32WB_TIM1_BASE + STM32WB_TIM_CCR2_OFFSET) -#define STM32WB_TIM1_CCR3 (STM32WB_TIM1_BASE + STM32WB_TIM_CCR3_OFFSET) -#define STM32WB_TIM1_CCR4 (STM32WB_TIM1_BASE + STM32WB_TIM_CCR4_OFFSET) -#define STM32WB_TIM1_BDTR (STM32WB_TIM1_BASE + STM32WB_TIM_BDTR_OFFSET) -#define STM32WB_TIM1_DCR (STM32WB_TIM1_BASE + STM32WB_TIM_DCR_OFFSET) -#define STM32WB_TIM1_DMAR (STM32WB_TIM1_BASE + STM32WB_TIM_DMAR_OFFSET) -#define STM32WB_TIM1_OR1 (STM32WB_TIM1_BASE + STM32WB_TIM_OR1_OFFSET) -#define STM32WB_TIM1_CCMR3 (STM32WB_TIM1_BASE + STM32WB_TIM_CCMR3_OFFSET) -#define STM32WB_TIM1_CCR5 (STM32WB_TIM1_BASE + STM32WB_TIM_CCR5_OFFSET) -#define STM32WB_TIM1_CCR6 (STM32WB_TIM1_BASE + STM32WB_TIM_CCR6_OFFSET) -#define STM32WB_TIM1_AF1 (STM32WB_TIM1_BASE + STM32WB_TIM_AF1_OFFSET) -#define STM32WB_TIM1_AF2 (STM32WB_TIM1_BASE + STM32WB_TIM_AF2_OFFSET) -#define STM32WB_TIM1_TISEL (STM32WB_TIM1_BASE + STM32WB_TIM_TISEL_OFFSET) +#define STM32_TIM1_CR1 (STM32_TIM1_BASE + STM32_TIM_CR1_OFFSET) +#define STM32_TIM1_CR2 (STM32_TIM1_BASE + STM32_TIM_CR2_OFFSET) +#define STM32_TIM1_SMCR (STM32_TIM1_BASE + STM32_TIM_SMCR_OFFSET) +#define STM32_TIM1_DIER (STM32_TIM1_BASE + STM32_TIM_DIER_OFFSET) +#define STM32_TIM1_SR (STM32_TIM1_BASE + STM32_TIM_SR_OFFSET) +#define STM32_TIM1_EGR (STM32_TIM1_BASE + STM32_TIM_EGR_OFFSET) +#define STM32_TIM1_CCMR1 (STM32_TIM1_BASE + STM32_TIM_CCMR1_OFFSET) +#define STM32_TIM1_CCMR2 (STM32_TIM1_BASE + STM32_TIM_CCMR2_OFFSET) +#define STM32_TIM1_CCER (STM32_TIM1_BASE + STM32_TIM_CCER_OFFSET) +#define STM32_TIM1_CNT (STM32_TIM1_BASE + STM32_TIM_CNT_OFFSET) +#define STM32_TIM1_PSC (STM32_TIM1_BASE + STM32_TIM_PSC_OFFSET) +#define STM32_TIM1_ARR (STM32_TIM1_BASE + STM32_TIM_ARR_OFFSET) +#define STM32_TIM1_RCR (STM32_TIM1_BASE + STM32_TIM_RCR_OFFSET) +#define STM32_TIM1_CCR1 (STM32_TIM1_BASE + STM32_TIM_CCR1_OFFSET) +#define STM32_TIM1_CCR2 (STM32_TIM1_BASE + STM32_TIM_CCR2_OFFSET) +#define STM32_TIM1_CCR3 (STM32_TIM1_BASE + STM32_TIM_CCR3_OFFSET) +#define STM32_TIM1_CCR4 (STM32_TIM1_BASE + STM32_TIM_CCR4_OFFSET) +#define STM32_TIM1_BDTR (STM32_TIM1_BASE + STM32_TIM_BDTR_OFFSET) +#define STM32_TIM1_DCR (STM32_TIM1_BASE + STM32_TIM_DCR_OFFSET) +#define STM32_TIM1_DMAR (STM32_TIM1_BASE + STM32_TIM_DMAR_OFFSET) +#define STM32_TIM1_OR1 (STM32_TIM1_BASE + STM32_TIM_OR1_OFFSET) +#define STM32_TIM1_CCMR3 (STM32_TIM1_BASE + STM32_TIM_CCMR3_OFFSET) +#define STM32_TIM1_CCR5 (STM32_TIM1_BASE + STM32_TIM_CCR5_OFFSET) +#define STM32_TIM1_CCR6 (STM32_TIM1_BASE + STM32_TIM_CCR6_OFFSET) +#define STM32_TIM1_AF1 (STM32_TIM1_BASE + STM32_TIM_AF1_OFFSET) +#define STM32_TIM1_AF2 (STM32_TIM1_BASE + STM32_TIM_AF2_OFFSET) +#define STM32_TIM1_TISEL (STM32_TIM1_BASE + STM32_TIM_TISEL_OFFSET) /* General 32-bit Timer TIM2 */ -#define STM32WB_TIM2_CR1 (STM32WB_TIM2_BASE + STM32WB_TIM_CR1_OFFSET) -#define STM32WB_TIM2_CR2 (STM32WB_TIM2_BASE + STM32WB_TIM_CR2_OFFSET) -#define STM32WB_TIM2_SMCR (STM32WB_TIM2_BASE + STM32WB_TIM_SMCR_OFFSET) -#define STM32WB_TIM2_DIER (STM32WB_TIM2_BASE + STM32WB_TIM_DIER_OFFSET) -#define STM32WB_TIM2_SR (STM32WB_TIM2_BASE + STM32WB_TIM_SR_OFFSET) -#define STM32WB_TIM2_EGR (STM32WB_TIM2_BASE + STM32WB_TIM_EGR_OFFSET) -#define STM32WB_TIM2_CCMR1 (STM32WB_TIM2_BASE + STM32WB_TIM_CCMR1_OFFSET) -#define STM32WB_TIM2_CCMR2 (STM32WB_TIM2_BASE + STM32WB_TIM_CCMR2_OFFSET) -#define STM32WB_TIM2_CCER (STM32WB_TIM2_BASE + STM32WB_TIM_CCER_OFFSET) -#define STM32WB_TIM2_CNT (STM32WB_TIM2_BASE + STM32WB_TIM_CNT_OFFSET) -#define STM32WB_TIM2_PSC (STM32WB_TIM2_BASE + STM32WB_TIM_PSC_OFFSET) -#define STM32WB_TIM2_ARR (STM32WB_TIM2_BASE + STM32WB_TIM_ARR_OFFSET) -#define STM32WB_TIM2_CCR1 (STM32WB_TIM2_BASE + STM32WB_TIM_CCR1_OFFSET) -#define STM32WB_TIM2_CCR2 (STM32WB_TIM2_BASE + STM32WB_TIM_CCR2_OFFSET) -#define STM32WB_TIM2_CCR3 (STM32WB_TIM2_BASE + STM32WB_TIM_CCR3_OFFSET) -#define STM32WB_TIM2_CCR4 (STM32WB_TIM2_BASE + STM32WB_TIM_CCR4_OFFSET) -#define STM32WB_TIM2_DCR (STM32WB_TIM2_BASE + STM32WB_TIM_DCR_OFFSET) -#define STM32WB_TIM2_DMAR (STM32WB_TIM2_BASE + STM32WB_TIM_DMAR_OFFSET) -#define STM32WB_TIM2_OR1 (STM32WB_TIM2_BASE + STM32WB_TIM_OR1_OFFSET) -#define STM32WB_TIM2_AF1 (STM32WB_TIM2_BASE + STM32WB_TIM_AF1_OFFSET) -#define STM32WB_TIM2_TISEL (STM32WB_TIM2_BASE + STM32WB_TIM_TISEL_OFFSET) +#define STM32_TIM2_CR1 (STM32_TIM2_BASE + STM32_TIM_CR1_OFFSET) +#define STM32_TIM2_CR2 (STM32_TIM2_BASE + STM32_TIM_CR2_OFFSET) +#define STM32_TIM2_SMCR (STM32_TIM2_BASE + STM32_TIM_SMCR_OFFSET) +#define STM32_TIM2_DIER (STM32_TIM2_BASE + STM32_TIM_DIER_OFFSET) +#define STM32_TIM2_SR (STM32_TIM2_BASE + STM32_TIM_SR_OFFSET) +#define STM32_TIM2_EGR (STM32_TIM2_BASE + STM32_TIM_EGR_OFFSET) +#define STM32_TIM2_CCMR1 (STM32_TIM2_BASE + STM32_TIM_CCMR1_OFFSET) +#define STM32_TIM2_CCMR2 (STM32_TIM2_BASE + STM32_TIM_CCMR2_OFFSET) +#define STM32_TIM2_CCER (STM32_TIM2_BASE + STM32_TIM_CCER_OFFSET) +#define STM32_TIM2_CNT (STM32_TIM2_BASE + STM32_TIM_CNT_OFFSET) +#define STM32_TIM2_PSC (STM32_TIM2_BASE + STM32_TIM_PSC_OFFSET) +#define STM32_TIM2_ARR (STM32_TIM2_BASE + STM32_TIM_ARR_OFFSET) +#define STM32_TIM2_CCR1 (STM32_TIM2_BASE + STM32_TIM_CCR1_OFFSET) +#define STM32_TIM2_CCR2 (STM32_TIM2_BASE + STM32_TIM_CCR2_OFFSET) +#define STM32_TIM2_CCR3 (STM32_TIM2_BASE + STM32_TIM_CCR3_OFFSET) +#define STM32_TIM2_CCR4 (STM32_TIM2_BASE + STM32_TIM_CCR4_OFFSET) +#define STM32_TIM2_DCR (STM32_TIM2_BASE + STM32_TIM_DCR_OFFSET) +#define STM32_TIM2_DMAR (STM32_TIM2_BASE + STM32_TIM_DMAR_OFFSET) +#define STM32_TIM2_OR1 (STM32_TIM2_BASE + STM32_TIM_OR1_OFFSET) +#define STM32_TIM2_AF1 (STM32_TIM2_BASE + STM32_TIM_AF1_OFFSET) +#define STM32_TIM2_TISEL (STM32_TIM2_BASE + STM32_TIM_TISEL_OFFSET) /* General Timers TIM16/TIM17 */ -#define STM32WB_TIM16_CR1 (STM32WB_TIM16_BASE + STM32WB_TIM_CR1_OFFSET) -#define STM32WB_TIM16_CR2 (STM32WB_TIM16_BASE + STM32WB_TIM_CR2_OFFSET) -#define STM32WB_TIM16_DIER (STM32WB_TIM16_BASE + STM32WB_TIM_DIER_OFFSET) -#define STM32WB_TIM16_SR (STM32WB_TIM16_BASE + STM32WB_TIM_SR_OFFSET) -#define STM32WB_TIM16_EGR (STM32WB_TIM16_BASE + STM32WB_TIM_EGR_OFFSET) -#define STM32WB_TIM16_CCMR1 (STM32WB_TIM16_BASE + STM32WB_TIM_CCMR1_OFFSET) -#define STM32WB_TIM16_CCER (STM32WB_TIM16_BASE + STM32WB_TIM_CCER_OFFSET) -#define STM32WB_TIM16_CNT (STM32WB_TIM16_BASE + STM32WB_TIM_CNT_OFFSET) -#define STM32WB_TIM16_PSC (STM32WB_TIM16_BASE + STM32WB_TIM_PSC_OFFSET) -#define STM32WB_TIM16_ARR (STM32WB_TIM16_BASE + STM32WB_TIM_ARR_OFFSET) -#define STM32WB_TIM16_RCR (STM32WB_TIM16_BASE + STM32WB_TIM_RCR_OFFSET) -#define STM32WB_TIM16_CCR1 (STM32WB_TIM16_BASE + STM32WB_TIM_CCR1_OFFSET) -#define STM32WB_TIM16_BDTR (STM32WB_TIM16_BASE + STM32WB_TIM_BDTR_OFFSET) -#define STM32WB_TIM16_DCR (STM32WB_TIM16_BASE + STM32WB_TIM_DCR_OFFSET) -#define STM32WB_TIM16_DMAR (STM32WB_TIM16_BASE + STM32WB_TIM_DMAR_OFFSET) -#define STM32WB_TIM16_OR1 (STM32WB_TIM16_BASE + STM32WB_TIM_OR1_OFFSET) -#define STM32WB_TIM16_AF1 (STM32WB_TIM16_BASE + STM32WB_TIM_AF1_OFFSET) -#define STM32WB_TIM16_TISEL (STM32WB_TIM16_BASE + STM32WB_TIM_TISEL_OFFSET) - -#define STM32WB_TIM17_CR1 (STM32WB_TIM17_BASE + STM32WB_TIM_CR1_OFFSET) -#define STM32WB_TIM17_CR2 (STM32WB_TIM17_BASE + STM32WB_TIM_CR2_OFFSET) -#define STM32WB_TIM17_DIER (STM32WB_TIM17_BASE + STM32WB_TIM_DIER_OFFSET) -#define STM32WB_TIM17_SR (STM32WB_TIM17_BASE + STM32WB_TIM_SR_OFFSET) -#define STM32WB_TIM17_EGR (STM32WB_TIM17_BASE + STM32WB_TIM_EGR_OFFSET) -#define STM32WB_TIM17_CCMR1 (STM32WB_TIM17_BASE + STM32WB_TIM_CCMR1_OFFSET) -#define STM32WB_TIM17_CCER (STM32WB_TIM17_BASE + STM32WB_TIM_CCER_OFFSET) -#define STM32WB_TIM17_CNT (STM32WB_TIM17_BASE + STM32WB_TIM_CNT_OFFSET) -#define STM32WB_TIM17_PSC (STM32WB_TIM17_BASE + STM32WB_TIM_PSC_OFFSET) -#define STM32WB_TIM17_ARR (STM32WB_TIM17_BASE + STM32WB_TIM_ARR_OFFSET) -#define STM32WB_TIM17_RCR (STM32WB_TIM17_BASE + STM32WB_TIM_RCR_OFFSET) -#define STM32WB_TIM17_CCR1 (STM32WB_TIM17_BASE + STM32WB_TIM_CCR1_OFFSET) -#define STM32WB_TIM17_BDTR (STM32WB_TIM17_BASE + STM32WB_TIM_BDTR_OFFSET) -#define STM32WB_TIM17_DCR (STM32WB_TIM17_BASE + STM32WB_TIM_DCR_OFFSET) -#define STM32WB_TIM17_DMAR (STM32WB_TIM17_BASE + STM32WB_TIM_DMAR_OFFSET) -#define STM32WB_TIM17_OR1 (STM32WB_TIM17_BASE + STM32WB_TIM_OR1_OFFSET) -#define STM32WB_TIM17_AF1 (STM32WB_TIM17_BASE + STM32WB_TIM_AF1_OFFSET) -#define STM32WB_TIM17_TISEL (STM32WB_TIM17_BASE + STM32WB_TIM_TISEL_OFFSET) +#define STM32_TIM16_CR1 (STM32_TIM16_BASE + STM32_TIM_CR1_OFFSET) +#define STM32_TIM16_CR2 (STM32_TIM16_BASE + STM32_TIM_CR2_OFFSET) +#define STM32_TIM16_DIER (STM32_TIM16_BASE + STM32_TIM_DIER_OFFSET) +#define STM32_TIM16_SR (STM32_TIM16_BASE + STM32_TIM_SR_OFFSET) +#define STM32_TIM16_EGR (STM32_TIM16_BASE + STM32_TIM_EGR_OFFSET) +#define STM32_TIM16_CCMR1 (STM32_TIM16_BASE + STM32_TIM_CCMR1_OFFSET) +#define STM32_TIM16_CCER (STM32_TIM16_BASE + STM32_TIM_CCER_OFFSET) +#define STM32_TIM16_CNT (STM32_TIM16_BASE + STM32_TIM_CNT_OFFSET) +#define STM32_TIM16_PSC (STM32_TIM16_BASE + STM32_TIM_PSC_OFFSET) +#define STM32_TIM16_ARR (STM32_TIM16_BASE + STM32_TIM_ARR_OFFSET) +#define STM32_TIM16_RCR (STM32_TIM16_BASE + STM32_TIM_RCR_OFFSET) +#define STM32_TIM16_CCR1 (STM32_TIM16_BASE + STM32_TIM_CCR1_OFFSET) +#define STM32_TIM16_BDTR (STM32_TIM16_BASE + STM32_TIM_BDTR_OFFSET) +#define STM32_TIM16_DCR (STM32_TIM16_BASE + STM32_TIM_DCR_OFFSET) +#define STM32_TIM16_DMAR (STM32_TIM16_BASE + STM32_TIM_DMAR_OFFSET) +#define STM32_TIM16_OR1 (STM32_TIM16_BASE + STM32_TIM_OR1_OFFSET) +#define STM32_TIM16_AF1 (STM32_TIM16_BASE + STM32_TIM_AF1_OFFSET) +#define STM32_TIM16_TISEL (STM32_TIM16_BASE + STM32_TIM_TISEL_OFFSET) + +#define STM32_TIM17_CR1 (STM32_TIM17_BASE + STM32_TIM_CR1_OFFSET) +#define STM32_TIM17_CR2 (STM32_TIM17_BASE + STM32_TIM_CR2_OFFSET) +#define STM32_TIM17_DIER (STM32_TIM17_BASE + STM32_TIM_DIER_OFFSET) +#define STM32_TIM17_SR (STM32_TIM17_BASE + STM32_TIM_SR_OFFSET) +#define STM32_TIM17_EGR (STM32_TIM17_BASE + STM32_TIM_EGR_OFFSET) +#define STM32_TIM17_CCMR1 (STM32_TIM17_BASE + STM32_TIM_CCMR1_OFFSET) +#define STM32_TIM17_CCER (STM32_TIM17_BASE + STM32_TIM_CCER_OFFSET) +#define STM32_TIM17_CNT (STM32_TIM17_BASE + STM32_TIM_CNT_OFFSET) +#define STM32_TIM17_PSC (STM32_TIM17_BASE + STM32_TIM_PSC_OFFSET) +#define STM32_TIM17_ARR (STM32_TIM17_BASE + STM32_TIM_ARR_OFFSET) +#define STM32_TIM17_RCR (STM32_TIM17_BASE + STM32_TIM_RCR_OFFSET) +#define STM32_TIM17_CCR1 (STM32_TIM17_BASE + STM32_TIM_CCR1_OFFSET) +#define STM32_TIM17_BDTR (STM32_TIM17_BASE + STM32_TIM_BDTR_OFFSET) +#define STM32_TIM17_DCR (STM32_TIM17_BASE + STM32_TIM_DCR_OFFSET) +#define STM32_TIM17_DMAR (STM32_TIM17_BASE + STM32_TIM_DMAR_OFFSET) +#define STM32_TIM17_OR1 (STM32_TIM17_BASE + STM32_TIM_OR1_OFFSET) +#define STM32_TIM17_AF1 (STM32_TIM17_BASE + STM32_TIM_AF1_OFFSET) +#define STM32_TIM17_TISEL (STM32_TIM17_BASE + STM32_TIM_TISEL_OFFSET) /* Register Value Constants *************************************************/ /* Digital Filter options */ -#define STM32WB_DF_NOFILT (0x0) /* 0000: No filter */ -#define STM32WB_DF_FCKINTn2 (0x1) /* 0001: fSAMPLING = fCK_INT, N=2 */ -#define STM32WB_DF_FCKINTn4 (0x2) /* 0010: fSAMPLING = fCK_INT, N=4 */ -#define STM32WB_DF_FCKINTn8 (0x3) /* 0011: fSAMPLING = fCK_INT, N=8 */ -#define STM32WB_DF_FDTSd2n6 (0x4) /* 0100: fSAMPLING = fDTS/2, N=6 */ -#define STM32WB_DF_FDTSd2n8 (0x5) /* 0101: fSAMPLING = fDTS/2, N=8 */ -#define STM32WB_DF_FDTSd4n6 (0x6) /* 0110: fSAMPLING = fDTS/4, N=6 */ -#define STM32WB_DF_FDTSd4n8 (0x7) /* 0111: fSAMPLING = fDTS/4, N=8 */ -#define STM32WB_DF_FDTSd8n6 (0x8) /* 1000: fSAMPLING = fDTS/8, N=6 */ -#define STM32WB_DF_FDTSd8n8 (0x9) /* 1001: fSAMPLING = fDTS/8, N=8 */ -#define STM32WB_DF_FDTSd16n5 (0xa) /* 1010: fSAMPLING = fDTS/16, N=5 */ -#define STM32WB_DF_FDTSd16n6 (0xb) /* 1011: fSAMPLING = fDTS/16, N=6 */ -#define STM32WB_DF_FDTSd16n8 (0xc) /* 1100: fSAMPLING = fDTS/16, N=8 */ -#define STM32WB_DF_FDTSd32n5 (0xd) /* 1101: fSAMPLING = fDTS/32, N=5 */ -#define STM32WB_DF_FDTSd32n6 (0xe) /* 1110: fSAMPLING = fDTS/32, N=6 */ -#define STM32WB_DF_FDTSd32n8 (0xf) /* 1111: fSAMPLING = fDTS/32, N=8 */ +#define STM32_DF_NOFILT (0x0) /* 0000: No filter */ +#define STM32_DF_FCKINTn2 (0x1) /* 0001: fSAMPLING = fCK_INT, N=2 */ +#define STM32_DF_FCKINTn4 (0x2) /* 0010: fSAMPLING = fCK_INT, N=4 */ +#define STM32_DF_FCKINTn8 (0x3) /* 0011: fSAMPLING = fCK_INT, N=8 */ +#define STM32_DF_FDTSd2n6 (0x4) /* 0100: fSAMPLING = fDTS/2, N=6 */ +#define STM32_DF_FDTSd2n8 (0x5) /* 0101: fSAMPLING = fDTS/2, N=8 */ +#define STM32_DF_FDTSd4n6 (0x6) /* 0110: fSAMPLING = fDTS/4, N=6 */ +#define STM32_DF_FDTSd4n8 (0x7) /* 0111: fSAMPLING = fDTS/4, N=8 */ +#define STM32_DF_FDTSd8n6 (0x8) /* 1000: fSAMPLING = fDTS/8, N=6 */ +#define STM32_DF_FDTSd8n8 (0x9) /* 1001: fSAMPLING = fDTS/8, N=8 */ +#define STM32_DF_FDTSd16n5 (0xa) /* 1010: fSAMPLING = fDTS/16, N=5 */ +#define STM32_DF_FDTSd16n6 (0xb) /* 1011: fSAMPLING = fDTS/16, N=6 */ +#define STM32_DF_FDTSd16n8 (0xc) /* 1100: fSAMPLING = fDTS/16, N=8 */ +#define STM32_DF_FDTSd32n5 (0xd) /* 1101: fSAMPLING = fDTS/32, N=5 */ +#define STM32_DF_FDTSd32n6 (0xe) /* 1110: fSAMPLING = fDTS/32, N=6 */ +#define STM32_DF_FDTSd32n8 (0xf) /* 1111: fSAMPLING = fDTS/32, N=8 */ /* Register Bitfield Definitions ********************************************/ @@ -397,7 +397,7 @@ #define TIM1_SMCR_MSM (1 << 7) /* Bit 7: Master/slave mode */ #define TIM1_SMCR_ETF_SHIFT (8) /* Bits 8-11: External trigger filter */ #define TIM1_SMCR_ETF_MASK (0xf << TIM1_SMCR_ETF_SHIFT) -# define TIM1_SMCR_ETF(f) ((f) << TIM1_SMCR_ETF_SHIFT) /* f = STM32WB_DF_[digital filter option] */ +# define TIM1_SMCR_ETF(f) ((f) << TIM1_SMCR_ETF_SHIFT) /* f = STM32_DF_[digital filter option] */ #define TIM1_SMCR_ETPS_SHIFT (12) /* Bits 12-13: External trigger prescaler */ #define TIM1_SMCR_ETPS_MASK (0x3 << TIM1_SMCR_ETPS_SHIFT) @@ -450,7 +450,7 @@ #define TIM2_SMCR_MSM (1 << 7) /* Bit 7: Master/slave mode */ #define TIM2_SMCR_ETF_SHIFT (8) /* Bits 8-11: External trigger filter */ #define TIM2_SMCR_ETF_MASK (0xf << TIM2_SMCR_ETF_SHIFT) -# define TIM2_SMCR_ETF(f) ((f) << TIM2_SMCR_ETF_SHIFT) /* f = STM32WB_DF_[digital filter option] */ +# define TIM2_SMCR_ETF(f) ((f) << TIM2_SMCR_ETF_SHIFT) /* f = STM32_DF_[digital filter option] */ #define TIM2_SMCR_ETPS_SHIFT (12) /* Bits 12-13: External trigger prescaler */ #define TIM2_SMCR_ETPS_MASK (0x3 << TIM2_SMCR_ETPS_SHIFT) @@ -920,7 +920,7 @@ #define TIM1_CCMR1_IC1F_SHIFT (4) /* Bits 4-7: Input Capture 1 Filter */ #define TIM1_CCMR1_IC1F_MASK (0xf << TIM1_CCMR1_IC1F_SHIFT) -# define TIM1_CCMR1_IC1F(f) ((f) << TIM1_CCMR1_IC1F_SHIFT) /* f = STM32WB_DF_[digital filter option] */ +# define TIM1_CCMR1_IC1F(f) ((f) << TIM1_CCMR1_IC1F_SHIFT) /* f = STM32_DF_[digital filter option] */ #define TIM1_CCMR1_IC2PSC_SHIFT (10) /* Bits 10-11: Input Capture 2 Prescaler */ #define TIM1_CCMR1_IC2PSC_MASK (0x3 << TIM1_CCMR1_IC2PSC_SHIFT) @@ -931,7 +931,7 @@ #define TIM1_CCMR1_IC2F_SHIFT (12) /* Bits 12-15: Input Capture 2 Filter */ #define TIM1_CCMR1_IC2F_MASK (0xf << TIM1_CCMR1_IC2F_SHIFT) -# define TIM1_CCMR1_IC2F(f) ((f) << TIM1_CCMR1_IC2F_SHIFT) /* f = STM32WB_DF_[digital filter option] */ +# define TIM1_CCMR1_IC2F(f) ((f) << TIM1_CCMR1_IC2F_SHIFT) /* f = STM32_DF_[digital filter option] */ #define TIM1_CCMR2_IC3PSC_SHIFT (2) /* Bits 2-3: Input Capture 3 Prescaler */ #define TIM1_CCMR2_IC3PSC_MASK (0x3 << TIM1_CCMR2_IC3PSC_SHIFT) @@ -942,7 +942,7 @@ #define TIM1_CCMR2_IC3F_SHIFT (4) /* Bits 4-7: Input Capture 3 Filter */ #define TIM1_CCMR2_IC3F_MASK (0xf << TIM1_CCMR2_IC3F_SHIFT) -# define TIM1_CCMR2_IC3F(f) ((f) << TIM1_CCMR2_IC3F_SHIFT) /* f = STM32WB_DF_[digital filter option] */ +# define TIM1_CCMR2_IC3F(f) ((f) << TIM1_CCMR2_IC3F_SHIFT) /* f = STM32_DF_[digital filter option] */ #define TIM1_CCMR2_IC4PSC_SHIFT (10) /* Bits 10-11: Input Capture 4 Prescaler */ #define TIM1_CCMR2_IC4PSC_MASK (0x3 << TIM1_CCMR2_IC4PSC_SHIFT) @@ -953,7 +953,7 @@ #define TIM1_CCMR2_IC4F_SHIFT (12) /* Bits 12-15: Input Capture 4 Filter */ #define TIM1_CCMR2_IC4F_MASK (0xf << TIM1_CCMR2_IC4F_SHIFT) -# define TIM1_CCMR2_IC4F(f) ((f) << TIM1_CCMR2_IC4F_SHIFT) /* f = STM32WB_DF_[digital filter option] */ +# define TIM1_CCMR2_IC4F(f) ((f) << TIM1_CCMR2_IC4F_SHIFT) /* f = STM32_DF_[digital filter option] */ #define TIM2_CCMR1_IC1PSC_SHIFT (2) /* Bits 2-3: Input Capture 1 Prescaler */ #define TIM2_CCMR1_IC1PSC_MASK (0x3 << TIM2_CCMR1_IC1PSC_SHIFT) @@ -964,7 +964,7 @@ #define TIM2_CCMR1_IC1F_SHIFT (4) /* Bits 4-7: Input Capture 1 Filter */ #define TIM2_CCMR1_IC1F_MASK (0xf << TIM2_CCMR1_IC1F_SHIFT) -# define TIM2_CCMR1_IC1F(f) ((f) << TIM2_CCMR1_IC1F_SHIFT) /* f = STM32WB_DF_[digital filter option] */ +# define TIM2_CCMR1_IC1F(f) ((f) << TIM2_CCMR1_IC1F_SHIFT) /* f = STM32_DF_[digital filter option] */ #define TIM2_CCMR1_IC2PSC_SHIFT (10) /* Bits 10-11: Input Capture 2 Prescaler */ #define TIM2_CCMR1_IC2PSC_MASK (0x3 << TIM2_CCMR1_IC2PSC_SHIFT) @@ -975,7 +975,7 @@ #define TIM2_CCMR1_IC2F_SHIFT (12) /* Bits 12-15: Input Capture 2 Filter */ #define TIM2_CCMR1_IC2F_MASK (0xf << TIM2_CCMR1_IC2F_SHIFT) -# define TIM2_CCMR1_IC2F(f) ((f) << TIM2_CCMR1_IC2F_SHIFT) /* f = STM32WB_DF_[digital filter option] */ +# define TIM2_CCMR1_IC2F(f) ((f) << TIM2_CCMR1_IC2F_SHIFT) /* f = STM32_DF_[digital filter option] */ #define TIM2_CCMR2_IC3PSC_SHIFT (2) /* Bits 2-3: Input Capture 3 Prescaler */ #define TIM2_CCMR2_IC3PSC_MASK (0x3 << TIM2_CCMR2_IC3PSC_SHIFT) @@ -986,7 +986,7 @@ #define TIM2_CCMR2_IC3F_SHIFT (4) /* Bits 4-7: Input Capture 3 Filter */ #define TIM2_CCMR2_IC3F_MASK (0xf << TIM2_CCMR2_IC3F_SHIFT) -# define TIM2_CCMR2_IC3F(f) ((f) << TIM2_CCMR2_IC3F_SHIFT) /* f = STM32WB_DF_[digital filter option] */ +# define TIM2_CCMR2_IC3F(f) ((f) << TIM2_CCMR2_IC3F_SHIFT) /* f = STM32_DF_[digital filter option] */ #define TIM2_CCMR2_IC4PSC_SHIFT (10) /* Bits 10-11: Input Capture 4 Prescaler */ #define TIM2_CCMR2_IC4PSC_MASK (0x3 << TIM2_CCMR2_IC4PSC_SHIFT) @@ -997,7 +997,7 @@ #define TIM2_CCMR2_IC4F_SHIFT (12) /* Bits 12-15: Input Capture 4 Filter */ #define TIM2_CCMR2_IC4F_MASK (0xf << TIM2_CCMR2_IC4F_SHIFT) -# define TIM2_CCMR2_IC4F(f) ((f) << TIM2_CCMR2_IC4F_SHIFT) /* f = STM32WB_DF_[digital filter option] */ +# define TIM2_CCMR2_IC4F(f) ((f) << TIM2_CCMR2_IC4F_SHIFT) /* f = STM32_DF_[digital filter option] */ #define TIM16_CCMR1_IC1PSC_SHIFT (2) /* Bits 2-3: Input Capture 1 Prescaler */ #define TIM16_CCMR1_IC1PSC_MASK (0x3 << TIM16_CCMR1_IC1PSC_SHIFT) @@ -1008,7 +1008,7 @@ #define TIM16_CCMR1_IC1F_SHIFT (4) /* Bits 4-7: Input Capture 1 Filter */ #define TIM16_CCMR1_IC1F_MASK (0xf << TIM16_CCMR1_IC1F_SHIFT) -# define TIM16_CCMR1_IC1F(f) ((f) << TIM16_CCMR1_IC1F_SHIFT) /* f = STM32WB_DF_[digital filter option] */ +# define TIM16_CCMR1_IC1F(f) ((f) << TIM16_CCMR1_IC1F_SHIFT) /* f = STM32_DF_[digital filter option] */ #define TIM17_CCMR1_IC1PSC_SHIFT (2) /* Bits 2-3: Input Capture 1 Prescaler */ #define TIM17_CCMR1_IC1PSC_MASK (0x3 << TIM17_CCMR1_IC1PSC_SHIFT) @@ -1019,7 +1019,7 @@ #define TIM17_CCMR1_IC1F_SHIFT (4) /* Bits 4-7: Input Capture 1 Filter */ #define TIM17_CCMR1_IC1F_MASK (0xf << TIM17_CCMR1_IC1F_SHIFT) -# define TIM17_CCMR1_IC1F(f) ((f) << TIM17_CCMR1_IC1F_SHIFT) /* f = STM32WB_DF_[digital filter option] */ +# define TIM17_CCMR1_IC1F(f) ((f) << TIM17_CCMR1_IC1F_SHIFT) /* f = STM32_DF_[digital filter option] */ /* Capture/compare enable register */ @@ -1178,11 +1178,11 @@ #define TIM1_BDTR_MOE (1 << 15) /* Bit 15: Main Output enable */ #define TIM1_BDTR_BKF_SHIFT (16) /* Bits 16-19: Break filter */ #define TIM1_BDTR_BKF_MASK (0xf << TIM1_BDTR_BKF_SHIFT) -# define TIM1_BDTR_BKF(f) ((f) << TIM1_BDTR_BKF_SHIFT) /* f = STM32WB_DF_[digital filter option] */ +# define TIM1_BDTR_BKF(f) ((f) << TIM1_BDTR_BKF_SHIFT) /* f = STM32_DF_[digital filter option] */ #define TIM1_BDTR_BK2F_SHIFT (20) /* Bits 20-23: Break 2 filter */ #define TIM1_BDTR_BK2F_MASK (0xf << TIM1_BDTR_BK2F_SHIFT) -# define TIM1_BDTR_BK2F(f) ((f) << TIM1_BDTR_BK2F_SHIFT) /* f = STM32WB_DF_[digital filter option] */ +# define TIM1_BDTR_BK2F(f) ((f) << TIM1_BDTR_BK2F_SHIFT) /* f = STM32_DF_[digital filter option] */ #define TIM1_BDTR_BK2E (1 << 24) /* Bit 24: Break 2 enable */ #define TIM1_BDTR_BK2P (1 << 25) /* Bit 25: Break 2 polarity */ @@ -1384,4 +1384,4 @@ #define TIM17_TISEL_TI1SEL_MASK (0xf << TIM17_TISEL_TI1SEL_SHIFT) # define TIM17_TISEL_TI1SEL_CH1 (0x0 << TIM17_TISEL_TI1SEL_SHIFT) /* 0000: CH1 input */ -#endif /* __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32WB_TIM_H */ +#endif /* __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32_TIM_H */ diff --git a/arch/arm/src/stm32wb/hardware/stm32wb_uart.h b/arch/arm/src/stm32wb/hardware/stm32wb_uart.h index 2ce1c1b6268bf..4cc8184015d2b 100644 --- a/arch/arm/src/stm32wb/hardware/stm32wb_uart.h +++ b/arch/arm/src/stm32wb/hardware/stm32wb_uart.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32WB_UART_H -#define __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32WB_UART_H +#ifndef __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32_UART_H +#define __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32_UART_H /**************************************************************************** * Included Files @@ -37,34 +37,34 @@ /* Register Offsets *********************************************************/ -#define STM32WB_USART_CR1_OFFSET 0x0000 /* Control Register 1 */ -#define STM32WB_USART_CR2_OFFSET 0x0004 /* Control Register 2 */ -#define STM32WB_USART_CR3_OFFSET 0x0008 /* Control Register 3 */ -#define STM32WB_USART_BRR_OFFSET 0x000c /* Baud Rate Register */ -#define STM32WB_USART_GTPR_OFFSET 0x0010 /* Guard Time and Prescaler Register */ -#define STM32WB_USART_RTOR_OFFSET 0x0014 /* Receiver Timeout Register */ -#define STM32WB_USART_RQR_OFFSET 0x0018 /* Request Register */ -#define STM32WB_USART_ISR_OFFSET 0x001c /* Interrupt and Status Register */ -#define STM32WB_USART_ICR_OFFSET 0x0020 /* Interrupt flag Clear Register */ -#define STM32WB_USART_RDR_OFFSET 0x0024 /* Receive Data Register */ -#define STM32WB_USART_TDR_OFFSET 0x0028 /* Transmit Data Register */ -#define STM32WB_USART_PRESC_OFFSET 0x002c /* Prescaler Register */ +#define STM32_USART_CR1_OFFSET 0x0000 /* Control Register 1 */ +#define STM32_USART_CR2_OFFSET 0x0004 /* Control Register 2 */ +#define STM32_USART_CR3_OFFSET 0x0008 /* Control Register 3 */ +#define STM32_USART_BRR_OFFSET 0x000c /* Baud Rate Register */ +#define STM32_USART_GTPR_OFFSET 0x0010 /* Guard Time and Prescaler Register */ +#define STM32_USART_RTOR_OFFSET 0x0014 /* Receiver Timeout Register */ +#define STM32_USART_RQR_OFFSET 0x0018 /* Request Register */ +#define STM32_USART_ISR_OFFSET 0x001c /* Interrupt and Status Register */ +#define STM32_USART_ICR_OFFSET 0x0020 /* Interrupt flag Clear Register */ +#define STM32_USART_RDR_OFFSET 0x0024 /* Receive Data Register */ +#define STM32_USART_TDR_OFFSET 0x0028 /* Transmit Data Register */ +#define STM32_USART_PRESC_OFFSET 0x002c /* Prescaler Register */ /* Register Addresses *******************************************************/ -#if STM32WB_NUSART > 0 -# define STM32WB_USART1_CR1 (STM32WB_USART1_BASE + STM32WB_USART_CR1_OFFSET) -# define STM32WB_USART1_CR2 (STM32WB_USART1_BASE + STM32WB_USART_CR2_OFFSET) -# define STM32WB_USART1_CR3 (STM32WB_USART1_BASE + STM32WB_USART_CR3_OFFSET) -# define STM32WB_USART1_BRR (STM32WB_USART1_BASE + STM32WB_USART_BRR_OFFSET) -# define STM32WB_USART1_GTPR (STM32WB_USART1_BASE + STM32WB_USART_GTPR_OFFSET) -# define STM32WB_USART1_RTOR (STM32WB_USART1_BASE + STM32WB_USART_RTOR_OFFSET) -# define STM32WB_USART1_RQR (STM32WB_USART1_BASE + STM32WB_USART_RQR_OFFSET) -# define STM32WB_USART1_ISR (STM32WB_USART1_BASE + STM32WB_USART_ISR_OFFSET) -# define STM32WB_USART1_ICR (STM32WB_USART1_BASE + STM32WB_USART_ICR_OFFSET) -# define STM32WB_USART1_RDR (STM32WB_USART1_BASE + STM32WB_USART_RDR_OFFSET) -# define STM32WB_USART1_TDR (STM32WB_USART1_BASE + STM32WB_USART_TDR_OFFSET) -# define STM32WB_USART1_PRESC (STM32WB_USART1_BASE + STM32WB_USART_PRESC_OFFSET) +#if STM32_NUSART > 0 +# define STM32_USART1_CR1 (STM32_USART1_BASE + STM32_USART_CR1_OFFSET) +# define STM32_USART1_CR2 (STM32_USART1_BASE + STM32_USART_CR2_OFFSET) +# define STM32_USART1_CR3 (STM32_USART1_BASE + STM32_USART_CR3_OFFSET) +# define STM32_USART1_BRR (STM32_USART1_BASE + STM32_USART_BRR_OFFSET) +# define STM32_USART1_GTPR (STM32_USART1_BASE + STM32_USART_GTPR_OFFSET) +# define STM32_USART1_RTOR (STM32_USART1_BASE + STM32_USART_RTOR_OFFSET) +# define STM32_USART1_RQR (STM32_USART1_BASE + STM32_USART_RQR_OFFSET) +# define STM32_USART1_ISR (STM32_USART1_BASE + STM32_USART_ISR_OFFSET) +# define STM32_USART1_ICR (STM32_USART1_BASE + STM32_USART_ICR_OFFSET) +# define STM32_USART1_RDR (STM32_USART1_BASE + STM32_USART_RDR_OFFSET) +# define STM32_USART1_TDR (STM32_USART1_BASE + STM32_USART_TDR_OFFSET) +# define STM32_USART1_PRESC (STM32_USART1_BASE + STM32_USART_PRESC_OFFSET) #endif /* Register Bitfield Definitions ********************************************/ @@ -338,4 +338,4 @@ * Public Function Prototypes ****************************************************************************/ -#endif /* __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32WB_UART_H */ +#endif /* __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32_UART_H */ diff --git a/arch/arm/src/stm32wb/hardware/stm32wbxx_pinmap.h b/arch/arm/src/stm32wb/hardware/stm32wbxx_pinmap.h index ab8255bba6bb9..7c9a15dd0451f 100644 --- a/arch/arm/src/stm32wb/hardware/stm32wbxx_pinmap.h +++ b/arch/arm/src/stm32wb/hardware/stm32wbxx_pinmap.h @@ -58,7 +58,7 @@ /* ADC */ -#if defined(CONFIG_STM32WB_STM32WB10) || defined(CONFIG_STM32WB_STM32WB15) +#if defined(CONFIG_STM32_STM32WB10) || defined(CONFIG_STM32_STM32WB15) # define GPIO_ADC1_IN2_0 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN7) # define GPIO_ADC1_IN3_0 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN8) # define GPIO_ADC1_IN4_0 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN9) @@ -77,8 +77,8 @@ #define GPIO_ADC1_IN10_0 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN5) #define GPIO_ADC1_IN11_0 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN6) -#if defined(CONFIG_STM32WB_STM32WB30) || defined(CONFIG_STM32WB_STM32WB50) \ - || defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55) +#if defined(CONFIG_STM32_STM32WB30) || defined(CONFIG_STM32_STM32WB50) \ + || defined(CONFIG_STM32_STM32WB35) || defined(CONFIG_STM32_STM32WB55) # define GPIO_ADC1_IN12_0 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN7) # define GPIO_ADC1_IN15_0 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN8) # define GPIO_ADC1_IN16_0 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN9) @@ -95,7 +95,7 @@ /* Comparators */ -#if defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55) +#if defined(CONFIG_STM32_STM32WB35) || defined(CONFIG_STM32_STM32WB55) #define GPIO_COMP1_INP_1 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN1) #define GPIO_COMP1_INP_2 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN2) @@ -128,7 +128,7 @@ # define GPIO_COMP2_OUT_4 (GPIO_ALT | GPIO_AF12 | GPIO_PORTB | GPIO_PIN11) #endif -#endif /* defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55) */ +#endif /* defined(CONFIG_STM32_STM32WB35) || defined(CONFIG_STM32_STM32WB55) */ /* I2C */ @@ -145,7 +145,7 @@ # define GPIO_I2C1_SDA_2 (GPIO_ALT | GPIO_AF4 | GPIO_OPENDRAIN | GPIO_PORTB | GPIO_PIN9) #endif -#if defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55) +#if defined(CONFIG_STM32_STM32WB35) || defined(CONFIG_STM32_STM32WB55) #define GPIO_I2C3_SDA_1 (GPIO_ALT | GPIO_AF4 | GPIO_OPENDRAIN | GPIO_PORTB | GPIO_PIN4) #define GPIO_I2C3_SCL_1 (GPIO_ALT | GPIO_AF4 | GPIO_OPENDRAIN | GPIO_PORTA | GPIO_PIN7) @@ -161,7 +161,7 @@ # define GPIO_I2C3_SDA_4 (GPIO_ALT | GPIO_AF4 | GPIO_OPENDRAIN | GPIO_PORTC | GPIO_PIN1) #endif -#endif /* defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55) */ +#endif /* defined(CONFIG_STM32_STM32WB35) || defined(CONFIG_STM32_STM32WB55) */ /* JTAG/SWD */ @@ -176,7 +176,7 @@ /* QUADSPI */ -#if defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55) +#if defined(CONFIG_STM32_STM32WB35) || defined(CONFIG_STM32_STM32WB55) #define GPIO_QSPI_NCS_1 (GPIO_ALT | GPIO_AF10 | GPIO_PORTA | GPIO_PIN2) #define GPIO_QSPI_CLK_1 (GPIO_ALT | GPIO_AF10 | GPIO_PORTA | GPIO_PIN3) @@ -198,7 +198,7 @@ # define GPIO_QSPI_BK1_IO3_2 (GPIO_ALT | GPIO_AF10 | GPIO_PORTD | GPIO_PIN7) #endif -#endif /* defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55) */ +#endif /* defined(CONFIG_STM32_STM32WB35) || defined(CONFIG_STM32_STM32WB55) */ /* RTC */ @@ -215,7 +215,7 @@ /* SAI */ -#if defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55) +#if defined(CONFIG_STM32_STM32WB35) || defined(CONFIG_STM32_STM32WB55) #define GPIO_SAI1_EXTCLK_1 (GPIO_ALT | GPIO_AF13 | GPIO_PORTA | GPIO_PIN0) #define GPIO_SAI1_EXTCLK_2 (GPIO_ALT | GPIO_AF13 | GPIO_PORTB | GPIO_PIN2) @@ -257,7 +257,7 @@ # define GPIO_SAI1_PDMDI1_3 (GPIO_ALT | GPIO_AF3 | GPIO_PORTD | GPIO_PIN6) #endif -#endif /* defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55) */ +#endif /* defined(CONFIG_STM32_STM32WB35) || defined(CONFIG_STM32_STM32WB55) */ /* SPI */ @@ -277,14 +277,14 @@ # define GPIO_SPI1_SCK_3 (GPIO_ALT | GPIO_AF5 | GPIO_PORTB | GPIO_PIN3) #endif -#if defined(CONFIG_STM32WB_STM32WB10) || defined(CONFIG_STM32WB_STM32WB15) +#if defined(CONFIG_STM32_STM32WB10) || defined(CONFIG_STM32_STM32WB15) # define GPIO_SPI1_MOSI_4 (GPIO_ALT | GPIO_AF4 | GPIO_PORTA | GPIO_PIN5) # define GPIO_SPI1_MOSI_5 (GPIO_ALT | GPIO_AF5 | GPIO_PORTA | GPIO_PIN13) # define GPIO_SPI1_NSS_4 (GPIO_ALT | GPIO_AF5 | GPIO_PORTA | GPIO_PIN14) # define GPIO_SPI1_NSS_5 (GPIO_ALT | GPIO_AF5 | GPIO_PORTB | GPIO_PIN6) #endif -#if defined(CONFIG_STM32WB_STM32WB55) +#if defined(CONFIG_STM32_STM32WB55) #define GPIO_SPI2_NSS_1 (GPIO_ALT | GPIO_AF5 | GPIO_PORTB | GPIO_PIN9) #define GPIO_SPI2_NSS_2 (GPIO_ALT | GPIO_AF5 | GPIO_PORTB | GPIO_PIN12) @@ -305,7 +305,7 @@ # define GPIO_SPI2_MISO_3 (GPIO_ALT | GPIO_AF5 | GPIO_PORTD | GPIO_PIN3) #endif -#endif /* defined(CONFIG_STM32WB_STM32WB55) */ +#endif /* defined(CONFIG_STM32_STM32WB55) */ /* Timers */ @@ -346,7 +346,7 @@ # define GPIO_TIM1_CH2OUT_2 (GPIO_ALT | GPIO_AF1 | GPIO_PUSHPULL | GPIO_PORTD | GPIO_PIN15) #endif -#if defined(CONFIG_STM32WB_STM32WB10) || defined(CONFIG_STM32WB_STM32WB15) +#if defined(CONFIG_STM32_STM32WB10) || defined(CONFIG_STM32_STM32WB15) # define GPIO_TIM1_CH3IN_2 (GPIO_ALT | GPIO_AF12 | GPIO_FLOAT | GPIO_PORTB | GPIO_PIN7) # define GPIO_TIM1_CH3OUT_2 (GPIO_ALT | GPIO_AF12 | GPIO_PUSHPULL | GPIO_PORTB | GPIO_PIN7) #endif @@ -393,8 +393,8 @@ # define GPIO_TIM2_CH3OUT_3 (GPIO_ALT | GPIO_AF1 | GPIO_PUSHPULL | GPIO_PORTB | GPIO_PIN13) #endif -#if defined(CONFIG_STM32WB_STM32WB30) || defined(CONFIG_STM32WB_STM32WB50) \ - || defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55) +#if defined(CONFIG_STM32_STM32WB30) || defined(CONFIG_STM32_STM32WB50) \ + || defined(CONFIG_STM32_STM32WB35) || defined(CONFIG_STM32_STM32WB55) #define GPIO_TIM16_BKIN_0 (GPIO_ALT | GPIO_AF14 | GPIO_PORTB | GPIO_PIN5) #define GPIO_TIM16_CH1IN_1 (GPIO_ALT | GPIO_AF14 | GPIO_FLOAT | GPIO_PORTB | GPIO_PIN8) @@ -420,7 +420,7 @@ # define GPIO_TIM17_CH1OUT_3 (GPIO_ALT | GPIO_AF14 | GPIO_PUSHPULL | GPIO_PORTE | GPIO_PIN1) #endif -#endif /* defined(CONFIG_STM32WB_STM32WB30) || defined(CONFIG_STM32WB_STM32WB50) || defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55) */ +#endif /* defined(CONFIG_STM32_STM32WB30) || defined(CONFIG_STM32_STM32WB50) || defined(CONFIG_STM32_STM32WB35) || defined(CONFIG_STM32_STM32WB55) */ #define GPIO_LPTIM1_ETR_1 (GPIO_ALT | GPIO_AF1 | GPIO_PORTB | GPIO_PIN6) #define GPIO_LPTIM1_OUT_1 (GPIO_ALT | GPIO_AF1 | GPIO_PORTA | GPIO_PIN14) @@ -453,7 +453,7 @@ /* Touch Screen Controller */ -#if defined(CONFIG_STM32WB_STM32WB10) || defined(CONFIG_STM32WB_STM32WB15) || defined(CONFIG_STM32WB_STM32WB55) +#if defined(CONFIG_STM32_STM32WB10) || defined(CONFIG_STM32_STM32WB15) || defined(CONFIG_STM32_STM32WB55) #if defined(CONFIG_STM32WB_IO_CONFIG_R) || defined(CONFIG_STM32WB_IO_CONFIG_V) # define GPIO_TSC_SYNC_1 (GPIO_ALT | GPIO_AF9 | GPIO_PORTB | GPIO_PIN10) @@ -523,7 +523,7 @@ # define GPIO_TSC_G7_IO3_0 (GPIO_ALT | GPIO_AF9 | GPIO_PORTE | GPIO_PIN2) #endif -#if defined(CONFIG_STM32WB_STM32WB15) +#if defined(CONFIG_STM32_STM32WB15) # define GPIO_TSC_G7_IO1_0 (GPIO_ALT | GPIO_AF9 | GPIO_PORTA | GPIO_PIN13) # define GPIO_TSC_G7_IO2_0 (GPIO_ALT | GPIO_AF9 | GPIO_PORTA | GPIO_PIN10) # define GPIO_TSC_G7_IO3_0 (GPIO_ALT | GPIO_AF9 | GPIO_PORTB | GPIO_PIN8) @@ -531,12 +531,12 @@ #define GPIO_TSC_G7_IO4_0 (GPIO_ALT | GPIO_AF9 | GPIO_PORTB | GPIO_PIN9) -#endif /* defined(CONFIG_STM32WB_STM32WB10) || defined(CONFIG_STM32WB_STM32WB15) || defined(CONFIG_STM32WB_STM32WB55) */ +#endif /* defined(CONFIG_STM32_STM32WB10) || defined(CONFIG_STM32_STM32WB15) || defined(CONFIG_STM32_STM32WB55) */ /* IR interface (with timers 16 and 17) */ -#if defined(CONFIG_STM32WB_STM32WB30) || defined(CONFIG_STM32WB_STM32WB50) \ - || defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55) +#if defined(CONFIG_STM32_STM32WB30) || defined(CONFIG_STM32_STM32WB50) \ + || defined(CONFIG_STM32_STM32WB35) || defined(CONFIG_STM32_STM32WB55) # define GPIO_IR_OUT_1 (GPIO_ALT | GPIO_AF8 | GPIO_PORTA | GPIO_PIN13) # define GPIO_IR_OUT_2 (GPIO_ALT | GPIO_AF8 | GPIO_PORTB | GPIO_PIN9) #endif @@ -570,7 +570,7 @@ # define GPIO_USART1_RTS_DE_2 (GPIO_ALT | GPIO_AF7 | GPIO_PORTB | GPIO_PIN3) #endif -#if defined(CONFIG_STM32WB_STM32WB15) || defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55) +#if defined(CONFIG_STM32_STM32WB15) || defined(CONFIG_STM32_STM32WB35) || defined(CONFIG_STM32_STM32WB55) #define GPIO_LPUART1_TX_1 (GPIO_ALT | GPIO_AF8 | GPIO_PORTA | GPIO_PIN2) #define GPIO_LPUART1_TX_2 (GPIO_ALT | GPIO_AF8 | GPIO_PORTB | GPIO_PIN5) @@ -588,11 +588,11 @@ # define GPIO_LPUART1_RTS_DE_2 (GPIO_ALT | GPIO_AF8 | GPIO_PORTB | GPIO_PIN12) #endif -#endif /* defined(CONFIG_STM32WB_STM32WB15) || defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55) */ +#endif /* defined(CONFIG_STM32_STM32WB15) || defined(CONFIG_STM32_STM32WB35) || defined(CONFIG_STM32_STM32WB55) */ /* USB */ -#if defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55) +#if defined(CONFIG_STM32_STM32WB35) || defined(CONFIG_STM32_STM32WB55) #define GPIO_USB_CRS_SYNC_0 (GPIO_ALT | GPIO_AF10 | GPIO_PORTA | GPIO_PIN10) #define GPIO_USB_DM_0 (GPIO_ALT | GPIO_AF10 | GPIO_PUSHPULL | GPIO_PORTA | GPIO_PIN11) @@ -603,6 +603,6 @@ # define GPIO_USB_NOE_2 (GPIO_ALT | GPIO_AF10 | GPIO_PUSHPULL | GPIO_PORTC | GPIO_PIN9) #endif -#endif /* defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55) */ +#endif /* defined(CONFIG_STM32_STM32WB35) || defined(CONFIG_STM32_STM32WB55) */ #endif /* __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32WBXX_PINMAP_H */ diff --git a/arch/arm/src/stm32wb/stm32.h b/arch/arm/src/stm32wb/stm32.h new file mode 100644 index 0000000000000..ef7f8b5db4872 --- /dev/null +++ b/arch/arm/src/stm32wb/stm32.h @@ -0,0 +1,45 @@ +/**************************************************************************** + * arch/arm/src/stm32wb/stm32.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32WB_STM32_H +#define __ARCH_ARM_SRC_STM32WB_STM32_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include +#include + +#include "arm_internal.h" + +/* Peripherals **************************************************************/ + +#include "chip.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#endif /* __ARCH_ARM_SRC_STM32WB_STM32_H */ diff --git a/arch/arm/src/stm32wb/stm32wb.h b/arch/arm/src/stm32wb/stm32wb.h deleted file mode 100644 index 25327d74d906e..0000000000000 --- a/arch/arm/src/stm32wb/stm32wb.h +++ /dev/null @@ -1,45 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32wb/stm32wb.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32WB_STM32WB_H -#define __ARCH_ARM_SRC_STM32WB_STM32WB_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include -#include -#include - -#include "arm_internal.h" - -/* Peripherals **************************************************************/ - -#include "chip.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#endif /* __ARCH_ARM_SRC_STM32WB_STM32WB_H */ diff --git a/arch/arm/src/stm32wb/stm32wb_allocateheap.c b/arch/arm/src/stm32wb/stm32wb_allocateheap.c index 1192100de8fc2..6b94fcd14020d 100644 --- a/arch/arm/src/stm32wb/stm32wb_allocateheap.c +++ b/arch/arm/src/stm32wb/stm32wb_allocateheap.c @@ -60,21 +60,21 @@ /* Set the range of system SRAM1 */ -#define SRAM1_START STM32WB_SRAM1_BASE -#define SRAM1_END (SRAM1_START + STM32WB_SRAM1_SIZE) +#define SRAM1_START STM32_SRAM1_BASE +#define SRAM1_END (SRAM1_START + STM32_SRAM1_SIZE) /* Set the range of SRAM2a as well, requires a second memory region */ -#ifdef CONFIG_STM32WB_SRAM2A_HEAP -# define SRAM2A_START (STM32WB_SRAM2A_BASE + CONFIG_STM32WB_SRAM2A_USER_BASE_OFFSET) -# define SRAM2A_END (SRAM2A_START + CONFIG_STM32WB_SRAM2A_USER_SIZE) +#ifdef CONFIG_STM32_SRAM2A_HEAP +# define SRAM2A_START (STM32_SRAM2A_BASE + CONFIG_STM32_SRAM2A_USER_BASE_OFFSET) +# define SRAM2A_END (SRAM2A_START + CONFIG_STM32_SRAM2A_USER_SIZE) #endif /* Set the range of SRAM2b as well, requires a third memory region */ -#ifdef CONFIG_STM32WB_SRAM2B_HEAP -# define SRAM2B_START STM32WB_SRAM2B_BASE -# define SRAM2B_END (SRAM2B_START + CONFIG_STM32WB_SRAM2B_USER_SIZE) +#ifdef CONFIG_STM32_SRAM2B_HEAP +# define SRAM2B_START STM32_SRAM2B_BASE +# define SRAM2B_END (SRAM2B_START + CONFIG_STM32_SRAM2B_USER_SIZE) #endif /* Some sanity checking. If multiple memory regions are defined, verify @@ -82,25 +82,25 @@ * that we have been asked to add to the heap. */ -#ifdef CONFIG_STM32WB_SRAM2A_HEAP -# if SRAM2A_END > STM32WB_SRAM2A_BASE + STM32WB_SRAM2A_SIZE +#ifdef CONFIG_STM32_SRAM2A_HEAP +# if SRAM2A_END > STM32_SRAM2A_BASE + STM32_SRAM2A_SIZE # error "SRAM2a heap memory region is out of it's physical address space" # endif #endif -#ifdef CONFIG_STM32WB_SRAM2B_HEAP -# if SRAM2B_END > STM32WB_SRAM2B_BASE + STM32WB_SRAM2B_SIZE +#ifdef CONFIG_STM32_SRAM2B_HEAP +# if SRAM2B_END > STM32_SRAM2B_BASE + STM32_SRAM2B_SIZE # error "SRAM2b heap memory region is out of it's physical address space" # endif #endif -#if CONFIG_MM_REGIONS < defined(CONFIG_STM32WB_SRAM2A_HEAP) + \ - defined(CONFIG_STM32WB_SRAM2B_HEAP) + 1 +#if CONFIG_MM_REGIONS < defined(CONFIG_STM32_SRAM2A_HEAP) + \ + defined(CONFIG_STM32_SRAM2B_HEAP) + 1 # error "You need more memory manager regions to support selected heap components" #endif -#if CONFIG_MM_REGIONS > defined(CONFIG_STM32WB_SRAM2A_HEAP) + \ - defined(CONFIG_STM32WB_SRAM2B_HEAP) + 1 +#if CONFIG_MM_REGIONS > defined(CONFIG_STM32_SRAM2A_HEAP) + \ + defined(CONFIG_STM32_SRAM2B_HEAP) + 1 # warning "CONFIG_MM_REGIONS large enough but I do not know what some of the region(s) are" #endif @@ -201,7 +201,7 @@ void up_allocate_heap(void **heap_start, size_t *heap_size) /* Allow user-mode access to the user heap memory */ - stm32wb_mpu_uheap((uintptr_t)ubase, usize); + stm32_mpu_uheap((uintptr_t)ubase, usize); #else /* Return the heap settings */ @@ -283,13 +283,13 @@ void arm_addregion(void) * from the release notes for STM32WB coprocessor wireless binaries. */ -#ifdef CONFIG_STM32WB_SRAM2A_HEAP +#ifdef CONFIG_STM32_SRAM2A_HEAP #if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP) /* Allow user-mode access to the SRAM2a heap */ - stm32wb_mpu_uheap((uintptr_t)SRAM2A_START, SRAM2A_END - SRAM2A_START); + stm32_mpu_uheap((uintptr_t)SRAM2A_START, SRAM2A_END - SRAM2A_START); #endif @@ -301,15 +301,15 @@ void arm_addregion(void) kumm_addregion((void *)SRAM2A_START, SRAM2A_END - SRAM2A_START); -#endif /* CONFIG_STM32WB_SRAM2A_HEAP */ +#endif /* CONFIG_STM32_SRAM2A_HEAP */ -#ifdef CONFIG_STM32WB_SRAM2B_HEAP +#ifdef CONFIG_STM32_SRAM2B_HEAP #if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP) /* Allow user-mode access to the SRAM2b heap */ - stm32wb_mpu_uheap((uintptr_t)SRAM2B_START, SRAM2B_END - SRAM2B_START); + stm32_mpu_uheap((uintptr_t)SRAM2B_START, SRAM2B_END - SRAM2B_START); #endif @@ -321,6 +321,6 @@ void arm_addregion(void) kumm_addregion((void *)SRAM2B_START, SRAM2B_END - SRAM2B_START); -#endif /* CONFIG_STM32WB_SRAM2B_HEAP */ +#endif /* CONFIG_STM32_SRAM2B_HEAP */ } #endif diff --git a/arch/arm/src/stm32wb/stm32wb_blehci.c b/arch/arm/src/stm32wb/stm32wb_blehci.c index 4e5de9fc88a0e..3df0927bd0e03 100644 --- a/arch/arm/src/stm32wb/stm32wb_blehci.c +++ b/arch/arm/src/stm32wb/stm32wb_blehci.c @@ -45,75 +45,75 @@ /* HCI event header fields helpers */ -#define STM32WB_BLEHCI_CCEVT_OPCODE(e) (*(uint16_t *)((uint8_t *)(e) + 3)) -#define STM32WB_BLEHCI_CCEVT_STATUS(e) (*((uint8_t *)(e) + 5)) +#define STM32_BLEHCI_CCEVT_OPCODE(e) (*(uint16_t *)((uint8_t *)(e) + 3)) +#define STM32_BLEHCI_CCEVT_STATUS(e) (*((uint8_t *)(e) + 5)) -#define STM32WB_BLEHCI_CSEVT_OPCODE(e) (*(uint16_t *)((uint8_t *)(e) + 4)) -#define STM32WB_BLEHCI_CSEVT_STATUS(e) (*((uint8_t *)(e) + 2)) +#define STM32_BLEHCI_CSEVT_OPCODE(e) (*(uint16_t *)((uint8_t *)(e) + 4)) +#define STM32_BLEHCI_CSEVT_STATUS(e) (*((uint8_t *)(e) + 2)) /* BLE init configuration params */ -#define STM32WB_BLE_PREP_WRITE_NUM \ - STM32WB_MBOX_DEFAULT_BLE_PREP_WRITE_NUM(CONFIG_STM32WB_BLE_MAX_ATT_MTU) +#define STM32_BLE_PREP_WRITE_NUM \ + STM32_MBOX_DEFAULT_BLE_PREP_WRITE_NUM(CONFIG_STM32_BLE_MAX_ATT_MTU) -#define STM32WB_C2_MEM_BLOCK_NUM \ - STM32WB_MBOX_DEFAULT_C2_MEM_BLOCK_NUM(CONFIG_STM32WB_BLE_MAX_ATT_MTU, \ - CONFIG_STM32WB_BLE_MAX_CONN, \ - STM32WB_BLE_PREP_WRITE_NUM) +#define STM32_C2_MEM_BLOCK_NUM \ + STM32_MBOX_DEFAULT_C2_MEM_BLOCK_NUM(CONFIG_STM32_BLE_MAX_ATT_MTU, \ + CONFIG_STM32_BLE_MAX_CONN, \ + STM32_BLE_PREP_WRITE_NUM) -#ifdef CONFIG_STM32WB_BLE_C2HOST -# define STM32WB_BLE_C2HOST STM32WB_SHCI_BLE_INIT_OPT_STACK_LL_HOST +#ifdef CONFIG_STM32_BLE_C2HOST +# define STM32_BLE_C2HOST STM32_SHCI_BLE_INIT_OPT_STACK_LL_HOST #else -# define STM32WB_BLE_C2HOST STM32WB_SHCI_BLE_INIT_OPT_STACK_LL +# define STM32_BLE_C2HOST STM32_SHCI_BLE_INIT_OPT_STACK_LL #endif -#ifdef CONFIG_STM32WB_BLE_SVC_CHANGED_CHAR -# define STM32WB_BLE_SVC_CHANGED_CHAR STM32WB_SHCI_BLE_INIT_OPT_SVC_CHCHAR_ENABLED +#ifdef CONFIG_STM32_BLE_SVC_CHANGED_CHAR +# define STM32_BLE_SVC_CHANGED_CHAR STM32_SHCI_BLE_INIT_OPT_SVC_CHCHAR_ENABLED #else -# define STM32WB_BLE_SVC_CHANGED_CHAR STM32WB_SHCI_BLE_INIT_OPT_SVC_CHCHAR_DISABLED +# define STM32_BLE_SVC_CHANGED_CHAR STM32_SHCI_BLE_INIT_OPT_SVC_CHCHAR_DISABLED #endif -#ifdef CONFIG_STM32WB_BLE_WRITABLE_DEVICE_NAME -# define STM32WB_BLE_DEVICE_NAME_MODE STM32WB_SHCI_BLE_INIT_OPT_DEVICE_NAME_MODE_RW +#ifdef CONFIG_STM32_BLE_WRITABLE_DEVICE_NAME +# define STM32_BLE_DEVICE_NAME_MODE STM32_SHCI_BLE_INIT_OPT_DEVICE_NAME_MODE_RW #else -# define STM32WB_BLE_DEVICE_NAME_MODE STM32WB_SHCI_BLE_INIT_OPT_DEVICE_NAME_MODE_RO +# define STM32_BLE_DEVICE_NAME_MODE STM32_SHCI_BLE_INIT_OPT_DEVICE_NAME_MODE_RO #endif -#ifdef CONFIG_STM32WB_BLE_CHAN_SEL_ALG2 -# define STM32WB_BLE_CS_ALG2 STM32WB_SHCI_BLE_INIT_OPT_CS_ALG2_ENABLED +#ifdef CONFIG_STM32_BLE_CHAN_SEL_ALG2 +# define STM32_BLE_CS_ALG2 STM32_SHCI_BLE_INIT_OPT_CS_ALG2_ENABLED #else -# define STM32WB_BLE_CS_ALG2 STM32WB_SHCI_BLE_INIT_OPT_CS_ALG2_DISABLED +# define STM32_BLE_CS_ALG2 STM32_SHCI_BLE_INIT_OPT_CS_ALG2_DISABLED #endif -#ifdef CONFIG_STM32WB_BLE_POWER_CLASS_1 -# define STM32WB_BLE_POWER_CLASS STM32WB_SHCI_BLE_INIT_OPT_POWER_CLASS_1 +#ifdef CONFIG_STM32_BLE_POWER_CLASS_1 +# define STM32_BLE_POWER_CLASS STM32_SHCI_BLE_INIT_OPT_POWER_CLASS_1 #else -# define STM32WB_BLE_POWER_CLASS STM32WB_SHCI_BLE_INIT_OPT_POWER_CLASS_2_3 +# define STM32_BLE_POWER_CLASS STM32_SHCI_BLE_INIT_OPT_POWER_CLASS_2_3 #endif -#define STM32WB_BLE_INIT_OPTIONS \ - (STM32WB_BLE_C2HOST | STM32WB_BLE_SVC_CHANGED_CHAR | \ - STM32WB_BLE_DEVICE_NAME_MODE | STM32WB_BLE_CS_ALG2 | \ - STM32WB_BLE_POWER_CLASS) +#define STM32_BLE_INIT_OPTIONS \ + (STM32_BLE_C2HOST | STM32_BLE_SVC_CHANGED_CHAR | \ + STM32_BLE_DEVICE_NAME_MODE | STM32_BLE_CS_ALG2 | \ + STM32_BLE_POWER_CLASS) -#ifdef CONFIG_STM32WB_BLE_AGC_RSSI_IMPROVED -# define STM32WB_BLE_RXMOD_AGC_RSSI STM32WB_SHCI_BLE_INIT_RXMOD_AGC_RSSI_IMPROVED +#ifdef CONFIG_STM32_BLE_AGC_RSSI_IMPROVED +# define STM32_BLE_RXMOD_AGC_RSSI STM32_SHCI_BLE_INIT_RXMOD_AGC_RSSI_IMPROVED #else -# define STM32WB_BLE_RXMOD_AGC_RSSI STM32WB_SHCI_BLE_INIT_RXMOD_AGC_RSSI_LEGACY +# define STM32_BLE_RXMOD_AGC_RSSI STM32_SHCI_BLE_INIT_RXMOD_AGC_RSSI_LEGACY #endif /**************************************************************************** * Private Function Prototypes ****************************************************************************/ -static int stm32wb_blehci_driveropen(struct bt_driver_s *btdev); -static int stm32wb_blehci_driversend(struct bt_driver_s *btdev, +static int stm32_blehci_driveropen(struct bt_driver_s *btdev); +static int stm32_blehci_driversend(struct bt_driver_s *btdev, enum bt_buf_type_e type, void *data, size_t len); -static int stm32wb_blehci_rxevt(struct stm32wb_mbox_evt_s *evt); -static void stm32wb_blehci_bleinit(void); -static int stm32wb_blehci_driverinitialize(void); -static void stm32wb_blehci_drvinitworker(void *arg); +static int stm32_blehci_rxevt(struct stm32_mbox_evt_s *evt); +static void stm32_blehci_bleinit(void); +static int stm32_blehci_driverinitialize(void); +static void stm32_blehci_drvinitworker(void *arg); /**************************************************************************** * Private Data @@ -122,8 +122,8 @@ static void stm32wb_blehci_drvinitworker(void *arg); static struct bt_driver_s g_blehci_driver = { .head_reserve = 0, - .open = stm32wb_blehci_driveropen, - .send = stm32wb_blehci_driversend + .open = stm32_blehci_driveropen, + .send = stm32_blehci_driversend }; static mutex_t g_lock = NXMUTEX_INITIALIZER; @@ -134,19 +134,19 @@ struct work_s g_drv_init_work; ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_blehci_driveropen + * Name: stm32_blehci_driveropen ****************************************************************************/ -static int stm32wb_blehci_driveropen(struct bt_driver_s *btdev) +static int stm32_blehci_driveropen(struct bt_driver_s *btdev) { return 0; } /**************************************************************************** - * Name: stm32wb_blehci_driversend + * Name: stm32_blehci_driversend ****************************************************************************/ -static int stm32wb_blehci_driversend(struct bt_driver_s *btdev, +static int stm32_blehci_driversend(struct bt_driver_s *btdev, enum bt_buf_type_e type, void *data, size_t len) { @@ -177,11 +177,11 @@ static int stm32wb_blehci_driversend(struct bt_driver_s *btdev, if (type == BT_CMD) { - ret = stm32wb_mbox_blecmd(data, len); + ret = stm32_mbox_blecmd(data, len); } else { - ret = stm32wb_mbox_bleacl(data, len); + ret = stm32_mbox_bleacl(data, len); } nxmutex_unlock(&g_lock); @@ -191,30 +191,30 @@ static int stm32wb_blehci_driversend(struct bt_driver_s *btdev, } /**************************************************************************** - * Name: stm32wb_blehci_rxevt + * Name: stm32_blehci_rxevt ****************************************************************************/ -static int stm32wb_blehci_rxevt(struct stm32wb_mbox_evt_s *evt) +static int stm32_blehci_rxevt(struct stm32_mbox_evt_s *evt) { size_t len; switch (evt->type) { - case STM32WB_MBOX_HCIEVT: + case STM32_MBOX_HCIEVT: len = sizeof(evt->evt_hdr) + evt->evt_hdr.len; if (evt->evt_hdr.evt == BT_HCI_EVT_CMD_COMPLETE) { wlinfo("received command COMPLETE event from mailbox " "(opcode: 0x%04x, status: %u)\n", - STM32WB_BLEHCI_CCEVT_OPCODE(&evt->evt_hdr), - STM32WB_BLEHCI_CCEVT_STATUS(&evt->evt_hdr)); + STM32_BLEHCI_CCEVT_OPCODE(&evt->evt_hdr), + STM32_BLEHCI_CCEVT_STATUS(&evt->evt_hdr)); } else if (evt->evt_hdr.evt == BT_HCI_EVT_CMD_STATUS) { wlinfo("received command STATUS event from mailbox " "(opcode: 0x%04x, status: %u)\n", - STM32WB_BLEHCI_CSEVT_OPCODE(&evt->evt_hdr), - STM32WB_BLEHCI_CSEVT_STATUS(&evt->evt_hdr)); + STM32_BLEHCI_CSEVT_OPCODE(&evt->evt_hdr), + STM32_BLEHCI_CSEVT_STATUS(&evt->evt_hdr)); #ifdef CONFIG_NIMBLE /* During initialisation NimBLE host stack sends unsupported @@ -223,18 +223,18 @@ static int stm32wb_blehci_rxevt(struct stm32wb_mbox_evt_s *evt) * with minimal impact we shim the response as succeeded. */ - if (STM32WB_BLEHCI_CSEVT_STATUS(&evt->evt_hdr) != 0 && - (STM32WB_BLEHCI_CSEVT_OPCODE(&evt->evt_hdr) == + if (STM32_BLEHCI_CSEVT_STATUS(&evt->evt_hdr) != 0 && + (STM32_BLEHCI_CSEVT_OPCODE(&evt->evt_hdr) == BT_OP(BT_OGF_BASEBAND, 0x0063))) { wlwarn("suppress FAILED command STATUS event from mailbox, " "(opcode: 0x%04x, status: %u) \n", - STM32WB_BLEHCI_CSEVT_OPCODE(&evt->evt_hdr), - STM32WB_BLEHCI_CSEVT_STATUS(&evt->evt_hdr)); + STM32_BLEHCI_CSEVT_OPCODE(&evt->evt_hdr), + STM32_BLEHCI_CSEVT_STATUS(&evt->evt_hdr)); /* Suppress status field error value */ - STM32WB_BLEHCI_CSEVT_STATUS(&evt->evt_hdr) = 0; + STM32_BLEHCI_CSEVT_STATUS(&evt->evt_hdr) = 0; } #endif } @@ -247,36 +247,36 @@ static int stm32wb_blehci_rxevt(struct stm32wb_mbox_evt_s *evt) bt_netdev_receive(&g_blehci_driver, BT_EVT, &evt->evt_hdr, len); break; - case STM32WB_MBOX_HCIACL: + case STM32_MBOX_HCIACL: len = sizeof(evt->acl_hdr) + evt->acl_hdr.len; wlinfo("received HCI ACL from mailbox (handle: 0x%04x, len: %u)\n", evt->acl_hdr.handle, evt->acl_hdr.len); bt_netdev_receive(&g_blehci_driver, BT_ACL_IN, &evt->acl_hdr, len); break; - case STM32WB_MBOX_SYSEVT: + case STM32_MBOX_SYSEVT: wlinfo("received SYS EVT 0x%02x from mailbox\n", evt->evt_hdr.evt); - if (evt->evt_hdr.evt == STM32WB_SHCI_ASYNC_EVT && - *(uint16_t *)(&evt->evt_hdr + 1) == STM32WB_SHCI_ASYNC_EVT_C2RDY) + if (evt->evt_hdr.evt == STM32_SHCI_ASYNC_EVT && + *(uint16_t *)(&evt->evt_hdr + 1) == STM32_SHCI_ASYNC_EVT_C2RDY) { - stm32wb_blehci_bleinit(); + stm32_blehci_bleinit(); } break; - case STM32WB_MBOX_SYSACK: + case STM32_MBOX_SYSACK: /* CPU2 Ready is the only expected response */ - DEBUGASSERT(evt->evt_hdr.evt == STM32WB_SHCI_ACK_EVT_C2RDY); + DEBUGASSERT(evt->evt_hdr.evt == STM32_SHCI_ACK_EVT_C2RDY); - if (evt->evt_hdr.evt == STM32WB_SHCI_ACK_EVT_C2RDY) + if (evt->evt_hdr.evt == STM32_SHCI_ACK_EVT_C2RDY) { wlinfo("system command ACK response"); /* Make driver initialisation in low priority work queue */ work_queue(LPWORK, &g_drv_init_work, - stm32wb_blehci_drvinitworker, NULL, 0); + stm32_blehci_drvinitworker, NULL, 0); } break; @@ -288,49 +288,49 @@ static int stm32wb_blehci_rxevt(struct stm32wb_mbox_evt_s *evt) } /**************************************************************************** - * Name: stm32wb_blehci_bleinit + * Name: stm32_blehci_bleinit ****************************************************************************/ -static void stm32wb_blehci_bleinit(void) +static void stm32_blehci_bleinit(void) { /* Prepare BLE configuration */ - struct stm32wb_shci_ble_init_cfg_s params = + struct stm32_shci_ble_init_cfg_s params = { .ble_buf = NULL, .ble_buf_size = 0, - .gatt_attr_num = CONFIG_STM32WB_BLE_GATT_MAX_ATTR_NUM, - .gatt_srv_num = CONFIG_STM32WB_BLE_GATT_MAX_SVC_NUM, - .gatt_attr_buf_size = CONFIG_STM32WB_BLE_GATT_ATTR_BUF_SIZE, - .max_conn = CONFIG_STM32WB_BLE_MAX_CONN, - .dle_enable = CONFIG_STM32WB_BLE_DLE, - .prep_write_op_num = STM32WB_BLE_PREP_WRITE_NUM, - .mem_block_num = STM32WB_C2_MEM_BLOCK_NUM, - .att_max_mtu_size = CONFIG_STM32WB_BLE_MAX_ATT_MTU, - .slave_sca = CONFIG_STM32WB_BLE_SLAVE_SCA, - .master_sca_range = CONFIG_STM32WB_BLE_MASTER_SCA, - .ls_clock_source = CONFIG_STM32WB_BLE_LS_CLK_SRC, - .conn_event_length = CONFIG_STM32WB_BLE_MAX_CONN_EVT_LENGTH, - .hse_startup = CONFIG_STM32WB_BLE_HSE_STARTUP, - .viterbi_enable = CONFIG_STM32WB_BLE_VITERBI, - .options = STM32WB_BLE_INIT_OPTIONS, + .gatt_attr_num = CONFIG_STM32_BLE_GATT_MAX_ATTR_NUM, + .gatt_srv_num = CONFIG_STM32_BLE_GATT_MAX_SVC_NUM, + .gatt_attr_buf_size = CONFIG_STM32_BLE_GATT_ATTR_BUF_SIZE, + .max_conn = CONFIG_STM32_BLE_MAX_CONN, + .dle_enable = CONFIG_STM32_BLE_DLE, + .prep_write_op_num = STM32_BLE_PREP_WRITE_NUM, + .mem_block_num = STM32_C2_MEM_BLOCK_NUM, + .att_max_mtu_size = CONFIG_STM32_BLE_MAX_ATT_MTU, + .slave_sca = CONFIG_STM32_BLE_SLAVE_SCA, + .master_sca_range = CONFIG_STM32_BLE_MASTER_SCA, + .ls_clock_source = CONFIG_STM32_BLE_LS_CLK_SRC, + .conn_event_length = CONFIG_STM32_BLE_MAX_CONN_EVT_LENGTH, + .hse_startup = CONFIG_STM32_BLE_HSE_STARTUP, + .viterbi_enable = CONFIG_STM32_BLE_VITERBI, + .options = STM32_BLE_INIT_OPTIONS, .hw_version = 0, - .max_initor_coc_num = CONFIG_STM32WB_BLE_MAX_INITOR_COC_NUM, - .tx_power_min = CONFIG_STM32WB_BLE_MIN_TX_POWER, - .tx_power_max = CONFIG_STM32WB_BLE_MAX_TX_POWER, - .rx_model_config = STM32WB_BLE_RXMOD_AGC_RSSI + .max_initor_coc_num = CONFIG_STM32_BLE_MAX_INITOR_COC_NUM, + .tx_power_min = CONFIG_STM32_BLE_MIN_TX_POWER, + .tx_power_max = CONFIG_STM32_BLE_MAX_TX_POWER, + .rx_model_config = STM32_BLE_RXMOD_AGC_RSSI }; /* Initialise BLE */ - stm32wb_mbox_bleinit(¶ms); + stm32_mbox_bleinit(¶ms); } /**************************************************************************** - * Name: stm32wb_blehci_driverinitialize + * Name: stm32_blehci_driverinitialize ****************************************************************************/ -static int stm32wb_blehci_driverinitialize(void) +static int stm32_blehci_driverinitialize(void) { int ret = 0; @@ -345,12 +345,12 @@ static int stm32wb_blehci_driverinitialize(void) } /**************************************************************************** - * Name: stm32wb_blehci_drvinitworker + * Name: stm32_blehci_drvinitworker ****************************************************************************/ -static void stm32wb_blehci_drvinitworker(void *arg) +static void stm32_blehci_drvinitworker(void *arg) { - stm32wb_blehci_driverinitialize(); + stm32_blehci_driverinitialize(); } /**************************************************************************** @@ -358,7 +358,7 @@ static void stm32wb_blehci_drvinitworker(void *arg) ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_blehci_initialize + * Name: stm32_blehci_initialize * * Description: * Initialize and register BLE HCI driver which interfaces a BLE host @@ -367,15 +367,15 @@ static void stm32wb_blehci_drvinitworker(void *arg) * ****************************************************************************/ -void stm32wb_blehci_initialize(void) +void stm32_blehci_initialize(void) { /* Initialize mbox internal data structures and set * event receive handler. */ - stm32wb_mboxinitialize(stm32wb_blehci_rxevt); + stm32_mboxinitialize(stm32_blehci_rxevt); /* Enable communication hardware and boot up CPU2 */ - stm32wb_mboxenable(); + stm32_mboxenable(); } diff --git a/arch/arm/src/stm32wb/stm32wb_blehci.h b/arch/arm/src/stm32wb/stm32wb_blehci.h index a8d5f6229d50b..eaa7fa0f2edd9 100644 --- a/arch/arm/src/stm32wb/stm32wb_blehci.h +++ b/arch/arm/src/stm32wb/stm32wb_blehci.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32WB_STM32WB_BLEHCI_H -#define __ARCH_ARM_SRC_STM32WB_STM32WB_BLEHCI_H +#ifndef __ARCH_ARM_SRC_STM32WB_STM32_BLEHCI_H +#define __ARCH_ARM_SRC_STM32WB_STM32_BLEHCI_H /**************************************************************************** * Included Files @@ -50,7 +50,7 @@ extern "C" ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_blehci_initialize + * Name: stm32_blehci_initialize * * Description: * Initialize and register BLE HCI driver which interfaces a BLE host @@ -59,7 +59,7 @@ extern "C" * ****************************************************************************/ -void stm32wb_blehci_initialize(void); +void stm32_blehci_initialize(void); #undef EXTERN #if defined(__cplusplus) @@ -67,4 +67,4 @@ void stm32wb_blehci_initialize(void); #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32WB_STM32WB_BLEHCI_H */ +#endif /* __ARCH_ARM_SRC_STM32WB_STM32_BLEHCI_H */ diff --git a/arch/arm/src/stm32wb/stm32wb_dma.c b/arch/arm/src/stm32wb/stm32wb_dma.c index ae37c4e53e096..2ba7cdd517d48 100644 --- a/arch/arm/src/stm32wb/stm32wb_dma.c +++ b/arch/arm/src/stm32wb/stm32wb_dma.c @@ -42,19 +42,19 @@ * Pre-processor Definitions ****************************************************************************/ -#ifndef CONFIG_STM32WB_DMAMUX -# error "Configuration error, CONFIG_STM32WB_DMAMUX not defined!" +#ifndef CONFIG_STM32_DMAMUX +# error "Configuration error, CONFIG_STM32_DMAMUX not defined!" #endif #define DMAMUX_NUM 1 #define DMA_CONTROLLERS 2 -#ifdef CONFIG_STM32WB_DMA1 +#ifdef CONFIG_STM32_DMA1 # define DMA1_NCHAN 7 #else # define DMA1_NCHAN 0 #endif -#ifdef CONFIG_STM32WB_DMA2 +#ifdef CONFIG_STM32_DMA2 # define DMA2_NCHAN 7 #else # define DMA2_NCHAN 0 @@ -75,20 +75,20 @@ /* This structure described one DMAMUX device */ -struct stm32wb_dmamux_s +struct stm32_dmamux_s { uint8_t id; /* DMAMUX id */ uint8_t nchan; /* DMAMUX channels */ uint32_t base; /* DMAMUX base address */ }; -typedef const struct stm32wb_dmamux_s *DMA_MUX; +typedef const struct stm32_dmamux_s *DMA_MUX; /* This structure describes one DMA controller */ -struct stm32wb_dma_s +struct stm32_dma_s { - uint8_t first; /* Offset in stm32wb_dmach_s array */ + uint8_t first; /* Offset in stm32_dmach_s array */ uint8_t nchan; /* Number of channels */ uint8_t dmamux_offset; /* DMAMUX channel offset */ uint32_t base; /* Base address */ @@ -97,7 +97,7 @@ struct stm32wb_dma_s /* This structure describes one DMA channel (DMA1, DMA2) */ -struct stm32wb_dmach_s +struct stm32_dmach_s { bool used; /* Channel in use */ uint8_t dmamux_req; /* Configured DMAMUX input request */ @@ -110,11 +110,11 @@ struct stm32wb_dmach_s void *arg; /* Argument passed to callback function */ }; -typedef struct stm32wb_dmach_s *DMA_CHANNEL; +typedef struct stm32_dmach_s *DMA_CHANNEL; /* DMA operations */ -struct stm32wb_dma_ops_s +struct stm32_dma_ops_s { /* Disable the DMA transfer */ @@ -145,12 +145,12 @@ struct stm32wb_dma_ops_s #ifdef CONFIG_DEBUG_DMA_INFO /* Sample the DMA registers */ - void (*dma_sample)(DMA_HANDLE handle, struct stm32wb_dmaregs_s *regs); + void (*dma_sample)(DMA_HANDLE handle, struct stm32_dmaregs_s *regs); /* Dump the DMA registers */ void (*dma_dump)(DMA_HANDLE handle, - const struct stm32wb_dmaregs_s *regs, + const struct stm32_dmaregs_s *regs, const char *msg); #endif }; @@ -159,20 +159,20 @@ struct stm32wb_dma_ops_s * Private Functions ****************************************************************************/ -#if defined(CONFIG_STM32WB_DMA1) || defined(CONFIG_STM32WB_DMA2) -static void stm32wb_dma12_disable(DMA_CHANNEL dmachan); -static int stm32wb_dma12_interrupt(int irq, void *context, void *arg); -static void stm32wb_dma12_setup(DMA_HANDLE handle, uint32_t paddr, +#if defined(CONFIG_STM32_DMA1) || defined(CONFIG_STM32_DMA2) +static void stm32_dma12_disable(DMA_CHANNEL dmachan); +static int stm32_dma12_interrupt(int irq, void *context, void *arg); +static void stm32_dma12_setup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr, size_t ntransfers, uint32_t ccr); -static void stm32wb_dma12_start(DMA_HANDLE handle, dma_callback_t callback, +static void stm32_dma12_start(DMA_HANDLE handle, dma_callback_t callback, void *arg, bool half); -static size_t stm32wb_dma12_residual(DMA_HANDLE handle); +static size_t stm32_dma12_residual(DMA_HANDLE handle); #ifdef CONFIG_DEBUG_DMA_INFO -static void stm32wb_dma12_sample(DMA_HANDLE handle, - struct stm32wb_dmaregs_s *regs); -static void stm32wb_dma12_dump(DMA_HANDLE handle, - const struct stm32wb_dmaregs_s *regs, +static void stm32_dma12_sample(DMA_HANDLE handle, + struct stm32_dmaregs_s *regs); +static void stm32_dma12_dump(DMA_HANDLE handle, + const struct stm32_dmaregs_s *regs, const char *msg); #endif #endif @@ -187,14 +187,14 @@ static void dmachan_putreg(DMA_CHANNEL dmachan, uint32_t offset, static void dmamux_putreg(DMA_MUX dmamux, uint32_t offset, uint32_t value); #ifdef CONFIG_DEBUG_DMA_INFO static uint32_t dmamux_getreg(DMA_MUX dmamux, uint32_t offset); -static void stm32wb_dmamux_sample(DMA_MUX dmamux, uint8_t chan, - struct stm32wb_dmaregs_s *regs); -static void stm32wb_dmamux_dump(DMA_MUX dmamux, uint8_t channel, - const struct stm32wb_dmaregs_s *regs); +static void stm32_dmamux_sample(DMA_MUX dmamux, uint8_t chan, + struct stm32_dmaregs_s *regs); +static void stm32_dmamux_dump(DMA_MUX dmamux, uint8_t channel, + const struct stm32_dmaregs_s *regs); #endif -static DMA_CHANNEL stm32wb_dma_channel_get(uint8_t channel, +static DMA_CHANNEL stm32_dma_channel_get(uint8_t channel, uint8_t controller); -static void stm32wb_gdma_limits_get(uint8_t controller, uint8_t *first, +static void stm32_gdma_limits_get(uint8_t controller, uint8_t *first, uint8_t *last); /**************************************************************************** @@ -203,20 +203,20 @@ static void stm32wb_gdma_limits_get(uint8_t controller, uint8_t *first, /* Operations specific to DMA controller */ -static const struct stm32wb_dma_ops_s g_dma_ops[DMA_CONTROLLERS] = +static const struct stm32_dma_ops_s g_dma_ops[DMA_CONTROLLERS] = { -#ifdef CONFIG_STM32WB_DMA1 +#ifdef CONFIG_STM32_DMA1 /* 0 - DMA1 */ { - .dma_disable = stm32wb_dma12_disable, - .dma_interrupt = stm32wb_dma12_interrupt, - .dma_setup = stm32wb_dma12_setup, - .dma_start = stm32wb_dma12_start, - .dma_residual = stm32wb_dma12_residual, + .dma_disable = stm32_dma12_disable, + .dma_interrupt = stm32_dma12_interrupt, + .dma_setup = stm32_dma12_setup, + .dma_start = stm32_dma12_start, + .dma_residual = stm32_dma12_residual, #ifdef CONFIG_DEBUG_DMA_INFO - .dma_sample = stm32wb_dma12_sample, - .dma_dump = stm32wb_dma12_dump, + .dma_sample = stm32_dma12_sample, + .dma_dump = stm32_dma12_dump, #endif }, #else @@ -225,18 +225,18 @@ static const struct stm32wb_dma_ops_s g_dma_ops[DMA_CONTROLLERS] = }, #endif -#ifdef CONFIG_STM32WB_DMA2 +#ifdef CONFIG_STM32_DMA2 /* 1 - DMA2 */ { - .dma_disable = stm32wb_dma12_disable, - .dma_interrupt = stm32wb_dma12_interrupt, - .dma_setup = stm32wb_dma12_setup, - .dma_start = stm32wb_dma12_start, - .dma_residual = stm32wb_dma12_residual, + .dma_disable = stm32_dma12_disable, + .dma_interrupt = stm32_dma12_interrupt, + .dma_setup = stm32_dma12_setup, + .dma_start = stm32_dma12_start, + .dma_residual = stm32_dma12_residual, #ifdef CONFIG_DEBUG_DMA_INFO - .dma_sample = stm32wb_dma12_sample, - .dma_dump = stm32wb_dma12_dump, + .dma_sample = stm32_dma12_sample, + .dma_dump = stm32_dma12_dump, #endif } #else @@ -248,23 +248,23 @@ static const struct stm32wb_dma_ops_s g_dma_ops[DMA_CONTROLLERS] = /* This array describes the state of DMAMUX controller */ -static const struct stm32wb_dmamux_s g_dmamux[DMAMUX_NUM] = +static const struct stm32_dmamux_s g_dmamux[DMAMUX_NUM] = { { .id = 1, .nchan = 14, /* 0-6 - DMA1, 7-13 - DMA2 */ - .base = STM32WB_DMAMUX1_BASE + .base = STM32_DMAMUX1_BASE } }; /* This array describes the state of each controller */ -static const struct stm32wb_dma_s g_dma[DMA_NCHANNELS] = +static const struct stm32_dma_s g_dma[DMA_NCHANNELS] = { /* 0 - DMA1 */ { - .base = STM32WB_DMA1_BASE, + .base = STM32_DMA1_BASE, .first = DMA1_FIRST, .nchan = DMA1_NCHAN, .dmamux = &g_dmamux[DMAMUX1], /* DMAMUX1 channels 0-6 */ @@ -274,7 +274,7 @@ static const struct stm32wb_dma_s g_dma[DMA_NCHANNELS] = /* 1 - DMA2 */ { - .base = STM32WB_DMA2_BASE, + .base = STM32_DMA2_BASE, .first = DMA2_FIRST, .nchan = DMA2_NCHAN, .dmamux = &g_dmamux[DMAMUX1], /* DMAMUX1 channels 7-13 */ @@ -284,125 +284,125 @@ static const struct stm32wb_dma_s g_dma[DMA_NCHANNELS] = /* This array describes the state of each DMA channel. */ -static struct stm32wb_dmach_s g_dmach[DMA_NCHANNELS] = +static struct stm32_dmach_s g_dmach[DMA_NCHANNELS] = { -#ifdef CONFIG_STM32WB_DMA1 +#ifdef CONFIG_STM32_DMA1 /* DMA1 */ { .ctrl = DMA1, .chan = 0, - .irq = STM32WB_IRQ_DMA1CH1, + .irq = STM32_IRQ_DMA1CH1, .shift = DMA_CHAN_SHIFT(0), - .base = STM32WB_DMA1_BASE + STM32WB_DMACHAN_OFFSET(0), + .base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(0), }, { .ctrl = DMA1, .chan = 1, - .irq = STM32WB_IRQ_DMA1CH2, + .irq = STM32_IRQ_DMA1CH2, .shift = DMA_CHAN_SHIFT(1), - .base = STM32WB_DMA1_BASE + STM32WB_DMACHAN_OFFSET(1), + .base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(1), }, { .ctrl = DMA1, .chan = 2, - .irq = STM32WB_IRQ_DMA1CH3, + .irq = STM32_IRQ_DMA1CH3, .shift = DMA_CHAN_SHIFT(2), - .base = STM32WB_DMA1_BASE + STM32WB_DMACHAN_OFFSET(2), + .base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(2), }, { .ctrl = DMA1, .chan = 3, - .irq = STM32WB_IRQ_DMA1CH4, + .irq = STM32_IRQ_DMA1CH4, .shift = DMA_CHAN_SHIFT(3), - .base = STM32WB_DMA1_BASE + STM32WB_DMACHAN_OFFSET(3), + .base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(3), }, { .ctrl = DMA1, .chan = 4, - .irq = STM32WB_IRQ_DMA1CH5, + .irq = STM32_IRQ_DMA1CH5, .shift = DMA_CHAN_SHIFT(4), - .base = STM32WB_DMA1_BASE + STM32WB_DMACHAN_OFFSET(4), + .base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(4), }, { .ctrl = DMA1, .chan = 5, - .irq = STM32WB_IRQ_DMA1CH6, + .irq = STM32_IRQ_DMA1CH6, .shift = DMA_CHAN_SHIFT(5), - .base = STM32WB_DMA1_BASE + STM32WB_DMACHAN_OFFSET(5), + .base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(5), }, { .ctrl = DMA1, .chan = 6, - .irq = STM32WB_IRQ_DMA1CH7, + .irq = STM32_IRQ_DMA1CH7, .shift = DMA_CHAN_SHIFT(6), - .base = STM32WB_DMA1_BASE + STM32WB_DMACHAN_OFFSET(6), + .base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(6), }, #endif -#ifdef CONFIG_STM32WB_DMA2 +#ifdef CONFIG_STM32_DMA2 /* DMA2 */ { .ctrl = DMA2, .chan = 0, - .irq = STM32WB_IRQ_DMA2CH1, + .irq = STM32_IRQ_DMA2CH1, .shift = DMA_CHAN_SHIFT(0), - .base = STM32WB_DMA2_BASE + STM32WB_DMACHAN_OFFSET(0), + .base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(0), }, { .ctrl = DMA2, .chan = 1, - .irq = STM32WB_IRQ_DMA2CH2, + .irq = STM32_IRQ_DMA2CH2, .shift = DMA_CHAN_SHIFT(1), - .base = STM32WB_DMA2_BASE + STM32WB_DMACHAN_OFFSET(1), + .base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(1), }, { .ctrl = DMA2, .chan = 2, - .irq = STM32WB_IRQ_DMA2CH3, + .irq = STM32_IRQ_DMA2CH3, .shift = DMA_CHAN_SHIFT(2), - .base = STM32WB_DMA2_BASE + STM32WB_DMACHAN_OFFSET(2), + .base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(2), }, { .ctrl = DMA2, .chan = 3, - .irq = STM32WB_IRQ_DMA2CH4, + .irq = STM32_IRQ_DMA2CH4, .shift = DMA_CHAN_SHIFT(3), - .base = STM32WB_DMA2_BASE + STM32WB_DMACHAN_OFFSET(3), + .base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(3), }, { .ctrl = DMA2, .chan = 4, - .irq = STM32WB_IRQ_DMA2CH5, + .irq = STM32_IRQ_DMA2CH5, .shift = DMA_CHAN_SHIFT(4), - .base = STM32WB_DMA2_BASE + STM32WB_DMACHAN_OFFSET(4), + .base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(4), }, { .ctrl = DMA2, .chan = 5, - .irq = STM32WB_IRQ_DMA2CH6, + .irq = STM32_IRQ_DMA2CH6, .shift = DMA_CHAN_SHIFT(5), - .base = STM32WB_DMA2_BASE + STM32WB_DMACHAN_OFFSET(5), + .base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(5), }, { .ctrl = DMA2, .chan = 6, - .irq = STM32WB_IRQ_DMA2CH7, + .irq = STM32_IRQ_DMA2CH7, .shift = DMA_CHAN_SHIFT(6), - .base = STM32WB_DMA2_BASE + STM32WB_DMACHAN_OFFSET(6), + .base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(6), }, #endif }; @@ -517,7 +517,7 @@ static uint32_t dmamux_getreg(DMA_MUX dmamux, uint32_t offset) #endif /**************************************************************************** - * Name: stm32wb_dma_channel_get + * Name: stm32_dma_channel_get * * Description: * Get the g_dmach table entry associated with a given DMA controller @@ -525,7 +525,7 @@ static uint32_t dmamux_getreg(DMA_MUX dmamux, uint32_t offset) * ****************************************************************************/ -static DMA_CHANNEL stm32wb_dma_channel_get(uint8_t channel, +static DMA_CHANNEL stm32_dma_channel_get(uint8_t channel, uint8_t controller) { uint8_t first = 0; @@ -533,7 +533,7 @@ static DMA_CHANNEL stm32wb_dma_channel_get(uint8_t channel, /* Get limits for g_dma array */ - stm32wb_gdma_limits_get(controller, &first, &nchan); + stm32_gdma_limits_get(controller, &first, &nchan); DEBUGASSERT(channel <= nchan); @@ -541,14 +541,14 @@ static DMA_CHANNEL stm32wb_dma_channel_get(uint8_t channel, } /**************************************************************************** - * Name: stm32wb_gdma_limits_get + * Name: stm32_gdma_limits_get * * Description: * Get g_dma array limits for a given DMA controller. * ****************************************************************************/ -static void stm32wb_gdma_limits_get(uint8_t controller, uint8_t *first, +static void stm32_gdma_limits_get(uint8_t controller, uint8_t *first, uint8_t *nchan) { DEBUGASSERT(first != NULL); @@ -564,17 +564,17 @@ static void stm32wb_gdma_limits_get(uint8_t controller, uint8_t *first, * DMA controller functions ****************************************************************************/ -#if defined(CONFIG_STM32WB_DMA1) || defined(CONFIG_STM32WB_DMA2) +#if defined(CONFIG_STM32_DMA1) || defined(CONFIG_STM32_DMA2) /**************************************************************************** - * Name: stm32wb_dma12_disable + * Name: stm32_dma12_disable * * Description: * Disable DMA channel (DMA1/DMA2) * ****************************************************************************/ -static void stm32wb_dma12_disable(DMA_CHANNEL dmachan) +static void stm32_dma12_disable(DMA_CHANNEL dmachan) { uint32_t regval; @@ -582,29 +582,29 @@ static void stm32wb_dma12_disable(DMA_CHANNEL dmachan) /* Disable all interrupts at the DMA controller */ - regval = dmachan_getreg(dmachan, STM32WB_DMACHAN_CCR_OFFSET); + regval = dmachan_getreg(dmachan, STM32_DMACHAN_CCR_OFFSET); regval &= ~DMA_CCR_ALLINTS; /* Disable the DMA channel */ regval &= ~DMA_CCR_EN; - dmachan_putreg(dmachan, STM32WB_DMACHAN_CCR_OFFSET, regval); + dmachan_putreg(dmachan, STM32_DMACHAN_CCR_OFFSET, regval); /* Clear pending channel interrupts */ - dmabase_putreg(dmachan, STM32WB_DMA_IFCR_OFFSET, + dmabase_putreg(dmachan, STM32_DMA_IFCR_OFFSET, DMA_ISR_CHAN_MASK(dmachan->chan)); } /**************************************************************************** - * Name: stm32wb_dma12_interrupt + * Name: stm32_dma12_interrupt * * Description: * DMA channel interrupt handler * ****************************************************************************/ -static int stm32wb_dma12_interrupt(int irq, void *context, void *arg) +static int stm32_dma12_interrupt(int irq, void *context, void *arg) { DMA_CHANNEL dmachan; uint32_t isr; @@ -616,22 +616,22 @@ static int stm32wb_dma12_interrupt(int irq, void *context, void *arg) if (0) { } -#ifdef CONFIG_STM32WB_DMA1 - else if (irq >= STM32WB_IRQ_DMA1CH1 && irq <= STM32WB_IRQ_DMA1CH7) +#ifdef CONFIG_STM32_DMA1 + else if (irq >= STM32_IRQ_DMA1CH1 && irq <= STM32_IRQ_DMA1CH7) { - channel = irq - STM32WB_IRQ_DMA1CH1; + channel = irq - STM32_IRQ_DMA1CH1; controller = DMA1; } #endif -#ifdef CONFIG_STM32WB_DMA2 - else if (irq >= STM32WB_IRQ_DMA2CH1 && irq <= STM32WB_IRQ_DMA2CH5) +#ifdef CONFIG_STM32_DMA2 + else if (irq >= STM32_IRQ_DMA2CH1 && irq <= STM32_IRQ_DMA2CH5) { - channel = irq - STM32WB_IRQ_DMA2CH1; + channel = irq - STM32_IRQ_DMA2CH1; controller = DMA2; } - else if (irq >= STM32WB_IRQ_DMA2CH6 && irq <= STM32WB_IRQ_DMA2CH7) + else if (irq >= STM32_IRQ_DMA2CH6 && irq <= STM32_IRQ_DMA2CH7) { - channel = irq - STM32WB_IRQ_DMA2CH6 + (6 - 1); + channel = irq - STM32_IRQ_DMA2CH6 + (6 - 1); controller = DMA2; } #endif @@ -643,11 +643,11 @@ static int stm32wb_dma12_interrupt(int irq, void *context, void *arg) /* Get the channel structure from the stream and controller numbers */ - dmachan = stm32wb_dma_channel_get(channel, controller); + dmachan = stm32_dma_channel_get(channel, controller); /* Get the interrupt status (for this channel only) */ - isr = dmabase_getreg(dmachan, STM32WB_DMA_ISR_OFFSET) & + isr = dmabase_getreg(dmachan, STM32_DMA_ISR_OFFSET) & DMA_ISR_CHAN_MASK(dmachan->chan); /* Invoke the callback */ @@ -660,20 +660,20 @@ static int stm32wb_dma12_interrupt(int irq, void *context, void *arg) /* Clear the interrupts we are handling */ - dmabase_putreg(dmachan, STM32WB_DMA_IFCR_OFFSET, isr); + dmabase_putreg(dmachan, STM32_DMA_IFCR_OFFSET, isr); return OK; } /**************************************************************************** - * Name: stm32wb_dma12_setup + * Name: stm32_dma12_setup * * Description: * Configure DMA before using * ****************************************************************************/ -static void stm32wb_dma12_setup(DMA_HANDLE handle, uint32_t paddr, +static void stm32_dma12_setup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr, size_t ntransfers, uint32_t ccr) { @@ -689,7 +689,7 @@ static void stm32wb_dma12_setup(DMA_HANDLE handle, uint32_t paddr, " ntransfers: %zd ccr: %08" PRIx32 "\n", paddr, maddr, ntransfers, ccr); -#ifdef CONFIG_STM32WB_DMACAPABLE +#ifdef CONFIG_STM32_DMACAPABLE DEBUGASSERT(g_dma_ops[dmachan->ctrl].dma_capable(maddr, ntransfers, ccr)); #endif @@ -697,28 +697,28 @@ static void stm32wb_dma12_setup(DMA_HANDLE handle, uint32_t paddr, * disabled. */ - regval = dmachan_getreg(dmachan, STM32WB_DMACHAN_CCR_OFFSET); + regval = dmachan_getreg(dmachan, STM32_DMACHAN_CCR_OFFSET); regval &= ~(DMA_CCR_EN); - dmachan_putreg(dmachan, STM32WB_DMACHAN_CCR_OFFSET, regval); + dmachan_putreg(dmachan, STM32_DMACHAN_CCR_OFFSET, regval); /* Set the peripheral register address in the DMA_CPARx register. The data * will be moved from/to this address to/from the memory after the * peripheral event. */ - dmachan_putreg(dmachan, STM32WB_DMACHAN_CPAR_OFFSET, paddr); + dmachan_putreg(dmachan, STM32_DMACHAN_CPAR_OFFSET, paddr); /* Set the memory address in the DMA_CMARx register. The data will be * written to or read from this memory after the peripheral event. */ - dmachan_putreg(dmachan, STM32WB_DMACHAN_CMAR_OFFSET, maddr); + dmachan_putreg(dmachan, STM32_DMACHAN_CMAR_OFFSET, maddr); /* Configure the total number of data to be transferred in the DMA_CNDTRx * register. After each peripheral event, this value will be decremented. */ - dmachan_putreg(dmachan, STM32WB_DMACHAN_CNDTR_OFFSET, ntransfers); + dmachan_putreg(dmachan, STM32_DMACHAN_CNDTR_OFFSET, ntransfers); /* Configure the channel priority using the PL[1:0] bits in the DMA_CCRx * register. Configure data transfer direction, circular mode, peripheral @@ -726,7 +726,7 @@ static void stm32wb_dma12_setup(DMA_HANDLE handle, uint32_t paddr, * after half and/or full transfer in the DMA_CCRx register. */ - regval = dmachan_getreg(dmachan, STM32WB_DMACHAN_CCR_OFFSET); + regval = dmachan_getreg(dmachan, STM32_DMACHAN_CCR_OFFSET); regval &= ~(DMA_CCR_MEM2MEM | DMA_CCR_PL_MASK | DMA_CCR_MSIZE_MASK | DMA_CCR_PSIZE_MASK | DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC | DMA_CCR_DIR); @@ -734,17 +734,17 @@ static void stm32wb_dma12_setup(DMA_HANDLE handle, uint32_t paddr, DMA_CCR_PSIZE_MASK | DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC | DMA_CCR_DIR); regval |= ccr; - dmachan_putreg(dmachan, STM32WB_DMACHAN_CCR_OFFSET, regval); + dmachan_putreg(dmachan, STM32_DMACHAN_CCR_OFFSET, regval); } /**************************************************************************** - * Name: stm32wb_dma12_start + * Name: stm32_dma12_start * * Description: * Start the standard DMA transfer ****************************************************************************/ -static void stm32wb_dma12_start(DMA_HANDLE handle, dma_callback_t callback, +static void stm32_dma12_start(DMA_HANDLE handle, dma_callback_t callback, void *arg, bool half) { DMA_CHANNEL dmachan = (DMA_CHANNEL)handle; @@ -762,7 +762,7 @@ static void stm32wb_dma12_start(DMA_HANDLE handle, dma_callback_t callback, * peripheral connected on the channel. */ - ccr = dmachan_getreg(dmachan, STM32WB_DMACHAN_CCR_OFFSET); + ccr = dmachan_getreg(dmachan, STM32_DMACHAN_CCR_OFFSET); ccr |= DMA_CCR_EN; /* In normal mode, interrupt at either half or full completion. In circular @@ -796,41 +796,41 @@ static void stm32wb_dma12_start(DMA_HANDLE handle, dma_callback_t callback, ccr |= (half ? DMA_CCR_HTIE : 0) | DMA_CCR_TCIE | DMA_CCR_TEIE; } - dmachan_putreg(dmachan, STM32WB_DMACHAN_CCR_OFFSET, ccr); + dmachan_putreg(dmachan, STM32_DMACHAN_CCR_OFFSET, ccr); } /**************************************************************************** - * Name: stm32wb_dma12_residual + * Name: stm32_dma12_residual ****************************************************************************/ -static size_t stm32wb_dma12_residual(DMA_HANDLE handle) +static size_t stm32_dma12_residual(DMA_HANDLE handle) { DMA_CHANNEL dmachan = (DMA_CHANNEL)handle; DEBUGASSERT(dmachan->ctrl == DMA1 || dmachan->ctrl == DMA2); - return dmachan_getreg(dmachan, STM32WB_DMACHAN_CNDTR_OFFSET); + return dmachan_getreg(dmachan, STM32_DMACHAN_CNDTR_OFFSET); } /**************************************************************************** - * Name: stm32wb_dma12_sample + * Name: stm32_dma12_sample ****************************************************************************/ #ifdef CONFIG_DEBUG_DMA_INFO -void stm32wb_dma12_sample(DMA_HANDLE handle, struct stm32wb_dmaregs_s *regs) +void stm32_dma12_sample(DMA_HANDLE handle, struct stm32_dmaregs_s *regs) { DMA_CHANNEL dmachan = (DMA_CHANNEL)handle; irqstate_t flags; flags = enter_critical_section(); - regs->isr = dmabase_getreg(dmachan, STM32WB_DMA_ISR_OFFSET); - regs->ccr = dmachan_getreg(dmachan, STM32WB_DMACHAN_CCR_OFFSET); - regs->cndtr = dmachan_getreg(dmachan, STM32WB_DMACHAN_CNDTR_OFFSET); - regs->cpar = dmachan_getreg(dmachan, STM32WB_DMACHAN_CPAR_OFFSET); - regs->cmar = dmachan_getreg(dmachan, STM32WB_DMACHAN_CMAR_OFFSET); + regs->isr = dmabase_getreg(dmachan, STM32_DMA_ISR_OFFSET); + regs->ccr = dmachan_getreg(dmachan, STM32_DMACHAN_CCR_OFFSET); + regs->cndtr = dmachan_getreg(dmachan, STM32_DMACHAN_CNDTR_OFFSET); + regs->cpar = dmachan_getreg(dmachan, STM32_DMACHAN_CPAR_OFFSET); + regs->cmar = dmachan_getreg(dmachan, STM32_DMACHAN_CMAR_OFFSET); - stm32wb_dmamux_sample(g_dma[dmachan->ctrl].dmamux, + stm32_dmamux_sample(g_dma[dmachan->ctrl].dmamux, dmachan->chan + g_dma[dmachan->ctrl].dmamux_offset, regs); @@ -839,12 +839,12 @@ void stm32wb_dma12_sample(DMA_HANDLE handle, struct stm32wb_dmaregs_s *regs) #endif /**************************************************************************** - * Name: stm32wb_dma12_dump + * Name: stm32_dma12_dump ****************************************************************************/ #ifdef CONFIG_DEBUG_DMA_INFO -static void stm32wb_dma12_dump(DMA_HANDLE handle, - const struct stm32wb_dmaregs_s *regs, +static void stm32_dma12_dump(DMA_HANDLE handle, + const struct stm32_dmaregs_s *regs, const char *msg) { DMA_CHANNEL dmachan = (DMA_CHANNEL)handle; @@ -857,71 +857,71 @@ static void stm32wb_dma12_dump(DMA_HANDLE handle, dmachan->ctrl + 1, msg); dmainfo(" ISR[%08x]: %08x\n", - dmabase + STM32WB_DMA_ISR_OFFSET, + dmabase + STM32_DMA_ISR_OFFSET, regs->isr); dmainfo(" CCR[%08x]: %08x\n", - dmachan->base + STM32WB_DMACHAN_CCR_OFFSET, + dmachan->base + STM32_DMACHAN_CCR_OFFSET, regs->ccr); dmainfo(" CNDTR[%08x]: %08x\n", - dmachan->base + STM32WB_DMACHAN_CNDTR_OFFSET, + dmachan->base + STM32_DMACHAN_CNDTR_OFFSET, regs->cndtr); dmainfo(" CPAR[%08x]: %08x\n", - dmachan->base + STM32WB_DMACHAN_CPAR_OFFSET, + dmachan->base + STM32_DMACHAN_CPAR_OFFSET, regs->cpar); dmainfo(" CMAR[%08x]: %08x\n", - dmachan->base + STM32WB_DMACHAN_CMAR_OFFSET, + dmachan->base + STM32_DMACHAN_CMAR_OFFSET, regs->cmar); - stm32wb_dmamux_dump(g_dma[dmachan->ctrl].dmamux, + stm32_dmamux_dump(g_dma[dmachan->ctrl].dmamux, dmachan->chan + g_dma[dmachan->ctrl].dmamux_offset, regs); } #endif -#endif /* CONFIG_STM32WB_DMA1 || CONFIG_STM32WB_DMA2 */ +#endif /* CONFIG_STM32_DMA1 || CONFIG_STM32_DMA2 */ /**************************************************************************** - * Name: stm32wb_dmamux_sample + * Name: stm32_dmamux_sample ****************************************************************************/ #ifdef CONFIG_DEBUG_DMA_INFO -static void stm32wb_dmamux_sample(DMA_MUX dmamux, uint8_t chan, - struct stm32wb_dmaregs_s *regs) +static void stm32_dmamux_sample(DMA_MUX dmamux, uint8_t chan, + struct stm32_dmaregs_s *regs) { - regs->dmamux.ccr = dmamux_getreg(dmamux, STM32WB_DMAMUX_CXCR_OFFSET(chan)); - regs->dmamux.csr = dmamux_getreg(dmamux, STM32WB_DMAMUX_CSR_OFFSET); - regs->dmamux.rg0cr = dmamux_getreg(dmamux, STM32WB_DMAMUX_RG0CR_OFFSET); - regs->dmamux.rg1cr = dmamux_getreg(dmamux, STM32WB_DMAMUX_RG1CR_OFFSET); - regs->dmamux.rg2cr = dmamux_getreg(dmamux, STM32WB_DMAMUX_RG2CR_OFFSET); - regs->dmamux.rg3cr = dmamux_getreg(dmamux, STM32WB_DMAMUX_RG3CR_OFFSET); - regs->dmamux.rgsr = dmamux_getreg(dmamux, STM32WB_DMAMUX_RGSR_OFFSET); + regs->dmamux.ccr = dmamux_getreg(dmamux, STM32_DMAMUX_CXCR_OFFSET(chan)); + regs->dmamux.csr = dmamux_getreg(dmamux, STM32_DMAMUX_CSR_OFFSET); + regs->dmamux.rg0cr = dmamux_getreg(dmamux, STM32_DMAMUX_RG0CR_OFFSET); + regs->dmamux.rg1cr = dmamux_getreg(dmamux, STM32_DMAMUX_RG1CR_OFFSET); + regs->dmamux.rg2cr = dmamux_getreg(dmamux, STM32_DMAMUX_RG2CR_OFFSET); + regs->dmamux.rg3cr = dmamux_getreg(dmamux, STM32_DMAMUX_RG3CR_OFFSET); + regs->dmamux.rgsr = dmamux_getreg(dmamux, STM32_DMAMUX_RGSR_OFFSET); } #endif /**************************************************************************** - * Name: stm32wb_dmamux_dump + * Name: stm32_dmamux_dump ****************************************************************************/ #ifdef CONFIG_DEBUG_DMA_INFO -static void stm32wb_dmamux_dump(DMA_MUX dmamux, uint8_t channel, - const struct stm32wb_dmaregs_s *regs) +static void stm32_dmamux_dump(DMA_MUX dmamux, uint8_t channel, + const struct stm32_dmaregs_s *regs) { dmainfo("DMAMUX%d CH=%d\n", dmamux->id, channel); dmainfo(" CCR[%08x]: %08x\n", - dmamux->base + STM32WB_DMAMUX_CXCR_OFFSET(channel), + dmamux->base + STM32_DMAMUX_CXCR_OFFSET(channel), regs->dmamux.ccr); dmainfo(" CSR[%08x]: %08x\n", - dmamux->base + STM32WB_DMAMUX_CSR_OFFSET, regs->dmamux.csr); + dmamux->base + STM32_DMAMUX_CSR_OFFSET, regs->dmamux.csr); dmainfo(" RG0CR[%08x]: %08x\n", - dmamux->base + STM32WB_DMAMUX_RG0CR_OFFSET, regs->dmamux.rg0cr); + dmamux->base + STM32_DMAMUX_RG0CR_OFFSET, regs->dmamux.rg0cr); dmainfo(" RG1CR[%08x]: %08x\n", - dmamux->base + STM32WB_DMAMUX_RG1CR_OFFSET, regs->dmamux.rg1cr); + dmamux->base + STM32_DMAMUX_RG1CR_OFFSET, regs->dmamux.rg1cr); dmainfo(" RG2CR[%08x]: %08x\n", - dmamux->base + STM32WB_DMAMUX_RG2CR_OFFSET, regs->dmamux.rg2cr); + dmamux->base + STM32_DMAMUX_RG2CR_OFFSET, regs->dmamux.rg2cr); dmainfo(" RG3CR[%08x]: %08x\n", - dmamux->base + STM32WB_DMAMUX_RG3CR_OFFSET, regs->dmamux.rg3cr); + dmamux->base + STM32_DMAMUX_RG3CR_OFFSET, regs->dmamux.rg3cr); dmainfo(" RGSR[%08x]: %08x\n", - dmamux->base + STM32WB_DMAMUX_RGSR_OFFSET, regs->dmamux.rgsr); + dmamux->base + STM32_DMAMUX_RGSR_OFFSET, regs->dmamux.rgsr); }; #endif @@ -980,7 +980,7 @@ void weak_function arm_dma_initialize(void) } /**************************************************************************** - * Name: stm32wb_dmachannel + * Name: stm32_dmachannel * * Description: * Allocate a DMA channel. This function gives the caller mutually @@ -1004,7 +1004,7 @@ void weak_function arm_dma_initialize(void) * ****************************************************************************/ -DMA_HANDLE stm32wb_dmachannel(unsigned int dmamap) +DMA_HANDLE stm32_dmachannel(unsigned int dmamap) { DMA_CHANNEL dmachan; uint8_t dmamux_req; @@ -1026,7 +1026,7 @@ DMA_HANDLE stm32wb_dmachannel(unsigned int dmamap) /* Get g_dma array limits for given controller */ - stm32wb_gdma_limits_get(controller, &first, &nchan); + stm32_gdma_limits_get(controller, &first, &nchan); /* Find available channel for given controller */ @@ -1070,13 +1070,13 @@ DMA_HANDLE stm32wb_dmachannel(unsigned int dmamap) } /**************************************************************************** - * Name: stm32wb_dmafree + * Name: stm32_dmafree * * Description: * Release a DMA channel and unmap DMAMUX if required. * * NOTE: The 'handle' used in this argument must NEVER be used again - * until stm32wb_dmachannel() is called again to re-gain access to the + * until stm32_dmachannel() is called again to re-gain access to the * channel. * * Returned Value: @@ -1088,7 +1088,7 @@ DMA_HANDLE stm32wb_dmachannel(unsigned int dmamap) * ****************************************************************************/ -void stm32wb_dmafree(DMA_HANDLE handle) +void stm32_dmafree(DMA_HANDLE handle) { DMA_CHANNEL dmachan = (DMA_CHANNEL)handle; uint8_t controller; @@ -1114,14 +1114,14 @@ void stm32wb_dmafree(DMA_HANDLE handle) } /**************************************************************************** - * Name: stm32wb_dmasetup + * Name: stm32_dmasetup * * Description: * Configure DMA before using * ****************************************************************************/ -void stm32wb_dmasetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr, +void stm32_dmasetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr, size_t ntransfers, uint32_t ccr) { DMA_CHANNEL dmachan = (DMA_CHANNEL)handle; @@ -1138,18 +1138,18 @@ void stm32wb_dmasetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr, } /**************************************************************************** - * Name: stm32wb_dmastart + * Name: stm32_dmastart * * Description: * Start the DMA transfer * * Assumptions: - * - DMA handle allocated by stm32wb_dmachannel() + * - DMA handle allocated by stm32_dmachannel() * - No DMA in progress * ****************************************************************************/ -void stm32wb_dmastart(DMA_HANDLE handle, dma_callback_t callback, void *arg, +void stm32_dmastart(DMA_HANDLE handle, dma_callback_t callback, void *arg, bool half) { DMA_CHANNEL dmachan = (DMA_CHANNEL)handle; @@ -1179,7 +1179,7 @@ void stm32wb_dmastart(DMA_HANDLE handle, dma_callback_t callback, void *arg, /* DMAMUX Set DMA channel source */ regval = dmachan->dmamux_req << DMAMUX_CCR_DMAREQID_SHIFT; - dmamux_putreg(dmamux, STM32WB_DMAMUX_CXCR_OFFSET(dmamux_chan), regval); + dmamux_putreg(dmamux, STM32_DMAMUX_CXCR_OFFSET(dmamux_chan), regval); /* Enable DMA channel */ @@ -1187,19 +1187,19 @@ void stm32wb_dmastart(DMA_HANDLE handle, dma_callback_t callback, void *arg, } /**************************************************************************** - * Name: stm32wb_dmastop + * Name: stm32_dmastop * * Description: - * Cancel the DMA. After stm32wb_dmastop() is called, the DMA channel is - * reset and stm32wb_dmasetup() must be called before stm32wb_dmastart() + * Cancel the DMA. After stm32_dmastop() is called, the DMA channel is + * reset and stm32_dmasetup() must be called before stm32_dmastart() * can be called again * * Assumptions: - * - DMA handle allocated by stm32wb_dmachannel() + * - DMA handle allocated by stm32_dmachannel() * ****************************************************************************/ -void stm32wb_dmastop(DMA_HANDLE handle) +void stm32_dmastop(DMA_HANDLE handle) { DMA_CHANNEL dmachan = (DMA_CHANNEL)handle; DMA_MUX dmamux; @@ -1224,21 +1224,21 @@ void stm32wb_dmastop(DMA_HANDLE handle) /* DMAMUX Clear DMA channel source */ - dmamux_putreg(dmamux, STM32WB_DMAMUX_CXCR_OFFSET(dmamux_chan), 0); + dmamux_putreg(dmamux, STM32_DMAMUX_CXCR_OFFSET(dmamux_chan), 0); } /**************************************************************************** - * Name: stm32wb_dmaresidual + * Name: stm32_dmaresidual * * Description: * Read the DMA bytes-remaining register. * * Assumptions: - * - DMA handle allocated by stm32wb_dmachannel() + * - DMA handle allocated by stm32_dmachannel() * ****************************************************************************/ -size_t stm32wb_dmaresidual(DMA_HANDLE handle) +size_t stm32_dmaresidual(DMA_HANDLE handle) { DMA_CHANNEL dmachan = (DMA_CHANNEL)handle; uint8_t controller; @@ -1254,7 +1254,7 @@ size_t stm32wb_dmaresidual(DMA_HANDLE handle) } /**************************************************************************** - * Name: stm32wb_dmacapable + * Name: stm32_dmacapable * * Description: * Check if the DMA controller can transfer data to/from given memory @@ -1270,8 +1270,8 @@ size_t stm32wb_dmaresidual(DMA_HANDLE handle) * ****************************************************************************/ -#ifdef CONFIG_STM32WB_DMACAPABLE -bool stm32wb_dmacapable(uint32_t maddr, uint32_t count, uint32_t ccr) +#ifdef CONFIG_STM32_DMACAPABLE +bool stm32_dmacapable(uint32_t maddr, uint32_t count, uint32_t ccr) { unsigned int msize_shift; uint32_t transfer_size; @@ -1315,23 +1315,23 @@ bool stm32wb_dmacapable(uint32_t maddr, uint32_t count, uint32_t ccr) mend = maddr + (count << msize_shift) - 1; - if ((maddr & STM32WB_REGION_MASK) != (mend & STM32WB_REGION_MASK)) + if ((maddr & STM32_REGION_MASK) != (mend & STM32_REGION_MASK)) { return false; } - switch (maddr & STM32WB_REGION_MASK) + switch (maddr & STM32_REGION_MASK) { - case STM32WB_PERIPH_BASE: - case STM32WB_FSMC_BASE: - case STM32WB_FSMC_BANK1: - case STM32WB_FSMC_BANK2: - case STM32WB_FSMC_BANK3: - case STM32WB_QSPI_BANK: - case STM32WB_SRAM_BASE: - case STM32WB_SRAM2_BASE: - case STM32WB_SRAM3_BASE: - case STM32WB_CODE_BASE: + case STM32_PERIPH_BASE: + case STM32_FSMC_BASE: + case STM32_FSMC_BANK1: + case STM32_FSMC_BANK2: + case STM32_FSMC_BANK3: + case STM32_QSPI_BANK: + case STM32_SRAM_BASE: + case STM32_SRAM2_BASE: + case STM32_SRAM3_BASE: + case STM32_CODE_BASE: /* All RAM and flash is supported */ @@ -1347,18 +1347,18 @@ bool stm32wb_dmacapable(uint32_t maddr, uint32_t count, uint32_t ccr) #endif /**************************************************************************** - * Name: stm32wb_dmasample + * Name: stm32_dmasample * * Description: * Sample DMA register contents * * Assumptions: - * - DMA handle allocated by stm32wb_dmachannel() + * - DMA handle allocated by stm32_dmachannel() * ****************************************************************************/ #ifdef CONFIG_DEBUG_DMA_INFO -void stm32wb_dmasample(DMA_HANDLE handle, struct stm32wb_dmaregs_s *regs) +void stm32_dmasample(DMA_HANDLE handle, struct stm32_dmaregs_s *regs) { DMA_CHANNEL dmachan = (DMA_CHANNEL)handle; uint8_t controller; @@ -1375,18 +1375,18 @@ void stm32wb_dmasample(DMA_HANDLE handle, struct stm32wb_dmaregs_s *regs) #endif /**************************************************************************** - * Name: stm32wb_dmadump + * Name: stm32_dmadump * * Description: * Dump previously sampled DMA register contents * * Assumptions: - * - DMA handle allocated by stm32wb_dmachannel() + * - DMA handle allocated by stm32_dmachannel() * ****************************************************************************/ #ifdef CONFIG_DEBUG_DMA_INFO -void stm32wb_dmadump(DMA_HANDLE handle, const struct stm32wb_dmaregs_s *regs, +void stm32_dmadump(DMA_HANDLE handle, const struct stm32_dmaregs_s *regs, const char *msg) { DMA_CHANNEL dmachan = (DMA_CHANNEL)handle; diff --git a/arch/arm/src/stm32wb/stm32wb_dma.h b/arch/arm/src/stm32wb/stm32wb_dma.h index 6caff11690612..8fb0903eae7ff 100644 --- a/arch/arm/src/stm32wb/stm32wb_dma.h +++ b/arch/arm/src/stm32wb/stm32wb_dma.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32WB_STM32WB_DMA_H -#define __ARCH_ARM_SRC_STM32WB_STM32WB_DMA_H +#ifndef __ARCH_ARM_SRC_STM32WB_STM32_DMA_H +#define __ARCH_ARM_SRC_STM32WB_STM32_DMA_H /**************************************************************************** * Included Files @@ -71,14 +71,14 @@ typedef void *DMA_HANDLE; typedef void (*dma_callback_t)(DMA_HANDLE handle, uint8_t status, void *arg); #ifdef CONFIG_DEBUG_DMA_INFO -struct stm32wb_dmaregs_s +struct stm32_dmaregs_s { uint32_t isr; /* Interrupt Status Register; each channel gets 4 bits */ uint32_t ccr; /* Channel Configuration Register; determines functionality */ uint32_t cndtr; /* Channel Count Register; determines number of transfers */ uint32_t cpar; /* Channel Peripheral Address Register; determines start */ uint32_t cmar; /* Channel Memory Address Register; determines start */ -#ifndef CONFIG_STM32WB_HAVE_DMAMUX +#ifndef CONFIG_STM32_HAVE_DMAMUX uint32_t cselr; /* Channel Selection Register; chooses peripheral bound */ #else struct @@ -139,18 +139,18 @@ extern "C" * ****************************************************************************/ -DMA_HANDLE stm32wb_dmachannel(unsigned int dmamap); +DMA_HANDLE stm32_dmachannel(unsigned int dmamap); /**************************************************************************** - * Name: stm32wb_dmafree + * Name: stm32_dmafree * * Description: * Release a DMA channel. If another thread is waiting for this DMA - * channel in a call to stm32wb_dmachannel, then this function will + * channel in a call to stm32_dmachannel, then this function will * re-assign the DMA channel to that thread and wake it up. * * NOTE: The 'handle' used in this argument must NEVER be used again - * until stm32wb_dmachannel() is called again to re-gain access to + * until stm32_dmachannel() is called again to re-gain access to * the channel. * * Returned Value: @@ -162,64 +162,64 @@ DMA_HANDLE stm32wb_dmachannel(unsigned int dmamap); * ****************************************************************************/ -void stm32wb_dmafree(DMA_HANDLE handle); +void stm32_dmafree(DMA_HANDLE handle); /**************************************************************************** - * Name: stm32wb_dmasetup + * Name: stm32_dmasetup * * Description: * Configure DMA before using * ****************************************************************************/ -void stm32wb_dmasetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr, +void stm32_dmasetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr, size_t ntransfers, uint32_t ccr); /**************************************************************************** - * Name: stm32wb_dmastart + * Name: stm32_dmastart * * Description: * Start the DMA transfer * * Assumptions: - * - DMA handle allocated by stm32wb_dmachannel() + * - DMA handle allocated by stm32_dmachannel() * - No DMA in progress * ****************************************************************************/ -void stm32wb_dmastart(DMA_HANDLE handle, dma_callback_t callback, void *arg, +void stm32_dmastart(DMA_HANDLE handle, dma_callback_t callback, void *arg, bool half); /**************************************************************************** - * Name: stm32wb_dmastop + * Name: stm32_dmastop * * Description: - * Cancel the DMA. After stm32wb_dmastop() is called, the DMA channel is - * reset and stm32wb_dmasetup() must be called before stm32wb_dmastart() + * Cancel the DMA. After stm32_dmastop() is called, the DMA channel is + * reset and stm32_dmasetup() must be called before stm32_dmastart() * can be called again * * Assumptions: - * - DMA handle allocated by stm32wb_dmachannel() + * - DMA handle allocated by stm32_dmachannel() * ****************************************************************************/ -void stm32wb_dmastop(DMA_HANDLE handle); +void stm32_dmastop(DMA_HANDLE handle); /**************************************************************************** - * Name: stm32wb_dmaresidual + * Name: stm32_dmaresidual * * Description: * Returns the number of bytes remaining to be transferred * * Assumptions: - * - DMA handle allocated by stm32wb_dmachannel() + * - DMA handle allocated by stm32_dmachannel() * ****************************************************************************/ -size_t stm32wb_dmaresidual(DMA_HANDLE handle); +size_t stm32_dmaresidual(DMA_HANDLE handle); /**************************************************************************** - * Name: stm32wb_dmacapable + * Name: stm32_dmacapable * * Description: * Check if the DMA controller can transfer data to/from given memory @@ -233,45 +233,45 @@ size_t stm32wb_dmaresidual(DMA_HANDLE handle); * ****************************************************************************/ -#ifdef CONFIG_STM32WB_DMACAPABLE -bool stm32wb_dmacapable(uintptr_t maddr, uint32_t count, uint32_t ccr); +#ifdef CONFIG_STM32_DMACAPABLE +bool stm32_dmacapable(uintptr_t maddr, uint32_t count, uint32_t ccr); #else -# define stm32wb_dmacapable(maddr, count, ccr) (true) +# define stm32_dmacapable(maddr, count, ccr) (true) #endif /**************************************************************************** - * Name: stm32wb_dmasample + * Name: stm32_dmasample * * Description: * Sample DMA register contents * * Assumptions: - * - DMA handle allocated by stm32wb_dmachannel() + * - DMA handle allocated by stm32_dmachannel() * ****************************************************************************/ #ifdef CONFIG_DEBUG_DMA_INFO -void stm32wb_dmasample(DMA_HANDLE handle, struct stm32wb_dmaregs_s *regs); +void stm32_dmasample(DMA_HANDLE handle, struct stm32_dmaregs_s *regs); #else -# define stm32wb_dmasample(handle,regs) ((void)0) +# define stm32_dmasample(handle,regs) ((void)0) #endif /**************************************************************************** - * Name: stm32wb_dmadump + * Name: stm32_dmadump * * Description: * Dump previously sampled DMA register contents * * Assumptions: - * - DMA handle allocated by stm32wb_dmachannel() + * - DMA handle allocated by stm32_dmachannel() * ****************************************************************************/ #ifdef CONFIG_DEBUG_DMA_INFO -void stm32wb_dmadump(DMA_HANDLE handle, const struct stm32wb_dmaregs_s *regs, +void stm32_dmadump(DMA_HANDLE handle, const struct stm32_dmaregs_s *regs, const char *msg); #else -# define stm32wb_dmadump(handle,regs,msg) ((void)0) +# define stm32_dmadump(handle,regs,msg) ((void)0) #endif #undef EXTERN @@ -280,4 +280,4 @@ void stm32wb_dmadump(DMA_HANDLE handle, const struct stm32wb_dmaregs_s *regs, #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32WB_STM32WB_DMA_H */ +#endif /* __ARCH_ARM_SRC_STM32WB_STM32_DMA_H */ diff --git a/arch/arm/src/stm32wb/stm32wb_dumpgpio.c b/arch/arm/src/stm32wb/stm32wb_dumpgpio.c index a0e29b306f188..6d3a9fddd60d1 100644 --- a/arch/arm/src/stm32wb/stm32wb_dumpgpio.c +++ b/arch/arm/src/stm32wb/stm32wb_dumpgpio.c @@ -49,13 +49,13 @@ /* Port letters for prettier debug output */ -static const char g_portchar[STM32WB_NPORTS] = +static const char g_portchar[STM32_NPORTS] = { 'A', 'B', 'C', -#if defined(CONFIG_STM32WB_GPIO_HAVE_PORTD) +#if defined(CONFIG_STM32_GPIO_HAVE_PORTD) 'D', #endif -#if defined(CONFIG_STM32WB_GPIO_HAVE_PORTE) +#if defined(CONFIG_STM32_GPIO_HAVE_PORTE) 'E', #endif 'H' @@ -66,14 +66,14 @@ static const char g_portchar[STM32WB_NPORTS] = ****************************************************************************/ /**************************************************************************** - * Function: stm32wb_dumpgpio + * Function: stm32_dumpgpio * * Description: * Dump all GPIO registers associated with the provided base address * ****************************************************************************/ -int stm32wb_dumpgpio(uint32_t pinset, const char *msg) +int stm32_dumpgpio(uint32_t pinset, const char *msg) { irqstate_t flags; uint32_t base; @@ -88,31 +88,31 @@ int stm32wb_dumpgpio(uint32_t pinset, const char *msg) flags = enter_critical_section(); - DEBUGASSERT(port < STM32WB_NPORTS); + DEBUGASSERT(port < STM32_NPORTS); _info("GPIO%c pinset: %08x base: %08x -- %s\n", g_portchar[port], pinset, base, msg); - if ((getreg32(STM32WB_RCC_AHB2ENR) & RCC_AHB2ENR_GPIOEN(port)) != 0) + if ((getreg32(STM32_RCC_AHB2ENR) & RCC_AHB2ENR_GPIOEN(port)) != 0) { _info(" MODE: %08x OTYPE: %04x OSPEED: %08x PUPDR: %08x\n", - getreg32(base + STM32WB_GPIO_MODER_OFFSET), - getreg32(base + STM32WB_GPIO_OTYPER_OFFSET), - getreg32(base + STM32WB_GPIO_OSPEED_OFFSET), - getreg32(base + STM32WB_GPIO_PUPDR_OFFSET)); + getreg32(base + STM32_GPIO_MODER_OFFSET), + getreg32(base + STM32_GPIO_OTYPER_OFFSET), + getreg32(base + STM32_GPIO_OSPEED_OFFSET), + getreg32(base + STM32_GPIO_PUPDR_OFFSET)); _info(" IDR: %04x ODR: %04x BSRR: %08x LCKR: %04x\n", - getreg32(base + STM32WB_GPIO_IDR_OFFSET), - getreg32(base + STM32WB_GPIO_ODR_OFFSET), - getreg32(base + STM32WB_GPIO_BSRR_OFFSET), - getreg32(base + STM32WB_GPIO_LCKR_OFFSET)); + getreg32(base + STM32_GPIO_IDR_OFFSET), + getreg32(base + STM32_GPIO_ODR_OFFSET), + getreg32(base + STM32_GPIO_BSRR_OFFSET), + getreg32(base + STM32_GPIO_LCKR_OFFSET)); _info(" AFRH: %08x AFRL: %08x\n", - getreg32(base + STM32WB_GPIO_AFRH_OFFSET), - getreg32(base + STM32WB_GPIO_AFRL_OFFSET)); + getreg32(base + STM32_GPIO_AFRH_OFFSET), + getreg32(base + STM32_GPIO_AFRL_OFFSET)); } else { _info(" GPIO%c not enabled: AHB2ENR: %08x\n", - g_portchar[port], getreg32(STM32WB_RCC_AHB2ENR)); + g_portchar[port], getreg32(STM32_RCC_AHB2ENR)); } leave_critical_section(flags); diff --git a/arch/arm/src/stm32wb/stm32wb_exti.h b/arch/arm/src/stm32wb/stm32wb_exti.h index 4049422399141..ffcc754fe79f6 100644 --- a/arch/arm/src/stm32wb/stm32wb_exti.h +++ b/arch/arm/src/stm32wb/stm32wb_exti.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32WB_STM32WB_EXTI_H -#define __ARCH_ARM_SRC_STM32WB_STM32WB_EXTI_H +#ifndef __ARCH_ARM_SRC_STM32WB_STM32_EXTI_H +#define __ARCH_ARM_SRC_STM32WB_STM32_EXTI_H /**************************************************************************** * Included Files @@ -54,7 +54,7 @@ extern "C" ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_gpiosetevent + * Name: stm32_gpiosetevent * * Description: * Sets/clears GPIO based event and interrupt triggers. @@ -73,11 +73,11 @@ extern "C" * ****************************************************************************/ -int stm32wb_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, +int stm32_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, bool event, xcpt_t func, void *arg); /**************************************************************************** - * Name: stm32wb_exti_alarm + * Name: stm32_exti_alarm * * Description: * Sets/clears EXTI alarm interrupt. @@ -95,12 +95,12 @@ int stm32wb_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, ****************************************************************************/ #ifdef CONFIG_RTC_ALARM -int stm32wb_exti_alarm(bool risingedge, bool fallingedge, bool event, +int stm32_exti_alarm(bool risingedge, bool fallingedge, bool event, xcpt_t func, void *arg); #endif /**************************************************************************** - * Name: stm32wb_exti_wakeup + * Name: stm32_exti_wakeup * * Description: * Sets/clears EXTI wakeup interrupt. @@ -118,7 +118,7 @@ int stm32wb_exti_alarm(bool risingedge, bool fallingedge, bool event, ****************************************************************************/ #ifdef CONFIG_RTC_PERIODIC -int stm32wb_exti_wakeup(bool risingedge, bool fallingedge, bool event, +int stm32_exti_wakeup(bool risingedge, bool fallingedge, bool event, xcpt_t func, void *arg); #endif @@ -128,4 +128,4 @@ int stm32wb_exti_wakeup(bool risingedge, bool fallingedge, bool event, #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32WB_STM32WB_EXTI_H */ +#endif /* __ARCH_ARM_SRC_STM32WB_STM32_EXTI_H */ diff --git a/arch/arm/src/stm32wb/stm32wb_exti_alarm.c b/arch/arm/src/stm32wb/stm32wb_exti_alarm.c index a0076663dba61..cff98eaeb9384 100644 --- a/arch/arm/src/stm32wb/stm32wb_exti_alarm.c +++ b/arch/arm/src/stm32wb/stm32wb_exti_alarm.c @@ -51,14 +51,14 @@ static void *g_callback_arg; ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_exti_alarm_isr + * Name: stm32_exti_alarm_isr * * Description: * EXTI ALARM interrupt service routine/dispatcher * ****************************************************************************/ -static int stm32wb_exti_alarm_isr(int irq, void *context, void *arg) +static int stm32_exti_alarm_isr(int irq, void *context, void *arg) { int ret = OK; @@ -71,7 +71,7 @@ static int stm32wb_exti_alarm_isr(int irq, void *context, void *arg) /* Clear the pending EXTI interrupt */ - putreg32(EXTI_PR1_PIF(EXTI_EVT_RTCALARM), STM32WB_EXTI_PR1); + putreg32(EXTI_PR1_PIF(EXTI_EVT_RTCALARM), STM32_EXTI_PR1); return ret; } @@ -81,7 +81,7 @@ static int stm32wb_exti_alarm_isr(int irq, void *context, void *arg) ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_exti_alarm + * Name: stm32_exti_alarm * * Description: * Sets/clears EXTI alarm interrupt. @@ -97,7 +97,7 @@ static int stm32wb_exti_alarm_isr(int irq, void *context, void *arg) * ****************************************************************************/ -int stm32wb_exti_alarm(bool risingedge, bool fallingedge, bool event, +int stm32_exti_alarm(bool risingedge, bool fallingedge, bool event, xcpt_t func, void *arg) { g_alarm_callback = func; @@ -107,29 +107,29 @@ int stm32wb_exti_alarm(bool risingedge, bool fallingedge, bool event, if (func) { - irq_attach(STM32WB_IRQ_RTCALRM, stm32wb_exti_alarm_isr, NULL); - up_enable_irq(STM32WB_IRQ_RTCALRM); + irq_attach(STM32_IRQ_RTCALRM, stm32_exti_alarm_isr, NULL); + up_enable_irq(STM32_IRQ_RTCALRM); } else { - up_disable_irq(STM32WB_IRQ_RTCALRM); + up_disable_irq(STM32_IRQ_RTCALRM); } /* Configure rising/falling edges */ - modifyreg32(STM32WB_EXTI_RTSR1, + modifyreg32(STM32_EXTI_RTSR1, risingedge ? 0 : EXTI_RTSR1_RT(EXTI_EVT_RTCALARM), risingedge ? EXTI_RTSR1_RT(EXTI_EVT_RTCALARM) : 0); - modifyreg32(STM32WB_EXTI_FTSR1, + modifyreg32(STM32_EXTI_FTSR1, fallingedge ? 0 : EXTI_FTSR1_FT(EXTI_EVT_RTCALARM), fallingedge ? EXTI_FTSR1_FT(EXTI_EVT_RTCALARM) : 0); /* Enable Events and Interrupts */ - modifyreg32(STM32WB_EXTI_C1EMR1, + modifyreg32(STM32_EXTI_C1EMR1, event ? 0 : EXTI_C1EMR1_EM(EXTI_EVT_RTCALARM), event ? EXTI_C1EMR1_EM(EXTI_EVT_RTCALARM) : 0); - modifyreg32(STM32WB_EXTI_C1IMR1, + modifyreg32(STM32_EXTI_C1IMR1, func ? 0 : EXTI_C1IMR1_IM(EXTI_EVT_RTCALARM), func ? EXTI_C1IMR1_IM(EXTI_EVT_RTCALARM) : 0); diff --git a/arch/arm/src/stm32wb/stm32wb_exti_gpio.c b/arch/arm/src/stm32wb/stm32wb_exti_gpio.c index 8ef567ccd1dc7..6e6597b60ca33 100644 --- a/arch/arm/src/stm32wb/stm32wb_exti_gpio.c +++ b/arch/arm/src/stm32wb/stm32wb_exti_gpio.c @@ -65,13 +65,13 @@ static struct gpio_callback_s g_gpio_handlers[16]; * Interrupt Service Routines - Dispatchers ****************************************************************************/ -static int stm32wb_exti0_isr(int irq, void *context, void *arg) +static int stm32_exti0_isr(int irq, void *context, void *arg) { int ret = OK; /* Clear the pending interrupt */ - putreg32(EXTI_PR1_PIF(0), STM32WB_EXTI_PR1); + putreg32(EXTI_PR1_PIF(0), STM32_EXTI_PR1); /* And dispatch the interrupt to the handler */ @@ -86,13 +86,13 @@ static int stm32wb_exti0_isr(int irq, void *context, void *arg) return ret; } -static int stm32wb_exti1_isr(int irq, void *context, void *arg) +static int stm32_exti1_isr(int irq, void *context, void *arg) { int ret = OK; /* Clear the pending interrupt */ - putreg32(EXTI_PR1_PIF(1), STM32WB_EXTI_PR1); + putreg32(EXTI_PR1_PIF(1), STM32_EXTI_PR1); /* And dispatch the interrupt to the handler */ @@ -107,13 +107,13 @@ static int stm32wb_exti1_isr(int irq, void *context, void *arg) return ret; } -static int stm32wb_exti2_isr(int irq, void *context, void *arg) +static int stm32_exti2_isr(int irq, void *context, void *arg) { int ret = OK; /* Clear the pending interrupt */ - putreg32(EXTI_PR1_PIF(2), STM32WB_EXTI_PR1); + putreg32(EXTI_PR1_PIF(2), STM32_EXTI_PR1); /* And dispatch the interrupt to the handler */ @@ -128,13 +128,13 @@ static int stm32wb_exti2_isr(int irq, void *context, void *arg) return ret; } -static int stm32wb_exti3_isr(int irq, void *context, void *arg) +static int stm32_exti3_isr(int irq, void *context, void *arg) { int ret = OK; /* Clear the pending interrupt */ - putreg32(EXTI_PR1_PIF(3), STM32WB_EXTI_PR1); + putreg32(EXTI_PR1_PIF(3), STM32_EXTI_PR1); /* And dispatch the interrupt to the handler */ @@ -149,13 +149,13 @@ static int stm32wb_exti3_isr(int irq, void *context, void *arg) return ret; } -static int stm32wb_exti4_isr(int irq, void *context, void *arg) +static int stm32_exti4_isr(int irq, void *context, void *arg) { int ret = OK; /* Clear the pending interrupt */ - putreg32(EXTI_PR1_PIF(4), STM32WB_EXTI_PR1); + putreg32(EXTI_PR1_PIF(4), STM32_EXTI_PR1); /* And dispatch the interrupt to the handler */ @@ -170,7 +170,7 @@ static int stm32wb_exti4_isr(int irq, void *context, void *arg) return ret; } -static int stm32wb_exti_multiisr(int irq, void *context, void *arg, +static int stm32_exti_multiisr(int irq, void *context, void *arg, int first, int last) { uint32_t pr; @@ -179,7 +179,7 @@ static int stm32wb_exti_multiisr(int irq, void *context, void *arg, /* Examine the state of each pin in the group */ - pr = getreg32(STM32WB_EXTI_PR1); + pr = getreg32(STM32_EXTI_PR1); /* And dispatch the interrupt to the handler */ @@ -192,7 +192,7 @@ static int stm32wb_exti_multiisr(int irq, void *context, void *arg, { /* Clear the pending interrupt */ - putreg32(mask, STM32WB_EXTI_PR1); + putreg32(mask, STM32_EXTI_PR1); /* And dispatch the interrupt to the handler */ @@ -214,14 +214,14 @@ static int stm32wb_exti_multiisr(int irq, void *context, void *arg, return ret; } -static int stm32wb_exti95_isr(int irq, void *context, void *arg) +static int stm32_exti95_isr(int irq, void *context, void *arg) { - return stm32wb_exti_multiisr(irq, context, arg, 5, 9); + return stm32_exti_multiisr(irq, context, arg, 5, 9); } -static int stm32wb_exti1510_isr(int irq, void *context, void *arg) +static int stm32_exti1510_isr(int irq, void *context, void *arg) { - return stm32wb_exti_multiisr(irq, context, arg, 10, 15); + return stm32_exti_multiisr(irq, context, arg, 10, 15); } /**************************************************************************** @@ -229,7 +229,7 @@ static int stm32wb_exti1510_isr(int irq, void *context, void *arg) ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_gpiosetevent + * Name: stm32_gpiosetevent * * Description: * Sets/clears GPIO based event and interrupt triggers. @@ -251,7 +251,7 @@ static int stm32wb_exti1510_isr(int irq, void *context, void *arg) * ****************************************************************************/ -int stm32wb_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, +int stm32_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, bool event, xcpt_t func, void *arg) { struct gpio_callback_s *shared_cbs; @@ -265,43 +265,43 @@ int stm32wb_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, if (pin < 5) { - irq = pin + STM32WB_IRQ_EXTI0; + irq = pin + STM32_IRQ_EXTI0; nshared = 1; shared_cbs = &g_gpio_handlers[pin]; switch (pin) { case 0: - handler = stm32wb_exti0_isr; + handler = stm32_exti0_isr; break; case 1: - handler = stm32wb_exti1_isr; + handler = stm32_exti1_isr; break; case 2: - handler = stm32wb_exti2_isr; + handler = stm32_exti2_isr; break; case 3: - handler = stm32wb_exti3_isr; + handler = stm32_exti3_isr; break; default: - handler = stm32wb_exti4_isr; + handler = stm32_exti4_isr; break; } } else if (pin < 10) { - irq = STM32WB_IRQ_EXTI95; - handler = stm32wb_exti95_isr; + irq = STM32_IRQ_EXTI95; + handler = stm32_exti95_isr; shared_cbs = &g_gpio_handlers[5]; nshared = 5; } else { - irq = STM32WB_IRQ_EXTI1510; - handler = stm32wb_exti1510_isr; + irq = STM32_IRQ_EXTI1510; + handler = stm32_exti1510_isr; shared_cbs = &g_gpio_handlers[10]; nshared = 6; } @@ -347,23 +347,23 @@ int stm32wb_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, pinset |= GPIO_EXTI; } - stm32wb_configgpio(pinset); + stm32_configgpio(pinset); /* Configure rising/falling edges */ - modifyreg32(STM32WB_EXTI_RTSR1, + modifyreg32(STM32_EXTI_RTSR1, risingedge ? 0 : EXTI_RTSR1_RT(pin), risingedge ? EXTI_RTSR1_RT(pin) : 0); - modifyreg32(STM32WB_EXTI_FTSR1, + modifyreg32(STM32_EXTI_FTSR1, fallingedge ? 0 : EXTI_FTSR1_FT(pin), fallingedge ? EXTI_FTSR1_FT(pin) : 0); /* Enable Events and Interrupts */ - modifyreg32(STM32WB_EXTI_C1EMR1, + modifyreg32(STM32_EXTI_C1EMR1, event ? 0 : EXTI_C1EMR1_EM(pin), event ? EXTI_C1EMR1_EM(pin) : 0); - modifyreg32(STM32WB_EXTI_C1IMR1, + modifyreg32(STM32_EXTI_C1IMR1, func ? 0 : EXTI_C1IMR1_IM(pin), func ? EXTI_C1IMR1_IM(pin) : 0); diff --git a/arch/arm/src/stm32wb/stm32wb_exti_pwr.c b/arch/arm/src/stm32wb/stm32wb_exti_pwr.c index d470837ff4d00..0cc045d27ca27 100644 --- a/arch/arm/src/stm32wb/stm32wb_exti_pwr.c +++ b/arch/arm/src/stm32wb/stm32wb_exti_pwr.c @@ -56,20 +56,20 @@ static void *g_callback_arg; ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_exti_pvd_isr + * Name: stm32_exti_pvd_isr * * Description: * EXTI PVD interrupt service routine/dispatcher * ****************************************************************************/ -static int stm32wb_exti_pvd_isr(int irq, void *context, void *arg) +static int stm32_exti_pvd_isr(int irq, void *context, void *arg) { int ret = OK; /* Clear the pending EXTI interrupt */ - putreg32(EXTI_PR1_PIF(EXTI_EVT_PVD), STM32WB_EXTI_PR1); + putreg32(EXTI_PR1_PIF(EXTI_EVT_PVD), STM32_EXTI_PR1); /* And dispatch the interrupt to the handler */ @@ -86,7 +86,7 @@ static int stm32wb_exti_pvd_isr(int irq, void *context, void *arg) ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_exti_pvd + * Name: stm32_exti_pvd * * Description: * Sets/clears EXTI PVD interrupt. @@ -102,7 +102,7 @@ static int stm32wb_exti_pvd_isr(int irq, void *context, void *arg) * ****************************************************************************/ -int stm32wb_exti_pvd(bool risingedge, bool fallingedge, bool event, +int stm32_exti_pvd(bool risingedge, bool fallingedge, bool event, xcpt_t func, void *arg) { /* Get the previous GPIO IRQ handler; Save the new IRQ handler. */ @@ -114,29 +114,29 @@ int stm32wb_exti_pvd(bool risingedge, bool fallingedge, bool event, if (func) { - irq_attach(STM32WB_IRQ_PVD, stm32wb_exti_pvd_isr, NULL); - up_enable_irq(STM32WB_IRQ_PVD); + irq_attach(STM32_IRQ_PVD, stm32_exti_pvd_isr, NULL); + up_enable_irq(STM32_IRQ_PVD); } else { - up_disable_irq(STM32WB_IRQ_PVD); + up_disable_irq(STM32_IRQ_PVD); } /* Configure rising/falling edges */ - modifyreg32(STM32WB_EXTI_RTSR1, + modifyreg32(STM32_EXTI_RTSR1, risingedge ? 0 : EXTI_RTSR1_RT(EXTI_EVT_PVD), risingedge ? EXTI_RTSR1_RT(EXTI_EVT_PVD) : 0); - modifyreg32(STM32WB_EXTI_FTSR1, + modifyreg32(STM32_EXTI_FTSR1, fallingedge ? 0 : EXTI_FTSR1_FT(EXTI_EVT_PVD), fallingedge ? EXTI_FTSR1_FT(EXTI_EVT_PVD) : 0); /* Enable Events and Interrupts */ - modifyreg32(STM32WB_EXTI_C1EMR1, + modifyreg32(STM32_EXTI_C1EMR1, event ? 0 : EXTI_C1EMR1_EM(EXTI_EVT_PVD), event ? EXTI_C1EMR1_EM(EXTI_EVT_PVD) : 0); - modifyreg32(STM32WB_EXTI_C1IMR1, + modifyreg32(STM32_EXTI_C1IMR1, func ? 0 : EXTI_C1IMR1_IM(EXTI_EVT_PVD), func ? EXTI_C1IMR1_IM(EXTI_EVT_PVD) : 0); diff --git a/arch/arm/src/stm32wb/stm32wb_exti_wakeup.c b/arch/arm/src/stm32wb/stm32wb_exti_wakeup.c index eae587fda8e1b..32fba5d71e982 100644 --- a/arch/arm/src/stm32wb/stm32wb_exti_wakeup.c +++ b/arch/arm/src/stm32wb/stm32wb_exti_wakeup.c @@ -51,14 +51,14 @@ static void *g_callback_arg; ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_exti_wakeup_isr + * Name: stm32_exti_wakeup_isr * * Description: * EXTI periodic WAKEUP interrupt service routine/dispatcher * ****************************************************************************/ -static int stm32wb_exti_wakeup_isr(int irq, void *context, void *arg) +static int stm32_exti_wakeup_isr(int irq, void *context, void *arg) { int ret = OK; @@ -71,7 +71,7 @@ static int stm32wb_exti_wakeup_isr(int irq, void *context, void *arg) /* Clear the pending EXTI interrupt */ - putreg32(EXTI_RTC_WAKEUP, STM32WB_EXTI_PR1); + putreg32(EXTI_RTC_WAKEUP, STM32_EXTI_PR1); return ret; } @@ -81,7 +81,7 @@ static int stm32wb_exti_wakeup_isr(int irq, void *context, void *arg) ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_exti_wakeup + * Name: stm32_exti_wakeup * * Description: * Sets/clears EXTI wakeup interrupt. @@ -97,7 +97,7 @@ static int stm32wb_exti_wakeup_isr(int irq, void *context, void *arg) * ****************************************************************************/ -int stm32wb_exti_wakeup(bool risingedge, bool fallingedge, bool event, +int stm32_exti_wakeup(bool risingedge, bool fallingedge, bool event, xcpt_t func, void *arg) { g_wakeup_callback = func; @@ -107,29 +107,29 @@ int stm32wb_exti_wakeup(bool risingedge, bool fallingedge, bool event, if (func) { - irq_attach(STM32WB_IRQ_RTC_WKUP, stm32wb_exti_wakeup_isr, NULL); - up_enable_irq(STM32WB_IRQ_RTC_WKUP); + irq_attach(STM32_IRQ_RTC_WKUP, stm32_exti_wakeup_isr, NULL); + up_enable_irq(STM32_IRQ_RTC_WKUP); } else { - up_disable_irq(STM32WB_IRQ_RTC_WKUP); + up_disable_irq(STM32_IRQ_RTC_WKUP); } /* Configure rising/falling edges */ - modifyreg32(STM32WB_EXTI_RTSR1, + modifyreg32(STM32_EXTI_RTSR1, risingedge ? 0 : EXTI_RTSR1_RT(EXTI_EVT_RTCWAKEUP), risingedge ? EXTI_RTSR1_RT(EXTI_EVT_RTCWAKEUP) : 0); - modifyreg32(STM32WB_EXTI_FTSR1, + modifyreg32(STM32_EXTI_FTSR1, fallingedge ? 0 : EXTI_FTSR1_FT(EXTI_EVT_RTCWAKEUP), fallingedge ? EXTI_FTSR1_FT(EXTI_EVT_RTCWAKEUP) : 0); /* Enable Events and Interrupts */ - modifyreg32(STM32WB_EXTI_C1EMR1, + modifyreg32(STM32_EXTI_C1EMR1, event ? 0 : EXTI_C1EMR1_EM(EXTI_EVT_RTCWAKEUP), event ? EXTI_C1EMR1_EM(EXTI_EVT_RTCWAKEUP) : 0); - modifyreg32(STM32WB_EXTI_C1IMR1, + modifyreg32(STM32_EXTI_C1IMR1, func ? 0 : EXTI_C1IMR1_IM(EXTI_EVT_RTCWAKEUP), func ? EXTI_C1IMR1_IM(EXTI_EVT_RTCWAKEUP) : 0); diff --git a/arch/arm/src/stm32wb/stm32wb_flash.c b/arch/arm/src/stm32wb/stm32wb_flash.c index 5d151d37c75dc..e3d1b28d1eba3 100644 --- a/arch/arm/src/stm32wb/stm32wb_flash.c +++ b/arch/arm/src/stm32wb/stm32wb_flash.c @@ -45,10 +45,10 @@ #include "arm_internal.h" #include "stm32wb_rcc.h" -#include "stm32wb_waste.h" +#include "stm32_waste.h" #include "stm32wb_flash.h" -#if !defined(CONFIG_STM32WB_FLASH_OVERRIDE_DEFAULT) +#if !defined(CONFIG_STM32_FLASH_OVERRIDE_DEFAULT) # warning "Flash Configuration has been overridden - make sure it is correct" #endif @@ -63,7 +63,7 @@ #define OPTBYTES_KEY1 0x08192a3b #define OPTBYTES_KEY2 0x4c5d6e7f -#define FLASH_PAGE_SIZE STM32WB_FLASH_PAGESIZE +#define FLASH_PAGE_SIZE STM32_FLASH_PAGESIZE #define FLASH_PAGE_WORDS (FLASH_PAGE_SIZE / 4) #define FLASH_PAGE_MASK (FLASH_PAGE_SIZE - 1) #define FLASH_PAGE_SHIFT (12) /* 2**12 = 4096B */ @@ -91,35 +91,35 @@ static uint32_t g_page_buffer[FLASH_PAGE_WORDS]; static void flash_unlock(void) { - while (getreg32(STM32WB_FLASH_SR) & FLASH_SR_BSY) + while (getreg32(STM32_FLASH_SR) & FLASH_SR_BSY) { - stm32wb_waste(); + stm32_waste(); } - if (getreg32(STM32WB_FLASH_CR) & FLASH_CR_LOCK) + if (getreg32(STM32_FLASH_CR) & FLASH_CR_LOCK) { /* Unlock sequence */ - putreg32(FLASH_KEY1, STM32WB_FLASH_KEYR); - putreg32(FLASH_KEY2, STM32WB_FLASH_KEYR); + putreg32(FLASH_KEY1, STM32_FLASH_KEYR); + putreg32(FLASH_KEY2, STM32_FLASH_KEYR); } } static void flash_lock(void) { - modifyreg32(STM32WB_FLASH_CR, 0, FLASH_CR_LOCK); + modifyreg32(STM32_FLASH_CR, 0, FLASH_CR_LOCK); } static void flash_optbytes_unlock(void) { flash_unlock(); - if (getreg32(STM32WB_FLASH_CR) & FLASH_CR_OPTLOCK) + if (getreg32(STM32_FLASH_CR) & FLASH_CR_OPTLOCK) { /* Unlock Option Bytes sequence */ - putreg32(OPTBYTES_KEY1, STM32WB_FLASH_OPTKEYR); - putreg32(OPTBYTES_KEY2, STM32WB_FLASH_OPTKEYR); + putreg32(OPTBYTES_KEY1, STM32_FLASH_OPTKEYR); + putreg32(OPTBYTES_KEY2, STM32_FLASH_OPTKEYR); } } @@ -136,24 +136,24 @@ static inline void flash_erase(size_t page) { finfo("erase page %u\n", page); - modifyreg32(STM32WB_FLASH_CR, 0, FLASH_CR_PAGE_ERASE); - modifyreg32(STM32WB_FLASH_CR, FLASH_CR_PNB_MASK, + modifyreg32(STM32_FLASH_CR, 0, FLASH_CR_PAGE_ERASE); + modifyreg32(STM32_FLASH_CR, FLASH_CR_PNB_MASK, FLASH_CR_PNB(page & 0xff)); - modifyreg32(STM32WB_FLASH_CR, 0, FLASH_CR_STRT); + modifyreg32(STM32_FLASH_CR, 0, FLASH_CR_STRT); - while (getreg32(STM32WB_FLASH_SR) & FLASH_SR_BSY) + while (getreg32(STM32_FLASH_SR) & FLASH_SR_BSY) { - stm32wb_waste(); + stm32_waste(); } - modifyreg32(STM32WB_FLASH_CR, FLASH_CR_PAGE_ERASE, 0); + modifyreg32(STM32_FLASH_CR, FLASH_CR_PAGE_ERASE, 0); } /**************************************************************************** * Public Functions ****************************************************************************/ -int stm32wb_flash_unlock(void) +int stm32_flash_unlock(void) { int ret; @@ -169,7 +169,7 @@ int stm32wb_flash_unlock(void) return ret; } -int stm32wb_flash_lock(void) +int stm32_flash_lock(void) { int ret; @@ -186,7 +186,7 @@ int stm32wb_flash_lock(void) } /**************************************************************************** - * Name: stm32wb_flash_user_optbytes + * Name: stm32_flash_user_optbytes * * Description: * Modify the contents of the user option bytes (USR OPT) on the flash. @@ -202,7 +202,7 @@ int stm32wb_flash_lock(void) * ****************************************************************************/ -uint32_t stm32wb_flash_user_optbytes(uint32_t clrbits, uint32_t setbits) +uint32_t stm32_flash_user_optbytes(uint32_t clrbits, uint32_t setbits) { uint32_t regval; int ret; @@ -225,22 +225,22 @@ uint32_t stm32wb_flash_user_optbytes(uint32_t clrbits, uint32_t setbits) /* Modify Option Bytes in register. */ - regval = getreg32(STM32WB_FLASH_OPTR); + regval = getreg32(STM32_FLASH_OPTR); finfo("Flash option bytes before: 0x%" PRIx32 "\n", regval); regval = (regval & ~clrbits) | setbits; - putreg32(regval, STM32WB_FLASH_OPTR); + putreg32(regval, STM32_FLASH_OPTR); finfo("Flash option bytes after: 0x%" PRIx32 "\n", regval); /* Start Option Bytes programming and wait for completion. */ - modifyreg32(STM32WB_FLASH_CR, 0, FLASH_CR_OPTSTRT); + modifyreg32(STM32_FLASH_CR, 0, FLASH_CR_OPTSTRT); - while (getreg32(STM32WB_FLASH_SR) & FLASH_SR_BSY) + while (getreg32(STM32_FLASH_SR) & FLASH_SR_BSY) { - stm32wb_waste(); + stm32_waste(); } flash_optbytes_lock(); @@ -251,42 +251,42 @@ uint32_t stm32wb_flash_user_optbytes(uint32_t clrbits, uint32_t setbits) size_t up_progmem_pagesize(size_t page) { - return STM32WB_FLASH_PAGESIZE; + return STM32_FLASH_PAGESIZE; } size_t up_progmem_erasesize(size_t block) { - return STM32WB_FLASH_PAGESIZE; + return STM32_FLASH_PAGESIZE; } ssize_t up_progmem_getpage(size_t addr) { - if (addr >= STM32WB_FLASH_BASE) + if (addr >= STM32_FLASH_BASE) { - addr -= STM32WB_FLASH_BASE; + addr -= STM32_FLASH_BASE; } - if (addr >= STM32WB_FLASH_SIZE) + if (addr >= STM32_FLASH_SIZE) { return -EFAULT; } - return addr / STM32WB_FLASH_PAGESIZE; + return addr / STM32_FLASH_PAGESIZE; } size_t up_progmem_getaddress(size_t page) { - if (page >= STM32WB_FLASH_NPAGES) + if (page >= STM32_FLASH_NPAGES) { return SIZE_MAX; } - return page * STM32WB_FLASH_PAGESIZE + STM32WB_FLASH_BASE; + return page * STM32_FLASH_PAGESIZE + STM32_FLASH_BASE; } size_t up_progmem_neraseblocks(void) { - return STM32WB_FLASH_NPAGES; + return STM32_FLASH_NPAGES; } bool up_progmem_isuniform(void) @@ -298,7 +298,7 @@ ssize_t up_progmem_eraseblock(size_t block) { int ret; - if (block >= STM32WB_FLASH_NPAGES) + if (block >= STM32_FLASH_NPAGES) { return -EFAULT; } @@ -336,7 +336,7 @@ ssize_t up_progmem_ispageerased(size_t page) size_t count; size_t bwritten = 0; - if (page >= STM32WB_FLASH_NPAGES) + if (page >= STM32_FLASH_NPAGES) { return -EFAULT; } @@ -369,12 +369,12 @@ ssize_t up_progmem_write(size_t addr, const void *buf, size_t buflen) /* Check for valid address range. */ offset = addr; - if (addr >= STM32WB_FLASH_BASE) + if (addr >= STM32_FLASH_BASE) { - offset -= STM32WB_FLASH_BASE; + offset -= STM32_FLASH_BASE; } - if (offset + buflen > STM32WB_FLASH_SIZE) + if (offset + buflen > STM32_FLASH_SIZE) { return -EFAULT; } @@ -444,23 +444,23 @@ ssize_t up_progmem_write(size_t addr, const void *buf, size_t buflen) /* Write the page. Must be with double-words. */ - modifyreg32(STM32WB_FLASH_CR, 0, FLASH_CR_PG); + modifyreg32(STM32_FLASH_CR, 0, FLASH_CR_PG); for (i = 0; i < FLASH_PAGE_WORDS; i += 2) { *dest++ = *src++; *dest++ = *src++; - while (getreg32(STM32WB_FLASH_SR) & FLASH_SR_BSY) + while (getreg32(STM32_FLASH_SR) & FLASH_SR_BSY) { - stm32wb_waste(); + stm32_waste(); } /* Verify */ - if (getreg32(STM32WB_FLASH_SR) & FLASH_SR_WRITE_PROTECTION_ERROR) + if (getreg32(STM32_FLASH_SR) & FLASH_SR_WRITE_PROTECTION_ERROR) { - modifyreg32(STM32WB_FLASH_CR, FLASH_CR_PG, 0); + modifyreg32(STM32_FLASH_CR, FLASH_CR_PG, 0); ret = -EROFS; goto out; } @@ -468,13 +468,13 @@ ssize_t up_progmem_write(size_t addr, const void *buf, size_t buflen) if (getreg32(dest - 1) != *(src - 1) || getreg32(dest - 2) != *(src - 2)) { - modifyreg32(STM32WB_FLASH_CR, FLASH_CR_PG, 0); + modifyreg32(STM32_FLASH_CR, FLASH_CR_PG, 0); ret = -EIO; goto out; } } - modifyreg32(STM32WB_FLASH_CR, FLASH_CR_PG, 0); + modifyreg32(STM32_FLASH_CR, FLASH_CR_PG, 0); /* Adjust pointers and counts for the next time through the loop */ @@ -494,9 +494,9 @@ ssize_t up_progmem_write(size_t addr, const void *buf, size_t buflen) if (ret != OK) { ferr("flash write error: %d, status: 0x%" PRIx32 "\n", - ret, getreg32(STM32WB_FLASH_SR)); + ret, getreg32(STM32_FLASH_SR)); - modifyreg32(STM32WB_FLASH_SR, 0, FLASH_SR_ALLERRS); + modifyreg32(STM32_FLASH_SR, 0, FLASH_SR_ALLERRS); } flash_lock(); diff --git a/arch/arm/src/stm32wb/stm32wb_flash.h b/arch/arm/src/stm32wb/stm32wb_flash.h index 36077d8b0f85c..72bf966904fdc 100644 --- a/arch/arm/src/stm32wb/stm32wb_flash.h +++ b/arch/arm/src/stm32wb/stm32wb_flash.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32WB_STM32WB_FLASH_H -#define __ARCH_ARM_SRC_STM32WB_STM32WB_FLASH_H +#ifndef __ARCH_ARM_SRC_STM32WB_STM32_FLASH_H +#define __ARCH_ARM_SRC_STM32WB_STM32_FLASH_H /**************************************************************************** * Included Files @@ -35,11 +35,11 @@ * Public Function Prototypes ****************************************************************************/ -int stm32wb_flash_lock(void); -int stm32wb_flash_unlock(void); +int stm32_flash_lock(void); +int stm32_flash_unlock(void); /**************************************************************************** - * Name: stm32wb_flash_user_optbytes + * Name: stm32_flash_user_optbytes * * Description: * Modify the contents of the user option bytes (USR OPT) on the flash. @@ -55,6 +55,6 @@ int stm32wb_flash_unlock(void); * ****************************************************************************/ -uint32_t stm32wb_flash_user_optbytes(uint32_t clrbits, uint32_t setbits); +uint32_t stm32_flash_user_optbytes(uint32_t clrbits, uint32_t setbits); -#endif /* __ARCH_ARM_SRC_STM32WB_STM32WB_FLASH_H */ +#endif /* __ARCH_ARM_SRC_STM32WB_STM32_FLASH_H */ diff --git a/arch/arm/src/stm32wb/stm32wb_freerun.c b/arch/arm/src/stm32wb/stm32wb_freerun.c index a4168046aa411..c308a611db3c9 100644 --- a/arch/arm/src/stm32wb/stm32wb_freerun.c +++ b/arch/arm/src/stm32wb/stm32wb_freerun.c @@ -37,14 +37,14 @@ #include "stm32wb_freerun.h" -#ifdef CONFIG_STM32WB_FREERUN +#ifdef CONFIG_STM32_FREERUN /**************************************************************************** * Private Functions ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_freerun_handler + * Name: stm32_freerun_handler * * Description: * Timer interrupt callback. When the freerun timer counter overflows, @@ -62,14 +62,14 @@ ****************************************************************************/ #ifndef CONFIG_CLOCK_TIMEKEEPING -static int stm32wb_freerun_handler(int irq, void *context, void *arg) +static int stm32_freerun_handler(int irq, void *context, void *arg) { - struct stm32wb_freerun_s *freerun = (struct stm32wb_freerun_s *)arg; + struct stm32_freerun_s *freerun = (struct stm32_freerun_s *)arg; DEBUGASSERT(freerun != NULL && freerun->overflow < UINT32_MAX); freerun->overflow++; - STM32WB_TIM_ACKINT(freerun->tch, GTIM_SR_UIF); + STM32_TIM_ACKINT(freerun->tch, GTIM_SR_UIF); return OK; } #endif /* CONFIG_CLOCK_TIMEKEEPING */ @@ -79,7 +79,7 @@ static int stm32wb_freerun_handler(int irq, void *context, void *arg) ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_freerun_initialize + * Name: stm32_freerun_initialize * * Description: * Initialize the freerun timer wrapper @@ -97,7 +97,7 @@ static int stm32wb_freerun_handler(int irq, void *context, void *arg) * ****************************************************************************/ -int stm32wb_freerun_initialize(struct stm32wb_freerun_s *freerun, int chan, +int stm32_freerun_initialize(struct stm32_freerun_s *freerun, int chan, uint16_t resolution) { uint32_t frequency; @@ -110,21 +110,21 @@ int stm32wb_freerun_initialize(struct stm32wb_freerun_s *freerun, int chan, frequency = USEC_PER_SEC / (uint32_t)resolution; freerun->frequency = frequency; - freerun->tch = stm32wb_tim_init(chan); + freerun->tch = stm32_tim_init(chan); if (!freerun->tch) { tmrerr("ERROR: Failed to allocate TIM%d\n", chan); return -EBUSY; } - STM32WB_TIM_SETCLOCK(freerun->tch, frequency); + STM32_TIM_SETCLOCK(freerun->tch, frequency); /* Initialize the remaining fields in the state structure and return * success. */ freerun->chan = chan; - freerun->width = STM32WB_TIM_GETWIDTH(freerun->tch); + freerun->width = STM32_TIM_GETWIDTH(freerun->tch); #ifdef CONFIG_CLOCK_TIMEKEEPING freerun->counter_mask = 0xffffffff; @@ -135,28 +135,28 @@ int stm32wb_freerun_initialize(struct stm32wb_freerun_s *freerun, int chan, /* Set up to receive the callback when the counter overflow occurs */ - STM32WB_TIM_SETISR(freerun->tch, stm32wb_freerun_handler, freerun, 0); + STM32_TIM_SETISR(freerun->tch, stm32_freerun_handler, freerun, 0); #endif /* Set timer period */ - STM32WB_TIM_SETPERIOD(freerun->tch, + STM32_TIM_SETPERIOD(freerun->tch, (uint32_t)((1ull << freerun->width) - 1)); /* Start the counter */ - STM32WB_TIM_SETMODE(freerun->tch, STM32WB_TIM_MODE_UP); + STM32_TIM_SETMODE(freerun->tch, STM32_TIM_MODE_UP); #ifndef CONFIG_CLOCK_TIMEKEEPING - STM32WB_TIM_ACKINT(freerun->tch, GTIM_SR_UIF); - STM32WB_TIM_ENABLEINT(freerun->tch, GTIM_DIER_UIE); + STM32_TIM_ACKINT(freerun->tch, GTIM_SR_UIF); + STM32_TIM_ENABLEINT(freerun->tch, GTIM_DIER_UIE); #endif return OK; } /**************************************************************************** - * Name: stm32wb_freerun_counter + * Name: stm32_freerun_counter * * Description: * Read the counter register of the free-running timer. @@ -164,7 +164,7 @@ int stm32wb_freerun_initialize(struct stm32wb_freerun_s *freerun, int chan, * Input Parameters: * freerun Caller allocated instance of the freerun state structure. This * structure must have been previously initialized via a call to - * stm32wb_freerun_initialize(); + * stm32_freerun_initialize(); * ts The location in which to return the time from the free-running * timer. * @@ -176,7 +176,7 @@ int stm32wb_freerun_initialize(struct stm32wb_freerun_s *freerun, int chan, #ifndef CONFIG_CLOCK_TIMEKEEPING -int stm32wb_freerun_counter(struct stm32wb_freerun_s *freerun, +int stm32_freerun_counter(struct stm32_freerun_s *freerun, struct timespec *ts) { uint64_t usec; @@ -190,7 +190,7 @@ int stm32wb_freerun_counter(struct stm32wb_freerun_s *freerun, DEBUGASSERT(freerun && freerun->tch && ts); /* Temporarily disable the overflow counter. NOTE that we have to be - * careful here because stm32wb_tc_getpending() will reset the pending + * careful here because stm32_tc_getpending() will reset the pending * interrupt status. If we do not handle the overflow here then, it will * be lost. */ @@ -198,9 +198,9 @@ int stm32wb_freerun_counter(struct stm32wb_freerun_s *freerun, flags = enter_critical_section(); overflow = freerun->overflow; - counter = STM32WB_TIM_GETCOUNTER(freerun->tch); - pending = STM32WB_TIM_CHECKINT(freerun->tch, 0); - verify = STM32WB_TIM_GETCOUNTER(freerun->tch); + counter = STM32_TIM_GETCOUNTER(freerun->tch); + pending = STM32_TIM_CHECKINT(freerun->tch, 0); + verify = STM32_TIM_GETCOUNTER(freerun->tch); /* If an interrupt was pending before we re-enabled interrupts, * then the overflow needs to be incremented. @@ -208,7 +208,7 @@ int stm32wb_freerun_counter(struct stm32wb_freerun_s *freerun, if (pending) { - STM32WB_TIM_ACKINT(freerun->tch, GTIM_SR_UIF); + STM32_TIM_ACKINT(freerun->tch, GTIM_SR_UIF); /* Increment the overflow count and use the value of the * guaranteed to be AFTER the overflow occurred. @@ -253,17 +253,17 @@ int stm32wb_freerun_counter(struct stm32wb_freerun_s *freerun, #else /* CONFIG_CLOCK_TIMEKEEPING */ -int stm32wb_freerun_counter(struct stm32wb_freerun_s *freerun, +int stm32_freerun_counter(struct stm32_freerun_s *freerun, uint64_t *counter) { - *counter = STM32WB_TIM_GETCOUNTER(freerun->tch); + *counter = STM32_TIM_GETCOUNTER(freerun->tch); return OK; } #endif /* CONFIG_CLOCK_TIMEKEEPING */ /**************************************************************************** - * Name: stm32wb_freerun_uninitialize + * Name: stm32_freerun_uninitialize * * Description: * Stop the free-running timer and release all resources that it uses. @@ -271,7 +271,7 @@ int stm32wb_freerun_counter(struct stm32wb_freerun_s *freerun, * Input Parameters: * freerun Caller allocated instance of the freerun state structure. This * structure must have been previously initialized via a call to - * stm32wb_freerun_initialize(); + * stm32_freerun_initialize(); * * Returned Value: * Zero (OK) is returned on success; a negated errno value is returned @@ -279,22 +279,22 @@ int stm32wb_freerun_counter(struct stm32wb_freerun_s *freerun, * ****************************************************************************/ -int stm32wb_freerun_uninitialize(struct stm32wb_freerun_s *freerun) +int stm32_freerun_uninitialize(struct stm32_freerun_s *freerun) { DEBUGASSERT(freerun && freerun->tch); /* Now we can disable the timer interrupt and disable the timer. */ - STM32WB_TIM_DISABLEINT(freerun->tch, GTIM_DIER_UIE); - STM32WB_TIM_SETMODE(freerun->tch, STM32WB_TIM_MODE_DISABLED); - STM32WB_TIM_SETISR(freerun->tch, NULL, NULL, 0); + STM32_TIM_DISABLEINT(freerun->tch, GTIM_DIER_UIE); + STM32_TIM_SETMODE(freerun->tch, STM32_TIM_MODE_DISABLED); + STM32_TIM_SETISR(freerun->tch, NULL, NULL, 0); /* Free the timer */ - stm32wb_tim_deinit(freerun->tch); + stm32_tim_deinit(freerun->tch); freerun->tch = NULL; return OK; } -#endif /* CONFIG_STM32WB_FREERUN */ +#endif /* CONFIG_STM32_FREERUN */ diff --git a/arch/arm/src/stm32wb/stm32wb_freerun.h b/arch/arm/src/stm32wb/stm32wb_freerun.h index ef95f59c32e5e..ae4dd49ba9c3a 100644 --- a/arch/arm/src/stm32wb/stm32wb_freerun.h +++ b/arch/arm/src/stm32wb/stm32wb_freerun.h @@ -35,24 +35,24 @@ #include "stm32wb_tim.h" -#ifdef CONFIG_STM32WB_FREERUN +#ifdef CONFIG_STM32_FREERUN /**************************************************************************** * Public Types ****************************************************************************/ /* The freerun client must allocate an instance of this structure and called - * stm32wb_freerun_initialize() before using the freerun facilities. The + * stm32_freerun_initialize() before using the freerun facilities. The * client should not access the contents of this structure directly since * the contents are subject to change. */ -struct stm32wb_freerun_s +struct stm32_freerun_s { uint8_t chan; /* The timer/counter in use */ uint8_t width; /* Width of timer (16- or 32-bits) */ - struct stm32wb_tim_dev_s *tch; /* Pointer returned by - * stm32wb_tim_init() */ + struct stm32_tim_dev_s *tch; /* Pointer returned by + * stm32_tim_init() */ uint32_t frequency; #ifndef CONFIG_CLOCK_TIMEKEEPING @@ -82,7 +82,7 @@ extern "C" ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_freerun_initialize + * Name: stm32_freerun_initialize * * Description: * Initialize the freerun timer wrapper @@ -100,11 +100,11 @@ extern "C" * ****************************************************************************/ -int stm32wb_freerun_initialize(struct stm32wb_freerun_s *freerun, int chan, +int stm32_freerun_initialize(struct stm32_freerun_s *freerun, int chan, uint16_t resolution); /**************************************************************************** - * Name: stm32wb_freerun_counter + * Name: stm32_freerun_counter * * Description: * Read the counter register of the free-running timer. @@ -112,7 +112,7 @@ int stm32wb_freerun_initialize(struct stm32wb_freerun_s *freerun, int chan, * Input Parameters: * freerun Caller allocated instance of the freerun state structure. This * structure must have been previously initialized via a call to - * stm32wb_freerun_initialize(); + * stm32_freerun_initialize(); * ts The location in which to return the time remaining on the * oneshot timer. * @@ -124,18 +124,18 @@ int stm32wb_freerun_initialize(struct stm32wb_freerun_s *freerun, int chan, #ifndef CONFIG_CLOCK_TIMEKEEPING -int stm32wb_freerun_counter(struct stm32wb_freerun_s *freerun, +int stm32_freerun_counter(struct stm32_freerun_s *freerun, struct timespec *ts); #else /* CONFIG_CLOCK_TIMEKEEPING */ -int stm32wb_freerun_counter(struct stm32_freerun_s *freerun, +int stm32_freerun_counter(struct stm32_freerun_s *freerun, uint64_t *counter); #endif /* CONFIG_CLOCK_TIMEKEEPING */ /**************************************************************************** - * Name: stm32wb_freerun_uninitialize + * Name: stm32_freerun_uninitialize * * Description: * Stop the free-running timer and release all resources that it uses. @@ -143,7 +143,7 @@ int stm32wb_freerun_counter(struct stm32_freerun_s *freerun, * Input Parameters: * freerun Caller allocated instance of the freerun state structure. This * structure must have been previously initialized via a call to - * stm32wb_freerun_initialize(); + * stm32_freerun_initialize(); * * Returned Value: * Zero (OK) is returned on success; a negated errno value is returned @@ -151,12 +151,12 @@ int stm32wb_freerun_counter(struct stm32_freerun_s *freerun, * ****************************************************************************/ -int stm32wb_freerun_uninitialize(struct stm32wb_freerun_s *freerun); +int stm32_freerun_uninitialize(struct stm32_freerun_s *freerun); #undef EXTERN #ifdef __cplusplus } #endif -#endif /* CONFIG_STM32WB_FREERUN */ +#endif /* CONFIG_STM32_FREERUN */ #endif /* __ARCH_ARM_SRC_STM32WB_STM32WB_FREERUN_H */ diff --git a/arch/arm/src/stm32wb/stm32wb_gpio.c b/arch/arm/src/stm32wb/stm32wb_gpio.c index d857d472a502c..a38e7398b74d2 100644 --- a/arch/arm/src/stm32wb/stm32wb_gpio.c +++ b/arch/arm/src/stm32wb/stm32wb_gpio.c @@ -52,14 +52,14 @@ static spinlock_t g_configgpio_lock = SP_UNLOCKED; /* Base addresses for each GPIO block */ -const uint32_t g_gpiobase[STM32WB_NPORTS] = +const uint32_t g_gpiobase[STM32_NPORTS] = { - STM32WB_GPIOA_BASE, - STM32WB_GPIOB_BASE, - STM32WB_GPIOC_BASE, - STM32WB_GPIOD_BASE, - STM32WB_GPIOE_BASE, - STM32WB_GPIOH_BASE + STM32_GPIOA_BASE, + STM32_GPIOB_BASE, + STM32_GPIOC_BASE, + STM32_GPIOD_BASE, + STM32_GPIOE_BASE, + STM32_GPIOH_BASE }; /**************************************************************************** @@ -71,13 +71,13 @@ const uint32_t g_gpiobase[STM32WB_NPORTS] = ****************************************************************************/ /**************************************************************************** - * Function: stm32wb_gpioinit + * Function: stm32_gpioinit * * Description: * Based on configuration within the .config file, it does: * - Remaps positions of alternative functions. * - * Typically called from stm32wb_start(). + * Typically called from stm32_start(). * * Assumptions: * This function is called early in the initialization sequence so that @@ -85,17 +85,17 @@ const uint32_t g_gpiobase[STM32WB_NPORTS] = * ****************************************************************************/ -void stm32wb_gpioinit(void) +void stm32_gpioinit(void) { } /**************************************************************************** - * Name: stm32wb_configgpio + * Name: stm32_configgpio * * Description: * Configure a GPIO pin based on bit-encoded description of the pin. * Once it is configured as Alternative (GPIO_ALT|GPIO_CNF_AFPP|...) - * function, it must be unconfigured with stm32wb_unconfiggpio() with + * function, it must be unconfigured with stm32_unconfiggpio() with * the same cfgset first before it can be set to non-alternative function. * * Returned Value: @@ -106,7 +106,7 @@ void stm32wb_gpioinit(void) * To-Do: Auto Power Enable ****************************************************************************/ -int stm32wb_configgpio(uint32_t cfgset) +int stm32_configgpio(uint32_t cfgset) { uintptr_t base; uint32_t regval; @@ -119,7 +119,7 @@ int stm32wb_configgpio(uint32_t cfgset) /* Verify that this hardware supports the select GPIO port */ port = (cfgset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; - if (port >= STM32WB_NPORTS) + if (port >= STM32_NPORTS) { return -EINVAL; } @@ -147,7 +147,7 @@ int stm32wb_configgpio(uint32_t cfgset) /* Set the initial output value */ - stm32wb_gpiowrite(cfgset, (cfgset & GPIO_OUTPUT_SET) != 0); + stm32_gpiowrite(cfgset, (cfgset & GPIO_OUTPUT_SET) != 0); pinmode = GPIO_MODER_OUTPUT; break; @@ -168,10 +168,10 @@ int stm32wb_configgpio(uint32_t cfgset) /* Now apply the configuration to the mode register */ - regval = getreg32(base + STM32WB_GPIO_MODER_OFFSET); + regval = getreg32(base + STM32_GPIO_MODER_OFFSET); regval &= ~GPIO_MODER_MASK(pin); regval |= ((uint32_t)pinmode << GPIO_MODER_SHIFT(pin)); - putreg32(regval, base + STM32WB_GPIO_MODER_OFFSET); + putreg32(regval, base + STM32_GPIO_MODER_OFFSET); /* Set up the pull-up/pull-down configuration (all but analog pins) */ @@ -194,10 +194,10 @@ int stm32wb_configgpio(uint32_t cfgset) } } - regval = getreg32(base + STM32WB_GPIO_PUPDR_OFFSET); + regval = getreg32(base + STM32_GPIO_PUPDR_OFFSET); regval &= ~GPIO_PUPDR_MASK(pin); regval |= (setting << GPIO_PUPDR_SHIFT(pin)); - putreg32(regval, base + STM32WB_GPIO_PUPDR_OFFSET); + putreg32(regval, base + STM32_GPIO_PUPDR_OFFSET); /* Set the alternate function (Only alternate function pins) */ @@ -212,17 +212,17 @@ int stm32wb_configgpio(uint32_t cfgset) if (pin < 8) { - regval = getreg32(base + STM32WB_GPIO_AFRL_OFFSET); + regval = getreg32(base + STM32_GPIO_AFRL_OFFSET); regval &= ~GPIO_AFRL_AFSEL_MASK(pin); regval |= (setting << GPIO_AFRL_AFSEL_SHIFT(pin)); - putreg32(regval, base + STM32WB_GPIO_AFRL_OFFSET); + putreg32(regval, base + STM32_GPIO_AFRL_OFFSET); } else { - regval = getreg32(base + STM32WB_GPIO_AFRH_OFFSET); + regval = getreg32(base + STM32_GPIO_AFRH_OFFSET); regval &= ~GPIO_AFRH_AFSEL_MASK(pin); regval |= (setting << GPIO_AFRH_AFSEL_SHIFT(pin)); - putreg32(regval, base + STM32WB_GPIO_AFRH_OFFSET); + putreg32(regval, base + STM32_GPIO_AFRH_OFFSET); } /* Set speed (Only outputs and alternate function pins) */ @@ -254,14 +254,14 @@ int stm32wb_configgpio(uint32_t cfgset) setting = 0; } - regval = getreg32(base + STM32WB_GPIO_OSPEED_OFFSET); + regval = getreg32(base + STM32_GPIO_OSPEED_OFFSET); regval &= ~GPIO_OSPEED_MASK(pin); regval |= (setting << GPIO_OSPEED_SHIFT(pin)); - putreg32(regval, base + STM32WB_GPIO_OSPEED_OFFSET); + putreg32(regval, base + STM32_GPIO_OSPEED_OFFSET); /* Set push-pull/open-drain (Only outputs and alternate function pins) */ - regval = getreg32(base + STM32WB_GPIO_OTYPER_OFFSET); + regval = getreg32(base + STM32_GPIO_OTYPER_OFFSET); setting = GPIO_OTYPER_OD(pin); if ((pinmode == GPIO_MODER_OUTPUT || pinmode == GPIO_MODER_ALT) && @@ -274,7 +274,7 @@ int stm32wb_configgpio(uint32_t cfgset) regval &= ~setting; } - putreg32(regval, base + STM32WB_GPIO_OTYPER_OFFSET); + putreg32(regval, base + STM32_GPIO_OTYPER_OFFSET); /* Otherwise, it is an input pin. Should it configured as an * EXTI interrupt? @@ -291,7 +291,7 @@ int stm32wb_configgpio(uint32_t cfgset) /* Set the bits in the SYSCFG EXTICR register */ - regaddr = STM32WB_SYSCFG_EXTICR(pin); + regaddr = STM32_SYSCFG_EXTICR(pin); regval = getreg32(regaddr); shift = SYSCFG_EXTICR_EXTI_SHIFT(pin); regval &= ~(SYSCFG_EXTICR_PORT_MASK << shift); @@ -305,7 +305,7 @@ int stm32wb_configgpio(uint32_t cfgset) } /**************************************************************************** - * Name: stm32wb_unconfiggpio + * Name: stm32_unconfiggpio * * Description: * Unconfigure a GPIO pin based on bit-encoded description of the pin, set @@ -325,7 +325,7 @@ int stm32wb_configgpio(uint32_t cfgset) * To-Do: Auto Power Disable ****************************************************************************/ -int stm32wb_unconfiggpio(uint32_t cfgset) +int stm32_unconfiggpio(uint32_t cfgset) { /* Reuse port and pin number and set it to default HiZ INPUT */ @@ -334,18 +334,18 @@ int stm32wb_unconfiggpio(uint32_t cfgset) /* To-Do: Mark its unuse for automatic power saving options */ - return stm32wb_configgpio(cfgset); + return stm32_configgpio(cfgset); } /**************************************************************************** - * Name: stm32wb_gpiowrite + * Name: stm32_gpiowrite * * Description: * Write one or zero to the selected GPIO pin * ****************************************************************************/ -void stm32wb_gpiowrite(uint32_t pinset, bool value) +void stm32_gpiowrite(uint32_t pinset, bool value) { uint32_t base; uint32_t bit; @@ -353,7 +353,7 @@ void stm32wb_gpiowrite(uint32_t pinset, bool value) unsigned int pin; port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; - if (port < STM32WB_NPORTS) + if (port < STM32_NPORTS) { /* Get the port base address */ @@ -374,26 +374,26 @@ void stm32wb_gpiowrite(uint32_t pinset, bool value) bit = GPIO_BSRR_RESET(pin); } - putreg32(bit, base + STM32WB_GPIO_BSRR_OFFSET); + putreg32(bit, base + STM32_GPIO_BSRR_OFFSET); } } /**************************************************************************** - * Name: stm32wb_gpioread + * Name: stm32_gpioread * * Description: * Read one or zero from the selected GPIO pin * ****************************************************************************/ -bool stm32wb_gpioread(uint32_t pinset) +bool stm32_gpioread(uint32_t pinset) { uint32_t base; unsigned int port; unsigned int pin; port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; - if (port < STM32WB_NPORTS) + if (port < STM32_NPORTS) { /* Get the port base address */ @@ -402,7 +402,7 @@ bool stm32wb_gpioread(uint32_t pinset) /* Get the pin number and return the input state of that pin */ pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT; - return ((getreg32(base + STM32WB_GPIO_IDR_OFFSET) & (1 << pin)) != 0); + return ((getreg32(base + STM32_GPIO_IDR_OFFSET) & (1 << pin)) != 0); } return 0; diff --git a/arch/arm/src/stm32wb/stm32wb_gpio.h b/arch/arm/src/stm32wb/stm32wb_gpio.h index befb722c0eeb6..f388d935afeb0 100644 --- a/arch/arm/src/stm32wb/stm32wb_gpio.h +++ b/arch/arm/src/stm32wb/stm32wb_gpio.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32WB_STM32WB_GPIO_H -#define __ARCH_ARM_SRC_STM32WB_STM32WB_GPIO_H +#ifndef __ARCH_ARM_SRC_STM32WB_STM32_GPIO_H +#define __ARCH_ARM_SRC_STM32WB_STM32_GPIO_H /**************************************************************************** * Included Files @@ -44,15 +44,15 @@ * Pre-Processor Declarations ****************************************************************************/ -#if defined(CONFIG_STM32WB_GPIO_HAVE_PORTD) && defined(CONFIG_STM32WB_GPIO_HAVE_PORTE) -# define STM32WB_NPORTS 6 -#elif defined(CONFIG_STM32WB_GPIO_HAVE_PORTE) -# define STM32WB_NPORTS 5 +#if defined(CONFIG_STM32_GPIO_HAVE_PORTD) && defined(CONFIG_STM32_GPIO_HAVE_PORTE) +# define STM32_NPORTS 6 +#elif defined(CONFIG_STM32_GPIO_HAVE_PORTE) +# define STM32_NPORTS 5 #else -# define STM32WB_NPORTS 4 +# define STM32_NPORTS 4 #endif -/* Bit-encoded input to stm32wb_configgpio() */ +/* Bit-encoded input to stm32_configgpio() */ /* Each port bit of the general-purpose I/O (GPIO) ports can be individually * configured by software in several modes: @@ -195,11 +195,11 @@ # define GPIO_PORTA (0 << GPIO_PORT_SHIFT) /* GPIOA */ # define GPIO_PORTB (1 << GPIO_PORT_SHIFT) /* GPIOB */ # define GPIO_PORTC (2 << GPIO_PORT_SHIFT) /* GPIOC */ -#if defined(CONFIG_STM32WB_GPIO_HAVE_PORTD) && defined(CONFIG_STM32WB_GPIO_HAVE_PORTE) +#if defined(CONFIG_STM32_GPIO_HAVE_PORTD) && defined(CONFIG_STM32_GPIO_HAVE_PORTE) # define GPIO_PORTD (3 << GPIO_PORT_SHIFT) /* GPIOD */ # define GPIO_PORTE (4 << GPIO_PORT_SHIFT) /* GPIOE */ # define GPIO_PORTH (5 << GPIO_PORT_SHIFT) /* GPIOH */ -#elif defined(CONFIG_STM32WB_GPIO_HAVE_PORTE) +#elif defined(CONFIG_STM32_GPIO_HAVE_PORTE) # define GPIO_PORTE (3 << GPIO_PORT_SHIFT) /* GPIOE */ # define GPIO_PORTH (4 << GPIO_PORT_SHIFT) /* GPIOH */ #else @@ -250,19 +250,19 @@ extern "C" /* Base addresses for each GPIO block */ -EXTERN const uint32_t g_gpiobase[STM32WB_NPORTS]; +EXTERN const uint32_t g_gpiobase[STM32_NPORTS]; /**************************************************************************** * Public Function Prototypes ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_configgpio + * Name: stm32_configgpio * * Description: * Configure a GPIO pin based on bit-encoded description of the pin. * Once it is configured as Alternative (GPIO_ALT|GPIO_CNF_AFPP|...) - * function, it must be unconfigured with stm32wb_unconfiggpio() with + * function, it must be unconfigured with stm32_unconfiggpio() with * the same cfgset first before it can be set to non-alternative function. * * Returned Value: @@ -271,10 +271,10 @@ EXTERN const uint32_t g_gpiobase[STM32WB_NPORTS]; * ****************************************************************************/ -int stm32wb_configgpio(uint32_t cfgset); +int stm32_configgpio(uint32_t cfgset); /**************************************************************************** - * Name: stm32wb_unconfiggpio + * Name: stm32_unconfiggpio * * Description: * Unconfigure a GPIO pin based on bit-encoded description of the pin, set @@ -293,30 +293,30 @@ int stm32wb_configgpio(uint32_t cfgset); * ****************************************************************************/ -int stm32wb_unconfiggpio(uint32_t cfgset); +int stm32_unconfiggpio(uint32_t cfgset); /**************************************************************************** - * Name: stm32wb_gpiowrite + * Name: stm32_gpiowrite * * Description: * Write one or zero to the selected GPIO pin * ****************************************************************************/ -void stm32wb_gpiowrite(uint32_t pinset, bool value); +void stm32_gpiowrite(uint32_t pinset, bool value); /**************************************************************************** - * Name: stm32wb_gpioread + * Name: stm32_gpioread * * Description: * Read one or zero from the selected GPIO pin * ****************************************************************************/ -bool stm32wb_gpioread(uint32_t pinset); +bool stm32_gpioread(uint32_t pinset); /**************************************************************************** - * Name: stm32wb_gpiosetevent + * Name: stm32_gpiosetevent * * Description: * Sets/clears GPIO based event and interrupt triggers. @@ -335,11 +335,11 @@ bool stm32wb_gpioread(uint32_t pinset); * ****************************************************************************/ -int stm32wb_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, +int stm32_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, bool event, xcpt_t func, void *arg); /**************************************************************************** - * Function: stm32wb_dumpgpio + * Function: stm32_dumpgpio * * Description: * Dump all GPIO registers associated with the provided base address @@ -347,23 +347,23 @@ int stm32wb_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, ****************************************************************************/ #ifdef CONFIG_DEBUG_FEATURES -int stm32wb_dumpgpio(uint32_t pinset, const char *msg); +int stm32_dumpgpio(uint32_t pinset, const char *msg); #else -# define stm32wb_dumpgpio(p,m) +# define stm32_dumpgpio(p,m) #endif /**************************************************************************** - * Function: stm32wb_gpioinit + * Function: stm32_gpioinit * * Description: * Based on configuration within the .config file, it does: * - Remaps positions of alternative functions. * - * Typically called from stm32wb_start(). + * Typically called from stm32_start(). * ****************************************************************************/ -void stm32wb_gpioinit(void); +void stm32_gpioinit(void); #undef EXTERN #if defined(__cplusplus) @@ -371,4 +371,4 @@ void stm32wb_gpioinit(void); #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32WB_STM32WB_GPIO_H */ +#endif /* __ARCH_ARM_SRC_STM32WB_STM32_GPIO_H */ diff --git a/arch/arm/src/stm32wb/stm32wb_i2c.c b/arch/arm/src/stm32wb/stm32wb_i2c.c index 3d7d6b8db1911..e2c67abe444af 100644 --- a/arch/arm/src/stm32wb/stm32wb_i2c.c +++ b/arch/arm/src/stm32wb/stm32wb_i2c.c @@ -32,7 +32,7 @@ * Standard-mode (up to 100 kHz) * Fast-mode (up to 400 kHz) * Fast-mode+ (up to 1 MHz) - * Clock source selection is based on STM32WB_RCC_CCIPR register + * Clock source selection is based on STM32_RCC_CCIPR register * * - Multiple instances (shared bus) * - Interrupt based operation @@ -111,26 +111,26 @@ * * To use this driver, enable the following configuration variable: * - * CONFIG_STM32WB_I2C + * CONFIG_STM32_I2C * * and one or more interfaces: * - * CONFIG_STM32WB_I2C1 - * CONFIG_STM32WB_I2C3 + * CONFIG_STM32_I2C1 + * CONFIG_STM32_I2C3 * * To configure the ISR timeout using fixed values - * (CONFIG_STM32WB_I2C_DYNTIMEO=n): + * (CONFIG_STM32_I2C_DYNTIMEO=n): * - * CONFIG_STM32WB_I2CTIMEOSEC (Timeout in seconds) - * CONFIG_STM32WB_I2CTIMEOMS (Timeout in milliseconds) - * CONFIG_STM32WB_I2CTIMEOTICKS (Timeout in ticks) + * CONFIG_STM32_I2CTIMEOSEC (Timeout in seconds) + * CONFIG_STM32_I2CTIMEOMS (Timeout in milliseconds) + * CONFIG_STM32_I2CTIMEOTICKS (Timeout in ticks) * * To configure the ISR timeout using dynamic values - * (CONFIG_STM32WB_I2C_DYNTIMEO=y): + * (CONFIG_STM32_I2C_DYNTIMEO=y): * - * CONFIG_STM32WB_I2C_DYNTIMEO_USECPERBYTE + * CONFIG_STM32_I2C_DYNTIMEO_USECPERBYTE * (Timeout in microseconds per byte) - * CONFIG_STM32WB_I2C_DYNTIMEO_STARTSTOP + * CONFIG_STM32_I2C_DYNTIMEO_STARTSTOP * (Timeout for start/stop in milliseconds) * * Debugging output enabled with: @@ -186,11 +186,11 @@ #include "stm32wb_gpio.h" #include "stm32wb_rcc.h" #include "stm32wb_i2c.h" -#include "stm32wb_waste.h" +#include "stm32_waste.h" /* At least one I2C peripheral must be enabled */ -#if defined(CONFIG_STM32WB_I2C1) || defined(CONFIG_STM32WB_I2C3) +#if defined(CONFIG_STM32_I2C1) || defined(CONFIG_STM32_I2C3) /**************************************************************************** * Pre-processor Definitions @@ -202,25 +202,25 @@ /* Interrupt wait timeout in seconds and milliseconds */ -#if !defined(CONFIG_STM32WB_I2CTIMEOSEC) && !defined(CONFIG_STM32WB_I2CTIMEOMS) -# define CONFIG_STM32WB_I2CTIMEOSEC 0 -# define CONFIG_STM32WB_I2CTIMEOMS 500 /* Default is 500 milliseconds */ +#if !defined(CONFIG_STM32_I2CTIMEOSEC) && !defined(CONFIG_STM32_I2CTIMEOMS) +# define CONFIG_STM32_I2CTIMEOSEC 0 +# define CONFIG_STM32_I2CTIMEOMS 500 /* Default is 500 milliseconds */ # warning "Using Default 500 Ms Timeout" -#elif !defined(CONFIG_STM32WB_I2CTIMEOSEC) -# define CONFIG_STM32WB_I2CTIMEOSEC 0 /* User provided milliseconds */ -#elif !defined(CONFIG_STM32WB_I2CTIMEOMS) -# define CONFIG_STM32WB_I2CTIMEOMS 0 /* User provided seconds */ +#elif !defined(CONFIG_STM32_I2CTIMEOSEC) +# define CONFIG_STM32_I2CTIMEOSEC 0 /* User provided milliseconds */ +#elif !defined(CONFIG_STM32_I2CTIMEOMS) +# define CONFIG_STM32_I2CTIMEOMS 0 /* User provided seconds */ #endif /* Interrupt wait time timeout in system timer ticks */ -#ifndef CONFIG_STM32WB_I2CTIMEOTICKS -# define CONFIG_STM32WB_I2CTIMEOTICKS \ - (SEC2TICK(CONFIG_STM32WB_I2CTIMEOSEC) + MSEC2TICK(CONFIG_STM32WB_I2CTIMEOMS)) +#ifndef CONFIG_STM32_I2CTIMEOTICKS +# define CONFIG_STM32_I2CTIMEOTICKS \ + (SEC2TICK(CONFIG_STM32_I2CTIMEOSEC) + MSEC2TICK(CONFIG_STM32_I2CTIMEOMS)) #endif -#ifndef CONFIG_STM32WB_I2C_DYNTIMEO_STARTSTOP -# define CONFIG_STM32WB_I2C_DYNTIMEO_STARTSTOP TICK2USEC(CONFIG_STM32WB_I2CTIMEOTICKS) +#ifndef CONFIG_STM32_I2C_DYNTIMEO_STARTSTOP +# define CONFIG_STM32_I2C_DYNTIMEO_STARTSTOP TICK2USEC(CONFIG_STM32_I2CTIMEOTICKS) #endif /* Macros to convert an I2C pin to a GPIO output */ @@ -245,10 +245,10 @@ */ #ifndef CONFIG_I2C_TRACE -# define stm32wb_i2c_tracereset(p) -# define stm32wb_i2c_tracenew(p,s) -# define stm32wb_i2c_traceevent(p,e,a) -# define stm32wb_i2c_tracedump(p) +# define stm32_i2c_tracereset(p) +# define stm32_i2c_tracenew(p,s) +# define stm32_i2c_traceevent(p,e,a) +# define stm32_i2c_tracedump(p) #endif #ifndef CONFIG_I2C_NTRACE @@ -261,7 +261,7 @@ /* Interrupt state */ -enum stm32wb_intstate_e +enum stm32_intstate_e { INTSTATE_IDLE = 0, /* No I2C activity */ INTSTATE_WAITING, /* Waiting for completion of interrupt activity */ @@ -270,7 +270,7 @@ enum stm32wb_intstate_e /* Trace events */ -enum stm32wb_trace_e +enum stm32_trace_e { I2CEVENT_NONE = 0, I2CEVENT_STATE_ERROR, @@ -293,18 +293,18 @@ enum stm32wb_trace_e /* Trace data */ -struct stm32wb_trace_s +struct stm32_trace_s { uint32_t status; /* I2C 32-bit SR2|SR1 status */ uint32_t count; /* Interrupt count when status change */ - enum stm32wb_intstate_e event; /* Last event that occurred with this status */ + enum stm32_intstate_e event; /* Last event that occurred with status */ uint32_t parm; /* Parameter associated with the event */ clock_t time; /* First of event or first status */ }; /* I2C Device hardware configuration */ -struct stm32wb_i2c_config_s +struct stm32_i2c_config_s { uint32_t base; /* I2C base address */ uint32_t clk_bit; /* Clock enable bit */ @@ -319,18 +319,18 @@ struct stm32wb_i2c_config_s /* I2C Device Private Data */ -struct stm32wb_i2c_priv_s +struct stm32_i2c_priv_s { /* Port configuration */ - const struct stm32wb_i2c_config_s *config; + const struct stm32_i2c_config_s *config; int refs; /* Reference count */ mutex_t lock; /* Mutual exclusion mutex */ #ifndef CONFIG_I2C_POLLED sem_t sem_isr; /* Interrupt wait semaphore */ #endif - volatile uint8_t intstate; /* Interrupt handshake (see enum stm32wb_intstate_e) */ + volatile uint8_t intstate; /* Interrupt handshake (see enum stm32_intstate_e) */ uint8_t msgc; /* Message count */ struct i2c_msg_s *msgv; /* Message list */ @@ -348,7 +348,7 @@ struct stm32wb_i2c_priv_s /* The actual trace data */ - struct stm32wb_trace_s trace[CONFIG_I2C_NTRACE]; + struct stm32_trace_s trace[CONFIG_I2C_NTRACE]; #endif uint32_t status; /* End of transfer SR2|SR1 status */ @@ -360,10 +360,10 @@ struct stm32wb_i2c_priv_s /* I2C Device, Instance */ -struct stm32wb_i2c_inst_s +struct stm32_i2c_inst_s { - const struct i2c_ops_s *ops; /* Standard I2C operations */ - struct stm32wb_i2c_priv_s *priv; /* Common driver private data structure */ + const struct i2c_ops_s *ops; /* Standard I2C operations */ + struct stm32_i2c_priv_s *priv; /* Common driver private data structure */ }; /**************************************************************************** @@ -371,57 +371,57 @@ struct stm32wb_i2c_inst_s ****************************************************************************/ static inline -uint16_t stm32wb_i2c_getreg(struct stm32wb_i2c_priv_s *priv, +uint16_t stm32_i2c_getreg(struct stm32_i2c_priv_s *priv, uint8_t offset); static inline -void stm32wb_i2c_putreg(struct stm32wb_i2c_priv_s *priv, +void stm32_i2c_putreg(struct stm32_i2c_priv_s *priv, uint8_t offset, uint16_t value); static inline -void stm32wb_i2c_putreg32(struct stm32wb_i2c_priv_s *priv, +void stm32_i2c_putreg32(struct stm32_i2c_priv_s *priv, uint8_t offset, uint32_t value); static inline -void stm32wb_i2c_modifyreg32(struct stm32wb_i2c_priv_s *priv, +void stm32_i2c_modifyreg32(struct stm32_i2c_priv_s *priv, uint8_t offset, uint32_t clearbits, uint32_t setbits); -#ifdef CONFIG_STM32WB_I2C_DYNTIMEO -static uint32_t stm32wb_i2c_toticks(int msgc, struct i2c_msg_s *msgs); -#endif /* CONFIG_STM32WB_I2C_DYNTIMEO */ +#ifdef CONFIG_STM32_I2C_DYNTIMEO +static uint32_t stm32_i2c_toticks(int msgc, struct i2c_msg_s *msgs); +#endif /* CONFIG_STM32_I2C_DYNTIMEO */ static inline -int stm32wb_i2c_sem_waitdone(struct stm32wb_i2c_priv_s *priv); +int stm32_i2c_sem_waitdone(struct stm32_i2c_priv_s *priv); static inline -void stm32wb_i2c_sem_waitstop(struct stm32wb_i2c_priv_s *priv); +void stm32_i2c_sem_waitstop(struct stm32_i2c_priv_s *priv); #ifdef CONFIG_I2C_TRACE -static void stm32wb_i2c_tracereset(struct stm32wb_i2c_priv_s *priv); -static void stm32wb_i2c_tracenew(struct stm32wb_i2c_priv_s *priv, +static void stm32_i2c_tracereset(struct stm32_i2c_priv_s *priv); +static void stm32_i2c_tracenew(struct stm32_i2c_priv_s *priv, uint32_t status); static void -stm32wb_i2c_traceevent(struct stm32wb_i2c_priv_s *priv, - enum stm32wb_trace_e event, uint32_t parm); -static void stm32wb_i2c_tracedump(struct stm32wb_i2c_priv_s *priv); +stm32_i2c_traceevent(struct stm32_i2c_priv_s *priv, + enum stm32_trace_e event, uint32_t parm); +static void stm32_i2c_tracedump(struct stm32_i2c_priv_s *priv); #endif /* CONFIG_I2C_TRACE */ -static void stm32wb_i2c_setclock(struct stm32wb_i2c_priv_s *priv, +static void stm32_i2c_setclock(struct stm32_i2c_priv_s *priv, uint32_t frequency); static inline -void stm32wb_i2c_sendstart(struct stm32wb_i2c_priv_s *priv); -static inline void stm32wb_i2c_sendstop(struct stm32wb_i2c_priv_s *priv); +void stm32_i2c_sendstart(struct stm32_i2c_priv_s *priv); +static inline void stm32_i2c_sendstop(struct stm32_i2c_priv_s *priv); static inline -uint32_t stm32wb_i2c_getstatus(struct stm32wb_i2c_priv_s *priv); -static int stm32wb_i2c_isr_process(struct stm32wb_i2c_priv_s *priv); +uint32_t stm32_i2c_getstatus(struct stm32_i2c_priv_s *priv); +static int stm32_i2c_isr_process(struct stm32_i2c_priv_s *priv); #ifndef CONFIG_I2C_POLLED -static int stm32wb_i2c_isr(int irq, void *context, void *arg); +static int stm32_i2c_isr(int irq, void *context, void *arg); #endif -static int stm32wb_i2c_init(struct stm32wb_i2c_priv_s *priv); -static int stm32wb_i2c_deinit(struct stm32wb_i2c_priv_s *priv); +static int stm32_i2c_init(struct stm32_i2c_priv_s *priv); +static int stm32_i2c_deinit(struct stm32_i2c_priv_s *priv); -static int stm32wb_i2c_process(struct i2c_master_s *dev, +static int stm32_i2c_process(struct i2c_master_s *dev, struct i2c_msg_s *msgs, int count); -static int stm32wb_i2c_transfer(struct i2c_master_s *dev, +static int stm32_i2c_transfer(struct i2c_master_s *dev, struct i2c_msg_s *msgs, int count); #ifdef CONFIG_I2C_RESET -static int stm32wb_i2c_reset(struct i2c_master_s *dev); +static int stm32_i2c_reset(struct i2c_master_s *dev); #endif #ifdef CONFIG_PM -static int stm32wb_i2c_pm_prepare(struct pm_callback_s *cb, int domain, +static int stm32_i2c_pm_prepare(struct pm_callback_s *cb, int domain, enum pm_state_e pmstate); #endif @@ -429,23 +429,23 @@ static int stm32wb_i2c_pm_prepare(struct pm_callback_s *cb, int domain, * Private Data ****************************************************************************/ -#ifdef CONFIG_STM32WB_I2C1 -static const struct stm32wb_i2c_config_s stm32wb_i2c1_config = +#ifdef CONFIG_STM32_I2C1 +static const struct stm32_i2c_config_s stm32_i2c1_config = { - .base = STM32WB_I2C1_BASE, + .base = STM32_I2C1_BASE, .clk_bit = RCC_APB1ENR1_I2C1EN, .reset_bit = RCC_APB1RSTR1_I2C1RST, .scl_pin = GPIO_I2C1_SCL, .sda_pin = GPIO_I2C1_SDA, #ifndef CONFIG_I2C_POLLED - .ev_irq = STM32WB_IRQ_I2C1EV, - .er_irq = STM32WB_IRQ_I2C1ER + .ev_irq = STM32_IRQ_I2C1EV, + .er_irq = STM32_IRQ_I2C1ER #endif }; -static struct stm32wb_i2c_priv_s stm32wb_i2c1_priv = +static struct stm32_i2c_priv_s stm32_i2c1_priv = { - .config = &stm32wb_i2c1_config, + .config = &stm32_i2c1_config, .refs = 0, .lock = NXMUTEX_INITIALIZER, #ifndef CONFIG_I2C_POLLED @@ -460,28 +460,28 @@ static struct stm32wb_i2c_priv_s stm32wb_i2c1_priv = .flags = 0, .status = 0, #ifdef CONFIG_PM - .pm_cb.prepare = stm32wb_i2c_pm_prepare, + .pm_cb.prepare = stm32_i2c_pm_prepare, #endif }; #endif -#ifdef CONFIG_STM32WB_I2C3 -static const struct stm32wb_i2c_config_s stm32wb_i2c3_config = +#ifdef CONFIG_STM32_I2C3 +static const struct stm32_i2c_config_s stm32_i2c3_config = { - .base = STM32WB_I2C3_BASE, + .base = STM32_I2C3_BASE, .clk_bit = RCC_APB1ENR1_I2C3EN, .reset_bit = RCC_APB1RSTR1_I2C3RST, .scl_pin = GPIO_I2C3_SCL, .sda_pin = GPIO_I2C3_SDA, #ifndef CONFIG_I2C_POLLED - .ev_irq = STM32WB_IRQ_I2C3EV, - .er_irq = STM32WB_IRQ_I2C3ER + .ev_irq = STM32_IRQ_I2C3EV, + .er_irq = STM32_IRQ_I2C3ER #endif }; -static struct stm32wb_i2c_priv_s stm32wb_i2c3_priv = +static struct stm32_i2c_priv_s stm32_i2c3_priv = { - .config = &stm32wb_i2c3_config, + .config = &stm32_i2c3_config, .refs = 0, .lock = NXMUTEX_INITIALIZER, #ifndef CONFIG_I2C_POLLED @@ -496,18 +496,18 @@ static struct stm32wb_i2c_priv_s stm32wb_i2c3_priv = .flags = 0, .status = 0, #ifdef CONFIG_PM - .pm_cb.prepare = stm32wb_i2c_pm_prepare, + .pm_cb.prepare = stm32_i2c_pm_prepare, #endif }; #endif /* Device Structures, Instantiation */ -static const struct i2c_ops_s stm32wb_i2c_ops = +static const struct i2c_ops_s stm32_i2c_ops = { - .transfer = stm32wb_i2c_transfer, + .transfer = stm32_i2c_transfer, #ifdef CONFIG_I2C_RESET - .reset = stm32wb_i2c_reset + .reset = stm32_i2c_reset #endif }; @@ -516,7 +516,7 @@ static const struct i2c_ops_s stm32wb_i2c_ops = ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_i2c_getreg + * Name: stm32_i2c_getreg * * Description: * Get a 16-bit register value by offset @@ -524,14 +524,14 @@ static const struct i2c_ops_s stm32wb_i2c_ops = ****************************************************************************/ static inline -uint16_t stm32wb_i2c_getreg(struct stm32wb_i2c_priv_s *priv, +uint16_t stm32_i2c_getreg(struct stm32_i2c_priv_s *priv, uint8_t offset) { return getreg16(priv->config->base + offset); } /**************************************************************************** - * Name: stm32wb_i2c_getreg32 + * Name: stm32_i2c_getreg32 * * Description: * Get a 32-bit register value by offset @@ -539,42 +539,42 @@ uint16_t stm32wb_i2c_getreg(struct stm32wb_i2c_priv_s *priv, ****************************************************************************/ static inline -uint32_t stm32wb_i2c_getreg32(struct stm32wb_i2c_priv_s *priv, +uint32_t stm32_i2c_getreg32(struct stm32_i2c_priv_s *priv, uint8_t offset) { return getreg32(priv->config->base + offset); } /**************************************************************************** - * Name: stm32wb_i2c_putreg + * Name: stm32_i2c_putreg * * Description: * Put a 16-bit register value by offset * ****************************************************************************/ -static inline void stm32wb_i2c_putreg(struct stm32wb_i2c_priv_s *priv, +static inline void stm32_i2c_putreg(struct stm32_i2c_priv_s *priv, uint8_t offset, uint16_t value) { putreg16(value, priv->config->base + offset); } /**************************************************************************** - * Name: stm32wb_i2c_putreg32 + * Name: stm32_i2c_putreg32 * * Description: * Put a 32-bit register value by offset * ****************************************************************************/ -static inline void stm32wb_i2c_putreg32(struct stm32wb_i2c_priv_s *priv, +static inline void stm32_i2c_putreg32(struct stm32_i2c_priv_s *priv, uint8_t offset, uint32_t value) { putreg32(value, priv->config->base + offset); } /**************************************************************************** - * Name: stm32wb_i2c_modifyreg32 + * Name: stm32_i2c_modifyreg32 * * Description: * Modify a 32-bit register value by offset @@ -582,7 +582,7 @@ static inline void stm32wb_i2c_putreg32(struct stm32wb_i2c_priv_s *priv, ****************************************************************************/ static inline -void stm32wb_i2c_modifyreg32(struct stm32wb_i2c_priv_s *priv, +void stm32_i2c_modifyreg32(struct stm32_i2c_priv_s *priv, uint8_t offset, uint32_t clearbits, uint32_t setbits) { @@ -590,7 +590,7 @@ void stm32wb_i2c_modifyreg32(struct stm32wb_i2c_priv_s *priv, } /**************************************************************************** - * Name: stm32wb_i2c_toticks + * Name: stm32_i2c_toticks * * Description: * Return a micro-second delay based on the number of bytes left to be @@ -598,8 +598,8 @@ void stm32wb_i2c_modifyreg32(struct stm32wb_i2c_priv_s *priv, * ****************************************************************************/ -#ifdef CONFIG_STM32WB_I2C_DYNTIMEO -static uint32_t stm32wb_i2c_toticks(int msgc, struct i2c_msg_s *msgs) +#ifdef CONFIG_STM32_I2C_DYNTIMEO +static uint32_t stm32_i2c_toticks(int msgc, struct i2c_msg_s *msgs) { size_t bytecount = 0; int i; @@ -615,12 +615,12 @@ static uint32_t stm32wb_i2c_toticks(int msgc, struct i2c_msg_s *msgs) * factor. */ - return USEC2TICK(CONFIG_STM32WB_I2C_DYNTIMEO_USECPERBYTE * bytecount); + return USEC2TICK(CONFIG_STM32_I2C_DYNTIMEO_USECPERBYTE * bytecount); } #endif /**************************************************************************** - * Name: stm32wb_i2c_enableinterrupts + * Name: stm32_i2c_enableinterrupts * * Description: * Enable I2C interrupts @@ -629,15 +629,15 @@ static uint32_t stm32wb_i2c_toticks(int msgc, struct i2c_msg_s *msgs) #ifndef CONFIG_I2C_POLLED static inline -void stm32wb_i2c_enableinterrupts(struct stm32wb_i2c_priv_s *priv) +void stm32_i2c_enableinterrupts(struct stm32_i2c_priv_s *priv) { - stm32wb_i2c_modifyreg32(priv, STM32WB_I2C_CR1_OFFSET, 0, + stm32_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, 0, (I2C_CR1_TXRX | I2C_CR1_NACKIE)); } #endif /**************************************************************************** - * Name: stm32wb_i2c_sem_waitdone + * Name: stm32_i2c_sem_waitdone * * Description: * Wait for a transfer to complete @@ -649,7 +649,7 @@ void stm32wb_i2c_enableinterrupts(struct stm32wb_i2c_priv_s *priv) #ifndef CONFIG_I2C_POLLED static inline -int stm32wb_i2c_sem_waitdone(struct stm32wb_i2c_priv_s *priv) +int stm32_i2c_sem_waitdone(struct stm32_i2c_priv_s *priv) { irqstate_t flags; int ret; @@ -659,11 +659,11 @@ int stm32wb_i2c_sem_waitdone(struct stm32wb_i2c_priv_s *priv) /* Enable I2C interrupts */ /* The TXIE and RXIE interrupts are enabled initially in - * stm32wb_i2c_process. The remainder of the interrupts, including + * stm32_i2c_process. The remainder of the interrupts, including * error-related, are enabled here. */ - stm32wb_i2c_modifyreg32(priv, STM32WB_I2C_CR1_OFFSET, 0, + stm32_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, 0, (I2C_CR1_ALLINTS & ~I2C_CR1_TXRX)); /* Signal the interrupt handler that we are waiting */ @@ -673,12 +673,12 @@ int stm32wb_i2c_sem_waitdone(struct stm32wb_i2c_priv_s *priv) { /* Wait until either the transfer is complete or the timeout expires */ -#ifdef CONFIG_STM32WB_I2C_DYNTIMEO +#ifdef CONFIG_STM32_I2C_DYNTIMEO ret = nxsem_tickwait_uninterruptible(&priv->sem_isr, - stm32wb_i2c_toticks(priv->msgc, priv->msgv)); + stm32_i2c_toticks(priv->msgc, priv->msgv)); #else ret = nxsem_tickwait_uninterruptible(&priv->sem_isr, - CONFIG_STM32WB_I2CTIMEOTICKS); + CONFIG_STM32_I2CTIMEOTICKS); #endif if (ret < 0) { @@ -701,14 +701,14 @@ int stm32wb_i2c_sem_waitdone(struct stm32wb_i2c_priv_s *priv) /* Disable I2C interrupts */ - stm32wb_i2c_modifyreg32(priv, STM32WB_I2C_CR1_OFFSET, I2C_CR1_ALLINTS, 0); + stm32_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, I2C_CR1_ALLINTS, 0); leave_critical_section(flags); return ret; } #else static inline -int stm32wb_i2c_sem_waitdone(struct stm32wb_i2c_priv_s *priv) +int stm32_i2c_sem_waitdone(struct stm32_i2c_priv_s *priv) { clock_t timeout; clock_t start; @@ -717,10 +717,10 @@ int stm32wb_i2c_sem_waitdone(struct stm32wb_i2c_priv_s *priv) /* Get the timeout value */ -#ifdef CONFIG_STM32WB_I2C_DYNTIMEO - timeout = stm32wb_i2c_toticks(priv->msgc, priv->msgv); +#ifdef CONFIG_STM32_I2C_DYNTIMEO + timeout = stm32_i2c_toticks(priv->msgc, priv->msgv); #else - timeout = CONFIG_STM32WB_I2CTIMEOTICKS; + timeout = CONFIG_STM32_I2CTIMEOTICKS; #endif /* Signal the interrupt handler that we are waiting. NOTE: Interrupts @@ -741,7 +741,7 @@ int stm32wb_i2c_sem_waitdone(struct stm32wb_i2c_priv_s *priv) * reports that it is done. */ - stm32wb_i2c_isr_process(priv); + stm32_i2c_isr_process(priv); } /* Loop until the transfer is complete. */ @@ -760,92 +760,92 @@ int stm32wb_i2c_sem_waitdone(struct stm32wb_i2c_priv_s *priv) #endif /**************************************************************************** - * Name: stm32wb_i2c_set_7bit_address + * Name: stm32_i2c_set_7bit_address * * Description: * ****************************************************************************/ static inline void -stm32wb_i2c_set_7bit_address(struct stm32wb_i2c_priv_s *priv) +stm32_i2c_set_7bit_address(struct stm32_i2c_priv_s *priv) { - stm32wb_i2c_modifyreg32(priv, STM32WB_I2C_CR2_OFFSET, I2C_CR2_SADD7_MASK, + stm32_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, I2C_CR2_SADD7_MASK, (priv->msgv->addr << I2C_CR2_SADD7_SHIFT) & I2C_CR2_SADD7_MASK); } /**************************************************************************** - * Name: stm32wb_i2c_set_bytes_to_transfer + * Name: stm32_i2c_set_bytes_to_transfer * * Description: * ****************************************************************************/ static inline void -stm32wb_i2c_set_bytes_to_transfer(struct stm32wb_i2c_priv_s *priv, +stm32_i2c_set_bytes_to_transfer(struct stm32_i2c_priv_s *priv, uint8_t n_bytes) { - stm32wb_i2c_modifyreg32(priv, STM32WB_I2C_CR2_OFFSET, I2C_CR2_NBYTES_MASK, + stm32_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, I2C_CR2_NBYTES_MASK, (n_bytes << I2C_CR2_NBYTES_SHIFT)); } /**************************************************************************** - * Name: stm32wb_i2c_set_write_transfer_dir + * Name: stm32_i2c_set_write_transfer_dir * * Description: * ****************************************************************************/ static inline void -stm32wb_i2c_set_write_transfer_dir(struct stm32wb_i2c_priv_s *priv) +stm32_i2c_set_write_transfer_dir(struct stm32_i2c_priv_s *priv) { - stm32wb_i2c_modifyreg32(priv, STM32WB_I2C_CR2_OFFSET, I2C_CR2_RD_WRN, 0); + stm32_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, I2C_CR2_RD_WRN, 0); } /**************************************************************************** - * Name: stm32wb_i2c_set_read_transfer_dir + * Name: stm32_i2c_set_read_transfer_dir * * Description: * ****************************************************************************/ static inline void -stm32wb_i2c_set_read_transfer_dir(struct stm32wb_i2c_priv_s *priv) +stm32_i2c_set_read_transfer_dir(struct stm32_i2c_priv_s *priv) { - stm32wb_i2c_modifyreg32(priv, STM32WB_I2C_CR2_OFFSET, + stm32_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, 0, I2C_CR2_RD_WRN); } /**************************************************************************** - * Name: stm32wb_i2c_enable_reload + * Name: stm32_i2c_enable_reload * * Description: * ****************************************************************************/ static inline void -stm32wb_i2c_enable_reload(struct stm32wb_i2c_priv_s *priv) +stm32_i2c_enable_reload(struct stm32_i2c_priv_s *priv) { - stm32wb_i2c_modifyreg32(priv, STM32WB_I2C_CR2_OFFSET, + stm32_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, 0, I2C_CR2_RELOAD); } /**************************************************************************** - * Name: stm32wb_i2c_disable_reload + * Name: stm32_i2c_disable_reload * * Description: * ****************************************************************************/ static inline void -stm32wb_i2c_disable_reload(struct stm32wb_i2c_priv_s *priv) +stm32_i2c_disable_reload(struct stm32_i2c_priv_s *priv) { - stm32wb_i2c_modifyreg32(priv, STM32WB_I2C_CR2_OFFSET, + stm32_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, I2C_CR2_RELOAD, 0); } /**************************************************************************** - * Name: stm32wb_i2c_sem_waitstop + * Name: stm32_i2c_sem_waitstop * * Description: * Wait for a STOP to complete @@ -853,7 +853,7 @@ stm32wb_i2c_disable_reload(struct stm32wb_i2c_priv_s *priv) ****************************************************************************/ static inline -void stm32wb_i2c_sem_waitstop(struct stm32wb_i2c_priv_s *priv) +void stm32_i2c_sem_waitstop(struct stm32_i2c_priv_s *priv) { clock_t start; clock_t elapsed; @@ -863,10 +863,10 @@ void stm32wb_i2c_sem_waitstop(struct stm32wb_i2c_priv_s *priv) /* Select a timeout */ -#ifdef CONFIG_STM32WB_I2C_DYNTIMEO - timeout = USEC2TICK(CONFIG_STM32WB_I2C_DYNTIMEO_STARTSTOP); +#ifdef CONFIG_STM32_I2C_DYNTIMEO + timeout = USEC2TICK(CONFIG_STM32_I2C_DYNTIMEO_STARTSTOP); #else - timeout = CONFIG_STM32WB_I2CTIMEOTICKS; + timeout = CONFIG_STM32_I2CTIMEOTICKS; #endif /* Wait as stop might still be in progress */ @@ -880,7 +880,7 @@ void stm32wb_i2c_sem_waitstop(struct stm32wb_i2c_priv_s *priv) /* Check for STOP condition */ - cr = stm32wb_i2c_getreg32(priv, STM32WB_I2C_CR2_OFFSET); + cr = stm32_i2c_getreg32(priv, STM32_I2C_CR2_OFFSET); if ((cr & I2C_CR2_STOP) == 0) { return; @@ -888,7 +888,7 @@ void stm32wb_i2c_sem_waitstop(struct stm32wb_i2c_priv_s *priv) /* Check for timeout error */ - sr = stm32wb_i2c_getreg(priv, STM32WB_I2C_ISR_OFFSET); + sr = stm32_i2c_getreg(priv, STM32_I2C_ISR_OFFSET); if ((sr & I2C_INT_TIMEOUT) != 0) { i2cerr("ERROR: waiting for a STOP isr timeout, elapsed: %lu\n", @@ -909,7 +909,7 @@ void stm32wb_i2c_sem_waitstop(struct stm32wb_i2c_priv_s *priv) } /**************************************************************************** - * Name: stm32wb_i2c_trace* + * Name: stm32_i2c_trace* * * Description: * I2C trace instrumentation @@ -917,9 +917,9 @@ void stm32wb_i2c_sem_waitstop(struct stm32wb_i2c_priv_s *priv) ****************************************************************************/ #ifdef CONFIG_I2C_TRACE -static void stm32wb_i2c_traceclear(struct stm32wb_i2c_priv_s *priv) +static void stm32_i2c_traceclear(struct stm32_i2c_priv_s *priv) { - struct stm32wb_trace_s *trace = &priv->trace[priv->tndx]; + struct stm32_trace_s *trace = &priv->trace[priv->tndx]; trace->status = 0; /* I2C 32-bit status */ trace->count = 0; /* Interrupt count when status change */ @@ -928,19 +928,19 @@ static void stm32wb_i2c_traceclear(struct stm32wb_i2c_priv_s *priv) trace->time = 0; /* Time of first status or event */ } -static void stm32wb_i2c_tracereset(struct stm32wb_i2c_priv_s *priv) +static void stm32_i2c_tracereset(struct stm32_i2c_priv_s *priv) { /* Reset the trace info for a new data collection */ priv->tndx = 0; priv->start_time = clock_systime_ticks(); - stm32wb_i2c_traceclear(priv); + stm32_i2c_traceclear(priv); } -static void stm32wb_i2c_tracenew(struct stm32wb_i2c_priv_s *priv, +static void stm32_i2c_tracenew(struct stm32_i2c_priv_s *priv, uint32_t status) { - struct stm32wb_trace_s *trace = &priv->trace[priv->tndx]; + struct stm32_trace_s *trace = &priv->trace[priv->tndx]; /* Is the current entry uninitialized? Has the status changed? */ @@ -966,7 +966,7 @@ static void stm32wb_i2c_tracenew(struct stm32wb_i2c_priv_s *priv, /* Initialize the new trace entry */ - stm32wb_i2c_traceclear(priv); + stm32_i2c_traceclear(priv); trace->status = status; trace->count = 1; trace->time = clock_systime_ticks(); @@ -979,10 +979,10 @@ static void stm32wb_i2c_tracenew(struct stm32wb_i2c_priv_s *priv, } } -static void stm32wb_i2c_traceevent(struct stm32wb_i2c_priv_s *priv, - enum stm32wb_trace_e event, uint32_t parm) +static void stm32_i2c_traceevent(struct stm32_i2c_priv_s *priv, + enum stm32_trace_e event, uint32_t parm) { - struct stm32wb_trace_s *trace; + struct stm32_trace_s *trace; if (event != I2CEVENT_NONE) { @@ -1002,13 +1002,13 @@ static void stm32wb_i2c_traceevent(struct stm32wb_i2c_priv_s *priv, } priv->tndx++; - stm32wb_i2c_traceclear(priv); + stm32_i2c_traceclear(priv); } } -static void stm32wb_i2c_tracedump(struct stm32wb_i2c_priv_s *priv) +static void stm32_i2c_tracedump(struct stm32_i2c_priv_s *priv) { - struct stm32wb_trace_s *trace; + struct stm32_trace_s *trace; int i; syslog(LOG_DEBUG, "Elapsed time: %d\n", @@ -1026,7 +1026,7 @@ static void stm32wb_i2c_tracedump(struct stm32wb_i2c_priv_s *priv) #endif /* CONFIG_I2C_TRACE */ /**************************************************************************** - * Name: stm32wb_i2c_setclock + * Name: stm32_i2c_setclock * * Description: * @@ -1066,7 +1066,7 @@ static void stm32wb_i2c_tracedump(struct stm32wb_i2c_priv_s *priv) * ****************************************************************************/ -static void stm32wb_i2c_setclock(struct stm32wb_i2c_priv_s *priv, +static void stm32_i2c_setclock(struct stm32_i2c_priv_s *priv, uint32_t frequency) { uint32_t pe; @@ -1076,14 +1076,14 @@ static void stm32wb_i2c_setclock(struct stm32wb_i2c_priv_s *priv, { /* I2C peripheral must be disabled to update clocking configuration */ - pe = stm32wb_i2c_getreg32(priv, STM32WB_I2C_CR1_OFFSET) & I2C_CR1_PE; + pe = stm32_i2c_getreg32(priv, STM32_I2C_CR1_OFFSET) & I2C_CR1_PE; if (pe) { - stm32wb_i2c_modifyreg32(priv, STM32WB_I2C_CR1_OFFSET, + stm32_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, I2C_CR1_PE, 0); } -#if defined(STM32WB_I2C_USE_HSI16) +#if defined(STM32_I2C_USE_HSI16) switch (frequency) { case 100000ul: @@ -1104,7 +1104,7 @@ static void stm32wb_i2c_setclock(struct stm32wb_i2c_priv_s *priv, } #else -#if STM32WB_PCLK1_FREQUENCY != 64000000ul +#if STM32_PCLK1_FREQUENCY != 64000000ul # error Unsupported I2C configuration. #endif @@ -1128,11 +1128,11 @@ static void stm32wb_i2c_setclock(struct stm32wb_i2c_priv_s *priv, } #endif - stm32wb_i2c_putreg32(priv, STM32WB_I2C_TIMINGR_OFFSET, timingr); + stm32_i2c_putreg32(priv, STM32_I2C_TIMINGR_OFFSET, timingr); if (pe) { - stm32wb_i2c_modifyreg32(priv, STM32WB_I2C_CR1_OFFSET, + stm32_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, 0, I2C_CR1_PE); } @@ -1141,7 +1141,7 @@ static void stm32wb_i2c_setclock(struct stm32wb_i2c_priv_s *priv, } /**************************************************************************** - * Name: stm32wb_i2c_sendstart + * Name: stm32_i2c_sendstart * * Description: * Send the START condition / force Master mode @@ -1168,7 +1168,7 @@ static void stm32wb_i2c_setclock(struct stm32wb_i2c_priv_s *priv, ****************************************************************************/ static inline -void stm32wb_i2c_sendstart(struct stm32wb_i2c_priv_s *priv) +void stm32_i2c_sendstart(struct stm32_i2c_priv_s *priv) { bool next_norestart = false; @@ -1230,13 +1230,13 @@ void stm32wb_i2c_sendstart(struct stm32wb_i2c_priv_s *priv) { i2cinfo("RELOAD enabled: dcnt = %i msgc = %i\n", priv->dcnt, priv->msgc); - stm32wb_i2c_enable_reload(priv); + stm32_i2c_enable_reload(priv); } else { i2cinfo("RELOAD disable: dcnt = %i msgc = %i\n", priv->dcnt, priv->msgc); - stm32wb_i2c_disable_reload(priv); + stm32_i2c_disable_reload(priv); } /* Set the number of bytes to transfer (I2C_CR2->NBYTES) to the number of @@ -1246,18 +1246,18 @@ void stm32wb_i2c_sendstart(struct stm32wb_i2c_priv_s *priv) if (priv->dcnt > 255) { - stm32wb_i2c_set_bytes_to_transfer(priv, 255); + stm32_i2c_set_bytes_to_transfer(priv, 255); } else { - stm32wb_i2c_set_bytes_to_transfer(priv, priv->dcnt); + stm32_i2c_set_bytes_to_transfer(priv, priv->dcnt); } /* Set the (7 bit) address. * 10 bit addressing is not yet supported. */ - stm32wb_i2c_set_7bit_address(priv); + stm32_i2c_set_7bit_address(priv); /* The flag of the current message is used to determine the direction of * transfer required for the current message. @@ -1265,11 +1265,11 @@ void stm32wb_i2c_sendstart(struct stm32wb_i2c_priv_s *priv) if (priv->flags & I2C_M_READ) { - stm32wb_i2c_set_read_transfer_dir(priv); + stm32_i2c_set_read_transfer_dir(priv); } else { - stm32wb_i2c_set_write_transfer_dir(priv); + stm32_i2c_set_write_transfer_dir(priv); } /* Set the I2C_CR2->START bit to 1 to instruct the hardware to send the @@ -1279,11 +1279,11 @@ void stm32wb_i2c_sendstart(struct stm32wb_i2c_priv_s *priv) i2cinfo("Sending START: dcnt=%i msgc=%i flags=0x%04x\n", priv->dcnt, priv->msgc, priv->flags); - stm32wb_i2c_modifyreg32(priv, STM32WB_I2C_CR2_OFFSET, 0, I2C_CR2_START); + stm32_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, 0, I2C_CR2_START); } /**************************************************************************** - * Name: stm32wb_i2c_sendstop + * Name: stm32_i2c_sendstop * * Description: * Send the STOP conditions @@ -1295,17 +1295,17 @@ void stm32wb_i2c_sendstart(struct stm32wb_i2c_priv_s *priv) ****************************************************************************/ static inline -void stm32wb_i2c_sendstop(struct stm32wb_i2c_priv_s *priv) +void stm32_i2c_sendstop(struct stm32_i2c_priv_s *priv) { i2cinfo("Sending STOP\n"); - stm32wb_i2c_traceevent(priv, I2CEVENT_WRITE_STOP, 0); + stm32_i2c_traceevent(priv, I2CEVENT_WRITE_STOP, 0); - stm32wb_i2c_modifyreg32(priv, STM32WB_I2C_CR2_OFFSET, + stm32_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, 0, I2C_CR2_STOP); } /**************************************************************************** - * Name: stm32wb_i2c_getstatus + * Name: stm32_i2c_getstatus * * Description: * Get 32-bit status (SR1 and SR2 combined) @@ -1313,13 +1313,13 @@ void stm32wb_i2c_sendstop(struct stm32wb_i2c_priv_s *priv) ****************************************************************************/ static inline -uint32_t stm32wb_i2c_getstatus(struct stm32wb_i2c_priv_s *priv) +uint32_t stm32_i2c_getstatus(struct stm32_i2c_priv_s *priv) { - return getreg32(priv->config->base + STM32WB_I2C_ISR_OFFSET); + return getreg32(priv->config->base + STM32_I2C_ISR_OFFSET); } /**************************************************************************** - * Name: stm32wb_i2c_clearinterrupts + * Name: stm32_i2c_clearinterrupts * * Description: * Clear all interrupts @@ -1327,14 +1327,14 @@ uint32_t stm32wb_i2c_getstatus(struct stm32wb_i2c_priv_s *priv) ****************************************************************************/ static inline -void stm32wb_i2c_clearinterrupts(struct stm32wb_i2c_priv_s *priv) +void stm32_i2c_clearinterrupts(struct stm32_i2c_priv_s *priv) { - stm32wb_i2c_modifyreg32(priv, STM32WB_I2C_ICR_OFFSET, + stm32_i2c_modifyreg32(priv, STM32_I2C_ICR_OFFSET, 0, I2C_ICR_CLEARMASK); } /**************************************************************************** - * Name: stm32wb_i2c_isr_process + * Name: stm32_i2c_isr_process * * Description: * Common interrupt service routine (ISR) that handles I2C protocol logic. @@ -1342,22 +1342,22 @@ void stm32wb_i2c_clearinterrupts(struct stm32wb_i2c_priv_s *priv) * * This ISR is activated and deactivated by: * - * stm32wb_i2c_process + * stm32_i2c_process * and - * stm32wb_i2c_waitdone + * stm32_i2c_waitdone * * Input Parameters: * priv - The private struct of the I2C driver. * ****************************************************************************/ -static int stm32wb_i2c_isr_process(struct stm32wb_i2c_priv_s *priv) +static int stm32_i2c_isr_process(struct stm32_i2c_priv_s *priv) { uint32_t status; /* Get state of the I2C controller */ - status = stm32wb_i2c_getreg32(priv, STM32WB_I2C_ISR_OFFSET); + status = stm32_i2c_getreg32(priv, STM32_I2C_ISR_OFFSET); i2cinfo("ENTER: status = 0x%08" PRIx32 "\n", status); @@ -1367,8 +1367,8 @@ static int stm32wb_i2c_isr_process(struct stm32wb_i2c_priv_s *priv) /* If this is a new transmission set up the trace table accordingly */ - stm32wb_i2c_tracenew(priv, status); - stm32wb_i2c_traceevent(priv, I2CEVENT_ISR_CALL, 0); + stm32_i2c_tracenew(priv, status); + stm32_i2c_traceevent(priv, I2CEVENT_ISR_CALL, 0); /* ------------------- Start of I2C protocol handling ------------------ */ @@ -1410,7 +1410,7 @@ static int stm32wb_i2c_isr_process(struct stm32wb_i2c_priv_s *priv) i2cinfo("NACK: Address invalid: dcnt=%i " "msgc=%i status=0x%08" PRIx32 "\n", priv->dcnt, priv->msgc, status); - stm32wb_i2c_traceevent(priv, I2CEVENT_ADDRESS_NACKED, + stm32_i2c_traceevent(priv, I2CEVENT_ADDRESS_NACKED, priv->msgv->addr); } else @@ -1420,7 +1420,7 @@ static int stm32wb_i2c_isr_process(struct stm32wb_i2c_priv_s *priv) i2cinfo("NACK: NACK received: dcnt=%i " "msgc=%i status=0x%08" PRIx32 "\n", priv->dcnt, priv->msgc, status); - stm32wb_i2c_traceevent(priv, I2CEVENT_ADDRESS_NACKED, + stm32_i2c_traceevent(priv, I2CEVENT_ADDRESS_NACKED, priv->msgv->addr); } @@ -1474,7 +1474,7 @@ static int stm32wb_i2c_isr_process(struct stm32wb_i2c_priv_s *priv) { /* TXIS interrupt occurred, address valid, ready to transmit */ - stm32wb_i2c_traceevent(priv, I2CEVENT_WRITE, 0); + stm32_i2c_traceevent(priv, I2CEVENT_WRITE, 0); i2cinfo("TXIS: ENTER dcnt = %i msgc = %i status 0x%08" PRIx32 "\n", priv->dcnt, priv->msgc, status); @@ -1487,7 +1487,7 @@ static int stm32wb_i2c_isr_process(struct stm32wb_i2c_priv_s *priv) if (priv->astart == true) { i2cinfo("TXIS: Address Valid\n"); - stm32wb_i2c_traceevent(priv, I2CEVENT_ADDRESS_ACKED, + stm32_i2c_traceevent(priv, I2CEVENT_ADDRESS_ACKED, priv->msgv->addr); priv->astart = false; } @@ -1498,7 +1498,7 @@ static int stm32wb_i2c_isr_process(struct stm32wb_i2c_priv_s *priv) { /* Prepare to transmit the current byte */ - stm32wb_i2c_traceevent(priv, I2CEVENT_WRITE_TO_DR, priv->dcnt); + stm32_i2c_traceevent(priv, I2CEVENT_WRITE_TO_DR, priv->dcnt); i2cinfo("TXIS: Write Data 0x%02x\n", *priv->ptr); /* Decrement byte counter */ @@ -1520,13 +1520,13 @@ static int stm32wb_i2c_isr_process(struct stm32wb_i2c_priv_s *priv) if (priv->msgc == 1) { - stm32wb_i2c_disable_reload(priv); + stm32_i2c_disable_reload(priv); } } /* Transmit current byte */ - stm32wb_i2c_putreg(priv, STM32WB_I2C_TXDR_OFFSET, *priv->ptr); + stm32_i2c_putreg(priv, STM32_I2C_TXDR_OFFSET, *priv->ptr); /* Advance to next byte */ @@ -1539,7 +1539,7 @@ static int stm32wb_i2c_isr_process(struct stm32wb_i2c_priv_s *priv) i2cerr("ERROR: TXIS Unsupported state detected, dcnt=%i, " "status 0x%08" PRIx32 "\n", priv->dcnt, status); - stm32wb_i2c_traceevent(priv, I2CEVENT_WRITE_ERROR, 0); + stm32_i2c_traceevent(priv, I2CEVENT_WRITE_ERROR, 0); } i2cinfo("TXIS: EXIT dcnt = %i msgc = %i status 0x%08" PRIx32 "\n", @@ -1582,7 +1582,7 @@ static int stm32wb_i2c_isr_process(struct stm32wb_i2c_priv_s *priv) * (RXNE is set) then the driver can read from the data register. */ - stm32wb_i2c_traceevent(priv, I2CEVENT_READ, 0); + stm32_i2c_traceevent(priv, I2CEVENT_READ, 0); i2cinfo("RXNE: ENTER dcnt = %i msgc = %i status 0x%08" PRIx32 "\n", priv->dcnt, priv->msgc, status); @@ -1590,7 +1590,7 @@ static int stm32wb_i2c_isr_process(struct stm32wb_i2c_priv_s *priv) if (priv->dcnt > 0) { - stm32wb_i2c_traceevent(priv, I2CEVENT_RCVBYTE, priv->dcnt); + stm32_i2c_traceevent(priv, I2CEVENT_RCVBYTE, priv->dcnt); /* No interrupts or context switches may occur in the following * sequence. Otherwise, additional bytes may be received. @@ -1601,7 +1601,7 @@ static int stm32wb_i2c_isr_process(struct stm32wb_i2c_priv_s *priv) #endif /* Receive a byte */ - *priv->ptr = stm32wb_i2c_getreg(priv, STM32WB_I2C_RXDR_OFFSET); + *priv->ptr = stm32_i2c_getreg(priv, STM32_I2C_RXDR_OFFSET); i2cinfo("RXNE: Read Data 0x%02x\n", *priv->ptr); @@ -1621,8 +1621,8 @@ static int stm32wb_i2c_isr_process(struct stm32wb_i2c_priv_s *priv) { /* Unsupported state */ - stm32wb_i2c_traceevent(priv, I2CEVENT_READ_ERROR, 0); - status = stm32wb_i2c_getreg(priv, STM32WB_I2C_ISR_OFFSET); + stm32_i2c_traceevent(priv, I2CEVENT_READ_ERROR, 0); + status = stm32_i2c_getreg(priv, STM32_I2C_ISR_OFFSET); i2cerr("ERROR: RXNE Unsupported state detected, dcnt=%i, " "status 0x%08" PRIx32 "\n", priv->dcnt, status); @@ -1688,7 +1688,7 @@ static int stm32wb_i2c_isr_process(struct stm32wb_i2c_priv_s *priv) { i2cinfo("TC: RESTART: dcnt=%i, msgc=%i\n", priv->dcnt, priv->msgc); - stm32wb_i2c_traceevent(priv, I2CEVENT_TC_NO_RESTART, priv->msgc); + stm32_i2c_traceevent(priv, I2CEVENT_TC_NO_RESTART, priv->msgc); /* Issue a START condition. * @@ -1702,7 +1702,7 @@ static int stm32wb_i2c_isr_process(struct stm32wb_i2c_priv_s *priv) priv->msgv++; - stm32wb_i2c_sendstart(priv); + stm32_i2c_sendstart(priv); } else { @@ -1715,9 +1715,9 @@ static int stm32wb_i2c_isr_process(struct stm32wb_i2c_priv_s *priv) i2cinfo("TC: STOP: dcnt=%i msgc=%i\n", priv->dcnt, priv->msgc); - stm32wb_i2c_traceevent(priv, I2CEVENT_STOP, priv->dcnt); + stm32_i2c_traceevent(priv, I2CEVENT_STOP, priv->dcnt); - stm32wb_i2c_sendstop(priv); + stm32_i2c_sendstop(priv); /* Set signals that will terminate ISR and wake waiting thread */ @@ -1796,7 +1796,7 @@ static int stm32wb_i2c_isr_process(struct stm32wb_i2c_priv_s *priv) i2cinfo("TCR: DISABLE RELOAD: dcnt = %i msgc = %i\n", priv->dcnt, priv->msgc); - stm32wb_i2c_disable_reload(priv); + stm32_i2c_disable_reload(priv); } /* Update NBYTES with length of current message */ @@ -1804,7 +1804,7 @@ static int stm32wb_i2c_isr_process(struct stm32wb_i2c_priv_s *priv) i2cinfo("TCR: NEXT MSG dcnt = %i msgc = %i\n", priv->dcnt, priv->msgc); - stm32wb_i2c_set_bytes_to_transfer(priv, priv->dcnt); + stm32_i2c_set_bytes_to_transfer(priv, priv->dcnt); } else { @@ -1829,9 +1829,9 @@ static int stm32wb_i2c_isr_process(struct stm32wb_i2c_priv_s *priv) * the transfer. */ - stm32wb_i2c_enable_reload(priv); + stm32_i2c_enable_reload(priv); - stm32wb_i2c_set_bytes_to_transfer(priv, 255); + stm32_i2c_set_bytes_to_transfer(priv, 255); } else { @@ -1848,9 +1848,9 @@ static int stm32wb_i2c_isr_process(struct stm32wb_i2c_priv_s *priv) i2cinfo("TCR: DISABLE RELOAD: NBYTES = dcnt = %i msgc = %i\n", priv->dcnt, priv->msgc); - stm32wb_i2c_disable_reload(priv); + stm32_i2c_disable_reload(priv); - stm32wb_i2c_set_bytes_to_transfer(priv, priv->dcnt); + stm32_i2c_set_bytes_to_transfer(priv, priv->dcnt); } i2cinfo("TCR: EXIT dcnt = %i msgc = %i status 0x%08" PRIx32 "\n", @@ -1866,10 +1866,10 @@ static int stm32wb_i2c_isr_process(struct stm32wb_i2c_priv_s *priv) else if (priv->dcnt == -1 && priv->msgc == 0) { - status = stm32wb_i2c_getreg(priv, STM32WB_I2C_ISR_OFFSET); + status = stm32_i2c_getreg(priv, STM32_I2C_ISR_OFFSET); i2cwarn("WARNING: EMPTY CALL: Stopping ISR: status 0x%08" PRIx32 "\n", status); - stm32wb_i2c_traceevent(priv, I2CEVENT_ISR_EMPTY_CALL, 0); + stm32_i2c_traceevent(priv, I2CEVENT_ISR_EMPTY_CALL, 0); } /* Error handler @@ -1885,11 +1885,11 @@ static int stm32wb_i2c_isr_process(struct stm32wb_i2c_priv_s *priv) else { #ifdef CONFIG_I2C_POLLED - stm32wb_i2c_traceevent(priv, I2CEVENT_POLL_DEV_NOT_RDY, 0); + stm32_i2c_traceevent(priv, I2CEVENT_POLL_DEV_NOT_RDY, 0); #else /* Read rest of the state */ - status = stm32wb_i2c_getreg(priv, STM32WB_I2C_ISR_OFFSET); + status = stm32_i2c_getreg(priv, STM32_I2C_ISR_OFFSET); i2cerr("ERROR: Invalid state detected, status 0x%08" PRIx32 "\n", status); @@ -1898,7 +1898,7 @@ static int stm32wb_i2c_isr_process(struct stm32wb_i2c_priv_s *priv) priv->dcnt = -1; priv->msgc = 0; - stm32wb_i2c_traceevent(priv, I2CEVENT_STATE_ERROR, 0); + stm32_i2c_traceevent(priv, I2CEVENT_STATE_ERROR, 0); #endif } @@ -1907,7 +1907,7 @@ static int stm32wb_i2c_isr_process(struct stm32wb_i2c_priv_s *priv) /* Message Handling * * Transmission of the whole message chain has been completed. We have to - * terminate the ISR and wake up stm32wb_i2c_process() that is waiting for + * terminate the ISR and wake up stm32_i2c_process() that is waiting for * the ISR cycle to handle the sending/receiving of the messages. */ @@ -1915,7 +1915,7 @@ static int stm32wb_i2c_isr_process(struct stm32wb_i2c_priv_s *priv) { i2cinfo("MSG: Shutting down I2C ISR\n"); - stm32wb_i2c_traceevent(priv, I2CEVENT_ISR_SHUTDOWN, 0); + stm32_i2c_traceevent(priv, I2CEVENT_ISR_SHUTDOWN, 0); /* Clear pointer to message content to reflect we are done * with the current transaction. @@ -1927,7 +1927,7 @@ static int stm32wb_i2c_isr_process(struct stm32wb_i2c_priv_s *priv) priv->intstate = INTSTATE_DONE; #else - status = stm32wb_i2c_getreg32(priv, STM32WB_I2C_ISR_OFFSET); + status = stm32_i2c_getreg32(priv, STM32_I2C_ISR_OFFSET); /* Update private state to capture NACK which is used in combination * with the astart flag to report the type of NACK received (address @@ -1941,7 +1941,7 @@ static int stm32wb_i2c_isr_process(struct stm32wb_i2c_priv_s *priv) /* Clear all interrupts */ - stm32wb_i2c_modifyreg32(priv, STM32WB_I2C_ICR_OFFSET, + stm32_i2c_modifyreg32(priv, STM32_I2C_ICR_OFFSET, 0, I2C_ICR_CLEARMASK); /* If a thread is waiting then inform it transfer is complete */ @@ -1954,14 +1954,14 @@ static int stm32wb_i2c_isr_process(struct stm32wb_i2c_priv_s *priv) #endif } - status = stm32wb_i2c_getreg32(priv, STM32WB_I2C_ISR_OFFSET); + status = stm32_i2c_getreg32(priv, STM32_I2C_ISR_OFFSET); i2cinfo("EXIT: status = 0x%08" PRIx32 "\n", status); return OK; } /**************************************************************************** - * Name: stm32wb_i2c_isr + * Name: stm32_i2c_isr * * Description: * Common I2C interrupt service routine @@ -1969,51 +1969,51 @@ static int stm32wb_i2c_isr_process(struct stm32wb_i2c_priv_s *priv) ****************************************************************************/ #ifndef CONFIG_I2C_POLLED -static int stm32wb_i2c_isr(int irq, void *context, void *arg) +static int stm32_i2c_isr(int irq, void *context, void *arg) { - struct stm32wb_i2c_priv_s *priv = (struct stm32wb_i2c_priv_s *)arg; + struct stm32_i2c_priv_s *priv = (struct stm32_i2c_priv_s *)arg; DEBUGASSERT(priv != NULL); - return stm32wb_i2c_isr_process(priv); + return stm32_i2c_isr_process(priv); } #endif /**************************************************************************** - * Name: stm32wb_i2c_init + * Name: stm32_i2c_init * * Description: * Setup the I2C hardware, ready for operation with defaults * ****************************************************************************/ -static int stm32wb_i2c_init(struct stm32wb_i2c_priv_s *priv) +static int stm32_i2c_init(struct stm32_i2c_priv_s *priv) { /* Power-up and configure GPIOs */ /* Enable power and reset the peripheral */ - modifyreg32(STM32WB_RCC_APB1ENR1, 0, priv->config->clk_bit); - modifyreg32(STM32WB_RCC_APB1RSTR1, 0, priv->config->reset_bit); - modifyreg32(STM32WB_RCC_APB1RSTR1, priv->config->reset_bit, 0); + modifyreg32(STM32_RCC_APB1ENR1, 0, priv->config->clk_bit); + modifyreg32(STM32_RCC_APB1RSTR1, 0, priv->config->reset_bit); + modifyreg32(STM32_RCC_APB1RSTR1, priv->config->reset_bit, 0); /* Configure pins */ - if (stm32wb_configgpio(priv->config->scl_pin) < 0) + if (stm32_configgpio(priv->config->scl_pin) < 0) { return ERROR; } - if (stm32wb_configgpio(priv->config->sda_pin) < 0) + if (stm32_configgpio(priv->config->sda_pin) < 0) { - stm32wb_unconfiggpio(priv->config->scl_pin); + stm32_unconfiggpio(priv->config->scl_pin); return ERROR; } #ifndef CONFIG_I2C_POLLED /* Attach error and event interrupts to the ISRs */ - irq_attach(priv->config->ev_irq, stm32wb_i2c_isr, priv); - irq_attach(priv->config->er_irq, stm32wb_i2c_isr, priv); + irq_attach(priv->config->ev_irq, stm32_i2c_isr, priv); + irq_attach(priv->config->er_irq, stm32_i2c_isr, priv); up_enable_irq(priv->config->ev_irq); up_enable_irq(priv->config->er_irq); #endif @@ -2026,33 +2026,33 @@ static int stm32wb_i2c_init(struct stm32wb_i2c_priv_s *priv) /* Force a frequency update */ priv->frequency = 0; - stm32wb_i2c_setclock(priv, 100000); + stm32_i2c_setclock(priv, 100000); /* Enable I2C peripheral */ - stm32wb_i2c_modifyreg32(priv, STM32WB_I2C_CR1_OFFSET, 0, I2C_CR1_PE); + stm32_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, 0, I2C_CR1_PE); return OK; } /**************************************************************************** - * Name: stm32wb_i2c_deinit + * Name: stm32_i2c_deinit * * Description: * Shutdown the I2C hardware * ****************************************************************************/ -static int stm32wb_i2c_deinit(struct stm32wb_i2c_priv_s *priv) +static int stm32_i2c_deinit(struct stm32_i2c_priv_s *priv) { /* Disable I2C */ - stm32wb_i2c_putreg32(priv, STM32WB_I2C_CR1_OFFSET, 0); + stm32_i2c_putreg32(priv, STM32_I2C_CR1_OFFSET, 0); /* Unconfigure GPIO pins */ - stm32wb_unconfiggpio(priv->config->scl_pin); - stm32wb_unconfiggpio(priv->config->sda_pin); + stm32_unconfiggpio(priv->config->scl_pin); + stm32_unconfiggpio(priv->config->sda_pin); #ifndef CONFIG_I2C_POLLED @@ -2066,13 +2066,13 @@ static int stm32wb_i2c_deinit(struct stm32wb_i2c_priv_s *priv) /* Disable clocking */ - modifyreg32(STM32WB_RCC_APB1ENR1, priv->config->clk_bit, 0); + modifyreg32(STM32_RCC_APB1ENR1, priv->config->clk_bit, 0); return OK; } /**************************************************************************** - * Name: stm32wb_i2c_process + * Name: stm32_i2c_process * * Description: * Common I2C transfer logic @@ -2082,11 +2082,11 @@ static int stm32wb_i2c_deinit(struct stm32wb_i2c_priv_s *priv) * ****************************************************************************/ -static int stm32wb_i2c_process(struct i2c_master_s *dev, +static int stm32_i2c_process(struct i2c_master_s *dev, struct i2c_msg_s *msgs, int count) { - struct stm32wb_i2c_inst_s *inst = (struct stm32wb_i2c_inst_s *)dev; - struct stm32wb_i2c_priv_s *priv = inst->priv; + struct stm32_i2c_inst_s *inst = (struct stm32_i2c_inst_s *)dev; + struct stm32_i2c_priv_s *priv = inst->priv; uint32_t status = 0; uint32_t cr1; uint32_t cr2; @@ -2097,11 +2097,11 @@ static int stm32wb_i2c_process(struct i2c_master_s *dev, /* Wait for any STOP in progress */ - stm32wb_i2c_sem_waitstop(priv); + stm32_i2c_sem_waitstop(priv); /* Clear any pending error interrupts */ - stm32wb_i2c_clearinterrupts(priv); + stm32_i2c_clearinterrupts(priv); /* Old transfers are done */ @@ -2110,14 +2110,14 @@ static int stm32wb_i2c_process(struct i2c_master_s *dev, /* Reset I2C trace logic */ - stm32wb_i2c_tracereset(priv); + stm32_i2c_tracereset(priv); /* Set I2C clock frequency (on change it toggles I2C_CR1_PE !) */ - stm32wb_i2c_setclock(priv, msgs->frequency); + stm32_i2c_setclock(priv, msgs->frequency); /* Trigger start condition, then the process moves into the ISR. I2C - * interrupts will be enabled within stm32wb_i2c_waitdone(). + * interrupts will be enabled within stm32_i2c_waitdone(). */ priv->status = 0; @@ -2126,17 +2126,17 @@ static int stm32wb_i2c_process(struct i2c_master_s *dev, /* Enable transmit and receive interrupts here so when we send the start * condition below the ISR will fire if the data was sent and some * response from the slave received. All other interrupts relevant to - * our needs are enabled in stm32wb_i2c_sem_waitdone() below. + * our needs are enabled in stm32_i2c_sem_waitdone() below. */ - stm32wb_i2c_enableinterrupts(priv); + stm32_i2c_enableinterrupts(priv); #endif /* Trigger START condition generation, which also sends the slave address * with read/write flag and the data in the first message */ - stm32wb_i2c_sendstart(priv); + stm32_i2c_sendstart(priv); /* Wait for the ISR to tell us that the transfer is complete by attempting * to grab the semaphore that is initially locked by the ISR. If the ISR @@ -2144,10 +2144,10 @@ static int stm32wb_i2c_process(struct i2c_master_s *dev, * the timeout period waitdone returns error and we report a timeout. */ - waitrc = stm32wb_i2c_sem_waitdone(priv); + waitrc = stm32_i2c_sem_waitdone(priv); - cr1 = stm32wb_i2c_getreg32(priv, STM32WB_I2C_CR1_OFFSET); - cr2 = stm32wb_i2c_getreg32(priv, STM32WB_I2C_CR2_OFFSET); + cr1 = stm32_i2c_getreg32(priv, STM32_I2C_CR1_OFFSET); + cr2 = stm32_i2c_getreg32(priv, STM32_I2C_CR2_OFFSET); #if !defined(CONFIG_DEBUG_I2C) UNUSED(cr1); UNUSED(cr2); @@ -2161,7 +2161,7 @@ static int stm32wb_i2c_process(struct i2c_master_s *dev, * like a NACK, so we reset the status field to include that information. */ - status = stm32wb_i2c_getstatus(priv); + status = stm32_i2c_getstatus(priv); /* The priv->status field can hold additional information like a NACK * event so we include that information. @@ -2266,7 +2266,7 @@ static int stm32wb_i2c_process(struct i2c_master_s *dev, /* This is not an error, but should not happen. The BUSY signal can be * present if devices on the bus are in an odd state and need to be reset. * NOTE: - * We will only see this busy indication if stm32wb_i2c_sem_waitdone() + * We will only see this busy indication if stm32_i2c_sem_waitdone() * fails above; Otherwise it is cleared. */ @@ -2276,7 +2276,7 @@ static int stm32wb_i2c_process(struct i2c_master_s *dev, * * This is a status condition rather than an error. * - * We will only see this busy indication if stm32wb_i2c_sem_waitdone() + * We will only see this busy indication if stm32_i2c_sem_waitdone() * fails above; Otherwise it is cleared by the hardware when the ISR * wraps up the transfer with a STOP condition. */ @@ -2284,7 +2284,7 @@ static int stm32wb_i2c_process(struct i2c_master_s *dev, clock_t start = clock_systime_ticks(); clock_t timeout = USEC2TICK(USEC_PER_SEC / priv->frequency) + 1; - status = stm32wb_i2c_getstatus(priv); + status = stm32_i2c_getstatus(priv); while (status & I2C_ISR_BUSY) { @@ -2295,27 +2295,27 @@ static int stm32wb_i2c_process(struct i2c_master_s *dev, break; } - status = stm32wb_i2c_getstatus(priv); + status = stm32_i2c_getstatus(priv); } } /* Dump the trace result */ - stm32wb_i2c_tracedump(priv); + stm32_i2c_tracedump(priv); nxmutex_unlock(&priv->lock); return -errval; } /**************************************************************************** - * Name: stm32wb_i2c_transfer + * Name: stm32_i2c_transfer * * Description: * Generic I2C transfer function * ****************************************************************************/ -static int stm32wb_i2c_transfer(struct i2c_master_s *dev, +static int stm32_i2c_transfer(struct i2c_master_s *dev, struct i2c_msg_s *msgs, int count) { @@ -2323,17 +2323,17 @@ static int stm32wb_i2c_transfer(struct i2c_master_s *dev, /* Ensure that address or flags don't change meanwhile */ - ret = nxmutex_lock(&((struct stm32wb_i2c_inst_s *)dev)->priv->lock); + ret = nxmutex_lock(&((struct stm32_i2c_inst_s *)dev)->priv->lock); if (ret >= 0) { - ret = stm32wb_i2c_process(dev, msgs, count); + ret = stm32_i2c_process(dev, msgs, count); } return ret; } /**************************************************************************** - * Name: stm32wb_i2c_reset + * Name: stm32_i2c_reset * * Description: * Reset an I2C bus @@ -2341,9 +2341,9 @@ static int stm32wb_i2c_transfer(struct i2c_master_s *dev, ****************************************************************************/ #ifdef CONFIG_I2C_RESET -static int stm32wb_i2c_reset(struct i2c_master_s * dev) +static int stm32_i2c_reset(struct i2c_master_s * dev) { - struct stm32wb_i2c_priv_s *priv; + struct stm32_i2c_priv_s *priv; unsigned int clock_count; unsigned int stretch_count; uint32_t scl_gpio; @@ -2355,7 +2355,7 @@ static int stm32wb_i2c_reset(struct i2c_master_s * dev) /* Get I2C private structure */ - priv = ((struct stm32wb_i2c_inst_s *)dev)->priv; + priv = ((struct stm32_i2c_inst_s *)dev)->priv; /* Our caller must own a ref */ @@ -2377,24 +2377,24 @@ static int stm32wb_i2c_reset(struct i2c_master_s * dev) /* De-init the port */ - stm32wb_i2c_deinit(priv); + stm32_i2c_deinit(priv); /* Use GPIO configuration to un-wedge the bus */ scl_gpio = MKI2C_OUTPUT(priv->config->scl_pin); sda_gpio = MKI2C_OUTPUT(priv->config->sda_pin); - stm32wb_configgpio(sda_gpio); - stm32wb_configgpio(scl_gpio); + stm32_configgpio(sda_gpio); + stm32_configgpio(scl_gpio); /* Let SDA go high */ - stm32wb_gpiowrite(sda_gpio, 1); + stm32_gpiowrite(sda_gpio, 1); /* Clock the bus until any slaves currently driving it let it go. */ clock_count = 0; - while (!stm32wb_gpioread(sda_gpio)) + while (!stm32_gpioread(sda_gpio)) { /* Give up if we have tried too hard */ @@ -2409,7 +2409,7 @@ static int stm32wb_i2c_reset(struct i2c_master_s * dev) */ stretch_count = 0; - while (!stm32wb_gpioread(scl_gpio)) + while (!stm32_gpioread(scl_gpio)) { /* Give up if we have tried too hard */ @@ -2423,12 +2423,12 @@ static int stm32wb_i2c_reset(struct i2c_master_s * dev) /* Drive SCL low */ - stm32wb_gpiowrite(scl_gpio, 0); + stm32_gpiowrite(scl_gpio, 0); up_udelay(10); /* Drive SCL high again */ - stm32wb_gpiowrite(scl_gpio, 1); + stm32_gpiowrite(scl_gpio, 1); up_udelay(10); } @@ -2436,27 +2436,27 @@ static int stm32wb_i2c_reset(struct i2c_master_s * dev) * state machines. */ - stm32wb_gpiowrite(sda_gpio, 0); + stm32_gpiowrite(sda_gpio, 0); up_udelay(10); - stm32wb_gpiowrite(scl_gpio, 0); + stm32_gpiowrite(scl_gpio, 0); up_udelay(10); - stm32wb_gpiowrite(scl_gpio, 1); + stm32_gpiowrite(scl_gpio, 1); up_udelay(10); - stm32wb_gpiowrite(sda_gpio, 1); + stm32_gpiowrite(sda_gpio, 1); up_udelay(10); /* Revert the GPIO configuration. */ - stm32wb_unconfiggpio(sda_gpio); - stm32wb_unconfiggpio(scl_gpio); + stm32_unconfiggpio(sda_gpio); + stm32_unconfiggpio(scl_gpio); /* Re-init the port */ - stm32wb_i2c_init(priv); + stm32_i2c_init(priv); /* Restore the frequency */ - stm32wb_i2c_setclock(priv, frequency); + stm32_i2c_setclock(priv, frequency); ret = OK; out: @@ -2469,7 +2469,7 @@ static int stm32wb_i2c_reset(struct i2c_master_s * dev) #endif /* CONFIG_I2C_RESET */ /**************************************************************************** - * Name: stm32wb_i2c_pm_prepare + * Name: stm32_i2c_pm_prepare * * Description: * Request the driver to prepare for a new power state. This is a @@ -2498,12 +2498,12 @@ static int stm32wb_i2c_reset(struct i2c_master_s * dev) ****************************************************************************/ #ifdef CONFIG_PM -static int stm32wb_i2c_pm_prepare(struct pm_callback_s *cb, int domain, +static int stm32_i2c_pm_prepare(struct pm_callback_s *cb, int domain, enum pm_state_e pmstate) { - struct stm32wb_i2c_priv_s *priv = - (struct stm32wb_i2c_priv_s *)((char *)cb - - offsetof(struct stm32wb_i2c_priv_s, pm_cb)); + struct stm32_i2c_priv_s *priv = + (struct stm32_i2c_priv_s *)((char *)cb - + offsetof(struct stm32_i2c_priv_s, pm_cb)); /* Logic to prepare for a reduced power state goes here. */ @@ -2545,30 +2545,30 @@ static int stm32wb_i2c_pm_prepare(struct pm_callback_s *cb, int domain, ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_i2cbus_initialize + * Name: stm32_i2cbus_initialize * * Description: * Initialize one I2C bus * ****************************************************************************/ -struct i2c_master_s *stm32wb_i2cbus_initialize(int port) +struct i2c_master_s *stm32_i2cbus_initialize(int port) { - struct stm32wb_i2c_priv_s *priv = NULL; /* private data of device with multiple instances */ - struct stm32wb_i2c_inst_s *inst = NULL; /* device, single instance */ + struct stm32_i2c_priv_s *priv = NULL; /* private data of device with multiple instances */ + struct stm32_i2c_inst_s *inst = NULL; /* device, single instance */ /* Get I2C private structure */ switch (port) { -#ifdef CONFIG_STM32WB_I2C1 +#ifdef CONFIG_STM32_I2C1 case 1: - priv = (struct stm32wb_i2c_priv_s *)&stm32wb_i2c1_priv; + priv = (struct stm32_i2c_priv_s *)&stm32_i2c1_priv; break; #endif -#ifdef CONFIG_STM32WB_I2C3 +#ifdef CONFIG_STM32_I2C3 case 3: - priv = (struct stm32wb_i2c_priv_s *)&stm32wb_i2c3_priv; + priv = (struct stm32_i2c_priv_s *)&stm32_i2c3_priv; break; #endif default: @@ -2577,14 +2577,14 @@ struct i2c_master_s *stm32wb_i2cbus_initialize(int port) /* Allocate instance */ - if (!(inst = kmm_malloc(sizeof(struct stm32wb_i2c_inst_s)))) + if (!(inst = kmm_malloc(sizeof(struct stm32_i2c_inst_s)))) { return NULL; } /* Initialize instance */ - inst->ops = &stm32wb_i2c_ops; + inst->ops = &stm32_i2c_ops; inst->priv = priv; /* Init private data for the first time, increment refs count, @@ -2594,7 +2594,7 @@ struct i2c_master_s *stm32wb_i2cbus_initialize(int port) nxmutex_lock(&priv->lock); if (priv->refs++ == 0) { - stm32wb_i2c_init(priv); + stm32_i2c_init(priv); #ifdef CONFIG_PM /* Register to receive power management callbacks */ @@ -2608,19 +2608,19 @@ struct i2c_master_s *stm32wb_i2cbus_initialize(int port) } /**************************************************************************** - * Name: stm32wb_i2cbus_uninitialize + * Name: stm32_i2cbus_uninitialize * * Description: * Uninitialize an I2C bus * ****************************************************************************/ -int stm32wb_i2cbus_uninitialize(struct i2c_master_s *dev) +int stm32_i2cbus_uninitialize(struct i2c_master_s *dev) { - struct stm32wb_i2c_priv_s *priv; + struct stm32_i2c_priv_s *priv; DEBUGASSERT(dev); - priv = ((struct stm32wb_i2c_inst_s *)dev)->priv; + priv = ((struct stm32_i2c_inst_s *)dev)->priv; /* Decrement refs and check for underflow */ @@ -2645,10 +2645,10 @@ int stm32wb_i2cbus_uninitialize(struct i2c_master_s *dev) /* Disable power and other HW resource (GPIO's) */ - stm32wb_i2c_deinit(priv); + stm32_i2c_deinit(priv); nxmutex_unlock(&priv->lock); kmm_free(dev); return OK; } -#endif /* CONFIG_STM32WB_I2C1 || CONFIG_STM32WB_I2C3 */ +#endif /* CONFIG_STM32_I2C1 || CONFIG_STM32_I2C3 */ diff --git a/arch/arm/src/stm32wb/stm32wb_i2c.h b/arch/arm/src/stm32wb/stm32wb_i2c.h index 3c9ea624557c7..af266f5ff02a4 100644 --- a/arch/arm/src/stm32wb/stm32wb_i2c.h +++ b/arch/arm/src/stm32wb/stm32wb_i2c.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32WB_STM32WB_I2C_H -#define __ARCH_ARM_SRC_STM32WB_STM32WB_I2C_H +#ifndef __ARCH_ARM_SRC_STM32WB_STM32_I2C_H +#define __ARCH_ARM_SRC_STM32WB_STM32_I2C_H /**************************************************************************** * Included Files @@ -41,10 +41,10 @@ * seconds per byte value must be provided as well. */ -#ifdef CONFIG_STM32WB_I2C_DYNTIMEO -# if CONFIG_STM32WB_I2C_DYNTIMEO_USECPERBYTE < 1 -# warning "Ignoring CONFIG_STM32WB_I2C_DYNTIMEO because of CONFIG_STM32WB_I2C_DYNTIMEO_USECPERBYTE" -# undef CONFIG_STM32WB_I2C_DYNTIMEO +#ifdef CONFIG_STM32_I2C_DYNTIMEO +# if CONFIG_STM32_I2C_DYNTIMEO_USECPERBYTE < 1 +# warning "Ignoring CONFIG_STM32_I2C_DYNTIMEO because of CONFIG_STM32_I2C_DYNTIMEO_USECPERBYTE" +# undef CONFIG_STM32_I2C_DYNTIMEO # endif #endif @@ -53,7 +53,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_i2cbus_initialize + * Name: stm32_i2cbus_initialize * * Description: * Initialize the selected I2C port. And return a unique instance of struct @@ -69,16 +69,16 @@ * ****************************************************************************/ -struct i2c_master_s *stm32wb_i2cbus_initialize(int port); +struct i2c_master_s *stm32_i2cbus_initialize(int port); /**************************************************************************** - * Name: stm32wb_i2cbus_uninitialize + * Name: stm32_i2cbus_uninitialize * * Description: * De-initialize the selected I2C port, and power down the device. * * Input Parameters: - * Device structure as returned by the stm32wb_i2cbus_initialize() + * Device structure as returned by the stm32_i2cbus_initialize() * * Returned Value: * OK on success, ERROR when internal reference count mismatch or dev @@ -86,6 +86,6 @@ struct i2c_master_s *stm32wb_i2cbus_initialize(int port); * ****************************************************************************/ -int stm32wb_i2cbus_uninitialize(struct i2c_master_s *dev); +int stm32_i2cbus_uninitialize(struct i2c_master_s *dev); -#endif /* __ARCH_ARM_SRC_STM32WB_STM32WB_I2C_H */ +#endif /* __ARCH_ARM_SRC_STM32WB_STM32_I2C_H */ diff --git a/arch/arm/src/stm32wb/stm32wb_idle.c b/arch/arm/src/stm32wb/stm32wb_idle.c index 977ff2970939a..4001f8210e593 100644 --- a/arch/arm/src/stm32wb/stm32wb_idle.c +++ b/arch/arm/src/stm32wb/stm32wb_idle.c @@ -119,12 +119,12 @@ static void up_idlepm(void) /* Enter STOP mode */ BEGIN_IDLE(); - stm32wb_pmstop(true); + stm32_pmstop(true); END_IDLE(); /* Set correct clock again after returning from STOP */ - stm32wb_clockenable(); + stm32_clockenable(); /* Inform of all drivers of the new state */ @@ -137,7 +137,7 @@ static void up_idlepm(void) break; case PM_SLEEP: - stm32wb_pmstandby(); + stm32_pmstandby(); break; default: @@ -184,7 +184,7 @@ void up_idle(void) /* Sleep until an interrupt occurs to save power. */ -#if !(defined(CONFIG_DEBUG_SYMBOLS) && defined(CONFIG_STM32WB_DISABLE_IDLE_SLEEP_DURING_DEBUG)) +#if !(defined(CONFIG_DEBUG_SYMBOLS) && defined(CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG)) BEGIN_IDLE(); __asm__ volatile ("wfi"); END_IDLE(); diff --git a/arch/arm/src/stm32wb/stm32wb_ipcc.c b/arch/arm/src/stm32wb/stm32wb_ipcc.c index a9999bdcd12c2..c9b889aec9a02 100644 --- a/arch/arm/src/stm32wb/stm32wb_ipcc.c +++ b/arch/arm/src/stm32wb/stm32wb_ipcc.c @@ -40,71 +40,71 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_ipccreset + * Name: stm32_ipccreset * * Description: * Reset the IPCC registers to default state * ****************************************************************************/ -void stm32wb_ipccreset(void) +void stm32_ipccreset(void) { uint32_t regval; /* Disable CPU1 IPCC interrupts */ - putreg32(0x00000000, STM32WB_IPCC_C1CR); + putreg32(0x00000000, STM32_IPCC_C1CR); /* Clear CPU1 IPCC receive channel status */ - putreg32(IPCC_C1SCR_CLR_MASK, STM32WB_IPCC_C1SCR); + putreg32(IPCC_C1SCR_CLR_MASK, STM32_IPCC_C1SCR); /* Clear CPU2 IPCC receive channel status */ - putreg32(IPCC_C2SCR_CLR_MASK, STM32WB_IPCC_C2SCR); + putreg32(IPCC_C2SCR_CLR_MASK, STM32_IPCC_C2SCR); /* Disable CPU1 transmit/receive channels */ - regval = getreg32(STM32WB_IPCC_C1MR); + regval = getreg32(STM32_IPCC_C1MR); regval |= IPCC_C1MR_OM_MASK | IPCC_C1MR_FM_MASK; - putreg32(regval, STM32WB_IPCC_C1MR); + putreg32(regval, STM32_IPCC_C1MR); /* Disable CPU2 transmit/receive channels */ - regval = getreg32(STM32WB_IPCC_C2MR); + regval = getreg32(STM32_IPCC_C2MR); regval |= IPCC_C2MR_OM_MASK | IPCC_C2MR_FM_MASK; - putreg32(regval, STM32WB_IPCC_C2MR); + putreg32(regval, STM32_IPCC_C2MR); } /**************************************************************************** - * Name: stm32wb_ipccenable + * Name: stm32_ipccenable * * Description: * Enable the IPCC and start CPU2 * ****************************************************************************/ -void stm32wb_ipccenable(void) +void stm32_ipccenable(void) { uint32_t regval; /* CPU2 IPCC clock enable */ - regval = getreg32(STM32WB_RCC_C2AHB3ENR); + regval = getreg32(STM32_RCC_C2AHB3ENR); regval |= RCC_C2AHB3ENR_IPCCEN; - putreg32(regval, STM32WB_RCC_C2AHB3ENR); + putreg32(regval, STM32_RCC_C2AHB3ENR); /* Enable EXTI event request for C1SEV interrupt to CPU2 */ - regval = getreg32(STM32WB_EXTI_C2EMR2); + regval = getreg32(STM32_EXTI_C2EMR2); regval |= EXTI_C2EMR2_EM(EXTI_EVT_C1SEV); - putreg32(regval, STM32WB_EXTI_C2EMR2); + putreg32(regval, STM32_EXTI_C2EMR2); /* Enable EXTI rising edge trigger for C1SEV interrupt to CPU2 */ - regval = getreg32(STM32WB_EXTI_RTSR2); + regval = getreg32(STM32_EXTI_RTSR2); regval |= EXTI_RTSR2_RT(EXTI_EVT_C1SEV); - putreg32(regval, STM32WB_EXTI_RTSR2); + putreg32(regval, STM32_EXTI_RTSR2); /* Set the internal event flag and send an event to CPU2 */ @@ -116,7 +116,7 @@ void stm32wb_ipccenable(void) /* Boot CPU2 after reset or wakeup from stop or standby modes */ - regval = getreg32(STM32WB_PWR_CR4); + regval = getreg32(STM32_PWR_CR4); regval |= PWR_CR4_C2BOOT; - putreg32(regval, STM32WB_PWR_CR4); + putreg32(regval, STM32_PWR_CR4); } diff --git a/arch/arm/src/stm32wb/stm32wb_ipcc.h b/arch/arm/src/stm32wb/stm32wb_ipcc.h index 1d8ae70afa55b..e492c24e7f972 100644 --- a/arch/arm/src/stm32wb/stm32wb_ipcc.h +++ b/arch/arm/src/stm32wb/stm32wb_ipcc.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32WB_STM32WB_IPCC_H -#define __ARCH_ARM_SRC_STM32WB_STM32WB_IPCC_H +#ifndef __ARCH_ARM_SRC_STM32WB_STM32_IPCC_H +#define __ARCH_ARM_SRC_STM32WB_STM32_IPCC_H /**************************************************************************** * Included Files @@ -55,126 +55,126 @@ extern "C" ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_ipccreset + * Name: stm32_ipccreset * * Description: * Reset the IPCC registers to default state * ****************************************************************************/ -void stm32wb_ipccreset(void); +void stm32_ipccreset(void); /**************************************************************************** - * Name: stm32wb_ipccenable + * Name: stm32_ipccenable * * Description: * Enable the IPCC and start CPU2 * ****************************************************************************/ -void stm32wb_ipccenable(void); +void stm32_ipccenable(void); /**************************************************************************** * Inline Functions ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_ipcc_rxactive + * Name: stm32_ipcc_rxactive * * Description: * Check channel receive active flag. * ****************************************************************************/ -static inline bool stm32wb_ipcc_rxactive(uint8_t chan) +static inline bool stm32_ipcc_rxactive(uint8_t chan) { - return (getreg32(STM32WB_IPCC_C2TOC1SR) & IPCC_C2TOC1SR_BIT(chan)) != 0; + return (getreg32(STM32_IPCC_C2TOC1SR) & IPCC_C2TOC1SR_BIT(chan)) != 0; } /**************************************************************************** - * Name: stm32wb_ipcc_txactive + * Name: stm32_ipcc_txactive * * Description: * Check channel transmit active flag. * ****************************************************************************/ -static inline bool stm32wb_ipcc_txactive(uint8_t chan) +static inline bool stm32_ipcc_txactive(uint8_t chan) { - return (getreg32(STM32WB_IPCC_C1TOC2SR) & IPCC_C1TOC2SR_BIT(chan)) != 0; + return (getreg32(STM32_IPCC_C1TOC2SR) & IPCC_C1TOC2SR_BIT(chan)) != 0; } /**************************************************************************** - * Name: stm32wb_ipcc_settxactive + * Name: stm32_ipcc_settxactive * * Description: * Set channel transmit active flag. * ****************************************************************************/ -static inline void stm32wb_ipcc_settxactive(uint8_t chan) +static inline void stm32_ipcc_settxactive(uint8_t chan) { - putreg32(IPCC_C1SCR_SET_BIT(chan), STM32WB_IPCC_C1SCR); + putreg32(IPCC_C1SCR_SET_BIT(chan), STM32_IPCC_C1SCR); } /**************************************************************************** - * Name: stm32wb_ipcc_masktxf + * Name: stm32_ipcc_masktxf * * Description: * Mask channel transmit free interrupt. * ****************************************************************************/ -static inline void stm32wb_ipcc_masktxf(uint8_t chan) +static inline void stm32_ipcc_masktxf(uint8_t chan) { - uint32_t regval = getreg32(STM32WB_IPCC_C1MR); + uint32_t regval = getreg32(STM32_IPCC_C1MR); regval |= IPCC_C1MR_FM_BIT(chan); - putreg32(regval, STM32WB_IPCC_C1MR); + putreg32(regval, STM32_IPCC_C1MR); } /**************************************************************************** - * Name: stm32wb_ipcc_unmasktxf + * Name: stm32_ipcc_unmasktxf * * Description: * Unmask channel transmit free interrupt. * ****************************************************************************/ -static inline void stm32wb_ipcc_unmasktxf(uint8_t chan) +static inline void stm32_ipcc_unmasktxf(uint8_t chan) { - uint32_t regval = getreg32(STM32WB_IPCC_C1MR); + uint32_t regval = getreg32(STM32_IPCC_C1MR); regval &= ~IPCC_C1MR_FM_BIT(chan); - putreg32(regval, STM32WB_IPCC_C1MR); + putreg32(regval, STM32_IPCC_C1MR); } /**************************************************************************** - * Name: stm32wb_ipcc_maskrxo + * Name: stm32_ipcc_maskrxo * * Description: * Mask channel receive occupied interrupt. * ****************************************************************************/ -static inline void stm32wb_ipcc_maskrxo(uint8_t chan) +static inline void stm32_ipcc_maskrxo(uint8_t chan) { - uint32_t regval = getreg32(STM32WB_IPCC_C1MR); + uint32_t regval = getreg32(STM32_IPCC_C1MR); regval |= IPCC_C1MR_OM_BIT(chan); - putreg32(regval, STM32WB_IPCC_C1MR); + putreg32(regval, STM32_IPCC_C1MR); } /**************************************************************************** - * Name: stm32wb_ipcc_maskrxo + * Name: stm32_ipcc_maskrxo * * Description: * Unmask channel receive occupied interrupt. * ****************************************************************************/ -static inline void stm32wb_ipcc_unmaskrxo(uint8_t chan) +static inline void stm32_ipcc_unmaskrxo(uint8_t chan) { - uint32_t regval = getreg32(STM32WB_IPCC_C1MR); + uint32_t regval = getreg32(STM32_IPCC_C1MR); regval &= ~IPCC_C1MR_OM_BIT(chan); - putreg32(regval, STM32WB_IPCC_C1MR); + putreg32(regval, STM32_IPCC_C1MR); } #undef EXTERN @@ -183,4 +183,4 @@ static inline void stm32wb_ipcc_unmaskrxo(uint8_t chan) #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32WB_STM32WB_IPCC_H */ +#endif /* __ARCH_ARM_SRC_STM32WB_STM32_IPCC_H */ diff --git a/arch/arm/src/stm32wb/stm32wb_irq.c b/arch/arm/src/stm32wb/stm32wb_irq.c index 9b06b2bd709a4..d03886cee305c 100644 --- a/arch/arm/src/stm32wb/stm32wb_irq.c +++ b/arch/arm/src/stm32wb/stm32wb_irq.c @@ -65,7 +65,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_dumpnvic + * Name: stm32_dumpnvic * * Description: * Dump some interesting NVIC registers @@ -73,7 +73,7 @@ ****************************************************************************/ #if defined(CONFIG_DEBUG_IRQ_INFO) -static void stm32wb_dumpnvic(const char *msg, int irq) +static void stm32_dumpnvic(const char *msg, int irq) { irqstate_t flags; @@ -129,11 +129,11 @@ static void stm32wb_dumpnvic(const char *msg, int irq) leave_critical_section(flags); } #else -# define stm32wb_dumpnvic(msg, irq) +# define stm32_dumpnvic(msg, irq) #endif /**************************************************************************** - * Name: stm32wb_nmi, stm32wb_pendsv,stm32wb_pendsv, stm32wb_reserved + * Name: stm32_nmi, stm32_pendsv,stm32_pendsv, stm32_reserved * * Description: * Handlers for various exceptions. None are handled and all are fatal @@ -143,7 +143,7 @@ static void stm32wb_dumpnvic(const char *msg, int irq) ****************************************************************************/ #ifdef CONFIG_DEBUG_FEATURES -static int stm32wb_nmi(int irq, void *context, void *arg) +static int stm32_nmi(int irq, void *context, void *arg) { up_irq_save(); _err("PANIC!!! NMI received\n"); @@ -151,7 +151,7 @@ static int stm32wb_nmi(int irq, void *context, void *arg) return 0; } -static int stm32wb_pendsv(int irq, void *context, void *arg) +static int stm32_pendsv(int irq, void *context, void *arg) { up_irq_save(); _err("PANIC!!! PendSV received\n"); @@ -159,7 +159,7 @@ static int stm32wb_pendsv(int irq, void *context, void *arg) return 0; } -static int stm32wb_reserved(int irq, void *context, void *arg) +static int stm32_reserved(int irq, void *context, void *arg) { up_irq_save(); _err("PANIC!!! Reserved interrupt\n"); @@ -169,7 +169,7 @@ static int stm32wb_reserved(int irq, void *context, void *arg) #endif /**************************************************************************** - * Name: stm32wb_prioritize_syscall + * Name: stm32_prioritize_syscall * * Description: * Set the priority of an exception. This function may be needed @@ -177,7 +177,7 @@ static int stm32wb_reserved(int irq, void *context, void *arg) * ****************************************************************************/ -static inline void stm32wb_prioritize_syscall(int priority) +static inline void stm32_prioritize_syscall(int priority) { uint32_t regval; @@ -190,7 +190,7 @@ static inline void stm32wb_prioritize_syscall(int priority) } /**************************************************************************** - * Name: stm32wb_irqinfo + * Name: stm32_irqinfo * * Description: * Given an IRQ number, provide the register and bit setting to enable or @@ -198,18 +198,18 @@ static inline void stm32wb_prioritize_syscall(int priority) * ****************************************************************************/ -static int stm32wb_irqinfo(int irq, uintptr_t *regaddr, uint32_t *bit, +static int stm32_irqinfo(int irq, uintptr_t *regaddr, uint32_t *bit, uintptr_t offset) { int n; - DEBUGASSERT(irq >= STM32WB_IRQ_NMI && irq < NR_IRQS); + DEBUGASSERT(irq >= STM32_IRQ_NMI && irq < NR_IRQS); /* Check for external interrupt */ - if (irq >= STM32WB_IRQ_FIRST) + if (irq >= STM32_IRQ_FIRST) { - n = irq - STM32WB_IRQ_FIRST; + n = irq - STM32_IRQ_FIRST; *regaddr = NVIC_IRQ_ENABLE(n) + offset; *bit = (uint32_t)1 << (n & 0x1f); } @@ -219,19 +219,19 @@ static int stm32wb_irqinfo(int irq, uintptr_t *regaddr, uint32_t *bit, else { *regaddr = NVIC_SYSHCON; - if (irq == STM32WB_IRQ_MEMFAULT) + if (irq == STM32_IRQ_MEMFAULT) { *bit = NVIC_SYSHCON_MEMFAULTENA; } - else if (irq == STM32WB_IRQ_BUSFAULT) + else if (irq == STM32_IRQ_BUSFAULT) { *bit = NVIC_SYSHCON_BUSFAULTENA; } - else if (irq == STM32WB_IRQ_USAGEFAULT) + else if (irq == STM32_IRQ_USAGEFAULT) { *bit = NVIC_SYSHCON_USGFAULTENA; } - else if (irq == STM32WB_IRQ_SYSTICK) + else if (irq == STM32_IRQ_SYSTICK) { *regaddr = NVIC_SYSTICK_CTRL; *bit = NVIC_SYSTICK_CTRL_ENABLE; @@ -261,7 +261,7 @@ void up_irqinitialize(void) /* Disable all interrupts */ - for (i = 0; i < NR_IRQS - STM32WB_IRQ_FIRST; i += 32) + for (i = 0; i < NR_IRQS - STM32_IRQ_FIRST; i += 32) { putreg32(0xffffffff, NVIC_IRQ_CLEAR(i)); } @@ -319,42 +319,42 @@ void up_irqinitialize(void) * under certain conditions. */ - irq_attach(STM32WB_IRQ_SVCALL, arm_svcall, NULL); - irq_attach(STM32WB_IRQ_HARDFAULT, arm_hardfault, NULL); + irq_attach(STM32_IRQ_SVCALL, arm_svcall, NULL); + irq_attach(STM32_IRQ_HARDFAULT, arm_hardfault, NULL); /* Set the priority of the SVCall interrupt */ #ifdef CONFIG_ARCH_IRQPRIO - /* up_prioritize_irq(STM32WB_IRQ_PENDSV, NVIC_SYSH_PRIORITY_MIN); */ + /* up_prioritize_irq(STM32_IRQ_PENDSV, NVIC_SYSH_PRIORITY_MIN); */ #endif - stm32wb_prioritize_syscall(NVIC_SYSH_SVCALL_PRIORITY); + stm32_prioritize_syscall(NVIC_SYSH_SVCALL_PRIORITY); /* If the MPU is enabled, then attach and enable the Memory Management * Fault handler. */ #ifdef CONFIG_ARM_MPU - irq_attach(STM32WB_IRQ_MEMFAULT, arm_memfault, NULL); - up_enable_irq(STM32WB_IRQ_MEMFAULT); + irq_attach(STM32_IRQ_MEMFAULT, arm_memfault, NULL); + up_enable_irq(STM32_IRQ_MEMFAULT); #endif /* Attach all other processor exceptions (except reset and sys tick) */ #ifdef CONFIG_DEBUG_FEATURES - irq_attach(STM32WB_IRQ_NMI, stm32wb_nmi, NULL); + irq_attach(STM32_IRQ_NMI, stm32_nmi, NULL); #ifndef CONFIG_ARM_MPU - irq_attach(STM32WB_IRQ_MEMFAULT, arm_memfault, NULL); + irq_attach(STM32_IRQ_MEMFAULT, arm_memfault, NULL); #endif - irq_attach(STM32WB_IRQ_BUSFAULT, arm_busfault, NULL); - irq_attach(STM32WB_IRQ_USAGEFAULT, arm_usagefault, NULL); - irq_attach(STM32WB_IRQ_PENDSV, stm32wb_pendsv, NULL); + irq_attach(STM32_IRQ_BUSFAULT, arm_busfault, NULL); + irq_attach(STM32_IRQ_USAGEFAULT, arm_usagefault, NULL); + irq_attach(STM32_IRQ_PENDSV, stm32_pendsv, NULL); arm_enable_dbgmonitor(); - irq_attach(STM32WB_IRQ_DBGMONITOR, arm_dbgmonitor, NULL); - irq_attach(STM32WB_IRQ_RESERVED, stm32wb_reserved, NULL); + irq_attach(STM32_IRQ_DBGMONITOR, arm_dbgmonitor, NULL); + irq_attach(STM32_IRQ_RESERVED, stm32_reserved, NULL); #endif - stm32wb_dumpnvic("initial", NR_IRQS); + stm32_dumpnvic("initial", NR_IRQS); #ifndef CONFIG_SUPPRESS_INTERRUPTS @@ -379,7 +379,7 @@ void up_disable_irq(int irq) uint32_t regval; uint32_t bit; - if (stm32wb_irqinfo(irq, ®addr, &bit, NVIC_CLRENA_OFFSET) == 0) + if (stm32_irqinfo(irq, ®addr, &bit, NVIC_CLRENA_OFFSET) == 0) { /* Modify the appropriate bit in the register to disable the interrupt. * For normal interrupts, we need to set the bit in the associated @@ -387,7 +387,7 @@ void up_disable_irq(int irq) * clear the bit in the System Handler Control and State Register. */ - if (irq >= STM32WB_IRQ_FIRST) + if (irq >= STM32_IRQ_FIRST) { putreg32(bit, regaddr); } @@ -414,7 +414,7 @@ void up_enable_irq(int irq) uint32_t regval; uint32_t bit; - if (stm32wb_irqinfo(irq, ®addr, &bit, NVIC_ENA_OFFSET) == 0) + if (stm32_irqinfo(irq, ®addr, &bit, NVIC_ENA_OFFSET) == 0) { /* Modify the appropriate bit in the register to enable the interrupt. * For normal interrupts, we need to set the bit in the associated @@ -422,7 +422,7 @@ void up_enable_irq(int irq) * set the bit in the System Handler Control and State Register. */ - if (irq >= STM32WB_IRQ_FIRST) + if (irq >= STM32_IRQ_FIRST) { putreg32(bit, regaddr); } @@ -465,10 +465,10 @@ int up_prioritize_irq(int irq, int priority) uint32_t regval; int shift; - DEBUGASSERT(irq >= STM32WB_IRQ_MEMFAULT && irq < NR_IRQS && + DEBUGASSERT(irq >= STM32_IRQ_MEMFAULT && irq < NR_IRQS && (unsigned)priority <= NVIC_SYSH_PRIORITY_MIN); - if (irq < STM32WB_IRQ_FIRST) + if (irq < STM32_IRQ_FIRST) { /* NVIC_SYSH_PRIORITY() maps {0..15} to one of three priority * registers (0-3 are invalid) @@ -481,7 +481,7 @@ int up_prioritize_irq(int irq, int priority) { /* NVIC_IRQ_PRIORITY() maps {0..} to one of many priority registers */ - irq -= STM32WB_IRQ_FIRST; + irq -= STM32_IRQ_FIRST; regaddr = NVIC_IRQ_PRIORITY(irq); } @@ -491,7 +491,7 @@ int up_prioritize_irq(int irq, int priority) regval |= (priority << shift); putreg32(regval, regaddr); - stm32wb_dumpnvic("prioritize", irq); + stm32_dumpnvic("prioritize", irq); return OK; } #endif diff --git a/arch/arm/src/stm32wb/stm32wb_lowputc.c b/arch/arm/src/stm32wb/stm32wb_lowputc.c index 7d73b1afd13c3..9175c37cffddf 100644 --- a/arch/arm/src/stm32wb/stm32wb_lowputc.c +++ b/arch/arm/src/stm32wb/stm32wb_lowputc.c @@ -32,7 +32,7 @@ #include "arm_internal.h" #include "chip.h" -#include "stm32wb.h" +#include "stm32.h" #include "stm32wb_rcc.h" #include "stm32wb_gpio.h" #include "stm32wb_uart.h" @@ -45,51 +45,51 @@ #ifdef HAVE_CONSOLE # if defined(CONFIG_LPUART1_SERIAL_CONSOLE) -# define STM32WB_CONSOLE_BASE STM32WB_LPUART1_BASE -# define STM32WB_APBCLOCK STM32WB_PCLK1_FREQUENCY -# define STM32WB_CONSOLE_APBREG STM32WB_RCC_APB1ENR2 -# define STM32WB_CONSOLE_APBEN RCC_APB1ENR2_LPUART1EN -# define STM32WB_CONSOLE_BAUD CONFIG_LPUART1_BAUD -# define STM32WB_CONSOLE_BITS CONFIG_LPUART1_BITS -# define STM32WB_CONSOLE_PARITY CONFIG_LPUART1_PARITY -# define STM32WB_CONSOLE_2STOP CONFIG_LPUART1_2STOP -# define STM32WB_CONSOLE_TX GPIO_LPUART1_TX -# define STM32WB_CONSOLE_RX GPIO_LPUART1_RX +# define STM32_CONSOLE_BASE STM32_LPUART1_BASE +# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY +# define STM32_CONSOLE_APBREG STM32_RCC_APB1ENR2 +# define STM32_CONSOLE_APBEN RCC_APB1ENR2_LPUART1EN +# define STM32_CONSOLE_BAUD CONFIG_LPUART1_BAUD +# define STM32_CONSOLE_BITS CONFIG_LPUART1_BITS +# define STM32_CONSOLE_PARITY CONFIG_LPUART1_PARITY +# define STM32_CONSOLE_2STOP CONFIG_LPUART1_2STOP +# define STM32_CONSOLE_TX GPIO_LPUART1_TX +# define STM32_CONSOLE_RX GPIO_LPUART1_RX # ifdef CONFIG_LPUART1_RS485 -# define STM32WB_CONSOLE_RS485_DIR GPIO_LPUART1_RS485_DIR +# define STM32_CONSOLE_RS485_DIR GPIO_LPUART1_RS485_DIR # if (CONFIG_LPUART1_RS485_DIR_POLARITY == 0) -# define STM32WB_CONSOLE_RS485_DIR_POLARITY false +# define STM32_CONSOLE_RS485_DIR_POLARITY false # else -# define STM32WB_CONSOLE_RS485_DIR_POLARITY true +# define STM32_CONSOLE_RS485_DIR_POLARITY true # endif # endif # elif defined(CONFIG_USART1_SERIAL_CONSOLE) -# define STM32WB_CONSOLE_BASE STM32WB_USART1_BASE -# define STM32WB_APBCLOCK STM32WB_PCLK2_FREQUENCY -# define STM32WB_CONSOLE_APBREG STM32WB_RCC_APB2ENR -# define STM32WB_CONSOLE_APBEN RCC_APB2ENR_USART1EN -# define STM32WB_CONSOLE_BAUD CONFIG_USART1_BAUD -# define STM32WB_CONSOLE_BITS CONFIG_USART1_BITS -# define STM32WB_CONSOLE_PARITY CONFIG_USART1_PARITY -# define STM32WB_CONSOLE_2STOP CONFIG_USART1_2STOP -# define STM32WB_CONSOLE_TX GPIO_USART1_TX -# define STM32WB_CONSOLE_RX GPIO_USART1_RX +# define STM32_CONSOLE_BASE STM32_USART1_BASE +# define STM32_APBCLOCK STM32_PCLK2_FREQUENCY +# define STM32_CONSOLE_APBREG STM32_RCC_APB2ENR +# define STM32_CONSOLE_APBEN RCC_APB2ENR_USART1EN +# define STM32_CONSOLE_BAUD CONFIG_USART1_BAUD +# define STM32_CONSOLE_BITS CONFIG_USART1_BITS +# define STM32_CONSOLE_PARITY CONFIG_USART1_PARITY +# define STM32_CONSOLE_2STOP CONFIG_USART1_2STOP +# define STM32_CONSOLE_TX GPIO_USART1_TX +# define STM32_CONSOLE_RX GPIO_USART1_RX # ifdef CONFIG_USART1_RS485 -# define STM32WB_CONSOLE_RS485_DIR GPIO_USART1_RS485_DIR +# define STM32_CONSOLE_RS485_DIR GPIO_USART1_RS485_DIR # if (CONFIG_USART1_RS485_DIR_POLARITY == 0) -# define STM32WB_CONSOLE_RS485_DIR_POLARITY false +# define STM32_CONSOLE_RS485_DIR_POLARITY false # else -# define STM32WB_CONSOLE_RS485_DIR_POLARITY true +# define STM32_CONSOLE_RS485_DIR_POLARITY true # endif # endif # endif /* CR1 settings */ -# if STM32WB_CONSOLE_BITS == 9 +# if STM32_CONSOLE_BITS == 9 # define USART_CR1_M0_VALUE USART_CR1_M0 # define USART_CR1_M1_VALUE 0 -# elif STM32WB_CONSOLE_BITS == 7 +# elif STM32_CONSOLE_BITS == 7 # define USART_CR1_M0_VALUE 0 # define USART_CR1_M1_VALUE USART_CR1_M1 # else /* 8 bits */ @@ -97,9 +97,9 @@ # define USART_CR1_M1_VALUE 0 # endif -# if STM32WB_CONSOLE_PARITY == 1 /* odd parity */ +# if STM32_CONSOLE_PARITY == 1 /* odd parity */ # define USART_CR1_PARITY_VALUE (USART_CR1_PCE|USART_CR1_PS) -# elif STM32WB_CONSOLE_PARITY == 2 /* even parity */ +# elif STM32_CONSOLE_PARITY == 2 /* even parity */ # define USART_CR1_PARITY_VALUE USART_CR1_PCE # else /* no parity */ # define USART_CR1_PARITY_VALUE 0 @@ -115,7 +115,7 @@ /* CR2 settings */ -# if STM32WB_CONSOLE_2STOP != 0 +# if STM32_CONSOLE_2STOP != 0 # define USART_CR2_STOP2_VALUE USART_CR2_STOP2 # else # define USART_CR2_STOP2_VALUE 0 @@ -157,19 +157,19 @@ * UARTDIV = 2 * fCK / baud */ -# define STM32WB_USARTDIV8 \ - (((STM32WB_APBCLOCK << 1) + (STM32WB_CONSOLE_BAUD >> 1)) / STM32WB_CONSOLE_BAUD) -# define STM32WB_USARTDIV16 \ - ((STM32WB_APBCLOCK + (STM32WB_CONSOLE_BAUD >> 1)) / STM32WB_CONSOLE_BAUD) +# define STM32_USARTDIV8 \ + (((STM32_APBCLOCK << 1) + (STM32_CONSOLE_BAUD >> 1)) / STM32_CONSOLE_BAUD) +# define STM32_USARTDIV16 \ + ((STM32_APBCLOCK + (STM32_CONSOLE_BAUD >> 1)) / STM32_CONSOLE_BAUD) /* Use oversamply by 8 only if the divisor is small. But what is small? */ -# if STM32WB_USARTDIV8 > 100 -# define STM32WB_BRR_VALUE STM32WB_USARTDIV16 +# if STM32_USARTDIV8 > 100 +# define STM32_BRR_VALUE STM32_USARTDIV16 # else # define USE_OVER8 1 -# define STM32WB_BRR_VALUE \ - ((STM32WB_USARTDIV8 & 0xfff0) | ((STM32WB_USARTDIV8 & 0x000f) >> 1)) +# define STM32_BRR_VALUE \ + ((STM32_USARTDIV8 & 0xfff0) | ((STM32_USARTDIV8 & 0x000f) >> 1)) # endif #endif /* HAVE_CONSOLE */ @@ -211,29 +211,29 @@ void arm_lowputc(char ch) #ifdef HAVE_CONSOLE /* Wait until the TX data register is empty */ - while ((getreg32(STM32WB_CONSOLE_BASE + STM32WB_USART_ISR_OFFSET) & + while ((getreg32(STM32_CONSOLE_BASE + STM32_USART_ISR_OFFSET) & USART_ISR_TXE) == 0); -#ifdef STM32WB_CONSOLE_RS485_DIR - stm32wb_gpiowrite(STM32WB_CONSOLE_RS485_DIR, - STM32WB_CONSOLE_RS485_DIR_POLARITY); +#ifdef STM32_CONSOLE_RS485_DIR + stm32_gpiowrite(STM32_CONSOLE_RS485_DIR, + STM32_CONSOLE_RS485_DIR_POLARITY); #endif /* Then send the character */ - putreg32((uint32_t)ch, STM32WB_CONSOLE_BASE + STM32WB_USART_TDR_OFFSET); + putreg32((uint32_t)ch, STM32_CONSOLE_BASE + STM32_USART_TDR_OFFSET); -#ifdef STM32WB_CONSOLE_RS485_DIR - while ((getreg32(STM32WB_CONSOLE_BASE + STM32WB_USART_ISR_OFFSET) & +#ifdef STM32_CONSOLE_RS485_DIR + while ((getreg32(STM32_CONSOLE_BASE + STM32_USART_ISR_OFFSET) & USART_ISR_TC) == 0); - stm32wb_gpiowrite(STM32WB_CONSOLE_RS485_DIR, - !STM32WB_CONSOLE_RS485_DIR_POLARITY); + stm32_gpiowrite(STM32_CONSOLE_RS485_DIR, + !STM32_CONSOLE_RS485_DIR_POLARITY); #endif #endif /* HAVE_CONSOLE */ } /**************************************************************************** - * Name: stm32wb_lowsetup + * Name: stm32_lowsetup * * Description: * This performs basic initialization of the USART used for the serial @@ -242,7 +242,7 @@ void arm_lowputc(char ch) * ****************************************************************************/ -void stm32wb_lowsetup(void) +void stm32_lowsetup(void) { #if defined(HAVE_UART) #if defined(HAVE_CONSOLE) && !defined(CONFIG_SUPPRESS_UART_CONFIG) @@ -252,26 +252,26 @@ void stm32wb_lowsetup(void) #if defined(HAVE_CONSOLE) /* Enable USART APB1/2 clock */ - modifyreg32(STM32WB_CONSOLE_APBREG, 0, STM32WB_CONSOLE_APBEN); + modifyreg32(STM32_CONSOLE_APBREG, 0, STM32_CONSOLE_APBEN); #endif /* Enable the console USART and configure GPIO pins needed for rx/tx. * * NOTE: Clocking for selected U[S]ARTs was already provided in - * stm32wb_rcc.c + * stm32_rcc.c */ -#ifdef STM32WB_CONSOLE_TX - stm32wb_configgpio(STM32WB_CONSOLE_TX); +#ifdef STM32_CONSOLE_TX + stm32_configgpio(STM32_CONSOLE_TX); #endif -#ifdef STM32WB_CONSOLE_RX - stm32wb_configgpio(STM32WB_CONSOLE_RX); +#ifdef STM32_CONSOLE_RX + stm32_configgpio(STM32_CONSOLE_RX); #endif -#ifdef STM32WB_CONSOLE_RS485_DIR - stm32wb_configgpio(STM32WB_CONSOLE_RS485_DIR); - stm32wb_gpiowrite(STM32WB_CONSOLE_RS485_DIR, - !STM32WB_CONSOLE_RS485_DIR_POLARITY); +#ifdef STM32_CONSOLE_RS485_DIR + stm32_configgpio(STM32_CONSOLE_RS485_DIR); + stm32_gpiowrite(STM32_CONSOLE_RS485_DIR, + !STM32_CONSOLE_RS485_DIR_POLARITY); #endif /* Enable and configure the selected console device */ @@ -279,42 +279,42 @@ void stm32wb_lowsetup(void) #if defined(HAVE_CONSOLE) && !defined(CONFIG_SUPPRESS_UART_CONFIG) /* Configure CR2 */ - cr = getreg32(STM32WB_CONSOLE_BASE + STM32WB_USART_CR2_OFFSET); + cr = getreg32(STM32_CONSOLE_BASE + STM32_USART_CR2_OFFSET); cr &= ~USART_CR2_CLRBITS; cr |= USART_CR2_SETBITS; - putreg32(cr, STM32WB_CONSOLE_BASE + STM32WB_USART_CR2_OFFSET); + putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR2_OFFSET); /* Configure CR1 */ - cr = getreg32(STM32WB_CONSOLE_BASE + STM32WB_USART_CR1_OFFSET); + cr = getreg32(STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET); cr &= ~USART_CR1_CLRBITS; cr |= USART_CR1_SETBITS; - putreg32(cr, STM32WB_CONSOLE_BASE + STM32WB_USART_CR1_OFFSET); + putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET); /* Configure CR3 */ - cr = getreg32(STM32WB_CONSOLE_BASE + STM32WB_USART_CR3_OFFSET); + cr = getreg32(STM32_CONSOLE_BASE + STM32_USART_CR3_OFFSET); cr &= ~USART_CR3_CLRBITS; cr |= USART_CR3_SETBITS; - putreg32(cr, STM32WB_CONSOLE_BASE + STM32WB_USART_CR3_OFFSET); + putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR3_OFFSET); /* Configure the USART Baud Rate */ - putreg32(STM32WB_BRR_VALUE, - STM32WB_CONSOLE_BASE + STM32WB_USART_BRR_OFFSET); + putreg32(STM32_BRR_VALUE, + STM32_CONSOLE_BASE + STM32_USART_BRR_OFFSET); /* Select oversampling by 8 */ - cr = getreg32(STM32WB_CONSOLE_BASE + STM32WB_USART_CR1_OFFSET); + cr = getreg32(STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET); #ifdef USE_OVER8 cr |= USART_CR1_OVER8; - putreg32(cr, STM32WB_CONSOLE_BASE + STM32WB_USART_CR1_OFFSET); + putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET); #endif /* Enable Rx, Tx, and the USART */ cr |= (USART_CR1_UE | USART_CR1_TE | USART_CR1_RE); - putreg32(cr, STM32WB_CONSOLE_BASE + STM32WB_USART_CR1_OFFSET); + putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET); #endif /* HAVE_CONSOLE && !CONFIG_SUPPRESS_UART_CONFIG */ #endif /* HAVE_UART */ diff --git a/arch/arm/src/stm32wb/stm32wb_lowputc.h b/arch/arm/src/stm32wb/stm32wb_lowputc.h index 8a8ca85b3386d..86c2296525798 100644 --- a/arch/arm/src/stm32wb/stm32wb_lowputc.h +++ b/arch/arm/src/stm32wb/stm32wb_lowputc.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32WB_STM32WB_LOWPUTC_H -#define __ARCH_ARM_SRC_STM32WB_STM32WB_LOWPUTC_H +#ifndef __ARCH_ARM_SRC_STM32WB_STM32_LOWPUTC_H +#define __ARCH_ARM_SRC_STM32WB_STM32_LOWPUTC_H /**************************************************************************** * Included Files @@ -47,7 +47,7 @@ extern "C" #endif /**************************************************************************** - * Name: stm32wb_lowsetup + * Name: stm32_lowsetup * * Description: * Called at the very beginning of _start. @@ -55,7 +55,7 @@ extern "C" * ****************************************************************************/ -void stm32wb_lowsetup(void); +void stm32_lowsetup(void); #undef EXTERN #if defined(__cplusplus) @@ -63,4 +63,4 @@ void stm32wb_lowsetup(void); #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32WB_STM32WB_LOWPUTC_H */ +#endif /* __ARCH_ARM_SRC_STM32WB_STM32_LOWPUTC_H */ diff --git a/arch/arm/src/stm32wb/stm32wb_mbox.c b/arch/arm/src/stm32wb/stm32wb_mbox.c index 86c2e298c686b..b066a6a804dac 100644 --- a/arch/arm/src/stm32wb/stm32wb_mbox.c +++ b/arch/arm/src/stm32wb/stm32wb_mbox.c @@ -44,27 +44,27 @@ * the beginning of SRAM2a. */ -#define STM32WB_MBOX_SHARED_BASE STM32WB_SRAM2A_BASE +#define STM32_MBOX_SHARED_BASE STM32_SRAM2A_BASE /* Mailbox shared buffer fields */ -#define stm32wb_mbox_shared \ - (*(struct stm32wb_mbox_shared_buffer_s *)STM32WB_MBOX_SHARED_BASE) +#define stm32_mbox_shared \ + (*(struct stm32_mbox_shared_buffer_s *)STM32_MBOX_SHARED_BASE) -#define stm32wb_mbox_ref_table (stm32wb_mbox_shared.ref_table) -#define stm32wb_mbox_di_table (stm32wb_mbox_shared.dev_info_table) -#define stm32wb_mbox_sys_table (stm32wb_mbox_shared.sys_table) -#define stm32wb_mbox_mm_table (stm32wb_mbox_shared.mm_table) -#define stm32wb_mbox_ble_table (stm32wb_mbox_shared.ble_table) +#define stm32_mbox_ref_table (stm32_mbox_shared.ref_table) +#define stm32_mbox_di_table (stm32_mbox_shared.dev_info_table) +#define stm32_mbox_sys_table (stm32_mbox_shared.sys_table) +#define stm32_mbox_mm_table (stm32_mbox_shared.mm_table) +#define stm32_mbox_ble_table (stm32_mbox_shared.ble_table) /* Mailbox buffer sizes */ -#define STM32WB_MBOX_CS_BUF_SIZE 16 -#define STM32WB_MBOX_CMDPKT_BUF_SIZE 268 -#define STM32WB_MBOX_ACLPKT_BUF_SIZE 264 +#define STM32_MBOX_CS_BUF_SIZE 16 +#define STM32_MBOX_CMDPKT_BUF_SIZE 268 +#define STM32_MBOX_ACLPKT_BUF_SIZE 264 -#define STM32WB_MBOX_RX_BUF_SIZE \ - (CONFIG_STM32WB_MBOX_RX_EVT_QUEUE_LEN * STM32WB_MBOX_CMDPKT_BUF_SIZE) +#define STM32_MBOX_RX_BUF_SIZE \ + (CONFIG_STM32_MBOX_RX_EVT_QUEUE_LEN * STM32_MBOX_CMDPKT_BUF_SIZE) /**************************************************************************** * Private Types @@ -72,19 +72,19 @@ /* Mailbox shared buffer structures */ -begin_packed_struct struct stm32wb_mbox_safe_boot_info_table_s +begin_packed_struct struct stm32_mbox_safe_boot_info_table_s { uint32_t version; } end_packed_struct; -begin_packed_struct struct stm32wb_mbox_fus_info_table_s +begin_packed_struct struct stm32_mbox_fus_info_table_s { uint32_t version; uint32_t memory_size; uint32_t fus_info; } end_packed_struct; -begin_packed_struct struct stm32wb_mbox_wireless_fw_info_table_s +begin_packed_struct struct stm32_mbox_wireless_fw_info_table_s { uint32_t version; uint32_t memory_size; @@ -92,14 +92,14 @@ begin_packed_struct struct stm32wb_mbox_wireless_fw_info_table_s uint32_t reserved; } end_packed_struct; -begin_packed_struct struct stm32wb_mbox_device_info_table_s +begin_packed_struct struct stm32_mbox_device_info_table_s { - struct stm32wb_mbox_safe_boot_info_table_s safe_boot_info_table; - struct stm32wb_mbox_fus_info_table_s fus_info_table; - struct stm32wb_mbox_wireless_fw_info_table_s wireless_fw_info_table; + struct stm32_mbox_safe_boot_info_table_s safe_boot_info_table; + struct stm32_mbox_fus_info_table_s fus_info_table; + struct stm32_mbox_wireless_fw_info_table_s wireless_fw_info_table; } end_packed_struct; -begin_packed_struct struct stm32wb_mbox_ble_table_s +begin_packed_struct struct stm32_mbox_ble_table_s { void *cmd_buffer; void *cs_buffer; @@ -107,13 +107,13 @@ begin_packed_struct struct stm32wb_mbox_ble_table_s void *acl_buffer; } end_packed_struct; -begin_packed_struct struct stm32wb_mbox_sys_table_s +begin_packed_struct struct stm32_mbox_sys_table_s { void *cmd_buffer; void *evt_queue; } end_packed_struct; -begin_packed_struct struct stm32wb_mbox_mem_manager_table_s +begin_packed_struct struct stm32_mbox_mem_manager_table_s { void *ble_spare_buffer; void *sys_spare_buffer; @@ -124,13 +124,13 @@ begin_packed_struct struct stm32wb_mbox_mem_manager_table_s uint32_t traces_evtpool_size; } end_packed_struct; -begin_packed_struct struct stm32wb_mbox_ref_table_s +begin_packed_struct struct stm32_mbox_ref_table_s { - struct stm32wb_mbox_device_info_table_s *dev_info_table; - struct stm32wb_mbox_ble_table_s *ble_table; + struct stm32_mbox_device_info_table_s *dev_info_table; + struct stm32_mbox_ble_table_s *ble_table; void *thread_table; - struct stm32wb_mbox_sys_table_s *sys_table; - struct stm32wb_mbox_mem_manager_table_s *mm_table; + struct stm32_mbox_sys_table_s *sys_table; + struct stm32_mbox_mem_manager_table_s *mm_table; void *traces_table; void *mac_802_15_4_table; void *zigbee_table; @@ -140,41 +140,41 @@ begin_packed_struct struct stm32wb_mbox_ref_table_s /* Mailbox shared buffer memory layout structure */ -struct stm32wb_mbox_shared_buffer_s +struct stm32_mbox_shared_buffer_s { - aligned_data(4) struct stm32wb_mbox_ref_table_s ref_table; + aligned_data(4) struct stm32_mbox_ref_table_s ref_table; - aligned_data(4) struct stm32wb_mbox_device_info_table_s dev_info_table; - aligned_data(4) struct stm32wb_mbox_ble_table_s ble_table; - aligned_data(4) struct stm32wb_mbox_sys_table_s sys_table; - aligned_data(4) struct stm32wb_mbox_mem_manager_table_s mm_table; + aligned_data(4) struct stm32_mbox_device_info_table_s dev_info_table; + aligned_data(4) struct stm32_mbox_ble_table_s ble_table; + aligned_data(4) struct stm32_mbox_sys_table_s sys_table; + aligned_data(4) struct stm32_mbox_mem_manager_table_s mm_table; - aligned_data(4) stm32wb_mbox_list_t evtfree_buffer; -#ifdef CONFIG_STM32WB_BLE - aligned_data(4) stm32wb_mbox_list_t ble_evt_queue; + aligned_data(4) stm32_mbox_list_t evtfree_buffer; +#ifdef CONFIG_STM32_BLE + aligned_data(4) stm32_mbox_list_t ble_evt_queue; #endif - aligned_data(4) stm32wb_mbox_list_t sys_evt_queue; + aligned_data(4) stm32_mbox_list_t sys_evt_queue; -#ifdef CONFIG_STM32WB_BLE - aligned_data(4) uint8_t ble_cs_buffer[STM32WB_MBOX_CS_BUF_SIZE]; +#ifdef CONFIG_STM32_BLE + aligned_data(4) uint8_t ble_cs_buffer[STM32_MBOX_CS_BUF_SIZE]; #endif - aligned_data(4) uint8_t evtpool_buffer[STM32WB_MBOX_RX_BUF_SIZE]; - aligned_data(4) uint8_t sys_cmd_buffer[STM32WB_MBOX_CMDPKT_BUF_SIZE]; - aligned_data(4) uint8_t sys_spare_buffer[STM32WB_MBOX_CMDPKT_BUF_SIZE]; -#ifdef CONFIG_STM32WB_BLE - aligned_data(4) uint8_t ble_spare_buffer[STM32WB_MBOX_CMDPKT_BUF_SIZE]; - aligned_data(4) uint8_t ble_cmd_buffer[STM32WB_MBOX_CMDPKT_BUF_SIZE]; - aligned_data(4) uint8_t ble_acl_buffer[STM32WB_MBOX_ACLPKT_BUF_SIZE]; + aligned_data(4) uint8_t evtpool_buffer[STM32_MBOX_RX_BUF_SIZE]; + aligned_data(4) uint8_t sys_cmd_buffer[STM32_MBOX_CMDPKT_BUF_SIZE]; + aligned_data(4) uint8_t sys_spare_buffer[STM32_MBOX_CMDPKT_BUF_SIZE]; +#ifdef CONFIG_STM32_BLE + aligned_data(4) uint8_t ble_spare_buffer[STM32_MBOX_CMDPKT_BUF_SIZE]; + aligned_data(4) uint8_t ble_cmd_buffer[STM32_MBOX_CMDPKT_BUF_SIZE]; + aligned_data(4) uint8_t ble_acl_buffer[STM32_MBOX_ACLPKT_BUF_SIZE]; #endif }; /* Mailbox channel data type */ -struct stm32wb_mbox_channel_s +struct stm32_mbox_channel_s { uint8_t ch_num; - stm32wb_mbox_list_t cmd_buf_queue; - struct stm32wb_mbox_cmd_s *cmd_buf; + stm32_mbox_list_t cmd_buf_queue; + struct stm32_mbox_cmd_s *cmd_buf; bool ack_ready; }; @@ -182,18 +182,18 @@ struct stm32wb_mbox_channel_s * Private Function prototypes ****************************************************************************/ -static void stm32wb_ipcc_rxoisr(int irq, uint32_t *regs, void *arg); -static void stm32wb_ipcc_txfisr(int irq, uint32_t *regs, void *arg); +static void stm32_ipcc_rxoisr(int irq, uint32_t *regs, void *arg); +static void stm32_ipcc_txfisr(int irq, uint32_t *regs, void *arg); -static void stm32wb_mbox_rxworker(void *arg); -static void stm32wb_mbox_txworker(void *arg); +static void stm32_mbox_rxworker(void *arg); +static void stm32_mbox_txworker(void *arg); -static void stm32wb_mbox_eventfree(stm32wb_mbox_list_t *evt); -static void stm32wb_mbox_acksyscmd(void); +static void stm32_mbox_eventfree(stm32_mbox_list_t *evt); +static void stm32_mbox_acksyscmd(void); -static int stm32wb_mbox_txdata(struct stm32wb_mbox_channel_s *chan, +static int stm32_mbox_txdata(struct stm32_mbox_channel_s *chan, uint8_t type, void *data, size_t len); -static bool stm32wb_mbox_txnext(struct stm32wb_mbox_channel_s *chan); +static bool stm32_mbox_txnext(struct stm32_mbox_channel_s *chan); /**************************************************************************** * Private Data @@ -202,26 +202,26 @@ static bool stm32wb_mbox_txnext(struct stm32wb_mbox_channel_s *chan); static struct work_s g_rx_evt_work; static struct work_s g_tx_cmd_work; -static stm32wb_mbox_list_t g_rx_evt_queue; -static stm32wb_mbox_list_t g_tx_evtfree_queue; -static uint8_t g_free_buffers[CONFIG_STM32WB_MBOX_TX_CMD_QUEUE_LEN] - [STM32WB_MBOX_CMDPKT_BUF_SIZE]; -static stm32wb_mbox_list_t g_free_buffers_pool; +static stm32_mbox_list_t g_rx_evt_queue; +static stm32_mbox_list_t g_tx_evtfree_queue; +static uint8_t g_free_buffers[CONFIG_STM32_MBOX_TX_CMD_QUEUE_LEN] + [STM32_MBOX_CMDPKT_BUF_SIZE]; +static stm32_mbox_list_t g_free_buffers_pool; -static struct stm32wb_mbox_channel_s g_syscmd_channel; -#ifdef CONFIG_STM32WB_BLE -static struct stm32wb_mbox_channel_s g_blecmd_channel; -static struct stm32wb_mbox_channel_s g_bleacl_channel; +static struct stm32_mbox_channel_s g_syscmd_channel; +#ifdef CONFIG_STM32_BLE +static struct stm32_mbox_channel_s g_blecmd_channel; +static struct stm32_mbox_channel_s g_bleacl_channel; #endif -static stm32wb_mbox_evt_handler_t receive_evt_handler; +static stm32_mbox_evt_handler_t receive_evt_handler; /**************************************************************************** * Private Functions ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_ipcc_rxoisr + * Name: stm32_ipcc_rxoisr * * Description: * RX channel occupied interrupt handler (communication data posted @@ -229,30 +229,30 @@ static stm32wb_mbox_evt_handler_t receive_evt_handler; * ****************************************************************************/ -static void stm32wb_ipcc_rxoisr(int irq, uint32_t *regs, void *arg) +static void stm32_ipcc_rxoisr(int irq, uint32_t *regs, void *arg) { uint32_t clrmask = 0; /* Pull events from system channel into processing queue */ - if (stm32wb_ipcc_rxactive(STM32WB_MBOX_SYSEVT_CHANNEL)) + if (stm32_ipcc_rxactive(STM32_MBOX_SYSEVT_CHANNEL)) { - stm32wb_mbox_list_moveall(&stm32wb_mbox_shared.sys_evt_queue, + stm32_mbox_list_moveall(&stm32_mbox_shared.sys_evt_queue, &g_rx_evt_queue); - clrmask |= IPCC_C1SCR_CLR_BIT(STM32WB_MBOX_SYSEVT_CHANNEL); + clrmask |= IPCC_C1SCR_CLR_BIT(STM32_MBOX_SYSEVT_CHANNEL); } -#ifdef CONFIG_STM32WB_BLE +#ifdef CONFIG_STM32_BLE /* Pull events from BLE channel into processing queue */ - if (stm32wb_ipcc_rxactive(STM32WB_MBOX_BLEEVT_CHANNEL)) + if (stm32_ipcc_rxactive(STM32_MBOX_BLEEVT_CHANNEL)) { - stm32wb_mbox_list_moveall(&stm32wb_mbox_shared.ble_evt_queue, + stm32_mbox_list_moveall(&stm32_mbox_shared.ble_evt_queue, &g_rx_evt_queue); - clrmask |= IPCC_C1SCR_CLR_BIT(STM32WB_MBOX_BLEEVT_CHANNEL); + clrmask |= IPCC_C1SCR_CLR_BIT(STM32_MBOX_BLEEVT_CHANNEL); } #endif @@ -260,16 +260,16 @@ static void stm32wb_ipcc_rxoisr(int irq, uint32_t *regs, void *arg) if (work_available(&g_rx_evt_work)) { - work_queue(HPWORK, &g_rx_evt_work, stm32wb_mbox_rxworker, NULL, 0); + work_queue(HPWORK, &g_rx_evt_work, stm32_mbox_rxworker, NULL, 0); } /* Clear active statuses */ - putreg32(clrmask, STM32WB_IPCC_C1SCR); + putreg32(clrmask, STM32_IPCC_C1SCR); } /**************************************************************************** - * Name: stm32wb_ipcc_txfisr + * Name: stm32_ipcc_txfisr * * Description: * TX channel free interrupt handler (communication data retrieved @@ -277,9 +277,9 @@ static void stm32wb_ipcc_rxoisr(int irq, uint32_t *regs, void *arg) * ****************************************************************************/ -static void stm32wb_ipcc_txfisr(int irq, uint32_t *regs, void *arg) +static void stm32_ipcc_txfisr(int irq, uint32_t *regs, void *arg) { - uint32_t c1mr = getreg32(STM32WB_IPCC_C1MR); + uint32_t c1mr = getreg32(STM32_IPCC_C1MR); uint32_t txfsrc; /* TXF interrupt can be triggered by not masked channels and active status @@ -287,33 +287,33 @@ static void stm32wb_ipcc_txfisr(int irq, uint32_t *regs, void *arg) * channels and rise other C1MR bits to highlight needed channels. */ - txfsrc = ~(c1mr | (getreg32(STM32WB_IPCC_C1TOC2SR) << IPCC_C1MR_FM_SHIFT)) + txfsrc = ~(c1mr | (getreg32(STM32_IPCC_C1TOC2SR) << IPCC_C1MR_FM_SHIFT)) & IPCC_C1MR_FM_MASK; /* Check if the release channel triggered the interrupt */ - if (txfsrc & IPCC_C1MR_FM_BIT(STM32WB_MBOX_EVT_RELEASE_CHANNEL)) + if (txfsrc & IPCC_C1MR_FM_BIT(STM32_MBOX_EVT_RELEASE_CHANNEL)) { /* Move all released events (if any) into transmission mailbox */ - if (!stm32wb_mbox_list_is_empty(&g_tx_evtfree_queue)) + if (!stm32_mbox_list_is_empty(&g_tx_evtfree_queue)) { - stm32wb_mbox_list_moveall(&g_tx_evtfree_queue, - &stm32wb_mbox_shared.evtfree_buffer); + stm32_mbox_list_moveall(&g_tx_evtfree_queue, + &stm32_mbox_shared.evtfree_buffer); /* Start release channel transmission */ - stm32wb_ipcc_settxactive(STM32WB_MBOX_EVT_RELEASE_CHANNEL); + stm32_ipcc_settxactive(STM32_MBOX_EVT_RELEASE_CHANNEL); } } /* Check other channels, except the release channel */ - if (txfsrc & ~IPCC_C1MR_FM_BIT(STM32WB_MBOX_EVT_RELEASE_CHANNEL)) + if (txfsrc & ~IPCC_C1MR_FM_BIT(STM32_MBOX_EVT_RELEASE_CHANNEL)) { /* Check if the system channel triggered the interrupt */ - if (txfsrc & IPCC_C1MR_FM_BIT(STM32WB_MBOX_SYSCMD_CHANNEL)) + if (txfsrc & IPCC_C1MR_FM_BIT(STM32_MBOX_SYSCMD_CHANNEL)) { /* System channel works in 'half-duplex' mode and acks * immediately on each command before TXF, so it needs @@ -327,20 +327,20 @@ static void stm32wb_ipcc_txfisr(int irq, uint32_t *regs, void *arg) if (work_available(&g_tx_cmd_work)) { - work_queue(HPWORK, &g_tx_cmd_work, stm32wb_mbox_txworker, NULL, 0); + work_queue(HPWORK, &g_tx_cmd_work, stm32_mbox_txworker, NULL, 0); } } /* Mask triggered channels */ - putreg32(c1mr | txfsrc, STM32WB_IPCC_C1MR); + putreg32(c1mr | txfsrc, STM32_IPCC_C1MR); } /**************************************************************************** - * Name: stm32wb_mbox_txworker + * Name: stm32_mbox_txworker ****************************************************************************/ -static void stm32wb_mbox_txworker(void *arg) +static void stm32_mbox_txworker(void *arg) { bool handled; @@ -350,28 +350,28 @@ static void stm32wb_mbox_txworker(void *arg) { handled = false; - if (!stm32wb_ipcc_txactive(STM32WB_MBOX_SYSCMD_CHANNEL)) + if (!stm32_ipcc_txactive(STM32_MBOX_SYSCMD_CHANNEL)) { /* Process ack response before send new command */ if (g_syscmd_channel.ack_ready) { - stm32wb_mbox_acksyscmd(); + stm32_mbox_acksyscmd(); g_syscmd_channel.ack_ready = false; } - handled = stm32wb_mbox_txnext(&g_syscmd_channel); + handled = stm32_mbox_txnext(&g_syscmd_channel); } -#ifdef CONFIG_STM32WB_BLE - if (!stm32wb_ipcc_txactive(STM32WB_MBOX_BLECMD_CHANNEL)) +#ifdef CONFIG_STM32_BLE + if (!stm32_ipcc_txactive(STM32_MBOX_BLECMD_CHANNEL)) { - handled |= stm32wb_mbox_txnext(&g_blecmd_channel); + handled |= stm32_mbox_txnext(&g_blecmd_channel); } - if (!stm32wb_ipcc_txactive(STM32WB_MBOX_BLEACL_CHANNEL)) + if (!stm32_ipcc_txactive(STM32_MBOX_BLEACL_CHANNEL)) { - handled |= stm32wb_mbox_txnext(&g_bleacl_channel); + handled |= stm32_mbox_txnext(&g_bleacl_channel); } #endif } @@ -379,12 +379,12 @@ static void stm32wb_mbox_txworker(void *arg) } /**************************************************************************** - * Name: stm32wb_mbox_rxworker + * Name: stm32_mbox_rxworker ****************************************************************************/ -static void stm32wb_mbox_rxworker(void *arg) +static void stm32_mbox_rxworker(void *arg) { - stm32wb_mbox_list_t *evt; + stm32_mbox_list_t *evt; irqstate_t flags; while (1) @@ -393,7 +393,7 @@ static void stm32wb_mbox_rxworker(void *arg) /* Pull an event from the queue */ - evt = stm32wb_mbox_list_remove_head(&g_rx_evt_queue); + evt = stm32_mbox_list_remove_head(&g_rx_evt_queue); leave_critical_section(flags); @@ -404,18 +404,18 @@ static void stm32wb_mbox_rxworker(void *arg) /* Pass event to a callback function without a list header */ - receive_evt_handler((struct stm32wb_mbox_evt_s *)(evt + 1)); + receive_evt_handler((struct stm32_mbox_evt_s *)(evt + 1)); /* Free completed event. Released event needs to return to CPU2 * via release channel. */ - stm32wb_mbox_eventfree((stm32wb_mbox_list_t *)evt); + stm32_mbox_eventfree((stm32_mbox_list_t *)evt); } } /**************************************************************************** - * Name: stm32wb_mbox_txdata + * Name: stm32_mbox_txdata * * Description: * Send data over specified mailbox channel if possible. If the @@ -423,11 +423,11 @@ static void stm32wb_mbox_rxworker(void *arg) * ****************************************************************************/ -static int stm32wb_mbox_txdata(struct stm32wb_mbox_channel_s *chan, +static int stm32_mbox_txdata(struct stm32_mbox_channel_s *chan, uint8_t type, void *data, size_t len) { irqstate_t flags; - struct stm32wb_mbox_cmd_s *pkt_buf; + struct stm32_mbox_cmd_s *pkt_buf; flags = enter_critical_section(); @@ -435,8 +435,8 @@ static int stm32wb_mbox_txdata(struct stm32wb_mbox_channel_s *chan, * none of other waiting commands and none of unprocessed ack responses. */ - if (stm32wb_mbox_list_is_empty(&chan->cmd_buf_queue) && - !stm32wb_ipcc_txactive(chan->ch_num) && !chan->ack_ready) + if (stm32_mbox_list_is_empty(&chan->cmd_buf_queue) && + !stm32_ipcc_txactive(chan->ch_num) && !chan->ack_ready) { /* Channel is ready, copy command into transmission buffer */ @@ -446,8 +446,8 @@ static int stm32wb_mbox_txdata(struct stm32wb_mbox_channel_s *chan, { /* Otherwise get temp buffer for command */ - pkt_buf = (struct stm32wb_mbox_cmd_s *) - stm32wb_mbox_list_remove_head(&g_free_buffers_pool); + pkt_buf = (struct stm32_mbox_cmd_s *) + stm32_mbox_list_remove_head(&g_free_buffers_pool); } leave_critical_section(flags); @@ -464,17 +464,17 @@ static int stm32wb_mbox_txdata(struct stm32wb_mbox_channel_s *chan, { /* Command is ready in mailbox buffer, start transmission now */ - stm32wb_ipcc_settxactive(chan->ch_num); + stm32_ipcc_settxactive(chan->ch_num); - if (!stm32wb_mbox_list_is_empty(&chan->cmd_buf_queue) || - chan->ch_num == STM32WB_MBOX_SYSCMD_CHANNEL) + if (!stm32_mbox_list_is_empty(&chan->cmd_buf_queue) || + chan->ch_num == STM32_MBOX_SYSCMD_CHANNEL) { /* There are more commands awaiting, so unmask interrupt to get * notified when channel gets ready to process a next one. * And the system channel needs to check ack on completion. */ - stm32wb_ipcc_unmasktxf(chan->ch_num); + stm32_ipcc_unmasktxf(chan->ch_num); } } else @@ -482,37 +482,37 @@ static int stm32wb_mbox_txdata(struct stm32wb_mbox_channel_s *chan, /* Command is in temp buffer, push it into queue */ flags = enter_critical_section(); - stm32wb_mbox_list_add_tail(&chan->cmd_buf_queue, &pkt_buf->list_hdr); + stm32_mbox_list_add_tail(&chan->cmd_buf_queue, &pkt_buf->list_hdr); leave_critical_section(flags); /* Unmask interrupt to get notified when channel gets free */ - stm32wb_ipcc_unmasktxf(chan->ch_num); + stm32_ipcc_unmasktxf(chan->ch_num); } return OK; } /**************************************************************************** - * Name: stm32wb_mbox_txnext + * Name: stm32_mbox_txnext * * Description: * Send next command from the queue. * ****************************************************************************/ -static bool stm32wb_mbox_txnext(struct stm32wb_mbox_channel_s *chan) +static bool stm32_mbox_txnext(struct stm32_mbox_channel_s *chan) { - struct stm32wb_mbox_cmd_s *pkt_buf; + struct stm32_mbox_cmd_s *pkt_buf; - pkt_buf = (struct stm32wb_mbox_cmd_s *) - stm32wb_mbox_list_remove_head(&chan->cmd_buf_queue); + pkt_buf = (struct stm32_mbox_cmd_s *) + stm32_mbox_list_remove_head(&chan->cmd_buf_queue); if (pkt_buf != NULL) { chan->cmd_buf->type = pkt_buf->type; - if (chan->ch_num == STM32WB_MBOX_BLEACL_CHANNEL) + if (chan->ch_num == STM32_MBOX_BLEACL_CHANNEL) { memcpy(&chan->cmd_buf->acl_hdr, &pkt_buf->acl_hdr, sizeof(pkt_buf->acl_hdr) + pkt_buf->acl_hdr.len); @@ -525,32 +525,32 @@ static bool stm32wb_mbox_txnext(struct stm32wb_mbox_channel_s *chan) /* Start transmission */ - stm32wb_ipcc_settxactive(chan->ch_num); + stm32_ipcc_settxactive(chan->ch_num); - if (!stm32wb_mbox_list_is_empty(&chan->cmd_buf_queue)) + if (!stm32_mbox_list_is_empty(&chan->cmd_buf_queue)) { /* Unmask TXF interrupt to get notified when completed */ - stm32wb_ipcc_unmasktxf(chan->ch_num); + stm32_ipcc_unmasktxf(chan->ch_num); } /* Put back to pool the freed command buffer */ - stm32wb_mbox_list_add_tail(&g_free_buffers_pool, &pkt_buf->list_hdr); + stm32_mbox_list_add_tail(&g_free_buffers_pool, &pkt_buf->list_hdr); } return pkt_buf != NULL; } /**************************************************************************** - * Name: stm32wb_mbox_eventfree + * Name: stm32_mbox_eventfree * * Description: * Free handled mailbox event. * ****************************************************************************/ -static void stm32wb_mbox_eventfree(stm32wb_mbox_list_t *evt) +static void stm32_mbox_eventfree(stm32_mbox_list_t *evt) { irqstate_t flags; @@ -558,49 +558,49 @@ static void stm32wb_mbox_eventfree(stm32wb_mbox_list_t *evt) /* Collect releasing events in the global list */ - stm32wb_mbox_list_add_tail(&g_tx_evtfree_queue, evt); + stm32_mbox_list_add_tail(&g_tx_evtfree_queue, evt); /* Check if release channel is ready to process now */ - if (!stm32wb_ipcc_txactive(STM32WB_MBOX_EVT_RELEASE_CHANNEL)) + if (!stm32_ipcc_txactive(STM32_MBOX_EVT_RELEASE_CHANNEL)) { /* Move all collected events into transmission queue */ - stm32wb_mbox_list_moveall(&g_tx_evtfree_queue, - &stm32wb_mbox_shared.evtfree_buffer); + stm32_mbox_list_moveall(&g_tx_evtfree_queue, + &stm32_mbox_shared.evtfree_buffer); /* Start transmission */ - stm32wb_ipcc_settxactive(STM32WB_MBOX_EVT_RELEASE_CHANNEL); + stm32_ipcc_settxactive(STM32_MBOX_EVT_RELEASE_CHANNEL); } else { /* Unmask interrupt to get notified when channel gets free */ - stm32wb_ipcc_unmasktxf(STM32WB_MBOX_EVT_RELEASE_CHANNEL); + stm32_ipcc_unmasktxf(STM32_MBOX_EVT_RELEASE_CHANNEL); } leave_critical_section(flags); } /**************************************************************************** - * Name: stm32wb_mbox_acksyscmd + * Name: stm32_mbox_acksyscmd * * Description: * Send ACK response event for completed system command. * ****************************************************************************/ -static void stm32wb_mbox_acksyscmd(void) +static void stm32_mbox_acksyscmd(void) { - struct stm32wb_mbox_evt_s *evt; + struct stm32_mbox_evt_s *evt; /* System command ACK response is placed at the same address as the * processed command but without a list header. */ - evt = (struct stm32wb_mbox_evt_s *)(&g_syscmd_channel.cmd_buf); - evt->type = STM32WB_MBOX_SYSACK; + evt = (struct stm32_mbox_evt_s *)(&g_syscmd_channel.cmd_buf); + evt->type = STM32_MBOX_SYSACK; receive_evt_handler(evt); } @@ -610,7 +610,7 @@ static void stm32wb_mbox_acksyscmd(void) ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_mboxinitialize + * Name: stm32_mboxinitialize * * Description: * Initialize mailbox driver memory. @@ -620,79 +620,79 @@ static void stm32wb_mbox_acksyscmd(void) * ****************************************************************************/ -void stm32wb_mboxinitialize(stm32wb_mbox_evt_handler_t evt_handler) +void stm32_mboxinitialize(stm32_mbox_evt_handler_t evt_handler) { int i; /* Init mailbox shared data */ - stm32wb_mbox_list_initialize(&stm32wb_mbox_shared.sys_evt_queue); - stm32wb_mbox_list_initialize(&stm32wb_mbox_shared.evtfree_buffer); -#ifdef CONFIG_STM32WB_BLE - stm32wb_mbox_list_initialize(&stm32wb_mbox_shared.ble_evt_queue); + stm32_mbox_list_initialize(&stm32_mbox_shared.sys_evt_queue); + stm32_mbox_list_initialize(&stm32_mbox_shared.evtfree_buffer); +#ifdef CONFIG_STM32_BLE + stm32_mbox_list_initialize(&stm32_mbox_shared.ble_evt_queue); #endif - stm32wb_mbox_ref_table.dev_info_table = &stm32wb_mbox_di_table; - stm32wb_mbox_ref_table.ble_table = &stm32wb_mbox_ble_table; - stm32wb_mbox_ref_table.sys_table = &stm32wb_mbox_sys_table; - stm32wb_mbox_ref_table.mm_table = &stm32wb_mbox_mm_table; + stm32_mbox_ref_table.dev_info_table = &stm32_mbox_di_table; + stm32_mbox_ref_table.ble_table = &stm32_mbox_ble_table; + stm32_mbox_ref_table.sys_table = &stm32_mbox_sys_table; + stm32_mbox_ref_table.mm_table = &stm32_mbox_mm_table; - stm32wb_mbox_sys_table.cmd_buffer = &stm32wb_mbox_shared.sys_cmd_buffer; - stm32wb_mbox_sys_table.evt_queue = &stm32wb_mbox_shared.sys_evt_queue; + stm32_mbox_sys_table.cmd_buffer = &stm32_mbox_shared.sys_cmd_buffer; + stm32_mbox_sys_table.evt_queue = &stm32_mbox_shared.sys_evt_queue; - stm32wb_mbox_mm_table.evtpool_buffer = &stm32wb_mbox_shared + stm32_mbox_mm_table.evtpool_buffer = &stm32_mbox_shared .evtpool_buffer; - stm32wb_mbox_mm_table.evtpool_size = sizeof(stm32wb_mbox_shared + stm32_mbox_mm_table.evtpool_size = sizeof(stm32_mbox_shared .evtpool_buffer); - stm32wb_mbox_mm_table.evtfree_buffer = &stm32wb_mbox_shared + stm32_mbox_mm_table.evtfree_buffer = &stm32_mbox_shared .evtfree_buffer; - stm32wb_mbox_mm_table.sys_spare_buffer = &stm32wb_mbox_shared + stm32_mbox_mm_table.sys_spare_buffer = &stm32_mbox_shared .sys_spare_buffer; -#ifdef CONFIG_STM32WB_BLE - stm32wb_mbox_mm_table.ble_spare_buffer = &stm32wb_mbox_shared +#ifdef CONFIG_STM32_BLE + stm32_mbox_mm_table.ble_spare_buffer = &stm32_mbox_shared .ble_spare_buffer; #endif -#ifdef CONFIG_STM32WB_BLE - stm32wb_mbox_ble_table.cmd_buffer = &stm32wb_mbox_shared.ble_cmd_buffer; - stm32wb_mbox_ble_table.acl_buffer = &stm32wb_mbox_shared.ble_acl_buffer; - stm32wb_mbox_ble_table.cs_buffer = &stm32wb_mbox_shared.ble_cs_buffer; - stm32wb_mbox_ble_table.evt_queue = &stm32wb_mbox_shared.ble_evt_queue; +#ifdef CONFIG_STM32_BLE + stm32_mbox_ble_table.cmd_buffer = &stm32_mbox_shared.ble_cmd_buffer; + stm32_mbox_ble_table.acl_buffer = &stm32_mbox_shared.ble_acl_buffer; + stm32_mbox_ble_table.cs_buffer = &stm32_mbox_shared.ble_cs_buffer; + stm32_mbox_ble_table.evt_queue = &stm32_mbox_shared.ble_evt_queue; #endif /* Init system channel data */ - g_syscmd_channel.ch_num = STM32WB_MBOX_SYSCMD_CHANNEL; - g_syscmd_channel.cmd_buf = (struct stm32wb_mbox_cmd_s *) - stm32wb_mbox_shared.sys_cmd_buffer; - stm32wb_mbox_list_initialize(&g_syscmd_channel.cmd_buf_queue); + g_syscmd_channel.ch_num = STM32_MBOX_SYSCMD_CHANNEL; + g_syscmd_channel.cmd_buf = (struct stm32_mbox_cmd_s *) + stm32_mbox_shared.sys_cmd_buffer; + stm32_mbox_list_initialize(&g_syscmd_channel.cmd_buf_queue); -#ifdef CONFIG_STM32WB_BLE +#ifdef CONFIG_STM32_BLE /* Init BLE command channel data */ - g_blecmd_channel.ch_num = STM32WB_MBOX_BLECMD_CHANNEL; - g_blecmd_channel.cmd_buf = (struct stm32wb_mbox_cmd_s *) - stm32wb_mbox_shared.ble_cmd_buffer; - stm32wb_mbox_list_initialize(&g_blecmd_channel.cmd_buf_queue); + g_blecmd_channel.ch_num = STM32_MBOX_BLECMD_CHANNEL; + g_blecmd_channel.cmd_buf = (struct stm32_mbox_cmd_s *) + stm32_mbox_shared.ble_cmd_buffer; + stm32_mbox_list_initialize(&g_blecmd_channel.cmd_buf_queue); /* Init BLE ACL channel data */ - g_bleacl_channel.ch_num = STM32WB_MBOX_BLEACL_CHANNEL; - g_bleacl_channel.cmd_buf = (struct stm32wb_mbox_cmd_s *) - stm32wb_mbox_shared.ble_acl_buffer; - stm32wb_mbox_list_initialize(&g_bleacl_channel.cmd_buf_queue); + g_bleacl_channel.ch_num = STM32_MBOX_BLEACL_CHANNEL; + g_bleacl_channel.cmd_buf = (struct stm32_mbox_cmd_s *) + stm32_mbox_shared.ble_acl_buffer; + stm32_mbox_list_initialize(&g_bleacl_channel.cmd_buf_queue); #endif /* Init local (not shared) queues */ - stm32wb_mbox_list_initialize(&g_rx_evt_queue); - stm32wb_mbox_list_initialize(&g_tx_evtfree_queue); + stm32_mbox_list_initialize(&g_rx_evt_queue); + stm32_mbox_list_initialize(&g_tx_evtfree_queue); - stm32wb_mbox_list_initialize(&g_free_buffers_pool); - for (i = 0; i < CONFIG_STM32WB_MBOX_TX_CMD_QUEUE_LEN; i++) + stm32_mbox_list_initialize(&g_free_buffers_pool); + for (i = 0; i < CONFIG_STM32_MBOX_TX_CMD_QUEUE_LEN; i++) { - stm32wb_mbox_list_add_tail(&g_free_buffers_pool, - (stm32wb_mbox_list_t *)g_free_buffers[i]); + stm32_mbox_list_add_tail(&g_free_buffers_pool, + (stm32_mbox_list_t *)g_free_buffers[i]); } /* Set event receive function */ @@ -701,7 +701,7 @@ void stm32wb_mboxinitialize(stm32wb_mbox_evt_handler_t evt_handler) } /**************************************************************************** - * Name: stm32wb_mboxenable + * Name: stm32_mboxenable * * Description: * Enable mailbox hardware and start communication. The CPU2 responses @@ -709,35 +709,35 @@ void stm32wb_mboxinitialize(stm32wb_mbox_evt_handler_t evt_handler) * ****************************************************************************/ -void stm32wb_mboxenable(void) +void stm32_mboxenable(void) { uint32_t regval; /* Setup RXO and TXF interrupts */ - irq_attach(STM32WB_IRQ_IPCCRX, (xcpt_t)stm32wb_ipcc_rxoisr, NULL); - up_enable_irq(STM32WB_IRQ_IPCCRX); + irq_attach(STM32_IRQ_IPCCRX, (xcpt_t)stm32_ipcc_rxoisr, NULL); + up_enable_irq(STM32_IRQ_IPCCRX); - irq_attach(STM32WB_IRQ_IPCCTX, (xcpt_t)stm32wb_ipcc_txfisr, NULL); - up_enable_irq(STM32WB_IRQ_IPCCTX); + irq_attach(STM32_IRQ_IPCCTX, (xcpt_t)stm32_ipcc_txfisr, NULL); + up_enable_irq(STM32_IRQ_IPCCTX); - regval = getreg32(STM32WB_IPCC_C1CR); + regval = getreg32(STM32_IPCC_C1CR); regval |= IPCC_C1CR_RXOIE | IPCC_C1CR_TXFIE; - putreg32(regval, STM32WB_IPCC_C1CR); + putreg32(regval, STM32_IPCC_C1CR); /* Unmask system channel RXO interrupt. Once CPU2 started we expect * to receive C2READY event via system channel. */ - stm32wb_ipcc_unmaskrxo(STM32WB_MBOX_SYSEVT_CHANNEL); + stm32_ipcc_unmaskrxo(STM32_MBOX_SYSEVT_CHANNEL); /* Enable IPCC hardware and boot up CPU2 */ - stm32wb_ipccenable(); + stm32_ipccenable(); } /**************************************************************************** - * Name: stm32wb_mbox_syscmd + * Name: stm32_mbox_syscmd * * Description: * Send command over mailbox system channel. Command data must be @@ -745,15 +745,15 @@ void stm32wb_mboxenable(void) * ****************************************************************************/ -int stm32wb_mbox_syscmd(void *data, size_t len) +int stm32_mbox_syscmd(void *data, size_t len) { - return stm32wb_mbox_txdata(&g_syscmd_channel, STM32WB_MBOX_SYSCMD, + return stm32_mbox_txdata(&g_syscmd_channel, STM32_MBOX_SYSCMD, data, len); } -#ifdef CONFIG_STM32WB_BLE +#ifdef CONFIG_STM32_BLE /**************************************************************************** - * Name: stm32wb_mbox_blecmd + * Name: stm32_mbox_blecmd * * Description: * Send command over mailbox BLE channel. Command data must be @@ -761,14 +761,14 @@ int stm32wb_mbox_syscmd(void *data, size_t len) * ****************************************************************************/ -int stm32wb_mbox_blecmd(void *data, size_t len) +int stm32_mbox_blecmd(void *data, size_t len) { - return stm32wb_mbox_txdata(&g_blecmd_channel, STM32WB_MBOX_HCICMD, + return stm32_mbox_txdata(&g_blecmd_channel, STM32_MBOX_HCICMD, data, len); } /**************************************************************************** - * Name: stm32wb_mbox_bleacl + * Name: stm32_mbox_bleacl * * Description: * Send BLE ACL data over mailbox BLE ACL channel. Data must be @@ -776,40 +776,40 @@ int stm32wb_mbox_blecmd(void *data, size_t len) * ****************************************************************************/ -int stm32wb_mbox_bleacl(void *data, size_t len) +int stm32_mbox_bleacl(void *data, size_t len) { - return stm32wb_mbox_txdata(&g_bleacl_channel, STM32WB_MBOX_HCIACL, + return stm32_mbox_txdata(&g_bleacl_channel, STM32_MBOX_HCIACL, data, len); } /**************************************************************************** - * Name: stm32wb_mbox_bleinit + * Name: stm32_mbox_bleinit * * Description: * Initialize and start BLE subsystem with provided configuration params. * ****************************************************************************/ -void stm32wb_mbox_bleinit(struct stm32wb_shci_ble_init_cfg_s *params) +void stm32_mbox_bleinit(struct stm32_shci_ble_init_cfg_s *params) { struct bt_hci_cmd_hdr_s *cmd; /* Just borrow a temporary free buffer for command data */ - cmd = (struct bt_hci_cmd_hdr_s *)stm32wb_mbox_shared.sys_spare_buffer; + cmd = (struct bt_hci_cmd_hdr_s *)stm32_mbox_shared.sys_spare_buffer; /* Prepare command data */ - cmd->opcode = STM32WB_SHCI_BLE_INIT; + cmd->opcode = STM32_SHCI_BLE_INIT; cmd->param_len = sizeof(*cmd); memcpy(cmd + 1, params, sizeof(*params)); /* Send BLE init command to CPU2 */ - stm32wb_mbox_syscmd(cmd, sizeof(*cmd) + sizeof(*params)); + stm32_mbox_syscmd(cmd, sizeof(*cmd) + sizeof(*params)); /* Unmask BLE event channel RXO interrupt */ - stm32wb_ipcc_unmaskrxo(STM32WB_MBOX_BLEEVT_CHANNEL); + stm32_ipcc_unmaskrxo(STM32_MBOX_BLEEVT_CHANNEL); } -#endif /* CONFIG_STM32WB_BLE */ +#endif /* CONFIG_STM32_BLE */ diff --git a/arch/arm/src/stm32wb/stm32wb_mbox.h b/arch/arm/src/stm32wb/stm32wb_mbox.h index f67821fa5c566..72eab3ba72fdc 100644 --- a/arch/arm/src/stm32wb/stm32wb_mbox.h +++ b/arch/arm/src/stm32wb/stm32wb_mbox.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32WB_STM32WB_MBOX_H -#define __ARCH_ARM_SRC_STM32WB_STM32WB_MBOX_H +#ifndef __ARCH_ARM_SRC_STM32WB_STM32_MBOX_H +#define __ARCH_ARM_SRC_STM32WB_STM32_MBOX_H /**************************************************************************** * Included Files @@ -42,34 +42,34 @@ /* Mailbox channels */ -#define STM32WB_MBOX_BLEEVT_CHANNEL 1 -#define STM32WB_MBOX_BLECMD_CHANNEL 1 -#define STM32WB_MBOX_SYSEVT_CHANNEL 2 -#define STM32WB_MBOX_SYSCMD_CHANNEL 2 -#define STM32WB_MBOX_EVT_RELEASE_CHANNEL 4 -#define STM32WB_MBOX_BLEACL_CHANNEL 6 +#define STM32_MBOX_BLEEVT_CHANNEL 1 +#define STM32_MBOX_BLECMD_CHANNEL 1 +#define STM32_MBOX_SYSEVT_CHANNEL 2 +#define STM32_MBOX_SYSCMD_CHANNEL 2 +#define STM32_MBOX_EVT_RELEASE_CHANNEL 4 +#define STM32_MBOX_BLEACL_CHANNEL 6 /* Mailbox packet types */ -#define STM32WB_MBOX_HCICMD 0x01 -#define STM32WB_MBOX_HCIACL 0x02 -#define STM32WB_MBOX_HCIEVT 0x04 -#define STM32WB_MBOX_SYSCMD 0x10 -#define STM32WB_MBOX_SYSEVT 0x12 -#define STM32WB_MBOX_SYSACK 0xe0 +#define STM32_MBOX_HCICMD 0x01 +#define STM32_MBOX_HCIACL 0x02 +#define STM32_MBOX_HCIEVT 0x04 +#define STM32_MBOX_SYSCMD 0x10 +#define STM32_MBOX_SYSEVT 0x12 +#define STM32_MBOX_SYSACK 0xe0 /* Mailbox configuration helpers */ -#define STM32WB_MBOX_BLE_ATT_DEFAULT_MTU 23 -#define STM32WB_MBOX_C2_MEM_BLOCK_SZ 32 +#define STM32_MBOX_BLE_ATT_DEFAULT_MTU 23 +#define STM32_MBOX_C2_MEM_BLOCK_SZ 32 #define DIV_UP(a, b) (((a) + (b) - 1) / (b)) -#define STM32WB_MBOX_DEFAULT_BLE_PREP_WRITE_NUM(max_mtu) \ - (DIV_UP((max_mtu), STM32WB_MBOX_BLE_ATT_DEFAULT_MTU - 5) * 2) +#define STM32_MBOX_DEFAULT_BLE_PREP_WRITE_NUM(max_mtu) \ + (DIV_UP((max_mtu), STM32_MBOX_BLE_ATT_DEFAULT_MTU - 5) * 2) -#define STM32WB_MBOX_DEFAULT_C2_MEM_BLOCK_NUM(max_mtu, max_conn, pw) \ - ((pw) + ((max_conn) + 1) * (DIV_UP((max_mtu) + 4, STM32WB_MBOX_C2_MEM_BLOCK_SZ) + 2)) +#define STM32_MBOX_DEFAULT_C2_MEM_BLOCK_NUM(max_mtu, max_conn, pw) \ + ((pw) + ((max_conn) + 1) * (DIV_UP((max_mtu) + 4, STM32_MBOX_C2_MEM_BLOCK_SZ) + 2)) /**************************************************************************** * Public Types @@ -77,7 +77,7 @@ /* Mailbox data transfer packets */ -begin_packed_struct struct stm32wb_mbox_evt_s +begin_packed_struct struct stm32_mbox_evt_s { uint8_t type; union @@ -87,9 +87,9 @@ begin_packed_struct struct stm32wb_mbox_evt_s }; } end_packed_struct; -begin_packed_struct struct stm32wb_mbox_cmd_s +begin_packed_struct struct stm32_mbox_cmd_s { - stm32wb_mbox_list_t list_hdr; + stm32_mbox_list_t list_hdr; uint8_t type; union { @@ -100,14 +100,14 @@ begin_packed_struct struct stm32wb_mbox_cmd_s /* Mailbox receive event handler type */ -typedef int (*stm32wb_mbox_evt_handler_t)(struct stm32wb_mbox_evt_s *); +typedef int (*stm32_mbox_evt_handler_t)(struct stm32_mbox_evt_s *); /**************************************************************************** * Public Function Prototypes ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_mboxinitialize + * Name: stm32_mboxinitialize * * Description: * Initialize mailbox driver memory. @@ -117,10 +117,10 @@ typedef int (*stm32wb_mbox_evt_handler_t)(struct stm32wb_mbox_evt_s *); * ****************************************************************************/ -void stm32wb_mboxinitialize(stm32wb_mbox_evt_handler_t evt_handler); +void stm32_mboxinitialize(stm32_mbox_evt_handler_t evt_handler); /**************************************************************************** - * Name: stm32wb_mboxenable + * Name: stm32_mboxenable * * Description: * Enable mailbox hardware and start communication. The CPU2 responses @@ -128,10 +128,10 @@ void stm32wb_mboxinitialize(stm32wb_mbox_evt_handler_t evt_handler); * ****************************************************************************/ -void stm32wb_mboxenable(void); +void stm32_mboxenable(void); /**************************************************************************** - * Name: stm32wb_mbox_syscmd + * Name: stm32_mbox_syscmd * * Description: * Send command over mailbox system channel. Command data must be @@ -139,10 +139,10 @@ void stm32wb_mboxenable(void); * ****************************************************************************/ -int stm32wb_mbox_syscmd(void *data, size_t len); +int stm32_mbox_syscmd(void *data, size_t len); /**************************************************************************** - * Name: stm32wb_mbox_blecmd + * Name: stm32_mbox_blecmd * * Description: * Send command over mailbox BLE channel. Command data must be @@ -150,10 +150,10 @@ int stm32wb_mbox_syscmd(void *data, size_t len); * ****************************************************************************/ -int stm32wb_mbox_blecmd(void *data, size_t len); +int stm32_mbox_blecmd(void *data, size_t len); /**************************************************************************** - * Name: stm32wb_mbox_bleacl + * Name: stm32_mbox_bleacl * * Description: * Send BLE ACL data over mailbox BLE ACL channel. Data must be @@ -161,16 +161,16 @@ int stm32wb_mbox_blecmd(void *data, size_t len); * ****************************************************************************/ -int stm32wb_mbox_bleacl(void *data, size_t len); +int stm32_mbox_bleacl(void *data, size_t len); /**************************************************************************** - * Name: stm32wb_mbox_bleinit + * Name: stm32_mbox_bleinit * * Description: * Initialize and start BLE subsystem with provided configuration params. * ****************************************************************************/ -void stm32wb_mbox_bleinit(struct stm32wb_shci_ble_init_cfg_s *params); +void stm32_mbox_bleinit(struct stm32_shci_ble_init_cfg_s *params); -#endif /* __ARCH_ARM_SRC_STM32WB_STM32WB_MBOX_H */ +#endif /* __ARCH_ARM_SRC_STM32WB_STM32_MBOX_H */ diff --git a/arch/arm/src/stm32wb/stm32wb_mbox_list.h b/arch/arm/src/stm32wb/stm32wb_mbox_list.h index 4208da7fbec04..35f9e3cb1e595 100644 --- a/arch/arm/src/stm32wb/stm32wb_mbox_list.h +++ b/arch/arm/src/stm32wb/stm32wb_mbox_list.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32WB_STM32WB_MBOX_LIST_H -#define __ARCH_ARM_SRC_STM32WB_STM32WB_MBOX_LIST_H +#ifndef __ARCH_ARM_SRC_STM32WB_STM32_MBOX_LIST_H +#define __ARCH_ARM_SRC_STM32WB_STM32_MBOX_LIST_H /**************************************************************************** * Included Files @@ -38,42 +38,42 @@ * a new list_moveall function. */ -begin_packed_struct struct stm32wb_mbox_list_s +begin_packed_struct struct stm32_mbox_list_s { - struct stm32wb_mbox_list_s *next; - struct stm32wb_mbox_list_s *prev; + struct stm32_mbox_list_s *next; + struct stm32_mbox_list_s *prev; } end_packed_struct; -typedef struct stm32wb_mbox_list_s stm32wb_mbox_list_t; +typedef struct stm32_mbox_list_s stm32_mbox_list_t; /**************************************************************************** * Inline Functions ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_mbox_list_initialize + * Name: stm32_mbox_list_initialize * * Description: * Initialize internal fields. * ****************************************************************************/ -static inline void stm32wb_mbox_list_initialize(stm32wb_mbox_list_t *list) +static inline void stm32_mbox_list_initialize(stm32_mbox_list_t *list) { list->prev = list; list->next = list; } /**************************************************************************** - * Name: stm32wb_mbox_list_add_tail + * Name: stm32_mbox_list_add_tail * * Description: * Add new node at the end of the list. * ****************************************************************************/ -static inline void stm32wb_mbox_list_add_tail(stm32wb_mbox_list_t *list, - stm32wb_mbox_list_t *item) +static inline void stm32_mbox_list_add_tail(stm32_mbox_list_t *list, + stm32_mbox_list_t *item) { item->prev = list->prev; item->next = list; @@ -82,19 +82,19 @@ static inline void stm32wb_mbox_list_add_tail(stm32wb_mbox_list_t *list, } /**************************************************************************** - * Name: stm32wb_mbox_list_remove_head + * Name: stm32_mbox_list_remove_head * * Description: * Remove and return first node from the list head (if any). * ****************************************************************************/ -static inline stm32wb_mbox_list_t * -stm32wb_mbox_list_remove_head(stm32wb_mbox_list_t *list) +static inline stm32_mbox_list_t * +stm32_mbox_list_remove_head(stm32_mbox_list_t *list) { if (list->next != list) { - stm32wb_mbox_list_t *item = list->next; + stm32_mbox_list_t *item = list->next; item->next->prev = item->prev; item->prev->next = item->next; item->prev = NULL; @@ -108,20 +108,20 @@ stm32wb_mbox_list_remove_head(stm32wb_mbox_list_t *list) } /**************************************************************************** - * Name: stm32wb_mbox_list_is_empty + * Name: stm32_mbox_list_is_empty * * Description: * Check if the list is empty. * ****************************************************************************/ -static inline bool stm32wb_mbox_list_is_empty(stm32wb_mbox_list_t *list) +static inline bool stm32_mbox_list_is_empty(stm32_mbox_list_t *list) { return (list->next == list); } /**************************************************************************** - * Name: stm32wb_mbox_list_moveall + * Name: stm32_mbox_list_moveall * * Description: * Remove all nodes from source list and add them to the end of the @@ -129,8 +129,8 @@ static inline bool stm32wb_mbox_list_is_empty(stm32wb_mbox_list_t *list) * ****************************************************************************/ -static inline void stm32wb_mbox_list_moveall(stm32wb_mbox_list_t *src, - stm32wb_mbox_list_t *dst) +static inline void stm32_mbox_list_moveall(stm32_mbox_list_t *src, + stm32_mbox_list_t *dst) { if (src->next != src) { @@ -143,4 +143,4 @@ static inline void stm32wb_mbox_list_moveall(stm32wb_mbox_list_t *src, } } -#endif /* __ARCH_ARM_SRC_STM32WB_STM32WB_MBOX_LIST_H */ +#endif /* __ARCH_ARM_SRC_STM32WB_STM32_MBOX_LIST_H */ diff --git a/arch/arm/src/stm32wb/stm32wb_mbox_shci.h b/arch/arm/src/stm32wb/stm32wb_mbox_shci.h index 68536c3cfcb96..267d6dad3f513 100644 --- a/arch/arm/src/stm32wb/stm32wb_mbox_shci.h +++ b/arch/arm/src/stm32wb/stm32wb_mbox_shci.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32WB_STM32WB_MBOX_SHCI_H -#define __ARCH_ARM_SRC_STM32WB_STM32WB_MBOX_SHCI_H +#ifndef __ARCH_ARM_SRC_STM32WB_STM32_MBOX_SHCI_H +#define __ARCH_ARM_SRC_STM32WB_STM32_MBOX_SHCI_H /**************************************************************************** * Included Files @@ -37,89 +37,89 @@ /* SHCI event types *********************************************************/ -#define STM32WB_SHCI_ASYNC_EVT 0xff +#define STM32_SHCI_ASYNC_EVT 0xff /* SHCI async event subtypes */ -#define STM32WB_SHCI_ASYNC_EVT_C2RDY 0x9200 +#define STM32_SHCI_ASYNC_EVT_C2RDY 0x9200 /* SHCI system command acknowledgement events */ -#define STM32WB_SHCI_ACK_EVT_C2RDY 0x05 +#define STM32_SHCI_ACK_EVT_C2RDY 0x05 /* SHCI command opcodes *****************************************************/ -#define STM32WB_SHCI_OGF 0x3f -#define STM32WB_SHCI_OP(ogf, ocf) (((ogf) << 10) | (ocf)) - -#define STM32WB_SHCI_FUS_GET_STATE STM32WB_SHCI_OP(STM32WB_SHCI_OGF, 0x52) -#define STM32WB_SHCI_FUS_FW_UPGRADE STM32WB_SHCI_OP(STM32WB_SHCI_OGF, 0x54) -#define STM32WB_SHCI_FUS_FW_DELETE STM32WB_SHCI_OP(STM32WB_SHCI_OGF, 0x55) -#define STM32WB_SHCI_FUS_UPDATE_AUTH_KEY STM32WB_SHCI_OP(STM32WB_SHCI_OGF, 0x56) -#define STM32WB_SHCI_FUS_LOCK_AUTH_KEY STM32WB_SHCI_OP(STM32WB_SHCI_OGF, 0x57) -#define STM32WB_SHCI_FUS_STORE_USR_KEY STM32WB_SHCI_OP(STM32WB_SHCI_OGF, 0x58) -#define STM32WB_SHCI_FUS_LOAD_USR_KEY STM32WB_SHCI_OP(STM32WB_SHCI_OGF, 0x59) -#define STM32WB_SHCI_FUS_START_WS STM32WB_SHCI_OP(STM32WB_SHCI_OGF, 0x5a) -#define STM32WB_SHCI_FUS_LOCK_USR_KEY STM32WB_SHCI_OP(STM32WB_SHCI_OGF, 0x5d) -#define STM32WB_SHCI_FUS_UNLOAD_USR_KEY STM32WB_SHCI_OP(STM32WB_SHCI_OGF, 0x5e) -#define STM32WB_SHCI_FUS_ANTIROLLBACK STM32WB_SHCI_OP(STM32WB_SHCI_OGF, 0x5f) -#define STM32WB_SHCI_BLE_INIT STM32WB_SHCI_OP(STM32WB_SHCI_OGF, 0x66) -#define STM32WB_SHCI_THREAD_INIT STM32WB_SHCI_OP(STM32WB_SHCI_OGF, 0x67) -#define STM32WB_SHCI_DEBUG_INIT STM32WB_SHCI_OP(STM32WB_SHCI_OGF, 0x68) -#define STM32WB_SHCI_FLASH_ERASE_ACTIVITY STM32WB_SHCI_OP(STM32WB_SHCI_OGF, 0x69) -#define STM32WB_SHCI_CONCURRENT_SET_MODE STM32WB_SHCI_OP(STM32WB_SHCI_OGF, 0x6a) -#define STM32WB_SHCI_FLASH_STORE_DATA STM32WB_SHCI_OP(STM32WB_SHCI_OGF, 0x6b) -#define STM32WB_SHCI_FLASH_ERASE_DATA STM32WB_SHCI_OP(STM32WB_SHCI_OGF, 0x6c) -#define STM32WB_SHCI_RADIO_ALLOW_LOW_POWER STM32WB_SHCI_OP(STM32WB_SHCI_OGF, 0x6d) -#define STM32WB_SHCI_MAC_802154_INIT STM32WB_SHCI_OP(STM32WB_SHCI_OGF, 0x6e) -#define STM32WB_SHCI_REINIT STM32WB_SHCI_OP(STM32WB_SHCI_OGF, 0x6f) -#define STM32WB_SHCI_ZIGBEE_INIT STM32WB_SHCI_OP(STM32WB_SHCI_OGF, 0x70) -#define STM32WB_SHCI_LLD_TESTS_INIT STM32WB_SHCI_OP(STM32WB_SHCI_OGF, 0x71) -#define STM32WB_SHCI_EXTPA_CONFIG STM32WB_SHCI_OP(STM32WB_SHCI_OGF, 0x72) -#define STM32WB_SHCI_SET_FLASH_CONTROL STM32WB_SHCI_OP(STM32WB_SHCI_OGF, 0x73) -#define STM32WB_SHCI_BLE_LLD_INIT STM32WB_SHCI_OP(STM32WB_SHCI_OGF, 0x74) -#define STM32WB_SHCI_CONFIG STM32WB_SHCI_OP(STM32WB_SHCI_OGF, 0x75) -#define STM32WB_SHCI_GET_NEXT_BLE_EVT_TIME STM32WB_SHCI_OP(STM32WB_SHCI_OGF, 0x76) -#define STM32WB_SHCI_ENABLE_NEXT_802154_NF STM32WB_SHCI_OP(STM32WB_SHCI_OGF, 0x77) -#define STM32WB_SHCI_802_15_4_DEINIT STM32WB_SHCI_OP(STM32WB_SHCI_OGF, 0x78) +#define STM32_SHCI_OGF 0x3f +#define STM32_SHCI_OP(ogf, ocf) (((ogf) << 10) | (ocf)) + +#define STM32_SHCI_FUS_GET_STATE STM32_SHCI_OP(STM32_SHCI_OGF, 0x52) +#define STM32_SHCI_FUS_FW_UPGRADE STM32_SHCI_OP(STM32_SHCI_OGF, 0x54) +#define STM32_SHCI_FUS_FW_DELETE STM32_SHCI_OP(STM32_SHCI_OGF, 0x55) +#define STM32_SHCI_FUS_UPDATE_AUTH_KEY STM32_SHCI_OP(STM32_SHCI_OGF, 0x56) +#define STM32_SHCI_FUS_LOCK_AUTH_KEY STM32_SHCI_OP(STM32_SHCI_OGF, 0x57) +#define STM32_SHCI_FUS_STORE_USR_KEY STM32_SHCI_OP(STM32_SHCI_OGF, 0x58) +#define STM32_SHCI_FUS_LOAD_USR_KEY STM32_SHCI_OP(STM32_SHCI_OGF, 0x59) +#define STM32_SHCI_FUS_START_WS STM32_SHCI_OP(STM32_SHCI_OGF, 0x5a) +#define STM32_SHCI_FUS_LOCK_USR_KEY STM32_SHCI_OP(STM32_SHCI_OGF, 0x5d) +#define STM32_SHCI_FUS_UNLOAD_USR_KEY STM32_SHCI_OP(STM32_SHCI_OGF, 0x5e) +#define STM32_SHCI_FUS_ANTIROLLBACK STM32_SHCI_OP(STM32_SHCI_OGF, 0x5f) +#define STM32_SHCI_BLE_INIT STM32_SHCI_OP(STM32_SHCI_OGF, 0x66) +#define STM32_SHCI_THREAD_INIT STM32_SHCI_OP(STM32_SHCI_OGF, 0x67) +#define STM32_SHCI_DEBUG_INIT STM32_SHCI_OP(STM32_SHCI_OGF, 0x68) +#define STM32_SHCI_FLASH_ERASE_ACTIVITY STM32_SHCI_OP(STM32_SHCI_OGF, 0x69) +#define STM32_SHCI_CONCURRENT_SET_MODE STM32_SHCI_OP(STM32_SHCI_OGF, 0x6a) +#define STM32_SHCI_FLASH_STORE_DATA STM32_SHCI_OP(STM32_SHCI_OGF, 0x6b) +#define STM32_SHCI_FLASH_ERASE_DATA STM32_SHCI_OP(STM32_SHCI_OGF, 0x6c) +#define STM32_SHCI_RADIO_ALLOW_LOW_POWER STM32_SHCI_OP(STM32_SHCI_OGF, 0x6d) +#define STM32_SHCI_MAC_802154_INIT STM32_SHCI_OP(STM32_SHCI_OGF, 0x6e) +#define STM32_SHCI_REINIT STM32_SHCI_OP(STM32_SHCI_OGF, 0x6f) +#define STM32_SHCI_ZIGBEE_INIT STM32_SHCI_OP(STM32_SHCI_OGF, 0x70) +#define STM32_SHCI_LLD_TESTS_INIT STM32_SHCI_OP(STM32_SHCI_OGF, 0x71) +#define STM32_SHCI_EXTPA_CONFIG STM32_SHCI_OP(STM32_SHCI_OGF, 0x72) +#define STM32_SHCI_SET_FLASH_CONTROL STM32_SHCI_OP(STM32_SHCI_OGF, 0x73) +#define STM32_SHCI_BLE_LLD_INIT STM32_SHCI_OP(STM32_SHCI_OGF, 0x74) +#define STM32_SHCI_CONFIG STM32_SHCI_OP(STM32_SHCI_OGF, 0x75) +#define STM32_SHCI_GET_NEXT_BLE_EVT_TIME STM32_SHCI_OP(STM32_SHCI_OGF, 0x76) +#define STM32_SHCI_ENABLE_NEXT_802154_NF STM32_SHCI_OP(STM32_SHCI_OGF, 0x77) +#define STM32_SHCI_802_15_4_DEINIT STM32_SHCI_OP(STM32_SHCI_OGF, 0x78) /* Command params bitfield definitions **************************************/ /* BLE init command option flags */ -#define STM32WB_SHCI_BLE_INIT_OPT_STACK_MASK (1 << 0) /* Bit 0: BLE stack select */ -# define STM32WB_SHCI_BLE_INIT_OPT_STACK_LL_HOST (0 << 0) /* 0x0: Link Layer and Host */ -# define STM32WB_SHCI_BLE_INIT_OPT_STACK_LL (1 << 0) /* 0x1: Link Layer only */ +#define STM32_SHCI_BLE_INIT_OPT_STACK_MASK (1 << 0) /* Bit 0: BLE stack select */ +# define STM32_SHCI_BLE_INIT_OPT_STACK_LL_HOST (0 << 0) /* 0x0: Link Layer and Host */ +# define STM32_SHCI_BLE_INIT_OPT_STACK_LL (1 << 0) /* 0x1: Link Layer only */ -#define STM32WB_SHCI_BLE_INIT_OPT_SVC_CHCHAR_MASK (1 << 1) /* Bit 1: Service Changed characteristic */ -# define STM32WB_SHCI_BLE_INIT_OPT_SVC_CHCHAR_ENABLED (0 << 1) /* 0x0: Characteristic enabled */ -# define STM32WB_SHCI_BLE_INIT_OPT_SVC_CHCHAR_DISABLED (1 << 1) /* 0x1: Characteristic disabled */ +#define STM32_SHCI_BLE_INIT_OPT_SVC_CHCHAR_MASK (1 << 1) /* Bit 1: Service Changed characteristic */ +# define STM32_SHCI_BLE_INIT_OPT_SVC_CHCHAR_ENABLED (0 << 1) /* 0x0: Characteristic enabled */ +# define STM32_SHCI_BLE_INIT_OPT_SVC_CHCHAR_DISABLED (1 << 1) /* 0x1: Characteristic disabled */ -#define STM32WB_SHCI_BLE_INIT_OPT_DEVICE_NAME_MODE_MASK (1 << 2) /* Bit 2: Device Name mode */ -# define STM32WB_SHCI_BLE_INIT_OPT_DEVICE_NAME_MODE_RW (0 << 2) /* 0x0: Read-Write mode */ -# define STM32WB_SHCI_BLE_INIT_OPT_DEVICE_NAME_MODE_RO (1 << 2) /* 0x1: Read-Only mode */ +#define STM32_SHCI_BLE_INIT_OPT_DEVICE_NAME_MODE_MASK (1 << 2) /* Bit 2: Device Name mode */ +# define STM32_SHCI_BLE_INIT_OPT_DEVICE_NAME_MODE_RW (0 << 2) /* 0x0: Read-Write mode */ +# define STM32_SHCI_BLE_INIT_OPT_DEVICE_NAME_MODE_RO (1 << 2) /* 0x1: Read-Only mode */ -#define STM32WB_SHCI_BLE_INIT_OPT_CS_ALG2_MASK (1 << 4) /* Bit 4: Channel selection algorithm 2 enabled */ -# define STM32WB_SHCI_BLE_INIT_OPT_CS_ALG2_DISABLED (0 << 4) /* 0x0: Algorithm 2 disabled */ -# define STM32WB_SHCI_BLE_INIT_OPT_CS_ALG2_ENABLED (1 << 4) /* 0x1: Algorithm 2 enabled */ +#define STM32_SHCI_BLE_INIT_OPT_CS_ALG2_MASK (1 << 4) /* Bit 4: Channel selection algorithm 2 enabled */ +# define STM32_SHCI_BLE_INIT_OPT_CS_ALG2_DISABLED (0 << 4) /* 0x0: Algorithm 2 disabled */ +# define STM32_SHCI_BLE_INIT_OPT_CS_ALG2_ENABLED (1 << 4) /* 0x1: Algorithm 2 enabled */ -#define STM32WB_SHCI_BLE_INIT_OPT_POWER_CLASS_MASK (1 << 7) /* Bit 7: Power class */ -# define STM32WB_SHCI_BLE_INIT_OPT_POWER_CLASS_2_3 (0 << 7) /* 0x0: Power Class 2-3 */ -# define STM32WB_SHCI_BLE_INIT_OPT_POWER_CLASS_1 (1 << 7) /* 0x1: Power Class 1 */ +#define STM32_SHCI_BLE_INIT_OPT_POWER_CLASS_MASK (1 << 7) /* Bit 7: Power class */ +# define STM32_SHCI_BLE_INIT_OPT_POWER_CLASS_2_3 (0 << 7) /* 0x0: Power Class 2-3 */ +# define STM32_SHCI_BLE_INIT_OPT_POWER_CLASS_1 (1 << 7) /* 0x1: Power Class 1 */ /* BLE init command rx_model_config flags */ -#define STM32WB_SHCI_BLE_INIT_RXMOD_AGC_RSSI_MASK (1 << 0) /* Bit 0: AGC RSSI model */ -# define STM32WB_SHCI_BLE_INIT_RXMOD_AGC_RSSI_LEGACY (0 << 0) /* 0x0: AGC RSSI Legacy */ -# define STM32WB_SHCI_BLE_INIT_RXMOD_AGC_RSSI_IMPROVED (1 << 0) /* 0x1: AGC RSSI Improved */ +#define STM32_SHCI_BLE_INIT_RXMOD_AGC_RSSI_MASK (1 << 0) /* Bit 0: AGC RSSI model */ +# define STM32_SHCI_BLE_INIT_RXMOD_AGC_RSSI_LEGACY (0 << 0) /* 0x0: AGC RSSI Legacy */ +# define STM32_SHCI_BLE_INIT_RXMOD_AGC_RSSI_IMPROVED (1 << 0) /* 0x1: AGC RSSI Improved */ /**************************************************************************** * Public Types ****************************************************************************/ -/* STM32WB_SHCI_BLE_INIT command params */ +/* STM32_SHCI_BLE_INIT command params */ -begin_packed_struct struct stm32wb_shci_ble_init_cfg_s +begin_packed_struct struct stm32_shci_ble_init_cfg_s { void *ble_buf; /* Not used, must be NULL. */ uint32_t ble_buf_size; /* Not used, must be 0. */ @@ -185,4 +185,4 @@ begin_packed_struct struct stm32wb_shci_ble_init_cfg_s uint8_t rx_model_config; /* RX model config flags */ } end_packed_struct; -#endif /* __ARCH_ARM_SRC_STM32WB_STM32WB_MBOX_SHCI_H */ +#endif /* __ARCH_ARM_SRC_STM32WB_STM32_MBOX_SHCI_H */ diff --git a/arch/arm/src/stm32wb/stm32wb_mpuinit.c b/arch/arm/src/stm32wb/stm32wb_mpuinit.c index b9d878aadd047..acc1576a64611 100644 --- a/arch/arm/src/stm32wb/stm32wb_mpuinit.c +++ b/arch/arm/src/stm32wb/stm32wb_mpuinit.c @@ -41,7 +41,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_mpuinitialize + * Name: stm32_mpuinitialize * * Description: * Configure the MPU to permit user-space access to only restricted SAM3U @@ -49,7 +49,7 @@ * ****************************************************************************/ -void stm32wb_mpuinitialize(void) +void stm32_mpuinitialize(void) { uintptr_t datastart = MIN(USERSPACE->us_datastart, USERSPACE->us_bssstart); uintptr_t dataend = MAX(USERSPACE->us_dataend, USERSPACE->us_bssend); @@ -74,7 +74,7 @@ void stm32wb_mpuinitialize(void) } /**************************************************************************** - * Name: stm32wb_mpu_uheap + * Name: stm32_mpu_uheap * * Description: * Map the user-heap region. @@ -83,7 +83,7 @@ void stm32wb_mpuinitialize(void) * ****************************************************************************/ -void stm32wb_mpu_uheap(uintptr_t start, size_t size) +void stm32_mpu_uheap(uintptr_t start, size_t size) { mpu_user_intsram(start, size); } diff --git a/arch/arm/src/stm32wb/stm32wb_mpuinit.h b/arch/arm/src/stm32wb/stm32wb_mpuinit.h index 1cc8d755c37aa..bd15906f7d272 100644 --- a/arch/arm/src/stm32wb/stm32wb_mpuinit.h +++ b/arch/arm/src/stm32wb/stm32wb_mpuinit.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32WB_STM32WB_MPUINIT_H -#define __ARCH_ARM_SRC_STM32WB_STM32WB_MPUINIT_H +#ifndef __ARCH_ARM_SRC_STM32WB_STM32_MPUINIT_H +#define __ARCH_ARM_SRC_STM32WB_STM32_MPUINIT_H /**************************************************************************** * Included Files @@ -34,7 +34,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_mpuinitialize + * Name: stm32_mpuinitialize * * Description: * Configure the MPU to permit user-space access to only unrestricted MCU @@ -43,13 +43,13 @@ ****************************************************************************/ #ifdef CONFIG_BUILD_PROTECTED -void stm32wb_mpuinitialize(void); +void stm32_mpuinitialize(void); #else -# define stm32wb_mpuinitialize() +# define stm32_mpuinitialize() #endif /**************************************************************************** - * Name: stm32wb_mpu_uheap + * Name: stm32_mpu_uheap * * Description: * Map the user heap region. @@ -57,9 +57,9 @@ void stm32wb_mpuinitialize(void); ****************************************************************************/ #ifdef CONFIG_BUILD_PROTECTED -void stm32wb_mpu_uheap(uintptr_t start, size_t size); +void stm32_mpu_uheap(uintptr_t start, size_t size); #else -# define stm32wb_mpu_uheap(start,size) +# define stm32_mpu_uheap(start,size) #endif -#endif /* __ARCH_ARM_SRC_STM32WB_STM32WB_MPUINIT_H */ +#endif /* __ARCH_ARM_SRC_STM32WB_STM32_MPUINIT_H */ diff --git a/arch/arm/src/stm32wb/stm32wb_oneshot.c b/arch/arm/src/stm32wb/stm32wb_oneshot.c index ed0d899531cf0..80e63c4b4e9f8 100644 --- a/arch/arm/src/stm32wb/stm32wb_oneshot.c +++ b/arch/arm/src/stm32wb/stm32wb_oneshot.c @@ -39,26 +39,26 @@ #include "stm32wb_oneshot.h" -#ifdef CONFIG_STM32WB_ONESHOT +#ifdef CONFIG_STM32_ONESHOT /**************************************************************************** * Private Function Prototypes ****************************************************************************/ -static int stm32wb_oneshot_handler(int irq, void *context, void *arg); +static int stm32_oneshot_handler(int irq, void *context, void *arg); /**************************************************************************** * Private Data ****************************************************************************/ -static struct stm32wb_oneshot_s *g_oneshot[CONFIG_STM32WB_ONESHOT_MAXTIMERS]; +static struct stm32_oneshot_s *g_oneshot[CONFIG_STM32_ONESHOT_MAXTIMERS]; /**************************************************************************** * Private Functions ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_oneshot_handler + * Name: stm32_oneshot_handler * * Description: * Common timer interrupt callback. When any oneshot timer interrupt @@ -73,9 +73,9 @@ static struct stm32wb_oneshot_s *g_oneshot[CONFIG_STM32WB_ONESHOT_MAXTIMERS]; * ****************************************************************************/ -static int stm32wb_oneshot_handler(int irq, void *context, void *arg) +static int stm32_oneshot_handler(int irq, void *context, void *arg) { - struct stm32wb_oneshot_s *oneshot = (struct stm32wb_oneshot_s *)arg; + struct stm32_oneshot_s *oneshot = (struct stm32_oneshot_s *)arg; oneshot_handler_t oneshot_handler; void *oneshot_arg; @@ -86,10 +86,10 @@ static int stm32wb_oneshot_handler(int irq, void *context, void *arg) * Disable the TC now and disable any further interrupts. */ - STM32WB_TIM_SETISR(oneshot->tch, NULL, NULL, 0); - STM32WB_TIM_DISABLEINT(oneshot->tch, GTIM_DIER_UIE); - STM32WB_TIM_SETMODE(oneshot->tch, STM32WB_TIM_MODE_DISABLED); - STM32WB_TIM_ACKINT(oneshot->tch, GTIM_SR_UIF); + STM32_TIM_SETISR(oneshot->tch, NULL, NULL, 0); + STM32_TIM_DISABLEINT(oneshot->tch, GTIM_DIER_UIE); + STM32_TIM_SETMODE(oneshot->tch, STM32_TIM_MODE_DISABLED); + STM32_TIM_ACKINT(oneshot->tch, GTIM_SR_UIF); /* The timer is no longer running */ @@ -107,7 +107,7 @@ static int stm32wb_oneshot_handler(int irq, void *context, void *arg) } /**************************************************************************** - * Name: stm32wb_allocate_handler + * Name: stm32_allocate_handler * * Description: * Allocate a timer callback handler for the oneshot instance. @@ -117,19 +117,19 @@ static int stm32wb_oneshot_handler(int irq, void *context, void *arg) * * Returned Value: * Returns zero (OK) on success. This can only fail if the number of - * timers exceeds CONFIG_STM32WB_ONESHOT_MAXTIMERS. + * timers exceeds CONFIG_STM32_ONESHOT_MAXTIMERS. * ****************************************************************************/ -static inline int stm32wb_allocate_handler(struct stm32wb_oneshot_s *oneshot) +static inline int stm32_allocate_handler(struct stm32_oneshot_s *oneshot) { -#if CONFIG_STM32WB_ONESHOT_MAXTIMERS > 1 +#if CONFIG_STM32_ONESHOT_MAXTIMERS > 1 int ret = -EBUSY; int i; /* Search for an unused handler */ - for (i = 0; i < CONFIG_STM32WB_ONESHOT_MAXTIMERS; i++) + for (i = 0; i < CONFIG_STM32_ONESHOT_MAXTIMERS; i++) { /* Is this handler available? */ @@ -162,7 +162,7 @@ static inline int stm32wb_allocate_handler(struct stm32wb_oneshot_s *oneshot) ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_oneshot_initialize + * Name: stm32_oneshot_initialize * * Description: * Initialize the oneshot timer wrapper @@ -180,7 +180,7 @@ static inline int stm32wb_allocate_handler(struct stm32wb_oneshot_s *oneshot) * ****************************************************************************/ -int stm32wb_oneshot_initialize(struct stm32wb_oneshot_s *oneshot, +int stm32_oneshot_initialize(struct stm32_oneshot_s *oneshot, int chan, uint16_t resolution) { uint32_t frequency; @@ -193,14 +193,14 @@ int stm32wb_oneshot_initialize(struct stm32wb_oneshot_s *oneshot, frequency = USEC_PER_SEC / (uint32_t)resolution; oneshot->frequency = frequency; - oneshot->tch = stm32wb_tim_init(chan); + oneshot->tch = stm32_tim_init(chan); if (!oneshot->tch) { tmrerr("ERROR: Failed to allocate TIM%d\n", chan); return -EBUSY; } - STM32WB_TIM_SETCLOCK(oneshot->tch, frequency); + STM32_TIM_SETCLOCK(oneshot->tch, frequency); /* Initialize the remaining fields in the state structure. */ @@ -211,18 +211,18 @@ int stm32wb_oneshot_initialize(struct stm32wb_oneshot_s *oneshot, /* Assign a callback handler to the oneshot */ - return stm32wb_allocate_handler(oneshot); + return stm32_allocate_handler(oneshot); } /**************************************************************************** - * Name: stm32wb_oneshot_max_delay + * Name: stm32_oneshot_max_delay * * Description: * Determine the maximum delay of the one-shot timer (in microseconds) * ****************************************************************************/ -int stm32wb_oneshot_max_delay(struct stm32wb_oneshot_s *oneshot, +int stm32_oneshot_max_delay(struct stm32_oneshot_s *oneshot, uint64_t *usec) { DEBUGASSERT(oneshot != NULL && usec != NULL); @@ -233,7 +233,7 @@ int stm32wb_oneshot_max_delay(struct stm32wb_oneshot_s *oneshot, } /**************************************************************************** - * Name: stm32wb_oneshot_start + * Name: stm32_oneshot_start * * Description: * Start the oneshot timer @@ -241,7 +241,7 @@ int stm32wb_oneshot_max_delay(struct stm32wb_oneshot_s *oneshot, * Input Parameters: * oneshot Caller allocated instance of the oneshot state structure. This * structure must have been previously initialized via a call to - * stm32wb_oneshot_initialize(); + * stm32_oneshot_initialize(); * handler The function to call when when the oneshot timer expires. * arg An opaque argument that will accompany the callback. * ts Provides the duration of the one shot timer. @@ -252,7 +252,7 @@ int stm32wb_oneshot_max_delay(struct stm32wb_oneshot_s *oneshot, * ****************************************************************************/ -int stm32wb_oneshot_start(struct stm32wb_oneshot_s *oneshot, +int stm32_oneshot_start(struct stm32_oneshot_s *oneshot, oneshot_handler_t handler, void *arg, const struct timespec *ts) { @@ -273,7 +273,7 @@ int stm32wb_oneshot_start(struct stm32wb_oneshot_s *oneshot, /* Yes.. then cancel it */ tmrinfo("Already running... cancelling\n"); - stm32wb_oneshot_cancel(oneshot, NULL); + stm32_oneshot_cancel(oneshot, NULL); } /* Save the new handler and its argument */ @@ -301,19 +301,19 @@ int stm32wb_oneshot_start(struct stm32wb_oneshot_s *oneshot, /* Set up to receive the callback when the interrupt occurs */ - STM32WB_TIM_SETISR(oneshot->tch, stm32wb_oneshot_handler, oneshot, 0); + STM32_TIM_SETISR(oneshot->tch, stm32_oneshot_handler, oneshot, 0); /* Set timer period */ oneshot->period = (uint32_t)period; - STM32WB_TIM_SETPERIOD(oneshot->tch, (uint32_t)period); + STM32_TIM_SETPERIOD(oneshot->tch, (uint32_t)period); /* Start the counter */ - STM32WB_TIM_SETMODE(oneshot->tch, STM32WB_TIM_MODE_PULSE); + STM32_TIM_SETMODE(oneshot->tch, STM32_TIM_MODE_PULSE); - STM32WB_TIM_ACKINT(oneshot->tch, GTIM_SR_UIF); - STM32WB_TIM_ENABLEINT(oneshot->tch, GTIM_DIER_UIE); + STM32_TIM_ACKINT(oneshot->tch, GTIM_SR_UIF); + STM32_TIM_ENABLEINT(oneshot->tch, GTIM_DIER_UIE); /* Enable interrupts. We should get the callback when the interrupt * occurs. @@ -325,7 +325,7 @@ int stm32wb_oneshot_start(struct stm32wb_oneshot_s *oneshot, } /**************************************************************************** - * Name: stm32wb_oneshot_cancel + * Name: stm32_oneshot_cancel * * Description: * Cancel the oneshot timer and return the time remaining on the timer. @@ -336,7 +336,7 @@ int stm32wb_oneshot_start(struct stm32wb_oneshot_s *oneshot, * Input Parameters: * oneshot Caller allocated instance of the oneshot state structure. This * structure must have been previously initialized via a call to - * stm32wb_oneshot_initialize(); + * stm32_oneshot_initialize(); * ts The location in which to return the time remaining on the * oneshot timer. A time of zero is returned if the timer is * not running. ts may be zero in which case the time remaining @@ -349,7 +349,7 @@ int stm32wb_oneshot_start(struct stm32wb_oneshot_s *oneshot, * ****************************************************************************/ -int stm32wb_oneshot_cancel(struct stm32wb_oneshot_s *oneshot, +int stm32_oneshot_cancel(struct stm32_oneshot_s *oneshot, struct timespec *ts) { irqstate_t flags; @@ -388,14 +388,14 @@ int stm32wb_oneshot_cancel(struct stm32wb_oneshot_s *oneshot, tmrinfo("Cancelling...\n"); - count = STM32WB_TIM_GETCOUNTER(oneshot->tch); + count = STM32_TIM_GETCOUNTER(oneshot->tch); period = oneshot->period; /* Now we can disable the interrupt and stop the timer. */ - STM32WB_TIM_DISABLEINT(oneshot->tch, GTIM_DIER_UIE); - STM32WB_TIM_SETISR(oneshot->tch, NULL, NULL, 0); - STM32WB_TIM_SETMODE(oneshot->tch, STM32WB_TIM_MODE_DISABLED); + STM32_TIM_DISABLEINT(oneshot->tch, GTIM_DIER_UIE); + STM32_TIM_SETISR(oneshot->tch, NULL, NULL, 0); + STM32_TIM_SETMODE(oneshot->tch, STM32_TIM_MODE_DISABLED); oneshot->running = false; oneshot->handler = NULL; @@ -456,4 +456,4 @@ int stm32wb_oneshot_cancel(struct stm32wb_oneshot_s *oneshot, return OK; } -#endif /* CONFIG_STM32WB_ONESHOT */ +#endif /* CONFIG_STM32_ONESHOT */ diff --git a/arch/arm/src/stm32wb/stm32wb_oneshot.h b/arch/arm/src/stm32wb/stm32wb_oneshot.h index 37d45ac8ed204..9b02e37ca1cd4 100644 --- a/arch/arm/src/stm32wb/stm32wb_oneshot.h +++ b/arch/arm/src/stm32wb/stm32wb_oneshot.h @@ -36,22 +36,22 @@ #include "stm32wb_tim.h" -#ifdef CONFIG_STM32WB_ONESHOT +#ifdef CONFIG_STM32_ONESHOT /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ -#if !defined(CONFIG_STM32WB_ONESHOT_MAXTIMERS) || \ - CONFIG_STM32WB_ONESHOT_MAXTIMERS < 1 -# undef CONFIG_STM32WB_ONESHOT_MAXTIMERS -# define CONFIG_STM32WB_ONESHOT_MAXTIMERS 1 +#if !defined(CONFIG_STM32_ONESHOT_MAXTIMERS) || \ + CONFIG_STM32_ONESHOT_MAXTIMERS < 1 +# undef CONFIG_STM32_ONESHOT_MAXTIMERS +# define CONFIG_STM32_ONESHOT_MAXTIMERS 1 #endif -#if CONFIG_STM32WB_ONESHOT_MAXTIMERS > 8 +#if CONFIG_STM32_ONESHOT_MAXTIMERS > 8 # warning Additional logic required to handle more than 8 timers -# undef CONFIG_STM32WB_ONESHOT_MAXTIMERS -# define CONFIG_STM32WB_ONESHOT_MAXTIMERS 8 +# undef CONFIG_STM32_ONESHOT_MAXTIMERS +# define CONFIG_STM32_ONESHOT_MAXTIMERS 8 #endif /**************************************************************************** @@ -67,20 +67,20 @@ typedef void (*oneshot_handler_t)(void *arg); /* The oneshot client must allocate an instance of this structure and called - * stm32wb_oneshot_initialize() before using the oneshot facilities. The + * stm32_oneshot_initialize() before using the oneshot facilities. The * client should not access the contents of this structure directly since * the contents are subject to change. */ -struct stm32wb_oneshot_s +struct stm32_oneshot_s { uint8_t chan; /* The timer/counter in use */ -#if CONFIG_STM32WB_ONESHOT_MAXTIMERS > 1 +#if CONFIG_STM32_ONESHOT_MAXTIMERS > 1 uint8_t cbndx; /* Timer callback handler index */ #endif volatile bool running; /* True: the timer is running */ - struct stm32wb_tim_dev_s *tch; /* Pointer returned by - * stm32wb_tim_init() */ + struct stm32_tim_dev_s *tch; /* Pointer returned by + * stm32_tim_init() */ volatile oneshot_handler_t handler; /* Oneshot expiration callback */ volatile void *arg; /* The argument that will accompany * the callback */ @@ -106,7 +106,7 @@ extern "C" ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_oneshot_initialize + * Name: stm32_oneshot_initialize * * Description: * Initialize the oneshot timer wrapper @@ -124,22 +124,22 @@ extern "C" * ****************************************************************************/ -int stm32wb_oneshot_initialize(struct stm32wb_oneshot_s *oneshot, int chan, +int stm32_oneshot_initialize(struct stm32_oneshot_s *oneshot, int chan, uint16_t resolution); /**************************************************************************** - * Name: stm32wb_oneshot_max_delay + * Name: stm32_oneshot_max_delay * * Description: * Determine the maximum delay of the one-shot timer (in microseconds) * ****************************************************************************/ -int stm32wb_oneshot_max_delay(struct stm32wb_oneshot_s *oneshot, +int stm32_oneshot_max_delay(struct stm32_oneshot_s *oneshot, uint64_t *usec); /**************************************************************************** - * Name: stm32wb_oneshot_start + * Name: stm32_oneshot_start * * Description: * Start the oneshot timer @@ -147,7 +147,7 @@ int stm32wb_oneshot_max_delay(struct stm32wb_oneshot_s *oneshot, * Input Parameters: * oneshot Caller allocated instance of the oneshot state structure. This * structure must have been previously initialized via a call to - * stm32wb_oneshot_initialize(); + * stm32_oneshot_initialize(); * handler The function to call when when the oneshot timer expires. * arg An opaque argument that will accompany the callback. * ts Provides the duration of the one shot timer. @@ -158,12 +158,12 @@ int stm32wb_oneshot_max_delay(struct stm32wb_oneshot_s *oneshot, * ****************************************************************************/ -int stm32wb_oneshot_start(struct stm32wb_oneshot_s *oneshot, +int stm32_oneshot_start(struct stm32_oneshot_s *oneshot, oneshot_handler_t handler, void *arg, const struct timespec *ts); /**************************************************************************** - * Name: stm32wb_oneshot_cancel + * Name: stm32_oneshot_cancel * * Description: * Cancel the oneshot timer and return the time remaining on the timer. @@ -174,7 +174,7 @@ int stm32wb_oneshot_start(struct stm32wb_oneshot_s *oneshot, * Input Parameters: * oneshot Caller allocated instance of the oneshot state structure. This * structure must have been previously initialized via a call to - * stm32wb_oneshot_initialize(); + * stm32_oneshot_initialize(); * ts The location in which to return the time remaining on the * oneshot timer. A time of zero is returned if the timer is * not running. @@ -186,7 +186,7 @@ int stm32wb_oneshot_start(struct stm32wb_oneshot_s *oneshot, * ****************************************************************************/ -int stm32wb_oneshot_cancel(struct stm32wb_oneshot_s *oneshot, +int stm32_oneshot_cancel(struct stm32_oneshot_s *oneshot, struct timespec *ts); #undef EXTERN @@ -194,5 +194,5 @@ int stm32wb_oneshot_cancel(struct stm32wb_oneshot_s *oneshot, } #endif -#endif /* CONFIG_STM32WB_ONESHOT */ +#endif /* CONFIG_STM32_ONESHOT */ #endif /* __ARCH_ARM_SRC_STM32WB_STM32WB_ONESHOT_H */ diff --git a/arch/arm/src/stm32wb/stm32wb_oneshot_lowerhalf.c b/arch/arm/src/stm32wb/stm32wb_oneshot_lowerhalf.c index 4c1b7030377cf..d98270362c4b7 100644 --- a/arch/arm/src/stm32wb/stm32wb_oneshot_lowerhalf.c +++ b/arch/arm/src/stm32wb/stm32wb_oneshot_lowerhalf.c @@ -45,32 +45,32 @@ * driver */ -struct stm32wb_oneshot_lowerhalf_s +struct stm32_oneshot_lowerhalf_s { /* This is the part of the lower half driver that is visible to the upper- * half client of the driver. This must be the first thing in this * structure so that pointers to struct oneshot_lowerhalf_s are cast - * compatible to struct stm32wb_oneshot_lowerhalf_s and vice versa. + * compatible to struct stm32_oneshot_lowerhalf_s and vice versa. */ struct oneshot_lowerhalf_s lh; /* Common lower-half driver fields */ /* Private lower half data follows */ - struct stm32wb_oneshot_s oneshot; /* STM32-specific oneshot state */ + struct stm32_oneshot_s oneshot; /* STM32-specific oneshot state */ }; /**************************************************************************** * Private Function Prototypes ****************************************************************************/ -static void stm32wb_oneshot_handler(void *arg); +static void stm32_oneshot_handler(void *arg); -static int stm32wb_max_delay(struct oneshot_lowerhalf_s *lower, +static int stm32_max_delay(struct oneshot_lowerhalf_s *lower, struct timespec *ts); -static int stm32wb_start(struct oneshot_lowerhalf_s *lower, +static int stm32_start(struct oneshot_lowerhalf_s *lower, const struct timespec *ts); -static int stm32wb_cancel(struct oneshot_lowerhalf_s *lower, +static int stm32_cancel(struct oneshot_lowerhalf_s *lower, struct timespec *ts); /**************************************************************************** @@ -81,9 +81,9 @@ static int stm32wb_cancel(struct oneshot_lowerhalf_s *lower, static const struct oneshot_operations_s g_oneshot_ops = { - .max_delay = stm32wb_max_delay, - .start = stm32wb_start, - .cancel = stm32wb_cancel, + .max_delay = stm32_max_delay, + .start = stm32_start, + .cancel = stm32_cancel, }; /**************************************************************************** @@ -91,13 +91,13 @@ static const struct oneshot_operations_s g_oneshot_ops = ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_oneshot_handler + * Name: stm32_oneshot_handler * * Description: * Timer expiration handler * * Input Parameters: - * arg - Should be the same argument provided when stm32wb_oneshot_start() + * arg - Should be the same argument provided when stm32_oneshot_start() * was called. * * Returned Value: @@ -105,22 +105,22 @@ static const struct oneshot_operations_s g_oneshot_ops = * ****************************************************************************/ -static void stm32wb_oneshot_handler(void *arg) +static void stm32_oneshot_handler(void *arg) { - struct stm32wb_oneshot_lowerhalf_s *priv = - (struct stm32wb_oneshot_lowerhalf_s *)arg; + struct stm32_oneshot_lowerhalf_s *priv = + (struct stm32_oneshot_lowerhalf_s *)arg; DEBUGASSERT(priv != NULL); /* Perhaps the callback was nullified in a race condition with - * stm32wb_cancel? + * stm32_cancel? */ oneshot_process_callback(&priv->lh); } /**************************************************************************** - * Name: stm32wb_max_delay + * Name: stm32_max_delay * * Description: * Determine the maximum delay of the one-shot timer (in microseconds) @@ -137,16 +137,16 @@ static void stm32wb_oneshot_handler(void *arg) * ****************************************************************************/ -static int stm32wb_max_delay(struct oneshot_lowerhalf_s *lower, +static int stm32_max_delay(struct oneshot_lowerhalf_s *lower, struct timespec *ts) { - struct stm32wb_oneshot_lowerhalf_s *priv = - (struct stm32wb_oneshot_lowerhalf_s *)lower; + struct stm32_oneshot_lowerhalf_s *priv = + (struct stm32_oneshot_lowerhalf_s *)lower; uint64_t usecs; int ret; DEBUGASSERT(priv != NULL && ts != NULL); - ret = stm32wb_oneshot_max_delay(&priv->oneshot, &usecs); + ret = stm32_oneshot_max_delay(&priv->oneshot, &usecs); if (ret >= 0) { uint64_t sec = usecs / 1000000; @@ -160,7 +160,7 @@ static int stm32wb_max_delay(struct oneshot_lowerhalf_s *lower, } /**************************************************************************** - * Name: stm32wb_start + * Name: stm32_start * * Description: * Start the oneshot timer @@ -179,11 +179,11 @@ static int stm32wb_max_delay(struct oneshot_lowerhalf_s *lower, * ****************************************************************************/ -static int stm32wb_start(struct oneshot_lowerhalf_s *lower, +static int stm32_start(struct oneshot_lowerhalf_s *lower, const struct timespec *ts) { - struct stm32wb_oneshot_lowerhalf_s *priv = - (struct stm32wb_oneshot_lowerhalf_s *)lower; + struct stm32_oneshot_lowerhalf_s *priv = + (struct stm32_oneshot_lowerhalf_s *)lower; irqstate_t flags; int ret; @@ -192,20 +192,20 @@ static int stm32wb_start(struct oneshot_lowerhalf_s *lower, /* Save the callback information and start the timer */ flags = enter_critical_section(); - ret = stm32wb_oneshot_start(&priv->oneshot, - stm32wb_oneshot_handler, priv, ts); + ret = stm32_oneshot_start(&priv->oneshot, + stm32_oneshot_handler, priv, ts); leave_critical_section(flags); if (ret < 0) { - tmrerr("ERROR: stm32wb_oneshot_start failed: %d\n", flags); + tmrerr("ERROR: stm32_oneshot_start failed: %d\n", flags); } return ret; } /**************************************************************************** - * Name: stm32wb_cancel + * Name: stm32_cancel * * Description: * Cancel the oneshot timer and return the time remaining on the timer. @@ -228,11 +228,11 @@ static int stm32wb_start(struct oneshot_lowerhalf_s *lower, * ****************************************************************************/ -static int stm32wb_cancel(struct oneshot_lowerhalf_s *lower, +static int stm32_cancel(struct oneshot_lowerhalf_s *lower, struct timespec *ts) { - struct stm32wb_oneshot_lowerhalf_s *priv = - (struct stm32wb_oneshot_lowerhalf_s *)lower; + struct stm32_oneshot_lowerhalf_s *priv = + (struct stm32_oneshot_lowerhalf_s *)lower; irqstate_t flags; int ret; @@ -241,12 +241,12 @@ static int stm32wb_cancel(struct oneshot_lowerhalf_s *lower, /* Cancel the timer */ flags = enter_critical_section(); - ret = stm32wb_oneshot_cancel(&priv->oneshot, ts); + ret = stm32_oneshot_cancel(&priv->oneshot, ts); leave_critical_section(flags); if (ret < 0) { - tmrerr("ERROR: stm32wb_oneshot_cancel failed: %d\n", flags); + tmrerr("ERROR: stm32_oneshot_cancel failed: %d\n", flags); } return ret; @@ -277,13 +277,13 @@ static int stm32wb_cancel(struct oneshot_lowerhalf_s *lower, struct oneshot_lowerhalf_s *oneshot_initialize(int chan, uint16_t resolution) { - struct stm32wb_oneshot_lowerhalf_s *priv; + struct stm32_oneshot_lowerhalf_s *priv; int ret; /* Allocate an instance of the lower half driver */ - priv = (struct stm32wb_oneshot_lowerhalf_s *) - kmm_zalloc(sizeof(struct stm32wb_oneshot_lowerhalf_s)); + priv = (struct stm32_oneshot_lowerhalf_s *) + kmm_zalloc(sizeof(struct stm32_oneshot_lowerhalf_s)); if (priv == NULL) { @@ -297,10 +297,10 @@ struct oneshot_lowerhalf_s *oneshot_initialize(int chan, uint16_t resolution) /* Initialize the contained STM32 oneshot timer */ - ret = stm32wb_oneshot_initialize(&priv->oneshot, chan, resolution); + ret = stm32_oneshot_initialize(&priv->oneshot, chan, resolution); if (ret < 0) { - tmrerr("ERROR: stm32wb_oneshot_initialize failed: %d\n", ret); + tmrerr("ERROR: stm32_oneshot_initialize failed: %d\n", ret); kmm_free(priv); return NULL; } diff --git a/arch/arm/src/stm32wb/stm32wb_pm.h b/arch/arm/src/stm32wb/stm32wb_pm.h index 3876288bc1a26..d30bf136c64d4 100644 --- a/arch/arm/src/stm32wb/stm32wb_pm.h +++ b/arch/arm/src/stm32wb/stm32wb_pm.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32WB_STM32WB_PM_H -#define __ARCH_ARM_SRC_STM32WB_STM32WB_PM_H +#ifndef __ARCH_ARM_SRC_STM32WB_STM32_PM_H +#define __ARCH_ARM_SRC_STM32WB_STM32_PM_H /**************************************************************************** * Included Files @@ -48,7 +48,7 @@ extern "C" #endif /**************************************************************************** - * Name: stm32wb_pmstop + * Name: stm32_pmstop * * Description: * Enter STOP mode. @@ -66,10 +66,10 @@ extern "C" * ****************************************************************************/ -int stm32wb_pmstop(bool lpds); +int stm32_pmstop(bool lpds); /**************************************************************************** - * Name: stm32wb_pmstop2 + * Name: stm32_pmstop2 * * Description: * Enter STOP2 mode. @@ -84,10 +84,10 @@ int stm32wb_pmstop(bool lpds); * ****************************************************************************/ -int stm32wb_pmstop2(void); +int stm32_pmstop2(void); /**************************************************************************** - * Name: stm32wb_pmstandby + * Name: stm32_pmstandby * * Description: * Enter STANDBY mode. @@ -103,10 +103,10 @@ int stm32wb_pmstop2(void); * ****************************************************************************/ -int stm32wb_pmstandby(void); +int stm32_pmstandby(void); /**************************************************************************** - * Name: stm32wb_pmsleep + * Name: stm32_pmsleep * * Description: * Enter SLEEP mode. @@ -122,10 +122,10 @@ int stm32wb_pmstandby(void); * ****************************************************************************/ -void stm32wb_pmsleep(bool sleeponexit); +void stm32_pmsleep(bool sleeponexit); /**************************************************************************** - * Name: stm32wb_pmlpr + * Name: stm32_pmlpr * * Description: * Enter Low-Power Run (LPR) mode. @@ -140,7 +140,7 @@ void stm32wb_pmsleep(bool sleeponexit); * ****************************************************************************/ -int stm32wb_pmlpr(void); +int stm32_pmlpr(void); #undef EXTERN #ifdef __cplusplus @@ -148,4 +148,4 @@ int stm32wb_pmlpr(void); #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32WB_STM32WB_PM_H */ +#endif /* __ARCH_ARM_SRC_STM32WB_STM32_PM_H */ diff --git a/arch/arm/src/stm32wb/stm32wb_pmlpr.c b/arch/arm/src/stm32wb/stm32wb_pmlpr.c index c81179f8c62b8..a86617edbfafb 100644 --- a/arch/arm/src/stm32wb/stm32wb_pmlpr.c +++ b/arch/arm/src/stm32wb/stm32wb_pmlpr.c @@ -39,7 +39,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_pmlpr + * Name: stm32_pmlpr * * Description: * Enter Low-Power Run (LPR) mode. @@ -54,40 +54,40 @@ * ****************************************************************************/ -int stm32wb_pmlpr(void) +int stm32_pmlpr(void) { uint32_t regval; /* Enable MSI clock */ - regval = getreg32(STM32WB_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_MSION; /* Set MSI clock to 2 MHz */ regval &= ~RCC_CR_MSIRANGE_MASK; regval |= RCC_CR_MSIRANGE_2M; /* 2 MHz */ - putreg32(regval, STM32WB_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Select MSI clock as system clock source */ - regval = getreg32(STM32WB_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_SW_MASK; regval |= RCC_CFGR_SW_MSI; - putreg32(regval, STM32WB_RCC_CFGR); + putreg32(regval, STM32_RCC_CFGR); /* Wait until the MSI source is used as the system clock source */ - while ((getreg32(STM32WB_RCC_CFGR) & RCC_CFGR_SWS_MASK) != + while ((getreg32(STM32_RCC_CFGR) & RCC_CFGR_SWS_MASK) != RCC_CFGR_SWS_MSI) { } /* Enable Low-Power Run */ - regval = getreg32(STM32WB_PWR_CR1); + regval = getreg32(STM32_PWR_CR1); regval |= PWR_CR1_LPR; - putreg32(regval, STM32WB_PWR_CR1); + putreg32(regval, STM32_PWR_CR1); return OK; } diff --git a/arch/arm/src/stm32wb/stm32wb_pmsleep.c b/arch/arm/src/stm32wb/stm32wb_pmsleep.c index b9b64dd940c1b..8a2b0d629673e 100644 --- a/arch/arm/src/stm32wb/stm32wb_pmsleep.c +++ b/arch/arm/src/stm32wb/stm32wb_pmsleep.c @@ -37,7 +37,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_pmsleep + * Name: stm32_pmsleep * * Description: * Enter SLEEP mode. @@ -53,7 +53,7 @@ * ****************************************************************************/ -void stm32wb_pmsleep(bool sleeponexit) +void stm32_pmsleep(bool sleeponexit) { uint32_t regval; diff --git a/arch/arm/src/stm32wb/stm32wb_pmstandby.c b/arch/arm/src/stm32wb/stm32wb_pmstandby.c index d1fd88ac03c50..09b81ae023680 100644 --- a/arch/arm/src/stm32wb/stm32wb_pmstandby.c +++ b/arch/arm/src/stm32wb/stm32wb_pmstandby.c @@ -37,7 +37,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_pmstandby + * Name: stm32_pmstandby * * Description: * Enter STANDBY mode. @@ -53,7 +53,7 @@ * ****************************************************************************/ -int stm32wb_pmstandby(void) +int stm32_pmstandby(void) { uint32_t regval; @@ -63,15 +63,15 @@ int stm32wb_pmstandby(void) regval = PWR_SCR_CWUF1 | PWR_SCR_CWUF2 | PWR_SCR_CWUF3 | PWR_SCR_CWUF4 | PWR_SCR_CWUF5; - putreg32(regval, STM32WB_PWR_SCR); + putreg32(regval, STM32_PWR_SCR); /* Select Standby mode */ - regval = getreg32(STM32WB_PWR_CR1); + regval = getreg32(STM32_PWR_CR1); regval &= ~PWR_CR1_LPMS_MASK; regval |= PWR_CR1_LPMS_STANDBY; - putreg32(regval, STM32WB_PWR_CR1); + putreg32(regval, STM32_PWR_CR1); /* Set SLEEPDEEP bit of Cortex System Control Register */ diff --git a/arch/arm/src/stm32wb/stm32wb_pmstop.c b/arch/arm/src/stm32wb/stm32wb_pmstop.c index 683af0cd07a24..31a53a9160219 100644 --- a/arch/arm/src/stm32wb/stm32wb_pmstop.c +++ b/arch/arm/src/stm32wb/stm32wb_pmstop.c @@ -72,7 +72,7 @@ static int do_stop(void) ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_pmstop + * Name: stm32_pmstop * * Description: * Enter STOP mode. @@ -90,7 +90,7 @@ static int do_stop(void) * ****************************************************************************/ -int stm32wb_pmstop(bool lpds) +int stm32_pmstop(bool lpds) { uint32_t regval; @@ -98,7 +98,7 @@ int stm32wb_pmstop(bool lpds) * register CR1. */ - regval = getreg32(STM32WB_PWR_CR1); + regval = getreg32(STM32_PWR_CR1); regval &= ~PWR_CR1_LPMS_MASK; /* Select Stop 1 mode with low-power regulator if so requested */ @@ -108,13 +108,13 @@ int stm32wb_pmstop(bool lpds) regval |= PWR_CR1_LPMS_STOP1; } - putreg32(regval, STM32WB_PWR_CR1); + putreg32(regval, STM32_PWR_CR1); return do_stop(); } /**************************************************************************** - * Name: stm32wb_pmstop2 + * Name: stm32_pmstop2 * * Description: * Enter STOP2 mode. @@ -129,16 +129,16 @@ int stm32wb_pmstop(bool lpds) * ****************************************************************************/ -int stm32wb_pmstop2(void) +int stm32_pmstop2(void) { uint32_t regval; /* Select Stop 2 mode in power control register 1. */ - regval = getreg32(STM32WB_PWR_CR1); + regval = getreg32(STM32_PWR_CR1); regval &= ~PWR_CR1_LPMS_MASK; regval |= PWR_CR1_LPMS_STOP2; - putreg32(regval, STM32WB_PWR_CR1); + putreg32(regval, STM32_PWR_CR1); return do_stop(); } diff --git a/arch/arm/src/stm32wb/stm32wb_pwr.c b/arch/arm/src/stm32wb/stm32wb_pwr.c index c13ca0b14803a..7e7338b9e1e59 100644 --- a/arch/arm/src/stm32wb/stm32wb_pwr.c +++ b/arch/arm/src/stm32wb/stm32wb_pwr.c @@ -39,20 +39,20 @@ * Private Functions ****************************************************************************/ -static inline uint16_t stm32wb_pwr_getreg(uint8_t offset) +static inline uint16_t stm32_pwr_getreg(uint8_t offset) { - return (uint16_t)getreg32(STM32WB_PWR_BASE + (uint32_t)offset); + return (uint16_t)getreg32(STM32_PWR_BASE + (uint32_t)offset); } -static inline void stm32wb_pwr_putreg(uint8_t offset, uint16_t value) +static inline void stm32_pwr_putreg(uint8_t offset, uint16_t value) { - putreg32((uint32_t)value, STM32WB_PWR_BASE + (uint32_t)offset); + putreg32((uint32_t)value, STM32_PWR_BASE + (uint32_t)offset); } -static inline void stm32wb_pwr_modifyreg(uint8_t offset, uint16_t clearbits, +static inline void stm32_pwr_modifyreg(uint8_t offset, uint16_t clearbits, uint16_t setbits) { - modifyreg32(STM32WB_PWR_BASE + (uint32_t)offset, + modifyreg32(STM32_PWR_BASE + (uint32_t)offset, (uint32_t)clearbits, (uint32_t)setbits); } @@ -61,7 +61,7 @@ static inline void stm32wb_pwr_modifyreg(uint8_t offset, uint16_t clearbits, ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_pwr_enablebkp + * Name: stm32_pwr_enablebkp * * Description: * Enables access to the backup domain (RTC registers and backup @@ -75,14 +75,14 @@ static inline void stm32wb_pwr_modifyreg(uint8_t offset, uint16_t clearbits, * ****************************************************************************/ -bool stm32wb_pwr_enablebkp(bool writable) +bool stm32_pwr_enablebkp(bool writable) { uint16_t regval; bool waswritable; /* Get the current state of the STM32WB PWR control register 1 */ - regval = stm32wb_pwr_getreg(STM32WB_PWR_CR1_OFFSET); + regval = stm32_pwr_getreg(STM32_PWR_CR1_OFFSET); waswritable = ((regval & PWR_CR1_DBP) != 0); /* Enable or disable the ability to write */ @@ -92,14 +92,14 @@ bool stm32wb_pwr_enablebkp(bool writable) /* Disable backup domain access */ regval &= ~PWR_CR1_DBP; - stm32wb_pwr_putreg(STM32WB_PWR_CR1_OFFSET, regval); + stm32_pwr_putreg(STM32_PWR_CR1_OFFSET, regval); } else if (!waswritable && writable) { /* Enable backup domain access */ regval |= PWR_CR1_DBP; - stm32wb_pwr_putreg(STM32WB_PWR_CR1_OFFSET, regval); + stm32_pwr_putreg(STM32_PWR_CR1_OFFSET, regval); /* Enable does not happen right away */ @@ -110,7 +110,7 @@ bool stm32wb_pwr_enablebkp(bool writable) } /**************************************************************************** - * Name: stm32wb_pwr_enableusv + * Name: stm32_pwr_enableusv * * Description: * Enables or disables the USB Supply Valid monitoring. Setting this bit @@ -125,14 +125,14 @@ bool stm32wb_pwr_enablebkp(bool writable) * ****************************************************************************/ -bool stm32wb_pwr_enableusv(bool set) +bool stm32_pwr_enableusv(bool set) { uint32_t regval; bool was_set; /* Get the current state of the STM32WB PWR control register 2 */ - regval = stm32wb_pwr_getreg(STM32WB_PWR_CR2_OFFSET); + regval = stm32_pwr_getreg(STM32_PWR_CR2_OFFSET); was_set = ((regval & PWR_CR2_USV) != 0); /* Enable or disable the ability to write */ @@ -142,14 +142,14 @@ bool stm32wb_pwr_enableusv(bool set) /* Disable the Vddusb monitoring */ regval &= ~PWR_CR2_USV; - stm32wb_pwr_putreg(STM32WB_PWR_CR2_OFFSET, regval); + stm32_pwr_putreg(STM32_PWR_CR2_OFFSET, regval); } else if (!was_set && set) { /* Enable the Vddusb monitoring */ regval |= PWR_CR2_USV; - stm32wb_pwr_putreg(STM32WB_PWR_CR2_OFFSET, regval); + stm32_pwr_putreg(STM32_PWR_CR2_OFFSET, regval); } return was_set; @@ -183,7 +183,7 @@ void stm32_pwr_setvos(int vos) return; } - regval = getreg32(STM32WB_PWR_CR1); + regval = getreg32(STM32_PWR_CR1); regval &= ~PWR_CR1_VOS_MASK; if (vos == 1) @@ -195,5 +195,5 @@ void stm32_pwr_setvos(int vos) regval |= PWR_CR1_VOS_RANGE2; } - putreg32(regval, STM32WB_PWR_CR1); + putreg32(regval, STM32_PWR_CR1); } diff --git a/arch/arm/src/stm32wb/stm32wb_pwr.h b/arch/arm/src/stm32wb/stm32wb_pwr.h index e9dea014de0de..e154381dfb913 100644 --- a/arch/arm/src/stm32wb/stm32wb_pwr.h +++ b/arch/arm/src/stm32wb/stm32wb_pwr.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32WB_STM32WB_PWR_H -#define __ARCH_ARM_SRC_STM32WB_STM32WB_PWR_H +#ifndef __ARCH_ARM_SRC_STM32WB_STM32_PWR_H +#define __ARCH_ARM_SRC_STM32WB_STM32_PWR_H /**************************************************************************** * Included Files @@ -54,7 +54,7 @@ extern "C" ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_pwr_enablebkp + * Name: stm32_pwr_enablebkp * * Description: * Enables access to the backup domain (RTC registers, RTC backup data @@ -68,10 +68,10 @@ extern "C" * ****************************************************************************/ -bool stm32wb_pwr_enablebkp(bool writable); +bool stm32_pwr_enablebkp(bool writable); /**************************************************************************** - * Name: stm32wb_pwr_enableusv + * Name: stm32_pwr_enableusv * * Description: * Enables or disables the USB Supply Valid monitoring. Setting this bit @@ -86,7 +86,7 @@ bool stm32wb_pwr_enablebkp(bool writable); * ****************************************************************************/ -bool stm32wb_pwr_enableusv(bool set); +bool stm32_pwr_enableusv(bool set); /**************************************************************************** * Name: stm32_pwr_setvos @@ -115,4 +115,4 @@ void stm32_pwr_setvos(int vos); #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32WB_STM32WB_PWR_H */ +#endif /* __ARCH_ARM_SRC_STM32WB_STM32_PWR_H */ diff --git a/arch/arm/src/stm32wb/stm32wb_rcc.c b/arch/arm/src/stm32wb/stm32wb_rcc.c index 9fd6f17b2a4b2..bd2878d4523b0 100644 --- a/arch/arm/src/stm32wb/stm32wb_rcc.c +++ b/arch/arm/src/stm32wb/stm32wb_rcc.c @@ -61,9 +61,9 @@ static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1, /* Determine if board wants to use HSI48 as 48 MHz oscillator. */ -#if defined(CONFIG_STM32WB_HAVE_HSI48) && defined(STM32WB_USE_CLK48) -# if STM32WB_CLK48_SEL == RCC_CCIPR_CLK48SEL_HSI48 -# define STM32WB_USE_HSI48 +#if defined(CONFIG_STM32_HAVE_HSI48) && defined(STM32_USE_CLK48) +# if STM32_CLK48_SEL == RCC_CCIPR_CLK48SEL_HSI48 +# define STM32_USE_HSI48 # endif #endif @@ -89,47 +89,47 @@ static inline void rcc_reset(void) /* Enable the Multi-Speed Internal clock (MSI) @ 4MHz */ - regval = getreg32(STM32WB_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval &= ~RCC_CR_MSIRANGE_MASK; regval |= RCC_CR_MSIRANGE_4M | RCC_CR_MSION; - putreg32(regval, STM32WB_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Reset CFGR register */ - regval = getreg32(STM32WB_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= RCC_CFGR_RESET_MASK; - putreg32(regval, STM32WB_RCC_CFGR); + putreg32(regval, STM32_RCC_CFGR); /* Reset PLLSAI1ON, PLLON, HSECSSON, HSEON, HSION, and MSIPLLON bits */ - regval = getreg32(STM32WB_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval &= ~(RCC_CR_PLLON | RCC_CR_PLLSAI1ON | RCC_CR_CSSON | RCC_CR_HSEON | RCC_CR_HSION | RCC_CR_MSIPLLEN); - putreg32(regval, STM32WB_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Reset LSI1 and LSI2 bits */ - regval = getreg32(STM32WB_RCC_CSR); + regval = getreg32(STM32_RCC_CSR); regval &= ~(RCC_CSR_LSI1ON | RCC_CSR_LSI2ON); - putreg32(regval, STM32WB_RCC_CSR); + putreg32(regval, STM32_RCC_CSR); /* Reset HSI48ON bit */ - regval = getreg32(STM32WB_RCC_CRRCR); + regval = getreg32(STM32_RCC_CRRCR); regval &= ~(RCC_CRRCR_HSI48ON); - putreg32(regval, STM32WB_RCC_CRRCR); + putreg32(regval, STM32_RCC_CRRCR); /* Reset PLLCFGR register */ - putreg32(RCC_PLLCFG_RESET, STM32WB_RCC_PLLCFG); + putreg32(RCC_PLLCFG_RESET, STM32_RCC_PLLCFG); /* Reset PLLSAI1CFG register */ - putreg32(RCC_PLLSAI1CFG_RESET, STM32WB_RCC_PLLSAI1CFG); + putreg32(RCC_PLLSAI1CFG_RESET, STM32_RCC_PLLSAI1CFG); /* Disable all interrupts */ - putreg32(0x00000000, STM32WB_RCC_CIER); + putreg32(0x00000000, STM32_RCC_CIER); } /**************************************************************************** @@ -148,39 +148,39 @@ static inline void rcc_enableahb1(void) * selected AHB1 peripherals. */ - regval = getreg32(STM32WB_RCC_AHB1ENR); + regval = getreg32(STM32_RCC_AHB1ENR); -#ifdef CONFIG_STM32WB_DMA1 +#ifdef CONFIG_STM32_DMA1 /* DMA 1 clock enable */ regval |= RCC_AHB1ENR_DMA1EN; #endif -#ifdef CONFIG_STM32WB_DMA2 +#ifdef CONFIG_STM32_DMA2 /* DMA 2 clock enable */ regval |= RCC_AHB1ENR_DMA2EN; #endif -#ifdef CONFIG_STM32WB_DMAMUX +#ifdef CONFIG_STM32_DMAMUX /* DMAMUX 1 clock enable */ regval |= RCC_AHB1ENR_DMAMUX1EN; #endif -#ifdef CONFIG_STM32WB_CRC +#ifdef CONFIG_STM32_CRC /* CRC clock enable */ regval |= RCC_AHB1ENR_CRCEN; #endif -#ifdef CONFIG_STM32WB_TSC +#ifdef CONFIG_STM32_TSC /* TSC clock enable */ regval |= RCC_AHB1ENR_TSCEN; #endif - putreg32(regval, STM32WB_RCC_AHB1ENR); /* Enable peripherals */ + putreg32(regval, STM32_RCC_AHB1ENR); /* Enable peripherals */ } /**************************************************************************** @@ -199,32 +199,32 @@ static inline void rcc_enableahb2(void) * selected AHB2 peripherals. */ - regval = getreg32(STM32WB_RCC_AHB2ENR); + regval = getreg32(STM32_RCC_AHB2ENR); /* Enable GPIO ports A-E, H */ regval |= (RCC_AHB2ENR_GPIOAEN | RCC_AHB2ENR_GPIOBEN | RCC_AHB2ENR_GPIOCEN -#if defined(CONFIG_STM32WB_GPIO_HAVE_PORTD) +#if defined(CONFIG_STM32_GPIO_HAVE_PORTD) | RCC_AHB2ENR_GPIODEN #endif -#if defined(CONFIG_STM32WB_GPIO_HAVE_PORTE) +#if defined(CONFIG_STM32_GPIO_HAVE_PORTE) | RCC_AHB2ENR_GPIOEEN #endif | RCC_AHB2ENR_GPIOHEN); -#if defined(CONFIG_STM32WB_ADC1) +#if defined(CONFIG_STM32_ADC1) /* ADC clock enable */ regval |= RCC_AHB2ENR_ADCEN; #endif -#ifdef CONFIG_STM32WB_AES1 +#ifdef CONFIG_STM32_AES1 /* AES1 cryptographic accelerator clock enable */ regval |= RCC_AHB2ENR_AES1EN; #endif - putreg32(regval, STM32WB_RCC_AHB2ENR); /* Enable peripherals */ + putreg32(regval, STM32_RCC_AHB2ENR); /* Enable peripherals */ } /**************************************************************************** @@ -243,51 +243,51 @@ static inline void rcc_enableahb3(void) * selected AHB3 peripherals. */ - regval = getreg32(STM32WB_RCC_AHB3ENR); + regval = getreg32(STM32_RCC_AHB3ENR); -#ifdef CONFIG_STM32WB_QSPI +#ifdef CONFIG_STM32_QSPI /* QuadSPI module clock enable */ regval |= RCC_AHB3ENR_QSPIEN; #endif -#ifdef CONFIG_STM32WB_PKA +#ifdef CONFIG_STM32_PKA /* Public key accelerator clock enable */ regval |= RCC_AHB3ENR_PKAEN; #endif -#ifdef CONFIG_STM32WB_AES2 +#ifdef CONFIG_STM32_AES2 /* AES2 cryptographic accelerator clock enable */ regval |= RCC_AHB3ENR_AES2EN; #endif -#ifdef CONFIG_STM32WB_RNG +#ifdef CONFIG_STM32_RNG /* Random number generator clock enable */ regval |= RCC_AHB3ENR_RNGEN; #endif -#ifdef CONFIG_STM32WB_HSEM +#ifdef CONFIG_STM32_HSEM /* Hardware semaphore clock enable */ regval |= RCC_AHB3ENR_HSEMEN; #endif -#ifdef CONFIG_STM32WB_IPCC +#ifdef CONFIG_STM32_IPCC /* Inter-processor communication controller clock enable */ regval |= RCC_AHB3ENR_IPCCEN; #endif -#ifdef CONFIG_STM32WB_FLASH +#ifdef CONFIG_STM32_FLASH /* Flash memory interface clock enable */ regval |= RCC_AHB3ENR_FLASHEN; #endif - putreg32(regval, STM32WB_RCC_AHB3ENR); /* Enable peripherals */ + putreg32(regval, STM32_RCC_AHB3ENR); /* Enable peripherals */ } /**************************************************************************** @@ -306,52 +306,52 @@ static inline void rcc_enableapb1(void) * selected APB1 peripherals. */ - regval = getreg32(STM32WB_RCC_APB1ENR1); + regval = getreg32(STM32_RCC_APB1ENR1); -#ifdef CONFIG_STM32WB_TIM2 +#ifdef CONFIG_STM32_TIM2 /* TIM2 clock enable */ regval |= RCC_APB1ENR1_TIM2EN; #endif -#ifdef CONFIG_STM32WB_LCD +#ifdef CONFIG_STM32_LCD /* LCD clock enable */ regval |= RCC_APB1ENR1_LCDEN; #endif -#if defined(CONFIG_STM32WB_RTC) +#if defined(CONFIG_STM32_RTC) /* RTC APB clock enable */ regval |= RCC_APB1ENR1_RTCAPBEN; #endif -#if defined(CONFIG_STM32WB_WWDG) +#if defined(CONFIG_STM32_WWDG) /* Window watchdog clock enable */ regval |= RCC_APB1ENR1_WWDGEN; #endif -#ifdef CONFIG_STM32WB_SPI2 +#ifdef CONFIG_STM32_SPI2 /* SPI2 clock enable */ regval |= RCC_APB1ENR1_SPI2EN; #endif -#ifdef CONFIG_STM32WB_I2C1 +#ifdef CONFIG_STM32_I2C1 /* I2C1 clock enable */ regval |= RCC_APB1ENR1_I2C1EN; #endif -#ifdef CONFIG_STM32WB_I2C3 +#ifdef CONFIG_STM32_I2C3 /* I2C3 clock enable */ regval |= RCC_APB1ENR1_I2C3EN; #endif -#ifdef STM32WB_USE_HSI48 - if (STM32WB_HSI48_SYNCSRC != SYNCSRC_NONE) +#ifdef STM32_USE_HSI48 + if (STM32_HSI48_SYNCSRC != SYNCSRC_NONE) { /* Clock Recovery System clock enable */ @@ -359,37 +359,37 @@ static inline void rcc_enableapb1(void) } #endif -#if defined(CONFIG_STM32WB_USB) +#if defined(CONFIG_STM32_USB) /* USB clock enable */ regval |= RCC_APB1ENR1_USBEN; #endif -#ifdef CONFIG_STM32WB_LPTIM1 +#ifdef CONFIG_STM32_LPTIM1 /* Low power timer 1 clock enable */ regval |= RCC_APB1ENR1_LPTIM1EN; #endif - putreg32(regval, STM32WB_RCC_APB1ENR1); /* Enable peripherals */ + putreg32(regval, STM32_RCC_APB1ENR1); /* Enable peripherals */ /* Second APB1 register */ - regval = getreg32(STM32WB_RCC_APB1ENR2); + regval = getreg32(STM32_RCC_APB1ENR2); -#ifdef CONFIG_STM32WB_LPUART1 +#ifdef CONFIG_STM32_LPUART1 /* Low power uart clock enable */ regval |= RCC_APB1ENR2_LPUART1EN; #endif -#ifdef CONFIG_STM32WB_LPTIM2 +#ifdef CONFIG_STM32_LPTIM2 /* Low power timer 2 clock enable */ regval |= RCC_APB1ENR2_LPTIM2EN; #endif - putreg32(regval, STM32WB_RCC_APB1ENR2); /* Enable peripherals */ + putreg32(regval, STM32_RCC_APB1ENR2); /* Enable peripherals */ } /**************************************************************************** @@ -408,45 +408,45 @@ static inline void rcc_enableapb2(void) * selected APB2 peripherals. */ - regval = getreg32(STM32WB_RCC_APB2ENR); + regval = getreg32(STM32_RCC_APB2ENR); -#ifdef CONFIG_STM32WB_TIM1 +#ifdef CONFIG_STM32_TIM1 /* TIM1 clock enable */ regval |= RCC_APB2ENR_TIM1EN; #endif -#ifdef CONFIG_STM32WB_SPI1 +#ifdef CONFIG_STM32_SPI1 /* SPI1 clock enable */ regval |= RCC_APB2ENR_SPI1EN; #endif -#ifdef CONFIG_STM32WB_USART1 +#ifdef CONFIG_STM32_USART1 /* USART1 clock enable */ regval |= RCC_APB2ENR_USART1EN; #endif -#ifdef CONFIG_STM32WB_TIM16 +#ifdef CONFIG_STM32_TIM16 /* TIM16 clock enable */ regval |= RCC_APB2ENR_TIM16EN; #endif -#ifdef CONFIG_STM32WB_TIM17 +#ifdef CONFIG_STM32_TIM17 /* TIM17 clock enable */ regval |= RCC_APB2ENR_TIM17EN; #endif -#ifdef CONFIG_STM32WB_SAI1 +#ifdef CONFIG_STM32_SAI1 /* SAI1 clock enable */ regval |= RCC_APB2ENR_SAI1EN; #endif - putreg32(regval, STM32WB_RCC_APB2ENR); /* Enable peripherals */ + putreg32(regval, STM32_RCC_APB2ENR); /* Enable peripherals */ } /**************************************************************************** @@ -466,26 +466,26 @@ static inline void rcc_enableccip(void) * will at least have a clock. */ - regval = getreg32(STM32WB_RCC_CCIPR); + regval = getreg32(STM32_RCC_CCIPR); -#if defined(STM32WB_I2C_USE_HSI16) -#ifdef CONFIG_STM32WB_I2C1 +#if defined(STM32_I2C_USE_HSI16) +#ifdef CONFIG_STM32_I2C1 /* Select HSI16 as I2C1 clock source. */ regval &= ~RCC_CCIPR_I2C1SEL_MASK; regval |= RCC_CCIPR_I2C1SEL_HSI16; #endif -#ifdef CONFIG_STM32WB_I2C3 +#ifdef CONFIG_STM32_I2C3 /* Select HSI16 as I2C3 clock source. */ regval &= ~RCC_CCIPR_I2C3SEL_MASK; regval |= RCC_CCIPR_I2C3SEL_HSI16; #endif -#endif /* STM32WB_I2C_USE_HSI16 */ +#endif /* STM32_I2C_USE_HSI16 */ -#if defined(STM32WB_USE_CLK48) +#if defined(STM32_USE_CLK48) /* XXX sanity if usb or rng, then we need to set the clk48 source - * and then we can also do away with STM32WB_USE_CLK48, and give better + * and then we can also do away with STM32_USE_CLK48, and give better * warning messages. */ @@ -493,18 +493,18 @@ static inline void rcc_enableccip(void) regval |= RCC_CCIPR_CLK48SEL_HSI48; #endif -#if defined(CONFIG_STM32WB_ADC1) +#if defined(CONFIG_STM32_ADC1) /* Select SYSCLK as ADC clock source */ regval &= ~RCC_CCIPR_ADCSEL_MASK; regval |= RCC_CCIPR_ADCSEL_SYSCLK; #endif - putreg32(regval, STM32WB_RCC_CCIPR); + putreg32(regval, STM32_RCC_CCIPR); } /**************************************************************************** - * Name: stm32wb_stdclockconfig + * Name: stm32_stdclockconfig * * Description: * Called to change to new clock based on settings in board.h @@ -513,18 +513,18 @@ static inline void rcc_enableccip(void) * power clocking modes! ****************************************************************************/ -#ifndef CONFIG_ARCH_BOARD_STM32WB_CUSTOM_CLOCKCONFIG -static void stm32wb_stdclockconfig(void) +#ifndef CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG +static void stm32_stdclockconfig(void) { uint32_t regval; volatile int32_t timeout; -#if defined(STM32WB_BOARD_USEHSI) || defined(STM32WB_I2C_USE_HSI16) +#if defined(STM32_BOARD_USEHSI) || defined(STM32_I2C_USE_HSI16) /* Enable Internal High-Speed Clock (HSI) */ - regval = getreg32(STM32WB_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_HSION; /* Enable HSI */ - putreg32(regval, STM32WB_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Wait until the HSI is ready (or until a timeout elapsed) */ @@ -532,7 +532,7 @@ static void stm32wb_stdclockconfig(void) { /* Check if the HSIRDY flag is the set in the CR */ - if ((getreg32(STM32WB_RCC_CR) & RCC_CR_HSIRDY) != 0) + if ((getreg32(STM32_RCC_CR) & RCC_CR_HSIRDY) != 0) { /* If so, then break-out with timeout > 0 */ @@ -541,17 +541,17 @@ static void stm32wb_stdclockconfig(void) } #endif -#if defined(STM32WB_BOARD_USEHSI) +#if defined(STM32_BOARD_USEHSI) /* Already set above */ -#elif defined(STM32WB_BOARD_USEMSI) +#elif defined(STM32_BOARD_USEMSI) /* Enable Internal Multi-Speed Clock (MSI) */ /* Wait until the MSI is either off or ready (or until a timeout elapsed) */ for (timeout = MSIRDY_TIMEOUT; timeout > 0; timeout--) { - regval = getreg32(STM32WB_RCC_CR); + regval = getreg32(STM32_RCC_CR); if ((regval & RCC_CR_MSIRDY) || ~(regval & RCC_CR_MSION)) { @@ -563,10 +563,10 @@ static void stm32wb_stdclockconfig(void) /* Setting MSIRANGE */ - regval = getreg32(STM32WB_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval &= ~RCC_CR_MSIRANGE_MASK; - regval |= (STM32WB_BOARD_MSIRANGE | RCC_CR_MSION); /* Enable MSI and frequency */ - putreg32(regval, STM32WB_RCC_CR); + regval |= (STM32_BOARD_MSIRANGE | RCC_CR_MSION); /* Enable MSI and frequency */ + putreg32(regval, STM32_RCC_CR); /* Wait until the MSI is ready (or until a timeout elapsed) */ @@ -574,7 +574,7 @@ static void stm32wb_stdclockconfig(void) { /* Check if the MSIRDY flag is the set in the CR */ - if ((getreg32(STM32WB_RCC_CR) & RCC_CR_MSIRDY) != 0) + if ((getreg32(STM32_RCC_CR) & RCC_CR_MSIRDY) != 0) { /* If so, then break-out with timeout > 0 */ @@ -582,12 +582,12 @@ static void stm32wb_stdclockconfig(void) } } -#elif defined(STM32WB_BOARD_USEHSE) +#elif defined(STM32_BOARD_USEHSE) /* Enable External High-Speed Clock (HSE) */ - regval = getreg32(STM32WB_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_HSEON; /* Enable HSE */ - putreg32(regval, STM32WB_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Wait until the HSE is ready (or until a timeout elapsed) */ @@ -595,7 +595,7 @@ static void stm32wb_stdclockconfig(void) { /* Check if the HSERDY flag is the set in the CR */ - if ((getreg32(STM32WB_RCC_CR) & RCC_CR_HSERDY) != 0) + if ((getreg32(STM32_RCC_CR) & RCC_CR_HSERDY) != 0) { /* If so, then break-out with timeout > 0 */ @@ -604,7 +604,7 @@ static void stm32wb_stdclockconfig(void) } #else -# error stm32wb_stdclockconfig(), must have one of STM32WB_BOARD_USEHSI, STM32WB_BOARD_USEMSI, STM32WB_BOARD_USEHSE defined +# error stm32_stdclockconfig(), must have one of STM32_BOARD_USEHSI, STM32_BOARD_USEMSI, STM32_BOARD_USEHSE defined #endif @@ -617,144 +617,144 @@ static void stm32wb_stdclockconfig(void) { /* Setup regulator voltage according to clock frequency */ - regval = getreg32(STM32WB_PWR_CR1); + regval = getreg32(STM32_PWR_CR1); regval &= ~PWR_CR1_VOS_MASK; -#if STM32WB_SYSCLK_FREQUENCY > 16000000 || \ +#if STM32_SYSCLK_FREQUENCY > 16000000 || \ (defined(BOARD_MAX_PLL_FREQUENCY) && BOARD_MAX_PLL_FREQUENCY > 16000000) regval |= PWR_CR1_VOS_RANGE1; #else regval |= PWR_CR1_VOS_RANGE2; #endif - putreg32(regval, STM32WB_PWR_CR1); + putreg32(regval, STM32_PWR_CR1); /* Set the HCLK source/divider */ - regval = getreg32(STM32WB_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_HPRE_MASK; - regval |= STM32WB_RCC_CFGR_HPRE; - putreg32(regval, STM32WB_RCC_CFGR); + regval |= STM32_RCC_CFGR_HPRE; + putreg32(regval, STM32_RCC_CFGR); /* Set the CPU2 HCLK2 source/divider */ - regval = getreg32(STM32WB_RCC_EXTCFGR); + regval = getreg32(STM32_RCC_EXTCFGR); regval &= ~RCC_EXTCFGR_C2HPRE_MASK; - regval |= STM32WB_RCC_EXTCFGR_C2HPRE; - putreg32(regval, STM32WB_RCC_EXTCFGR); + regval |= STM32_RCC_EXTCFGR_C2HPRE; + putreg32(regval, STM32_RCC_EXTCFGR); /* Set the HCLK4 source/divider */ - regval = getreg32(STM32WB_RCC_EXTCFGR); + regval = getreg32(STM32_RCC_EXTCFGR); regval &= ~RCC_EXTCFGR_SHDHPRE_MASK; - regval |= STM32WB_RCC_EXTCFGR_SHDHPRE; - putreg32(regval, STM32WB_RCC_EXTCFGR); + regval |= STM32_RCC_EXTCFGR_SHDHPRE; + putreg32(regval, STM32_RCC_EXTCFGR); /* Set the PCLK1 divider */ - regval = getreg32(STM32WB_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_PPRE1_MASK; - regval |= STM32WB_RCC_CFGR_PPRE1; - putreg32(regval, STM32WB_RCC_CFGR); + regval |= STM32_RCC_CFGR_PPRE1; + putreg32(regval, STM32_RCC_CFGR); /* Set the PCLK2 divider */ - regval = getreg32(STM32WB_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_PPRE2_MASK; - regval |= STM32WB_RCC_CFGR_PPRE2; - putreg32(regval, STM32WB_RCC_CFGR); + regval |= STM32_RCC_CFGR_PPRE2; + putreg32(regval, STM32_RCC_CFGR); /* Configure Main PLL */ - regval = getreg32(STM32WB_RCC_PLLCFG); + regval = getreg32(STM32_RCC_PLLCFG); regval &= ~(RCC_PLLCFG_PLLM_MASK | RCC_PLLCFG_PLLN_MASK); - regval |= (STM32WB_PLLCFG_PLLM | STM32WB_PLLCFG_PLLN); + regval |= (STM32_PLLCFG_PLLM | STM32_PLLCFG_PLLN); /* Set the PLL dividers and multipliers to configure the main PLL */ regval &= ~(RCC_PLLCFG_PLLPEN | RCC_PLLCFG_PLLQEN | RCC_PLLCFG_PLLREN); -#ifdef STM32WB_PLLCFG_PLLP_ENABLED +#ifdef STM32_PLLCFG_PLLP_ENABLED regval &= ~RCC_PLLCFG_PLLP_MASK; - regval |= (RCC_PLLCFG_PLLPEN | STM32WB_PLLCFG_PLLP); + regval |= (RCC_PLLCFG_PLLPEN | STM32_PLLCFG_PLLP); #endif -#ifdef STM32WB_PLLCFG_PLLQ_ENABLED +#ifdef STM32_PLLCFG_PLLQ_ENABLED regval &= ~RCC_PLLCFG_PLLQ_MASK; - regval |= (RCC_PLLCFG_PLLQEN | STM32WB_PLLCFG_PLLQ); + regval |= (RCC_PLLCFG_PLLQEN | STM32_PLLCFG_PLLQ); #endif -#ifdef STM32WB_PLLCFG_PLLR_ENABLED +#ifdef STM32_PLLCFG_PLLR_ENABLED regval &= ~RCC_PLLCFG_PLLR_MASK; - regval |= (RCC_PLLCFG_PLLREN | STM32WB_PLLCFG_PLLR); + regval |= (RCC_PLLCFG_PLLREN | STM32_PLLCFG_PLLR); #endif /* XXX The choice of clock source to PLL (all three) is independent - * of the sys clock source choice, review the STM32WB_BOARD_USEHSI + * of the sys clock source choice, review the STM32_BOARD_USEHSI * name; probably split it into two, one for PLL source and one * for sys clock source. */ regval &= ~RCC_PLLCFG_PLLSRC_MASK; -#ifdef STM32WB_BOARD_USEHSI +#ifdef STM32_BOARD_USEHSI regval |= RCC_PLLCFG_PLLSRC_HSI16; -#elif defined(STM32WB_BOARD_USEMSI) +#elif defined(STM32_BOARD_USEMSI) regval |= RCC_PLLCFG_PLLSRC_MSI; -#else /* if STM32WB_BOARD_USEHSE */ +#else /* if STM32_BOARD_USEHSE */ regval |= RCC_PLLCFG_PLLSRC_HSE; #endif - putreg32(regval, STM32WB_RCC_PLLCFG); + putreg32(regval, STM32_RCC_PLLCFG); /* Enable the main PLL */ - regval = getreg32(STM32WB_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_PLLON; - putreg32(regval, STM32WB_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Wait until the PLL is ready */ - while ((getreg32(STM32WB_RCC_CR) & RCC_CR_PLLRDY) == 0) + while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLRDY) == 0) { } -#ifdef CONFIG_STM32WB_SAI1PLL +#ifdef CONFIG_STM32_SAI1PLL /* Configure SAI1 PLL */ - regval = getreg32(STM32WB_RCC_PLLSAI1CFG); + regval = getreg32(STM32_RCC_PLLSAI1CFG); regval &= ~RCC_PLLSAI1CFG_PLLN_MASK; - regval |= STM32WB_PLLSAI1CFG_PLLN; + regval |= STM32_PLLSAI1CFG_PLLN; /* Set the PLL dividers and multipliers to configure the SAI1 PLL */ regval &= ~(RCC_PLLSAI1CFG_PLLPEN | RCC_PLLSAI1CFG_PLLQEN | RCC_PLLSAI1CFG_PLLREN); -#ifdef STM32WB_PLLSAI1CFG_PLLP_ENABLED +#ifdef STM32_PLLSAI1CFG_PLLP_ENABLED regval &= ~RCC_PLLSAI1CFG_PLLP_MASK; - regval |= (RCC_PLLSAI1CFG_PLLPEN | STM32WB_PLLSAI1CFG_PLLP); + regval |= (RCC_PLLSAI1CFG_PLLPEN | STM32_PLLSAI1CFG_PLLP); #endif -#ifdef STM32WB_PLLSAI1CFG_PLLQ_ENABLED +#ifdef STM32_PLLSAI1CFG_PLLQ_ENABLED regval &= ~RCC_PLLSAI1CFG_PLLQ_MASK; - regval |= (RCC_PLLSAI1CFG_PLLQEN | STM32WB_PLLSAI1CFG_PLLQ); + regval |= (RCC_PLLSAI1CFG_PLLQEN | STM32_PLLSAI1CFG_PLLQ); #endif -#ifdef STM32WB_PLLSAI1CFG_PLLR_ENABLED +#ifdef STM32_PLLSAI1CFG_PLLR_ENABLED regval &= ~RCC_PLLSAI1CFG_PLLR_MASK; - regval |= (RCC_PLLSAI1CFG_PLLREN | STM32WB_PLLSAI1CFG_PLLR); + regval |= (RCC_PLLSAI1CFG_PLLREN | STM32_PLLSAI1CFG_PLLR); #endif - putreg32(regval, STM32WB_RCC_PLLSAI1CFG); + putreg32(regval, STM32_RCC_PLLSAI1CFG); /* Enable the SAI1 PLL */ - regval = getreg32(STM32WB_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_PLLSAI1ON; - putreg32(regval, STM32WB_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Wait until the PLL is ready */ - while ((getreg32(STM32WB_RCC_CR) & RCC_CR_PLLSAI1RDY) == 0) + while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLSAI1RDY) == 0) { } #endif /* Configure FLASH wait states */ - regval = getreg32(STM32WB_FLASH_ACR); + regval = getreg32(STM32_FLASH_ACR); regval &= ~FLASH_ACR_LATENCY_MASK; #ifdef BOARD_FLASH_WAITSTATES regval |= FLASH_ACR_LATENCY(BOARD_FLASH_WAITSTATES); @@ -764,35 +764,35 @@ static void stm32wb_stdclockconfig(void) /* Enable FLASH prefetch, instruction cache and data cache */ -#ifdef CONFIG_STM32WB_FLASH_PREFETCH +#ifdef CONFIG_STM32_FLASH_PREFETCH regval |= FLASH_ACR_PRFTEN; #else regval &= ~FLASH_ACR_PRFTEN; #endif regval |= (FLASH_ACR_ICEN | FLASH_ACR_DCEN); - putreg32(regval, STM32WB_FLASH_ACR); + putreg32(regval, STM32_FLASH_ACR); /* Select the main PLL as system clock source */ - regval = getreg32(STM32WB_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_SW_MASK; regval |= RCC_CFGR_SW_PLL; - putreg32(regval, STM32WB_RCC_CFGR); + putreg32(regval, STM32_RCC_CFGR); /* Wait until the PLL source is used as the system clock source */ - while ((getreg32(STM32WB_RCC_CFGR) & RCC_CFGR_SWS_MASK) != + while ((getreg32(STM32_RCC_CFGR) & RCC_CFGR_SWS_MASK) != RCC_CFGR_SWS_PLL) { } -#if defined(CONFIG_STM32WB_IWDG) || defined(CONFIG_STM32WB_RTC_LSICLOCK) +#if defined(CONFIG_STM32_IWDG) || defined(CONFIG_STM32_RTC_LSICLOCK) /* Low speed internal clock source LSI */ - stm32wb_rcc_enable_lsi(); + stm32_rcc_enable_lsi(); #endif -#if defined(STM32WB_USE_LSE) +#if defined(STM32_USE_LSE) /* Low speed external clock source LSE * * TODO: There is another case where the LSE needs to @@ -805,27 +805,27 @@ static void stm32wb_stdclockconfig(void) * this for automatically trimming MSI, etc. */ - stm32wb_rcc_enable_lse(); + stm32_rcc_enable_lse(); -# if defined(STM32WB_BOARD_USEMSI) +# if defined(STM32_BOARD_USEMSI) /* Now that LSE is up, auto trim the MSI */ - regval = getreg32(STM32WB_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_MSIPLLEN; - putreg32(regval, STM32WB_RCC_CR); + putreg32(regval, STM32_RCC_CR); # endif -#endif /* STM32WB_USE_LSE */ +#endif /* STM32_USE_LSE */ /* Select CPU2 RF wakeup clock source, no clock if not set */ - regval = getreg32(STM32WB_RCC_CSR); + regval = getreg32(STM32_RCC_CSR); regval &= ~RCC_CSR_RFWKPSEL_MASK; -#if defined(STM32WB_BOARD_RFWKP_USELSE) +#if defined(STM32_BOARD_RFWKP_USELSE) regval |= RCC_CSR_RFWKPSEL_LSE; -#elif defined(STM32WB_BOARD_RFWKP_USEHSE) +#elif defined(STM32_BOARD_RFWKP_USEHSE) regval |= RCC_CSR_RFWKPSEL_HSE; #endif - putreg32(regval, STM32WB_RCC_CSR); + putreg32(regval, STM32_RCC_CSR); } } #endif @@ -843,10 +843,10 @@ static inline void rcc_enableperipherals(void) rcc_enableapb1(); rcc_enableapb2(); -#ifdef STM32WB_USE_HSI48 +#ifdef STM32_USE_HSI48 /* Enable HSI48 clocking to support USB transfers or RNG */ - stm32wb_enable_hsi48(STM32WB_HSI48_SYNCSRC); + stm32_enable_hsi48(STM32_HSI48_SYNCSRC); #endif } @@ -871,50 +871,50 @@ static inline void rcc_enableperipherals(void) * ****************************************************************************/ -#if defined(CONFIG_STM32WB_PWR) && defined(CONFIG_STM32WB_RTC) +#if defined(CONFIG_STM32_PWR) && defined(CONFIG_STM32_RTC) static inline void rcc_resetbkp(void) { bool init_stat; /* Check if the RTC is already configured */ - init_stat = stm32wb_rtc_is_initialized(); + init_stat = stm32_rtc_is_initialized(); if (!init_stat) { - uint32_t bkregs[STM32WB_RTC_BKCOUNT]; + uint32_t bkregs[STM32_RTC_BKCOUNT]; int i; /* Backup backup-registers before RTC reset. */ - for (i = 0; i < STM32WB_RTC_BKCOUNT; i++) + for (i = 0; i < STM32_RTC_BKCOUNT; i++) { - bkregs[i] = getreg32(STM32WB_RTC_BKPR(i)); + bkregs[i] = getreg32(STM32_RTC_BKPR(i)); } /* Enable write access to the backup domain (RTC registers, RTC * backup data registers and backup SRAM). */ - stm32wb_pwr_enablebkp(true); + stm32_pwr_enablebkp(true); /* We might be changing RTCSEL - to ensure such changes work, we must * reset the backup domain (having backed up the RTC_MAGIC token) */ - modifyreg32(STM32WB_RCC_BDCR, 0, RCC_BDCR_BDRST); - modifyreg32(STM32WB_RCC_BDCR, RCC_BDCR_BDRST, 0); + modifyreg32(STM32_RCC_BDCR, 0, RCC_BDCR_BDRST); + modifyreg32(STM32_RCC_BDCR, RCC_BDCR_BDRST, 0); /* Restore backup-registers, except RTC related. */ - for (i = 0; i < STM32WB_RTC_BKCOUNT; i++) + for (i = 0; i < STM32_RTC_BKCOUNT; i++) { - if (RTC_MAGIC_REG != STM32WB_RTC_BKPR(i)) + if (RTC_MAGIC_REG != STM32_RTC_BKPR(i)) { - putreg32(bkregs[i], STM32WB_RTC_BKPR(i)); + putreg32(bkregs[i], STM32_RTC_BKPR(i)); } } - stm32wb_pwr_enablebkp(false); + stm32_pwr_enablebkp(false); } } #else @@ -922,7 +922,7 @@ static inline void rcc_resetbkp(void) #endif /**************************************************************************** - * Name: stm32wb_clockconfig + * Name: stm32_clockconfig * * Description: * Called to establish the clock settings based on the values in board.h. @@ -930,9 +930,9 @@ static inline void rcc_resetbkp(void) * and enable peripheral clocking for all peripherals enabled in the NuttX * configuration file. * - * If CONFIG_ARCH_BOARD_STM32WB_CUSTOM_CLOCKCONFIG is defined, then + * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then * clocking will be enabled by an externally provided, board-specific - * function called stm32wb_board_clockconfig(). + * function called stm32_board_clockconfig(). * * Input Parameters: * None @@ -942,7 +942,7 @@ static inline void rcc_resetbkp(void) * ****************************************************************************/ -void stm32wb_clockconfig(void) +void stm32_clockconfig(void) { /* Make sure that we are starting in the reset state */ @@ -952,11 +952,11 @@ void stm32wb_clockconfig(void) rcc_resetbkp(); -#if defined(CONFIG_ARCH_BOARD_STM32WB_CUSTOM_CLOCKCONFIG) +#if defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) /* Invoke Board Custom Clock Configuration */ - stm32wb_board_clockconfig(); + stm32_board_clockconfig(); #else @@ -964,7 +964,7 @@ void stm32wb_clockconfig(void) * board.h */ - stm32wb_stdclockconfig(); + stm32_stdclockconfig(); #endif @@ -974,7 +974,7 @@ void stm32wb_clockconfig(void) } /**************************************************************************** - * Name: stm32wb_clockenable + * Name: stm32_clockenable * * Description: * Re-enable the clock and restore the clock settings based on settings in @@ -984,12 +984,12 @@ void stm32wb_clockconfig(void) * re-enable/re-start the PLL * * This functional performs a subset of the operations performed by - * stm32wb_clockconfig(): It does not reset any devices, and it does not + * stm32_clockconfig(): It does not reset any devices, and it does not * reset the currently enabled peripheral clocks. * - * If CONFIG_ARCH_BOARD_STM32WB_CUSTOM_CLOCKCONFIG is defined, then + * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then * clocking will be enabled by an externally provided, board-specific - * function called stm32wb_board_clockconfig(). + * function called stm32_board_clockconfig(). * * Input Parameters: * None @@ -1000,13 +1000,13 @@ void stm32wb_clockconfig(void) ****************************************************************************/ #ifdef CONFIG_PM -void stm32wb_clockenable(void) +void stm32_clockenable(void) { -#if defined(CONFIG_ARCH_BOARD_STM32WB_CUSTOM_CLOCKCONFIG) +#if defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) /* Invoke Board Custom Clock Configuration */ - stm32wb_board_clockconfig(); + stm32_board_clockconfig(); #else @@ -1014,7 +1014,7 @@ void stm32wb_clockenable(void) * board.h */ - stm32wb_stdclockconfig(); + stm32_stdclockconfig(); #endif } diff --git a/arch/arm/src/stm32wb/stm32wb_rcc.h b/arch/arm/src/stm32wb/stm32wb_rcc.h index c770e462bd143..7fbbbd8ab19e4 100644 --- a/arch/arm/src/stm32wb/stm32wb_rcc.h +++ b/arch/arm/src/stm32wb/stm32wb_rcc.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32WB_STM32WB_RCC_H -#define __ARCH_ARM_SRC_STM32WB_STM32WB_RCC_H +#ifndef __ARCH_ARM_SRC_STM32WB_STM32_RCC_H +#define __ARCH_ARM_SRC_STM32WB_STM32_RCC_H /**************************************************************************** * Included Files @@ -29,6 +29,7 @@ #include +#include "arm_internal.h" #include "chip.h" #include "hardware/stm32wb_rcc.h" @@ -68,7 +69,7 @@ typedef enum crs_syncsrc_e crs_syncsrc_t; ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_mcoconfig + * Name: stm32_mcoconfig * * Description: * Selects the clock source to output and clock divider on MC pin @@ -84,11 +85,11 @@ typedef enum crs_syncsrc_e crs_syncsrc_t; * ****************************************************************************/ -static inline void stm32wb_mcoconfig(uint32_t source, uint32_t divider) +static inline void stm32_mcoconfig(uint32_t source, uint32_t divider) { uint32_t regval; - regval = getreg32(STM32WB_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); /* Set MCO source */ @@ -99,7 +100,7 @@ static inline void stm32wb_mcoconfig(uint32_t source, uint32_t divider) regval &= ~(RCC_CFGR_MCOPRE_MASK); regval |= (divider & RCC_CFGR_MCOPRE_MASK); - putreg32(regval, STM32WB_RCC_CFGR); + putreg32(regval, STM32_RCC_CFGR); } /**************************************************************************** @@ -107,7 +108,7 @@ static inline void stm32wb_mcoconfig(uint32_t source, uint32_t divider) ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_clockconfig + * Name: stm32_clockconfig * * Description: * Called to establish the clock settings based on the values in board.h. @@ -115,9 +116,9 @@ static inline void stm32wb_mcoconfig(uint32_t source, uint32_t divider) * and enable peripheral clocking for all periperipherals enabled in the * NuttX configuration file. * - * If CONFIG_ARCH_BOARD_STM32WB_CUSTOM_CLOCKCONFIG is defined, then + * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then * clocking will be enabled by an externally provided, board-specific - * function called stm32wb_board_clockconfig(). + * function called stm32_board_clockconfig(). * * Input Parameters: * None @@ -127,10 +128,10 @@ static inline void stm32wb_mcoconfig(uint32_t source, uint32_t divider) * ****************************************************************************/ -void stm32wb_clockconfig(void); +void stm32_clockconfig(void); /**************************************************************************** - * Name: stm32wb_board_clockconfig + * Name: stm32_board_clockconfig * * Description: * Any STM32WB board may replace the "standard" board clock configuration @@ -138,12 +139,12 @@ void stm32wb_clockconfig(void); * ****************************************************************************/ -#ifdef CONFIG_ARCH_BOARD_STM32WB_CUSTOM_CLOCKCONFIG -void stm32wb_board_clockconfig(void); +#ifdef CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG +void stm32_board_clockconfig(void); #endif /**************************************************************************** - * Name: stm32wb_clockenable + * Name: stm32_clockenable * * Description: * Re-enable the clock and restore the clock settings based on settings in @@ -153,12 +154,12 @@ void stm32wb_board_clockconfig(void); * re-start the PLL * * This functional performs a subset of the operations performed by - * stm32wb_clockconfig(): It does not reset any devices, and it does not + * stm32_clockconfig(): It does not reset any devices, and it does not * reset the currently enabled peripheral clocks. * - * If CONFIG_ARCH_BOARD_STM32WB_CUSTOM_CLOCKCONFIG is defined, then + * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then * clocking will be enabled by an externally provided, board-specific - * function called stm32wb_board_clockconfig(). + * function called stm32_board_clockconfig(). * * Input Parameters: * None @@ -169,11 +170,11 @@ void stm32wb_board_clockconfig(void); ****************************************************************************/ #ifdef CONFIG_PM -void stm32wb_clockenable(void); +void stm32_clockenable(void); #endif /**************************************************************************** - * Name: stm32wb_rcc_enable_lse + * Name: stm32_rcc_enable_lse * * Description: * Enable the External Low-Speed (LSE) Oscillator. @@ -186,30 +187,30 @@ void stm32wb_clockenable(void); * ****************************************************************************/ -void stm32wb_rcc_enable_lse(void); +void stm32_rcc_enable_lse(void); /**************************************************************************** - * Name: stm32wb_rcc_enable_lsi + * Name: stm32_rcc_enable_lsi * * Description: * Enable the Internal Low-Speed (LSI) RC Oscillator. * ****************************************************************************/ -void stm32wb_rcc_enable_lsi(void); +void stm32_rcc_enable_lsi(void); /**************************************************************************** - * Name: stm32wb_rcc_disable_lsi + * Name: stm32_rcc_disable_lsi * * Description: * Disable the Internal Low-Speed (LSI) RC Oscillator. * ****************************************************************************/ -void stm32wb_rcc_disable_lsi(void); +void stm32_rcc_disable_lsi(void); /**************************************************************************** - * Name: stm32wb_rcc_enable_hsi48 + * Name: stm32_rcc_enable_hsi48 * * Description: * HSI48 clock signal is generated from an internal 48 MHz RC oscillator @@ -235,10 +236,10 @@ void stm32wb_rcc_disable_lsi(void); * ****************************************************************************/ -void stm32wb_rcc_enable_hsi48(crs_syncsrc_t syncsrc); +void stm32_rcc_enable_hsi48(crs_syncsrc_t syncsrc); /**************************************************************************** - * Name: stm32wb_rcc_disable_hsi48 + * Name: stm32_rcc_disable_hsi48 * * Description: * Disable the HSI48 clock. @@ -251,11 +252,11 @@ void stm32wb_rcc_enable_hsi48(crs_syncsrc_t syncsrc); * ****************************************************************************/ -void stm32wb_rcc_disable_hsi48(void); +void stm32_rcc_disable_hsi48(void); #undef EXTERN #if defined(__cplusplus) } #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32WB_STM32WB_RCC_H */ +#endif /* __ARCH_ARM_SRC_STM32WB_STM32_RCC_H */ diff --git a/arch/arm/src/stm32wb/stm32wb_rcc_hsi48.c b/arch/arm/src/stm32wb/stm32wb_rcc_hsi48.c index e8d12b2d35282..c3276e6d236a7 100644 --- a/arch/arm/src/stm32wb/stm32wb_rcc_hsi48.c +++ b/arch/arm/src/stm32wb/stm32wb_rcc_hsi48.c @@ -35,7 +35,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_rcc_enable_hsi48 + * Name: stm32_rcc_enable_hsi48 * * Description: * HSI48 clock signal is generated from an internal 48 MHz RC oscillator @@ -61,7 +61,7 @@ * ****************************************************************************/ -void stm32wb_rcc_enable_hsi48(crs_syncsrc_t syncsrc) +void stm32_rcc_enable_hsi48(crs_syncsrc_t syncsrc) { uint32_t regval; @@ -77,13 +77,13 @@ void stm32wb_rcc_enable_hsi48(crs_syncsrc_t syncsrc) * enabled. */ - regval = getreg32(STM32WB_RCC_CRRCR); + regval = getreg32(STM32_RCC_CRRCR); regval |= RCC_CRRCR_HSI48ON; - putreg32(regval, STM32WB_RCC_CRRCR); + putreg32(regval, STM32_RCC_CRRCR); /* Wait for the HSI48 clock to stabilize */ - while ((getreg32(STM32WB_RCC_CRRCR) & RCC_CRRCR_HSI48RDY) == 0); + while ((getreg32(STM32_RCC_CRRCR) & RCC_CRRCR_HSI48RDY) == 0); /* Return if no synchronization */ @@ -97,7 +97,7 @@ void stm32wb_rcc_enable_hsi48(crs_syncsrc_t syncsrc) * clock or the USB SOF signal. */ - regval = getreg32(STM32WB_CRS_CFGR); + regval = getreg32(STM32_CRS_CFGR); regval &= ~CRS_CFGR_SYNCSRC_MASK; switch (syncsrc) @@ -116,7 +116,7 @@ void stm32wb_rcc_enable_hsi48(crs_syncsrc_t syncsrc) break; } - putreg32(regval, STM32WB_CRS_CFGR); + putreg32(regval, STM32_CRS_CFGR); /* Set the AUTOTRIMEN bit the CRS_CR register to enables the automatic * hardware adjustment of TRIM bits according to the measured frequency @@ -124,13 +124,13 @@ void stm32wb_rcc_enable_hsi48(crs_syncsrc_t syncsrc) * frequency error counter and SYNC events. */ - regval = getreg32(STM32WB_CRS_CR); + regval = getreg32(STM32_CRS_CR); regval |= CRS_CR_AUTOTRIMEN | CRS_CR_CEN; - putreg32(regval, STM32WB_CRS_CR); + putreg32(regval, STM32_CRS_CR); } /**************************************************************************** - * Name: stm32wb_rcc_disable_hsi48 + * Name: stm32_rcc_disable_hsi48 * * Description: * Disable the HSI48 clock. @@ -143,24 +143,24 @@ void stm32wb_rcc_enable_hsi48(crs_syncsrc_t syncsrc) * ****************************************************************************/ -void stm32wb_rcc_disable_hsi48(void) +void stm32_rcc_disable_hsi48(void) { uint32_t regval; /* Disable the HSI48 clock */ - regval = getreg32(STM32WB_RCC_CRRCR); + regval = getreg32(STM32_RCC_CRRCR); regval &= ~RCC_CRRCR_HSI48ON; - putreg32(regval, STM32WB_RCC_CRRCR); + putreg32(regval, STM32_RCC_CRRCR); /* Set other registers to the default settings. */ - regval = getreg32(STM32WB_CRS_CFGR); + regval = getreg32(STM32_CRS_CFGR); regval &= ~CRS_CFGR_SYNCSRC_MASK; regval |= CRS_CFGR_SYNCSRC_USBSOF; - putreg32(regval, STM32WB_CRS_CFGR); + putreg32(regval, STM32_CRS_CFGR); - regval = getreg32(STM32WB_CRS_CR); + regval = getreg32(STM32_CRS_CR); regval &= ~CRS_CR_AUTOTRIMEN; - putreg32(regval, STM32WB_CRS_CR); + putreg32(regval, STM32_CRS_CR); } diff --git a/arch/arm/src/stm32wb/stm32wb_rcc_lse.c b/arch/arm/src/stm32wb/stm32wb_rcc_lse.c index 4927de6dec4cd..f5af711a996aa 100644 --- a/arch/arm/src/stm32wb/stm32wb_rcc_lse.c +++ b/arch/arm/src/stm32wb/stm32wb_rcc_lse.c @@ -29,22 +29,22 @@ #include "arm_internal.h" #include "stm32wb_pwr.h" #include "stm32wb_rcc.h" -#include "stm32wb_waste.h" +#include "stm32_waste.h" /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ -#ifdef CONFIG_STM32WB_RTC_LSECLOCK_START_DRV_CAPABILITY -# if CONFIG_STM32WB_RTC_LSECLOCK_START_DRV_CAPABILITY < 0 || \ - CONFIG_STM32WB_RTC_LSECLOCK_START_DRV_CAPABILITY > 3 +#ifdef CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY +# if CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY < 0 || \ + CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY > 3 # error "Invalid LSE drive capability setting" # endif #endif -#ifdef CONFIG_STM32WB_RTC_LSECLOCK_RUN_DRV_CAPABILITY -# if CONFIG_STM32WB_RTC_LSECLOCK_RUN_DRV_CAPABILITY < 0 || \ - CONFIG_STM32WB_RTC_LSECLOCK_RUN_DRV_CAPABILITY > 3 +#ifdef CONFIG_STM32_RTC_LSECLOCK_RUN_DRV_CAPABILITY +# if CONFIG_STM32_RTC_LSECLOCK_RUN_DRV_CAPABILITY < 0 || \ + CONFIG_STM32_RTC_LSECLOCK_RUN_DRV_CAPABILITY > 3 # error "Invalid LSE drive capability setting" # endif #endif @@ -54,21 +54,21 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_rcc_enable_lse + * Name: stm32_rcc_enable_lse * * Description: * Enable the External Low-Speed (LSE) oscillator. * ****************************************************************************/ -void stm32wb_rcc_enable_lse(void) +void stm32_rcc_enable_lse(void) { bool writable; uint32_t regval; /* Check if the External Low-Speed (LSE) oscillator is already running. */ - regval = getreg32(STM32WB_RCC_BDCR); + regval = getreg32(STM32_RCC_BDCR); if ((regval & (RCC_BDCR_LSEON | RCC_BDCR_LSERDY)) != (RCC_BDCR_LSEON | RCC_BDCR_LSERDY)) @@ -78,7 +78,7 @@ void stm32wb_rcc_enable_lse(void) * in the PWR CR register before to configuring the LSE. */ - writable = stm32wb_pwr_enablebkp(true); + writable = stm32_pwr_enablebkp(true); /* Enable the External Low-Speed (LSE) oscillator by setting the * LSEON bit the RCC BDCR register. @@ -86,41 +86,41 @@ void stm32wb_rcc_enable_lse(void) regval |= RCC_BDCR_LSEON; -#ifdef CONFIG_STM32WB_RTC_LSECLOCK_START_DRV_CAPABILITY +#ifdef CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY /* Set start-up drive capability for LSE oscillator. */ regval &= ~RCC_BDCR_LSEDRV_MASK; - regval |= CONFIG_STM32WB_RTC_LSECLOCK_START_DRV_CAPABILITY << + regval |= CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY << RCC_BDCR_LSEDRV_SHIFT; #endif - putreg32(regval, STM32WB_RCC_BDCR); + putreg32(regval, STM32_RCC_BDCR); /* Wait for the LSE clock to be ready */ - while (((regval = getreg32(STM32WB_RCC_BDCR)) & RCC_BDCR_LSERDY) == 0) + while (((regval = getreg32(STM32_RCC_BDCR)) & RCC_BDCR_LSERDY) == 0) { - stm32wb_waste(); + stm32_waste(); } -#if defined(CONFIG_STM32WB_RTC_LSECLOCK_RUN_DRV_CAPABILITY) && \ - CONFIG_STM32WB_RTC_LSECLOCK_START_DRV_CAPABILITY != \ - CONFIG_STM32WB_RTC_LSECLOCK_RUN_DRV_CAPABILITY +#if defined(CONFIG_STM32_RTC_LSECLOCK_RUN_DRV_CAPABILITY) && \ + CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY != \ + CONFIG_STM32_RTC_LSECLOCK_RUN_DRV_CAPABILITY -# if CONFIG_STM32WB_RTC_LSECLOCK_RUN_DRV_CAPABILITY != 0 +# if CONFIG_STM32_RTC_LSECLOCK_RUN_DRV_CAPABILITY != 0 # error "STM32WB only allows lowering LSE drive capability to zero" # endif /* Set running drive capability for LSE oscillator. */ regval &= ~RCC_BDCR_LSEDRV_MASK; - regval |= CONFIG_STM32WB_RTC_LSECLOCK_RUN_DRV_CAPABILITY << + regval |= CONFIG_STM32_RTC_LSECLOCK_RUN_DRV_CAPABILITY << RCC_BDCR_LSEDRV_SHIFT; - putreg32(regval, STM32WB_RCC_BDCR); + putreg32(regval, STM32_RCC_BDCR); #endif /* Disable backup domain access if it was disabled on entry */ - stm32wb_pwr_enablebkp(writable); + stm32_pwr_enablebkp(writable); } } diff --git a/arch/arm/src/stm32wb/stm32wb_rcc_lsi.c b/arch/arm/src/stm32wb/stm32wb_rcc_lsi.c index 32597118fbfd8..7dcdc39a50b48 100644 --- a/arch/arm/src/stm32wb/stm32wb_rcc_lsi.c +++ b/arch/arm/src/stm32wb/stm32wb_rcc_lsi.c @@ -34,41 +34,41 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_rcc_enable_lsi + * Name: stm32_rcc_enable_lsi * * Description: * Enable the Internal Low-Speed (LSI) RC Oscillator. * ****************************************************************************/ -void stm32wb_rcc_enable_lsi(void) +void stm32_rcc_enable_lsi(void) { /* Enable the Internal Low-Speed (LSI) RC Oscillator by setting the LSION * bit the RCC CSR register. */ - modifyreg32(STM32WB_RCC_CSR, 0, RCC_CSR_LSI1ON); + modifyreg32(STM32_RCC_CSR, 0, RCC_CSR_LSI1ON); /* Wait for the internal LSI oscillator to be stable. */ - while ((getreg32(STM32WB_RCC_CSR) & RCC_CSR_LSI1RDY) == 0); + while ((getreg32(STM32_RCC_CSR) & RCC_CSR_LSI1RDY) == 0); } /**************************************************************************** - * Name: stm32wb_rcc_disable_lsi + * Name: stm32_rcc_disable_lsi * * Description: * Disable the Internal Low-Speed (LSI) RC Oscillator. * ****************************************************************************/ -void stm32wb_rcc_disable_lsi(void) +void stm32_rcc_disable_lsi(void) { /* Enable the Internal Low-Speed (LSI) RC Oscillator by setting the LSION * bit the RCC CSR register. */ - modifyreg32(STM32WB_RCC_CSR, RCC_CSR_LSI1ON, 0); + modifyreg32(STM32_RCC_CSR, RCC_CSR_LSI1ON, 0); /* LSIRDY should go low after 3 LSI clock cycles */ } diff --git a/arch/arm/src/stm32wb/stm32wb_rtc.c b/arch/arm/src/stm32wb/stm32wb_rtc.c index f33974fdb4e94..ed057295c6929 100644 --- a/arch/arm/src/stm32wb/stm32wb_rtc.c +++ b/arch/arm/src/stm32wb/stm32wb_rtc.c @@ -43,7 +43,7 @@ #include "stm32wb_rtc.h" #include "stm32wb_exti.h" -#ifdef CONFIG_STM32WB_RTC +#ifdef CONFIG_STM32_RTC /**************************************************************************** * Pre-processor Definitions @@ -64,8 +64,8 @@ # error "CONFIG_RTC_HIRES must NOT be set with this driver" #endif -#ifndef CONFIG_STM32WB_PWR -# error "CONFIG_STM32WB_PWR must selected to use this driver" +#ifndef CONFIG_STM32_PWR +# error "CONFIG_STM32_PWR must selected to use this driver" #endif /* Constants ****************************************************************/ @@ -139,23 +139,23 @@ static inline void rtc_enable_alarm(void); static void rtc_dumpregs(const char *msg) { rtcinfo("%s:\n", msg); - rtcinfo(" TR: %08" PRIx32 "\n", getreg32(STM32WB_RTC_TR)); - rtcinfo(" DR: %08" PRIx32 "\n", getreg32(STM32WB_RTC_DR)); - rtcinfo(" CR: %08" PRIx32 "\n", getreg32(STM32WB_RTC_CR)); - rtcinfo(" ISR: %08" PRIx32 "\n", getreg32(STM32WB_RTC_ISR)); - rtcinfo(" PRER: %08" PRIx32 "\n", getreg32(STM32WB_RTC_PRER)); - rtcinfo(" WUTR: %08" PRIx32 "\n", getreg32(STM32WB_RTC_WUTR)); - rtcinfo(" ALRMAR: %08" PRIx32 "\n", getreg32(STM32WB_RTC_ALRMAR)); - rtcinfo(" ALRMBR: %08" PRIx32 "\n", getreg32(STM32WB_RTC_ALRMBR)); - rtcinfo(" SHIFTR: %08" PRIx32 "\n", getreg32(STM32WB_RTC_SHIFTR)); - rtcinfo(" TSTR: %08" PRIx32 "\n", getreg32(STM32WB_RTC_TSTR)); - rtcinfo(" TSDR: %08" PRIx32 "\n", getreg32(STM32WB_RTC_TSDR)); - rtcinfo(" TSSSR: %08" PRIx32 "\n", getreg32(STM32WB_RTC_TSSSR)); - rtcinfo(" CALR: %08" PRIx32 "\n", getreg32(STM32WB_RTC_CALR)); - rtcinfo(" TAMPCR: %08" PRIx32 "\n", getreg32(STM32WB_RTC_TAMPCR)); - rtcinfo("ALRMASSR: %08" PRIx32 "\n", getreg32(STM32WB_RTC_ALRMASSR)); - rtcinfo("ALRMBSSR: %08" PRIx32 "\n", getreg32(STM32WB_RTC_ALRMBSSR)); - rtcinfo(" OR: %08" PRIx32 "\n", getreg32(STM32WB_RTC_OR)); + rtcinfo(" TR: %08" PRIx32 "\n", getreg32(STM32_RTC_TR)); + rtcinfo(" DR: %08" PRIx32 "\n", getreg32(STM32_RTC_DR)); + rtcinfo(" CR: %08" PRIx32 "\n", getreg32(STM32_RTC_CR)); + rtcinfo(" ISR: %08" PRIx32 "\n", getreg32(STM32_RTC_ISR)); + rtcinfo(" PRER: %08" PRIx32 "\n", getreg32(STM32_RTC_PRER)); + rtcinfo(" WUTR: %08" PRIx32 "\n", getreg32(STM32_RTC_WUTR)); + rtcinfo(" ALRMAR: %08" PRIx32 "\n", getreg32(STM32_RTC_ALRMAR)); + rtcinfo(" ALRMBR: %08" PRIx32 "\n", getreg32(STM32_RTC_ALRMBR)); + rtcinfo(" SHIFTR: %08" PRIx32 "\n", getreg32(STM32_RTC_SHIFTR)); + rtcinfo(" TSTR: %08" PRIx32 "\n", getreg32(STM32_RTC_TSTR)); + rtcinfo(" TSDR: %08" PRIx32 "\n", getreg32(STM32_RTC_TSDR)); + rtcinfo(" TSSSR: %08" PRIx32 "\n", getreg32(STM32_RTC_TSSSR)); + rtcinfo(" CALR: %08" PRIx32 "\n", getreg32(STM32_RTC_CALR)); + rtcinfo(" TAMPCR: %08" PRIx32 "\n", getreg32(STM32_RTC_TAMPCR)); + rtcinfo("ALRMASSR: %08" PRIx32 "\n", getreg32(STM32_RTC_ALRMASSR)); + rtcinfo("ALRMBSSR: %08" PRIx32 "\n", getreg32(STM32_RTC_ALRMBSSR)); + rtcinfo(" OR: %08" PRIx32 "\n", getreg32(STM32_RTC_OR)); rtcinfo("MAGICREG: %08" PRIx32 "\n", getreg32(RTC_MAGIC_REG)); } #else @@ -199,7 +199,7 @@ static void rtc_wprunlock(void) { /* Enable write access to the backup domain. */ - stm32wb_pwr_enablebkp(true); + stm32_pwr_enablebkp(true); /* The following steps are required to unlock the write protection on * all the RTC registers (except for RTC_ISR[13:8], RTC_TAFCR, and @@ -211,8 +211,8 @@ static void rtc_wprunlock(void) * Writing a wrong key re-activates the write protection. */ - putreg32(RTC_WPR_KEY1, STM32WB_RTC_WPR); - putreg32(RTC_WPR_KEY2, STM32WB_RTC_WPR); + putreg32(RTC_WPR_KEY1, STM32_RTC_WPR); + putreg32(RTC_WPR_KEY2, STM32_RTC_WPR); } /**************************************************************************** @@ -233,11 +233,11 @@ static inline void rtc_wprlock(void) { /* Writing any wrong key re-activates the write protection. */ - putreg32(0xff, STM32WB_RTC_WPR); + putreg32(0xff, STM32_RTC_WPR); /* Disable write access to the backup domain. */ - stm32wb_pwr_enablebkp(false); + stm32_pwr_enablebkp(false); } /**************************************************************************** @@ -263,16 +263,16 @@ static int rtc_synchwait(void) /* Clear Registers synchronization flag (RSF) */ - regval = getreg32(STM32WB_RTC_ISR); + regval = getreg32(STM32_RTC_ISR); regval &= ~RTC_ISR_RSF; - putreg32(regval, STM32WB_RTC_ISR); + putreg32(regval, STM32_RTC_ISR); /* Now wait the registers to become synchronised */ ret = -ETIMEDOUT; for (timeout = 0; timeout < SYNCHRO_TIMEOUT; timeout++) { - regval = getreg32(STM32WB_RTC_ISR); + regval = getreg32(STM32_RTC_ISR); if ((regval & RTC_ISR_RSF) != 0) { /* Synchronized */ @@ -307,21 +307,21 @@ static int rtc_enterinit(void) /* Check if the Initialization mode is already set */ - regval = getreg32(STM32WB_RTC_ISR); + regval = getreg32(STM32_RTC_ISR); ret = OK; if ((regval & RTC_ISR_INITF) == 0) { /* Set the Initialization mode */ - putreg32(RTC_ISR_INIT, STM32WB_RTC_ISR); + putreg32(RTC_ISR_INIT, STM32_RTC_ISR); /* Wait until the RTC is in the INIT state (or a timeout occurs) */ ret = -ETIMEDOUT; for (timeout = 0; timeout < INITMODE_TIMEOUT; timeout++) { - regval = getreg32(STM32WB_RTC_ISR); + regval = getreg32(STM32_RTC_ISR); if ((regval & RTC_ISR_INITF) != 0) { ret = OK; @@ -351,9 +351,9 @@ static void rtc_exitinit(void) { uint32_t regval; - regval = getreg32(STM32WB_RTC_ISR); + regval = getreg32(STM32_RTC_ISR); regval &= ~(RTC_ISR_INIT); - putreg32(regval, STM32WB_RTC_ISR); + putreg32(regval, STM32_RTC_ISR); } /**************************************************************************** @@ -425,18 +425,18 @@ static void rtc_resume(void) /* Clear the RTC alarm flags */ - regval = getreg32(STM32WB_RTC_ISR); + regval = getreg32(STM32_RTC_ISR); regval &= ~(RTC_ISR_ALRAF | RTC_ISR_ALRBF); - putreg32(regval, STM32WB_RTC_ISR); + putreg32(regval, STM32_RTC_ISR); /* Clear the EXTI Line 17 Pending bit (Connected internally to RTC Alarm) */ - putreg32(EXTI_PR1_PIF(EXTI_EVT_RTCALARM), STM32WB_EXTI_PR1); + putreg32(EXTI_PR1_PIF(EXTI_EVT_RTCALARM), STM32_EXTI_PR1); #endif } /**************************************************************************** - * Name: stm32wb_rtc_alarm_handler + * Name: stm32_rtc_alarm_handler * * Description: * RTC ALARM interrupt service routine through the EXTI line @@ -451,7 +451,7 @@ static void rtc_resume(void) ****************************************************************************/ #ifdef CONFIG_RTC_ALARM -static int stm32wb_rtc_alarm_handler(int irq, void *context, +static int stm32_rtc_alarm_handler(int irq, void *context, void *rtc_handler_arg) { struct alm_cbinfo_s *cbinfo; @@ -465,14 +465,14 @@ static int stm32wb_rtc_alarm_handler(int irq, void *context, * backup data registers and backup SRAM). */ - stm32wb_pwr_enablebkp(true); + stm32_pwr_enablebkp(true); /* Check for EXTI from Alarm A or B and handle according */ - cr = getreg32(STM32WB_RTC_CR); + cr = getreg32(STM32_RTC_CR); if ((cr & RTC_CR_ALRAIE) != 0) { - isr = getreg32(STM32WB_RTC_ISR); + isr = getreg32(STM32_RTC_ISR); if ((isr & RTC_ISR_ALRAF) != 0) { cbinfo = &g_alarmcb[RTC_ALARMA]; @@ -491,17 +491,17 @@ static int stm32wb_rtc_alarm_handler(int irq, void *context, /* note, bits 8-13 do /not/ require the write enable procedure */ - isr = getreg32(STM32WB_RTC_ISR); + isr = getreg32(STM32_RTC_ISR); isr &= ~RTC_ISR_ALRAF; - putreg32(isr, STM32WB_RTC_ISR); + putreg32(isr, STM32_RTC_ISR); } } #if CONFIG_RTC_NALARMS > 1 - cr = getreg32(STM32WB_RTC_CR); + cr = getreg32(STM32_RTC_CR); if ((cr & RTC_CR_ALRBIE) != 0) { - isr = getreg32(STM32WB_RTC_ISR); + isr = getreg32(STM32_RTC_ISR); if ((isr & RTC_ISR_ALRBF) != 0) { cbinfo = &g_alarmcb[RTC_ALARMB]; @@ -520,9 +520,9 @@ static int stm32wb_rtc_alarm_handler(int irq, void *context, /* note, bits 8-13 do /not/ require the write enable procedure */ - isr = getreg32(STM32WB_RTC_ISR); + isr = getreg32(STM32_RTC_ISR); isr &= ~RTC_ISR_ALRBF; - putreg32(isr, STM32WB_RTC_ISR); + putreg32(isr, STM32_RTC_ISR); } } #endif @@ -531,7 +531,7 @@ static int stm32wb_rtc_alarm_handler(int irq, void *context, * data registers and backup SRAM). */ - stm32wb_pwr_enablebkp(false); + stm32_pwr_enablebkp(false); return ret; } @@ -565,7 +565,7 @@ static int rtchw_check_alrawf(void) for (timeout = 0; timeout < INITMODE_TIMEOUT; timeout++) { - regval = getreg32(STM32WB_RTC_ISR); + regval = getreg32(STM32_RTC_ISR); if ((regval & RTC_ISR_ALRAWF) != 0) { ret = OK; @@ -591,7 +591,7 @@ static int rtchw_check_alrbwf(void) for (timeout = 0; timeout < INITMODE_TIMEOUT; timeout++) { - regval = getreg32(STM32WB_RTC_ISR); + regval = getreg32(STM32_RTC_ISR); if ((regval & RTC_ISR_ALRBWF) != 0) { ret = OK; @@ -630,12 +630,12 @@ static int rtchw_set_alrmar(rtc_alarmreg_t alarmreg) /* Disable RTC alarm A & Interrupt A */ - modifyreg32(STM32WB_RTC_CR, (RTC_CR_ALRAE | RTC_CR_ALRAIE), 0); + modifyreg32(STM32_RTC_CR, (RTC_CR_ALRAE | RTC_CR_ALRAIE), 0); /* Ensure Alarm A flag reset; this is edge triggered */ - isr = getreg32(STM32WB_RTC_ISR) & ~RTC_ISR_ALRAF; - putreg32(isr, STM32WB_RTC_ISR); + isr = getreg32(STM32_RTC_ISR) & ~RTC_ISR_ALRAF; + putreg32(isr, STM32_RTC_ISR); /* Wait for Alarm A to be writable */ @@ -647,13 +647,13 @@ static int rtchw_set_alrmar(rtc_alarmreg_t alarmreg) /* Set the RTC Alarm A register */ - putreg32(alarmreg, STM32WB_RTC_ALRMAR); - putreg32(0, STM32WB_RTC_ALRMASSR); - rtcinfo(" ALRMAR: %08" PRIx32 "\n", getreg32(STM32WB_RTC_ALRMAR)); + putreg32(alarmreg, STM32_RTC_ALRMAR); + putreg32(0, STM32_RTC_ALRMASSR); + rtcinfo(" ALRMAR: %08" PRIx32 "\n", getreg32(STM32_RTC_ALRMAR)); /* Enable RTC alarm A */ - modifyreg32(STM32WB_RTC_CR, 0, (RTC_CR_ALRAE | RTC_CR_ALRAIE)); + modifyreg32(STM32_RTC_CR, 0, (RTC_CR_ALRAE | RTC_CR_ALRAIE)); errout_with_wprunlock: rtc_wprlock(); @@ -673,12 +673,12 @@ static int rtchw_set_alrmbr(rtc_alarmreg_t alarmreg) /* Disable RTC alarm B & Interrupt B */ - modifyreg32(STM32WB_RTC_CR, (RTC_CR_ALRBE | RTC_CR_ALRBIE), 0); + modifyreg32(STM32_RTC_CR, (RTC_CR_ALRBE | RTC_CR_ALRBIE), 0); /* Ensure Alarm B flag reset; this is edge triggered */ - isr = getreg32(STM32WB_RTC_ISR) & ~RTC_ISR_ALRBF; - putreg32(isr, STM32WB_RTC_ISR); + isr = getreg32(STM32_RTC_ISR) & ~RTC_ISR_ALRBF; + putreg32(isr, STM32_RTC_ISR); /* Wait for Alarm B to be writable */ @@ -690,13 +690,13 @@ static int rtchw_set_alrmbr(rtc_alarmreg_t alarmreg) /* Set the RTC Alarm B register */ - putreg32(alarmreg, STM32WB_RTC_ALRMBR); - putreg32(0, STM32WB_RTC_ALRMBSSR); - rtcinfo(" ALRMBR: %08" PRIx32 "\n", getreg32(STM32WB_RTC_ALRMBR)); + putreg32(alarmreg, STM32_RTC_ALRMBR); + putreg32(0, STM32_RTC_ALRMBSSR); + rtcinfo(" ALRMBR: %08" PRIx32 "\n", getreg32(STM32_RTC_ALRMBR)); /* Enable RTC alarm B */ - modifyreg32(STM32WB_RTC_CR, 0, (RTC_CR_ALRBE | RTC_CR_ALRBIE)); + modifyreg32(STM32_RTC_CR, 0, (RTC_CR_ALRBE | RTC_CR_ALRBIE)); rtchw_set_alrmbr_exit: rtc_wprlock(); @@ -737,14 +737,14 @@ static inline void rtc_enable_alarm(void) * 3. Configure the RTC to generate RTC alarms (Alarm A or Alarm B). */ - stm32wb_exti_alarm(true, false, true, stm32wb_rtc_alarm_handler, NULL); + stm32_exti_alarm(true, false, true, stm32_rtc_alarm_handler, NULL); g_alarm_enabled = true; } } #endif /**************************************************************************** - * Name: stm32wb_rtc_getalarmdatetime + * Name: stm32_rtc_getalarmdatetime * * Description: * Get the current date and time for a RTC alarm. @@ -759,7 +759,7 @@ static inline void rtc_enable_alarm(void) ****************************************************************************/ #ifdef CONFIG_RTC_ALARM -static int stm32wb_rtc_getalarmdatetime(rtc_alarmreg_t reg, +static int stm32_rtc_getalarmdatetime(rtc_alarmreg_t reg, struct tm *tp) { uint32_t data; @@ -800,7 +800,7 @@ static int stm32wb_rtc_getalarmdatetime(rtc_alarmreg_t reg, ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_rtc_is_initialized + * Name: stm32_rtc_is_initialized * * Description: * Returns 'true' if the RTC has been initialized @@ -816,7 +816,7 @@ static int stm32wb_rtc_getalarmdatetime(rtc_alarmreg_t reg, * ****************************************************************************/ -bool stm32wb_rtc_is_initialized(void) +bool stm32_rtc_is_initialized(void) { uint32_t regval; @@ -851,23 +851,23 @@ int up_rtc_initialize(void) * backed, we don't need or want to re-initialize on each reset. */ - init_stat = stm32wb_rtc_is_initialized(); + init_stat = stm32_rtc_is_initialized(); if (!init_stat) { /* Enable write access to the backup domain (RTC registers, RTC * backup data registers and backup SRAM). */ - stm32wb_pwr_enablebkp(true); + stm32_pwr_enablebkp(true); -#if defined(CONFIG_STM32WB_RTC_HSECLOCK) - modifyreg32(STM32WB_RCC_BDCR, RCC_BDCR_RTCSEL_MASK, +#if defined(CONFIG_STM32_RTC_HSECLOCK) + modifyreg32(STM32_RCC_BDCR, RCC_BDCR_RTCSEL_MASK, RCC_BDCR_RTCSEL_HSE); -#elif defined(CONFIG_STM32WB_RTC_LSICLOCK) - modifyreg32(STM32WB_RCC_BDCR, RCC_BDCR_RTCSEL_MASK, +#elif defined(CONFIG_STM32_RTC_LSICLOCK) + modifyreg32(STM32_RCC_BDCR, RCC_BDCR_RTCSEL_MASK, RCC_BDCR_RTCSEL_LSI); -#elif defined(CONFIG_STM32WB_RTC_LSECLOCK) - modifyreg32(STM32WB_RCC_BDCR, RCC_BDCR_RTCSEL_MASK, +#elif defined(CONFIG_STM32_RTC_LSECLOCK) + modifyreg32(STM32_RCC_BDCR, RCC_BDCR_RTCSEL_MASK, RCC_BDCR_RTCSEL_LSE); #else # error "No clock for RTC!" @@ -875,7 +875,7 @@ int up_rtc_initialize(void) /* Enable the RTC Clock by setting the RTCEN bit in the RCC register */ - modifyreg32(STM32WB_RCC_BDCR, 0, RCC_BDCR_RTCEN); + modifyreg32(STM32_RCC_BDCR, 0, RCC_BDCR_RTCEN); /* Disable the write protection for RTC registers */ @@ -893,7 +893,7 @@ int up_rtc_initialize(void) * RTC backup data registers and backup SRAM). */ - stm32wb_pwr_enablebkp(false); + stm32_pwr_enablebkp(false); rtc_dumpregs("After Failed Initialization"); @@ -903,13 +903,13 @@ int up_rtc_initialize(void) { /* Clear RTC_CR FMT, OSEL and POL Bits */ - regval = getreg32(STM32WB_RTC_CR); + regval = getreg32(STM32_RTC_CR); regval &= ~(RTC_CR_FMT | RTC_CR_OSEL_MASK | RTC_CR_POL); - putreg32(regval, STM32WB_RTC_CR); + putreg32(regval, STM32_RTC_CR); /* Configure RTC pre-scaler with the required values */ -#ifdef CONFIG_STM32WB_RTC_HSECLOCK +#ifdef CONFIG_STM32_RTC_HSECLOCK /* The HSE is divided by 32 prior to the prescaler we set here. * 1953 * NOTE: max HSE/32 is 4 MHz if it is to be used with RTC @@ -921,21 +921,21 @@ int up_rtc_initialize(void) putreg32(((uint32_t)7812 << RTC_PRER_PREDIV_S_SHIFT) | ((uint32_t)0x7f << RTC_PRER_PREDIV_A_SHIFT), - STM32WB_RTC_PRER); -#elif defined(CONFIG_STM32WB_RTC_LSICLOCK) + STM32_RTC_PRER); +#elif defined(CONFIG_STM32_RTC_LSICLOCK) /* Suitable values for 32.000 KHz LSI clock (29.5 - 34 KHz, * though) */ putreg32(((uint32_t)0xf9 << RTC_PRER_PREDIV_S_SHIFT) | ((uint32_t)0x7f << RTC_PRER_PREDIV_A_SHIFT), - STM32WB_RTC_PRER); -#else /* defined(CONFIG_STM32WB_RTC_LSECLOCK) */ + STM32_RTC_PRER); +#else /* defined(CONFIG_STM32_RTC_LSECLOCK) */ /* Correct values for 32.768 KHz LSE clock */ putreg32(((uint32_t)0xff << RTC_PRER_PREDIV_S_SHIFT) | ((uint32_t)0x7f << RTC_PRER_PREDIV_A_SHIFT), - STM32WB_RTC_PRER); + STM32_RTC_PRER); #endif /* Exit Initialization mode */ @@ -960,7 +960,7 @@ int up_rtc_initialize(void) * RTC backup data registers and backup SRAM). */ - stm32wb_pwr_enablebkp(false); + stm32_pwr_enablebkp(false); } } else @@ -969,7 +969,7 @@ int up_rtc_initialize(void) * backup data registers and backup SRAM). */ - stm32wb_pwr_enablebkp(true); + stm32_pwr_enablebkp(true); /* Write protection for RTC registers does not need to be disabled. */ @@ -979,7 +979,7 @@ int up_rtc_initialize(void) * data registers and backup SRAM). */ - stm32wb_pwr_enablebkp(false); + stm32_pwr_enablebkp(false); } g_rtc_enabled = true; @@ -989,7 +989,7 @@ int up_rtc_initialize(void) } /**************************************************************************** - * Name: stm32wb_rtc_getdatetime_with_subseconds + * Name: stm32_rtc_getdatetime_with_subseconds * * Description: * Get the current date and time from the date/time RTC. This interface @@ -1009,10 +1009,10 @@ int up_rtc_initialize(void) * ****************************************************************************/ -int stm32wb_rtc_getdatetime_with_subseconds(struct tm *tp, +int stm32_rtc_getdatetime_with_subseconds(struct tm *tp, long *nsec) { -#ifdef CONFIG_STM32WB_HAVE_RTC_SUBSECONDS +#ifdef CONFIG_STM32_HAVE_RTC_SUBSECONDS uint32_t ssr; #endif uint32_t dr; @@ -1029,18 +1029,18 @@ int stm32wb_rtc_getdatetime_with_subseconds(struct tm *tp, do { - dr = getreg32(STM32WB_RTC_DR); - tr = getreg32(STM32WB_RTC_TR); -#ifdef CONFIG_STM32WB_HAVE_RTC_SUBSECONDS - ssr = getreg32(STM32WB_RTC_SSR); - tmp = getreg32(STM32WB_RTC_TR); + dr = getreg32(STM32_RTC_DR); + tr = getreg32(STM32_RTC_TR); +#ifdef CONFIG_STM32_HAVE_RTC_SUBSECONDS + ssr = getreg32(STM32_RTC_SSR); + tmp = getreg32(STM32_RTC_TR); if (tmp != tr) { continue; } #endif - tmp = getreg32(STM32WB_RTC_DR); + tmp = getreg32(STM32_RTC_DR); } while (tmp != dr); @@ -1089,13 +1089,13 @@ int stm32wb_rtc_getdatetime_with_subseconds(struct tm *tp, * of nsec has been provided to receive the sub-second value. */ -#ifdef CONFIG_STM32WB_HAVE_RTC_SUBSECONDS +#ifdef CONFIG_STM32_HAVE_RTC_SUBSECONDS if (nsec) { uint32_t prediv_s; uint32_t usecs; - prediv_s = getreg32(STM32WB_RTC_PRER) & RTC_PRER_PREDIV_S_MASK; + prediv_s = getreg32(STM32_RTC_PRER) & RTC_PRER_PREDIV_S_MASK; prediv_s >>= RTC_PRER_PREDIV_S_SHIFT; ssr &= RTC_SSR_MASK; @@ -1140,7 +1140,7 @@ int stm32wb_rtc_getdatetime_with_subseconds(struct tm *tp, int up_rtc_getdatetime(struct tm *tp) { - return stm32wb_rtc_getdatetime_with_subseconds(tp, NULL); + return stm32_rtc_getdatetime_with_subseconds(tp, NULL); } /**************************************************************************** @@ -1169,17 +1169,17 @@ int up_rtc_getdatetime(struct tm *tp) ****************************************************************************/ #ifdef CONFIG_ARCH_HAVE_RTC_SUBSECONDS -# ifndef CONFIG_STM32WB_HAVE_RTC_SUBSECONDS -# error "Invalid config, enable CONFIG_STM32WB_HAVE_RTC_SUBSECONDS." +# ifndef CONFIG_STM32_HAVE_RTC_SUBSECONDS +# error "Invalid config, enable CONFIG_STM32_HAVE_RTC_SUBSECONDS." # endif int up_rtc_getdatetime_with_subseconds(struct tm *tp, long *nsec) { - return stm32wb_rtc_getdatetime_with_subseconds(tp, nsec); + return stm32_rtc_getdatetime_with_subseconds(tp, nsec); } #endif /**************************************************************************** - * Name: stm32wb_rtc_setdatetime + * Name: stm32_rtc_setdatetime * * Description: * Set the RTC to the provided time. RTC implementations which provide @@ -1194,7 +1194,7 @@ int up_rtc_getdatetime_with_subseconds(struct tm *tp, long *nsec) * ****************************************************************************/ -int stm32wb_rtc_setdatetime(const struct tm *tp) +int stm32_rtc_setdatetime(const struct tm *tp) { uint32_t tr; uint32_t dr; @@ -1242,8 +1242,8 @@ int stm32wb_rtc_setdatetime(const struct tm *tp) { /* Set the RTC TR and DR registers */ - putreg32(tr, STM32WB_RTC_TR); - putreg32(dr, STM32WB_RTC_DR); + putreg32(tr, STM32_RTC_TR); + putreg32(dr, STM32_RTC_DR); /* Exit Initialization mode and wait for the RTC Time and Date * registers to be synchronized with RTC APB clock. @@ -1257,9 +1257,9 @@ int stm32wb_rtc_setdatetime(const struct tm *tp) if (getreg32(RTC_MAGIC_REG) != RTC_MAGIC_TIME_SET) { - stm32wb_pwr_enablebkp(true); + stm32_pwr_enablebkp(true); putreg32(RTC_MAGIC_TIME_SET, RTC_MAGIC_REG); - stm32wb_pwr_enablebkp(false); + stm32_pwr_enablebkp(false); } /* Re-enable the write protection for RTC registers */ @@ -1270,7 +1270,7 @@ int stm32wb_rtc_setdatetime(const struct tm *tp) } /**************************************************************************** - * Name: stm32wb_rtc_havesettime + * Name: stm32_rtc_havesettime * * Description: * Check if RTC time has been set. @@ -1280,7 +1280,7 @@ int stm32wb_rtc_setdatetime(const struct tm *tp) * ****************************************************************************/ -bool stm32wb_rtc_havesettime(void) +bool stm32_rtc_havesettime(void) { return getreg32(RTC_MAGIC_REG) == RTC_MAGIC_TIME_SET; } @@ -1309,11 +1309,11 @@ int up_rtc_settime(const struct timespec *tp) */ gmtime_r(&tp->tv_sec, &newtime); - return stm32wb_rtc_setdatetime(&newtime); + return stm32_rtc_setdatetime(&newtime); } /**************************************************************************** - * Name: stm32wb_rtc_setalarm + * Name: stm32_rtc_setalarm * * Description: * Set an alarm to an absolute time using associated hardware. @@ -1327,7 +1327,7 @@ int up_rtc_settime(const struct timespec *tp) ****************************************************************************/ #ifdef CONFIG_RTC_ALARM -int stm32wb_rtc_setalarm(struct alm_setalarm_s *alminfo) +int stm32_rtc_setalarm(struct alm_setalarm_s *alminfo) { struct alm_cbinfo_s *cbinfo; rtc_alarmreg_t alarmreg; @@ -1402,7 +1402,7 @@ int stm32wb_rtc_setalarm(struct alm_setalarm_s *alminfo) #endif /**************************************************************************** - * Name: stm32wb_rtc_cancelalarm + * Name: stm32_rtc_cancelalarm * * Description: * Cancel an alarm. @@ -1416,7 +1416,7 @@ int stm32wb_rtc_setalarm(struct alm_setalarm_s *alminfo) ****************************************************************************/ #ifdef CONFIG_RTC_ALARM -int stm32wb_rtc_cancelalarm(enum alm_id_e alarmid) +int stm32_rtc_cancelalarm(enum alm_id_e alarmid) { int ret = -EINVAL; @@ -1439,7 +1439,7 @@ int stm32wb_rtc_cancelalarm(enum alm_id_e alarmid) /* Disable RTC alarm and interrupt */ - modifyreg32(STM32WB_RTC_CR, (RTC_CR_ALRAE | RTC_CR_ALRAIE), 0); + modifyreg32(STM32_RTC_CR, (RTC_CR_ALRAE | RTC_CR_ALRAIE), 0); ret = rtchw_check_alrawf(); if (ret < 0) @@ -1449,8 +1449,8 @@ int stm32wb_rtc_cancelalarm(enum alm_id_e alarmid) /* Unset the alarm */ - putreg32(0xffffffff, STM32WB_RTC_ALRMAR); - modifyreg32(STM32WB_RTC_ISR, RTC_ISR_ALRAF, 0); + putreg32(0xffffffff, STM32_RTC_ALRMAR); + modifyreg32(STM32_RTC_ISR, RTC_ISR_ALRAF, 0); rtc_wprlock(); ret = OK; } @@ -1470,7 +1470,7 @@ int stm32wb_rtc_cancelalarm(enum alm_id_e alarmid) /* Disable RTC alarm and interrupt */ - modifyreg32(STM32WB_RTC_CR, (RTC_CR_ALRBE | RTC_CR_ALRBIE), 0); + modifyreg32(STM32_RTC_CR, (RTC_CR_ALRBE | RTC_CR_ALRBIE), 0); ret = rtchw_check_alrbwf(); if (ret < 0) @@ -1480,8 +1480,8 @@ int stm32wb_rtc_cancelalarm(enum alm_id_e alarmid) /* Unset the alarm */ - putreg32(0xffffffff, STM32WB_RTC_ALRMBR); - modifyreg32(STM32WB_RTC_ISR, RTC_ISR_ALRBF, 0); + putreg32(0xffffffff, STM32_RTC_ALRMBR); + modifyreg32(STM32_RTC_ISR, RTC_ISR_ALRBF, 0); rtc_wprlock(); ret = OK; } @@ -1502,7 +1502,7 @@ int stm32wb_rtc_cancelalarm(enum alm_id_e alarmid) #endif /**************************************************************************** - * Name: stm32wb_rtc_rdalarm + * Name: stm32_rtc_rdalarm * * Description: * Query an alarm configured in hardware. @@ -1516,7 +1516,7 @@ int stm32wb_rtc_cancelalarm(enum alm_id_e alarmid) ****************************************************************************/ #ifdef CONFIG_RTC_ALARM -int stm32wb_rtc_rdalarm(struct alm_rdalarm_s *alminfo) +int stm32_rtc_rdalarm(struct alm_rdalarm_s *alminfo) { rtc_alarmreg_t alarmreg; int ret = -EINVAL; @@ -1528,8 +1528,8 @@ int stm32wb_rtc_rdalarm(struct alm_rdalarm_s *alminfo) { case RTC_ALARMA: { - alarmreg = STM32WB_RTC_ALRMAR; - ret = stm32wb_rtc_getalarmdatetime(alarmreg, + alarmreg = STM32_RTC_ALRMAR; + ret = stm32_rtc_getalarmdatetime(alarmreg, (struct tm *)alminfo->ar_time); } break; @@ -1537,8 +1537,8 @@ int stm32wb_rtc_rdalarm(struct alm_rdalarm_s *alminfo) #if CONFIG_RTC_NALARMS > 1 case RTC_ALARMB: { - alarmreg = STM32WB_RTC_ALRMBR; - ret = stm32wb_rtc_getalarmdatetime(alarmreg, + alarmreg = STM32_RTC_ALRMBR; + ret = stm32_rtc_getalarmdatetime(alarmreg, (struct tm *)alminfo->ar_time); } break; @@ -1554,7 +1554,7 @@ int stm32wb_rtc_rdalarm(struct alm_rdalarm_s *alminfo) #endif /**************************************************************************** - * Name: stm32wb_rtc_wakeup_handler + * Name: stm32_rtc_wakeup_handler * * Description: * RTC WAKEUP interrupt service routine through the EXTI line @@ -1568,17 +1568,17 @@ int stm32wb_rtc_rdalarm(struct alm_rdalarm_s *alminfo) ****************************************************************************/ #ifdef CONFIG_RTC_PERIODIC -static int stm32wb_rtc_wakeup_handler(int irq, void *context, void *arg) +static int stm32_rtc_wakeup_handler(int irq, void *context, void *arg) { uint32_t regval = 0; - stm32wb_pwr_enablebkp(true); + stm32_pwr_enablebkp(true); - regval = getreg32(STM32WB_RTC_ISR); + regval = getreg32(STM32_RTC_ISR); regval &= ~RTC_ISR_WUTF; - putreg32(regval, STM32WB_RTC_ISR); + putreg32(regval, STM32_RTC_ISR); - stm32wb_pwr_enablebkp(false); + stm32_pwr_enablebkp(false); if (g_wakeupcb != NULL) { @@ -1602,7 +1602,7 @@ static inline void rtc_enable_wakeup(void) { if (!g_wakeup_enabled) { - stm32wb_exti_wakeup(true, false, true, stm32wb_rtc_wakeup_handler, + stm32_exti_wakeup(true, false, true, stm32_rtc_wakeup_handler, NULL); g_wakeup_enabled = true; } @@ -1622,15 +1622,15 @@ static inline void rtc_set_wcksel(unsigned int wucksel) { uint32_t regval = 0; - regval = getreg32(STM32WB_RTC_CR); + regval = getreg32(STM32_RTC_CR); regval &= ~RTC_CR_WUCKSEL_MASK; regval |= wucksel; - putreg32(regval, STM32WB_RTC_CR); + putreg32(regval, STM32_RTC_CR); } #endif /**************************************************************************** - * Name: stm32wb_rtc_setperiodic + * Name: stm32_rtc_setperiodic * * Description: * Set a periodic RTC wakeup @@ -1645,7 +1645,7 @@ static inline void rtc_set_wcksel(unsigned int wucksel) ****************************************************************************/ #ifdef CONFIG_RTC_PERIODIC -int stm32wb_rtc_setperiodic(const struct timespec *period, +int stm32_rtc_setperiodic(const struct timespec *period, wakeupcb_t callback) { unsigned int wutr_val; @@ -1655,13 +1655,13 @@ int stm32wb_rtc_setperiodic(const struct timespec *period, uint32_t secs; uint32_t millisecs; -#if defined(CONFIG_STM32WB_RTC_HSECLOCK) +#if defined(CONFIG_STM32_RTC_HSECLOCK) # error "Periodic wakeup not available for HSE" -#elif defined(CONFIG_STM32WB_RTC_LSICLOCK) +#elif defined(CONFIG_STM32_RTC_LSICLOCK) # error "Periodic wakeup not available for LSI (and it is too inaccurate!)" -#elif defined(CONFIG_STM32WB_RTC_LSECLOCK) +#elif defined(CONFIG_STM32_RTC_LSECLOCK) const uint32_t rtc_div16_max_msecs = 16 * 1000 * 0xffffu / - STM32WB_LSE_FREQUENCY; + STM32_LSE_FREQUENCY; #else # error "No clock for RTC!" #endif @@ -1699,9 +1699,9 @@ int stm32wb_rtc_setperiodic(const struct timespec *period, /* Clear WUTE in RTC_CR to disable the wakeup timer */ - regval = getreg32(STM32WB_RTC_CR); + regval = getreg32(STM32_RTC_CR); regval &= ~RTC_CR_WUTE; - putreg32(regval, STM32WB_RTC_CR); + putreg32(regval, STM32_RTC_CR); /* Poll WUTWF until it is set in RTC_ISR (takes around 2 RTCCLK * clock cycles) @@ -1710,7 +1710,7 @@ int stm32wb_rtc_setperiodic(const struct timespec *period, ret = -ETIMEDOUT; for (timeout = 0; timeout < SYNCHRO_TIMEOUT; timeout++) { - regval = getreg32(STM32WB_RTC_ISR); + regval = getreg32(STM32_RTC_ISR); if ((regval & RTC_ISR_WUTWF) != 0) { /* Synchronized */ @@ -1734,7 +1734,7 @@ int stm32wb_rtc_setperiodic(const struct timespec *period, /* Get number of ticks. */ - ticks = millisecs * STM32WB_LSE_FREQUENCY / (16 * 1000); + ticks = millisecs * STM32_LSE_FREQUENCY / (16 * 1000); /* Wake-up is after WUT+1 ticks. */ @@ -1755,17 +1755,17 @@ int stm32wb_rtc_setperiodic(const struct timespec *period, * selection. */ - putreg32(wutr_val, STM32WB_RTC_WUTR); + putreg32(wutr_val, STM32_RTC_WUTR); - regval = getreg32(STM32WB_RTC_CR); + regval = getreg32(STM32_RTC_CR); regval |= RTC_CR_WUTIE | RTC_CR_WUTE; - putreg32(regval, STM32WB_RTC_CR); + putreg32(regval, STM32_RTC_CR); /* Just in case resets the WUTF flag in RTC_ISR */ - regval = getreg32(STM32WB_RTC_ISR); + regval = getreg32(STM32_RTC_ISR); regval &= ~RTC_ISR_WUTF; - putreg32(regval, STM32WB_RTC_ISR); + putreg32(regval, STM32_RTC_ISR); rtc_wprlock(); @@ -1774,7 +1774,7 @@ int stm32wb_rtc_setperiodic(const struct timespec *period, #endif /**************************************************************************** - * Name: stm32wb_rtc_cancelperiodic + * Name: stm32_rtc_cancelperiodic * * Description: * Cancel a periodic wakeup @@ -1787,7 +1787,7 @@ int stm32wb_rtc_setperiodic(const struct timespec *period, ****************************************************************************/ #ifdef CONFIG_RTC_PERIODIC -int stm32wb_rtc_cancelperiodic(void) +int stm32_rtc_cancelperiodic(void) { int ret = OK; int timeout = 0; @@ -1797,9 +1797,9 @@ int stm32wb_rtc_cancelperiodic(void) /* Clear WUTE and WUTIE in RTC_CR to disable the wakeup timer */ - regval = getreg32(STM32WB_RTC_CR); + regval = getreg32(STM32_RTC_CR); regval &= ~(RTC_CR_WUTE | RTC_CR_WUTIE); - putreg32(regval, STM32WB_RTC_CR); + putreg32(regval, STM32_RTC_CR); /* Poll WUTWF until it is set in RTC_ISR (takes around 2 RTCCLK * clock cycles) @@ -1808,7 +1808,7 @@ int stm32wb_rtc_cancelperiodic(void) ret = -ETIMEDOUT; for (timeout = 0; timeout < SYNCHRO_TIMEOUT; timeout++) { - regval = getreg32(STM32WB_RTC_ISR); + regval = getreg32(STM32_RTC_ISR); if ((regval & RTC_ISR_WUTWF) != 0) { /* Synchronized */ @@ -1820,9 +1820,9 @@ int stm32wb_rtc_cancelperiodic(void) /* Clears RTC_WUTR register */ - regval = getreg32(STM32WB_RTC_WUTR); + regval = getreg32(STM32_RTC_WUTR); regval &= ~RTC_WUTR_MASK; - putreg32(regval, STM32WB_RTC_WUTR); + putreg32(regval, STM32_RTC_WUTR); rtc_wprlock(); @@ -1830,4 +1830,4 @@ int stm32wb_rtc_cancelperiodic(void) } #endif -#endif /* CONFIG_STM32WB_RTC */ +#endif /* CONFIG_STM32_RTC */ diff --git a/arch/arm/src/stm32wb/stm32wb_rtc.h b/arch/arm/src/stm32wb/stm32wb_rtc.h index 6868b14ddcf15..500d5dfcd4d41 100644 --- a/arch/arm/src/stm32wb/stm32wb_rtc.h +++ b/arch/arm/src/stm32wb/stm32wb_rtc.h @@ -38,26 +38,26 @@ * Pre-processor Definitions ****************************************************************************/ -#define STM32WB_RTC_PRESCALER_SECOND 32767 /* Default prescaler +#define STM32_RTC_PRESCALER_SECOND 32767 /* Default prescaler * to get a second base */ -#define STM32WB_RTC_PRESCALER_MIN 1 /* Maximum speed +#define STM32_RTC_PRESCALER_MIN 1 /* Maximum speed * of 16384 Hz */ -#if !defined(CONFIG_STM32WB_RTC_MAGIC) -# define CONFIG_STM32WB_RTC_MAGIC (0xfacefeee) +#if !defined(CONFIG_STM32_RTC_MAGIC) +# define CONFIG_STM32_RTC_MAGIC (0xfacefeee) #endif -#if !defined(CONFIG_STM32WB_RTC_MAGIC_TIME_SET) -# define CONFIG_STM32WB_RTC_MAGIC_TIME_SET (0xf00dface) +#if !defined(CONFIG_STM32_RTC_MAGIC_TIME_SET) +# define CONFIG_STM32_RTC_MAGIC_TIME_SET (0xf00dface) #endif -#if !defined(CONFIG_STM32WB_RTC_MAGIC_REG) -# define CONFIG_STM32WB_RTC_MAGIC_REG (0) +#if !defined(CONFIG_STM32_RTC_MAGIC_REG) +# define CONFIG_STM32_RTC_MAGIC_REG (0) #endif -#define RTC_MAGIC CONFIG_STM32WB_RTC_MAGIC -#define RTC_MAGIC_TIME_SET CONFIG_STM32WB_RTC_MAGIC_TIME_SET -#define RTC_MAGIC_REG STM32WB_RTC_BKPR(CONFIG_STM32WB_RTC_MAGIC_REG) +#define RTC_MAGIC CONFIG_STM32_RTC_MAGIC +#define RTC_MAGIC_TIME_SET CONFIG_STM32_RTC_MAGIC_TIME_SET +#define RTC_MAGIC_REG STM32_RTC_BKPR(CONFIG_STM32_RTC_MAGIC_REG) /**************************************************************************** * Public Types @@ -120,7 +120,7 @@ extern "C" ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_rtc_is_initialized + * Name: stm32_rtc_is_initialized * * Description: * Returns 'true' if the RTC has been initialized @@ -135,10 +135,10 @@ extern "C" * ****************************************************************************/ -bool stm32wb_rtc_is_initialized(void); +bool stm32_rtc_is_initialized(void); /**************************************************************************** - * Name: stm32wb_rtc_getdatetime_with_subseconds + * Name: stm32_rtc_getdatetime_with_subseconds * * Description: * Get the current date and time from the date/time RTC. This interface @@ -158,12 +158,12 @@ bool stm32wb_rtc_is_initialized(void); * ****************************************************************************/ -#ifdef CONFIG_STM32WB_HAVE_RTC_SUBSECONDS -int stm32wb_rtc_getdatetime_with_subseconds(struct tm *tp, long *nsec); +#ifdef CONFIG_STM32_HAVE_RTC_SUBSECONDS +int stm32_rtc_getdatetime_with_subseconds(struct tm *tp, long *nsec); #endif /**************************************************************************** - * Name: stm32wb_rtc_setdatetime + * Name: stm32_rtc_setdatetime * * Description: * Set the RTC to the provided time. RTC implementations which provide @@ -180,11 +180,11 @@ int stm32wb_rtc_getdatetime_with_subseconds(struct tm *tp, long *nsec); #ifdef CONFIG_RTC_DATETIME struct tm; -int stm32wb_rtc_setdatetime(const struct tm *tp); +int stm32_rtc_setdatetime(const struct tm *tp); #endif /**************************************************************************** - * Name: stm32wb_rtc_havesettime + * Name: stm32_rtc_havesettime * * Description: * Check if RTC time has been set. @@ -194,11 +194,11 @@ int stm32wb_rtc_setdatetime(const struct tm *tp); * ****************************************************************************/ -bool stm32wb_rtc_havesettime(void); +bool stm32_rtc_havesettime(void); #ifdef CONFIG_RTC_ALARM /**************************************************************************** - * Name: stm32wb_rtc_setalarm + * Name: stm32_rtc_setalarm * * Description: * Set an alarm to an absolute time using associated hardware. @@ -211,10 +211,10 @@ bool stm32wb_rtc_havesettime(void); * ****************************************************************************/ -int stm32wb_rtc_setalarm(struct alm_setalarm_s *alminfo); +int stm32_rtc_setalarm(struct alm_setalarm_s *alminfo); /**************************************************************************** - * Name: stm32wb_rtc_rdalarm + * Name: stm32_rtc_rdalarm * * Description: * Query an alarm configured in hardware. @@ -227,10 +227,10 @@ int stm32wb_rtc_setalarm(struct alm_setalarm_s *alminfo); * ****************************************************************************/ -int stm32wb_rtc_rdalarm(struct alm_rdalarm_s *alminfo); +int stm32_rtc_rdalarm(struct alm_rdalarm_s *alminfo); /**************************************************************************** - * Name: stm32wb_rtc_cancelalarm + * Name: stm32_rtc_cancelalarm * * Description: * Cancel an alarm. @@ -243,13 +243,13 @@ int stm32wb_rtc_rdalarm(struct alm_rdalarm_s *alminfo); * ****************************************************************************/ -int stm32wb_rtc_cancelalarm(enum alm_id_e alarmid); +int stm32_rtc_cancelalarm(enum alm_id_e alarmid); #endif /* CONFIG_RTC_ALARM */ #ifdef CONFIG_RTC_PERIODIC /**************************************************************************** - * Name: stm32wb_rtc_setperiodic + * Name: stm32_rtc_setperiodic * * Description: * Set a periodic RTC wakeup @@ -263,11 +263,11 @@ int stm32wb_rtc_cancelalarm(enum alm_id_e alarmid); * ****************************************************************************/ -int stm32wb_rtc_setperiodic(const struct timespec *period, +int stm32_rtc_setperiodic(const struct timespec *period, wakeupcb_t callback); /**************************************************************************** - * Name: stm32wb_rtc_cancelperiodic + * Name: stm32_rtc_cancelperiodic * * Description: * Cancel a periodic wakeup @@ -279,11 +279,11 @@ int stm32wb_rtc_setperiodic(const struct timespec *period, * ****************************************************************************/ -int stm32wb_rtc_cancelperiodic(void); +int stm32_rtc_cancelperiodic(void); #endif /* CONFIG_RTC_PERIODIC */ /**************************************************************************** - * Name: stm32wb_rtc_lowerhalf + * Name: stm32_rtc_lowerhalf * * Description: * Instantiate the RTC lower half driver for the STM32WB. General usage: @@ -292,7 +292,7 @@ int stm32wb_rtc_cancelperiodic(void); * #include "stm32wb_rtc.h> * * struct rtc_lowerhalf_s *lower; - * lower = stm32wb_rtc_lowerhalf(); + * lower = stm32_rtc_lowerhalf(); * rtc_initialize(0, lower); * * Input Parameters: @@ -306,7 +306,7 @@ int stm32wb_rtc_cancelperiodic(void); #ifdef CONFIG_RTC_DRIVER struct rtc_lowerhalf_s; -struct rtc_lowerhalf_s *stm32wb_rtc_lowerhalf(void); +struct rtc_lowerhalf_s *stm32_rtc_lowerhalf(void); #endif #undef EXTERN diff --git a/arch/arm/src/stm32wb/stm32wb_rtc_lowerhalf.c b/arch/arm/src/stm32wb/stm32wb_rtc_lowerhalf.c index 009ead5cea0c2..fca4009e4bf73 100644 --- a/arch/arm/src/stm32wb/stm32wb_rtc_lowerhalf.c +++ b/arch/arm/src/stm32wb/stm32wb_rtc_lowerhalf.c @@ -45,14 +45,14 @@ * Pre-processor Definitions ****************************************************************************/ -#define STM32WB_NALARMS 2 +#define STM32_NALARMS 2 /**************************************************************************** * Private Types ****************************************************************************/ #ifdef CONFIG_RTC_ALARM -struct stm32wb_cbinfo_s +struct stm32_cbinfo_s { volatile rtc_alarm_callback_t cb; /* Callback when the alarm expires */ volatile void *priv; /* Private argument for callback */ @@ -64,7 +64,7 @@ struct stm32wb_cbinfo_s * with struct rtc_lowerhalf_s. */ -struct stm32wb_lowerhalf_s +struct stm32_lowerhalf_s { /* This is the contained reference to the read-only, lower-half * operations vtable (which may lie in FLASH or ROM) @@ -81,7 +81,7 @@ struct stm32wb_lowerhalf_s #ifdef CONFIG_RTC_ALARM /* Alarm callback information */ - struct stm32wb_cbinfo_s cbinfo[STM32WB_NALARMS]; + struct stm32_cbinfo_s cbinfo[STM32_NALARMS]; #endif #ifdef CONFIG_RTC_PERIODIC @@ -97,29 +97,29 @@ struct stm32wb_lowerhalf_s /* Prototypes for static methods in struct rtc_ops_s */ -static int stm32wb_rdtime(struct rtc_lowerhalf_s *lower, +static int stm32_rdtime(struct rtc_lowerhalf_s *lower, struct rtc_time *rtctime); -static int stm32wb_settime(struct rtc_lowerhalf_s *lower, +static int stm32_settime(struct rtc_lowerhalf_s *lower, const struct rtc_time *rtctime); -static bool stm32wb_havesettime(struct rtc_lowerhalf_s *lower); +static bool stm32_havesettime(struct rtc_lowerhalf_s *lower); #ifdef CONFIG_RTC_ALARM -static int stm32wb_setalarm(struct rtc_lowerhalf_s *lower, +static int stm32_setalarm(struct rtc_lowerhalf_s *lower, const struct lower_setalarm_s *alarminfo); static int -stm32wb_setrelative(struct rtc_lowerhalf_s *lower, +stm32_setrelative(struct rtc_lowerhalf_s *lower, const struct lower_setrelative_s *alarminfo); -static int stm32wb_cancelalarm(struct rtc_lowerhalf_s *lower, int alarmid); -static int stm32wb_rdalarm(struct rtc_lowerhalf_s *lower, +static int stm32_cancelalarm(struct rtc_lowerhalf_s *lower, int alarmid); +static int stm32_rdalarm(struct rtc_lowerhalf_s *lower, struct lower_rdalarm_s *alarminfo); #endif #ifdef CONFIG_RTC_PERIODIC static int -stm32wb_setperiodic(struct rtc_lowerhalf_s *lower, +stm32_setperiodic(struct rtc_lowerhalf_s *lower, const struct lower_setperiodic_s *alarminfo); static int -stm32wb_cancelperiodic(struct rtc_lowerhalf_s *lower, int id); +stm32_cancelperiodic(struct rtc_lowerhalf_s *lower, int id); #endif /**************************************************************************** @@ -130,24 +130,24 @@ stm32wb_cancelperiodic(struct rtc_lowerhalf_s *lower, int id); static const struct rtc_ops_s g_rtc_ops = { - .rdtime = stm32wb_rdtime, - .settime = stm32wb_settime, - .havesettime = stm32wb_havesettime, + .rdtime = stm32_rdtime, + .settime = stm32_settime, + .havesettime = stm32_havesettime, #ifdef CONFIG_RTC_ALARM - .setalarm = stm32wb_setalarm, - .setrelative = stm32wb_setrelative, - .cancelalarm = stm32wb_cancelalarm, - .rdalarm = stm32wb_rdalarm, + .setalarm = stm32_setalarm, + .setrelative = stm32_setrelative, + .cancelalarm = stm32_cancelalarm, + .rdalarm = stm32_rdalarm, #endif #ifdef CONFIG_RTC_PERIODIC - .setperiodic = stm32wb_setperiodic, - .cancelperiodic = stm32wb_cancelperiodic, + .setperiodic = stm32_setperiodic, + .cancelperiodic = stm32_cancelperiodic, #endif }; /* STM32WB RTC device state */ -static struct stm32wb_lowerhalf_s g_rtc_lowerhalf = +static struct stm32_lowerhalf_s g_rtc_lowerhalf = { .ops = &g_rtc_ops, .devlock = NXMUTEX_INITIALIZER, @@ -158,7 +158,7 @@ static struct stm32wb_lowerhalf_s g_rtc_lowerhalf = ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_alarm_callback + * Name: stm32_alarm_callback * * Description: * This is the function that is called from the RTC driver when the alarm @@ -173,17 +173,17 @@ static struct stm32wb_lowerhalf_s g_rtc_lowerhalf = ****************************************************************************/ #ifdef CONFIG_RTC_ALARM -static void stm32wb_alarm_callback(void *arg, unsigned int alarmid) +static void stm32_alarm_callback(void *arg, unsigned int alarmid) { - struct stm32wb_lowerhalf_s *lower; - struct stm32wb_cbinfo_s *cbinfo; + struct stm32_lowerhalf_s *lower; + struct stm32_cbinfo_s *cbinfo; rtc_alarm_callback_t cb; void *priv; DEBUGASSERT(arg != NULL); DEBUGASSERT(alarmid == RTC_ALARMA || alarmid == RTC_ALARMB); - lower = (struct stm32wb_lowerhalf_s *)arg; + lower = (struct stm32_lowerhalf_s *)arg; cbinfo = &lower->cbinfo[alarmid]; /* Sample and clear the callback information to minimize the window in @@ -206,7 +206,7 @@ static void stm32wb_alarm_callback(void *arg, unsigned int alarmid) #endif /* CONFIG_RTC_ALARM */ /**************************************************************************** - * Name: stm32wb_rdtime + * Name: stm32_rdtime * * Description: * Implements the rdtime() method of the RTC driver interface @@ -221,13 +221,13 @@ static void stm32wb_alarm_callback(void *arg, unsigned int alarmid) * ****************************************************************************/ -static int stm32wb_rdtime(struct rtc_lowerhalf_s *lower, +static int stm32_rdtime(struct rtc_lowerhalf_s *lower, struct rtc_time *rtctime) { - struct stm32wb_lowerhalf_s *priv; + struct stm32_lowerhalf_s *priv; int ret; - priv = (struct stm32wb_lowerhalf_s *)lower; + priv = (struct stm32_lowerhalf_s *)lower; ret = nxmutex_lock(&priv->devlock); if (ret < 0) @@ -246,7 +246,7 @@ static int stm32wb_rdtime(struct rtc_lowerhalf_s *lower, } /**************************************************************************** - * Name: stm32wb_settime + * Name: stm32_settime * * Description: * Implements the settime() method of the RTC driver interface @@ -261,13 +261,13 @@ static int stm32wb_rdtime(struct rtc_lowerhalf_s *lower, * ****************************************************************************/ -static int stm32wb_settime(struct rtc_lowerhalf_s *lower, +static int stm32_settime(struct rtc_lowerhalf_s *lower, const struct rtc_time *rtctime) { - struct stm32wb_lowerhalf_s *priv; + struct stm32_lowerhalf_s *priv; int ret; - priv = (struct stm32wb_lowerhalf_s *)lower; + priv = (struct stm32_lowerhalf_s *)lower; ret = nxmutex_lock(&priv->devlock); if (ret < 0) @@ -279,14 +279,14 @@ static int stm32wb_settime(struct rtc_lowerhalf_s *lower, * compatible with struct tm. */ - ret = stm32wb_rtc_setdatetime((const struct tm *)rtctime); + ret = stm32_rtc_setdatetime((const struct tm *)rtctime); nxmutex_unlock(&priv->devlock); return ret; } /**************************************************************************** - * Name: stm32wb_havesettime + * Name: stm32_havesettime * * Description: * Implements the havesettime() method of the RTC driver interface @@ -299,13 +299,13 @@ static int stm32wb_settime(struct rtc_lowerhalf_s *lower, * ****************************************************************************/ -static bool stm32wb_havesettime(struct rtc_lowerhalf_s *lower) +static bool stm32_havesettime(struct rtc_lowerhalf_s *lower) { - return stm32wb_rtc_havesettime(); + return stm32_rtc_havesettime(); } /**************************************************************************** - * Name: stm32wb_setalarm + * Name: stm32_setalarm * * Description: * Set a new alarm. This function implements the setalarm() method of the @@ -322,11 +322,11 @@ static bool stm32wb_havesettime(struct rtc_lowerhalf_s *lower) ****************************************************************************/ #ifdef CONFIG_RTC_ALARM -static int stm32wb_setalarm(struct rtc_lowerhalf_s *lower, +static int stm32_setalarm(struct rtc_lowerhalf_s *lower, const struct lower_setalarm_s *alarminfo) { - struct stm32wb_lowerhalf_s *priv; - struct stm32wb_cbinfo_s *cbinfo; + struct stm32_lowerhalf_s *priv; + struct stm32_cbinfo_s *cbinfo; struct alm_setalarm_s lowerinfo; int ret; @@ -334,7 +334,7 @@ static int stm32wb_setalarm(struct rtc_lowerhalf_s *lower, DEBUGASSERT(lower != NULL && alarminfo != NULL); DEBUGASSERT(alarminfo->id == RTC_ALARMA || alarminfo->id == RTC_ALARMB); - priv = (struct stm32wb_lowerhalf_s *)lower; + priv = (struct stm32_lowerhalf_s *)lower; ret = nxmutex_lock(&priv->devlock); if (ret < 0) @@ -355,13 +355,13 @@ static int stm32wb_setalarm(struct rtc_lowerhalf_s *lower, /* Set the alarm */ lowerinfo.as_id = alarminfo->id; - lowerinfo.as_cb = stm32wb_alarm_callback; + lowerinfo.as_cb = stm32_alarm_callback; lowerinfo.as_arg = priv; memcpy(&lowerinfo.as_time, &alarminfo->time, sizeof(struct tm)); /* And set the alarm */ - ret = stm32wb_rtc_setalarm(&lowerinfo); + ret = stm32_rtc_setalarm(&lowerinfo); if (ret < 0) { cbinfo->cb = NULL; @@ -375,7 +375,7 @@ static int stm32wb_setalarm(struct rtc_lowerhalf_s *lower, #endif /**************************************************************************** - * Name: stm32wb_setrelative + * Name: stm32_setrelative * * Description: * Set a new alarm relative to the current time. This function implements @@ -393,7 +393,7 @@ static int stm32wb_setalarm(struct rtc_lowerhalf_s *lower, #ifdef CONFIG_RTC_ALARM static int -stm32wb_setrelative(struct rtc_lowerhalf_s *lower, +stm32_setrelative(struct rtc_lowerhalf_s *lower, const struct lower_setrelative_s *alarminfo) { struct lower_setalarm_s setalarm; @@ -439,7 +439,7 @@ stm32wb_setrelative(struct rtc_lowerhalf_s *lower, setalarm.cb = alarminfo->cb; setalarm.priv = alarminfo->priv; - ret = stm32wb_setalarm(lower, &setalarm); + ret = stm32_setalarm(lower, &setalarm); } leave_critical_section(flags); @@ -450,7 +450,7 @@ stm32wb_setrelative(struct rtc_lowerhalf_s *lower, #endif /**************************************************************************** - * Name: stm32wb_cancelalarm + * Name: stm32_cancelalarm * * Description: * Cancel the current alarm. This function implements the cancelalarm() @@ -467,15 +467,15 @@ stm32wb_setrelative(struct rtc_lowerhalf_s *lower, ****************************************************************************/ #ifdef CONFIG_RTC_ALARM -static int stm32wb_cancelalarm(struct rtc_lowerhalf_s *lower, int alarmid) +static int stm32_cancelalarm(struct rtc_lowerhalf_s *lower, int alarmid) { - struct stm32wb_lowerhalf_s *priv; - struct stm32wb_cbinfo_s *cbinfo; + struct stm32_lowerhalf_s *priv; + struct stm32_cbinfo_s *cbinfo; int ret; DEBUGASSERT(lower != NULL); DEBUGASSERT(alarmid == RTC_ALARMA || alarmid == RTC_ALARMB); - priv = (struct stm32wb_lowerhalf_s *)lower; + priv = (struct stm32_lowerhalf_s *)lower; ret = nxmutex_lock(&priv->devlock); if (ret < 0) @@ -496,7 +496,7 @@ static int stm32wb_cancelalarm(struct rtc_lowerhalf_s *lower, int alarmid) /* Then cancel the alarm */ - ret = stm32wb_rtc_cancelalarm((enum alm_id_e)alarmid); + ret = stm32_rtc_cancelalarm((enum alm_id_e)alarmid); } nxmutex_unlock(&priv->devlock); @@ -505,7 +505,7 @@ static int stm32wb_cancelalarm(struct rtc_lowerhalf_s *lower, int alarmid) #endif /**************************************************************************** - * Name: stm32wb_rdalarm + * Name: stm32_rdalarm * * Description: * Query the RTC alarm. @@ -521,7 +521,7 @@ static int stm32wb_cancelalarm(struct rtc_lowerhalf_s *lower, int alarmid) ****************************************************************************/ #ifdef CONFIG_RTC_ALARM -static int stm32wb_rdalarm(struct rtc_lowerhalf_s *lower, +static int stm32_rdalarm(struct rtc_lowerhalf_s *lower, struct lower_rdalarm_s *alarminfo) { struct alm_rdalarm_s lowerinfo; @@ -542,7 +542,7 @@ static int stm32wb_rdalarm(struct rtc_lowerhalf_s *lower, lowerinfo.ar_id = alarminfo->id; lowerinfo.ar_time = alarminfo->time; - ret = stm32wb_rtc_rdalarm(&lowerinfo); + ret = stm32_rtc_rdalarm(&lowerinfo); leave_critical_section(flags); } @@ -552,7 +552,7 @@ static int stm32wb_rdalarm(struct rtc_lowerhalf_s *lower, #endif /**************************************************************************** - * Name: stm32wb_periodic_callback + * Name: stm32_periodic_callback * * Description: * This is the function that is called from the RTC driver when the @@ -568,14 +568,14 @@ static int stm32wb_rdalarm(struct rtc_lowerhalf_s *lower, ****************************************************************************/ #ifdef CONFIG_RTC_PERIODIC -static int stm32wb_periodic_callback(void) +static int stm32_periodic_callback(void) { - struct stm32wb_lowerhalf_s *lower; + struct stm32_lowerhalf_s *lower; struct lower_setperiodic_s *cbinfo; rtc_wakeup_callback_t cb; void *priv; - lower = (struct stm32wb_lowerhalf_s *)&g_rtc_lowerhalf; + lower = (struct stm32_lowerhalf_s *)&g_rtc_lowerhalf; cbinfo = &lower->periodic; cb = (rtc_wakeup_callback_t)cbinfo->cb; @@ -593,7 +593,7 @@ static int stm32wb_periodic_callback(void) #endif /* CONFIG_RTC_PERIODIC */ /**************************************************************************** - * Name: stm32wb_setperiodic + * Name: stm32_setperiodic * * Description: * Set a new periodic wakeup relative to the current time, with a given @@ -612,14 +612,14 @@ static int stm32wb_periodic_callback(void) #ifdef CONFIG_RTC_PERIODIC static int -stm32wb_setperiodic(struct rtc_lowerhalf_s *lower, +stm32_setperiodic(struct rtc_lowerhalf_s *lower, const struct lower_setperiodic_s *alarminfo) { - struct stm32wb_lowerhalf_s *priv; + struct stm32_lowerhalf_s *priv; int ret; DEBUGASSERT(lower != NULL && alarminfo != NULL); - priv = (struct stm32wb_lowerhalf_s *)lower; + priv = (struct stm32_lowerhalf_s *)lower; ret = nxmutex_lock(&priv->devlock); if (ret < 0) @@ -628,8 +628,8 @@ stm32wb_setperiodic(struct rtc_lowerhalf_s *lower, } memcpy(&priv->periodic, alarminfo, sizeof(struct lower_setperiodic_s)); - ret = stm32wb_rtc_setperiodic(&alarminfo->period, - stm32wb_periodic_callback); + ret = stm32_rtc_setperiodic(&alarminfo->period, + stm32_periodic_callback); nxmutex_unlock(&priv->devlock); return ret; @@ -637,7 +637,7 @@ stm32wb_setperiodic(struct rtc_lowerhalf_s *lower, #endif /**************************************************************************** - * Name: stm32wb_cancelperiodic + * Name: stm32_cancelperiodic * * Description: * Cancel the current periodic wakeup activity. This function implements @@ -653,13 +653,13 @@ stm32wb_setperiodic(struct rtc_lowerhalf_s *lower, ****************************************************************************/ #ifdef CONFIG_RTC_PERIODIC -static int stm32wb_cancelperiodic(struct rtc_lowerhalf_s *lower, int id) +static int stm32_cancelperiodic(struct rtc_lowerhalf_s *lower, int id) { - struct stm32wb_lowerhalf_s *priv; + struct stm32_lowerhalf_s *priv; int ret; DEBUGASSERT(lower != NULL); - priv = (struct stm32wb_lowerhalf_s *)lower; + priv = (struct stm32_lowerhalf_s *)lower; DEBUGASSERT(id == 0); @@ -669,7 +669,7 @@ static int stm32wb_cancelperiodic(struct rtc_lowerhalf_s *lower, int id) return ret; } - ret = stm32wb_rtc_cancelperiodic(); + ret = stm32_rtc_cancelperiodic(); nxmutex_unlock(&priv->devlock); return ret; @@ -681,7 +681,7 @@ static int stm32wb_cancelperiodic(struct rtc_lowerhalf_s *lower, int id) ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_rtc_lowerhalf + * Name: stm32_rtc_lowerhalf * * Description: * Instantiate the RTC lower half driver for the STM32. General usage: @@ -690,7 +690,7 @@ static int stm32wb_cancelperiodic(struct rtc_lowerhalf_s *lower, int id) * #include "stm32wb_rtc.h> * * struct rtc_lowerhalf_s *lower; - * lower = stm32wb_rtc_lowerhalf(); + * lower = stm32_rtc_lowerhalf(); * rtc_initialize(0, lower); * * Input Parameters: @@ -702,7 +702,7 @@ static int stm32wb_cancelperiodic(struct rtc_lowerhalf_s *lower, int id) * ****************************************************************************/ -struct rtc_lowerhalf_s *stm32wb_rtc_lowerhalf(void) +struct rtc_lowerhalf_s *stm32_rtc_lowerhalf(void) { return (struct rtc_lowerhalf_s *)&g_rtc_lowerhalf; } diff --git a/arch/arm/src/stm32wb/stm32wb_serial.c b/arch/arm/src/stm32wb/stm32wb_serial.c index e657d7435de58..a67006f7cf9b2 100644 --- a/arch/arm/src/stm32wb/stm32wb_serial.c +++ b/arch/arm/src/stm32wb/stm32wb_serial.c @@ -87,11 +87,11 @@ * The buffer size should be an even multiple of ARMV7M_DCACHE_LINESIZE. */ -# if !defined(CONFIG_STM32WB_SERIAL_RXDMA_BUFFER_SIZE) || \ - CONFIG_STM32WB_SERIAL_RXDMA_BUFFER_SIZE == 0 +# if !defined(CONFIG_STM32_SERIAL_RXDMA_BUFFER_SIZE) || \ + CONFIG_STM32_SERIAL_RXDMA_BUFFER_SIZE == 0 # define RXDMA_BUFFER_SIZE 32 # else -# define RXDMA_BUFFER_SIZE ((CONFIG_STM32WB_SERIAL_RXDMA_BUFFER_SIZE + 31) & ~31) +# define RXDMA_BUFFER_SIZE ((CONFIG_STM32_SERIAL_RXDMA_BUFFER_SIZE + 31) & ~31) # endif /* DMA priority */ @@ -123,8 +123,8 @@ /* Power management definitions */ -#if defined(CONFIG_PM) && !defined(CONFIG_STM32WB_PM_SERIAL_ACTIVITY) -# define CONFIG_STM32WB_PM_SERIAL_ACTIVITY 10 +#if defined(CONFIG_PM) && !defined(CONFIG_STM32_PM_SERIAL_ACTIVITY) +# define CONFIG_STM32_PM_SERIAL_ACTIVITY 10 #endif #if defined(CONFIG_PM) # define PM_IDLE_DOMAIN 0 /* Revisit */ @@ -138,10 +138,10 @@ * register. It must not collide with USART_CR1_USED_INTS or USART_CR3_EIE * 2) USART_CR3_EIE is also carried in the up_dev_s ie member. * - * See stm32wb_serial_restoreusartint where the masking is done. + * See stm32_serial_restoreusartint where the masking is done. */ -#ifdef CONFIG_STM32WB_SERIALBRK_BSDCOMPAT +#ifdef CONFIG_STM32_SERIALBRK_BSDCOMPAT # define USART_CR1_IE_BREAK_INPROGRESS_SHFTS 15 # define USART_CR1_IE_BREAK_INPROGRESS (1 << USART_CR1_IE_BREAK_INPROGRESS_SHFTS) #endif @@ -153,7 +153,7 @@ * Private Types ****************************************************************************/ -struct stm32wb_serial_s +struct stm32_serial_s { struct uart_dev_s dev; /* Generic UART device */ uint16_t ie; /* Saved interrupt mask bits value */ @@ -239,51 +239,51 @@ struct stm32wb_serial_s ****************************************************************************/ #ifndef CONFIG_SUPPRESS_UART_CONFIG -static void stm32wb_serial_setformat(struct uart_dev_s *dev); +static void stm32_serial_setformat(struct uart_dev_s *dev); #endif -static int stm32wb_serial_setup(struct uart_dev_s *dev); -static void stm32wb_serial_shutdown(struct uart_dev_s *dev); -static int stm32wb_serial_attach(struct uart_dev_s *dev); -static void stm32wb_serial_detach(struct uart_dev_s *dev); +static int stm32_serial_setup(struct uart_dev_s *dev); +static void stm32_serial_shutdown(struct uart_dev_s *dev); +static int stm32_serial_attach(struct uart_dev_s *dev); +static void stm32_serial_detach(struct uart_dev_s *dev); static int up_interrupt(int irq, void *context, void *arg); -static int stm32wb_serial_ioctl(struct file *filep, int cmd, +static int stm32_serial_ioctl(struct file *filep, int cmd, unsigned long arg); #ifndef SERIAL_HAVE_ONLY_DMA -static int stm32wb_serial_receive(struct uart_dev_s *dev, +static int stm32_serial_receive(struct uart_dev_s *dev, unsigned int *status); -static void stm32wb_serial_rxint(struct uart_dev_s *dev, bool enable); -static bool stm32wb_serial_rxavailable(struct uart_dev_s *dev); +static void stm32_serial_rxint(struct uart_dev_s *dev, bool enable); +static bool stm32_serial_rxavailable(struct uart_dev_s *dev); #endif #ifdef CONFIG_SERIAL_IFLOWCONTROL -static bool stm32wb_serial_rxflowcontrol(struct uart_dev_s *dev, +static bool stm32_serial_rxflowcontrol(struct uart_dev_s *dev, unsigned int nbuffered, bool upper); #endif -static void stm32wb_serial_send(struct uart_dev_s *dev, int ch); -static void stm32wb_serial_txint(struct uart_dev_s *dev, bool enable); -static bool stm32wb_serial_txready(struct uart_dev_s *dev); +static void stm32_serial_send(struct uart_dev_s *dev, int ch); +static void stm32_serial_txint(struct uart_dev_s *dev, bool enable); +static bool stm32_serial_txready(struct uart_dev_s *dev); #ifdef SERIAL_HAVE_RXDMA -static int stm32wb_serial_dmasetup(struct uart_dev_s *dev); -static void stm32wb_serial_dmashutdown(struct uart_dev_s *dev); -static int stm32wb_serial_dmareceive(struct uart_dev_s *dev, +static int stm32_serial_dmasetup(struct uart_dev_s *dev); +static void stm32_serial_dmashutdown(struct uart_dev_s *dev); +static int stm32_serial_dmareceive(struct uart_dev_s *dev, unsigned int *status); -static void stm32wb_serial_dmareenable(struct stm32wb_serial_s *priv); +static void stm32_serial_dmareenable(struct stm32_serial_s *priv); #ifdef CONFIG_SERIAL_IFLOWCONTROL -static bool stm32wb_serial_dmaiflowrestart(struct stm32wb_serial_s *priv); +static bool stm32_serial_dmaiflowrestart(struct stm32_serial_s *priv); #endif -static void stm32wb_serial_dmarxint(struct uart_dev_s *dev, bool enable); -static bool stm32wb_serial_dmarxavailable(struct uart_dev_s *dev); +static void stm32_serial_dmarxint(struct uart_dev_s *dev, bool enable); +static bool stm32_serial_dmarxavailable(struct uart_dev_s *dev); -static void stm32wb_serial_dmarxcallback(DMA_HANDLE handle, uint8_t status, +static void stm32_serial_dmarxcallback(DMA_HANDLE handle, uint8_t status, void *arg); #endif #ifdef CONFIG_PM -static void stm32wb_serial_setsuspend(struct uart_dev_s *dev, bool suspend); -static void stm32wb_serial_pm_setsuspend(bool suspend); -static void stm32wb_serial_pmnotify(struct pm_callback_s *cb, +static void stm32_serial_setsuspend(struct uart_dev_s *dev, bool suspend); +static void stm32_serial_pm_setsuspend(bool suspend); +static void stm32_serial_pmnotify(struct pm_callback_s *cb, int domain, enum pm_state_e pmstate); -static int stm32wb_serial_pmprepare(struct pm_callback_s *cb, +static int stm32_serial_pmprepare(struct pm_callback_s *cb, int domain, enum pm_state_e pmstate); #endif @@ -294,48 +294,48 @@ static int stm32wb_serial_pmprepare(struct pm_callback_s *cb, #ifndef SERIAL_HAVE_ONLY_DMA static const struct uart_ops_s g_uart_ops = { - .setup = stm32wb_serial_setup, - .shutdown = stm32wb_serial_shutdown, - .attach = stm32wb_serial_attach, - .detach = stm32wb_serial_detach, - .ioctl = stm32wb_serial_ioctl, - .receive = stm32wb_serial_receive, - .rxint = stm32wb_serial_rxint, - .rxavailable = stm32wb_serial_rxavailable, + .setup = stm32_serial_setup, + .shutdown = stm32_serial_shutdown, + .attach = stm32_serial_attach, + .detach = stm32_serial_detach, + .ioctl = stm32_serial_ioctl, + .receive = stm32_serial_receive, + .rxint = stm32_serial_rxint, + .rxavailable = stm32_serial_rxavailable, #ifdef CONFIG_SERIAL_IFLOWCONTROL - .rxflowcontrol = stm32wb_serial_rxflowcontrol, + .rxflowcontrol = stm32_serial_rxflowcontrol, #endif - .send = stm32wb_serial_send, - .txint = stm32wb_serial_txint, - .txready = stm32wb_serial_txready, - .txempty = stm32wb_serial_txready, + .send = stm32_serial_send, + .txint = stm32_serial_txint, + .txready = stm32_serial_txready, + .txempty = stm32_serial_txready, }; #endif #ifdef SERIAL_HAVE_RXDMA static const struct uart_ops_s g_uart_dma_ops = { - .setup = stm32wb_serial_dmasetup, - .shutdown = stm32wb_serial_dmashutdown, - .attach = stm32wb_serial_attach, - .detach = stm32wb_serial_detach, - .ioctl = stm32wb_serial_ioctl, - .receive = stm32wb_serial_dmareceive, - .rxint = stm32wb_serial_dmarxint, - .rxavailable = stm32wb_serial_dmarxavailable, + .setup = stm32_serial_dmasetup, + .shutdown = stm32_serial_dmashutdown, + .attach = stm32_serial_attach, + .detach = stm32_serial_detach, + .ioctl = stm32_serial_ioctl, + .receive = stm32_serial_dmareceive, + .rxint = stm32_serial_dmarxint, + .rxavailable = stm32_serial_dmarxavailable, #ifdef CONFIG_SERIAL_IFLOWCONTROL - .rxflowcontrol = stm32wb_serial_rxflowcontrol, + .rxflowcontrol = stm32_serial_rxflowcontrol, #endif - .send = stm32wb_serial_send, - .txint = stm32wb_serial_txint, - .txready = stm32wb_serial_txready, - .txempty = stm32wb_serial_txready, + .send = stm32_serial_send, + .txint = stm32_serial_txint, + .txready = stm32_serial_txready, + .txempty = stm32_serial_txready, }; #endif /* I/O buffers */ -#ifdef CONFIG_STM32WB_LPUART1_SERIALDRIVER +#ifdef CONFIG_STM32_LPUART1_SERIALDRIVER static char g_lpuart1rxbuffer[CONFIG_LPUART1_RXBUFSIZE]; static char g_lpuart1txbuffer[CONFIG_LPUART1_TXBUFSIZE]; # ifdef CONFIG_LPUART1_RXDMA @@ -343,7 +343,7 @@ static char g_lpuart1rxfifo[RXDMA_BUFFER_SIZE]; # endif #endif -#ifdef CONFIG_STM32WB_USART1_SERIALDRIVER +#ifdef CONFIG_STM32_USART1_SERIALDRIVER static char g_usart1rxbuffer[CONFIG_USART1_RXBUFSIZE]; static char g_usart1txbuffer[CONFIG_USART1_TXBUFSIZE]; # ifdef CONFIG_USART1_RXDMA @@ -353,8 +353,8 @@ static char g_usart1rxfifo[RXDMA_BUFFER_SIZE]; /* This describes the state of the STM32WB LPUART1 port. */ -#ifdef CONFIG_STM32WB_LPUART1_SERIALDRIVER -static struct stm32wb_serial_s g_lpuart1priv = +#ifdef CONFIG_STM32_LPUART1_SERIALDRIVER +static struct stm32_serial_s g_lpuart1priv = { .dev = { @@ -379,13 +379,13 @@ static struct stm32wb_serial_s g_lpuart1priv = .priv = &g_lpuart1priv, }, - .irq = STM32WB_IRQ_LPUART1, + .irq = STM32_IRQ_LPUART1, .parity = CONFIG_LPUART1_PARITY, .bits = CONFIG_LPUART1_BITS, .stopbits2 = CONFIG_LPUART1_2STOP, .baud = CONFIG_LPUART1_BAUD, - .apbclock = STM32WB_PCLK1_FREQUENCY, - .usartbase = STM32WB_LPUART1_BASE, + .apbclock = STM32_PCLK1_FREQUENCY, + .usartbase = STM32_LPUART1_BASE, .tx_gpio = GPIO_LPUART1_TX, .rx_gpio = GPIO_LPUART1_RX, #if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_LPUART1_OFLOWCONTROL) @@ -415,8 +415,8 @@ static struct stm32wb_serial_s g_lpuart1priv = /* This describes the state of the STM32WB USART1 port. */ -#ifdef CONFIG_STM32WB_USART1_SERIALDRIVER -static struct stm32wb_serial_s g_usart1priv = +#ifdef CONFIG_STM32_USART1_SERIALDRIVER +static struct stm32_serial_s g_usart1priv = { .dev = { @@ -441,13 +441,13 @@ static struct stm32wb_serial_s g_usart1priv = .priv = &g_usart1priv, }, - .irq = STM32WB_IRQ_USART1, + .irq = STM32_IRQ_USART1, .parity = CONFIG_USART1_PARITY, .bits = CONFIG_USART1_BITS, .stopbits2 = CONFIG_USART1_2STOP, .baud = CONFIG_USART1_BAUD, - .apbclock = STM32WB_PCLK2_FREQUENCY, - .usartbase = STM32WB_USART1_BASE, + .apbclock = STM32_PCLK2_FREQUENCY, + .usartbase = STM32_USART1_BASE, .tx_gpio = GPIO_USART1_TX, .rx_gpio = GPIO_USART1_RX, #if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_USART1_OFLOWCONTROL) @@ -477,13 +477,13 @@ static struct stm32wb_serial_s g_usart1priv = /* This table lets us iterate over the configured USARTs */ -static struct stm32wb_serial_s * -const g_uart_devs[STM32WB_NLPUART + STM32WB_NUSART] = +static struct stm32_serial_s * +const g_uart_devs[STM32_NLPUART + STM32_NUSART] = { -#ifdef CONFIG_STM32WB_LPUART1_SERIALDRIVER +#ifdef CONFIG_STM32_LPUART1_SERIALDRIVER [0] = &g_lpuart1priv, #endif -#ifdef CONFIG_STM32WB_USART1_SERIALDRIVER +#ifdef CONFIG_STM32_USART1_SERIALDRIVER [1] = &g_usart1priv, #endif }; @@ -495,8 +495,8 @@ static struct bool serial_suspended; } g_serialpm = { - .pm_cb.notify = stm32wb_serial_pmnotify, - .pm_cb.prepare = stm32wb_serial_pmprepare, + .pm_cb.notify = stm32_serial_pmnotify, + .pm_cb.prepare = stm32_serial_pmprepare, .serial_suspended = false }; #endif @@ -506,31 +506,31 @@ static struct ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_serial_getreg + * Name: stm32_serial_getreg ****************************************************************************/ static inline -uint32_t stm32wb_serial_getreg(struct stm32wb_serial_s *priv, int offset) +uint32_t stm32_serial_getreg(struct stm32_serial_s *priv, int offset) { return getreg32(priv->usartbase + offset); } /**************************************************************************** - * Name: stm32wb_serial_putreg + * Name: stm32_serial_putreg ****************************************************************************/ -static inline void stm32wb_serial_putreg(struct stm32wb_serial_s *priv, +static inline void stm32_serial_putreg(struct stm32_serial_s *priv, int offset, uint32_t value) { putreg32(value, priv->usartbase + offset); } /**************************************************************************** - * Name: stm32wb_serial_setusartint + * Name: stm32_serial_setusartint ****************************************************************************/ static inline -void stm32wb_serial_setusartint(struct stm32wb_serial_s *priv, uint16_t ie) +void stm32_serial_setusartint(struct stm32_serial_s *priv, uint16_t ie) { uint32_t cr; @@ -542,38 +542,38 @@ void stm32wb_serial_setusartint(struct stm32wb_serial_s *priv, uint16_t ie) * enable/usage table above) */ - cr = stm32wb_serial_getreg(priv, STM32WB_USART_CR1_OFFSET); + cr = stm32_serial_getreg(priv, STM32_USART_CR1_OFFSET); cr &= ~(USART_CR1_USED_INTS); cr |= (ie & (USART_CR1_USED_INTS)); - stm32wb_serial_putreg(priv, STM32WB_USART_CR1_OFFSET, cr); + stm32_serial_putreg(priv, STM32_USART_CR1_OFFSET, cr); - cr = stm32wb_serial_getreg(priv, STM32WB_USART_CR3_OFFSET); + cr = stm32_serial_getreg(priv, STM32_USART_CR3_OFFSET); cr &= ~USART_CR3_EIE; cr |= (ie & USART_CR3_EIE); - stm32wb_serial_putreg(priv, STM32WB_USART_CR3_OFFSET, cr); + stm32_serial_putreg(priv, STM32_USART_CR3_OFFSET, cr); } /**************************************************************************** * Name: up_restoreusartint ****************************************************************************/ -static void stm32wb_serial_restoreusartint(struct stm32wb_serial_s *priv, +static void stm32_serial_restoreusartint(struct stm32_serial_s *priv, uint16_t ie) { irqstate_t flags; flags = spin_lock_irqsave(&priv->lock); - stm32wb_serial_setusartint(priv, ie); + stm32_serial_setusartint(priv, ie); spin_unlock_irqrestore(&priv->lock, flags); } /**************************************************************************** - * Name: stm32wb_serial_disableusartint + * Name: stm32_serial_disableusartint ****************************************************************************/ -static void stm32wb_serial_disableusartint(struct stm32wb_serial_s *priv, +static void stm32_serial_disableusartint(struct stm32_serial_s *priv, uint16_t *ie) { irqstate_t flags; @@ -610,8 +610,8 @@ static void stm32wb_serial_disableusartint(struct stm32wb_serial_s *priv, * USART_CR3_CTSIE USART_ISR_CTS CTS flag (not used) */ - cr1 = stm32wb_serial_getreg(priv, STM32WB_USART_CR1_OFFSET); - cr3 = stm32wb_serial_getreg(priv, STM32WB_USART_CR3_OFFSET); + cr1 = stm32_serial_getreg(priv, STM32_USART_CR1_OFFSET); + cr3 = stm32_serial_getreg(priv, STM32_USART_CR3_OFFSET); /* Return the current interrupt mask value for the used interrupts. * Notice that this depends on the fact that none of the used interrupt @@ -624,13 +624,13 @@ static void stm32wb_serial_disableusartint(struct stm32wb_serial_s *priv, /* Disable all interrupts */ - stm32wb_serial_setusartint(priv, 0); + stm32_serial_setusartint(priv, 0); spin_unlock_irqrestore(&priv->lock, flags); } /**************************************************************************** - * Name: stm32wb_serial_dmanextrx + * Name: stm32_serial_dmanextrx * * Description: * Returns the index into the RX FIFO where the DMA will place the next @@ -639,18 +639,18 @@ static void stm32wb_serial_disableusartint(struct stm32wb_serial_s *priv, ****************************************************************************/ #ifdef SERIAL_HAVE_RXDMA -static int stm32wb_serial_dmanextrx(struct stm32wb_serial_s *priv) +static int stm32_serial_dmanextrx(struct stm32_serial_s *priv) { size_t dmaresidual; - dmaresidual = stm32wb_dmaresidual(priv->rxdma); + dmaresidual = stm32_dmaresidual(priv->rxdma); return (RXDMA_BUFFER_SIZE - (int)dmaresidual); } #endif /**************************************************************************** - * Name: stm32wb_serial_setbaud_usart + * Name: stm32_serial_setbaud_usart * * Description: * Set the serial line baud rate (USART only). @@ -658,7 +658,7 @@ static int stm32wb_serial_dmanextrx(struct stm32wb_serial_s *priv) ****************************************************************************/ #ifndef CONFIG_SUPPRESS_UART_CONFIG -static void stm32wb_serial_setbaud_usart(struct stm32wb_serial_s *priv) +static void stm32_serial_setbaud_usart(struct stm32_serial_s *priv) { /* This first implementation is for U[S]ARTs that support oversampling * by 8 in additional to the standard oversampling by 16. @@ -686,8 +686,8 @@ static void stm32wb_serial_setbaud_usart(struct stm32wb_serial_s *priv) /* Use oversamply by 8 only if the divisor is small. But what is small? */ - cr1 = stm32wb_serial_getreg(priv, STM32WB_USART_CR1_OFFSET); - brr = stm32wb_serial_getreg(priv, STM32WB_USART_BRR_OFFSET); + cr1 = stm32_serial_getreg(priv, STM32_USART_CR1_OFFSET); + brr = stm32_serial_getreg(priv, STM32_USART_BRR_OFFSET); brr &= ~(USART_BRR_MANT_MASK | USART_BRR_FRAC_MASK); if (usartdiv8 > 100) @@ -713,13 +713,13 @@ static void stm32wb_serial_setbaud_usart(struct stm32wb_serial_s *priv) cr1 |= USART_CR1_OVER8; } - stm32wb_serial_putreg(priv, STM32WB_USART_CR1_OFFSET, cr1); - stm32wb_serial_putreg(priv, STM32WB_USART_BRR_OFFSET, brr); + stm32_serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1); + stm32_serial_putreg(priv, STM32_USART_BRR_OFFSET, brr); } #endif /**************************************************************************** - * Name: stm32wb_serial_setbaud_lpuart + * Name: stm32_serial_setbaud_lpuart * * Description: * Set the serial line baud rate (LPUART only). @@ -727,8 +727,8 @@ static void stm32wb_serial_setbaud_usart(struct stm32wb_serial_s *priv) ****************************************************************************/ #ifndef CONFIG_SUPPRESS_UART_CONFIG -#ifdef CONFIG_STM32WB_LPUART1_SERIALDRIVER -static void stm32wb_serial_setbaud_lpuart(struct stm32wb_serial_s *priv) +#ifdef CONFIG_STM32_LPUART1_SERIALDRIVER +static void stm32_serial_setbaud_lpuart(struct stm32_serial_s *priv) { uint32_t brr; @@ -750,13 +750,13 @@ static void stm32wb_serial_setbaud_lpuart(struct stm32wb_serial_s *priv) brr = LPUART_BRR_MIN; } - stm32wb_serial_putreg(priv, STM32WB_USART_BRR_OFFSET, brr); + stm32_serial_putreg(priv, STM32_USART_BRR_OFFSET, brr); } #endif #endif /**************************************************************************** - * Name: stm32wb_serial_setformat + * Name: stm32_serial_setformat * * Description: * Set the serial line format and speed. @@ -764,27 +764,27 @@ static void stm32wb_serial_setbaud_lpuart(struct stm32wb_serial_s *priv) ****************************************************************************/ #ifndef CONFIG_SUPPRESS_UART_CONFIG -static void stm32wb_serial_setformat(struct uart_dev_s *dev) +static void stm32_serial_setformat(struct uart_dev_s *dev) { - struct stm32wb_serial_s *priv = (struct stm32wb_serial_s *)dev->priv; + struct stm32_serial_s *priv = (struct stm32_serial_s *)dev->priv; uint32_t regval; /* Set baud rate */ -#ifdef CONFIG_STM32WB_LPUART1_SERIALDRIVER - if (priv->usartbase == STM32WB_LPUART1_BASE) +#ifdef CONFIG_STM32_LPUART1_SERIALDRIVER + if (priv->usartbase == STM32_LPUART1_BASE) { - stm32wb_serial_setbaud_lpuart(priv); + stm32_serial_setbaud_lpuart(priv); } else #endif { - stm32wb_serial_setbaud_usart(priv); + stm32_serial_setbaud_usart(priv); } /* Configure parity mode */ - regval = stm32wb_serial_getreg(priv, STM32WB_USART_CR1_OFFSET); + regval = stm32_serial_getreg(priv, STM32_USART_CR1_OFFSET); regval &= ~(USART_CR1_PCE | USART_CR1_PS | USART_CR1_M0 | USART_CR1_M1); if (priv->parity == 1) /* Odd parity */ @@ -822,11 +822,11 @@ static void stm32wb_serial_setformat(struct uart_dev_s *dev) * 1 start, 8 data (no parity), n stop. */ - stm32wb_serial_putreg(priv, STM32WB_USART_CR1_OFFSET, regval); + stm32_serial_putreg(priv, STM32_USART_CR1_OFFSET, regval); /* Configure STOP bits */ - regval = stm32wb_serial_getreg(priv, STM32WB_USART_CR2_OFFSET); + regval = stm32_serial_getreg(priv, STM32_USART_CR2_OFFSET); regval &= ~(USART_CR2_STOP_MASK); if (priv->stopbits2) @@ -834,14 +834,14 @@ static void stm32wb_serial_setformat(struct uart_dev_s *dev) regval |= USART_CR2_STOP2; } - stm32wb_serial_putreg(priv, STM32WB_USART_CR2_OFFSET, regval); + stm32_serial_putreg(priv, STM32_USART_CR2_OFFSET, regval); /* Configure hardware flow control */ - regval = stm32wb_serial_getreg(priv, STM32WB_USART_CR3_OFFSET); + regval = stm32_serial_getreg(priv, STM32_USART_CR3_OFFSET); regval &= ~(USART_CR3_CTSE | USART_CR3_RTSE); -#if defined(CONFIG_SERIAL_IFLOWCONTROL) && !defined(CONFIG_STM32WB_FLOWCONTROL_BROKEN) +#if defined(CONFIG_SERIAL_IFLOWCONTROL) && !defined(CONFIG_STM32_FLOWCONTROL_BROKEN) if (priv->iflow && (priv->rts_gpio != 0)) { regval |= USART_CR3_RTSE; @@ -855,12 +855,12 @@ static void stm32wb_serial_setformat(struct uart_dev_s *dev) } #endif - stm32wb_serial_putreg(priv, STM32WB_USART_CR3_OFFSET, regval); + stm32_serial_putreg(priv, STM32_USART_CR3_OFFSET, regval); } #endif /* CONFIG_SUPPRESS_UART_CONFIG */ /**************************************************************************** - * Name: stm32wb_serial_setsuspend + * Name: stm32_serial_setsuspend * * Description: * Suspend or resume serial peripheral. @@ -868,9 +868,9 @@ static void stm32wb_serial_setformat(struct uart_dev_s *dev) ****************************************************************************/ #ifdef CONFIG_PM -static void stm32wb_serial_setsuspend(struct uart_dev_s *dev, bool suspend) +static void stm32_serial_setsuspend(struct uart_dev_s *dev, bool suspend) { - struct stm32wb_serial_s *priv = (struct stm32wb_serial_s *)dev->priv; + struct stm32_serial_s *priv = (struct stm32_serial_s *)dev->priv; #ifdef SERIAL_HAVE_RXDMA bool dmarestored = false; #endif @@ -889,18 +889,18 @@ static void stm32wb_serial_setsuspend(struct uart_dev_s *dev, bool suspend) { /* Force RTS high to prevent further Rx. */ - stm32wb_configgpio((priv->rts_gpio & ~GPIO_MODE_MASK) + stm32_configgpio((priv->rts_gpio & ~GPIO_MODE_MASK) | (GPIO_OUTPUT | GPIO_OUTPUT_SET)); } #endif /* Disable interrupts to prevent Tx. */ - stm32wb_serial_disableusartint(priv, &priv->suspended_ie); + stm32_serial_disableusartint(priv, &priv->suspended_ie); /* Wait last Tx to complete. */ - while ((stm32wb_serial_getreg(priv, STM32WB_USART_ISR_OFFSET) & + while ((stm32_serial_getreg(priv, STM32_USART_ISR_OFFSET) & USART_ISR_TC) == 0); #ifdef SERIAL_HAVE_RXDMA @@ -918,7 +918,7 @@ static void stm32wb_serial_setsuspend(struct uart_dev_s *dev, bool suspend) { /* Suspend Rx DMA. */ - stm32wb_dmastop(priv->rxdma); + stm32_dmastop(priv->rxdma); priv->rxdmasusp = true; } } @@ -932,7 +932,7 @@ static void stm32wb_serial_setsuspend(struct uart_dev_s *dev, bool suspend) #ifdef CONFIG_SERIAL_IFLOWCONTROL if (priv->iflow) { - stm32wb_serial_dmaiflowrestart(priv); + stm32_serial_dmaiflowrestart(priv); } else #endif @@ -942,7 +942,7 @@ static void stm32wb_serial_setsuspend(struct uart_dev_s *dev, bool suspend) * to DMA buffer before suspending). */ - stm32wb_serial_dmareenable(priv); + stm32_serial_dmareenable(priv); priv->rxdmasusp = false; } @@ -952,14 +952,14 @@ static void stm32wb_serial_setsuspend(struct uart_dev_s *dev, bool suspend) /* Re-enable interrupts to resume Tx. */ - stm32wb_serial_restoreusartint(priv, priv->suspended_ie); + stm32_serial_restoreusartint(priv, priv->suspended_ie); #ifdef CONFIG_SERIAL_IFLOWCONTROL if (priv->iflow) { /* Restore peripheral RTS control. */ - stm32wb_configgpio(priv->rts_gpio); + stm32_configgpio(priv->rts_gpio); } #endif } @@ -977,7 +977,7 @@ static void stm32wb_serial_setsuspend(struct uart_dev_s *dev, bool suspend) if (priv->rxdma != NULL) { - stm32wb_serial_dmarxcallback(priv->rxdma, 0, priv); + stm32_serial_dmarxcallback(priv->rxdma, 0, priv); } leave_critical_section(flags); @@ -987,7 +987,7 @@ static void stm32wb_serial_setsuspend(struct uart_dev_s *dev, bool suspend) #endif /**************************************************************************** - * Name: stm32wb_serial_pm_setsuspend + * Name: stm32_serial_pm_setsuspend * * Description: * Suspend or resume serial peripherals for/from deep-sleep/stop modes. @@ -995,7 +995,7 @@ static void stm32wb_serial_setsuspend(struct uart_dev_s *dev, bool suspend) ****************************************************************************/ #ifdef CONFIG_PM -static void stm32wb_serial_pm_setsuspend(bool suspend) +static void stm32_serial_pm_setsuspend(bool suspend) { int n; @@ -1008,20 +1008,20 @@ static void stm32wb_serial_pm_setsuspend(bool suspend) g_serialpm.serial_suspended = suspend; - for (n = 0; n < STM32WB_NLPUART + STM32WB_NUSART; n++) + for (n = 0; n < STM32_NLPUART + STM32_NUSART; n++) { - struct stm32wb_serial_s *priv = g_uart_devs[n]; + struct stm32_serial_s *priv = g_uart_devs[n]; if (priv != NULL && priv->initialized != NULL) { - stm32wb_serial_setsuspend(&priv->dev, suspend); + stm32_serial_setsuspend(&priv->dev, suspend); } } } #endif /**************************************************************************** - * Name: stm32wb_serial_setapbclock + * Name: stm32_serial_setapbclock * * Description: * Enable or disable APB clock for the USART peripheral @@ -1032,9 +1032,9 @@ static void stm32wb_serial_pm_setsuspend(bool suspend) * ****************************************************************************/ -static void stm32wb_serial_setapbclock(struct uart_dev_s *dev, bool on) +static void stm32_serial_setapbclock(struct uart_dev_s *dev, bool on) { - struct stm32wb_serial_s *priv = (struct stm32wb_serial_s *)dev->priv; + struct stm32_serial_s *priv = (struct stm32_serial_s *)dev->priv; uint32_t rcc_en; uint32_t regaddr; @@ -1044,16 +1044,16 @@ static void stm32wb_serial_setapbclock(struct uart_dev_s *dev, bool on) { default: return; -#ifdef CONFIG_STM32WB_LPUART1_SERIALDRIVER - case STM32WB_LPUART1_BASE: +#ifdef CONFIG_STM32_LPUART1_SERIALDRIVER + case STM32_LPUART1_BASE: rcc_en = RCC_APB1ENR2_LPUART1EN; - regaddr = STM32WB_RCC_APB1ENR2; + regaddr = STM32_RCC_APB1ENR2; break; #endif -#ifdef CONFIG_STM32WB_USART1_SERIALDRIVER - case STM32WB_USART1_BASE: +#ifdef CONFIG_STM32_USART1_SERIALDRIVER + case STM32_USART1_BASE: rcc_en = RCC_APB2ENR_USART1EN; - regaddr = STM32WB_RCC_APB2ENR; + regaddr = STM32_RCC_APB2ENR; break; #endif } @@ -1071,7 +1071,7 @@ static void stm32wb_serial_setapbclock(struct uart_dev_s *dev, bool on) } /**************************************************************************** - * Name: stm32wb_serial_setup + * Name: stm32_serial_setup * * Description: * Configure the USART baud, bits, parity, etc. This method is called the @@ -1079,37 +1079,37 @@ static void stm32wb_serial_setapbclock(struct uart_dev_s *dev, bool on) * ****************************************************************************/ -static int stm32wb_serial_setup(struct uart_dev_s *dev) +static int stm32_serial_setup(struct uart_dev_s *dev) { - struct stm32wb_serial_s *priv = (struct stm32wb_serial_s *)dev->priv; + struct stm32_serial_s *priv = (struct stm32_serial_s *)dev->priv; #ifndef CONFIG_SUPPRESS_UART_CONFIG uint32_t regval; /* Note: The logic here depends on the fact that that the USART module - * was enabled in stm32wb_lowsetup(). + * was enabled in stm32_lowsetup(). */ /* Enable USART APB1/2 clock */ - stm32wb_serial_setapbclock(dev, true); + stm32_serial_setapbclock(dev, true); /* Configure pins for USART use */ if (priv->tx_gpio != 0) { - stm32wb_configgpio(priv->tx_gpio); + stm32_configgpio(priv->tx_gpio); } if (priv->rx_gpio != 0) { - stm32wb_configgpio(priv->rx_gpio); + stm32_configgpio(priv->rx_gpio); } #ifdef CONFIG_SERIAL_OFLOWCONTROL if (priv->cts_gpio != 0) { - stm32wb_configgpio(priv->cts_gpio); + stm32_configgpio(priv->cts_gpio); } #endif @@ -1118,20 +1118,20 @@ static int stm32wb_serial_setup(struct uart_dev_s *dev) { uint32_t config = priv->rts_gpio; -#ifdef CONFIG_STM32WB_FLOWCONTROL_BROKEN +#ifdef CONFIG_STM32_FLOWCONTROL_BROKEN /* Instead of letting hw manage this pin, we will bitbang */ config = (config & ~GPIO_MODE_MASK) | GPIO_OUTPUT; #endif - stm32wb_configgpio(config); + stm32_configgpio(config); } #endif #ifdef HAVE_RS485 if (priv->rs485_dir_gpio != 0) { - stm32wb_configgpio(priv->rs485_dir_gpio); - stm32wb_gpiowrite(priv->rs485_dir_gpio, !priv->rs485_dir_polarity); + stm32_configgpio(priv->rs485_dir_gpio); + stm32_gpiowrite(priv->rs485_dir_gpio, !priv->rs485_dir_polarity); } #endif @@ -1139,7 +1139,7 @@ static int stm32wb_serial_setup(struct uart_dev_s *dev) /* Clear STOP, CLKEN, CPOL, CPHA, LBCL, and interrupt enable bits */ - regval = stm32wb_serial_getreg(priv, STM32WB_USART_CR2_OFFSET); + regval = stm32_serial_getreg(priv, STM32_USART_CR2_OFFSET); regval &= ~(USART_CR2_STOP_MASK | USART_CR2_CLKEN | USART_CR2_CPOL | USART_CR2_CPHA | USART_CR2_LBCL | USART_CR2_LBDIE); @@ -1150,36 +1150,36 @@ static int stm32wb_serial_setup(struct uart_dev_s *dev) regval |= USART_CR2_STOP2; } - stm32wb_serial_putreg(priv, STM32WB_USART_CR2_OFFSET, regval); + stm32_serial_putreg(priv, STM32_USART_CR2_OFFSET, regval); /* Configure CR1 */ /* Clear TE, REm and all interrupt enable bits */ - regval = stm32wb_serial_getreg(priv, STM32WB_USART_CR1_OFFSET); + regval = stm32_serial_getreg(priv, STM32_USART_CR1_OFFSET); regval &= ~(USART_CR1_TE | USART_CR1_RE | USART_CR1_ALLINTS); - stm32wb_serial_putreg(priv, STM32WB_USART_CR1_OFFSET, regval); + stm32_serial_putreg(priv, STM32_USART_CR1_OFFSET, regval); /* Configure CR3 */ /* Clear CTSE, RTSE, and all interrupt enable bits */ - regval = stm32wb_serial_getreg(priv, STM32WB_USART_CR3_OFFSET); + regval = stm32_serial_getreg(priv, STM32_USART_CR3_OFFSET); regval &= ~(USART_CR3_CTSIE | USART_CR3_CTSE | USART_CR3_RTSE | USART_CR3_EIE); - stm32wb_serial_putreg(priv, STM32WB_USART_CR3_OFFSET, regval); + stm32_serial_putreg(priv, STM32_USART_CR3_OFFSET, regval); /* Configure the USART line format and speed. */ - stm32wb_serial_setformat(dev); + stm32_serial_setformat(dev); /* Enable Rx, Tx, and the USART */ - regval = stm32wb_serial_getreg(priv, STM32WB_USART_CR1_OFFSET); + regval = stm32_serial_getreg(priv, STM32_USART_CR1_OFFSET); regval |= (USART_CR1_UE | USART_CR1_TE | USART_CR1_RE); - stm32wb_serial_putreg(priv, STM32WB_USART_CR1_OFFSET, regval); + stm32_serial_putreg(priv, STM32_USART_CR1_OFFSET, regval); #endif /* CONFIG_SUPPRESS_UART_CONFIG */ @@ -1195,7 +1195,7 @@ static int stm32wb_serial_setup(struct uart_dev_s *dev) } /**************************************************************************** - * Name: stm32wb_serial_dmasetup + * Name: stm32_serial_dmasetup * * Description: * Configure the USART baud, bits, parity, etc. This method is called the @@ -1204,9 +1204,9 @@ static int stm32wb_serial_setup(struct uart_dev_s *dev) ****************************************************************************/ #ifdef SERIAL_HAVE_RXDMA -static int stm32wb_serial_dmasetup(struct uart_dev_s *dev) +static int stm32_serial_dmasetup(struct uart_dev_s *dev) { - struct stm32wb_serial_s *priv = (struct stm32wb_serial_s *)dev->priv; + struct stm32_serial_s *priv = (struct stm32_serial_s *)dev->priv; int result; uint32_t regval; @@ -1214,7 +1214,7 @@ static int stm32wb_serial_dmasetup(struct uart_dev_s *dev) if (!dev->isconsole) { - result = stm32wb_serial_setup(dev); + result = stm32_serial_setup(dev); if (result != OK) { return result; @@ -1223,15 +1223,15 @@ static int stm32wb_serial_dmasetup(struct uart_dev_s *dev) /* Acquire the DMA channel. This should always succeed. */ - priv->rxdma = stm32wb_dmachannel(priv->rxdma_channel); + priv->rxdma = stm32_dmachannel(priv->rxdma_channel); #ifdef CONFIG_SERIAL_IFLOWCONTROL if (priv->iflow) { /* Configure for non-circular DMA reception into the RX FIFO */ - stm32wb_dmasetup(priv->rxdma, - priv->usartbase + STM32WB_USART_RDR_OFFSET, + stm32_dmasetup(priv->rxdma, + priv->usartbase + STM32_USART_RDR_OFFSET, (uint32_t)priv->rxfifo, RXDMA_BUFFER_SIZE, SERIAL_DMA_IFLOW_CONTROL_WORD); @@ -1241,8 +1241,8 @@ static int stm32wb_serial_dmasetup(struct uart_dev_s *dev) { /* Configure for circular DMA reception into the RX FIFO */ - stm32wb_dmasetup(priv->rxdma, - priv->usartbase + STM32WB_USART_RDR_OFFSET, + stm32_dmasetup(priv->rxdma, + priv->usartbase + STM32_USART_RDR_OFFSET, (uint32_t)priv->rxfifo, RXDMA_BUFFER_SIZE, SERIAL_DMA_CONTROL_WORD); @@ -1256,9 +1256,9 @@ static int stm32wb_serial_dmasetup(struct uart_dev_s *dev) /* Enable receive DMA for the UART */ - regval = stm32wb_serial_getreg(priv, STM32WB_USART_CR3_OFFSET); + regval = stm32_serial_getreg(priv, STM32_USART_CR3_OFFSET); regval |= USART_CR3_DMAR; - stm32wb_serial_putreg(priv, STM32WB_USART_CR3_OFFSET, regval); + stm32_serial_putreg(priv, STM32_USART_CR3_OFFSET, regval); #ifdef CONFIG_SERIAL_IFLOWCONTROL if (priv->iflow) @@ -1268,7 +1268,7 @@ static int stm32wb_serial_dmasetup(struct uart_dev_s *dev) * in and DMA transfer is stopped. */ - stm32wb_dmastart(priv->rxdma, stm32wb_serial_dmarxcallback, priv, + stm32_dmastart(priv->rxdma, stm32_serial_dmarxcallback, priv, false); } else @@ -1279,7 +1279,7 @@ static int stm32wb_serial_dmasetup(struct uart_dev_s *dev) * worth of time to claim bytes before they are overwritten. */ - stm32wb_dmastart(priv->rxdma, stm32wb_serial_dmarxcallback, priv, + stm32_dmastart(priv->rxdma, stm32_serial_dmarxcallback, priv, true); } @@ -1288,7 +1288,7 @@ static int stm32wb_serial_dmasetup(struct uart_dev_s *dev) #endif /**************************************************************************** - * Name: stm32wb_serial_shutdown + * Name: stm32_serial_shutdown * * Description: * Disable the USART. This method is called when the serial @@ -1296,9 +1296,9 @@ static int stm32wb_serial_dmasetup(struct uart_dev_s *dev) * ****************************************************************************/ -static void stm32wb_serial_shutdown(struct uart_dev_s *dev) +static void stm32_serial_shutdown(struct uart_dev_s *dev) { - struct stm32wb_serial_s *priv = (struct stm32wb_serial_s *)dev->priv; + struct stm32_serial_s *priv = (struct stm32_serial_s *)dev->priv; uint32_t regval; /* Mark device as uninitialized. */ @@ -1307,17 +1307,17 @@ static void stm32wb_serial_shutdown(struct uart_dev_s *dev) /* Disable all interrupts */ - stm32wb_serial_disableusartint(priv, NULL); + stm32_serial_disableusartint(priv, NULL); /* Disable USART APB1/2 clock */ - stm32wb_serial_setapbclock(dev, false); + stm32_serial_setapbclock(dev, false); /* Disable Rx, Tx, and the UART */ - regval = stm32wb_serial_getreg(priv, STM32WB_USART_CR1_OFFSET); + regval = stm32_serial_getreg(priv, STM32_USART_CR1_OFFSET); regval &= ~(USART_CR1_UE | USART_CR1_TE | USART_CR1_RE); - stm32wb_serial_putreg(priv, STM32WB_USART_CR1_OFFSET, regval); + stm32_serial_putreg(priv, STM32_USART_CR1_OFFSET, regval); /* Release pins. "If the serial-attached device is powered down, the TX * pin causes back-powering, potentially confusing the device to the point @@ -1329,38 +1329,38 @@ static void stm32wb_serial_shutdown(struct uart_dev_s *dev) if (priv->tx_gpio != 0) { - stm32wb_unconfiggpio(priv->tx_gpio); + stm32_unconfiggpio(priv->tx_gpio); } if (priv->rx_gpio != 0) { - stm32wb_unconfiggpio(priv->rx_gpio); + stm32_unconfiggpio(priv->rx_gpio); } #ifdef CONFIG_SERIAL_OFLOWCONTROL if (priv->cts_gpio != 0) { - stm32wb_unconfiggpio(priv->cts_gpio); + stm32_unconfiggpio(priv->cts_gpio); } #endif #ifdef CONFIG_SERIAL_IFLOWCONTROL if (priv->rts_gpio != 0) { - stm32wb_unconfiggpio(priv->rts_gpio); + stm32_unconfiggpio(priv->rts_gpio); } #endif #ifdef HAVE_RS485 if (priv->rs485_dir_gpio != 0) { - stm32wb_unconfiggpio(priv->rs485_dir_gpio); + stm32_unconfiggpio(priv->rs485_dir_gpio); } #endif } /**************************************************************************** - * Name: stm32wb_serial_dmashutdown + * Name: stm32_serial_dmashutdown * * Description: * Disable the USART. This method is called when the serial @@ -1369,27 +1369,27 @@ static void stm32wb_serial_shutdown(struct uart_dev_s *dev) ****************************************************************************/ #ifdef SERIAL_HAVE_RXDMA -static void stm32wb_serial_dmashutdown(struct uart_dev_s *dev) +static void stm32_serial_dmashutdown(struct uart_dev_s *dev) { - struct stm32wb_serial_s *priv = (struct stm32wb_serial_s *)dev->priv; + struct stm32_serial_s *priv = (struct stm32_serial_s *)dev->priv; /* Perform the normal UART shutdown */ - stm32wb_serial_shutdown(dev); + stm32_serial_shutdown(dev); /* Stop the DMA channel */ - stm32wb_dmastop(priv->rxdma); + stm32_dmastop(priv->rxdma); /* Release the DMA channel */ - stm32wb_dmafree(priv->rxdma); + stm32_dmafree(priv->rxdma); priv->rxdma = NULL; } #endif /**************************************************************************** - * Name: stm32wb_serial_attach + * Name: stm32_serial_attach * * Description: * Configure the USART to operation in interrupt driven mode. This method @@ -1404,9 +1404,9 @@ static void stm32wb_serial_dmashutdown(struct uart_dev_s *dev) * ****************************************************************************/ -static int stm32wb_serial_attach(struct uart_dev_s *dev) +static int stm32_serial_attach(struct uart_dev_s *dev) { - struct stm32wb_serial_s *priv = (struct stm32wb_serial_s *)dev->priv; + struct stm32_serial_s *priv = (struct stm32_serial_s *)dev->priv; int ret; /* Attach and enable the IRQ */ @@ -1425,7 +1425,7 @@ static int stm32wb_serial_attach(struct uart_dev_s *dev) } /**************************************************************************** - * Name: stm32wb_serial_detach + * Name: stm32_serial_detach * * Description: * Detach USART interrupts. This method is called when the serial port is @@ -1434,9 +1434,9 @@ static int stm32wb_serial_attach(struct uart_dev_s *dev) * ****************************************************************************/ -static void stm32wb_serial_detach(struct uart_dev_s *dev) +static void stm32_serial_detach(struct uart_dev_s *dev) { - struct stm32wb_serial_s *priv = (struct stm32wb_serial_s *)dev->priv; + struct stm32_serial_s *priv = (struct stm32_serial_s *)dev->priv; up_disable_irq(priv->irq); irq_detach(priv->irq); } @@ -1455,7 +1455,7 @@ static void stm32wb_serial_detach(struct uart_dev_s *dev) static int up_interrupt(int irq, void *context, void *arg) { - struct stm32wb_serial_s *priv = (struct stm32wb_serial_s *)arg; + struct stm32_serial_s *priv = (struct stm32_serial_s *)arg; int passes; bool handled; @@ -1463,8 +1463,8 @@ static int up_interrupt(int irq, void *context, void *arg) /* Report serial activity to the power management logic */ -#if defined(CONFIG_PM) && CONFIG_STM32WB_PM_SERIAL_ACTIVITY > 0 - pm_activity(PM_IDLE_DOMAIN, CONFIG_STM32WB_PM_SERIAL_ACTIVITY); +#if defined(CONFIG_PM) && CONFIG_STM32_PM_SERIAL_ACTIVITY > 0 + pm_activity(PM_IDLE_DOMAIN, CONFIG_STM32_PM_SERIAL_ACTIVITY); #endif /* Loop until there are no characters to be transferred or, @@ -1478,7 +1478,7 @@ static int up_interrupt(int irq, void *context, void *arg) /* Get the masked USART status word. */ - priv->sr = stm32wb_serial_getreg(priv, STM32WB_USART_ISR_OFFSET); + priv->sr = stm32_serial_getreg(priv, STM32_USART_ISR_OFFSET); /* USART interrupts: * @@ -1520,8 +1520,8 @@ static int up_interrupt(int irq, void *context, void *arg) (priv->ie & USART_CR1_TCIE) != 0 && (priv->ie & USART_CR1_TXEIE) == 0) { - stm32wb_gpiowrite(priv->rs485_dir_gpio, !priv->rs485_dir_polarity); - stm32wb_serial_restoreusartint(priv, priv->ie & ~USART_CR1_TCIE); + stm32_gpiowrite(priv->rs485_dir_gpio, !priv->rs485_dir_polarity); + stm32_serial_restoreusartint(priv, priv->ie & ~USART_CR1_TCIE); } #endif @@ -1550,7 +1550,7 @@ static int up_interrupt(int irq, void *context, void *arg) * interrupt clear register (ICR). */ - stm32wb_serial_putreg(priv, STM32WB_USART_ICR_OFFSET, + stm32_serial_putreg(priv, STM32_USART_ICR_OFFSET, (USART_ICR_NCF | USART_ICR_ORECF | USART_ICR_FECF)); } @@ -1571,14 +1571,14 @@ static int up_interrupt(int irq, void *context, void *arg) } /**************************************************************************** - * Name: stm32wb_serial_ioctl + * Name: stm32_serial_ioctl * * Description: * All ioctl calls will be routed through this method * ****************************************************************************/ -static int stm32wb_serial_ioctl(struct file *filep, int cmd, +static int stm32_serial_ioctl(struct file *filep, int cmd, unsigned long arg) { #if defined(CONFIG_SERIAL_TERMIOS) || defined(CONFIG_SERIAL_TIOCSERGSTRUCT) @@ -1586,7 +1586,7 @@ static int stm32wb_serial_ioctl(struct file *filep, int cmd, struct uart_dev_s *dev = inode->i_private; #endif #if defined(CONFIG_SERIAL_TERMIOS) - struct stm32wb_serial_s *priv = (struct stm32wb_serial_s *)dev->priv; + struct stm32_serial_s *priv = (struct stm32_serial_s *)dev->priv; #endif int ret = OK; @@ -1595,20 +1595,20 @@ static int stm32wb_serial_ioctl(struct file *filep, int cmd, #ifdef CONFIG_SERIAL_TIOCSERGSTRUCT case TIOCSERGSTRUCT: { - struct stm32wb_serial_s *user = (struct stm32wb_serial_s *)arg; + struct stm32_serial_s *user = (struct stm32_serial_s *)arg; if (!user) { ret = -EINVAL; } else { - memcpy(user, dev, sizeof(struct stm32wb_serial_s)); + memcpy(user, dev, sizeof(struct stm32_serial_s)); } } break; #endif -#ifdef CONFIG_STM32WB_USART_SINGLEWIRE +#ifdef CONFIG_STM32_USART_SINGLEWIRE case TIOCSSINGLEWIRE: { uint32_t cr1; @@ -1619,19 +1619,19 @@ static int stm32wb_serial_ioctl(struct file *filep, int cmd, /* Get the original state of UE */ - cr1 = stm32wb_serial_getreg(priv, STM32WB_USART_CR1_OFFSET); + cr1 = stm32_serial_getreg(priv, STM32_USART_CR1_OFFSET); cr1_ue = cr1 & USART_CR1_UE; cr1 &= ~USART_CR1_UE; /* Disable UE, HDSEL can only be written when UE=0 */ - stm32wb_serial_putreg(priv, STM32WB_USART_CR1_OFFSET, cr1); + stm32_serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1); /* Change the TX port to be open-drain/push-pull and enable/disable * half-duplex mode. */ - uint32_t cr = stm32wb_serial_getreg(priv, STM32WB_USART_CR3_OFFSET); + uint32_t cr = stm32_serial_getreg(priv, STM32_USART_CR3_OFFSET); if ((arg & SER_SINGLEWIRE_ENABLED) != 0) { @@ -1648,7 +1648,7 @@ static int stm32wb_serial_ioctl(struct file *filep, int cmd, if (priv->tx_gpio != 0) { - stm32wb_configgpio((priv->tx_gpio & ~(GPIO_PUPD_MASK | + stm32_configgpio((priv->tx_gpio & ~(GPIO_PUPD_MASK | GPIO_OPENDRAIN)) | gpio_val); } @@ -1659,7 +1659,7 @@ static int stm32wb_serial_ioctl(struct file *filep, int cmd, { if (priv->tx_gpio != 0) { - stm32wb_configgpio((priv->tx_gpio & ~(GPIO_PUPD_MASK | + stm32_configgpio((priv->tx_gpio & ~(GPIO_PUPD_MASK | GPIO_OPENDRAIN)) | GPIO_PUSHPULL); } @@ -1667,17 +1667,17 @@ static int stm32wb_serial_ioctl(struct file *filep, int cmd, cr &= ~USART_CR3_HDSEL; } - stm32wb_serial_putreg(priv, STM32WB_USART_CR3_OFFSET, cr); + stm32_serial_putreg(priv, STM32_USART_CR3_OFFSET, cr); /* Re-enable UE if appropriate */ - stm32wb_serial_putreg(priv, STM32WB_USART_CR1_OFFSET, cr1 | cr1_ue); + stm32_serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1 | cr1_ue); leave_critical_section(flags); } break; #endif -#ifdef CONFIG_STM32WB_USART_INVERT +#ifdef CONFIG_STM32_USART_INVERT case TIOCSINVERT: { uint32_t cr1; @@ -1688,17 +1688,17 @@ static int stm32wb_serial_ioctl(struct file *filep, int cmd, /* Get the original state of UE */ - cr1 = stm32wb_serial_getreg(priv, STM32WB_USART_CR1_OFFSET); + cr1 = stm32_serial_getreg(priv, STM32_USART_CR1_OFFSET); cr1_ue = cr1 & USART_CR1_UE; cr1 &= ~USART_CR1_UE; /* Disable UE, {R,T}XINV can only be written when UE=0 */ - stm32wb_serial_putreg(priv, STM32WB_USART_CR1_OFFSET, cr1); + stm32_serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1); /* Enable/disable signal inversion. */ - uint32_t cr = stm32wb_serial_getreg(priv, STM32WB_USART_CR2_OFFSET); + uint32_t cr = stm32_serial_getreg(priv, STM32_USART_CR2_OFFSET); if (arg & SER_INVERT_ENABLED_RX) { @@ -1718,17 +1718,17 @@ static int stm32wb_serial_ioctl(struct file *filep, int cmd, cr &= ~USART_CR2_TXINV; } - stm32wb_serial_putreg(priv, STM32WB_USART_CR2_OFFSET, cr); + stm32_serial_putreg(priv, STM32_USART_CR2_OFFSET, cr); /* Re-enable UE if appropriate */ - stm32wb_serial_putreg(priv, STM32WB_USART_CR1_OFFSET, cr1 | cr1_ue); + stm32_serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1 | cr1_ue); leave_critical_section(flags); } break; #endif -#ifdef CONFIG_STM32WB_USART_SWAP +#ifdef CONFIG_STM32_USART_SWAP case TIOCSSWAP: { uint32_t cr1; @@ -1739,17 +1739,17 @@ static int stm32wb_serial_ioctl(struct file *filep, int cmd, /* Get the original state of UE */ - cr1 = stm32wb_serial_getreg(priv, STM32WB_USART_CR1_OFFSET); + cr1 = stm32_serial_getreg(priv, STM32_USART_CR1_OFFSET); cr1_ue = cr1 & USART_CR1_UE; cr1 &= ~USART_CR1_UE; /* Disable UE, SWAP can only be written when UE=0 */ - stm32wb_serial_putreg(priv, STM32WB_USART_CR1_OFFSET, cr1); + stm32_serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1); /* Enable/disable Swap mode. */ - uint32_t cr = stm32wb_serial_getreg(priv, STM32WB_USART_CR2_OFFSET); + uint32_t cr = stm32_serial_getreg(priv, STM32_USART_CR2_OFFSET); if (arg == SER_SWAP_ENABLED) { @@ -1760,11 +1760,11 @@ static int stm32wb_serial_ioctl(struct file *filep, int cmd, cr &= ~USART_CR2_SWAP; } - stm32wb_serial_putreg(priv, STM32WB_USART_CR2_OFFSET, cr); + stm32_serial_putreg(priv, STM32_USART_CR2_OFFSET, cr); /* Re-enable UE if appropriate */ - stm32wb_serial_putreg(priv, STM32WB_USART_CR1_OFFSET, cr1 | cr1_ue); + stm32_serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1 | cr1_ue); leave_critical_section(flags); } break; @@ -1860,13 +1860,13 @@ static int stm32wb_serial_ioctl(struct file *filep, int cmd, * TCSADRAIN / TCSAFLUSH */ - stm32wb_serial_setformat(dev); + stm32_serial_setformat(dev); } break; #endif /* CONFIG_SERIAL_TERMIOS */ -#ifdef CONFIG_STM32WB_USART_BREAKS -# ifdef CONFIG_STM32WB_SERIALBRK_BSDCOMPAT +#ifdef CONFIG_STM32_USART_BREAKS +# ifdef CONFIG_STM32_SERIALBRK_BSDCOMPAT case TIOCSBRK: /* BSD compatibility: Turn break on, unconditionally */ { irqstate_t flags; @@ -1877,7 +1877,7 @@ static int stm32wb_serial_ioctl(struct file *filep, int cmd, priv->ie |= USART_CR1_IE_BREAK_INPROGRESS; - stm32wb_serial_txint(dev, false); + stm32_serial_txint(dev, false); /* Configure TX as a GPIO output pin and Send a break signal */ @@ -1885,7 +1885,7 @@ static int stm32wb_serial_ioctl(struct file *filep, int cmd, { uint32_t tx_break = GPIO_OUTPUT | (~(GPIO_MODE_MASK | GPIO_OUTPUT_SET) & priv->tx_gpio); - stm32wb_configgpio(tx_break); + stm32_configgpio(tx_break); } leave_critical_section(flags); @@ -1902,14 +1902,14 @@ static int stm32wb_serial_ioctl(struct file *filep, int cmd, if (priv->tx_gpio != 0) { - stm32wb_configgpio(priv->tx_gpio); + stm32_configgpio(priv->tx_gpio); } priv->ie &= ~USART_CR1_IE_BREAK_INPROGRESS; /* Enable further tx activity */ - stm32wb_serial_txint(dev, true); + stm32_serial_txint(dev, true); leave_critical_section(flags); } @@ -1921,8 +1921,8 @@ static int stm32wb_serial_ioctl(struct file *filep, int cmd, irqstate_t flags; flags = enter_critical_section(); - cr1 = stm32wb_serial_getreg(priv, STM32WB_USART_CR1_OFFSET); - stm32wb_serial_putreg(priv, STM32WB_USART_CR1_OFFSET, + cr1 = stm32_serial_getreg(priv, STM32_USART_CR1_OFFSET); + stm32_serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1 | USART_CR1_SBK); leave_critical_section(flags); } @@ -1934,8 +1934,8 @@ static int stm32wb_serial_ioctl(struct file *filep, int cmd, irqstate_t flags; flags = enter_critical_section(); - cr1 = stm32wb_serial_getreg(priv, STM32WB_USART_CR1_OFFSET); - stm32wb_serial_putreg(priv, STM32WB_USART_CR1_OFFSET, + cr1 = stm32_serial_getreg(priv, STM32_USART_CR1_OFFSET); + stm32_serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1 & ~USART_CR1_SBK); leave_critical_section(flags); } @@ -1952,7 +1952,7 @@ static int stm32wb_serial_ioctl(struct file *filep, int cmd, } /**************************************************************************** - * Name: stm32wb_serial_receive + * Name: stm32_serial_receive * * Description: * Called (usually) from the interrupt level to receive one @@ -1962,15 +1962,15 @@ static int stm32wb_serial_ioctl(struct file *filep, int cmd, ****************************************************************************/ #ifndef SERIAL_HAVE_ONLY_DMA -static int stm32wb_serial_receive(struct uart_dev_s *dev, +static int stm32_serial_receive(struct uart_dev_s *dev, unsigned int *status) { - struct stm32wb_serial_s *priv = (struct stm32wb_serial_s *)dev->priv; + struct stm32_serial_s *priv = (struct stm32_serial_s *)dev->priv; uint32_t rdr; /* Get the Rx byte */ - rdr = stm32wb_serial_getreg(priv, STM32WB_USART_RDR_OFFSET); + rdr = stm32_serial_getreg(priv, STM32_USART_RDR_OFFSET); /* Get the Rx byte plux error information. Return those in status */ @@ -1984,7 +1984,7 @@ static int stm32wb_serial_receive(struct uart_dev_s *dev, #endif /**************************************************************************** - * Name: stm32wb_serial_rxint + * Name: stm32_serial_rxint * * Description: * Call to enable or disable RX interrupts @@ -1992,9 +1992,9 @@ static int stm32wb_serial_receive(struct uart_dev_s *dev, ****************************************************************************/ #ifndef SERIAL_HAVE_ONLY_DMA -static void stm32wb_serial_rxint(struct uart_dev_s *dev, bool enable) +static void stm32_serial_rxint(struct uart_dev_s *dev, bool enable) { - struct stm32wb_serial_s *priv = (struct stm32wb_serial_s *)dev->priv; + struct stm32_serial_s *priv = (struct stm32_serial_s *)dev->priv; irqstate_t flags; uint16_t ie; @@ -2040,13 +2040,13 @@ static void stm32wb_serial_rxint(struct uart_dev_s *dev, bool enable) /* Then set the new interrupt state */ - stm32wb_serial_restoreusartint(priv, ie); + stm32_serial_restoreusartint(priv, ie); leave_critical_section(flags); } #endif /**************************************************************************** - * Name: stm32wb_serial_rxavailable + * Name: stm32_serial_rxavailable * * Description: * Return true if the receive register is not empty @@ -2054,17 +2054,17 @@ static void stm32wb_serial_rxint(struct uart_dev_s *dev, bool enable) ****************************************************************************/ #ifndef SERIAL_HAVE_ONLY_DMA -static bool stm32wb_serial_rxavailable(struct uart_dev_s *dev) +static bool stm32_serial_rxavailable(struct uart_dev_s *dev) { - struct stm32wb_serial_s *priv = (struct stm32wb_serial_s *)dev->priv; + struct stm32_serial_s *priv = (struct stm32_serial_s *)dev->priv; - return ((stm32wb_serial_getreg(priv, STM32WB_USART_ISR_OFFSET) & + return ((stm32_serial_getreg(priv, STM32_USART_ISR_OFFSET) & USART_ISR_RXNE) != 0); } #endif /**************************************************************************** - * Name: stm32wb_serial_rxflowcontrol + * Name: stm32_serial_rxflowcontrol * * Description: * Called when Rx buffer is full (or exceeds configured watermark levels @@ -2087,18 +2087,18 @@ static bool stm32wb_serial_rxavailable(struct uart_dev_s *dev) ****************************************************************************/ #ifdef CONFIG_SERIAL_IFLOWCONTROL -static bool stm32wb_serial_rxflowcontrol(struct uart_dev_s *dev, +static bool stm32_serial_rxflowcontrol(struct uart_dev_s *dev, unsigned int nbuffered, bool upper) { - struct stm32wb_serial_s *priv = (struct stm32wb_serial_s *)dev->priv; + struct stm32_serial_s *priv = (struct stm32_serial_s *)dev->priv; #if defined(CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS) && \ - defined(CONFIG_STM32WB_FLOWCONTROL_BROKEN) + defined(CONFIG_STM32_FLOWCONTROL_BROKEN) if (priv->iflow && (priv->rts_gpio != 0)) { /* Assert/de-assert nRTS set it high resume/stop sending */ - stm32wb_gpiowrite(priv->rts_gpio, upper); + stm32_gpiowrite(priv->rts_gpio, upper); if (upper) { @@ -2160,7 +2160,7 @@ static bool stm32wb_serial_rxflowcontrol(struct uart_dev_s *dev, #endif /**************************************************************************** - * Name: stm32wb_serial_dmareceive + * Name: stm32_serial_dmareceive * * Description: * Called (usually) from the interrupt level to receive one @@ -2170,13 +2170,13 @@ static bool stm32wb_serial_rxflowcontrol(struct uart_dev_s *dev, ****************************************************************************/ #ifdef SERIAL_HAVE_RXDMA -static int stm32wb_serial_dmareceive(struct uart_dev_s *dev, +static int stm32_serial_dmareceive(struct uart_dev_s *dev, unsigned int *status) { - struct stm32wb_serial_s *priv = (struct stm32wb_serial_s *)dev->priv; + struct stm32_serial_s *priv = (struct stm32_serial_s *)dev->priv; int c = 0; - if (stm32wb_serial_dmanextrx(priv) != priv->rxdmanext) + if (stm32_serial_dmanextrx(priv) != priv->rxdmanext) { c = priv->rxfifo[priv->rxdmanext]; @@ -2203,7 +2203,7 @@ static int stm32wb_serial_dmareceive(struct uart_dev_s *dev, #endif /**************************************************************************** - * Name: stm32wb_serial_dmareenable + * Name: stm32_serial_dmareenable * * Description: * Call to re-enable RX DMA. @@ -2211,15 +2211,15 @@ static int stm32wb_serial_dmareceive(struct uart_dev_s *dev, ****************************************************************************/ #if defined(SERIAL_HAVE_RXDMA) -static void stm32wb_serial_dmareenable(struct stm32wb_serial_s *priv) +static void stm32_serial_dmareenable(struct stm32_serial_s *priv) { #ifdef CONFIG_SERIAL_IFLOWCONTROL if (priv->iflow) { /* Configure for non-circular DMA reception into the RX FIFO */ - stm32wb_dmasetup(priv->rxdma, - priv->usartbase + STM32WB_USART_RDR_OFFSET, + stm32_dmasetup(priv->rxdma, + priv->usartbase + STM32_USART_RDR_OFFSET, (uint32_t)priv->rxfifo, RXDMA_BUFFER_SIZE, SERIAL_DMA_IFLOW_CONTROL_WORD); @@ -2229,8 +2229,8 @@ static void stm32wb_serial_dmareenable(struct stm32wb_serial_s *priv) { /* Configure for circular DMA reception into the RX FIFO */ - stm32wb_dmasetup(priv->rxdma, - priv->usartbase + STM32WB_USART_RDR_OFFSET, + stm32_dmasetup(priv->rxdma, + priv->usartbase + STM32_USART_RDR_OFFSET, (uint32_t)priv->rxfifo, RXDMA_BUFFER_SIZE, SERIAL_DMA_CONTROL_WORD); @@ -2250,7 +2250,7 @@ static void stm32wb_serial_dmareenable(struct stm32wb_serial_s *priv) * in and DMA transfer is stopped. */ - stm32wb_dmastart(priv->rxdma, stm32wb_serial_dmarxcallback, priv, + stm32_dmastart(priv->rxdma, stm32_serial_dmarxcallback, priv, false); } else @@ -2261,7 +2261,7 @@ static void stm32wb_serial_dmareenable(struct stm32wb_serial_s *priv) * worth of time to claim bytes before they are overwritten. */ - stm32wb_dmastart(priv->rxdma, stm32wb_serial_dmarxcallback, priv, + stm32_dmastart(priv->rxdma, stm32_serial_dmarxcallback, priv, true); } @@ -2274,7 +2274,7 @@ static void stm32wb_serial_dmareenable(struct stm32wb_serial_s *priv) #endif /**************************************************************************** - * Name: stm32wb_serial_dmaiflowrestart + * Name: stm32_serial_dmaiflowrestart * * Description: * Call to restart RX DMA for input flow-controlled USART @@ -2282,7 +2282,7 @@ static void stm32wb_serial_dmareenable(struct stm32wb_serial_s *priv) ****************************************************************************/ #if defined(SERIAL_HAVE_RXDMA) && defined(CONFIG_SERIAL_IFLOWCONTROL) -static bool stm32wb_serial_dmaiflowrestart(struct stm32wb_serial_s *priv) +static bool stm32_serial_dmaiflowrestart(struct stm32_serial_s *priv) { if (!priv->rxenable) { @@ -2298,7 +2298,7 @@ static bool stm32wb_serial_dmaiflowrestart(struct stm32wb_serial_s *priv) { /* Rx DMA in suspended state. */ - if (stm32wb_serial_dmarxavailable(&priv->dev)) + if (stm32_serial_dmarxavailable(&priv->dev)) { /* DMA buffer has unprocessed data, do not re-enable yet. */ @@ -2316,14 +2316,14 @@ static bool stm32wb_serial_dmaiflowrestart(struct stm32wb_serial_s *priv) * re-enabling without data loss is now safe. */ - stm32wb_serial_dmareenable(priv); + stm32_serial_dmareenable(priv); return true; } #endif /**************************************************************************** - * Name: stm32wb_serial_dmarxint + * Name: stm32_serial_dmarxint * * Description: * Call to enable or disable RX interrupts @@ -2331,9 +2331,9 @@ static bool stm32wb_serial_dmaiflowrestart(struct stm32wb_serial_s *priv) ****************************************************************************/ #ifdef SERIAL_HAVE_RXDMA -static void stm32wb_serial_dmarxint(struct uart_dev_s *dev, bool enable) +static void stm32_serial_dmarxint(struct uart_dev_s *dev, bool enable) { - struct stm32wb_serial_s *priv = (struct stm32wb_serial_s *)dev->priv; + struct stm32_serial_s *priv = (struct stm32_serial_s *)dev->priv; /* En/disable DMA reception. * @@ -2350,14 +2350,14 @@ static void stm32wb_serial_dmarxint(struct uart_dev_s *dev, bool enable) { /* Re-enable RX DMA. */ - stm32wb_serial_dmaiflowrestart(priv); + stm32_serial_dmaiflowrestart(priv); } #endif } #endif /**************************************************************************** - * Name: stm32wb_serial_dmarxavailable + * Name: stm32_serial_dmarxavailable * * Description: * Return true if the receive register is not empty @@ -2365,51 +2365,51 @@ static void stm32wb_serial_dmarxint(struct uart_dev_s *dev, bool enable) ****************************************************************************/ #ifdef SERIAL_HAVE_RXDMA -static bool stm32wb_serial_dmarxavailable(struct uart_dev_s *dev) +static bool stm32_serial_dmarxavailable(struct uart_dev_s *dev) { - struct stm32wb_serial_s *priv = (struct stm32wb_serial_s *)dev->priv; + struct stm32_serial_s *priv = (struct stm32_serial_s *)dev->priv; /* Compare our receive pointer to the current DMA pointer, if they * do not match, then there are bytes to be received. */ - return (stm32wb_serial_dmanextrx(priv) != priv->rxdmanext); + return (stm32_serial_dmanextrx(priv) != priv->rxdmanext); } #endif /**************************************************************************** - * Name: stm32wb_serial_send + * Name: stm32_serial_send * * Description: * This method will send one byte on the USART * ****************************************************************************/ -static void stm32wb_serial_send(struct uart_dev_s *dev, int ch) +static void stm32_serial_send(struct uart_dev_s *dev, int ch) { - struct stm32wb_serial_s *priv = (struct stm32wb_serial_s *)dev->priv; + struct stm32_serial_s *priv = (struct stm32_serial_s *)dev->priv; #ifdef HAVE_RS485 if (priv->rs485_dir_gpio != 0) { - stm32wb_gpiowrite(priv->rs485_dir_gpio, priv->rs485_dir_polarity); + stm32_gpiowrite(priv->rs485_dir_gpio, priv->rs485_dir_polarity); } #endif - stm32wb_serial_putreg(priv, STM32WB_USART_TDR_OFFSET, (uint32_t)ch); + stm32_serial_putreg(priv, STM32_USART_TDR_OFFSET, (uint32_t)ch); } /**************************************************************************** - * Name: stm32wb_serial_txint + * Name: stm32_serial_txint * * Description: * Call to enable or disable TX interrupts * ****************************************************************************/ -static void stm32wb_serial_txint(struct uart_dev_s *dev, bool enable) +static void stm32_serial_txint(struct uart_dev_s *dev, bool enable) { - struct stm32wb_serial_s *priv = (struct stm32wb_serial_s *)dev->priv; + struct stm32_serial_s *priv = (struct stm32_serial_s *)dev->priv; irqstate_t flags; @@ -2444,7 +2444,7 @@ static void stm32wb_serial_txint(struct uart_dev_s *dev, bool enable) } # endif -# ifdef CONFIG_STM32WB_SERIALBRK_BSDCOMPAT +# ifdef CONFIG_STM32_SERIALBRK_BSDCOMPAT if (priv->ie & USART_CR1_IE_BREAK_INPROGRESS) { leave_critical_section(flags); @@ -2452,7 +2452,7 @@ static void stm32wb_serial_txint(struct uart_dev_s *dev, bool enable) } # endif - stm32wb_serial_restoreusartint(priv, ie); + stm32_serial_restoreusartint(priv, ie); /* Fake a TX interrupt here by just calling uart_xmitchars() with * interrupts disabled (note this may recurse). @@ -2465,29 +2465,29 @@ static void stm32wb_serial_txint(struct uart_dev_s *dev, bool enable) { /* Disable the TX interrupt */ - stm32wb_serial_restoreusartint(priv, priv->ie & ~USART_CR1_TXEIE); + stm32_serial_restoreusartint(priv, priv->ie & ~USART_CR1_TXEIE); } leave_critical_section(flags); } /**************************************************************************** - * Name: stm32wb_serial_txready + * Name: stm32_serial_txready * * Description: * Return true if the transmit data register is empty * ****************************************************************************/ -static bool stm32wb_serial_txready(struct uart_dev_s *dev) +static bool stm32_serial_txready(struct uart_dev_s *dev) { - struct stm32wb_serial_s *priv = (struct stm32wb_serial_s *)dev->priv; - return ((stm32wb_serial_getreg(priv, STM32WB_USART_ISR_OFFSET) & + struct stm32_serial_s *priv = (struct stm32_serial_s *)dev->priv; + return ((stm32_serial_getreg(priv, STM32_USART_ISR_OFFSET) & USART_ISR_TXE) != 0); } /**************************************************************************** - * Name: stm32wb_serial_dmarxcallback + * Name: stm32_serial_dmarxcallback * * Description: * This function checks the current DMA state and calls the generic @@ -2496,12 +2496,12 @@ static bool stm32wb_serial_txready(struct uart_dev_s *dev) ****************************************************************************/ #ifdef SERIAL_HAVE_RXDMA -static void stm32wb_serial_dmarxcallback(DMA_HANDLE handle, uint8_t status, +static void stm32_serial_dmarxcallback(DMA_HANDLE handle, uint8_t status, void *arg) { - struct stm32wb_serial_s *priv = (struct stm32wb_serial_s *)arg; + struct stm32_serial_s *priv = (struct stm32_serial_s *)arg; - if (priv->rxenable && stm32wb_serial_dmarxavailable(&priv->dev)) + if (priv->rxenable && stm32_serial_dmarxavailable(&priv->dev)) { uart_recvchars(&priv->dev); @@ -2510,7 +2510,7 @@ static void stm32wb_serial_dmarxcallback(DMA_HANDLE handle, uint8_t status, { /* Re-enable RX DMA. */ - stm32wb_serial_dmaiflowrestart(priv); + stm32_serial_dmaiflowrestart(priv); } #endif } @@ -2525,11 +2525,11 @@ static void stm32wb_serial_dmarxcallback(DMA_HANDLE handle, uint8_t status, * will release Rx DMA. */ - priv->sr = stm32wb_serial_getreg(priv, STM32WB_USART_ISR_OFFSET); + priv->sr = stm32_serial_getreg(priv, STM32_USART_ISR_OFFSET); if ((priv->sr & (USART_ISR_ORE | USART_ISR_NE | USART_ISR_FE)) != 0) { - stm32wb_serial_putreg(priv, STM32WB_USART_ICR_OFFSET, + stm32_serial_putreg(priv, STM32_USART_ICR_OFFSET, (USART_ICR_NCF | USART_ICR_ORECF | USART_ICR_FECF)); } @@ -2537,7 +2537,7 @@ static void stm32wb_serial_dmarxcallback(DMA_HANDLE handle, uint8_t status, #endif /**************************************************************************** - * Name: stm32wb_serial_pmnotify + * Name: stm32_serial_pmnotify * * Description: * Notify the driver of new power state. This callback is called after @@ -2559,17 +2559,17 @@ static void stm32wb_serial_dmarxcallback(DMA_HANDLE handle, uint8_t status, ****************************************************************************/ #ifdef CONFIG_PM -static void stm32wb_serial_pmnotify(struct pm_callback_s *cb, int domain, +static void stm32_serial_pmnotify(struct pm_callback_s *cb, int domain, enum pm_state_e pmstate) { switch (pmstate) { case PM_NORMAL: - stm32wb_serial_pm_setsuspend(false); + stm32_serial_pm_setsuspend(false); break; case PM_IDLE: - stm32wb_serial_pm_setsuspend(false); + stm32_serial_pm_setsuspend(false); break; case PM_STANDBY: @@ -2579,11 +2579,11 @@ static void stm32wb_serial_pmnotify(struct pm_callback_s *cb, int domain, * Rx/Tx buffers are empty (checked in pmprepare). */ - stm32wb_serial_pm_setsuspend(true); + stm32_serial_pm_setsuspend(true); break; case PM_SLEEP: - stm32wb_serial_pm_setsuspend(true); + stm32_serial_pm_setsuspend(true); break; default: @@ -2594,7 +2594,7 @@ static void stm32wb_serial_pmnotify(struct pm_callback_s *cb, int domain, #endif /**************************************************************************** - * Name: stm32wb_serial_pmprepare + * Name: stm32_serial_pmprepare * * Description: * Request the driver to prepare for a new power state. This is a warning @@ -2627,7 +2627,7 @@ static void stm32wb_serial_pmnotify(struct pm_callback_s *cb, int domain, ****************************************************************************/ #ifdef CONFIG_PM -static int stm32wb_serial_pmprepare(struct pm_callback_s *cb, int domain, +static int stm32_serial_pmprepare(struct pm_callback_s *cb, int domain, enum pm_state_e pmstate) { int n; @@ -2648,16 +2648,16 @@ static int stm32wb_serial_pmprepare(struct pm_callback_s *cb, int domain, * buffers. */ - stm32wb_serial_dma_poll(); + stm32_serial_dma_poll(); #endif /* Check if any of the active ports have data pending on Tx/Rx * buffers. */ - for (n = 0; n < STM32WB_NLPUART + STM32WB_NUSART; n++) + for (n = 0; n < STM32_NLPUART + STM32_NUSART; n++) { - struct stm32wb_serial_s *priv = g_uart_devs[n]; + struct stm32_serial_s *priv = g_uart_devs[n]; if (!priv || !priv->initialized) { @@ -2723,18 +2723,18 @@ void arm_earlyserialinit(void) /* Disable all USART interrupts */ - for (i = 0; i < STM32WB_NLPUART + STM32WB_NUSART; i++) + for (i = 0; i < STM32_NLPUART + STM32_NUSART; i++) { if (g_uart_devs[i]) { - stm32wb_serial_disableusartint(g_uart_devs[i], NULL); + stm32_serial_disableusartint(g_uart_devs[i], NULL); } } /* Configure whichever one is the console */ #if CONSOLE_UART > 0 - stm32wb_serial_setup(&g_uart_devs[CONSOLE_UART - 1]->dev); + stm32_serial_setup(&g_uart_devs[CONSOLE_UART - 1]->dev); #endif #endif /* HAVE UART */ } @@ -2767,7 +2767,7 @@ void arm_serialinit(void) #if CONSOLE_UART > 0 uart_register("/dev/console", &g_uart_devs[CONSOLE_UART - 1]->dev); -#ifndef CONFIG_STM32WB_SERIAL_DISABLE_REORDERING +#ifndef CONFIG_STM32_SERIAL_DISABLE_REORDERING /* If not disabled, register the console UART to ttyS0 and exclude * it from initializing it further down */ @@ -2779,7 +2779,7 @@ void arm_serialinit(void) #ifdef SERIAL_HAVE_CONSOLE_DMA /* If we need to re-initialise the console to enable DMA do that here. */ - stm32wb_serial_dmasetup(&g_uart_devs[CONSOLE_UART - 1]->dev); + stm32_serial_dmasetup(&g_uart_devs[CONSOLE_UART - 1]->dev); #endif #endif /* CONSOLE_UART > 0 */ @@ -2787,7 +2787,7 @@ void arm_serialinit(void) strlcpy(devname, "/dev/ttySx", sizeof(devname)); - for (i = 0; i < STM32WB_NLPUART + STM32WB_NUSART; i++) + for (i = 0; i < STM32_NLPUART + STM32_NUSART; i++) { /* Don't create a device for non-configured ports. */ @@ -2796,7 +2796,7 @@ void arm_serialinit(void) continue; } -#ifndef CONFIG_STM32WB_SERIAL_DISABLE_REORDERING +#ifndef CONFIG_STM32_SERIAL_DISABLE_REORDERING /* Don't create a device for the console - we did that above */ if (g_uart_devs[i]->dev.isconsole) @@ -2814,7 +2814,7 @@ void arm_serialinit(void) } /**************************************************************************** - * Name: stm32wb_serial_dma_poll + * Name: stm32_serial_dma_poll * * Description: * Checks receive DMA buffers for received bytes that have not accumulated @@ -2825,7 +2825,7 @@ void arm_serialinit(void) ****************************************************************************/ #ifdef SERIAL_HAVE_RXDMA -void stm32wb_serial_dma_poll(void) +void stm32_serial_dma_poll(void) { irqstate_t flags; @@ -2834,14 +2834,14 @@ void stm32wb_serial_dma_poll(void) #ifdef CONFIG_LPUART1_RXDMA if (g_lpuart1priv.rxdma != NULL) { - stm32wb_serial_dmarxcallback(g_lpuart1priv.rxdma, 0, &g_lpuart1priv); + stm32_serial_dmarxcallback(g_lpuart1priv.rxdma, 0, &g_lpuart1priv); } #endif #ifdef CONFIG_USART1_RXDMA if (g_usart1priv.rxdma != NULL) { - stm32wb_serial_dmarxcallback(g_usart1priv.rxdma, 0, &g_usart1priv); + stm32_serial_dmarxcallback(g_usart1priv.rxdma, 0, &g_usart1priv); } #endif @@ -2860,12 +2860,12 @@ void stm32wb_serial_dma_poll(void) void up_putc(int ch) { #if CONSOLE_UART > 0 - struct stm32wb_serial_s *priv = g_uart_devs[CONSOLE_UART - 1]; + struct stm32_serial_s *priv = g_uart_devs[CONSOLE_UART - 1]; uint16_t ie; - stm32wb_serial_disableusartint(priv, &ie); + stm32_serial_disableusartint(priv, &ie); arm_lowputc(ch); - stm32wb_serial_restoreusartint(priv, ie); + stm32_serial_restoreusartint(priv, ie); #endif } diff --git a/arch/arm/src/stm32wb/stm32wb_spi.c b/arch/arm/src/stm32wb/stm32wb_spi.c index 7666a72f780c0..515f98920ab11 100644 --- a/arch/arm/src/stm32wb/stm32wb_spi.c +++ b/arch/arm/src/stm32wb/stm32wb_spi.c @@ -21,22 +21,22 @@ ****************************************************************************/ /**************************************************************************** - * The external functions, stm32wb_spi1/2select and stm32wb_spi1/2status + * The external functions, stm32_spi1/2select and stm32_spi1/2status * must be provided by board-specific logic. They are implementations of the * select and status methods of the SPI interface defined by struct spi_ops_s * (see include/nuttx/spi/spi.h). All other methods (including - * stm32wb_spibus_initialize()) are provided by common STM32 logic. To use + * stm32_spibus_initialize()) are provided by common STM32 logic. To use * this common SPI logic on your board: * - * 1. Provide logic in stm32wb_board_initialize() to configure SPI chip + * 1. Provide logic in stm32_board_initialize() to configure SPI chip * select pins. - * 2. Provide stm32wb_spi1/2select() and stm32wb_spi1/2status() + * 2. Provide stm32_spi1/2select() and stm32_spi1/2status() * functions in your board-specific logic. These functions will perform * chip selection and status operations using GPIOs in the way your * board is configured. - * 3. Add a calls to stm32wb_spibus_initialize() in your low level + * 3. Add a calls to stm32_spibus_initialize() in your low level * application initialization logic - * 4. The handle returned by stm32wb_spibus_initialize() may then be used + * 4. The handle returned by stm32_spibus_initialize() may then be used * to bind the SPI driver to higher level logic (e.g., calling * mmcsd_spislotinitialize(), for example, will bind the SPI driver to * the SPI MMC/SD driver). @@ -73,14 +73,14 @@ #include "arm_internal.h" #include "chip.h" -#include "stm32wb.h" +#include "stm32.h" #include "stm32wb_gpio.h" #include "stm32wb_dma.h" #include "stm32wb_spi.h" #include -#if defined(CONFIG_STM32WB_SPI1) || defined(CONFIG_STM32WB_SPI2) +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) /**************************************************************************** * Pre-processor Definitions @@ -90,19 +90,19 @@ /* SPI interrupts */ -#ifdef CONFIG_STM32WB_SPI_INTERRUPTS +#ifdef CONFIG_STM32_SPI_INTERRUPTS # error "Interrupt driven SPI not yet supported" #endif /* Can't have both interrupt driven SPI and SPI DMA */ -#if defined(CONFIG_STM32WB_SPI_INTERRUPTS) && defined(CONFIG_STM32WB_SPI_DMA) +#if defined(CONFIG_STM32_SPI_INTERRUPTS) && defined(CONFIG_STM32_SPI_DMA) # error "Cannot enable both interrupt mode and DMA mode for SPI" #endif /* SPI DMA priority */ -#ifdef CONFIG_STM32WB_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA # if defined(CONFIG_SPI_DMAPRIO) # define SPI_DMA_PRIO CONFIG_SPI_DMAPRIO @@ -131,15 +131,15 @@ * Private Types ****************************************************************************/ -struct stm32wb_spidev_s +struct stm32_spidev_s { struct spi_dev_s spidev; /* Externally visible part of the SPI interface */ uint32_t spibase; /* SPIn base address */ uint32_t spiclock; /* Clocking for the SPI module */ -#ifdef CONFIG_STM32WB_SPI_INTERRUPTS +#ifdef CONFIG_STM32_SPI_INTERRUPTS uint8_t spiirq; /* SPI IRQ number */ #endif -#ifdef CONFIG_STM32WB_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA volatile uint8_t rxresult; /* Result of the RX DMA */ volatile uint8_t txresult; /* Result of the RX DMA */ #ifdef CONFIG_SPI_TRIGGER @@ -172,34 +172,34 @@ struct stm32wb_spidev_s /* Helpers */ -static inline uint16_t spi_getreg(struct stm32wb_spidev_s *priv, +static inline uint16_t spi_getreg(struct stm32_spidev_s *priv, uint8_t offset); -static inline void spi_putreg(struct stm32wb_spidev_s *priv, +static inline void spi_putreg(struct stm32_spidev_s *priv, uint8_t offset, uint16_t value); -static inline uint16_t spi_readword(struct stm32wb_spidev_s *priv); -static inline void spi_writeword(struct stm32wb_spidev_s *priv, +static inline uint16_t spi_readword(struct stm32_spidev_s *priv); +static inline void spi_writeword(struct stm32_spidev_s *priv, uint16_t byte); -static inline bool spi_16bitmode(struct stm32wb_spidev_s *priv); +static inline bool spi_16bitmode(struct stm32_spidev_s *priv); /* DMA support */ -#ifdef CONFIG_STM32WB_SPI_DMA -static int spi_dmarxwait(struct stm32wb_spidev_s *priv); -static int spi_dmatxwait(struct stm32wb_spidev_s *priv); -static inline void spi_dmarxwakeup(struct stm32wb_spidev_s *priv); -static inline void spi_dmatxwakeup(struct stm32wb_spidev_s *priv); +#ifdef CONFIG_STM32_SPI_DMA +static int spi_dmarxwait(struct stm32_spidev_s *priv); +static int spi_dmatxwait(struct stm32_spidev_s *priv); +static inline void spi_dmarxwakeup(struct stm32_spidev_s *priv); +static inline void spi_dmatxwakeup(struct stm32_spidev_s *priv); static void spi_dmarxcallback(DMA_HANDLE handle, uint8_t isr, void *arg); static void spi_dmatxcallback(DMA_HANDLE handle, uint8_t isr, void *arg); -static void spi_dmarxsetup(struct stm32wb_spidev_s *priv, +static void spi_dmarxsetup(struct stm32_spidev_s *priv, void *rxbuffer, void *rxdummy, size_t nwords); -static void spi_dmatxsetup(struct stm32wb_spidev_s *priv, +static void spi_dmatxsetup(struct stm32_spidev_s *priv, const void *txbuffer, const void *txdummy, size_t nwords); -static inline void spi_dmarxstart(struct stm32wb_spidev_s *priv); -static inline void spi_dmatxstart(struct stm32wb_spidev_s *priv); +static inline void spi_dmarxstart(struct stm32_spidev_s *priv); +static inline void spi_dmatxstart(struct stm32_spidev_s *priv); #endif /* SPI methods */ @@ -230,7 +230,7 @@ static void spi_recvblock(struct spi_dev_s *dev, /* Initialization */ -static void spi_bus_initialize(struct stm32wb_spidev_s *priv); +static void spi_bus_initialize(struct stm32_spidev_s *priv); /* PM interface */ @@ -243,20 +243,20 @@ static int spi_pm_prepare(struct pm_callback_s *cb, int domain, * Private Data ****************************************************************************/ -#ifdef CONFIG_STM32WB_SPI1 +#ifdef CONFIG_STM32_SPI1 static const struct spi_ops_s g_spi1ops = { .lock = spi_lock, - .select = stm32wb_spi1select, + .select = stm32_spi1select, .setfrequency = spi_setfrequency, .setmode = spi_setmode, .setbits = spi_setbits, #ifdef CONFIG_SPI_HWFEATURES .hwfeatures = spi_hwfeatures, #endif - .status = stm32wb_spi1status, + .status = stm32_spi1status, #ifdef CONFIG_SPI_CMDDATA - .cmddata = stm32wb_spi1cmddata, + .cmddata = stm32_spi1cmddata, #endif .send = spi_send, #ifdef CONFIG_SPI_EXCHANGE @@ -269,24 +269,24 @@ static const struct spi_ops_s g_spi1ops = .trigger = spi_trigger, #endif #ifdef CONFIG_SPI_CALLBACK - .registercallback = stm32wb_spi1register, /* Provided externally */ + .registercallback = stm32_spi1register, /* Provided externally */ #else .registercallback = 0, /* Not implemented */ #endif }; -static struct stm32wb_spidev_s g_spi1dev = +static struct stm32_spidev_s g_spi1dev = { .spidev = { .ops = &g_spi1ops, }, - .spibase = STM32WB_SPI1_BASE, - .spiclock = STM32WB_PCLK2_FREQUENCY, -#ifdef CONFIG_STM32WB_SPI_INTERRUPTS - .spiirq = STM32WB_IRQ_SPI1, + .spibase = STM32_SPI1_BASE, + .spiclock = STM32_PCLK2_FREQUENCY, +#ifdef CONFIG_STM32_SPI_INTERRUPTS + .spiirq = STM32_IRQ_SPI1, #endif -#ifdef CONFIG_STM32WB_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA /* lines must be configured in board.h */ .rxch = DMAMAP_SPI1_RX, @@ -301,20 +301,20 @@ static struct stm32wb_spidev_s g_spi1dev = }; #endif -#ifdef CONFIG_STM32WB_SPI2 +#ifdef CONFIG_STM32_SPI2 static const struct spi_ops_s g_spi2ops = { .lock = spi_lock, - .select = stm32wb_spi2select, + .select = stm32_spi2select, .setfrequency = spi_setfrequency, .setmode = spi_setmode, .setbits = spi_setbits, #ifdef CONFIG_SPI_HWFEATURES .hwfeatures = spi_hwfeatures, #endif - .status = stm32wb_spi2status, + .status = stm32_spi2status, #ifdef CONFIG_SPI_CMDDATA - .cmddata = stm32wb_spi2cmddata, + .cmddata = stm32_spi2cmddata, #endif .send = spi_send, #ifdef CONFIG_SPI_EXCHANGE @@ -327,24 +327,24 @@ static const struct spi_ops_s g_spi2ops = .trigger = spi_trigger, #endif #ifdef CONFIG_SPI_CALLBACK - .registercallback = stm32wb_spi2register, /* provided externally */ + .registercallback = stm32_spi2register, /* provided externally */ #else .registercallback = 0, /* not implemented */ #endif }; -static struct stm32wb_spidev_s g_spi2dev = +static struct stm32_spidev_s g_spi2dev = { .spidev = { .ops = &g_spi2ops, }, - .spibase = STM32WB_SPI2_BASE, - .spiclock = STM32WB_PCLK1_FREQUENCY, -#ifdef CONFIG_STM32WB_SPI_INTERRUPTS - .spiirq = STM32WB_IRQ_SPI2, + .spibase = STM32_SPI2_BASE, + .spiclock = STM32_PCLK1_FREQUENCY, +#ifdef CONFIG_STM32_SPI_INTERRUPTS + .spiirq = STM32_IRQ_SPI2, #endif -#ifdef CONFIG_STM32WB_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA .rxch = DMACHAN_SPI2_RX, .txch = DMACHAN_SPI2_TX, .rxsem = SEM_INITIALIZER(0), @@ -376,7 +376,7 @@ static struct stm32wb_spidev_s g_spi2dev = * ****************************************************************************/ -static inline uint16_t spi_getreg(struct stm32wb_spidev_s *priv, +static inline uint16_t spi_getreg(struct stm32_spidev_s *priv, uint8_t offset) { return getreg16(priv->spibase + offset); @@ -398,7 +398,7 @@ static inline uint16_t spi_getreg(struct stm32wb_spidev_s *priv, * ****************************************************************************/ -static inline void spi_putreg(struct stm32wb_spidev_s *priv, +static inline void spi_putreg(struct stm32_spidev_s *priv, uint8_t offset, uint16_t value) { putreg16(value, priv->spibase + offset); @@ -419,7 +419,7 @@ static inline void spi_putreg(struct stm32wb_spidev_s *priv, * ****************************************************************************/ -static inline uint8_t spi_getreg8(struct stm32wb_spidev_s *priv, +static inline uint8_t spi_getreg8(struct stm32_spidev_s *priv, uint8_t offset) { return getreg8(priv->spibase + offset); @@ -438,7 +438,7 @@ static inline uint8_t spi_getreg8(struct stm32wb_spidev_s *priv, * ****************************************************************************/ -static inline void spi_putreg8(struct stm32wb_spidev_s *priv, +static inline void spi_putreg8(struct stm32_spidev_s *priv, uint8_t offset, uint8_t value) { putreg8(value, priv->spibase + offset); @@ -458,15 +458,15 @@ static inline void spi_putreg8(struct stm32wb_spidev_s *priv, * ****************************************************************************/ -static inline uint16_t spi_readword(struct stm32wb_spidev_s *priv) +static inline uint16_t spi_readword(struct stm32_spidev_s *priv) { /* Wait until the receive buffer is not empty */ - while ((spi_getreg(priv, STM32WB_SPI_SR_OFFSET) & SPI_SR_RXNE) == 0); + while ((spi_getreg(priv, STM32_SPI_SR_OFFSET) & SPI_SR_RXNE) == 0); /* Then return the received byte */ - return spi_getreg(priv, STM32WB_SPI_DR_OFFSET); + return spi_getreg(priv, STM32_SPI_DR_OFFSET); } /**************************************************************************** @@ -483,15 +483,15 @@ static inline uint16_t spi_readword(struct stm32wb_spidev_s *priv) * ****************************************************************************/ -static inline uint8_t spi_readbyte(struct stm32wb_spidev_s *priv) +static inline uint8_t spi_readbyte(struct stm32_spidev_s *priv) { /* Wait until the receive buffer is not empty */ - while ((spi_getreg(priv, STM32WB_SPI_SR_OFFSET) & SPI_SR_RXNE) == 0); + while ((spi_getreg(priv, STM32_SPI_SR_OFFSET) & SPI_SR_RXNE) == 0); /* Then return the received byte */ - return spi_getreg8(priv, STM32WB_SPI_DR_OFFSET); + return spi_getreg8(priv, STM32_SPI_DR_OFFSET); } /**************************************************************************** @@ -509,16 +509,16 @@ static inline uint8_t spi_readbyte(struct stm32wb_spidev_s *priv) * ****************************************************************************/ -static inline void spi_writeword(struct stm32wb_spidev_s *priv, +static inline void spi_writeword(struct stm32_spidev_s *priv, uint16_t word) { /* Wait until the transmit buffer is empty */ - while ((spi_getreg(priv, STM32WB_SPI_SR_OFFSET) & SPI_SR_TXE) == 0); + while ((spi_getreg(priv, STM32_SPI_SR_OFFSET) & SPI_SR_TXE) == 0); /* Then send the byte */ - spi_putreg(priv, STM32WB_SPI_DR_OFFSET, word); + spi_putreg(priv, STM32_SPI_DR_OFFSET, word); } /**************************************************************************** @@ -536,16 +536,16 @@ static inline void spi_writeword(struct stm32wb_spidev_s *priv, * ****************************************************************************/ -static inline void spi_writebyte(struct stm32wb_spidev_s *priv, +static inline void spi_writebyte(struct stm32_spidev_s *priv, uint8_t byte) { /* Wait until the transmit buffer is empty */ - while ((spi_getreg(priv, STM32WB_SPI_SR_OFFSET) & SPI_SR_TXE) == 0); + while ((spi_getreg(priv, STM32_SPI_SR_OFFSET) & SPI_SR_TXE) == 0); /* Then send the byte */ - spi_putreg8(priv, STM32WB_SPI_DR_OFFSET, byte); + spi_putreg8(priv, STM32_SPI_DR_OFFSET, byte); } /**************************************************************************** @@ -562,7 +562,7 @@ static inline void spi_writebyte(struct stm32wb_spidev_s *priv, * ****************************************************************************/ -static inline bool spi_16bitmode(struct stm32wb_spidev_s *priv) +static inline bool spi_16bitmode(struct stm32_spidev_s *priv) { return (priv->nbits > 8); } @@ -575,8 +575,8 @@ static inline bool spi_16bitmode(struct stm32wb_spidev_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32WB_SPI_DMA -static int spi_dmarxwait(struct stm32wb_spidev_s *priv) +#ifdef CONFIG_STM32_SPI_DMA +static int spi_dmarxwait(struct stm32_spidev_s *priv) { int ret; @@ -608,8 +608,8 @@ static int spi_dmarxwait(struct stm32wb_spidev_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32WB_SPI_DMA -static int spi_dmatxwait(struct stm32wb_spidev_s *priv) +#ifdef CONFIG_STM32_SPI_DMA +static int spi_dmatxwait(struct stm32_spidev_s *priv) { int ret; @@ -641,8 +641,8 @@ static int spi_dmatxwait(struct stm32wb_spidev_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32WB_SPI_DMA -static inline void spi_dmarxwakeup(struct stm32wb_spidev_s *priv) +#ifdef CONFIG_STM32_SPI_DMA +static inline void spi_dmarxwakeup(struct stm32_spidev_s *priv) { nxsem_post(&priv->rxsem); } @@ -656,8 +656,8 @@ static inline void spi_dmarxwakeup(struct stm32wb_spidev_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32WB_SPI_DMA -static inline void spi_dmatxwakeup(struct stm32wb_spidev_s *priv) +#ifdef CONFIG_STM32_SPI_DMA +static inline void spi_dmatxwakeup(struct stm32_spidev_s *priv) { nxsem_post(&priv->txsem); } @@ -671,10 +671,10 @@ static inline void spi_dmatxwakeup(struct stm32wb_spidev_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32WB_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_dmarxcallback(DMA_HANDLE handle, uint8_t isr, void *arg) { - struct stm32wb_spidev_s *priv = (struct stm32wb_spidev_s *)arg; + struct stm32_spidev_s *priv = (struct stm32_spidev_s *)arg; /* Wake-up the SPI driver */ @@ -691,10 +691,10 @@ static void spi_dmarxcallback(DMA_HANDLE handle, uint8_t isr, void *arg) * ****************************************************************************/ -#ifdef CONFIG_STM32WB_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_dmatxcallback(DMA_HANDLE handle, uint8_t isr, void *arg) { - struct stm32wb_spidev_s *priv = (struct stm32wb_spidev_s *)arg; + struct stm32_spidev_s *priv = (struct stm32_spidev_s *)arg; /* Wake-up the SPI driver */ @@ -711,8 +711,8 @@ static void spi_dmatxcallback(DMA_HANDLE handle, uint8_t isr, void *arg) * ****************************************************************************/ -#ifdef CONFIG_STM32WB_SPI_DMA -static void spi_dmarxsetup(struct stm32wb_spidev_s *priv, +#ifdef CONFIG_STM32_SPI_DMA +static void spi_dmarxsetup(struct stm32_spidev_s *priv, void *rxbuffer, void *rxdummy, size_t nwords) { /* 8- or 16-bit mode? */ @@ -748,7 +748,7 @@ static void spi_dmarxsetup(struct stm32wb_spidev_s *priv, /* Configure the RX DMA */ - stm32wb_dmasetup(priv->rxdma, priv->spibase + STM32WB_SPI_DR_OFFSET, + stm32_dmasetup(priv->rxdma, priv->spibase + STM32_SPI_DR_OFFSET, (uint32_t)rxbuffer, nwords, priv->rxccr); } #endif @@ -761,8 +761,8 @@ static void spi_dmarxsetup(struct stm32wb_spidev_s *priv, * ****************************************************************************/ -#ifdef CONFIG_STM32WB_SPI_DMA -static void spi_dmatxsetup(struct stm32wb_spidev_s *priv, +#ifdef CONFIG_STM32_SPI_DMA +static void spi_dmatxsetup(struct stm32_spidev_s *priv, const void *txbuffer, const void *txdummy, size_t nwords) { @@ -799,7 +799,7 @@ static void spi_dmatxsetup(struct stm32wb_spidev_s *priv, /* Setup the TX DMA */ - stm32wb_dmasetup(priv->txdma, priv->spibase + STM32WB_SPI_DR_OFFSET, + stm32_dmasetup(priv->txdma, priv->spibase + STM32_SPI_DR_OFFSET, (uint32_t)txbuffer, nwords, priv->txccr); } #endif @@ -812,11 +812,11 @@ static void spi_dmatxsetup(struct stm32wb_spidev_s *priv, * ****************************************************************************/ -#ifdef CONFIG_STM32WB_SPI_DMA -static inline void spi_dmarxstart(struct stm32wb_spidev_s *priv) +#ifdef CONFIG_STM32_SPI_DMA +static inline void spi_dmarxstart(struct stm32_spidev_s *priv) { priv->rxresult = 0; - stm32wb_dmastart(priv->rxdma, spi_dmarxcallback, priv, false); + stm32_dmastart(priv->rxdma, spi_dmarxcallback, priv, false); } #endif @@ -828,11 +828,11 @@ static inline void spi_dmarxstart(struct stm32wb_spidev_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32WB_SPI_DMA -static inline void spi_dmatxstart(struct stm32wb_spidev_s *priv) +#ifdef CONFIG_STM32_SPI_DMA +static inline void spi_dmatxstart(struct stm32_spidev_s *priv) { priv->txresult = 0; - stm32wb_dmastart(priv->txdma, spi_dmatxcallback, priv, false); + stm32_dmastart(priv->txdma, spi_dmatxcallback, priv, false); } #endif @@ -852,7 +852,7 @@ static inline void spi_dmatxstart(struct stm32wb_spidev_s *priv) * ****************************************************************************/ -static void spi_modifycr(uint32_t addr, struct stm32wb_spidev_s *priv, +static void spi_modifycr(uint32_t addr, struct stm32_spidev_s *priv, uint16_t setbits, uint16_t clrbits) { uint16_t cr; @@ -886,7 +886,7 @@ static void spi_modifycr(uint32_t addr, struct stm32wb_spidev_s *priv, static int spi_lock(struct spi_dev_s *dev, bool lock) { - struct stm32wb_spidev_s *priv = (struct stm32wb_spidev_s *)dev; + struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev; int ret; if (lock) @@ -918,15 +918,15 @@ static int spi_lock(struct spi_dev_s *dev, bool lock) static uint32_t spi_setfrequency(struct spi_dev_s *dev, uint32_t frequency) { - struct stm32wb_spidev_s *priv = (struct stm32wb_spidev_s *)dev; + struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev; uint16_t setbits; uint32_t actual; - /* Limit to max possible (if STM32WB_SPI_CLK_MAX is defined in board.h) */ + /* Limit to max possible (if STM32_SPI_CLK_MAX is defined in board.h) */ - if (frequency > STM32WB_SPI_CLK_MAX) + if (frequency > STM32_SPI_CLK_MAX) { - frequency = STM32WB_SPI_CLK_MAX; + frequency = STM32_SPI_CLK_MAX; } /* Has the frequency changed? */ @@ -992,9 +992,9 @@ static uint32_t spi_setfrequency(struct spi_dev_s *dev, uint32_t frequency) actual = priv->spiclock >> 8; } - spi_modifycr(STM32WB_SPI_CR1_OFFSET, priv, 0, SPI_CR1_SPE); - spi_modifycr(STM32WB_SPI_CR1_OFFSET, priv, setbits, SPI_CR1_BR_MASK); - spi_modifycr(STM32WB_SPI_CR1_OFFSET, priv, SPI_CR1_SPE, 0); + spi_modifycr(STM32_SPI_CR1_OFFSET, priv, 0, SPI_CR1_SPE); + spi_modifycr(STM32_SPI_CR1_OFFSET, priv, setbits, SPI_CR1_BR_MASK); + spi_modifycr(STM32_SPI_CR1_OFFSET, priv, SPI_CR1_SPE, 0); /* Save the frequency selection so that subsequent reconfigurations * will be faster. @@ -1026,7 +1026,7 @@ static uint32_t spi_setfrequency(struct spi_dev_s *dev, uint32_t frequency) static void spi_setmode(struct spi_dev_s *dev, enum spi_mode_e mode) { - struct stm32wb_spidev_s *priv = (struct stm32wb_spidev_s *)dev; + struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev; uint16_t setbits; uint16_t clrbits; @@ -1064,9 +1064,9 @@ static void spi_setmode(struct spi_dev_s *dev, enum spi_mode_e mode) return; } - spi_modifycr(STM32WB_SPI_CR1_OFFSET, priv, 0, SPI_CR1_SPE); - spi_modifycr(STM32WB_SPI_CR1_OFFSET, priv, setbits, clrbits); - spi_modifycr(STM32WB_SPI_CR1_OFFSET, priv, SPI_CR1_SPE, 0); + spi_modifycr(STM32_SPI_CR1_OFFSET, priv, 0, SPI_CR1_SPE); + spi_modifycr(STM32_SPI_CR1_OFFSET, priv, setbits, clrbits); + spi_modifycr(STM32_SPI_CR1_OFFSET, priv, SPI_CR1_SPE, 0); /* Save the mode so that subsequent re-configurations will be * faster. @@ -1094,7 +1094,7 @@ static void spi_setmode(struct spi_dev_s *dev, enum spi_mode_e mode) static void spi_setbits(struct spi_dev_s *dev, int nbits) { - struct stm32wb_spidev_s *priv = (struct stm32wb_spidev_s *)dev; + struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev; uint16_t setbits; uint16_t clrbits; @@ -1130,9 +1130,9 @@ static void spi_setbits(struct spi_dev_s *dev, int nbits) clrbits |= SPI_CR2_FRXTH; /* RX FIFO Threshold = 2 bytes */ } - spi_modifycr(STM32WB_SPI_CR1_OFFSET, priv, 0, SPI_CR1_SPE); - spi_modifycr(STM32WB_SPI_CR2_OFFSET, priv, setbits, clrbits); - spi_modifycr(STM32WB_SPI_CR1_OFFSET, priv, SPI_CR1_SPE, 0); + spi_modifycr(STM32_SPI_CR1_OFFSET, priv, 0, SPI_CR1_SPE); + spi_modifycr(STM32_SPI_CR2_OFFSET, priv, setbits, clrbits); + spi_modifycr(STM32_SPI_CR1_OFFSET, priv, SPI_CR1_SPE, 0); /* Save the selection so that subsequent re-configurations will be * faster. @@ -1162,7 +1162,7 @@ static void spi_setbits(struct spi_dev_s *dev, int nbits) static int spi_hwfeatures(struct spi_dev_s *dev, spi_hwfeatures_t features) { #if defined(CONFIG_SPI_BITORDER) || defined(CONFIG_SPI_TRIGGER) - struct stm32wb_spidev_s *priv = (struct stm32wb_spidev_s *)dev; + struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev; #endif #ifdef CONFIG_SPI_BITORDER @@ -1184,9 +1184,9 @@ static int spi_hwfeatures(struct spi_dev_s *dev, spi_hwfeatures_t features) clrbits = SPI_CR1_LSBFIRST; } - spi_modifycr(STM32WB_SPI_CR1_OFFSET, priv, 0, SPI_CR1_SPE); - spi_modifycr(STM32WB_SPI_CR1_OFFSET, priv, setbits, clrbits); - spi_modifycr(STM32WB_SPI_CR1_OFFSET, priv, SPI_CR1_SPE, 0); + spi_modifycr(STM32_SPI_CR1_OFFSET, priv, 0, SPI_CR1_SPE); + spi_modifycr(STM32_SPI_CR1_OFFSET, priv, setbits, clrbits); + spi_modifycr(STM32_SPI_CR1_OFFSET, priv, SPI_CR1_SPE, 0); features &= ~HWFEAT_LSBFIRST; #endif @@ -1226,7 +1226,7 @@ static int spi_hwfeatures(struct spi_dev_s *dev, spi_hwfeatures_t features) static uint32_t spi_send(struct spi_dev_s *dev, uint32_t wd) { - struct stm32wb_spidev_s *priv = (struct stm32wb_spidev_s *)dev; + struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev; uint32_t regval; uint32_t ret; @@ -1252,7 +1252,7 @@ static uint32_t spi_send(struct spi_dev_s *dev, uint32_t wd) * flags). */ - regval = spi_getreg(priv, STM32WB_SPI_SR_OFFSET); + regval = spi_getreg(priv, STM32_SPI_SR_OFFSET); if (spi_16bitmode(priv)) { @@ -1290,8 +1290,8 @@ static uint32_t spi_send(struct spi_dev_s *dev, uint32_t wd) * ****************************************************************************/ -#if !defined(CONFIG_STM32WB_SPI_DMA) || defined(CONFIG_STM32WB_DMACAPABLE) -#if !defined(CONFIG_STM32WB_SPI_DMA) +#if !defined(CONFIG_STM32_SPI_DMA) || defined(CONFIG_STM32_DMACAPABLE) +#if !defined(CONFIG_STM32_SPI_DMA) static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, void *rxbuffer, size_t nwords) #else @@ -1300,7 +1300,7 @@ static void spi_exchange_nodma(struct spi_dev_s *dev, size_t nwords) #endif { - struct stm32wb_spidev_s *priv = (struct stm32wb_spidev_s *)dev; + struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev; DEBUGASSERT(priv && priv->spibase); spiinfo("txbuffer=%p rxbuffer=%p nwords=%d\n", txbuffer, rxbuffer, nwords); @@ -1374,7 +1374,7 @@ static void spi_exchange_nodma(struct spi_dev_s *dev, } } } -#endif /* !CONFIG_STM32WB_SPI_DMA || CONFIG_STM32WB_DMACAPABLE */ +#endif /* !CONFIG_STM32_SPI_DMA || CONFIG_STM32_DMACAPABLE */ /**************************************************************************** * Name: spi_exchange (with DMA capability) @@ -1397,18 +1397,18 @@ static void spi_exchange_nodma(struct spi_dev_s *dev, * ****************************************************************************/ -#ifdef CONFIG_STM32WB_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, void *rxbuffer, size_t nwords) { - struct stm32wb_spidev_s *priv = (struct stm32wb_spidev_s *)dev; + struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev; int ret; -#ifdef CONFIG_STM32WB_DMACAPABLE +#ifdef CONFIG_STM32_DMACAPABLE if ((txbuffer != NULL && - !stm32wb_dmacapable((uint32_t)txbuffer, nwords, priv->txccr)) || + !stm32_dmacapable((uint32_t)txbuffer, nwords, priv->txccr)) || (rxbuffer != NULL && - !stm32wb_dmacapable((uint32_t)rxbuffer, nwords, priv->rxccr))) + !stm32_dmacapable((uint32_t)rxbuffer, nwords, priv->rxccr))) { /* Unsupported memory region, fall back to non-DMA method. */ @@ -1466,7 +1466,7 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, #endif } } -#endif /* CONFIG_STM32WB_SPI_DMA */ +#endif /* CONFIG_STM32_SPI_DMA */ /**************************************************************************** * Name: spi_trigger @@ -1487,7 +1487,7 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, #ifdef CONFIG_SPI_TRIGGER static int spi_trigger(struct spi_dev_s *dev) { -#ifdef CONFIG_STM32WB_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev; if (!priv->trigarmed) @@ -1596,8 +1596,8 @@ static void spi_recvblock(struct spi_dev_s *dev, void *rxbuffer, static int spi_pm_prepare(struct pm_callback_s *cb, int domain, enum pm_state_e pmstate) { - struct stm32wb_spidev_s *priv = (struct stm32wb_spidev_s *)((char *)cb - - offsetof(struct stm32wb_spidev_s, pm_cb)); + struct stm32_spidev_s *priv = (struct stm32_spidev_s *)((char *)cb - + offsetof(struct stm32_spidev_s, pm_cb)); /* Logic to prepare for a reduced power state goes here. */ @@ -1647,7 +1647,7 @@ static int spi_pm_prepare(struct pm_callback_s *cb, int domain, * ****************************************************************************/ -static void spi_bus_initialize(struct stm32wb_spidev_s *priv) +static void spi_bus_initialize(struct stm32_spidev_s *priv) { uint16_t setbits; uint16_t clrbits; @@ -1670,11 +1670,11 @@ static void spi_bus_initialize(struct stm32wb_spidev_s *priv) SPI_CR1_LSBFIRST | SPI_CR1_RXONLY | SPI_CR1_BIDIOE | SPI_CR1_BIDIMODE; setbits = SPI_CR1_MSTR | SPI_CR1_SSI | SPI_CR1_SSM; - spi_modifycr(STM32WB_SPI_CR1_OFFSET, priv, setbits, clrbits); + spi_modifycr(STM32_SPI_CR1_OFFSET, priv, setbits, clrbits); clrbits = SPI_CR2_DS_MASK; setbits = SPI_CR2_DS_8BIT | SPI_CR2_FRXTH; /* FRXTH must be high in 8-bit mode */ - spi_modifycr(STM32WB_SPI_CR2_OFFSET, priv, setbits, clrbits); + spi_modifycr(STM32_SPI_CR2_OFFSET, priv, setbits, clrbits); priv->frequency = 0; priv->nbits = 8; @@ -1686,28 +1686,28 @@ static void spi_bus_initialize(struct stm32wb_spidev_s *priv) /* CRCPOLY configuration */ - spi_putreg(priv, STM32WB_SPI_CRCPR_OFFSET, 7); + spi_putreg(priv, STM32_SPI_CRCPR_OFFSET, 7); -#ifdef CONFIG_STM32WB_SPI_DMA - /* Get DMA channels. NOTE: stm32wb_dmachannel() will always assign the DMA - * channel. If the channel is not available, then stm32wb_dmachannel() +#ifdef CONFIG_STM32_SPI_DMA + /* Get DMA channels. NOTE: stm32_dmachannel() will always assign the DMA + * channel. If the channel is not available, then stm32_dmachannel() * will block and wait until the channel becomes available. WARNING: If * you have another device sharing a DMA channel with SPI and the code - * never releases that channel, then the call to stm32wb_dmachannel() will + * never releases that channel, then the call to stm32_dmachannel() will * hang forever in this function! Don't let your design do that! */ - priv->rxdma = stm32wb_dmachannel(priv->rxch); - priv->txdma = stm32wb_dmachannel(priv->txch); + priv->rxdma = stm32_dmachannel(priv->rxch); + priv->txdma = stm32_dmachannel(priv->txch); DEBUGASSERT(priv->rxdma && priv->txdma); - spi_modifycr(STM32WB_SPI_CR2_OFFSET, priv, + spi_modifycr(STM32_SPI_CR2_OFFSET, priv, SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN, 0); #endif /* Enable spi */ - spi_modifycr(STM32WB_SPI_CR1_OFFSET, priv, SPI_CR1_SPE, 0); + spi_modifycr(STM32_SPI_CR1_OFFSET, priv, SPI_CR1_SPE, 0); #ifdef CONFIG_PM /* Register to receive power management callbacks */ @@ -1723,7 +1723,7 @@ static void spi_bus_initialize(struct stm32wb_spidev_s *priv) ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_spibus_initialize + * Name: stm32_spibus_initialize * * Description: * Initialize the selected SPI bus @@ -1736,13 +1736,13 @@ static void spi_bus_initialize(struct stm32wb_spidev_s *priv) * ****************************************************************************/ -struct spi_dev_s *stm32wb_spibus_initialize(int bus) +struct spi_dev_s *stm32_spibus_initialize(int bus) { - struct stm32wb_spidev_s *priv = NULL; + struct stm32_spidev_s *priv = NULL; irqstate_t flags = enter_critical_section(); -#ifdef CONFIG_STM32WB_SPI1 +#ifdef CONFIG_STM32_SPI1 if (bus == 1) { /* Select SPI1 */ @@ -1755,9 +1755,9 @@ struct spi_dev_s *stm32wb_spibus_initialize(int bus) { /* Configure SPI1 pins: SCK, MISO, and MOSI */ - stm32wb_configgpio(GPIO_SPI1_SCK); - stm32wb_configgpio(GPIO_SPI1_MISO); - stm32wb_configgpio(GPIO_SPI1_MOSI); + stm32_configgpio(GPIO_SPI1_SCK); + stm32_configgpio(GPIO_SPI1_MISO); + stm32_configgpio(GPIO_SPI1_MOSI); /* Set up default configuration: Master, 8-bit, etc. */ @@ -1767,7 +1767,7 @@ struct spi_dev_s *stm32wb_spibus_initialize(int bus) } else #endif -#ifdef CONFIG_STM32WB_SPI2 +#ifdef CONFIG_STM32_SPI2 if (bus == 2) { /* Select SPI2 */ @@ -1780,9 +1780,9 @@ struct spi_dev_s *stm32wb_spibus_initialize(int bus) { /* Configure SPI2 pins: SCK, MISO, and MOSI */ - stm32wb_configgpio(GPIO_SPI2_SCK); - stm32wb_configgpio(GPIO_SPI2_MISO); - stm32wb_configgpio(GPIO_SPI2_MOSI); + stm32_configgpio(GPIO_SPI2_SCK); + stm32_configgpio(GPIO_SPI2_MISO); + stm32_configgpio(GPIO_SPI2_MOSI); /* Set up default configuration: Master, 8-bit, etc. */ @@ -1800,4 +1800,4 @@ struct spi_dev_s *stm32wb_spibus_initialize(int bus) return (struct spi_dev_s *)priv; } -#endif /* CONFIG_STM32WB_SPI1 || CONFIG_STM32WB_SPI2 */ +#endif /* CONFIG_STM32_SPI1 || CONFIG_STM32_SPI2 */ diff --git a/arch/arm/src/stm32wb/stm32wb_spi.h b/arch/arm/src/stm32wb/stm32wb_spi.h index f7998c56b6e12..cf19583f6263d 100644 --- a/arch/arm/src/stm32wb/stm32wb_spi.h +++ b/arch/arm/src/stm32wb/stm32wb_spi.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32WB_STM32WB_SPI_H -#define __ARCH_ARM_SRC_STM32WB_STM32WB_SPI_H +#ifndef __ARCH_ARM_SRC_STM32WB_STM32_SPI_H +#define __ARCH_ARM_SRC_STM32WB_STM32_SPI_H /**************************************************************************** * Included Files @@ -58,7 +58,7 @@ struct spi_dev_s; ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_spibus_initialize + * Name: stm32_spibus_initialize * * Description: * Initialize the selected SPI bus @@ -71,55 +71,55 @@ struct spi_dev_s; * ****************************************************************************/ -struct spi_dev_s *stm32wb_spibus_initialize(int bus); +struct spi_dev_s *stm32_spibus_initialize(int bus); /**************************************************************************** - * Name: stm32wb_spi1/2/...select and stm32wb_spi1/2/...status + * Name: stm32_spi1/2/...select and stm32_spi1/2/...status * * Description: - * The external functions, stm32wb_spi1/2/...select, - * stm32wb_spi1/2/...status, and stm32wb_spi1/2/...cmddata must be + * The external functions, stm32_spi1/2/...select, + * stm32_spi1/2/...status, and stm32_spi1/2/...cmddata must be * provided by board-specific logic. These are implementations of the * select, status, and cmddata methods of the SPI interface defined by * struct spi_ops_s (see include/nuttx/spi/spi.h). All other methods - * (including stm32wb_spibus_initialize()) are provided by common + * (including stm32_spibus_initialize()) are provided by common * STM32 logic. To use this common SPI logic on your board: * - * 1. Provide logic in stm32wb_board_initialize() to configure SPI chip + * 1. Provide logic in stm32_board_initialize() to configure SPI chip * select pins. - * 2. Provide stm32wb_spi1/2/...select() and stm32wb_spi1/2/...status() + * 2. Provide stm32_spi1/2/...select() and stm32_spi1/2/...status() * functions in your board-specific logic. These functions will perform * chip selection and status operations using GPIOs in the way your * board is configured. * 3. If CONFIG_SPI_CMDDATA is defined in your NuttX configuration file, - * then provide stm32wb_spi1/2/...cmddata() functions in your + * then provide stm32_spi1/2/...cmddata() functions in your * board-specific logic. These functions will perform cmd/data selection * operations using GPIOs in the way your board is configured. - * 4. Add a calls to stm32wb_spibus_initialize() in your low level + * 4. Add a calls to stm32_spibus_initialize() in your low level * application initialization logic - * 5. The handle returned by stm32wb_spibus_initialize() may then be used + * 5. The handle returned by stm32_spibus_initialize() may then be used * to bind the SPI driver to higher level logic (e.g., calling * mmcsd_spislotinitialize(), for example, will bind the SPI driver to * the SPI MMC/SD driver). * ****************************************************************************/ -#ifdef CONFIG_STM32WB_SPI1 -void stm32wb_spi1select(struct spi_dev_s *dev, +#ifdef CONFIG_STM32_SPI1 +void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, bool selected); -uint8_t stm32wb_spi1status(struct spi_dev_s *dev, uint32_t devid); -int stm32wb_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); +uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid); +int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); #endif -#ifdef CONFIG_STM32WB_SPI2 -void stm32wb_spi2select(struct spi_dev_s *dev, +#ifdef CONFIG_STM32_SPI2 +void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid, bool selected); -uint8_t stm32wb_spi2status(struct spi_dev_s *dev, uint32_t devid); -int stm32wb_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); +uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid); +int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); #endif /**************************************************************************** - * Name: stm32wb_spi1/2/...register + * Name: stm32_spi1/2/...register * * Description: * If the board supports a card detect callback to inform the SPI-based @@ -139,13 +139,13 @@ int stm32wb_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); ****************************************************************************/ #ifdef CONFIG_SPI_CALLBACK -#ifdef CONFIG_STM32WB_SPI1 -int stm32wb_spi1register(struct spi_dev_s *dev, spi_mediachange_t callback, +#ifdef CONFIG_STM32_SPI1 +int stm32_spi1register(struct spi_dev_s *dev, spi_mediachange_t callback, void *arg); #endif -#ifdef CONFIG_STM32WB_SPI2 -int stm32wb_spi2register(struct spi_dev_s *dev, spi_mediachange_t callback, +#ifdef CONFIG_STM32_SPI2 +int stm32_spi2register(struct spi_dev_s *dev, spi_mediachange_t callback, void *arg); #endif #endif @@ -156,4 +156,4 @@ int stm32wb_spi2register(struct spi_dev_s *dev, spi_mediachange_t callback, #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32WB_STM32WB_SPI_H */ +#endif /* __ARCH_ARM_SRC_STM32WB_STM32_SPI_H */ diff --git a/arch/arm/src/stm32wb/stm32wb_start.c b/arch/arm/src/stm32wb/stm32wb_start.c index 7ecd128a5c9d0..6e80fa7f6d87d 100644 --- a/arch/arm/src/stm32wb/stm32wb_start.c +++ b/arch/arm/src/stm32wb/stm32wb_start.c @@ -63,14 +63,14 @@ #define HEAP_BASE ((uintptr_t)_ebss + CONFIG_IDLETHREAD_STACKSIZE) -#ifdef CONFIG_STM32WB_SRAM2A_HEAP -# define SRAM2A_START (STM32WB_SRAM2A_BASE + CONFIG_STM32WB_SRAM2A_USER_BASE_OFFSET) -# define SRAM2A_END (SRAM2A_START + CONFIG_STM32WB_SRAM2A_USER_SIZE) +#ifdef CONFIG_STM32_SRAM2A_HEAP +# define SRAM2A_START (STM32_SRAM2A_BASE + CONFIG_STM32_SRAM2A_USER_BASE_OFFSET) +# define SRAM2A_END (SRAM2A_START + CONFIG_STM32_SRAM2A_USER_SIZE) #endif -#ifdef CONFIG_STM32WB_SRAM2B_HEAP -# define SRAM2B_START STM32WB_SRAM2B_BASE -# define SRAM2B_END (SRAM2B_START + CONFIG_STM32WB_SRAM2B_USER_SIZE) +#ifdef CONFIG_STM32_SRAM2B_HEAP +# define SRAM2B_START STM32_SRAM2B_BASE +# define SRAM2B_END (SRAM2B_START + CONFIG_STM32_SRAM2B_USER_SIZE) #endif /* g_idle_topstack: _sbss is the start of the BSS region as defined by the @@ -148,14 +148,14 @@ void __start(void) * using this memory for, say, additional heap space, then this is handy. */ -#ifdef CONFIG_STM32WB_SRAM2A_INIT +#ifdef CONFIG_STM32_SRAM2A_INIT for (dest = (uint32_t *)SRAM2A_START; dest < (uint32_t *)SRAM2A_END; ) { *dest++ = 0; } #endif -#ifdef CONFIG_STM32WB_SRAM2B_INIT +#ifdef CONFIG_STM32_SRAM2B_INIT for (dest = (uint32_t *)SRAM2B_START; dest < (uint32_t *)SRAM2B_END; ) { *dest++ = 0; @@ -164,15 +164,15 @@ void __start(void) /* Configure the UART so that we can get debug output as soon as possible */ - stm32wb_clockconfig(); -#ifdef CONFIG_STM32WB_IPCC - stm32wb_ipccreset(); + stm32_clockconfig(); +#ifdef CONFIG_STM32_IPCC + stm32_ipccreset(); #endif arm_fpuconfig(); - /* Todo: stm32wb_lowsetup(); */ + /* Todo: stm32_lowsetup(); */ - stm32wb_gpioinit(); + stm32_gpioinit(); showprogress('A'); /* Clear .bss. We'll do this inline (vs. calling memset) just to be @@ -223,13 +223,13 @@ void __start(void) */ #ifdef CONFIG_BUILD_PROTECTED - stm32wb_userspace(); + stm32_userspace(); showprogress('E'); #endif /* Initialize onboard resources */ - stm32wb_board_initialize(); + stm32_board_initialize(); showprogress('F'); /* Then start NuttX */ diff --git a/arch/arm/src/stm32wb/stm32wb_start.h b/arch/arm/src/stm32wb/stm32wb_start.h index e59d2843c56fd..7e9b47cd2523a 100644 --- a/arch/arm/src/stm32wb/stm32wb_start.h +++ b/arch/arm/src/stm32wb/stm32wb_start.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32WB_STM32WB_START_H -#define __ARCH_ARM_SRC_STM32WB_STM32WB_START_H +#ifndef __ARCH_ARM_SRC_STM32WB_STM32_START_H +#define __ARCH_ARM_SRC_STM32WB_STM32_START_H /**************************************************************************** * Included Files @@ -32,7 +32,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_board_initialize + * Name: stm32_board_initialize * * Description: * All STM32WB architectures must provide the following entry point. This @@ -42,6 +42,6 @@ * ****************************************************************************/ -void stm32wb_board_initialize(void); +void stm32_board_initialize(void); -#endif /* __ARCH_ARM_SRC_STM32WB_STM32WB_START_H */ +#endif /* __ARCH_ARM_SRC_STM32WB_STM32_START_H */ diff --git a/arch/arm/src/stm32wb/stm32wb_tickless.c b/arch/arm/src/stm32wb/stm32wb_tickless.c index ef5e64b5f60da..a8ae84dc54e3d 100644 --- a/arch/arm/src/stm32wb/stm32wb_tickless.c +++ b/arch/arm/src/stm32wb/stm32wb_tickless.c @@ -52,7 +52,7 @@ * There are two interrupts generated from our timer, the overflow interrupt * which drives the timing handler and the capture/compare interrupt which * drives the interval handler. There are some low level timer control - * functions implemented here because the API of stm32wb_tim.c does not + * functions implemented here because the API of stm32_tim.c does not * provide adequate control over capture/compare interrupts. * ****************************************************************************/ @@ -84,25 +84,25 @@ #undef HAVE_32BIT_TICKLESS -#ifdef CONFIG_STM32WB_TICKLESS_TIMER -# if CONFIG_STM32WB_TICKLESS_TIMER == 2 +#ifdef CONFIG_STM32_TICKLESS_TIMER +# if CONFIG_STM32_TICKLESS_TIMER == 2 # define HAVE_32BIT_TICKLESS 1 # endif #else -# error "STM32WB_TICKLESS_TIMER must be defined for tickless configuration" +# error "STM32_TICKLESS_TIMER must be defined for tickless configuration" #endif /**************************************************************************** * Private Types ****************************************************************************/ -struct stm32wb_tickless_s +struct stm32_tickless_s { uint8_t timer; /* The timer/counter in use */ uint8_t channel; /* The timer channel to use * for intervals */ - struct stm32wb_tim_dev_s *tch; /* Pointer returned by - * stm32wb_tim_init() */ + struct stm32_tim_dev_s *tch; /* Pointer returned by + * stm32_tim_init() */ uint32_t frequency; uint32_t overflow; /* Timer counter overflow */ volatile bool pending; /* True: pending task */ @@ -114,98 +114,98 @@ struct stm32wb_tickless_s * Private Data ****************************************************************************/ -static struct stm32wb_tickless_s g_tickless; +static struct stm32_tickless_s g_tickless; /**************************************************************************** * Private Functions ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_getreg16 + * Name: stm32_getreg16 * * Description: * Get a 16-bit register value by offset * ****************************************************************************/ -static inline uint16_t stm32wb_getreg16(uint8_t offset) +static inline uint16_t stm32_getreg16(uint8_t offset) { return getreg16(g_tickless.base + offset); } /**************************************************************************** - * Name: stm32wb_putreg16 + * Name: stm32_putreg16 * * Description: * Put a 16-bit register value by offset * ****************************************************************************/ -static inline void stm32wb_putreg16(uint8_t offset, uint16_t value) +static inline void stm32_putreg16(uint8_t offset, uint16_t value) { putreg16(value, g_tickless.base + offset); } /**************************************************************************** - * Name: stm32wb_modifyreg16 + * Name: stm32_modifyreg16 * * Description: * Modify a 16-bit register value by offset * ****************************************************************************/ -static inline void stm32wb_modifyreg16(uint8_t offset, uint16_t clearbits, +static inline void stm32_modifyreg16(uint8_t offset, uint16_t clearbits, uint16_t setbits) { modifyreg16(g_tickless.base + offset, clearbits, setbits); } /**************************************************************************** - * Name: stm32wb_tickless_enableint + * Name: stm32_tickless_enableint ****************************************************************************/ -static inline void stm32wb_tickless_enableint(int channel) +static inline void stm32_tickless_enableint(int channel) { - stm32wb_modifyreg16(STM32WB_TIM_DIER_OFFSET, 0, 1 << channel); + stm32_modifyreg16(STM32_TIM_DIER_OFFSET, 0, 1 << channel); } /**************************************************************************** - * Name: stm32wb_tickless_disableint + * Name: stm32_tickless_disableint ****************************************************************************/ -static inline void stm32wb_tickless_disableint(int channel) +static inline void stm32_tickless_disableint(int channel) { - stm32wb_modifyreg16(STM32WB_TIM_DIER_OFFSET, 1 << channel, 0); + stm32_modifyreg16(STM32_TIM_DIER_OFFSET, 1 << channel, 0); } /**************************************************************************** - * Name: stm32wb_tickless_ackint + * Name: stm32_tickless_ackint ****************************************************************************/ -static inline void stm32wb_tickless_ackint(int channel) +static inline void stm32_tickless_ackint(int channel) { - stm32wb_putreg16(STM32WB_TIM_SR_OFFSET, ~(1 << channel)); + stm32_putreg16(STM32_TIM_SR_OFFSET, ~(1 << channel)); } /**************************************************************************** - * Name: stm32wb_tickless_getint + * Name: stm32_tickless_getint ****************************************************************************/ -static inline uint16_t stm32wb_tickless_getint(void) +static inline uint16_t stm32_tickless_getint(void) { - return stm32wb_getreg16(STM32WB_TIM_SR_OFFSET); + return stm32_getreg16(STM32_TIM_SR_OFFSET); } /**************************************************************************** - * Name: stm32wb_tickless_setchannel + * Name: stm32_tickless_setchannel ****************************************************************************/ -static int stm32wb_tickless_setchannel(uint8_t channel) +static int stm32_tickless_setchannel(uint8_t channel) { uint16_t ccmr_orig = 0; uint16_t ccmr_val = 0; uint16_t ccer_val; - uint8_t ccmr_offset = STM32WB_TIM_CCMR1_OFFSET; + uint8_t ccmr_offset = STM32_TIM_CCMR1_OFFSET; /* Further we use range as 0..3; if channel=0 it will also overflow here */ @@ -216,7 +216,7 @@ static int stm32wb_tickless_setchannel(uint8_t channel) /* Assume that channel is disabled and polarity is active high */ - ccer_val = stm32wb_getreg16(STM32WB_TIM_CCER_OFFSET); + ccer_val = stm32_getreg16(STM32_TIM_CCER_OFFSET); ccer_val &= ~(GTIM_CCER_CCXE(channel) | GTIM_CCER_CCXP(channel)); /* Frozen mode because we don't want to change the GPIO, preload register @@ -231,20 +231,20 @@ static int stm32wb_tickless_setchannel(uint8_t channel) if (channel > 1) { - ccmr_offset = STM32WB_TIM_CCMR2_OFFSET; + ccmr_offset = STM32_TIM_CCMR2_OFFSET; } - ccmr_orig = stm32wb_getreg16(ccmr_offset); + ccmr_orig = stm32_getreg16(ccmr_offset); ccmr_orig &= ~(GTIM_CCMR_OCXM_MASK(channel) | GTIM_CCMR_OCXPE(channel)); ccmr_orig |= ccmr_val; - stm32wb_putreg16(ccmr_offset, ccmr_orig); - stm32wb_putreg16(STM32WB_TIM_CCER_OFFSET, ccer_val); + stm32_putreg16(ccmr_offset, ccmr_orig); + stm32_putreg16(STM32_TIM_CCER_OFFSET, ccer_val); return OK; } /**************************************************************************** - * Name: stm32wb_interval_handler + * Name: stm32_interval_handler * * Description: * Called when the timer counter matches the compare register @@ -261,14 +261,14 @@ static int stm32wb_tickless_setchannel(uint8_t channel) * ****************************************************************************/ -static void stm32wb_interval_handler(void) +static void stm32_interval_handler(void) { tmrinfo("Expired...\n"); /* Disable the compare interrupt now. */ - stm32wb_tickless_disableint(g_tickless.channel); - stm32wb_tickless_ackint(g_tickless.channel); + stm32_tickless_disableint(g_tickless.channel); + stm32_tickless_ackint(g_tickless.channel); g_tickless.pending = false; @@ -276,7 +276,7 @@ static void stm32wb_interval_handler(void) } /**************************************************************************** - * Name: stm32wb_timing_handler + * Name: stm32_timing_handler * * Description: * Timer interrupt callback. When the freerun timer counter overflows, @@ -290,15 +290,15 @@ static void stm32wb_interval_handler(void) * ****************************************************************************/ -static void stm32wb_timing_handler(void) +static void stm32_timing_handler(void) { g_tickless.overflow++; - STM32WB_TIM_ACKINT(g_tickless.tch, GTIM_SR_UIF); + STM32_TIM_ACKINT(g_tickless.tch, GTIM_SR_UIF); } /**************************************************************************** - * Name: stm32wb_tickless_handler + * Name: stm32_tickless_handler * * Description: * Generic interrupt handler for this timer. It checks the source of the @@ -312,18 +312,18 @@ static void stm32wb_timing_handler(void) * ****************************************************************************/ -static int stm32wb_tickless_handler(int irq, void *context, void *arg) +static int stm32_tickless_handler(int irq, void *context, void *arg) { - int interrupt_flags = stm32wb_tickless_getint(); + int interrupt_flags = stm32_tickless_getint(); if (interrupt_flags & GTIM_SR_UIF) { - stm32wb_timing_handler(); + stm32_timing_handler(); } if (interrupt_flags & (1 << g_tickless.channel)) { - stm32wb_interval_handler(); + stm32_interval_handler(); } return OK; @@ -360,29 +360,29 @@ static int stm32wb_tickless_handler(int irq, void *context, void *arg) void up_timer_initialize(void) { - switch (CONFIG_STM32WB_TICKLESS_TIMER) + switch (CONFIG_STM32_TICKLESS_TIMER) { -#ifdef CONFIG_STM32WB_TIM1 +#ifdef CONFIG_STM32_TIM1 case 1: - g_tickless.base = STM32WB_TIM1_BASE; + g_tickless.base = STM32_TIM1_BASE; break; #endif -#ifdef CONFIG_STM32WB_TIM2 +#ifdef CONFIG_STM32_TIM2 case 2: - g_tickless.base = STM32WB_TIM2_BASE; + g_tickless.base = STM32_TIM2_BASE; break; #endif -#ifdef CONFIG_STM32WB_TIM16 +#ifdef CONFIG_STM32_TIM16 case 16: - g_tickless.base = STM32WB_TIM16_BASE; + g_tickless.base = STM32_TIM16_BASE; break; #endif -#ifdef CONFIG_STM32WB_TIM17 +#ifdef CONFIG_STM32_TIM17 case 17: - g_tickless.base = STM32WB_TIM17_BASE; + g_tickless.base = STM32_TIM17_BASE; break; #endif @@ -393,8 +393,8 @@ void up_timer_initialize(void) /* Get the TC frequency that corresponds to the requested resolution */ g_tickless.frequency = USEC_PER_SEC / (uint32_t)CONFIG_USEC_PER_TICK; - g_tickless.timer = CONFIG_STM32WB_TICKLESS_TIMER; - g_tickless.channel = CONFIG_STM32WB_TICKLESS_CHANNEL; + g_tickless.timer = CONFIG_STM32_TICKLESS_TIMER; + g_tickless.channel = CONFIG_STM32_TICKLESS_CHANNEL; g_tickless.pending = false; g_tickless.period = 0; g_tickless.overflow = 0; @@ -402,36 +402,36 @@ void up_timer_initialize(void) tmrinfo("timer=%d channel=%d frequency=%lu Hz\n", g_tickless.timer, g_tickless.channel, g_tickless.frequency); - g_tickless.tch = stm32wb_tim_init(g_tickless.timer); + g_tickless.tch = stm32_tim_init(g_tickless.timer); if (!g_tickless.tch) { tmrerr("ERROR: Failed to allocate TIM%d\n", g_tickless.timer); DEBUGPANIC(); } - STM32WB_TIM_SETCLOCK(g_tickless.tch, g_tickless.frequency); + STM32_TIM_SETCLOCK(g_tickless.tch, g_tickless.frequency); /* Set up to receive the callback when the counter overflow occurs */ - STM32WB_TIM_SETISR(g_tickless.tch, stm32wb_tickless_handler, NULL, 0); + STM32_TIM_SETISR(g_tickless.tch, stm32_tickless_handler, NULL, 0); /* Initialize interval to zero */ - STM32WB_TIM_SETCOMPARE(g_tickless.tch, g_tickless.channel, 0); + STM32_TIM_SETCOMPARE(g_tickless.tch, g_tickless.channel, 0); /* Setup compare channel for the interval timing */ - stm32wb_tickless_setchannel(g_tickless.channel); + stm32_tickless_setchannel(g_tickless.channel); /* Set timer period */ #ifdef HAVE_32BIT_TICKLESS - STM32WB_TIM_SETPERIOD(g_tickless.tch, UINT32_MAX); + STM32_TIM_SETPERIOD(g_tickless.tch, UINT32_MAX); #ifdef CONFIG_SCHED_TICKLESS_LIMIT_MAX_SLEEP g_oneshot_maxticks = UINT32_MAX; #endif #else - STM32WB_TIM_SETPERIOD(g_tickless.tch, UINT16_MAX); + STM32_TIM_SETPERIOD(g_tickless.tch, UINT16_MAX); #ifdef CONFIG_SCHED_TICKLESS_LIMIT_MAX_SLEEP g_oneshot_maxticks = UINT16_MAX; #endif @@ -439,12 +439,12 @@ void up_timer_initialize(void) /* Initialize the counter */ - STM32WB_TIM_SETMODE(g_tickless.tch, STM32WB_TIM_MODE_UP); + STM32_TIM_SETMODE(g_tickless.tch, STM32_TIM_MODE_UP); /* Start the timer */ - STM32WB_TIM_ACKINT(g_tickless.tch, ~0); - STM32WB_TIM_ENABLEINT(g_tickless.tch, GTIM_DIER_UIE); + STM32_TIM_ACKINT(g_tickless.tch, ~0); + STM32_TIM_ENABLEINT(g_tickless.tch, GTIM_DIER_UIE); } /**************************************************************************** @@ -493,7 +493,7 @@ int up_timer_gettime(struct timespec *ts) DEBUGASSERT(g_tickless.tch && ts); /* Temporarily disable the overflow counter. NOTE that we have to be - * careful here because stm32wb_tc_getpending() will reset the pending + * careful here because stm32_tc_getpending() will reset the pending * interrupt status. If we do not handle the overflow here then, it will * be lost. */ @@ -501,9 +501,9 @@ int up_timer_gettime(struct timespec *ts) flags = enter_critical_section(); overflow = g_tickless.overflow; - counter = STM32WB_TIM_GETCOUNTER(g_tickless.tch); - pending = STM32WB_TIM_CHECKINT(g_tickless.tch, GTIM_SR_UIF); - verify = STM32WB_TIM_GETCOUNTER(g_tickless.tch); + counter = STM32_TIM_GETCOUNTER(g_tickless.tch); + pending = STM32_TIM_CHECKINT(g_tickless.tch, GTIM_SR_UIF); + verify = STM32_TIM_GETCOUNTER(g_tickless.tch); /* If an interrupt was pending before we re-enabled interrupts, * then the overflow needs to be incremented. @@ -511,7 +511,7 @@ int up_timer_gettime(struct timespec *ts) if (pending) { - STM32WB_TIM_ACKINT(g_tickless.tch, GTIM_SR_UIF); + STM32_TIM_ACKINT(g_tickless.tch, GTIM_SR_UIF); /* Increment the overflow count and use the value of the * guaranteed to be AFTER the overflow occurred. @@ -576,7 +576,7 @@ int up_timer_gettime(struct timespec *ts) int up_timer_gettick(clock_t *ticks) { - *ticks = STM32WB_TIM_GETCOUNTER(g_tickless.tch); + *ticks = STM32_TIM_GETCOUNTER(g_tickless.tch); return OK; } @@ -679,9 +679,9 @@ int up_timer_cancel(struct timespec *ts) /* Disable the interrupt. */ - stm32wb_tickless_disableint(g_tickless.channel); + stm32_tickless_disableint(g_tickless.channel); - count = STM32WB_TIM_GETCOUNTER(g_tickless.tch); + count = STM32_TIM_GETCOUNTER(g_tickless.tch); period = g_tickless.period; g_tickless.pending = false; @@ -807,7 +807,7 @@ int up_timer_start(const struct timespec *ts) */ period = (usec * (uint64_t)g_tickless.frequency) / USEC_PER_SEC; - count = STM32WB_TIM_GETCOUNTER(g_tickless.tch); + count = STM32_TIM_GETCOUNTER(g_tickless.tch); tmrinfo("usec=%llu period=%08llx\n", usec, period); @@ -822,15 +822,15 @@ int up_timer_start(const struct timespec *ts) g_tickless.period = (uint16_t)(period + count); #endif - STM32WB_TIM_SETCOMPARE(g_tickless.tch, g_tickless.channel, + STM32_TIM_SETCOMPARE(g_tickless.tch, g_tickless.channel, g_tickless.period); /* Enable interrupts. We should get the callback when the interrupt * occurs. */ - stm32wb_tickless_ackint(g_tickless.channel); - stm32wb_tickless_enableint(g_tickless.channel); + stm32_tickless_ackint(g_tickless.channel); + stm32_tickless_enableint(g_tickless.channel); g_tickless.pending = true; leave_critical_section(flags); diff --git a/arch/arm/src/stm32wb/stm32wb_tim.c b/arch/arm/src/stm32wb/stm32wb_tim.c index 9bc6340317bf0..22402ed4da183 100644 --- a/arch/arm/src/stm32wb/stm32wb_tim.c +++ b/arch/arm/src/stm32wb/stm32wb_tim.c @@ -37,7 +37,7 @@ #include "arm_internal.h" #include "chip.h" -#include "stm32wb.h" +#include "stm32.h" #include "stm32wb_tim.h" #include "stm32wb_gpio.h" #include "stm32wb_rcc.h" @@ -52,63 +52,63 @@ * Such special purposes include: * * - To generate modulated outputs for such things as motor control. If - * CONFIG_STM32WB_TIMn is defined then the CONFIG_STM32WB_TIMn_PWM may also + * CONFIG_STM32_TIMn is defined then the CONFIG_STM32_TIMn_PWM may also * be defined to indicate that the timer is intended to be used for pulsed * output modulation. * - * - To control periodic ADC input sampling. If CONFIG_STM32WB_TIMn is - * defined then CONFIG_STM32WB_TIMn_ADC may also be defined to indicate + * - To control periodic ADC input sampling. If CONFIG_STM32_TIMn is + * defined then CONFIG_STM32_TIMn_ADC may also be defined to indicate * that timer "n" is intended to be used for that purpose. * - * - To use a Quadrature Encoder. If CONFIG_STM32WB_TIMn is defined then - * CONFIG_STM32WB_TIMn_QE may also be defined to indicate that timer "n" + * - To use a Quadrature Encoder. If CONFIG_STM32_TIMn is defined then + * CONFIG_STM32_TIMn_QE may also be defined to indicate that timer "n" * is intended to be used for that purpose. * * In any of these cases, the timer will not be used by this timer module. */ -#if defined(CONFIG_STM32WB_TIM1_PWM) || defined (CONFIG_STM32WB_TIM1_ADC) || \ - defined(CONFIG_STM32WB_TIM1_QE) -# undef CONFIG_STM32WB_TIM1 +#if defined(CONFIG_STM32_TIM1_PWM) || defined (CONFIG_STM32_TIM1_ADC) || \ + defined(CONFIG_STM32_TIM1_QE) +# undef CONFIG_STM32_TIM1 #endif -#if defined(CONFIG_STM32WB_TIM2_PWM) || defined (CONFIG_STM32WB_TIM2_ADC) || \ - defined(CONFIG_STM32WB_TIM2_QE) -# undef CONFIG_STM32WB_TIM2 +#if defined(CONFIG_STM32_TIM2_PWM) || defined (CONFIG_STM32_TIM2_ADC) || \ + defined(CONFIG_STM32_TIM2_QE) +# undef CONFIG_STM32_TIM2 #endif -#if defined(CONFIG_STM32WB_TIM16_PWM) || defined (CONFIG_STM32WB_TIM16_ADC) || \ - defined(CONFIG_STM32WB_TIM16_QE) -# undef CONFIG_STM32WB_TIM16 +#if defined(CONFIG_STM32_TIM16_PWM) || defined (CONFIG_STM32_TIM16_ADC) || \ + defined(CONFIG_STM32_TIM16_QE) +# undef CONFIG_STM32_TIM16 #endif -#if defined(CONFIG_STM32WB_TIM17_PWM) || defined (CONFIG_STM32WB_TIM17_ADC) || \ - defined(CONFIG_STM32WB_TIM17_QE) -# undef CONFIG_STM32WB_TIM17 +#if defined(CONFIG_STM32_TIM17_PWM) || defined (CONFIG_STM32_TIM17_ADC) || \ + defined(CONFIG_STM32_TIM17_QE) +# undef CONFIG_STM32_TIM17 #endif -#if defined(CONFIG_STM32WB_TIM1) +#if defined(CONFIG_STM32_TIM1) # if defined(GPIO_TIM1_CH1OUT) || defined(GPIO_TIM1_CH2OUT) || \ defined(GPIO_TIM1_CH3OUT) || defined(GPIO_TIM1_CH4OUT) # define HAVE_TIM1_GPIOCONFIG 1 #endif #endif -#if defined(CONFIG_STM32WB_TIM2) +#if defined(CONFIG_STM32_TIM2) # if defined(GPIO_TIM2_CH1OUT) || defined(GPIO_TIM2_CH2OUT) || \ defined(GPIO_TIM2_CH3OUT) || defined(GPIO_TIM2_CH4OUT) # define HAVE_TIM2_GPIOCONFIG 1 #endif #endif -#if defined(CONFIG_STM32WB_TIM16) +#if defined(CONFIG_STM32_TIM16) # if defined(GPIO_TIM16_CH1OUT) || defined(GPIO_TIM16_CH2OUT) || \ defined(GPIO_TIM16_CH3OUT) || defined(GPIO_TIM16_CH4OUT) # define HAVE_TIM16_GPIOCONFIG 1 #endif #endif -#if defined(CONFIG_STM32WB_TIM17) +#if defined(CONFIG_STM32_TIM17) # if defined(GPIO_TIM17_CH1OUT) || defined(GPIO_TIM17_CH2OUT) || \ defined(GPIO_TIM17_CH3OUT) || defined(GPIO_TIM17_CH4OUT) # define HAVE_TIM17_GPIOCONFIG 1 @@ -119,8 +119,8 @@ * intended for some other purpose. */ -#if defined(CONFIG_STM32WB_TIM1) || defined(CONFIG_STM32WB_TIM2) || \ - defined(CONFIG_STM32WB_TIM16) || defined(CONFIG_STM32WB_TIM17) +#if defined(CONFIG_STM32_TIM1) || defined(CONFIG_STM32_TIM2) || \ + defined(CONFIG_STM32_TIM16) || defined(CONFIG_STM32_TIM17) /**************************************************************************** * Private Types @@ -128,10 +128,10 @@ /* TIM Device Structure */ -struct stm32wb_tim_priv_s +struct stm32_tim_priv_s { - const struct stm32wb_tim_ops_s *ops; - enum stm32wb_tim_mode_e mode; + const struct stm32_tim_ops_s *ops; + enum stm32_tim_mode_e mode; uint32_t base; /* TIMn base address */ }; @@ -141,118 +141,118 @@ struct stm32wb_tim_priv_s /* Register helpers */ -static inline uint16_t stm32wb_getreg16(struct stm32wb_tim_dev_s *dev, +static inline uint16_t stm32_getreg16(struct stm32_tim_dev_s *dev, uint8_t offset); -static inline void stm32wb_putreg16(struct stm32wb_tim_dev_s *dev, +static inline void stm32_putreg16(struct stm32_tim_dev_s *dev, uint8_t offset, uint16_t value); -static inline void stm32wb_modifyreg16(struct stm32wb_tim_dev_s *dev, +static inline void stm32_modifyreg16(struct stm32_tim_dev_s *dev, uint8_t offset, uint16_t clearbits, uint16_t setbits); -static inline uint32_t stm32wb_getreg32(struct stm32wb_tim_dev_s *dev, +static inline uint32_t stm32_getreg32(struct stm32_tim_dev_s *dev, uint8_t offset); -static inline void stm32wb_putreg32(struct stm32wb_tim_dev_s *dev, +static inline void stm32_putreg32(struct stm32_tim_dev_s *dev, uint8_t offset, uint32_t value); /* Timer helpers */ -static void stm32wb_tim_reload_counter(struct stm32wb_tim_dev_s *dev); -static void stm32wb_tim_enable(struct stm32wb_tim_dev_s *dev); -static void stm32wb_tim_disable(struct stm32wb_tim_dev_s *dev); -static void stm32wb_tim_reset(struct stm32wb_tim_dev_s *dev); +static void stm32_tim_reload_counter(struct stm32_tim_dev_s *dev); +static void stm32_tim_enable(struct stm32_tim_dev_s *dev); +static void stm32_tim_disable(struct stm32_tim_dev_s *dev); +static void stm32_tim_reset(struct stm32_tim_dev_s *dev); #if defined(HAVE_TIM1_GPIOCONFIG) || defined(HAVE_TIM2_GPIOCONFIG) || \ defined(HAVE_TIM16_GPIOCONFIG) || defined(HAVE_TIM17_GPIOCONFIG) -static void stm32wb_tim_gpioconfig(uint32_t cfg, - enum stm32wb_tim_channel_e mode); +static void stm32_tim_gpioconfig(uint32_t cfg, + enum stm32_tim_channel_e mode); #endif -static void stm32wb_tim_dumpregs(struct stm32wb_tim_dev_s *dev); +static void stm32_tim_dumpregs(struct stm32_tim_dev_s *dev); /* Timer methods */ -static int stm32wb_tim_setmode(struct stm32wb_tim_dev_s *dev, - enum stm32wb_tim_mode_e mode); -static int stm32wb_tim_setfreq(struct stm32wb_tim_dev_s *dev, uint32_t freq); -static int stm32wb_tim_setclock(struct stm32wb_tim_dev_s *dev, +static int stm32_tim_setmode(struct stm32_tim_dev_s *dev, + enum stm32_tim_mode_e mode); +static int stm32_tim_setfreq(struct stm32_tim_dev_s *dev, uint32_t freq); +static int stm32_tim_setclock(struct stm32_tim_dev_s *dev, uint32_t freq); -static uint32_t stm32wb_tim_getclock(struct stm32wb_tim_dev_s *dev); -static void stm32wb_tim_setperiod(struct stm32wb_tim_dev_s *dev, +static uint32_t stm32_tim_getclock(struct stm32_tim_dev_s *dev); +static void stm32_tim_setperiod(struct stm32_tim_dev_s *dev, uint32_t period); -static uint32_t stm32wb_tim_getperiod(struct stm32wb_tim_dev_s *dev); -static uint32_t stm32wb_tim_getcounter(struct stm32wb_tim_dev_s *dev); -static uint32_t stm32wb_tim_getwidth(struct stm32wb_tim_dev_s *dev); -static int stm32wb_tim_setchannel(struct stm32wb_tim_dev_s *dev, +static uint32_t stm32_tim_getperiod(struct stm32_tim_dev_s *dev); +static uint32_t stm32_tim_getcounter(struct stm32_tim_dev_s *dev); +static uint32_t stm32_tim_getwidth(struct stm32_tim_dev_s *dev); +static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, uint8_t channel, - enum stm32wb_tim_channel_e mode); -static int stm32wb_tim_setcompare(struct stm32wb_tim_dev_s *dev, + enum stm32_tim_channel_e mode); +static int stm32_tim_setcompare(struct stm32_tim_dev_s *dev, uint8_t channel, uint32_t compare); -static uint32_t stm32wb_tim_getcapture(struct stm32wb_tim_dev_s *dev, +static uint32_t stm32_tim_getcapture(struct stm32_tim_dev_s *dev, uint8_t channel); -static int stm32wb_tim_setisr(struct stm32wb_tim_dev_s *dev, +static int stm32_tim_setisr(struct stm32_tim_dev_s *dev, xcpt_t handler, void *arg, int source); -static void stm32wb_tim_enableint(struct stm32wb_tim_dev_s *dev, int source); -static void stm32wb_tim_disableint(struct stm32wb_tim_dev_s *dev, +static void stm32_tim_enableint(struct stm32_tim_dev_s *dev, int source); +static void stm32_tim_disableint(struct stm32_tim_dev_s *dev, int source); -static void stm32wb_tim_ackint(struct stm32wb_tim_dev_s *dev, int source); -static int stm32wb_tim_checkint(struct stm32wb_tim_dev_s *dev, int source); +static void stm32_tim_ackint(struct stm32_tim_dev_s *dev, int source); +static int stm32_tim_checkint(struct stm32_tim_dev_s *dev, int source); /**************************************************************************** * Private Data ****************************************************************************/ -static const struct stm32wb_tim_ops_s stm32wb_tim_ops = +static const struct stm32_tim_ops_s stm32_tim_ops = { - .enable = stm32wb_tim_enable, - .disable = stm32wb_tim_disable, - .setmode = stm32wb_tim_setmode, - .setfreq = stm32wb_tim_setfreq, - .setclock = stm32wb_tim_setclock, - .getclock = stm32wb_tim_getclock, - .setperiod = stm32wb_tim_setperiod, - .getperiod = stm32wb_tim_getperiod, - .getcounter = stm32wb_tim_getcounter, - .getwidth = stm32wb_tim_getwidth, - .setchannel = stm32wb_tim_setchannel, - .setcompare = stm32wb_tim_setcompare, - .getcapture = stm32wb_tim_getcapture, - .setisr = stm32wb_tim_setisr, - .enableint = stm32wb_tim_enableint, - .disableint = stm32wb_tim_disableint, - .ackint = stm32wb_tim_ackint, - .checkint = stm32wb_tim_checkint, - .dump_regs = stm32wb_tim_dumpregs, + .enable = stm32_tim_enable, + .disable = stm32_tim_disable, + .setmode = stm32_tim_setmode, + .setfreq = stm32_tim_setfreq, + .setclock = stm32_tim_setclock, + .getclock = stm32_tim_getclock, + .setperiod = stm32_tim_setperiod, + .getperiod = stm32_tim_getperiod, + .getcounter = stm32_tim_getcounter, + .getwidth = stm32_tim_getwidth, + .setchannel = stm32_tim_setchannel, + .setcompare = stm32_tim_setcompare, + .getcapture = stm32_tim_getcapture, + .setisr = stm32_tim_setisr, + .enableint = stm32_tim_enableint, + .disableint = stm32_tim_disableint, + .ackint = stm32_tim_ackint, + .checkint = stm32_tim_checkint, + .dump_regs = stm32_tim_dumpregs, }; -#ifdef CONFIG_STM32WB_TIM1 -struct stm32wb_tim_priv_s stm32wb_tim1_priv = +#ifdef CONFIG_STM32_TIM1 +struct stm32_tim_priv_s stm32_tim1_priv = { - .ops = &stm32wb_tim_ops, - .mode = STM32WB_TIM_MODE_UNUSED, - .base = STM32WB_TIM1_BASE, + .ops = &stm32_tim_ops, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM1_BASE, }; #endif -#ifdef CONFIG_STM32WB_TIM2 -struct stm32wb_tim_priv_s stm32wb_tim2_priv = +#ifdef CONFIG_STM32_TIM2 +struct stm32_tim_priv_s stm32_tim2_priv = { - .ops = &stm32wb_tim_ops, - .mode = STM32WB_TIM_MODE_UNUSED, - .base = STM32WB_TIM2_BASE, + .ops = &stm32_tim_ops, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM2_BASE, }; #endif -#ifdef CONFIG_STM32WB_TIM16 -struct stm32wb_tim_priv_s stm32wb_tim16_priv = +#ifdef CONFIG_STM32_TIM16 +struct stm32_tim_priv_s stm32_tim16_priv = { - .ops = &stm32wb_tim_ops, - .mode = STM32WB_TIM_MODE_UNUSED, - .base = STM32WB_TIM16_BASE, + .ops = &stm32_tim_ops, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM16_BASE, }; #endif -#ifdef CONFIG_STM32WB_TIM17 -struct stm32wb_tim_priv_s stm32wb_tim17_priv = +#ifdef CONFIG_STM32_TIM17 +struct stm32_tim_priv_s stm32_tim17_priv = { - .ops = &stm32wb_tim_ops, - .mode = STM32WB_TIM_MODE_UNUSED, - .base = STM32WB_TIM17_BASE, + .ops = &stm32_tim_ops, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM17_BASE, }; #endif @@ -261,51 +261,51 @@ struct stm32wb_tim_priv_s stm32wb_tim17_priv = ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_getreg16 + * Name: stm32_getreg16 * * Description: * Get a 16-bit register value by offset * ****************************************************************************/ -static inline uint16_t stm32wb_getreg16(struct stm32wb_tim_dev_s *dev, +static inline uint16_t stm32_getreg16(struct stm32_tim_dev_s *dev, uint8_t offset) { - return getreg16(((struct stm32wb_tim_priv_s *)dev)->base + offset); + return getreg16(((struct stm32_tim_priv_s *)dev)->base + offset); } /**************************************************************************** - * Name: stm32wb_putreg16 + * Name: stm32_putreg16 * * Description: * Put a 16-bit register value by offset * ****************************************************************************/ -static inline void stm32wb_putreg16(struct stm32wb_tim_dev_s *dev, +static inline void stm32_putreg16(struct stm32_tim_dev_s *dev, uint8_t offset, uint16_t value) { - putreg16(value, ((struct stm32wb_tim_priv_s *)dev)->base + offset); + putreg16(value, ((struct stm32_tim_priv_s *)dev)->base + offset); } /**************************************************************************** - * Name: stm32wb_modifyreg16 + * Name: stm32_modifyreg16 * * Description: * Modify a 16-bit register value by offset * ****************************************************************************/ -static inline void stm32wb_modifyreg16(struct stm32wb_tim_dev_s *dev, +static inline void stm32_modifyreg16(struct stm32_tim_dev_s *dev, uint8_t offset, uint16_t clearbits, uint16_t setbits) { - modifyreg16(((struct stm32wb_tim_priv_s *)dev)->base + offset, clearbits, + modifyreg16(((struct stm32_tim_priv_s *)dev)->base + offset, clearbits, setbits); } /**************************************************************************** - * Name: stm32wb_getreg32 + * Name: stm32_getreg32 * * Description: * Get a 32-bit register value by offset. This applies only for the STM32WB @@ -313,14 +313,14 @@ static inline void stm32wb_modifyreg16(struct stm32wb_tim_dev_s *dev, * ****************************************************************************/ -static inline uint32_t stm32wb_getreg32(struct stm32wb_tim_dev_s *dev, +static inline uint32_t stm32_getreg32(struct stm32_tim_dev_s *dev, uint8_t offset) { - return getreg32(((struct stm32wb_tim_priv_s *)dev)->base + offset); + return getreg32(((struct stm32_tim_priv_s *)dev)->base + offset); } /**************************************************************************** - * Name: stm32wb_putreg32 + * Name: stm32_putreg32 * * Description: * Put a 32-bit register value by offset. This applies only for the STM32WB @@ -328,49 +328,49 @@ static inline uint32_t stm32wb_getreg32(struct stm32wb_tim_dev_s *dev, * ****************************************************************************/ -static inline void stm32wb_putreg32(struct stm32wb_tim_dev_s *dev, +static inline void stm32_putreg32(struct stm32_tim_dev_s *dev, uint8_t offset, uint32_t value) { - putreg32(value, ((struct stm32wb_tim_priv_s *)dev)->base + offset); + putreg32(value, ((struct stm32_tim_priv_s *)dev)->base + offset); } /**************************************************************************** - * Name: stm32wb_tim_reload_counter + * Name: stm32_tim_reload_counter ****************************************************************************/ -static void stm32wb_tim_reload_counter(struct stm32wb_tim_dev_s *dev) +static void stm32_tim_reload_counter(struct stm32_tim_dev_s *dev) { - uint16_t val = stm32wb_getreg16(dev, STM32WB_TIM_EGR_OFFSET); + uint16_t val = stm32_getreg16(dev, STM32_TIM_EGR_OFFSET); val |= GTIM_EGR_UG; - stm32wb_putreg16(dev, STM32WB_TIM_EGR_OFFSET, val); + stm32_putreg16(dev, STM32_TIM_EGR_OFFSET, val); } /**************************************************************************** - * Name: stm32wb_tim_enable + * Name: stm32_tim_enable ****************************************************************************/ -static void stm32wb_tim_enable(struct stm32wb_tim_dev_s *dev) +static void stm32_tim_enable(struct stm32_tim_dev_s *dev) { - uint16_t val = stm32wb_getreg16(dev, STM32WB_TIM_CR1_OFFSET); + uint16_t val = stm32_getreg16(dev, STM32_TIM_CR1_OFFSET); val |= GTIM_CR1_CEN; - stm32wb_tim_reload_counter(dev); - stm32wb_putreg16(dev, STM32WB_TIM_CR1_OFFSET, val); + stm32_tim_reload_counter(dev); + stm32_putreg16(dev, STM32_TIM_CR1_OFFSET, val); } /**************************************************************************** - * Name: stm32wb_tim_disable + * Name: stm32_tim_disable ****************************************************************************/ -static void stm32wb_tim_disable(struct stm32wb_tim_dev_s *dev) +static void stm32_tim_disable(struct stm32_tim_dev_s *dev) { - uint16_t val = stm32wb_getreg16(dev, STM32WB_TIM_CR1_OFFSET); + uint16_t val = stm32_getreg16(dev, STM32_TIM_CR1_OFFSET); val &= ~GTIM_CR1_CEN; - stm32wb_putreg16(dev, STM32WB_TIM_CR1_OFFSET, val); + stm32_putreg16(dev, STM32_TIM_CR1_OFFSET, val); } /**************************************************************************** - * Name: stm32wb_tim_reset + * Name: stm32_tim_reset * * Description: * Reset timer into system default state, but do not affect output/input @@ -378,86 +378,86 @@ static void stm32wb_tim_disable(struct stm32wb_tim_dev_s *dev) * ****************************************************************************/ -static void stm32wb_tim_reset(struct stm32wb_tim_dev_s *dev) +static void stm32_tim_reset(struct stm32_tim_dev_s *dev) { - ((struct stm32wb_tim_priv_s *)dev)->mode = STM32WB_TIM_MODE_DISABLED; - stm32wb_tim_disable(dev); + ((struct stm32_tim_priv_s *)dev)->mode = STM32_TIM_MODE_DISABLED; + stm32_tim_disable(dev); } /**************************************************************************** - * Name: stm32wb_tim_gpioconfig + * Name: stm32_tim_gpioconfig ****************************************************************************/ #if defined(HAVE_TIM1_GPIOCONFIG) || defined(HAVE_TIM2_GPIOCONFIG) || \ defined(HAVE_TIM16_GPIOCONFIG) || defined(HAVE_TIM17_GPIOCONFIG) -static void stm32wb_tim_gpioconfig(uint32_t cfg, - enum stm32wb_tim_channel_e mode) +static void stm32_tim_gpioconfig(uint32_t cfg, + enum stm32_tim_channel_e mode) { - if (mode & STM32WB_TIM_CH_MODE_MASK) + if (mode & STM32_TIM_CH_MODE_MASK) { - stm32wb_configgpio(cfg); + stm32_configgpio(cfg); } else { - stm32wb_unconfiggpio(cfg); + stm32_unconfiggpio(cfg); } } #endif /**************************************************************************** - * Name: stm32wb_tim_dumpregs + * Name: stm32_tim_dumpregs ****************************************************************************/ -static void stm32wb_tim_dumpregs(struct stm32wb_tim_dev_s *dev) +static void stm32_tim_dumpregs(struct stm32_tim_dev_s *dev) { - struct stm32wb_tim_priv_s *priv = (struct stm32wb_tim_priv_s *)dev; + struct stm32_tim_priv_s *priv = (struct stm32_tim_priv_s *)dev; ainfo(" CR1: %04x CR2: %04x SMCR: %04x DIER: %04x\n", - stm32wb_getreg16(dev, STM32WB_TIM_CR1_OFFSET), - stm32wb_getreg16(dev, STM32WB_TIM_CR2_OFFSET), - stm32wb_getreg16(dev, STM32WB_TIM_SMCR_OFFSET), - stm32wb_getreg16(dev, STM32WB_TIM_DIER_OFFSET) + stm32_getreg16(dev, STM32_TIM_CR1_OFFSET), + stm32_getreg16(dev, STM32_TIM_CR2_OFFSET), + stm32_getreg16(dev, STM32_TIM_SMCR_OFFSET), + stm32_getreg16(dev, STM32_TIM_DIER_OFFSET) ); ainfo(" SR: %04x EGR: 0000 CCMR1: %04x CCMR2: %04x\n", - stm32wb_getreg16(dev, STM32WB_TIM_SR_OFFSET), - stm32wb_getreg16(dev, STM32WB_TIM_CCMR1_OFFSET), - stm32wb_getreg16(dev, STM32WB_TIM_CCMR2_OFFSET) + stm32_getreg16(dev, STM32_TIM_SR_OFFSET), + stm32_getreg16(dev, STM32_TIM_CCMR1_OFFSET), + stm32_getreg16(dev, STM32_TIM_CCMR2_OFFSET) ); ainfo(" CCER: %04x CNT: %04x PSC: %04x ARR: %04x\n", - stm32wb_getreg16(dev, STM32WB_TIM_CCER_OFFSET), - stm32wb_getreg16(dev, STM32WB_TIM_CNT_OFFSET), - stm32wb_getreg16(dev, STM32WB_TIM_PSC_OFFSET), - stm32wb_getreg16(dev, STM32WB_TIM_ARR_OFFSET) + stm32_getreg16(dev, STM32_TIM_CCER_OFFSET), + stm32_getreg16(dev, STM32_TIM_CNT_OFFSET), + stm32_getreg16(dev, STM32_TIM_PSC_OFFSET), + stm32_getreg16(dev, STM32_TIM_ARR_OFFSET) ); ainfo(" CCR1: %04x CCR2: %04x CCR3: %04x CCR4: %04x\n", - stm32wb_getreg16(dev, STM32WB_TIM_CCR1_OFFSET), - stm32wb_getreg16(dev, STM32WB_TIM_CCR2_OFFSET), - stm32wb_getreg16(dev, STM32WB_TIM_CCR3_OFFSET), - stm32wb_getreg16(dev, STM32WB_TIM_CCR4_OFFSET) + stm32_getreg16(dev, STM32_TIM_CCR1_OFFSET), + stm32_getreg16(dev, STM32_TIM_CCR2_OFFSET), + stm32_getreg16(dev, STM32_TIM_CCR3_OFFSET), + stm32_getreg16(dev, STM32_TIM_CCR4_OFFSET) ); - if (priv->base == STM32WB_TIM1_BASE) + if (priv->base == STM32_TIM1_BASE) { ainfo(" RCR: %04x BDTR: %04x DCR: %04x DMAR: %04x\n", - stm32wb_getreg16(dev, STM32WB_TIM_RCR_OFFSET), - stm32wb_getreg16(dev, STM32WB_TIM_BDTR_OFFSET), - stm32wb_getreg16(dev, STM32WB_TIM_DCR_OFFSET), - stm32wb_getreg16(dev, STM32WB_TIM_DMAR_OFFSET)); + stm32_getreg16(dev, STM32_TIM_RCR_OFFSET), + stm32_getreg16(dev, STM32_TIM_BDTR_OFFSET), + stm32_getreg16(dev, STM32_TIM_DCR_OFFSET), + stm32_getreg16(dev, STM32_TIM_DMAR_OFFSET)); } else { ainfo(" DCR: %04x DMAR: %04x\n", - stm32wb_getreg16(dev, STM32WB_TIM_DCR_OFFSET), - stm32wb_getreg16(dev, STM32WB_TIM_DMAR_OFFSET)); + stm32_getreg16(dev, STM32_TIM_DCR_OFFSET), + stm32_getreg16(dev, STM32_TIM_DMAR_OFFSET)); } } /**************************************************************************** - * Name: stm32wb_tim_setmode + * Name: stm32_tim_setmode ****************************************************************************/ -static int stm32wb_tim_setmode(struct stm32wb_tim_dev_s *dev, - enum stm32wb_tim_mode_e mode) +static int stm32_tim_setmode(struct stm32_tim_dev_s *dev, + enum stm32_tim_mode_e mode) { uint16_t val; @@ -465,18 +465,18 @@ static int stm32wb_tim_setmode(struct stm32wb_tim_dev_s *dev, /* The modes DOWN and UPDOWN are not supported on TIM16 and TIM17. */ -#if defined(CONFIG_STM32WB_TIM16) || defined(CONFIG_STM32WB_TIM17) - if ((mode == STM32WB_TIM_MODE_DOWN || mode == STM32WB_TIM_MODE_UPDOWN)) +#if defined(CONFIG_STM32_TIM16) || defined(CONFIG_STM32_TIM17) + if ((mode == STM32_TIM_MODE_DOWN || mode == STM32_TIM_MODE_UPDOWN)) { -#if defined(CONFIG_STM32WB_TIM16) - if (((struct stm32wb_tim_priv_s *)dev)->base == STM32WB_TIM16_BASE) +#if defined(CONFIG_STM32_TIM16) + if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM16_BASE) { return -EINVAL; } #endif -#if defined(CONFIG_STM32WB_TIM17) - if (((struct stm32wb_tim_priv_s *)dev)->base == STM32WB_TIM17_BASE) +#if defined(CONFIG_STM32_TIM17) + if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM17_BASE) { return -EINVAL; } @@ -486,22 +486,22 @@ static int stm32wb_tim_setmode(struct stm32wb_tim_dev_s *dev, /* Decode operational modes */ - switch (mode & STM32WB_TIM_MODE_MASK) + switch (mode & STM32_TIM_MODE_MASK) { - case STM32WB_TIM_MODE_DISABLED: + case STM32_TIM_MODE_DISABLED: val = 0; break; - case STM32WB_TIM_MODE_UP: + case STM32_TIM_MODE_UP: val = GTIM_CR1_CEN | GTIM_CR1_ARPE; break; -#if defined(CONFIG_STM32WB_TIM1) || defined(CONFIG_STM32WB_TIM2) - case STM32WB_TIM_MODE_DOWN: +#if defined(CONFIG_STM32_TIM1) || defined(CONFIG_STM32_TIM2) + case STM32_TIM_MODE_DOWN: val = GTIM_CR1_CEN | GTIM_CR1_ARPE | TIM_1_2_CR1_DIR; break; - case STM32WB_TIM_MODE_UPDOWN: + case STM32_TIM_MODE_UPDOWN: val = GTIM_CR1_CEN | GTIM_CR1_ARPE | TIM_1_2_CR1_CMS_CNTR1; /* Our default: @@ -511,7 +511,7 @@ static int stm32wb_tim_setmode(struct stm32wb_tim_dev_s *dev, break; #endif - case STM32WB_TIM_MODE_PULSE: + case STM32_TIM_MODE_PULSE: val = GTIM_CR1_CEN | GTIM_CR1_ARPE | GTIM_CR1_OPM; break; @@ -519,15 +519,15 @@ static int stm32wb_tim_setmode(struct stm32wb_tim_dev_s *dev, return -EINVAL; } - stm32wb_tim_reload_counter(dev); - stm32wb_putreg16(dev, STM32WB_TIM_CR1_OFFSET, val); + stm32_tim_reload_counter(dev); + stm32_putreg16(dev, STM32_TIM_CR1_OFFSET, val); -#ifdef CONFIG_STM32WB_TIM1 +#ifdef CONFIG_STM32_TIM1 /* Advanced registers require Main Output Enable */ - if (((struct stm32wb_tim_priv_s *)dev)->base == STM32WB_TIM1_BASE) + if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM1_BASE) { - stm32wb_modifyreg16(dev, STM32WB_TIM_BDTR_OFFSET, 0, TIM1_BDTR_MOE); + stm32_modifyreg16(dev, STM32_TIM_BDTR_OFFSET, 0, TIM1_BDTR_MOE); } #endif @@ -535,10 +535,10 @@ static int stm32wb_tim_setmode(struct stm32wb_tim_dev_s *dev, } /**************************************************************************** - * Name: stm32wb_tim_setfreq + * Name: stm32_tim_setfreq ****************************************************************************/ -static int stm32wb_tim_setfreq(struct stm32wb_tim_dev_s *dev, uint32_t freq) +static int stm32_tim_setfreq(struct stm32_tim_dev_s *dev, uint32_t freq) { uint32_t freqin; int prescaler; @@ -551,7 +551,7 @@ static int stm32wb_tim_setfreq(struct stm32wb_tim_dev_s *dev, uint32_t freq) if (freq == 0) { - stm32wb_tim_disable(dev); + stm32_tim_disable(dev); return 0; } @@ -561,28 +561,28 @@ static int stm32wb_tim_setfreq(struct stm32wb_tim_dev_s *dev, uint32_t freq) * must be defined in the board.h header file. */ - switch (((struct stm32wb_tim_priv_s *)dev)->base) + switch (((struct stm32_tim_priv_s *)dev)->base) { -#ifdef CONFIG_STM32WB_TIM1 - case STM32WB_TIM1_BASE: +#ifdef CONFIG_STM32_TIM1 + case STM32_TIM1_BASE: freqin = BOARD_TIM1_FREQUENCY; break; #endif -#ifdef CONFIG_STM32WB_TIM2 - case STM32WB_TIM2_BASE: +#ifdef CONFIG_STM32_TIM2 + case STM32_TIM2_BASE: freqin = BOARD_TIM2_FREQUENCY; break; #endif -#ifdef CONFIG_STM32WB_TIM16 - case STM32WB_TIM16_BASE: +#ifdef CONFIG_STM32_TIM16 + case STM32_TIM16_BASE: freqin = BOARD_TIM16_FREQUENCY; break; #endif -#ifdef CONFIG_STM32WB_TIM17 - case STM32WB_TIM17_BASE: +#ifdef CONFIG_STM32_TIM17 + case STM32_TIM17_BASE: freqin = BOARD_TIM17_FREQUENCY; break; #endif @@ -647,17 +647,17 @@ static int stm32wb_tim_setfreq(struct stm32wb_tim_dev_s *dev, uint32_t freq) /* Set the reload and prescaler values */ - stm32wb_putreg16(dev, STM32WB_TIM_PSC_OFFSET, prescaler - 1); - stm32wb_putreg16(dev, STM32WB_TIM_ARR_OFFSET, reload); + stm32_putreg16(dev, STM32_TIM_PSC_OFFSET, prescaler - 1); + stm32_putreg16(dev, STM32_TIM_ARR_OFFSET, reload); return (timclk / reload); } /**************************************************************************** - * Name: stm32wb_tim_setclock + * Name: stm32_tim_setclock ****************************************************************************/ -static int stm32wb_tim_setclock(struct stm32wb_tim_dev_s *dev, uint32_t freq) +static int stm32_tim_setclock(struct stm32_tim_dev_s *dev, uint32_t freq) { uint32_t freqin; int prescaler; @@ -668,7 +668,7 @@ static int stm32wb_tim_setclock(struct stm32wb_tim_dev_s *dev, uint32_t freq) if (freq == 0) { - stm32wb_tim_disable(dev); + stm32_tim_disable(dev); return 0; } @@ -678,28 +678,28 @@ static int stm32wb_tim_setclock(struct stm32wb_tim_dev_s *dev, uint32_t freq) * must be defined in the board.h header file. */ - switch (((struct stm32wb_tim_priv_s *)dev)->base) + switch (((struct stm32_tim_priv_s *)dev)->base) { -#ifdef CONFIG_STM32WB_TIM1 - case STM32WB_TIM1_BASE: +#ifdef CONFIG_STM32_TIM1 + case STM32_TIM1_BASE: freqin = BOARD_TIM1_FREQUENCY; break; #endif -#ifdef CONFIG_STM32WB_TIM2 - case STM32WB_TIM2_BASE: +#ifdef CONFIG_STM32_TIM2 + case STM32_TIM2_BASE: freqin = BOARD_TIM2_FREQUENCY; break; #endif -#ifdef CONFIG_STM32WB_TIM16 - case STM32WB_TIM16_BASE: +#ifdef CONFIG_STM32_TIM16 + case STM32_TIM16_BASE: freqin = BOARD_TIM16_FREQUENCY; break; #endif -#ifdef CONFIG_STM32WB_TIM17 - case STM32WB_TIM17_BASE: +#ifdef CONFIG_STM32_TIM17 + case STM32_TIM17_BASE: freqin = BOARD_TIM17_FREQUENCY; break; #endif @@ -730,16 +730,16 @@ static int stm32wb_tim_setclock(struct stm32wb_tim_dev_s *dev, uint32_t freq) prescaler = 0xffff; } - stm32wb_putreg16(dev, STM32WB_TIM_PSC_OFFSET, prescaler); + stm32_putreg16(dev, STM32_TIM_PSC_OFFSET, prescaler); return prescaler; } /**************************************************************************** - * Name: stm32wb_tim_getclock + * Name: stm32_tim_getclock ****************************************************************************/ -static uint32_t stm32wb_tim_getclock(struct stm32wb_tim_dev_s *dev) +static uint32_t stm32_tim_getclock(struct stm32_tim_dev_s *dev) { uint32_t freqin; uint32_t clock; @@ -751,28 +751,28 @@ static uint32_t stm32wb_tim_getclock(struct stm32wb_tim_dev_s *dev) * must be defined in the board.h header file. */ - switch (((struct stm32wb_tim_priv_s *)dev)->base) + switch (((struct stm32_tim_priv_s *)dev)->base) { -#ifdef CONFIG_STM32WB_TIM1 - case STM32WB_TIM1_BASE: +#ifdef CONFIG_STM32_TIM1 + case STM32_TIM1_BASE: freqin = BOARD_TIM1_FREQUENCY; break; #endif -#ifdef CONFIG_STM32WB_TIM2 - case STM32WB_TIM2_BASE: +#ifdef CONFIG_STM32_TIM2 + case STM32_TIM2_BASE: freqin = BOARD_TIM2_FREQUENCY; break; #endif -#ifdef CONFIG_STM32WB_TIM16 - case STM32WB_TIM16_BASE: +#ifdef CONFIG_STM32_TIM16 + case STM32_TIM16_BASE: freqin = BOARD_TIM16_FREQUENCY; break; #endif -#ifdef CONFIG_STM32WB_TIM17 - case STM32WB_TIM17_BASE: +#ifdef CONFIG_STM32_TIM17 + case STM32_TIM17_BASE: freqin = BOARD_TIM17_FREQUENCY; break; #endif @@ -782,44 +782,44 @@ static uint32_t stm32wb_tim_getclock(struct stm32wb_tim_dev_s *dev) /* From chip datasheet, at page 1179. */ - clock = freqin / (stm32wb_getreg16(dev, STM32WB_TIM_PSC_OFFSET) + 1); + clock = freqin / (stm32_getreg16(dev, STM32_TIM_PSC_OFFSET) + 1); return clock; } /**************************************************************************** - * Name: stm32wb_tim_setperiod + * Name: stm32_tim_setperiod ****************************************************************************/ -static void stm32wb_tim_setperiod(struct stm32wb_tim_dev_s *dev, +static void stm32_tim_setperiod(struct stm32_tim_dev_s *dev, uint32_t period) { DEBUGASSERT(dev != NULL); - stm32wb_putreg32(dev, STM32WB_TIM_ARR_OFFSET, period); + stm32_putreg32(dev, STM32_TIM_ARR_OFFSET, period); } /**************************************************************************** - * Name: stm32wb_tim_getperiod + * Name: stm32_tim_getperiod ****************************************************************************/ -static uint32_t stm32wb_tim_getperiod (struct stm32wb_tim_dev_s *dev) +static uint32_t stm32_tim_getperiod (struct stm32_tim_dev_s *dev) { DEBUGASSERT(dev != NULL); - return stm32wb_getreg32 (dev, STM32WB_TIM_ARR_OFFSET); + return stm32_getreg32 (dev, STM32_TIM_ARR_OFFSET); } /**************************************************************************** - * Name: stm32wb_tim_getcounter + * Name: stm32_tim_getcounter ****************************************************************************/ -static uint32_t stm32wb_tim_getcounter(struct stm32wb_tim_dev_s *dev) +static uint32_t stm32_tim_getcounter(struct stm32_tim_dev_s *dev) { DEBUGASSERT(dev != NULL); - uint32_t counter = stm32wb_getreg32(dev, STM32WB_TIM_CNT_OFFSET); + uint32_t counter = stm32_getreg32(dev, STM32_TIM_CNT_OFFSET); /* TIM2 is a 32-bit timer. */ -#if defined(CONFIG_STM32WB_TIM2) - if (((struct stm32wb_tim_priv_s *)dev)->base == STM32WB_TIM2_BASE) +#if defined(CONFIG_STM32_TIM2) + if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM2_BASE) { return counter; } @@ -829,15 +829,15 @@ static uint32_t stm32wb_tim_getcounter(struct stm32wb_tim_dev_s *dev) } /**************************************************************************** - * Name: stm32wb_tim_getwidth + * Name: stm32_tim_getwidth ****************************************************************************/ -static uint32_t stm32wb_tim_getwidth(struct stm32wb_tim_dev_s *dev) +static uint32_t stm32_tim_getwidth(struct stm32_tim_dev_s *dev) { /* Only TIM2 is a 32-bit timer. */ -#if defined(CONFIG_STM32WB_TIM2) - if (((struct stm32wb_tim_priv_s *)dev)->base == STM32WB_TIM2_BASE) +#if defined(CONFIG_STM32_TIM2) + if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM2_BASE) { return 32; } @@ -849,17 +849,17 @@ static uint32_t stm32wb_tim_getwidth(struct stm32wb_tim_dev_s *dev) } /**************************************************************************** - * Name: stm32wb_tim_setchannel + * Name: stm32_tim_setchannel ****************************************************************************/ -static int stm32wb_tim_setchannel(struct stm32wb_tim_dev_s *dev, +static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, uint8_t channel, - enum stm32wb_tim_channel_e mode) + enum stm32_tim_channel_e mode) { uint16_t ccmr_orig = 0; uint16_t ccmr_val = 0; uint16_t ccer_val; - uint8_t ccmr_offset = STM32WB_TIM_CCMR1_OFFSET; + uint8_t ccmr_offset = STM32_TIM_CCMR1_OFFSET; DEBUGASSERT(dev != NULL); @@ -872,17 +872,17 @@ static int stm32wb_tim_setchannel(struct stm32wb_tim_dev_s *dev, /* Assume that channel is disabled and polarity is active high */ - ccer_val = stm32wb_getreg16(dev, STM32WB_TIM_CCER_OFFSET); + ccer_val = stm32_getreg16(dev, STM32_TIM_CCER_OFFSET); ccer_val &= ~(GTIM_CCER_CCXE(channel) | GTIM_CCER_CCXP(channel)); /* Decode configuration */ - switch (mode & STM32WB_TIM_CH_MODE_MASK) + switch (mode & STM32_TIM_CH_MODE_MASK) { - case STM32WB_TIM_CH_DISABLED: + case STM32_TIM_CH_DISABLED: break; - case STM32WB_TIM_CH_OUTPWM: + case STM32_TIM_CH_OUTPWM: ccmr_val = GTIM_CCMR_OCXM_PWM1(channel) | GTIM_CCMR_OCXPE(channel); ccer_val |= GTIM_CCER_CCXE(channel); break; @@ -893,51 +893,51 @@ static int stm32wb_tim_setchannel(struct stm32wb_tim_dev_s *dev, /* Set polarity */ - if (mode & STM32WB_TIM_CH_POLARITY_NEG) + if (mode & STM32_TIM_CH_POLARITY_NEG) { ccer_val |= GTIM_CCER_CCXP(channel); } if (channel > 1) { - ccmr_offset = STM32WB_TIM_CCMR2_OFFSET; + ccmr_offset = STM32_TIM_CCMR2_OFFSET; } - ccmr_orig = stm32wb_getreg16(dev, ccmr_offset); + ccmr_orig = stm32_getreg16(dev, ccmr_offset); ccmr_orig &= ~(GTIM_CCMR_OCXM_MASK(channel) | GTIM_CCMR_OCXPE(channel)); ccmr_orig |= ccmr_val; - stm32wb_putreg16(dev, ccmr_offset, ccmr_orig); - stm32wb_putreg16(dev, STM32WB_TIM_CCER_OFFSET, ccer_val); + stm32_putreg16(dev, ccmr_offset, ccmr_orig); + stm32_putreg16(dev, STM32_TIM_CCER_OFFSET, ccer_val); /* set GPIO */ - switch (((struct stm32wb_tim_priv_s *)dev)->base) + switch (((struct stm32_tim_priv_s *)dev)->base) { -#ifdef CONFIG_STM32WB_TIM1 - case STM32WB_TIM1_BASE: +#ifdef CONFIG_STM32_TIM1 + case STM32_TIM1_BASE: switch (channel) { #if defined(GPIO_TIM1_CH1OUT) case 0: - stm32wb_tim_gpioconfig(GPIO_TIM1_CH1OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM1_CH1OUT, mode); break; #endif #if defined(GPIO_TIM1_CH2OUT) case 1: - stm32wb_tim_gpioconfig(GPIO_TIM1_CH2OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM1_CH2OUT, mode); break; #endif #if defined(GPIO_TIM1_CH3OUT) case 2: - stm32wb_tim_gpioconfig(GPIO_TIM1_CH3OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM1_CH3OUT, mode); break; #endif #if defined(GPIO_TIM1_CH4OUT) case 3: - stm32wb_tim_gpioconfig(GPIO_TIM1_CH4OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM1_CH4OUT, mode); break; #endif @@ -946,31 +946,31 @@ static int stm32wb_tim_setchannel(struct stm32wb_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32WB_TIM2 - case STM32WB_TIM2_BASE: +#ifdef CONFIG_STM32_TIM2 + case STM32_TIM2_BASE: switch (channel) { #if defined(GPIO_TIM2_CH1OUT) case 0: - stm32wb_tim_gpioconfig(GPIO_TIM2_CH1OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM2_CH1OUT, mode); break; #endif #if defined(GPIO_TIM2_CH2OUT) case 1: - stm32wb_tim_gpioconfig(GPIO_TIM2_CH2OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM2_CH2OUT, mode); break; #endif #if defined(GPIO_TIM2_CH3OUT) case 2: - stm32wb_tim_gpioconfig(GPIO_TIM2_CH3OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM2_CH3OUT, mode); break; #endif #if defined(GPIO_TIM2_CH4OUT) case 3: - stm32wb_tim_gpioconfig(GPIO_TIM2_CH4OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM2_CH4OUT, mode); break; #endif @@ -979,13 +979,13 @@ static int stm32wb_tim_setchannel(struct stm32wb_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32WB_TIM16 - case STM32WB_TIM16_BASE: +#ifdef CONFIG_STM32_TIM16 + case STM32_TIM16_BASE: switch (channel) { #if defined(GPIO_TIM16_CH1OUT) case 0: - stm32wb_tim_gpioconfig(GPIO_TIM16_CH1OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM16_CH1OUT, mode); break; #endif @@ -994,13 +994,13 @@ static int stm32wb_tim_setchannel(struct stm32wb_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32WB_TIM17 - case STM32WB_TIM17_BASE: +#ifdef CONFIG_STM32_TIM17 + case STM32_TIM17_BASE: switch (channel) { #if defined(GPIO_TIM17_CH1OUT) case 0: - stm32wb_tim_gpioconfig(GPIO_TIM17_CH1OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM17_CH1OUT, mode); break; #endif @@ -1018,10 +1018,10 @@ static int stm32wb_tim_setchannel(struct stm32wb_tim_dev_s *dev, } /**************************************************************************** - * Name: stm32wb_tim_setcompare + * Name: stm32_tim_setcompare ****************************************************************************/ -static int stm32wb_tim_setcompare(struct stm32wb_tim_dev_s *dev, +static int stm32_tim_setcompare(struct stm32_tim_dev_s *dev, uint8_t channel, uint32_t compare) { DEBUGASSERT(dev != NULL); @@ -1029,19 +1029,19 @@ static int stm32wb_tim_setcompare(struct stm32wb_tim_dev_s *dev, switch (channel) { case 1: - stm32wb_putreg32(dev, STM32WB_TIM_CCR1_OFFSET, compare); + stm32_putreg32(dev, STM32_TIM_CCR1_OFFSET, compare); break; case 2: - stm32wb_putreg32(dev, STM32WB_TIM_CCR2_OFFSET, compare); + stm32_putreg32(dev, STM32_TIM_CCR2_OFFSET, compare); break; case 3: - stm32wb_putreg32(dev, STM32WB_TIM_CCR3_OFFSET, compare); + stm32_putreg32(dev, STM32_TIM_CCR3_OFFSET, compare); break; case 4: - stm32wb_putreg32(dev, STM32WB_TIM_CCR4_OFFSET, compare); + stm32_putreg32(dev, STM32_TIM_CCR4_OFFSET, compare); break; default: @@ -1052,10 +1052,10 @@ static int stm32wb_tim_setcompare(struct stm32wb_tim_dev_s *dev, } /**************************************************************************** - * Name: stm32wb_tim_getcapture + * Name: stm32_tim_getcapture ****************************************************************************/ -static uint32_t stm32wb_tim_getcapture(struct stm32wb_tim_dev_s *dev, +static uint32_t stm32_tim_getcapture(struct stm32_tim_dev_s *dev, uint8_t channel) { DEBUGASSERT(dev != NULL); @@ -1063,26 +1063,26 @@ static uint32_t stm32wb_tim_getcapture(struct stm32wb_tim_dev_s *dev, switch (channel) { case 1: - return stm32wb_getreg32(dev, STM32WB_TIM_CCR1_OFFSET); + return stm32_getreg32(dev, STM32_TIM_CCR1_OFFSET); case 2: - return stm32wb_getreg32(dev, STM32WB_TIM_CCR2_OFFSET); + return stm32_getreg32(dev, STM32_TIM_CCR2_OFFSET); case 3: - return stm32wb_getreg32(dev, STM32WB_TIM_CCR3_OFFSET); + return stm32_getreg32(dev, STM32_TIM_CCR3_OFFSET); case 4: - return stm32wb_getreg32(dev, STM32WB_TIM_CCR4_OFFSET); + return stm32_getreg32(dev, STM32_TIM_CCR4_OFFSET); } return -EINVAL; } /**************************************************************************** - * Name: stm32wb_tim_setisr + * Name: stm32_tim_setisr ****************************************************************************/ -static int stm32wb_tim_setisr(struct stm32wb_tim_dev_s *dev, +static int stm32_tim_setisr(struct stm32_tim_dev_s *dev, xcpt_t handler, void *arg, int source) { int vectorno; @@ -1090,29 +1090,29 @@ static int stm32wb_tim_setisr(struct stm32wb_tim_dev_s *dev, DEBUGASSERT(dev != NULL); DEBUGASSERT(source == 0); - switch (((struct stm32wb_tim_priv_s *)dev)->base) + switch (((struct stm32_tim_priv_s *)dev)->base) { -#ifdef CONFIG_STM32WB_TIM1 - case STM32WB_TIM1_BASE: - vectorno = STM32WB_IRQ_TIM1UP; +#ifdef CONFIG_STM32_TIM1 + case STM32_TIM1_BASE: + vectorno = STM32_IRQ_TIM1UP; break; #endif -#ifdef CONFIG_STM32WB_TIM2 - case STM32WB_TIM2_BASE: - vectorno = STM32WB_IRQ_TIM2; +#ifdef CONFIG_STM32_TIM2 + case STM32_TIM2_BASE: + vectorno = STM32_IRQ_TIM2; break; #endif -#ifdef CONFIG_STM32WB_TIM16 - case STM32WB_TIM16_BASE: - vectorno = STM32WB_IRQ_TIM16; +#ifdef CONFIG_STM32_TIM16 + case STM32_TIM16_BASE: + vectorno = STM32_IRQ_TIM16; break; #endif -#ifdef CONFIG_STM32WB_TIM17 - case STM32WB_TIM17_BASE: - vectorno = STM32WB_IRQ_TIM17; +#ifdef CONFIG_STM32_TIM17 + case STM32_TIM17_BASE: + vectorno = STM32_IRQ_TIM17; break; #endif @@ -1138,41 +1138,41 @@ static int stm32wb_tim_setisr(struct stm32wb_tim_dev_s *dev, } /**************************************************************************** - * Name: stm32wb_tim_enableint + * Name: stm32_tim_enableint ****************************************************************************/ -static void stm32wb_tim_enableint(struct stm32wb_tim_dev_s *dev, int source) +static void stm32_tim_enableint(struct stm32_tim_dev_s *dev, int source) { DEBUGASSERT(dev != NULL); - stm32wb_modifyreg16(dev, STM32WB_TIM_DIER_OFFSET, 0, source); + stm32_modifyreg16(dev, STM32_TIM_DIER_OFFSET, 0, source); } /**************************************************************************** - * Name: stm32wb_tim_disableint + * Name: stm32_tim_disableint ****************************************************************************/ -static void stm32wb_tim_disableint(struct stm32wb_tim_dev_s *dev, int source) +static void stm32_tim_disableint(struct stm32_tim_dev_s *dev, int source) { DEBUGASSERT(dev != NULL); - stm32wb_modifyreg16(dev, STM32WB_TIM_DIER_OFFSET, source, 0); + stm32_modifyreg16(dev, STM32_TIM_DIER_OFFSET, source, 0); } /**************************************************************************** - * Name: stm32wb_tim_ackint + * Name: stm32_tim_ackint ****************************************************************************/ -static void stm32wb_tim_ackint(struct stm32wb_tim_dev_s *dev, int source) +static void stm32_tim_ackint(struct stm32_tim_dev_s *dev, int source) { - stm32wb_putreg16(dev, STM32WB_TIM_SR_OFFSET, ~source); + stm32_putreg16(dev, STM32_TIM_SR_OFFSET, ~source); } /**************************************************************************** - * Name: stm32wb_tim_checkint + * Name: stm32_tim_checkint ****************************************************************************/ -static int stm32wb_tim_checkint(struct stm32wb_tim_dev_s *dev, int source) +static int stm32_tim_checkint(struct stm32_tim_dev_s *dev, int source) { - uint16_t regval = stm32wb_getreg16(dev, STM32WB_TIM_SR_OFFSET); + uint16_t regval = stm32_getreg16(dev, STM32_TIM_SR_OFFSET); return (regval & source) ? 1 : 0; } @@ -1181,42 +1181,42 @@ static int stm32wb_tim_checkint(struct stm32wb_tim_dev_s *dev, int source) ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_tim_init + * Name: stm32_tim_init ****************************************************************************/ -struct stm32wb_tim_dev_s *stm32wb_tim_init(int timer) +struct stm32_tim_dev_s *stm32_tim_init(int timer) { - struct stm32wb_tim_dev_s *dev = NULL; + struct stm32_tim_dev_s *dev = NULL; /* Get structure and enable power */ switch (timer) { -#ifdef CONFIG_STM32WB_TIM1 +#ifdef CONFIG_STM32_TIM1 case 1: - dev = (struct stm32wb_tim_dev_s *)&stm32wb_tim1_priv; - modifyreg32(STM32WB_RCC_APB2ENR, 0, RCC_APB2ENR_TIM1EN); + dev = (struct stm32_tim_dev_s *)&stm32_tim1_priv; + modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM1EN); break; #endif -#ifdef CONFIG_STM32WB_TIM2 +#ifdef CONFIG_STM32_TIM2 case 2: - dev = (struct stm32wb_tim_dev_s *)&stm32wb_tim2_priv; - modifyreg32(STM32WB_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM2EN); + dev = (struct stm32_tim_dev_s *)&stm32_tim2_priv; + modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM2EN); break; #endif -#ifdef CONFIG_STM32WB_TIM16 +#ifdef CONFIG_STM32_TIM16 case 16: - dev = (struct stm32wb_tim_dev_s *)&stm32wb_tim16_priv; - modifyreg32(STM32WB_RCC_APB2ENR, 0, RCC_APB2ENR_TIM16EN); + dev = (struct stm32_tim_dev_s *)&stm32_tim16_priv; + modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM16EN); break; #endif -#ifdef CONFIG_STM32WB_TIM17 +#ifdef CONFIG_STM32_TIM17 case 17: - dev = (struct stm32wb_tim_dev_s *)&stm32wb_tim17_priv; - modifyreg32(STM32WB_RCC_APB2ENR, 0, RCC_APB2ENR_TIM17EN); + dev = (struct stm32_tim_dev_s *)&stm32_tim17_priv; + modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM17EN); break; #endif @@ -1226,52 +1226,52 @@ struct stm32wb_tim_dev_s *stm32wb_tim_init(int timer) /* Is device already allocated */ - if (((struct stm32wb_tim_priv_s *)dev)->mode != STM32WB_TIM_MODE_UNUSED) + if (((struct stm32_tim_priv_s *)dev)->mode != STM32_TIM_MODE_UNUSED) { return NULL; } - stm32wb_tim_reset(dev); + stm32_tim_reset(dev); return dev; } /**************************************************************************** - * Name: stm32wb_tim_deinit + * Name: stm32_tim_deinit * * TODO: Detach interrupts, and close down all TIM Channels * ****************************************************************************/ -int stm32wb_tim_deinit(struct stm32wb_tim_dev_s *dev) +int stm32_tim_deinit(struct stm32_tim_dev_s *dev) { DEBUGASSERT(dev != NULL); /* Disable power */ - switch (((struct stm32wb_tim_priv_s *)dev)->base) + switch (((struct stm32_tim_priv_s *)dev)->base) { -#ifdef CONFIG_STM32WB_TIM1 - case STM32WB_TIM1_BASE: - modifyreg32(STM32WB_RCC_APB2ENR, RCC_APB2ENR_TIM1EN, 0); +#ifdef CONFIG_STM32_TIM1 + case STM32_TIM1_BASE: + modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM1EN, 0); break; #endif -#ifdef CONFIG_STM32WB_TIM2 - case STM32WB_TIM2_BASE: - modifyreg32(STM32WB_RCC_APB1ENR1, RCC_APB1ENR1_TIM2EN, 0); +#ifdef CONFIG_STM32_TIM2 + case STM32_TIM2_BASE: + modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM2EN, 0); break; #endif -#ifdef CONFIG_STM32WB_TIM16 - case STM32WB_TIM16_BASE: - modifyreg32(STM32WB_RCC_APB2ENR, RCC_APB2ENR_TIM16EN, 0); +#ifdef CONFIG_STM32_TIM16 + case STM32_TIM16_BASE: + modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM16EN, 0); break; #endif -#ifdef CONFIG_STM32WB_TIM17 - case STM32WB_TIM17_BASE: - modifyreg32(STM32WB_RCC_APB2ENR, RCC_APB2ENR_TIM17EN, 0); +#ifdef CONFIG_STM32_TIM17 + case STM32_TIM17_BASE: + modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM17EN, 0); break; #endif @@ -1281,9 +1281,9 @@ int stm32wb_tim_deinit(struct stm32wb_tim_dev_s *dev) /* Mark it as free */ - ((struct stm32wb_tim_priv_s *)dev)->mode = STM32WB_TIM_MODE_UNUSED; + ((struct stm32_tim_priv_s *)dev)->mode = STM32_TIM_MODE_UNUSED; return OK; } -#endif /* defined(CONFIG_STM32WB_TIM1 || ... || TIM17) */ +#endif /* defined(CONFIG_STM32_TIM1 || ... || TIM17) */ diff --git a/arch/arm/src/stm32wb/stm32wb_tim.h b/arch/arm/src/stm32wb/stm32wb_tim.h index a1257fbee512b..e928d3e6ddd9b 100644 --- a/arch/arm/src/stm32wb/stm32wb_tim.h +++ b/arch/arm/src/stm32wb/stm32wb_tim.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32WB_STM32WB_TIM_H -#define __ARCH_ARM_SRC_STM32WB_STM32WB_TIM_H +#ifndef __ARCH_ARM_SRC_STM32WB_STM32_TIM_H +#define __ARCH_ARM_SRC_STM32WB_STM32_TIM_H /**************************************************************************** * Included Files @@ -64,25 +64,25 @@ /* Helpers ******************************************************************/ -#define STM32WB_TIM_SETMODE(d,mode) ((d)->ops->setmode(d,mode)) -#define STM32WB_TIM_SETFREQ(d,freq) ((d)->ops->setfreq(d,freq)) -#define STM32WB_TIM_SETCLOCK(d,freq) ((d)->ops->setclock(d,freq)) -#define STM32WB_TIM_GETCLOCK(d) ((d)->ops->getclock(d)) -#define STM32WB_TIM_SETPERIOD(d,period) ((d)->ops->setperiod(d,period)) -#define STM32WB_TIM_GETPERIOD(d) ((d)->ops->getperiod(d)) -#define STM32WB_TIM_GETCOUNTER(d) ((d)->ops->getcounter(d)) -#define STM32WB_TIM_GETWIDTH(d) ((d)->ops->getwidth(d)) -#define STM32WB_TIM_SETCHANNEL(d,ch,mode) ((d)->ops->setchannel(d,ch,mode)) -#define STM32WB_TIM_SETCOMPARE(d,ch,comp) ((d)->ops->setcompare(d,ch,comp)) -#define STM32WB_TIM_GETCAPTURE(d,ch) ((d)->ops->getcapture(d,ch)) -#define STM32WB_TIM_SETISR(d,hnd,arg,s) ((d)->ops->setisr(d,hnd,arg,s)) -#define STM32WB_TIM_ENABLEINT(d,s) ((d)->ops->enableint(d,s)) -#define STM32WB_TIM_DISABLEINT(d,s) ((d)->ops->disableint(d,s)) -#define STM32WB_TIM_ACKINT(d,s) ((d)->ops->ackint(d,s)) -#define STM32WB_TIM_CHECKINT(d,s) ((d)->ops->checkint(d,s)) -#define STM32WB_TIM_ENABLE(d) ((d)->ops->enable(d)) -#define STM32WB_TIM_DISABLE(d) ((d)->ops->disable(d)) -#define STM32WB_TIM_DUMPREGS(d) ((d)->ops->dump_regs(d)) +#define STM32_TIM_SETMODE(d,mode) ((d)->ops->setmode(d,mode)) +#define STM32_TIM_SETFREQ(d,freq) ((d)->ops->setfreq(d,freq)) +#define STM32_TIM_SETCLOCK(d,freq) ((d)->ops->setclock(d,freq)) +#define STM32_TIM_GETCLOCK(d) ((d)->ops->getclock(d)) +#define STM32_TIM_SETPERIOD(d,period) ((d)->ops->setperiod(d,period)) +#define STM32_TIM_GETPERIOD(d) ((d)->ops->getperiod(d)) +#define STM32_TIM_GETCOUNTER(d) ((d)->ops->getcounter(d)) +#define STM32_TIM_GETWIDTH(d) ((d)->ops->getwidth(d)) +#define STM32_TIM_SETCHANNEL(d,ch,mode) ((d)->ops->setchannel(d,ch,mode)) +#define STM32_TIM_SETCOMPARE(d,ch,comp) ((d)->ops->setcompare(d,ch,comp)) +#define STM32_TIM_GETCAPTURE(d,ch) ((d)->ops->getcapture(d,ch)) +#define STM32_TIM_SETISR(d,hnd,arg,s) ((d)->ops->setisr(d,hnd,arg,s)) +#define STM32_TIM_ENABLEINT(d,s) ((d)->ops->enableint(d,s)) +#define STM32_TIM_DISABLEINT(d,s) ((d)->ops->disableint(d,s)) +#define STM32_TIM_ACKINT(d,s) ((d)->ops->ackint(d,s)) +#define STM32_TIM_CHECKINT(d,s) ((d)->ops->checkint(d,s)) +#define STM32_TIM_ENABLE(d) ((d)->ops->enable(d)) +#define STM32_TIM_DISABLE(d) ((d)->ops->disable(d)) +#define STM32_TIM_DUMPREGS(d) ((d)->ops->dump_regs(d)) /**************************************************************************** * Public Types @@ -101,43 +101,43 @@ extern "C" /* TIM Device Structure */ -struct stm32wb_tim_dev_s +struct stm32_tim_dev_s { - struct stm32wb_tim_ops_s *ops; + struct stm32_tim_ops_s *ops; }; /* TIM Modes of Operation */ -enum stm32wb_tim_mode_e +enum stm32_tim_mode_e { - STM32WB_TIM_MODE_UNUSED = -1, + STM32_TIM_MODE_UNUSED = -1, /* One of the following */ - STM32WB_TIM_MODE_MASK = 0x0310, - STM32WB_TIM_MODE_DISABLED = 0x0000, - STM32WB_TIM_MODE_UP = 0x0100, - STM32WB_TIM_MODE_DOWN = 0x0110, - STM32WB_TIM_MODE_UPDOWN = 0x0200, - STM32WB_TIM_MODE_PULSE = 0x0300, + STM32_TIM_MODE_MASK = 0x0310, + STM32_TIM_MODE_DISABLED = 0x0000, + STM32_TIM_MODE_UP = 0x0100, + STM32_TIM_MODE_DOWN = 0x0110, + STM32_TIM_MODE_UPDOWN = 0x0200, + STM32_TIM_MODE_PULSE = 0x0300, /* One of the following */ - STM32WB_TIM_MODE_CK_INT = 0x0000, + STM32_TIM_MODE_CK_INT = 0x0000, #if 0 - STM32WB_TIM_MODE_CK_INT_TRIG = 0x0400, - STM32WB_TIM_MODE_CK_EXT = 0x0800, - STM32WB_TIM_MODE_CK_EXT_TRIG = 0x0c00, + STM32_TIM_MODE_CK_INT_TRIG = 0x0400, + STM32_TIM_MODE_CK_EXT = 0x0800, + STM32_TIM_MODE_CK_EXT_TRIG = 0x0c00, #endif /* Clock sources, OR'ed with CK_EXT */ #if 0 - STM32WB_TIM_MODE_CK_CHINVALID = 0x0000, - STM32WB_TIM_MODE_CK_CH1 = 0x0001, - STM32WB_TIM_MODE_CK_CH2 = 0x0002, - STM32WB_TIM_MODE_CK_CH3 = 0x0003, - STM32WB_TIM_MODE_CK_CH4 = 0x0004 + STM32_TIM_MODE_CK_CHINVALID = 0x0000, + STM32_TIM_MODE_CK_CH1 = 0x0001, + STM32_TIM_MODE_CK_CH2 = 0x0002, + STM32_TIM_MODE_CK_CH3 = 0x0003, + STM32_TIM_MODE_CK_CH4 = 0x0004 #endif /* Todo: external trigger block */ @@ -145,70 +145,70 @@ enum stm32wb_tim_mode_e /* TIM Channel Modes */ -enum stm32wb_tim_channel_e +enum stm32_tim_channel_e { - STM32WB_TIM_CH_DISABLED = 0x00, + STM32_TIM_CH_DISABLED = 0x00, /* Common configuration */ - STM32WB_TIM_CH_POLARITY_POS = 0x00, - STM32WB_TIM_CH_POLARITY_NEG = 0x01, + STM32_TIM_CH_POLARITY_POS = 0x00, + STM32_TIM_CH_POLARITY_NEG = 0x01, /* MODES: */ - STM32WB_TIM_CH_MODE_MASK = 0x06, + STM32_TIM_CH_MODE_MASK = 0x06, /* Output Compare Modes */ - STM32WB_TIM_CH_OUTPWM = 0x04, /* Enable standard PWM mode, active + STM32_TIM_CH_OUTPWM = 0x04, /* Enable standard PWM mode, active * high when counter < compare */ #if 0 - STM32WB_TIM_CH_OUTCOMPARE = 0x06, + STM32_TIM_CH_OUTCOMPARE = 0x06, #endif /* TODO other modes ... as PWM capture, ENCODER and Hall Sensor */ #if 0 - STM32WB_TIM_CH_INCAPTURE = 0x10, - STM32WB_TIM_CH_INPWM = 0x20 - STM32WB_TIM_CH_DRIVE_OC /* Open collector mode */ + STM32_TIM_CH_INCAPTURE = 0x10, + STM32_TIM_CH_INPWM = 0x20 + STM32_TIM_CH_DRIVE_OC /* Open collector mode */ #endif }; /* TIM Operations */ -struct stm32wb_tim_ops_s +struct stm32_tim_ops_s { - void (*enable)(struct stm32wb_tim_dev_s *dev); - void (*disable)(struct stm32wb_tim_dev_s *dev); - int (*setmode)(struct stm32wb_tim_dev_s *dev, - enum stm32wb_tim_mode_e mode); - int (*setfreq)(struct stm32wb_tim_dev_s *dev, uint32_t freq); - int (*setclock)(struct stm32wb_tim_dev_s *dev, uint32_t freq); - uint32_t (*getclock)(struct stm32wb_tim_dev_s *dev); - void (*setperiod)(struct stm32wb_tim_dev_s *dev, uint32_t period); - uint32_t (*getperiod)(struct stm32wb_tim_dev_s *dev); - uint32_t (*getcounter)(struct stm32wb_tim_dev_s *dev); - uint32_t (*getwidth)(struct stm32wb_tim_dev_s *dev); - int (*setchannel)(struct stm32wb_tim_dev_s *dev, uint8_t channel, - enum stm32wb_tim_channel_e mode); - int (*setcompare)(struct stm32wb_tim_dev_s *dev, uint8_t channel, + void (*enable)(struct stm32_tim_dev_s *dev); + void (*disable)(struct stm32_tim_dev_s *dev); + int (*setmode)(struct stm32_tim_dev_s *dev, + enum stm32_tim_mode_e mode); + int (*setfreq)(struct stm32_tim_dev_s *dev, uint32_t freq); + int (*setclock)(struct stm32_tim_dev_s *dev, uint32_t freq); + uint32_t (*getclock)(struct stm32_tim_dev_s *dev); + void (*setperiod)(struct stm32_tim_dev_s *dev, uint32_t period); + uint32_t (*getperiod)(struct stm32_tim_dev_s *dev); + uint32_t (*getcounter)(struct stm32_tim_dev_s *dev); + uint32_t (*getwidth)(struct stm32_tim_dev_s *dev); + int (*setchannel)(struct stm32_tim_dev_s *dev, uint8_t channel, + enum stm32_tim_channel_e mode); + int (*setcompare)(struct stm32_tim_dev_s *dev, uint8_t channel, uint32_t compare); - uint32_t (*getcapture)(struct stm32wb_tim_dev_s *dev, uint8_t channel); + uint32_t (*getcapture)(struct stm32_tim_dev_s *dev, uint8_t channel); /* Timer interrupts */ - int (*setisr)(struct stm32wb_tim_dev_s *dev, + int (*setisr)(struct stm32_tim_dev_s *dev, xcpt_t handler, void *arg, int source); - void (*enableint)(struct stm32wb_tim_dev_s *dev, int source); - void (*disableint)(struct stm32wb_tim_dev_s *dev, int source); - void (*ackint)(struct stm32wb_tim_dev_s *dev, int source); - int (*checkint)(struct stm32wb_tim_dev_s *dev, int source); + void (*enableint)(struct stm32_tim_dev_s *dev, int source); + void (*disableint)(struct stm32_tim_dev_s *dev, int source); + void (*ackint)(struct stm32_tim_dev_s *dev, int source); + int (*checkint)(struct stm32_tim_dev_s *dev, int source); /* Debug */ - void (*dump_regs)(struct stm32wb_tim_dev_s *dev); + void (*dump_regs)(struct stm32_tim_dev_s *dev); }; /**************************************************************************** @@ -217,14 +217,14 @@ struct stm32wb_tim_ops_s /* Power-up timer and get its structure */ -struct stm32wb_tim_dev_s *stm32wb_tim_init(int timer); +struct stm32_tim_dev_s *stm32_tim_init(int timer); /* Power-down timer, mark it as unused */ -int stm32wb_tim_deinit(struct stm32wb_tim_dev_s *dev); +int stm32_tim_deinit(struct stm32_tim_dev_s *dev); /**************************************************************************** - * Name: stm32wb_timer_initialize + * Name: stm32_timer_initialize * * Description: * Bind the configuration timer to a timer lower half instance and @@ -242,7 +242,7 @@ int stm32wb_tim_deinit(struct stm32wb_tim_dev_s *dev); ****************************************************************************/ #ifdef CONFIG_TIMER -int stm32wb_timer_initialize(const char *devpath, int timer); +int stm32_timer_initialize(const char *devpath, int timer); #endif #undef EXTERN @@ -251,4 +251,4 @@ int stm32wb_timer_initialize(const char *devpath, int timer); #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32WB_STM32WB_TIM_H */ +#endif /* __ARCH_ARM_SRC_STM32WB_STM32_TIM_H */ diff --git a/arch/arm/src/stm32wb/stm32wb_tim_lowerhalf.c b/arch/arm/src/stm32wb/stm32wb_tim_lowerhalf.c index ef7af07926eb1..38e8db5b4aabb 100644 --- a/arch/arm/src/stm32wb/stm32wb_tim_lowerhalf.c +++ b/arch/arm/src/stm32wb/stm32wb_tim_lowerhalf.c @@ -37,17 +37,17 @@ #include "stm32wb_tim.h" #if defined(CONFIG_TIMER) && \ - (defined(CONFIG_STM32WB_TIM1) || defined(CONFIG_STM32WB_TIM2) || \ - defined(CONFIG_STM32WB_TIM16) || defined(CONFIG_STM32WB_TIM17)) + (defined(CONFIG_STM32_TIM1) || defined(CONFIG_STM32_TIM2) || \ + defined(CONFIG_STM32_TIM16) || defined(CONFIG_STM32_TIM17)) /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ -#define STM32WB_TIM1_RES 16 -#define STM32WB_TIM2_RES 32 -#define STM32WB_TIM16_RES 16 -#define STM32WB_TIM17_RES 16 +#define STM32_TIM1_RES 16 +#define STM32_TIM2_RES 32 +#define STM32_TIM16_RES 16 +#define STM32_TIM17_RES 16 /**************************************************************************** * Private Types @@ -58,10 +58,10 @@ * timer_lowerhalf_s structure. */ -struct stm32wb_lowerhalf_s +struct stm32_lowerhalf_s { const struct timer_ops_s *ops; /* Lower half operations */ - struct stm32wb_tim_dev_s *tim; /* stm32 timer driver */ + struct stm32_tim_dev_s *tim; /* stm32 timer driver */ tccb_t callback; /* Current upper half interrupt callback */ void *arg; /* Argument passed to upper half callback */ bool started; /* True: Timer has been started */ @@ -74,17 +74,17 @@ struct stm32wb_lowerhalf_s /* Interrupt handling *******************************************************/ -static int stm32wb_timer_handler(int irq, void *context, void *arg); +static int stm32_timer_handler(int irq, void *context, void *arg); /* "Lower half" driver methods **********************************************/ -static int stm32wb_start(struct timer_lowerhalf_s *lower); -static int stm32wb_stop(struct timer_lowerhalf_s *lower); -static int stm32wb_getstatus(struct timer_lowerhalf_s *lower, +static int stm32_start(struct timer_lowerhalf_s *lower); +static int stm32_stop(struct timer_lowerhalf_s *lower); +static int stm32_getstatus(struct timer_lowerhalf_s *lower, struct timer_status_s *status); -static int stm32wb_settimeout(struct timer_lowerhalf_s *lower, +static int stm32_settimeout(struct timer_lowerhalf_s *lower, uint32_t timeout); -static void stm32wb_setcallback(struct timer_lowerhalf_s *lower, +static void stm32_setcallback(struct timer_lowerhalf_s *lower, tccb_t callback, void *arg); /**************************************************************************** @@ -95,43 +95,43 @@ static void stm32wb_setcallback(struct timer_lowerhalf_s *lower, static const struct timer_ops_s g_timer_ops = { - .start = stm32wb_start, - .stop = stm32wb_stop, - .getstatus = stm32wb_getstatus, - .settimeout = stm32wb_settimeout, - .setcallback = stm32wb_setcallback, + .start = stm32_start, + .stop = stm32_stop, + .getstatus = stm32_getstatus, + .settimeout = stm32_settimeout, + .setcallback = stm32_setcallback, .ioctl = NULL, }; -#ifdef CONFIG_STM32WB_TIM1 -static struct stm32wb_lowerhalf_s g_tim1_lowerhalf = +#ifdef CONFIG_STM32_TIM1 +static struct stm32_lowerhalf_s g_tim1_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32WB_TIM1_RES, + .resolution = STM32_TIM1_RES, }; #endif -#ifdef CONFIG_STM32WB_TIM2 -static struct stm32wb_lowerhalf_s g_tim2_lowerhalf = +#ifdef CONFIG_STM32_TIM2 +static struct stm32_lowerhalf_s g_tim2_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32WB_TIM2_RES, + .resolution = STM32_TIM2_RES, }; #endif -#ifdef CONFIG_STM32WB_TIM16 -static struct stm32wb_lowerhalf_s g_tim16_lowerhalf = +#ifdef CONFIG_STM32_TIM16 +static struct stm32_lowerhalf_s g_tim16_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32WB_TIM16_RES, + .resolution = STM32_TIM16_RES, }; #endif -#ifdef CONFIG_STM32WB_TIM17 -static struct stm32wb_lowerhalf_s g_tim17_lowerhalf = +#ifdef CONFIG_STM32_TIM17 +static struct stm32_lowerhalf_s g_tim17_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32WB_TIM17_RES, + .resolution = STM32_TIM17_RES, }; #endif @@ -140,7 +140,7 @@ static struct stm32wb_lowerhalf_s g_tim17_lowerhalf = ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_timer_handler + * Name: stm32_timer_handler * * Description: * timer interrupt handler @@ -151,30 +151,30 @@ static struct stm32wb_lowerhalf_s g_tim17_lowerhalf = * ****************************************************************************/ -static int stm32wb_timer_handler(int irq, void *context, void *arg) +static int stm32_timer_handler(int irq, void *context, void *arg) { - struct stm32wb_lowerhalf_s *lower = (struct stm32wb_lowerhalf_s *)arg; + struct stm32_lowerhalf_s *lower = (struct stm32_lowerhalf_s *)arg; uint32_t next_interval_us = 0; - STM32WB_TIM_ACKINT(lower->tim, GTIM_DIER_UIE); + STM32_TIM_ACKINT(lower->tim, GTIM_DIER_UIE); if (lower->callback(&next_interval_us, lower->arg)) { if (next_interval_us > 0) { - STM32WB_TIM_SETPERIOD(lower->tim, next_interval_us); + STM32_TIM_SETPERIOD(lower->tim, next_interval_us); } } else { - stm32wb_stop((struct timer_lowerhalf_s *)lower); + stm32_stop((struct timer_lowerhalf_s *)lower); } return OK; } /**************************************************************************** - * Name: stm32wb_start + * Name: stm32_start * * Description: * Start the timer, resetting the time to the current timeout, @@ -188,18 +188,18 @@ static int stm32wb_timer_handler(int irq, void *context, void *arg) * ****************************************************************************/ -static int stm32wb_start(struct timer_lowerhalf_s *lower) +static int stm32_start(struct timer_lowerhalf_s *lower) { - struct stm32wb_lowerhalf_s *priv = (struct stm32wb_lowerhalf_s *)lower; + struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; if (!priv->started) { - STM32WB_TIM_SETMODE(priv->tim, STM32WB_TIM_MODE_UP); + STM32_TIM_SETMODE(priv->tim, STM32_TIM_MODE_UP); if (priv->callback != NULL) { - STM32WB_TIM_SETISR(priv->tim, stm32wb_timer_handler, priv, 0); - STM32WB_TIM_ENABLEINT(priv->tim, GTIM_DIER_UIE); + STM32_TIM_SETISR(priv->tim, stm32_timer_handler, priv, 0); + STM32_TIM_ENABLEINT(priv->tim, GTIM_DIER_UIE); } priv->started = true; @@ -212,7 +212,7 @@ static int stm32wb_start(struct timer_lowerhalf_s *lower) } /**************************************************************************** - * Name: stm32wb_stop + * Name: stm32_stop * * Description: * Stop the timer @@ -226,15 +226,15 @@ static int stm32wb_start(struct timer_lowerhalf_s *lower) * ****************************************************************************/ -static int stm32wb_stop(struct timer_lowerhalf_s *lower) +static int stm32_stop(struct timer_lowerhalf_s *lower) { - struct stm32wb_lowerhalf_s *priv = (struct stm32wb_lowerhalf_s *)lower; + struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; if (priv->started) { - STM32WB_TIM_SETMODE(priv->tim, STM32WB_TIM_MODE_DISABLED); - STM32WB_TIM_DISABLEINT(priv->tim, GTIM_DIER_UIE); - STM32WB_TIM_SETISR(priv->tim, NULL, NULL, 0); + STM32_TIM_SETMODE(priv->tim, STM32_TIM_MODE_DISABLED); + STM32_TIM_DISABLEINT(priv->tim, GTIM_DIER_UIE); + STM32_TIM_SETISR(priv->tim, NULL, NULL, 0); priv->started = false; return OK; } @@ -245,7 +245,7 @@ static int stm32wb_stop(struct timer_lowerhalf_s *lower) } /**************************************************************************** - * Name: stm32wb_getstatus + * Name: stm32_getstatus * * Description: * get timer status @@ -260,10 +260,10 @@ static int stm32wb_stop(struct timer_lowerhalf_s *lower) * ****************************************************************************/ -static int stm32wb_getstatus(struct timer_lowerhalf_s *lower, +static int stm32_getstatus(struct timer_lowerhalf_s *lower, struct timer_status_s *status) { - struct stm32wb_lowerhalf_s *priv = (struct stm32wb_lowerhalf_s *)lower; + struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; uint64_t maxtimeout; uint32_t timeout; uint32_t clock; @@ -288,8 +288,8 @@ static int stm32wb_getstatus(struct timer_lowerhalf_s *lower, /* Get timeout */ maxtimeout = (1 << priv->resolution) - 1; - clock = STM32WB_TIM_GETCLOCK(priv->tim); - period = STM32WB_TIM_GETPERIOD(priv->tim); + clock = STM32_TIM_GETCLOCK(priv->tim); + period = STM32_TIM_GETPERIOD(priv->tim); if (clock == 1000000) { @@ -305,13 +305,13 @@ static int stm32wb_getstatus(struct timer_lowerhalf_s *lower, /* Get the time remaining until the timer expires (in microseconds) */ clock_factor = clock / 1000000; - status->timeleft = (timeout - STM32WB_TIM_GETCOUNTER(priv->tim)) * + status->timeleft = (timeout - STM32_TIM_GETCOUNTER(priv->tim)) * clock_factor; return OK; } /**************************************************************************** - * Name: stm32wb_settimeout + * Name: stm32_settimeout * * Description: * Set a new timeout value (and reset the timer) @@ -326,10 +326,10 @@ static int stm32wb_getstatus(struct timer_lowerhalf_s *lower, * ****************************************************************************/ -static int stm32wb_settimeout(struct timer_lowerhalf_s *lower, +static int stm32_settimeout(struct timer_lowerhalf_s *lower, uint32_t timeout) { - struct stm32wb_lowerhalf_s *priv = (struct stm32wb_lowerhalf_s *)lower; + struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; uint64_t maxtimeout; if (priv->started) @@ -341,20 +341,20 @@ static int stm32wb_settimeout(struct timer_lowerhalf_s *lower, if (timeout > maxtimeout) { uint64_t freq = (maxtimeout * 1000000) / timeout; - STM32WB_TIM_SETCLOCK(priv->tim, freq); - STM32WB_TIM_SETPERIOD(priv->tim, maxtimeout); + STM32_TIM_SETCLOCK(priv->tim, freq); + STM32_TIM_SETPERIOD(priv->tim, maxtimeout); } else { - STM32WB_TIM_SETCLOCK(priv->tim, 1000000); - STM32WB_TIM_SETPERIOD(priv->tim, timeout); + STM32_TIM_SETCLOCK(priv->tim, 1000000); + STM32_TIM_SETPERIOD(priv->tim, timeout); } return OK; } /**************************************************************************** - * Name: stm32wb_sethandler + * Name: stm32_sethandler * * Description: * Call this user provided timeout handler. @@ -373,10 +373,10 @@ static int stm32wb_settimeout(struct timer_lowerhalf_s *lower, * ****************************************************************************/ -static void stm32wb_setcallback(struct timer_lowerhalf_s *lower, +static void stm32_setcallback(struct timer_lowerhalf_s *lower, tccb_t callback, void *arg) { - struct stm32wb_lowerhalf_s *priv = (struct stm32wb_lowerhalf_s *)lower; + struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; irqstate_t flags = enter_critical_section(); /* Save the new callback */ @@ -386,13 +386,13 @@ static void stm32wb_setcallback(struct timer_lowerhalf_s *lower, if (callback != NULL && priv->started) { - STM32WB_TIM_SETISR(priv->tim, stm32wb_timer_handler, priv, 0); - STM32WB_TIM_ENABLEINT(priv->tim, GTIM_DIER_UIE); + STM32_TIM_SETISR(priv->tim, stm32_timer_handler, priv, 0); + STM32_TIM_ENABLEINT(priv->tim, GTIM_DIER_UIE); } else { - STM32WB_TIM_DISABLEINT(priv->tim, GTIM_DIER_UIE); - STM32WB_TIM_SETISR(priv->tim, NULL, NULL, 0); + STM32_TIM_DISABLEINT(priv->tim, GTIM_DIER_UIE); + STM32_TIM_SETISR(priv->tim, NULL, NULL, 0); } leave_critical_section(flags); @@ -403,7 +403,7 @@ static void stm32wb_setcallback(struct timer_lowerhalf_s *lower, ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_timer_initialize + * Name: stm32_timer_initialize * * Description: * Bind the configuration timer to a timer lower half instance and @@ -420,31 +420,31 @@ static void stm32wb_setcallback(struct timer_lowerhalf_s *lower, * ****************************************************************************/ -int stm32wb_timer_initialize(const char *devpath, int timer) +int stm32_timer_initialize(const char *devpath, int timer) { - struct stm32wb_lowerhalf_s *lower; + struct stm32_lowerhalf_s *lower; switch (timer) { -#ifdef CONFIG_STM32WB_TIM1 +#ifdef CONFIG_STM32_TIM1 case 1: lower = &g_tim1_lowerhalf; break; #endif -#ifdef CONFIG_STM32WB_TIM2 +#ifdef CONFIG_STM32_TIM2 case 2: lower = &g_tim2_lowerhalf; break; #endif -#ifdef CONFIG_STM32WB_TIM16 +#ifdef CONFIG_STM32_TIM16 case 16: lower = &g_tim16_lowerhalf; break; #endif -#ifdef CONFIG_STM32WB_TIM17 +#ifdef CONFIG_STM32_TIM17 case 17: lower = &g_tim17_lowerhalf; break; @@ -458,7 +458,7 @@ int stm32wb_timer_initialize(const char *devpath, int timer) lower->started = false; lower->callback = NULL; - lower->tim = stm32wb_tim_init(timer); + lower->tim = stm32_tim_init(timer); if (lower->tim == NULL) { diff --git a/arch/arm/src/stm32wb/stm32wb_timerisr.c b/arch/arm/src/stm32wb/stm32wb_timerisr.c index c9dc2cc473866..ea28a500667ed 100644 --- a/arch/arm/src/stm32wb/stm32wb_timerisr.c +++ b/arch/arm/src/stm32wb/stm32wb_timerisr.c @@ -56,12 +56,12 @@ * And I don't know now to re-configure it yet */ -#undef CONFIG_STM32WB_SYSTICK_HCLKd8 +#undef CONFIG_STM32_SYSTICK_HCLKd8 -#ifdef CONFIG_STM32WB_SYSTICK_HCLKd8 -# define SYSTICK_RELOAD ((STM32WB_HCLK_FREQUENCY / 8 / CLK_TCK) - 1) +#ifdef CONFIG_STM32_SYSTICK_HCLKd8 +# define SYSTICK_RELOAD ((STM32_HCLK_FREQUENCY / 8 / CLK_TCK) - 1) #else -# define SYSTICK_RELOAD ((STM32WB_HCLK_FREQUENCY / CLK_TCK) - 1) +# define SYSTICK_RELOAD ((STM32_HCLK_FREQUENCY / CLK_TCK) - 1) #endif /* The size of the reload field is 24 bits. Verify that the reload value @@ -77,7 +77,7 @@ ****************************************************************************/ /**************************************************************************** - * Function: stm32wb_timerisr + * Function: stm32_timerisr * * Description: * The timer ISR will perform a variety of services for various portions @@ -85,7 +85,7 @@ * ****************************************************************************/ -static int stm32wb_timerisr(int irq, uint32_t *regs, void *arg) +static int stm32_timerisr(int irq, uint32_t *regs, void *arg) { /* Process timer interrupt */ @@ -121,7 +121,7 @@ void up_timer_initialize(void) #if 0 /* Does not work. Comes up with HCLK source and I can't change it */ regval = getreg32(NVIC_SYSTICK_CTRL); -#ifdef CONFIG_STM32WB_SYSTICK_HCLKd8 +#ifdef CONFIG_STM32_SYSTICK_HCLKd8 regval &= ~NVIC_SYSTICK_CTRL_CLKSOURCE; #else regval |= NVIC_SYSTICK_CTRL_CLKSOURCE; @@ -135,7 +135,7 @@ void up_timer_initialize(void) /* Attach the timer interrupt vector */ - irq_attach(STM32WB_IRQ_SYSTICK, (xcpt_t)stm32wb_timerisr, NULL); + irq_attach(STM32_IRQ_SYSTICK, (xcpt_t)stm32_timerisr, NULL); /* Enable SysTick interrupts */ @@ -144,5 +144,5 @@ void up_timer_initialize(void) /* And enable the timer interrupt */ - up_enable_irq(STM32WB_IRQ_SYSTICK); + up_enable_irq(STM32_IRQ_SYSTICK); } diff --git a/arch/arm/src/stm32wb/stm32wb_uart.h b/arch/arm/src/stm32wb/stm32wb_uart.h index dc4e2dadff446..c2745718b5ce6 100644 --- a/arch/arm/src/stm32wb/stm32wb_uart.h +++ b/arch/arm/src/stm32wb/stm32wb_uart.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_STC_STM32WB_STM32WB_UART_H -#define __ARCH_ARM_STC_STM32WB_STM32WB_UART_H +#ifndef __ARCH_ARM_SRC_STM32WB_STM32_UART_H +#define __ARCH_ARM_SRC_STM32WB_STM32_UART_H /**************************************************************************** * Included Files @@ -39,28 +39,28 @@ /* Sanity checks */ -#if !defined(CONFIG_STM32WB_LPUART1) -# undef CONFIG_STM32WB_LPUART1_SERIALDRIVER -# undef CONFIG_STM32WB_LPUART1_1WIREDRIVER +#if !defined(CONFIG_STM32_LPUART1) +# undef CONFIG_STM32_LPUART1_SERIALDRIVER +# undef CONFIG_STM32_LPUART1_1WIREDRIVER #endif -#if !defined(CONFIG_STM32WB_USART1) -# undef CONFIG_STM32WB_USART1_SERIALDRIVER -# undef CONFIG_STM32WB_USART1_1WIREDRIVER +#if !defined(CONFIG_STM32_USART1) +# undef CONFIG_STM32_USART1_SERIALDRIVER +# undef CONFIG_STM32_USART1_1WIREDRIVER #endif /* Is there a USART enabled? */ -#if defined(CONFIG_STM32WB_LPUART1) || defined(CONFIG_STM32WB_USART1) +#if defined(CONFIG_STM32_LPUART1) || defined(CONFIG_STM32_USART1) # define HAVE_UART 1 #endif /* Is there a serial console? */ -#if defined(CONFIG_LPUART1_SERIAL_CONSOLE) && defined(CONFIG_STM32WB_LPUART1_SERIALDRIVER) +#if defined(CONFIG_LPUART1_SERIAL_CONSOLE) && defined(CONFIG_STM32_LPUART1_SERIALDRIVER) # undef CONFIG_USART1_SERIAL_CONSOLE # define CONSOLE_UART 1 # define HAVE_CONSOLE 1 -#elif defined(CONFIG_USART1_SERIAL_CONSOLE) && defined(CONFIG_STM32WB_USART1_SERIALDRIVER) +#elif defined(CONFIG_USART1_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART1_SERIALDRIVER) # undef CONFIG_LPUART1_SERIAL_CONSOLE # define CONSOLE_UART 2 # define HAVE_CONSOLE 1 @@ -82,11 +82,11 @@ /* Disable the DMA configuration on all unused USARTs */ -#ifndef CONFIG_STM32WB_LPUART1_SERIALDRIVER +#ifndef CONFIG_STM32_LPUART1_SERIALDRIVER # undef CONFIG_LPUART1_RXDMA #endif -#ifndef CONFIG_STM32WB_USART1_SERIALDRIVER +#ifndef CONFIG_STM32_USART1_SERIALDRIVER # undef CONFIG_USART1_RXDMA #endif @@ -109,9 +109,9 @@ /* Is DMA used on all (enabled) USARTs */ #define SERIAL_HAVE_ONLY_DMA 1 -#if defined(CONFIG_STM32WB_LPUART1_SERIALDRIVER) && !defined(CONFIG_LPUART1_RXDMA) +#if defined(CONFIG_STM32_LPUART1_SERIALDRIVER) && !defined(CONFIG_LPUART1_RXDMA) # undef SERIAL_HAVE_ONLY_DMA -#elif defined(CONFIG_STM32WB_USART1_SERIALDRIVER) && !defined(CONFIG_USART1_RXDMA) +#elif defined(CONFIG_STM32_USART1_SERIALDRIVER) && !defined(CONFIG_USART1_RXDMA) # undef SERIAL_HAVE_ONLY_DMA #endif @@ -151,7 +151,7 @@ extern "C" ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_serial_dma_poll + * Name: stm32_serial_dma_poll * * Description: * Must be called periodically if any STM32WB UART is configured for DMA. @@ -164,7 +164,7 @@ extern "C" ****************************************************************************/ #ifdef SERIAL_HAVE_RXDMA -void stm32wb_serial_dma_poll(void); +void stm32_serial_dma_poll(void); #endif #undef EXTERN @@ -173,4 +173,4 @@ void stm32wb_serial_dma_poll(void); #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_STC_STM32WB_STM32WB_UART_H */ +#endif /* __ARCH_ARM_SRC_STM32WB_STM32_UART_H */ diff --git a/arch/arm/src/stm32wb/stm32wb_uid.c b/arch/arm/src/stm32wb/stm32wb_uid.c deleted file mode 100644 index 22e781f8c6f77..0000000000000 --- a/arch/arm/src/stm32wb/stm32wb_uid.c +++ /dev/null @@ -1,48 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32wb/stm32wb_uid.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "hardware/stm32wb_memorymap.h" -#include "stm32wb_uid.h" - -#ifdef STM32WB_SYSMEM_UID - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -void stm32wb_get_uniqueid(uint8_t uniqueid[12]) -{ - int i; - - for (i = 0; i < 12; i++) - { - uniqueid[i] = *((uint8_t *)(STM32WB_SYSMEM_UID) + i); - } -} - -#endif /* STM32WB_SYSMEM_UID */ diff --git a/arch/arm/src/stm32wb/stm32wb_uid.h b/arch/arm/src/stm32wb/stm32wb_uid.h deleted file mode 100644 index e1f01292df57e..0000000000000 --- a/arch/arm/src/stm32wb/stm32wb_uid.h +++ /dev/null @@ -1,38 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32wb/stm32wb_uid.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32WB_STM32WB_UID_H -#define __ARCH_ARM_SRC_STM32WB_STM32WB_UID_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -void stm32wb_get_uniqueid(uint8_t uniqueid[12]); - -#endif /* __ARCH_ARM_SRC_STM32WB_STM32WB_UID_H */ diff --git a/arch/arm/src/stm32wb/stm32wb_userspace.c b/arch/arm/src/stm32wb/stm32wb_userspace.c index 6f9a3451e63dc..e07473c8d67a2 100644 --- a/arch/arm/src/stm32wb/stm32wb_userspace.c +++ b/arch/arm/src/stm32wb/stm32wb_userspace.c @@ -41,7 +41,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_userspace + * Name: stm32_userspace * * Description: * For the case of the separate user-/kernel-space build, perform whatever @@ -51,7 +51,7 @@ * ****************************************************************************/ -void stm32wb_userspace(void) +void stm32_userspace(void) { uint8_t *src; uint8_t *dest; @@ -87,7 +87,7 @@ void stm32wb_userspace(void) /* Configure the MPU to permit user-space access to its FLASH and RAM */ - stm32wb_mpuinitialize(); + stm32_mpuinitialize(); } #endif /* CONFIG_BUILD_PROTECTED */ diff --git a/arch/arm/src/stm32wb/stm32wb_userspace.h b/arch/arm/src/stm32wb/stm32wb_userspace.h index 4a428e9b7c892..67f2b2dbb7200 100644 --- a/arch/arm/src/stm32wb/stm32wb_userspace.h +++ b/arch/arm/src/stm32wb/stm32wb_userspace.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32W_STM32W_USERSPACE_H -#define __ARCH_ARM_SRC_STM32W_STM32W_USERSPACE_H +#ifndef __ARCH_ARM_SRC_STM32WB_STM32W_USERSPACE_H +#define __ARCH_ARM_SRC_STM32WB_STM32W_USERSPACE_H /**************************************************************************** * Included Files @@ -34,7 +34,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_userspace + * Name: stm32_userspace * * Description: * For the case of the separate user-/kernel-space build, perform whatever @@ -45,7 +45,7 @@ ****************************************************************************/ #ifdef CONFIG_BUILD_PROTECTED -void stm32wb_userspace(void); +void stm32_userspace(void); #endif -#endif /* __ARCH_ARM_SRC_STM32W_STM32W_USERSPACE_H */ +#endif /* __ARCH_ARM_SRC_STM32WB_STM32W_USERSPACE_H */ diff --git a/arch/arm/src/stm32wb/stm32wb_waste.c b/arch/arm/src/stm32wb/stm32wb_waste.c deleted file mode 100644 index 48f022c7d4811..0000000000000 --- a/arch/arm/src/stm32wb/stm32wb_waste.c +++ /dev/null @@ -1,46 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32wb/stm32wb_waste.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include "stm32wb_waste.h" - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -uint32_t g_waste_counter; - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -void stm32wb_waste(void) -{ - g_waste_counter++; -} diff --git a/arch/arm/src/stm32wb/stm32wb_waste.h b/arch/arm/src/stm32wb/stm32wb_waste.h deleted file mode 100644 index 97660bf160892..0000000000000 --- a/arch/arm/src/stm32wb/stm32wb_waste.h +++ /dev/null @@ -1,66 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32wb/stm32wb_waste.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32WB_STM32WB_WASTE_H -#define __ARCH_ARM_SRC_STM32WB_STM32WB_WASTE_H - -/* Waste CPU Time */ - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#ifndef __ASSEMBLY__ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/* Waste CPU Time - * - * stm32wb_waste() is the logic that will be executed when portions of - * kernel or user-app is polling some register or similar, waiting for - * desired status. This time is wasted away. This function offers a - * measure of badly written piece of software or some undesired behavior. - * - * At the same time this function adds to some IDLE time which portion - * cannot be used for other purposes (yet). - */ - -void stm32wb_waste(void); - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32WB_STM32WB_WASTE_H */ diff --git a/arch/arm/src/stm32wl5/CMakeLists.txt b/arch/arm/src/stm32wl5/CMakeLists.txt index 86a13b68e1ef9..b13a427ce34d6 100644 --- a/arch/arm/src/stm32wl5/CMakeLists.txt +++ b/arch/arm/src/stm32wl5/CMakeLists.txt @@ -31,8 +31,6 @@ set(SRCS stm32wl5_rcc.c stm32wl5_serial.c stm32wl5_start.c - stm32wl5_waste.c - stm32wl5_uid.c stm32wl5_lse.c stm32wl5_lsi.c stm32wl5_idle.c @@ -42,8 +40,10 @@ set(SRCS stm32wl5_timerisr.c stm32wl5_spi.c) -if(CONFIG_STM32WL5_IPCC) +if(CONFIG_STM32_IPCC) list(APPEND SRCS stm32wl5_ipcc.c) endif() target_sources(arch PRIVATE ${SRCS}) + +add_subdirectory(${NUTTX_DIR}/arch/arm/src/common/stm32 stm32_common) diff --git a/arch/arm/src/stm32wl5/Kconfig b/arch/arm/src/stm32wl5/Kconfig index 99e5a6cd68b26..eee194b3ad43b 100644 --- a/arch/arm/src/stm32wl5/Kconfig +++ b/arch/arm/src/stm32wl5/Kconfig @@ -7,6 +7,11 @@ if ARCH_CHIP_STM32WL5 comment "STM32WL5 Configuration Options" +config STM32_WL5_PERIPHERALS + bool + default ARCH_CHIP_STM32WL5 + select STM32_HAVE_SYSCFG + choice prompt "STM32 WL5 Chip Selection" default ARCH_CHIP_STM32WL55JC_CPU1 @@ -14,396 +19,34 @@ choice config ARCH_CHIP_STM32WL55JC_CPU1 bool "STM32WL55JC (cpu1)" - select STM32WL5_STM32WL5XXX_CPU1 - select STM32WL5_STM32WL5XXX - select STM32WL5_FLASH_CONFIG_C + select STM32_STM32WL5XXX_CPU1 + select STM32_STM32WL5XXX + select STM32_FLASH_CONFIG_C ---help--- STM32 WL5 Cortex M4 (cpu1), 256kiB FLASH, 64kiB SRAM config ARCH_CHIP_STM32WL55JC_CPU2 bool "STM32WL55JC (cpu2)" - select STM32WL5_STM32WL5XXX_CPU2 - select STM32WL5_STM32WL5XXX - select STM32WL5_FLASH_CONFIG_C + select STM32_STM32WL5XXX_CPU2 + select STM32_STM32WL5XXX + select STM32_FLASH_CONFIG_C ---help--- STM32 WL5 Cortex M0 (cpu2), 256kiB FLASH, 64kiB SRAM - endchoice # STM32 WL5 Chip Selection # Chip product lines -config STM32WL5_STM32WL5XXX +config STM32_STM32WL5XXX bool -config STM32WL5_STM32WL5XXX_CPU1 +config STM32_STM32WL5XXX_CPU1 bool default y - select STM32WL5_HAVE_USART1 - select STM32WL5_HAVE_USART2 - select STM32WL5_HAVE_LPUART1 - select STM32WL5_HAVE_SPI1 - select STM32WL5_HAVE_SPI2S2 - - -comment "STM32WL5 Peripherals" - -menu "STM32WL5 Peripheral Support" - -choice - prompt "Override Flash Size Designator" - depends on ARCH_CHIP_STM32WL5 - default STM32WL5_FLASH_OVERRIDE_DEFAULT - ---help--- - STM32WL5 series parts numbering (sans the package type) ends with a letter - that designates the FLASH size. - - Designator Size in KiB - 8 64 - B 128 - C 256 - E 512 - G 1024 - I 2048 - - This configuration option defaults to using the configuration based on that designator - or the default smaller size if there is no last character designator is present in the - STM32 Chip Selection. - - Examples: - If the STM32WL55JC is chosen, the Flash configuration would be 'C', if a variant of - the part with a 1024 KiB Flash is released in the future one could simply select - the 'G' designator here. - - If an STM32WL5xxx Series parts is chosen the default Flash configuration will be set - herein and can be changed. - -config STM32WL5_FLASH_OVERRIDE_DEFAULT - bool "Default" - -config STM32WL5_FLASH_OVERRIDE_8 - bool "8 64 KB" - -config STM32WL5_FLASH_OVERRIDE_B - bool "B 128 KB" - -config STM32WL5_FLASH_OVERRIDE_C - bool "C 256 KB" - -config STM32WL5_FLASH_OVERRIDE_E - bool "E 512 KB" - -config STM32WL5_FLASH_OVERRIDE_G - bool "G 1024 KB" - -endchoice # "Override Flash Size Designator" - -# Flash configurations - -config STM32WL5_FLASH_CONFIG_8 - bool - default n - -config STM32WL5_FLASH_CONFIG_B - bool - default n - -config STM32WL5_FLASH_CONFIG_C - bool - default n - -config STM32WL5_FLASH_CONFIG_E - bool - default n - -config STM32WL5_FLASH_CONFIG_G - bool - default n - -# These "hidden" settings determine whether a peripheral option is available -# for the selected MCU - -config STM32WL5_HAVE_USART1 - bool - default n - -config STM32WL5_HAVE_USART2 - bool - default n - -config STM32WL5_HAVE_LPUART1 - bool - default n - -config STM32WL5_HAVE_SPI1 - bool - default n - -config STM32WL5_HAVE_SPI2S2 - bool - default n - -# These "hidden" settings are the OR of individual peripheral selections -# indicating that the general capability is required. - -config STM32WL5_USART - bool - default n - -config STM32WL5_SPI - bool - default n - -config STM32WL5_SPI_DMA - bool - default n - -# These are the peripheral selections proper - -comment "APB1 Peripherals" - -config STM32WL5_USART2 - bool "USART2" - default n - depends on STM32WL5_HAVE_USART2 - select ARCH_HAVE_SERIAL_TERMIOS - select STM32WL5_USART - -config STM32WL5_LPUART1 - bool "LPUART1" - default n - depends on STM32WL5_HAVE_LPUART1 - select ARCH_HAVE_SERIAL_TERMIOS - select STM32WL5_USART - -config STM32WL5_SPI2S2 - bool "SPI2S2" - default n - depends on STM32WL5_HAVE_SPI2S2 - select STM32WL5_SPI - -comment "APB2 Peripherals" - -config STM32WL5_SYSCFG - bool "SYSCFG" - default y - -config STM32WL5_USART1 - bool "USART1" - default n - depends on STM32WL5_HAVE_USART1 - select ARCH_HAVE_SERIAL_TERMIOS - select STM32WL5_USART - -config STM32WL5_SPI1 - bool "SPI1" - default n - depends on STM32WL5_HAVE_SPI1 - select STM32WL5_SPI - -comment "AHB3 Peripherals" - -config STM32WL5_IPCC - bool "IPCC" - select IPCC - default n - ---help--- - IPCC - Inter Processor Communication Controller. A very simple - character device stream driver to exchange data between - CM0 and CM4. - -endmenu # STM32WL5 Peripheral Support - - -config STM32WL5_SERIALDRIVER - bool - -menu "[LP]U[S]ART Configuration" - depends on STM32WL5_USART - -choice - prompt "USART1 Driver Configuration" - default STM32WL5_USART1_SERIALDRIVER - depends on STM32WL5_USART1 - -config STM32WL5_USART1_SERIALDRIVER - bool "Standard serial driver" - select USART1_SERIALDRIVER - select STM32WL5_SERIALDRIVER - -endchoice # USART1 Driver Configuration - -choice - prompt "USART2 Driver Configuration" - default STM32WL5_USART2_SERIALDRIVER - depends on STM32WL5_USART2 - -config STM32WL5_USART2_SERIALDRIVER - bool "Standard serial driver" - select USART2_SERIALDRIVER - select STM32WL5_SERIALDRIVER - -endchoice # USART2 Driver Configuration - -choice - prompt "LPUART1 Driver Configuration" - default STM32WL5_LPUART1_SERIALDRIVER - depends on STM32WL5_LPUART1 - -config STM32WL5_LPUART1_SERIALDRIVER - bool "Standard serial driver" - select LPUART1_SERIALDRIVER - select STM32WL5_SERIALDRIVER - -endchoice # LPUART1 Driver Configuration - -endmenu # [LP]U[S]ART Configuration - -menu "SPI Configuration" - depends on STM32WL5_SPI - -config STM32WL5_SPI_INTERRUPTS - bool "Interrupt driver SPI" - default n - ---help--- - Select to enable interrupt driven SPI support. Non-interrupt-driven, - poll-waiting is recommended if the interrupt rate would be to high in - the interrupt driven case. - -config STM32WL5_SPI1_DMA - bool "SPI1 DMA" - default n - depends on STM32WL5_SPI1 && !STM32WL5_SPI_INTERRUPT - select STM32WL5_SPI_DMA - ---help--- - Use DMA to improve SPI1 transfer performance. Cannot be used with STM32WL5_SPI_INTERRUPT. - -config STM32WL5_SPI1_DMA_BUFFER - int "SPI1 DMA buffer size" - default 0 - depends on STM32WL5_SPI1_DMA - ---help--- - Add a properly aligned DMA buffer for RX and TX DMA for SPI1. - -config STM32WL5_SPI_DMATHRESHOLD - int "SPI DMA threshold" - default 4 - depends on STM32WL5_SPI_DMA - ---help--- - When SPI DMA is enabled, small DMA transfers will still be performed - by polling logic. But we need a threshold value to determine what - is small. - -config STM32WL5_SPI2S2_DMA - bool "SPI2S2 DMA" - default n - depends on STM32WL5_SPI2 && !STM32WL5_SPI_INTERRUPT - select STM32WL5_SPI_DMA - ---help--- - Use DMA to improve SPI2S2 transfer performance. Cannot be used with STM32WL5_SPI_INTERRUPT. - -config STM32WL5_SPI2S2_DMA_BUFFER - int "SPI2S2 DMA buffer size" - default 0 - depends on STM32WL5_SPI2S2_DMA - ---help--- - Add a properly aligned DMA buffer for RX and TX DMA for SPI2S2. - -endmenu # SPI Configuration - -menu "IPCC Configuration" - depends on STM32WL5_IPCC - -config STM32WL5_IPCC_CHAN1_RX_SIZE - int "Channel 1 RX size" - default 256 - ---help--- - Size of the receive buffer. Another CPU will write to this - buffer and currently running CPU will read from it. - -config STM32WL5_IPCC_CHAN1_TX_SIZE - int "Channel 1 TX size" - default 256 - ---help--- - Size of the send buffer. Another CPU will read from this - buffer and currently running CPU will write to it. - -config STM32WL5_IPCC_CHAN2 - bool "Enable channel 2" - default n - -if STM32WL5_IPCC_CHAN2 - -config STM32WL5_IPCC_CHAN2_RX_SIZE - int "Channel 2 RX size" - default 256 - -config STM32WL5_IPCC_CHAN2_TX_SIZE - int "Channel 2 TX size" - default 256 - -config STM32WL5_IPCC_CHAN3 - bool "Enable channel 3" - default n - -if STM32WL5_IPCC_CHAN3 - -config STM32WL5_IPCC_CHAN3_RX_SIZE - int "Channel 3 RX size" - default 256 - -config STM32WL5_IPCC_CHAN3_TX_SIZE - int "Channel 3 TX size" - default 256 - -config STM32WL5_IPCC_CHAN4 - bool "Enable channel 4" - default n - -if STM32WL5_IPCC_CHAN4 - -config STM32WL5_IPCC_CHAN4_RX_SIZE - int "Channel 4 RX size" - default 256 - -config STM32WL5_IPCC_CHAN4_TX_SIZE - int "Channel 4 TX size" - default 256 - -config STM32WL5_IPCC_CHAN5 - bool "Enable channel 5" - default n - -if STM32WL5_IPCC_CHAN5 - -config STM32WL5_IPCC_CHAN5_RX_SIZE - int "Channel 5 RX size" - default 256 - -config STM32WL5_IPCC_CHAN5_TX_SIZE - int "Channel 5 TX size" - default 256 - -config STM32WL5_IPCC_CHAN6 - bool "Enable channel 6" - default n - -if STM32WL5_IPCC_CHAN6 - -config STM32WL5_IPCC_CHAN6_RX_SIZE - int "Channel 6 RX size" - default 256 - -config STM32WL5_IPCC_CHAN6_TX_SIZE - int "Channel 6 TX size" - default 256 - -endif # STM32WL5_IPCC_CHAN2 -endif # STM32WL5_IPCC_CHAN3 -endif # STM32WL5_IPCC_CHAN4 -endif # STM32WL5_IPCC_CHAN5 -endif # STM32WL5_IPCC_CHAN6 - -endmenu # IPCC Configuration + select STM32_HAVE_USART1 + select STM32_HAVE_USART2 + select STM32_HAVE_LPUART1 + select STM32_HAVE_SPI1 + select STM32_HAVE_SPI2S2 endif # ARCH_CHIP_STM32WL5 diff --git a/arch/arm/src/stm32wl5/Make.defs b/arch/arm/src/stm32wl5/Make.defs index fc265b697ae57..d61921e8c127b 100644 --- a/arch/arm/src/stm32wl5/Make.defs +++ b/arch/arm/src/stm32wl5/Make.defs @@ -26,16 +26,17 @@ # Common ARM and Cortex-M4 files (copied from stm32/Make.defs) include armv7-m/Make.defs +include common/stm32/Make.defs # Required STM32WL5 files -CHIP_CSRCS = stm32wl5_allocateheap.c stm32wl5_exti_gpio.c stm32wl5_gpio.c +CHIP_CSRCS += stm32wl5_allocateheap.c stm32wl5_exti_gpio.c stm32wl5_gpio.c CHIP_CSRCS += stm32wl5_irq.c stm32wl5_lowputc.c stm32wl5_rcc.c -CHIP_CSRCS += stm32wl5_serial.c stm32wl5_start.c stm32wl5_waste.c stm32wl5_uid.c +CHIP_CSRCS += stm32wl5_serial.c stm32wl5_start.c CHIP_CSRCS += stm32wl5_lse.c stm32wl5_lsi.c stm32wl5_idle.c CHIP_CSRCS += stm32wl5_pwr.c stm32wl5_tim.c stm32wl5_flash.c stm32wl5_timerisr.c CHIP_CSRCS += stm32wl5_spi.c -CSRCS-$(CONFIG_STM32WL5_IPCC) = stm32wl5_ipcc.c +CSRCS-$(CONFIG_STM32_IPCC) = stm32wl5_ipcc.c CHIP_CSRCS += $(CSRCS-y) diff --git a/arch/arm/src/stm32wl5/chip.h b/arch/arm/src/stm32wl5/chip.h index b9f0208954f43..cfb6d0903edd9 100644 --- a/arch/arm/src/stm32wl5/chip.h +++ b/arch/arm/src/stm32wl5/chip.h @@ -49,7 +49,7 @@ * arch/stm32wl5/chip.h header file. */ -#define ARMV7M_PERIPHERAL_INTERRUPTS STM32WL5_IRQ_NEXTINTS +#define ARMV7M_PERIPHERAL_INTERRUPTS STM32_IRQ_NEXTINTS /* Cache line sizes (in bytes) for the STM32WL5 */ diff --git a/arch/arm/src/stm32wl5/hardware/stm32wl5_exti.h b/arch/arm/src/stm32wl5/hardware/stm32wl5_exti.h index 3a3b11d974c51..d1f8cb8e886b8 100644 --- a/arch/arm/src/stm32wl5/hardware/stm32wl5_exti.h +++ b/arch/arm/src/stm32wl5/hardware/stm32wl5_exti.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32WL5_HARDWARE_STM32WL5_EXTI_H -#define __ARCH_ARM_SRC_STM32WL5_HARDWARE_STM32WL5_EXTI_H +#ifndef __ARCH_ARM_SRC_STM32WL5_HARDWARE_STM32_EXTI_H +#define __ARCH_ARM_SRC_STM32WL5_HARDWARE_STM32_EXTI_H /**************************************************************************** * Included Files @@ -34,48 +34,48 @@ * Pre-processor Definitions ****************************************************************************/ -#define STM32WL5_NEXTI1 31 -#define STM32WL5_EXTI1_MASK 0xffffffff -#define STM32WL5_NEXTI2 9 -#define STM32WL5_EXTI2_MASK 0x000001ff +#define STM32_NEXTI1 31 +#define STM32_EXTI1_MASK 0xffffffff +#define STM32_NEXTI2 9 +#define STM32_EXTI2_MASK 0x000001ff /* Register Offsets *********************************************************/ -#define STM32WL5_EXTI_RTSR1_OFFSET 0x0000 /* Rising trigger selection 1 */ -#define STM32WL5_EXTI_FTSR1_OFFSET 0x0004 /* Falling trigger selection 1 */ -#define STM32WL5_EXTI_SWIER1_OFFSET 0x0008 /* Software interrupt event 1 */ -#define STM32WL5_EXTI_PR1_OFFSET 0x000c /* Pending 1 */ -#define STM32WL5_EXTI_RTSR2_OFFSET 0x0020 /* Rising trigger selection 2 */ -#define STM32WL5_EXTI_FTSR2_OFFSET 0x0024 /* Falling trigger selection 2 */ -#define STM32WL5_EXTI_SWIER2_OFFSET 0x0028 /* Software interrupt event 2 */ -#define STM32WL5_EXTI_PR2_OFFSET 0x002c /* Pending 2 */ -#define STM32WL5_EXTI_C1IMR1_OFFSET 0x0080 /* Interrupt mask 1 for cpu1 */ -#define STM32WL5_EXTI_C1EMR1_OFFSET 0x0084 /* Event mask 1 for cpu1 */ -#define STM32WL5_EXTI_C1IMR2_OFFSET 0x0090 /* Interrupt mask 2 for cpu1 */ -#define STM32WL5_EXTI_C1EMR2_OFFSET 0x0094 /* Event mask 2 for cpu1 */ -#define STM32WL5_EXTI_C2IMR1_OFFSET 0x00c0 /* Interrupt mask 1 for cpu2 */ -#define STM32WL5_EXTI_C2EMR1_OFFSET 0x00c4 /* Event mask 1 for cpu2 */ -#define STM32WL5_EXTI_C2IMR2_OFFSET 0x00d0 /* Interrupt mask 2 for cpu2 */ -#define STM32WL5_EXTI_C2EMR2_OFFSET 0x00d4 /* Event mask 2 for cpu2 */ +#define STM32_EXTI_RTSR1_OFFSET 0x0000 /* Rising trigger selection 1 */ +#define STM32_EXTI_FTSR1_OFFSET 0x0004 /* Falling trigger selection 1 */ +#define STM32_EXTI_SWIER1_OFFSET 0x0008 /* Software interrupt event 1 */ +#define STM32_EXTI_PR1_OFFSET 0x000c /* Pending 1 */ +#define STM32_EXTI_RTSR2_OFFSET 0x0020 /* Rising trigger selection 2 */ +#define STM32_EXTI_FTSR2_OFFSET 0x0024 /* Falling trigger selection 2 */ +#define STM32_EXTI_SWIER2_OFFSET 0x0028 /* Software interrupt event 2 */ +#define STM32_EXTI_PR2_OFFSET 0x002c /* Pending 2 */ +#define STM32_EXTI_C1IMR1_OFFSET 0x0080 /* Interrupt mask 1 for cpu1 */ +#define STM32_EXTI_C1EMR1_OFFSET 0x0084 /* Event mask 1 for cpu1 */ +#define STM32_EXTI_C1IMR2_OFFSET 0x0090 /* Interrupt mask 2 for cpu1 */ +#define STM32_EXTI_C1EMR2_OFFSET 0x0094 /* Event mask 2 for cpu1 */ +#define STM32_EXTI_C2IMR1_OFFSET 0x00c0 /* Interrupt mask 1 for cpu2 */ +#define STM32_EXTI_C2EMR1_OFFSET 0x00c4 /* Event mask 1 for cpu2 */ +#define STM32_EXTI_C2IMR2_OFFSET 0x00d0 /* Interrupt mask 2 for cpu2 */ +#define STM32_EXTI_C2EMR2_OFFSET 0x00d4 /* Event mask 2 for cpu2 */ /* Register Addresses *******************************************************/ -#define STM32WL5_EXTI_RTSR1 (STM32WL5_EXTI_BASE+STM32WL5_EXTI_RTSR1_OFFSET) -#define STM32WL5_EXTI_FTSR1 (STM32WL5_EXTI_BASE+STM32WL5_EXTI_FTSR1_OFFSET) -#define STM32WL5_EXTI_SWIER1 (STM32WL5_EXTI_BASE+STM32WL5_EXTI_SWIER1_OFFSET) -#define STM32WL5_EXTI_PR1 (STM32WL5_EXTI_BASE+STM32WL5_EXTI_PR1_OFFSET) -#define STM32WL5_EXTI_RTSR2 (STM32WL5_EXTI_BASE+STM32WL5_EXTI_RTSR2_OFFSET) -#define STM32WL5_EXTI_FTSR2 (STM32WL5_EXTI_BASE+STM32WL5_EXTI_FTSR2_OFFSET) -#define STM32WL5_EXTI_SWIER2 (STM32WL5_EXTI_BASE+STM32WL5_EXTI_SWIER2_OFFSET) -#define STM32WL5_EXTI_PR2 (STM32WL5_EXTI_BASE+STM32WL5_EXTI_PR2_OFFSET) -#define STM32WL5_EXTI_C1IMR1 (STM32WL5_EXTI_BASE+STM32WL5_EXTI_C1IMR1_OFFSET) -#define STM32WL5_EXTI_C1EMR1 (STM32WL5_EXTI_BASE+STM32WL5_EXTI_C1EMR1_OFFSET) -#define STM32WL5_EXTI_C1IMR2 (STM32WL5_EXTI_BASE+STM32WL5_EXTI_C1IMR2_OFFSET) -#define STM32WL5_EXTI_C1EMR2 (STM32WL5_EXTI_BASE+STM32WL5_EXTI_C1EMR2_OFFSET) -#define STM32WL5_EXTI_C2IMR1 (STM32WL5_EXTI_BASE+STM32WL5_EXTI_C2IMR1_OFFSET) -#define STM32WL5_EXTI_C2EMR1 (STM32WL5_EXTI_BASE+STM32WL5_EXTI_C2EMR1_OFFSET) -#define STM32WL5_EXTI_C2IMR2 (STM32WL5_EXTI_BASE+STM32WL5_EXTI_C2IMR2_OFFSET) -#define STM32WL5_EXTI_C2EMR2 (STM32WL5_EXTI_BASE+STM32WL5_EXTI_C2EMR2_OFFSET) +#define STM32_EXTI_RTSR1 (STM32_EXTI_BASE+STM32_EXTI_RTSR1_OFFSET) +#define STM32_EXTI_FTSR1 (STM32_EXTI_BASE+STM32_EXTI_FTSR1_OFFSET) +#define STM32_EXTI_SWIER1 (STM32_EXTI_BASE+STM32_EXTI_SWIER1_OFFSET) +#define STM32_EXTI_PR1 (STM32_EXTI_BASE+STM32_EXTI_PR1_OFFSET) +#define STM32_EXTI_RTSR2 (STM32_EXTI_BASE+STM32_EXTI_RTSR2_OFFSET) +#define STM32_EXTI_FTSR2 (STM32_EXTI_BASE+STM32_EXTI_FTSR2_OFFSET) +#define STM32_EXTI_SWIER2 (STM32_EXTI_BASE+STM32_EXTI_SWIER2_OFFSET) +#define STM32_EXTI_PR2 (STM32_EXTI_BASE+STM32_EXTI_PR2_OFFSET) +#define STM32_EXTI_C1IMR1 (STM32_EXTI_BASE+STM32_EXTI_C1IMR1_OFFSET) +#define STM32_EXTI_C1EMR1 (STM32_EXTI_BASE+STM32_EXTI_C1EMR1_OFFSET) +#define STM32_EXTI_C1IMR2 (STM32_EXTI_BASE+STM32_EXTI_C1IMR2_OFFSET) +#define STM32_EXTI_C1EMR2 (STM32_EXTI_BASE+STM32_EXTI_C1EMR2_OFFSET) +#define STM32_EXTI_C2IMR1 (STM32_EXTI_BASE+STM32_EXTI_C2IMR1_OFFSET) +#define STM32_EXTI_C2EMR1 (STM32_EXTI_BASE+STM32_EXTI_C2EMR1_OFFSET) +#define STM32_EXTI_C2IMR2 (STM32_EXTI_BASE+STM32_EXTI_C2IMR2_OFFSET) +#define STM32_EXTI_C2EMR2 (STM32_EXTI_BASE+STM32_EXTI_C2EMR2_OFFSET) /* Register Bitfield Definitions ********************************************/ @@ -190,4 +190,4 @@ #define EXTI_C2EMR2_SHIFT (0) /* Bits Bits 0-X: Event Mask for all lines */ #define EXTI_C2EMR2_MASK (0x00000300) -#endif /* __ARCH_ARM_SRC_STM32WL5_HARDWARE_STM32WL5_EXTI_H */ +#endif /* __ARCH_ARM_SRC_STM32WL5_HARDWARE_STM32_EXTI_H */ diff --git a/arch/arm/src/stm32wl5/hardware/stm32wl5_flash.h b/arch/arm/src/stm32wl5/hardware/stm32wl5_flash.h index 0f14d1b02ae4f..808f6fb5a3cb6 100644 --- a/arch/arm/src/stm32wl5/hardware/stm32wl5_flash.h +++ b/arch/arm/src/stm32wl5/hardware/stm32wl5_flash.h @@ -35,10 +35,10 @@ /* Flash size is known from the chip selection: * - * When CONFIG_STM32WL5_FLASH_OVERRIDE_DEFAULT is set the - * CONFIG_STM32WL5_FLASH_CONFIG_x selects the default FLASH size based + * When CONFIG_STM32_FLASH_OVERRIDE_DEFAULT is set the + * CONFIG_STM32_FLASH_CONFIG_x selects the default FLASH size based * on the chip part number. This value can be overridden with - * CONFIG_STM32WL5_FLASH_OVERRIDE_x. For example: + * CONFIG_STM32_FLASH_OVERRIDE_x. For example: * * Parts STM32WL5xx8 have 64KiB of FLASH * Parts STM32WL5xxB have 128KiB of FLASH @@ -47,110 +47,110 @@ * STM32WL5xxx has only single bank flash and page size 2KiB */ -#if !defined(CONFIG_STM32WL5_FLASH_OVERRIDE_DEFAULT) && \ - !defined(CONFIG_STM32WL5_FLASH_OVERRIDE_8) && \ - !defined(CONFIG_STM32WL5_FLASH_OVERRIDE_B) && \ - !defined(CONFIG_STM32WL5_FLASH_OVERRIDE_C) && \ - !defined(CONFIG_STM32WL5_FLASH_OVERRIDE_E) && \ - !defined(CONFIG_STM32WL5_FLASH_OVERRIDE_G) && \ - !defined(CONFIG_STM32WL5_FLASH_CONFIG_8) && \ - !defined(CONFIG_STM32WL5_FLASH_CONFIG_B) && \ - !defined(CONFIG_STM32WL5_FLASH_CONFIG_C) && \ - !defined(CONFIG_STM32WL5_FLASH_CONFIG_E) && \ - !defined(CONFIG_STM32WL5_FLASH_CONFIG_G) -# define CONFIG_STM32WL5_FLASH_OVERRIDE_E +#if !defined(CONFIG_STM32_FLASH_OVERRIDE_DEFAULT) && \ + !defined(CONFIG_STM32_FLASH_OVERRIDE_8) && \ + !defined(CONFIG_STM32_FLASH_OVERRIDE_B) && \ + !defined(CONFIG_STM32_FLASH_OVERRIDE_C) && \ + !defined(CONFIG_STM32_FLASH_OVERRIDE_E) && \ + !defined(CONFIG_STM32_FLASH_OVERRIDE_G) && \ + !defined(CONFIG_STM32_FLASH_CONFIG_8) && \ + !defined(CONFIG_STM32_FLASH_CONFIG_B) && \ + !defined(CONFIG_STM32_FLASH_CONFIG_C) && \ + !defined(CONFIG_STM32_FLASH_CONFIG_E) && \ + !defined(CONFIG_STM32_FLASH_CONFIG_G) +# define CONFIG_STM32_FLASH_OVERRIDE_E # warning "Flash size not defined defaulting to 512KiB (E)" #endif /* Override of the Flash has been chosen */ -#if !defined(CONFIG_STM32WL5_FLASH_OVERRIDE_DEFAULT) -# undef CONFIG_STM32WL5_FLASH_CONFIG_8 -# undef CONFIG_STM32WL5_FLASH_CONFIG_B -# undef CONFIG_STM32WL5_FLASH_CONFIG_C -# undef CONFIG_STM32WL5_FLASH_CONFIG_E -# undef CONFIG_STM32WL5_FLASH_CONFIG_G -# if defined(CONFIG_STM32WL5_FLASH_OVERRIDE_8) -# define CONFIG_STM32WL5_FLASH_CONFIG_8 -# elif defined(CONFIG_STM32WL5_FLASH_OVERRIDE_B) -# define CONFIG_STM32WL5_FLASH_CONFIG_B -# elif defined(CONFIG_STM32WL5_FLASH_OVERRIDE_C) -# define CONFIG_STM32WL5_FLASH_CONFIG_C -# elif defined(CONFIG_STM32WL5_FLASH_OVERRIDE_E) -# define CONFIG_STM32WL5_FLASH_CONFIG_E -# elif defined(CONFIG_STM32WL5_FLASH_OVERRIDE_G) -# define CONFIG_STM32WL5_FLASH_CONFIG_G +#if !defined(CONFIG_STM32_FLASH_OVERRIDE_DEFAULT) +# undef CONFIG_STM32_FLASH_CONFIG_8 +# undef CONFIG_STM32_FLASH_CONFIG_B +# undef CONFIG_STM32_FLASH_CONFIG_C +# undef CONFIG_STM32_FLASH_CONFIG_E +# undef CONFIG_STM32_FLASH_CONFIG_G +# if defined(CONFIG_STM32_FLASH_OVERRIDE_8) +# define CONFIG_STM32_FLASH_CONFIG_8 +# elif defined(CONFIG_STM32_FLASH_OVERRIDE_B) +# define CONFIG_STM32_FLASH_CONFIG_B +# elif defined(CONFIG_STM32_FLASH_OVERRIDE_C) +# define CONFIG_STM32_FLASH_CONFIG_C +# elif defined(CONFIG_STM32_FLASH_OVERRIDE_E) +# define CONFIG_STM32_FLASH_CONFIG_E +# elif defined(CONFIG_STM32_FLASH_OVERRIDE_G) +# define CONFIG_STM32_FLASH_CONFIG_G # endif #endif /* Define the valid configuration */ -#if defined(CONFIG_STM32WL5_FLASH_CONFIG_8) /* 64 kB */ -# define STM32WL5_FLASH_NPAGES 32 -# define STM32WL5_FLASH_PAGESIZE 2048 -#elif defined(CONFIG_STM32WL5_FLASH_CONFIG_B) /* 128 kB */ -# define STM32WL5_FLASH_NPAGES 64 -# define STM32WL5_FLASH_PAGESIZE 2048 -#elif defined(CONFIG_STM32WL5_FLASH_CONFIG_C) /* 256 kB */ -# define STM32WL5_FLASH_NPAGES 128 -# define STM32WL5_FLASH_PAGESIZE 2048 -#elif defined(CONFIG_STM32WL5_FLASH_CONFIG_E) /* 512 kB */ -# define STM32WL5_FLASH_NPAGES 256 -# define STM32WL5_FLASH_PAGESIZE 2048 -#elif defined(CONFIG_STM32WL5_FLASH_CONFIG_G) /* 1 MB */ -# define STM32WL5_FLASH_NPAGES 512 -# define STM32WL5_FLASH_PAGESIZE 2048 +#if defined(CONFIG_STM32_FLASH_CONFIG_8) /* 64 kB */ +# define STM32_FLASH_NPAGES 32 +# define STM32_FLASH_PAGESIZE 2048 +#elif defined(CONFIG_STM32_FLASH_CONFIG_B) /* 128 kB */ +# define STM32_FLASH_NPAGES 64 +# define STM32_FLASH_PAGESIZE 2048 +#elif defined(CONFIG_STM32_FLASH_CONFIG_C) /* 256 kB */ +# define STM32_FLASH_NPAGES 128 +# define STM32_FLASH_PAGESIZE 2048 +#elif defined(CONFIG_STM32_FLASH_CONFIG_E) /* 512 kB */ +# define STM32_FLASH_NPAGES 256 +# define STM32_FLASH_PAGESIZE 2048 +#elif defined(CONFIG_STM32_FLASH_CONFIG_G) /* 1 MB */ +# define STM32_FLASH_NPAGES 512 +# define STM32_FLASH_PAGESIZE 2048 #else # error "unknown flash configuration!" #endif -#define STM32WL5_FLASH_SIZE (STM32WL5_FLASH_NPAGES * STM32WL5_FLASH_PAGESIZE) +#define STM32_FLASH_SIZE (STM32_FLASH_NPAGES * STM32_FLASH_PAGESIZE) /* Register Offsets *********************************************************/ -#define STM32WL5_FLASH_ACR_OFFSET 0x0000 -#define STM32WL5_FLASH_ACR2_OFFSET 0x0004 -#define STM32WL5_FLASH_KEYR_OFFSET 0x0008 -#define STM32WL5_FLASH_OPTKEYR_OFFSET 0x000c -#define STM32WL5_FLASH_SR_OFFSET 0x0010 -#define STM32WL5_FLASH_CR_OFFSET 0x0014 -#define STM32WL5_FLASH_ECCR_OFFSET 0x0018 -#define STM32WL5_FLASH_OPTR_OFFSET 0x0020 -#define STM32WL5_FLASH_PCROP1ASR_OFFSET 0x0024 -#define STM32WL5_FLASH_PCROP1AER_OFFSET 0x0028 -#define STM32WL5_FLASH_WRP1AR_OFFSET 0x002c -#define STM32WL5_FLASH_WRP1BR_OFFSET 0x0030 -#define STM32WL5_FLASH_PCROP1BSR_OFFSET 0x0034 -#define STM32WL5_FLASH_PCROP1BER_OFFSET 0x0038 -#define STM32WL5_FLASH_IPCCBR_OFFSET 0x003c -#define STM32WL5_FLASH_C2ACR_OFFSET 0x005c -#define STM32WL5_FLASH_C2SR_OFFSET 0x0060 -#define STM32WL5_FLASH_C2CR_OFFSET 0x0064 -#define STM32WL5_FLASH_SFR_OFFSET 0x0080 -#define STM32WL5_FLASH_SRRVR_OFFSET 0x0084 +#define STM32_FLASH_ACR_OFFSET 0x0000 +#define STM32_FLASH_ACR2_OFFSET 0x0004 +#define STM32_FLASH_KEYR_OFFSET 0x0008 +#define STM32_FLASH_OPTKEYR_OFFSET 0x000c +#define STM32_FLASH_SR_OFFSET 0x0010 +#define STM32_FLASH_CR_OFFSET 0x0014 +#define STM32_FLASH_ECCR_OFFSET 0x0018 +#define STM32_FLASH_OPTR_OFFSET 0x0020 +#define STM32_FLASH_PCROP1ASR_OFFSET 0x0024 +#define STM32_FLASH_PCROP1AER_OFFSET 0x0028 +#define STM32_FLASH_WRP1AR_OFFSET 0x002c +#define STM32_FLASH_WRP1BR_OFFSET 0x0030 +#define STM32_FLASH_PCROP1BSR_OFFSET 0x0034 +#define STM32_FLASH_PCROP1BER_OFFSET 0x0038 +#define STM32_FLASH_IPCCBR_OFFSET 0x003c +#define STM32_FLASH_C2ACR_OFFSET 0x005c +#define STM32_FLASH_C2SR_OFFSET 0x0060 +#define STM32_FLASH_C2CR_OFFSET 0x0064 +#define STM32_FLASH_SFR_OFFSET 0x0080 +#define STM32_FLASH_SRRVR_OFFSET 0x0084 /* Register Addresses *******************************************************/ -#define STM32WL5_FLASH_ACR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_ACR_OFFSET) -#define STM32WL5_FLASH_ACR2 (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_ACR2_OFFSET) -#define STM32WL5_FLASH_KEYR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_KEYR_OFFSET) -#define STM32WL5_FLASH_OPTKEYR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_OPTKEYR_OFFSET) -#define STM32WL5_FLASH_SR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_SR_OFFSET) -#define STM32WL5_FLASH_CR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_CR_OFFSET) -#define STM32WL5_FLASH_ECCR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_ECCR_OFFSET) -#define STM32WL5_FLASH_OPTR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_OPTR_OFFSET) -#define STM32WL5_FLASH_PCROP1ASR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_PCROP1ASR_OFFSET) -#define STM32WL5_FLASH_PCROP1AER (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_PCROP1AER_OFFSET) -#define STM32WL5_FLASH_WRP1AR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_WRP1AR_OFFSET) -#define STM32WL5_FLASH_WRP1BR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_WRP1BR_OFFSET) -#define STM32WL5_FLASH_PCROP1BSR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_PCROP1BSR_OFFSET) -#define STM32WL5_FLASH_PCROP1BER (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_PCROP1BER_OFFSET) -#define STM32WL5_FLASH_IPCCBR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_IPCCBR_OFFSET) -#define STM32WL5_FLASH_C2ACR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_C2ACR_OFFSET) -#define STM32WL5_FLASH_C2SR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_C2SR_OFFSET) -#define STM32WL5_FLASH_C2CR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_C2CR_OFFSET) -#define STM32WL5_FLASH_SFR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_SFR_OFFSET) -#define STM32WL5_FLASH_SRRVR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_SRRVR_OFFSET) +#define STM32_FLASH_ACR (STM32_FLASHIF_BASE+STM32_FLASH_ACR_OFFSET) +#define STM32_FLASH_ACR2 (STM32_FLASHIF_BASE+STM32_FLASH_ACR2_OFFSET) +#define STM32_FLASH_KEYR (STM32_FLASHIF_BASE+STM32_FLASH_KEYR_OFFSET) +#define STM32_FLASH_OPTKEYR (STM32_FLASHIF_BASE+STM32_FLASH_OPTKEYR_OFFSET) +#define STM32_FLASH_SR (STM32_FLASHIF_BASE+STM32_FLASH_SR_OFFSET) +#define STM32_FLASH_CR (STM32_FLASHIF_BASE+STM32_FLASH_CR_OFFSET) +#define STM32_FLASH_ECCR (STM32_FLASHIF_BASE+STM32_FLASH_ECCR_OFFSET) +#define STM32_FLASH_OPTR (STM32_FLASHIF_BASE+STM32_FLASH_OPTR_OFFSET) +#define STM32_FLASH_PCROP1ASR (STM32_FLASHIF_BASE+STM32_FLASH_PCROP1ASR_OFFSET) +#define STM32_FLASH_PCROP1AER (STM32_FLASHIF_BASE+STM32_FLASH_PCROP1AER_OFFSET) +#define STM32_FLASH_WRP1AR (STM32_FLASHIF_BASE+STM32_FLASH_WRP1AR_OFFSET) +#define STM32_FLASH_WRP1BR (STM32_FLASHIF_BASE+STM32_FLASH_WRP1BR_OFFSET) +#define STM32_FLASH_PCROP1BSR (STM32_FLASHIF_BASE+STM32_FLASH_PCROP1BSR_OFFSET) +#define STM32_FLASH_PCROP1BER (STM32_FLASHIF_BASE+STM32_FLASH_PCROP1BER_OFFSET) +#define STM32_FLASH_IPCCBR (STM32_FLASHIF_BASE+STM32_FLASH_IPCCBR_OFFSET) +#define STM32_FLASH_C2ACR (STM32_FLASHIF_BASE+STM32_FLASH_C2ACR_OFFSET) +#define STM32_FLASH_C2SR (STM32_FLASHIF_BASE+STM32_FLASH_C2SR_OFFSET) +#define STM32_FLASH_C2CR (STM32_FLASHIF_BASE+STM32_FLASH_C2CR_OFFSET) +#define STM32_FLASH_SFR (STM32_FLASHIF_BASE+STM32_FLASH_SFR_OFFSET) +#define STM32_FLASH_SRRVR (STM32_FLASHIF_BASE+STM32_FLASH_SRRVR_OFFSET) /* Register Bitfield Definitions ********************************************/ diff --git a/arch/arm/src/stm32wl5/hardware/stm32wl5_gpio.h b/arch/arm/src/stm32wl5/hardware/stm32wl5_gpio.h index 9f76cb4efa0fc..780b84646d494 100644 --- a/arch/arm/src/stm32wl5/hardware/stm32wl5_gpio.h +++ b/arch/arm/src/stm32wl5/hardware/stm32wl5_gpio.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32WL5_HARDWARE_STM32WL5_GPIO_H -#define __ARCH_ARM_SRC_STM32WL5_HARDWARE_STM32WL5_GPIO_H +#ifndef __ARCH_ARM_SRC_STM32WL5_HARDWARE_STM32_GPIO_H +#define __ARCH_ARM_SRC_STM32WL5_HARDWARE_STM32_GPIO_H /**************************************************************************** * Included Files @@ -36,71 +36,71 @@ /* Register Offsets *********************************************************/ -#define STM32WL5_GPIO_MODER_OFFSET 0x0000 /* GPIO port mode register */ -#define STM32WL5_GPIO_OTYPER_OFFSET 0x0004 /* GPIO port output type register */ -#define STM32WL5_GPIO_OSPEED_OFFSET 0x0008 /* GPIO port output speed register */ -#define STM32WL5_GPIO_PUPDR_OFFSET 0x000c /* GPIO port pull-up/pull-down register */ -#define STM32WL5_GPIO_IDR_OFFSET 0x0010 /* GPIO port input data register */ -#define STM32WL5_GPIO_ODR_OFFSET 0x0014 /* GPIO port output data register */ -#define STM32WL5_GPIO_BSRR_OFFSET 0x0018 /* GPIO port bit set/reset register */ -#define STM32WL5_GPIO_LCKR_OFFSET 0x001c /* GPIO port configuration lock register */ -#define STM32WL5_GPIO_AFRL_OFFSET 0x0020 /* GPIO alternate function low register */ -#define STM32WL5_GPIO_AFRH_OFFSET 0x0024 /* GPIO alternate function high register */ -#define STM32WL5_GPIO_BRR_OFFSET 0x0028 /* GPIO port bit reset register */ +#define STM32_GPIO_MODER_OFFSET 0x0000 /* GPIO port mode register */ +#define STM32_GPIO_OTYPER_OFFSET 0x0004 /* GPIO port output type register */ +#define STM32_GPIO_OSPEED_OFFSET 0x0008 /* GPIO port output speed register */ +#define STM32_GPIO_PUPDR_OFFSET 0x000c /* GPIO port pull-up/pull-down register */ +#define STM32_GPIO_IDR_OFFSET 0x0010 /* GPIO port input data register */ +#define STM32_GPIO_ODR_OFFSET 0x0014 /* GPIO port output data register */ +#define STM32_GPIO_BSRR_OFFSET 0x0018 /* GPIO port bit set/reset register */ +#define STM32_GPIO_LCKR_OFFSET 0x001c /* GPIO port configuration lock register */ +#define STM32_GPIO_AFRL_OFFSET 0x0020 /* GPIO alternate function low register */ +#define STM32_GPIO_AFRH_OFFSET 0x0024 /* GPIO alternate function high register */ +#define STM32_GPIO_BRR_OFFSET 0x0028 /* GPIO port bit reset register */ /* Register Addresses *******************************************************/ -#define STM32WL5_GPIOA_MODER (STM32WL5_GPIOA_BASE+STM32WL5_GPIO_MODER_OFFSET) -#define STM32WL5_GPIOA_OTYPER (STM32WL5_GPIOA_BASE+STM32WL5_GPIO_OTYPER_OFFSET) -#define STM32WL5_GPIOA_OSPEED (STM32WL5_GPIOA_BASE+STM32WL5_GPIO_OSPEED_OFFSET) -#define STM32WL5_GPIOA_PUPDR (STM32WL5_GPIOA_BASE+STM32WL5_GPIO_PUPDR_OFFSET) -#define STM32WL5_GPIOA_IDR (STM32WL5_GPIOA_BASE+STM32WL5_GPIO_IDR_OFFSET) -#define STM32WL5_GPIOA_ODR (STM32WL5_GPIOA_BASE+STM32WL5_GPIO_ODR_OFFSET) -#define STM32WL5_GPIOA_BSRR (STM32WL5_GPIOA_BASE+STM32WL5_GPIO_BSRR_OFFSET) -#define STM32WL5_GPIOA_LCKR (STM32WL5_GPIOA_BASE+STM32WL5_GPIO_LCKR_OFFSET) -#define STM32WL5_GPIOA_AFRL (STM32WL5_GPIOA_BASE+STM32WL5_GPIO_AFRL_OFFSET) -#define STM32WL5_GPIOA_AFRH (STM32WL5_GPIOA_BASE+STM32WL5_GPIO_AFRH_OFFSET) -#define STM32WL5_GPIOA_BRR (STM32WL5_GPIOA_BASE+STM32WL5_GPIO_BRR_OFFSET) -#define STM32WL5_GPIOA_ASCR (STM32WL5_GPIOA_BASE+STM32WL5_GPIO_ASCR_OFFSET) - -#define STM32WL5_GPIOB_MODER (STM32WL5_GPIOB_BASE+STM32WL5_GPIO_MODER_OFFSET) -#define STM32WL5_GPIOB_OTYPER (STM32WL5_GPIOB_BASE+STM32WL5_GPIO_OTYPER_OFFSET) -#define STM32WL5_GPIOB_OSPEED (STM32WL5_GPIOB_BASE+STM32WL5_GPIO_OSPEED_OFFSET) -#define STM32WL5_GPIOB_PUPDR (STM32WL5_GPIOB_BASE+STM32WL5_GPIO_PUPDR_OFFSET) -#define STM32WL5_GPIOB_IDR (STM32WL5_GPIOB_BASE+STM32WL5_GPIO_IDR_OFFSET) -#define STM32WL5_GPIOB_ODR (STM32WL5_GPIOB_BASE+STM32WL5_GPIO_ODR_OFFSET) -#define STM32WL5_GPIOB_BSRR (STM32WL5_GPIOB_BASE+STM32WL5_GPIO_BSRR_OFFSET) -#define STM32WL5_GPIOB_LCKR (STM32WL5_GPIOB_BASE+STM32WL5_GPIO_LCKR_OFFSET) -#define STM32WL5_GPIOB_AFRL (STM32WL5_GPIOB_BASE+STM32WL5_GPIO_AFRL_OFFSET) -#define STM32WL5_GPIOB_AFRH (STM32WL5_GPIOB_BASE+STM32WL5_GPIO_AFRH_OFFSET) -#define STM32WL5_GPIOB_BRR (STM32WL5_GPIOB_BASE+STM32WL5_GPIO_BRR_OFFSET) -#define STM32WL5_GPIOB_ASCR (STM32WL5_GPIOB_BASE+STM32WL5_GPIO_ASCR_OFFSET) - -#define STM32WL5_GPIOC_MODER (STM32WL5_GPIOC_BASE+STM32WL5_GPIO_MODER_OFFSET) -#define STM32WL5_GPIOC_OTYPER (STM32WL5_GPIOC_BASE+STM32WL5_GPIO_OTYPER_OFFSET) -#define STM32WL5_GPIOC_OSPEED (STM32WL5_GPIOC_BASE+STM32WL5_GPIO_OSPEED_OFFSET) -#define STM32WL5_GPIOC_PUPDR (STM32WL5_GPIOC_BASE+STM32WL5_GPIO_PUPDR_OFFSET) -#define STM32WL5_GPIOC_IDR (STM32WL5_GPIOC_BASE+STM32WL5_GPIO_IDR_OFFSET) -#define STM32WL5_GPIOC_ODR (STM32WL5_GPIOC_BASE+STM32WL5_GPIO_ODR_OFFSET) -#define STM32WL5_GPIOC_BSRR (STM32WL5_GPIOC_BASE+STM32WL5_GPIO_BSRR_OFFSET) -#define STM32WL5_GPIOC_LCKR (STM32WL5_GPIOC_BASE+STM32WL5_GPIO_LCKR_OFFSET) -#define STM32WL5_GPIOC_AFRL (STM32WL5_GPIOC_BASE+STM32WL5_GPIO_AFRL_OFFSET) -#define STM32WL5_GPIOC_AFRH (STM32WL5_GPIOC_BASE+STM32WL5_GPIO_AFRH_OFFSET) -#define STM32WL5_GPIOC_BRR (STM32WL5_GPIOC_BASE+STM32WL5_GPIO_BRR_OFFSET) -#define STM32WL5_GPIOC_ASCR (STM32WL5_GPIOC_BASE+STM32WL5_GPIO_ASCR_OFFSET) - -#define STM32WL5_GPIOH_MODER (STM32WL5_GPIOH_BASE+STM32WL5_GPIO_MODER_OFFSET) -#define STM32WL5_GPIOH_OTYPER (STM32WL5_GPIOH_BASE+STM32WL5_GPIO_OTYPER_OFFSET) -#define STM32WL5_GPIOH_OSPEED (STM32WL5_GPIOH_BASE+STM32WL5_GPIO_OSPEED_OFFSET) -#define STM32WL5_GPIOH_PUPDR (STM32WL5_GPIOH_BASE+STM32WL5_GPIO_PUPDR_OFFSET) -#define STM32WL5_GPIOH_IDR (STM32WL5_GPIOH_BASE+STM32WL5_GPIO_IDR_OFFSET) -#define STM32WL5_GPIOH_ODR (STM32WL5_GPIOH_BASE+STM32WL5_GPIO_ODR_OFFSET) -#define STM32WL5_GPIOH_BSRR (STM32WL5_GPIOH_BASE+STM32WL5_GPIO_BSRR_OFFSET) -#define STM32WL5_GPIOH_LCKR (STM32WL5_GPIOH_BASE+STM32WL5_GPIO_LCKR_OFFSET) -#define STM32WL5_GPIOH_AFRL (STM32WL5_GPIOH_BASE+STM32WL5_GPIO_AFRL_OFFSET) -#define STM32WL5_GPIOH_AFRH (STM32WL5_GPIOH_BASE+STM32WL5_GPIO_AFRH_OFFSET) -#define STM32WL5_GPIOH_BRR (STM32WL5_GPIOH_BASE+STM32WL5_GPIO_BRR_OFFSET) -#define STM32WL5_GPIOH_ASCR (STM32WL5_GPIOH_BASE+STM32WL5_GPIO_ASCR_OFFSET) +#define STM32_GPIOA_MODER (STM32_GPIOA_BASE+STM32_GPIO_MODER_OFFSET) +#define STM32_GPIOA_OTYPER (STM32_GPIOA_BASE+STM32_GPIO_OTYPER_OFFSET) +#define STM32_GPIOA_OSPEED (STM32_GPIOA_BASE+STM32_GPIO_OSPEED_OFFSET) +#define STM32_GPIOA_PUPDR (STM32_GPIOA_BASE+STM32_GPIO_PUPDR_OFFSET) +#define STM32_GPIOA_IDR (STM32_GPIOA_BASE+STM32_GPIO_IDR_OFFSET) +#define STM32_GPIOA_ODR (STM32_GPIOA_BASE+STM32_GPIO_ODR_OFFSET) +#define STM32_GPIOA_BSRR (STM32_GPIOA_BASE+STM32_GPIO_BSRR_OFFSET) +#define STM32_GPIOA_LCKR (STM32_GPIOA_BASE+STM32_GPIO_LCKR_OFFSET) +#define STM32_GPIOA_AFRL (STM32_GPIOA_BASE+STM32_GPIO_AFRL_OFFSET) +#define STM32_GPIOA_AFRH (STM32_GPIOA_BASE+STM32_GPIO_AFRH_OFFSET) +#define STM32_GPIOA_BRR (STM32_GPIOA_BASE+STM32_GPIO_BRR_OFFSET) +#define STM32_GPIOA_ASCR (STM32_GPIOA_BASE+STM32_GPIO_ASCR_OFFSET) + +#define STM32_GPIOB_MODER (STM32_GPIOB_BASE+STM32_GPIO_MODER_OFFSET) +#define STM32_GPIOB_OTYPER (STM32_GPIOB_BASE+STM32_GPIO_OTYPER_OFFSET) +#define STM32_GPIOB_OSPEED (STM32_GPIOB_BASE+STM32_GPIO_OSPEED_OFFSET) +#define STM32_GPIOB_PUPDR (STM32_GPIOB_BASE+STM32_GPIO_PUPDR_OFFSET) +#define STM32_GPIOB_IDR (STM32_GPIOB_BASE+STM32_GPIO_IDR_OFFSET) +#define STM32_GPIOB_ODR (STM32_GPIOB_BASE+STM32_GPIO_ODR_OFFSET) +#define STM32_GPIOB_BSRR (STM32_GPIOB_BASE+STM32_GPIO_BSRR_OFFSET) +#define STM32_GPIOB_LCKR (STM32_GPIOB_BASE+STM32_GPIO_LCKR_OFFSET) +#define STM32_GPIOB_AFRL (STM32_GPIOB_BASE+STM32_GPIO_AFRL_OFFSET) +#define STM32_GPIOB_AFRH (STM32_GPIOB_BASE+STM32_GPIO_AFRH_OFFSET) +#define STM32_GPIOB_BRR (STM32_GPIOB_BASE+STM32_GPIO_BRR_OFFSET) +#define STM32_GPIOB_ASCR (STM32_GPIOB_BASE+STM32_GPIO_ASCR_OFFSET) + +#define STM32_GPIOC_MODER (STM32_GPIOC_BASE+STM32_GPIO_MODER_OFFSET) +#define STM32_GPIOC_OTYPER (STM32_GPIOC_BASE+STM32_GPIO_OTYPER_OFFSET) +#define STM32_GPIOC_OSPEED (STM32_GPIOC_BASE+STM32_GPIO_OSPEED_OFFSET) +#define STM32_GPIOC_PUPDR (STM32_GPIOC_BASE+STM32_GPIO_PUPDR_OFFSET) +#define STM32_GPIOC_IDR (STM32_GPIOC_BASE+STM32_GPIO_IDR_OFFSET) +#define STM32_GPIOC_ODR (STM32_GPIOC_BASE+STM32_GPIO_ODR_OFFSET) +#define STM32_GPIOC_BSRR (STM32_GPIOC_BASE+STM32_GPIO_BSRR_OFFSET) +#define STM32_GPIOC_LCKR (STM32_GPIOC_BASE+STM32_GPIO_LCKR_OFFSET) +#define STM32_GPIOC_AFRL (STM32_GPIOC_BASE+STM32_GPIO_AFRL_OFFSET) +#define STM32_GPIOC_AFRH (STM32_GPIOC_BASE+STM32_GPIO_AFRH_OFFSET) +#define STM32_GPIOC_BRR (STM32_GPIOC_BASE+STM32_GPIO_BRR_OFFSET) +#define STM32_GPIOC_ASCR (STM32_GPIOC_BASE+STM32_GPIO_ASCR_OFFSET) + +#define STM32_GPIOH_MODER (STM32_GPIOH_BASE+STM32_GPIO_MODER_OFFSET) +#define STM32_GPIOH_OTYPER (STM32_GPIOH_BASE+STM32_GPIO_OTYPER_OFFSET) +#define STM32_GPIOH_OSPEED (STM32_GPIOH_BASE+STM32_GPIO_OSPEED_OFFSET) +#define STM32_GPIOH_PUPDR (STM32_GPIOH_BASE+STM32_GPIO_PUPDR_OFFSET) +#define STM32_GPIOH_IDR (STM32_GPIOH_BASE+STM32_GPIO_IDR_OFFSET) +#define STM32_GPIOH_ODR (STM32_GPIOH_BASE+STM32_GPIO_ODR_OFFSET) +#define STM32_GPIOH_BSRR (STM32_GPIOH_BASE+STM32_GPIO_BSRR_OFFSET) +#define STM32_GPIOH_LCKR (STM32_GPIOH_BASE+STM32_GPIO_LCKR_OFFSET) +#define STM32_GPIOH_AFRL (STM32_GPIOH_BASE+STM32_GPIO_AFRL_OFFSET) +#define STM32_GPIOH_AFRH (STM32_GPIOH_BASE+STM32_GPIO_AFRH_OFFSET) +#define STM32_GPIOH_BRR (STM32_GPIOH_BASE+STM32_GPIO_BRR_OFFSET) +#define STM32_GPIOH_ASCR (STM32_GPIOH_BASE+STM32_GPIO_ASCR_OFFSET) /* Register Bitfield Definitions ********************************************/ @@ -298,4 +298,4 @@ #define GPIO_ASCR(n) (1 << (n)) -#endif /* __ARCH_ARM_SRC_STM32WL5_HARDWARE_STM32WL5_GPIO_H */ +#endif /* __ARCH_ARM_SRC_STM32WL5_HARDWARE_STM32_GPIO_H */ diff --git a/arch/arm/src/stm32wl5/hardware/stm32wl5_ipcc.h b/arch/arm/src/stm32wl5/hardware/stm32wl5_ipcc.h index 56632c5a9360a..d94f168008b0b 100644 --- a/arch/arm/src/stm32wl5/hardware/stm32wl5_ipcc.h +++ b/arch/arm/src/stm32wl5/hardware/stm32wl5_ipcc.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32WL5_HARDWARE_STM32WL5_IPCC_H -#define __ARCH_ARM_SRC_STM32WL5_HARDWARE_STM32WL5_IPCC_H +#ifndef __ARCH_ARM_SRC_STM32WL5_HARDWARE_STM32_IPCC_H +#define __ARCH_ARM_SRC_STM32WL5_HARDWARE_STM32_IPCC_H /**************************************************************************** * Included Files @@ -34,48 +34,48 @@ * Pre-processor Definitions ****************************************************************************/ -#define STM32WL5_IPCC_CPU1_OFFSET 0x00 -#define STM32WL5_IPCC_CPU2_OFFSET 0x10 +#define STM32_IPCC_CPU1_OFFSET 0x00 +#define STM32_IPCC_CPU2_OFFSET 0x10 /* Register Offsets *********************************************************/ -#define STM32WL5_IPCC_CR_OFFSET 0x00 /* IPCC control register */ -#define STM32WL5_IPCC_MR_OFFSET 0x04 /* IPCC mask register */ -#define STM32WL5_IPCC_SCR_OFFSET 0x08 /* IPCC status set clear register */ -#define STM32WL5_IPCC_CTOCSR_OFFSET 0x0c /* IPCC processor to processor status register */ +#define STM32_IPCC_CR_OFFSET 0x00 /* IPCC control register */ +#define STM32_IPCC_MR_OFFSET 0x04 /* IPCC mask register */ +#define STM32_IPCC_SCR_OFFSET 0x08 /* IPCC status set clear register */ +#define STM32_IPCC_CTOCSR_OFFSET 0x0c /* IPCC processor to processor status register */ /* Register Addresses *******************************************************/ -#define STM32WL5_IPCC_C1CR (STM32WL5_IPCC_BASE+STM32WL5_IPCC_CR_OFFSET+STM32WL5_IPCC_CPU1_OFFSET) -#define STM32WL5_IPCC_C1MR (STM32WL5_IPCC_BASE+STM32WL5_IPCC_MR_OFFSET+STM32WL5_IPCC_CPU1_OFFSET) -#define STM32WL5_IPCC_C1SCR (STM32WL5_IPCC_BASE+STM32WL5_IPCC_SCR_OFFSET+STM32WL5_IPCC_CPU1_OFFSET) -#define STM32WL5_IPCC_C1TOC2SR (STM32WL5_IPCC_BASE+STM32WL5_IPCC_CTOCSR_OFFSET+STM32WL5_IPCC_CPU1_OFFSET) -#define STM32WL5_IPCC_C2CR (STM32WL5_IPCC_BASE+STM32WL5_IPCC_CR_OFFSET+STM32WL5_IPCC_CPU2_OFFSET) -#define STM32WL5_IPCC_C2MR (STM32WL5_IPCC_BASE+STM32WL5_IPCC_MR_OFFSET+STM32WL5_IPCC_CPU2_OFFSET) -#define STM32WL5_IPCC_C2SCR (STM32WL5_IPCC_BASE+STM32WL5_IPCC_SCR_OFFSET+STM32WL5_IPCC_CPU2_OFFSET) -#define STM32WL5_IPCC_C2TOC1SR (STM32WL5_IPCC_BASE+STM32WL5_IPCC_CTOCSR_OFFSET+STM32WL5_IPCC_CPU2_OFFSET) +#define STM32_IPCC_C1CR (STM32_IPCC_BASE+STM32_IPCC_CR_OFFSET+STM32_IPCC_CPU1_OFFSET) +#define STM32_IPCC_C1MR (STM32_IPCC_BASE+STM32_IPCC_MR_OFFSET+STM32_IPCC_CPU1_OFFSET) +#define STM32_IPCC_C1SCR (STM32_IPCC_BASE+STM32_IPCC_SCR_OFFSET+STM32_IPCC_CPU1_OFFSET) +#define STM32_IPCC_C1TOC2SR (STM32_IPCC_BASE+STM32_IPCC_CTOCSR_OFFSET+STM32_IPCC_CPU1_OFFSET) +#define STM32_IPCC_C2CR (STM32_IPCC_BASE+STM32_IPCC_CR_OFFSET+STM32_IPCC_CPU2_OFFSET) +#define STM32_IPCC_C2MR (STM32_IPCC_BASE+STM32_IPCC_MR_OFFSET+STM32_IPCC_CPU2_OFFSET) +#define STM32_IPCC_C2SCR (STM32_IPCC_BASE+STM32_IPCC_SCR_OFFSET+STM32_IPCC_CPU2_OFFSET) +#define STM32_IPCC_C2TOC1SR (STM32_IPCC_BASE+STM32_IPCC_CTOCSR_OFFSET+STM32_IPCC_CPU2_OFFSET) /* Register Bitfield Definitions ********************************************/ -#define STM32WL5_IPCC_TX_SHIFT (16) /* TX shift for all registers */ +#define STM32_IPCC_TX_SHIFT (16) /* TX shift for all registers */ /* IPCC control register */ -#define STM32WL5_IPCC_CR_RXOIE (1 << 0) /* Bit 0: Receive channel occupied interrupt enable */ -#define STM32WL5_IPCC_CR_TXFIE (1 << 16) /* Bit 16: Transmit channel free interrupt enable */ +#define STM32_IPCC_CR_RXOIE (1 << 0) /* Bit 0: Receive channel occupied interrupt enable */ +#define STM32_IPCC_CR_TXFIE (1 << 16) /* Bit 16: Transmit channel free interrupt enable */ /* IPCC mask register */ -#define STM32WL5_IPCC_MR_CHNOM(n) (1 << (n)) /* Bit 0..5: Receive channel n occupied interrupt enable, Channels 0..5 */ -#define STM32WL5_IPCC_MR_CHNFM(n) (1 << (16 + (n))) /* Bit 16..21: Transmit channel n free interrupt enable, Channels 0..5 */ +#define STM32_IPCC_MR_CHNOM(n) (1 << (n)) /* Bit 0..5: Receive channel n occupied interrupt enable, Channels 0..5 */ +#define STM32_IPCC_MR_CHNFM(n) (1 << (16 + (n))) /* Bit 16..21: Transmit channel n free interrupt enable, Channels 0..5 */ /* IPCC status set clear register */ -#define STM32WL5_IPCC_SCR_CHNC(n) (1 << (n)) /* Bit 0..5: Receive channel n status bit clear, Channels 0..5 */ -#define STM32WL5_IPCC_SCR_CHNS(n) (1 << (16 + (n))) /* Bit 16..21: Transmit channel n status bit set, Channels 0..5 */ +#define STM32_IPCC_SCR_CHNC(n) (1 << (n)) /* Bit 0..5: Receive channel n status bit clear, Channels 0..5 */ +#define STM32_IPCC_SCR_CHNS(n) (1 << (16 + (n))) /* Bit 16..21: Transmit channel n status bit set, Channels 0..5 */ /* IPCC processor to processor status register */ -#define STM32WL5_IPCC_CTOCSR_CHNF(n) (1 << (n)) /* Bit 0..5: Channel n occupied, Channels 0..5 */ +#define STM32_IPCC_CTOCSR_CHNF(n) (1 << (n)) /* Bit 0..5: Channel n occupied, Channels 0..5 */ -#endif /* __ARCH_ARM_SRC_STM32WL5_HARDWARE_STM32WL5_IPCC_H */ +#endif /* __ARCH_ARM_SRC_STM32WL5_HARDWARE_STM32_IPCC_H */ diff --git a/arch/arm/src/stm32wl5/hardware/stm32wl5_memorymap.h b/arch/arm/src/stm32wl5/hardware/stm32wl5_memorymap.h index 89df326775bf3..4d336c7fe61d4 100644 --- a/arch/arm/src/stm32wl5/hardware/stm32wl5_memorymap.h +++ b/arch/arm/src/stm32wl5/hardware/stm32wl5_memorymap.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32WL5_STM32WL5_MEMORYMAP_H -#define __ARCH_ARM_SRC_STM32WL5_STM32WL5_MEMORYMAP_H +#ifndef __ARCH_ARM_SRC_STM32WL5_STM32_MEMORYMAP_H +#define __ARCH_ARM_SRC_STM32WL5_STM32_MEMORYMAP_H /**************************************************************************** * Pre-processor Definitions @@ -29,40 +29,40 @@ /* STM32WL5XXX Address Blocks ***********************************************/ -#define STM32WL5_CODE_BASE 0x00000000 /* 0x0000 0000-0x1fff ffff: 512Mb code block */ -#define STM32WL5_SRAM_BASE 0x20000000 /* 0x2000 0000-0x3fff ffff: 512Mb sram block (48k to 256k) */ -#define STM32WL5_PERIPH_BASE 0x40000000 /* 0x4000 0000-0x5fff ffff: 512Mb peripheral block */ - /* 0x6000 0000-0xdfff ffff: 2048Mb (not used) */ -#define STM32WL5_CORTEX_BASE 0xe0000000 /* 0xe000 0000-0xffff ffff: 512Mb Cortex-M4/M0 block */ +#define STM32_CODE_BASE 0x00000000 /* 0x0000 0000-0x1fff ffff: 512Mb code block */ +#define STM32_SRAM_BASE 0x20000000 /* 0x2000 0000-0x3fff ffff: 512Mb sram block (48k to 256k) */ +#define STM32_PERIPH_BASE 0x40000000 /* 0x4000 0000-0x5fff ffff: 512Mb peripheral block */ + /* 0x6000 0000-0xdfff ffff: 2048Mb (not used) */ +#define STM32_CORTEX_BASE 0xe0000000 /* 0xe000 0000-0xffff ffff: 512Mb Cortex-M4/M0 block */ -#define STM32WL5_REGION_MASK 0xf0000000 -#define STM32WL5_IS_SRAM(a) ((((uint32_t)(a)) & STM32WL5_REGION_MASK) == STM32WL5_SRAM_BASE) +#define STM32_REGION_MASK 0xf0000000 +#define STM32_IS_SRAM(a) ((((uint32_t)(a)) & STM32_REGION_MASK) == STM32_SRAM_BASE) /* Code Base Addresses ******************************************************/ -#define STM32WL5_BOOT_BASE 0x00000000 /* 0x0000 0000-0x0003 ffff: Aliased boot memory */ - /* 0x0004 0000-0x07ff ffff: Reserved */ -#define STM32WL5_FLASH_BASE 0x08000000 /* 0x0800 0000-0x0803 ffff: FLASH memory */ - /* 0x0804 0000-0x0fff ffff: Reserved */ -#define STM32WL5_FLASH_MASK 0xf8000000 /* Test if addr in FLASH */ - /* 0x1000 0000-0x1ffe 6fff: Reserved */ -#define STM32WL5_SYSMEM_BASE 0x1fff0000 /* 0x1fff 0000-0x1fff 6fff: System memory */ -#define STM32WL5_OTP_BASE 0x1fff7000 /* 0x1fff 7000-0x1fff 73ff: 1k otp memory */ -#define STM32WL5_ENGI_BASE 0x1fff7400 /* 0x1fff 7400-0x1fff 77ff: 1k engi flash */ -#define STM32WL5_OPTION_BASE 0x1fff7800 /* 0x1fff 7800-0x1fff 7fff: 2k flash user options */ - /* 0x1fff 8000-0x1fff ffff: reserved */ -#define STM32WL5_SRAM2_BASE 0x20008000 /* 0x2000 8000-0x2000 ffff: 32k SRAM2 */ +#define STM32_BOOT_BASE 0x00000000 /* 0x0000 0000-0x0003 ffff: Aliased boot memory */ + /* 0x0004 0000-0x07ff ffff: Reserved */ +#define STM32_FLASH_BASE 0x08000000 /* 0x0800 0000-0x0803 ffff: FLASH memory */ + /* 0x0804 0000-0x0fff ffff: Reserved */ +#define STM32_FLASH_MASK 0xf8000000 /* Test if addr in FLASH */ + /* 0x1000 0000-0x1ffe 6fff: Reserved */ +#define STM32_SYSMEM_BASE 0x1fff0000 /* 0x1fff 0000-0x1fff 6fff: System memory */ +#define STM32_OTP_BASE 0x1fff7000 /* 0x1fff 7000-0x1fff 73ff: 1k otp memory */ +#define STM32_ENGI_BASE 0x1fff7400 /* 0x1fff 7400-0x1fff 77ff: 1k engi flash */ +#define STM32_OPTION_BASE 0x1fff7800 /* 0x1fff 7800-0x1fff 7fff: 2k flash user options */ + /* 0x1fff 8000-0x1fff ffff: reserved */ +#define STM32_SRAM2_BASE 0x20008000 /* 0x2000 8000-0x2000 ffff: 32k SRAM2 */ /* System Memory Addresses **************************************************/ -#define STM32WL5_SYSMEM_PACKAGE 0x1fff7500 /* This bitfield indicates the package +#define STM32_SYSMEM_PACKAGE 0x1fff7500 /* This bitfield indicates the package * type. * 0: UFBGA73 * 2: WLCSP59 * 10: UFQFPN48 */ -#define STM32WL5_SYSMEM_UID 0x1fff7590 /* The 96-bit unique device identifier */ -#define STM32WL5_SYSMEM_FSIZE 0x1fff75E0 /* This bitfield indicates the size of +#define STM32_SYSMEM_UID 0x1fff7590 /* The 96-bit unique device identifier */ +#define STM32_SYSMEM_FSIZE 0x1fff75E0 /* This bitfield indicates the size of * the device Flash memory expressed in * Kbytes. Example: 0x0400 corresponds * to 1024 Kbytes. @@ -70,92 +70,92 @@ /* SRAM Base Addresses ******************************************************/ -#define STM32WL5_SRAMBB_BASE 0x22000000 /* 0x22000000- : SRAM bit-band region */ +#define STM32_SRAMBB_BASE 0x22000000 /* 0x22000000- : SRAM bit-band region */ /* Peripheral Base Addresses ************************************************/ -#define STM32WL5_APB1_BASE 0x40000000 /* 0x4000 0000-0x4000 b3ff: APB1 */ - /* 0x4000 B400-0x4000 ffff: Reserved */ -#define STM32WL5_APB2_BASE 0x40010000 /* 0x4001 0000-0x4001 4bff: APB2 */ - /* 0x4001 4c00-0x4001 ffff: Reserved */ -#define STM32WL5_AHB1_BASE 0x40020000 /* 0x4002 0000-0x425f ffff: APB1 */ - /* 0x4260 0000-0x47ff ffff: Reserved */ -#define STM32WL5_AHB2_BASE 0x48000000 /* 0x4800 0000-0x4800 1fff: AHB2 */ - /* 0x4800 2000-0x57ff ffff: Reserved */ -#define STM32WL5_AHB3_BASE 0x58000000 /* 0x5800 0000-0x5800 4bff: AHB3 */ - /* 0x5800 40c0-0x5800 ffff: Reserved */ +#define STM32_APB1_BASE 0x40000000 /* 0x4000 0000-0x4000 b3ff: APB1 */ + /* 0x4000 B400-0x4000 ffff: Reserved */ +#define STM32_APB2_BASE 0x40010000 /* 0x4001 0000-0x4001 4bff: APB2 */ + /* 0x4001 4c00-0x4001 ffff: Reserved */ +#define STM32_AHB1_BASE 0x40020000 /* 0x4002 0000-0x425f ffff: APB1 */ + /* 0x4260 0000-0x47ff ffff: Reserved */ +#define STM32_AHB2_BASE 0x48000000 /* 0x4800 0000-0x4800 1fff: AHB2 */ + /* 0x4800 2000-0x57ff ffff: Reserved */ +#define STM32_AHB3_BASE 0x58000000 /* 0x5800 0000-0x5800 4bff: AHB3 */ + /* 0x5800 40c0-0x5800 ffff: Reserved */ /* Radio Base Addresses *****************************************************/ -#define STM32WL5_APB3_BASE 0x58010000 /* 0x5801 0000-0x5801 03ff: APB3 */ - /* 0x5801 0400-0x5801 ffff: Reserved */ +#define STM32_APB3_BASE 0x58010000 /* 0x5801 0000-0x5801 03ff: APB3 */ + /* 0x5801 0400-0x5801 ffff: Reserved */ /* in datasheet order */ /* APB1 Base Addresses ******************************************************/ -#define STM32WL5_TAMP_BASE 0x4000B000 -#define STM32WL5_LPTIM3_BASE 0x40009800 -#define STM32WL5_LPTIM2_BASE 0x40009400 -#define STM32WL5_LPUART1_BASE 0x40008000 -#define STM32WL5_LPTIM1_BASE 0x40007C00 -#define STM32WL5_DAC_BASE 0x40007400 -#define STM32WL5_I2C3_BASE 0x40005C00 -#define STM32WL5_I2C2_BASE 0x40005800 -#define STM32WL5_I2C1_BASE 0x40005400 -#define STM32WL5_USART2_BASE 0x40004400 -#define STM32WL5_SPI2S2_BASE 0x40003800 -#define STM32WL5_IWDG_BASE 0x40003000 -#define STM32WL5_WWDG_BASE 0x40002C00 -#define STM32WL5_RTC_BASE 0x40002800 -#define STM32WL5_TIM2_BASE 0x40000000 +#define STM32_TAMP_BASE 0x4000B000 +#define STM32_LPTIM3_BASE 0x40009800 +#define STM32_LPTIM2_BASE 0x40009400 +#define STM32_LPUART1_BASE 0x40008000 +#define STM32_LPTIM1_BASE 0x40007C00 +#define STM32_DAC_BASE 0x40007400 +#define STM32_I2C3_BASE 0x40005C00 +#define STM32_I2C2_BASE 0x40005800 +#define STM32_I2C1_BASE 0x40005400 +#define STM32_USART2_BASE 0x40004400 +#define STM32_SPI2S2_BASE 0x40003800 +#define STM32_IWDG_BASE 0x40003000 +#define STM32_WWDG_BASE 0x40002C00 +#define STM32_RTC_BASE 0x40002800 +#define STM32_TIM2_BASE 0x40000000 /* APB2 Base Addresses ******************************************************/ -#define STM32WL5_TIM17_BASE 0x40014800 -#define STM32WL5_TIM16_BASE 0x40014400 -#define STM32WL5_USART1_BASE 0x40013800 -#define STM32WL5_SPI1_BASE 0x40013000 -#define STM32WL5_TIM1_BASE 0x40012C00 -#define STM32WL5_ADC_BASE 0x40012400 -#define STM32WL5_COMP_BASE 0x40010200 -#define STM32WL5_SYSCFG2_BASE 0x40010100 -#define STM32WL5_VREFBUF_BASE 0x40010030 -#define STM32WL5_SYSCFG_BASE 0x40010000 +#define STM32_TIM17_BASE 0x40014800 +#define STM32_TIM16_BASE 0x40014400 +#define STM32_USART1_BASE 0x40013800 +#define STM32_SPI1_BASE 0x40013000 +#define STM32_TIM1_BASE 0x40012C00 +#define STM32_ADC_BASE 0x40012400 +#define STM32_COMP_BASE 0x40010200 +#define STM32_SYSCFG2_BASE 0x40010100 +#define STM32_VREFBUF_BASE 0x40010030 +#define STM32_SYSCFG_BASE 0x40010000 /* AHB1 Base Addresses ******************************************************/ -#define STM32WL5_CRC_BASE 0x40023000 -#define STM32WL5_DMAMUX1_BASE 0x40200800 -#define STM32WL5_DMA2_BASE 0x40200400 -#define STM32WL5_DMA1_BASE 0x40020000 +#define STM32_CRC_BASE 0x40023000 +#define STM32_DMAMUX1_BASE 0x40200800 +#define STM32_DMA2_BASE 0x40200400 +#define STM32_DMA1_BASE 0x40020000 /* AHB2 Base Addresses ******************************************************/ -#define STM32WL5_GPIOH_BASE 0x48001C00 -#define STM32WL5_GPIOC_BASE 0x48000800 -#define STM32WL5_GPIOB_BASE 0x48000400 -#define STM32WL5_GPIOA_BASE 0x48000000 +#define STM32_GPIOH_BASE 0x48001C00 +#define STM32_GPIOC_BASE 0x48000800 +#define STM32_GPIOB_BASE 0x48000400 +#define STM32_GPIOA_BASE 0x48000000 /* AHB3 Base Addresses ******************************************************/ -#define STM32WL5_GTZC_TZIC_BASE 0x58004800 -#define STM32WL5_GTZC_TZSC_BASE 0x58004400 -#define STM32WL5_FLASHIF_BASE 0x58004000 -#define STM32WL5_PKA2_BASE 0x58003400 -#define STM32WL5_PKARAM_BASE 0x58002400 -#define STM32WL5_PKA_BASE 0x58002000 -#define STM32WL5_AES_BASE 0x58001800 -#define STM32WL5_HSEM_BASE 0x58001400 -#define STM32WL5_RNG_BASE 0x58001000 -#define STM32WL5_IPCC_BASE 0x58000C00 -#define STM32WL5_EXTI_BASE 0x58000800 -#define STM32WL5_PWR_BASE 0x58000400 -#define STM32WL5_RCC_BASE 0x58000000 +#define STM32_GTZC_TZIC_BASE 0x58004800 +#define STM32_GTZC_TZSC_BASE 0x58004400 +#define STM32_FLASHIF_BASE 0x58004000 +#define STM32_PKA2_BASE 0x58003400 +#define STM32_PKARAM_BASE 0x58002400 +#define STM32_PKA_BASE 0x58002000 +#define STM32_AES_BASE 0x58001800 +#define STM32_HSEM_BASE 0x58001400 +#define STM32_RNG_BASE 0x58001000 +#define STM32_IPCC_BASE 0x58000C00 +#define STM32_EXTI_BASE 0x58000800 +#define STM32_PWR_BASE 0x58000400 +#define STM32_RCC_BASE 0x58000000 /* APB3 Base Addresses ******************************************************/ -#define STM32WL5_SUBGHZSPI_BASE 0x58010000 +#define STM32_SUBGHZSPI_BASE 0x58010000 /* Cortex-M4 Base Addresses *************************************************/ @@ -163,7 +163,7 @@ * this address range */ -#define STM32WL5_SCS_BASE 0xe000e000 -#define STM32WL5_DEBUGMCU_BASE 0xe0042000 +#define STM32_SCS_BASE 0xe000e000 +#define STM32_DEBUGMCU_BASE 0xe0042000 -#endif /* __ARCH_ARM_SRC_STM32WL5_STM32WL5_MEMORYMAP_H */ +#endif /* __ARCH_ARM_SRC_STM32WL5_STM32_MEMORYMAP_H */ diff --git a/arch/arm/src/stm32wl5/hardware/stm32wl5_pinmap.h b/arch/arm/src/stm32wl5/hardware/stm32wl5_pinmap.h index b38799ada8bcc..421bbc2625d11 100644 --- a/arch/arm/src/stm32wl5/hardware/stm32wl5_pinmap.h +++ b/arch/arm/src/stm32wl5/hardware/stm32wl5_pinmap.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32WL5_HARDWARE_STM32WL5_PINMAP_H -#define __ARCH_ARM_SRC_STM32WL5_HARDWARE_STM32WL5_PINMAP_H +#ifndef __ARCH_ARM_SRC_STM32WL5_HARDWARE_STM32_PINMAP_H +#define __ARCH_ARM_SRC_STM32WL5_HARDWARE_STM32_PINMAP_H /**************************************************************************** * Included Files @@ -331,4 +331,4 @@ #define GPIO_LSCO_1 (GPIO_ALT|GPIO_AF0 |GPIO_PORTA|GPIO_PIN2) #define GPIO_MCO_1 (GPIO_ALT|GPIO_AF0 |GPIO_PORTA|GPIO_PIN8) -#endif /* __ARCH_ARM_SRC_STM32WL5_HARDWARE_STM32WL5_PINMAP_H */ +#endif /* __ARCH_ARM_SRC_STM32WL5_HARDWARE_STM32_PINMAP_H */ diff --git a/arch/arm/src/stm32wl5/hardware/stm32wl5_pwr.h b/arch/arm/src/stm32wl5/hardware/stm32wl5_pwr.h index 978e931a4d588..3523cfbb80438 100644 --- a/arch/arm/src/stm32wl5/hardware/stm32wl5_pwr.h +++ b/arch/arm/src/stm32wl5/hardware/stm32wl5_pwr.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32WL5_HARDWARE_STM32WL5_PWR_H -#define __ARCH_ARM_SRC_STM32WL5_HARDWARE_STM32WL5_PWR_H +#ifndef __ARCH_ARM_SRC_STM32WL5_HARDWARE_STM32_PWR_H +#define __ARCH_ARM_SRC_STM32WL5_HARDWARE_STM32_PWR_H /**************************************************************************** * Included Files @@ -36,53 +36,53 @@ /* Register Offsets *********************************************************/ -#define STM32WL5_PWR_CR1_OFFSET 0x0000 /* Power control register 1 */ -#define STM32WL5_PWR_CR2_OFFSET 0x0004 /* Power control register 2 */ -#define STM32WL5_PWR_CR3_OFFSET 0x0008 /* Power control register 3 */ -#define STM32WL5_PWR_CR4_OFFSET 0x000C /* Power control register 4 */ -#define STM32WL5_PWR_SR1_OFFSET 0x0010 /* Power status register 1 */ -#define STM32WL5_PWR_SR2_OFFSET 0x0014 /* Power status register 2 */ -#define STM32WL5_PWR_SCR_OFFSET 0x0018 /* Power status clear register */ -#define STM32WL5_PWR_CR5_OFFSET 0x001C /* Power control register 5 */ -#define STM32WL5_PWR_PUCRA_OFFSET 0x0020 /* Power Port A pull-up control register */ -#define STM32WL5_PWR_PDCRA_OFFSET 0x0024 /* Power Port A pull-down control register */ -#define STM32WL5_PWR_PUCRB_OFFSET 0x0028 /* Power Port B pull-up control register */ -#define STM32WL5_PWR_PDCRB_OFFSET 0x002C /* Power Port B pull-down control register */ -#define STM32WL5_PWR_PUCRC_OFFSET 0x0030 /* Power Port C pull-up control register */ -#define STM32WL5_PWR_PDCRC_OFFSET 0x0034 /* Power Port C pull-down control register */ -#define STM32WL5_PWR_PUCRH_OFFSET 0x0058 /* Power Port H pull-up control register */ -#define STM32WL5_PWR_PDCRH_OFFSET 0x005C /* Power Port H pull-down control register */ -#define STM32WL5_PWR_C2CR1_OFFSET 0x0080 /* Power control register 1 for cpu2 */ -#define STM32WL5_PWR_C2CR3_OFFSET 0x0084 /* Power control register 3 for cpu2 */ -#define STM32WL5_PWR_EXTSCR_OFFSET 0x0088 /* Power extended status */ -#define STM32WL5_PWR_SECCFGR_OFFSET 0x0088 /* Power security configuration */ -#define STM32WL5_PWR_SUBGHZSPICR_OFFSET 0x0088 /* Power sub-ghz spi radio control */ -#define STM32WL5_PWR_RSSCMDR_OFFSET 0x0088 /* Power RSS command */ +#define STM32_PWR_CR1_OFFSET 0x0000 /* Power control register 1 */ +#define STM32_PWR_CR2_OFFSET 0x0004 /* Power control register 2 */ +#define STM32_PWR_CR3_OFFSET 0x0008 /* Power control register 3 */ +#define STM32_PWR_CR4_OFFSET 0x000C /* Power control register 4 */ +#define STM32_PWR_SR1_OFFSET 0x0010 /* Power status register 1 */ +#define STM32_PWR_SR2_OFFSET 0x0014 /* Power status register 2 */ +#define STM32_PWR_SCR_OFFSET 0x0018 /* Power status clear register */ +#define STM32_PWR_CR5_OFFSET 0x001C /* Power control register 5 */ +#define STM32_PWR_PUCRA_OFFSET 0x0020 /* Power Port A pull-up control register */ +#define STM32_PWR_PDCRA_OFFSET 0x0024 /* Power Port A pull-down control register */ +#define STM32_PWR_PUCRB_OFFSET 0x0028 /* Power Port B pull-up control register */ +#define STM32_PWR_PDCRB_OFFSET 0x002C /* Power Port B pull-down control register */ +#define STM32_PWR_PUCRC_OFFSET 0x0030 /* Power Port C pull-up control register */ +#define STM32_PWR_PDCRC_OFFSET 0x0034 /* Power Port C pull-down control register */ +#define STM32_PWR_PUCRH_OFFSET 0x0058 /* Power Port H pull-up control register */ +#define STM32_PWR_PDCRH_OFFSET 0x005C /* Power Port H pull-down control register */ +#define STM32_PWR_C2CR1_OFFSET 0x0080 /* Power control register 1 for cpu2 */ +#define STM32_PWR_C2CR3_OFFSET 0x0084 /* Power control register 3 for cpu2 */ +#define STM32_PWR_EXTSCR_OFFSET 0x0088 /* Power extended status */ +#define STM32_PWR_SECCFGR_OFFSET 0x0088 /* Power security configuration */ +#define STM32_PWR_SUBGHZSPICR_OFFSET 0x0088 /* Power sub-ghz spi radio control */ +#define STM32_PWR_RSSCMDR_OFFSET 0x0088 /* Power RSS command */ /* Register Addresses *******************************************************/ -#define STM32WL5_PWR_CR1 (STM32WL5_PWR_BASE+STM32WL5_PWR_CR1_OFFSET) -#define STM32WL5_PWR_CR2 (STM32WL5_PWR_BASE+STM32WL5_PWR_CR2_OFFSET) -#define STM32WL5_PWR_CR3 (STM32WL5_PWR_BASE+STM32WL5_PWR_CR3_OFFSET) -#define STM32WL5_PWR_CR4 (STM32WL5_PWR_BASE+STM32WL5_PWR_CR4_OFFSET) -#define STM32WL5_PWR_SR1 (STM32WL5_PWR_BASE+STM32WL5_PWR_SR1_OFFSET) -#define STM32WL5_PWR_SR2 (STM32WL5_PWR_BASE+STM32WL5_PWR_SR2_OFFSET) -#define STM32WL5_PWR_SCR (STM32WL5_PWR_BASE+STM32WL5_PWR_SCR_OFFSET) -#define STM32WL5_PWR_CR5 (STM32WL5_PWR_BASE+STM32WL5_PWR_CR5_OFFSET) -#define STM32WL5_PWR_PUCRA (STM32WL5_PWR_BASE+STM32WL5_PWR_PUCRA_OFFSET) -#define STM32WL5_PWR_PDCRA (STM32WL5_PWR_BASE+STM32WL5_PWR_PDCRA_OFFSET) -#define STM32WL5_PWR_PUCRB (STM32WL5_PWR_BASE+STM32WL5_PWR_PUCRB_OFFSET) -#define STM32WL5_PWR_PDCRB (STM32WL5_PWR_BASE+STM32WL5_PWR_PDCRB_OFFSET) -#define STM32WL5_PWR_PUCRC (STM32WL5_PWR_BASE+STM32WL5_PWR_PUCRC_OFFSET) -#define STM32WL5_PWR_PDCRC (STM32WL5_PWR_BASE+STM32WL5_PWR_PDCRC_OFFSET) -#define STM32WL5_PWR_PUCRH (STM32WL5_PWR_BASE+STM32WL5_PWR_PUCRH_OFFSET) -#define STM32WL5_PWR_PDCRH (STM32WL5_PWR_BASE+STM32WL5_PWR_PDCRH_OFFSET) -#define STM32WL5_PWR_C2CR1 (STM32WL5_PWR_BASE+STM32WL5_PWR_C2CR1_OFFSET) -#define STM32WL5_PWR_C2CR3 (STM32WL5_PWR_BASE+STM32WL5_PWR_C2CR3_OFFSET) -#define STM32WL5_PWR_EXTSCR (STM32WL5_PWR_BASE+STM32WL5_PWR_EXTSCR_OFFSET) -#define STM32WL5_PWR_SECCFGR (STM32WL5_PWR_BASE+STM32WL5_PWR_SECCFGR_OFFSET) -#define STM32WL5_PWR_SUBGHZSPICR (STM32WL5_PWR_BASE+STM32WL5_PWR_SUBGHZSPICR_OFFSET) -#define STM32WL5_PWR_RSSCMDR (STM32WL5_PWR_BASE+STM32WL5_PWR_RSSCMDR_OFFSET) +#define STM32_PWR_CR1 (STM32_PWR_BASE+STM32_PWR_CR1_OFFSET) +#define STM32_PWR_CR2 (STM32_PWR_BASE+STM32_PWR_CR2_OFFSET) +#define STM32_PWR_CR3 (STM32_PWR_BASE+STM32_PWR_CR3_OFFSET) +#define STM32_PWR_CR4 (STM32_PWR_BASE+STM32_PWR_CR4_OFFSET) +#define STM32_PWR_SR1 (STM32_PWR_BASE+STM32_PWR_SR1_OFFSET) +#define STM32_PWR_SR2 (STM32_PWR_BASE+STM32_PWR_SR2_OFFSET) +#define STM32_PWR_SCR (STM32_PWR_BASE+STM32_PWR_SCR_OFFSET) +#define STM32_PWR_CR5 (STM32_PWR_BASE+STM32_PWR_CR5_OFFSET) +#define STM32_PWR_PUCRA (STM32_PWR_BASE+STM32_PWR_PUCRA_OFFSET) +#define STM32_PWR_PDCRA (STM32_PWR_BASE+STM32_PWR_PDCRA_OFFSET) +#define STM32_PWR_PUCRB (STM32_PWR_BASE+STM32_PWR_PUCRB_OFFSET) +#define STM32_PWR_PDCRB (STM32_PWR_BASE+STM32_PWR_PDCRB_OFFSET) +#define STM32_PWR_PUCRC (STM32_PWR_BASE+STM32_PWR_PUCRC_OFFSET) +#define STM32_PWR_PDCRC (STM32_PWR_BASE+STM32_PWR_PDCRC_OFFSET) +#define STM32_PWR_PUCRH (STM32_PWR_BASE+STM32_PWR_PUCRH_OFFSET) +#define STM32_PWR_PDCRH (STM32_PWR_BASE+STM32_PWR_PDCRH_OFFSET) +#define STM32_PWR_C2CR1 (STM32_PWR_BASE+STM32_PWR_C2CR1_OFFSET) +#define STM32_PWR_C2CR3 (STM32_PWR_BASE+STM32_PWR_C2CR3_OFFSET) +#define STM32_PWR_EXTSCR (STM32_PWR_BASE+STM32_PWR_EXTSCR_OFFSET) +#define STM32_PWR_SECCFGR (STM32_PWR_BASE+STM32_PWR_SECCFGR_OFFSET) +#define STM32_PWR_SUBGHZSPICR (STM32_PWR_BASE+STM32_PWR_SUBGHZSPICR_OFFSET) +#define STM32_PWR_RSSCMDR (STM32_PWR_BASE+STM32_PWR_RSSCMDR_OFFSET) /* Register Bitfield Definitions ********************************************/ @@ -197,4 +197,4 @@ * with a few exceptions */ -#endif /* __ARCH_ARM_SRC_STM32WL5_HARDWARE_STM32WL5_PWR_H */ +#endif /* __ARCH_ARM_SRC_STM32WL5_HARDWARE_STM32_PWR_H */ diff --git a/arch/arm/src/stm32wl5/hardware/stm32wl5_rcc.h b/arch/arm/src/stm32wl5/hardware/stm32wl5_rcc.h index 3f7309342f300..d0bfdf1b601ab 100644 --- a/arch/arm/src/stm32wl5/hardware/stm32wl5_rcc.h +++ b/arch/arm/src/stm32wl5/hardware/stm32wl5_rcc.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32WL5_HARDWARE_STM32WL5_RCC_H -#define __ARCH_ARM_SRC_STM32WL5_HARDWARE_STM32WL5_RCC_H +#ifndef __ARCH_ARM_SRC_STM32WL5_HARDWARE_STM32_RCC_H +#define __ARCH_ARM_SRC_STM32WL5_HARDWARE_STM32_RCC_H /**************************************************************************** * Included Files @@ -35,95 +35,95 @@ /* Register Offsets *********************************************************/ -#define STM32WL5_RCC_CR_OFFSET 0x0000 /* Clock control register */ -#define STM32WL5_RCC_ICSCR_OFFSET 0x0004 /* Internal clock sources calibration register */ -#define STM32WL5_RCC_CFGR_OFFSET 0x0008 /* Clock configuration register */ -#define STM32WL5_RCC_PLLCFG_OFFSET 0x000c /* PLL configuration register */ -#define STM32WL5_RCC_CIER_OFFSET 0x0018 /* Clock interrupt enable register */ -#define STM32WL5_RCC_CIFR_OFFSET 0x001c /* Clock interrupt flag register */ -#define STM32WL5_RCC_CICR_OFFSET 0x0020 /* Clock interrupt clear register */ -#define STM32WL5_RCC_AHB1RSTR_OFFSET 0x0028 /* AHB1 peripheral reset register */ -#define STM32WL5_RCC_AHB2RSTR_OFFSET 0x002c /* AHB2 peripheral reset register */ -#define STM32WL5_RCC_AHB3RSTR_OFFSET 0x0030 /* AHB3 peripheral reset register */ -#define STM32WL5_RCC_APB1RSTR1_OFFSET 0x0038 /* APB1 Peripheral reset register 1 */ -#define STM32WL5_RCC_APB1RSTR2_OFFSET 0x003c /* APB1 Peripheral reset register 2 */ -#define STM32WL5_RCC_APB2RSTR_OFFSET 0x0040 /* APB2 Peripheral reset register */ -#define STM32WL5_RCC_AHB1ENR_OFFSET 0x0048 /* AHB1 Peripheral Clock enable register */ -#define STM32WL5_RCC_AHB2ENR_OFFSET 0x004c /* AHB2 Peripheral Clock enable register */ -#define STM32WL5_RCC_AHB3ENR_OFFSET 0x0050 /* AHB3 Peripheral Clock enable register */ -#define STM32WL5_RCC_APB1ENR1_OFFSET 0x0058 /* APB1 Peripheral Clock enable register 1 */ -#define STM32WL5_RCC_APB1ENR2_OFFSET 0x005c /* APB1 Peripheral Clock enable register 2 */ -#define STM32WL5_RCC_APB2ENR_OFFSET 0x0060 /* APB2 Peripheral Clock enable register */ -#define STM32WL5_RCC_AHB1SMENR_OFFSET 0x0068 /* RCC AHB1 low power mode peripheral clock enable register */ -#define STM32WL5_RCC_AHB2SMENR_OFFSET 0x006c /* RCC AHB2 low power mode peripheral clock enable register */ -#define STM32WL5_RCC_AHB3SMENR_OFFSET 0x0070 /* RCC AHB3 low power mode peripheral clock enable register */ -#define STM32WL5_RCC_APB1SMENR1_OFFSET 0x0078 /* RCC APB1 low power mode peripheral clock enable register 1 */ -#define STM32WL5_RCC_APB1SMENR2_OFFSET 0x007c /* RCC APB1 low power mode peripheral clock enable register 2 */ -#define STM32WL5_RCC_APB2SMENR_OFFSET 0x0080 /* RCC APB2 low power mode peripheral clock enable register */ -#define STM32WL5_RCC_CCIPR_OFFSET 0x0088 /* Peripherals independent clock configuration register 1 */ -#define STM32WL5_RCC_BDCR_OFFSET 0x0090 /* Backup domain control register */ -#define STM32WL5_RCC_CSR_OFFSET 0x0094 /* Control/status register */ -#define STM32WL5_RCC_EXTCFGR_OFFSET 0x0108 -#define STM32WL5_RCC_C2AHB1ENR_OFFSET 0x0148 /* CPU2 AHB1 Peripheral Clock enable register */ -#define STM32WL5_RCC_C2AHB2ENR_OFFSET 0x014c /* CPU2 AHB2 Peripheral Clock enable register */ -#define STM32WL5_RCC_C2AHB3ENR_OFFSET 0x0150 /* CPU2 AHB3 Peripheral Clock enable register */ -#define STM32WL5_RCC_C2APB1ENR1_OFFSET 0x0158 /* CPU2 APB1 Peripheral Clock enable register 1 */ -#define STM32WL5_RCC_C2APB1ENR2_OFFSET 0x015c /* CPU2 APB1 Peripheral Clock enable register 2 */ -#define STM32WL5_RCC_C2APB2ENR_OFFSET 0x0160 /* CPU2 APB2 Peripheral Clock enable register */ -#define STM32WL5_RCC_C2APB3ENR_OFFSET 0x0164 /* CPU2 APB3 Peripheral Clock enable register */ -#define STM32WL5_RCC_C2AHB1SMENR_OFFSET 0x0168 /* CPU2 RCC AHB1 low power mode peripheral clock enable register */ -#define STM32WL5_RCC_C2AHB2SMENR_OFFSET 0x016c /* CPU2 RCC AHB2 low power mode peripheral clock enable register */ -#define STM32WL5_RCC_C2AHB3SMENR_OFFSET 0x0170 /* CPU2 RCC AHB3 low power mode peripheral clock enable register */ -#define STM32WL5_RCC_C2APB1SMENR1_OFFSET 0x0178 /* CPU2 RCC APB1 low power mode peripheral clock enable register 1 */ -#define STM32WL5_RCC_C2APB1SMENR2_OFFSET 0x017c /* CPU2 RCC APB1 low power mode peripheral clock enable register 2 */ -#define STM32WL5_RCC_C2APB2SMENR_OFFSET 0x0180 /* CPU2 RCC APB2 low power mode peripheral clock enable register */ -#define STM32WL5_RCC_C2APB3SMENR_OFFSET 0x0184 /* CPU2 RCC APB3 low power mode peripheral clock enable register */ +#define STM32_RCC_CR_OFFSET 0x0000 /* Clock control register */ +#define STM32_RCC_ICSCR_OFFSET 0x0004 /* Internal clock sources calibration register */ +#define STM32_RCC_CFGR_OFFSET 0x0008 /* Clock configuration register */ +#define STM32_RCC_PLLCFG_OFFSET 0x000c /* PLL configuration register */ +#define STM32_RCC_CIER_OFFSET 0x0018 /* Clock interrupt enable register */ +#define STM32_RCC_CIFR_OFFSET 0x001c /* Clock interrupt flag register */ +#define STM32_RCC_CICR_OFFSET 0x0020 /* Clock interrupt clear register */ +#define STM32_RCC_AHB1RSTR_OFFSET 0x0028 /* AHB1 peripheral reset register */ +#define STM32_RCC_AHB2RSTR_OFFSET 0x002c /* AHB2 peripheral reset register */ +#define STM32_RCC_AHB3RSTR_OFFSET 0x0030 /* AHB3 peripheral reset register */ +#define STM32_RCC_APB1RSTR1_OFFSET 0x0038 /* APB1 Peripheral reset register 1 */ +#define STM32_RCC_APB1RSTR2_OFFSET 0x003c /* APB1 Peripheral reset register 2 */ +#define STM32_RCC_APB2RSTR_OFFSET 0x0040 /* APB2 Peripheral reset register */ +#define STM32_RCC_AHB1ENR_OFFSET 0x0048 /* AHB1 Peripheral Clock enable register */ +#define STM32_RCC_AHB2ENR_OFFSET 0x004c /* AHB2 Peripheral Clock enable register */ +#define STM32_RCC_AHB3ENR_OFFSET 0x0050 /* AHB3 Peripheral Clock enable register */ +#define STM32_RCC_APB1ENR1_OFFSET 0x0058 /* APB1 Peripheral Clock enable register 1 */ +#define STM32_RCC_APB1ENR2_OFFSET 0x005c /* APB1 Peripheral Clock enable register 2 */ +#define STM32_RCC_APB2ENR_OFFSET 0x0060 /* APB2 Peripheral Clock enable register */ +#define STM32_RCC_AHB1SMENR_OFFSET 0x0068 /* RCC AHB1 low power mode peripheral clock enable register */ +#define STM32_RCC_AHB2SMENR_OFFSET 0x006c /* RCC AHB2 low power mode peripheral clock enable register */ +#define STM32_RCC_AHB3SMENR_OFFSET 0x0070 /* RCC AHB3 low power mode peripheral clock enable register */ +#define STM32_RCC_APB1SMENR1_OFFSET 0x0078 /* RCC APB1 low power mode peripheral clock enable register 1 */ +#define STM32_RCC_APB1SMENR2_OFFSET 0x007c /* RCC APB1 low power mode peripheral clock enable register 2 */ +#define STM32_RCC_APB2SMENR_OFFSET 0x0080 /* RCC APB2 low power mode peripheral clock enable register */ +#define STM32_RCC_CCIPR_OFFSET 0x0088 /* Peripherals independent clock configuration register 1 */ +#define STM32_RCC_BDCR_OFFSET 0x0090 /* Backup domain control register */ +#define STM32_RCC_CSR_OFFSET 0x0094 /* Control/status register */ +#define STM32_RCC_EXTCFGR_OFFSET 0x0108 +#define STM32_RCC_C2AHB1ENR_OFFSET 0x0148 /* CPU2 AHB1 Peripheral Clock enable register */ +#define STM32_RCC_C2AHB2ENR_OFFSET 0x014c /* CPU2 AHB2 Peripheral Clock enable register */ +#define STM32_RCC_C2AHB3ENR_OFFSET 0x0150 /* CPU2 AHB3 Peripheral Clock enable register */ +#define STM32_RCC_C2APB1ENR1_OFFSET 0x0158 /* CPU2 APB1 Peripheral Clock enable register 1 */ +#define STM32_RCC_C2APB1ENR2_OFFSET 0x015c /* CPU2 APB1 Peripheral Clock enable register 2 */ +#define STM32_RCC_C2APB2ENR_OFFSET 0x0160 /* CPU2 APB2 Peripheral Clock enable register */ +#define STM32_RCC_C2APB3ENR_OFFSET 0x0164 /* CPU2 APB3 Peripheral Clock enable register */ +#define STM32_RCC_C2AHB1SMENR_OFFSET 0x0168 /* CPU2 RCC AHB1 low power mode peripheral clock enable register */ +#define STM32_RCC_C2AHB2SMENR_OFFSET 0x016c /* CPU2 RCC AHB2 low power mode peripheral clock enable register */ +#define STM32_RCC_C2AHB3SMENR_OFFSET 0x0170 /* CPU2 RCC AHB3 low power mode peripheral clock enable register */ +#define STM32_RCC_C2APB1SMENR1_OFFSET 0x0178 /* CPU2 RCC APB1 low power mode peripheral clock enable register 1 */ +#define STM32_RCC_C2APB1SMENR2_OFFSET 0x017c /* CPU2 RCC APB1 low power mode peripheral clock enable register 2 */ +#define STM32_RCC_C2APB2SMENR_OFFSET 0x0180 /* CPU2 RCC APB2 low power mode peripheral clock enable register */ +#define STM32_RCC_C2APB3SMENR_OFFSET 0x0184 /* CPU2 RCC APB3 low power mode peripheral clock enable register */ /* Register Addresses *******************************************************/ -#define STM32WL5_RCC_CR (STM32WL5_RCC_BASE + STM32WL5_RCC_CR_OFFSET) -#define STM32WL5_RCC_ICSCR (STM32WL5_RCC_BASE + STM32WL5_RCC_ICSCR_OFFSET) -#define STM32WL5_RCC_CFGR (STM32WL5_RCC_BASE + STM32WL5_RCC_CFGR_OFFSET) -#define STM32WL5_RCC_PLLCFG (STM32WL5_RCC_BASE + STM32WL5_RCC_PLLCFG_OFFSET) -#define STM32WL5_RCC_CIER (STM32WL5_RCC_BASE + STM32WL5_RCC_CIER_OFFSET) -#define STM32WL5_RCC_CIFR (STM32WL5_RCC_BASE + STM32WL5_RCC_CIFR_OFFSET) -#define STM32WL5_RCC_CICR (STM32WL5_RCC_BASE + STM32WL5_RCC_CICR_OFFSET) -#define STM32WL5_RCC_AHB1RSTR (STM32WL5_RCC_BASE + STM32WL5_RCC_AHB1RSTR_OFFSET) -#define STM32WL5_RCC_AHB2RSTR (STM32WL5_RCC_BASE + STM32WL5_RCC_AHB2RSTR_OFFSET) -#define STM32WL5_RCC_AHB3RSTR (STM32WL5_RCC_BASE + STM32WL5_RCC_AHB3RSTR_OFFSET) -#define STM32WL5_RCC_APB1RSTR1 (STM32WL5_RCC_BASE + STM32WL5_RCC_APB1RSTR1_OFFSET) -#define STM32WL5_RCC_APB1RSTR2 (STM32WL5_RCC_BASE + STM32WL5_RCC_APB1RSTR2_OFFSET) -#define STM32WL5_RCC_APB2RSTR (STM32WL5_RCC_BASE + STM32WL5_RCC_APB2RSTR_OFFSET) -#define STM32WL5_RCC_AHB1ENR (STM32WL5_RCC_BASE + STM32WL5_RCC_AHB1ENR_OFFSET) -#define STM32WL5_RCC_AHB2ENR (STM32WL5_RCC_BASE + STM32WL5_RCC_AHB2ENR_OFFSET) -#define STM32WL5_RCC_AHB3ENR (STM32WL5_RCC_BASE + STM32WL5_RCC_AHB3ENR_OFFSET) -#define STM32WL5_RCC_APB1ENR1 (STM32WL5_RCC_BASE + STM32WL5_RCC_APB1ENR1_OFFSET) -#define STM32WL5_RCC_APB1ENR2 (STM32WL5_RCC_BASE + STM32WL5_RCC_APB1ENR2_OFFSET) -#define STM32WL5_RCC_APB2ENR (STM32WL5_RCC_BASE + STM32WL5_RCC_APB2ENR_OFFSET) -#define STM32WL5_RCC_AHB1SMENR (STM32WL5_RCC_BASE + STM32WL5_RCC_AHB1SMENR_OFFSET) -#define STM32WL5_RCC_AHB2SMENR (STM32WL5_RCC_BASE + STM32WL5_RCC_AHB2SMENR_OFFSET) -#define STM32WL5_RCC_AHB3SMENR (STM32WL5_RCC_BASE + STM32WL5_RCC_AHB3SMENR_OFFSET) -#define STM32WL5_RCC_APB1SMENR1 (STM32WL5_RCC_BASE + STM32WL5_RCC_APB1SMENR1_OFFSET) -#define STM32WL5_RCC_APB1SMENR2 (STM32WL5_RCC_BASE + STM32WL5_RCC_APB1SMENR2_OFFSET) -#define STM32WL5_RCC_APB2SMENR (STM32WL5_RCC_BASE + STM32WL5_RCC_APB2SMENR_OFFSET) -#define STM32WL5_RCC_CCIPR (STM32WL5_RCC_BASE + STM32WL5_RCC_CCIPR_OFFSET) -#define STM32WL5_RCC_BDCR (STM32WL5_RCC_BASE + STM32WL5_RCC_BDCR_OFFSET) -#define STM32WL5_RCC_CSR (STM32WL5_RCC_BASE + STM32WL5_RCC_CSR_OFFSET) -#define STM32WL5_RCC_EXTCFGR (STM32WL5_RCC_BASE + STM32WL5_RCC_EXTCFGR_OFFSET) -#define STM32WL5_RCC_C2AHB1ENR (STM32WL5_RCC_BASE + STM32WL5_RCC_C2AHB1ENR_OFFSET) -#define STM32WL5_RCC_C2AHB2ENR (STM32WL5_RCC_BASE + STM32WL5_RCC_C2AHB2ENR_OFFSET) -#define STM32WL5_RCC_C2AHB3ENR (STM32WL5_RCC_BASE + STM32WL5_RCC_C2AHB3ENR_OFFSET) -#define STM32WL5_RCC_C2APB1ENR1 (STM32WL5_RCC_BASE + STM32WL5_RCC_C2APB1ENR1_OFFSET) -#define STM32WL5_RCC_C2APB1ENR2 (STM32WL5_RCC_BASE + STM32WL5_RCC_C2APB1ENR2_OFFSET) -#define STM32WL5_RCC_C2APB2ENR (STM32WL5_RCC_BASE + STM32WL5_RCC_C2APB2ENR_OFFSET) -#define STM32WL5_RCC_C2APB3ENR (STM32WL5_RCC_BASE + STM32WL5_RCC_C2APB3ENR_OFFSET) -#define STM32WL5_RCC_C2AHB1SMENR (STM32WL5_RCC_BASE + STM32WL5_RCC_C2AHB1SMENR_OFFSET) -#define STM32WL5_RCC_C2AHB2SMENR (STM32WL5_RCC_BASE + STM32WL5_RCC_C2AHB2SMENR_OFFSET) -#define STM32WL5_RCC_C2AHB3SMENR (STM32WL5_RCC_BASE + STM32WL5_RCC_C2AHB3SMENR_OFFSET) -#define STM32WL5_RCC_C2APB1SMENR1 (STM32WL5_RCC_BASE + STM32WL5_RCC_C2APB1SMENR1_OFFSET) -#define STM32WL5_RCC_C2APB1SMENR2 (STM32WL5_RCC_BASE + STM32WL5_RCC_C2APB1SMENR2_OFFSET) -#define STM32WL5_RCC_C2APB2SMENR (STM32WL5_RCC_BASE + STM32WL5_RCC_C2APB2SMENR_OFFSET) -#define STM32WL5_RCC_C2APB3SMENR (STM32WL5_RCC_BASE + STM32WL5_RCC_C2APB3SMENR_OFFSET) +#define STM32_RCC_CR (STM32_RCC_BASE + STM32_RCC_CR_OFFSET) +#define STM32_RCC_ICSCR (STM32_RCC_BASE + STM32_RCC_ICSCR_OFFSET) +#define STM32_RCC_CFGR (STM32_RCC_BASE + STM32_RCC_CFGR_OFFSET) +#define STM32_RCC_PLLCFG (STM32_RCC_BASE + STM32_RCC_PLLCFG_OFFSET) +#define STM32_RCC_CIER (STM32_RCC_BASE + STM32_RCC_CIER_OFFSET) +#define STM32_RCC_CIFR (STM32_RCC_BASE + STM32_RCC_CIFR_OFFSET) +#define STM32_RCC_CICR (STM32_RCC_BASE + STM32_RCC_CICR_OFFSET) +#define STM32_RCC_AHB1RSTR (STM32_RCC_BASE + STM32_RCC_AHB1RSTR_OFFSET) +#define STM32_RCC_AHB2RSTR (STM32_RCC_BASE + STM32_RCC_AHB2RSTR_OFFSET) +#define STM32_RCC_AHB3RSTR (STM32_RCC_BASE + STM32_RCC_AHB3RSTR_OFFSET) +#define STM32_RCC_APB1RSTR1 (STM32_RCC_BASE + STM32_RCC_APB1RSTR1_OFFSET) +#define STM32_RCC_APB1RSTR2 (STM32_RCC_BASE + STM32_RCC_APB1RSTR2_OFFSET) +#define STM32_RCC_APB2RSTR (STM32_RCC_BASE + STM32_RCC_APB2RSTR_OFFSET) +#define STM32_RCC_AHB1ENR (STM32_RCC_BASE + STM32_RCC_AHB1ENR_OFFSET) +#define STM32_RCC_AHB2ENR (STM32_RCC_BASE + STM32_RCC_AHB2ENR_OFFSET) +#define STM32_RCC_AHB3ENR (STM32_RCC_BASE + STM32_RCC_AHB3ENR_OFFSET) +#define STM32_RCC_APB1ENR1 (STM32_RCC_BASE + STM32_RCC_APB1ENR1_OFFSET) +#define STM32_RCC_APB1ENR2 (STM32_RCC_BASE + STM32_RCC_APB1ENR2_OFFSET) +#define STM32_RCC_APB2ENR (STM32_RCC_BASE + STM32_RCC_APB2ENR_OFFSET) +#define STM32_RCC_AHB1SMENR (STM32_RCC_BASE + STM32_RCC_AHB1SMENR_OFFSET) +#define STM32_RCC_AHB2SMENR (STM32_RCC_BASE + STM32_RCC_AHB2SMENR_OFFSET) +#define STM32_RCC_AHB3SMENR (STM32_RCC_BASE + STM32_RCC_AHB3SMENR_OFFSET) +#define STM32_RCC_APB1SMENR1 (STM32_RCC_BASE + STM32_RCC_APB1SMENR1_OFFSET) +#define STM32_RCC_APB1SMENR2 (STM32_RCC_BASE + STM32_RCC_APB1SMENR2_OFFSET) +#define STM32_RCC_APB2SMENR (STM32_RCC_BASE + STM32_RCC_APB2SMENR_OFFSET) +#define STM32_RCC_CCIPR (STM32_RCC_BASE + STM32_RCC_CCIPR_OFFSET) +#define STM32_RCC_BDCR (STM32_RCC_BASE + STM32_RCC_BDCR_OFFSET) +#define STM32_RCC_CSR (STM32_RCC_BASE + STM32_RCC_CSR_OFFSET) +#define STM32_RCC_EXTCFGR (STM32_RCC_BASE + STM32_RCC_EXTCFGR_OFFSET) +#define STM32_RCC_C2AHB1ENR (STM32_RCC_BASE + STM32_RCC_C2AHB1ENR_OFFSET) +#define STM32_RCC_C2AHB2ENR (STM32_RCC_BASE + STM32_RCC_C2AHB2ENR_OFFSET) +#define STM32_RCC_C2AHB3ENR (STM32_RCC_BASE + STM32_RCC_C2AHB3ENR_OFFSET) +#define STM32_RCC_C2APB1ENR1 (STM32_RCC_BASE + STM32_RCC_C2APB1ENR1_OFFSET) +#define STM32_RCC_C2APB1ENR2 (STM32_RCC_BASE + STM32_RCC_C2APB1ENR2_OFFSET) +#define STM32_RCC_C2APB2ENR (STM32_RCC_BASE + STM32_RCC_C2APB2ENR_OFFSET) +#define STM32_RCC_C2APB3ENR (STM32_RCC_BASE + STM32_RCC_C2APB3ENR_OFFSET) +#define STM32_RCC_C2AHB1SMENR (STM32_RCC_BASE + STM32_RCC_C2AHB1SMENR_OFFSET) +#define STM32_RCC_C2AHB2SMENR (STM32_RCC_BASE + STM32_RCC_C2AHB2SMENR_OFFSET) +#define STM32_RCC_C2AHB3SMENR (STM32_RCC_BASE + STM32_RCC_C2AHB3SMENR_OFFSET) +#define STM32_RCC_C2APB1SMENR1 (STM32_RCC_BASE + STM32_RCC_C2APB1SMENR1_OFFSET) +#define STM32_RCC_C2APB1SMENR2 (STM32_RCC_BASE + STM32_RCC_C2APB1SMENR2_OFFSET) +#define STM32_RCC_C2APB2SMENR (STM32_RCC_BASE + STM32_RCC_C2APB2SMENR_OFFSET) +#define STM32_RCC_C2APB3SMENR (STM32_RCC_BASE + STM32_RCC_C2APB3SMENR_OFFSET) /* Register Bitfield Definitions ********************************************/ diff --git a/arch/arm/src/stm32wl5/hardware/stm32wl5_spi.h b/arch/arm/src/stm32wl5/hardware/stm32wl5_spi.h index 22c61af23aedb..9e3afea3506bc 100644 --- a/arch/arm/src/stm32wl5/hardware/stm32wl5_spi.h +++ b/arch/arm/src/stm32wl5/hardware/stm32wl5_spi.h @@ -45,7 +45,7 @@ #undef HAVE_SPI_FIFOS /* No Tx/Rx FIFOs */ #undef HAVE_SPI_NSSP /* No NSS Pulse Management in master mode */ -#if defined(STM32WL5_HAVE_IP_SPI_V2) +#if defined(STM32_HAVE_IP_SPI_V2) # define HAVE_SPI_I2S /* Some SPI peripherals have I2S mode */ # undef HAVE_SPI_I2S_ASTRT /* No I2S asynchronous start capability */ # define HAVE_SPI_TI_MODE /* Have Motorola and TI frame modes */ @@ -54,7 +54,7 @@ # undef HAVE_SPI_NSSP /* No NSS Pulse Management in master mode */ #endif -#if defined(STM32WL5_HAVE_IP_SPI_V3) +#if defined(STM32_HAVE_IP_SPI_V3) # define HAVE_SPI_I2S /* Some SPI peripherals have I2S mode */ # undef HAVE_SPI_I2S_ASTRT /* No I2S asynchronous start capability */ # define HAVE_SPI_TI_MODE /* Have Motorola and TI frame modes */ @@ -63,7 +63,7 @@ # undef HAVE_SPI_NSSP /* No NSS Pulse Management in master mode */ #endif -#if defined(STM32WL5_HAVE_IP_SPI_V4) +#if defined(STM32_HAVE_IP_SPI_V4) # define HAVE_SPI_I2S /* Some SPI peripherals have I2S mode */ # define HAVE_SPI_I2S_ASTRT /* Supports I2S asynchronous start capability */ # define HAVE_SPI_TI_MODE /* Have Motorola and TI frame modes */ @@ -74,66 +74,66 @@ /* Maximum allowed speed as per specifications for all SPIs */ -#if defined(CONFIG_STM32WL5_STM32F4XXX) -# define STM32WL5_SPI_CLK_MAX 37500000UL +#if defined(CONFIG_STM32_STM32F4XXX) +# define STM32_SPI_CLK_MAX 37500000UL #else -# define STM32WL5_SPI_CLK_MAX 18000000UL +# define STM32_SPI_CLK_MAX 18000000UL #endif /* Register Offsets *********************************************************/ -#define STM32WL5_SPI_CR1_OFFSET 0x0000 /* SPI Control Register 1 (16-bit) */ -#define STM32WL5_SPI_CR2_OFFSET 0x0004 /* SPI control register 2 (16-bit) */ -#define STM32WL5_SPI_SR_OFFSET 0x0008 /* SPI status register (16-bit) */ -#define STM32WL5_SPI_DR_OFFSET 0x000c /* SPI data register (16-bit) */ -#define STM32WL5_SPI_CRCPR_OFFSET 0x0010 /* SPI CRC polynomial register (16-bit) */ -#define STM32WL5_SPI_RXCRCR_OFFSET 0x0014 /* SPI Rx CRC register (16-bit) */ -#define STM32WL5_SPI_TXCRCR_OFFSET 0x0018 /* SPI Tx CRC register (16-bit) */ +#define STM32_SPI_CR1_OFFSET 0x0000 /* SPI Control Register 1 (16-bit) */ +#define STM32_SPI_CR2_OFFSET 0x0004 /* SPI control register 2 (16-bit) */ +#define STM32_SPI_SR_OFFSET 0x0008 /* SPI status register (16-bit) */ +#define STM32_SPI_DR_OFFSET 0x000c /* SPI data register (16-bit) */ +#define STM32_SPI_CRCPR_OFFSET 0x0010 /* SPI CRC polynomial register (16-bit) */ +#define STM32_SPI_RXCRCR_OFFSET 0x0014 /* SPI Rx CRC register (16-bit) */ +#define STM32_SPI_TXCRCR_OFFSET 0x0018 /* SPI Tx CRC register (16-bit) */ #if defined(HAVE_SPI_I2S) -# define STM32WL5_SPI_I2SCFGR_OFFSET 0x001c /* I2S configuration register */ -# define STM32WL5_SPI_I2SPR_OFFSET 0x0020 /* I2S prescaler register */ +# define STM32_SPI_I2SCFGR_OFFSET 0x001c /* I2S configuration register */ +# define STM32_SPI_I2SPR_OFFSET 0x0020 /* I2S prescaler register */ #endif /* Register Addresses *******************************************************/ -#if STM32WL5_NSPI > 0 -# define STM32WL5_SPI1_CR1 \ - (STM32WL5_SPI1_BASE + STM32WL5_SPI_CR1_OFFSET) -# define STM32WL5_SPI1_CR2 \ - (STM32WL5_SPI1_BASE + STM32WL5_SPI_CR2_OFFSET) -# define STM32WL5_SPI1_SR \ - (STM32WL5_SPI1_BASE + STM32WL5_SPI_SR_OFFSET) -# define STM32WL5_SPI1_DR \ - (STM32WL5_SPI1_BASE + STM32WL5_SPI_DR_OFFSET) -# define STM32WL5_SPI1_CRCPR \ - (STM32WL5_SPI1_BASE + STM32WL5_SPI_CRCPR_OFFSET) -# define STM32WL5_SPI1_RXCRCR \ - (STM32WL5_SPI1_BASE + STM32WL5_SPI_RXCRCR_OFFSET) -# define STM32WL5_SPI1_TXCRCR \ - (STM32WL5_SPI1_BASE + STM32WL5_SPI_TXCRCR_OFFSET) +#if STM32_NSPI > 0 +# define STM32_SPI1_CR1 \ + (STM32_SPI1_BASE + STM32_SPI_CR1_OFFSET) +# define STM32_SPI1_CR2 \ + (STM32_SPI1_BASE + STM32_SPI_CR2_OFFSET) +# define STM32_SPI1_SR \ + (STM32_SPI1_BASE + STM32_SPI_SR_OFFSET) +# define STM32_SPI1_DR \ + (STM32_SPI1_BASE + STM32_SPI_DR_OFFSET) +# define STM32_SPI1_CRCPR \ + (STM32_SPI1_BASE + STM32_SPI_CRCPR_OFFSET) +# define STM32_SPI1_RXCRCR \ + (STM32_SPI1_BASE + STM32_SPI_RXCRCR_OFFSET) +# define STM32_SPI1_TXCRCR \ + (STM32_SPI1_BASE + STM32_SPI_TXCRCR_OFFSET) #endif -#if STM32WL5_NSPI > 1 -# define STM32WL5_SPI2S2_CR1 \ - (STM32WL5_SPI2S2_BASE + STM32WL5_SPI_CR1_OFFSET) -# define STM32WL5_SPI2S2_CR2 \ - (STM32WL5_SPI2S2_BASE + STM32WL5_SPI_CR2_OFFSET) -# define STM32WL5_SPI2S2_SR \ - (STM32WL5_SPI2S2_BASE + STM32WL5_SPI_SR_OFFSET) -# define STM32WL5_SPI2S2_DR \ - (STM32WL5_SPI2S2_BASE + STM32WL5_SPI_DR_OFFSET) -# define STM32WL5_SPI2S2_CRCPR \ - (STM32WL5_SPI2S2_BASE + STM32WL5_SPI_CRCPR_OFFSET) -# define STM32WL5_SPI2S2_RXCRCR \ - (STM32WL5_SPI2S2_BASE + STM32WL5_SPI_RXCRCR_OFFSET) -# define STM32WL5_SPI2S2_TXCRCR \ - (STM32WL5_SPI2S2_BASE + STM32WL5_SPI_TXCRCR_OFFSET) +#if STM32_NSPI > 1 +# define STM32_SPI2S2_CR1 \ + (STM32_SPI2S2_BASE + STM32_SPI_CR1_OFFSET) +# define STM32_SPI2S2_CR2 \ + (STM32_SPI2S2_BASE + STM32_SPI_CR2_OFFSET) +# define STM32_SPI2S2_SR \ + (STM32_SPI2S2_BASE + STM32_SPI_SR_OFFSET) +# define STM32_SPI2S2_DR \ + (STM32_SPI2S2_BASE + STM32_SPI_DR_OFFSET) +# define STM32_SPI2S2_CRCPR \ + (STM32_SPI2S2_BASE + STM32_SPI_CRCPR_OFFSET) +# define STM32_SPI2S2_RXCRCR \ + (STM32_SPI2S2_BASE + STM32_SPI_RXCRCR_OFFSET) +# define STM32_SPI2S2_TXCRCR \ + (STM32_SPI2S2_BASE + STM32_SPI_TXCRCR_OFFSET) # if defined(HAVE_SPI_I2S) -# define STM32WL5_SPI2S2_I2SCFGR \ - (STM32WL5_SPI2S2_BASE + STM32WL5_SPI_I2SCFGR_OFFSET) -# define STM32WL5_SPI2S2_I2SPR \ - (STM32WL5_SPI2S2_BASE + STM32WL5_SPI_I2SPR_OFFSET) +# define STM32_SPI2S2_I2SCFGR \ + (STM32_SPI2S2_BASE + STM32_SPI_I2SCFGR_OFFSET) +# define STM32_SPI2S2_I2SPR \ + (STM32_SPI2S2_BASE + STM32_SPI_I2SPR_OFFSET) # endif #endif diff --git a/arch/arm/src/stm32wl5/hardware/stm32wl5_syscfg.h b/arch/arm/src/stm32wl5/hardware/stm32wl5_syscfg.h index eaf17d3ad0d82..b0025be1da990 100644 --- a/arch/arm/src/stm32wl5/hardware/stm32wl5_syscfg.h +++ b/arch/arm/src/stm32wl5/hardware/stm32wl5_syscfg.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32WL5_HARDWARE_STM32WL5_SYSCFG_H -#define __ARCH_ARM_SRC_STM32WL5_HARDWARE_STM32WL5_SYSCFG_H +#ifndef __ARCH_ARM_SRC_STM32WL5_HARDWARE_STM32_SYSCFG_H +#define __ARCH_ARM_SRC_STM32WL5_HARDWARE_STM32_SYSCFG_H /**************************************************************************** * Included Files @@ -36,43 +36,43 @@ /* Register Offsets *********************************************************/ -#define STM32WL5_SYSCFG_MEMRMP_OFFSET 0x0000 /* SYSCFG memory remap register */ -#define STM32WL5_SYSCFG_CFGR1_OFFSET 0x0004 /* SYSCFG configuration register 1 */ - -#define STM32WL5_SYSCFG_EXTICR_OFFSET(p) (0x0008 + ((p) & 0x000c)) /* Registers are displaced by 4! */ - -#define STM32WL5_SYSCFG_EXTICR1_OFFSET 0x0008 /* SYSCFG external interrupt configuration register 1 */ -#define STM32WL5_SYSCFG_EXTICR2_OFFSET 0x000c /* SYSCFG external interrupt configuration register 2 */ -#define STM32WL5_SYSCFG_EXTICR3_OFFSET 0x0010 /* SYSCFG external interrupt configuration register 3 */ -#define STM32WL5_SYSCFG_EXTICR4_OFFSET 0x0014 /* SYSCFG external interrupt configuration register 4 */ -#define STM32WL5_SYSCFG_SCSR_OFFSET 0x0018 /* SYSCFG SRAM2 control and status register */ -#define STM32WL5_SYSCFG_CFGR2_OFFSET 0x001c /* SYSCFG configuration register 2 */ -#define STM32WL5_SYSCFG_SWPR_OFFSET 0x0020 /* SYSCFG SRAM2 write protection register */ -#define STM32WL5_SYSCFG_SKR_OFFSET 0x0024 /* SYSCFG SRAM2 key register */ -#define STM32WL5_SYSCFG_IMR1_OFFSET 0x0100 /* SYSCFG cpu1 interrupt mask register 1 */ -#define STM32WL5_SYSCFG_IMR2_OFFSET 0x0104 /* SYSCFG cpu1 interrupt mask register 2 */ -#define STM32WL5_SYSCFG_C2IMR1_OFFSET 0x0108 /* SYSCFG cpu2 interrupt mask register 1 */ -#define STM32WL5_SYSCFG_C2IMR2_OFFSET 0x010c /* SYSCFG cpu2 interrupt mask register 2 */ -#define STM32WL5_SYSCFG_RFDCR_OFFSET 0x0208 /* SYSCFG radio debug control register */ +#define STM32_SYSCFG_MEMRMP_OFFSET 0x0000 /* SYSCFG memory remap register */ +#define STM32_SYSCFG_CFGR1_OFFSET 0x0004 /* SYSCFG configuration register 1 */ + +#define STM32_SYSCFG_EXTICR_OFFSET(p) (0x0008 + ((p) & 0x000c)) /* Registers are displaced by 4! */ + +#define STM32_SYSCFG_EXTICR1_OFFSET 0x0008 /* SYSCFG external interrupt configuration register 1 */ +#define STM32_SYSCFG_EXTICR2_OFFSET 0x000c /* SYSCFG external interrupt configuration register 2 */ +#define STM32_SYSCFG_EXTICR3_OFFSET 0x0010 /* SYSCFG external interrupt configuration register 3 */ +#define STM32_SYSCFG_EXTICR4_OFFSET 0x0014 /* SYSCFG external interrupt configuration register 4 */ +#define STM32_SYSCFG_SCSR_OFFSET 0x0018 /* SYSCFG SRAM2 control and status register */ +#define STM32_SYSCFG_CFGR2_OFFSET 0x001c /* SYSCFG configuration register 2 */ +#define STM32_SYSCFG_SWPR_OFFSET 0x0020 /* SYSCFG SRAM2 write protection register */ +#define STM32_SYSCFG_SKR_OFFSET 0x0024 /* SYSCFG SRAM2 key register */ +#define STM32_SYSCFG_IMR1_OFFSET 0x0100 /* SYSCFG cpu1 interrupt mask register 1 */ +#define STM32_SYSCFG_IMR2_OFFSET 0x0104 /* SYSCFG cpu1 interrupt mask register 2 */ +#define STM32_SYSCFG_C2IMR1_OFFSET 0x0108 /* SYSCFG cpu2 interrupt mask register 1 */ +#define STM32_SYSCFG_C2IMR2_OFFSET 0x010c /* SYSCFG cpu2 interrupt mask register 2 */ +#define STM32_SYSCFG_RFDCR_OFFSET 0x0208 /* SYSCFG radio debug control register */ /* Register Addresses *******************************************************/ -#define STM32WL5_SYSCFG_MEMRMP (STM32WL5_SYSCFG_BASE+STM32WL5_SYSCFG_MEMRMP_OFFSET) -#define STM32WL5_SYSCFG_CFGR1 (STM32WL5_SYSCFG_BASE+STM32WL5_SYSCFG_CFGR1_OFFSET) -#define STM32WL5_SYSCFG_EXTICR(p) (STM32WL5_SYSCFG_BASE+STM32WL5_SYSCFG_EXTICR_OFFSET(p)) -#define STM32WL5_SYSCFG_EXTICR1 (STM32WL5_SYSCFG_BASE+STM32WL5_SYSCFG_EXTICR1) -#define STM32WL5_SYSCFG_EXTICR2 (STM32WL5_SYSCFG_BASE+STM32WL5_SYSCFG_EXTICR2) -#define STM32WL5_SYSCFG_EXTICR3 (STM32WL5_SYSCFG_BASE+STM32WL5_SYSCFG_EXTICR3) -#define STM32WL5_SYSCFG_EXTICR4 (STM32WL5_SYSCFG_BASE+STM32WL5_SYSCFG_EXTICR4) -#define STM32WL5_SYSCFG_SCSR (STM32WL5_SYSCFG_BASE+STM32WL5_SYSCFG_SCSR) -#define STM32WL5_SYSCFG_CFGR2 (STM32WL5_SYSCFG_BASE+STM32WL5_SYSCFG_CFGR2) -#define STM32WL5_SYSCFG_SWPR (STM32WL5_SYSCFG_BASE+STM32WL5_SYSCFG_SWPR) -#define STM32WL5_SYSCFG_SKR (STM32WL5_SYSCFG_BASE+STM32WL5_SYSCFG_SKR) -#define STM32WL5_SYSCFG_IMR1 (STM32WL5_SYSCFG_BASE+STM32WL5_SYSCFG_IMR1) -#define STM32WL5_SYSCFG_IMR2 (STM32WL5_SYSCFG_BASE+STM32WL5_SYSCFG_IMR2) -#define STM32WL5_SYSCFG_C2IMR1 (STM32WL5_SYSCFG_BASE+STM32WL5_SYSCFG_C2IMR1) -#define STM32WL5_SYSCFG_C2IMR2 (STM32WL5_SYSCFG_BASE+STM32WL5_SYSCFG_C2IMR2) -#define STM32WL5_SYSCFG_RFDCR (STM32WL5_SYSCFG_BASE+STM32WL5_SYSCFG_RFDCR) +#define STM32_SYSCFG_MEMRMP (STM32_SYSCFG_BASE+STM32_SYSCFG_MEMRMP_OFFSET) +#define STM32_SYSCFG_CFGR1 (STM32_SYSCFG_BASE+STM32_SYSCFG_CFGR1_OFFSET) +#define STM32_SYSCFG_EXTICR(p) (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR_OFFSET(p)) +#define STM32_SYSCFG_EXTICR1 (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR1) +#define STM32_SYSCFG_EXTICR2 (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR2) +#define STM32_SYSCFG_EXTICR3 (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR3) +#define STM32_SYSCFG_EXTICR4 (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR4) +#define STM32_SYSCFG_SCSR (STM32_SYSCFG_BASE+STM32_SYSCFG_SCSR) +#define STM32_SYSCFG_CFGR2 (STM32_SYSCFG_BASE+STM32_SYSCFG_CFGR2) +#define STM32_SYSCFG_SWPR (STM32_SYSCFG_BASE+STM32_SYSCFG_SWPR) +#define STM32_SYSCFG_SKR (STM32_SYSCFG_BASE+STM32_SYSCFG_SKR) +#define STM32_SYSCFG_IMR1 (STM32_SYSCFG_BASE+STM32_SYSCFG_IMR1) +#define STM32_SYSCFG_IMR2 (STM32_SYSCFG_BASE+STM32_SYSCFG_IMR2) +#define STM32_SYSCFG_C2IMR1 (STM32_SYSCFG_BASE+STM32_SYSCFG_C2IMR1) +#define STM32_SYSCFG_C2IMR2 (STM32_SYSCFG_BASE+STM32_SYSCFG_C2IMR2) +#define STM32_SYSCFG_RFDCR (STM32_SYSCFG_BASE+STM32_SYSCFG_RFDCR) /* Register Bitfield Definitions ********************************************/ @@ -243,4 +243,4 @@ #define SYSCFG_RFDCR_RFTBSEL (1 << 0) /* Bit 0: Analog test bus on RF[ADTB[3:0] */ -#endif /* __ARCH_ARM_SRC_STM32WL5_HARDWARE_STM32WL5_SYSCFG_H */ +#endif /* __ARCH_ARM_SRC_STM32WL5_HARDWARE_STM32_SYSCFG_H */ diff --git a/arch/arm/src/stm32wl5/hardware/stm32wl5_tim.h b/arch/arm/src/stm32wl5/hardware/stm32wl5_tim.h index 1ffe5b780381b..3871365bc4920 100644 --- a/arch/arm/src/stm32wl5/hardware/stm32wl5_tim.h +++ b/arch/arm/src/stm32wl5/hardware/stm32wl5_tim.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32WL5_HARDWARE_STM32WL5_TIM_H -#define __ARCH_ARM_SRC_STM32WL5_HARDWARE_STM32WL5_TIM_H +#ifndef __ARCH_ARM_SRC_STM32WL5_HARDWARE_STM32_TIM_H +#define __ARCH_ARM_SRC_STM32WL5_HARDWARE_STM32_TIM_H /**************************************************************************** * Pre-processor Definitions @@ -31,166 +31,166 @@ /* Basic Timers - TIM6 and TIM7 */ -#define STM32WL5_BTIM_CR1_OFFSET 0x0000 /* Control register 1 (16-bit) */ -#define STM32WL5_BTIM_CR2_OFFSET 0x0004 /* Control register 2 (16-bit) */ -#define STM32WL5_BTIM_DIER_OFFSET 0x000c /* DMA/Interrupt enable register (16-bit) */ -#define STM32WL5_BTIM_SR_OFFSET 0x0010 /* Status register (16-bit) */ -#define STM32WL5_BTIM_EGR_OFFSET 0x0014 /* Event generation register (16-bit) */ -#define STM32WL5_BTIM_CCMR1_OFFSET 0x0018 /* Capture/compare mode */ -#define STM32WL5_BTIM_CCER_OFFSET 0x0020 /* Capture/compare enable register */ -#define STM32WL5_BTIM_CNT_OFFSET 0x0024 /* Counter (16-bit) */ -#define STM32WL5_BTIM_PSC_OFFSET 0x0028 /* Prescaler (16-bit) */ -#define STM32WL5_BTIM_ARR_OFFSET 0x002c /* Auto-reload register (16-bit) */ +#define STM32_BTIM_CR1_OFFSET 0x0000 /* Control register 1 (16-bit) */ +#define STM32_BTIM_CR2_OFFSET 0x0004 /* Control register 2 (16-bit) */ +#define STM32_BTIM_DIER_OFFSET 0x000c /* DMA/Interrupt enable register (16-bit) */ +#define STM32_BTIM_SR_OFFSET 0x0010 /* Status register (16-bit) */ +#define STM32_BTIM_EGR_OFFSET 0x0014 /* Event generation register (16-bit) */ +#define STM32_BTIM_CCMR1_OFFSET 0x0018 /* Capture/compare mode */ +#define STM32_BTIM_CCER_OFFSET 0x0020 /* Capture/compare enable register */ +#define STM32_BTIM_CNT_OFFSET 0x0024 /* Counter (16-bit) */ +#define STM32_BTIM_PSC_OFFSET 0x0028 /* Prescaler (16-bit) */ +#define STM32_BTIM_ARR_OFFSET 0x002c /* Auto-reload register (16-bit) */ /* 32-bit General Timers - TIM2 * TIM2 and 5 are 32-bit. * TIM15, 16 and 17 are 16-bit. */ -#define STM32WL5_GTIM_CR1_OFFSET 0x0000 /* Control register 1 (16-bit) */ -#define STM32WL5_GTIM_CR2_OFFSET 0x0004 /* Control register 2 (16-bit) */ -#define STM32WL5_GTIM_SMCR_OFFSET 0x0008 /* Slave mode control register (16-bit, TIM2-5,15 only) */ -#define STM32WL5_GTIM_DIER_OFFSET 0x000c /* DMA/Interrupt enable register (16-bit) */ -#define STM32WL5_GTIM_SR_OFFSET 0x0010 /* Status register (16-bit) */ -#define STM32WL5_GTIM_EGR_OFFSET 0x0014 /* Event generation register (16-bit) */ -#define STM32WL5_GTIM_CCMR1_OFFSET 0x0018 /* Capture/compare mode register 1 (32-bit) */ -#define STM32WL5_GTIM_CCMR2_OFFSET 0x001c /* Capture/compare mode register 2 (32-bit, TIM2-5 only) */ -#define STM32WL5_GTIM_CCER_OFFSET 0x0020 /* Capture/compare enable register (16-bit) */ -#define STM32WL5_GTIM_CNT_OFFSET 0x0024 /* Counter (16-bit or 32-bit TIM2/5) */ -#define STM32WL5_GTIM_PSC_OFFSET 0x0028 /* Prescaler (16-bit) */ -#define STM32WL5_GTIM_ARR_OFFSET 0x002c /* Auto-reload register (16-bit or 32-bit TIM2/5) */ -#define STM32WL5_GTIM_CCR1_OFFSET 0x0034 /* Capture/compare register 1 (16-bit or 32-bit TIM2/5) */ -#define STM32WL5_GTIM_CCR2_OFFSET 0x0038 /* Capture/compare register 2 (16-bit TIM2-5,15 only or 32-bit TIM2/5) */ -#define STM32WL5_GTIM_CCR3_OFFSET 0x003c /* Capture/compare register 3 (16-bit TIM2-5 only or 32-bit TIM2/5) */ -#define STM32WL5_GTIM_CCR4_OFFSET 0x0040 /* Capture/compare register 4 (16-bit TIM2-5 only or 32-bit TIM2/5) */ -#define STM32WL5_GTIM_DCR_OFFSET 0x0048 /* DMA control register (16-bit) */ -#define STM32WL5_GTIM_DMAR_OFFSET 0x004c /* DMA address for burst mode (16-bit) */ -#define STM32WL5_GTIM_OR1_OFFSET 0x0050 /* Option register 1 */ -#define STM32WL5_GTIM_OR2_OFFSET 0x0060 /* Option register 2 */ +#define STM32_GTIM_CR1_OFFSET 0x0000 /* Control register 1 (16-bit) */ +#define STM32_GTIM_CR2_OFFSET 0x0004 /* Control register 2 (16-bit) */ +#define STM32_GTIM_SMCR_OFFSET 0x0008 /* Slave mode control register (16-bit, TIM2-5,15 only) */ +#define STM32_GTIM_DIER_OFFSET 0x000c /* DMA/Interrupt enable register (16-bit) */ +#define STM32_GTIM_SR_OFFSET 0x0010 /* Status register (16-bit) */ +#define STM32_GTIM_EGR_OFFSET 0x0014 /* Event generation register (16-bit) */ +#define STM32_GTIM_CCMR1_OFFSET 0x0018 /* Capture/compare mode register 1 (32-bit) */ +#define STM32_GTIM_CCMR2_OFFSET 0x001c /* Capture/compare mode register 2 (32-bit, TIM2-5 only) */ +#define STM32_GTIM_CCER_OFFSET 0x0020 /* Capture/compare enable register (16-bit) */ +#define STM32_GTIM_CNT_OFFSET 0x0024 /* Counter (16-bit or 32-bit TIM2/5) */ +#define STM32_GTIM_PSC_OFFSET 0x0028 /* Prescaler (16-bit) */ +#define STM32_GTIM_ARR_OFFSET 0x002c /* Auto-reload register (16-bit or 32-bit TIM2/5) */ +#define STM32_GTIM_CCR1_OFFSET 0x0034 /* Capture/compare register 1 (16-bit or 32-bit TIM2/5) */ +#define STM32_GTIM_CCR2_OFFSET 0x0038 /* Capture/compare register 2 (16-bit TIM2-5,15 only or 32-bit TIM2/5) */ +#define STM32_GTIM_CCR3_OFFSET 0x003c /* Capture/compare register 3 (16-bit TIM2-5 only or 32-bit TIM2/5) */ +#define STM32_GTIM_CCR4_OFFSET 0x0040 /* Capture/compare register 4 (16-bit TIM2-5 only or 32-bit TIM2/5) */ +#define STM32_GTIM_DCR_OFFSET 0x0048 /* DMA control register (16-bit) */ +#define STM32_GTIM_DMAR_OFFSET 0x004c /* DMA address for burst mode (16-bit) */ +#define STM32_GTIM_OR1_OFFSET 0x0050 /* Option register 1 */ +#define STM32_GTIM_OR2_OFFSET 0x0060 /* Option register 2 */ /* TIM15, 16, and 17 only. */ -#define STM32WL5_GTIM_RCR_OFFSET 0x0030 /* Repetition counter register (TIM16/TIM17) */ -#define STM32WL5_GTIM_BDTR_OFFSET 0x0044 /* Break and dead-time register (TIM16/TIM17) */ +#define STM32_GTIM_RCR_OFFSET 0x0030 /* Repetition counter register (TIM16/TIM17) */ +#define STM32_GTIM_BDTR_OFFSET 0x0044 /* Break and dead-time register (TIM16/TIM17) */ /* Advanced Timers - TIM1 */ -#define STM32WL5_ATIM_CR1_OFFSET 0x0000 /* Control register 1 (16-bit) */ -#define STM32WL5_ATIM_CR2_OFFSET 0x0004 /* Control register 2 (16-bit*) */ -#define STM32WL5_ATIM_SMCR_OFFSET 0x0008 /* Slave mode control register (16-bit) */ -#define STM32WL5_ATIM_DIER_OFFSET 0x000c /* DMA/Interrupt enable register (16-bit) */ -#define STM32WL5_ATIM_SR_OFFSET 0x0010 /* Status register (16-bit*) */ -#define STM32WL5_ATIM_EGR_OFFSET 0x0014 /* Event generation register (16-bit) */ -#define STM32WL5_ATIM_CCMR1_OFFSET 0x0018 /* Capture/compare mode register 1 (16-bit*) */ -#define STM32WL5_ATIM_CCMR2_OFFSET 0x001c /* Capture/compare mode register 2 (16-bit*) */ -#define STM32WL5_ATIM_CCER_OFFSET 0x0020 /* Capture/compare enable register (16-bit*) */ -#define STM32WL5_ATIM_CNT_OFFSET 0x0024 /* Counter (16-bit) */ -#define STM32WL5_ATIM_PSC_OFFSET 0x0028 /* Prescaler (16-bit) */ -#define STM32WL5_ATIM_ARR_OFFSET 0x002c /* Auto-reload register (16-bit) */ -#define STM32WL5_ATIM_RCR_OFFSET 0x0030 /* Repetition counter register (16-bit) */ -#define STM32WL5_ATIM_CCR1_OFFSET 0x0034 /* Capture/compare register 1 (16-bit) */ -#define STM32WL5_ATIM_CCR2_OFFSET 0x0038 /* Capture/compare register 2 (16-bit) */ -#define STM32WL5_ATIM_CCR3_OFFSET 0x003c /* Capture/compare register 3 (16-bit) */ -#define STM32WL5_ATIM_CCR4_OFFSET 0x0040 /* Capture/compare register 4 (16-bit) */ -#define STM32WL5_ATIM_BDTR_OFFSET 0x0044 /* Break and dead-time register (16-bit*) */ -#define STM32WL5_ATIM_DCR_OFFSET 0x0048 /* DMA control register (16-bit) */ -#define STM32WL5_ATIM_DMAR_OFFSET 0x004c /* DMA address for burst mode (16-bit) */ -#define STM32WL5_ATIM_OR1_OFFSET 0x0050 /* Timer option register 1 */ -#define STM32WL5_ATIM_CCMR3_OFFSET 0x0054 /* Capture/compare mode register 3 (32-bit) */ -#define STM32WL5_ATIM_CCR5_OFFSET 0x0058 /* Capture/compare register 4 (16-bit) */ -#define STM32WL5_ATIM_CCR6_OFFSET 0x005c /* Capture/compare register 4 (32-bit) */ -#define STM32WL5_ATIM_OR2_OFFSET 0x0050 /* Timer option register 2 */ -#define STM32WL5_ATIM_OR3_OFFSET 0x0050 /* Timer option register 3 */ +#define STM32_ATIM_CR1_OFFSET 0x0000 /* Control register 1 (16-bit) */ +#define STM32_ATIM_CR2_OFFSET 0x0004 /* Control register 2 (16-bit*) */ +#define STM32_ATIM_SMCR_OFFSET 0x0008 /* Slave mode control register (16-bit) */ +#define STM32_ATIM_DIER_OFFSET 0x000c /* DMA/Interrupt enable register (16-bit) */ +#define STM32_ATIM_SR_OFFSET 0x0010 /* Status register (16-bit*) */ +#define STM32_ATIM_EGR_OFFSET 0x0014 /* Event generation register (16-bit) */ +#define STM32_ATIM_CCMR1_OFFSET 0x0018 /* Capture/compare mode register 1 (16-bit*) */ +#define STM32_ATIM_CCMR2_OFFSET 0x001c /* Capture/compare mode register 2 (16-bit*) */ +#define STM32_ATIM_CCER_OFFSET 0x0020 /* Capture/compare enable register (16-bit*) */ +#define STM32_ATIM_CNT_OFFSET 0x0024 /* Counter (16-bit) */ +#define STM32_ATIM_PSC_OFFSET 0x0028 /* Prescaler (16-bit) */ +#define STM32_ATIM_ARR_OFFSET 0x002c /* Auto-reload register (16-bit) */ +#define STM32_ATIM_RCR_OFFSET 0x0030 /* Repetition counter register (16-bit) */ +#define STM32_ATIM_CCR1_OFFSET 0x0034 /* Capture/compare register 1 (16-bit) */ +#define STM32_ATIM_CCR2_OFFSET 0x0038 /* Capture/compare register 2 (16-bit) */ +#define STM32_ATIM_CCR3_OFFSET 0x003c /* Capture/compare register 3 (16-bit) */ +#define STM32_ATIM_CCR4_OFFSET 0x0040 /* Capture/compare register 4 (16-bit) */ +#define STM32_ATIM_BDTR_OFFSET 0x0044 /* Break and dead-time register (16-bit*) */ +#define STM32_ATIM_DCR_OFFSET 0x0048 /* DMA control register (16-bit) */ +#define STM32_ATIM_DMAR_OFFSET 0x004c /* DMA address for burst mode (16-bit) */ +#define STM32_ATIM_OR1_OFFSET 0x0050 /* Timer option register 1 */ +#define STM32_ATIM_CCMR3_OFFSET 0x0054 /* Capture/compare mode register 3 (32-bit) */ +#define STM32_ATIM_CCR5_OFFSET 0x0058 /* Capture/compare register 4 (16-bit) */ +#define STM32_ATIM_CCR6_OFFSET 0x005c /* Capture/compare register 4 (32-bit) */ +#define STM32_ATIM_OR2_OFFSET 0x0050 /* Timer option register 2 */ +#define STM32_ATIM_OR3_OFFSET 0x0050 /* Timer option register 3 */ /* Register Addresses *******************************************************/ /* Advanced Timers - TIM1 and TIM8 */ -#define STM32WL5_TIM1_CR1 (STM32WL5_TIM1_BASE+STM32WL5_ATIM_CR1_OFFSET) -#define STM32WL5_TIM1_CR2 (STM32WL5_TIM1_BASE+STM32WL5_ATIM_CR2_OFFSET) -#define STM32WL5_TIM1_SMCR (STM32WL5_TIM1_BASE+STM32WL5_ATIM_SMCR_OFFSET) -#define STM32WL5_TIM1_DIER (STM32WL5_TIM1_BASE+STM32WL5_ATIM_DIER_OFFSET) -#define STM32WL5_TIM1_SR (STM32WL5_TIM1_BASE+STM32WL5_ATIM_SR_OFFSET) -#define STM32WL5_TIM1_EGR (STM32WL5_TIM1_BASE+STM32WL5_ATIM_EGR_OFFSET) -#define STM32WL5_TIM1_CCMR1 (STM32WL5_TIM1_BASE+STM32WL5_ATIM_CCMR1_OFFSET) -#define STM32WL5_TIM1_CCMR2 (STM32WL5_TIM1_BASE+STM32WL5_ATIM_CCMR2_OFFSET) -#define STM32WL5_TIM1_CCER (STM32WL5_TIM1_BASE+STM32WL5_ATIM_CCER_OFFSET) -#define STM32WL5_TIM1_CNT (STM32WL5_TIM1_BASE+STM32WL5_ATIM_CNT_OFFSET) -#define STM32WL5_TIM1_PSC (STM32WL5_TIM1_BASE+STM32WL5_ATIM_PSC_OFFSET) -#define STM32WL5_TIM1_ARR (STM32WL5_TIM1_BASE+STM32WL5_ATIM_ARR_OFFSET) -#define STM32WL5_TIM1_RCR (STM32WL5_TIM1_BASE+STM32WL5_ATIM_RCR_OFFSET) -#define STM32WL5_TIM1_CCR1 (STM32WL5_TIM1_BASE+STM32WL5_ATIM_CCR1_OFFSET) -#define STM32WL5_TIM1_CCR2 (STM32WL5_TIM1_BASE+STM32WL5_ATIM_CCR2_OFFSET) -#define STM32WL5_TIM1_CCR3 (STM32WL5_TIM1_BASE+STM32WL5_ATIM_CCR3_OFFSET) -#define STM32WL5_TIM1_CCR4 (STM32WL5_TIM1_BASE+STM32WL5_ATIM_CCR4_OFFSET) -#define STM32WL5_TIM1_BDTR (STM32WL5_TIM1_BASE+STM32WL5_ATIM_BDTR_OFFSET) -#define STM32WL5_TIM1_DCR (STM32WL5_TIM1_BASE+STM32WL5_ATIM_DCR_OFFSET) -#define STM32WL5_TIM1_DMAR (STM32WL5_TIM1_BASE+STM32WL5_ATIM_DMAR_OFFSET) -#define STM32WL5_TIM1_OR1 (STM32WL5_TIM1_BASE+STM32WL5_ATIM_OR1_OFFSET) -#define STM32WL5_TIM1_CCMR3 (STM32WL5_TIM1_BASE+STM32WL5_ATIM_CCMR3_OFFSET) -#define STM32WL5_TIM1_CCR5 (STM32WL5_TIM1_BASE+STM32WL5_ATIM_CCR5_OFFSET) -#define STM32WL5_TIM1_CCR6 (STM32WL5_TIM1_BASE+STM32WL5_ATIM_CCR6_OFFSET) -#define STM32WL5_TIM1_OR2 (STM32WL5_TIM1_BASE+STM32WL5_ATIM_OR2_OFFSET) -#define STM32WL5_TIM1_OR3 (STM32WL5_TIM1_BASE+STM32WL5_ATIM_OR3_OFFSET) +#define STM32_TIM1_CR1 (STM32_TIM1_BASE+STM32_ATIM_CR1_OFFSET) +#define STM32_TIM1_CR2 (STM32_TIM1_BASE+STM32_ATIM_CR2_OFFSET) +#define STM32_TIM1_SMCR (STM32_TIM1_BASE+STM32_ATIM_SMCR_OFFSET) +#define STM32_TIM1_DIER (STM32_TIM1_BASE+STM32_ATIM_DIER_OFFSET) +#define STM32_TIM1_SR (STM32_TIM1_BASE+STM32_ATIM_SR_OFFSET) +#define STM32_TIM1_EGR (STM32_TIM1_BASE+STM32_ATIM_EGR_OFFSET) +#define STM32_TIM1_CCMR1 (STM32_TIM1_BASE+STM32_ATIM_CCMR1_OFFSET) +#define STM32_TIM1_CCMR2 (STM32_TIM1_BASE+STM32_ATIM_CCMR2_OFFSET) +#define STM32_TIM1_CCER (STM32_TIM1_BASE+STM32_ATIM_CCER_OFFSET) +#define STM32_TIM1_CNT (STM32_TIM1_BASE+STM32_ATIM_CNT_OFFSET) +#define STM32_TIM1_PSC (STM32_TIM1_BASE+STM32_ATIM_PSC_OFFSET) +#define STM32_TIM1_ARR (STM32_TIM1_BASE+STM32_ATIM_ARR_OFFSET) +#define STM32_TIM1_RCR (STM32_TIM1_BASE+STM32_ATIM_RCR_OFFSET) +#define STM32_TIM1_CCR1 (STM32_TIM1_BASE+STM32_ATIM_CCR1_OFFSET) +#define STM32_TIM1_CCR2 (STM32_TIM1_BASE+STM32_ATIM_CCR2_OFFSET) +#define STM32_TIM1_CCR3 (STM32_TIM1_BASE+STM32_ATIM_CCR3_OFFSET) +#define STM32_TIM1_CCR4 (STM32_TIM1_BASE+STM32_ATIM_CCR4_OFFSET) +#define STM32_TIM1_BDTR (STM32_TIM1_BASE+STM32_ATIM_BDTR_OFFSET) +#define STM32_TIM1_DCR (STM32_TIM1_BASE+STM32_ATIM_DCR_OFFSET) +#define STM32_TIM1_DMAR (STM32_TIM1_BASE+STM32_ATIM_DMAR_OFFSET) +#define STM32_TIM1_OR1 (STM32_TIM1_BASE+STM32_ATIM_OR1_OFFSET) +#define STM32_TIM1_CCMR3 (STM32_TIM1_BASE+STM32_ATIM_CCMR3_OFFSET) +#define STM32_TIM1_CCR5 (STM32_TIM1_BASE+STM32_ATIM_CCR5_OFFSET) +#define STM32_TIM1_CCR6 (STM32_TIM1_BASE+STM32_ATIM_CCR6_OFFSET) +#define STM32_TIM1_OR2 (STM32_TIM1_BASE+STM32_ATIM_OR2_OFFSET) +#define STM32_TIM1_OR3 (STM32_TIM1_BASE+STM32_ATIM_OR3_OFFSET) /* 16-/32-bit General Timers - TIM2, TIM16-17. * TIM2 is 32-bit. * TIM16 and 17 are 16-bit. */ -#define STM32WL5_TIM2_CR1 (STM32WL5_TIM2_BASE+STM32WL5_GTIM_CR1_OFFSET) -#define STM32WL5_TIM2_CR2 (STM32WL5_TIM2_BASE+STM32WL5_GTIM_CR2_OFFSET) -#define STM32WL5_TIM2_SMCR (STM32WL5_TIM2_BASE+STM32WL5_GTIM_SMCR_OFFSET) -#define STM32WL5_TIM2_DIER (STM32WL5_TIM2_BASE+STM32WL5_GTIM_DIER_OFFSET) -#define STM32WL5_TIM2_SR (STM32WL5_TIM2_BASE+STM32WL5_GTIM_SR_OFFSET) -#define STM32WL5_TIM2_EGR (STM32WL5_TIM2_BASE+STM32WL5_GTIM_EGR_OFFSET) -#define STM32WL5_TIM2_CCMR1 (STM32WL5_TIM2_BASE+STM32WL5_GTIM_CCMR1_OFFSET) -#define STM32WL5_TIM2_CCMR2 (STM32WL5_TIM2_BASE+STM32WL5_GTIM_CCMR2_OFFSET) -#define STM32WL5_TIM2_CCER (STM32WL5_TIM2_BASE+STM32WL5_GTIM_CCER_OFFSET) -#define STM32WL5_TIM2_CNT (STM32WL5_TIM2_BASE+STM32WL5_GTIM_CNT_OFFSET) -#define STM32WL5_TIM2_PSC (STM32WL5_TIM2_BASE+STM32WL5_GTIM_PSC_OFFSET) -#define STM32WL5_TIM2_ARR (STM32WL5_TIM2_BASE+STM32WL5_GTIM_ARR_OFFSET) -#define STM32WL5_TIM2_CCR1 (STM32WL5_TIM2_BASE+STM32WL5_GTIM_CCR1_OFFSET) -#define STM32WL5_TIM2_CCR2 (STM32WL5_TIM2_BASE+STM32WL5_GTIM_CCR2_OFFSET) -#define STM32WL5_TIM2_CCR3 (STM32WL5_TIM2_BASE+STM32WL5_GTIM_CCR3_OFFSET) -#define STM32WL5_TIM2_CCR4 (STM32WL5_TIM2_BASE+STM32WL5_GTIM_CCR4_OFFSET) -#define STM32WL5_TIM2_DCR (STM32WL5_TIM2_BASE+STM32WL5_GTIM_DCR_OFFSET) -#define STM32WL5_TIM2_DMAR (STM32WL5_TIM2_BASE+STM32WL5_GTIM_DMAR_OFFSET) -#define STM32WL5_TIM2_OR (STM32WL5_TIM2_BASE+STM32WL5_GTIM_OR_OFFSET) - -#define STM32WL5_TIM16_CR1 (STM32WL5_TIM16_BASE+STM32WL5_GTIM_CR1_OFFSET) -#define STM32WL5_TIM16_CR2 (STM32WL5_TIM16_BASE+STM32WL5_GTIM_CR2_OFFSET) -#define STM32WL5_TIM16_DIER (STM32WL5_TIM16_BASE+STM32WL5_GTIM_DIER_OFFSET) -#define STM32WL5_TIM16_SR (STM32WL5_TIM16_BASE+STM32WL5_GTIM_SR_OFFSET) -#define STM32WL5_TIM16_EGR (STM32WL5_TIM16_BASE+STM32WL5_GTIM_EGR_OFFSET) -#define STM32WL5_TIM16_CCMR1 (STM32WL5_TIM16_BASE+STM32WL5_GTIM_CCMR1_OFFSET) -#define STM32WL5_TIM16_CCER (STM32WL5_TIM16_BASE+STM32WL5_GTIM_CCER_OFFSET) -#define STM32WL5_TIM16_CNT (STM32WL5_TIM16_BASE+STM32WL5_GTIM_CNT_OFFSET) -#define STM32WL5_TIM16_PSC (STM32WL5_TIM16_BASE+STM32WL5_GTIM_PSC_OFFSET) -#define STM32WL5_TIM16_ARR (STM32WL5_TIM16_BASE+STM32WL5_GTIM_ARR_OFFSET) -#define STM32WL5_TIM16_RCR (STM32WL5_TIM16_BASE+STM32WL5_GTIM_RCR_OFFSET) -#define STM32WL5_TIM16_CCR1 (STM32WL5_TIM16_BASE+STM32WL5_GTIM_CCR1_OFFSET) -#define STM32WL5_TIM16_BDTR (STM32WL5_TIM16_BASE+STM32WL5_GTIM_BDTR_OFFSET) -#define STM32WL5_TIM16_DCR (STM32WL5_TIM16_BASE+STM32WL5_GTIM_DCR_OFFSET) -#define STM32WL5_TIM16_DMAR (STM32WL5_TIM16_BASE+STM32WL5_GTIM_DMAR_OFFSET) -#define STM32WL5_TIM16_OR (STM32WL5_TIM16_BASE+STM32WL5_GTIM_OR_OFFSET) - -#define STM32WL5_TIM17_CR1 (STM32WL5_TIM17_BASE+STM32WL5_GTIM_CR1_OFFSET) -#define STM32WL5_TIM17_CR2 (STM32WL5_TIM17_BASE+STM32WL5_GTIM_CR2_OFFSET) -#define STM32WL5_TIM17_DIER (STM32WL5_TIM17_BASE+STM32WL5_GTIM_DIER_OFFSET) -#define STM32WL5_TIM17_SR (STM32WL5_TIM17_BASE+STM32WL5_GTIM_SR_OFFSET) -#define STM32WL5_TIM17_EGR (STM32WL5_TIM17_BASE+STM32WL5_GTIM_EGR_OFFSET) -#define STM32WL5_TIM17_CCMR1 (STM32WL5_TIM17_BASE+STM32WL5_GTIM_CCMR1_OFFSET) -#define STM32WL5_TIM17_CCER (STM32WL5_TIM17_BASE+STM32WL5_GTIM_CCER_OFFSET) -#define STM32WL5_TIM17_CNT (STM32WL5_TIM17_BASE+STM32WL5_GTIM_CNT_OFFSET) -#define STM32WL5_TIM17_PSC (STM32WL5_TIM17_BASE+STM32WL5_GTIM_PSC_OFFSET) -#define STM32WL5_TIM17_ARR (STM32WL5_TIM17_BASE+STM32WL5_GTIM_ARR_OFFSET) -#define STM32WL5_TIM17_RCR (STM32WL5_TIM17_BASE+STM32WL5_GTIM_RCR_OFFSET) -#define STM32WL5_TIM17_CCR1 (STM32WL5_TIM17_BASE+STM32WL5_GTIM_CCR1_OFFSET) -#define STM32WL5_TIM17_BDTR (STM32WL5_TIM17_BASE+STM32WL5_GTIM_BDTR_OFFSET) -#define STM32WL5_TIM17_DCR (STM32WL5_TIM17_BASE+STM32WL5_GTIM_DCR_OFFSET) -#define STM32WL5_TIM17_DMAR (STM32WL5_TIM17_BASE+STM32WL5_GTIM_DMAR_OFFSET) +#define STM32_TIM2_CR1 (STM32_TIM2_BASE+STM32_GTIM_CR1_OFFSET) +#define STM32_TIM2_CR2 (STM32_TIM2_BASE+STM32_GTIM_CR2_OFFSET) +#define STM32_TIM2_SMCR (STM32_TIM2_BASE+STM32_GTIM_SMCR_OFFSET) +#define STM32_TIM2_DIER (STM32_TIM2_BASE+STM32_GTIM_DIER_OFFSET) +#define STM32_TIM2_SR (STM32_TIM2_BASE+STM32_GTIM_SR_OFFSET) +#define STM32_TIM2_EGR (STM32_TIM2_BASE+STM32_GTIM_EGR_OFFSET) +#define STM32_TIM2_CCMR1 (STM32_TIM2_BASE+STM32_GTIM_CCMR1_OFFSET) +#define STM32_TIM2_CCMR2 (STM32_TIM2_BASE+STM32_GTIM_CCMR2_OFFSET) +#define STM32_TIM2_CCER (STM32_TIM2_BASE+STM32_GTIM_CCER_OFFSET) +#define STM32_TIM2_CNT (STM32_TIM2_BASE+STM32_GTIM_CNT_OFFSET) +#define STM32_TIM2_PSC (STM32_TIM2_BASE+STM32_GTIM_PSC_OFFSET) +#define STM32_TIM2_ARR (STM32_TIM2_BASE+STM32_GTIM_ARR_OFFSET) +#define STM32_TIM2_CCR1 (STM32_TIM2_BASE+STM32_GTIM_CCR1_OFFSET) +#define STM32_TIM2_CCR2 (STM32_TIM2_BASE+STM32_GTIM_CCR2_OFFSET) +#define STM32_TIM2_CCR3 (STM32_TIM2_BASE+STM32_GTIM_CCR3_OFFSET) +#define STM32_TIM2_CCR4 (STM32_TIM2_BASE+STM32_GTIM_CCR4_OFFSET) +#define STM32_TIM2_DCR (STM32_TIM2_BASE+STM32_GTIM_DCR_OFFSET) +#define STM32_TIM2_DMAR (STM32_TIM2_BASE+STM32_GTIM_DMAR_OFFSET) +#define STM32_TIM2_OR (STM32_TIM2_BASE+STM32_GTIM_OR_OFFSET) + +#define STM32_TIM16_CR1 (STM32_TIM16_BASE+STM32_GTIM_CR1_OFFSET) +#define STM32_TIM16_CR2 (STM32_TIM16_BASE+STM32_GTIM_CR2_OFFSET) +#define STM32_TIM16_DIER (STM32_TIM16_BASE+STM32_GTIM_DIER_OFFSET) +#define STM32_TIM16_SR (STM32_TIM16_BASE+STM32_GTIM_SR_OFFSET) +#define STM32_TIM16_EGR (STM32_TIM16_BASE+STM32_GTIM_EGR_OFFSET) +#define STM32_TIM16_CCMR1 (STM32_TIM16_BASE+STM32_GTIM_CCMR1_OFFSET) +#define STM32_TIM16_CCER (STM32_TIM16_BASE+STM32_GTIM_CCER_OFFSET) +#define STM32_TIM16_CNT (STM32_TIM16_BASE+STM32_GTIM_CNT_OFFSET) +#define STM32_TIM16_PSC (STM32_TIM16_BASE+STM32_GTIM_PSC_OFFSET) +#define STM32_TIM16_ARR (STM32_TIM16_BASE+STM32_GTIM_ARR_OFFSET) +#define STM32_TIM16_RCR (STM32_TIM16_BASE+STM32_GTIM_RCR_OFFSET) +#define STM32_TIM16_CCR1 (STM32_TIM16_BASE+STM32_GTIM_CCR1_OFFSET) +#define STM32_TIM16_BDTR (STM32_TIM16_BASE+STM32_GTIM_BDTR_OFFSET) +#define STM32_TIM16_DCR (STM32_TIM16_BASE+STM32_GTIM_DCR_OFFSET) +#define STM32_TIM16_DMAR (STM32_TIM16_BASE+STM32_GTIM_DMAR_OFFSET) +#define STM32_TIM16_OR (STM32_TIM16_BASE+STM32_GTIM_OR_OFFSET) + +#define STM32_TIM17_CR1 (STM32_TIM17_BASE+STM32_GTIM_CR1_OFFSET) +#define STM32_TIM17_CR2 (STM32_TIM17_BASE+STM32_GTIM_CR2_OFFSET) +#define STM32_TIM17_DIER (STM32_TIM17_BASE+STM32_GTIM_DIER_OFFSET) +#define STM32_TIM17_SR (STM32_TIM17_BASE+STM32_GTIM_SR_OFFSET) +#define STM32_TIM17_EGR (STM32_TIM17_BASE+STM32_GTIM_EGR_OFFSET) +#define STM32_TIM17_CCMR1 (STM32_TIM17_BASE+STM32_GTIM_CCMR1_OFFSET) +#define STM32_TIM17_CCER (STM32_TIM17_BASE+STM32_GTIM_CCER_OFFSET) +#define STM32_TIM17_CNT (STM32_TIM17_BASE+STM32_GTIM_CNT_OFFSET) +#define STM32_TIM17_PSC (STM32_TIM17_BASE+STM32_GTIM_PSC_OFFSET) +#define STM32_TIM17_ARR (STM32_TIM17_BASE+STM32_GTIM_ARR_OFFSET) +#define STM32_TIM17_RCR (STM32_TIM17_BASE+STM32_GTIM_RCR_OFFSET) +#define STM32_TIM17_CCR1 (STM32_TIM17_BASE+STM32_GTIM_CCR1_OFFSET) +#define STM32_TIM17_BDTR (STM32_TIM17_BASE+STM32_GTIM_BDTR_OFFSET) +#define STM32_TIM17_DCR (STM32_TIM17_BASE+STM32_GTIM_DCR_OFFSET) +#define STM32_TIM17_DMAR (STM32_TIM17_BASE+STM32_GTIM_DMAR_OFFSET) /* Register Bitfield Definitions ********************************************/ @@ -999,4 +999,4 @@ #define BTIM_EGR_UG (1 << 0) /* Bit 0: Update generation */ -#endif /* __ARCH_ARM_SRC_STM32WL5_HARDWARE_STM32WL5_TIM_H */ +#endif /* __ARCH_ARM_SRC_STM32WL5_HARDWARE_STM32_TIM_H */ diff --git a/arch/arm/src/stm32wl5/hardware/stm32wl5_uart.h b/arch/arm/src/stm32wl5/hardware/stm32wl5_uart.h index 5eb2450e7a34f..a98e638157028 100644 --- a/arch/arm/src/stm32wl5/hardware/stm32wl5_uart.h +++ b/arch/arm/src/stm32wl5/hardware/stm32wl5_uart.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32WL5_HARDWARE_STM32WL5_UART_H -#define __ARCH_ARM_SRC_STM32WL5_HARDWARE_STM32WL5_UART_H +#ifndef __ARCH_ARM_SRC_STM32WL5_HARDWARE_STM32_UART_H +#define __ARCH_ARM_SRC_STM32WL5_HARDWARE_STM32_UART_H /**************************************************************************** * Included Files @@ -37,57 +37,57 @@ /* Register Offsets *********************************************************/ -#define STM32WL5_USART_CR1_OFFSET 0x0000 /* Control register 1 */ -#define STM32WL5_USART_CR2_OFFSET 0x0004 /* Control register 2 */ -#define STM32WL5_USART_CR3_OFFSET 0x0008 /* Control register 3 */ -#define STM32WL5_USART_BRR_OFFSET 0x000c /* Baud Rate register */ -#define STM32WL5_USART_GTPR_OFFSET 0x0010 /* Guard time and prescaler register */ -#define STM32WL5_USART_RTOR_OFFSET 0x0014 /* Receiver timeout register */ -#define STM32WL5_USART_RQR_OFFSET 0x0018 /* Request register */ -#define STM32WL5_USART_ISR_OFFSET 0x001c /* Interrupt and status register */ -#define STM32WL5_USART_ICR_OFFSET 0x0020 /* Interrupt flag clear register */ -#define STM32WL5_USART_RDR_OFFSET 0x0024 /* Receive Data register */ -#define STM32WL5_USART_TDR_OFFSET 0x0028 /* Transmit Data register */ -#define STM32WL5_USART_PRESC_OFFSET 0x002c /* Prescaler */ +#define STM32_USART_CR1_OFFSET 0x0000 /* Control register 1 */ +#define STM32_USART_CR2_OFFSET 0x0004 /* Control register 2 */ +#define STM32_USART_CR3_OFFSET 0x0008 /* Control register 3 */ +#define STM32_USART_BRR_OFFSET 0x000c /* Baud Rate register */ +#define STM32_USART_GTPR_OFFSET 0x0010 /* Guard time and prescaler register */ +#define STM32_USART_RTOR_OFFSET 0x0014 /* Receiver timeout register */ +#define STM32_USART_RQR_OFFSET 0x0018 /* Request register */ +#define STM32_USART_ISR_OFFSET 0x001c /* Interrupt and status register */ +#define STM32_USART_ICR_OFFSET 0x0020 /* Interrupt flag clear register */ +#define STM32_USART_RDR_OFFSET 0x0024 /* Receive Data register */ +#define STM32_USART_TDR_OFFSET 0x0028 /* Transmit Data register */ +#define STM32_USART_PRESC_OFFSET 0x002c /* Prescaler */ /* Register Addresses *******************************************************/ -#define STM32WL5_USART1_CR1 (STM32WL5_USART1_BASE+STM32WL5_USART_CR1_OFFSET) -#define STM32WL5_USART1_CR2 (STM32WL5_USART1_BASE+STM32WL5_USART_CR2_OFFSET) -#define STM32WL5_USART1_CR3 (STM32WL5_USART1_BASE+STM32WL5_USART_CR3_OFFSET) -#define STM32WL5_USART1_BRR (STM32WL5_USART1_BASE+STM32WL5_USART_BRR_OFFSET) -#define STM32WL5_USART1_GTPR (STM32WL5_USART1_BASE+STM32WL5_USART_GTPR_OFFSET) -#define STM32WL5_USART1_RTOR (STM32WL5_USART1_BASE+STM32WL5_USART_RTOR_OFFSET) -#define STM32WL5_USART1_RQR (STM32WL5_USART1_BASE+STM32WL5_USART_RQR_OFFSET) -#define STM32WL5_USART1_ISR (STM32WL5_USART1_BASE+STM32WL5_USART_ISR_OFFSET) -#define STM32WL5_USART1_ICR (STM32WL5_USART1_BASE+STM32WL5_USART_ICR_OFFSET) -#define STM32WL5_USART1_RDR (STM32WL5_USART1_BASE+STM32WL5_USART_RDR_OFFSET) -#define STM32WL5_USART1_TDR (STM32WL5_USART1_BASE+STM32WL5_USART_TDR_OFFSET) -#define STM32WL5_USART1_PRESC (STM32WL5_USART1_BASE+STM32WL5_USART_PRESC_OFFSET) - -#define STM32WL5_USART2_CR1 (STM32WL5_USART2_BASE+STM32WL5_USART_CR1_OFFSET) -#define STM32WL5_USART2_CR2 (STM32WL5_USART2_BASE+STM32WL5_USART_CR2_OFFSET) -#define STM32WL5_USART2_CR3 (STM32WL5_USART2_BASE+STM32WL5_USART_CR3_OFFSET) -#define STM32WL5_USART2_BRR (STM32WL5_USART2_BASE+STM32WL5_USART_BRR_OFFSET) -#define STM32WL5_USART2_GTPR (STM32WL5_USART2_BASE+STM32WL5_USART_GTPR_OFFSET) -#define STM32WL5_USART2_RTOR (STM32WL5_USART2_BASE+STM32WL5_USART_RTOR_OFFSET) -#define STM32WL5_USART2_RQR (STM32WL5_USART2_BASE+STM32WL5_USART_RQR_OFFSET) -#define STM32WL5_USART2_ISR (STM32WL5_USART2_BASE+STM32WL5_USART_ISR_OFFSET) -#define STM32WL5_USART2_ICR (STM32WL5_USART2_BASE+STM32WL5_USART_ICR_OFFSET) -#define STM32WL5_USART2_RDR (STM32WL5_USART2_BASE+STM32WL5_USART_RDR_OFFSET) -#define STM32WL5_USART2_TDR (STM32WL5_USART2_BASE+STM32WL5_USART_TDR_OFFSET) -#define STM32WL5_USART2_PRESC (STM32WL5_USART2_BASE+STM32WL5_USART_PRESC_OFFSET) - -#define STM32WL5_LPUART1_CR1 (STM32WL5_LPUART1_BASE+STM32WL5_USART_CR1_OFFSET) -#define STM32WL5_LPUART1_CR2 (STM32WL5_LPUART1_BASE+STM32WL5_USART_CR2_OFFSET) -#define STM32WL5_LPUART1_CR3 (STM32WL5_LPUART1_BASE+STM32WL5_USART_CR3_OFFSET) -#define STM32WL5_LPUART1_BRR (STM32WL5_LPUART1_BASE+STM32WL5_USART_BRR_OFFSET) -#define STM32WL5_LPUART1_RQR (STM32WL5_LPUART1_BASE+STM32WL5_USART_RQR_OFFSET) -#define STM32WL5_LPUART1_ISR (STM32WL5_LPUART1_BASE+STM32WL5_USART_ISR_OFFSET) -#define STM32WL5_LPUART1_ICR (STM32WL5_LPUART1_BASE+STM32WL5_USART_ICR_OFFSET) -#define STM32WL5_LPUART1_RDR (STM32WL5_LPUART1_BASE+STM32WL5_USART_RDR_OFFSET) -#define STM32WL5_LPUART1_TDR (STM32WL5_LPUART1_BASE+STM32WL5_USART_TDR_OFFSET) -#define STM32WL5_LPUART1_PRESC (STM32WL5_LPUART1_BASE+STM32WL5_USART_PRESC_OFFSET) +#define STM32_USART1_CR1 (STM32_USART1_BASE+STM32_USART_CR1_OFFSET) +#define STM32_USART1_CR2 (STM32_USART1_BASE+STM32_USART_CR2_OFFSET) +#define STM32_USART1_CR3 (STM32_USART1_BASE+STM32_USART_CR3_OFFSET) +#define STM32_USART1_BRR (STM32_USART1_BASE+STM32_USART_BRR_OFFSET) +#define STM32_USART1_GTPR (STM32_USART1_BASE+STM32_USART_GTPR_OFFSET) +#define STM32_USART1_RTOR (STM32_USART1_BASE+STM32_USART_RTOR_OFFSET) +#define STM32_USART1_RQR (STM32_USART1_BASE+STM32_USART_RQR_OFFSET) +#define STM32_USART1_ISR (STM32_USART1_BASE+STM32_USART_ISR_OFFSET) +#define STM32_USART1_ICR (STM32_USART1_BASE+STM32_USART_ICR_OFFSET) +#define STM32_USART1_RDR (STM32_USART1_BASE+STM32_USART_RDR_OFFSET) +#define STM32_USART1_TDR (STM32_USART1_BASE+STM32_USART_TDR_OFFSET) +#define STM32_USART1_PRESC (STM32_USART1_BASE+STM32_USART_PRESC_OFFSET) + +#define STM32_USART2_CR1 (STM32_USART2_BASE+STM32_USART_CR1_OFFSET) +#define STM32_USART2_CR2 (STM32_USART2_BASE+STM32_USART_CR2_OFFSET) +#define STM32_USART2_CR3 (STM32_USART2_BASE+STM32_USART_CR3_OFFSET) +#define STM32_USART2_BRR (STM32_USART2_BASE+STM32_USART_BRR_OFFSET) +#define STM32_USART2_GTPR (STM32_USART2_BASE+STM32_USART_GTPR_OFFSET) +#define STM32_USART2_RTOR (STM32_USART2_BASE+STM32_USART_RTOR_OFFSET) +#define STM32_USART2_RQR (STM32_USART2_BASE+STM32_USART_RQR_OFFSET) +#define STM32_USART2_ISR (STM32_USART2_BASE+STM32_USART_ISR_OFFSET) +#define STM32_USART2_ICR (STM32_USART2_BASE+STM32_USART_ICR_OFFSET) +#define STM32_USART2_RDR (STM32_USART2_BASE+STM32_USART_RDR_OFFSET) +#define STM32_USART2_TDR (STM32_USART2_BASE+STM32_USART_TDR_OFFSET) +#define STM32_USART2_PRESC (STM32_USART2_BASE+STM32_USART_PRESC_OFFSET) + +#define STM32_LPUART1_CR1 (STM32_LPUART1_BASE+STM32_USART_CR1_OFFSET) +#define STM32_LPUART1_CR2 (STM32_LPUART1_BASE+STM32_USART_CR2_OFFSET) +#define STM32_LPUART1_CR3 (STM32_LPUART1_BASE+STM32_USART_CR3_OFFSET) +#define STM32_LPUART1_BRR (STM32_LPUART1_BASE+STM32_USART_BRR_OFFSET) +#define STM32_LPUART1_RQR (STM32_LPUART1_BASE+STM32_USART_RQR_OFFSET) +#define STM32_LPUART1_ISR (STM32_LPUART1_BASE+STM32_USART_ISR_OFFSET) +#define STM32_LPUART1_ICR (STM32_LPUART1_BASE+STM32_USART_ICR_OFFSET) +#define STM32_LPUART1_RDR (STM32_LPUART1_BASE+STM32_USART_RDR_OFFSET) +#define STM32_LPUART1_TDR (STM32_LPUART1_BASE+STM32_USART_TDR_OFFSET) +#define STM32_LPUART1_PRESC (STM32_LPUART1_BASE+STM32_USART_PRESC_OFFSET) /* Register Bitfield Definitions ********************************************/ @@ -330,4 +330,4 @@ * Public Functions Prototypes ****************************************************************************/ -#endif /* __ARCH_ARM_SRC_STM32WL5_HARDWARE_STM32WL5_UART_H */ +#endif /* __ARCH_ARM_SRC_STM32WL5_HARDWARE_STM32_UART_H */ diff --git a/arch/arm/src/stm32wl5/stm32.h b/arch/arm/src/stm32wl5/stm32.h new file mode 100644 index 0000000000000..3fe581bc7f3d3 --- /dev/null +++ b/arch/arm/src/stm32wl5/stm32.h @@ -0,0 +1,67 @@ +/**************************************************************************** + * arch/arm/src/stm32wl5/stm32.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32WL5_STM32_H +#define __ARCH_ARM_SRC_STM32WL5_STM32_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include +#include + +#include "arm_internal.h" + +/* Peripherals **************************************************************/ + +#include "chip.h" +#include "stm32wl5_flash.h" +#include "stm32wl5_gpio.h" +#include "stm32wl5_lowputc.h" +#include "stm32wl5_pwr.h" +#include "stm32wl5_rcc.h" +#include "stm32wl5_spi.h" +#include "stm32wl5_tim.h" +#include "stm32wl5_uart.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_spidev_initialize + * + * Description: + * Called to configure SPI chip select GPIO pins. + * + ****************************************************************************/ + +void stm32_spidev_initialize(void); + +#endif /* __ARCH_ARM_SRC_STM32WL5_STM32_H */ diff --git a/arch/arm/src/stm32wl5/stm32wl5.h b/arch/arm/src/stm32wl5/stm32wl5.h deleted file mode 100644 index 5b7eb4404301f..0000000000000 --- a/arch/arm/src/stm32wl5/stm32wl5.h +++ /dev/null @@ -1,67 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32wl5/stm32wl5.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32WL5_STM32WL5_H -#define __ARCH_ARM_SRC_STM32WL5_STM32WL5_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include -#include -#include - -#include "arm_internal.h" - -/* Peripherals **************************************************************/ - -#include "chip.h" -#include "stm32wl5_flash.h" -#include "stm32wl5_gpio.h" -#include "stm32wl5_lowputc.h" -#include "stm32wl5_pwr.h" -#include "stm32wl5_rcc.h" -#include "stm32wl5_spi.h" -#include "stm32wl5_tim.h" -#include "stm32wl5_uart.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32wl5_spidev_initialize - * - * Description: - * Called to configure SPI chip select GPIO pins. - * - ****************************************************************************/ - -void stm32wl5_spidev_initialize(void); - -#endif /* __ARCH_ARM_SRC_STM32WL5_STM32WL5_H */ diff --git a/arch/arm/src/stm32wl5/stm32wl5_allocateheap.c b/arch/arm/src/stm32wl5/stm32wl5_allocateheap.c index 61e9a51df81f7..29422cc4b0bd3 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_allocateheap.c +++ b/arch/arm/src/stm32wl5/stm32wl5_allocateheap.c @@ -66,28 +66,28 @@ /* Set the range of system SRAM */ -#define SRAM1_START STM32WL5_SRAM_BASE -#define SRAM1_END (SRAM1_START + STM32WL5_SRAM1_SIZE) +#define SRAM1_START STM32_SRAM_BASE +#define SRAM1_END (SRAM1_START + STM32_SRAM1_SIZE) /* Set the range of SRAM2 as well, requires a second memory region */ #ifdef CONFIG_IPCC # define SRAM2_START IPCC_END #else -# define SRAM2_START STM32WL5_SRAM2_BASE +# define SRAM2_START STM32_SRAM2_BASE #endif -#define SRAM2_END (SRAM2_START + STM32WL5_SRAM2_SIZE) +#define SRAM2_END (SRAM2_START + STM32_SRAM2_SIZE) /* Some sanity checking. If multiple memory regions are defined, verify * that CONFIG_MM_REGIONS is set to match the number of memory regions * that we have been asked to add to the heap. */ -#if CONFIG_MM_REGIONS < defined(CONFIG_STM32WL5_SRAM2_HEAP) + 1 +#if CONFIG_MM_REGIONS < defined(CONFIG_STM32_SRAM2_HEAP) + 1 # error "You need more memory manager regions to support selected heap components" #endif -#if CONFIG_MM_REGIONS > defined(CONFIG_STM32WL5_SRAM2_HEAP) + 1 +#if CONFIG_MM_REGIONS > defined(CONFIG_STM32_SRAM2_HEAP) + 1 # warning "CONFIG_MM_REGIONS large enough but I do not know what some of the region(s) are" #endif @@ -192,7 +192,7 @@ void up_allocate_heap(void **heap_start, size_t *heap_size) /* Allow user-mode access to the user heap memory */ - stm32wl5_mpu_uheap((uintptr_t)ubase, usize); + stm32_mpu_uheap((uintptr_t)ubase, usize); #else /* Return the heap settings */ @@ -264,13 +264,13 @@ void up_allocate_kheap(void **heap_start, size_t *heap_size) #if CONFIG_MM_REGIONS > 1 void arm_addregion(void) { -#ifdef CONFIG_STM32WL5_SRAM2_HEAP +#ifdef CONFIG_STM32_SRAM2_HEAP #if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP) /* Allow user-mode access to the SRAM2 heap */ - stm32wl5_mpu_uheap((uintptr_t)SRAM2_START, SRAM2_END - SRAM2_START); + stm32_mpu_uheap((uintptr_t)SRAM2_START, SRAM2_END - SRAM2_START); #endif /* Colorize the heap for debug */ diff --git a/arch/arm/src/stm32wl5/stm32wl5_exti.h b/arch/arm/src/stm32wl5/stm32wl5_exti.h index 9535111414edb..1ea988fbaf38e 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_exti.h +++ b/arch/arm/src/stm32wl5/stm32wl5_exti.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32WL5_STM32WL5_EXTI_H -#define __ARCH_ARM_SRC_STM32WL5_STM32WL5_EXTI_H +#ifndef __ARCH_ARM_SRC_STM32WL5_STM32_EXTI_H +#define __ARCH_ARM_SRC_STM32WL5_STM32_EXTI_H /**************************************************************************** * Included Files @@ -54,7 +54,7 @@ extern "C" ****************************************************************************/ /**************************************************************************** - * Name: stm32wl5_gpiosetevent + * Name: stm32_gpiosetevent * * Description: * Sets/clears GPIO based event and interrupt triggers. @@ -73,11 +73,11 @@ extern "C" * ****************************************************************************/ -int stm32wl5_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, +int stm32_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, bool event, xcpt_t func, void *arg); /**************************************************************************** - * Name: stm32wl5_exti_alarm + * Name: stm32_exti_alarm * * Description: * Sets/clears EXTI alarm interrupt. @@ -95,12 +95,12 @@ int stm32wl5_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, ****************************************************************************/ #ifdef CONFIG_RTC_ALARM -int stm32wl5_exti_alarm(bool risingedge, bool fallingedge, bool event, +int stm32_exti_alarm(bool risingedge, bool fallingedge, bool event, xcpt_t func, void *arg); #endif /**************************************************************************** - * Name: stm32wl5_exti_wakeup + * Name: stm32_exti_wakeup * * Description: * Sets/clears EXTI wakeup interrupt. @@ -118,12 +118,12 @@ int stm32wl5_exti_alarm(bool risingedge, bool fallingedge, bool event, ****************************************************************************/ #ifdef CONFIG_RTC_PERIODIC -int stm32wl5_exti_wakeup(bool risingedge, bool fallingedge, bool event, +int stm32_exti_wakeup(bool risingedge, bool fallingedge, bool event, xcpt_t func, void *arg); #endif /**************************************************************************** - * Name: stm32wl5_exti_comp + * Name: stm32_exti_comp * * Description: * Sets/clears comparator based events and interrupt triggers. @@ -141,8 +141,8 @@ int stm32wl5_exti_wakeup(bool risingedge, bool fallingedge, bool event, * ****************************************************************************/ -#ifdef CONFIG_STM32WL5_COMP -int stm32wl5_exti_comp(int cmp, bool risingedge, bool fallingedge, +#ifdef CONFIG_STM32_COMP +int stm32_exti_comp(int cmp, bool risingedge, bool fallingedge, bool event, xcpt_t func, void *arg); #endif @@ -152,4 +152,4 @@ int stm32wl5_exti_comp(int cmp, bool risingedge, bool fallingedge, #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32WL5_STM32WL5_EXTI_H */ +#endif /* __ARCH_ARM_SRC_STM32WL5_STM32_EXTI_H */ diff --git a/arch/arm/src/stm32wl5/stm32wl5_exti_gpio.c b/arch/arm/src/stm32wl5/stm32wl5_exti_gpio.c index 6d6318f023832..eec0c58a667c0 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_exti_gpio.c +++ b/arch/arm/src/stm32wl5/stm32wl5_exti_gpio.c @@ -66,13 +66,13 @@ static struct gpio_callback_s g_gpio_handlers[16]; * Interrupt Service Routines - Dispatchers ****************************************************************************/ -static int stm32wl5_exti0_isr(int irq, void *context, void *arg) +static int stm32_exti0_isr(int irq, void *context, void *arg) { int ret = OK; /* Clear the pending interrupt */ - putreg32(0x0001, STM32WL5_EXTI_PR1); + putreg32(0x0001, STM32_EXTI_PR1); /* And dispatch the interrupt to the handler */ @@ -87,13 +87,13 @@ static int stm32wl5_exti0_isr(int irq, void *context, void *arg) return ret; } -static int stm32wl5_exti1_isr(int irq, void *context, void *arg) +static int stm32_exti1_isr(int irq, void *context, void *arg) { int ret = OK; /* Clear the pending interrupt */ - putreg32(0x0002, STM32WL5_EXTI_PR1); + putreg32(0x0002, STM32_EXTI_PR1); /* And dispatch the interrupt to the handler */ @@ -108,13 +108,13 @@ static int stm32wl5_exti1_isr(int irq, void *context, void *arg) return ret; } -static int stm32wl5_exti2_isr(int irq, void *context, void *arg) +static int stm32_exti2_isr(int irq, void *context, void *arg) { int ret = OK; /* Clear the pending interrupt */ - putreg32(0x0004, STM32WL5_EXTI_PR1); + putreg32(0x0004, STM32_EXTI_PR1); /* And dispatch the interrupt to the handler */ @@ -129,13 +129,13 @@ static int stm32wl5_exti2_isr(int irq, void *context, void *arg) return ret; } -static int stm32wl5_exti3_isr(int irq, void *context, void *arg) +static int stm32_exti3_isr(int irq, void *context, void *arg) { int ret = OK; /* Clear the pending interrupt */ - putreg32(0x0008, STM32WL5_EXTI_PR1); + putreg32(0x0008, STM32_EXTI_PR1); /* And dispatch the interrupt to the handler */ @@ -150,13 +150,13 @@ static int stm32wl5_exti3_isr(int irq, void *context, void *arg) return ret; } -static int stm32wl5_exti4_isr(int irq, void *context, void *arg) +static int stm32_exti4_isr(int irq, void *context, void *arg) { int ret = OK; /* Clear the pending interrupt */ - putreg32(0x0010, STM32WL5_EXTI_PR1); + putreg32(0x0010, STM32_EXTI_PR1); /* And dispatch the interrupt to the handler */ @@ -171,7 +171,7 @@ static int stm32wl5_exti4_isr(int irq, void *context, void *arg) return ret; } -static int stm32wl5_exti_multiisr(int irq, void *context, void *arg, +static int stm32_exti_multiisr(int irq, void *context, void *arg, int first, int last) { uint32_t pr; @@ -180,7 +180,7 @@ static int stm32wl5_exti_multiisr(int irq, void *context, void *arg, /* Examine the state of each pin in the group */ - pr = getreg32(STM32WL5_EXTI_PR1); + pr = getreg32(STM32_EXTI_PR1); /* And dispatch the interrupt to the handler */ @@ -193,7 +193,7 @@ static int stm32wl5_exti_multiisr(int irq, void *context, void *arg, { /* Clear the pending interrupt */ - putreg32(mask, STM32WL5_EXTI_PR1); + putreg32(mask, STM32_EXTI_PR1); /* And dispatch the interrupt to the handler */ @@ -215,14 +215,14 @@ static int stm32wl5_exti_multiisr(int irq, void *context, void *arg, return ret; } -static int stm32wl5_exti95_isr(int irq, void *context, void *arg) +static int stm32_exti95_isr(int irq, void *context, void *arg) { - return stm32wl5_exti_multiisr(irq, context, arg, 5, 9); + return stm32_exti_multiisr(irq, context, arg, 5, 9); } -static int stm32wl5_exti1510_isr(int irq, void *context, void *arg) +static int stm32_exti1510_isr(int irq, void *context, void *arg) { - return stm32wl5_exti_multiisr(irq, context, arg, 10, 15); + return stm32_exti_multiisr(irq, context, arg, 10, 15); } /**************************************************************************** @@ -230,7 +230,7 @@ static int stm32wl5_exti1510_isr(int irq, void *context, void *arg) ****************************************************************************/ /**************************************************************************** - * Name: stm32wl5_gpiosetevent + * Name: stm32_gpiosetevent * * Description: * Sets/clears GPIO based event and interrupt triggers. @@ -252,7 +252,7 @@ static int stm32wl5_exti1510_isr(int irq, void *context, void *arg) * ****************************************************************************/ -int stm32wl5_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, +int stm32_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, bool event, xcpt_t func, void *arg) { struct gpio_callback_s *shared_cbs; @@ -267,43 +267,43 @@ int stm32wl5_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, if (pin < 5) { - irq = pin + STM32WL5_IRQ_EXTI0; + irq = pin + STM32_IRQ_EXTI0; nshared = 1; shared_cbs = &g_gpio_handlers[pin]; switch (pin) { case 0: - handler = stm32wl5_exti0_isr; + handler = stm32_exti0_isr; break; case 1: - handler = stm32wl5_exti1_isr; + handler = stm32_exti1_isr; break; case 2: - handler = stm32wl5_exti2_isr; + handler = stm32_exti2_isr; break; case 3: - handler = stm32wl5_exti3_isr; + handler = stm32_exti3_isr; break; default: - handler = stm32wl5_exti4_isr; + handler = stm32_exti4_isr; break; } } else if (pin < 10) { - irq = STM32WL5_IRQ_EXTI95; - handler = stm32wl5_exti95_isr; + irq = STM32_IRQ_EXTI95; + handler = stm32_exti95_isr; shared_cbs = &g_gpio_handlers[5]; nshared = 5; } else { - irq = STM32WL5_IRQ_EXTI1510; - handler = stm32wl5_exti1510_isr; + irq = STM32_IRQ_EXTI1510; + handler = stm32_exti1510_isr; shared_cbs = &g_gpio_handlers[10]; nshared = 6; } @@ -349,23 +349,23 @@ int stm32wl5_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, pinset |= GPIO_EXTI; } - stm32wl5_configgpio(pinset); + stm32_configgpio(pinset); /* Configure rising/falling edges */ - modifyreg32(STM32WL5_EXTI_RTSR1, + modifyreg32(STM32_EXTI_RTSR1, risingedge ? 0 : exti, risingedge ? exti : 0); - modifyreg32(STM32WL5_EXTI_FTSR1, + modifyreg32(STM32_EXTI_FTSR1, fallingedge ? 0 : exti, fallingedge ? exti : 0); /* Enable Events and Interrupts */ - modifyreg32(STM32WL5_EXTI_C1EMR1, + modifyreg32(STM32_EXTI_C1EMR1, event ? 0 : exti, event ? exti : 0); - modifyreg32(STM32WL5_EXTI_C1IMR1, + modifyreg32(STM32_EXTI_C1IMR1, func ? 0 : exti, func ? exti : 0); diff --git a/arch/arm/src/stm32wl5/stm32wl5_flash.c b/arch/arm/src/stm32wl5/stm32wl5_flash.c index 054ca10b3ae1d..4c251c982dca4 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_flash.c +++ b/arch/arm/src/stm32wl5/stm32wl5_flash.c @@ -46,11 +46,11 @@ #include #include "stm32wl5_rcc.h" -#include "stm32wl5_waste.h" +#include "stm32_waste.h" #include "stm32wl5_flash.h" #include "arm_internal.h" -#if !defined(CONFIG_STM32WL5_FLASH_OVERRIDE_DEFAULT) +#if !defined(CONFIG_STM32_FLASH_OVERRIDE_DEFAULT) # warning "Flash Configuration has been overridden - make sure it is correct" #endif @@ -65,7 +65,7 @@ #define OPTBYTES_KEY1 0x08192A3B #define OPTBYTES_KEY2 0x4C5D6E7F -#define FLASH_PAGE_SIZE STM32WL5_FLASH_PAGESIZE +#define FLASH_PAGE_SIZE STM32_FLASH_PAGESIZE #define FLASH_PAGE_WORDS (FLASH_PAGE_SIZE / 4) #define FLASH_PAGE_MASK (FLASH_PAGE_SIZE - 1) #define FLASH_PAGE_SHIFT (11) /* 2**11 = 2048B */ @@ -93,35 +93,35 @@ static uint32_t g_page_buffer[FLASH_PAGE_WORDS]; static void flash_unlock(void) { - while (getreg32(STM32WL5_FLASH_SR) & FLASH_SR_BSY) + while (getreg32(STM32_FLASH_SR) & FLASH_SR_BSY) { - stm32wl5_waste(); + stm32_waste(); } - if (getreg32(STM32WL5_FLASH_CR) & FLASH_CR_LOCK) + if (getreg32(STM32_FLASH_CR) & FLASH_CR_LOCK) { /* Unlock sequence */ - putreg32(FLASH_KEY1, STM32WL5_FLASH_KEYR); - putreg32(FLASH_KEY2, STM32WL5_FLASH_KEYR); + putreg32(FLASH_KEY1, STM32_FLASH_KEYR); + putreg32(FLASH_KEY2, STM32_FLASH_KEYR); } } static void flash_lock(void) { - modifyreg32(STM32WL5_FLASH_CR, 0, FLASH_CR_LOCK); + modifyreg32(STM32_FLASH_CR, 0, FLASH_CR_LOCK); } static void flash_optbytes_unlock(void) { flash_unlock(); - if (getreg32(STM32WL5_FLASH_CR) & FLASH_CR_OPTLOCK) + if (getreg32(STM32_FLASH_CR) & FLASH_CR_OPTLOCK) { /* Unlock Option Bytes sequence */ - putreg32(OPTBYTES_KEY1, STM32WL5_FLASH_OPTKEYR); - putreg32(OPTBYTES_KEY2, STM32WL5_FLASH_OPTKEYR); + putreg32(OPTBYTES_KEY1, STM32_FLASH_OPTKEYR); + putreg32(OPTBYTES_KEY2, STM32_FLASH_OPTKEYR); } } @@ -138,24 +138,24 @@ static inline void flash_erase(size_t page) { finfo("erase page %u\n", (unsigned int)page); - modifyreg32(STM32WL5_FLASH_CR, 0, FLASH_CR_PAGE_ERASE); - modifyreg32(STM32WL5_FLASH_CR, FLASH_CR_PNB_MASK, + modifyreg32(STM32_FLASH_CR, 0, FLASH_CR_PAGE_ERASE); + modifyreg32(STM32_FLASH_CR, FLASH_CR_PNB_MASK, FLASH_CR_PNB(page & 0xff)); - modifyreg32(STM32WL5_FLASH_CR, 0, FLASH_CR_START); + modifyreg32(STM32_FLASH_CR, 0, FLASH_CR_START); - while (getreg32(STM32WL5_FLASH_SR) & FLASH_SR_BSY) + while (getreg32(STM32_FLASH_SR) & FLASH_SR_BSY) { - stm32wl5_waste(); + stm32_waste(); } - modifyreg32(STM32WL5_FLASH_CR, FLASH_CR_PAGE_ERASE, 0); + modifyreg32(STM32_FLASH_CR, FLASH_CR_PAGE_ERASE, 0); } /**************************************************************************** * Public Functions ****************************************************************************/ -int stm32wl5_flash_unlock(void) +int stm32_flash_unlock(void) { int ret; @@ -171,7 +171,7 @@ int stm32wl5_flash_unlock(void) return ret; } -int stm32wl5_flash_lock(void) +int stm32_flash_lock(void) { int ret; @@ -188,7 +188,7 @@ int stm32wl5_flash_lock(void) } /**************************************************************************** - * Name: stm32wl5_flash_user_optbytes + * Name: stm32_flash_user_optbytes * * Description: * Modify the contents of the user option bytes (USR OPT) on the flash. @@ -204,7 +204,7 @@ int stm32wl5_flash_lock(void) * ****************************************************************************/ -uint32_t stm32wl5_flash_user_optbytes(uint32_t clrbits, uint32_t setbits) +uint32_t stm32_flash_user_optbytes(uint32_t clrbits, uint32_t setbits) { uint32_t regval; int ret; @@ -227,22 +227,22 @@ uint32_t stm32wl5_flash_user_optbytes(uint32_t clrbits, uint32_t setbits) /* Modify Option Bytes in register. */ - regval = getreg32(STM32WL5_FLASH_OPTR); + regval = getreg32(STM32_FLASH_OPTR); finfo("Flash option bytes before: 0x%" PRIx32 "\n", regval); regval = (regval & ~clrbits) | setbits; - putreg32(regval, STM32WL5_FLASH_OPTR); + putreg32(regval, STM32_FLASH_OPTR); finfo("Flash option bytes after: 0x%" PRIx32 "\n", regval); /* Start Option Bytes programming and wait for completion. */ - modifyreg32(STM32WL5_FLASH_CR, 0, FLASH_CR_OPTSTRT); + modifyreg32(STM32_FLASH_CR, 0, FLASH_CR_OPTSTRT); - while (getreg32(STM32WL5_FLASH_SR) & FLASH_SR_BSY) + while (getreg32(STM32_FLASH_SR) & FLASH_SR_BSY) { - stm32wl5_waste(); + stm32_waste(); } flash_optbytes_lock(); @@ -253,42 +253,42 @@ uint32_t stm32wl5_flash_user_optbytes(uint32_t clrbits, uint32_t setbits) size_t up_progmem_pagesize(size_t page) { - return STM32WL5_FLASH_PAGESIZE; + return STM32_FLASH_PAGESIZE; } size_t up_progmem_erasesize(size_t block) { - return STM32WL5_FLASH_PAGESIZE; + return STM32_FLASH_PAGESIZE; } ssize_t up_progmem_getpage(size_t addr) { - if (addr >= STM32WL5_FLASH_BASE) + if (addr >= STM32_FLASH_BASE) { - addr -= STM32WL5_FLASH_BASE; + addr -= STM32_FLASH_BASE; } - if (addr >= STM32WL5_FLASH_SIZE) + if (addr >= STM32_FLASH_SIZE) { return -EFAULT; } - return addr / STM32WL5_FLASH_PAGESIZE; + return addr / STM32_FLASH_PAGESIZE; } size_t up_progmem_getaddress(size_t page) { - if (page >= STM32WL5_FLASH_NPAGES) + if (page >= STM32_FLASH_NPAGES) { return SIZE_MAX; } - return page * STM32WL5_FLASH_PAGESIZE + STM32WL5_FLASH_BASE; + return page * STM32_FLASH_PAGESIZE + STM32_FLASH_BASE; } size_t up_progmem_neraseblocks(void) { - return STM32WL5_FLASH_NPAGES; + return STM32_FLASH_NPAGES; } bool up_progmem_isuniform(void) @@ -300,7 +300,7 @@ ssize_t up_progmem_eraseblock(size_t block) { int ret; - if (block >= STM32WL5_FLASH_NPAGES) + if (block >= STM32_FLASH_NPAGES) { return -EFAULT; } @@ -338,7 +338,7 @@ ssize_t up_progmem_ispageerased(size_t page) size_t count; size_t bwritten = 0; - if (page >= STM32WL5_FLASH_NPAGES) + if (page >= STM32_FLASH_NPAGES) { return -EFAULT; } @@ -372,12 +372,12 @@ ssize_t up_progmem_write(size_t addr, const void *buf, size_t buflen) /* Check for valid address range. */ offset = addr; - if (addr >= STM32WL5_FLASH_BASE) + if (addr >= STM32_FLASH_BASE) { - offset -= STM32WL5_FLASH_BASE; + offset -= STM32_FLASH_BASE; } - if (offset + buflen > STM32WL5_FLASH_SIZE) + if (offset + buflen > STM32_FLASH_SIZE) { return -EFAULT; } @@ -447,7 +447,7 @@ ssize_t up_progmem_write(size_t addr, const void *buf, size_t buflen) /* Write the page. Must be with double-words. */ - modifyreg32(STM32WL5_FLASH_CR, 0, FLASH_CR_PG); + modifyreg32(STM32_FLASH_CR, 0, FLASH_CR_PG); set_pg_bit = true; for (i = 0; i < FLASH_PAGE_WORDS; i += 2) @@ -455,14 +455,14 @@ ssize_t up_progmem_write(size_t addr, const void *buf, size_t buflen) *dest++ = *src++; *dest++ = *src++; - while (getreg32(STM32WL5_FLASH_SR) & FLASH_SR_BSY) + while (getreg32(STM32_FLASH_SR) & FLASH_SR_BSY) { - stm32wl5_waste(); + stm32_waste(); } /* Verify */ - if (getreg32(STM32WL5_FLASH_SR) & FLASH_SR_WRITE_PROTECTION_ERROR) + if (getreg32(STM32_FLASH_SR) & FLASH_SR_WRITE_PROTECTION_ERROR) { ret = -EROFS; goto out; @@ -476,7 +476,7 @@ ssize_t up_progmem_write(size_t addr, const void *buf, size_t buflen) } } - modifyreg32(STM32WL5_FLASH_CR, FLASH_CR_PG, 0); + modifyreg32(STM32_FLASH_CR, FLASH_CR_PG, 0); set_pg_bit = false; /* Adjust pointers and counts for the next time through the loop */ @@ -492,7 +492,7 @@ ssize_t up_progmem_write(size_t addr, const void *buf, size_t buflen) out: if (set_pg_bit) { - modifyreg32(STM32WL5_FLASH_CR, FLASH_CR_PG, 0); + modifyreg32(STM32_FLASH_CR, FLASH_CR_PG, 0); } /* If there was an error, clear all error flags in status register (rc_w1 @@ -502,9 +502,9 @@ ssize_t up_progmem_write(size_t addr, const void *buf, size_t buflen) if (ret != OK) { ferr("flash write error: %d, status: 0x%" PRIx32 "\n", - ret, getreg32(STM32WL5_FLASH_SR)); + ret, getreg32(STM32_FLASH_SR)); - modifyreg32(STM32WL5_FLASH_SR, 0, FLASH_SR_ALLERRS); + modifyreg32(STM32_FLASH_SR, 0, FLASH_SR_ALLERRS); } flash_lock(); diff --git a/arch/arm/src/stm32wl5/stm32wl5_flash.h b/arch/arm/src/stm32wl5/stm32wl5_flash.h index 87f0abbdeb3e6..063b45e36ab7d 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_flash.h +++ b/arch/arm/src/stm32wl5/stm32wl5_flash.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32WL5_STM32WL5_FLASH_H -#define __ARCH_ARM_SRC_STM32WL5_STM32WL5_FLASH_H +#ifndef __ARCH_ARM_SRC_STM32WL5_STM32_FLASH_H +#define __ARCH_ARM_SRC_STM32WL5_STM32_FLASH_H /**************************************************************************** * Included Files @@ -36,11 +36,11 @@ * Public Functions Prototypes ****************************************************************************/ -int stm32wl5_flash_lock(void); -int stm32wl5_flash_unlock(void); +int stm32_flash_lock(void); +int stm32_flash_unlock(void); /**************************************************************************** - * Name: stm32wl5_flash_user_optbytes + * Name: stm32_flash_user_optbytes * * Description: * Modify the contents of the user option bytes (USR OPT) on the flash. @@ -56,6 +56,6 @@ int stm32wl5_flash_unlock(void); * ****************************************************************************/ -uint32_t stm32wl5_flash_user_optbytes(uint32_t clrbits, uint32_t setbits); +uint32_t stm32_flash_user_optbytes(uint32_t clrbits, uint32_t setbits); -#endif /* __ARCH_ARM_SRC_STM32WL5_STM32WL5_FLASH_H */ +#endif /* __ARCH_ARM_SRC_STM32WL5_STM32_FLASH_H */ diff --git a/arch/arm/src/stm32wl5/stm32wl5_gpio.c b/arch/arm/src/stm32wl5/stm32wl5_gpio.c index 3b22db6f904e2..402d44079f963 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_gpio.c +++ b/arch/arm/src/stm32wl5/stm32wl5_gpio.c @@ -55,19 +55,19 @@ static spinlock_t g_configgpio_lock = SP_UNLOCKED; /* Base addresses for each GPIO block */ -const uint32_t g_gpiobase[STM32WL5_NPORTS] = +const uint32_t g_gpiobase[STM32_NPORTS] = { -#if STM32WL5_NPORTS > 0 - STM32WL5_GPIOA_BASE, +#if STM32_NPORTS > 0 + STM32_GPIOA_BASE, #endif -#if STM32WL5_NPORTS > 1 - STM32WL5_GPIOB_BASE, +#if STM32_NPORTS > 1 + STM32_GPIOB_BASE, #endif -#if STM32WL5_NPORTS > 2 - STM32WL5_GPIOC_BASE, +#if STM32_NPORTS > 2 + STM32_GPIOC_BASE, #endif -#if STM32WL5_NPORTS > 3 - STM32WL5_GPIOH_BASE, +#if STM32_NPORTS > 3 + STM32_GPIOH_BASE, #endif }; @@ -80,13 +80,13 @@ const uint32_t g_gpiobase[STM32WL5_NPORTS] = ****************************************************************************/ /**************************************************************************** - * Function: stm32wl5_gpioinit + * Function: stm32_gpioinit * * Description: * Based on configuration within the .config file, it does: * - Remaps positions of alternative functions. * - * Typically called from stm32wl5_start(). + * Typically called from stm32_start(). * * Assumptions: * This function is called early in the initialization sequence so that @@ -94,17 +94,17 @@ const uint32_t g_gpiobase[STM32WL5_NPORTS] = * ****************************************************************************/ -void stm32wl5_gpioinit(void) +void stm32_gpioinit(void) { } /**************************************************************************** - * Name: stm32wl5_configgpio + * Name: stm32_configgpio * * Description: * Configure a GPIO pin based on bit-encoded description of the pin. * Once it is configured as Alternative (GPIO_ALT|GPIO_CNF_AFPP|...) - * function, it must be unconfigured with stm32wl5_unconfiggpio() with + * function, it must be unconfigured with stm32_unconfiggpio() with * the same cfgset first before it can be set to non-alternative function. * * Returned Value: @@ -115,7 +115,7 @@ void stm32wl5_gpioinit(void) * To-Do: Auto Power Enable ****************************************************************************/ -int stm32wl5_configgpio(uint32_t cfgset) +int stm32_configgpio(uint32_t cfgset) { uintptr_t base; uint32_t regval; @@ -130,7 +130,7 @@ int stm32wl5_configgpio(uint32_t cfgset) /* Verify that this hardware supports the select GPIO port */ port = (cfgset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; - if (port >= STM32WL5_NPORTS) + if (port >= STM32_NPORTS) { return -EINVAL; } @@ -158,7 +158,7 @@ int stm32wl5_configgpio(uint32_t cfgset) /* Set the initial output value */ - stm32wl5_gpiowrite(cfgset, (cfgset & GPIO_OUTPUT_SET) != 0); + stm32_gpiowrite(cfgset, (cfgset & GPIO_OUTPUT_SET) != 0); pinmode = GPIO_MODER_OUTPUT; break; @@ -179,10 +179,10 @@ int stm32wl5_configgpio(uint32_t cfgset) /* Now apply the configuration to the mode register */ - regval = getreg32(base + STM32WL5_GPIO_MODER_OFFSET); + regval = getreg32(base + STM32_GPIO_MODER_OFFSET); regval &= ~GPIO_MODER_MASK(pin); regval |= ((uint32_t)pinmode << GPIO_MODER_SHIFT(pin)); - putreg32(regval, base + STM32WL5_GPIO_MODER_OFFSET); + putreg32(regval, base + STM32_GPIO_MODER_OFFSET); /* Set up the pull-up/pull-down configuration (all but analog pins) */ @@ -205,10 +205,10 @@ int stm32wl5_configgpio(uint32_t cfgset) } } - regval = getreg32(base + STM32WL5_GPIO_PUPDR_OFFSET); + regval = getreg32(base + STM32_GPIO_PUPDR_OFFSET); regval &= ~GPIO_PUPDR_MASK(pin); regval |= (setting << GPIO_PUPDR_SHIFT(pin)); - putreg32(regval, base + STM32WL5_GPIO_PUPDR_OFFSET); + putreg32(regval, base + STM32_GPIO_PUPDR_OFFSET); /* Set the alternate function (Only alternate function pins) */ @@ -223,12 +223,12 @@ int stm32wl5_configgpio(uint32_t cfgset) if (pin < 8) { - regoffset = STM32WL5_GPIO_AFRL_OFFSET; + regoffset = STM32_GPIO_AFRL_OFFSET; pos = pin; } else { - regoffset = STM32WL5_GPIO_AFRH_OFFSET; + regoffset = STM32_GPIO_AFRH_OFFSET; pos = pin - 8; } @@ -266,14 +266,14 @@ int stm32wl5_configgpio(uint32_t cfgset) setting = 0; } - regval = getreg32(base + STM32WL5_GPIO_OSPEED_OFFSET); + regval = getreg32(base + STM32_GPIO_OSPEED_OFFSET); regval &= ~GPIO_OSPEED_MASK(pin); regval |= (setting << GPIO_OSPEED_SHIFT(pin)); - putreg32(regval, base + STM32WL5_GPIO_OSPEED_OFFSET); + putreg32(regval, base + STM32_GPIO_OSPEED_OFFSET); /* Set push-pull/open-drain (Only outputs and alternate function pins) */ - regval = getreg32(base + STM32WL5_GPIO_OTYPER_OFFSET); + regval = getreg32(base + STM32_GPIO_OTYPER_OFFSET); setting = GPIO_OTYPER_OD(pin); if ((pinmode == GPIO_MODER_OUTPUT || pinmode == GPIO_MODER_ALT) && @@ -286,7 +286,7 @@ int stm32wl5_configgpio(uint32_t cfgset) regval &= ~setting; } - putreg32(regval, base + STM32WL5_GPIO_OTYPER_OFFSET); + putreg32(regval, base + STM32_GPIO_OTYPER_OFFSET); /* Otherwise, it is an input pin. Should it configured as an * EXTI interrupt? @@ -303,7 +303,7 @@ int stm32wl5_configgpio(uint32_t cfgset) /* Set the bits in the SYSCFG EXTICR register */ - regaddr = STM32WL5_SYSCFG_EXTICR(pin); + regaddr = STM32_SYSCFG_EXTICR(pin); regval = getreg32(regaddr); shift = SYSCFG_EXTICR_EXTI_SHIFT(pin); regval &= ~(SYSCFG_EXTICR_PORT_MASK << shift); @@ -317,7 +317,7 @@ int stm32wl5_configgpio(uint32_t cfgset) } /**************************************************************************** - * Name: stm32wl5_unconfiggpio + * Name: stm32_unconfiggpio * * Description: * Unconfigure a GPIO pin based on bit-encoded description of the pin, set @@ -337,7 +337,7 @@ int stm32wl5_configgpio(uint32_t cfgset) * To-Do: Auto Power Disable ****************************************************************************/ -int stm32wl5_unconfiggpio(uint32_t cfgset) +int stm32_unconfiggpio(uint32_t cfgset) { /* Reuse port and pin number and set it to default HiZ INPUT */ @@ -346,18 +346,18 @@ int stm32wl5_unconfiggpio(uint32_t cfgset) /* To-Do: Mark its unuse for automatic power saving options */ - return stm32wl5_configgpio(cfgset); + return stm32_configgpio(cfgset); } /**************************************************************************** - * Name: stm32wl5_gpiowrite + * Name: stm32_gpiowrite * * Description: * Write one or zero to the selected GPIO pin * ****************************************************************************/ -void stm32wl5_gpiowrite(uint32_t pinset, bool value) +void stm32_gpiowrite(uint32_t pinset, bool value) { uint32_t base; uint32_t bit; @@ -365,7 +365,7 @@ void stm32wl5_gpiowrite(uint32_t pinset, bool value) unsigned int pin; port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; - if (port < STM32WL5_NPORTS) + if (port < STM32_NPORTS) { /* Get the port base address */ @@ -386,26 +386,26 @@ void stm32wl5_gpiowrite(uint32_t pinset, bool value) bit = GPIO_BSRR_RESET(pin); } - putreg32(bit, base + STM32WL5_GPIO_BSRR_OFFSET); + putreg32(bit, base + STM32_GPIO_BSRR_OFFSET); } } /**************************************************************************** - * Name: stm32wl5_gpioread + * Name: stm32_gpioread * * Description: * Read one or zero from the selected GPIO pin * ****************************************************************************/ -bool stm32wl5_gpioread(uint32_t pinset) +bool stm32_gpioread(uint32_t pinset) { uint32_t base; unsigned int port; unsigned int pin; port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; - if (port < STM32WL5_NPORTS) + if (port < STM32_NPORTS) { /* Get the port base address */ @@ -414,7 +414,7 @@ bool stm32wl5_gpioread(uint32_t pinset) /* Get the pin number and return the input state of that pin */ pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT; - return ((getreg32(base + STM32WL5_GPIO_IDR_OFFSET) & (1 << pin)) != 0); + return ((getreg32(base + STM32_GPIO_IDR_OFFSET) & (1 << pin)) != 0); } return 0; diff --git a/arch/arm/src/stm32wl5/stm32wl5_gpio.h b/arch/arm/src/stm32wl5/stm32wl5_gpio.h index 86480eb193a55..7cfdb7fac2f10 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_gpio.h +++ b/arch/arm/src/stm32wl5/stm32wl5_gpio.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32WL5_STM32WL5_GPIO_H -#define __ARCH_ARM_SRC_STM32WL5_STM32WL5_GPIO_H +#ifndef __ARCH_ARM_SRC_STM32WL5_STM32_GPIO_H +#define __ARCH_ARM_SRC_STM32WL5_STM32_GPIO_H /**************************************************************************** * Included Files @@ -39,7 +39,7 @@ #include "chip.h" -#if defined(CONFIG_STM32WL5_STM32WL5XXX) +#if defined(CONFIG_STM32_STM32WL5XXX) # include "hardware/stm32wl5_gpio.h" #else # error "Unsupported STM32WL5 chip" @@ -49,7 +49,7 @@ * Pre-Processor Declarations ****************************************************************************/ -/* Bit-encoded input to stm32wl5_configgpio() */ +/* Bit-encoded input to stm32_configgpio() */ /* Each port bit of the general-purpose I/O (GPIO) ports can be individually * configured by software in several modes: @@ -237,19 +237,19 @@ extern "C" /* Base addresses for each GPIO block */ -EXTERN const uint32_t g_gpiobase[STM32WL5_NPORTS]; +EXTERN const uint32_t g_gpiobase[STM32_NPORTS]; /**************************************************************************** * Public Function Prototypes ****************************************************************************/ /**************************************************************************** - * Name: stm32wl5_configgpio + * Name: stm32_configgpio * * Description: * Configure a GPIO pin based on bit-encoded description of the pin. * Once it is configured as Alternative (GPIO_ALT|GPIO_CNF_AFPP|...) - * function, it must be unconfigured with stm32wl5_unconfiggpio() with + * function, it must be unconfigured with stm32_unconfiggpio() with * the same cfgset first before it can be set to non-alternative function. * * Returned Value: @@ -258,10 +258,10 @@ EXTERN const uint32_t g_gpiobase[STM32WL5_NPORTS]; * ****************************************************************************/ -int stm32wl5_configgpio(uint32_t cfgset); +int stm32_configgpio(uint32_t cfgset); /**************************************************************************** - * Name: stm32wl5_unconfiggpio + * Name: stm32_unconfiggpio * * Description: * Unconfigure a GPIO pin based on bit-encoded description of the pin, set @@ -280,30 +280,30 @@ int stm32wl5_configgpio(uint32_t cfgset); * ****************************************************************************/ -int stm32wl5_unconfiggpio(uint32_t cfgset); +int stm32_unconfiggpio(uint32_t cfgset); /**************************************************************************** - * Name: stm32wl5_gpiowrite + * Name: stm32_gpiowrite * * Description: * Write one or zero to the selected GPIO pin * ****************************************************************************/ -void stm32wl5_gpiowrite(uint32_t pinset, bool value); +void stm32_gpiowrite(uint32_t pinset, bool value); /**************************************************************************** - * Name: stm32wl5_gpioread + * Name: stm32_gpioread * * Description: * Read one or zero from the selected GPIO pin * ****************************************************************************/ -bool stm32wl5_gpioread(uint32_t pinset); +bool stm32_gpioread(uint32_t pinset); /**************************************************************************** - * Name: stm32wl5_gpiosetevent + * Name: stm32_gpiosetevent * * Description: * Sets/clears GPIO based event and interrupt triggers. @@ -322,11 +322,11 @@ bool stm32wl5_gpioread(uint32_t pinset); * ****************************************************************************/ -int stm32wl5_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, +int stm32_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, bool event, xcpt_t func, void *arg); /**************************************************************************** - * Function: stm32wl5_dumpgpio + * Function: stm32_dumpgpio * * Description: * Dump all GPIO registers associated with the provided base address @@ -334,23 +334,23 @@ int stm32wl5_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, ****************************************************************************/ #ifdef CONFIG_DEBUG_FEATURES -int stm32wl5_dumpgpio(uint32_t pinset, const char *msg); +int stm32_dumpgpio(uint32_t pinset, const char *msg); #else -# define stm32wl5_dumpgpio(p,m) +# define stm32_dumpgpio(p,m) #endif /**************************************************************************** - * Function: stm32wl5_gpioinit + * Function: stm32_gpioinit * * Description: * Based on configuration within the .config file, it does: * - Remaps positions of alternative functions. * - * Typically called from stm32wl5_start(). + * Typically called from stm32_start(). * ****************************************************************************/ -void stm32wl5_gpioinit(void); +void stm32_gpioinit(void); #undef EXTERN #if defined(__cplusplus) @@ -358,4 +358,4 @@ void stm32wl5_gpioinit(void); #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32WL5_STM32WL5_GPIO_H */ +#endif /* __ARCH_ARM_SRC_STM32WL5_STM32_GPIO_H */ diff --git a/arch/arm/src/stm32wl5/stm32wl5_idle.c b/arch/arm/src/stm32wl5/stm32wl5_idle.c index ec70f83270f97..ab1fb4d073dda 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_idle.c +++ b/arch/arm/src/stm32wl5/stm32wl5_idle.c @@ -88,7 +88,7 @@ void up_idle(void) /* Sleep until an interrupt occurs to save power. */ -#if !(defined(CONFIG_DEBUG_SYMBOLS) && defined(CONFIG_STM32WL5_DISABLE_IDLE_SLEEP_DURING_DEBUG)) +#if !(defined(CONFIG_DEBUG_SYMBOLS) && defined(CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG)) BEGIN_IDLE(); asm("WFI"); END_IDLE(); diff --git a/arch/arm/src/stm32wl5/stm32wl5_ipcc.c b/arch/arm/src/stm32wl5/stm32wl5_ipcc.c index 38a41c718032e..e8960ddced0b3 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_ipcc.c +++ b/arch/arm/src/stm32wl5/stm32wl5_ipcc.c @@ -35,7 +35,7 @@ #include #include "hardware/stm32wl5_ipcc.h" -#include "stm32wl5.h" +#include "stm32.h" #include "stm32wl5_ipcc.h" /**************************************************************************** @@ -44,7 +44,7 @@ /* This structure describes tx or rx of single channel in memory */ -struct stm32wl5_ipcc_chan_mem_s +struct stm32_ipcc_chan_mem_s { unsigned len; /* Number of valid bytes in data[] */ char data[]; /* Data in IPCC memory */ @@ -52,7 +52,7 @@ struct stm32wl5_ipcc_chan_mem_s /* Internal stm32wl5 ipcc structure describing channel state. */ -struct stm32wl5_ipcc_s +struct stm32_ipcc_s { /* Pointer to API connecting upper and lower half of the driver */ @@ -65,14 +65,14 @@ struct stm32wl5_ipcc_s char *rxmem; /* Maximum length of data that rxmem can hold. It is size of the - * reserved space for rxmem minus sizeof(stm32wl5_ipcc_chan_mem_s.len) + * reserved space for rxmem minus sizeof(stm32_ipcc_chan_mem_s.len) */ unsigned rxlen; /* Number of bytes copied from IPCC memory to buffer. Can be less than - * stm32wl5_ipcc_chan_mem_s.len after copy operation when buffer is full. - * Value can persist between multiple ISR and stm32wl5_ipcc_buffer_data() + * stm32_ipcc_chan_mem_s.len after copy operation when buffer is full. + * Value can persist between multiple ISR and stm32_ipcc_buffer_data() * calls, until all data from IPCC memory is successfully buffered. * * When unbuffered version is used, this holds number of bytes already @@ -89,7 +89,7 @@ struct stm32wl5_ipcc_s char *txmem; /* Maximum length of data that txmem can hold. It is size of the - * reserved space for txmem minus sizeof(stm32wl5_ipcc_chan_mem_s.len) + * reserved space for txmem minus sizeof(stm32_ipcc_chan_mem_s.len) */ unsigned txlen; @@ -99,24 +99,24 @@ struct stm32wl5_ipcc_s * Private Function Prototypes ****************************************************************************/ -static ssize_t stm32wl5_ipcc_read(struct ipcc_lower_s *ipcc, +static ssize_t stm32_ipcc_read(struct ipcc_lower_s *ipcc, char *buffer, size_t buflen); -static ssize_t stm32wl5_ipcc_write(struct ipcc_lower_s *ipcc, +static ssize_t stm32_ipcc_write(struct ipcc_lower_s *ipcc, const char *buffer, size_t buflen); #ifdef CONFIG_IPCC_BUFFERED -static ssize_t stm32wl5_ipcc_buffer_data(struct ipcc_lower_s *ipcc, +static ssize_t stm32_ipcc_buffer_data(struct ipcc_lower_s *ipcc, struct circbuf_s *rxbuf); -static ssize_t stm32wl5_ipcc_copy_to_buffer(int chan, +static ssize_t stm32_ipcc_copy_to_buffer(int chan, struct circbuf_s *rxbuf); #endif -static int stm32wl5_ipcc_rx_isr(int irq, void *context, void *arg); -static int stm32wl5_ipcc_tx_isr(int irq, void *context, void *arg); +static int stm32_ipcc_rx_isr(int irq, void *context, void *arg); +static int stm32_ipcc_tx_isr(int irq, void *context, void *arg); /**************************************************************************** * Private Data ****************************************************************************/ -struct stm32wl5_ipcc_s g_ipccpriv[IPCC_NCHAN] = +struct stm32_ipcc_s g_ipccpriv[IPCC_NCHAN] = { /* Channel 1 is always enabled when IPCC is enabled */ @@ -183,7 +183,7 @@ struct stm32wl5_ipcc_s g_ipccpriv[IPCC_NCHAN] = ****************************************************************************/ /**************************************************************************** - * Name: stm32wl5_ipcc_tx_isr + * Name: stm32_ipcc_tx_isr * * Description: * IPCC TX interrupt service routine. This interrupt is called when @@ -209,24 +209,24 @@ struct stm32wl5_ipcc_s g_ipccpriv[IPCC_NCHAN] = * ****************************************************************************/ -static int stm32wl5_ipcc_tx_isr(int irq, void *context, void *arg) +static int stm32_ipcc_tx_isr(int irq, void *context, void *arg) { int chan; uint32_t mr; uint32_t sr; uint32_t status; - struct stm32wl5_ipcc_s *priv; + struct stm32_ipcc_s *priv; #ifdef CONFIG_IPCC_BUFFERED size_t nwritten; - struct stm32wl5_ipcc_chan_mem_s *txmem; + struct stm32_ipcc_chan_mem_s *txmem; #endif UNUSED(context); UNUSED(arg); UNUSED(irq); - mr = getreg32(STM32WL5_IPCC_C1MR) >> STM32WL5_IPCC_TX_SHIFT; - sr = getreg32(STM32WL5_IPCC_C1TOC2SR); + mr = getreg32(STM32_IPCC_C1MR) >> STM32_IPCC_TX_SHIFT; + sr = getreg32(STM32_IPCC_C1TOC2SR); /* Consider only channels that have tx memory free and are unmasked */ @@ -251,7 +251,7 @@ static int stm32wl5_ipcc_tx_isr(int irq, void *context, void *arg) priv = &g_ipccpriv[chan]; #ifdef CONFIG_IPCC_BUFFERED - txmem = (struct stm32wl5_ipcc_chan_mem_s *)priv->txmem; + txmem = (struct stm32_ipcc_chan_mem_s *)priv->txmem; /* Copy as much as we can into IPCC memory, circbuf won't copy * more than there is in the buffer. @@ -266,7 +266,7 @@ static int stm32wl5_ipcc_tx_isr(int irq, void *context, void *arg) /* Yes, tell another CPU that data is available to read */ txmem->len = nwritten; - modifyreg32(STM32WL5_IPCC_C1SCR, 0, STM32WL5_IPCC_SCR_CHNS(chan)); + modifyreg32(STM32_IPCC_C1SCR, 0, STM32_IPCC_SCR_CHNS(chan)); } if (circbuf_used(&priv->ipcc->txbuf) == 0) @@ -276,7 +276,7 @@ static int stm32wl5_ipcc_tx_isr(int irq, void *context, void *arg) * will be constantly interrupted by tx free irq. */ - modifyreg32(STM32WL5_IPCC_C1MR, 0, STM32WL5_IPCC_MR_CHNFM(chan)); + modifyreg32(STM32_IPCC_C1MR, 0, STM32_IPCC_MR_CHNFM(chan)); } #else /* CONFIG_IPCC_BUFFERED */ /* In unbuffered operations we never write anything to IPCC @@ -284,7 +284,7 @@ static int stm32wl5_ipcc_tx_isr(int irq, void *context, void *arg) * or else we will constantly get TX interrupts */ - modifyreg32(STM32WL5_IPCC_C1MR, 0, STM32WL5_IPCC_MR_CHNFM(chan)); + modifyreg32(STM32_IPCC_C1MR, 0, STM32_IPCC_MR_CHNFM(chan)); #endif /* CONFIG_IPCC_BUFFERED */ /* Wake up all blocked writers that there is free space available * in IPCC memory (or txbuffer) to write. @@ -297,7 +297,7 @@ static int stm32wl5_ipcc_tx_isr(int irq, void *context, void *arg) } /**************************************************************************** - * Name: stm32wl5_ipcc_write + * Name: stm32_ipcc_write * * Description: * Function writes buffer to IPCC memory that will be later read by @@ -316,15 +316,15 @@ static int stm32wl5_ipcc_tx_isr(int irq, void *context, void *arg) * ****************************************************************************/ -static ssize_t stm32wl5_ipcc_write(struct ipcc_lower_s *ipcc, +static ssize_t stm32_ipcc_write(struct ipcc_lower_s *ipcc, const char *buffer, size_t buflen) { size_t to_copy; - struct stm32wl5_ipcc_s *priv; - struct stm32wl5_ipcc_chan_mem_s *txmem; + struct stm32_ipcc_s *priv; + struct stm32_ipcc_chan_mem_s *txmem; uint32_t sr; - sr = getreg32(STM32WL5_IPCC_C1TOC2SR); + sr = getreg32(STM32_IPCC_C1TOC2SR); if ((sr & (1 << ipcc->chan))) { @@ -334,16 +334,16 @@ static ssize_t stm32wl5_ipcc_write(struct ipcc_lower_s *ipcc, * so we are notified when we can write to memory. */ - modifyreg32(STM32WL5_IPCC_C1MR, STM32WL5_IPCC_MR_CHNFM(ipcc->chan), 0); + modifyreg32(STM32_IPCC_C1MR, STM32_IPCC_MR_CHNFM(ipcc->chan), 0); return 0; } priv = &g_ipccpriv[ipcc->chan]; - txmem = (struct stm32wl5_ipcc_chan_mem_s *)priv->txmem; + txmem = (struct stm32_ipcc_chan_mem_s *)priv->txmem; /* Disable TX interrupt since we will modify shared data */ - up_disable_irq(STM32WL5_IRQ_IPCC_C1_TX_IT); + up_disable_irq(STM32_IRQ_IPCC_C1_TX_IT); /* Copy as much as we can into IPCC memory */ @@ -353,12 +353,12 @@ static ssize_t stm32wl5_ipcc_write(struct ipcc_lower_s *ipcc, /* Tell another CPU that data is available to read */ - modifyreg32(STM32WL5_IPCC_C1SCR, 0, STM32WL5_IPCC_SCR_CHNS(ipcc->chan)); + modifyreg32(STM32_IPCC_C1SCR, 0, STM32_IPCC_SCR_CHNS(ipcc->chan)); /* Re-enable interrupts */ - modifyreg32(STM32WL5_IPCC_C1MR, STM32WL5_IPCC_MR_CHNFM(ipcc->chan), 0); - up_enable_irq(STM32WL5_IRQ_IPCC_C1_TX_IT); + modifyreg32(STM32_IPCC_C1MR, STM32_IPCC_MR_CHNFM(ipcc->chan), 0); + up_enable_irq(STM32_IRQ_IPCC_C1_TX_IT); /* Return number of successfully copied bytes to IPCC memory */ @@ -366,7 +366,7 @@ static ssize_t stm32wl5_ipcc_write(struct ipcc_lower_s *ipcc, } /**************************************************************************** - * Name: stm32wl5_ipcc_rx_isr + * Name: stm32_ipcc_rx_isr * * Description: * Interrupt service routine - this function is called when another CPU @@ -389,13 +389,13 @@ static ssize_t stm32wl5_ipcc_write(struct ipcc_lower_s *ipcc, * ****************************************************************************/ -static int stm32wl5_ipcc_rx_isr(int irq, void *context, void *arg) +static int stm32_ipcc_rx_isr(int irq, void *context, void *arg) { int chan; uint32_t mr; uint32_t sr; uint32_t status; - struct stm32wl5_ipcc_s *priv; + struct stm32_ipcc_s *priv; #ifdef CONFIG_IPCC_BUFFERED ssize_t nread; #endif @@ -404,8 +404,8 @@ static int stm32wl5_ipcc_rx_isr(int irq, void *context, void *arg) UNUSED(arg); UNUSED(irq); - mr = getreg32(STM32WL5_IPCC_C1MR); - sr = getreg32(STM32WL5_IPCC_C2TOC1SR); + mr = getreg32(STM32_IPCC_C1MR); + sr = getreg32(STM32_IPCC_C2TOC1SR); /* Consider only channels that have data in rx memory and are unmasked */ @@ -429,7 +429,7 @@ static int stm32wl5_ipcc_rx_isr(int irq, void *context, void *arg) priv = &g_ipccpriv[chan]; #ifdef CONFIG_IPCC_BUFFERED - nread = stm32wl5_ipcc_copy_to_buffer(chan, &priv->ipcc->rxbuf); + nread = stm32_ipcc_copy_to_buffer(chan, &priv->ipcc->rxbuf); if (nread) #endif /* CONFIG_IPCC_BUFFERED */ @@ -446,7 +446,7 @@ static int stm32wl5_ipcc_rx_isr(int irq, void *context, void *arg) * we have to mask rxirq so we don't get that irq again. */ - modifyreg32(STM32WL5_IPCC_C1MR, 0, STM32WL5_IPCC_MR_CHNOM(chan)); + modifyreg32(STM32_IPCC_C1MR, 0, STM32_IPCC_MR_CHNOM(chan)); #endif } @@ -454,7 +454,7 @@ static int stm32wl5_ipcc_rx_isr(int irq, void *context, void *arg) } /**************************************************************************** - * Name: stm32wl5_ipcc_read + * Name: stm32_ipcc_read * * Description: * Function will copy requests number of bytes to buffer. If there is not @@ -477,15 +477,15 @@ static int stm32wl5_ipcc_rx_isr(int irq, void *context, void *arg) * ****************************************************************************/ -static ssize_t stm32wl5_ipcc_read(struct ipcc_lower_s *ipcc, +static ssize_t stm32_ipcc_read(struct ipcc_lower_s *ipcc, char *buffer, size_t buflen) { size_t to_copy; uint32_t sr; - struct stm32wl5_ipcc_s *priv; - struct stm32wl5_ipcc_chan_mem_s *rxmem; + struct stm32_ipcc_s *priv; + struct stm32_ipcc_chan_mem_s *rxmem; - sr = getreg32(STM32WL5_IPCC_C2TOC1SR); + sr = getreg32(STM32_IPCC_C2TOC1SR); if (!(sr & (1 << ipcc->chan))) { @@ -498,11 +498,11 @@ static ssize_t stm32wl5_ipcc_read(struct ipcc_lower_s *ipcc, } priv = &g_ipccpriv[ipcc->chan]; - rxmem = (struct stm32wl5_ipcc_chan_mem_s *)priv->rxmem; + rxmem = (struct stm32_ipcc_chan_mem_s *)priv->rxmem; /* Disable RX interrupt since we will modify shared data */ - up_disable_irq(STM32WL5_IRQ_IPCC_C1_RX_IT); + up_disable_irq(STM32_IRQ_IPCC_C1_RX_IT); /* This function may be called multiple times to get only part * of data from IPCC memory, ie. There are 8 bytes of data in @@ -525,23 +525,23 @@ static ssize_t stm32wl5_ipcc_read(struct ipcc_lower_s *ipcc, /* Tell another CPU that IPCC rx buffer is free to be populated */ - modifyreg32(STM32WL5_IPCC_C1SCR, 0, - STM32WL5_IPCC_SCR_CHNC(ipcc->chan)); + modifyreg32(STM32_IPCC_C1SCR, 0, + STM32_IPCC_SCR_CHNC(ipcc->chan)); /* Unmask RX interrupt to know when second CPU sends us a message */ - modifyreg32(STM32WL5_IPCC_C1MR, STM32WL5_IPCC_MR_CHNOM(ipcc->chan), 0); + modifyreg32(STM32_IPCC_C1MR, STM32_IPCC_MR_CHNOM(ipcc->chan), 0); } /* Re-enable interrupt */ - up_enable_irq(STM32WL5_IRQ_IPCC_C1_RX_IT); + up_enable_irq(STM32_IRQ_IPCC_C1_RX_IT); return to_copy; } /**************************************************************************** - * Name: stm32wl5_ipcc_copy_to_buffer + * Name: stm32_ipcc_copy_to_buffer * * Description: * Copies as much bytes from channel as possible to rxbuf circ buffer. @@ -560,16 +560,16 @@ static ssize_t stm32wl5_ipcc_read(struct ipcc_lower_s *ipcc, ****************************************************************************/ #ifdef CONFIG_IPCC_BUFFERED -static ssize_t stm32wl5_ipcc_copy_to_buffer(int chan, +static ssize_t stm32_ipcc_copy_to_buffer(int chan, struct circbuf_s *rxbuf) { size_t to_copy; size_t rxbuf_space; - struct stm32wl5_ipcc_s *priv; - struct stm32wl5_ipcc_chan_mem_s *rxmem; + struct stm32_ipcc_s *priv; + struct stm32_ipcc_chan_mem_s *rxmem; uint32_t sr; - sr = getreg32(STM32WL5_IPCC_C2TOC1SR); + sr = getreg32(STM32_IPCC_C2TOC1SR); if (!(sr & (1 << chan))) { @@ -582,7 +582,7 @@ static ssize_t stm32wl5_ipcc_copy_to_buffer(int chan, } priv = &g_ipccpriv[chan]; - rxmem = (struct stm32wl5_ipcc_chan_mem_s *)priv->rxmem; + rxmem = (struct stm32_ipcc_chan_mem_s *)priv->rxmem; /* If buffer is full, it's possible we did not copy everything from * IPCC memory to buffer in previous interrupt. Then when another @@ -609,7 +609,7 @@ static ssize_t stm32wl5_ipcc_copy_to_buffer(int chan, * this one. */ - modifyreg32(STM32WL5_IPCC_C1MR, 0, STM32WL5_IPCC_MR_CHNOM(chan)); + modifyreg32(STM32_IPCC_C1MR, 0, STM32_IPCC_MR_CHNOM(chan)); } /* Buffer data. This function cannot really fail us if we @@ -629,11 +629,11 @@ static ssize_t stm32wl5_ipcc_copy_to_buffer(int chan, /* Tell another CPU that IPCC rx buffer is free to be populated */ - modifyreg32(STM32WL5_IPCC_C1SCR, 0, STM32WL5_IPCC_SCR_CHNC(chan)); + modifyreg32(STM32_IPCC_C1SCR, 0, STM32_IPCC_SCR_CHNC(chan)); /* Unmask RX interrupt to know when second CPU sends us a message */ - modifyreg32(STM32WL5_IPCC_C1MR, STM32WL5_IPCC_MR_CHNOM(chan), 0); + modifyreg32(STM32_IPCC_C1MR, STM32_IPCC_MR_CHNOM(chan), 0); } return to_copy; @@ -641,7 +641,7 @@ static ssize_t stm32wl5_ipcc_copy_to_buffer(int chan, #endif /**************************************************************************** - * Name: stm32wl5_ipcc_buffer_data + * Name: stm32_ipcc_buffer_data * * Description: * Copies as many bytes as possible from ipcc channel to rxbuf. @@ -658,22 +658,22 @@ static ssize_t stm32wl5_ipcc_copy_to_buffer(int chan, ****************************************************************************/ #ifdef CONFIG_IPCC_BUFFERED -static ssize_t stm32wl5_ipcc_buffer_data(struct ipcc_lower_s *ipcc, +static ssize_t stm32_ipcc_buffer_data(struct ipcc_lower_s *ipcc, struct circbuf_s *rxbuf) { int ret; /* Disable RX interrupt since we will modify shared data */ - up_disable_irq(STM32WL5_IRQ_IPCC_C1_RX_IT); + up_disable_irq(STM32_IRQ_IPCC_C1_RX_IT); /* Copy data to buffer */ - ret = stm32wl5_ipcc_copy_to_buffer(ipcc->chan, rxbuf); + ret = stm32_ipcc_copy_to_buffer(ipcc->chan, rxbuf); /* Re-enable interrupt */ - up_enable_irq(STM32WL5_IRQ_IPCC_C1_RX_IT); + up_enable_irq(STM32_IRQ_IPCC_C1_RX_IT); /* Return number of bytes that were successfully buffered */ @@ -682,7 +682,7 @@ static ssize_t stm32wl5_ipcc_buffer_data(struct ipcc_lower_s *ipcc, #endif /**************************************************************************** - * Name: stm32wl5_ipcc_write_notify + * Name: stm32_ipcc_write_notify * * Description: * This function is called when there is new data on circ buffer. @@ -699,18 +699,18 @@ static ssize_t stm32wl5_ipcc_buffer_data(struct ipcc_lower_s *ipcc, ****************************************************************************/ #ifdef CONFIG_IPCC_BUFFERED -static ssize_t stm32wl5_ipcc_write_notify(struct ipcc_lower_s *ipcc) +static ssize_t stm32_ipcc_write_notify(struct ipcc_lower_s *ipcc) { - modifyreg32(STM32WL5_IPCC_C1MR, STM32WL5_IPCC_MR_CHNFM(ipcc->chan), 0); + modifyreg32(STM32_IPCC_C1MR, STM32_IPCC_MR_CHNFM(ipcc->chan), 0); return 0; } #endif /**************************************************************************** - * Name: stm32wl5_ipcc_cleanup + * Name: stm32_ipcc_cleanup * * Description: - * Cleans up resources initialized by stm32wl5_ipcc_init(). This will + * Cleans up resources initialized by stm32_ipcc_init(). This will * free() ipcc pointer! * * Input Parameters: @@ -721,15 +721,15 @@ static ssize_t stm32wl5_ipcc_write_notify(struct ipcc_lower_s *ipcc) * ****************************************************************************/ -static int stm32wl5_ipcc_cleanup(struct ipcc_lower_s *ipcc) +static int stm32_ipcc_cleanup(struct ipcc_lower_s *ipcc) { DEBUGASSERT(ipcc); DEBUGASSERT(ipcc->chan <= IPCC_NCHAN); /* Mask interrupts for given channel */ - modifyreg32(STM32WL5_IPCC_C1MR, 1, STM32WL5_IPCC_MR_CHNFM(ipcc->chan)); - modifyreg32(STM32WL5_IPCC_C1MR, 1, STM32WL5_IPCC_MR_CHNOM(ipcc->chan)); + modifyreg32(STM32_IPCC_C1MR, 1, STM32_IPCC_MR_CHNFM(ipcc->chan)); + modifyreg32(STM32_IPCC_C1MR, 1, STM32_IPCC_MR_CHNOM(ipcc->chan)); /* Free allocated ipcc memory */ @@ -743,7 +743,7 @@ static int stm32wl5_ipcc_cleanup(struct ipcc_lower_s *ipcc) ****************************************************************************/ /**************************************************************************** - * Name: stm32wl5_ipcc_init + * Name: stm32_ipcc_init * * Description: * Function initializes runtime options for IPCC. This function is called @@ -762,7 +762,7 @@ static int stm32wl5_ipcc_cleanup(struct ipcc_lower_s *ipcc) * ****************************************************************************/ -struct ipcc_lower_s *stm32wl5_ipcc_init(int chan) +struct ipcc_lower_s *stm32_ipcc_init(int chan) { int ret; static int ipcc_fti; @@ -786,20 +786,20 @@ struct ipcc_lower_s *stm32wl5_ipcc_init(int chan) * upper half needs to call to work properly. */ - ipcc->ops.read = stm32wl5_ipcc_read; - ipcc->ops.write = stm32wl5_ipcc_write; - ipcc->ops.cleanup = stm32wl5_ipcc_cleanup; + ipcc->ops.read = stm32_ipcc_read; + ipcc->ops.write = stm32_ipcc_write; + ipcc->ops.cleanup = stm32_ipcc_cleanup; #ifdef CONFIG_IPCC_BUFFERED - ipcc->ops.buffer_data = stm32wl5_ipcc_buffer_data; - ipcc->ops.write_notify = stm32wl5_ipcc_write_notify; + ipcc->ops.buffer_data = stm32_ipcc_buffer_data; + ipcc->ops.write_notify = stm32_ipcc_write_notify; #endif ipcc->chan = chan; /* Unmask channel interrupt */ - modifyreg32(STM32WL5_IPCC_C1MR, STM32WL5_IPCC_MR_CHNFM(chan), 0); - modifyreg32(STM32WL5_IPCC_C1MR, STM32WL5_IPCC_MR_CHNOM(chan), 0); + modifyreg32(STM32_IPCC_C1MR, STM32_IPCC_MR_CHNFM(chan), 0); + modifyreg32(STM32_IPCC_C1MR, STM32_IPCC_MR_CHNOM(chan), 0); if (ipcc_fti) { @@ -810,14 +810,14 @@ struct ipcc_lower_s *stm32wl5_ipcc_init(int chan) * interrupt functions */ - ret = irq_attach(STM32WL5_IRQ_IPCC_C1_RX_IT, stm32wl5_ipcc_rx_isr, NULL); + ret = irq_attach(STM32_IRQ_IPCC_C1_RX_IT, stm32_ipcc_rx_isr, NULL); if (ret) { kmm_free(ipcc); return NULL; } - ret = irq_attach(STM32WL5_IRQ_IPCC_C1_TX_IT, stm32wl5_ipcc_tx_isr, NULL); + ret = irq_attach(STM32_IRQ_IPCC_C1_TX_IT, stm32_ipcc_tx_isr, NULL); if (ret) { kmm_free(ipcc); @@ -829,11 +829,11 @@ struct ipcc_lower_s *stm32wl5_ipcc_init(int chan) * - CPU2 has read message from us and TX memory is free to be used again */ - putreg32(STM32WL5_IPCC_CR_RXOIE | STM32WL5_IPCC_CR_TXFIE, - STM32WL5_IPCC_C1CR); + putreg32(STM32_IPCC_CR_RXOIE | STM32_IPCC_CR_TXFIE, + STM32_IPCC_C1CR); - up_enable_irq(STM32WL5_IRQ_IPCC_C1_RX_IT); - up_enable_irq(STM32WL5_IRQ_IPCC_C1_TX_IT); + up_enable_irq(STM32_IRQ_IPCC_C1_RX_IT); + up_enable_irq(STM32_IRQ_IPCC_C1_TX_IT); ipcc_fti = 1; diff --git a/arch/arm/src/stm32wl5/stm32wl5_ipcc.h b/arch/arm/src/stm32wl5/stm32wl5_ipcc.h index 14b68fdb151f3..bd420571efc44 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_ipcc.h +++ b/arch/arm/src/stm32wl5/stm32wl5_ipcc.h @@ -41,17 +41,17 @@ /* channel 1 configuration **************************************************/ -#define IPCC_CHAN1_RX_SIZE (CONFIG_STM32WL5_IPCC_CHAN1_RX_SIZE) -#define IPCC_CHAN1_TX_SIZE (CONFIG_STM32WL5_IPCC_CHAN1_TX_SIZE) +#define IPCC_CHAN1_RX_SIZE (CONFIG_STM32_IPCC_CHAN1_RX_SIZE) +#define IPCC_CHAN1_TX_SIZE (CONFIG_STM32_IPCC_CHAN1_TX_SIZE) #define IPCC_CHAN1_START (IPCC_START) #define IPCC_CHAN1_SIZE (IPCC_CHAN1_RX_SIZE + IPCC_CHAN1_TX_SIZE) #define IPCC_CHAN1 (1) /* channel 2 configuration **************************************************/ -#if defined(CONFIG_STM32WL5_IPCC_CHAN2) -# define IPCC_CHAN2_RX_SIZE (CONFIG_STM32WL5_IPCC_CHAN2_RX_SIZE) -# define IPCC_CHAN2_TX_SIZE (CONFIG_STM32WL5_IPCC_CHAN2_TX_SIZE) +#if defined(CONFIG_STM32_IPCC_CHAN2) +# define IPCC_CHAN2_RX_SIZE (CONFIG_STM32_IPCC_CHAN2_RX_SIZE) +# define IPCC_CHAN2_TX_SIZE (CONFIG_STM32_IPCC_CHAN2_TX_SIZE) # define IPCC_CHAN2_START (IPCC_CHAN1_START + IPCC_CHAN1_SIZE) # define IPCC_CHAN2_SIZE (IPCC_CHAN2_RX_SIZE + IPCC_CHAN2_TX_SIZE) # define IPCC_CHAN2 (1) @@ -62,9 +62,9 @@ /* channel 3 configuration **************************************************/ -#if defined(CONFIG_STM32WL5_IPCC_CHAN3) -# define IPCC_CHAN3_RX_SIZE (CONFIG_STM32WL5_IPCC_CHAN3_RX_SIZE) -# define IPCC_CHAN3_TX_SIZE (CONFIG_STM32WL5_IPCC_CHAN3_TX_SIZE) +#if defined(CONFIG_STM32_IPCC_CHAN3) +# define IPCC_CHAN3_RX_SIZE (CONFIG_STM32_IPCC_CHAN3_RX_SIZE) +# define IPCC_CHAN3_TX_SIZE (CONFIG_STM32_IPCC_CHAN3_TX_SIZE) # define IPCC_CHAN3_START (IPCC_CHAN2_START + IPCC_CHAN2_SIZE) # define IPCC_CHAN3_SIZE (IPCC_CHAN3_RX_SIZE + IPCC_CHAN3_TX_SIZE) # define IPCC_CHAN3 (1) @@ -75,9 +75,9 @@ /* channel 4 configuration **************************************************/ -#if defined(CONFIG_STM32WL5_IPCC_CHAN4) -# define IPCC_CHAN4_RX_SIZE (CONFIG_STM32WL5_IPCC_CHAN4_RX_SIZE) -# define IPCC_CHAN4_TX_SIZE (CONFIG_STM32WL5_IPCC_CHAN4_TX_SIZE) +#if defined(CONFIG_STM32_IPCC_CHAN4) +# define IPCC_CHAN4_RX_SIZE (CONFIG_STM32_IPCC_CHAN4_RX_SIZE) +# define IPCC_CHAN4_TX_SIZE (CONFIG_STM32_IPCC_CHAN4_TX_SIZE) # define IPCC_CHAN4_START (IPCC_CHAN3_START + IPCC_CHAN3_SIZE) # define IPCC_CHAN4_SIZE (IPCC_CHAN4_RX_SIZE + IPCC_CHAN4_TX_SIZE) # define IPCC_CHAN4 (1) @@ -88,9 +88,9 @@ /* channel 5 configuration **************************************************/ -#if defined(CONFIG_STM32WL5_IPCC_CHAN5) -# define IPCC_CHAN5_RX_SIZE (CONFIG_STM32WL5_IPCC_CHAN5_RX_SIZE) -# define IPCC_CHAN5_TX_SIZE (CONFIG_STM32WL5_IPCC_CHAN5_TX_SIZE) +#if defined(CONFIG_STM32_IPCC_CHAN5) +# define IPCC_CHAN5_RX_SIZE (CONFIG_STM32_IPCC_CHAN5_RX_SIZE) +# define IPCC_CHAN5_TX_SIZE (CONFIG_STM32_IPCC_CHAN5_TX_SIZE) # define IPCC_CHAN5_START (IPCC_CHAN4_START + IPCC_CHAN4_SIZE) # define IPCC_CHAN5_SIZE (IPCC_CHAN5_RX_SIZE + IPCC_CHAN5_TX_SIZE) # define IPCC_CHAN5 (1) @@ -101,9 +101,9 @@ /* channel 6 configuration **************************************************/ -#if defined(CONFIG_STM32WL5_IPCC_CHAN6) -# define IPCC_CHAN6_RX_SIZE (CONFIG_STM32WL5_IPCC_CHAN6_RX_SIZE) -# define IPCC_CHAN6_TX_SIZE (CONFIG_STM32WL5_IPCC_CHAN6_TX_SIZE) +#if defined(CONFIG_STM32_IPCC_CHAN6) +# define IPCC_CHAN6_RX_SIZE (CONFIG_STM32_IPCC_CHAN6_RX_SIZE) +# define IPCC_CHAN6_TX_SIZE (CONFIG_STM32_IPCC_CHAN6_TX_SIZE) # define IPCC_CHAN6_START (IPCC_CHAN5_START + IPCC_CHAN5_SIZE) # define IPCC_CHAN6_SIZE (IPCC_CHAN6_RX_SIZE + IPCC_CHAN6_TX_SIZE) # define IPCC_CHAN6 (1) @@ -135,13 +135,13 @@ * of SRAM2. SRAM2 region will be right after IPCC reserved memory */ -#define IPCC_START STM32WL5_SRAM2_BASE +#define IPCC_START STM32_SRAM2_BASE #define IPCC_NCHAN (IPCC_CHAN1 + IPCC_CHAN2 + IPCC_CHAN3 + \ IPCC_CHAN4 + IPCC_CHAN5 + IPCC_CHAN6) #define IPCC_END (IPCC_START + IPCC_CHAN1_SIZE + IPCC_CHAN2_SIZE + \ IPCC_CHAN3_SIZE + IPCC_CHAN4_SIZE + \ IPCC_CHAN5_SIZE + IPCC_CHAN6_SIZE) -struct ipcc_lower_s *stm32wl5_ipcc_init(int chan); +struct ipcc_lower_s *stm32_ipcc_init(int chan); #endif /* __ARCH_ARM_SRC_STM32WL5_IPCC_H */ diff --git a/arch/arm/src/stm32wl5/stm32wl5_irq.c b/arch/arm/src/stm32wl5/stm32wl5_irq.c index 8e953adb2500f..3fc635c72f7e9 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_irq.c +++ b/arch/arm/src/stm32wl5/stm32wl5_irq.c @@ -38,7 +38,7 @@ #include "nvic.h" #include "ram_vectors.h" #include "arm_internal.h" -#include "stm32wl5.h" +#include "stm32.h" /**************************************************************************** * Pre-processor Definitions @@ -64,7 +64,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32wl5_dumpnvic + * Name: stm32_dumpnvic * * Description: * Dump some interesting NVIC registers @@ -72,7 +72,7 @@ ****************************************************************************/ #if defined(CONFIG_DEBUG_IRQ_INFO) -static void stm32wl5_dumpnvic(const char *msg, int irq) +static void stm32_dumpnvic(const char *msg, int irq) { irqstate_t flags; @@ -128,11 +128,11 @@ static void stm32wl5_dumpnvic(const char *msg, int irq) leave_critical_section(flags); } #else -# define stm32wl5_dumpnvic(msg, irq) +# define stm32_dumpnvic(msg, irq) #endif /**************************************************************************** - * Name: stm32wl5_nmi, stm32wl5_pendsv, stm32wl5_pendsv, stm32wl5_reserved + * Name: stm32_nmi, stm32_pendsv, stm32_pendsv, stm32_reserved * * Description: * Handlers for various exceptions. None are handled and all are fatal @@ -142,7 +142,7 @@ static void stm32wl5_dumpnvic(const char *msg, int irq) ****************************************************************************/ #ifdef CONFIG_DEBUG_FEATURES -static int stm32wl5_nmi(int irq, void *context, void *arg) +static int stm32_nmi(int irq, void *context, void *arg) { up_irq_save(); _err("PANIC!!! NMI received\n"); @@ -150,7 +150,7 @@ static int stm32wl5_nmi(int irq, void *context, void *arg) return 0; } -static int stm32wl5_pendsv(int irq, void *context, void *arg) +static int stm32_pendsv(int irq, void *context, void *arg) { up_irq_save(); _err("PANIC!!! PendSV received\n"); @@ -158,7 +158,7 @@ static int stm32wl5_pendsv(int irq, void *context, void *arg) return 0; } -static int stm32wl5_reserved(int irq, void *context, void *arg) +static int stm32_reserved(int irq, void *context, void *arg) { up_irq_save(); _err("PANIC!!! Reserved interrupt\n"); @@ -168,7 +168,7 @@ static int stm32wl5_reserved(int irq, void *context, void *arg) #endif /**************************************************************************** - * Name: stm32wl5_prioritize_syscall + * Name: stm32_prioritize_syscall * * Description: * Set the priority of an exception. This function may be needed @@ -176,7 +176,7 @@ static int stm32wl5_reserved(int irq, void *context, void *arg) * ****************************************************************************/ -static inline void stm32wl5_prioritize_syscall(int priority) +static inline void stm32_prioritize_syscall(int priority) { uint32_t regval; @@ -189,7 +189,7 @@ static inline void stm32wl5_prioritize_syscall(int priority) } /**************************************************************************** - * Name: stm32wl5_irqinfo + * Name: stm32_irqinfo * * Description: * Given an IRQ number, provide the register and bit setting to enable or @@ -197,18 +197,18 @@ static inline void stm32wl5_prioritize_syscall(int priority) * ****************************************************************************/ -static int stm32wl5_irqinfo(int irq, uintptr_t *regaddr, uint32_t *bit, +static int stm32_irqinfo(int irq, uintptr_t *regaddr, uint32_t *bit, uintptr_t offset) { int n; - DEBUGASSERT(irq >= STM32WL5_IRQ_NMI && irq < NR_IRQS); + DEBUGASSERT(irq >= STM32_IRQ_NMI && irq < NR_IRQS); /* Check for external interrupt */ - if (irq >= STM32WL5_IRQ_FIRST) + if (irq >= STM32_IRQ_FIRST) { - n = irq - STM32WL5_IRQ_FIRST; + n = irq - STM32_IRQ_FIRST; *regaddr = NVIC_IRQ_ENABLE(n) + offset; *bit = (uint32_t)1 << (n & 0x1f); } @@ -218,19 +218,19 @@ static int stm32wl5_irqinfo(int irq, uintptr_t *regaddr, uint32_t *bit, else { *regaddr = NVIC_SYSHCON; - if (irq == STM32WL5_IRQ_MEMFAULT) + if (irq == STM32_IRQ_MEMFAULT) { *bit = NVIC_SYSHCON_MEMFAULTENA; } - else if (irq == STM32WL5_IRQ_BUSFAULT) + else if (irq == STM32_IRQ_BUSFAULT) { *bit = NVIC_SYSHCON_BUSFAULTENA; } - else if (irq == STM32WL5_IRQ_USAGEFAULT) + else if (irq == STM32_IRQ_USAGEFAULT) { *bit = NVIC_SYSHCON_USGFAULTENA; } - else if (irq == STM32WL5_IRQ_SYSTICK) + else if (irq == STM32_IRQ_SYSTICK) { *regaddr = NVIC_SYSTICK_CTRL; *bit = NVIC_SYSTICK_CTRL_ENABLE; @@ -260,7 +260,7 @@ void up_irqinitialize(void) /* Disable all interrupts */ - for (i = 0; i < NR_IRQS - STM32WL5_IRQ_FIRST; i += 32) + for (i = 0; i < NR_IRQS - STM32_IRQ_FIRST; i += 32) { putreg32(0xffffffff, NVIC_IRQ_CLEAR(i)); } @@ -314,42 +314,42 @@ void up_irqinitialize(void) * under certain conditions. */ - irq_attach(STM32WL5_IRQ_SVCALL, arm_svcall, NULL); - irq_attach(STM32WL5_IRQ_HARDFAULT, arm_hardfault, NULL); + irq_attach(STM32_IRQ_SVCALL, arm_svcall, NULL); + irq_attach(STM32_IRQ_HARDFAULT, arm_hardfault, NULL); /* Set the priority of the SVCall interrupt */ #ifdef CONFIG_ARCH_IRQPRIO - /* up_prioritize_irq(STM32WL5_IRQ_PENDSV, NVIC_SYSH_PRIORITY_MIN); */ + /* up_prioritize_irq(STM32_IRQ_PENDSV, NVIC_SYSH_PRIORITY_MIN); */ #endif - stm32wl5_prioritize_syscall(NVIC_SYSH_SVCALL_PRIORITY); + stm32_prioritize_syscall(NVIC_SYSH_SVCALL_PRIORITY); /* If the MPU is enabled, then attach and enable the Memory Management * Fault handler. */ #ifdef CONFIG_ARM_MPU - irq_attach(STM32WL5_IRQ_MEMFAULT, arm_memfault, NULL); - up_enable_irq(STM32WL5_IRQ_MEMFAULT); + irq_attach(STM32_IRQ_MEMFAULT, arm_memfault, NULL); + up_enable_irq(STM32_IRQ_MEMFAULT); #endif /* Attach all other processor exceptions (except reset and sys tick) */ #ifdef CONFIG_DEBUG_FEATURES - irq_attach(STM32WL5_IRQ_NMI, stm32wl5_nmi, NULL); + irq_attach(STM32_IRQ_NMI, stm32_nmi, NULL); #ifndef CONFIG_ARM_MPU - irq_attach(STM32WL5_IRQ_MEMFAULT, arm_memfault, NULL); + irq_attach(STM32_IRQ_MEMFAULT, arm_memfault, NULL); #endif - irq_attach(STM32WL5_IRQ_BUSFAULT, arm_busfault, NULL); - irq_attach(STM32WL5_IRQ_USAGEFAULT, arm_usagefault, NULL); - irq_attach(STM32WL5_IRQ_PENDSV, stm32wl5_pendsv, NULL); + irq_attach(STM32_IRQ_BUSFAULT, arm_busfault, NULL); + irq_attach(STM32_IRQ_USAGEFAULT, arm_usagefault, NULL); + irq_attach(STM32_IRQ_PENDSV, stm32_pendsv, NULL); arm_enable_dbgmonitor(); - irq_attach(STM32WL5_IRQ_DBGMONITOR, arm_dbgmonitor, NULL); - irq_attach(STM32WL5_IRQ_RESERVED, stm32wl5_reserved, NULL); + irq_attach(STM32_IRQ_DBGMONITOR, arm_dbgmonitor, NULL); + irq_attach(STM32_IRQ_RESERVED, stm32_reserved, NULL); #endif - stm32wl5_dumpnvic("initial", NR_IRQS); + stm32_dumpnvic("initial", NR_IRQS); #ifndef CONFIG_SUPPRESS_INTERRUPTS @@ -374,7 +374,7 @@ void up_disable_irq(int irq) uint32_t regval; uint32_t bit; - if (stm32wl5_irqinfo(irq, ®addr, &bit, NVIC_CLRENA_OFFSET) == 0) + if (stm32_irqinfo(irq, ®addr, &bit, NVIC_CLRENA_OFFSET) == 0) { /* Modify the appropriate bit in the register to disable the interrupt. * For normal interrupts, we need to set the bit in the associated @@ -382,7 +382,7 @@ void up_disable_irq(int irq) * clear the bit in the System Handler Control and State Register. */ - if (irq >= STM32WL5_IRQ_FIRST) + if (irq >= STM32_IRQ_FIRST) { putreg32(bit, regaddr); } @@ -409,7 +409,7 @@ void up_enable_irq(int irq) uint32_t regval; uint32_t bit; - if (stm32wl5_irqinfo(irq, ®addr, &bit, NVIC_ENA_OFFSET) == 0) + if (stm32_irqinfo(irq, ®addr, &bit, NVIC_ENA_OFFSET) == 0) { /* Modify the appropriate bit in the register to enable the interrupt. * For normal interrupts, we need to set the bit in the associated @@ -417,7 +417,7 @@ void up_enable_irq(int irq) * set the bit in the System Handler Control and State Register. */ - if (irq >= STM32WL5_IRQ_FIRST) + if (irq >= STM32_IRQ_FIRST) { putreg32(bit, regaddr); } @@ -460,10 +460,10 @@ int up_prioritize_irq(int irq, int priority) uint32_t regval; int shift; - DEBUGASSERT(irq >= STM32WL5_IRQ_MEMFAULT && irq < NR_IRQS && + DEBUGASSERT(irq >= STM32_IRQ_MEMFAULT && irq < NR_IRQS && (unsigned)priority <= NVIC_SYSH_PRIORITY_MIN); - if (irq < STM32WL5_IRQ_FIRST) + if (irq < STM32_IRQ_FIRST) { /* NVIC_SYSH_PRIORITY() maps {0..15} to one of three priority * registers (0-3 are invalid) @@ -476,7 +476,7 @@ int up_prioritize_irq(int irq, int priority) { /* NVIC_IRQ_PRIORITY() maps {0..} to one of many priority registers */ - irq -= STM32WL5_IRQ_FIRST; + irq -= STM32_IRQ_FIRST; regaddr = NVIC_IRQ_PRIORITY(irq); } @@ -486,7 +486,7 @@ int up_prioritize_irq(int irq, int priority) regval |= (priority << shift); putreg32(regval, regaddr); - stm32wl5_dumpnvic("prioritize", irq); + stm32_dumpnvic("prioritize", irq); return OK; } #endif diff --git a/arch/arm/src/stm32wl5/stm32wl5_lowputc.c b/arch/arm/src/stm32wl5/stm32wl5_lowputc.c index 06a47209fc635..fd992865e706e 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_lowputc.c +++ b/arch/arm/src/stm32wl5/stm32wl5_lowputc.c @@ -34,7 +34,7 @@ #include "chip.h" -#include "stm32wl5.h" +#include "stm32.h" #include "stm32wl5_rcc.h" #include "stm32wl5_gpio.h" #include "stm32wl5_uart.h" @@ -47,70 +47,70 @@ #ifdef HAVE_CONSOLE # if defined(CONFIG_LPUART1_SERIAL_CONSOLE) -# define STM32WL5_CONSOLE_BASE STM32WL5_LPUART1_BASE -# define STM32WL5_APBCLOCK STM32WL5_PCLK1_FREQUENCY -# define STM32WL5_CONSOLE_APBREG STM32WL5_RCC_APB1ENR2 -# define STM32WL5_CONSOLE_APBEN RCC_APB1ENR2_LPUART1EN -# define STM32WL5_CONSOLE_BAUD CONFIG_LPUART1_BAUD -# define STM32WL5_CONSOLE_BITS CONFIG_LPUART1_BITS -# define STM32WL5_CONSOLE_PARITY CONFIG_LPUART1_PARITY -# define STM32WL5_CONSOLE_2STOP CONFIG_LPUART1_2STOP -# define STM32WL5_CONSOLE_TX GPIO_LPUART1_TX -# define STM32WL5_CONSOLE_RX GPIO_LPUART1_RX +# define STM32_CONSOLE_BASE STM32_LPUART1_BASE +# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY +# define STM32_CONSOLE_APBREG STM32_RCC_APB1ENR2 +# define STM32_CONSOLE_APBEN RCC_APB1ENR2_LPUART1EN +# define STM32_CONSOLE_BAUD CONFIG_LPUART1_BAUD +# define STM32_CONSOLE_BITS CONFIG_LPUART1_BITS +# define STM32_CONSOLE_PARITY CONFIG_LPUART1_PARITY +# define STM32_CONSOLE_2STOP CONFIG_LPUART1_2STOP +# define STM32_CONSOLE_TX GPIO_LPUART1_TX +# define STM32_CONSOLE_RX GPIO_LPUART1_RX # ifdef CONFIG_LPUART1_RS485 -# define STM32WL5_CONSOLE_RS485_DIR GPIO_LPUART1_RS485_DIR +# define STM32_CONSOLE_RS485_DIR GPIO_LPUART1_RS485_DIR # if (CONFIG_LPUART1_RS485_DIR_POLARITY == 0) -# define STM32WL5_CONSOLE_RS485_DIR_POLARITY false +# define STM32_CONSOLE_RS485_DIR_POLARITY false # else -# define STM32WL5_CONSOLE_RS485_DIR_POLARITY true +# define STM32_CONSOLE_RS485_DIR_POLARITY true # endif # endif # elif defined(CONFIG_USART1_SERIAL_CONSOLE) -# define STM32WL5_CONSOLE_BASE STM32WL5_USART1_BASE -# define STM32WL5_APBCLOCK STM32WL5_PCLK2_FREQUENCY -# define STM32WL5_CONSOLE_APBREG STM32WL5_RCC_APB2ENR -# define STM32WL5_CONSOLE_APBEN RCC_APB2ENR_USART1EN -# define STM32WL5_CONSOLE_BAUD CONFIG_USART1_BAUD -# define STM32WL5_CONSOLE_BITS CONFIG_USART1_BITS -# define STM32WL5_CONSOLE_PARITY CONFIG_USART1_PARITY -# define STM32WL5_CONSOLE_2STOP CONFIG_USART1_2STOP -# define STM32WL5_CONSOLE_TX GPIO_USART1_TX -# define STM32WL5_CONSOLE_RX GPIO_USART1_RX +# define STM32_CONSOLE_BASE STM32_USART1_BASE +# define STM32_APBCLOCK STM32_PCLK2_FREQUENCY +# define STM32_CONSOLE_APBREG STM32_RCC_APB2ENR +# define STM32_CONSOLE_APBEN RCC_APB2ENR_USART1EN +# define STM32_CONSOLE_BAUD CONFIG_USART1_BAUD +# define STM32_CONSOLE_BITS CONFIG_USART1_BITS +# define STM32_CONSOLE_PARITY CONFIG_USART1_PARITY +# define STM32_CONSOLE_2STOP CONFIG_USART1_2STOP +# define STM32_CONSOLE_TX GPIO_USART1_TX +# define STM32_CONSOLE_RX GPIO_USART1_RX # ifdef CONFIG_USART1_RS485 -# define STM32WL5_CONSOLE_RS485_DIR GPIO_USART1_RS485_DIR +# define STM32_CONSOLE_RS485_DIR GPIO_USART1_RS485_DIR # if (CONFIG_USART1_RS485_DIR_POLARITY == 0) -# define STM32WL5_CONSOLE_RS485_DIR_POLARITY false +# define STM32_CONSOLE_RS485_DIR_POLARITY false # else -# define STM32WL5_CONSOLE_RS485_DIR_POLARITY true +# define STM32_CONSOLE_RS485_DIR_POLARITY true # endif # endif # elif defined(CONFIG_USART2_SERIAL_CONSOLE) -# define STM32WL5_CONSOLE_BASE STM32WL5_USART2_BASE -# define STM32WL5_APBCLOCK STM32WL5_PCLK1_FREQUENCY -# define STM32WL5_CONSOLE_APBREG STM32WL5_RCC_APB1ENR1 -# define STM32WL5_CONSOLE_APBEN RCC_APB1ENR1_USART2EN -# define STM32WL5_CONSOLE_BAUD CONFIG_USART2_BAUD -# define STM32WL5_CONSOLE_BITS CONFIG_USART2_BITS -# define STM32WL5_CONSOLE_PARITY CONFIG_USART2_PARITY -# define STM32WL5_CONSOLE_2STOP CONFIG_USART2_2STOP -# define STM32WL5_CONSOLE_TX GPIO_USART2_TX -# define STM32WL5_CONSOLE_RX GPIO_USART2_RX +# define STM32_CONSOLE_BASE STM32_USART2_BASE +# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY +# define STM32_CONSOLE_APBREG STM32_RCC_APB1ENR1 +# define STM32_CONSOLE_APBEN RCC_APB1ENR1_USART2EN +# define STM32_CONSOLE_BAUD CONFIG_USART2_BAUD +# define STM32_CONSOLE_BITS CONFIG_USART2_BITS +# define STM32_CONSOLE_PARITY CONFIG_USART2_PARITY +# define STM32_CONSOLE_2STOP CONFIG_USART2_2STOP +# define STM32_CONSOLE_TX GPIO_USART2_TX +# define STM32_CONSOLE_RX GPIO_USART2_RX # ifdef CONFIG_USART2_RS485 -# define STM32WL5_CONSOLE_RS485_DIR GPIO_USART2_RS485_DIR +# define STM32_CONSOLE_RS485_DIR GPIO_USART2_RS485_DIR # if (CONFIG_USART2_RS485_DIR_POLARITY == 0) -# define STM32WL5_CONSOLE_RS485_DIR_POLARITY false +# define STM32_CONSOLE_RS485_DIR_POLARITY false # else -# define STM32WL5_CONSOLE_RS485_DIR_POLARITY true +# define STM32_CONSOLE_RS485_DIR_POLARITY true # endif # endif # endif /* CR1 settings */ -# if STM32WL5_CONSOLE_BITS == 9 +# if STM32_CONSOLE_BITS == 9 # define USART_CR1_M0_VALUE USART_CR1_M0 # define USART_CR1_M1_VALUE 0 -# elif STM32WL5_CONSOLE_BITS == 7 +# elif STM32_CONSOLE_BITS == 7 # define USART_CR1_M0_VALUE 0 # define USART_CR1_M1_VALUE USART_CR1_M1 # else /* 8 bits */ @@ -118,9 +118,9 @@ # define USART_CR1_M1_VALUE 0 # endif -# if STM32WL5_CONSOLE_PARITY == 1 /* odd parity */ +# if STM32_CONSOLE_PARITY == 1 /* odd parity */ # define USART_CR1_PARITY_VALUE (USART_CR1_PCE|USART_CR1_PS) -# elif STM32WL5_CONSOLE_PARITY == 2 /* even parity */ +# elif STM32_CONSOLE_PARITY == 2 /* even parity */ # define USART_CR1_PARITY_VALUE USART_CR1_PCE # else /* no parity */ # define USART_CR1_PARITY_VALUE 0 @@ -136,7 +136,7 @@ /* CR2 settings */ -# if STM32WL5_CONSOLE_2STOP != 0 +# if STM32_CONSOLE_2STOP != 0 # define USART_CR2_STOP2_VALUE USART_CR2_STOP2 # else # define USART_CR2_STOP2_VALUE 0 @@ -178,24 +178,24 @@ * UARTDIV = 2 * fCK / baud */ -# define STM32WL5_USARTDIV8 \ - (((STM32WL5_APBCLOCK << 1) + (STM32WL5_CONSOLE_BAUD >> 1)) / STM32WL5_CONSOLE_BAUD) -# define STM32WL5_USARTDIV16 \ - ((STM32WL5_APBCLOCK + (STM32WL5_CONSOLE_BAUD >> 1)) / STM32WL5_CONSOLE_BAUD) +# define STM32_USARTDIV8 \ + (((STM32_APBCLOCK << 1) + (STM32_CONSOLE_BAUD >> 1)) / STM32_CONSOLE_BAUD) +# define STM32_USARTDIV16 \ + ((STM32_APBCLOCK + (STM32_CONSOLE_BAUD >> 1)) / STM32_CONSOLE_BAUD) /* Use oversamply by 8 only if the divisor is small. But what is small? */ # if defined(CONFIG_LPUART1_SERIAL_CONSOLE) /* lpuart has different formula for baud rate than normal uart */ -# define STM32WL5_BRR_VALUE \ - (((256ull * STM32WL5_APBCLOCK) / STM32WL5_CONSOLE_BAUD) & LPUART_BRR_MASK) +# define STM32_BRR_VALUE \ + (((256ull * STM32_APBCLOCK) / STM32_CONSOLE_BAUD) & LPUART_BRR_MASK) # else /* CONFIG_LPUART1_SERIAL_CONSOLE */ -# if STM32WL5_USARTDIV8 > 2000 -# define STM32WL5_BRR_VALUE STM32WL5_USARTDIV16 +# if STM32_USARTDIV8 > 2000 +# define STM32_BRR_VALUE STM32_USARTDIV16 # else # define USE_OVER8 1 -# define STM32WL5_BRR_VALUE \ - ((STM32WL5_USARTDIV8 & 0xfff0) | ((STM32WL5_USARTDIV8 & 0x000f) >> 1)) +# define STM32_BRR_VALUE \ + ((STM32_USARTDIV8 & 0xfff0) | ((STM32_USARTDIV8 & 0x000f) >> 1)) # endif # endif /* CONFIG_LPUART1_SERIAL_CONSOLE */ @@ -238,29 +238,29 @@ void arm_lowputc(char ch) #ifdef HAVE_CONSOLE /* Wait until the TX data register is empty */ - while ((getreg32(STM32WL5_CONSOLE_BASE + STM32WL5_USART_ISR_OFFSET) & + while ((getreg32(STM32_CONSOLE_BASE + STM32_USART_ISR_OFFSET) & USART_ISR_TXE) == 0); -#ifdef STM32WL5_CONSOLE_RS485_DIR - stm32wl5_gpiowrite(STM32WL5_CONSOLE_RS485_DIR, - STM32WL5_CONSOLE_RS485_DIR_POLARITY); +#ifdef STM32_CONSOLE_RS485_DIR + stm32_gpiowrite(STM32_CONSOLE_RS485_DIR, + STM32_CONSOLE_RS485_DIR_POLARITY); #endif /* Then send the character */ - putreg32((uint32_t)ch, STM32WL5_CONSOLE_BASE + STM32WL5_USART_TDR_OFFSET); + putreg32((uint32_t)ch, STM32_CONSOLE_BASE + STM32_USART_TDR_OFFSET); -#ifdef STM32WL5_CONSOLE_RS485_DIR - while ((getreg32(STM32WL5_CONSOLE_BASE + STM32WL5_USART_ISR_OFFSET) & +#ifdef STM32_CONSOLE_RS485_DIR + while ((getreg32(STM32_CONSOLE_BASE + STM32_USART_ISR_OFFSET) & USART_ISR_TC) == 0); - stm32wl5_gpiowrite(STM32WL5_CONSOLE_RS485_DIR, - !STM32WL5_CONSOLE_RS485_DIR_POLARITY); + stm32_gpiowrite(STM32_CONSOLE_RS485_DIR, + !STM32_CONSOLE_RS485_DIR_POLARITY); #endif #endif /* HAVE_CONSOLE */ } /**************************************************************************** - * Name: stm32wl5_lowsetup + * Name: stm32_lowsetup * * Description: * This performs basic initialization of the USART used for the serial @@ -269,7 +269,7 @@ void arm_lowputc(char ch) * ****************************************************************************/ -void stm32wl5_lowsetup(void) +void stm32_lowsetup(void) { #if defined(HAVE_UART) #if defined(HAVE_CONSOLE) && !defined(CONFIG_SUPPRESS_UART_CONFIG) @@ -279,26 +279,26 @@ void stm32wl5_lowsetup(void) #if defined(HAVE_CONSOLE) /* Enable USART APB1/2 clock */ - modifyreg32(STM32WL5_CONSOLE_APBREG, 0, STM32WL5_CONSOLE_APBEN); + modifyreg32(STM32_CONSOLE_APBREG, 0, STM32_CONSOLE_APBEN); #endif /* Enable the console USART and configure GPIO pins needed for rx/tx. * * NOTE: Clocking for selected U[S]ARTs was already provided in - * stm32wl5_rcc.c + * stm32_rcc.c */ -#ifdef STM32WL5_CONSOLE_TX - stm32wl5_configgpio(STM32WL5_CONSOLE_TX); +#ifdef STM32_CONSOLE_TX + stm32_configgpio(STM32_CONSOLE_TX); #endif -#ifdef STM32WL5_CONSOLE_RX - stm32wl5_configgpio(STM32WL5_CONSOLE_RX); +#ifdef STM32_CONSOLE_RX + stm32_configgpio(STM32_CONSOLE_RX); #endif -#ifdef STM32WL5_CONSOLE_RS485_DIR - stm32wl5_configgpio(STM32WL5_CONSOLE_RS485_DIR); - stm32wl5_gpiowrite(STM32WL5_CONSOLE_RS485_DIR, - !STM32WL5_CONSOLE_RS485_DIR_POLARITY); +#ifdef STM32_CONSOLE_RS485_DIR + stm32_configgpio(STM32_CONSOLE_RS485_DIR); + stm32_gpiowrite(STM32_CONSOLE_RS485_DIR, + !STM32_CONSOLE_RS485_DIR_POLARITY); #endif /* Enable and configure the selected console device */ @@ -306,42 +306,42 @@ void stm32wl5_lowsetup(void) #if defined(HAVE_CONSOLE) && !defined(CONFIG_SUPPRESS_UART_CONFIG) /* Configure CR2 */ - cr = getreg32(STM32WL5_CONSOLE_BASE + STM32WL5_USART_CR2_OFFSET); + cr = getreg32(STM32_CONSOLE_BASE + STM32_USART_CR2_OFFSET); cr &= ~USART_CR2_CLRBITS; cr |= USART_CR2_SETBITS; - putreg32(cr, STM32WL5_CONSOLE_BASE + STM32WL5_USART_CR2_OFFSET); + putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR2_OFFSET); /* Configure CR1 */ - cr = getreg32(STM32WL5_CONSOLE_BASE + STM32WL5_USART_CR1_OFFSET); + cr = getreg32(STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET); cr &= ~USART_CR1_CLRBITS; cr |= USART_CR1_SETBITS; - putreg32(cr, STM32WL5_CONSOLE_BASE + STM32WL5_USART_CR1_OFFSET); + putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET); /* Configure CR3 */ - cr = getreg32(STM32WL5_CONSOLE_BASE + STM32WL5_USART_CR3_OFFSET); + cr = getreg32(STM32_CONSOLE_BASE + STM32_USART_CR3_OFFSET); cr &= ~USART_CR3_CLRBITS; cr |= USART_CR3_SETBITS; - putreg32(cr, STM32WL5_CONSOLE_BASE + STM32WL5_USART_CR3_OFFSET); + putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR3_OFFSET); /* Configure the USART Baud Rate */ - putreg32(STM32WL5_BRR_VALUE, - STM32WL5_CONSOLE_BASE + STM32WL5_USART_BRR_OFFSET); + putreg32(STM32_BRR_VALUE, + STM32_CONSOLE_BASE + STM32_USART_BRR_OFFSET); /* Select oversampling by 8 */ - cr = getreg32(STM32WL5_CONSOLE_BASE + STM32WL5_USART_CR1_OFFSET); + cr = getreg32(STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET); #ifdef USE_OVER8 cr |= USART_CR1_OVER8; - putreg32(cr, STM32WL5_CONSOLE_BASE + STM32WL5_USART_CR1_OFFSET); + putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET); #endif /* Enable Rx, Tx, and the USART */ cr |= (USART_CR1_UE | USART_CR1_TE | USART_CR1_RE); - putreg32(cr, STM32WL5_CONSOLE_BASE + STM32WL5_USART_CR1_OFFSET); + putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET); #endif /* HAVE_CONSOLE && !CONFIG_SUPPRESS_UART_CONFIG */ #endif /* HAVE_UART */ diff --git a/arch/arm/src/stm32wl5/stm32wl5_lowputc.h b/arch/arm/src/stm32wl5/stm32wl5_lowputc.h index 3ab795bc58ca6..f4c7d186d3b10 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_lowputc.h +++ b/arch/arm/src/stm32wl5/stm32wl5_lowputc.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32WL5_STM32WL5_LOWPUTC_H -#define __ARCH_ARM_SRC_STM32WL5_STM32WL5_LOWPUTC_H +#ifndef __ARCH_ARM_SRC_STM32WL5_STM32_LOWPUTC_H +#define __ARCH_ARM_SRC_STM32WL5_STM32_LOWPUTC_H /**************************************************************************** * Included Files @@ -47,7 +47,7 @@ extern "C" #endif /**************************************************************************** - * Name: stm32wl5_lowsetup + * Name: stm32_lowsetup * * Description: * Called at the very beginning of _start. Performs low level @@ -55,7 +55,7 @@ extern "C" * ****************************************************************************/ -void stm32wl5_lowsetup(void); +void stm32_lowsetup(void); #undef EXTERN #if defined(__cplusplus) @@ -63,4 +63,4 @@ void stm32wl5_lowsetup(void); #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32WL5_STM32WL5_LOWPUTC_H */ +#endif /* __ARCH_ARM_SRC_STM32WL5_STM32_LOWPUTC_H */ diff --git a/arch/arm/src/stm32wl5/stm32wl5_lse.c b/arch/arm/src/stm32wl5/stm32wl5_lse.c index 5abad5f93ab6c..50857241ebc3b 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_lse.c +++ b/arch/arm/src/stm32wl5/stm32wl5_lse.c @@ -32,7 +32,7 @@ #include "stm32wl5_pwr.h" #include "stm32wl5_rcc.h" -#include "stm32wl5_waste.h" +#include "stm32_waste.h" /**************************************************************************** * Pre-processor Definitions @@ -43,9 +43,9 @@ static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1, #define LSERDY_TIMEOUT (500 * CONFIG_BOARD_LOOPSPERMSEC) -#ifdef CONFIG_STM32WL5_RTC_LSECLOCK_START_DRV_CAPABILITY -# if CONFIG_STM32WL5_RTC_LSECLOCK_START_DRV_CAPABILITY < 0 || \ - CONFIG_STM32WL5_RTC_LSECLOCK_START_DRV_CAPABILITY > 3 +#ifdef CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY +# if CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY < 0 || \ + CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY > 3 # error "Invalid LSE drive capability setting" # endif #endif @@ -54,7 +54,7 @@ static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1, * Private Data ****************************************************************************/ -#ifdef CONFIG_STM32WL5_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY +#ifdef CONFIG_STM32_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY static const uint32_t drives[4] = { RCC_BDCR_LSEDRV_LOW, @@ -69,19 +69,19 @@ static const uint32_t drives[4] = ****************************************************************************/ /**************************************************************************** - * Name: stm32wl5_rcc_enablelse + * Name: stm32_rcc_enablelse * * Description: * Enable the External Low-Speed (LSE) oscillator and the LSE system clock. * ****************************************************************************/ -void stm32wl5_rcc_enablelse(void) +void stm32_rcc_enablelse(void) { int writable; uint32_t regval; volatile int32_t timeout; -#ifdef CONFIG_STM32WL5_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY +#ifdef CONFIG_STM32_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY volatile int32_t drive = 0; #endif @@ -89,7 +89,7 @@ void stm32wl5_rcc_enablelse(void) * clock are already running. */ - regval = getreg32(STM32WL5_RCC_BDCR); + regval = getreg32(STM32_RCC_BDCR); if ((regval & (RCC_BDCR_LSEON | RCC_BDCR_LSERDY | RCC_BDCR_LSESYSEN | RCC_BDCR_LSESYSEN)) != @@ -101,7 +101,7 @@ void stm32wl5_rcc_enablelse(void) * the PWR CR register before to configuring the LSE. */ - writable = stm32wl5_pwr_enablebkp(true); + writable = stm32_pwr_enablebkp(true); /* Enable the External Low-Speed (LSE) oscillator by setting the LSEON * bit the RCC BDCR register. @@ -109,28 +109,28 @@ void stm32wl5_rcc_enablelse(void) regval |= RCC_BDCR_LSEON; -#ifdef CONFIG_STM32WL5_RTC_LSECLOCK_START_DRV_CAPABILITY +#ifdef CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY /* Set start-up drive capability for LSE oscillator. LSE must be OFF * to change drive strength. */ regval &= ~(RCC_BDCR_LSEDRV_MASK | RCC_BDCR_LSEON); - regval |= CONFIG_STM32WL5_RTC_LSECLOCK_START_DRV_CAPABILITY << + regval |= CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY << RCC_BDCR_LSEDRV_SHIFT; - putreg32(regval, STM32WL5_RCC_BDCR); + putreg32(regval, STM32_RCC_BDCR); regval |= RCC_BDCR_LSEON; #endif -#ifdef CONFIG_STM32WL5_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY +#ifdef CONFIG_STM32_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY do { regval &= ~(RCC_BDCR_LSEDRV_MASK | RCC_BDCR_LSEON); regval |= drives[drive++]; - putreg32(regval, STM32WL5_RCC_BDCR); + putreg32(regval, STM32_RCC_BDCR); regval |= RCC_BDCR_LSEON; #endif - putreg32(regval, STM32WL5_RCC_BDCR); + putreg32(regval, STM32_RCC_BDCR); /* Wait for the LSE clock to be ready (or until a timeout elapsed) */ @@ -139,7 +139,7 @@ void stm32wl5_rcc_enablelse(void) { /* Check if the LSERDY flag is the set in the BDCR */ - regval = getreg32(STM32WL5_RCC_BDCR); + regval = getreg32(STM32_RCC_BDCR); if (regval & RCC_BDCR_LSERDY) { @@ -149,7 +149,7 @@ void stm32wl5_rcc_enablelse(void) } } -#ifdef CONFIG_STM32WL5_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY +#ifdef CONFIG_STM32_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY if (timeout != 0) { break; @@ -167,28 +167,28 @@ void stm32wl5_rcc_enablelse(void) regval |= RCC_BDCR_LSESYSEN; - putreg32(regval, STM32WL5_RCC_BDCR); + putreg32(regval, STM32_RCC_BDCR); /* Wait for the LSE system clock to be ready */ - while (!((regval = getreg32(STM32WL5_RCC_BDCR)) & + while (!((regval = getreg32(STM32_RCC_BDCR)) & RCC_BDCR_LSESYSRDY)) { - stm32wl5_waste(); + stm32_waste(); } } -#ifdef CONFIG_STM32WL5_RTC_LSECLOCK_LOWER_RUN_DRV_CAPABILITY +#ifdef CONFIG_STM32_RTC_LSECLOCK_LOWER_RUN_DRV_CAPABILITY /* Set running drive capability for LSE oscillator. */ regval &= ~RCC_BDCR_LSEDRV_MASK; regval |= RCC_BDCR_LSEDRV_LOW << RCC_BDCR_LSEDRV_SHIFT; - putreg32(regval, STM32WL5_RCC_BDCR); + putreg32(regval, STM32_RCC_BDCR); #endif /* Disable backup domain access if it was disabled on entry */ - (void)stm32wl5_pwr_enablebkp(writable); + (void)stm32_pwr_enablebkp(writable); } } diff --git a/arch/arm/src/stm32wl5/stm32wl5_lsi.c b/arch/arm/src/stm32wl5/stm32wl5_lsi.c index ea4495ddbd664..12ce587823d89 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_lsi.c +++ b/arch/arm/src/stm32wl5/stm32wl5_lsi.c @@ -33,41 +33,41 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32wl5_rcc_enablelsi + * Name: stm32_rcc_enablelsi * * Description: * Enable the Internal Low-Speed (LSI) RC Oscillator. * ****************************************************************************/ -void stm32wl5_rcc_enablelsi(void) +void stm32_rcc_enablelsi(void) { /* Enable the Internal Low-Speed (LSI) RC Oscillator by setting the LSION * bit the RCC CSR register. */ - modifyreg32(STM32WL5_RCC_CSR, 0, RCC_CSR_LSION); + modifyreg32(STM32_RCC_CSR, 0, RCC_CSR_LSION); /* Wait for the internal LSI oscillator to be stable. */ - while ((getreg32(STM32WL5_RCC_CSR) & RCC_CSR_LSIRDY) == 0); + while ((getreg32(STM32_RCC_CSR) & RCC_CSR_LSIRDY) == 0); } /**************************************************************************** - * Name: stm32wl5_rcc_disablelsi + * Name: stm32_rcc_disablelsi * * Description: * Disable the Internal Low-Speed (LSI) RC Oscillator. * ****************************************************************************/ -void stm32wl5_rcc_disablelsi(void) +void stm32_rcc_disablelsi(void) { /* Enable the Internal Low-Speed (LSI) RC Oscillator by setting the LSION * bit the RCC CSR register. */ - modifyreg32(STM32WL5_RCC_CSR, RCC_CSR_LSION, 0); + modifyreg32(STM32_RCC_CSR, RCC_CSR_LSION, 0); /* LSIRDY should go low after 3 LSI clock cycles */ } diff --git a/arch/arm/src/stm32wl5/stm32wl5_mpuinit.c b/arch/arm/src/stm32wl5/stm32wl5_mpuinit.c index beab699c02548..07fe40f5aefc2 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_mpuinit.c +++ b/arch/arm/src/stm32wl5/stm32wl5_mpuinit.c @@ -41,7 +41,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32wl5_mpuinitialize + * Name: stm32_mpuinitialize * * Description: * Configure the MPU to permit user-space access to only restricted SAM3U @@ -49,7 +49,7 @@ * ****************************************************************************/ -void stm32wl5_mpuinitialize(void) +void stm32_mpuinitialize(void) { uintptr_t datastart = MIN(USERSPACE->us_datastart, USERSPACE->us_bssstart); uintptr_t dataend = MAX(USERSPACE->us_dataend, USERSPACE->us_bssend); @@ -74,7 +74,7 @@ void stm32wl5_mpuinitialize(void) } /**************************************************************************** - * Name: stm32wl5_mpu_uheap + * Name: stm32_mpu_uheap * * Description: * Map the user-heap region. @@ -83,7 +83,7 @@ void stm32wl5_mpuinitialize(void) * ****************************************************************************/ -void stm32wl5_mpu_uheap(uintptr_t start, size_t size) +void stm32_mpu_uheap(uintptr_t start, size_t size) { mpu_user_intsram(start, size); } diff --git a/arch/arm/src/stm32wl5/stm32wl5_mpuinit.h b/arch/arm/src/stm32wl5/stm32wl5_mpuinit.h index 46968b5add0b2..4ea88ebba9892 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_mpuinit.h +++ b/arch/arm/src/stm32wl5/stm32wl5_mpuinit.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32WL5_STM32WL5_MPUINIT_H -#define __ARCH_ARM_SRC_STM32WL5_STM32WL5_MPUINIT_H +#ifndef __ARCH_ARM_SRC_STM32WL5_STM32_MPUINIT_H +#define __ARCH_ARM_SRC_STM32WL5_STM32_MPUINIT_H /**************************************************************************** * Included Files @@ -34,7 +34,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32wl5_mpuinitialize + * Name: stm32_mpuinitialize * * Description: * Configure the MPU to permit user-space access to only unrestricted MCU @@ -43,13 +43,13 @@ ****************************************************************************/ #ifdef CONFIG_BUILD_PROTECTED -void stm32wl5_mpuinitialize(void); +void stm32_mpuinitialize(void); #else -# define stm32wl5_mpuinitialize() +# define stm32_mpuinitialize() #endif /**************************************************************************** - * Name: stm32wl5_mpu_uheap + * Name: stm32_mpu_uheap * * Description: * Map the user heap region. @@ -57,9 +57,9 @@ void stm32wl5_mpuinitialize(void); ****************************************************************************/ #ifdef CONFIG_BUILD_PROTECTED -void stm32wl5_mpu_uheap(uintptr_t start, size_t size); +void stm32_mpu_uheap(uintptr_t start, size_t size); #else -# define stm32wl5_mpu_uheap(start,size) +# define stm32_mpu_uheap(start,size) #endif -#endif /* __ARCH_ARM_SRC_STM32WL5_STM32WL5_MPUINIT_H */ +#endif /* __ARCH_ARM_SRC_STM32WL5_STM32_MPUINIT_H */ diff --git a/arch/arm/src/stm32wl5/stm32wl5_pwr.c b/arch/arm/src/stm32wl5/stm32wl5_pwr.c index e1a1644ed5631..001302dab922f 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_pwr.c +++ b/arch/arm/src/stm32wl5/stm32wl5_pwr.c @@ -40,20 +40,20 @@ * Private Functions ****************************************************************************/ -static inline uint16_t stm32wl5_pwr_getreg(uint8_t offset) +static inline uint16_t stm32_pwr_getreg(uint8_t offset) { - return (uint16_t)getreg32(STM32WL5_PWR_BASE + (uint32_t)offset); + return (uint16_t)getreg32(STM32_PWR_BASE + (uint32_t)offset); } -static inline void stm32wl5_pwr_putreg(uint8_t offset, uint16_t value) +static inline void stm32_pwr_putreg(uint8_t offset, uint16_t value) { - putreg32((uint32_t)value, STM32WL5_PWR_BASE + (uint32_t)offset); + putreg32((uint32_t)value, STM32_PWR_BASE + (uint32_t)offset); } -static inline void stm32wl5_pwr_modifyreg(uint8_t offset, uint16_t clearbits, +static inline void stm32_pwr_modifyreg(uint8_t offset, uint16_t clearbits, uint16_t setbits) { - modifyreg32(STM32WL5_PWR_BASE + (uint32_t)offset, (uint32_t)clearbits, + modifyreg32(STM32_PWR_BASE + (uint32_t)offset, (uint32_t)clearbits, (uint32_t)setbits); } @@ -62,7 +62,7 @@ static inline void stm32wl5_pwr_modifyreg(uint8_t offset, uint16_t clearbits, ****************************************************************************/ /**************************************************************************** - * Name: stm32wl5_pwr_enablebkp + * Name: stm32_pwr_enablebkp * * Description: * Enables access to the backup domain (RTC registers, RTC backup data @@ -76,14 +76,14 @@ static inline void stm32wl5_pwr_modifyreg(uint8_t offset, uint16_t clearbits, * ****************************************************************************/ -bool stm32wl5_pwr_enablebkp(bool writable) +bool stm32_pwr_enablebkp(bool writable) { uint16_t regval; bool waswritable; /* Get the current state of the STM32WL5 PWR control register 1 */ - regval = stm32wl5_pwr_getreg(STM32WL5_PWR_CR1_OFFSET); + regval = stm32_pwr_getreg(STM32_PWR_CR1_OFFSET); waswritable = ((regval & PWR_CR1_DBP) != 0); /* Enable or disable the ability to write */ @@ -93,14 +93,14 @@ bool stm32wl5_pwr_enablebkp(bool writable) /* Disable backup domain access */ regval &= ~PWR_CR1_DBP; - stm32wl5_pwr_putreg(STM32WL5_PWR_CR1_OFFSET, regval); + stm32_pwr_putreg(STM32_PWR_CR1_OFFSET, regval); } else if (!waswritable && writable) { /* Enable backup domain access */ regval |= PWR_CR1_DBP; - stm32wl5_pwr_putreg(STM32WL5_PWR_CR1_OFFSET, regval); + stm32_pwr_putreg(STM32_PWR_CR1_OFFSET, regval); /* Enable does not happen right away */ @@ -111,7 +111,7 @@ bool stm32wl5_pwr_enablebkp(bool writable) } /**************************************************************************** - * Name: stm32wl5_pwr_boot_c2 + * Name: stm32_pwr_boot_c2 * * Description: * Boots up CPU2 (cortex-m0) after reset or wakeup from stop or standby @@ -119,7 +119,7 @@ bool stm32wl5_pwr_enablebkp(bool writable) * ****************************************************************************/ -void stm32wl5_pwr_boot_c2(void) +void stm32_pwr_boot_c2(void) { - modifyreg32(STM32WL5_PWR_CR4, 0, PWR_CR4_C2BOOT); + modifyreg32(STM32_PWR_CR4, 0, PWR_CR4_C2BOOT); } diff --git a/arch/arm/src/stm32wl5/stm32wl5_pwr.h b/arch/arm/src/stm32wl5/stm32wl5_pwr.h index 7ad5243285396..824bb05fe19f7 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_pwr.h +++ b/arch/arm/src/stm32wl5/stm32wl5_pwr.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32WL5_STM32WL5_PWR_H -#define __ARCH_ARM_SRC_STM32WL5_STM32WL5_PWR_H +#ifndef __ARCH_ARM_SRC_STM32WL5_STM32_PWR_H +#define __ARCH_ARM_SRC_STM32WL5_STM32_PWR_H /**************************************************************************** * Included Files @@ -54,7 +54,7 @@ extern "C" ****************************************************************************/ /**************************************************************************** - * Name: stm32wl5_pwr_enablebkp + * Name: stm32_pwr_enablebkp * * Description: * Enables access to the backup domain (RTC registers, RTC backup data @@ -68,10 +68,10 @@ extern "C" * ****************************************************************************/ -bool stm32wl5_pwr_enablebkp(bool writable); +bool stm32_pwr_enablebkp(bool writable); /**************************************************************************** - * Name: stm32wl5_pwr_boot_c2 + * Name: stm32_pwr_boot_c2 * * Description: * Boots up CPU2 (cortex-m0) after reset or wakeup from stop or standby @@ -79,7 +79,7 @@ bool stm32wl5_pwr_enablebkp(bool writable); * ****************************************************************************/ -void stm32wl5_pwr_boot_c2(void); +void stm32_pwr_boot_c2(void); #undef EXTERN #if defined(__cplusplus) @@ -87,4 +87,4 @@ void stm32wl5_pwr_boot_c2(void); #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32WL5_STM32WL5_PWR_H */ +#endif /* __ARCH_ARM_SRC_STM32WL5_STM32_PWR_H */ diff --git a/arch/arm/src/stm32wl5/stm32wl5_rcc.c b/arch/arm/src/stm32wl5/stm32wl5_rcc.c index 571ea43fc7fd7..d3e4786f5ee95 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_rcc.c +++ b/arch/arm/src/stm32wl5/stm32wl5_rcc.c @@ -38,8 +38,8 @@ #include "chip.h" #include "stm32wl5_rcc.h" #include "stm32wl5_flash.h" -#include "stm32wl5.h" -#include "stm32wl5_waste.h" +#include "stm32.h" +#include "stm32_waste.h" /**************************************************************************** * Pre-processor Definitions @@ -74,52 +74,52 @@ * ****************************************************************************/ -#if defined(CONFIG_STM32WL5_PWR) && defined(CONFIG_STM32WL5_RTC) -static inline void stm32wl5_rcc_resetbkp(void) +#if defined(CONFIG_STM32_PWR) && defined(CONFIG_STM32_RTC) +static inline void stm32_rcc_resetbkp(void) { bool init_stat; /* Check if the RTC is already configured */ - init_stat = stm32wl5_rtc_is_initialized(); + init_stat = stm32_rtc_is_initialized(); if (!init_stat) { - uint32_t bkregs[STM32WL5_RTC_BKCOUNT]; + uint32_t bkregs[STM32_RTC_BKCOUNT]; int i; /* Backup backup-registers before RTC reset. */ - for (i = 0; i < STM32WL5_RTC_BKCOUNT; i++) + for (i = 0; i < STM32_RTC_BKCOUNT; i++) { - bkregs[i] = getreg32(STM32WL5_RTC_BKR(i)); + bkregs[i] = getreg32(STM32_RTC_BKR(i)); } /* Enable write access to the backup domain (RTC registers, RTC * backup data registers and backup SRAM). */ - (void)stm32wl5_pwr_enablebkp(true); + (void)stm32_pwr_enablebkp(true); /* We might be changing RTCSEL - to ensure such changes work, we must * reset the backup domain (having backed up the RTC_MAGIC token) */ - modifyreg32(STM32WL5_RCC_BDCR, 0, RCC_BDCR_BDRST); - modifyreg32(STM32WL5_RCC_BDCR, RCC_BDCR_BDRST, 0); + modifyreg32(STM32_RCC_BDCR, 0, RCC_BDCR_BDRST); + modifyreg32(STM32_RCC_BDCR, RCC_BDCR_BDRST, 0); /* Restore backup-registers, except RTC related. */ - for (i = 0; i < STM32WL5_RTC_BKCOUNT; i++) + for (i = 0; i < STM32_RTC_BKCOUNT; i++) { - if (RTC_MAGIC_REG == STM32WL5_RTC_BKR(i)) + if (RTC_MAGIC_REG == STM32_RTC_BKR(i)) { continue; } - putreg32(bkregs[i], STM32WL5_RTC_BKR(i)); + putreg32(bkregs[i], STM32_RTC_BKR(i)); } - (void)stm32wl5_pwr_enablebkp(false); + (void)stm32_pwr_enablebkp(false); } } #else @@ -139,9 +139,9 @@ static inline void stm32wl5_rcc_resetbkp(void) * and enable peripheral clocking for all peripherals enabled in the NuttX * configuration file. * - * If CONFIG_ARCH_BOARD_STM32WL5_CUSTOM_CLOCKCONFIG is defined, then + * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then * clocking will be enabled by an externally provided, board-specific - * function called stm32wl5_board_clockconfig(). + * function called stm32_board_clockconfig(). * * Input Parameters * None @@ -151,7 +151,7 @@ static inline void stm32wl5_rcc_resetbkp(void) * ****************************************************************************/ -void stm32wl5_clockconfig(void) +void stm32_clockconfig(void) { #if 0 /* Make sure that we are starting in the reset state */ @@ -162,11 +162,11 @@ void stm32wl5_clockconfig(void) rcc_resetbkp(); #endif -#if defined(CONFIG_ARCH_BOARD_STM32WL5_CUSTOM_CLOCKCONFIG) +#if defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) /* Invoke Board Custom Clock Configuration */ - stm32wl5_board_clockconfig(); + stm32_board_clockconfig(); #else @@ -174,13 +174,13 @@ void stm32wl5_clockconfig(void) * board.h */ - stm32wl5_stdclockconfig(); + stm32_stdclockconfig(); #endif /* Enable peripheral clocking */ - stm32wl5_rcc_enableperipherals(); + stm32_rcc_enableperipherals(); } /**************************************************************************** @@ -191,7 +191,7 @@ void stm32wl5_clockconfig(void) * ****************************************************************************/ -static void stm32wl5_rcc_enableahb1(void) +static void stm32_rcc_enableahb1(void) { uint32_t regval; @@ -199,27 +199,27 @@ static void stm32wl5_rcc_enableahb1(void) * selected AHB1 peripherals. */ - regval = getreg32(STM32WL5_RCC_AHB1ENR); + regval = getreg32(STM32_RCC_AHB1ENR); -#ifdef CONFIG_STM32WL5_DMA1 +#ifdef CONFIG_STM32_DMA1 /* DMA 1 clock enable */ regval |= RCC_AHB1ENR_DMA1EN; #endif -#ifdef CONFIG_STM32WL5_DMA2 +#ifdef CONFIG_STM32_DMA2 /* DMA 2 clock enable */ regval |= RCC_AHB1ENR_DMA2EN; #endif -#ifdef CONFIG_STM32WL5_CRC +#ifdef CONFIG_STM32_CRC /* CRC clock enable */ regval |= RCC_AHB1ENR_CRCEN; #endif - putreg32(regval, STM32WL5_RCC_AHB1ENR); /* Enable peripherals */ + putreg32(regval, STM32_RCC_AHB1ENR); /* Enable peripherals */ } /**************************************************************************** @@ -230,7 +230,7 @@ static void stm32wl5_rcc_enableahb1(void) * ****************************************************************************/ -static inline void stm32wl5_rcc_enableahb2(void) +static inline void stm32_rcc_enableahb2(void) { uint32_t regval; @@ -238,25 +238,25 @@ static inline void stm32wl5_rcc_enableahb2(void) * selected AHB2 peripherals. */ - regval = getreg32(STM32WL5_RCC_AHB2ENR); + regval = getreg32(STM32_RCC_AHB2ENR); /* Enable GPIOA, GPIOB, .... GPIOH */ -#if STM32WL5_NPORTS > 0 +#if STM32_NPORTS > 0 regval |= (RCC_AHB2ENR_GPIOAEN -#if STM32WL5_NPORTS > 1 +#if STM32_NPORTS > 1 | RCC_AHB2ENR_GPIOBEN #endif -#if STM32WL5_NPORTS > 2 +#if STM32_NPORTS > 2 | RCC_AHB2ENR_GPIOCEN #endif -#if STM32WL5_NPORTS > 3 +#if STM32_NPORTS > 3 | RCC_AHB2ENR_GPIOHEN #endif ); -#endif /* STM32WL5_NPORTS */ +#endif /* STM32_NPORTS */ - putreg32(regval, STM32WL5_RCC_AHB2ENR); /* Enable peripherals */ + putreg32(regval, STM32_RCC_AHB2ENR); /* Enable peripherals */ } /**************************************************************************** @@ -267,7 +267,7 @@ static inline void stm32wl5_rcc_enableahb2(void) * ****************************************************************************/ -static inline void stm32wl5_rcc_enableahb3(void) +static inline void stm32_rcc_enableahb3(void) { uint32_t regval; @@ -275,33 +275,33 @@ static inline void stm32wl5_rcc_enableahb3(void) * selected AHB3 peripherals. */ - regval = getreg32(STM32WL5_RCC_AHB3ENR); + regval = getreg32(STM32_RCC_AHB3ENR); -#ifdef CONFIG_STM32WL5_AES +#ifdef CONFIG_STM32_AES /* Cryptographic modules clock enable */ regval |= RCC_AHB2ENR_AESEN; #endif -#ifdef CONFIG_STM32WL5_RNG +#ifdef CONFIG_STM32_RNG /* Random number generator clock enable */ regval |= RCC_AHB2ENR_RNGEN; #endif -#ifdef CONFIG_STM32WL5_FLASHEN +#ifdef CONFIG_STM32_FLASHEN /* Flash memory interface clock enable */ regval |= RCC_AHB3ENR_FLASHEN; #endif -#ifdef CONFIG_STM32WL5_IPCC +#ifdef CONFIG_STM32_IPCC /* IPCC interface clock enable */ regval |= RCC_AHB3ENR_IPCCEN; #endif - putreg32(regval, STM32WL5_RCC_AHB3ENR); /* Enable peripherals */ + putreg32(regval, STM32_RCC_AHB3ENR); /* Enable peripherals */ } /**************************************************************************** @@ -312,7 +312,7 @@ static inline void stm32wl5_rcc_enableahb3(void) * ****************************************************************************/ -static inline void stm32wl5_rcc_enableapb1(void) +static inline void stm32_rcc_enableapb1(void) { uint32_t regval; @@ -320,81 +320,81 @@ static inline void stm32wl5_rcc_enableapb1(void) * selected APB1 peripherals. */ - regval = getreg32(STM32WL5_RCC_APB1ENR1); + regval = getreg32(STM32_RCC_APB1ENR1); -#ifdef CONFIG_STM32WL5_TIM2 +#ifdef CONFIG_STM32_TIM2 /* TIM2 clock enable */ regval |= RCC_APB1ENR1_TIM2EN; #endif -#ifdef CONFIG_STM32WL5_SPI2 +#ifdef CONFIG_STM32_SPI2 /* SPI2 clock enable */ regval |= RCC_APB1ENR1_SPI2EN; #endif -#ifdef CONFIG_STM32WL5_USART2 +#ifdef CONFIG_STM32_USART2 /* USART 2 clock enable */ regval |= RCC_APB1ENR1_USART2EN; #endif -#ifdef CONFIG_STM32WL5_I2C1 +#ifdef CONFIG_STM32_I2C1 /* I2C1 clock enable */ regval |= RCC_APB1ENR1_I2C1EN; #endif -#ifdef CONFIG_STM32WL5_I2C2 +#ifdef CONFIG_STM32_I2C2 /* I2C2 clock enable */ regval |= RCC_APB1ENR1_I2C2EN; #endif -#ifdef CONFIG_STM32WL5_I2C3 +#ifdef CONFIG_STM32_I2C3 /* I2C3 clock enable */ regval |= RCC_APB1ENR1_I2C3EN; #endif -#if defined (CONFIG_STM32WL5_DAC1) +#if defined (CONFIG_STM32_DAC1) /* DAC interface clock enable */ regval |= RCC_APB1ENR1_DAC1EN; #endif -#ifdef CONFIG_STM32WL5_LPTIM1 +#ifdef CONFIG_STM32_LPTIM1 /* Low power timer 1 clock enable */ regval |= RCC_APB1ENR1_LPTIM1EN; #endif - putreg32(regval, STM32WL5_RCC_APB1ENR1); /* Enable peripherals */ + putreg32(regval, STM32_RCC_APB1ENR1); /* Enable peripherals */ /* Second APB1 register */ - regval = getreg32(STM32WL5_RCC_APB1ENR2); + regval = getreg32(STM32_RCC_APB1ENR2); -#ifdef CONFIG_STM32WL5_LPUART1 +#ifdef CONFIG_STM32_LPUART1 /* Low power uart clock enable */ regval |= RCC_APB1ENR2_LPUART1EN; #endif -#ifdef CONFIG_STM32WL5_LPTIM2 +#ifdef CONFIG_STM32_LPTIM2 /* Low power timer 2 clock enable */ regval |= RCC_APB1ENR2_LPTIM2EN; #endif -#ifdef CONFIG_STM32WL5_LPTIM3 +#ifdef CONFIG_STM32_LPTIM3 /* Low power timer 3 clock enable */ regval |= RCC_APB1ENR2_LPTIM3EN; #endif - putreg32(regval, STM32WL5_RCC_APB1ENR2); /* Enable peripherals */ + putreg32(regval, STM32_RCC_APB1ENR2); /* Enable peripherals */ } /**************************************************************************** @@ -405,7 +405,7 @@ static inline void stm32wl5_rcc_enableapb1(void) * ****************************************************************************/ -static inline void stm32wl5_rcc_enableapb2(void) +static inline void stm32_rcc_enableapb2(void) { uint32_t regval; @@ -413,45 +413,45 @@ static inline void stm32wl5_rcc_enableapb2(void) * selected APB2 peripherals. */ - regval = getreg32(STM32WL5_RCC_APB2ENR); + regval = getreg32(STM32_RCC_APB2ENR); -#if defined(CONFIG_STM32WL5_ADC1) +#if defined(CONFIG_STM32_ADC1) /* ADC clock enable */ regval |= RCC_AHB2ENR_ADC1EN; #endif -#ifdef CONFIG_STM32WL5_TIM1 +#ifdef CONFIG_STM32_TIM1 /* TIM1 clock enable */ regval |= RCC_APB2ENR_TIM1EN; #endif -#ifdef CONFIG_STM32WL5_SPI1 +#ifdef CONFIG_STM32_SPI1 /* SPI1 clock enable */ regval |= RCC_APB2ENR_SPI1EN; #endif -#ifdef CONFIG_STM32WL5_USART1 +#ifdef CONFIG_STM32_USART1 /* USART1 clock enable */ regval |= RCC_APB2ENR_USART1EN; #endif -#ifdef CONFIG_STM32WL5_TIM16 +#ifdef CONFIG_STM32_TIM16 /* TIM16 clock enable */ regval |= RCC_APB2ENR_TIM16EN; #endif -#ifdef CONFIG_STM32WL5_TIM17 +#ifdef CONFIG_STM32_TIM17 /* TIM16 clock enable */ regval |= RCC_APB2ENR_TIM17EN; #endif - putreg32(regval, STM32WL5_RCC_APB2ENR); /* Enable peripherals */ + putreg32(regval, STM32_RCC_APB2ENR); /* Enable peripherals */ } /**************************************************************************** @@ -462,7 +462,7 @@ static inline void stm32wl5_rcc_enableapb2(void) * ****************************************************************************/ -static inline void stm32wl5_rcc_enableccip(void) +static inline void stm32_rcc_enableccip(void) { uint32_t regval; @@ -471,42 +471,42 @@ static inline void stm32wl5_rcc_enableccip(void) * will at least have a clock. */ - regval = getreg32(STM32WL5_RCC_CCIPR); + regval = getreg32(STM32_RCC_CCIPR); -#if defined(STM32WL5_I2C_USE_HSI16) -#ifdef CONFIG_STM32WL5_I2C1 +#if defined(STM32_I2C_USE_HSI16) +#ifdef CONFIG_STM32_I2C1 /* Select HSI16 as I2C1 clock source. */ regval |= RCC_CCIPR_I2C1SEL_HSI; #endif -#ifdef CONFIG_STM32WL5_I2C2 +#ifdef CONFIG_STM32_I2C2 /* Select HSI16 as I2C2 clock source. */ regval |= RCC_CCIPR_I2C2SEL_HSI; #endif -#ifdef CONFIG_STM32WL5_I2C3 +#ifdef CONFIG_STM32_I2C3 /* Select HSI16 as I2C3 clock source. */ regval |= RCC_CCIPR_I2C3SEL_HSI; #endif -#endif /* STM32WL5_I2C_USE_HSI16 */ +#endif /* STM32_I2C_USE_HSI16 */ -#if defined(STM32WL5_USE_CLK48) +#if defined(STM32_USE_CLK48) /* XXX sanity if sdmmc1 or usb or rng, then we need to set the clk48 source - * and then we can also do away with STM32WL5_USE_CLK48, and give better + * and then we can also do away with STM32_USE_CLK48, and give better * warning messages. */ - regval |= STM32WL5_CLK48_SEL; + regval |= STM32_CLK48_SEL; #endif -#if defined(CONFIG_STM32WL5_ADC1) +#if defined(CONFIG_STM32_ADC1) /* Select SYSCLK as ADC clock source */ regval |= RCC_CCIPR_ADCSEL_SYSCLK; #endif -#ifdef CONFIG_STM32WL5_DFSDM1 +#ifdef CONFIG_STM32_DFSDM1 /* Select SYSCLK as DFSDM clock source */ /* RM0394 Rev 3, p. 525 is confused about DFSDM clock source. @@ -518,19 +518,19 @@ static inline void stm32wl5_rcc_enableccip(void) regval |= RCC_CCIPR_DFSDMSEL_SYSCLK; #endif - putreg32(regval, STM32WL5_RCC_CCIPR); + putreg32(regval, STM32_RCC_CCIPR); /* I2C4 alone has their clock selection in CCIPR2 register. */ -#if defined(STM32WL5_I2C_USE_HSI16) -#ifdef CONFIG_STM32WL5_I2C4 - regval = getreg32(STM32WL5_RCC_CCIPR2); +#if defined(STM32_I2C_USE_HSI16) +#ifdef CONFIG_STM32_I2C4 + regval = getreg32(STM32_RCC_CCIPR2); /* Select HSI16 as I2C4 clock source. */ regval |= RCC_CCIPR_I2C4SEL_HSI; - putreg32(regval, STM32WL5_RCC_CCIPR2); + putreg32(regval, STM32_RCC_CCIPR2); #endif #endif } @@ -545,12 +545,12 @@ static inline void stm32wl5_rcc_enableccip(void) * re-enable/re-start the PLL * * This function performs a subset of the operations performed by - * stm32wl5_clockconfig() + * stm32_clockconfig() * reset the currently enabled peripheral clocks. * - * If CONFIG_ARCH_BOARD_STM32WL5_CUSTOM_CLOCKCONFIG is defined, then + * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then * clocking will be enabled by an externally provided, board-specific - * function called stm32wl5_board_clockconfig(). + * function called stm32_board_clockconfig(). * * Input Parameters * None @@ -561,13 +561,13 @@ static inline void stm32wl5_rcc_enableccip(void) ****************************************************************************/ #ifdef CONFIG_PM -void stm32wl5_clockenable(void) +void stm32_clockenable(void) { -#if defined(CONFIG_ARCH_BOARD_STM32WL5_CUSTOM_CLOCKCONFIG) +#if defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) /* Invoke Board Custom Clock Configuration */ - stm32wl5_board_clockconfig(); + stm32_board_clockconfig(); #else @@ -575,28 +575,28 @@ void stm32wl5_clockenable(void) * board.h */ - stm32wl5_stdclockconfig(); + stm32_stdclockconfig(); #endif } #endif /**************************************************************************** - * Name: stm32wl5_rcc_enableperipherals + * Name: stm32_rcc_enableperipherals ****************************************************************************/ -void stm32wl5_rcc_enableperipherals(void) +void stm32_rcc_enableperipherals(void) { - stm32wl5_rcc_enableccip(); - stm32wl5_rcc_enableahb1(); - stm32wl5_rcc_enableahb2(); - stm32wl5_rcc_enableahb3(); - stm32wl5_rcc_enableapb1(); - stm32wl5_rcc_enableapb2(); + stm32_rcc_enableccip(); + stm32_rcc_enableahb1(); + stm32_rcc_enableahb2(); + stm32_rcc_enableahb3(); + stm32_rcc_enableapb1(); + stm32_rcc_enableapb2(); } /**************************************************************************** - * Name: stm32wl5_stdclockconfig + * Name: stm32_stdclockconfig * * Description: * Called to change to new clock based on settings in board.h @@ -605,17 +605,17 @@ void stm32wl5_rcc_enableperipherals(void) * power clocking modes! ****************************************************************************/ -#ifndef CONFIG_ARCH_BOARD_STM32WL5_CUSTOM_CLOCKCONFIG -void stm32wl5_stdclockconfig(void) +#ifndef CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG +void stm32_stdclockconfig(void) { uint32_t regval; -#if defined(STM32WL5_BOARD_USEHSI) || defined(STM32WL5_I2C_USE_HSI16) +#if defined(STM32_BOARD_USEHSI) || defined(STM32_I2C_USE_HSI16) /* Enable Internal High-Speed Clock (HSI) */ - regval = getreg32(STM32WL5_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_HSION; /* Enable HSI */ - putreg32(regval, STM32WL5_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Wait until the HSI is ready */ @@ -623,7 +623,7 @@ void stm32wl5_stdclockconfig(void) { /* Check if the HSIRDY flag is the set in the CR */ - if ((getreg32(STM32WL5_RCC_CR) & RCC_CR_HSIRDY) != 0) + if ((getreg32(STM32_RCC_CR) & RCC_CR_HSIRDY) != 0) { /* If so, then break-out */ @@ -632,17 +632,17 @@ void stm32wl5_stdclockconfig(void) } #endif -#if defined(STM32WL5_BOARD_USEHSI) +#if defined(STM32_BOARD_USEHSI) /* Already set above */ -#elif defined(STM32WL5_BOARD_USEMSI) +#elif defined(STM32_BOARD_USEMSI) /* Enable Internal Multi-Speed Clock (MSI) */ /* Wait until the MSI is either off or ready */ for (; ; ) { - if ((regval = getreg32(STM32WL5_RCC_CR)), + if ((regval = getreg32(STM32_RCC_CR)), (regval & RCC_CR_MSIRDY) || ~(regval & RCC_CR_MSION)) { /* If so, then break-out */ @@ -653,9 +653,9 @@ void stm32wl5_stdclockconfig(void) /* setting MSIRANGE */ - regval = getreg32(STM32WL5_RCC_CR); - regval |= (STM32WL5_BOARD_MSIRANGE | RCC_CR_MSION); /* Enable MSI and frequency */ - putreg32(regval, STM32WL5_RCC_CR); + regval = getreg32(STM32_RCC_CR); + regval |= (STM32_BOARD_MSIRANGE | RCC_CR_MSION); /* Enable MSI and frequency */ + putreg32(regval, STM32_RCC_CR); /* Wait until the MSI is ready */ @@ -663,7 +663,7 @@ void stm32wl5_stdclockconfig(void) { /* Check if the MSIRDY flag is the set in the CR */ - if ((getreg32(STM32WL5_RCC_CR) & RCC_CR_MSIRDY) != 0) + if ((getreg32(STM32_RCC_CR) & RCC_CR_MSIRDY) != 0) { /* If so, then break-out */ @@ -671,23 +671,23 @@ void stm32wl5_stdclockconfig(void) } } -#elif defined(STM32WL5_BOARD_USEHSE) +#elif defined(STM32_BOARD_USEHSE) /* Enable External High-Speed Clock (HSE) */ -#if defined(STM32WL5_BOARD_USETCXO) +#if defined(STM32_BOARD_USETCXO) /* nucleo-wl55jc uses TCXO crystal, which needs to be first * powered up with PB0 pin - or more conveniently by setting * HSEBYPPWR register. This has to be done before HSE is enabled */ - regval = getreg32(STM32WL5_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_HSEBYPPWR; - putreg32(regval, STM32WL5_RCC_CR); + putreg32(regval, STM32_RCC_CR); #endif - regval = getreg32(STM32WL5_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_HSEON; /* Enable HSE */ - putreg32(regval, STM32WL5_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Wait until the HSE is ready */ @@ -695,7 +695,7 @@ void stm32wl5_stdclockconfig(void) { /* Check if the HSERDY flag is the set in the CR */ - if ((getreg32(STM32WL5_RCC_CR) & RCC_CR_HSERDY) != 0) + if ((getreg32(STM32_RCC_CR) & RCC_CR_HSERDY) != 0) { /* If so, then break-out */ @@ -704,7 +704,7 @@ void stm32wl5_stdclockconfig(void) } #else -# error stm32wl5_stdclockconfig(), must have one of STM32WL5_BOARD_USEHSI, STM32WL5_BOARD_USEMSI, STM32WL5_BOARD_USEHSE defined +# error stm32_stdclockconfig(), must have one of STM32_BOARD_USEHSI, STM32_BOARD_USEMSI, STM32_BOARD_USEHSE defined #endif @@ -714,10 +714,10 @@ void stm32wl5_stdclockconfig(void) /* Select correct main regulator range */ - regval = getreg32(STM32WL5_PWR_CR1); + regval = getreg32(STM32_PWR_CR1); regval &= ~PWR_CR1_VOS_MASK; - if (STM32WL5_SYSCLK_FREQUENCY <= 16000000) + if (STM32_SYSCLK_FREQUENCY <= 16000000) { /* set low power range for frequencies <= 16MHz */ @@ -730,129 +730,129 @@ void stm32wl5_stdclockconfig(void) regval |= PWR_CR1_VOS_RANGE1; } - putreg32(regval, STM32WL5_PWR_CR1); + putreg32(regval, STM32_PWR_CR1); /* Wait for voltage regulator to stabilize */ - while (getreg32(STM32WL5_PWR_SR2) & PWR_SR2_VOSF) + while (getreg32(STM32_PWR_SR2) & PWR_SR2_VOSF) { } /* Set the HCLK source/divider */ - regval = getreg32(STM32WL5_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_HPRE_MASK; - regval |= STM32WL5_RCC_CFGR_HPRE; - putreg32(regval, STM32WL5_RCC_CFGR); + regval |= STM32_RCC_CFGR_HPRE; + putreg32(regval, STM32_RCC_CFGR); /* Set the PCLK2 divider */ - regval = getreg32(STM32WL5_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_PPRE2_MASK; - regval |= STM32WL5_RCC_CFGR_PPRE2; - putreg32(regval, STM32WL5_RCC_CFGR); + regval |= STM32_RCC_CFGR_PPRE2; + putreg32(regval, STM32_RCC_CFGR); /* Set the PCLK1 divider */ - regval = getreg32(STM32WL5_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_PPRE1_MASK; - regval |= STM32WL5_RCC_CFGR_PPRE1; - putreg32(regval, STM32WL5_RCC_CFGR); + regval |= STM32_RCC_CFGR_PPRE1; + putreg32(regval, STM32_RCC_CFGR); -#ifdef CONFIG_STM32WL5_RTC_HSECLOCK +#ifdef CONFIG_STM32_RTC_HSECLOCK /* Set the RTC clock divisor */ - regval = getreg32(STM32WL5_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_RTCPRE_MASK; regval |= RCC_CFGR_RTCPRE(HSE_DIVISOR); - putreg32(regval, STM32WL5_RCC_CFGR); + putreg32(regval, STM32_RCC_CFGR); #endif /* Set the PLL source and main divider */ - regval = getreg32(STM32WL5_RCC_PLLCFG); + regval = getreg32(STM32_RCC_PLLCFG); /* Configure Main PLL */ /* Set the PLL dividers and multipliers to configure the main PLL */ - regval = (STM32WL5_PLLCFG_PLLM | STM32WL5_PLLCFG_PLLN | - STM32WL5_PLLCFG_PLLP | STM32WL5_PLLCFG_PLLQ | - STM32WL5_PLLCFG_PLLR); + regval = (STM32_PLLCFG_PLLM | STM32_PLLCFG_PLLN | + STM32_PLLCFG_PLLP | STM32_PLLCFG_PLLQ | + STM32_PLLCFG_PLLR); -#ifdef STM32WL5_PLLCFG_PLLP_ENABLED +#ifdef STM32_PLLCFG_PLLP_ENABLED regval |= RCC_PLLCFG_PLLPEN; #endif -#ifdef STM32WL5_PLLCFG_PLLQ_ENABLED +#ifdef STM32_PLLCFG_PLLQ_ENABLED regval |= RCC_PLLCFG_PLLQEN; #endif -#ifdef STM32WL5_PLLCFG_PLLR_ENABLED +#ifdef STM32_PLLCFG_PLLR_ENABLED regval |= RCC_PLLCFG_PLLREN; #endif /* XXX The choice of clock source to PLL (all three) is independent - * of the sys clock source choice, review the STM32WL5_BOARD_USEHSI + * of the sys clock source choice, review the STM32_BOARD_USEHSI * name; probably split it into two, one for PLL source and one * for sys clock source. */ -#ifdef STM32WL5_BOARD_USEHSI +#ifdef STM32_BOARD_USEHSI regval |= RCC_PLLCFG_PLLSRC_HSI16; -#elif defined(STM32WL5_BOARD_USEMSI) +#elif defined(STM32_BOARD_USEMSI) regval |= RCC_PLLCFG_PLLSRC_MSI; -#else /* if STM32WL5_BOARD_USEHSE */ +#else /* if STM32_BOARD_USEHSE */ regval |= RCC_PLLCFG_PLLSRC_HSE; #endif - putreg32(regval, STM32WL5_RCC_PLLCFG); + putreg32(regval, STM32_RCC_PLLCFG); /* Enable the main PLL */ - regval = getreg32(STM32WL5_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_PLLON; - putreg32(regval, STM32WL5_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Wait until the PLL is ready */ - while ((getreg32(STM32WL5_RCC_CR) & RCC_CR_PLLRDY) == 0) + while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLRDY) == 0) { } /* Configure flash wait states according to manual */ - if (STM32WL5_HCLK3_FREQUENCY <= 18000000 /* 18MHz */) + if (STM32_HCLK3_FREQUENCY <= 18000000 /* 18MHz */) { regval = FLASH_ACR_LATENCY_0; } - else if (STM32WL5_HCLK3_FREQUENCY <= 36000000 /* 36MHz */) + else if (STM32_HCLK3_FREQUENCY <= 36000000 /* 36MHz */) { regval = FLASH_ACR_LATENCY_1; } - else /* STM32WL5_HCLK3_FREQUENCY <= 48MHz */ + else /* STM32_HCLK3_FREQUENCY <= 48MHz */ { regval = FLASH_ACR_LATENCY_2; } - putreg32(regval, STM32WL5_FLASH_ACR); + putreg32(regval, STM32_FLASH_ACR); /* Select the main PLL as system clock source */ - regval = getreg32(STM32WL5_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_SW_MASK; regval |= RCC_CFGR_SW_PLL; - putreg32(regval, STM32WL5_RCC_CFGR); + putreg32(regval, STM32_RCC_CFGR); /* Wait until the PLL source is used as the system clock source */ - while ((getreg32(STM32WL5_RCC_CFGR) & RCC_CFGR_SWS_MASK) != + while ((getreg32(STM32_RCC_CFGR) & RCC_CFGR_SWS_MASK) != RCC_CFGR_SWS_PLL) { } -#if defined(CONFIG_STM32WL5_IWDG) || defined(CONFIG_STM32WL5_RTC_LSICLOCK) +#if defined(CONFIG_STM32_IWDG) || defined(CONFIG_STM32_RTC_LSICLOCK) /* Low speed internal clock source LSI */ - stm32wl5_rcc_enablelsi(); + stm32_rcc_enablelsi(); #endif } #endif diff --git a/arch/arm/src/stm32wl5/stm32wl5_rcc.h b/arch/arm/src/stm32wl5/stm32wl5_rcc.h index 1989f237afd61..5b1cd5dc7ef67 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_rcc.h +++ b/arch/arm/src/stm32wl5/stm32wl5_rcc.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32WL5_STM32WL5_RCC_H -#define __ARCH_ARM_SRC_STM32WL5_STM32WL5_RCC_H +#ifndef __ARCH_ARM_SRC_STM32WL5_STM32_RCC_H +#define __ARCH_ARM_SRC_STM32WL5_STM32_RCC_H /**************************************************************************** * Included Files @@ -54,7 +54,7 @@ extern "C" ****************************************************************************/ /**************************************************************************** - * Name: stm32wl5_mcoconfig + * Name: stm32_mcoconfig * * Description: * Selects the clock source to output on MC pin (PA8) for stm32wl562xx @@ -71,16 +71,16 @@ extern "C" * ****************************************************************************/ -static inline void stm32wl5_mcoconfig(uint32_t source) +static inline void stm32_mcoconfig(uint32_t source) { uint32_t regval; /* Set MCO source */ - regval = getreg32(STM32WL5_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~(RCC_CFGR_MCOSEL_MASK); regval |= (source & RCC_CFGR_MCOSEL_MASK); - putreg32(regval, STM32WL5_RCC_CFGR); + putreg32(regval, STM32_RCC_CFGR); } /**************************************************************************** @@ -88,7 +88,7 @@ static inline void stm32wl5_mcoconfig(uint32_t source) ****************************************************************************/ /**************************************************************************** - * Name: stm32wl5_clockconfig + * Name: stm32_clockconfig * * Description: * Called to establish the clock settings based on the values in board.h. @@ -96,9 +96,9 @@ static inline void stm32wl5_mcoconfig(uint32_t source) * and enable peripheral clocking for all periperipherals enabled in the * NuttX configuration file. * - * If CONFIG_ARCH_BOARD_STM32WL5_CUSTOM_CLOCKCONFIG is defined, then + * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then * clocking will be enabled by an externally provided, board-specific - * function called stm32wl5_board_clockconfig(). + * function called stm32_board_clockconfig(). * * Input Parameters: * None @@ -108,10 +108,10 @@ static inline void stm32wl5_mcoconfig(uint32_t source) * ****************************************************************************/ -void stm32wl5_clockconfig(void); +void stm32_clockconfig(void); /**************************************************************************** - * Name: stm32wl5_board_clockconfig + * Name: stm32_board_clockconfig * * Description: * Any STM32WL5 board may replace the "standard" board clock configuration @@ -119,12 +119,12 @@ void stm32wl5_clockconfig(void); * ****************************************************************************/ -#ifdef CONFIG_ARCH_BOARD_STM32WL5_CUSTOM_CLOCKCONFIG -void stm32wl5_board_clockconfig(void); +#ifdef CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG +void stm32_board_clockconfig(void); #endif /**************************************************************************** - * Name: stm32wl5_stdclockconfig + * Name: stm32_stdclockconfig * * Description: * The standard logic to configure the clocks based on settings in board.h. @@ -134,12 +134,12 @@ void stm32wl5_board_clockconfig(void); * ****************************************************************************/ -#ifndef CONFIG_ARCH_BOARD_STM32WL5_CUSTOM_CLOCKCONFIG -void stm32wl5_stdclockconfig(void); +#ifndef CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG +void stm32_stdclockconfig(void); #endif /**************************************************************************** - * Name: stm32wl5_clockenable + * Name: stm32_clockenable * * Description: * Re-enable the clock and restore the clock settings based on settings in @@ -148,12 +148,12 @@ void stm32wl5_stdclockconfig(void); * re-enable/re-start the PLL * * This function performs a subset of the operations performed by - * stm32wl5_clockconfig(): It does not reset any devices, and it does not + * stm32_clockconfig(): It does not reset any devices, and it does not * reset the currently enabled peripheral clocks. * - * If CONFIG_ARCH_BOARD_STM32WL5_CUSTOM_CLOCKCONFIG is defined, then + * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then * clocking will be enabled by an externally provided, board-specific - * function called stm32wl5_board_clockconfig(). + * function called stm32_board_clockconfig(). * * Input Parameters: * None @@ -164,11 +164,11 @@ void stm32wl5_stdclockconfig(void); ****************************************************************************/ #ifdef CONFIG_PM -void stm32wl5_clockenable(void); +void stm32_clockenable(void); #endif /**************************************************************************** - * Name: stm32wl5_rcc_enablelse + * Name: stm32_rcc_enablelse * * Description: * Enable the External Low-Speed (LSE) Oscillator. @@ -181,30 +181,30 @@ void stm32wl5_clockenable(void); * ****************************************************************************/ -void stm32wl5_rcc_enablelse(void); +void stm32_rcc_enablelse(void); /**************************************************************************** - * Name: stm32wl5_rcc_enablelsi + * Name: stm32_rcc_enablelsi * * Description: * Enable the Internal Low-Speed (LSI) RC Oscillator. * ****************************************************************************/ -void stm32wl5_rcc_enablelsi(void); +void stm32_rcc_enablelsi(void); /**************************************************************************** - * Name: stm32wl5_rcc_disablelsi + * Name: stm32_rcc_disablelsi * * Description: * Disable the Internal Low-Speed (LSI) RC Oscillator. * ****************************************************************************/ -void stm32wl5_rcc_disablelsi(void); +void stm32_rcc_disablelsi(void); /**************************************************************************** - * Name: stm32wl5_rcc_enableperipherals + * Name: stm32_rcc_enableperipherals * * Description: * Enable all the chip peripherals according to configuration. This is @@ -213,11 +213,11 @@ void stm32wl5_rcc_disablelsi(void); * ****************************************************************************/ -void stm32wl5_rcc_enableperipherals(void); +void stm32_rcc_enableperipherals(void); #undef EXTERN #if defined(__cplusplus) } #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32WL5_STM32WL5_RCC_H */ +#endif /* __ARCH_ARM_SRC_STM32WL5_STM32_RCC_H */ diff --git a/arch/arm/src/stm32wl5/stm32wl5_serial.c b/arch/arm/src/stm32wl5/stm32wl5_serial.c index 524483ef5cbe1..757055353331c 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_serial.c +++ b/arch/arm/src/stm32wl5/stm32wl5_serial.c @@ -82,8 +82,8 @@ */ # if defined(CONFIG_USART2_RXDMA) -# if !defined(CONFIG_STM32WL5_DMA1) && !defined(CONFIG_STM32WL5_DMAMUX) -# error STM32WL5 USART2/3 receive DMA requires CONFIG_STM32WL5_DMA1 +# if !defined(CONFIG_STM32_DMA1) && !defined(CONFIG_STM32_DMAMUX) +# error STM32WL5 USART2/3 receive DMA requires CONFIG_STM32_DMA1 # endif # endif @@ -98,7 +98,7 @@ /* UART2-5 have no alternate channels without DMAMUX */ -# ifndef CONFIG_STM32WL5_HAVE_DMAMUX +# ifndef CONFIG_STM32_HAVE_DMAMUX # define DMAMAP_USART2_RX DMACHAN_USART2_RX # endif @@ -116,11 +116,11 @@ * can be individually invalidated. */ -# if !defined(CONFIG_STM32WL5_SERIAL_RXDMA_BUFFER_SIZE) || \ - CONFIG_STM32WL5_SERIAL_RXDMA_BUFFER_SIZE == 0 +# if !defined(CONFIG_STM32_SERIAL_RXDMA_BUFFER_SIZE) || \ + CONFIG_STM32_SERIAL_RXDMA_BUFFER_SIZE == 0 # define RXDMA_BUFFER_SIZE 32 # else -# define RXDMA_BUFFER_SIZE ((CONFIG_STM32WL5_SERIAL_RXDMA_BUFFER_SIZE + 31) & ~31) +# define RXDMA_BUFFER_SIZE ((CONFIG_STM32_SERIAL_RXDMA_BUFFER_SIZE + 31) & ~31) # endif /* DMA priority */ @@ -152,8 +152,8 @@ /* Power management definitions */ -#if defined(CONFIG_PM) && !defined(CONFIG_STM32WL5_PM_SERIAL_ACTIVITY) -# define CONFIG_STM32WL5_PM_SERIAL_ACTIVITY 10 +#if defined(CONFIG_PM) && !defined(CONFIG_STM32_PM_SERIAL_ACTIVITY) +# define CONFIG_STM32_PM_SERIAL_ACTIVITY 10 #endif #if defined(CONFIG_PM) # define PM_IDLE_DOMAIN 0 /* Revisit */ @@ -170,7 +170,7 @@ * See stm32wl5serial_restoreusartint where the masking is done. */ -#ifdef CONFIG_STM32WL5_SERIALBRK_BSDCOMPAT +#ifdef CONFIG_STM32_SERIALBRK_BSDCOMPAT # define USART_CR1_IE_BREAK_INPROGRESS_SHFTS 15 # define USART_CR1_IE_BREAK_INPROGRESS (1 << USART_CR1_IE_BREAK_INPROGRESS_SHFTS) #endif @@ -182,7 +182,7 @@ * Private Types ****************************************************************************/ -struct stm32wl5_serial_s +struct stm32_serial_s { struct uart_dev_s dev; /* Generic UART device */ uint16_t ie; /* Saved interrupt mask bits value */ @@ -297,9 +297,9 @@ static int stm32wl5serial_dmasetup(struct uart_dev_s *dev); static void stm32wl5serial_dmashutdown(struct uart_dev_s *dev); static int stm32wl5serial_dmareceive(struct uart_dev_s *dev, unsigned int *status); -static void stm32wl5serial_dmareenable(struct stm32wl5_serial_s *priv); +static void stm32wl5serial_dmareenable(struct stm32_serial_s *priv); #ifdef CONFIG_SERIAL_IFLOWCONTROL -static bool stm32wl5serial_dmaiflowrestart(struct stm32wl5_serial_s *priv); +static bool stm32wl5serial_dmaiflowrestart(struct stm32_serial_s *priv); #endif static void stm32wl5serial_dmarxint(struct uart_dev_s *dev, bool enable); static bool stm32wl5serial_dmarxavailable(struct uart_dev_s *dev); @@ -366,7 +366,7 @@ static const struct uart_ops_s g_uart_dma_ops = /* I/O buffers */ -#ifdef CONFIG_STM32WL5_LPUART1_SERIALDRIVER +#ifdef CONFIG_STM32_LPUART1_SERIALDRIVER static char g_lpuart1rxbuffer[CONFIG_LPUART1_RXBUFSIZE]; static char g_lpuart1txbuffer[CONFIG_LPUART1_TXBUFSIZE]; # ifdef CONFIG_LPUART1_RXDMA @@ -374,7 +374,7 @@ static char g_lpuart1rxfifo[RXDMA_BUFFER_SIZE]; # endif #endif -#ifdef CONFIG_STM32WL5_USART1_SERIALDRIVER +#ifdef CONFIG_STM32_USART1_SERIALDRIVER static char g_usart1rxbuffer[CONFIG_USART1_RXBUFSIZE]; static char g_usart1txbuffer[CONFIG_USART1_TXBUFSIZE]; # ifdef CONFIG_USART1_RXDMA @@ -382,7 +382,7 @@ static char g_usart1rxfifo[RXDMA_BUFFER_SIZE]; # endif #endif -#ifdef CONFIG_STM32WL5_USART2_SERIALDRIVER +#ifdef CONFIG_STM32_USART2_SERIALDRIVER static char g_usart2rxbuffer[CONFIG_USART2_RXBUFSIZE]; static char g_usart2txbuffer[CONFIG_USART2_TXBUFSIZE]; # ifdef CONFIG_USART2_RXDMA @@ -392,8 +392,8 @@ static char g_usart2rxfifo[RXDMA_BUFFER_SIZE]; /* This describes the state of the STM32 USART1 ports. */ -#ifdef CONFIG_STM32WL5_LPUART1_SERIALDRIVER -static struct stm32wl5_serial_s g_lpuart1priv = +#ifdef CONFIG_STM32_LPUART1_SERIALDRIVER +static struct stm32_serial_s g_lpuart1priv = { .dev = { @@ -418,13 +418,13 @@ static struct stm32wl5_serial_s g_lpuart1priv = .priv = &g_lpuart1priv, }, - .irq = STM32WL5_IRQ_LPUART1, + .irq = STM32_IRQ_LPUART1, .parity = CONFIG_LPUART1_PARITY, .bits = CONFIG_LPUART1_BITS, .stopbits2 = CONFIG_LPUART1_2STOP, .baud = CONFIG_LPUART1_BAUD, - .apbclock = STM32WL5_PCLK2_FREQUENCY, - .usartbase = STM32WL5_LPUART1_BASE, + .apbclock = STM32_PCLK2_FREQUENCY, + .usartbase = STM32_LPUART1_BASE, .tx_gpio = GPIO_LPUART1_TX, .rx_gpio = GPIO_LPUART1_RX, # if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_LPUART1_OFLOWCONTROL) @@ -452,8 +452,8 @@ static struct stm32wl5_serial_s g_lpuart1priv = }; #endif -#ifdef CONFIG_STM32WL5_USART1_SERIALDRIVER -static struct stm32wl5_serial_s g_usart1priv = +#ifdef CONFIG_STM32_USART1_SERIALDRIVER +static struct stm32_serial_s g_usart1priv = { .dev = { @@ -478,13 +478,13 @@ static struct stm32wl5_serial_s g_usart1priv = .priv = &g_usart1priv, }, - .irq = STM32WL5_IRQ_USART1, + .irq = STM32_IRQ_USART1, .parity = CONFIG_USART1_PARITY, .bits = CONFIG_USART1_BITS, .stopbits2 = CONFIG_USART1_2STOP, .baud = CONFIG_USART1_BAUD, - .apbclock = STM32WL5_PCLK2_FREQUENCY, - .usartbase = STM32WL5_USART1_BASE, + .apbclock = STM32_PCLK2_FREQUENCY, + .usartbase = STM32_USART1_BASE, .tx_gpio = GPIO_USART1_TX, .rx_gpio = GPIO_USART1_RX, # if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_USART1_OFLOWCONTROL) @@ -514,8 +514,8 @@ static struct stm32wl5_serial_s g_usart1priv = /* This describes the state of the STM32 USART2 port. */ -#ifdef CONFIG_STM32WL5_USART2_SERIALDRIVER -static struct stm32wl5_serial_s g_usart2priv = +#ifdef CONFIG_STM32_USART2_SERIALDRIVER +static struct stm32_serial_s g_usart2priv = { .dev = { @@ -540,13 +540,13 @@ static struct stm32wl5_serial_s g_usart2priv = .priv = &g_usart2priv, }, - .irq = STM32WL5_IRQ_USART2, + .irq = STM32_IRQ_USART2, .parity = CONFIG_USART2_PARITY, .bits = CONFIG_USART2_BITS, .stopbits2 = CONFIG_USART2_2STOP, .baud = CONFIG_USART2_BAUD, - .apbclock = STM32WL5_PCLK1_FREQUENCY, - .usartbase = STM32WL5_USART2_BASE, + .apbclock = STM32_PCLK1_FREQUENCY, + .usartbase = STM32_USART2_BASE, .tx_gpio = GPIO_USART2_TX, .rx_gpio = GPIO_USART2_RX, # if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_USART2_OFLOWCONTROL) @@ -576,16 +576,16 @@ static struct stm32wl5_serial_s g_usart2priv = /* This table lets us iterate over the configured USARTs */ -static struct stm32wl5_serial_s * const - g_uart_devs[STM32WL5_NLPUART + STM32WL5_NUSART] = +static struct stm32_serial_s * const + g_uart_devs[STM32_NLPUART + STM32_NUSART] = { -#ifdef CONFIG_STM32WL5_LPUART1_SERIALDRIVER +#ifdef CONFIG_STM32_LPUART1_SERIALDRIVER [0] = &g_lpuart1priv, #endif -#ifdef CONFIG_STM32WL5_USART1_SERIALDRIVER +#ifdef CONFIG_STM32_USART1_SERIALDRIVER [1] = &g_usart1priv, #endif -#ifdef CONFIG_STM32WL5_USART2_SERIALDRIVER +#ifdef CONFIG_STM32_USART2_SERIALDRIVER [2] = &g_usart2priv, #endif }; @@ -614,7 +614,7 @@ static struct serialpm_s g_serialpm = ****************************************************************************/ static inline -uint32_t stm32wl5serial_getreg(struct stm32wl5_serial_s *priv, int offset) +uint32_t stm32wl5serial_getreg(struct stm32_serial_s *priv, int offset) { return getreg32(priv->usartbase + offset); } @@ -624,7 +624,7 @@ uint32_t stm32wl5serial_getreg(struct stm32wl5_serial_s *priv, int offset) ****************************************************************************/ static inline -void stm32wl5serial_putreg(struct stm32wl5_serial_s *priv, +void stm32wl5serial_putreg(struct stm32_serial_s *priv, int offset, uint32_t value) { putreg32(value, priv->usartbase + offset); @@ -635,7 +635,7 @@ void stm32wl5serial_putreg(struct stm32wl5_serial_s *priv, ****************************************************************************/ static inline -void stm32wl5serial_setusartint(struct stm32wl5_serial_s *priv, uint16_t ie) +void stm32wl5serial_setusartint(struct stm32_serial_s *priv, uint16_t ie) { uint32_t cr; @@ -647,22 +647,22 @@ void stm32wl5serial_setusartint(struct stm32wl5_serial_s *priv, uint16_t ie) * above) */ - cr = stm32wl5serial_getreg(priv, STM32WL5_USART_CR1_OFFSET); + cr = stm32wl5serial_getreg(priv, STM32_USART_CR1_OFFSET); cr &= ~(USART_CR1_USED_INTS); cr |= (ie & (USART_CR1_USED_INTS)); - stm32wl5serial_putreg(priv, STM32WL5_USART_CR1_OFFSET, cr); + stm32wl5serial_putreg(priv, STM32_USART_CR1_OFFSET, cr); - cr = stm32wl5serial_getreg(priv, STM32WL5_USART_CR3_OFFSET); + cr = stm32wl5serial_getreg(priv, STM32_USART_CR3_OFFSET); cr &= ~USART_CR3_EIE; cr |= (ie & USART_CR3_EIE); - stm32wl5serial_putreg(priv, STM32WL5_USART_CR3_OFFSET, cr); + stm32wl5serial_putreg(priv, STM32_USART_CR3_OFFSET, cr); } /**************************************************************************** * Name: up_restoreusartint ****************************************************************************/ -static void stm32wl5serial_restoreusartint(struct stm32wl5_serial_s *priv, +static void stm32wl5serial_restoreusartint(struct stm32_serial_s *priv, uint16_t ie) { irqstate_t flags; @@ -678,7 +678,7 @@ static void stm32wl5serial_restoreusartint(struct stm32wl5_serial_s *priv, * Name: stm32wl5serial_disableusartint ****************************************************************************/ -static void stm32wl5serial_disableusartint(struct stm32wl5_serial_s *priv, +static void stm32wl5serial_disableusartint(struct stm32_serial_s *priv, uint16_t *ie) { irqstate_t flags; @@ -710,8 +710,8 @@ static void stm32wl5serial_disableusartint(struct stm32wl5_serial_s *priv, * USART_CR3_CTSIE USART_ISR_CTS CTS flag (not used) */ - cr1 = stm32wl5serial_getreg(priv, STM32WL5_USART_CR1_OFFSET); - cr3 = stm32wl5serial_getreg(priv, STM32WL5_USART_CR3_OFFSET); + cr1 = stm32wl5serial_getreg(priv, STM32_USART_CR1_OFFSET); + cr3 = stm32wl5serial_getreg(priv, STM32_USART_CR3_OFFSET); /* Return the current interrupt mask value for the used interrupts. * Notice that this depends on the fact that none of the used interrupt @@ -739,11 +739,11 @@ static void stm32wl5serial_disableusartint(struct stm32wl5_serial_s *priv, ****************************************************************************/ #ifdef SERIAL_HAVE_DMA -static int stm32wl5serial_dmanextrx(struct stm32wl5_serial_s *priv) +static int stm32wl5serial_dmanextrx(struct stm32_serial_s *priv) { size_t dmaresidual; - dmaresidual = stm32wl5_dmaresidual(priv->rxdma); + dmaresidual = stm32_dmaresidual(priv->rxdma); return (RXDMA_BUFFER_SIZE - (int)dmaresidual); } @@ -760,8 +760,8 @@ static int stm32wl5serial_dmanextrx(struct stm32wl5_serial_s *priv) #ifndef CONFIG_SUPPRESS_UART_CONFIG static void stm32wl5serial_setformat(struct uart_dev_s *dev) { - struct stm32wl5_serial_s *priv = - (struct stm32wl5_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; uint32_t regval; /* This first implementation is for U[S]ARTs that support oversampling @@ -772,7 +772,7 @@ static void stm32wl5serial_setformat(struct uart_dev_s *dev) uint32_t cr1; uint32_t brr; - if (priv->usartbase == STM32WL5_LPUART1_BASE) + if (priv->usartbase == STM32_LPUART1_BASE) { /* lpuart has different calculations baudrate, and there is not * oversampling: @@ -804,7 +804,7 @@ static void stm32wl5serial_setformat(struct uart_dev_s *dev) * But what is small? */ - cr1 = stm32wl5serial_getreg(priv, STM32WL5_USART_CR1_OFFSET); + cr1 = stm32wl5serial_getreg(priv, STM32_USART_CR1_OFFSET); if (usartdiv8 > 2000) { /* Use usartdiv16 */ @@ -828,14 +828,14 @@ static void stm32wl5serial_setformat(struct uart_dev_s *dev) cr1 |= USART_CR1_OVER8; } - stm32wl5serial_putreg(priv, STM32WL5_USART_CR1_OFFSET, cr1); + stm32wl5serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1); } - stm32wl5serial_putreg(priv, STM32WL5_USART_BRR_OFFSET, brr); + stm32wl5serial_putreg(priv, STM32_USART_BRR_OFFSET, brr); /* Configure parity mode */ - regval = stm32wl5serial_getreg(priv, STM32WL5_USART_CR1_OFFSET); + regval = stm32wl5serial_getreg(priv, STM32_USART_CR1_OFFSET); regval &= ~(USART_CR1_PCE | USART_CR1_PS | USART_CR1_M0 | USART_CR1_M1); if (priv->parity == 1) /* Odd parity */ @@ -873,11 +873,11 @@ static void stm32wl5serial_setformat(struct uart_dev_s *dev) * 1 start, 8 data (no parity), n stop. */ - stm32wl5serial_putreg(priv, STM32WL5_USART_CR1_OFFSET, regval); + stm32wl5serial_putreg(priv, STM32_USART_CR1_OFFSET, regval); /* Configure STOP bits */ - regval = stm32wl5serial_getreg(priv, STM32WL5_USART_CR2_OFFSET); + regval = stm32wl5serial_getreg(priv, STM32_USART_CR2_OFFSET); regval &= ~(USART_CR2_STOP_MASK); if (priv->stopbits2) @@ -885,14 +885,14 @@ static void stm32wl5serial_setformat(struct uart_dev_s *dev) regval |= USART_CR2_STOP2; } - stm32wl5serial_putreg(priv, STM32WL5_USART_CR2_OFFSET, regval); + stm32wl5serial_putreg(priv, STM32_USART_CR2_OFFSET, regval); /* Configure hardware flow control */ - regval = stm32wl5serial_getreg(priv, STM32WL5_USART_CR3_OFFSET); + regval = stm32wl5serial_getreg(priv, STM32_USART_CR3_OFFSET); regval &= ~(USART_CR3_CTSE | USART_CR3_RTSE); -#if defined(CONFIG_SERIAL_IFLOWCONTROL) && !defined(CONFIG_STM32WL5_FLOWCONTROL_BROKEN) +#if defined(CONFIG_SERIAL_IFLOWCONTROL) && !defined(CONFIG_STM32_FLOWCONTROL_BROKEN) if (priv->iflow && (priv->rts_gpio != 0)) { regval |= USART_CR3_RTSE; @@ -906,7 +906,7 @@ static void stm32wl5serial_setformat(struct uart_dev_s *dev) } #endif - stm32wl5serial_putreg(priv, STM32WL5_USART_CR3_OFFSET, regval); + stm32wl5serial_putreg(priv, STM32_USART_CR3_OFFSET, regval); } #endif /* CONFIG_SUPPRESS_UART_CONFIG */ @@ -921,7 +921,7 @@ static void stm32wl5serial_setformat(struct uart_dev_s *dev) #ifdef CONFIG_PM static void stm32wl5serial_setsuspend(struct uart_dev_s *dev, bool suspend) { - struct stm32wl5_serial_s *priv = (struct stm32wl5_serial_s *)dev->priv; + struct stm32_serial_s *priv = (struct stm32_serial_s *)dev->priv; #ifdef SERIAL_HAVE_DMA bool dmarestored = false; #endif @@ -940,7 +940,7 @@ static void stm32wl5serial_setsuspend(struct uart_dev_s *dev, bool suspend) { /* Force RTS high to prevent further Rx. */ - stm32wl5_configgpio((priv->rts_gpio & ~GPIO_MODE_MASK) + stm32_configgpio((priv->rts_gpio & ~GPIO_MODE_MASK) | (GPIO_OUTPUT | GPIO_OUTPUT_SET)); } #endif @@ -951,7 +951,7 @@ static void stm32wl5serial_setsuspend(struct uart_dev_s *dev, bool suspend) /* Wait last Tx to complete. */ - while ((stm32wl5serial_getreg(priv, STM32WL5_USART_ISR_OFFSET) & + while ((stm32wl5serial_getreg(priv, STM32_USART_ISR_OFFSET) & USART_ISR_TC) == 0); #ifdef SERIAL_HAVE_DMA @@ -969,7 +969,7 @@ static void stm32wl5serial_setsuspend(struct uart_dev_s *dev, bool suspend) { /* Suspend Rx DMA. */ - stm32wl5_dmastop(priv->rxdma); + stm32_dmastop(priv->rxdma); priv->rxdmasusp = true; } } @@ -1010,7 +1010,7 @@ static void stm32wl5serial_setsuspend(struct uart_dev_s *dev, bool suspend) { /* Restore peripheral RTS control. */ - stm32wl5_configgpio(priv->rts_gpio); + stm32_configgpio(priv->rts_gpio); } #endif } @@ -1057,9 +1057,9 @@ static void stm32wl5serial_pm_setsuspend(bool suspend) g_serialpm.serial_suspended = suspend; - for (n = 0; n < STM32WL5_NLPUART + STM32WL5_NUSART; n++) + for (n = 0; n < STM32_NLPUART + STM32_NUSART; n++) { - struct stm32wl5_serial_s *priv = g_uart_devs[n]; + struct stm32_serial_s *priv = g_uart_devs[n]; if (!priv || !priv->initialized) { @@ -1085,8 +1085,8 @@ static void stm32wl5serial_pm_setsuspend(bool suspend) static void stm32wl5serial_setapbclock(struct uart_dev_s *dev, bool on) { - struct stm32wl5_serial_s *priv = - (struct stm32wl5_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; uint32_t rcc_en; uint32_t regaddr; @@ -1096,22 +1096,22 @@ static void stm32wl5serial_setapbclock(struct uart_dev_s *dev, bool on) { default: return; -#ifdef CONFIG_STM32WL5_LPUART1_SERIALDRIVER - case STM32WL5_LPUART1_BASE: +#ifdef CONFIG_STM32_LPUART1_SERIALDRIVER + case STM32_LPUART1_BASE: rcc_en = RCC_APB1ENR2_LPUART1EN; - regaddr = STM32WL5_RCC_APB1ENR2; + regaddr = STM32_RCC_APB1ENR2; break; #endif -#ifdef CONFIG_STM32WL5_USART1_SERIALDRIVER - case STM32WL5_USART1_BASE: +#ifdef CONFIG_STM32_USART1_SERIALDRIVER + case STM32_USART1_BASE: rcc_en = RCC_APB2ENR_USART1EN; - regaddr = STM32WL5_RCC_APB2ENR; + regaddr = STM32_RCC_APB2ENR; break; #endif -#ifdef CONFIG_STM32WL5_USART2_SERIALDRIVER - case STM32WL5_USART2_BASE: +#ifdef CONFIG_STM32_USART2_SERIALDRIVER + case STM32_USART2_BASE: rcc_en = RCC_APB1ENR1_USART2EN; - regaddr = STM32WL5_RCC_APB1ENR1; + regaddr = STM32_RCC_APB1ENR1; break; #endif } @@ -1139,14 +1139,14 @@ static void stm32wl5serial_setapbclock(struct uart_dev_s *dev, bool on) static int stm32wl5serial_setup(struct uart_dev_s *dev) { - struct stm32wl5_serial_s *priv = - (struct stm32wl5_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; #ifndef CONFIG_SUPPRESS_UART_CONFIG uint32_t regval; /* Note: The logic here depends on the fact that that the USART module - * was enabled in stm32wl5_lowsetup(). + * was enabled in stm32_lowsetup(). */ /* Enable USART APB1/2 clock */ @@ -1157,18 +1157,18 @@ static int stm32wl5serial_setup(struct uart_dev_s *dev) if (priv->tx_gpio != 0) { - stm32wl5_configgpio(priv->tx_gpio); + stm32_configgpio(priv->tx_gpio); } if (priv->rx_gpio != 0) { - stm32wl5_configgpio(priv->rx_gpio); + stm32_configgpio(priv->rx_gpio); } #ifdef CONFIG_SERIAL_OFLOWCONTROL if (priv->cts_gpio != 0) { - stm32wl5_configgpio(priv->cts_gpio); + stm32_configgpio(priv->cts_gpio); } #endif @@ -1177,20 +1177,20 @@ static int stm32wl5serial_setup(struct uart_dev_s *dev) { uint32_t config = priv->rts_gpio; -#ifdef CONFIG_STM32WL5_FLOWCONTROL_BROKEN +#ifdef CONFIG_STM32_FLOWCONTROL_BROKEN /* Instead of letting hw manage this pin, we will bitbang */ config = (config & ~GPIO_MODE_MASK) | GPIO_OUTPUT; #endif - stm32wl5_configgpio(config); + stm32_configgpio(config); } #endif #ifdef HAVE_RS485 if (priv->rs485_dir_gpio != 0) { - stm32wl5_configgpio(priv->rs485_dir_gpio); - stm32wl5_gpiowrite(priv->rs485_dir_gpio, !priv->rs485_dir_polarity); + stm32_configgpio(priv->rs485_dir_gpio); + stm32_gpiowrite(priv->rs485_dir_gpio, !priv->rs485_dir_polarity); } #endif @@ -1198,7 +1198,7 @@ static int stm32wl5serial_setup(struct uart_dev_s *dev) /* Clear STOP, CLKEN, CPOL, CPHA, LBCL, and interrupt enable bits */ - regval = stm32wl5serial_getreg(priv, STM32WL5_USART_CR2_OFFSET); + regval = stm32wl5serial_getreg(priv, STM32_USART_CR2_OFFSET); regval &= ~(USART_CR2_STOP_MASK | USART_CR2_CLKEN | USART_CR2_CPOL | USART_CR2_CPHA | USART_CR2_LBCL | USART_CR2_LBDIE); @@ -1209,26 +1209,26 @@ static int stm32wl5serial_setup(struct uart_dev_s *dev) regval |= USART_CR2_STOP2; } - stm32wl5serial_putreg(priv, STM32WL5_USART_CR2_OFFSET, regval); + stm32wl5serial_putreg(priv, STM32_USART_CR2_OFFSET, regval); /* Configure CR1 */ /* Clear TE, REm and all interrupt enable bits */ - regval = stm32wl5serial_getreg(priv, STM32WL5_USART_CR1_OFFSET); + regval = stm32wl5serial_getreg(priv, STM32_USART_CR1_OFFSET); regval &= ~(USART_CR1_TE | USART_CR1_RE | USART_CR1_ALLINTS); - stm32wl5serial_putreg(priv, STM32WL5_USART_CR1_OFFSET, regval); + stm32wl5serial_putreg(priv, STM32_USART_CR1_OFFSET, regval); /* Configure CR3 */ /* Clear CTSE, RTSE, and all interrupt enable bits */ - regval = stm32wl5serial_getreg(priv, STM32WL5_USART_CR3_OFFSET); + regval = stm32wl5serial_getreg(priv, STM32_USART_CR3_OFFSET); regval &= ~(USART_CR3_CTSIE | USART_CR3_CTSE | USART_CR3_RTSE | USART_CR3_EIE); - stm32wl5serial_putreg(priv, STM32WL5_USART_CR3_OFFSET, regval); + stm32wl5serial_putreg(priv, STM32_USART_CR3_OFFSET, regval); /* Configure the USART line format and speed. */ @@ -1236,9 +1236,9 @@ static int stm32wl5serial_setup(struct uart_dev_s *dev) /* Enable Rx, Tx, and the USART */ - regval = stm32wl5serial_getreg(priv, STM32WL5_USART_CR1_OFFSET); + regval = stm32wl5serial_getreg(priv, STM32_USART_CR1_OFFSET); regval |= (USART_CR1_UE | USART_CR1_TE | USART_CR1_RE); - stm32wl5serial_putreg(priv, STM32WL5_USART_CR1_OFFSET, regval); + stm32wl5serial_putreg(priv, STM32_USART_CR1_OFFSET, regval); #endif /* CONFIG_SUPPRESS_UART_CONFIG */ @@ -1265,8 +1265,8 @@ static int stm32wl5serial_setup(struct uart_dev_s *dev) #ifdef SERIAL_HAVE_DMA static int stm32wl5serial_dmasetup(struct uart_dev_s *dev) { - struct stm32wl5_serial_s *priv = - (struct stm32wl5_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; int result; uint32_t regval; @@ -1283,15 +1283,15 @@ static int stm32wl5serial_dmasetup(struct uart_dev_s *dev) /* Acquire the DMA channel. This should always succeed. */ - priv->rxdma = stm32wl5_dmachannel(priv->rxdma_channel); + priv->rxdma = stm32_dmachannel(priv->rxdma_channel); #ifdef CONFIG_SERIAL_IFLOWCONTROL if (priv->iflow) { /* Configure for non-circular DMA reception into the RX FIFO */ - stm32wl5_dmasetup(priv->rxdma, - priv->usartbase + STM32WL5_USART_RDR_OFFSET, + stm32_dmasetup(priv->rxdma, + priv->usartbase + STM32_USART_RDR_OFFSET, (uint32_t)priv->rxfifo, RXDMA_BUFFER_SIZE, SERIAL_DMA_IFLOW_CONTROL_WORD); @@ -1301,8 +1301,8 @@ static int stm32wl5serial_dmasetup(struct uart_dev_s *dev) { /* Configure for circular DMA reception into the RX FIFO */ - stm32wl5_dmasetup(priv->rxdma, - priv->usartbase + STM32WL5_USART_RDR_OFFSET, + stm32_dmasetup(priv->rxdma, + priv->usartbase + STM32_USART_RDR_OFFSET, (uint32_t)priv->rxfifo, RXDMA_BUFFER_SIZE, SERIAL_DMA_CONTROL_WORD); @@ -1316,9 +1316,9 @@ static int stm32wl5serial_dmasetup(struct uart_dev_s *dev) /* Enable receive DMA for the UART */ - regval = stm32wl5serial_getreg(priv, STM32WL5_USART_CR3_OFFSET); + regval = stm32wl5serial_getreg(priv, STM32_USART_CR3_OFFSET); regval |= USART_CR3_DMAR; - stm32wl5serial_putreg(priv, STM32WL5_USART_CR3_OFFSET, regval); + stm32wl5serial_putreg(priv, STM32_USART_CR3_OFFSET, regval); #ifdef CONFIG_SERIAL_IFLOWCONTROL if (priv->iflow) @@ -1328,7 +1328,7 @@ static int stm32wl5serial_dmasetup(struct uart_dev_s *dev) * in and DMA transfer is stopped. */ - stm32wl5_dmastart(priv->rxdma, stm32wl5serial_dmarxcallback, + stm32_dmastart(priv->rxdma, stm32wl5serial_dmarxcallback, (void *)priv, false); } else @@ -1339,7 +1339,7 @@ static int stm32wl5serial_dmasetup(struct uart_dev_s *dev) * worth of time to claim bytes before they are overwritten. */ - stm32wl5_dmastart(priv->rxdma, stm32wl5serial_dmarxcallback, + stm32_dmastart(priv->rxdma, stm32wl5serial_dmarxcallback, (void *)priv, true); } @@ -1358,8 +1358,8 @@ static int stm32wl5serial_dmasetup(struct uart_dev_s *dev) static void stm32wl5serial_shutdown(struct uart_dev_s *dev) { - struct stm32wl5_serial_s *priv = - (struct stm32wl5_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; uint32_t regval; /* Mark device as uninitialized. */ @@ -1376,9 +1376,9 @@ static void stm32wl5serial_shutdown(struct uart_dev_s *dev) /* Disable Rx, Tx, and the UART */ - regval = stm32wl5serial_getreg(priv, STM32WL5_USART_CR1_OFFSET); + regval = stm32wl5serial_getreg(priv, STM32_USART_CR1_OFFSET); regval &= ~(USART_CR1_UE | USART_CR1_TE | USART_CR1_RE); - stm32wl5serial_putreg(priv, STM32WL5_USART_CR1_OFFSET, regval); + stm32wl5serial_putreg(priv, STM32_USART_CR1_OFFSET, regval); /* Release pins. "If the serial-attached device is powered down, the TX * pin causes back-powering, potentially confusing the device to the point @@ -1390,32 +1390,32 @@ static void stm32wl5serial_shutdown(struct uart_dev_s *dev) if (priv->tx_gpio != 0) { - stm32wl5_unconfiggpio(priv->tx_gpio); + stm32_unconfiggpio(priv->tx_gpio); } if (priv->rx_gpio != 0) { - stm32wl5_unconfiggpio(priv->rx_gpio); + stm32_unconfiggpio(priv->rx_gpio); } #ifdef CONFIG_SERIAL_OFLOWCONTROL if (priv->cts_gpio != 0) { - stm32wl5_unconfiggpio(priv->cts_gpio); + stm32_unconfiggpio(priv->cts_gpio); } #endif #ifdef CONFIG_SERIAL_IFLOWCONTROL if (priv->rts_gpio != 0) { - stm32wl5_unconfiggpio(priv->rts_gpio); + stm32_unconfiggpio(priv->rts_gpio); } #endif #ifdef HAVE_RS485 if (priv->rs485_dir_gpio != 0) { - stm32wl5_unconfiggpio(priv->rs485_dir_gpio); + stm32_unconfiggpio(priv->rs485_dir_gpio); } #endif } @@ -1432,8 +1432,8 @@ static void stm32wl5serial_shutdown(struct uart_dev_s *dev) #ifdef SERIAL_HAVE_DMA static void stm32wl5serial_dmashutdown(struct uart_dev_s *dev) { - struct stm32wl5_serial_s *priv = - (struct stm32wl5_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; /* Perform the normal UART shutdown */ @@ -1441,11 +1441,11 @@ static void stm32wl5serial_dmashutdown(struct uart_dev_s *dev) /* Stop the DMA channel */ - stm32wl5_dmastop(priv->rxdma); + stm32_dmastop(priv->rxdma); /* Release the DMA channel */ - stm32wl5_dmafree(priv->rxdma); + stm32_dmafree(priv->rxdma); priv->rxdma = NULL; } #endif @@ -1468,8 +1468,8 @@ static void stm32wl5serial_dmashutdown(struct uart_dev_s *dev) static int stm32wl5serial_attach(struct uart_dev_s *dev) { - struct stm32wl5_serial_s *priv = - (struct stm32wl5_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; int ret; /* Attach and enable the IRQ */ @@ -1500,8 +1500,8 @@ static int stm32wl5serial_attach(struct uart_dev_s *dev) static void stm32wl5serial_detach(struct uart_dev_s *dev) { - struct stm32wl5_serial_s *priv = - (struct stm32wl5_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; up_disable_irq(priv->irq); irq_detach(priv->irq); } @@ -1521,7 +1521,7 @@ static void stm32wl5serial_detach(struct uart_dev_s *dev) static int stm32wl5serial_interrupt(int irq, void *context, void *arg) { - struct stm32wl5_serial_s *priv = (struct stm32wl5_serial_s *)arg; + struct stm32_serial_s *priv = (struct stm32_serial_s *)arg; int passes; bool handled; @@ -1529,8 +1529,8 @@ static int stm32wl5serial_interrupt(int irq, void *context, /* Report serial activity to the power management logic */ -#if defined(CONFIG_PM) && CONFIG_STM32WL5_PM_SERIAL_ACTIVITY > 0 - pm_activity(PM_IDLE_DOMAIN, CONFIG_STM32WL5_PM_SERIAL_ACTIVITY); +#if defined(CONFIG_PM) && CONFIG_STM32_PM_SERIAL_ACTIVITY > 0 + pm_activity(PM_IDLE_DOMAIN, CONFIG_STM32_PM_SERIAL_ACTIVITY); #endif /* Loop until there are no characters to be transferred or, @@ -1544,7 +1544,7 @@ static int stm32wl5serial_interrupt(int irq, void *context, /* Get the masked USART status word. */ - priv->sr = stm32wl5serial_getreg(priv, STM32WL5_USART_ISR_OFFSET); + priv->sr = stm32wl5serial_getreg(priv, STM32_USART_ISR_OFFSET); /* USART interrupts: * @@ -1581,7 +1581,7 @@ static int stm32wl5serial_interrupt(int irq, void *context, (priv->ie & USART_CR1_TCIE) != 0 && (priv->ie & USART_CR1_TXEIE) == 0) { - stm32wl5_gpiowrite(priv->rs485_dir_gpio, + stm32_gpiowrite(priv->rs485_dir_gpio, !priv->rs485_dir_polarity); stm32wl5serial_restoreusartint(priv, priv->ie & ~USART_CR1_TCIE); } @@ -1612,7 +1612,7 @@ static int stm32wl5serial_interrupt(int irq, void *context, * interrupt clear register (ICR). */ - stm32wl5serial_putreg(priv, STM32WL5_USART_ICR_OFFSET, + stm32wl5serial_putreg(priv, STM32_USART_ICR_OFFSET, (USART_ICR_NCF | USART_ICR_ORECF | USART_ICR_FECF)); } @@ -1648,8 +1648,8 @@ static int stm32wl5serial_ioctl(struct file *filep, int cmd, struct uart_dev_s *dev = inode->i_private; #endif #if defined(CONFIG_SERIAL_TERMIOS) - struct stm32wl5_serial_s *priv = - (struct stm32wl5_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; #endif int ret = OK; @@ -1658,9 +1658,9 @@ static int stm32wl5serial_ioctl(struct file *filep, int cmd, #ifdef CONFIG_SERIAL_TIOCSERGSTRUCT case TIOCSERGSTRUCT: { - struct stm32wl5_serial_s *user; + struct stm32_serial_s *user; - user = (struct stm32wl5_serial_s *)arg; + user = (struct stm32_serial_s *)arg; if (!user) { @@ -1668,13 +1668,13 @@ static int stm32wl5serial_ioctl(struct file *filep, int cmd, } else { - memcpy(user, dev, sizeof(struct stm32wl5_serial_s)); + memcpy(user, dev, sizeof(struct stm32_serial_s)); } } break; #endif -#ifdef CONFIG_STM32WL5_USART_SINGLEWIRE +#ifdef CONFIG_STM32_USART_SINGLEWIRE case TIOCSSINGLEWIRE: { uint32_t cr1; @@ -1685,19 +1685,19 @@ static int stm32wl5serial_ioctl(struct file *filep, int cmd, /* Get the original state of UE */ - cr1 = stm32wl5serial_getreg(priv, STM32WL5_USART_CR1_OFFSET); + cr1 = stm32wl5serial_getreg(priv, STM32_USART_CR1_OFFSET); cr1_ue = cr1 & USART_CR1_UE; cr1 &= ~USART_CR1_UE; /* Disable UE, HDSEL can only be written when UE=0 */ - stm32wl5serial_putreg(priv, STM32WL5_USART_CR1_OFFSET, cr1); + stm32wl5serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1); /* Change the TX port to be open-drain/push-pull and enable/disable * half-duplex mode. */ - uint32_t cr = stm32wl5serial_getreg(priv, STM32WL5_USART_CR3_OFFSET); + uint32_t cr = stm32wl5serial_getreg(priv, STM32_USART_CR3_OFFSET); if ((arg & SER_SINGLEWIRE_ENABLED) != 0) { @@ -1723,7 +1723,7 @@ static int stm32wl5serial_ioctl(struct file *filep, int cmd, if (priv->tx_gpio != 0) { - stm32wl5_configgpio((priv->tx_gpio & + stm32_configgpio((priv->tx_gpio & ~(GPIO_PUPD_MASK | GPIO_OPENDRAIN)) | gpio_val); } @@ -1734,7 +1734,7 @@ static int stm32wl5serial_ioctl(struct file *filep, int cmd, { if (priv->tx_gpio != 0) { - stm32wl5_configgpio((priv->tx_gpio & + stm32_configgpio((priv->tx_gpio & ~(GPIO_PUPD_MASK | GPIO_OPENDRAIN)) | GPIO_PUSHPULL); } @@ -1742,17 +1742,17 @@ static int stm32wl5serial_ioctl(struct file *filep, int cmd, cr &= ~USART_CR3_HDSEL; } - stm32wl5serial_putreg(priv, STM32WL5_USART_CR3_OFFSET, cr); + stm32wl5serial_putreg(priv, STM32_USART_CR3_OFFSET, cr); /* Re-enable UE if appropriate */ - stm32wl5serial_putreg(priv, STM32WL5_USART_CR1_OFFSET, cr1 | cr1_ue); + stm32wl5serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1 | cr1_ue); leave_critical_section(flags); } break; #endif -#ifdef CONFIG_STM32WL5_USART_INVERT +#ifdef CONFIG_STM32_USART_INVERT case TIOCSINVERT: { uint32_t cr1; @@ -1763,17 +1763,17 @@ static int stm32wl5serial_ioctl(struct file *filep, int cmd, /* Get the original state of UE */ - cr1 = stm32wl5serial_getreg(priv, STM32WL5_USART_CR1_OFFSET); + cr1 = stm32wl5serial_getreg(priv, STM32_USART_CR1_OFFSET); cr1_ue = cr1 & USART_CR1_UE; cr1 &= ~USART_CR1_UE; /* Disable UE, {R,T}XINV can only be written when UE=0 */ - stm32wl5serial_putreg(priv, STM32WL5_USART_CR1_OFFSET, cr1); + stm32wl5serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1); /* Enable/disable signal inversion. */ - uint32_t cr = stm32wl5serial_getreg(priv, STM32WL5_USART_CR2_OFFSET); + uint32_t cr = stm32wl5serial_getreg(priv, STM32_USART_CR2_OFFSET); if (arg & SER_INVERT_ENABLED_RX) { @@ -1793,17 +1793,17 @@ static int stm32wl5serial_ioctl(struct file *filep, int cmd, cr &= ~USART_CR2_TXINV; } - stm32wl5serial_putreg(priv, STM32WL5_USART_CR2_OFFSET, cr); + stm32wl5serial_putreg(priv, STM32_USART_CR2_OFFSET, cr); /* Re-enable UE if appropriate */ - stm32wl5serial_putreg(priv, STM32WL5_USART_CR1_OFFSET, cr1 | cr1_ue); + stm32wl5serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1 | cr1_ue); leave_critical_section(flags); } break; #endif -#ifdef CONFIG_STM32WL5_USART_SWAP +#ifdef CONFIG_STM32_USART_SWAP case TIOCSSWAP: { uint32_t cr1; @@ -1814,17 +1814,17 @@ static int stm32wl5serial_ioctl(struct file *filep, int cmd, /* Get the original state of UE */ - cr1 = stm32wl5serial_getreg(priv, STM32WL5_USART_CR1_OFFSET); + cr1 = stm32wl5serial_getreg(priv, STM32_USART_CR1_OFFSET); cr1_ue = cr1 & USART_CR1_UE; cr1 &= ~USART_CR1_UE; /* Disable UE, SWAP can only be written when UE=0 */ - stm32wl5serial_putreg(priv, STM32WL5_USART_CR1_OFFSET, cr1); + stm32wl5serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1); /* Enable/disable Swap mode. */ - uint32_t cr = stm32wl5serial_getreg(priv, STM32WL5_USART_CR2_OFFSET); + uint32_t cr = stm32wl5serial_getreg(priv, STM32_USART_CR2_OFFSET); if (arg == SER_SWAP_ENABLED) { @@ -1835,11 +1835,11 @@ static int stm32wl5serial_ioctl(struct file *filep, int cmd, cr &= ~USART_CR2_SWAP; } - stm32wl5serial_putreg(priv, STM32WL5_USART_CR2_OFFSET, cr); + stm32wl5serial_putreg(priv, STM32_USART_CR2_OFFSET, cr); /* Re-enable UE if appropriate */ - stm32wl5serial_putreg(priv, STM32WL5_USART_CR1_OFFSET, cr1 | cr1_ue); + stm32wl5serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1 | cr1_ue); leave_critical_section(flags); } break; @@ -1940,8 +1940,8 @@ static int stm32wl5serial_ioctl(struct file *filep, int cmd, break; #endif /* CONFIG_SERIAL_TERMIOS */ -#ifdef CONFIG_STM32WL5_USART_BREAKS -# ifdef CONFIG_STM32WL5_SERIALBRK_BSDCOMPAT +#ifdef CONFIG_STM32_USART_BREAKS +# ifdef CONFIG_STM32_SERIALBRK_BSDCOMPAT case TIOCSBRK: /* BSD compatibility: Turn break on, unconditionally */ { irqstate_t flags; @@ -1960,7 +1960,7 @@ static int stm32wl5serial_ioctl(struct file *filep, int cmd, { uint32_t tx_break = GPIO_OUTPUT | (~(GPIO_MODE_MASK | GPIO_OUTPUT_SET) & priv->tx_gpio); - stm32wl5_configgpio(tx_break); + stm32_configgpio(tx_break); } leave_critical_section(flags); @@ -1977,7 +1977,7 @@ static int stm32wl5serial_ioctl(struct file *filep, int cmd, if (priv->tx_gpio != 0) { - stm32wl5_configgpio(priv->tx_gpio); + stm32_configgpio(priv->tx_gpio); } priv->ie &= ~USART_CR1_IE_BREAK_INPROGRESS; @@ -1996,8 +1996,8 @@ static int stm32wl5serial_ioctl(struct file *filep, int cmd, irqstate_t flags; flags = enter_critical_section(); - cr1 = stm32wl5serial_getreg(priv, STM32WL5_USART_CR1_OFFSET); - stm32wl5serial_putreg(priv, STM32WL5_USART_CR1_OFFSET, + cr1 = stm32wl5serial_getreg(priv, STM32_USART_CR1_OFFSET); + stm32wl5serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1 | USART_CR1_SBK); leave_critical_section(flags); } @@ -2009,8 +2009,8 @@ static int stm32wl5serial_ioctl(struct file *filep, int cmd, irqstate_t flags; flags = enter_critical_section(); - cr1 = stm32wl5serial_getreg(priv, STM32WL5_USART_CR1_OFFSET); - stm32wl5serial_putreg(priv, STM32WL5_USART_CR1_OFFSET, + cr1 = stm32wl5serial_getreg(priv, STM32_USART_CR1_OFFSET); + stm32wl5serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1 & ~USART_CR1_SBK); leave_critical_section(flags); } @@ -2040,13 +2040,13 @@ static int stm32wl5serial_ioctl(struct file *filep, int cmd, static int stm32wl5serial_receive(struct uart_dev_s *dev, unsigned int *status) { - struct stm32wl5_serial_s *priv = - (struct stm32wl5_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; uint32_t rdr; /* Get the Rx byte */ - rdr = stm32wl5serial_getreg(priv, STM32WL5_USART_RDR_OFFSET); + rdr = stm32wl5serial_getreg(priv, STM32_USART_RDR_OFFSET); /* Get the Rx byte plux error information. Return those in status */ @@ -2070,8 +2070,8 @@ static int stm32wl5serial_receive(struct uart_dev_s *dev, #ifndef SERIAL_HAVE_ONLY_DMA static void stm32wl5serial_rxint(struct uart_dev_s *dev, bool enable) { - struct stm32wl5_serial_s *priv = - (struct stm32wl5_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; irqstate_t flags; uint16_t ie; @@ -2130,10 +2130,10 @@ static void stm32wl5serial_rxint(struct uart_dev_s *dev, bool enable) #ifndef SERIAL_HAVE_ONLY_DMA static bool stm32wl5serial_rxavailable(struct uart_dev_s *dev) { - struct stm32wl5_serial_s *priv = - (struct stm32wl5_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; - return ((stm32wl5serial_getreg(priv, STM32WL5_USART_ISR_OFFSET) & + return ((stm32wl5serial_getreg(priv, STM32_USART_ISR_OFFSET) & USART_ISR_RXNE) != 0); } #endif @@ -2165,16 +2165,16 @@ static bool stm32wl5serial_rxavailable(struct uart_dev_s *dev) static bool stm32wl5serial_rxflowcontrol(struct uart_dev_s *dev, unsigned int nbuffered, bool upper) { - struct stm32wl5_serial_s *priv = - (struct stm32wl5_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; #if defined(CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS) && \ - defined(CONFIG_STM32WL5_FLOWCONTROL_BROKEN) + defined(CONFIG_STM32_FLOWCONTROL_BROKEN) if (priv->iflow && (priv->rts_gpio != 0)) { /* Assert/de-assert nRTS set it high resume/stop sending */ - stm32wl5_gpiowrite(priv->rts_gpio, upper); + stm32_gpiowrite(priv->rts_gpio, upper); if (upper) { @@ -2249,8 +2249,8 @@ static bool stm32wl5serial_rxflowcontrol(struct uart_dev_s *dev, static int stm32wl5serial_dmareceive(struct uart_dev_s *dev, unsigned int *status) { - struct stm32wl5_serial_s *priv = - (struct stm32wl5_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; int c = 0; if (stm32wl5serial_dmanextrx(priv) != priv->rxdmanext) @@ -2288,15 +2288,15 @@ static int stm32wl5serial_dmareceive(struct uart_dev_s *dev, ****************************************************************************/ #if defined(SERIAL_HAVE_DMA) -static void stm32wl5serial_dmareenable(struct stm32wl5_serial_s *priv) +static void stm32wl5serial_dmareenable(struct stm32_serial_s *priv) { #ifdef CONFIG_SERIAL_IFLOWCONTROL if (priv->iflow) { /* Configure for non-circular DMA reception into the RX FIFO */ - stm32wl5_dmasetup(priv->rxdma, - priv->usartbase + STM32WL5_USART_RDR_OFFSET, + stm32_dmasetup(priv->rxdma, + priv->usartbase + STM32_USART_RDR_OFFSET, (uint32_t)priv->rxfifo, RXDMA_BUFFER_SIZE, SERIAL_DMA_IFLOW_CONTROL_WORD); @@ -2306,8 +2306,8 @@ static void stm32wl5serial_dmareenable(struct stm32wl5_serial_s *priv) { /* Configure for circular DMA reception into the RX FIFO */ - stm32wl5_dmasetup(priv->rxdma, - priv->usartbase + STM32WL5_USART_RDR_OFFSET, + stm32_dmasetup(priv->rxdma, + priv->usartbase + STM32_USART_RDR_OFFSET, (uint32_t)priv->rxfifo, RXDMA_BUFFER_SIZE, SERIAL_DMA_CONTROL_WORD); @@ -2327,7 +2327,7 @@ static void stm32wl5serial_dmareenable(struct stm32wl5_serial_s *priv) * in and DMA transfer is stopped. */ - stm32wl5_dmastart(priv->rxdma, stm32wl5serial_dmarxcallback, + stm32_dmastart(priv->rxdma, stm32wl5serial_dmarxcallback, (void *)priv, false); } else @@ -2338,7 +2338,7 @@ static void stm32wl5serial_dmareenable(struct stm32wl5_serial_s *priv) * worth of time to claim bytes before they are overwritten. */ - stm32wl5_dmastart(priv->rxdma, stm32wl5serial_dmarxcallback, + stm32_dmastart(priv->rxdma, stm32wl5serial_dmarxcallback, (void *)priv, true); } @@ -2359,7 +2359,7 @@ static void stm32wl5serial_dmareenable(struct stm32wl5_serial_s *priv) ****************************************************************************/ #if defined(SERIAL_HAVE_DMA) && defined(CONFIG_SERIAL_IFLOWCONTROL) -static bool stm32wl5serial_dmaiflowrestart(struct stm32wl5_serial_s *priv) +static bool stm32wl5serial_dmaiflowrestart(struct stm32_serial_s *priv) { if (!priv->rxenable) { @@ -2410,8 +2410,8 @@ static bool stm32wl5serial_dmaiflowrestart(struct stm32wl5_serial_s *priv) #ifdef SERIAL_HAVE_DMA static void stm32wl5serial_dmarxint(struct uart_dev_s *dev, bool enable) { - struct stm32wl5_serial_s *priv = - (struct stm32wl5_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; /* En/disable DMA reception. * @@ -2445,8 +2445,8 @@ static void stm32wl5serial_dmarxint(struct uart_dev_s *dev, bool enable) #ifdef SERIAL_HAVE_DMA static bool stm32wl5serial_dmarxavailable(struct uart_dev_s *dev) { - struct stm32wl5_serial_s *priv = - (struct stm32wl5_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; /* Compare our receive pointer to the current DMA pointer, if they * do not match, then there are bytes to be received. @@ -2466,17 +2466,17 @@ static bool stm32wl5serial_dmarxavailable(struct uart_dev_s *dev) static void stm32wl5serial_send(struct uart_dev_s *dev, int ch) { - struct stm32wl5_serial_s *priv = - (struct stm32wl5_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; #ifdef HAVE_RS485 if (priv->rs485_dir_gpio != 0) { - stm32wl5_gpiowrite(priv->rs485_dir_gpio, priv->rs485_dir_polarity); + stm32_gpiowrite(priv->rs485_dir_gpio, priv->rs485_dir_polarity); } #endif - stm32wl5serial_putreg(priv, STM32WL5_USART_TDR_OFFSET, (uint32_t)ch); + stm32wl5serial_putreg(priv, STM32_USART_TDR_OFFSET, (uint32_t)ch); } /**************************************************************************** @@ -2489,8 +2489,8 @@ static void stm32wl5serial_send(struct uart_dev_s *dev, int ch) static void stm32wl5serial_txint(struct uart_dev_s *dev, bool enable) { - struct stm32wl5_serial_s *priv = - (struct stm32wl5_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; irqstate_t flags; /* USART transmit interrupts: @@ -2521,7 +2521,7 @@ static void stm32wl5serial_txint(struct uart_dev_s *dev, bool enable) } # endif -# ifdef CONFIG_STM32WL5_SERIALBRK_BSDCOMPAT +# ifdef CONFIG_STM32_SERIALBRK_BSDCOMPAT if (priv->ie & USART_CR1_IE_BREAK_INPROGRESS) { leave_critical_section(flags); @@ -2558,10 +2558,10 @@ static void stm32wl5serial_txint(struct uart_dev_s *dev, bool enable) static bool stm32wl5serial_txready(struct uart_dev_s *dev) { - struct stm32wl5_serial_s *priv = - (struct stm32wl5_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; - return ((stm32wl5serial_getreg(priv, STM32WL5_USART_ISR_OFFSET) & + return ((stm32wl5serial_getreg(priv, STM32_USART_ISR_OFFSET) & USART_ISR_TXE) != 0); } @@ -2578,7 +2578,7 @@ static bool stm32wl5serial_txready(struct uart_dev_s *dev) static void stm32wl5serial_dmarxcallback(DMA_HANDLE handle, uint8_t status, void *arg) { - struct stm32wl5_serial_s *priv = (struct stm32wl5_serial_s *)arg; + struct stm32_serial_s *priv = (struct stm32_serial_s *)arg; if (priv->rxenable && stm32wl5serial_dmarxavailable(&priv->dev)) { @@ -2603,11 +2603,11 @@ static void stm32wl5serial_dmarxcallback(DMA_HANDLE handle, uint8_t status, * will release Rx DMA. */ - priv->sr = stm32wl5serial_getreg(priv, STM32WL5_USART_ISR_OFFSET); + priv->sr = stm32wl5serial_getreg(priv, STM32_USART_ISR_OFFSET); if ((priv->sr & (USART_ISR_ORE | USART_ISR_NF | USART_ISR_FE)) != 0) { - stm32wl5serial_putreg(priv, STM32WL5_USART_ICR_OFFSET, + stm32wl5serial_putreg(priv, STM32_USART_ICR_OFFSET, (USART_ICR_NCF | USART_ICR_ORECF | USART_ICR_FECF)); } @@ -2736,16 +2736,16 @@ static int stm32wl5serial_pmprepare(struct pm_callback_s *cb, int domain, * buffers. */ - stm32wl5_serial_dma_poll(); + stm32_serial_dma_poll(); #endif /* Check if any of the active ports have data pending on Tx/Rx * buffers. */ - for (n = 0; n < STM32WL5_NLPUART + STM32WL5_NUSART; n++) + for (n = 0; n < STM32_NLPUART + STM32_NUSART; n++) { - struct stm32wl5_serial_s *priv = g_uart_devs[n]; + struct stm32_serial_s *priv = g_uart_devs[n]; if (!priv || !priv->initialized) { @@ -2813,7 +2813,7 @@ void arm_earlyserialinit(void) /* Disable all USART interrupts */ - for (i = 0; i < STM32WL5_NLPUART + STM32WL5_NUSART; i++) + for (i = 0; i < STM32_NLPUART + STM32_NUSART; i++) { if (g_uart_devs[i]) { @@ -2862,7 +2862,7 @@ void arm_serialinit(void) #if CONSOLE_UART > 0 (void)uart_register("/dev/console", &g_uart_devs[CONSOLE_UART - 1]->dev); -#ifndef CONFIG_STM32WL5_SERIAL_DISABLE_REORDERING +#ifndef CONFIG_STM32_SERIAL_DISABLE_REORDERING /* If not disabled, register the console UART to ttyS0 and exclude * it from initializing it further down */ @@ -2882,7 +2882,7 @@ void arm_serialinit(void) strlcpy(devname, "/dev/ttySx", sizeof(devname)); - for (i = 0; i < STM32WL5_NLPUART + STM32WL5_NUSART; i++) + for (i = 0; i < STM32_NLPUART + STM32_NUSART; i++) { /* Don't create a device for non-configured ports. */ @@ -2891,7 +2891,7 @@ void arm_serialinit(void) continue; } -#ifndef CONFIG_STM32WL5_SERIAL_DISABLE_REORDERING +#ifndef CONFIG_STM32_SERIAL_DISABLE_REORDERING /* Don't create a device for the console - we did that above */ if (g_uart_devs[i]->dev.isconsole) @@ -2909,7 +2909,7 @@ void arm_serialinit(void) } /**************************************************************************** - * Name: stm32wl5_serial_dma_poll + * Name: stm32_serial_dma_poll * * Description: * Checks receive DMA buffers for received bytes that have not accumulated @@ -2920,7 +2920,7 @@ void arm_serialinit(void) ****************************************************************************/ #ifdef SERIAL_HAVE_DMA -void stm32wl5_serial_dma_poll(void) +void stm32_serial_dma_poll(void) { irqstate_t flags; @@ -2962,7 +2962,7 @@ void stm32wl5_serial_dma_poll(void) void up_putc(int ch) { #if CONSOLE_UART > 0 - struct stm32wl5_serial_s *priv = g_uart_devs[CONSOLE_UART - 1]; + struct stm32_serial_s *priv = g_uart_devs[CONSOLE_UART - 1]; uint16_t ie; stm32wl5serial_disableusartint(priv, &ie); diff --git a/arch/arm/src/stm32wl5/stm32wl5_spi.c b/arch/arm/src/stm32wl5/stm32wl5_spi.c index 3aa45fe20c4f2..9c7f0008af69b 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_spi.c +++ b/arch/arm/src/stm32wl5/stm32wl5_spi.c @@ -21,22 +21,22 @@ ****************************************************************************/ /**************************************************************************** - * The external functions, stm32wl5_spi1/2select and stm32wl5_spi1/2status + * The external functions, stm32_spi1/2select and stm32_spi1/2status * must be provided by board-specific logic. They are implementations of the * select and status methods of the SPI interface defined by struct spi_ops_s * (see include/nuttx/spi/spi.h). - * All other methods (including stm32wl5_spibus_initialize()) are provided + * All other methods (including stm32_spibus_initialize()) are provided * by common STM32 logic. To use this common SPI logic on your board: * - * 1. Provide logic in stm32wl5_boardinitialize() to configure SPI chip + * 1. Provide logic in stm32_boardinitialize() to configure SPI chip * select pins. - * 2. Provide stm32wl5_spi1/2select() and stm32wl5_spi1/2() functions + * 2. Provide stm32_spi1/2select() and stm32_spi1/2() functions * in your board-specific logic. These functions will perform chip * selection and status operations using GPIOs in the way your board is * configured. - * 3. Add a calls to stm32wl5_spibus_initialize() in your low level + * 3. Add a calls to stm32_spibus_initialize() in your low level * application initialization logic - * 4. The handle returned by stm32wl5_spibus_initialize() may then be used + * 4. The handle returned by stm32_spibus_initialize() may then be used * to bind the SPI driver to higher level logic (e.g., calling * mmcsd_spislotinitialize(), for example, will bind the SPI driver to * the SPI MMC/SD driver). @@ -67,14 +67,14 @@ #include "arm_internal.h" #include "chip.h" -#include "stm32wl5.h" +#include "stm32.h" #include "stm32wl5_gpio.h" -#ifdef CONFIG_STM32WL5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA #include "stm32wl5_dma.h" #endif #include "stm32wl5_spi.h" -#if defined(CONFIG_STM32WL5_SPI1) || defined(CONFIG_STM32WL5_SPI2S2) +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2S2) /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ @@ -83,34 +83,34 @@ /* SPI interrupts */ -#ifdef CONFIG_STM32WL5_SPI_INTERRUPTS +#ifdef CONFIG_STM32_SPI_INTERRUPTS # error "Interrupt driven SPI not yet supported" #endif -#ifdef CONFIG_STM32WL5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA # error "DMA driven SPI not yet supported" #endif /* Can't have both interrupt driven SPI and SPI DMA */ -#if defined(CONFIG_STM32WL5_SPI_INTERRUPTS) && defined(CONFIG_STM32WL5_SPI_DMA) +#if defined(CONFIG_STM32_SPI_INTERRUPTS) && defined(CONFIG_STM32_SPI_DMA) # error "Cannot enable both interrupt mode and DMA mode for SPI" #endif /* SPI DMA priority */ -#ifdef CONFIG_STM32WL5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA # if defined(CONFIG_SPI_DMAPRIO) # define SPI_DMA_PRIO CONFIG_SPI_DMAPRIO -# elif defined(CONFIG_STM32WL5_STM32WL5XXX_CPU1 +# elif defined(CONFIG_STM32_STM32WL5XXX_CPU1 #warning "Verify, read doc and Implement" # define SPI_DMA_PRIO DMA_CCR_PRIMED # else # error "Unknown STM32WL5 DMA" # endif -# if defined(CONFIG_STM32WL5_STM32WL5XXX_CPU1) +# if defined(CONFIG_STM32_STM32WL5XXX_CPU1) # if (SPI_DMA_PRIO & ~DMA_CCR_PL_MASK) != 0 # error "Illegal value for CONFIG_SPI_DMAPRIO" # endif @@ -120,7 +120,7 @@ /* DMA channel configuration */ -#if defined(CONFIG_STM32WL5_STM32WL5XXX_CPU1) +#if defined(CONFIG_STM32_STM32WL5XXX_CPU1) # define SPI_RXDMA16_CONFIG (SPI_DMA_PRIO|DMA_CCR_MSIZE_16BITS|DMA_CCR_PSIZE_16BITS|DMA_CCR_MINC ) # define SPI_RXDMA8_CONFIG (SPI_DMA_PRIO|DMA_CCR_MSIZE_8BITS |DMA_CCR_PSIZE_8BITS |DMA_CCR_MINC ) # define SPI_RXDMA16NULL_CONFIG (SPI_DMA_PRIO|DMA_CCR_MSIZE_8BITS |DMA_CCR_PSIZE_16BITS ) @@ -137,15 +137,15 @@ # define SPIDMA_SIZE(b) (((b) + SPIDMA_BUFFER_MASK) & ~SPIDMA_BUFFER_MASK) # define SPIDMA_BUF_ALIGN aligned_data(4) -# if defined(CONFIG_STM32WL5_SPI1_DMA_BUFFER) && \ - CONFIG_STM32WL5_SPI1_DMA_BUFFER > 0 -# define SPI1_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32WL5_SPI1_DMA_BUFFER) +# if defined(CONFIG_STM32_SPI1_DMA_BUFFER) && \ + CONFIG_STM32_SPI1_DMA_BUFFER > 0 +# define SPI1_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32_SPI1_DMA_BUFFER) # define SPI1_DMABUFSIZE_ALGN SPIDMA_BUF_ALIGN # endif -# if defined(CONFIG_STM32WL5_SPI2S2_DMA_BUFFER) && \ - CONFIG_STM32WL5_SPI2S2_DMA_BUFFER > 0 -# define SPI2S2_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32WL5_SPI2S2_DMA_BUFFER) +# if defined(CONFIG_STM32_SPI2S2_DMA_BUFFER) && \ + CONFIG_STM32_SPI2S2_DMA_BUFFER > 0 +# define SPI2S2_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32_SPI2S2_DMA_BUFFER) # define SPI2S2_DMABUFSIZE_ALGN SPIDMA_BUF_ALIGN # endif @@ -155,15 +155,15 @@ * Private Types ****************************************************************************/ -struct stm32wl5_spidev_s +struct stm32_spidev_s { struct spi_dev_s spidev; /* Externally visible part of the SPI interface */ uint32_t spibase; /* SPIn base address */ uint32_t spiclock; /* Clocking for the SPI module */ -#ifdef CONFIG_STM32WL5_SPI_INTERRUPTS +#ifdef CONFIG_STM32_SPI_INTERRUPTS uint8_t spiirq; /* SPI IRQ number */ #endif -#ifdef CONFIG_STM32WL5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA volatile uint8_t rxresult; /* Result of the RX DMA */ volatile uint8_t txresult; /* Result of the RX DMA */ #ifdef CONFIG_SPI_TRIGGER @@ -196,45 +196,45 @@ struct stm32wl5_spidev_s /* Helpers */ -static inline uint16_t spi_getreg(struct stm32wl5_spidev_s *priv, +static inline uint16_t spi_getreg(struct stm32_spidev_s *priv, uint8_t offset); -static inline uint8_t spi_getreg8(struct stm32wl5_spidev_s *priv, +static inline uint8_t spi_getreg8(struct stm32_spidev_s *priv, uint8_t offset); -static inline void spi_putreg(struct stm32wl5_spidev_s *priv, +static inline void spi_putreg(struct stm32_spidev_s *priv, uint8_t offset, uint16_t value); -static inline void spi_putreg8(struct stm32wl5_spidev_s *priv, +static inline void spi_putreg8(struct stm32_spidev_s *priv, uint8_t offset, uint8_t value); -static inline uint16_t spi_readword(struct stm32wl5_spidev_s *priv); -static inline void spi_writeword(struct stm32wl5_spidev_s *priv, +static inline uint16_t spi_readword(struct stm32_spidev_s *priv); +static inline void spi_writeword(struct stm32_spidev_s *priv, uint16_t byte); /* DMA support */ -#ifdef CONFIG_STM32WL5_SPI_DMA -static int spi_dmarxwait(struct stm32wl5_spidev_s *priv); -static int spi_dmatxwait(struct stm32wl5_spidev_s *priv); -static inline void spi_dmarxwakeup(struct stm32wl5_spidev_s *priv); -static inline void spi_dmatxwakeup(struct stm32wl5_spidev_s *priv); +#ifdef CONFIG_STM32_SPI_DMA +static int spi_dmarxwait(struct stm32_spidev_s *priv); +static int spi_dmatxwait(struct stm32_spidev_s *priv); +static inline void spi_dmarxwakeup(struct stm32_spidev_s *priv); +static inline void spi_dmatxwakeup(struct stm32_spidev_s *priv); static void spi_dmarxcallback(DMA_HANDLE handle, uint8_t isr, void *arg); static void spi_dmatxcallback(DMA_HANDLE handle, uint8_t isr, void *arg); -static void spi_dmarxsetup(struct stm32wl5_spidev_s *priv, +static void spi_dmarxsetup(struct stm32_spidev_s *priv, void *rxbuffer, void *rxdummy, size_t nwords); -static void spi_dmatxsetup(struct stm32wl5_spidev_s *priv, +static void spi_dmatxsetup(struct stm32_spidev_s *priv, const void *txbuffer, const void *txdummy, size_t nwords); -static inline void spi_dmarxstart(struct stm32wl5_spidev_s *priv); -static inline void spi_dmatxstart(struct stm32wl5_spidev_s *priv); +static inline void spi_dmarxstart(struct stm32_spidev_s *priv); +static inline void spi_dmatxstart(struct stm32_spidev_s *priv); #endif /* SPI methods */ @@ -267,26 +267,26 @@ static void spi_recvblock(struct spi_dev_s *dev, /* Initialization */ -static void spi_bus_initialize(struct stm32wl5_spidev_s *priv); +static void spi_bus_initialize(struct stm32_spidev_s *priv); /**************************************************************************** * Private Data ****************************************************************************/ -#ifdef CONFIG_STM32WL5_SPI1 +#ifdef CONFIG_STM32_SPI1 static const struct spi_ops_s g_sp1iops = { .lock = spi_lock, - .select = stm32wl5_spi1select, + .select = stm32_spi1select, .setfrequency = spi_setfrequency, .setmode = spi_setmode, .setbits = spi_setbits, #ifdef CONFIG_SPI_HWFEATURES .hwfeatures = spi_hwfeatures, #endif - .status = stm32wl5_spi1status, + .status = stm32_spi1status, #ifdef CONFIG_SPI_CMDDATA - .cmddata = stm32wl5_spi1cmddata, + .cmddata = stm32_spi1cmddata, #endif .send = spi_send, #ifdef CONFIG_SPI_EXCHANGE @@ -299,7 +299,7 @@ static const struct spi_ops_s g_sp1iops = .trigger = spi_trigger, #endif #ifdef CONFIG_SPI_CALLBACK - .registercallback = stm32wl5_spi1register, /* Provided externally */ + .registercallback = stm32_spi1register, /* Provided externally */ #else .registercallback = 0, /* Not implemented */ #endif @@ -310,19 +310,19 @@ static uint8_t g_spi1_txbuf[SPI1_DMABUFSIZE_ADJUSTED] SPI1_DMABUFSIZE_ALGN; static uint8_t g_spi1_rxbuf[SPI1_DMABUFSIZE_ADJUSTED] SPI1_DMABUFSIZE_ALGN; #endif -static struct stm32wl5_spidev_s g_spi1dev = +static struct stm32_spidev_s g_spi1dev = { .spidev = { .ops = &g_sp1iops, }, - .spibase = STM32WL5_SPI1_BASE, - .spiclock = STM32WL5_PCLK2_FREQUENCY, -#ifdef CONFIG_STM32WL5_SPI_INTERRUPTS - .spiirq = STM32WL5_IRQ_SPI1, + .spibase = STM32_SPI1_BASE, + .spiclock = STM32_PCLK2_FREQUENCY, +#ifdef CONFIG_STM32_SPI_INTERRUPTS + .spiirq = STM32_IRQ_SPI1, #endif -#ifdef CONFIG_STM32WL5_SPI_DMA -# ifdef CONFIG_STM32WL5_SPI1_DMA +#ifdef CONFIG_STM32_SPI_DMA +# ifdef CONFIG_STM32_SPI1_DMA .rxch = DMACHAN_SPI1_RX, .txch = DMACHAN_SPI1_TX, #if defined(SPI1_DMABUFSIZE_ADJUSTED) @@ -341,20 +341,20 @@ static struct stm32wl5_spidev_s g_spi1dev = }; #endif -#ifdef CONFIG_STM32WL5_SPI2S2 +#ifdef CONFIG_STM32_SPI2S2 static const struct spi_ops_s g_sp2iops = { .lock = spi_lock, - .select = stm32wl5_spi2s2select, + .select = stm32_spi2s2select, .setfrequency = spi_setfrequency, .setmode = spi_setmode, .setbits = spi_setbits, #ifdef CONFIG_SPI_HWFEATURES .hwfeatures = spi_hwfeatures, #endif - .status = stm32wl5_spi2s2status, + .status = stm32_spi2s2status, #ifdef CONFIG_SPI_CMDDATA - .cmddata = stm32wl5_spi2s2cmddata, + .cmddata = stm32_spi2s2cmddata, #endif .send = spi_send, #ifdef CONFIG_SPI_EXCHANGE @@ -367,7 +367,7 @@ static const struct spi_ops_s g_sp2iops = .trigger = spi_trigger, #endif #ifdef CONFIG_SPI_CALLBACK - .registercallback = stm32wl5_s2register, /* provided externally */ + .registercallback = stm32_s2register, /* provided externally */ #else .registercallback = 0, /* not implemented */ #endif @@ -380,19 +380,19 @@ static uint8_t g_spi2s2_rxbuf[SPI2S2_DMABUFSIZE_ADJUSTED] SPI2S2_DMABUFSIZE_ALGN; #endif -static struct stm32wl5_spidev_s g_spi2s2dev = +static struct stm32_spidev_s g_spi2s2dev = { .spidev = { &g_sp2iops }, - .spibase = STM32WL5_SPI2S2_BASE, - .spiclock = STM32WL5_PCLK1_FREQUENCY, -#ifdef CONFIG_STM32WL5_SPI_INTERRUPTS - .spiirq = STM32WL5_IRQ_SPI2S2, + .spibase = STM32_SPI2S2_BASE, + .spiclock = STM32_PCLK1_FREQUENCY, +#ifdef CONFIG_STM32_SPI_INTERRUPTS + .spiirq = STM32_IRQ_SPI2S2, #endif -#ifdef CONFIG_STM32WL5_SPI_DMA -# ifdef CONFIG_STM32WL5_SPI2S2_DMA +#ifdef CONFIG_STM32_SPI_DMA +# ifdef CONFIG_STM32_SPI2S2_DMA .rxch = DMACHAN_SPI2S2_RX, .txch = DMACHAN_SPI2S2_TX, #if defined(SPI2S2_DMABUFSIZE_ADJUSTED) @@ -427,7 +427,7 @@ static struct stm32wl5_spidev_s g_spi2s2dev = * ****************************************************************************/ -static inline uint8_t spi_getreg8(struct stm32wl5_spidev_s *priv, +static inline uint8_t spi_getreg8(struct stm32_spidev_s *priv, uint8_t offset) { return getreg8(priv->spibase + offset); @@ -448,7 +448,7 @@ static inline uint8_t spi_getreg8(struct stm32wl5_spidev_s *priv, * ****************************************************************************/ -static inline uint16_t spi_getreg(struct stm32wl5_spidev_s *priv, +static inline uint16_t spi_getreg(struct stm32_spidev_s *priv, uint8_t offset) { return getreg16(priv->spibase + offset); @@ -470,7 +470,7 @@ static inline uint16_t spi_getreg(struct stm32wl5_spidev_s *priv, * ****************************************************************************/ -static inline void spi_putreg(struct stm32wl5_spidev_s *priv, +static inline void spi_putreg(struct stm32_spidev_s *priv, uint8_t offset, uint16_t value) { @@ -493,7 +493,7 @@ static inline void spi_putreg(struct stm32wl5_spidev_s *priv, * ****************************************************************************/ -static inline void spi_putreg8(struct stm32wl5_spidev_s *priv, +static inline void spi_putreg8(struct stm32_spidev_s *priv, uint8_t offset, uint8_t value) { @@ -514,11 +514,11 @@ static inline void spi_putreg8(struct stm32wl5_spidev_s *priv, * ****************************************************************************/ -static inline uint16_t spi_readword(struct stm32wl5_spidev_s *priv) +static inline uint16_t spi_readword(struct stm32_spidev_s *priv) { /* Wait until the receive buffer is not empty */ - while ((spi_getreg(priv, STM32WL5_SPI_SR_OFFSET) & SPI_SR_RXNE) == 0) + while ((spi_getreg(priv, STM32_SPI_SR_OFFSET) & SPI_SR_RXNE) == 0) { } @@ -539,11 +539,11 @@ static inline uint16_t spi_readword(struct stm32wl5_spidev_s *priv) if (priv->nbits < 9) { - return (uint16_t)spi_getreg8(priv, STM32WL5_SPI_DR_OFFSET); + return (uint16_t)spi_getreg8(priv, STM32_SPI_DR_OFFSET); } else { - return spi_getreg(priv, STM32WL5_SPI_DR_OFFSET); + return spi_getreg(priv, STM32_SPI_DR_OFFSET); } } @@ -563,12 +563,12 @@ static inline uint16_t spi_readword(struct stm32wl5_spidev_s *priv) * ****************************************************************************/ -static inline void spi_writeword(struct stm32wl5_spidev_s *priv, +static inline void spi_writeword(struct stm32_spidev_s *priv, uint16_t word) { /* Wait until the transmit buffer is empty */ - while ((spi_getreg(priv, STM32WL5_SPI_SR_OFFSET) & SPI_SR_TXE) == 0) + while ((spi_getreg(priv, STM32_SPI_SR_OFFSET) & SPI_SR_TXE) == 0) { } @@ -576,11 +576,11 @@ static inline void spi_writeword(struct stm32wl5_spidev_s *priv, if (priv->nbits < 9) { - spi_putreg8(priv, STM32WL5_SPI_DR_OFFSET, (uint8_t)word); + spi_putreg8(priv, STM32_SPI_DR_OFFSET, (uint8_t)word); } else { - spi_putreg(priv, STM32WL5_SPI_DR_OFFSET, word); + spi_putreg(priv, STM32_SPI_DR_OFFSET, word); } } @@ -592,8 +592,8 @@ static inline void spi_writeword(struct stm32wl5_spidev_s *priv, * ****************************************************************************/ -#ifdef CONFIG_STM32WL5_SPI_DMA -static int spi_dmarxwait(struct stm32wl5_spidev_s *priv) +#ifdef CONFIG_STM32_SPI_DMA +static int spi_dmarxwait(struct stm32_spidev_s *priv) { int ret; @@ -625,8 +625,8 @@ static int spi_dmarxwait(struct stm32wl5_spidev_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32WL5_SPI_DMA -static int spi_dmatxwait(struct stm32wl5_spidev_s *priv) +#ifdef CONFIG_STM32_SPI_DMA +static int spi_dmatxwait(struct stm32_spidev_s *priv) { int ret; @@ -658,8 +658,8 @@ static int spi_dmatxwait(struct stm32wl5_spidev_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32WL5_SPI_DMA -static inline void spi_dmarxwakeup(struct stm32wl5_spidev_s *priv) +#ifdef CONFIG_STM32_SPI_DMA +static inline void spi_dmarxwakeup(struct stm32_spidev_s *priv) { nxsem_post(&priv->rxsem); } @@ -673,8 +673,8 @@ static inline void spi_dmarxwakeup(struct stm32wl5_spidev_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32WL5_SPI_DMA -static inline void spi_dmatxwakeup(struct stm32wl5_spidev_s *priv) +#ifdef CONFIG_STM32_SPI_DMA +static inline void spi_dmatxwakeup(struct stm32_spidev_s *priv) { nxsem_post(&priv->txsem); } @@ -688,10 +688,10 @@ static inline void spi_dmatxwakeup(struct stm32wl5_spidev_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32WL5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_dmarxcallback(DMA_HANDLE handle, uint8_t isr, void *arg) { - struct stm32wl5_spidev_s *priv = (struct stm32wl5_spidev_s *)arg; + struct stm32_spidev_s *priv = (struct stm32_spidev_s *)arg; /* Wake-up the SPI driver */ @@ -708,10 +708,10 @@ static void spi_dmarxcallback(DMA_HANDLE handle, uint8_t isr, void *arg) * ****************************************************************************/ -#ifdef CONFIG_STM32WL5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_dmatxcallback(DMA_HANDLE handle, uint8_t isr, void *arg) { - struct stm32wl5_spidev_s *priv = (struct stm32wl5_spidev_s *)arg; + struct stm32_spidev_s *priv = (struct stm32_spidev_s *)arg; /* Wake-up the SPI driver */ @@ -728,8 +728,8 @@ static void spi_dmatxcallback(DMA_HANDLE handle, uint8_t isr, void *arg) * ****************************************************************************/ -#ifdef CONFIG_STM32WL5_SPI_DMA -static void spi_dmarxsetup(struct stm32wl5_spidev_s *priv, +#ifdef CONFIG_STM32_SPI_DMA +static void spi_dmarxsetup(struct stm32_spidev_s *priv, void *rxbuffer, void *rxdummy, size_t nwords) { @@ -766,7 +766,7 @@ static void spi_dmarxsetup(struct stm32wl5_spidev_s *priv, /* Configure the RX DMA */ - stm32wl5_dmasetup(priv->rxdma, priv->spibase + STM32WL5_SPI_DR_OFFSET, + stm32_dmasetup(priv->rxdma, priv->spibase + STM32_SPI_DR_OFFSET, (uint32_t)rxbuffer, nwords, priv->rxccr); } #endif @@ -779,8 +779,8 @@ static void spi_dmarxsetup(struct stm32wl5_spidev_s *priv, * ****************************************************************************/ -#ifdef CONFIG_STM32WL5_SPI_DMA -static void spi_dmatxsetup(struct stm32wl5_spidev_s *priv, +#ifdef CONFIG_STM32_SPI_DMA +static void spi_dmatxsetup(struct stm32_spidev_s *priv, const void *txbuffer, const void *txdummy, size_t nwords) { @@ -817,7 +817,7 @@ static void spi_dmatxsetup(struct stm32wl5_spidev_s *priv, /* Setup the TX DMA */ - stm32wl5_dmasetup(priv->txdma, priv->spibase + STM32WL5_SPI_DR_OFFSET, + stm32_dmasetup(priv->txdma, priv->spibase + STM32_SPI_DR_OFFSET, (uint32_t)txbuffer, nwords, priv->txccr); } #endif @@ -830,11 +830,11 @@ static void spi_dmatxsetup(struct stm32wl5_spidev_s *priv, * ****************************************************************************/ -#ifdef CONFIG_STM32WL5_SPI_DMA -static inline void spi_dmarxstart(struct stm32wl5_spidev_s *priv) +#ifdef CONFIG_STM32_SPI_DMA +static inline void spi_dmarxstart(struct stm32_spidev_s *priv) { priv->rxresult = 0; - stm32wl5_dmastart(priv->rxdma, spi_dmarxcallback, priv, false); + stm32_dmastart(priv->rxdma, spi_dmarxcallback, priv, false); } #endif @@ -846,11 +846,11 @@ static inline void spi_dmarxstart(struct stm32wl5_spidev_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32WL5_SPI_DMA -static inline void spi_dmatxstart(struct stm32wl5_spidev_s *priv) +#ifdef CONFIG_STM32_SPI_DMA +static inline void spi_dmatxstart(struct stm32_spidev_s *priv) { priv->txresult = 0; - stm32wl5_dmastart(priv->txdma, spi_dmatxcallback, priv, false); + stm32_dmastart(priv->txdma, spi_dmatxcallback, priv, false); } #endif @@ -870,17 +870,17 @@ static inline void spi_dmatxstart(struct stm32wl5_spidev_s *priv) * ****************************************************************************/ -static void spi_modifycr1(struct stm32wl5_spidev_s *priv, +static void spi_modifycr1(struct stm32_spidev_s *priv, uint16_t setbits, uint16_t clrbits) { uint16_t cr1; - cr1 = spi_getreg(priv, STM32WL5_SPI_CR1_OFFSET); + cr1 = spi_getreg(priv, STM32_SPI_CR1_OFFSET); cr1 &= ~clrbits; cr1 |= setbits; - spi_putreg(priv, STM32WL5_SPI_CR1_OFFSET, cr1); + spi_putreg(priv, STM32_SPI_CR1_OFFSET, cr1); - spiinfo("CR1 (0x%lx) = 0x%04x\n", priv->spibase + STM32WL5_SPI_CR1_OFFSET, + spiinfo("CR1 (0x%lx) = 0x%04x\n", priv->spibase + STM32_SPI_CR1_OFFSET, cr1); } @@ -900,15 +900,15 @@ static void spi_modifycr1(struct stm32wl5_spidev_s *priv, * ****************************************************************************/ -static void spi_modifycr2(struct stm32wl5_spidev_s *priv, uint16_t setbits, +static void spi_modifycr2(struct stm32_spidev_s *priv, uint16_t setbits, uint16_t clrbits) { uint16_t cr2; - cr2 = spi_getreg(priv, STM32WL5_SPI_CR2_OFFSET); + cr2 = spi_getreg(priv, STM32_SPI_CR2_OFFSET); cr2 &= ~clrbits; cr2 |= setbits; - spi_putreg(priv, STM32WL5_SPI_CR2_OFFSET, cr2); - spiinfo("CR2 (0x%lx) = 0x%04x\n", priv->spibase + STM32WL5_SPI_CR2_OFFSET, + spi_putreg(priv, STM32_SPI_CR2_OFFSET, cr2); + spiinfo("CR2 (0x%lx) = 0x%04x\n", priv->spibase + STM32_SPI_CR2_OFFSET, cr2); } @@ -935,7 +935,7 @@ static void spi_modifycr2(struct stm32wl5_spidev_s *priv, uint16_t setbits, static int spi_lock(struct spi_dev_s *dev, bool lock) { - struct stm32wl5_spidev_s *priv = (struct stm32wl5_spidev_s *)dev; + struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev; int ret; if (lock) @@ -968,7 +968,7 @@ static int spi_lock(struct spi_dev_s *dev, bool lock) static uint32_t spi_setfrequency(struct spi_dev_s *dev, uint32_t frequency) { - struct stm32wl5_spidev_s *priv = (struct stm32wl5_spidev_s *)dev; + struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev; uint16_t setbits; uint32_t actual; @@ -1069,7 +1069,7 @@ static uint32_t spi_setfrequency(struct spi_dev_s *dev, static void spi_setmode(struct spi_dev_s *dev, enum spi_mode_e mode) { - struct stm32wl5_spidev_s *priv = (struct stm32wl5_spidev_s *)dev; + struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev; uint16_t setbits; uint16_t clrbits; @@ -1168,7 +1168,7 @@ static void spi_setmode(struct spi_dev_s *dev, enum spi_mode_e mode) static void spi_setbits(struct spi_dev_s *dev, int nbits) { - struct stm32wl5_spidev_s *priv = (struct stm32wl5_spidev_s *)dev; + struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev; uint16_t setbits; uint16_t clrbits; @@ -1237,7 +1237,7 @@ static int spi_hwfeatures(struct spi_dev_s *dev, spi_hwfeatures_t features) { #if defined(CONFIG_SPI_BITORDER) || defined(CONFIG_SPI_TRIGGER) - struct stm32wl5_spidev_s *priv = (struct stm32wl5_spidev_s *)dev; + struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev; #endif #ifdef CONFIG_SPI_BITORDER @@ -1301,7 +1301,7 @@ static int spi_hwfeatures(struct spi_dev_s *dev, static uint32_t spi_send(struct spi_dev_s *dev, uint32_t wd) { - struct stm32wl5_spidev_s *priv = (struct stm32wl5_spidev_s *)dev; + struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev; uint32_t regval; uint32_t ret; @@ -1314,7 +1314,7 @@ static uint32_t spi_send(struct spi_dev_s *dev, uint32_t wd) * (Reading from the SR clears the error flags) */ - regval = spi_getreg(priv, STM32WL5_SPI_SR_OFFSET); + regval = spi_getreg(priv, STM32_SPI_SR_OFFSET); spiinfo("Sent: %04" PRIx32 " Return: %04" PRIx32 " Status: %02" PRIx32 "\n", wd, ret, regval); @@ -1348,9 +1348,9 @@ static uint32_t spi_send(struct spi_dev_s *dev, uint32_t wd) * ****************************************************************************/ -#if !defined(CONFIG_STM32WL5_SPI_DMA) || defined(CONFIG_STM32WL5_DMACAPABLE) || \ - defined(CONFIG_STM32WL5_SPI_DMATHRESHOLD) -#if !defined(CONFIG_STM32WL5_SPI_DMA) +#if !defined(CONFIG_STM32_SPI_DMA) || defined(CONFIG_STM32_DMACAPABLE) || \ + defined(CONFIG_STM32_SPI_DMATHRESHOLD) +#if !defined(CONFIG_STM32_SPI_DMA) static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, void *rxbuffer, size_t nwords) #else @@ -1359,7 +1359,7 @@ static void spi_exchange_nodma(struct spi_dev_s *dev, void *rxbuffer, size_t nwords) #endif { - struct stm32wl5_spidev_s *priv = (struct stm32wl5_spidev_s *)dev; + struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev; DEBUGASSERT(priv && priv->spibase); spiinfo("txbuffer=%p rxbuffer=%p nwords=%d\n", txbuffer, rxbuffer, nwords); @@ -1433,7 +1433,7 @@ static void spi_exchange_nodma(struct spi_dev_s *dev, } } } -#endif /* !CONFIG_STM32WL5_SPI_DMA || CONFIG_STM32WL5_DMACAPABLE || CONFIG_STM32WL5_SPI_DMATHRESHOLD */ +#endif /* !CONFIG_STM32_SPI_DMA || CONFIG_STM32_DMACAPABLE || CONFIG_STM32_SPI_DMATHRESHOLD */ /**************************************************************************** * Name: spi_exchange (with DMA capability) @@ -1456,11 +1456,11 @@ static void spi_exchange_nodma(struct spi_dev_s *dev, * ****************************************************************************/ -#ifdef CONFIG_STM32WL5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, void *rxbuffer, size_t nwords) { - struct stm32wl5_spidev_s *priv = (struct stm32wl5_spidev_s *)dev; + struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev; void *xbuffer = rxbuffer; int ret; @@ -1470,12 +1470,12 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, size_t nbytes = (priv->nbits > 8) ? nwords << 1 : nwords; -#ifdef CONFIG_STM32WL5_SPI_DMATHRESHOLD +#ifdef CONFIG_STM32_SPI_DMATHRESHOLD /* If this is a small SPI transfer, then let spi_exchange_nodma() do the * work. */ - if (nbytes <= CONFIG_STM32WL5_SPI_DMATHRESHOLD) + if (nbytes <= CONFIG_STM32_SPI_DMATHRESHOLD) { spi_exchange_nodma(dev, txbuffer, rxbuffer, nwords); return; @@ -1493,11 +1493,11 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, return; } -#ifdef CONFIG_STM32WL5_DMACAPABLE +#ifdef CONFIG_STM32_DMACAPABLE if ((txbuffer != NULL && priv->txbuf == NULL && - !stm32wl5_dmacapable((uintptr_t)txbuffer, nwords, priv->txccr)) || + !stm32_dmacapable((uintptr_t)txbuffer, nwords, priv->txccr)) || (rxbuffer != NULL && priv->rxbuf == NULL && - !stm32wl5_dmacapable((uintptr_t)rxbuffer, nwords, priv->rxccr))) + !stm32_dmacapable((uintptr_t)rxbuffer, nwords, priv->rxccr))) { /* Unsupported memory region fall back to non-DMA method. */ @@ -1580,7 +1580,7 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, #endif } } -#endif /* CONFIG_STM32WL5_SPI_DMA */ +#endif /* CONFIG_STM32_SPI_DMA */ /**************************************************************************** * Name: spi_trigger @@ -1601,8 +1601,8 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, #ifdef CONFIG_SPI_TRIGGER static int spi_trigger(struct spi_dev_s *dev) { -#ifdef CONFIG_STM32WL5_SPI_DMA - struct stm32wl5_spidev_s *priv = (struct stm32wl5_spidev_s *)dev; +#ifdef CONFIG_STM32_SPI_DMA + struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev; if (!priv->trigarmed) { @@ -1695,7 +1695,7 @@ static void spi_recvblock(struct spi_dev_s *dev, * ****************************************************************************/ -static void spi_bus_initialize(struct stm32wl5_spidev_s *priv) +static void spi_bus_initialize(struct stm32_spidev_s *priv) { uint16_t setbits; uint16_t clrbits; @@ -1731,23 +1731,23 @@ static void spi_bus_initialize(struct stm32wl5_spidev_s *priv) /* CRCPOLY configuration */ - spi_putreg(priv, STM32WL5_SPI_CRCPR_OFFSET, 7); + spi_putreg(priv, STM32_SPI_CRCPR_OFFSET, 7); -#ifdef CONFIG_STM32WL5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA if (priv->rxch && priv->txch) { - /* Get DMA channels. NOTE: stm32wl5_dmachannel() will always assign + /* Get DMA channels. NOTE: stm32_dmachannel() will always assign * the DMA channel. If the channel is not available, then - * stm32wl5_dmachannel() will block and wait until the channel becomes + * stm32_dmachannel() will block and wait until the channel becomes * available. * WARNING: If you have another device sharing a DMA channel with * SPI and the code never releases that channel, then the call to - * stm32wl5_dmachannel() will hang forever in this function! + * stm32_dmachannel() will hang forever in this function! * Don't let your design do that! */ - priv->rxdma = stm32wl5_dmachannel(priv->rxch); - priv->txdma = stm32wl5_dmachannel(priv->txch); + priv->rxdma = stm32_dmachannel(priv->rxch); + priv->txdma = stm32_dmachannel(priv->txch); DEBUGASSERT(priv->rxdma && priv->txdma); spi_modifycr2(priv, SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN, 0); @@ -1769,7 +1769,7 @@ static void spi_bus_initialize(struct stm32wl5_spidev_s *priv) ****************************************************************************/ /**************************************************************************** - * Name: stm32wl5_spibus_initialize + * Name: stm32_spibus_initialize * * Description: * Initialize the selected SPI bus @@ -1782,13 +1782,13 @@ static void spi_bus_initialize(struct stm32wl5_spidev_s *priv) * ****************************************************************************/ -struct spi_dev_s *stm32wl5_spibus_initialize(int bus) +struct spi_dev_s *stm32_spibus_initialize(int bus) { - struct stm32wl5_spidev_s *priv = NULL; + struct stm32_spidev_s *priv = NULL; irqstate_t flags = enter_critical_section(); -#ifdef CONFIG_STM32WL5_SPI1 +#ifdef CONFIG_STM32_SPI1 if (bus == 1) { /* Select SPI1 */ @@ -1801,9 +1801,9 @@ struct spi_dev_s *stm32wl5_spibus_initialize(int bus) { /* Configure SPI1 pins: SCK, MISO, and MOSI */ - stm32wl5_configgpio(GPIO_SPI1_SCK); - stm32wl5_configgpio(GPIO_SPI1_MISO); - stm32wl5_configgpio(GPIO_SPI1_MOSI); + stm32_configgpio(GPIO_SPI1_SCK); + stm32_configgpio(GPIO_SPI1_MISO); + stm32_configgpio(GPIO_SPI1_MOSI); /* Set up default configuration: Master, 8-bit, etc. */ @@ -1813,7 +1813,7 @@ struct spi_dev_s *stm32wl5_spibus_initialize(int bus) } else #endif -#ifdef CONFIG_STM32WL5_SPI2S2 +#ifdef CONFIG_STM32_SPI2S2 if (bus == 2) { /* Select SPI2S2 */ @@ -1826,9 +1826,9 @@ struct spi_dev_s *stm32wl5_spibus_initialize(int bus) { /* Configure SPI2S2 pins: SCK, MISO, and MOSI */ - stm32wl5_configgpio(GPIO_SPI2S2_SCK); - stm32wl5_configgpio(GPIO_SPI2S2_MISO); - stm32wl5_configgpio(GPIO_SPI2S2_MOSI); + stm32_configgpio(GPIO_SPI2S2_SCK); + stm32_configgpio(GPIO_SPI2S2_MISO); + stm32_configgpio(GPIO_SPI2S2_MOSI); /* Set up default configuration: Master, 8-bit, etc. */ @@ -1846,4 +1846,4 @@ struct spi_dev_s *stm32wl5_spibus_initialize(int bus) return (struct spi_dev_s *)priv; } -#endif /* CONFIG_STM32WL5_SPI1 || CONFIG_STM32WL5_SPI2S2 */ +#endif /* CONFIG_STM32_SPI1 || CONFIG_STM32_SPI2S2 */ diff --git a/arch/arm/src/stm32wl5/stm32wl5_spi.h b/arch/arm/src/stm32wl5/stm32wl5_spi.h index 17071c7fa3268..aa505c047b8da 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_spi.h +++ b/arch/arm/src/stm32wl5/stm32wl5_spi.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32WL5_STM32WL5_SPI_H -#define __ARCH_ARM_SRC_STM32WL5_STM32WL5_SPI_H +#ifndef __ARCH_ARM_SRC_STM32WL5_STM32_SPI_H +#define __ARCH_ARM_SRC_STM32WL5_STM32_SPI_H /**************************************************************************** * Included Files @@ -61,7 +61,7 @@ struct spi_dev_s; ****************************************************************************/ /**************************************************************************** - * Name: stm32wl5_spibus_initialize + * Name: stm32_spibus_initialize * * Description: * Initialize the selected SPI bus @@ -74,55 +74,55 @@ struct spi_dev_s; * ****************************************************************************/ -struct spi_dev_s *stm32wl5_spibus_initialize(int bus); +struct spi_dev_s *stm32_spibus_initialize(int bus); /**************************************************************************** - * Name: stm32wl5_spi1/2select and stm32wl5_spi1/2status + * Name: stm32_spi1/2select and stm32_spi1/2status * * Description: - * The external functions, stm32wl5_spi1/2select, stm32wl5_spi1/2status, - * and stm32wl5_spi1/2cmddata must be provided by board-specific logic. + * The external functions, stm32_spi1/2select, stm32_spi1/2status, + * and stm32_spi1/2cmddata must be provided by board-specific logic. * These are implementations of the select, status, and cmddata methods of * the SPI interface defined by struct spi_ops_s (see * include/nuttx/spi/spi.h). All other methods (including - * stm32wl5_spibus_initialize()) are provided by common STM32 logic. + * stm32_spibus_initialize()) are provided by common STM32 logic. * To use this common SPI logic on your board: * - * 1. Provide logic in stm32wl5_boardinitialize() to configure SPI chip + * 1. Provide logic in stm32_boardinitialize() to configure SPI chip * select pins. - * 2. Provide stm32wl5_spi1/2select() and stm32wl5_spi1/2status() + * 2. Provide stm32_spi1/2select() and stm32_spi1/2status() * functions in your board-specific logic. These functions will * perform chip selection and status operations using GPIOs in the way * your board is configured. * 3. If CONFIG_SPI_CMDDATA is defined in your NuttX configuration file, - * then provide stm32wl5_spi1/2cmddata() functions in your board- + * then provide stm32_spi1/2cmddata() functions in your board- * specific logic. These functions will perform cmd/data selection * operations using GPIOs in the way your board is configured. - * 4. Add a calls to stm32wl5_spibus_initialize() in your low level + * 4. Add a calls to stm32_spibus_initialize() in your low level * application initialization logic - * 5. The handle returned by stm32wl5_spibus_initialize() may then be used + * 5. The handle returned by stm32_spibus_initialize() may then be used * to bind the SPI driver to higher level logic (e.g., calling * mmcsd_spislotinitialize(), for example, will bind the SPI driver to * the SPI MMC/SD driver). * ****************************************************************************/ -#ifdef CONFIG_STM32WL5_SPI1 -void stm32wl5_spi1select(struct spi_dev_s *dev, uint32_t devid, +#ifdef CONFIG_STM32_SPI1 +void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, bool selected); -uint8_t stm32wl5_spi1status(struct spi_dev_s *dev, uint32_t devid); -int stm32wl5_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); +uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid); +int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); #endif -#ifdef CONFIG_STM32WL5_SPI2S2 -void stm32wl5_spi2s2select(struct spi_dev_s *dev, uint32_t devid, +#ifdef CONFIG_STM32_SPI2S2 +void stm32_spi2s2select(struct spi_dev_s *dev, uint32_t devid, bool selected); -uint8_t stm32wl5_spi2s2status(struct spi_dev_s *dev, uint32_t devid); -int stm32wl5_spi2s2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); +uint8_t stm32_spi2s2status(struct spi_dev_s *dev, uint32_t devid); +int stm32_spi2s2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); #endif /**************************************************************************** - * Name: stm32wl5_spi1/2s2register + * Name: stm32_spi1/2s2register * * Description: * If the board supports a card detect callback to inform the SPI-based @@ -142,13 +142,13 @@ int stm32wl5_spi2s2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); ****************************************************************************/ #ifdef CONFIG_SPI_CALLBACK -#ifdef CONFIG_STM32WL5_SPI1 -int stm32wl5_spi1register(struct spi_dev_s *dev, spi_mediachange_t callback, +#ifdef CONFIG_STM32_SPI1 +int stm32_spi1register(struct spi_dev_s *dev, spi_mediachange_t callback, void *arg); #endif -#ifdef CONFIG_STM32WL5_SPI2S2 -int stm32wl5_spi2s2register(struct spi_dev_s *dev, +#ifdef CONFIG_STM32_SPI2S2 +int stm32_spi2s2register(struct spi_dev_s *dev, spi_mediachange_t callback, void *arg); #endif @@ -160,4 +160,4 @@ int stm32wl5_spi2s2register(struct spi_dev_s *dev, #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32WL5_STM32WL5_SPI_H */ +#endif /* __ARCH_ARM_SRC_STM32WL5_STM32_SPI_H */ diff --git a/arch/arm/src/stm32wl5/stm32wl5_start.c b/arch/arm/src/stm32wl5/stm32wl5_start.c index e828fca974eda..24a7a9c240a8a 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_start.c +++ b/arch/arm/src/stm32wl5/stm32wl5_start.c @@ -36,7 +36,7 @@ #include "arm_internal.h" #include "nvic.h" -#include "stm32wl5.h" +#include "stm32.h" #include "stm32wl5_gpio.h" #include "stm32wl5_userspace.h" #include "stm32wl5_start.h" @@ -60,8 +60,8 @@ * 0x2000:8000 - Start of internal SRAM2 */ -#define SRAM2_START STM32WL5_SRAM2_BASE -#define SRAM2_END (SRAM2_START + STM32WL5_SRAM2_SIZE) +#define SRAM2_START STM32_SRAM2_BASE +#define SRAM2_END (SRAM2_START + STM32_SRAM2_SIZE) #define HEAP_BASE ((uintptr_t)_ebss + CONFIG_IDLETHREAD_STACKSIZE) @@ -133,7 +133,7 @@ void __start(void) "r"(CONFIG_IDLETHREAD_STACKSIZE - 64) :); #endif -#ifdef CONFIG_STM32WL5_SRAM2_INIT +#ifdef CONFIG_STM32_SRAM2_INIT /* The SRAM2 region is parity checked, but upon power up, it will be in * a random state and probably invalid with respect to parity, potentially * generating faults if accessed. If elected, we will write zeros to the @@ -153,9 +153,9 @@ void __start(void) /* Configure the UART so that we can get debug output as soon as possible */ - stm32wl5_clockconfig(); - stm32wl5_lowsetup(); - stm32wl5_gpioinit(); + stm32_clockconfig(); + stm32_lowsetup(); + stm32_gpioinit(); showprogress('A'); /* Clear .bss. We'll do this inline (vs. calling memset) just to be @@ -202,13 +202,13 @@ void __start(void) */ #ifdef CONFIG_BUILD_PROTECTED - stm32wl5_userspace(); + stm32_userspace(); showprogress('E'); #endif /* Initialize onboard resources */ - stm32wl5_board_initialize(); + stm32_board_initialize(); showprogress('F'); /* Then start NuttX */ diff --git a/arch/arm/src/stm32wl5/stm32wl5_start.h b/arch/arm/src/stm32wl5/stm32wl5_start.h index b36f7600b6094..254676852790a 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_start.h +++ b/arch/arm/src/stm32wl5/stm32wl5_start.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32WL5_STM32WL5_START_H -#define __ARCH_ARM_SRC_STM32WL5_STM32WL5_START_H +#ifndef __ARCH_ARM_SRC_STM32WL5_STM32_START_H +#define __ARCH_ARM_SRC_STM32WL5_STM32_START_H /**************************************************************************** * Included Files @@ -32,7 +32,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32wl5_board_initialize + * Name: stm32_board_initialize * * Description: * All STM32WL5 architectures must provide the following entry point. This @@ -42,6 +42,6 @@ * ****************************************************************************/ -void stm32wl5_board_initialize(void); +void stm32_board_initialize(void); -#endif /* __ARCH_ARM_SRC_STM32WL5_STM32WL5_START_H */ +#endif /* __ARCH_ARM_SRC_STM32WL5_STM32_START_H */ diff --git a/arch/arm/src/stm32wl5/stm32wl5_tim.c b/arch/arm/src/stm32wl5/stm32wl5_tim.c index 7be699ed8f7fb..56bcfa281f6a2 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_tim.c +++ b/arch/arm/src/stm32wl5/stm32wl5_tim.c @@ -41,7 +41,7 @@ #include "chip.h" #include "arm_internal.h" -#include "stm32wl5.h" +#include "stm32.h" #include "stm32wl5_gpio.h" #include "stm32wl5_tim.h" @@ -55,137 +55,137 @@ * include: * * - To generate modulated outputs for such things as motor control. If - * CONFIG_STM32WL5_TIMn is defined then the CONFIG_STM32WL5_TIMn_PWM may + * CONFIG_STM32_TIMn is defined then the CONFIG_STM32_TIMn_PWM may * also be defined to indicate that the timer is intended to be used for * pulsed output modulation. * - * - To control periodic ADC input sampling. If CONFIG_STM32WL5_TIMn is - * defined then CONFIG_STM32WL5_TIMn_ADC may also be defined to indicate + * - To control periodic ADC input sampling. If CONFIG_STM32_TIMn is + * defined then CONFIG_STM32_TIMn_ADC may also be defined to indicate * that timer "n" is intended to be used for that purpose. * - * - To control periodic DAC outputs. If CONFIG_STM32WL5_TIMn is defined - * then CONFIG_STM32WL5_TIMn_DAC may also be defined to indicate that + * - To control periodic DAC outputs. If CONFIG_STM32_TIMn is defined + * then CONFIG_STM32_TIMn_DAC may also be defined to indicate that * timer "n" is intended to be used for that purpose. * - * - To use a Quadrature Encoder. If CONFIG_STM32WL5_TIMn is defined then - * CONFIG_STM32WL5_TIMn_QE may also be defined to indicate that timer "n" + * - To use a Quadrature Encoder. If CONFIG_STM32_TIMn is defined then + * CONFIG_STM32_TIMn_QE may also be defined to indicate that timer "n" * is intended to be used for that purpose. * * In any of these cases, the timer will not be used by this timer module. */ -#if defined(CONFIG_STM32WL5_TIM1_PWM) || defined (CONFIG_STM32WL5_TIM1_ADC) || \ - defined(CONFIG_STM32WL5_TIM1_DAC) || defined(CONFIG_STM32WL5_TIM1_QE) -# undef CONFIG_STM32WL5_TIM1 +#if defined(CONFIG_STM32_TIM1_PWM) || defined (CONFIG_STM32_TIM1_ADC) || \ + defined(CONFIG_STM32_TIM1_DAC) || defined(CONFIG_STM32_TIM1_QE) +# undef CONFIG_STM32_TIM1 #endif -#if defined(CONFIG_STM32WL5_TIM2_PWM) || defined (CONFIG_STM32WL5_TIM2_ADC) || \ - defined(CONFIG_STM32WL5_TIM2_DAC) || defined(CONFIG_STM32WL5_TIM2_QE) -# undef CONFIG_STM32WL5_TIM2 +#if defined(CONFIG_STM32_TIM2_PWM) || defined (CONFIG_STM32_TIM2_ADC) || \ + defined(CONFIG_STM32_TIM2_DAC) || defined(CONFIG_STM32_TIM2_QE) +# undef CONFIG_STM32_TIM2 #endif -#if defined(CONFIG_STM32WL5_TIM3_PWM) || defined (CONFIG_STM32WL5_TIM3_ADC) || \ - defined(CONFIG_STM32WL5_TIM3_DAC) || defined(CONFIG_STM32WL5_TIM3_QE) -# undef CONFIG_STM32WL5_TIM3 +#if defined(CONFIG_STM32_TIM3_PWM) || defined (CONFIG_STM32_TIM3_ADC) || \ + defined(CONFIG_STM32_TIM3_DAC) || defined(CONFIG_STM32_TIM3_QE) +# undef CONFIG_STM32_TIM3 #endif -#if defined(CONFIG_STM32WL5_TIM4_PWM) || defined (CONFIG_STM32WL5_TIM4_ADC) || \ - defined(CONFIG_STM32WL5_TIM4_DAC) || defined(CONFIG_STM32WL5_TIM4_QE) -# undef CONFIG_STM32WL5_TIM4 +#if defined(CONFIG_STM32_TIM4_PWM) || defined (CONFIG_STM32_TIM4_ADC) || \ + defined(CONFIG_STM32_TIM4_DAC) || defined(CONFIG_STM32_TIM4_QE) +# undef CONFIG_STM32_TIM4 #endif -#if defined(CONFIG_STM32WL5_TIM5_PWM) || defined (CONFIG_STM32WL5_TIM5_ADC) || \ - defined(CONFIG_STM32WL5_TIM5_DAC) || defined(CONFIG_STM32WL5_TIM5_QE) -# undef CONFIG_STM32WL5_TIM5 +#if defined(CONFIG_STM32_TIM5_PWM) || defined (CONFIG_STM32_TIM5_ADC) || \ + defined(CONFIG_STM32_TIM5_DAC) || defined(CONFIG_STM32_TIM5_QE) +# undef CONFIG_STM32_TIM5 #endif -#if defined(CONFIG_STM32WL5_TIM6_PWM) || defined (CONFIG_STM32WL5_TIM6_ADC) || \ - defined(CONFIG_STM32WL5_TIM6_DAC) || defined(CONFIG_STM32WL5_TIM6_QE) -# undef CONFIG_STM32WL5_TIM6 +#if defined(CONFIG_STM32_TIM6_PWM) || defined (CONFIG_STM32_TIM6_ADC) || \ + defined(CONFIG_STM32_TIM6_DAC) || defined(CONFIG_STM32_TIM6_QE) +# undef CONFIG_STM32_TIM6 #endif -#if defined(CONFIG_STM32WL5_TIM7_PWM) || defined (CONFIG_STM32WL5_TIM7_ADC) || \ - defined(CONFIG_STM32WL5_TIM7_DAC) || defined(CONFIG_STM32WL5_TIM7_QE) -# undef CONFIG_STM32WL5_TIM7 +#if defined(CONFIG_STM32_TIM7_PWM) || defined (CONFIG_STM32_TIM7_ADC) || \ + defined(CONFIG_STM32_TIM7_DAC) || defined(CONFIG_STM32_TIM7_QE) +# undef CONFIG_STM32_TIM7 #endif -#if defined(CONFIG_STM32WL5_TIM8_PWM) || defined (CONFIG_STM32WL5_TIM8_ADC) || \ - defined(CONFIG_STM32WL5_TIM8_DAC) || defined(CONFIG_STM32WL5_TIM8_QE) -# undef CONFIG_STM32WL5_TIM8 +#if defined(CONFIG_STM32_TIM8_PWM) || defined (CONFIG_STM32_TIM8_ADC) || \ + defined(CONFIG_STM32_TIM8_DAC) || defined(CONFIG_STM32_TIM8_QE) +# undef CONFIG_STM32_TIM8 #endif -#if defined(CONFIG_STM32WL5_TIM15_PWM) || defined (CONFIG_STM32WL5_TIM15_ADC) || \ - defined(CONFIG_STM32WL5_TIM15_DAC) || defined(CONFIG_STM32WL5_TIM15_QE) -# undef CONFIG_STM32WL5_TIM15 +#if defined(CONFIG_STM32_TIM15_PWM) || defined (CONFIG_STM32_TIM15_ADC) || \ + defined(CONFIG_STM32_TIM15_DAC) || defined(CONFIG_STM32_TIM15_QE) +# undef CONFIG_STM32_TIM15 #endif -#if defined(CONFIG_STM32WL5_TIM16_PWM) || defined (CONFIG_STM32WL5_TIM16_ADC) || \ - defined(CONFIG_STM32WL5_TIM16_DAC) || defined(CONFIG_STM32WL5_TIM16_QE) -# undef CONFIG_STM32WL5_TIM16 +#if defined(CONFIG_STM32_TIM16_PWM) || defined (CONFIG_STM32_TIM16_ADC) || \ + defined(CONFIG_STM32_TIM16_DAC) || defined(CONFIG_STM32_TIM16_QE) +# undef CONFIG_STM32_TIM16 #endif -#if defined(CONFIG_STM32WL5_TIM17_PWM) || defined (CONFIG_STM32WL5_TIM17_ADC) || \ - defined(CONFIG_STM32WL5_TIM17_DAC) || defined(CONFIG_STM32WL5_TIM17_QE) -# undef CONFIG_STM32WL5_TIM17 +#if defined(CONFIG_STM32_TIM17_PWM) || defined (CONFIG_STM32_TIM17_ADC) || \ + defined(CONFIG_STM32_TIM17_DAC) || defined(CONFIG_STM32_TIM17_QE) +# undef CONFIG_STM32_TIM17 #endif -#if defined(CONFIG_STM32WL5_TIM1) +#if defined(CONFIG_STM32_TIM1) # if defined(GPIO_TIM1_CH1OUT) ||defined(GPIO_TIM1_CH2OUT)||\ defined(GPIO_TIM1_CH3OUT) ||defined(GPIO_TIM1_CH4OUT) # define HAVE_TIM1_GPIOCONFIG 1 #endif #endif -#if defined(CONFIG_STM32WL5_TIM2) +#if defined(CONFIG_STM32_TIM2) # if defined(GPIO_TIM2_CH1OUT) ||defined(GPIO_TIM2_CH2OUT)||\ defined(GPIO_TIM2_CH3OUT) ||defined(GPIO_TIM2_CH4OUT) # define HAVE_TIM2_GPIOCONFIG 1 #endif #endif -#if defined(CONFIG_STM32WL5_TIM3) +#if defined(CONFIG_STM32_TIM3) # if defined(GPIO_TIM3_CH1OUT) ||defined(GPIO_TIM3_CH2OUT)||\ defined(GPIO_TIM3_CH3OUT) ||defined(GPIO_TIM3_CH4OUT) # define HAVE_TIM3_GPIOCONFIG 1 #endif #endif -#if defined(CONFIG_STM32WL5_TIM4) +#if defined(CONFIG_STM32_TIM4) # if defined(GPIO_TIM4_CH1OUT) ||defined(GPIO_TIM4_CH2OUT)||\ defined(GPIO_TIM4_CH3OUT) ||defined(GPIO_TIM4_CH4OUT) # define HAVE_TIM4_GPIOCONFIG 1 #endif #endif -#if defined(CONFIG_STM32WL5_TIM5) +#if defined(CONFIG_STM32_TIM5) # if defined(GPIO_TIM5_CH1OUT) ||defined(GPIO_TIM5_CH2OUT)||\ defined(GPIO_TIM5_CH3OUT) ||defined(GPIO_TIM5_CH4OUT) # define HAVE_TIM5_GPIOCONFIG 1 #endif #endif -#if defined(CONFIG_STM32WL5_TIM8) +#if defined(CONFIG_STM32_TIM8) # if defined(GPIO_TIM8_CH1OUT) ||defined(GPIO_TIM8_CH2OUT)||\ defined(GPIO_TIM8_CH3OUT) ||defined(GPIO_TIM8_CH4OUT) # define HAVE_TIM8_GPIOCONFIG 1 #endif #endif -#if defined(CONFIG_STM32WL5_TIM15) +#if defined(CONFIG_STM32_TIM15) # if defined(GPIO_TIM15_CH1OUT) ||defined(GPIO_TIM15_CH2OUT)||\ defined(GPIO_TIM15_CH3OUT) ||defined(GPIO_TIM15_CH4OUT) # define HAVE_TIM15_GPIOCONFIG 1 #endif #endif -#if defined(CONFIG_STM32WL5_TIM16) +#if defined(CONFIG_STM32_TIM16) # if defined(GPIO_TIM16_CH1OUT) ||defined(GPIO_TIM16_CH2OUT)||\ defined(GPIO_TIM16_CH3OUT) ||defined(GPIO_TIM16_CH4OUT) # define HAVE_TIM16_GPIOCONFIG 1 #endif #endif -#if defined(CONFIG_STM32WL5_TIM17) +#if defined(CONFIG_STM32_TIM17) # if defined(GPIO_TIM17_CH1OUT) ||defined(GPIO_TIM17_CH2OUT)||\ defined(GPIO_TIM17_CH3OUT) ||defined(GPIO_TIM17_CH4OUT) # define HAVE_TIM17_GPIOCONFIG 1 @@ -196,12 +196,12 @@ * intended for some other purpose. */ -#if defined(CONFIG_STM32WL5_TIM1) || defined(CONFIG_STM32WL5_TIM2) || \ - defined(CONFIG_STM32WL5_TIM3) || defined(CONFIG_STM32WL5_TIM4) || \ - defined(CONFIG_STM32WL5_TIM5) || defined(CONFIG_STM32WL5_TIM6) || \ - defined(CONFIG_STM32WL5_TIM7) || defined(CONFIG_STM32WL5_TIM8) || \ - defined(CONFIG_STM32WL5_TIM15) || defined(CONFIG_STM32WL5_TIM16) || \ - defined(CONFIG_STM32WL5_TIM17) +#if defined(CONFIG_STM32_TIM1) || defined(CONFIG_STM32_TIM2) || \ + defined(CONFIG_STM32_TIM3) || defined(CONFIG_STM32_TIM4) || \ + defined(CONFIG_STM32_TIM5) || defined(CONFIG_STM32_TIM6) || \ + defined(CONFIG_STM32_TIM7) || defined(CONFIG_STM32_TIM8) || \ + defined(CONFIG_STM32_TIM15) || defined(CONFIG_STM32_TIM16) || \ + defined(CONFIG_STM32_TIM17) /**************************************************************************** * Private Types @@ -209,10 +209,10 @@ /* TIM Device Structure */ -struct stm32wl5_tim_priv_s +struct stm32_tim_priv_s { - const struct stm32wl5_tim_ops_s *ops; - enum stm32wl5_tim_mode_e mode; + const struct stm32_tim_ops_s *ops; + enum stm32_tim_mode_e mode; uint32_t base; /* TIMn base address */ }; @@ -222,181 +222,181 @@ struct stm32wl5_tim_priv_s /* Register helpers */ -static inline uint16_t stm32wl5_getreg16(struct stm32wl5_tim_dev_s *dev, +static inline uint16_t stm32_getreg16(struct stm32_tim_dev_s *dev, uint8_t offset); -static inline void stm32wl5_putreg16(struct stm32wl5_tim_dev_s *dev, +static inline void stm32_putreg16(struct stm32_tim_dev_s *dev, uint8_t offset, uint16_t value); -static inline void stm32wl5_modifyreg16(struct stm32wl5_tim_dev_s *dev, +static inline void stm32_modifyreg16(struct stm32_tim_dev_s *dev, uint8_t offset, uint16_t clearbits, uint16_t setbits); -static inline uint32_t stm32wl5_getreg32(struct stm32wl5_tim_dev_s *dev, +static inline uint32_t stm32_getreg32(struct stm32_tim_dev_s *dev, uint8_t offset); -static inline void stm32wl5_putreg32(struct stm32wl5_tim_dev_s *dev, +static inline void stm32_putreg32(struct stm32_tim_dev_s *dev, uint8_t offset, uint32_t value); /* Timer helpers */ -static void stm32wl5_tim_reload_counter(struct stm32wl5_tim_dev_s *dev); -static void stm32wl5_tim_enable(struct stm32wl5_tim_dev_s *dev); -static void stm32wl5_tim_disable(struct stm32wl5_tim_dev_s *dev); -static void stm32wl5_tim_reset(struct stm32wl5_tim_dev_s *dev); +static void stm32_tim_reload_counter(struct stm32_tim_dev_s *dev); +static void stm32_tim_enable(struct stm32_tim_dev_s *dev); +static void stm32_tim_disable(struct stm32_tim_dev_s *dev); +static void stm32_tim_reset(struct stm32_tim_dev_s *dev); #if defined(HAVE_TIM1_GPIOCONFIG) || defined(HAVE_TIM2_GPIOCONFIG) || \ defined(HAVE_TIM3_GPIOCONFIG) || defined(HAVE_TIM4_GPIOCONFIG) || \ defined(HAVE_TIM5_GPIOCONFIG) || defined(HAVE_TIM8_GPIOCONFIG) || \ defined(HAVE_TIM15_GPIOCONFIG) || defined(HAVE_TIM16_GPIOCONFIG) || \ defined(HAVE_TIM17_GPIOCONFIG) -static void stm32wl5_tim_gpioconfig(uint32_t cfg, - enum stm32wl5_tim_channel_e mode); +static void stm32_tim_gpioconfig(uint32_t cfg, + enum stm32_tim_channel_e mode); #endif /* Timer methods */ -static int stm32wl5_tim_setmode(struct stm32wl5_tim_dev_s *dev, - enum stm32wl5_tim_mode_e mode); -static int stm32wl5_tim_setclock(struct stm32wl5_tim_dev_s *dev, +static int stm32_tim_setmode(struct stm32_tim_dev_s *dev, + enum stm32_tim_mode_e mode); +static int stm32_tim_setclock(struct stm32_tim_dev_s *dev, uint32_t freq); -static uint32_t stm32wl5_tim_getclock(struct stm32wl5_tim_dev_s *dev); -static void stm32wl5_tim_setperiod(struct stm32wl5_tim_dev_s *dev, +static uint32_t stm32_tim_getclock(struct stm32_tim_dev_s *dev); +static void stm32_tim_setperiod(struct stm32_tim_dev_s *dev, uint32_t period); -static uint32_t stm32wl5_tim_getperiod(struct stm32wl5_tim_dev_s *dev); -static uint32_t stm32wl5_tim_getcounter(struct stm32wl5_tim_dev_s *dev); -static int stm32wl5_tim_setchannel(struct stm32wl5_tim_dev_s *dev, +static uint32_t stm32_tim_getperiod(struct stm32_tim_dev_s *dev); +static uint32_t stm32_tim_getcounter(struct stm32_tim_dev_s *dev); +static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, uint8_t channel, - enum stm32wl5_tim_channel_e mode); -static int stm32wl5_tim_setcompare(struct stm32wl5_tim_dev_s *dev, + enum stm32_tim_channel_e mode); +static int stm32_tim_setcompare(struct stm32_tim_dev_s *dev, uint8_t channel, uint32_t compare); -static int stm32wl5_tim_getcapture(struct stm32wl5_tim_dev_s *dev, +static int stm32_tim_getcapture(struct stm32_tim_dev_s *dev, uint8_t channel); -static int stm32wl5_tim_setisr(struct stm32wl5_tim_dev_s *dev, +static int stm32_tim_setisr(struct stm32_tim_dev_s *dev, xcpt_t handler, void *arg, int source); -static void stm32wl5_tim_enableint(struct stm32wl5_tim_dev_s *dev, +static void stm32_tim_enableint(struct stm32_tim_dev_s *dev, int source); -static void stm32wl5_tim_disableint(struct stm32wl5_tim_dev_s *dev, +static void stm32_tim_disableint(struct stm32_tim_dev_s *dev, int source); -static void stm32wl5_tim_ackint(struct stm32wl5_tim_dev_s *dev, +static void stm32_tim_ackint(struct stm32_tim_dev_s *dev, int source); -static int stm32wl5_tim_checkint(struct stm32wl5_tim_dev_s *dev, +static int stm32_tim_checkint(struct stm32_tim_dev_s *dev, int source); /**************************************************************************** * Private Data ****************************************************************************/ -static const struct stm32wl5_tim_ops_s stm32wl5_tim_ops = +static const struct stm32_tim_ops_s stm32_tim_ops = { - .enable = stm32wl5_tim_enable, - .disable = stm32wl5_tim_disable, - .setmode = stm32wl5_tim_setmode, - .setclock = stm32wl5_tim_setclock, - .getclock = stm32wl5_tim_getclock, - .setperiod = stm32wl5_tim_setperiod, - .getperiod = stm32wl5_tim_getperiod, - .getcounter = stm32wl5_tim_getcounter, - .setchannel = stm32wl5_tim_setchannel, - .setcompare = stm32wl5_tim_setcompare, - .getcapture = stm32wl5_tim_getcapture, - .setisr = stm32wl5_tim_setisr, - .enableint = stm32wl5_tim_enableint, - .disableint = stm32wl5_tim_disableint, - .ackint = stm32wl5_tim_ackint, - .checkint = stm32wl5_tim_checkint, + .enable = stm32_tim_enable, + .disable = stm32_tim_disable, + .setmode = stm32_tim_setmode, + .setclock = stm32_tim_setclock, + .getclock = stm32_tim_getclock, + .setperiod = stm32_tim_setperiod, + .getperiod = stm32_tim_getperiod, + .getcounter = stm32_tim_getcounter, + .setchannel = stm32_tim_setchannel, + .setcompare = stm32_tim_setcompare, + .getcapture = stm32_tim_getcapture, + .setisr = stm32_tim_setisr, + .enableint = stm32_tim_enableint, + .disableint = stm32_tim_disableint, + .ackint = stm32_tim_ackint, + .checkint = stm32_tim_checkint, }; -#ifdef CONFIG_STM32WL5_TIM1 -struct stm32wl5_tim_priv_s stm32wl5_tim1_priv = +#ifdef CONFIG_STM32_TIM1 +struct stm32_tim_priv_s stm32_tim1_priv = { - .ops = &stm32wl5_tim_ops, - .mode = STM32WL5_TIM_MODE_UNUSED, - .base = STM32WL5_TIM1_BASE, + .ops = &stm32_tim_ops, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM1_BASE, }; #endif -#ifdef CONFIG_STM32WL5_TIM2 -struct stm32wl5_tim_priv_s stm32wl5_tim2_priv = +#ifdef CONFIG_STM32_TIM2 +struct stm32_tim_priv_s stm32_tim2_priv = { - .ops = &stm32wl5_tim_ops, - .mode = STM32WL5_TIM_MODE_UNUSED, - .base = STM32WL5_TIM2_BASE, + .ops = &stm32_tim_ops, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM2_BASE, }; #endif -#ifdef CONFIG_STM32WL5_TIM3 -struct stm32wl5_tim_priv_s stm32wl5_tim3_priv = +#ifdef CONFIG_STM32_TIM3 +struct stm32_tim_priv_s stm32_tim3_priv = { - .ops = &stm32wl5_tim_ops, - .mode = STM32WL5_TIM_MODE_UNUSED, - .base = STM32WL5_TIM3_BASE, + .ops = &stm32_tim_ops, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM3_BASE, }; #endif -#ifdef CONFIG_STM32WL5_TIM4 -struct stm32wl5_tim_priv_s stm32wl5_tim4_priv = +#ifdef CONFIG_STM32_TIM4 +struct stm32_tim_priv_s stm32_tim4_priv = { - .ops = &stm32wl5_tim_ops, - .mode = STM32WL5_TIM_MODE_UNUSED, - .base = STM32WL5_TIM4_BASE, + .ops = &stm32_tim_ops, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM4_BASE, }; #endif -#ifdef CONFIG_STM32WL5_TIM5 -struct stm32wl5_tim_priv_s stm32wl5_tim5_priv = +#ifdef CONFIG_STM32_TIM5 +struct stm32_tim_priv_s stm32_tim5_priv = { - .ops = &stm32wl5_tim_ops, - .mode = STM32WL5_TIM_MODE_UNUSED, - .base = STM32WL5_TIM5_BASE, + .ops = &stm32_tim_ops, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM5_BASE, }; #endif -#ifdef CONFIG_STM32WL5_TIM6 -struct stm32wl5_tim_priv_s stm32wl5_tim6_priv = +#ifdef CONFIG_STM32_TIM6 +struct stm32_tim_priv_s stm32_tim6_priv = { - .ops = &stm32wl5_tim_ops, - .mode = STM32WL5_TIM_MODE_UNUSED, - .base = STM32WL5_TIM6_BASE, + .ops = &stm32_tim_ops, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM6_BASE, }; #endif -#ifdef CONFIG_STM32WL5_TIM7 -struct stm32wl5_tim_priv_s stm32wl5_tim7_priv = +#ifdef CONFIG_STM32_TIM7 +struct stm32_tim_priv_s stm32_tim7_priv = { - .ops = &stm32wl5_tim_ops, - .mode = STM32WL5_TIM_MODE_UNUSED, - .base = STM32WL5_TIM7_BASE, + .ops = &stm32_tim_ops, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM7_BASE, }; #endif -#ifdef CONFIG_STM32WL5_TIM8 -struct stm32wl5_tim_priv_s stm32wl5_tim8_priv = +#ifdef CONFIG_STM32_TIM8 +struct stm32_tim_priv_s stm32_tim8_priv = { - .ops = &stm32wl5_tim_ops, - .mode = STM32WL5_TIM_MODE_UNUSED, - .base = STM32WL5_TIM8_BASE, + .ops = &stm32_tim_ops, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM8_BASE, }; #endif -#ifdef CONFIG_STM32WL5_TIM15 -struct stm32wl5_tim_priv_s stm32wl5_tim15_priv = +#ifdef CONFIG_STM32_TIM15 +struct stm32_tim_priv_s stm32_tim15_priv = { - .ops = &stm32wl5_tim_ops, - .mode = STM32WL5_TIM_MODE_UNUSED, - .base = STM32WL5_TIM15_BASE, + .ops = &stm32_tim_ops, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM15_BASE, }; #endif -#ifdef CONFIG_STM32WL5_TIM16 -struct stm32wl5_tim_priv_s stm32wl5_tim16_priv = +#ifdef CONFIG_STM32_TIM16 +struct stm32_tim_priv_s stm32_tim16_priv = { - .ops = &stm32wl5_tim_ops, - .mode = STM32WL5_TIM_MODE_UNUSED, - .base = STM32WL5_TIM16_BASE, + .ops = &stm32_tim_ops, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM16_BASE, }; #endif -#ifdef CONFIG_STM32WL5_TIM17 -struct stm32wl5_tim_priv_s stm32wl5_tim17_priv = +#ifdef CONFIG_STM32_TIM17 +struct stm32_tim_priv_s stm32_tim17_priv = { - .ops = &stm32wl5_tim_ops, - .mode = STM32WL5_TIM_MODE_UNUSED, - .base = STM32WL5_TIM17_BASE, + .ops = &stm32_tim_ops, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM17_BASE, }; #endif @@ -405,51 +405,51 @@ struct stm32wl5_tim_priv_s stm32wl5_tim17_priv = ****************************************************************************/ /**************************************************************************** - * Name: stm32wl5_getreg16 + * Name: stm32_getreg16 * * Description: * Get a 16-bit register value by offset * ****************************************************************************/ -static inline uint16_t stm32wl5_getreg16(struct stm32wl5_tim_dev_s *dev, +static inline uint16_t stm32_getreg16(struct stm32_tim_dev_s *dev, uint8_t offset) { - return getreg16(((struct stm32wl5_tim_priv_s *)dev)->base + offset); + return getreg16(((struct stm32_tim_priv_s *)dev)->base + offset); } /**************************************************************************** - * Name: stm32wl5_putreg16 + * Name: stm32_putreg16 * * Description: * Put a 16-bit register value by offset * ****************************************************************************/ -static inline void stm32wl5_putreg16(struct stm32wl5_tim_dev_s *dev, +static inline void stm32_putreg16(struct stm32_tim_dev_s *dev, uint8_t offset, uint16_t value) { - putreg16(value, ((struct stm32wl5_tim_priv_s *)dev)->base + offset); + putreg16(value, ((struct stm32_tim_priv_s *)dev)->base + offset); } /**************************************************************************** - * Name: stm32wl5_modifyreg16 + * Name: stm32_modifyreg16 * * Description: * Modify a 16-bit register value by offset * ****************************************************************************/ -static inline void stm32wl5_modifyreg16(struct stm32wl5_tim_dev_s *dev, +static inline void stm32_modifyreg16(struct stm32_tim_dev_s *dev, uint8_t offset, uint16_t clearbits, uint16_t setbits) { - modifyreg16(((struct stm32wl5_tim_priv_s *)dev)->base + offset, clearbits, + modifyreg16(((struct stm32_tim_priv_s *)dev)->base + offset, clearbits, setbits); } /**************************************************************************** - * Name: stm32wl5_getreg32 + * Name: stm32_getreg32 * * Description: * Get a 32-bit register value by offset. This applies only for the @@ -457,14 +457,14 @@ static inline void stm32wl5_modifyreg16(struct stm32wl5_tim_dev_s *dev, * ****************************************************************************/ -static inline uint32_t stm32wl5_getreg32(struct stm32wl5_tim_dev_s *dev, +static inline uint32_t stm32_getreg32(struct stm32_tim_dev_s *dev, uint8_t offset) { - return getreg32(((struct stm32wl5_tim_priv_s *)dev)->base + offset); + return getreg32(((struct stm32_tim_priv_s *)dev)->base + offset); } /**************************************************************************** - * Name: stm32wl5_putreg32 + * Name: stm32_putreg32 * * Description: * Put a 32-bit register value by offset. This applies only for the @@ -472,48 +472,48 @@ static inline uint32_t stm32wl5_getreg32(struct stm32wl5_tim_dev_s *dev, * ****************************************************************************/ -static inline void stm32wl5_putreg32(struct stm32wl5_tim_dev_s *dev, +static inline void stm32_putreg32(struct stm32_tim_dev_s *dev, uint8_t offset, uint32_t value) { - putreg32(value, ((struct stm32wl5_tim_priv_s *)dev)->base + offset); + putreg32(value, ((struct stm32_tim_priv_s *)dev)->base + offset); } /**************************************************************************** - * Name: stm32wl5_tim_reload_counter + * Name: stm32_tim_reload_counter ****************************************************************************/ -static void stm32wl5_tim_reload_counter(struct stm32wl5_tim_dev_s *dev) +static void stm32_tim_reload_counter(struct stm32_tim_dev_s *dev) { - uint16_t val = stm32wl5_getreg16(dev, STM32WL5_GTIM_EGR_OFFSET); + uint16_t val = stm32_getreg16(dev, STM32_GTIM_EGR_OFFSET); val |= GTIM_EGR_UG; - stm32wl5_putreg16(dev, STM32WL5_GTIM_EGR_OFFSET, val); + stm32_putreg16(dev, STM32_GTIM_EGR_OFFSET, val); } /**************************************************************************** - * Name: stm32wl5_tim_enable + * Name: stm32_tim_enable ****************************************************************************/ -static void stm32wl5_tim_enable(struct stm32wl5_tim_dev_s *dev) +static void stm32_tim_enable(struct stm32_tim_dev_s *dev) { - uint16_t val = stm32wl5_getreg16(dev, STM32WL5_GTIM_CR1_OFFSET); + uint16_t val = stm32_getreg16(dev, STM32_GTIM_CR1_OFFSET); val |= GTIM_CR1_CEN; - stm32wl5_tim_reload_counter(dev); - stm32wl5_putreg16(dev, STM32WL5_GTIM_CR1_OFFSET, val); + stm32_tim_reload_counter(dev); + stm32_putreg16(dev, STM32_GTIM_CR1_OFFSET, val); } /**************************************************************************** - * Name: stm32wl5_tim_disable + * Name: stm32_tim_disable ****************************************************************************/ -static void stm32wl5_tim_disable(struct stm32wl5_tim_dev_s *dev) +static void stm32_tim_disable(struct stm32_tim_dev_s *dev) { - uint16_t val = stm32wl5_getreg16(dev, STM32WL5_GTIM_CR1_OFFSET); + uint16_t val = stm32_getreg16(dev, STM32_GTIM_CR1_OFFSET); val &= ~GTIM_CR1_CEN; - stm32wl5_putreg16(dev, STM32WL5_GTIM_CR1_OFFSET, val); + stm32_putreg16(dev, STM32_GTIM_CR1_OFFSET, val); } /**************************************************************************** - * Name: stm32wl5_tim_reset + * Name: stm32_tim_reset * * Description: * Reset timer into system default state, but do not affect output/input @@ -521,14 +521,14 @@ static void stm32wl5_tim_disable(struct stm32wl5_tim_dev_s *dev) * ****************************************************************************/ -static void stm32wl5_tim_reset(struct stm32wl5_tim_dev_s *dev) +static void stm32_tim_reset(struct stm32_tim_dev_s *dev) { - ((struct stm32wl5_tim_priv_s *)dev)->mode = STM32WL5_TIM_MODE_DISABLED; - stm32wl5_tim_disable(dev); + ((struct stm32_tim_priv_s *)dev)->mode = STM32_TIM_MODE_DISABLED; + stm32_tim_disable(dev); } /**************************************************************************** - * Name: stm32wl5_tim_gpioconfig + * Name: stm32_tim_gpioconfig ****************************************************************************/ #if defined(HAVE_TIM1_GPIOCONFIG) || defined(HAVE_TIM2_GPIOCONFIG) || \ @@ -536,28 +536,28 @@ static void stm32wl5_tim_reset(struct stm32wl5_tim_dev_s *dev) defined(HAVE_TIM5_GPIOCONFIG) || defined(HAVE_TIM8_GPIOCONFIG) || \ defined(HAVE_TIM15_GPIOCONFIG) || defined(HAVE_TIM16_GPIOCONFIG) || \ defined(HAVE_TIM17_GPIOCONFIG) -static void stm32wl5_tim_gpioconfig(uint32_t cfg, - enum stm32wl5_tim_channel_e mode) +static void stm32_tim_gpioconfig(uint32_t cfg, + enum stm32_tim_channel_e mode) { /* TODO: Add support for input capture and bipolar dual outputs for TIM8 */ - if (mode & STM32WL5_TIM_CH_MODE_MASK) + if (mode & STM32_TIM_CH_MODE_MASK) { - stm32wl5_configgpio(cfg); + stm32_configgpio(cfg); } else { - stm32wl5_unconfiggpio(cfg); + stm32_unconfiggpio(cfg); } } #endif /**************************************************************************** - * Name: stm32wl5_tim_setmode + * Name: stm32_tim_setmode ****************************************************************************/ -static int stm32wl5_tim_setmode(struct stm32wl5_tim_dev_s *dev, - enum stm32wl5_tim_mode_e mode) +static int stm32_tim_setmode(struct stm32_tim_dev_s *dev, + enum stm32_tim_mode_e mode) { uint16_t val = GTIM_CR1_CEN | GTIM_CR1_ARPE; @@ -567,13 +567,13 @@ static int stm32wl5_tim_setmode(struct stm32wl5_tim_dev_s *dev, * disable it, simply set its clock to valid frequency or zero. */ -#if STM32WL5_NBTIM > 0 - if (((struct stm32wl5_tim_priv_s *)dev)->base == STM32WL5_TIM6_BASE +#if STM32_NBTIM > 0 + if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM6_BASE #endif -#if STM32WL5_NBTIM > 1 - || ((struct stm32wl5_tim_priv_s *)dev)->base == STM32WL5_TIM7_BASE +#if STM32_NBTIM > 1 + || ((struct stm32_tim_priv_s *)dev)->base == STM32_TIM7_BASE #endif -#if STM32WL5_NBTIM > 0 +#if STM32_NBTIM > 0 ) { return -EINVAL; @@ -582,19 +582,19 @@ static int stm32wl5_tim_setmode(struct stm32wl5_tim_dev_s *dev, /* Decode operational modes */ - switch (mode & STM32WL5_TIM_MODE_MASK) + switch (mode & STM32_TIM_MODE_MASK) { - case STM32WL5_TIM_MODE_DISABLED: + case STM32_TIM_MODE_DISABLED: val = 0; break; - case STM32WL5_TIM_MODE_DOWN: + case STM32_TIM_MODE_DOWN: val |= GTIM_CR1_DIR; - case STM32WL5_TIM_MODE_UP: + case STM32_TIM_MODE_UP: break; - case STM32WL5_TIM_MODE_UPDOWN: + case STM32_TIM_MODE_UPDOWN: val |= GTIM_CR1_CENTER1; /* Our default: Interrupts are generated on compare, when counting @@ -603,7 +603,7 @@ static int stm32wl5_tim_setmode(struct stm32wl5_tim_dev_s *dev, break; - case STM32WL5_TIM_MODE_PULSE: + case STM32_TIM_MODE_PULSE: val |= GTIM_CR1_OPM; break; @@ -611,16 +611,16 @@ static int stm32wl5_tim_setmode(struct stm32wl5_tim_dev_s *dev, return -EINVAL; } - stm32wl5_tim_reload_counter(dev); - stm32wl5_putreg16(dev, STM32WL5_GTIM_CR1_OFFSET, val); + stm32_tim_reload_counter(dev); + stm32_putreg16(dev, STM32_GTIM_CR1_OFFSET, val); -#if STM32WL5_NATIM > 0 +#if STM32_NATIM > 0 /* Advanced registers require Main Output Enable */ - if (((struct stm32wl5_tim_priv_s *)dev)->base == STM32WL5_TIM1_BASE || - ((struct stm32wl5_tim_priv_s *)dev)->base == STM32WL5_TIM8_BASE) + if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM1_BASE || + ((struct stm32_tim_priv_s *)dev)->base == STM32_TIM8_BASE) { - stm32wl5_modifyreg16(dev, STM32WL5_ATIM_BDTR_OFFSET, + stm32_modifyreg16(dev, STM32_ATIM_BDTR_OFFSET, 0, ATIM_BDTR_MOE); } #endif @@ -629,10 +629,10 @@ static int stm32wl5_tim_setmode(struct stm32wl5_tim_dev_s *dev, } /**************************************************************************** - * Name: stm32wl5_tim_setclock + * Name: stm32_tim_setclock ****************************************************************************/ -static int stm32wl5_tim_setclock(struct stm32wl5_tim_dev_s *dev, +static int stm32_tim_setclock(struct stm32_tim_dev_s *dev, uint32_t freq) { uint32_t freqin; @@ -644,7 +644,7 @@ static int stm32wl5_tim_setclock(struct stm32wl5_tim_dev_s *dev, if (freq == 0) { - stm32wl5_tim_disable(dev); + stm32_tim_disable(dev); return 0; } @@ -654,69 +654,69 @@ static int stm32wl5_tim_setclock(struct stm32wl5_tim_dev_s *dev, * must be defined in the board.h header file. */ - switch (((struct stm32wl5_tim_priv_s *)dev)->base) + switch (((struct stm32_tim_priv_s *)dev)->base) { -#ifdef CONFIG_STM32WL5_TIM1 - case STM32WL5_TIM1_BASE: +#ifdef CONFIG_STM32_TIM1 + case STM32_TIM1_BASE: freqin = BOARD_TIM1_FREQUENCY; break; #endif -#ifdef CONFIG_STM32WL5_TIM2 - case STM32WL5_TIM2_BASE: +#ifdef CONFIG_STM32_TIM2 + case STM32_TIM2_BASE: freqin = BOARD_TIM2_FREQUENCY; break; #endif -#ifdef CONFIG_STM32WL5_TIM3 - case STM32WL5_TIM3_BASE: +#ifdef CONFIG_STM32_TIM3 + case STM32_TIM3_BASE: freqin = BOARD_TIM3_FREQUENCY; break; #endif -#ifdef CONFIG_STM32WL5_TIM4 - case STM32WL5_TIM4_BASE: +#ifdef CONFIG_STM32_TIM4 + case STM32_TIM4_BASE: freqin = BOARD_TIM4_FREQUENCY; break; #endif -#ifdef CONFIG_STM32WL5_TIM5 - case STM32WL5_TIM5_BASE: +#ifdef CONFIG_STM32_TIM5 + case STM32_TIM5_BASE: freqin = BOARD_TIM5_FREQUENCY; break; #endif -#ifdef CONFIG_STM32WL5_TIM6 - case STM32WL5_TIM6_BASE: +#ifdef CONFIG_STM32_TIM6 + case STM32_TIM6_BASE: freqin = BOARD_TIM6_FREQUENCY; break; #endif -#ifdef CONFIG_STM32WL5_TIM7 - case STM32WL5_TIM7_BASE: +#ifdef CONFIG_STM32_TIM7 + case STM32_TIM7_BASE: freqin = BOARD_TIM7_FREQUENCY; break; #endif -#ifdef CONFIG_STM32WL5_TIM8 - case STM32WL5_TIM8_BASE: +#ifdef CONFIG_STM32_TIM8 + case STM32_TIM8_BASE: freqin = BOARD_TIM8_FREQUENCY; break; #endif -#ifdef CONFIG_STM32WL5_TIM15 - case STM32WL5_TIM15_BASE: +#ifdef CONFIG_STM32_TIM15 + case STM32_TIM15_BASE: freqin = BOARD_TIM15_FREQUENCY; break; #endif -#ifdef CONFIG_STM32WL5_TIM16 - case STM32WL5_TIM16_BASE: +#ifdef CONFIG_STM32_TIM16 + case STM32_TIM16_BASE: freqin = BOARD_TIM16_FREQUENCY; break; #endif -#ifdef CONFIG_STM32WL5_TIM17 - case STM32WL5_TIM17_BASE: +#ifdef CONFIG_STM32_TIM17 + case STM32_TIM17_BASE: freqin = BOARD_TIM17_FREQUENCY; break; #endif @@ -747,17 +747,17 @@ static int stm32wl5_tim_setclock(struct stm32wl5_tim_dev_s *dev, prescaler = 0xffff; } - stm32wl5_putreg16(dev, STM32WL5_GTIM_PSC_OFFSET, prescaler); - stm32wl5_tim_enable(dev); + stm32_putreg16(dev, STM32_GTIM_PSC_OFFSET, prescaler); + stm32_tim_enable(dev); return prescaler; } /**************************************************************************** - * Name: stm32wl5_tim_getclock + * Name: stm32_tim_getclock ****************************************************************************/ -static uint32_t stm32wl5_tim_getclock(struct stm32wl5_tim_dev_s *dev) +static uint32_t stm32_tim_getclock(struct stm32_tim_dev_s *dev) { uint32_t freqin; uint32_t clock; @@ -769,67 +769,67 @@ static uint32_t stm32wl5_tim_getclock(struct stm32wl5_tim_dev_s *dev) * must be defined in the board.h header file. */ - switch (((struct stm32wl5_tim_priv_s *)dev)->base) + switch (((struct stm32_tim_priv_s *)dev)->base) { -#ifdef CONFIG_STM32WL5_TIM1 - case STM32WL5_TIM1_BASE: +#ifdef CONFIG_STM32_TIM1 + case STM32_TIM1_BASE: freqin = BOARD_TIM1_FREQUENCY; break; #endif -#ifdef CONFIG_STM32WL5_TIM2 - case STM32WL5_TIM2_BASE: +#ifdef CONFIG_STM32_TIM2 + case STM32_TIM2_BASE: freqin = BOARD_TIM2_FREQUENCY; break; #endif -#ifdef CONFIG_STM32WL5_TIM3 - case STM32WL5_TIM3_BASE: +#ifdef CONFIG_STM32_TIM3 + case STM32_TIM3_BASE: freqin = BOARD_TIM3_FREQUENCY; break; #endif -#ifdef CONFIG_STM32WL5_TIM4 - case STM32WL5_TIM4_BASE: +#ifdef CONFIG_STM32_TIM4 + case STM32_TIM4_BASE: freqin = BOARD_TIM4_FREQUENCY; break; #endif -#ifdef CONFIG_STM32WL5_TIM5 - case STM32WL5_TIM5_BASE: +#ifdef CONFIG_STM32_TIM5 + case STM32_TIM5_BASE: freqin = BOARD_TIM5_FREQUENCY; break; #endif -#ifdef CONFIG_STM32WL5_TIM6 - case STM32WL5_TIM6_BASE: +#ifdef CONFIG_STM32_TIM6 + case STM32_TIM6_BASE: freqin = BOARD_TIM6_FREQUENCY; break; #endif -#ifdef CONFIG_STM32WL5_TIM7 - case STM32WL5_TIM7_BASE: +#ifdef CONFIG_STM32_TIM7 + case STM32_TIM7_BASE: freqin = BOARD_TIM7_FREQUENCY; break; #endif -#ifdef CONFIG_STM32WL5_TIM8 - case STM32WL5_TIM8_BASE: +#ifdef CONFIG_STM32_TIM8 + case STM32_TIM8_BASE: freqin = BOARD_TIM8_FREQUENCY; break; #endif -#ifdef CONFIG_STM32WL5_TIM15 - case STM32WL5_TIM15_BASE: +#ifdef CONFIG_STM32_TIM15 + case STM32_TIM15_BASE: freqin = BOARD_TIM15_FREQUENCY; break; #endif -#ifdef CONFIG_STM32WL5_TIM16 - case STM32WL5_TIM16_BASE: +#ifdef CONFIG_STM32_TIM16 + case STM32_TIM16_BASE: freqin = BOARD_TIM16_FREQUENCY; break; #endif -#ifdef CONFIG_STM32WL5_TIM17 - case STM32WL5_TIM17_BASE: +#ifdef CONFIG_STM32_TIM17 + case STM32_TIM17_BASE: freqin = BOARD_TIM17_FREQUENCY; break; #endif @@ -839,52 +839,52 @@ static uint32_t stm32wl5_tim_getclock(struct stm32wl5_tim_dev_s *dev) /* From chip datasheet, at page 1179. */ - clock = freqin / (stm32wl5_getreg16(dev, STM32WL5_GTIM_PSC_OFFSET) + 1); + clock = freqin / (stm32_getreg16(dev, STM32_GTIM_PSC_OFFSET) + 1); return clock; } /**************************************************************************** - * Name: stm32wl5_tim_setperiod + * Name: stm32_tim_setperiod ****************************************************************************/ -static void stm32wl5_tim_setperiod(struct stm32wl5_tim_dev_s *dev, +static void stm32_tim_setperiod(struct stm32_tim_dev_s *dev, uint32_t period) { DEBUGASSERT(dev != NULL); - stm32wl5_putreg32(dev, STM32WL5_GTIM_ARR_OFFSET, period); + stm32_putreg32(dev, STM32_GTIM_ARR_OFFSET, period); } /**************************************************************************** - * Name: stm32wl5_tim_getperiod + * Name: stm32_tim_getperiod ****************************************************************************/ -static uint32_t stm32wl5_tim_getperiod (struct stm32wl5_tim_dev_s *dev) +static uint32_t stm32_tim_getperiod (struct stm32_tim_dev_s *dev) { DEBUGASSERT(dev != NULL); - return stm32wl5_getreg32 (dev, STM32WL5_GTIM_ARR_OFFSET); + return stm32_getreg32 (dev, STM32_GTIM_ARR_OFFSET); } /**************************************************************************** - * Name: stm32wl5_tim_getcounter + * Name: stm32_tim_getcounter ****************************************************************************/ -static uint32_t stm32wl5_tim_getcounter(struct stm32wl5_tim_dev_s *dev) +static uint32_t stm32_tim_getcounter(struct stm32_tim_dev_s *dev) { DEBUGASSERT(dev != NULL); - uint32_t counter = stm32wl5_getreg32(dev, STM32WL5_GTIM_CNT_OFFSET); + uint32_t counter = stm32_getreg32(dev, STM32_GTIM_CNT_OFFSET); /* In datasheet page 988, there is a useless bit named UIFCPY in TIMx_CNT. * reset it it result when not TIM2 or TIM5. */ -#if defined(CONFIG_STM32WL5_TIM2) || defined(CONFIG_STM32WL5_TIM5) - switch (((struct stm32wl5_tim_priv_s *)dev)->base) +#if defined(CONFIG_STM32_TIM2) || defined(CONFIG_STM32_TIM5) + switch (((struct stm32_tim_priv_s *)dev)->base) { -#ifdef CONFIG_STM32WL5_TIM2 - case STM32WL5_TIM2_BASE: +#ifdef CONFIG_STM32_TIM2 + case STM32_TIM2_BASE: #endif -#ifdef CONFIG_STM32WL5_TIM5 - case STM32WL5_TIM5_BASE: +#ifdef CONFIG_STM32_TIM5 + case STM32_TIM5_BASE: #endif return counter; @@ -897,18 +897,18 @@ static uint32_t stm32wl5_tim_getcounter(struct stm32wl5_tim_dev_s *dev) } /**************************************************************************** - * Name: stm32wl5_tim_setchannel + * Name: stm32_tim_setchannel ****************************************************************************/ -static int stm32wl5_tim_setchannel(struct stm32wl5_tim_dev_s *dev, +static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, uint8_t channel, - enum stm32wl5_tim_channel_e mode) + enum stm32_tim_channel_e mode) { uint16_t ccmr_orig = 0; uint16_t ccmr_val = 0; uint16_t ccmr_mask = 0xff; uint16_t ccer_val; - uint8_t ccmr_offset = STM32WL5_GTIM_CCMR1_OFFSET; + uint8_t ccmr_offset = STM32_GTIM_CCMR1_OFFSET; DEBUGASSERT(dev != NULL); @@ -921,7 +921,7 @@ static int stm32wl5_tim_setchannel(struct stm32wl5_tim_dev_s *dev, /* Assume that channel is disabled and polarity is active high */ - ccer_val = stm32wl5_getreg16(dev, STM32WL5_GTIM_CCER_OFFSET); + ccer_val = stm32_getreg16(dev, STM32_GTIM_CCER_OFFSET); ccer_val &= ~((GTIM_CCER_CC1P | GTIM_CCER_CC1E) << GTIM_CCER_CCXBASE(channel)); @@ -929,13 +929,13 @@ static int stm32wl5_tim_setchannel(struct stm32wl5_tim_dev_s *dev, * disable it, simply set its clock to valid frequency or zero. */ -#if STM32WL5_NBTIM > 0 - if (((struct stm32wl5_tim_priv_s *)dev)->base == STM32WL5_TIM6_BASE +#if STM32_NBTIM > 0 + if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM6_BASE #endif -#if STM32WL5_NBTIM > 1 - || ((struct stm32wl5_tim_priv_s *)dev)->base == STM32WL5_TIM7_BASE +#if STM32_NBTIM > 1 + || ((struct stm32_tim_priv_s *)dev)->base == STM32_TIM7_BASE #endif -#if STM32WL5_NBTIM > 0 +#if STM32_NBTIM > 0 ) { return -EINVAL; @@ -944,12 +944,12 @@ static int stm32wl5_tim_setchannel(struct stm32wl5_tim_dev_s *dev, /* Decode configuration */ - switch (mode & STM32WL5_TIM_CH_MODE_MASK) + switch (mode & STM32_TIM_CH_MODE_MASK) { - case STM32WL5_TIM_CH_DISABLED: + case STM32_TIM_CH_DISABLED: break; - case STM32WL5_TIM_CH_OUTPWM: + case STM32_TIM_CH_OUTPWM: ccmr_val = (GTIM_CCMR_MODE_PWM1 << GTIM_CCMR1_OC1M_SHIFT) + GTIM_CCMR1_OC1PE; ccer_val |= GTIM_CCER_CC1E << GTIM_CCER_CCXBASE(channel); @@ -961,7 +961,7 @@ static int stm32wl5_tim_setchannel(struct stm32wl5_tim_dev_s *dev, /* Set polarity */ - if (mode & STM32WL5_TIM_CH_POLARITY_NEG) + if (mode & STM32_TIM_CH_POLARITY_NEG) { ccer_val |= GTIM_CCER_CC1P << GTIM_CCER_CCXBASE(channel); } @@ -976,44 +976,44 @@ static int stm32wl5_tim_setchannel(struct stm32wl5_tim_dev_s *dev, if (channel > 1) { - ccmr_offset = STM32WL5_GTIM_CCMR2_OFFSET; + ccmr_offset = STM32_GTIM_CCMR2_OFFSET; } - ccmr_orig = stm32wl5_getreg16(dev, ccmr_offset); + ccmr_orig = stm32_getreg16(dev, ccmr_offset); ccmr_orig &= ~ccmr_mask; ccmr_orig |= ccmr_val; - stm32wl5_putreg16(dev, ccmr_offset, ccmr_orig); - stm32wl5_putreg16(dev, STM32WL5_GTIM_CCER_OFFSET, ccer_val); + stm32_putreg16(dev, ccmr_offset, ccmr_orig); + stm32_putreg16(dev, STM32_GTIM_CCER_OFFSET, ccer_val); /* set GPIO */ - switch (((struct stm32wl5_tim_priv_s *)dev)->base) + switch (((struct stm32_tim_priv_s *)dev)->base) { -#ifdef CONFIG_STM32WL5_TIM1 - case STM32WL5_TIM1_BASE: +#ifdef CONFIG_STM32_TIM1 + case STM32_TIM1_BASE: switch (channel) { #if defined(GPIO_TIM1_CH1OUT) case 0: - stm32wl5_tim_gpioconfig(GPIO_TIM1_CH1OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM1_CH1OUT, mode); break; #endif #if defined(GPIO_TIM1_CH2OUT) case 1: - stm32wl5_tim_gpioconfig(GPIO_TIM1_CH2OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM1_CH2OUT, mode); break; #endif #if defined(GPIO_TIM1_CH3OUT) case 2: - stm32wl5_tim_gpioconfig(GPIO_TIM1_CH3OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM1_CH3OUT, mode); break; #endif #if defined(GPIO_TIM1_CH4OUT) case 3: - stm32wl5_tim_gpioconfig(GPIO_TIM1_CH4OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM1_CH4OUT, mode); break; #endif @@ -1022,31 +1022,31 @@ static int stm32wl5_tim_setchannel(struct stm32wl5_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32WL5_TIM2 - case STM32WL5_TIM2_BASE: +#ifdef CONFIG_STM32_TIM2 + case STM32_TIM2_BASE: switch (channel) { #if defined(GPIO_TIM2_CH1OUT) case 0: - stm32wl5_tim_gpioconfig(GPIO_TIM2_CH1OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM2_CH1OUT, mode); break; #endif #if defined(GPIO_TIM2_CH2OUT) case 1: - stm32wl5_tim_gpioconfig(GPIO_TIM2_CH2OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM2_CH2OUT, mode); break; #endif #if defined(GPIO_TIM2_CH3OUT) case 2: - stm32wl5_tim_gpioconfig(GPIO_TIM2_CH3OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM2_CH3OUT, mode); break; #endif #if defined(GPIO_TIM2_CH4OUT) case 3: - stm32wl5_tim_gpioconfig(GPIO_TIM2_CH4OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM2_CH4OUT, mode); break; #endif @@ -1055,31 +1055,31 @@ static int stm32wl5_tim_setchannel(struct stm32wl5_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32WL5_TIM3 - case STM32WL5_TIM3_BASE: +#ifdef CONFIG_STM32_TIM3 + case STM32_TIM3_BASE: switch (channel) { #if defined(GPIO_TIM3_CH1OUT) case 0: - stm32wl5_tim_gpioconfig(GPIO_TIM3_CH1OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM3_CH1OUT, mode); break; #endif #if defined(GPIO_TIM3_CH2OUT) case 1: - stm32wl5_tim_gpioconfig(GPIO_TIM3_CH2OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM3_CH2OUT, mode); break; #endif #if defined(GPIO_TIM3_CH3OUT) case 2: - stm32wl5_tim_gpioconfig(GPIO_TIM3_CH3OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM3_CH3OUT, mode); break; #endif #if defined(GPIO_TIM3_CH4OUT) case 3: - stm32wl5_tim_gpioconfig(GPIO_TIM3_CH4OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM3_CH4OUT, mode); break; #endif @@ -1088,30 +1088,30 @@ static int stm32wl5_tim_setchannel(struct stm32wl5_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32WL5_TIM4 - case STM32WL5_TIM4_BASE: +#ifdef CONFIG_STM32_TIM4 + case STM32_TIM4_BASE: switch (channel) { #if defined(GPIO_TIM4_CH1OUT) case 0: - stm32wl5_tim_gpioconfig(GPIO_TIM4_CH1OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM4_CH1OUT, mode); break; #endif #if defined(GPIO_TIM4_CH2OUT) case 1: - stm32wl5_tim_gpioconfig(GPIO_TIM4_CH2OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM4_CH2OUT, mode); break; #endif #if defined(GPIO_TIM4_CH3OUT) case 2: - stm32wl5_tim_gpioconfig(GPIO_TIM4_CH3OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM4_CH3OUT, mode); break; #endif #if defined(GPIO_TIM4_CH4OUT) case 3: - stm32wl5_tim_gpioconfig(GPIO_TIM4_CH4OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM4_CH4OUT, mode); break; #endif @@ -1120,31 +1120,31 @@ static int stm32wl5_tim_setchannel(struct stm32wl5_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32WL5_TIM5 - case STM32WL5_TIM5_BASE: +#ifdef CONFIG_STM32_TIM5 + case STM32_TIM5_BASE: switch (channel) { #if defined(GPIO_TIM5_CH1OUT) case 0: - stm32wl5_tim_gpioconfig(GPIO_TIM5_CH1OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM5_CH1OUT, mode); break; #endif #if defined(GPIO_TIM5_CH2OUT) case 1: - stm32wl5_tim_gpioconfig(GPIO_TIM5_CH2OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM5_CH2OUT, mode); break; #endif #if defined(GPIO_TIM5_CH3OUT) case 2: - stm32wl5_tim_gpioconfig(GPIO_TIM5_CH3OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM5_CH3OUT, mode); break; #endif #if defined(GPIO_TIM5_CH4OUT) case 3: - stm32wl5_tim_gpioconfig(GPIO_TIM5_CH4OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM5_CH4OUT, mode); break; #endif @@ -1153,31 +1153,31 @@ static int stm32wl5_tim_setchannel(struct stm32wl5_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32WL5_TIM8 - case STM32WL5_TIM8_BASE: +#ifdef CONFIG_STM32_TIM8 + case STM32_TIM8_BASE: switch (channel) { #if defined(GPIO_TIM8_CH1OUT) case 0: - stm32wl5_tim_gpioconfig(GPIO_TIM8_CH1OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM8_CH1OUT, mode); break; #endif #if defined(GPIO_TIM8_CH2OUT) case 1: - stm32wl5_tim_gpioconfig(GPIO_TIM8_CH2OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM8_CH2OUT, mode); break; #endif #if defined(GPIO_TIM8_CH3OUT) case 2: - stm32wl5_tim_gpioconfig(GPIO_TIM8_CH3OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM8_CH3OUT, mode); break; #endif #if defined(GPIO_TIM8_CH4OUT) case 3: - stm32wl5_tim_gpioconfig(GPIO_TIM8_CH4OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM8_CH4OUT, mode); break; #endif @@ -1186,31 +1186,31 @@ static int stm32wl5_tim_setchannel(struct stm32wl5_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32WL5_TIM15 - case STM32WL5_TIM15_BASE: +#ifdef CONFIG_STM32_TIM15 + case STM32_TIM15_BASE: switch (channel) { #if defined(GPIO_TIM15_CH1OUT) case 0: - stm32wl5_tim_gpioconfig(GPIO_TIM15_CH1OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM15_CH1OUT, mode); break; #endif #if defined(GPIO_TIM15_CH2OUT) case 1: - stm32wl5_tim_gpioconfig(GPIO_TIM15_CH2OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM15_CH2OUT, mode); break; #endif #if defined(GPIO_TIM15_CH3OUT) case 2: - stm32wl5_tim_gpioconfig(GPIO_TIM15_CH3OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM15_CH3OUT, mode); break; #endif #if defined(GPIO_TIM15_CH4OUT) case 3: - stm32wl5_tim_gpioconfig(GPIO_TIM15_CH4OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM15_CH4OUT, mode); break; #endif @@ -1219,31 +1219,31 @@ static int stm32wl5_tim_setchannel(struct stm32wl5_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32WL5_TIM16 - case STM32WL5_TIM16_BASE: +#ifdef CONFIG_STM32_TIM16 + case STM32_TIM16_BASE: switch (channel) { #if defined(GPIO_TIM16_CH1OUT) case 0: - stm32wl5_tim_gpioconfig(GPIO_TIM16_CH1OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM16_CH1OUT, mode); break; #endif #if defined(GPIO_TIM16_CH2OUT) case 1: - stm32wl5_tim_gpioconfig(GPIO_TIM16_CH2OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM16_CH2OUT, mode); break; #endif #if defined(GPIO_TIM16_CH3OUT) case 2: - stm32wl5_tim_gpioconfig(GPIO_TIM16_CH3OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM16_CH3OUT, mode); break; #endif #if defined(GPIO_TIM16_CH4OUT) case 3: - stm32wl5_tim_gpioconfig(GPIO_TIM16_CH4OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM16_CH4OUT, mode); break; #endif @@ -1252,31 +1252,31 @@ static int stm32wl5_tim_setchannel(struct stm32wl5_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32WL5_TIM17 - case STM32WL5_TIM17_BASE: +#ifdef CONFIG_STM32_TIM17 + case STM32_TIM17_BASE: switch (channel) { #if defined(GPIO_TIM17_CH1OUT) case 0: - stm32wl5_tim_gpioconfig(GPIO_TIM17_CH1OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM17_CH1OUT, mode); break; #endif #if defined(GPIO_TIM17_CH2OUT) case 1: - stm32wl5_tim_gpioconfig(GPIO_TIM17_CH2OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM17_CH2OUT, mode); break; #endif #if defined(GPIO_TIM17_CH3OUT) case 2: - stm32wl5_tim_gpioconfig(GPIO_TIM17_CH3OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM17_CH3OUT, mode); break; #endif #if defined(GPIO_TIM17_CH4OUT) case 3: - stm32wl5_tim_gpioconfig(GPIO_TIM17_CH4OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM17_CH4OUT, mode); break; #endif @@ -1294,10 +1294,10 @@ static int stm32wl5_tim_setchannel(struct stm32wl5_tim_dev_s *dev, } /**************************************************************************** - * Name: stm32wl5_tim_setcompare + * Name: stm32_tim_setcompare ****************************************************************************/ -static int stm32wl5_tim_setcompare(struct stm32wl5_tim_dev_s *dev, +static int stm32_tim_setcompare(struct stm32_tim_dev_s *dev, uint8_t channel, uint32_t compare) { DEBUGASSERT(dev != NULL); @@ -1305,19 +1305,19 @@ static int stm32wl5_tim_setcompare(struct stm32wl5_tim_dev_s *dev, switch (channel) { case 1: - stm32wl5_putreg32(dev, STM32WL5_GTIM_CCR1_OFFSET, compare); + stm32_putreg32(dev, STM32_GTIM_CCR1_OFFSET, compare); break; case 2: - stm32wl5_putreg32(dev, STM32WL5_GTIM_CCR2_OFFSET, compare); + stm32_putreg32(dev, STM32_GTIM_CCR2_OFFSET, compare); break; case 3: - stm32wl5_putreg32(dev, STM32WL5_GTIM_CCR3_OFFSET, compare); + stm32_putreg32(dev, STM32_GTIM_CCR3_OFFSET, compare); break; case 4: - stm32wl5_putreg32(dev, STM32WL5_GTIM_CCR4_OFFSET, compare); + stm32_putreg32(dev, STM32_GTIM_CCR4_OFFSET, compare); break; default: @@ -1328,10 +1328,10 @@ static int stm32wl5_tim_setcompare(struct stm32wl5_tim_dev_s *dev, } /**************************************************************************** - * Name: stm32wl5_tim_getcapture + * Name: stm32_tim_getcapture ****************************************************************************/ -static int stm32wl5_tim_getcapture(struct stm32wl5_tim_dev_s *dev, +static int stm32_tim_getcapture(struct stm32_tim_dev_s *dev, uint8_t channel) { DEBUGASSERT(dev != NULL); @@ -1339,26 +1339,26 @@ static int stm32wl5_tim_getcapture(struct stm32wl5_tim_dev_s *dev, switch (channel) { case 1: - return stm32wl5_getreg32(dev, STM32WL5_GTIM_CCR1_OFFSET); + return stm32_getreg32(dev, STM32_GTIM_CCR1_OFFSET); case 2: - return stm32wl5_getreg32(dev, STM32WL5_GTIM_CCR2_OFFSET); + return stm32_getreg32(dev, STM32_GTIM_CCR2_OFFSET); case 3: - return stm32wl5_getreg32(dev, STM32WL5_GTIM_CCR3_OFFSET); + return stm32_getreg32(dev, STM32_GTIM_CCR3_OFFSET); case 4: - return stm32wl5_getreg32(dev, STM32WL5_GTIM_CCR4_OFFSET); + return stm32_getreg32(dev, STM32_GTIM_CCR4_OFFSET); } return -EINVAL; } /**************************************************************************** - * Name: stm32wl5_tim_setisr + * Name: stm32_tim_setisr ****************************************************************************/ -static int stm32wl5_tim_setisr(struct stm32wl5_tim_dev_s *dev, +static int stm32_tim_setisr(struct stm32_tim_dev_s *dev, xcpt_t handler, void *arg, int source) { int vectorno; @@ -1366,69 +1366,69 @@ static int stm32wl5_tim_setisr(struct stm32wl5_tim_dev_s *dev, DEBUGASSERT(dev != NULL); DEBUGASSERT(source == 0); - switch (((struct stm32wl5_tim_priv_s *)dev)->base) + switch (((struct stm32_tim_priv_s *)dev)->base) { -#ifdef CONFIG_STM32WL5_TIM1 - case STM32WL5_TIM1_BASE: - vectorno = STM32WL5_IRQ_TIM1UP; +#ifdef CONFIG_STM32_TIM1 + case STM32_TIM1_BASE: + vectorno = STM32_IRQ_TIM1UP; break; #endif -#ifdef CONFIG_STM32WL5_TIM2 - case STM32WL5_TIM2_BASE: - vectorno = STM32WL5_IRQ_TIM2; +#ifdef CONFIG_STM32_TIM2 + case STM32_TIM2_BASE: + vectorno = STM32_IRQ_TIM2; break; #endif -#ifdef CONFIG_STM32WL5_TIM3 - case STM32WL5_TIM3_BASE: - vectorno = STM32WL5_IRQ_TIM3; +#ifdef CONFIG_STM32_TIM3 + case STM32_TIM3_BASE: + vectorno = STM32_IRQ_TIM3; break; #endif -#ifdef CONFIG_STM32WL5_TIM4 - case STM32WL5_TIM4_BASE: - vectorno = STM32WL5_IRQ_TIM4; +#ifdef CONFIG_STM32_TIM4 + case STM32_TIM4_BASE: + vectorno = STM32_IRQ_TIM4; break; #endif -#ifdef CONFIG_STM32WL5_TIM5 - case STM32WL5_TIM5_BASE: - vectorno = STM32WL5_IRQ_TIM5; +#ifdef CONFIG_STM32_TIM5 + case STM32_TIM5_BASE: + vectorno = STM32_IRQ_TIM5; break; #endif -#ifdef CONFIG_STM32WL5_TIM6 - case STM32WL5_TIM6_BASE: - vectorno = STM32WL5_IRQ_TIM6; +#ifdef CONFIG_STM32_TIM6 + case STM32_TIM6_BASE: + vectorno = STM32_IRQ_TIM6; break; #endif -#ifdef CONFIG_STM32WL5_TIM7 - case STM32WL5_TIM7_BASE: - vectorno = STM32WL5_IRQ_TIM7; +#ifdef CONFIG_STM32_TIM7 + case STM32_TIM7_BASE: + vectorno = STM32_IRQ_TIM7; break; #endif -#ifdef CONFIG_STM32WL5_TIM8 - case STM32WL5_TIM8_BASE: - vectorno = STM32WL5_IRQ_TIM8UP; +#ifdef CONFIG_STM32_TIM8 + case STM32_TIM8_BASE: + vectorno = STM32_IRQ_TIM8UP; break; #endif -#ifdef CONFIG_STM32WL5_TIM15 - case STM32WL5_TIM15_BASE: - vectorno = STM32WL5_IRQ_TIM15; +#ifdef CONFIG_STM32_TIM15 + case STM32_TIM15_BASE: + vectorno = STM32_IRQ_TIM15; break; #endif -#ifdef CONFIG_STM32WL5_TIM16 - case STM32WL5_TIM16_BASE: - vectorno = STM32WL5_IRQ_TIM16; +#ifdef CONFIG_STM32_TIM16 + case STM32_TIM16_BASE: + vectorno = STM32_IRQ_TIM16; break; #endif -#ifdef CONFIG_STM32WL5_TIM17 - case STM32WL5_TIM17_BASE: - vectorno = STM32WL5_IRQ_TIM17; +#ifdef CONFIG_STM32_TIM17 + case STM32_TIM17_BASE: + vectorno = STM32_IRQ_TIM17; break; #endif @@ -1454,44 +1454,44 @@ static int stm32wl5_tim_setisr(struct stm32wl5_tim_dev_s *dev, } /**************************************************************************** - * Name: stm32wl5_tim_enableint + * Name: stm32_tim_enableint ****************************************************************************/ -static void stm32wl5_tim_enableint(struct stm32wl5_tim_dev_s *dev, +static void stm32_tim_enableint(struct stm32_tim_dev_s *dev, int source) { DEBUGASSERT(dev != NULL); - stm32wl5_modifyreg16(dev, STM32WL5_GTIM_DIER_OFFSET, 0, GTIM_DIER_UIE); + stm32_modifyreg16(dev, STM32_GTIM_DIER_OFFSET, 0, GTIM_DIER_UIE); } /**************************************************************************** - * Name: stm32wl5_tim_disableint + * Name: stm32_tim_disableint ****************************************************************************/ -static void stm32wl5_tim_disableint(struct stm32wl5_tim_dev_s *dev, +static void stm32_tim_disableint(struct stm32_tim_dev_s *dev, int source) { DEBUGASSERT(dev != NULL); - stm32wl5_modifyreg16(dev, STM32WL5_GTIM_DIER_OFFSET, GTIM_DIER_UIE, 0); + stm32_modifyreg16(dev, STM32_GTIM_DIER_OFFSET, GTIM_DIER_UIE, 0); } /**************************************************************************** - * Name: stm32wl5_tim_ackint + * Name: stm32_tim_ackint ****************************************************************************/ -static void stm32wl5_tim_ackint(struct stm32wl5_tim_dev_s *dev, int source) +static void stm32_tim_ackint(struct stm32_tim_dev_s *dev, int source) { - stm32wl5_putreg16(dev, STM32WL5_GTIM_SR_OFFSET, ~GTIM_SR_UIF); + stm32_putreg16(dev, STM32_GTIM_SR_OFFSET, ~GTIM_SR_UIF); } /**************************************************************************** - * Name: stm32wl5_tim_checkint + * Name: stm32_tim_checkint ****************************************************************************/ -static int stm32wl5_tim_checkint(struct stm32wl5_tim_dev_s *dev, +static int stm32_tim_checkint(struct stm32_tim_dev_s *dev, int source) { - uint16_t regval = stm32wl5_getreg16(dev, STM32WL5_GTIM_SR_OFFSET); + uint16_t regval = stm32_getreg16(dev, STM32_GTIM_SR_OFFSET); return (regval & GTIM_SR_UIF) ? 1 : 0; } @@ -1500,90 +1500,90 @@ static int stm32wl5_tim_checkint(struct stm32wl5_tim_dev_s *dev, ****************************************************************************/ /**************************************************************************** - * Name: stm32wl5_tim_init + * Name: stm32_tim_init ****************************************************************************/ -struct stm32wl5_tim_dev_s *stm32wl5_tim_init(int timer) +struct stm32_tim_dev_s *stm32_tim_init(int timer) { - struct stm32wl5_tim_dev_s *dev = NULL; + struct stm32_tim_dev_s *dev = NULL; /* Get structure and enable power */ switch (timer) { -#ifdef CONFIG_STM32WL5_TIM1 +#ifdef CONFIG_STM32_TIM1 case 1: - dev = (struct stm32wl5_tim_dev_s *)&stm32wl5_tim1_priv; - modifyreg32(STM32WL5_RCC_APB2ENR, 0, RCC_APB2ENR_TIM1EN); + dev = (struct stm32_tim_dev_s *)&stm32_tim1_priv; + modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM1EN); break; #endif -#ifdef CONFIG_STM32WL5_TIM2 +#ifdef CONFIG_STM32_TIM2 case 2: - dev = (struct stm32wl5_tim_dev_s *)&stm32wl5_tim2_priv; - modifyreg32(STM32WL5_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM2EN); + dev = (struct stm32_tim_dev_s *)&stm32_tim2_priv; + modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM2EN); break; #endif -#ifdef CONFIG_STM32WL5_TIM3 +#ifdef CONFIG_STM32_TIM3 case 3: - dev = (struct stm32wl5_tim_dev_s *)&stm32wl5_tim3_priv; - modifyreg32(STM32WL5_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM3EN); + dev = (struct stm32_tim_dev_s *)&stm32_tim3_priv; + modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM3EN); break; #endif -#ifdef CONFIG_STM32WL5_TIM4 +#ifdef CONFIG_STM32_TIM4 case 4: - dev = (struct stm32wl5_tim_dev_s *)&stm32wl5_tim4_priv; - modifyreg32(STM32WL5_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM4EN); + dev = (struct stm32_tim_dev_s *)&stm32_tim4_priv; + modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM4EN); break; #endif -#ifdef CONFIG_STM32WL5_TIM5 +#ifdef CONFIG_STM32_TIM5 case 5: - dev = (struct stm32wl5_tim_dev_s *)&stm32wl5_tim5_priv; - modifyreg32(STM32WL5_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM5EN); + dev = (struct stm32_tim_dev_s *)&stm32_tim5_priv; + modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM5EN); break; #endif -#ifdef CONFIG_STM32WL5_TIM6 +#ifdef CONFIG_STM32_TIM6 case 6: - dev = (struct stm32wl5_tim_dev_s *)&stm32wl5_tim6_priv; - modifyreg32(STM32WL5_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM6EN); + dev = (struct stm32_tim_dev_s *)&stm32_tim6_priv; + modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM6EN); break; #endif -#ifdef CONFIG_STM32WL5_TIM7 +#ifdef CONFIG_STM32_TIM7 case 7: - dev = (struct stm32wl5_tim_dev_s *)&stm32wl5_tim7_priv; - modifyreg32(STM32WL5_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM7EN); + dev = (struct stm32_tim_dev_s *)&stm32_tim7_priv; + modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM7EN); break; #endif -#ifdef CONFIG_STM32WL5_TIM8 +#ifdef CONFIG_STM32_TIM8 case 8: - dev = (struct stm32wl5_tim_dev_s *)&stm32wl5_tim8_priv; - modifyreg32(STM32WL5_RCC_APB2ENR, 0, RCC_APB2ENR_TIM8EN); + dev = (struct stm32_tim_dev_s *)&stm32_tim8_priv; + modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM8EN); break; #endif -#ifdef CONFIG_STM32WL5_TIM15 +#ifdef CONFIG_STM32_TIM15 case 15: - dev = (struct stm32wl5_tim_dev_s *)&stm32wl5_tim15_priv; - modifyreg32(STM32WL5_RCC_APB2ENR, 0, RCC_APB2ENR_TIM15EN); + dev = (struct stm32_tim_dev_s *)&stm32_tim15_priv; + modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM15EN); break; #endif -#ifdef CONFIG_STM32WL5_TIM16 +#ifdef CONFIG_STM32_TIM16 case 16: - dev = (struct stm32wl5_tim_dev_s *)&stm32wl5_tim16_priv; - modifyreg32(STM32WL5_RCC_APB2ENR, 0, RCC_APB2ENR_TIM16EN); + dev = (struct stm32_tim_dev_s *)&stm32_tim16_priv; + modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM16EN); break; #endif -#ifdef CONFIG_STM32WL5_TIM17 +#ifdef CONFIG_STM32_TIM17 case 17: - dev = (struct stm32wl5_tim_dev_s *)&stm32wl5_tim17_priv; - modifyreg32(STM32WL5_RCC_APB2ENR, 0, RCC_APB2ENR_TIM17EN); + dev = (struct stm32_tim_dev_s *)&stm32_tim17_priv; + modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM17EN); break; #endif @@ -1593,93 +1593,93 @@ struct stm32wl5_tim_dev_s *stm32wl5_tim_init(int timer) /* Is device already allocated */ - if (((struct stm32wl5_tim_priv_s *)dev)->mode != STM32WL5_TIM_MODE_UNUSED) + if (((struct stm32_tim_priv_s *)dev)->mode != STM32_TIM_MODE_UNUSED) { return NULL; } - stm32wl5_tim_reset(dev); + stm32_tim_reset(dev); return dev; } /**************************************************************************** - * Name: stm32wl5_tim_deinit + * Name: stm32_tim_deinit * * TODO: Detach interrupts, and close down all TIM Channels * ****************************************************************************/ -int stm32wl5_tim_deinit(struct stm32wl5_tim_dev_s *dev) +int stm32_tim_deinit(struct stm32_tim_dev_s *dev) { DEBUGASSERT(dev != NULL); /* Disable power */ - switch (((struct stm32wl5_tim_priv_s *)dev)->base) + switch (((struct stm32_tim_priv_s *)dev)->base) { -#ifdef CONFIG_STM32WL5_TIM1 - case STM32WL5_TIM1_BASE: - modifyreg32(STM32WL5_RCC_APB2ENR, RCC_APB2ENR_TIM1EN, 0); +#ifdef CONFIG_STM32_TIM1 + case STM32_TIM1_BASE: + modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM1EN, 0); break; #endif -#ifdef CONFIG_STM32WL5_TIM2 - case STM32WL5_TIM2_BASE: - modifyreg32(STM32WL5_RCC_APB1ENR1, RCC_APB1ENR1_TIM2EN, 0); +#ifdef CONFIG_STM32_TIM2 + case STM32_TIM2_BASE: + modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM2EN, 0); break; #endif -#ifdef CONFIG_STM32WL5_TIM3 - case STM32WL5_TIM3_BASE: - modifyreg32(STM32WL5_RCC_APB1ENR1, RCC_APB1ENR1_TIM3EN, 0); +#ifdef CONFIG_STM32_TIM3 + case STM32_TIM3_BASE: + modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM3EN, 0); break; #endif -#ifdef CONFIG_STM32WL5_TIM4 - case STM32WL5_TIM4_BASE: - modifyreg32(STM32WL5_RCC_APB1ENR1, RCC_APB1ENR1_TIM4EN, 0); +#ifdef CONFIG_STM32_TIM4 + case STM32_TIM4_BASE: + modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM4EN, 0); break; #endif -#ifdef CONFIG_STM32WL5_TIM5 - case STM32WL5_TIM5_BASE: - modifyreg32(STM32WL5_RCC_APB1ENR1, RCC_APB1ENR1_TIM5EN, 0); +#ifdef CONFIG_STM32_TIM5 + case STM32_TIM5_BASE: + modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM5EN, 0); break; #endif -#ifdef CONFIG_STM32WL5_TIM6 - case STM32WL5_TIM6_BASE: - modifyreg32(STM32WL5_RCC_APB1ENR1, RCC_APB1ENR1_TIM6EN, 0); +#ifdef CONFIG_STM32_TIM6 + case STM32_TIM6_BASE: + modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM6EN, 0); break; #endif -#ifdef CONFIG_STM32WL5_TIM7 - case STM32WL5_TIM7_BASE: - modifyreg32(STM32WL5_RCC_APB1ENR1, RCC_APB1ENR1_TIM7EN, 0); +#ifdef CONFIG_STM32_TIM7 + case STM32_TIM7_BASE: + modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM7EN, 0); break; #endif -#ifdef CONFIG_STM32WL5_TIM8 - case STM32WL5_TIM8_BASE: - modifyreg32(STM32WL5_RCC_APB2ENR, RCC_APB2ENR_TIM8EN, 0); +#ifdef CONFIG_STM32_TIM8 + case STM32_TIM8_BASE: + modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM8EN, 0); break; #endif -#ifdef CONFIG_STM32WL5_TIM15 - case STM32WL5_TIM15_BASE: - modifyreg32(STM32WL5_RCC_APB2ENR, RCC_APB2ENR_TIM15EN, 0); +#ifdef CONFIG_STM32_TIM15 + case STM32_TIM15_BASE: + modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM15EN, 0); break; #endif -#ifdef CONFIG_STM32WL5_TIM16 - case STM32WL5_TIM16_BASE: - modifyreg32(STM32WL5_RCC_APB2ENR, RCC_APB2ENR_TIM16EN, 0); +#ifdef CONFIG_STM32_TIM16 + case STM32_TIM16_BASE: + modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM16EN, 0); break; #endif -#ifdef CONFIG_STM32WL5_TIM17 - case STM32WL5_TIM17_BASE: - modifyreg32(STM32WL5_RCC_APB2ENR, RCC_APB2ENR_TIM17EN, 0); +#ifdef CONFIG_STM32_TIM17 + case STM32_TIM17_BASE: + modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM17EN, 0); break; #endif @@ -1689,9 +1689,9 @@ int stm32wl5_tim_deinit(struct stm32wl5_tim_dev_s *dev) /* Mark it as free */ - ((struct stm32wl5_tim_priv_s *)dev)->mode = STM32WL5_TIM_MODE_UNUSED; + ((struct stm32_tim_priv_s *)dev)->mode = STM32_TIM_MODE_UNUSED; return OK; } -#endif /* defined(CONFIG_STM32WL5_TIM1 || ... || TIM17) */ +#endif /* defined(CONFIG_STM32_TIM1 || ... || TIM17) */ diff --git a/arch/arm/src/stm32wl5/stm32wl5_tim.h b/arch/arm/src/stm32wl5/stm32wl5_tim.h index 9826600b87ab0..7bdffaa7800fa 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_tim.h +++ b/arch/arm/src/stm32wl5/stm32wl5_tim.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32WL5_STM32WL5_TIM_H -#define __ARCH_ARM_SRC_STM32WL5_STM32WL5_TIM_H +#ifndef __ARCH_ARM_SRC_STM32WL5_STM32_TIM_H +#define __ARCH_ARM_SRC_STM32WL5_STM32_TIM_H /**************************************************************************** * Included Files @@ -38,20 +38,20 @@ /* Helpers ******************************************************************/ -#define STM32WL5_TIM_SETMODE(d,mode) ((d)->ops->setmode(d,mode)) -#define STM32WL5_TIM_SETCLOCK(d,freq) ((d)->ops->setclock(d,freq)) -#define STM32WL5_TIM_GETCLOCK(d) ((d)->ops->getclock(d)) -#define STM32WL5_TIM_SETPERIOD(d,period) ((d)->ops->setperiod(d,period)) -#define STM32WL5_TIM_GETPERIOD(d) ((d)->ops->getperiod(d)) -#define STM32WL5_TIM_GETCOUNTER(d) ((d)->ops->getcounter(d)) -#define STM32WL5_TIM_SETCHANNEL(d,ch,mode) ((d)->ops->setchannel(d,ch,mode)) -#define STM32WL5_TIM_SETCOMPARE(d,ch,comp) ((d)->ops->setcompare(d,ch,comp)) -#define STM32WL5_TIM_GETCAPTURE(d,ch) ((d)->ops->getcapture(d,ch)) -#define STM32WL5_TIM_SETISR(d,hnd,arg,s) ((d)->ops->setisr(d,hnd,arg,s)) -#define STM32WL5_TIM_ENABLEINT(d,s) ((d)->ops->enableint(d,s)) -#define STM32WL5_TIM_DISABLEINT(d,s) ((d)->ops->disableint(d,s)) -#define STM32WL5_TIM_ACKINT(d,s) ((d)->ops->ackint(d,s)) -#define STM32WL5_TIM_CHECKINT(d,s) ((d)->ops->checkint(d,s)) +#define STM32_TIM_SETMODE(d,mode) ((d)->ops->setmode(d,mode)) +#define STM32_TIM_SETCLOCK(d,freq) ((d)->ops->setclock(d,freq)) +#define STM32_TIM_GETCLOCK(d) ((d)->ops->getclock(d)) +#define STM32_TIM_SETPERIOD(d,period) ((d)->ops->setperiod(d,period)) +#define STM32_TIM_GETPERIOD(d) ((d)->ops->getperiod(d)) +#define STM32_TIM_GETCOUNTER(d) ((d)->ops->getcounter(d)) +#define STM32_TIM_SETCHANNEL(d,ch,mode) ((d)->ops->setchannel(d,ch,mode)) +#define STM32_TIM_SETCOMPARE(d,ch,comp) ((d)->ops->setcompare(d,ch,comp)) +#define STM32_TIM_GETCAPTURE(d,ch) ((d)->ops->getcapture(d,ch)) +#define STM32_TIM_SETISR(d,hnd,arg,s) ((d)->ops->setisr(d,hnd,arg,s)) +#define STM32_TIM_ENABLEINT(d,s) ((d)->ops->enableint(d,s)) +#define STM32_TIM_DISABLEINT(d,s) ((d)->ops->disableint(d,s)) +#define STM32_TIM_ACKINT(d,s) ((d)->ops->ackint(d,s)) +#define STM32_TIM_CHECKINT(d,s) ((d)->ops->checkint(d,s)) #define STM32_TIM_ENABLE(d) ((d)->ops->enable(d)) #define STM32_TIM_DISABLE(d) ((d)->ops->disable(d)) @@ -72,43 +72,43 @@ extern "C" /* TIM Device Structure */ -struct stm32wl5_tim_dev_s +struct stm32_tim_dev_s { - struct stm32wl5_tim_ops_s *ops; + struct stm32_tim_ops_s *ops; }; /* TIM Modes of Operation */ -enum stm32wl5_tim_mode_e +enum stm32_tim_mode_e { - STM32WL5_TIM_MODE_UNUSED = -1, + STM32_TIM_MODE_UNUSED = -1, /* One of the following */ - STM32WL5_TIM_MODE_MASK = 0x0310, - STM32WL5_TIM_MODE_DISABLED = 0x0000, - STM32WL5_TIM_MODE_UP = 0x0100, - STM32WL5_TIM_MODE_DOWN = 0x0110, - STM32WL5_TIM_MODE_UPDOWN = 0x0200, - STM32WL5_TIM_MODE_PULSE = 0x0300, + STM32_TIM_MODE_MASK = 0x0310, + STM32_TIM_MODE_DISABLED = 0x0000, + STM32_TIM_MODE_UP = 0x0100, + STM32_TIM_MODE_DOWN = 0x0110, + STM32_TIM_MODE_UPDOWN = 0x0200, + STM32_TIM_MODE_PULSE = 0x0300, /* One of the following */ - STM32WL5_TIM_MODE_CK_INT = 0x0000, + STM32_TIM_MODE_CK_INT = 0x0000, #if 0 - STM32WL5_TIM_MODE_CK_INT_TRIG = 0x0400, - STM32WL5_TIM_MODE_CK_EXT = 0x0800, - STM32WL5_TIM_MODE_CK_EXT_TRIG = 0x0c00, + STM32_TIM_MODE_CK_INT_TRIG = 0x0400, + STM32_TIM_MODE_CK_EXT = 0x0800, + STM32_TIM_MODE_CK_EXT_TRIG = 0x0c00, #endif /* Clock sources, OR'ed with CK_EXT */ #if 0 - STM32WL5_TIM_MODE_CK_CHINVALID = 0x0000, - STM32WL5_TIM_MODE_CK_CH1 = 0x0001, - STM32WL5_TIM_MODE_CK_CH2 = 0x0002, - STM32WL5_TIM_MODE_CK_CH3 = 0x0003, - STM32WL5_TIM_MODE_CK_CH4 = 0x0004 + STM32_TIM_MODE_CK_CHINVALID = 0x0000, + STM32_TIM_MODE_CK_CH1 = 0x0001, + STM32_TIM_MODE_CK_CH2 = 0x0002, + STM32_TIM_MODE_CK_CH3 = 0x0003, + STM32_TIM_MODE_CK_CH4 = 0x0004 #endif /* Todo: external trigger block */ @@ -116,59 +116,59 @@ enum stm32wl5_tim_mode_e /* TIM Channel Modes */ -enum stm32wl5_tim_channel_e +enum stm32_tim_channel_e { - STM32WL5_TIM_CH_DISABLED = 0x00, + STM32_TIM_CH_DISABLED = 0x00, /* Common configuration */ - STM32WL5_TIM_CH_POLARITY_POS = 0x00, - STM32WL5_TIM_CH_POLARITY_NEG = 0x01, + STM32_TIM_CH_POLARITY_POS = 0x00, + STM32_TIM_CH_POLARITY_NEG = 0x01, /* MODES: */ - STM32WL5_TIM_CH_MODE_MASK = 0x06, + STM32_TIM_CH_MODE_MASK = 0x06, /* Output Compare Modes */ - STM32WL5_TIM_CH_OUTPWM = 0x04, /* Enable standard PWM mode, active high when counter < compare */ + STM32_TIM_CH_OUTPWM = 0x04, /* Enable standard PWM mode, active high when counter < compare */ #if 0 - STM32WL5_TIM_CH_OUTCOMPARE = 0x06, + STM32_TIM_CH_OUTCOMPARE = 0x06, #endif }; /* TIM Operations */ -struct stm32wl5_tim_ops_s +struct stm32_tim_ops_s { /* Basic Timers */ - void (*enable)(struct stm32wl5_tim_dev_s *dev); - void (*disable)(struct stm32wl5_tim_dev_s *dev); - int (*setmode)(struct stm32wl5_tim_dev_s *dev, - enum stm32wl5_tim_mode_e mode); - int (*setclock)(struct stm32wl5_tim_dev_s *dev, uint32_t freq); - uint32_t (*getclock)(struct stm32wl5_tim_dev_s *dev); - void (*setperiod)(struct stm32wl5_tim_dev_s *dev, uint32_t period); - uint32_t (*getperiod)(struct stm32wl5_tim_dev_s *dev); - uint32_t (*getcounter)(struct stm32wl5_tim_dev_s *dev); + void (*enable)(struct stm32_tim_dev_s *dev); + void (*disable)(struct stm32_tim_dev_s *dev); + int (*setmode)(struct stm32_tim_dev_s *dev, + enum stm32_tim_mode_e mode); + int (*setclock)(struct stm32_tim_dev_s *dev, uint32_t freq); + uint32_t (*getclock)(struct stm32_tim_dev_s *dev); + void (*setperiod)(struct stm32_tim_dev_s *dev, uint32_t period); + uint32_t (*getperiod)(struct stm32_tim_dev_s *dev); + uint32_t (*getcounter)(struct stm32_tim_dev_s *dev); /* General and Advanced Timers Adds */ - int (*setchannel)(struct stm32wl5_tim_dev_s *dev, uint8_t channel, - enum stm32wl5_tim_channel_e mode); - int (*setcompare)(struct stm32wl5_tim_dev_s *dev, uint8_t channel, + int (*setchannel)(struct stm32_tim_dev_s *dev, uint8_t channel, + enum stm32_tim_channel_e mode); + int (*setcompare)(struct stm32_tim_dev_s *dev, uint8_t channel, uint32_t compare); - int (*getcapture)(struct stm32wl5_tim_dev_s *dev, uint8_t channel); + int (*getcapture)(struct stm32_tim_dev_s *dev, uint8_t channel); /* Timer interrupts */ - int (*setisr)(struct stm32wl5_tim_dev_s *dev, + int (*setisr)(struct stm32_tim_dev_s *dev, xcpt_t handler, void *arg, int source); - void (*enableint)(struct stm32wl5_tim_dev_s *dev, int source); - void (*disableint)(struct stm32wl5_tim_dev_s *dev, int source); - void (*ackint)(struct stm32wl5_tim_dev_s *dev, int source); - int (*checkint)(struct stm32wl5_tim_dev_s *dev, int source); + void (*enableint)(struct stm32_tim_dev_s *dev, int source); + void (*disableint)(struct stm32_tim_dev_s *dev, int source); + void (*ackint)(struct stm32_tim_dev_s *dev, int source); + int (*checkint)(struct stm32_tim_dev_s *dev, int source); }; /**************************************************************************** @@ -177,14 +177,14 @@ struct stm32wl5_tim_ops_s /* Power-up timer and get its structure */ -struct stm32wl5_tim_dev_s *stm32wl5_tim_init(int timer); +struct stm32_tim_dev_s *stm32_tim_init(int timer); /* Power-down timer, mark it as unused */ -int stm32wl5_tim_deinit(struct stm32wl5_tim_dev_s *dev); +int stm32_tim_deinit(struct stm32_tim_dev_s *dev); /**************************************************************************** - * Name: stm32wl5_timer_initialize + * Name: stm32_timer_initialize * * Description: * Bind the configuration timer to a timer lower half instance and @@ -202,7 +202,7 @@ int stm32wl5_tim_deinit(struct stm32wl5_tim_dev_s *dev); ****************************************************************************/ #ifdef CONFIG_TIMER -int stm32wl5_timer_initialize(const char *devpath, int timer); +int stm32_timer_initialize(const char *devpath, int timer); #endif #undef EXTERN @@ -211,4 +211,4 @@ int stm32wl5_timer_initialize(const char *devpath, int timer); #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32WL5_STM32WL5_TIM_H */ +#endif /* __ARCH_ARM_SRC_STM32WL5_STM32_TIM_H */ diff --git a/arch/arm/src/stm32wl5/stm32wl5_tim_lowerhalf.c b/arch/arm/src/stm32wl5/stm32wl5_tim_lowerhalf.c index 572c4c95c218c..233008d82f047 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_tim_lowerhalf.c +++ b/arch/arm/src/stm32wl5/stm32wl5_tim_lowerhalf.c @@ -41,28 +41,28 @@ #include "stm32wl5_tim.h" #if defined(CONFIG_TIMER) && \ - (defined(CONFIG_STM32WL5_TIM1) || defined(CONFIG_STM32WL5_TIM2) || \ - defined(CONFIG_STM32WL5_TIM3) || defined(CONFIG_STM32WL5_TIM4) || \ - defined(CONFIG_STM32WL5_TIM5) || defined(CONFIG_STM32WL5_TIM6) || \ - defined(CONFIG_STM32WL5_TIM7) || defined(CONFIG_STM32WL5_TIM8) || \ - defined(CONFIG_STM32WL5_TIM15) || defined(CONFIG_STM32WL5_TIM16) || \ - defined(CONFIG_STM32WL5_TIM17)) + (defined(CONFIG_STM32_TIM1) || defined(CONFIG_STM32_TIM2) || \ + defined(CONFIG_STM32_TIM3) || defined(CONFIG_STM32_TIM4) || \ + defined(CONFIG_STM32_TIM5) || defined(CONFIG_STM32_TIM6) || \ + defined(CONFIG_STM32_TIM7) || defined(CONFIG_STM32_TIM8) || \ + defined(CONFIG_STM32_TIM15) || defined(CONFIG_STM32_TIM16) || \ + defined(CONFIG_STM32_TIM17)) /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ -#define STM32WL5_TIM1_RES 16 -#define STM32WL5_TIM2_RES 32 -#define STM32WL5_TIM3_RES 16 -#define STM32WL5_TIM4_RES 16 -#define STM32WL5_TIM5_RES 32 -#define STM32WL5_TIM6_RES 16 -#define STM32WL5_TIM7_RES 16 -#define STM32WL5_TIM8_RES 16 -#define STM32WL5_TIM15_RES 16 -#define STM32WL5_TIM16_RES 16 -#define STM32WL5_TIM17_RES 16 +#define STM32_TIM1_RES 16 +#define STM32_TIM2_RES 32 +#define STM32_TIM3_RES 16 +#define STM32_TIM4_RES 16 +#define STM32_TIM5_RES 32 +#define STM32_TIM6_RES 16 +#define STM32_TIM7_RES 16 +#define STM32_TIM8_RES 16 +#define STM32_TIM15_RES 16 +#define STM32_TIM16_RES 16 +#define STM32_TIM17_RES 16 /**************************************************************************** * Private Types @@ -73,10 +73,10 @@ * timer_lowerhalf_s structure. */ -struct stm32wl5_lowerhalf_s +struct stm32_lowerhalf_s { const struct timer_ops_s *ops; /* Lower half operations */ - struct stm32wl5_tim_dev_s *tim; /* stm32 timer driver */ + struct stm32_tim_dev_s *tim; /* stm32 timer driver */ tccb_t callback; /* Current upper half interrupt callback */ void *arg; /* Argument passed to upper half callback */ bool started; /* True: Timer has been started */ @@ -89,17 +89,17 @@ struct stm32wl5_lowerhalf_s /* Interrupt handling *******************************************************/ -static int stm32wl5_timer_handler(int irq, void *context, void *arg); +static int stm32_timer_handler(int irq, void *context, void *arg); /* "Lower half" driver methods **********************************************/ -static int stm32wl5_start(struct timer_lowerhalf_s *lower); -static int stm32wl5_stop(struct timer_lowerhalf_s *lower); -static int stm32wl5_getstatus(struct timer_lowerhalf_s *lower, +static int stm32_start(struct timer_lowerhalf_s *lower); +static int stm32_stop(struct timer_lowerhalf_s *lower); +static int stm32_getstatus(struct timer_lowerhalf_s *lower, struct timer_status_s *status); -static int stm32wl5_settimeout(struct timer_lowerhalf_s *lower, +static int stm32_settimeout(struct timer_lowerhalf_s *lower, uint32_t timeout); -static void stm32wl5_setcallback(struct timer_lowerhalf_s *lower, +static void stm32_setcallback(struct timer_lowerhalf_s *lower, tccb_t callback, void *arg); /**************************************************************************** @@ -110,99 +110,99 @@ static void stm32wl5_setcallback(struct timer_lowerhalf_s *lower, static const struct timer_ops_s g_timer_ops = { - .start = stm32wl5_start, - .stop = stm32wl5_stop, - .getstatus = stm32wl5_getstatus, - .settimeout = stm32wl5_settimeout, - .setcallback = stm32wl5_setcallback, + .start = stm32_start, + .stop = stm32_stop, + .getstatus = stm32_getstatus, + .settimeout = stm32_settimeout, + .setcallback = stm32_setcallback, .ioctl = NULL, }; -#ifdef CONFIG_STM32WL5_TIM1 -static struct stm32wl5_lowerhalf_s g_tim1_lowerhalf = +#ifdef CONFIG_STM32_TIM1 +static struct stm32_lowerhalf_s g_tim1_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32WL5_TIM1_RES, + .resolution = STM32_TIM1_RES, }; #endif -#ifdef CONFIG_STM32WL5_TIM2 -static struct stm32wl5_lowerhalf_s g_tim2_lowerhalf = +#ifdef CONFIG_STM32_TIM2 +static struct stm32_lowerhalf_s g_tim2_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32WL5_TIM2_RES, + .resolution = STM32_TIM2_RES, }; #endif -#ifdef CONFIG_STM32WL5_TIM3 -static struct stm32wl5_lowerhalf_s g_tim3_lowerhalf = +#ifdef CONFIG_STM32_TIM3 +static struct stm32_lowerhalf_s g_tim3_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32WL5_TIM3_RES, + .resolution = STM32_TIM3_RES, }; #endif -#ifdef CONFIG_STM32WL5_TIM4 -static struct stm32wl5_lowerhalf_s g_tim4_lowerhalf = +#ifdef CONFIG_STM32_TIM4 +static struct stm32_lowerhalf_s g_tim4_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32WL5_TIM4_RES, + .resolution = STM32_TIM4_RES, }; #endif -#ifdef CONFIG_STM32WL5_TIM5 -static struct stm32wl5_lowerhalf_s g_tim5_lowerhalf = +#ifdef CONFIG_STM32_TIM5 +static struct stm32_lowerhalf_s g_tim5_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32WL5_TIM5_RES, + .resolution = STM32_TIM5_RES, }; #endif -#ifdef CONFIG_STM32WL5_TIM6 -static struct stm32wl5_lowerhalf_s g_tim6_lowerhalf = +#ifdef CONFIG_STM32_TIM6 +static struct stm32_lowerhalf_s g_tim6_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32WL5_TIM6_RES, + .resolution = STM32_TIM6_RES, }; #endif -#ifdef CONFIG_STM32WL5_TIM7 -static struct stm32wl5_lowerhalf_s g_tim7_lowerhalf = +#ifdef CONFIG_STM32_TIM7 +static struct stm32_lowerhalf_s g_tim7_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32WL5_TIM7_RES, + .resolution = STM32_TIM7_RES, }; #endif -#ifdef CONFIG_STM32WL5_TIM8 -static struct stm32wl5_lowerhalf_s g_tim8_lowerhalf = +#ifdef CONFIG_STM32_TIM8 +static struct stm32_lowerhalf_s g_tim8_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32WL5_TIM8_RES, + .resolution = STM32_TIM8_RES, }; #endif -#ifdef CONFIG_STM32WL5_TIM15 -static struct stm32wl5_lowerhalf_s g_tim15_lowerhalf = +#ifdef CONFIG_STM32_TIM15 +static struct stm32_lowerhalf_s g_tim15_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32WL5_TIM15_RES, + .resolution = STM32_TIM15_RES, }; #endif -#ifdef CONFIG_STM32WL5_TIM16 -static struct stm32wl5_lowerhalf_s g_tim16_lowerhalf = +#ifdef CONFIG_STM32_TIM16 +static struct stm32_lowerhalf_s g_tim16_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32WL5_TIM16_RES, + .resolution = STM32_TIM16_RES, }; #endif -#ifdef CONFIG_STM32WL5_TIM17 -static struct stm32wl5_lowerhalf_s g_tim17_lowerhalf = +#ifdef CONFIG_STM32_TIM17 +static struct stm32_lowerhalf_s g_tim17_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32WL5_TIM17_RES, + .resolution = STM32_TIM17_RES, }; #endif @@ -211,7 +211,7 @@ static struct stm32wl5_lowerhalf_s g_tim17_lowerhalf = ****************************************************************************/ /**************************************************************************** - * Name: stm32wl5_timer_handler + * Name: stm32_timer_handler * * Description: * timer interrupt handler @@ -222,31 +222,31 @@ static struct stm32wl5_lowerhalf_s g_tim17_lowerhalf = * ****************************************************************************/ -static int stm32wl5_timer_handler(int irq, void *context, void *arg) +static int stm32_timer_handler(int irq, void *context, void *arg) { - struct stm32wl5_lowerhalf_s *lower = - (struct stm32wl5_lowerhalf_s *)arg; + struct stm32_lowerhalf_s *lower = + (struct stm32_lowerhalf_s *)arg; uint32_t next_interval_us = 0; - STM32WL5_TIM_ACKINT(lower->tim, 0); + STM32_TIM_ACKINT(lower->tim, 0); if (lower->callback(&next_interval_us, lower->arg)) { if (next_interval_us > 0) { - STM32WL5_TIM_SETPERIOD(lower->tim, next_interval_us); + STM32_TIM_SETPERIOD(lower->tim, next_interval_us); } } else { - stm32wl5_stop((struct timer_lowerhalf_s *)lower); + stm32_stop((struct timer_lowerhalf_s *)lower); } return OK; } /**************************************************************************** - * Name: stm32wl5_start + * Name: stm32_start * * Description: * Start the timer, resetting the time to the current timeout, @@ -260,19 +260,19 @@ static int stm32wl5_timer_handler(int irq, void *context, void *arg) * ****************************************************************************/ -static int stm32wl5_start(struct timer_lowerhalf_s *lower) +static int stm32_start(struct timer_lowerhalf_s *lower) { - struct stm32wl5_lowerhalf_s *priv = - (struct stm32wl5_lowerhalf_s *)lower; + struct stm32_lowerhalf_s *priv = + (struct stm32_lowerhalf_s *)lower; if (!priv->started) { - STM32WL5_TIM_SETMODE(priv->tim, STM32WL5_TIM_MODE_UP); + STM32_TIM_SETMODE(priv->tim, STM32_TIM_MODE_UP); if (priv->callback != NULL) { - STM32WL5_TIM_SETISR(priv->tim, stm32wl5_timer_handler, priv, 0); - STM32WL5_TIM_ENABLEINT(priv->tim, 0); + STM32_TIM_SETISR(priv->tim, stm32_timer_handler, priv, 0); + STM32_TIM_ENABLEINT(priv->tim, 0); } priv->started = true; @@ -285,7 +285,7 @@ static int stm32wl5_start(struct timer_lowerhalf_s *lower) } /**************************************************************************** - * Name: stm32wl5_stop + * Name: stm32_stop * * Description: * Stop the timer @@ -299,16 +299,16 @@ static int stm32wl5_start(struct timer_lowerhalf_s *lower) * ****************************************************************************/ -static int stm32wl5_stop(struct timer_lowerhalf_s *lower) +static int stm32_stop(struct timer_lowerhalf_s *lower) { - struct stm32wl5_lowerhalf_s *priv = - (struct stm32wl5_lowerhalf_s *)lower; + struct stm32_lowerhalf_s *priv = + (struct stm32_lowerhalf_s *)lower; if (priv->started) { - STM32WL5_TIM_SETMODE(priv->tim, STM32WL5_TIM_MODE_DISABLED); - STM32WL5_TIM_DISABLEINT(priv->tim, 0); - STM32WL5_TIM_SETISR(priv->tim, NULL, NULL, 0); + STM32_TIM_SETMODE(priv->tim, STM32_TIM_MODE_DISABLED); + STM32_TIM_DISABLEINT(priv->tim, 0); + STM32_TIM_SETISR(priv->tim, NULL, NULL, 0); priv->started = false; return OK; } @@ -319,7 +319,7 @@ static int stm32wl5_stop(struct timer_lowerhalf_s *lower) } /**************************************************************************** - * Name: stm32wl5_getstatus + * Name: stm32_getstatus * * Description: * get timer status @@ -334,11 +334,11 @@ static int stm32wl5_stop(struct timer_lowerhalf_s *lower) * ****************************************************************************/ -static int stm32wl5_getstatus(struct timer_lowerhalf_s *lower, +static int stm32_getstatus(struct timer_lowerhalf_s *lower, struct timer_status_s *status) { - struct stm32wl5_lowerhalf_s *priv = - (struct stm32wl5_lowerhalf_s *)lower; + struct stm32_lowerhalf_s *priv = + (struct stm32_lowerhalf_s *)lower; uint64_t maxtimeout; uint32_t timeout; uint32_t clock; @@ -363,8 +363,8 @@ static int stm32wl5_getstatus(struct timer_lowerhalf_s *lower, /* Get timeout */ maxtimeout = (1 << priv->resolution) - 1; - clock = STM32WL5_TIM_GETCLOCK(priv->tim); - period = STM32WL5_TIM_GETPERIOD(priv->tim); + clock = STM32_TIM_GETCLOCK(priv->tim); + period = STM32_TIM_GETPERIOD(priv->tim); if (clock == 1000000) { @@ -380,13 +380,13 @@ static int stm32wl5_getstatus(struct timer_lowerhalf_s *lower, /* Get the time remaining until the timer expires (in microseconds) */ clock_factor = (clock == 1000000)? 1: (clock / 1000000); - status->timeleft = (timeout - STM32WL5_TIM_GETCOUNTER(priv->tim)) * + status->timeleft = (timeout - STM32_TIM_GETCOUNTER(priv->tim)) * clock_factor; return OK; } /**************************************************************************** - * Name: stm32wl5_settimeout + * Name: stm32_settimeout * * Description: * Set a new timeout value (and reset the timer) @@ -401,11 +401,11 @@ static int stm32wl5_getstatus(struct timer_lowerhalf_s *lower, * ****************************************************************************/ -static int stm32wl5_settimeout(struct timer_lowerhalf_s *lower, +static int stm32_settimeout(struct timer_lowerhalf_s *lower, uint32_t timeout) { - struct stm32wl5_lowerhalf_s *priv = - (struct stm32wl5_lowerhalf_s *)lower; + struct stm32_lowerhalf_s *priv = + (struct stm32_lowerhalf_s *)lower; uint64_t maxtimeout; if (priv->started) @@ -417,20 +417,20 @@ static int stm32wl5_settimeout(struct timer_lowerhalf_s *lower, if (timeout > maxtimeout) { uint64_t freq = (maxtimeout * 1000000) / timeout; - STM32WL5_TIM_SETCLOCK(priv->tim, freq); - STM32WL5_TIM_SETPERIOD(priv->tim, maxtimeout); + STM32_TIM_SETCLOCK(priv->tim, freq); + STM32_TIM_SETPERIOD(priv->tim, maxtimeout); } else { - STM32WL5_TIM_SETCLOCK(priv->tim, 1000000); - STM32WL5_TIM_SETPERIOD(priv->tim, timeout); + STM32_TIM_SETCLOCK(priv->tim, 1000000); + STM32_TIM_SETPERIOD(priv->tim, timeout); } return OK; } /**************************************************************************** - * Name: stm32wl5_sethandler + * Name: stm32_sethandler * * Description: * Call this user provided timeout handler. @@ -449,11 +449,11 @@ static int stm32wl5_settimeout(struct timer_lowerhalf_s *lower, * ****************************************************************************/ -static void stm32wl5_setcallback(struct timer_lowerhalf_s *lower, +static void stm32_setcallback(struct timer_lowerhalf_s *lower, tccb_t callback, void *arg) { - struct stm32wl5_lowerhalf_s *priv = - (struct stm32wl5_lowerhalf_s *)lower; + struct stm32_lowerhalf_s *priv = + (struct stm32_lowerhalf_s *)lower; irqstate_t flags = enter_critical_section(); /* Save the new callback */ @@ -463,13 +463,13 @@ static void stm32wl5_setcallback(struct timer_lowerhalf_s *lower, if (callback != NULL && priv->started) { - STM32WL5_TIM_SETISR(priv->tim, stm32wl5_timer_handler, priv, 0); - STM32WL5_TIM_ENABLEINT(priv->tim, 0); + STM32_TIM_SETISR(priv->tim, stm32_timer_handler, priv, 0); + STM32_TIM_ENABLEINT(priv->tim, 0); } else { - STM32WL5_TIM_DISABLEINT(priv->tim, 0); - STM32WL5_TIM_SETISR(priv->tim, NULL, NULL, 0); + STM32_TIM_DISABLEINT(priv->tim, 0); + STM32_TIM_SETISR(priv->tim, NULL, NULL, 0); } leave_critical_section(flags); @@ -480,7 +480,7 @@ static void stm32wl5_setcallback(struct timer_lowerhalf_s *lower, ****************************************************************************/ /**************************************************************************** - * Name: stm32wl5_timer_initialize + * Name: stm32_timer_initialize * * Description: * Bind the configuration timer to a timer lower half instance and @@ -497,72 +497,72 @@ static void stm32wl5_setcallback(struct timer_lowerhalf_s *lower, * ****************************************************************************/ -int stm32wl5_timer_initialize(const char *devpath, int timer) +int stm32_timer_initialize(const char *devpath, int timer) { - struct stm32wl5_lowerhalf_s *lower; + struct stm32_lowerhalf_s *lower; switch (timer) { -#ifdef CONFIG_STM32WL5_TIM1 +#ifdef CONFIG_STM32_TIM1 case 1: lower = &g_tim1_lowerhalf; break; #endif -#ifdef CONFIG_STM32WL5_TIM2 +#ifdef CONFIG_STM32_TIM2 case 2: lower = &g_tim2_lowerhalf; break; #endif -#ifdef CONFIG_STM32WL5_TIM3 +#ifdef CONFIG_STM32_TIM3 case 3: lower = &g_tim3_lowerhalf; break; #endif -#ifdef CONFIG_STM32WL5_TIM4 +#ifdef CONFIG_STM32_TIM4 case 4: lower = &g_tim4_lowerhalf; break; #endif -#ifdef CONFIG_STM32WL5_TIM5 +#ifdef CONFIG_STM32_TIM5 case 5: lower = &g_tim5_lowerhalf; break; #endif -#ifdef CONFIG_STM32WL5_TIM6 +#ifdef CONFIG_STM32_TIM6 case 6: lower = &g_tim6_lowerhalf; break; #endif -#ifdef CONFIG_STM32WL5_TIM7 +#ifdef CONFIG_STM32_TIM7 case 7: lower = &g_tim7_lowerhalf; break; #endif -#ifdef CONFIG_STM32WL5_TIM8 +#ifdef CONFIG_STM32_TIM8 case 8: lower = &g_tim8_lowerhalf; break; #endif -#ifdef CONFIG_STM32WL5_TIM15 +#ifdef CONFIG_STM32_TIM15 case 15: lower = &g_tim15_lowerhalf; break; #endif -#ifdef CONFIG_STM32WL5_TIM16 +#ifdef CONFIG_STM32_TIM16 case 16: lower = &g_tim16_lowerhalf; break; #endif -#ifdef CONFIG_STM32WL5_TIM17 +#ifdef CONFIG_STM32_TIM17 case 17: lower = &g_tim17_lowerhalf; break; @@ -576,7 +576,7 @@ int stm32wl5_timer_initialize(const char *devpath, int timer) lower->started = false; lower->callback = NULL; - lower->tim = stm32wl5_tim_init(timer); + lower->tim = stm32_tim_init(timer); if (lower->tim == NULL) { diff --git a/arch/arm/src/stm32wl5/stm32wl5_timerisr.c b/arch/arm/src/stm32wl5/stm32wl5_timerisr.c index c4238fbf26827..4de3d6b393692 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_timerisr.c +++ b/arch/arm/src/stm32wl5/stm32wl5_timerisr.c @@ -38,7 +38,7 @@ #include "arm_internal.h" #include "chip.h" -#include "stm32wl5.h" +#include "stm32.h" /**************************************************************************** * Pre-processor Definitions @@ -59,12 +59,12 @@ * And I don't know now to re-configure it yet */ -#undef CONFIG_STM32WL5_SYSTICK_HCLKd8 +#undef CONFIG_STM32_SYSTICK_HCLKd8 -#ifdef CONFIG_STM32WL5_SYSTICK_HCLKd8 -# define SYSTICK_RELOAD ((STM32WL5_HCLK_FREQUENCY / 8 / CLK_TCK) - 1) +#ifdef CONFIG_STM32_SYSTICK_HCLKd8 +# define SYSTICK_RELOAD ((STM32_HCLK_FREQUENCY / 8 / CLK_TCK) - 1) #else -# define SYSTICK_RELOAD ((STM32WL5_HCLK_FREQUENCY / CLK_TCK) - 1) +# define SYSTICK_RELOAD ((STM32_HCLK_FREQUENCY / CLK_TCK) - 1) #endif /* The size of the reload field is 24 bits. Verify that the reload value @@ -80,7 +80,7 @@ ****************************************************************************/ /**************************************************************************** - * Function: stm32wl5_timerisr + * Function: stm32_timerisr * * Description: * The timer ISR will perform a variety of services for various portions @@ -88,7 +88,7 @@ * ****************************************************************************/ -static int stm32wl5_timerisr(int irq, uint32_t *regs, void *arg) +static int stm32_timerisr(int irq, uint32_t *regs, void *arg) { /* Process timer interrupt */ @@ -124,7 +124,7 @@ void up_timer_initialize(void) #if 0 /* Does not work. Comes up with HCLK source and I can't change it */ regval = getreg32(NVIC_SYSTICK_CTRL); -#ifdef CONFIG_STM32WL5_SYSTICK_HCLKd8 +#ifdef CONFIG_STM32_SYSTICK_HCLKd8 regval &= ~NVIC_SYSTICK_CTRL_CLKSOURCE; #else regval |= NVIC_SYSTICK_CTRL_CLKSOURCE; @@ -138,7 +138,7 @@ void up_timer_initialize(void) /* Attach the timer interrupt vector */ - (void)irq_attach(STM32WL5_IRQ_SYSTICK, (xcpt_t)stm32wl5_timerisr, NULL); + (void)irq_attach(STM32_IRQ_SYSTICK, (xcpt_t)stm32_timerisr, NULL); /* Enable SysTick interrupts */ @@ -147,5 +147,5 @@ void up_timer_initialize(void) /* And enable the timer interrupt */ - up_enable_irq(STM32WL5_IRQ_SYSTICK); + up_enable_irq(STM32_IRQ_SYSTICK); } diff --git a/arch/arm/src/stm32wl5/stm32wl5_uart.h b/arch/arm/src/stm32wl5/stm32wl5_uart.h index 8abf47c83c574..06c8ed8c86fac 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_uart.h +++ b/arch/arm/src/stm32wl5/stm32wl5_uart.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_STC_STM32WL5_STM32WL5_UART_H -#define __ARCH_ARM_STC_STM32WL5_STM32WL5_UART_H +#ifndef __ARCH_ARM_SRC_STM32WL5_STM32_UART_H +#define __ARCH_ARM_SRC_STM32WL5_STM32_UART_H /**************************************************************************** * Included Files @@ -42,42 +42,42 @@ * device. */ -#if !defined(CONFIG_STM32WL5_HAVE_USART2) -# undef CONFIG_STM32WL5_USART2 +#if !defined(CONFIG_STM32_HAVE_USART2) +# undef CONFIG_STM32_USART2 #endif -#if !defined(CONFIG_STM32WL5_HAVE_USART1) -# undef CONFIG_STM32WL5_USART1 +#if !defined(CONFIG_STM32_HAVE_USART1) +# undef CONFIG_STM32_USART1 #endif -#if !defined(CONFIG_STM32WL5_HAVE_LPUART1) -# undef CONFIG_STM32WL5_LPUART1 +#if !defined(CONFIG_STM32_HAVE_LPUART1) +# undef CONFIG_STM32_LPUART1 #endif /* Sanity checks */ -#if !defined(CONFIG_STM32WL5_LPUART1) -# undef CONFIG_STM32WL5_LPUART1_SERIALDRIVER -# undef CONFIG_STM32WL5_LPUART1_1WIREDRIVER +#if !defined(CONFIG_STM32_LPUART1) +# undef CONFIG_STM32_LPUART1_SERIALDRIVER +# undef CONFIG_STM32_LPUART1_1WIREDRIVER #endif -#if !defined(CONFIG_STM32WL5_USART1) -# undef CONFIG_STM32WL5_USART1_SERIALDRIVER -# undef CONFIG_STM32WL5_USART1_1WIREDRIVER +#if !defined(CONFIG_STM32_USART1) +# undef CONFIG_STM32_USART1_SERIALDRIVER +# undef CONFIG_STM32_USART1_1WIREDRIVER #endif -#if !defined(CONFIG_STM32WL5_USART2) -# undef CONFIG_STM32WL5_USART2_SERIALDRIVER -# undef CONFIG_STM32WL5_USART2_1WIREDRIVER +#if !defined(CONFIG_STM32_USART2) +# undef CONFIG_STM32_USART2_SERIALDRIVER +# undef CONFIG_STM32_USART2_1WIREDRIVER #endif /* Is there a USART enabled? */ -#if defined(CONFIG_STM32WL5_LPUART1) || \ - defined(CONFIG_STM32WL5_USART1) || \ - defined(CONFIG_STM32WL5_USART2) +#if defined(CONFIG_STM32_LPUART1) || \ + defined(CONFIG_STM32_USART1) || \ + defined(CONFIG_STM32_USART2) # define HAVE_UART 1 #endif /* Is there a serial console? */ -#if defined(CONFIG_LPUART1_SERIAL_CONSOLE) && defined(CONFIG_STM32WL5_LPUART1_SERIALDRIVER) +#if defined(CONFIG_LPUART1_SERIAL_CONSOLE) && defined(CONFIG_STM32_LPUART1_SERIALDRIVER) # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE @@ -85,7 +85,7 @@ # undef CONFIG_UART5_SERIAL_CONSOLE # define CONSOLE_UART 1 # define HAVE_CONSOLE 1 -#elif defined(CONFIG_USART1_SERIAL_CONSOLE) && defined(CONFIG_STM32WL5_USART1_SERIALDRIVER) +#elif defined(CONFIG_USART1_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART1_SERIALDRIVER) # undef CONFIG_LPUART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE @@ -93,7 +93,7 @@ # undef CONFIG_UART5_SERIAL_CONSOLE # define CONSOLE_UART 2 # define HAVE_CONSOLE 1 -#elif defined(CONFIG_USART2_SERIAL_CONSOLE) && defined(CONFIG_STM32WL5_USART2_SERIALDRIVER) +#elif defined(CONFIG_USART2_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART2_SERIALDRIVER) # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE # undef CONFIG_UART4_SERIAL_CONSOLE @@ -121,15 +121,15 @@ /* Disable the DMA configuration on all unused USARTs */ -#ifndef CONFIG_STM32WL5_LPUART1_SERIALDRIVER +#ifndef CONFIG_STM32_LPUART1_SERIALDRIVER # undef CONFIG_LPUART1_RXDMA #endif -#ifndef CONFIG_STM32WL5_USART1_SERIALDRIVER +#ifndef CONFIG_STM32_USART1_SERIALDRIVER # undef CONFIG_USART1_RXDMA #endif -#ifndef CONFIG_STM32WL5_USART2_SERIALDRIVER +#ifndef CONFIG_STM32_USART2_SERIALDRIVER # undef CONFIG_USART2_RXDMA #endif @@ -156,11 +156,11 @@ /* Is DMA used on all (enabled) USARTs */ #define SERIAL_HAVE_ONLY_DMA 1 -#if defined(CONFIG_STM32WL5_LPUART1_SERIALDRIVER) && !defined(CONFIG_LPUART1_RXDMA) +#if defined(CONFIG_STM32_LPUART1_SERIALDRIVER) && !defined(CONFIG_LPUART1_RXDMA) # undef SERIAL_HAVE_ONLY_DMA -#elif defined(CONFIG_STM32WL5_USART1_SERIALDRIVER) && !defined(CONFIG_USART1_RXDMA) +#elif defined(CONFIG_STM32_USART1_SERIALDRIVER) && !defined(CONFIG_USART1_RXDMA) # undef SERIAL_HAVE_ONLY_DMA -#elif defined(CONFIG_STM32WL5_USART2_SERIALDRIVER) && !defined(CONFIG_USART2_RXDMA) +#elif defined(CONFIG_STM32_USART2_SERIALDRIVER) && !defined(CONFIG_USART2_RXDMA) # undef SERIAL_HAVE_ONLY_DMA #endif @@ -202,7 +202,7 @@ extern "C" ****************************************************************************/ /**************************************************************************** - * Name: stm32wl5_serial_dma_poll + * Name: stm32_serial_dma_poll * * Description: * Must be called periodically if any STM32 UART is configured for DMA. @@ -215,7 +215,7 @@ extern "C" ****************************************************************************/ #ifdef SERIAL_HAVE_DMA -void stm32wl5_serial_dma_poll(void); +void stm32_serial_dma_poll(void); #endif #undef EXTERN @@ -224,4 +224,4 @@ void stm32wl5_serial_dma_poll(void); #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_STC_STM32WL5_STM32WL5_UART_H */ +#endif /* __ARCH_ARM_SRC_STM32WL5_STM32_UART_H */ diff --git a/arch/arm/src/stm32wl5/stm32wl5_uid.c b/arch/arm/src/stm32wl5/stm32wl5_uid.c deleted file mode 100644 index b8fa93730bf10..0000000000000 --- a/arch/arm/src/stm32wl5/stm32wl5_uid.c +++ /dev/null @@ -1,63 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32wl5/stm32wl5_uid.c - * - * SPDX-License-Identifier: BSD-3-Clause - * SPDX-FileCopyrightText: 2015 Marawan Ragab. All rights reserved. - * SPDX-FileContributor: Marawan Ragab - * SPDX-FileContributor: dev@ziggurat9.com - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "hardware/stm32wl5_memorymap.h" -#include "stm32wl5_uid.h" - -#ifdef STM32WL5_SYSMEM_UID - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -void stm32wl5_get_uniqueid(uint8_t uniqueid[12]) -{ - int i; - - for (i = 0; i < 12; i++) - { - uniqueid[i] = *((uint8_t *)(STM32WL5_SYSMEM_UID)+i); - } -} - -#endif /* STM32WL5_SYSMEM_UID */ diff --git a/arch/arm/src/stm32wl5/stm32wl5_uid.h b/arch/arm/src/stm32wl5/stm32wl5_uid.h deleted file mode 100644 index 6992f84b9c3ee..0000000000000 --- a/arch/arm/src/stm32wl5/stm32wl5_uid.h +++ /dev/null @@ -1,53 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32wl5/stm32wl5_uid.h - * - * SPDX-License-Identifier: BSD-3-Clause - * SPDX-FileCopyrightText: 2015 Marawan Ragab. All rights reserved. - * SPDX-FileContributor: Marawan Ragab - * SPDX-FileContributor: dev@ziggurat9.com - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32WL5_STM32WL5_UID_H -#define __ARCH_ARM_SRC_STM32WL5_STM32WL5_UID_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -void stm32wl5_get_uniqueid(uint8_t uniqueid[12]); - -#endif /* __ARCH_ARM_SRC_STM32WL5_STM32WL5_UID_H */ diff --git a/arch/arm/src/stm32wl5/stm32wl5_userspace.c b/arch/arm/src/stm32wl5/stm32wl5_userspace.c index 345a6f0f45772..23a8bfe9bba65 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_userspace.c +++ b/arch/arm/src/stm32wl5/stm32wl5_userspace.c @@ -41,7 +41,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32wl5_userspace + * Name: stm32_userspace * * Description: * For the case of the separate user-/kernel-space build, perform whatever @@ -51,7 +51,7 @@ * ****************************************************************************/ -void stm32wl5_userspace(void) +void stm32_userspace(void) { uint8_t *src; uint8_t *dest; @@ -87,7 +87,7 @@ void stm32wl5_userspace(void) /* Configure the MPU to permit user-space access to its FLASH and RAM */ - stm32wl5_mpuinitialize(); + stm32_mpuinitialize(); } #endif /* CONFIG_BUILD_PROTECTED */ diff --git a/arch/arm/src/stm32wl5/stm32wl5_userspace.h b/arch/arm/src/stm32wl5/stm32wl5_userspace.h index 3ca2fdf521c6e..900a75750a1bd 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_userspace.h +++ b/arch/arm/src/stm32wl5/stm32wl5_userspace.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32WL5_STM32WL5_USERSPACE_H -#define __ARCH_ARM_SRC_STM32WL5_STM32WL5_USERSPACE_H +#ifndef __ARCH_ARM_SRC_STM32WL5_STM32_USERSPACE_H +#define __ARCH_ARM_SRC_STM32WL5_STM32_USERSPACE_H /**************************************************************************** * Included Files @@ -34,7 +34,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32wl5_userspace + * Name: stm32_userspace * * Description: * For the case of the separate user-/kernel-space build, perform whatever @@ -45,7 +45,7 @@ ****************************************************************************/ #ifdef CONFIG_BUILD_PROTECTED -void stm32wl5_userspace(void); +void stm32_userspace(void); #endif -#endif /* __ARCH_ARM_SRC_STM32WL5_STM32WL5_USERSPACE_H */ +#endif /* __ARCH_ARM_SRC_STM32WL5_STM32_USERSPACE_H */ diff --git a/arch/arm/src/stm32wl5/stm32wl5_waste.c b/arch/arm/src/stm32wl5/stm32wl5_waste.c deleted file mode 100644 index 96f0e621cf3b1..0000000000000 --- a/arch/arm/src/stm32wl5/stm32wl5_waste.c +++ /dev/null @@ -1,44 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32wl5/stm32wl5_waste.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include -#include "stm32wl5_waste.h" - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -uint32_t idle_wastecounter = 0; - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -void stm32wl5_waste(void) -{ - idle_wastecounter++; -} diff --git a/arch/arm/src/stm32wl5/stm32wl5_waste.h b/arch/arm/src/stm32wl5/stm32wl5_waste.h deleted file mode 100644 index 348469b498213..0000000000000 --- a/arch/arm/src/stm32wl5/stm32wl5_waste.h +++ /dev/null @@ -1,65 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32wl5/stm32wl5_waste.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32WL5_STM32WL5_WASTE_H -#define __ARCH_ARM_SRC_STM32WL5_STM32WL5_WASTE_H - -/* Waste CPU Time */ - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#ifndef __ASSEMBLY__ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/* Waste CPU Time - * - * stm32wl5_waste() is the logic that will be executed when portions of - * kernel or user-app is polling some register or similar, waiting for - * desired status. This time is wasted away. This function offers a measure - * of badly written piece of software or some undesired behavior. At - * the same time this function adds to some IDLE time which portion cannot - * be used for other purposes (yet). - */ - -void stm32wl5_waste(void); - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32WL5_STM32WL5_WASTE_H */ diff --git a/boards/Kconfig b/boards/Kconfig index 2a6a401dd15a0..9ebfc82638982 100644 --- a/boards/Kconfig +++ b/boards/Kconfig @@ -4486,52 +4486,52 @@ if ARCH_BOARD_PIC32CZCA70_CURIOSITY source "boards/arm/samv7/pic32czca70-curiosity/Kconfig" endif if ARCH_BOARD_B_G474E_DPOW1 -source "boards/arm/stm32/b-g474e-dpow1/Kconfig" +source "boards/arm/stm32g4/b-g474e-dpow1/Kconfig" endif if ARCH_BOARD_B_G431B_ESC1 -source "boards/arm/stm32/b-g431b-esc1/Kconfig" +source "boards/arm/stm32g4/b-g431b-esc1/Kconfig" endif if ARCH_BOARD_NUCLEO_G431KB -source "boards/arm/stm32/nucleo-g431kb/Kconfig" +source "boards/arm/stm32g4/nucleo-g431kb/Kconfig" endif if ARCH_BOARD_NUCLEO_G431RB -source "boards/arm/stm32/nucleo-g431rb/Kconfig" +source "boards/arm/stm32g4/nucleo-g431rb/Kconfig" endif if ARCH_BOARD_B_L072Z_LRWAN1 -source "boards/arm/stm32f0l0g0/b-l072z-lrwan1/Kconfig" +source "boards/arm/stm32l0/b-l072z-lrwan1/Kconfig" endif if ARCH_BOARD_NUCLEO_F072RB -source "boards/arm/stm32f0l0g0/nucleo-f072rb/Kconfig" +source "boards/arm/stm32f0/nucleo-f072rb/Kconfig" endif if ARCH_BOARD_NUCLEO_F091RC -source "boards/arm/stm32f0l0g0/nucleo-f091rc/Kconfig" +source "boards/arm/stm32f0/nucleo-f091rc/Kconfig" endif if ARCH_BOARD_NUCLEO_G070RB -source "boards/arm/stm32f0l0g0/nucleo-g070rb/Kconfig" +source "boards/arm/stm32g0/nucleo-g070rb/Kconfig" endif if ARCH_BOARD_NUCLEO_G071RB -source "boards/arm/stm32f0l0g0/nucleo-g071rb/Kconfig" +source "boards/arm/stm32g0/nucleo-g071rb/Kconfig" endif if ARCH_BOARD_NUCLEO_G0B1RE -source "boards/arm/stm32f0l0g0/nucleo-g0b1re/Kconfig" +source "boards/arm/stm32g0/nucleo-g0b1re/Kconfig" endif if ARCH_BOARD_NUCLEO_L073RZ -source "boards/arm/stm32f0l0g0/nucleo-l073rz/Kconfig" +source "boards/arm/stm32l0/nucleo-l073rz/Kconfig" endif if ARCH_BOARD_STM32F051_DISCOVERY -source "boards/arm/stm32f0l0g0/stm32f051-discovery/Kconfig" +source "boards/arm/stm32f0/stm32f051-discovery/Kconfig" endif if ARCH_BOARD_STM32L0538_DISCO -source "boards/arm/stm32f0l0g0/stm32l0538-disco/Kconfig" +source "boards/arm/stm32l0/stm32l0538-disco/Kconfig" endif if ARCH_BOARD_STM32F072_DISCOVERY -source "boards/arm/stm32f0l0g0/stm32f072-discovery/Kconfig" +source "boards/arm/stm32f0/stm32f072-discovery/Kconfig" endif if ARCH_BOARD_NUCLEO_C071RB -source "boards/arm/stm32f0l0g0/nucleo-c071rb/Kconfig" +source "boards/arm/stm32c0/nucleo-c071rb/Kconfig" endif if ARCH_BOARD_NUCLEO_C092RC -source "boards/arm/stm32f0l0g0/nucleo-c092rc/Kconfig" +source "boards/arm/stm32c0/nucleo-c092rc/Kconfig" endif if ARCH_BOARD_NUCLEO_F722ZE source "boards/arm/stm32f7/nucleo-f722ze/Kconfig" @@ -4651,151 +4651,151 @@ if ARCH_BOARD_NUCLEO_WB55RG source "boards/arm/stm32wb/nucleo-wb55rg/Kconfig" endif if ARCH_BOARD_AXOLOTI -source "boards/arm/stm32/axoloti/Kconfig" +source "boards/arm/stm32f4/axoloti/Kconfig" endif if ARCH_BOARD_CLICKER2_STM32 -source "boards/arm/stm32/clicker2-stm32/Kconfig" +source "boards/arm/stm32f4/clicker2-stm32/Kconfig" endif if ARCH_BOARD_CLOUDCTRL -source "boards/arm/stm32/cloudctrl/Kconfig" +source "boards/arm/stm32f1/cloudctrl/Kconfig" endif if ARCH_BOARD_EMW3162 -source "boards/arm/stm32/emw3162/Kconfig" +source "boards/arm/stm32f2/emw3162/Kconfig" endif if ARCH_BOARD_FIRE_STM32 -source "boards/arm/stm32/fire-stm32v2/Kconfig" +source "boards/arm/stm32f1/fire-stm32v2/Kconfig" endif if ARCH_BOARD_HYMINI_STM32V -source "boards/arm/stm32/hymini-stm32v/Kconfig" +source "boards/arm/stm32f1/hymini-stm32v/Kconfig" endif if ARCH_BOARD_MAPLE -source "boards/arm/stm32/maple/Kconfig" +source "boards/arm/stm32f1/maple/Kconfig" endif if ARCH_BOARD_ET_STM32_STAMP -source "boards/arm/stm32/et-stm32-stamp/Kconfig" +source "boards/arm/stm32f1/et-stm32-stamp/Kconfig" endif if ARCH_BOARD_MIKROE_STM32F4 -source "boards/arm/stm32/mikroe-stm32f4/Kconfig" +source "boards/arm/stm32f4/mikroe-stm32f4/Kconfig" endif if ARCH_BOARD_NUCLEO_F103RB -source "boards/arm/stm32/nucleo-f103rb/Kconfig" +source "boards/arm/stm32f1/nucleo-f103rb/Kconfig" endif if ARCH_BOARD_NUCLEO_F207ZG -source "boards/arm/stm32/nucleo-f207zg/Kconfig" +source "boards/arm/stm32f2/nucleo-f207zg/Kconfig" endif if ARCH_BOARD_NUCLEO_F302R8 -source "boards/arm/stm32/nucleo-f302r8/Kconfig" +source "boards/arm/stm32f3/nucleo-f302r8/Kconfig" endif if ARCH_BOARD_NUCLEO_F303RE -source "boards/arm/stm32/nucleo-f303re/Kconfig" +source "boards/arm/stm32f3/nucleo-f303re/Kconfig" endif if ARCH_BOARD_NUCLEO_F303ZE -source "boards/arm/stm32/nucleo-f303ze/Kconfig" +source "boards/arm/stm32f3/nucleo-f303ze/Kconfig" endif if ARCH_BOARD_NUCLEO_F334R8 -source "boards/arm/stm32/nucleo-f334r8/Kconfig" +source "boards/arm/stm32f3/nucleo-f334r8/Kconfig" endif if ARCH_BOARD_NUCLEO_F410RB -source "boards/arm/stm32/nucleo-f410rb/Kconfig" +source "boards/arm/stm32f4/nucleo-f410rb/Kconfig" endif if ARCH_BOARD_NUCLEO_F412ZG -source "boards/arm/stm32/nucleo-f412zg/Kconfig" +source "boards/arm/stm32f4/nucleo-f412zg/Kconfig" endif if ARCH_BOARD_NUCLEO_F446RE -source "boards/arm/stm32/nucleo-f446re/Kconfig" +source "boards/arm/stm32f4/nucleo-f446re/Kconfig" endif if ARCH_BOARD_NUCLEO_F401RE -source "boards/arm/stm32/nucleo-f401re/Kconfig" +source "boards/arm/stm32f4/nucleo-f401re/Kconfig" endif if ARCH_BOARD_NUCLEO_F411RE -source "boards/arm/stm32/nucleo-f411re/Kconfig" +source "boards/arm/stm32f4/nucleo-f411re/Kconfig" endif if ARCH_BOARD_STM32F401RC_RS485 -source "boards/arm/stm32/stm32f401rc-rs485/Kconfig" +source "boards/arm/stm32f4/stm32f401rc-rs485/Kconfig" endif if ARCH_BOARD_NUCLEO_F429ZI -source "boards/arm/stm32/nucleo-f429zi/Kconfig" +source "boards/arm/stm32f4/nucleo-f429zi/Kconfig" endif if ARCH_BOARD_NUCLEO_L152RE -source "boards/arm/stm32/nucleo-l152re/Kconfig" +source "boards/arm/stm32l1/nucleo-l152re/Kconfig" endif if ARCH_BOARD_ODRIVE36 -source "boards/arm/stm32/odrive36/Kconfig" +source "boards/arm/stm32f4/odrive36/Kconfig" endif if ARCH_BOARD_OLIMEX_STM32E407 -source "boards/arm/stm32/olimex-stm32-e407/Kconfig" +source "boards/arm/stm32f4/olimex-stm32-e407/Kconfig" endif if ARCH_BOARD_OLIMEX_STM32H405 -source "boards/arm/stm32/olimex-stm32-h405/Kconfig" +source "boards/arm/stm32f4/olimex-stm32-h405/Kconfig" endif if ARCH_BOARD_OLIMEX_STM32H407 -source "boards/arm/stm32/olimex-stm32-h407/Kconfig" +source "boards/arm/stm32f4/olimex-stm32-h407/Kconfig" endif if ARCH_BOARD_OLIMEX_STM32P107 -source "boards/arm/stm32/olimex-stm32-p107/Kconfig" +source "boards/arm/stm32f1/olimex-stm32-p107/Kconfig" endif if ARCH_BOARD_OLIMEX_STM32P207 -source "boards/arm/stm32/olimex-stm32-p207/Kconfig" +source "boards/arm/stm32f2/olimex-stm32-p207/Kconfig" endif if ARCH_BOARD_OLIMEX_STM32P407 -source "boards/arm/stm32/olimex-stm32-p407/Kconfig" +source "boards/arm/stm32f4/olimex-stm32-p407/Kconfig" endif if ARCH_BOARD_OLIMEXINO_STM32 -source "boards/arm/stm32/olimexino-stm32/Kconfig" +source "boards/arm/stm32f1/olimexino-stm32/Kconfig" endif if ARCH_BOARD_OMNIBUSF4 -source "boards/arm/stm32/omnibusf4/Kconfig" +source "boards/arm/stm32f4/omnibusf4/Kconfig" endif if ARCH_BOARD_PHOTON -source "boards/arm/stm32/photon/Kconfig" +source "boards/arm/stm32f2/photon/Kconfig" endif if ARCH_BOARD_SHENZHOU -source "boards/arm/stm32/shenzhou/Kconfig" +source "boards/arm/stm32f1/shenzhou/Kconfig" endif if ARCH_BOARD_STM3210E_EVAL -source "boards/arm/stm32/stm3210e-eval/Kconfig" +source "boards/arm/stm32f1/stm3210e-eval/Kconfig" endif if ARCH_BOARD_STM3220G_EVAL -source "boards/arm/stm32/stm3220g-eval/Kconfig" +source "boards/arm/stm32f2/stm3220g-eval/Kconfig" endif if ARCH_BOARD_STM3240G_EVAL -source "boards/arm/stm32/stm3240g-eval/Kconfig" +source "boards/arm/stm32f4/stm3240g-eval/Kconfig" endif if ARCH_BOARD_STM32_TINY -source "boards/arm/stm32/stm32_tiny/Kconfig" +source "boards/arm/stm32f1/stm32_tiny/Kconfig" endif if ARCH_BOARD_STM32_BUTTERFLY2 -source "boards/arm/stm32/stm32butterfly2/Kconfig" +source "boards/arm/stm32f1/stm32butterfly2/Kconfig" endif if ARCH_BOARD_STM32F103_MINIMUM -source "boards/arm/stm32/stm32f103-minimum/Kconfig" +source "boards/arm/stm32f1/stm32f103-minimum/Kconfig" endif if ARCH_BOARD_STM32F411_MINIMUM -source "boards/arm/stm32/stm32f411-minimum/Kconfig" +source "boards/arm/stm32f4/stm32f411-minimum/Kconfig" endif if ARCH_BOARD_STM32F334_DISCO -source "boards/arm/stm32/stm32f334-disco/Kconfig" +source "boards/arm/stm32f3/stm32f334-disco/Kconfig" endif if ARCH_BOARD_STM32F3_DISCOVERY -source "boards/arm/stm32/stm32f3discovery/Kconfig" +source "boards/arm/stm32f3/stm32f3discovery/Kconfig" endif if ARCH_BOARD_STM32F411E_DISCO -source "boards/arm/stm32/stm32f411e-disco/Kconfig" +source "boards/arm/stm32f4/stm32f411e-disco/Kconfig" endif if ARCH_BOARD_STM32F429I_DISCO -source "boards/arm/stm32/stm32f429i-disco/Kconfig" +source "boards/arm/stm32f4/stm32f429i-disco/Kconfig" endif if ARCH_BOARD_STM32F4_DISCOVERY -source "boards/arm/stm32/stm32f4discovery/Kconfig" +source "boards/arm/stm32f4/stm32f4discovery/Kconfig" endif if ARCH_BOARD_STM32L_DISCOVERY -source "boards/arm/stm32/stm32ldiscovery/Kconfig" +source "boards/arm/stm32l1/stm32ldiscovery/Kconfig" endif if ARCH_BOARD_STM32VL_DISCOVERY -source "boards/arm/stm32/stm32vldiscovery/Kconfig" +source "boards/arm/stm32f1/stm32vldiscovery/Kconfig" endif if ARCH_BOARD_VIEWTOOL_STM32F107 -source "boards/arm/stm32/viewtool-stm32f107/Kconfig" +source "boards/arm/stm32f1/viewtool-stm32f107/Kconfig" endif if ARCH_BOARD_OLIMEX_STRP711 source "boards/arm/str71x/olimex-strp711/Kconfig" @@ -5206,14 +5206,8 @@ endif if ARCH_CHIP_SAMV7 source "boards/arm/samv7/common/Kconfig" endif -if ARCH_CHIP_STM32 -source "boards/arm/stm32/common/Kconfig" -endif -if ARCH_CHIP_STM32F7 -source "boards/arm/stm32f7/common/Kconfig" -endif -if ARCH_CHIP_STM32F0L0G0 -source "boards/arm/stm32f0l0g0/common/Kconfig" +if ARCH_CHIP_STM32C0 || ARCH_CHIP_STM32F0 || ARCH_CHIP_STM32F1 || ARCH_CHIP_STM32F2 || ARCH_CHIP_STM32F3 || ARCH_CHIP_STM32F4 || ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32G0 || ARCH_CHIP_STM32G4 || ARCH_CHIP_STM32L0 || ARCH_CHIP_STM32L1 || ARCH_CHIP_STM32H5 || ARCH_CHIP_STM32H7 || ARCH_CHIP_STM32L5 || ARCH_CHIP_STM32U5 || ARCH_CHIP_STM32WB || ARCH_CHIP_STM32WL5 || ARCH_CHIP_STM32N6 +source "boards/arm/common/stm32/Kconfig" endif if ARCH_CHIP_RP2040 source "boards/arm/rp2040/common/Kconfig" diff --git a/boards/arm/common/stm32/CMakeLists.txt b/boards/arm/common/stm32/CMakeLists.txt new file mode 100644 index 0000000000000..1c54914f408d5 --- /dev/null +++ b/boards/arm/common/stm32/CMakeLists.txt @@ -0,0 +1,24 @@ +# ############################################################################## +# boards/arm/common/stm32/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) +target_include_directories(board PRIVATE include) diff --git a/boards/arm/common/stm32/Kconfig b/boards/arm/common/stm32/Kconfig new file mode 100644 index 0000000000000..1c025f51839dc --- /dev/null +++ b/boards/arm/common/stm32/Kconfig @@ -0,0 +1,247 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# + +if STM32_FOC + +menuconfig BOARD_STM32_IHM07M1 + bool "X-NUCLEO-IHM07M1 board support" + default n + ---help--- + Board based on the L6230 DMOS driver. + +if BOARD_STM32_IHM07M1 + +config BOARD_STM32_IHM07M1_VBUS + bool "X-NUCLEO-IHM07M1 board VBUS sense" + default n + +config BOARD_STM32_IHM07M1_POT + bool "X-NUCLEO-IHM07M1 board POT support" + default n + +endif # BOARD_STM32_IHM07M1 + +menuconfig BOARD_STM32_IHM08M1 + bool "X-NUCLEO-IHM08M1 board support" + default n + select STM32_FOC_HAS_PWM_COMPLEMENTARY + ---help--- + Board based on the discrete L6398 gate drivers and STL220N6F7 POWER MOSFETs. + +if BOARD_STM32_IHM08M1 + +config BOARD_STM32_IHM08M1_VBUS + bool "X-NUCLEO-IHM08M1 board VBUS sense" + default n + +config BOARD_STM32_IHM08M1_POT + bool "X-NUCLEO-IHM08M1 board POT support" + default n + +endif # BOARD_STM32_IHM08M1 + +menuconfig BOARD_STM32_IHM16M1 + bool "X-NUCLEO-IHM16M1 board support" + default n + ---help--- + Board based on the STSPIN830 three-phase brushless motor driver. + +if BOARD_STM32_IHM16M1 + +config BOARD_STM32_IHM16M1_VBUS + bool "X-NUCLEO-IHM16M1 board VBUS sense" + default n + +config BOARD_STM32_IHM16M1_POT + bool "X-NUCLEO-IHM16M1 board POT support" + default n + +endif # BOARD_STM32_IHM16M1 + +endif # STM32_FOC + +if SENSORS_HALL3PHASE + +config BOARD_STM32_HALL3PHASE_SAMPLES + int "3-phase Hall effect sensor number of samples" + default 10 + +endif # SENSORS_HALL3PHASE + +config STM32_ROMFS + bool "Automount baked-in ROMFS image" + default n + depends on FS_ROMFS + ---help--- + Select STM32_ROMFS_IMAGEFILE, STM32_ROMFS_DEV_MINOR, STM32_ROMFS_MOUNTPOINT + +config STM32_ROMFS_DEV_MINOR + int "Minor for the block device backing the data" + depends on STM32_ROMFS + default 64 + +config STM32_ROMFS_MOUNTPOINT + string "Mountpoint of the custom romfs image" + depends on STM32_ROMFS + default "/rom" + +config STM32_ROMFS_IMAGEFILE + string "ROMFS image file to include into build" + depends on STM32_ROMFS + default "../../../rom.img" + +config STM32_SPI_TEST + bool "Enable SPI test" + default n + ---help--- + Enable Spi test - initialize and configure SPI to send + STM32_SPI_TEST_MESSAGE text. The text is sent on the + selected SPI Buses with the configured parameters. + Note the CS lines will not be asserted. + +if STM32_SPI_TEST + +config STM32_SPI_TEST_MESSAGE + string "Text to Send on SPI Bus(es)" + default "Hello World" + depends on STM32_SPI_TEST + ---help--- + Text to sent on SPI bus(es) + +config STM32_SPI1_TEST + bool "Test SPI bus 1" + default n + depends on STM32_SPI_TEST + ---help--- + Enable Spi test - on SPI BUS 1 + +if STM32_SPI1_TEST + +config STM32_SPI1_TEST_FREQ + int "SPI 1 Clock Freq in Hz" + default 1000000 + depends on STM32_SPI1_TEST + ---help--- + Sets SPI 1 Clock Freq + +config STM32_SPI1_TEST_BITS + int "SPI 1 number of bits" + default 8 + depends on STM32_SPI1_TEST + ---help--- + Sets SPI 1 bit length + +choice + prompt "SPI BUS 1 Clock Mode" + default STM32_SPI1_TEST_MODE3 + ---help--- + Sets SPI 1 clock mode + +config STM32_SPI1_TEST_MODE0 + bool "CPOL=0 CPHA=0" + +config STM32_SPI1_TEST_MODE1 + bool "CPOL=0 CPHA=1" + +config STM32_SPI1_TEST_MODE2 + bool "CPOL=1 CPHA=0" + +config STM32_SPI1_TEST_MODE3 + bool "CPOL=1 CPHA=1" + +endchoice # "SPI BUS 1 Clock Mode" + +endif # STM32_SPI1_TEST + +config STM32_SPI2_TEST + bool "Test SPI bus 2" + default n + depends on STM32_SPI_TEST + ---help--- + Enable Spi test - on SPI BUS 2 + +if STM32_SPI2_TEST + +config STM32_SPI2_TEST_FREQ + int "SPI 2 Clock Freq in Hz" + default 12000000 + depends on STM32_SPI2_TEST + ---help--- + Sets SPI 2 Clock Freq + +config STM32_SPI2_TEST_BITS + int "SPI 2 number of bits" + default 8 + depends on STM32_SPI2_TEST + ---help--- + Sets SPI 2 bit length + +choice + prompt "SPI BUS 2 Clock Mode" + default STM32_SPI2_TEST_MODE3 + ---help--- + Sets SPI 2 clock mode + +config STM32_SPI2_TEST_MODE0 + bool "CPOL=0 CPHA=0" + +config STM32_SPI2_TEST_MODE1 + bool "CPOL=0 CPHA=1" + +config STM32_SPI2_TEST_MODE2 + bool "CPOL=1 CPHA=0" + +config STM32_SPI2_TEST_MODE3 + bool "CPOL=1 CPHA=1" + +endchoice # "SPI BUS 2 Clock Mode" + +endif # STM32_SPI2_TEST + +config STM32_SPI3_TEST + bool "Test SPI bus 3" + default n + depends on STM32_SPI_TEST + ---help--- + Enable Spi test - on SPI BUS 3 + +if STM32_SPI3_TEST + +config STM32_SPI3_TEST_FREQ + int "SPI 3 Clock Freq in Hz" + default 40000000 + depends on STM32_SPI3_TEST + ---help--- + Sets SPI 3 Clock Freq + +config STM32_SPI3_TEST_BITS + int "SPI 3 number of bits" + default 8 + depends on STM32_SPI3_TEST + ---help--- + Sets SPI 3 bit length + +choice + prompt "SPI BUS 3 Clock Mode" + default STM32_SPI3_TEST_MODE3 + ---help--- + Sets SPI 3 clock mode + +config STM32_SPI3_TEST_MODE0 + bool "CPOL=0 CPHA=0" + +config STM32_SPI3_TEST_MODE1 + bool "CPOL=0 CPHA=1" + +config STM32_SPI3_TEST_MODE2 + bool "CPOL=1 CPHA=0" + +config STM32_SPI3_TEST_MODE3 + bool "CPOL=1 CPHA=1" + +endchoice # "SPI BUS 3 Clock Mode" + +endif # STM32_SPI3_TEST +endif # STM32_SPI_TEST diff --git a/boards/arm/common/stm32/Makefile b/boards/arm/common/stm32/Makefile new file mode 100644 index 0000000000000..3ce135c107029 --- /dev/null +++ b/boards/arm/common/stm32/Makefile @@ -0,0 +1,35 @@ +############################################################################# +# boards/arm/common/stm32/Makefile +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################# + +include $(TOPDIR)/Make.defs + +include board/Make.defs +include src/Make.defs + +DEPPATH += --dep-path board +DEPPATH += --dep-path src + +include $(TOPDIR)/boards/Board.mk + +ARCHSRCDIR = $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src +BOARDDIR = $(ARCHSRCDIR)$(DELIM)board +CFLAGS += ${INCDIR_PREFIX}$(BOARDDIR)$(DELIM)include diff --git a/boards/arm/stm32/common/include/board_hall3ph.h b/boards/arm/common/stm32/include/board_hall3ph.h similarity index 91% rename from boards/arm/stm32/common/include/board_hall3ph.h rename to boards/arm/common/stm32/include/board_hall3ph.h index 3cd1f2d819a18..21ab10f8220db 100644 --- a/boards/arm/stm32/common/include/board_hall3ph.h +++ b/boards/arm/common/stm32/include/board_hall3ph.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/include/board_hall3ph.h + * boards/arm/common/stm32/include/board_hall3ph.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32_COMMON_INCLUDE_BOARD_HALL3PH_H -#define __BOARDS_ARM_STM32_COMMON_INCLUDE_BOARD_HALL3PH_H +#ifndef __BOARDS_ARM_COMMON_STM32_INCLUDE_BOARD_HALL3PH_H +#define __BOARDS_ARM_COMMON_STM32_INCLUDE_BOARD_HALL3PH_H /**************************************************************************** * Included Files @@ -66,4 +66,4 @@ int board_hall3ph_initialize(int devno, int pha, int phb, int phc); } #endif -#endif /* __BOARDS_ARM_STM32_COMMON_INCLUDE_BOARD_HALL3PH_H */ +#endif /* __BOARDS_ARM_COMMON_STM32_INCLUDE_BOARD_HALL3PH_H */ diff --git a/boards/arm/stm32f0l0g0/common/include/board_pwm.h b/boards/arm/common/stm32/include/board_pwm.h similarity index 85% rename from boards/arm/stm32f0l0g0/common/include/board_pwm.h rename to boards/arm/common/stm32/include/board_pwm.h index b86407e0aa590..2e67391573319 100644 --- a/boards/arm/stm32f0l0g0/common/include/board_pwm.h +++ b/boards/arm/common/stm32/include/board_pwm.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/common/include/board_pwm.h + * boards/arm/common/stm32/include/board_pwm.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32F0L0G0_COMMON_INCLUDE_BOARD_PWM_H -#define __BOARDS_ARM_STM32F0L0G0_COMMON_INCLUDE_BOARD_PWM_H +#ifndef __BOARDS_ARM_COMMON_STM32_INCLUDE_BOARD_PWM_H +#define __BOARDS_ARM_COMMON_STM32_INCLUDE_BOARD_PWM_H /**************************************************************************** * Included Files @@ -37,4 +37,4 @@ int stm32_pwm_setup(void); #endif -#endif /* __BOARDS_ARM_STM32F0L0G0_COMMON_INCLUDE_BOARD_PWM_H */ +#endif /* __BOARDS_ARM_COMMON_STM32_INCLUDE_BOARD_PWM_H */ diff --git a/boards/arm/common/stm32/include/board_qencoder.h b/boards/arm/common/stm32/include/board_qencoder.h new file mode 100644 index 0000000000000..241f64d4ad089 --- /dev/null +++ b/boards/arm/common/stm32/include/board_qencoder.h @@ -0,0 +1,75 @@ +/**************************************************************************** + * boards/arm/common/stm32/include/board_qencoder.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_COMMON_STM32_INCLUDE_BOARD_QENCODER_H +#define __BOARDS_ARM_COMMON_STM32_INCLUDE_BOARD_QENCODER_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Inline Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: board_qencoder_initialize + * + * Description: + * Initialize the quadrature encoder driver for the given timer + * + ****************************************************************************/ + +int board_qencoder_initialize(int devno, int timerno); + +#undef EXTERN +#ifdef __cplusplus +} +#endif + +#endif /* __BOARDS_ARM_COMMON_STM32_INCLUDE_BOARD_QENCODER_H */ diff --git a/boards/arm/stm32/common/include/board_sbutton.h b/boards/arm/common/stm32/include/board_sbutton.h similarity index 92% rename from boards/arm/stm32/common/include/board_sbutton.h rename to boards/arm/common/stm32/include/board_sbutton.h index 0dd67c113980a..f123d0b4f5789 100644 --- a/boards/arm/stm32/common/include/board_sbutton.h +++ b/boards/arm/common/stm32/include/board_sbutton.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/include/board_sbutton.h + * boards/arm/common/stm32/include/board_sbutton.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32_COMMON_INCLUDE_BOARD_SBUTTON_H -#define __BOARDS_ARM_STM32_COMMON_INCLUDE_BOARD_SBUTTON_H +#ifndef __BOARDS_ARM_COMMON_STM32_INCLUDE_BOARD_SBUTTON_H +#define __BOARDS_ARM_COMMON_STM32_INCLUDE_BOARD_SBUTTON_H /**************************************************************************** * Included Files @@ -80,4 +80,4 @@ int board_sbutton_initialize(int devno); } #endif -#endif /* __BOARDS_ARM_STM32_COMMON_INCLUDE_BOARD_SBUTTON_H */ +#endif /* __BOARDS_ARM_COMMON_STM32_INCLUDE_BOARD_SBUTTON_H */ diff --git a/boards/arm/stm32/common/include/stm32_amg88xx.h b/boards/arm/common/stm32/include/stm32_amg88xx.h similarity index 92% rename from boards/arm/stm32/common/include/stm32_amg88xx.h rename to boards/arm/common/stm32/include/stm32_amg88xx.h index c8cb6fb724f64..e11cee5e7e8b9 100644 --- a/boards/arm/stm32/common/include/stm32_amg88xx.h +++ b/boards/arm/common/stm32/include/stm32_amg88xx.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/include/stm32_amg88xx.h + * boards/arm/common/stm32/include/stm32_amg88xx.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_AMG88XX_H -#define __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_AMG88XX_H +#ifndef __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_AMG88XX_H +#define __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_AMG88XX_H /**************************************************************************** * Included Files @@ -78,4 +78,4 @@ int board_amg88xx_initialize(int busno); } #endif -#endif /* __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_AMG88XX_H */ +#endif /* __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_AMG88XX_H */ diff --git a/boards/arm/stm32/common/include/stm32_apa102.h b/boards/arm/common/stm32/include/stm32_apa102.h similarity index 92% rename from boards/arm/stm32/common/include/stm32_apa102.h rename to boards/arm/common/stm32/include/stm32_apa102.h index 241fb474b0714..ad36c2e60682a 100644 --- a/boards/arm/stm32/common/include/stm32_apa102.h +++ b/boards/arm/common/stm32/include/stm32_apa102.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/include/stm32_apa102.h + * boards/arm/common/stm32/include/stm32_apa102.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_APA102_H -#define __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_APA102_H +#ifndef __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_APA102_H +#define __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_APA102_H /**************************************************************************** * Included Files @@ -83,4 +83,4 @@ int board_apa102_initialize(int devno, int spino); } #endif -#endif /* __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_APA102_H */ +#endif /* __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_APA102_H */ diff --git a/boards/arm/stm32/common/include/stm32_apds9960.h b/boards/arm/common/stm32/include/stm32_apds9960.h similarity index 92% rename from boards/arm/stm32/common/include/stm32_apds9960.h rename to boards/arm/common/stm32/include/stm32_apds9960.h index c38b3a5bdf897..c2fe29bae609f 100644 --- a/boards/arm/stm32/common/include/stm32_apds9960.h +++ b/boards/arm/common/stm32/include/stm32_apds9960.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/include/stm32_apds9960.h + * boards/arm/common/stm32/include/stm32_apds9960.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_APDS9960_H -#define __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_APDS9960_H +#ifndef __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_APDS9960_H +#define __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_APDS9960_H /**************************************************************************** * Included Files @@ -79,4 +79,4 @@ int board_apds9960_initialize(int devno, int busno); } #endif -#endif /* __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_APDS9960_H */ +#endif /* __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_APDS9960_H */ diff --git a/boards/arm/common/stm32/include/stm32_bh1750.h b/boards/arm/common/stm32/include/stm32_bh1750.h new file mode 100644 index 0000000000000..96be9db21f1c8 --- /dev/null +++ b/boards/arm/common/stm32/include/stm32_bh1750.h @@ -0,0 +1,82 @@ +/**************************************************************************** + * boards/arm/common/stm32/include/stm32_bh1750.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_BH1750_H +#define __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_BH1750_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Inline Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: board_bh1750_initialize + * + * Description: + * Initialize and register the BH1750FVI Ambient Light driver. + * + * Input Parameters: + * devno - The device number, used to build the device path as /dev/lightN + * busno - The I2C bus number + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +int board_bh1750_initialize(int devno, int busno); + +#undef EXTERN +#ifdef __cplusplus +} +#endif + +#endif /* __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_BH1750_H */ diff --git a/boards/arm/stm32f7/common/include/stm32_bmi270.h b/boards/arm/common/stm32/include/stm32_bmi270.h similarity index 92% rename from boards/arm/stm32f7/common/include/stm32_bmi270.h rename to boards/arm/common/stm32/include/stm32_bmi270.h index 50d4be70ae763..8b3d23c9a06ea 100644 --- a/boards/arm/stm32f7/common/include/stm32_bmi270.h +++ b/boards/arm/common/stm32/include/stm32_bmi270.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f7/common/include/stm32_bmi270.h + * boards/arm/common/stm32/include/stm32_bmi270.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32F7_COMMON_INCLUDE_STM32_BMI270_H -#define __BOARDS_ARM_STM32F7_COMMON_INCLUDE_STM32_BMI270_H +#ifndef __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_BMI270_H +#define __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_BMI270_H /**************************************************************************** * Included Files @@ -79,4 +79,4 @@ int board_bmi270_initialize(int devno, int busno); } #endif -#endif /* __BOARDS_ARM_STM32F7_COMMON_INCLUDE_STM32_BMI270_H */ +#endif /* __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_BMI270_H */ diff --git a/boards/arm/stm32/common/include/stm32_bmp180.h b/boards/arm/common/stm32/include/stm32_bmp180.h similarity index 92% rename from boards/arm/stm32/common/include/stm32_bmp180.h rename to boards/arm/common/stm32/include/stm32_bmp180.h index 0e963442c9bb3..6b7865c6e9ba4 100644 --- a/boards/arm/stm32/common/include/stm32_bmp180.h +++ b/boards/arm/common/stm32/include/stm32_bmp180.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/include/stm32_bmp180.h + * boards/arm/common/stm32/include/stm32_bmp180.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_BMP180_H -#define __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_BMP180_H +#ifndef __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_BMP180_H +#define __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_BMP180_H /**************************************************************************** * Included Files @@ -83,4 +83,4 @@ int board_bmp180_initialize(int devno, int busno); } #endif -#endif /* __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_BMP180_H */ +#endif /* __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_BMP180_H */ diff --git a/boards/arm/stm32/common/include/stm32_bmp280.h b/boards/arm/common/stm32/include/stm32_bmp280.h similarity index 92% rename from boards/arm/stm32/common/include/stm32_bmp280.h rename to boards/arm/common/stm32/include/stm32_bmp280.h index cf558b6791f90..22b375eaaa5de 100644 --- a/boards/arm/stm32/common/include/stm32_bmp280.h +++ b/boards/arm/common/stm32/include/stm32_bmp280.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/include/stm32_bmp280.h + * boards/arm/common/stm32/include/stm32_bmp280.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_BMP280_H -#define __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_BMP280_H +#ifndef __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_BMP280_H +#define __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_BMP280_H /**************************************************************************** * Included Files @@ -83,4 +83,4 @@ int board_bmp280_initialize(int devno, int busno); } #endif -#endif /* __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_BMP280_H */ +#endif /* __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_BMP280_H */ diff --git a/boards/arm/stm32f7/common/include/stm32_can_setup.h b/boards/arm/common/stm32/include/stm32_can_setup.h similarity index 89% rename from boards/arm/stm32f7/common/include/stm32_can_setup.h rename to boards/arm/common/stm32/include/stm32_can_setup.h index 5361bfe204abe..9cd211d05b98b 100644 --- a/boards/arm/stm32f7/common/include/stm32_can_setup.h +++ b/boards/arm/common/stm32/include/stm32_can_setup.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f7/common/include/stm32_can_setup.h + * boards/arm/common/stm32/include/stm32_can_setup.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32F7_COMMON_INCLUDE_STM32_CAN_SETUP_H -#define __BOARDS_ARM_STM32F7_COMMON_INCLUDE_STM32_CAN_SETUP_H +#ifndef __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_CAN_SETUP_H +#define __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_CAN_SETUP_H /**************************************************************************** * Included Files @@ -61,7 +61,7 @@ extern "C" * Name: stm32_can_setup ****************************************************************************/ -#ifdef CONFIG_STM32F7_CAN_CHARDRIVER +#ifdef CONFIG_STM32_CAN_CHARDRIVER int stm32_can_setup(void); #endif @@ -70,4 +70,4 @@ int stm32_can_setup(void); } #endif -#endif /* __BOARDS_ARM_STM32F7_COMMON_INCLUDE_STM32_CAN_SETUP_H */ +#endif /* __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_CAN_SETUP_H */ diff --git a/boards/arm/stm32f7/common/include/stm32_cansock_setup.h b/boards/arm/common/stm32/include/stm32_cansock_setup.h similarity index 89% rename from boards/arm/stm32f7/common/include/stm32_cansock_setup.h rename to boards/arm/common/stm32/include/stm32_cansock_setup.h index 971f2216dcbe2..77a41b66574fa 100644 --- a/boards/arm/stm32f7/common/include/stm32_cansock_setup.h +++ b/boards/arm/common/stm32/include/stm32_cansock_setup.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f7/common/include/stm32_cansock_setup.h + * boards/arm/common/stm32/include/stm32_cansock_setup.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32F7_COMMON_INCLUDE_STM32_CANSOCK_SETUP_H -#define __BOARDS_ARM_STM32F7_COMMON_INCLUDE_STM32_CANSOCK_SETUP_H +#ifndef __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_CANSOCK_SETUP_H +#define __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_CANSOCK_SETUP_H /**************************************************************************** * Included Files @@ -61,7 +61,7 @@ extern "C" * Name: stm32_cansock_setup ****************************************************************************/ -#ifdef CONFIG_STM32F7_CAN_SOCKET +#ifdef CONFIG_STM32_CAN_SOCKET int stm32_cansock_setup(void); #endif @@ -70,4 +70,4 @@ int stm32_cansock_setup(void); } #endif -#endif /* __BOARDS_ARM_STM32F7_COMMON_INCLUDE_STM32_CANSOCK_SETUP_H */ +#endif /* __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_CANSOCK_SETUP_H */ diff --git a/boards/arm/stm32f7/common/include/stm32_cs4344.h b/boards/arm/common/stm32/include/stm32_cs4344.h similarity index 92% rename from boards/arm/stm32f7/common/include/stm32_cs4344.h rename to boards/arm/common/stm32/include/stm32_cs4344.h index 5050fb7345f11..eb84188d0380e 100644 --- a/boards/arm/stm32f7/common/include/stm32_cs4344.h +++ b/boards/arm/common/stm32/include/stm32_cs4344.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f7/common/include/stm32_cs4344.h + * boards/arm/common/stm32/include/stm32_cs4344.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32F7_COMMON_INCLUDE_STM32_CS4344_H -#define __BOARDS_ARM_STM32F7_COMMON_INCLUDE_STM32_CS4344_H +#ifndef __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_CS4344_H +#define __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_CS4344_H /**************************************************************************** * Included Files @@ -81,4 +81,4 @@ int board_cs4344_initialize(int devno, int port); } #endif -#endif /* __BOARDS_ARM_STM32F7_COMMON_INCLUDE_STM32_CS4344_H */ +#endif /* __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_CS4344_H */ diff --git a/boards/arm/stm32/common/include/stm32_dhtxx.h b/boards/arm/common/stm32/include/stm32_dhtxx.h similarity index 92% rename from boards/arm/stm32/common/include/stm32_dhtxx.h rename to boards/arm/common/stm32/include/stm32_dhtxx.h index 7c1b5d6a9f41b..5b971aa41ae3b 100644 --- a/boards/arm/stm32/common/include/stm32_dhtxx.h +++ b/boards/arm/common/stm32/include/stm32_dhtxx.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/include/stm32_dhtxx.h + * boards/arm/common/stm32/include/stm32_dhtxx.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_DHTXX_H -#define __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_DHTXX_H +#ifndef __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_DHTXX_H +#define __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_DHTXX_H /**************************************************************************** * Included Files @@ -80,4 +80,4 @@ int board_dhtxx_initialize(int devno); } #endif -#endif /* __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_DHTXX_H */ +#endif /* __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_DHTXX_H */ diff --git a/boards/arm/stm32/common/include/stm32_drv8266.h b/boards/arm/common/stm32/include/stm32_drv8266.h similarity index 91% rename from boards/arm/stm32/common/include/stm32_drv8266.h rename to boards/arm/common/stm32/include/stm32_drv8266.h index f0252073074af..ec0dc22b10c08 100644 --- a/boards/arm/stm32/common/include/stm32_drv8266.h +++ b/boards/arm/common/stm32/include/stm32_drv8266.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/include/stm32_drv8266.h + * boards/arm/common/stm32/include/stm32_drv8266.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_DRV8825_H -#define __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_DRV8825_H +#ifndef __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_DRV8825_H +#define __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_DRV8825_H /**************************************************************************** * Included Files @@ -72,4 +72,4 @@ int board_drv8825_initialize(int devno); } #endif -#endif /* __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_DRV8825_H */ +#endif /* __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_DRV8825_H */ diff --git a/boards/arm/stm32/common/include/stm32_ds1307.h b/boards/arm/common/stm32/include/stm32_ds1307.h similarity index 92% rename from boards/arm/stm32/common/include/stm32_ds1307.h rename to boards/arm/common/stm32/include/stm32_ds1307.h index 6baf58c63c4db..2e39c16ffba10 100644 --- a/boards/arm/stm32/common/include/stm32_ds1307.h +++ b/boards/arm/common/stm32/include/stm32_ds1307.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/include/stm32_ds1307.h + * boards/arm/common/stm32/include/stm32_ds1307.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_DS1307_H -#define __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_DS1307_H +#ifndef __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_DS1307_H +#define __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_DS1307_H /**************************************************************************** * Included Files @@ -82,4 +82,4 @@ int board_ds1307_initialize(int busno); } #endif -#endif /* __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_DS1307_H */ +#endif /* __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_DS1307_H */ diff --git a/boards/arm/stm32/common/include/stm32_hcsr04.h b/boards/arm/common/stm32/include/stm32_hcsr04.h similarity index 92% rename from boards/arm/stm32/common/include/stm32_hcsr04.h rename to boards/arm/common/stm32/include/stm32_hcsr04.h index d58e0e503564a..59ab41da73b89 100644 --- a/boards/arm/stm32/common/include/stm32_hcsr04.h +++ b/boards/arm/common/stm32/include/stm32_hcsr04.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/include/stm32_hcsr04.h + * boards/arm/common/stm32/include/stm32_hcsr04.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_HCSR04_H -#define __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_HCSR04_H +#ifndef __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_HCSR04_H +#define __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_HCSR04_H /**************************************************************************** * Included Files @@ -80,4 +80,4 @@ int board_hcsr04_initialize(int devno); } #endif -#endif /* __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_HCSR04_H */ +#endif /* __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_HCSR04_H */ diff --git a/boards/arm/stm32/common/include/stm32_ihm07m1.h b/boards/arm/common/stm32/include/stm32_ihm07m1.h similarity index 89% rename from boards/arm/stm32/common/include/stm32_ihm07m1.h rename to boards/arm/common/stm32/include/stm32_ihm07m1.h index 6de00e3ec97e3..32c5601bc73c3 100644 --- a/boards/arm/stm32/common/include/stm32_ihm07m1.h +++ b/boards/arm/common/stm32/include/stm32_ihm07m1.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/include/stm32_ihm07m1.h + * boards/arm/common/stm32/include/stm32_ihm07m1.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_IHM07M1_H -#define __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_IHM07M1_H +#ifndef __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_IHM07M1_H +#define __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_IHM07M1_H /**************************************************************************** * Included Files @@ -58,4 +58,4 @@ int board_ihm07m1_initialize(struct stm32_foc_adc_s *adc_cfg); } #endif -#endif /* __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_IHM07M1_H */ +#endif /* __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_IHM07M1_H */ diff --git a/boards/arm/stm32/common/include/stm32_ihm08m1.h b/boards/arm/common/stm32/include/stm32_ihm08m1.h similarity index 89% rename from boards/arm/stm32/common/include/stm32_ihm08m1.h rename to boards/arm/common/stm32/include/stm32_ihm08m1.h index 3f9738eadb3e1..eaee68a8875a4 100644 --- a/boards/arm/stm32/common/include/stm32_ihm08m1.h +++ b/boards/arm/common/stm32/include/stm32_ihm08m1.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/include/stm32_ihm08m1.h + * boards/arm/common/stm32/include/stm32_ihm08m1.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_IHM08M1_H -#define __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_IHM08M1_H +#ifndef __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_IHM08M1_H +#define __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_IHM08M1_H /**************************************************************************** * Included Files @@ -58,4 +58,4 @@ int board_ihm08m1_initialize(struct stm32_foc_adc_s *adc_cfg); } #endif -#endif /* __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_IHM08M1_H */ +#endif /* __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_IHM08M1_H */ diff --git a/boards/arm/stm32/common/include/stm32_ihm16m1.h b/boards/arm/common/stm32/include/stm32_ihm16m1.h similarity index 89% rename from boards/arm/stm32/common/include/stm32_ihm16m1.h rename to boards/arm/common/stm32/include/stm32_ihm16m1.h index 442dc3bb3863f..76ff0c49b8e51 100644 --- a/boards/arm/stm32/common/include/stm32_ihm16m1.h +++ b/boards/arm/common/stm32/include/stm32_ihm16m1.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/include/stm32_ihm16m1.h + * boards/arm/common/stm32/include/stm32_ihm16m1.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_IHM16M1_H -#define __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_IHM16M1_H +#ifndef __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_IHM16M1_H +#define __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_IHM16M1_H /**************************************************************************** * Included Files @@ -58,4 +58,4 @@ int board_ihm16m1_initialize(struct stm32_foc_adc_s *adc_cfg); } #endif -#endif /* __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_IHM16M1_H */ +#endif /* __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_IHM16M1_H */ diff --git a/boards/arm/stm32/common/include/stm32_ina219.h b/boards/arm/common/stm32/include/stm32_ina219.h similarity index 92% rename from boards/arm/stm32/common/include/stm32_ina219.h rename to boards/arm/common/stm32/include/stm32_ina219.h index 4fa91899c3d09..20b5a1e4656d8 100644 --- a/boards/arm/stm32/common/include/stm32_ina219.h +++ b/boards/arm/common/stm32/include/stm32_ina219.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/include/stm32_ina219.h + * boards/arm/common/stm32/include/stm32_ina219.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_INA219_H -#define __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_INA219_H +#ifndef __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_INA219_H +#define __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_INA219_H /**************************************************************************** * Included Files @@ -79,4 +79,4 @@ int board_ina219_initialize(int devno, int busno); } #endif -#endif /* __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_INA219_H */ +#endif /* __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_INA219_H */ diff --git a/boards/arm/stm32/common/include/stm32_kmatrix_gpio.h b/boards/arm/common/stm32/include/stm32_kmatrix_gpio.h similarity index 92% rename from boards/arm/stm32/common/include/stm32_kmatrix_gpio.h rename to boards/arm/common/stm32/include/stm32_kmatrix_gpio.h index 6615fcc9b36fe..bfad9923c9a39 100644 --- a/boards/arm/stm32/common/include/stm32_kmatrix_gpio.h +++ b/boards/arm/common/stm32/include/stm32_kmatrix_gpio.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/include/stm32_kmatrix_gpio.h + * boards/arm/common/stm32/include/stm32_kmatrix_gpio.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_KMATRIX_GPIO_H -#define __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_KMATRIX_GPIO_H +#ifndef __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_KMATRIX_GPIO_H +#define __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_KMATRIX_GPIO_H /**************************************************************************** * Included Files @@ -84,4 +84,4 @@ int board_kmatrix_initialize(const char *devpath); } #endif -#endif /* __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_KMATRIX_GPIO_H */ +#endif /* __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_KMATRIX_GPIO_H */ diff --git a/boards/arm/stm32/common/include/stm32_kmatrix_i2c.h b/boards/arm/common/stm32/include/stm32_kmatrix_i2c.h similarity index 92% rename from boards/arm/stm32/common/include/stm32_kmatrix_i2c.h rename to boards/arm/common/stm32/include/stm32_kmatrix_i2c.h index 82669a943dbc4..51f6295e5ec2a 100644 --- a/boards/arm/stm32/common/include/stm32_kmatrix_i2c.h +++ b/boards/arm/common/stm32/include/stm32_kmatrix_i2c.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/include/stm32_kmatrix_i2c.h + * boards/arm/common/stm32/include/stm32_kmatrix_i2c.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_KMATRIX_I2C_H -#define __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_KMATRIX_I2C_H +#ifndef __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_KMATRIX_I2C_H +#define __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_KMATRIX_I2C_H /**************************************************************************** * Included Files @@ -84,4 +84,4 @@ int board_kmatrix_i2c_initialize(const char *devpath); } #endif -#endif /* __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_KMATRIX_I2C_H */ +#endif /* __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_KMATRIX_I2C_H */ diff --git a/boards/arm/stm32/common/include/stm32_l3gd20.h b/boards/arm/common/stm32/include/stm32_l3gd20.h similarity index 92% rename from boards/arm/stm32/common/include/stm32_l3gd20.h rename to boards/arm/common/stm32/include/stm32_l3gd20.h index 8400e1193456d..edd5c6ca3b5e2 100644 --- a/boards/arm/stm32/common/include/stm32_l3gd20.h +++ b/boards/arm/common/stm32/include/stm32_l3gd20.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/include/stm32_l3gd20.h + * boards/arm/common/stm32/include/stm32_l3gd20.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_L3GD20_H -#define __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_L3GD20_H +#ifndef __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_L3GD20_H +#define __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_L3GD20_H /**************************************************************************** * Included Files @@ -80,4 +80,4 @@ int board_l3gd20_initialize(int devno, int busno); } #endif -#endif /* __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_L3GD20_H */ +#endif /* __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_L3GD20_H */ diff --git a/boards/arm/stm32/common/include/stm32_lcd_backpack.h b/boards/arm/common/stm32/include/stm32_lcd_backpack.h similarity index 92% rename from boards/arm/stm32/common/include/stm32_lcd_backpack.h rename to boards/arm/common/stm32/include/stm32_lcd_backpack.h index f0923df0c2a2a..731e0ed039f66 100644 --- a/boards/arm/stm32/common/include/stm32_lcd_backpack.h +++ b/boards/arm/common/stm32/include/stm32_lcd_backpack.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/include/stm32_lcd_backpack.h + * boards/arm/common/stm32/include/stm32_lcd_backpack.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_LCD_BACKPACK_H -#define __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_LCD_BACKPACK_H +#ifndef __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_LCD_BACKPACK_H +#define __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_LCD_BACKPACK_H /**************************************************************************** * Included Files @@ -82,4 +82,4 @@ int board_lcd_backpack_init(int devno, int busno, int rows, int cols); } #endif -#endif /* __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_LCD_BACKPACK_H */ +#endif /* __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_LCD_BACKPACK_H */ diff --git a/boards/arm/stm32/common/include/stm32_lis3dsh.h b/boards/arm/common/stm32/include/stm32_lis3dsh.h similarity index 92% rename from boards/arm/stm32/common/include/stm32_lis3dsh.h rename to boards/arm/common/stm32/include/stm32_lis3dsh.h index 6c28d6e8b1c26..ea92bd41f5718 100644 --- a/boards/arm/stm32/common/include/stm32_lis3dsh.h +++ b/boards/arm/common/stm32/include/stm32_lis3dsh.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/include/stm32_lis3dsh.h + * boards/arm/common/stm32/include/stm32_lis3dsh.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_LIS3DSH_H -#define __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_LIS3DSH_H +#ifndef __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_LIS3DSH_H +#define __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_LIS3DSH_H /**************************************************************************** * Included Files @@ -79,4 +79,4 @@ int board_lis3dsh_initialize(int devno, int busno); } #endif -#endif /* __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_LIS3DSH_H */ +#endif /* __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_LIS3DSH_H */ diff --git a/boards/arm/stm32/common/include/stm32_lm75.h b/boards/arm/common/stm32/include/stm32_lm75.h similarity index 92% rename from boards/arm/stm32/common/include/stm32_lm75.h rename to boards/arm/common/stm32/include/stm32_lm75.h index 74e846e3a1391..339d91433d1f4 100644 --- a/boards/arm/stm32/common/include/stm32_lm75.h +++ b/boards/arm/common/stm32/include/stm32_lm75.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/include/stm32_lm75.h + * boards/arm/common/stm32/include/stm32_lm75.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_LM75_H -#define __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_LM75_H +#ifndef __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_LM75_H +#define __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_LM75_H /**************************************************************************** * Included Files @@ -79,4 +79,4 @@ int board_lm75_initialize(int devno, int busno); } #endif -#endif /* __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_LM75_H */ +#endif /* __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_LM75_H */ diff --git a/boards/arm/stm32/common/include/stm32_max31855.h b/boards/arm/common/stm32/include/stm32_max31855.h similarity index 92% rename from boards/arm/stm32/common/include/stm32_max31855.h rename to boards/arm/common/stm32/include/stm32_max31855.h index 36196eb6602be..243bd335ea9c1 100644 --- a/boards/arm/stm32/common/include/stm32_max31855.h +++ b/boards/arm/common/stm32/include/stm32_max31855.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/include/stm32_max31855.h + * boards/arm/common/stm32/include/stm32_max31855.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_MAX31855_H -#define __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_MAX31855_H +#ifndef __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_MAX31855_H +#define __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_MAX31855_H /**************************************************************************** * Included Files @@ -79,4 +79,4 @@ int board_max31855_initialize(int devno, int busno); } #endif -#endif /* __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_MAX31855_H */ +#endif /* __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_MAX31855_H */ diff --git a/boards/arm/stm32/common/include/stm32_max6675.h b/boards/arm/common/stm32/include/stm32_max6675.h similarity index 92% rename from boards/arm/stm32/common/include/stm32_max6675.h rename to boards/arm/common/stm32/include/stm32_max6675.h index 01cdd85bc615c..6386116c9df62 100644 --- a/boards/arm/stm32/common/include/stm32_max6675.h +++ b/boards/arm/common/stm32/include/stm32_max6675.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/include/stm32_max6675.h + * boards/arm/common/stm32/include/stm32_max6675.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_MAX6675_H -#define __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_MAX6675_H +#ifndef __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_MAX6675_H +#define __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_MAX6675_H /**************************************************************************** * Included Files @@ -83,4 +83,4 @@ int board_max6675_initialize(int devno, int busno); } #endif -#endif /* __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_MAX6675_H */ +#endif /* __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_MAX6675_H */ diff --git a/boards/arm/stm32/common/include/stm32_max7219_matrix.h b/boards/arm/common/stm32/include/stm32_max7219_matrix.h similarity index 91% rename from boards/arm/stm32/common/include/stm32_max7219_matrix.h rename to boards/arm/common/stm32/include/stm32_max7219_matrix.h index a22addd854355..fea20cbaea3e2 100644 --- a/boards/arm/stm32/common/include/stm32_max7219_matrix.h +++ b/boards/arm/common/stm32/include/stm32_max7219_matrix.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/include/stm32_max7219_matrix.h + * boards/arm/common/stm32/include/stm32_max7219_matrix.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_MAX7219_H -#define __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_MAX7219_H +#ifndef __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_MAX7219_H +#define __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_MAX7219_H /**************************************************************************** * Included Files @@ -78,4 +78,4 @@ int board_max7219_matrix_initialize(int busno); } #endif -#endif /* __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_MAX7219_H */ +#endif /* __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_MAX7219_H */ diff --git a/boards/arm/stm32/common/include/stm32_mfrc522.h b/boards/arm/common/stm32/include/stm32_mfrc522.h similarity index 92% rename from boards/arm/stm32/common/include/stm32_mfrc522.h rename to boards/arm/common/stm32/include/stm32_mfrc522.h index 6934ea3de6a6b..46a3956b264c0 100644 --- a/boards/arm/stm32/common/include/stm32_mfrc522.h +++ b/boards/arm/common/stm32/include/stm32_mfrc522.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/include/stm32_mfrc522.h + * boards/arm/common/stm32/include/stm32_mfrc522.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_MFRC522_H -#define __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_MFRC522_H +#ifndef __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_MFRC522_H +#define __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_MFRC522_H /**************************************************************************** * Included Files @@ -78,4 +78,4 @@ int stm32_mfrc522initialize(const char *devpath); } #endif -#endif /* __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_MFRC522_H */ +#endif /* __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_MFRC522_H */ diff --git a/boards/arm/stm32/common/include/stm32_mlx90614.h b/boards/arm/common/stm32/include/stm32_mlx90614.h similarity index 92% rename from boards/arm/stm32/common/include/stm32_mlx90614.h rename to boards/arm/common/stm32/include/stm32_mlx90614.h index 3f6bd970d8f7a..5115ae35de705 100644 --- a/boards/arm/stm32/common/include/stm32_mlx90614.h +++ b/boards/arm/common/stm32/include/stm32_mlx90614.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/include/stm32_mlx90614.h + * boards/arm/common/stm32/include/stm32_mlx90614.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_MLX90614_H -#define __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_MLX90614_H +#ifndef __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_MLX90614_H +#define __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_MLX90614_H /**************************************************************************** * Included Files @@ -79,4 +79,4 @@ int board_mlx90614_initialize(int devno, int busno); } #endif -#endif /* __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_MLX90614_H */ +#endif /* __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_MLX90614_H */ diff --git a/boards/arm/stm32/common/include/stm32_mpl115a.h b/boards/arm/common/stm32/include/stm32_mpl115a.h similarity index 92% rename from boards/arm/stm32/common/include/stm32_mpl115a.h rename to boards/arm/common/stm32/include/stm32_mpl115a.h index 88c3e3cc5a573..309d39481fda8 100644 --- a/boards/arm/stm32/common/include/stm32_mpl115a.h +++ b/boards/arm/common/stm32/include/stm32_mpl115a.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/include/stm32_mpl115a.h + * boards/arm/common/stm32/include/stm32_mpl115a.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_MPL115A_H -#define __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_MPL115A_H +#ifndef __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_MPL115A_H +#define __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_MPL115A_H /**************************************************************************** * Included Files @@ -79,4 +79,4 @@ int board_mpl115a_initialize(int devno, int busno); } #endif -#endif /* __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_MPL115A_H */ +#endif /* __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_MPL115A_H */ diff --git a/boards/arm/stm32/common/include/stm32_mpr121.h b/boards/arm/common/stm32/include/stm32_mpr121.h similarity index 92% rename from boards/arm/stm32/common/include/stm32_mpr121.h rename to boards/arm/common/stm32/include/stm32_mpr121.h index 185f2aac544c2..a35b1c0247602 100644 --- a/boards/arm/stm32/common/include/stm32_mpr121.h +++ b/boards/arm/common/stm32/include/stm32_mpr121.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/include/stm32_mpr121.h + * boards/arm/common/stm32/include/stm32_mpr121.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_MPR121_H -#define __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_MPR121_H +#ifndef __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_MPR121_H +#define __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_MPR121_H /**************************************************************************** * Included Files @@ -79,4 +79,4 @@ int board_mpr121_initialize(int devno, int busno); } #endif -#endif /* __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_MPR121_H */ +#endif /* __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_MPR121_H */ diff --git a/boards/arm/stm32/common/include/stm32_ms5611.h b/boards/arm/common/stm32/include/stm32_ms5611.h similarity index 94% rename from boards/arm/stm32/common/include/stm32_ms5611.h rename to boards/arm/common/stm32/include/stm32_ms5611.h index f5a27d3394975..2e9c63e68b074 100644 --- a/boards/arm/stm32/common/include/stm32_ms5611.h +++ b/boards/arm/common/stm32/include/stm32_ms5611.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/include/stm32_ms5611.h + * boards/arm/common/stm32/include/stm32_ms5611.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_MS5611_H -#define __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_MS5611_H +#ifndef __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_MS5611_H +#define __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_MS5611_H /**************************************************************************** * Included Files diff --git a/boards/arm/stm32/common/include/stm32_mt6816.h b/boards/arm/common/stm32/include/stm32_mt6816.h similarity index 91% rename from boards/arm/stm32/common/include/stm32_mt6816.h rename to boards/arm/common/stm32/include/stm32_mt6816.h index 2497d13aa9ad1..ff6447fded542 100644 --- a/boards/arm/stm32/common/include/stm32_mt6816.h +++ b/boards/arm/common/stm32/include/stm32_mt6816.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/include/stm32_mt6816.h + * boards/arm/common/stm32/include/stm32_mt6816.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_MT6816_H -#define __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_MT6816_H +#ifndef __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_MT6816_H +#define __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_MT6816_H /**************************************************************************** * Included Files @@ -72,4 +72,4 @@ int board_mt6816_initialize(int devno, int spi_busno); } #endif -#endif /* __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_MT6816_H */ +#endif /* __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_MT6816_H */ diff --git a/boards/arm/stm32/common/include/stm32_nrf24l01.h b/boards/arm/common/stm32/include/stm32_nrf24l01.h similarity index 91% rename from boards/arm/stm32/common/include/stm32_nrf24l01.h rename to boards/arm/common/stm32/include/stm32_nrf24l01.h index e5207c6d16d0f..8a676add6ba3d 100644 --- a/boards/arm/stm32/common/include/stm32_nrf24l01.h +++ b/boards/arm/common/stm32/include/stm32_nrf24l01.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/include/stm32_nrf24l01.h + * boards/arm/common/stm32/include/stm32_nrf24l01.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_NRF24L01_H -#define __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_NRF24L01_H +#ifndef __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_NRF24L01_H +#define __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_NRF24L01_H /**************************************************************************** * Included Files @@ -78,4 +78,4 @@ int board_nrf24l01_initialize(int busno); } #endif -#endif /* __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_NRF24L01_H */ +#endif /* __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_NRF24L01_H */ diff --git a/boards/arm/stm32/common/include/stm32_nunchuck.h b/boards/arm/common/stm32/include/stm32_nunchuck.h similarity index 92% rename from boards/arm/stm32/common/include/stm32_nunchuck.h rename to boards/arm/common/stm32/include/stm32_nunchuck.h index 138fab2feff3a..b08f8ee6b1776 100644 --- a/boards/arm/stm32/common/include/stm32_nunchuck.h +++ b/boards/arm/common/stm32/include/stm32_nunchuck.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/include/stm32_nunchuck.h + * boards/arm/common/stm32/include/stm32_nunchuck.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_NUNCHUCK_H -#define __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_NUNCHUCK_H +#ifndef __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_NUNCHUCK_H +#define __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_NUNCHUCK_H /**************************************************************************** * Included Files @@ -84,4 +84,4 @@ int board_nunchuck_initialize(int devno, int busno); } #endif -#endif /* __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_NUNCHUCK_H */ +#endif /* __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_NUNCHUCK_H */ diff --git a/boards/arm/common/stm32/include/stm32_romfs.h b/boards/arm/common/stm32/include/stm32_romfs.h new file mode 100644 index 0000000000000..cbb982ebb5cf1 --- /dev/null +++ b/boards/arm/common/stm32/include/stm32_romfs.h @@ -0,0 +1,77 @@ +/**************************************************************************** + * boards/arm/common/stm32/include/stm32_romfs.h + * + * SPDX-License-Identifier: BSD-3-Clause + * SPDX-FileCopyrightText: 2017 Tomasz Wozniak. All rights reserved. + * SPDX-FileContributor: Tomasz Wozniak + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_ROMFS_H +#define __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_ROMFS_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#ifdef CONFIG_STM32_ROMFS + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define ROMFS_SECTOR_SIZE 64 + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_romfs_initialize + * + * Description: + * Registers built-in ROMFS image as block device and mounts it. + * + * Returned Value: + * Zero (OK) on success, a negated errno value on error. + * + * Assumptions/Limitations: + * Memory addresses [romfs_data_begin .. romfs_data_end) should contain + * ROMFS volume data, as included in the assembly snippet above (l. 84). + * + ****************************************************************************/ + +int stm32_romfs_initialize(void); + +#endif /* CONFIG_STM32_ROMFS */ + +#endif /* __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_ROMFS_H */ diff --git a/boards/arm/stm32f7/common/include/stm32_spitest.h b/boards/arm/common/stm32/include/stm32_spitest.h similarity index 89% rename from boards/arm/stm32f7/common/include/stm32_spitest.h rename to boards/arm/common/stm32/include/stm32_spitest.h index 09605759e1e0b..29efe4880af6a 100644 --- a/boards/arm/stm32f7/common/include/stm32_spitest.h +++ b/boards/arm/common/stm32/include/stm32_spitest.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f7/common/include/stm32_spitest.h + * boards/arm/common/stm32/include/stm32_spitest.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32F7_COMMON_INCLUDE_STM32_SPITEST_H -#define __BOARDS_ARM_STM32F7_COMMON_INCLUDE_STM32_SPITEST_H +#ifndef __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_SPITEST_H +#define __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_SPITEST_H /**************************************************************************** * Included Files @@ -62,7 +62,7 @@ extern "C" * * Description: * Called to create the defined SPI buses and test them by initializing - * them and sending the CONFIG_STM32F7_SPI_TEST_MESSAGE (no chip select). + * them and sending the CONFIG_STM32_SPI_TEST_MESSAGE (no chip select). * ****************************************************************************/ @@ -73,4 +73,4 @@ int stm32_spidev_bus_test(void); } #endif -#endif /* __BOARDS_ARM_STM32F7_COMMON_INCLUDE_STM32_SPITEST_H */ +#endif /* __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_SPITEST_H */ diff --git a/boards/arm/common/stm32/include/stm32_ssd1306.h b/boards/arm/common/stm32/include/stm32_ssd1306.h new file mode 100644 index 0000000000000..a23b2d776ad28 --- /dev/null +++ b/boards/arm/common/stm32/include/stm32_ssd1306.h @@ -0,0 +1,82 @@ +/**************************************************************************** + * boards/arm/common/stm32/include/stm32_ssd1306.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_SSD1306_H +#define __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_SSD1306_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: board_ssd1306_initialize + * + * Description: + * Initialize and register the device + * + * Input Parameters: + * busno - The I2C or SPI bus number + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +int board_ssd1306_initialize(int busno); + +/**************************************************************************** + * Name: board_ssd1306_getdev + * + * Description: + * Get the SSD1306 device driver instance + * + * Returned Value: + * Pointer to the instance + * + ****************************************************************************/ + +struct lcd_dev_s *board_ssd1306_getdev(void); + +#undef EXTERN +#ifdef __cplusplus +} +#endif + +#endif /* __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_SSD1306_H */ diff --git a/boards/arm/stm32/common/include/stm32_tone.h b/boards/arm/common/stm32/include/stm32_tone.h similarity index 92% rename from boards/arm/stm32/common/include/stm32_tone.h rename to boards/arm/common/stm32/include/stm32_tone.h index 1834af76bab05..5306c10f30869 100644 --- a/boards/arm/stm32/common/include/stm32_tone.h +++ b/boards/arm/common/stm32/include/stm32_tone.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/include/stm32_tone.h + * boards/arm/common/stm32/include/stm32_tone.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_TONE_H -#define __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_TONE_H +#ifndef __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_TONE_H +#define __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_TONE_H /**************************************************************************** * Included Files @@ -75,4 +75,4 @@ int board_tone_initialize(int devno); } #endif -#endif /* __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_TONE_H */ +#endif /* __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_TONE_H */ diff --git a/boards/arm/stm32/common/include/stm32_veml6070.h b/boards/arm/common/stm32/include/stm32_veml6070.h similarity index 92% rename from boards/arm/stm32/common/include/stm32_veml6070.h rename to boards/arm/common/stm32/include/stm32_veml6070.h index 3b3a68999718f..ab73c1504ddf8 100644 --- a/boards/arm/stm32/common/include/stm32_veml6070.h +++ b/boards/arm/common/stm32/include/stm32_veml6070.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/include/stm32_veml6070.h + * boards/arm/common/stm32/include/stm32_veml6070.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_VEML6070_H -#define __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_VEML6070_H +#ifndef __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_VEML6070_H +#define __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_VEML6070_H /**************************************************************************** * Included Files @@ -84,4 +84,4 @@ int board_veml6070_initialize(int devno, int busno); } #endif -#endif /* __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_VEML6070_H */ +#endif /* __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_VEML6070_H */ diff --git a/boards/arm/stm32/common/include/stm32_ws2812.h b/boards/arm/common/stm32/include/stm32_ws2812.h similarity index 92% rename from boards/arm/stm32/common/include/stm32_ws2812.h rename to boards/arm/common/stm32/include/stm32_ws2812.h index ef6dfb8d8ab1a..76fa9b5724b6c 100644 --- a/boards/arm/stm32/common/include/stm32_ws2812.h +++ b/boards/arm/common/stm32/include/stm32_ws2812.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/include/stm32_ws2812.h + * boards/arm/common/stm32/include/stm32_ws2812.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_WS2812_H -#define __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_WS2812_H +#ifndef __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_WS2812_H +#define __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_WS2812_H /**************************************************************************** * Included Files @@ -84,4 +84,4 @@ int board_ws2812_initialize(int devno, int spino, uint16_t nleds); } #endif -#endif /* __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_WS2812_H */ +#endif /* __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_WS2812_H */ diff --git a/boards/arm/stm32/common/include/stm32_xen1210.h b/boards/arm/common/stm32/include/stm32_xen1210.h similarity index 92% rename from boards/arm/stm32/common/include/stm32_xen1210.h rename to boards/arm/common/stm32/include/stm32_xen1210.h index 19ed0c4246eab..a6b8e30955de7 100644 --- a/boards/arm/stm32/common/include/stm32_xen1210.h +++ b/boards/arm/common/stm32/include/stm32_xen1210.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/include/stm32_xen1210.h + * boards/arm/common/stm32/include/stm32_xen1210.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_XEN1210_H -#define __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_XEN1210_H +#ifndef __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_XEN1210_H +#define __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_XEN1210_H /**************************************************************************** * Included Files @@ -80,4 +80,4 @@ int board_xen1210_initialize(int devno, int busno); } #endif -#endif /* __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_XEN1210_H */ +#endif /* __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_XEN1210_H */ diff --git a/boards/arm/stm32/common/include/stm32_zerocross.h b/boards/arm/common/stm32/include/stm32_zerocross.h similarity index 91% rename from boards/arm/stm32/common/include/stm32_zerocross.h rename to boards/arm/common/stm32/include/stm32_zerocross.h index ae07c6ddb5e76..2d92fd900be90 100644 --- a/boards/arm/stm32/common/include/stm32_zerocross.h +++ b/boards/arm/common/stm32/include/stm32_zerocross.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/include/stm32_zerocross.h + * boards/arm/common/stm32/include/stm32_zerocross.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_ZEROCROSS_H -#define __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_ZEROCROSS_H +#ifndef __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_ZEROCROSS_H +#define __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_ZEROCROSS_H /**************************************************************************** * Included Files @@ -72,4 +72,4 @@ int board_zerocross_initialize(int devno); } #endif -#endif /* __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_ZEROCROSS_H */ +#endif /* __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_ZEROCROSS_H */ diff --git a/boards/arm/common/stm32/src/CMakeLists.txt b/boards/arm/common/stm32/src/CMakeLists.txt new file mode 100644 index 0000000000000..7f55789437062 --- /dev/null +++ b/boards/arm/common/stm32/src/CMakeLists.txt @@ -0,0 +1,212 @@ +# ############################################################################## +# boards/arm/common/stm32/src/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(SRCS) + +if(CONFIG_SENSORS_BMP180) + list(APPEND SRCS stm32_bmp180.c) +endif() + +if(CONFIG_SENSORS_BMP280) + list(APPEND SRCS stm32_bmp280.c) +endif() + +if(CONFIG_LEDS_APA102) + list(APPEND SRCS stm32_apa102.c) +endif() + +if(CONFIG_WS2812) + list(APPEND SRCS stm32_ws2812.c) +endif() + +if(CONFIG_SENSORS_MAX6675) + list(APPEND SRCS stm32_max6675.c) +endif() + +if(CONFIG_SENSORS_VEML6070) + list(APPEND SRCS stm32_veml6070.c) +endif() + +if(CONFIG_INPUT_NUNCHUCK) + list(APPEND SRCS stm32_nunchuck.c) +endif() + +if(CONFIG_AUDIO_TONE) + list(APPEND SRCS stm32_tone.c) +endif() + +if(CONFIG_LCD_BACKPACK) + list(APPEND SRCS stm32_lcd_backpack.c) +endif() + +if(CONFIG_LCD_SSD1306) + list(APPEND SRCS stm32_ssd1306.c) +endif() + +if(CONFIG_RTC_DS1307) + list(APPEND SRCS stm32_ds1307.c) +endif() + +if(CONFIG_SENSORS_LM75) + list(APPEND SRCS stm32_lm75.c) +endif() + +if(CONFIG_WL_NRF24L01) + list(APPEND SRCS stm32_nrf24l01.c) +endif() + +if(CONFIG_SENSORS_HCSR04) + list(APPEND SRCS stm32_hcsr04.c) +endif() + +if(CONFIG_SENSORS_APDS9960) + list(APPEND SRCS stm32_apds9960.c) +endif() + +if(CONFIG_SENSORS_MT6816) + list(APPEND SRCS stm32_mt6816.c) +endif() + +if(CONFIG_SENSORS_ZEROCROSS) + list(APPEND SRCS stm32_zerocross.c) +endif() + +if(CONFIG_SENSORS_QENCODER) + if(CONFIG_STM32_QE) + list(APPEND SRCS board_qencoder.c) + endif() +endif() + +if(CONFIG_PWM AND NOT EXISTS ${NUTTX_BOARD_DIR}/src/stm32_pwm.c) + list(APPEND SRCS board_pwm.c) +endif() + +if(CONFIG_SENSORS_INA219) + list(APPEND SRCS stm32_ina219.c) +endif() + +if(CONFIG_SENSORS_L3GD20) + list(APPEND SRCS stm32_l3gd20.c) +endif() + +if(CONFIG_SENSORS_MPL115A) + list(APPEND SRCS stm32_mpl115a.c) +endif() + +if(CONFIG_SENSORS_DHTXX) + list(APPEND SRCS stm32_dhtxx.c) +endif() + +if(CONFIG_SENSORS_XEN1210) + list(APPEND SRCS stm32_xen1210.c) +endif() + +if(CONFIG_SENSORS_BH1750FVI) + list(APPEND SRCS stm32_bh1750.c) +endif() + +if(CONFIG_SENSORS_MLX90614) + list(APPEND SRCS stm32_mlx90614.c) +endif() + +if(CONFIG_SENSORS_MAX31855) + list(APPEND SRCS stm32_max31855.c) +endif() + +if(CONFIG_LCD_MAX7219) + list(APPEND SRCS stm32_max7219_matrix.c) +endif() + +if(CONFIG_CL_MFRC522) + list(APPEND SRCS stm32_mfrc522.c) +endif() + +if(CONFIG_SENSORS_AMG88XX) + list(APPEND SRCS stm32_amg88xx.c) +endif() + +if(CONFIG_LIS3DSH) + list(APPEND SRCS stm32_lis3dsh.c) +endif() + +if(CONFIG_BOARD_STM32_IHM07M1) + list(APPEND SRCS stm32_ihm07m1.c) +endif() + +if(CONFIG_BOARD_STM32_IHM08M1) + list(APPEND SRCS stm32_ihm08m1.c) +endif() + +if(CONFIG_BOARD_STM32_IHM16M1) + list(APPEND SRCS stm32_ihm16m1.c) +endif() + +if(CONFIG_STEPPER_DRV8825) + list(APPEND SRCS stm32_drv8825.c) +endif() + +if(CONFIG_INPUT_SBUTTON) + list(APPEND SRCS stm32_sbutton.c) +endif() + +if(CONFIG_INPUT_KMATRIX) + list(APPEND SRCS stm32_kmatrix_gpio.c) +endif() + +if(CONFIG_INPUT_KMATRIX_I2C) + list(APPEND SRCS stm32_kmatrix_i2c.c) +endif() + +if(CONFIG_INPUT_MPR121_KEYPAD) + list(APPEND SRCS stm32_mpr121.c) +endif() + +if(CONFIG_SENSORS_BMI270_I2C) + list(APPEND SRCS stm32_bmi270.c) +endif() + +if(CONFIG_AUDIO_CS4344) + list(APPEND SRCS stm32_cs4344.c) +endif() + +if(CONFIG_STM32_CAN) + if(CONFIG_STM32_CAN_CHARDRIVER) + list(APPEND SRCS stm32_can_setup.c) + endif() + if(CONFIG_STM32_CAN_SOCKET) + list(APPEND SRCS stm32_cansock_setup.c) + endif() +endif() + +if(CONFIG_BOARDCTL_RESET) + list(APPEND SRCS stm32_reset.c) +endif() + +if(CONFIG_STM32_ROMFS) + list(APPEND SRCS stm32_romfs_initialize.c) +endif() + +if(CONFIG_STM32_SPI_TEST) + list(APPEND SRCS stm32_spitest.c) +endif() + +target_sources(board PRIVATE ${SRCS}) diff --git a/boards/arm/common/stm32/src/Make.defs b/boards/arm/common/stm32/src/Make.defs new file mode 100644 index 0000000000000..95482c114898f --- /dev/null +++ b/boards/arm/common/stm32/src/Make.defs @@ -0,0 +1,229 @@ +############################################################################# +# boards/arm/common/stm32/src/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################# + +ifeq ($(CONFIG_ARCH_BOARD_COMMON),y) + +STM32_BOARD_COMMON_DIR := $(TOPDIR)$(DELIM)boards$(DELIM)arm$(DELIM)common$(DELIM)stm32 + +ifeq ($(CONFIG_SENSORS_BMP180),y) + CSRCS += stm32_bmp180.c +endif + +ifeq ($(CONFIG_SENSORS_BMP280),y) + CSRCS += stm32_bmp280.c +endif + +ifeq ($(CONFIG_SENSORS_MS56XX),y) + CSRCS += stm32_ms5611.c +endif + +ifeq ($(CONFIG_LEDS_APA102),y) + CSRCS += stm32_apa102.c +endif + +ifeq ($(CONFIG_WS2812),y) + CSRCS += stm32_ws2812.c +endif + +ifeq ($(CONFIG_SENSORS_MAX6675),y) + CSRCS += stm32_max6675.c +endif + +ifeq ($(CONFIG_SENSORS_VEML6070),y) + CSRCS += stm32_veml6070.c +endif + +ifeq ($(CONFIG_INPUT_NUNCHUCK),y) +CSRCS += stm32_nunchuck.c +endif + +ifeq ($(CONFIG_AUDIO_TONE),y) + CSRCS += stm32_tone.c +endif + +ifeq ($(CONFIG_LCD_BACKPACK),y) + CSRCS += stm32_lcd_backpack.c +endif + +ifeq ($(CONFIG_LCD_SSD1306),y) + CSRCS += stm32_ssd1306.c +endif + +ifeq ($(CONFIG_RTC_DS1307),y) + CSRCS += stm32_ds1307.c +endif + +ifeq ($(CONFIG_SENSORS_LM75),y) + CSRCS += stm32_lm75.c +endif + +ifeq ($(CONFIG_WL_NRF24L01),y) + CSRCS += stm32_nrf24l01.c +endif + +ifeq ($(CONFIG_SENSORS_HCSR04),y) + CSRCS += stm32_hcsr04.c +endif + +ifeq ($(CONFIG_SENSORS_APDS9960),y) + CSRCS += stm32_apds9960.c +endif + +ifeq ($(CONFIG_SENSORS_MT6816),y) + CSRCS += stm32_mt6816.c +endif + +ifeq ($(CONFIG_INPUT_MPR121_KEYPAD),y) + CSRCS += stm32_mpr121.c +endif + +ifeq ($(CONFIG_SENSORS_ZEROCROSS),y) + CSRCS += stm32_zerocross.c +endif + +ifeq ($(CONFIG_SENSORS_QENCODER),y) + ifeq ($(CONFIG_STM32_QE),y) + CSRCS += board_qencoder.c + endif +endif + +ifeq ($(CONFIG_PWM),y) + ifeq (,$(wildcard $(BOARD_DIR)$(DELIM)src$(DELIM)stm32_pwm.c)) + CSRCS += board_pwm.c + endif +endif + +ifeq ($(CONFIG_SENSORS_HALL3PHASE),y) + CSRCS += board_hall3ph.c +endif + +ifeq ($(CONFIG_SENSORS_INA219),y) + CSRCS += stm32_ina219.c +endif + +ifeq ($(CONFIG_SENSORS_L3GD20),y) + CSRCS += stm32_l3gd20.c +endif + +ifeq ($(CONFIG_SENSORS_MPL115A),y) + CSRCS += stm32_mpl115a.c +endif + +ifeq ($(CONFIG_SENSORS_DHTXX),y) + CSRCS += stm32_dhtxx.c +endif + +ifeq ($(CONFIG_SENSORS_XEN1210),y) + CSRCS += stm32_xen1210.c +endif + +ifeq ($(CONFIG_SENSORS_BH1750FVI),y) + CSRCS += stm32_bh1750.c +endif + +ifeq ($(CONFIG_SENSORS_MLX90614),y) + CSRCS += stm32_mlx90614.c +endif + +ifeq ($(CONFIG_SENSORS_MAX31855),y) + CSRCS += stm32_max31855.c +endif + +ifeq ($(CONFIG_LCD_MAX7219),y) + CSRCS += stm32_max7219_matrix.c +endif + +ifeq ($(CONFIG_CL_MFRC522),y) + CSRCS += stm32_mfrc522.c +endif + +ifeq ($(CONFIG_SENSORS_AMG88XX),y) + CSRCS+= stm32_amg88xx.c +endif + +ifeq ($(CONFIG_LIS3DSH),y) + CSRCS += stm32_lis3dsh.c +endif + +ifeq ($(CONFIG_BOARD_STM32_IHM07M1),y) + CSRCS += stm32_ihm07m1.c +endif + +ifeq ($(CONFIG_BOARD_STM32_IHM08M1),y) + CSRCS += stm32_ihm08m1.c +endif + +ifeq ($(CONFIG_BOARD_STM32_IHM16M1),y) + CSRCS += stm32_ihm16m1.c +endif + +ifeq ($(CONFIG_STEPPER_DRV8825),y) + CSRCS += stm32_drv8825.c +endif + +ifeq ($(CONFIG_INPUT_SBUTTON),y) + CSRCS += stm32_sbutton.c +endif + +ifeq ($(CONFIG_INPUT_KMATRIX),y) + CSRCS += stm32_kmatrix_gpio.c +endif + +ifeq ($(CONFIG_INPUT_KMATRIX_I2C),y) + CSRCS += stm32_kmatrix_i2c.c +endif + +ifeq ($(CONFIG_SENSORS_BMI270_I2C),y) + CSRCS += stm32_bmi270.c +endif + +ifeq ($(CONFIG_AUDIO_CS4344),y) + CSRCS += stm32_cs4344.c +endif + +ifeq ($(CONFIG_STM32_CAN),y) + ifeq ($(CONFIG_STM32_CAN_CHARDRIVER),y) + CSRCS += stm32_can_setup.c + endif + ifeq ($(CONFIG_STM32_CAN_SOCKET),y) + CSRCS += stm32_cansock_setup.c + endif +endif + +ifeq ($(CONFIG_BOARDCTL_RESET),y) + CSRCS += stm32_reset.c +endif + +ifeq ($(CONFIG_STM32_ROMFS),y) + CSRCS += stm32_romfs_initialize.c +endif + +ifeq ($(CONFIG_STM32_SPI_TEST),y) + CSRCS += stm32_spitest.c +endif + +DEPPATH += --dep-path $(STM32_BOARD_COMMON_DIR)$(DELIM)src +VPATH += :$(STM32_BOARD_COMMON_DIR)$(DELIM)src +CFLAGS += ${INCDIR_PREFIX}$(STM32_BOARD_COMMON_DIR)$(DELIM)include +CFLAGS += ${INCDIR_PREFIX}$(STM32_BOARD_COMMON_DIR)$(DELIM)src + +endif diff --git a/boards/arm/stm32/common/src/board_hall3ph.c b/boards/arm/common/stm32/src/board_hall3ph.c similarity index 98% rename from boards/arm/stm32/common/src/board_hall3ph.c rename to boards/arm/common/stm32/src/board_hall3ph.c index f96d5a953f3f1..3ce8efa7607cd 100644 --- a/boards/arm/stm32/common/src/board_hall3ph.c +++ b/boards/arm/common/stm32/src/board_hall3ph.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/src/board_hall3ph.c + * boards/arm/common/stm32/src/board_hall3ph.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/common/src/board_pwm.c b/boards/arm/common/stm32/src/board_pwm.c similarity index 93% rename from boards/arm/stm32f0l0g0/common/src/board_pwm.c rename to boards/arm/common/stm32/src/board_pwm.c index 793b0398537d8..fdc3ad58f4250 100644 --- a/boards/arm/stm32f0l0g0/common/src/board_pwm.c +++ b/boards/arm/common/stm32/src/board_pwm.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/common/src/board_pwm.c + * boards/arm/common/stm32/src/board_pwm.c * * SPDX-License-Identifier: Apache-2.0 * @@ -55,7 +55,7 @@ int stm32_pwm_setup(void) if (!initialized) { -#ifdef CONFIG_STM32F0L0G0_TIM1_PWM +#ifdef CONFIG_STM32_TIM1_PWM pwm = stm32_pwminitialize(1); if (pwm == NULL) { @@ -71,7 +71,7 @@ int stm32_pwm_setup(void) } #endif -#ifdef CONFIG_STM32F0L0G0_TIM2_PWM +#ifdef CONFIG_STM32_TIM2_PWM pwm = stm32_pwminitialize(2); if (pwm == NULL) { @@ -87,7 +87,7 @@ int stm32_pwm_setup(void) } #endif -#ifdef CONFIG_STM32F0L0G0_TIM3_PWM +#ifdef CONFIG_STM32_TIM3_PWM pwm = stm32_pwminitialize(3); if (pwm == NULL) { @@ -103,7 +103,7 @@ int stm32_pwm_setup(void) } #endif -#ifdef CONFIG_STM32F0L0G0_TIM14_PWM +#ifdef CONFIG_STM32_TIM14_PWM pwm = stm32_pwminitialize(14); if (pwm == NULL) { @@ -119,7 +119,7 @@ int stm32_pwm_setup(void) } #endif -#ifdef CONFIG_STM32F0L0G0_TIM15_PWM +#ifdef CONFIG_STM32_TIM15_PWM pwm = stm32_pwminitialize(15); if (pwm == NULL) { @@ -135,7 +135,7 @@ int stm32_pwm_setup(void) } #endif -#ifdef CONFIG_STM32F0L0G0_TIM16_PWM +#ifdef CONFIG_STM32_TIM16_PWM pwm = stm32_pwminitialize(16); if (pwm == NULL) { @@ -151,7 +151,7 @@ int stm32_pwm_setup(void) } #endif -#ifdef CONFIG_STM32F0L0G0_TIM17_PWM +#ifdef CONFIG_STM32_TIM17_PWM pwm = stm32_pwminitialize(17); if (pwm == NULL) { diff --git a/boards/arm/stm32f0l0g0/common/src/board_qencoder.c b/boards/arm/common/stm32/src/board_qencoder.c similarity index 96% rename from boards/arm/stm32f0l0g0/common/src/board_qencoder.c rename to boards/arm/common/stm32/src/board_qencoder.c index 6f7e6260977a4..f67c7d857f44a 100644 --- a/boards/arm/stm32f0l0g0/common/src/board_qencoder.c +++ b/boards/arm/common/stm32/src/board_qencoder.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/common/src/board_qencoder.c + * boards/arm/common/stm32/src/board_qencoder.c * * SPDX-License-Identifier: Apache-2.0 * @@ -27,7 +27,7 @@ #include #include -#include +#include #include #include diff --git a/boards/arm/stm32/common/src/stm32_amg88xx.c b/boards/arm/common/stm32/src/stm32_amg88xx.c similarity index 98% rename from boards/arm/stm32/common/src/stm32_amg88xx.c rename to boards/arm/common/stm32/src/stm32_amg88xx.c index 4760fd947f17f..995a28e141253 100644 --- a/boards/arm/stm32/common/src/stm32_amg88xx.c +++ b/boards/arm/common/stm32/src/stm32_amg88xx.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/src/stm32_amg88xx.c + * boards/arm/common/stm32/src/stm32_amg88xx.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/common/stm32/src/stm32_apa102.c b/boards/arm/common/stm32/src/stm32_apa102.c new file mode 100644 index 0000000000000..5de33d0dc6bfc --- /dev/null +++ b/boards/arm/common/stm32/src/stm32_apa102.c @@ -0,0 +1,110 @@ +/**************************************************************************** + * boards/arm/common/stm32/src/stm32_apa102.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "stm32.h" +#include "stm32_spi.h" + +#ifdef CONFIG_LEDS_APA102 + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_apa102_initialize + * + * Description: + * Initialize and register the APA102 LED Strip driver. + * + * Input Parameters: + * devno - The device number, used to build the device path as /dev/leddrvN + * spino - SPI port number + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +int board_apa102_initialize(int devno, int spino) +{ + struct spi_dev_s *spi; + char devpath[13]; + int ret; + + spi = stm32_spibus_initialize(spino); + if (spi == NULL) + { + return -ENODEV; + } + + /* Register the APA102 Driver at the specified location. */ + + snprintf(devpath, sizeof(devpath), "/dev/leddrv%d", devno); + ret = apa102_register(devpath, spi); + if (ret < 0) + { + lederr("ERROR: apa102_register(%s) failed: %d\n", + devpath, ret); + return ret; + } + + return OK; +} + +#endif diff --git a/boards/arm/stm32/common/src/stm32_apds9960.c b/boards/arm/common/stm32/src/stm32_apds9960.c similarity index 99% rename from boards/arm/stm32/common/src/stm32_apds9960.c rename to boards/arm/common/stm32/src/stm32_apds9960.c index 902cac423d5ca..ff709d6949777 100644 --- a/boards/arm/stm32/common/src/stm32_apds9960.c +++ b/boards/arm/common/stm32/src/stm32_apds9960.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/src/stm32_apds9960.c + * boards/arm/common/stm32/src/stm32_apds9960.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/common/stm32/src/stm32_bh1750.c b/boards/arm/common/stm32/src/stm32_bh1750.c new file mode 100644 index 0000000000000..d8f742f357b48 --- /dev/null +++ b/boards/arm/common/stm32/src/stm32_bh1750.c @@ -0,0 +1,90 @@ +/**************************************************************************** + * boards/arm/common/stm32/src/stm32_bh1750.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include +#include + +#include "stm32.h" +#include "stm32_i2c.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_bh1750initialize + * + * Description: + * Initialize and register the BH1750FVI Ambient Light driver. + * + * Input Parameters: + * devno - The device number, used to build the device path as /dev/lightN + * busno - The I2C bus number + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +int board_bh1750_initialize(int devno, int busno) +{ + struct i2c_master_s *i2c; + char devpath[12]; + int ret; + + sninfo("Initializing BH1750FVI!\n"); + + /* Initialize I2C */ + + i2c = stm32_i2cbus_initialize(busno); + if (!i2c) + { + return -ENODEV; + } + + /* Then register the ambient light sensor */ + + snprintf(devpath, sizeof(devpath), "/dev/light%d", devno); + ret = bh1750fvi_register(devpath, i2c, BH1750FVI_I2C_ADDR); + if (ret < 0) + { + snerr("ERROR: Error registering BH1750FVI\n"); + } + + return ret; +} + diff --git a/boards/arm/stm32f7/common/src/stm32_bmi270.c b/boards/arm/common/stm32/src/stm32_bmi270.c similarity index 98% rename from boards/arm/stm32f7/common/src/stm32_bmi270.c rename to boards/arm/common/stm32/src/stm32_bmi270.c index 8ebe848cb39c1..8c0ac8fcdc03d 100644 --- a/boards/arm/stm32f7/common/src/stm32_bmi270.c +++ b/boards/arm/common/stm32/src/stm32_bmi270.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f7/common/src/stm32_bmi270.c + * boards/arm/common/stm32/src/stm32_bmi270.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/common/src/stm32_bmp180.c b/boards/arm/common/stm32/src/stm32_bmp180.c similarity index 98% rename from boards/arm/stm32/common/src/stm32_bmp180.c rename to boards/arm/common/stm32/src/stm32_bmp180.c index 35b6bf15a32c7..3301d4baf1bee 100644 --- a/boards/arm/stm32/common/src/stm32_bmp180.c +++ b/boards/arm/common/stm32/src/stm32_bmp180.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/src/stm32_bmp180.c + * boards/arm/common/stm32/src/stm32_bmp180.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/common/src/stm32_bmp280.c b/boards/arm/common/stm32/src/stm32_bmp280.c similarity index 98% rename from boards/arm/stm32/common/src/stm32_bmp280.c rename to boards/arm/common/stm32/src/stm32_bmp280.c index c42be6b3ec8cc..2d748ac1128de 100644 --- a/boards/arm/stm32/common/src/stm32_bmp280.c +++ b/boards/arm/common/stm32/src/stm32_bmp280.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/src/stm32_bmp280.c + * boards/arm/common/stm32/src/stm32_bmp280.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f7/common/src/stm32_can_setup.c b/boards/arm/common/stm32/src/stm32_can_setup.c similarity index 95% rename from boards/arm/stm32f7/common/src/stm32_can_setup.c rename to boards/arm/common/stm32/src/stm32_can_setup.c index 5f62d6da00f17..bad1ffbc2d6fd 100644 --- a/boards/arm/stm32f7/common/src/stm32_can_setup.c +++ b/boards/arm/common/stm32/src/stm32_can_setup.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f7/common/src/stm32_can_setup.c + * boards/arm/common/stm32/src/stm32_can_setup.c * * SPDX-License-Identifier: Apache-2.0 * @@ -40,7 +40,7 @@ * Pre-processor Definitions ****************************************************************************/ -#ifdef CONFIG_STM32F7_CAN1 +#ifdef CONFIG_STM32_CAN1 # define CAN_PORT 1 #else # define CAN_PORT 2 @@ -60,7 +60,7 @@ int stm32_can_setup(void) { -#if defined(CONFIG_STM32F7_CAN1) +#if defined(CONFIG_STM32_CAN1) struct can_dev_s *can; int ret; @@ -85,7 +85,7 @@ int stm32_can_setup(void) return OK; #endif -#if defined(CONFIG_STM32F7_CAN2) +#if defined(CONFIG_STM32_CAN2) struct can_dev_s *can; int ret; diff --git a/boards/arm/stm32f7/common/src/stm32_cansock_setup.c b/boards/arm/common/stm32/src/stm32_cansock_setup.c similarity index 93% rename from boards/arm/stm32f7/common/src/stm32_cansock_setup.c rename to boards/arm/common/stm32/src/stm32_cansock_setup.c index 2bb60d2b8bc21..aad7a7df26de5 100644 --- a/boards/arm/stm32f7/common/src/stm32_cansock_setup.c +++ b/boards/arm/common/stm32/src/stm32_cansock_setup.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f7/common/src/stm32_cansock_setup.c + * boards/arm/common/stm32/src/stm32_cansock_setup.c * * SPDX-License-Identifier: Apache-2.0 * @@ -36,7 +36,7 @@ /* Configuration ************************************************************/ -#if !defined(CONFIG_STM32F7_CAN1) && !defined(CONFIG_STM32F7_CAN2) +#if !defined(CONFIG_STM32_CAN1) && !defined(CONFIG_STM32_CAN2) # error "No CAN is enable. Please enable at least one CAN device" #endif @@ -58,7 +58,7 @@ int stm32_cansock_setup(void) UNUSED(ret); -#ifdef CONFIG_STM32F7_CAN1 +#ifdef CONFIG_STM32_CAN1 /* Call stm32_caninitialize() to get an instance of the CAN interface */ ret = stm32_cansockinitialize(1); @@ -69,7 +69,7 @@ int stm32_cansock_setup(void) } #endif -#ifdef CONFIG_STM32F7_CAN2 +#ifdef CONFIG_STM32_CAN2 /* Call stm32_caninitialize() to get an instance of the CAN interface */ ret = stm32_cansockinitialize(2); diff --git a/boards/arm/common/stm32/src/stm32_cs4344.c b/boards/arm/common/stm32/src/stm32_cs4344.c new file mode 100644 index 0000000000000..64f8ee946a881 --- /dev/null +++ b/boards/arm/common/stm32/src/stm32_cs4344.c @@ -0,0 +1,170 @@ +/**************************************************************************** + * boards/arm/common/stm32/src/stm32_cs4344.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include + +#include "stm32_i2s.h" +#include "stm32_pwr.h" +#include "stm32_rcc.h" + +/**************************************************************************** + * Pre-Processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_cs4344_initialize + * + * Description: + * This function is called by platform-specific, setup logic to configure + * and register the CS4344 device. This function will register the driver + * as /dev/audio/pcm[x] where x is determined by the minor device number. + * + * Input Parameters: + * minor - The input device minor number + * + * Returned Value: + * Zero is returned on success. Otherwise, a negated errno value is + * returned to indicate the nature of the failure. + * + ****************************************************************************/ + +int board_cs4344_initialize(int devno, int port) +{ + struct audio_lowerhalf_s *cs4344; + struct audio_lowerhalf_s *pcm; + struct i2s_dev_s *i2s; + static bool initialized = false; + char devname[12]; + int ret; + + audinfo("minor %d\n", devno); + DEBUGASSERT(devno >= 0 && devno <= 25); + + /* Have we already initialized? Since we never uninitialize we must + * prevent multiple initializations. This is necessary, for example, + * when the touchscreen example is used as a built-in application in + * NSH and can be called numerous time. It will attempt to initialize + * each time. + */ + + if (!initialized) + { + /* Get an instance of the I2S interface for the CS4344 data channel */ + + i2s = stm32_i2sbus_initialize(port); + if (!i2s) + { + auderr("ERROR: Failed to initialize I2S%d\n", port); + ret = -ENODEV; + goto errout; + } + + /* Now we can use this I2S interface to initialize the CS4344 which + * will return an audio interface. + */ + + cs4344 = cs4344_initialize(i2s); + if (!cs4344) + { + auderr("ERROR: Failed to initialize the CS4344\n"); + ret = -ENODEV; + goto errout; + } + + /* No we can embed the CS4344/I2S conglomerate into a PCM decoder + * instance so that we will have a PCM front end for the CS4344 + * driver. + */ + + pcm = pcm_decode_initialize(cs4344); + if (!pcm) + { + auderr("ERROR: Failed create the PCM decoder\n"); + ret = -ENODEV; + goto errout; + } + + /* Create a device name */ + + snprintf(devname, sizeof(devname), "pcm%d", devno); + + /* Finally, we can register the PCM/CS4344/I2S audio device. + * + * Is anyone young enough to remember Rube Goldberg? + */ + + ret = audio_register(devname, pcm); + if (ret < 0) + { + auderr("ERROR: Failed to register /dev/%s device: %d\n", + devname, ret); + goto errout; + } + + /* Now we are initialized */ + + initialized = true; + } + + return OK; + +errout: + return ret; +} + diff --git a/boards/arm/stm32/common/src/stm32_dhtxx.c b/boards/arm/common/stm32/src/stm32_dhtxx.c similarity index 99% rename from boards/arm/stm32/common/src/stm32_dhtxx.c rename to boards/arm/common/stm32/src/stm32_dhtxx.c index 017f7de8f1456..24c82362750ec 100644 --- a/boards/arm/stm32/common/src/stm32_dhtxx.c +++ b/boards/arm/common/stm32/src/stm32_dhtxx.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/src/stm32_dhtxx.c + * boards/arm/common/stm32/src/stm32_dhtxx.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/common/src/stm32_drv8825.c b/boards/arm/common/stm32/src/stm32_drv8825.c similarity index 99% rename from boards/arm/stm32/common/src/stm32_drv8825.c rename to boards/arm/common/stm32/src/stm32_drv8825.c index e11b644d947df..60187a9eb9fe0 100644 --- a/boards/arm/stm32/common/src/stm32_drv8825.c +++ b/boards/arm/common/stm32/src/stm32_drv8825.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/src/stm32_drv8825.c + * boards/arm/common/stm32/src/stm32_drv8825.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/common/src/stm32_ds1307.c b/boards/arm/common/stm32/src/stm32_ds1307.c similarity index 98% rename from boards/arm/stm32/common/src/stm32_ds1307.c rename to boards/arm/common/stm32/src/stm32_ds1307.c index 6d34e5255ca54..fb7cf4129b295 100644 --- a/boards/arm/stm32/common/src/stm32_ds1307.c +++ b/boards/arm/common/stm32/src/stm32_ds1307.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/src/stm32_ds1307.c + * boards/arm/common/stm32/src/stm32_ds1307.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/common/src/stm32_hcsr04.c b/boards/arm/common/stm32/src/stm32_hcsr04.c similarity index 99% rename from boards/arm/stm32/common/src/stm32_hcsr04.c rename to boards/arm/common/stm32/src/stm32_hcsr04.c index 7f8c235f0de6f..3f2d6ae229bbf 100644 --- a/boards/arm/stm32/common/src/stm32_hcsr04.c +++ b/boards/arm/common/stm32/src/stm32_hcsr04.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/src/stm32_hcsr04.c + * boards/arm/common/stm32/src/stm32_hcsr04.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/common/src/stm32_ihm07m1.c b/boards/arm/common/stm32/src/stm32_ihm07m1.c similarity index 99% rename from boards/arm/stm32/common/src/stm32_ihm07m1.c rename to boards/arm/common/stm32/src/stm32_ihm07m1.c index 39e550affaa41..6fa02180e4183 100644 --- a/boards/arm/stm32/common/src/stm32_ihm07m1.c +++ b/boards/arm/common/stm32/src/stm32_ihm07m1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/src/stm32_ihm07m1.c + * boards/arm/common/stm32/src/stm32_ihm07m1.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/common/src/stm32_ihm08m1.c b/boards/arm/common/stm32/src/stm32_ihm08m1.c similarity index 99% rename from boards/arm/stm32/common/src/stm32_ihm08m1.c rename to boards/arm/common/stm32/src/stm32_ihm08m1.c index 97a12482b59a1..2c5b1b366a84b 100644 --- a/boards/arm/stm32/common/src/stm32_ihm08m1.c +++ b/boards/arm/common/stm32/src/stm32_ihm08m1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/src/stm32_ihm08m1.c + * boards/arm/common/stm32/src/stm32_ihm08m1.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/common/src/stm32_ihm16m1.c b/boards/arm/common/stm32/src/stm32_ihm16m1.c similarity index 99% rename from boards/arm/stm32/common/src/stm32_ihm16m1.c rename to boards/arm/common/stm32/src/stm32_ihm16m1.c index d3d6ccb838e74..6bf525ca0b7f3 100644 --- a/boards/arm/stm32/common/src/stm32_ihm16m1.c +++ b/boards/arm/common/stm32/src/stm32_ihm16m1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/src/stm32_ihm16m1.c + * boards/arm/common/stm32/src/stm32_ihm16m1.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/common/src/stm32_ina219.c b/boards/arm/common/stm32/src/stm32_ina219.c similarity index 98% rename from boards/arm/stm32/common/src/stm32_ina219.c rename to boards/arm/common/stm32/src/stm32_ina219.c index 98968b1adbc3a..20b1e565dadcc 100644 --- a/boards/arm/stm32/common/src/stm32_ina219.c +++ b/boards/arm/common/stm32/src/stm32_ina219.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/src/stm32_ina219.c + * boards/arm/common/stm32/src/stm32_ina219.c * * SPDX-License-Identifier: BSD-3-Clause * SPDX-FileCopyrightText: 2018 Erle Robotics (Juan Flores Muñoz). diff --git a/boards/arm/stm32/common/src/stm32_kmatrix_gpio.c b/boards/arm/common/stm32/src/stm32_kmatrix_gpio.c similarity index 99% rename from boards/arm/stm32/common/src/stm32_kmatrix_gpio.c rename to boards/arm/common/stm32/src/stm32_kmatrix_gpio.c index d76d94fa0f3e2..7f5a68d0acd03 100644 --- a/boards/arm/stm32/common/src/stm32_kmatrix_gpio.c +++ b/boards/arm/common/stm32/src/stm32_kmatrix_gpio.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/src/stm32_kmatrix_gpio.c + * boards/arm/common/stm32/src/stm32_kmatrix_gpio.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/common/src/stm32_kmatrix_i2c.c b/boards/arm/common/stm32/src/stm32_kmatrix_i2c.c similarity index 99% rename from boards/arm/stm32/common/src/stm32_kmatrix_i2c.c rename to boards/arm/common/stm32/src/stm32_kmatrix_i2c.c index 358c1d5584fe3..d4978eca0a56c 100644 --- a/boards/arm/stm32/common/src/stm32_kmatrix_i2c.c +++ b/boards/arm/common/stm32/src/stm32_kmatrix_i2c.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/src/stm32_kmatrix_i2c.c + * boards/arm/common/stm32/src/stm32_kmatrix_i2c.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/common/src/stm32_l3gd20.c b/boards/arm/common/stm32/src/stm32_l3gd20.c similarity index 98% rename from boards/arm/stm32/common/src/stm32_l3gd20.c rename to boards/arm/common/stm32/src/stm32_l3gd20.c index 5cbd5021d843c..145060bd52de8 100644 --- a/boards/arm/stm32/common/src/stm32_l3gd20.c +++ b/boards/arm/common/stm32/src/stm32_l3gd20.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/src/stm32_l3gd20.c + * boards/arm/common/stm32/src/stm32_l3gd20.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/common/src/stm32_lcd_backpack.c b/boards/arm/common/stm32/src/stm32_lcd_backpack.c similarity index 98% rename from boards/arm/stm32/common/src/stm32_lcd_backpack.c rename to boards/arm/common/stm32/src/stm32_lcd_backpack.c index c288d2b4dd6e4..b65a3fcaaec19 100644 --- a/boards/arm/stm32/common/src/stm32_lcd_backpack.c +++ b/boards/arm/common/stm32/src/stm32_lcd_backpack.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/src/stm32_lcd_backpack.c + * boards/arm/common/stm32/src/stm32_lcd_backpack.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/common/src/stm32_lis3dsh.c b/boards/arm/common/stm32/src/stm32_lis3dsh.c similarity index 98% rename from boards/arm/stm32/common/src/stm32_lis3dsh.c rename to boards/arm/common/stm32/src/stm32_lis3dsh.c index 03d3fa84ad405..f1cfaa31ce388 100644 --- a/boards/arm/stm32/common/src/stm32_lis3dsh.c +++ b/boards/arm/common/stm32/src/stm32_lis3dsh.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/src/stm32_lis3dsh.c + * boards/arm/common/stm32/src/stm32_lis3dsh.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/common/src/stm32_lm75.c b/boards/arm/common/stm32/src/stm32_lm75.c similarity index 98% rename from boards/arm/stm32/common/src/stm32_lm75.c rename to boards/arm/common/stm32/src/stm32_lm75.c index ce7c9f796e65c..6f01942a00a78 100644 --- a/boards/arm/stm32/common/src/stm32_lm75.c +++ b/boards/arm/common/stm32/src/stm32_lm75.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/src/stm32_lm75.c + * boards/arm/common/stm32/src/stm32_lm75.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/common/src/stm32_max31855.c b/boards/arm/common/stm32/src/stm32_max31855.c similarity index 98% rename from boards/arm/stm32/common/src/stm32_max31855.c rename to boards/arm/common/stm32/src/stm32_max31855.c index b520888c5979f..ae21864b0951a 100644 --- a/boards/arm/stm32/common/src/stm32_max31855.c +++ b/boards/arm/common/stm32/src/stm32_max31855.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/src/stm32_max31855.c + * boards/arm/common/stm32/src/stm32_max31855.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/common/src/stm32_max6675.c b/boards/arm/common/stm32/src/stm32_max6675.c similarity index 98% rename from boards/arm/stm32/common/src/stm32_max6675.c rename to boards/arm/common/stm32/src/stm32_max6675.c index bd6b20d0e0f0f..4082eea356a9a 100644 --- a/boards/arm/stm32/common/src/stm32_max6675.c +++ b/boards/arm/common/stm32/src/stm32_max6675.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/src/stm32_max6675.c + * boards/arm/common/stm32/src/stm32_max6675.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/common/src/stm32_max7219_matrix.c b/boards/arm/common/stm32/src/stm32_max7219_matrix.c similarity index 98% rename from boards/arm/stm32/common/src/stm32_max7219_matrix.c rename to boards/arm/common/stm32/src/stm32_max7219_matrix.c index 4e5ac76473b5c..0ee46493a9c4c 100644 --- a/boards/arm/stm32/common/src/stm32_max7219_matrix.c +++ b/boards/arm/common/stm32/src/stm32_max7219_matrix.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/src/stm32_max7219_matrix.c + * boards/arm/common/stm32/src/stm32_max7219_matrix.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/common/stm32/src/stm32_mfrc522.c b/boards/arm/common/stm32/src/stm32_mfrc522.c new file mode 100644 index 0000000000000..0da85237c697b --- /dev/null +++ b/boards/arm/common/stm32/src/stm32_mfrc522.c @@ -0,0 +1,86 @@ +/**************************************************************************** + * boards/arm/common/stm32/src/stm32_mfrc522.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include +#include + +#include "stm32.h" +#include "stm32_spi.h" + +#if defined(CONFIG_SPI) && defined(CONFIG_STM32_SPI1) && defined(CONFIG_CL_MFRC522) + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define MFRC522_SPI_PORTNO 1 /* On SPI1 */ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_mfrc522initialize + * + * Description: + * Initialize and register the MFRC522 RFID driver. + * + * Input Parameters: + * devpath - The full path to the driver to register. E.g., "/dev/rfid0" + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +int stm32_mfrc522initialize(const char *devpath) +{ + struct spi_dev_s *spi; + int ret; + spi = stm32_spibus_initialize(MFRC522_SPI_PORTNO); + if (!spi) + { + return -ENODEV; + } + + /* Then register the MFRC522 */ + + ret = mfrc522_register(devpath, spi); + if (ret < 0) + { + snerr("ERROR: Error registering MFRC522\n"); + } + + return ret; +} + +#endif /* CONFIG_SPI && CONFIG_MFRC522 */ diff --git a/boards/arm/stm32/common/src/stm32_mlx90614.c b/boards/arm/common/stm32/src/stm32_mlx90614.c similarity index 98% rename from boards/arm/stm32/common/src/stm32_mlx90614.c rename to boards/arm/common/stm32/src/stm32_mlx90614.c index 3d6944c30fded..984422d914927 100644 --- a/boards/arm/stm32/common/src/stm32_mlx90614.c +++ b/boards/arm/common/stm32/src/stm32_mlx90614.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/src/stm32_mlx90614.c + * boards/arm/common/stm32/src/stm32_mlx90614.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/common/src/stm32_mpl115a.c b/boards/arm/common/stm32/src/stm32_mpl115a.c similarity index 98% rename from boards/arm/stm32/common/src/stm32_mpl115a.c rename to boards/arm/common/stm32/src/stm32_mpl115a.c index ad467fd5d167e..f246d1716849c 100644 --- a/boards/arm/stm32/common/src/stm32_mpl115a.c +++ b/boards/arm/common/stm32/src/stm32_mpl115a.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/src/stm32_mpl115a.c + * boards/arm/common/stm32/src/stm32_mpl115a.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/common/src/stm32_mpr121.c b/boards/arm/common/stm32/src/stm32_mpr121.c similarity index 99% rename from boards/arm/stm32/common/src/stm32_mpr121.c rename to boards/arm/common/stm32/src/stm32_mpr121.c index bd0d0d5ad5e02..29a5049dfadf6 100644 --- a/boards/arm/stm32/common/src/stm32_mpr121.c +++ b/boards/arm/common/stm32/src/stm32_mpr121.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/src/stm32_mpr121.c + * boards/arm/common/stm32/src/stm32_mpr121.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/common/src/stm32_ms5611.c b/boards/arm/common/stm32/src/stm32_ms5611.c similarity index 98% rename from boards/arm/stm32/common/src/stm32_ms5611.c rename to boards/arm/common/stm32/src/stm32_ms5611.c index 9e230e86afb56..b38b0097608c9 100644 --- a/boards/arm/stm32/common/src/stm32_ms5611.c +++ b/boards/arm/common/stm32/src/stm32_ms5611.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/src/stm32_ms5611.c + * boards/arm/common/stm32/src/stm32_ms5611.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/common/src/stm32_mt6816.c b/boards/arm/common/stm32/src/stm32_mt6816.c similarity index 98% rename from boards/arm/stm32/common/src/stm32_mt6816.c rename to boards/arm/common/stm32/src/stm32_mt6816.c index 834e120385036..41757f28677d2 100644 --- a/boards/arm/stm32/common/src/stm32_mt6816.c +++ b/boards/arm/common/stm32/src/stm32_mt6816.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/src/stm32_mt6816.c + * boards/arm/common/stm32/src/stm32_mt6816.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/common/stm32/src/stm32_nrf24l01.c b/boards/arm/common/stm32/src/stm32_nrf24l01.c new file mode 100644 index 0000000000000..9b086e8c3b3eb --- /dev/null +++ b/boards/arm/common/stm32/src/stm32_nrf24l01.c @@ -0,0 +1,142 @@ +/**************************************************************************** + * boards/arm/common/stm32/src/stm32_nrf24l01.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include "arm_internal.h" +#include "chip.h" +#include "stm32.h" +#include "stm32_nrf24l01.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +static int nrf24l01_irq_attach(xcpt_t isr, void *arg); +static void nrf24l01_chip_enable(bool enable); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static struct nrf24l01_config_s nrf_cfg = +{ + .irqattach = nrf24l01_irq_attach, + .chipenable = nrf24l01_chip_enable, +}; + +static xcpt_t g_isr; +static void *g_arg; + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +static int nrf24l01_irq_attach(xcpt_t isr, void *arg) +{ + wlinfo("Attach IRQ\n"); + g_isr = isr; + g_arg = arg; + stm32_gpiosetevent(BOARD_NRF24L01_GPIO_IRQ, false, true, false, + g_isr, g_arg); + return OK; +} + +static void nrf24l01_chip_enable(bool enable) +{ + wlinfo("CE:%d\n", enable); + stm32_gpiowrite(BOARD_NRF24L01_GPIO_CE, enable); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_nrf24l01_initialize + * + * Description: + * Initialize the NRF24L01 wireless module + * + * Input Parameters: + * busno - The SPI bus number + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +int board_nrf24l01_initialize(int busno) +{ + struct spi_dev_s *spidev; + int result; + + /* Setup CE & IRQ line IOs */ + + stm32_configgpio(BOARD_NRF24L01_GPIO_CE); + stm32_configgpio(BOARD_NRF24L01_GPIO_IRQ); + + /* Init SPI bus */ + + spidev = stm32_spibus_initialize(busno); + if (!spidev) + { + wlerr("ERROR: Failed to initialize SPI bus\n"); + return -ENODEV; + } + + result = nrf24l01_register(spidev, &nrf_cfg); + if (result != OK) + { + wlerr("ERROR: Failed to register initialize SPI bus\n"); + return -ENODEV; + } + + return OK; +} diff --git a/boards/arm/stm32/common/src/stm32_nunchuck.c b/boards/arm/common/stm32/src/stm32_nunchuck.c similarity index 98% rename from boards/arm/stm32/common/src/stm32_nunchuck.c rename to boards/arm/common/stm32/src/stm32_nunchuck.c index e25d7fe770ab4..27b4ba76b7f6a 100644 --- a/boards/arm/stm32/common/src/stm32_nunchuck.c +++ b/boards/arm/common/stm32/src/stm32_nunchuck.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/src/stm32_nunchuck.c + * boards/arm/common/stm32/src/stm32_nunchuck.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/common/stm32/src/stm32_reset.c b/boards/arm/common/stm32/src/stm32_reset.c new file mode 100644 index 0000000000000..ea664e886151f --- /dev/null +++ b/boards/arm/common/stm32/src/stm32_reset.c @@ -0,0 +1,60 @@ +/**************************************************************************** + * boards/arm/common/stm32/src/stm32_reset.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_reset + * + * Description: + * Reset board. Support for this function is required by board-level + * logic if CONFIG_BOARDCTL_RESET is selected. + * + * Input Parameters: + * status - Status information provided with the reset event. This + * meaning of this status information is board-specific. If not + * used by a board, the value zero may be provided in calls to + * board_reset(). + * + * Returned Value: + * If this function returns, then it was not possible to power-off the + * board due to some constraints. The return value int this case is a + * board-specific reason for the failure to shutdown. + * + ****************************************************************************/ + +int board_reset(int status) +{ + up_systemreset(); + return 0; +} diff --git a/boards/arm/common/stm32/src/stm32_romfs_initialize.c b/boards/arm/common/stm32/src/stm32_romfs_initialize.c new file mode 100644 index 0000000000000..37690d7c9c769 --- /dev/null +++ b/boards/arm/common/stm32/src/stm32_romfs_initialize.c @@ -0,0 +1,151 @@ +/**************************************************************************** + * boards/arm/common/stm32/src/stm32_romfs_initialize.c + * + * SPDX-License-Identifier: BSD-3-Clause + * SPDX-FileCopyrightText: Tomasz Wozniak. All rights reserved. + * SPDX-FileContributor: Tomasz Wozniak + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include + +#include +#include +#include "stm32_romfs.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifndef CONFIG_STM32_ROMFS +# error "CONFIG_STM32_ROMFS must be defined" +#endif + +#ifndef CONFIG_STM32_ROMFS_IMAGEFILE +# error "CONFIG_STM32_ROMFS_IMAGEFILE must be defined" +#endif + +#ifndef CONFIG_STM32_ROMFS_DEV_MINOR +# error "CONFIG_STM32_ROMFS_DEV_MINOR must be defined" +#endif + +#ifndef CONFIG_STM32_ROMFS_MOUNTPOINT +# error "CONFIG_STM32_ROMFS_MOUNTPOINT must be defined" +#endif + +#define NSECTORS(size) (((size) + ROMFS_SECTOR_SIZE - 1)/ROMFS_SECTOR_SIZE) + +#define STR2(m) #m +#define STR(m) STR2(m) + +#define MKMOUNT_DEVNAME(m) "/dev/ram" STR(m) +#define MOUNT_DEVNAME MKMOUNT_DEVNAME(CONFIG_STM32_ROMFS_DEV_MINOR) + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +__asm__ ( + ".section .rodata, \"a\"\n" + ".balign 16\n" + ".globl romfs_data_begin\n" +"romfs_data_begin:\n" + ".incbin " STR(CONFIG_STM32_ROMFS_IMAGEFILE) "\n"\ + \ + ".balign " STR(ROMFS_SECTOR_SIZE) "\n" + ".globl romfs_data_end\n" +"romfs_data_end:\n"); + +extern const uint8_t romfs_data_begin[]; +extern const uint8_t romfs_data_end[]; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_romfs_initialize + * + * Description: + * Registers the aboveincluded binary file as block device. + * Then mounts the block device as ROMFS filesystems. + * + * Returned Value: + * Zero (OK) on success, a negated errno value on error. + * + * Assumptions/Limitations: + * Memory addresses [romfs_data_begin .. romfs_data_end) should contain + * ROMFS volume data, as included in the assembly snippet above (l. 84). + * + ****************************************************************************/ + +int stm32_romfs_initialize(void) +{ + size_t romfs_data_len; + int ret; + + /* Create a ROM disk for the /etc filesystem */ + + romfs_data_len = romfs_data_end - romfs_data_begin; + + ret = romdisk_register(CONFIG_STM32_ROMFS_DEV_MINOR, romfs_data_begin, + NSECTORS(romfs_data_len), ROMFS_SECTOR_SIZE); + if (ret < 0) + { + ferr("ERROR: romdisk_register failed: %d\n", -ret); + return ret; + } + + /* Mount the file system */ + + finfo("Mounting ROMFS filesystem at target=%s with source=%s\n", + CONFIG_STM32_ROMFS_MOUNTPOINT, MOUNT_DEVNAME); + + ret = nx_mount(MOUNT_DEVNAME, CONFIG_STM32_ROMFS_MOUNTPOINT, + "romfs", MS_RDONLY, NULL); + if (ret < 0) + { + ferr("ERROR: nx_mount(%s,%s,romfs) failed: %d\n", + MOUNT_DEVNAME, CONFIG_STM32_ROMFS_MOUNTPOINT, ret); + return ret; + } + + return OK; +} diff --git a/boards/arm/stm32/common/src/stm32_sbutton.c b/boards/arm/common/stm32/src/stm32_sbutton.c similarity index 99% rename from boards/arm/stm32/common/src/stm32_sbutton.c rename to boards/arm/common/stm32/src/stm32_sbutton.c index 5f2e52a9ac8c0..0659794a375ae 100644 --- a/boards/arm/stm32/common/src/stm32_sbutton.c +++ b/boards/arm/common/stm32/src/stm32_sbutton.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/src/stm32_sbutton.c + * boards/arm/common/stm32/src/stm32_sbutton.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/common/stm32/src/stm32_spitest.c b/boards/arm/common/stm32/src/stm32_spitest.c new file mode 100644 index 0000000000000..f5c628d00a5b0 --- /dev/null +++ b/boards/arm/common/stm32/src/stm32_spitest.c @@ -0,0 +1,176 @@ +/**************************************************************************** + * boards/arm/common/stm32/src/stm32_spitest.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include + +#include +#include + +#include "arm_internal.h" +#include "chip.h" +#include "stm32_spi.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#if defined(CONFIG_STM32_SPI1_TEST) +# if defined(CONFIG_STM32_SPI1_TEST_MODE0) +# define CONFIG_STM32_SPI1_TEST_MODE SPIDEV_MODE0 +# elif defined(CONFIG_STM32_SPI1_TEST_MODE1) +# define CONFIG_STM32_SPI1_TEST_MODE SPIDEV_MODE1 +# elif defined(CONFIG_STM32_SPI1_TEST_MODE2) +# define CONFIG_STM32_SPI1_TEST_MODE SPIDEV_MODE2 +# elif defined(CONFIG_STM32_SPI1_TEST_MODE3) +# define CONFIG_STM32_SPI1_TEST_MODE SPIDEV_MODE3 +# else +# error "No CONFIG_STM32_SPI1_TEST_MODEx defined" +# endif +#endif + +#if defined(CONFIG_STM32_SPI2_TEST) +# if defined(CONFIG_STM32_SPI2_TEST_MODE0) +# define CONFIG_STM32_SPI2_TEST_MODE SPIDEV_MODE0 +# elif defined(CONFIG_STM32_SPI2_TEST_MODE1) +# define CONFIG_STM32_SPI2_TEST_MODE SPIDEV_MODE1 +# elif defined(CONFIG_STM32_SPI2_TEST_MODE2) +# define CONFIG_STM32_SPI2_TEST_MODE SPIDEV_MODE2 +# elif defined(CONFIG_STM32_SPI2_TEST_MODE3) +# define CONFIG_STM32_SPI2_TEST_MODE SPIDEV_MODE3 +# else +# error "No CONFIG_STM32_SPI2_TEST_MODEx defined" +# endif +#endif + +#if defined(CONFIG_STM32_SPI3_TEST) +# if defined(CONFIG_STM32_SPI3_TEST_MODE0) +# define CONFIG_STM32_SPI3_TEST_MODE SPIDEV_MODE0 +# elif defined(CONFIG_STM32_SPI3_TEST_MODE1) +# define CONFIG_STM32_SPI3_TEST_MODE SPIDEV_MODE1 +# elif defined(CONFIG_STM32_SPI3_TEST_MODE2) +# define CONFIG_STM32_SPI3_TEST_MODE SPIDEV_MODE2 +# elif defined(CONFIG_STM32_SPI3_TEST_MODE3) +# define CONFIG_STM32_SPI3_TEST_MODE SPIDEV_MODE3 +# else +# error "No CONFIG_STM32_SPI3_TEST_MODEx defined" +# endif +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#if defined(CONFIG_STM32_SPI1) +struct spi_dev_s *g_spi1; +#endif +#if defined(CONFIG_STM32_SPI2) +struct spi_dev_s *g_spi2; +#endif +#if defined(CONFIG_STM32_SPI3) +struct spi_dev_s *g_spi3; +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_spidev_bus_test + * + * Description: + * Called to create the defined SPI buses and test them by initializing + * them and sending the CONFIG_STM32_SPI_TEST_MESSAGE (no chip select). + * + ****************************************************************************/ + +int stm32_spidev_bus_test(void) +{ + /* Configure and test SPI- */ + + uint8_t *tx = (uint8_t *)CONFIG_STM32_SPI_TEST_MESSAGE; + +#if defined(CONFIG_STM32_SPI1_TEST) + g_spi1 = stm32_spibus_initialize(1); + + if (!g_spi1) + { + syslog(LOG_ERR, "ERROR Failed to initialize SPI port 1\n"); + return -ENODEV; + } + + /* Default SPI1 to STM32_SPI1_FREQ and mode */ + + SPI_SETFREQUENCY(g_spi1, CONFIG_STM32_SPI1_TEST_FREQ); + SPI_SETBITS(g_spi1, CONFIG_STM32_SPI1_TEST_BITS); + SPI_SETMODE(g_spi1, CONFIG_STM32_SPI1_TEST_MODE); + SPI_EXCHANGE(g_spi1, tx, NULL, + nitems(CONFIG_STM32_SPI_TEST_MESSAGE)); +#endif + +#if defined(CONFIG_STM32_SPI2_TEST) + g_spi2 = stm32_spibus_initialize(2); + + if (!g_spi2) + { + syslog(LOG_ERR, "ERROR Failed to initialize SPI port 2\n"); + return -ENODEV; + } + + /* Default SPI2 to STM32_SPI2_FREQ and mode */ + + SPI_SETFREQUENCY(g_spi2, CONFIG_STM32_SPI2_TEST_FREQ); + SPI_SETBITS(g_spi2, CONFIG_STM32_SPI2_TEST_BITS); + SPI_SETMODE(g_spi2, CONFIG_STM32_SPI2_TEST_MODE); + SPI_EXCHANGE(g_spi2, tx, NULL, + nitems(CONFIG_STM32_SPI_TEST_MESSAGE)); +#endif + +#if defined(CONFIG_STM32_SPI3_TEST) + g_spi3 = stm32_spibus_initialize(3); + + if (!g_spi3) + { + syslog(LOG_ERR, "ERROR Failed to initialize SPI port 2\n"); + return -ENODEV; + } + + /* Default SPI3 to STM32_SPI3_FREQ and mode */ + + SPI_SETFREQUENCY(g_spi3, CONFIG_STM32_SPI3_TEST_FREQ); + SPI_SETBITS(g_spi3, CONFIG_STM32_SPI3_TEST_BITS); + SPI_SETMODE(g_spi3, CONFIG_STM32_SPI3_TEST_MODE); + SPI_EXCHANGE(g_spi3, tx, NULL, + nitems(CONFIG_STM32_SPI_TEST_MESSAGE)); +#endif + + return OK; +} diff --git a/boards/arm/common/stm32/src/stm32_ssd1306.c b/boards/arm/common/stm32/src/stm32_ssd1306.c new file mode 100644 index 0000000000000..1c73555da92e4 --- /dev/null +++ b/boards/arm/common/stm32/src/stm32_ssd1306.c @@ -0,0 +1,163 @@ +/**************************************************************************** + * boards/arm/common/stm32/src/stm32_ssd1306.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include +#include +#include +#include +#include + +#include "stm32_i2c.h" +#include "stm32_spi.h" + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static struct lcd_dev_s *g_lcddev; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_ssd1306_initialize + * + * Description: + * Initialize and register the device. I2C version. + * + * Input Parameters: + * busno - The I2C bus number + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ +#ifdef CONFIG_LCD_SSD1306_I2C +int board_ssd1306_initialize(int busno) +{ + struct i2c_master_s *i2c; + const int devno = 0; + + /* Initialize I2C */ + + i2c = stm32_i2cbus_initialize(busno); + if (!i2c) + { + lcderr("ERROR: Failed to initialize I2C port %d\n", busno); + return -ENODEV; + } + + /* Bind the I2C port to the OLED */ + + g_lcddev = ssd1306_initialize(i2c, NULL, devno); + if (!g_lcddev) + { + lcderr("ERROR: Failed to bind I2C port %d to OLED %d\n", busno, devno); + return -ENODEV; + } + else + { + lcdinfo("Bound I2C port %d to OLED %d\n", busno, devno); + + /* And turn the OLED on */ + + g_lcddev->setpower(g_lcddev, CONFIG_LCD_MAXPOWER); + + ssd1306_fill(g_lcddev, 0xff); + + return OK; + } +} +#endif + +/**************************************************************************** + * Name: board_ssd1306_initialize + * + * Description: + * Initialize and register the device. SPI version. + * + * Input Parameters: + * busno - The SPI bus number + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ +#ifdef CONFIG_LCD_SSD1306_SPI +int board_ssd1306_initialize(int busno) +{ + struct spi_dev_s *spi; + const int devno = 0; + + /* Initialize SPI */ + + spi = stm32_spibus_initialize(busno); + if (!spi) + { + lcderr("ERROR: Failed to initialize SPI port %d\n", busno); + return -ENODEV; + } + + /* Bind the SPI port to the OLED */ + + g_lcddev = ssd1306_initialize(spi, NULL, devno); + if (!g_lcddev) + { + lcderr("ERROR: Failed to bind SPI port %d to OLED %d\n", busno, devno); + return -ENODEV; + } + else + { + lcdinfo("Bound SPI port %d to OLED %d\n", busno, devno); + + /* And turn the OLED on */ + + g_lcddev->setpower(g_lcddev, CONFIG_LCD_MAXPOWER); + return OK; + } +} +#endif + +/**************************************************************************** + * Name: board_ssd1306_getdev + * + * Description: + * Get the SSD1306 device driver instance + * + * Returned Value: + * Pointer to the instance + * + ****************************************************************************/ + +struct lcd_dev_s *board_ssd1306_getdev(void) +{ + return g_lcddev; +} diff --git a/boards/arm/stm32/common/src/stm32_tone.c b/boards/arm/common/stm32/src/stm32_tone.c similarity index 99% rename from boards/arm/stm32/common/src/stm32_tone.c rename to boards/arm/common/stm32/src/stm32_tone.c index 58bbcd22242ad..178f8c1504c8a 100644 --- a/boards/arm/stm32/common/src/stm32_tone.c +++ b/boards/arm/common/stm32/src/stm32_tone.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/src/stm32_tone.c + * boards/arm/common/stm32/src/stm32_tone.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/common/src/stm32_veml6070.c b/boards/arm/common/stm32/src/stm32_veml6070.c similarity index 98% rename from boards/arm/stm32/common/src/stm32_veml6070.c rename to boards/arm/common/stm32/src/stm32_veml6070.c index e5b38b9ac9b84..b5e918973f20c 100644 --- a/boards/arm/stm32/common/src/stm32_veml6070.c +++ b/boards/arm/common/stm32/src/stm32_veml6070.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/src/stm32_veml6070.c + * boards/arm/common/stm32/src/stm32_veml6070.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/common/src/stm32_ws2812.c b/boards/arm/common/stm32/src/stm32_ws2812.c similarity index 98% rename from boards/arm/stm32/common/src/stm32_ws2812.c rename to boards/arm/common/stm32/src/stm32_ws2812.c index 640fb1e630879..d206941ed91ae 100644 --- a/boards/arm/stm32/common/src/stm32_ws2812.c +++ b/boards/arm/common/stm32/src/stm32_ws2812.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/src/stm32_ws2812.c + * boards/arm/common/stm32/src/stm32_ws2812.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/common/src/stm32_xen1210.c b/boards/arm/common/stm32/src/stm32_xen1210.c similarity index 99% rename from boards/arm/stm32/common/src/stm32_xen1210.c rename to boards/arm/common/stm32/src/stm32_xen1210.c index 1dcb2a2787ee6..4b4311933c7b9 100644 --- a/boards/arm/stm32/common/src/stm32_xen1210.c +++ b/boards/arm/common/stm32/src/stm32_xen1210.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/src/stm32_xen1210.c + * boards/arm/common/stm32/src/stm32_xen1210.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/common/src/stm32_zerocross.c b/boards/arm/common/stm32/src/stm32_zerocross.c similarity index 99% rename from boards/arm/stm32/common/src/stm32_zerocross.c rename to boards/arm/common/stm32/src/stm32_zerocross.c index c0a8a3900f4e8..660719d6fb996 100644 --- a/boards/arm/stm32/common/src/stm32_zerocross.c +++ b/boards/arm/common/stm32/src/stm32_zerocross.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/src/stm32_zerocross.c + * boards/arm/common/stm32/src/stm32_zerocross.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/axoloti/CMakeLists.txt b/boards/arm/stm32/axoloti/CMakeLists.txt deleted file mode 100644 index 47501793832b2..0000000000000 --- a/boards/arm/stm32/axoloti/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/axoloti/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32/axoloti/configs/nsh/defconfig b/boards/arm/stm32/axoloti/configs/nsh/defconfig deleted file mode 100644 index 1d43644ebd105..0000000000000 --- a/boards/arm/stm32/axoloti/configs/nsh/defconfig +++ /dev/null @@ -1,39 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_ARCH_LEDS is not set -# CONFIG_NSH_DISABLE_PS is not set -# CONFIG_STANDARD_SERIAL is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="axoloti" -CONFIG_ARCH_BOARD_AXOLOTI=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F427I=y -CONFIG_ARCH_IRQBUTTONS=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INPUT=y -CONFIG_INPUT_BUTTONS=y -CONFIG_INPUT_BUTTONS_LOWER=y -CONFIG_LIBC_FLOATINGPOINT=y -CONFIG_MM_REGIONS=2 -CONFIG_RAW_BINARY=y -CONFIG_STM32_CCMEXCLUDE=y -CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32_JTAG_FULL_ENABLE=y -CONFIG_STM32_USART1=y -CONFIG_STM32_USART6=y -CONFIG_SYSTEM_NSH=y -CONFIG_USART1_SERIAL_CONSOLE=y -CONFIG_USART6_BAUD=31250 -CONFIG_USART6_RXBUFSIZE=128 -CONFIG_USART6_TXBUFSIZE=32 -CONFIG_USERLED=y -CONFIG_USERLED_LOWER=y diff --git a/boards/arm/stm32/axoloti/include/board.h b/boards/arm/stm32/axoloti/include/board.h deleted file mode 100644 index 41d122815b3f8..0000000000000 --- a/boards/arm/stm32/axoloti/include/board.h +++ /dev/null @@ -1,263 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/axoloti/include/board.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __BOARDS_ARM_STM32_AXOLOTI_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32_AXOLOTI_INCLUDE_BOARD_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#ifndef __ASSEMBLY__ -# include -# include -#endif - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Clocking - * The Axoloti board has an external 8MHz crystal. - * The SoC can run at 180MHz, but the required USB clock of 48MHz cannot be - * configured at that system clock rate, so the core clock is 168MHz. - * - * This is the canonical configuration: - * System Clock source : PLL (HSE) - * SYSCLK(Hz) : 168000000 Determined by PLL configuration - * HCLK(Hz) : 168000000 (STM32_RCC_CFGR_HPRE) - * AHB Prescaler : 1 (STM32_RCC_CFGR_HPRE) - * APB1 Prescaler : 4 (STM32_RCC_CFGR_PPRE1) - * APB2 Prescaler : 2 (STM32_RCC_CFGR_PPRE2) - * HSE Frequency(Hz) : 8000000 (STM32_BOARD_XTAL) - * PLLM : 8 (STM32_PLLCFG_PLLM) - * PLLN : 336 (STM32_PLLCFG_PLLN) - * PLLP : 2 (STM32_PLLCFG_PLLP) - * PLLQ : 7 (STM32_PLLCFG_PLLQ) - * Main regulator - * output voltage : Scale1 mode Needed for high speed SYSCLK - * Flash Latency(WS) : 5 - * Prefetch Buffer : OFF - * Instruction cache : ON - * Data cache : ON - * Require 48MHz for - * USB OTG FS, - * SDIO and RNG clock : Enabled - */ - -/* HSI - 16 MHz RC factory-trimmed - * LSI - 32 KHz RC - * HSE - On-board crystal frequency is 8MHz - * LSE - 32.768 kHz - */ - -#define STM32_BOARD_XTAL 8000000ul - -#define STM32_HSI_FREQUENCY 16000000ul -#define STM32_LSI_FREQUENCY 32000 -#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL -#define STM32_LSE_FREQUENCY 32768 - -/* Main PLL Configuration. - * - * PLL source is HSE - * PLL_VCO = (STM32_HSE_FREQUENCY / PLLM) * PLLN - * = (8,000,000 / 8) * 336 - * = 336,000,000 - * SYSCLK = PLL_VCO / PLLP - * = 336,000,000 / 2 = 168,000,000 - * USB OTG FS, SDIO and RNG Clock - * = PLL_VCO / PLLQ - * = 48,000,000 - */ - -#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(8) -#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(336) -#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_2 -#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(7) - -#define STM32_SYSCLK_FREQUENCY 168000000ul - -/* AHB clock (HCLK) is SYSCLK (168MHz) */ - -#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ -#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY - -/* APB1 clock (PCLK1) is HCLK/4 (42MHz) */ - -#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd4 /* PCLK1 = HCLK / 4 */ -#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/4) - -/* APB2 clock (PCLK2) is HCLK/2 (84MHz) */ - -#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLKd2 /* PCLK2 = HCLK / 2 */ -#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/2) - -/**************************************************************************** - * LED Definitions - * If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs in - * any way. The following definitions are used to access individual LEDs. - */ - -/* LED index values for use with board_userled() */ - -#define BOARD_LED1 0 -#define BOARD_LED2 1 -#define BOARD_NLEDS 2 -#define BOARD_LED_GREEN BOARD_LED1 -#define BOARD_LED_RED BOARD_LED2 - -/* LED bits for use with board_userled_all() */ - -#define BOARD_LED1_BIT (1 << BOARD_LED1) -#define BOARD_LED2_BIT (1 << BOARD_LED2) - -/**************************************************************************** - * Button Definitions - * There are two buttons on the axoloti, one of them is GPIO connected. The - * other is a reset button and is not under software control. - */ - -#define BUTTON_USER 0 -#define NUM_BUTTONS 1 -#define BUTTON_USER_BIT (1 << BUTTON_USER) - -/**************************************************************************** - * UARTs - * The MIDI in/out ports of the axoloti are connected on USART6. - * It maybe convenient to run a serial port connected to the header pins, - * so we can optionally use USART1 for that. - */ - -/* USART1 - console on header pins */ - -#define GPIO_USART1_RX (GPIO_USART1_RX_2|GPIO_SPEED_100MHz) /* AF7, PB7 */ -#define GPIO_USART1_TX (GPIO_USART1_TX_2|GPIO_SPEED_100MHz) /* AF7, PB6 */ - -/* USART6 - midi in/out */ - -#define GPIO_USART6_RX (GPIO_ALT|GPIO_AF8|GPIO_PORTG|GPIO_PIN9| \ - GPIO_PULLUP|GPIO_SPEED_2MHz|GPIO_PUSHPULL) - -#define GPIO_USART6_TX (GPIO_ALT|GPIO_AF8|GPIO_PORTG|GPIO_PIN14| \ - GPIO_FLOAT|GPIO_SPEED_2MHz|GPIO_OPENDRAIN) - -/**************************************************************************** - * I2C Bus - * Turn on the internal pullups since there are no external pullups. - */ - -/* I2C1 - for external devices */ - -#define GPIO_I2C1_SCL (GPIO_ALT|GPIO_AF4|GPIO_PORTB|GPIO_PIN8| \ - GPIO_SPEED_2MHz|GPIO_OPENDRAIN|GPIO_PULLUP) - -#define GPIO_I2C1_SDA (GPIO_ALT|GPIO_AF4|GPIO_PORTB|GPIO_PIN9| \ - GPIO_SPEED_2MHz|GPIO_OPENDRAIN|GPIO_PULLUP) - -/* I2C3 - for the ADAU1961 codec */ - -#define GPIO_I2C3_SCL (GPIO_ALT|GPIO_AF4|GPIO_PORTH|GPIO_PIN7| \ - GPIO_SPEED_2MHz|GPIO_OPENDRAIN|GPIO_PULLUP) - -#define GPIO_I2C3_SDA (GPIO_ALT|GPIO_AF4|GPIO_PORTH|GPIO_PIN8| \ - GPIO_SPEED_2MHz|GPIO_OPENDRAIN|GPIO_PULLUP) - -/**************************************************************************** - * SAI Bus - * Used with the ADAU1961 CODEC - * PE3_SAI1_SD_B (GPIO_SAI1_SD_B_1) - * PE4_SAI1_FS_A (GPIO_SAI1_FS_A) - * PE5_SAI1_SCK_A (GPIO_SAI1_SCK_A) - * PE6_SAI1_SD_A (GPIO_SAI1_SD_A_2) - * PA8_MCO1 - */ - -#define GPIO_SAI1_SD_B GPIO_SAI1_SD_B_1 /* AF6, PE3 */ -#define GPIO_SAI1_SD_A GPIO_SAI1_SD_A_2 /* AF6, PE6 */ - -#define STM32_SAI1_FREQUENCY (48000 * 2 * 256) /* TODO ?? */ - -/* DAC DMA to Codec - * dma 2, stream 1, channel 0 - * memory to peripheral - * 32 bits - */ -#define DMACHAN_SAI1_A DMAMAP_SAI1_A_1 - -/* ADC DMA from Codec - * dma 2, stream 4, channel 1, - * peripheral to memory - * 32 bits - */ -#define DMACHAN_SAI1_B DMAMAP_SAI1_B_2 - -/**************************************************************************** - * SDIO - * Used for the SD card interface. - * d0 (AF12, PC8) - * d1 (AF12, PC9) - * d2 (AF12, PC10) - * d3 (AF12, PC11) - * clk (AF12, PC12) - * cmd (AF12, PD2) - * cd1 PD13 - */ - -/* SDIO dividers. Note that slower clocking is required when DMA is disabled - * in order to avoid RX overrun/TX underrun errors due to delayed responses - * to service FIFOs in interrupt driven mode. These values have not been - * tuned!!! - * - * SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(118+2)=400 KHz - */ - -#define SDIO_INIT_CLKDIV (118 << SDIO_CLKCR_CLKDIV_SHIFT) - -/* DMA ON: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(1+2)=16 MHz - * DMA OFF: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(2+2)=12 MHz - */ - -#ifdef CONFIG_SDIO_DMA -# define SDIO_MMCXFR_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT) -#else -# define SDIO_MMCXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT) -#endif - -/* DMA ON: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(1+2)=16 MHz - * DMA OFF: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(2+2)=12 MHz - */ - -#ifdef CONFIG_SDIO_DMA -# define SDIO_SDXFR_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT) -#else -# define SDIO_SDXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT) -#endif - -/* dma 2, stream 6, channel 4 */ - -#define DMAMAP_SDIO DMAMAP_SDIO_2 - -#endif /* __BOARDS_ARM_STM32_AXOLOTI_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32/axoloti/scripts/Make.defs b/boards/arm/stm32/axoloti/scripts/Make.defs deleted file mode 100644 index e284200c3badc..0000000000000 --- a/boards/arm/stm32/axoloti/scripts/Make.defs +++ /dev/null @@ -1,41 +0,0 @@ -############################################################################ -# boards/arm/stm32/axoloti/scripts/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/.config -include $(TOPDIR)/tools/Config.mk -include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs - -LDSCRIPT = ld.script -ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) - -ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 - -CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) -CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) -CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -AFLAGS := $(CFLAGS) -D__ASSEMBLY__ - -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections -LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32/axoloti/scripts/kernel-space.ld b/boards/arm/stm32/axoloti/scripts/kernel-space.ld deleted file mode 100644 index 64edc323381f0..0000000000000 --- a/boards/arm/stm32/axoloti/scripts/kernel-space.ld +++ /dev/null @@ -1,100 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/axoloti/scripts/kernel-space.ld - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* NOTE: This depends on the memory.ld script having been included prior to - * this script. - */ - -OUTPUT_ARCH(arm) -EXTERN(_vectors) -ENTRY(_stext) -SECTIONS -{ - .text : { - _stext = ABSOLUTE(.); - *(.vectors) - *(.text .text.*) - *(.fixup) - *(.gnu.warning) - *(.rodata .rodata.*) - *(.gnu.linkonce.t.*) - *(.glue_7) - *(.glue_7t) - *(.got) - *(.gcc_except_table) - *(.gnu.linkonce.r.*) - _etext = ABSOLUTE(.); - } > kflash - - .init_section : { - _sinit = ABSOLUTE(.); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) - KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) - _einit = ABSOLUTE(.); - } > kflash - - .ARM.extab : { - *(.ARM.extab*) - } > kflash - - __exidx_start = ABSOLUTE(.); - .ARM.exidx : { - *(.ARM.exidx*) - } > kflash - - __exidx_end = ABSOLUTE(.); - - _eronly = ABSOLUTE(.); - - .data : { - _sdata = ABSOLUTE(.); - *(.data .data.*) - *(.gnu.linkonce.d.*) - CONSTRUCTORS - . = ALIGN(4); - _edata = ABSOLUTE(.); - } > ksram AT > kflash - - .bss : { - _sbss = ABSOLUTE(.); - *(.bss .bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - . = ALIGN(8); - _ebss = ABSOLUTE(.); - } > ksram - - /* Stabs debugging sections */ - - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_info 0 : { *(.debug_info) } - .debug_line 0 : { *(.debug_line) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_aranges 0 : { *(.debug_aranges) } -} diff --git a/boards/arm/stm32/axoloti/scripts/ld.script b/boards/arm/stm32/axoloti/scripts/ld.script deleted file mode 100644 index c7bb602cb211c..0000000000000 --- a/boards/arm/stm32/axoloti/scripts/ld.script +++ /dev/null @@ -1,132 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/axoloti/scripts/ld.script - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* The STM32F427IGH6 has 1024KiB of FLASH beginning at address 0x0800:0000 and - * 256KiB of SRAM. SRAM is split up into four blocks: - * - * 1) 112KiB of SRAM beginning at address 0x2000:0000 - * 2) 16KiB of SRAM beginning at address 0x2001:c000 - * 3) 64KiB of SRAM beginning at address 0x2002:0000 - * 4) 64KiB of CCM SRAM beginning at address 0x1000:0000 - * - * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 - * where the code expects to begin execution by jumping to the entry point in - * the 0x0800:0000 address - * range. - */ - -MEMORY -{ - flash (rx) : ORIGIN = 0x08000000, LENGTH = 1024K - sram (rwx) : ORIGIN = 0x20000000, LENGTH = 112K -} - -OUTPUT_ARCH(arm) -EXTERN(_vectors) -ENTRY(_stext) -SECTIONS -{ - .text : { - _stext = ABSOLUTE(.); - *(.vectors) - *(.text .text.*) - *(.fixup) - *(.gnu.warning) - *(.rodata .rodata.*) - *(.gnu.linkonce.t.*) - *(.glue_7) - *(.glue_7t) - *(.got) - *(.gcc_except_table) - *(.gnu.linkonce.r.*) - _etext = ABSOLUTE(.); - } > flash - - .init_section : { - _sinit = ABSOLUTE(.); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) - KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) - _einit = ABSOLUTE(.); - } > flash - - .ARM.extab : { - *(.ARM.extab*) - } > flash - - __exidx_start = ABSOLUTE(.); - .ARM.exidx : { - *(.ARM.exidx*) - } > flash - __exidx_end = ABSOLUTE(.); - - .tdata : { - _stdata = ABSOLUTE(.); - *(.tdata .tdata.* .gnu.linkonce.td.*); - _etdata = ABSOLUTE(.); - } > flash - - .tbss : { - _stbss = ABSOLUTE(.); - *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); - _etbss = ABSOLUTE(.); - } > flash - - _eronly = ABSOLUTE(.); - - /* The RAM vector table (if present) should lie at the beginning of SRAM */ - - .ram_vectors : { - *(.ram_vectors) - } > sram - - .data : { - _sdata = ABSOLUTE(.); - *(.data .data.*) - *(.gnu.linkonce.d.*) - CONSTRUCTORS - . = ALIGN(4); - _edata = ABSOLUTE(.); - } > sram AT > flash - - .bss : { - _sbss = ABSOLUTE(.); - *(.bss .bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - . = ALIGN(4); - _ebss = ABSOLUTE(.); - } > sram - - /* Stabs debugging sections. */ - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_info 0 : { *(.debug_info) } - .debug_line 0 : { *(.debug_line) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_aranges 0 : { *(.debug_aranges) } -} diff --git a/boards/arm/stm32/axoloti/scripts/memory.ld b/boards/arm/stm32/axoloti/scripts/memory.ld deleted file mode 100644 index 2815db533fba4..0000000000000 --- a/boards/arm/stm32/axoloti/scripts/memory.ld +++ /dev/null @@ -1,88 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/axoloti/scripts/memory.ld - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* The STM32F427IGH6 has 1024KiB of FLASH beginning at address 0x0800:0000 and - * 256KiB of SRAM. SRAM is split up into four blocks: - * - * 1) 112KiB of SRAM beginning at address 0x2000:0000 - * 2) 16KiB of SRAM beginning at address 0x2001:c000 - * 3) 64KiB of SRAM beginning at address 0x2002:0000 - * 4) 64KiB of CCM SRAM beginning at address 0x1000:0000 - * - * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 - * where the code expects to begin execution by jumping to the entry point in - * the 0x0800:0000 address range. - * - * For MPU support, the kernel-mode NuttX section is assumed to be 128Kb of - * FLASH and 4Kb of SRAM. That is an excessive amount for the kernel which - * should fit into 64KB and, of course, can be optimized as needed (See - * also boards/arm/stm32/axoloti/scripts/kernel-space.ld). Allowing the - * additional does permit addition debug instrumentation to be added to the - * kernel space without overflowing the partition. - * - * Alignment of the user space FLASH partition is also a critical factor: - * The user space FLASH partition will be spanned with a single region of - * size 2**n bytes. The alignment of the user-space region must be the same. - * As a consequence, as the user-space increases in size, the alignment - * requirement also increases. - * - * This alignment requirement means that the largest user space FLASH region - * you can have will be 512KB at it would have to be positioned at - * 0x08800000. If you change this address, don't forget to change the - * CONFIG_NUTTX_USERSPACE configuration setting to match and to modify - * the check in kernel/userspace.c. - * - * For the same reasons, the maximum size of the SRAM mapping is limited to - * 4KB. Both of these alignment limitations could be reduced by using - * multiple regions to map the FLASH/SDRAM range or perhaps with some - * clever use of subregions. - * - * A detailed memory map for the 112KB SRAM region is as follows: - * - * 0x20000 0000: Kernel .data region. Typical size: 0.1KB - * ------- ---- Kernel .bss region. Typical size: 1.8KB - * 0x20000 0800: Kernel IDLE thread stack (approximate). Size is - * determined by CONFIG_IDLETHREAD_STACKSIZE and - * adjustments for alignment. Typical is 1KB. - * ------- ---- Padded to 4KB - * 0x20000 1000: User .data region. Size is variable. - * ------- ---- User .bss region Size is variable. - * 0x20000 2000: Beginning of kernel heap. Size determined by - * CONFIG_MM_KERNEL_HEAPSIZE. - * ------- ---- Beginning of user heap. Can vary with other settings. - * 0x20001 c000: End+1 of CPU RAM - */ - -MEMORY -{ - /* 1024Kb FLASH */ - - kflash (rx) : ORIGIN = 0x08000000, LENGTH = 128K - uflash (rx) : ORIGIN = 0x08020000, LENGTH = 128K - xflash (rx) : ORIGIN = 0x08040000, LENGTH = 768K - - /* 112Kb of contiguous SRAM */ - - ksram (rwx) : ORIGIN = 0x20000000, LENGTH = 4K - usram (rwx) : ORIGIN = 0x20001000, LENGTH = 4K - xsram (rwx) : ORIGIN = 0x20002000, LENGTH = 104K -} diff --git a/boards/arm/stm32/axoloti/scripts/user-space.ld b/boards/arm/stm32/axoloti/scripts/user-space.ld deleted file mode 100644 index 0a24aa25f6cec..0000000000000 --- a/boards/arm/stm32/axoloti/scripts/user-space.ld +++ /dev/null @@ -1,114 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/axoloti/scripts/user-space.ld - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* NOTE: This depends on the memory.ld script having been included prior to - * this script. - */ - -/* Make sure that the critical memory management functions are in user-space. - * the user heap memory manager will reside in user-space but be usable both - * by kernel- and user-space code - */ - -EXTERN(umm_initialize) -EXTERN(umm_addregion) - -EXTERN(malloc) -EXTERN(realloc) -EXTERN(zalloc) -EXTERN(free) - -OUTPUT_ARCH(arm) -SECTIONS -{ - .userspace : { - *(.userspace) - } > uflash - - .text : { - _stext = ABSOLUTE(.); - *(.text .text.*) - *(.fixup) - *(.gnu.warning) - *(.rodata .rodata.*) - *(.gnu.linkonce.t.*) - *(.glue_7) - *(.glue_7t) - *(.got) - *(.gcc_except_table) - *(.gnu.linkonce.r.*) - _etext = ABSOLUTE(.); - } > uflash - - .init_section : { - _sinit = ABSOLUTE(.); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) - KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) - _einit = ABSOLUTE(.); - } > uflash - - .ARM.extab : { - *(.ARM.extab*) - } > uflash - - __exidx_start = ABSOLUTE(.); - .ARM.exidx : { - *(.ARM.exidx*) - } > uflash - - __exidx_end = ABSOLUTE(.); - - _eronly = ABSOLUTE(.); - - .data : { - _sdata = ABSOLUTE(.); - *(.data .data.*) - *(.gnu.linkonce.d.*) - CONSTRUCTORS - . = ALIGN(4); - _edata = ABSOLUTE(.); - } > usram AT > uflash - - .bss : { - _sbss = ABSOLUTE(.); - *(.bss .bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - . = ALIGN(8); - _ebss = ABSOLUTE(.); - } > usram - - /* Stabs debugging sections */ - - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_info 0 : { *(.debug_info) } - .debug_line 0 : { *(.debug_line) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_aranges 0 : { *(.debug_aranges) } -} diff --git a/boards/arm/stm32/axoloti/src/CMakeLists.txt b/boards/arm/stm32/axoloti/src/CMakeLists.txt deleted file mode 100644 index c232216905b87..0000000000000 --- a/boards/arm/stm32/axoloti/src/CMakeLists.txt +++ /dev/null @@ -1,53 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/axoloti/src/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -set(SRCS stm32_boot.c stm32_bringup.c) - -if(CONFIG_STM32_FMC) - list(APPEND SRCS stm32_extmem.c) -endif() - -if(CONFIG_ARCH_LEDS) - list(APPEND SRCS stm32_autoleds.c) -else() - list(APPEND SRCS stm32_userleds.c) -endif() - -if(CONFIG_AUDIO_ADAU1961) - list(APPEND SRCS stm32_adau1961.c) -endif() - -if(CONFIG_ARCH_BUTTONS) - list(APPEND SRCS stm32_buttons.c) -endif() - -if(CONFIG_STM32_SDIO) - list(APPEND SRCS stm32_sdio.c) -endif() - -if(CONFIG_USBHOST) - list(APPEND SRCS stm32_usbhost.c) -endif() - -target_sources(board PRIVATE ${SRCS}) - -set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/ld.script") diff --git a/boards/arm/stm32/axoloti/src/Make.defs b/boards/arm/stm32/axoloti/src/Make.defs deleted file mode 100644 index e13a8e8280230..0000000000000 --- a/boards/arm/stm32/axoloti/src/Make.defs +++ /dev/null @@ -1,55 +0,0 @@ -############################################################################ -# boards/arm/stm32/axoloti/src/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/Make.defs - -CSRCS = stm32_boot.c stm32_bringup.c - -ifeq ($(CONFIG_STM32_FMC),y) -CSRCS += stm32_extmem.c -endif - -ifeq ($(CONFIG_ARCH_LEDS),y) -CSRCS += stm32_autoleds.c -else -CSRCS += stm32_userleds.c -endif - -ifeq ($(CONFIG_AUDIO_ADAU1961),y) -CSRCS += stm32_adau1961.c -endif - -ifeq ($(CONFIG_ARCH_BUTTONS),y) -CSRCS += stm32_buttons.c -endif - -ifeq ($(CONFIG_STM32_SDIO),y) -CSRCS += stm32_sdio.c -endif - -ifeq ($(CONFIG_USBHOST),y) -CSRCS += stm32_usbhost.c -endif - -DEPPATH += --dep-path board -VPATH += :board -CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/axoloti/src/stm32_boot.c b/boards/arm/stm32/axoloti/src/stm32_boot.c deleted file mode 100644 index eda2b87a77412..0000000000000 --- a/boards/arm/stm32/axoloti/src/stm32_boot.c +++ /dev/null @@ -1,89 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/axoloti/src/stm32_boot.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include -#include - -#include "arm_internal.h" -#include "nvic.h" -#include "itm.h" - -#include "stm32.h" -#include "axoloti.h" - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_boardinitialize - * - * Description: - * All STM32 architectures must provide the following entry point. This - * entry point is called early in the initialization -- after all memory - * has been configured and mapped but before any devices have been - * initialized. - * - ****************************************************************************/ - -void stm32_boardinitialize(void) -{ -#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || \ - defined(CONFIG_STM32_SPI3) - stm32_spidev_initialize(); -#endif - -#if defined(CONFIG_STM32_OTGHS) || defined(CONFIG_STM32_OTGFS) - stm32_usbinitialize(); -#endif -} - -/**************************************************************************** - * Name: board_late_initialize - * - * Description: - * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional - * initialization call will be performed in the boot-up sequence to a - * function called board_late_initialize(). board_late_initialize() will - * be called immediately after up_initialize() is called and just before - * the initial application is started. This additional initialization - * phase may be used, for example, to initialize board-specific device - * drivers. - * - ****************************************************************************/ - -#ifdef CONFIG_BOARD_LATE_INITIALIZE -void board_late_initialize(void) -{ - /* Perform board-specific initialization */ - - stm32_bringup(); -} -#endif diff --git a/boards/arm/stm32/axoloti/src/stm32_bringup.c b/boards/arm/stm32/axoloti/src/stm32_bringup.c deleted file mode 100644 index 0232a265bf966..0000000000000 --- a/boards/arm/stm32/axoloti/src/stm32_bringup.c +++ /dev/null @@ -1,176 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/axoloti/src/stm32_bringup.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include - -#include - -#ifdef CONFIG_USBMONITOR -# include -#endif - -#include "stm32.h" - -#ifdef CONFIG_STM32_OTGHS -# include "stm32_usbhost.h" -#endif - -#ifdef CONFIG_INPUT_BUTTONS -# include -#endif - -#ifdef CONFIG_USERLED -# include -#endif - -#include "axoloti.h" - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_bringup - * - * Description: - * Perform architecture-specific initialization - * - * CONFIG_BOARD_LATE_INITIALIZE=y : - * Called from board_late_initialize(). - * - ****************************************************************************/ - -int stm32_bringup(void) -{ -#ifdef HAVE_RTC_DRIVER - struct rtc_lowerhalf_s *lower; -#endif - int ret = OK; - -#ifdef HAVE_SDRAM - /* Initialize access to the SDRAM device */ - - ret = stm32_sdram_initialize(); - if (ret != OK) - { - syslog(LOG_ERR, "stm32_sdram_initialize failed %d\n", ret); - return ret; - } -#endif - -#ifdef HAVE_SDIO - /* Initialize the SDIO block driver */ - - ret = stm32_sdio_initialize(); - if (ret != OK) - { - syslog(LOG_ERR, "stm32_sdio_initialize failed %d\n", ret); - return ret; - } -#endif - -#ifdef HAVE_USBHOST - /* Initialize USB host operation. stm32_usbhost_initialize() starts a - * thread will monitor for USB connection and disconnection events. - */ - - ret = stm32_usbhost_initialize(); - if (ret != OK) - { - syslog(LOG_ERR, "stm32_usbhost_initialize failed %d\n", ret); - return ret; - } -#endif - -#ifdef HAVE_USBMONITOR - /* Start the USB Monitor */ - - ret = usbmonitor_start(); - if (ret != OK) - { - syslog(LOG_ERR, "usbmonitor_start failed %d\n", ret); - return ret; - } -#endif - -#ifdef CONFIG_INPUT_BUTTONS - /* Register the BUTTON driver */ - - ret = btn_lower_initialize("/dev/buttons"); - if (ret < 0) - { - syslog(LOG_ERR, "btn_lower_initialize failed %d\n", ret); - } -#endif - -#ifdef CONFIG_INPUT_REI2C - /* Register the rei2c driver */ - - ret = rei2c_initialize("/dev/re0"); - if (ret < 0) - { - syslog(LOG_ERR, "rei2c_initialize failed %d\n", ret); - } -#endif - -#ifdef CONFIG_USERLED - /* Register the LED driver */ - - ret = userled_lower_initialize("/dev/userleds"); - if (ret < 0) - { - syslog(LOG_ERR, "userled_lower_initialize failed %d\n", ret); - } -#endif - -#ifdef HAVE_ADAU1961 - /* Configure ADAU1961 audio */ - - ret = stm32_adau1961_initialize(1); - if (ret != OK) - { - syslog(LOG_ERR, "stm32_adau1961_initialize failed %d\n", ret); - } -#endif - -#ifdef CONFIG_FS_PROCFS - /* Mount the procfs file system */ - - ret = nx_mount(NULL, STM32_PROCFS_MOUNTPOINT, "procfs", 0, NULL); - if (ret < 0) - { - syslog(LOG_ERR, "failed to mount procfs at %s %d\n", - STM32_PROCFS_MOUNTPOINT, ret); - } -#endif - - return ret; -} diff --git a/boards/arm/stm32/axoloti/src/stm32_buttons.c b/boards/arm/stm32/axoloti/src/stm32_buttons.c deleted file mode 100644 index 2fc688a660c57..0000000000000 --- a/boards/arm/stm32/axoloti/src/stm32_buttons.c +++ /dev/null @@ -1,151 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/axoloti/src/stm32_buttons.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include -#include - -#include "stm32.h" -#include "axoloti.h" - -#ifdef CONFIG_ARCH_BUTTONS - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* Pin configuration for each axoloti button. This array is indexed by - * the BUTTON_* definitions in board.h - */ - -static const uint32_t g_buttons[NUM_BUTTONS] = -{ - GPIO_BTN_USER, -}; - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_button_initialize - * - * Description: - * board_button_initialize() must be called to initialize button resources. - * After that, board_buttons() may be called to collect the current state - * of all buttons or board_button_irq() may be called to register button - * interrupt handlers. - * - ****************************************************************************/ - -uint32_t board_button_initialize(void) -{ - int i; - - /* Configure the GPIO pins as inputs. - * EXTI interrupts are configured for all pins. - */ - - for (i = 0; i < NUM_BUTTONS; i++) - { - stm32_configgpio(g_buttons[i]); - } - - return NUM_BUTTONS; -} - -/**************************************************************************** - * Name: board_buttons - ****************************************************************************/ - -uint32_t board_buttons(void) -{ - uint32_t ret = 0; - int i; - - /* Check that state of each key */ - - for (i = 0; i < NUM_BUTTONS; i++) - { - /* A HI value means that the key is pressed. */ - - bool pressed = stm32_gpioread(g_buttons[i]); - - /* Accumulate the set of depressed (not released) keys */ - - if (pressed) - { - ret |= (1 << i); - } - } - - return ret; -} - -/**************************************************************************** - * Button support. - * - * Description: - * board_button_initialize() must be called to initialize button resources. - * After that, board_buttons() may be called to collect the current state - * of all buttons or board_button_irq() may be called to register button - * interrupt handlers. - * - * After board_button_initialize() has been called, board_buttons() may be - * called to collect the state of all buttons. board_buttons() returns an - * 32-bit bit set with each bit associated with a button. See the - * BUTTON_*_BIT definitions in board.h for the meaning of each bit. - * - * board_button_irq() may be called to register an interrupt handler that - * will be called when a button is depressed or released. The ID value is - * a button enumeration value that uniquely identifies a button resource. - * See the BUTTON_* definitions in board.h for the meaning of enumeration - * value. - * - ****************************************************************************/ - -#ifdef CONFIG_ARCH_IRQBUTTONS -int board_button_irq(int id, xcpt_t irqhandler, void *arg) -{ - int ret = -EINVAL; - - /* The following should be atomic */ - - if (id >= MIN_IRQBUTTON && id <= MAX_IRQBUTTON) - { - ret = - stm32_gpiosetevent(g_buttons[id], true, true, true, irqhandler, arg); - } - - return ret; -} -#endif -#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/stm32/axoloti/src/stm32_extmem.c b/boards/arm/stm32/axoloti/src/stm32_extmem.c deleted file mode 100644 index a1558ff885cd6..0000000000000 --- a/boards/arm/stm32/axoloti/src/stm32_extmem.c +++ /dev/null @@ -1,310 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/axoloti/src/stm32_extmem.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32.h" -#include "axoloti.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#ifndef CONFIG_STM32_FMC -#warning "FMC is not enabled" -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* Axoloti SDRAM GPIO configuration */ - -static const uint32_t g_sdram_config[] = -{ - /* Data lines */ - - GPIO_FMC_D0, GPIO_FMC_D1, GPIO_FMC_D2, GPIO_FMC_D3, - GPIO_FMC_D4, GPIO_FMC_D5, GPIO_FMC_D6, GPIO_FMC_D7, - GPIO_FMC_D8, GPIO_FMC_D9, GPIO_FMC_D10, GPIO_FMC_D11, - GPIO_FMC_D12, GPIO_FMC_D13, GPIO_FMC_D14, GPIO_FMC_D15, - - /* Address lines */ - - GPIO_FMC_A0, GPIO_FMC_A1, GPIO_FMC_A2, GPIO_FMC_A3, - GPIO_FMC_A4, GPIO_FMC_A5, GPIO_FMC_A6, GPIO_FMC_A7, - GPIO_FMC_A8, GPIO_FMC_A9, GPIO_FMC_A10, GPIO_FMC_A11, - GPIO_FMC_A12, - - /* Control lines */ - - GPIO_FMC_BA0, /* ba0 */ - GPIO_FMC_BA1, /* ba1 */ - GPIO_FMC_NBL0, /* ldqm */ - GPIO_FMC_NBL1, /* udqm */ - GPIO_FMC_SDCLK, /* clk */ - GPIO_FMC_SDCKE0_1, /* cke */ - GPIO_FMC_SDNWE_2, /* we */ - GPIO_FMC_SDNCAS, /* cas */ - GPIO_FMC_SDNRAS, /* ras */ - GPIO_FMC_SDNE0_1, /* cs0 */ - GPIO_FMC_SDNE1_2, /* cs1 */ -}; - -#define NUM_SDRAM_GPIOS (sizeof(g_sdram_config) / sizeof(uint32_t)) - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_sdram_memtest - * - * Description: - * Test the SDRAM. - * - ****************************************************************************/ - -#define RAND_A 22695477 -#define RAND_C 1 -#define TEST_ITERATIONS 16 - -int stm32_sdram_memtest(void *base, uint32_t size) -{ - volatile int iter; - volatile int i; - - /* Linear write with linear congruential generator values */ - - for (iter = 0; iter < TEST_ITERATIONS; iter++) - { - uint32_t x = iter; - - /* Write */ - - for (i = 0; i < size / 4; i++) - { - x = (RAND_A * x) + RAND_C; - ((volatile uint32_t *)base)[i] = x; - } - - /* Read/verify */ - - x = iter; - for (i = 0; i < size / 4; i++) - { - x = (RAND_A * x) + RAND_C; - if (((volatile uint32_t *)base)[i] != x) - { - return -1; - } - } - } - - /* Scattered byte write at linear congruential generator addresses */ - - for (iter = 0; iter < TEST_ITERATIONS; iter++) - { - uint32_t x = iter; - - /* Write */ - - for (i = 0; i < 1024 * 1024; i++) - { - x = (RAND_A * x) + RAND_C; - ((volatile uint8_t *)base)[x & (size - 1)] = (uint8_t) i; - } - - /* Read/verify */ - - x = iter; - for (i = 0; i < 1024 * 1024; i++) - { - x = (RAND_A * x) + RAND_C; - if (((volatile uint8_t *)base)[x & (size - 1)] != (uint8_t) i) - { - return -1; - } - } - } - - return OK; -} - -/**************************************************************************** - * Name: stm32_sdram_initialize - * - * Description: - * Called from stm32_bringup to initialize external SDRAM access. - * The Axoloti uses an Alliance Memory AS4C4M16SA SDRAM. - * - ****************************************************************************/ - -int stm32_sdram_initialize(void) -{ - uint32_t val; - int i; - - /* Configure SDRAM GPIOs */ - - for (i = 0; i < NUM_SDRAM_GPIOS; i++) - { - stm32_configgpio(g_sdram_config[i]); - } - - /* Enable the FMC */ - - stm32_fmc_enable(); - - /* Go through the SDRAM initialization steps per the reference manual. - * The sdclk period is set to 2 x hclk. That is: 168 /2 = 84 MHz - * This gives a clock period of about 11.9 ns - */ - - /* Step 1: - * Program the memory device features into the FMC_SDCRx register. The - * SDRAM clock frequency, RBURST and RPIPE must be programmed in the - * FMC_SDCR1 register. - */ - - val = FMC_SDCR_RPIPE_1 | /* rpipe = 1 hclk */ - FMC_SDCR_READBURST | /* read burst enabled */ - FMC_SDCR_SDCLK_2X | /* sdclk = 2 hclk */ - FMC_SDCR_CAS_LATENCY_2 | /* cas latency = 2 cycles */ - FMC_SDCR_NBANKS_4 | /* 4 internal banks */ - FMC_SDCR_WIDTH_16 | /* width = 16 bits */ - FMC_SDCR_ROWS_12 | /* numrows = 12 */ - FMC_SDCR_COLS_8; /* numcols = 8 bits */ - stm32_fmc_sdram_set_control(1, val); - - /* Step 2: - * Program the memory device timing into the FMC_SDTRx register. The - * TRP and TRC timings must be programmed in the FMC_SDTR1 register. - */ - - val = FMC_SDTR_TRCD(2) | /* ras to cas delay 21ns => 2x11.90ns */ - FMC_SDTR_TRP(2) | /* row precharge 21ns => 2x11.90ns */ - FMC_SDTR_TRC(6) | /* row cycle time 63ns => 6x11.9ns */ - FMC_SDTR_TRAS(4) | /* row active time 42ns = >4x11.9ns */ - FMC_SDTR_TWR(4) | /* write to precharge 42ns => 4x11.9ns */ - FMC_SDTR_TXSR(6) | /* exit self refresh 65ns => 6x11.9ns */ - FMC_SDTR_TMRD(2); /* load mode register to active 2 clks */ - stm32_fmc_sdram_set_timing(1, val); - - /* Step 3: - * Set MODE bits to ‘001’ and configure the Target Bank bits (CTB1 - * and/or CTB2) in the FMC_SDCMR register to start delivering the clock - * to the memory (SDCKE is driven high). - */ - - val = FMC_SDCMR_BANK_1 | FMC_SDCMR_CMD_CLK_ENABLE; - stm32_fmc_sdram_command(val); - - /* Step 4: - * Wait during the prescribed delay period. Typical delay is around 100 - * μs (refer to the SDRAM datasheet for the required delay after - * power-up). - */ - - nxsched_usleep(1000); - - /* Step 5: - * Set MODE bits to ‘010’ and configure the Target Bank bits (CTB1 - * and/or CTB2) in the FMC_SDCMR register to issue a “Precharge All” - * command. - */ - - val = FMC_SDCMR_BANK_1 | FMC_SDCMR_CMD_PALL; - stm32_fmc_sdram_command(val); - - /* Step 6: - * Set MODE bits to ‘011’, and configure the Target Bank bits (CTB1 - * and/or CTB2) as well as the number of consecutive Auto-refresh - * commands (NRFS) in the FMC_SDCMR register. Refer to the SDRAM - * datasheet for the number of Auto-refresh commands that should be - * issued. Typical number is 8. - */ - - val = FMC_SDCMR_NRFS(5) | FMC_SDCMR_BANK_1 | FMC_SDCMR_CMD_AUTO_REFRESH; - stm32_fmc_sdram_command(val); - - /* Step 7: - * Configure the MRD field according to your SDRAM device, set the MODE - * bits to '100', and configure the Target Bank bits (CTB1 and/or CTB2) - * in the FMC_SDCMR register to issue a "Load Mode Register" command in - * order to program the SDRAM. In particular: - * a) The CAS latency must be selected following configured value in - * FMC_SDCR1/2 registers - * b) The Burst Length (BL) of 1 must be selected by configuring the - * M[2:0] bits to 000 in the mode register (refer to the SDRAM - * datasheet). If the Mode Register is not the same for both SDRAM - * banks, this step has to be repeated twice, once for each bank, - * and the Target Bank bits set accordingly. - */ - - val = FMC_SDCMR_MDR_BURST_LENGTH_2 | - FMC_SDCMR_MDR_BURST_TYPE_SEQUENTIAL | - FMC_SDCMR_MDR_CAS_LATENCY_2 | - FMC_SDCMR_MDR_MODE_NORMAL | - FMC_SDCMR_MDR_WBL_SINGLE | FMC_SDCMR_BANK_1 | FMC_SDCMR_CMD_LOAD_MODE; - stm32_fmc_sdram_command(val); - - /* Step 8: - * Program the refresh rate in the FMC_SDRTR register - * The refresh rate corresponds to the delay between refresh cycles. Its - * value must be adapted to SDRAM devices. - */ - - stm32_fmc_sdram_set_refresh_rate(1292); /* (64ms/4096rows) x 84MHz) - 20 */ - - /* Step 9: - * For mobile SDRAM devices, to program the extended mode register it - * should be done once the SDRAM device is initialized: First, a dummy - * read access should be performed while BA1=1 and BA=0 (refer to SDRAM - * address mapping section for BA[1:0] address mapping) in order to select - * the extended mode register instead of Load mode register and then - * program the needed value. - */ - - /* Setting EMRS is optional and we're not bothering ... */ - - /* Enable memory writes for bank 1 */ - - stm32_fmc_sdram_write_protect(1, false); - - /* Wait for the controller to be ready */ - - stm32_fmc_sdram_wait(); - return OK; -} diff --git a/boards/arm/stm32/axoloti/src/stm32_sdio.c b/boards/arm/stm32/axoloti/src/stm32_sdio.c deleted file mode 100644 index 58b957bc57ae6..0000000000000 --- a/boards/arm/stm32/axoloti/src/stm32_sdio.c +++ /dev/null @@ -1,156 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/axoloti/src/stm32_sdio.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include - -#include -#include - -#include "stm32.h" -#include "axoloti.h" - -#ifdef HAVE_SDIO - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Card detections requires card support and a card detection GPIO */ - -#define HAVE_NCD 1 -#if !defined(HAVE_SDIO) || !defined(GPIO_SDIO_NCD) -#undef HAVE_NCD -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -static struct sdio_dev_s *g_sdio_dev; -#ifdef HAVE_NCD -static bool g_sd_inserted; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_ncd_interrupt - * - * Description: - * Card detect interrupt handler. - * - ****************************************************************************/ - -#ifdef HAVE_NCD -static int stm32_ncd_interrupt(int irq, void *context, void *arg) -{ - bool present; - - present = !stm32_gpioread(GPIO_SDIO_NCD); - if (present != g_sd_inserted) - { - sdio_mediachange(g_sdio_dev, present); - g_sd_inserted = present; - } - - return OK; -} -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_sdio_initialize - * - * Description: - * Initialize SDIO-based MMC/SD card support - * - ****************************************************************************/ - -int stm32_sdio_initialize(void) -{ - int ret; - -#ifdef HAVE_NCD - /* Configure the card detect GPIO */ - - stm32_configgpio(GPIO_SDIO_NCD); - - /* Register an interrupt handler for the card detect pin */ - - stm32_gpiosetevent(GPIO_SDIO_NCD, true, true, true, - stm32_ncd_interrupt, NULL); -#endif - - /* Mount the SDIO-based MMC/SD block driver. - * First, get an instance of the SDIO interface - */ - - finfo("Initializing SDIO slot %d\n", SDIO_SLOTNO); - g_sdio_dev = sdio_initialize(SDIO_SLOTNO); - if (!g_sdio_dev) - { - ferr("ERROR: Failed to initialize SDIO slot %d\n", SDIO_SLOTNO); - return -ENODEV; - } - - /* Now bind the SDIO interface to the MMC/SD driver */ - - finfo("Bind SDIO to the MMC/SD driver, minor=%d\n", SDIO_MINOR); - ret = mmcsd_slotinitialize(SDIO_MINOR, g_sdio_dev); - if (ret != OK) - { - ferr("ERROR: Failed to bind SDIO to the MMC/SD driver: %d\n", ret); - return ret; - } - - finfo("Successfully bound SDIO to the MMC/SD driver\n"); - -#ifdef HAVE_NCD - /* Use SD card detect pin to check if a card is g_sd_inserted */ - - g_sd_inserted = !stm32_gpioread(GPIO_SDIO_NCD); - finfo("Card detect : %d\n", g_sd_inserted); - sdio_mediachange(g_sdio_dev, g_sd_inserted); -#else - /* Assume that the SD card is inserted. What choice do we have? */ - - sdio_mediachange(g_sdio_dev, true); -#endif - - return OK; -} - -#endif /* HAVE_SDIO */ diff --git a/boards/arm/stm32/axoloti/src/stm32_usbhost.c b/boards/arm/stm32/axoloti/src/stm32_usbhost.c deleted file mode 100644 index c4b42ffc54aca..0000000000000 --- a/boards/arm/stm32/axoloti/src/stm32_usbhost.c +++ /dev/null @@ -1,265 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/axoloti/src/stm32_usbhost.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -#include "arm_internal.h" -#include "stm32.h" -#include "stm32_otghs.h" -#include "axoloti.h" - -#ifdef CONFIG_STM32_OTGHS - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#if defined(CONFIG_USBDEV) || defined(CONFIG_USBHOST) -#define HAVE_USB 1 -#else -#warning "CONFIG_STM32_OTGHS is enabled but neither CONFIG_USBDEV nor CONFIG_USBHOST" -#undef HAVE_USB -#endif - -#ifndef CONFIG_AXOLOTI_USBHOST_PRIO -#define CONFIG_AXOLOTI_USBHOST_PRIO 100 -#endif - -#ifndef CONFIG_AXOLOTI_USBHOST_STACKSIZE -#define CONFIG_AXOLOTI_USBHOST_STACKSIZE 1024 -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -#ifdef CONFIG_USBHOST -static struct usbhost_connection_s *g_usbconn; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: usbhost_waiter - * - * Description: - * Wait for USB devices to be connected. - * - ****************************************************************************/ - -#ifdef CONFIG_USBHOST -static int usbhost_waiter(int argc, char *argv[]) -{ - struct usbhost_hubport_s *hport; - uinfo("Running\n"); - - for (; ; ) - { - /* Wait for the device to change state */ - - DEBUGVERIFY(CONN_WAIT(g_usbconn, &hport)); - uinfo("%s\n", hport->connected ? "connected" : "disconnected"); - - /* Did we just become connected? */ - - if (hport->connected) - { - /* Yes.. enumerate the newly connected device */ - - CONN_ENUMERATE(g_usbconn, hport); - } - } - - /* Keep the compiler from complaining */ - - return 0; -} -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_usbinitialize - * - * Description: - * Called from stm32_usbinitialize very early in initialization to setup - * USB-related GPIO pins for the Axoloti board. - * - ****************************************************************************/ - -void stm32_usbinitialize(void) -{ -#ifdef CONFIG_STM32_OTGHS - stm32_configgpio(GPIO_OTGHS_PWRON); - stm32_configgpio(GPIO_OTGHS_OVER); -#endif -} - -/**************************************************************************** - * Name: stm32_usbhost_vbusdrive - * - * Description: - * Enable/disable driving of VBUS 5V output. This function must be provided - * be each platform that implements the STM32 OTG HS host interface - * - * Input Parameters: - * iface - For future growth to handle multiple USB host interface. Should - * be zero. - * enable - true: enable VBUS power; false: disable VBUS power - * - ****************************************************************************/ - -#ifdef CONFIG_USBHOST -void stm32_usbhost_vbusdrive(int iface, bool enable) -{ - DEBUGASSERT(iface == 0); - if (enable) - { - /* Enable the Power Switch by driving the enable pin low */ - - stm32_gpiowrite(GPIO_OTGHS_PWRON, false); - } - else - { - /* Disable the Power Switch by driving the enable pin high */ - - stm32_gpiowrite(GPIO_OTGHS_PWRON, true); - } -} -#endif - -/**************************************************************************** - * Name: stm32_setup_overcurrent - * - * Description: - * Setup to receive an interrupt-level callback if an overcurrent condition - * is detected. - * - * Input Parameters: - * handler - New overcurrent interrupt handler - * arg - The argument provided for the interrupt handler - * - * Returned Value: - * Zero (OK) is returned on success. Otherwise, a negated errno value is - * returned to indicate the nature of the failure. - * - ****************************************************************************/ - -#ifdef CONFIG_USBHOST -int stm32_setup_overcurrent(xcpt_t handler, void *arg) -{ - return stm32_gpiosetevent(GPIO_OTGHS_OVER, true, true, true, handler, arg); -} -#endif - -/**************************************************************************** - * Name: stm32_usbhost_initialize - * - * Description: - * Called at application startup time to initialize the USB host - * functionality. This function will start a thread that will monitor for - * device connection/disconnection events. - * - ****************************************************************************/ - -#ifdef CONFIG_USBHOST -int stm32_usbhost_initialize(void) -{ - int ret; - - /* First, register all of the class drivers needed to support the drivers - * that we care about: - */ - - uinfo("Register class drivers\n"); - -#ifdef CONFIG_USBHOST_MSC - /* Register the USB mass storage class class */ - - ret = usbhost_msc_initialize(); - if (ret != OK) - { - uerr("ERROR: Failed to register the mass storage class: %d\n", ret); - } -#endif - -#ifdef CONFIG_USBHOST_HIDKBD - /* Initialize the HID keyboard class */ - - ret = usbhost_kbdinit(); - if (ret != OK) - { - uerr("ERROR: Failed to register the HID keyboard class\n"); - } -#endif - -#ifdef CONFIG_USBHOST_HIDMOUSE - /* Initialize the HID mouse class */ - - ret = usbhost_mouse_init(); - if (ret != OK) - { - uerr("ERROR: Failed to register the HID mouse class\n"); - } -#endif - - /* Then get an instance of the USB host interface */ - - uinfo("Initialize USB host\n"); - g_usbconn = stm32_otghshost_initialize(0); - if (g_usbconn) - { - /* Start a thread to handle device connection. */ - - uinfo("Start usbhost_waiter\n"); - ret = kthread_create("usbhost", CONFIG_AXOLOTI_USBHOST_PRIO, - CONFIG_AXOLOTI_USBHOST_STACKSIZE, - usbhost_waiter, NULL); - return ret < 0 ? -ENOEXEC : OK; - } - - return -ENODEV; -} -#endif - -#endif /* CONFIG_STM32_OTGHS */ diff --git a/boards/arm/stm32/axoloti/src/stm32_userleds.c b/boards/arm/stm32/axoloti/src/stm32_userleds.c deleted file mode 100644 index c1aae2069041d..0000000000000 --- a/boards/arm/stm32/axoloti/src/stm32_userleds.c +++ /dev/null @@ -1,93 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/axoloti/src/stm32_userleds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32.h" -#include "axoloti.h" - -#ifndef CONFIG_ARCH_LEDS - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* This array maps an LED number to GPIO pin configuration */ - -static uint32_t g_ledcfg[BOARD_NLEDS] = -{ - GPIO_LED1, GPIO_LED2, -}; - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_userled_initialize - ****************************************************************************/ - -uint32_t board_userled_initialize(void) -{ - /* Configure LED1-2 GPIOs for output */ - - stm32_configgpio(GPIO_LED1); - stm32_configgpio(GPIO_LED2); - return BOARD_NLEDS; -} - -/**************************************************************************** - * Name: board_userled - ****************************************************************************/ - -void board_userled(int led, bool ledon) -{ - if ((unsigned)led < BOARD_NLEDS) - { - stm32_gpiowrite(g_ledcfg[led], ledon); - } -} - -/**************************************************************************** - * Name: board_userled_all - ****************************************************************************/ - -void board_userled_all(uint32_t ledset) -{ - stm32_gpiowrite(GPIO_LED1, (ledset & BOARD_LED1_BIT) == 0); - stm32_gpiowrite(GPIO_LED2, (ledset & BOARD_LED2_BIT) == 0); -} - -#endif /* !CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/b-g431b-esc1/CMakeLists.txt b/boards/arm/stm32/b-g431b-esc1/CMakeLists.txt deleted file mode 100644 index 8651bd8562263..0000000000000 --- a/boards/arm/stm32/b-g431b-esc1/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/b-g431b-esc1/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32/b-g431b-esc1/configs/can/defconfig b/boards/arm/stm32/b-g431b-esc1/configs/can/defconfig deleted file mode 100644 index 43dc0f4143a21..0000000000000 --- a/boards/arm/stm32/b-g431b-esc1/configs/can/defconfig +++ /dev/null @@ -1,53 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -# CONFIG_NSH_DISABLE_IFCONFIG is not set -# CONFIG_NSH_DISABLE_PS is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="b-g431b-esc1" -CONFIG_ARCH_BOARD_B_G431B_ESC1=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32G431C=y -CONFIG_ARCH_INTERRUPTSTACK=2048 -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=8499 -CONFIG_BOARD_STM32_BG431BESC1_USE_HSE=y -CONFIG_BUILTIN=y -CONFIG_CAN_ERRORS=y -CONFIG_CAN_EXTID=y -CONFIG_DEBUG_FULLOPT=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_EXAMPLES_CAN=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=22528 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=14 -CONFIG_START_MONTH=10 -CONFIG_START_YEAR=2014 -CONFIG_STM32_FDCAN1=y -CONFIG_STM32_FDCAN1_BITRATE=250000 -CONFIG_STM32_FDCAN1_NTSEG1=23 -CONFIG_STM32_FDCAN1_NTSEG2=8 -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_USART2=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/b-g431b-esc1/configs/cansock/defconfig b/boards/arm/stm32/b-g431b-esc1/configs/cansock/defconfig deleted file mode 100644 index ba24fe7e2fe9a..0000000000000 --- a/boards/arm/stm32/b-g431b-esc1/configs/cansock/defconfig +++ /dev/null @@ -1,61 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_NET_ETHERNET is not set -# CONFIG_NET_IPv4 is not set -CONFIG_ALLOW_BSD_COMPONENTS=y -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="b-g431b-esc1" -CONFIG_ARCH_BOARD_B_G431B_ESC1=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32G431C=y -CONFIG_ARCH_INTERRUPTSTACK=1024 -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=8499 -CONFIG_BOARD_STM32_BG431BESC1_USE_HSE=y -CONFIG_BUILTIN=y -CONFIG_CANUTILS_CANDUMP=y -CONFIG_CANUTILS_CANSEND=y -CONFIG_CANUTILS_LIBCANUTILS=y -CONFIG_DEBUG_FULLOPT=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_FS_PROCFS=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_IOB_BUFSIZE=128 -CONFIG_IOB_NBUFFERS=10 -CONFIG_LINE_MAX=64 -CONFIG_NET=y -CONFIG_NETDEV_IFINDEX=y -CONFIG_NETDEV_LATEINIT=y -CONFIG_NET_CAN=y -CONFIG_NET_SOCKOPTS=y -CONFIG_NET_STATISTICS=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_RAM_SIZE=22528 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_LPWORK=y -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=14 -CONFIG_START_MONTH=10 -CONFIG_START_YEAR=2014 -CONFIG_STM32_FDCAN1=y -CONFIG_STM32_FDCAN1_BITRATE=250000 -CONFIG_STM32_FDCAN1_NTSEG1=23 -CONFIG_STM32_FDCAN1_NTSEG2=8 -CONFIG_STM32_FDCAN_SOCKET=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_USART2=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/b-g431b-esc1/configs/foc_b16/defconfig b/boards/arm/stm32/b-g431b-esc1/configs/foc_b16/defconfig deleted file mode 100644 index a8d73452d001e..0000000000000 --- a/boards/arm/stm32/b-g431b-esc1/configs/foc_b16/defconfig +++ /dev/null @@ -1,87 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_DISABLE_MQUEUE is not set -# CONFIG_DISABLE_PTHREAD is not set -CONFIG_ADC=y -CONFIG_ADC_FIFOSIZE=3 -CONFIG_ANALOG=y -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="b-g431b-esc1" -CONFIG_ARCH_BOARD_B_G431B_ESC1=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32G431C=y -CONFIG_ARCH_INTERRUPTSTACK=1024 -CONFIG_ARCH_IRQBUTTONS=y -CONFIG_ARMV7M_LIBM=y -CONFIG_BOARDCTL=y -CONFIG_BOARD_LOOPSPERMSEC=8499 -CONFIG_BOARD_STM32_BG431BESC1_FOC_POT=y -CONFIG_BOARD_STM32_BG431BESC1_FOC_VBUS=y -CONFIG_BUILTIN=y -CONFIG_DEBUG_FULLOPT=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_DEFAULT_SMALL=y -CONFIG_DEFAULT_TASK_STACKSIZE=1024 -CONFIG_EXAMPLES_FOC=y -CONFIG_EXAMPLES_FOC_ADC_MAX=4095 -CONFIG_EXAMPLES_FOC_ADC_VREF=3300 -CONFIG_EXAMPLES_FOC_CONTROL_STACKSIZE=2048 -CONFIG_EXAMPLES_FOC_FIXED16_INST=1 -CONFIG_EXAMPLES_FOC_HAVE_BUTTON=y -CONFIG_EXAMPLES_FOC_NOTIFIER_FREQ=10000 -CONFIG_EXAMPLES_FOC_PWM_FREQ=20000 -CONFIG_EXAMPLES_FOC_RAMP_ACC=200000 -CONFIG_EXAMPLES_FOC_RAMP_DEC=200000 -CONFIG_EXAMPLES_FOC_RAMP_THR=10000 -CONFIG_EXAMPLES_FOC_SETPOINT_ADC=y -CONFIG_EXAMPLES_FOC_VBUS_ADC=y -CONFIG_EXAMPLES_FOC_VBUS_SCALE=10400 -CONFIG_INDUSTRY_FOC=y -CONFIG_INDUSTRY_FOC_FIXED16=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INPUT=y -CONFIG_INPUT_BUTTONS=y -CONFIG_INPUT_BUTTONS_LOWER=y -CONFIG_INTELHEX_BINARY=y -CONFIG_LIBM=y -CONFIG_MOTOR=y -CONFIG_MOTOR_FOC=y -CONFIG_MOTOR_FOC_SHUNTS=2 -CONFIG_MQ_MAXMSGSIZE=5 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_RAM_SIZE=22528 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=14 -CONFIG_START_MONTH=10 -CONFIG_START_YEAR=2014 -CONFIG_STM32_ADC1_ANIOC_TRIGGER=1 -CONFIG_STM32_ADC1_DMA=y -CONFIG_STM32_ADC1_DMA_CFG=1 -CONFIG_STM32_ADC1_INJECTED_CHAN=3 -CONFIG_STM32_DMA1=y -CONFIG_STM32_DMA2=y -CONFIG_STM32_DMAMUX1=y -CONFIG_STM32_FOC=y -CONFIG_STM32_FOC_FOC0=y -CONFIG_STM32_FOC_G4_ADCCHAN0_WORKAROUND=y -CONFIG_STM32_FOC_HAS_PWM_COMPLEMENTARY=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_TIM1_CH1MODE=0 -CONFIG_STM32_TIM1_CH2MODE=0 -CONFIG_STM32_TIM1_CH3MODE=0 -CONFIG_STM32_TIM1_MODE=2 -CONFIG_STM32_USART2=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART2_SERIAL_CONSOLE=y -CONFIG_USART2_TXDMA=y diff --git a/boards/arm/stm32/b-g431b-esc1/configs/foc_f32/defconfig b/boards/arm/stm32/b-g431b-esc1/configs/foc_f32/defconfig deleted file mode 100644 index 2dd0555c613ff..0000000000000 --- a/boards/arm/stm32/b-g431b-esc1/configs/foc_f32/defconfig +++ /dev/null @@ -1,88 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_DISABLE_MQUEUE is not set -# CONFIG_DISABLE_PTHREAD is not set -CONFIG_ADC=y -CONFIG_ADC_FIFOSIZE=3 -CONFIG_ANALOG=y -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="b-g431b-esc1" -CONFIG_ARCH_BOARD_B_G431B_ESC1=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32G431C=y -CONFIG_ARCH_INTERRUPTSTACK=1024 -CONFIG_ARCH_IRQBUTTONS=y -CONFIG_ARMV7M_LIBM=y -CONFIG_BOARDCTL=y -CONFIG_BOARD_LOOPSPERMSEC=8499 -CONFIG_BOARD_STM32_BG431BESC1_FOC_POT=y -CONFIG_BOARD_STM32_BG431BESC1_FOC_VBUS=y -CONFIG_BUILTIN=y -CONFIG_DEBUG_FULLOPT=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_DEFAULT_SMALL=y -CONFIG_DEFAULT_TASK_STACKSIZE=1024 -CONFIG_EXAMPLES_FOC=y -CONFIG_EXAMPLES_FOC_ADC_MAX=4095 -CONFIG_EXAMPLES_FOC_ADC_VREF=3300 -CONFIG_EXAMPLES_FOC_CONTROL_STACKSIZE=2048 -CONFIG_EXAMPLES_FOC_FLOAT_INST=1 -CONFIG_EXAMPLES_FOC_HAVE_BUTTON=y -CONFIG_EXAMPLES_FOC_NOTIFIER_FREQ=10000 -CONFIG_EXAMPLES_FOC_PWM_FREQ=20000 -CONFIG_EXAMPLES_FOC_RAMP_ACC=200000 -CONFIG_EXAMPLES_FOC_RAMP_DEC=200000 -CONFIG_EXAMPLES_FOC_RAMP_THR=10000 -CONFIG_EXAMPLES_FOC_SETPOINT_ADC=y -CONFIG_EXAMPLES_FOC_VBUS_ADC=y -CONFIG_EXAMPLES_FOC_VBUS_SCALE=10400 -CONFIG_INDUSTRY_FOC=y -CONFIG_INDUSTRY_FOC_FLOAT=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INPUT=y -CONFIG_INPUT_BUTTONS=y -CONFIG_INPUT_BUTTONS_LOWER=y -CONFIG_INTELHEX_BINARY=y -CONFIG_LIBC_FLOATINGPOINT=y -CONFIG_LIBM=y -CONFIG_MOTOR=y -CONFIG_MOTOR_FOC=y -CONFIG_MOTOR_FOC_SHUNTS=2 -CONFIG_MQ_MAXMSGSIZE=5 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_RAM_SIZE=22528 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=14 -CONFIG_START_MONTH=10 -CONFIG_START_YEAR=2014 -CONFIG_STM32_ADC1_ANIOC_TRIGGER=1 -CONFIG_STM32_ADC1_DMA=y -CONFIG_STM32_ADC1_DMA_CFG=1 -CONFIG_STM32_ADC1_INJECTED_CHAN=3 -CONFIG_STM32_DMA1=y -CONFIG_STM32_DMA2=y -CONFIG_STM32_DMAMUX1=y -CONFIG_STM32_FOC=y -CONFIG_STM32_FOC_FOC0=y -CONFIG_STM32_FOC_G4_ADCCHAN0_WORKAROUND=y -CONFIG_STM32_FOC_HAS_PWM_COMPLEMENTARY=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_TIM1_CH1MODE=0 -CONFIG_STM32_TIM1_CH2MODE=0 -CONFIG_STM32_TIM1_CH3MODE=0 -CONFIG_STM32_TIM1_MODE=2 -CONFIG_STM32_USART2=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART2_SERIAL_CONSOLE=y -CONFIG_USART2_TXDMA=y diff --git a/boards/arm/stm32/b-g431b-esc1/configs/nsh/defconfig b/boards/arm/stm32/b-g431b-esc1/configs/nsh/defconfig deleted file mode 100644 index 7008df0865512..0000000000000 --- a/boards/arm/stm32/b-g431b-esc1/configs/nsh/defconfig +++ /dev/null @@ -1,48 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -# CONFIG_NSH_DISABLE_IFCONFIG is not set -# CONFIG_NSH_DISABLE_PS is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="b-g431b-esc1" -CONFIG_ARCH_BOARD_B_G431B_ESC1=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32G431C=y -CONFIG_ARCH_INTERRUPTSTACK=2048 -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=8499 -CONFIG_BUILTIN=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_LTO_FULL=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=22528 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=14 -CONFIG_START_MONTH=10 -CONFIG_START_YEAR=2014 -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_USART2=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_TESTING_OSTEST=y -CONFIG_TESTING_OSTEST_STACKSIZE=1024 -CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/b-g431b-esc1/include/board.h b/boards/arm/stm32/b-g431b-esc1/include/board.h deleted file mode 100644 index f5568827ce88d..0000000000000 --- a/boards/arm/stm32/b-g431b-esc1/include/board.h +++ /dev/null @@ -1,380 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/b-g431b-esc1/include/board.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __BOARDS_ARM_STM32_B_G431B_ESC1_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32_B_G431B_ESC1_INCLUDE_BOARD_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Clocking *****************************************************************/ - -#define STM32_BOARD_XTAL 8000000 /* 8MHz */ - -#define STM32_HSI_FREQUENCY 16000000ul /* 16MHz */ -#define STM32_LSI_FREQUENCY 32000 /* 32kHz */ -#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL /* Y2 on board */ -#undef STM32_LSE_FREQUENCY /* Not available on this board */ - -#ifdef CONFIG_BOARD_STM32_BG431BESC1_USE_HSI - -/* Main PLL Configuration. - * - * PLL source is HSI = 16MHz - * PLLN = 85, PLLM = 4, PLLP = 10, PLLQ = 2, PLLR = 2 - * - * f(VCO Clock) = f(PLL Clock Input) x (PLLN / PLLM) - * f(PLL_P) = f(VCO Clock) / PLLP - * f(PLL_Q) = f(VCO Clock) / PLLQ - * f(PLL_R) = f(VCO Clock) / PLLR - * - * Where: - * 8 <= PLLN <= 127 - * 1 <= PLLM <= 16 - * PLLP = 2 through 31 - * PLLQ = 2, 4, 6, or 8 - * PLLR = 2, 4, 6, or 8 - * - * Do not exceed 170MHz on f(PLL_P), f(PLL_Q), or f(PLL_R). - * 64MHz <= f(VCO Clock) <= 344MHz. - * - * Given the above: - * - * f(VCO Clock) = HSI x PLLN / PLLM - * = 16MHz x 85 / 4 - * = 340MHz - * - * PLLPCLK = f(VCO Clock) / PLLP - * = 340MHz / 10 - * = 34MHz - * (May be used for ADC) - * - * PLLQCLK = f(VCO Clock) / PLLQ - * = 340MHz / 2 - * = 170MHz - * (May be used for QUADSPI, FDCAN, SAI1, I2S3. If set to - * 48MHz, may be used for USB, RNG.) - * - * PLLRCLK = f(VCO Clock) / PLLR - * = 340MHz / 2 - * = 170MHz - * (May be used for SYSCLK and most peripherals.) - */ - -#define STM32_PLLCFGR_PLLSRC RCC_PLLCFGR_PLLSRC_HSI -#define STM32_PLLCFGR_PLLCFG (RCC_PLLCFGR_PLLPEN | \ - RCC_PLLCFGR_PLLQEN | \ - RCC_PLLCFGR_PLLREN) - -#define STM32_PLLCFGR_PLLN RCC_PLLCFGR_PLLN(85) -#define STM32_PLLCFGR_PLLM RCC_PLLCFGR_PLLM(4) -#define STM32_PLLCFGR_PLLP RCC_PLLCFGR_PLLPDIV(10) -#define STM32_PLLCFGR_PLLQ RCC_PLLCFGR_PLLQ_2 -#define STM32_PLLCFGR_PLLR RCC_PLLCFGR_PLLR_2 - -#define STM32_VCO_FREQUENCY ((STM32_HSI_FREQUENCY / 4) * 85) -#define STM32_PLLP_FREQUENCY (STM32_VCO_FREQUENCY / 10) -#define STM32_PLLQ_FREQUENCY (STM32_VCO_FREQUENCY / 2) -#define STM32_PLLR_FREQUENCY (STM32_VCO_FREQUENCY / 2) - -/* Use the PLL and set the SYSCLK source to be PLLR (170MHz) */ - -#define STM32_SYSCLK_SW RCC_CFGR_SW_PLL -#define STM32_SYSCLK_SWS RCC_CFGR_SWS_PLL -#define STM32_SYSCLK_FREQUENCY STM32_PLLR_FREQUENCY - -/* AHB clock (HCLK) is SYSCLK (170MHz) */ - -#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK -#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY - -/* APB1 clock (PCLK1) is HCLK (170MHz) */ - -#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK -#define STM32_PCLK1_FREQUENCY STM32_HCLK_FREQUENCY - -/* APB2 clock (PCLK2) is HCLK (170MHz) */ - -#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK -#define STM32_PCLK2_FREQUENCY STM32_HCLK_FREQUENCY - -#endif /* CONFIG_BOARD_STM32_BG431BESC1_USE_HSI */ - -#ifdef CONFIG_BOARD_STM32_BG431BESC1_USE_HSE - -/* Main PLL Configuration. - * - * PLL source is HSE = 8MHz - * PLLN = 85, PLLM = 2, PLLP = 10, PLLQ = 2, PLLR = 2 - * - * f(VCO Clock) = f(PLL Clock Input) x (PLLN / PLLM) - * f(PLL_P) = f(VCO Clock) / PLLP - * f(PLL_Q) = f(VCO Clock) / PLLQ - * f(PLL_R) = f(VCO Clock) / PLLR - * - * Where: - * 8 <= PLLN <= 127 - * 1 <= PLLM <= 16 - * PLLP = 2 through 31 - * PLLQ = 2, 4, 6, or 8 - * PLLR = 2, 4, 6, or 8 - * - * Do not exceed 170MHz on f(PLL_P), f(PLL_Q), or f(PLL_R). - * 64MHz <= f(VCO Clock) <= 344MHz. - * - * Given the above: - * - * f(VCO Clock) = HSI x PLLN / PLLM - * = 8MHz x 85 / 2 - * = 340MHz - * - * PLLPCLK = f(VCO Clock) / PLLP - * = 340MHz / 10 - * = 34MHz - * (May be used for ADC) - * - * PLLQCLK = f(VCO Clock) / PLLQ - * = 340MHz / 2 - * = 170MHz - * (May be used for QUADSPI, FDCAN, SAI1, I2S3. If set to - * 48MHz, may be used for USB, RNG.) - * - * PLLRCLK = f(VCO Clock) / PLLR - * = 340MHz / 2 - * = 170MHz - * (May be used for SYSCLK and most peripherals.) - */ - -#define STM32_PLLCFGR_PLLSRC RCC_PLLCFGR_PLLSRC_HSE -#define STM32_PLLCFGR_PLLCFG (RCC_PLLCFGR_PLLPEN | \ - RCC_PLLCFGR_PLLQEN | \ - RCC_PLLCFGR_PLLREN) - -#define STM32_PLLCFGR_PLLN RCC_PLLCFGR_PLLN(85) -#define STM32_PLLCFGR_PLLM RCC_PLLCFGR_PLLM(2) -#define STM32_PLLCFGR_PLLP RCC_PLLCFGR_PLLPDIV(10) -#define STM32_PLLCFGR_PLLQ RCC_PLLCFGR_PLLQ_2 -#define STM32_PLLCFGR_PLLR RCC_PLLCFGR_PLLR_2 - -#define STM32_VCO_FREQUENCY ((STM32_HSI_FREQUENCY / 4) * 85) -#define STM32_PLLP_FREQUENCY (STM32_VCO_FREQUENCY / 10) -#define STM32_PLLQ_FREQUENCY (STM32_VCO_FREQUENCY / 2) -#define STM32_PLLR_FREQUENCY (STM32_VCO_FREQUENCY / 2) - -/* Use the PLL and set the SYSCLK source to be PLLR (170MHz) */ - -#define STM32_SYSCLK_SW RCC_CFGR_SW_PLL -#define STM32_SYSCLK_SWS RCC_CFGR_SWS_PLL -#define STM32_SYSCLK_FREQUENCY STM32_PLLR_FREQUENCY - -/* AHB clock (HCLK) is SYSCLK (170MHz) */ - -#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK -#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY - -/* APB1 clock (PCLK1) is HCLK (170MHz) */ - -#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK -#define STM32_PCLK1_FREQUENCY STM32_HCLK_FREQUENCY - -/* APB2 clock (PCLK2) is HCLK (170MHz) */ - -#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK -#define STM32_PCLK2_FREQUENCY STM32_HCLK_FREQUENCY - -#endif /* CONFIG_BOARD_STM32_BG431BESC1_USE_HSE */ - -/* APB2 timers 1, 8, 20 and 15-17 will receive PCLK2. */ - -/* Timers driven from APB2 will be PCLK2 */ - -#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB1_TIM15_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB1_TIM16_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB1_TIM17_CLKIN (STM32_PCLK2_FREQUENCY) - -/* APB1 timers 2-7 will be twice PCLK1 */ - -#define STM32_APB1_TIM2_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM4_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (STM32_PCLK1_FREQUENCY) - -/* USB divider -- Divide PLL clock by 1.5 */ - -#define STM32_CFGR_USBPRE 0 - -/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx - * otherwise frequency is 2xAPBx. - */ - -#define BOARD_TIM1_FREQUENCY (STM32_PCLK2_FREQUENCY) -#define BOARD_TIM2_FREQUENCY (STM32_PCLK1_FREQUENCY) -#define BOARD_TIM3_FREQUENCY (STM32_PCLK1_FREQUENCY) -#define BOARD_TIM4_FREQUENCY (STM32_PCLK1_FREQUENCY) -#define BOARD_TIM5_FREQUENCY (STM32_PCLK1_FREQUENCY) -#define BOARD_TIM6_FREQUENCY (STM32_PCLK1_FREQUENCY) -#define BOARD_TIM7_FREQUENCY (STM32_PCLK1_FREQUENCY) -#define BOARD_TIM8_FREQUENCY (STM32_PCLK2_FREQUENCY) -#define BOARD_TIM15_FREQUENCY (STM32_PCLK2_FREQUENCY) -#define BOARD_TIM16_FREQUENCY (STM32_PCLK2_FREQUENCY) -#define BOARD_TIM17_FREQUENCY (STM32_PCLK2_FREQUENCY) -#define BOARD_TIM20_FREQUENCY (STM32_PCLK2_FREQUENCY) - -#ifdef CONFIG_STM32_FDCAN -# ifdef CONFIG_BOARD_STM32_BG431BESC1_USE_HSE -# define STM32_CCIPR_FDCANSRC (RCC_CCIPR_FDCANSEL_HSE) -# define STM32_FDCAN_FREQUENCY (STM32_HSE_FREQUENCY) -# else -# error For now FDCAN supported only if HSE enabled -# endif -#endif - -/* LED definitions **********************************************************/ - -/* The B-G431B-ESC1 has four user LEDs. - * - * If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs in - * any way. The following definitions are used to access individual LEDs. - */ - -/* LED index values for use with board_userled() */ - -#define BOARD_LED1 0 /* User LD2 */ -#define BOARD_NLEDS 1 - -/* LED bits for use with board_userled_all() */ - -#define BOARD_LED1_BIT (1 << BOARD_LED1) - -/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the LED on board - * the Nucleo G431RB. The following definitions describe how NuttX controls - * the LED: - * - * SYMBOL Meaning LED1 state - * ------------------ ----------------------- ---------- - * LED_STARTED NuttX has been started OFF - * LED_HEAPALLOCATE Heap has been allocated OFF - * LED_IRQSENABLED Interrupts enabled OFF - * LED_STACKCREATED Idle stack created ON - * LED_INIRQ In an interrupt No change - * LED_SIGNAL In a signal handler No change - * LED_ASSERTION An assertion failed No change - * LED_PANIC The system has crashed Blinking - * LED_IDLE STM32 is in sleep mode Not used - */ - -#define LED_STARTED 0 -#define LED_HEAPALLOCATE 0 -#define LED_IRQSENABLED 0 -#define LED_STACKCREATED 1 -#define LED_INIRQ 2 -#define LED_SIGNAL 2 -#define LED_ASSERTION 2 -#define LED_PANIC 1 - -/* Button definitions *******************************************************/ - -/* The B-G431B-ESC supports one buttons controllabe by software: - * - * B1 USER: user button connected to the I/O PC10. - */ - -#define BUTTON_USER 0 -#define NUM_BUTTONS 1 - -#define BUTTON_USER_BIT (1 << BUTTON_USER) - -/* Alternate function pin selections ****************************************/ - -/* ADC1 */ - -#define GPIO_ADC1_IN1 GPIO_ADC1_IN1_0 /* PA0 */ -#define GPIO_ADC1_IN2 GPIO_ADC1_IN2_0 /* PA1 */ -#define GPIO_ADC1_IN3 GPIO_ADC1_IN3_0 /* PA2 */ -#define GPIO_ADC1_IN4 GPIO_ADC1_IN4_0 /* PA3 */ -#define GPIO_ADC1_IN5 GPIO_ADC1_IN5_0 /* PB14 */ -#define GPIO_ADC1_IN10 GPIO_ADC1_IN10_0 /* PF0 */ -#define GPIO_ADC1_IN11 GPIO_ADC1_IN11_0 /* PB12 */ -#define GPIO_ADC1_IN12 GPIO_ADC1_IN12_0 /* PB1 */ -#define GPIO_ADC1_IN14 GPIO_ADC1_IN14_0 /* PB11 */ -#define GPIO_ADC1_IN15 GPIO_ADC1_IN15_0 /* PB0 */ - -/* USART2 (ST LINK Virtual Console and J3 pads) */ - -#define GPIO_USART2_TX GPIO_USART2_TX_3 /* PB3 */ -#define GPIO_USART2_RX GPIO_USART2_RX_3 /* PB4 */ - -/* TIM1 configuration *******************************************************/ - -#define GPIO_TIM1_CH1OUT (GPIO_TIM1_CH1OUT_0 | GPIO_SPEED_50MHz) /* TIM1 CH1 - PA8 - U high */ -#define GPIO_TIM1_CH2OUT (GPIO_TIM1_CH2OUT_0 | GPIO_SPEED_50MHz) /* TIM1 CH2 - PA9 - V high */ -#define GPIO_TIM1_CH3OUT (GPIO_TIM1_CH3OUT_0 | GPIO_SPEED_50MHz) /* TIM1 CH3 - PA10 - W high */ -#define GPIO_TIM1_CH1NOUT (GPIO_TIM1_CH1NOUT_4 | GPIO_SPEED_50MHz) /* TIM1 CH1N - PC13 - U low */ -#define GPIO_TIM1_CH2NOUT (GPIO_TIM1_CH2NOUT_1 | GPIO_SPEED_50MHz) /* TIM1 CH2N - PA12 - V low */ -#define GPIO_TIM1_CH3NOUT (GPIO_TIM1_CH3NOUT_3 | GPIO_SPEED_50MHz) /* TIM1 CH3N - PB15 - W low */ - -/* TIM4 QE configuration ****************************************************/ - -#define GPIO_TIM4_CH1IN (GPIO_TIM4_CH1IN_2 | GPIO_SPEED_50MHz) /* TIM4 CH1 - PB6 */ -#define GPIO_TIM4_CH2IN (GPIO_TIM4_CH2IN_2 | GPIO_SPEED_50MHz) /* TIM4 CH2 - PB7 */ - -/* OPAMP configuration ******************************************************/ - -#define GPIO_OPAMP1_VINM0 (GPIO_OPAMP1_VINM0_0) /* PA3 */ -#define GPIO_OPAMP1_VINP0 (GPIO_OPAMP1_VINP0_0) /* PA1 */ -#define GPIO_OPAMP1_VOUT (GPIO_OPAMP1_VOUT_0) /* PA2 */ - -#define GPIO_OPAMP2_VINM0 (GPIO_OPAMP2_VINM0_0) /* PA5 */ -#define GPIO_OPAMP2_VINP0 (GPIO_OPAMP2_VINP0_0) /* PA7 */ -#define GPIO_OPAMP2_VOUT (GPIO_OPAMP2_VOUT_0) /* PA6 */ - -#define GPIO_OPAMP3_VINM0 (GPIO_OPAMP3_VINM0_0) /* PB2 */ -#define GPIO_OPAMP3_VINP0 (GPIO_OPAMP3_VINP0_0) /* PB0 */ -#define GPIO_OPAMP3_VOUT (GPIO_OPAMP3_VOUT_0) /* PB1 */ - -/* CAN configuration ********************************************************/ - -#define GPIO_FDCAN1_RX (GPIO_FDCAN1_RX_1 | GPIO_SPEED_50MHz) /* PA11 */ -#define GPIO_FDCAN1_TX (GPIO_FDCAN1_TX_2 | GPIO_SPEED_50MHz) /* PB9 */ - -/* DMA channels *************************************************************/ - -/* ADC */ - -#define ADC1_DMA_CHAN DMAMAP_DMA12_ADC1_0 /* DMA1 */ - -/* USART2 */ - -#define DMACHAN_USART2_TX DMAMAP_DMA12_USART2TX_0 /* DMA1 */ -#define DMACHAN_USART2_RX DMAMAP_DMA12_USART2RX_0 /* DMA1 */ - -#endif /* __BOARDS_ARM_STM32_B_G431B_ESC1_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32/b-g431b-esc1/scripts/Make.defs b/boards/arm/stm32/b-g431b-esc1/scripts/Make.defs deleted file mode 100644 index 0a510303baa4b..0000000000000 --- a/boards/arm/stm32/b-g431b-esc1/scripts/Make.defs +++ /dev/null @@ -1,51 +0,0 @@ -############################################################################ -# boards/arm/stm32/b-g431b-esc1/scripts/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/.config -include $(TOPDIR)/tools/Config.mk -include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs - -ifeq ($(CONFIG_STM32_DFU),y) - LDSCRIPT = ld.script.dfu -else - LDSCRIPT = ld.script -endif - -ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) - -ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 - -CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) -CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) -CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -AFLAGS := $(CFLAGS) -D__ASSEMBLY__ - -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections -LDNXFLATFLAGS = -e main -s 2048 - -# Embed absolute path to source file in debug information so that Eclipse -# source level debugging won't get confused. See: -# https://stackoverflow.com/questions/1275476/gcc-gdb-how-to-embed-absolute-path-to-source-file-in-debug-information -CFLAGS += -fdebug-prefix-map=..=$(readlink -f ..) diff --git a/boards/arm/stm32/b-g431b-esc1/scripts/ld.script b/boards/arm/stm32/b-g431b-esc1/scripts/ld.script deleted file mode 100644 index aae24391abfd7..0000000000000 --- a/boards/arm/stm32/b-g431b-esc1/scripts/ld.script +++ /dev/null @@ -1,139 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/b-g431b-esc1/scripts/ld.script - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* The STM32G431CB has 128 KiB of FLASH beginning at address 0x0800:0000. - * - * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 - * where the code expects to begin execution by jumping to the entry point in - * the 0x0800:0000 address range. - * - * The STM32G431CB has a total of 32 KiB of SRAM in three separate areas: - * - * 1) 16 KiB SRAM1 mapped at 0x2000:0000 thru 0x2000:3fff. - * 2) 6 KiB SRAM2 mapped at 0x2000:4000 thru 0x2000:57ff. - * - * CCM SRAM (Routine Booster): - * - * 3) 10 KiB CCM SRAM mapped at 0x1000:0000 thru 0x1000:27ff - * but also aliased at at 0x2000:5800 thru 0x2000:7fff to be contiguous - * with the SRAM1 and SRAM2. - * - * Because SRAM1 and SRAM2 are contiguous, they are treated as one region - * by this logic. - * - * CCM SRAM is also contiguous to SRAM1 and SRAM2, however it is excluded - * from this linker script, to keep it reserved for special uses in code. - * REVISIT: Is this the correct way to handle CCM SRAM? - */ - -MEMORY -{ - flash (rx) : ORIGIN = 0x08000000, LENGTH = 128K - sram (rwx) : ORIGIN = 0x20000000, LENGTH = 22K -} - -OUTPUT_ARCH(arm) -EXTERN(_vectors) -ENTRY(_stext) - -SECTIONS -{ - .text : { - _stext = ABSOLUTE(.); - *(.vectors) - *(.text .text.*) - *(.fixup) - *(.gnu.warning) - *(.rodata .rodata.*) - *(.gnu.linkonce.t.*) - *(.glue_7) - *(.glue_7t) - *(.got) - *(.gcc_except_table) - *(.gnu.linkonce.r.*) - _etext = ABSOLUTE(.); - } > flash - - .init_section : ALIGN(4) { - _sinit = ABSOLUTE(.); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) - KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) - _einit = ABSOLUTE(.); - } > flash - - .ARM.extab : ALIGN(4) { - *(.ARM.extab*) - } > flash - - .ARM.exidx : ALIGN(4) { - __exidx_start = ABSOLUTE(.); - *(.ARM.exidx*) - __exidx_end = ABSOLUTE(.); - } > flash - - .tdata : { - _stdata = ABSOLUTE(.); - *(.tdata .tdata.* .gnu.linkonce.td.*); - _etdata = ABSOLUTE(.); - } > flash - - .tbss : { - _stbss = ABSOLUTE(.); - *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); - _etbss = ABSOLUTE(.); - } > flash - - _eronly = ABSOLUTE(.); - - .data : ALIGN(4) { - _sdata = ABSOLUTE(.); - *(.data .data.*) - *(.gnu.linkonce.d.*) - CONSTRUCTORS - . = ALIGN(4); - _edata = ABSOLUTE(.); - } > sram AT > flash - - .bss : ALIGN(4) { - _sbss = ABSOLUTE(.); - *(.bss .bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - . = ALIGN(4); - _ebss = ABSOLUTE(.); - } > sram - - /* Stabs debugging sections. */ - - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_info 0 : { *(.debug_info) } - .debug_line 0 : { *(.debug_line) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_aranges 0 : { *(.debug_aranges) } -} diff --git a/boards/arm/stm32/b-g431b-esc1/src/CMakeLists.txt b/boards/arm/stm32/b-g431b-esc1/src/CMakeLists.txt deleted file mode 100644 index 76a72b59c7a86..0000000000000 --- a/boards/arm/stm32/b-g431b-esc1/src/CMakeLists.txt +++ /dev/null @@ -1,50 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/b-g431b-esc1/src/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -set(SRCS stm32_boot.c stm32_bringup.c) - -if(CONFIG_ARCH_LEDS) - list(APPEND SRCS stm32_autoleds.c) -else() - list(APPEND SRCS stm32_userleds.c) -endif() - -if(CONFIG_ARCH_BUTTONS) - list(APPEND SRCS stm32_buttons.c) -endif() - -if(CONFIG_STM32_FOC) - list(APPEND SRCS stm32_foc.c) -endif() - -if(CONFIG_STM32_FDCAN) - if(CONFIG_STM32_FDCAN_CHARDRIVER) - list(APPEND SRCS stm32_can.c) - endif() - if(CONFIG_STM32_FDCAN_SOCKET) - list(APPEND SRCS stm32_cansock.c) - endif() -endif() - -target_sources(board PRIVATE ${SRCS}) - -set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/ld.script") diff --git a/boards/arm/stm32/b-g431b-esc1/src/Make.defs b/boards/arm/stm32/b-g431b-esc1/src/Make.defs deleted file mode 100644 index 2d49b9a66c91e..0000000000000 --- a/boards/arm/stm32/b-g431b-esc1/src/Make.defs +++ /dev/null @@ -1,53 +0,0 @@ -############################################################################ -# boards/arm/stm32/b-g431b-esc1/src/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/Make.defs - -ASRCS = -CSRCS = stm32_boot.c stm32_bringup.c - -ifeq ($(CONFIG_ARCH_LEDS),y) -CSRCS += stm32_autoleds.c -else -CSRCS += stm32_userleds.c -endif - -ifeq ($(CONFIG_ARCH_BUTTONS),y) -CSRCS += stm32_buttons.c -endif - -ifeq ($(CONFIG_STM32_FOC),y) -CSRCS += stm32_foc.c -endif - -ifeq ($(CONFIG_STM32_FDCAN),y) -ifeq ($(CONFIG_STM32_FDCAN_CHARDRIVER),y) -CSRCS += stm32_can.c -endif -ifeq ($(CONFIG_STM32_FDCAN_SOCKET),y) -CSRCS += stm32_cansock.c -endif -endif - -DEPPATH += --dep-path board -VPATH += :board -CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/b-g431b-esc1/src/stm32_autoleds.c b/boards/arm/stm32/b-g431b-esc1/src/stm32_autoleds.c deleted file mode 100644 index ec5bbf09cf59c..0000000000000 --- a/boards/arm/stm32/b-g431b-esc1/src/stm32_autoleds.c +++ /dev/null @@ -1,80 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/b-g431b-esc1/src/stm32_autoleds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include "stm32.h" -#include "b-g431b-esc1.h" - -#if defined(CONFIG_ARCH_LEDS) - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_autoled_initialize - ****************************************************************************/ - -void board_autoled_initialize(void) -{ - /* Configure LED GPIOs for output */ - - stm32_configgpio(GPIO_LED1); -} - -/**************************************************************************** - * Name: board_autoled_on - ****************************************************************************/ - -void board_autoled_on(int led) -{ - if (led == BOARD_LED1) - { - stm32_gpiowrite(GPIO_LED1, true); - } -} - -/**************************************************************************** - * Name: board_autoled_off - ****************************************************************************/ - -void board_autoled_off(int led) -{ - if (led == BOARD_LED1) - { - stm32_gpiowrite(GPIO_LED1, false); - } -} - -#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/b-g431b-esc1/src/stm32_boot.c b/boards/arm/stm32/b-g431b-esc1/src/stm32_boot.c deleted file mode 100644 index 12e9e93bf6e60..0000000000000 --- a/boards/arm/stm32/b-g431b-esc1/src/stm32_boot.c +++ /dev/null @@ -1,95 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/b-g431b-esc1/src/stm32_boot.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include "b-g431b-esc1.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_boardinitialize - * - * Description: - * All STM32 architectures must provide the following entry point. This - * entry point is called early in the initialization -- after all memory - * has been configured and mapped but before any devices have been - * initialized. - * - ****************************************************************************/ - -void stm32_boardinitialize(void) -{ - /* Configure on-board LEDs if LED support has been selected. */ - -#ifdef CONFIG_ARCH_LEDS - board_autoled_initialize(); -#endif -} - -/**************************************************************************** - * Name: board_late_initialize - * - * Description: - * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional - * initialization call will be performed in the boot-up sequence to a - * function called board_late_initialize(). board_late_initialize() will - * be called immediately after up_initialize() is called and just before - * the initial application is started. This additional initialization - * phase may be used, for example, to initialize board-specific device - * drivers. - * - ****************************************************************************/ - -#ifdef CONFIG_BOARD_LATE_INITIALIZE -void board_late_initialize(void) -{ - /* Perform board-specific initialization */ - - stm32_bringup(); -} -#endif diff --git a/boards/arm/stm32/b-g431b-esc1/src/stm32_bringup.c b/boards/arm/stm32/b-g431b-esc1/src/stm32_bringup.c deleted file mode 100644 index 3b5cf90e92647..0000000000000 --- a/boards/arm/stm32/b-g431b-esc1/src/stm32_bringup.c +++ /dev/null @@ -1,185 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/b-g431b-esc1/src/stm32_bringup.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include - -#include - -#ifdef CONFIG_USERLED -# include -#endif - -#ifdef CONFIG_INPUT_BUTTONS -# include -#endif - -#ifdef CONFIG_SENSORS_QENCODER -# include "board_qencoder.h" -#endif - -#ifdef CONFIG_SENSORS_HALL3PHASE -# include "board_hall3ph.h" -#endif - -#include "b-g431b-esc1.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#undef HAVE_LEDS - -#if !defined(CONFIG_ARCH_LEDS) && defined(CONFIG_USERLED_LOWER) -# define HAVE_LEDS 1 -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_bringup - * - * Description: - * Perform architecture-specific initialization - * - * CONFIG_BOARD_LATE_INITIALIZE=y : - * Called from board_late_initialize(). - * - ****************************************************************************/ - -int stm32_bringup(void) -{ - int ret; - -#ifdef CONFIG_FS_PROCFS - /* Mount the procfs file system */ - - ret = nx_mount(NULL, STM32_PROCFS_MOUNTPOINT, "procfs", 0, NULL); - if (ret < 0) - { - syslog(LOG_ERR, - "ERROR: Failed to mount the PROC filesystem: %d\n", ret); - } -#endif /* CONFIG_FS_PROCFS */ - -#ifdef CONFIG_INPUT_BUTTONS - /* Register the BUTTON driver */ - - ret = btn_lower_initialize("/dev/buttons"); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: btn_lower_initialize() failed: %d\n", ret); - } -#endif - -#if defined(HAVE_LEDS) - /* Register the LED driver */ - - ret = userled_lower_initialize(LED_DRIVER_PATH); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: userled_lower_initialize() failed: %d\n", ret); - return ret; - } -#endif - -#ifdef CONFIG_STM32_FOC - /* Initialize and register the FOC device - must be before ADC setup */ - - ret = stm32_foc_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_foc_setup failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_ADC - /* Initialize ADC and register the ADC driver. */ - - ret = stm32_adc_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_adc_setup failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_SENSORS_QENCODER - /* Initialize and register the qencoder driver - TIM4 */ - - ret = board_qencoder_initialize(0, 4); - if (ret != OK) - { - syslog(LOG_ERR, - "ERROR: Failed to register the qencoder: %d\n", - ret); - return ret; - } -#endif - -#ifdef CONFIG_SENSORS_HALL3PHASE - /* Initialize and register the 3-phase Hall effect sensor driver */ - - ret = board_hall3ph_initialize(0, GPIO_HALL_PHA, GPIO_HALL_PHB, - GPIO_HALL_PHC); - if (ret != OK) - { - syslog(LOG_ERR, - "ERROR: Failed to register the hall : %d\n", - ret); - return ret; - } -#endif - -#ifdef CONFIG_STM32_FDCAN_CHARDRIVER - /* Initialize CAN and register the CAN driver. */ - - ret = stm32_can_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_fdcan_setup failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_STM32_FDCAN_SOCKET - /* Initialize CAN socket interface */ - - ret = stm32_cansock_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_cansock_setup failed: %d\n", ret); - } -#endif - - UNUSED(ret); - return OK; -} diff --git a/boards/arm/stm32/b-g431b-esc1/src/stm32_buttons.c b/boards/arm/stm32/b-g431b-esc1/src/stm32_buttons.c deleted file mode 100644 index 3e7c93b00f732..0000000000000 --- a/boards/arm/stm32/b-g431b-esc1/src/stm32_buttons.c +++ /dev/null @@ -1,113 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/b-g431b-esc1/src/stm32_buttons.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include "stm32.h" -#include "b-g431b-esc1.h" - -#ifdef CONFIG_ARCH_BUTTONS - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_button_initialize - * - * Description: - * board_button_initialize() must be called to initialize button - * resources. After that, board_buttons() may be called to collect the - * current state of all buttons or board_button_irq() may be called to - * register button interrupt handlers. - * - ****************************************************************************/ - -uint32_t board_button_initialize(void) -{ - /* Configure the single button as an input. NOTE that EXTI interrupts are - * also configured for the pin. - */ - - stm32_configgpio(GPIO_BTN_USER); - return NUM_BUTTONS; -} - -/**************************************************************************** - * Name: board_buttons - * - * Description: - * After board_button_initialize() has been called, board_buttons() may be - * called to collect the state of all buttons. board_buttons() returns an - * 32-bit unsigned integer with each bit associated with a button. See the - * BUTTON_*_BIT definitions in board.h for the meaning of each bit. - * - ****************************************************************************/ - -uint32_t board_buttons(void) -{ - /* Check the state of the USER button. A LOW value means that the key is - * pressed. - */ - - return stm32_gpioread(GPIO_BTN_USER) ? 0 : BUTTON_USER_BIT; -} - -/**************************************************************************** - * Name: board_button_irq - * - * Description: - * board_button_irq() may be called to register an interrupt handler that - * will be called when a button is depressed or released. The ID value is - * a button enumeration value that uniquely identifies a button resource. - * See the BUTTON_* definitions in board.h for the meaning of the - * enumeration value. - * - ****************************************************************************/ - -#ifdef CONFIG_ARCH_IRQBUTTONS -int board_button_irq(int id, xcpt_t irqhandler, void *arg) -{ - int ret = -EINVAL; - - if (id == BUTTON_USER) - { - ret = stm32_gpiosetevent(GPIO_BTN_USER, true, true, true, irqhandler, - arg); - } - - return ret; -} -#endif - -#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/stm32/b-g431b-esc1/src/stm32_can.c b/boards/arm/stm32/b-g431b-esc1/src/stm32_can.c deleted file mode 100644 index 5a8c005e9ba3b..0000000000000 --- a/boards/arm/stm32/b-g431b-esc1/src/stm32_can.c +++ /dev/null @@ -1,105 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/b-g431b-esc1/src/stm32_can.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32.h" -#include "stm32_fdcan.h" -#include "b-g431b-esc1.h" - -#ifdef CONFIG_CAN - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -#if !defined(CONFIG_STM32_FDCAN1) -# error "No CAN is enable. Please enable at least one CAN device" -#endif - -#ifdef CONFIG_BOARD_STM32_BG431BESC1_CANTERM -# define BG431BESC1_CANTERM (true) -#else -# define BG431BESC1_CANTERM (false) -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_can_setup - * - * Description: - * Initialize CAN and register the CAN device - * - ****************************************************************************/ - -int stm32_can_setup(void) -{ - struct can_dev_s *can; - int ret; - - /* Call stm32_fdcaninitialize() to get an instance of the CAN interface */ - - can = stm32_fdcaninitialize(1); - if (can == NULL) - { - canerr("ERROR: Failed to get CAN interface\n"); - return -ENODEV; - } - - /* Register the CAN driver at "/dev/can0" */ - - ret = can_register("/dev/can0", can); - if (ret < 0) - { - canerr("ERROR: can_register failed: %d\n", ret); - return ret; - } - - /* Configure CAN_TERM pin for output */ - - stm32_configgpio(GPIO_CANTERM); - - /* Set CAN_TERM pin high or low */ - - stm32_gpiowrite(GPIO_CANTERM, BG431BESC1_CANTERM); - - return OK; -} - -#endif /* CONFIG_CAN */ diff --git a/boards/arm/stm32/b-g431b-esc1/src/stm32_cansock.c b/boards/arm/stm32/b-g431b-esc1/src/stm32_cansock.c deleted file mode 100644 index 1841bc9e6cd7c..0000000000000 --- a/boards/arm/stm32/b-g431b-esc1/src/stm32_cansock.c +++ /dev/null @@ -1,84 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/b-g431b-esc1/src/stm32_cansock.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include "stm32_fdcan.h" -#include "b-g431b-esc1.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -#if !defined(CONFIG_STM32_FDCAN1) -# error "No CAN is enable. Please enable at least one CAN device" -#endif - -#ifdef CONFIG_BOARD_STM32_BG431BESC1_CANTERM -# define BG431BESC1_CANTERM (true) -#else -# define BG431BESC1_CANTERM (false) -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_cansock_setup - * - * Description: - * Initialize CAN socket interface - * - ****************************************************************************/ - -int stm32_cansock_setup(void) -{ - int ret; - - /* Call stm32_fdcaninitialize() to get an instance of the FDCAN interface */ - - ret = stm32_fdcansockinitialize(1); - if (ret < 0) - { - canerr("ERROR: Failed to get FDCAN interface %d\n", ret); - return ret; - } - - /* Configure CAN_TERM pin for output */ - - stm32_configgpio(GPIO_CANTERM); - - /* Set CAN_TERM pin high or low */ - - stm32_gpiowrite(GPIO_CANTERM, BG431BESC1_CANTERM); - - return OK; -} diff --git a/boards/arm/stm32/b-g431b-esc1/src/stm32_foc.c b/boards/arm/stm32/b-g431b-esc1/src/stm32_foc.c deleted file mode 100644 index 6b22e655b382b..0000000000000 --- a/boards/arm/stm32/b-g431b-esc1/src/stm32_foc.c +++ /dev/null @@ -1,766 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/b-g431b-esc1/src/stm32_foc.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include - -#include - -#include "hardware/stm32g4xxxx_opamp.h" - -#if defined(CONFIG_SENSORS_QENCODER) || defined(CONFIG_SENSORS_HALL3PHASE) -# include "hardware/stm32g4xxxx_pwr.h" -#endif - -#include "stm32_foc.h" - -#ifdef CONFIG_SENSORS_QENCODER -# include "stm32_qencoder.h" -#endif - -#include "arm_internal.h" -#include "b-g431b-esc1.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* We don't use phase 2 feedback as it is no connected to ADC1 */ - -#if CONFIG_MOTOR_FOC_SHUNTS != 2 -# error Only 2-shunts configuration is supported -#endif - -/* Configuration specific for L6387ED: - * 1. PWM channels must have positive polarity - * 2. PWM complementary channels must have positive polarity - */ - -#ifndef CONFIG_STM32_FOC_HAS_PWM_COMPLEMENTARY -# error -#endif - -#if CONFIG_STM32_TIM1_CH1POL != 0 -# error -#endif -#if CONFIG_STM32_TIM1_CH2POL != 0 -# error -#endif -#if CONFIG_STM32_TIM1_CH3POL != 0 -# error -#endif -#if CONFIG_STM32_TIM1_CH1NPOL != 0 -# error -#endif -#if CONFIG_STM32_TIM1_CH2NPOL != 0 -# error -#endif -#if CONFIG_STM32_TIM1_CH3NPOL != 0 -# error -#endif - -/* SYSCFG must be enabled for OPAMP */ - -#ifndef CONFIG_STM32_SYSCFG -# error -#endif - -/* Aux ADC needs DMA enabled and workaround for G4 ADC CHAN0 enabled */ - -#ifdef CONFIG_ADC -# ifndef CONFIG_STM32_ADC1_DMA -# error -# endif -# ifndef CONFIG_STM32_FOC_G4_ADCCHAN0_WORKAROUND -# error -# endif -#endif - -/* REVISIT: */ - -#define PWM_DEADTIME (20) -#define PWM_DEADTIME_NS (500) - -/* Devpath for FOC driver */ - -#define FOC_DEVPATH "/dev/foc0" - -/* Board parameters: - * Current shunt resistance = 0.003 - * PGA gain = 16 - * Current sense gain = -9.14 (inverted current) - * Vbus sense gain = 0.0962 - * Vbus min = 7V - * Vbus max = 25V (6S LiPo battery pack) - * Iout max = 40A peak - * IPHASE_RATIO = 1/(R_shunt*gain) = -36.47 - * ADC_REF_VOLTAGE = 3.3 - * ADC_VAL_MAX = 4095 - * ADC_TO_VOLT = ADC_REF_VOLTAGE / ADC_VAL_MAX - * IPHASE_ADC = IPHASE_RATIO * ADC_TO_VOLT = -0.02939 - * VBUS_RATIO = 1/VBUS_gain = 10.4 - */ - -/* OPAMP gain */ - -#define CURRENT_PGA_GAIN 16 - -/* Center-aligned PWM duty cycle limits */ - -#define MAX_DUTY_B16 ftob16(0.95f) - -/* ADC sample time */ - -#define CURRENT_SAMPLE_TIME ADC_SMPR_2p5 -#define VOLTAGE_SAMPLE_TIME ADC_SMPR_2p5 -#define VBUS_SAMPLE_TIME ADC_SMPR_640p5 -#define POT_SAMPLE_TIME ADC_SMPR_640p5 - -/* ADC1 channels used in this example */ - -#define ADC1_INJECTED (CONFIG_MOTOR_FOC_SHUNTS) - -#ifdef CONFIG_BOARD_STM32_BG431BESC1_FOC_VBUS -# define BG431BESC1_FOC_VBUS 1 -#else -# define BG431BESC1_FOC_VBUS 0 -#endif - -#ifdef CONFIG_BOARD_STM32_BG431BESC1_FOC_POT -# define BG431BESC1_FOC_POT 1 -#else -# define BG431BESC1_FOC_POT 0 -#endif - -#define ADC1_REGULAR (BG431BESC1_FOC_VBUS + BG431BESC1_FOC_POT) -#define ADC1_NCHANNELS (ADC1_INJECTED + ADC1_REGULAR) - -#ifdef CONFIG_MOTOR_FOC_BEMF_SENSE -/* ADC2 channels used for BEMF sensing */ - -# define ADC2_INJECTED (CONFIG_MOTOR_FOC_PHASES) -# define ADC2_REGULAR (0) -# define ADC2_NCHANNELS (ADC2_INJECTED + ADC2_REGULAR) -#endif - -/* Check ADC1 configuration */ - -#ifdef CONFIG_STM32_FOC_G4_ADCCHAN0_WORKAROUND -# if ADC1_INJECTED != (CONFIG_STM32_ADC1_INJECTED_CHAN - 1) -# error -# endif -#else -# if ADC1_INJECTED != CONFIG_STM32_ADC1_INJECTED_CHAN -# error -# endif -#endif - -#if CONFIG_STM32_ADC1_RESOLUTION != 0 -# error -#endif - -/* Qenco configuration - only TIM4 */ - -#ifdef CONFIG_SENSORS_QENCODER -# ifndef CONFIG_STM32_TIM4_QE -# error -# endif -# if CONFIG_STM32_TIM4_QEPSC != 0 -# error -# endif -#endif - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/**************************************************************************** - * Private Function Protototypes - ****************************************************************************/ - -static int board_foc_setup(struct foc_dev_s *dev); -static int board_foc_shutdown(struct foc_dev_s *dev); -static int board_foc_calibration(struct foc_dev_s *dev, bool state); -static int board_foc_fault_clear(struct foc_dev_s *dev); -static int board_foc_pwm_start(struct foc_dev_s *dev, bool state); -static int board_foc_current_get(struct foc_dev_s *dev, - int16_t *curr_raw, - foc_current_t *curr); -#ifdef CONFIG_MOTOR_FOC_BEMF_SENSE -static int board_foc_voltage_get(struct foc_dev_s *dev, - int16_t *volt_raw, - foc_voltage_t *volt); -#endif -static int board_foc_info_get(struct foc_dev_s *dev, - struct foc_info_s *info); -#ifdef CONFIG_MOTOR_FOC_TRACE -static int board_foc_trace_init(struct foc_dev_s *dev); -static void board_foc_trace(struct foc_dev_s *dev, int type, bool state); -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* OPAMP configuration: - * - connected with ADC through output pin (OPAINTOEN=0) - * - Current U+ - OPAMP1_VINP0 (PA1) - * - Current U- - OPAMP1_VINP0 (PA3) - * - Current V+ - OPAMP2_VINP0 (PA7) - * - Current V- - OPAMP2_VINP0 (PA5) - * - Current W+ - OPAMP3_VINP0 (PB0) - * - Current W- - OPAMP3_VINP0 (PB2) - * - * ADC configuration: - * - Current Phase V -> ADC1 INJ1 -> ADC1_IN3 (OPAMP1_VOUT/PA2) - * - Current Phase U -> Not used, no ADC1 connection - * - Current Phase W -> ADC1 INJ2 -> ADC1_IN12 (OPAMP3_VOUT/PB12) - * optional: - * - VBUS -> ADC1 REG -> ADC1_IN1 (PA0) - * - POT -> ADC1 REG -> ADC1_IN11 (PB12) - * - * TIM1 PWM configuration: - * - Phase U high -> TIM1_CH1 (PA8) - * - Phase U low -> TIM1_CH1N (PC13) - * - Phase V high -> TIM1_CH2 (PA9) - * - Phase V low -> TIM1_CH2N (PA12) - * - Phase W high -> TIM1_CH3 (PA10) - * - Phase W low -> TIM1_CH3N (PB15) - */ - -static uint8_t g_adc1_chan[] = -{ -#ifdef CONFIG_BOARD_STM32_BG431BESC1_FOC_VBUS - 1, /* ADC1 REG - VBUS */ -#endif -#ifdef CONFIG_BOARD_STM32_BG431BESC1_FOC_POT - 11, /* ADC1 REG - POT */ -#endif - 3, /* ADC1 INJ1 - PHASE 1 */ - 12, /* ADC1 INJ2 - PHASE 3 */ -}; - -static uint32_t g_adc1_pins[] = -{ -#ifdef CONFIG_BOARD_STM32_BG431BESC1_FOC_VBUS - GPIO_ADC1_IN1, -#endif -#ifdef CONFIG_BOARD_STM32_BG431BESC1_FOC_POT - GPIO_ADC1_IN11, -#endif - GPIO_ADC1_IN3, - GPIO_ADC1_IN12, -}; - -/* ADC1 sample time configuration */ - -static adc_channel_t g_adc1_stime[] = -{ -#ifdef CONFIG_BOARD_STM32_BG431BESC1_FOC_VBUS - { - .channel = 1, - .sample_time = VBUS_SAMPLE_TIME - }, -#endif -#ifdef CONFIG_BOARD_STM32_BG431BESC1_FOC_POT - { - .channel = 11, - .sample_time = POT_SAMPLE_TIME - }, -#endif - { - .channel = 3, - .sample_time = CURRENT_SAMPLE_TIME - }, - { - .channel = 12, - .sample_time = CURRENT_SAMPLE_TIME - }, -}; - -/* Board specific ADC configuration for FOC */ - -static struct stm32_foc_adc_s g_adc_cfg = -{ - .chan = g_adc1_chan, - .pins = g_adc1_pins, - .stime = g_adc1_stime, - .nchan = ADC1_NCHANNELS, - .regch = ADC1_REGULAR, - .intf = 1 -}; - -#ifdef CONFIG_MOTOR_FOC_BEMF_SENSE -static uint8_t g_adc2_chan[] = -{ - 17, /* ADC2 INJ1 - PHASE 1 */ - 5, /* ADC2 INJ2 - PHASE 2 */ - 14, /* ADC2 INJ3 - PHASE 3 */ -}; - -static uint32_t g_adc2_pins[] = -{ - GPIO_ADC2_IN17, - GPIO_ADC2_IN5, - GPIO_ADC2_IN14, -}; - -/* ADC2 sample time configuration */ - -static adc_channel_t g_adc2_stime[] = -{ - { - .channel = 17, - .sample_time = VOLTAGE_SAMPLE_TIME - }, - { - .channel = 5, - .sample_time = VOLTAGE_SAMPLE_TIME - }, - { - .channel = 14, - .sample_time = VOLTAGE_SAMPLE_TIME - }, -}; - -/* Board specific ADC configuration for BEMF */ - -static struct stm32_foc_adc_s g_vadc_cfg = -{ - .chan = g_adc2_chan, - .pins = g_adc2_pins, - .stime = g_adc2_stime, - .nchan = ADC2_NCHANNELS, - .regch = ADC2_REGULAR, - .intf = 2 -}; -#endif - -/* Board specific ops */ - -static struct stm32_foc_board_ops_s g_stm32_foc_board_ops = -{ - .setup = board_foc_setup, - .shutdown = board_foc_shutdown, - .calibration = board_foc_calibration, - .fault_clear = board_foc_fault_clear, - .pwm_start = board_foc_pwm_start, - .current_get = board_foc_current_get, -#ifdef CONFIG_MOTOR_FOC_BEMF_SENSE - .voltage_get = board_foc_voltage_get, -#endif - .info_get = board_foc_info_get, -#ifdef CONFIG_MOTOR_FOC_TRACE - .trace_init = board_foc_trace_init, - .trace = board_foc_trace -#endif -}; - -/* Board specific data */ - -static struct stm32_foc_board_data_s g_stm32_foc_board_data = -{ - .adc_cfg = &g_adc_cfg, -#ifdef CONFIG_MOTOR_FOC_BEMF_SENSE - .vadc_cfg = &g_vadc_cfg, -#endif - .pwm_dt = PWM_DEADTIME -}; - -/* Board specific configuration */ - -static struct stm32_foc_board_s g_stm32_foc_board = -{ - .data = &g_stm32_foc_board_data, - .ops = &g_stm32_foc_board_ops, -}; - -/* Global pointer to the upper FOC driver */ - -static struct foc_dev_s *g_foc_dev = NULL; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_foc_setup - ****************************************************************************/ - -static int board_foc_setup(struct foc_dev_s *dev) -{ - uint32_t regval = 0; - - DEBUGASSERT(dev); - - UNUSED(dev); - - /* OPAMP1/2/3 pins: - * OPAMP1_VINM - PA3 (VINM0) - * OPAMP1_VINP - PA1 (VINP0) - * OPAMP2_VINM - PA5 (VINM0) - * OPAMP2_VINP - PA7 (VINP0) - * OPAMP3_VINM - PB2 (VINM0) - * OPAMP3_VINP - PB0 (VINP0) - */ - - /* Configure GPIO */ - - stm32_configgpio(GPIO_OPAMP1_VINM0); - stm32_configgpio(GPIO_OPAMP1_VINP0); - stm32_configgpio(GPIO_OPAMP1_VOUT); - stm32_configgpio(GPIO_OPAMP2_VINM0); - stm32_configgpio(GPIO_OPAMP2_VINP0); - stm32_configgpio(GPIO_OPAMP2_VOUT); - stm32_configgpio(GPIO_OPAMP3_VINM0); - stm32_configgpio(GPIO_OPAMP3_VINP0); - stm32_configgpio(GPIO_OPAMP3_VOUT); -#ifdef CONFIG_MOTOR_FOC_BEMF_SENSE - stm32_configgpio(GPIO_GPIOBEMF); -#endif - - /* Configure OPAMP inputs */ - - regval += (OPAMP_CSR_VPSEL_VINP0 | OPAMP_CSR_VMSEL_PGA); - - /* PGA mode, non-inverting configuration with external bias on VINM0 */ - -#if CURRENT_PGA_GAIN == 16 - regval += ((0b01011 << OPAMP_CSR_PGAGAIN_SHIFT) & OPAMP_CSR_PGAGAIN_MASK); -#else -# error Not supported -#endif - - /* Enable high-speed mode */ - - regval += OPAMP_CSR_OPAHSM; - - /* Write configuration */ - - putreg32(regval, STM32_OPAMP1_CSR); - putreg32(regval, STM32_OPAMP2_CSR); - putreg32(regval, STM32_OPAMP3_CSR); - - /* Enable OPAMPs in separate write */ - - regval += OPAMP_CSR_OPAMPEN; - - putreg32(regval, STM32_OPAMP1_CSR); - putreg32(regval, STM32_OPAMP2_CSR); - putreg32(regval, STM32_OPAMP3_CSR); - -#ifdef CONFIG_MOTOR_FOC_BEMF_SENSE - /* Keep GPIO_BEMF low to create BEMF voltage divider */ - - stm32_gpiowrite(GPIO_GPIOBEMF, false); -#endif - - return OK; -} - -/**************************************************************************** - * Name: board_foc_shutdown - ****************************************************************************/ - -static int board_foc_shutdown(struct foc_dev_s *dev) -{ - DEBUGASSERT(dev); - - UNUSED(dev); - - return OK; -} - -/**************************************************************************** - * Name: board_foc_calibration - ****************************************************************************/ - -static int board_foc_calibration(struct foc_dev_s *dev, bool state) -{ - DEBUGASSERT(dev); - - UNUSED(dev); - - return OK; -} - -/**************************************************************************** - * Name: board_foc_fault_clear - ****************************************************************************/ - -static int board_foc_fault_clear(struct foc_dev_s *dev) -{ - DEBUGASSERT(dev); - - UNUSED(dev); - - return OK; -} - -/**************************************************************************** - * Name: board_foc_pwm_start - ****************************************************************************/ - -static int board_foc_pwm_start(struct foc_dev_s *dev, bool state) -{ - DEBUGASSERT(dev); - - UNUSED(dev); - - return OK; -} - -/**************************************************************************** - * Name: board_foc_current_get - ****************************************************************************/ - -static int board_foc_current_get(struct foc_dev_s *dev, - int16_t *curr_raw, - foc_current_t *curr) -{ - DEBUGASSERT(dev); - DEBUGASSERT(curr_raw); - DEBUGASSERT(curr); - - /* Get currents */ - - curr[0] = curr_raw[0]; - curr[2] = curr_raw[1]; - - /* Phase 2 reconstruction */ - - curr[1] = -(curr_raw[0] + curr_raw[1]); - - return OK; -} - -#ifdef CONFIG_MOTOR_FOC_BEMF_SENSE -/**************************************************************************** - * Name: board_foc_voltage_get - ****************************************************************************/ - -static int board_foc_voltage_get(struct foc_dev_s *dev, - int16_t *volt_raw, - foc_voltage_t *volt) -{ - DEBUGASSERT(dev); - DEBUGASSERT(volt_raw); - DEBUGASSERT(volt); - - /* Get voltages */ - - volt[0] = volt_raw[0]; - volt[1] = volt_raw[1]; - volt[2] = volt_raw[2]; - - return OK; -} -#endif - -/**************************************************************************** - * Name: board_foc_info_get - ****************************************************************************/ - -static int board_foc_info_get(struct foc_dev_s *dev, struct foc_info_s *info) -{ - DEBUGASSERT(dev); - DEBUGASSERT(info); - - UNUSED(dev); - - /* PWM */ - - info->hw_cfg.pwm_dt_ns = PWM_DEADTIME_NS; - info->hw_cfg.pwm_max = MAX_DUTY_B16; - - /* ADC BEMF */ - -#ifdef CONFIG_MOTOR_FOC_BEMF_SENSE - info->hw_cfg.bemf_scale = 0; /* TODO */ -#endif - - /* ADC Current - dynamic current scale not supported */ - - info->hw_cfg.iphase_max = 40000; - info->hw_cfg.iphase_scale = -2939; - - return OK; -} - -#ifdef CONFIG_MOTOR_FOC_TRACE -/**************************************************************************** - * Name: board_foc_trace_init - ****************************************************************************/ - -static int board_foc_trace_init(struct foc_dev_s *dev) -{ - DEBUGASSERT(dev); - - UNUSED(dev); - - /* Not supported */ - - return -1; -} - -/**************************************************************************** - * Name: board_foc_trace - ****************************************************************************/ - -static void board_foc_trace(struct foc_dev_s *dev, int type, bool state) -{ - DEBUGASSERT(dev); - - UNUSED(dev); -} -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_foc_setup - * - * Description: - * Initialize FOC driver. - * - * Returned Value: - * 0 on success, a negated errno value on failure - * - ****************************************************************************/ - -int stm32_foc_setup(void) -{ - struct foc_dev_s *foc = NULL; - int ret = OK; - - /* Initialize only once */ - - if (g_foc_dev == NULL) - { -#if defined(CONFIG_SENSORS_QENCODER) || defined(CONFIG_SENSORS_HALL3PHASE) - /* Disable USB Type-C and Power Delivery Dead Battery */ - - modifyreg32(STM32_PWR_CR3, 0, PWR_CR3_UCPD1_DBDIS); -#endif - -#if defined(CONFIG_SENSORS_QENCODER) && defined(CONFIG_STM32_QENCODER_INDEX_PIN) - /* Configure encoder index GPIO */ - - ret = stm32_qe_index_init(4, QENCODER_TIM4_INDEX_GPIO); - if (ret < 0) - { - mtrerr("Failed to register encoder index pin %d\n", ret); - ret = -EACCES; - goto errout; - } -#endif - - /* Initialize arch specific FOC lower-half */ - - foc = stm32_foc_initialize(0, &g_stm32_foc_board); - if (foc == NULL) - { - ret = -errno; - mtrerr("Failed to initialize STM32 FOC: %d\n", ret); - goto errout; - } - - DEBUGASSERT(foc->lower); - - /* Register FOC device */ - - ret = foc_register(FOC_DEVPATH, foc); - if (ret < 0) - { - mtrerr("Failed to register FOC device: %d\n", ret); - goto errout; - } - - /* Store pointer to driver */ - - g_foc_dev = foc; - } - -errout: - return ret; -} - -#ifdef CONFIG_ADC -/**************************************************************************** - * Name: stm32_adc_setup - * - * Description: - * Initialize ADC and register the ADC driver. - * - ****************************************************************************/ - -int stm32_adc_setup(void) -{ - struct adc_dev_s *adc = NULL; - int ret = OK; - static bool initialized = false; - - /* Initialize only once */ - - if (initialized == false) - { - if (g_foc_dev == NULL) - { - mtrerr("Failed to get g_foc_dev device\n"); - ret = -EACCES; - goto errout; - } - - /* Register regular channel ADC */ - - adc = stm32_foc_adcget(g_foc_dev); - if (adc == NULL) - { - mtrerr("Failed to get ADC device: %d\n", ret); - goto errout; - } - - ret = adc_register("/dev/adc0", adc); - if (ret < 0) - { - mtrerr("adc_register failed: %d\n", ret); - goto errout; - } - - initialized = true; - } - -errout: - return ret; -} -#endif diff --git a/boards/arm/stm32/b-g431b-esc1/src/stm32_userleds.c b/boards/arm/stm32/b-g431b-esc1/src/stm32_userleds.c deleted file mode 100644 index 2606087a8fa8c..0000000000000 --- a/boards/arm/stm32/b-g431b-esc1/src/stm32_userleds.c +++ /dev/null @@ -1,77 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/b-g431b-esc1/src/stm32_userleds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include - -#include "stm32.h" -#include "b-g431b-esc1.h" - -#if !defined(CONFIG_ARCH_LEDS) - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_userled_initialize - ****************************************************************************/ - -uint32_t board_userled_initialize(void) -{ - /* Configure LED GPIOs for output */ - - stm32_configgpio(GPIO_LED1); - return BOARD_NLEDS; -} - -/**************************************************************************** - * Name: board_userled - ****************************************************************************/ - -void board_userled(int led, bool ledon) -{ - if (led == BOARD_LED1) - { - stm32_gpiowrite(GPIO_LED1, ledon); - } -} - -/**************************************************************************** - * Name: board_userled_all - ****************************************************************************/ - -void board_userled_all(uint32_t ledset) -{ - stm32_gpiowrite(GPIO_LED1, (ledset & BOARD_LED1_BIT) != 0); -} - -#endif /* !CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/b-g474e-dpow1/CMakeLists.txt b/boards/arm/stm32/b-g474e-dpow1/CMakeLists.txt deleted file mode 100644 index f0b7d812e4415..0000000000000 --- a/boards/arm/stm32/b-g474e-dpow1/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/b-g474e-dpow1/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32/b-g474e-dpow1/configs/buckboost/defconfig b/boards/arm/stm32/b-g474e-dpow1/configs/buckboost/defconfig deleted file mode 100644 index fadfe62a85213..0000000000000 --- a/boards/arm/stm32/b-g474e-dpow1/configs/buckboost/defconfig +++ /dev/null @@ -1,89 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_LEDS is not set -CONFIG_ADC=y -CONFIG_ANALOG=y -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="b-g474e-dpow1" -CONFIG_ARCH_BOARD_B_G474E_DPOW1=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32G474R=y -CONFIG_ARCH_HIPRI_INTERRUPT=y -CONFIG_ARCH_RAMVECTORS=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_DEBUG_FULLOPT=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_DISABLE_ENVIRON=y -CONFIG_DISABLE_MQUEUE=y -CONFIG_DISABLE_POSIX_TIMERS=y -CONFIG_DISABLE_PTHREAD=y -CONFIG_DRIVERS_SMPS=y -CONFIG_EXAMPLES_SMPS=y -CONFIG_EXAMPLES_SMPS_DEVPATH="/dev/smps0" -CONFIG_EXAMPLES_SMPS_IN_VOLTAGE_LIMIT=10000 -CONFIG_EXAMPLES_SMPS_OUT_CURRENT_LIMIT=100 -CONFIG_EXAMPLES_SMPS_OUT_POWER_LIMIT=100 -CONFIG_EXAMPLES_SMPS_OUT_VOLTAGE_DEFAULT=5000 -CONFIG_EXAMPLES_SMPS_OUT_VOLTAGE_LIMIT=10000 -CONFIG_EXAMPLES_SMPS_TIME_DEFAULT=10 -CONFIG_FDCLONE_STDIO=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INIT_STACKSIZE=1024 -CONFIG_INTELHEX_BINARY=y -CONFIG_LIBDSP=y -CONFIG_LIBM=y -CONFIG_LINE_MAX=64 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=256 -CONFIG_NSH_READLINE=y -CONFIG_POSIX_SPAWN_DEFAULT_STACKSIZE=512 -CONFIG_PTHREAD_STACK_DEFAULT=1024 -CONFIG_PTHREAD_STACK_MIN=1024 -CONFIG_RAM_SIZE=98304 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_SMPS_HAVE_INPUT_VOLTAGE=y -CONFIG_SMPS_HAVE_OUTPUT_VOLTAGE=y -CONFIG_START_DAY=6 -CONFIG_START_MONTH=12 -CONFIG_START_YEAR=2011 -CONFIG_STDIO_BUFFER_SIZE=128 -CONFIG_STM32_ADC1=y -CONFIG_STM32_ADC1_INJECTED_CHAN=2 -CONFIG_STM32_ADC_CHANGE_SAMPLETIME=y -CONFIG_STM32_ADC_LL_OPS=y -CONFIG_STM32_ADC_NOIRQ=y -CONFIG_STM32_CCMEXCLUDE=y -CONFIG_STM32_HRTIM1=y -CONFIG_STM32_HRTIM_ADC1_TRG2=y -CONFIG_STM32_HRTIM_ADC=y -CONFIG_STM32_HRTIM_DEADTIME=y -CONFIG_STM32_HRTIM_DISABLE_CHARDRV=y -CONFIG_STM32_HRTIM_PWM=y -CONFIG_STM32_HRTIM_TIMC=y -CONFIG_STM32_HRTIM_TIMC_DT=y -CONFIG_STM32_HRTIM_TIMC_PWM=y -CONFIG_STM32_HRTIM_TIMC_PWM_CH1=y -CONFIG_STM32_HRTIM_TIMC_PWM_CH2=y -CONFIG_STM32_HRTIM_TIMD=y -CONFIG_STM32_HRTIM_TIMD_DT=y -CONFIG_STM32_HRTIM_TIMD_PWM=y -CONFIG_STM32_HRTIM_TIMD_PWM_CH1=y -CONFIG_STM32_HRTIM_TIMD_PWM_CH2=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_PWR=y -CONFIG_STM32_USART3=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART3_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/b-g474e-dpow1/configs/nsh/defconfig b/boards/arm/stm32/b-g474e-dpow1/configs/nsh/defconfig deleted file mode 100644 index 067ed86173846..0000000000000 --- a/boards/arm/stm32/b-g474e-dpow1/configs/nsh/defconfig +++ /dev/null @@ -1,41 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_LEDS is not set -# CONFIG_DISABLE_OS_API is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="b-g474e-dpow1" -CONFIG_ARCH_BOARD_B_G474E_DPOW1=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32G474R=y -CONFIG_ARCH_HIPRI_INTERRUPT=y -CONFIG_ARCH_RAMVECTORS=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_ARMV7M_LIBM=y -CONFIG_ARMV7M_MEMCPY=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_DEBUG_FEATURES=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_LIBM=y -CONFIG_LINE_MAX=64 -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PRIORITY_INHERITANCE=y -CONFIG_RAM_SIZE=98304 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_LPWORK=y -CONFIG_SCHED_WAITPID=y -CONFIG_STM32_USART3=y -CONFIG_SYSTEM_NSH=y -CONFIG_USART3_SERIAL_CONSOLE=y -CONFIG_USERLED=y -CONFIG_USERLED_LOWER=y diff --git a/boards/arm/stm32/b-g474e-dpow1/configs/ostest/defconfig b/boards/arm/stm32/b-g474e-dpow1/configs/ostest/defconfig deleted file mode 100644 index 70a00af2020a5..0000000000000 --- a/boards/arm/stm32/b-g474e-dpow1/configs/ostest/defconfig +++ /dev/null @@ -1,43 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_LEDS is not set -# CONFIG_DISABLE_OS_API is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="b-g474e-dpow1" -CONFIG_ARCH_BOARD_B_G474E_DPOW1=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32G474R=y -CONFIG_ARCH_HIPRI_INTERRUPT=y -CONFIG_ARCH_RAMVECTORS=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_ARMV7M_LIBM=y -CONFIG_ARMV7M_MEMCPY=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_DEBUG_FEATURES=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_LIBM=y -CONFIG_LINE_MAX=64 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_RAM_SIZE=98304 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_LPWORK=y -CONFIG_SCHED_WAITPID=y -CONFIG_STM32_USART3=y -CONFIG_SYSTEM_NSH=y -CONFIG_TESTING_OSTEST=y -CONFIG_USART3_SERIAL_CONSOLE=y -CONFIG_USERLED=y -CONFIG_USERLED_LOWER=y diff --git a/boards/arm/stm32/b-g474e-dpow1/include/board.h b/boards/arm/stm32/b-g474e-dpow1/include/board.h deleted file mode 100644 index 03a0e8edd1a70..0000000000000 --- a/boards/arm/stm32/b-g474e-dpow1/include/board.h +++ /dev/null @@ -1,256 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/b-g474e-dpow1/include/board.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __BOARDS_ARM_STM32_B_G474E_DPOW1_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32_B_G474E_DPOW1_INCLUDE_BOARD_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Clocking *****************************************************************/ - -#undef STM32_BOARD_XTAL /* Not installed by default */ - -#define STM32_HSI_FREQUENCY 16000000ul /* 16MHz */ -#define STM32_LSI_FREQUENCY 32000 /* 32kHz */ -#undef STM32_HSE_FREQUENCY /* Not installed by default */ -#undef STM32_LSE_FREQUENCY /* Not available on this board */ - -/* Main PLL Configuration. - * - * PLL source is HSI = 16MHz - * PLLN = 85, PLLM = 4, PLLP = 10, PLLQ = 2, PLLR = 2 - * - * f(VCO Clock) = f(PLL Clock Input) x (PLLN / PLLM) - * f(PLL_P) = f(VCO Clock) / PLLP - * f(PLL_Q) = f(VCO Clock) / PLLQ - * f(PLL_R) = f(VCO Clock) / PLLR - * - * Where: - * 8 <= PLLN <= 127 - * 1 <= PLLM <= 16 - * PLLP = 2 through 31 - * PLLQ = 2, 4, 6, or 8 - * PLLR = 2, 4, 6, or 8 - * - * Do not exceed 170MHz on f(PLL_P), f(PLL_Q), or f(PLL_R). - * 64MHz <= f(VCO Clock) <= 344MHz. - * - * Given the above: - * - * f(VCO Clock) = HSI x PLLN / PLLM - * = 16MHz x 85 / 4 - * = 340MHz - * - * PLLPCLK = f(VCO Clock) / PLLP - * = 340MHz / 10 - * = 34MHz - * (May be used for ADC) - * - * PLLQCLK = f(VCO Clock) / PLLQ - * = 340MHz / 2 - * = 170MHz - * (May be used for QUADSPI, FDCAN, SAI1, I2S3. If set to - * 48MHz, may be used for USB, RNG.) - * - * PLLRCLK = f(VCO Clock) / PLLR - * = 340MHz / 2 - * = 170MHz - * (May be used for SYSCLK and most peripherals.) - */ - -#define STM32_PLLCFGR_PLLSRC RCC_PLLCFGR_PLLSRC_HSI -#define STM32_PLLCFGR_PLLCFG (RCC_PLLCFGR_PLLPEN | \ - RCC_PLLCFGR_PLLQEN | \ - RCC_PLLCFGR_PLLREN) - -#define STM32_PLLCFGR_PLLN RCC_PLLCFGR_PLLN(85) -#define STM32_PLLCFGR_PLLM RCC_PLLCFGR_PLLM(4) -#define STM32_PLLCFGR_PLLP RCC_PLLCFGR_PLLPDIV(10) -#define STM32_PLLCFGR_PLLQ RCC_PLLCFGR_PLLQ_2 -#define STM32_PLLCFGR_PLLR RCC_PLLCFGR_PLLR_2 - -#define STM32_VCO_FREQUENCY ((STM32_HSI_FREQUENCY / 4) * 85) -#define STM32_PLLP_FREQUENCY (STM32_VCO_FREQUENCY / 10) -#define STM32_PLLQ_FREQUENCY (STM32_VCO_FREQUENCY / 2) -#define STM32_PLLR_FREQUENCY (STM32_VCO_FREQUENCY / 2) - -/* Use the PLL and set the SYSCLK source to be PLLR (170MHz) */ - -#define STM32_SYSCLK_SW RCC_CFGR_SW_PLL -#define STM32_SYSCLK_SWS RCC_CFGR_SWS_PLL -#define STM32_SYSCLK_FREQUENCY STM32_PLLR_FREQUENCY - -/* AHB clock (HCLK) is SYSCLK (170MHz) */ - -#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK -#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY - -/* APB1 clock (PCLK1) is HCLK (170MHz) */ - -#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK -#define STM32_PCLK1_FREQUENCY STM32_HCLK_FREQUENCY - -/* APB2 clock (PCLK2) is HCLK (170MHz) */ - -#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK -#define STM32_PCLK2_FREQUENCY STM32_HCLK_FREQUENCY - -/* LED definitions **********************************************************/ - -/* The B-G474E-DPOW1 Discovery kit has four user LEDs. - * - * If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs in - * any way. The following definitions are used to access individual LEDs. - */ - -/* LED index values for use with board_userled() */ - -#define BOARD_LED1 0 /* User LD2 (Blue) */ -#define BOARD_LED2 1 /* User LD3 (Orange) */ -#define BOARD_LED3 2 /* User LD4 (Green) */ -#define BOARD_LED4 3 /* User LD5 (Red)*/ -#define BOARD_NLEDS 4 - -/* LED bits for use with board_userled_all() */ - -#define BOARD_LED1_BIT (1 << BOARD_LED1) -#define BOARD_LED2_BIT (1 << BOARD_LED2) -#define BOARD_LED3_BIT (1 << BOARD_LED3) -#define BOARD_LED4_BIT (1 << BOARD_LED4) - -/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the 4 user LEDs - * on the board. The following definitions describe how NuttX controls the - * LEDs: - * - * |--------------------|-------------------------|------------| - * | SYMBOL | Meaning | LED states | - * |--------------------|-------------------------|------------| - * | LED_STARTED | NuttX has been started | 0 0 0 0 | - * | LED_HEAPALLOCATE | Heap has been allocated | 0 0 0 0 | - * | LED_IRQSENABLED | Interrupts enabled | 0 0 0 0 | - * | LED_STACKCREATED | Idle stack created | 1 0 0 0 | - * | LED_INIRQ | In an interrupt | No change | - * | LED_SIGNAL | In a signal handler | No change | - * | LED_ASSERTION | An assertion failed | No change | - * | LED_PANIC | The system has crashed | 0 B 0 0 | - * | LED_IDLE | STM32 is in sleep mode | Not used | - * |--------------------|-------------------------|------------| - * - * LED states legend: - * 0 = off - * 1 = on - * B = blink - */ - -#define LED_STARTED 0 -#define LED_HEAPALLOCATE 0 -#define LED_IRQSENABLED 0 -#define LED_STACKCREATED 1 -#define LED_INIRQ 2 -#define LED_SIGNAL 2 -#define LED_ASSERTION 2 -#define LED_PANIC 3 - -/* Button definitions *******************************************************/ - -/* Alternate function pin selections ****************************************/ - -/* USART3 (ST LINK V3E Virtual Console) */ - -#define GPIO_USART3_TX GPIO_USART3_TX_3 /* PC10 */ -#define GPIO_USART3_RX GPIO_USART3_RX_3 /* PC11 */ - -/* Board configuration for SMPS example: - * PB12 - HRTIM1_CHC1 - * PB13 - HRTIM1_CHC2 - * PB14 - HRTIM1_CHD1 - * PB15 - HRTIM1_CHD2 - * VIN - ADC Channel 2 (PA1) - * VOUT - ADC Channel 4 (PA3) - */ - -#if defined(CONFIG_EXAMPLES_SMPS) - -/* HRTIM configuration ******************************************************/ - -/* Timer C configuration - Buck operations */ - -#define HRTIM_TIMC_PRESCALER HRTIM_PRESCALER_1 -#define HRTIM_TIMC_MODE HRTIM_MODE_CONT -#define HRTIM_TIMC_UPDATE 0 -#define HRTIM_TIMC_RESET 0 - -#define HRTIM_TIMC_CH1_SET HRTIM_OUT_SET_NONE -#define HRTIM_TIMC_CH1_RST HRTIM_OUT_RST_NONE -#define HRTIM_TIMC_CH2_SET HRTIM_OUT_SET_NONE -#define HRTIM_TIMC_CH2_RST HRTIM_OUT_RST_NONE - -#define HRTIM_TIMC_DT_FSLOCK HRTIM_DT_LOCK -#define HRTIM_TIMC_DT_RSLOCK HRTIM_DT_LOCK -#define HRTIM_TIMC_DT_FVLOCK HRTIM_DT_RW -#define HRTIM_TIMC_DT_RVLOCK HRTIM_DT_RW -#define HRTIM_TIMC_DT_FSIGN HRTIM_DT_SIGN_POSITIVE -#define HRTIM_TIMC_DT_RSIGN HRTIM_DT_SIGN_POSITIVE -#define HRTIM_TIMC_DT_PRESCALER HRTIM_DEADTIME_PRESCALER_1 - -/* Timer D configuration - Boost operations */ - -#define HRTIM_TIMD_PRESCALER HRTIM_PRESCALER_1 -#define HRTIM_TIMD_MODE HRTIM_MODE_CONT -#define HRTIM_TIMD_UPDATE 0 -#define HRTIM_TIMD_RESET 0 - -#define HRTIM_TIMD_CH1_SET HRTIM_OUT_SET_NONE -#define HRTIM_TIMD_CH1_RST HRTIM_OUT_RST_NONE -#define HRTIM_TIMD_CH2_SET HRTIM_OUT_SET_NONE -#define HRTIM_TIMD_CH2_RST HRTIM_OUT_RST_NONE - -#define HRTIM_TIMD_DT_FSLOCK HRTIM_DT_LOCK -#define HRTIM_TIMD_DT_RSLOCK HRTIM_DT_LOCK -#define HRTIM_TIMD_DT_FVLOCK HRTIM_DT_RW -#define HRTIM_TIMD_DT_RVLOCK HRTIM_DT_RW -#define HRTIM_TIMD_DT_FSIGN HRTIM_DT_SIGN_POSITIVE -#define HRTIM_TIMD_DT_RSIGN HRTIM_DT_SIGN_POSITIVE -#define HRTIM_TIMD_DT_PRESCALER HRTIM_DEADTIME_PRESCALER_1 - -#define HRTIM_ADC_TRG2 HRTIM_ADCTRG24_CC4 - -/* DMA channels *************************************************************/ - -#endif /* CONFIG_EXAMPLES_SMPS */ - -/* HRTIM */ - -#define GPIO_HRTIM1_CHC1 GPIO_HRTIM1_CHC1_0 -#define GPIO_HRTIM1_CHC2 GPIO_HRTIM1_CHC2_0 -#define GPIO_HRTIM1_CHD1 GPIO_HRTIM1_CHD1_0 -#define GPIO_HRTIM1_CHD2 GPIO_HRTIM1_CHD2_0 - -#endif /* __BOARDS_ARM_STM32_B_G474E_DPOW1_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32/b-g474e-dpow1/scripts/Make.defs b/boards/arm/stm32/b-g474e-dpow1/scripts/Make.defs deleted file mode 100644 index 57c27ead5ec10..0000000000000 --- a/boards/arm/stm32/b-g474e-dpow1/scripts/Make.defs +++ /dev/null @@ -1,51 +0,0 @@ -############################################################################ -# boards/arm/stm32/b-g474e-dpow1/scripts/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/.config -include $(TOPDIR)/tools/Config.mk -include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs - -ifeq ($(CONFIG_STM32_DFU),y) - LDSCRIPT = ld.script.dfu -else - LDSCRIPT = ld.script -endif - -ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) - -ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 - -CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) -CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) -CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -AFLAGS := $(CFLAGS) -D__ASSEMBLY__ - -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections -LDNXFLATFLAGS = -e main -s 2048 - -# Embed absolute path to source file in debug information so that Eclipse -# source level debugging won't get confused. See: -# https://stackoverflow.com/questions/1275476/gcc-gdb-how-to-embed-absolute-path-to-source-file-in-debug-information -CFLAGS += -fdebug-prefix-map=..=$(readlink -f ..) diff --git a/boards/arm/stm32/b-g474e-dpow1/scripts/ld.script b/boards/arm/stm32/b-g474e-dpow1/scripts/ld.script deleted file mode 100644 index 64c1953f7fcef..0000000000000 --- a/boards/arm/stm32/b-g474e-dpow1/scripts/ld.script +++ /dev/null @@ -1,139 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/b-g474e-dpow1/scripts/ld.script - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* The STM32G474RE has 512 KiB of FLASH beginning at address 0x0800:0000. - * - * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 - * where the code expects to begin execution by jumping to the entry point in - * the 0x0800:0000 address range. - * - * The STM32G474RE has a total of 128 KiB of SRAM in three separate areas: - * - * 1) 80 KiB SRAM1 mapped at 0x2000:0000 thru 0x2001:3fff. - * 2) 16 KiB SRAM2 mapped at 0x2001:4000 thru 0x2001:7fff. - * - * CCM SRAM (Routine Booster): - * - * 3) 32 KiB CCM SRAM mapped at 0x1000:0000 thru 0x1000:7fff - * but also aliased at at 0x2001:8000 thru 0x2001:ffff to be contiguous - * with the SRAM1 and SRAM2. - * - * Because SRAM1 and SRAM2 are contiguous, they are treated as one region - * by this logic. - * - * CCM SRAM is also contiguous to SRAM1 and SRAM2, however it is excluded - * from this linker script, to keep it reserved for special uses in code. - * REVISIT: Is this the correct way to handle CCM SRAM? - */ - -MEMORY -{ - flash (rx) : ORIGIN = 0x08000000, LENGTH = 512K - sram (rwx) : ORIGIN = 0x20000000, LENGTH = 96K -} - -OUTPUT_ARCH(arm) -EXTERN(_vectors) -ENTRY(_stext) - -SECTIONS -{ - .text : { - _stext = ABSOLUTE(.); - *(.vectors) - *(.text .text.*) - *(.fixup) - *(.gnu.warning) - *(.rodata .rodata.*) - *(.gnu.linkonce.t.*) - *(.glue_7) - *(.glue_7t) - *(.got) - *(.gcc_except_table) - *(.gnu.linkonce.r.*) - _etext = ABSOLUTE(.); - } > flash - - .init_section : ALIGN(4) { - _sinit = ABSOLUTE(.); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) - KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) - _einit = ABSOLUTE(.); - } > flash - - .ARM.extab : ALIGN(4) { - *(.ARM.extab*) - } > flash - - .ARM.exidx : ALIGN(4) { - __exidx_start = ABSOLUTE(.); - *(.ARM.exidx*) - __exidx_end = ABSOLUTE(.); - } > flash - - .tdata : { - _stdata = ABSOLUTE(.); - *(.tdata .tdata.* .gnu.linkonce.td.*); - _etdata = ABSOLUTE(.); - } > flash - - .tbss : { - _stbss = ABSOLUTE(.); - *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); - _etbss = ABSOLUTE(.); - } > flash - - _eronly = ABSOLUTE(.); - - .data : ALIGN(4) { - _sdata = ABSOLUTE(.); - *(.data .data.*) - *(.gnu.linkonce.d.*) - CONSTRUCTORS - . = ALIGN(4); - _edata = ABSOLUTE(.); - } > sram AT > flash - - .bss : ALIGN(4) { - _sbss = ABSOLUTE(.); - *(.bss .bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - . = ALIGN(4); - _ebss = ABSOLUTE(.); - } > sram - - /* Stabs debugging sections. */ - - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_info 0 : { *(.debug_info) } - .debug_line 0 : { *(.debug_line) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_aranges 0 : { *(.debug_aranges) } -} diff --git a/boards/arm/stm32/b-g474e-dpow1/scripts/ld.script.dfu b/boards/arm/stm32/b-g474e-dpow1/scripts/ld.script.dfu deleted file mode 100644 index d27ca98a1445b..0000000000000 --- a/boards/arm/stm32/b-g474e-dpow1/scripts/ld.script.dfu +++ /dev/null @@ -1,142 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/b-g474e-dpow1/scripts/ld.script - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* The STM32G474RE has 512 KiB of FLASH beginning at address 0x0800:0000. - * - * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 - * where the code expects to begin execution by jumping to the entry point in - * the 0x0800:0000 address range. The FLASH bootloader is located there and - * allocated up to 24KiB (6 pages of 4k if single bank mode or 12 pages of 2k - * if dual bank mode), so our executable will begin at 0x0800:6000, leaving - * 488KiB. - * - * The STM32G474RE has a total of 128 KiB of SRAM in three separate areas: - * - * 1) 80 KiB SRAM1 mapped at 0x2000:0000 thru 0x2001:3fff. - * 2) 16 KiB SRAM2 mapped at 0x2001:4000 thru 0x2001:7fff. - * - * CCM SRAM (Routine Booster): - * - * 3) 32 KiB CCM SRAM mapped at 0x1000:0000 thru 0x1000:7fff - * but also aliased at at 0x2001:8000 thru 0x2001:ffff to be contiguous - * with the SRAM1 and SRAM2. - * - * Because SRAM1 and SRAM2 are contiguous, they are treated as one region - * by this logic. - * - * CCM SRAM is also contiguous to SRAM1 and SRAM2, however it is excluded - * from this linker script, to keep it reserved for special uses in code. - * REVISIT: Is this the correct way to handle CCM SRAM? - */ - -MEMORY -{ - flash (rx) : ORIGIN = 0x08006000, LENGTH = 488K - sram (rwx) : ORIGIN = 0x20000000, LENGTH = 96K -} - -OUTPUT_ARCH(arm) -EXTERN(_vectors) -ENTRY(_stext) - -SECTIONS -{ - .text : { - _stext = ABSOLUTE(.); - *(.vectors) - *(.text .text.*) - *(.fixup) - *(.gnu.warning) - *(.rodata .rodata.*) - *(.gnu.linkonce.t.*) - *(.glue_7) - *(.glue_7t) - *(.got) - *(.gcc_except_table) - *(.gnu.linkonce.r.*) - _etext = ABSOLUTE(.); - } > flash - - .init_section : ALIGN(4) { - _sinit = ABSOLUTE(.); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) - KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) - _einit = ABSOLUTE(.); - } > flash - - .ARM.extab : ALIGN(4) { - *(.ARM.extab*) - } > flash - - .ARM.exidx : ALIGN(4) { - __exidx_start = ABSOLUTE(.); - *(.ARM.exidx*) - __exidx_end = ABSOLUTE(.); - } > flash - - .tdata : { - _stdata = ABSOLUTE(.); - *(.tdata .tdata.* .gnu.linkonce.td.*); - _etdata = ABSOLUTE(.); - } > flash - - .tbss : { - _stbss = ABSOLUTE(.); - *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); - _etbss = ABSOLUTE(.); - } > flash - - _eronly = ABSOLUTE(.); - - .data : ALIGN(4) { - _sdata = ABSOLUTE(.); - *(.data .data.*) - *(.gnu.linkonce.d.*) - CONSTRUCTORS - . = ALIGN(4); - _edata = ABSOLUTE(.); - } > sram AT > flash - - .bss : ALIGN(4) { - _sbss = ABSOLUTE(.); - *(.bss .bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - . = ALIGN(4); - _ebss = ABSOLUTE(.); - } > sram - - /* Stabs debugging sections. */ - - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_info 0 : { *(.debug_info) } - .debug_line 0 : { *(.debug_line) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_aranges 0 : { *(.debug_aranges) } -} diff --git a/boards/arm/stm32/b-g474e-dpow1/src/CMakeLists.txt b/boards/arm/stm32/b-g474e-dpow1/src/CMakeLists.txt deleted file mode 100644 index 87e3c2b6ee9b7..0000000000000 --- a/boards/arm/stm32/b-g474e-dpow1/src/CMakeLists.txt +++ /dev/null @@ -1,37 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/b-g474e-dpow1/src/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -set(SRCS stm32_boot.c) - -if(CONFIG_ARCH_LEDS) - list(APPEND SRCS stm32_autoleds.c) -else() - list(APPEND SRCS stm32_userleds.c) -endif() - -if(CONFIG_DRIVERS_SMPS) - list(APPEND SRCS stm32_smps.c) -endif() - -target_sources(board PRIVATE ${SRCS}) - -set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/ld.script") diff --git a/boards/arm/stm32/b-g474e-dpow1/src/Make.defs b/boards/arm/stm32/b-g474e-dpow1/src/Make.defs deleted file mode 100644 index e91f93fd7a573..0000000000000 --- a/boards/arm/stm32/b-g474e-dpow1/src/Make.defs +++ /dev/null @@ -1,40 +0,0 @@ -############################################################################ -# boards/arm/stm32/b-g474e-dpow1/src/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/Make.defs - -ASRCS = -CSRCS = stm32_boot.c - -ifeq ($(CONFIG_ARCH_LEDS),y) -CSRCS += stm32_autoleds.c -else -CSRCS += stm32_userleds.c -endif - -ifeq ($(CONFIG_DRIVERS_SMPS),y) -CSRCS += stm32_smps.c -endif - -DEPPATH += --dep-path board -VPATH += :board -CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/b-g474e-dpow1/src/stm32_autoleds.c b/boards/arm/stm32/b-g474e-dpow1/src/stm32_autoleds.c deleted file mode 100644 index 1591f068d43bd..0000000000000 --- a/boards/arm/stm32/b-g474e-dpow1/src/stm32_autoleds.c +++ /dev/null @@ -1,111 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/b-g474e-dpow1/src/stm32_autoleds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include "stm32.h" -#include "b-g474e-dpow1.h" - -#if defined(CONFIG_ARCH_LEDS) - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_autoled_initialize - ****************************************************************************/ - -void board_autoled_initialize(void) -{ - /* Configure LED GPIOs for output */ - - stm32_configgpio(GPIO_LED1); - stm32_configgpio(GPIO_LED2); - stm32_configgpio(GPIO_LED3); - stm32_configgpio(GPIO_LED4); -} - -/**************************************************************************** - * Name: board_autoled_on - ****************************************************************************/ - -void board_autoled_on(int led) -{ - switch (led) - { - case BOARD_LED1: - stm32_gpiowrite(GPIO_LED1, true); - break; - - case BOARD_LED2: - stm32_gpiowrite(GPIO_LED2, true); - break; - - case BOARD_LED3: - stm32_gpiowrite(GPIO_LED3, true); - break; - - case BOARD_LED4: - stm32_gpiowrite(GPIO_LED4, true); - break; - } -} - -/**************************************************************************** - * Name: board_autoled_off - ****************************************************************************/ - -void board_autoled_off(int led) -{ - switch (led) - { - case BOARD_LED1: - stm32_gpiowrite(GPIO_LED1, false); - break; - - case BOARD_LED2: - stm32_gpiowrite(GPIO_LED2, false); - break; - - case BOARD_LED3: - stm32_gpiowrite(GPIO_LED3, false); - break; - - case BOARD_LED4: - stm32_gpiowrite(GPIO_LED4, false); - break; - } -} - -#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/b-g474e-dpow1/src/stm32_boot.c b/boards/arm/stm32/b-g474e-dpow1/src/stm32_boot.c deleted file mode 100644 index f901b448b028d..0000000000000 --- a/boards/arm/stm32/b-g474e-dpow1/src/stm32_boot.c +++ /dev/null @@ -1,125 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/b-g474e-dpow1/src/stm32_boot.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include -#include - -#include "b-g474e-dpow1.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#undef HAVE_LEDS - -#if !defined(CONFIG_ARCH_LEDS) && defined(CONFIG_USERLED_LOWER) -# define HAVE_LEDS 1 -#endif - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_boardinitialize - * - * Description: - * All STM32 architectures must provide the following entry point. This - * entry point is called early in the initialization -- after all memory - * has been configured and mapped but before any devices have been - * initialized. - * - ****************************************************************************/ - -void stm32_boardinitialize(void) -{ -#if defined(CONFIG_ARCH_LEDS) - /* Configure on-board LEDs if LED support has been selected. */ - - board_autoled_initialize(); -#endif -} - -/**************************************************************************** - * Name: board_late_initialize - * - * Description: - * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional - * initialization call will be performed in the boot-up sequence to a - * function called board_late_initialize(). board_late_initialize() will be - * called immediately after up_initialize() is called and just before the - * initial application is started. This additional initialization phase - * may be used, for example, to initialize board-specific device drivers. - * - ****************************************************************************/ - -#ifdef CONFIG_BOARD_LATE_INITIALIZE -void board_late_initialize(void) -{ - int ret; - -#if defined(HAVE_LEDS) - /* Register the LED driver */ - - ret = userled_lower_initialize(LED_DRIVER_PATH); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: userled_lower_initialize() failed: %d\n", ret); - return; - } -#endif - -#ifdef CONFIG_DRIVERS_SMPS - /* Initialize smps and register the smps driver */ - - ret = stm32_smps_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_smps_setup failed: %d\n", ret); - } -#endif - - UNUSED(ret); -} -#endif diff --git a/boards/arm/stm32/b-g474e-dpow1/src/stm32_smps.c b/boards/arm/stm32/b-g474e-dpow1/src/stm32_smps.c deleted file mode 100644 index b2496a63d859b..0000000000000 --- a/boards/arm/stm32/b-g474e-dpow1/src/stm32_smps.c +++ /dev/null @@ -1,1262 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/b-g474e-dpow1/src/stm32_smps.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include - -#include - -#include "arm_internal.h" -#include "ram_vectors.h" - -#include "stm32_hrtim.h" -#include "stm32_adc.h" - -#include - -#if defined(CONFIG_EXAMPLES_SMPS) && defined(CONFIG_DRIVERS_SMPS) - -#ifndef CONFIG_LIBDSP -# error CONFIG_LIBDSP is required -#endif - -#ifndef CONFIG_ARCH_HIPRI_INTERRUPT -# error CONFIG_ARCH_HIPRI_INTERRUPT is required -#endif - -#ifndef CONFIG_ARCH_RAMVECTORS -# error CONFIG_ARCH_RAMVECTORS is required -#endif - -#ifndef CONFIG_ARCH_IRQPRIO -# error CONFIG_ARCH_IRQPRIO is required -#endif - -#ifndef CONFIG_ARCH_FPU -# warning Set CONFIG_ARCH_FPU for hardware FPU support -#endif - -#if !defined(CONFIG_STM32_HRTIM1) || !defined(CONFIG_STM32_HRTIM) -# error "SMPS example requires HRTIM1 support" -#endif - -#if !defined(CONFIG_STM32_ADC1) || !defined(CONFIG_ADC) -# error "SMPS example requires ADC1 support" -#endif - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* ADC1 channels used in this example */ - -#define ADC1_NCHANNELS 2 - -/* ADC1 injected channels numeration */ - -#define V_IN_ADC_INJ_CHANNEL 0 -#define V_OUT_ADC_INJ_CHANNEL 1 - -/* Voltage reference for ADC */ - -#define ADC_REF_VOLTAGE ((float)3.3) - -/* ADC resolution */ - -#define ADC_VAL_MAX 4095 - -/* Input voltage conversion ratio - 6.8k/(6.8k + 27k) */ - -#define V_IN_RATIO (float)((float)(6800+27000)/(float)6800) - -/* Output voltage conversion ratio - 3.3k/(3.3k + 13.3k) */ - -#define V_OUT_RATIO (float)((float)(3300+13300)/(float)3300) - -/* Some absolute limits */ - -#define SMPS_ABSOLUTE_OUT_CURRENT_LIMIT_mA 250 -#define SMPS_ABSOLUTE_OUT_VOLTAGE_LIMIT_mV 15000 -#define SMPS_ABSOLUTE_IN_VOLTAGE_LIMIT_mV 15000 - -#if CONFIG_EXAMPLES_SMPS_OUT_CURRENT_LIMIT > SMPS_ABSOLUTE_OUT_CURRENT_LIMIT_mA -# error "Output current limit great than absolute limit!" -#endif -#if CONFIG_EXAMPLES_SMPS_OUT_VOLTAGE_LIMIT > SMPS_ABSOLUTE_OUT_VOLTAGE_LIMIT_mV -# error "Output voltage limit greater than absolute limit!" -#endif -#if CONFIG_EXAMPLES_SMPS_IN_VOLTAGE_LIMIT > SMPS_ABSOLUTE_IN_VOLTAGE_LIMIT_mV -# error "Input voltage limit greater than absolute limit!" -#endif - -/* Maximum output voltage for boost converter in float */ - -#define BOOST_VOLT_MAX ((float)CONFIG_EXAMPLES_SMPS_OUT_VOLTAGE_LIMIT/1000.0) - -/* At this time only PID controller implemented */ - -#define SMPS_CONTROLLER_PID 1 - -/* Converter's finite accuracy */ - -#define SMPS_VOLTAGE_ACCURACY ((float)0.01) - -/* Buck-boost mode threshold */ - -#define SMPS_BUCKBOOST_RANGE ((float)0.5) - -/* PID controller configuration */ - -#define PID_KP ((float)1.0) -#define PID_KI ((float)0.1) -#define PID_KD ((float)0.0) - -/* Converter frequencies: - * - TIMC_PWM_FREQ - buck converter 250kHz - * - TIMD_PWM_FREQ - boost converter 250kHz - */ - -#define TIMC_PWM_FREQ 250000 -#define TIMD_PWM_FREQ 250000 - -/* Deadtime configuration */ - -#define DT_RISING 0x0B0 -#define DT_FALLING 0x0B0 - -/* Helper macros */ - -#define HRTIM_ALL_OUTPUTS_ENABLE(hrtim, state) \ - HRTIM_OUTPUTS_ENABLE(hrtim, HRTIM_OUT_TIMC_CH1|HRTIM_OUT_TIMC_CH2| \ - HRTIM_OUT_TIMD_CH1|HRTIM_OUT_TIMD_CH2, state); - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/* Current converter mode */ - -enum converter_mode_e -{ - CONVERTER_MODE_INIT, /* Initial mode */ - CONVERTER_MODE_BUCK, /* Buck mode operations (V_in > V_out) */ - CONVERTER_MODE_BOOST, /* Boost mode operations (V_in < V_out) */ - CONVERTER_MODE_BUCKBOOST, /* Buck-boost operations (V_in near V_out) */ -}; - -/* SMPS lower drivers structure */ - -struct smps_lower_dev_s -{ - struct hrtim_dev_s *hrtim; /* PWM generation */ - struct stm32_adc_dev_s *adc; /* input and output voltage sense */ - struct comp_dev_s *comp; /* not used in this demo - only as reference */ - struct dac_dev_s *dac; /* not used in this demo - only as reference */ - struct opamp_dev_s *opamp; /* not used in this demo - only as reference */ -}; - -/* Private data for smps */ - -struct smps_priv_s -{ - uint8_t conv_mode; /* Converter mode */ - uint16_t v_in_raw; /* Voltage input RAW value */ - uint16_t v_out_raw; /* Voltage output RAW value */ - float v_in; /* Voltage input real value in V */ - float v_out; /* Voltage output real value in V */ - bool running; /* Running flag */ - pid_controller_f32_t pid; /* PID controller */ - float *c_limit_tab; /* Current limit tab */ -}; - -/**************************************************************************** - * Private Function Protototypes - ****************************************************************************/ - -static int smps_setup(struct smps_dev_s *dev); -static int smps_shutdown(struct smps_dev_s *dev); -static int smps_start(struct smps_dev_s *dev); -static int smps_stop(struct smps_dev_s *dev); -static int smps_params_set(struct smps_dev_s *dev, - struct smps_params_s *param); -static int smps_mode_set(struct smps_dev_s *dev, uint8_t mode); -static int smps_limits_set(struct smps_dev_s *dev, - struct smps_limits_s *limits); -static int smps_state_get(struct smps_dev_s *dev, - struct smps_state_s *state); -static int smps_fault_set(struct smps_dev_s *dev, uint8_t fault); -static int smps_fault_get(struct smps_dev_s *dev, - uint8_t *fault); -static int smps_fault_clean(struct smps_dev_s *dev, - uint8_t fault); -static int smps_ioctl(struct smps_dev_s *dev, int cmd, - unsigned long arg); - -static void smps_conv_mode_set(struct smps_priv_s *priv, - struct smps_lower_dev_s *lower, - uint8_t mode); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -struct smps_lower_dev_s g_smps_lower; -struct smps_priv_s g_smps_priv; -struct smps_s g_smps; - -struct smps_ops_s g_smps_ops = -{ - .setup = smps_setup, - .shutdown = smps_shutdown, - .start = smps_start, - .stop = smps_stop, - .params_set = smps_params_set, - .mode_set = smps_mode_set, - .limits_set = smps_limits_set, - .fault_set = smps_fault_set, - .state_get = smps_state_get, - .fault_get = smps_fault_get, - .fault_clean = smps_fault_clean, - .ioctl = smps_ioctl -}; - -struct smps_dev_s g_smps_dev = -{ - .ops = &g_smps_ops, - .priv = &g_smps, - .lower = NULL -}; - -/* ADC configuration: - * - Input voltage (V_IN) - ADC1 Channel 2 (PA1) - * - Output voltage (V_OUT) - ADC1 Channel 4 (PA3) - * - * ADC channels configured in injected mode. - * - * Transistors configuration in buck mode: - * - T6 - ON - * - T2 - OFF - * - T5 and T1 - buck operation - * Transistors configuration in boost mode: - * - T5 - ON - * - T1 - OFF - * - T6 and T2 - boost operation - * Transistors configuration in buck-boost mode: - * - T5 and T1 - buck operation - * - T6 and T2 - boost operation - * - * HRTIM outputs configuration: - * - T5 -> PB12 -> HRTIM_CHC1 - * - T6 -> PB14 -> HRTIM_CHD1 - * - T1 -> PB13 -> HRTIM_CHC2 - * - T2 -> PB15 -> HRTIM_CHD2 - */ - -/* ADC channel list */ - -static const uint8_t g_adc1chan[ADC1_NCHANNELS] = -{ - 2, - 4 -}; - -/* Configurations of pins used by ADC channel */ - -static const uint32_t g_adc1pins[ADC1_NCHANNELS] = -{ - GPIO_ADC1_IN2_0, /* PA1 - V_IN */ - GPIO_ADC1_IN4_0, /* PA3 - V_OUT */ -}; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: smps_setup - * - * Description: - * - * Returned Value: - * 0 on success, a negated errno value on failure - * - ****************************************************************************/ - -static int smps_setup(struct smps_dev_s *dev) -{ - struct smps_lower_dev_s *lower = dev->lower; - struct smps_s *smps = (struct smps_s *)dev->priv; - struct hrtim_dev_s *hrtim = NULL; - struct stm32_adc_dev_s *adc = NULL; - struct smps_priv_s *priv; - struct adc_channel_s channels[ADC1_NCHANNELS]; - struct adc_sample_time_s stime; - int ret = OK; - int i = 0; - - /* Initialize smps structure */ - - smps->opmode = SMPS_OPMODE_INIT; - smps->state.state = SMPS_STATE_INIT; - smps->priv = &g_smps_priv; - - /* Check lower half drivers */ - - hrtim = lower->hrtim; - if (hrtim == NULL) - { - pwrerr("ERROR: Failed to get hrtim "); - ret = ERROR; - goto errout; - } - - adc = lower->adc; - if (adc == NULL) - { - pwrerr("ERROR: Failed to get ADC lower level interface"); - ret = ERROR; - goto errout; - } - - /* Update ADC sample time */ - - for (i = 0; i < ADC1_NCHANNELS; i += 1) - { - channels[i].sample_time = ADC_SMPR_92p5; - channels[i].channel = g_adc1chan[i]; - } - - memset(&stime, 0, sizeof(struct adc_sample_time_s)); - - stime.channels_nbr = ADC1_NCHANNELS; - stime.channel = channels; - - STM32_ADC_SAMPLETIME_SET(adc, &stime); - STM32_ADC_SAMPLETIME_WRITE(adc); - - /* TODO: create current limit table */ - - UNUSED(priv); - -errout: - return ret; -} - -/**************************************************************************** - * Name: smps_shutdown - * - * Description: - * - * Returned Value: - * 0 on success, a negated errno value on failure - * - ****************************************************************************/ - -static int smps_shutdown(struct smps_dev_s *dev) -{ - struct smps_s *smps = (struct smps_s *)dev->priv; - struct smps_priv_s *priv = (struct smps_priv_s *)smps->priv; - - /* Stop smps if running */ - - if (priv->running == true) - { - smps_stop(dev); - } - - /* Reset smps structure */ - - memset(smps, 0, sizeof(struct smps_s)); - - return OK; -} - -/**************************************************************************** - * Name: smps_start - * - * Description: - * - * Returned Value: - * 0 on success, a negated errno value on failure - * - ****************************************************************************/ - -static int smps_start(struct smps_dev_s *dev) -{ - struct smps_lower_dev_s *lower = dev->lower; - struct smps_s *smps = (struct smps_s *)dev->priv; - struct smps_priv_s *priv = (struct smps_priv_s *)smps->priv; - struct hrtim_dev_s *hrtim = lower->hrtim; - struct stm32_adc_dev_s *adc = lower->adc; - volatile uint64_t per = 0; - uint64_t fclk = 0; - int ret = OK; - - /* Disable HRTIM outputs */ - - HRTIM_ALL_OUTPUTS_ENABLE(hrtim, false); - - /* Reset SMPS private structure */ - - memset(priv, 0, sizeof(struct smps_priv_s)); - -#ifdef SMPS_CONTROLLER_PID - /* Initialize PID controller */ - - pid_controller_init(&priv->pid, PID_KP, PID_KI, PID_KD); - - /* Set PID controller saturation */ - - pid_saturation_set(&priv->pid, 0.0, BOOST_VOLT_MAX); - - /* Reset PI integral if saturated */ - - pi_ireset_enable(&priv->pid, true); -#endif - - /* Get TIMC period value for given frequency */ - - fclk = HRTIM_FCLK_GET(hrtim, HRTIM_TIMER_TIMC); - per = fclk / TIMC_PWM_FREQ; - if (per > HRTIM_PER_MAX) - { - pwrerr("ERROR: Can not achieve timc pwm " - "freq=%" PRIu32 " if fclk=%" PRIu64 "\n", - (uint32_t)TIMC_PWM_FREQ, fclk); - ret = -EINVAL; - goto errout; - } - - /* Set TIMC period value */ - - HRTIM_PER_SET(hrtim, HRTIM_TIMER_TIMC, (uint16_t)per); - - /* Get TIMD period value for given frequency */ - - fclk = HRTIM_FCLK_GET(hrtim, HRTIM_TIMER_TIMD); - per = fclk / TIMD_PWM_FREQ; - if (per > HRTIM_PER_MAX) - { - pwrerr("ERROR: Can not achieve timd pwm " - "freq=%" PRIu32 " if fclk=%" PRIu64 "\n", - (uint32_t)TIMD_PWM_FREQ, fclk); - ret = -EINVAL; - goto errout; - } - - /* Set TIMD period value */ - - HRTIM_PER_SET(hrtim, HRTIM_TIMER_TIMD, (uint16_t)per); - - /* ADC trigger on TIMC CMP4 */ - - HRTIM_CMP_SET(hrtim, HRTIM_TIMER_TIMC, HRTIM_CMP4, 10000); - - /* Configure TIMER C and TIMER D deadtime mode - * - * NOTE: In deadtime mode we have to configure output 1 only - * (SETx1, RSTx1), output 2 configuration is not significant. - */ - - HRTIM_DEADTIME_UPDATE(hrtim, HRTIM_TIMER_TIMC, HRTIM_DT_EDGE_RISING, - DT_RISING); - HRTIM_DEADTIME_UPDATE(hrtim, HRTIM_TIMER_TIMC, HRTIM_DT_EDGE_FALLING, - DT_FALLING); - HRTIM_DEADTIME_UPDATE(hrtim, HRTIM_TIMER_TIMD, HRTIM_DT_EDGE_RISING, - DT_RISING); - HRTIM_DEADTIME_UPDATE(hrtim, HRTIM_TIMER_TIMD, HRTIM_DT_EDGE_FALLING, - DT_FALLING); - - /* Set T5 and T2 to a low state. - * Deadtime mode force T1 and T6 to a high state. - */ - - HRTIM_OUTPUT_SET_SET(hrtim, HRTIM_OUT_TIMC_CH1, HRTIM_OUT_SET_NONE); - HRTIM_OUTPUT_RST_SET(hrtim, HRTIM_OUT_TIMC_CH1, HRTIM_OUT_RST_PER); - - HRTIM_OUTPUT_SET_SET(hrtim, HRTIM_OUT_TIMD_CH1, HRTIM_OUT_SET_NONE); - HRTIM_OUTPUT_RST_SET(hrtim, HRTIM_OUT_TIMD_CH1, HRTIM_OUT_RST_PER); - - /* Set running flag */ - - priv->running = true; - - HRTIM_ALL_OUTPUTS_ENABLE(hrtim, true); - - /* Enable ADC JEOS interrupts */ - - STM32_ADC_INT_ENABLE(adc, ADC_INT_JEOS); - - /* Enable ADC12 interrupts */ - - up_enable_irq(STM32_IRQ_ADC12); - - /* Start injected conversion */ - - STM32_ADC_INJ_STARTCONV(adc, true); - -errout: - return ret; -} - -/**************************************************************************** - * Name: smps_stop - * - * Description: - * - * Returned Value: - * 0 on success, a negated errno value on failure - * - ****************************************************************************/ - -static int smps_stop(struct smps_dev_s *dev) -{ - struct smps_lower_dev_s *lower = dev->lower; - struct smps_s *smps = (struct smps_s *)dev->priv; - struct smps_priv_s *priv = (struct smps_priv_s *)smps->priv; - struct hrtim_dev_s *hrtim = lower->hrtim; - struct stm32_adc_dev_s *adc = lower->adc; - - /* Disable HRTIM outputs */ - - HRTIM_ALL_OUTPUTS_ENABLE(hrtim, false); - - /* Stop injected conversion */ - - STM32_ADC_INJ_STARTCONV(adc, false); - - /* Disable ADC JEOS interrupts */ - - STM32_ADC_INT_DISABLE(adc, ADC_INT_JEOS); - - /* Disable ADC12 interrupts */ - - up_disable_irq(STM32_IRQ_ADC12); - - /* Reset running flag */ - - priv->running = false; - - return OK; -} - -/**************************************************************************** - * Name: smps_params_set - * - * Description: - * - * Returned Value: - * 0 on success, a negated errno value on failure - * - ****************************************************************************/ - -static int smps_params_set(struct smps_dev_s *dev, - struct smps_params_s *param) -{ - struct smps_s *smps = (struct smps_s *)dev->priv; - int ret = OK; - - /* Only output voltage */ - - smps->param.v_out = param->v_out; - - /* REVISIT: use current and power parameters ? */ - - if (param->i_out > 0) - { - pwrwarn("WARNING: Output current parameters not used in this demo\n"); - } - - if (param->p_out > 0) - { - pwrwarn("WARNING: Output power parameters not used in this demo\n"); - } - - return ret; -} - -/**************************************************************************** - * Name: smps_mode_set - * - * Description: - * - * Returned Value: - * 0 on success, a negated errno value on failure - * - ****************************************************************************/ - -static int smps_mode_set(struct smps_dev_s *dev, uint8_t mode) -{ - struct smps_s *smps = (struct smps_s *)dev->priv; - int ret = OK; - - /* Only constant voltage mode supported */ - - if (mode == SMPS_OPMODE_CV) - { - smps->opmode = mode; - } - else - { - pwrerr("ERROR: Unsupported SMPS mode %d!\n", mode); - ret = ERROR; - goto errout; - } - -errout: - return ret; -} - -/**************************************************************************** - * Name: smps_limits_set - * - * Description: - * - * Returned Value: - * 0 on success, a negated errno value on failure - * - ****************************************************************************/ - -static int smps_limits_set(struct smps_dev_s *dev, - struct smps_limits_s *limits) -{ - struct smps_s *smps = (struct smps_s *)dev->priv; - int ret = OK; - - /* Some assertions */ - - if (limits->v_out <= 0) - { - pwrerr("ERROR: Output voltage limit must be set!\n"); - ret = ERROR; - goto errout; - } - - if (limits->v_in <= 0) - { - pwrerr("ERROR: Input voltage limit must be set!\n"); - ret = ERROR; - goto errout; - } - - if (limits->i_out <= 0) - { - pwrerr("ERROR: Output current limit must be set!\n"); - ret = ERROR; - goto errout; - } - - if (limits->v_out * 1000 > CONFIG_EXAMPLES_SMPS_OUT_VOLTAGE_LIMIT) - { - limits->v_out = (float)CONFIG_EXAMPLES_SMPS_OUT_VOLTAGE_LIMIT / 1000.0; - pwrwarn("WARNING: " - "SMPS output voltage limiit > SMPS absolute output voltage " - "limit. Set output voltage limit to %.2f.\n", - limits->v_out); - } - - if (limits->v_in * 1000 > CONFIG_EXAMPLES_SMPS_IN_VOLTAGE_LIMIT) - { - limits->v_in = (float)CONFIG_EXAMPLES_SMPS_IN_VOLTAGE_LIMIT / 1000.0; - pwrwarn("WARNING: " - "SMPS input voltage limiit > SMPS absolute input voltage " - "limit. Set input voltage limit to %.2f.\n", - limits->v_in); - } - - if (limits->i_out * 1000 > CONFIG_EXAMPLES_SMPS_OUT_CURRENT_LIMIT) - { - limits->i_out = (float)CONFIG_EXAMPLES_SMPS_OUT_CURRENT_LIMIT / 1000.0; - pwrwarn("WARNING: " - "SMPS output current limiit > SMPS absolute output current " - "limit. Set output current limit to %.2f.\n", - limits->i_out); - } - - /* Set output voltage limit */ - - smps->limits.v_out = limits->v_out; - - /* Set input voltage limit */ - - smps->limits.v_in = limits->v_in; - - /* Set current limit */ - - smps->limits.i_out = limits->i_out; - - /* Lock limits */ - - smps->limits.lock = true; - -errout: - return ret; -} - -/**************************************************************************** - * Name: smps_state_get - * - * Description: - * - * Returned Value: - * 0 on success, a negated errno value on failure - * - ****************************************************************************/ - -static int smps_state_get(struct smps_dev_s *dev, - struct smps_state_s *state) -{ - struct smps_s *smps = (struct smps_s *)dev->priv; - - /* Copy locally stored feedbacks data to status structure */ - - smps->state.fb.v_in = g_smps_priv.v_in; - smps->state.fb.v_out = g_smps_priv.v_out; - - /* Return state structure to caller */ - - memcpy(state, &smps->state, sizeof(struct smps_state_s)); - - return OK; -} - -/**************************************************************************** - * Name: smps_fault_set - * - * Description: - * - * Returned Value: - * 0 on success, a negated errno value on failure - * - ****************************************************************************/ - -static int smps_fault_set(struct smps_dev_s *dev, uint8_t fault) -{ - return OK; -} - -/**************************************************************************** - * Name: smps_fault_get - * - * Description: - * - * Returned Value: - * 0 on success, a negated errno value on failure - * - ****************************************************************************/ - -static int smps_fault_get(struct smps_dev_s *dev, uint8_t *fault) -{ - return OK; -} - -/**************************************************************************** - * Name: smps_fault_clean - * - * Description: - * - * Returned Value: - * 0 on success, a negated errno value on failure - * - ****************************************************************************/ - -static int smps_fault_clean(struct smps_dev_s *dev, uint8_t fault) -{ - return OK; -} - -/**************************************************************************** - * Name: smps_state_get - * - * Description: - * - * Returned Value: - * 0 on success, a negated errno value on failure - * - ****************************************************************************/ - -static int smps_ioctl(struct smps_dev_s *dev, int cmd, unsigned long arg) -{ - return OK; -} - -/**************************************************************************** - * Name: smps_controller - * - * Description: - * - * Returned Value: - * - ****************************************************************************/ - -static float smps_controller(struct smps_priv_s *priv, float err) -{ - float out = 0.0; - -#ifdef SMPS_CONTROLLER_PID - out = pid_controller(&priv->pid, err); -#else -# error "At this time only PID controller implemented" -#endif - - return out; -} - -/**************************************************************************** - * Name: smps_duty_set - * - * Description: - * - * Returned Value: - * - ****************************************************************************/ - -static void smps_duty_set(struct smps_priv_s *priv, - struct smps_lower_dev_s *lower, - float out) -{ - struct hrtim_dev_s *hrtim = lower->hrtim; - uint8_t mode = priv->conv_mode; - uint16_t cmp = 0; - float duty = 0.0; - uint16_t per = 0; - - switch (mode) - { - case CONVERTER_MODE_INIT: - { - /* Do nothing */ - - break; - } - - case CONVERTER_MODE_BUCK: - { - if (out >= priv->v_in) out = priv->v_in; - if (out < 0.0) out = 0.0; - - duty = out / priv->v_in; - -#warning TODO: current limit in buck mode - - per = HRTIM_PER_GET(hrtim, HRTIM_TIMER_TIMC); - - cmp = (uint16_t)(per * duty); - - if (cmp > per - 30) cmp = per - 30; - - /* Set T5 duty cycle. T1 is complementary to T5 */ - - HRTIM_CMP_SET(hrtim, HRTIM_TIMER_TIMC, HRTIM_CMP1, cmp); - - break; - } - - case CONVERTER_MODE_BOOST: - { - per = HRTIM_PER_GET(hrtim, HRTIM_TIMER_TIMC); - - if (out < priv->v_in) out = priv->v_in; - if (out >= BOOST_VOLT_MAX) out = BOOST_VOLT_MAX; - - duty = 1.0 - priv->v_in / out; - -#warning TODO: current limit in boost mode - - cmp = (uint16_t)(per * duty); - - /* Set T2 duty cycle. T6 is complementary to T2 */ - - HRTIM_CMP_SET(hrtim, HRTIM_TIMER_TIMD, HRTIM_CMP1, cmp); - - break; - } - - case CONVERTER_MODE_BUCKBOOST: - { - /* Buck converter is set to fixed duty cycle (80%). - * Now we need set boost converter - */ - - per = HRTIM_PER_GET(hrtim, HRTIM_TIMER_TIMC); - - if (out < priv->v_in) out = priv->v_in; - if (out >= BOOST_VOLT_MAX) out = BOOST_VOLT_MAX; - - duty = 1.0 - priv->v_in / out; - -#warning TODO: current limit in buck boost mode - - cmp = (uint16_t)(per * duty); - - /* Set T2 duty cycle. T6 is complementary to T2 */ - - HRTIM_CMP_SET(hrtim, HRTIM_TIMER_TIMD, HRTIM_CMP1, cmp); - - break; - } - - default: - { - pwrerr("ERROR: Unknown converter mode %d!\n", mode); - break; - } - } -} - -/**************************************************************************** - * Name: smps_conv_mode_set - * - * Description: - * Change converter mode (buck/boost/buck-boost). - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void smps_conv_mode_set(struct smps_priv_s *priv, - struct smps_lower_dev_s *lower, - uint8_t mode) -{ - struct hrtim_dev_s *hrtim = lower->hrtim; - - /* Disable all outputs */ - - HRTIM_ALL_OUTPUTS_ENABLE(hrtim, false); - - switch (mode) - { - case CONVERTER_MODE_INIT: - { - break; - } - - case CONVERTER_MODE_BUCK: - { - /* Set T2 low (T6 high) on the next PER */ - - HRTIM_OUTPUT_SET_SET(hrtim, HRTIM_OUT_TIMD_CH1, - HRTIM_OUT_SET_NONE); - HRTIM_OUTPUT_RST_SET(hrtim, HRTIM_OUT_TIMD_CH1, - HRTIM_OUT_RST_PER); - - /* Set T5 to a high state on PER and reset on CMP1. - * T1 is complementary to T5. - */ - - HRTIM_OUTPUT_SET_SET(hrtim, HRTIM_OUT_TIMC_CH1, - HRTIM_OUT_SET_PER); - HRTIM_OUTPUT_RST_SET(hrtim, HRTIM_OUT_TIMC_CH1, - HRTIM_OUT_RST_CMP1); - - break; - } - - case CONVERTER_MODE_BOOST: - { - /* Set T4 high (T11 low) on the next PER */ - - HRTIM_OUTPUT_SET_SET(hrtim, HRTIM_OUT_TIMC_CH1, - HRTIM_OUT_SET_PER); - HRTIM_OUTPUT_RST_SET(hrtim, HRTIM_OUT_TIMC_CH1, - HRTIM_OUT_RST_NONE); - - /* Set T12 to a high state on PER and reset on CMP1. - * T5 is complementary to T12. - */ - - HRTIM_OUTPUT_SET_SET(hrtim, HRTIM_OUT_TIMD_CH1, - HRTIM_OUT_SET_PER); - HRTIM_OUTPUT_RST_SET(hrtim, HRTIM_OUT_TIMD_CH1, - HRTIM_OUT_RST_CMP1); - - break; - } - - case CONVERTER_MODE_BUCKBOOST: - { - /* Set T4 to a high state on PER and reset on CMP1. - * T11 is complementary to T4. - */ - - HRTIM_OUTPUT_SET_SET(hrtim, HRTIM_OUT_TIMC_CH1, - HRTIM_OUT_SET_PER); - HRTIM_OUTPUT_RST_SET(hrtim, HRTIM_OUT_TIMC_CH1, - HRTIM_OUT_RST_CMP1); - - /* Set T12 to a high state on PER and reset on CMP1. - * T5 is complementary to T12. - */ - - HRTIM_OUTPUT_SET_SET(hrtim, HRTIM_OUT_TIMD_CH1, - HRTIM_OUT_SET_PER); - HRTIM_OUTPUT_RST_SET(hrtim, HRTIM_OUT_TIMD_CH1, - HRTIM_OUT_RST_CMP1); - - /* Set fixed duty cycle (80%) on buck converter (T4 and T11) */ - - HRTIM_CMP_SET(hrtim, HRTIM_TIMER_TIMC, HRTIM_CMP1, - 0.8 * ((uint16_t)HRTIM_PER_GET(hrtim, - HRTIM_TIMER_TIMC))); - - break; - } - - default: - { - pwrerr("ERROR: Unknown converter mode %d!\n", mode); - break; - } - } - - /* Set mode in private data */ - - priv->conv_mode = mode; - - /* Enable outputs */ - - HRTIM_ALL_OUTPUTS_ENABLE(hrtim, true); -} - -/**************************************************************************** - * Name: adc12_handler - ****************************************************************************/ - -static void adc12_handler(void) -{ - struct smps_dev_s *dev = &g_smps_dev; - struct smps_s *smps = (struct smps_s *)dev->priv; - struct smps_priv_s *priv = (struct smps_priv_s *)smps->priv; - struct smps_lower_dev_s *lower = dev->lower; - struct stm32_adc_dev_s *adc = lower->adc; - uint32_t pending; - float ref = ADC_REF_VOLTAGE; - float bit = ADC_VAL_MAX; - float err; - float out; - uint8_t mode; - - pending = STM32_ADC_INT_GET(adc); - - if (pending & ADC_INT_JEOC && priv->running == true) - { - /* Get raw ADC values */ - - priv->v_out_raw = STM32_ADC_INJDATA_GET(adc, V_OUT_ADC_INJ_CHANNEL); - priv->v_in_raw = STM32_ADC_INJDATA_GET(adc, V_IN_ADC_INJ_CHANNEL); - - /* Convert raw values to real values */ - - priv->v_out = (priv->v_out_raw * ref / bit) * V_OUT_RATIO; - priv->v_in = (priv->v_in_raw * ref / bit) * V_IN_RATIO; - - /* According to measured voltages we set converter - * in appropriate mode - */ - - if (smps->param.v_out > (priv->v_in + SMPS_BUCKBOOST_RANGE)) - { - /* Desired output voltage greater than input voltage - set - * boost converter - */ - - mode = CONVERTER_MODE_BOOST; - } - - else if (smps->param.v_out < (priv->v_in - SMPS_BUCKBOOST_RANGE)) - { - /* Desired output voltage lower than input voltage - set - * buck converter - */ - - mode = CONVERTER_MODE_BUCK; - } - - else - { - /* Desired output voltage close to input voltage - set - * buck-boost converter - */ - - mode = CONVERTER_MODE_BUCKBOOST; - } - - /* Configure converter to the new mode if needed */ - - if (priv->conv_mode != mode) - { - smps_conv_mode_set(priv, lower, mode); - } - - /* Get regulator error */ - - err = smps->param.v_out - priv->v_out; - - if (err >= SMPS_VOLTAGE_ACCURACY || err <= (-SMPS_VOLTAGE_ACCURACY)) - { - /* PID controller */ - - out = smps_controller(priv, err); - - /* Update duty cycle */ - - smps_duty_set(priv, lower, out); - } - } - - /* Clear pending */ - - STM32_ADC_INT_ACK(adc, pending); -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_smps_setup - * - * Description: - * Initialize SMPS driver. - * - * Returned Value: - * 0 on success, a negated errno value on failure - * - ****************************************************************************/ - -int stm32_smps_setup(void) -{ - struct smps_lower_dev_s *lower = &g_smps_lower; - struct smps_dev_s *smps = &g_smps_dev; - struct hrtim_dev_s *hrtim = NULL; - struct adc_dev_s *adc = NULL; - static bool initialized = false; - int ret = OK; - int i; - - /* Initialize only once */ - - if (!initialized) - { - /* Get the HRTIM interface */ - - hrtim = stm32_hrtiminitialize(); - if (hrtim == NULL) - { - pwrerr("ERROR: Failed to get HRTIM1 interface\n"); - return -ENODEV; - } - - /* Configure the pins as analog inputs for the selected channels */ - - for (i = 0; i < ADC1_NCHANNELS; i++) - { - stm32_configgpio(g_adc1pins[i]); - } - - /* Get the ADC interface */ - - adc = stm32_adcinitialize(1, g_adc1chan, ADC1_NCHANNELS); - if (adc == NULL) - { - pwrerr("ERROR: Failed to get ADC %d interface\n", 1); - return -ENODEV; - } - - /* Initialize SMPS lower driver interfaces */ - - lower->hrtim = hrtim; - lower->adc = adc->ad_priv; - lower->comp = NULL; - lower->dac = NULL; - lower->opamp = NULL; - - /* Attach ADC12 ram vector */ - - ret = arm_ramvec_attach(STM32_IRQ_ADC12, adc12_handler); - if (ret < 0) - { - pwrerr("ERROR: arm_ramvec_attach failed: %d\n", ret); - ret = EXIT_FAILURE; - goto errout; - } - - /* Set the priority of the ADC12 interrupt vector */ - - ret = up_prioritize_irq(STM32_IRQ_ADC12, NVIC_SYSH_HIGH_PRIORITY); - if (ret < 0) - { - pwrerr("ERROR: up_prioritize_irq failed: %d\n", ret); - ret = EXIT_FAILURE; - goto errout; - } - - /* Setup ADC hardware */ - - adc->ad_ops->ao_setup(adc); - - /* We do not need register character drivers for SMPS lower - * peripherals. All control should be done via SMPS character - * driver. - */ - - ret = smps_register(CONFIG_EXAMPLES_SMPS_DEVPATH, smps, (void *)lower); - if (ret < 0) - { - pwrerr("ERROR: smps_register failed: %d\n", ret); - return ret; - } - - initialized = true; - } - -errout: - return ret; -} - -#endif /* CONFIG_EXAMPLE_SMPS && CONFIG_DRIVERS_SMPS*/ diff --git a/boards/arm/stm32/b-g474e-dpow1/src/stm32_userleds.c b/boards/arm/stm32/b-g474e-dpow1/src/stm32_userleds.c deleted file mode 100644 index badccd03daae3..0000000000000 --- a/boards/arm/stm32/b-g474e-dpow1/src/stm32_userleds.c +++ /dev/null @@ -1,124 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/b-g474e-dpow1/src/stm32_userleds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include - -#include "stm32.h" -#include "b-g474e-dpow1.h" - -#if !defined(CONFIG_ARCH_LEDS) - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_userled_initialize - * - * Description: - * Initialize the user LEDs before use. Note: For this function to be - * available to user application logic, CONFIG_ARCH_LEDS must not be - * defined. - ****************************************************************************/ - -uint32_t board_userled_initialize(void) -{ - /* Configure LED GPIOs for output */ - - stm32_configgpio(GPIO_LED1); - stm32_configgpio(GPIO_LED2); - stm32_configgpio(GPIO_LED3); - stm32_configgpio(GPIO_LED4); - return BOARD_NLEDS; -} - -/**************************************************************************** - * Name: board_userled - * - * Description: - * Allow user application logic to control LEDs one at a time. Note: For - * this function to be available to user application logic, - * CONFIG_ARCH_LEDS must not be defined. - * - * Parameters: - * led: Index to the LED, which may be one of the defines BOARD_LED1, - * BOARD_LED2, BOARD_LED3, or BOARD_LED4. - * ledon: true to turn the LED on, false to turn it off. - ****************************************************************************/ - -void board_userled(int led, bool ledon) -{ - switch (led) - { - case BOARD_LED1: - stm32_gpiowrite(GPIO_LED1, ledon); - break; - - case BOARD_LED2: - stm32_gpiowrite(GPIO_LED2, ledon); - break; - - case BOARD_LED3: - stm32_gpiowrite(GPIO_LED3, ledon); - break; - - case BOARD_LED4: - stm32_gpiowrite(GPIO_LED4, ledon); - break; - } -} - -/**************************************************************************** - * Name: board_userled_all - * - * Description: - * Allow user application logic to control all LEDs in one function call. - * Note: For this function to be available to user application logic, - * CONFIG_ARCH_LEDS must not be defined. - * - * Parameters: - * ledset: Bitmask indicating the new state for all LEDs, where a set bit - * indicates LED on and a clear bit indicates LED off. To - * construct the bitmask, using a bitwise OR of the defines - * BOARD_LED1_BIT, BOARD_LED2_BIT, BOARD_LED3_BIT, and/or - * BOARD_LED4_BIT. - ****************************************************************************/ - -void board_userled_all(uint32_t ledset) -{ - stm32_gpiowrite(GPIO_LED1, (ledset & BOARD_LED1_BIT) != 0); - stm32_gpiowrite(GPIO_LED2, (ledset & BOARD_LED2_BIT) != 0); - stm32_gpiowrite(GPIO_LED3, (ledset & BOARD_LED3_BIT) != 0); - stm32_gpiowrite(GPIO_LED4, (ledset & BOARD_LED4_BIT) != 0); -} - -#endif /* !CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/clicker2-stm32/CMakeLists.txt b/boards/arm/stm32/clicker2-stm32/CMakeLists.txt deleted file mode 100644 index 40b17adb6cbf6..0000000000000 --- a/boards/arm/stm32/clicker2-stm32/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/clicker2-stm32/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32/clicker2-stm32/configs/knsh/defconfig b/boards/arm/stm32/clicker2-stm32/configs/knsh/defconfig deleted file mode 100644 index b44ea5be1a4b9..0000000000000 --- a/boards/arm/stm32/clicker2-stm32/configs/knsh/defconfig +++ /dev/null @@ -1,54 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_SYSTEM_DD is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="clicker2-stm32" -CONFIG_ARCH_BOARD_CLICKER2_STM32=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F407VG=y -CONFIG_ARCH_IRQBUTTONS=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_ARM_MPU=y -CONFIG_BOARDCTL=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILD_PROTECTED=y -CONFIG_FS_PROCFS=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_NSH_DISABLE_GET=y -CONFIG_NSH_DISABLE_IFUPDOWN=y -CONFIG_NSH_DISABLE_MKRD=y -CONFIG_NSH_DISABLE_PUT=y -CONFIG_NSH_DISABLE_WGET=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_NUTTX_USERSPACE=0x08020000 -CONFIG_PASS1_BUILDIR="boards/arm/stm32/clicker2-stm32/kernel" -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=131072 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_HPWORKPRIORITY=192 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=25 -CONFIG_START_MONTH=3 -CONFIG_STM32_CCMEXCLUDE=y -CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_PWR=y -CONFIG_STM32_USART3=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=32 -CONFIG_USART3_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/clicker2-stm32/configs/mrf24j40-6lowpan/defconfig b/boards/arm/stm32/clicker2-stm32/configs/mrf24j40-6lowpan/defconfig deleted file mode 100644 index 67b83406eb150..0000000000000 --- a/boards/arm/stm32/clicker2-stm32/configs/mrf24j40-6lowpan/defconfig +++ /dev/null @@ -1,108 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_DEV_CONSOLE is not set -# CONFIG_NET_ETHERNET is not set -# CONFIG_NET_IPv4 is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="clicker2-stm32" -CONFIG_ARCH_BOARD_CLICKER2_STM32=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F407VG=y -CONFIG_ARCH_IRQBUTTONS=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARDCTL_USBDEVCTRL=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_CDCACM=y -CONFIG_CDCACM_CONSOLE=y -CONFIG_CDCACM_RXBUFSIZE=256 -CONFIG_CDCACM_TXBUFSIZE=256 -CONFIG_DRIVERS_IEEE802154=y -CONFIG_DRIVERS_WIRELESS=y -CONFIG_EXAMPLES_NETTEST=y -CONFIG_EXAMPLES_NETTEST_DEVNAME="wpan0" -CONFIG_EXAMPLES_NETTEST_SERVERIPv6ADDR_1=0xfe80 -CONFIG_EXAMPLES_NETTEST_SERVERIPv6ADDR_6=0x00ff -CONFIG_EXAMPLES_NETTEST_SERVERIPv6ADDR_7=0xfe00 -CONFIG_EXAMPLES_NETTEST_SERVERIPv6ADDR_8=0x0800 -CONFIG_EXAMPLES_NETTEST_SERVER_PORTNO=61616 -CONFIG_EXAMPLES_NETTEST_TARGET2=y -CONFIG_EXAMPLES_UDP=y -CONFIG_EXAMPLES_UDP_CLIENT_PORTNO=61617 -CONFIG_EXAMPLES_UDP_DEVNAME="wpan0" -CONFIG_EXAMPLES_UDP_SERVERIPv6ADDR_1=0xfe80 -CONFIG_EXAMPLES_UDP_SERVERIPv6ADDR_6=0x00ff -CONFIG_EXAMPLES_UDP_SERVERIPv6ADDR_7=0xfe00 -CONFIG_EXAMPLES_UDP_SERVERIPv6ADDR_8=0x0d00 -CONFIG_EXAMPLES_UDP_SERVER_PORTNO=61616 -CONFIG_EXAMPLES_UDP_TARGET2=y -CONFIG_FAT_LCNAMES=y -CONFIG_FAT_LFN=y -CONFIG_FS_FAT=y -CONFIG_FS_PROCFS=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_IEEE802154_I8SAK=y -CONFIG_IEEE802154_MAC=y -CONFIG_IEEE802154_MACDEV=y -CONFIG_IEEE802154_MRF24J40=y -CONFIG_IEEE802154_NETDEV=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_IOB_BUFSIZE=128 -CONFIG_IOB_NBUFFERS=32 -CONFIG_IOB_NCHAINS=16 -CONFIG_LIBC_HOSTNAME="MRF24J40" -CONFIG_LINE_MAX=64 -CONFIG_MAC802154_NTXDESC=32 -CONFIG_NET=y -CONFIG_NETDEV_LATEINIT=y -CONFIG_NETDEV_STATISTICS=y -CONFIG_NETDEV_WIRELESS_IOCTL=y -CONFIG_NETINIT_NETLOCAL=y -CONFIG_NETINIT_NOMAC=y -CONFIG_NETUTILS_TELNETD=y -CONFIG_NET_6LOWPAN=y -CONFIG_NET_BROADCAST=y -CONFIG_NET_IPv6=y -CONFIG_NET_SOCKOPTS=y -CONFIG_NET_STATISTICS=y -CONFIG_NET_TCP=y -CONFIG_NET_TCP_WRITE_BUFFERS=y -CONFIG_NET_UDP=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_DISABLE_GET=y -CONFIG_NSH_DISABLE_PUT=y -CONFIG_NSH_DISABLE_WGET=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=131072 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_HPWORKPRIORITY=192 -CONFIG_SCHED_LPWORK=y -CONFIG_SCHED_LPWORKPRIORITY=160 -CONFIG_SCHED_WAITPID=y -CONFIG_START_YEAR=2013 -CONFIG_STM32_CCMEXCLUDE=y -CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_OTGFS=y -CONFIG_STM32_PWR=y -CONFIG_STM32_USART3=y -CONFIG_SYSTEM_NSH=y -CONFIG_SYSTEM_TELNET_CLIENT=y -CONFIG_TASK_NAME_SIZE=32 -CONFIG_USBDEV=y -CONFIG_WIRELESS=y -CONFIG_WIRELESS_IEEE802154=y diff --git a/boards/arm/stm32/clicker2-stm32/configs/mrf24j40-mac/defconfig b/boards/arm/stm32/clicker2-stm32/configs/mrf24j40-mac/defconfig deleted file mode 100644 index bb355e1aeb496..0000000000000 --- a/boards/arm/stm32/clicker2-stm32/configs/mrf24j40-mac/defconfig +++ /dev/null @@ -1,60 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="clicker2-stm32" -CONFIG_ARCH_BOARD_CLICKER2_STM32=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F407VG=y -CONFIG_ARCH_IRQBUTTONS=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_DRIVERS_IEEE802154=y -CONFIG_DRIVERS_WIRELESS=y -CONFIG_FS_PROCFS=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_IDLETHREAD_STACKSIZE=2048 -CONFIG_IEEE802154_I8SAK=y -CONFIG_IEEE802154_MAC=y -CONFIG_IEEE802154_MACDEV=y -CONFIG_IEEE802154_MRF24J40=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_DISABLE_GET=y -CONFIG_NSH_DISABLE_IFUPDOWN=y -CONFIG_NSH_DISABLE_PUT=y -CONFIG_NSH_DISABLE_WGET=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAMLOG=y -CONFIG_RAMLOG_SYSLOG=y -CONFIG_RAM_SIZE=131072 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_HPWORKPRIORITY=192 -CONFIG_SCHED_LPWORK=y -CONFIG_SCHED_WAITPID=y -CONFIG_START_YEAR=2013 -CONFIG_STM32_CCMEXCLUDE=y -CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_PWR=y -CONFIG_STM32_USART3=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=32 -CONFIG_USART3_SERIAL_CONSOLE=y -CONFIG_WIRELESS=y -CONFIG_WIRELESS_IEEE802154=y diff --git a/boards/arm/stm32/clicker2-stm32/configs/mrf24j40-starhub/defconfig b/boards/arm/stm32/clicker2-stm32/configs/mrf24j40-starhub/defconfig deleted file mode 100644 index 1d2e6c692f546..0000000000000 --- a/boards/arm/stm32/clicker2-stm32/configs/mrf24j40-starhub/defconfig +++ /dev/null @@ -1,93 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_DEV_CONSOLE is not set -# CONFIG_NET_ETHERNET is not set -# CONFIG_NET_IPv4 is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="clicker2-stm32" -CONFIG_ARCH_BOARD_CLICKER2_STM32=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F407VG=y -CONFIG_ARCH_IRQBUTTONS=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARDCTL_USBDEVCTRL=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_CDCACM=y -CONFIG_CDCACM_CONSOLE=y -CONFIG_CDCACM_RXBUFSIZE=256 -CONFIG_CDCACM_TXBUFSIZE=256 -CONFIG_DRIVERS_IEEE802154=y -CONFIG_DRIVERS_WIRELESS=y -CONFIG_FAT_LCNAMES=y -CONFIG_FAT_LFN=y -CONFIG_FS_FAT=y -CONFIG_FS_PROCFS=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_IEEE802154_I8SAK=y -CONFIG_IEEE802154_MAC=y -CONFIG_IEEE802154_MACDEV=y -CONFIG_IEEE802154_MRF24J40=y -CONFIG_IEEE802154_NETDEV=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_IOB_BUFSIZE=128 -CONFIG_IOB_NBUFFERS=32 -CONFIG_IOB_NCHAINS=16 -CONFIG_LIBC_HOSTNAME="MRF24J40" -CONFIG_LINE_MAX=64 -CONFIG_MAC802154_NTXDESC=32 -CONFIG_NET=y -CONFIG_NETDEV_LATEINIT=y -CONFIG_NETDEV_STATISTICS=y -CONFIG_NETDEV_TELNET=y -CONFIG_NETDEV_WIRELESS_IOCTL=y -CONFIG_NETINIT_NETLOCAL=y -CONFIG_NETINIT_NOMAC=y -CONFIG_NET_6LOWPAN=y -CONFIG_NET_BROADCAST=y -CONFIG_NET_IPv6=y -CONFIG_NET_SOCKOPTS=y -CONFIG_NET_STAR=y -CONFIG_NET_STARHUB=y -CONFIG_NET_STATISTICS=y -CONFIG_NET_TCP=y -CONFIG_NET_TCP_WRITE_BUFFERS=y -CONFIG_NET_UDP=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_DISABLE_GET=y -CONFIG_NSH_DISABLE_PUT=y -CONFIG_NSH_DISABLE_WGET=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=131072 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_HPWORKPRIORITY=192 -CONFIG_SCHED_LPWORK=y -CONFIG_SCHED_LPWORKPRIORITY=160 -CONFIG_SCHED_WAITPID=y -CONFIG_START_YEAR=2013 -CONFIG_STM32_CCMEXCLUDE=y -CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_OTGFS=y -CONFIG_STM32_PWR=y -CONFIG_STM32_USART3=y -CONFIG_SYSTEM_NSH=y -CONFIG_SYSTEM_TELNET_CLIENT=y -CONFIG_TASK_NAME_SIZE=32 -CONFIG_USBDEV=y -CONFIG_WIRELESS=y -CONFIG_WIRELESS_IEEE802154=y diff --git a/boards/arm/stm32/clicker2-stm32/configs/mrf24j40-starpoint/defconfig b/boards/arm/stm32/clicker2-stm32/configs/mrf24j40-starpoint/defconfig deleted file mode 100644 index d49e01b2da3c0..0000000000000 --- a/boards/arm/stm32/clicker2-stm32/configs/mrf24j40-starpoint/defconfig +++ /dev/null @@ -1,109 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_DEV_CONSOLE is not set -# CONFIG_NET_ETHERNET is not set -# CONFIG_NET_IPv4 is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="clicker2-stm32" -CONFIG_ARCH_BOARD_CLICKER2_STM32=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F407VG=y -CONFIG_ARCH_IRQBUTTONS=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARDCTL_USBDEVCTRL=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_CDCACM=y -CONFIG_CDCACM_CONSOLE=y -CONFIG_CDCACM_RXBUFSIZE=256 -CONFIG_CDCACM_TXBUFSIZE=256 -CONFIG_DRIVERS_IEEE802154=y -CONFIG_DRIVERS_WIRELESS=y -CONFIG_EXAMPLES_NETTEST=y -CONFIG_EXAMPLES_NETTEST_DEVNAME="wpan0" -CONFIG_EXAMPLES_NETTEST_SERVERIPv6ADDR_1=0xfe80 -CONFIG_EXAMPLES_NETTEST_SERVERIPv6ADDR_6=0x00ff -CONFIG_EXAMPLES_NETTEST_SERVERIPv6ADDR_7=0xfe00 -CONFIG_EXAMPLES_NETTEST_SERVERIPv6ADDR_8=0x0800 -CONFIG_EXAMPLES_NETTEST_SERVER_PORTNO=61616 -CONFIG_EXAMPLES_NETTEST_TARGET2=y -CONFIG_EXAMPLES_UDP=y -CONFIG_EXAMPLES_UDP_CLIENT_PORTNO=61617 -CONFIG_EXAMPLES_UDP_DEVNAME="wpan0" -CONFIG_EXAMPLES_UDP_SERVERIPv6ADDR_1=0xfe80 -CONFIG_EXAMPLES_UDP_SERVERIPv6ADDR_6=0x00ff -CONFIG_EXAMPLES_UDP_SERVERIPv6ADDR_7=0xfe00 -CONFIG_EXAMPLES_UDP_SERVERIPv6ADDR_8=0x0d00 -CONFIG_EXAMPLES_UDP_SERVER_PORTNO=61616 -CONFIG_EXAMPLES_UDP_TARGET2=y -CONFIG_FAT_LCNAMES=y -CONFIG_FAT_LFN=y -CONFIG_FS_FAT=y -CONFIG_FS_PROCFS=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_IEEE802154_I8SAK=y -CONFIG_IEEE802154_MAC=y -CONFIG_IEEE802154_MACDEV=y -CONFIG_IEEE802154_MRF24J40=y -CONFIG_IEEE802154_NETDEV=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_IOB_BUFSIZE=128 -CONFIG_IOB_NBUFFERS=32 -CONFIG_IOB_NCHAINS=16 -CONFIG_LIBC_HOSTNAME="MRF24J40" -CONFIG_LINE_MAX=64 -CONFIG_MAC802154_NTXDESC=32 -CONFIG_NET=y -CONFIG_NETDEV_LATEINIT=y -CONFIG_NETDEV_STATISTICS=y -CONFIG_NETDEV_WIRELESS_IOCTL=y -CONFIG_NETINIT_NETLOCAL=y -CONFIG_NETINIT_NOMAC=y -CONFIG_NETUTILS_TELNETC=y -CONFIG_NETUTILS_TELNETD=y -CONFIG_NET_6LOWPAN=y -CONFIG_NET_BROADCAST=y -CONFIG_NET_IPv6=y -CONFIG_NET_SOCKOPTS=y -CONFIG_NET_STAR=y -CONFIG_NET_STATISTICS=y -CONFIG_NET_TCP=y -CONFIG_NET_TCP_WRITE_BUFFERS=y -CONFIG_NET_UDP=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_DISABLE_GET=y -CONFIG_NSH_DISABLE_PUT=y -CONFIG_NSH_DISABLE_WGET=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=131072 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_HPWORKPRIORITY=192 -CONFIG_SCHED_LPWORK=y -CONFIG_SCHED_LPWORKPRIORITY=160 -CONFIG_SCHED_WAITPID=y -CONFIG_START_YEAR=2013 -CONFIG_STM32_CCMEXCLUDE=y -CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_OTGFS=y -CONFIG_STM32_PWR=y -CONFIG_STM32_USART3=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=32 -CONFIG_USBDEV=y -CONFIG_WIRELESS=y -CONFIG_WIRELESS_IEEE802154=y diff --git a/boards/arm/stm32/clicker2-stm32/configs/nsh/defconfig b/boards/arm/stm32/clicker2-stm32/configs/nsh/defconfig deleted file mode 100644 index 8d0945efcca12..0000000000000 --- a/boards/arm/stm32/clicker2-stm32/configs/nsh/defconfig +++ /dev/null @@ -1,49 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="clicker2-stm32" -CONFIG_ARCH_BOARD_CLICKER2_STM32=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F407VG=y -CONFIG_ARCH_IRQBUTTONS=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_FS_PROCFS=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_DISABLE_GET=y -CONFIG_NSH_DISABLE_IFUPDOWN=y -CONFIG_NSH_DISABLE_PUT=y -CONFIG_NSH_DISABLE_WGET=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=131072 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_HPWORKPRIORITY=192 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=25 -CONFIG_START_MONTH=3 -CONFIG_STM32_CCMEXCLUDE=y -CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_PWR=y -CONFIG_STM32_USART3=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=32 -CONFIG_USART3_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/clicker2-stm32/configs/usbnsh/defconfig b/boards/arm/stm32/clicker2-stm32/configs/usbnsh/defconfig deleted file mode 100644 index 48aee341fff70..0000000000000 --- a/boards/arm/stm32/clicker2-stm32/configs/usbnsh/defconfig +++ /dev/null @@ -1,63 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_DEV_CONSOLE is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="clicker2-stm32" -CONFIG_ARCH_BOARD_CLICKER2_STM32=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F407VG=y -CONFIG_ARCH_IRQBUTTONS=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARDCTL_USBDEVCTRL=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_CDCACM=y -CONFIG_CDCACM_CONSOLE=y -CONFIG_CDCACM_RXBUFSIZE=256 -CONFIG_CDCACM_TXBUFSIZE=256 -CONFIG_FAT_LCNAMES=y -CONFIG_FAT_LFN=y -CONFIG_FS_FAT=y -CONFIG_FS_PROCFS=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_DISABLE_GET=y -CONFIG_NSH_DISABLE_IFUPDOWN=y -CONFIG_NSH_DISABLE_PUT=y -CONFIG_NSH_DISABLE_WGET=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=131072 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_HPWORKPRIORITY=192 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=25 -CONFIG_START_MONTH=3 -CONFIG_STM32_CCMEXCLUDE=y -CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_OTGFS=y -CONFIG_STM32_PWR=y -CONFIG_STM32_USART3=y -CONFIG_SYSLOG_CHAR=y -CONFIG_SYSLOG_DEVPATH="/dev/ttyS0" -CONFIG_SYSLOG_INTBUFFER=y -CONFIG_SYSLOG_INTBUFSIZE=396 -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=32 -CONFIG_USBDEV=y diff --git a/boards/arm/stm32/clicker2-stm32/configs/xbee-6lowpan/defconfig b/boards/arm/stm32/clicker2-stm32/configs/xbee-6lowpan/defconfig deleted file mode 100644 index 4f4c219be01c2..0000000000000 --- a/boards/arm/stm32/clicker2-stm32/configs/xbee-6lowpan/defconfig +++ /dev/null @@ -1,104 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_DEV_CONSOLE is not set -# CONFIG_NET_ETHERNET is not set -# CONFIG_NET_IPv4 is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="clicker2-stm32" -CONFIG_ARCH_BOARD_CLICKER2_STM32=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F407VG=y -CONFIG_ARCH_IRQBUTTONS=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARDCTL_USBDEVCTRL=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_CDCACM=y -CONFIG_CDCACM_CONSOLE=y -CONFIG_CDCACM_RXBUFSIZE=256 -CONFIG_CDCACM_TXBUFSIZE=256 -CONFIG_CLICKER2_STM32_MB1_XBEE=y -CONFIG_DRIVERS_IEEE802154=y -CONFIG_DRIVERS_WIRELESS=y -CONFIG_EXAMPLES_NETTEST=y -CONFIG_EXAMPLES_NETTEST_DEVNAME="wpan0" -CONFIG_EXAMPLES_NETTEST_SERVERIPv6ADDR_1=0xfe80 -CONFIG_EXAMPLES_NETTEST_SERVERIPv6ADDR_6=0x00ff -CONFIG_EXAMPLES_NETTEST_SERVERIPv6ADDR_7=0xfe00 -CONFIG_EXAMPLES_NETTEST_SERVERIPv6ADDR_8=0x0800 -CONFIG_EXAMPLES_NETTEST_SERVER_PORTNO=61616 -CONFIG_EXAMPLES_NETTEST_TARGET2=y -CONFIG_EXAMPLES_UDP=y -CONFIG_EXAMPLES_UDP_CLIENT_PORTNO=61617 -CONFIG_EXAMPLES_UDP_DEVNAME="wpan0" -CONFIG_EXAMPLES_UDP_SERVERIPv6ADDR_1=0xfe80 -CONFIG_EXAMPLES_UDP_SERVERIPv6ADDR_6=0x00ff -CONFIG_EXAMPLES_UDP_SERVERIPv6ADDR_7=0xfe00 -CONFIG_EXAMPLES_UDP_SERVERIPv6ADDR_8=0x0d00 -CONFIG_EXAMPLES_UDP_SERVER_PORTNO=61616 -CONFIG_EXAMPLES_UDP_TARGET2=y -CONFIG_FAT_LCNAMES=y -CONFIG_FAT_LFN=y -CONFIG_FS_FAT=y -CONFIG_FS_PROCFS=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_IEEE802154_I8SAK=y -CONFIG_IEEE802154_XBEE=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_IOB_BUFSIZE=128 -CONFIG_IOB_NBUFFERS=32 -CONFIG_IOB_NCHAINS=16 -CONFIG_LIBC_HOSTNAME="XBee" -CONFIG_LINE_MAX=64 -CONFIG_NET=y -CONFIG_NETDEV_LATEINIT=y -CONFIG_NETDEV_WIRELESS_IOCTL=y -CONFIG_NETINIT_NETLOCAL=y -CONFIG_NETINIT_NOMAC=y -CONFIG_NETUTILS_TELNETD=y -CONFIG_NET_6LOWPAN=y -CONFIG_NET_BROADCAST=y -CONFIG_NET_IPv6=y -CONFIG_NET_SOCKOPTS=y -CONFIG_NET_STATISTICS=y -CONFIG_NET_TCP=y -CONFIG_NET_TCP_WRITE_BUFFERS=y -CONFIG_NET_UDP=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_DISABLE_GET=y -CONFIG_NSH_DISABLE_PUT=y -CONFIG_NSH_DISABLE_WGET=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=131072 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_HPWORKPRIORITY=192 -CONFIG_SCHED_LPWORK=y -CONFIG_SCHED_LPWORKPRIORITY=160 -CONFIG_SCHED_WAITPID=y -CONFIG_START_YEAR=2013 -CONFIG_STM32_CCMEXCLUDE=y -CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_OTGFS=y -CONFIG_STM32_PWR=y -CONFIG_STM32_USART3=y -CONFIG_SYSTEM_NSH=y -CONFIG_SYSTEM_TELNET_CLIENT=y -CONFIG_TASK_NAME_SIZE=32 -CONFIG_USBDEV=y -CONFIG_WIRELESS=y -CONFIG_WIRELESS_IEEE802154=y diff --git a/boards/arm/stm32/clicker2-stm32/include/board.h b/boards/arm/stm32/clicker2-stm32/include/board.h deleted file mode 100644 index e13c619319b26..0000000000000 --- a/boards/arm/stm32/clicker2-stm32/include/board.h +++ /dev/null @@ -1,321 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/clicker2-stm32/include/board.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __BOARDS_ARM_STM32_CLICKER2_STM32_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32_CLICKER2_STM32_INCLUDE_BOARD_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#ifndef __ASSEMBLY__ -# include -# include -#endif - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Clocking *****************************************************************/ - -/* The Clicker 2 for STM32 board features a 25Hz crystal and 32.768kHz RTC - * crystal. - * - * This is the canonical configuration: - * System Clock source : PLL (HSE) - * SYSCLK(Hz) : 168000000 Determined by PLL configuration - * HCLK(Hz) : 168000000 (STM32_RCC_CFGR_HPRE) - * AHB Prescaler : 1 (STM32_RCC_CFGR_HPRE) - * APB1 Prescaler : 4 (STM32_RCC_CFGR_PPRE1) - * APB2 Prescaler : 2 (STM32_RCC_CFGR_PPRE2) - * HSE Frequency(Hz) : 25000000 (STM32_BOARD_XTAL) - * PLLM : 25 (STM32_PLLCFG_PLLM) - * PLLN : 336 (STM32_PLLCFG_PLLN) - * PLLP : 2 (STM32_PLLCFG_PLLP) - * PLLQ : 7 (STM32_PLLCFG_PLLQ) - * Main regulator - * output voltage : Scale1 mode Needed for high speed SYSCLK - * Flash Latency(WS) : 5 - * Prefetch Buffer : OFF - * Instruction cache : ON - * Data cache : ON - * Require 48MHz for - * USB OTG FS, : Enabled - * SDIO and RNG clock - */ - -/* HSI - 16 MHz RC factory-trimmed - * LSI - 32 KHz RC - * HSE - On-board crystal frequency is 25MHz - * LSE - 32.768 kHz - */ - -#define STM32_BOARD_XTAL 25000000ul - -#define STM32_HSI_FREQUENCY 16000000ul -#define STM32_LSI_FREQUENCY 32000 -#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL -#define STM32_LSE_FREQUENCY 32768 - -/* Main PLL Configuration. - * - * PLL source is HSE - * PLL_VCO = (STM32_HSE_FREQUENCY / PLLM) * PLLN - * = (25,000,000 / 25) * 336 - * = 336,000,000 - * SYSCLK = PLL_VCO / PLLP - * = 336,000,000 / 2 = 168,000,000 - * USB OTG FS, SDIO and RNG Clock - * = PLL_VCO / PLLQ - * = 48,000,000 - */ - -#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(25) -#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(336) -#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_2 -#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(7) - -#define STM32_SYSCLK_FREQUENCY 168000000ul - -/* AHB clock (HCLK) is SYSCLK (168MHz) */ - -#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ -#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY - -/* APB1 clock (PCLK1) is HCLK/4 (42MHz) */ - -#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd4 /* PCLK1 = HCLK / 4 */ -#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/4) - -/* Timers driven from APB1 will be twice PCLK1 */ - -#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) - -/* APB2 clock (PCLK2) is HCLK/2 (84MHz) */ - -#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLKd2 /* PCLK2 = HCLK / 2 */ -#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/2) - -/* Timers driven from APB2 will be twice PCLK2 */ - -#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM9_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM10_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM11_CLKIN (2*STM32_PCLK2_FREQUENCY) - -/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx - * otherwise frequency is 2xAPBx. - * Note: TIM1,8 are on APB2, others on APB1 - */ - -#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM2_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM3_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM4_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM5_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM6_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM7_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY - -/* SDIO dividers. Note that slower clocking is required when DMA is disabled - * in order to avoid RX overrun/TX underrun errors due to delayed responses - * to service FIFOs in interrupt driven mode. These values have not been - * tuned!!! - * - * SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(118+2)=400 KHz - */ - -#define SDIO_INIT_CLKDIV (118 << SDIO_CLKCR_CLKDIV_SHIFT) - -/* DMA ON: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(1+2)=16 MHz - * DMA OFF: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(2+2)=12 MHz - */ - -#ifdef CONFIG_SDIO_DMA -# define SDIO_MMCXFR_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT) -#else -# define SDIO_MMCXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT) -#endif - -/* DMA ON: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(1+2)=16 MHz - * DMA OFF: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(2+2)=12 MHz - */ - -#ifdef CONFIG_SDIO_DMA -# define SDIO_SDXFR_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT) -#else -# define SDIO_SDXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT) -#endif - -/* LED definitions **********************************************************/ - -/* The Mikroe Clicker2 STM32 has two user controllable LEDs: - * - * LD1 - PE12, Active high output illuminates - * LD2 - PE15, Active high output illuminates - * - * If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs in - * any way. The following definitions are used to access individual LEDs. - */ - -/* LED index values for use with board_userled() */ - -#define BOARD_LED1 0 -#define BOARD_LED2 1 -#define BOARD_NLEDS 2 - -/* LED bits for use with board_userled_all() */ - -#define BOARD_LED1_BIT (1 << BOARD_LED1) -#define BOARD_LED2_BIT (1 << BOARD_LED2) - -/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the 2 LEDs on - * board the Clicker2 for STM32. - * The following definitions describe how NuttX controls the LEDs: - * - * SYMBOL Meaning LED state - * LED1 LED2 - * ------------------- ----------------------- -------- -------- - * LED_STARTED NuttX has been started OFF OFF - * LED_HEAPALLOCATE Heap has been allocated OFF OFF - * LED_IRQSENABLED Interrupts enabled OFF OFF - * LED_STACKCREATED Idle stack created ON OFF - * LED_INIRQ In an interrupt N/C ON - * LED_SIGNAL In a signal handler No change - * LED_ASSERTION An assertion failed No change - * LED_PANIC The system has crashed OFF Blinking - * LED_IDLE STM32 is in sleep mode Not used - */ - -#define LED_STARTED 0 -#define LED_HEAPALLOCATE 0 -#define LED_IRQSENABLED 0 -#define LED_STACKCREATED 1 -#define LED_INIRQ 2 -#define LED_SIGNAL 3 -#define LED_ASSERTION 3 -#define LED_PANIC 4 - -/* Button definitions *******************************************************/ - -/* The Mikroe Clicker2 STM32 has two buttons available to software: - * - * T2 - PE0, Low sensed when pressed - * T3 - PA10, Low sensed when pressed - */ - -#define BUTTON_T2 0 -#define BUTTON_T3 1 -#define NUM_BUTTONS 2 - -#define BUTTON_T2_BIT (1 << BUTTON_T2) -#define BUTTON_T3_BIT (1 << BUTTON_T3) - -/* Alternate function pin selections ****************************************/ - -/* U[S]ARTs - * - * USART2 - mikroBUS1 - * USART3 - mikroBUS2 - * - * Assuming RS-232 connverted connected on mikroMB1/12 - */ - -#define GPIO_USART2_RX (GPIO_USART2_RX_2|GPIO_SPEED_100MHz) /* PD6 */ -#define GPIO_USART2_TX (GPIO_USART2_TX_2|GPIO_SPEED_100MHz) /* PD5 */ - -#define GPIO_USART3_RX (GPIO_USART3_RX_3|GPIO_SPEED_100MHz) /* PD9 */ -#define GPIO_USART3_TX (GPIO_USART3_TX_3|GPIO_SPEED_100MHz) /* PD8 */ - -/* SPI - * - * SPI2 - mikroBUS2 - * SPI3 - mikroBUS1 - */ - -#define GPIO_SPI2_MISO (GPIO_SPI2_MISO_1|GPIO_SPEED_50MHz) /* PC12 */ -#define GPIO_SPI2_MOSI (GPIO_SPI2_MOSI_1|GPIO_SPEED_50MHz) /* PC11 */ -#define GPIO_SPI2_SCK (GPIO_SPI2_SCK_2|GPIO_SPEED_50MHz) /* PC10 */ - -#define GPIO_SPI3_MISO (GPIO_SPI3_MISO_2|GPIO_SPEED_50MHz) /* PB15 */ -#define GPIO_SPI3_MOSI (GPIO_SPI3_MOSI_2|GPIO_SPEED_50MHz) /* PB14 */ -#define GPIO_SPI3_SCK (GPIO_SPI3_SCK_2|GPIO_SPEED_50MHz) /* PB13 */ - -/* I2C - * - * I2C2 - mikroBUS2 - * I2C3 - mikroBUS1 - */ - -#define GPIO_I2C2_SCL (GPIO_I2C2_SCL_1|GPIO_SPEED_50MHz) /* PB10 */ -#define GPIO_I2C2_SDA (GPIO_I2C2_SDA_1|GPIO_SPEED_50MHz) /* PB11 */ - -#define GPIO_I2C3_SCL (GPIO_I2C3_SCL_1|GPIO_SPEED_50MHz) /* PA8 */ -#define GPIO_I2C3_SDA (GPIO_I2C3_SDA_1|GPIO_SPEED_50MHz) /* PC9 */ - -/* Analog - * - * mikroBUS1 ADC: PA2-MB1_AN - * mikroBUS1 ADC: PA3-MB2_AN - */ - -/* PWM - * - * mikroBUS1 ADC: PE9-MB1-PWM (TIM1, channel 1) - * mikroBUS1 ADC: PD12-MB2-PWM (TIM4, channel 1) - */ - -#define GPIO_TIM1_CH1OUT (GPIO_TIM1_CH1OUT_2|GPIO_SPEED_50MHz) /* PE9 */ -#define GPIO_TIM4_CH1OUT (GPIO_TIM4_CH1OUT_2|GPIO_SPEED_50MHz) /* PD12 */ - -/* DMA Channel/Stream Selections ********************************************/ - -/* Stream selections are arbitrary for now but might become important in the - * future if we set aside more DMA channels/streams. - * - * SDIO DMA - * DMAMAP_SDIO_1 = Channel 4, Stream 3 - * DMAMAP_SDIO_2 = Channel 4, Stream 6 - */ - -#define DMAMAP_SDIO DMAMAP_SDIO_1 - -/* USB OTG FS */ - -#define GPIO_OTGFS_DM (GPIO_OTGFS_DM_0|GPIO_SPEED_100MHz) -#define GPIO_OTGFS_DP (GPIO_OTGFS_DP_0|GPIO_SPEED_100MHz) -#define GPIO_OTGFS_ID (GPIO_OTGFS_ID_0|GPIO_SPEED_100MHz) -#define GPIO_OTGFS_SOF (GPIO_OTGFS_SOF_0|GPIO_SPEED_100MHz) - -#endif /* __BOARDS_ARM_STM32_CLICKER2_STM32_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32/clicker2-stm32/kernel/Makefile b/boards/arm/stm32/clicker2-stm32/kernel/Makefile deleted file mode 100644 index 5807644db2b12..0000000000000 --- a/boards/arm/stm32/clicker2-stm32/kernel/Makefile +++ /dev/null @@ -1,94 +0,0 @@ -############################################################################ -# boards/arm/stm32/clicker2-stm32/kernel/Makefile -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/Make.defs - -# The entry point name (if none is provided in the .config file) - -CONFIG_INIT_ENTRYPOINT ?= user_start -ENTRYPT = $(patsubst "%",%,$(CONFIG_INIT_ENTRYPOINT)) - -# Get the paths to the libraries and the links script path in format that -# is appropriate for the host OS - -USER_LIBPATHS = $(addprefix -L,$(call CONVERT_PATH,$(addprefix $(TOPDIR)$(DELIM),$(dir $(USERLIBS))))) -USER_LDSCRIPT = -T $(call CONVERT_PATH,$(BOARD_DIR)$(DELIM)scripts$(DELIM)memory.ld) -USER_LDSCRIPT += -T $(call CONVERT_PATH,$(BOARD_DIR)$(DELIM)scripts$(DELIM)user-space.ld) -USER_HEXFILE += $(call CONVERT_PATH,$(TOPDIR)$(DELIM)nuttx_user.hex) -USER_SRECFILE += $(call CONVERT_PATH,$(TOPDIR)$(DELIM)nuttx_user.srec) -USER_BINFILE += $(call CONVERT_PATH,$(TOPDIR)$(DELIM)nuttx_user.bin) - -USER_LDFLAGS = --undefined=$(ENTRYPT) --entry=$(ENTRYPT) $(USER_LDSCRIPT) -USER_LDLIBS = $(patsubst lib%,-l%,$(basename $(notdir $(USERLIBS)))) -USER_LIBGCC = "${shell "$(CC)" $(ARCHCPUFLAGS) -print-libgcc-file-name}" - -# Source files - -CSRCS = stm32_userspace.c -COBJS = $(CSRCS:.c=$(OBJEXT)) -OBJS = $(COBJS) - -# Targets: - -all: $(TOPDIR)$(DELIM)nuttx_user.elf $(TOPDIR)$(DELIM)User.map -.PHONY: nuttx_user.elf depend clean distclean - -$(COBJS): %$(OBJEXT): %.c - $(call COMPILE, $<, $@) - -# Create the nuttx_user.elf file containing all of the user-mode code - -nuttx_user.elf: $(OBJS) - $(Q) $(LD) -o $@ $(USER_LDFLAGS) $(USER_LIBPATHS) $(OBJS) --start-group $(USER_LDLIBS) --end-group $(USER_LIBGCC) - -$(TOPDIR)$(DELIM)nuttx_user.elf: nuttx_user.elf - @echo "LD: nuttx_user.elf" - $(Q) cp -a nuttx_user.elf $(TOPDIR)$(DELIM)nuttx_user.elf -ifeq ($(CONFIG_INTELHEX_BINARY),y) - @echo "CP: nuttx_user.hex" - $(Q) $(OBJCOPY) $(OBJCOPYARGS) -O ihex nuttx_user.elf $(USER_HEXFILE) -endif -ifeq ($(CONFIG_MOTOROLA_SREC),y) - @echo "CP: nuttx_user.srec" - $(Q) $(OBJCOPY) $(OBJCOPYARGS) -O srec nuttx_user.elf $(USER_SRECFILE) -endif -ifeq ($(CONFIG_RAW_BINARY),y) - @echo "CP: nuttx_user.bin" - $(Q) $(OBJCOPY) $(OBJCOPYARGS) -O binary nuttx_user.elf $(USER_BINFILE) -endif - -$(TOPDIR)$(DELIM)User.map: nuttx_user.elf - @echo "MK: User.map" - $(Q) $(NM) nuttx_user.elf >$(TOPDIR)$(DELIM)User.map - $(Q) $(CROSSDEV)size nuttx_user.elf - -.depend: - -depend: .depend - -clean: - $(call DELFILE, nuttx_user.elf) - $(call DELFILE, "$(TOPDIR)$(DELIM)nuttx_user.*") - $(call DELFILE, "$(TOPDIR)$(DELIM)User.map") - $(call CLEAN) - -distclean: clean diff --git a/boards/arm/stm32/clicker2-stm32/kernel/stm32_userspace.c b/boards/arm/stm32/clicker2-stm32/kernel/stm32_userspace.c deleted file mode 100644 index 0274e2ab46574..0000000000000 --- a/boards/arm/stm32/clicker2-stm32/kernel/stm32_userspace.c +++ /dev/null @@ -1,113 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/clicker2-stm32/kernel/stm32_userspace.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include -#include -#include -#include - -#if defined(CONFIG_BUILD_PROTECTED) && !defined(__KERNEL__) - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -#ifndef CONFIG_NUTTX_USERSPACE -# error "CONFIG_NUTTX_USERSPACE not defined" -#endif - -#if CONFIG_NUTTX_USERSPACE != 0x08020000 -# error "CONFIG_NUTTX_USERSPACE must be 0x08020000 to match memory.ld" -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -static struct userspace_data_s g_userspace_data = -{ - .us_heap = &g_mmheap, -}; - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/* These 'addresses' of these values are setup by - * the linker script. - */ - -extern uint8_t _stext[]; /* Start of .text */ -extern uint8_t _etext[]; /* End_1 of .text + .rodata */ -extern const uint8_t _eronly[]; /* End+1 of read only section (.text + .rodata) */ -extern uint8_t _sdata[]; /* Start of .data */ -extern uint8_t _edata[]; /* End+1 of .data */ -extern uint8_t _sbss[]; /* Start of .bss */ -extern uint8_t _ebss[]; /* End+1 of .bss */ - -const struct userspace_s userspace locate_data(".userspace") = -{ - /* General memory map */ - - .us_entrypoint = CONFIG_INIT_ENTRYPOINT, - .us_textstart = (uintptr_t)_stext, - .us_textend = (uintptr_t)_etext, - .us_datasource = (uintptr_t)_eronly, - .us_datastart = (uintptr_t)_sdata, - .us_dataend = (uintptr_t)_edata, - .us_bssstart = (uintptr_t)_sbss, - .us_bssend = (uintptr_t)_ebss, - - /* User data memory structure */ - - .us_data = &g_userspace_data, - - /* Task/thread startup routines */ - - .task_startup = nxtask_startup, - - /* Signal handler trampoline */ - - .signal_handler = up_signal_handler, - - /* User-space work queue support (declared in include/nuttx/wqueue.h) */ - -#ifdef CONFIG_LIBC_USRWORK - .work_usrstart = work_usrstart, -#endif -}; - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -#endif /* CONFIG_BUILD_PROTECTED && !__KERNEL__ */ diff --git a/boards/arm/stm32/clicker2-stm32/scripts/Make.defs b/boards/arm/stm32/clicker2-stm32/scripts/Make.defs deleted file mode 100644 index c20f435cec414..0000000000000 --- a/boards/arm/stm32/clicker2-stm32/scripts/Make.defs +++ /dev/null @@ -1,41 +0,0 @@ -############################################################################ -# boards/arm/stm32/clicker2-stm32/scripts/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/.config -include $(TOPDIR)/tools/Config.mk -include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs - -LDSCRIPT = flash.ld -ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) - -ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 - -CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) -CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) -CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -AFLAGS := $(CFLAGS) -D__ASSEMBLY__ - -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-gotoff.ld -no-check-sections -LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32/clicker2-stm32/scripts/flash.ld b/boards/arm/stm32/clicker2-stm32/scripts/flash.ld deleted file mode 100644 index 31444fc0659b4..0000000000000 --- a/boards/arm/stm32/clicker2-stm32/scripts/flash.ld +++ /dev/null @@ -1,131 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/clicker2-stm32/scripts/flash.ld - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* The STM32F407VG has 1024Kb of FLASH beginning at address 0x0800:0000 and - * 192Kb of SRAM. SRAM is split up into three blocks: - * - * 1) 112Kb of SRAM beginning at address 0x2000:0000 - * 2) 16Kb of SRAM beginning at address 0x2001:c000 - * 3) 64Kb of CCM SRAM beginning at address 0x1000:0000 - * - * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 - * where the code expects to begin execution by jumping to the entry point in - * the 0x0800:0000 address range. - */ - -MEMORY -{ - flash (rx) : ORIGIN = 0x08000000, LENGTH = 1024K - sram (rwx) : ORIGIN = 0x20000000, LENGTH = 112K -} - -OUTPUT_ARCH(arm) -EXTERN(_vectors) -ENTRY(_stext) -SECTIONS -{ - .text : - { - _stext = ABSOLUTE(.); - *(.vectors) - *(.text .text.*) - *(.fixup) - *(.gnu.warning) - *(.rodata .rodata.*) - *(.gnu.linkonce.t.*) - *(.glue_7) - *(.glue_7t) - *(.got) - *(.gcc_except_table) - *(.gnu.linkonce.r.*) - _etext = ABSOLUTE(.); - } > flash - - .init_section : - { - _sinit = ABSOLUTE(.); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) - KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) - _einit = ABSOLUTE(.); - } > flash - - .ARM.extab : - { - *(.ARM.extab*) - } > flash - - __exidx_start = ABSOLUTE(.); - .ARM.exidx : - { - *(.ARM.exidx*) - } > flash - __exidx_end = ABSOLUTE(.); - - .tdata : { - _stdata = ABSOLUTE(.); - *(.tdata .tdata.* .gnu.linkonce.td.*); - _etdata = ABSOLUTE(.); - } > flash - - .tbss : { - _stbss = ABSOLUTE(.); - *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); - _etbss = ABSOLUTE(.); - } > flash - - _eronly = ABSOLUTE(.); - - .data : - { - _sdata = ABSOLUTE(.); - *(.data .data.*) - *(.gnu.linkonce.d.*) - CONSTRUCTORS - . = ALIGN(4); - _edata = ABSOLUTE(.); - } > sram AT > flash - - .bss : - { - _sbss = ABSOLUTE(.); - *(.bss .bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - . = ALIGN(8); - _ebss = ABSOLUTE(.); - } > sram - - /* Stabs debugging sections. */ - - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_info 0 : { *(.debug_info) } - .debug_line 0 : { *(.debug_line) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_aranges 0 : { *(.debug_aranges) } -} diff --git a/boards/arm/stm32/clicker2-stm32/scripts/kernel-space.ld b/boards/arm/stm32/clicker2-stm32/scripts/kernel-space.ld deleted file mode 100644 index d67c215eb7eb5..0000000000000 --- a/boards/arm/stm32/clicker2-stm32/scripts/kernel-space.ld +++ /dev/null @@ -1,106 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/clicker2-stm32/scripts/kernel-space.ld - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* NOTE: This depends on the memory.ld script having been included prior to - * this script. - */ - -OUTPUT_ARCH(arm) -EXTERN(_vectors) -ENTRY(_stext) -SECTIONS -{ - .text : - { - _stext = ABSOLUTE(.); - *(.vectors) - *(.text .text.*) - *(.fixup) - *(.gnu.warning) - *(.rodata .rodata.*) - *(.gnu.linkonce.t.*) - *(.glue_7) - *(.glue_7t) - *(.got) - *(.gcc_except_table) - *(.gnu.linkonce.r.*) - _etext = ABSOLUTE(.); - } > kflash - - .init_section : - { - _sinit = ABSOLUTE(.); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) - KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) - _einit = ABSOLUTE(.); - } > kflash - - .ARM.extab : - { - *(.ARM.extab*) - } > kflash - - __exidx_start = ABSOLUTE(.); - .ARM.exidx : - { - *(.ARM.exidx*) - } > kflash - - __exidx_end = ABSOLUTE(.); - - _eronly = ABSOLUTE(.); - - .data : - { - _sdata = ABSOLUTE(.); - *(.data .data.*) - *(.gnu.linkonce.d.*) - CONSTRUCTORS - . = ALIGN(4); - _edata = ABSOLUTE(.); - } > ksram AT > kflash - - .bss : - { - _sbss = ABSOLUTE(.); - *(.bss .bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - . = ALIGN(8); - _ebss = ABSOLUTE(.); - } > ksram - - /* Stabs debugging sections */ - - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_info 0 : { *(.debug_info) } - .debug_line 0 : { *(.debug_line) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_aranges 0 : { *(.debug_aranges) } -} diff --git a/boards/arm/stm32/clicker2-stm32/scripts/memory.ld b/boards/arm/stm32/clicker2-stm32/scripts/memory.ld deleted file mode 100644 index 75ae8743baf4c..0000000000000 --- a/boards/arm/stm32/clicker2-stm32/scripts/memory.ld +++ /dev/null @@ -1,87 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/clicker2-stm32/scripts/memory.ld - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* The STM32F407VG has 1024Kb of FLASH beginning at address 0x0800:0000 and - * 192Kb of SRAM. SRAM is split up into three blocks: - * - * 1) 112KB of SRAM beginning at address 0x2000:0000 - * 2) 16KB of SRAM beginning at address 0x2001:c000 - * 3) 64KB of CCM SRAM beginning at address 0x1000:0000 - * - * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 - * where the code expects to begin execution by jumping to the entry point in - * the 0x0800:0000 address range. - * - * For MPU support, the kernel-mode NuttX section is assumed to be 128Kb of - * FLASH and 4Kb of SRAM. That is an excessive amount for the kernel which - * should fit into 64KB and, of course, can be optimized as needed (See - * also boards/arm/stm32/clicker2-stm32/scripts/kernel-space.ld). Allowing the - * additional does permit addition debug instrumentation to be added to the - * kernel space without overflowing the partition. - * - * Alignment of the user space FLASH partition is also a critical factor: - * The user space FLASH partition will be spanned with a single region of - * size 2**n bytes. The alignment of the user-space region must be the same. - * As a consequence, as the user-space increases in size, the alignment - * requirement also increases. - * - * This alignment requirement means that the largest user space FLASH region - * you can have will be 512KB at it would have to be positioned at - * 0x08800000. If you change this address, don't forget to change the - * CONFIG_NUTTX_USERSPACE configuration setting to match and to modify - * the check in kernel/userspace.c. - * - * For the same reasons, the maximum size of the SRAM mapping is limited to - * 4KB. Both of these alignment limitations could be reduced by using - * multiple regions to map the FLASH/SDRAM range or perhaps with some - * clever use of subregions. - * - * A detailed memory map for the 112KB SRAM region is as follows: - * - * 0x20000 0000: Kernel .data region. Typical size: 0.1KB - * ------- ---- Kernel .bss region. Typical size: 1.8KB - * 0x20000 0800: Kernel IDLE thread stack (approximate). Size is - * determined by CONFIG_IDLETHREAD_STACKSIZE and - * adjustments for alignment. Typical is 1KB. - * ------- ---- Padded to 4KB - * 0x20000 1000: User .data region. Size is variable. - * ------- ---- User .bss region Size is variable. - * 0x20000 2000: Beginning of kernel heap. Size determined by - * CONFIG_MM_KERNEL_HEAPSIZE. - * ------- ---- Beginning of user heap. Can vary with other settings. - * 0x20001 c000: End+1 of CPU RAM - */ - -MEMORY -{ - /* 1024Kb FLASH */ - - kflash (rx) : ORIGIN = 0x08000000, LENGTH = 128K - uflash (rx) : ORIGIN = 0x08020000, LENGTH = 128K - xflash (rx) : ORIGIN = 0x08040000, LENGTH = 768K - - /* 112Kb of contiguous SRAM */ - - ksram (rwx) : ORIGIN = 0x20000000, LENGTH = 4K - usram (rwx) : ORIGIN = 0x20001000, LENGTH = 4K - xsram (rwx) : ORIGIN = 0x20002000, LENGTH = 104K -} diff --git a/boards/arm/stm32/clicker2-stm32/scripts/user-space.ld b/boards/arm/stm32/clicker2-stm32/scripts/user-space.ld deleted file mode 100644 index 1e89ef45fd06f..0000000000000 --- a/boards/arm/stm32/clicker2-stm32/scripts/user-space.ld +++ /dev/null @@ -1,108 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/clicker2-stm32/scripts/user-space.ld - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* NOTE: This depends on the memory.ld script having been included prior to - * this script. - */ - -OUTPUT_ARCH(arm) -SECTIONS -{ - .userspace : - { - *(.userspace) - } > uflash - - .text : - { - _stext = ABSOLUTE(.); - *(.text .text.*) - *(.fixup) - *(.gnu.warning) - *(.rodata .rodata.*) - *(.gnu.linkonce.t.*) - *(.glue_7) - *(.glue_7t) - *(.got) - *(.gcc_except_table) - *(.gnu.linkonce.r.*) - _etext = ABSOLUTE(.); - } > uflash - - .init_section : - { - _sinit = ABSOLUTE(.); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) - KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) - _einit = ABSOLUTE(.); - } > uflash - - .ARM.extab : - { - *(.ARM.extab*) - } > uflash - - __exidx_start = ABSOLUTE(.); - .ARM.exidx : - { - *(.ARM.exidx*) - } > uflash - - __exidx_end = ABSOLUTE(.); - - _eronly = ABSOLUTE(.); - - .data : - { - _sdata = ABSOLUTE(.); - *(.data .data.*) - *(.gnu.linkonce.d.*) - CONSTRUCTORS - . = ALIGN(4); - _edata = ABSOLUTE(.); - } > usram AT > uflash - - .bss : - { - _sbss = ABSOLUTE(.); - *(.bss .bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - . = ALIGN(8); - _ebss = ABSOLUTE(.); - } > usram - - /* Stabs debugging sections */ - - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_info 0 : { *(.debug_info) } - .debug_line 0 : { *(.debug_line) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_aranges 0 : { *(.debug_aranges) } -} diff --git a/boards/arm/stm32/clicker2-stm32/src/CMakeLists.txt b/boards/arm/stm32/clicker2-stm32/src/CMakeLists.txt deleted file mode 100644 index cb3d46c6c34a6..0000000000000 --- a/boards/arm/stm32/clicker2-stm32/src/CMakeLists.txt +++ /dev/null @@ -1,65 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/clicker2-stm32/src/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -set(SRCS stm32_boot.c stm32_bringup.c stm32_spi.c) - -if(CONFIG_ARCH_LEDS) - list(APPEND SRCS stm32_autoleds.c) -else() - list(APPEND SRCS stm32_userleds.c) -endif() - -if(CONFIG_ARCH_BUTTONS) - list(APPEND SRCS stm32_buttons.c) -endif() - -if(CONFIG_STM32_OTGFS) - list(APPEND SRCS stm32_usb.c) -endif() - -if(CONFIG_IEEE802154_MRF24J40) - list(APPEND SRCS stm32_mrf24j40.c) -endif() - -if(CONFIG_IEEE802154_XBEE) - list(APPEND SRCS stm32_xbee.c) -endif() - -if(CONFIG_MMCSD_SPI) - list(APPEND SRCS stm32_mmcsd.c) -endif() - -if(CONFIG_FS_AUTOMOUNTER) - list(APPEND SRCS stm32_automount.c) -endif() - -if(CONFIG_ADC) - list(APPEND SRCS stm32_adc.c) -endif() - -if(CONFIG_STM32_CAN_CHARDRIVER) - list(APPEND SRCS stm32_can.c) -endif() - -target_sources(board PRIVATE ${SRCS}) - -set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/flash.ld") diff --git a/boards/arm/stm32/clicker2-stm32/src/Make.defs b/boards/arm/stm32/clicker2-stm32/src/Make.defs deleted file mode 100644 index 6079d7268eae5..0000000000000 --- a/boards/arm/stm32/clicker2-stm32/src/Make.defs +++ /dev/null @@ -1,67 +0,0 @@ -############################################################################ -# boards/arm/stm32/clicker2-stm32/src/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/Make.defs - -CSRCS = stm32_boot.c stm32_bringup.c stm32_spi.c - -ifeq ($(CONFIG_ARCH_LEDS),y) -CSRCS += stm32_autoleds.c -else -CSRCS += stm32_userleds.c -endif - -ifeq ($(CONFIG_ARCH_BUTTONS),y) -CSRCS += stm32_buttons.c -endif - -ifeq ($(CONFIG_STM32_OTGFS),y) -CSRCS += stm32_usb.c -endif - -ifeq ($(CONFIG_IEEE802154_MRF24J40),y) -CSRCS += stm32_mrf24j40.c -endif - -ifeq ($(CONFIG_IEEE802154_XBEE),y) -CSRCS += stm32_xbee.c -endif - -ifeq ($(CONFIG_MMCSD_SPI),y) -CSRCS += stm32_mmcsd.c -endif - -ifeq ($(CONFIG_FS_AUTOMOUNTER),y) -CSRCS += stm32_automount.c -endif - -ifeq ($(CONFIG_ADC),y) -CSRCS += stm32_adc.c -endif - -ifeq ($(CONFIG_STM32_CAN_CHARDRIVER),y) -CSRCS += stm32_can.c -endif - -DEPPATH += --dep-path board -VPATH += :board -CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/clicker2-stm32/src/stm32_adc.c b/boards/arm/stm32/clicker2-stm32/src/stm32_adc.c deleted file mode 100644 index 0f3fa6dd71284..0000000000000 --- a/boards/arm/stm32/clicker2-stm32/src/stm32_adc.c +++ /dev/null @@ -1,156 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/clicker2-stm32/src/stm32_adc.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include -#include - -#include "chip.h" -#include "stm32_adc.h" -#include "clicker2-stm32.h" - -#ifdef CONFIG_ADC - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -/* Up to 3 ADC interfaces are supported */ - -#if STM32_NADC < 3 -# undef CONFIG_STM32_ADC3 -#endif - -#if STM32_NADC < 2 -# undef CONFIG_STM32_ADC2 -#endif - -#if STM32_NADC < 1 -# undef CONFIG_STM32_ADC1 -#endif - -#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) || defined(CONFIG_STM32_ADC3) -#ifndef CONFIG_STM32_ADC1 -# warning "Channel information only available for ADC1" -#endif - -/* The number of ADC channels in the conversion list */ - -#define ADC1_NCHANNELS 1 - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* The Olimex STM32-P407 has a 10 Kohm potentiometer AN_TR connected to PC0 - * ADC123_IN10 - */ - -/* Identifying number of each ADC channel: Variable Resistor. */ - -#ifdef CONFIG_STM32_ADC1 -static const uint8_t g_chanlist[ADC1_NCHANNELS] = -{ - 10 -}; - -/* Configurations of pins used byte each ADC channels */ - -static const uint32_t g_pinlist[ADC1_NCHANNELS] = -{ - GPIO_ADC1_IN10 -}; -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_adc_setup - * - * Description: - * Initialize ADC and register the ADC driver. - * - ****************************************************************************/ - -int stm32_adc_setup(void) -{ -#ifdef CONFIG_STM32_ADC1 - static bool initialized = false; - struct adc_dev_s *adc; - int ret; - int i; - - /* Check if we have already initialized */ - - if (!initialized) - { - /* Configure the pins as analog inputs for the selected channels */ - - for (i = 0; i < ADC1_NCHANNELS; i++) - { - stm32_configgpio(g_pinlist[i]); - } - - /* Call stm32_adcinitialize() to get an instance of the ADC interface */ - - adc = stm32_adcinitialize(1, g_chanlist, ADC1_NCHANNELS); - if (adc == NULL) - { - aerr("ERROR: Failed to get ADC interface\n"); - return -ENODEV; - } - - /* Register the ADC driver at "/dev/adc0" */ - - ret = adc_register("/dev/adc0", adc); - if (ret < 0) - { - aerr("ERROR: adc_register failed: %d\n", ret); - return ret; - } - - /* Now we are initialized */ - - initialized = true; - } - - return OK; -#else - return -ENOSYS; -#endif -} - -#endif /* CONFIG_STM32_ADC1 || CONFIG_STM32_ADC2 || CONFIG_STM32_ADC3 */ -#endif /* CONFIG_ADC */ diff --git a/boards/arm/stm32/clicker2-stm32/src/stm32_autoleds.c b/boards/arm/stm32/clicker2-stm32/src/stm32_autoleds.c deleted file mode 100644 index ea8eaced9400d..0000000000000 --- a/boards/arm/stm32/clicker2-stm32/src/stm32_autoleds.c +++ /dev/null @@ -1,189 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/clicker2-stm32/src/stm32_autoleds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the 2 LEDs on - * board the Clicker2 for STM32. The following definitions describe how - * NuttX controls the LEDs: - * - * SYMBOL Meaning LED state - * LED1 LED2 - * ------------------- ----------------------- -------- -------- - * LED_STARTED NuttX has been started OFF OFF - * LED_HEAPALLOCATE Heap has been allocated OFF OFF - * LED_IRQSENABLED Interrupts enabled OFF OFF - * LED_STACKCREATED Idle stack created ON OFF - * LED_INIRQ In an interrupt N/C ON - * LED_SIGNAL In a signal handler No change - * LED_ASSERTION An assertion failed No change - * LED_PANIC The system has crashed OFF Blinking - * LED_IDLE STM32 is in sleep mode Not used - * - * VALUE - * -------------------------------------------- -------- -------- - * 0 OFF OFF - * 1 ON OFF - * 2 N/C ON - * 3 N/C N/C - * 4 OFF ON - */ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include "stm32.h" -#include "clicker2-stm32.h" - -#ifdef CONFIG_ARCH_LEDS - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -static void board_led1_on(int led) -{ - bool ledon = false; - - switch (led) - { - case 0: /* LED1=OFF */ - case 4: /* LED1=OFF */ - break; - - case 1: /* LED1=ON */ - ledon = true; - break; - - case 2: /* LED1=N/C */ - case 3: /* LED1=N/C */ - default: - return; - } - - stm32_gpiowrite(GPIO_LED1, ledon); -} - -static void board_led2_on(int led) -{ - bool ledon = false; - - switch (led) - { - case 0: /* LED2=OFF */ - case 1: /* LED2=OFF */ - break; - - case 2: /* LED2=ON */ - case 4: /* LED2=ON */ - ledon = true; - break; - - case 3: /* LED2=N/C */ - default: - return; - } - - stm32_gpiowrite(GPIO_LED2, ledon); -} - -static void board_led1_off(int led) -{ - switch (led) - { - case 0: /* LED1=OFF */ - case 1: /* LED1=OFF */ - case 4: /* LED1=OFF */ - break; - - case 2: /* LED1=N/C */ - case 3: /* LED1=N/C */ - default: - return; - } - - stm32_gpiowrite(GPIO_LED1, false); -} - -static void board_led2_off(int led) -{ - switch (led) - { - case 0: /* LED2=OFF */ - case 1: /* LED2=OFF */ - case 2: /* LED2=OFF */ - case 4: /* LED2=OFF */ - break; - - case 3: /* LED2=N/C */ - default: - return; - } - - stm32_gpiowrite(GPIO_LED2, false); -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_autoled_initialize - ****************************************************************************/ - -void board_autoled_initialize(void) -{ - /* Configure LED1-2 GPIOs for output */ - - stm32_configgpio(GPIO_LED1); - stm32_configgpio(GPIO_LED2); -} - -/**************************************************************************** - * Name: board_autoled_on - ****************************************************************************/ - -void board_autoled_on(int led) -{ - board_led1_on(led); - board_led2_on(led); -} - -/**************************************************************************** - * Name: board_autoled_off - ****************************************************************************/ - -void board_autoled_off(int led) -{ - board_led1_off(led); - board_led2_off(led); -} - -#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/clicker2-stm32/src/stm32_boot.c b/boards/arm/stm32/clicker2-stm32/src/stm32_boot.c deleted file mode 100644 index 7c6c0bd27c793..0000000000000 --- a/boards/arm/stm32/clicker2-stm32/src/stm32_boot.c +++ /dev/null @@ -1,139 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/clicker2-stm32/src/stm32_boot.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include -#include -#include -#include - -#include -#include -#include -#include -#include - -#include "clicker2-stm32.h" - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_boardinitialize - * - * Description: - * All STM32 architectures must provide the following entry point. - * This entry point is called early in the initialization -- after all - * memory has been configured and mapped but before any devices have been - * initialized. - * - ****************************************************************************/ - -void stm32_boardinitialize(void) -{ -#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || defined(CONFIG_STM32_SPI3) - /* Configure SPI chip selects if 1) SPI is not disabled, and 2) the weak - * function stm32_spidev_initialize() has been brought into the link. - */ - - if (stm32_spidev_initialize) - { - stm32_spidev_initialize(); - } -#endif - -#ifdef CONFIG_STM32_OTGFS - /* Initialize USB if the 1) OTG FS controller is in the configuration and - * 2) disabled, and 3) the weak function stm32_usb_configure() has been - * brought into the build. Presumably either CONFIG_USBDEV or - * CONFIG_USBHOST is also selected. - */ - - stm32_usb_configure(); -#endif - -#ifdef CONFIG_ARCH_LEDS - /* Configure on-board LEDs if LED support has been selected. */ - - board_autoled_initialize(); -#endif - -#ifdef CONFIG_ARCH_BUTTONS - /* Configure on-board BUTTONs if BUTTON support has been selected. */ - - board_button_initialize(); -#endif -} - -/**************************************************************************** - * Name: board_late_initialize - * - * Description: - * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional - * initialization call will be performed in the boot-up sequence to a - * function called board_late_initialize(). board_late_initialize() will be - * called immediately after up_initialize() is called and just before the - * initial application is started. This additional initialization phase - * may be used, for example, to initialize board-specific device drivers. - * - ****************************************************************************/ - -#ifdef CONFIG_BOARD_LATE_INITIALIZE -void board_late_initialize(void) -{ - int ret; - - ret = stm32_bringup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_bringup() failed: %d\n", ret); - return; - } - -#ifdef CONFIG_CLICKER2_STM32_SYSLOG_FILE - - /* Delay some time for the automounter to finish mounting before - * bringing up file syslog. - */ - - nxsched_usleep(CONFIG_CLICKER2_STM32_SYSLOG_FILE_DELAY * 1000); - - syslog_channel_t *channel; - channel = syslog_file_channel(CONFIG_CLICKER2_STM32_SYSLOG_FILE_PATH); - if (channel == NULL) - { - syslog(LOG_ERR, "ERROR: syslog_file_channel() failed\n"); - return; - } -#endif - - UNUSED(ret); -} -#endif diff --git a/boards/arm/stm32/clicker2-stm32/src/stm32_bringup.c b/boards/arm/stm32/clicker2-stm32/src/stm32_bringup.c deleted file mode 100644 index 3dd96d97b7ee0..0000000000000 --- a/boards/arm/stm32/clicker2-stm32/src/stm32_bringup.c +++ /dev/null @@ -1,193 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/clicker2-stm32/src/stm32_bringup.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include - -#include -#include -#include - -#ifdef CONFIG_USBMONITOR -# include -#endif - -#ifdef CONFIG_RNDIS -# include -# include -#endif - -#include "stm32.h" -#include "clicker2-stm32.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#ifdef CONFIG_RNDIS -# ifndef CONFIG_CLICKER2_STM32_RNDIS_MACADDR -# define CONFIG_CLICKER2_STM32_RNDIS_MACADDR 0xfadedeadbeef -# endif -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_bringup - * - * Description: - * Perform architecture-specific initialization - * - * CONFIG_BOARD_LATE_INITIALIZE=y : - * Called from board_late_initialize(). - * - ****************************************************************************/ - -int stm32_bringup(void) -{ - int ret; - -#ifdef CONFIG_FS_PROCFS - /* Mount the procfs file system */ - - ret = nx_mount(NULL, "/proc", "procfs", 0, NULL); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: Failed to mount procfs at /proc: %d\n", ret); - } -#endif - -#ifdef CONFIG_STM32_CAN_CHARDRIVER - /* Initialize CAN and register the CAN driver. */ - - ret = stm32_can_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_can_setup failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_ADC - /* Initialize ADC and register the ADC driver. */ - - ret = stm32_adc_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_adc_setup failed: %d\n", ret); - } -#endif - -#ifdef HAVE_USBMONITOR - /* Start the USB Monitor */ - - ret = usbmonitor_start(); - if (ret != OK) - { - syslog(LOG_ERR, "ERROR: Failed to start USB monitor: %d\n", ret); - } -#endif - -#if defined(CONFIG_CLICKER2_STM32_MB1_BEE) || defined(CONFIG_CLICKER2_STM32_MB2_BEE) - /* Configure MRF24J40 wireless */ - - ret = stm32_mrf24j40_initialize(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_mrf24j40_initialize() failed: %d\n", - ret); - } -#endif - -#if defined(CONFIG_CLICKER2_STM32_MB1_XBEE) || defined(CONFIG_CLICKER2_STM32_MB2_XBEE) - /* Configure XBee wireless */ - - ret = stm32_xbee_initialize(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_xbee_initialize() failed: %d\n", ret); - } -#endif - -#if defined(CONFIG_CLICKER2_STM32_MB1_MMCSD_AUTOMOUNT) || \ - defined(CONFIG_CLICKER2_STM32_MB2_MMCSD_AUTOMOUNT) - /* Configure uSD automounter */ - - ret = stm32_automount_initialize(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_automount_initialize() failed: %d\n", - ret); - } -#endif - -#if defined(CONFIG_CLICKER2_STM32_MB1_MMCSD) || defined(CONFIG_CLICKER2_STM32_MB2_MMCSD) - /* Configure uSD card slot */ - - ret = stm32_mmcsd_initialize(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_mmcsd_initialize() failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_INPUT_BUTTONS - /* Register the BUTTON driver */ - - ret = btn_lower_initialize("/dev/buttons"); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: btn_lower_initialize() failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_RNDIS - uint8_t mac[IFHWADDRLEN]; - - mac[0] = (CONFIG_CLICKER2_STM32_RNDIS_MACADDR >> (8 * 5)) & 0xff; - mac[1] = (CONFIG_CLICKER2_STM32_RNDIS_MACADDR >> (8 * 4)) & 0xff; - mac[2] = (CONFIG_CLICKER2_STM32_RNDIS_MACADDR >> (8 * 3)) & 0xff; - mac[3] = (CONFIG_CLICKER2_STM32_RNDIS_MACADDR >> (8 * 2)) & 0xff; - mac[4] = (CONFIG_CLICKER2_STM32_RNDIS_MACADDR >> (8 * 1)) & 0xff; - mac[5] = (CONFIG_CLICKER2_STM32_RNDIS_MACADDR >> (8 * 0)) & 0xff; - - /* Register USB RNDIS Driver */ - - ret = usbdev_rndis_initialize(mac); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: usbdev_rndis_initialize() failed %d\n", ret); - } -#endif - - UNUSED(ret); - return OK; -} diff --git a/boards/arm/stm32/clicker2-stm32/src/stm32_buttons.c b/boards/arm/stm32/clicker2-stm32/src/stm32_buttons.c deleted file mode 100644 index ccae882484fbf..0000000000000 --- a/boards/arm/stm32/clicker2-stm32/src/stm32_buttons.c +++ /dev/null @@ -1,123 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/clicker2-stm32/src/stm32_buttons.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include -#include - -#include "stm32_gpio.h" -#include "stm32_exti.h" - -#include "clicker2-stm32.h" - -#ifdef CONFIG_ARCH_BUTTONS - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_button_initialize - * - * Description: - * board_button_initialize() must be called to initialize button resources. - * After that, board_buttons() may be called to collect the current state - * of all buttons or board_button_irq() may be called to register button - * interrupt handlers. - * - ****************************************************************************/ - -uint32_t board_button_initialize(void) -{ - /* Configure BUTTONS T2-T3 GPIOs for input */ - - stm32_configgpio(GPIO_BTN_T2); - stm32_configgpio(GPIO_BTN_T3); - return NUM_BUTTONS; -} - -/**************************************************************************** - * Name: board_buttons - ****************************************************************************/ - -uint32_t board_buttons(void) -{ - uint32_t ret = 0; - - /* Check that state of each key. A low value will be sensed when the - * button is pressed. - */ - - if (!stm32_gpioread(GPIO_BTN_T2)) - { - ret |= BUTTON_T2_BIT; - } - - if (!stm32_gpioread(GPIO_BTN_T3)) - { - ret |= BUTTON_T3_BIT; - } - - return ret; -} - -/**************************************************************************** - * Button support. - * - * Description: - * board_button_initialize() must be called to initialize button resources. - * After that, board_buttons() may be called to collect the current state - * of all buttons or board_button_irq() may be called to register button - * interrupt handlers. - * - * After board_button_initialize() has been called, board_buttons() may be - * called to collect the state of all buttons. board_buttons() returns an - * 32-bit bit set with each bit associated with a button. See the - * BUTTON_*_BIT definitions in board.h for the meaning of each bit. - * - * board_button_irq() may be called to register an interrupt handler that - * will be called when a button is depressed or released. The ID value is a - * button enumeration value that uniquely identifies a button resource. See - * the BUTTON_* definitions in board.h for the meaning of enumeration - * value. - * - ****************************************************************************/ - -#ifdef CONFIG_ARCH_IRQBUTTONS -int board_button_irq(int id, xcpt_t irqhandler, void *arg) -{ - uint32_t btncfg; - - btncfg = (id == BUTTON_T2) ? GPIO_BTN_T2 : GPIO_BTN_T3; - return stm32_gpiosetevent(btncfg, true, true, true, irqhandler, arg); -} -#endif -#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/stm32/clicker2-stm32/src/stm32_can.c b/boards/arm/stm32/clicker2-stm32/src/stm32_can.c deleted file mode 100644 index ac1db032f958a..0000000000000 --- a/boards/arm/stm32/clicker2-stm32/src/stm32_can.c +++ /dev/null @@ -1,100 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/clicker2-stm32/src/stm32_can.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include - -#include "stm32.h" -#include "stm32_can.h" -#include "clicker2-stm32.h" - -#ifdef CONFIG_CAN - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -#if defined(CONFIG_STM32_CAN1) && defined(CONFIG_STM32_CAN2) -# warning "Both CAN1 and CAN2 are enabled. Only CAN1 is connected." -# undef CONFIG_STM32_CAN2 -#endif - -#ifdef CONFIG_STM32_CAN1 -# define CAN_PORT 1 -#else -# define CAN_PORT 2 -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_can_setup - * - * Description: - * Initialize CAN and register the CAN device - * - ****************************************************************************/ - -int stm32_can_setup(void) -{ -#if defined(CONFIG_STM32_CAN1) || defined(CONFIG_STM32_CAN2) - struct can_dev_s *can; - int ret; - - /* Call stm32_caninitialize() to get an instance of the CAN interface */ - - can = stm32_caninitialize(CAN_PORT); - if (can == NULL) - { - canerr("ERROR: Failed to get CAN interface\n"); - return -ENODEV; - } - - /* Register the CAN driver at "/dev/can0" */ - - ret = can_register("/dev/can0", can); - if (ret < 0) - { - canerr("ERROR: can_register failed: %d\n", ret); - return ret; - } - - return OK; -#else - return -ENODEV; -#endif -} - -#endif /* CONFIG_CAN */ diff --git a/boards/arm/stm32/clicker2-stm32/src/stm32_mmcsd.c b/boards/arm/stm32/clicker2-stm32/src/stm32_mmcsd.c deleted file mode 100644 index a9988f5017f3f..0000000000000 --- a/boards/arm/stm32/clicker2-stm32/src/stm32_mmcsd.c +++ /dev/null @@ -1,423 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/clicker2-stm32/src/stm32_mmcsd.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include - -#include "stm32_spi.h" - -#include "clicker2-stm32.h" - -#ifdef CONFIG_MMCSD_SPI - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#if !defined(CONFIG_CLICKER2_STM32_MB1_MMCSD) && \ - !defined(CONFIG_CLICKER2_STM32_MB2_MMCSD) -# error Only the Mikroe uSD click boards are supported -#endif - -/* Can't support MMC/SD features if mountpoints are disabled or if SDIO - * support is not enabled. - */ - -#if defined(CONFIG_DISABLE_MOUNTPOINT) -# error Mountpoints are required for MMCSD support -#endif - -#ifdef CONFIG_CLICKER2_STM32_MB1_MMCSD -# ifndef CONFIG_STM32_SPI3 -# error MMCSD on mikroBUS1 requires CONFIG_STM32_SPI3 -# endif -#endif - -#ifdef CONFIG_CLICKER2_STM32_MB2_MMCSD -# ifndef CONFIG_STM32_SPI2 -# error MMCSD on mikroBUS1 requires CONFIG_STM32_SPI2 -# endif -#endif - -#ifdef CONFIG_SCHED_LPWORK -# define MMCSDWORK LPWORK -#elif defined (CONFIG_SCHED_HPWORK) -# define MMCSDWORK HPWORK -#else -# error High or low priority work queue required for MMCSD support -#endif - -/* Card Detect - * - * mikroBUS1 Card Detect (AN pin): PE10-MB1_INT - * mikroBUS2 Card Detect (AN pin: PE14-MB2_INT - * - * There is a pull-up on the uSD click board` - */ - -#define GPIO_MB1_CD (GPIO_INPUT|GPIO_FLOAT|GPIO_EXTI|GPIO_PORTA|GPIO_PIN2) -#define GPIO_MB2_CD (GPIO_INPUT|GPIO_FLOAT|GPIO_EXTI|GPIO_PORTA|GPIO_PIN3) - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/* This structure holds static information unique to one MMCSD slot */ - -struct stm32_mmcsd_state_s -{ - uint8_t spidev; /* SPI bus used for MMCSD */ - uint8_t slotno; /* Slot number */ - int minor; /* The MMC/SD minor device number */ - uint32_t cdcfg; /* Card detect PIO pin configuration */ - xcpt_t handler; /* Interrupt handler */ - bool cd; /* TRUE: card is inserted */ - spi_mediachange_t callback; /* SPI media change callback */ - void *cbarg; /* Argument to pass to media change callback */ - struct work_s work; /* For deferring card detect interrupt work */ -}; - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -static bool stm32_cardinserted_internal(struct stm32_mmcsd_state_s *state); -static void stm32_mmcsd_carddetect(void *arg); -static int stm32_mmcsd_setup(struct stm32_mmcsd_state_s *); - -#ifdef CONFIG_CLICKER2_STM32_MB1_MMCSD -static int stm32_mb1_mmcsd_carddetect(int irq, - void *regs, - void *arg); -#endif - -#ifdef CONFIG_CLICKER2_STM32_MB2_MMCSD -static int stm32_mb2_mmcsd_carddetect(int irq, - void *regs, - void *arg); -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* MMCSD device state */ - -#ifdef CONFIG_CLICKER2_STM32_MB1_MMCSD -static int stm32_mb1_mmcsd_carddetect(int irq, void *regs, void *arg); - -static struct stm32_mmcsd_state_s g_mb1_mmcsd = -{ - .spidev = 3, - .slotno = MB1_MMCSD_SLOTNO, - .minor = MB1_MMCSD_MINOR, - .cdcfg = GPIO_MB1_CD, - .handler = stm32_mb1_mmcsd_carddetect, - .callback = NULL, - .cbarg = NULL, -}; -#endif - -#ifdef CONFIG_CLICKER2_STM32_MB2_MMCSD -static int stm32_mb2_mmcsd_carddetect(int irq, void *regs, void *arg); - -static struct stm32_mmcsd_state_s g_mb2_mmcsd = -{ - .spidev = 2, - .slotno = MB2_MMCSD_SLOTNO, - .minor = MB2_MMCSD_MINOR, - .cdcfg = GPIO_MB2_CD, - .handler = stm32_mb2_mmcsd_carddetect, - .callback = NULL, - .cbarg = NULL, -}; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_cardinserted_internal - * - * Description: - * Check if a card is inserted into the selected MMCSD slot - * - ****************************************************************************/ - -static bool stm32_cardinserted_internal(struct stm32_mmcsd_state_s *state) -{ - bool inserted; - - /* Get the state of the PIO pin */ - - inserted = stm32_gpioread(state->cdcfg); - finfo("Slot %d inserted: %s\n", state->slotno, inserted ? "NO" : "YES"); - return !inserted; -} - -/**************************************************************************** - * Name: stm32_mmcsd_carddetect, stm32_mb1_mmcsd_carddetect, and - * stm32_mb2_mmcsd_carddetect - * - * Description: - * Card detect interrupt handlers - * - ****************************************************************************/ - -static void stm32_mmcsd_carddetect(void *arg) -{ - bool cd; - struct stm32_mmcsd_state_s *state = - (struct stm32_mmcsd_state_s *)arg; - - /* Get the current card insertion state */ - - cd = stm32_cardinserted_internal(state); - - /* Has the card detect state changed? */ - - if (cd != state->cd) - { - /* Yes... remember that new state and inform the HSMCI driver */ - - state->cd = cd; - - /* Report the new state to the SPI driver */ - - if (state->callback) - { - state->callback(state->cbarg); - } - } - -#ifdef HAVE_AUTOMOUNTER - /* Let the automounter know about the insertion event */ - - stm32_automount_event(state->slotno, stm32_cardinserted(state->slotno)); -#endif -} - -#ifdef CONFIG_CLICKER2_STM32_MB1_MMCSD -static int stm32_mb1_mmcsd_carddetect(int irq, void *regs, void *arg) -{ - if (work_available(&g_mb1_mmcsd.work)) - { - return work_queue(MMCSDWORK, &g_mb1_mmcsd.work, stm32_mmcsd_carddetect, - &g_mb1_mmcsd, 0); - } - - return OK; -} -#endif - -#ifdef CONFIG_CLICKER2_STM32_MB2_MMCSD -static int stm32_mb2_mmcsd_carddetect(int irq, void *regs, void *arg) -{ - if (work_available(&g_mb2_mmcsd.work)) - { - return work_queue(MMCSDWORK, &g_mb2_mmcsd.work, stm32_mmcsd_carddetect, - &g_mb2_mmcsd, 0); - } - - return OK; -} -#endif - -static int stm32_mmcsd_setup(struct stm32_mmcsd_state_s *state) -{ - struct spi_dev_s *spi; - int ret; - - /* Initialize the SPI bus and get an instance of the SPI interface */ - - spi = stm32_spibus_initialize(state->spidev); - if (spi == NULL) - { - spierr("ERROR: Failed to initialize SPI bus %d\n", state->spidev); - return -ENODEV; - } - - ret = mmcsd_spislotinitialize(state->minor, state->slotno, spi); - if (ret < 0) - { - mcerr("ERROR: Failed to bind SPI port %d to SD slot %d\n", - state->spidev, state->slotno); - return ret; - } - - /* Initialize Card Detect pin and enable interrupt on edges */ - - stm32_configgpio(state->cdcfg); - stm32_gpiosetevent(state->cdcfg, true, true, true, state->handler, NULL); - - state->cd = stm32_cardinserted_internal(state); - if (state->callback) - { - state->callback(state->cbarg); - } - -#ifdef HAVE_AUTOMOUNTER - /* Let the automounter know about the insertion event */ - - stm32_automount_event(state->slotno, stm32_cardinserted(state->slotno)); -#endif - - mcinfo("INFO: mmcsd%d card has been initialized successfully\n", - state->minor); - return OK; -} - -/**************************************************************************** - * Public Function - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_mmcsd_initialize - * - * Description: - * Initialize the MMCSD device. - * - * Returned Value: - * Zero is returned on success. Otherwise, a negated errno value is - * returned to indicate the nature of the failure. - * - ****************************************************************************/ - -int stm32_mmcsd_initialize(void) -{ - int ret; - -#ifdef CONFIG_CLICKER2_STM32_MB1_MMCSD - finfo("Configuring MMCSD on mikroBUS1\n"); - - ret = stm32_mmcsd_setup(&g_mb1_mmcsd); - if (ret < 0) - { - mcerr("ERROR: Failed to initialize MMCSD on mikroBus1: %d\n", ret); - } -#endif - -#ifdef CONFIG_CLICKER2_STM32_MB2_MMCSD - finfo("Configuring MMCSD on mikroBUS2\n"); - ret = stm32_mmcsd_setup(&g_mb2_mmcsd); - if (ret < 0) - { - mcerr("ERROR: Failed to initialize MMCSD on mikroBus2: %d\n", ret); - } -#endif - - UNUSED(ret); - return OK; -} - -/**************************************************************************** - * Name: stm32_cardinserted - * - * Description: - * Check if a card is inserted into the selected MMCSD slot - * - ****************************************************************************/ - -bool stm32_cardinserted(int slotno) -{ - struct stm32_mmcsd_state_s *state; - - /* Get the MMCSD description */ - -#ifdef CONFIG_CLICKER2_STM32_MB1_MMCSD - if (slotno == g_mb1_mmcsd.slotno) - { - state = &g_mb1_mmcsd; - } -#endif -#ifdef CONFIG_CLICKER2_STM32_MB2_MMCSD - - if (slotno == g_mb2_mmcsd.slotno) - { - state = &g_mb2_mmcsd; - } -#endif - - if (!state) - { - ferr("ERROR: No state for slotno %d\n", slotno); - return false; - } - - /* Return the state of the CD pin */ - - return stm32_cardinserted_internal(state); -} - -/**************************************************************************** - * Name: stm32_spi2register - * - * Description: - * Registers media change callback - ****************************************************************************/ - -int stm32_spi2register(struct spi_dev_s *dev, spi_mediachange_t callback, - void *arg) -{ - spiinfo("INFO: Registering spi2 device\n"); -#ifdef CONFIG_CLICKER2_STM32_MB2_MMCSD - g_mb2_mmcsd.callback = callback; - g_mb2_mmcsd.cbarg = arg; -#endif - return OK; -} - -/**************************************************************************** - * Name: stm32_spi3register - * - * Description: - * Registers media change callback - ****************************************************************************/ - -int stm32_spi3register(struct spi_dev_s *dev, spi_mediachange_t callback, - void *arg) -{ - spiinfo("INFO: Registering spi3 device\n"); -#ifdef CONFIG_CLICKER2_STM32_MB1_MMCSD - g_mb1_mmcsd.callback = callback; - g_mb1_mmcsd.cbarg = arg; -#endif - return OK; -} - -#endif /* CONFIG_MMCSD_SPI */ diff --git a/boards/arm/stm32/clicker2-stm32/src/stm32_mrf24j40.c b/boards/arm/stm32/clicker2-stm32/src/stm32_mrf24j40.c deleted file mode 100644 index 35b8324947995..0000000000000 --- a/boards/arm/stm32/clicker2-stm32/src/stm32_mrf24j40.c +++ /dev/null @@ -1,328 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/clicker2-stm32/src/stm32_mrf24j40.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -#include "stm32_gpio.h" -#include "stm32_exti.h" -#include "stm32_spi.h" - -#include "clicker2-stm32.h" - -#ifdef CONFIG_IEEE802154_MRF24J40 - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#ifndef CONFIG_DRIVERS_WIRELESS -# error Wireless support requires CONFIG_DRIVERS_WIRELESS -#endif - -#if !defined(CONFIG_CLICKER2_STM32_MB1_BEE) && \ - !defined(CONFIG_CLICKER2_STM32_MB2_BEE) -# error Only the Mikroe BEE board is supported -#endif - -#ifdef CONFIG_CLICKER2_STM32_MB1_BEE -# ifndef CONFIG_STM32_SPI3 -# error Mikroe BEE on mikroBUS1 requires CONFIG_STM32_SPI3 -# endif -#endif - -#ifdef CONFIG_CLICKER2_STM32_MB2_BEE -# ifndef CONFIG_STM32_SPI2 -# error Mikroe BEE on mikroBUS1 requires CONFIG_STM32_SPI2 -# endif -#endif - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -struct stm32_priv_s -{ - struct mrf24j40_lower_s dev; - xcpt_t handler; - void *arg; - uint32_t intcfg; - uint8_t spidev; -}; - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -/* IRQ/GPIO access callbacks. These operations all hidden behind callbacks - * to isolate the MRF24J40 driver from differences in GPIO interrupt handling - * varying boards and MCUs. - * - * irq_attach - Attach the MRF24J40 interrupt handler to the GPIO - * interrupt - * irq_enable - Enable or disable the GPIO interrupt - */ - -static int stm32_attach_irq(const struct mrf24j40_lower_s *lower, - xcpt_t handler, void *arg); -static void stm32_enable_irq(const struct mrf24j40_lower_s *lower, - bool state); -static int stm32_mrf24j40_devsetup(struct stm32_priv_s *priv); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* A reference to a structure of this type must be passed to the MRF24J40 - * driver. This structure provides information about the configuration - * of the MRF24J40 and provides some board-specific hooks. - * - * Memory for this structure is provided by the caller. It is not copied - * by the driver and is presumed to persist while the driver is active. The - * memory must be writable because, under certain circumstances, the driver - * may modify frequency or X plate resistance values. - */ - -#ifdef CONFIG_CLICKER2_STM32_MB1_BEE -static struct stm32_priv_s g_mrf24j40_mb1_priv = -{ - .dev.attach = stm32_attach_irq, - .dev.enable = stm32_enable_irq, - .handler = NULL, - .arg = NULL, - .intcfg = GPIO_MB1_INT, - .spidev = 3, -}; -#endif - -#ifdef CONFIG_CLICKER2_STM32_MB2_BEE -static struct stm32_priv_s g_mrf24j40_mb2_priv = -{ - .dev.attach = stm32_attach_irq, - .dev.enable = stm32_enable_irq, - .handler = NULL, - .arg = NULL, - .intcfg = GPIO_MB2_INT, - .spidev = 2, -}; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/* IRQ/GPIO access callbacks. These operations all hidden behind - * callbacks to isolate the MRF24J40 driver from differences in GPIO - * interrupt handling by varying boards and MCUs. If possible, - * interrupts should be configured on both rising and falling edges - * so that contact and loss-of-contact events can be detected. - * - * irq_attach - Attach the MRF24J40 interrupt handler to the GPIO - * interrupt - * irq_enable - Enable or disable the GPIO interrupt - */ - -static int stm32_attach_irq(const struct mrf24j40_lower_s *lower, - xcpt_t handler, void *arg) -{ - struct stm32_priv_s *priv = (struct stm32_priv_s *)lower; - - DEBUGASSERT(priv != NULL); - - /* Just save the handler for use when the interrupt is enabled */ - - priv->handler = handler; - priv->arg = arg; - return OK; -} - -static void stm32_enable_irq(const struct mrf24j40_lower_s *lower, - bool state) -{ - struct stm32_priv_s *priv = (struct stm32_priv_s *)lower; - - /* The caller should not attempt to enable interrupts if the handler - * has not yet been 'attached' - */ - - DEBUGASSERT(priv != NULL && (priv->handler != NULL || !state)); - -#ifdef CONFIG_CLICKER2_STM32_MRF24J40LH_VERBOSE - wlinfo("state:%d\n", (int)state); -#endif - - /* Attach and enable, or detach and disable */ - - if (state) - { - stm32_gpiosetevent(priv->intcfg, false, true, true, - priv->handler, priv->arg); - } - else - { - stm32_gpiosetevent(priv->intcfg, false, false, false, - NULL, NULL); - } -} - -/**************************************************************************** - * Name: stm32_mrf24j40_devsetup - * - * Description: - * Initialize one the MRF24J40 device in one mikroBUS slot - * - * Returned Value: - * Zero is returned on success. Otherwise, a negated errno value is - * returned to indicate the nature of the failure. - * - ****************************************************************************/ - -static int stm32_mrf24j40_devsetup(struct stm32_priv_s *priv) -{ - struct ieee802154_radio_s *radio; - MACHANDLE mac; - struct spi_dev_s *spi; - int ret; - - /* Configure the interrupt pin */ - - stm32_configgpio(priv->intcfg); - - /* Initialize the SPI bus and get an instance of the SPI interface */ - - spi = stm32_spibus_initialize(priv->spidev); - if (spi == NULL) - { - wlerr("ERROR: Failed to initialize SPI bus %d\n", priv->spidev); - return -ENODEV; - } - - /* Initialize and register the SPI MRF24J40 device */ - - radio = mrf24j40_init(spi, &priv->dev); - if (radio == NULL) - { - wlerr("ERROR: Failed to initialize SPI bus %d\n", priv->spidev); - return -ENODEV; - } - - /* Create a 802.15.4 MAC device from a 802.15.4 compatible radio device. */ - - mac = mac802154_create(radio); - if (mac == NULL) - { - wlerr("ERROR: Failed to initialize IEEE802.15.4 MAC\n"); - return -ENODEV; - } - -#ifdef CONFIG_IEEE802154_NETDEV - /* Use the IEEE802.15.4 MAC interface instance to create a 6LoWPAN - * network interface by wrapping the MAC interface instance in a - * network device driver via mac802154dev_register(). - */ - - ret = mac802154netdev_register(mac); - if (ret < 0) - { - wlerr("ERROR: Failed to register the MAC network driver wpan%d: %d\n", - 0, ret); - return ret; - } -#endif - -#ifdef CONFIG_IEEE802154_MACDEV - /* If want to call these APIs from userspace, you have to wrap the MAC - * interface in a character device viamac802154dev_register(). - */ - - ret = mac802154dev_register(mac, 0); - if (ret < 0) - { - wlerr("ERROR:"); - wlerr(" Failed to register the MAC character driver /dev/ieee%d: %d\n", - 0, ret); - return ret; - } -#endif - - UNUSED(ret); - return OK; -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_mrf24j40_initialize - * - * Description: - * Initialize the MRF24J40 device. - * - * Returned Value: - * Zero is returned on success. Otherwise, a negated errno value is - * returned to indicate the nature of the failure. - * - ****************************************************************************/ - -int stm32_mrf24j40_initialize(void) -{ - int ret; - -#ifdef CONFIG_CLICKER2_STM32_MB1_BEE - wlinfo("Configuring BEE in mikroBUS1\n"); - - ret = stm32_mrf24j40_devsetup(&g_mrf24j40_mb1_priv); - if (ret < 0) - { - wlerr("ERROR: Failed to initialize BD in mikroBUS1: %d\n", ret); - } -#endif - -#ifdef CONFIG_CLICKER2_STM32_MB2_BEE - wlinfo("Configuring BEE in mikroBUS2\n"); - - ret = stm32_mrf24j40_devsetup(&g_mrf24j40_mb2_priv); - if (ret < 0) - { - wlerr("ERROR: Failed to initialize BD in mikroBUS2: %d\n", ret); - } -#endif - - UNUSED(ret); - return OK; -} -#endif /* CONFIG_IEEE802154_MRF24J40 */ diff --git a/boards/arm/stm32/clicker2-stm32/src/stm32_spi.c b/boards/arm/stm32/clicker2-stm32/src/stm32_spi.c deleted file mode 100644 index 26df2d0e6d353..0000000000000 --- a/boards/arm/stm32/clicker2-stm32/src/stm32_spi.c +++ /dev/null @@ -1,268 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/clicker2-stm32/src/stm32_spi.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include - -#include -#include - -#include "arm_internal.h" -#include "chip.h" -#include "stm32.h" - -#include "clicker2-stm32.h" - -#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || defined(CONFIG_STM32_SPI3) - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_spidev_initialize - * - * Description: - * Called to configure SPI chip select GPIO pins for the Mikroe Clicker2 - * STM32 board. - * - ****************************************************************************/ - -void weak_function stm32_spidev_initialize(void) -{ -#if defined(CONFIG_STM32_SPI3) && defined(CONFIG_CLICKER2_STM32_MB1_SPI) - /* Enable chip select for mikroBUS1 */ - - stm32_configgpio(GPIO_MB1_CS); -#endif -#if defined(CONFIG_STM32_SPI2) && defined(CONFIG_CLICKER2_STM32_MB2_SPI) - /* Enable chip select for mikroBUS2 */ - - stm32_configgpio(GPIO_MB2_CS); -#endif -} - -/**************************************************************************** - * Name: stm32_spi1/2/3select and stm32_spi1/2/3status - * - * Description: - * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status - * must be provided by board-specific logic. They are implementations of - * the select and status methods of the SPI interface defined by struct - * spi_ops_s (see include/nuttx/spi/spi.h). All other methods - * (including stm32_spibus_initialize()) are provided by common STM32 - * logic. To use this common SPI logic on your board: - * - * 1. Provide logic in stm32_boardinitialize() to configure SPI chip select - * pins. - * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() functions - * in your board-specific logic. These functions will perform chip - * selection and status operations using GPIOs in the way your board is - * configured. - * 3. Add a calls to stm32_spibus_initialize() in your low level - * application initialization logic - * 4. The handle returned by stm32_spibus_initialize() may then be used to - * bind the SPI driver to higher level logic (e.g., calling - * mmcsd_spislotinitialize(), for example, will bind the SPI driver to - * the SPI MMC/SD driver). - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_SPI1 -void stm32_spi1select(struct spi_dev_s *dev, - uint32_t devid, bool selected) -{ - spiinfo("devid: %d CS: %s\n", - (int)devid, selected ? "assert" : "de-assert"); -} - -uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) -{ - return 0; -} -#endif - -#ifdef CONFIG_STM32_SPI2 -void stm32_spi2select(struct spi_dev_s *dev, - uint32_t devid, bool selected) -{ - spiinfo("devid: %d CS: %s\n", - (int)devid, selected ? "assert" : "de-assert"); - - switch (devid) - { -#ifdef CONFIG_IEEE802154_MRF24J40 - case SPIDEV_IEEE802154(0): - - /* Set the GPIO low to select and high to de-select */ - - stm32_gpiowrite(GPIO_MB2_CS, !selected); - break; -#endif -#ifdef CONFIG_IEEE802154_XBEE - case SPIDEV_IEEE802154(0): - - /* Set the GPIO low to select and high to de-select */ - - stm32_gpiowrite(GPIO_MB2_CS, !selected); - break; -#endif -#ifdef CONFIG_MMCSD_SPI - case SPIDEV_MMCSD(0): - - /* Set the GPIO low to select and high to de-select */ - - stm32_gpiowrite(GPIO_MB2_CS, !selected); - break; -#endif - default: - break; - } -} - -uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) -{ - uint8_t status = 0; - -#ifdef CONFIG_CLICKER2_STM32_MB2_MMCSD - if (devid == SPIDEV_MMCSD(0)) - { - status = stm32_cardinserted(MB2_MMCSD_SLOTNO); - } -#endif - - return status; -} -#endif - -#ifdef CONFIG_STM32_SPI3 -void stm32_spi3select(struct spi_dev_s *dev, - uint32_t devid, bool selected) -{ - spiinfo("devid: %d CS: %s\n", - (int)devid, selected ? "assert" : "de-assert"); - - switch (devid) - { -#ifdef CONFIG_IEEE802154_MRF24J40 - case SPIDEV_IEEE802154(0): - - /* Set the GPIO low to select and high to de-select */ - - stm32_gpiowrite(GPIO_MB1_CS, !selected); - break; -#endif -#ifdef CONFIG_IEEE802154_XBEE - case SPIDEV_IEEE802154(0): - - /* Set the GPIO low to select and high to de-select */ - - stm32_gpiowrite(GPIO_MB1_CS, !selected); - break; -#endif -#ifdef CONFIG_MMCSD_SPI - case SPIDEV_MMCSD(0): - - /* Set the GPIO low to select and high to de-select */ - - stm32_gpiowrite(GPIO_MB1_CS, !selected); - break; -#endif - default: - break; - } -} - -uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid) -{ - uint8_t status = 0; - -#ifdef CONFIG_CLICKER2_STM32_MB1_MMCSD - if (devid == SPIDEV_MMCSD(0)) - { - status |= stm32_cardinserted(MB1_MMCSD_SLOTNO); - } -#endif - - return status; -} -#endif - -/**************************************************************************** - * Name: stm32_spi1cmddata - * - * Description: - * Set or clear the SH1101A A0 or SD1306 D/C n bit to select data (true) - * or command (false). This function must be provided by platform-specific - * logic. This is an implementation of the cmddata method of the SPI - * interface defined by struct spi_ops_s (see include/nuttx/spi/spi.h). - * - * Input Parameters: - * - * spi - SPI device that controls the bus the device that requires the CMD/ - * DATA selection. - * devid - If there are multiple devices on the bus, this selects which one - * to select cmd or data. NOTE: This design restricts, for example, - * one one SPI display per SPI bus. - * cmd - true: select command; false: select data - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef CONFIG_SPI_CMDDATA -#ifdef CONFIG_STM32_SPI1 -int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) -{ - return -ENODEV; -} -#endif - -#ifdef CONFIG_STM32_SPI2 -int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) -{ - /* To be provided */ - - return -ENODEV; -} -#endif - -#ifdef CONFIG_STM32_SPI3 -int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) -{ - /* To be provided */ - - return -ENODEV; -} -#endif -#endif /* CONFIG_SPI_CMDDATA */ - -#endif /* CONFIG_STM32_SPI1 || CONFIG_STM32_SPI2 */ diff --git a/boards/arm/stm32/clicker2-stm32/src/stm32_usb.c b/boards/arm/stm32/clicker2-stm32/src/stm32_usb.c deleted file mode 100644 index 5739adee9832d..0000000000000 --- a/boards/arm/stm32/clicker2-stm32/src/stm32_usb.c +++ /dev/null @@ -1,96 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/clicker2-stm32/src/stm32_usb.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include - -#include "stm32_otgfs.h" -#include "stm32_gpio.h" -#include "clicker2-stm32.h" - -#ifdef CONFIG_STM32_OTGFS - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#ifdef CONFIG_USBDEV -# define HAVE_USB 1 -#else -# warning "CONFIG_STM32_OTGFS is enabled but CONFIG_USBDEV is not" -# undef HAVE_USB -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_usb_configure - * - * Description: - * Called from stm32_boardinitialize very early in initialization to setup - * USB-related GPIO pins for the Olimex STM32 P407 board. - * - ****************************************************************************/ - -void stm32_usb_configure(void) -{ -#ifdef CONFIG_STM32_OTGFS - /* The OTG FS has an internal soft pull-up. - * No GPIO configuration is required - */ - - /* Configure the OTG FS VBUS sensing GPIO */ - - stm32_configgpio(GPIO_OTGFS_VBUS); -#endif -} - -/**************************************************************************** - * Name: stm32_usbsuspend - * - * Description: - * Board logic must provide the stm32_usbsuspend logic if the USBDEV - * driver is used. This function is called whenever the USB enters or - * leaves suspend mode. - * This is an opportunity for the board logic to shutdown clocks, power, - * etc. while the USB is suspended. - * - ****************************************************************************/ - -#ifdef CONFIG_USBDEV -void stm32_usbsuspend(struct usbdev_s *dev, bool resume) -{ - uinfo("resume: %d\n", resume); -} -#endif - -#endif /* CONFIG_STM32_OTGFS */ diff --git a/boards/arm/stm32/clicker2-stm32/src/stm32_userleds.c b/boards/arm/stm32/clicker2-stm32/src/stm32_userleds.c deleted file mode 100644 index 0ad9207c75189..0000000000000 --- a/boards/arm/stm32/clicker2-stm32/src/stm32_userleds.c +++ /dev/null @@ -1,89 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/clicker2-stm32/src/stm32_userleds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include "stm32.h" -#include "clicker2-stm32.h" - -#ifndef CONFIG_ARCH_LEDS - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_userled_initialize - ****************************************************************************/ - -uint32_t board_userled_initialize(void) -{ - /* Configure LED1-2 GPIOs for output */ - - stm32_configgpio(GPIO_LED1); - stm32_configgpio(GPIO_LED2); - return BOARD_NLEDS; -} - -/**************************************************************************** - * Name: board_userled - ****************************************************************************/ - -void board_userled(int led, bool ledon) -{ - gpioconfig_t ledcfg; - - if (led == BOARD_LED1) - { - ledcfg = GPIO_LED1; - } - else if (led == BOARD_LED2) - { - ledcfg = GPIO_LED2; - } - else - { - return; - } - - stm32_gpiowrite(ledcfg, true); -} - -/**************************************************************************** - * Name: board_userled_all - ****************************************************************************/ - -void board_userled_all(uint32_t ledset) -{ - stm32_gpiowrite(GPIO_LED1, (ledset & BOARD_LED1_BIT) != 0); - stm32_gpiowrite(GPIO_LED2, (ledset & BOARD_LED2_BIT) != 0); -} - -#endif /* !CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/cloudctrl/CMakeLists.txt b/boards/arm/stm32/cloudctrl/CMakeLists.txt deleted file mode 100644 index 17ccd5a4c7821..0000000000000 --- a/boards/arm/stm32/cloudctrl/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/cloudctrl/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32/cloudctrl/configs/nsh/defconfig b/boards/arm/stm32/cloudctrl/configs/nsh/defconfig deleted file mode 100644 index be4882c81d088..0000000000000 --- a/boards/arm/stm32/cloudctrl/configs/nsh/defconfig +++ /dev/null @@ -1,78 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_NSH_DISABLE_IFCONFIG is not set -# CONFIG_NSH_DISABLE_PS is not set -# CONFIG_SPI_CALLBACK is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="cloudctrl" -CONFIG_ARCH_BOARD_CLOUDCTRL=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F107VC=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=5483 -CONFIG_BUILTIN=y -CONFIG_ETH0_PHY_DM9161=y -CONFIG_FAT_LCNAMES=y -CONFIG_FAT_LFN=y -CONFIG_FS_FAT=y -CONFIG_HAVE_CXX=y -CONFIG_HOST_WINDOWS=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_MMCSD=y -CONFIG_MMCSD_SPICLOCK=12500000 -CONFIG_NET=y -CONFIG_NETDB_DNSCLIENT=y -CONFIG_NETDB_DNSSERVER_NOADDR=y -CONFIG_NETINIT_NOMAC=y -CONFIG_NETUTILS_TELNETD=y -CONFIG_NETUTILS_TFTPC=y -CONFIG_NETUTILS_WEBCLIENT=y -CONFIG_NET_ICMP_SOCKET=y -CONFIG_NET_MAX_LISTENPORTS=40 -CONFIG_NET_STATISTICS=y -CONFIG_NET_TCP=y -CONFIG_NET_TCP_PREALLOC_CONNS=40 -CONFIG_NET_UDP=y -CONFIG_NET_UDP_CHECKSUMS=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_MMCSDSPIPORTNO=1 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=65536 -CONFIG_RAM_START=0x20000000 -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_WAITPID=y -CONFIG_STM32_BKP=y -CONFIG_STM32_ETHMAC=y -CONFIG_STM32_ETH_REMAP=y -CONFIG_STM32_JTAG_FULL_ENABLE=y -CONFIG_STM32_PHYADDR=0 -CONFIG_STM32_PHYINIT=y -CONFIG_STM32_PHYSR=17 -CONFIG_STM32_PHYSR_100FD=0x8000 -CONFIG_STM32_PHYSR_100HD=0x4000 -CONFIG_STM32_PHYSR_10FD=0x2000 -CONFIG_STM32_PHYSR_10HD=0x1000 -CONFIG_STM32_PHYSR_ALTCONFIG=y -CONFIG_STM32_PHYSR_ALTMODE=0xf000 -CONFIG_STM32_PWR=y -CONFIG_STM32_RTC=y -CONFIG_STM32_SPI1=y -CONFIG_STM32_USART2=y -CONFIG_STM32_USART2_REMAP=y -CONFIG_SYSTEM_NSH=y -CONFIG_SYSTEM_PING=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART2_RXBUFSIZE=128 -CONFIG_USART2_SERIAL_CONSOLE=y -CONFIG_USART2_TXBUFSIZE=128 diff --git a/boards/arm/stm32/cloudctrl/include/board.h b/boards/arm/stm32/cloudctrl/include/board.h deleted file mode 100644 index 93955bad8b774..0000000000000 --- a/boards/arm/stm32/cloudctrl/include/board.h +++ /dev/null @@ -1,409 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/cloudctrl/include/board.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __BOARDS_ARM_STM32_CLOUDCTRL_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32_CLOUDCTRL_INCLUDE_BOARD_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#ifndef __ASSEMBLY__ -# include -#endif - -#include - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Clocking *****************************************************************/ - -/* HSI - 8 MHz RC factory-trimmed - * LSI - 40 KHz RC (30-60KHz, uncalibrated) - * HSE - On-board crystal frequency is 25MHz - * LSE - 32.768 kHz - */ - -#define STM32_BOARD_XTAL 25000000ul - -#define STM32_HSI_FREQUENCY 8000000ul -#define STM32_LSI_FREQUENCY 40000 -#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL -#define STM32_LSE_FREQUENCY 32768 - -/* PLL output is 72MHz */ - -#define STM32_PLL_PREDIV2 RCC_CFGR2_PREDIV2d5 /* 25MHz / 5 => 5MHz */ -#define STM32_PLL_PLL2MUL RCC_CFGR2_PLL2MULx8 /* 5MHz * 8 => 40MHz */ -#define STM32_PLL_PREDIV1 RCC_CFGR2_PREDIV1d5 /* 40MHz / 5 => 8MHz */ -#define STM32_PLL_PLLMUL RCC_CFGR_PLLMUL_CLKx9 /* 8MHz * 9 => 72Mhz */ -#define STM32_PLL_FREQUENCY (72000000) - -/* SYCLLK and HCLK are the PLL frequency */ - -#define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY -#define STM32_HCLK_FREQUENCY STM32_PLL_FREQUENCY - -/* APB2 clock (PCLK2) is HCLK (72MHz) */ - -#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK -#define STM32_PCLK2_FREQUENCY STM32_HCLK_FREQUENCY -#define STM32_APB2_CLKIN (STM32_PCLK2_FREQUENCY) /* Timers 2-7, 12-14 */ - -/* APB2 timers 1 and 8 will receive PCLK2. */ - -#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) - -/* APB1 clock (PCLK1) is HCLK/2 (36MHz) */ - -#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd2 -#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/2) - -/* APB1 timers 2-7 will be twice PCLK1 */ - -#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) - -/* MCO output driven by PLL3. From above, we already have PLL3 input - * frequency as: - * - * STM32_PLL_PREDIV2 = 5, 25MHz / 5 => 5MHz - */ - -#if defined(CONFIG_STM32_MII_MCO) || defined(CONFIG_STM32_RMII_MCO) -# define BOARD_CFGR_MCO_SOURCE RCC_CFGR_PLL3CLK /* Source: PLL3 */ -# define STM32_PLL_PLL3MUL RCC_CFGR2_PLL3MULx10 /* MCO 5MHz * 10 = 50MHz */ -#endif - -/* LED definitions **********************************************************/ - -/* If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs in - * any way. The following definitions are used to access individual LEDs. - */ - -/* LED index values for use with board_userled() */ - -#define BOARD_LED1 0 -#define BOARD_LED2 1 -#define BOARD_LED3 2 -#define BOARD_LED4 3 -#define BOARD_NLEDS 4 - -/* LED bits for use with board_userled_all() */ - -#define BOARD_LED1_BIT (1 << BOARD_LED1) -#define BOARD_LED2_BIT (1 << BOARD_LED2) -#define BOARD_LED3_BIT (1 << BOARD_LED3) -#define BOARD_LED4_BIT (1 << BOARD_LED4) - -/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the 4 LEDs on - * board the STM3240G-EVAL. - * The following definitions describe how NuttX controls the LEDs: - */ - -#define LED_STARTED 0 /* LED1 */ -#define LED_HEAPALLOCATE 1 /* LED2 */ -#define LED_IRQSENABLED 2 /* LED1 + LED2 */ -#define LED_STACKCREATED 3 /* LED3 */ -#define LED_INIRQ 4 /* LED1 + LED3 */ -#define LED_SIGNAL 5 /* LED2 + LED3 */ -#define LED_ASSERTION 6 /* LED1 + LED2 + LED3 */ -#define LED_PANIC 7 /* N/C + N/C + N/C + LED4 */ - -/* Button definitions *******************************************************/ - -/* The STM3240G-EVAL supports three buttons: */ - -#define BUTTON_KEY1 0 /* Name printed on board */ -#define BUTTON_KEY2 1 -#define BUTTON_KEY3 2 -#define NUM_BUTTONS 3 - -#define BUTTON_USERKEY BUTTON_KEY1 /* Names in schematic */ -#define BUTTON_TAMPER BUTTON_KEY2 -#define BUTTON_WAKEUP BUTTON_KEY3 - -#define BUTTON_KEY1_BIT (1 << BUTTON_KEY1) -#define BUTTON_KEY2_BIT (1 << BUTTON_KEY2) -#define BUTTON_KEY3_BIT (1 << BUTTON_KEY3) - -#define BUTTON_USERKEY_BIT BUTTON_KEY1_BIT -#define BUTTON_TAMPER_BIT BUTTON_KEY2_BIT -#define BUTTON_WAKEUP_BIT BUTTON_KEY3_BIT - -/* Relays */ - -#define NUM_RELAYS 2 - -/* Pin selections ***********************************************************/ - -/* Ethernet - * - * -- ---- -------------- --------------------------------------------------- - * PN NAME SIGNAL NOTES - * -- ---- -------------- --------------------------------------------------- - * 24 PA1 MII_RX_CLK Ethernet PHY NOTE: Despite the MII labeling of - * RMII_REF_CLK Ethernet PHY these signals, the DM916AEP is - * 25 PA2 MII_MDIO Ethernet PHY actually configured to work in - * 48 PB11 MII_TX_EN Ethernet PHY RMII mode. - * 51 PB12 MII_TXD0 Ethernet PHY - * 52 PB13 MII_TXD1 Ethernet PHY - * 16 PC1 MII_MDC Ethernet PHY - * 34 PC5 MII_INT Ethernet PHY - * 55 PD8 MII_RX_DV Ethernet PHY. Requires CONFIG_STM32_ETH_REMAP - * 55 PD8 RMII_CRSDV Ethernet PHY. Requires CONFIG_STM32_ETH_REMAP - * 56 PD9 MII_RXD0 Ethernet PHY. Requires CONFIG_STM32_ETH_REMAP - * 57 PD10 MII_RXD1 Ethernet PHY. Requires CONFIG_STM32_ETH_REMAP - * - * The board desdign can support a 50MHz external clock to drive the PHY - * (U9). However, on my board, U9 is not present. - * - * 67 PA8 MCO DM9161AEP - */ - -#ifdef CONFIG_STM32_ETHMAC -# ifndef CONFIG_STM32_ETH_REMAP -# error "STM32 Ethernet requires CONFIG_STM32_ETH_REMAP" -# endif -# ifndef CONFIG_STM32_RMII -# error "STM32 Ethernet requires CONFIG_STM32_RMII" -# endif -# ifndef CONFIG_STM32_RMII_MCO -# error "STM32 Ethernet requires CONFIG_STM32_RMII_MCO" -# endif -#endif - -/* USB - * - * -- ---- -------------- --------------------------------------------------- - * PN NAME SIGNAL NOTES - * -- ---- -------------- --------------------------------------------------- - * 68 PA9 USB_VBUS MINI-USB-AB. JP3 - * 69 PA10 USB_ID MINI-USB-AB. JP5 - * 70 PA11 USB_DM MINI-USB-AB - * 71 PA12 USB_DP MINI-USB-AB - * 95 PB8 USB_PWR Drives USB VBUS - */ - -/* UARTS/USARTS - * - * -- ---- -------------- --------------------------------------------------- - * PN NAME SIGNAL NOTES - * -- ---- -------------- --------------------------------------------------- - * 68 PA9 USART1_TX MAX3232 to CN5. Requires CONFIG_STM32_USART1_REMAP - * 69 PA10 USART1_RX MAX3232 to CN5. Requires CONFIG_STM32_USART1_REMAP - * 86 PD5 USART2_TX MAX3232 to CN6. Requires CONFIG_STM32_USART2_REMAP - * 87 PD6 USART2_RX MAX3232 to CN6. Requires CONFIG_STM32_USART2_REMAP - * 86 PD5 485_TX Same as USART2_TX but goes to SP3485 - * 87 PD6 485_RX Save as USART2_RX but goes to SP3485 (see JP4) - */ - -#if defined(CONFIG_STM32_USART1) && !defined(CONFIG_STM32_USART1_REMAP) -# error "CONFIG_STM32_USART1 requires CONFIG_STM32_USART1_REMAP" -#endif - -#if defined(CONFIG_STM32_USART2) && !defined(CONFIG_STM32_USART2_REMAP) -# error "CONFIG_STM32_USART2 requires CONFIG_STM32_USART2_REMAP" -#endif - -/* SPI - * - * -- ---- -------------- --------------------------------------------------- - * PN NAME SIGNAL NOTES - * -- ---- -------------- --------------------------------------------------- - * 30 PA5 SPI1_SCK To the SD card, SPI FLASH. - * Requires !CONFIG_STM32_SPI1_REMAP - * 31 PA6 SPI1_MISO To the SD card, SPI FLASH. - * Requires !CONFIG_STM32_SPI1_REMAP - * 32 PA7 SPI1_MOSI To the SD card, SPI FLASH. - * Requires !CONFIG_STM32_SPI1_REMAP - * 78 PC10 SPI3_SCK To TFT LCD (CN13), - * the NRF24L01 2.4G wireless module. - * Requires CONFIG_STM32_SPI3_REMAP. - * 79 PC11 SPI3_MISO To TFT LCD (CN13), - * the NRF24L01 2.4G wireless module. - * Requires CONFIG_STM32_SPI3_REMAP. - * 80 PC12 SPI3_MOSI To TFT LCD (CN13), - * the NRF24L01 2.4G wireless module. - * Requires CONFIG_STM32_SPI3_REMAP. - */ - -#if defined(CONFIG_STM32_SPI1) && defined(CONFIG_STM32_SPI1_REMAP) -# error "CONFIG_STM32_SPI1 must not have CONFIG_STM32_SPI1_REMAP" -#endif - -#if defined(CONFIG_STM32_SPI3) && !defined(CONFIG_STM32_SPI3_REMAP) -# error "CONFIG_STM32_SPI3 requires CONFIG_STM32_SPI3_REMAP" -#endif - -/* DAC - * - * -- ---- -------------- --------------------------------------------------- - * PN NAME SIGNAL NOTES - * -- ---- -------------- --------------------------------------------------- - * 29 PA4 DAC_OUT1 To CON5(CN14) - * 30 PA5 DAC_OUT2 To CON5(CN14). JP10 - */ - -/* ADC - * - * -- ---- -------------- --------------------------------------------------- - * PN NAME SIGNAL NOTES - * -- ---- -------------- --------------------------------------------------- - * 35 PB0 ADC_IN1 GPIO_ADC12_IN8. To CON5(CN14) - * 36 PB1 ADC_IN2 GPIO_ADC12_IN9. To CON5(CN14) - * 15 PC0 POTENTIO_METER GPIO_ADC12_IN10 - */ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -#ifndef __ASSEMBLY__ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_lcdclear - * - * Description: - * This is a non-standard LCD interface just for the Shenzhou board. - * Because of the various rotations, clearing the display in the normal - * way by writing a sequences of runs that covers the entire display can - * be very slow. Here the display is cleared by simply setting all GRAM - * memory to the specified color. - * - ****************************************************************************/ - -void stm32_lcdclear(uint16_t color); - -/**************************************************************************** - * Relay control functions - * - * Description: - * Non-standard functions for relay control from the Shenzhou board. - * - * NOTE: These must match the prototypes in include/nuttx/arch.h - * - ****************************************************************************/ - -#ifdef CONFIG_ARCH_RELAYS -void up_relaysinit(void); -void relays_setstat(int relays, bool stat); -bool relays_getstat(int relays); -void relays_setstats(uint32_t relays_stat); -uint32_t relays_getstats(void); -void relays_onoff(int relays, uint32_t mdelay); -void relays_onoffs(uint32_t relays_stat, uint32_t mdelay); -void relays_resetmode(int relays); -void relays_powermode(int relays); -void relays_resetmodes(uint32_t relays_stat); -void relays_powermodes(uint32_t relays_stat); -#endif - -/**************************************************************************** - * Chip ID functions - * - * Description: - * Non-standard functions to obtain chip ID information. - * - ****************************************************************************/ - -const char *stm32_getchipid(void); -const char *stm32_getchipid_string(void); - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ - -/* Alternate function pin selections (auto-aliased for new pinmap) */ - -/* USART2 */ - -#define GPIO_USART2_TX GPIO_ADJUST_MODE(GPIO_USART2_TX_0, GPIO_MODE_50MHz) -#define GPIO_USART2_RX GPIO_USART2_RX_0 -#define GPIO_USART2_CTS GPIO_USART2_CTS_0 -#define GPIO_USART2_RTS GPIO_ADJUST_MODE(GPIO_USART2_RTS_0, GPIO_MODE_50MHz) -#define GPIO_USART2_CK GPIO_ADJUST_MODE(GPIO_USART2_CK_0, GPIO_MODE_50MHz) - -/* SPI1 */ - -#define GPIO_SPI1_NSS GPIO_ADJUST_MODE(GPIO_SPI1_NSS_0, GPIO_MODE_50MHz) -#define GPIO_SPI1_SCK GPIO_ADJUST_MODE(GPIO_SPI1_SCK_0, GPIO_MODE_50MHz) -#define GPIO_SPI1_MISO GPIO_ADJUST_MODE(GPIO_SPI1_MISO_0, GPIO_MODE_50MHz) -#define GPIO_SPI1_MOSI GPIO_ADJUST_MODE(GPIO_SPI1_MOSI_0, GPIO_MODE_50MHz) - -/* MCO */ - -#define GPIO_MCO GPIO_ADJUST_MODE(GPIO_MCO_0, GPIO_MODE_50MHz) - -/* Ethernet (MII/RMII) */ - -#define GPIO_ETH_MDC GPIO_ADJUST_MODE(GPIO_ETH_MDC_0, GPIO_MODE_50MHz) -#define GPIO_ETH_MDIO GPIO_ADJUST_MODE(GPIO_ETH_MDIO_0, GPIO_MODE_50MHz) -#define GPIO_ETH_MII_COL GPIO_ETH_MII_COL_0 -#define GPIO_ETH_MII_CRS GPIO_ETH_MII_CRS_0 -#define GPIO_ETH_MII_RX_CLK GPIO_ETH_MII_RX_CLK_0 -#define GPIO_ETH_MII_RXD0 GPIO_ETH_MII_RXD0_0 -#define GPIO_ETH_MII_RXD1 GPIO_ETH_MII_RXD1_0 -#define GPIO_ETH_MII_RXD2 GPIO_ETH_MII_RXD2_0 -#define GPIO_ETH_MII_RXD3 GPIO_ETH_MII_RXD3_0 -#define GPIO_ETH_MII_RX_DV GPIO_ETH_MII_RX_DV_0 -#define GPIO_ETH_MII_RX_ER GPIO_ETH_MII_RX_ER_0 -#define GPIO_ETH_MII_TX_CLK GPIO_ETH_MII_TX_CLK_0 -#define GPIO_ETH_MII_TXD0 GPIO_ADJUST_MODE(GPIO_ETH_MII_TXD0_0, GPIO_MODE_50MHz) -#define GPIO_ETH_MII_TXD1 GPIO_ADJUST_MODE(GPIO_ETH_MII_TXD1_0, GPIO_MODE_50MHz) -#define GPIO_ETH_MII_TXD2 GPIO_ADJUST_MODE(GPIO_ETH_MII_TXD2_0, GPIO_MODE_50MHz) -#define GPIO_ETH_MII_TXD3 GPIO_ADJUST_MODE(GPIO_ETH_MII_TXD3_0, GPIO_MODE_50MHz) -#define GPIO_ETH_MII_TX_EN GPIO_ADJUST_MODE(GPIO_ETH_MII_TX_EN_0, GPIO_MODE_50MHz) -#define GPIO_ETH_RMII_CRS_DV GPIO_ETH_RMII_CRS_DV_0 -#define GPIO_ETH_RMII_REF_CLK GPIO_ETH_RMII_REF_CLK_0 -#define GPIO_ETH_RMII_RXD0 GPIO_ETH_RMII_RXD0_0 -#define GPIO_ETH_RMII_RXD1 GPIO_ETH_RMII_RXD1_0 -#define GPIO_ETH_RMII_TXD0 GPIO_ADJUST_MODE(GPIO_ETH_RMII_TXD0_0, GPIO_MODE_50MHz) -#define GPIO_ETH_RMII_TXD1 GPIO_ADJUST_MODE(GPIO_ETH_RMII_TXD1_0, GPIO_MODE_50MHz) -#define GPIO_ETH_RMII_TX_EN GPIO_ADJUST_MODE(GPIO_ETH_RMII_TX_EN_0, GPIO_MODE_50MHz) - -#endif /* __BOARDS_ARM_STM32_CLOUDCTRL_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32/cloudctrl/scripts/Make.defs b/boards/arm/stm32/cloudctrl/scripts/Make.defs deleted file mode 100644 index ef5f8e0d7da1d..0000000000000 --- a/boards/arm/stm32/cloudctrl/scripts/Make.defs +++ /dev/null @@ -1,48 +0,0 @@ -############################################################################ -# boards/arm/stm32/cloudctrl/scripts/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/.config -include $(TOPDIR)/tools/Config.mk -include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs - -# Pick the linker script - -ifeq ($(CONFIG_STM32_DFU),y) - LDSCRIPT = cloudctrl-dfu.ld -else - LDSCRIPT = cloudctrl.ld -endif - -ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) - -ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 - -CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) -CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) -CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -AFLAGS := $(CFLAGS) -D__ASSEMBLY__ - -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-gotoff.ld -no-check-sections -LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32/cloudctrl/src/CMakeLists.txt b/boards/arm/stm32/cloudctrl/src/CMakeLists.txt deleted file mode 100644 index 2c62ad02c35df..0000000000000 --- a/boards/arm/stm32/cloudctrl/src/CMakeLists.txt +++ /dev/null @@ -1,67 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/cloudctrl/src/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -set(SRCS stm32_boot.c stm32_spi.c stm32_chipid.c) - -if(CONFIG_ARCH_LEDS) - list(APPEND SRCS stm32_autoleds.c) -else() - list(APPEND SRCS stm32_userleds.c) -endif() - -if(CONFIG_ARCH_BUTTONS) - list(APPEND SRCS stm32_buttons.c) -endif() - -if(CONFIG_ARCH_RELAYS) - list(APPEND SRCS stm32_relays.c) -endif() - -if(CONFIG_STM32_OTGFS) - list(APPEND SRCS stm32_usb.c) -endif() - -if(CONFIG_MTD_W25) - list(APPEND SRCS stm32_w25.c) -endif() - -if(CONFIG_USBMSC) - list(APPEND SRCS stm32_usbmsc.c) -endif() - -if(CONFIG_ADC) - list(APPEND SRCS stm32_adc.c) -endif() - -if(CONFIG_STM32_PHYINIT) - list(APPEND SRCS stm32_phyinit.c) -endif() - -target_sources(board PRIVATE ${SRCS}) - -if(CONFIG_STM32_DFU) - set_property(GLOBAL PROPERTY LD_SCRIPT - "${NUTTX_BOARD_DIR}/scripts/cloudctrl-dfu.ld") -else() - set_property(GLOBAL PROPERTY LD_SCRIPT - "${NUTTX_BOARD_DIR}/scripts/cloudctrl.ld") -endif() diff --git a/boards/arm/stm32/cloudctrl/src/Make.defs b/boards/arm/stm32/cloudctrl/src/Make.defs deleted file mode 100644 index 746c1618cf64c..0000000000000 --- a/boards/arm/stm32/cloudctrl/src/Make.defs +++ /dev/null @@ -1,63 +0,0 @@ -############################################################################ -# boards/arm/stm32/cloudctrl/src/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/Make.defs - -CSRCS = stm32_boot.c stm32_spi.c stm32_chipid.c - -ifeq ($(CONFIG_ARCH_LEDS),y) -CSRCS += stm32_autoleds.c -else -CSRCS += stm32_userleds.c -endif - -ifeq ($(CONFIG_ARCH_BUTTONS),y) -CSRCS += stm32_buttons.c -endif - -ifeq ($(CONFIG_ARCH_RELAYS),y) -CSRCS += stm32_relays.c -endif - -ifeq ($(CONFIG_STM32_OTGFS),y) -CSRCS += stm32_usb.c -endif - -ifeq ($(CONFIG_MTD_W25),y) -CSRCS += stm32_w25.c -endif - -ifeq ($(CONFIG_USBMSC),y) -CSRCS += stm32_usbmsc.c -endif - -ifeq ($(CONFIG_ADC),y) -CSRCS += stm32_adc.c -endif - -ifeq ($(CONFIG_STM32_PHYINIT),y) -CSRCS += stm32_phyinit.c -endif - -DEPPATH += --dep-path board -VPATH += :board -CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/cloudctrl/src/stm32_adc.c b/boards/arm/stm32/cloudctrl/src/stm32_adc.c deleted file mode 100644 index 075adeb257a01..0000000000000 --- a/boards/arm/stm32/cloudctrl/src/stm32_adc.c +++ /dev/null @@ -1,164 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/cloudctrl/src/stm32_adc.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32_pwm.h" -#include "cloudctrl.h" - -#ifdef CONFIG_ADC - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -/* Up to 3 ADC interfaces are supported */ - -#if STM32_NADC < 3 -# undef CONFIG_STM32_ADC3 -#endif - -#if STM32_NADC < 2 -# undef CONFIG_STM32_ADC2 -#endif - -#if STM32_NADC < 1 -# undef CONFIG_STM32_ADC1 -#endif - -#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) || defined(CONFIG_STM32_ADC3) -#ifndef CONFIG_STM32_ADC1 -# warning "Channel information only available for ADC1" -#endif - -/* The number of ADC channels in the conversion list */ - -#define ADC1_NCHANNELS 1 - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* Identifying number of each ADC channel. The only internal signal for ADC - * testing is the potentiometer input: - * - * ADC1_IN10(PC0) Potentiometer - * - * External signals are also available on CON5 CN14: - * - * ADC_IN8 (PB0) CON5 CN14 Pin2 - * ADC_IN9 (PB1) CON5 CN14 Pin1 - */ - -#ifdef CONFIG_STM32_ADC1 -static const uint8_t g_chanlist[ADC1_NCHANNELS] = -{ - 10 /* {10, 8, 9}; */ -}; - -/* Configurations of pins used by each ADC channel */ - -static const uint32_t g_pinlist[ADC1_NCHANNELS] = -{ - GPIO_ADC12_IN10 -}; - -/* {GPIO_ADC12_IN10, GPIO_ADC12_IN8, GPIO_ADC12_IN9}; */ -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_adc_setup - * - * Description: - * Initialize ADC and register the ADC driver. - * - ****************************************************************************/ - -int stm32_adc_setup(void) -{ -#ifdef CONFIG_STM32_ADC1 - static bool initialized = false; - struct adc_dev_s *adc; - int ret; - int i; - - /* Check if we have already initialized */ - - if (!initialized) - { - /* Configure the pins as analog inputs for the selected channels */ - - for (i = 0; i < ADC1_NCHANNELS; i++) - { - stm32_configgpio(g_pinlist[i]); - } - - /* Call stm32_adcinitialize() to get an instance of the ADC interface */ - - adc = stm32_adcinitialize(1, g_chanlist, ADC1_NCHANNELS); - if (adc == NULL) - { - aerr("ERROR: Failed to get ADC interface\n"); - return -ENODEV; - } - - /* Register the ADC driver at "/dev/adc0" */ - - ret = adc_register("/dev/adc0", adc); - if (ret < 0) - { - aerr("ERROR: adc_register failed: %d\n", ret); - return ret; - } - - /* Now we are initialized */ - - initialized = true; - } - - return OK; -#else - return -ENOSYS; -#endif -} - -#endif /* CONFIG_STM32_ADC1 || CONFIG_STM32_ADC2 || CONFIG_STM32_ADC3 */ -#endif /* CONFIG_ADC */ diff --git a/boards/arm/stm32/cloudctrl/src/stm32_autoleds.c b/boards/arm/stm32/cloudctrl/src/stm32_autoleds.c deleted file mode 100644 index f4ecba575e85d..0000000000000 --- a/boards/arm/stm32/cloudctrl/src/stm32_autoleds.c +++ /dev/null @@ -1,376 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/cloudctrl/src/stm32_autoleds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32.h" -#include "cloudctrl.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* The following definitions map the encoded LED setting to GPIO settings */ - -#define CLOUDCTRL_LED1 (1 << 0) -#define CLOUDCTRL_LED2 (1 << 1) -#define CLOUDCTRL_LED3 (1 << 2) -#define CLOUDCTRL_LED4 (1 << 3) - -#define ON_SETBITS_SHIFT (0) -#define ON_CLRBITS_SHIFT (4) -#define OFF_SETBITS_SHIFT (8) -#define OFF_CLRBITS_SHIFT (12) - -#define ON_BITS(v) ((v) & 0xff) -#define OFF_BITS(v) (((v) >> 8) & 0x0ff) -#define SETBITS(b) ((b) & 0x0f) -#define CLRBITS(b) (((b) >> 4) & 0x0f) - -#define ON_SETBITS(v) (SETBITS(ON_BITS(v)) -#define ON_CLRBITS(v) (CLRBITS(ON_BITS(v)) -#define OFF_SETBITS(v) (SETBITS(OFF_BITS(v)) -#define OFF_CLRBITS(v) (CLRBITS(OFF_BITS(v)) - -#define LED_STARTED_ON_SETBITS ((CLOUDCTRL_LED1) << ON_SETBITS_SHIFT) -#define LED_STARTED_ON_CLRBITS ((CLOUDCTRL_LED2|CLOUDCTRL_LED3|CLOUDCTRL_LED4) << ON_CLRBITS_SHIFT) -#define LED_STARTED_OFF_SETBITS (0 << OFF_SETBITS_SHIFT) -#define LED_STARTED_OFF_CLRBITS ((CLOUDCTRL_LED1|CLOUDCTRL_LED2|CLOUDCTRL_LED3|CLOUDCTRL_LED4) << OFF_CLRBITS_SHIFT) - -#define LED_HEAPALLOCATE_ON_SETBITS ((CLOUDCTRL_LED2) << ON_SETBITS_SHIFT) -#define LED_HEAPALLOCATE_ON_CLRBITS ((CLOUDCTRL_LED1|CLOUDCTRL_LED3|CLOUDCTRL_LED4) << ON_CLRBITS_SHIFT) -#define LED_HEAPALLOCATE_OFF_SETBITS ((CLOUDCTRL_LED1) << OFF_SETBITS_SHIFT) -#define LED_HEAPALLOCATE_OFF_CLRBITS ((CLOUDCTRL_LED2|CLOUDCTRL_LED3|CLOUDCTRL_LED4) << OFF_CLRBITS_SHIFT) - -#define LED_IRQSENABLED_ON_SETBITS ((CLOUDCTRL_LED1|CLOUDCTRL_LED2) << ON_SETBITS_SHIFT) -#define LED_IRQSENABLED_ON_CLRBITS ((CLOUDCTRL_LED3|CLOUDCTRL_LED4) << ON_CLRBITS_SHIFT) -#define LED_IRQSENABLED_OFF_SETBITS ((CLOUDCTRL_LED2) << OFF_SETBITS_SHIFT) -#define LED_IRQSENABLED_OFF_CLRBITS ((CLOUDCTRL_LED1|CLOUDCTRL_LED3|CLOUDCTRL_LED4) << OFF_CLRBITS_SHIFT) - -#define LED_STACKCREATED_ON_SETBITS ((CLOUDCTRL_LED3) << ON_SETBITS_SHIFT) -#define LED_STACKCREATED_ON_CLRBITS ((CLOUDCTRL_LED1|CLOUDCTRL_LED2|CLOUDCTRL_LED4) << ON_CLRBITS_SHIFT) -#define LED_STACKCREATED_OFF_SETBITS ((CLOUDCTRL_LED1|CLOUDCTRL_LED2) << OFF_SETBITS_SHIFT) -#define LED_STACKCREATED_OFF_CLRBITS ((CLOUDCTRL_LED3|CLOUDCTRL_LED4) << OFF_CLRBITS_SHIFT) - -#define LED_INIRQ_ON_SETBITS ((CLOUDCTRL_LED1) << ON_SETBITS_SHIFT) -#define LED_INIRQ_ON_CLRBITS ((0) << ON_CLRBITS_SHIFT) -#define LED_INIRQ_OFF_SETBITS ((0) << OFF_SETBITS_SHIFT) -#define LED_INIRQ_OFF_CLRBITS ((CLOUDCTRL_LED1) << OFF_CLRBITS_SHIFT) - -#define LED_SIGNAL_ON_SETBITS ((CLOUDCTRL_LED2) << ON_SETBITS_SHIFT) -#define LED_SIGNAL_ON_CLRBITS ((0) << ON_CLRBITS_SHIFT) -#define LED_SIGNAL_OFF_SETBITS ((0) << OFF_SETBITS_SHIFT) -#define LED_SIGNAL_OFF_CLRBITS ((CLOUDCTRL_LED2) << OFF_CLRBITS_SHIFT) - -#define LED_ASSERTION_ON_SETBITS ((CLOUDCTRL_LED3) << ON_SETBITS_SHIFT) -#define LED_ASSERTION_ON_CLRBITS ((0) << ON_CLRBITS_SHIFT) -#define LED_ASSERTION_OFF_SETBITS ((0) << OFF_SETBITS_SHIFT) -#define LED_ASSERTION_OFF_CLRBITS ((CLOUDCTRL_LED3) << OFF_CLRBITS_SHIFT) - -#define LED_PANIC_ON_SETBITS ((CLOUDCTRL_LED3) << ON_SETBITS_SHIFT) -#define LED_PANIC_ON_CLRBITS ((0) << ON_CLRBITS_SHIFT) -#define LED_PANIC_OFF_SETBITS ((0) << OFF_SETBITS_SHIFT) -#define LED_PANIC_OFF_CLRBITS ((CLOUDCTRL_LED3) << OFF_CLRBITS_SHIFT) - -/**************************************************************************** - * Private Function Protototypes - ****************************************************************************/ - -/* LED State Controls */ - -static inline void led_clrbits(unsigned int clrbits); -static inline void led_setbits(unsigned int setbits); -static void led_setonoff(unsigned int bits); - -/* LED Power Management */ - -#ifdef CONFIG_PM -static void led_pm_notify(struct pm_callback_s *cb, int domain, - enum pm_state_e pmstate); -static int led_pm_prepare(struct pm_callback_s *cb, int domain, - enum pm_state_e pmstate); -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -static const uint16_t g_ledbits[8] = -{ - (LED_STARTED_ON_SETBITS | LED_STARTED_ON_CLRBITS | - LED_STARTED_OFF_SETBITS | LED_STARTED_OFF_CLRBITS), - - (LED_HEAPALLOCATE_ON_SETBITS | LED_HEAPALLOCATE_ON_CLRBITS | - LED_HEAPALLOCATE_OFF_SETBITS | LED_HEAPALLOCATE_OFF_CLRBITS), - - (LED_IRQSENABLED_ON_SETBITS | LED_IRQSENABLED_ON_CLRBITS | - LED_IRQSENABLED_OFF_SETBITS | LED_IRQSENABLED_OFF_CLRBITS), - - (LED_STACKCREATED_ON_SETBITS | LED_STACKCREATED_ON_CLRBITS | - LED_STACKCREATED_OFF_SETBITS | LED_STACKCREATED_OFF_CLRBITS), - - (LED_INIRQ_ON_SETBITS | LED_INIRQ_ON_CLRBITS | - LED_INIRQ_OFF_SETBITS | LED_INIRQ_OFF_CLRBITS), - - (LED_SIGNAL_ON_SETBITS | LED_SIGNAL_ON_CLRBITS | - LED_SIGNAL_OFF_SETBITS | LED_SIGNAL_OFF_CLRBITS), - - (LED_ASSERTION_ON_SETBITS | LED_ASSERTION_ON_CLRBITS | - LED_ASSERTION_OFF_SETBITS | LED_ASSERTION_OFF_CLRBITS), - - (LED_PANIC_ON_SETBITS | LED_PANIC_ON_CLRBITS | - LED_PANIC_OFF_SETBITS | LED_PANIC_OFF_CLRBITS) -}; - -#ifdef CONFIG_PM -static struct pm_callback_s g_ledscb = -{ - .notify = led_pm_notify, - .prepare = led_pm_prepare, -}; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: led_clrbits - * - * Description: - * Clear all LEDs to the bit encoded state - * - ****************************************************************************/ - -static inline void led_clrbits(unsigned int clrbits) -{ - /* All LEDs are pulled up and, hence, active low */ - - if ((clrbits & CLOUDCTRL_LED1) != 0) - { - stm32_gpiowrite(GPIO_LED1, true); - } - - if ((clrbits & CLOUDCTRL_LED2) != 0) - { - stm32_gpiowrite(GPIO_LED2, true); - } - - if ((clrbits & CLOUDCTRL_LED3) != 0) - { - stm32_gpiowrite(GPIO_LED3, true); - } - - if ((clrbits & CLOUDCTRL_LED4) != 0) - { - stm32_gpiowrite(GPIO_LED4, true); - } -} - -/**************************************************************************** - * Name: led_setbits - * - * Description: - * Set all LEDs to the bit encoded state - * - ****************************************************************************/ - -static inline void led_setbits(unsigned int setbits) -{ - /* All LEDs are pulled up and, hence, active low */ - - if ((setbits & CLOUDCTRL_LED1) != 0) - { - stm32_gpiowrite(GPIO_LED1, false); - } - - if ((setbits & CLOUDCTRL_LED2) != 0) - { - stm32_gpiowrite(GPIO_LED2, false); - } - - if ((setbits & CLOUDCTRL_LED3) != 0) - { - stm32_gpiowrite(GPIO_LED3, false); - } - - if ((setbits & CLOUDCTRL_LED4) != 0) - { - stm32_gpiowrite(GPIO_LED4, false); - } -} - -/**************************************************************************** - * Name: led_setonoff - * - * Description: - * Set/clear all LEDs to the bit encoded state - * - ****************************************************************************/ - -static void led_setonoff(unsigned int bits) -{ - led_clrbits(CLRBITS(bits)); - led_setbits(SETBITS(bits)); -} - -/**************************************************************************** - * Name: led_pm_notify - * - * Description: - * Notify the driver of new power state. This callback is called after - * all drivers have had the opportunity to prepare for the new power state. - * - ****************************************************************************/ - -#ifdef CONFIG_PM -static void led_pm_notify(struct pm_callback_s *cb, int domain, - enum pm_state_e pmstate) -{ - switch (pmstate) - { - case PM_NORMAL: - { - /* Restore normal LEDs operation */ - } - break; - - case PM_IDLE: - { - /* Entering IDLE mode - Turn leds off */ - } - break; - - case PM_STANDBY: - { - /* Entering STANDBY mode - Logic for PM_STANDBY goes here */ - } - break; - - case PM_SLEEP: - { - /* Entering SLEEP mode - Logic for PM_SLEEP goes here */ - } - break; - - default: - { - /* Should not get here */ - } - break; - } -} -#endif - -/**************************************************************************** - * Name: led_pm_prepare - * - * Description: - * Request the driver to prepare for a new power state. This is a warning - * that the system is about to enter into a new power state. The driver - * should begin whatever operations that may be required to enter power - * state. The driver may abort the state change mode by returning a - * non-zero value from the callback function. - * - ****************************************************************************/ - -#ifdef CONFIG_PM -static int led_pm_prepare(struct pm_callback_s *cb, int domain, - enum pm_state_e pmstate) -{ - /* No preparation to change power modes is required by the LEDs driver. - * We always accept the state change by returning OK. - */ - - return OK; -} -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_autoled_initialize - ****************************************************************************/ - -#ifdef CONFIG_ARCH_LEDS -void board_autoled_initialize(void) -{ - /* Configure LED1-4 GPIOs for output */ - - stm32_configgpio(GPIO_LED1); - stm32_configgpio(GPIO_LED2); - stm32_configgpio(GPIO_LED3); - stm32_configgpio(GPIO_LED4); -} - -/**************************************************************************** - * Name: board_autoled_on - ****************************************************************************/ - -void board_autoled_on(int led) -{ - led_setonoff(ON_BITS(g_ledbits[led])); -} - -/**************************************************************************** - * Name: board_autoled_off - ****************************************************************************/ - -void board_autoled_off(int led) -{ - led_setonoff(OFF_BITS(g_ledbits[led])); -} - -/**************************************************************************** - * Name: up_ledpminitialize - ****************************************************************************/ - -#ifdef CONFIG_PM -void up_ledpminitialize(void) -{ - /* Register to receive power management callbacks */ - - int ret = pm_register(&g_ledscb); - if (ret != OK) - { - board_autoled_on(LED_ASSERTION); - } -} -#endif /* CONFIG_PM */ - -#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/cloudctrl/src/stm32_boot.c b/boards/arm/stm32/cloudctrl/src/stm32_boot.c deleted file mode 100644 index cd489c2ae3deb..0000000000000 --- a/boards/arm/stm32/cloudctrl/src/stm32_boot.c +++ /dev/null @@ -1,200 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/cloudctrl/src/stm32_boot.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include -#include -#include -#include - -#include -#include - -#include "arm_internal.h" -#include "stm32.h" -#include "cloudctrl.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -/* Assume that we support everything until convinced otherwise */ - -#define HAVE_USBDEV 1 -#define HAVE_USBHOST 1 -#define HAVE_W25 1 - -/* Can't support the W25 device if it SPI1 or W25 support is not enabled */ - -#if !defined(CONFIG_STM32_SPI1) || !defined(CONFIG_MTD_W25) -# undef HAVE_W25 -#endif - -/* Can't support W25 features if mountpoints are disabled */ - -#ifdef CONFIG_DISABLE_MOUNTPOINT -# undef HAVE_W25 -#endif - -/* Default W25 minor number */ - -#if defined(HAVE_W25) && !defined(CONFIG_NSH_W25MINOR) -# define CONFIG_NSH_W25MINOR 0 -#endif - -/* Can't support USB host or device features if USB OTG FS is not enabled */ - -#ifndef CONFIG_STM32_OTGFS -# undef HAVE_USBDEV -# undef HAVE_USBHOST -#endif - -/* Can't support USB device is USB device is not enabled */ - -#ifndef CONFIG_USBDEV -# undef HAVE_USBDEV -#endif - -/* Can't support USB host is USB host is not enabled */ - -#ifndef CONFIG_USBHOST -# undef HAVE_USBHOST -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_boardinitialize - * - * Description: - * All STM32 architectures must provide the following entry point. This - * entry point is called early in the initialization -- after all memory - * has been configured and mapped but before any devices have been - * initialized. - * - ****************************************************************************/ - -void stm32_boardinitialize(void) -{ - /* Configure SPI chip selects if 1) SPI is not disabled, and 2) the weak - * function stm32_spidev_initialize() has been brought into the link. - */ - -#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI3) - if (stm32_spidev_initialize) - { - stm32_spidev_initialize(); - } -#endif - - /* Initialize USB is 1) USBDEV is selected, 2) the USB controller is not - * disabled, and 3) the weak function stm32_usbinitialize() has been - * brought into the build. - */ - -#if defined(CONFIG_USBDEV) && defined(CONFIG_STM32_USB) - if (stm32_usbinitialize) - { - stm32_usbinitialize(); - } -#endif - - /* Configure on-board LEDs if LED support has been selected. */ - -#ifdef CONFIG_ARCH_LEDS - board_autoled_initialize(); -#endif -} - -/**************************************************************************** - * Name: board_late_initialize - * - * Description: - * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional - * initialization call will be performed in the boot-up sequence to a - * function called board_late_initialize(). board_late_initialize() will - * be called immediately after up_initialize() is called and just before - * the initial application is started. This additional initialization - * phase may be used, for example, to initialize board-specific device - * drivers. - * - ****************************************************************************/ - -#ifdef CONFIG_BOARD_LATE_INITIALIZE -void board_late_initialize(void) -{ - int ret; - - /* Initialize and register the W25 FLASH file system. */ - -#ifdef HAVE_W25 - ret = stm32_w25initialize(CONFIG_NSH_W25MINOR); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: Failed to initialize W25 minor %d: %d\n", - CONFIG_NSH_W25MINOR, ret); - return; - } -#endif - - /* Initialize USB host operation. stm32_usbhost_initialize() starts a - * thread will monitor for USB connection and disconnection events. - */ - -#ifdef HAVE_USBHOST - ret = stm32_usbhost_initialize(); - if (ret != OK) - { - syslog(LOG_ERR, "ERROR: Failed to initialize USB host: %d\n", ret); - return; - } -#endif - -#ifdef CONFIG_ADC - /* Initialize ADC and register the ADC driver. */ - - ret = stm32_adc_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_adc_setup failed: %d\n", ret); - return; - } -#endif - - UNUSED(ret); -} -#endif diff --git a/boards/arm/stm32/cloudctrl/src/stm32_buttons.c b/boards/arm/stm32/cloudctrl/src/stm32_buttons.c deleted file mode 100644 index cc0e9ea8ea209..0000000000000 --- a/boards/arm/stm32/cloudctrl/src/stm32_buttons.c +++ /dev/null @@ -1,165 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/cloudctrl/src/stm32_buttons.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include -#include - -#include "cloudctrl.h" - -#ifdef CONFIG_ARCH_BUTTONS - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* Pin configuration for each cloudctrl button. This array is indexed by - * the BUTTON_* definitions in board.h - */ - -static const uint32_t g_buttons[NUM_BUTTONS] = -{ - GPIO_BTN_USERKEY, GPIO_BTN_TAMPER, GPIO_BTN_WAKEUP -}; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_button_initialize - * - * Description: - * board_button_initialize() must be called to initialize button resources. - * After that, board_buttons() may be called to collect the current state - * of all buttons or board_button_irq() may be called to register button - * interrupt handlers. - * - ****************************************************************************/ - -uint32_t board_button_initialize(void) -{ - int i; - - /* Configure the GPIO pins as inputs. NOTE that EXTI interrupts are - * configured for some pins but NOT used in this file - */ - - for (i = 0; i < NUM_BUTTONS; i++) - { - stm32_configgpio(g_buttons[i]); - } - - return NUM_BUTTONS; -} - -/**************************************************************************** - * Name: board_buttons - ****************************************************************************/ - -uint32_t board_buttons(void) -{ - uint32_t ret = 0; - int i; - - /* Check that state of each key */ - - for (i = 0; i < NUM_BUTTONS; i++) - { - /* A LOW value means that the key is pressed for most keys. - * The exception is the WAKEUP button. - */ - - bool released = stm32_gpioread(g_buttons[i]); - if (i == BUTTON_WAKEUP) - { - released = !released; - } - - /* Accumulate the set of depressed (not released) keys */ - - if (!released) - { - ret |= (1 << i); - } - } - - return ret; -} - -/**************************************************************************** - * Button support. - * - * Description: - * board_button_initialize() must be called to initialize button resources. - * After that, board_buttons() may be called to collect the current state - * of all buttons or board_button_irq() may be called to register button - * interrupt handlers. - * - * After board_button_initialize() has been called, board_buttons() may be - * called to collect the state of all buttons. board_buttons() returns an - * 32-bit bit set with each bit associated with a button. See the - * BUTTON_*_BIT and JOYSTICK_*_BIT definitions in board.h for the meaning - * of each bit. - * - * board_button_irq() may be called to register an interrupt handler that - * will be called when a button is depressed or released. The ID value is a - * button enumeration value that uniquely identifies a button resource. See - * the BUTTON_* and JOYSTICK_* definitions in board.h for the meaning of - * enumeration value. - * - ****************************************************************************/ - -#ifdef CONFIG_ARCH_IRQBUTTONS -int board_button_irq(int id, xcpt_t irqhandler, void *arg) -{ - int ret = -EINVAL; - - /* The following should be atomic */ - - if (id >= MIN_IRQBUTTON && id <= MAX_IRQBUTTON) - { - ret = stm32_gpiosetevent(g_buttons[id], true, true, true, irqhandler, - arg); - } - - return ret; -} -#endif -#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/stm32/cloudctrl/src/stm32_chipid.c b/boards/arm/stm32/cloudctrl/src/stm32_chipid.c deleted file mode 100644 index c2f6f75cf00a4..0000000000000 --- a/boards/arm/stm32/cloudctrl/src/stm32_chipid.c +++ /dev/null @@ -1,79 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/cloudctrl/src/stm32_chipid.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include - -#include "arm_internal.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -const char *stm32_getchipid(void) -{ - static char cpuid[12]; - int i; - - for (i = 0; i < 12; i++) - { - cpuid[i] = getreg8(0x1ffff7e8 + i); - } - - return cpuid; -} - -const char *stm32_getchipid_string(void) -{ - static char cpuid[27]; - int c; - int i; - - for (i = 0, c = 0; i < 12; i++) - { - snprintf(&cpuid[c], sizeof(cpuid) - c, - "%02X", getreg8(0x1ffff7e8 + 11 - i)); - c += 2; - if (i % 4 == 3) - { - cpuid[c++] = '-'; - } - } - - cpuid[26] = '\0'; - return cpuid; -} diff --git a/boards/arm/stm32/cloudctrl/src/stm32_relays.c b/boards/arm/stm32/cloudctrl/src/stm32_relays.c deleted file mode 100644 index 0007901ff80bb..0000000000000 --- a/boards/arm/stm32/cloudctrl/src/stm32_relays.c +++ /dev/null @@ -1,274 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/cloudctrl/src/stm32_relays.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include -#include - -#include "cloudctrl.h" - -#ifdef CONFIG_ARCH_RELAYS - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#define RELAYS_MIN_RESET_TIME 5 -#define RELAYS_RESET_MTIME 5 -#define RELAYS_POWER_MTIME 50 - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -static uint32_t g_relays_stat = 0; -static bool g_relays_init = false; - -static const uint16_t g_relays[NUM_RELAYS] = -{ - GPIO_RELAYS_R00 -#ifdef GPIO_RELAYS_R01 - , GPIO_RELAYS_R01 -#endif -#ifdef GPIO_RELAYS_R02 - , GPIO_RELAYS_R02 -#endif -#ifdef GPIO_RELAYS_R03 - , GPIO_RELAYS_R03 -#endif -#ifdef GPIO_RELAYS_R04 - , GPIO_RELAYS_R04 -#endif -#ifdef GPIO_RELAYS_R05 - , GPIO_RELAYS_R05 -#endif -#ifdef GPIO_RELAYS_R06 - , GPIO_RELAYS_R06 -#endif -#ifdef GPIO_RELAYS_R07 - , GPIO_RELAYS_R07 -#endif -#ifdef GPIO_RELAYS_R08 - , GPIO_RELAYS_R08 -#endif -#ifdef GPIO_RELAYS_R09 - , GPIO_RELAYS_R09 -#endif -#ifdef GPIO_RELAYS_R10 - , GPIO_RELAYS_R10 -#endif -#ifdef GPIO_RELAYS_R11 - , GPIO_RELAYS_R11 -#endif -#ifdef GPIO_RELAYS_R12 - , GPIO_RELAYS_R12 -#endif -#ifdef GPIO_RELAYS_R13 - , GPIO_RELAYS_R13 -#endif -#ifdef GPIO_RELAYS_R14 - , GPIO_RELAYS_R14 -#endif -#ifdef GPIO_RELAYS_R15 - , GPIO_RELAYS_R15 -#endif -#ifdef GPIO_RELAYS_R16 - , GPIO_RELAYS_R16 -#endif -#ifdef GPIO_RELAYS_R17 - , GPIO_RELAYS_R17 -#endif -#ifdef GPIO_RELAYS_R18 - , GPIO_RELAYS_R18 -#endif -#ifdef GPIO_RELAYS_R19 - , GPIO_RELAYS_R19 -#endif -#ifdef GPIO_RELAYS_R20 - , GPIO_RELAYS_R20 -#endif -#ifdef GPIO_RELAYS_R21 - , GPIO_RELAYS_R21 -#endif -#ifdef GPIO_RELAYS_R22 - , GPIO_RELAYS_R22 -#endif -#ifdef GPIO_RELAYS_R23 - , GPIO_RELAYS_R23 -#endif -#ifdef GPIO_RELAYS_R24 - , GPIO_RELAYS_R24 -#endif -#ifdef GPIO_RELAYS_R25 - , GPIO_RELAYS_R25 -#endif -#ifdef GPIO_RELAYS_R26 - , GPIO_RELAYS_R26 -#endif -#ifdef GPIO_RELAYS_R27 - , GPIO_RELAYS_R27 -#endif -#ifdef GPIO_RELAYS_R28 - , GPIO_RELAYS_R28 -#endif -#ifdef GPIO_RELAYS_R29 - , GPIO_RELAYS_R29 -#endif -#ifdef GPIO_RELAYS_R30 - , GPIO_RELAYS_R30 -#endif -#ifdef GPIO_RELAYS_R31 - , GPIO_RELAYS_R31 -#endif -}; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -void up_relaysinit(void) -{ - int i; - - if (g_relays_init) - { - return; - } - - /* Configure the GPIO pins as inputs. NOTE that EXTI interrupts are - * configured for some pins but NOT used in this file - */ - - for (i = 0; i < NUM_RELAYS; i++) - { - stm32_configgpio(g_relays[i]); - stm32_gpiowrite(g_relays[i], false); - } - - g_relays_init = true; -} - -void relays_setstat(int relays, bool stat) -{ - if ((unsigned)relays < NUM_RELAYS) - { - stm32_gpiowrite(g_relays[relays], stat); - if (!stat) - { - g_relays_stat &= ~(1 << relays); - } - else - { - g_relays_stat |= (1 << relays); - } - } -} - -bool relays_getstat(int relays) -{ - if ((unsigned)relays < NUM_RELAYS) - { - return (g_relays_stat & (1 << relays)) != 0; - } - - return false; -} - -void relays_setstats(uint32_t relays_stat) -{ - int i; - - for (i = 0; i < NUM_RELAYS; i++) - { - relays_setstat(i, (relays_stat & (1 << i)) != 0); - } -} - -uint32_t relays_getstats(void) -{ - return (uint32_t)g_relays_stat; -} - -void relays_onoff(int relays, uint32_t mdelay) -{ - if ((unsigned)relays < NUM_RELAYS) - { - if (mdelay > 0) - { - if (relays_getstat(relays)) - { - relays_setstat(relays, false); - nxsched_usleep(RELAYS_MIN_RESET_TIME * 1000 * 1000); - } - - relays_setstat(relays, true); - nxsched_usleep(mdelay * 100 * 1000); - relays_setstat(relays, false); - } - } -} - -void relays_onoffs(uint32_t relays_stat, uint32_t mdelay) -{ - int i; - - for (i = 0; i < NUM_RELAYS; i++) - { - relays_onoff(i, mdelay); - } -} - -void relays_resetmode(int relays) -{ - relays_onoff(relays, RELAYS_RESET_MTIME); -} - -void relays_powermode(int relays) -{ - relays_onoff(relays, RELAYS_POWER_MTIME); -} - -void relays_resetmodes(uint32_t relays_stat) -{ - relays_onoffs(relays_stat, RELAYS_RESET_MTIME); -} - -void relays_powermodes(uint32_t relays_stat) -{ - relays_onoffs(relays_stat, RELAYS_POWER_MTIME); -} - -#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/stm32/cloudctrl/src/stm32_spi.c b/boards/arm/stm32/cloudctrl/src/stm32_spi.c deleted file mode 100644 index 9e5e2a3d88c23..0000000000000 --- a/boards/arm/stm32/cloudctrl/src/stm32_spi.c +++ /dev/null @@ -1,139 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/cloudctrl/src/stm32_spi.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include "arm_internal.h" -#include "chip.h" -#include "stm32.h" -#include "cloudctrl.h" - -#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI3) - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_spidev_initialize - * - * Description: - * Called to configure SPI chip select GPIO pins for the cloudctrl board. - * - ****************************************************************************/ - -void weak_function stm32_spidev_initialize(void) -{ - /* NOTE: Clocking for SPI1 and/or SPI3 was already provided in stm32_rcc.c. - * Configurations of SPI pins is performed in stm32_spi.c. - * Here, we only initialize chip select pins unique to the board - * architecture. - */ - - /* SPI1 connects to the SD CARD and to the SPI FLASH */ - -#ifdef CONFIG_STM32_SPI1 - stm32_configgpio(GPIO_FLASH_CS); /* FLASH chip select */ -#endif - - /* SPI3 connects to TFT LCD module and the RF24L01 2.4G wireless module */ - -#ifdef CONFIG_STM32_SPI3 - -#endif -} - -/**************************************************************************** - * Name: stm32_spi1/2/3select and stm32_spi1/2/3status - * - * Description: - * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status - * must be provided by board-specific logic. They are implementations of - * the select and status methods of the SPI interface defined by struct - * spi_ops_s (see include/nuttx/spi/spi.h). All other methods (including - * stm32_spibus_initialize()) are provided by common STM32 logic. - * To use this common SPI logic on your board: - * - * 1. Provide logic in stm32_boardinitialize() to configure SPI chip - * select pins. - * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() functions - * in your board-specific logic. These functions will perform chip - * selection and status operations using GPIOs in the way your board is - * configured. - * 3. Add a calls to stm32_spibus_initialize() in your low level - * application initialization logic - * 4. The handle returned by stm32_spibus_initialize() may then be used to - * bind the SPI driver to higher level logic (e.g., calling - * mmcsd_spislotinitialize(), for example, will bind the SPI driver to - * the SPI MMC/SD driver). - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_SPI1 -void stm32_spi1select(struct spi_dev_s *dev, - uint32_t devid, bool selected) -{ - spiinfo("devid: %d CS: %s\n", - (int)devid, selected ? "assert" : "de-assert"); - - /* SPI1 connects to the SD CARD and to the SPI FLASH */ - - if (devid == SPIDEV_FLASH(0)) - { - /* Set the GPIO low to select and high to de-select */ - - stm32_gpiowrite(GPIO_FLASH_CS, !selected); - } -} - -uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) -{ - return SPI_STATUS_PRESENT; -} -#endif - -#ifdef CONFIG_STM32_SPI3 -void stm32_spi3select(struct spi_dev_s *dev, - uint32_t devid, bool selected) -{ - spiinfo("devid: %d CS: %s\n", - (int)devid, selected ? "assert" : "de-assert"); -} - -uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid) -{ - return 0; -} -#endif - -#endif /* CONFIG_STM32_SPI1 || CONFIG_STM32_SPI3 */ diff --git a/boards/arm/stm32/cloudctrl/src/stm32_usb.c b/boards/arm/stm32/cloudctrl/src/stm32_usb.c deleted file mode 100644 index ae70668bb50f8..0000000000000 --- a/boards/arm/stm32/cloudctrl/src/stm32_usb.c +++ /dev/null @@ -1,304 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/cloudctrl/src/stm32_usb.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -#include "arm_internal.h" -#include "stm32.h" -#include "stm32_otgfs.h" -#include "cloudctrl.h" - -#ifdef CONFIG_STM32_OTGFS - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#if defined(CONFIG_USBDEV) || defined(CONFIG_USBHOST) -# define HAVE_USB 1 -#else -# warning "CONFIG_STM32_OTGFS is enabled but neither CONFIG_USBDEV nor CONFIG_USBHOST" -# undef HAVE_USB -#endif - -#ifndef CONFIG_USBHOST_DEFPRIO -# define CONFIG_USBHOST_DEFPRIO 50 -#endif - -#ifndef CONFIG_USBHOST_STACKSIZE -# ifdef CONFIG_USBHOST_HUB -# define CONFIG_USBHOST_STACKSIZE 1536 -# else -# define CONFIG_USBHOST_STACKSIZE 1024 -# endif -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -#ifdef CONFIG_USBHOST -static struct usbhost_connection_s *g_usbconn; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: usbhost_waiter - * - * Description: - * Wait for USB devices to be connected. - * - ****************************************************************************/ - -#ifdef CONFIG_USBHOST -static int usbhost_waiter(int argc, char *argv[]) -{ - struct usbhost_hubport_s *hport; - - uinfo("Running\n"); - for (; ; ) - { - /* Wait for the device to change state */ - - DEBUGVERIFY(CONN_WAIT(g_usbconn, &hport)); - uinfo("%s\n", hport->connected ? "connected" : "disconnected"); - - /* Did we just become connected? */ - - if (hport->connected) - { - /* Yes.. enumerate the newly connected device */ - - CONN_ENUMERATE(g_usbconn, hport); - } - } - - /* Keep the compiler from complaining */ - - return 0; -} -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_usbinitialize - * - * Description: - * Called from stm32_usbinitialize very early in initialization to setup - * USB-related GPIO pins for the STM3240G-EVAL board. - * - ****************************************************************************/ - -void stm32_usbinitialize(void) -{ - /* The OTG FS has an internal soft pull-up. - * No GPIO configuration is required - */ - - /* Configure the OTG FS VBUS sensing GPIO, - * Power On, and Overcurrent GPIOs - */ - -#ifdef CONFIG_STM32_OTGFS - stm32_configgpio(GPIO_OTGFS_VBUS); - stm32_configgpio(GPIO_OTGFS_PWRON); - stm32_configgpio(GPIO_OTGFS_OVER); -#endif -} - -/**************************************************************************** - * Name: stm32_usbhost_initialize - * - * Description: - * Called at application startup time to initialize the USB host - * functionality. - * This function will start a thread that will monitor for device - * connection/disconnection events. - * - ****************************************************************************/ - -#ifdef CONFIG_USBHOST -int stm32_usbhost_initialize(void) -{ - int ret; - - /* First, register all of the class drivers needed to support the drivers - * that we care about: - */ - - uinfo("Register class drivers\n"); - -#ifdef CONFIG_USBHOST_MSC - /* Register the USB mass storage class */ - - ret = usbhost_msc_initialize(); - if (ret != OK) - { - uerr("ERROR: Failed to register the mass storage class\n"); - } -#endif - -#ifdef CONFIG_USBHOST_CDCACM - /* Register the CDC/ACM serial class */ - - ret = usbhost_cdcacm_initialize(); - if (ret != OK) - { - uerr("ERROR: Failed to register the CDC/ACM serial class\n"); - } -#endif - - /* Then get an instance of the USB host interface */ - - uinfo("Initialize USB host\n"); - g_usbconn = stm32_otgfshost_initialize(0); - if (g_usbconn) - { - /* Start a thread to handle device connection. */ - - uinfo("Start usbhost_waiter\n"); - - ret = kthread_create("usbhost", CONFIG_USBHOST_DEFPRIO, - CONFIG_USBHOST_STACKSIZE, - usbhost_waiter, NULL); - return ret < 0 ? -ENOEXEC : OK; - } - - return -ENODEV; -} -#endif - -/**************************************************************************** - * Name: stm32_usbhost_vbusdrive - * - * Description: - * Enable/disable driving of VBUS 5V output. This function must be - * provided be each platform that implements the STM32 OTG FS host - * interface - * - * "On-chip 5 V VBUS generation is not supported. For this reason, a - * charge pump or, if 5 V are available on the application board, a - * basic power switch, must be added externally to drive the 5 V VBUS - * line. The external charge pump can be driven by any GPIO output. - * When the application decides to power on VBUS using the chosen GPIO, - * it must also set the port power bit in the host port control and - * status register (PPWR bit in OTG_FS_HPRT). - * - * "The application uses this field to control power to this port, - * and the core clears this bit on an overcurrent condition." - * - * Input Parameters: - * iface - For future growth to handle multiple USB host interface. - * Should be zero. - * enable - true: enable VBUS power; false: disable VBUS power - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef CONFIG_USBHOST -void stm32_usbhost_vbusdrive(int iface, bool enable) -{ - DEBUGASSERT(iface == 0); - - if (enable) - { - /* Enable the Power Switch by driving the enable pin low */ - - stm32_gpiowrite(GPIO_OTGFS_PWRON, false); - } - else - { - /* Disable the Power Switch by driving the enable pin high */ - - stm32_gpiowrite(GPIO_OTGFS_PWRON, true); - } -} -#endif - -/**************************************************************************** - * Name: stm32_setup_overcurrent - * - * Description: - * Setup to receive an interrupt-level callback if an overcurrent - * condition is detected. - * - * Input Parameters: - * handler - New overcurrent interrupt handler - * arg - The argument provided for the interrupt handler - * - * Returned Value: - * Zero (OK) is returned on success. Otherwise, a negated errno value - * is returned to indicate the nature of the failure. - * - ****************************************************************************/ - -#ifdef CONFIG_USBHOST -int stm32_setup_overcurrent(xcpt_t handler, void *arg) -{ - return -ENOSYS; -} -#endif - -/**************************************************************************** - * Name: stm32_usbsuspend - * - * Description: - * Board logic must provide the stm32_usbsuspend logic if the USBDEV - * driver is used. This function is called whenever the USB enters or - * leaves suspend mode. This is an opportunity for the board logic to - * shutdown clocks, power, etc. while the USB is suspended. - * - ****************************************************************************/ - -#ifdef CONFIG_USBDEV -void stm32_usbsuspend(struct usbdev_s *dev, bool resume) -{ - uinfo("resume: %d\n", resume); -} -#endif - -#endif /* CONFIG_STM32_OTGFS */ diff --git a/boards/arm/stm32/cloudctrl/src/stm32_usbmsc.c b/boards/arm/stm32/cloudctrl/src/stm32_usbmsc.c deleted file mode 100644 index ab372b7c35533..0000000000000 --- a/boards/arm/stm32/cloudctrl/src/stm32_usbmsc.c +++ /dev/null @@ -1,71 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/cloudctrl/src/stm32_usbmsc.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include - -#include "stm32.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -#ifndef CONFIG_SYSTEM_USBMSC_DEVMINOR1 -# define CONFIG_SYSTEM_USBMSC_DEVMINOR1 0 -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_usbmsc_initialize - * - * Description: - * Perform architecture specific initialization of the USB MSC device. - * - ****************************************************************************/ - -int board_usbmsc_initialize(int port) -{ - /* If system/usbmsc is built as an NSH command, then SD slot should - * already have been initialized. - * In this case, there is nothing further to be done here. - */ - -#ifndef CONFIG_NSH_BUILTIN_APPS - return stm32_sdinitialize(CONFIG_SYSTEM_USBMSC_DEVMINOR1); -#else - return OK; -#endif -} diff --git a/boards/arm/stm32/cloudctrl/src/stm32_userleds.c b/boards/arm/stm32/cloudctrl/src/stm32_userleds.c deleted file mode 100644 index d9f75c9aa286b..0000000000000 --- a/boards/arm/stm32/cloudctrl/src/stm32_userleds.c +++ /dev/null @@ -1,96 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/cloudctrl/src/stm32_userleds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32.h" -#include "cloudctrl.h" - -#ifndef CONFIG_ARCH_LEDS - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* This array maps an LED number to GPIO pin configuration */ - -static uint32_t g_ledcfg[BOARD_NLEDS] = -{ - GPIO_LED1, GPIO_LED2, GPIO_LED3, GPIO_LED4 -}; - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_userled_initialize - ****************************************************************************/ - -uint32_t board_userled_initialize(void) -{ - /* Configure LED1-3 GPIOs for output */ - - stm32_configgpio(GPIO_LED1); - stm32_configgpio(GPIO_LED2); - stm32_configgpio(GPIO_LED3); - stm32_configgpio(GPIO_LED4); - return BOARD_NLEDS; -} - -/**************************************************************************** - * Name: board_userled - ****************************************************************************/ - -void board_userled(int led, bool ledon) -{ - if ((unsigned)led < BOARD_NLEDS) - { - stm32_gpiowrite(g_ledcfg[led], ledon); - } -} - -/**************************************************************************** - * Name: board_userled_all - ****************************************************************************/ - -void board_userled_all(uint32_t ledset) -{ - stm32_gpiowrite(GPIO_LED1, (ledset & BOARD_LED1_BIT) == 0); - stm32_gpiowrite(GPIO_LED2, (ledset & BOARD_LED2_BIT) == 0); - stm32_gpiowrite(GPIO_LED3, (ledset & BOARD_LED3_BIT) == 0); - stm32_gpiowrite(GPIO_LED4, (ledset & BOARD_LED4_BIT) == 0); -} - -#endif /* !CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/cloudctrl/src/stm32_w25.c b/boards/arm/stm32/cloudctrl/src/stm32_w25.c deleted file mode 100644 index bcd7be927bc9b..0000000000000 --- a/boards/arm/stm32/cloudctrl/src/stm32_w25.c +++ /dev/null @@ -1,144 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/cloudctrl/src/stm32_w25.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include - -#ifdef CONFIG_STM32_SPI1 -# include -# include -# include -# include -#endif - -#include "stm32_spi.h" -#include "cloudctrl.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -/* Can't support the W25 device if it SPI1 or W25 support is not enabled */ - -#define HAVE_W25 1 -#if !defined(CONFIG_STM32_SPI1) || !defined(CONFIG_MTD_W25) -# undef HAVE_W25 -#endif - -/* Can't support W25 features if mountpoints are disabled */ - -#if defined(CONFIG_DISABLE_MOUNTPOINT) -# undef HAVE_W25 -#endif - -/* Can't support both FAT and NXFFS */ - -#if defined(CONFIG_FS_FAT) && defined(CONFIG_FS_NXFFS) -# warning "Can't support both FAT and NXFFS -- using FAT" -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_w25initialize - * - * Description: - * Initialize and register the W25 FLASH file system. - * - ****************************************************************************/ - -int stm32_w25initialize(int minor) -{ -#ifdef HAVE_W25 - struct spi_dev_s *spi; - struct mtd_dev_s *mtd; -#ifdef CONFIG_FS_NXFFS - char devname[12]; -#endif - int ret; - - /* Get the SPI port */ - - spi = stm32_spibus_initialize(1); - if (!spi) - { - ferr("ERROR: Failed to initialize SPI port 2\n"); - return -ENODEV; - } - - /* Now bind the SPI interface to the W25 SPI FLASH driver */ - - mtd = w25_initialize(spi); - if (!mtd) - { - ferr("ERROR: Failed to bind SPI port 2 to the SST 25 FLASH driver\n"); - return -ENODEV; - } - -#ifndef CONFIG_FS_NXFFS - /* Register the MTD driver */ - - char path[32]; - snprintf(path, sizeof(path), "/dev/mtdblock%d", minor); - ret = register_mtddriver(path, mtd, 0755, NULL); - if (ret < 0) - { - ferr("ERROR: Failed to register the MTD driver %s, ret %d\n", - path, ret); - return ret; - } -#else - /* Initialize to provide NXFFS on the MTD interface */ - - ret = nxffs_initialize(mtd); - if (ret < 0) - { - ferr("ERROR: NXFFS initialization failed: %d\n", -ret); - return ret; - } - - /* Mount the file system at /mnt/w25 */ - - snprintf(devname, sizeof(devname), "/mnt/w25%c", 'a' + minor); - ret = nx_mount(NULL, devname, "nxffs", 0, NULL); - if (ret < 0) - { - ferr("ERROR: Failed to mount the NXFFS volume: %d\n", ret); - return ret; - } -#endif -#endif - - return OK; -} diff --git a/boards/arm/stm32/common/CMakeLists.txt b/boards/arm/stm32/common/CMakeLists.txt deleted file mode 100644 index 48a2ca9e109b2..0000000000000 --- a/boards/arm/stm32/common/CMakeLists.txt +++ /dev/null @@ -1,24 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/common/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) -target_include_directories(board PRIVATE include) diff --git a/boards/arm/stm32/common/Kconfig b/boards/arm/stm32/common/Kconfig deleted file mode 100644 index 3e611724880f7..0000000000000 --- a/boards/arm/stm32/common/Kconfig +++ /dev/null @@ -1,71 +0,0 @@ -# -# For a description of the syntax of this configuration file, -# see the file kconfig-language.txt in the NuttX tools repository. -# - -if STM32_FOC - -menuconfig BOARD_STM32_IHM07M1 - bool "X-NUCLEO-IHM07M1 board support" - default n - ---help--- - Board based on the L6230 DMOS driver. - -if BOARD_STM32_IHM07M1 - -config BOARD_STM32_IHM07M1_VBUS - bool "X-NUCLEO-IHM07M1 board VBUS sense" - default n - -config BOARD_STM32_IHM07M1_POT - bool "X-NUCLEO-IHM07M1 board POT support" - default n - -endif # BOARD_STM32_IHM07M1 - -menuconfig BOARD_STM32_IHM08M1 - bool "X-NUCLEO-IHM08M1 board support" - default n - select STM32_FOC_HAS_PWM_COMPLEMENTARY - ---help--- - Board based on the discrete L6398 gate drivers and STL220N6F7 POWER MOSFETs. - -if BOARD_STM32_IHM08M1 - -config BOARD_STM32_IHM08M1_VBUS - bool "X-NUCLEO-IHM08M1 board VBUS sense" - default n - -config BOARD_STM32_IHM08M1_POT - bool "X-NUCLEO-IHM08M1 board POT support" - default n - -endif # BOARD_STM32_IHM08M1 - -menuconfig BOARD_STM32_IHM16M1 - bool "X-NUCLEO-IHM16M1 board support" - default n - ---help--- - Board based on the STSPIN830 three-phase brushless motor driver. - -if BOARD_STM32_IHM16M1 - -config BOARD_STM32_IHM16M1_VBUS - bool "X-NUCLEO-IHM16M1 board VBUS sense" - default n - -config BOARD_STM32_IHM16M1_POT - bool "X-NUCLEO-IHM16M1 board POT support" - default n - -endif # BOARD_STM32_IHM16M1 - -endif # STM32_FOC - -if SENSORS_HALL3PHASE - -config BOARD_STM32_HALL3PHASE_SAMPLES - int "3-phase Hall effect sensor number of samples" - default 10 - -endif # SENSORS_HALL3PHASE diff --git a/boards/arm/stm32/common/Makefile b/boards/arm/stm32/common/Makefile deleted file mode 100644 index c6b78fa6a476c..0000000000000 --- a/boards/arm/stm32/common/Makefile +++ /dev/null @@ -1,35 +0,0 @@ -############################################################################# -# boards/arm/stm32/common/Makefile -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################# - -include $(TOPDIR)/Make.defs - -include board/Make.defs -include src/Make.defs - -DEPPATH += --dep-path board -DEPPATH += --dep-path src - -include $(TOPDIR)/boards/Board.mk - -ARCHSRCDIR = $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src -BOARDDIR = $(ARCHSRCDIR)$(DELIM)board -CFLAGS += ${INCDIR_PREFIX}$(BOARDDIR)$(DELIM)include diff --git a/boards/arm/stm32/common/include/board_qencoder.h b/boards/arm/stm32/common/include/board_qencoder.h deleted file mode 100644 index 5d6dbe191786c..0000000000000 --- a/boards/arm/stm32/common/include/board_qencoder.h +++ /dev/null @@ -1,75 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/common/include/board_qencoder.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __BOARDS_ARM_STM32_COMMON_INCLUDE_BOARD_QENCODER_H -#define __BOARDS_ARM_STM32_COMMON_INCLUDE_BOARD_QENCODER_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -#ifdef __cplusplus -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Inline Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: board_qencoder_initialize - * - * Description: - * Initialize the quadrature encoder driver for the given timer - * - ****************************************************************************/ - -int board_qencoder_initialize(int devno, int timerno); - -#undef EXTERN -#ifdef __cplusplus -} -#endif - -#endif /* __BOARDS_ARM_STM32_COMMON_INCLUDE_BOARD_QENCODER_H */ diff --git a/boards/arm/stm32/common/include/stm32_bh1750.h b/boards/arm/stm32/common/include/stm32_bh1750.h deleted file mode 100644 index b9de5a874ddb9..0000000000000 --- a/boards/arm/stm32/common/include/stm32_bh1750.h +++ /dev/null @@ -1,82 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/common/include/stm32_bh1750.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_BH1750_H -#define __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_BH1750_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -#ifdef __cplusplus -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Inline Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: board_bh1750_initialize - * - * Description: - * Initialize and register the BH1750FVI Ambient Light driver. - * - * Input Parameters: - * devno - The device number, used to build the device path as /dev/lightN - * busno - The I2C bus number - * - * Returned Value: - * Zero (OK) on success; a negated errno value on failure. - * - ****************************************************************************/ - -int board_bh1750_initialize(int devno, int busno); - -#undef EXTERN -#ifdef __cplusplus -} -#endif - -#endif /* __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_BH1750_H */ diff --git a/boards/arm/stm32/common/include/stm32_ssd1306.h b/boards/arm/stm32/common/include/stm32_ssd1306.h deleted file mode 100644 index d5e2d5279968b..0000000000000 --- a/boards/arm/stm32/common/include/stm32_ssd1306.h +++ /dev/null @@ -1,82 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/common/include/stm32_ssd1306.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_SSD1306_H -#define __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_SSD1306_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -#ifdef __cplusplus -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: board_ssd1306_initialize - * - * Description: - * Initialize and register the device - * - * Input Parameters: - * busno - The I2C or SPI bus number - * - * Returned Value: - * Zero (OK) on success; a negated errno value on failure. - * - ****************************************************************************/ - -int board_ssd1306_initialize(int busno); - -/**************************************************************************** - * Name: board_ssd1306_getdev - * - * Description: - * Get the SSD1306 device driver instance - * - * Returned Value: - * Pointer to the instance - * - ****************************************************************************/ - -struct lcd_dev_s *board_ssd1306_getdev(void); - -#undef EXTERN -#ifdef __cplusplus -} -#endif - -#endif /* __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_SSD1306_H */ diff --git a/boards/arm/stm32/common/src/CMakeLists.txt b/boards/arm/stm32/common/src/CMakeLists.txt deleted file mode 100644 index c7d9426af29e7..0000000000000 --- a/boards/arm/stm32/common/src/CMakeLists.txt +++ /dev/null @@ -1,179 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/common/src/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -set(SRCS) - -if(CONFIG_SENSORS_BMP180) - list(APPEND SRCS stm32_bmp180.c) -endif() - -if(CONFIG_SENSORS_BMP280) - list(APPEND SRCS stm32_bmp280.c) -endif() - -if(CONFIG_LEDS_APA102) - list(APPEND SRCS stm32_apa102.c) -endif() - -if(CONFIG_WS2812) - list(APPEND SRCS stm32_ws2812.c) -endif() - -if(CONFIG_SENSORS_MAX6675) - list(APPEND SRCS stm32_max6675.c) -endif() - -if(CONFIG_SENSORS_VEML6070) - list(APPEND SRCS stm32_veml6070.c) -endif() - -if(CONFIG_INPUT_NUNCHUCK) - list(APPEND SRCS stm32_nunchuck.c) -endif() - -if(CONFIG_AUDIO_TONE) - list(APPEND SRCS stm32_tone.c) -endif() - -if(CONFIG_LCD_BACKPACK) - list(APPEND SRCS stm32_lcd_backpack.c) -endif() - -if(CONFIG_LCD_SSD1306) - list(APPEND SRCS stm32_ssd1306.c) -endif() - -if(CONFIG_RTC_DS1307) - list(APPEND SRCS stm32_ds1307.c) -endif() - -if(CONFIG_SENSORS_LM75) - list(APPEND SRCS stm32_lm75.c) -endif() - -if(CONFIG_WL_NRF24L01) - list(APPEND SRCS stm32_nrf24l01.c) -endif() - -if(CONFIG_SENSORS_HCSR04) - list(APPEND SRCS stm32_hcsr04.c) -endif() - -if(CONFIG_SENSORS_APDS9960) - list(APPEND SRCS stm32_apds9960.c) -endif() - -if(CONFIG_SENSORS_MT6816) - list(APPEND SRCS stm32_mt6816.c) -endif() - -if(CONFIG_SENSORS_ZEROCROSS) - list(APPEND SRCS stm32_zerocross.c) -endif() - -if(CONFIG_SENSORS_QENCODER) - if(CONFIG_STM32_QE) - list(APPEND SRCS stm32_qencoder.c) - endif() -endif() - -if(CONFIG_SENSORS_INA219) - list(APPEND SRCS stm32_ina219.c) -endif() - -if(CONFIG_SENSORS_L3GD20) - list(APPEND SRCS stm32_l3gd20.c) -endif() - -if(CONFIG_SENSORS_MPL115A) - list(APPEND SRCS stm32_mpl115a.c) -endif() - -if(CONFIG_SENSORS_DHTXX) - list(APPEND SRCS stm32_dhtxx.c) -endif() - -if(CONFIG_SENSORS_XEN1210) - list(APPEND SRCS stm32_xen1210.c) -endif() - -if(CONFIG_SENSORS_BH1750FVI) - list(APPEND SRCS stm32_bh1750.c) -endif() - -if(CONFIG_SENSORS_MLX90614) - list(APPEND SRCS stm32_mlx90614.c) -endif() - -if(CONFIG_SENSORS_MAX31855) - list(APPEND SRCS stm32_max31855.c) -endif() - -if(CONFIG_LCD_MAX7219) - list(APPEND SRCS stm32_max7219_matrix.c) -endif() - -if(CONFIG_CL_MFRC522) - list(APPEND SRCS stm32_mfrc522.c) -endif() - -if(CONFIG_SENSORS_AMG88XX) - list(APPEND SRCS stm32_amg88xx.c) -endif() - -if(CONFIG_LIS3DSH) - list(APPEND SRCS stm32_lis3dsh.c) -endif() - -if(CONFIG_BOARD_STM32_IHM07M1) - list(APPEND SRCS stm32_ihm07m1.c) -endif() - -if(CONFIG_BOARD_STM32_IHM08M1) - list(APPEND SRCS stm32_ihm08m1.c) -endif() - -if(CONFIG_BOARD_STM32_IHM16M1) - list(APPEND SRCS stm32_ihm16m1.c) -endif() - -if(CONFIG_STEPPER_DRV8825) - list(APPEND SRCS stm32_drv8825.c) -endif() - -if(CONFIG_INPUT_SBUTTON) - list(APPEND SRCS stm32_sbutton.c) -endif() - -if(CONFIG_INPUT_KMATRIX) - list(APPEND SRCS stm32_kmatrix_gpio.c) -endif() - -if(CONFIG_INPUT_KMATRIX_I2C) - list(APPEND SRCS stm32_kmatrix_i2c.c) -endif() - -if(CONFIG_INPUT_MPR121_KEYPAD) - list(APPEND SRCS stm32_mpr121.c) -endif() - -target_sources(board PRIVATE ${SRCS}) diff --git a/boards/arm/stm32/common/src/Make.defs b/boards/arm/stm32/common/src/Make.defs deleted file mode 100644 index 5b1f8556d767f..0000000000000 --- a/boards/arm/stm32/common/src/Make.defs +++ /dev/null @@ -1,191 +0,0 @@ -############################################################################# -# boards/arm/stm32/common/src/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################# - -ifeq ($(CONFIG_ARCH_BOARD_COMMON),y) - -ifeq ($(CONFIG_SENSORS_BMP180),y) - CSRCS += stm32_bmp180.c -endif - -ifeq ($(CONFIG_SENSORS_BMP280),y) - CSRCS += stm32_bmp280.c -endif - -ifeq ($(CONFIG_SENSORS_MS56XX),y) - CSRCS += stm32_ms5611.c -endif - -ifeq ($(CONFIG_LEDS_APA102),y) - CSRCS += stm32_apa102.c -endif - -ifeq ($(CONFIG_WS2812),y) - CSRCS += stm32_ws2812.c -endif - -ifeq ($(CONFIG_SENSORS_MAX6675),y) - CSRCS += stm32_max6675.c -endif - -ifeq ($(CONFIG_SENSORS_VEML6070),y) - CSRCS += stm32_veml6070.c -endif - -ifeq ($(CONFIG_INPUT_NUNCHUCK),y) -CSRCS += stm32_nunchuck.c -endif - -ifeq ($(CONFIG_AUDIO_TONE),y) - CSRCS += stm32_tone.c -endif - -ifeq ($(CONFIG_LCD_BACKPACK),y) - CSRCS += stm32_lcd_backpack.c -endif - -ifeq ($(CONFIG_LCD_SSD1306),y) - CSRCS += stm32_ssd1306.c -endif - -ifeq ($(CONFIG_RTC_DS1307),y) - CSRCS += stm32_ds1307.c -endif - -ifeq ($(CONFIG_SENSORS_LM75),y) - CSRCS += stm32_lm75.c -endif - -ifeq ($(CONFIG_WL_NRF24L01),y) - CSRCS += stm32_nrf24l01.c -endif - -ifeq ($(CONFIG_SENSORS_HCSR04),y) - CSRCS += stm32_hcsr04.c -endif - -ifeq ($(CONFIG_SENSORS_APDS9960),y) - CSRCS += stm32_apds9960.c -endif - -ifeq ($(CONFIG_SENSORS_MT6816),y) - CSRCS += stm32_mt6816.c -endif - -ifeq ($(CONFIG_INPUT_MPR121_KEYPAD),y) - CSRCS += stm32_mpr121.c -endif - -ifeq ($(CONFIG_SENSORS_ZEROCROSS),y) - CSRCS += stm32_zerocross.c -endif - -ifeq ($(CONFIG_SENSORS_QENCODER),y) - ifeq ($(CONFIG_STM32_QE),y) - CSRCS += stm32_qencoder.c - endif -endif - -ifeq ($(CONFIG_SENSORS_HALL3PHASE),y) - CSRCS += board_hall3ph.c -endif - -ifeq ($(CONFIG_SENSORS_INA219),y) - CSRCS += stm32_ina219.c -endif - -ifeq ($(CONFIG_SENSORS_L3GD20),y) - CSRCS += stm32_l3gd20.c -endif - -ifeq ($(CONFIG_SENSORS_MPL115A),y) - CSRCS += stm32_mpl115a.c -endif - -ifeq ($(CONFIG_SENSORS_DHTXX),y) - CSRCS += stm32_dhtxx.c -endif - -ifeq ($(CONFIG_SENSORS_XEN1210),y) - CSRCS += stm32_xen1210.c -endif - -ifeq ($(CONFIG_SENSORS_BH1750FVI),y) - CSRCS += stm32_bh1750.c -endif - -ifeq ($(CONFIG_SENSORS_MLX90614),y) - CSRCS += stm32_mlx90614.c -endif - -ifeq ($(CONFIG_SENSORS_MAX31855),y) - CSRCS += stm32_max31855.c -endif - -ifeq ($(CONFIG_LCD_MAX7219),y) - CSRCS += stm32_max7219_matrix.c -endif - -ifeq ($(CONFIG_CL_MFRC522),y) - CSRCS += stm32_mfrc522.c -endif - -ifeq ($(CONFIG_SENSORS_AMG88XX),y) - CSRCS+= stm32_amg88xx.c -endif - -ifeq ($(CONFIG_LIS3DSH),y) - CSRCS += stm32_lis3dsh.c -endif - -ifeq ($(CONFIG_BOARD_STM32_IHM07M1),y) - CSRCS += stm32_ihm07m1.c -endif - -ifeq ($(CONFIG_BOARD_STM32_IHM08M1),y) - CSRCS += stm32_ihm08m1.c -endif - -ifeq ($(CONFIG_BOARD_STM32_IHM16M1),y) - CSRCS += stm32_ihm16m1.c -endif - -ifeq ($(CONFIG_STEPPER_DRV8825),y) - CSRCS += stm32_drv8825.c -endif - -ifeq ($(CONFIG_INPUT_SBUTTON),y) - CSRCS += stm32_sbutton.c -endif - -ifeq ($(CONFIG_INPUT_KMATRIX),y) - CSRCS += stm32_kmatrix_gpio.c -endif - -ifeq ($(CONFIG_INPUT_KMATRIX_I2C),y) - CSRCS += stm32_kmatrix_i2c.c -endif - -DEPPATH += --dep-path src -VPATH += :src -CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)src - -endif diff --git a/boards/arm/stm32/common/src/stm32_apa102.c b/boards/arm/stm32/common/src/stm32_apa102.c deleted file mode 100644 index 5b19432385c66..0000000000000 --- a/boards/arm/stm32/common/src/stm32_apa102.c +++ /dev/null @@ -1,110 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/common/src/stm32_apa102.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include "stm32.h" -#include "stm32_spi.h" - -#ifdef CONFIG_LEDS_APA102 - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_apa102_initialize - * - * Description: - * Initialize and register the APA102 LED Strip driver. - * - * Input Parameters: - * devno - The device number, used to build the device path as /dev/leddrvN - * spino - SPI port number - * - * Returned Value: - * Zero (OK) on success; a negated errno value on failure. - * - ****************************************************************************/ - -int board_apa102_initialize(int devno, int spino) -{ - struct spi_dev_s *spi; - char devpath[13]; - int ret; - - spi = stm32_spibus_initialize(spino); - if (spi == NULL) - { - return -ENODEV; - } - - /* Register the APA102 Driver at the specified location. */ - - snprintf(devpath, sizeof(devpath), "/dev/leddrv%d", devno); - ret = apa102_register(devpath, spi); - if (ret < 0) - { - lederr("ERROR: apa102_register(%s) failed: %d\n", - devpath, ret); - return ret; - } - - return OK; -} - -#endif diff --git a/boards/arm/stm32/common/src/stm32_bh1750.c b/boards/arm/stm32/common/src/stm32_bh1750.c deleted file mode 100644 index 4a21eee85c3f6..0000000000000 --- a/boards/arm/stm32/common/src/stm32_bh1750.c +++ /dev/null @@ -1,90 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/common/src/stm32_bh1750.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include -#include - -#include "stm32.h" -#include "stm32_i2c.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_bh1750initialize - * - * Description: - * Initialize and register the BH1750FVI Ambient Light driver. - * - * Input Parameters: - * devno - The device number, used to build the device path as /dev/lightN - * busno - The I2C bus number - * - * Returned Value: - * Zero (OK) on success; a negated errno value on failure. - * - ****************************************************************************/ - -int board_bh1750_initialize(int devno, int busno) -{ - struct i2c_master_s *i2c; - char devpath[12]; - int ret; - - sninfo("Initializing BH1750FVI!\n"); - - /* Initialize I2C */ - - i2c = stm32_i2cbus_initialize(busno); - if (!i2c) - { - return -ENODEV; - } - - /* Then register the ambient light sensor */ - - snprintf(devpath, sizeof(devpath), "/dev/light%d", devno); - ret = bh1750fvi_register(devpath, i2c, BH1750FVI_I2C_ADDR); - if (ret < 0) - { - snerr("ERROR: Error registering BH1750FVI\n"); - } - - return ret; -} - diff --git a/boards/arm/stm32/common/src/stm32_mfrc522.c b/boards/arm/stm32/common/src/stm32_mfrc522.c deleted file mode 100644 index fc0d5bdf40e0b..0000000000000 --- a/boards/arm/stm32/common/src/stm32_mfrc522.c +++ /dev/null @@ -1,86 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/common/src/stm32_mfrc522.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include -#include - -#include "stm32.h" -#include "stm32_spi.h" - -#if defined(CONFIG_SPI) && defined(CONFIG_STM32_SPI1) && defined(CONFIG_CL_MFRC522) - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#define MFRC522_SPI_PORTNO 1 /* On SPI1 */ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_mfrc522initialize - * - * Description: - * Initialize and register the MFRC522 RFID driver. - * - * Input Parameters: - * devpath - The full path to the driver to register. E.g., "/dev/rfid0" - * - * Returned Value: - * Zero (OK) on success; a negated errno value on failure. - * - ****************************************************************************/ - -int stm32_mfrc522initialize(const char *devpath) -{ - struct spi_dev_s *spi; - int ret; - spi = stm32_spibus_initialize(MFRC522_SPI_PORTNO); - if (!spi) - { - return -ENODEV; - } - - /* Then register the MFRC522 */ - - ret = mfrc522_register(devpath, spi); - if (ret < 0) - { - snerr("ERROR: Error registering MFRC522\n"); - } - - return ret; -} - -#endif /* CONFIG_SPI && CONFIG_MFRC522 */ diff --git a/boards/arm/stm32/common/src/stm32_nrf24l01.c b/boards/arm/stm32/common/src/stm32_nrf24l01.c deleted file mode 100644 index 62560e1244328..0000000000000 --- a/boards/arm/stm32/common/src/stm32_nrf24l01.c +++ /dev/null @@ -1,142 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/common/src/stm32_nrf24l01.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -#include "arm_internal.h" -#include "chip.h" -#include "stm32.h" -#include "stm32_nrf24l01.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -static int nrf24l01_irq_attach(xcpt_t isr, void *arg); -static void nrf24l01_chip_enable(bool enable); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -static struct nrf24l01_config_s nrf_cfg = -{ - .irqattach = nrf24l01_irq_attach, - .chipenable = nrf24l01_chip_enable, -}; - -static xcpt_t g_isr; -static void *g_arg; - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -static int nrf24l01_irq_attach(xcpt_t isr, void *arg) -{ - wlinfo("Attach IRQ\n"); - g_isr = isr; - g_arg = arg; - stm32_gpiosetevent(BOARD_NRF24L01_GPIO_IRQ, false, true, false, - g_isr, g_arg); - return OK; -} - -static void nrf24l01_chip_enable(bool enable) -{ - wlinfo("CE:%d\n", enable); - stm32_gpiowrite(BOARD_NRF24L01_GPIO_CE, enable); -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_nrf24l01_initialize - * - * Description: - * Initialize the NRF24L01 wireless module - * - * Input Parameters: - * busno - The SPI bus number - * - * Returned Value: - * Zero (OK) on success; a negated errno value on failure. - * - ****************************************************************************/ - -int board_nrf24l01_initialize(int busno) -{ - struct spi_dev_s *spidev; - int result; - - /* Setup CE & IRQ line IOs */ - - stm32_configgpio(BOARD_NRF24L01_GPIO_CE); - stm32_configgpio(BOARD_NRF24L01_GPIO_IRQ); - - /* Init SPI bus */ - - spidev = stm32_spibus_initialize(busno); - if (!spidev) - { - wlerr("ERROR: Failed to initialize SPI bus\n"); - return -ENODEV; - } - - result = nrf24l01_register(spidev, &nrf_cfg); - if (result != OK) - { - wlerr("ERROR: Failed to register initialize SPI bus\n"); - return -ENODEV; - } - - return OK; -} diff --git a/boards/arm/stm32/common/src/stm32_qencoder.c b/boards/arm/stm32/common/src/stm32_qencoder.c deleted file mode 100644 index c701ecc056409..0000000000000 --- a/boards/arm/stm32/common/src/stm32_qencoder.c +++ /dev/null @@ -1,68 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/common/src/stm32_qencoder.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32_qencoder.h" - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_qencoder_initialize - * - * Description: - * Initialize the quadrature encoder driver for the given timer - * - ****************************************************************************/ - -int board_qencoder_initialize(int devno, int timerno) -{ - int ret; - char devpath[12]; - - /* Initialize a quadrature encoder interface. */ - - sninfo("Initializing the quadrature encoder using TIM%d\n", timerno); - snprintf(devpath, sizeof(devpath), "/dev/qe%d", devno); - ret = stm32_qeinitialize(devpath, timerno); - if (ret < 0) - { - snerr("ERROR: stm32_qeinitialize failed: %d\n", ret); - } - - return ret; -} diff --git a/boards/arm/stm32/common/src/stm32_ssd1306.c b/boards/arm/stm32/common/src/stm32_ssd1306.c deleted file mode 100644 index 093699e26b866..0000000000000 --- a/boards/arm/stm32/common/src/stm32_ssd1306.c +++ /dev/null @@ -1,160 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/common/src/stm32_ssd1306.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include -#include -#include -#include -#include - -#include "stm32_i2c.h" -#include "stm32_spi.h" - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -static struct lcd_dev_s *g_lcddev; - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_ssd1306_initialize - * - * Description: - * Initialize and register the device. I2C version. - * - * Input Parameters: - * busno - The I2C bus number - * - * Returned Value: - * Zero (OK) on success; a negated errno value on failure. - * - ****************************************************************************/ -#ifdef CONFIG_LCD_SSD1306_I2C -int board_ssd1306_initialize(int busno) -{ - struct i2c_master_s *i2c; - const int devno = 0; - - /* Initialize I2C */ - - i2c = stm32_i2cbus_initialize(busno); - if (!i2c) - { - lcderr("ERROR: Failed to initialize I2C port %d\n", busno); - return -ENODEV; - } - - /* Bind the I2C port to the OLED */ - - g_lcddev = ssd1306_initialize(i2c, NULL, devno); - if (!g_lcddev) - { - lcderr("ERROR: Failed to bind I2C port %d to OLED %d\n", busno, devno); - return -ENODEV; - } - else - { - lcdinfo("Bound I2C port %d to OLED %d\n", busno, devno); - - /* And turn the OLED on */ - - g_lcddev->setpower(g_lcddev, CONFIG_LCD_MAXPOWER); - return OK; - } -} -#endif - -/**************************************************************************** - * Name: board_ssd1306_initialize - * - * Description: - * Initialize and register the device. SPI version. - * - * Input Parameters: - * busno - The SPI bus number - * - * Returned Value: - * Zero (OK) on success; a negated errno value on failure. - * - ****************************************************************************/ -#ifdef CONFIG_LCD_SSD1306_SPI -int board_ssd1306_initialize(int busno) -{ - struct spi_dev_s *spi; - const int devno = 0; - - /* Initialize SPI */ - - spi = stm32_spibus_initialize(busno); - if (!spi) - { - lcderr("ERROR: Failed to initialize SPI port %d\n", busno); - return -ENODEV; - } - - /* Bind the SPI port to the OLED */ - - g_lcddev = ssd1306_initialize(spi, NULL, devno); - if (!g_lcddev) - { - lcderr("ERROR: Failed to bind SPI port %d to OLED %d\n", busno, devno); - return -ENODEV; - } - else - { - lcdinfo("Bound SPI port %d to OLED %d\n", busno, devno); - - /* And turn the OLED on */ - - g_lcddev->setpower(g_lcddev, CONFIG_LCD_MAXPOWER); - return OK; - } -} -#endif - -/**************************************************************************** - * Name: board_ssd1306_getdev - * - * Description: - * Get the SSD1306 device driver instance - * - * Returned Value: - * Pointer to the instance - * - ****************************************************************************/ - -struct lcd_dev_s *board_ssd1306_getdev(void) -{ - return g_lcddev; -} diff --git a/boards/arm/stm32/emw3162/CMakeLists.txt b/boards/arm/stm32/emw3162/CMakeLists.txt deleted file mode 100644 index f31385e8a774e..0000000000000 --- a/boards/arm/stm32/emw3162/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/emw3162/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32/emw3162/configs/nsh/defconfig b/boards/arm/stm32/emw3162/configs/nsh/defconfig deleted file mode 100644 index 9688757eaf295..0000000000000 --- a/boards/arm/stm32/emw3162/configs/nsh/defconfig +++ /dev/null @@ -1,41 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="emw3162" -CONFIG_ARCH_BOARD_EMW3162=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F205RG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_FS_PROCFS=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_MM_REGIONS=2 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=6 -CONFIG_START_MONTH=12 -CONFIG_START_YEAR=2011 -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_USART1=y -CONFIG_SYSTEM_NSH=y -CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/emw3162/configs/wlan/defconfig b/boards/arm/stm32/emw3162/configs/wlan/defconfig deleted file mode 100644 index ceeedd6a6b56f..0000000000000 --- a/boards/arm/stm32/emw3162/configs/wlan/defconfig +++ /dev/null @@ -1,82 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_IEEE80211_BROADCOM_FWFILES is not set -# CONFIG_MMCSD_HAVE_CARDDETECT is not set -# CONFIG_MMCSD_MMCSUPPORT is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="emw3162" -CONFIG_ARCH_BOARD_EMW3162=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F205RG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_DRIVERS_IEEE80211=y -CONFIG_DRIVERS_WIRELESS=y -CONFIG_EMW3162_WLAN=y -CONFIG_FS_PROCFS=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_IEEE80211_BROADCOM_BCM43362=y -CONFIG_IEEE80211_BROADCOM_DMABUF_ALIGNMENT=16 -CONFIG_IEEE80211_BROADCOM_FULLMAC_SDIO=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LIBM=y -CONFIG_LINE_MAX=64 -CONFIG_MMCSD=y -CONFIG_MMCSD_SDIO=y -CONFIG_MM_REGIONS=2 -CONFIG_NET=y -CONFIG_NETDB_DNSCLIENT=y -CONFIG_NETDEV_LATEINIT=y -CONFIG_NETDEV_WIRELESS_IOCTL=y -CONFIG_NETINIT_DHCPC=y -CONFIG_NETINIT_DRIPADDR=0xc0a80001 -CONFIG_NETUTILS_DHCPC=y -CONFIG_NETUTILS_TELNETD=y -CONFIG_NET_BROADCAST=y -CONFIG_NET_ETH_PKTSIZE=800 -CONFIG_NET_GUARDSIZE=32 -CONFIG_NET_ICMP_SOCKET=y -CONFIG_NET_PKT=y -CONFIG_NET_TCP=y -CONFIG_NET_UDP=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_RTC_DATETIME=y -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_WAITPID=y -CONFIG_SDIO_BLOCKSETUP=y -CONFIG_START_DAY=6 -CONFIG_START_MONTH=12 -CONFIG_START_YEAR=2011 -CONFIG_STM32_DMA2=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_PWR=y -CONFIG_STM32_RTC=y -CONFIG_STM32_SDIO=y -CONFIG_STM32_SDIO_CARD=y -CONFIG_STM32_SDIO_PULLUP=y -CONFIG_STM32_USART1=y -CONFIG_SYSLOG_CHAR=y -CONFIG_SYSLOG_DEVPATH="/dev/ttyS0" -CONFIG_SYSTEM_NSH=y -CONFIG_SYSTEM_PING=y -CONFIG_USART1_SERIAL_CONSOLE=y -CONFIG_WIRELESS_WAPI=y -CONFIG_WIRELESS_WAPI_CMDTOOL=y diff --git a/boards/arm/stm32/emw3162/include/board.h b/boards/arm/stm32/emw3162/include/board.h deleted file mode 100644 index 96825cff434d9..0000000000000 --- a/boards/arm/stm32/emw3162/include/board.h +++ /dev/null @@ -1,218 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/emw3162/include/board.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __BOARDS_ARM_STM32_EMW3162_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32_EMW3162_INCLUDE_BOARD_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#ifndef __ASSEMBLY__ -# include -#endif - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Clocking *****************************************************************/ - -/* The EMW3162 board features a single 26MHz crystal. - * - * This is the canonical configuration: - * System Clock source : PLL (HSE) - * SYSCLK(Hz) : 120000000 Determined by PLL - * configuration - * HCLK(Hz) : 120000000 (STM32_RCC_CFGR_HPRE) - * AHB Prescaler : 1 (STM32_RCC_CFGR_HPRE) - * APB1 Prescaler : 4 (STM32_RCC_CFGR_PPRE1) - * APB2 Prescaler : 2 (STM32_RCC_CFGR_PPRE2) - * HSE Frequency(Hz) : 26000000 (STM32_BOARD_XTAL) - * PLLM : 26 (STM32_PLLCFG_PLLM) - * PLLN : 240 (STM32_PLLCFG_PLLN) - * PLLP : 2 (STM32_PLLCFG_PLLP) - * PLLQ : 5 (STM32_PLLCFG_PLLQ) - * Main regulator output voltage : Scale1 mode Needed for high speed - * SYSCLK - * Flash Latency(WS) : 3 - * Prefetch Buffer : OFF - * Instruction cache : ON - * Data cache : ON - * Require 48MHz for USB OTG HS : Enabled - * SDIO and RNG clock - */ - -/* HSI - 16 MHz RC factory-trimmed - * LSI - 32 KHz RC - * HSE - On-board crystal frequency is 26MHz - * LSE - 32.768 kHz - */ - -#define STM32_BOARD_XTAL 26000000ul - -#define STM32_HSI_FREQUENCY 16000000ul -#define STM32_LSI_FREQUENCY 32000 -#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL -#define STM32_LSE_FREQUENCY 32768 - -/* Main PLL Configuration. - * - * PLL source is HSE - * PLL_VCO = (STM32_HSE_FREQUENCY / PLLM) * PLLN - * = (26,000,000 / 26) * 240 - * = 240,000,000 - * SYSCLK = PLL_VCO / PLLP - * = 240,000,000 / 2 = 120,000,000 - * USB OTG FS, SDIO and RNG Clock - * = PLL_VCO / PLLQ - * = 48,000,000 - */ - -#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(26) -#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(240) -#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_2 -#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(5) - -#define STM32_SYSCLK_FREQUENCY 120000000ul - -/* AHB clock (HCLK) is SYSCLK (120MHz) */ - -#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ -#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY - -/* APB1 clock (PCLK1) is HCLK/4 (30MHz) */ - -#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd4 /* PCLK1 = HCLK / 4 */ -#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/4) - -/* APB2 clock (PCLK2) is HCLK/2 (60MHz) */ - -#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLKd2 /* PCLK2 = HCLK / 2 */ -#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/2) - -/* LED definitions **********************************************************/ - -/* LED index values for use with board_userled() */ - -#define BOARD_LED1 0 -#define BOARD_NLEDS 1 - -/* LED bits for use with board_userled_all() */ - -#define BOARD_LED1_BIT (1 << BOARD_LED1) - -/* These LEDs are not used by the board port unless CONFIG_ARCH_LEDS is - * defined. In that case, the usage by the board port is defined in - * include/board.h and src/sam_autoleds.c. The LEDs are used to encode - * OS-related events as follows: - * - * ------------------- ---------------------------- ------ - * SYMBOL Meaning LED - * ------------------- ---------------------------- ------ - */ - -#define LED_STARTED 0 /* NuttX has been started OFF */ -#define LED_HEAPALLOCATE 0 /* Heap has been allocated OFF */ -#define LED_IRQSENABLED 0 /* Interrupts enabled OFF */ -#define LED_STACKCREATED 1 /* Idle stack created ON */ -#define LED_INIRQ 2 /* In an interrupt N/C */ -#define LED_SIGNAL 2 /* In a signal handler N/C */ -#define LED_ASSERTION 2 /* An assertion failed N/C */ -#define LED_PANIC 3 /* The system has crashed FLASH */ -#undef LED_IDLE /* MCU is in sleep mode Not used */ - -/* Thus if LED is statically on, NuttX has successfully booted and is, - * apparently, running normally. If LED is flashing at approximately - * 2Hz, then a fatal error has been detected and the system has halted. - */ - -/* Alternate function pin selections ****************************************/ - -/* UART1 */ - -#ifdef CONFIG_STM32_USART1 -# define GPIO_USART1_RX (GPIO_USART1_RX_1|GPIO_SPEED_100MHz) -# define GPIO_USART1_TX (GPIO_USART1_TX_1|GPIO_SPEED_100MHz) -#endif - -/* MCO1 */ - -#define GPIO_MCO1 (GPIO_MCO1_0|GPIO_SPEED_100MHz) - -/* SDIO */ - -#define GPIO_SDIO_CK (GPIO_SDIO_CK_0|GPIO_SPEED_50MHz) -#define GPIO_SDIO_CMD (GPIO_SDIO_CMD_0|GPIO_SPEED_50MHz) -#define GPIO_SDIO_D0 (GPIO_SDIO_D0_0|GPIO_SPEED_50MHz) -#define GPIO_SDIO_D1 (GPIO_SDIO_D1_0|GPIO_SPEED_50MHz) -#define GPIO_SDIO_D2 (GPIO_SDIO_D2_0|GPIO_SPEED_50MHz) -#define GPIO_SDIO_D3 (GPIO_SDIO_D3_0|GPIO_SPEED_50MHz) - -/* SDIO definitions *********************************************************/ - -/* Note that slower clocking is required when DMA is disabled in order - * to avoid RX overrun/TX underrun errors due to delayed responses - * to service FIFOs in interrupt driven mode. - * - * These values have not been tuned!!! - * - * SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(118+2)=400 KHz - */ - -#define SDIO_INIT_CLKDIV (118 << SDIO_CLKCR_CLKDIV_SHIFT) - -/* DMA ON: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(1+2)=16 MHz - * DMA OFF: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(2+2)=12 MHz - */ - -#ifdef CONFIG_SDIO_DMA -# define SDIO_MMCXFR_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT) -#else -# define SDIO_MMCXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT) -#endif - -/* DMA ON: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(1+2)=16 MHz - * DMA OFF: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(2+2)=12 MHz - */ - -#ifdef CONFIG_SDIO_DMA -# define SDIO_SDXFR_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT) -#else -# define SDIO_SDXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT) -#endif - -/* DMA Channel/Stream Selections ********************************************/ - -/* Stream selections are arbitrary for now but might become important in the - * future if we set aside more DMA channels/streams. - * - * SDIO DMA - * DMAMAP_SDIO_1 = Channel 4, Stream 3 - * DMAMAP_SDIO_2 = Channel 4, Stream 6 - */ - -#define DMAMAP_SDIO DMAMAP_SDIO_1 - -#endif /* __BOARDS_ARM_STM32_EMW3162_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32/emw3162/scripts/Make.defs b/boards/arm/stm32/emw3162/scripts/Make.defs deleted file mode 100644 index bc77620c6b44b..0000000000000 --- a/boards/arm/stm32/emw3162/scripts/Make.defs +++ /dev/null @@ -1,41 +0,0 @@ -############################################################################ -# boards/arm/stm32/emw3162/scripts/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/.config -include $(TOPDIR)/tools/Config.mk -include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs - -LDSCRIPT = ld.script -ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) - -ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 - -CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) -CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) -CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -AFLAGS := $(CFLAGS) -D__ASSEMBLY__ - -NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -Wl,-no-check-sections -LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32/emw3162/scripts/ld.script b/boards/arm/stm32/emw3162/scripts/ld.script deleted file mode 100644 index 469fdbf5198f5..0000000000000 --- a/boards/arm/stm32/emw3162/scripts/ld.script +++ /dev/null @@ -1,130 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/emw3162/scripts/ld.script - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* The STM32F205RG has 1024Kb of FLASH beginning at address 0x0800:0000 and - * 112Kb of SRAM in main SRAM1 and 16 Kb in auxiliary SRAM2. - * - * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 - * where the code expects to begin execution by jumping to the entry point in - * the 0x0800:0000 address - * range. - */ - -MEMORY -{ - flash (rx) : ORIGIN = 0x08000000, LENGTH = 1024K - sram (rwx) : ORIGIN = 0x20000000, LENGTH = 112K -} - -OUTPUT_ARCH(arm) -EXTERN(_vectors) -ENTRY(_stext) -SECTIONS -{ - .text : { - _stext = ABSOLUTE(.); - *(.vectors) - *(.text .text.*) - *(.fixup) - *(.gnu.warning) - - wlan_firmware_image_location = .; - *(.wlan_firmware_image .wlan_firmware_image.*) - wlan_firmware_image_end = .; - - wlan_nvram_image_location = .; - *(.wlan_nvram_image .wlan_nvram_image.*) - wlan_nvram_image_end = .; - - *(.rodata .rodata.*) - *(.gnu.linkonce.t.*) - *(.glue_7) - *(.glue_7t) - *(.got) - *(.gcc_except_table) - *(.gnu.linkonce.r.*) - _etext = ABSOLUTE(.); - } > flash - - .init_section : { - _sinit = ABSOLUTE(.); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) - KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) - _einit = ABSOLUTE(.); - } > flash - - .ARM.extab : { - *(.ARM.extab*) - } > flash - - __exidx_start = ABSOLUTE(.); - .ARM.exidx : { - *(.ARM.exidx*) - } > flash - __exidx_end = ABSOLUTE(.); - - .tdata : { - _stdata = ABSOLUTE(.); - *(.tdata .tdata.* .gnu.linkonce.td.*); - _etdata = ABSOLUTE(.); - } > flash - - .tbss : { - _stbss = ABSOLUTE(.); - *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); - _etbss = ABSOLUTE(.); - } > flash - - _eronly = ABSOLUTE(.); - - .data : { - _sdata = ABSOLUTE(.); - *(.data .data.*) - *(.gnu.linkonce.d.*) - CONSTRUCTORS - . = ALIGN(4); - _edata = ABSOLUTE(.); - } > sram AT > flash - - .bss : { - _sbss = ABSOLUTE(.); - *(.bss .bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - . = ALIGN(4); - _ebss = ABSOLUTE(.); - } > sram - - /* Stabs debugging sections. */ - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_info 0 : { *(.debug_info) } - .debug_line 0 : { *(.debug_line) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_aranges 0 : { *(.debug_aranges) } -} diff --git a/boards/arm/stm32/emw3162/src/CMakeLists.txt b/boards/arm/stm32/emw3162/src/CMakeLists.txt deleted file mode 100644 index 8c94250123d10..0000000000000 --- a/boards/arm/stm32/emw3162/src/CMakeLists.txt +++ /dev/null @@ -1,38 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/emw3162/src/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -set(SRCS stm32_boot.c stm32_bringup.c) - -if(CONFIG_ARCH_LEDS) - list(APPEND SRCS stm32_autoleds.c) -else() - list(APPEND SRCS stm32_userleds.c) -endif() - -if(CONFIG_EMW3162_WLAN) - list(APPEND SRCS stm32_wlan.c) - list(APPEND SRCS stm32_wlan_firmware.c) -endif() - -target_sources(board PRIVATE ${SRCS}) - -set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/ld.script") diff --git a/boards/arm/stm32/emw3162/src/Make.defs b/boards/arm/stm32/emw3162/src/Make.defs deleted file mode 100644 index f397baef02ba8..0000000000000 --- a/boards/arm/stm32/emw3162/src/Make.defs +++ /dev/null @@ -1,40 +0,0 @@ -############################################################################ -# boards/arm/stm32/emw3162/src/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/Make.defs - -CSRCS = stm32_boot.c stm32_bringup.c - -ifeq ($(CONFIG_ARCH_LEDS),y) -CSRCS += stm32_autoleds.c -else -CSRCS += stm32_userleds.c -endif - -ifeq ($(CONFIG_EMW3162_WLAN),y) -CSRCS += stm32_wlan.c -CSRCS += stm32_wlan_firmware.c -endif - -DEPPATH += --dep-path board -VPATH += :board -CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/emw3162/src/stm32_autoleds.c b/boards/arm/stm32/emw3162/src/stm32_autoleds.c deleted file mode 100644 index cb2dd8f580b9e..0000000000000 --- a/boards/arm/stm32/emw3162/src/stm32_autoleds.c +++ /dev/null @@ -1,101 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/emw3162/src/stm32_autoleds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* LEDs - * - * These LEDs are not used by the board port unless CONFIG_ARCH_LEDS is - * defined. In that case, the usage by the board port is defined in - * include/board.h and src/sam_autoleds.c. The LEDs are used to encode - * OS-related events as follows: - * - * ------------------- ----------------------- ------ - * SYMBOL Meaning LED - * ------------------- ----------------------- ------ - * LED_STARTED NuttX has been started OFF - * LED_HEAPALLOCATE Heap has been allocated OFF - * LED_IRQSENABLED Interrupts enabled OFF - * LED_STACKCREATED Idle stack created ON - * LED_INIRQ In an interrupt N/C - * LED_SIGNAL In a signal handler N/C - * LED_ASSERTION An assertion failed N/C - * LED_PANIC The system has crashed FLASH - * - * Thus is LED is statically on, NuttX has successfully booted and is, - * apparently, running normally. If LED is flashing at approximately - * 2Hz, then a fatal error has been detected and the system has halted. - */ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include - -#include -#include - -#include "stm32_gpio.h" -#include "emw3162.h" - -#ifdef CONFIG_ARCH_LEDS - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_autoled_initialize - ****************************************************************************/ - -void board_autoled_initialize(void) -{ - /* Configure EMW3162 LED gpio as output */ - - stm32_configgpio(GPIO_LED1); -} - -/**************************************************************************** - * Name: board_autoled_on - ****************************************************************************/ - -void board_autoled_on(int led) -{ - if (led == 1 || led == 3) - { - stm32_gpiowrite(GPIO_LED1, true); - } -} - -/**************************************************************************** - * Name: board_autoled_off - ****************************************************************************/ - -void board_autoled_off(int led) -{ - if (led == 3) - { - stm32_gpiowrite(GPIO_LED1, false); - } -} - -#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/emw3162/src/stm32_boot.c b/boards/arm/stm32/emw3162/src/stm32_boot.c deleted file mode 100644 index fc3647ca0cf37..0000000000000 --- a/boards/arm/stm32/emw3162/src/stm32_boot.c +++ /dev/null @@ -1,80 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/emw3162/src/stm32_boot.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include "arm_internal.h" -#include "emw3162.h" - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_boardinitialize - * - * Description: - * All STM32 architectures must provide the following entry point. This - * entry point is called early in the initialization -- after all memory - * has been configured and mapped but before any devices have been - * initialized. - * - ****************************************************************************/ - -void stm32_boardinitialize(void) -{ -#ifdef CONFIG_ARCH_LEDS - /* Configure on-board LEDs if LED support has been selected. */ - - board_autoled_initialize(); -#endif -} - -/**************************************************************************** - * Name: board_late_initialize - * - * Description: - * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional - * initialization call will be performed in the boot-up sequence to a - * function called board_late_initialize(). board_late_initialize() will - * be called immediately after up_intitialize() is called and just before - * the initial application is started. This additional initialization - * phase may be used, for example, to initialize board-specific device - * drivers. - * - ****************************************************************************/ - -#ifdef CONFIG_BOARD_LATE_INITIALIZE -void board_late_initialize(void) -{ - /* Perform board initialization */ - - stm32_bringup(); -} -#endif /* CONFIG_BOARD_LATE_INITIALIZE */ diff --git a/boards/arm/stm32/emw3162/src/stm32_bringup.c b/boards/arm/stm32/emw3162/src/stm32_bringup.c deleted file mode 100644 index 0ffd40553fca8..0000000000000 --- a/boards/arm/stm32/emw3162/src/stm32_bringup.c +++ /dev/null @@ -1,96 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/emw3162/src/stm32_bringup.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include -#include - -#include - -#include "emw3162.h" - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_bringup - * - * Description: - * This function initializes and configures all on-board features - * appropriate for the selected configuration. - * - ****************************************************************************/ - -int stm32_bringup(void) -{ - int ret = OK; - -#ifdef CONFIG_FS_PROCFS - /* Mount the procfs file system */ - - ret = nx_mount(NULL, "/proc", "procfs", 0, NULL); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: Failed to mount procfs at /proc: %d\n", ret); - } -#endif - -#if defined(CONFIG_USERLED) && !defined(CONFIG_ARCH_LEDS) -#ifdef CONFIG_USERLED_LOWER - /* Register the LED driver */ - - ret = userled_lower_initialize("/dev/userleds"); - if (ret != OK) - { - syslog(LOG_ERR, "ERROR: userled_lower_initialize() failed: %d\n", ret); - return ret; - } -#else - /* Enable USER LED support for some other purpose */ - - board_userled_initialize(); -#endif /* CONFIG_USERLED_LOWER */ -#endif /* CONFIG_USERLED && !CONFIG_ARCH_LEDS */ - -#ifdef CONFIG_EMW3162_WLAN - /* Initialize wlan driver and hardware */ - - ret = emw3162_wlan_initialize(); - if (ret != OK) - { - syslog(LOG_ERR, "Failed to initialize wlan: %d\n", ret); - return ret; - } -#endif - - return ret; -} diff --git a/boards/arm/stm32/emw3162/src/stm32_userleds.c b/boards/arm/stm32/emw3162/src/stm32_userleds.c deleted file mode 100644 index 61d304b6cf600..0000000000000 --- a/boards/arm/stm32/emw3162/src/stm32_userleds.c +++ /dev/null @@ -1,74 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/emw3162/src/stm32_userleds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include - -#include -#include "emw3162.h" - -#include "stm32_gpio.h" - -#ifndef CONFIG_ARCH_LEDS - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_userled_initialize - ****************************************************************************/ - -uint32_t board_userled_initialize(void) -{ - /* Configure EMW3162 LED gpio as output */ - - stm32_configgpio(GPIO_LED1); - return BOARD_NLEDS; -} - -/**************************************************************************** - * Name: board_userled - ****************************************************************************/ - -void board_userled(int led, bool ledon) -{ - if (led == BOARD_LED1) - { - stm32_gpiowrite(GPIO_LED1, ledon); - } -} - -/**************************************************************************** - * Name: board_userled_all - ****************************************************************************/ - -void board_userled_all(uint32_t ledset) -{ - stm32_gpiowrite(GPIO_LED1, !!(ledset & BOARD_LED1_BIT)); -} - -#endif /* !CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/emw3162/src/stm32_wlan.c b/boards/arm/stm32/emw3162/src/stm32_wlan.c deleted file mode 100644 index d8a110dc14fec..0000000000000 --- a/boards/arm/stm32/emw3162/src/stm32_wlan.c +++ /dev/null @@ -1,176 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/emw3162/src/stm32_wlan.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include -#include - -#include - -#include "stm32.h" -#include "stm32_gpio.h" -#include "stm32_sdio.h" - -#include "emw3162.h" - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -static struct sdio_dev_s *g_sdio_dev; - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: bcmf_board_reset - ****************************************************************************/ - -void bcmf_board_reset(int minor, bool reset) -{ - if (minor != SDIO_WLAN0_MINOR) - { - return; - } - - stm32_gpiowrite(GPIO_WLAN0_RESET, !reset); -} - -/**************************************************************************** - * Name: bcmf_board_power - ****************************************************************************/ - -void bcmf_board_power(int minor, bool power) -{ - if (minor != SDIO_WLAN0_MINOR) - { - return; - } - - stm32_gpiowrite(GPIO_WLAN0_PWRDN, !power); -} - -/**************************************************************************** - * Name: bcmf_board_initialize - ****************************************************************************/ - -void bcmf_board_initialize(int minor) -{ - if (minor != SDIO_WLAN0_MINOR) - { - return; - } - - /* Configure MCO1 output to drive EXT_SLEEP_CLK input pin of BCM43362 */ - - stm32_configgpio(GPIO_MCO1); - stm32_mco1config(RCC_CFGR_MCO1_LSE, RCC_CFGR_MCO1PRE_NONE); - - /* Configure PowerDown pin */ - - stm32_configgpio(GPIO_WLAN0_PWRDN); - - /* Shutdown wlan chip */ - - bcmf_board_power(minor, false); - - /* Configure reset pin */ - - stm32_configgpio(GPIO_WLAN0_RESET); - - /* Put wlan chip in reset state */ - - bcmf_board_reset(minor, true); -} - -/**************************************************************************** - * Name: bcmf_board_setup_oob_irq - ****************************************************************************/ - -void bcmf_board_setup_oob_irq(int minor, int (*func)(void *), void *arg) -{ - if (minor != SDIO_WLAN0_MINOR) - { - return; - } - - /* Configure SDIO card in-band interrupt callback */ - - if (g_sdio_dev != NULL) - { - sdio_set_sdio_card_isr(g_sdio_dev, func, arg); - } -} - -/**************************************************************************** - * Name: bcmf_board_etheraddr - ****************************************************************************/ - -bool bcmf_board_etheraddr(struct ether_addr *ethaddr) -{ - return false; -} - -/**************************************************************************** - * Name: emw3162_wlan_initialize - ****************************************************************************/ - -int emw3162_wlan_initialize() -{ - int ret; - - /* Initialize sdio interface */ - - wlinfo("Initializing SDIO slot %d\n", SDIO_WLAN0_SLOTNO); - - g_sdio_dev = sdio_initialize(SDIO_WLAN0_SLOTNO); - - if (!g_sdio_dev) - { - wlerr("ERROR: Failed to initialize SDIO with slot %d\n", - SDIO_WLAN0_SLOTNO); - return ERROR; - } - - /* Bind the SDIO interface to the bcmf driver */ - - ret = bcmf_sdio_initialize(SDIO_WLAN0_MINOR, g_sdio_dev); - - if (ret != OK) - { - wlerr("ERROR: Failed to bind SDIO to bcmf driver\n"); - - /* FIXME deinitialize sdio device */ - - return ERROR; - } - - return OK; -} diff --git a/boards/arm/stm32/et-stm32-stamp/CMakeLists.txt b/boards/arm/stm32/et-stm32-stamp/CMakeLists.txt deleted file mode 100644 index d1c3d364013d5..0000000000000 --- a/boards/arm/stm32/et-stm32-stamp/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/et-stm32-stamp/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32/et-stm32-stamp/configs/nsh/defconfig b/boards/arm/stm32/et-stm32-stamp/configs/nsh/defconfig deleted file mode 100644 index 4c71777c0f8a7..0000000000000 --- a/boards/arm/stm32/et-stm32-stamp/configs/nsh/defconfig +++ /dev/null @@ -1,35 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="et-stm32-stamp" -CONFIG_ARCH_BOARD_ET_STM32_STAMP=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F103RE=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=5483 -CONFIG_BUILTIN=y -CONFIG_DEFAULT_SMALL=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_LIBC_RAND_ORDER=2 -CONFIG_LINE_MAX=80 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=1024 -CONFIG_PTHREAD_STACK_DEFAULT=1024 -CONFIG_RAM_SIZE=20480 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_START_DAY=23 -CONFIG_START_MONTH=10 -CONFIG_START_YEAR=2009 -CONFIG_STM32_USART1=y -CONFIG_SYMTAB_ORDEREDBYNAME=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/et-stm32-stamp/include/board.h b/boards/arm/stm32/et-stm32-stamp/include/board.h deleted file mode 100644 index c2d3dd4b1a930..0000000000000 --- a/boards/arm/stm32/et-stm32-stamp/include/board.h +++ /dev/null @@ -1,155 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/et-stm32-stamp/include/board.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __BOARDS_ARM_STM32_ET_STM32_STAMP_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32_ET_STM32_STAMP_INCLUDE_BOARD_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#ifndef __ASSEMBLY__ -# include -#endif - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Clocking *****************************************************************/ - -/* On-board crystal frequency is 8MHz (HSE) */ - -#define STM32_BOARD_XTAL 8000000ul - -/* PLL source is HSE/1, PLL multiplier is 9: - * PLL frequency is 8MHz (XTAL) x 9 = 72MHz - */ - -#define STM32_CFGR_PLLSRC RCC_CFGR_PLLSRC -#define STM32_CFGR_PLLXTPRE 0 -#define STM32_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx9 -#define STM32_PLL_FREQUENCY (9*STM32_BOARD_XTAL) - -/* Use the PLL and set the SYSCLK source to be the PLL */ - -#define STM32_SYSCLK_SW RCC_CFGR_SW_PLL -#define STM32_SYSCLK_SWS RCC_CFGR_SWS_PLL -#define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY - -/* AHB clock (HCLK) is SYSCLK (72MHz) */ - -#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK -#define STM32_HCLK_FREQUENCY STM32_PLL_FREQUENCY - -/* APB2 clock (PCLK2) is HCLK (72MHz) */ - -#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK -#define STM32_PCLK2_FREQUENCY STM32_HCLK_FREQUENCY - -/* APB2 timers 1 and 8 will receive PCLK2. */ - -#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) - -/* APB1 clock (PCLK1) is HCLK/2 (36MHz) */ - -#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd2 -#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/2) - -/* APB1 timers 2-7 will be twice PCLK1 */ - -#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) - -/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx - * otherwise frequency is 2xAPBx. - * Note: TIM1,8 are on APB2, others on APB1 - */ - -#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM2_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM3_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM4_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM5_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM6_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM7_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY - -/* SDIO dividers. Note that slower clocking is required when DMA is disabled - * in order to avoid RX overrun/TX underrun errors due to delayed responses - * to service FIFOs in interrupt driven mode. These values have not been - * tuned!!! - * - * HCLK=72MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(178+2)=400 KHz - */ - -#define SDIO_INIT_CLKDIV (178 << SDIO_CLKCR_CLKDIV_SHIFT) - -/* DMA ON: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(2+2)=18 MHz - * DMA OFF: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(3+2)=14.4 MHz - */ - -#ifdef CONFIG_SDIO_DMA -# define SDIO_MMCXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT) -#else -# define SDIO_MMCXFR_CLKDIV (3 << SDIO_CLKCR_CLKDIV_SHIFT) -#endif - -/* DMA ON: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(1+2)=24 MHz - * DMA OFF: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(3+2)=14.4 MHz - */ - -#ifdef CONFIG_SDIO_DMA -# define SDIO_SDXFR_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT) -#else -# define SDIO_SDXFR_CLKDIV (3 << SDIO_CLKCR_CLKDIV_SHIFT) -#endif - -/* LED definitions **********************************************************/ - -/* The ET-STM32 Stamp doesn't have an on-board LED. These innocent macros - * can still be here. - */ - -#define LED_STARTED 0 /* No LEDs */ -#define LED_HEAPALLOCATE 1 /* LED1 on */ -#define LED_IRQSENABLED 2 /* LED2 on */ -#define LED_STACKCREATED 3 /* LED1 on */ -#define LED_INIRQ 4 /* LED1 off */ -#define LED_SIGNAL 5 /* LED2 on */ -#define LED_ASSERTION 6 /* LED1 + LED2 */ -#define LED_PANIC 7 /* LED1 / LED2 blinking */ - -/* Alternate function pin selections (auto-aliased for new pinmap) */ - -/* USART1 */ - -#define GPIO_USART1_TX GPIO_ADJUST_MODE(GPIO_USART1_TX_0, GPIO_MODE_50MHz) -#define GPIO_USART1_RX GPIO_USART1_RX_0 - -#endif /* __BOARDS_ARM_STM32_ET_STM32_STAMP_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32/et-stm32-stamp/scripts/Make.defs b/boards/arm/stm32/et-stm32-stamp/scripts/Make.defs deleted file mode 100644 index 702ac50cba50b..0000000000000 --- a/boards/arm/stm32/et-stm32-stamp/scripts/Make.defs +++ /dev/null @@ -1,41 +0,0 @@ -############################################################################ -# boards/arm/stm32/et-stm32-stamp/scripts/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/.config -include $(TOPDIR)/tools/Config.mk -include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs - -LDSCRIPT = ld.script -ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) - -ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 - -CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) -CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) -CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -AFLAGS := $(CFLAGS) -D__ASSEMBLY__ - -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections -LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32/et-stm32-stamp/scripts/ld.script b/boards/arm/stm32/et-stm32-stamp/scripts/ld.script deleted file mode 100644 index ddf645d3c6c7d..0000000000000 --- a/boards/arm/stm32/et-stm32-stamp/scripts/ld.script +++ /dev/null @@ -1,123 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/et-stm32-stamp/scripts/ld.script - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - * - ****************************************************************************/ - -/* The STM32F103RE has 512Kb of FLASH beginning at address 0x0800:0000 and - * 64Kb of SRAM beginning at address 0x2000:0000. When booting from FLASH, - * FLASH memory is aliased to address 0x0000:0000 where the code expects to - * begin execution by jumping to the entry point in the 0x0800:0000 address - * range. - */ - -MEMORY -{ - flash (rx) : ORIGIN = 0x08000000, LENGTH = 512K - sram (rwx) : ORIGIN = 0x20000000, LENGTH = 64K -} - -OUTPUT_ARCH(arm) -EXTERN(_vectors) -ENTRY(_stext) -SECTIONS -{ - .text : { - _stext = ABSOLUTE(.); - *(.vectors) - *(.text .text.*) - *(.fixup) - *(.gnu.warning) - *(.rodata .rodata.*) - *(.gnu.linkonce.t.*) - *(.glue_7) - *(.glue_7t) - *(.got) - *(.gcc_except_table) - *(.gnu.linkonce.r.*) - _etext = ABSOLUTE(.); - } > flash - - .init_section : ALIGN(4) { - _sinit = ABSOLUTE(.); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) - KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) - _einit = ABSOLUTE(.); - } > flash - - .ARM.extab : ALIGN(4) { - *(.ARM.extab*) - } > flash - - .ARM.exidx : ALIGN(4) { - __exidx_start = ABSOLUTE(.); - *(.ARM.exidx*) - __exidx_end = ABSOLUTE(.); - } > flash - - .tdata : { - _stdata = ABSOLUTE(.); - *(.tdata .tdata.* .gnu.linkonce.td.*); - _etdata = ABSOLUTE(.); - } > flash - - .tbss : { - _stbss = ABSOLUTE(.); - *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); - _etbss = ABSOLUTE(.); - } > flash - - _eronly = ABSOLUTE(.); - - /* The STM32F103RET6 has 64Kb of SRAM beginning at the following address */ - - .data : ALIGN(4) { - _sdata = ABSOLUTE(.); - *(.data .data.*) - *(.gnu.linkonce.d.*) - CONSTRUCTORS - . = ALIGN(4); - _edata = ABSOLUTE(.); - } > sram AT > flash - - .bss : ALIGN(4) { - _sbss = ABSOLUTE(.); - *(.bss .bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - . = ALIGN(4); - _ebss = ABSOLUTE(.); - } > sram - - /* Stabs debugging sections. */ - - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_info 0 : { *(.debug_info) } - .debug_line 0 : { *(.debug_line) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_aranges 0 : { *(.debug_aranges) } -} diff --git a/boards/arm/stm32/et-stm32-stamp/src/CMakeLists.txt b/boards/arm/stm32/et-stm32-stamp/src/CMakeLists.txt deleted file mode 100644 index 3aa3d6093c62e..0000000000000 --- a/boards/arm/stm32/et-stm32-stamp/src/CMakeLists.txt +++ /dev/null @@ -1,27 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/et-stm32-stamp/src/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -set(SRCS stm32_boot.c) - -target_sources(board PRIVATE ${SRCS}) - -set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/ld.script") diff --git a/boards/arm/stm32/et-stm32-stamp/src/Make.defs b/boards/arm/stm32/et-stm32-stamp/src/Make.defs deleted file mode 100644 index 009c8104955d9..0000000000000 --- a/boards/arm/stm32/et-stm32-stamp/src/Make.defs +++ /dev/null @@ -1,29 +0,0 @@ -############################################################################ -# boards/arm/stm32/et-stm32-stamp/src/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/Make.defs - -CSRCS = stm32_boot.c - -DEPPATH += --dep-path board -VPATH += :board -CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/et-stm32-stamp/src/stm32_boot.c b/boards/arm/stm32/et-stm32-stamp/src/stm32_boot.c deleted file mode 100644 index b56fe99ba7168..0000000000000 --- a/boards/arm/stm32/et-stm32-stamp/src/stm32_boot.c +++ /dev/null @@ -1,83 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/et-stm32-stamp/src/stm32_boot.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include -#include - -#include -#include - -#include "arm_internal.h" -#include "et-stm32-stamp.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_boardinitialize - * - * Description: - * All STM32 architectures must provide the following entry point. This - * entry point is called early in the initialization -- after all memory - * has been configured and mapped but before any devices have been - * initialized. - * - ****************************************************************************/ - -void stm32_boardinitialize(void) -{ - /* Empty for now. */ -} - -/**************************************************************************** - * Name: board_late_initialize - * - * Description: - * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional - * initialization call will be performed in the boot-up sequence to a - * function called board_late_initialize(). board_late_initialize() will - * be called immediately after up_initialize() is called and just before - * the initial application is started. This additional initialization - * phase may be used, for example, to initialize board-specific device - * drivers. - * - ****************************************************************************/ - -#ifdef CONFIG_BOARD_LATE_INITIALIZE -void board_late_initialize(void) -{ -} -#endif diff --git a/boards/arm/stm32/fire-stm32v2/CMakeLists.txt b/boards/arm/stm32/fire-stm32v2/CMakeLists.txt deleted file mode 100644 index a7c4eb1ccad98..0000000000000 --- a/boards/arm/stm32/fire-stm32v2/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/fire-stm32v2/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32/fire-stm32v2/configs/nsh/defconfig b/boards/arm/stm32/fire-stm32v2/configs/nsh/defconfig deleted file mode 100644 index 334352f98536b..0000000000000 --- a/boards/arm/stm32/fire-stm32v2/configs/nsh/defconfig +++ /dev/null @@ -1,88 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_MMCSD_HAVE_CARDDETECT is not set -# CONFIG_MMCSD_MMCSUPPORT is not set -# CONFIG_NSH_DISABLE_IFCONFIG is not set -# CONFIG_NSH_DISABLE_PS is not set -# CONFIG_SPI_CALLBACK is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="fire-stm32v2" -CONFIG_ARCH_BOARD_FIRE_STM32=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F103VE=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=5483 -CONFIG_BUILTIN=y -CONFIG_ENC28J60=y -CONFIG_FAT_LCNAMES=y -CONFIG_FAT_LFN=y -CONFIG_FS_FAT=y -CONFIG_HOST_WINDOWS=y -CONFIG_I2C=y -CONFIG_I2CTOOL_DEFFREQ=100000 -CONFIG_I2CTOOL_MAXBUS=2 -CONFIG_I2CTOOL_MINBUS=1 -CONFIG_I2C_POLLED=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_MMCSD=y -CONFIG_MMCSD_SDIO=y -CONFIG_NET=y -CONFIG_NETDB_DNSCLIENT=y -CONFIG_NETDB_DNSSERVER_NOADDR=y -CONFIG_NETINIT_NOMAC=y -CONFIG_NETUTILS_TELNETD=y -CONFIG_NETUTILS_TFTPC=y -CONFIG_NETUTILS_WEBCLIENT=y -CONFIG_NET_BROADCAST=y -CONFIG_NET_ICMP_SOCKET=y -CONFIG_NET_MAX_LISTENPORTS=16 -CONFIG_NET_STATISTICS=y -CONFIG_NET_TCP=y -CONFIG_NET_TCP_PREALLOC_CONNS=16 -CONFIG_NET_UDP=y -CONFIG_NET_UDP_CHECKSUMS=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_RAM_SIZE=65536 -CONFIG_RAM_START=0x20000000 -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_HPWORKPRIORITY=192 -CONFIG_SCHED_HPWORKSTACKSIZE=1024 -CONFIG_SCHED_WAITPID=y -CONFIG_STM32_BKP=y -CONFIG_STM32_DMA2=y -CONFIG_STM32_I2C1=y -CONFIG_STM32_JTAG_FULL_ENABLE=y -CONFIG_STM32_PWR=y -CONFIG_STM32_RTC=y -CONFIG_STM32_SDIO=y -CONFIG_STM32_SPI1=y -CONFIG_STM32_USART1=y -CONFIG_STM32_USART2=y -CONFIG_STM32_USB=y -CONFIG_SYSTEM_I2CTOOL=y -CONFIG_SYSTEM_NSH=y -CONFIG_SYSTEM_PING=y -CONFIG_SYSTEM_USBMSC=y -CONFIG_SYSTEM_USBMSC_DEVMINOR1=0 -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART1_SERIAL_CONSOLE=y -CONFIG_USBMSC=y -CONFIG_USBMSC_BULKINREQLEN=256 -CONFIG_USBMSC_BULKOUTREQLEN=256 -CONFIG_USBMSC_EPBULKIN=5 -CONFIG_USBMSC_NRDREQS=2 -CONFIG_USBMSC_NWRREQS=2 -CONFIG_USBMSC_PRODUCTSTR="USBdev Storage" -CONFIG_USBMSC_REMOVABLE=y -CONFIG_USBMSC_VERSIONNO=0x0399 diff --git a/boards/arm/stm32/fire-stm32v2/include/board.h b/boards/arm/stm32/fire-stm32v2/include/board.h deleted file mode 100644 index 573773b7da393..0000000000000 --- a/boards/arm/stm32/fire-stm32v2/include/board.h +++ /dev/null @@ -1,451 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/fire-stm32v2/include/board.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __BOARDS_ARM_STM32_FIRE_STM32V2_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32_FIRE_STM32V2_INCLUDE_BOARD_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#ifndef __ASSEMBLY__ -# include -#endif - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Clocking *****************************************************************/ - -/* HSI - 8 MHz RC factory-trimmed - * LSI - 40 KHz RC (30-60KHz, uncalibrated) - * HSE - On-board crystal frequency is 8MHz - * LSE - 32.768 kHz crytal - */ - -#define STM32_BOARD_XTAL 8000000ul - -#define STM32_HSI_FREQUENCY 8000000ul -#define STM32_LSI_FREQUENCY 40000 -#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL -#define STM32_LSE_FREQUENCY 32768 - -/* PLL source is HSE/1, - * PLL multiplier is 9: - * PLL frequency is 8MHz (XTAL) x 9 = 72MHz - */ - -#define STM32_CFGR_PLLSRC RCC_CFGR_PLLSRC -#define STM32_CFGR_PLLXTPRE 0 -#define STM32_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx9 -#define STM32_PLL_FREQUENCY (9*STM32_BOARD_XTAL) - -/* Use the PLL and set the SYSCLK source to be the PLL */ - -#define STM32_SYSCLK_SW RCC_CFGR_SW_PLL -#define STM32_SYSCLK_SWS RCC_CFGR_SWS_PLL -#define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY - -/* AHB clock (HCLK) is SYSCLK (72MHz) */ - -#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK -#define STM32_HCLK_FREQUENCY STM32_PLL_FREQUENCY - -/* APB2 clock (PCLK2) is HCLK (72MHz) */ - -#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK -#define STM32_PCLK2_FREQUENCY STM32_HCLK_FREQUENCY -#define STM32_APB2_CLKIN (STM32_PCLK2_FREQUENCY) /* Timers 2-7, 12-14 */ - -/* APB2 timers 1 and 8 will receive PCLK2. */ - -#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) - -/* APB1 clock (PCLK1) is HCLK/2 (36MHz) */ - -#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd2 -#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/2) - -/* APB1 timers 2-7 will be twice PCLK1 */ - -#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) - -/* USB divider -- Divide PLL clock by 1.5 */ - -#define STM32_CFGR_USBPRE 0 - -/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx - * otherwise frequency is 2xAPBx. - * Note: TIM1,8 are on APB2, others on APB1 - */ - -#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM2_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM3_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM4_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM5_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM6_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM7_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY - -/* SDIO dividers. Note that slower clocking is required when DMA is disabled - * in order to avoid RX overrun/TX underrun errors due to delayed responses - * to service FIFOs in interrupt driven mode. These values have not been - * tuned!!! - * - * HCLK=72MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(178+2)=400 KHz - */ - -#define SDIO_INIT_CLKDIV (178 << SDIO_CLKCR_CLKDIV_SHIFT) - -/* DMA ON: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(2+2)=18 MHz - * DMA OFF: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(3+2)=14.4 MHz - */ - -#ifdef CONFIG_STM32_SDIO_DMA -# define SDIO_MMCXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT) -#else -# define SDIO_MMCXFR_CLKDIV (3 << SDIO_CLKCR_CLKDIV_SHIFT) -#endif - -/* DMA ON: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(1+2)=24 MHz - * DMA OFF: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(3+2)=14.4 MHz - */ - -#ifdef CONFIG_STM32_SDIO_DMA -# define SDIO_SDXFR_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT) -#else -# define SDIO_SDXFR_CLKDIV (3 << SDIO_CLKCR_CLKDIV_SHIFT) -#endif - -/* LED definitions **********************************************************/ - -/* The M3 Wildfire has 3 LEDs labeled LED1, LED2 and LED3. - * These LEDs are not used by the NuttX port unless CONFIG_ARCH_LEDS is - * defined. In that case, the usage by the board port is defined in - * include/board.h and src/up_autoleds.c. - * The LEDs are used to encode OS-related events as follows: - */ - - /* LED1 LED2 LED3 */ -#define LED_STARTED 0 /* OFF OFF OFF */ -#define LED_HEAPALLOCATE 1 /* ON OFF OFF */ -#define LED_IRQSENABLED 2 /* OFF ON OFF */ -#define LED_STACKCREATED 3 /* OFF OFF OFF */ - -#define LED_INIRQ 4 /* NC NC ON (momentary) */ -#define LED_SIGNAL 4 /* NC NC ON (momentary) */ -#define LED_ASSERTION 4 /* NC NC ON (momentary) */ -#define LED_PANIC 4 /* NC NC ON (2Hz flashing) */ -#undef LED_IDLE /* Sleep mode indication not supported */ - -/* The M3 Wildfire supports several two user buttons: KEY1 and KEY2 */ - -#define BUTTON_KEY1 0 -#define BUTTON_KEY2 1 -#define NUM_BUTTONS 2 - -#define BUTTON_KEY1_BIT (1 << BUTTON_KEY1) -#define BUTTON_KEY2_BIT (1 << BUTTON_KEY2) - -/* Pin Remapping ************************************************************/ - -/* USB 2.0 - * - * --- ------ -------------- ------------------------------------------------ - * PIN NAME SIGNAL NOTES - * --- ------ -------------- ------------------------------------------------ - * - * 70 PA11 PA11-USBDM USB2.0 - * 71 PA12 PA12-USBDP USB2.0 - * 2 PE3 PE3-USB-M USB2.0 - */ - -/* 2.4" TFT + Touchscreen - * - * --- ------ -------------- ------------------------------------------------ - * PIN NAME SIGNAL NOTES - * --- ------ -------------- ------------------------------------------------ - * - * 30 PA5 PA5-SPI1-SCK 2.4" TFT + Touchscreen, 10Mbit ENC28J60, - * SPI 2M FLASH - * 31 PA6 PA6-SPI1-MISO 2.4" TFT + Touchscreen, 10Mbit ENC28J60, - * SPI 2M FLASH - * 32 PA7 PA7-SPI1-MOSI 2.4" TFT + Touchscreen, 10Mbit ENC28J60, - * SPI 2M FLASH - * 92 PB6 PB6-I2C1-SCL 2.4" TFT + Touchscreen, AT24C02 - * 93 PB7 PB7-I2C1-SDA 2.4" TFT + Touchscreen, AT24C02 - * 81 PD0 PD0-FSMC_D2 2.4" TFT + Touchscreen - * 82 PD1 PD1-FSMC_D3 2.4" TFT + Touchscreen - * 85 PD4 PD4-FSMC_NOE 2.4" TFT + Touchscreen - * 86 PD5 PD5-FSMC_NWE 2.4" TFT + Touchscreen - * 88 PD7 PD7-FSMC_NE1 2.4" TFT + Touchscreen - * 55 PD8 PD8-FSMC_D13 2.4" TFT + Touchscreen - * 56 PD9 PD9-FSMC_D14 2.4" TFT + Touchscreen - * 57 PD10 PD10-FSMC_D15 2.4" TFT + Touchscreen - * 58 PD11 PD11-FSMC_A16 2.4" TFT + Touchscreen - * 60 PD13 PD13-LCD/LIGHT 2.4" TFT + Touchscreen - * 61 PD14 PD14-FSMC_D0 2.4" TFT + Touchscreen - * 62 PD15 PD15-FSMC_D1 2.4" TFT + Touchscreen - * 98 PE1 PE1-FSMC_NBL1 2.4" TFT + Touchscreen, 10Mbit EN28J60 Reset - * 38 PE7 PE7-FSMC_D4 2.4" TFT + Touchscreen - * 39 PE8 PE8-FSMC_D5 2.4" TFT + Touchscreen - * 40 PE9 PE9-FSMC_D6 2.4" TFT + Touchscreen - * 41 PE10 PE10-FSMC_D7 2.4" TFT + Touchscreen - * 42 PE11 PE11-FSMC_D8 2.4" TFT + Touchscreen - * 43 PE12 PE12-FSMC_D9 2.4" TFT + Touchscreen - * 44 PE13 PE13-FSMC_D10 2.4" TFT + Touchscreen - * 45 PE14 PE14-FSMC_D11 2.4" TFT + Touchscreen - * 46 PE15 PE15-FSMC_D12 2.4" TFT + Touchscreen - */ - -#if defined(CONFIG_STM32_SPI1) && defined(CONFIG_STM32_SPI1_REMAP) -# error "SPI1 requires CONFIG_STM32_SPI1_REMAP=n" -#endif - -#if defined(CONFIG_STM32_I2C1) && defined(CONFIG_STM32_I2C1_REMAP) -# error "SPI1 requires CONFIG_STM32_I2C1_REMAP=n" -#endif - -/* AT24C02 - * - * --- ------ -------------- ------------------------------------------------ - * PIN NAME SIGNAL NOTES - * --- ------ -------------- ------------------------------------------------ - * - * 92 PB6 PB6-I2C1-SCL 2.4" TFT + Touchscreen, AT24C02 - * 93 PB7 PB7-I2C1-SDA 2.4" TFT + Touchscreen, AT24C02 - */ - -#if defined(CONFIG_STM32_I2C1) && defined(CONFIG_STM32_I2C1_REMAP) -# error "SPI1 requires CONFIG_STM32_I2C1_REMAP=n" -#endif - -/* Potentiometer/ADC - * - * --- ------ -------------- ------------------------------------------------ - * PIN NAME SIGNAL NOTES - * --- ------ -------------- ------------------------------------------------ - * - * 16 PC1 PC1/ADC123-IN11 Potentiometer (R16) - * 24 PA1 PC1/ADC123-IN1 - */ - -/* USARTs - * - * --- ------ -------------- ------------------------------------------------ - * PIN NAME SIGNAL NOTES - * --- ------ -------------- ------------------------------------------------ - * - * 68 PA9 PA9-US1-TX MAX3232, DB9 D8, - * Requires !CONFIG_STM32_USART1_REMAP - * 69 PA10 PA10-US1-RX MAX3232, DB9 D8, - * Requires !CONFIG_STM32_USART1_REMAP - * 25 PA2 PA2-US2-TX MAX3232, DB9 D7, - * Requires !CONFIG_STM32_USART2_REMAP - * 26 PA3 PA3-US2-RX MAX3232, DB9 D7, - * Requires !CONFIG_STM32_USART2_REMAP - */ - -#if defined(CONFIG_STM32_USART1) && defined(CONFIG_STM32_USART1_REMAP) -# error "USART1 requires CONFIG_STM32_USART1_REMAP=n" -#endif - -#if defined(CONFIG_STM32_USART2) && defined(CONFIG_STM32_USART2_REMAP) -# error "USART2 requires CONFIG_STM32_USART2_REMAP=n" -#endif - -/* 2MBit SPI FLASH - * - * --- ------ -------------- ------------------------------------------------ - * PIN NAME SIGNAL NOTES - * --- ------ -------------- ------------------------------------------------ - * - * 29 PA4 PA4-SPI1-NSS 10Mbit ENC28J60, SPI 2M FLASH - * 30 PA5 PA5-SPI1-SCK 2.4" TFT + Touchscreen, 10Mbit ENC28J60, - * SPI 2M FLASH - * 31 PA6 PA6-SPI1-MISO 2.4" TFT + Touchscreen, 10Mbit ENC28J60, - * SPI 2M FLASH - * 32 PA7 PA7-SPI1-MOSI 2.4" TFT + Touchscreen, 10Mbit ENC28J60, - * SPI 2M FLASH - */ - -#if defined(CONFIG_STM32_SPI1) && defined(CONFIG_STM32_SPI1_REMAP) -# error "SPI1 requires CONFIG_STM32_SPI1_REMAP=n" -#endif - -/* ENC28J60 - * - * --- ------ -------------- ------------------------------------------------ - * PIN NAME SIGNAL NOTES - * --- ------ -------------- ------------------------------------------------ - * - * 29 PA4 PA4-SPI1-NSS 10Mbit ENC28J60, SPI 2M FLASH - * 30 PA5 PA5-SPI1-SCK 2.4" TFT + Touchscreen, 10Mbit ENC28J60, - * SPI 2M FLASH - * 31 PA6 PA6-SPI1-MISO 2.4" TFT + Touchscreen, 10Mbit ENC28J60, - * SPI 2M FLASH - * 32 PA7 PA7-SPI1-MOSI 2.4" TFT + Touchscreen, 10Mbit ENC28J60, - * SPI 2M FLASH - * 98 PE1 PE1-FSMC_NBL1 2.4" TFT + Touchscreen, 10Mbit EN28J60 Reset - * 4 PE5 (no name) 10Mbps ENC28J60 Interrupt - */ - -#if defined(CONFIG_STM32_SPI1) && defined(CONFIG_STM32_SPI1_REMAP) -# error "SPI1 requires CONFIG_STM32_SPI1_REMAP=n" -#endif - -/* MP3 - * - * --- ------ -------------- ------------------------------------------------ - * PIN NAME SIGNAL NOTES - * --- ------ -------------- ------------------------------------------------ - * - * 48 PB11 PB11-MP3-RST MP3 - * 51 PB12 PB12-SPI2-NSS MP3 - * 52 PB13 PB13-SPI2-SCK MP3 - * 53 PB14 PB14-SPI2-MISO MP3 - * 54 PB15 PB15-SPI2-MOSI MP3 - * 63 PC6 PC6-MP3-XDCS MP3 - * 64 PC7 PC7-MP3-DREQ MP3 - */ - -/* SD Card - * - * --- ------ -------------- ------------------------------------------------ - * PIN NAME SIGNAL NOTES - * --- ------ -------------- ------------------------------------------------ - * - * 65 PC8 PC8-SDIO-D0 SD card, pulled high - * 66 PC9 PC9-SDIO-D1 SD card, pulled high - * 78 PC10 PC10-SDIO-D2 SD card, pulled high - * 79 PC11 PC10-SDIO-D3 SD card, pulled high - * 80 PC12 PC12-SDIO-CLK SD card - * 83 PD2 PD2-SDIO-CMD SD card, pulled high - */ - -/* CAN - * - * --- ------ -------------- ------------------------------------------------ - * PIN NAME SIGNAL NOTES - * --- ------ -------------- ------------------------------------------------ - * - * 95 PB8 PB8-CAN-RX CAN transceiver, Header 2H - * 96 PB9 PB9-CAN-TX CAN transceiver, Header 2H - */ - -#if defined(CONFIG_STM32_CAN1) && !defined(CONFIG_STM32_CAN1_REMAP1) -# error "SPI1 requires CONFIG_STM32_CAN1_REMAP1=y" -#endif - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -#ifndef __ASSEMBLY__ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: fire_lcdclear - * - * Description: - * This is a non-standard LCD interface just for the M3 Wildfire board. - * Because of the various rotations, clearing the display in the normal - * way by writing a sequences of runs that covers the entire display can be - * very slow. Here the display is cleared by simply setting all GRAM - * memory to the specified color. - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_FSMC -void fire_lcdclear(uint16_t color); -#endif - -#if defined(__cplusplus) -} -#endif -#undef EXTERN - -#endif /* __ASSEMBLY__ */ - -/* Alternate function pin selections (auto-aliased for new pinmap) */ - -/* USART1 */ - -#define GPIO_USART1_TX GPIO_ADJUST_MODE(GPIO_USART1_TX_0, GPIO_MODE_50MHz) -#define GPIO_USART1_RX GPIO_USART1_RX_0 - -/* USART2 */ - -#define GPIO_USART2_TX GPIO_ADJUST_MODE(GPIO_USART2_TX_0, GPIO_MODE_50MHz) -#define GPIO_USART2_RX GPIO_USART2_RX_0 -#define GPIO_USART2_CTS GPIO_USART2_CTS_0 -#define GPIO_USART2_RTS GPIO_ADJUST_MODE(GPIO_USART2_RTS_0, GPIO_MODE_50MHz) -#define GPIO_USART2_CK GPIO_ADJUST_MODE(GPIO_USART2_CK_0, GPIO_MODE_50MHz) - -/* SPI1 */ - -#define GPIO_SPI1_NSS GPIO_ADJUST_MODE(GPIO_SPI1_NSS_0, GPIO_MODE_50MHz) -#define GPIO_SPI1_SCK GPIO_ADJUST_MODE(GPIO_SPI1_SCK_0, GPIO_MODE_50MHz) -#define GPIO_SPI1_MISO GPIO_ADJUST_MODE(GPIO_SPI1_MISO_0, GPIO_MODE_50MHz) -#define GPIO_SPI1_MOSI GPIO_ADJUST_MODE(GPIO_SPI1_MOSI_0, GPIO_MODE_50MHz) - -/* I2C1 */ - -#define GPIO_I2C1_SCL GPIO_ADJUST_MODE(GPIO_I2C1_SCL_0, GPIO_MODE_50MHz) -#define GPIO_I2C1_SDA GPIO_ADJUST_MODE(GPIO_I2C1_SDA_0, GPIO_MODE_50MHz) - -/* SDIO */ - -#define GPIO_SDIO_CK GPIO_ADJUST_MODE(GPIO_SDIO_CK_0, GPIO_MODE_50MHz) -#define GPIO_SDIO_CMD GPIO_ADJUST_MODE(GPIO_SDIO_CMD_0, GPIO_MODE_50MHz) -#define GPIO_SDIO_D0 GPIO_ADJUST_MODE(GPIO_SDIO_D0_0, GPIO_MODE_50MHz) -#define GPIO_SDIO_D1 GPIO_ADJUST_MODE(GPIO_SDIO_D1_0, GPIO_MODE_50MHz) -#define GPIO_SDIO_D2 GPIO_ADJUST_MODE(GPIO_SDIO_D2_0, GPIO_MODE_50MHz) -#define GPIO_SDIO_D3 GPIO_ADJUST_MODE(GPIO_SDIO_D3_0, GPIO_MODE_50MHz) - -/* USB */ - -#define GPIO_USB_DM GPIO_USB_DM_0 -#define GPIO_USB_DP GPIO_USB_DP_0 - -#endif /* __BOARDS_ARM_STM32_FIRE_STM32V2_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32/fire-stm32v2/scripts/Make.defs b/boards/arm/stm32/fire-stm32v2/scripts/Make.defs deleted file mode 100644 index f51a205edbf4e..0000000000000 --- a/boards/arm/stm32/fire-stm32v2/scripts/Make.defs +++ /dev/null @@ -1,48 +0,0 @@ -############################################################################ -# boards/arm/stm32/fire-stm32v2/scripts/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/.config -include $(TOPDIR)/tools/Config.mk -include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs - -# Pick the linker script - -ifeq ($(CONFIG_STM32_DFU),y) - LDSCRIPT = fire-stm32v2-dfu.ld -else - LDSCRIPT = fire-stm32v2.ld -endif - -ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) - -ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 - -CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) -CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) -CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -AFLAGS := $(CFLAGS) -D__ASSEMBLY__ - -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections -LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32/fire-stm32v2/src/CMakeLists.txt b/boards/arm/stm32/fire-stm32v2/src/CMakeLists.txt deleted file mode 100644 index 8d9a77eabc3ec..0000000000000 --- a/boards/arm/stm32/fire-stm32v2/src/CMakeLists.txt +++ /dev/null @@ -1,59 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/fire-stm32v2/src/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -set(SRCS stm32_boot.c stm32_spi.c stm32_usbdev.c stm32_mmcsd.c) - -if(CONFIG_STM32_FSMC) - list(APPEND SRCS stm32_lcd.c stm32_selectlcd.c) -endif() - -if(CONFIG_ARCH_LEDS) - list(APPEND SRCS stm32_autoleds.c) -else() - list(APPEND SRCS stm32_userleds.c) -endif() - -if(CONFIG_ARCH_BUTTONS) - list(APPEND SRCS stm32_buttons.c) -endif() - -if(CONFIG_ENC28J60) - list(APPEND SRCS stm32_enc28j60.c) -endif() - -if(CONFIG_MTD_W25) - list(APPEND SRCS stm32_w25.c) -endif() - -if(CONFIG_USBMSC) - list(APPEND SRCS stm32_usbmsc.c) -endif() - -target_sources(board PRIVATE ${SRCS}) - -if(CONFIG_STM32_DFU) - set_property(GLOBAL PROPERTY LD_SCRIPT - "${NUTTX_BOARD_DIR}/scripts/fire-stm32v2-dfu.ld") -else() - set_property(GLOBAL PROPERTY LD_SCRIPT - "${NUTTX_BOARD_DIR}/scripts/fire-stm32v2.ld") -endif() diff --git a/boards/arm/stm32/fire-stm32v2/src/Make.defs b/boards/arm/stm32/fire-stm32v2/src/Make.defs deleted file mode 100644 index fdfe1aaa4b39a..0000000000000 --- a/boards/arm/stm32/fire-stm32v2/src/Make.defs +++ /dev/null @@ -1,55 +0,0 @@ -############################################################################ -# boards/arm/stm32/fire-stm32v2/src/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/Make.defs - -CSRCS = stm32_boot.c stm32_spi.c stm32_usbdev.c stm32_mmcsd.c - -ifeq ($(CONFIG_STM32_FSMC),y) -CSRCS += stm32_lcd.c stm32_selectlcd.c -endif - -ifeq ($(CONFIG_ARCH_LEDS),y) -CSRCS += stm32_autoleds.c -else -CSRCS += stm32_userleds.c -endif - -ifeq ($(CONFIG_ARCH_BUTTONS),y) -CSRCS += stm32_buttons.c -endif - -ifeq ($(CONFIG_ENC28J60),y) -CSRCS += stm32_enc28j60.c -endif - -ifeq ($(CONFIG_MTD_W25),y) -CSRCS += stm32_w25.c -endif - -ifeq ($(CONFIG_USBMSC),y) -CSRCS += stm32_usbmsc.c -endif - -DEPPATH += --dep-path board -VPATH += :board -CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/fire-stm32v2/src/stm32_autoleds.c b/boards/arm/stm32/fire-stm32v2/src/stm32_autoleds.c deleted file mode 100644 index 882946b820ace..0000000000000 --- a/boards/arm/stm32/fire-stm32v2/src/stm32_autoleds.c +++ /dev/null @@ -1,359 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/fire-stm32v2/src/stm32_autoleds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32.h" -#include "fire-stm32v2.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* The following definitions map the encoded LED setting to GPIO settings. - * - * OFFBITS ONBITS - * CLR SET CLR SET - * 210 210 210 210 - */ - -#define FIRE_LED1 (1 << 0) -#define FIRE_LED2 (1 << 1) -#define FIRE_LED3 (1 << 2) - -#define ON_SETBITS_SHIFT (0) -#define ON_CLRBITS_SHIFT (3) -#define OFF_SETBITS_SHIFT (6) -#define OFF_CLRBITS_SHIFT (9) - -#define ON_BITS(v) ((v) & 0x3f) -#define OFF_BITS(v) (((v) >> 6) & 0x03f) -#define SETBITS(b) ((b) & 0x07) -#define CLRBITS(b) (((b) >> 3) & 0x07) - -#define ON_SETBITS(v) (SETBITS(ON_BITS(v)) -#define ON_CLRBITS(v) (CLRBITS(ON_BITS(v)) -#define OFF_SETBITS(v) (SETBITS(OFF_BITS(v)) -#define OFF_CLRBITS(v) (CLRBITS(OFF_BITS(v)) - -/* ON OFF - * -------------------------- -- ------------------ ----------------- - * LED1 LED2 LED3 LED1 LED2 LED3 - * -------------------------- -- ------ ----- ----- ----- ----- ----- - * LED_STARTED 0 OFF OFF OFF OFF OFF OFF - * LED_HEAPALLOCATE 1 ON OFF OFF OFF OFF OFF - * LED_IRQSENABLED 2 OFF ON OFF ON OFF OFF - * LED_STACKCREATED 3 OFF OFF OFF OFF ON OFF - * - * LED_INIRQ 4 NC NC ON NC NC OFF - * LED_SIGNAL 4 NC NC ON NC NC OFF - * LED_ASSERTION 4 NC NC ON NC NC OFF - * LED_PANIC 4 NC NC ON NC NC OFF - * -------------------------- -- ------ ----- ----- ----- ----- ----- - */ - -#define LED_STARTED_ON_SETBITS (0) -#define LED_STARTED_ON_CLRBITS ((FIRE_LED1|FIRE_LED2|FIRE_LED3) << ON_CLRBITS_SHIFT) -#define LED_STARTED_OFF_SETBITS (0) -#define LED_STARTED_OFF_CLRBITS ((FIRE_LED1|FIRE_LED2|FIRE_LED3) << OFF_CLRBITS_SHIFT) - -#define LED_HEAPALLOCATE_ON_SETBITS ((FIRE_LED1) << ON_SETBITS_SHIFT) -#define LED_HEAPALLOCATE_ON_CLRBITS ((FIRE_LED2|FIRE_LED3) << ON_CLRBITS_SHIFT) -#define LED_HEAPALLOCATE_OFF_SETBITS (0) -#define LED_HEAPALLOCATE_OFF_CLRBITS ((FIRE_LED1|FIRE_LED2|FIRE_LED3) << OFF_CLRBITS_SHIFT) - -#define LED_IRQSENABLED_ON_SETBITS ((FIRE_LED2) << ON_SETBITS_SHIFT) -#define LED_IRQSENABLED_ON_CLRBITS ((FIRE_LED1|FIRE_LED3) << ON_CLRBITS_SHIFT) -#define LED_IRQSENABLED_OFF_SETBITS ((FIRE_LED1) << OFF_SETBITS_SHIFT) -#define LED_IRQSENABLED_OFF_CLRBITS ((FIRE_LED1|FIRE_LED2|FIRE_LED3) << OFF_CLRBITS_SHIFT) - -#define LED_STACKCREATED_ON_SETBITS (0) -#define LED_STACKCREATED_ON_CLRBITS ((FIRE_LED1|FIRE_LED2|FIRE_LED3) << ON_CLRBITS_SHIFT) -#define LED_STACKCREATED_OFF_SETBITS ((FIRE_LED2) << OFF_SETBITS_SHIFT) -#define LED_STACKCREATED_OFF_CLRBITS ((FIRE_LED1|FIRE_LED3) << OFF_CLRBITS_SHIFT) - -#define LED_FLASH_ON_SETBITS ((FIRE_LED3) << ON_SETBITS_SHIFT) -#define LED_FLASH_ON_CLRBITS ((0) << ON_CLRBITS_SHIFT) -#define LED_FLASH_OFF_SETBITS ((0) << OFF_SETBITS_SHIFT) -#define LED_FLASH_OFF_CLRBITS ((FIRE_LED3) << OFF_CLRBITS_SHIFT) - -/**************************************************************************** - * Private Function Protototypes - ****************************************************************************/ - -/* LED State Controls */ - -static inline void led_clrbits(unsigned int clrbits); -static inline void led_setbits(unsigned int setbits); -static void led_setonoff(unsigned int bits); - -/* LED Power Management */ - -#ifdef CONFIG_PM -static void led_pm_notify(struct pm_callback_s *cb, int domain, - enum pm_state_e pmstate); -static int led_pm_prepare(struct pm_callback_s *cb, int domain, - enum pm_state_e pmstate); -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -static const uint16_t g_ledbits[8] = -{ - (LED_STARTED_ON_SETBITS | LED_STARTED_ON_CLRBITS | - LED_STARTED_OFF_SETBITS | LED_STARTED_OFF_CLRBITS), - - (LED_HEAPALLOCATE_ON_SETBITS | LED_HEAPALLOCATE_ON_CLRBITS | - LED_HEAPALLOCATE_OFF_SETBITS | LED_HEAPALLOCATE_OFF_CLRBITS), - - (LED_IRQSENABLED_ON_SETBITS | LED_IRQSENABLED_ON_CLRBITS | - LED_IRQSENABLED_OFF_SETBITS | LED_IRQSENABLED_OFF_CLRBITS), - - (LED_STACKCREATED_ON_SETBITS | LED_STACKCREATED_ON_CLRBITS | - LED_STACKCREATED_OFF_SETBITS | LED_STACKCREATED_OFF_CLRBITS), - - (LED_FLASH_ON_SETBITS | LED_FLASH_ON_CLRBITS | - LED_FLASH_OFF_SETBITS | LED_FLASH_OFF_CLRBITS) -}; - -#ifdef CONFIG_PM -static struct pm_callback_s g_ledscb = -{ - .notify = led_pm_notify, - .prepare = led_pm_prepare, -}; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: led_clrbits - * - * Description: - * Clear all LEDs to the bit encoded state. The LEDs are pulled up and, - * hence, active low. - * - ****************************************************************************/ - -static inline void led_clrbits(unsigned int clrbits) -{ - if ((clrbits & FIRE_LED1) != 0) - { - stm32_gpiowrite(GPIO_LED1, true); - } - - if ((clrbits & FIRE_LED2) != 0) - { - stm32_gpiowrite(GPIO_LED2, true); - } - - if ((clrbits & FIRE_LED3) != 0) - { - stm32_gpiowrite(GPIO_LED3, true); - } -} - -/**************************************************************************** - * Name: led_setbits - * - * Description: - * Set all LEDs to the bit encoded state. The LEDs are pulled up and, - * hence, active low. - * - ****************************************************************************/ - -static inline void led_setbits(unsigned int setbits) -{ - if ((setbits & FIRE_LED1) != 0) - { - stm32_gpiowrite(GPIO_LED1, false); - } - - if ((setbits & FIRE_LED2) != 0) - { - stm32_gpiowrite(GPIO_LED2, false); - } - - if ((setbits & FIRE_LED3) != 0) - { - stm32_gpiowrite(GPIO_LED3, false); - } -} - -/**************************************************************************** - * Name: led_setonoff - * - * Description: - * Set/clear all LEDs to the bit encoded state - * - ****************************************************************************/ - -static void led_setonoff(unsigned int bits) -{ - led_clrbits(CLRBITS(bits)); - led_setbits(SETBITS(bits)); -} - -/**************************************************************************** - * Name: led_pm_notify - * - * Description: - * Notify the driver of new power state. This callback is called after - * all drivers have had the opportunity to prepare for the new power state. - * - ****************************************************************************/ - -#ifdef CONFIG_PM -static void led_pm_notify(struct pm_callback_s *cb, int domain, - enum pm_state_e pmstate) -{ - switch (pmstate) - { - case PM_NORMAL: - { - /* Restore normal LEDs operation */ - } - break; - - case PM_IDLE: - { - /* Entering IDLE mode - Turn leds off */ - } - break; - - case PM_STANDBY: - { - /* Entering STANDBY mode - Logic for PM_STANDBY goes here */ - } - break; - - case PM_SLEEP: - { - /* Entering SLEEP mode - Logic for PM_SLEEP goes here */ - } - break; - - default: - { - /* Should not get here */ - } - break; - } -} -#endif - -/**************************************************************************** - * Name: led_pm_prepare - * - * Description: - * Request the driver to prepare for a new power state. This is a warning - * that the system is about to enter into a new power state. The driver - * should begin whatever operations that may be required to enter power - * state. The driver may abort the state change mode by returning a - * non-zero value from the callback function. - * - ****************************************************************************/ - -#ifdef CONFIG_PM -static int led_pm_prepare(struct pm_callback_s *cb, int domain, - enum pm_state_e pmstate) -{ - /* No preparation to change power modes is required by the LEDs driver. - * We always accept the state change by returning OK. - */ - - return OK; -} -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_autoled_initialize - ****************************************************************************/ - -#ifdef CONFIG_ARCH_LEDS -void board_autoled_initialize(void) -{ - /* Configure LED1-4 GPIOs for output */ - - stm32_configgpio(GPIO_LED1); - stm32_configgpio(GPIO_LED2); - stm32_configgpio(GPIO_LED3); -} - -/**************************************************************************** - * Name: board_autoled_on - ****************************************************************************/ - -void board_autoled_on(int led) -{ - led_setonoff(ON_BITS(g_ledbits[led])); -} - -/**************************************************************************** - * Name: board_autoled_off - ****************************************************************************/ - -void board_autoled_off(int led) -{ - led_setonoff(OFF_BITS(g_ledbits[led])); -} - -/**************************************************************************** - * Name: up_ledpminitialize - ****************************************************************************/ - -#ifdef CONFIG_PM -void up_ledpminitialize(void) -{ - /* Register to receive power management callbacks */ - - int ret = pm_register(&g_ledscb); - if (ret != OK) - { - board_autoled_on(LED_ASSERTION); - } -} -#endif /* CONFIG_PM */ - -#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/fire-stm32v2/src/stm32_boot.c b/boards/arm/stm32/fire-stm32v2/src/stm32_boot.c deleted file mode 100644 index 9ee669b3fbc53..0000000000000 --- a/boards/arm/stm32/fire-stm32v2/src/stm32_boot.c +++ /dev/null @@ -1,277 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/fire-stm32v2/src/stm32_boot.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include -#include -#include - -#include -#include -#include - -#include "stm32.h" -#include "stm32_i2c.h" -#include "arm_internal.h" -#include "fire-stm32v2.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -/* Assume that we support everything until convinced otherwise */ - -#define HAVE_MMCSD 1 -#define HAVE_USBDEV 1 -#define HAVE_W25 1 - -/* Configuration ************************************************************/ - -/* SPI1 connects to the SD CARD (and to the SPI FLASH) */ - -#define STM32_MMCSDSPIPORTNO 1 /* SPI1 */ -#define STM32_MMCSDSLOTNO 0 /* Only one slot */ - -/* Can't support MMC/SD features if the SDIO peripheral is disabled */ - -#ifndef CONFIG_STM32_SDIO -# undef HAVE_MMCSD -#endif - -/* Can't support MMC/SD features if mountpoints are disabled */ - -#ifdef CONFIG_DISABLE_MOUNTPOINT -# undef HAVE_MMCSD -#endif - -/* Default MMC/SD minor number */ - -#ifdef HAVE_MMCSD -# ifndef CONFIG_NSH_MMCSDMINOR -# define CONFIG_NSH_MMCSDMINOR 0 -# endif - -/* Default MMC/SD SLOT number */ - -# if defined(CONFIG_NSH_MMCSDSLOTNO) && CONFIG_NSH_MMCSDSLOTNO != STM32_MMCSDSLOTNO -# error "Only one MMC/SD slot: Slot 0" -# undef CONFIG_NSH_MMCSDSLOTNO -# define CONFIG_NSH_MMCSDSLOTNO STM32_MMCSDSLOTNO -# endif - -# ifndef CONFIG_NSH_MMCSDSLOTNO -# define CONFIG_NSH_MMCSDSLOTNO STM32_MMCSDSLOTNO -# endif -#endif - -/* Can't support the W25 device if it SPI1 or W25 support is not enabled */ - -#if !defined(CONFIG_STM32_SPI1) || !defined(CONFIG_MTD_W25) -# undef HAVE_W25 -#endif - -/* Can't support W25 features if mountpoints are disabled */ - -#if defined(CONFIG_DISABLE_MOUNTPOINT) -# undef HAVE_W25 -#endif - -/* Default W25 minor number */ - -#if defined(HAVE_W25) && !defined(CONFIG_NSH_W25MINOR) -# define CONFIG_NSH_W25MINOR 0 -#endif - -/* Can't support USB host or device features if the USB peripheral or the USB - * device infrastructure is not enabled - */ - -#if !defined(CONFIG_STM32_USB) || !defined(CONFIG_USBDEV) -# undef HAVE_USBDEV -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_i2c_register - * - * Description: - * Register one I2C drivers for the I2C tool. - * - ****************************************************************************/ - -#ifdef HAVE_I2CTOOL -static void stm32_i2c_register(int bus) -{ - struct i2c_master_s *i2c; - int ret; - - i2c = stm32_i2cbus_initialize(bus); - if (i2c == NULL) - { - _err("ERROR: Failed to get I2C%d interface\n", bus); - } - else - { - ret = i2c_register(i2c, bus); - if (ret < 0) - { - _err("ERROR: Failed to register I2C%d driver: %d\n", bus, ret); - stm32_i2cbus_uninitialize(i2c); - } - } -} -#endif - -/**************************************************************************** - * Name: stm32_i2ctool - * - * Description: - * Register I2C drivers for the I2C tool. - * - ****************************************************************************/ - -#ifdef HAVE_I2CTOOL -static void stm32_i2ctool(void) -{ -#ifdef CONFIG_STM32_I2C1 - stm32_i2c_register(1); -#endif -#ifdef CONFIG_STM32_I2C2 - stm32_i2c_register(2); -#endif -#ifdef CONFIG_STM32_I2C3 - stm32_i2c_register(3); -#endif -} -#else -# define stm32_i2ctool() -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_boardinitialize - * - * Description: - * All STM32 architectures must provide the following entry point. - * This entry point is called early in the initialization -- after all - * memory has been configured and mapped but before any devices have been - * initialized. - * - ****************************************************************************/ - -void stm32_boardinitialize(void) -{ - /* Configure SPI chip selects if 1) SPI is not disabled, and 2) the weak - * function stm32_spidev_initialize() has been brought into the link. - */ - -#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) - if (stm32_spidev_initialize) - { - stm32_spidev_initialize(); - } -#endif - - /* Initialize USB is 1) USBDEV is selected, 2) the USB controller is not - * disabled, and 3) the weak function stm32_usbinitialize() has been - * brought into the build. - */ - -#if defined(CONFIG_USBDEV) && defined(CONFIG_STM32_USB) - if (stm32_usbinitialize) - { - stm32_usbinitialize(); - } -#endif - - /* Configure on-board LEDs if LED support has been selected. */ - -#ifdef CONFIG_ARCH_LEDS - board_autoled_initialize(); -#endif -} - -/**************************************************************************** - * Name: board_late_initialize - * - * Description: - * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional - * initialization call will be performed in the boot-up sequence to a - * function called board_late_initialize(). board_late_initialize() will - * be called immediately after up_initialize() is called and just before - * the initial application is started. This additional initialization - * phase may be used, for example, to initialize board-specific device - * drivers. - * - ****************************************************************************/ - -#ifdef CONFIG_BOARD_LATE_INITIALIZE -void board_late_initialize(void) -{ -#if defined(HAVE_MMCSD) || defined(HAVE_W25) - int ret; -#endif - - /* Register I2C drivers on behalf of the I2C tool */ - - stm32_i2ctool(); - -#ifdef HAVE_W25 - /* Initialize and register the W25 FLASH file system. */ - - ret = stm32_w25initialize(CONFIG_NSH_W25MINOR); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: Failed to initialize W25 minor %d: %d\n", - CONFIG_NSH_W25MINOR, ret); - return; - } -#endif - -#ifdef HAVE_MMCSD - /* Initialize the SDIO-based MMC/SD slot */ - - ret = stm32_sdinitialize(CONFIG_NSH_MMCSDMINOR); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: Failed to initialize MMC/SD slot %d: %d\n", - CONFIG_NSH_MMCSDSLOTNO, ret); - return; - } -#endif -} -#endif diff --git a/boards/arm/stm32/fire-stm32v2/src/stm32_buttons.c b/boards/arm/stm32/fire-stm32v2/src/stm32_buttons.c deleted file mode 100644 index 735bda0f2fd80..0000000000000 --- a/boards/arm/stm32/fire-stm32v2/src/stm32_buttons.c +++ /dev/null @@ -1,148 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/fire-stm32v2/src/stm32_buttons.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include -#include - -#include "fire-stm32v2.h" - -#ifdef CONFIG_ARCH_BUTTONS - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_button_initialize - * - * Description: - * board_button_initialize() must be called to initialize button resources. - * After that, board_buttons() may be called to collect the current state - * of all buttons or board_button_irq() may be called to register button - * interrupt handlers. - * - ****************************************************************************/ - -uint32_t board_button_initialize(void) -{ - /* Configure the GPIO pins as inputs. NOTE that EXTI interrupts are - * configured for some pins but NOT used in this file - */ - - stm32_configgpio(GPIO_BTN_KEY1); - stm32_configgpio(GPIO_BTN_KEY2); - return NUM_BUTTONS; -} - -/**************************************************************************** - * Name: board_buttons - ****************************************************************************/ - -uint32_t board_buttons(void) -{ - uint32_t ret = 0; - - /* Check that state of each key. - * A LOW value means that the key is pressed. - */ - - if (!stm32_gpioread(GPIO_BTN_KEY1)) - { - ret |= BUTTON_KEY1_BIT; - } - - if (!stm32_gpioread(GPIO_BTN_KEY2)) - { - ret |= BUTTON_KEY2_BIT; - } - - return ret; -} - -/**************************************************************************** - * Button support. - * - * Description: - * board_button_initialize() must be called to initialize button resources. - * After that, board_buttons() may be called to collect the current state - * of all buttons or board_button_irq() may be called to register button - * interrupt handlers. - * - * After board_button_initialize() has been called, board_buttons() may be - * called to collect the state of all buttons. board_buttons() returns an - * 32-bit bit set with each bit associated with a button. See the - * BUTTON_*_BIT and JOYSTICK_*_BIT definitions in board.h for the meaning - * of each bit. - * - * board_button_irq() may be called to register an interrupt handler that - * will be called when a button is depressed or released. The ID value is a - * button enumeration value that uniquely identifies a button resource. See - * the BUTTON_* and JOYSTICK_* definitions in board.h for the meaning of - * enumeration values. - * - ****************************************************************************/ - -#ifdef CONFIG_ARCH_IRQBUTTONS -int board_button_irq(int id, xcpt_t irqhandler, void *arg) -{ - uint16_t gpio; - int ret; - - if (id == BUTTON_KEY1) - { - gpio = GPIO_KEY1; - } - else if (id == BUTTON_KEY2) - { - gpio = GPIO_KEY2; - } - else - { - return -EINVAL; - } - - return stm32_gpiosetevent(gpio, true, true, true, irqhandler, arg); -} -#endif -#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/stm32/fire-stm32v2/src/stm32_enc28j60.c b/boards/arm/stm32/fire-stm32v2/src/stm32_enc28j60.c deleted file mode 100644 index de824d6ad02b2..0000000000000 --- a/boards/arm/stm32/fire-stm32v2/src/stm32_enc28j60.c +++ /dev/null @@ -1,222 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/fire-stm32v2/src/stm32_enc28j60.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* 2MBit SPI FLASH OR ENC28J60 - * - * --- ------ -------------- ------------------------------------------------ - * PIN NAME SIGNAL NOTES - * --- ------ -------------- ------------------------------------------------ - * - * 29 PA4 PA4-SPI1-NSS 10Mbit ENC28J60, SPI 2M FLASH - * 30 PA5 PA5-SPI1-SCK 2.4" TFT + Touchscreen, 10Mbit ENC28J60, - * SPI 2M FLASH - * 31 PA6 PA6-SPI1-MISO 2.4" TFT + Touchscreen, 10Mbit ENC28J60, - * SPI 2M FLASH - * 32 PA7 PA7-SPI1-MOSI 2.4" TFT + Touchscreen, 10Mbit ENC28J60, - * SPI 2M FLASH - */ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include - -#include -#include - -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32_spi.h" - -#include "fire-stm32v2.h" - -#ifdef CONFIG_ENC28J60 - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -/* ENC28J60 - * - * --- ------ -------------- ------------------------------------------------ - * PIN NAME SIGNAL NOTES - * --- ------ -------------- ------------------------------------------------ - * - * 29 PA4 PA4-SPI1-NSS 10Mbit ENC28J60, SPI 2M FLASH - * 30 PA5 PA5-SPI1-SCK 2.4" TFT + Touchscreen, 10Mbit ENC28J60, - * SPI 2M FLASH - * 31 PA6 PA6-SPI1-MISO 2.4" TFT + Touchscreen, 10Mbit ENC28J60, - * SPI 2M FLASH - * 32 PA7 PA7-SPI1-MOSI 2.4" TFT + Touchscreen, 10Mbit ENC28J60, - * SPI 2M FLASH - * 98 PE1 PE1-FSMC_NBL1 2.4" TFT + Touchscreen, 10Mbit EN28J60 Reset - * 4 PE5 (no name) 10Mbps ENC28J60 Interrupt - */ - -/* ENC28J60 is on SPI1 */ - -#ifndef CONFIG_STM32_SPI1 -# error "Need CONFIG_STM32_SPI1 in the configuration" -#endif - -/* SPI Assumptions **********************************************************/ - -#define ENC28J60_SPI_PORTNO 1 /* On SPI1 */ -#define ENC28J60_DEVNO 0 /* Only one ENC28J60 */ - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -struct stm32_lower_s -{ - const struct enc_lower_s lower; /* Low-level MCU interface */ - xcpt_t handler; /* ENC28J60 interrupt handler */ - void *arg; /* Argument that accompanies the interrupt */ -}; - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -static int up_attach(const struct enc_lower_s *lower, xcpt_t handler, - void *arg); -static void up_enable(const struct enc_lower_s *lower); -static void up_disable(const struct enc_lower_s *lower); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* The ENC28J60 normal provides interrupts to the MCU via a GPIO pin. The - * following structure provides an MCU-independent mechanixm for controlling - * the ENC28J60 GPIO interrupt. - */ - -static struct stm32_lower_s g_enclower = -{ - .lower = - { - .attach = up_attach, - .enable = up_enable, - .disable = up_disable - }, - .handler = NULL, - .arg = NULL -}; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: struct enc_lower_s methods - ****************************************************************************/ - -static int up_attach(const struct enc_lower_s *lower, xcpt_t handler, - void *arg) -{ - struct stm32_lower_s *priv = (struct stm32_lower_s *)lower; - - /* Just save the handler for use when the interrupt is enabled */ - - priv->handler = handler; - priv->arg = arg; - return OK; -} - -static void up_enable(const struct enc_lower_s *lower) -{ - struct stm32_lower_s *priv = (struct stm32_lower_s *)lower; - - DEBUGASSERT(priv->handler); - stm32_gpiosetevent(GPIO_ENC28J60_INTR, false, true, true, - priv->handler, priv->arg); -} - -/* REVISIT: Since the interrupt is completely torn down, not just disabled, - * in interrupt requests that occurs while the interrupt is disabled will be - * lost. - */ - -static void up_disable(const struct enc_lower_s *lower) -{ - stm32_gpiosetevent(GPIO_ENC28J60_INTR, false, true, true, - NULL, NULL); -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: arm_netinitialize - ****************************************************************************/ - -void arm_netinitialize(void) -{ - struct spi_dev_s *spi; - int ret; - - /* Assumptions: - * 1) ENC28J60 pins were configured in up_spi.c early in the boot-up phase. - * 2) Clocking for the SPI1 peripheral was also provided earlier in - * boot-up. - */ - - spi = stm32_spibus_initialize(ENC28J60_SPI_PORTNO); - if (!spi) - { - nerr("ERROR: Failed to initialize SPI port %d\n", - ENC28J60_SPI_PORTNO); - return; - } - - /* Take ENC28J60 out of reset (active low) */ - - stm32_gpiowrite(GPIO_ENC28J60_RESET, true); - - /* Bind the SPI port to the ENC28J60 driver */ - - ret = enc_initialize(spi, &g_enclower.lower, ENC28J60_DEVNO); - if (ret < 0) - { - nerr("ERROR: Failed to bind SPI port %d ENC28J60 device %d: %d\n", - ENC28J60_SPI_PORTNO, ENC28J60_DEVNO, ret); - return; - } - - ninfo("Bound SPI port %d to ENC28J60 device %d\n", - ENC28J60_SPI_PORTNO, ENC28J60_DEVNO); -} - -#endif /* CONFIG_ENC28J60 */ diff --git a/boards/arm/stm32/fire-stm32v2/src/stm32_mmcsd.c b/boards/arm/stm32/fire-stm32v2/src/stm32_mmcsd.c deleted file mode 100644 index 5b800a06600ec..0000000000000 --- a/boards/arm/stm32/fire-stm32v2/src/stm32_mmcsd.c +++ /dev/null @@ -1,111 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/fire-stm32v2/src/stm32_mmcsd.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include "stm32_sdio.h" -#include "fire-stm32v2.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -#define HAVE_MMCSD 1 /* Assume that we have SD support */ -#define STM32_MMCSDSLOTNO 0 /* There is only one slot */ - -/* Can't support MMC/SD features if the SDIO peripheral is disabled */ - -#ifndef CONFIG_STM32_SDIO -# undef HAVE_MMCSD -#endif - -/* Can't support MMC/SD features if mountpoints are disabled */ - -#ifdef CONFIG_DISABLE_MOUNTPOINT -# undef HAVE_MMCSD -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_sdinitialize - * - * Description: - * Initialize the SPI-based SD card. Requires CONFIG_DISABLE_MOUNTPOINT=n - * and CONFIG_STM32_SDIO=y - * - ****************************************************************************/ - -int stm32_sdinitialize(int minor) -{ -#ifdef HAVE_MMCSD - struct sdio_dev_s *sdio; - int ret; - - /* First, get an instance of the SDIO interface */ - - sdio = sdio_initialize(STM32_MMCSDSLOTNO); - if (!sdio) - { - ferr("ERROR: Failed to initialize SDIO slot %d\n", STM32_MMCSDSLOTNO); - return -ENODEV; - } - - finfo("Initialized SDIO slot %d\n", STM32_MMCSDSLOTNO); - - /* Now bind the SDIO interface to the MMC/SD driver */ - - ret = mmcsd_slotinitialize(minor, sdio); - if (ret != OK) - { - ferr("ERROR:"); - ferr(" Failed to bind SDIO slot %d to the MMC/SD driver, minor=%d\n", - STM32_MMCSDSLOTNO, minor); - } - - finfo("Bound SDIO slot %d to the MMC/SD driver, minor=%d\n", - STM32_MMCSDSLOTNO, minor); - - /* Then let's guess and say that there is a card in the slot. - * I need to check to see if the M3 Wildfire board supports a GPIO to - * detect if there is a card in the slot. - */ - - sdio_mediachange(sdio, true); -#endif - return OK; -} diff --git a/boards/arm/stm32/fire-stm32v2/src/stm32_selectlcd.c b/boards/arm/stm32/fire-stm32v2/src/stm32_selectlcd.c deleted file mode 100644 index a1654527d2317..0000000000000 --- a/boards/arm/stm32/fire-stm32v2/src/stm32_selectlcd.c +++ /dev/null @@ -1,182 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/fire-stm32v2/src/stm32_selectlcd.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32_gpio.h" -#include "stm32.h" -#include "fire-stm32v2.h" - -#ifdef CONFIG_STM32_FSMC - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#ifndef CONFIG_STM32_FSMC -# warning "FSMC is not enabled" -#endif - -#if STM32_NGPIO_PORTS < 6 -# error "Required GPIO ports not enabled" -#endif - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/* 2.4" TFT + Touchscreen. FSMC Bank1 - * - * --- ------ -------------- ------------------------------------------------ - * PIN NAME SIGNAL NOTES - * --- ------ -------------- ------------------------------------------------ - * - * 30 PA5 PA5-SPI1-SCK 2.4" TFT + Touchscreen, 10Mbit ENC28J60, - * SPI 2M FLASH - * 31 PA6 PA6-SPI1-MISO 2.4" TFT + Touchscreen, 10Mbit ENC28J60, - * SPI 2M FLASH - * 32 PA7 PA7-SPI1-MOSI 2.4" TFT + Touchscreen, 10Mbit ENC28J60, - * SPI 2M FLASH - * 92 PB6 PB6-I2C1-SCL 2.4" TFT + Touchscreen, AT24C02 - * 93 PB7 PB7-I2C1-SDA 2.4" TFT + Touchscreen, AT24C02 - * 81 PD0 PD0-FSMC_D2 2.4" TFT + Touchscreen - * 82 PD1 PD1-FSMC_D3 2.4" TFT + Touchscreen - * 85 PD4 PD4-FSMC_NOE 2.4" TFT + Touchscreen - * 86 PD5 PD5-FSMC_NWE 2.4" TFT + Touchscreen - * 88 PD7 PD7-FSMC_NE1 2.4" TFT + Touchscreen - * 55 PD8 PD8-FSMC_D13 2.4" TFT + Touchscreen - * 56 PD9 PD9-FSMC_D14 2.4" TFT + Touchscreen - * 57 PD10 PD10-FSMC_D15 2.4" TFT + Touchscreen - * 58 PD11 PD11-FSMC_A16 2.4" TFT + Touchscreen - * 60 PD13 PD13-LCD/LIGHT 2.4" TFT + Touchscreen - * 61 PD14 PD14-FSMC_D0 2.4" TFT + Touchscreen - * 62 PD15 PD15-FSMC_D1 2.4" TFT + Touchscreen - * 98 PE1 PE1-FSMC_NBL1 2.4" TFT + Touchscreen - * 38 PE7 PE7-FSMC_D4 2.4" TFT + Touchscreen - * 39 PE8 PE8-FSMC_D5 2.4" TFT + Touchscreen - * 40 PE9 PE9-FSMC_D6 2.4" TFT + Touchscreen - * 41 PE10 PE10-FSMC_D7 2.4" TFT + Touchscreen - * 42 PE11 PE11-FSMC_D8 2.4" TFT + Touchscreen - * 43 PE12 PE12-FSMC_D9 2.4" TFT + Touchscreen - * 44 PE13 PE13-FSMC_D10 2.4" TFT + Touchscreen - * 45 PE14 PE14-FSMC_D11 2.4" TFT + Touchscreen - * 46 PE15 PE15-FSMC_D12 2.4" TFT + Touchscreen - * - * NOTE: - * SPI and I2C pin configuration is controlled in the SPI and I2C drivers, - * respectively. - */ - -static const uint16_t g_lcdconfig[NCOMMON_CONFIG] = -{ - /* Address Lines: A16 only */ - - GPIO_NPS_A16, - - /* Data Lines: D0... D15 */ - - GPIO_NPS_D0, GPIO_NPS_D1, GPIO_NPS_D2, GPIO_NPS_D3, - GPIO_NPS_D4, GPIO_NPS_D5, GPIO_NPS_D6, GPIO_NPS_D7, - GPIO_NPS_D8, GPIO_NPS_D9, GPIO_NPS_D10, GPIO_NPS_D11, - GPIO_NPS_D12, GPIO_NPS_D13, GPIO_NPS_D14, GPIO_NPS_D15, - - /* NOE, NWE, NE1, NBL1 */ - - GPIO_NPS_NOE, GPIO_NPS_NWE, GPIO_NPS_NE1, GPIO_NPS_NBL1, - - /* Backlight GPIO */ - - GPIO_LCD_BACKLIGHT -}; -#define NLCD_CONFIG (sizeof(g_lcdconfig) / sizeof(uint16_t)) - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_selectlcd - * - * Description: - * Initialize to the LCD pin configuration. - * - ****************************************************************************/ - -void stm32_selectlcd(void) -{ - irqstate_t flags; - int i; - - /* Configure LCD GPIO pis */ - - flags = enter_critical_section(); - for (i = 0; i < NLCD_GPIOS; i++) - { - stm32_configgpio(g_lcdconfig[i]); - } - - /* Enable AHB clocking to the FSMC */ - - stm32_fsmc_enable(); - - /* Bank1 NOR/SRAM control register configuration */ - - putreg32(FSMC_BCR_SRAM | FSMC_BCR_MWID16 | FSMC_BCR_WREN, STM32_FSMC_BCR1); - - /* Bank1 NOR/SRAM timing register configuration */ - - putreg32(FSMC_BTR_ADDSET(1) | FSMC_BTR_ADDHLD(1) | - FSMC_BTR_DATAST(2) | FSMC_BTR_BUSTURN(1) | - FSMC_BTR_CLKDIV(1) | FSMC_BTR_DATLAT(2) | - FSMC_BTR_ACCMODA, STM32_FSMC_BTR1); - - putreg32(0xffffffff, STM32_FSMC_BWTR4); - - /* Enable the bank by setting the MBKEN bit */ - - putreg32(FSMC_BCR_MBKEN | FSMC_BCR_SRAM | - FSMC_BCR_MWID16 | FSMC_BCR_WREN, STM32_FSMC_BCR1); - leave_critical_section(flags); -} - -#endif /* CONFIG_STM32_FSMC */ diff --git a/boards/arm/stm32/fire-stm32v2/src/stm32_spi.c b/boards/arm/stm32/fire-stm32v2/src/stm32_spi.c deleted file mode 100644 index 309d8d175decb..0000000000000 --- a/boards/arm/stm32/fire-stm32v2/src/stm32_spi.c +++ /dev/null @@ -1,181 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/fire-stm32v2/src/stm32_spi.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include "arm_internal.h" -#include "chip.h" -#include "stm32.h" -#include "fire-stm32v2.h" - -#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_spidev_initialize - * - * Description: - * Called to configure SPI chip select GPIO pins for the M3 Wildfire board. - * - ****************************************************************************/ - -void weak_function stm32_spidev_initialize(void) -{ - /* NOTE: Clocking for SPI1 and/or SPI2 was already provided in stm32_rcc.c. - * Configurations of SPI pins is performed in stm32_spi.c. - * Here, we only initialize chip select pins unique to the board - * architecture. - */ - -#ifdef CONFIG_STM32_SPI1 - /* Configure the TFT/Touchscreen CS GPIO */ - -#if 0 /* Need to study this */ - stm32_configgpio(GPIO_LCD_CS); -#endif - - /* Configure the TFT/Touchscreen and ENC28J60 or SPI-based FLASH PIOs */ - - /* Configure ENC28J60 SPI1 CS (also RESET and interrupt pins) */ - -#ifdef CONFIG_ENC28J60 - stm32_configgpio(GPIO_ENC28J60_CS); - stm32_configgpio(GPIO_ENC28J60_RESET); - stm32_configgpio(GPIO_ENC28J60_INTR); -#else - - /* Configure FLASH SPI1 CS */ - - stm32_configgpio(GPIO_FLASH_CS); -#endif - -#endif /* CONFIG_STM32_SPI1 */ - -#ifdef CONFIG_STM32_SPI2 - /* Configure the MP3 SPI2 CS GPIO */ - - stm32_configgpio(GPIO_MP3_CS); - -#endif /* CONFIG_STM32_SPI2 */ -} - -/**************************************************************************** - * Name: stm32_spi1/2/3select and stm32_spi1/2/3status - * - * Description: - * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status - * must be provided by board-specific logic. They are implementations of - * the select and status methods of the SPI interface defined by struct - * spi_ops_s (see include/nuttx/spi/spi.h). All other methods - * (including stm32_spibus_initialize()) are provided by common STM32 - * logic. To use this common SPI logic on your board: - * - * 1. Provide logic in stm32_boardinitialize() to configure SPI chip select - * pins. - * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() functions - * in your board-specific logic. These functions will perform chip - * selection and status operations using GPIOs in the way your board is - * configured. - * 3. Add a calls to stm32_spibus_initialize() in your low level - * application initialization logic - * 4. The handle returned by stm32_spibus_initialize() may then be used to - * bind the SPI driver to higher level logic (e.g., calling - * mmcsd_spislotinitialize(), for example, will bind the SPI driver to - * the SPI MMC/SD driver). - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_SPI1 -void stm32_spi1select(struct spi_dev_s *dev, - uint32_t devid, bool selected) -{ - spiinfo("devid: %d CS: %s\n", - (int)devid, selected ? "assert" : "de-assert"); - -#if 0 /* Need to study this */ - if (devid == SPIDEV_LCD) - { - /* Set the GPIO low to select and high to de-select */ - - stm32_gpiowrite(GPIO_LCD_CS, !selected); - } - else -#endif -#ifdef CONFIG_ENC28J60 - if (devid == SPIDEV_ETHERNET(0)) - { - /* Set the GPIO low to select and high to de-select */ - - stm32_gpiowrite(GPIO_ENC28J60_CS, !selected); - } -#else - if (devid == SPIDEV_FLASH(0)) - { - /* Set the GPIO low to select and high to de-select */ - - stm32_gpiowrite(GPIO_FLASH_CS, !selected); - } -#endif -} - -uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) -{ - return SPI_STATUS_PRESENT; -} -#endif - -#ifdef CONFIG_STM32_SPI2 -void stm32_spi2select(struct spi_dev_s *dev, - uint32_t devid, bool selected) -{ - spiinfo("devid: %d CS: %s\n", - (int)devid, selected ? "assert" : "de-assert"); - - if (devid == SPIDEV_AUDIO) - { - /* Set the GPIO low to select and high to de-select */ - - stm32_gpiowrite(GPIO_MP3_CS, !selected); - } -} - -uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) -{ - return SPI_STATUS_PRESENT; -} -#endif - -#endif /* CONFIG_STM32_SPI1 || CONFIG_STM32_SPI2 */ diff --git a/boards/arm/stm32/fire-stm32v2/src/stm32_usbdev.c b/boards/arm/stm32/fire-stm32v2/src/stm32_usbdev.c deleted file mode 100644 index 4d592165ae870..0000000000000 --- a/boards/arm/stm32/fire-stm32v2/src/stm32_usbdev.c +++ /dev/null @@ -1,107 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/fire-stm32v2/src/stm32_usbdev.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include - -#include -#include - -#include "arm_internal.h" -#include "stm32.h" -#include "fire-stm32v2.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_usbinitialize - * - * Description: - * Called to setup USB-related GPIO pins for the M3 Wildfire board. - * - ****************************************************************************/ - -void stm32_usbinitialize(void) -{ - /* USB Soft Connect Pullup */ - -#if 0 /* REVISIT */ - stm32_configgpio(GPIO_USB_PULLUP); -#endif -} - -/**************************************************************************** - * Name: stm32_usbpullup - * - * Description: - * If USB is supported and the board supports a pullup via GPIO (for USB - * software connect and disconnect), then the board software must provide - * stm32_pullup. See include/nuttx/usb/usbdev.h for additional description - * of this method. - * Alternatively, if no pull-up GPIO the following EXTERN can be redefined - * to be NULL. - * - ****************************************************************************/ - -int stm32_usbpullup(struct usbdev_s *dev, bool enable) -{ - usbtrace(TRACE_DEVPULLUP, (uint16_t)enable); -#if 0 /* REVISIT */ - stm32_gpiowrite(GPIO_USB_PULLUP, !enable); -#endif - return OK; -} - -/**************************************************************************** - * Name: stm32_usbsuspend - * - * Description: - * Board logic must provide the stm32_usbsuspend logic if the USBDEV driver - * is used. This function is called whenever the USB enters or leaves - * suspend mode. - * This is an opportunity for the board logic to shutdown clocks, power, - * etc. while the USB is suspended. - * - ****************************************************************************/ - -void stm32_usbsuspend(struct usbdev_s *dev, bool resume) -{ - uinfo("resume: %d\n", resume); -} diff --git a/boards/arm/stm32/fire-stm32v2/src/stm32_usbmsc.c b/boards/arm/stm32/fire-stm32v2/src/stm32_usbmsc.c deleted file mode 100644 index dd87c605e78da..0000000000000 --- a/boards/arm/stm32/fire-stm32v2/src/stm32_usbmsc.c +++ /dev/null @@ -1,71 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/fire-stm32v2/src/stm32_usbmsc.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include - -#include "stm32.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -#ifndef CONFIG_SYSTEM_USBMSC_DEVMINOR1 -# define CONFIG_SYSTEM_USBMSC_DEVMINOR1 0 -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_usbmsc_initialize - * - * Description: - * Perform architecture specific initialization of the USB MSC device. - * - ****************************************************************************/ - -int board_usbmsc_initialize(int port) -{ - /* If system/usbmsc is built as an NSH command, then SD slot should - * already have been initialized. - * In this case, there is nothing further to be done here. - */ - -#ifndef CONFIG_NSH_BUILTIN_APPS - return stm32_sdinitialize(CONFIG_SYSTEM_USBMSC_DEVMINOR1); -#else - return OK; -#endif -} diff --git a/boards/arm/stm32/fire-stm32v2/src/stm32_userleds.c b/boards/arm/stm32/fire-stm32v2/src/stm32_userleds.c deleted file mode 100644 index 15f5e2506f711..0000000000000 --- a/boards/arm/stm32/fire-stm32v2/src/stm32_userleds.c +++ /dev/null @@ -1,104 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/fire-stm32v2/src/stm32_userleds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32.h" -#include "fire-stm32v2.h" - -#ifndef CONFIG_ARCH_LEDS - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* This array maps an LED number to GPIO pin configuration */ - -static uint32_t g_ledcfg[BOARD_NLEDS] = -{ - GPIO_LED1, GPIO_LED2, GPIO_LED3 -}; - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_userled_initialize - ****************************************************************************/ - -uint32_t board_userled_initialize(void) -{ - /* Configure LED1-4 GPIOs for output */ - - stm32_configgpio(GPIO_LED1); - stm32_configgpio(GPIO_LED2); - stm32_configgpio(GPIO_LED3); - return 3; -} - -/**************************************************************************** - * Name: board_userled - * - * Description: - * Set one LED to the 'ledon' state. The LEDs are pulled up and, hence, - * active low. - * - ****************************************************************************/ - -void board_userled(int led, bool ledon) -{ - if ((unsigned)led < BOARD_NLEDS) - { - stm32_gpiowrite(g_ledcfg[led], !ledon); - } -} - -/**************************************************************************** - * Name: board_userled_all - * - * Description: - * Set each LED to the bit encoded state. The LEDs are pulled up and, - * hence, active low. - * - ****************************************************************************/ - -void board_userled_all(uint32_t ledset) -{ - stm32_gpiowrite(GPIO_LED1, (ledset & BOARD_LED1_BIT) == 0); - stm32_gpiowrite(GPIO_LED2, (ledset & BOARD_LED2_BIT) == 0); - stm32_gpiowrite(GPIO_LED3, (ledset & BOARD_LED3_BIT) == 0); -} - -#endif /* !CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/fire-stm32v2/src/stm32_w25.c b/boards/arm/stm32/fire-stm32v2/src/stm32_w25.c deleted file mode 100644 index 3dd694251ba43..0000000000000 --- a/boards/arm/stm32/fire-stm32v2/src/stm32_w25.c +++ /dev/null @@ -1,144 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/fire-stm32v2/src/stm32_w25.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include - -#ifdef CONFIG_STM32_SPI1 -# include -# include -# include -# include -#endif - -#include "stm32_spi.h" -#include "fire-stm32v2.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -/* Can't support the W25 device if it SPI1 or W25 support is not enabled */ - -#define HAVE_W25 1 -#if !defined(CONFIG_STM32_SPI1) || !defined(CONFIG_MTD_W25) -# undef HAVE_W25 -#endif - -/* Can't support W25 features if mountpoints are disabled */ - -#if defined(CONFIG_DISABLE_MOUNTPOINT) -# undef HAVE_W25 -#endif - -/* Can't support both FAT and NXFFS */ - -#if defined(CONFIG_FS_FAT) && defined(CONFIG_FS_NXFFS) -# warning "Can't support both FAT and NXFFS -- using FAT" -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_w25initialize - * - * Description: - * Initialize and register the W25 FLASH file system. - * - ****************************************************************************/ - -int stm32_w25initialize(int minor) -{ -#ifdef HAVE_W25 - struct spi_dev_s *spi; - struct mtd_dev_s *mtd; -#ifdef CONFIG_FS_NXFFS - char devname[12]; -#endif - int ret; - - /* Get the SPI port */ - - spi = stm32_spibus_initialize(1); - if (!spi) - { - ferr("ERROR: Failed to initialize SPI port 2\n"); - return -ENODEV; - } - - /* Now bind the SPI interface to the W25 SPI FLASH driver */ - - mtd = w25_initialize(spi); - if (!mtd) - { - ferr("ERROR: Failed to bind SPI port 2 to the SST 25 FLASH driver\n"); - return -ENODEV; - } - -#ifndef CONFIG_FS_NXFFS - /* Register the MTD driver */ - - char path[32]; - snprintf(path, sizeof(path), "/dev/mtdblock%d", minor); - ret = register_mtddriver(path, mtd, 0755, NULL); - if (ret < 0) - { - ferr("ERROR: Failed to register the MTD driver %s, ret %d\n", - path, ret); - return ret; - } -#else - /* Initialize to provide NXFFS on the MTD interface */ - - ret = nxffs_initialize(mtd); - if (ret < 0) - { - ferr("ERROR: NXFFS initialization failed: %d\n", -ret); - return ret; - } - - /* Mount the file system at /mnt/w25 */ - - snprintf(devname, sizeof(devname), "/mnt/w25%c", 'a' + minor); - ret = nx_mount(NULL, devname, "nxffs", 0, NULL); - if (ret < 0) - { - ferr("ERROR: Failed to mount the NXFFS volume: %d\n", ret); - return ret; - } -#endif -#endif - - return OK; -} diff --git a/boards/arm/stm32/hymini-stm32v/CMakeLists.txt b/boards/arm/stm32/hymini-stm32v/CMakeLists.txt deleted file mode 100644 index 7cc2354980b45..0000000000000 --- a/boards/arm/stm32/hymini-stm32v/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/hymini-stm32v/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32/hymini-stm32v/configs/nsh/defconfig b/boards/arm/stm32/hymini-stm32v/configs/nsh/defconfig deleted file mode 100644 index 46a47095c31e1..0000000000000 --- a/boards/arm/stm32/hymini-stm32v/configs/nsh/defconfig +++ /dev/null @@ -1,47 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_NSH_DISABLE_IFCONFIG is not set -# CONFIG_NSH_DISABLE_PS is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="hymini-stm32v" -CONFIG_ARCH_BOARD_HYMINI_STM32V=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F103VC=y -CONFIG_ARCH_IRQBUTTONS=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BINFMT_DISABLE=y -CONFIG_BOARD_LOOPSPERMSEC=5483 -CONFIG_FAT_LCNAMES=y -CONFIG_FS_FAT=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_MMCSD=y -CONFIG_MMCSD_SDIO=y -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=49152 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_HPWORKPRIORITY=192 -CONFIG_SCHED_HPWORKSTACKSIZE=1024 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=5 -CONFIG_START_MONTH=7 -CONFIG_START_YEAR=2011 -CONFIG_STM32_BKP=y -CONFIG_STM32_DMA2=y -CONFIG_STM32_PWR=y -CONFIG_STM32_SDIO=y -CONFIG_STM32_USART1=y -CONFIG_SYMTAB_ORDEREDBYNAME=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/hymini-stm32v/configs/nsh2/defconfig b/boards/arm/stm32/hymini-stm32v/configs/nsh2/defconfig deleted file mode 100644 index 07770b9836be2..0000000000000 --- a/boards/arm/stm32/hymini-stm32v/configs/nsh2/defconfig +++ /dev/null @@ -1,90 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_MMCSD_MMCSUPPORT is not set -# CONFIG_NSH_DISABLE_IFCONFIG is not set -# CONFIG_NSH_DISABLE_PS is not set -# CONFIG_NXFONTS_DISABLE_16BPP is not set -# CONFIG_NX_DISABLE_16BPP is not set -# CONFIG_NX_PACKEDMSFIRST is not set -# CONFIG_SPI_CALLBACK is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="hymini-stm32v" -CONFIG_ARCH_BOARD_HYMINI_STM32V=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F103VC=y -CONFIG_ARCH_IRQBUTTONS=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=5483 -CONFIG_BUILTIN=y -CONFIG_EXAMPLES_NX=y -CONFIG_EXAMPLES_NXHELLO=y -CONFIG_EXAMPLES_NXHELLO_BPP=16 -CONFIG_EXAMPLES_NXIMAGE=y -CONFIG_EXAMPLES_NXIMAGE_BPP=16 -CONFIG_EXAMPLES_NX_BPP=16 -CONFIG_EXAMPLES_TOUCHSCREEN=y -CONFIG_FAT_LCNAMES=y -CONFIG_FAT_LFN=y -CONFIG_FS_FAT=y -CONFIG_FS_FATTIME=y -CONFIG_FS_ROMFS=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INPUT=y -CONFIG_INPUT_ADS7843E=y -CONFIG_LCD=y -CONFIG_LCD_MAXCONTRAST=1 -CONFIG_LCD_MAXPOWER=100 -CONFIG_LCD_SSD1289=y -CONFIG_MMCSD=y -CONFIG_MMCSD_SDIO=y -CONFIG_MQ_MAXMSGSIZE=64 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_READLINE=y -CONFIG_NX=y -CONFIG_NXFONT_SANS23X27=y -CONFIG_NXFONT_SANS28X37B=y -CONFIG_NX_BLOCKING=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=49152 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_HPWORKPRIORITY=192 -CONFIG_SCHED_HPWORKSTACKSIZE=1024 -CONFIG_SCHED_WAITPID=y -CONFIG_SSD1289_PROFILE2=y -CONFIG_STM32_BKP=y -CONFIG_STM32_DMA2=y -CONFIG_STM32_FSMC=y -CONFIG_STM32_PWR=y -CONFIG_STM32_RTC=y -CONFIG_STM32_SDIO=y -CONFIG_STM32_SPI1=y -CONFIG_STM32_TIM3=y -CONFIG_STM32_TIM3_PARTIAL_REMAP=y -CONFIG_STM32_USART1=y -CONFIG_STM32_USB=y -CONFIG_SYMTAB_ORDEREDBYNAME=y -CONFIG_SYSTEM_NSH=y -CONFIG_SYSTEM_USBMSC=y -CONFIG_SYSTEM_USBMSC_DEVMINOR1=0 -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART1_SERIAL_CONSOLE=y -CONFIG_USBDEV_TRACE=y -CONFIG_USBMSC=y -CONFIG_USBMSC_BULKINREQLEN=256 -CONFIG_USBMSC_BULKOUTREQLEN=256 -CONFIG_USBMSC_EPBULKIN=5 -CONFIG_USBMSC_NRDREQS=2 -CONFIG_USBMSC_NWRREQS=2 -CONFIG_USBMSC_PRODUCTSTR="USBdev Storage" -CONFIG_USBMSC_REMOVABLE=y -CONFIG_USBMSC_VERSIONNO=0x0399 diff --git a/boards/arm/stm32/hymini-stm32v/configs/usbmsc/defconfig b/boards/arm/stm32/hymini-stm32v/configs/usbmsc/defconfig deleted file mode 100644 index 429596080a6e9..0000000000000 --- a/boards/arm/stm32/hymini-stm32v/configs/usbmsc/defconfig +++ /dev/null @@ -1,52 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_MMCSD_HAVE_CARDDETECT is not set -# CONFIG_MMCSD_MMCSUPPORT is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="hymini-stm32v" -CONFIG_ARCH_BOARD_HYMINI_STM32V=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F103VC=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARDCTL=y -CONFIG_BOARD_LOOPSPERMSEC=5483 -CONFIG_INIT_ENTRYPOINT="msconn_main" -CONFIG_MMCSD=y -CONFIG_MMCSD_SDIO=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=49152 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_HPWORKPRIORITY=192 -CONFIG_SCHED_HPWORKSTACKSIZE=1024 -CONFIG_START_DAY=30 -CONFIG_START_MONTH=11 -CONFIG_START_YEAR=2009 -CONFIG_STM32_DMA2=y -CONFIG_STM32_FSMC=y -CONFIG_STM32_SDIO=y -CONFIG_STM32_USART1=y -CONFIG_STM32_USART2=y -CONFIG_STM32_USB=y -CONFIG_SYMTAB_ORDEREDBYNAME=y -CONFIG_SYSTEM_USBMSC=y -CONFIG_SYSTEM_USBMSC_DEVMINOR1=0 -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART1_SERIAL_CONSOLE=y -CONFIG_USBMSC=y -CONFIG_USBMSC_BULKINREQLEN=256 -CONFIG_USBMSC_BULKOUTREQLEN=256 -CONFIG_USBMSC_EPBULKIN=5 -CONFIG_USBMSC_NRDREQS=2 -CONFIG_USBMSC_NWRREQS=2 -CONFIG_USBMSC_PRODUCTSTR="USBdev Storage" -CONFIG_USBMSC_REMOVABLE=y -CONFIG_USBMSC_VERSIONNO=0x0399 diff --git a/boards/arm/stm32/hymini-stm32v/configs/usbnsh/defconfig b/boards/arm/stm32/hymini-stm32v/configs/usbnsh/defconfig deleted file mode 100644 index 73800aa8adfc4..0000000000000 --- a/boards/arm/stm32/hymini-stm32v/configs/usbnsh/defconfig +++ /dev/null @@ -1,48 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_NSH_DISABLE_IFCONFIG is not set -# CONFIG_NSH_DISABLE_PS is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="hymini-stm32v" -CONFIG_ARCH_BOARD_HYMINI_STM32V=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F103VC=y -CONFIG_ARCH_IRQBUTTONS=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BINFMT_DISABLE=y -CONFIG_BOARDCTL_USBDEVCTRL=y -CONFIG_BOARD_LOOPSPERMSEC=5483 -CONFIG_CDCACM=y -CONFIG_CDCACM_CONSOLE=y -CONFIG_CDCACM_RXBUFSIZE=256 -CONFIG_CDCACM_TXBUFSIZE=256 -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=49152 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_HPWORKPRIORITY=192 -CONFIG_SCHED_HPWORKSTACKSIZE=1024 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=5 -CONFIG_START_MONTH=7 -CONFIG_START_YEAR=2011 -CONFIG_STM32_BKP=y -CONFIG_STM32_PWR=y -CONFIG_STM32_USART1=y -CONFIG_STM32_USB=y -CONFIG_SYMTAB_ORDEREDBYNAME=y -CONFIG_SYSLOG_CHAR=y -CONFIG_SYSLOG_DEVPATH="/dev/ttyS0" -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 diff --git a/boards/arm/stm32/hymini-stm32v/configs/usbserial/defconfig b/boards/arm/stm32/hymini-stm32v/configs/usbserial/defconfig deleted file mode 100644 index 7f6da595e2a9e..0000000000000 --- a/boards/arm/stm32/hymini-stm32v/configs/usbserial/defconfig +++ /dev/null @@ -1,36 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="hymini-stm32v" -CONFIG_ARCH_BOARD_HYMINI_STM32V=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F103VC=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARDCTL=y -CONFIG_BOARD_LOOPSPERMSEC=5483 -CONFIG_DISABLE_MOUNTPOINT=y -CONFIG_EXAMPLES_USBSERIAL=y -CONFIG_INIT_ENTRYPOINT="usbserial_main" -CONFIG_PL2303=y -CONFIG_PL2303_PRODUCTSTR="USBdev Serial" -CONFIG_PL2303_RXBUFSIZE=512 -CONFIG_PL2303_TXBUFSIZE=512 -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=49152 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_START_DAY=23 -CONFIG_START_MONTH=10 -CONFIG_START_YEAR=2009 -CONFIG_STM32_USART1=y -CONFIG_STM32_USART2=y -CONFIG_STM32_USB=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/hymini-stm32v/include/board.h b/boards/arm/stm32/hymini-stm32v/include/board.h deleted file mode 100644 index 9fae5bdda94af..0000000000000 --- a/boards/arm/stm32/hymini-stm32v/include/board.h +++ /dev/null @@ -1,242 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/hymini-stm32v/include/board.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __BOARDS_ARM_STM32_HYMINI_STM32V_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32_HYMINI_STM32V_INCLUDE_BOARD_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Clocking *****************************************************************/ - -/* On-board crystal frequency is 8MHz (HSE) */ - -#define STM32_BOARD_XTAL 8000000ul - -/* PLL source is HSE/1, PLL multiplier is 9: - * PLL frequency is 8MHz (XTAL) x 9 = 72MHz - */ - -#define STM32_CFGR_PLLSRC RCC_CFGR_PLLSRC -#define STM32_CFGR_PLLXTPRE 0 -#define STM32_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx9 -#define STM32_PLL_FREQUENCY (9*STM32_BOARD_XTAL) - -/* Use the PLL and set the SYSCLK source to be the PLL */ - -#define STM32_SYSCLK_SW RCC_CFGR_SW_PLL -#define STM32_SYSCLK_SWS RCC_CFGR_SWS_PLL -#define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY - -/* AHB clock (HCLK) is SYSCLK (72MHz) */ - -#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK -#define STM32_HCLK_FREQUENCY STM32_PLL_FREQUENCY - -/* APB2 clock (PCLK2) is HCLK (72MHz) */ - -#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK -#define STM32_PCLK2_FREQUENCY STM32_HCLK_FREQUENCY - -/* APB2 timers 1 and 8 will receive PCLK2. */ - -#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) - -/* APB1 clock (PCLK1) is HCLK/2 (36MHz) */ - -#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd2 -#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/2) - -/* APB1 timers 2-7 will be twice PCLK1 */ - -#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) - -/* USB divider -- Divide PLL clock by 1.5 */ - -#define STM32_CFGR_USBPRE 0 - -/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx - * otherwise frequency is 2xAPBx. - * Note: TIM1,8 are on APB2, others on APB1 - */ - -#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM2_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM3_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM4_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM5_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM6_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM7_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY - -/* SDIO dividers. Note that slower clocking is required when DMA is disabled - * in order to avoid RX overrun/TX underrun errors due to delayed responses - * to service FIFOs in interrupt driven mode. These values have not been - * tuned!!! - * - * HCLK=72MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(178+2)=400 KHz - */ - -#define SDIO_INIT_CLKDIV (178 << SDIO_CLKCR_CLKDIV_SHIFT) - -/* DMA ON: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(2+2)=18 MHz - * DMA OFF: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(3+2)=14.4 MHz - */ - -#ifdef CONFIG_STM32_SDIO_DMA -# define SDIO_MMCXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT) -#else -# define SDIO_MMCXFR_CLKDIV (3 << SDIO_CLKCR_CLKDIV_SHIFT) -#endif - -/* DMA ON: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(1+2)=24 MHz - * DMA OFF: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(3+2)=14.4 MHz - */ - -#ifdef CONFIG_STM32_SDIO_DMA -# define SDIO_SDXFR_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT) -#else -# define SDIO_SDXFR_CLKDIV (3 << SDIO_CLKCR_CLKDIV_SHIFT) -#endif - -/* LED definitions **********************************************************/ - -/* The board has 2 LEDs that we will encode as: */ -#define LED_STARTED 0 /* No LEDs */ -#define LED_HEAPALLOCATE 1 /* LED1 on */ -#define LED_IRQSENABLED 2 /* LED2 on */ -#define LED_STACKCREATED 3 /* LED1 on */ -#define LED_INIRQ 4 /* LED1 off */ -#define LED_SIGNAL 5 /* LED2 on */ -#define LED_ASSERTION 6 /* LED1 + LED2 */ -#define LED_PANIC 7 /* LED1 / LED2 blinking */ - -/* The board supports two user buttons - * - * KeyA -- Connected to PC.13 - * KeyB -- Connected to PB.2 - */ - -#define BUTTON_KEYA 0 -#define BUTTON_KEYB 1 - -#define NUM_BUTTONS 2 - -#define BUTTON_KEYA_BIT (1 << BUTTON_KEYA) -#define BUTTON_KEYB_BIT (1 << BUTTON_KEYB) - -/* Alternate function pin selections (auto-aliased for new pinmap) */ - -/* USART1 */ - -#define GPIO_USART1_TX GPIO_ADJUST_MODE(GPIO_USART1_TX_0, GPIO_MODE_50MHz) -#define GPIO_USART1_RX GPIO_USART1_RX_0 - -/* USART2 */ - -#define GPIO_USART2_TX GPIO_ADJUST_MODE(GPIO_USART2_TX_0, GPIO_MODE_50MHz) -#define GPIO_USART2_RX GPIO_USART2_RX_0 -#define GPIO_USART2_CTS GPIO_USART2_CTS_0 -#define GPIO_USART2_RTS GPIO_ADJUST_MODE(GPIO_USART2_RTS_0, GPIO_MODE_50MHz) -#define GPIO_USART2_CK GPIO_ADJUST_MODE(GPIO_USART2_CK_0, GPIO_MODE_50MHz) - -/* SPI1 */ - -#define GPIO_SPI1_NSS GPIO_ADJUST_MODE(GPIO_SPI1_NSS_0, GPIO_MODE_50MHz) -#define GPIO_SPI1_SCK GPIO_ADJUST_MODE(GPIO_SPI1_SCK_0, GPIO_MODE_50MHz) -#define GPIO_SPI1_MISO GPIO_ADJUST_MODE(GPIO_SPI1_MISO_0, GPIO_MODE_50MHz) -#define GPIO_SPI1_MOSI GPIO_ADJUST_MODE(GPIO_SPI1_MOSI_0, GPIO_MODE_50MHz) - -/* USB */ - -#define GPIO_USB_DM GPIO_USB_DM_0 -#define GPIO_USB_DP GPIO_USB_DP_0 - -/* SDIO */ - -#define GPIO_SDIO_CK GPIO_ADJUST_MODE(GPIO_SDIO_CK_0, GPIO_MODE_50MHz) -#define GPIO_SDIO_CMD GPIO_ADJUST_MODE(GPIO_SDIO_CMD_0, GPIO_MODE_50MHz) -#define GPIO_SDIO_D0 GPIO_ADJUST_MODE(GPIO_SDIO_D0_0, GPIO_MODE_50MHz) -#define GPIO_SDIO_D1 GPIO_ADJUST_MODE(GPIO_SDIO_D1_0, GPIO_MODE_50MHz) -#define GPIO_SDIO_D2 GPIO_ADJUST_MODE(GPIO_SDIO_D2_0, GPIO_MODE_50MHz) -#define GPIO_SDIO_D3 GPIO_ADJUST_MODE(GPIO_SDIO_D3_0, GPIO_MODE_50MHz) - -/* TIM3 */ - -#define GPIO_TIM3_CH1IN GPIO_TIM3_CH1IN_0 -#define GPIO_TIM3_CH1OUT GPIO_ADJUST_MODE(GPIO_TIM3_CH1OUT_0, GPIO_MODE_50MHz) -#define GPIO_TIM3_CH2IN GPIO_TIM3_CH2IN_0 -#define GPIO_TIM3_CH2OUT GPIO_ADJUST_MODE(GPIO_TIM3_CH2OUT_0, GPIO_MODE_50MHz) -#define GPIO_TIM3_CH3IN GPIO_TIM3_CH3IN_0 -#define GPIO_TIM3_CH3OUT GPIO_ADJUST_MODE(GPIO_TIM3_CH3OUT_0, GPIO_MODE_50MHz) -#define GPIO_TIM3_CH4IN GPIO_TIM3_CH4IN_0 -#define GPIO_TIM3_CH4OUT GPIO_ADJUST_MODE(GPIO_TIM3_CH4OUT_0, GPIO_MODE_50MHz) - -/* FSMC NPS_A address pins (used by LCD srcs) */ - -#define GPIO_NPS_A16 GPIO_ADJUST_MODE(GPIO_NPS_A16_0, GPIO_MODE_50MHz) -#define GPIO_NPS_A17 GPIO_ADJUST_MODE(GPIO_NPS_A17_0, GPIO_MODE_50MHz) -#define GPIO_NPS_A18 GPIO_ADJUST_MODE(GPIO_NPS_A18_0, GPIO_MODE_50MHz) -#define GPIO_NPS_A19 GPIO_ADJUST_MODE(GPIO_NPS_A19_0, GPIO_MODE_50MHz) -#define GPIO_NPS_A20 GPIO_ADJUST_MODE(GPIO_NPS_A20_0, GPIO_MODE_50MHz) -#define GPIO_NPS_A21 GPIO_ADJUST_MODE(GPIO_NPS_A21_0, GPIO_MODE_50MHz) -#define GPIO_NPS_A22 GPIO_ADJUST_MODE(GPIO_NPS_A22_0, GPIO_MODE_50MHz) -#define GPIO_NPS_A23 GPIO_ADJUST_MODE(GPIO_NPS_A23_0, GPIO_MODE_50MHz) -#define GPIO_NPS_A24 GPIO_ADJUST_MODE(GPIO_NPS_A24_0, GPIO_MODE_50MHz) -#define GPIO_NPS_A25 GPIO_ADJUST_MODE(GPIO_NPS_A25_0, GPIO_MODE_50MHz) - -/* FSMC NPS_D pins (used by LCD srcs) */ - -#define GPIO_NPS_D0 GPIO_ADJUST_MODE(GPIO_NPS_D0_0, GPIO_MODE_50MHz) -#define GPIO_NPS_D1 GPIO_ADJUST_MODE(GPIO_NPS_D1_0, GPIO_MODE_50MHz) -#define GPIO_NPS_D10 GPIO_ADJUST_MODE(GPIO_NPS_D10_0, GPIO_MODE_50MHz) -#define GPIO_NPS_D11 GPIO_ADJUST_MODE(GPIO_NPS_D11_0, GPIO_MODE_50MHz) -#define GPIO_NPS_D12 GPIO_ADJUST_MODE(GPIO_NPS_D12_0, GPIO_MODE_50MHz) -#define GPIO_NPS_D13 GPIO_ADJUST_MODE(GPIO_NPS_D13_0, GPIO_MODE_50MHz) -#define GPIO_NPS_D14 GPIO_ADJUST_MODE(GPIO_NPS_D14_0, GPIO_MODE_50MHz) -#define GPIO_NPS_D15 GPIO_ADJUST_MODE(GPIO_NPS_D15_0, GPIO_MODE_50MHz) -#define GPIO_NPS_D2 GPIO_ADJUST_MODE(GPIO_NPS_D2_0, GPIO_MODE_50MHz) -#define GPIO_NPS_D3 GPIO_ADJUST_MODE(GPIO_NPS_D3_0, GPIO_MODE_50MHz) -#define GPIO_NPS_D4 GPIO_ADJUST_MODE(GPIO_NPS_D4_0, GPIO_MODE_50MHz) -#define GPIO_NPS_D5 GPIO_ADJUST_MODE(GPIO_NPS_D5_0, GPIO_MODE_50MHz) -#define GPIO_NPS_D6 GPIO_ADJUST_MODE(GPIO_NPS_D6_0, GPIO_MODE_50MHz) -#define GPIO_NPS_D7 GPIO_ADJUST_MODE(GPIO_NPS_D7_0, GPIO_MODE_50MHz) -#define GPIO_NPS_D8 GPIO_ADJUST_MODE(GPIO_NPS_D8_0, GPIO_MODE_50MHz) -#define GPIO_NPS_D9 GPIO_ADJUST_MODE(GPIO_NPS_D9_0, GPIO_MODE_50MHz) -#define GPIO_NPS_NE1 GPIO_ADJUST_MODE(GPIO_NPS_NE1_0, GPIO_MODE_50MHz) -#define GPIO_NPS_NOE GPIO_ADJUST_MODE(GPIO_NPS_NOE_0, GPIO_MODE_50MHz) -#define GPIO_NPS_NWE GPIO_ADJUST_MODE(GPIO_NPS_NWE_0, GPIO_MODE_50MHz) - -#endif /* __BOARDS_ARM_STM32_HYMINI_STM32V_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32/hymini-stm32v/scripts/Make.defs b/boards/arm/stm32/hymini-stm32v/scripts/Make.defs deleted file mode 100644 index 40a135bea3b15..0000000000000 --- a/boards/arm/stm32/hymini-stm32v/scripts/Make.defs +++ /dev/null @@ -1,46 +0,0 @@ -############################################################################ -# boards/arm/stm32/hymini-stm32v/scripts/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/.config -include $(TOPDIR)/tools/Config.mk -include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs - -ifeq ($(CONFIG_STM32_DFU),y) - LDSCRIPT = ld.script.dfu -else - LDSCRIPT = ld.script -endif - -ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) - -ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 - -CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) -CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) -CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -AFLAGS := $(CFLAGS) -D__ASSEMBLY__ - -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections -LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32/hymini-stm32v/scripts/ld.script b/boards/arm/stm32/hymini-stm32v/scripts/ld.script deleted file mode 100644 index 0f1cc348f8a99..0000000000000 --- a/boards/arm/stm32/hymini-stm32v/scripts/ld.script +++ /dev/null @@ -1,122 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/hymini-stm32v/scripts/ld.script - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* The STM32F103VCT6 has 256Kb of FLASH beginning at address 0x0800:0000 and - * 48Kb of SRAM beginning at address 0x2000:0000. When booting from FLASH, - * FLASH memory is aliased to address 0x0000:0000 where the code expects to - * begin execution by jumping to the entry point in the 0x0800:0000 address - * range. - */ - -MEMORY -{ - flash (rx) : ORIGIN = 0x08000000, LENGTH = 256K - sram (rwx) : ORIGIN = 0x20000000, LENGTH = 48K -} - -OUTPUT_ARCH(arm) -EXTERN(_vectors) -ENTRY(_stext) -SECTIONS -{ - .text : { - _stext = ABSOLUTE(.); - *(.vectors) - *(.text .text.*) - *(.fixup) - *(.gnu.warning) - *(.rodata .rodata.*) - *(.gnu.linkonce.t.*) - *(.glue_7) - *(.glue_7t) - *(.got) - *(.gcc_except_table) - *(.gnu.linkonce.r.*) - _etext = ABSOLUTE(.); - } > flash - - .init_section : ALIGN(4) { - _sinit = ABSOLUTE(.); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) - KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) - _einit = ABSOLUTE(.); - } > flash - - .ARM.extab : ALIGN(4) { - *(.ARM.extab*) - } > flash - - .ARM.exidx : ALIGN(4) { - __exidx_start = ABSOLUTE(.); - *(.ARM.exidx*) - __exidx_end = ABSOLUTE(.); - } > flash - - .tdata : { - _stdata = ABSOLUTE(.); - *(.tdata .tdata.* .gnu.linkonce.td.*); - _etdata = ABSOLUTE(.); - } > flash - - .tbss : { - _stbss = ABSOLUTE(.); - *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); - _etbss = ABSOLUTE(.); - } > flash - - _eronly = ABSOLUTE(.); - - /* The STM32F103VCT6 has 48Kb of SRAM beginning at the following address */ - - .data : ALIGN(4) { - _sdata = ABSOLUTE(.); - *(.data .data.*) - *(.gnu.linkonce.d.*) - CONSTRUCTORS - . = ALIGN(4); - _edata = ABSOLUTE(.); - } > sram AT > flash - - .bss : ALIGN(4) { - _sbss = ABSOLUTE(.); - *(.bss .bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - . = ALIGN(4); - _ebss = ABSOLUTE(.); - } > sram - - /* Stabs debugging sections. */ - - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_info 0 : { *(.debug_info) } - .debug_line 0 : { *(.debug_line) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_aranges 0 : { *(.debug_aranges) } -} diff --git a/boards/arm/stm32/hymini-stm32v/src/CMakeLists.txt b/boards/arm/stm32/hymini-stm32v/src/CMakeLists.txt deleted file mode 100644 index e31d5a0ca4c72..0000000000000 --- a/boards/arm/stm32/hymini-stm32v/src/CMakeLists.txt +++ /dev/null @@ -1,43 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/hymini-stm32v/src/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -set(SRCS stm32_boot.c stm32_leds.c stm32_buttons.c stm32_spi.c stm32_usbdev.c) - -if(CONFIG_LCD_SSD1289) - list(APPEND SRCS stm32_ssd1289.c) -else() - if(CONFIG_LCD_R61505U) - list(APPEND SRCS stm32_r61505u.c) - endif() -endif() - -if(CONFIG_INPUT) - list(APPEND SRCS stm32_ts.c) -endif() - -if(CONFIG_USBMSC) - list(APPEND SRCS stm32_usbmsc.c) -endif() - -target_sources(board PRIVATE ${SRCS}) - -set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/ld.script") diff --git a/boards/arm/stm32/hymini-stm32v/src/Make.defs b/boards/arm/stm32/hymini-stm32v/src/Make.defs deleted file mode 100644 index d96eeceb4ada9..0000000000000 --- a/boards/arm/stm32/hymini-stm32v/src/Make.defs +++ /dev/null @@ -1,45 +0,0 @@ -############################################################################ -# boards/arm/stm32/hymini-stm32v/src/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/Make.defs - -CSRCS = stm32_boot.c stm32_leds.c stm32_buttons.c stm32_spi.c stm32_usbdev.c - -ifeq ($(CONFIG_LCD_SSD1289),y) -CSRCS += stm32_ssd1289.c -else -ifeq ($(CONFIG_LCD_R61505U),y) -CSRCS += stm32_r61505u.c -endif -endif - -ifeq ($(CONFIG_INPUT),y) -CSRCS += stm32_ts.c -endif - -ifeq ($(CONFIG_USBMSC),y) -CSRCS += stm32_usbmsc.c -endif - -DEPPATH += --dep-path board -VPATH += :board -CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/hymini-stm32v/src/stm32_boot.c b/boards/arm/stm32/hymini-stm32v/src/stm32_boot.c deleted file mode 100644 index 755f41cf03999..0000000000000 --- a/boards/arm/stm32/hymini-stm32v/src/stm32_boot.c +++ /dev/null @@ -1,264 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/hymini-stm32v/src/stm32_boot.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include - -#include - -#include -#include -#include - -#include - -#ifdef CONFIG_STM32_SPI1 -# include -# include -#endif - -#ifdef CONFIG_STM32_SDIO -# include -# include -#endif - -#include "arm_internal.h" -#include "stm32.h" -#include "hymini-stm32v.h" - -#include /* Should always be included last due to dependencies */ - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -/* For now, don't build in any SPI1 support -- NSH is not using it */ - -#undef CONFIG_STM32_SPI1 - -/* Check if we can have USB device in NSH */ - -#define NSH_HAVEUSBDEV 1 - -/* Can't support USB features if USB is not enabled */ - -#ifndef CONFIG_USBDEV -# undef NSH_HAVEUSBDEV -#endif - -/* Check if we can have MMC/SD slot support in NSH */ - -#define NSH_HAVEMMCSD 1 - -/* Can't support MMC/SD features if mountpoints are disabled or if SDIO - * support is not enabled. - */ - -#if defined(CONFIG_DISABLE_MOUNTPOINT) || !defined(CONFIG_STM32_SDIO) -# undef NSH_HAVEMMCSD -#endif - -#ifdef NSH_HAVEMMCSD -# ifndef CONFIG_NSH_MMCSDMINOR -# define CONFIG_NSH_MMCSDMINOR 0 -# endif -# if defined(CONFIG_NSH_MMCSDSLOTNO) && CONFIG_NSH_MMCSDSLOTNO != 0 -# error "Only one MMC/SD slot" -# undef CONFIG_NSH_MMCSDSLOTNO -# endif -# ifndef CONFIG_NSH_MMCSDSLOTNO -# define CONFIG_NSH_MMCSDSLOTNO 0 -# endif -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -#ifdef CONFIG_MMCSD -static struct sdio_dev_s *g_sdiodev; -static bool g_sd_inserted; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: nsh_cdinterrupt - * - * Description: - * Card detect interrupt handler. - * - ****************************************************************************/ - -#ifdef NSH_HAVEMMCSD -static int nsh_cdinterrupt(int irq, void *context, void *arg) -{ - bool present; - - present = !stm32_gpioread(GPIO_SD_CD); - if (present != g_sd_inserted) - { - sdio_mediachange(g_sdiodev, present); - g_sd_inserted = present; - } - - return OK; -} -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_boardinitialize - * - * Description: - * All STM32 architectures must provide the following entry point. This - * entry point is called early in the initialization -- after all memory - * has been configured and mapped but before any devices have been - * initialized. - * - ****************************************************************************/ - -void stm32_boardinitialize(void) -{ - /* Configure SPI chip selects if - * 1) SPI is not disabled, and - * 2) the weak function stm32_spidev_initialize() has been brought into - * the link. - */ - -#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) - if (stm32_spidev_initialize) - { - stm32_spidev_initialize(); - } -#endif - - /* Initialize USB is 1) USBDEV is selected, 2) the USB controller is not - * disabled, and 3) the weak function stm32_usbinitialize() has been - * brought into the build. - */ - -#if defined(CONFIG_USBDEV) && defined(CONFIG_STM32_USB) - if (stm32_usbinitialize) - { - stm32_usbinitialize(); - } -#endif - - /* Configure on-board LEDs if LED support has been selected. */ - -#ifdef CONFIG_ARCH_LEDS - board_autoled_initialize(); -#endif -} - -/**************************************************************************** - * Name: board_late_initialize - * - * Description: - * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional - * initialization call will be performed in the boot-up sequence to a - * function called board_late_initialize(). board_late_initialize() will - * be called immediately after up_initialize() is called and just before - * the initial application is started. This additional initialization - * phase may be used, for example, to initialize board-specific device - * drivers. - * - ****************************************************************************/ - -#ifdef CONFIG_BOARD_LATE_INITIALIZE -void board_late_initialize(void) -{ - int ret; - -#ifdef NSH_HAVEMMCSD - /* Configure the card detect GPIO */ - - stm32_configgpio(GPIO_SD_CD); - - /* Register an interrupt handler for the card detect pin */ - - stm32_gpiosetevent(GPIO_SD_CD, true, true, true, nsh_cdinterrupt, NULL); - - /* Mount the SDIO-based MMC/SD block driver */ - - /* First, get an instance of the SDIO interface */ - - syslog(LOG_INFO, "Initializing SDIO slot %d\n", - CONFIG_NSH_MMCSDSLOTNO); - - g_sdiodev = sdio_initialize(CONFIG_NSH_MMCSDSLOTNO); - if (!g_sdiodev) - { - syslog(LOG_ERR, "ERROR: Failed to initialize SDIO slot %d\n", - CONFIG_NSH_MMCSDSLOTNO); - return; - } - - /* Now bind the SDIO interface to the MMC/SD driver */ - - syslog(LOG_INFO, "Bind SDIO to the MMC/SD driver, minor=%d\n", - CONFIG_NSH_MMCSDMINOR); - - ret = mmcsd_slotinitialize(CONFIG_NSH_MMCSDMINOR, g_sdiodev); - if (ret != OK) - { - syslog(LOG_ERR, - "ERROR: Failed to bind SDIO to the MMC/SD driver: %d\n", - ret); - return; - } - - syslog(LOG_INFO, "Successfully bound SDIO to the MMC/SD driver\n"); - - /* Use SD card detect pin to check if a card is inserted */ - - g_sd_inserted = !stm32_gpioread(GPIO_SD_CD); - _info("Card detect : %hhu\n", g_sd_inserted); - - sdio_mediachange(g_sdiodev, g_sd_inserted); -#endif - -#ifdef CONFIG_INPUT - /* Initialize the touchscreen */ - - ret = stm32_tsc_setup(0); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_tsc_setup failed: %d\n", ret); - } -#endif - - UNUSED(ret); -} -#endif diff --git a/boards/arm/stm32/hymini-stm32v/src/stm32_buttons.c b/boards/arm/stm32/hymini-stm32v/src/stm32_buttons.c deleted file mode 100644 index dccdff634d9ce..0000000000000 --- a/boards/arm/stm32/hymini-stm32v/src/stm32_buttons.c +++ /dev/null @@ -1,140 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/hymini-stm32v/src/stm32_buttons.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include - -#include "stm32_gpio.h" -#include "hymini-stm32v.h" - -#ifdef CONFIG_ARCH_BUTTONS - -#include /* Should always be included last due to dependencies */ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_button_initialize - * - * Description: - * board_button_initialize() must be called to initialize button resources. - * After that, board_buttons() may be called to collect the current state - * of all buttons or board_button_irq() may be called to register button - * interrupt handlers. - * - ****************************************************************************/ - -uint32_t board_button_initialize(void) -{ - stm32_configgpio(GPIO_BTN_KEYA); - stm32_configgpio(GPIO_BTN_KEYB); - return NUM_BUTTONS; -} - -/**************************************************************************** - * Name: board_buttons - ****************************************************************************/ - -uint32_t board_buttons(void) -{ - uint32_t ret = 0; - bool value; - - /* Check that state of each key */ - - /* Pin is pulled up */ - - value = stm32_gpioread(GPIO_BTN_KEYA); - if (!value) - { - /* Button pressed */ - - ret = 1 << BUTTON_KEYA; - } - - /* Pin is pulled down */ - - value = stm32_gpioread(GPIO_BTN_KEYB); - if (value) - { - /* Button pressed */ - - ret |= 1 << BUTTON_KEYB; - } - - return ret; -} - -/**************************************************************************** - * Button support. - * - * Description: - * board_button_initialize() must be called to initialize button resources. - * After that, board_buttons() may be called to collect the current state - * of all buttons or board_button_irq() may be called to register button - * interrupt handlers. - * - * After board_button_initialize() has been called, board_buttons() may be - * called to collect the state of all buttons. board_buttons() returns an - * 32-bit bit set with each bit associated with a button. See the - * BUTTON_*_BIT and JOYSTICK_*_BIT definitions in board.h for the meaning - * of each bit. - * - * board_button_irq() may be called to register an interrupt handler that - * will be called when a button is depressed or released. The ID value is a - * button enumeration value that uniquely identifies a button resource. See - * the BUTTON_* definitions in board.h for the meaning of enumeration - * value. - * - ****************************************************************************/ - -#ifdef CONFIG_ARCH_IRQBUTTONS -int board_button_irq(int id, xcpt_t irqhandler, void *arg) -{ - uint32_t pinset = GPIO_BTN_KEYA; - int ret = -EINVAL; - - if (id == 1) - { - pinset = GPIO_BTN_KEYB; - } - - if (id < 2) - { - ret = stm32_gpiosetevent(pinset, true, true, true, irqhandler, arg); - } - - return ret; -} -#endif -#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/stm32/hymini-stm32v/src/stm32_leds.c b/boards/arm/stm32/hymini-stm32v/src/stm32_leds.c deleted file mode 100644 index f54f78f99ed01..0000000000000 --- a/boards/arm/stm32/hymini-stm32v/src/stm32_leds.c +++ /dev/null @@ -1,224 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/hymini-stm32v/src/stm32_leds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32.h" -#include "hymini-stm32v.h" - -#include /* Should always be included last due to dependencies */ - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* The following definitions map the encoded LED setting to GPIO settings */ - -#define HYMINI_STM32_LED1 (1 << 0) -#define HYMINI_STM32_LED2 (1 << 1) - -#define ON_SETBITS_SHIFT (0) -#define ON_CLRBITS_SHIFT (4) -#define OFF_SETBITS_SHIFT (8) -#define OFF_CLRBITS_SHIFT (12) - -#define ON_BITS(v) ((v) & 0xff) -#define OFF_BITS(v) (((v) >> 8) & 0x0ff) -#define SETBITS(b) ((b) & 0x0f) -#define CLRBITS(b) (((b) >> 4) & 0x0f) - -#define ON_SETBITS(v) (SETBITS(ON_BITS(v)) -#define ON_CLRBITS(v) (CLRBITS(ON_BITS(v)) -#define OFF_SETBITS(v) (SETBITS(OFF_BITS(v)) -#define OFF_CLRBITS(v) (CLRBITS(OFF_BITS(v)) - -/* On: !LED1 + !LED2 Off: - */ - -#define LED_STARTED_ON_SETBITS ((0) << ON_SETBITS_SHIFT) -#define LED_STARTED_ON_CLRBITS ((HYMINI_STM32_LED1|HYMINI_STM32_LED2) << ON_CLRBITS_SHIFT) -#define LED_STARTED_OFF_SETBITS (0 << OFF_SETBITS_SHIFT) -#define LED_STARTED_OFF_CLRBITS (0 << OFF_CLRBITS_SHIFT) - -/* On: LED1+!LED2 Off: N/A */ - -#define LED_HEAPALLOCATE_ON_SETBITS ((HYMINI_STM32_LED1) << ON_SETBITS_SHIFT) -#define LED_HEAPALLOCATE_ON_CLRBITS ((HYMINI_STM32_LED2) << ON_CLRBITS_SHIFT) -#define LED_HEAPALLOCATE_OFF_SETBITS (0) -#define LED_HEAPALLOCATE_OFF_CLRBITS (0) - -/* On: LED2+!LED1 Off: N/A */ - -#define LED_IRQSENABLED_ON_SETBITS ((HYMINI_STM32_LED2) << ON_SETBITS_SHIFT) -#define LED_IRQSENABLED_ON_CLRBITS ((HYMINI_STM32_LED1) << ON_CLRBITS_SHIFT) -#define LED_IRQSENABLED_OFF_SETBITS (0) -#define LED_IRQSENABLED_OFF_CLRBITS (0) - -/* On: LED1+!LED2 Off: N/A */ - -#define LED_STACKCREATED_ON_SETBITS ((HYMINI_STM32_LED1) << ON_SETBITS_SHIFT) -#define LED_STACKCREATED_ON_CLRBITS ((HYMINI_STM32_LED2) << ON_CLRBITS_SHIFT) -#define LED_STACKCREATED_OFF_SETBITS (0) -#define LED_STACKCREATED_OFF_CLRBITS (0) - -/* On: !LED1 Off: LED1 */ - -#define LED_INIRQ_ON_SETBITS ((0) << ON_SETBITS_SHIFT) -#define LED_INIRQ_ON_CLRBITS ((HYMINI_STM32_LED1) << ON_CLRBITS_SHIFT) -#define LED_INIRQ_OFF_SETBITS ((HYMINI_STM32_LED1) << OFF_SETBITS_SHIFT) -#define LED_INIRQ_OFF_CLRBITS ((0) << OFF_CLRBITS_SHIFT) - -/* On: LED2 Off: !LED2 */ - -#define LED_SIGNAL_ON_SETBITS ((HYMINI_STM32_LED2) << ON_SETBITS_SHIFT) -#define LED_SIGNAL_ON_CLRBITS ((0) << ON_CLRBITS_SHIFT) -#define LED_SIGNAL_OFF_SETBITS ((0) << OFF_SETBITS_SHIFT) -#define LED_SIGNAL_OFF_CLRBITS ((HYMINI_STM32_LED2) << OFF_CLRBITS_SHIFT) - -/* On: LED1+LED2 Off: - */ - -#define LED_ASSERTION_ON_SETBITS ((HYMINI_STM32_LED2|HYMINI_STM32_LED2) << ON_SETBITS_SHIFT) -#define LED_ASSERTION_ON_CLRBITS ((0) << ON_CLRBITS_SHIFT) -#define LED_ASSERTION_OFF_SETBITS ((0) << OFF_SETBITS_SHIFT) -#define LED_ASSERTION_OFF_CLRBITS ((0) << OFF_CLRBITS_SHIFT) - -/* On: LED1 Off: LED2 */ - -#define LED_PANIC_ON_SETBITS ((HYMINI_STM32_LED1) << ON_SETBITS_SHIFT) -#define LED_PANIC_ON_CLRBITS ((HYMINI_STM32_LED2) << ON_CLRBITS_SHIFT) -#define LED_PANIC_OFF_SETBITS ((HYMINI_STM32_LED2) << OFF_SETBITS_SHIFT) -#define LED_PANIC_OFF_CLRBITS ((HYMINI_STM32_LED1) << OFF_CLRBITS_SHIFT) - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -static const uint16_t g_ledbits[8] = -{ - (LED_STARTED_ON_SETBITS | LED_STARTED_ON_CLRBITS | - LED_STARTED_OFF_SETBITS | LED_STARTED_OFF_CLRBITS), - - (LED_HEAPALLOCATE_ON_SETBITS | LED_HEAPALLOCATE_ON_CLRBITS | - LED_HEAPALLOCATE_OFF_SETBITS | LED_HEAPALLOCATE_OFF_CLRBITS), - - (LED_IRQSENABLED_ON_SETBITS | LED_IRQSENABLED_ON_CLRBITS | - LED_IRQSENABLED_OFF_SETBITS | LED_IRQSENABLED_OFF_CLRBITS), - - (LED_STACKCREATED_ON_SETBITS | LED_STACKCREATED_ON_CLRBITS | - LED_STACKCREATED_OFF_SETBITS | LED_STACKCREATED_OFF_CLRBITS), - - (LED_INIRQ_ON_SETBITS | LED_INIRQ_ON_CLRBITS | - LED_INIRQ_OFF_SETBITS | LED_INIRQ_OFF_CLRBITS), - - (LED_SIGNAL_ON_SETBITS | LED_SIGNAL_ON_CLRBITS | - LED_SIGNAL_OFF_SETBITS | LED_SIGNAL_OFF_CLRBITS), - - (LED_ASSERTION_ON_SETBITS | LED_ASSERTION_ON_CLRBITS | - LED_ASSERTION_OFF_SETBITS | LED_ASSERTION_OFF_CLRBITS), - - (LED_PANIC_ON_SETBITS | LED_PANIC_ON_CLRBITS | - LED_PANIC_OFF_SETBITS | LED_PANIC_OFF_CLRBITS) -}; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -static inline void led_clrbits(unsigned int clrbits) -{ - if ((clrbits & HYMINI_STM32_LED1) != 0) - { - stm32_gpiowrite(GPIO_LED1, false); - } - - if ((clrbits & HYMINI_STM32_LED2) != 0) - { - stm32_gpiowrite(GPIO_LED2, false); - } -} - -static inline void led_setbits(unsigned int setbits) -{ - if ((setbits & HYMINI_STM32_LED1) != 0) - { - stm32_gpiowrite(GPIO_LED1, true); - } - - if ((setbits & HYMINI_STM32_LED2) != 0) - { - stm32_gpiowrite(GPIO_LED2, true); - } -} - -static void led_setonoff(unsigned int bits) -{ - led_clrbits(CLRBITS(bits)); - led_setbits(SETBITS(bits)); -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_autoled_initialize - ****************************************************************************/ - -#ifdef CONFIG_ARCH_LEDS -void board_autoled_initialize(void) -{ - /* Configure LED1 & LED2 GPIOs for output */ - - stm32_configgpio(GPIO_LED1); - stm32_configgpio(GPIO_LED2); -} - -/**************************************************************************** - * Name: board_autoled_on - ****************************************************************************/ - -void board_autoled_on(int led) -{ - led_setonoff(ON_BITS(g_ledbits[led])); -} - -/**************************************************************************** - * Name: board_autoled_off - ****************************************************************************/ - -void board_autoled_off(int led) -{ - led_setonoff(OFF_BITS(g_ledbits[led])); -} - -#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/hymini-stm32v/src/stm32_spi.c b/boards/arm/stm32/hymini-stm32v/src/stm32_spi.c deleted file mode 100644 index 75eb1cbfd1778..0000000000000 --- a/boards/arm/stm32/hymini-stm32v/src/stm32_spi.c +++ /dev/null @@ -1,148 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/hymini-stm32v/src/stm32_spi.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include - -#include "arm_internal.h" -#include "chip.h" -#include "stm32.h" -#include "hymini-stm32v.h" - -#include /* Should always be included last due to dependencies */ - -#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_spidev_initialize - * - * Description: - * Called to configure SPI chip select GPIO pins for the HY-MiniSTM32 - * board. - * - ****************************************************************************/ - -void stm32_spidev_initialize(void) -{ - /* NOTE: Clocking for SPI1 and/or SPI2 was already provided in stm32_rcc.c. - * Configurations of SPI pins is performed in stm32_spi.c. - * Here, we only initialize chip select pins unique to the board - * architecture. - */ - -#ifdef CONFIG_STM32_SPI1 - /* Configure the SPI-based touch screen CS GPIO */ - - spiinfo("Configure GPIO for SPI1/CS\n"); - stm32_configgpio(GPIO_TS_CS); -#endif -} - -/**************************************************************************** - * Name: stm32_spi1/2/3select and stm32_spi1/2/3status - * - * Description: - * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status - * must be provided by board-specific logic. They are implementations of - * the select and status methods of the SPI interface defined by struct - * spi_ops_s (see include/nuttx/spi/spi.h). All other methods (including - * stm32_spibus_initialize()) are provided by common STM32 logic. - * To use this common SPI logic on your board: - * - * 1. Provide logic in stm32_boardinitialize() to configure SPI chip select - * pins. - * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() functions - * in your board-specific logic. These functions will perform chip - * selection and status operations using GPIOs in the way your board is - * configured. - * 3. Add a calls to stm32_spibus_initialize() in your low level - * application initialization logic - * 4. The handle returned by stm32_spibus_initialize() may then be used to - * bind the SPI driver to higher level logic (e.g., calling - * mmcsd_spislotinitialize(), for example, will bind the SPI driver to - * the SPI MMC/SD driver). - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_SPI1 -void stm32_spi1select(struct spi_dev_s *dev, - uint32_t devid, bool selected) -{ - spiinfo("devid: %d CS: %s\n", - (int)devid, selected ? "assert" : "de-assert"); - - if (devid == SPIDEV_TOUCHSCREEN(0)) - { - /* Set the GPIO low to select and high to de-select */ - - stm32_gpiowrite(GPIO_TS_CS, !selected); - } -} - -uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) -{ - return SPI_STATUS_PRESENT; -} -#endif - -#ifdef CONFIG_STM32_SPI2 -void stm32_spi2select(struct spi_dev_s *dev, - uint32_t devid, bool selected) -{ - spiinfo("devid: %d CS: %s\n", - (int)devid, selected ? "assert" : "de-assert"); -} - -uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) -{ - return SPI_STATUS_PRESENT; -} -#endif - -#ifdef CONFIG_STM32_SPI3 -void stm32_spi3select(struct spi_dev_s *dev, - uint32_t devid, bool selected) -{ - spiinfo("devid: %d CS: %s\n", - (int)devid, selected ? "assert" : "de-assert"); -} - -uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid) -{ - return SPI_STATUS_PRESENT; -} -#endif - -#endif /* CONFIG_STM32_SPI1 || CONFIG_STM32_SPI2 */ diff --git a/boards/arm/stm32/hymini-stm32v/src/stm32_ssd1289.c b/boards/arm/stm32/hymini-stm32v/src/stm32_ssd1289.c deleted file mode 100644 index 6da455a5bd46f..0000000000000 --- a/boards/arm/stm32/hymini-stm32v/src/stm32_ssd1289.c +++ /dev/null @@ -1,489 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/hymini-stm32v/src/stm32_ssd1289.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -#include "arm_internal.h" -#include "stm32.h" -#include "hymini-stm32v.h" - -#include /* Should always be included last due to dependencies */ - -#ifdef CONFIG_LCD_SSD1289 - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -#ifndef CONFIG_STM32_FSMC -# error "CONFIG_STM32_FSMC is required to use the LCD" -#endif - -/* Color depth and format */ - -#define LCD_BPP 16 -#define LCD_COLORFMT FB_FMT_RGB16_565 - -/* Display Resolution */ - -#if defined(CONFIG_LCD_LANDSCAPE) -# define LCD_XRES 320 -# define LCD_YRES 240 -#else -# define LCD_XRES 240 -# define LCD_YRES 320 -#endif - -#define LCD_BL_TIMER_PERIOD 8999 - -/* LCD is connected to the FSMC_Bank1_NOR/SRAM1 and NE1 is used as ship - * select signal - */ - -/* RS <==> A16 */ - -#define LCD_INDEX 0x60000000 /* RS = 0 */ -#define LCD_DATA 0x60020000 /* RS = 1 */ - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -/* Low Level LCD access */ - -static void stm32_select(struct ssd1289_lcd_s *dev); -static void stm32_deselect(struct ssd1289_lcd_s *dev); -static void stm32_index(struct ssd1289_lcd_s *dev, uint8_t index); -#ifndef CONFIG_SSD1289_WRONLY -static uint16_t stm32_read(struct ssd1289_lcd_s *dev); -#endif -static void stm32_write(struct ssd1289_lcd_s *dev, uint16_t data); -static void stm32_backlight(struct ssd1289_lcd_s *dev, int power); - -static void stm32_extmemgpios(const uint16_t *gpios, int ngpios); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -const uint16_t fsmc_gpios[] = -{ - /* A16... A24 */ - - GPIO_NPS_A16, GPIO_NPS_A17, GPIO_NPS_A18, GPIO_NPS_A19, GPIO_NPS_A20, - GPIO_NPS_A21, GPIO_NPS_A22, GPIO_NPS_A23, - - /* D0... D15 */ - - GPIO_NPS_D0, GPIO_NPS_D1, GPIO_NPS_D2, GPIO_NPS_D3, GPIO_NPS_D4, - GPIO_NPS_D5, GPIO_NPS_D6, GPIO_NPS_D7, GPIO_NPS_D8, GPIO_NPS_D9, - GPIO_NPS_D10, GPIO_NPS_D11, GPIO_NPS_D12, GPIO_NPS_D13, GPIO_NPS_D14, - GPIO_NPS_D15, - - /* NOE, NWE */ - - GPIO_NPS_NOE, GPIO_NPS_NWE, - - /* NE1 */ - - GPIO_NPS_NE1 -}; - -#define NGPIOS (sizeof(fsmc_gpios)/sizeof(uint16_t)) - -/* This is the driver state structure */ - -static struct ssd1289_lcd_s g_ssd1289 = -{ - .select = stm32_select, - .deselect = stm32_deselect, - .index = stm32_index, -#ifndef CONFIG_SSD1289_WRONLY - .read = stm32_read, -#endif - .write = stm32_write, - .backlight = stm32_backlight -}; - -/* The saved instance of the LCD driver */ - -static struct lcd_dev_s *g_ssd1289drvr; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_select - * - * Description: - * Select the LCD device - * - ****************************************************************************/ - -static void stm32_select(struct ssd1289_lcd_s *dev) -{ - /* Does not apply to this hardware */ -} - -/**************************************************************************** - * Name: stm32_deselect - * - * Description: - * De-select the LCD device - * - ****************************************************************************/ - -static void stm32_deselect(struct ssd1289_lcd_s *dev) -{ - /* Does not apply to this hardware */ -} - -/**************************************************************************** - * Name: stm32_index - * - * Description: - * Set the index register - * - ****************************************************************************/ - -static void stm32_index(struct ssd1289_lcd_s *dev, uint8_t index) -{ - putreg16((uint16_t)index, LCD_INDEX); -} - -/**************************************************************************** - * Name: stm32_read - * - * Description: - * Read LCD data (GRAM data or register contents) - * - ****************************************************************************/ - -#ifndef CONFIG_SSD1289_WRONLY -static uint16_t stm32_read(struct ssd1289_lcd_s *dev) -{ - return getreg16(LCD_DATA); -} -#endif - -/**************************************************************************** - * Name: stm32_write - * - * Description: - * Write LCD data (GRAM data or register contents) - * - ****************************************************************************/ - -static void stm32_write(struct ssd1289_lcd_s *dev, uint16_t data) -{ - putreg16((uint16_t)data, LCD_DATA); -} - -/**************************************************************************** - * Name: stm32_backlight - * - * Description: - * Enable/disable LCD panel power (0: full off - CONFIG_LCD_MAXPOWER: - * full on). - * Used here to set pwm duty on timer used for backlight. - * - ****************************************************************************/ - -static void stm32_backlight(struct ssd1289_lcd_s *dev, int power) -{ - DEBUGASSERT(power <= CONFIG_LCD_MAXPOWER); - - /* Set new power level */ - - if (power > 0) - { - uint32_t duty; - - /* Calculate the new backlight duty. It is a fraction of the timer - * period based on the ration of the current power setting to the - * maximum power setting. - */ - - duty = ((uint32_t)LCD_BL_TIMER_PERIOD * (uint32_t)power) / - CONFIG_LCD_MAXPOWER; - if (duty >= LCD_BL_TIMER_PERIOD) - { - duty = LCD_BL_TIMER_PERIOD - 1; - } - - putreg16((uint16_t)duty, STM32_TIM3_CCR2); - } - else - { - putreg16((uint16_t)0, STM32_TIM3_CCR2); - } -} - -static void init_lcd_backlight(void) -{ - uint16_t ccmr; - uint16_t ccer; - - /* Configure PB5 as TIM3 CH2 output */ - - stm32_configgpio(GPIO_TIM3_CH2OUT); - - /* Enable timer 3 clocking */ - - modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM3EN); - - /* Reset timer 3 */ - - modifyreg32(STM32_RCC_APB1RSTR, 0, RCC_APB1RSTR_TIM3RST); - modifyreg32(STM32_RCC_APB1RSTR, RCC_APB1RSTR_TIM3RST, 0); - - /* Reset the Counter Mode and set the clock division */ - - putreg16(0, STM32_TIM3_CR1); - - /* Set the Autoreload value */ - - putreg16(LCD_BL_TIMER_PERIOD, STM32_TIM3_ARR); - - /* Set the Prescaler value */ - - putreg16(0, STM32_TIM3_PSC); - - /* Generate an update event to reload the Prescaler value immediately */ - - putreg16(ATIM_EGR_UG, STM32_TIM3_EGR); - - /* Disable the Channel 2 */ - - ccer = getreg16(STM32_TIM3_CCER); - ccer &= ~ATIM_CCER_CC2E; - putreg16(ccer, STM32_TIM3_CCER); - - /* Select the Output Compare Mode Bits */ - - ccmr = getreg16(STM32_TIM3_CCMR1); - ccmr &= ATIM_CCMR1_OC2M_MASK; - ccmr |= (ATIM_CCMR_MODE_PWM1 << ATIM_CCMR1_OC2M_SHIFT); - - putreg16(0, STM32_TIM3_CCR2); - - /* Select the output polarity level == HIGH */ - - ccer &= ~ATIM_CCER_CC2P; - - /* Enable channel 2 */ - - ccer |= ATIM_CCER_CC2E; - - /* Write the timer configuration */ - - putreg16(ccmr, STM32_TIM3_CCMR1); - putreg16(ccer, STM32_TIM3_CCER); - - /* Set the auto preload enable bit */ - - modifyreg16(STM32_TIM3_CR1, 0, ATIM_CR1_ARPE); - - /* Enable Backlight Timer !!!! */ - - modifyreg16(STM32_TIM3_CR1, 0, ATIM_CR1_CEN); - - /* Dump timer3 registers */ - - lcdinfo("APB1ENR: %08" PRIx32 "\n", getreg32(STM32_RCC_APB1ENR)); - lcdinfo("CR1: %04" PRIx32 "\n", getreg32(STM32_TIM3_CR1)); - lcdinfo("CR2: %04" PRIx32 "\n", getreg32(STM32_TIM3_CR2)); - lcdinfo("SMCR: %04" PRIx32 "\n", getreg32(STM32_TIM3_SMCR)); - lcdinfo("DIER: %04" PRIx32 "\n", getreg32(STM32_TIM3_DIER)); - lcdinfo("SR: %04" PRIx32 "\n", getreg32(STM32_TIM3_SR)); - lcdinfo("EGR: %04" PRIx32 "\n", getreg32(STM32_TIM3_EGR)); - lcdinfo("CCMR1: %04" PRIx32 "\n", getreg32(STM32_TIM3_CCMR1)); - lcdinfo("CCMR2: %04" PRIx32 "\n", getreg32(STM32_TIM3_CCMR2)); - lcdinfo("CCER: %04" PRIx32 "\n", getreg32(STM32_TIM3_CCER)); - lcdinfo("CNT: %04" PRIx32 "\n", getreg32(STM32_TIM3_CNT)); - lcdinfo("PSC: %04" PRIx32 "\n", getreg32(STM32_TIM3_PSC)); - lcdinfo("ARR: %04" PRIx32 "\n", getreg32(STM32_TIM3_ARR)); - lcdinfo("CCR1: %04" PRIx32 "\n", getreg32(STM32_TIM3_CCR1)); - lcdinfo("CCR2: %04" PRIx32 "\n", getreg32(STM32_TIM3_CCR2)); - lcdinfo("CCR3: %04" PRIx32 "\n", getreg32(STM32_TIM3_CCR3)); - lcdinfo("CCR4: %04" PRIx32 "\n", getreg32(STM32_TIM3_CCR4)); - lcdinfo("CCR4: %04" PRIx32 "\n", getreg32(STM32_TIM3_CCR4)); - lcdinfo("CCR4: %04" PRIx32 "\n", getreg32(STM32_TIM3_CCR4)); - lcdinfo("DMAR: %04" PRIx32 "\n", getreg32(STM32_TIM3_DMAR)); -} - -/**************************************************************************** - * Name: stm32_selectlcd - * - * Description: - * Initialize the memory controller (FSMC) - * - ****************************************************************************/ - -static void stm32_selectlcd(void) -{ - /* Configure new GPIO state */ - - stm32_extmemgpios(fsmc_gpios, NGPIOS); - - /* Enable AHB clocking to the FSMC */ - - stm32_fsmc_enable(); - - /* Bank1 NOR/SRAM control register configuration */ - - putreg32(FSMC_BCR_SRAM | FSMC_BCR_MWID16 | FSMC_BCR_WREN, STM32_FSMC_BCR1); - - /* Bank1 NOR/SRAM timing register configuration */ - - putreg32(FSMC_BTR_ADDSET(1) | FSMC_BTR_ADDHLD(1) | FSMC_BTR_DATAST(2) | - FSMC_BTR_BUSTURN(1) | FSMC_BTR_CLKDIV(1) | FSMC_BTR_DATLAT(2) | - FSMC_BTR_ACCMODA, - STM32_FSMC_BTR1); - - /* As ext mode is not active the write timing is ignored!! */ - - putreg32(0xffffffff, STM32_FSMC_BWTR1); - - /* Enable the bank by setting the MBKEN bit */ - - putreg32(FSMC_BCR_MBKEN | FSMC_BCR_SRAM | FSMC_BCR_MWID16 | FSMC_BCR_WREN, - STM32_FSMC_BCR1); -} - -/**************************************************************************** - * Name: stm32_extmemgpios - * - * Description: - * Initialize GPIOs for NOR or SRAM - * - ****************************************************************************/ - -static void stm32_extmemgpios(const uint16_t *gpios, int ngpios) -{ - int i; - - /* Configure GPIOs */ - - for (i = 0; i < ngpios; i++) - { - stm32_configgpio(gpios[i]); - } -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_lcd_initialize - * - * Description: - * Initialize the LCD video hardware. The initial state of the LCD is - * fully initialized, display memory cleared, and the LCD ready to use, - * but with the power setting at 0 (full off). - * - ****************************************************************************/ - -int board_lcd_initialize(void) -{ - /* Only initialize the driver once */ - - if (!g_ssd1289drvr) - { - lcdinfo("Initializing\n"); - - init_lcd_backlight(); - - /* Configure GPIO pins and configure the FSMC to support the LCD */ - - stm32_selectlcd(); - - /* Configure and enable the LCD */ - - up_mdelay(50); - g_ssd1289drvr = ssd1289_lcdinitialize(&g_ssd1289); - if (!g_ssd1289drvr) - { - lcderr("ERROR: ssd1289_lcdinitialize failed\n"); - return -ENODEV; - } - } - - /* Turn the display off */ - - g_ssd1289drvr->setpower(g_ssd1289drvr, 0); - return OK; -} - -/**************************************************************************** - * Name: board_lcd_getdev - * - * Description: - * Return a a reference to the LCD object for the specified LCD. This - * allows support for multiple LCD devices. - * - ****************************************************************************/ - -struct lcd_dev_s *board_lcd_getdev(int lcddev) -{ - DEBUGASSERT(lcddev == 0); - return g_ssd1289drvr; -} - -/**************************************************************************** - * Name: board_lcd_uninitialize - * - * Description: - * Uninitialize the LCD support - * - ****************************************************************************/ - -void board_lcd_uninitialize(void) -{ - /* Turn the display off */ - - g_ssd1289drvr->setpower(g_ssd1289drvr, 0); -} - -#endif /* CONFIG_LCD_SSD1289 */ diff --git a/boards/arm/stm32/hymini-stm32v/src/stm32_usbdev.c b/boards/arm/stm32/hymini-stm32v/src/stm32_usbdev.c deleted file mode 100644 index c5bbfba802af1..0000000000000 --- a/boards/arm/stm32/hymini-stm32v/src/stm32_usbdev.c +++ /dev/null @@ -1,105 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/hymini-stm32v/src/stm32_usbdev.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include - -#include -#include - -#include "arm_internal.h" -#include "stm32.h" -#include "hymini-stm32v.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_usbinitialize - * - * Description: - * Called to setup USB-related GPIO pins for the Hy-Mini STM32v board. - * - ****************************************************************************/ - -void stm32_usbinitialize(void) -{ - uinfo("called\n"); - - /* USB Soft Connect Pullup */ - - stm32_configgpio(GPIO_USB_PULLUP); -} - -/**************************************************************************** - * Name: stm32_usbpullup - * - * Description: - * If USB is supported and the board supports a pullup via GPIO - * (for USB software connect and disconnect), then the board software must - * provide stm32_pullup. - * See include/nuttx/usb/usbdev.h for additional description of this - * method. Alternatively, if no pull-up GPIO the following EXTERN can - * be redefined to be NULL. - * - ****************************************************************************/ - -int stm32_usbpullup(struct usbdev_s *dev, bool enable) -{ - usbtrace(TRACE_DEVPULLUP, (uint16_t)enable); - stm32_gpiowrite(GPIO_USB_PULLUP, !enable); - return OK; -} - -/**************************************************************************** - * Name: stm32_usbsuspend - * - * Description: - * Board logic must provide the stm32_usbsuspend logic if the USBDEV driver - * is used. This function is called whenever the USB enters or leaves - * suspend mode. - * This is an opportunity for the board logic to shutdown clocks, power, - * etc. while the USB is suspended. - * - ****************************************************************************/ - -void stm32_usbsuspend(struct usbdev_s *dev, bool resume) -{ - uinfo("resume: %d\n", resume); -} diff --git a/boards/arm/stm32/hymini-stm32v/src/stm32_usbmsc.c b/boards/arm/stm32/hymini-stm32v/src/stm32_usbmsc.c deleted file mode 100644 index 5072bc4531f2b..0000000000000 --- a/boards/arm/stm32/hymini-stm32v/src/stm32_usbmsc.c +++ /dev/null @@ -1,127 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/hymini-stm32v/src/stm32_usbmsc.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include -#include - -#include "stm32.h" - -/* There is nothing to do here if SDIO support is not selected. */ - -#ifdef CONFIG_STM32_SDIO - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -#ifndef CONFIG_SYSTEM_USBMSC_DEVMINOR1 -# define CONFIG_SYSTEM_USBMSC_DEVMINOR1 0 -#endif - -/* SLOT number(s) could depend on the board configuration */ - -#ifdef CONFIG_ARCH_BOARD_HYMINI_STM32V -# undef STM32_MMCSDSLOTNO -# define STM32_MMCSDSLOTNO 0 -#else -/* Add configuration for new STM32 boards here */ - -# error "Unrecognized STM32 board" -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_usbmsc_initialize - * - * Description: - * Perform architecture specific initialization of the USB MSC device. - * - ****************************************************************************/ - -int board_usbmsc_initialize(int port) -{ - /* If system/usbmsc is built as an NSH command, then SD slot should - * already have been initialized. - * In this case, there is nothing further to be done here. - */ - -#ifndef CONFIG_NSH_BUILTIN_APPS - struct sdio_dev_s *sdio; - int ret; - - /* First, get an instance of the SDIO interface */ - - syslog(LOG_INFO, "Initializing SDIO slot %d\n", STM32_MMCSDSLOTNO); - - sdio = sdio_initialize(STM32_MMCSDSLOTNO); - if (!sdio) - { - syslog(LOG_ERR, "ERROR: Failed to initialize SDIO slot %d\n", - STM32_MMCSDSLOTNO); - return -ENODEV; - } - - /* Now bind the SDIO interface to the MMC/SD driver */ - - syslog(LOG_INFO, "Bind SDIO to the MMC/SD driver, minor=%d\n", - CONFIG_SYSTEM_USBMSC_DEVMINOR1); - - ret = mmcsd_slotinitialize(CONFIG_SYSTEM_USBMSC_DEVMINOR1, sdio); - if (ret != OK) - { - syslog(LOG_ERR, "" - "ERROR: Failed to bind SDIO to the MMC/SD driver: %d\n", - ret); - return ret; - } - - syslog(LOG_INFO, "Successfully bound SDIO to the MMC/SD driver\n"); - - /* Then let's guess and say that there is a card in the slot. - * I need to check to see if the Hy-Mini STM32v board supports a GPIO to - * detect if there is a card in the slot. - */ - - sdio_mediachange(sdio, true); - -#endif /* CONFIG_NSH_BUILTIN_APPS */ - - return OK; -} - -#endif /* CONFIG_STM32_SDIO */ diff --git a/boards/arm/stm32/maple/CMakeLists.txt b/boards/arm/stm32/maple/CMakeLists.txt deleted file mode 100644 index ebbac811ea8c8..0000000000000 --- a/boards/arm/stm32/maple/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/maple/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32/maple/configs/nsh/defconfig b/boards/arm/stm32/maple/configs/nsh/defconfig deleted file mode 100644 index 7c9ac9e17fbbc..0000000000000 --- a/boards/arm/stm32/maple/configs/nsh/defconfig +++ /dev/null @@ -1,54 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_DISABLE_OS_API is not set -# CONFIG_NSH_DISABLEBG is not set -# CONFIG_NSH_DISABLESCRIPT is not set -# CONFIG_NSH_DISABLE_CMP is not set -# CONFIG_NSH_DISABLE_EXEC is not set -# CONFIG_NSH_DISABLE_EXIT is not set -# CONFIG_NSH_DISABLE_GET is not set -# CONFIG_NSH_DISABLE_HEXDUMP is not set -# CONFIG_NSH_DISABLE_IFCONFIG is not set -# CONFIG_NSH_DISABLE_LOSETUP is not set -# CONFIG_NSH_DISABLE_MKRD is not set -# CONFIG_NSH_DISABLE_PS is not set -# CONFIG_NSH_DISABLE_PUT is not set -# CONFIG_NSH_DISABLE_WGET is not set -# CONFIG_NSH_DISABLE_XD is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="maple" -CONFIG_ARCH_BOARD_MAPLE=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F103CB=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=5483 -CONFIG_BUILTIN=y -CONFIG_DEFAULT_SMALL=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_LIBC_RAND_ORDER=2 -CONFIG_LINE_MAX=80 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=1024 -CONFIG_PTHREAD_STACK_DEFAULT=1024 -CONFIG_RAM_SIZE=20480 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_START_DAY=23 -CONFIG_START_MONTH=10 -CONFIG_START_YEAR=2009 -CONFIG_STM32_DFU=y -CONFIG_STM32_USART1=y -CONFIG_STM32_USB=y -CONFIG_SYMTAB_ORDEREDBYNAME=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART1_SERIAL_CONSOLE=y -CONFIG_USBDEV_TRACE=y -CONFIG_USBDEV_TRACE_NRECORDS=32 diff --git a/boards/arm/stm32/maple/configs/nx/defconfig b/boards/arm/stm32/maple/configs/nx/defconfig deleted file mode 100644 index 9ffbeb782a291..0000000000000 --- a/boards/arm/stm32/maple/configs/nx/defconfig +++ /dev/null @@ -1,77 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_DEV_CONSOLE is not set -# CONFIG_DISABLE_OS_API is not set -# CONFIG_NSH_DISABLEBG is not set -# CONFIG_NSH_DISABLESCRIPT is not set -# CONFIG_NSH_DISABLE_CMP is not set -# CONFIG_NSH_DISABLE_EXEC is not set -# CONFIG_NSH_DISABLE_EXIT is not set -# CONFIG_NSH_DISABLE_GET is not set -# CONFIG_NSH_DISABLE_HEXDUMP is not set -# CONFIG_NSH_DISABLE_IFCONFIG is not set -# CONFIG_NSH_DISABLE_LOSETUP is not set -# CONFIG_NSH_DISABLE_MKRD is not set -# CONFIG_NSH_DISABLE_PS is not set -# CONFIG_NSH_DISABLE_PUT is not set -# CONFIG_NSH_DISABLE_WGET is not set -# CONFIG_NSH_DISABLE_XD is not set -# CONFIG_NX_DISABLE_1BPP is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="maple" -CONFIG_ARCH_BOARD_MAPLE=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F103CB=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=5483 -CONFIG_BUILTIN=y -CONFIG_CDCACM=y -CONFIG_CDCACM_CONSOLE=y -CONFIG_CDCACM_RXBUFSIZE=256 -CONFIG_CDCACM_TXBUFSIZE=256 -CONFIG_DEFAULT_SMALL=y -CONFIG_EXAMPLES_NX=y -CONFIG_EXAMPLES_NXHELLO=y -CONFIG_EXAMPLES_NXHELLO_BPP=1 -CONFIG_EXAMPLES_NX_BPP=1 -CONFIG_I2C=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_LCD=y -CONFIG_LCD_SHARP_MEMLCD=y -CONFIG_LIBC_RAND_ORDER=2 -CONFIG_LINE_MAX=80 -CONFIG_MQ_MAXMSGSIZE=64 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=1024 -CONFIG_NSH_USBCONSOLE=y -CONFIG_NX=y -CONFIG_NXFONT_MONO5X8=y -CONFIG_NX_BLOCKING=y -CONFIG_PTHREAD_STACK_DEFAULT=1024 -CONFIG_RAM_SIZE=20480 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SPI_BITORDER=y -CONFIG_START_DAY=23 -CONFIG_START_MONTH=10 -CONFIG_START_YEAR=2009 -CONFIG_STM32_DFU=y -CONFIG_STM32_I2C1=y -CONFIG_STM32_I2C2=y -CONFIG_STM32_I2CTIMEOSEC=1 -CONFIG_STM32_SPI1=y -CONFIG_STM32_TIM2=y -CONFIG_STM32_USART1=y -CONFIG_STM32_USB=y -CONFIG_SYMTAB_ORDEREDBYNAME=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=15 -CONFIG_USBDEV_TRACE=y -CONFIG_USBDEV_TRACE_NRECORDS=32 diff --git a/boards/arm/stm32/maple/configs/usbnsh/defconfig b/boards/arm/stm32/maple/configs/usbnsh/defconfig deleted file mode 100644 index 5dac2d2057063..0000000000000 --- a/boards/arm/stm32/maple/configs/usbnsh/defconfig +++ /dev/null @@ -1,60 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_DEV_CONSOLE is not set -# CONFIG_DISABLE_OS_API is not set -# CONFIG_NSH_DISABLEBG is not set -# CONFIG_NSH_DISABLESCRIPT is not set -# CONFIG_NSH_DISABLE_CMP is not set -# CONFIG_NSH_DISABLE_EXEC is not set -# CONFIG_NSH_DISABLE_EXIT is not set -# CONFIG_NSH_DISABLE_GET is not set -# CONFIG_NSH_DISABLE_HEXDUMP is not set -# CONFIG_NSH_DISABLE_IFCONFIG is not set -# CONFIG_NSH_DISABLE_LOSETUP is not set -# CONFIG_NSH_DISABLE_MKRD is not set -# CONFIG_NSH_DISABLE_PS is not set -# CONFIG_NSH_DISABLE_PUT is not set -# CONFIG_NSH_DISABLE_WGET is not set -# CONFIG_NSH_DISABLE_XD is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="maple" -CONFIG_ARCH_BOARD_MAPLE=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F103CB=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=5483 -CONFIG_BUILTIN=y -CONFIG_CDCACM=y -CONFIG_CDCACM_CONSOLE=y -CONFIG_CDCACM_RXBUFSIZE=256 -CONFIG_CDCACM_TXBUFSIZE=256 -CONFIG_DEFAULT_SMALL=y -CONFIG_I2C=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_LIBC_RAND_ORDER=2 -CONFIG_LINE_MAX=80 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=1024 -CONFIG_NSH_USBCONSOLE=y -CONFIG_PTHREAD_STACK_DEFAULT=1024 -CONFIG_RAM_SIZE=20480 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_START_DAY=23 -CONFIG_START_MONTH=10 -CONFIG_START_YEAR=2009 -CONFIG_STM32_DFU=y -CONFIG_STM32_USART1=y -CONFIG_STM32_USB=y -CONFIG_SYMTAB_ORDEREDBYNAME=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USBDEV_TRACE=y -CONFIG_USBDEV_TRACE_NRECORDS=32 diff --git a/boards/arm/stm32/maple/include/board.h b/boards/arm/stm32/maple/include/board.h deleted file mode 100644 index dd3a2053a28f7..0000000000000 --- a/boards/arm/stm32/maple/include/board.h +++ /dev/null @@ -1,190 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/maple/include/board.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __BOARDS_ARM_STM32_MAPLE_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32_MAPLE_INCLUDE_BOARD_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#ifndef __ASSEMBLY__ -# include -#endif - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Clocking *****************************************************************/ - -/* On-board crystal frequency is 8MHz (HSE) */ - -#define STM32_BOARD_XTAL 8000000ul - -/* PLL source is HSE/1, PLL multiplier is 9: - * PLL frequency is 8MHz (XTAL) x 9 = 72MHz - */ - -#define STM32_CFGR_PLLSRC RCC_CFGR_PLLSRC -#define STM32_CFGR_PLLXTPRE 0 -#define STM32_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx9 -#define STM32_PLL_FREQUENCY (9*STM32_BOARD_XTAL) - -/* Use the PLL and set the SYSCLK source to be the PLL */ - -#define STM32_SYSCLK_SW RCC_CFGR_SW_PLL -#define STM32_SYSCLK_SWS RCC_CFGR_SWS_PLL -#define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY - -/* AHB clock (HCLK) is SYSCLK (72MHz) */ - -#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK -#define STM32_HCLK_FREQUENCY STM32_PLL_FREQUENCY - -/* APB2 clock (PCLK2) is HCLK (72MHz) */ - -#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK -#define STM32_PCLK2_FREQUENCY STM32_HCLK_FREQUENCY - -/* APB2 timers 1 and 8 will receive PCLK2. */ - -#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) - -/* APB1 clock (PCLK1) is HCLK/2 (36MHz) */ - -#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd2 -#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/2) - -/* APB1 timers 2-7 will be twice PCLK1 */ - -#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) - -/* USB divider -- Divide PLL clock by 1.5 */ - -#define STM32_CFGR_USBPRE 0 - -/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx - * otherwise frequency is 2xAPBx. - * Note: TIM1,8 are on APB2, others on APB1 - */ - -#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM2_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM3_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM4_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM5_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM6_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM7_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY - -/* SDIO dividers. Note that slower clocking is required when DMA is disabled - * in order to avoid RX overrun/TX underrun errors due to delayed responses - * to service FIFOs in interrupt driven mode. These values have not been - * tuned!!! - * - * HCLK=72MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(178+2)=400 KHz - */ - -#define SDIO_INIT_CLKDIV (178 << SDIO_CLKCR_CLKDIV_SHIFT) - -/* DMA ON: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(2+2)=18 MHz - * DMA OFF: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(3+2)=14.4 MHz - */ - -#ifdef CONFIG_SDIO_DMA -# define SDIO_MMCXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT) -#else -# define SDIO_MMCXFR_CLKDIV (3 << SDIO_CLKCR_CLKDIV_SHIFT) -#endif - -/* DMA ON: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(1+2)=24 MHz - * DMA OFF: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(3+2)=14.4 MHz - */ - -#ifdef CONFIG_SDIO_DMA -# define SDIO_SDXFR_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT) -#else -# define SDIO_SDXFR_CLKDIV (3 << SDIO_CLKCR_CLKDIV_SHIFT) -#endif - -/* LED definitions **********************************************************/ - -/* The board has only one controllable LED */ - -#define LED_STARTED 0 /* No LEDs */ -#define LED_HEAPALLOCATE 1 /* LED1 on */ -#define LED_IRQSENABLED 2 /* LED2 on */ -#define LED_STACKCREATED 3 /* LED1 on */ -#define LED_INIRQ 4 /* LED1 off */ -#define LED_SIGNAL 5 /* LED2 on */ -#define LED_ASSERTION 6 /* LED1 + LED2 */ -#define LED_PANIC 7 /* LED1 / LED2 blinking */ - -/* Alternate function pin selections (auto-aliased for new pinmap) */ - -/* USART1 */ - -#define GPIO_USART1_TX GPIO_ADJUST_MODE(GPIO_USART1_TX_0, GPIO_MODE_50MHz) -#define GPIO_USART1_RX GPIO_USART1_RX_0 - -/* SPI1 */ - -#define GPIO_SPI1_NSS GPIO_ADJUST_MODE(GPIO_SPI1_NSS_0, GPIO_MODE_50MHz) -#define GPIO_SPI1_SCK GPIO_ADJUST_MODE(GPIO_SPI1_SCK_0, GPIO_MODE_50MHz) -#define GPIO_SPI1_MISO GPIO_ADJUST_MODE(GPIO_SPI1_MISO_0, GPIO_MODE_50MHz) -#define GPIO_SPI1_MOSI GPIO_ADJUST_MODE(GPIO_SPI1_MOSI_0, GPIO_MODE_50MHz) - -/* I2C1 */ - -#define GPIO_I2C1_SCL GPIO_ADJUST_MODE(GPIO_I2C1_SCL_0, GPIO_MODE_50MHz) -#define GPIO_I2C1_SDA GPIO_ADJUST_MODE(GPIO_I2C1_SDA_0, GPIO_MODE_50MHz) - -/* I2C2 */ - -#define GPIO_I2C2_SCL GPIO_ADJUST_MODE(GPIO_I2C2_SCL_0, GPIO_MODE_50MHz) -#define GPIO_I2C2_SDA GPIO_ADJUST_MODE(GPIO_I2C2_SDA_0, GPIO_MODE_50MHz) - -/* USB */ - -#define GPIO_USB_DM GPIO_USB_DM_0 -#define GPIO_USB_DP GPIO_USB_DP_0 - -/* TIM2 */ - -#define GPIO_TIM2_CH1IN GPIO_TIM2_CH1IN_0 -#define GPIO_TIM2_CH1OUT GPIO_ADJUST_MODE(GPIO_TIM2_CH1OUT_0, GPIO_MODE_50MHz) -#define GPIO_TIM2_CH2IN GPIO_TIM2_CH2IN_0 -#define GPIO_TIM2_CH2OUT GPIO_ADJUST_MODE(GPIO_TIM2_CH2OUT_0, GPIO_MODE_50MHz) -#define GPIO_TIM2_CH3IN GPIO_TIM2_CH3IN_0 -#define GPIO_TIM2_CH3OUT GPIO_ADJUST_MODE(GPIO_TIM2_CH3OUT_0, GPIO_MODE_50MHz) -#define GPIO_TIM2_CH4IN GPIO_TIM2_CH4IN_0 -#define GPIO_TIM2_CH4OUT GPIO_ADJUST_MODE(GPIO_TIM2_CH4OUT_0, GPIO_MODE_50MHz) - -#endif /* __BOARDS_ARM_STM32_MAPLE_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32/maple/scripts/Make.defs b/boards/arm/stm32/maple/scripts/Make.defs deleted file mode 100644 index 29529db249b31..0000000000000 --- a/boards/arm/stm32/maple/scripts/Make.defs +++ /dev/null @@ -1,46 +0,0 @@ -############################################################################ -# boards/arm/stm32/maple/scripts/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/.config -include $(TOPDIR)/tools/Config.mk -include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs - -ifeq ($(CONFIG_STM32_DFU),y) - LDSCRIPT = ld.script.dfu -else - LDSCRIPT = ld.script -endif - -ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) - -ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 - -CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) -CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) -CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -AFLAGS := $(CFLAGS) -D__ASSEMBLY__ - -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections -LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32/maple/scripts/ld.script b/boards/arm/stm32/maple/scripts/ld.script deleted file mode 100644 index afe284a8b80f4..0000000000000 --- a/boards/arm/stm32/maple/scripts/ld.script +++ /dev/null @@ -1,122 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/maple/scripts/ld.script - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* The STM32F103xB has 128Kb of FLASH beginning at address 0x0800:0000 and - * 20Kb of SRAM beginning at address 0x2000:0000. When booting from FLASH, - * FLASH memory is aliased to address 0x0000:0000 where the code expects to - * begin execution by jumping to the entry point in the 0x0800:0000 address - * range. - */ - -MEMORY -{ - flash (rx) : ORIGIN = 0x08000000, LENGTH = 128K - sram (rwx) : ORIGIN = 0x20000000, LENGTH = 20K -} - -OUTPUT_ARCH(arm) -EXTERN(_vectors) -ENTRY(_stext) -SECTIONS -{ - .text : { - _stext = ABSOLUTE(.); - *(.vectors) - *(.text .text.*) - *(.fixup) - *(.gnu.warning) - *(.rodata .rodata.*) - *(.gnu.linkonce.t.*) - *(.glue_7) - *(.glue_7t) - *(.got) - *(.gcc_except_table) - *(.gnu.linkonce.r.*) - _etext = ABSOLUTE(.); - } > flash - - .init_section : ALIGN(4) { - _sinit = ABSOLUTE(.); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) - KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) - _einit = ABSOLUTE(.); - } > flash - - .ARM.extab : ALIGN(4) { - *(.ARM.extab*) - } > flash - - .ARM.exidx : ALIGN(4) { - __exidx_start = ABSOLUTE(.); - *(.ARM.exidx*) - __exidx_end = ABSOLUTE(.); - } > flash - - .tdata : { - _stdata = ABSOLUTE(.); - *(.tdata .tdata.* .gnu.linkonce.td.*); - _etdata = ABSOLUTE(.); - } > flash - - .tbss : { - _stbss = ABSOLUTE(.); - *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); - _etbss = ABSOLUTE(.); - } > flash - - _eronly = ABSOLUTE(.); - - /* The STM32F103VCT6 has 48Kb of SRAM beginning at the following address */ - - .data : ALIGN(4) { - _sdata = ABSOLUTE(.); - *(.data .data.*) - *(.gnu.linkonce.d.*) - CONSTRUCTORS - . = ALIGN(4); - _edata = ABSOLUTE(.); - } > sram AT > flash - - .bss : ALIGN(4) { - _sbss = ABSOLUTE(.); - *(.bss .bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - . = ALIGN(4); - _ebss = ABSOLUTE(.); - } > sram - - /* Stabs debugging sections. */ - - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_info 0 : { *(.debug_info) } - .debug_line 0 : { *(.debug_line) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_aranges 0 : { *(.debug_aranges) } -} diff --git a/boards/arm/stm32/maple/scripts/ld.script.dfu b/boards/arm/stm32/maple/scripts/ld.script.dfu deleted file mode 100644 index f36caa9525e43..0000000000000 --- a/boards/arm/stm32/maple/scripts/ld.script.dfu +++ /dev/null @@ -1,107 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/maple/scripts/ld.script.dfu - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* The STM32F103xB has 128Kb of FLASH beginning at address 0x0800:0000 and - * 20Kb of SRAM beginning at address 0x2000:0000. Here we assume that the - * maple's DFU bootloader is being used. In that case, the correct - * load .text load address is 0x0800:5000 (leaving 108Kb). - */ - -MEMORY -{ - flash (rx) : ORIGIN = 0x08005000, LENGTH = 108K - sram (rwx) : ORIGIN = 0x20000000, LENGTH = 20K -} - -OUTPUT_ARCH(arm) -EXTERN(_vectors) -ENTRY(_stext) - -SECTIONS -{ - .text : { - _stext = ABSOLUTE(.); - *(.vectors) - *(.text .text.*) - *(.fixup) - *(.gnu.warning) - *(.rodata .rodata.*) - *(.gnu.linkonce.t.*) - *(.glue_7) - *(.glue_7t) - *(.got) - *(.gcc_except_table) - *(.gnu.linkonce.r.*) - _etext = ABSOLUTE(.); - } > flash - - .init_section : ALIGN(4) { - _sinit = ABSOLUTE(.); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) - KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) - _einit = ABSOLUTE(.); - } > flash - - .ARM.extab : ALIGN(4) { - *(.ARM.extab*) - } > flash - - .ARM.exidx : ALIGN(4) { - __exidx_start = ABSOLUTE(.); - *(.ARM.exidx*) - __exidx_end = ABSOLUTE(.); - } > flash - - _eronly = ABSOLUTE(.); - - /* The STM32F103VCT6 has 48Kb of SRAM beginning at the following address */ - - .data : ALIGN(4) { - _sdata = ABSOLUTE(.); - *(.data .data.*) - *(.gnu.linkonce.d.*) - CONSTRUCTORS - _edata = ABSOLUTE(.); - } > sram AT > flash - - .bss : ALIGN(4) { - _sbss = ABSOLUTE(.); - *(.bss .bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - _ebss = ABSOLUTE(.); - } > sram - - /* Stabs debugging sections. */ - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_info 0 : { *(.debug_info) } - .debug_line 0 : { *(.debug_line) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_aranges 0 : { *(.debug_aranges) } -} diff --git a/boards/arm/stm32/maple/src/CMakeLists.txt b/boards/arm/stm32/maple/src/CMakeLists.txt deleted file mode 100644 index 9eec7a7387bb1..0000000000000 --- a/boards/arm/stm32/maple/src/CMakeLists.txt +++ /dev/null @@ -1,43 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/maple/src/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -set(SRCS stm32_boot.c stm32_leds.c stm32_usbdev.c stm32_spi.c) - -if(CONFIG_NX_LCDDRIVER) - list(APPEND SRCS stm32_lcd.c) -endif() - -if(CONFIG_BOARDCTL) - -endif() - -if(CONFIG_INPUT) - -endif() - -if(CONFIG_USBMSC) - -endif() - -target_sources(board PRIVATE ${SRCS}) - -set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/ld.script") diff --git a/boards/arm/stm32/maple/src/Make.defs b/boards/arm/stm32/maple/src/Make.defs deleted file mode 100644 index 90ae23399e304..0000000000000 --- a/boards/arm/stm32/maple/src/Make.defs +++ /dev/null @@ -1,42 +0,0 @@ -############################################################################ -# boards/arm/stm32/maple/src/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/Make.defs - -CSRCS = stm32_boot.c stm32_leds.c stm32_usbdev.c stm32_spi.c - -ifeq ($(CONFIG_NX_LCDDRIVER),y) -CSRCS += stm32_lcd.c -endif - -ifeq ($(CONFIG_BOARDCTL),y) -endif - -ifeq ($(CONFIG_INPUT),y) -endif - -ifeq ($(CONFIG_USBMSC),y) -endif - -DEPPATH += --dep-path board -VPATH += :board -CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/maple/src/stm32_boot.c b/boards/arm/stm32/maple/src/stm32_boot.c deleted file mode 100644 index 56d8a61eb6d35..0000000000000 --- a/boards/arm/stm32/maple/src/stm32_boot.c +++ /dev/null @@ -1,109 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/maple/src/stm32_boot.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include -#include - -#include -#include - -#include "arm_internal.h" -#include "maple.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_boardinitialize - * - * Description: - * All STM32 architectures must provide the following entry point. This - * entry point is called early in the initialization -- after all memory - * has been configured and mapped but before any devices have been - * initialized. - * - ****************************************************************************/ - -void stm32_boardinitialize(void) -{ - /* Configure on-board LEDs if LED support has been selected. */ - -#ifdef CONFIG_ARCH_LEDS - board_autoled_initialize(); -#endif - - /* Configure SPI chip selects if 1) SPI is not disabled, and 2) the weak - * function stm32_spidev_initialize() has been brought into the link. - */ - -#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) - stm32_spidev_initialize(); -#endif - - /* Initialize USB is 1) USBDEV is selected, 2) the USB controller is not - * disabled, and 3) the weak function stm32_usbinitialize() has been - * brought into the build. - */ - -#if defined(CONFIG_USBDEV) && defined(CONFIG_STM32_USB) - stm32_usbinitialize(); -#endif -} - -/**************************************************************************** - * Name: board_late_initialize - * - * Description: - * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional - * initialization call will be performed in the boot-up sequence to a - * function called board_late_initialize(). board_late_initialize() will - * be called after up_initialize() and board_early_initialize() and just - * before the initial application is started. This additional - * initialization phase may be used, for example, to initialize board- - * specific device drivers for which board_early_initialize() is not - * suitable. - * - * Waiting for events, use of I2C, SPI, etc are permissible in the context - * of board_late_initialize(). That is because board_late_initialize() - * will run on a temporary, internal kernel thread. - * - ****************************************************************************/ - -#ifdef CONFIG_BOARD_LATE_INITIALIZE -void board_late_initialize(void) -{ -} -#endif diff --git a/boards/arm/stm32/maple/src/stm32_lcd.c b/boards/arm/stm32/maple/src/stm32_lcd.c deleted file mode 100644 index b81dc0df3e78c..0000000000000 --- a/boards/arm/stm32/maple/src/stm32_lcd.c +++ /dev/null @@ -1,198 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/maple/src/stm32_lcd.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32.h" -#include "maple.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -#define EXTCOMIN_FREQ 24 -#define TIMER_FREQ 1200 /* 72000000/60000 */ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -static struct lcd_dev_s *l_lcddev; -static struct spi_dev_s *spi; -static struct stm32_tim_dev_s *tim; -static xcpt_t g_isr; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -static int up_lcdextcominisr(int irq, void *context, void *arg) -{ - STM32_TIM_ACKINT(tim, ATIM_SR_UIF); - if (g_isr == NULL) - { - lcderr("ERROR: error, irq not attached, disabled\n"); - STM32_TIM_DISABLEINT(tim, ATIM_DIER_UIE); - return OK; - } - - return g_isr(irq, context, arg); -} - -static int up_lcdirqattach(xcpt_t isr, void * arg) -{ - lcdinfo("%s IRQ\n", isr == NULL ? "Detach" : "Attach"); - - if (isr != NULL) - { - STM32_TIM_SETISR(tim, up_lcdextcominisr, arg, ATIM_SR_UIF); - g_isr = isr; - } - else - { - STM32_TIM_SETISR(tim, NULL, NULL, ATIM_SR_UIF); - g_isr = NULL; - } - - return OK; -} - -static void up_lcddispcontrol(bool on) -{ - lcdinfo("set: %s\n", on ? "on" : "off"); - - if (on) - { - stm32_gpiowrite(GPIO_MEMLCD_DISP, 1); - STM32_TIM_ENABLEINT(tim, ATIM_DIER_UIE); - } - else - { - stm32_gpiowrite(GPIO_MEMLCD_DISP, 0); - STM32_TIM_DISABLEINT(tim, ATIM_DIER_UIE); - } -} - -#ifndef CONFIG_MEMLCD_EXTCOMIN_MODE_HW -static void up_lcdsetpolarity(bool pol) -{ - stm32_gpiowrite(GPIO_LED, pol); - stm32_gpiowrite(GPIO_MEMLCD_EXTCOMIN, pol); -} -#endif - -static void up_lcdsetvcomfreq(unsigned int freq) -{ - lcdinfo("freq: %d\n", freq); - DEBUGASSERT(freq >= 1 && freq <= 60); - STM32_TIM_SETPERIOD(tim, TIMER_FREQ / freq); -} - -static struct memlcd_priv_s memlcd_priv = -{ - .attachirq = up_lcdirqattach, - .dispcontrol = up_lcddispcontrol, -#ifndef CONFIG_MEMLCD_EXTCOMIN_MODE_HW - .setpolarity = up_lcdsetpolarity, -#endif - .setvcomfreq = up_lcdsetvcomfreq, -}; - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_lcd_initialize - * - * Description: - * Initialize the LCD video hardware. The initial state of the LCD is - * fully initialized, display memory cleared, and the LCD ready to use, - * but with the power setting at 0 (full off). - * - ****************************************************************************/ - -int board_lcd_initialize(void) -{ - lcdinfo("Initializing lcd\n"); - - lcdinfo("init spi1\n"); - spi = stm32_spibus_initialize(1); - DEBUGASSERT(spi); - - lcdinfo("configure related io\n"); - stm32_configgpio(GPIO_MEMLCD_EXTCOMIN); - stm32_configgpio(GPIO_MEMLCD_DISP); - - lcdinfo("configure EXTCOMIN timer\n"); - if (tim == NULL) - { - tim = stm32_tim_init(2); - DEBUGASSERT(tim); - STM32_TIM_SETPERIOD(tim, TIMER_FREQ / EXTCOMIN_FREQ); - STM32_TIM_SETCLOCK(tim, TIMER_FREQ); - STM32_TIM_SETMODE(tim, STM32_TIM_MODE_UP); - } - - lcdinfo("init lcd\n"); - l_lcddev = memlcd_initialize(spi, &memlcd_priv, 0); - DEBUGASSERT(l_lcddev); - - return OK; -} - -/**************************************************************************** - * Name: board_lcd_getdev - * - * Description: - * Return a a reference to the LCD object for the specified LCD. This - * allows support for multiple LCD devices. - * - ****************************************************************************/ - -struct lcd_dev_s *board_lcd_getdev(int lcddev) -{ - DEBUGASSERT(lcddev == 0); - return l_lcddev; -} diff --git a/boards/arm/stm32/maple/src/stm32_leds.c b/boards/arm/stm32/maple/src/stm32_leds.c deleted file mode 100644 index b0ae48072052e..0000000000000 --- a/boards/arm/stm32/maple/src/stm32_leds.c +++ /dev/null @@ -1,120 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/maple/src/stm32_leds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32.h" -#include "maple.h" - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -static inline void set_led(bool v) -{ - ledinfo("Turn LED %s\n", v? "on":"off"); - stm32_gpiowrite(GPIO_LED, v); -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_autoled_initialize - ****************************************************************************/ - -#ifdef CONFIG_ARCH_LEDS -void board_autoled_initialize(void) -{ - /* Configure LED GPIO for output */ - - stm32_configgpio(GPIO_LED); -} - -/**************************************************************************** - * Name: board_autoled_on - ****************************************************************************/ - -void board_autoled_on(int led) -{ - ledinfo("board_autoled_on(%d)\n", led); - switch (led) - { - case LED_STARTED: - case LED_HEAPALLOCATE: - /* As the board provides only one soft controllable LED, we simply turn - * it on when the board boots - */ - - set_led(true); - break; - - case LED_PANIC: - - /* For panic state, the LED is blinking */ - - set_led(true); - break; - - default: - break; - } -} - -/**************************************************************************** - * Name: board_autoled_off - ****************************************************************************/ - -void board_autoled_off(int led) -{ - ledinfo("board_autoled_off(%d)\n", led); - - switch (led) - { - case LED_STARTED: - case LED_PANIC: - - /* For panic state, the LED is blinking */ - - set_led(false); - break; - - default: - break; - } -} - -#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/maple/src/stm32_spi.c b/boards/arm/stm32/maple/src/stm32_spi.c deleted file mode 100644 index 22d6bb192e27a..0000000000000 --- a/boards/arm/stm32/maple/src/stm32_spi.c +++ /dev/null @@ -1,138 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/maple/src/stm32_spi.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include - -#include -#include - -#include "arm_internal.h" -#include "chip.h" -#include "stm32.h" -#include "maple.h" - -#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_spidev_initialize - * - * Description: - * Called to configure SPI chip select GPIO pins for the maple board. - * - ****************************************************************************/ - -void weak_function stm32_spidev_initialize(void) -{ - /* NOTE: Clocking for SPI1 and/or SPI2 was already provided in stm32_rcc.c. - * Configurations of SPI pins is performed in stm32_spi.c. - * Here, we only initialize chip select pins unique to the board - * architecture. - */ - - stm32_configgpio(GPIO_MEMLCD_CS); -} - -/**************************************************************************** - * Name: stm32_spi1/2select and stm32_spi1/2status - * - * Description: - * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status - * must be provided by board-specific logic. They are implementations of - * the select and status methods of the SPI interface defined by struct - * spi_ops_s (see include/nuttx/spi/spi.h). All other methods (including - * stm32_spibus_initialize()) are provided by common STM32 logic. - * To use this common SPI logic on your board: - * - * 1. Provide logic in stm32_boardinitialize() to configure SPI chip - * select pins. - * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() functions - * in your board-specific logic. These functions will perform chip - * selection and status operations using GPIOs in the way your board is - * configured. - * 3. Add a calls to stm32_spibus_initialize() in your low level - * application initialization logic - * 4. The handle returned by stm32_spibus_initialize() may then be used to - * bind the SPI driver to higher level logic (e.g., calling - * mmcsd_spislotinitialize(), for example, will bind the SPI driver to - * the SPI MMC/SD driver). - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_SPI1 -void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, - bool selected) -{ - spiinfo("devid: %d CS: %s\n", - (int)devid, selected ? "assert" : "de-assert"); - -# if defined(CONFIG_LCD_SHARP_MEMLCD) - if (devid == SPIDEV_DISPLAY(0)) - { - stm32_gpiowrite(GPIO_MEMLCD_CS, selected); - } -# endif -} - -uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) -{ - return 0; -} - -int stm32_spi1cmddata(struct spi_dev_s *dev, - uint32_t devid, bool cmd) -{ - return -ENODEV; -} -#endif - -#ifdef CONFIG_STM32_SPI2 -void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid, - bool selected) -{ -} - -uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) -{ - return 0; -} - -int stm32_spi1cmddata(struct spi_dev_s *dev, - uint32_t devid, bool cmd) -{ - return -ENODEV; -} -#endif - -#endif /* CONFIG_STM32_SPI1 || CONFIG_STM32_SPI2 */ diff --git a/boards/arm/stm32/maple/src/stm32_usbdev.c b/boards/arm/stm32/maple/src/stm32_usbdev.c deleted file mode 100644 index 648bfe8a9295c..0000000000000 --- a/boards/arm/stm32/maple/src/stm32_usbdev.c +++ /dev/null @@ -1,103 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/maple/src/stm32_usbdev.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include - -#include -#include - -#include "arm_internal.h" -#include "stm32.h" -#include "maple.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_usbinitialize - * - * Description: - * Called to setup USB-related GPIO pins. - * - ****************************************************************************/ - -void stm32_usbinitialize(void) -{ - uinfo("called\n"); - - /* USB Soft Connect Pullup */ - - stm32_configgpio(GPIO_USB_PULLUP); -} - -/**************************************************************************** - * Name: stm32_usbpullup - * - * Description: - * If USB is supported and the board supports a pullup via GPIO (for USB - * software connect and disconnect), then the board software must provide - * stm32_pullup. See include/nuttx/usb/usbdev.h for additional description - * of this method. Alternatively, if no pull-up GPIO the following EXTERN - * can be redefined to be NULL. - * - ****************************************************************************/ - -int stm32_usbpullup(struct usbdev_s *dev, bool enable) -{ - usbtrace(TRACE_DEVPULLUP, (uint16_t)enable); - stm32_gpiowrite(GPIO_USB_PULLUP, !enable); - return OK; -} - -/**************************************************************************** - * Name: stm32_usbsuspend - * - * Description: - * Board logic must provide the stm32_usbsuspend logic if the USBDEV driver - * is used. This function is called whenever the USB enters or leaves - * suspend mode. This is an opportunity for the board logic to shutdown - * clocks, power, etc. while the USB is suspended. - * - ****************************************************************************/ - -void stm32_usbsuspend(struct usbdev_s *dev, bool resume) -{ - uinfo("resume: %d\n", resume); -} diff --git a/boards/arm/stm32/mikroe-stm32f4/CMakeLists.txt b/boards/arm/stm32/mikroe-stm32f4/CMakeLists.txt deleted file mode 100644 index 1f40202c3298f..0000000000000 --- a/boards/arm/stm32/mikroe-stm32f4/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/mikroe-stm32f4/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32/mikroe-stm32f4/configs/fulldemo/defconfig b/boards/arm/stm32/mikroe-stm32f4/configs/fulldemo/defconfig deleted file mode 100644 index 7413ebbd7f9db..0000000000000 --- a/boards/arm/stm32/mikroe-stm32f4/configs/fulldemo/defconfig +++ /dev/null @@ -1,136 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_DEV_CONSOLE is not set -# CONFIG_NSH_DISABLE_IFCONFIG is not set -# CONFIG_NSH_DISABLE_PS is not set -# CONFIG_NXFONTS_DISABLE_16BPP is not set -# CONFIG_NXPLAYER_INCLUDE_PREFERRED_DEVICE is not set -# CONFIG_NXTK_DEFAULT_BORDERCOLORS is not set -# CONFIG_NX_DISABLE_16BPP is not set -# CONFIG_SPI_CALLBACK is not set -# CONFIG_STM32_CCMEXCLUDE is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="mikroe-stm32f4" -CONFIG_ARCH_BOARD_MIKROE_STM32F4=y -CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F407VG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_AUDIO=y -CONFIG_AUDIO_FORMAT_MIDI=y -CONFIG_AUDIO_VS1053=y -CONFIG_BOARDCTL_USBDEVCTRL=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_CDCACM=y -CONFIG_CDCACM_CONSOLE=y -CONFIG_CDCACM_RXBUFSIZE=256 -CONFIG_CDCACM_TXBUFSIZE=256 -CONFIG_DEBUG_SYMBOLS=y -CONFIG_DEV_LOOP=y -CONFIG_DRIVERS_AUDIO=y -CONFIG_ETC_FATDEVNO=0 -CONFIG_ETC_ROMFS=y -CONFIG_EXAMPLES_NX=y -CONFIG_EXAMPLES_NX_BPP=16 -CONFIG_EXAMPLES_TOUCHSCREEN=y -CONFIG_FS_BINFS=y -CONFIG_FS_FAT=y -CONFIG_FS_ROMFS=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_IDLETHREAD_STACKSIZE=2048 -CONFIG_INIT_ENTRYPOINT="nxwm_main" -CONFIG_INPUT=y -CONFIG_INTELHEX_BINARY=y -CONFIG_LCD=y -CONFIG_LCD_MIO283QT2=y -CONFIG_LIBC_MAX_EXITFUNS=4 -CONFIG_LIBC_PERROR_STDOUT=y -CONFIG_LIBC_STRERROR=y -CONFIG_LINE_MAX=64 -CONFIG_M25P_MANUFACTURER=0x1C -CONFIG_M25P_MEMORY_TYPE=0x31 -CONFIG_M25P_SUBSECTOR_ERASE=y -CONFIG_MIKROE_FLASH=y -CONFIG_MIKROE_FLASH_PART=y -CONFIG_MMCSD=y -CONFIG_MMCSD_SPICLOCK=30000000 -CONFIG_MM_REGIONS=2 -CONFIG_MQ_MAXMSGSIZE=64 -CONFIG_MTD_CONFIG=y -CONFIG_MTD_PARTITION=y -CONFIG_MTD_SMART_SECTOR_SIZE=512 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_NSH_STRERROR=y -CONFIG_NX=y -CONFIG_NXFONT_SANS17X23B=y -CONFIG_NXFONT_SANS20X27B=y -CONFIG_NXFONT_SANS22X29B=y -CONFIG_NXFONT_SANS28X37B=y -CONFIG_NXFONT_SERIF22X28B=y -CONFIG_NXPLAYER_DEFAULT_MEDIADIR="/usr/sounds" -CONFIG_NXPLAYER_INCLUDE_SYSTEM_RESET=y -CONFIG_NXTERM=y -CONFIG_NXTERM_CURSORCHAR=95 -CONFIG_NXTK_BORDERCOLOR1=0x8410 -CONFIG_NXTK_BORDERCOLOR2=0x4208 -CONFIG_NXTK_BORDERCOLOR3=0xc618 -CONFIG_NXTK_BORDERWIDTH=3 -CONFIG_NXWIDGETS=y -CONFIG_NXWIDGETS_BPP=16 -CONFIG_NXWIDGETS_SIZEOFCHAR=1 -CONFIG_NXWM=y -CONFIG_NXWM_BACKGROUND_IMAGE="" -CONFIG_NXWM_HEXCALCULATOR_BACKGROUNDCOLOR=0x39C7 -CONFIG_NXWM_HEXCALCULATOR_CUSTOM_COLORS=y -CONFIG_NXWM_KEYBOARD=y -CONFIG_NXWM_KEYBOARD_DEVPATH="/dev/ttyS0" -CONFIG_NXWM_KEYBOARD_LISTENERPRIO=100 -CONFIG_NXWM_MEDIAPLAYER=y -CONFIG_NXWM_TASKBAR_LEFT=y -CONFIG_NXWM_TOUCHSCREEN_CONFIGDATA=y -CONFIG_NXWM_TOUCHSCREEN_LISTENERPRIO=100 -CONFIG_NX_BLOCKING=y -CONFIG_NX_KBD=y -CONFIG_NX_XYINPUT_TOUCHSCREEN=y -CONFIG_PLATFORM_CONFIGDATA=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAMMTD=y -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_RTC_ALARM=y -CONFIG_RTC_DATETIME=y -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_HPWORKPRIORITY=192 -CONFIG_SCHED_WAITPID=y -CONFIG_STM32_ADC2=y -CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32_DMA1=y -CONFIG_STM32_FLASH_PREFETCH=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_OTGFS=y -CONFIG_STM32_PWR=y -CONFIG_STM32_RNG=y -CONFIG_STM32_RTC=y -CONFIG_STM32_SPI2=y -CONFIG_STM32_TIM1=y -CONFIG_STM32_USART2=y -CONFIG_SYSLOG_CHAR=y -CONFIG_SYSLOG_DEVPATH="/dev/ttyS0" -CONFIG_SYSTEM_FLASH_ERASEALL=y -CONFIG_SYSTEM_NSH=y -CONFIG_SYSTEM_NXPLAYER=y -CONFIG_TASK_NAME_SIZE=11 -CONFIG_USBDEV=y diff --git a/boards/arm/stm32/mikroe-stm32f4/configs/kostest/defconfig b/boards/arm/stm32/mikroe-stm32f4/configs/kostest/defconfig deleted file mode 100644 index e89262a68b986..0000000000000 --- a/boards/arm/stm32/mikroe-stm32f4/configs/kostest/defconfig +++ /dev/null @@ -1,83 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_DEV_CONSOLE is not set -# CONFIG_NSH_DISABLE_IFCONFIG is not set -# CONFIG_SPI_CALLBACK is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="mikroe-stm32f4" -CONFIG_ARCH_BOARD_MIKROE_STM32F4=y -CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F407VG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_ARM_MPU=y -CONFIG_BOARDCTL_USBDEVCTRL=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILD_PROTECTED=y -CONFIG_CDCACM=y -CONFIG_CDCACM_CONSOLE=y -CONFIG_CDCACM_RXBUFSIZE=256 -CONFIG_CDCACM_TXBUFSIZE=256 -CONFIG_DEBUG_SYMBOLS=y -CONFIG_DEV_LOOP=y -CONFIG_FS_FAT=y -CONFIG_FS_ROMFS=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_IDLETHREAD_STACKSIZE=2048 -CONFIG_INIT_ENTRYPOINT="ostest_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LIBC_MAX_EXITFUNS=4 -CONFIG_LIBC_PERROR_STDOUT=y -CONFIG_LIBC_STRERROR=y -CONFIG_LINE_MAX=64 -CONFIG_M25P_MANUFACTURER=0x1C -CONFIG_M25P_MEMORY_TYPE=0x31 -CONFIG_M25P_SUBSECTOR_ERASE=y -CONFIG_MIKROE_FLASH=y -CONFIG_MIKROE_FLASH_PART=y -CONFIG_MIKROE_FLASH_PART_LIST="256,768" -CONFIG_MMCSD=y -CONFIG_MM_REGIONS=2 -CONFIG_MTD_PARTITION=y -CONFIG_MTD_SMART_SECTOR_SIZE=512 -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_NSH_STRERROR=y -CONFIG_NUTTX_USERSPACE=0x08020000 -CONFIG_PASS1_BUILDIR="boards/arm/stm32/mikroe-stm32f4/kernel" -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAMMTD=y -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_RTC_ALARM=y -CONFIG_RTC_DATETIME=y -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_HPWORKPRIORITY=192 -CONFIG_SCHED_WAITPID=y -CONFIG_STM32_ADC2=y -CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32_FLASH_PREFETCH=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_OTGFS=y -CONFIG_STM32_PWR=y -CONFIG_STM32_RNG=y -CONFIG_STM32_RTC=y -CONFIG_STM32_SPI2=y -CONFIG_STM32_TIM1=y -CONFIG_STM32_USART2=y -CONFIG_SYSLOG_CHAR=y -CONFIG_SYSLOG_DEVPATH="/dev/ttyS0" -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=11 -CONFIG_TESTING_OSTEST=y -CONFIG_USBDEV=y diff --git a/boards/arm/stm32/mikroe-stm32f4/configs/nsh/defconfig b/boards/arm/stm32/mikroe-stm32f4/configs/nsh/defconfig deleted file mode 100644 index 78dfe980601ea..0000000000000 --- a/boards/arm/stm32/mikroe-stm32f4/configs/nsh/defconfig +++ /dev/null @@ -1,69 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_DEV_CONSOLE is not set -# CONFIG_DISABLE_OS_API is not set -# CONFIG_NSH_DISABLE_IFCONFIG is not set -# CONFIG_NSH_DISABLE_PS is not set -# CONFIG_SPI_CALLBACK is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="mikroe-stm32f4" -CONFIG_ARCH_BOARD_MIKROE_STM32F4=y -CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F407VG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_DEV_LOOP=y -CONFIG_FS_FAT=y -CONFIG_FS_ROMFS=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_IDLETHREAD_STACKSIZE=2048 -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LIBC_PERROR_STDOUT=y -CONFIG_LIBC_STRERROR=y -CONFIG_LINE_MAX=64 -CONFIG_M25P_MANUFACTURER=0x1C -CONFIG_M25P_MEMORY_TYPE=0x31 -CONFIG_M25P_SUBSECTOR_ERASE=y -CONFIG_MIKROE_FLASH=y -CONFIG_MIKROE_FLASH_PART=y -CONFIG_MIKROE_FLASH_PART_LIST="256,768" -CONFIG_MMCSD=y -CONFIG_MM_REGIONS=2 -CONFIG_MTD_PARTITION=y -CONFIG_MTD_SMART_SECTOR_SIZE=512 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_NSH_STRERROR=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAMMTD=y -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=27 -CONFIG_START_YEAR=2013 -CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_PWR=y -CONFIG_STM32_RNG=y -CONFIG_STM32_SPI2=y -CONFIG_STM32_USART2=y -CONFIG_SYSLOG_CHAR=y -CONFIG_SYSLOG_DEVPATH="/dev/ttyS0" -CONFIG_SYSTEM_FLASH_ERASEALL=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/mikroe-stm32f4/configs/nx/defconfig b/boards/arm/stm32/mikroe-stm32f4/configs/nx/defconfig deleted file mode 100644 index c8b0ef583d7e5..0000000000000 --- a/boards/arm/stm32/mikroe-stm32f4/configs/nx/defconfig +++ /dev/null @@ -1,65 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_DEV_CONSOLE is not set -# CONFIG_NSH_DISABLE_IFCONFIG is not set -# CONFIG_NSH_DISABLE_PS is not set -# CONFIG_NXFONTS_DISABLE_16BPP is not set -# CONFIG_NXTK_DEFAULT_BORDERCOLORS is not set -# CONFIG_NX_DISABLE_16BPP is not set -# CONFIG_SERIAL is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="mikroe-stm32f4" -CONFIG_ARCH_BOARD_MIKROE_STM32F4=y -CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F407VG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_EXAMPLES_NX=y -CONFIG_EXAMPLES_NX_BPP=16 -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_IDLETHREAD_STACKSIZE=2048 -CONFIG_INIT_ENTRYPOINT="nx_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LCD=y -CONFIG_LCD_MIO283QT2=y -CONFIG_LIBC_PERROR_STDOUT=y -CONFIG_LIBC_STRERROR=y -CONFIG_LINE_MAX=64 -CONFIG_MM_REGIONS=2 -CONFIG_MQ_MAXMSGSIZE=64 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_LIBRARY=y -CONFIG_NSH_READLINE=y -CONFIG_NSH_STRERROR=y -CONFIG_NX=y -CONFIG_NXFONT_SERIF22X28B=y -CONFIG_NXTK_BORDERCOLOR1=0x8410 -CONFIG_NXTK_BORDERCOLOR2=0x4208 -CONFIG_NXTK_BORDERCOLOR3=0xc618 -CONFIG_NXTK_BORDERWIDTH=3 -CONFIG_NX_BLOCKING=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=27 -CONFIG_START_YEAR=2013 -CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_PWR=y -CONFIG_SYSLOG_CHAR=y -CONFIG_SYSLOG_DEVPATH="/dev/ttyS0" -CONFIG_TASK_NAME_SIZE=0 diff --git a/boards/arm/stm32/mikroe-stm32f4/configs/nxlines/defconfig b/boards/arm/stm32/mikroe-stm32f4/configs/nxlines/defconfig deleted file mode 100644 index 9245c04e424dd..0000000000000 --- a/boards/arm/stm32/mikroe-stm32f4/configs/nxlines/defconfig +++ /dev/null @@ -1,69 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_DEV_CONSOLE is not set -# CONFIG_EXAMPLES_NXLINES_DEFAULT_COLORS is not set -# CONFIG_NSH_DISABLE_IFCONFIG is not set -# CONFIG_NSH_DISABLE_PS is not set -# CONFIG_NXFONTS_DISABLE_16BPP is not set -# CONFIG_NXTK_DEFAULT_BORDERCOLORS is not set -# CONFIG_NX_DISABLE_16BPP is not set -# CONFIG_NX_WRITEONLY is not set -# CONFIG_SERIAL is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="mikroe-stm32f4" -CONFIG_ARCH_BOARD_MIKROE_STM32F4=y -CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F407VG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_EXAMPLES_NXLINES=y -CONFIG_EXAMPLES_NXLINES_BGCOLOR=0x0 -CONFIG_EXAMPLES_NXLINES_BORDERCOLOR=0xFFE0 -CONFIG_EXAMPLES_NXLINES_BPP=16 -CONFIG_EXAMPLES_NXLINES_CIRCLECOLOR=0x87F0 -CONFIG_EXAMPLES_NXLINES_LINECOLOR=0x861F -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_IDLETHREAD_STACKSIZE=2048 -CONFIG_INIT_ENTRYPOINT="nxlines_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LCD=y -CONFIG_LCD_MIO283QT2=y -CONFIG_LCD_NOGETRUN=y -CONFIG_LINE_MAX=64 -CONFIG_MM_REGIONS=2 -CONFIG_MQ_MAXMSGSIZE=64 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_LIBRARY=y -CONFIG_NSH_READLINE=y -CONFIG_NX=y -CONFIG_NXFONT_SERIF22X28B=y -CONFIG_NXTK_BORDERCOLOR1=0x8410 -CONFIG_NXTK_BORDERCOLOR2=0x4208 -CONFIG_NXTK_BORDERCOLOR3=0xc618 -CONFIG_NXTK_BORDERWIDTH=3 -CONFIG_NX_BLOCKING=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=27 -CONFIG_START_YEAR=2013 -CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_PWR=y -CONFIG_SYSLOG_CHAR=y -CONFIG_SYSLOG_DEVPATH="/dev/ttyS0" -CONFIG_TASK_NAME_SIZE=0 diff --git a/boards/arm/stm32/mikroe-stm32f4/configs/nxtext/defconfig b/boards/arm/stm32/mikroe-stm32f4/configs/nxtext/defconfig deleted file mode 100644 index 7959ef4608663..0000000000000 --- a/boards/arm/stm32/mikroe-stm32f4/configs/nxtext/defconfig +++ /dev/null @@ -1,63 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_DEV_CONSOLE is not set -# CONFIG_NSH_DISABLE_IFCONFIG is not set -# CONFIG_NSH_DISABLE_PS is not set -# CONFIG_NXFONTS_DISABLE_16BPP is not set -# CONFIG_NXTK_DEFAULT_BORDERCOLORS is not set -# CONFIG_NX_DISABLE_16BPP is not set -# CONFIG_SERIAL is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="mikroe-stm32f4" -CONFIG_ARCH_BOARD_MIKROE_STM32F4=y -CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F407VG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_EXAMPLES_NXTEXT=y -CONFIG_EXAMPLES_NXTEXT_BPP=16 -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_IDLETHREAD_STACKSIZE=2048 -CONFIG_INIT_ENTRYPOINT="nxtext_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LCD=y -CONFIG_LCD_MIO283QT2=y -CONFIG_LINE_MAX=64 -CONFIG_MM_REGIONS=2 -CONFIG_MQ_MAXMSGSIZE=64 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_LIBRARY=y -CONFIG_NSH_READLINE=y -CONFIG_NX=y -CONFIG_NXFONT_SERIF22X28B=y -CONFIG_NXTK_BORDERCOLOR1=0x8410 -CONFIG_NXTK_BORDERCOLOR2=0x4208 -CONFIG_NXTK_BORDERCOLOR3=0xc618 -CONFIG_NXTK_BORDERWIDTH=3 -CONFIG_NX_BLOCKING=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=27 -CONFIG_START_YEAR=2013 -CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_PWR=y -CONFIG_SYSLOG_CHAR=y -CONFIG_SYSLOG_DEVPATH="/dev/ttyS0" -CONFIG_TASK_NAME_SIZE=0 diff --git a/boards/arm/stm32/mikroe-stm32f4/configs/usbnsh/defconfig b/boards/arm/stm32/mikroe-stm32f4/configs/usbnsh/defconfig deleted file mode 100644 index c011fdde8bb9b..0000000000000 --- a/boards/arm/stm32/mikroe-stm32f4/configs/usbnsh/defconfig +++ /dev/null @@ -1,74 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_DEV_CONSOLE is not set -# CONFIG_NSH_DISABLE_IFCONFIG is not set -# CONFIG_NSH_DISABLE_PS is not set -# CONFIG_SPI_CALLBACK is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="mikroe-stm32f4" -CONFIG_ARCH_BOARD_MIKROE_STM32F4=y -CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F407VG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARDCTL_USBDEVCTRL=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_CDCACM=y -CONFIG_CDCACM_CONSOLE=y -CONFIG_CDCACM_RXBUFSIZE=256 -CONFIG_CDCACM_TXBUFSIZE=256 -CONFIG_DEV_LOOP=y -CONFIG_FS_FAT=y -CONFIG_FS_ROMFS=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_IDLETHREAD_STACKSIZE=2048 -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LIBC_PERROR_STDOUT=y -CONFIG_LIBC_STRERROR=y -CONFIG_LINE_MAX=64 -CONFIG_M25P_MANUFACTURER=0x1C -CONFIG_M25P_MEMORY_TYPE=0x31 -CONFIG_M25P_SUBSECTOR_ERASE=y -CONFIG_MIKROE_FLASH=y -CONFIG_MIKROE_FLASH_PART=y -CONFIG_MIKROE_FLASH_PART_LIST="256,768" -CONFIG_MIKROE_RAMMTD=y -CONFIG_MMCSD=y -CONFIG_MM_REGIONS=2 -CONFIG_MTD_PARTITION=y -CONFIG_MTD_SMART_SECTOR_SIZE=512 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_NSH_STRERROR=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=27 -CONFIG_START_YEAR=2013 -CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_OTGFS=y -CONFIG_STM32_PWR=y -CONFIG_STM32_RNG=y -CONFIG_STM32_SPI2=y -CONFIG_STM32_USART2=y -CONFIG_SYSLOG_CHAR=y -CONFIG_SYSLOG_DEVPATH="/dev/ttyS0" -CONFIG_SYSTEM_FLASH_ERASEALL=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USBDEV=y diff --git a/boards/arm/stm32/mikroe-stm32f4/include/board.h b/boards/arm/stm32/mikroe-stm32f4/include/board.h deleted file mode 100644 index 7c5d365a96b7f..0000000000000 --- a/boards/arm/stm32/mikroe-stm32f4/include/board.h +++ /dev/null @@ -1,251 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/mikroe-stm32f4/include/board.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __BOARDS_ARM_STM32_MIKROE_STM32F4_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32_MIKROE_STM32F4_INCLUDE_BOARD_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#ifndef __ASSEMBLY__ -# include -#endif - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Clocking *****************************************************************/ - -/* The Mikroe STM32F4 Mikromedia board features a single 32kHz crystal. - * The main clock uses the internal 16Mhz RC oscillator. - * - * This is the canonical configuration: - * System Clock source :PLL (HSE) - * SYSCLK(Hz) :168000000 Determined by PLL configuration - * HCLK(Hz) :168000000 (STM32_RCC_CFGR_HPRE) - * AHB Prescaler :1 (STM32_RCC_CFGR_HPRE) - * APB1 Prescaler :4 (STM32_RCC_CFGR_PPRE1) - * APB2 Prescaler :2 (STM32_RCC_CFGR_PPRE2) - * HSI Frequency(Hz) :16000000 (STM32_HSI_FREQUENCY) - * PLLM :16 (STM32_PLLCFG_PLLM) - * PLLN :36 (STM32_PLLCFG_PLLN) - * PLLP :2 (STM32_PLLCFG_PLLP) - * PLLQ :7 (STM32_PLLCFG_PLLQ) - * Main regulator output voltage :Scale1 mode Needed for high speed SYSCLK - * Flash Latency(WS) :5 - * Prefetch Buffer :OFF - * Instruction cache :ON - * Data cache :ON - * Require 48MHz for USB OTG FS, :Enabled - * SDIO and RNG clock - */ - -/* HSI - 16 MHz RC factory-trimmed - * LSI - 32 KHz RC - * HSE - On-board crystal frequency is 8MHz - * LSE - 32.768 kHz - */ - -#define STM32_BOARD_XTAL 8000000ul - -#define STM32_HSI_FREQUENCY 16000000ul -#define STM32_LSI_FREQUENCY 32000 -#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL -#define STM32_LSE_FREQUENCY 32768 - -/* Main PLL Configuration. - * - * PLL source is HSI - * PLL_VCO = (STM32_HSI_FREQUENCY / PLLM) * PLLN - * = (16,000,000 / 16) * 336 - * = 336,000,000 - * SYSCLK = PLL_VCO / PLLP - * = 336,000,000 / 2 = 168,000,000 - * USB OTG FS, SDIO and RNG Clock - * = PLL_VCO / PLLQ - * = 48,000,000 - */ - -#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(16) -#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(336) -#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_2 -#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(7) - -#define STM32_SYSCLK_FREQUENCY 168000000ul - -/* AHB clock (HCLK) is SYSCLK (168MHz) */ - -#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ -#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY - -/* APB1 clock (PCLK1) is HCLK/4 (42MHz) */ - -#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd4 /* PCLK1 = HCLK / 4 */ -#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/4) - -/* Timers driven from APB1 will be twice PCLK1 */ - -#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) - -/* APB2 clock (PCLK2) is HCLK/2 (84MHz) */ - -#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLKd2 /* PCLK2 = HCLK / 2 */ -#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/2) - -/* Timers driven from APB2 will be twice PCLK2 */ - -#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM9_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM10_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM11_CLKIN (2*STM32_PCLK2_FREQUENCY) - -/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx - * otherwise frequency is 2xAPBx. - * Note: TIM1,8 are on APB2, others on APB1 - */ - -#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM2_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM3_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM4_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM5_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM6_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM7_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY - -/* LED definitions **********************************************************/ - -/* If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs in - * any way. The following definitions are used to access individual LEDs. - */ - -/* LED index values for use with board_userled() */ - -#if 0 -#define BOARD_LED1 0 -#define BOARD_LED2 1 -#define BOARD_LED3 2 -#define BOARD_LED4 3 -#endif -#define BOARD_NLEDS 0 - -#if 0 -#define BOARD_LED_GREEN BOARD_LED1 -#define BOARD_LED_ORANGE BOARD_LED2 -#define BOARD_LED_RED BOARD_LED3 -#define BOARD_LED_BLUE BOARD_LED4 - -/* LED bits for use with board_userled_all() */ - -#define BOARD_LED1_BIT (1 << BOARD_LED1) -#define BOARD_LED2_BIT (1 << BOARD_LED2) -#define BOARD_LED3_BIT (1 << BOARD_LED3) -#define BOARD_LED4_BIT (1 << BOARD_LED4) - -/* If CONFIG_ARCH_LEDs is defined, - * then NuttX will control the 4 LEDs on board the stm32f4discovery. - * The following definitions describe how NuttX controls the LEDs: - */ - -#define LED_STARTED 0 /* LED1 */ -#define LED_HEAPALLOCATE 1 /* LED2 */ -#define LED_IRQSENABLED 2 /* LED1 + LED2 */ -#define LED_STACKCREATED 3 /* LED3 */ -#define LED_INIRQ 4 /* LED1 + LED3 */ -#define LED_SIGNAL 5 /* LED2 + LED3 */ -#define LED_ASSERTION 6 /* LED1 + LED2 + LED3 */ -#define LED_PANIC 7 /* N/C + N/C + N/C + LED4 */ - -/* Button definitions *******************************************************/ - -/* The STM32F4 Discovery supports one button: */ - -#define BUTTON_USER 0 - -#define NUM_BUTTONS 0 - -#define BUTTON_USER_BIT (1 << BUTTON_USER) - -#endif /* 0 */ - -/* Alternate function pin selections ****************************************/ - -/* UART2: - * - * The Mikroe-STM32F4 board has no on-board serial devices, but it brings out - * UART2 to the expansion header. - */ - -#define GPIO_USART2_RX (GPIO_USART2_RX_2|GPIO_SPEED_100MHz) -#define GPIO_USART2_TX (GPIO_USART2_TX_2|GPIO_SPEED_100MHz) - -/* PWM - * - * The STM32F4 Discovery has no real on-board PWM devices, but the board can - * be configured to output a pulse train using TIM4 CH2 on PD13. - */ - -#define GPIO_TIM4_CH2OUT (GPIO_TIM4_CH2OUT_2|GPIO_SPEED_50MHz) - -/* SPI - Onboard devices use SPI3, plus SPI2 routes to the I/O header */ - -#define GPIO_SPI2_MISO (GPIO_SPI2_MISO_1|GPIO_SPEED_50MHz) -#define GPIO_SPI2_MOSI (GPIO_SPI2_MOSI_1|GPIO_SPEED_50MHz) -#define GPIO_SPI2_SCK (GPIO_SPI2_SCK_2|GPIO_SPEED_50MHz) -#define DMACHAN_SPI2_RX DMAMAP_SPI2_RX -#define DMACHAN_SPI2_TX DMAMAP_SPI2_TX - -#define GPIO_SPI3_MISO (GPIO_SPI3_MISO_2|GPIO_SPEED_50MHz) -#define GPIO_SPI3_MOSI (GPIO_SPI3_MOSI_2|GPIO_SPEED_50MHz) -#define GPIO_SPI3_SCK (GPIO_SPI3_SCK_2|GPIO_SPEED_50MHz) -#define DMACHAN_SPI3_RX DMAMAP_SPI3_RX_2 -#define DMACHAN_SPI3_TX DMAMAP_SPI3_TX_2 - -/* Timer Inputs/Outputs */ - -#define GPIO_TIM2_CH1IN (GPIO_TIM2_CH1IN_2|GPIO_SPEED_50MHz) -#define GPIO_TIM2_CH2IN (GPIO_TIM2_CH2IN_1|GPIO_SPEED_50MHz) - -#define GPIO_TIM8_CH1IN (GPIO_TIM8_CH1IN_1|GPIO_SPEED_50MHz) -#define GPIO_TIM8_CH2IN (GPIO_TIM8_CH2IN_1|GPIO_SPEED_50MHz) - -/* USB OTG FS */ - -#define GPIO_OTGFS_DM (GPIO_OTGFS_DM_0|GPIO_SPEED_100MHz) -#define GPIO_OTGFS_DP (GPIO_OTGFS_DP_0|GPIO_SPEED_100MHz) -#define GPIO_OTGFS_ID (GPIO_OTGFS_ID_0|GPIO_SPEED_100MHz) -#define GPIO_OTGFS_SOF (GPIO_OTGFS_SOF_0|GPIO_SPEED_100MHz) - -#endif /* __BOARDS_ARM_STM32_MIKROE_STM32F4_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32/mikroe-stm32f4/kernel/Makefile b/boards/arm/stm32/mikroe-stm32f4/kernel/Makefile deleted file mode 100644 index 6983f10eff198..0000000000000 --- a/boards/arm/stm32/mikroe-stm32f4/kernel/Makefile +++ /dev/null @@ -1,94 +0,0 @@ -############################################################################ -# boards/arm/stm32/mikroe-stm32f4/kernel/Makefile -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/Make.defs - -# The entry point name (if none is provided in the .config file) - -CONFIG_INIT_ENTRYPOINT ?= user_start -ENTRYPT = $(patsubst "%",%,$(CONFIG_INIT_ENTRYPOINT)) - -# Get the paths to the libraries and the links script path in format that -# is appropriate for the host OS - -USER_LIBPATHS = $(addprefix -L,$(call CONVERT_PATH,$(addprefix $(TOPDIR)$(DELIM),$(dir $(USERLIBS))))) -USER_LDSCRIPT = -T $(call CONVERT_PATH,$(BOARD_DIR)$(DELIM)scripts$(DELIM)memory.ld) -USER_LDSCRIPT += -T $(call CONVERT_PATH,$(BOARD_DIR)$(DELIM)scripts$(DELIM)user-space.ld) -USER_HEXFILE += $(call CONVERT_PATH,$(TOPDIR)$(DELIM)nuttx_user.hex) -USER_SRECFILE += $(call CONVERT_PATH,$(TOPDIR)$(DELIM)nuttx_user.srec) -USER_BINFILE += $(call CONVERT_PATH,$(TOPDIR)$(DELIM)nuttx_user.bin) - -USER_LDFLAGS = --undefined=$(ENTRYPT) --entry=$(ENTRYPT) $(USER_LDSCRIPT) -USER_LDLIBS = $(patsubst lib%,-l%,$(basename $(notdir $(USERLIBS)))) -USER_LIBGCC = "${shell "$(CC)" $(ARCHCPUFLAGS) -print-libgcc-file-name}" - -# Source files - -CSRCS = stm32_userspace.c -COBJS = $(CSRCS:.c=$(OBJEXT)) -OBJS = $(COBJS) - -# Targets: - -all: $(TOPDIR)$(DELIM)nuttx_user.elf $(TOPDIR)$(DELIM)User.map -.PHONY: nuttx_user.elf depend clean distclean - -$(COBJS): %$(OBJEXT): %.c - $(call COMPILE, $<, $@) - -# Create the nuttx_user.elf file containing all of the user-mode code - -nuttx_user.elf: $(OBJS) - $(Q) $(LD) -o $@ $(USER_LDFLAGS) $(USER_LIBPATHS) $(OBJS) --start-group $(USER_LDLIBS) --end-group $(USER_LIBGCC) - -$(TOPDIR)$(DELIM)nuttx_user.elf: nuttx_user.elf - @echo "LD: nuttx_user.elf" - $(Q) cp -a nuttx_user.elf $(TOPDIR)$(DELIM)nuttx_user.elf -ifeq ($(CONFIG_INTELHEX_BINARY),y) - @echo "CP: nuttx_user.hex" - $(Q) $(OBJCOPY) $(OBJCOPYARGS) -O ihex nuttx_user.elf $(USER_HEXFILE) -endif -ifeq ($(CONFIG_MOTOROLA_SREC),y) - @echo "CP: nuttx_user.srec" - $(Q) $(OBJCOPY) $(OBJCOPYARGS) -O srec nuttx_user.elf $(USER_SRECFILE) -endif -ifeq ($(CONFIG_RAW_BINARY),y) - @echo "CP: nuttx_user.bin" - $(Q) $(OBJCOPY) $(OBJCOPYARGS) -O binary nuttx_user.elf $(USER_BINFILE) -endif - -$(TOPDIR)$(DELIM)User.map: nuttx_user.elf - @echo "MK: User.map" - $(Q) $(NM) nuttx_user.elf >$(TOPDIR)$(DELIM)User.map - $(Q) $(CROSSDEV)size nuttx_user.elf - -.depend: - -depend: .depend - -clean: - $(call DELFILE, nuttx_user.elf) - $(call DELFILE, "$(TOPDIR)$(DELIM)nuttx_user.*") - $(call DELFILE, "$(TOPDIR)$(DELIM)User.map") - $(call CLEAN) - -distclean: clean diff --git a/boards/arm/stm32/mikroe-stm32f4/kernel/stm32_userspace.c b/boards/arm/stm32/mikroe-stm32f4/kernel/stm32_userspace.c deleted file mode 100644 index 81c267d2fd5fe..0000000000000 --- a/boards/arm/stm32/mikroe-stm32f4/kernel/stm32_userspace.c +++ /dev/null @@ -1,110 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/mikroe-stm32f4/kernel/stm32_userspace.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include -#include -#include - -#if defined(CONFIG_BUILD_PROTECTED) && !defined(__KERNEL__) - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -#ifndef CONFIG_NUTTX_USERSPACE -# error "CONFIG_NUTTX_USERSPACE not defined" -#endif - -#if CONFIG_NUTTX_USERSPACE != 0x08020000 -# error "CONFIG_NUTTX_USERSPACE must be 0x08020000 to match memory.ld" -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -static struct userspace_data_s g_userspace_data = -{ - .us_heap = &g_mmheap, -}; - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/* These 'addresses' of these values are setup by the linker script. */ - -extern uint8_t _stext[]; /* Start of .text */ -extern uint8_t _etext[]; /* End_1 of .text + .rodata */ -extern const uint8_t _eronly[]; /* End+1 of read only section (.text + .rodata) */ -extern uint8_t _sdata[]; /* Start of .data */ -extern uint8_t _edata[]; /* End+1 of .data */ -extern uint8_t _sbss[]; /* Start of .bss */ -extern uint8_t _ebss[]; /* End+1 of .bss */ - -const struct userspace_s userspace locate_data(".userspace") = -{ - /* General memory map */ - - .us_entrypoint = CONFIG_INIT_ENTRYPOINT, - .us_textstart = (uintptr_t)_stext, - .us_textend = (uintptr_t)_etext, - .us_datasource = (uintptr_t)_eronly, - .us_datastart = (uintptr_t)_sdata, - .us_dataend = (uintptr_t)_edata, - .us_bssstart = (uintptr_t)_sbss, - .us_bssend = (uintptr_t)_ebss, - - /* User data memory structure */ - - .us_data = &g_userspace_data, - - /* Task/thread startup routines */ - - .task_startup = nxtask_startup, - - /* Signal handler trampoline */ - - .signal_handler = up_signal_handler, - - /* User-space work queue support (declared in include/nuttx/wqueue.h) */ - -#ifdef CONFIG_LIBC_USRWORK - .work_usrstart = work_usrstart, -#endif -}; - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -#endif /* CONFIG_BUILD_PROTECTED && !__KERNEL__ */ diff --git a/boards/arm/stm32/mikroe-stm32f4/scripts/Make.defs b/boards/arm/stm32/mikroe-stm32f4/scripts/Make.defs deleted file mode 100644 index 36864251081d8..0000000000000 --- a/boards/arm/stm32/mikroe-stm32f4/scripts/Make.defs +++ /dev/null @@ -1,41 +0,0 @@ -############################################################################ -# boards/arm/stm32/mikroe-stm32f4/scripts/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/.config -include $(TOPDIR)/tools/Config.mk -include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs - -LDSCRIPT = ld.script -ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) - -ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 - -CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) -CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) -CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -AFLAGS := $(CFLAGS) -D__ASSEMBLY__ - -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections -LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32/mikroe-stm32f4/scripts/kernel-space.ld b/boards/arm/stm32/mikroe-stm32f4/scripts/kernel-space.ld deleted file mode 100644 index 1555c66cdded9..0000000000000 --- a/boards/arm/stm32/mikroe-stm32f4/scripts/kernel-space.ld +++ /dev/null @@ -1,100 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/mikroe-stm32f4/scripts/kernel-space.ld - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* NOTE: This depends on the memory.ld script having been included prior to - * this script. - */ - -OUTPUT_ARCH(arm) -EXTERN(_vectors) -ENTRY(_stext) -SECTIONS -{ - .text : { - _stext = ABSOLUTE(.); - *(.vectors) - *(.text .text.*) - *(.fixup) - *(.gnu.warning) - *(.rodata .rodata.*) - *(.gnu.linkonce.t.*) - *(.glue_7) - *(.glue_7t) - *(.got) - *(.gcc_except_table) - *(.gnu.linkonce.r.*) - _etext = ABSOLUTE(.); - } > kflash - - .init_section : { - _sinit = ABSOLUTE(.); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) - KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) - _einit = ABSOLUTE(.); - } > kflash - - .ARM.extab : { - *(.ARM.extab*) - } > kflash - - __exidx_start = ABSOLUTE(.); - .ARM.exidx : { - *(.ARM.exidx*) - } > kflash - - __exidx_end = ABSOLUTE(.); - - _eronly = ABSOLUTE(.); - - .data : { - _sdata = ABSOLUTE(.); - *(.data .data.*) - *(.gnu.linkonce.d.*) - CONSTRUCTORS - . = ALIGN(4); - _edata = ABSOLUTE(.); - } > ksram AT > kflash - - .bss : { - _sbss = ABSOLUTE(.); - *(.bss .bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - . = ALIGN(8); - _ebss = ABSOLUTE(.); - } > ksram - - /* Stabs debugging sections */ - - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_info 0 : { *(.debug_info) } - .debug_line 0 : { *(.debug_line) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_aranges 0 : { *(.debug_aranges) } -} diff --git a/boards/arm/stm32/mikroe-stm32f4/scripts/ld.script b/boards/arm/stm32/mikroe-stm32f4/scripts/ld.script deleted file mode 100644 index c576581edc4fd..0000000000000 --- a/boards/arm/stm32/mikroe-stm32f4/scripts/ld.script +++ /dev/null @@ -1,126 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/mikroe-stm32f4/scripts/ld.script - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* The STM32F407VG has 1024Kb of FLASH beginning at address 0x0800:0000 and - * 192Kb of SRAM. SRAM is split up into three blocks: - * - * 1) 112Kb of SRAM beginning at address 0x2000:0000 - * 2) 16Kb of SRAM beginning at address 0x2001:c000 - * 3) 64Kb of CCM SRAM beginning at address 0x1000:0000 - * - * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 - * where the code expects to begin execution by jumping to the entry point in - * the 0x0800:0000 address - * range. - */ - -MEMORY -{ - flash (rx) : ORIGIN = 0x08000000, LENGTH = 1024K - sram (rwx) : ORIGIN = 0x20000000, LENGTH = 112K -} - -OUTPUT_ARCH(arm) -EXTERN(_vectors) -ENTRY(_stext) -SECTIONS -{ - .text : { - _stext = ABSOLUTE(.); - *(.vectors) - *(.text .text.*) - *(.fixup) - *(.gnu.warning) - *(.rodata .rodata.*) - *(.gnu.linkonce.t.*) - *(.glue_7) - *(.glue_7t) - *(.got) - *(.gcc_except_table) - *(.gnu.linkonce.r.*) - _etext = ABSOLUTE(.); - } > flash - - .init_section : ALIGN(4) { - _sinit = ABSOLUTE(.); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) - KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) - _einit = ABSOLUTE(.); - } > flash - - .ARM.extab : ALIGN(4) { - *(.ARM.extab*) - } > flash - - .ARM.exidx : ALIGN(4) { - __exidx_start = ABSOLUTE(.); - *(.ARM.exidx*) - __exidx_end = ABSOLUTE(.); - } > flash - - .tdata : { - _stdata = ABSOLUTE(.); - *(.tdata .tdata.* .gnu.linkonce.td.*); - _etdata = ABSOLUTE(.); - } > flash - - .tbss : { - _stbss = ABSOLUTE(.); - *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); - _etbss = ABSOLUTE(.); - } > flash - - _eronly = ABSOLUTE(.); - - .data : ALIGN(4) { - _sdata = ABSOLUTE(.); - *(.data .data.*) - *(.gnu.linkonce.d.*) - CONSTRUCTORS - . = ALIGN(4); - _edata = ABSOLUTE(.); - } > sram AT > flash - - .bss : ALIGN(4) { - _sbss = ABSOLUTE(.); - *(.bss .bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - . = ALIGN(4); - _ebss = ABSOLUTE(.); - } > sram - - /* Stabs debugging sections. */ - - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_info 0 : { *(.debug_info) } - .debug_line 0 : { *(.debug_line) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_aranges 0 : { *(.debug_aranges) } -} diff --git a/boards/arm/stm32/mikroe-stm32f4/scripts/memory.ld b/boards/arm/stm32/mikroe-stm32f4/scripts/memory.ld deleted file mode 100644 index a8f5498242e0b..0000000000000 --- a/boards/arm/stm32/mikroe-stm32f4/scripts/memory.ld +++ /dev/null @@ -1,87 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/mikroe-stm32f4/scripts/memory.ld - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* The STM32F407VG has 1024Kb of FLASH beginning at address 0x0800:0000 and - * 192Kb of SRAM. SRAM is split up into three blocks: - * - * 1) 112KB of SRAM beginning at address 0x2000:0000 - * 2) 16KB of SRAM beginning at address 0x2001:c000 - * 3) 64KB of CCM SRAM beginning at address 0x1000:0000 - * - * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 - * where the code expects to begin execution by jumping to the entry point in - * the 0x0800:0000 address range. - * - * For MPU support, the kernel-mode NuttX section is assumed to be 128Kb of - * FLASH and 4Kb of SRAM. That is an excessive amount for the kernel which - * should fit into 64KB and, of course, can be optimized as needed (See - * also boards/stm32f4discovery/scripts/kernel-space.ld). Allowing the - * additional does permit addition debug instrumentation to be added to the - * kernel space without overflowing the partition. - * - * Alignment of the user space FLASH partition is also a critical factor: - * The user space FLASH partition will be spanned with a single region of - * size 2**n bytes. The alignment of the user-space region must be the same. - * As a consequence, as the user-space increases in size, the alignment - * requirement also increases. - * - * This alignment requirement means that the largest user space FLASH region - * you can have will be 512KB at it would have to be positioned at - * 0x08800000. If you change this address, don't forget to change the - * CONFIG_NUTTX_USERSPACE configuration setting to match and to modify - * the check in kernel/userspace.c. - * - * For the same reasons, the maximum size of the SRAM mapping is limited to - * 4KB. Both of these alignment limitations could be reduced by using - * multiple regions to map the FLASH/SDRAM range or perhaps with some - * clever use of subregions. - * - * A detailed memory map for the 112KB SRAM region is as follows: - * - * 0x20000 0000: Kernel .data region. Typical size: 0.1KB - * ------- ---- Kernel .bss region. Typical size: 1.8KB - * 0x20000 0800: Kernel IDLE thread stack (approximate). Size is - * determined by CONFIG_IDLETHREAD_STACKSIZE and - * adjustments for alignment. Typical is 1KB. - * ------- ---- Padded to 4KB - * 0x20000 1000: User .data region. Size is variable. - * ------- ---- User .bss region Size is variable. - * 0x20000 2000: Beginning of kernel heap. Size determined by - * CONFIG_MM_KERNEL_HEAPSIZE. - * ------- ---- Beginning of user heap. Can vary with other settings. - * 0x20001 c000: End+1 of CPU RAM - */ - -MEMORY -{ - /* 1024Kb FLASH */ - - kflash (rx) : ORIGIN = 0x08000000, LENGTH = 128K - uflash (rx) : ORIGIN = 0x08020000, LENGTH = 128K - xflash (rx) : ORIGIN = 0x08040000, LENGTH = 768K - - /* 112Kb of contiguous SRAM */ - - ksram (rwx) : ORIGIN = 0x20000000, LENGTH = 4K - usram (rwx) : ORIGIN = 0x20001000, LENGTH = 4K - xsram (rwx) : ORIGIN = 0x20002000, LENGTH = 104K -} diff --git a/boards/arm/stm32/mikroe-stm32f4/scripts/user-space.ld b/boards/arm/stm32/mikroe-stm32f4/scripts/user-space.ld deleted file mode 100644 index e7e09d43613b1..0000000000000 --- a/boards/arm/stm32/mikroe-stm32f4/scripts/user-space.ld +++ /dev/null @@ -1,101 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/mikroe-stm32f4/scripts/user-space.ld - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* NOTE: This depends on the memory.ld script having been included prior to - * this script. - */ - -OUTPUT_ARCH(arm) -SECTIONS -{ - .userspace : { - *(.userspace) - } > uflash - - .text : { - _stext = ABSOLUTE(.); - *(.text .text.*) - *(.fixup) - *(.gnu.warning) - *(.rodata .rodata.*) - *(.gnu.linkonce.t.*) - *(.glue_7) - *(.glue_7t) - *(.got) - *(.gcc_except_table) - *(.gnu.linkonce.r.*) - _etext = ABSOLUTE(.); - } > uflash - - .init_section : { - _sinit = ABSOLUTE(.); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) - KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) - _einit = ABSOLUTE(.); - } > uflash - - .ARM.extab : { - *(.ARM.extab*) - } > uflash - - __exidx_start = ABSOLUTE(.); - .ARM.exidx : { - *(.ARM.exidx*) - } > uflash - - __exidx_end = ABSOLUTE(.); - - _eronly = ABSOLUTE(.); - - .data : { - _sdata = ABSOLUTE(.); - *(.data .data.*) - *(.gnu.linkonce.d.*) - CONSTRUCTORS - . = ALIGN(4); - _edata = ABSOLUTE(.); - } > usram AT > uflash - - .bss : { - _sbss = ABSOLUTE(.); - *(.bss .bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - . = ALIGN(8); - _ebss = ABSOLUTE(.); - } > usram - - /* Stabs debugging sections */ - - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_info 0 : { *(.debug_info) } - .debug_line 0 : { *(.debug_line) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_aranges 0 : { *(.debug_aranges) } -} diff --git a/boards/arm/stm32/mikroe-stm32f4/src/CMakeLists.txt b/boards/arm/stm32/mikroe-stm32f4/src/CMakeLists.txt deleted file mode 100644 index ccadb52a73910..0000000000000 --- a/boards/arm/stm32/mikroe-stm32f4/src/CMakeLists.txt +++ /dev/null @@ -1,67 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/mikroe-stm32f4/src/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -set(SRCS stm32_boot.c stm32_spi.c) - -if(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) - list(APPEND SRCS stm32_clockconfig.c) -endif() - -if(CONFIG_STM32_OTGFS) - list(APPEND SRCS stm32_usb.c) -endif() - -if(CONFIG_PWM) - list(APPEND SRCS stm32_pwm.c) -endif() - -if(CONFIG_ARCH_CUSTOM_PMINIT) - list(APPEND SRCS stm32_pm.c) -endif() - -if(CONFIG_ARCH_IDLE_CUSTOM) - list(APPEND SRCS stm32_idle.c) -endif() - -if(CONFIG_STM32_FSMC) - list(APPEND SRCS stm32_extmem.c) -endif() - -if(CONFIG_INPUT) - list(APPEND SRCS stm32_touchscreen.c) -endif() - -if(CONFIG_LCD_MIO283QT2) - list(APPEND SRCS stm32_mio283qt2.c) -endif() - -if(CONFIG_LCD_MIO283QT9A) - list(APPEND SRCS stm32_mio283qt9a.c) -endif() - -if(CONFIG_AUDIO_VS1053) - list(APPEND SRCS stm32_vs1053.c) -endif() - -target_sources(board PRIVATE ${SRCS}) - -set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/ld.script") diff --git a/boards/arm/stm32/mikroe-stm32f4/src/Make.defs b/boards/arm/stm32/mikroe-stm32f4/src/Make.defs deleted file mode 100644 index 4d1e116adb868..0000000000000 --- a/boards/arm/stm32/mikroe-stm32f4/src/Make.defs +++ /dev/null @@ -1,73 +0,0 @@ -############################################################################ -# boards/arm/stm32/mikroe-stm32f4/src/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/Make.defs - -CSRCS = stm32_boot.c stm32_spi.c - -ifeq ($(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG),y) -CSRCS += stm32_clockconfig.c -endif - -ifeq ($(CONFIG_STM32_OTGFS),y) -CSRCS += stm32_usb.c -endif - -ifeq ($(CONFIG_PWM),y) -CSRCS += stm32_pwm.c -endif - -ifeq ($(CONFIG_ARCH_CUSTOM_PMINIT),y) -CSRCS += stm32_pm.c -endif - -ifeq ($(CONFIG_ARCH_IDLE_CUSTOM),y) -CSRCS += stm32_idle.c -endif - -ifeq ($(CONFIG_STM32_FSMC),y) -CSRCS += stm32_extmem.c -endif - -ifeq ($(CONFIG_INPUT),y) -CSRCS += stm32_touchscreen.c -endif - -ifeq ($(CONFIG_LCD_MIO283QT2),y) -CSRCS += stm32_mio283qt2.c -endif - -ifeq ($(CONFIG_LCD_MIO283QT9A),y) -CSRCS += stm32_mio283qt9a.c -endif - -ifeq ($(CONFIG_AUDIO_VS1053),y) -CSRCS += stm32_vs1053.c -endif - -ifeq ($(CONFIG_ETC_ROMFS),y) -CSRCS += etc_romfs.c -endif - -DEPPATH += --dep-path board -VPATH += :board -CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/mikroe-stm32f4/src/stm32_boot.c b/boards/arm/stm32/mikroe-stm32f4/src/stm32_boot.c deleted file mode 100644 index aa2a1c87b0965..0000000000000 --- a/boards/arm/stm32/mikroe-stm32f4/src/stm32_boot.c +++ /dev/null @@ -1,467 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/mikroe-stm32f4/src/stm32_boot.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include -#include -#include -#include - -#include -#include -#include - -#ifdef CONFIG_STM32_SPI3 -# include -#endif - -#ifdef CONFIG_MTD_M25P -# include -#endif - -#ifdef CONFIG_USBMONITOR -# include -#endif - -#ifdef CONFIG_MIKROE_FLASH_CONFIG_PART -#ifdef CONFIG_PLATFORM_CONFIGDATA -# include -#endif -#endif - -#ifdef CONFIG_AUDIO -# include -#endif - -#ifdef CONFIG_STM32_OTGFS -# include "stm32_usbhost.h" -#endif - -#include "stm32.h" -#include "arm_internal.h" -#include "mikroe-stm32f4.h" - -#ifdef CONFIG_SENSORS_QENCODER -#include "board_qencoder.h" -#endif - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -#define HAVE_USBDEV 1 -#define HAVE_USBHOST 1 -#define HAVE_USBMONITOR 1 -#define NSH_HAVEMMCSD 1 - -/* Can't support USB host or device features if USB OTG FS is not enabled */ - -#ifndef CONFIG_STM32_OTGFS -# undef HAVE_USBDEV -# undef HAVE_USBHOST -#endif - -/* Can't support USB device is USB device is not enabled */ - -#ifndef CONFIG_USBDEV -# undef HAVE_USBDEV -#endif - -/* Can't support USB host is USB host is not enabled */ - -#ifndef CONFIG_USBHOST -# undef HAVE_USBHOST -#endif - -/* Check if we should enable the USB monitor before starting NSH */ - -#ifndef CONFIG_USBMONITOR -# undef HAVE_USBMONITOR -#endif - -#ifndef HAVE_USBDEV -# undef CONFIG_USBDEV_TRACE -#endif - -#ifndef HAVE_USBHOST -# undef CONFIG_USBHOST_TRACE -#endif - -#if !defined(CONFIG_USBDEV_TRACE) && !defined(CONFIG_USBHOST_TRACE) -# undef HAVE_USBMONITOR -#endif - -/* Can't support MMC/SD features if mountpoints are disabled or if SDIO - * support is not enabled. - */ - -#if defined(CONFIG_DISABLE_MOUNTPOINT) || !defined(CONFIG_STM32_SPI3) -# undef NSH_HAVEMMCSD -#endif - -#ifndef CONFIG_NSH_MMCSDMINOR -# define CONFIG_NSH_MMCSDMINOR 0 -#endif - -# ifndef CONFIG_RAMMTD_BLOCKSIZE -# define CONFIG_RAMMTD_BLOCKSIZE 512 -# endif - -# ifndef CONFIG_RAMMTD_ERASESIZE -# define CONFIG_RAMMTD_ERASESIZE 4096 -# endif - -# ifndef CONFIG_TESTING_SMART_NEBLOCKS -# define CONFIG_TESTING_SMART_NEBLOCKS (22) -# endif - -#ifdef CONFIG_MIKROE_RAMMTD -# ifndef CONFIG_MIKROE_RAMMTD_MINOR -# define CONFIG_MIKROE_RAMMTD_MINOR 1 -# endif -# ifndef CONFIG_MIKROE_RAMMTD_SIZE -# define CONFIG_MIKROE_RAMMTD_SIZE 32 -# endif -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_boardinitialize - * - * Description: - * All STM32 architectures must provide the following entry point. - * This entry point is called early in the initialization -- after all - * memory has been configured and mapped but before any devices have been - * initialized. - * - ****************************************************************************/ - -void stm32_boardinitialize(void) -{ - /* First reset the VS1053 since it tends to produce noise out of power on - * reset - */ - -#ifdef CONFIG_AUDIO_VS1053 - stm32_configgpio(GPIO_VS1053_RST); -#endif - - /* Configure GPIOs for controlling the LCD */ - -#if defined(CONFIG_LCD_MIO283QT2) || defined(CONFIG_LCD_MIO283QT9A) - stm32_lcdinitialize(); -#endif - - /* Configure SPI chip selects if 1) SPI is not disabled, and 2) the weak - * function stm32_spidev_initialize() has been brought into the link. - */ - -#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || defined(CONFIG_STM32_SPI3) - if (stm32_spidev_initialize) - { - stm32_spidev_initialize(); - } -#endif - - /* Initialize USB if the 1) OTG FS controller is in the configuration and - * 2) disabled, and 3) the weak function stm32_usbinitialize() has been - * brought into the build. Presumably either CONFIG_USBDEV or - * CONFIG_USBHOST is also selected. - */ - -#ifdef CONFIG_STM32_OTGFS - if (stm32_usbinitialize) - { - stm32_usbinitialize(); - } -#endif -} - -/**************************************************************************** - * Name: board_late_initialize - * - * Description: - * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional - * initialization call will be performed in the boot-up sequence to a - * function called board_late_initialize(). board_late_initialize() will - * be called immediately after up_initialize() is called and just before - * the initial application is started. This additional initialization - * phase may be used, for example, to initialize board-specific device - * drivers. - * - ****************************************************************************/ - -#ifdef CONFIG_BOARD_LATE_INITIALIZE -void board_late_initialize(void) -{ -#ifdef CONFIG_STM32_SPI3 - struct spi_dev_s *spi; - struct mtd_dev_s *mtd; -#endif - int ret = OK; - - /* Configure SPI-based devices */ - -#ifdef CONFIG_STM32_SPI3 - /* Get the SPI port */ - - syslog(LOG_INFO, "Initializing SPI port 3\n"); - spi = stm32_spibus_initialize(3); - if (!spi) - { - syslog(LOG_ERR, "ERROR: Failed to initialize SPI port 3\n"); - return; - } - - syslog(LOG_INFO, "Successfully initialized SPI port 3\n"); - - /* Now bind the SPI interface to the M25P8 SPI FLASH driver */ - -#if defined(CONFIG_MTD) && defined(CONFIG_MIKROE_FLASH) - syslog(LOG_INFO, "Bind SPI to the SPI flash driver\n"); - - mtd = m25p_initialize(spi); - if (!mtd) - { - syslog(LOG_ERR, "ERROR: Failed to bind SPI port 3 to the SPI" - " FLASH driver\n"); - } - else - { - syslog(LOG_INFO, "Successfully bound SPI port 3 to the SPI" - " FLASH driver\n"); - -#ifdef CONFIG_MIKROE_FLASH_PART - { - int partno; - int partsize; - int partoffset; - const char *partstring = CONFIG_MIKROE_FLASH_PART_LIST; - const char *ptr; - struct mtd_dev_s *mtd_part; - char partname[16]; - - /* Now create a partition on the FLASH device */ - - partno = 0; - ptr = partstring; - partoffset = 0; - - while (*ptr != '\0') - { - /* Get the partition size */ - - partsize = atoi(ptr); - mtd_part = mtd_partition(mtd, partoffset, - (partsize >> 2) * 16); - partoffset += (partsize >> 2) * 16; - -#ifdef CONFIG_MIKROE_FLASH_CONFIG_PART - /* Test if this is the config partition */ - - if (CONFIG_MIKROE_FLASH_CONFIG_PART_NUMBER == partno) - { - /* Register the partition as the config device */ - - mtdconfig_register(mtd_part); - } - else -#endif - { - /* Now initialize a SMART Flash block device and bind it - * to the MTD device. - */ - - #if defined(CONFIG_MTD_SMART) && defined(CONFIG_FS_SMARTFS) - snprintf(partname, sizeof(partname), "p%d", partno); - smart_initialize(CONFIG_MIKROE_FLASH_MINOR, mtd_part, - partname); -#endif - } - - /* Update the pointer to point to the next size in the list */ - - while ((*ptr >= '0') && (*ptr <= '9')) - { - ptr++; - } - - if (*ptr == ',') - { - ptr++; - } - - /* Increment the part number */ - - partno++; - } - } -#else /* CONFIG_MIKROE_FLASH_PART */ - - /* Configure the device with no partition support */ - - smart_initialize(CONFIG_MIKROE_FLASH_MINOR, mtd, NULL); - -#endif /* CONFIG_MIKROE_FLASH_PART */ - } - - /* Create a RAM MTD device if configured */ - -#if defined(CONFIG_RAMMTD) && defined(CONFIG_MIKROE_RAMMTD) - { - uint8_t *start = - kmm_malloc(CONFIG_MIKROE_RAMMTD_SIZE * 1024); - mtd = rammtd_initialize(start, CONFIG_MIKROE_RAMMTD_SIZE * 1024); - mtd->ioctl(mtd, MTDIOC_BULKERASE, 0); - - /* Now initialize a SMART Flash block device and bind it to the - * MTD device - */ - -#if defined(CONFIG_MTD_SMART) && defined(CONFIG_FS_SMARTFS) - smart_initialize(CONFIG_MIKROE_RAMMTD_MINOR, mtd, NULL); -#endif - } - -#endif /* CONFIG_RAMMTD && CONFIG_MIKROE_RAMMTD */ - -#endif /* CONFIG_MTD */ -#endif /* CONFIG_STM32_SPI3 */ - - /* Create the SPI FLASH MTD instance */ - - /* The M25Pxx is not a good media to implement a file system.. - * its block sizes are too large - */ - - /* Mount the SDIO-based MMC/SD block driver */ - -#ifdef NSH_HAVEMMCSD - /* Bind the spi interface to the MMC/SD driver */ - - syslog(LOG_INFO, "Bind SDIO to the MMC/SD driver, minor=%d\n", - CONFIG_NSH_MMCSDMINOR); - - ret = mmcsd_spislotinitialize(CONFIG_NSH_MMCSDMINOR, - CONFIG_NSH_MMCSDSLOTNO, spi); - if (ret != OK) - { - syslog(LOG_ERR, "ERROR: Failed to bind SPI to the MMC/SD driver:" - " %d\n", ret); - } - else - { - syslog(LOG_INFO, "Successfully bound SPI to the MMC/SD driver\n"); - } -#endif - -#ifdef HAVE_USBHOST - /* Initialize USB host operation. stm32_usbhost_initialize() starts a - * thread will monitor for USB connection and disconnection events. - */ - - ret = stm32_usbhost_initialize(); - if (ret != OK) - { - syslog(LOG_ERR, "ERROR: Failed to initialize USB host: %d\n", ret); - return; - } -#endif - -#ifdef HAVE_USBMONITOR - /* Start the USB Monitor */ - - ret = usbmonitor_start(); - if (ret != OK) - { - syslog(LOG_ERR, "ERROR: Failed to start USB monitor: %d\n", ret); - } -#endif - -#ifdef CONFIG_INPUT - /* Initialize the touchscreen */ - - ret = stm32_tsc_setup(0); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_tsc_setup failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_PWM - /* Initialize PWM and register the PWM device. */ - - ret = stm32_pwm_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_pwm_setup() failed: %d\n", ret); - } -#endif - -#if defined(CONFIG_LCD_MIO283QT2) || defined(CONFIG_LCD_MIO283QT9A) - /* Configure the TFT LCD module */ - - syslog(LOG_INFO, "Initializing TFT LCD module\n"); - - ret = board_lcd_initialize(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: Failed to initialize TFT LCD module\n"); - } -#endif - -#ifdef CONFIG_SENSORS_QENCODER - /* Initialize and register the qencoder driver */ - - ret = board_qencoder_initialize(0, CONFIG_MIKROE_QETIMER); - if (ret != OK) - { - syslog(LOG_ERR, - "ERROR: Failed to register the qencoder: %d\n", - ret); - return; - } -#endif - -#ifdef CONFIG_AUDIO - /* Configure the Audio sub-system if enabled and bind it to SPI 3 */ - - up_vs1053initialize(spi); -#endif -} -#endif diff --git a/boards/arm/stm32/mikroe-stm32f4/src/stm32_extmem.c b/boards/arm/stm32/mikroe-stm32f4/src/stm32_extmem.c deleted file mode 100644 index bcc1ef406e2f4..0000000000000 --- a/boards/arm/stm32/mikroe-stm32f4/src/stm32_extmem.c +++ /dev/null @@ -1,141 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/mikroe-stm32f4/src/stm32_extmem.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32_gpio.h" -#include "stm32.h" -#include "mikroe-stm32f4.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#ifndef CONFIG_STM32_FSMC -# warning "FSMC is not enabled" -#endif - -#if STM32_NGPIO_PORTS < 6 -# error "Required GPIO ports not enabled" -#endif - -#define STM32_FSMC_NADDRCONFIGS 26 -#define STM32_FSMC_NDATACONFIGS 16 - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/* GPIO configurations common to most external memories */ - -static const uint32_t g_addressconfig[STM32_FSMC_NADDRCONFIGS] = -{ - GPIO_FSMC_A0, GPIO_FSMC_A1 , GPIO_FSMC_A2, - GPIO_FSMC_A3, GPIO_FSMC_A4 , GPIO_FSMC_A5, - GPIO_FSMC_A6, GPIO_FSMC_A7, GPIO_FSMC_A8, - GPIO_FSMC_A9, GPIO_FSMC_A10, GPIO_FSMC_A11, - GPIO_FSMC_A12, GPIO_FSMC_A13, GPIO_FSMC_A14, - GPIO_FSMC_A15, GPIO_FSMC_A16, GPIO_FSMC_A17, - GPIO_FSMC_A18, GPIO_FSMC_A19, GPIO_FSMC_A20, - GPIO_FSMC_A21, GPIO_FSMC_A22, GPIO_FSMC_A23, - GPIO_FSMC_A24, GPIO_FSMC_A25 -}; - -static const uint32_t g_dataconfig[STM32_FSMC_NDATACONFIGS] = -{ - GPIO_FSMC_D0, GPIO_FSMC_D1 , GPIO_FSMC_D2, - GPIO_FSMC_D3, GPIO_FSMC_D4 , GPIO_FSMC_D5, - GPIO_FSMC_D6, GPIO_FSMC_D7, GPIO_FSMC_D8, - GPIO_FSMC_D9, GPIO_FSMC_D10, GPIO_FSMC_D11, - GPIO_FSMC_D12, GPIO_FSMC_D13, GPIO_FSMC_D14, - GPIO_FSMC_D15 -}; - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_extmemgpios - * - * Description: - * Initialize GPIOs for external memory usage - * - ****************************************************************************/ - -void stm32_extmemgpios(const uint32_t *gpios, int ngpios) -{ - int i; - - /* Configure GPIOs */ - - for (i = 0; i < ngpios; i++) - { - stm32_configgpio(gpios[i]); - } -} - -/**************************************************************************** - * Name: stm32_extmemaddr - * - * Description: - * Initialize address line GPIOs for external memory access - * - ****************************************************************************/ - -void stm32_extmemaddr(int naddrs) -{ - stm32_extmemgpios(g_addressconfig, naddrs); -} - -/**************************************************************************** - * Name: stm32_extmemdata - * - * Description: - * Initialize data line GPIOs for external memory access - * - ****************************************************************************/ - -void stm32_extmemdata(int ndata) -{ - stm32_extmemgpios(g_dataconfig, ndata); -} diff --git a/boards/arm/stm32/mikroe-stm32f4/src/stm32_idle.c b/boards/arm/stm32/mikroe-stm32f4/src/stm32_idle.c deleted file mode 100644 index f03d247d4adbf..0000000000000 --- a/boards/arm/stm32/mikroe-stm32f4/src/stm32_idle.c +++ /dev/null @@ -1,263 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/mikroe-stm32f4/src/stm32_idle.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include - -#include - -#include -#include -#include -#include - -#include - -#include "arm_internal.h" -#include "stm32_pm.h" -#include "stm32_rcc.h" -#include "stm32_exti.h" - -#include "mikroe-stm32f4.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -/* Does the board support an IDLE LED to indicate that the board is in the - * IDLE state? - */ - -#if defined(CONFIG_ARCH_LEDS) && defined(LED_IDLE) -# define BEGIN_IDLE() board_autoled_on(LED_IDLE) -# define END_IDLE() board_autoled_off(LED_IDLE) -#else -# define BEGIN_IDLE() -# define END_IDLE() -#endif - -/* Values for the RTC Alarm to wake up from the PM_STANDBY mode */ - -#ifndef CONFIG_PM_ALARM_SEC -# define CONFIG_PM_ALARM_SEC 3 -#endif - -#ifndef CONFIG_PM_ALARM_NSEC -# define CONFIG_PM_ALARM_NSEC 0 -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -#if defined(CONFIG_PM) && defined(CONFIG_RTC_ALARM) -static void up_alarmcb(void); -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: up_idlepm - * - * Description: - * Perform IDLE state power management. - * - ****************************************************************************/ - -#ifdef CONFIG_PM -static void up_idlepm(void) -{ -#ifdef CONFIG_RTC_ALARM - struct timespec alarmtime; -#endif - static enum pm_state_e oldstate = PM_NORMAL; - enum pm_state_e newstate; - irqstate_t flags; - int ret; - - /* Decide, which power saving level can be obtained */ - - newstate = pm_checkstate(PM_IDLE_DOMAIN); - - /* Check for state changes */ - - if (newstate != oldstate) - { - _info("newstate= %d oldstate=%d\n", newstate, oldstate); - - flags = enter_critical_section(); - - /* Force the global state change */ - - ret = pm_changestate(PM_IDLE_DOMAIN, newstate); - if (ret < 0) - { - /* The new state change failed, revert to the preceding state */ - - pm_changestate(PM_IDLE_DOMAIN, oldstate); - - /* No state change... */ - - goto errout; - } - - /* Then perform board-specific, state-dependent logic here */ - - switch (newstate) - { - case PM_NORMAL: - { - } - break; - - case PM_IDLE: - { - } - break; - - case PM_STANDBY: - { -#ifdef CONFIG_RTC_ALARM - /* Disable RTC Alarm interrupt */ - -#warning "missing logic" - - /* Configure the RTC alarm to Auto Wake the system */ - -#warning "missing logic" - - /* The tv_nsec value must not exceed 1,000,000,000. That - * would be an invalid time. - */ - -#warning "missing logic" - - /* Set the alarm */ - -#warning "missing logic" -#endif - /* Call the STM32 stop mode */ - - stm32_pmstop(true); - - /* We have been re-awakened by some even: A button press? - * An alarm? Cancel any pending alarm and resume the normal - * operation. - */ - -#ifdef CONFIG_RTC_ALARM -#warning "missing logic" -#endif - /* Resume normal operation */ - - pm_changestate(PM_IDLE_DOMAIN, PM_NORMAL); - newstate = PM_NORMAL; - } - break; - - case PM_SLEEP: - { - /* We should not return from standby mode. The only way out - * of standby is via the reset path. - */ - - stm32_pmstandby(); - } - break; - - default: - break; - } - - /* Save the new state */ - - oldstate = newstate; - -errout: - leave_critical_section(flags); - } -} -#else -# define up_idlepm() -#endif - -/**************************************************************************** - * Name: up_alarmcb - * - * Description: - * RTC alarm service routine - * - ****************************************************************************/ - -#if defined(CONFIG_PM) && defined(CONFIG_RTC_ALARM) -static void up_alarmcb(void) -{ - /* This alarm occurs because there wasn't any EXTI interrupt during the - * PM_STANDBY period. So just go to sleep. - */ - - pm_changestate(PM_IDLE_DOMAIN, PM_SLEEP); -} -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: up_idle - * - * Description: - * up_idle() is the logic that will be executed when their is no other - * ready-to-run task. This is processor idle time and will continue until - * some interrupt occurs to cause a context switch from the idle task. - * - * Processing in this state may be processor-specific. e.g., this is where - * power management operations might be performed. - * - ****************************************************************************/ - -void up_idle(void) -{ -#if defined(CONFIG_SUPPRESS_INTERRUPTS) || defined(CONFIG_SUPPRESS_TIMER_INTS) - /* If the system is idle and there are no timer interrupts, then process - * "fake" timer interrupts. Hopefully, something will wake up. - */ - - nxsched_process_timer(); -#else - - /* Perform IDLE mode power management */ - - BEGIN_IDLE(); - up_idlepm(); - END_IDLE(); -#endif -} diff --git a/boards/arm/stm32/mikroe-stm32f4/src/stm32_pm.c b/boards/arm/stm32/mikroe-stm32f4/src/stm32_pm.c deleted file mode 100644 index d7ce01fddfd5b..0000000000000 --- a/boards/arm/stm32/mikroe-stm32f4/src/stm32_pm.c +++ /dev/null @@ -1,75 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/mikroe-stm32f4/src/stm32_pm.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include - -#include "arm_internal.h" -#include "stm32_pm.h" -#include "mikroe-stm32f4.h" - -#ifdef CONFIG_PM - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: arm_pminitialize - * - * Description: - * This function is called by MCU-specific logic at power-on reset in - * order to provide one-time initialization the power management subsystem. - * This function must be called *very* early in the initialization sequence - * *before* any other device drivers are initialized (since they may - * attempt to register with the power management subsystem). - * - * Input Parameters: - * None. - * - * Returned Value: - * None. - * - ****************************************************************************/ - -void arm_pminitialize(void) -{ - /* Initialize the NuttX power management subsystem proper */ - - pm_initialize(); - -#if defined(CONFIG_ARCH_IDLE_CUSTOM) && defined(CONFIG_PM_BUTTONS) - /* Initialize the buttons to wake up the system from low power modes */ - - up_pmbuttons(); -#endif - - /* Initialize the LED PM */ - - up_ledpminitialize(); -} - -#endif /* CONFIG_PM */ diff --git a/boards/arm/stm32/mikroe-stm32f4/src/stm32_pwm.c b/boards/arm/stm32/mikroe-stm32f4/src/stm32_pwm.c deleted file mode 100644 index 28cb28a66536f..0000000000000 --- a/boards/arm/stm32/mikroe-stm32f4/src/stm32_pwm.c +++ /dev/null @@ -1,127 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/mikroe-stm32f4/src/stm32_pwm.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include - -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32_pwm.h" -#include "mikroe-stm32f4.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -/* PWM - * - * The mikroe_stm32f4 has no real on-board PWM devices, but the board can be - * configured to output a pulse train using TIM4 CH2. - * This pin is used by FSMC is connected to CN5 just for this purpose: - * - * PD13 FSMC_A18 / MC_TIM4_CH2OUT pin 33 (EnB) - * - * FSMC must be disabled in this case! - */ - -#define HAVE_PWM 1 - -#ifndef CONFIG_PWM -# undef HAVE_PWM -#endif - -#ifndef CONFIG_STM32_TIM4 -# undef HAVE_PWM -#endif - -#ifndef CONFIG_STM32_TIM4_PWM -# undef HAVE_PWM -#endif - -#if CONFIG_STM32_TIM4_CHANNEL != STM32F4DISCOVERY_PWMCHANNEL -# undef HAVE_PWM -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_pwm_setup - * - * Description: - * Initialize PWM and register the PWM device. - * - ****************************************************************************/ - -int stm32_pwm_setup(void) -{ -#ifdef HAVE_PWM - static bool initialized = false; - struct pwm_lowerhalf_s *pwm; - int ret; - - /* Have we already initialized? */ - - if (!initialized) - { - /* Call stm32_pwminitialize() to get an instance of the PWM interface */ - - pwm = stm32_pwminitialize(STM32F4DISCOVERY_PWMTIMER); - if (!pwm) - { - _err("ERROR: Failed to get the STM32 PWM lower half\n"); - return -ENODEV; - } - - /* Register the PWM driver at "/dev/pwm0" */ - - ret = pwm_register("/dev/pwm0", pwm); - if (ret < 0) - { - aerr("ERROR: pwm_register failed: %d\n", ret); - return ret; - } - - /* Now we are initialized */ - - initialized = true; - } - - return OK; -#else - return -ENODEV; -#endif -} diff --git a/boards/arm/stm32/mikroe-stm32f4/src/stm32_spi.c b/boards/arm/stm32/mikroe-stm32f4/src/stm32_spi.c deleted file mode 100644 index 2877044cc8a91..0000000000000 --- a/boards/arm/stm32/mikroe-stm32f4/src/stm32_spi.c +++ /dev/null @@ -1,246 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/mikroe-stm32f4/src/stm32_spi.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include - -#include -#include - -#include "arm_internal.h" -#include "chip.h" -#include "stm32.h" -#include "mikroe-stm32f4.h" - -#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || defined(CONFIG_STM32_SPI3) - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_spidev_initialize - * - * Description: - * Called to configure SPI chip select GPIO pins for the mikroe_stm32f4 - * board. - * - ****************************************************************************/ - -void weak_function stm32_spidev_initialize(void) -{ -#ifdef CONFIG_STM32_SPI3 - -#ifdef CONFIG_MTD_M25P - stm32_configgpio(GPIO_CS_FLASH); /* FLASH chip select */ -#endif - -#if defined(CONFIG_MMCSD) - stm32_configgpio(GPIO_CS_MMCSD); /* MMC/SD chip select */ - stm32_configgpio(GPIO_SD_CD); /* MMC/SD card detect */ -#endif - -#ifdef CONFIG_AUDIO_VS1053 - stm32_configgpio(GPIO_CS_MP3_DATA); /* MP3 codec chip select for DATA */ - stm32_configgpio(GPIO_CS_MP3_CMD); /* MP3 codec chip select for CMD */ -#endif - - /* Configure the EXP I/O cs for SPI3 */ - - stm32_configgpio(GPIO_CS_EXP_SPI3); /* Expander chip select */ - -#endif -} - -/**************************************************************************** - * Name: stm32_spi1/2/3select and stm32_spi1/2/3status - * - * Description: - * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status - * must be provided by board-specific logic. They are implementations of - * the select and status methods of the SPI interface defined by struct - * spi_ops_s (see include/nuttx/spi/spi.h). All other methods (including - * stm32_spibus_initialize()) are provided by common STM32 logic. - * To use this common SPI logic on your board: - * - * 1. Provide logic in stm32_boardinitialize() to configure SPI chip - * select pins. - * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() functions - * in your board-specific logic. These functions will perform chip - * selection and status operations using GPIOs in the way your board is - * configured. - * 3. Add a calls to stm32_spibus_initialize() in your low level - * application initialization logic - * 4. The handle returned by stm32_spibus_initialize() may then be used to - * bind the SPI driver to higher level logic (e.g., calling - * mmcsd_spislotinitialize(), for example, will bind the SPI driver to - * the SPI MMC/SD driver). - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_SPI3 -void stm32_spi3select(struct spi_dev_s *dev, - uint32_t devid, bool selected) -{ - spiinfo("devid: %d CS: %s\n", - (int)devid, selected ? "assert" : "de-assert"); - -#if defined(CONFIG_AUDIO_VS1053) - if (devid == SPIDEV_AUDIO_DATA(0)) - { - stm32_gpiowrite(GPIO_CS_MP3_DATA, !selected); - } - else if (devid == SPIDEV_AUDIO_CTRL(0)) - { - stm32_gpiowrite(GPIO_CS_MP3_CMD, !selected); - } - else -#endif - -#if defined(CONFIG_MMCSD) - if (devid == SPIDEV_MMCSD(0)) - { - stm32_gpiowrite(GPIO_CS_MMCSD, !selected); - } - else -#endif - -#if defined(CONFIG_MTD_M25P) - if (devid == SPIDEV_FLASH(0)) - { - stm32_gpiowrite(GPIO_CS_FLASH, !selected); - } - else -#endif - - /* Must be the expansion header device */ - - if (devid == SPIDEV_EXPANDER(0)) - { - stm32_gpiowrite(GPIO_CS_EXP_SPI3, !selected); - } -} - -uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid) -{ - uint8_t ret = 0; - -#if defined(CONFIG_MMCSD) - if (devid == SPIDEV_MMCSD(0)) - { - /* A low value indicates the card is present */ - - if (!stm32_gpioread(GPIO_SD_CD)) - { - ret = SPI_STATUS_PRESENT; - } - } -#endif - - return ret; -} -#endif - -#ifdef CONFIG_STM32_SPI2 -void stm32_spi2select(struct spi_dev_s *dev, - uint32_t devid, bool selected) -{ - spiinfo("devid: %d CS: %s\n", - (int)devid, selected ? "assert" : "de-assert"); -} - -uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) -{ - return 0; -} -#endif - -#ifdef CONFIG_STM32_SPI1 -void stm32_spi1select(struct spi_dev_s *dev, - uint32_t devid, bool selected) -{ - spiinfo("devid: %d CS: %s\n", - (int)devid, selected ? "assert" : "de-assert"); -} - -uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) -{ - return 0; -} -#endif - -/**************************************************************************** - * Name: stm32_spi1cmddata - * - * Description: - * Set or clear the SH1101A A0 or SD1306 D/C n bit to select data (true) - * or command (false). This function must be provided by platform-specific - * logic. This is an implementation of the cmddata method of the SPI - * interface defined by struct spi_ops_s (see include/nuttx/spi/spi.h). - * - * Input Parameters: - * - * spi - SPI device that controls the bus the device that requires the CMD/ - * DATA selection. - * devid - If there are multiple devices on the bus, this selects which one - * to select cmd or data. NOTE: This design restricts, for example, - * one one SPI display per SPI bus. - * cmd - true: select command; false: select data - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef CONFIG_SPI_CMDDATA -#ifdef CONFIG_STM32_SPI1 -int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) -{ - return -ENODEV; -} -#endif - -#ifdef CONFIG_STM32_SPI2 -int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) -{ - return OK; -} -#endif - -#ifdef CONFIG_STM32_SPI3 -int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) -{ - return OK; -} -#endif -#endif /* CONFIG_SPI_CMDDATA */ - -#endif /* CONFIG_STM32_SPI1 || CONFIG_STM32_SPI2 */ diff --git a/boards/arm/stm32/mikroe-stm32f4/src/stm32_touchscreen.c b/boards/arm/stm32/mikroe-stm32f4/src/stm32_touchscreen.c deleted file mode 100644 index d95270676d7f8..0000000000000 --- a/boards/arm/stm32/mikroe-stm32f4/src/stm32_touchscreen.c +++ /dev/null @@ -1,1547 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/mikroe-stm32f4/src/stm32_touchscreen.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include "arm_internal.h" -#include "stm32_adc.h" -#include "stm32_gpio.h" -#include "mikroe-stm32f4.h" - -#ifdef CONFIG_INPUT - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -/* Reference counting is partially implemented, but not needed in the current - * design. - */ - -#define CONFIG_TOUCHSCREEN_REFCNT -/* Should we try again on bad samples? */ - -#undef CONFIG_TOUCHSCREEN_RESAMPLE - -/* TP uses ADC Channel #2 in a dedicated mode. Ensure ADC2 not selected for - * general use via the menuconfig - */ - -#ifndef CONFIG_STM32_ADC2 -# error Touchpanel Input (CONFIG_INPUT=y) requires enablinga ADC2 (CONFIG_STM32_ADC2=y) -#endif - -/* Work queue support is required */ - -#ifndef CONFIG_SCHED_WORKQUEUE -# warning Work queue support is required (CONFIG_SCHED_WORKQUEUE=y) -#endif - -/* CONFIG_TOUCHSCREEN_THRESHX and CONFIG_TOUCHSCREEN_THRESHY - * Touchscreen data comes in a a very high rate. New touch positions - * will only be reported when the X or Y data changes by these thresholds. - * This trades reduces data rate for some loss in dragging accuracy. The - * touchscreen is configure for 12-bit values so the raw ranges are 0-4096. - * So for example, if your display is 320x240, then THRESHX=3 and THRESHY=4 - * would correspond to one pixel. Default: 4 - */ - -#ifndef CONFIG_TOUCHSCREEN_THRESHX -# define CONFIG_TOUCHSCREEN_THRESHX 12 -#endif - -#ifndef CONFIG_TOUCHSCREEN_THRESHY -# define CONFIG_TOUCHSCREEN_THRESHY 12 -#endif - -#ifndef CONFIG_TOUCHSCREEN_AVG_SAMPLES -# define CONFIG_TOUCHSCREEN_AVG_SAMPLES 2 -#endif - -#ifndef CONFIG_TOUCHSCREEN_NPOLLWAITERS -# define CONFIG_TOUCHSCREEN_NPOLLWAITERS 2 -#endif - -/* Driver support ***********************************************************/ - -/* This format is used to construct the /dev/input[n] device driver path. It - * is defined here so that it will be used consistently in all places. - */ - -#define DEV_FORMAT "/dev/input%d" -#define DEV_NAMELEN 16 - -/* Mikroe-STM32M4 Touchscreen Hardware Definitions ************************** - * PIN CONFIGURATIONS SIGNAL NAME ON-BOARD CONNECTIONS - * --- ---------------------------------- -------------------- -------------- - * 35 PB0 LCD-YD YD Analog input - * 36 PB1 LCD-XL XL Analog input - * 95 PB8 DRIVEA Drives XR, XL and YU - * 96 PB9 DRIVEB Drives YD - */ - -#define LCD_YD_PIN (0) -#define LCD_XL_PIN (1) -#define LCD_YD_CHANNEL (8) -#define LCD_XL_CHANNEL (9) -#define LCD_DRIVEA_PIN (8) -#define LCD_DRIVEB_PIN (9) - -#define LCD_DRIVEA_BIT (1 << LCD_DRIVEA_PIN) -#define LCD_DRIVEB_BIT (1 << LCD_DRIVEB_PIN) -#define LCD_SAMPX_BITS (LCD_DRIVEA_BIT | (LCD_DRIVEB_BIT << 16)) -#define LCD_SAMPY_BITS (LCD_DRIVEB_BIT | (LCD_DRIVEA_BIT << 16)) -#define LCD_TP_PORT_SETRESET STM32_GPIOB_BSRR - -#define TC_ADC_BASE STM32_ADC2_BASE /* ADC Channel base for TP */ -#define ADC_CR1_ALLINTS (ADC_CR1_AWDIE | ADC_CR1_EOCIE | ADC_CR1_JEOCIE) - -/* Conversions are performed as 10-bit samples represented as 16-bit */ - -#define MAX_ADC (4096) - -/* A measured value has to be within this range to be considered */ - -#define UPPER_THRESHOLD (MAX_ADC-1) -#define LOWER_THRESHOLD (362) - -/* Delays *******************************************************************/ - -/* All values will be increased by one system timer tick (probably 10MS). */ - -#define TC_PENUP_POLL_TICKS MSEC2TICK(70) /* IDLE polling rate: 70 MSec */ -#define TC_PENDOWN_POLL_TICKS MSEC2TICK(40) /* Active polling rate: 40 MSec */ -#define TC_DEBOUNCE_TICKS MSEC2TICK(16) /* Delay before re-sampling: 16 MSec */ -#define TC_SAMPLE_TICKS MSEC2TICK(4) /* Delay for A/D sampling: 4 MSec */ -#define TC_SETTLE_TICKS MSEC2TICK(10) /* Delay for A/D settling: 10 MSec */ -#define TC_RESAMPLE_TICKS TC_SAMPLE_TICKS - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/* This enumeration describes the state of touchscreen state machine */ - -enum tc_state_e -{ - TC_READY = 0, /* Ready to begin next sample */ - TC_READY_SETTLE, /* Allowing time for Y DRIVE to settle */ - TC_YPENDOWN, /* Allowing time for the Y pen down sampling */ - TC_DEBOUNCE, /* Allowing a debounce time for the first sample */ - TC_RESAMPLE, /* Restart sampling on a bad measurement */ - TC_YSAMPLE, /* Allowing time for the Y sampling */ - TC_XSETTLE, /* Allowing time for the X to settle after changing DRIVE */ - TC_XSAMPLE, /* Allowing time for the X sampling */ - TC_XRESAMPLE, /* Allow time to resample X */ - TC_PENDOWN, /* Conversion is complete -- pen down */ - TC_PENUP /* Conversion is complete -- pen up */ -}; - -/* This describes the state of one contact */ - -enum tc_contact_e -{ - CONTACT_NONE = 0, /* No contact */ - CONTACT_DOWN, /* First contact */ - CONTACT_MOVE, /* Same contact, possibly different position */ - CONTACT_UP, /* Contact lost */ -}; - -/* This structure describes the results of one touchscreen sample */ - -struct tc_sample_s -{ - uint8_t id; /* Sampled touch point ID */ - uint8_t contact; /* Contact state (see enum tc_contact_e) */ - bool valid; /* True: x,y contain valid, sampled data */ - uint16_t x; /* Thresholded X position */ - uint16_t y; /* Thresholded Y position */ -}; - -/* This structure describes the state of one touchscreen driver instance */ - -struct tc_dev_s -{ -#ifdef CONFIG_TOUCHSCREEN_REFCNT - uint8_t crefs; /* Number of times the device has been opened */ -#endif - uint8_t state; /* See enum tc_state_e */ - uint8_t nwaiters; /* Number of threads waiting for touchscreen data */ - uint8_t id; /* Current touch point ID */ - volatile bool penchange; /* An unreported event is buffered */ - uint16_t value; /* Partial sample value (Y+ or X-) */ - uint16_t newy; /* New, un-thresholded Y value */ - uint8_t sampcount; /* Count of samples for average so far */ - uint8_t resamplecount; /* Countdown to PENUP */ - mutex_t devlock; /* Manages exclusive access to this structure */ - sem_t waitsem; /* Used to wait for the availability of data */ - struct tc_sample_s sample; /* Last sampled touch point data */ - struct work_s work; /* Supports the state machine delayed processing */ - - /* The following is a list if poll structures of threads waiting for - * driver events. The 'struct pollfd' reference for each open is also - * retained in the f_priv field of the 'struct file'. - */ - - struct pollfd *fds[CONFIG_TOUCHSCREEN_NPOLLWAITERS]; -}; - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -static void tc_adc_init(void); -static void tc_adc_start_sample(int pin); -static uint16_t tc_adc_read_sample(void); -static void tc_y_sample(void); -static void tc_x_sample(void); -static inline bool tc_valid_sample(uint16_t sample); - -static void tc_notify(struct tc_dev_s *priv); -static int tc_sample(struct tc_dev_s *priv, - struct tc_sample_s *sample); -static int tc_waitsample(struct tc_dev_s *priv, - struct tc_sample_s *sample); -static void tc_worker(void *arg); - -/* Character driver methods */ - -static int tc_open(struct file *filep); -static int tc_close(struct file *filep); -static ssize_t tc_read(struct file *filep, char *buffer, size_t len); -static int tc_ioctl(struct file *filep, int cmd, unsigned long arg); -static int tc_poll(struct file *filep, struct pollfd *fds, bool setup); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* This the vtable that supports the character driver interface */ - -static const struct file_operations g_tc_fops = -{ - tc_open, /* open */ - tc_close, /* close */ - tc_read, /* read */ - NULL, /* write */ - NULL, /* seek */ - tc_ioctl, /* ioctl */ - NULL, /* mmap */ - NULL, /* truncate */ - tc_poll /* poll */ -}; - -/* If only a single touchscreen device is supported, then the driver state - * structure may as well be pre-allocated. - */ - -#ifndef CONFIG_TOUCHSCREEN_MULTIPLE -static struct tc_dev_s g_touchscreen; -static bool g_touchinitdone = false; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: tc_adc_getreg - * - * Description: - * Read the value of an TC ADC channel (#2) register. - * - * Input Parameters: - * offset - The offset to the register to read - * value - * - * Returned Value: - * - ****************************************************************************/ - -static inline uint32_t tc_adc_getreg(int offset) -{ - return getreg32(TC_ADC_BASE + offset); -} - -/**************************************************************************** - * Name: tc_adc_putreg - * - * Description: - * Set the value of an ADC register. - * - * Input Parameters: - * offset - The offset to the register to read - * - * Returned Value: - * - ****************************************************************************/ - -static inline void tc_adc_putreg(int offset, uint32_t value) -{ - putreg32(value, TC_ADC_BASE + offset); -} - -/**************************************************************************** - * Name: tc_adc_init - * - * Description: - * Initialize ADC Channel #2 for use with the touch panel. The touch panel - * uses Channels 8 and 9 (PB0 and PB1) to read the X and Y axis touch - * positions. - * - ****************************************************************************/ - -static void tc_adc_init(void) -{ - irqstate_t flags; - uint32_t regval; - - /* Do an rcc reset to reset the ADC peripheral */ - - /* Disable interrupts. This is necessary because the APB2RTSR register - * is used by several different drivers. - */ - - flags = enter_critical_section(); - - /* Enable ADC reset state */ - - regval = getreg32(STM32_RCC_APB2RSTR); - regval |= RCC_APB2RSTR_ADCRST; - putreg32(regval, STM32_RCC_APB2RSTR); - - /* Release ADC from reset state */ - - regval &= ~RCC_APB2RSTR_ADCRST; - putreg32(regval, STM32_RCC_APB2RSTR); - - /* Initialize the watchdog high threshold register */ - - tc_adc_putreg(STM32_ADC_HTR_OFFSET, 0x00000fff); - - /* Initialize the watchdog low threshold register */ - - tc_adc_putreg(STM32_ADC_LTR_OFFSET, 0x00000000); - - /* Initialize the same sample time for each ADC 55.5 cycles - * - * During sample cycles channel selection bits must remain unchanged. - * - * 000: 1.5 cycles - * 001: 7.5 cycles - * 010: 13.5 cycles - * 011: 28.5 cycles - * 100: 41.5 cycles - * 101: 55.5 cycles - * 110: 71.5 cycles - * 111: 239.5 cycles - */ - - tc_adc_putreg(STM32_ADC_SMPR1_OFFSET, 0x00b6db6d); - tc_adc_putreg(STM32_ADC_SMPR2_OFFSET, 0x00b6db6d); - - /* ADC CR1 Configuration */ - - regval = tc_adc_getreg(STM32_ADC_CR1_OFFSET); - - /* Initialize the Analog watchdog enable */ - - regval &= ~ADC_CR1_AWDEN; - regval |= (LCD_YD_CHANNEL << ADC_CR1_AWDCH_SHIFT); - - /* Enable interrupt flags */ - - /* regval |= ADC_CR1_ALLINTS; */ - - /* Disable Overrun interrupt */ - - regval &= ~ADC_CR1_OVRIE; - - /* Set the resolution of the conversion. We only need 10 bits. */ - - regval |= ADC_CR1_RES_12BIT; - - tc_adc_putreg(STM32_ADC_CR1_OFFSET, regval); - - /* ADC CR2 Configuration */ - - regval = tc_adc_getreg(STM32_ADC_CR2_OFFSET); - - /* Clear CONT, continuous mode disable. We will perform single - * sampling on one channel at a time. - */ - - regval &= ~ADC_CR2_CONT; - - /* Set ALIGN (Right = 0) */ - - regval &= ~ADC_CR2_ALIGN; - - /* External trigger disable. We will do SW triggering */ - - regval &= ~ADC_CR2_EXTEN_MASK; - - tc_adc_putreg(STM32_ADC_CR2_OFFSET, regval); - - /* Configuration of the channel conversion - start with Y sampling */ - - regval = tc_adc_getreg(STM32_ADC_SQR3_OFFSET) & ADC_SQR3_RESERVED; - regval |= LCD_YD_CHANNEL; - tc_adc_putreg(STM32_ADC_SQR3_OFFSET, regval); - - /* Set the number of conversions = 1 */ - - regval = tc_adc_getreg(STM32_ADC_SQR1_OFFSET) & ADC_SQR1_RESERVED; - regval |= 0 << ADC_SQR1_L_SHIFT; - tc_adc_putreg(STM32_ADC_SQR1_OFFSET, regval); - - /* ADC CCR configuration */ - - regval = getreg32(STM32_ADC_CCR); - regval &= ~(ADC_CCR_MULTI_MASK | ADC_CCR_DELAY_MASK | ADC_CCR_DDS | - ADC_CCR_DMA_MASK | ADC_CCR_ADCPRE_MASK | ADC_CCR_VBATEN | - ADC_CCR_TSVREFE); - regval |= (ADC_CCR_MULTI_NONE | ADC_CCR_DMA_DISABLED | - ADC_CCR_ADCPRE_DIV2); - putreg32(regval, STM32_ADC_CCR); - - /* Set ADON to wake up the ADC from Power Down state. */ - - regval = tc_adc_getreg(STM32_ADC_CR2_OFFSET); - regval |= ADC_CR2_ADON; - tc_adc_putreg(STM32_ADC_CR2_OFFSET, regval); - - /* Restore the IRQ state */ - - leave_critical_section(flags); -} - -/**************************************************************************** - * Name: tc_adc_start_sample - * - * Description: - * Perform A/D sampling. Time must be allowed between the start of - * sampling and conversion (approx. 100Ms). - * - ****************************************************************************/ - -static void tc_adc_start_sample(int channel) -{ - uint32_t regval; - - /* Configure the specified channel for ADC conversion. */ - - regval = tc_adc_getreg(STM32_ADC_SQR3_OFFSET) & ADC_SQR3_RESERVED; - regval |= channel; - tc_adc_putreg(STM32_ADC_SQR3_OFFSET, regval); - - /* Configure the Watchdog for this channel */ - - regval = tc_adc_getreg(STM32_ADC_CR1_OFFSET) & ADC_CR1_AWDCH_MASK; - regval |= (channel << ADC_CR1_AWDCH_SHIFT); - tc_adc_putreg(STM32_ADC_CR1_OFFSET, regval); - - /* Start the conversion */ - - regval = tc_adc_getreg(STM32_ADC_CR2_OFFSET); - regval |= ADC_CR2_SWSTART; - tc_adc_putreg(STM32_ADC_CR2_OFFSET, regval); -} - -/**************************************************************************** - * Name: tc_adc_read_sample - * - * Description: - * Begin A/D conversion. Time must be allowed between the start of - * sampling and conversion (approx. 100Ms). - * - * Assumptions: - * 1) All output pins configured as outputs: - * 2) Appropriate pins are driven high and low - * - ****************************************************************************/ - -static uint16_t tc_adc_read_sample(void) -{ - uint16_t retval; - uint32_t adcsr; - uint16_t count = 0; - - /* Validate the conversion is complete */ - - adcsr = tc_adc_getreg(STM32_ADC_SR_OFFSET); - while ((adcsr & ADC_SR_EOC) == 0) - { - adcsr = tc_adc_getreg(STM32_ADC_SR_OFFSET); - count++; - } - - /* Read the sample */ - - retval = tc_adc_getreg(STM32_ADC_DR_OFFSET); - retval &= ADC_DR_RDATA_MASK; - - if (count > 0) - { - iinfo("Count = %d\n", count); - } - - return retval; -} - -/**************************************************************************** - * Name: tc_y_sample - * - * Description: - * Initiate sampling on Y - * - ****************************************************************************/ - -static void tc_y_sample(void) -{ - /* Start the Y axis sampling */ - - tc_adc_start_sample(LCD_XL_CHANNEL); -} - -/**************************************************************************** - * Name: tc_x_sample - * - * Description: - * Initiate sampling on X - * - ****************************************************************************/ - -static void tc_x_sample(void) -{ - /* Start the X axis sampling */ - - tc_adc_start_sample(LCD_YD_CHANNEL); -} - -/**************************************************************************** - * Name: tc_valid_sample - ****************************************************************************/ - -static inline bool tc_valid_sample(uint16_t sample) -{ - return (sample > LOWER_THRESHOLD); -} - -/**************************************************************************** - * Name: tc_notify - ****************************************************************************/ - -static void tc_notify(struct tc_dev_s *priv) -{ - /* If no threads have the driver open, then just dump the state */ - -#ifdef CONFIG_TOUCHSCREEN_REFCNT - if ((priv->crefs == 0) && priv->sample.contact == CONTACT_UP) - { - priv->sample.contact = CONTACT_NONE; - priv->sample.valid = false; - priv->id++; - return; - } -#endif - - /* If there are threads waiting on poll() for touchscreen data to become - * available, then wake them up now. NOTE: we wake up all waiting threads - * because we do not know that they are going to do. If they all try to - * read the data, then some make end up blocking after all. - */ - - poll_notify(priv->fds, CONFIG_TOUCHSCREEN_NPOLLWAITERS, POLLIN); - - /* If there are threads waiting for read data, then signal one of them - * that the read data is available. - */ - - if (priv->nwaiters > 0) - { - /* After posting this semaphore, we need to exit because the - * touchscreen is no longer available. - */ - - nxsem_post(&priv->waitsem); - } -} - -/**************************************************************************** - * Name: tc_sample - * - * Assumptions: pre-emption is disabled - * - ****************************************************************************/ - -static int tc_sample(struct tc_dev_s *priv, - struct tc_sample_s *sample) -{ - int ret = -EAGAIN; - - /* Is there new touchscreen sample data available? */ - - if (priv->penchange) - { - /* Yes.. the state has changed in some way. Return a copy of the - * sampled data. - */ - - memcpy(sample, &priv->sample, sizeof(struct tc_sample_s)); - - /* Now manage state transitions */ - - if (sample->contact == CONTACT_UP) - { - /* Next.. no contact. Increment the ID so that next contact ID - * will be unique. X/Y positions are no longer valid. - */ - - priv->sample.contact = CONTACT_NONE; - priv->sample.valid = false; - priv->id++; - } - else if (sample->contact == CONTACT_DOWN) - { - /* First report -- next report will be a movement */ - - priv->sample.contact = CONTACT_MOVE; - } - - priv->penchange = false; - ret = OK; - } - - return ret; -} - -/**************************************************************************** - * Name: tc_waitsample - ****************************************************************************/ - -static int tc_waitsample(struct tc_dev_s *priv, - struct tc_sample_s *sample) -{ - int ret; - irqstate_t flags; - - /* Interrupts must be disabled when this is called to (1) prevent posting - * of semaphores from interrupt handlers, and (2) to prevent sampled data - * from changing until it has been reported. - */ - - flags = enter_critical_section(); - - /* Now release the mutex that manages mutually exclusive access to - * the device structure. This may cause other tasks to become ready to - * run, but they cannot run yet because pre-emption is disabled. - */ - - nxmutex_unlock(&priv->devlock); - - /* Try to get the a sample... if we cannot, then wait on the semaphore - * that is posted when new sample data is available. - */ - - while (tc_sample(priv, sample) < 0) - { - /* Wait for a change in the touchscreen state */ - - priv->nwaiters++; - ret = nxsem_wait(&priv->waitsem); - priv->nwaiters--; - - if (ret < 0) - { - goto errout; - } - } - - /* Re-acquire the semaphore that manages mutually exclusive access to - * the device structure. We may have to wait here. But we have our - * sample. Interrupts and pre-emption will be re-enabled while we wait. - */ - - ret = nxmutex_lock(&priv->devlock); - -errout: - /* Then re-enable interrupts. We might get interrupt here and there - * could be a new sample. But no new threads will run because we still - * have pre-emption disabled. - */ - - leave_critical_section(flags); - return ret; -} - -/**************************************************************************** - * Name: tc_worker - ****************************************************************************/ - -static void tc_worker(void *arg) -{ - struct tc_dev_s *priv = (struct tc_dev_s *)arg; - uint32_t delay = TC_PENUP_POLL_TICKS; - uint16_t value; - uint16_t newx = 0; - int16_t xdiff; - int16_t ydiff; - - DEBUGASSERT(priv != NULL); - - /* Perform the next action based on the state of the conversions */ - - switch (priv->state) - { - /* The touchscreen is IDLE and we are ready to begin the next sample */ - - case TC_READY: - { - /* Select DRIVE for Y sampling */ - - /* Configure XL, XR with drive voltages and disable YU drive. Note - * that this is configuring the DRIVEA and DRIVEB outputs to enable - * the on-board transistor drive logic to energize the touch panel. - */ - - *((uint32_t *)LCD_TP_PORT_SETRESET) = LCD_SAMPY_BITS; - - /* Allow time for the Y DRIVE to settle */ - - priv->resamplecount = 0; - priv->sampcount = 0; - priv->value = 0; - priv->state = TC_READY_SETTLE; - delay = TC_SETTLE_TICKS; - } - break; - - case TC_READY_SETTLE: - { - /* Start Y sampling */ - - tc_y_sample(); - - /* Allow time for the Y pend down sampling */ - - priv->state = TC_YPENDOWN; - delay = TC_SAMPLE_TICKS; - } - break; - - /* The Y sampling time has elapsed and the Y value should be ready - * for conversion - */ - - case TC_YPENDOWN: - { - /* Convert the Y sample value */ - - value = tc_adc_read_sample(); - - /* A converted value at the minimum would mean that there is no touch - * and that the sampling period is complete. - */ - - if (!tc_valid_sample(value)) - { - priv->state = TC_PENUP; - } - else - { - /* Allow time for touch inputs to stabilize */ - - priv->state = TC_DEBOUNCE; - delay = TC_DEBOUNCE_TICKS; - } - } - break; - - /* The debounce time period has elapsed and we are ready to re-sample - * the touchscreen. - */ - - case TC_RESAMPLE: - { - /* Select DRIVE for Y sampling */ - - /* Configure XL, XR with drive voltages and disable YU drive. Note - * that this is configuring the DRIVEA and DRIVEB outputs to enable - * the on-board transistor drive logic to energize the touch panel. - */ - - *((uint32_t *)LCD_TP_PORT_SETRESET) = LCD_SAMPY_BITS; - - /* Allow time for the Y DRIVE to settle */ - - priv->state = TC_DEBOUNCE; - delay = TC_SETTLE_TICKS; - } - break; - - case TC_DEBOUNCE: - { - /* (Re-)start Y sampling */ - - tc_y_sample(); - - /* Allow time for the Y sampling */ - - priv->state = TC_YSAMPLE; - delay = TC_SAMPLE_TICKS; - } - break; - - /* The Y sampling period has elapsed and we are ready to perform the - * conversion. - */ - - case TC_YSAMPLE: /* Allowing time for the Y sampling */ - { - /* Read the Y axis position */ - - value = tc_adc_read_sample(); - - /* A converted value at the minimum would mean that we lost the - * contact before all of the conversions were completed. At - * converted value at the maximum value is probably bad too. - */ - - if (!tc_valid_sample(value)) - { -#ifdef CONFIG_TOUCHSCREEN_RESAMPLE - priv->state = TC_RESAMPLE; - delay = TC_RESAMPLE_TICKS; -#else - priv->state = TC_PENUP; -#endif - } - else - { - value = MAX_ADC - value; - priv->value += value; - if (++priv->sampcount < CONFIG_TOUCHSCREEN_AVG_SAMPLES) - { - priv->state = TC_READY_SETTLE; - delay = 1; - break; - } - - priv->newy = value / CONFIG_TOUCHSCREEN_AVG_SAMPLES; - priv->value = 0; - priv->sampcount = 0; - iinfo("Y=%d\n", priv->newy); - - /* Configure YU and YD with drive voltages and disable XR drive. - * Note that this is configuring the DRIVEA and DRIVEB outputs - * to enable the on-board transistor drive logic to energize the - * touch panel. - */ - - *((uint32_t *)LCD_TP_PORT_SETRESET) = LCD_SAMPX_BITS; - - /* Allow time for the X sampling */ - - priv->state = TC_XSETTLE; - delay = TC_SETTLE_TICKS; - } - } - break; - - case TC_XRESAMPLE: /* Perform X resampling */ - { - if (priv->resamplecount-- == 0) - { - priv->state = TC_PENUP; - break; - } - } - - case TC_XSETTLE: /* Allowing time X to settle after changing DRIVE */ - { - /* The X Drive settling time has elaspsed and it's time to start - * the conversion - */ - - /* Start X sampling */ - - tc_x_sample(); - - /* Allow time for the X sampling */ - - priv->state = TC_XSAMPLE; - delay = TC_SAMPLE_TICKS; - } - break; - - case TC_XSAMPLE: /* Allowing time for the X sampling */ - { - /* Read the converted X axis position */ - - value = tc_adc_read_sample(); - - /* A converted value at the minimum would mean that we lost the - * contact before all of the conversions were completed. At - * converted value at the maximum value is probably bad too. - */ - - if (!tc_valid_sample(value)) - { -#ifdef CONFIG_TOUCHSCREEN_RESAMPLE - priv->state = TC_XRESAMPLE; - if (priv->resamplecount == 0) - priv->resamplecount = 1; - delay = TC_RESAMPLE_TICKS; -#else - priv->state = TC_PENUP; -#endif - } - else - { - /* Calculate the X axis position */ - - priv->value += value; - if (++priv->sampcount < CONFIG_TOUCHSCREEN_AVG_SAMPLES) - { - priv->state = TC_XSETTLE; - delay = 1; - break; - } - - newx = value / CONFIG_TOUCHSCREEN_AVG_SAMPLES; - iinfo("X=%d\n", newx); - - /* Samples are available */ - - priv->state = TC_PENDOWN; - } - } - break; - } - - /* Check for terminal conditions.. */ - - /* Check if the sampling resulted in a pen up decision. If so, we need to - * handle the change from pen down to pen up. - */ - - if (priv->state == TC_PENUP) - { - /* Ignore if the pen was already down (CONTACT_NONE == pen up and - * already reported. CONTACT_UP == pen up, but not reported) - */ - - if (priv->sample.contact != CONTACT_NONE && - priv->sample.contact != CONTACT_UP) - { - /* The pen is up. We know from the above test, that this is a - * loss of contact condition. This will be changed to CONTACT_NONE - * after the loss of contact is sampled. - */ - - priv->sample.contact = CONTACT_UP; - - /* Indicate the availability of new sample data for this ID */ - - priv->sample.id = priv->id; - priv->penchange = true; - - /* Notify any waiters that new touchscreen data is available */ - - iinfo("1:X=%d, Y=%d\n", priv->sample.x, priv->sample.y); - - tc_notify(priv); - } - - /* Set up for the next poll */ - - priv->sample.valid = false; - priv->state = TC_READY; - delay = TC_PENUP_POLL_TICKS; - } - - /* Check if the sampling resulted in a pen down decision. */ - - else if (priv->state == TC_PENDOWN) - { - /* It is a pen down event. If the last loss-of-contact event has not - * been processed yet, then we have to ignore the pen down event (or - * else it will look like a drag event) - */ - - if (priv->sample.contact != CONTACT_UP) - { - /* Perform a thresholding operation so that the results will be - * more stable. If the difference from the last sample is small, - * then ignore the event. - */ - - xdiff = (int16_t)priv->sample.x - (int16_t)newx; - if (xdiff < 0) - { - xdiff = -xdiff; - } - - ydiff = (int16_t)priv->sample.y - (int16_t)priv->newy; - if (ydiff < 0) - { - ydiff = -ydiff; - } - - if (xdiff >= CONFIG_TOUCHSCREEN_THRESHX || - ydiff >= CONFIG_TOUCHSCREEN_THRESHY) - { - /* There is some change above the threshold... - * Report the change. - */ - -#ifdef CONFIG_LCD_LANDSCAPE - priv->sample.x = MAX_ADC - priv->newy; - priv->sample.y = newx; -#else - priv->sample.x = newx; - priv->sample.y = priv->newy; -#endif - priv->sample.valid = true; - - /* If this is the first (acknowledged) penddown report, then - * report this as the 1st contact. If contact == CONTACT_DOWN, - * it will be set to set to CONTACT_MOVE after the contact is - * first sampled. - */ - - if (priv->sample.contact != CONTACT_MOVE) - { - /* First contact */ - - priv->sample.contact = CONTACT_DOWN; - } - - /* Indicate the availability of new sample data for this ID */ - - priv->sample.id = priv->id; - priv->penchange = true; - - /* Notify any waiters that nes touchscreen data is available */ - - iinfo("2:X=%d, Y=%d\n", priv->sample.x, priv->sample.y); - - tc_notify(priv); - } - } - - /* Set up for the next poll */ - - priv->state = TC_READY; - delay = TC_PENDOWN_POLL_TICKS; - } - - /* Set up the next sample event */ - - work_queue(HPWORK, &priv->work, tc_worker, priv, delay); -} - -/**************************************************************************** - * Name: tc_open - ****************************************************************************/ - -static int tc_open(struct file *filep) -{ -#ifdef CONFIG_TOUCHSCREEN_REFCNT - struct inode *inode; - struct tc_dev_s *priv; - uint8_t tmp; - int ret; - - inode = filep->f_inode; - - DEBUGASSERT(inode->i_private); - priv = inode->i_private; - - /* Get exclusive access to the driver data structure */ - - ret = nxmutex_lock(&priv->devlock); - if (ret < 0) - { - return ret; - } - - /* Increment the reference count */ - - tmp = priv->crefs + 1; - if (tmp == 0) - { - /* More than 255 opens; uint8_t overflows to zero */ - - ret = -EMFILE; - goto errout_with_lock; - } - - /* When the reference increments to 1, this is the first open event - * on the driver.. and an opportunity to do any one-time initialization. - */ - - /* Save the new open count on success */ - - priv->crefs = tmp; - -errout_with_lock: - nxmutex_unlock(&priv->devlock); - return ret; -#else - return OK; -#endif -} - -/**************************************************************************** - * Name: tc_close - ****************************************************************************/ - -static int tc_close(struct file *filep) -{ -#ifdef CONFIG_TOUCHSCREEN_REFCNT - struct inode *inode; - struct tc_dev_s *priv; - int ret; - - inode = filep->f_inode; - - DEBUGASSERT(inode->i_private); - priv = inode->i_private; - - /* Get exclusive access to the driver data structure */ - - ret = nxmutex_lock(&priv->devlock); - if (ret < 0) - { - return ret; - } - - /* Decrement the reference count unless it would decrement a negative - * value. When the count decrements to zero, there are no further - * open references to the driver. - */ - - if (priv->crefs >= 1) - { - priv->crefs--; - } - - nxmutex_unlock(&priv->devlock); -#endif - return OK; -} - -/**************************************************************************** - * Name: tc_read - ****************************************************************************/ - -static ssize_t tc_read(struct file *filep, char *buffer, size_t len) -{ - struct inode *inode; - struct tc_dev_s *priv; - struct touch_sample_s *report; - struct tc_sample_s sample; - int ret; - - inode = filep->f_inode; - - DEBUGASSERT(inode->i_private); - priv = inode->i_private; - - /* Verify that the caller has provided a buffer large enough to receive - * the touch data. - */ - - if (len < SIZEOF_TOUCH_SAMPLE_S(1)) - { - /* We could provide logic to break up a touch report into segments and - * handle smaller reads... but why? - */ - - return -ENOSYS; - } - - /* Get exclusive access to the driver data structure */ - - ret = nxmutex_lock(&priv->devlock); - if (ret < 0) - { - return ret; - } - - /* Try to read sample data. */ - - ret = tc_sample(priv, &sample); - if (ret < 0) - { - /* Sample data is not available now. We would ave to wait to get - * receive sample data. If the user has specified the O_NONBLOCK - * option, then just return an error. - */ - - if (filep->f_oflags & O_NONBLOCK) - { - ret = -EAGAIN; - goto errout; - } - - /* Wait for sample data */ - - ret = tc_waitsample(priv, &sample); - if (ret < 0) - { - /* We might have been awakened by a signal */ - - goto errout; - } - } - - /* In any event, we now have sampled touchscreen data that we can report - * to the caller. - */ - - report = (struct touch_sample_s *)buffer; - memset(report, 0, SIZEOF_TOUCH_SAMPLE_S(1)); - report->npoints = 1; - report->point[0].id = sample.id; - report->point[0].x = sample.x; - report->point[0].y = sample.y; - - /* Report the appropriate flags */ - - if (sample.contact == CONTACT_UP) - { - /* Pen is now up. Is the positional data valid? This is important to - * know because the release will be sent to the window based on its - * last positional data. - */ - - if (sample.valid) - { - report->point[0].flags = TOUCH_UP | TOUCH_ID_VALID | - TOUCH_POS_VALID | TOUCH_PRESSURE_VALID; - } - else - { - report->point[0].flags = TOUCH_UP | TOUCH_ID_VALID; - } - } - else - { - if (sample.contact == CONTACT_DOWN) - { - /* First contact */ - - report->point[0].flags = TOUCH_DOWN | TOUCH_ID_VALID | - TOUCH_POS_VALID; - } - else /* if (sample->contact == CONTACT_MOVE) */ - { - /* Movement of the same contact */ - - report->point[0].flags = TOUCH_MOVE | TOUCH_ID_VALID | - TOUCH_POS_VALID; - } - } - - ret = SIZEOF_TOUCH_SAMPLE_S(1); - -errout: - nxmutex_unlock(&priv->devlock); - return ret; -} - -/**************************************************************************** - * Name: tc_ioctl - ****************************************************************************/ - -static int tc_ioctl(struct file *filep, int cmd, unsigned long arg) -{ -#if 1 - iinfo("cmd: %d arg: %ld\n", cmd, arg); - return -ENOTTY; /* None yet supported */ -#else - struct inode *inode; - struct tc_dev_s *priv; - int ret; - - iinfo("cmd: %d arg: %ld\n", cmd, arg); - inode = filep->f_inode; - - DEBUGASSERT(inode->i_private); - priv = inode->i_private; - - /* Get exclusive access to the driver data structure */ - - ret = nxmutex_lock(&priv->devlock); - if (ret < 0) - { - return ret; - } - - /* Process the IOCTL by command */ - - switch (cmd) - { - /* ADD IOCTL COMMAND CASES HERE */ - - default: - ret = -ENOTTY; - break; - } - - nxmutex_unlock(&priv->devlock); - return ret; -#endif -} - -/**************************************************************************** - * Name: tc_poll - ****************************************************************************/ - -static int tc_poll(struct file *filep, struct pollfd *fds, bool setup) -{ - struct inode *inode; - struct tc_dev_s *priv; - int ret; - int i; - - iinfo("setup: %d\n", (int)setup); - DEBUGASSERT(fds); - inode = filep->f_inode; - - DEBUGASSERT(inode->i_private); - priv = inode->i_private; - - /* Are we setting up the poll? Or tearing it down? */ - - ret = nxmutex_lock(&priv->devlock); - if (ret < 0) - { - return ret; - } - - if (setup) - { - /* Ignore waits that do not include POLLIN */ - - if ((fds->events & POLLIN) == 0) - { - ierr("ERROR: Missing POLLIN: revents: %08" PRIx32 "\n", - fds->revents); - ret = -EDEADLK; - goto errout; - } - - /* This is a request to set up the poll. Find an available - * slot for the poll structure reference - */ - - for (i = 0; i < CONFIG_TOUCHSCREEN_NPOLLWAITERS; i++) - { - /* Find an available slot */ - - if (!priv->fds[i]) - { - /* Bind the poll structure and this slot */ - - priv->fds[i] = fds; - fds->priv = &priv->fds[i]; - break; - } - } - - if (i >= CONFIG_TOUCHSCREEN_NPOLLWAITERS) - { - ierr("ERROR: No available slot found: %d\n", i); - fds->priv = NULL; - ret = -EBUSY; - goto errout; - } - - /* Should we immediately notify on any of the requested events? */ - - if (priv->penchange) - { - poll_notify(&fds, 1, POLLIN); - } - } - else if (fds->priv) - { - /* This is a request to tear down the poll. */ - - struct pollfd **slot = (struct pollfd **)fds->priv; - DEBUGASSERT(slot != NULL); - - /* Remove all memory of the poll setup */ - - *slot = NULL; - fds->priv = NULL; - } - -errout: - nxmutex_unlock(&priv->devlock); - return ret; -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_tsc_setup - * - * Description: - * This function is called by board-bringup logic to configure the - * touchscreen device. This function will register the driver as - * /dev/inputN where N is the minor device number. - * - * Input Parameters: - * minor - The input device minor number - * - * Returned Value: - * Zero is returned on success. Otherwise, a negated errno value is - * returned to indicate the nature of the failure. - * - ****************************************************************************/ - -int stm32_tsc_setup(int minor) -{ - struct tc_dev_s *priv; - char devname[DEV_NAMELEN]; -#ifdef CONFIG_TOUCHSCREEN_MULTIPLE - irqstate_t flags; -#endif - int ret; - - iinfo("minor: %d\n", minor); - DEBUGASSERT(minor >= 0 && minor < 100); - - /* If we only have one touchscreen, check if we already did init */ - -#ifndef CONFIG_TOUCHSCREEN_MULTIPLE - if (g_touchinitdone) - { - return OK; - } -#endif - - /* Configure the touchscreen DRIVEA and DRIVEB pins for output */ - - stm32_configgpio(GPIO_TP_DRIVEA); - stm32_configgpio(GPIO_TP_DRIVEB); - - /* Configure Analog inputs for sampling X and Y coordinates */ - - stm32_configgpio(GPIO_TP_XL); - stm32_configgpio(GPIO_TP_YD); - - tc_adc_init(); - - /* Create and initialize a touchscreen device driver instance */ - -#ifndef CONFIG_TOUCHSCREEN_MULTIPLE - priv = &g_touchscreen; -#else - priv = kmm_malloc(sizeof(struct tc_dev_s)); - if (!priv) - { - ierr("ERROR: kmm_malloc(%d) failed\n", sizeof(struct tc_dev_s)); - return -ENOMEM; - } -#endif - - /* Initialize the touchscreen device driver instance */ - - memset(priv, 0, sizeof(struct tc_dev_s)); - nxmutex_init(&priv->devlock); /* Initialize device structure mutex */ - nxsem_init(&priv->waitsem, 0, 0); /* Initialize pen event wait semaphore */ - - /* Register the device as an input device */ - - snprintf(devname, sizeof(devname), DEV_FORMAT, minor); - iinfo("Registering %s\n", devname); - - ret = register_driver(devname, &g_tc_fops, 0666, priv); - if (ret < 0) - { - ierr("ERROR: register_driver() failed: %d\n", ret); - goto errout_with_priv; - } - - /* Schedule work to perform the initial sampling and to set the data - * availability conditions. - */ - - priv->state = TC_READY; - ret = work_queue(HPWORK, &priv->work, tc_worker, priv, 0); - if (ret != 0) - { - ierr("ERROR: Failed to queue work: %d\n", ret); - goto errout_with_priv; - } - - /* And return success (?) */ - -#ifndef CONFIG_TOUCHSCREEN_MULTIPLE - g_touchinitdone = true; -#endif - - return OK; - -errout_with_priv: - nxmutex_destroy(&priv->devlock); - nxsem_destroy(&priv->waitsem); -#ifdef CONFIG_TOUCHSCREEN_MULTIPLE - kmm_free(priv); -#endif - return ret; -} - -#endif /* CONFIG_INPUT */ diff --git a/boards/arm/stm32/mikroe-stm32f4/src/stm32_usb.c b/boards/arm/stm32/mikroe-stm32f4/src/stm32_usb.c deleted file mode 100644 index bba5752941bad..0000000000000 --- a/boards/arm/stm32/mikroe-stm32f4/src/stm32_usb.c +++ /dev/null @@ -1,304 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/mikroe-stm32f4/src/stm32_usb.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -#include "arm_internal.h" -#include "stm32.h" -#include "stm32_otgfs.h" -#include "mikroe-stm32f4.h" - -#ifdef CONFIG_STM32_OTGFS - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#if defined(CONFIG_USBDEV) || defined(CONFIG_USBHOST) -# define HAVE_USB 1 -#else -# warning "CONFIG_STM32_OTGFS is enabled but neither CONFIG_USBDEV nor CONFIG_USBHOST" -# undef HAVE_USB -#endif - -#ifndef CONFIG_USBHOST_DEFPRIO -# define CONFIG_USBHOST_DEFPRIO 50 -#endif - -#ifndef CONFIG_USBHOST_STACKSIZE -# ifdef CONFIG_USBHOST_HUB -# define CONFIG_USBHOST_STACKSIZE 1536 -# else -# define CONFIG_USBHOST_STACKSIZE 1024 -# endif -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -#ifdef CONFIG_USBHOST -static struct usbhost_connection_s *g_usbconn; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: usbhost_waiter - * - * Description: - * Wait for USB devices to be connected. - * - ****************************************************************************/ - -#ifdef CONFIG_USBHOST -static int usbhost_waiter(int argc, char *argv[]) -{ - struct usbhost_hubport_s *hport; - - uinfo("Running\n"); - for (; ; ) - { - /* Wait for the device to change state */ - - DEBUGVERIFY(CONN_WAIT(g_usbconn, &hport)); - uinfo("%s\n", hport->connected ? "connected" : "disconnected"); - - /* Did we just become connected? */ - - if (hport->connected) - { - /* Yes.. enumerate the newly connected device */ - - CONN_ENUMERATE(g_usbconn, hport); - } - } - - /* Keep the compiler from complaining */ - - return 0; -} -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_usbinitialize - * - * Description: - * Called from stm32_usbinitialize very early in initialization to setup - * USB-related GPIO pins for the STM32F4Discovery board. - * - ****************************************************************************/ - -void stm32_usbinitialize(void) -{ - /* The OTG FS has an internal soft pull-up. - * No GPIO configuration is required - */ - - /* Configure the OTG FS VBUS sensing GPIO, - * Power On, and Overcurrent GPIOs - */ - -#ifdef CONFIG_STM32_OTGFS - stm32_configgpio(GPIO_OTGFS_VBUS); - stm32_configgpio(GPIO_OTGFS_PWRON); - stm32_configgpio(GPIO_OTGFS_OVER); -#endif -} - -/**************************************************************************** - * Name: stm32_usbhost_initialize - * - * Description: - * Called at application startup time to initialize the USB host - * functionality. - * This function will start a thread that will monitor for device - * connection/disconnection events. - * - ****************************************************************************/ - -#ifdef CONFIG_USBHOST -int stm32_usbhost_initialize(void) -{ - int ret; - - /* First, register all of the class drivers needed to support the drivers - * that we care about: - */ - - uinfo("Register class drivers\n"); - -#ifdef CONFIG_USBHOST_MSC - /* Register the USB host Mass Storage Class */ - - ret = usbhost_msc_initialize(); - if (ret != OK) - { - uerr("ERROR: Failed to register the mass storage class: %d\n", ret); - } -#endif - -#ifdef CONFIG_USBHOST_CDCACM - /* Register the CDC/ACM serial class */ - - ret = usbhost_cdcacm_initialize(); - if (ret != OK) - { - uerr("ERROR: Failed to register the CDC/ACM serial class: %d\n", ret); - } -#endif - - /* Then get an instance of the USB host interface */ - - uinfo("Initialize USB host\n"); - g_usbconn = stm32_otgfshost_initialize(0); - if (g_usbconn) - { - /* Start a thread to handle device connection. */ - - uinfo("Start usbhost_waiter\n"); - - ret = kthread_create("usbhost", CONFIG_USBHOST_DEFPRIO, - CONFIG_USBHOST_STACKSIZE, - usbhost_waiter, NULL); - return ret < 0 ? -ENOEXEC : OK; - } - - return -ENODEV; -} -#endif - -/**************************************************************************** - * Name: stm32_usbhost_vbusdrive - * - * Description: - * Enable/disable driving of VBUS 5V output. This function must be - * provided be each platform that implements the STM32 OTG FS host - * interface - * - * "On-chip 5 V VBUS generation is not supported. For this reason, a - * charge pump or, if 5 V are available on the application board, a - * basic power switch, must be added externally to drive the 5 V VBUS - * line. The external charge pump can be driven by any GPIO output. - * When the application decides to power on VBUS using the chosen GPIO, - * it must also set the port power bit in the host port control and - * status register (PPWR bit in OTG_FS_HPRT). - * - * "The application uses this field to control power to this port, - * and the core clears this bit on an overcurrent condition." - * - * Input Parameters: - * iface - For future growth to handle multiple USB host interface. - * Should be zero. - * enable - true: enable VBUS power; false: disable VBUS power - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef CONFIG_USBHOST -void stm32_usbhost_vbusdrive(int iface, bool enable) -{ - DEBUGASSERT(iface == 0); - - if (enable) - { - /* Enable the Power Switch by driving the enable pin low */ - - stm32_gpiowrite(GPIO_OTGFS_PWRON, false); - } - else - { - /* Disable the Power Switch by driving the enable pin high */ - - stm32_gpiowrite(GPIO_OTGFS_PWRON, true); - } -} -#endif - -/**************************************************************************** - * Name: stm32_setup_overcurrent - * - * Description: - * Setup to receive an interrupt-level callback if an overcurrent - * condition is detected. - * - * Input Parameters: - * handler - New overcurrent interrupt handler - * arg - The argument provided for the interrupt handler - * - * Returned Value: - * Zero (OK) is returned on success. Otherwise, a negated errno value - * is returned to indicate the nature of the failure. - * - ****************************************************************************/ - -#ifdef CONFIG_USBHOST -int stm32_setup_overcurrent(xcpt_t handler, void *arg) -{ - return stm32_gpiosetevent(GPIO_OTGFS_OVER, true, true, true, handler, arg); -} -#endif - -/**************************************************************************** - * Name: stm32_usbsuspend - * - * Description: - * Board logic must provide the stm32_usbsuspend logic if the USBDEV - * driver is used. This function is called whenever the USB enters or - * leaves suspend mode. This is an opportunity for the board logic to - * shutdown clocks, power, etc. while the USB is suspended. - * - ****************************************************************************/ - -#ifdef CONFIG_USBDEV -void stm32_usbsuspend(struct usbdev_s *dev, bool resume) -{ - uinfo("resume: %d\n", resume); -} -#endif - -#endif /* CONFIG_STM32_OTGFS */ diff --git a/boards/arm/stm32/nucleo-f103rb/CMakeLists.txt b/boards/arm/stm32/nucleo-f103rb/CMakeLists.txt deleted file mode 100644 index 3444cc83430de..0000000000000 --- a/boards/arm/stm32/nucleo-f103rb/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/nucleo-f103rb/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32/nucleo-f103rb/configs/adc/defconfig b/boards/arm/stm32/nucleo-f103rb/configs/adc/defconfig deleted file mode 100644 index 46570b4a60830..0000000000000 --- a/boards/arm/stm32/nucleo-f103rb/configs/adc/defconfig +++ /dev/null @@ -1,53 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -CONFIG_ADC=y -CONFIG_ADC_FIFOSIZE=4 -CONFIG_ANALOG=y -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="nucleo-f103rb" -CONFIG_ARCH_BOARD_NUCLEO_F103RB=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F103RB=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=5483 -CONFIG_BUILTIN=y -CONFIG_DEBUG_FULLOPT=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_DEFAULT_SMALL=y -CONFIG_FILE_STREAM=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=80 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=1024 -CONFIG_RAM_SIZE=20480 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_HPWORKPRIORITY=192 -CONFIG_SCHED_WAITPID=y -CONFIG_SERIAL_TERMIOS=y -CONFIG_START_DAY=5 -CONFIG_START_MONTH=7 -CONFIG_START_YEAR=2011 -CONFIG_STM32_ADC1=y -CONFIG_STM32_ADC1_DMA=y -CONFIG_STM32_ADC2=y -CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32_DMA1=y -CONFIG_STM32_FORCEPOWER=y -CONFIG_STM32_JTAG_FULL_ENABLE=y -CONFIG_STM32_TIM1=y -CONFIG_STM32_TIM1_ADC=y -CONFIG_STM32_USART2=y -CONFIG_SYMTAB_ORDEREDBYNAME=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/nucleo-f103rb/configs/ihm07m1_b16/defconfig b/boards/arm/stm32/nucleo-f103rb/configs/ihm07m1_b16/defconfig deleted file mode 100644 index e8185cb780297..0000000000000 --- a/boards/arm/stm32/nucleo-f103rb/configs/ihm07m1_b16/defconfig +++ /dev/null @@ -1,85 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_DISABLE_MQUEUE is not set -# CONFIG_DISABLE_PTHREAD is not set -CONFIG_ADC=y -CONFIG_ADC_FIFOSIZE=3 -CONFIG_ANALOG=y -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="nucleo-f103rb" -CONFIG_ARCH_BOARD_COMMON=y -CONFIG_ARCH_BOARD_NUCLEO_F103RB=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F103RB=y -CONFIG_ARCH_INTERRUPTSTACK=1024 -CONFIG_ARCH_IRQBUTTONS=y -CONFIG_BOARDCTL=y -CONFIG_BOARD_LOOPSPERMSEC=8499 -CONFIG_BOARD_STM32_IHM07M1=y -CONFIG_BOARD_STM32_IHM07M1_POT=y -CONFIG_BOARD_STM32_IHM07M1_VBUS=y -CONFIG_BUILTIN=y -CONFIG_DEBUG_FULLOPT=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_DEFAULT_SMALL=y -CONFIG_DEFAULT_TASK_STACKSIZE=1024 -CONFIG_EXAMPLES_FOC=y -CONFIG_EXAMPLES_FOC_ADC_MAX=4095 -CONFIG_EXAMPLES_FOC_ADC_VREF=3300 -CONFIG_EXAMPLES_FOC_CONTROL_STACKSIZE=2048 -CONFIG_EXAMPLES_FOC_FIXED16_INST=1 -CONFIG_EXAMPLES_FOC_HAVE_BUTTON=y -CONFIG_EXAMPLES_FOC_NOTIFIER_FREQ=5000 -CONFIG_EXAMPLES_FOC_PWM_FREQ=20000 -CONFIG_EXAMPLES_FOC_RAMP_ACC=1000000 -CONFIG_EXAMPLES_FOC_RAMP_DEC=1000000 -CONFIG_EXAMPLES_FOC_RAMP_THR=10000 -CONFIG_EXAMPLES_FOC_SETPOINT_ADC=y -CONFIG_EXAMPLES_FOC_VBUS_ADC=y -CONFIG_EXAMPLES_FOC_VBUS_SCALE=19152 -CONFIG_INDUSTRY_FOC=y -CONFIG_INDUSTRY_FOC_FIXED16=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INPUT=y -CONFIG_INPUT_BUTTONS=y -CONFIG_INPUT_BUTTONS_LOWER=y -CONFIG_INTELHEX_BINARY=y -CONFIG_LIBM=y -CONFIG_MOTOR=y -CONFIG_MOTOR_FOC=y -CONFIG_MOTOR_FOC_TRACE=y -CONFIG_MQ_MAXMSGSIZE=5 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_RAM_SIZE=16386 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=14 -CONFIG_START_MONTH=10 -CONFIG_START_YEAR=2014 -CONFIG_STM32_ADC1_ANIOC_TRIGGER=1 -CONFIG_STM32_ADC1_DMA=y -CONFIG_STM32_ADC1_INJECTED_CHAN=3 -CONFIG_STM32_DMA1=y -CONFIG_STM32_DMA2=y -CONFIG_STM32_FOC=y -CONFIG_STM32_FOC_FOC0=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_TIM1_CH1MODE=0 -CONFIG_STM32_TIM1_CH2MODE=0 -CONFIG_STM32_TIM1_CH3MODE=0 -CONFIG_STM32_TIM1_MODE=2 -CONFIG_STM32_TIM1_PARTIAL_REMAP=y -CONFIG_STM32_USART2=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART2_SERIAL_CONSOLE=y -CONFIG_USART2_TXDMA=y diff --git a/boards/arm/stm32/nucleo-f103rb/configs/nsh/defconfig b/boards/arm/stm32/nucleo-f103rb/configs/nsh/defconfig deleted file mode 100644 index 2be574f9f8662..0000000000000 --- a/boards/arm/stm32/nucleo-f103rb/configs/nsh/defconfig +++ /dev/null @@ -1,42 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="nucleo-f103rb" -CONFIG_ARCH_BOARD_NUCLEO_F103RB=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F103RB=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=5483 -CONFIG_BUILTIN=y -CONFIG_DEBUG_FULLOPT=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_DEFAULT_SMALL=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=80 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=1024 -CONFIG_RAM_SIZE=20480 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_HPWORKPRIORITY=192 -CONFIG_SCHED_WAITPID=y -CONFIG_SERIAL_TERMIOS=y -CONFIG_START_DAY=5 -CONFIG_START_MONTH=7 -CONFIG_START_YEAR=2011 -CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32_JTAG_FULL_ENABLE=y -CONFIG_STM32_USART2=y -CONFIG_SYMTAB_ORDEREDBYNAME=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/nucleo-f103rb/configs/pwm/defconfig b/boards/arm/stm32/nucleo-f103rb/configs/pwm/defconfig deleted file mode 100644 index 1fd7b4dd5e8c9..0000000000000 --- a/boards/arm/stm32/nucleo-f103rb/configs/pwm/defconfig +++ /dev/null @@ -1,49 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="nucleo-f103rb" -CONFIG_ARCH_BOARD_NUCLEO_F103RB=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F103RB=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=5483 -CONFIG_BUILTIN=y -CONFIG_DEBUG_FULLOPT=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_DEFAULT_SMALL=y -CONFIG_EXAMPLES_PWM=y -CONFIG_FILE_STREAM=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=80 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=1024 -CONFIG_PWM=y -CONFIG_RAM_SIZE=20480 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_HPWORKPRIORITY=192 -CONFIG_SCHED_WAITPID=y -CONFIG_SERIAL_TERMIOS=y -CONFIG_START_DAY=5 -CONFIG_START_MONTH=7 -CONFIG_START_YEAR=2011 -CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32_FORCEPOWER=y -CONFIG_STM32_JTAG_FULL_ENABLE=y -CONFIG_STM32_TIM1=y -CONFIG_STM32_TIM1_CH1OUT=y -CONFIG_STM32_TIM1_PWM=y -CONFIG_STM32_USART2=y -CONFIG_SYMTAB_ORDEREDBYNAME=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/nucleo-f103rb/configs/qenco/defconfig b/boards/arm/stm32/nucleo-f103rb/configs/qenco/defconfig deleted file mode 100644 index df060b58063de..0000000000000 --- a/boards/arm/stm32/nucleo-f103rb/configs/qenco/defconfig +++ /dev/null @@ -1,55 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="nucleo-f103rb" -CONFIG_ARCH_BOARD_COMMON=y -CONFIG_ARCH_BOARD_NUCLEO_F103RB=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F103RB=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=5483 -CONFIG_BUILTIN=y -CONFIG_DEBUG_FULLOPT=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_DEFAULT_SMALL=y -CONFIG_EXAMPLES_QENCODER=y -CONFIG_EXAMPLES_QENCODER_HAVE_MAXPOS=y -CONFIG_EXAMPLES_QENCODER_MAXPOS=8192 -CONFIG_FILE_STREAM=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=80 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=1024 -CONFIG_RAM_SIZE=20480 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_HPWORKPRIORITY=192 -CONFIG_SCHED_WAITPID=y -CONFIG_SENSORS=y -CONFIG_SENSORS_QENCODER=y -CONFIG_SERIAL_TERMIOS=y -CONFIG_START_DAY=5 -CONFIG_START_MONTH=7 -CONFIG_START_YEAR=2011 -CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_QENCODER_DISABLE_EXTEND16BTIMERS=y -CONFIG_STM32_QENCODER_SAMPLE_FDTS_2=y -CONFIG_STM32_TIM2=y -CONFIG_STM32_TIM2_PARTIAL_REMAP_1=y -CONFIG_STM32_TIM2_QE=y -CONFIG_STM32_TIM2_QEPSC=0 -CONFIG_STM32_USART2=y -CONFIG_SYMTAB_ORDEREDBYNAME=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/nucleo-f103rb/include/board.h b/boards/arm/stm32/nucleo-f103rb/include/board.h deleted file mode 100644 index 6eb712c909cf5..0000000000000 --- a/boards/arm/stm32/nucleo-f103rb/include/board.h +++ /dev/null @@ -1,251 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f103rb/include/board.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __BOARDS_ARM_STM32_NUCLEO_F103RB_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32_NUCLEO_F103RB_INCLUDE_BOARD_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#ifndef __ASSEMBLY__ -# include -# include -#endif - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Clocking *****************************************************************/ - -/* HSI - Internal 8 MHz RC Oscillator - * LSI - 32 KHz RC - * HSE - 8 MHz from MCO output of ST-LINK - * LSE - 32.768 kHz - */ - -#define STM32_BOARD_XTAL 8000000ul /* X1 on board */ - -#define STM32_HSI_FREQUENCY 8000000ul -#define STM32_LSI_FREQUENCY 40000 /* Between 30kHz and 60kHz */ -#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL -#define STM32_LSE_FREQUENCY 32768 /* X2 on board */ - -/* PLL source is HSE/1, PLL multiplier is 9: - * PLL frequency is 8MHz (XTAL) x 9 = 72MHz - */ - -#define STM32_CFGR_PLLSRC RCC_CFGR_PLLSRC -#define STM32_CFGR_PLLXTPRE 0 -#define STM32_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx9 -#define STM32_PLL_FREQUENCY (9*STM32_BOARD_XTAL) - -/* Use the PLL and set the SYSCLK source to be the PLL */ - -#define STM32_SYSCLK_SW RCC_CFGR_SW_PLL -#define STM32_SYSCLK_SWS RCC_CFGR_SWS_PLL -#define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY - -/* AHB clock (HCLK) is SYSCLK (72MHz) */ - -#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK -#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY - -/* APB2 clock (PCLK2) is HCLK (72MHz) */ - -#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK -#define STM32_PCLK2_FREQUENCY STM32_HCLK_FREQUENCY -#define STM32_APB2_CLKIN (STM32_PCLK2_FREQUENCY) /* Timers 1 and 8, 15-17 */ - -/* APB1 clock (PCLK1) is HCLK/2 (36MHz) */ - -#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd2 -#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/2) - -/* APB2 TIM 1 will receive PCLK2 (72MHz) */ - -#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) - -/* APB1 TIM 2-4 will be twice PCLK1 (72MHz) */ - -#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) - -/* LED definitions **********************************************************/ - -/* The Nucleo F103RB board has three LEDs. Two of these are controlled by - * logic on the board and are not available for software control: - * - * LD1 COM: LD1 default status is red. LD1 turns to green to indicate that - * communications are in progress between the PC and the - * ST-LINK/V2-1. - * LD3 PWR: red LED indicates that the board is powered. - * - * And one can be controlled by software: - * - * User LD2: green LED is a user LED connected to the I/O PA5 of the - * STM32F103RBT6. - * - * If CONFIG_ARCH_LEDS is not defined, then the user can control the LED in - * any way. The following definition is used to access the LED. - */ - -/* LED index values for use with board_userled() */ - -#define BOARD_LED1 0 /* User LD2 */ -#define BOARD_NLEDS 1 - -/* LED bits for use with board_userled_all() */ - -#define BOARD_LED1_BIT (1 << BOARD_LED1) - -/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the LED on board - * the Nucleo F103RB. The following definitions describe how NuttX controls - * the LED: - * - * SYMBOL Meaning LED1 state - * ------------------ ----------------------- ---------- - * LED_STARTED NuttX has been started OFF - * LED_HEAPALLOCATE Heap has been allocated OFF - * LED_IRQSENABLED Interrupts enabled OFF - * LED_STACKCREATED Idle stack created ON - * LED_INIRQ In an interrupt No change - * LED_SIGNAL In a signal handler No change - * LED_ASSERTION An assertion failed No change - * LED_PANIC The system has crashed Blinking - * LED_IDLE STM32 is in sleep mode Not used - */ - -#define LED_STARTED 0 -#define LED_HEAPALLOCATE 0 -#define LED_IRQSENABLED 0 -#define LED_STACKCREATED 1 -#define LED_INIRQ 2 -#define LED_SIGNAL 2 -#define LED_ASSERTION 2 -#define LED_PANIC 1 - -/* Button definitions *******************************************************/ - -/* The Nucleo F103RB supports two buttons; only one button is controllable - * by software: - * - * B1 USER: user button connected to the I/O PC13 of the STM32F103RBT6. - * B2 RESET: push button connected to NRST is used to RESET the - * STM32F103RBT6. - */ - -#define BUTTON_USER 0 -#define NUM_BUTTONS 1 - -#define BUTTON_USER_BIT (1 << BUTTON_USER) - -/* Alternate function pin selections ****************************************/ - -/* DMA channels *************************************************************/ - -/* ADC */ - -#define ADC1_DMA_CHAN DMACHAN_ADC1 /* DMA1_CH1 */ - -#ifdef CONFIG_BOARD_STM32_IHM07M1 - -/* Configuration specific for the X-NUCLEO-IHM07M1 expansion board with - * the L6230 gate drivers. - */ - -/* TIM1 configuration *******************************************************/ - -/* Configured in stm32/hardware/stm32f103r_pinmap.h */ - -/* UVW ENABLE */ - -# define GPIO_FOC_EN_U (GPIO_OUTPUT|GPIO_CNF_OUTPP|GPIO_MODE_50MHz| \ - GPIO_OUTPUT_CLEAR|GPIO_PORTC|GPIO_PIN10) -# define GPIO_FOC_EN_V (GPIO_OUTPUT|GPIO_CNF_OUTPP|GPIO_MODE_50MHz| \ - GPIO_OUTPUT_CLEAR|GPIO_PORTC|GPIO_PIN11) -# define GPIO_FOC_EN_W (GPIO_OUTPUT|GPIO_CNF_OUTPP|GPIO_MODE_50MHz| \ - GPIO_OUTPUT_CLEAR|GPIO_PORTC|GPIO_PIN12) - -/* DIAG/ENABLE */ - -# define GPIO_FOC_DIAGEN (GPIO_OUTPUT|GPIO_CNF_OUTOD|GPIO_MODE_50MHz| \ - GPIO_OUTPUT_CLEAR|GPIO_PORTA|GPIO_PIN11) - -# define GPIO_FOC_LED2 (GPIO_OUTPUT|GPIO_CNF_OUTPP|GPIO_MODE_50MHz| \ - GPIO_OUTPUT_CLEAR|GPIO_PORTB|GPIO_PIN2) - -/* Debug pins */ - -# define GPIO_FOC_DEBUG0 (GPIO_OUTPUT|GPIO_CNF_OUTPP|GPIO_MODE_50MHz| \ - GPIO_OUTPUT_CLEAR|GPIO_PORTB|GPIO_PIN8) -# define GPIO_FOC_DEBUG1 (GPIO_OUTPUT|GPIO_CNF_OUTPP|GPIO_MODE_50MHz| \ - GPIO_OUTPUT_CLEAR|GPIO_PORTB|GPIO_PIN9) -# define GPIO_FOC_DEBUG2 (GPIO_OUTPUT|GPIO_CNF_OUTPP|GPIO_MODE_50MHz| \ - GPIO_OUTPUT_CLEAR|GPIO_PORTC|GPIO_PIN6) -# define GPIO_FOC_DEBUG3 (GPIO_OUTPUT|GPIO_CNF_OUTPP|GPIO_MODE_50MHz| \ - GPIO_OUTPUT_CLEAR|GPIO_PORTC|GPIO_PIN5) - -#endif /* CONFIG_BOARD_STM32_IHM07M1 */ - -/* Alternate function pin selections (auto-aliased for new pinmap) */ - -/* USART2 */ - -#define GPIO_USART2_TX GPIO_ADJUST_MODE(GPIO_USART2_TX_0, GPIO_MODE_50MHz) -#define GPIO_USART2_RX GPIO_USART2_RX_0 -#define GPIO_USART2_CTS GPIO_USART2_CTS_0 -#define GPIO_USART2_RTS GPIO_ADJUST_MODE(GPIO_USART2_RTS_0, GPIO_MODE_50MHz) -#define GPIO_USART2_CK GPIO_ADJUST_MODE(GPIO_USART2_CK_0, GPIO_MODE_50MHz) - -/* TIM1 */ - -#define GPIO_TIM1_CH1IN GPIO_TIM1_CH1IN_0 -#define GPIO_TIM1_CH1OUT GPIO_ADJUST_MODE(GPIO_TIM1_CH1OUT_0, GPIO_MODE_50MHz) -#define GPIO_TIM1_CH2IN GPIO_TIM1_CH2IN_0 -#define GPIO_TIM1_CH2OUT GPIO_ADJUST_MODE(GPIO_TIM1_CH2OUT_0, GPIO_MODE_50MHz) -#define GPIO_TIM1_CH3IN GPIO_TIM1_CH3IN_0 -#define GPIO_TIM1_CH3OUT GPIO_ADJUST_MODE(GPIO_TIM1_CH3OUT_0, GPIO_MODE_50MHz) -#define GPIO_TIM1_CH4IN GPIO_TIM1_CH4IN_0 -#define GPIO_TIM1_CH4OUT GPIO_ADJUST_MODE(GPIO_TIM1_CH4OUT_0, GPIO_MODE_50MHz) -#define GPIO_TIM1_BKIN GPIO_TIM1_BKIN_0 -#define GPIO_TIM1_ETR GPIO_TIM1_ETR_0 -#define GPIO_TIM1_CH1NOUT GPIO_ADJUST_MODE(GPIO_TIM1_CH1NOUT_0, GPIO_MODE_50MHz) -#define GPIO_TIM1_CH2NOUT GPIO_ADJUST_MODE(GPIO_TIM1_CH2NOUT_0, GPIO_MODE_50MHz) -#define GPIO_TIM1_CH3NOUT GPIO_ADJUST_MODE(GPIO_TIM1_CH3NOUT_0, GPIO_MODE_50MHz) - -/* TIM2 */ - -#define GPIO_TIM2_CH1IN GPIO_TIM2_CH1IN_0 -#define GPIO_TIM2_CH1OUT GPIO_ADJUST_MODE(GPIO_TIM2_CH1OUT_0, GPIO_MODE_50MHz) -#define GPIO_TIM2_CH2IN GPIO_TIM2_CH2IN_0 -#define GPIO_TIM2_CH2OUT GPIO_ADJUST_MODE(GPIO_TIM2_CH2OUT_0, GPIO_MODE_50MHz) -#define GPIO_TIM2_CH3IN GPIO_TIM2_CH3IN_0 -#define GPIO_TIM2_CH3OUT GPIO_ADJUST_MODE(GPIO_TIM2_CH3OUT_0, GPIO_MODE_50MHz) -#define GPIO_TIM2_CH4IN GPIO_TIM2_CH4IN_0 -#define GPIO_TIM2_CH4OUT GPIO_ADJUST_MODE(GPIO_TIM2_CH4OUT_0, GPIO_MODE_50MHz) - -#endif /* __BOARDS_ARM_STM32_NUCLEO_F103RB_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32/nucleo-f103rb/scripts/Make.defs b/boards/arm/stm32/nucleo-f103rb/scripts/Make.defs deleted file mode 100644 index a9ad56f5283cd..0000000000000 --- a/boards/arm/stm32/nucleo-f103rb/scripts/Make.defs +++ /dev/null @@ -1,41 +0,0 @@ -############################################################################ -# boards/arm/stm32/nucleo-f103rb/scripts/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/.config -include $(TOPDIR)/tools/Config.mk -include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs - -LDSCRIPT = ld.script -ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) - -ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 - -CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) -CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) -CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -AFLAGS := $(CFLAGS) -D__ASSEMBLY__ - -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections -LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32/nucleo-f103rb/scripts/ld.script b/boards/arm/stm32/nucleo-f103rb/scripts/ld.script deleted file mode 100644 index 26fb217a12ab3..0000000000000 --- a/boards/arm/stm32/nucleo-f103rb/scripts/ld.script +++ /dev/null @@ -1,127 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f103rb/scripts/ld.script - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* The STM32F103RBT6 has 128Kb of FLASH beginning at address 0x0800:0000 and - * 20Kb of SRAM. - * - * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 - * where the code expects to begin execution by jumping to the entry point in - * the 0x0800:0000 address range. - */ - -MEMORY -{ - flash (rx) : ORIGIN = 0x08000000, LENGTH = 128K - sram (rwx) : ORIGIN = 0x20000000, LENGTH = 20K -} - -OUTPUT_ARCH(arm) -EXTERN(_vectors) -ENTRY(_stext) -SECTIONS -{ - .text : { - _stext = ABSOLUTE(.); - *(.vectors) - *(.text .text.*) - *(.fixup) - *(.gnu.warning) - *(.rodata .rodata.*) - *(.gnu.linkonce.t.*) - *(.glue_7) - *(.glue_7t) - *(.got) - *(.gcc_except_table) - *(.gnu.linkonce.r.*) - _etext = ABSOLUTE(.); - } > flash - - .init_section : ALIGN(4) { - _sinit = ABSOLUTE(.); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) - KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) - _einit = ABSOLUTE(.); - } > flash - - .ARM.extab : ALIGN(4) { - *(.ARM.extab*) - } > flash - - .ARM.exidx : ALIGN(4) { - __exidx_start = ABSOLUTE(.); - *(.ARM.exidx*) - __exidx_end = ABSOLUTE(.); - } > flash - - .tdata : { - _stdata = ABSOLUTE(.); - *(.tdata .tdata.* .gnu.linkonce.td.*); - _etdata = ABSOLUTE(.); - } > flash - - .tbss : { - _stbss = ABSOLUTE(.); - *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); - _etbss = ABSOLUTE(.); - } > flash - - _eronly = ABSOLUTE(.); - - /* The RAM vector table (if present) should lie at the beginning of SRAM */ - - .ram_vectors : { - *(.ram_vectors) - } > sram - - .data : ALIGN(4) { - _sdata = ABSOLUTE(.); - *(.data .data.*) - *(.gnu.linkonce.d.*) - CONSTRUCTORS - . = ALIGN(4); - _edata = ABSOLUTE(.); - } > sram AT > flash - - .bss : ALIGN(4) { - _sbss = ABSOLUTE(.); - *(.bss .bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - . = ALIGN(4); - _ebss = ABSOLUTE(.); - } > sram - - /* Stabs debugging sections. */ - - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_info 0 : { *(.debug_info) } - .debug_line 0 : { *(.debug_line) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_aranges 0 : { *(.debug_aranges) } -} diff --git a/boards/arm/stm32/nucleo-f103rb/src/CMakeLists.txt b/boards/arm/stm32/nucleo-f103rb/src/CMakeLists.txt deleted file mode 100644 index 513418e9419d8..0000000000000 --- a/boards/arm/stm32/nucleo-f103rb/src/CMakeLists.txt +++ /dev/null @@ -1,51 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/nucleo-f103rb/src/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -set(SRCS stm32_boot.c stm32_bringup.c) - -if(CONFIG_ARCH_LEDS) - list(APPEND SRCS stm32_autoleds.c) -else() - list(APPEND SRCS stm32_userleds.c) -endif() - -if(CONFIG_ARCH_BUTTONS) - list(APPEND SRCS stm32_buttons.c) -endif() - -if(NOT CONFIG_STM32_FOC) - if(CONFIG_ADC) - list(APPEND SRCS stm32_adc.c) - endif() - - if(CONFIG_PWM) - list(APPEND SRCS stm32_pwm.c) - endif() -endif() - -if(CONFIG_BOARD_STM32_IHM07M1) - list(APPEND SRCS stm32_foc_ihm07m1.c) -endif() - -target_sources(board PRIVATE ${SRCS}) - -set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/ld.script") diff --git a/boards/arm/stm32/nucleo-f103rb/src/Make.defs b/boards/arm/stm32/nucleo-f103rb/src/Make.defs deleted file mode 100644 index fa7a6e9872078..0000000000000 --- a/boards/arm/stm32/nucleo-f103rb/src/Make.defs +++ /dev/null @@ -1,53 +0,0 @@ -############################################################################ -# boards/arm/stm32/nucleo-f103rb/src/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/Make.defs - -CSRCS = stm32_boot.c stm32_bringup.c - -ifeq ($(CONFIG_ARCH_LEDS),y) -CSRCS += stm32_autoleds.c -else -CSRCS += stm32_userleds.c -endif - -ifeq ($(CONFIG_ARCH_BUTTONS),y) -CSRCS += stm32_buttons.c -endif - -ifneq ($(CONFIG_STM32_FOC),y) -ifeq ($(CONFIG_ADC),y) -CSRCS += stm32_adc.c -endif - -ifeq ($(CONFIG_PWM),y) -CSRCS += stm32_pwm.c -endif -endif - -ifeq ($(CONFIG_BOARD_STM32_IHM07M1),y) -CSRCS += stm32_foc_ihm07m1.c -endif - -DEPPATH += --dep-path board -VPATH += :board -CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/nucleo-f103rb/src/stm32_adc.c b/boards/arm/stm32/nucleo-f103rb/src/stm32_adc.c deleted file mode 100644 index e3f6006eabc90..0000000000000 --- a/boards/arm/stm32/nucleo-f103rb/src/stm32_adc.c +++ /dev/null @@ -1,242 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f103rb/src/stm32_adc.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include "stm32.h" - -#if defined(CONFIG_ADC) && (defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2)) - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -/* 1 or 2 ADC devices (DEV1, DEV2) */ - -#if defined(CONFIG_STM32_ADC1) -# define DEV1_PORT 1 -#endif - -#if defined(CONFIG_STM32_ADC2) -# if defined(DEV1_PORT) -# define DEV2_PORT 2 -# else -# define DEV1_PORT 2 -# endif -#endif - -/* The number of ADC channels in the conversion list */ - -/* TODO DMA */ - -#define ADC1_NCHANNELS 3 -#define ADC2_NCHANNELS 3 - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* DEV 1 */ - -#if DEV1_PORT == 1 - -#define DEV1_NCHANNELS ADC1_NCHANNELS - -/* Identifying number of each ADC channel (even if NCHANNELS is less) */ - -static const uint8_t g_chanlist1[3] = -{ - 0, - 1, - 4 -}; - -/* Configurations of pins used by each ADC channel */ - -static const uint32_t g_pinlist1[3] = -{ - GPIO_ADC123_IN0_0, /* PA0/A0 */ - GPIO_ADC123_IN1_0, /* PA1/A1 */ - GPIO_ADC12_IN4_0, /* PA4/A2 */ -}; - -#elif DEV1_PORT == 2 - -#define DEV1_NCHANNELS ADC2_NCHANNELS - -/* Identifying number of each ADC channel */ - -static const uint8_t g_chanlist1[3] = -{ - 8, - 11, - 10 -}; - -/* Configurations of pins used by each ADC channel */ - -static const uint32_t g_pinlist1[3] = -{ - GPIO_ADC12_IN8_0, /* PB0/A3 */ - GPIO_ADC123_IN11_0, /* PC1/A4 */ - GPIO_ADC123_IN10_0, /* PC0/A5 */ -}; - -#endif /* DEV1_PORT == 1 */ - -#ifdef DEV2_PORT - -/* DEV 2 */ - -#if DEV2_PORT == 2 - -#define DEV2_NCHANNELS ADC2_NCHANNELS - -/* Identifying number of each ADC channel */ - -static const uint8_t g_chanlist2[3] = -{ - 8, - 11, - 10 -}; - -/* Configurations of pins used by each ADC channel */ - -static const uint32_t g_pinlist2[3] = -{ - GPIO_ADC12_IN8_0, /* PB0/A3 */ - GPIO_ADC123_IN11_0, /* PC1/A4 */ - GPIO_ADC123_IN10_0, /* PC0/A5 */ -}; - -#endif /* DEV2_PORT == 2 */ -#endif /* DEV2_PORT */ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_adc_setup - * - * Description: - * Initialize ADC and register the ADC driver. - * - ****************************************************************************/ - -int stm32_adc_setup(void) -{ - static bool initialized = false; - struct adc_dev_s *adc; - int ret; - int i; - - /* Check if we have already initialized */ - - if (!initialized) - { - /* DEV1 */ - - /* Configure the pins as analog inputs for the selected channels */ - - for (i = 0; i < DEV1_NCHANNELS; i++) - { - stm32_configgpio(g_pinlist1[i]); - } - - /* Call stm32_adcinitialize() to get an instance of the ADC interface */ - - adc = stm32_adcinitialize(DEV1_PORT, g_chanlist1, DEV1_NCHANNELS); - if (adc == NULL) - { - aerr("ERROR: Failed to get ADC interface 1\n"); - return -ENODEV; - } - - /* Register the ADC driver at "/dev/adc0" */ - - ret = adc_register("/dev/adc0", adc); - if (ret < 0) - { - aerr("ERROR: adc_register /dev/adc0 failed: %d\n", ret); - return ret; - } - -#ifdef DEV2_PORT - - /* DEV2 */ - - /* Configure the pins as analog inputs for the selected channels */ - - for (i = 0; i < DEV2_NCHANNELS; i++) - { - stm32_configgpio(g_pinlist2[i]); - } - - /* Call stm32_adcinitialize() to get an instance of the ADC interface */ - - adc = stm32_adcinitialize(DEV2_PORT, g_chanlist2, DEV2_NCHANNELS); - if (adc == NULL) - { - aerr("ERROR: Failed to get ADC interface 2\n"); - return -ENODEV; - } - - /* Register the ADC driver at "/dev/adc1" */ - - ret = adc_register("/dev/adc1", adc); - if (ret < 0) - { - aerr("ERROR: adc_register /dev/adc1 failed: %d\n", ret); - return ret; - } -#endif - - initialized = true; - } - - return OK; -} - -#endif /* CONFIG_ADC && (CONFIG_STM32_ADC1 || CONFIG_STM32_ADC2) */ diff --git a/boards/arm/stm32/nucleo-f103rb/src/stm32_autoleds.c b/boards/arm/stm32/nucleo-f103rb/src/stm32_autoleds.c deleted file mode 100644 index 891d76833e2ce..0000000000000 --- a/boards/arm/stm32/nucleo-f103rb/src/stm32_autoleds.c +++ /dev/null @@ -1,80 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f103rb/src/stm32_autoleds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include "stm32.h" -#include "nucleo-f103rb.h" - -#ifdef CONFIG_ARCH_LEDS - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_autoled_initialize - ****************************************************************************/ - -void board_autoled_initialize(void) -{ - /* Configure LED1 GPIO for output */ - - stm32_configgpio(GPIO_LED1); -} - -/**************************************************************************** - * Name: board_autoled_on - ****************************************************************************/ - -void board_autoled_on(int led) -{ - if (led == BOARD_LED1) - { - stm32_gpiowrite(GPIO_LED1, true); - } -} - -/**************************************************************************** - * Name: board_autoled_off - ****************************************************************************/ - -void board_autoled_off(int led) -{ - if (led == BOARD_LED1) - { - stm32_gpiowrite(GPIO_LED1, false); - } -} - -#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/nucleo-f103rb/src/stm32_boot.c b/boards/arm/stm32/nucleo-f103rb/src/stm32_boot.c deleted file mode 100644 index b2362627a32ec..0000000000000 --- a/boards/arm/stm32/nucleo-f103rb/src/stm32_boot.c +++ /dev/null @@ -1,95 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f103rb/src/stm32_boot.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include "nucleo-f103rb.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_boardinitialize - * - * Description: - * All STM32 architectures must provide the following entry point. This - * entry point is called early in the initialization -- after all memory - * has been configured and mapped but before any devices have been - * initialized. - * - ****************************************************************************/ - -void stm32_boardinitialize(void) -{ - /* Configure on-board LEDs if LED support has been selected. */ - -#ifdef CONFIG_ARCH_LEDS - board_autoled_initialize(); -#endif -} - -/**************************************************************************** - * Name: board_late_initialize - * - * Description: - * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional - * initialization call will be performed in the boot-up sequence to a - * function called board_late_initialize(). board_late_initialize() will - * be called immediately after up_initialize() is called and just before - * the initial application is started. This additional initialization - * phase may be used, for example, to initialize board-specific device - * drivers. - * - ****************************************************************************/ - -#ifdef CONFIG_BOARD_LATE_INITIALIZE -void board_late_initialize(void) -{ - /* Perform board-specific initialization */ - - stm32_bringup(); -} -#endif diff --git a/boards/arm/stm32/nucleo-f103rb/src/stm32_bringup.c b/boards/arm/stm32/nucleo-f103rb/src/stm32_bringup.c deleted file mode 100644 index 8ea6ec5e144dc..0000000000000 --- a/boards/arm/stm32/nucleo-f103rb/src/stm32_bringup.c +++ /dev/null @@ -1,143 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f103rb/src/stm32_bringup.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include - -#ifdef CONFIG_USERLED -# include -#endif - -#ifdef CONFIG_INPUT_BUTTONS -# include -#endif - -#ifdef CONFIG_SENSORS_QENCODER -# include "board_qencoder.h" -#endif - -#include "nucleo-f103rb.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#undef HAVE_LEDS - -#if !defined(CONFIG_ARCH_LEDS) && defined(CONFIG_USERLED_LOWER) -# define HAVE_LEDS 1 -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_bringup - * - * Description: - * Perform architecture-specific initialization - * - * CONFIG_BOARD_LATE_INITIALIZE=y : - * Called from board_late_initialize(). - * - ****************************************************************************/ - -int stm32_bringup(void) -{ - int ret; - -#ifdef CONFIG_INPUT_BUTTONS - /* Register the BUTTON driver */ - - ret = btn_lower_initialize("/dev/buttons"); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: btn_lower_initialize() failed: %d\n", ret); - } -#endif - -#ifdef HAVE_LEDS - /* Register the LED driver */ - - ret = userled_lower_initialize(LED_DRIVER_PATH); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: userled_lower_initialize() failed: %d\n", ret); - return ret; - } -#endif - -#ifdef CONFIG_PWM - /* Initialize PWM and register the PWM device. */ - - ret = stm32_pwm_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_pwm_setup() failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_STM32_FOC - /* Initialize and register the FOC device */ - - ret = stm32_foc_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_foc_setup failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_ADC - /* Initialize ADC and register the ADC driver. */ - - ret = stm32_adc_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_adc_setup failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_SENSORS_QENCODER - /* Initialize and register the qencoder driver */ - - ret = board_qencoder_initialize(0, CONFIG_NUCLEO_F103RB_QETIMER); - if (ret != OK) - { - syslog(LOG_ERR, - "ERROR: Failed to register the qencoder: %d\n", - ret); - return ret; - } -#endif - - UNUSED(ret); - return OK; -} diff --git a/boards/arm/stm32/nucleo-f103rb/src/stm32_buttons.c b/boards/arm/stm32/nucleo-f103rb/src/stm32_buttons.c deleted file mode 100644 index 5631fb1246a2d..0000000000000 --- a/boards/arm/stm32/nucleo-f103rb/src/stm32_buttons.c +++ /dev/null @@ -1,113 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f103rb/src/stm32_buttons.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include "stm32.h" -#include "nucleo-f103rb.h" - -#ifdef CONFIG_ARCH_BUTTONS - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_button_initialize - * - * Description: - * board_button_initialize() must be called to initialize button - * resources. After that, board_buttons() may be called to collect the - * current state of all buttons or board_button_irq() may be called to - * register button interrupt handlers. - * - ****************************************************************************/ - -uint32_t board_button_initialize(void) -{ - /* Configure the single button as an input. NOTE that EXTI interrupts are - * also configured for the pin. - */ - - stm32_configgpio(GPIO_BTN_USER); - return NUM_BUTTONS; -} - -/**************************************************************************** - * Name: board_buttons - * - * Description: - * After board_button_initialize() has been called, board_buttons() may be - * called to collect the state of all buttons. board_buttons() returns an - * 32-bit unsigned integer with each bit associated with a button. See the - * BUTTON_*_BIT definitions in board.h for the meaning of each bit. - * - ****************************************************************************/ - -uint32_t board_buttons(void) -{ - /* Check the state of the USER button. A LOW value means that the key is - * pressed. - */ - - return stm32_gpioread(GPIO_BTN_USER) ? 0 : BUTTON_USER_BIT; -} - -/**************************************************************************** - * Name: board_button_irq - * - * Description: - * board_button_irq() may be called to register an interrupt handler that - * will be called when a button is depressed or released. The ID value is - * a button enumeration value that uniquely identifies a button resource. - * See the BUTTON_* definitions in board.h for the meaning of the - * enumeration value. - * - ****************************************************************************/ - -#ifdef CONFIG_ARCH_IRQBUTTONS -int board_button_irq(int id, xcpt_t irqhandler, void *arg) -{ - int ret = -EINVAL; - - if (id == BUTTON_USER) - { - ret = stm32_gpiosetevent(GPIO_BTN_USER, true, true, true, irqhandler, - arg); - } - - return ret; -} -#endif - -#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/stm32/nucleo-f103rb/src/stm32_foc_ihm07m1.c b/boards/arm/stm32/nucleo-f103rb/src/stm32_foc_ihm07m1.c deleted file mode 100644 index f22035b78c4b6..0000000000000 --- a/boards/arm/stm32/nucleo-f103rb/src/stm32_foc_ihm07m1.c +++ /dev/null @@ -1,185 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f103rb/src/stm32_foc_ihm07m1.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "stm32_ihm07m1.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#define CURRENT_SAMPLE_TIME ADC_SMPR_28p5 -#define VBUS_SAMPLE_TIME ADC_SMPR_239p5 -#define POT_SAMPLE_TIME ADC_SMPR_239p5 - -/* ADC1 channels used in this example */ - -#define ADC1_INJECTED (CONFIG_MOTOR_FOC_SHUNTS) - -#ifdef CONFIG_BOARD_STM32_IHM07M1_VBUS -# define IHM07M1_VBUS 1 -#else -# define IHM07M1_VBUS 0 -#endif - -#ifdef CONFIG_BOARD_STM32_IHM07M1_POT -# define IHM07M1_POT 1 -#else -# define IHM07M1_POT 0 -#endif - -#define ADC1_REGULAR (IHM07M1_VBUS + IHM07M1_POT) -#define ADC1_NCHANNELS (ADC1_INJECTED + ADC1_REGULAR) - -/* Check ADC1 configuration */ - -#if ADC1_INJECTED != CONFIG_STM32_ADC1_INJECTED_CHAN -# error -#endif - -/* TIM1 configuration */ - -#ifndef CONFIG_STM32_TIM1_PARTIAL_REMAP -# error -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* FOC ADC configuration: - * - Current Phase V -> ADC1 INJ1 -> ADC1_IN0 (PA0) - * - Current Phase U -> ADC1 INJ2 -> ADC1_IN11 (PC1) - * - Current Phase W -> ADC1 INJ3 -> ADC1_I10 (PC0) - * optional: - * - VBUS -> ADC1 REG -> ADC1_IN1 (PA1) - * - POT -> ADC1 REG -> ADC1_IN9 (PB1) - * - * TIM1 PWM configuration: - * - Phase U high -> TIM1_CH1 (PA8) - * - Phase V high -> TIM1_CH2 (PA9) - * - Phase W high -> TIM1_CH3 (PA10) - * - */ - -static uint8_t g_adc1_chan[] = -{ -#ifdef CONFIG_BOARD_STM32_IHM07M1_VBUS - 1, /* ADC1 REG - VBUS */ -#endif -#ifdef CONFIG_BOARD_STM32_IHM07M1_POT - 9, /* ADC1 REG - POT */ -#endif - 0, /* ADC1 INJ1 - PHASE 1 */ -#if CONFIG_MOTOR_FOC_SHUNTS == 3 - 11, /* ADC1 INJ2 - PHASE 2 */ - 10, /* ADC1 INJ3 - PHASE 3 */ -#endif -}; - -static uint32_t g_adc1_pins[] = -{ -#ifdef CONFIG_BOARD_STM32_IHM07M1_VBUS - GPIO_ADC123_IN1_0, -#endif -#ifdef CONFIG_BOARD_STM32_IHM07M1_POT - GPIO_ADC12_IN9_0, -#endif - GPIO_ADC123_IN0_0, -#if CONFIG_MOTOR_FOC_SHUNTS > 1 - GPIO_ADC123_IN11_0, -#endif -#if CONFIG_MOTOR_FOC_SHUNTS > 2 - GPIO_ADC123_IN10_0, -#endif -}; - -/* ADC1 sample time configuration */ - -static adc_channel_t g_adc1_stime[] = -{ -#ifdef CONFIG_BOARD_STM32_IHM07M1_VBUS - { - .channel = 2, - .sample_time = VBUS_SAMPLE_TIME - }, -#endif -#ifdef CONFIG_BOARD_STM32_IHM07M1_POT - { - .channel = 12, - .sample_time = POT_SAMPLE_TIME - }, -#endif - { - .channel = 1, - .sample_time = CURRENT_SAMPLE_TIME - }, -#if CONFIG_MOTOR_FOC_SHUNTS > 1 - { - .channel = 7, - .sample_time = CURRENT_SAMPLE_TIME - }, -#endif -#if CONFIG_MOTOR_FOC_SHUNTS > 2 - { - .channel = 6, - .sample_time = CURRENT_SAMPLE_TIME - }, -#endif -}; - -/* Board specific ADC configuration for FOC */ - -static struct stm32_foc_adc_s g_adc_cfg = -{ - .chan = g_adc1_chan, - .pins = g_adc1_pins, - .stime = g_adc1_stime, - .nchan = ADC1_NCHANNELS, - .regch = ADC1_REGULAR, - .intf = 1 -}; - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_foc_setup - * - * Description: - * Initialize FOC driver. - * - * Returned Value: - * 0 on success, a negated errno value on failure - * - ****************************************************************************/ - -int stm32_foc_setup(void) -{ - return board_ihm07m1_initialize(&g_adc_cfg); -} diff --git a/boards/arm/stm32/nucleo-f103rb/src/stm32_pwm.c b/boards/arm/stm32/nucleo-f103rb/src/stm32_pwm.c deleted file mode 100644 index e17931280d112..0000000000000 --- a/boards/arm/stm32/nucleo-f103rb/src/stm32_pwm.c +++ /dev/null @@ -1,110 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f103rb/src/stm32_pwm.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32_pwm.h" -#include "nucleo-f103rb.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -#define HAVE_PWM 1 - -#ifndef CONFIG_PWM -# undef HAVE_PWM -#endif - -#ifndef CONFIG_STM32_TIM1 -# undef HAVE_PWM -#endif - -#ifndef CONFIG_STM32_TIM1_PWM -# undef HAVE_PWM -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_pwm_setup - * - * Description: - * Initialize PWM and register the PWM device. - * - ****************************************************************************/ - -int stm32_pwm_setup(void) -{ -#ifdef HAVE_PWM - static bool initialized = false; - struct pwm_lowerhalf_s *pwm; - int ret; - - /* Have we already initialized? */ - - if (!initialized) - { - /* Call stm32_pwminitialize() to get an instance of the PWM interface */ - - pwm = stm32_pwminitialize(NUCLEOF103RB_PWMTIMER); - if (!pwm) - { - tmrerr("ERROR: Failed to get the STM32 PWM lower half\n"); - return -ENODEV; - } - - /* Register the PWM driver at "/dev/pwm0" */ - - ret = pwm_register("/dev/pwm0", pwm); - if (ret < 0) - { - tmrerr("ERROR: pwm_register failed: %d\n", ret); - return ret; - } - - /* Now we are initialized */ - - initialized = true; - } - - return OK; -#else - return -ENODEV; -#endif -} diff --git a/boards/arm/stm32/nucleo-f103rb/src/stm32_userleds.c b/boards/arm/stm32/nucleo-f103rb/src/stm32_userleds.c deleted file mode 100644 index cb23d594b1149..0000000000000 --- a/boards/arm/stm32/nucleo-f103rb/src/stm32_userleds.c +++ /dev/null @@ -1,77 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f103rb/src/stm32_userleds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include - -#include "stm32.h" -#include "nucleo-f103rb.h" - -#ifndef CONFIG_ARCH_LEDS - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_userled_initialize - ****************************************************************************/ - -uint32_t board_userled_initialize(void) -{ - /* Configure LED1 GPIO for output */ - - stm32_configgpio(GPIO_LED1); - return BOARD_NLEDS; -} - -/**************************************************************************** - * Name: board_userled - ****************************************************************************/ - -void board_userled(int led, bool ledon) -{ - if (led == BOARD_LED1) - { - stm32_gpiowrite(GPIO_LED1, ledon); - } -} - -/**************************************************************************** - * Name: board_userled_all - ****************************************************************************/ - -void board_userled_all(uint32_t ledset) -{ - stm32_gpiowrite(GPIO_LED1, (ledset & BOARD_LED1_BIT) != 0); -} - -#endif /* !CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/nucleo-f207zg/CMakeLists.txt b/boards/arm/stm32/nucleo-f207zg/CMakeLists.txt deleted file mode 100644 index 9fe17612d1738..0000000000000 --- a/boards/arm/stm32/nucleo-f207zg/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/nucleo-f207zg/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32/nucleo-f207zg/configs/adc/defconfig b/boards/arm/stm32/nucleo-f207zg/configs/adc/defconfig deleted file mode 100644 index 2615e630e80d0..0000000000000 --- a/boards/arm/stm32/nucleo-f207zg/configs/adc/defconfig +++ /dev/null @@ -1,47 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -CONFIG_ADC=y -CONFIG_ADC_FIFOSIZE=4 -CONFIG_ANALOG=y -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="nucleo-f207zg" -CONFIG_ARCH_BOARD_NUCLEO_F207ZG=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F207ZG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=6522 -CONFIG_BUILTIN=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_EXAMPLES_ADC=y -CONFIG_EXAMPLES_ADC_GROUPSIZE=3 -CONFIG_IDLETHREAD_STACKSIZE=2048 -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_MM_REGIONS=2 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=27 -CONFIG_START_YEAR=2013 -CONFIG_STM32_ADC1=y -CONFIG_STM32_ADC1_DMA=y -CONFIG_STM32_ADC3=y -CONFIG_STM32_DMA2=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_TIM1=y -CONFIG_STM32_TIM1_ADC=y -CONFIG_STM32_USART3=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART3_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/nucleo-f207zg/configs/nsh/defconfig b/boards/arm/stm32/nucleo-f207zg/configs/nsh/defconfig deleted file mode 100644 index 855e4c155bb5d..0000000000000 --- a/boards/arm/stm32/nucleo-f207zg/configs/nsh/defconfig +++ /dev/null @@ -1,37 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="nucleo-f207zg" -CONFIG_ARCH_BOARD_NUCLEO_F207ZG=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F207ZG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=6522 -CONFIG_BUILTIN=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_EXAMPLES_HELLO=y -CONFIG_IDLETHREAD_STACKSIZE=2048 -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_MM_REGIONS=2 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=27 -CONFIG_START_YEAR=2013 -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_USART3=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART3_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/nucleo-f207zg/configs/pwm/defconfig b/boards/arm/stm32/nucleo-f207zg/configs/pwm/defconfig deleted file mode 100644 index 03abe05bec910..0000000000000 --- a/boards/arm/stm32/nucleo-f207zg/configs/pwm/defconfig +++ /dev/null @@ -1,41 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="nucleo-f207zg" -CONFIG_ARCH_BOARD_NUCLEO_F207ZG=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F207ZG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=6522 -CONFIG_BUILTIN=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_EXAMPLES_PWM=y -CONFIG_IDLETHREAD_STACKSIZE=2048 -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_MM_REGIONS=2 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_PWM=y -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=27 -CONFIG_START_YEAR=2013 -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_TIM1=y -CONFIG_STM32_TIM1_CH1OUT=y -CONFIG_STM32_TIM1_PWM=y -CONFIG_STM32_USART3=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART3_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/nucleo-f207zg/include/board.h b/boards/arm/stm32/nucleo-f207zg/include/board.h deleted file mode 100644 index bf2ce642c59d5..0000000000000 --- a/boards/arm/stm32/nucleo-f207zg/include/board.h +++ /dev/null @@ -1,209 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f207zg/include/board.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __BOARDS_ARM_STM32_NUCLEO_F207ZG_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32_NUCLEO_F207ZG_INCLUDE_BOARD_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#ifndef __ASSEMBLY__ -# include -# include -#endif - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Clocking *****************************************************************/ - -/* HSI - 16 MHz RC factory-trimmed - * LSI - 32 KHz RC - * HSE - 8 MHz from MCO output of ST-LINK - * LSE - 32.768 kHz - */ - -#define STM32_BOARD_XTAL 8000000ul - -#define STM32_HSI_FREQUENCY 16000000ul -#define STM32_LSI_FREQUENCY 32000 -#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL -#define STM32_LSE_FREQUENCY 32768 /* X2 on board */ - -/* Main PLL Configuration. - * - * Formulae: - * - * VCO input frequency = - * PLL input clock frequency / PLLM, 2 <= PLLM <= 63 - * VCO output frequency = - * VCO input frequency × PLLN, 50 <= PLLN <= 432 - * PLL output clock frequency = - * VCO frequency / PLLP, PLLP = 2, 4, 6, or 8 - * USB OTG FS clock frequency = - * VCO frequency / PLLQ, 2 <= PLLQ <= 15 - * - * We will configure like this - * - * PLL source is HSE - * PLL_VCO = (STM32_HSE_FREQUENCY / PLLM) * PLLN - * = (8,000,000 / 2) * 100 - * = 400,000,000 - * SYSCLK = PLL_VCO / PLLP - * = 400,000,000 / 4 = 100,000,000 - * RNG Clock - * = PLL_VCO / PLLQ - * = 400,000,000 / 8 = 50,000,000 - * - */ - -#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(2) -#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(100) -#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_4 -#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(8) - -#define STM32_SYSCLK_FREQUENCY 100000000ul - -/* AHB clock (HCLK) is SYSCLK (100MHz) */ - -#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ -#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY - -/* APB1 clock (PCLK1) is HCLK/2 (25MHz) */ - -#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd4 /* PCLK1 = HCLK / 4 */ -#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/4) - -/* APB2 clock (PCLK2) is HCLK/2 (50MHz) */ - -#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 2 */ -#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/2) - -/* Timers driven from APB2 will be twice PCLK2 (100Mhz) */ - -#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM9_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM10_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM11_CLKIN (2*STM32_PCLK2_FREQUENCY) - -/* Timers driven from APB1 will be twice PCLK1 (50MHz) */ - -#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) - -/* LED definitions **********************************************************/ - -/* The Nucleo-144 board has numerous LEDs but only three, LD1 a Green LED, - * LD2 a Blue LED and LD3 a Red LED, that can be controlled by software. - * The following definitions assume the default Solder Bridges are installed. - * - * If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs - * in any way. - * The following definitions are used to access individual LEDs. - */ - -/* LED index values for use with board_userled() */ - -#define BOARD_LED1 0 -#define BOARD_LED2 1 -#define BOARD_LED3 2 -#define BOARD_NLEDS 3 - -#define BOARD_LED_GREEN BOARD_LED1 -#define BOARD_LED_BLUE BOARD_LED2 -#define BOARD_LED_RED BOARD_LED3 - -/* LED bits for use with board_userled_all() */ - -#define BOARD_LED1_BIT (1 << BOARD_LED1) -#define BOARD_LED2_BIT (1 << BOARD_LED2) -#define BOARD_LED3_BIT (1 << BOARD_LED3) - -/* If CONFIG_ARCH_LEDS is defined, the usage by the board port is defined in - * include/board.h and src/stm32_leds.c. The LEDs are used to encode - * OS-related events as follows: - * - * - * SYMBOL Meaning LED state - * Red Green Blue - * ---------------------- -------------------------- ------ ------ ---- - */ - -#define LED_STARTED 0 /* NuttX has been started OFF OFF OFF */ -#define LED_HEAPALLOCATE 1 /* Heap has been allocated OFF OFF ON */ -#define LED_IRQSENABLED 2 /* Interrupts enabled OFF ON OFF */ -#define LED_STACKCREATED 3 /* Idle stack created OFF ON ON */ -#define LED_INIRQ 4 /* In an interrupt N/C N/C GLOW */ -#define LED_SIGNAL 5 /* In a signal handler N/C GLOW N/C */ -#define LED_ASSERTION 6 /* An assertion failed GLOW N/C GLOW */ -#define LED_PANIC 7 /* The system has crashed Blink OFF N/C */ -#define LED_IDLE 8 /* MCU is in sleep mode ON OFF OFF */ - -/* Button definitions *******************************************************/ - -/* The NUCLEO board supports one button: Pushbutton B1, labeled "User", is - * connected to GPIO PC13. A high value will be sensed when the button is - * depressed. - */ - -#define BUTTON_USER 0 -#define NUM_BUTTONS 1 - -#define BUTTON_USER_BIT (1 << BUTTON_USER) - -/* Alternate function pin selections ****************************************/ - -/* USART3 (Nucleo Virtual Console) */ - -#define GPIO_USART3_RX (GPIO_USART3_RX_3|GPIO_SPEED_100MHz) /* PD9 */ -#define GPIO_USART3_TX (GPIO_USART3_TX_3|GPIO_SPEED_100MHz) /* PD8 */ - -/* PWM configuration ********************************************************/ - -/* TIM1 PWM */ - -#define GPIO_TIM1_CH1OUT (GPIO_TIM1_CH1OUT_2|GPIO_SPEED_50MHz) /* PE9 */ -#define GPIO_TIM1_CH1NOUT GPIO_TIM1_CH1N_3 /* PE8 */ -#define GPIO_TIM1_CH2OUT (GPIO_TIM1_CH2OUT_2|GPIO_SPEED_50MHz) /* PE11 */ -#define GPIO_TIM1_CH2NOUT GPIO_TIM1_CH2N_3 /* PE10 */ -#define GPIO_TIM1_CH3OUT (GPIO_TIM1_CH3OUT_2|GPIO_SPEED_50MHz) /* PE13 */ -#define GPIO_TIM1_CH3NOUT GPIO_TIM1_CH3N_3 /* PE12 */ - -/* DMA channels *************************************************************/ - -/* ADC */ - -#define ADC1_DMA_CHAN DMAMAP_ADC1_1 - -#endif /* __BOARDS_ARM_STM32_NUCLEO_F207ZG_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32/nucleo-f207zg/scripts/Make.defs b/boards/arm/stm32/nucleo-f207zg/scripts/Make.defs deleted file mode 100644 index a0ae3c3954b6f..0000000000000 --- a/boards/arm/stm32/nucleo-f207zg/scripts/Make.defs +++ /dev/null @@ -1,41 +0,0 @@ -############################################################################ -# boards/arm/stm32/nucleo-f207zg/scripts/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/.config -include $(TOPDIR)/tools/Config.mk -include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs - -LDSCRIPT = ld.script -ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) - -ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 - -CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) -CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) -CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -AFLAGS := $(CFLAGS) -D__ASSEMBLY__ - -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections -LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32/nucleo-f207zg/scripts/ld.script b/boards/arm/stm32/nucleo-f207zg/scripts/ld.script deleted file mode 100644 index 0f8ef1906b016..0000000000000 --- a/boards/arm/stm32/nucleo-f207zg/scripts/ld.script +++ /dev/null @@ -1,124 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f207zg/scripts/ld.script - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* The STM32F207ZG has 1Mb of FLASH beginning at address 0x0800:0000, - * 128Kb of SRAM. SRAM is split up into two blocks: - * - * 1) 112Kb of SRAM beginning at address 0x2000:0000 - * 2) 16Kb of SRAM beginning at address 0x2001:c000 - * - * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 - * where the code expects to begin execution by jumping to the entry point in - * the 0x0800:0000 address range. - */ - -MEMORY -{ - flash (rx) : ORIGIN = 0x08000000, LENGTH = 1M - sram (rwx) : ORIGIN = 0x20000000, LENGTH = 112K -} - -OUTPUT_ARCH(arm) -EXTERN(_vectors) -ENTRY(_stext) -SECTIONS -{ - .text : { - _stext = ABSOLUTE(.); - *(.vectors) - *(.text .text.*) - *(.fixup) - *(.gnu.warning) - *(.rodata .rodata.*) - *(.gnu.linkonce.t.*) - *(.glue_7) - *(.glue_7t) - *(.got) - *(.gcc_except_table) - *(.gnu.linkonce.r.*) - _etext = ABSOLUTE(.); - } > flash - - .init_section : ALIGN(4) { - _sinit = ABSOLUTE(.); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) - KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) - _einit = ABSOLUTE(.); - } > flash - - .ARM.extab : ALIGN(4) { - *(.ARM.extab*) - } > flash - - .ARM.exidx : ALIGN(4) { - __exidx_start = ABSOLUTE(.); - *(.ARM.exidx*) - __exidx_end = ABSOLUTE(.); - } > flash - - .tdata : { - _stdata = ABSOLUTE(.); - *(.tdata .tdata.* .gnu.linkonce.td.*); - _etdata = ABSOLUTE(.); - } > flash - - .tbss : { - _stbss = ABSOLUTE(.); - *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); - _etbss = ABSOLUTE(.); - } > flash - - _eronly = ABSOLUTE(.); - - .data : ALIGN(4) { - _sdata = ABSOLUTE(.); - *(.data .data.*) - *(.gnu.linkonce.d.*) - CONSTRUCTORS - . = ALIGN(4); - _edata = ABSOLUTE(.); - } > sram AT > flash - - .bss : ALIGN(4) { - _sbss = ABSOLUTE(.); - *(.bss .bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - . = ALIGN(4); - _ebss = ABSOLUTE(.); - } > sram - - /* Stabs debugging sections. */ - - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_info 0 : { *(.debug_info) } - .debug_line 0 : { *(.debug_line) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_aranges 0 : { *(.debug_aranges) } -} diff --git a/boards/arm/stm32/nucleo-f207zg/src/CMakeLists.txt b/boards/arm/stm32/nucleo-f207zg/src/CMakeLists.txt deleted file mode 100644 index 5ca78ff3da4ae..0000000000000 --- a/boards/arm/stm32/nucleo-f207zg/src/CMakeLists.txt +++ /dev/null @@ -1,49 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/nucleo-f207zg/src/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -set(SRCS stm32_boot.c stm32_bringup.c) - -if(CONFIG_ARCH_LEDS) - list(APPEND SRCS stm32_autoleds.c) -else() - list(APPEND SRCS stm32_userleds.c) -endif() - -if(CONFIG_ARCH_BUTTONS) - list(APPEND SRCS stm32_buttons.c) -endif() - -if(CONFIG_STM32_OTGFS) - list(APPEND SRCS stm32_usb.c) -endif() - -if(CONFIG_ADC) - list(APPEND SRCS stm32_adc.c) -endif() - -if(CONFIG_PWM) - list(APPEND SRCS stm32_pwm.c) -endif() - -target_sources(board PRIVATE ${SRCS}) - -set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/ld.script") diff --git a/boards/arm/stm32/nucleo-f207zg/src/Make.defs b/boards/arm/stm32/nucleo-f207zg/src/Make.defs deleted file mode 100644 index 3962a5368fde3..0000000000000 --- a/boards/arm/stm32/nucleo-f207zg/src/Make.defs +++ /dev/null @@ -1,51 +0,0 @@ -############################################################################ -# boards/arm/stm32/nucleo-f207zg/src/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/Make.defs - -CSRCS = stm32_boot.c stm32_bringup.c - -ifeq ($(CONFIG_ARCH_LEDS),y) -CSRCS += stm32_autoleds.c -else -CSRCS += stm32_userleds.c -endif - -ifeq ($(CONFIG_ARCH_BUTTONS),y) -CSRCS += stm32_buttons.c -endif - -ifeq ($(CONFIG_STM32_OTGFS),y) -CSRCS += stm32_usb.c -endif - -ifeq ($(CONFIG_ADC),y) -CSRCS += stm32_adc.c -endif - -ifeq ($(CONFIG_PWM),y) -CSRCS += stm32_pwm.c -endif - -DEPPATH += --dep-path board -VPATH += :board -CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/nucleo-f207zg/src/stm32_adc.c b/boards/arm/stm32/nucleo-f207zg/src/stm32_adc.c deleted file mode 100644 index 6a7e27ca6b7da..0000000000000 --- a/boards/arm/stm32/nucleo-f207zg/src/stm32_adc.c +++ /dev/null @@ -1,243 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f207zg/src/stm32_adc.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include "stm32.h" - -#if defined(CONFIG_ADC) && (defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC3)) - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -/* 1 or 2 ADC devices (DEV1, DEV2). - * ADC1 and ADC3 supported for now. - */ - -#if defined(CONFIG_STM32_ADC1) -# define DEV1_PORT 1 -#endif - -#if defined(CONFIG_STM32_ADC3) -# if defined(DEV1_PORT) -# define DEV2_PORT 3 -# else -# define DEV1_PORT 3 -# endif -#endif - -/* The number of ADC channels in the conversion list */ - -/* TODO DMA */ - -#define ADC1_NCHANNELS 3 -#define ADC3_NCHANNELS 3 - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* DEV 1 */ - -#if DEV1_PORT == 1 - -#define DEV1_NCHANNELS ADC1_NCHANNELS - -/* Identifying number of each ADC channel (even if NCHANNELS is less ) */ - -static const uint8_t g_chanlist1[3] = -{ - 3, - 10, - 13 -}; - -/* Configurations of pins used by each ADC channel */ - -static const uint32_t g_pinlist1[3] = -{ - GPIO_ADC1_IN3_0, /* PA3/A0 */ - GPIO_ADC1_IN10_0, /* PC0/A1 */ - GPIO_ADC1_IN13_0, /* PC3/A2 */ -}; - -#elif DEV1_PORT == 3 - -#define DEV1_NCHANNELS ADC3_NCHANNELS - -/* Identifying number of each ADC channel */ - -static const uint8_t g_chanlist1[3] = -{ - 9, - 15, - 8 -}; - -/* Configurations of pins used by each ADC channel */ - -static const uint32_t g_pinlist1[3] = -{ - GPIO_ADC3_IN9_0, /* PF3/A3 */ - GPIO_ADC3_IN15_0, /* PF5/A4 */ - GPIO_ADC3_IN8_0, /* PF10/A5 */ -}; - -#endif /* DEV1_PORT == 1 */ - -#ifdef DEV2_PORT - -/* DEV 2 */ - -#if DEV2_PORT == 3 - -#define DEV2_NCHANNELS ADC3_NCHANNELS - -/* Identifying number of each ADC channel */ - -static const uint8_t g_chanlist2[3] = -{ - 9, - 15, - 8 -}; - -/* Configurations of pins used by each ADC channel */ - -static const uint32_t g_pinlist2[3] = -{ - GPIO_ADC3_IN9_0, /* PF3/A3 */ - GPIO_ADC3_IN15_0, /* PF5/A4 */ - GPIO_ADC3_IN8_0, /* PF10/A5 */ -}; - -#endif /* DEV2_PORT == 3 */ -#endif /* DEV2_PORT */ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_adc_setup - * - * Description: - * Initialize ADC and register the ADC driver. - * - ****************************************************************************/ - -int stm32_adc_setup(void) -{ - static bool initialized = false; - struct adc_dev_s *adc; - int ret; - int i; - - /* Check if we have already initialized */ - - if (!initialized) - { - /* DEV1 */ - - /* Configure the pins as analog inputs for the selected channels */ - - for (i = 0; i < DEV1_NCHANNELS; i++) - { - stm32_configgpio(g_pinlist1[i]); - } - - /* Call stm32_adcinitialize() to get an instance of the ADC interface */ - - adc = stm32_adcinitialize(DEV1_PORT, g_chanlist1, DEV1_NCHANNELS); - if (adc == NULL) - { - aerr("ERROR: Failed to get ADC interface 1\n"); - return -ENODEV; - } - - /* Register the ADC driver at "/dev/adc0" */ - - ret = adc_register("/dev/adc0", adc); - if (ret < 0) - { - aerr("ERROR: adc_register /dev/adc0 failed: %d\n", ret); - return ret; - } - -#ifdef DEV2_PORT - /* DEV2 */ - - /* Configure the pins as analog inputs for the selected channels */ - - for (i = 0; i < DEV2_NCHANNELS; i++) - { - stm32_configgpio(g_pinlist2[i]); - } - - /* Call stm32_adcinitialize() to get an instance of the ADC interface */ - - adc = stm32_adcinitialize(DEV2_PORT, g_chanlist2, DEV2_NCHANNELS); - if (adc == NULL) - { - aerr("ERROR: Failed to get ADC interface 2\n"); - return -ENODEV; - } - - /* Register the ADC driver at "/dev/adc1" */ - - ret = adc_register("/dev/adc1", adc); - if (ret < 0) - { - aerr("ERROR: adc_register /dev/adc1 failed: %d\n", ret); - return ret; - } -#endif - - initialized = true; - } - - return OK; -} - -#endif /* CONFIG_ADC && (CONFIG_STM32_ADC1 || CONFIG_STM32_ADC3) */ diff --git a/boards/arm/stm32/nucleo-f207zg/src/stm32_autoleds.c b/boards/arm/stm32/nucleo-f207zg/src/stm32_autoleds.c deleted file mode 100644 index 9a1986701ba20..0000000000000 --- a/boards/arm/stm32/nucleo-f207zg/src/stm32_autoleds.c +++ /dev/null @@ -1,171 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f207zg/src/stm32_autoleds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include - -#include -#include - -#include "stm32_gpio.h" -#include "nucleo-f207zg.h" - -#ifdef CONFIG_ARCH_LEDS - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* Indexed by BOARD_LED_ */ - -static const uint32_t g_ledmap[BOARD_NLEDS] = -{ - GPIO_LED_GREEN, - GPIO_LED_BLUE, - GPIO_LED_RED, -}; - -static bool g_initialized; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -static void phy_set_led(int led, bool state) -{ - /* Active High */ - - stm32_gpiowrite(g_ledmap[led], state); -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_autoled_initialize - ****************************************************************************/ - -void board_autoled_initialize(void) -{ - int i; - - /* Configure the LD1 GPIO for output. Initial state is OFF */ - - for (i = 0; i < nitems(g_ledmap); i++) - { - stm32_configgpio(g_ledmap[i]); - } -} - -/**************************************************************************** - * Name: board_autoled_on - ****************************************************************************/ - -void board_autoled_on(int led) -{ - switch (led) - { - default: - break; - - case LED_HEAPALLOCATE: - phy_set_led(BOARD_LED_BLUE, true); - break; - - case LED_IRQSENABLED: - phy_set_led(BOARD_LED_BLUE, false); - phy_set_led(BOARD_LED_GREEN, true); - break; - - case LED_STACKCREATED: - phy_set_led(BOARD_LED_GREEN, true); - phy_set_led(BOARD_LED_BLUE, true); - g_initialized = true; - break; - - case LED_INIRQ: - phy_set_led(BOARD_LED_BLUE, true); - break; - - case LED_SIGNAL: - phy_set_led(BOARD_LED_GREEN, true); - break; - - case LED_ASSERTION: - phy_set_led(BOARD_LED_RED, true); - phy_set_led(BOARD_LED_BLUE, true); - break; - - case LED_PANIC: - phy_set_led(BOARD_LED_RED, true); - break; - - case LED_IDLE : /* IDLE */ - phy_set_led(BOARD_LED_RED, true); - break; - } -} - -/**************************************************************************** - * Name: board_autoled_off - ****************************************************************************/ - -void board_autoled_off(int led) -{ - switch (led) - { - default: - break; - - case LED_SIGNAL: - phy_set_led(BOARD_LED_GREEN, false); - break; - - case LED_INIRQ: - phy_set_led(BOARD_LED_BLUE, false); - break; - - case LED_ASSERTION: - phy_set_led(BOARD_LED_RED, false); - phy_set_led(BOARD_LED_BLUE, false); - break; - - case LED_PANIC: - phy_set_led(BOARD_LED_RED, false); - break; - - case LED_IDLE : /* IDLE */ - phy_set_led(BOARD_LED_RED, false); - break; - } -} - -#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/nucleo-f207zg/src/stm32_boot.c b/boards/arm/stm32/nucleo-f207zg/src/stm32_boot.c deleted file mode 100644 index 3f7ae0c33c105..0000000000000 --- a/boards/arm/stm32/nucleo-f207zg/src/stm32_boot.c +++ /dev/null @@ -1,87 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f207zg/src/stm32_boot.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include -#include - -#include "arm_internal.h" -#include "stm32_start.h" -#include "nucleo-f207zg.h" - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_boardinitialize - * - * Description: - * All STM32 architectures must provide the following entry point. - * This entry point is called early in the initialization -- after all - * memory has been configured and mapped but before any devices have been - * initialized. - * - ****************************************************************************/ - -void stm32_boardinitialize(void) -{ -#ifdef CONFIG_ARCH_LEDS - /* Configure on-board LEDs if LED support has been selected. */ - - board_autoled_initialize(); -#endif - -#if defined(CONFIG_STM32_OTGFS) || defined(CONFIG_STM32_HOST) - /* Initialize USB */ - - stm32_usbinitialize(); -#endif -} - -/**************************************************************************** - * Name: board_late_initialize - * - * Description: - * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional - * initialization call will be performed in the boot-up sequence to a - * function called board_late_initialize(). board_late_initialize() - * will be called immediately after up_initialize() is called and just - * before the initial application is started. - * This additional initialization phase may be used, for example, to - * initialize board-specific device drivers. - * - ****************************************************************************/ - -#ifdef CONFIG_BOARD_LATE_INITIALIZE -void board_late_initialize(void) -{ - stm32_bringup(); -} -#endif diff --git a/boards/arm/stm32/nucleo-f207zg/src/stm32_bringup.c b/boards/arm/stm32/nucleo-f207zg/src/stm32_bringup.c deleted file mode 100644 index 149f1cc0930e1..0000000000000 --- a/boards/arm/stm32/nucleo-f207zg/src/stm32_bringup.c +++ /dev/null @@ -1,92 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f207zg/src/stm32_bringup.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include "nucleo-f207zg.h" - -#ifdef CONFIG_INPUT_BUTTONS -# include -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_bringup - * - * Description: - * Perform architecture-specific initialization - * - * CONFIG_BOARD_LATE_INITIALIZE=y : - * Called from board_late_initialize(). - * - ****************************************************************************/ - -int stm32_bringup(void) -{ - int ret = OK; - -#ifdef CONFIG_ADC - /* Initialize ADC and register the ADC driver. */ - - ret = stm32_adc_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_adc_setup failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_PWM - /* Initialize PWM and register the PWM driver. */ - - ret = stm32_pwm_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_pwm_setup failed: %d\n", ret); - } -#endif - -#if defined(CONFIG_CDCACM) && !defined(CONFIG_CDCACM_CONSOLE) - /* Initialize CDCACM */ - - syslog(LOG_INFO, "Initialize CDCACM device\n"); - - ret = cdcacm_initialize(0, NULL); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: cdcacm_initialize failed: %d\n", ret); - } -#endif - - UNUSED(ret); - return OK; -} diff --git a/boards/arm/stm32/nucleo-f207zg/src/stm32_buttons.c b/boards/arm/stm32/nucleo-f207zg/src/stm32_buttons.c deleted file mode 100644 index 861f569c31f68..0000000000000 --- a/boards/arm/stm32/nucleo-f207zg/src/stm32_buttons.c +++ /dev/null @@ -1,107 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f207zg/src/stm32_buttons.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include - -#include "stm32_gpio.h" -#include "nucleo-f207zg.h" -#include - -#ifdef CONFIG_ARCH_BUTTONS - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_button_initialize - * - * Description: - * board_button_initialize() must be called to initialize button resources. - * After that, board_buttons() may be called to collect the current state - * of all buttons or board_button_irq() may be called to register button - * interrupt handlers. - * - ****************************************************************************/ - -uint32_t board_button_initialize(void) -{ - stm32_configgpio(GPIO_BTN_USER); - return NUM_BUTTONS; -} - -/**************************************************************************** - * Name: board_buttons - ****************************************************************************/ - -uint32_t board_buttons(void) -{ - return stm32_gpioread(GPIO_BTN_USER) ? 1 : 0; -} - -/**************************************************************************** - * Button support. - * - * Description: - * board_button_initialize() must be called to initialize button resources. - * After that, board_buttons() may be called to collect the current state - * of all buttons or board_button_irq() may be called to register button - * interrupt handlers. - * - * After board_button_initialize() has been called, board_buttons() may be - * called to collect the state of all buttons. board_buttons() returns a - * 32-bit bit set with each bit associated with a button. See the - * BUTTON_*_BIT definitions in board.h for the meaning of each bit. - * - * board_button_irq() may be called to register an interrupt handler that - * will be called when a button is depressed or released. The ID value is - * a button enumeration value that uniquely identifies a button resource. - * See the BUTTON_* definitions in board.h for the meaning of enumeration - * value. - * - ****************************************************************************/ - -#ifdef CONFIG_ARCH_IRQBUTTONS -int board_button_irq(int id, xcpt_t irqhandler, void *arg) -{ - int ret = -EINVAL; - - if (id == BUTTON_USER) - { - ret = stm32_gpiosetevent(GPIO_BTN_USER, true, true, true, - irqhandler, arg); - } - - return ret; -} -#endif -#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/stm32/nucleo-f207zg/src/stm32_pwm.c b/boards/arm/stm32/nucleo-f207zg/src/stm32_pwm.c deleted file mode 100644 index 298ae7ce61721..0000000000000 --- a/boards/arm/stm32/nucleo-f207zg/src/stm32_pwm.c +++ /dev/null @@ -1,110 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f207zg/src/stm32_pwm.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32_pwm.h" -#include "nucleo-f207zg.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -#define HAVE_PWM 1 - -#ifndef CONFIG_PWM -# undef HAVE_PWM -#endif - -#ifndef CONFIG_STM32_TIM1 -# undef HAVE_PWM -#endif - -#ifndef CONFIG_STM32_TIM1_PWM -# undef HAVE_PWM -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_pwm_setup - * - * Description: - * Initialize PWM and register the PWM device. - * - ****************************************************************************/ - -int stm32_pwm_setup(void) -{ -#ifdef HAVE_PWM - static bool initialized = false; - struct pwm_lowerhalf_s *pwm; - int ret; - - /* Have we already initialized? */ - - if (!initialized) - { - /* Call stm32_pwminitialize() to get an instance of the PWM interface */ - - pwm = stm32_pwminitialize(NUCLEOF207ZG_PWMTIMER); - if (!pwm) - { - tmrerr("ERROR: Failed to get the STM32 PWM lower half\n"); - return -ENODEV; - } - - /* Register the PWM driver at "/dev/pwm0" */ - - ret = pwm_register("/dev/pwm0", pwm); - if (ret < 0) - { - tmrerr("ERROR: pwm_register failed: %d\n", ret); - return ret; - } - - /* Now we are initialized */ - - initialized = true; - } - - return OK; -#else - return -ENODEV; -#endif -} diff --git a/boards/arm/stm32/nucleo-f207zg/src/stm32_usb.c b/boards/arm/stm32/nucleo-f207zg/src/stm32_usb.c deleted file mode 100644 index d984030911228..0000000000000 --- a/boards/arm/stm32/nucleo-f207zg/src/stm32_usb.c +++ /dev/null @@ -1,322 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f207zg/src/stm32_usb.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -#include "arm_internal.h" -#include "chip.h" -#include "stm32_gpio.h" -#include "stm32_otgfs.h" -#include "nucleo-f207zg.h" - -#ifdef CONFIG_STM32_OTGFS - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#if defined(CONFIG_USBDEV) || defined(CONFIG_USBHOST) -# define HAVE_USB 1 -#else -# warning "CONFIG_STM32_OTGFS is enabled but neither CONFIG_USBDEV nor CONFIG_USBHOST" -# undef HAVE_USB -#endif - -#ifndef CONFIG_NUCLEOF207ZG_USBHOST_PRIO -# define CONFIG_NUCLEOF207ZG_USBHOST_PRIO 100 -#endif - -#ifndef CONFIG_NUCLEOF207ZG_USBHOST_STACKSIZE -# define CONFIG_NUCLEOF207ZG_USBHOST_STACKSIZE 1024 -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -#ifdef CONFIG_USBHOST -static struct usbhost_connection_s *g_usbconn; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: usbhost_waiter - * - * Description: - * Wait for USB devices to be connected. - * - ****************************************************************************/ - -#ifdef CONFIG_USBHOST -static int usbhost_waiter(int argc, char *argv[]) -{ - struct usbhost_hubport_s *hport; - - uinfo("Running\n"); - for (; ; ) - { - /* Wait for the device to change state */ - - DEBUGVERIFY(CONN_WAIT(g_usbconn, &hport)); - uinfo("%s\n", hport->connected ? "connected" : "disconnected"); - - /* Did we just become connected? */ - - if (hport->connected) - { - /* Yes.. enumerate the newly connected device */ - - CONN_ENUMERATE(g_usbconn, hport); - } - } - - /* Keep the compiler from complaining */ - - return 0; -} -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_usbinitialize - * - * Description: - * Called from stm32_usbinitialize very early in initialization to setup - * USB-related GPIO pins for the nucleo-144 board. - * - ****************************************************************************/ - -void stm32_usbinitialize(void) -{ - /* The OTG FS has an internal soft pull-up. - * No GPIO configuration is required - */ - - /* Configure the OTG FS VBUS sensing GPIO, - * Power On, and Overcurrent GPIOs - */ - -#ifdef CONFIG_STM32_OTGFS - stm32_configgpio(GPIO_OTGFS_VBUS); - stm32_configgpio(GPIO_OTGFS_PWRON); - stm32_configgpio(GPIO_OTGFS_OVER); -#endif -} - -/**************************************************************************** - * Name: stm32_usbhost_initialize - * - * Description: - * Called at application startup time to initialize the USB host - * functionality. - * This function will start a thread that will monitor for device - * connection/disconnection events. - * - ****************************************************************************/ - -#ifdef CONFIG_USBHOST -int stm32_usbhost_initialize(void) -{ - int ret; - - /* First, register all of the class drivers needed to support the drivers - * that we care about: - */ - - uinfo("Register class drivers\n"); - -#ifdef CONFIG_USBHOST_HUB - /* Initialize USB hub class support */ - - ret = usbhost_hub_initialize(); - if (ret < 0) - { - uerr("ERROR: usbhost_hub_initialize failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_USBHOST_MSC - /* Register the USB mass storage class class */ - - ret = usbhost_msc_initialize(); - if (ret != OK) - { - uerr("ERROR: Failed to register the mass storage class: %d\n", ret); - } -#endif - -#ifdef CONFIG_USBHOST_CDCACM - /* Register the CDC/ACM serial class */ - - ret = usbhost_cdcacm_initialize(); - if (ret != OK) - { - uerr("ERROR: Failed to register the CDC/ACM serial class: %d\n", ret); - } -#endif - -#ifdef CONFIG_USBHOST_HIDKBD - /* Initialize the HID keyboard class */ - - ret = usbhost_kbdinit(); - if (ret != OK) - { - uerr("ERROR: Failed to register the HID keyboard class\n"); - } -#endif - -#ifdef CONFIG_USBHOST_HIDMOUSE - /* Initialize the HID mouse class */ - - ret = usbhost_mouse_init(); - if (ret != OK) - { - uerr("ERROR: Failed to register the HID mouse class\n"); - } -#endif - - /* Then get an instance of the USB host interface */ - - uinfo("Initialize USB host\n"); - g_usbconn = stm32_otgfshost_initialize(0); - if (g_usbconn) - { - /* Start a thread to handle device connection. */ - - uinfo("Start usbhost_waiter\n"); - - ret = kthread_create("usbhost", CONFIG_NUCLEOF207ZG_USBHOST_PRIO, - CONFIG_NUCLEOF207ZG_USBHOST_STACKSIZE, - usbhost_waiter, NULL); - return ret < 0 ? -ENOEXEC : OK; - } - - return -ENODEV; -} -#endif - -/**************************************************************************** - * Name: stm32_usbhost_vbusdrive - * - * Description: - * Enable/disable driving of VBUS 5V output. This function must be - * provided be each platform that implements the STM32 OTG FS host - * interface - * - * "On-chip 5 V VBUS generation is not supported. For this reason, a - * charge pump or, if 5 V are available on the application board, a - * basic power switch, must be added externally to drive the 5 V VBUS - * line. The external charge pump can be driven by any GPIO output. - * When the application decides to power on VBUS using the chosen GPIO, - * it must also set the port power bit in the host port control and - * status register (PPWR bit in OTG_FS_HPRT). - * - * "The application uses this field to control power to this port, - * and the core clears this bit on an overcurrent condition." - * - * Input Parameters: - * iface - For future growth to handle multiple USB host interface. - * Should be zero. - * enable - true: enable VBUS power; false: disable VBUS power - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef CONFIG_USBHOST -void stm32_usbhost_vbusdrive(int iface, bool enable) -{ - DEBUGASSERT(iface == 0); - - /* Set the Power Switch by driving the active low enable pin */ - - stm32_gpiowrite(GPIO_OTGFS_PWRON, !enable); -} -#endif - -/**************************************************************************** - * Name: stm32_setup_overcurrent - * - * Description: - * Setup to receive an interrupt-level callback if an overcurrent - * condition is detected. - * - * Input Parameters: - * handler - New overcurrent interrupt handler - * arg - The argument provided for the interrupt handler - * - * Returned Value: - * Zero (OK) is returned on success. Otherwise, a negated errno value - * is returned to indicate the nature of the failure. - * - ****************************************************************************/ - -#ifdef CONFIG_USBHOST -int stm32_setup_overcurrent(xcpt_t handler, void *arg) -{ - return stm32_gpiosetevent(GPIO_OTGFS_OVER, true, true, true, handler, arg); -} -#endif - -/**************************************************************************** - * Name: stm32_usbsuspend - * - * Description: - * Board logic must provide the stm32_usbsuspend logic if the USBDEV - * driver is used. This function is called whenever the USB enters or - * leaves suspend mode. This is an opportunity for the board logic to - * shutdown clocks, power, etc. while the USB is suspended. - * - ****************************************************************************/ - -#ifdef CONFIG_USBDEV -void stm32_usbsuspend(struct usbdev_s *dev, bool resume) -{ - uinfo("resume: %d\n", resume); -} -#endif - -#endif /* CONFIG_STM32_OTGFS */ diff --git a/boards/arm/stm32/nucleo-f207zg/src/stm32_userleds.c b/boards/arm/stm32/nucleo-f207zg/src/stm32_userleds.c deleted file mode 100644 index d0ce94829eef2..0000000000000 --- a/boards/arm/stm32/nucleo-f207zg/src/stm32_userleds.c +++ /dev/null @@ -1,127 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f207zg/src/stm32_userleds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include - -#include -#include - -#include "stm32_gpio.h" -#include "nucleo-f207zg.h" - -#ifndef CONFIG_ARCH_LEDS - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* This array maps an LED number to GPIO pin configuration and is indexed by - * BOARD_LED_ - */ - -static const uint32_t g_ledcfg[BOARD_NLEDS] = -{ - GPIO_LED_GREEN, - GPIO_LED_BLUE, - GPIO_LED_RED, -}; - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_userled_initialize - * - * Description: - * If CONFIG_ARCH_LEDS is defined, then NuttX will control the on-board - * LEDs. If CONFIG_ARCH_LEDS is not defined, then the - * board_userled_initialize() is available to initialize the LED from user - * application logic. - * - ****************************************************************************/ - -uint32_t board_userled_initialize(void) -{ - int i; - - /* Configure LED1-3 GPIOs for output */ - - for (i = 0; i < nitems(g_ledcfg); i++) - { - stm32_configgpio(g_ledcfg[i]); - } - - return BOARD_NLEDS; -} - -/**************************************************************************** - * Name: board_userled - * - * Description: - * If CONFIG_ARCH_LEDS is defined, then NuttX will control the on-board - * LEDs. If CONFIG_ARCH_LEDS is not defined, then the board_userled() is - * available to control the LED from user application logic. - * - ****************************************************************************/ - -void board_userled(int led, bool ledon) -{ - if ((unsigned)led < nitems(g_ledcfg)) - { - stm32_gpiowrite(g_ledcfg[led], ledon); - } -} - -/**************************************************************************** - * Name: board_userled_all - * - * Description: - * If CONFIG_ARCH_LEDS is defined, then NuttX will control the on-board - * LEDs. If CONFIG_ARCH_LEDS is not defined, then the board_userled_all() - * is available to control the LED from user application logic. NOTE: since - * there is only a single LED on-board, this is function is not very useful. - * - ****************************************************************************/ - -void board_userled_all(uint32_t ledset) -{ - int i; - - /* Configure LED1-3 GPIOs for output */ - - for (i = 0; i < nitems(g_ledcfg); i++) - { - stm32_gpiowrite(g_ledcfg[i], (ledset & (1 << i)) != 0); - } -} - -#endif /* !CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/nucleo-f302r8/CMakeLists.txt b/boards/arm/stm32/nucleo-f302r8/CMakeLists.txt deleted file mode 100644 index 62e41b7cca4dc..0000000000000 --- a/boards/arm/stm32/nucleo-f302r8/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/nucleo-f302r8/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32/nucleo-f302r8/configs/can/defconfig b/boards/arm/stm32/nucleo-f302r8/configs/can/defconfig deleted file mode 100644 index def904eba3da8..0000000000000 --- a/boards/arm/stm32/nucleo-f302r8/configs/can/defconfig +++ /dev/null @@ -1,54 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="nucleo-f302r8" -CONFIG_ARCH_BOARD_NUCLEO_F302R8=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F302R8=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_CAN_ERRORS=y -CONFIG_CAN_EXTID=y -CONFIG_DEBUG_FULLOPT=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_DEFAULT_SMALL=y -CONFIG_EXAMPLES_CAN=y -CONFIG_EXAMPLES_CAN_WRITE=y -CONFIG_FDCLONE_STDIO=y -CONFIG_FILE_STREAM=y -CONFIG_FS_LARGEFILE=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INIT_STACKSIZE=1024 -CONFIG_INTELHEX_BINARY=y -CONFIG_NAME_MAX=16 -CONFIG_NSH_ARGCAT=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=256 -CONFIG_NSH_QUOTE=y -CONFIG_POSIX_SPAWN_DEFAULT_STACKSIZE=512 -CONFIG_RAM_SIZE=16386 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=6 -CONFIG_START_MONTH=12 -CONFIG_START_YEAR=2011 -CONFIG_STDIO_BUFFER_SIZE=255 -CONFIG_STM32_CAN1=y -CONFIG_STM32_CAN_TSEG1=15 -CONFIG_STM32_CAN_TSEG2=2 -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_PWR=y -CONFIG_STM32_USART2=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/nucleo-f302r8/configs/cansock/defconfig b/boards/arm/stm32/nucleo-f302r8/configs/cansock/defconfig deleted file mode 100644 index 701e71056cc6d..0000000000000 --- a/boards/arm/stm32/nucleo-f302r8/configs/cansock/defconfig +++ /dev/null @@ -1,67 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_NET_ETHERNET is not set -# CONFIG_NET_IPv4 is not set -CONFIG_ALLOW_BSD_COMPONENTS=y -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="nucleo-f302r8" -CONFIG_ARCH_BOARD_NUCLEO_F302R8=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F302R8=y -CONFIG_ARCH_INTERRUPTSTACK=1024 -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_INITTHREAD_STACKSIZE=1024 -CONFIG_BOARD_LOOPSPERMSEC=8499 -CONFIG_BUILTIN=y -CONFIG_CANUTILS_CANDUMP=y -CONFIG_CANUTILS_CANSEND=y -CONFIG_CANUTILS_LIBCANUTILS=y -CONFIG_DEBUG_FULLOPT=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_DEFAULT_SMALL=y -CONFIG_ENABLE_ALL_SIGNALS=y -CONFIG_FILE_STREAM=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_IOB_BUFSIZE=64 -CONFIG_IOB_NBUFFERS=5 -CONFIG_IRQ_WORK_STACKSIZE=1024 -CONFIG_LTO_FULL=y -CONFIG_NAME_MAX=0 -CONFIG_NET=y -CONFIG_NETDEV_IFINDEX=y -CONFIG_NETDEV_LATEINIT=y -CONFIG_NET_CAN=y -CONFIG_NET_CAN_ERRORS=y -CONFIG_NET_PREALLOC_DEVIF_CALLBACKS=2 -CONFIG_NET_SOCKOPTS=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_PROMPT_MAX=8 -CONFIG_RAM_SIZE=16386 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_LPWORK=y -CONFIG_SCHED_LPWORKSTACKSIZE=1024 -CONFIG_SCHED_WAITPID=y -CONFIG_SIG_PREALLOC_IRQ_ACTIONS=0 -CONFIG_START_DAY=14 -CONFIG_START_MONTH=10 -CONFIG_START_YEAR=2014 -CONFIG_STM32_CAN1=y -CONFIG_STM32_CAN_SOCKET=y -CONFIG_STM32_CAN_TSEG1=15 -CONFIG_STM32_CAN_TSEG2=2 -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_USART2=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/nucleo-f302r8/configs/highpri/defconfig b/boards/arm/stm32/nucleo-f302r8/configs/highpri/defconfig deleted file mode 100644 index 386f0a3d39965..0000000000000 --- a/boards/arm/stm32/nucleo-f302r8/configs/highpri/defconfig +++ /dev/null @@ -1,58 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="nucleo-f302r8" -CONFIG_ARCH_BOARD_NUCLEO_F302R8=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F302R8=y -CONFIG_ARCH_HIPRI_INTERRUPT=y -CONFIG_ARCH_RAMVECTORS=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARDCTL=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_DISABLE_ENVIRON=y -CONFIG_DISABLE_MQUEUE=y -CONFIG_DISABLE_POSIX_TIMERS=y -CONFIG_FDCLONE_STDIO=y -CONFIG_INIT_ENTRYPOINT="highpri_main" -CONFIG_INIT_STACKSIZE=1024 -CONFIG_INTELHEX_BINARY=y -CONFIG_LIBM=y -CONFIG_NAME_MAX=16 -CONFIG_NUCLEOF302R8_HIGHPRI=y -CONFIG_POSIX_SPAWN_DEFAULT_STACKSIZE=512 -CONFIG_PTHREAD_STACK_DEFAULT=1024 -CONFIG_PTHREAD_STACK_MIN=1024 -CONFIG_PWM=y -CONFIG_RAM_SIZE=12288 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=6 -CONFIG_START_MONTH=12 -CONFIG_START_YEAR=2011 -CONFIG_STM32_ADC1=y -CONFIG_STM32_ADC1_DMA=y -CONFIG_STM32_ADC1_DMA_CFG=1 -CONFIG_STM32_ADC1_EXTSEL=y -CONFIG_STM32_ADC_LL_OPS=y -CONFIG_STM32_ADC_NOIRQ=y -CONFIG_STM32_DMA1=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_PWM_LL_OPS=y -CONFIG_STM32_PWR=y -CONFIG_STM32_TIM1=y -CONFIG_STM32_TIM1_PWM=y -CONFIG_STM32_USART2=y -CONFIG_SYSTEM_READLINE=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/nucleo-f302r8/configs/ihm07m1_b16/defconfig b/boards/arm/stm32/nucleo-f302r8/configs/ihm07m1_b16/defconfig deleted file mode 100644 index 39910fedf6952..0000000000000 --- a/boards/arm/stm32/nucleo-f302r8/configs/ihm07m1_b16/defconfig +++ /dev/null @@ -1,87 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_DISABLE_MQUEUE is not set -# CONFIG_DISABLE_PTHREAD is not set -CONFIG_ADC=y -CONFIG_ADC_FIFOSIZE=3 -CONFIG_ANALOG=y -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="nucleo-f302r8" -CONFIG_ARCH_BOARD_COMMON=y -CONFIG_ARCH_BOARD_NUCLEO_F302R8=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F302R8=y -CONFIG_ARCH_INTERRUPTSTACK=1024 -CONFIG_ARCH_IRQBUTTONS=y -CONFIG_ARMV7M_LIBM=y -CONFIG_BOARDCTL=y -CONFIG_BOARD_LOOPSPERMSEC=8499 -CONFIG_BOARD_STM32_IHM07M1=y -CONFIG_BOARD_STM32_IHM07M1_POT=y -CONFIG_BOARD_STM32_IHM07M1_VBUS=y -CONFIG_BUILTIN=y -CONFIG_DEBUG_FULLOPT=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_DEFAULT_SMALL=y -CONFIG_DEFAULT_TASK_STACKSIZE=1024 -CONFIG_EXAMPLES_FOC=y -CONFIG_EXAMPLES_FOC_ADC_MAX=4095 -CONFIG_EXAMPLES_FOC_ADC_VREF=3300 -CONFIG_EXAMPLES_FOC_CONTROL_STACKSIZE=2048 -CONFIG_EXAMPLES_FOC_FIXED16_INST=1 -CONFIG_EXAMPLES_FOC_HAVE_BUTTON=y -CONFIG_EXAMPLES_FOC_NOTIFIER_FREQ=5000 -CONFIG_EXAMPLES_FOC_PWM_FREQ=20000 -CONFIG_EXAMPLES_FOC_RAMP_ACC=1000000 -CONFIG_EXAMPLES_FOC_RAMP_DEC=1000000 -CONFIG_EXAMPLES_FOC_RAMP_THR=10000 -CONFIG_EXAMPLES_FOC_SETPOINT_ADC=y -CONFIG_EXAMPLES_FOC_VBUS_ADC=y -CONFIG_EXAMPLES_FOC_VBUS_SCALE=19152 -CONFIG_INDUSTRY_FOC=y -CONFIG_INDUSTRY_FOC_FIXED16=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INPUT=y -CONFIG_INPUT_BUTTONS=y -CONFIG_INPUT_BUTTONS_LOWER=y -CONFIG_INTELHEX_BINARY=y -CONFIG_LIBM=y -CONFIG_MOTOR=y -CONFIG_MOTOR_FOC=y -CONFIG_MOTOR_FOC_TRACE=y -CONFIG_MQ_MAXMSGSIZE=5 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_DISABLE_HELP=y -CONFIG_RAM_SIZE=16386 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=14 -CONFIG_START_MONTH=10 -CONFIG_START_YEAR=2014 -CONFIG_STM32_ADC1_ANIOC_TRIGGER=1 -CONFIG_STM32_ADC1_DMA=y -CONFIG_STM32_ADC1_DMA_CFG=1 -CONFIG_STM32_ADC1_INJECTED_CHAN=3 -CONFIG_STM32_DMA1=y -CONFIG_STM32_DMA2=y -CONFIG_STM32_FOC=y -CONFIG_STM32_FOC_FOC0=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_TIM1_CH1MODE=0 -CONFIG_STM32_TIM1_CH2MODE=0 -CONFIG_STM32_TIM1_CH3MODE=0 -CONFIG_STM32_TIM1_MODE=2 -CONFIG_STM32_USART2=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART2_SERIAL_CONSOLE=y -CONFIG_USART2_TXDMA=y diff --git a/boards/arm/stm32/nucleo-f302r8/configs/ihm07m1_f32/defconfig b/boards/arm/stm32/nucleo-f302r8/configs/ihm07m1_f32/defconfig deleted file mode 100644 index c3c5fc1ce3430..0000000000000 --- a/boards/arm/stm32/nucleo-f302r8/configs/ihm07m1_f32/defconfig +++ /dev/null @@ -1,86 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_DISABLE_MQUEUE is not set -# CONFIG_DISABLE_PTHREAD is not set -CONFIG_ADC=y -CONFIG_ADC_FIFOSIZE=3 -CONFIG_ANALOG=y -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="nucleo-f302r8" -CONFIG_ARCH_BOARD_COMMON=y -CONFIG_ARCH_BOARD_NUCLEO_F302R8=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F302R8=y -CONFIG_ARCH_INTERRUPTSTACK=1024 -CONFIG_ARCH_IRQBUTTONS=y -CONFIG_ARMV7M_LIBM=y -CONFIG_BOARDCTL=y -CONFIG_BOARD_LOOPSPERMSEC=8499 -CONFIG_BOARD_STM32_IHM07M1=y -CONFIG_BOARD_STM32_IHM07M1_POT=y -CONFIG_BOARD_STM32_IHM07M1_VBUS=y -CONFIG_BUILTIN=y -CONFIG_DEBUG_FULLOPT=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_DEFAULT_SMALL=y -CONFIG_DEFAULT_TASK_STACKSIZE=1024 -CONFIG_EXAMPLES_FOC=y -CONFIG_EXAMPLES_FOC_ADC_MAX=4095 -CONFIG_EXAMPLES_FOC_ADC_VREF=3300 -CONFIG_EXAMPLES_FOC_CONTROL_STACKSIZE=2048 -CONFIG_EXAMPLES_FOC_FLOAT_INST=1 -CONFIG_EXAMPLES_FOC_HAVE_BUTTON=y -CONFIG_EXAMPLES_FOC_NOTIFIER_FREQ=5000 -CONFIG_EXAMPLES_FOC_PWM_FREQ=20000 -CONFIG_EXAMPLES_FOC_RAMP_ACC=1000000 -CONFIG_EXAMPLES_FOC_RAMP_DEC=1000000 -CONFIG_EXAMPLES_FOC_RAMP_THR=10000 -CONFIG_EXAMPLES_FOC_SETPOINT_ADC=y -CONFIG_EXAMPLES_FOC_VBUS_ADC=y -CONFIG_EXAMPLES_FOC_VBUS_SCALE=19152 -CONFIG_INDUSTRY_FOC=y -CONFIG_INDUSTRY_FOC_FLOAT=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INPUT=y -CONFIG_INPUT_BUTTONS=y -CONFIG_INPUT_BUTTONS_LOWER=y -CONFIG_INTELHEX_BINARY=y -CONFIG_LIBM=y -CONFIG_MOTOR=y -CONFIG_MOTOR_FOC=y -CONFIG_MOTOR_FOC_TRACE=y -CONFIG_MQ_MAXMSGSIZE=5 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_RAM_SIZE=16386 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=14 -CONFIG_START_MONTH=10 -CONFIG_START_YEAR=2014 -CONFIG_STM32_ADC1_ANIOC_TRIGGER=1 -CONFIG_STM32_ADC1_DMA=y -CONFIG_STM32_ADC1_DMA_CFG=1 -CONFIG_STM32_ADC1_INJECTED_CHAN=3 -CONFIG_STM32_DMA1=y -CONFIG_STM32_DMA2=y -CONFIG_STM32_FOC=y -CONFIG_STM32_FOC_FOC0=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_TIM1_CH1MODE=0 -CONFIG_STM32_TIM1_CH2MODE=0 -CONFIG_STM32_TIM1_CH3MODE=0 -CONFIG_STM32_TIM1_MODE=2 -CONFIG_STM32_USART2=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART2_SERIAL_CONSOLE=y -CONFIG_USART2_TXDMA=y diff --git a/boards/arm/stm32/nucleo-f302r8/configs/nsh/defconfig b/boards/arm/stm32/nucleo-f302r8/configs/nsh/defconfig deleted file mode 100644 index a1df51d77ca57..0000000000000 --- a/boards/arm/stm32/nucleo-f302r8/configs/nsh/defconfig +++ /dev/null @@ -1,85 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_SYSTEM_DD is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="nucleo-f302r8" -CONFIG_ARCH_BOARD_NUCLEO_F302R8=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F302R8=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_DEBUG_FULLOPT=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_DISABLE_ENVIRON=y -CONFIG_DISABLE_MQUEUE=y -CONFIG_DISABLE_POSIX_TIMERS=y -CONFIG_DISABLE_PTHREAD=y -CONFIG_EXAMPLES_HELLO=y -CONFIG_FDCLONE_STDIO=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INIT_STACKSIZE=1024 -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_NAME_MAX=16 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_DISABLE_BASENAME=y -CONFIG_NSH_DISABLE_CAT=y -CONFIG_NSH_DISABLE_CD=y -CONFIG_NSH_DISABLE_CMP=y -CONFIG_NSH_DISABLE_CP=y -CONFIG_NSH_DISABLE_DF=y -CONFIG_NSH_DISABLE_DIRNAME=y -CONFIG_NSH_DISABLE_EXEC=y -CONFIG_NSH_DISABLE_EXIT=y -CONFIG_NSH_DISABLE_GET=y -CONFIG_NSH_DISABLE_HEXDUMP=y -CONFIG_NSH_DISABLE_KILL=y -CONFIG_NSH_DISABLE_LOSETUP=y -CONFIG_NSH_DISABLE_LS=y -CONFIG_NSH_DISABLE_MKDIR=y -CONFIG_NSH_DISABLE_MKRD=y -CONFIG_NSH_DISABLE_MOUNT=y -CONFIG_NSH_DISABLE_MV=y -CONFIG_NSH_DISABLE_PUT=y -CONFIG_NSH_DISABLE_PWD=y -CONFIG_NSH_DISABLE_RM=y -CONFIG_NSH_DISABLE_RMDIR=y -CONFIG_NSH_DISABLE_SET=y -CONFIG_NSH_DISABLE_SLEEP=y -CONFIG_NSH_DISABLE_SOURCE=y -CONFIG_NSH_DISABLE_TEST=y -CONFIG_NSH_DISABLE_TIME=y -CONFIG_NSH_DISABLE_UMOUNT=y -CONFIG_NSH_DISABLE_UNAME=y -CONFIG_NSH_DISABLE_UNSET=y -CONFIG_NSH_DISABLE_USLEEP=y -CONFIG_NSH_DISABLE_WGET=y -CONFIG_NSH_DISABLE_XD=y -CONFIG_NSH_FILEIOSIZE=256 -CONFIG_NSH_READLINE=y -CONFIG_POSIX_SPAWN_DEFAULT_STACKSIZE=512 -CONFIG_PTHREAD_STACK_DEFAULT=1024 -CONFIG_PTHREAD_STACK_MIN=1024 -CONFIG_RAM_SIZE=16386 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=6 -CONFIG_START_MONTH=12 -CONFIG_START_YEAR=2011 -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_PWR=y -CONFIG_STM32_USART2=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/nucleo-f302r8/configs/qenco/defconfig b/boards/arm/stm32/nucleo-f302r8/configs/qenco/defconfig deleted file mode 100644 index 1197a24f5e613..0000000000000 --- a/boards/arm/stm32/nucleo-f302r8/configs/qenco/defconfig +++ /dev/null @@ -1,111 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_DISABLE_ENVIRON is not set -# CONFIG_DISABLE_MQUEUE is not set -# CONFIG_DISABLE_MQUEUE_NOTIFICATION is not set -# CONFIG_DISABLE_POSIX_TIMERS is not set -# CONFIG_DISABLE_PSEUDOFS_OPERATIONS is not set -# CONFIG_DISABLE_PTHREAD is not set -# CONFIG_NSH_DISABLEBG is not set -# CONFIG_NSH_DISABLESCRIPT is not set -# CONFIG_NSH_DISABLE_BASENAME is not set -# CONFIG_NSH_DISABLE_CAT is not set -# CONFIG_NSH_DISABLE_CD is not set -# CONFIG_NSH_DISABLE_CMP is not set -# CONFIG_NSH_DISABLE_CP is not set -# CONFIG_NSH_DISABLE_DF is not set -# CONFIG_NSH_DISABLE_DIRNAME is not set -# CONFIG_NSH_DISABLE_DMESG is not set -# CONFIG_NSH_DISABLE_ECHO is not set -# CONFIG_NSH_DISABLE_ENV is not set -# CONFIG_NSH_DISABLE_EXEC is not set -# CONFIG_NSH_DISABLE_EXIT is not set -# CONFIG_NSH_DISABLE_EXPORT is not set -# CONFIG_NSH_DISABLE_FREE is not set -# CONFIG_NSH_DISABLE_GET is not set -# CONFIG_NSH_DISABLE_HEXDUMP is not set -# CONFIG_NSH_DISABLE_ITEF is not set -# CONFIG_NSH_DISABLE_KILL is not set -# CONFIG_NSH_DISABLE_LOOPS is not set -# CONFIG_NSH_DISABLE_LOSETUP is not set -# CONFIG_NSH_DISABLE_LS is not set -# CONFIG_NSH_DISABLE_MKDIR is not set -# CONFIG_NSH_DISABLE_MKRD is not set -# CONFIG_NSH_DISABLE_MOUNT is not set -# CONFIG_NSH_DISABLE_MV is not set -# CONFIG_NSH_DISABLE_PRINTF is not set -# CONFIG_NSH_DISABLE_PUT is not set -# CONFIG_NSH_DISABLE_PWD is not set -# CONFIG_NSH_DISABLE_RM is not set -# CONFIG_NSH_DISABLE_RMDIR is not set -# CONFIG_NSH_DISABLE_SEMICOLON is not set -# CONFIG_NSH_DISABLE_SET is not set -# CONFIG_NSH_DISABLE_SLEEP is not set -# CONFIG_NSH_DISABLE_SOURCE is not set -# CONFIG_NSH_DISABLE_TEST is not set -# CONFIG_NSH_DISABLE_TIME is not set -# CONFIG_NSH_DISABLE_TRUNCATE is not set -# CONFIG_NSH_DISABLE_UMOUNT is not set -# CONFIG_NSH_DISABLE_UNAME is not set -# CONFIG_NSH_DISABLE_UNSET is not set -# CONFIG_NSH_DISABLE_UPTIME is not set -# CONFIG_NSH_DISABLE_USLEEP is not set -# CONFIG_NSH_DISABLE_WGET is not set -# CONFIG_NSH_DISABLE_XD is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="nucleo-f302r8" -CONFIG_ARCH_BOARD_COMMON=y -CONFIG_ARCH_BOARD_NUCLEO_F302R8=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F302R8=y -CONFIG_ARCH_INTERRUPTSTACK=1024 -CONFIG_ARCH_IRQPRIO=y -CONFIG_BOARD_LOOPSPERMSEC=8499 -CONFIG_BUILTIN=y -CONFIG_DEBUG_FULLOPT=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_DEFAULT_SMALL=y -CONFIG_EXAMPLES_QENCODER=y -CONFIG_EXAMPLES_QENCODER_HAVE_MAXPOS=y -CONFIG_EXAMPLES_QENCODER_MAXPOS=8192 -CONFIG_FILE_STREAM=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LIBM_TOOLCHAIN=y -CONFIG_LINE_MAX=80 -CONFIG_MQ_MAXMSGSIZE=5 -CONFIG_NSH_ARGCAT=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_CLE=y -CONFIG_NSH_FILEIOSIZE=1024 -CONFIG_PREALLOC_MQ_IRQ_MSGS=8 -CONFIG_PREALLOC_MQ_MSGS=8 -CONFIG_PTHREAD_MUTEX_ROBUST=y -CONFIG_RAM_SIZE=16386 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_SENSORS=y -CONFIG_SENSORS_QENCODER=y -CONFIG_SIG_PREALLOC_IRQ_ACTIONS=8 -CONFIG_START_DAY=14 -CONFIG_START_MONTH=10 -CONFIG_START_YEAR=2014 -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_QENCODER_DISABLE_EXTEND16BTIMERS=y -CONFIG_STM32_QENCODER_SAMPLE_FDTS_2=y -CONFIG_STM32_TIM2=y -CONFIG_STM32_TIM2_QE=y -CONFIG_STM32_TIM2_QEPSC=0 -CONFIG_STM32_USART2=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/nucleo-f302r8/include/board.h b/boards/arm/stm32/nucleo-f302r8/include/board.h deleted file mode 100644 index 21d24f4b50e87..0000000000000 --- a/boards/arm/stm32/nucleo-f302r8/include/board.h +++ /dev/null @@ -1,308 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f302r8/include/board.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __BOARDS_ARM_STM32_NUCLEO_F302R8_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32_NUCLEO_F302R8_INCLUDE_BOARD_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#ifndef __ASSEMBLY__ -# include -# include -#endif - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Clocking *****************************************************************/ - -/* HSI - Internal 8 MHz RC Oscillator - * LSI - 32 KHz RC - * HSE - On-board crystal frequency is 8MHz - * LSE - 32.768 kHz - */ - -#define STM32_BOARD_XTAL 8000000ul /* X1 on board */ - -#define STM32_HSI_FREQUENCY 8000000ul -#define STM32_LSI_FREQUENCY 40000 /* Between 30kHz and 60kHz */ -#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL -#define STM32_LSE_FREQUENCY 32768 /* X2 on board */ - -/* PLL source is HSE/1, PLL multiplier is 9: PLL frequency is - * 8MHz (XTAL) x 9 = 72MHz - */ - -#define STM32_CFGR_PLLSRC RCC_CFGR_PLLSRC -#define STM32_CFGR_PLLXTPRE 0 -#define STM32_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx9 -#define STM32_PLL_FREQUENCY (9*STM32_BOARD_XTAL) - -/* Use the PLL and set the SYSCLK source to be the PLL */ - -#define STM32_SYSCLK_SW RCC_CFGR_SW_PLL -#define STM32_SYSCLK_SWS RCC_CFGR_SWS_PLL -#define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY - -/* AHB clock (HCLK) is SYSCLK (72MHz) */ - -#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK -#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY - -/* APB2 clock (PCLK2) is HCLK (72MHz) */ - -#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK -#define STM32_PCLK2_FREQUENCY STM32_HCLK_FREQUENCY -#define STM32_APB2_CLKIN (STM32_PCLK2_FREQUENCY) /* Timers 1 and 8, 15-17 */ - -/* APB2 timers 1 and 8, 15-17 will receive PCLK2. */ - -/* Timers driven from APB2 will be PCLK2 */ - -#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB1_TIM15_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB1_TIM16_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB1_TIM17_CLKIN (STM32_PCLK2_FREQUENCY) - -/* APB1 clock (PCLK1) is HCLK/2 (36MHz) */ - -#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd2 -#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/2) - -/* APB1 timers 2-7 will be twice PCLK1 */ - -#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) - -/* USB divider -- Divide PLL clock by 1.5 */ - -#define STM32_CFGR_USBPRE 0 - -/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx - * otherwise frequency is 2xAPBx. - * Note: TIM1,8 are on APB2, others on APB1 - */ - -#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM2_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM3_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM4_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM5_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM6_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM7_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY - -/* LED definitions **********************************************************/ - -/* The Nucleo F302R8 board has three LEDs. Two of these are controlled by - * logic on the board and are not available for software control: - * - * LD1 COM: LD1 default status is red. LD1 turns to green to indicate that - * communications are in progress between the PC and the - * ST-LINK/V2-1. - * LD3 PWR: red LED indicates that the board is powered. - * - * And one can be controlled by software: - * - * User LD2: green LED is a user LED connected to the I/O PB13 of the - * STM32F302R8T6. - * - * If CONFIG_ARCH_LEDS is not defined, then the user can control the LED in - * any way. The following definition is used to access the LED. - */ - -/* LED index values for use with board_userled() */ - -#define BOARD_LED1 0 /* User LD2 */ -#define BOARD_NLEDS 1 - -/* LED bits for use with board_userled_all() */ - -#define BOARD_LED1_BIT (1 << BOARD_LED1) - -/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the LED on board - * the Nucleo F302R8. The following definitions describe how NuttX controls - * the LED: - * - * SYMBOL Meaning LED1 state - * ------------------ ----------------------- ---------- - * LED_STARTED NuttX has been started OFF - * LED_HEAPALLOCATE Heap has been allocated OFF - * LED_IRQSENABLED Interrupts enabled OFF - * LED_STACKCREATED Idle stack created ON - * LED_INIRQ In an interrupt No change - * LED_SIGNAL In a signal handler No change - * LED_ASSERTION An assertion failed No change - * LED_PANIC The system has crashed Blinking - * LED_IDLE STM32 is in sleep mode Not used - */ - -#define LED_STARTED 0 -#define LED_HEAPALLOCATE 0 -#define LED_IRQSENABLED 0 -#define LED_STACKCREATED 1 -#define LED_INIRQ 2 -#define LED_SIGNAL 2 -#define LED_ASSERTION 2 -#define LED_PANIC 1 - -/* Button definitions *******************************************************/ - -/* The Nucleo F302R8 supports two buttons; only one button is controllable - * by software: - * - * B1 USER: user button connected to the I/O PC13 of the STM32F302R8T6. - * B2 RESET: push button connected to NRST is used to RESET the - * STM32F302R8T6. - */ - -#define BUTTON_USER 0 -#define NUM_BUTTONS 1 - -#define BUTTON_USER_BIT (1 << BUTTON_USER) - -/* Alternate function pin selections ****************************************/ - -/* TIM2 input ***************************************************************/ - -#define GPIO_TIM2_CH1IN (GPIO_TIM2_CH1IN_2 | GPIO_PULLUP | GPIO_SPEED_50MHz) /* PA15 */ -#define GPIO_TIM2_CH2IN (GPIO_TIM2_CH2IN_2 | GPIO_PULLUP | GPIO_SPEED_50MHz) /* PB3 */ - -/* USART */ - -/* By default the USART2 is connected to STLINK Virtual COM Port: - * USART2_RX - PA3 - * USART2_TX - PA2 - */ - -#define GPIO_USART2_RX (GPIO_USART2_RX_2|GPIO_SPEED_50MHz) /* PA3 */ -#define GPIO_USART2_TX (GPIO_USART2_TX_2|GPIO_SPEED_50MHz) /* PA2 */ - -/* USART1 - * - * At default use: - * USART1_RX - PB7 - * USART1_TX - PB6 - * - * If CONFIG_NUCLEOF302R8_RS485_WAVESHARE=y use configuration to match RS485 - * shield from Waveshare: - * - * USART1_RX - PA10 - * USART1_TX - PA9 - * RS485_DIR - PA8 (arduino D7) - * - */ - -#ifdef CONFIG_NUCLEOF302R8_RS485_WAVESHARE -# define GPIO_USART1_RX (GPIO_USART1_RX_1|GPIO_SPEED_50MHz) /* PA10 */ -# define GPIO_USART1_TX (GPIO_USART1_TX_1|GPIO_SPEED_50MHz) /* PA9 */ -# define GPIO_USART1_RS485_DIR (GPIO_OUTPUT | GPIO_PUSHPULL | \ - GPIO_SPEED_50MHz | GPIO_OUTPUT_CLEAR | \ - GPIO_PORTA | GPIO_PIN8) -#else -# define GPIO_USART1_RX (GPIO_USART1_RX_2|GPIO_SPEED_50MHz) /* PB7 */ -# define GPIO_USART1_TX (GPIO_USART1_TX_2|GPIO_SPEED_50MHz) /* PB6 */ -#endif - -/* CAN */ - -#define GPIO_CAN1_RX (GPIO_CAN_RX_3|GPIO_SPEED_50MHz) /* PB8 */ -#define GPIO_CAN1_TX (GPIO_CAN_TX_3|GPIO_SPEED_50MHz) /* PB9 */ - -/* PWM configuration ********************************************************/ - -/* TIM1 PWM */ - -#define STM32_TIM1_TRGO 0 - -#define GPIO_TIM1_CH1OUT (GPIO_TIM1_CH1OUT_2|GPIO_SPEED_50MHz) /* PA8 */ -#define GPIO_TIM1_CH1NOUT (GPIO_TIM1_CH1N_3|GPIO_SPEED_50MHz) /* PA11 */ -#define GPIO_TIM1_CH2OUT (GPIO_TIM1_CH2OUT_2|GPIO_SPEED_50MHz) /* PA9 */ -#define GPIO_TIM1_CH2NOUT (GPIO_TIM1_CH2N_2|GPIO_SPEED_50MHz) /* PA12 */ -#define GPIO_TIM1_CH3OUT (GPIO_TIM1_CH3OUT_2|GPIO_SPEED_50MHz) /* PA10 */ -#define GPIO_TIM1_CH3NOUT (GPIO_TIM1_CH3N_3|GPIO_SPEED_50MHz) /* PB1 */ - -/* TIM2 PWM */ - -#define GPIO_TIM2_CH1OUT (GPIO_TIM2_CH1_ETR_1|GPIO_SPEED_50MHz) /* PA0 */ -#define GPIO_TIM2_CH2OUT (GPIO_TIM2_CH2OUT_1|GPIO_SPEED_50MHz) /* PA1 */ -#define GPIO_TIM2_CH3OUT (GPIO_TIM2_CH3OUT_1|GPIO_SPEED_50MHz) /* PA9 */ - -/* DMA channels *************************************************************/ - -/* ADC */ - -#define ADC1_DMA_CHAN DMACHAN_ADC1 /* DMA1_CH1 */ - -#ifdef CONFIG_BOARD_STM32_IHM07M1 - -/* Configuration specific for the X-NUCLEO-IHM07M1 expansion board with - * the L6230 gate drivers. - */ - -/* TIM1 configuration *******************************************************/ - -# define GPIO_TIM1_CH1OUT (GPIO_TIM1_CH1OUT_2|GPIO_SPEED_50MHz) /* TIM1 CH1 - PA8 - U high */ -# define GPIO_TIM1_CH2OUT (GPIO_TIM1_CH2OUT_2|GPIO_SPEED_50MHz) /* TIM1 CH2 - PA9 - V high */ -# define GPIO_TIM1_CH3OUT (GPIO_TIM1_CH3OUT_2|GPIO_SPEED_50MHz) /* TIM1 CH3 - PA10 - W high */ -# define GPIO_TIM1_CH4OUT 0 /* not used as output */ - -/* UVW ENABLE */ - -# define GPIO_FOC_EN_U (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz| \ - GPIO_OUTPUT_CLEAR|GPIO_PORTC|GPIO_PIN10) -# define GPIO_FOC_EN_V (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz| \ - GPIO_OUTPUT_CLEAR|GPIO_PORTC|GPIO_PIN11) -# define GPIO_FOC_EN_W (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz| \ - GPIO_OUTPUT_CLEAR|GPIO_PORTC|GPIO_PIN12) - -/* DIAG/ENABLE */ - -# define GPIO_FOC_DIAGEN (GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz| \ - GPIO_OUTPUT_CLEAR|GPIO_PORTA|GPIO_PIN11) - -# define GPIO_FOC_LED2 (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz| \ - GPIO_OUTPUT_CLEAR|GPIO_PORTB|GPIO_PIN2) - -/* Debug pins */ - -# define GPIO_FOC_DEBUG0 (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz| \ - GPIO_OUTPUT_CLEAR|GPIO_PORTB|GPIO_PIN8) -# define GPIO_FOC_DEBUG1 (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz| \ - GPIO_OUTPUT_CLEAR|GPIO_PORTB|GPIO_PIN9) -# define GPIO_FOC_DEBUG2 (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz| \ - GPIO_OUTPUT_CLEAR|GPIO_PORTC|GPIO_PIN6) -# define GPIO_FOC_DEBUG3 (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz| \ - GPIO_OUTPUT_CLEAR|GPIO_PORTC|GPIO_PIN5) - -#endif /* CONFIG_BOARD_STM32_IHM07M1 */ - -#endif /* __BOARDS_ARM_STM32_NUCLEO_F302R8_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32/nucleo-f302r8/scripts/Make.defs b/boards/arm/stm32/nucleo-f302r8/scripts/Make.defs deleted file mode 100644 index d863be25bf563..0000000000000 --- a/boards/arm/stm32/nucleo-f302r8/scripts/Make.defs +++ /dev/null @@ -1,41 +0,0 @@ -############################################################################ -# boards/arm/stm32/nucleo-f302r8/scripts/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/.config -include $(TOPDIR)/tools/Config.mk -include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs - -LDSCRIPT = ld.script -ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) - -ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 - -CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) -CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) -CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -AFLAGS := $(CFLAGS) -D__ASSEMBLY__ - -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections -LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32/nucleo-f302r8/scripts/ld.script b/boards/arm/stm32/nucleo-f302r8/scripts/ld.script deleted file mode 100644 index cde87e144cb28..0000000000000 --- a/boards/arm/stm32/nucleo-f302r8/scripts/ld.script +++ /dev/null @@ -1,127 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f302r8/scripts/ld.script - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* The STM32F302R8T6 has 64Kb of FLASH beginning at address 0x0800:0000 and - * 16Kb of SRAM. - * - * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 - * where the code expects to begin execution by jumping to the entry point in - * the 0x0800:0000 address range. - */ - -MEMORY -{ - flash (rx) : ORIGIN = 0x08000000, LENGTH = 64K - sram (rwx) : ORIGIN = 0x20000000, LENGTH = 16K -} - -OUTPUT_ARCH(arm) -EXTERN(_vectors) -ENTRY(_stext) -SECTIONS -{ - .text : { - _stext = ABSOLUTE(.); - *(.vectors) - *(.text .text.*) - *(.fixup) - *(.gnu.warning) - *(.rodata .rodata.*) - *(.gnu.linkonce.t.*) - *(.glue_7) - *(.glue_7t) - *(.got) - *(.gcc_except_table) - *(.gnu.linkonce.r.*) - _etext = ABSOLUTE(.); - } > flash - - .init_section : ALIGN(4) { - _sinit = ABSOLUTE(.); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) - KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) - _einit = ABSOLUTE(.); - } > flash - - .ARM.extab : ALIGN(4) { - *(.ARM.extab*) - } > flash - - .ARM.exidx : ALIGN(4) { - __exidx_start = ABSOLUTE(.); - *(.ARM.exidx*) - __exidx_end = ABSOLUTE(.); - } > flash - - .tdata : { - _stdata = ABSOLUTE(.); - *(.tdata .tdata.* .gnu.linkonce.td.*); - _etdata = ABSOLUTE(.); - } > flash - - .tbss : { - _stbss = ABSOLUTE(.); - *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); - _etbss = ABSOLUTE(.); - } > flash - - _eronly = ABSOLUTE(.); - - /* The RAM vector table (if present) should lie at the beginning of SRAM */ - - .ram_vectors : { - *(.ram_vectors) - } > sram - - .data : ALIGN(4) { - _sdata = ABSOLUTE(.); - *(.data .data.*) - *(.gnu.linkonce.d.*) - CONSTRUCTORS - . = ALIGN(4); - _edata = ABSOLUTE(.); - } > sram AT > flash - - .bss : ALIGN(4) { - _sbss = ABSOLUTE(.); - *(.bss .bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - . = ALIGN(4); - _ebss = ABSOLUTE(.); - } > sram - - /* Stabs debugging sections. */ - - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_info 0 : { *(.debug_info) } - .debug_line 0 : { *(.debug_line) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_aranges 0 : { *(.debug_aranges) } -} diff --git a/boards/arm/stm32/nucleo-f302r8/src/CMakeLists.txt b/boards/arm/stm32/nucleo-f302r8/src/CMakeLists.txt deleted file mode 100644 index e5e905b763f6d..0000000000000 --- a/boards/arm/stm32/nucleo-f302r8/src/CMakeLists.txt +++ /dev/null @@ -1,62 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/nucleo-f302r8/src/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -set(SRCS stm32_boot.c stm32_bringup.c) - -if(CONFIG_ARCH_LEDS) - list(APPEND SRCS stm32_autoleds.c) -else() - list(APPEND SRCS stm32_userleds.c) -endif() - -if(CONFIG_ARCH_BUTTONS) - list(APPEND SRCS stm32_buttons.c) -endif() - -if(CONFIG_PWM) - list(APPEND SRCS stm32_pwm.c) -endif() - -if(CONFIG_NUCLEOF302R8_HIGHPRI) - list(APPEND SRCS stm32_highpri.c) -endif() - -if(CONFIG_BOARD_STM32_IHM07M1) - list(APPEND SRCS stm32_foc_ihm07m1.c) -else() - if(CONFIG_ADC) - list(APPEND SRCS stm32_adc.c) - endif() -endif() - -if(CONFIG_STM32_CAN) - if(CONFIG_STM32_CAN_CHARDRIVER) - list(APPEND SRCS stm32_can.c) - endif() - if(CONFIG_STM32_CAN_SOCKET) - list(APPEND SRCS stm32_cansock.c) - endif() -endif() - -target_sources(board PRIVATE ${SRCS}) - -set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/ld.script") diff --git a/boards/arm/stm32/nucleo-f302r8/src/Make.defs b/boards/arm/stm32/nucleo-f302r8/src/Make.defs deleted file mode 100644 index 7c9ce0e0b1fe8..0000000000000 --- a/boards/arm/stm32/nucleo-f302r8/src/Make.defs +++ /dev/null @@ -1,64 +0,0 @@ -############################################################################ -# boards/arm/stm32/nucleo-f302r8/src/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/Make.defs - -CSRCS = stm32_boot.c stm32_bringup.c - -ifeq ($(CONFIG_ARCH_LEDS),y) -CSRCS += stm32_autoleds.c -else -CSRCS += stm32_userleds.c -endif - -ifeq ($(CONFIG_ARCH_BUTTONS),y) -CSRCS += stm32_buttons.c -endif - -ifeq ($(CONFIG_PWM),y) -CSRCS += stm32_pwm.c -endif - -ifeq ($(CONFIG_NUCLEOF302R8_HIGHPRI),y) -CSRCS += stm32_highpri.c -endif - -ifeq ($(CONFIG_BOARD_STM32_IHM07M1),y) -CSRCS += stm32_foc_ihm07m1.c -else -ifeq ($(CONFIG_ADC),y) -CSRCS += stm32_adc.c -endif -endif - -ifeq ($(CONFIG_STM32_CAN),y) -ifeq ($(CONFIG_STM32_CAN_CHARDRIVER),y) -CSRCS += stm32_can.c -endif -ifeq ($(CONFIG_STM32_CAN_SOCKET),y) -CSRCS += stm32_cansock.c -endif -endif - -DEPPATH += --dep-path board -VPATH += :board -CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/nucleo-f302r8/src/stm32_adc.c b/boards/arm/stm32/nucleo-f302r8/src/stm32_adc.c deleted file mode 100644 index f4ec3e6b3179e..0000000000000 --- a/boards/arm/stm32/nucleo-f302r8/src/stm32_adc.c +++ /dev/null @@ -1,112 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f302r8/src/stm32_adc.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include - -#include "stm32.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#ifndef CONFIG_STM32_ADC1 -# error ADC1 support must be enabled -#endif - -#ifndef CONFIG_STM32_ADC1_DMA -# error ADC1 DMA support must be enabled -#endif - -#define ADC1_NCHANNELS 4 - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* Use CN8 pins 35, 36, 37 and 38 */ - -static const uint8_t g_adc1_chanlist[ADC1_NCHANNELS] = -{ - 6, 7, 8, 9 -}; - -static const uint32_t g_adc1_pinlist[ADC1_NCHANNELS] = -{ - GPIO_ADC1_IN6_0, /* PC0 */ - GPIO_ADC1_IN7_0, /* PC1 */ - GPIO_ADC1_IN8_0, /* PC2 */ - GPIO_ADC1_IN9_0, /* PC3 */ -}; - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_adc_setup - * - * Description: - * Initialize ADC and register the ADC driver. - * - ****************************************************************************/ - -int stm32_adc_setup(void) -{ - struct adc_dev_s *adc; - int ret; - int i; - - /* Configure the pins as analog inputs for the selected channels */ - - for (i = 0; i < ADC1_NCHANNELS; i++) - { - stm32_configgpio(g_adc1_pinlist[i]); - } - - /* Call stm32_adcinitialize() to get an instance of the ADC interface */ - - adc = stm32_adcinitialize(1, g_adc1_chanlist, ADC1_NCHANNELS); - if (adc == NULL) - { - aerr("ERROR: Failed to get ADC interface\n"); - return -ENODEV; - } - - /* Register the ADC driver at "/dev/adc0" */ - - ret = adc_register("/dev/adc0", adc); - if (ret < 0) - { - aerr("ERROR: adc_register failed: %d\n", ret); - return ret; - } - - return OK; -} diff --git a/boards/arm/stm32/nucleo-f302r8/src/stm32_autoleds.c b/boards/arm/stm32/nucleo-f302r8/src/stm32_autoleds.c deleted file mode 100644 index 0175408b56161..0000000000000 --- a/boards/arm/stm32/nucleo-f302r8/src/stm32_autoleds.c +++ /dev/null @@ -1,80 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f302r8/src/stm32_autoleds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include "stm32.h" -#include "nucleo-f302r8.h" - -#ifdef CONFIG_ARCH_LEDS - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_autoled_initialize - ****************************************************************************/ - -void board_autoled_initialize(void) -{ - /* Configure LED1 GPIO for output */ - - stm32_configgpio(GPIO_LED1); -} - -/**************************************************************************** - * Name: board_autoled_on - ****************************************************************************/ - -void board_autoled_on(int led) -{ - if (led == BOARD_LED1) - { - stm32_gpiowrite(GPIO_LED1, true); - } -} - -/**************************************************************************** - * Name: board_autoled_off - ****************************************************************************/ - -void board_autoled_off(int led) -{ - if (led == BOARD_LED1) - { - stm32_gpiowrite(GPIO_LED1, false); - } -} - -#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/nucleo-f302r8/src/stm32_boot.c b/boards/arm/stm32/nucleo-f302r8/src/stm32_boot.c deleted file mode 100644 index 36c4aa9905c0d..0000000000000 --- a/boards/arm/stm32/nucleo-f302r8/src/stm32_boot.c +++ /dev/null @@ -1,95 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f302r8/src/stm32_boot.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include "nucleo-f302r8.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_boardinitialize - * - * Description: - * All STM32 architectures must provide the following entry point. This - * entry point is called early in the initialization -- after all memory - * has been configured and mapped but before any devices have been - * initialized. - * - ****************************************************************************/ - -void stm32_boardinitialize(void) -{ - /* Configure on-board LEDs if LED support has been selected. */ - -#ifdef CONFIG_ARCH_LEDS - board_autoled_initialize(); -#endif -} - -/**************************************************************************** - * Name: board_late_initialize - * - * Description: - * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional - * initialization call will be performed in the boot-up sequence to a - * function called board_late_initialize(). board_late_initialize() will - * be called immediately after up_initialize() is called and just before - * the initial application is started. This additional initialization - * phase may be used, for example, to initialize board-specific device - * drivers. - * - ****************************************************************************/ - -#ifdef CONFIG_BOARD_LATE_INITIALIZE -void board_late_initialize(void) -{ - /* Perform board-specific initialization */ - - stm32_bringup(); -} -#endif diff --git a/boards/arm/stm32/nucleo-f302r8/src/stm32_bringup.c b/boards/arm/stm32/nucleo-f302r8/src/stm32_bringup.c deleted file mode 100644 index 4a878d66e0598..0000000000000 --- a/boards/arm/stm32/nucleo-f302r8/src/stm32_bringup.c +++ /dev/null @@ -1,188 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f302r8/src/stm32_bringup.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include - -#include - -#ifdef CONFIG_USERLED -# include -#endif - -#ifdef CONFIG_INPUT_BUTTONS -# include -#endif - -#ifdef CONFIG_SENSORS_QENCODER -# include "board_qencoder.h" -#endif - -#ifdef CONFIG_SENSORS_HALL3PHASE -# include "board_hall3ph.h" -#endif - -#include "nucleo-f302r8.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#undef HAVE_LEDS -#undef HAVE_DAC - -#if !defined(CONFIG_ARCH_LEDS) && defined(CONFIG_USERLED_LOWER) -# define HAVE_LEDS 1 -#endif - -#if defined(CONFIG_DAC) -# define HAVE_DAC 1 -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_bringup - * - * Description: - * Perform architecture-specific initialization - * - * CONFIG_BOARD_LATE_INITIALIZE=y : - * Called from board_late_initialize(). - * - ****************************************************************************/ - -int stm32_bringup(void) -{ - int ret; - -#ifdef CONFIG_INPUT_BUTTONS - /* Register the BUTTON driver */ - - ret = btn_lower_initialize("/dev/buttons"); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: btn_lower_initialize() failed: %d\n", ret); - } -#endif - -#ifdef HAVE_LEDS - /* Register the LED driver */ - - ret = userled_lower_initialize(LED_DRIVER_PATH); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: userled_lower_initialize() failed: %d\n", ret); - return ret; - } -#endif - -#ifdef CONFIG_PWM - /* Initialize PWM and register the PWM device. */ - - ret = stm32_pwm_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_pwm_setup() failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_STM32_FOC - /* Initialize and register the FOC device */ - - ret = stm32_foc_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_foc_setup failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_ADC - /* Initialize ADC and register the ADC driver. */ - - ret = stm32_adc_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_adc_setup failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_SENSORS_QENCODER - /* Initialize and register the qencoder driver */ - - ret = board_qencoder_initialize(0, CONFIG_NUCLEO_F302R8_QETIMER); - if (ret != OK) - { - syslog(LOG_ERR, - "ERROR: Failed to register the qencoder: %d\n", - ret); - return ret; - } -#endif - -#ifdef CONFIG_SENSORS_HALL3PHASE - /* Initialize and register the 3-phase Hall effect sensor driver */ - - ret = board_hall3ph_initialize(0, GPIO_HALL_PHA, GPIO_HALL_PHB, - GPIO_HALL_PHC); - if (ret != OK) - { - syslog(LOG_ERR, - "ERROR: Failed to register the hall : %d\n", - ret); - return ret; - } -#endif - -#ifdef CONFIG_STM32_CAN_CHARDRIVER - /* Initialize CAN and register the CAN driver. */ - - ret = stm32_can_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_can_setup failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_STM32_CAN_SOCKET - /* Initialize CAN socket interface */ - - ret = stm32_cansock_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_cansock_setup failed: %d\n", ret); - } -#endif - - UNUSED(ret); - return OK; -} diff --git a/boards/arm/stm32/nucleo-f302r8/src/stm32_buttons.c b/boards/arm/stm32/nucleo-f302r8/src/stm32_buttons.c deleted file mode 100644 index 581c45bda8e11..0000000000000 --- a/boards/arm/stm32/nucleo-f302r8/src/stm32_buttons.c +++ /dev/null @@ -1,113 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f302r8/src/stm32_buttons.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include "stm32.h" -#include "nucleo-f302r8.h" - -#ifdef CONFIG_ARCH_BUTTONS - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_button_initialize - * - * Description: - * board_button_initialize() must be called to initialize button - * resources. After that, board_buttons() may be called to collect the - * current state of all buttons or board_button_irq() may be called to - * register button interrupt handlers. - * - ****************************************************************************/ - -uint32_t board_button_initialize(void) -{ - /* Configure the single button as an input. NOTE that EXTI interrupts are - * also configured for the pin. - */ - - stm32_configgpio(GPIO_BTN_USER); - return NUM_BUTTONS; -} - -/**************************************************************************** - * Name: board_buttons - * - * Description: - * After board_button_initialize() has been called, board_buttons() may be - * called to collect the state of all buttons. board_buttons() returns an - * 32-bit unsigned integer with each bit associated with a button. See the - * BUTTON_*_BIT definitions in board.h for the meaning of each bit. - * - ****************************************************************************/ - -uint32_t board_buttons(void) -{ - /* Check the state of the USER button. A LOW value means that the key is - * pressed. - */ - - return stm32_gpioread(GPIO_BTN_USER) ? 0 : BUTTON_USER_BIT; -} - -/**************************************************************************** - * Name: board_button_irq - * - * Description: - * board_button_irq() may be called to register an interrupt handler that - * will be called when a button is depressed or released. The ID value is - * a button enumeration value that uniquely identifies a button resource. - * See the BUTTON_* definitions in board.h for the meaning of the - * enumeration value. - * - ****************************************************************************/ - -#ifdef CONFIG_ARCH_IRQBUTTONS -int board_button_irq(int id, xcpt_t irqhandler, void *arg) -{ - int ret = -EINVAL; - - if (id == BUTTON_USER) - { - ret = stm32_gpiosetevent(GPIO_BTN_USER, true, true, true, irqhandler, - arg); - } - - return ret; -} -#endif - -#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/stm32/nucleo-f302r8/src/stm32_can.c b/boards/arm/stm32/nucleo-f302r8/src/stm32_can.c deleted file mode 100644 index 3fae10a1a6a7b..0000000000000 --- a/boards/arm/stm32/nucleo-f302r8/src/stm32_can.c +++ /dev/null @@ -1,73 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f302r8/src/stm32_can.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include - -#include "stm32.h" - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_can_setup - * - * Description: - * Initialize CAN and register the CAN device - * - ****************************************************************************/ - -int stm32_can_setup(void) -{ - struct can_dev_s *can; - int ret; - - /* Call stm32_caninitialize() to get an instance of the CAN interface */ - - can = stm32_caninitialize(1); - if (can == NULL) - { - canerr("ERROR: Failed to get CAN interface\n"); - return -ENODEV; - } - - /* Register the CAN driver at "/dev/can0" */ - - ret = can_register("/dev/can0", can); - if (ret < 0) - { - canerr("ERROR: can_register failed: %d\n", ret); - return ret; - } - - return OK; -} diff --git a/boards/arm/stm32/nucleo-f302r8/src/stm32_cansock.c b/boards/arm/stm32/nucleo-f302r8/src/stm32_cansock.c deleted file mode 100644 index 7ccf0ad686be4..0000000000000 --- a/boards/arm/stm32/nucleo-f302r8/src/stm32_cansock.c +++ /dev/null @@ -1,59 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f302r8/src/stm32_cansock.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include "stm32_can.h" - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_cansock_setup - * - * Description: - * Initialize CAN socket interface - * - ****************************************************************************/ - -int stm32_cansock_setup(void) -{ - int ret; - - /* Call stm32_caninitialize() to get an instance of the CAN interface */ - - ret = stm32_cansockinitialize(1); - if (ret < 0) - { - canerr("ERROR: Failed to get CAN interface %d\n", ret); - return ret; - } - - return OK; -} diff --git a/boards/arm/stm32/nucleo-f302r8/src/stm32_foc_ihm07m1.c b/boards/arm/stm32/nucleo-f302r8/src/stm32_foc_ihm07m1.c deleted file mode 100644 index 3d061622c9000..0000000000000 --- a/boards/arm/stm32/nucleo-f302r8/src/stm32_foc_ihm07m1.c +++ /dev/null @@ -1,183 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f302r8/src/stm32_foc_ihm07m1.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "stm32_ihm07m1.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#define CURRENT_SAMPLE_TIME ADC_SMPR_19p5 -#define VBUS_SAMPLE_TIME ADC_SMPR_601p5 -#define POT_SAMPLE_TIME ADC_SMPR_601p5 - -/* ADC1 channels used in this example */ - -#define ADC1_INJECTED (CONFIG_MOTOR_FOC_SHUNTS) - -#ifdef CONFIG_BOARD_STM32_IHM07M1_VBUS -# define IHM07M1_VBUS 1 -#else -# define IHM07M1_VBUS 0 -#endif - -#ifdef CONFIG_BOARD_STM32_IHM07M1_POT -# define IHM07M1_POT 1 -#else -# define IHM07M1_POT 0 -#endif - -#define ADC1_REGULAR (IHM07M1_VBUS + IHM07M1_POT) -#define ADC1_NCHANNELS (ADC1_INJECTED + ADC1_REGULAR) - -/* Check ADC1 configuration */ - -#if ADC1_INJECTED != CONFIG_STM32_ADC1_INJECTED_CHAN -# error -#endif - -#if CONFIG_STM32_ADC1_RESOLUTION != 0 -# error -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* FOC ADC configuration: - * - Current Phase V -> ADC1 INJ1 -> ADC1_IN1 (PA0) - * - Current Phase U -> ADC1 INJ2 -> ADC1_IN7 (PC1) - * - Current Phase W -> ADC1 INJ3 -> ADC1_IN6 (PC0) - * optional: - * - VBUS -> ADC1 REG -> ADC1_IN2 (PA1) - * - POT -> ADC1 REG -> ADC1_IN12 (PB1) - * - * TIM1 PWM configuration: - * - Phase U high -> TIM1_CH1 (PA8) - * - Phase V high -> TIM1_CH2 (PA9) - * - Phase W high -> TIM1_CH3 (PA10) - * - */ - -static uint8_t g_adc1_chan[] = -{ -#ifdef CONFIG_BOARD_STM32_IHM07M1_VBUS - 2, /* ADC1 REG - VBUS */ -#endif -#ifdef CONFIG_BOARD_STM32_IHM07M1_POT - 12, /* ADC1 REG - POT */ -#endif - 1, /* ADC1 INJ1 - PHASE 1 */ -#if CONFIG_MOTOR_FOC_SHUNTS == 3 - 7, /* ADC1 INJ2 - PHASE 2 */ - 6, /* ADC1 INJ3 - PHASE 3 */ -#endif -}; - -static uint32_t g_adc1_pins[] = -{ -#ifdef CONFIG_BOARD_STM32_IHM07M1_VBUS - GPIO_ADC1_IN2_0, -#endif -#ifdef CONFIG_BOARD_STM32_IHM07M1_POT - GPIO_ADC1_IN12_0, -#endif - GPIO_ADC1_IN1_0, -#if CONFIG_MOTOR_FOC_SHUNTS > 1 - GPIO_ADC1_IN7_0, -#endif -#if CONFIG_MOTOR_FOC_SHUNTS > 2 - GPIO_ADC1_IN6_0, -#endif -}; - -/* ADC1 sample time configuration */ - -static adc_channel_t g_adc1_stime[] = -{ -#ifdef CONFIG_BOARD_STM32_IHM07M1_VBUS - { - .channel = 2, - .sample_time = VBUS_SAMPLE_TIME - }, -#endif -#ifdef CONFIG_BOARD_STM32_IHM07M1_POT - { - .channel = 12, - .sample_time = POT_SAMPLE_TIME - }, -#endif - { - .channel = 1, - .sample_time = CURRENT_SAMPLE_TIME - }, -#if CONFIG_MOTOR_FOC_SHUNTS > 1 - { - .channel = 7, - .sample_time = CURRENT_SAMPLE_TIME - }, -#endif -#if CONFIG_MOTOR_FOC_SHUNTS > 2 - { - .channel = 6, - .sample_time = CURRENT_SAMPLE_TIME - }, -#endif -}; - -/* Board specific ADC configuration for FOC */ - -static struct stm32_foc_adc_s g_adc_cfg = -{ - .chan = g_adc1_chan, - .pins = g_adc1_pins, - .stime = g_adc1_stime, - .nchan = ADC1_NCHANNELS, - .regch = ADC1_REGULAR, - .intf = 1 -}; - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_foc_setup - * - * Description: - * Initialize FOC driver. - * - * Returned Value: - * 0 on success, a negated errno value on failure - * - ****************************************************************************/ - -int stm32_foc_setup(void) -{ - return board_ihm07m1_initialize(&g_adc_cfg); -} diff --git a/boards/arm/stm32/nucleo-f302r8/src/stm32_highpri.c b/boards/arm/stm32/nucleo-f302r8/src/stm32_highpri.c deleted file mode 100644 index a7775f2b0ece9..0000000000000 --- a/boards/arm/stm32/nucleo-f302r8/src/stm32_highpri.c +++ /dev/null @@ -1,544 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f302r8/src/stm32_highpri.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include - -#include -#include - -#include "arm_internal.h" -#include "ram_vectors.h" - -#include "stm32_pwm.h" -#include "stm32_adc.h" -#include "stm32_dma.h" - -#include - -#ifdef CONFIG_NUCLEOF302R8_HIGHPRI - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -#ifndef CONFIG_ARCH_HIPRI_INTERRUPT -# error CONFIG_ARCH_HIPRI_INTERRUPT is required -#endif - -#ifndef CONFIG_ARCH_RAMVECTORS -# error CONFIG_ARCH_RAMVECTORS is required -#endif - -#ifndef CONFIG_ARCH_IRQPRIO -# error CONFIG_ARCH_IRQPRIO is required -#endif - -#ifndef CONFIG_ARCH_FPU -# warning Set CONFIG_ARCH_FPU for hardware FPU support -#endif - -#ifdef CONFIG_STM32_ADC1_DMA -# if defined(CONFIG_STM32_TIM1_PWM) -# define HIGHPRI_HAVE_TIM1 -# endif -# if (CONFIG_STM32_ADC1_DMA_CFG != 1) -# error ADC1 DMA must be configured in Circular Mode -# endif -# if !defined(HIGHPRI_HAVE_TIM1) -# error "Needs TIM1 to trigger ADC DMA" -# endif -#endif - -#if (CONFIG_STM32_ADC1_INJECTED_CHAN > 0) -# if (CONFIG_STM32_ADC1_INJECTED_CHAN > 2) -# error Max 2 injected channels supported for now -# else -# define HIGHPRI_HAVE_INJECTED -# endif -#endif - -#ifdef HIGHPRI_HAVE_INJECTED -# define INJ_NCHANNELS CONFIG_STM32_ADC1_INJECTED_CHAN -#else -# define INJ_NCHANNELS (0) -#endif - -#ifndef CONFIG_STM32_ADC1_DMA -# define REG_NCHANNELS (1) -#else -# define REG_NCHANNELS (3) -#endif - -#define ADC1_NCHANNELS (REG_NCHANNELS + INJ_NCHANNELS) - -#define DEV1_PORT (1) -#define DEV1_NCHANNELS ADC1_NCHANNELS -#define ADC_REF_VOLTAGE (3.3f) -#define ADC_VAL_MAX (4095) - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/* High priority example private data */ - -struct highpri_s -{ - struct stm32_adc_dev_s *adc1; -#ifdef HIGHPRI_HAVE_TIM1 - struct stm32_pwm_dev_s *pwm; -#endif - volatile uint32_t cntr1; - volatile uint32_t cntr2; - volatile uint8_t current; - uint16_t r_val[REG_NCHANNELS]; - float r_volt[REG_NCHANNELS]; -#ifdef HIGHPRI_HAVE_INJECTED - uint16_t j_val[INJ_NCHANNELS]; - float j_volt[INJ_NCHANNELS]; -#endif - bool lock; -}; - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* ADC channel list */ - -static const uint8_t g_chanlist1[DEV1_NCHANNELS] = -{ - 1, -#ifdef CONFIG_STM32_ADC1_DMA - 2, - 11, -#endif -#if INJ_NCHANNELS > 0 - 7, -#endif -#if INJ_NCHANNELS > 1 - 6 -#endif -}; - -/* Configurations of pins used by ADC channel */ - -static const uint32_t g_pinlist1[DEV1_NCHANNELS] = -{ - GPIO_ADC1_IN1_0, /* PA0/A0 */ -#ifdef CONFIG_STM32_ADC1_DMA - GPIO_ADC1_IN2_0, /* PA1/A1 */ - GPIO_ADC1_IN11_0, /* PB0/A3 */ -#endif -#if INJ_NCHANNELS > 0 - GPIO_ADC1_IN7_0, /* PC1/A4 */ -#endif -#if INJ_NCHANNELS > 1 - GPIO_ADC1_IN6_0 /* PC0/A5 */ -#endif -}; - -static struct highpri_s g_highpri; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: adc12_handler - * - * Description: - * This is the handler for the high speed ADC interrupt. - * - ****************************************************************************/ - -#if !defined(CONFIG_STM32_ADC1_DMA) || defined(HIGHPRI_HAVE_INJECTED) -void adc12_handler(void) -{ - struct stm32_adc_dev_s *adc = g_highpri.adc1; - float ref = ADC_REF_VOLTAGE; - float bit = ADC_VAL_MAX; - uint32_t pending; -#ifdef HIGHPRI_HAVE_INJECTED - int i = 0; -#endif - - /* Get pending ADC interrupts */ - - pending = STM32_ADC_INT_GET(adc); - - if (g_highpri.lock == true) - { - goto irq_out; - } - -#ifndef CONFIG_STM32_ADC1_DMA - /* Regular channel end of conversion */ - - if (pending & ADC_ISR_EOC) - { - /* Increase regular sequence counter */ - - g_highpri.cntr1 += 1; - - /* Get regular data */ - - g_highpri.r_val[g_highpri.current] = STM32_ADC_REGDATA_GET(adc); - - /* Do some floating point operations */ - - g_highpri.r_volt[g_highpri.current] = - (float)g_highpri.r_val[g_highpri.current] * ref / bit; - - if (g_highpri.current >= REG_NCHANNELS - 1) - { - g_highpri.current = 0; - } - else - { - g_highpri.current += 1; - } - } -#endif - -#ifdef HIGHPRI_HAVE_INJECTED - /* Injected channel end of sequence */ - - if (pending & ADC_ISR_JEOS) - { - /* Increase injected sequence counter */ - - g_highpri.cntr2 += 1; - - /* Get injected channels */ - - for (i = 0; i < INJ_NCHANNELS; i += 1) - { - g_highpri.j_val[i] = STM32_ADC_INJDATA_GET(adc, i); - } - - /* Do some floating point operations */ - - for (i = 0; i < INJ_NCHANNELS; i += 1) - { - g_highpri.j_volt[i] = (float)g_highpri.j_val[i] * ref / bit; - } - } -#endif - -irq_out: - - /* Clear ADC pending interrupts */ - - STM32_ADC_INT_ACK(adc, pending); -} -#endif - -/**************************************************************************** - * Name: dmach1_handler - * - * Description: - * This is the handler for the high speed ADC interrupt using DMA transfer. - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_ADC1_DMA -void dma1ch1_handler(void) -{ - float ref = ADC_REF_VOLTAGE; - float bit = ADC_VAL_MAX; - uint32_t pending; - int i; - - pending = stm32_dma_intget(STM32_DMA1_CHAN1); - - if (g_highpri.lock == true) - { - goto irq_out; - } - - /* Increase regular sequence counter */ - - g_highpri.cntr1 += 1; - - for (i = 0; i < REG_NCHANNELS; i += 1) - { - /* Do some floating point operations */ - - g_highpri.r_volt[i] = (float)g_highpri.r_val[i] * ref / bit; - } - -irq_out: - - /* Clear DMA pending interrupts */ - - stm32_dma_intack(STM32_DMA1_CHAN1, pending); -} -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: highpri_main - * - * Description: - * Main entry point in into the high priority interrupt test. - * - ****************************************************************************/ - -int highpri_main(int argc, char *argv[]) -{ -#ifdef HIGHPRI_HAVE_TIM1 - struct stm32_pwm_dev_s *pwm1; -#endif - struct adc_dev_s *adc1; - struct highpri_s *highpri; - int ret; - int i; - - highpri = &g_highpri; - - /* Initialize highpri structure */ - - memset(highpri, 0, sizeof(struct highpri_s)); - - printf("\nhighpri_main: Started\n"); - - /* Configure the pins as analog inputs for the selected channels */ - - for (i = 0; i < DEV1_NCHANNELS; i++) - { - stm32_configgpio(g_pinlist1[i]); - } - - /* Initialize ADC driver */ - - adc1 = stm32_adcinitialize(DEV1_PORT, g_chanlist1, DEV1_NCHANNELS); - if (adc1 == NULL) - { - aerr("ERROR: Failed to get ADC interface 1\n"); - ret = EXIT_FAILURE; - goto errout; - } - - highpri->adc1 = (struct stm32_adc_dev_s *)adc1->ad_priv; - -#ifdef HIGHPRI_HAVE_TIM1 - /* Initialize TIM1 */ - - pwm1 = (struct stm32_pwm_dev_s *) stm32_pwminitialize(1); - if (pwm1 == NULL) - { - printf("ERROR: Failed to get PWM1 interface\n"); - ret = EXIT_FAILURE; - goto errout; - } - - highpri->pwm = pwm1; - - /* Setup PWM device */ - - PWM_SETUP(pwm1); - - /* Set timer frequency */ - - PWM_FREQ_UPDATE(pwm1, 1000); - - /* Set CCR1 */ - - PWM_CCR_UPDATE(pwm1, 1, 0x0f00); - - /* Enable TIM1 OUT1 */ - - PWM_OUTPUTS_ENABLE(pwm1, STM32_PWM_OUT1, true); - -#ifdef CONFIG_DEBUG_PWM_INFO - /* Print debug */ - - PWM_DUMP_REGS(pwm1); -#endif - -#endif /* HIGHPRI_HAVE_TIM1 */ - -#if !defined(CONFIG_STM32_ADC1_DMA) || defined(HIGHPRI_HAVE_INJECTED) - /* Attach ADC12 ram vector if no DMA or injected channels support */ - - ret = arm_ramvec_attach(STM32_IRQ_ADC12, adc12_handler); - if (ret < 0) - { - fprintf(stderr, "highpri_main: ERROR: arm_ramvec_attach failed: %d\n", - ret); - ret = EXIT_FAILURE; - goto errout; - } - - /* Set the priority of the ADC12 interrupt vector */ - - ret = up_prioritize_irq(STM32_IRQ_ADC12, NVIC_SYSH_HIGH_PRIORITY); - if (ret < 0) - { - fprintf(stderr, "highpri_main: ERROR: up_prioritize_irq failed: %d\n", - ret); - ret = EXIT_FAILURE; - goto errout; - } - - up_enable_irq(STM32_IRQ_ADC12); -#endif - -#ifdef CONFIG_STM32_ADC1_DMA - /* Attach DMA1 CH1 ram vector if DMA */ - - ret = arm_ramvec_attach(STM32_IRQ_DMA1CH1, dma1ch1_handler); - if (ret < 0) - { - fprintf(stderr, "highpri_main: ERROR: arm_ramvec_attach failed: %d\n", - ret); - ret = EXIT_FAILURE; - goto errout; - } - - /* Set the priority of the DMA1CH1 interrupt vector */ - - ret = up_prioritize_irq(STM32_IRQ_DMA1CH1, NVIC_SYSH_HIGH_PRIORITY); - if (ret < 0) - { - fprintf(stderr, "highpri_main: ERROR: up_prioritize_irq failed: %d\n", - ret); - ret = EXIT_FAILURE; - goto errout; - } - - up_enable_irq(STM32_IRQ_DMA1CH1); -#endif - - /* Setup ADC hardware */ - - adc1->ad_ops->ao_setup(adc1); - - /* Configure regular channels trigger to T1CC1 */ - - STM32_ADC_EXTCFG_SET(highpri->adc1, - ADC1_EXTSEL_T1CC1 | ADC_EXTREG_EXTEN_DEFAULT); - -#ifndef CONFIG_STM32_ADC1_DMA - /* Enable ADC regular conversion interrupts if no DMA */ - - STM32_ADC_INT_ENABLE(highpri->adc1, ADC_IER_EOC); -#else - /* Register ADC buffer for DMA transfer */ - - STM32_ADC_REGBUF_REGISTER(highpri->adc1, g_highpri.r_val, REG_NCHANNELS); -#endif - -#ifdef HIGHPRI_HAVE_INJECTED - /* Enable ADC injected sequence end interrupts */ - - STM32_ADC_INT_ENABLE(highpri->adc1, ADC_IER_JEOS); -#endif - -#ifdef HIGHPRI_HAVE_TIM1 - /* Enable timer counter after ADC configuration */ - - PWM_TIM_ENABLE(pwm1, true); -#endif - - while (1) - { -#ifndef CONFIG_STM32_ADC1_DMA - /* Software trigger for regular sequence */ - - adc1->ad_ops->ao_ioctl(adc1, IO_TRIGGER_REG, 0); - - nxsched_usleep(100); -#endif - -#ifdef HIGHPRI_HAVE_INJECTED - /* Software trigger for injected sequence */ - - adc1->ad_ops->ao_ioctl(adc1, IO_TRIGGER_INJ, 0); - - nxsched_usleep(100); -#endif - /* Lock global data */ - - g_highpri.lock = true; - -#ifndef CONFIG_STM32_ADC1_DMA - printf("%" PRId32 " [%d] %0.3fV\n", g_highpri.cntr1, g_highpri.current, - g_highpri.r_volt[g_highpri.current]); -#else - printf("%" PRId32 " ", g_highpri.cntr1); - - for (i = 0; i < REG_NCHANNELS; i += 1) - { - printf("r:[%d] %0.3fV, ", i, g_highpri.r_volt[i]); - } - - printf("\n"); -#endif - -#ifdef HIGHPRI_HAVE_INJECTED - /* Print data from injected channels */ - - printf("%" PRId32 " ", g_highpri.cntr2); - - for (i = 0; i < INJ_NCHANNELS; i += 1) - { - printf("j:[%d] %0.3fV, ", i, g_highpri.j_volt[i]); - } - - printf("\n"); -#endif - /* Unlock global data */ - - g_highpri.lock = false; - - nxsched_sleep(1); - } - -errout: - return ret; -} - -#endif /* CONFIG_NUCLEOF302R8_HIGHPRI */ diff --git a/boards/arm/stm32/nucleo-f302r8/src/stm32_pwm.c b/boards/arm/stm32/nucleo-f302r8/src/stm32_pwm.c deleted file mode 100644 index 49997999a1c71..0000000000000 --- a/boards/arm/stm32/nucleo-f302r8/src/stm32_pwm.c +++ /dev/null @@ -1,110 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f302r8/src/stm32_pwm.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32_pwm.h" -#include "nucleo-f302r8.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -#define HAVE_PWM 1 - -#ifndef CONFIG_PWM -# undef HAVE_PWM -#endif - -#ifndef CONFIG_STM32_TIM1 -# undef HAVE_PWM -#endif - -#ifndef CONFIG_STM32_TIM1_PWM -# undef HAVE_PWM -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_pwm_setup - * - * Description: - * Initialize PWM and register the PWM device. - * - ****************************************************************************/ - -int stm32_pwm_setup(void) -{ -#ifdef HAVE_PWM - static bool initialized = false; - struct pwm_lowerhalf_s *pwm; - int ret; - - /* Have we already initialized? */ - - if (!initialized) - { - /* Call stm32_pwminitialize() to get an instance of the PWM interface */ - - pwm = stm32_pwminitialize(NUCLEOF302R8_PWMTIMER); - if (!pwm) - { - tmrerr("ERROR: Failed to get the STM32 PWM lower half\n"); - return -ENODEV; - } - - /* Register the PWM driver at "/dev/pwm0" */ - - ret = pwm_register("/dev/pwm0", pwm); - if (ret < 0) - { - tmrerr("ERROR: pwm_register failed: %d\n", ret); - return ret; - } - - /* Now we are initialized */ - - initialized = true; - } - - return OK; -#else - return -ENODEV; -#endif -} diff --git a/boards/arm/stm32/nucleo-f302r8/src/stm32_userleds.c b/boards/arm/stm32/nucleo-f302r8/src/stm32_userleds.c deleted file mode 100644 index 1895649936c1b..0000000000000 --- a/boards/arm/stm32/nucleo-f302r8/src/stm32_userleds.c +++ /dev/null @@ -1,77 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f302r8/src/stm32_userleds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include - -#include "stm32.h" -#include "nucleo-f302r8.h" - -#ifndef CONFIG_ARCH_LEDS - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_userled_initialize - ****************************************************************************/ - -uint32_t board_userled_initialize(void) -{ - /* Configure LED1 GPIO for output */ - - stm32_configgpio(GPIO_LED1); - return BOARD_NLEDS; -} - -/**************************************************************************** - * Name: board_userled - ****************************************************************************/ - -void board_userled(int led, bool ledon) -{ - if (led == BOARD_LED1) - { - stm32_gpiowrite(GPIO_LED1, ledon); - } -} - -/**************************************************************************** - * Name: board_userled_all - ****************************************************************************/ - -void board_userled_all(uint32_t ledset) -{ - stm32_gpiowrite(GPIO_LED1, (ledset & BOARD_LED1_BIT) != 0); -} - -#endif /* !CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/nucleo-f303re/CMakeLists.txt b/boards/arm/stm32/nucleo-f303re/CMakeLists.txt deleted file mode 100644 index fb2ec37234ebb..0000000000000 --- a/boards/arm/stm32/nucleo-f303re/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/nucleo-f303re/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32/nucleo-f303re/configs/adc/defconfig b/boards/arm/stm32/nucleo-f303re/configs/adc/defconfig deleted file mode 100644 index ea4831dc3fd30..0000000000000 --- a/boards/arm/stm32/nucleo-f303re/configs/adc/defconfig +++ /dev/null @@ -1,47 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -CONFIG_ADC=y -CONFIG_ANALOG=y -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="nucleo-f303re" -CONFIG_ARCH_BOARD_NUCLEO_F303RE=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F303RE=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=6522 -CONFIG_BUILTIN=y -CONFIG_EXAMPLES_ADC=y -CONFIG_EXAMPLES_ADC_GROUPSIZE=3 -CONFIG_EXAMPLES_ADC_SWTRIG=y -CONFIG_IDLETHREAD_STACKSIZE=2048 -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=65536 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=27 -CONFIG_START_YEAR=2013 -CONFIG_STM32_ADC1=y -CONFIG_STM32_ADC1_DMA=y -CONFIG_STM32_ADC3=y -CONFIG_STM32_DMA1=y -CONFIG_STM32_FORCEPOWER=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_TIM1=y -CONFIG_STM32_TIM1_ADC=y -CONFIG_STM32_USART2=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/nucleo-f303re/configs/can/defconfig b/boards/arm/stm32/nucleo-f303re/configs/can/defconfig deleted file mode 100644 index 4c85a315731f0..0000000000000 --- a/boards/arm/stm32/nucleo-f303re/configs/can/defconfig +++ /dev/null @@ -1,39 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_DEV_CONSOLE is not set -# CONFIG_SERIAL is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="nucleo-f303re" -CONFIG_ARCH_BOARD_NUCLEO_F303RE=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F303RE=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARDCTL=y -CONFIG_BOARD_LOOPSPERMSEC=6522 -CONFIG_EXAMPLES_CAN=y -CONFIG_IDLETHREAD_STACKSIZE=2048 -CONFIG_INIT_ENTRYPOINT="can_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_MM_REGIONS=2 -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=65536 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=27 -CONFIG_START_YEAR=2013 -CONFIG_STM32_CAN1=y -CONFIG_STM32_CAN_TSEG1=15 -CONFIG_STM32_CAN_TSEG2=2 -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_SYSLOG_NONE=y -CONFIG_TASK_NAME_SIZE=0 diff --git a/boards/arm/stm32/nucleo-f303re/configs/hello/defconfig b/boards/arm/stm32/nucleo-f303re/configs/hello/defconfig deleted file mode 100644 index a51fa54aaa0b7..0000000000000 --- a/boards/arm/stm32/nucleo-f303re/configs/hello/defconfig +++ /dev/null @@ -1,35 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="nucleo-f303re" -CONFIG_ARCH_BOARD_NUCLEO_F303RE=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F303RE=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=6522 -CONFIG_DEBUG_SYMBOLS=y -CONFIG_EXAMPLES_HELLO=y -CONFIG_IDLETHREAD_STACKSIZE=2048 -CONFIG_INIT_ENTRYPOINT="hello_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_MM_REGIONS=2 -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=65536 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=27 -CONFIG_START_YEAR=2013 -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_USART2=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/nucleo-f303re/configs/nsh/defconfig b/boards/arm/stm32/nucleo-f303re/configs/nsh/defconfig deleted file mode 100644 index 95b091e30b498..0000000000000 --- a/boards/arm/stm32/nucleo-f303re/configs/nsh/defconfig +++ /dev/null @@ -1,35 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="nucleo-f303re" -CONFIG_ARCH_BOARD_NUCLEO_F303RE=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F303RE=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=6522 -CONFIG_DEBUG_SYMBOLS=y -CONFIG_IDLETHREAD_STACKSIZE=2048 -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_MM_REGIONS=2 -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=65536 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=27 -CONFIG_START_YEAR=2013 -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_USART2=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/nucleo-f303re/configs/nxlines/defconfig b/boards/arm/stm32/nucleo-f303re/configs/nxlines/defconfig deleted file mode 100644 index 8bacca4eb3fb6..0000000000000 --- a/boards/arm/stm32/nucleo-f303re/configs/nxlines/defconfig +++ /dev/null @@ -1,47 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_DEV_CONSOLE is not set -# CONFIG_NXFONTS_DISABLE_16BPP is not set -# CONFIG_NX_DISABLE_16BPP is not set -# CONFIG_SERIAL is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="nucleo-f303re" -CONFIG_ARCH_BOARD_NUCLEO_F303RE=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F303RE=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=6522 -CONFIG_CAN=y -CONFIG_EXAMPLES_NXLINES=y -CONFIG_IDLETHREAD_STACKSIZE=2048 -CONFIG_INIT_ENTRYPOINT="nxlines_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LCD=y -CONFIG_LCD_SSD1351=y -CONFIG_MM_REGIONS=2 -CONFIG_MQ_MAXMSGSIZE=64 -CONFIG_NX=y -CONFIG_NXFONT_MONO5X8=y -CONFIG_NXSTART_EXTERNINIT=y -CONFIG_NX_BLOCKING=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAMLOG=y -CONFIG_RAMLOG_SYSLOG=y -CONFIG_RAM_SIZE=65536 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=27 -CONFIG_START_YEAR=2013 -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_SPI1=y -CONFIG_TASK_NAME_SIZE=0 diff --git a/boards/arm/stm32/nucleo-f303re/configs/pwm/defconfig b/boards/arm/stm32/nucleo-f303re/configs/pwm/defconfig deleted file mode 100644 index 7c449ee522c3e..0000000000000 --- a/boards/arm/stm32/nucleo-f303re/configs/pwm/defconfig +++ /dev/null @@ -1,46 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="nucleo-f303re" -CONFIG_ARCH_BOARD_NUCLEO_F303RE=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F303RE=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=6522 -CONFIG_BUILTIN=y -CONFIG_EXAMPLES_PWM=y -CONFIG_IDLETHREAD_STACKSIZE=2048 -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_MM_REGIONS=2 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_PWM=y -CONFIG_PWM_NCHANNELS=2 -CONFIG_RAM_SIZE=65536 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=27 -CONFIG_START_YEAR=2013 -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_PWM_MULTICHAN=y -CONFIG_STM32_TIM3=y -CONFIG_STM32_TIM3_CH1OUT=y -CONFIG_STM32_TIM3_CH2OUT=y -CONFIG_STM32_TIM3_CHANNEL1=y -CONFIG_STM32_TIM3_CHANNEL2=y -CONFIG_STM32_TIM3_PWM=y -CONFIG_STM32_USART2=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/nucleo-f303re/configs/serialrx/defconfig b/boards/arm/stm32/nucleo-f303re/configs/serialrx/defconfig deleted file mode 100644 index 16397524983bf..0000000000000 --- a/boards/arm/stm32/nucleo-f303re/configs/serialrx/defconfig +++ /dev/null @@ -1,38 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_DEV_CONSOLE is not set -CONFIG_ANALOG=y -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="nucleo-f303re" -CONFIG_ARCH_BOARD_NUCLEO_F303RE=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F303RE=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARDCTL=y -CONFIG_BOARD_LOOPSPERMSEC=6522 -CONFIG_EXAMPLES_SERIALRX=y -CONFIG_EXAMPLES_SERIALRX_PRINTSTR=y -CONFIG_IDLETHREAD_STACKSIZE=2048 -CONFIG_INIT_ENTRYPOINT="serialrx_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_MM_REGIONS=2 -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=65536 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=27 -CONFIG_START_YEAR=2013 -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_UART4=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_UART4_BAUD=9600 diff --git a/boards/arm/stm32/nucleo-f303re/include/board.h b/boards/arm/stm32/nucleo-f303re/include/board.h deleted file mode 100644 index d5cb48ca3b4f8..0000000000000 --- a/boards/arm/stm32/nucleo-f303re/include/board.h +++ /dev/null @@ -1,241 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f303re/include/board.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __BOARDS_ARM_STM32_NUCLEO_F303RE_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32_NUCLEO_F303RE_INCLUDE_BOARD_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#ifndef __ASSEMBLY__ -# include -# include -#endif - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Clocking *****************************************************************/ - -/* HSI - Internal 8 MHz RC Oscillator - * LSI - 32 KHz RC - * HSE - 8 MHz from MCO output of ST-LINK - * LSE - 32.768 kHz - */ - -#define STM32_BOARD_XTAL 8000000ul /* X1 on board */ - -#define STM32_HSEBYP_ENABLE -#define STM32_HSI_FREQUENCY 8000000ul -#define STM32_LSI_FREQUENCY 40000 /* Between 30kHz and 60kHz */ -#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL -#define STM32_LSE_FREQUENCY 32768 /* X2 on board */ - -/* PLL source is HSE/1, - * PLL multiplier is 9: - * PLL frequency is 8MHz (XTAL) x 9 = 72MHz - */ - -#define STM32_CFGR_PLLSRC RCC_CFGR_PLLSRC -#define STM32_CFGR_PLLXTPRE 0 -#define STM32_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx9 -#define STM32_PLL_FREQUENCY (9*STM32_BOARD_XTAL) - -/* Use the PLL and set the SYSCLK source to be the PLL */ - -#define STM32_SYSCLK_SW RCC_CFGR_SW_PLL -#define STM32_SYSCLK_SWS RCC_CFGR_SWS_PLL -#define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY - -/* AHB clock (HCLK) is SYSCLK (72MHz) */ - -#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK -#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY - -/* APB2 clock (PCLK2) is HCLK (72MHz) */ - -#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK -#define STM32_PCLK2_FREQUENCY STM32_HCLK_FREQUENCY -#define STM32_APB2_CLKIN (STM32_PCLK2_FREQUENCY) /* Timers 1 and 8, 15-17 */ - -/* APB2 timers 1 and 8, 15-17 will receive PCLK2. */ - -/* Timers driven from APB2 will be PCLK2 */ - -#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB1_TIM15_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB1_TIM16_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB1_TIM17_CLKIN (STM32_PCLK2_FREQUENCY) - -/* APB1 clock (PCLK1) is HCLK/2 (36MHz) */ - -#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd2 -#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/2) - -/* APB1 timers 2-7 will be twice PCLK1 */ - -#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) - -/* USB divider -- Divide PLL clock by 1.5 */ - -#define STM32_CFGR_USBPRE 0 - -/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx - * otherwise frequency is 2xAPBx. - * Note: TIM1,8 are on APB2, others on APB1 - */ - -#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM2_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM3_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM4_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM5_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM6_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM7_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY - -/* LED definitions **********************************************************/ - -/* The Nucleo F303RE board has three LEDs. Two of these are controlled by - * logic on the board and are not available for software control: - * - * LD1 COM: LD1 default status is red. LD1 turns to green to indicate that - * communications are in progress between the PC and the - * ST-LINK/V2-1. - * LD3 PWR: red LED indicates that the board is powered. - * - * And one can be controlled by software: - * - * User LD2: green LED is a user LED connected to the I/O PA5 of the - * STM32F303RET6. - * - * If CONFIG_ARCH_LEDS is not defined, then the user can control the LED in - * any way. The following definition is used to access the LED. - */ - -/* LED index values for use with board_userled() */ - -#define BOARD_LED1 0 /* User LD2 */ -#define BOARD_NLEDS 1 - -/* LED bits for use with board_userled_all() */ - -#define BOARD_LED1_BIT (1 << BOARD_LED1) - -/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the LED on board - * the Nucleo F303RE. The following definitions describe how NuttX controls - * the LED: - * - * SYMBOL Meaning LED1 state - * ------------------ ----------------------- ---------- - * LED_STARTED NuttX has been started OFF - * LED_HEAPALLOCATE Heap has been allocated OFF - * LED_IRQSENABLED Interrupts enabled OFF - * LED_STACKCREATED Idle stack created ON - * LED_INIRQ In an interrupt No change - * LED_SIGNAL In a signal handler No change - * LED_ASSERTION An assertion failed No change - * LED_PANIC The system has crashed Blinking - * LED_IDLE STM32 is in sleep mode Not used - */ - -#define LED_STARTED 0 -#define LED_HEAPALLOCATE 0 -#define LED_IRQSENABLED 0 -#define LED_STACKCREATED 1 -#define LED_INIRQ 2 -#define LED_SIGNAL 2 -#define LED_ASSERTION 2 -#define LED_PANIC 1 - -/* Button definitions *******************************************************/ - -/* The Nucleo F303RE supports two buttons; only one button is controllable - * by software: - * - * B1 USER: user button connected to the I/O PC13 of the STM32F303RET6. - * B2 RESET: push button connected to NRST is used to RESET the - * STM32F303RET6. - */ - -#define BUTTON_USER 0 -#define NUM_BUTTONS 1 - -#define BUTTON_USER_BIT (1 << BUTTON_USER) - -/* Alternate function pin selections ****************************************/ - -/* CAN */ - -#define GPIO_CAN1_RX (GPIO_CAN_RX_2|GPIO_SPEED_25MHz) -#define GPIO_CAN1_TX (GPIO_CAN_TX_2|GPIO_SPEED_25MHz) - -/* I2C */ - -#define GPIO_I2C1_SCL (GPIO_I2C1_SCL_3|GPIO_SPEED_50MHz) -#define GPIO_I2C1_SDA (GPIO_I2C1_SDA_3|GPIO_SPEED_50MHz) - -/* SPI */ - -#define GPIO_SPI1_MISO GPIO_SPI1_MISO_1 -#define GPIO_SPI1_MOSI GPIO_SPI1_MOSI_1 -#define GPIO_SPI1_SCK GPIO_SPI1_SCK_1 - -/* TIM */ - -#define GPIO_TIM2_CH2OUT (GPIO_TIM2_CH2OUT_2|GPIO_SPEED_50MHz) -#define GPIO_TIM2_CH3OUT (GPIO_TIM2_CH3OUT_3|GPIO_SPEED_50MHz) - -#define GPIO_TIM3_CH1OUT (GPIO_TIM3_CH1OUT_2|GPIO_SPEED_50MHz) -#define GPIO_TIM3_CH2OUT (GPIO_TIM3_CH2OUT_4|GPIO_SPEED_50MHz) - -#define GPIO_TIM4_CH1OUT (GPIO_TIM4_CH1OUT_2|GPIO_SPEED_50MHz) - -/* USART */ - -#define GPIO_USART2_RX (GPIO_USART2_RX_2|GPIO_SPEED_50MHz) -#define GPIO_USART2_TX (GPIO_USART2_TX_2|GPIO_SPEED_50MHz) - -/* UART4 */ - -#define GPIO_UART4_RX (GPIO_UART4_RX_0|GPIO_SPEED_50MHz) -#define GPIO_UART4_TX (GPIO_UART4_TX_0|GPIO_SPEED_50MHz) - -/* DMA channels *************************************************************/ - -/* ADC */ - -#define ADC1_DMA_CHAN DMACHAN_ADC1 -#define ADC2_DMA_CHAN DMACHAN_ADC2_1 -#define ADC3_DMA_CHAN DMACHAN_ADC3 -#define ADC4_DMA_CHAN DMACHAN_ADC4_1 - -#endif /* __BOARDS_ARM_STM32_NUCLEO_F303RE_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32/nucleo-f303re/scripts/Make.defs b/boards/arm/stm32/nucleo-f303re/scripts/Make.defs deleted file mode 100644 index eb1b16a4ac204..0000000000000 --- a/boards/arm/stm32/nucleo-f303re/scripts/Make.defs +++ /dev/null @@ -1,41 +0,0 @@ -############################################################################ -# boards/arm/stm32/nucleo-f303re/scripts/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/.config -include $(TOPDIR)/tools/Config.mk -include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs - -LDSCRIPT = ld.script -ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) - -ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 - -CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) -CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) -CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -AFLAGS := $(CFLAGS) -D__ASSEMBLY__ - -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections -LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32/nucleo-f303re/scripts/ld.script b/boards/arm/stm32/nucleo-f303re/scripts/ld.script deleted file mode 100644 index 509bf141fad7e..0000000000000 --- a/boards/arm/stm32/nucleo-f303re/scripts/ld.script +++ /dev/null @@ -1,121 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f303re/scripts/ld.script - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* The STM32F303RET6 has 512Kb of FLASH beginning at address 0x0800:0000 and - * 64Kb of SRAM. - * - * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 - * where the code expects to begin execution by jumping to the entry point in - * the 0x0800:0000 address range. - */ - -MEMORY -{ - flash (rx) : ORIGIN = 0x08000000, LENGTH = 512K - sram (rwx) : ORIGIN = 0x20000000, LENGTH = 64K -} - -OUTPUT_ARCH(arm) -EXTERN(_vectors) -ENTRY(_stext) -SECTIONS -{ - .text : { - _stext = ABSOLUTE(.); - *(.vectors) - *(.text .text.*) - *(.fixup) - *(.gnu.warning) - *(.rodata .rodata.*) - *(.gnu.linkonce.t.*) - *(.glue_7) - *(.glue_7t) - *(.got) - *(.gcc_except_table) - *(.gnu.linkonce.r.*) - _etext = ABSOLUTE(.); - } > flash - - .init_section : ALIGN(4) { - _sinit = ABSOLUTE(.); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) - KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) - _einit = ABSOLUTE(.); - } > flash - - .ARM.extab : ALIGN(4) { - *(.ARM.extab*) - } > flash - - .ARM.exidx : ALIGN(4) { - __exidx_start = ABSOLUTE(.); - *(.ARM.exidx*) - __exidx_end = ABSOLUTE(.); - } > flash - - .tdata : { - _stdata = ABSOLUTE(.); - *(.tdata .tdata.* .gnu.linkonce.td.*); - _etdata = ABSOLUTE(.); - } > flash - - .tbss : { - _stbss = ABSOLUTE(.); - *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); - _etbss = ABSOLUTE(.); - } > flash - - _eronly = ABSOLUTE(.); - - .data : ALIGN(4) { - _sdata = ABSOLUTE(.); - *(.data .data.*) - *(.gnu.linkonce.d.*) - CONSTRUCTORS - . = ALIGN(4); - _edata = ABSOLUTE(.); - } > sram AT > flash - - .bss : ALIGN(4) { - _sbss = ABSOLUTE(.); - *(.bss .bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - . = ALIGN(4); - _ebss = ABSOLUTE(.); - } > sram - - /* Stabs debugging sections. */ - - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_info 0 : { *(.debug_info) } - .debug_line 0 : { *(.debug_line) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_aranges 0 : { *(.debug_aranges) } -} diff --git a/boards/arm/stm32/nucleo-f303re/src/CMakeLists.txt b/boards/arm/stm32/nucleo-f303re/src/CMakeLists.txt deleted file mode 100644 index bcc8d69e66ca3..0000000000000 --- a/boards/arm/stm32/nucleo-f303re/src/CMakeLists.txt +++ /dev/null @@ -1,69 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/nucleo-f303re/src/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -set(SRCS stm32_boot.c) - -if(CONFIG_ARCH_LEDS) - list(APPEND SRCS stm32_autoleds.c) -else() - list(APPEND SRCS stm32_userleds.c) -endif() - -if(CONFIG_ARCH_BUTTONS) - list(APPEND SRCS stm32_buttons.c) -endif() - -if(CONFIG_ADC) - list(APPEND SRCS stm32_adc.c) -endif() - -if(CONFIG_STM32_CAN_CHARDRIVER) - list(APPEND SRCS stm32_can.c) -endif() - -if(CONFIG_DAC) - list(APPEND SRCS stm32_dac.c) -endif() - -if(CONFIG_PWM) - list(APPEND SRCS stm32_pwm.c) -endif() - -if(CONFIG_SPI) - list(APPEND SRCS stm32_spi.c) -endif() - -if(CONFIG_LCD_SSD1351) - list(APPEND SRCS stm32_ssd1351.c) -endif() - -if(CONFIG_TIMER) - list(APPEND SRCS stm32_timer.c) -endif() - -if(CONFIG_BOARDCTL_UNIQUEID) - list(APPEND SRCS stm32_uid.c) -endif() - -target_sources(board PRIVATE ${SRCS}) - -set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/ld.script") diff --git a/boards/arm/stm32/nucleo-f303re/src/Make.defs b/boards/arm/stm32/nucleo-f303re/src/Make.defs deleted file mode 100644 index 08749d74cd058..0000000000000 --- a/boards/arm/stm32/nucleo-f303re/src/Make.defs +++ /dev/null @@ -1,71 +0,0 @@ -############################################################################ -# boards/arm/stm32/nucleo-f303re/src/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/Make.defs - -CSRCS = stm32_boot.c - -ifeq ($(CONFIG_ARCH_LEDS),y) -CSRCS += stm32_autoleds.c -else -CSRCS += stm32_userleds.c -endif - -ifeq ($(CONFIG_ARCH_BUTTONS),y) -CSRCS += stm32_buttons.c -endif - -ifeq ($(CONFIG_ADC),y) -CSRCS += stm32_adc.c -endif - -ifeq ($(CONFIG_STM32_CAN_CHARDRIVER),y) -CSRCS += stm32_can.c -endif - -ifeq ($(CONFIG_DAC),y) -CSRCS += stm32_dac.c -endif - -ifeq ($(CONFIG_PWM),y) -CSRCS += stm32_pwm.c -endif - -ifeq ($(CONFIG_SPI),y) -CSRCS += stm32_spi.c -endif - -ifeq ($(CONFIG_LCD_SSD1351),y) -CSRCS += stm32_ssd1351.c -endif - -ifeq ($(CONFIG_TIMER),y) -CSRCS += stm32_timer.c -endif - -ifeq ($(CONFIG_BOARDCTL_UNIQUEID),y) -CSRCS += stm32_uid.c -endif - -DEPPATH += --dep-path board -VPATH += :board -CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/nucleo-f303re/src/stm32_adc.c b/boards/arm/stm32/nucleo-f303re/src/stm32_adc.c deleted file mode 100644 index 7f9f78d1d8e21..0000000000000 --- a/boards/arm/stm32/nucleo-f303re/src/stm32_adc.c +++ /dev/null @@ -1,374 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f303re/src/stm32_adc.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include "stm32.h" - -#if defined(CONFIG_ADC) && \ - (defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) || \ - defined(CONFIG_STM32_ADC3) || defined(CONFIG_STM32_ADC4)) - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -#if (defined(CONFIG_STM32_ADC1) && defined(CONFIG_STM32_ADC2)) || \ - (defined(CONFIG_STM32_ADC3) && defined(CONFIG_STM32_ADC4)) -# error "will not work with this combination of ADCs" -#endif - -/* 1 or 2 ADC devices (DEV1, DEV2) */ - -#if defined(CONFIG_STM32_ADC1) -# define DEV1_PORT 1 -#endif - -#if defined(CONFIG_STM32_ADC2) -# if defined(DEV1_PORT) -# define DEV2_PORT 2 -# else -# define DEV1_PORT 2 -# endif -#endif - -#if defined(CONFIG_STM32_ADC3) -# if defined(DEV2_PORT) -# error "Choose maximum two of ADC1, ADC2, ADC3, ADC4" -# else -# if defined(DEV1_PORT) -# define DEV2_PORT 3 -# else -# define DEV1_PORT 3 -# endif -# endif -#endif - -#if defined(CONFIG_STM32_ADC4) -# if defined(DEV2_PORT) -# error "Choose maximum two of ADC1, ADC2, ADC3, ADC4" -# else -# if defined(DEV1_PORT) -# define DEV2_PORT 4 -# else -# define DEV1_PORT 4 -# endif -# endif -#endif - -/* The number of ADC channels in the conversion list */ - -/* TODO DMA */ - -#define ADC1_NCHANNELS 4 -#define ADC2_NCHANNELS 3 -#define ADC3_NCHANNELS 3 -#define ADC4_NCHANNELS 1 - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* DEV 1 */ - -#if DEV1_PORT == 1 - -#define DEV1_NCHANNELS ADC1_NCHANNELS - -/* Identifying number of each ADC channel (even if NCHANNELS is less ) */ - -static const uint8_t g_chanlist1[4] = -{ - 1, - 2, - 6, - 7, -}; - -/* Configurations of pins used by each ADC channel */ - -static const uint32_t g_pinlist1[4] = -{ - GPIO_ADC1_IN1_0, - GPIO_ADC1_IN2_0, - GPIO_ADC1_IN6_0, - GPIO_ADC1_IN7_0 -}; - -#elif DEV1_PORT == 2 - -#define DEV1_NCHANNELS ADC2_NCHANNELS - -/* Identifying number of each ADC channel */ - -static const uint8_t g_chanlist1[3] = -{ - 1, - 3, - 4 -}; - -/* Configurations of pins used by each ADC channel */ - -static const uint32_t g_pinlist1[3] = -{ - GPIO_ADC2_IN1_0, - GPIO_ADC2_IN3_0, - GPIO_ADC2_IN4_0 -}; - -#elif DEV1_PORT == 3 - -#define DEV1_NCHANNELS ADC3_NCHANNELS - -/* Identifying number of each ADC channel */ - -static const uint8_t g_chanlist1[3] = -{ - 1, - 5, - 12 -}; - -/* Configurations of pins used by each ADC channel */ - -static const uint32_t g_pinlist1[3] = -{ - GPIO_ADC3_IN1_0, - GPIO_ADC3_IN5_0, - GPIO_ADC3_IN12_0 -}; - -#elif DEV1_PORT == 4 - -#define DEV1_NCHANNELS ADC4_NCHANNELS - -/* Identifying number of each ADC channel */ - -static const uint8_t g_chanlist1[1] = -{ - 3 -}; - -/* Configurations of pins used by each ADC channel */ - -static const uint32_t g_pinlist1[1] = -{ - GPIO_ADC4_IN3_0 -}; - -#endif - -#ifdef DEV2_PORT - -/* DEV 2 */ - -#if DEV2_PORT == 1 - -#define DEV2_NCHANNELS ADC1_NCHANNELS - -/* Identifying number of each ADC channel (even if NCHANNELS is less ) */ - -static const uint8_t g_chanlist2[4] = -{ - 1, - 2, - 6, - 7 -}; - -/* Configurations of pins used by each ADC channel */ - -static const uint32_t g_pinlist2[4] = -{ - GPIO_ADC1_IN1_0, - GPIO_ADC1_IN2_0, - GPIO_ADC1_IN6_0, - GPIO_ADC1_IN7_0 -}; - -#elif DEV2_PORT == 2 - -#define DEV2_NCHANNELS ADC2_NCHANNELS - -/* Identifying number of each ADC channel */ - -static const uint8_t g_chanlist2[3] = -{ - 1, - 3, - 4 -}; - -/* Configurations of pins used by each ADC channel */ - -static const uint32_t g_pinlist2[3] = -{ - GPIO_ADC2_IN1_0, - GPIO_ADC2_IN3_0, - GPIO_ADC2_IN4_0 -}; - -#elif DEV2_PORT == 3 - -#define DEV2_NCHANNELS ADC3_NCHANNELS - -/* Identifying number of each ADC channel */ - -static const uint8_t g_chanlist2[3] = -{ - 1, - 5, - 12 -}; - -/* Configurations of pins used by each ADC channel */ - -static const uint32_t g_pinlist2[3] = -{ - GPIO_ADC3_IN1_0, - GPIO_ADC3_IN5_0, - GPIO_ADC3_IN12_0 -}; - -#elif DEV2_PORT == 4 - -#define DEV2_NCHANNELS ADC4_NCHANNELS - -/* Identifying number of each ADC channel */ - -static const uint8_t g_chanlist2[1] = -{ - 3 -}; - -/* Configurations of pins used by each ADC channel */ - -static const uint32_t g_pinlist2[1] = -{ - GPIO_ADC4_IN3_0 -}; - -#endif -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_adc_setup - * - * Description: - * Initialize ADC and register the ADC driver. - * - ****************************************************************************/ - -int stm32_adc_setup(void) -{ - struct adc_dev_s *adc; - int ret; - int i; - - /* DEV1 */ - - /* Configure the pins as analog inputs for the selected channels */ - - for (i = 0; i < DEV1_NCHANNELS; i++) - { - stm32_configgpio(g_pinlist1[i]); - } - - /* Call stm32_adcinitialize() to get an instance of the ADC interface */ - - adc = stm32_adcinitialize(DEV1_PORT, g_chanlist1, DEV1_NCHANNELS); - if (adc == NULL) - { - aerr("ERROR: Failed to get ADC interface 1\n"); - return -ENODEV; - } - - /* Register the ADC driver at "/dev/adc0" */ - - ret = adc_register("/dev/adc0", adc); - if (ret < 0) - { - aerr("ERROR: adc_register /dev/adc0 failed: %d\n", ret); - return ret; - } - -#ifdef DEV2_PORT - - /* DEV2 */ - - /* Configure the pins as analog inputs for the selected channels */ - - for (i = 0; i < DEV2_NCHANNELS; i++) - { - stm32_configgpio(g_pinlist2[i]); - } - - /* Call stm32_adcinitialize() to get an instance of the ADC interface */ - - adc = stm32_adcinitialize(DEV2_PORT, g_chanlist2, DEV2_NCHANNELS); - if (adc == NULL) - { - aerr("ERROR: Failed to get ADC interface 2\n"); - return -ENODEV; - } - - /* Register the ADC driver at "/dev/adc1" */ - - ret = adc_register("/dev/adc1", adc); - if (ret < 0) - { - aerr("ERROR: adc_register /dev/adc1 failed: %d\n", ret); - return ret; - } -#endif - - return OK; -} - -#endif /* CONFIG_ADC && (CONFIG_STM32_ADC1 || CONFIG_STM32_ADC2 || - * CONFIG_STM32_ADC3 || CONFIG_STM32_ADC4) */ diff --git a/boards/arm/stm32/nucleo-f303re/src/stm32_autoleds.c b/boards/arm/stm32/nucleo-f303re/src/stm32_autoleds.c deleted file mode 100644 index 55c7df56a711d..0000000000000 --- a/boards/arm/stm32/nucleo-f303re/src/stm32_autoleds.c +++ /dev/null @@ -1,80 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f303re/src/stm32_autoleds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include "stm32.h" -#include "nucleo-f303re.h" - -#ifdef CONFIG_ARCH_LEDS - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_autoled_initialize - ****************************************************************************/ - -void board_autoled_initialize(void) -{ - /* Configure LED1 GPIO for output */ - - stm32_configgpio(GPIO_LED1); -} - -/**************************************************************************** - * Name: board_autoled_on - ****************************************************************************/ - -void board_autoled_on(int led) -{ - if (led == BOARD_LED1) - { - stm32_gpiowrite(GPIO_LED1, true); - } -} - -/**************************************************************************** - * Name: board_autoled_off - ****************************************************************************/ - -void board_autoled_off(int led) -{ - if (led == BOARD_LED1) - { - stm32_gpiowrite(GPIO_LED1, false); - } -} - -#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/nucleo-f303re/src/stm32_boot.c b/boards/arm/stm32/nucleo-f303re/src/stm32_boot.c deleted file mode 100644 index 6231f8b5f59c0..0000000000000 --- a/boards/arm/stm32/nucleo-f303re/src/stm32_boot.c +++ /dev/null @@ -1,171 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f303re/src/stm32_boot.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include -#include - -#include "nucleo-f303re.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#undef HAVE_LEDS -#undef HAVE_DAC - -#if !defined(CONFIG_ARCH_LEDS) && defined(CONFIG_USERLED_LOWER) -# define HAVE_LEDS 1 -#endif - -#if defined(CONFIG_DAC) -# define HAVE_DAC 1 -#endif - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_boardinitialize - * - * Description: - * All STM32 architectures must provide the following entry point. This - * entry point is called early in the initialization -- after all memory - * has been configured and mapped but before any devices have been - * initialized. - * - ****************************************************************************/ - -void stm32_boardinitialize(void) -{ -#ifdef CONFIG_SPI - if (stm32_spidev_initialize != NULL) - { - stm32_spidev_initialize(); - } -#endif - - /* Configure on-board LEDs if LED support has been selected. */ - -#ifdef CONFIG_ARCH_LEDS - board_autoled_initialize(); -#endif -} - -/**************************************************************************** - * Name: board_late_initialize - * - * Description: - * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional - * initialization call will be performed in the boot-up sequence to a - * function called board_late_initialize(). board_late_initialize() will - * be called immediately after up_intitialize() is called and just before - * the initial application is started. This additional initialization - * phase may be used, for example, to initialize board-specific device - * drivers. - * - ****************************************************************************/ - -#ifdef CONFIG_BOARD_LATE_INITIALIZE -void board_late_initialize(void) -{ - int ret; - -#ifdef HAVE_LEDS - /* Register the LED driver */ - - ret = userled_lower_initialize(LED_DRIVER_PATH); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: userled_lower_initialize() failed: %d\n", ret); - return ret; - } -#endif - -#ifdef CONFIG_PWM - /* Initialize PWM and register the PWM device. */ - - ret = stm32_pwm_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_pwm_setup() failed: %d\n", ret); - } -#endif - - /* Contrairement à l'ADC, il n'y a pas de BOARDIOC_DAC_SETUP spécifique. - * Il faut le faire ici - */ - -#ifdef HAVE_DAC - ret = board_dac_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: board_dac_setup() failed: %d\n", ret); - return; - } -#endif - -#ifdef CONFIG_ADC - /* Initialize ADC and register the ADC driver. */ - - ret = stm32_adc_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_adc_setup failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_STM32_CAN_CHARDRIVER - /* Initialize CAN and register the CAN driver. */ - - ret = stm32_can_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_can_setup failed: %d\n", ret); - } -#endif - - UNUSED(ret); -} -#endif /* CONFIG_BOARD_LATE_INITIALIZE */ diff --git a/boards/arm/stm32/nucleo-f303re/src/stm32_buttons.c b/boards/arm/stm32/nucleo-f303re/src/stm32_buttons.c deleted file mode 100644 index f93ac3a5f9bc2..0000000000000 --- a/boards/arm/stm32/nucleo-f303re/src/stm32_buttons.c +++ /dev/null @@ -1,113 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f303re/src/stm32_buttons.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include "stm32.h" -#include "nucleo-f303re.h" - -#ifdef CONFIG_ARCH_BUTTONS - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_button_initialize - * - * Description: - * board_button_initialize() must be called to initialize button - * resources. After that, board_buttons() may be called to collect the - * current state of all buttons or board_button_irq() may be called to - * register button interrupt handlers. - * - ****************************************************************************/ - -uint32_t board_button_initialize(void) -{ - /* Configure the single button as an input. NOTE that EXTI interrupts are - * also configured for the pin. - */ - - stm32_configgpio(GPIO_BTN_USER); - return NUM_BUTTONS; -} - -/**************************************************************************** - * Name: board_buttons - * - * Description: - * After board_button_initialize() has been called, board_buttons() may be - * called to collect the state of all buttons. board_buttons() returns an - * 32-bit unsigned integer with each bit associated with a button. See the - * BUTTON_*_BIT definitions in board.h for the meaning of each bit. - * - ****************************************************************************/ - -uint32_t board_buttons(void) -{ - /* Check the state of the USER button. A LOW value means that the key is - * pressed. - */ - - return stm32_gpioread(GPIO_BTN_USER) ? 0 : BUTTON_USER_BIT; -} - -/**************************************************************************** - * Name: board_button_irq - * - * Description: - * board_button_irq() may be called to register an interrupt handler that - * will be called when a button is depressed or released. The ID value is - * a button enumeration value that uniquely identifies a button resource. - * See the BUTTON_* definitions in board.h for the meaning of the - * enumeration value. - * - ****************************************************************************/ - -#ifdef CONFIG_ARCH_IRQBUTTONS -int board_button_irq(int id, xcpt_t irqhandler, void *arg) -{ - int ret = -EINVAL; - - if (id == BUTTON_USER) - { - ret = stm32_gpiosetevent(GPIO_BTN_USER, true, true, true, irqhandler, - arg); - } - - return ret; -} -#endif - -#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/stm32/nucleo-f303re/src/stm32_can.c b/boards/arm/stm32/nucleo-f303re/src/stm32_can.c deleted file mode 100644 index e7b25cf16ae33..0000000000000 --- a/boards/arm/stm32/nucleo-f303re/src/stm32_can.c +++ /dev/null @@ -1,81 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f303re/src/stm32_can.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include - -#include "stm32.h" - -#ifdef CONFIG_CAN - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_can_setup - * - * Description: - * Initialize CAN and register the CAN device - * - ****************************************************************************/ - -int stm32_can_setup(void) -{ -#ifdef CONFIG_STM32_CAN1 - struct can_dev_s *can; - int ret; - - /* Call stm32_caninitialize() to get an instance of the CAN interface */ - - can = stm32_caninitialize(1); - if (can == NULL) - { - canerr("ERROR: Failed to get CAN interface\n"); - return -ENODEV; - } - - /* Register the CAN driver at "/dev/can0" */ - - ret = can_register("/dev/can0", can); - if (ret < 0) - { - canerr("ERROR: can_register failed: %d\n", ret); - return ret; - } - - return OK; -#else - return -ENODEV; -#endif -} - -#endif /* CONFIG_CAN */ diff --git a/boards/arm/stm32/nucleo-f303re/src/stm32_pwm.c b/boards/arm/stm32/nucleo-f303re/src/stm32_pwm.c deleted file mode 100644 index 5d4544d1e8cbf..0000000000000 --- a/boards/arm/stm32/nucleo-f303re/src/stm32_pwm.c +++ /dev/null @@ -1,89 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f303re/src/stm32_pwm.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include "stm32_pwm.h" -#include "nucleo-f303re.h" - -#ifdef CONFIG_PWM - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_pwm_setup - * - * Description: - * Initialize PWM and register the PWM device. - * - ****************************************************************************/ - -int stm32_pwm_setup(void) -{ - static bool initialized = false; - struct pwm_lowerhalf_s *pwm; - int ret; - - /* Have we already initialized? */ - - if (!initialized) - { - /* Call stm32_pwminitialize() to get an instance of the PWM interface */ - - pwm = stm32_pwminitialize(NUCLEO_F303RE_PWMTIMER); - if (pwm == NULL) - { - pwmerr("ERROR: Failed to get the STM32 PWM lower half\n"); - return -ENODEV; - } - - /* Register the PWM driver at "/dev/pwm0" */ - - ret = pwm_register("/dev/pwm0", pwm); - if (ret < 0) - { - pwmerr("ERROR: pwm_register failed: %d\n", ret); - return ret; - } - - /* Now we are initialized */ - - initialized = true; - } - - return OK; -} - -#endif /* CONFIG_PWM */ diff --git a/boards/arm/stm32/nucleo-f303re/src/stm32_spi.c b/boards/arm/stm32/nucleo-f303re/src/stm32_spi.c deleted file mode 100644 index 559b5020f0383..0000000000000 --- a/boards/arm/stm32/nucleo-f303re/src/stm32_spi.c +++ /dev/null @@ -1,195 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f303re/src/stm32_spi.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include - -#include -#include - -#include "arm_internal.h" -#include "chip.h" -#include "stm32.h" -#include "nucleo-f303re.h" - -#ifdef CONFIG_SPI - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_spidev_initialize - * - * Description: - * Called to configure SPI chip select GPIO pins for the board. - * - ****************************************************************************/ - -void weak_function stm32_spidev_initialize(void) -{ -#if defined(CONFIG_LCD_SSD1351) - stm32_configgpio(GPIO_OLED_CS); /* OLED chip select */ - stm32_configgpio(GPIO_OLED_DC); /* OLED Command/Data */ -#endif -} - -/**************************************************************************** - * Name: stm32_spi1/2/3select and stm32_spi1/2/3status - * - * Description: - * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status - * must be provided by board-specific logic. They are implementations of - * the select and status methods of the SPI interface defined by struct - * spi_ops_s (see include/nuttx/spi/spi.h). All other methods (including - * stm32_spibus_initialize()) are provided by common STM32 logic. - * To use this common SPI logic on your board: - * - * 1. Provide logic in stm32_boardinitialize() to configure SPI chip select - * pins. - * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() functions - * in your board-specific logic. These functions will perform chip - * selection and status operations using GPIOs in the way your board is - * configured. - * 3. Add a calls to stm32_spibus_initialize() in your low level - * application initialization logic - * 4. The handle returned by stm32_spibus_initialize() may then be used to - * bind the SPI driver to higher level logic (e.g., calling - * mmcsd_spislotinitialize(), for example, will bind the SPI driver to - * the SPI MMC/SD driver). - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_SPI1 -void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, - bool selected) -{ - spiinfo("devid: %d CS: %s\n", - (int)devid, selected ? "assert" : "de-assert"); - -#if defined(CONFIG_LCD_SSD1351) - if (devid == SPIDEV_DISPLAY(0)) - { - stm32_gpiowrite(GPIO_OLED_CS, !selected); - } -#endif -} - -uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) -{ - return 0; -} -#endif - -#ifdef CONFIG_STM32_SPI2 -void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid, - bool selected) -{ - spiinfo("devid: %d CS: %s\n", - (int)devid, selected ? "assert" : "de-assert"); -} - -uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) -{ - return 0; -} -#endif - -#ifdef CONFIG_STM32_SPI3 -void stm32_spi3select(struct spi_dev_s *dev, uint32_t devid, - bool selected) -{ - spiinfo("devid: %d CS: %s\n", - (int)devid, selected ? "assert" : "de-assert"); -} - -uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid) -{ - return 0; -} -#endif - -/**************************************************************************** - * Name: stm32_spi1cmddata - * - * Description: - * Set or clear the SSD1351 D/C n bit to select data (true) or command - * (false). This function must be provided by platform-specific logic. - * This is an implementation of the cmddata method of the SPI interface - * defined by struct spi_ops_s (see include/nuttx/spi/spi.h). - * - * Input Parameters: - * spi - SPI device that controls the bus the device that requires the - * CMD/DATA selection. - * devid - If there are multiple devices on the bus, this selects which one - * to select cmd or data. NOTE: This design restricts, for - * example, one SPI display per SPI bus. - * cmd - true: select command; false: select data - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef CONFIG_SPI_CMDDATA -#ifdef CONFIG_STM32_SPI1 -int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, - bool cmd) -{ -#ifdef CONFIG_LCD_SSD1351 - if (devid == SPIDEV_DISPLAY(0)) - { - stm32_gpiowrite(GPIO_OLED_DC, !cmd); - return OK; - } -#endif - - return -ENODEV; -} -#endif - -#ifdef CONFIG_STM32_SPI2 -int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, - bool cmd) -{ - return -ENODEV; -} -#endif - -#ifdef CONFIG_STM32_SPI3 -int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, - bool cmd) -{ - return -ENODEV; -} -#endif -#endif /* CONFIG_SPI_CMDDATA */ - -#endif /* CONFIG_SPI */ diff --git a/boards/arm/stm32/nucleo-f303re/src/stm32_ssd1351.c b/boards/arm/stm32/nucleo-f303re/src/stm32_ssd1351.c deleted file mode 100644 index b0f3a56d028d2..0000000000000 --- a/boards/arm/stm32/nucleo-f303re/src/stm32_ssd1351.c +++ /dev/null @@ -1,118 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f303re/src/stm32_ssd1351.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include -#include -#include -#include -#include - -#include "stm32_gpio.h" -#include "stm32_spi.h" - -#include "nucleo-f303re.h" - -#ifdef CONFIG_LCD_SSD1351 - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -/* The pin configurations here require that SPI1 is selected */ - -#ifndef CONFIG_STM32_SPI1 -# error "The OLED driver requires CONFIG_STM32_SPI1 in the configuration" -#endif - -#ifndef CONFIG_SSD1351_SPI4WIRE -# error "The configuration requires the SPI 4-wire interface" -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_graphics_setup - * - * Description: - * Called by NX initialization logic to configure the OLED. - * - ****************************************************************************/ - -struct lcd_dev_s *board_graphics_setup(unsigned int devno) -{ - struct spi_dev_s *spi; - struct lcd_dev_s *dev; - - /* Configure the OLED GPIOs. This initial configuration is RESET low, - * putting the OLED into reset state. - */ - - stm32_configgpio(GPIO_OLED_RESET); - - /* Wait a bit then release the OLED from the reset state */ - - up_mdelay(20); - stm32_gpiowrite(GPIO_OLED_RESET, true); - - /* Get the SPI1 port interface */ - - spi = stm32_spibus_initialize(1); - if (spi == NULL) - { - lcderr("ERROR: Failed to initialize SPI port 1\n"); - } - else - { - /* Bind the SPI port to the OLED */ - - dev = ssd1351_initialize(spi, devno); - if (dev == NULL) - { - lcderr("ERROR: Failed to bind SPI port 1 to OLED %d\n", devno); - } - else - { - lcdinfo("Bound SPI port 1 to OLED %d\n", devno); - - /* And turn the OLED on */ - - dev->setpower(dev, LCD_FULL_ON); - return dev; - } - } - - return NULL; -} - -#endif /* CONFIG_LCD_SSD1351 */ diff --git a/boards/arm/stm32/nucleo-f303re/src/stm32_timer.c b/boards/arm/stm32/nucleo-f303re/src/stm32_timer.c deleted file mode 100644 index 221f721b5affa..0000000000000 --- a/boards/arm/stm32/nucleo-f303re/src/stm32_timer.c +++ /dev/null @@ -1,67 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f303re/src/stm32_timer.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include - -#include - -#include "stm32_tim.h" -#include "nucleo-f303re.h" - -#ifdef CONFIG_TIMER - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_timer_driver_setup - * - * Description: - * Configure the timer driver. - * - * Input Parameters: - * devpath - The full path to the timer device. This should be of the - * form /dev/timer0 - * timer - The timer's number. - * - * Returned Value: - * Zero (OK) is returned on success; A negated errno value is returned - * to indicate the nature of any failure. - * - ****************************************************************************/ - -int stm32_timer_driver_setup(const char *devpath, int timer) -{ - return stm32_timer_initialize(devpath, timer); -} - -#endif diff --git a/boards/arm/stm32/nucleo-f303re/src/stm32_uid.c b/boards/arm/stm32/nucleo-f303re/src/stm32_uid.c deleted file mode 100644 index af1a488fa10cf..0000000000000 --- a/boards/arm/stm32/nucleo-f303re/src/stm32_uid.c +++ /dev/null @@ -1,68 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f303re/src/stm32_uid.c - * - * SPDX-License-Identifier: BSD-3-Clause - * SPDX-FileCopyrightText: 2015 Marawan Ragab. All rights reserved. - * SPDX-FileContributor: Marawan Ragab - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include "stm32_uid.h" - -#include - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -#if defined(CONFIG_BOARDCTL_UNIQUEID) -int board_uniqueid(uint8_t *uniqueid) -{ - if (uniqueid == NULL) - { - return -EINVAL; - } - - stm32_get_uniqueid(uniqueid); - return OK; -} -#endif diff --git a/boards/arm/stm32/nucleo-f303re/src/stm32_userleds.c b/boards/arm/stm32/nucleo-f303re/src/stm32_userleds.c deleted file mode 100644 index 121230d908eff..0000000000000 --- a/boards/arm/stm32/nucleo-f303re/src/stm32_userleds.c +++ /dev/null @@ -1,77 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f303re/src/stm32_userleds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include - -#include "stm32.h" -#include "nucleo-f303re.h" - -#ifndef CONFIG_ARCH_LEDS - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_userled_initialize - ****************************************************************************/ - -uint32_t board_userled_initialize(void) -{ - /* Configure LED1 GPIO for output */ - - stm32_configgpio(GPIO_LED1); - return BOARD_NLEDS; -} - -/**************************************************************************** - * Name: board_userled - ****************************************************************************/ - -void board_userled(int led, bool ledon) -{ - if (led == BOARD_LED1) - { - stm32_gpiowrite(GPIO_LED1, ledon); - } -} - -/**************************************************************************** - * Name: board_userled_all - ****************************************************************************/ - -void board_userled_all(uint32_t ledset) -{ - stm32_gpiowrite(GPIO_LED1, (ledset & BOARD_LED1_BIT) != 0); -} - -#endif /* !CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/nucleo-f303ze/CMakeLists.txt b/boards/arm/stm32/nucleo-f303ze/CMakeLists.txt deleted file mode 100644 index 0892584b29463..0000000000000 --- a/boards/arm/stm32/nucleo-f303ze/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/nucleo-f303ze/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32/nucleo-f303ze/configs/adc/defconfig b/boards/arm/stm32/nucleo-f303ze/configs/adc/defconfig deleted file mode 100644 index b90be268b186f..0000000000000 --- a/boards/arm/stm32/nucleo-f303ze/configs/adc/defconfig +++ /dev/null @@ -1,52 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_STM32_CCMEXCLUDE is not set -CONFIG_ADC=y -CONFIG_ANALOG=y -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="nucleo-f303ze" -CONFIG_ARCH_BOARD_NUCLEO_F303ZE=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F303ZE=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=6522 -CONFIG_BUILTIN=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_EXAMPLES_ADC=y -CONFIG_EXAMPLES_ADC_GROUPSIZE=3 -CONFIG_EXAMPLES_ADC_SWTRIG=y -CONFIG_IDLETHREAD_STACKSIZE=2048 -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_MM_REGIONS=2 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=65536 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=27 -CONFIG_START_YEAR=2013 -CONFIG_STM32_ADC1=y -CONFIG_STM32_ADC1_DMA=y -CONFIG_STM32_ADC3=y -CONFIG_STM32_ADC3_RESOLUTION=3 -CONFIG_STM32_DMA1=y -CONFIG_STM32_DMA2=y -CONFIG_STM32_FORCEPOWER=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_TIM1=y -CONFIG_STM32_TIM1_ADC=y -CONFIG_STM32_USART3=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART3_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/nucleo-f303ze/configs/nsh/defconfig b/boards/arm/stm32/nucleo-f303ze/configs/nsh/defconfig deleted file mode 100644 index 7081c146db74b..0000000000000 --- a/boards/arm/stm32/nucleo-f303ze/configs/nsh/defconfig +++ /dev/null @@ -1,38 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="nucleo-f303ze" -CONFIG_ARCH_BOARD_NUCLEO_F303ZE=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F303ZE=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=6522 -CONFIG_BUILTIN=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_EXAMPLES_HELLO=y -CONFIG_IDLETHREAD_STACKSIZE=2048 -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_MM_REGIONS=2 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=65536 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=27 -CONFIG_START_YEAR=2013 -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_USART3=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART3_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/nucleo-f303ze/configs/nxlines_oled/defconfig b/boards/arm/stm32/nucleo-f303ze/configs/nxlines_oled/defconfig deleted file mode 100644 index 3c09c2da60034..0000000000000 --- a/boards/arm/stm32/nucleo-f303ze/configs/nxlines_oled/defconfig +++ /dev/null @@ -1,53 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_EXAMPLES_NXLINES_DEFAULT_COLORS is not set -# CONFIG_NX_DISABLE_1BPP is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="nucleo-f303ze" -CONFIG_ARCH_BOARD_COMMON=y -CONFIG_ARCH_BOARD_NUCLEO_F303ZE=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F303ZE=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=6522 -CONFIG_BUILTIN=y -CONFIG_EXAMPLES_NXLINES=y -CONFIG_EXAMPLES_NXLINES_BORDERWIDTH=1 -CONFIG_EXAMPLES_NXLINES_BPP=1 -CONFIG_EXAMPLES_NXLINES_LINECOLOR=0xff -CONFIG_EXAMPLES_NXLINES_LINEWIDTH=1 -CONFIG_IDLETHREAD_STACKSIZE=2048 -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LCD=y -CONFIG_LCD_MAXCONTRAST=255 -CONFIG_LCD_SH1106_OLED_132=y -CONFIG_LCD_SSD1306_I2C=y -CONFIG_MM_REGIONS=2 -CONFIG_MQ_MAXMSGSIZE=64 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NX=y -CONFIG_NXFONT_MONO5X8=y -CONFIG_NX_BLOCKING=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=65536 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=27 -CONFIG_START_YEAR=2013 -CONFIG_STM32_I2C1=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_USART3=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART3_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/nucleo-f303ze/include/board.h b/boards/arm/stm32/nucleo-f303ze/include/board.h deleted file mode 100644 index b604725820c16..0000000000000 --- a/boards/arm/stm32/nucleo-f303ze/include/board.h +++ /dev/null @@ -1,207 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f303ze/include/board.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __BOARDS_ARM_STM32_NUCLEO_F303ZE_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32_NUCLEO_F303ZE_INCLUDE_BOARD_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#ifndef __ASSEMBLY__ -# include -# include -#endif - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Clocking *****************************************************************/ - -/* HSI - Internal 8 MHz RC Oscillator - * LSI - 32 KHz RC - * HSE - 8 MHz from MCO output of ST-LINK - * LSE - 32.768 kHz - */ - -#define STM32_BOARD_XTAL 8000000ul /* X1 on board */ - -#define STM32_HSEBYP_ENABLE -#define STM32_HSI_FREQUENCY 8000000ul -#define STM32_LSI_FREQUENCY 40000 /* Between 30kHz and 60kHz */ -#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL -#define STM32_LSE_FREQUENCY 32768 /* X2 on board */ - -/* PLL source is HSE/1, PLL multiplier is 9: - * PLL frequency is 8MHz (XTAL) x 9 = 72MHz - */ - -#define STM32_CFGR_PLLSRC RCC_CFGR_PLLSRC -#define STM32_CFGR_PLLXTPRE 0 -#define STM32_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx9 -#define STM32_PLL_FREQUENCY (9*STM32_BOARD_XTAL) - -/* Use the PLL and set the SYSCLK source to be the PLL */ - -#define STM32_SYSCLK_SW RCC_CFGR_SW_PLL -#define STM32_SYSCLK_SWS RCC_CFGR_SWS_PLL -#define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY - -/* AHB clock (HCLK) is SYSCLK (72MHz) */ - -#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK -#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY - -/* APB2 clock (PCLK2) is HCLK (72MHz) */ - -#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK -#define STM32_PCLK2_FREQUENCY STM32_HCLK_FREQUENCY -#define STM32_APB2_CLKIN (STM32_PCLK2_FREQUENCY) /* Timers 1 and 8, 15-17 */ - -/* APB2 timers 1 and 8, 15-17 will receive PCLK2. */ - -/* Timers driven from APB2 will be PCLK2 */ - -#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB1_TIM15_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB1_TIM16_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB1_TIM17_CLKIN (STM32_PCLK2_FREQUENCY) - -/* APB1 clock (PCLK1) is HCLK/2 (36MHz) */ - -#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd2 -#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/2) - -/* APB1 timers 2-7 will be twice PCLK1 */ - -#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) - -/* USB divider -- Divide PLL clock by 1.5 */ - -#define STM32_CFGR_USBPRE 0 - -/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx - * otherwise frequency is 2xAPBx. - * Note: TIM1,8 are on APB2, others on APB1 - */ - -#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM2_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM3_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM4_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM5_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM6_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM7_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY - -/* LED definitions **********************************************************/ - -/* The Nucleo-144 board has numerous LEDs but only three, LD1 a Green LED, - * LD2 a Blue LED and LD3 a Red LED, that can be controlled by software. - * The following definitions assume the default Solder Bridges are installed. - * - * If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs - * in any way. - * The following definitions are used to access individual LEDs. - */ - -/* LED index values for use with board_userled() */ - -#define BOARD_LED1 0 -#define BOARD_LED2 1 -#define BOARD_LED3 2 -#define BOARD_NLEDS 3 - -#define BOARD_LED_GREEN BOARD_LED1 -#define BOARD_LED_BLUE BOARD_LED2 -#define BOARD_LED_RED BOARD_LED3 - -/* LED bits for use with board_userled_all() */ - -#define BOARD_LED1_BIT (1 << BOARD_LED1) -#define BOARD_LED2_BIT (1 << BOARD_LED2) -#define BOARD_LED3_BIT (1 << BOARD_LED3) - -/* If CONFIG_ARCH_LEDS is defined, the usage by the board port is defined in - * include/board.h and src/stm32_leds.c. The LEDs are used to encode - * OS-related events as follows: - * - * - * SYMBOL Meaning LED state - * Red Green Blue - * ---------------------- -------------------------- ------ ------ ---- - */ - -#define LED_STARTED 0 /* NuttX has been started OFF OFF OFF */ -#define LED_HEAPALLOCATE 1 /* Heap has been allocated OFF OFF ON */ -#define LED_IRQSENABLED 2 /* Interrupts enabled OFF ON OFF */ -#define LED_STACKCREATED 3 /* Idle stack created OFF ON ON */ -#define LED_INIRQ 4 /* In an interrupt N/C N/C GLOW */ -#define LED_SIGNAL 5 /* In a signal handler N/C GLOW N/C */ -#define LED_ASSERTION 6 /* An assertion failed GLOW N/C GLOW */ -#define LED_PANIC 7 /* The system has crashed Blink OFF N/C */ -#define LED_IDLE 8 /* MCU is in sleep mode ON OFF OFF */ - -/* Button definitions *******************************************************/ - -/* The NUCLEO board supports one button: Pushbutton B1, labeled "User", is - * connected to GPIO PC13. A high value will be sensed when the button is - * depressed. - */ - -#define BUTTON_USER 0 -#define NUM_BUTTONS 1 - -#define BUTTON_USER_BIT (1 << BUTTON_USER) - -/* Alternate function pin selections ****************************************/ - -/* USART3 (Nucleo Virtual Console) */ - -#define GPIO_USART3_RX (GPIO_USART3_RX_3|GPIO_SPEED_50MHz) /* PD9 */ -#define GPIO_USART3_TX (GPIO_USART3_TX_3|GPIO_SPEED_50MHz) /* PD8 */ - -/* I2C1 Use Nucleo I2C1 pins */ - -#define GPIO_I2C1_SCL (GPIO_I2C1_SCL_3|GPIO_SPEED_50MHz) /* PB8 - D15 */ -#define GPIO_I2C1_SDA (GPIO_I2C1_SDA_3|GPIO_SPEED_50MHz) /* PB9 - D14 */ - -/* I2C2 Use Nucleo I2C2 pins */ - -#define GPIO_I2C2_SCL (GPIO_I2C2_SCL_2|GPIO_SPEED_50MHz) /* PF1 - D69 */ -#define GPIO_I2C2_SDA (GPIO_I2C2_SDA_2|GPIO_SPEED_50MHz) /* PF0 - D68 */ -#define GPIO_I2C2_SMBA (GPIO_I2C2_SMBA_2|GPIO_SPEED_50MHz) /* PF2 - D70 */ - -/* DMA **********************************************************************/ - -#define ADC1_DMA_CHAN DMACHAN_ADC1 -#define ADC3_DMA_CHAN DMACHAN_ADC3 - -#endif /* __BOARDS_ARM_STM32_NUCLEO_F303ZE_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32/nucleo-f303ze/scripts/Make.defs b/boards/arm/stm32/nucleo-f303ze/scripts/Make.defs deleted file mode 100644 index fba0285e3737c..0000000000000 --- a/boards/arm/stm32/nucleo-f303ze/scripts/Make.defs +++ /dev/null @@ -1,41 +0,0 @@ -############################################################################ -# boards/arm/stm32/nucleo-f303ze/scripts/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/.config -include $(TOPDIR)/tools/Config.mk -include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs - -LDSCRIPT = ld.script -ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) - -ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 - -CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) -CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) -CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -AFLAGS := $(CFLAGS) -D__ASSEMBLY__ - -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections -LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32/nucleo-f303ze/scripts/ld.script b/boards/arm/stm32/nucleo-f303ze/scripts/ld.script deleted file mode 100644 index c43ec67e0d904..0000000000000 --- a/boards/arm/stm32/nucleo-f303ze/scripts/ld.script +++ /dev/null @@ -1,121 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f303ze/scripts/ld.script - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* The STM32F303ZET6 has 512Kb of FLASH beginning at address 0x0800:0000, - * 64Kb of SRAM and 16kb CCM RAM. - * - * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 - * where the code expects to begin execution by jumping to the entry point in - * the 0x0800:0000 address range. - */ - -MEMORY -{ - flash (rx) : ORIGIN = 0x08000000, LENGTH = 512K - sram (rwx) : ORIGIN = 0x20000000, LENGTH = 64K -} - -OUTPUT_ARCH(arm) -EXTERN(_vectors) -ENTRY(_stext) -SECTIONS -{ - .text : { - _stext = ABSOLUTE(.); - *(.vectors) - *(.text .text.*) - *(.fixup) - *(.gnu.warning) - *(.rodata .rodata.*) - *(.gnu.linkonce.t.*) - *(.glue_7) - *(.glue_7t) - *(.got) - *(.gcc_except_table) - *(.gnu.linkonce.r.*) - _etext = ABSOLUTE(.); - } > flash - - .init_section : ALIGN(4) { - _sinit = ABSOLUTE(.); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) - KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) - _einit = ABSOLUTE(.); - } > flash - - .ARM.extab : ALIGN(4) { - *(.ARM.extab*) - } > flash - - .ARM.exidx : ALIGN(4) { - __exidx_start = ABSOLUTE(.); - *(.ARM.exidx*) - __exidx_end = ABSOLUTE(.); - } > flash - - .tdata : { - _stdata = ABSOLUTE(.); - *(.tdata .tdata.* .gnu.linkonce.td.*); - _etdata = ABSOLUTE(.); - } > flash - - .tbss : { - _stbss = ABSOLUTE(.); - *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); - _etbss = ABSOLUTE(.); - } > flash - - _eronly = ABSOLUTE(.); - - .data : ALIGN(4) { - _sdata = ABSOLUTE(.); - *(.data .data.*) - *(.gnu.linkonce.d.*) - CONSTRUCTORS - . = ALIGN(4); - _edata = ABSOLUTE(.); - } > sram AT > flash - - .bss : ALIGN(4) { - _sbss = ABSOLUTE(.); - *(.bss .bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - . = ALIGN(4); - _ebss = ABSOLUTE(.); - } > sram - - /* Stabs debugging sections. */ - - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_info 0 : { *(.debug_info) } - .debug_line 0 : { *(.debug_line) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_aranges 0 : { *(.debug_aranges) } -} diff --git a/boards/arm/stm32/nucleo-f303ze/src/CMakeLists.txt b/boards/arm/stm32/nucleo-f303ze/src/CMakeLists.txt deleted file mode 100644 index 5c6e0c74cb3cf..0000000000000 --- a/boards/arm/stm32/nucleo-f303ze/src/CMakeLists.txt +++ /dev/null @@ -1,45 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/nucleo-f303ze/src/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -set(SRCS stm32_boot.c stm32_bringup.c) - -if(CONFIG_ARCH_LEDS) - list(APPEND SRCS stm32_autoleds.c) -else() - list(APPEND SRCS stm32_userleds.c) -endif() - -if(CONFIG_ARCH_BUTTONS) - list(APPEND SRCS stm32_buttons.c) -endif() - -if(CONFIG_ADC) - list(APPEND SRCS stm32_adc.c) -endif() - -if(CONFIG_LCD_SSD1306) - list(APPEND SRCS stm32_lcd.c) -endif() - -target_sources(board PRIVATE ${SRCS}) - -set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/ld.script") diff --git a/boards/arm/stm32/nucleo-f303ze/src/Make.defs b/boards/arm/stm32/nucleo-f303ze/src/Make.defs deleted file mode 100644 index 099d67193b38b..0000000000000 --- a/boards/arm/stm32/nucleo-f303ze/src/Make.defs +++ /dev/null @@ -1,47 +0,0 @@ -############################################################################ -# boards/arm/stm32/nucleo-f303ze/src/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/Make.defs - -CSRCS = stm32_boot.c stm32_bringup.c - -ifeq ($(CONFIG_ARCH_LEDS),y) -CSRCS += stm32_autoleds.c -else -CSRCS += stm32_userleds.c -endif - -ifeq ($(CONFIG_ARCH_BUTTONS),y) -CSRCS += stm32_buttons.c -endif - -ifeq ($(CONFIG_ADC),y) -CSRCS += stm32_adc.c -endif - -ifeq ($(CONFIG_LCD_SSD1306),y) -CSRCS += stm32_lcd.c -endif - -DEPPATH += --dep-path board -VPATH += :board -CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/nucleo-f303ze/src/stm32_adc.c b/boards/arm/stm32/nucleo-f303ze/src/stm32_adc.c deleted file mode 100644 index a5f559fb43276..0000000000000 --- a/boards/arm/stm32/nucleo-f303ze/src/stm32_adc.c +++ /dev/null @@ -1,243 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f303ze/src/stm32_adc.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include "stm32.h" - -#if defined(CONFIG_ADC) && (defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC3)) - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -/* 1 or 2 ADC devices (DEV1, DEV2). - * ADC1 and ADC3 supported for now. - */ - -#if defined(CONFIG_STM32_ADC1) -# define DEV1_PORT 1 -#endif - -#if defined(CONFIG_STM32_ADC3) -# if defined(DEV1_PORT) -# define DEV2_PORT 3 -# else -# define DEV1_PORT 3 -# endif -#endif - -/* The number of ADC channels in the conversion list */ - -/* TODO DMA */ - -#define ADC1_NCHANNELS 3 -#define ADC3_NCHANNELS 3 - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* DEV 1 */ - -#if DEV1_PORT == 1 - -#define DEV1_NCHANNELS ADC1_NCHANNELS - -/* Identifying number of each ADC channel (even if NCHANNELS is less ) */ - -static const uint8_t g_chanlist1[3] = -{ - 4, - 6, - 9 -}; - -/* Configurations of pins used by each ADC channel */ - -static const uint32_t g_pinlist1[3] = -{ - GPIO_ADC1_IN4_0, /* PA3/A0 */ - GPIO_ADC1_IN6_0, /* PC0/A1 */ - GPIO_ADC1_IN9_0, /* PC3/A2 */ -}; - -#elif DEV1_PORT == 3 - -#define DEV1_NCHANNELS ADC3_NCHANNELS - -/* Identifying number of each ADC channel */ - -static const uint8_t g_chanlist1[3] = -{ - 8, - 9, - 10 -}; - -/* Configurations of pins used by each ADC channel */ - -static const uint32_t g_pinlist1[3] = -{ - GPIO_ADC3_IN8_0, /* PD11/A3 */ - GPIO_ADC3_IN9_0, /* PD12/A4 */ - GPIO_ADC3_IN10_0, /* PD13/A5 */ -}; - -#endif /* DEV1_PORT == 1 */ - -#ifdef DEV2_PORT - -/* DEV 2 */ - -#if DEV2_PORT == 3 - -#define DEV2_NCHANNELS ADC3_NCHANNELS - -/* Identifying number of each ADC channel */ - -static const uint8_t g_chanlist2[3] = -{ - 8, - 9, - 10 -}; - -/* Configurations of pins used by each ADC channel */ - -static const uint32_t g_pinlist2[3] = -{ - GPIO_ADC3_IN8_0, /* PD11/A3 */ - GPIO_ADC3_IN9_0, /* PD12/A4 */ - GPIO_ADC3_IN10_0, /* PD13/A5 */ -}; - -#endif /* DEV2_PORT == 3 */ -#endif /* DEV2_PORT */ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_adc_setup - * - * Description: - * Initialize ADC and register the ADC driver. - * - ****************************************************************************/ - -int stm32_adc_setup(void) -{ - static bool initialized = false; - struct adc_dev_s *adc; - int ret; - int i; - - /* Check if we have already initialized */ - - if (!initialized) - { - /* DEV1 */ - - /* Configure the pins as analog inputs for the selected channels */ - - for (i = 0; i < DEV1_NCHANNELS; i++) - { - stm32_configgpio(g_pinlist1[i]); - } - - /* Call stm32_adcinitialize() to get an instance of the ADC interface */ - - adc = stm32_adcinitialize(DEV1_PORT, g_chanlist1, DEV1_NCHANNELS); - if (adc == NULL) - { - aerr("ERROR: Failed to get ADC interface 1\n"); - return -ENODEV; - } - - /* Register the ADC driver at "/dev/adc0" */ - - ret = adc_register("/dev/adc0", adc); - if (ret < 0) - { - aerr("ERROR: adc_register /dev/adc0 failed: %d\n", ret); - return ret; - } - -#ifdef DEV2_PORT - /* DEV2 */ - - /* Configure the pins as analog inputs for the selected channels */ - - for (i = 0; i < DEV2_NCHANNELS; i++) - { - stm32_configgpio(g_pinlist2[i]); - } - - /* Call stm32_adcinitialize() to get an instance of the ADC interface */ - - adc = stm32_adcinitialize(DEV2_PORT, g_chanlist2, DEV2_NCHANNELS); - if (adc == NULL) - { - aerr("ERROR: Failed to get ADC interface 2\n"); - return -ENODEV; - } - - /* Register the ADC driver at "/dev/adc1" */ - - ret = adc_register("/dev/adc1", adc); - if (ret < 0) - { - aerr("ERROR: adc_register /dev/adc1 failed: %d\n", ret); - return ret; - } -#endif - - initialized = true; - } - - return OK; -} - -#endif /* CONFIG_ADC && (CONFIG_STM32_ADC1 || CONFIG_STM32_ADC3) */ diff --git a/boards/arm/stm32/nucleo-f303ze/src/stm32_autoleds.c b/boards/arm/stm32/nucleo-f303ze/src/stm32_autoleds.c deleted file mode 100644 index b990cdd6219b8..0000000000000 --- a/boards/arm/stm32/nucleo-f303ze/src/stm32_autoleds.c +++ /dev/null @@ -1,171 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f303ze/src/stm32_autoleds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include - -#include -#include - -#include "stm32_gpio.h" -#include "nucleo-f303ze.h" - -#ifdef CONFIG_ARCH_LEDS - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* Indexed by BOARD_LED_ */ - -static const uint32_t g_ledmap[BOARD_NLEDS] = -{ - GPIO_LED_GREEN, - GPIO_LED_BLUE, - GPIO_LED_RED, -}; - -static bool g_initialized; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -static void phy_set_led(int led, bool state) -{ - /* Active High */ - - stm32_gpiowrite(g_ledmap[led], state); -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_autoled_initialize - ****************************************************************************/ - -void board_autoled_initialize(void) -{ - int i; - - /* Configure the LD1 GPIO for output. Initial state is OFF */ - - for (i = 0; i < nitems(g_ledmap); i++) - { - stm32_configgpio(g_ledmap[i]); - } -} - -/**************************************************************************** - * Name: board_autoled_on - ****************************************************************************/ - -void board_autoled_on(int led) -{ - switch (led) - { - default: - break; - - case LED_HEAPALLOCATE: - phy_set_led(BOARD_LED_BLUE, true); - break; - - case LED_IRQSENABLED: - phy_set_led(BOARD_LED_BLUE, false); - phy_set_led(BOARD_LED_GREEN, true); - break; - - case LED_STACKCREATED: - phy_set_led(BOARD_LED_GREEN, true); - phy_set_led(BOARD_LED_BLUE, true); - g_initialized = true; - break; - - case LED_INIRQ: - phy_set_led(BOARD_LED_BLUE, true); - break; - - case LED_SIGNAL: - phy_set_led(BOARD_LED_GREEN, true); - break; - - case LED_ASSERTION: - phy_set_led(BOARD_LED_RED, true); - phy_set_led(BOARD_LED_BLUE, true); - break; - - case LED_PANIC: - phy_set_led(BOARD_LED_RED, true); - break; - - case LED_IDLE : /* IDLE */ - phy_set_led(BOARD_LED_RED, true); - break; - } -} - -/**************************************************************************** - * Name: board_autoled_off - ****************************************************************************/ - -void board_autoled_off(int led) -{ - switch (led) - { - default: - break; - - case LED_SIGNAL: - phy_set_led(BOARD_LED_GREEN, false); - break; - - case LED_INIRQ: - phy_set_led(BOARD_LED_BLUE, false); - break; - - case LED_ASSERTION: - phy_set_led(BOARD_LED_RED, false); - phy_set_led(BOARD_LED_BLUE, false); - break; - - case LED_PANIC: - phy_set_led(BOARD_LED_RED, false); - break; - - case LED_IDLE : /* IDLE */ - phy_set_led(BOARD_LED_RED, false); - break; - } -} - -#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/nucleo-f303ze/src/stm32_boot.c b/boards/arm/stm32/nucleo-f303ze/src/stm32_boot.c deleted file mode 100644 index f2c54d36d4e31..0000000000000 --- a/boards/arm/stm32/nucleo-f303ze/src/stm32_boot.c +++ /dev/null @@ -1,81 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f303ze/src/stm32_boot.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include -#include - -#include "arm_internal.h" -#include "stm32_start.h" -#include "nucleo-f303ze.h" - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_boardinitialize - * - * Description: - * All STM32 architectures must provide the following entry point. - * This entry point is called early in the initialization -- after all - * memory has been configured and mapped but before any devices have been - * initialized. - * - ****************************************************************************/ - -void stm32_boardinitialize(void) -{ -#ifdef CONFIG_ARCH_LEDS - /* Configure on-board LEDs if LED support has been selected. */ - - board_autoled_initialize(); -#endif -} - -/**************************************************************************** - * Name: board_late_initialize - * - * Description: - * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional - * initialization call will be performed in the boot-up sequence to a - * function called board_late_initialize(). board_late_initialize() will - * be called immediately after up_initialize() is called and just before - * the initial application is started. - * This additional initialization phase may be used, for example, to - * initialize board-specific device drivers. - * - ****************************************************************************/ - -#ifdef CONFIG_BOARD_LATE_INITIALIZE -void board_late_initialize(void) -{ - stm32_bringup(); -} -#endif diff --git a/boards/arm/stm32/nucleo-f303ze/src/stm32_bringup.c b/boards/arm/stm32/nucleo-f303ze/src/stm32_bringup.c deleted file mode 100644 index 697969eec6678..0000000000000 --- a/boards/arm/stm32/nucleo-f303ze/src/stm32_bringup.c +++ /dev/null @@ -1,71 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f303ze/src/stm32_bringup.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include "nucleo-f303ze.h" - -#ifdef CONFIG_INPUT_BUTTONS -# include -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_bringup - * - * Description: - * Perform architecture-specific initialization - * - * CONFIG_BOARD_LATE_INITIALIZE=y : - * Called from board_late_initialize(). - * - ****************************************************************************/ - -int stm32_bringup(void) -{ - int ret = OK; - - UNUSED(ret); - -#ifdef CONFIG_ADC - /* Initialize ADC and register the ADC driver. */ - - ret = stm32_adc_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_adc_setup failed: %d\n", ret); - } -#endif - - return OK; -} diff --git a/boards/arm/stm32/nucleo-f303ze/src/stm32_buttons.c b/boards/arm/stm32/nucleo-f303ze/src/stm32_buttons.c deleted file mode 100644 index 9e82309922da4..0000000000000 --- a/boards/arm/stm32/nucleo-f303ze/src/stm32_buttons.c +++ /dev/null @@ -1,107 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f303ze/src/stm32_buttons.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include - -#include "stm32_gpio.h" -#include "nucleo-f303ze.h" -#include - -#ifdef CONFIG_ARCH_BUTTONS - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_button_initialize - * - * Description: - * board_button_initialize() must be called to initialize button resources. - * After that, board_buttons() may be called to collect the current state - * of all buttons or board_button_irq() may be called to register button - * interrupt handlers. - * - ****************************************************************************/ - -uint32_t board_button_initialize(void) -{ - stm32_configgpio(GPIO_BTN_USER); - return NUM_BUTTONS; -} - -/**************************************************************************** - * Name: board_buttons - ****************************************************************************/ - -uint32_t board_buttons(void) -{ - return stm32_gpioread(GPIO_BTN_USER) ? 1 : 0; -} - -/**************************************************************************** - * Button support. - * - * Description: - * board_button_initialize() must be called to initialize button resources. - * After that, board_buttons() may be called to collect the current state - * of all buttons or board_button_irq() may be called to register button - * interrupt handlers. - * - * After board_button_initialize() has been called, board_buttons() may be - * called to collect the state of all buttons. board_buttons() returns a - * 32-bit bit set with each bit associated with a button. See the - * BUTTON_*_BIT definitions in board.h for the meaning of each bit. - * - * board_button_irq() may be called to register an interrupt handler that - * will be called when a button is depressed or released. The ID value is - * a button enumeration value that uniquely identifies a button resource. - * See the BUTTON_* definitions in board.h for the meaning of enumeration - * value. - * - ****************************************************************************/ - -#ifdef CONFIG_ARCH_IRQBUTTONS -int board_button_irq(int id, xcpt_t irqhandler, void *arg) -{ - int ret = -EINVAL; - - if (id == BUTTON_USER) - { - ret = stm32_gpiosetevent(GPIO_BTN_USER, true, true, true, - irqhandler, arg); - } - - return ret; -} -#endif -#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/stm32/nucleo-f303ze/src/stm32_lcd.c b/boards/arm/stm32/nucleo-f303ze/src/stm32_lcd.c deleted file mode 100644 index cb6b3ffe895c4..0000000000000 --- a/boards/arm/stm32/nucleo-f303ze/src/stm32_lcd.c +++ /dev/null @@ -1,89 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f303ze/src/stm32_lcd.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include -#include -#include -#include - -#include "stm32.h" -#include "nucleo-f303ze.h" - -#include "stm32_ssd1306.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#define OLED_I2C_PORT 1 /* OLED display connected to I2C1 */ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_lcd_initialize - ****************************************************************************/ - -int board_lcd_initialize(void) -{ - int ret; - - ret = board_ssd1306_initialize(OLED_I2C_PORT); - if (ret < 0) - { - lcderr("ERROR: Failed to initialize SSD1306\n"); - return ret; - } - - return OK; -} - -/**************************************************************************** - * Name: board_lcd_getdev - ****************************************************************************/ - -struct lcd_dev_s *board_lcd_getdev(int devno) -{ - return board_ssd1306_getdev(); -} - -/**************************************************************************** - * Name: board_lcd_uninitialize - ****************************************************************************/ - -void board_lcd_uninitialize(void) -{ - /* TO-FIX */ -} diff --git a/boards/arm/stm32/nucleo-f303ze/src/stm32_userleds.c b/boards/arm/stm32/nucleo-f303ze/src/stm32_userleds.c deleted file mode 100644 index f2f7522ee6900..0000000000000 --- a/boards/arm/stm32/nucleo-f303ze/src/stm32_userleds.c +++ /dev/null @@ -1,127 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f303ze/src/stm32_userleds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include - -#include -#include - -#include "stm32_gpio.h" -#include "nucleo-f303ze.h" - -#ifndef CONFIG_ARCH_LEDS - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* This array maps an LED number to GPIO pin configuration and is indexed by - * BOARD_LED_ - */ - -static const uint32_t g_ledcfg[BOARD_NLEDS] = -{ - GPIO_LED_GREEN, - GPIO_LED_BLUE, - GPIO_LED_RED, -}; - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_userled_initialize - * - * Description: - * If CONFIG_ARCH_LEDS is defined, then NuttX will control the on-board - * LEDs. If CONFIG_ARCH_LEDS is not defined, then the - * board_userled_initialize() is available to initialize the LED from user - * application logic. - * - ****************************************************************************/ - -uint32_t board_userled_initialize(void) -{ - int i; - - /* Configure LED1-3 GPIOs for output */ - - for (i = 0; i < nitems(g_ledcfg); i++) - { - stm32_configgpio(g_ledcfg[i]); - } - - return BOARD_NLEDS; -} - -/**************************************************************************** - * Name: board_userled - * - * Description: - * If CONFIG_ARCH_LEDS is defined, then NuttX will control the on-board - * LEDs. If CONFIG_ARCH_LEDS is not defined, then the board_userled() is - * available to control the LED from user application logic. - * - ****************************************************************************/ - -void board_userled(int led, bool ledon) -{ - if ((unsigned)led < nitems(g_ledcfg)) - { - stm32_gpiowrite(g_ledcfg[led], ledon); - } -} - -/**************************************************************************** - * Name: board_userled_all - * - * Description: - * If CONFIG_ARCH_LEDS is defined, then NuttX will control the on-board - * LEDs. If CONFIG_ARCH_LEDS is not defined, then the board_userled_all() - * is available to control the LED from user application logic. NOTE: since - * there is only a single LED on-board, this is function is not very useful. - * - ****************************************************************************/ - -void board_userled_all(uint32_t ledset) -{ - int i; - - /* Configure LED1-3 GPIOs for output */ - - for (i = 0; i < nitems(g_ledcfg); i++) - { - stm32_gpiowrite(g_ledcfg[i], (ledset & (1 << i)) != 0); - } -} - -#endif /* !CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/nucleo-f334r8/CMakeLists.txt b/boards/arm/stm32/nucleo-f334r8/CMakeLists.txt deleted file mode 100644 index ef3be834441c3..0000000000000 --- a/boards/arm/stm32/nucleo-f334r8/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/nucleo-f334r8/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32/nucleo-f334r8/configs/adc/defconfig b/boards/arm/stm32/nucleo-f334r8/configs/adc/defconfig deleted file mode 100644 index 33656febfca35..0000000000000 --- a/boards/arm/stm32/nucleo-f334r8/configs/adc/defconfig +++ /dev/null @@ -1,95 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_SYSTEM_DD is not set -CONFIG_ADC=y -CONFIG_ANALOG=y -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="nucleo-f334r8" -CONFIG_ARCH_BOARD_NUCLEO_F334R8=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F334R8=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARDCTL=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_DISABLE_ENVIRON=y -CONFIG_DISABLE_MQUEUE=y -CONFIG_DISABLE_POSIX_TIMERS=y -CONFIG_DISABLE_PTHREAD=y -CONFIG_EXAMPLES_ADC=y -CONFIG_EXAMPLES_ADC_GROUPSIZE=3 -CONFIG_EXAMPLES_ADC_SWTRIG=y -CONFIG_FDCLONE_STDIO=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INIT_STACKSIZE=1024 -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_NAME_MAX=16 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_DISABLE_BASENAME=y -CONFIG_NSH_DISABLE_CAT=y -CONFIG_NSH_DISABLE_CD=y -CONFIG_NSH_DISABLE_CMP=y -CONFIG_NSH_DISABLE_CP=y -CONFIG_NSH_DISABLE_DF=y -CONFIG_NSH_DISABLE_DIRNAME=y -CONFIG_NSH_DISABLE_EXEC=y -CONFIG_NSH_DISABLE_EXIT=y -CONFIG_NSH_DISABLE_GET=y -CONFIG_NSH_DISABLE_HEXDUMP=y -CONFIG_NSH_DISABLE_KILL=y -CONFIG_NSH_DISABLE_LOSETUP=y -CONFIG_NSH_DISABLE_LS=y -CONFIG_NSH_DISABLE_MKDIR=y -CONFIG_NSH_DISABLE_MKRD=y -CONFIG_NSH_DISABLE_MOUNT=y -CONFIG_NSH_DISABLE_MV=y -CONFIG_NSH_DISABLE_PUT=y -CONFIG_NSH_DISABLE_PWD=y -CONFIG_NSH_DISABLE_RM=y -CONFIG_NSH_DISABLE_RMDIR=y -CONFIG_NSH_DISABLE_SET=y -CONFIG_NSH_DISABLE_SLEEP=y -CONFIG_NSH_DISABLE_SOURCE=y -CONFIG_NSH_DISABLE_TEST=y -CONFIG_NSH_DISABLE_TIME=y -CONFIG_NSH_DISABLE_UMOUNT=y -CONFIG_NSH_DISABLE_UNAME=y -CONFIG_NSH_DISABLE_UNSET=y -CONFIG_NSH_DISABLE_USLEEP=y -CONFIG_NSH_DISABLE_WGET=y -CONFIG_NSH_DISABLE_XD=y -CONFIG_NSH_FILEIOSIZE=256 -CONFIG_NSH_READLINE=y -CONFIG_POSIX_SPAWN_DEFAULT_STACKSIZE=512 -CONFIG_PTHREAD_STACK_DEFAULT=1024 -CONFIG_PTHREAD_STACK_MIN=1024 -CONFIG_RAM_SIZE=12288 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=6 -CONFIG_START_MONTH=12 -CONFIG_START_YEAR=2011 -CONFIG_STM32_ADC1=y -CONFIG_STM32_ADC1_DMA=y -CONFIG_STM32_ADC2=y -CONFIG_STM32_DMA1=y -CONFIG_STM32_FORCEPOWER=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_PWR=y -CONFIG_STM32_TIM1=y -CONFIG_STM32_TIM1_ADC=y -CONFIG_STM32_USART2=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/nucleo-f334r8/configs/highpri/defconfig b/boards/arm/stm32/nucleo-f334r8/configs/highpri/defconfig deleted file mode 100644 index 1866cd70f3cf7..0000000000000 --- a/boards/arm/stm32/nucleo-f334r8/configs/highpri/defconfig +++ /dev/null @@ -1,62 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="nucleo-f334r8" -CONFIG_ARCH_BOARD_NUCLEO_F334R8=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F334R8=y -CONFIG_ARCH_HIPRI_INTERRUPT=y -CONFIG_ARCH_RAMVECTORS=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARDCTL=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_DISABLE_ENVIRON=y -CONFIG_DISABLE_MQUEUE=y -CONFIG_DISABLE_POSIX_TIMERS=y -CONFIG_FDCLONE_STDIO=y -CONFIG_INIT_ENTRYPOINT="highpri_main" -CONFIG_INIT_STACKSIZE=1024 -CONFIG_INTELHEX_BINARY=y -CONFIG_LIBM=y -CONFIG_NAME_MAX=16 -CONFIG_NUCLEOF334R8_HIGHPRI=y -CONFIG_POSIX_SPAWN_DEFAULT_STACKSIZE=512 -CONFIG_PTHREAD_STACK_DEFAULT=1024 -CONFIG_PTHREAD_STACK_MIN=1024 -CONFIG_RAM_SIZE=12288 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=6 -CONFIG_START_MONTH=12 -CONFIG_START_YEAR=2011 -CONFIG_STM32_ADC1=y -CONFIG_STM32_ADC1_DMA=y -CONFIG_STM32_ADC1_DMA_CFG=1 -CONFIG_STM32_ADC1_EXTSEL=y -CONFIG_STM32_ADC1_INJECTED_CHAN=1 -CONFIG_STM32_ADC_LL_OPS=y -CONFIG_STM32_ADC_NOIRQ=y -CONFIG_STM32_DMA1=y -CONFIG_STM32_HRTIM1=y -CONFIG_STM32_HRTIM_ADC1_TRG1=y -CONFIG_STM32_HRTIM_ADC=y -CONFIG_STM32_HRTIM_CLK_FROM_PLL=y -CONFIG_STM32_HRTIM_DISABLE_CHARDRV=y -CONFIG_STM32_HRTIM_NO_ENABLE_TIMERS=y -CONFIG_STM32_HRTIM_TIMA=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_PWR=y -CONFIG_STM32_USART2=y -CONFIG_SYSTEM_READLINE=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/nucleo-f334r8/configs/nsh/defconfig b/boards/arm/stm32/nucleo-f334r8/configs/nsh/defconfig deleted file mode 100644 index 2bb393ba17062..0000000000000 --- a/boards/arm/stm32/nucleo-f334r8/configs/nsh/defconfig +++ /dev/null @@ -1,86 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_SYSTEM_DD is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="nucleo-f334r8" -CONFIG_ARCH_BOARD_NUCLEO_F334R8=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F334R8=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_DEBUG_FULLOPT=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_DISABLE_ENVIRON=y -CONFIG_DISABLE_MQUEUE=y -CONFIG_DISABLE_POSIX_TIMERS=y -CONFIG_DISABLE_PTHREAD=y -CONFIG_EXAMPLES_HELLO=y -CONFIG_FDCLONE_STDIO=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INIT_STACKSIZE=1024 -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_NAME_MAX=16 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_DISABLE_BASENAME=y -CONFIG_NSH_DISABLE_CAT=y -CONFIG_NSH_DISABLE_CD=y -CONFIG_NSH_DISABLE_CMP=y -CONFIG_NSH_DISABLE_CP=y -CONFIG_NSH_DISABLE_DF=y -CONFIG_NSH_DISABLE_DIRNAME=y -CONFIG_NSH_DISABLE_EXEC=y -CONFIG_NSH_DISABLE_EXIT=y -CONFIG_NSH_DISABLE_GET=y -CONFIG_NSH_DISABLE_HEXDUMP=y -CONFIG_NSH_DISABLE_KILL=y -CONFIG_NSH_DISABLE_LOSETUP=y -CONFIG_NSH_DISABLE_LS=y -CONFIG_NSH_DISABLE_MKDIR=y -CONFIG_NSH_DISABLE_MKRD=y -CONFIG_NSH_DISABLE_MOUNT=y -CONFIG_NSH_DISABLE_MV=y -CONFIG_NSH_DISABLE_PUT=y -CONFIG_NSH_DISABLE_PWD=y -CONFIG_NSH_DISABLE_RM=y -CONFIG_NSH_DISABLE_RMDIR=y -CONFIG_NSH_DISABLE_SET=y -CONFIG_NSH_DISABLE_SLEEP=y -CONFIG_NSH_DISABLE_SOURCE=y -CONFIG_NSH_DISABLE_TEST=y -CONFIG_NSH_DISABLE_TIME=y -CONFIG_NSH_DISABLE_UMOUNT=y -CONFIG_NSH_DISABLE_UNAME=y -CONFIG_NSH_DISABLE_UNSET=y -CONFIG_NSH_DISABLE_USLEEP=y -CONFIG_NSH_DISABLE_WGET=y -CONFIG_NSH_DISABLE_XD=y -CONFIG_NSH_FILEIOSIZE=256 -CONFIG_NSH_READLINE=y -CONFIG_POSIX_SPAWN_DEFAULT_STACKSIZE=512 -CONFIG_PTHREAD_STACK_DEFAULT=1024 -CONFIG_PTHREAD_STACK_MIN=1024 -CONFIG_RAM_SIZE=12288 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=6 -CONFIG_START_MONTH=12 -CONFIG_START_YEAR=2011 -CONFIG_STM32_CCMEXCLUDE=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_PWR=y -CONFIG_STM32_USART2=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/nucleo-f334r8/configs/spwm1/defconfig b/boards/arm/stm32/nucleo-f334r8/configs/spwm1/defconfig deleted file mode 100644 index 37daa3d7509e5..0000000000000 --- a/boards/arm/stm32/nucleo-f334r8/configs/spwm1/defconfig +++ /dev/null @@ -1,73 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="nucleo-f334r8" -CONFIG_ARCH_BOARD_NUCLEO_F334R8=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F334R8=y -CONFIG_ARCH_HIPRI_INTERRUPT=y -CONFIG_ARCH_RAMVECTORS=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARDCTL=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_DISABLE_ENVIRON=y -CONFIG_DISABLE_MQUEUE=y -CONFIG_DISABLE_POSIX_TIMERS=y -CONFIG_FDCLONE_STDIO=y -CONFIG_INIT_ENTRYPOINT="spwm_main" -CONFIG_INIT_STACKSIZE=1024 -CONFIG_INTELHEX_BINARY=y -CONFIG_LIBM=y -CONFIG_NAME_MAX=16 -CONFIG_NUCLEOF334R8_SPWM=y -CONFIG_NUCLEOF334R8_SPWM_PHASE_NUM=3 -CONFIG_NUCLEOF334R8_SPWM_USE_HRTIM1=y -CONFIG_POSIX_SPAWN_DEFAULT_STACKSIZE=512 -CONFIG_PTHREAD_STACK_DEFAULT=1024 -CONFIG_PTHREAD_STACK_MIN=1024 -CONFIG_RAM_SIZE=12288 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=6 -CONFIG_START_MONTH=12 -CONFIG_START_YEAR=2011 -CONFIG_STM32_CCMEXCLUDE=y -CONFIG_STM32_HRTIM1=y -CONFIG_STM32_HRTIM_CLK_FROM_PLL=y -CONFIG_STM32_HRTIM_DISABLE_CHARDRV=y -CONFIG_STM32_HRTIM_INTERRUPTS=y -CONFIG_STM32_HRTIM_MASTER=y -CONFIG_STM32_HRTIM_MASTER_IRQ=y -CONFIG_STM32_HRTIM_NO_ENABLE_TIMERS=y -CONFIG_STM32_HRTIM_PWM=y -CONFIG_STM32_HRTIM_TIMA=y -CONFIG_STM32_HRTIM_TIMA_PWM=y -CONFIG_STM32_HRTIM_TIMA_PWM_CH1=y -CONFIG_STM32_HRTIM_TIMB=y -CONFIG_STM32_HRTIM_TIMB_PWM=y -CONFIG_STM32_HRTIM_TIMB_PWM_CH1=y -CONFIG_STM32_HRTIM_TIMC=y -CONFIG_STM32_HRTIM_TIMC_PWM=y -CONFIG_STM32_HRTIM_TIMC_PWM_CH1=y -CONFIG_STM32_HRTIM_TIMD=y -CONFIG_STM32_HRTIM_TIMD_PWM=y -CONFIG_STM32_HRTIM_TIMD_PWM_CH1=y -CONFIG_STM32_HRTIM_TIME=y -CONFIG_STM32_HRTIM_TIME_PWM=y -CONFIG_STM32_HRTIM_TIME_PWM_CH1=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_PWR=y -CONFIG_STM32_USART2=y -CONFIG_SYSTEM_READLINE=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/nucleo-f334r8/configs/spwm2/defconfig b/boards/arm/stm32/nucleo-f334r8/configs/spwm2/defconfig deleted file mode 100644 index d238c8b4564f3..0000000000000 --- a/boards/arm/stm32/nucleo-f334r8/configs/spwm2/defconfig +++ /dev/null @@ -1,64 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="nucleo-f334r8" -CONFIG_ARCH_BOARD_NUCLEO_F334R8=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F334R8=y -CONFIG_ARCH_HIPRI_INTERRUPT=y -CONFIG_ARCH_RAMVECTORS=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARDCTL=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_DEBUG_FULLOPT=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_DISABLE_ENVIRON=y -CONFIG_DISABLE_MQUEUE=y -CONFIG_DISABLE_POSIX_TIMERS=y -CONFIG_FDCLONE_STDIO=y -CONFIG_INIT_ENTRYPOINT="spwm_main" -CONFIG_INIT_STACKSIZE=1024 -CONFIG_INTELHEX_BINARY=y -CONFIG_LIBM=y -CONFIG_NAME_MAX=16 -CONFIG_NUCLEOF334R8_SPWM=y -CONFIG_NUCLEOF334R8_SPWM_PHASE_NUM=4 -CONFIG_POSIX_SPAWN_DEFAULT_STACKSIZE=512 -CONFIG_PTHREAD_STACK_DEFAULT=1024 -CONFIG_PTHREAD_STACK_MIN=1024 -CONFIG_RAM_SIZE=12288 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=6 -CONFIG_START_MONTH=12 -CONFIG_START_YEAR=2011 -CONFIG_STM32_CCMEXCLUDE=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_PWM_LL_OPS=y -CONFIG_STM32_PWM_MULTICHAN=y -CONFIG_STM32_PWR=y -CONFIG_STM32_TIM1=y -CONFIG_STM32_TIM1_CH1OUT=y -CONFIG_STM32_TIM1_CH2OUT=y -CONFIG_STM32_TIM1_CH3OUT=y -CONFIG_STM32_TIM1_CH4OUT=y -CONFIG_STM32_TIM1_CHANNEL1=y -CONFIG_STM32_TIM1_CHANNEL2=y -CONFIG_STM32_TIM1_CHANNEL3=y -CONFIG_STM32_TIM1_CHANNEL4=y -CONFIG_STM32_TIM1_PWM=y -CONFIG_STM32_TIM6=y -CONFIG_STM32_USART2=y -CONFIG_SYSTEM_READLINE=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/nucleo-f334r8/include/board.h b/boards/arm/stm32/nucleo-f334r8/include/board.h deleted file mode 100644 index e437be709a153..0000000000000 --- a/boards/arm/stm32/nucleo-f334r8/include/board.h +++ /dev/null @@ -1,344 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f334r8/include/board.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __BOARDS_ARM_STM32_NUCLEO_F334R8_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32_NUCLEO_F334R8_INCLUDE_BOARD_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#ifndef __ASSEMBLY__ -# include -# include -#endif - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Clocking *****************************************************************/ - -/* HSI - Internal 8 MHz RC Oscillator - * LSI - 32 KHz RC - * HSE - 8 MHz from MCO output of ST-LINK - * LSE - 32.768 kHz - */ - -#define STM32_BOARD_XTAL 8000000ul - -#define STM32_HSI_FREQUENCY 8000000ul -#define STM32_LSI_FREQUENCY 32000 /* Between 30kHz and 60kHz */ -#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL -#define STM32_LSE_FREQUENCY 32768 /* X2 on board */ - -/* PLL source is HSE/1, PLL multiplier is 9: PLL frequency is - * 8MHz (XTAL) x 9 = 72MHz - */ - -#define STM32_CFGR_PLLSRC RCC_CFGR_PLLSRC -#define STM32_CFGR_PLLXTPRE 0 -#define STM32_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx9 -#define STM32_PLL_FREQUENCY (9*STM32_BOARD_XTAL) - -/* Use the PLL and set the SYSCLK source to be the PLL */ - -#define STM32_SYSCLK_SW RCC_CFGR_SW_PLL -#define STM32_SYSCLK_SWS RCC_CFGR_SWS_PLL -#define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY - -/* AHB clock (HCLK) is SYSCLK (72MHz) */ - -#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK -#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY - -/* APB2 clock (PCLK2) is HCLK (72MHz) */ - -#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK -#define STM32_PCLK2_FREQUENCY STM32_HCLK_FREQUENCY -#define STM32_APB2_CLKIN (STM32_PCLK2_FREQUENCY) - -/* APB2 timers 1, 8, 15-17 and HRTIM1 will receive PCLK2. */ - -/* Timers driven from APB2 will be PCLK2 */ - -#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB1_TIM15_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB1_TIM16_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB1_TIM17_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB1_THRTIM1_CLKIN (STM32_PCLK2_FREQUENCY) - -/* APB1 clock (PCLK1) is HCLK/2 (36MHz) */ - -#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd2 -#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/2) - -/* APB1 timers 2-7 will be twice PCLK1 */ - -#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) - -/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx - * otherwise frequency is 2xAPBx. - * Note: TIM1,8 are on APB2, others on APB1 - */ - -#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM15_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM16_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM17_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM2_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM3_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM5_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM6_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM7_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_HRTIM1_FREQUENCY STM32_HCLK_FREQUENCY - -/* LED definitions **********************************************************/ - -/* The Nucleo F334R8 board has three LEDs. Two of these are controlled by - * logic on the board and are not available for software control: - * - * LD1 COM: LD1 default status is red. LD1 turns to green to indicate that - * communications are in progress between the PC and the - * ST-LINK/V2-1. - * LD3 PWR: red LED indicates that the board is powered. - * - * And one can be controlled by software: - * - * User LD2: green LED is a user LED connected to the I/O PA5 of the - * STM32F334R8. - * - * If CONFIG_ARCH_LEDS is not defined, then the user can control the LED in - * any way. The following definition is used to access the LED. - */ - -/* LED index values for use with board_userled() */ - -#define BOARD_LED1 0 /* User LD2 */ -#define BOARD_NLEDS 1 - -/* LED bits for use with board_userled_all() */ - -#define BOARD_LED1_BIT (1 << BOARD_LED1) - -/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the LED on board - * the Nucleo F334R8. The following definitions describe how NuttX controls - * the LED: - * - * SYMBOL Meaning LED1 state - * ------------------ ----------------------- ---------- - * LED_STARTED NuttX has been started OFF - * LED_HEAPALLOCATE Heap has been allocated OFF - * LED_IRQSENABLED Interrupts enabled OFF - * LED_STACKCREATED Idle stack created ON - * LED_INIRQ In an interrupt No change - * LED_SIGNAL In a signal handler No change - * LED_ASSERTION An assertion failed No change - * LED_PANIC The system has crashed Blinking - * LED_IDLE STM32 is in sleep mode Not used - */ - -#define LED_STARTED 0 -#define LED_HEAPALLOCATE 0 -#define LED_IRQSENABLED 0 -#define LED_STACKCREATED 1 -#define LED_INIRQ 2 -#define LED_SIGNAL 2 -#define LED_ASSERTION 2 -#define LED_PANIC 1 - -/* Button definitions *******************************************************/ - -/* The Nucleo F334R8 supports two buttons; only one button is controllable - * by software: - * - * B1 USER: user button connected to the I/O PC13 of the STM32F334R8. - * B2 RESET: push button connected to NRST is used to RESET the - * STM32F334R8. - */ - -#define BUTTON_USER 0 -#define NUM_BUTTONS 1 - -#define BUTTON_USER_BIT (1 << BUTTON_USER) - -/* Alternate function pin selections ****************************************/ - -/* CAN */ - -#define GPIO_CAN1_RX (GPIO_CAN_RX_2|GPIO_SPEED_50MHz) -#define GPIO_CAN1_TX (GPIO_CAN_TX_2|GPIO_SPEED_50MHz) - -/* I2C */ - -#define GPIO_I2C1_SCL (GPIO_I2C1_SCL_3|GPIO_SPEED_50MHz) -#define GPIO_I2C1_SDA (GPIO_I2C1_SDA_3|GPIO_SPEED_50MHz) - -/* SPI */ - -#define GPIO_SPI1_MISO (GPIO_SPI1_MISO_1|GPIO_SPEED_50MHz) -#define GPIO_SPI1_MOSI (GPIO_SPI1_MOSI_1|GPIO_SPEED_50MHz) -#define GPIO_SPI1_SCK (GPIO_SPI1_SCK_1|GPIO_SPEED_50MHz) - -/* TIM */ - -#define GPIO_TIM2_CH2OUT (GPIO_TIM2_CH2OUT_2|GPIO_SPEED_50MHz) -#define GPIO_TIM2_CH3OUT (GPIO_TIM2_CH3OUT_3|GPIO_SPEED_50MHz) - -#define GPIO_TIM3_CH1OUT (GPIO_TIM3_CH1OUT_2|GPIO_SPEED_50MHz) -#define GPIO_TIM3_CH2OUT (GPIO_TIM3_CH2OUT_4|GPIO_SPEED_50MHz) - -#define GPIO_TIM4_CH1OUT (GPIO_TIM4_CH1OUT_2|GPIO_SPEED_50MHz) - -/* USART */ - -/* By default the USART2 is connected to STLINK Virtual COM Port: - * USART2_RX - PA3 - * USART2_TX - PA2 - */ - -#define GPIO_USART2_RX (GPIO_USART2_RX_1|GPIO_SPEED_50MHz) /* PA3 */ -#define GPIO_USART2_TX (GPIO_USART2_TX_1|GPIO_SPEED_50MHz) /* PA2 */ - -#define GPIO_USART1_RX (GPIO_USART1_RX_1|GPIO_SPEED_50MHz) /* PA10 */ -#define GPIO_USART1_TX (GPIO_USART1_TX_1|GPIO_SPEED_50MHz) /* PA9 */ - -/* COMP */ - -/* OPAMP */ - -#define OPAMP2_VMSEL OPAMP2_VMSEL_PC5 -#define OPAMP2_VPSEL OPAMP2_VPSEL_PB14 - -/* Configuration specific to high priority interrupts example: - * - HRTIM Timer A trigger for ADC if DMA transfer and HRTIM - * - TIM1 CC1 trigger for ADC if DMA transfer and TIM1 PWM - * - ADC DMA transfer on DMA1_CH1 - */ - -#ifdef CONFIG_NUCLEOF334R8_HIGHPRI - -#if defined(CONFIG_STM32_HRTIM1) && defined(CONFIG_STM32_ADC1_DMA) - -/* HRTIM - ADC trigger */ - -#define HRTIM_TIMA_PRESCALER HRTIM_PRESCALER_128 -#define HRTIM_TIMA_MODE HRTIM_MODE_CONT -#define HRTIM_TIMA_UPDATE 0 -#define HRTIM_TIMA_RESET 0 - -#define HRTIM_ADC_TRG1 HRTIM_ADCTRG13_APER - -#endif /* CONFIG_STM32_HRTIM1 && CONFIG_STM32_ADC1_DMA*/ -#endif /* CONFIG_NUCLEOF334R8_HIGHPRI */ - -#ifdef CONFIG_NUCLEOF334R8_SPWM -# ifdef CONFIG_NUCLEOF334R8_SPWM_USE_TIM1 - -/* TIM1 PWM configuration ***************************************************/ - -# define GPIO_TIM1_CH1OUT (GPIO_TIM1_CH1OUT_1|GPIO_SPEED_50MHz) /* TIM1 CH1 - PA8 */ -# define GPIO_TIM1_CH1NOUT (GPIO_TIM1_CH1N_3|GPIO_SPEED_50MHz) /* TIM1 CH1N - PA7 */ - /* TIM1 CH2 - PA9 */ -# define GPIO_TIM1_CH2NOUT (GPIO_TIM1_CH2N_2|GPIO_SPEED_50MHz) /* TIM1 CH2N - PB0 */ -# define GPIO_TIM1_CH3OUT (GPIO_TIM1_CH3OUT_1|GPIO_SPEED_50MHz) /* TIM1 CH3 - PA10 */ -# define GPIO_TIM1_CH3NOUT (GPIO_TIM1_CH3N_2|GPIO_SPEED_50MHz) /* TIM1 CH3N - PB1 */ -# define GPIO_TIM1_CH4OUT (GPIO_TIM1_CH4OUT_1|GPIO_SPEED_50MHz) /* TIM1 CH4 - PA11 */ -# endif - -# ifdef CONFIG_NUCLEOF334R8_SPWM_USE_HRTIM1 - -/* HRTIM configuration ******************************************************/ - -# define HRTIM_MASTER_PRESCALER HRTIM_PRESCALER_128 -# define HRTIM_MASTER_MODE HRTIM_MODE_CONT - -# define HRTIM_TIMA_PRESCALER HRTIM_PRESCALER_128 -# define HRTIM_TIMA_MODE (HRTIM_MODE_CONT | HRTIM_MODE_PRELOAD) -# define HRTIM_TIMA_CH1_SET HRTIM_OUT_SET_PER -# define HRTIM_TIMA_CH1_RST HRTIM_OUT_RST_CMP1 -# define HRTIM_TIMA_UPDATE HRTIM_UPDATE_MSTU -# define HRTIM_TIMA_RESET 0 - -# define HRTIM_TIMB_PRESCALER HRTIM_PRESCALER_128 -# define HRTIM_TIMB_MODE (HRTIM_MODE_CONT | HRTIM_MODE_PRELOAD) -# define HRTIM_TIMB_CH1_SET HRTIM_OUT_SET_PER -# define HRTIM_TIMB_CH1_RST HRTIM_OUT_RST_CMP1 -# define HRTIM_TIMB_UPDATE HRTIM_UPDATE_MSTU -# define HRTIM_TIMB_RESET 0 - -# define HRTIM_TIMC_PRESCALER HRTIM_PRESCALER_128 -# define HRTIM_TIMC_MODE (HRTIM_MODE_CONT | HRTIM_MODE_PRELOAD) -# define HRTIM_TIMC_CH1_SET HRTIM_OUT_SET_PER -# define HRTIM_TIMC_CH1_RST HRTIM_OUT_RST_CMP1 -# define HRTIM_TIMC_UPDATE HRTIM_UPDATE_MSTU -# define HRTIM_TIMC_RESET 0 - -# define HRTIM_TIMD_PRESCALER HRTIM_PRESCALER_128 -# define HRTIM_TIMD_MODE (HRTIM_MODE_CONT | HRTIM_MODE_PRELOAD) -# define HRTIM_TIMD_CH1_SET HRTIM_OUT_SET_PER -# define HRTIM_TIMD_CH1_RST HRTIM_OUT_RST_CMP1 -# define HRTIM_TIMD_UPDATE HRTIM_UPDATE_MSTU -# define HRTIM_TIMD_RESET 0 - -# define HRTIM_TIME_PRESCALER HRTIM_PRESCALER_128 -# define HRTIM_TIME_MODE (HRTIM_MODE_CONT | HRTIM_MODE_PRELOAD) -# define HRTIM_TIME_CH1_SET HRTIM_OUT_SET_PER -# define HRTIM_TIME_CH1_RST HRTIM_OUT_RST_CMP1 -# define HRTIM_TIME_UPDATE HRTIM_UPDATE_MSTU -# define HRTIM_TIME_RESET 0 - -# define HRTIM_MASTER_IRQ HRTIM_IRQ_MCMP1 -# endif - -#endif /* CONFIG_NUCLEOF334R8_SPWM */ - -/* DMA channels *************************************************************/ - -/* ADC */ - -#define ADC1_DMA_CHAN DMACHAN_ADC1 /* DMA1_CH1 */ - -/* TIM1 CH2 alias (used by spwm2 config) */ - -#define GPIO_TIM1_CH2OUT (GPIO_TIM1_CH2OUT_0|GPIO_SPEED_50MHz) - -/* HRTIM1 */ - -#define GPIO_HRTIM1_CHA1 GPIO_HRTIM1_CHA1_0 -#define GPIO_HRTIM1_CHA2 GPIO_HRTIM1_CHA2_0 -#define GPIO_HRTIM1_CHB1 GPIO_HRTIM1_CHB1_0 -#define GPIO_HRTIM1_CHB2 GPIO_HRTIM1_CHB2_0 -#define GPIO_HRTIM1_CHC1 GPIO_HRTIM1_CHC1_0 -#define GPIO_HRTIM1_CHC2 GPIO_HRTIM1_CHC2_0 -#define GPIO_HRTIM1_CHD1 GPIO_HRTIM1_CHD1_0 -#define GPIO_HRTIM1_CHD2 GPIO_HRTIM1_CHD2_0 -#define GPIO_HRTIM1_CHE1 GPIO_HRTIM1_CHE1_0 -#define GPIO_HRTIM1_CHE2 GPIO_HRTIM1_CHE2_0 - -#endif /* __BOARDS_ARM_STM32_NUCLEO_F334R8_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32/nucleo-f334r8/scripts/Make.defs b/boards/arm/stm32/nucleo-f334r8/scripts/Make.defs deleted file mode 100644 index 24b7d458136a4..0000000000000 --- a/boards/arm/stm32/nucleo-f334r8/scripts/Make.defs +++ /dev/null @@ -1,41 +0,0 @@ -############################################################################ -# boards/arm/stm32/nucleo-f334r8/scripts/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/.config -include $(TOPDIR)/tools/Config.mk -include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs - -LDSCRIPT = ld.script -ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) - -ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 - -CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) -CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) -CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -AFLAGS := $(CFLAGS) -D__ASSEMBLY__ - -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections -LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32/nucleo-f334r8/scripts/ld.script b/boards/arm/stm32/nucleo-f334r8/scripts/ld.script deleted file mode 100644 index 5f4e9d8ae7180..0000000000000 --- a/boards/arm/stm32/nucleo-f334r8/scripts/ld.script +++ /dev/null @@ -1,127 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f334r8/scripts/ld.script - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* The STM32F334R8 has 64Kb of FLASH beginning at address 0x0800:0000, - * 12Kb of SRAM and 4Kb of CCM SRAM. - * - * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 - * where the code expects to begin execution by jumping to the entry point in - * the 0x0800:0000 address range. - */ - -MEMORY -{ - flash (rx) : ORIGIN = 0x08000000, LENGTH = 64K - sram (rwx) : ORIGIN = 0x20000000, LENGTH = 12K -} - -OUTPUT_ARCH(arm) -EXTERN(_vectors) -ENTRY(_stext) -SECTIONS -{ - .text : { - _stext = ABSOLUTE(.); - *(.vectors) - *(.text .text.*) - *(.fixup) - *(.gnu.warning) - *(.rodata .rodata.*) - *(.gnu.linkonce.t.*) - *(.glue_7) - *(.glue_7t) - *(.got) - *(.gcc_except_table) - *(.gnu.linkonce.r.*) - _etext = ABSOLUTE(.); - } > flash - - .init_section : ALIGN(4) { - _sinit = ABSOLUTE(.); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) - KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) - _einit = ABSOLUTE(.); - } > flash - - .ARM.extab : ALIGN(4) { - *(.ARM.extab*) - } > flash - - .ARM.exidx : ALIGN(4) { - __exidx_start = ABSOLUTE(.); - *(.ARM.exidx*) - __exidx_end = ABSOLUTE(.); - } > flash - - .tdata : { - _stdata = ABSOLUTE(.); - *(.tdata .tdata.* .gnu.linkonce.td.*); - _etdata = ABSOLUTE(.); - } > flash - - .tbss : { - _stbss = ABSOLUTE(.); - *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); - _etbss = ABSOLUTE(.); - } > flash - - _eronly = ABSOLUTE(.); - - /* The RAM vector table (if present) should lie at the beginning of SRAM */ - - .ram_vectors : { - *(.ram_vectors) - } > sram - - .data : ALIGN(4) { - _sdata = ABSOLUTE(.); - *(.data .data.*) - *(.gnu.linkonce.d.*) - CONSTRUCTORS - . = ALIGN(4); - _edata = ABSOLUTE(.); - } > sram AT > flash - - .bss : ALIGN(4) { - _sbss = ABSOLUTE(.); - *(.bss .bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - . = ALIGN(4); - _ebss = ABSOLUTE(.); - } > sram - - /* Stabs debugging sections. */ - - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_info 0 : { *(.debug_info) } - .debug_line 0 : { *(.debug_line) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_aranges 0 : { *(.debug_aranges) } -} diff --git a/boards/arm/stm32/nucleo-f334r8/src/CMakeLists.txt b/boards/arm/stm32/nucleo-f334r8/src/CMakeLists.txt deleted file mode 100644 index 30f5bccef47a4..0000000000000 --- a/boards/arm/stm32/nucleo-f334r8/src/CMakeLists.txt +++ /dev/null @@ -1,59 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/nucleo-f334r8/src/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -set(SRCS stm32_boot.c) - -if(CONFIG_ARCH_LEDS) - list(APPEND SRCS stm32_autoleds.c) -endif() - -if(CONFIG_ADC) - list(APPEND SRCS stm32_adc.c) -endif() - -if(CONFIG_DAC) - list(APPEND SRCS stm32_dac.c) -endif() - -if(CONFIG_STM32_HRTIM) - list(APPEND SRCS stm32_hrtim.c) -endif() - -if(CONFIG_COMP) - list(APPEND SRCS stm32_comp.c) -endif() - -if(CONFIG_OPAMP) - list(APPEND SRCS stm32_opamp.c) -endif() - -if(CONFIG_NUCLEOF334R8_HIGHPRI) - list(APPEND SRCS stm32_highpri.c) -endif() - -if(CONFIG_NUCLEOF334R8_SPWM) - list(APPEND SRCS stm32_spwm.c) -endif() - -target_sources(board PRIVATE ${SRCS}) - -set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/ld.script") diff --git a/boards/arm/stm32/nucleo-f334r8/src/Make.defs b/boards/arm/stm32/nucleo-f334r8/src/Make.defs deleted file mode 100644 index 97dbc7a0f51fd..0000000000000 --- a/boards/arm/stm32/nucleo-f334r8/src/Make.defs +++ /dev/null @@ -1,61 +0,0 @@ -############################################################################ -# boards/arm/stm32/nucleo-f334r8/src/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/Make.defs - -CSRCS = stm32_boot.c - -ifeq ($(CONFIG_ARCH_LEDS),y) -CSRCS += stm32_autoleds.c -endif - -ifeq ($(CONFIG_ADC),y) -CSRCS += stm32_adc.c -endif - -ifeq ($(CONFIG_DAC),y) -CSRCS += stm32_dac.c -endif - -ifeq ($(CONFIG_STM32_HRTIM),y) -CSRCS += stm32_hrtim.c -endif - -ifeq ($(CONFIG_COMP),y) -CSRCS += stm32_comp.c -endif - -ifeq ($(CONFIG_OPAMP),y) -CSRCS += stm32_opamp.c -endif - -ifeq ($(CONFIG_NUCLEOF334R8_HIGHPRI),y) -CSRCS += stm32_highpri.c -endif - -ifeq ($(CONFIG_NUCLEOF334R8_SPWM),y) -CSRCS += stm32_spwm.c -endif - -DEPPATH += --dep-path board -VPATH += :board -CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/nucleo-f334r8/src/stm32_adc.c b/boards/arm/stm32/nucleo-f334r8/src/stm32_adc.c deleted file mode 100644 index a369fe2f4fa1e..0000000000000 --- a/boards/arm/stm32/nucleo-f334r8/src/stm32_adc.c +++ /dev/null @@ -1,242 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f334r8/src/stm32_adc.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include "stm32.h" - -#if defined(CONFIG_ADC) && (defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2)) - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -/* 1 or 2 ADC devices (DEV1, DEV2) */ - -#if defined(CONFIG_STM32_ADC1) -# define DEV1_PORT 1 -#endif - -#if defined(CONFIG_STM32_ADC2) -# if defined(DEV1_PORT) -# define DEV2_PORT 2 -# else -# define DEV1_PORT 2 -# endif -#endif - -/* The number of ADC channels in the conversion list */ - -/* TODO DMA */ - -#define ADC1_NCHANNELS 3 -#define ADC2_NCHANNELS 3 - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* DEV 1 */ - -#if DEV1_PORT == 1 - -#define DEV1_NCHANNELS ADC1_NCHANNELS - -/* Identifying number of each ADC channel (even if NCHANNELS is less ) */ - -static const uint8_t g_chanlist1[3] = -{ - 1, - 2, - 11 -}; - -/* Configurations of pins used by each ADC channel */ - -static const uint32_t g_pinlist1[3] = -{ - GPIO_ADC1_IN1_0, /* PA0/A0 */ - GPIO_ADC1_IN2_0, /* PA1/A1 */ - GPIO_ADC1_IN11_0, /* PB0/A3 */ -}; - -#elif DEV1_PORT == 2 - -#define DEV1_NCHANNELS ADC2_NCHANNELS - -/* Identifying number of each ADC channel */ - -static const uint8_t g_chanlist1[3] = -{ - 1, - 6, - 7 -}; - -/* Configurations of pins used by each ADC channel */ - -static const uint32_t g_pinlist1[3] = -{ - GPIO_ADC2_IN1_0, /* PA4/A2 */ - GPIO_ADC2_IN7_0, /* PC1/A4 */ - GPIO_ADC2_IN6_0, /* PC0/A5 */ -}; - -#endif /* DEV1_PORT == 1 */ - -#ifdef DEV2_PORT - -/* DEV 2 */ - -#if DEV2_PORT == 2 - -#define DEV2_NCHANNELS ADC2_NCHANNELS - -/* Identifying number of each ADC channel */ - -static const uint8_t g_chanlist2[3] = -{ - 1, - 6, - 7 -}; - -/* Configurations of pins used by each ADC channel */ - -static const uint32_t g_pinlist2[3] = -{ - GPIO_ADC2_IN1_0, /* PA4/A2 */ - GPIO_ADC2_IN7_0, /* PC1/A4 */ - GPIO_ADC2_IN6_0, /* PC0/A5 */ -}; - -#endif /* DEV2_PORT == 2 */ -#endif /* DEV2_PORT */ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_adc_setup - * - * Description: - * Initialize ADC and register the ADC driver. - * - ****************************************************************************/ - -int stm32_adc_setup(void) -{ - static bool initialized = false; - struct adc_dev_s *adc; - int ret; - int i; - - /* Check if we have already initialized */ - - if (!initialized) - { - /* DEV1 */ - - /* Configure the pins as analog inputs for the selected channels */ - - for (i = 0; i < DEV1_NCHANNELS; i++) - { - stm32_configgpio(g_pinlist1[i]); - } - - /* Call stm32_adcinitialize() to get an instance of the ADC interface */ - - adc = stm32_adcinitialize(DEV1_PORT, g_chanlist1, DEV1_NCHANNELS); - if (adc == NULL) - { - aerr("ERROR: Failed to get ADC interface 1\n"); - return -ENODEV; - } - - /* Register the ADC driver at "/dev/adc0" */ - - ret = adc_register("/dev/adc0", adc); - if (ret < 0) - { - aerr("ERROR: adc_register /dev/adc0 failed: %d\n", ret); - return ret; - } - -#ifdef DEV2_PORT - - /* DEV2 */ - - /* Configure the pins as analog inputs for the selected channels */ - - for (i = 0; i < DEV2_NCHANNELS; i++) - { - stm32_configgpio(g_pinlist2[i]); - } - - /* Call stm32_adcinitialize() to get an instance of the ADC interface */ - - adc = stm32_adcinitialize(DEV2_PORT, g_chanlist2, DEV2_NCHANNELS); - if (adc == NULL) - { - aerr("ERROR: Failed to get ADC interface 2\n"); - return -ENODEV; - } - - /* Register the ADC driver at "/dev/adc1" */ - - ret = adc_register("/dev/adc1", adc); - if (ret < 0) - { - aerr("ERROR: adc_register /dev/adc1 failed: %d\n", ret); - return ret; - } -#endif - - initialized = true; - } - - return OK; -} - -#endif /* CONFIG_ADC && (CONFIG_STM32_ADC1 || CONFIG_STM32_ADC2) */ diff --git a/boards/arm/stm32/nucleo-f334r8/src/stm32_autoleds.c b/boards/arm/stm32/nucleo-f334r8/src/stm32_autoleds.c deleted file mode 100644 index e2088b7ea6f88..0000000000000 --- a/boards/arm/stm32/nucleo-f334r8/src/stm32_autoleds.c +++ /dev/null @@ -1,80 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f334r8/src/stm32_autoleds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include "stm32.h" -#include "nucleo-f334r8.h" - -#ifdef CONFIG_ARCH_LEDS - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_autoled_initialize - ****************************************************************************/ - -void board_autoled_initialize(void) -{ - /* Configure LED1 GPIO for output */ - - stm32_configgpio(GPIO_LED1); -} - -/**************************************************************************** - * Name: board_autoled_on - ****************************************************************************/ - -void board_autoled_on(int led) -{ - if (led == BOARD_LED1) - { - stm32_gpiowrite(GPIO_LED1, true); - } -} - -/**************************************************************************** - * Name: board_autoled_off - ****************************************************************************/ - -void board_autoled_off(int led) -{ - if (led == BOARD_LED1) - { - stm32_gpiowrite(GPIO_LED1, false); - } -} - -#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/nucleo-f334r8/src/stm32_boot.c b/boards/arm/stm32/nucleo-f334r8/src/stm32_boot.c deleted file mode 100644 index 6387f93c8a38c..0000000000000 --- a/boards/arm/stm32/nucleo-f334r8/src/stm32_boot.c +++ /dev/null @@ -1,162 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f334r8/src/stm32_boot.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include -#include - -#include "nucleo-f334r8.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#undef HAVE_LEDS -#undef HAVE_DAC - -#if !defined(CONFIG_ARCH_LEDS) && defined(CONFIG_USERLED_LOWER) -# define HAVE_LEDS 1 -#endif - -#if defined(CONFIG_DAC) -# define HAVE_DAC1 1 -# define HAVE_DAC2 1 -#endif - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_boardinitialize - * - * Description: - * All STM32 architectures must provide the following entry point. This - * entry point is called early in the initialization -- after all memory - * has been configured and mapped but before any devices have been - * initialized. - * - ****************************************************************************/ - -void stm32_boardinitialize(void) -{ -#ifdef CONFIG_ARCH_LEDS - /* Configure on-board LEDs if LED support has been selected. */ - - board_autoled_initialize(); -#endif -} - -/**************************************************************************** - * Name: board_late_initialize - * - * Description: - * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional - * initialization call will be performed in the boot-up sequence to a - * function called board_late_initialize(). board_late_initialize() will - * be called immediately after up_initialize() is called and just before - * the initial application is started. This additional initialization - * phase may be used, for example, to initialize board-specific device - * drivers. - * - ****************************************************************************/ - -#ifdef CONFIG_BOARD_LATE_INITIALIZE -void board_late_initialize(void) -{ - int ret; - -#ifdef HAVE_LEDS - /* Register the LED driver */ - - ret = userled_lower_initialize(LED_DRIVER_PATH); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: userled_lower_initialize() failed: %d\n", ret); - return; - } -#endif - -#ifdef CONFIG_ADC - /* Initialize ADC and register the ADC driver. */ - - ret = stm32_adc_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_adc_setup failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_DAC - /* Initialize DAC and register the DAC driver. */ - - ret = stm32_dac_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_dac_setup failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_COMP - /* Initialize COMP and register the COMP driver. */ - - ret = stm32_comp_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_comp_setup failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_OPAMP - /* Initialize OPAMP and register the OPAMP driver. */ - - ret = stm32_opamp_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_opamp_setup failed: %d\n", ret); - } -#endif - - UNUSED(ret); -} -#endif diff --git a/boards/arm/stm32/nucleo-f334r8/src/stm32_comp.c b/boards/arm/stm32/nucleo-f334r8/src/stm32_comp.c deleted file mode 100644 index 1175e6b17ba3a..0000000000000 --- a/boards/arm/stm32/nucleo-f334r8/src/stm32_comp.c +++ /dev/null @@ -1,122 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f334r8/src/stm32_comp.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include "stm32.h" - -#if defined(CONFIG_COMP) && (defined(CONFIG_STM32_COMP2) || \ - defined(CONFIG_STM32_COMP4) || \ - defined(CONFIG_STM32_COMP6)) - -#ifdef CONFIG_STM32_COMP2 -# if defined(CONFIG_STM32_COMP4) || defined(CONFIG_STM32_COMP6) -# error "Currently only one COMP device supported" -# endif -#elif CONFIG_STM32_COMP4 -# if defined(CONFIG_STM32_COMP2) || defined(CONFIG_STM32_COMP6) -# error "Currently only one COMP device supported" -# endif -#elif CONFIG_STM32_COMP6 -# if defined(CONFIG_STM32_COMP2) || defined(CONFIG_STM32_COMP4) -# error "Currently only one COMP device supported" -# endif -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_comp_setup - * - * Description: - * Initialize COMP - * - ****************************************************************************/ - -int stm32_comp_setup(void) -{ - static bool initialized = false; - struct comp_dev_s *comp = NULL; - int ret; - - if (!initialized) - { - /* Get the comparator interface */ - -#ifdef CONFIG_STM32_COMP2 - comp = stm32_compinitialize(2); - if (comp == NULL) - { - aerr("ERROR: Failed to get COMP%d interface\n", 2); - return -ENODEV; - } -#endif - -#ifdef CONFIG_STM32_COMP4 - comp = stm32_compinitialize(4); - if (comp == NULL) - { - aerr("ERROR: Failed to get COMP%d interface\n", 4); - return -ENODEV; - } -#endif - -#ifdef CONFIG_STM32_COMP6 - comp = stm32_compinitialize(6); - if (comp == NULL) - { - aerr("ERROR: Failed to get COMP%d interface\n", 6); - return -ENODEV; - } -#endif - - /* Register the comparator character driver at /dev/comp0 */ - - ret = comp_register("/dev/comp0", comp); - if (ret < 0) - { - aerr("ERROR: comp_register failed: %d\n", ret); - return ret; - } - - initialized = true; - } - - return OK; -} - -#endif /* CONFIG_COMP && (CONFIG_STM32_COMP1 || - * CONFIG_STM32_COMP2 - * CONFIG_STM32_COMP6) */ diff --git a/boards/arm/stm32/nucleo-f334r8/src/stm32_highpri.c b/boards/arm/stm32/nucleo-f334r8/src/stm32_highpri.c deleted file mode 100644 index 7be598a774724..0000000000000 --- a/boards/arm/stm32/nucleo-f334r8/src/stm32_highpri.c +++ /dev/null @@ -1,586 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f334r8/src/stm32_highpri.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include - -#include -#include - -#include "arm_internal.h" -#include "ram_vectors.h" - -#include "stm32_hrtim.h" -#include "stm32_pwm.h" -#include "stm32_adc.h" -#include "stm32_dma.h" - -#include - -#ifdef CONFIG_NUCLEOF334R8_HIGHPRI - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -#ifndef CONFIG_ARCH_HIPRI_INTERRUPT -# error CONFIG_ARCH_HIPRI_INTERRUPT is required -#endif - -#ifndef CONFIG_ARCH_RAMVECTORS -# error CONFIG_ARCH_RAMVECTORS is required -#endif - -#ifndef CONFIG_ARCH_IRQPRIO -# error CONFIG_ARCH_IRQPRIO is required -#endif - -#ifndef CONFIG_ARCH_FPU -# warning Set CONFIG_ARCH_FPU for hardware FPU support -#endif - -#ifdef CONFIG_STM32_ADC1_DMA -# if defined(CONFIG_STM32_HRTIM1) && defined(CONFIG_STM32_HRTIM_TIMA) -# define HIGHPRI_HAVE_HRTIM -# endif -# if defined(CONFIG_STM32_TIM1_PWM) -# define HIGHPRI_HAVE_TIM1 -# endif -# if (CONFIG_STM32_ADC1_DMA_CFG != 1) -# error ADC1 DMA must be configured in Circular Mode -# endif -# if defined(HIGHPRI_HAVE_HRTIM) && defined(HIGHPRI_HAVE_TIM1) -# error HRTIM TIM A or TIM1 ! -# elif !defined(HIGHPRI_HAVE_HRTIM) && !defined(HIGHPRI_HAVE_TIM1) -# error "Needs HRTIM TIMA or TIM1 to trigger ADC DMA" -# endif -#endif - -#ifdef HIGHPRI_HAVE_HRTIM -# if !defined(CONFIG_STM32_HRTIM_ADC1_TRG1) || !defined(CONFIG_STM32_HRTIM_ADC) -# error -# endif -#endif - -#if (CONFIG_STM32_ADC1_INJECTED_CHAN > 0) -# if (CONFIG_STM32_ADC1_INJECTED_CHAN > 2) -# error Max 2 injected channels supported for now -# else -# define HIGHPRI_HAVE_INJECTED -# endif -#endif - -#ifdef HIGHPRI_HAVE_INJECTED -# define INJ_NCHANNELS CONFIG_STM32_ADC1_INJECTED_CHAN -#else -# define INJ_NCHANNELS (0) -#endif - -#ifndef CONFIG_STM32_ADC1_DMA -# define REG_NCHANNELS (1) -#else -# define REG_NCHANNELS (3) -#endif - -#define ADC1_NCHANNELS (REG_NCHANNELS + INJ_NCHANNELS) - -#define DEV1_PORT (1) -#define DEV1_NCHANNELS ADC1_NCHANNELS -#define ADC_REF_VOLTAGE (3.3f) -#define ADC_VAL_MAX (4095) - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/* High priority example private data */ - -struct highpri_s -{ - struct stm32_adc_dev_s *adc1; -#ifdef HIGHPRI_HAVE_HRTIM - struct hrtim_dev_s *hrtim; -#endif -#ifdef HIGHPRI_HAVE_TIM1 - struct stm32_pwm_dev_s *pwm; -#endif - volatile uint32_t cntr1; - volatile uint32_t cntr2; - volatile uint8_t current; - uint16_t r_val[REG_NCHANNELS]; - float r_volt[REG_NCHANNELS]; -#ifdef HIGHPRI_HAVE_INJECTED - uint16_t j_val[INJ_NCHANNELS]; - float j_volt[INJ_NCHANNELS]; -#endif - bool lock; -}; - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* ADC channel list */ - -static const uint8_t g_chanlist1[DEV1_NCHANNELS] = -{ - 1, -#ifdef CONFIG_STM32_ADC1_DMA - 2, - 11, -#endif -#if INJ_NCHANNELS > 0 - 7, -#endif -#if INJ_NCHANNELS > 1 - 6 -#endif -}; - -/* Configurations of pins used by ADC channel */ - -static const uint32_t g_pinlist1[DEV1_NCHANNELS] = -{ - GPIO_ADC1_IN1_0, /* PA0/A0 */ -#ifdef CONFIG_STM32_ADC1_DMA - GPIO_ADC1_IN2_0, /* PA1/A1 */ - GPIO_ADC1_IN11_0, /* PB0/A3 */ -#endif -#if INJ_NCHANNELS > 0 - GPIO_ADC1_IN7_0, /* PC1/A4 */ -#endif -#if INJ_NCHANNELS > 1 - GPIO_ADC1_IN6_0 /* PC0/A5 */ -#endif -}; - -static struct highpri_s g_highpri; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: adc12_handler - * - * Description: - * This is the handler for the high speed ADC interrupt. - * - ****************************************************************************/ - -#if !defined(CONFIG_STM32_ADC1_DMA) || defined(HIGHPRI_HAVE_INJECTED) -void adc12_handler(void) -{ - struct stm32_adc_dev_s *adc = g_highpri.adc1; - float ref = ADC_REF_VOLTAGE; - float bit = ADC_VAL_MAX; - uint32_t pending; -#ifdef HIGHPRI_HAVE_INJECTED - int i = 0; -#endif - - /* Get pending ADC interrupts */ - - pending = STM32_ADC_INT_GET(adc); - - if (g_highpri.lock == true) - { - goto irq_out; - } - -#ifndef CONFIG_STM32_ADC1_DMA - /* Regular channel end of conversion */ - - if (pending & ADC_ISR_EOC) - { - /* Increase regular sequence counter */ - - g_highpri.cntr1 += 1; - - /* Get regular data */ - - g_highpri.r_val[g_highpri.current] = STM32_ADC_REGDATA_GET(adc); - - /* Do some floating point operations */ - - g_highpri.r_volt[g_highpri.current] = - (float)g_highpri.r_val[g_highpri.current] * ref / bit; - - if (g_highpri.current >= REG_NCHANNELS - 1) - { - g_highpri.current = 0; - } - else - { - g_highpri.current += 1; - } - } -#endif - -#ifdef HIGHPRI_HAVE_INJECTED - /* Injected channel end of sequence */ - - if (pending & ADC_ISR_JEOS) - { - /* Increase injected sequence counter */ - - g_highpri.cntr2 += 1; - - /* Get injected channels */ - - for (i = 0; i < INJ_NCHANNELS; i += 1) - { - g_highpri.j_val[i] = STM32_ADC_INJDATA_GET(adc, i); - } - - /* Do some floating point operations */ - - for (i = 0; i < INJ_NCHANNELS; i += 1) - { - g_highpri.j_volt[i] = (float)g_highpri.j_val[i] * ref / bit; - } - } -#endif - -irq_out: - - /* Clear ADC pending interrupts */ - - STM32_ADC_INT_ACK(adc, pending); -} -#endif - -/**************************************************************************** - * Name: dmach1_handler - * - * Description: - * This is the handler for the high speed ADC interrupt using DMA transfer. - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_ADC1_DMA -void dma1ch1_handler(void) -{ - float ref = ADC_REF_VOLTAGE; - float bit = ADC_VAL_MAX; - uint32_t pending; - int i; - - pending = stm32_dma_intget(STM32_DMA1_CHAN1); - - if (g_highpri.lock == true) - { - goto irq_out; - } - - /* Increase regular sequence counter */ - - g_highpri.cntr1 += 1; - - for (i = 0; i < REG_NCHANNELS; i += 1) - { - /* Do some floating point operations */ - - g_highpri.r_volt[i] = (float)g_highpri.r_val[i] * ref / bit; - } - -irq_out: - - /* Clear DMA pending interrupts */ - - stm32_dma_intack(STM32_DMA1_CHAN1, pending); -} -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: highpri_main - * - * Description: - * Main entry point in into the high priority interrupt test. - * - ****************************************************************************/ - -int highpri_main(int argc, char *argv[]) -{ -#ifdef HIGHPRI_HAVE_HRTIM - struct hrtim_dev_s *hrtim; -#endif -#ifdef HIGHPRI_HAVE_TIM1 - struct stm32_pwm_dev_s *pwm1; -#endif - struct adc_dev_s *adc1; - struct highpri_s *highpri; - int ret; - int i; - - highpri = &g_highpri; - - /* Initialize highpri structure */ - - memset(highpri, 0, sizeof(struct highpri_s)); - - printf("\nhighpri_main: Started\n"); - - /* Configure the pins as analog inputs for the selected channels */ - - for (i = 0; i < DEV1_NCHANNELS; i++) - { - stm32_configgpio(g_pinlist1[i]); - } - - /* Initialize ADC driver */ - - adc1 = stm32_adcinitialize(DEV1_PORT, g_chanlist1, DEV1_NCHANNELS); - if (adc1 == NULL) - { - aerr("ERROR: Failed to get ADC interface 1\n"); - ret = EXIT_FAILURE; - goto errout; - } - - highpri->adc1 = (struct stm32_adc_dev_s *)adc1->ad_priv; - -#ifdef HIGHPRI_HAVE_HRTIM - /* Configure HRTIM */ - - hrtim = stm32_hrtiminitialize(); - if (hrtim == NULL) - { - printf("ERROR: Failed to get HRTIM1 interface\n"); - ret = EXIT_FAILURE; - goto errout; - } - - highpri->hrtim = hrtim; - - /* Set Timer A Period */ - - HRTIM_PER_SET(hrtim, HRTIM_TIMER_TIMA, 0xffd0); -#endif /* HIGHPRI_HAVE_HRTIM */ - -#ifdef HIGHPRI_HAVE_TIM1 - /* Initialize TIM1 */ - - pwm1 = (struct stm32_pwm_dev_s *) stm32_pwminitialize(1); - if (pwm1 == NULL) - { - printf("ERROR: Failed to get PWM1 interface\n"); - ret = EXIT_FAILURE; - goto errout; - } - - highpri->pwm = pwm1; - - /* Setup PWM device */ - - PWM_SETUP(pwm1); - - /* Set timer frequency */ - - PWM_FREQ_UPDATE(pwm1, 1000); - - /* Set CCR1 */ - - PWM_CCR_UPDATE(pwm1, 1, 0x0f00); - - /* Enable TIM1 OUT1 */ - - PWM_OUTPUTS_ENABLE(pwm1, STM32_PWM_OUT1, true); - -#ifdef CONFIG_DEBUG_PWM_INFO - /* Print debug */ - - PWM_DUMP_REGS(pwm1); -#endif - -#endif /* HIGHPRI_HAVE_TIM1 */ - -#if !defined(CONFIG_STM32_ADC1_DMA) || defined(HIGHPRI_HAVE_INJECTED) - /* Attach ADC12 ram vector if no DMA or injected channels support */ - - ret = arm_ramvec_attach(STM32_IRQ_ADC12, adc12_handler); - if (ret < 0) - { - fprintf(stderr, "highpri_main: ERROR: arm_ramvec_attach failed: %d\n", - ret); - ret = EXIT_FAILURE; - goto errout; - } - - /* Set the priority of the ADC12 interrupt vector */ - - ret = up_prioritize_irq(STM32_IRQ_ADC12, NVIC_SYSH_HIGH_PRIORITY); - if (ret < 0) - { - fprintf(stderr, "highpri_main: ERROR: up_prioritize_irq failed: %d\n", - ret); - ret = EXIT_FAILURE; - goto errout; - } - - up_enable_irq(STM32_IRQ_ADC12); -#endif - -#ifdef CONFIG_STM32_ADC1_DMA - /* Attach DMA1 CH1 ram vector if DMA */ - - ret = arm_ramvec_attach(STM32_IRQ_DMA1CH1, dma1ch1_handler); - if (ret < 0) - { - fprintf(stderr, "highpri_main: ERROR: arm_ramvec_attach failed: %d\n", - ret); - ret = EXIT_FAILURE; - goto errout; - } - - /* Set the priority of the DMA1CH1 interrupt vector */ - - ret = up_prioritize_irq(STM32_IRQ_DMA1CH1, NVIC_SYSH_HIGH_PRIORITY); - if (ret < 0) - { - fprintf(stderr, "highpri_main: ERROR: up_prioritize_irq failed: %d\n", - ret); - ret = EXIT_FAILURE; - goto errout; - } - - up_enable_irq(STM32_IRQ_DMA1CH1); -#endif - - /* Setup ADC hardware */ - - adc1->ad_ops->ao_setup(adc1); - - /* Configure regular channels trigger to T1CC1 */ - - STM32_ADC_EXTCFG_SET(highpri->adc1, - ADC1_EXTSEL_T1CC1 | ADC_EXTREG_EXTEN_DEFAULT); - -#ifndef CONFIG_STM32_ADC1_DMA - /* Enable ADC regular conversion interrupts if no DMA */ - - STM32_ADC_INT_ENABLE(highpri->adc1, ADC_IER_EOC); -#else - /* Register ADC buffer for DMA transfer */ - - STM32_ADC_REGBUF_REGISTER(highpri->adc1, g_highpri.r_val, REG_NCHANNELS); -#endif - -#ifdef HIGHPRI_HAVE_INJECTED - /* Enable ADC injected sequence end interrupts */ - - STM32_ADC_INT_ENABLE(highpri->adc1, ADC_IER_JEOS); -#endif - -#ifdef HIGHPRI_HAVE_HRTIM - /* Enable HRTIM TIMA after ADC configuration */ - - HRTIM_TIM_ENABLE(highpri->hrtim, HRTIM_TIMER_TIMA, true); -#endif - -#ifdef HIGHPRI_HAVE_TIM1 - /* Enable timer counter after ADC configuration */ - - PWM_TIM_ENABLE(pwm1, true); -#endif - - while (1) - { -#ifndef CONFIG_STM32_ADC1_DMA - /* Software trigger for regular sequence */ - - adc1->ad_ops->ao_ioctl(adc1, IO_TRIGGER_REG, 0); - - nxsched_usleep(100); -#endif - -#ifdef HIGHPRI_HAVE_INJECTED - /* Software trigger for injected sequence */ - - adc1->ad_ops->ao_ioctl(adc1, IO_TRIGGER_INJ, 0); - - nxsched_usleep(100); -#endif - /* Lock global data */ - - g_highpri.lock = true; - -#ifndef CONFIG_STM32_ADC1_DMA - printf("%" PRId32 " [%d] %0.3fV\n", g_highpri.cntr1, g_highpri.current, - g_highpri.r_volt[g_highpri.current]); -#else - printf("%" PRId32 " ", g_highpri.cntr1); - - for (i = 0; i < REG_NCHANNELS; i += 1) - { - printf("r:[%d] %0.3fV, ", i, g_highpri.r_volt[i]); - } - - printf("\n"); -#endif - -#ifdef HIGHPRI_HAVE_INJECTED - /* Print data from injected channels */ - - printf("%" PRId32 " ", g_highpri.cntr2); - - for (i = 0; i < INJ_NCHANNELS; i += 1) - { - printf("j:[%d] %0.3fV, ", i, g_highpri.j_volt[i]); - } - - printf("\n"); -#endif - /* Unlock global data */ - - g_highpri.lock = false; - - nxsched_sleep(1); - } - -errout: - return ret; -} - -#endif /* CONFIG_NUCLEOF334R8_HIGHPRI */ diff --git a/boards/arm/stm32/nucleo-f334r8/src/stm32_hrtim.c b/boards/arm/stm32/nucleo-f334r8/src/stm32_hrtim.c deleted file mode 100644 index 6b493ee1cbd1e..0000000000000 --- a/boards/arm/stm32/nucleo-f334r8/src/stm32_hrtim.c +++ /dev/null @@ -1,86 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f334r8/src/stm32_hrtim.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include - -#include "stm32_hrtim.h" - -#ifndef CONFIG_STM32_HRTIM_DISABLE_CHARDRV - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_hrtim_setup - * - * Description: - * Initialize HRTIM driver - * - * Returned Value: - * 0 on success, a negated errno value on failure - * - ****************************************************************************/ - -int stm32_hrtim_setup(void) -{ - static bool initialized = false; - struct hrtim_dev_s *hrtim = NULL; - int ret; - - if (!initialized) - { - /* Get the HRTIM interface */ - - hrtim = stm32_hrtiminitialize(); - if (hrtim == NULL) - { - tmrerr("ERROR: Failed to get HRTIM1 interface\n"); - return -ENODEV; - } - - /* Register the HRTIM character driver at /dev/hrtim0 */ - - ret = hrtim_register("/dev/hrtim0", hrtim); - if (ret < 0) - { - tmrerr("ERROR: hrtim_register failed: %d\n", ret); - return ret; - } - - initialized = true; - } - - return OK; -} - -#endif /* CONFIG_STM32_HRTIM && CONFIG_STM32_HRTIM1 */ diff --git a/boards/arm/stm32/nucleo-f334r8/src/stm32_opamp.c b/boards/arm/stm32/nucleo-f334r8/src/stm32_opamp.c deleted file mode 100644 index cdc526cb42757..0000000000000 --- a/boards/arm/stm32/nucleo-f334r8/src/stm32_opamp.c +++ /dev/null @@ -1,86 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f334r8/src/stm32_opamp.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include "stm32.h" - -#if defined(CONFIG_OPAMP) && defined(CONFIG_STM32_OPAMP2) - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_opamp_setup - * - * Description: - * Initialize OPAMP - * - ****************************************************************************/ - -int stm32_opamp_setup(void) -{ - static bool initialized = false; - struct opamp_dev_s *opamp = NULL; - int ret; - - if (!initialized) - { - /* Get the OPAMP interface */ - -#ifdef CONFIG_STM32_OPAMP2 - opamp = stm32_opampinitialize(2); - if (opamp == NULL) - { - aerr("ERROR: Failed to get OPAMP%d interface\n", 2); - return -ENODEV; - } -#endif - - /* Register the OPAMP character driver at /dev/opamp0 */ - - ret = opamp_register("/dev/opamp0", opamp); - if (ret < 0) - { - aerr("ERROR: opamp_register failed: %d\n", ret); - return ret; - } - - initialized = true; - } - - return OK; -} - -#endif /* CONFIG_OPAMP && CONFIG_STM32_OPAMP2 */ diff --git a/boards/arm/stm32/nucleo-f401re/CMakeLists.txt b/boards/arm/stm32/nucleo-f401re/CMakeLists.txt deleted file mode 100644 index fc3725e660d65..0000000000000 --- a/boards/arm/stm32/nucleo-f401re/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/nucleo-f401re/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32/nucleo-f401re/configs/fb/defconfig b/boards/arm/stm32/nucleo-f401re/configs/fb/defconfig deleted file mode 100644 index 88504078e4d20..0000000000000 --- a/boards/arm/stm32/nucleo-f401re/configs/fb/defconfig +++ /dev/null @@ -1,62 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_ARCH_LEDS is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -# CONFIG_NSH_DISABLE_IFCONFIG is not set -# CONFIG_NSH_DISABLE_PS is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="nucleo-f401re" -CONFIG_ARCH_BOARD_COMMON=y -CONFIG_ARCH_BOARD_NUCLEO_F401RE=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F401RE=y -CONFIG_ARCH_INTERRUPTSTACK=2048 -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=8499 -CONFIG_BUILTIN=y -CONFIG_DRIVERS_VIDEO=y -CONFIG_EXAMPLES_FB=y -CONFIG_FB_MODULEINFO=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LCD=y -CONFIG_LCD_DEV=y -CONFIG_LCD_FRAMEBUFFER=y -CONFIG_LCD_UG2864HSWEG01=y -CONFIG_LINE_MAX=64 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=98304 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_SPI_CMDDATA=y -CONFIG_SPI_DRIVER=y -CONFIG_SSD1306_FREQUENCY=1000000 -CONFIG_START_DAY=5 -CONFIG_START_MONTH=5 -CONFIG_START_YEAR=2014 -CONFIG_STM32_I2C1=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_OTGFS=y -CONFIG_STM32_PWR=y -CONFIG_STM32_SPI1=y -CONFIG_STM32_USART2=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART2_SERIAL_CONSOLE=y -CONFIG_VIDEO_FB=y diff --git a/boards/arm/stm32/nucleo-f401re/configs/nsh/defconfig b/boards/arm/stm32/nucleo-f401re/configs/nsh/defconfig deleted file mode 100644 index 8bf7d35ad498e..0000000000000 --- a/boards/arm/stm32/nucleo-f401re/configs/nsh/defconfig +++ /dev/null @@ -1,48 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -# CONFIG_NSH_DISABLE_IFCONFIG is not set -# CONFIG_NSH_DISABLE_PS is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="nucleo-f401re" -CONFIG_ARCH_BOARD_NUCLEO_F401RE=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F401RE=y -CONFIG_ARCH_INTERRUPTSTACK=2048 -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=8499 -CONFIG_BUILTIN=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=98304 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_SPI=y -CONFIG_START_DAY=5 -CONFIG_START_MONTH=5 -CONFIG_START_YEAR=2014 -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_OTGFS=y -CONFIG_STM32_PWR=y -CONFIG_STM32_USART2=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/nucleo-f401re/include/board.h b/boards/arm/stm32/nucleo-f401re/include/board.h deleted file mode 100644 index 48a13db82da87..0000000000000 --- a/boards/arm/stm32/nucleo-f401re/include/board.h +++ /dev/null @@ -1,380 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f401re/include/board.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __BOARDS_ARM_STM32_NUCLEO_F401RE_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32_NUCLEO_F401RE_INCLUDE_BOARD_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#ifndef __ASSEMBLY__ -# include -#endif - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Clocking *****************************************************************/ - -/* The NUCLEO401RE supports both HSE and LSE crystals (X2 and X3). - * However, as shipped, the X2 and X3 crystals are not populated. - * Therefore the Nucleo-F401RE will need to run off the 16MHz HSI clock. - * - * System Clock source : PLL (HSI) - * SYSCLK(Hz) : 84000000 Determined by PLL - * configuration - * HCLK(Hz) : 84000000 (STM32_RCC_CFGR_HPRE) - * AHB Prescaler : 1 (STM32_RCC_CFGR_HPRE) - * APB1 Prescaler : 2 (STM32_RCC_CFGR_PPRE1) - * APB2 Prescaler : 1 (STM32_RCC_CFGR_PPRE2) - * HSI Frequency(Hz) : 16000000 (nominal) - * PLLM : 16 (STM32_PLLCFG_PLLM) - * PLLN : 336 (STM32_PLLCFG_PLLN) - * PLLP : 4 (STM32_PLLCFG_PLLP) - * PLLQ : 7 (STM32_PLLCFG_PPQ) - * Flash Latency(WS) : 5 - * Prefetch Buffer : OFF - * Instruction cache : ON - * Data cache : ON - * Require 48MHz for USB OTG FS, : Enabled - * SDIO and RNG clock - */ - -/* HSI - 16 MHz RC factory-trimmed - * LSI - 32 KHz RC - * HSE - not installed - * LSE - not installed - */ - -#define STM32_HSI_FREQUENCY 16000000ul -#define STM32_LSI_FREQUENCY 32000 -#define STM32_BOARD_USEHSI 1 - -/* Main PLL Configuration. - * - * Formulae: - * - * VCO input frequency = PLL input clock frequency / PLLM, - * 2 <= PLLM <= 63 - * VCO output frequency = VCO input frequency × PLLN, - * 192 <= PLLN <= 432 - * PLL output clock frequency = VCO frequency / PLLP, - * PLLP = 2, 4, 6, or 8 - * USB OTG FS clock frequency = VCO frequency / PLLQ, - * 2 <= PLLQ <= 15 - * - * We would like to have SYSYCLK=84MHz and we must have the USB clock= 48MHz. - * Some possible solutions include: - * - * PLLN=210 PLLM=5 PLLP=8 PLLQ=14 SYSCLK=84000000 OTGFS=48000000 - * PLLN=210 PLLM=10 PLLP=4 PLLQ=7 SYSCLK=84000000 OTGFS=48000000 - * PLLN=336 PLLM=8 PLLP=8 PLLQ=14 SYSCLK=84000000 OTGFS=48000000 - * PLLN=336 PLLM=16 PLLP=4 PLLQ=7 SYSCLK=84000000 OTGFS=48000000 - * PLLN=420 PLLM=10 PLLP=8 PLLQ=14 SYSCLK=84000000 OTGFS=48000000 - * PLLN=420 PLLM=20 PLLP=4 PLLQ=7 SYSCLK=84000000 OTGFS=48000000 - * - * We will configure like this - * - * PLL source is HSI - * PLL_VCO = (STM32_HSI_FREQUENCY / PLLM) * PLLN - * = (16,000,000 / 16) * 336 - * = 336,000,000 - * SYSCLK = PLL_VCO / PLLP - * = 336,000,000 / 4 = 84,000,000 - * USB OTG FS and SDIO Clock - * = PLL_VCO / PLLQ - * = 336,000,000 / 7 = 48,000,000 - * - * REVISIT: Trimming of the HSI is not yet supported. - */ - -#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(16) -#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(336) -#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_4 -#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(7) - -#define STM32_SYSCLK_FREQUENCY 84000000ul - -/* AHB clock (HCLK) is SYSCLK (84MHz) */ - -#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ -#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY - -/* APB1 clock (PCLK1) is HCLK/2 (42MHz) */ - -#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd2 /* PCLK1 = HCLK / 2 */ -#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/2) - -/* Timers driven from APB1 will be twice PCLK1 */ - -/* REVISIT */ - -#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) - -/* APB2 clock (PCLK2) is HCLK (84MHz) */ - -#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ -#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/1) - -/* Timers driven from APB2 will be twice PCLK2 */ - -/* REVISIT */ - -#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM9_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB2_TIM10_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB2_TIM11_CLKIN (2*STM32_PCLK1_FREQUENCY) - -/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx - * otherwise frequency is 2xAPBx. - * Note: TIM1,8 are on APB2, others on APB1 - */ - -/* REVISIT */ - -#define BOARD_TIM1_FREQUENCY (2*STM32_PCLK2_FREQUENCY) -#define BOARD_TIM2_FREQUENCY (2*STM32_PCLK1_FREQUENCY) -#define BOARD_TIM3_FREQUENCY (2*STM32_PCLK1_FREQUENCY) -#define BOARD_TIM4_FREQUENCY (2*STM32_PCLK1_FREQUENCY) -#define BOARD_TIM5_FREQUENCY (2*STM32_PCLK1_FREQUENCY) -#define BOARD_TIM6_FREQUENCY (2*STM32_PCLK1_FREQUENCY) -#define BOARD_TIM7_FREQUENCY (2*STM32_PCLK1_FREQUENCY) -#define BOARD_TIM8_FREQUENCY (2*STM32_PCLK2_FREQUENCY) - -/* SDIO dividers. Note that slower clocking is required when DMA is disabled - * in order to avoid RX overrun/TX underrun errors due to delayed responses - * to service FIFOs in interrupt driven mode. These values have not been - * tuned!!! - * - * HCLK=72MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(178+2)=400 KHz - */ - -/* REVISIT */ - -#define SDIO_INIT_CLKDIV (178 << SDIO_CLKCR_CLKDIV_SHIFT) - -/* DMA ON: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(2+2)=18 MHz - * DMA OFF: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(3+2)=14.4 MHz - */ - -/* REVISIT */ - -#ifdef CONFIG_SDIO_DMA -# define SDIO_MMCXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT) -#else -# define SDIO_MMCXFR_CLKDIV (3 << SDIO_CLKCR_CLKDIV_SHIFT) -#endif - -/* DMA ON: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(1+2)=24 MHz - * DMA OFF: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(3+2)=14.4 MHz - */ - -/* REVISIT */ - -#ifdef CONFIG_SDIO_DMA -# define SDIO_SDXFR_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT) -#else -# define SDIO_SDXFR_CLKDIV (3 << SDIO_CLKCR_CLKDIV_SHIFT) -#endif - -/* DMA Channel/Stream Selections ********************************************/ - -/* Stream selections are arbitrary for now but might become important in - * the future is we set aside more DMA channels/streams. - * - * SDIO DMA - *   DMAMAP_SDIO_1 = Channel 4, Stream 3 <- may later be used by SPI DMA - *   DMAMAP_SDIO_2 = Channel 4, Stream 6 - */ - -#define DMAMAP_SDIO DMAMAP_SDIO_1 - -/* Need to VERIFY fwb */ - -#define DMACHAN_SPI1_RX DMAMAP_SPI1_RX_1 -#define DMACHAN_SPI1_TX DMAMAP_SPI1_TX_1 -#define DMACHAN_SPI2_RX DMAMAP_SPI2_RX -#define DMACHAN_SPI2_TX DMAMAP_SPI2_TX - -/* Alternate function pin selections ****************************************/ - -/* USART1: - * RXD: PA10 CN9 pin 3, CN10 pin 33 - * PB7 CN7 pin 21 - * TXD: PA9 CN5 pin 1, CN10 pin 21 - * PB6 CN5 pin 3, CN10 pin 17 - */ - -#if 1 -# define GPIO_USART1_RX (GPIO_USART1_RX_1|GPIO_SPEED_100MHz) /* PA10 */ -# define GPIO_USART1_TX (GPIO_USART1_TX_1|GPIO_SPEED_100MHz) /* PA9 */ -#else -# define GPIO_USART1_RX (GPIO_USART1_RX_2|GPIO_SPEED_100MHz) /* PB7 */ -# define GPIO_USART1_TX (GPIO_USART1_TX_2|GPIO_SPEED_100MHz) /* PB6 */ -#endif - -/* USART2: - * RXD: PA3 CN9 pin 1 (See SB13, 14, 62, 63). CN10 pin 37 - * PD6 - * TXD: PA2 CN9 pin 2(See SB13, 14, 62, 63). CN10 pin 35 - * PD5 - */ - -#define GPIO_USART2_RX (GPIO_USART2_RX_1|GPIO_SPEED_100MHz) /* PA3 */ -#define GPIO_USART2_TX (GPIO_USART2_TX_1|GPIO_SPEED_100MHz) /* PA2 */ -#define GPIO_USART2_RTS GPIO_USART2_RTS_2 -#define GPIO_USART2_CTS GPIO_USART2_CTS_2 - -/* USART6: - * RXD: PC7 CN5 pin2, CN10 pin 19 - * PA12 CN10, pin 12 - * TXD: PC6 CN10, pin 4 - * PA11 CN10, pin 14 - */ - -#define GPIO_USART6_RX (GPIO_USART6_RX_1|GPIO_SPEED_100MHz) /* PC7 */ -#define GPIO_USART6_TX (GPIO_USART6_TX_1|GPIO_SPEED_100MHz) /* PC6 */ - -/* UART RX DMA configurations */ - -#define DMAMAP_USART1_RX DMAMAP_USART1_RX_2 -#define DMAMAP_USART6_RX DMAMAP_USART6_RX_2 - -/* I2C - * - * The optional _GPIO configurations allow the I2C driver to manually - * reset the bus to clear stuck slaves. They match the pin configuration, - * but are normally-high GPIOs. - */ - -#define GPIO_I2C1_SCL (GPIO_I2C1_SCL_2|GPIO_SPEED_50MHz) -#define GPIO_I2C1_SDA (GPIO_I2C1_SDA_2|GPIO_SPEED_50MHz) -#define GPIO_I2C1_SCL_GPIO \ - (GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTB|GPIO_PIN8) -#define GPIO_I2C1_SDA_GPIO \ - (GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTB|GPIO_PIN9) - -#define GPIO_I2C2_SCL (GPIO_I2C2_SCL_1|GPIO_SPEED_50MHz) -#define GPIO_I2C2_SDA (GPIO_I2C2_SDA_1|GPIO_SPEED_50MHz) -#define GPIO_I2C2_SCL_GPIO \ - (GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTB|GPIO_PIN10) -#define GPIO_I2C2_SDA_GPIO \ - (GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTB|GPIO_PIN11) - -/* SPI - * - * There are sensors on SPI1, and SPI2 is connected to the FRAM. - */ - -#define GPIO_SPI1_MISO (GPIO_SPI1_MISO_1|GPIO_SPEED_50MHz) -#define GPIO_SPI1_MOSI (GPIO_SPI1_MOSI_1|GPIO_SPEED_50MHz) -#define GPIO_SPI1_SCK (GPIO_SPI1_SCK_1|GPIO_SPEED_50MHz) - -#define GPIO_SPI2_MISO (GPIO_SPI2_MISO_1|GPIO_SPEED_50MHz) -#define GPIO_SPI2_MOSI (GPIO_SPI2_MOSI_1|GPIO_SPEED_50MHz) -#define GPIO_SPI2_SCK (GPIO_SPI2_SCK_2|GPIO_SPEED_50MHz) - -/* LEDs - * - * The Nucleo F401RE board provide a single user LED, LD2. LD2 - * is the green LED connected to Arduino signal D13 corresponding to MCU I/O - * PA5 (pin 21) or PB13 (pin 34) depending on the STM32 target. - * - * - When the I/O is HIGH value, the LED is on. - * - When the I/O is LOW, the LED is off. - */ - -/* LED index values for use with board_userled() */ - -#define BOARD_LD2 0 -#define BOARD_NLEDS 1 - -/* LED bits for use with board_userled_all() */ - -#define BOARD_LD2_BIT (1 << BOARD_LD2) - -/* These LEDs are not used by the board port unless CONFIG_ARCH_LEDS is - * defined. In that case, the usage by the board port is defined in - * include/board.h and src/sam_leds.c. The LEDs are used to encode OS-related - * events as follows when the red LED (PE24) is available: - * - * SYMBOL Meaning LD2 - * ------------------- ----------------------- ----------- - * LED_STARTED NuttX has been started OFF - * LED_HEAPALLOCATE Heap has been allocated OFF - * LED_IRQSENABLED Interrupts enabled OFF - * LED_STACKCREATED Idle stack created ON - * LED_INIRQ In an interrupt No change - * LED_SIGNAL In a signal handler No change - * LED_ASSERTION An assertion failed No change - * LED_PANIC The system has crashed Blinking - * LED_IDLE MCU is in sleep mode Not used - * - * Thus if LD2, NuttX has successfully booted and is, apparently, running - * normally. If LD2 is flashing at approximately 2Hz, then a fatal error - * has been detected and the system has halted. - */ - -#define LED_STARTED 0 -#define LED_HEAPALLOCATE 0 -#define LED_IRQSENABLED 0 -#define LED_STACKCREATED 1 -#define LED_INIRQ 2 -#define LED_SIGNAL 2 -#define LED_ASSERTION 2 -#define LED_PANIC 1 - -/* Buttons - * - * B1 USER: - * the user button is connected to the I/O PC13 (pin 2) of the STM32 - * microcontroller. - */ - -#define BUTTON_USER 0 -#define NUM_BUTTONS 1 - -#define BUTTON_USER_BIT (1 << BUTTON_USER) - -#define GPIO_TIM2_CH1IN (GPIO_TIM2_CH1IN_1 | GPIO_PULLUP | GPIO_SPEED_50MHz) -#define GPIO_TIM2_CH2IN (GPIO_TIM2_CH2IN_1 | GPIO_PULLUP | GPIO_SPEED_50MHz) - -/* USB OTG FS */ - -#define GPIO_OTGFS_DM (GPIO_OTGFS_DM_0|GPIO_SPEED_100MHz) -#define GPIO_OTGFS_DP (GPIO_OTGFS_DP_0|GPIO_SPEED_100MHz) -#define GPIO_OTGFS_ID (GPIO_OTGFS_ID_0|GPIO_SPEED_100MHz) -#define GPIO_OTGFS_SOF (GPIO_OTGFS_SOF_0|GPIO_SPEED_100MHz) - -#endif /* __BOARDS_ARM_STM32_NUCLEO_F401RE_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32/nucleo-f401re/scripts/Make.defs b/boards/arm/stm32/nucleo-f401re/scripts/Make.defs deleted file mode 100644 index a106e21e6af79..0000000000000 --- a/boards/arm/stm32/nucleo-f401re/scripts/Make.defs +++ /dev/null @@ -1,43 +0,0 @@ -############################################################################ -# boards/arm/stm32/nucleo-f401re/scripts/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/.config -include $(TOPDIR)/tools/Config.mk -include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs - -LDSCRIPT = flash.ld - -ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) - -ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 - -CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) -CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) -CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -AFLAGS := $(CFLAGS) -D__ASSEMBLY__ - -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections -LDNXFLATFLAGS = -e main -s 2048 - diff --git a/boards/arm/stm32/nucleo-f401re/scripts/flash.ld b/boards/arm/stm32/nucleo-f401re/scripts/flash.ld deleted file mode 100644 index 4ad627c8819d8..0000000000000 --- a/boards/arm/stm32/nucleo-f401re/scripts/flash.ld +++ /dev/null @@ -1,109 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f401re/scripts/flash.ld - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* The STM32F401RE has 512Kb of FLASH beginning at address 0x0800:0000 and - * 96Kb of SRAM beginning at address 0x2000:0000. When booting from FLASH, - * FLASH memory is aliased to address 0x0000:0000 where the code expects to - * begin execution by jumping to the entry point in the 0x0800:0000 address - * range. - */ - -MEMORY -{ - flash (rx) : ORIGIN = 0x08000000, LENGTH = 512K - sram (rwx) : ORIGIN = 0x20000000, LENGTH = 96K -} - -OUTPUT_ARCH(arm) -EXTERN(_vectors) -ENTRY(_stext) -SECTIONS -{ - .text : { - _stext = ABSOLUTE(.); - *(.vectors) - *(.text .text.*) - *(.fixup) - *(.gnu.warning) - *(.rodata .rodata.*) - *(.gnu.linkonce.t.*) - *(.glue_7) - *(.glue_7t) - *(.got) - *(.gcc_except_table) - *(.gnu.linkonce.r.*) - _etext = ABSOLUTE(.); - } > flash - - .init_section : { - _sinit = ABSOLUTE(.); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) - KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) - _einit = ABSOLUTE(.); - } > flash - - .ARM.extab : { - *(.ARM.extab*) - } > flash - - __exidx_start = ABSOLUTE(.); - .ARM.exidx : { - *(.ARM.exidx*) - } > flash - __exidx_end = ABSOLUTE(.); - - _eronly = ABSOLUTE(.); - - /* The STM32F103VCT6 has 48Kb of SRAM beginning at the following address */ - - .data : { - _sdata = ABSOLUTE(.); - *(.data .data.*) - *(.gnu.linkonce.d.*) - CONSTRUCTORS - . = ALIGN(4); - _edata = ABSOLUTE(.); - } > sram AT > flash - - .bss : { - _sbss = ABSOLUTE(.); - *(.bss .bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - . = ALIGN(8); - _ebss = ABSOLUTE(.); - } > sram - - /* Stabs debugging sections. */ - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_info 0 : { *(.debug_info) } - .debug_line 0 : { *(.debug_line) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_aranges 0 : { *(.debug_aranges) } -} diff --git a/boards/arm/stm32/nucleo-f401re/src/CMakeLists.txt b/boards/arm/stm32/nucleo-f401re/src/CMakeLists.txt deleted file mode 100644 index d1e694f440518..0000000000000 --- a/boards/arm/stm32/nucleo-f401re/src/CMakeLists.txt +++ /dev/null @@ -1,54 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/nucleo-f401re/src/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -set(SRCS stm32_boot.c stm32_spi.c stm32_bringup.c) - -if(CONFIG_VIDEO_FB) - if(CONFIG_LCD_SSD1306) - list(APPEND SRCS stm32_lcd_ssd1306.c) - endif() -endif() - -if(CONFIG_ARCH_LEDS) - list(APPEND SRCS stm32_autoleds.c) -else() - list(APPEND SRCS stm32_userleds.c) -endif() - -if(CONFIG_ARCH_BUTTONS) - list(APPEND SRCS stm32_buttons.c) -endif() - -if(CONFIG_ADC) - list(APPEND SRCS stm32_adc.c) - if(CONFIG_INPUT_AJOYSTICK) - list(APPEND SRCS stm32_ajoystick.c) - endif() -endif() - -if(CONFIG_CAN_MCP2515) - list(APPEND SRCS stm32_mcp2515.c) -endif() - -target_sources(board PRIVATE ${SRCS}) - -set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/flash.ld") diff --git a/boards/arm/stm32/nucleo-f401re/src/Make.defs b/boards/arm/stm32/nucleo-f401re/src/Make.defs deleted file mode 100644 index 45725b5052ed6..0000000000000 --- a/boards/arm/stm32/nucleo-f401re/src/Make.defs +++ /dev/null @@ -1,56 +0,0 @@ -############################################################################ -# boards/arm/stm32/nucleo-f401re/src/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/Make.defs - -CSRCS = stm32_boot.c stm32_spi.c stm32_bringup.c - -ifeq ($(CONFIG_VIDEO_FB),y) -ifeq ($(CONFIG_LCD_SSD1306),y) - CSRCS += stm32_lcd_ssd1306.c -endif -endif - -ifeq ($(CONFIG_ARCH_LEDS),y) -CSRCS += stm32_autoleds.c -else -CSRCS += stm32_userleds.c -endif - -ifeq ($(CONFIG_ARCH_BUTTONS),y) -CSRCS += stm32_buttons.c -endif - -ifeq ($(CONFIG_ADC),y) -CSRCS += stm32_adc.c -ifeq ($(CONFIG_INPUT_AJOYSTICK),y) -CSRCS += stm32_ajoystick.c -endif -endif - -ifeq ($(CONFIG_CAN_MCP2515),y) - CSRCS += stm32_mcp2515.c -endif - -DEPPATH += --dep-path board -VPATH += :board -CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/nucleo-f401re/src/stm32_adc.c b/boards/arm/stm32/nucleo-f401re/src/stm32_adc.c deleted file mode 100644 index 2ad4c4e22e8ca..0000000000000 --- a/boards/arm/stm32/nucleo-f401re/src/stm32_adc.c +++ /dev/null @@ -1,142 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f401re/src/stm32_adc.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32_adc.h" -#include "nucleo-f401re.h" - -#include - -#ifdef CONFIG_STM32_ADC1 - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* The number of ADC channels in the conversion list */ - -#ifdef CONFIG_ADC_DMA -# define ADC1_NCHANNELS 2 -#else -# define ADC1_NCHANNELS 1 -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* Identifying number of each ADC channel. */ - -#ifdef CONFIG_ADC_DMA -/* Configure ADC inputs on ADC_IN0 and ADC_IN1 */ - -static const uint8_t g_adc1_chanlist[ADC1_NCHANNELS] = -{ - 0, 1 -}; - -/* Configurations of pins used byte each ADC channels */ - -static const uint32_t g_adc1_pinlist[ADC1_NCHANNELS] = -{ - GPIO_ADC1_IN0, GPIO_ADC1_IN0 -}; - -#else -/* Without DMA, only a single channel can be supported */ - -/* Configura ADC input on ADC_IN0 */ - -static const uint8_t g_adc1_chanlist[ADC1_NCHANNELS] = -{ - 0 -}; - -/* Configurations of pins used byte each ADC channels */ - -static const uint32_t g_adc1_pinlist[ADC1_NCHANNELS] = -{ - GPIO_ADC1_IN0 -}; - -#endif /* CONFIG_ADC_DMA */ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_adc_setup - * - * Description: - * Initialize ADC and register the ADC driver. - * - ****************************************************************************/ - -int stm32_adc_setup(void) -{ - struct adc_dev_s *adc; - int ret; - int i; - - /* Configure the pins as analog inputs for the selected channels */ - - for (i = 0; i < ADC1_NCHANNELS; i++) - { - stm32_configgpio(g_adc1_pinlist[i]); - } - - /* Call stm32_adcinitialize() to get an instance of the ADC interface */ - - adc = stm32_adcinitialize(1, g_adc1_chanlist, ADC1_NCHANNELS); - if (adc == NULL) - { - aerr("ERROR: Failed to get ADC interface\n"); - return -ENODEV; - } - - /* Register the ADC driver at "/dev/adc0" */ - - ret = adc_register("/dev/adc0", adc); - if (ret < 0) - { - aerr("ERROR: adc_register failed: %d\n", ret); - return ret; - } - - return OK; -} - -#endif /* CONFIG_STM32_ADC1 */ diff --git a/boards/arm/stm32/nucleo-f401re/src/stm32_ajoystick.c b/boards/arm/stm32/nucleo-f401re/src/stm32_ajoystick.c deleted file mode 100644 index 7752b7a61da43..0000000000000 --- a/boards/arm/stm32/nucleo-f401re/src/stm32_ajoystick.c +++ /dev/null @@ -1,490 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f401re/src/stm32_ajoystick.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include - -#include -#include -#include -#include -#include - -#include "stm32_gpio.h" -#include "stm32_adc.h" -#include "hardware/stm32_adc.h" -#include "nucleo-f401re.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Check for pre-requisites and pin conflicts */ - -#ifdef CONFIG_INPUT_AJOYSTICK -# if !defined(CONFIG_ADC) -# error CONFIG_ADC is required for the Itead joystick -# undef CONFIG_INPUT_AJOYSTICK -# elif !defined(CONFIG_STM32_ADC1) -# error CONFIG_STM32_ADC1 is required for Itead joystick -# undef CONFIG_INPUT_AJOYSTICK -# endif -#endif /* CONFIG_INPUT_AJOYSTICK */ - -#ifdef CONFIG_INPUT_AJOYSTICK - -/* A no-ADC, buttons only version can be built for testing */ - -#undef NO_JOYSTICK_ADC - -/* Maximum number of ADC channels */ - -#define MAX_ADC_CHANNELS 8 - -/* Dual channel ADC support requires DMA */ - -#ifdef CONFIG_ADC_DMA -# define NJOYSTICK_CHANNELS 2 -#else -# define NJOYSTICK_CHANNELS 1 -#endif - -#ifdef CONFIG_NUCLEO_F401RE_AJOY_MINBUTTONS -/* Number of Joystick buttons */ - -# define AJOY_NGPIOS 3 - -/* Bitset of supported Joystick buttons */ - -# define AJOY_SUPPORTED (AJOY_BUTTON_1_BIT | AJOY_BUTTON_2_BIT | \ - AJOY_BUTTON_3_BIT) -#else -/* Number of Joystick buttons */ - -# define AJOY_NGPIOS 7 - -/* Bitset of supported Joystick buttons */ - -# define AJOY_SUPPORTED (AJOY_BUTTON_1_BIT | AJOY_BUTTON_2_BIT | \ - AJOY_BUTTON_3_BIT | AJOY_BUTTON_4_BIT | \ - AJOY_BUTTON_5_BIT | AJOY_BUTTON_6_BIT | \ - AJOY_BUTTON_7_BIT ) -#endif - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -static ajoy_buttonset_t -ajoy_supported(const struct ajoy_lowerhalf_s *lower); -static int ajoy_sample(const struct ajoy_lowerhalf_s *lower, - struct ajoy_sample_s *sample); -static ajoy_buttonset_t -ajoy_buttons(const struct ajoy_lowerhalf_s *lower); -static void ajoy_enable(const struct ajoy_lowerhalf_s *lower, - ajoy_buttonset_t press, ajoy_buttonset_t release, - ajoy_handler_t handler, void *arg); - -static void ajoy_disable(void); -static int ajoy_interrupt(int irq, void *context, void *arg); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* Pin configuration for each Itead joystick button. Index using AJOY_* - * button definitions in include/nuttx/input/ajoystick.h. - */ - -#ifdef CONFIG_NUCLEO_F401RE_AJOY_MINBUTTONS -static const uint32_t g_joygpio[AJOY_NGPIOS] = -{ - GPIO_BUTTON_1, GPIO_BUTTON_2, GPIO_BUTTON_3 -}; -#else -static const uint32_t g_joygpio[AJOY_NGPIOS] = -{ - GPIO_BUTTON_1, GPIO_BUTTON_2, GPIO_BUTTON_3, GPIO_BUTTON_4, - GPIO_BUTTON_5, GPIO_BUTTON_6, GPIO_BUTTON_7 -}; -#endif - -/* This is the button joystick lower half driver interface */ - -static const struct ajoy_lowerhalf_s g_ajoylower = -{ - .al_supported = ajoy_supported, - .al_sample = ajoy_sample, - .al_buttons = ajoy_buttons, - .al_enable = ajoy_enable, -}; - -#ifndef NO_JOYSTICK_ADC -/* Thread-independent file structure for the open ADC driver */ - -static struct file g_adcfile; -#endif - -/* Current interrupt handler and argument */ - -static ajoy_handler_t g_ajoyhandler; -static void *g_ajoyarg; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: ajoy_supported - * - * Description: - * Return the set of buttons supported on the button joystick device - * - ****************************************************************************/ - -static ajoy_buttonset_t -ajoy_supported(const struct ajoy_lowerhalf_s *lower) -{ - iinfo("Supported: %02x\n", AJOY_SUPPORTED); - return (ajoy_buttonset_t)AJOY_SUPPORTED; -} - -/**************************************************************************** - * Name: ajoy_sample - * - * Description: - * Return the current state of all button joystick buttons - * - ****************************************************************************/ - -static int ajoy_sample(const struct ajoy_lowerhalf_s *lower, - struct ajoy_sample_s *sample) -{ -#ifndef NO_JOYSTICK_ADC - struct adc_msg_s adcmsg[MAX_ADC_CHANNELS]; - struct adc_msg_s *ptr; - ssize_t nread; - ssize_t offset; - int have; - int i; - - /* Read all of the available samples (handling the case where additional - * channels are enabled). - */ - - nread = file_read(&g_adcfile, adcmsg, - MAX_ADC_CHANNELS * sizeof(struct adc_msg_s)); - if (nread < 0) - { - if (nread != -EINTR) - { - ierr("ERROR: read failed: %d\n", (int)nread); - } - - return nread; - } - else if (nread < NJOYSTICK_CHANNELS * sizeof(struct adc_msg_s)) - { - ierr("ERROR: read too small: %ld\n", (long)nread); - return -EIO; - } - - /* Sample and the raw analog inputs */ - -#ifdef CONFIG_ADC_DMA - have = 0; - -#else - /* If DMA is not supported, then we will have only a single ADC channel */ - - have = 2; - sample->as_y = 0; -#endif - - for (i = 0, offset = 0; - i < MAX_ADC_CHANNELS && offset < nread && have != 3; - i++, offset += sizeof(struct adc_msg_s)) - { - ptr = &adcmsg[i]; - - /* Is this one of the channels that we need? */ - - if ((have & 1) == 0 && ptr->am_channel == 0) - { - int32_t tmp = ptr->am_data; - sample->as_x = (int16_t)tmp; - have |= 1; - - iinfo("X sample: %ld -> %d\n", (long)tmp, (int)sample->as_x); - } - -#ifdef CONFIG_ADC_DMA - if ((have & 2) == 0 && ptr->am_channel == 1) - { - int32_t tmp = ptr->am_data; - sample->as_y = (int16_t)tmp; - have |= 2; - - iinfo("Y sample: %ld -> %d\n", (long)tmp, (int)sample->as_y); - } -#endif - } - - if (have != 3) - { - ierr("ERROR: Could not find joystick channels\n"); - return -EIO; - } - -#else - /* ADC support is disabled */ - - sample->as_x = 0; - sample->as_y = 0; -#endif - - /* Sample the discrete button inputs */ - - sample->as_buttons = ajoy_buttons(lower); - iinfo("Returning: %02x\n", sample->as_buttons); - return OK; -} - -/**************************************************************************** - * Name: ajoy_buttons - * - * Description: - * Return the current state of button data (only) - * - ****************************************************************************/ - -static ajoy_buttonset_t -ajoy_buttons(const struct ajoy_lowerhalf_s *lower) -{ - ajoy_buttonset_t ret = 0; - int i; - - /* Read each joystick GPIO value */ - - for (i = 0; i < AJOY_NGPIOS; i++) - { - /* Button outputs are pulled high. So a sensed low level means that the - * button is pressed. - */ - - if (!stm32_gpioread(g_joygpio[i])) - { - ret |= (1 << i); - } - } - - iinfo("Returning: %02x\n", ret); - return ret; -} - -/**************************************************************************** - * Name: ajoy_enable - * - * Description: - * Enable interrupts on the selected set of joystick buttons. And empty - * set will disable all interrupts. - * - ****************************************************************************/ - -static void ajoy_enable(const struct ajoy_lowerhalf_s *lower, - ajoy_buttonset_t press, ajoy_buttonset_t release, - ajoy_handler_t handler, void *arg) -{ - irqstate_t flags; - ajoy_buttonset_t either = press | release; - ajoy_buttonset_t bit; - bool rising; - bool falling; - int i; - - /* Start with all interrupts disabled */ - - flags = enter_critical_section(); - ajoy_disable(); - - iinfo("press: %02x release: %02x handler: %p arg: %p\n", - press, release, handler, arg); - - /* If no events are indicated or if no handler is provided, then this - * must really be a request to disable interrupts. - */ - - if (either && handler) - { - /* Save the new the handler and argument */ - - g_ajoyhandler = handler; - g_ajoyarg = arg; - - /* Check each GPIO. */ - - for (i = 0; i < AJOY_NGPIOS; i++) - { - /* Enable interrupts on each pin that has either a press or - * release event associated with it. - */ - - bit = (1 << i); - if ((either & bit) != 0) - { - /* Active low so a press corresponds to a falling edge and - * a release corresponds to a rising edge. - */ - - falling = ((press & bit) != 0); - rising = ((release & bit) != 0); - - iinfo("GPIO %d: rising: %d falling: %d\n", - i, rising, falling); - - stm32_gpiosetevent(g_joygpio[i], rising, falling, - true, ajoy_interrupt, NULL); - } - } - } - - leave_critical_section(flags); -} - -/**************************************************************************** - * Name: ajoy_disable - * - * Description: - * Disable all joystick interrupts - * - ****************************************************************************/ - -static void ajoy_disable(void) -{ - irqstate_t flags; - int i; - - /* Disable each joystick interrupt */ - - flags = enter_critical_section(); - for (i = 0; i < AJOY_NGPIOS; i++) - { - stm32_gpiosetevent(g_joygpio[i], false, false, false, NULL, NULL); - } - - leave_critical_section(flags); - - /* Nullify the handler and argument */ - - g_ajoyhandler = NULL; - g_ajoyarg = NULL; -} - -/**************************************************************************** - * Name: ajoy_interrupt - * - * Description: - * Discrete joystick interrupt handler - * - ****************************************************************************/ - -static int ajoy_interrupt(int irq, void *context, void *arg) -{ - DEBUGASSERT(g_ajoyhandler); - - if (g_ajoyhandler) - { - g_ajoyhandler(&g_ajoylower, g_ajoyarg); - } - - return OK; -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_ajoy_initialize - * - * Description: - * Initialize and register the button joystick driver - * - ****************************************************************************/ - -int board_ajoy_initialize(void) -{ - int ret; - int i; - -#ifndef NO_JOYSTICK_ADC - iinfo("Initialize ADC driver: /dev/adc0\n"); - - /* NOTE: The ADC driver was initialized earlier in the bring-up sequence. */ - - /* Open the ADC driver for reading. */ - - ret = file_open(&g_adcfile, "/dev/adc0", O_RDONLY); - if (ret < 0) - { - ierr("ERROR: Failed to open /dev/adc0: %d\n", ret); - return ret; - } -#endif - - /* Configure the GPIO pins as interrupting inputs. NOTE: This is - * unnecessary for interrupting pins since it will also be done by - * stm32_gpiosetevent(). - */ - - for (i = 0; i < AJOY_NGPIOS; i++) - { - /* Configure the PIO as an input */ - - stm32_configgpio(g_joygpio[i]); - } - - /* Register the joystick device as /dev/ajoy0 */ - - iinfo("Initialize joystick driver: /dev/ajoy0\n"); - - ret = ajoy_register("/dev/ajoy0", &g_ajoylower); - if (ret < 0) - { - ierr("ERROR: ajoy_register failed: %d\n", ret); -#ifndef NO_JOYSTICK_ADC - file_close(&g_adcfile); -#endif - } - - return ret; -} - -#endif /* CONFIG_INPUT_AJOYSTICK */ diff --git a/boards/arm/stm32/nucleo-f401re/src/stm32_autoleds.c b/boards/arm/stm32/nucleo-f401re/src/stm32_autoleds.c deleted file mode 100644 index 6dffbce983e5c..0000000000000 --- a/boards/arm/stm32/nucleo-f401re/src/stm32_autoleds.c +++ /dev/null @@ -1,83 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f401re/src/stm32_autoleds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32.h" -#include "nucleo-f401re.h" - -#include - -#ifdef CONFIG_ARCH_LEDS - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_autoled_initialize - ****************************************************************************/ - -void board_autoled_initialize(void) -{ - /* Configure LD2 GPIO for output */ - - stm32_configgpio(GPIO_LD2); -} - -/**************************************************************************** - * Name: board_autoled_on - ****************************************************************************/ - -void board_autoled_on(int led) -{ - if (led == 1) - { - stm32_gpiowrite(GPIO_LD2, true); - } -} - -/**************************************************************************** - * Name: board_autoled_off - ****************************************************************************/ - -void board_autoled_off(int led) -{ - if (led == 1) - { - stm32_gpiowrite(GPIO_LD2, false); - } -} - -#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/nucleo-f401re/src/stm32_boot.c b/boards/arm/stm32/nucleo-f401re/src/stm32_boot.c deleted file mode 100644 index 66eb41c6066f8..0000000000000 --- a/boards/arm/stm32/nucleo-f401re/src/stm32_boot.c +++ /dev/null @@ -1,101 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f401re/src/stm32_boot.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include -#include - -#include - -#include "arm_internal.h" -#include "nucleo-f401re.h" - -#include - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_boardinitialize - * - * Description: - * All STM32 architectures must provide the following entry point. - * This entry point is called early in the initialization -- after all - * memory has been configured and mapped but before any devices have been - * initialized. - * - ****************************************************************************/ - -void stm32_boardinitialize(void) -{ - /* Configure on-board LEDs if LED support has been selected. */ - -#ifdef CONFIG_ARCH_LEDS - board_autoled_initialize(); -#endif - - /* Configure SPI chip selects if 1) SP2 is not disabled, and 2) the weak - * function stm32_spidev_initialize() has been brought into the link. - */ - -#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || defined(CONFIG_STM32_SPI3) - stm32_spidev_initialize(); -#endif - - /* Initialize USB is 1) USBDEV is selected, 2) the USB controller is not - * disabled, and 3) the weak function stm32_usbinitialize() has been - * brought into the build. - */ - -#if defined(CONFIG_USBDEV) && defined(CONFIG_STM32_USB) - stm32_usbinitialize(); -#endif -} - -/**************************************************************************** - * Name: board_late_initialize - * - * Description: - * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional - * initialization call will be performed in the boot-up sequence to a - * function called board_late_initialize(). board_late_initialize() will - * be called immediately after up_initialize() is called and just before - * the initial application is started. This additional initialization - * phase may be used, for example, to initialize board-specific device - * drivers. - * - ****************************************************************************/ - -#ifdef CONFIG_BOARD_LATE_INITIALIZE -void board_late_initialize(void) -{ - stm32_bringup(); -} -#endif diff --git a/boards/arm/stm32/nucleo-f401re/src/stm32_bringup.c b/boards/arm/stm32/nucleo-f401re/src/stm32_bringup.c deleted file mode 100644 index d768f5dc584f6..0000000000000 --- a/boards/arm/stm32/nucleo-f401re/src/stm32_bringup.c +++ /dev/null @@ -1,212 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f401re/src/stm32_bringup.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include -#include - -#include -#include - -#include - -#ifdef CONFIG_USERLED -# include -#endif - -#ifdef CONFIG_INPUT_BUTTONS -# include -#endif - -#include "nucleo-f401re.h" - -#include - -#ifdef CONFIG_SENSORS_QENCODER -#include "board_qencoder.h" -#endif - -#undef HAVE_LEDS -#if !defined(CONFIG_ARCH_LEDS) && defined(CONFIG_USERLED_LOWER) -# define HAVE_LEDS 1 -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_bringup - * - * Description: - * Perform architecture-specific initialization - * - * CONFIG_BOARD_LATE_INITIALIZE=y : - * Called from board_late_initialize(). - * - ****************************************************************************/ - -int stm32_bringup(void) -{ - int ret = OK; - -#ifdef HAVE_LEDS - /* Register the LED driver */ - - ret = userled_lower_initialize("/dev/userleds"); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: userled_lower_initialize() failed: %d\n", ret); - return ret; - } -#endif - -#ifdef CONFIG_INPUT_BUTTONS - /* Register the BUTTON driver */ - - ret = btn_lower_initialize("/dev/buttons"); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: btn_lower_initialize() failed: %d\n", ret); - } -#endif - - /* Configure SPI-based devices */ - -#ifdef CONFIG_STM32_SPI1 - /* Get the SPI port */ - - struct spi_dev_s *spi; - - spi = stm32_spibus_initialize(1); - if (!spi) - { - syslog(LOG_ERR, "ERROR: Failed to initialize SPI port 1\n"); - return -ENODEV; - } - -#if defined(CONFIG_LCD_SSD1306_SPI) && !defined(CONFIG_VIDEO_FB) - board_lcd_initialize(); -#endif - -#ifdef CONFIG_VIDEO_FB - ret = fb_register(0, 0); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: fb_register() failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_CAN_MCP2515 -#ifdef CONFIG_STM32_SPI1 - stm32_configgpio(GPIO_MCP2515_CS); /* MEMS chip select */ -#endif - - /* Configure and initialize the MCP2515 CAN device */ - - ret = stm32_mcp2515initialize("/dev/can0"); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_mcp2515initialize() failed: %d\n", ret); - } -#endif -#endif - -#ifdef HAVE_MMCSD - /* First, get an instance of the SDIO interface */ - - g_sdio = sdio_initialize(CONFIG_NSH_MMCSDSLOTNO); - if (!g_sdio) - { - syslog(LOG_ERR, "ERROR: Failed to initialize SDIO slot %d\n", - CONFIG_NSH_MMCSDSLOTNO); - return -ENODEV; - } - - /* Now bind the SDIO interface to the MMC/SD driver */ - - ret = mmcsd_slotinitialize(CONFIG_NSH_MMCSDMINOR, g_sdio); - if (ret != OK) - { - syslog(LOG_ERR, - "ERROR: Failed to bind SDIO to the MMC/SD driver: %d\n", - ret); - return ret; - } - - /* Then let's guess and say that there is a card in the slot. There is no - * card detect GPIO. - */ - - sdio_mediachange(g_sdio, true); - - syslog(LOG_INFO, "[boot] Initialized SDIO\n"); -#endif - -#ifdef CONFIG_ADC - /* Initialize ADC and register the ADC driver. */ - - ret = stm32_adc_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_adc_setup failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_SENSORS_QENCODER - /* Initialize and register the qencoder driver */ - - ret = board_qencoder_initialize(0, CONFIG_NUCLEO_F401RE_QETIMER); - if (ret != OK) - { - syslog(LOG_ERR, - "ERROR: Failed to register the qencoder: %d\n", - ret); - return ret; - } -#endif - -#ifdef CONFIG_INPUT_AJOYSTICK - /* Initialize and register the joystick driver */ - - ret = board_ajoy_initialize(); - if (ret != OK) - { - syslog(LOG_ERR, - "ERROR: Failed to register the joystick driver: %d\n", - ret); - return ret; - } -#endif - - return ret; -} diff --git a/boards/arm/stm32/nucleo-f401re/src/stm32_buttons.c b/boards/arm/stm32/nucleo-f401re/src/stm32_buttons.c deleted file mode 100644 index b0a02f7a879d7..0000000000000 --- a/boards/arm/stm32/nucleo-f401re/src/stm32_buttons.c +++ /dev/null @@ -1,117 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f401re/src/stm32_buttons.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include - -#include "stm32_gpio.h" -#include "nucleo-f401re.h" - -#include - -#ifdef CONFIG_ARCH_BUTTONS - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_button_initialize - * - * Description: - * board_button_initialize() must be called to initialize button resources. - * After that, board_buttons() may be called to collect the current state - * of all buttons or board_button_irq() may be called to register button - * interrupt handlers. - * - ****************************************************************************/ - -uint32_t board_button_initialize(void) -{ - /* Configure the single button as an input. NOTE that EXTI interrupts are - * also configured for the pin. - */ - - stm32_configgpio(GPIO_BTN_USER); - return NUM_BUTTONS; -} - -/**************************************************************************** - * Name: board_buttons - ****************************************************************************/ - -uint32_t board_buttons(void) -{ - /* Check that state of each USER button. A LOW value means that the key is - * pressed. - */ - - bool released = stm32_gpioread(GPIO_BTN_USER); - return !released; -} - -/**************************************************************************** - * Button support. - * - * Description: - * board_button_initialize() must be called to initialize button resources. - * After that, board_buttons() may be called to collect the current state - * of all buttons or board_button_irq() may be called to register button - * interrupt handlers. - * - * After board_button_initialize() has been called, board_buttons() may be - * called to collect the state of all buttons. board_buttons() returns an - * 32-bit bit set with each bit associated with a button. See the - * BUTTON_*_BIT definitions in board.h for the meaning of each bit. - * - * board_button_irq() may be called to register an interrupt handler that - * will be called when a button is depressed or released. The ID value is a - * button enumeration value that uniquely identifies a button resource. See - * the BUTTON_* definitions in board.h for the meaning of enumeration - * value. - * - ****************************************************************************/ - -#ifdef CONFIG_ARCH_IRQBUTTONS -int board_button_irq(int id, xcpt_t irqhandler, void *arg) -{ - int ret = -EINVAL; - - if (id == BUTTON_USER) - { - ret = stm32_gpiosetevent(GPIO_BTN_USER, true, true, true, - irqhandler, arg); - } - - return ret; -} -#endif -#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/stm32/nucleo-f401re/src/stm32_lcd_ssd1306.c b/boards/arm/stm32/nucleo-f401re/src/stm32_lcd_ssd1306.c deleted file mode 100644 index 144f5b50c5802..0000000000000 --- a/boards/arm/stm32/nucleo-f401re/src/stm32_lcd_ssd1306.c +++ /dev/null @@ -1,88 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f401re/src/stm32_lcd_ssd1306.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include -#include -#include - -#include "stm32.h" -#include "nucleo-f401re.h" - -#include "stm32_ssd1306.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#define OLED_SPI_PORT 1 /* OLED display connected to SPI1 */ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_lcd_initialize - ****************************************************************************/ - -int board_lcd_initialize(void) -{ - int ret; - - ret = board_ssd1306_initialize(OLED_SPI_PORT); - if (ret < 0) - { - lcderr("ERROR: Failed to initialize SSD1306\n"); - return ret; - } - - return OK; -} - -/**************************************************************************** - * Name: board_lcd_getdev - ****************************************************************************/ - -struct lcd_dev_s *board_lcd_getdev(int devno) -{ - return board_ssd1306_getdev(); -} - -/**************************************************************************** - * Name: board_lcd_uninitialize - ****************************************************************************/ - -void board_lcd_uninitialize(void) -{ - /* TO-FIX */ -} diff --git a/boards/arm/stm32/nucleo-f401re/src/stm32_mcp2515.c b/boards/arm/stm32/nucleo-f401re/src/stm32_mcp2515.c deleted file mode 100644 index 5ed40a07fdebb..0000000000000 --- a/boards/arm/stm32/nucleo-f401re/src/stm32_mcp2515.c +++ /dev/null @@ -1,241 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f401re/src/stm32_mcp2515.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include "stm32.h" -#include "stm32_spi.h" -#include "nucleo-f401re.h" - -#if defined(CONFIG_SPI) && defined(CONFIG_STM32_SPI1) && \ - defined(CONFIG_CAN_MCP2515) - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#define MCP2515_SPI_PORTNO 1 /* On SPI1 */ - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -struct stm32_mcp2515config_s -{ - /* Configuration structure as seen by the MCP2515 driver */ - - struct mcp2515_config_s config; - - /* Additional private definitions only known to this driver */ - - struct mcp2515_can_s *handle; /* The MCP2515 driver handle */ - mcp2515_handler_t handler; /* The MCP2515 interrupt handler */ - void *arg; /* Argument to pass to the interrupt handler */ -}; - -/**************************************************************************** - * Static Function Prototypes - ****************************************************************************/ - -/* IRQ/GPIO access callbacks. These operations all hidden behind callbacks - * to isolate the MCP2515 driver from differences in GPIO interrupt handling - * by varying boards and MCUs. - * - * attach - Attach the MCP2515 interrupt handler to the GPIO interrupt - */ - -static int mcp2515_attach(struct mcp2515_config_s *state, - mcp2515_handler_t handler, void *arg); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* A reference to a structure of this type must be passed to the MCP2515 - * driver. This structure provides information about the configuration - * of the MCP2515 and provides some board-specific hooks. - * - * Memory for this structure is provided by the caller. It is not copied - * by the driver and is presumed to persist while the driver is active. The - * memory must be writable because, under certain circumstances, the driver - * may modify frequency or X plate resistance values. - */ - -static struct stm32_mcp2515config_s g_mcp2515config = -{ - .config = - { - .spi = NULL, - .baud = 0, /* REVISIT. Probably broken by commit eb7373cedfa */ - .btp = 0, /* REVISIT. Probably broken by commit eb7373cedfa */ - .devid = 0, - .mode = 0, /* REVISIT. Probably broken by commit eb7373cedfa */ - .nfilters = 6, -#ifdef MCP2515_LOOPBACK - .loopback = false; -#endif - .attach = mcp2515_attach, - }, -}; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/* This is the MCP2515 Interrupt handler */ - -int mcp2515_interrupt(int irq, void *context, void *arg) -{ - struct stm32_mcp2515config_s *priv = - (struct stm32_mcp2515config_s *)arg; - - DEBUGASSERT(priv != NULL); - - /* Verify that we have a handler attached */ - - if (priv->handler) - { - /* Yes.. forward with interrupt along with its argument */ - - priv->handler(&priv->config, priv->arg); - } - - return OK; -} - -static int mcp2515_attach(struct mcp2515_config_s *state, - mcp2515_handler_t handler, void *arg) -{ - struct stm32_mcp2515config_s *priv = - (struct stm32_mcp2515config_s *)state; - irqstate_t flags; - - caninfo("Saving handler %p\n", handler); - - flags = enter_critical_section(); - - priv->handler = handler; - priv->arg = arg; - - /* Configure the interrupt for falling edge */ - - stm32_gpiosetevent(GPIO_MCP2515_IRQ, false, true, false, - mcp2515_interrupt, priv); - - leave_critical_section(flags); - - return OK; -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_mcp2515initialize - * - * Description: - * Initialize and register the MCP2515 RFID driver. - * - * Input Parameters: - * devpath - The full path to the driver to register. E.g., "/dev/rfid0" - * - * Returned Value: - * Zero (OK) on success; a negated errno value on failure. - * - ****************************************************************************/ - -int stm32_mcp2515initialize(const char *devpath) -{ - struct spi_dev_s *spi; - struct can_dev_s *can; - struct mcp2515_can_s *mcp2515; - int ret; - - /* Check if we are already initialized */ - - if (!g_mcp2515config.handle) - { - sninfo("Initializing\n"); - - /* Configure the MCP2515 interrupt pin as an input */ - - stm32_configgpio(GPIO_MCP2515_IRQ); - - spi = stm32_spibus_initialize(MCP2515_SPI_PORTNO); - - if (!spi) - { - return -ENODEV; - } - - /* Save the SPI instance in the mcp2515_config_s structure */ - - g_mcp2515config.config.spi = spi; - - /* Instantiate the MCP2515 CAN Driver */ - - mcp2515 = mcp2515_instantiate(&g_mcp2515config.config); - if (mcp2515 == NULL) - { - canerr("ERROR: Failed to get MCP2515 Driver Loaded\n"); - return -ENODEV; - } - - /* Save the opaque structure */ - - g_mcp2515config.handle = mcp2515; - - /* Initialize the CAN Device with the MCP2515 operations */ - - can = mcp2515_initialize(mcp2515); - if (can == NULL) - { - canerr("ERROR: Failed to get CAN interface\n"); - return -ENODEV; - } - - /* Register the CAN driver at "/dev/can0" */ - - ret = can_register(devpath, can); - if (ret < 0) - { - canerr("ERROR: can_register failed: %d\n", ret); - return ret; - } - } - - return OK; -} - -#endif /* CONFIG_SPI && CONFIG_CAN_MCP2515 */ diff --git a/boards/arm/stm32/nucleo-f401re/src/stm32_spi.c b/boards/arm/stm32/nucleo-f401re/src/stm32_spi.c deleted file mode 100644 index 2b7cf5fac7921..0000000000000 --- a/boards/arm/stm32/nucleo-f401re/src/stm32_spi.c +++ /dev/null @@ -1,246 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f401re/src/stm32_spi.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include - -#include - -#include "arm_internal.h" -#include "chip.h" -#include "stm32.h" - -#include "nucleo-f401re.h" - -#include - -#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || \ - defined(CONFIG_STM32_SPI3) - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/* Global driver instances */ - -#ifdef CONFIG_STM32_SPI1 -struct spi_dev_s *g_spi1; -#endif -#ifdef CONFIG_STM32_SPI2 -struct spi_dev_s *g_spi2; -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_spidev_initialize - * - * Description: - * Called to configure SPI chip select GPIO pins for the Nucleo-F401RE - * - ****************************************************************************/ - -void weak_function stm32_spidev_initialize(void) -{ -#ifdef CONFIG_STM32_SPI1 - /* Configure SPI-based devices */ - - g_spi1 = stm32_spibus_initialize(1); - if (!g_spi1) - { - spierr("ERROR: FAILED to initialize SPI port 1\n"); - } - -#ifdef CONFIG_LCD_SSD1306_SPI - stm32_configgpio(GPIO_SSD1306_CS); /* SSD1306 chip select */ - stm32_configgpio(GPIO_SSD1306_CMD); /* SSD1306 data/!command */ -#endif - -#ifdef CONFIG_CAN_MCP2515 - stm32_configgpio(GPIO_MCP2515_CS); /* MCP2515 chip select */ -#endif - -#ifdef HAVE_MMCSD - stm32_configgpio(GPIO_SPI_CS_SD_CARD); -#endif -#endif - -#ifdef CONFIG_STM32_SPI2 - /* Configure SPI-based devices */ - - g_spi2 = stm32_spibus_initialize(2); -#endif -} - -/**************************************************************************** - * Name: stm32_spi1/2/3select and stm32_spi1/2/3status - * - * Description: - * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status - * must be provided by board-specific logic. They are implementations of - * the select and status methods of the SPI interface defined by struct - * spi_ops_s (see include/nuttx/spi/spi.h). All other methods (including - * stm32_spibus_initialize()) are provided by common STM32 logic. To use - * this common SPI logic on your board: - * - * 1. Provide logic in stm32_boardinitialize() to configure SPI chip select - * pins. - * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() functions - * in your board-specific logic. These functions will perform chip - * selection and status operations using GPIOs in the way your board is - * configured. - * 3. Add a calls to stm32_spibus_initialize() in your low level - * application initialization logic - * 4. The handle returned by stm32_spibus_initialize() may then be used to - * bind the SPI driver to higher level logic (e.g., calling - * mmcsd_spislotinitialize(), for example, will bind the SPI driver to - * the SPI MMC/SD driver). - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_SPI1 -void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, - bool selected) -{ - spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : - "de-assert"); - -#if defined(CONFIG_LCD_SSD1306_SPI) - if (devid == SPIDEV_DISPLAY(0)) - { - stm32_gpiowrite(GPIO_SSD1306_CS, !selected); - } -#endif - -#if defined(CONFIG_CAN_MCP2515) - if (devid == SPIDEV_CANBUS(0)) - { - stm32_gpiowrite(GPIO_MCP2515_CS, !selected); - } -#endif - -#ifdef HAVE_MMCSD - if (devid == SPIDEV_MMCSD(0)) - { - stm32_gpiowrite(GPIO_SPI_CS_SD_CARD, !selected); - } -#endif -} - -uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) -{ - return 0; -} -#endif - -#ifdef CONFIG_STM32_SPI2 -void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid, - bool selected) -{ - spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : - "de-assert"); -} - -uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) -{ - return 0; -} -#endif - -#ifdef CONFIG_STM32_SPI3 -void stm32_spi3select(struct spi_dev_s *dev, uint32_t devid, - bool selected) -{ - spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : - "de-assert"); -} - -uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid) -{ - return 0; -} -#endif - -/**************************************************************************** - * Name: stm32_spi1cmddata - * - * Description: - * Set or clear the SH1101A A0 or SD1306 D/C n bit to select data (true) - * or command (false). This function must be provided by platform-specific - * logic. This is an implementation of the cmddata method of the SPI - * interface defined by struct spi_ops_s (see include/nuttx/spi/spi.h). - * - * Input Parameters: - * - * spi - SPI device that controls the bus the device that requires the CMD/ - * DATA selection. - * devid - If there are multiple devices on the bus, this selects which one - * to select cmd or data. NOTE: This design restricts, for example, - * one one SPI display per SPI bus. - * cmd - true: select command; false: select data - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef CONFIG_SPI_CMDDATA -#ifdef CONFIG_STM32_SPI1 -int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) -{ -#if defined(CONFIG_LCD_SSD1306_SPI) - if (devid == SPIDEV_DISPLAY(0)) - { - stm32_gpiowrite(GPIO_SSD1306_CMD, !cmd); - } -#endif - - return OK; -} -#endif - -#ifdef CONFIG_STM32_SPI2 -int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) -{ - return OK; -} -#endif - -#ifdef CONFIG_STM32_SPI3 -int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) -{ - return OK; -} -#endif -#endif /* CONFIG_SPI_CMDDATA */ - -#endif /* CONFIG_STM32_SPI1 || CONFIG_STM32_SPI2 || CONFIG_STM32_SPI3 */ diff --git a/boards/arm/stm32/nucleo-f401re/src/stm32_userleds.c b/boards/arm/stm32/nucleo-f401re/src/stm32_userleds.c deleted file mode 100644 index 0415373cc07eb..0000000000000 --- a/boards/arm/stm32/nucleo-f401re/src/stm32_userleds.c +++ /dev/null @@ -1,218 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f401re/src/stm32_userleds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include - -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32.h" -#include "nucleo-f401re.h" - -#include - -#ifndef CONFIG_ARCH_LEDS - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -/* LED Power Management */ - -#ifdef CONFIG_PM -static void led_pm_notify(struct pm_callback_s *cb, int domain, - enum pm_state_e pmstate); -static int led_pm_prepare(struct pm_callback_s *cb, int domain, - enum pm_state_e pmstate); -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -#ifdef CONFIG_PM -static struct pm_callback_s g_ledscb = -{ - .notify = led_pm_notify, - .prepare = led_pm_prepare, -}; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: led_pm_notify - * - * Description: - * Notify the driver of new power state. This callback is called after - * all drivers have had the opportunity to prepare for the new power state. - * - ****************************************************************************/ - -#ifdef CONFIG_PM -static void led_pm_notify(struct pm_callback_s *cb, int domain, - enum pm_state_e pmstate) -{ - switch (pmstate) - { - case PM_NORMAL: - { - /* Restore normal LEDs operation */ - } - break; - - case PM_IDLE: - { - /* Entering IDLE mode - Turn leds off */ - } - break; - - case PM_STANDBY: - { - /* Entering STANDBY mode - Logic for PM_STANDBY goes here */ - } - break; - - case PM_SLEEP: - { - /* Entering SLEEP mode - Logic for PM_SLEEP goes here */ - } - break; - - default: - { - /* Should not get here */ - } - break; - } -} -#endif - -/**************************************************************************** - * Name: led_pm_prepare - * - * Description: - * Request the driver to prepare for a new power state. This is a warning - * that the system is about to enter into a new power state. The driver - * should begin whatever operations that may be required to enter power - * state. The driver may abort the state change mode by returning a - * non-zero value from the callback function. - * - ****************************************************************************/ - -#ifdef CONFIG_PM -static int led_pm_prepare(struct pm_callback_s *cb, int domain, - enum pm_state_e pmstate) -{ - /* No preparation to change power modes is required by the LEDs driver. - * We always accept the state change by returning OK. - */ - - return OK; -} -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_userled_initialize - ****************************************************************************/ - -uint32_t board_userled_initialize(void) -{ - /* Configure LD2 GPIO for output */ - - stm32_configgpio(GPIO_LD2); - return BOARD_NLEDS; -} - -/**************************************************************************** - * Name: board_userled - ****************************************************************************/ - -void board_userled(int led, bool ledon) -{ - if (BOARD_LD2_BIT == (1 << led)) - { - stm32_gpiowrite(GPIO_LD2, ledon); - } -} - -/**************************************************************************** - * Name: board_userled_all - ****************************************************************************/ - -void board_userled_all(uint32_t ledset) -{ - /* An output of '1' illuminates the LED */ - - stm32_gpiowrite(GPIO_LD2, (ledset & BOARD_LD2_BIT) != 0); -} - -#ifdef CONFIG_USERLED_LOWER_READSTATE -/**************************************************************************** - * Name: board_userled_getall - ****************************************************************************/ - -void board_userled_getall(uint32_t *ledset) -{ - /* Clear the LED bits */ - - *ledset = 0; - - /* Get LED state. An output of '1' illuminates the LED. */ - - *ledset |= ((stm32_gpioread(GPIO_LD2) & 1) << BOARD_LD2); -} - -#endif /* CONFIG_USERLED_LOWER_READSTATE */ - -/**************************************************************************** - * Name: stm32_led_pminitialize - ****************************************************************************/ - -#ifdef CONFIG_PM -void stm32_led_pminitialize(void) -{ - /* Register to receive power management callbacks */ - - int ret = pm_register(&g_ledscb); - DEBUGASSERT(ret == OK); - UNUSED(ret); -} -#endif /* CONFIG_PM */ - -#endif /* !CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/nucleo-f410rb/CMakeLists.txt b/boards/arm/stm32/nucleo-f410rb/CMakeLists.txt deleted file mode 100644 index 9c873cd876538..0000000000000 --- a/boards/arm/stm32/nucleo-f410rb/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/nucleo-f410rb/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32/nucleo-f410rb/configs/nsh/defconfig b/boards/arm/stm32/nucleo-f410rb/configs/nsh/defconfig deleted file mode 100644 index 58fb8efa0e53d..0000000000000 --- a/boards/arm/stm32/nucleo-f410rb/configs/nsh/defconfig +++ /dev/null @@ -1,57 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -# CONFIG_NSH_DISABLE_IFCONFIG is not set -# CONFIG_NSH_DISABLE_PS is not set -CONFIG_ADC=y -CONFIG_ANALOG=y -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="nucleo-f410rb" -CONFIG_ARCH_BOARD_NUCLEO_F410RB=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F410RB=y -CONFIG_ARCH_INTERRUPTSTACK=2048 -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=8499 -CONFIG_BUILTIN=y -CONFIG_EXAMPLES_HELLO=y -CONFIG_HAVE_CXX=y -CONFIG_HEAP_COLORATION=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=32768 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_SERIAL_TERMIOS=y -CONFIG_STACK_COLORATION=y -CONFIG_START_DAY=25 -CONFIG_START_MONTH=9 -CONFIG_START_YEAR=2017 -CONFIG_STM32_ADC1=y -CONFIG_STM32_ADC1_DMA=y -CONFIG_STM32_DMA2=y -CONFIG_STM32_FLASH_CONFIG_B=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_PWR=y -CONFIG_STM32_USART2=y -CONFIG_SYSTEM_CLE=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART2_SERIAL_CONSOLE=y -CONFIG_USERLED=y -CONFIG_USERLED_LOWER=y diff --git a/boards/arm/stm32/nucleo-f410rb/include/board.h b/boards/arm/stm32/nucleo-f410rb/include/board.h deleted file mode 100644 index 0da6ad80797b0..0000000000000 --- a/boards/arm/stm32/nucleo-f410rb/include/board.h +++ /dev/null @@ -1,303 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f410rb/include/board.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __BOARDS_ARM_STM32_NUCLEO_F410RB_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32_NUCLEO_F410RB_INCLUDE_BOARD_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#ifndef __ASSEMBLY__ -# include -#endif - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Clocking *****************************************************************/ - -/* The NUCLEO410RB supports both HSE and LSE crystals (X2 and X3). - * However, as shipped, the X3 crystals is not populated. - * Therefore the Nucleo-F410RB will need to run off the 16MHz HSI clock. - * - * System Clock source : PLL (HSI) - * SYSCLK(Hz) : 100000000 Determined by PLL configuration - * HCLK(Hz) : 100000000 (STM32_RCC_CFGR_HPRE) - * AHB Prescaler : 1 (STM32_RCC_CFGR_HPRE) - * APB1 Prescaler : 2 (STM32_RCC_CFGR_PPRE1) - * APB2 Prescaler : 1 (STM32_RCC_CFGR_PPRE2) - * HSI Frequency(Hz) : 16000000 (nominal) - * PLLM : 2 (STM32_PLLCFG_PLLM) - * PLLN : 50 (STM32_PLLCFG_PLLN) - * PLLP : 4 (STM32_PLLCFG_PLLP) - * PLLQ : 8 (STM32_PLLCFG_PPQ) - * Flash Latency(WS) : 5 - * Prefetch Buffer : OFF - * Instruction cache : ON - * Data cache : ON - */ - -/* HSI - 16 MHz RC factory-trimmed - * LSI - 32 KHz RC - * HSE - not installed - * LSE - not installed - */ - -#define STM32_HSI_FREQUENCY 16000000ul -#define STM32_LSI_FREQUENCY 32000 -#define STM32_BOARD_USEHSI 1 - -/* Main PLL Configuration. - * - * Formulae: - * - * VCO input frequency = PLL input clock frequency / PLLM, - * 2 <= PLLM <= 63 - * VCO output frequency = VCO input frequency � PLLN, - * 50 <= PLLN <= 432 - * PLL output clock frequency = VCO frequency / PLLP, - * PLLP = 2, 4, 6, or 8 - * USB OTG FS clock frequency = VCO frequency / PLLQ, - * 2 <= PLLQ <= 15 - * - * We will configure like this - * - * PLL source is HSI - * PLL_VCO = (STM32_HSI_FREQUENCY / PLLM) * PLLN - * = (16,000,000 / 2) * 50 - * = 400,000,000 - * SYSCLK = PLL_VCO / PLLP - * = 400,000,000 / 4 = 100,000,000 - * RNG Clock - * = PLL_VCO / PLLQ - * = 400,000,000 / 8 = 50,000,000 - * - * REVISIT: Trimming of the HSI is not yet supported. - */ - -#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(2) -#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(50) -#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_4 -#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(8) - -#define STM32_SYSCLK_FREQUENCY 100000000ul - -/* AHB clock (HCLK) is SYSCLK (100MHz) */ - -#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ -#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY - -/* APB1 clock (PCLK1) is HCLK/2 (50MHz) */ - -#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd2 /* PCLK1 = HCLK / 2 */ -#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/2) - -/* Timers driven from APB1 will be twice PCLK1 */ - -/* REVISIT */ - -#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) - -/* APB2 clock (PCLK2) is HCLK (100MHz) */ - -#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK */ -#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY) - -/* Timers driven from APB2 will be PCLK2 */ - -/* REVISIT */ - -#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM9_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM11_CLKIN (STM32_PCLK2_FREQUENCY) - -/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx - * otherwise frequency is 2xAPBx. - * Note: TIM1,9,11 are on APB2, others on APB1 - */ - -/* REVISIT */ - -#define BOARD_TIM1_FREQUENCY STM32_APB2_TIM1_CLKIN -#define BOARD_TIM5_FREQUENCY STM32_APB1_TIM5_CLKIN -#define BOARD_TIM6_FREQUENCY STM32_APB1_TIM6_CLKIN -#define BOARD_TIM9_FREQUENCY STM32_APB2_TIM9_CLKIN -#define BOARD_TIM11_FREQUENCY STM32_APB2_TIM11_CLKIN - -/* DMA Channel/Stream Selections ********************************************/ - -/* Stream selections are arbitrary for now but might become important in the - * future is we set aside more DMA channels/streams. - */ - -#define ADC1_DMA_CHAN DMAMAP_ADC1_1 -#define GPIO_TIM1_CH1OUT (GPIO_TIM1_CH1OUT_1|GPIO_SPEED_50MHz) - -#define DMACHAN_SPI1_RX DMAMAP_SPI1_RX_1 -#define DMACHAN_SPI1_TX DMAMAP_SPI1_TX_1 -#define DMACHAN_SPI2_RX DMAMAP_SPI2_RX -#define DMACHAN_SPI2_TX DMAMAP_SPI2_TX - -/* Alternate function pin selections ****************************************/ - -/* USART1: - * RXD: PA10 CN9 pin 3, CN10 pin 33 - * PB7 CN7 pin 21 - * TXD: PA9 CN5 pin 1, CN10 pin 21 - * PB6 CN5 pin 3, CN10 pin 17 - */ - -#if 1 -# define GPIO_USART1_RX (GPIO_USART1_RX_1|GPIO_SPEED_100MHz) /* PA10 */ -# define GPIO_USART1_TX (GPIO_USART1_TX_1|GPIO_SPEED_100MHz) /* PA9 */ -#else -# define GPIO_USART1_RX (GPIO_USART1_RX_2|GPIO_SPEED_100MHz) /* PB7 */ -# define GPIO_USART1_TX (GPIO_USART1_TX_2|GPIO_SPEED_100MHz) /* PB6 */ -#endif - -/* USART2: - * RXD: PA3 CN9 pin 1 (See SB13, 14, 62, 63). CN10 pin 37 - * PD6 - * TXD: PA2 CN9 pin 2(See SB13, 14, 62, 63). CN10 pin 35 - * PD5 - */ - -#define GPIO_USART2_RX (GPIO_USART2_RX_1|GPIO_SPEED_100MHz) /* PA3 */ -#define GPIO_USART2_TX (GPIO_USART2_TX_1|GPIO_SPEED_100MHz) /* PA2 */ -#define GPIO_USART2_RTS GPIO_USART2_RTS_2 -#define GPIO_USART2_CTS GPIO_USART2_CTS_2 - -/* USART6: - * RXD: PC7 CN5 pin2, CN10 pin 19 - * PA12 CN10, pin 12 - * TXD: PC6 CN10, pin 4 - * PA11 CN10, pin 14 - */ - -#define GPIO_USART6_RX (GPIO_USART6_RX_1|GPIO_SPEED_100MHz) /* PC7 */ -#define GPIO_USART6_TX (GPIO_USART6_TX_1|GPIO_SPEED_100MHz) /* PC6 */ - -/* UART RX DMA configurations */ - -#define DMAMAP_USART1_RX DMAMAP_USART1_RX_2 -#define DMAMAP_USART6_RX DMAMAP_USART6_RX_2 - -/* I2C - * - * The optional _GPIO configurations allow the I2C driver to manually - * reset the bus to clear stuck slaves. They match the pin configuration, - * but are normally-high GPIOs. - */ - -#define GPIO_I2C1_SCL (GPIO_I2C1_SCL_2|GPIO_SPEED_50MHz) -#define GPIO_I2C1_SDA (GPIO_I2C1_SDA_2|GPIO_SPEED_50MHz) -#define GPIO_I2C1_SCL_GPIO \ - (GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTB|GPIO_PIN8) -#define GPIO_I2C1_SDA_GPIO \ - (GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTB|GPIO_PIN9) - -#define GPIO_I2C2_SCL (GPIO_I2C2_SCL_1|GPIO_SPEED_50MHz) -#define GPIO_I2C2_SDA (GPIO_I2C2_SDA_1|GPIO_SPEED_50MHz) -#define GPIO_I2C2_SCL_GPIO \ - (GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTB|GPIO_PIN10) -#define GPIO_I2C2_SDA_GPIO \ - (GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTB|GPIO_PIN11) - -/* SPI - * - */ - -#define GPIO_SPI1_MISO (GPIO_SPI1_MISO_1|GPIO_SPEED_50MHz) -#define GPIO_SPI1_MOSI (GPIO_SPI1_MOSI_1|GPIO_SPEED_50MHz) -#define GPIO_SPI1_SCK (GPIO_SPI1_SCK_1|GPIO_SPEED_50MHz) - -#define GPIO_SPI2_MISO (GPIO_SPI2_MISO_1|GPIO_SPEED_50MHz) -#define GPIO_SPI2_MOSI (GPIO_SPI2_MOSI_1|GPIO_SPEED_50MHz) -#define GPIO_SPI2_SCK (GPIO_SPI2_SCK_2|GPIO_SPEED_50MHz) - -/* LEDs - * - * The Nucleo F410RB board provide a single user LED, LD2. LD2 - * is the green LED connected to Arduino signal D13 corresponding to MCU I/O - * PA5 (pin 21) or PB13 (pin 34) depending on the STM32 target. - * - * - When the I/O is HIGH value, the LED is on. - * - When the I/O is LOW, the LED is off. - */ - -/* LED index values for use with board_userled() */ - -#define BOARD_LD2 0 -#define BOARD_NLEDS 1 - -/* LED bits for use with board_userled_all() */ - -#define BOARD_LD2_BIT (1 << BOARD_LD2) - -/* These LEDs are not used by the board port unless CONFIG_ARCH_LEDS is - * defined. In that case, the usage by the board port is defined in - * include/board.h and src/sam_leds.c. The LEDs are used to encode OS-related - * events as follows when the red LED (PE24) is available: - * - * SYMBOL Meaning LD2 - * ------------------- ----------------------- ----------- - * LED_STARTED NuttX has been started OFF - * LED_HEAPALLOCATE Heap has been allocated OFF - * LED_IRQSENABLED Interrupts enabled OFF - * LED_STACKCREATED Idle stack created ON - * LED_INIRQ In an interrupt No change - * LED_SIGNAL In a signal handler No change - * LED_ASSERTION An assertion failed No change - * LED_PANIC The system has crashed Blinking - * LED_IDLE MCU is in sleep mode Not used - * - * Thus if LD2, NuttX has successfully booted and is, apparently, running - * normally. If LD2 is flashing at approximately 2Hz, then a fatal error - * has been detected and the system has halted. - */ - -#define LED_STARTED 0 -#define LED_HEAPALLOCATE 0 -#define LED_IRQSENABLED 0 -#define LED_STACKCREATED 1 -#define LED_INIRQ 2 -#define LED_SIGNAL 2 -#define LED_ASSERTION 2 -#define LED_PANIC 1 - -/* Buttons - * - * B1 USER: - * the user button is connected to the I/O PC13 (pin 2) of the STM32 - * microcontroller. - */ - -#define BUTTON_USER 0 -#define NUM_BUTTONS 1 - -#define BUTTON_USER_BIT (1 << BUTTON_USER) - -#endif /* __BOARDS_ARM_STM32_NUCLEO_F410RB_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32/nucleo-f410rb/scripts/Make.defs b/boards/arm/stm32/nucleo-f410rb/scripts/Make.defs deleted file mode 100644 index af0a457b2633d..0000000000000 --- a/boards/arm/stm32/nucleo-f410rb/scripts/Make.defs +++ /dev/null @@ -1,41 +0,0 @@ -############################################################################ -# boards/arm/stm32/nucleo-f410rb/scripts/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/.config -include $(TOPDIR)/tools/Config.mk -include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs - -LDSCRIPT = f410rb.ld -ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) - -ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 - -CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) -CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) -CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -AFLAGS := $(CFLAGS) -D__ASSEMBLY__ - -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections -LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32/nucleo-f410rb/src/CMakeLists.txt b/boards/arm/stm32/nucleo-f410rb/src/CMakeLists.txt deleted file mode 100644 index df15551bccbbe..0000000000000 --- a/boards/arm/stm32/nucleo-f410rb/src/CMakeLists.txt +++ /dev/null @@ -1,41 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/nucleo-f410rb/src/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -set(SRCS stm32_boot.c stm32_bringup.c) - -if(CONFIG_ARCH_LEDS) - list(APPEND SRCS stm32_autoleds.c) -else() - list(APPEND SRCS stm32_userleds.c) -endif() - -if(CONFIG_ARCH_BUTTONS) - list(APPEND SRCS stm32_buttons.c) -endif() - -if(CONFIG_ADC) - list(APPEND SRCS stm32_adc.c) -endif() - -target_sources(board PRIVATE ${SRCS}) - -set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/f410rb.ld") diff --git a/boards/arm/stm32/nucleo-f410rb/src/Make.defs b/boards/arm/stm32/nucleo-f410rb/src/Make.defs deleted file mode 100644 index abd7559d83199..0000000000000 --- a/boards/arm/stm32/nucleo-f410rb/src/Make.defs +++ /dev/null @@ -1,43 +0,0 @@ -############################################################################ -# boards/arm/stm32/nucleo-f410rb/src/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/Make.defs - -CSRCS = stm32_boot.c stm32_bringup.c - -ifeq ($(CONFIG_ARCH_LEDS),y) -CSRCS += stm32_autoleds.c -else -CSRCS += stm32_userleds.c -endif - -ifeq ($(CONFIG_ARCH_BUTTONS),y) -CSRCS += stm32_buttons.c -endif - -ifeq ($(CONFIG_ADC),y) -CSRCS += stm32_adc.c -endif - -DEPPATH += --dep-path board -VPATH += :board -CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/nucleo-f410rb/src/stm32_adc.c b/boards/arm/stm32/nucleo-f410rb/src/stm32_adc.c deleted file mode 100644 index cf679ab14d277..0000000000000 --- a/boards/arm/stm32/nucleo-f410rb/src/stm32_adc.c +++ /dev/null @@ -1,142 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f410rb/src/stm32_adc.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include -#include - -#include "chip.h" -#include "arm_internal.h" -#include "nucleo-f410rb.h" - -#ifdef CONFIG_STM32_ADC1 - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* The number of ADC channels in the conversion list */ - -#ifdef CONFIG_STM32_ADC1_DMA -# define ADC1_NCHANNELS 2 -#else -# define ADC1_NCHANNELS 1 -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* Identifying number of each ADC channel. */ - -#ifdef CONFIG_STM32_ADC1_DMA -/* ADC_IN0 and ADC_IN1 */ - -static const uint8_t g_adc1_chanlist[ADC1_NCHANNELS] = -{ - 9, 8 -}; - -/* Configurations of pins used byte each ADC channels */ - -static const uint32_t g_adc1_pinlist[ADC1_NCHANNELS] = -{ - GPIO_ADC1_IN9_0, GPIO_ADC1_IN8_0 -}; - -#else -/* Without DMA, only a single channel can be supported */ - -/* ADC_IN0 */ - -static const uint8_t g_adc1_chanlist[ADC1_NCHANNELS] = -{ - 9 -}; - -/* Configurations of pins used byte each ADC channels */ - -static const uint32_t g_adc1_pinlist[ADC1_NCHANNELS] = -{ - GPIO_ADC1_IN9_0 -}; - -#endif /* CONFIG_STM32_ADC1_DMA */ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_adc_setup - * - * Description: - * Initialize ADC and register the ADC driver. - * - ****************************************************************************/ - -int stm32_adc_setup(void) -{ - struct adc_dev_s *adc; - int ret; - int i; - - /* Configure the pins as analog inputs for the selected channels */ - - syslog(LOG_ERR, "stm32_adc_setup configuration: %d\n", ADC1_NCHANNELS); - - for (i = 0; i < ADC1_NCHANNELS; i++) - { - stm32_configgpio(g_adc1_pinlist[i]); - } - - /* Call stm32_adcinitialize() to get an instance of the ADC interface */ - - adc = stm32_adcinitialize(1, g_adc1_chanlist, ADC1_NCHANNELS); - if (adc == NULL) - { - aerr("ERROR: Failed to get ADC interface\n"); - return -ENODEV; - } - - /* Register the ADC driver at "/dev/adc0" */ - - ret = adc_register("/dev/adc0", adc); - if (ret < 0) - { - aerr("ERROR: adc_register failed: %d\n", ret); - return ret; - } - - return OK; -} - -#endif /* CONFIG_STM32_ADC1 */ diff --git a/boards/arm/stm32/nucleo-f410rb/src/stm32_autoleds.c b/boards/arm/stm32/nucleo-f410rb/src/stm32_autoleds.c deleted file mode 100644 index 4eaaaf20686ff..0000000000000 --- a/boards/arm/stm32/nucleo-f410rb/src/stm32_autoleds.c +++ /dev/null @@ -1,82 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f410rb/src/stm32_autoleds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32.h" -#include "nucleo-f410rb.h" - -#ifdef CONFIG_ARCH_LEDS - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_autoled_initialize - ****************************************************************************/ - -void board_autoled_initialize(void) -{ - /* Configure LD2 GPIO for output */ - - stm32_configgpio(GPIO_LD2); -} - -/**************************************************************************** - * Name: board_autoled_on - ****************************************************************************/ - -void board_autoled_on(int led) -{ - if (led == 1) - { - stm32_gpiowrite(GPIO_LD2, true); - } -} - -/**************************************************************************** - * Name: board_autoled_off - ****************************************************************************/ - -void board_autoled_off(int led) -{ - if (led == 1) - { - stm32_gpiowrite(GPIO_LD2, false); - } -} - -#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/nucleo-f410rb/src/stm32_boot.c b/boards/arm/stm32/nucleo-f410rb/src/stm32_boot.c deleted file mode 100644 index d85baaa2d49d3..0000000000000 --- a/boards/arm/stm32/nucleo-f410rb/src/stm32_boot.c +++ /dev/null @@ -1,95 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f410rb/src/stm32_boot.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include -#include -#include - -#include "arm_internal.h" -#include "nucleo-f410rb.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_boardinitialize - * - * Description: - * All STM32 architectures must provide the following entry point. This - * entry point is called early in the initialization -- after all memory - * has been configured and mapped but before any devices have been - * initialized. - * - ****************************************************************************/ - -void stm32_boardinitialize(void) -{ -#ifdef CONFIG_ARCH_LEDS - /* Configure on-board LEDs if LED support has been selected. */ - - board_autoled_initialize(); -#endif - -#ifdef CONFIG_ARCH_BUTTONS - /* Configure on-board BUTTONs if BUTTON support has been selected. */ - - board_button_initialize(); -#endif -} - -/**************************************************************************** - * Name: board_late_initialize - * - * Description: - * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional - * initialization call will be performed in the boot-up sequence to a - * function called board_late_initialize(). board_late_initialize() will - * be called immediately after up_initialize() is called and just before - * the initial application is started. This additional initialization - * phase may be used, for example, to initialize board-specific device - * drivers. - * - ****************************************************************************/ - -#ifdef CONFIG_BOARD_LATE_INITIALIZE -void board_late_initialize(void) -{ - stm32_bringup(); -} -#endif diff --git a/boards/arm/stm32/nucleo-f410rb/src/stm32_bringup.c b/boards/arm/stm32/nucleo-f410rb/src/stm32_bringup.c deleted file mode 100644 index 043d8c543a8f0..0000000000000 --- a/boards/arm/stm32/nucleo-f410rb/src/stm32_bringup.c +++ /dev/null @@ -1,70 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f410rb/src/stm32_bringup.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include - -#include - -#include "nucleo-f410rb.h" - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_bringup - * - * Description: - * Perform architecture-specific initialization - * - * CONFIG_BOARD_LATE_INITIALIZE=y : - * Called from board_late_initialize(). - * - ****************************************************************************/ - -int stm32_bringup(void) -{ - int ret; - -#ifdef CONFIG_ADC - /* Initialize ADC and register the ADC driver. */ - - ret = stm32_adc_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_adc_setup failed: %d\n", ret); - } -#endif - - UNUSED(ret); - return OK; -} diff --git a/boards/arm/stm32/nucleo-f410rb/src/stm32_buttons.c b/boards/arm/stm32/nucleo-f410rb/src/stm32_buttons.c deleted file mode 100644 index 0797e9f5139f5..0000000000000 --- a/boards/arm/stm32/nucleo-f410rb/src/stm32_buttons.c +++ /dev/null @@ -1,115 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f410rb/src/stm32_buttons.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include -#include - -#include "nucleo-f410rb.h" - -#ifdef CONFIG_ARCH_BUTTONS - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_button_initialize - * - * Description: - * board_button_initialize() must be called to initialize button resources. - * After that, board_buttons() may be called to collect the current state - * of all buttons or board_button_irq() may be called to register button - * interrupt handlers. - * - ****************************************************************************/ - -uint32_t board_button_initialize(void) -{ - /* Configure the single button as an input. NOTE that EXTI interrupts are - * also configured for the pin. - */ - - stm32_configgpio(GPIO_BTN_USER); - return NUM_BUTTONS; -} - -/**************************************************************************** - * Name: board_buttons - ****************************************************************************/ - -uint32_t board_buttons(void) -{ - /* Check that state of each USER button. A LOW value means that the key is - * pressed. - */ - - bool released = stm32_gpioread(GPIO_BTN_USER); - return !released; -} - -/**************************************************************************** - * Button support. - * - * Description: - * board_button_initialize() must be called to initialize button resources. - * After that, board_buttons() may be called to collect the current state - * of all buttons or board_button_irq() may be called to register button - * interrupt handlers. - * - * After board_button_initialize() has been called, board_buttons() may be - * called to collect the state of all buttons. board_buttons() returns an - * 32-bit bit set with each bit associated with a button. See the - * BUTTON_*_BIT definitions in board.h for the meaning of each bit. - * - * board_button_irq() may be called to register an interrupt handler that - * will be called when a button is depressed or released. The ID value is a - * button enumeration value that uniquely identifies a button resource. See - * the BUTTON_* definitions in board.h for the meaning of enumeration - * value. - * - ****************************************************************************/ - -#ifdef CONFIG_ARCH_IRQBUTTONS -int board_button_irq(int id, xcpt_t irqhandler, void *arg) -{ - int ret = -EINVAL; - - if (id == BUTTON_USER) - { - ret = stm32_gpiosetevent(GPIO_BTN_USER, true, true, true, - irqhandler, arg); - } - - return ret; -} -#endif -#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/stm32/nucleo-f410rb/src/stm32_userleds.c b/boards/arm/stm32/nucleo-f410rb/src/stm32_userleds.c deleted file mode 100644 index b007a34d32386..0000000000000 --- a/boards/arm/stm32/nucleo-f410rb/src/stm32_userleds.c +++ /dev/null @@ -1,197 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f410rb/src/stm32_userleds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include - -#include -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32.h" -#include "nucleo-f410rb.h" - -#ifndef CONFIG_ARCH_LEDS - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -/* LED Power Management */ - -#ifdef CONFIG_PM -static void led_pm_notify(struct pm_callback_s *cb, int domain, - enum pm_state_e pmstate); -static int led_pm_prepare(struct pm_callback_s *cb, int domain, - enum pm_state_e pmstate); -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -#ifdef CONFIG_PM -static struct pm_callback_s g_ledscb = -{ - .notify = led_pm_notify, - .prepare = led_pm_prepare, -}; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: led_pm_notify - * - * Description: - * Notify the driver of new power state. This callback is called after - * all drivers have had the opportunity to prepare for the new power state. - * - ****************************************************************************/ - -#ifdef CONFIG_PM -static void led_pm_notify(struct pm_callback_s *cb, int domain, - enum pm_state_e pmstate) -{ - switch (pmstate) - { - case PM_NORMAL: - { - /* Restore normal LEDs operation */ - } - break; - - case PM_IDLE: - { - /* Entering IDLE mode - Turn leds off */ - } - break; - - case PM_STANDBY: - { - /* Entering STANDBY mode - Logic for PM_STANDBY goes here */ - } - break; - - case PM_SLEEP: - { - /* Entering SLEEP mode - Logic for PM_SLEEP goes here */ - } - break; - - default: - { - /* Should not get here */ - } - break; - } -} -#endif - -/**************************************************************************** - * Name: led_pm_prepare - * - * Description: - * Request the driver to prepare for a new power state. This is a warning - * that the system is about to enter into a new power state. The driver - * should begin whatever operations that may be required to enter power - * state. The driver may abort the state change mode by returning a - * non-zero value from the callback function. - * - ****************************************************************************/ - -#ifdef CONFIG_PM -static int led_pm_prepare(struct pm_callback_s *cb, int domain, - enum pm_state_e pmstate) -{ - /* No preparation to change power modes is required by the LEDs driver. - * We always accept the state change by returning OK. - */ - - return OK; -} -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_userled_initialize - ****************************************************************************/ - -uint32_t board_userled_initialize(void) -{ - /* Configure LD2 GPIO for output */ - - stm32_configgpio(GPIO_LD2); - return BOARD_NLEDS; -} - -/**************************************************************************** - * Name: board_userled - ****************************************************************************/ - -void board_userled(int led, bool ledon) -{ - if (led == BOARD_LD2) - { - stm32_gpiowrite(GPIO_LD2, ledon); - } -} - -/**************************************************************************** - * Name: board_userled_all - ****************************************************************************/ - -void board_userled_all(uint32_t ledset) -{ - stm32_gpiowrite(GPIO_LD2, (ledset & BOARD_LD2_BIT) != 0); -} - -/**************************************************************************** - * Name: stm32_led_pminitialize - ****************************************************************************/ - -#ifdef CONFIG_PM -void stm32_led_pminitialize(void) -{ - /* Register to receive power management callbacks */ - - int ret = pm_register(&g_ledscb); - DEBUGASSERT(ret == OK); - UNUSED(ret); -} -#endif /* CONFIG_PM */ - -#endif /* !CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/nucleo-f411re/CMakeLists.txt b/boards/arm/stm32/nucleo-f411re/CMakeLists.txt deleted file mode 100644 index 53fe0025e449b..0000000000000 --- a/boards/arm/stm32/nucleo-f411re/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/nucleo-f411re/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32/nucleo-f411re/configs/mcp2515-extid/defconfig b/boards/arm/stm32/nucleo-f411re/configs/mcp2515-extid/defconfig deleted file mode 100644 index 78f646b76fe3c..0000000000000 --- a/boards/arm/stm32/nucleo-f411re/configs/mcp2515-extid/defconfig +++ /dev/null @@ -1,58 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -# CONFIG_NSH_DISABLE_IFCONFIG is not set -# CONFIG_NSH_DISABLE_PS is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="nucleo-f411re" -CONFIG_ARCH_BOARD_NUCLEO_F411RE=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F411RE=y -CONFIG_ARCH_INTERRUPTSTACK=2048 -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=8499 -CONFIG_BUILTIN=y -CONFIG_CAN=y -CONFIG_CANUTILS_CANLIB=y -CONFIG_CAN_EXTID=y -CONFIG_CAN_MCP2515=y -CONFIG_EXAMPLES_CAN=y -CONFIG_EXAMPLES_CAN_NMSGS=1 -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_MCP2515_PHASESEG1=3 -CONFIG_MCP2515_PROPSEG=1 -CONFIG_MCP2515_SPI_SCK_FREQUENCY=500000 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=131072 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=14 -CONFIG_START_MONTH=10 -CONFIG_START_YEAR=2014 -CONFIG_STM32_CRC=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_OTGFS=y -CONFIG_STM32_PWR=y -CONFIG_STM32_SPI1=y -CONFIG_STM32_USART1=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/nucleo-f411re/configs/nsh/defconfig b/boards/arm/stm32/nucleo-f411re/configs/nsh/defconfig deleted file mode 100644 index ecb6ba9c1d2f2..0000000000000 --- a/boards/arm/stm32/nucleo-f411re/configs/nsh/defconfig +++ /dev/null @@ -1,49 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -# CONFIG_NSH_DISABLE_IFCONFIG is not set -# CONFIG_NSH_DISABLE_PS is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="nucleo-f411re" -CONFIG_ARCH_BOARD_NUCLEO_F411RE=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F411RE=y -CONFIG_ARCH_INTERRUPTSTACK=2048 -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=8499 -CONFIG_BUILTIN=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=131072 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_SPI=y -CONFIG_START_DAY=14 -CONFIG_START_MONTH=10 -CONFIG_START_YEAR=2014 -CONFIG_STM32_CRC=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_OTGFS=y -CONFIG_STM32_PWR=y -CONFIG_STM32_USART2=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/nucleo-f411re/include/board.h b/boards/arm/stm32/nucleo-f411re/include/board.h deleted file mode 100644 index 9b16ece415431..0000000000000 --- a/boards/arm/stm32/nucleo-f411re/include/board.h +++ /dev/null @@ -1,377 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f411re/include/board.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __BOARDS_ARM_STM32_NUCLEO_F411RE_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32_NUCLEO_F411RE_INCLUDE_BOARD_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#ifndef __ASSEMBLY__ -# include -#endif - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Clocking *****************************************************************/ - -/* The NUCLEOF411RE supports both HSE and LSE crystals (X2 and X3). - * However, as shipped, the X2 and X3 crystals are not populated. - * Therefore the Nucleo-FF411RE will need to run off the 16MHz HSI clock. - * - * System Clock source : PLL (HSI) - * SYSCLK(Hz) : 104000000 Determined by PLL - * configuration - * HCLK(Hz) : 104000000 (STM32_RCC_CFGR_HPRE) - * AHB Prescaler : 1 (STM32_RCC_CFGR_HPRE) - * APB1 Prescaler : 2 (STM32_RCC_CFGR_PPRE1) - * APB2 Prescaler : 1 (STM32_RCC_CFGR_PPRE2) - * HSI Frequency(Hz) : 16000000 (nominal) - * PLLM : 8 (STM32_PLLCFG_PLLM) - * PLLN : 216 (STM32_PLLCFG_PLLN) - * PLLP : 4 (STM32_PLLCFG_PLLP) - * PLLQ : 9 (STM32_PLLCFG_PPQ) - * Flash Latency(WS) : 4 - * Prefetch Buffer : OFF - * Instruction cache : ON - * Data cache : ON - * Require 48MHz for USB OTG FS, : Enabled - * SDIO and RNG clock - */ - -/* HSI - 16 MHz RC factory-trimmed - * LSI - 32 KHz RC - * HSE - not installed - * LSE - not installed - */ - -#define STM32_HSI_FREQUENCY 16000000ul -#define STM32_LSI_FREQUENCY 32000 -#define STM32_BOARD_USEHSI 1 - -/* Main PLL Configuration. - * - * Formulae: - * - * VCO input frequency = PLL input clock frequency / PLLM, - * 2 <= PLLM <= 63 - * VCO output frequency = VCO input frequency × PLLN, - * 192 <= PLLN <= 432 - * PLL output clock frequency = VCO frequency / PLLP, - * PLLP = 2, 4, 6, or 8 - * USB OTG FS clock frequency = VCO frequency / PLLQ, - * 2 <= PLLQ <= 15 - * - - * There is no config for 100 MHz and 48 MHz for usb, - * so we would like to have SYSYCLK=104MHz and we must have - * the USB clock= 48MHz. - * - * PLLQ = 13 PLLP = 6 PLLN=390 PLLM=10 - * - * We will configure like this - * - * PLL source is HSI - * PLL_VCO = (STM32_HSI_FREQUENCY / PLLM) * PLLN - * = (16,000,000 / 10) * 390 - * = 624,000,000 - * SYSCLK = PLL_VCO / PLLP - * = 624,000,000 / 6 = 104,000,000 - * USB OTG FS and SDIO Clock - * = PLL_VCO / PLLQ - * = 624,000,000 / 13 = 48,000,000 - * - * REVISIT: Trimming of the HSI is not yet supported. - */ - -#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(10) -#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(390) -#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_6 -#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(13) - -#define STM32_SYSCLK_FREQUENCY 104000000ul - -/* AHB clock (HCLK) is SYSCLK (104MHz) */ - -#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ -#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY - -/* APB1 clock (PCLK1) is HCLK/2 (52MHz) */ - -#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd2 /* PCLK1 = HCLK / 2 */ -#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/2) - -/* Timers driven from APB1 will be twice PCLK1 */ - -/* REVISIT */ - -#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) - -/* APB2 clock (PCLK2) is HCLK (104MHz) */ - -#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ -#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/1) - -/* Timers driven from APB2 will be twice PCLK2 */ - -/* REVISIT */ - -#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM9_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB2_TIM10_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB2_TIM11_CLKIN (2*STM32_PCLK1_FREQUENCY) - -/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx - * otherwise frequency is 2xAPBx. - * Note: TIM1,8 are on APB2, others on APB1 - */ - -/* REVISIT */ - -#define BOARD_TIM1_FREQUENCY (2*STM32_PCLK2_FREQUENCY) -#define BOARD_TIM2_FREQUENCY (2*STM32_PCLK1_FREQUENCY) -#define BOARD_TIM3_FREQUENCY (2*STM32_PCLK1_FREQUENCY) -#define BOARD_TIM4_FREQUENCY (2*STM32_PCLK1_FREQUENCY) -#define BOARD_TIM5_FREQUENCY (2*STM32_PCLK1_FREQUENCY) -#define BOARD_TIM6_FREQUENCY (2*STM32_PCLK1_FREQUENCY) -#define BOARD_TIM7_FREQUENCY (2*STM32_PCLK1_FREQUENCY) -#define BOARD_TIM8_FREQUENCY (2*STM32_PCLK2_FREQUENCY) - -/* SDIO dividers. Note that slower clocking is required when DMA is disabled - * in order to avoid RX overrun/TX underrun errors due to delayed responses - * to service FIFOs in interrupt driven mode. These values have not been - * tuned!!! - * - * HCLK=72MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(178+2)=400 KHz - */ - -/* REVISIT */ - -#define SDIO_INIT_CLKDIV (178 << SDIO_CLKCR_CLKDIV_SHIFT) - -/* DMA ON: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(2+2)=18 MHz - * DMA OFF: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(3+2)=14.4 MHz - */ - -/* REVISIT */ - -#ifdef CONFIG_SDIO_DMA -# define SDIO_MMCXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT) -#else -# define SDIO_MMCXFR_CLKDIV (3 << SDIO_CLKCR_CLKDIV_SHIFT) -#endif - -/* DMA ON: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(1+2)=24 MHz - * DMA OFF: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(3+2)=14.4 MHz - */ - -/* REVISIT */ - -#ifdef CONFIG_SDIO_DMA -# define SDIO_SDXFR_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT) -#else -# define SDIO_SDXFR_CLKDIV (3 << SDIO_CLKCR_CLKDIV_SHIFT) -#endif - -/* DMA Channel/Stream Selections ********************************************/ - -/* Stream selections are arbitrary for now but might become important in - * the future is we set aside more DMA channels/streams. - * - * SDIO DMA - *   DMAMAP_SDIO_1 = Channel 4, Stream 3 <- may later be used by SPI DMA - *   DMAMAP_SDIO_2 = Channel 4, Stream 6 - */ - -#define DMAMAP_SDIO DMAMAP_SDIO_1 - -/* Need to VERIFY fwb */ - -#define DMACHAN_SPI1_RX DMAMAP_SPI1_RX_1 -#define DMACHAN_SPI1_TX DMAMAP_SPI1_TX_1 -#define DMACHAN_SPI2_RX DMAMAP_SPI2_RX -#define DMACHAN_SPI2_TX DMAMAP_SPI2_TX - -/* Alternate function pin selections ****************************************/ - -/* USART1: - * RXD: PA10 CN9 pin 3, CN10 pin 33 - * PB7 CN7 pin 21 - * TXD: PA9 CN5 pin 1, CN10 pin 21 - * PB6 CN5 pin 3, CN10 pin 17 - */ - -#if 1 -# define GPIO_USART1_RX (GPIO_USART1_RX_1|GPIO_SPEED_100MHz) /* PA10 */ -# define GPIO_USART1_TX (GPIO_USART1_TX_1|GPIO_SPEED_100MHz) /* PA9 */ -#else -# define GPIO_USART1_RX (GPIO_USART1_RX_2|GPIO_SPEED_100MHz) /* PB7 */ -# define GPIO_USART1_TX (GPIO_USART1_TX_2|GPIO_SPEED_100MHz) /* PB6 */ -#endif - -/* USART2: - * RXD: PA3 CN9 pin 1 (See SB13, 14, 62, 63). CN10 pin 37 - * PD6 - * TXD: PA2 CN9 pin 2(See SB13, 14, 62, 63). CN10 pin 35 - * PD5 - */ - -#define GPIO_USART2_RX (GPIO_USART2_RX_1|GPIO_SPEED_100MHz) /* PA3 */ -#define GPIO_USART2_TX (GPIO_USART2_TX_1|GPIO_SPEED_100MHz) /* PA2 */ -#define GPIO_USART2_RTS GPIO_USART2_RTS_2 -#define GPIO_USART2_CTS GPIO_USART2_CTS_2 - -/* USART6: - * RXD: PC7 CN5 pin2, CN10 pin 19 - * PA12 CN10, pin 12 - * TXD: PC6 CN10, pin 4 - * PA11 CN10, pin 14 - */ - -#define GPIO_USART6_RX (GPIO_USART6_RX_1|GPIO_SPEED_100MHz) /* PC7 */ -#define GPIO_USART6_TX (GPIO_USART6_TX_1|GPIO_SPEED_100MHz) /* PC6 */ - -/* UART RX DMA configurations */ - -#define DMAMAP_USART1_RX DMAMAP_USART1_RX_2 -#define DMAMAP_USART6_RX DMAMAP_USART6_RX_2 - -/* I2C - * - * The optional _GPIO configurations allow the I2C driver to manually - * reset the bus to clear stuck slaves. They match the pin configuration, - * but are normally-high GPIOs. - */ - -#define GPIO_I2C1_SCL (GPIO_I2C1_SCL_2|GPIO_SPEED_50MHz) -#define GPIO_I2C1_SDA (GPIO_I2C1_SDA_2|GPIO_SPEED_50MHz) -#define GPIO_I2C1_SCL_GPIO \ - (GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTB|GPIO_PIN8) -#define GPIO_I2C1_SDA_GPIO \ - (GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTB|GPIO_PIN9) - -#define GPIO_I2C2_SCL (GPIO_I2C2_SCL_1|GPIO_SPEED_50MHz) -#define GPIO_I2C2_SDA (GPIO_I2C2_SDA_1|GPIO_SPEED_50MHz) -#define GPIO_I2C2_SCL_GPIO \ - (GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTB|GPIO_PIN10) -#define GPIO_I2C2_SDA_GPIO \ - (GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTB|GPIO_PIN11) - -/* SPI - * - * There are sensors on SPI1, and SPI2 is connected to the FRAM. - */ - -#define GPIO_SPI1_MISO (GPIO_SPI1_MISO_1|GPIO_SPEED_50MHz) -#define GPIO_SPI1_MOSI (GPIO_SPI1_MOSI_1|GPIO_SPEED_50MHz) -#define GPIO_SPI1_SCK (GPIO_SPI1_SCK_1|GPIO_SPEED_50MHz) - -#define GPIO_SPI2_MISO (GPIO_SPI2_MISO_1|GPIO_SPEED_50MHz) -#define GPIO_SPI2_MOSI (GPIO_SPI2_MOSI_1|GPIO_SPEED_50MHz) -#define GPIO_SPI2_SCK (GPIO_SPI2_SCK_2|GPIO_SPEED_50MHz) - -/* LEDs - * - * The Nucleo F411RE board provide a single user LED, LD2. LD2 - * is the green LED connected to Arduino signal D13 corresponding to MCU I/O - * PA5 (pin 21) or PB13 (pin 34) depending on the STM32 target. - * - * - When the I/O is HIGH value, the LED is on. - * - When the I/O is LOW, the LED is off. - */ - -/* LED index values for use with board_userled() */ - -#define BOARD_LD2 0 -#define BOARD_NLEDS 1 - -/* LED bits for use with board_userled_all() */ - -#define BOARD_LD2_BIT (1 << BOARD_LD2) - -/* These LEDs are not used by the board port unless CONFIG_ARCH_LEDS is - * defined. In that case, the usage by the board port is defined in - * include/board.h and src/sam_leds.c. The LEDs are used to encode OS-related - * events as follows when the red LED (PE24) is available: - * - * SYMBOL Meaning LD2 - * ------------------- ----------------------- ----------- - * LED_STARTED NuttX has been started OFF - * LED_HEAPALLOCATE Heap has been allocated OFF - * LED_IRQSENABLED Interrupts enabled OFF - * LED_STACKCREATED Idle stack created ON - * LED_INIRQ In an interrupt No change - * LED_SIGNAL In a signal handler No change - * LED_ASSERTION An assertion failed No change - * LED_PANIC The system has crashed Blinking - * LED_IDLE MCU is in sleep mode Not used - * - * Thus if LD2, NuttX has successfully booted and is, apparently, running - * normally. If LD2 is flashing at approximately 2Hz, then a fatal error - * has been detected and the system has halted. - */ - -#define LED_STARTED 0 -#define LED_HEAPALLOCATE 0 -#define LED_IRQSENABLED 0 -#define LED_STACKCREATED 1 -#define LED_INIRQ 2 -#define LED_SIGNAL 2 -#define LED_ASSERTION 2 -#define LED_PANIC 1 - -/* Buttons - * - * B1 USER: - * the user button is connected to the I/O PC13 (pin 2) of the STM32 - * microcontroller. - */ - -#define BUTTON_USER 0 -#define NUM_BUTTONS 1 - -#define BUTTON_USER_BIT (1 << BUTTON_USER) - -#define GPIO_TIM2_CH1IN (GPIO_TIM2_CH1IN_1 | GPIO_PULLUP | GPIO_SPEED_50MHz) -#define GPIO_TIM2_CH2IN (GPIO_TIM2_CH2IN_1 | GPIO_PULLUP | GPIO_SPEED_50MHz) - -/* USB OTG FS */ - -#define GPIO_OTGFS_DM (GPIO_OTGFS_DM_0|GPIO_SPEED_100MHz) -#define GPIO_OTGFS_DP (GPIO_OTGFS_DP_0|GPIO_SPEED_100MHz) -#define GPIO_OTGFS_ID (GPIO_OTGFS_ID_0|GPIO_SPEED_100MHz) -#define GPIO_OTGFS_SOF (GPIO_OTGFS_SOF_0|GPIO_SPEED_100MHz) - -#endif /* __BOARDS_ARM_STM32_NUCLEO_F411RE_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32/nucleo-f411re/scripts/Make.defs b/boards/arm/stm32/nucleo-f411re/scripts/Make.defs deleted file mode 100644 index 88f77e2be62d9..0000000000000 --- a/boards/arm/stm32/nucleo-f411re/scripts/Make.defs +++ /dev/null @@ -1,43 +0,0 @@ -############################################################################ -# boards/arm/stm32/nucleo-f411re/scripts/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/.config -include $(TOPDIR)/tools/Config.mk -include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs - -LDSCRIPT = flash.ld - -ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) - -ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 - -CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) -CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) -CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -AFLAGS := $(CFLAGS) -D__ASSEMBLY__ - -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections -LDNXFLATFLAGS = -e main -s 2048 - diff --git a/boards/arm/stm32/nucleo-f411re/scripts/flash.ld b/boards/arm/stm32/nucleo-f411re/scripts/flash.ld deleted file mode 100644 index 09718dfc8e320..0000000000000 --- a/boards/arm/stm32/nucleo-f411re/scripts/flash.ld +++ /dev/null @@ -1,121 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f411re/scripts/flash.ld - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* The STM32F411RE has 512Kb of FLASH beginning at address 0x0800:0000 and - * 128Kb of SRAM beginning at address 0x2000:0000. When booting from FLASH, - * FLASH memory is aliased to address 0x0000:0000 where the code expects to - * begin execution by jumping to the entry point in the 0x0800:0000 address - * range. - */ - -MEMORY -{ - flash (rx) : ORIGIN = 0x08000000, LENGTH = 512K - sram (rwx) : ORIGIN = 0x20000000, LENGTH = 128K -} - -OUTPUT_ARCH(arm) -EXTERN(_vectors) -ENTRY(_stext) -SECTIONS -{ - .text : { - _stext = ABSOLUTE(.); - *(.vectors) - *(.text .text.*) - *(.fixup) - *(.gnu.warning) - *(.rodata .rodata.*) - *(.gnu.linkonce.t.*) - *(.glue_7) - *(.glue_7t) - *(.got) - *(.gcc_except_table) - *(.gnu.linkonce.r.*) - _etext = ABSOLUTE(.); - } > flash - - .init_section : { - _sinit = ABSOLUTE(.); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) - KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) - _einit = ABSOLUTE(.); - } > flash - - .tdata : { - _stdata = ABSOLUTE(.); - *(.tdata .tdata.* .gnu.linkonce.td.*); - _etdata = ABSOLUTE(.); - } > flash - - .tbss : { - _stbss = ABSOLUTE(.); - *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); - _etbss = ABSOLUTE(.); - } > flash - - .ARM.extab : { - *(.ARM.extab*) - } > flash - - __exidx_start = ABSOLUTE(.); - .ARM.exidx : { - *(.ARM.exidx*) - } > flash - __exidx_end = ABSOLUTE(.); - - _eronly = ABSOLUTE(.); - - /* The STM32F103VCT6 has 48Kb of SRAM beginning at the following address */ - - .data : { - _sdata = ABSOLUTE(.); - *(.data .data.*) - *(.gnu.linkonce.d.*) - CONSTRUCTORS - . = ALIGN(4); - _edata = ABSOLUTE(.); - } > sram AT > flash - - .bss : { - _sbss = ABSOLUTE(.); - *(.bss .bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - . = ALIGN(8); - _ebss = ABSOLUTE(.); - } > sram - - /* Stabs debugging sections. */ - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_info 0 : { *(.debug_info) } - .debug_line 0 : { *(.debug_line) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_aranges 0 : { *(.debug_aranges) } -} diff --git a/boards/arm/stm32/nucleo-f411re/src/CMakeLists.txt b/boards/arm/stm32/nucleo-f411re/src/CMakeLists.txt deleted file mode 100644 index 9339106e5ded2..0000000000000 --- a/boards/arm/stm32/nucleo-f411re/src/CMakeLists.txt +++ /dev/null @@ -1,54 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/nucleo-f411re/src/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -set(SRCS stm32_boot.c stm32_spi.c stm32_bringup.c) - -if(CONFIG_VIDEO_FB) - if(CONFIG_LCD_SSD1306) - list(APPEND SRCS stm32_lcd_ssd1306.c) - endif() -endif() - -if(CONFIG_ARCH_LEDS) - list(APPEND SRCS stm32_autoleds.c) -else() - list(APPEND SRCS stm32_userleds.c) -endif() - -if(CONFIG_ARCH_BUTTONS) - list(APPEND SRCS stm32_buttons.c) -endif() - -if(CONFIG_ADC) - list(APPEND SRCS stm32_adc.c) - if(CONFIG_INPUT_AJOYSTICK) - list(APPEND SRCS stm32_ajoystick.c) - endif() -endif() - -if(CONFIG_CAN_MCP2515) - list(APPEND SRCS stm32_mcp2515.c) -endif() - -target_sources(board PRIVATE ${SRCS}) - -set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/flash.ld") diff --git a/boards/arm/stm32/nucleo-f411re/src/Make.defs b/boards/arm/stm32/nucleo-f411re/src/Make.defs deleted file mode 100644 index 0bab56576f560..0000000000000 --- a/boards/arm/stm32/nucleo-f411re/src/Make.defs +++ /dev/null @@ -1,56 +0,0 @@ -############################################################################ -# boards/arm/stm32/nucleo-f411re/src/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/Make.defs - -CSRCS = stm32_boot.c stm32_spi.c stm32_bringup.c - -ifeq ($(CONFIG_VIDEO_FB),y) -ifeq ($(CONFIG_LCD_SSD1306),y) - CSRCS += stm32_lcd_ssd1306.c -endif -endif - -ifeq ($(CONFIG_ARCH_LEDS),y) -CSRCS += stm32_autoleds.c -else -CSRCS += stm32_userleds.c -endif - -ifeq ($(CONFIG_ARCH_BUTTONS),y) -CSRCS += stm32_buttons.c -endif - -ifeq ($(CONFIG_ADC),y) -CSRCS += stm32_adc.c -ifeq ($(CONFIG_INPUT_AJOYSTICK),y) -CSRCS += stm32_ajoystick.c -endif -endif - -ifeq ($(CONFIG_CAN_MCP2515),y) - CSRCS += stm32_mcp2515.c -endif - -DEPPATH += --dep-path board -VPATH += :board -CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/nucleo-f411re/src/stm32_adc.c b/boards/arm/stm32/nucleo-f411re/src/stm32_adc.c deleted file mode 100644 index cde6cfc40ae1c..0000000000000 --- a/boards/arm/stm32/nucleo-f411re/src/stm32_adc.c +++ /dev/null @@ -1,142 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f411re/src/stm32_adc.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32_adc.h" -#include "nucleo-f411re.h" - -#include - -#ifdef CONFIG_STM32_ADC1 - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* The number of ADC channels in the conversion list */ - -#ifdef CONFIG_ADC_DMA -# define ADC1_NCHANNELS 2 -#else -# define ADC1_NCHANNELS 1 -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* Identifying number of each ADC channel. */ - -#ifdef CONFIG_ADC_DMA -/* Configure ADC inputs on ADC_IN0 and ADC_IN1 */ - -static const uint8_t g_adc1_chanlist[ADC1_NCHANNELS] = -{ - 0, 1 -}; - -/* Configurations of pins used byte each ADC channels */ - -static const uint32_t g_adc1_pinlist[ADC1_NCHANNELS] = -{ - GPIO_ADC1_IN0, GPIO_ADC1_IN0 -}; - -#else -/* Without DMA, only a single channel can be supported */ - -/* Configura ADC input on ADC_IN0 */ - -static const uint8_t g_adc1_chanlist[ADC1_NCHANNELS] = -{ - 0 -}; - -/* Configurations of pins used byte each ADC channels */ - -static const uint32_t g_adc1_pinlist[ADC1_NCHANNELS] = -{ - GPIO_ADC1_IN0 -}; - -#endif /* CONFIG_ADC_DMA */ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_adc_setup - * - * Description: - * Initialize ADC and register the ADC driver. - * - ****************************************************************************/ - -int stm32_adc_setup(void) -{ - struct adc_dev_s *adc; - int ret; - int i; - - /* Configure the pins as analog inputs for the selected channels */ - - for (i = 0; i < ADC1_NCHANNELS; i++) - { - stm32_configgpio(g_adc1_pinlist[i]); - } - - /* Call stm32_adcinitialize() to get an instance of the ADC interface */ - - adc = stm32_adcinitialize(1, g_adc1_chanlist, ADC1_NCHANNELS); - if (adc == NULL) - { - aerr("ERROR: Failed to get ADC interface\n"); - return -ENODEV; - } - - /* Register the ADC driver at "/dev/adc0" */ - - ret = adc_register("/dev/adc0", adc); - if (ret < 0) - { - aerr("ERROR: adc_register failed: %d\n", ret); - return ret; - } - - return OK; -} - -#endif /* CONFIG_STM32_ADC1 */ diff --git a/boards/arm/stm32/nucleo-f411re/src/stm32_ajoystick.c b/boards/arm/stm32/nucleo-f411re/src/stm32_ajoystick.c deleted file mode 100644 index 69dcfc850d040..0000000000000 --- a/boards/arm/stm32/nucleo-f411re/src/stm32_ajoystick.c +++ /dev/null @@ -1,490 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f411re/src/stm32_ajoystick.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include - -#include -#include -#include -#include -#include - -#include "stm32_gpio.h" -#include "stm32_adc.h" -#include "hardware/stm32_adc.h" -#include "nucleo-f411re.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Check for pre-requisites and pin conflicts */ - -#ifdef CONFIG_INPUT_AJOYSTICK -# if !defined(CONFIG_ADC) -# error CONFIG_ADC is required for the Itead joystick -# undef CONFIG_INPUT_AJOYSTICK -# elif !defined(CONFIG_STM32_ADC1) -# error CONFIG_STM32_ADC1 is required for Itead joystick -# undef CONFIG_INPUT_AJOYSTICK -# endif -#endif /* CONFIG_INPUT_AJOYSTICK */ - -#ifdef CONFIG_INPUT_AJOYSTICK - -/* A no-ADC, buttons only version can be built for testing */ - -#undef NO_JOYSTICK_ADC - -/* Maximum number of ADC channels */ - -#define MAX_ADC_CHANNELS 8 - -/* Dual channel ADC support requires DMA */ - -#ifdef CONFIG_ADC_DMA -# define NJOYSTICK_CHANNELS 2 -#else -# define NJOYSTICK_CHANNELS 1 -#endif - -#ifdef CONFIG_NUCLEO_F411RE_AJOY_MINBUTTONS -/* Number of Joystick buttons */ - -# define AJOY_NGPIOS 3 - -/* Bitset of supported Joystick buttons */ - -# define AJOY_SUPPORTED (AJOY_BUTTON_1_BIT | AJOY_BUTTON_2_BIT | \ - AJOY_BUTTON_3_BIT) -#else -/* Number of Joystick buttons */ - -# define AJOY_NGPIOS 7 - -/* Bitset of supported Joystick buttons */ - -# define AJOY_SUPPORTED (AJOY_BUTTON_1_BIT | AJOY_BUTTON_2_BIT | \ - AJOY_BUTTON_3_BIT | AJOY_BUTTON_4_BIT | \ - AJOY_BUTTON_5_BIT | AJOY_BUTTON_6_BIT | \ - AJOY_BUTTON_7_BIT ) -#endif - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -static ajoy_buttonset_t -ajoy_supported(const struct ajoy_lowerhalf_s *lower); -static int ajoy_sample(const struct ajoy_lowerhalf_s *lower, - struct ajoy_sample_s *sample); -static ajoy_buttonset_t -ajoy_buttons(const struct ajoy_lowerhalf_s *lower); -static void ajoy_enable(const struct ajoy_lowerhalf_s *lower, - ajoy_buttonset_t press, ajoy_buttonset_t release, - ajoy_handler_t handler, void *arg); - -static void ajoy_disable(void); -static int ajoy_interrupt(int irq, void *context, void *arg); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* Pin configuration for each Itead joystick button. Index using AJOY_* - * button definitions in include/nuttx/input/ajoystick.h. - */ - -#ifdef CONFIG_NUCLEO_F411RE_AJOY_MINBUTTONS -static const uint32_t g_joygpio[AJOY_NGPIOS] = -{ - GPIO_BUTTON_1, GPIO_BUTTON_2, GPIO_BUTTON_3 -}; -#else -static const uint32_t g_joygpio[AJOY_NGPIOS] = -{ - GPIO_BUTTON_1, GPIO_BUTTON_2, GPIO_BUTTON_3, GPIO_BUTTON_4, - GPIO_BUTTON_5, GPIO_BUTTON_6, GPIO_BUTTON_7 -}; -#endif - -/* This is the button joystick lower half driver interface */ - -static const struct ajoy_lowerhalf_s g_ajoylower = -{ - .al_supported = ajoy_supported, - .al_sample = ajoy_sample, - .al_buttons = ajoy_buttons, - .al_enable = ajoy_enable, -}; - -#ifndef NO_JOYSTICK_ADC -/* Thread-independent file structure for the open ADC driver */ - -static struct file g_adcfile; -#endif - -/* Current interrupt handler and argument */ - -static ajoy_handler_t g_ajoyhandler; -static void *g_ajoyarg; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: ajoy_supported - * - * Description: - * Return the set of buttons supported on the button joystick device - * - ****************************************************************************/ - -static ajoy_buttonset_t -ajoy_supported(const struct ajoy_lowerhalf_s *lower) -{ - iinfo("Supported: %02x\n", AJOY_SUPPORTED); - return (ajoy_buttonset_t)AJOY_SUPPORTED; -} - -/**************************************************************************** - * Name: ajoy_sample - * - * Description: - * Return the current state of all button joystick buttons - * - ****************************************************************************/ - -static int ajoy_sample(const struct ajoy_lowerhalf_s *lower, - struct ajoy_sample_s *sample) -{ -#ifndef NO_JOYSTICK_ADC - struct adc_msg_s adcmsg[MAX_ADC_CHANNELS]; - struct adc_msg_s *ptr; - ssize_t nread; - ssize_t offset; - int have; - int i; - - /* Read all of the available samples (handling the case where additional - * channels are enabled). - */ - - nread = file_read(&g_adcfile, adcmsg, - MAX_ADC_CHANNELS * sizeof(struct adc_msg_s)); - if (nread < 0) - { - if (nread != -EINTR) - { - ierr("ERROR: read failed: %d\n", (int)nread); - } - - return nread; - } - else if (nread < NJOYSTICK_CHANNELS * sizeof(struct adc_msg_s)) - { - ierr("ERROR: read too small: %ld\n", (long)nread); - return -EIO; - } - - /* Sample and the raw analog inputs */ - -#ifdef CONFIG_ADC_DMA - have = 0; - -#else - /* If DMA is not supported, then we will have only a single ADC channel */ - - have = 2; - sample->as_y = 0; -#endif - - for (i = 0, offset = 0; - i < MAX_ADC_CHANNELS && offset < nread && have != 3; - i++, offset += sizeof(struct adc_msg_s)) - { - ptr = &adcmsg[i]; - - /* Is this one of the channels that we need? */ - - if ((have & 1) == 0 && ptr->am_channel == 0) - { - int32_t tmp = ptr->am_data; - sample->as_x = (int16_t)tmp; - have |= 1; - - iinfo("X sample: %ld -> %d\n", (long)tmp, (int)sample->as_x); - } - -#ifdef CONFIG_ADC_DMA - if ((have & 2) == 0 && ptr->am_channel == 1) - { - int32_t tmp = ptr->am_data; - sample->as_y = (int16_t)tmp; - have |= 2; - - iinfo("Y sample: %ld -> %d\n", (long)tmp, (int)sample->as_y); - } -#endif - } - - if (have != 3) - { - ierr("ERROR: Could not find joystick channels\n"); - return -EIO; - } - -#else - /* ADC support is disabled */ - - sample->as_x = 0; - sample->as_y = 0; -#endif - - /* Sample the discrete button inputs */ - - sample->as_buttons = ajoy_buttons(lower); - iinfo("Returning: %02x\n", sample->as_buttons); - return OK; -} - -/**************************************************************************** - * Name: ajoy_buttons - * - * Description: - * Return the current state of button data (only) - * - ****************************************************************************/ - -static ajoy_buttonset_t -ajoy_buttons(const struct ajoy_lowerhalf_s *lower) -{ - ajoy_buttonset_t ret = 0; - int i; - - /* Read each joystick GPIO value */ - - for (i = 0; i < AJOY_NGPIOS; i++) - { - /* Button outputs are pulled high. So a sensed low level means that the - * button is pressed. - */ - - if (!stm32_gpioread(g_joygpio[i])) - { - ret |= (1 << i); - } - } - - iinfo("Returning: %02x\n", ret); - return ret; -} - -/**************************************************************************** - * Name: ajoy_enable - * - * Description: - * Enable interrupts on the selected set of joystick buttons. And empty - * set will disable all interrupts. - * - ****************************************************************************/ - -static void ajoy_enable(const struct ajoy_lowerhalf_s *lower, - ajoy_buttonset_t press, ajoy_buttonset_t release, - ajoy_handler_t handler, void *arg) -{ - irqstate_t flags; - ajoy_buttonset_t either = press | release; - ajoy_buttonset_t bit; - bool rising; - bool falling; - int i; - - /* Start with all interrupts disabled */ - - flags = enter_critical_section(); - ajoy_disable(); - - iinfo("press: %02x release: %02x handler: %p arg: %p\n", - press, release, handler, arg); - - /* If no events are indicated or if no handler is provided, then this - * must really be a request to disable interrupts. - */ - - if (either && handler) - { - /* Save the new the handler and argument */ - - g_ajoyhandler = handler; - g_ajoyarg = arg; - - /* Check each GPIO. */ - - for (i = 0; i < AJOY_NGPIOS; i++) - { - /* Enable interrupts on each pin that has either a press or - * release event associated with it. - */ - - bit = (1 << i); - if ((either & bit) != 0) - { - /* Active low so a press corresponds to a falling edge and - * a release corresponds to a rising edge. - */ - - falling = ((press & bit) != 0); - rising = ((release & bit) != 0); - - iinfo("GPIO %d: rising: %d falling: %d\n", - i, rising, falling); - - stm32_gpiosetevent(g_joygpio[i], rising, falling, - true, ajoy_interrupt, NULL); - } - } - } - - leave_critical_section(flags); -} - -/**************************************************************************** - * Name: ajoy_disable - * - * Description: - * Disable all joystick interrupts - * - ****************************************************************************/ - -static void ajoy_disable(void) -{ - irqstate_t flags; - int i; - - /* Disable each joystick interrupt */ - - flags = enter_critical_section(); - for (i = 0; i < AJOY_NGPIOS; i++) - { - stm32_gpiosetevent(g_joygpio[i], false, false, false, NULL, NULL); - } - - leave_critical_section(flags); - - /* Nullify the handler and argument */ - - g_ajoyhandler = NULL; - g_ajoyarg = NULL; -} - -/**************************************************************************** - * Name: ajoy_interrupt - * - * Description: - * Discrete joystick interrupt handler - * - ****************************************************************************/ - -static int ajoy_interrupt(int irq, void *context, void *arg) -{ - DEBUGASSERT(g_ajoyhandler); - - if (g_ajoyhandler) - { - g_ajoyhandler(&g_ajoylower, g_ajoyarg); - } - - return OK; -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_ajoy_initialize - * - * Description: - * Initialize and register the button joystick driver - * - ****************************************************************************/ - -int board_ajoy_initialize(void) -{ - int ret; - int i; - -#ifndef NO_JOYSTICK_ADC - iinfo("Initialize ADC driver: /dev/adc0\n"); - - /* NOTE: The ADC driver was initialized earlier in the bring-up sequence. */ - - /* Open the ADC driver for reading. */ - - ret = file_open(&g_adcfile, "/dev/adc0", O_RDONLY); - if (ret < 0) - { - ierr("ERROR: Failed to open /dev/adc0: %d\n", ret); - return ret; - } -#endif - - /* Configure the GPIO pins as interrupting inputs. NOTE: This is - * unnecessary for interrupting pins since it will also be done by - * stm32_gpiosetevent(). - */ - - for (i = 0; i < AJOY_NGPIOS; i++) - { - /* Configure the PIO as an input */ - - stm32_configgpio(g_joygpio[i]); - } - - /* Register the joystick device as /dev/ajoy0 */ - - iinfo("Initialize joystick driver: /dev/ajoy0\n"); - - ret = ajoy_register("/dev/ajoy0", &g_ajoylower); - if (ret < 0) - { - ierr("ERROR: ajoy_register failed: %d\n", ret); -#ifndef NO_JOYSTICK_ADC - file_close(&g_adcfile); -#endif - } - - return ret; -} - -#endif /* CONFIG_INPUT_AJOYSTICK */ diff --git a/boards/arm/stm32/nucleo-f411re/src/stm32_autoleds.c b/boards/arm/stm32/nucleo-f411re/src/stm32_autoleds.c deleted file mode 100644 index 24b8a3db27ed7..0000000000000 --- a/boards/arm/stm32/nucleo-f411re/src/stm32_autoleds.c +++ /dev/null @@ -1,83 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f411re/src/stm32_autoleds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32.h" -#include "nucleo-f411re.h" - -#include - -#ifdef CONFIG_ARCH_LEDS - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_autoled_initialize - ****************************************************************************/ - -void board_autoled_initialize(void) -{ - /* Configure LD2 GPIO for output */ - - stm32_configgpio(GPIO_LD2); -} - -/**************************************************************************** - * Name: board_autoled_on - ****************************************************************************/ - -void board_autoled_on(int led) -{ - if (led == 1) - { - stm32_gpiowrite(GPIO_LD2, true); - } -} - -/**************************************************************************** - * Name: board_autoled_off - ****************************************************************************/ - -void board_autoled_off(int led) -{ - if (led == 1) - { - stm32_gpiowrite(GPIO_LD2, false); - } -} - -#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/nucleo-f411re/src/stm32_boot.c b/boards/arm/stm32/nucleo-f411re/src/stm32_boot.c deleted file mode 100644 index 88b543398badf..0000000000000 --- a/boards/arm/stm32/nucleo-f411re/src/stm32_boot.c +++ /dev/null @@ -1,101 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f411re/src/stm32_boot.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include -#include - -#include - -#include "arm_internal.h" -#include "nucleo-f411re.h" - -#include - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_boardinitialize - * - * Description: - * All STM32 architectures must provide the following entry point. - * This entry point is called early in the initialization -- after all - * memory has been configured and mapped but before any devices have been - * initialized. - * - ****************************************************************************/ - -void stm32_boardinitialize(void) -{ - /* Configure on-board LEDs if LED support has been selected. */ - -#ifdef CONFIG_ARCH_LEDS - board_autoled_initialize(); -#endif - - /* Configure SPI chip selects if 1) SP2 is not disabled, and 2) the weak - * function stm32_spidev_initialize() has been brought into the link. - */ - -#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || defined(CONFIG_STM32_SPI3) - stm32_spidev_initialize(); -#endif - - /* Initialize USB is 1) USBDEV is selected, 2) the USB controller is not - * disabled, and 3) the weak function stm32_usbinitialize() has been - * brought into the build. - */ - -#if defined(CONFIG_USBDEV) && defined(CONFIG_STM32_USB) - stm32_usbinitialize(); -#endif -} - -/**************************************************************************** - * Name: board_late_initialize - * - * Description: - * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional - * initialization call will be performed in the boot-up sequence to a - * function called board_late_initialize(). board_late_initialize() will - * be called immediately after up_initialize() is called and just before - * the initial application is started. This additional initialization - * phase may be used, for example, to initialize board-specific device - * drivers. - * - ****************************************************************************/ - -#ifdef CONFIG_BOARD_LATE_INITIALIZE -void board_late_initialize(void) -{ - stm32_bringup(); -} -#endif diff --git a/boards/arm/stm32/nucleo-f411re/src/stm32_bringup.c b/boards/arm/stm32/nucleo-f411re/src/stm32_bringup.c deleted file mode 100644 index 04836ee845a0e..0000000000000 --- a/boards/arm/stm32/nucleo-f411re/src/stm32_bringup.c +++ /dev/null @@ -1,212 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f411re/src/stm32_bringup.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include -#include - -#include -#include - -#include - -#ifdef CONFIG_USERLED -# include -#endif - -#ifdef CONFIG_INPUT_BUTTONS -# include -#endif - -#include "nucleo-f411re.h" - -#include - -#ifdef CONFIG_SENSORS_QENCODER -#include "board_qencoder.h" -#endif - -#undef HAVE_LEDS -#if !defined(CONFIG_ARCH_LEDS) && defined(CONFIG_USERLED_LOWER) -# define HAVE_LEDS 1 -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_bringup - * - * Description: - * Perform architecture-specific initialization - * - * CONFIG_BOARD_LATE_INITIALIZE=y : - * Called from board_late_initialize(). - * - ****************************************************************************/ - -int stm32_bringup(void) -{ - int ret = OK; - -#ifdef HAVE_LEDS - /* Register the LED driver */ - - ret = userled_lower_initialize("/dev/userleds"); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: userled_lower_initialize() failed: %d\n", ret); - return ret; - } -#endif - -#ifdef CONFIG_INPUT_BUTTONS - /* Register the BUTTON driver */ - - ret = btn_lower_initialize("/dev/buttons"); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: btn_lower_initialize() failed: %d\n", ret); - } -#endif - - /* Configure SPI-based devices */ - -#ifdef CONFIG_STM32_SPI1 - /* Get the SPI port */ - - struct spi_dev_s *spi; - - spi = stm32_spibus_initialize(1); - if (!spi) - { - syslog(LOG_ERR, "ERROR: Failed to initialize SPI port 1\n"); - return -ENODEV; - } - -#if defined(CONFIG_LCD_SSD1306_SPI) && !defined(CONFIG_VIDEO_FB) - board_lcd_initialize(); -#endif - -#ifdef CONFIG_VIDEO_FB - ret = fb_register(0, 0); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: fb_register() failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_CAN_MCP2515 -#ifdef CONFIG_STM32_SPI1 - stm32_configgpio(GPIO_MCP2515_CS); /* MEMS chip select */ -#endif - - /* Configure and initialize the MCP2515 CAN device */ - - ret = stm32_mcp2515initialize("/dev/can0"); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_mcp2515initialize() failed: %d\n", ret); - } -#endif -#endif - -#ifdef HAVE_MMCSD - /* First, get an instance of the SDIO interface */ - - g_sdio = sdio_initialize(CONFIG_NSH_MMCSDSLOTNO); - if (!g_sdio) - { - syslog(LOG_ERR, "ERROR: Failed to initialize SDIO slot %d\n", - CONFIG_NSH_MMCSDSLOTNO); - return -ENODEV; - } - - /* Now bind the SDIO interface to the MMC/SD driver */ - - ret = mmcsd_slotinitialize(CONFIG_NSH_MMCSDMINOR, g_sdio); - if (ret != OK) - { - syslog(LOG_ERR, - "ERROR: Failed to bind SDIO to the MMC/SD driver: %d\n", - ret); - return ret; - } - - /* Then let's guess and say that there is a card in the slot. There is no - * card detect GPIO. - */ - - sdio_mediachange(g_sdio, true); - - syslog(LOG_INFO, "[boot] Initialized SDIO\n"); -#endif - -#ifdef CONFIG_ADC - /* Initialize ADC and register the ADC driver. */ - - ret = stm32_adc_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_adc_setup failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_SENSORS_QENCODER - /* Initialize and register the qencoder driver */ - - ret = board_qencoder_initialize(0, CONFIG_NUCLEO_F411RE_QETIMER); - if (ret != OK) - { - syslog(LOG_ERR, - "ERROR: Failed to register the qencoder: %d\n", - ret); - return ret; - } -#endif - -#ifdef CONFIG_INPUT_AJOYSTICK - /* Initialize and register the joystick driver */ - - ret = board_ajoy_initialize(); - if (ret != OK) - { - syslog(LOG_ERR, - "ERROR: Failed to register the joystick driver: %d\n", - ret); - return ret; - } -#endif - - return ret; -} diff --git a/boards/arm/stm32/nucleo-f411re/src/stm32_buttons.c b/boards/arm/stm32/nucleo-f411re/src/stm32_buttons.c deleted file mode 100644 index 7d064a6b2d5e9..0000000000000 --- a/boards/arm/stm32/nucleo-f411re/src/stm32_buttons.c +++ /dev/null @@ -1,117 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f411re/src/stm32_buttons.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include - -#include "stm32_gpio.h" -#include "nucleo-f411re.h" - -#include - -#ifdef CONFIG_ARCH_BUTTONS - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_button_initialize - * - * Description: - * board_button_initialize() must be called to initialize button resources. - * After that, board_buttons() may be called to collect the current state - * of all buttons or board_button_irq() may be called to register button - * interrupt handlers. - * - ****************************************************************************/ - -uint32_t board_button_initialize(void) -{ - /* Configure the single button as an input. NOTE that EXTI interrupts are - * also configured for the pin. - */ - - stm32_configgpio(GPIO_BTN_USER); - return NUM_BUTTONS; -} - -/**************************************************************************** - * Name: board_buttons - ****************************************************************************/ - -uint32_t board_buttons(void) -{ - /* Check that state of each USER button. A LOW value means that the key is - * pressed. - */ - - bool released = stm32_gpioread(GPIO_BTN_USER); - return !released; -} - -/**************************************************************************** - * Button support. - * - * Description: - * board_button_initialize() must be called to initialize button resources. - * After that, board_buttons() may be called to collect the current state - * of all buttons or board_button_irq() may be called to register button - * interrupt handlers. - * - * After board_button_initialize() has been called, board_buttons() may be - * called to collect the state of all buttons. board_buttons() returns an - * 32-bit bit set with each bit associated with a button. See the - * BUTTON_*_BIT definitions in board.h for the meaning of each bit. - * - * board_button_irq() may be called to register an interrupt handler that - * will be called when a button is depressed or released. The ID value is a - * button enumeration value that uniquely identifies a button resource. See - * the BUTTON_* definitions in board.h for the meaning of enumeration - * value. - * - ****************************************************************************/ - -#ifdef CONFIG_ARCH_IRQBUTTONS -int board_button_irq(int id, xcpt_t irqhandler, void *arg) -{ - int ret = -EINVAL; - - if (id == BUTTON_USER) - { - ret = stm32_gpiosetevent(GPIO_BTN_USER, true, true, true, - irqhandler, arg); - } - - return ret; -} -#endif -#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/stm32/nucleo-f411re/src/stm32_lcd_ssd1306.c b/boards/arm/stm32/nucleo-f411re/src/stm32_lcd_ssd1306.c deleted file mode 100644 index 558b20fa145a8..0000000000000 --- a/boards/arm/stm32/nucleo-f411re/src/stm32_lcd_ssd1306.c +++ /dev/null @@ -1,88 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f411re/src/stm32_lcd_ssd1306.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include -#include -#include - -#include "stm32.h" -#include "nucleo-f411re.h" - -#include "stm32_ssd1306.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#define OLED_SPI_PORT 1 /* OLED display connected to SPI1 */ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_lcd_initialize - ****************************************************************************/ - -int board_lcd_initialize(void) -{ - int ret; - - ret = board_ssd1306_initialize(OLED_SPI_PORT); - if (ret < 0) - { - lcderr("ERROR: Failed to initialize SSD1306\n"); - return ret; - } - - return OK; -} - -/**************************************************************************** - * Name: board_lcd_getdev - ****************************************************************************/ - -struct lcd_dev_s *board_lcd_getdev(int devno) -{ - return board_ssd1306_getdev(); -} - -/**************************************************************************** - * Name: board_lcd_uninitialize - ****************************************************************************/ - -void board_lcd_uninitialize(void) -{ - /* TO-FIX */ -} diff --git a/boards/arm/stm32/nucleo-f411re/src/stm32_mcp2515.c b/boards/arm/stm32/nucleo-f411re/src/stm32_mcp2515.c deleted file mode 100644 index 2de6483c23635..0000000000000 --- a/boards/arm/stm32/nucleo-f411re/src/stm32_mcp2515.c +++ /dev/null @@ -1,241 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f411re/src/stm32_mcp2515.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include "stm32.h" -#include "stm32_spi.h" -#include "nucleo-f411re.h" - -#if defined(CONFIG_SPI) && defined(CONFIG_STM32_SPI1) && \ - defined(CONFIG_CAN_MCP2515) - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#define MCP2515_SPI_PORTNO 1 /* On SPI1 */ - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -struct stm32_mcp2515config_s -{ - /* Configuration structure as seen by the MCP2515 driver */ - - struct mcp2515_config_s config; - - /* Additional private definitions only known to this driver */ - - struct mcp2515_can_s *handle; /* The MCP2515 driver handle */ - mcp2515_handler_t handler; /* The MCP2515 interrupt handler */ - void *arg; /* Argument to pass to the interrupt handler */ -}; - -/**************************************************************************** - * Static Function Prototypes - ****************************************************************************/ - -/* IRQ/GPIO access callbacks. These operations all hidden behind callbacks - * to isolate the MCP2515 driver from differences in GPIO interrupt handling - * by varying boards and MCUs. - * - * attach - Attach the MCP2515 interrupt handler to the GPIO interrupt - */ - -static int mcp2515_attach(struct mcp2515_config_s *state, - mcp2515_handler_t handler, void *arg); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* A reference to a structure of this type must be passed to the MCP2515 - * driver. This structure provides information about the configuration - * of the MCP2515 and provides some board-specific hooks. - * - * Memory for this structure is provided by the caller. It is not copied - * by the driver and is presumed to persist while the driver is active. The - * memory must be writable because, under certain circumstances, the driver - * may modify frequency or X plate resistance values. - */ - -static struct stm32_mcp2515config_s g_mcp2515config = -{ - .config = - { - .spi = NULL, - .baud = 0, /* REVISIT. Probably broken by commit eb7373cedfa */ - .btp = 0, /* REVISIT. Probably broken by commit eb7373cedfa */ - .devid = 0, - .mode = 0, /* REVISIT. Probably broken by commit eb7373cedfa */ - .nfilters = 6, -#ifdef MCP2515_LOOPBACK - .loopback = false; -#endif - .attach = mcp2515_attach, - }, -}; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/* This is the MCP2515 Interrupt handler */ - -int mcp2515_interrupt(int irq, void *context, void *arg) -{ - struct stm32_mcp2515config_s *priv = - (struct stm32_mcp2515config_s *)arg; - - DEBUGASSERT(priv != NULL); - - /* Verify that we have a handler attached */ - - if (priv->handler) - { - /* Yes.. forward with interrupt along with its argument */ - - priv->handler(&priv->config, priv->arg); - } - - return OK; -} - -static int mcp2515_attach(struct mcp2515_config_s *state, - mcp2515_handler_t handler, void *arg) -{ - struct stm32_mcp2515config_s *priv = - (struct stm32_mcp2515config_s *)state; - irqstate_t flags; - - caninfo("Saving handler %p\n", handler); - - flags = enter_critical_section(); - - priv->handler = handler; - priv->arg = arg; - - /* Configure the interrupt for falling edge */ - - stm32_gpiosetevent(GPIO_MCP2515_IRQ, false, true, false, - mcp2515_interrupt, priv); - - leave_critical_section(flags); - - return OK; -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_mcp2515initialize - * - * Description: - * Initialize and register the MCP2515 RFID driver. - * - * Input Parameters: - * devpath - The full path to the driver to register. E.g., "/dev/rfid0" - * - * Returned Value: - * Zero (OK) on success; a negated errno value on failure. - * - ****************************************************************************/ - -int stm32_mcp2515initialize(const char *devpath) -{ - struct spi_dev_s *spi; - struct can_dev_s *can; - struct mcp2515_can_s *mcp2515; - int ret; - - /* Check if we are already initialized */ - - if (!g_mcp2515config.handle) - { - sninfo("Initializing\n"); - - /* Configure the MCP2515 interrupt pin as an input */ - - stm32_configgpio(GPIO_MCP2515_IRQ); - - spi = stm32_spibus_initialize(MCP2515_SPI_PORTNO); - - if (!spi) - { - return -ENODEV; - } - - /* Save the SPI instance in the mcp2515_config_s structure */ - - g_mcp2515config.config.spi = spi; - - /* Instantiate the MCP2515 CAN Driver */ - - mcp2515 = mcp2515_instantiate(&g_mcp2515config.config); - if (mcp2515 == NULL) - { - canerr("ERROR: Failed to get MCP2515 Driver Loaded\n"); - return -ENODEV; - } - - /* Save the opaque structure */ - - g_mcp2515config.handle = mcp2515; - - /* Initialize the CAN Device with the MCP2515 operations */ - - can = mcp2515_initialize(mcp2515); - if (can == NULL) - { - canerr("ERROR: Failed to get CAN interface\n"); - return -ENODEV; - } - - /* Register the CAN driver at "/dev/can0" */ - - ret = can_register(devpath, can); - if (ret < 0) - { - canerr("ERROR: can_register failed: %d\n", ret); - return ret; - } - } - - return OK; -} - -#endif /* CONFIG_SPI && CONFIG_CAN_MCP2515 */ diff --git a/boards/arm/stm32/nucleo-f411re/src/stm32_spi.c b/boards/arm/stm32/nucleo-f411re/src/stm32_spi.c deleted file mode 100644 index 9a7d4878355aa..0000000000000 --- a/boards/arm/stm32/nucleo-f411re/src/stm32_spi.c +++ /dev/null @@ -1,246 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f411re/src/stm32_spi.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include - -#include - -#include "arm_internal.h" -#include "chip.h" -#include "stm32.h" - -#include "nucleo-f411re.h" - -#include - -#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || \ - defined(CONFIG_STM32_SPI3) - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/* Global driver instances */ - -#ifdef CONFIG_STM32_SPI1 -struct spi_dev_s *g_spi1; -#endif -#ifdef CONFIG_STM32_SPI2 -struct spi_dev_s *g_spi2; -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_spidev_initialize - * - * Description: - * Called to configure SPI chip select GPIO pins for the Nucleo-F411RE - * - ****************************************************************************/ - -void weak_function stm32_spidev_initialize(void) -{ -#ifdef CONFIG_STM32_SPI1 - /* Configure SPI-based devices */ - - g_spi1 = stm32_spibus_initialize(1); - if (!g_spi1) - { - spierr("ERROR: FAILED to initialize SPI port 1\n"); - } - -#ifdef CONFIG_LCD_SSD1306_SPI - stm32_configgpio(GPIO_SSD1306_CS); /* SSD1306 chip select */ - stm32_configgpio(GPIO_SSD1306_CMD); /* SSD1306 data/!command */ -#endif - -#ifdef CONFIG_CAN_MCP2515 - stm32_configgpio(GPIO_MCP2515_CS); /* MCP2515 chip select */ -#endif - -#ifdef HAVE_MMCSD - stm32_configgpio(GPIO_SPI_CS_SD_CARD); -#endif -#endif - -#ifdef CONFIG_STM32_SPI2 - /* Configure SPI-based devices */ - - g_spi2 = stm32_spibus_initialize(2); -#endif -} - -/**************************************************************************** - * Name: stm32_spi1/2/3select and stm32_spi1/2/3status - * - * Description: - * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status - * must be provided by board-specific logic. They are implementations of - * the select and status methods of the SPI interface defined by struct - * spi_ops_s (see include/nuttx/spi/spi.h). All other methods (including - * stm32_spibus_initialize()) are provided by common STM32 logic. To use - * this common SPI logic on your board: - * - * 1. Provide logic in stm32_boardinitialize() to configure SPI chip select - * pins. - * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() functions - * in your board-specific logic. These functions will perform chip - * selection and status operations using GPIOs in the way your board is - * configured. - * 3. Add a calls to stm32_spibus_initialize() in your low level - * application initialization logic - * 4. The handle returned by stm32_spibus_initialize() may then be used to - * bind the SPI driver to higher level logic (e.g., calling - * mmcsd_spislotinitialize(), for example, will bind the SPI driver to - * the SPI MMC/SD driver). - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_SPI1 -void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, - bool selected) -{ - spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : - "de-assert"); - -#if defined(CONFIG_LCD_SSD1306_SPI) - if (devid == SPIDEV_DISPLAY(0)) - { - stm32_gpiowrite(GPIO_SSD1306_CS, !selected); - } -#endif - -#if defined(CONFIG_CAN_MCP2515) - if (devid == SPIDEV_CANBUS(0)) - { - stm32_gpiowrite(GPIO_MCP2515_CS, !selected); - } -#endif - -#ifdef HAVE_MMCSD - if (devid == SPIDEV_MMCSD(0)) - { - stm32_gpiowrite(GPIO_SPI_CS_SD_CARD, !selected); - } -#endif -} - -uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) -{ - return 0; -} -#endif - -#ifdef CONFIG_STM32_SPI2 -void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid, - bool selected) -{ - spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : - "de-assert"); -} - -uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) -{ - return 0; -} -#endif - -#ifdef CONFIG_STM32_SPI3 -void stm32_spi3select(struct spi_dev_s *dev, uint32_t devid, - bool selected) -{ - spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : - "de-assert"); -} - -uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid) -{ - return 0; -} -#endif - -/**************************************************************************** - * Name: stm32_spi1cmddata - * - * Description: - * Set or clear the SH1101A A0 or SD1306 D/C n bit to select data (true) - * or command (false). This function must be provided by platform-specific - * logic. This is an implementation of the cmddata method of the SPI - * interface defined by struct spi_ops_s (see include/nuttx/spi/spi.h). - * - * Input Parameters: - * - * spi - SPI device that controls the bus the device that requires the CMD/ - * DATA selection. - * devid - If there are multiple devices on the bus, this selects which one - * to select cmd or data. NOTE: This design restricts, for example, - * one one SPI display per SPI bus. - * cmd - true: select command; false: select data - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef CONFIG_SPI_CMDDATA -#ifdef CONFIG_STM32_SPI1 -int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) -{ -#if defined(CONFIG_LCD_SSD1306_SPI) - if (devid == SPIDEV_DISPLAY(0)) - { - stm32_gpiowrite(GPIO_SSD1306_CMD, !cmd); - } -#endif - - return OK; -} -#endif - -#ifdef CONFIG_STM32_SPI2 -int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) -{ - return OK; -} -#endif - -#ifdef CONFIG_STM32_SPI3 -int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) -{ - return OK; -} -#endif -#endif /* CONFIG_SPI_CMDDATA */ - -#endif /* CONFIG_STM32_SPI1 || CONFIG_STM32_SPI2 || CONFIG_STM32_SPI3 */ diff --git a/boards/arm/stm32/nucleo-f411re/src/stm32_userleds.c b/boards/arm/stm32/nucleo-f411re/src/stm32_userleds.c deleted file mode 100644 index 63434897ac3f3..0000000000000 --- a/boards/arm/stm32/nucleo-f411re/src/stm32_userleds.c +++ /dev/null @@ -1,218 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f411re/src/stm32_userleds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include - -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32.h" -#include "nucleo-f411re.h" - -#include - -#ifndef CONFIG_ARCH_LEDS - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -/* LED Power Management */ - -#ifdef CONFIG_PM -static void led_pm_notify(struct pm_callback_s *cb, int domain, - enum pm_state_e pmstate); -static int led_pm_prepare(struct pm_callback_s *cb, int domain, - enum pm_state_e pmstate); -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -#ifdef CONFIG_PM -static struct pm_callback_s g_ledscb = -{ - .notify = led_pm_notify, - .prepare = led_pm_prepare, -}; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: led_pm_notify - * - * Description: - * Notify the driver of new power state. This callback is called after - * all drivers have had the opportunity to prepare for the new power state. - * - ****************************************************************************/ - -#ifdef CONFIG_PM -static void led_pm_notify(struct pm_callback_s *cb, int domain, - enum pm_state_e pmstate) -{ - switch (pmstate) - { - case PM_NORMAL: - { - /* Restore normal LEDs operation */ - } - break; - - case PM_IDLE: - { - /* Entering IDLE mode - Turn leds off */ - } - break; - - case PM_STANDBY: - { - /* Entering STANDBY mode - Logic for PM_STANDBY goes here */ - } - break; - - case PM_SLEEP: - { - /* Entering SLEEP mode - Logic for PM_SLEEP goes here */ - } - break; - - default: - { - /* Should not get here */ - } - break; - } -} -#endif - -/**************************************************************************** - * Name: led_pm_prepare - * - * Description: - * Request the driver to prepare for a new power state. This is a warning - * that the system is about to enter into a new power state. The driver - * should begin whatever operations that may be required to enter power - * state. The driver may abort the state change mode by returning a - * non-zero value from the callback function. - * - ****************************************************************************/ - -#ifdef CONFIG_PM -static int led_pm_prepare(struct pm_callback_s *cb, int domain, - enum pm_state_e pmstate) -{ - /* No preparation to change power modes is required by the LEDs driver. - * We always accept the state change by returning OK. - */ - - return OK; -} -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_userled_initialize - ****************************************************************************/ - -uint32_t board_userled_initialize(void) -{ - /* Configure LD2 GPIO for output */ - - stm32_configgpio(GPIO_LD2); - return BOARD_NLEDS; -} - -/**************************************************************************** - * Name: board_userled - ****************************************************************************/ - -void board_userled(int led, bool ledon) -{ - if (BOARD_LD2_BIT == (1 << led)) - { - stm32_gpiowrite(GPIO_LD2, ledon); - } -} - -/**************************************************************************** - * Name: board_userled_all - ****************************************************************************/ - -void board_userled_all(uint32_t ledset) -{ - /* An output of '1' illuminates the LED */ - - stm32_gpiowrite(GPIO_LD2, (ledset & BOARD_LD2_BIT) != 0); -} - -#ifdef CONFIG_USERLED_LOWER_READSTATE -/**************************************************************************** - * Name: board_userled_getall - ****************************************************************************/ - -void board_userled_getall(uint32_t *ledset) -{ - /* Clear the LED bits */ - - *ledset = 0; - - /* Get LED state. An output of '1' illuminates the LED. */ - - *ledset |= ((stm32_gpioread(GPIO_LD2) & 1) << BOARD_LD2); -} - -#endif /* CONFIG_USERLED_LOWER_READSTATE */ - -/**************************************************************************** - * Name: stm32_led_pminitialize - ****************************************************************************/ - -#ifdef CONFIG_PM -void stm32_led_pminitialize(void) -{ - /* Register to receive power management callbacks */ - - int ret = pm_register(&g_ledscb); - DEBUGASSERT(ret == OK); - UNUSED(ret); -} -#endif /* CONFIG_PM */ - -#endif /* !CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/nucleo-f412zg/CMakeLists.txt b/boards/arm/stm32/nucleo-f412zg/CMakeLists.txt deleted file mode 100644 index df7b29ff230fd..0000000000000 --- a/boards/arm/stm32/nucleo-f412zg/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/nucleo-f412zg/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32/nucleo-f412zg/configs/coremark/defconfig b/boards/arm/stm32/nucleo-f412zg/configs/coremark/defconfig deleted file mode 100644 index 6dd586b0050fc..0000000000000 --- a/boards/arm/stm32/nucleo-f412zg/configs/coremark/defconfig +++ /dev/null @@ -1,51 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_DISABLE_OS_API is not set -# CONFIG_STM32_SYSCFG is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="nucleo-f412zg" -CONFIG_ARCH_BOARD_NUCLEO_F412ZG=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F412ZG=y -CONFIG_ARCH_INTERRUPTSTACK=2048 -CONFIG_ARCH_SIZET_LONG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BENCHMARK_COREMARK=y -CONFIG_BOARDCTL=y -CONFIG_BOARDCTL_MKRD=y -CONFIG_BOARD_LOOPSPERMSEC=8499 -CONFIG_BUILTIN=y -CONFIG_DEBUG_CUSTOMOPT=y -CONFIG_DEBUG_HARDFAULT_ALERT=y -CONFIG_DEBUG_OPTLEVEL="-O3" -CONFIG_INIT_ENTRYPOINT="coremark_main" -CONFIG_INIT_STACKSIZE=4096 -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_PREALLOC_CHILDSTATUS=2 -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=262144 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_SCHED_CHILD_STATUS=y -CONFIG_SCHED_HAVE_PARENT=y -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=30 -CONFIG_START_MONTH=11 -CONFIG_START_YEAR=2019 -CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32_FLASH_PREFETCH=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_SERIAL_DISABLE_REORDERING=y -CONFIG_STM32_USART3=y -CONFIG_SYSTEM_READLINE=y -CONFIG_TASK_NAME_SIZE=32 -CONFIG_USART3_SERIAL_CONSOLE=y -CONFIG_USEC_PER_TICK=1000 diff --git a/boards/arm/stm32/nucleo-f412zg/configs/nsh/defconfig b/boards/arm/stm32/nucleo-f412zg/configs/nsh/defconfig deleted file mode 100644 index fc06830d00be0..0000000000000 --- a/boards/arm/stm32/nucleo-f412zg/configs/nsh/defconfig +++ /dev/null @@ -1,59 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_DISABLE_OS_API is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -# CONFIG_NSH_DISABLE_IFCONFIG is not set -# CONFIG_NSH_DISABLE_PS is not set -# CONFIG_STM32_SYSCFG is not set -CONFIG_ADC=y -CONFIG_ANALOG=y -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="nucleo-f412zg" -CONFIG_ARCH_BOARD_NUCLEO_F412ZG=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F412ZG=y -CONFIG_ARCH_INTERRUPTSTACK=2048 -CONFIG_ARCH_SIZET_LONG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=8499 -CONFIG_BUILTIN=y -CONFIG_CAN=y -CONFIG_DEBUG_HARDFAULT_ALERT=y -CONFIG_HAVE_CXX=y -CONFIG_I2C=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_CHILDSTATUS=2 -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=262144 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_SCHED_CHILD_STATUS=y -CONFIG_SCHED_HAVE_PARENT=y -CONFIG_SCHED_WAITPID=y -CONFIG_SPI=y -CONFIG_START_DAY=30 -CONFIG_START_MONTH=11 -CONFIG_START_YEAR=2019 -CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32_FLASH_PREFETCH=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_SERIAL_DISABLE_REORDERING=y -CONFIG_STM32_USART3=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=32 -CONFIG_TIMER=y -CONFIG_USART3_SERIAL_CONSOLE=y -CONFIG_USEC_PER_TICK=1000 diff --git a/boards/arm/stm32/nucleo-f412zg/configs/ostest/defconfig b/boards/arm/stm32/nucleo-f412zg/configs/ostest/defconfig deleted file mode 100644 index 5c9c9c9657cc1..0000000000000 --- a/boards/arm/stm32/nucleo-f412zg/configs/ostest/defconfig +++ /dev/null @@ -1,60 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_DISABLE_OS_API is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -# CONFIG_NSH_DISABLE_IFCONFIG is not set -# CONFIG_NSH_DISABLE_PS is not set -# CONFIG_STM32_SYSCFG is not set -CONFIG_ADC=y -CONFIG_ANALOG=y -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="nucleo-f412zg" -CONFIG_ARCH_BOARD_NUCLEO_F412ZG=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F412ZG=y -CONFIG_ARCH_INTERRUPTSTACK=2048 -CONFIG_ARCH_SIZET_LONG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=8499 -CONFIG_BUILTIN=y -CONFIG_CAN=y -CONFIG_DEBUG_HARDFAULT_ALERT=y -CONFIG_HAVE_CXX=y -CONFIG_I2C=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_CHILDSTATUS=2 -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=262144 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_SCHED_CHILD_STATUS=y -CONFIG_SCHED_HAVE_PARENT=y -CONFIG_SCHED_WAITPID=y -CONFIG_SPI=y -CONFIG_START_DAY=30 -CONFIG_START_MONTH=11 -CONFIG_START_YEAR=2019 -CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32_FLASH_PREFETCH=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_SERIAL_DISABLE_REORDERING=y -CONFIG_STM32_USART3=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=32 -CONFIG_TESTING_OSTEST=y -CONFIG_TIMER=y -CONFIG_USART3_SERIAL_CONSOLE=y -CONFIG_USEC_PER_TICK=1000 diff --git a/boards/arm/stm32/nucleo-f412zg/include/board.h b/boards/arm/stm32/nucleo-f412zg/include/board.h deleted file mode 100644 index 9414bde3d6331..0000000000000 --- a/boards/arm/stm32/nucleo-f412zg/include/board.h +++ /dev/null @@ -1,228 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f412zg/include/board.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __BOARDS_ARM_STM32_NUCLEO_F412ZG_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32_NUCLEO_F412ZG_INCLUDE_BOARD_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#ifndef __ASSEMBLY__ -# include -#endif - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* HSI - 16 MHz RC factory-trimmed - * LSI - 32 KHz RC - * HSE - 8 MHz Crystal - * LSE - not installed - */ - -#define STM32_BOARD_USEHSE 1 -#define STM32_BOARD_XTAL 8000000 -#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL - -#define STM32_HSI_FREQUENCY 16000000ul -#define STM32_LSI_FREQUENCY 32000 - -/* Main PLL Configuration */ - -#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(8) -#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(384) -#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_4 -#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(8) -#define STM32_PLLCFG_PLLR RCC_PLLCFG_PLLR(2) - -#define STM32_RCC_PLLI2SCFGR_PLLI2SM RCC_PLLI2SCFGR_PLLI2SM(16) -#define STM32_RCC_PLLI2SCFGR_PLLI2SN RCC_PLLI2SCFGR_PLLI2SN(192) -#define STM32_RCC_PLLI2SCFGR_PLLI2SQ RCC_PLLI2SCFGR_PLLI2SQ(2) -#define STM32_RCC_PLLI2SCFGR_PLLI2SR RCC_PLLI2SCFGR_PLLI2SR(2) -#define STM32_RCC_PLLI2SCFGR_PLLI2SSRC RCC_PLLI2SCFGR_PLLI2SSRC(0) /* HSE or HSI depending on PLLSRC of PLLCFGR*/ - -#define STM32_RCC_DCKCFGR2_CK48MSEL RCC_DCKCFGR2_CK48MSEL_PLL -#define STM32_RCC_DCKCFGR2_FMPI2C1SEL RCC_DCKCFGR2_FMPI2C1SEL_APB -#define STM32_RCC_DCKCFGR2_SDIOSEL RCC_DCKCFGR2_SDIOSEL_48MHZ - -#define STM32_SYSCLK_FREQUENCY 96000000ul - -/* AHB clock (HCLK) is SYSCLK (96MHz) */ - -#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ -#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY - -/* APB1 clock (PCLK1) is HCLK/2 (48MHz) */ - -#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd2 /* PCLK1 = HCLK / 2 */ -#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/2) - -/* Timers driven from APB1 will be twice PCLK1 */ - -#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) - -/* APB2 clock (PCLK2) is HCLK (96MHz) */ - -#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK */ -#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY) - -/* Timers driven from APB2 will be PCLK2 since no prescale division */ - -#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM9_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM10_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM11_CLKIN (STM32_PCLK2_FREQUENCY) - -/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx - * otherwise frequency is 2xAPBx. - * Note: TIM1,8 are on APB2, others on APB1 - */ - -#define BOARD_TIM2_FREQUENCY (2 * STM32_PCLK1_FREQUENCY) -#define BOARD_TIM3_FREQUENCY (2 * STM32_PCLK1_FREQUENCY) -#define BOARD_TIM4_FREQUENCY (2 * STM32_PCLK1_FREQUENCY) -#define BOARD_TIM5_FREQUENCY (2 * STM32_PCLK1_FREQUENCY) -#define BOARD_TIM6_FREQUENCY (2 * STM32_PCLK1_FREQUENCY) -#define BOARD_TIM7_FREQUENCY (2 * STM32_PCLK1_FREQUENCY) -#define BOARD_TIM8_FREQUENCY (2 * STM32_PCLK2_FREQUENCY) - -/* Alternate function pin selections ****************************************/ - -/* USART2: - * RXD: PD6 CN9 pin 4 - * TXD: PD5 CN9 pin 6 - */ - -# define GPIO_USART2_RX (GPIO_USART2_RX_2|GPIO_SPEED_100MHz) -# define GPIO_USART2_TX (GPIO_USART2_TX_2|GPIO_SPEED_100MHz) - -/* USART3 (ST-LINK Virtual COM Port): - * RXD: PD9 - * TXD: PD8 - */ - -# define GPIO_USART3_RX (GPIO_USART3_RX_3|GPIO_SPEED_100MHz) -# define GPIO_USART3_TX (GPIO_USART3_TX_3|GPIO_SPEED_100MHz) - -/* USART6: - * RXD: PG9 CN10 pin 16 - * TXD: PG14 CN10 pin 14 - */ - -#define GPIO_USART6_RX (GPIO_USART6_RX_2|GPIO_SPEED_100MHz) -#define GPIO_USART6_TX (GPIO_USART6_TX_2|GPIO_SPEED_100MHz) - -/* I2C1: - * SCL: PB8 CN7 pin2 - * SDA: PB9 CN7 pin4 - */ - -#define GPIO_I2C1_SCL (GPIO_I2C1_SCL_2|GPIO_SPEED_50MHz) -#define GPIO_I2C1_SDA (GPIO_I2C1_SDA_2|GPIO_SPEED_50MHz) - -#define GPIO_I2C1_SCL_GPIO \ - (GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTB|GPIO_PIN8) -#define GPIO_I2C1_SDA_GPIO \ - (GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTB|GPIO_PIN9) - -/* SPI1: - * MISO: PA6 CN7 pin 12 - * MOSI: PA7 CN7 pin 14 - * SCK: PA5 CN7 pin 10 - */ - -#define GPIO_SPI1_MISO (GPIO_SPI1_MISO_1|GPIO_SPEED_50MHz) -#define GPIO_SPI1_MOSI (GPIO_SPI1_MOSI_1|GPIO_SPEED_50MHz) -#define GPIO_SPI1_SCK (GPIO_SPI1_SCK_1|GPIO_SPEED_50MHz) - -/* CAN1: - * RX: PD0 CN9 pin 25 - * TX: PD1 CN9 pin 27 - */ - -#define GPIO_CAN1_RX (GPIO_CAN1_RX_3|GPIO_SPEED_50MHz) -#define GPIO_CAN1_TX (GPIO_CAN1_TX_3|GPIO_SPEED_50MHz) - -/* LEDs - * - * The NUCLEO-F412ZG board has 3 user leds. - * LD1: PB0 GREEN - * LD2: PB7 BLUE - * LD3: PB14 RED - */ - -#define BOARD_NLEDS 3 - -#define GPIO_LD1 \ -(GPIO_PORTB | GPIO_PIN0 | GPIO_OUTPUT_CLEAR | GPIO_OUTPUT | GPIO_PULLUP | \ -GPIO_SPEED_50MHz) - -#define GPIO_LD2 \ -(GPIO_PORTB | GPIO_PIN7 | GPIO_OUTPUT_CLEAR | GPIO_OUTPUT | GPIO_PULLUP | \ -GPIO_SPEED_50MHz) - -#define GPIO_LD3 \ -(GPIO_PORTB | GPIO_PIN14 | GPIO_OUTPUT_CLEAR | GPIO_OUTPUT | GPIO_PULLUP | \ -GPIO_SPEED_50MHz) - -/* These LEDs are not used by the board port unless CONFIG_ARCH_LEDS is - * defined. In that case, the usage by the board port is defined in - * include/board.h and src/sam_leds.c. The LEDs are used to encode OS-related - * events as follows when the red LED (PE24) is available: - * - * SYMBOL Meaning - * ------------------- ----------------------- - * LED_STARTED NuttX has been started - * LED_HEAPALLOCATE Heap has been allocated - * LED_IRQSENABLED Interrupts enabled - * LED_STACKCREATED Idle stack created - * LED_INIRQ In an interrupt - * LED_SIGNAL In a signal handler - * LED_ASSERTION An assertion failed - * LED_PANIC The system has crashed - * LED_IDLE MCU is in sleep mode - * - * Thus if LD2, NuttX has successfully booted and is, apparently, running - * normally. If LD2 is flashing at approximately 2Hz, then a fatal error - * has been detected and the system has halted. - */ - -#define LED_STARTED 1 -#define LED_HEAPALLOCATE 0 -#define LED_IRQSENABLED 0 -#define LED_STACKCREATED 3 -#define LED_INIRQ 0 -#define LED_SIGNAL 0 -#define LED_ASSERTION 1 -#define LED_PANIC 1 - -#endif /* __BOARDS_ARM_STM32_NUCLEO_F412ZG_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32/nucleo-f412zg/scripts/Make.defs b/boards/arm/stm32/nucleo-f412zg/scripts/Make.defs deleted file mode 100644 index 9cc6754a29403..0000000000000 --- a/boards/arm/stm32/nucleo-f412zg/scripts/Make.defs +++ /dev/null @@ -1,42 +0,0 @@ -############################################################################ -# boards/arm/stm32/nucleo-f412zg/scripts/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include ${TOPDIR}/.config -include ${TOPDIR}/tools/Config.mk -include ${TOPDIR}/arch/arm/src/armv7-m/Toolchain.defs - -LDSCRIPT = f412zg.ld -ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) - -ARCHDEFINES = -ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 - -CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) -CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) -CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -AFLAGS := $(CFLAGS) -D__ASSEMBLY__ - -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections -LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32/nucleo-f412zg/src/CMakeLists.txt b/boards/arm/stm32/nucleo-f412zg/src/CMakeLists.txt deleted file mode 100644 index b3cae915b2537..0000000000000 --- a/boards/arm/stm32/nucleo-f412zg/src/CMakeLists.txt +++ /dev/null @@ -1,35 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/nucleo-f412zg/src/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -set(SRCS stm32_boot.c stm32_bringup.c) - -if(CONFIG_ARCH_LEDS) - list(APPEND SRCS stm32_autoleds.c) -endif() - -if(CONFIG_STM32_OTGFS) - list(APPEND SRCS stm32_usb.c) -endif() - -target_sources(board PRIVATE ${SRCS}) - -set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/f412zg.ld") diff --git a/boards/arm/stm32/nucleo-f412zg/src/Make.defs b/boards/arm/stm32/nucleo-f412zg/src/Make.defs deleted file mode 100644 index d437533fd2453..0000000000000 --- a/boards/arm/stm32/nucleo-f412zg/src/Make.defs +++ /dev/null @@ -1,38 +0,0 @@ -############################################################################ -# boards/arm/stm32/nucleo-f412zg/src/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - --include $(TOPDIR)/Make.defs - -ASRCS = -CSRCS = stm32_boot.c stm32_bringup.c - -ifeq ($(CONFIG_ARCH_LEDS),y) -CSRCS += stm32_autoleds.c -endif - -ifeq ($(CONFIG_STM32_OTGFS),y) -CSRCS += stm32_usb.c -endif - -DEPPATH += --dep-path board -VPATH += :board -CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/nucleo-f412zg/src/stm32_autoleds.c b/boards/arm/stm32/nucleo-f412zg/src/stm32_autoleds.c deleted file mode 100644 index 554db9c523bb6..0000000000000 --- a/boards/arm/stm32/nucleo-f412zg/src/stm32_autoleds.c +++ /dev/null @@ -1,104 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f412zg/src/stm32_autoleds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32.h" -#include "nucleo-f412zg.h" - -#ifdef CONFIG_ARCH_LEDS - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_autoled_initialize - ****************************************************************************/ - -void board_autoled_initialize(void) -{ - stm32_configgpio(GPIO_LD1); - stm32_configgpio(GPIO_LD2); - stm32_configgpio(GPIO_LD3); -} - -/**************************************************************************** - * Name: board_autoled_on - ****************************************************************************/ - -void board_autoled_on(int led) -{ - switch (led) - { - case 1: - stm32_gpiowrite(GPIO_LD1, true); - break; - case 2: - stm32_gpiowrite(GPIO_LD1, true); - stm32_gpiowrite(GPIO_LD2, true); - break; - case 3: - stm32_gpiowrite(GPIO_LD1, true); - stm32_gpiowrite(GPIO_LD2, true); - stm32_gpiowrite(GPIO_LD3, true); - break; - } -} - -/**************************************************************************** - * Name: board_autoled_off - ****************************************************************************/ - -void board_autoled_off(int led) -{ - switch (led) - { - case 1: - stm32_gpiowrite(GPIO_LD1, false); - break; - case 2: - stm32_gpiowrite(GPIO_LD1, false); - stm32_gpiowrite(GPIO_LD2, false); - break; - case 3: - stm32_gpiowrite(GPIO_LD1, false); - stm32_gpiowrite(GPIO_LD2, false); - stm32_gpiowrite(GPIO_LD3, false); - break; - } -} - -#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/nucleo-f412zg/src/stm32_boot.c b/boards/arm/stm32/nucleo-f412zg/src/stm32_boot.c deleted file mode 100644 index f55d0686040e3..0000000000000 --- a/boards/arm/stm32/nucleo-f412zg/src/stm32_boot.c +++ /dev/null @@ -1,100 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f412zg/src/stm32_boot.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include -#include - -#include - -#include "arm_internal.h" -#include "nucleo-f412zg.h" -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_boardinitialize - * - * Description: - * All STM32 architectures must provide the following entry point. This - * entry point is called early in the initialization -- after all memory - * has been configured and mapped but before any devices have been - * initialized. - * - ****************************************************************************/ - -void stm32_boardinitialize(void) -{ -#ifdef CONFIG_ARCH_LEDS - /* Configure on-board LEDs if LED support has been selected. */ - - board_autoled_initialize(); -#endif - -#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || \ - defined(CONFIG_STM32_SPI3) - /* Configure SPI chip selects if 1) SP2 is not disabled, and 2) the - * weak function stm32_spidev_initialize() has been brought into the link. - */ - - stm32_spidev_initialize(); -#endif - -#ifdef CONFIG_STM32_OTGFS - /* Initialize USB if the OTG FS controller is in the configuration. - * Presumably either CONFIG_USBDEV or CONFIG_USBHOST is also selected. - */ - - stm32_usbinitialize(); -#endif -} - -/**************************************************************************** - * Name: board_late_initialize - * - * Description: - * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional - * initialization call will be performed in the boot-up sequence to a - * function called board_late_initialize(). board_late_initialize() will - * be called immediately after up_initialize() is called and just before - * the initial application is started. This additional initialization - * phase may be used, for example, to initialize board-specific device - * drivers. - * - ****************************************************************************/ - -#ifdef CONFIG_BOARD_LATE_INITIALIZE -void board_late_initialize(void) -{ - /* Perform board-specific initialization */ - - stm32_bringup(); -} -#endif diff --git a/boards/arm/stm32/nucleo-f412zg/src/stm32_bringup.c b/boards/arm/stm32/nucleo-f412zg/src/stm32_bringup.c deleted file mode 100644 index 5b14c9c8f271c..0000000000000 --- a/boards/arm/stm32/nucleo-f412zg/src/stm32_bringup.c +++ /dev/null @@ -1,84 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f412zg/src/stm32_bringup.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include - -#include "stm32.h" -#include "nucleo-f412zg.h" - -#ifdef CONFIG_STM32_OTGFS -# include "stm32_usbhost.h" -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_bringup - * - * Description: - * Perform architecture-specific initialization - * - * CONFIG_BOARD_LATE_INITIALIZE=y : - * Called from board_late_initialize(). - * - ****************************************************************************/ - -int stm32_bringup(void) -{ - int ret = OK; - -#if defined(CONFIG_STM32_OTGFS) && defined(CONFIG_USBHOST) - /* Initialize USB host operation. stm32_usbhost_initialize() starts a - * thread will monitor for USB connection and disconnection events. - */ - - ret = stm32_usbhost_initialize(); - if (ret != OK) - { - uerr("ERROR: Failed to initialize USB host: %d\n", ret); - return ret; - } -#endif - -#ifdef CONFIG_FS_PROCFS - /* Mount the procfs file system */ - - ret = nx_mount(NULL, STM32_PROCFS_MOUNTPOINT, "procfs", 0, NULL); - if (ret < 0) - { - ferr("ERROR: Failed to mount procfs at %s: %d\n", - STM32_PROCFS_MOUNTPOINT, ret); - } -#endif - - return ret; -} diff --git a/boards/arm/stm32/nucleo-f412zg/src/stm32_usb.c b/boards/arm/stm32/nucleo-f412zg/src/stm32_usb.c deleted file mode 100644 index d3eef5fcdc6c3..0000000000000 --- a/boards/arm/stm32/nucleo-f412zg/src/stm32_usb.c +++ /dev/null @@ -1,352 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f412zg/src/stm32_usb.c - * - * SPDX-License-Identifier: BSD-3-Clause - * SPDX-FileCopyrightText: 2017 Gregory Nutt. All rights reserved. - * SPDX-FileCopyrightText: 2017 Brian Webb. All rights reserved. - * SPDX-FileContributor: Gregory Nutt - * SPDX-FileContributor: Brian Webb - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -#include "up_internal.h" -#include "stm32.h" -#include "stm32_otgfs.h" -#include "nucleo-f412zg.h" - -#ifdef CONFIG_STM32_OTGFS - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#if !defined(CONFIG_USBDEV) && !defined(CONFIG_USBHOST) -# warning "CONFIG_STM32_OTGFS is enabled but neither CONFIG_USBDEV nor CONFIG_USBHOST" -#endif - -#ifndef CONFIG_STM32F411DISCO_USBHOST_PRIO -# define CONFIG_STM32F411DISCO_USBHOST_PRIO 100 -#endif - -#ifndef CONFIG_STM32F411DISCO_USBHOST_STACKSIZE -# define CONFIG_STM32F411DISCO_USBHOST_STACKSIZE 1024 -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -#ifdef CONFIG_USBHOST -static struct usbhost_connection_s *g_usbconn; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: usbhost_waiter - * - * Description: - * Wait for USB devices to be connected. - * - ****************************************************************************/ - -#ifdef CONFIG_USBHOST -static int usbhost_waiter(int argc, char *argv[]) -{ - struct usbhost_hubport_s *hport; - - uinfo("Running\n"); - for (; ; ) - { - /* Wait for the device to change state */ - - DEBUGVERIFY(CONN_WAIT(g_usbconn, &hport)); - uinfo("%s\n", hport->connected ? "connected" : "disconnected"); - - /* Did we just become connected? */ - - if (hport->connected) - { - /* Yes.. enumerate the newly connected device */ - - CONN_ENUMERATE(g_usbconn, hport); - } - } - - /* Keep the compiler from complaining */ - - return 0; -} -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_usbinitialize - * - * Description: - * Called from stm32_usbinitialize very early in initialization to setup - * USB-related GPIO pins for the STM32F411 Discovery board. - * - ****************************************************************************/ - -void stm32_usbinitialize(void) -{ - /* The OTG FS has an internal soft pull-up. - * No GPIO configuration is required. - */ - - /* Configure the OTG FS VBUS sensing GPIO, - * Power On, and Overcurrent GPIOs. - */ - -#ifdef CONFIG_STM32_OTGFS - stm32_configgpio(GPIO_OTGFS_VBUS); - stm32_configgpio(GPIO_OTGFS_PWRON); - stm32_configgpio(GPIO_OTGFS_OVER); -#endif -} - -/**************************************************************************** - * Name: stm32_usbhost_initialize - * - * Description: - * Called at application startup time to initialize the USB host - * functionality. This function will start a thread that will monitor - * for device connection/disconnection events. - * - ****************************************************************************/ - -#ifdef CONFIG_USBHOST -int stm32_usbhost_initialize(void) -{ - int ret; - - /* First, register all of the class drivers needed to support the drivers - * that we care about: - */ - - uinfo("Register class drivers\n"); - -#ifdef CONFIG_USBHOST_HUB - /* Initialize USB hub class support */ - - ret = usbhost_hub_initialize(); - if (ret < 0) - { - uerr("ERROR: usbhost_hub_initialize failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_USBHOST_MSC - /* Register the USB mass storage class class */ - - ret = usbhost_msc_initialize(); - if (ret != OK) - { - uerr("ERROR: Failed to register the mass storage class: %d\n", ret); - } -#endif - -#ifdef CONFIG_USBHOST_CDCACM - /* Register the CDC/ACM serial class */ - - ret = usbhost_cdcacm_initialize(); - if (ret != OK) - { - uerr("ERROR: Failed to register the CDC/ACM serial class: %d\n", ret); - } -#endif - -#ifdef CONFIG_USBHOST_HIDKBD - /* Initialize the HID keyboard class */ - - ret = usbhost_kbdinit(); - if (ret != OK) - { - uerr("ERROR: Failed to register the HID keyboard class\n"); - } -#endif - -#ifdef CONFIG_USBHOST_HIDMOUSE - /* Initialize the HID mouse class */ - - ret = usbhost_mouse_init(); - if (ret != OK) - { - uerr("ERROR: Failed to register the HID mouse class\n"); - } -#endif - -#ifdef CONFIG_USBHOST_XBOXCONTROLLER - /* Initialize the HID mouse class */ - - ret = usbhost_xboxcontroller_init(); - if (ret != OK) - { - uerr("ERROR: Failed to register the XBox Controller class\n"); - } -#endif - - /* Then get an instance of the USB host interface */ - - uinfo("Initialize USB host\n"); - g_usbconn = stm32_otgfshost_initialize(0); - if (g_usbconn) - { - /* Start a thread to handle device connection. */ - - uinfo("Start usbhost_waiter\n"); - - ret = kthread_create("usbhost", CONFIG_STM32F411DISCO_USBHOST_PRIO, - CONFIG_STM32F411DISCO_USBHOST_STACKSIZE, - usbhost_waiter, NULL); - return ret < 0 ? -ENOEXEC : OK; - } - - return -ENODEV; -} -#endif - -/**************************************************************************** - * Name: stm32_usbhost_vbusdrive - * - * Description: - * Enable/disable driving of VBUS 5V output. This function must be - * provided be each platform that implements the STM32 OTG FS host - * interface. - * - * "On-chip 5 V VBUS generation is not supported. For this reason, a charge - * pump or, if 5 V are available on the application board, a basic power - * switch, must be added externally to drive the 5 V VBUS line. The - * external charge pump can be driven by any GPIO output. When the - * application decides to power on VBUS using the chosen GPIO, it must - * also set the port power bit in the host port control and status - * register (PPWR bit in OTG_FS_HPRT). - * - * "The application uses this field to control power to this port, and - * the core clears this bit on an overcurrent condition." - * - * Input Parameters: - * iface - For future growth to handle multiple USB host interface. - * Should be zero. - * enable - true: enable VBUS power; false: disable VBUS power - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef CONFIG_USBHOST -void stm32_usbhost_vbusdrive(int iface, bool enable) -{ - DEBUGASSERT(iface == 0); - - if (enable) - { - /* Enable the Power Switch by driving the enable pin low */ - - stm32_gpiowrite(GPIO_OTGFS_PWRON, false); - } - else - { - /* Disable the Power Switch by driving the enable pin high */ - - stm32_gpiowrite(GPIO_OTGFS_PWRON, true); - } -} -#endif - -/**************************************************************************** - * Name: stm32_setup_overcurrent - * - * Description: - * Setup to receive an interrupt-level callback if an overcurrent condition - * is detected. - * - * Input Parameters: - * handler - New overcurrent interrupt handler - * arg - The argument provided for the interrupt handler - * - * Returned Value: - * Zero (OK) is returned on success. Otherwise, a negated errno value is - * returned to indicate the nature of the failure. - * - ****************************************************************************/ - -#ifdef CONFIG_USBHOST -int stm32_setup_overcurrent(xcpt_t handler, void *arg) -{ - return stm32_gpiosetevent(GPIO_OTGFS_OVER, true, true, true, handler, arg); -} -#endif - -/**************************************************************************** - * Name: stm32_usbsuspend - * - * Description: - * Board logic must provide the stm32_usbsuspend logic if the USBDEV driver - * is used. This function is called whenever the USB enters or leaves - * suspend mode. This is an opportunity for the board logic to shutdown - * clocks, power, etc. while the USB is suspended. - * - ****************************************************************************/ - -#ifdef CONFIG_USBDEV -void stm32_usbsuspend(struct usbdev_s *dev, bool resume) -{ - uinfo("resume: %d\n", resume); -} -#endif - -#endif /* CONFIG_STM32_OTGFS */ diff --git a/boards/arm/stm32/nucleo-f429zi/CMakeLists.txt b/boards/arm/stm32/nucleo-f429zi/CMakeLists.txt deleted file mode 100644 index 5d868f0710bba..0000000000000 --- a/boards/arm/stm32/nucleo-f429zi/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/nucleo-f429zi/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32/nucleo-f429zi/configs/netnsh/defconfig b/boards/arm/stm32/nucleo-f429zi/configs/netnsh/defconfig deleted file mode 100644 index 8af3bb56e5f71..0000000000000 --- a/boards/arm/stm32/nucleo-f429zi/configs/netnsh/defconfig +++ /dev/null @@ -1,81 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_STM32_FLASH_PREFETCH is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="nucleo-f429zi" -CONFIG_ARCH_BOARD_NUCLEO_F429ZI=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F429Z=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_ETH0_PHY_LAN8742A=y -CONFIG_FS_PROCFS=y -CONFIG_FS_PROCFS_REGISTER=y -CONFIG_FS_TMPFS=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_MM_REGIONS=2 -CONFIG_NET=y -CONFIG_NETDB_DNSCLIENT=y -CONFIG_NETINIT_DHCPC=y -CONFIG_NETINIT_NOMAC=y -CONFIG_NETUTILS_DISCOVER=y -CONFIG_NETUTILS_TELNETD=y -CONFIG_NETUTILS_WEBCLIENT=y -CONFIG_NET_ARP_IPIN=y -CONFIG_NET_BROADCAST=y -CONFIG_NET_ETH_PKTSIZE=1500 -CONFIG_NET_ICMP_SOCKET=y -CONFIG_NET_IGMP=y -CONFIG_NET_LOOPBACK=y -CONFIG_NET_ROUTE=y -CONFIG_NET_STATISTICS=y -CONFIG_NET_TCP=y -CONFIG_NET_UDP=y -CONFIG_NET_UDP_CHECKSUMS=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_NUCLEO_F429ZI_CONSOLE_VIRTUAL=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_LPWORK=y -CONFIG_SCHED_WAITPID=y -CONFIG_SPI=y -CONFIG_START_DAY=6 -CONFIG_START_MONTH=12 -CONFIG_START_YEAR=2011 -CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32_ETHMAC=y -CONFIG_STM32_FLASH_CONFIG_I=y -CONFIG_STM32_PHYADDR=0 -CONFIG_STM32_PHYSR=31 -CONFIG_STM32_PHYSR_100FD=0x0018 -CONFIG_STM32_PHYSR_100HD=0x0008 -CONFIG_STM32_PHYSR_10FD=0x0014 -CONFIG_STM32_PHYSR_10HD=0x0004 -CONFIG_STM32_PHYSR_ALTCONFIG=y -CONFIG_STM32_PHYSR_ALTMODE=0x001c -CONFIG_STM32_RMII_EXTCLK=y -CONFIG_SYSTEM_DHCPC_RENEW=y -CONFIG_SYSTEM_NSH=y -CONFIG_SYSTEM_PING=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART3_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/nucleo-f429zi/configs/nsh/defconfig b/boards/arm/stm32/nucleo-f429zi/configs/nsh/defconfig deleted file mode 100644 index d13b9d0031e44..0000000000000 --- a/boards/arm/stm32/nucleo-f429zi/configs/nsh/defconfig +++ /dev/null @@ -1,48 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_STM32_FLASH_PREFETCH is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="nucleo-f429zi" -CONFIG_ARCH_BOARD_NUCLEO_F429ZI=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F429Z=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_FS_PROCFS=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_MM_REGIONS=2 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_NUCLEO_F429ZI_CONSOLE_VIRTUAL=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_SPI=y -CONFIG_START_DAY=6 -CONFIG_START_MONTH=12 -CONFIG_START_YEAR=2011 -CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32_FLASH_CONFIG_I=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_PWR=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART3_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/nucleo-f429zi/configs/trace/defconfig b/boards/arm/stm32/nucleo-f429zi/configs/trace/defconfig deleted file mode 100644 index a82d50d95dd03..0000000000000 --- a/boards/arm/stm32/nucleo-f429zi/configs/trace/defconfig +++ /dev/null @@ -1,89 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_STM32_FLASH_PREFETCH is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="nucleo-f429zi" -CONFIG_ARCH_BOARD_NUCLEO_F429ZI=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F429Z=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_DRIVERS_NOTE=y -CONFIG_DRIVERS_NOTECTL=y -CONFIG_ETH0_PHY_LAN8742A=y -CONFIG_FS_PROCFS=y -CONFIG_FS_PROCFS_REGISTER=y -CONFIG_FS_TMPFS=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_MM_REGIONS=2 -CONFIG_NET=y -CONFIG_NETDB_DNSCLIENT=y -CONFIG_NETINIT_DHCPC=y -CONFIG_NETINIT_NOMAC=y -CONFIG_NETUTILS_DISCOVER=y -CONFIG_NETUTILS_TELNETD=y -CONFIG_NETUTILS_WEBCLIENT=y -CONFIG_NET_ARP_IPIN=y -CONFIG_NET_BROADCAST=y -CONFIG_NET_ETH_PKTSIZE=1500 -CONFIG_NET_ICMP_SOCKET=y -CONFIG_NET_IGMP=y -CONFIG_NET_LOOPBACK=y -CONFIG_NET_ROUTE=y -CONFIG_NET_STATISTICS=y -CONFIG_NET_TCP=y -CONFIG_NET_UDP=y -CONFIG_NET_UDP_CHECKSUMS=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_NUCLEO_F429ZI_CONSOLE_VIRTUAL=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_INSTRUMENTATION=y -CONFIG_SCHED_INSTRUMENTATION_DUMP=y -CONFIG_SCHED_INSTRUMENTATION_FILTER=y -CONFIG_SCHED_LPWORK=y -CONFIG_SCHED_WAITPID=y -CONFIG_SPI=y -CONFIG_STACK_USAGE=y -CONFIG_START_DAY=6 -CONFIG_START_MONTH=12 -CONFIG_START_YEAR=2011 -CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32_ETHMAC=y -CONFIG_STM32_FLASH_CONFIG_I=y -CONFIG_STM32_PHYADDR=0 -CONFIG_STM32_PHYSR=31 -CONFIG_STM32_PHYSR_100FD=0x0018 -CONFIG_STM32_PHYSR_100HD=0x0008 -CONFIG_STM32_PHYSR_10FD=0x0014 -CONFIG_STM32_PHYSR_10HD=0x0004 -CONFIG_STM32_PHYSR_ALTCONFIG=y -CONFIG_STM32_PHYSR_ALTMODE=0x001c -CONFIG_STM32_RMII_EXTCLK=y -CONFIG_SYSTEM_DHCPC_RENEW=y -CONFIG_SYSTEM_NSH=y -CONFIG_SYSTEM_PING=y -CONFIG_SYSTEM_TRACE=y -CONFIG_SYSTEM_TRACE_STACKSIZE=8192 -CONFIG_TASK_NAME_SIZE=32 -CONFIG_USART3_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/nucleo-f429zi/include/board.h b/boards/arm/stm32/nucleo-f429zi/include/board.h deleted file mode 100644 index 04829a544e878..0000000000000 --- a/boards/arm/stm32/nucleo-f429zi/include/board.h +++ /dev/null @@ -1,376 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f429zi/include/board.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __BOARDS_ARM_STM32F4_NUCLEO_F429ZI_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32F4_NUCLEO_F429ZI_INCLUDE_BOARD_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#ifndef __ASSEMBLY__ -# include -#endif - -/* Do not include STM32 F4 header files here */ - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Clocking *****************************************************************/ - -/* The STM32F4 Discovery board features a single 8MHz crystal. Space is - * provided for a 32kHz RTC backup crystal, but it is not stuffed. - * - * This is the canonical configuration: - * System Clock source : PLL (HSE) - * SYSCLK(Hz) : 180000000 Determined by PLL config - * HCLK(Hz) : 180000000 (STM32_RCC_CFGR_HPRE) - * AHB Prescaler : 1 (STM32_RCC_CFGR_HPRE) - * APB1 Prescaler : 4 (STM32_RCC_CFGR_PPRE1) - * APB2 Prescaler : 2 (STM32_RCC_CFGR_PPRE2) - * HSE Frequency(Hz) : 8000000 (STM32_BOARD_XTAL) - * PLLM : 8 (STM32_PLLCFG_PLLM) - * PLLN : 336 (STM32_PLLCFG_PLLN) - * PLLP : 2 (STM32_PLLCFG_PLLP) - * PLLQ : 7 (STM32_PLLCFG_PLLQ) - * Main regulator output voltage : Scale1 mode Needed for highspeed SYSCLK - * Flash Latency(WS) : 5 - * Prefetch Buffer : OFF - * Instruction cache : ON - * Data cache : ON - * Require 48MHz for USB OTG FS, : Enabled - * SDIO and RNG clock - */ - -/* HSI - 16 MHz RC factory-trimmed - * LSI - 32 KHz RC - * HSE - On-board crystal frequency is 8MHz - * LSE - 32.768 kHz - */ - -#define STM32_BOARD_XTAL 8000000ul - -#define STM32_HSI_FREQUENCY 16000000ul -#define STM32_LSI_FREQUENCY 32000 -#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL -#define STM32_LSE_FREQUENCY 32768 - -/* Main PLL Configuration. - * - * PLL source is HSE - * PLL_VCO = (STM32_HSE_FREQUENCY / PLLM) * PLLN - * = (8,000,000 / 8) * 336 - * = 336,000,000 - * SYSCLK = PLL_VCO / PLLP - * = 336,000,000 / 2 = 168,000,000 - * USB OTG FS, SDIO and RNG Clock - * = PLL_VCO / PLLQ - * = 48,000,000 - */ - -#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(8) -#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(336) -#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_2 -#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(7) - -#define STM32_SYSCLK_FREQUENCY 168000000ul - -/* AHB clock (HCLK) is SYSCLK (168MHz) */ - -#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ -#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY - -#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd4 /* PCLK1 = HCLK / 4 */ -#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/4) - -/* Timers driven from APB1 will be twice PCLK1 */ - -#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) - -/* APB2 clock (PCLK2) is HCLK/2 (84MHz) */ - -#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLKd2 /* PCLK2 = HCLK / 2 */ -#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/2) - -/* Timers driven from APB2 will be twice PCLK2 */ - -#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM9_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM10_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM11_CLKIN (2*STM32_PCLK2_FREQUENCY) - -/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx - * otherwise frequency is 2xAPBx. - * Note: TIM1,8 are on APB2, others on APB1 - */ - -#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM2_FREQUENCY (STM32_HCLK_FREQUENCY/2) -#define BOARD_TIM3_FREQUENCY (STM32_HCLK_FREQUENCY/2) -#define BOARD_TIM4_FREQUENCY (STM32_HCLK_FREQUENCY/2) -#define BOARD_TIM5_FREQUENCY (STM32_HCLK_FREQUENCY/2) -#define BOARD_TIM6_FREQUENCY (STM32_HCLK_FREQUENCY/2) -#define BOARD_TIM7_FREQUENCY (STM32_HCLK_FREQUENCY/2) -#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY - -/* DMA Channel/Stream Selections ********************************************/ - -/* Stream selections are arbitrary for now but might become important in the - * future if we set aside more DMA channels/streams. - * - * SDMMC DMA is on DMA2 - * - * SDMMC1 DMA - * DMAMAP_SDMMC1_1 = Channel 4, Stream 3 - * DMAMAP_SDMMC1_2 = Channel 4, Stream 6 - * - * SDMMC2 DMA - * DMAMAP_SDMMC2_1 = Channel 11, Stream 0 - * DMAMAP_SDMMC3_2 = Channel 11, Stream 5 - */ - -#define DMAMAP_SDMMC1 DMAMAP_SDMMC1_1 -#define DMAMAP_SDMMC2 DMAMAP_SDMMC2_1 - -/* FLASH wait states - * - * --------- ---------- ----------- - * VDD MAX SYSCLK WAIT STATES - * --------- ---------- ----------- - * 1.7-2.1 V 180 MHz 8 - * 2.1-2.4 V 216 MHz 9 - * 2.4-2.7 V 216 MHz 8 - * 2.7-3.6 V 216 MHz 7 - * --------- ---------- ----------- - */ - -#define BOARD_FLASH_WAITSTATES 7 - -/* LED definitions **********************************************************/ - -/* The Nucleo-144 board has numerous LEDs but only three, LD1 a Green LED, - * LD2 a Blue LED and LD3 a Red LED, that can be controlled by software. - * The following definitions assume the default Solder Bridges are installed. - * - * If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs - * in any way. - * The following definitions are used to access individual LEDs. - */ - -/* LED index values for use with board_userled() */ - -#define BOARD_LED1 0 -#define BOARD_LED2 1 -#define BOARD_LED3 2 -#define BOARD_NLEDS 3 - -#define BOARD_LED_GREEN BOARD_LED1 -#define BOARD_LED_BLUE BOARD_LED2 -#define BOARD_LED_RED BOARD_LED3 - -/* LED bits for use with board_userled_all() */ - -#define BOARD_LED1_BIT (1 << BOARD_LED1) -#define BOARD_LED2_BIT (1 << BOARD_LED2) -#define BOARD_LED3_BIT (1 << BOARD_LED3) - -/* If CONFIG_ARCH_LEDS is defined, the usage by the board port is defined in - * include/board.h and src/stm32_leds.c. The LEDs are used to encode - * OS-related events as follows: - * - * - * SYMBOL Meaning LED state - * Red Green Blue - * ---------------------- -------------------------- ------ ------ --- - */ - -#define LED_STARTED 0 /* NuttX has been started OFF OFF OFF */ -#define LED_HEAPALLOCATE 1 /* Heap has been allocated OFF OFF ON */ -#define LED_IRQSENABLED 2 /* Interrupts enabled OFF ON OFF */ -#define LED_STACKCREATED 3 /* Idle stack created OFF ON ON */ -#define LED_INIRQ 4 /* In an interrupt N/C N/C GLOW */ -#define LED_SIGNAL 5 /* In a signal handler N/C GLOW N/C */ -#define LED_ASSERTION 6 /* An assertion failed GLOW N/C GLOW */ -#define LED_PANIC 7 /* The system has crashed Blink OFF N/C */ -#define LED_IDLE 8 /* MCU is in sleep mode ON OFF OFF */ - -/* Thus if the Green LED is statically on, NuttX has successfully booted and - * is, apparently, running normally. If the Red LED is flashing at - * approximately 2Hz, then a fatal error has been detected and the system - * has halted. - */ - -/* Button definitions *******************************************************/ - -/* The STM32F4 Discovery supports one button: Pushbutton B1, labeled "User", - * is connected to GPIO PI11. - * A high value will be sensed when the button is depressed. - */ - -#define BUTTON_USER 0 -#define NUM_BUTTONS 1 -#define BUTTON_USER_BIT (1 << BUTTON_USER) - -/* Alternate function pin selections ****************************************/ - -/* TIM */ - -#define GPIO_TIM1_CH1OUT (GPIO_TIM1_CH1OUT_1|GPIO_SPEED_50MHz) -#define GPIO_TIM2_CH1OUT (GPIO_TIM2_CH1OUT_1|GPIO_SPEED_50MHz) -#define GPIO_TIM3_CH1OUT (GPIO_TIM3_CH1OUT_1|GPIO_SPEED_50MHz) -#define GPIO_TIM4_CH1OUT (GPIO_TIM4_CH1OUT_1|GPIO_SPEED_50MHz) - -#if defined(CONFIG_NUCLEO_F429ZI_CONSOLE_ARDUINO) - -/* USART6: - * - * These configurations assume that you are using a standard Arduio RS-232 - * shield with the serial interface with RX on pin D0 and TX on pin D1: - * - * -------- --------------- - * STM32F4 - * ARDUIONO FUNCTION GPIO - * -- ----- --------- ----- - * DO RX USART6_RX PG9 - * D1 TX USART6_TX PG14 - * -- ----- --------- ----- - */ - - # define GPIO_USART6_RX (GPIO_USART6_RX_2|GPIO_SPEED_100MHz) - # define GPIO_USART6_TX (GPIO_USART6_TX_2|GPIO_SPEED_100MHz) -#endif - -/* USART3: - * Use USART3 and the USB virtual COM port - */ - -#if defined(CONFIG_NUCLEO_F429ZI_CONSOLE_VIRTUAL) - # define GPIO_USART3_RX (GPIO_USART3_RX_3|GPIO_SPEED_100MHz) - # define GPIO_USART3_TX (GPIO_USART3_TX_3|GPIO_SPEED_100MHz) -#endif - -/* DMA channels *************************************************************/ - -/* ADC */ - -#define ADC1_DMA_CHAN DMAMAP_ADC1_1 -#define ADC2_DMA_CHAN DMAMAP_ADC2_1 -#define ADC3_DMA_CHAN DMAMAP_ADC3_1 - -/* SPI - * - * - * PA6 SPI1_MISO CN12-13 - * PA7 SPI1_MOSI CN12-15 - * PA5 SPI1_SCK CN12-11 - * - * PB14 SPI2_MISO CN12-28 - * PB15 SPI2_MOSI CN12-26 - * PB13 SPI2_SCK CN12-30 - * - * PB4 SPI3_MISO CN12-27 - * PB5 SPI3_MOSI CN12-29 - * PB3 SPI3_SCK CN12-31 - */ - -#define GPIO_SPI1_MISO (GPIO_SPI1_MISO_1|GPIO_SPEED_50MHz) -#define GPIO_SPI1_MOSI (GPIO_SPI1_MOSI_1|GPIO_SPEED_50MHz) -#define GPIO_SPI1_SCK (GPIO_SPI1_SCK_1|GPIO_SPEED_50MHz) - -#define GPIO_SPI2_MISO (GPIO_SPI2_MISO_1|GPIO_SPEED_50MHz) -#define GPIO_SPI2_MOSI (GPIO_SPI2_MOSI_1|GPIO_SPEED_50MHz) -#define GPIO_SPI2_SCK (GPIO_SPI2_SCK_3|GPIO_SPEED_50MHz) - -#define GPIO_SPI3_MISO (GPIO_SPI3_MISO_1|GPIO_SPEED_50MHz) -#define GPIO_SPI3_MOSI (GPIO_SPI3_MOSI_2|GPIO_SPEED_50MHz) -#define GPIO_SPI3_SCK (GPIO_SPI3_SCK_1|GPIO_SPEED_50MHz) - -/* I2C - * - * - * PB8 I2C1_SCL CN12-3 - * PB9 I2C1_SDA CN12-5 - - * PB10 I2C2_SCL CN11-51 - * PB11 I2C2_SDA CN12-18 - * - * PA8 I2C3_SCL CN12-23 - * PC9 I2C3_SDA CN12-1 - * - */ - -#define GPIO_I2C1_SCL (GPIO_I2C1_SCL_2|GPIO_SPEED_50MHz) -#define GPIO_I2C1_SDA (GPIO_I2C1_SDA_2|GPIO_SPEED_50MHz) - -#define GPIO_I2C2_SCL (GPIO_I2C2_SCL_1|GPIO_SPEED_50MHz) -#define GPIO_I2C2_SDA (GPIO_I2C2_SDA_1|GPIO_SPEED_50MHz) - -#define GPIO_I2C3_SCL (GPIO_I2C3_SCL_1|GPIO_SPEED_50MHz) -#define GPIO_I2C3_SDA (GPIO_I2C3_SDA_1|GPIO_SPEED_50MHz) - -/* The STM32 F4 connects to a SMSC LAN8742A PHY using these pins: - * - * STM32 F4 BOARD LAN8742A - * GPIO SIGNAL PIN NAME - * -------- ------------ ------------- - * PG11 RMII_TX_EN TXEN - * PG13 RMII_TXD0 TXD0 - * PB13 RMII_TXD1 TXD1 - * PC4 RMII_RXD0 RXD0/MODE0 - * PC5 RMII_RXD1 RXD1/MODE1 - * PG2 RMII_RXER RXER/PHYAD0 -- Not used - * PA7 RMII_CRS_DV CRS_DV/MODE2 - * PC1 RMII_MDC MDC - * PA2 RMII_MDIO MDIO - * N/A NRST nRST - * PA1 RMII_REF_CLK nINT/REFCLK0 - * N/A OSC_25M XTAL1/CLKIN - * - * The PHY address is either 0 or 1, depending on the state of PG2 on reset. - * PG2 is not controlled but appears to result in a PHY address of 0. - */ - -#define GPIO_ETH_RMII_TX_EN (GPIO_ETH_RMII_TX_EN_2|GPIO_SPEED_100MHz) -#define GPIO_ETH_RMII_TXD0 (GPIO_ETH_RMII_TXD0_2|GPIO_SPEED_100MHz) -#define GPIO_ETH_RMII_TXD1 (GPIO_ETH_RMII_TXD1_1|GPIO_SPEED_100MHz) - -#define GPIO_ETH_MDC (GPIO_ETH_MDC_0|GPIO_SPEED_100MHz) -#define GPIO_ETH_MDIO (GPIO_ETH_MDIO_0|GPIO_SPEED_100MHz) -#define GPIO_ETH_RMII_CRS_DV (GPIO_ETH_RMII_CRS_DV_0|GPIO_SPEED_100MHz) -#define GPIO_ETH_RMII_REF_CLK (GPIO_ETH_RMII_REF_CLK_0|GPIO_SPEED_100MHz) -#define GPIO_ETH_RMII_RXD0 (GPIO_ETH_RMII_RXD0_0|GPIO_SPEED_100MHz) -#define GPIO_ETH_RMII_RXD1 (GPIO_ETH_RMII_RXD1_0|GPIO_SPEED_100MHz) - -#endif /* __BOARDS_ARM_STM32F4_NUCLEO_F429ZI_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32/nucleo-f429zi/scripts/Make.defs b/boards/arm/stm32/nucleo-f429zi/scripts/Make.defs deleted file mode 100644 index 70114e47e2117..0000000000000 --- a/boards/arm/stm32/nucleo-f429zi/scripts/Make.defs +++ /dev/null @@ -1,41 +0,0 @@ -############################################################################ -# boards/arm/stm32/nucleo-f429zi/scripts/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/.config -include $(TOPDIR)/tools/Config.mk -include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs - -LDSCRIPT = ld.script -ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) - -ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 - -CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) -CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) -CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -AFLAGS := $(CFLAGS) -D__ASSEMBLY__ - -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections -LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32/nucleo-f429zi/scripts/kernel-space.ld b/boards/arm/stm32/nucleo-f429zi/scripts/kernel-space.ld deleted file mode 100644 index 43a2313798fd9..0000000000000 --- a/boards/arm/stm32/nucleo-f429zi/scripts/kernel-space.ld +++ /dev/null @@ -1,100 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f429zi/scripts/kernel-space.ld - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* NOTE: This depends on the memory.ld script having been included prior to - * this script. - */ - -OUTPUT_ARCH(arm) -EXTERN(_vectors) -ENTRY(_stext) -SECTIONS -{ - .text : { - _stext = ABSOLUTE(.); - *(.vectors) - *(.text .text.*) - *(.fixup) - *(.gnu.warning) - *(.rodata .rodata.*) - *(.gnu.linkonce.t.*) - *(.glue_7) - *(.glue_7t) - *(.got) - *(.gcc_except_table) - *(.gnu.linkonce.r.*) - _etext = ABSOLUTE(.); - } > kflash - - .init_section : { - _sinit = ABSOLUTE(.); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) - KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) - _einit = ABSOLUTE(.); - } > kflash - - .ARM.extab : { - *(.ARM.extab*) - } > kflash - - __exidx_start = ABSOLUTE(.); - .ARM.exidx : { - *(.ARM.exidx*) - } > kflash - - __exidx_end = ABSOLUTE(.); - - _eronly = ABSOLUTE(.); - - .data : { - _sdata = ABSOLUTE(.); - *(.data .data.*) - *(.gnu.linkonce.d.*) - CONSTRUCTORS - . = ALIGN(4); - _edata = ABSOLUTE(.); - } > ksram AT > kflash - - .bss : { - _sbss = ABSOLUTE(.); - *(.bss .bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - . = ALIGN(8); - _ebss = ABSOLUTE(.); - } > ksram - - /* Stabs debugging sections */ - - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_info 0 : { *(.debug_info) } - .debug_line 0 : { *(.debug_line) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_aranges 0 : { *(.debug_aranges) } -} diff --git a/boards/arm/stm32/nucleo-f429zi/scripts/ld.script b/boards/arm/stm32/nucleo-f429zi/scripts/ld.script deleted file mode 100644 index 7c53a58843444..0000000000000 --- a/boards/arm/stm32/nucleo-f429zi/scripts/ld.script +++ /dev/null @@ -1,133 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f429zi/scripts/ld.script - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* The STM32F429ZIT6 has 2048Kb of FLASH beginning at address 0x0800:0000 and - * 256Kb of SRAM. SRAM is split up into four blocks: - * - * 1) 112Kb of SRAM beginning at address 0x2000:0000 - * 2) 16Kb of SRAM beginning at address 0x2001:c000 - * 3) 64Kb of SRAM beginning at address 0x2002:0000 - * 4) 64Kb of CCM SRAM beginning at address 0x1000:0000 - * - * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 - * where the code expects to begin execution by jumping to the entry point in - * the 0x0800:0000 address - * range. - */ - -MEMORY -{ - flash (rx) : ORIGIN = 0x08000000, LENGTH = 2048K - sram (rwx) : ORIGIN = 0x20000000, LENGTH = 112K -} - -OUTPUT_ARCH(arm) -EXTERN(_vectors) -ENTRY(_stext) -SECTIONS -{ - .text : { - _stext = ABSOLUTE(.); - *(.vectors) - *(.text .text.*) - *(.fixup) - *(.gnu.warning) - *(.rodata .rodata.*) - *(.gnu.linkonce.t.*) - *(.glue_7) - *(.glue_7t) - *(.got) - *(.gcc_except_table) - *(.gnu.linkonce.r.*) - _etext = ABSOLUTE(.); - } > flash - - .init_section : ALIGN(4) { - _sinit = ABSOLUTE(.); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) - KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) - _einit = ABSOLUTE(.); - } > flash - - .ARM.extab : ALIGN(4) { - *(.ARM.extab*) - } > flash - - .ARM.exidx : ALIGN(4) { - __exidx_start = ABSOLUTE(.); - *(.ARM.exidx*) - __exidx_end = ABSOLUTE(.); - } > flash - - .tdata : { - _stdata = ABSOLUTE(.); - *(.tdata .tdata.* .gnu.linkonce.td.*); - _etdata = ABSOLUTE(.); - } > flash - - .tbss : { - _stbss = ABSOLUTE(.); - *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); - _etbss = ABSOLUTE(.); - } > flash - - _eronly = ABSOLUTE(.); - - /* The RAM vector table (if present) should lie at the beginning of SRAM */ - - .ram_vectors : { - *(.ram_vectors) - } > sram - - .data : ALIGN(4) { - _sdata = ABSOLUTE(.); - *(.data .data.*) - *(.gnu.linkonce.d.*) - CONSTRUCTORS - . = ALIGN(4); - _edata = ABSOLUTE(.); - } > sram AT > flash - - .bss : ALIGN(4) { - _sbss = ABSOLUTE(.); - *(.bss .bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - . = ALIGN(4); - _ebss = ABSOLUTE(.); - } > sram - - /* Stabs debugging sections. */ - - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_info 0 : { *(.debug_info) } - .debug_line 0 : { *(.debug_line) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_aranges 0 : { *(.debug_aranges) } -} diff --git a/boards/arm/stm32/nucleo-f429zi/scripts/memory.ld b/boards/arm/stm32/nucleo-f429zi/scripts/memory.ld deleted file mode 100644 index b1be62434027f..0000000000000 --- a/boards/arm/stm32/nucleo-f429zi/scripts/memory.ld +++ /dev/null @@ -1,88 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f429zi/scripts/memory.ld - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* The STM32F429ZIT has 2048Kb of FLASH beginning at address 0x0800:0000 and - * 256Kb of SRAM. SRAM is split up into four blocks: - * - * 1) 112KB of SRAM beginning at address 0x2000:0000 - * 2) 16KB of SRAM beginning at address 0x2001:c000 - * 3) 64KB of SRAM beginning at address 0x2002:0000 - * 4) 64KB of CCM SRAM beginning at address 0x1000:0000 - * - * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 - * where the code expects to begin execution by jumping to the entry point in - * the 0x0800:0000 address range. - * - * For MPU support, the kernel-mode NuttX section is assumed to be 128Kb of - * FLASH and 4Kb of SRAM. That is an excessive amount for the kernel which - * should fit into 64KB and, of course, can be optimized as needed (See - * also boards/arm/stm32/stm32f429i-disco/scripts/kernel-space.ld). Allowing the - * additional does permit addition debug instrumentation to be added to the - * kernel space without overflowing the partition. - * - * Alignment of the user space FLASH partition is also a critical factor: - * The user space FLASH partition will be spanned with a single region of - * size 2**n bytes. The alignment of the user-space region must be the same. - * As a consequence, as the user-space increases in size, the alignment - * requirement also increases. - * - * This alignment requirement means that the largest user space FLASH region - * you can have will be 512KB at it would have to be positioned at - * 0x08800000. If you change this address, don't forget to change the - * CONFIG_NUTTX_USERSPACE configuration setting to match and to modify - * the check in kernel/userspace.c. - * - * For the same reasons, the maximum size of the SRAM mapping is limited to - * 4KB. Both of these alignment limitations could be reduced by using - * multiple regions to map the FLASH/SDRAM range or perhaps with some - * clever use of subregions. - * - * A detailed memory map for the 112KB SRAM region is as follows: - * - * 0x20000 0000: Kernel .data region. Typical size: 0.1KB - * ------- ---- Kernel .bss region. Typical size: 1.8KB - * 0x20000 0800: Kernel IDLE thread stack (approximate). Size is - * determined by CONFIG_IDLETHREAD_STACKSIZE and - * adjustments for alignment. Typical is 1KB. - * ------- ---- Padded to 4KB - * 0x20000 1000: User .data region. Size is variable. - * ------- ---- User .bss region Size is variable. - * 0x20000 2000: Beginning of kernel heap. Size determined by - * CONFIG_MM_KERNEL_HEAPSIZE. - * ------- ---- Beginning of user heap. Can vary with other settings. - * 0x20001 c000: End+1 of CPU RAM - */ - -MEMORY -{ - /* 1024Kb FLASH */ - - kflash (rx) : ORIGIN = 0x08000000, LENGTH = 128K - uflash (rx) : ORIGIN = 0x08020000, LENGTH = 128K - xflash (rx) : ORIGIN = 0x08040000, LENGTH = 768K - - /* 112Kb of contiguous SRAM */ - - ksram (rwx) : ORIGIN = 0x20000000, LENGTH = 4K - usram (rwx) : ORIGIN = 0x20001000, LENGTH = 4K - xsram (rwx) : ORIGIN = 0x20002000, LENGTH = 104K -} diff --git a/boards/arm/stm32/nucleo-f429zi/scripts/user-space.ld b/boards/arm/stm32/nucleo-f429zi/scripts/user-space.ld deleted file mode 100644 index 03cd4598f1b61..0000000000000 --- a/boards/arm/stm32/nucleo-f429zi/scripts/user-space.ld +++ /dev/null @@ -1,114 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f429zi/scripts/user-space.ld - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* NOTE: This depends on the memory.ld script having been included prior to - * this script. - */ - -/* Make sure that the critical memory management functions are in user-space. - * the user heap memory manager will reside in user-space but be usable both - * by kernel- and user-space code - */ - -EXTERN(umm_initialize) -EXTERN(umm_addregion) - -EXTERN(malloc) -EXTERN(realloc) -EXTERN(zalloc) -EXTERN(free) - -OUTPUT_ARCH(arm) -SECTIONS -{ - .userspace : { - *(.userspace) - } > uflash - - .text : { - _stext = ABSOLUTE(.); - *(.text .text.*) - *(.fixup) - *(.gnu.warning) - *(.rodata .rodata.*) - *(.gnu.linkonce.t.*) - *(.glue_7) - *(.glue_7t) - *(.got) - *(.gcc_except_table) - *(.gnu.linkonce.r.*) - _etext = ABSOLUTE(.); - } > uflash - - .init_section : { - _sinit = ABSOLUTE(.); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) - KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) - _einit = ABSOLUTE(.); - } > uflash - - .ARM.extab : { - *(.ARM.extab*) - } > uflash - - __exidx_start = ABSOLUTE(.); - .ARM.exidx : { - *(.ARM.exidx*) - } > uflash - - __exidx_end = ABSOLUTE(.); - - _eronly = ABSOLUTE(.); - - .data : { - _sdata = ABSOLUTE(.); - *(.data .data.*) - *(.gnu.linkonce.d.*) - CONSTRUCTORS - . = ALIGN(4); - _edata = ABSOLUTE(.); - } > usram AT > uflash - - .bss : { - _sbss = ABSOLUTE(.); - *(.bss .bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - . = ALIGN(8); - _ebss = ABSOLUTE(.); - } > usram - - /* Stabs debugging sections */ - - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_info 0 : { *(.debug_info) } - .debug_line 0 : { *(.debug_line) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_aranges 0 : { *(.debug_aranges) } -} diff --git a/boards/arm/stm32/nucleo-f429zi/src/CMakeLists.txt b/boards/arm/stm32/nucleo-f429zi/src/CMakeLists.txt deleted file mode 100644 index cfcef00556c11..0000000000000 --- a/boards/arm/stm32/nucleo-f429zi/src/CMakeLists.txt +++ /dev/null @@ -1,73 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/nucleo-f429zi/src/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -set(SRCS stm32_boot.c) - -if(CONFIG_ARCH_LEDS) - list(APPEND SRCS stm32_autoleds.c) -else() - list(APPEND SRCS stm32_userleds.c) -endif() - -if(CONFIG_ARCH_BUTTONS) - list(APPEND SRCS stm32_buttons.c) -endif() - -if(CONFIG_DEV_GPIO) - list(APPEND SRCS stm32_gpio.c) -endif() - -if(CONFIG_SPI) - list(APPEND SRCS stm32_spi.c) -endif() - -if(CONFIG_ADC) - list(APPEND SRCS stm32_adc.c) -endif() - -if(CONFIG_PWM) - list(APPEND SRCS stm32_pwm.c) -endif() - -if(CONFIG_MMCSD) - list(APPEND SRCS stm32_sdio.c) -endif() - -if(CONFIG_STM32_OTGFS) - list(APPEND SRCS stm32_usb.c) -endif() - -if(CONFIG_STM32_BBSRAM) - list(APPEND SRCS stm32_bbsram.c) -endif() - -if(CONFIG_BOARDCTL_RESET) - list(APPEND SRCS stm32_reset.c) -endif() - -if(CONFIG_STM32_ROMFS) - list(APPEND SRCS stm32_romfs_initialize.c) -endif() - -target_sources(board PRIVATE ${SRCS}) - -set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/ld.script") diff --git a/boards/arm/stm32/nucleo-f429zi/src/Make.defs b/boards/arm/stm32/nucleo-f429zi/src/Make.defs deleted file mode 100644 index 2824447d2d6c8..0000000000000 --- a/boards/arm/stm32/nucleo-f429zi/src/Make.defs +++ /dev/null @@ -1,75 +0,0 @@ -############################################################################ -# boards/arm/stm32/nucleo-f429zi/src/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/Make.defs - -CSRCS = stm32_boot.c - -ifeq ($(CONFIG_ARCH_LEDS),y) -CSRCS += stm32_autoleds.c -else -CSRCS += stm32_userleds.c -endif - -ifeq ($(CONFIG_ARCH_BUTTONS),y) -CSRCS += stm32_buttons.c -endif - -ifeq ($(CONFIG_DEV_GPIO),y) -CSRCS += stm32_gpio.c -endif - -ifeq ($(CONFIG_SPI),y) -CSRCS += stm32_spi.c -endif - -ifeq ($(CONFIG_ADC),y) -CSRCS += stm32_adc.c -endif - -ifeq ($(CONFIG_PWM),y) -CSRCS += stm32_pwm.c -endif - -ifeq ($(CONFIG_MMCSD),y) -CSRCS += stm32_sdio.c -endif - -ifeq ($(CONFIG_STM32_OTGFS),y) -CSRCS += stm32_usb.c -endif - -ifeq ($(CONFIG_STM32_BBSRAM),y) -CSRCS += stm32_bbsram.c -endif - -ifeq ($(CONFIG_BOARDCTL_RESET),y) -CSRCS += stm32_reset.c -endif - -ifeq ($(CONFIG_STM32_ROMFS),y) -CSRCS += stm32_romfs_initialize.c -endif - -DEPPATH += --dep-path board -VPATH += :board -CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/nucleo-f429zi/src/stm32_adc.c b/boards/arm/stm32/nucleo-f429zi/src/stm32_adc.c deleted file mode 100644 index 25efe68db8b1c..0000000000000 --- a/boards/arm/stm32/nucleo-f429zi/src/stm32_adc.c +++ /dev/null @@ -1,169 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f429zi/src/stm32_adc.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include -#include - -#include "chip.h" -#include "stm32_gpio.h" -#include "stm32_adc.h" -#include "nucleo-144.h" - -#ifdef CONFIG_ADC - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -/* Up to 3 ADC interfaces are supported */ - -#if STM32F4_NADC < 3 -# undef CONFIG_STM32_ADC3 -#endif - -#if STM32F4_NADC < 2 -# undef CONFIG_STM32_ADC2 -#endif - -#if STM32F4_NADC < 1 -# undef CONFIG_STM32_ADC1 -#endif - -#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) || defined(CONFIG_STM32_ADC3) -#ifndef CONFIG_STM32_ADC1 -# warning "Channel information only available for ADC1" -#endif - -/* The number of ADC channels in the conversion list */ - -#define ADC1_NCHANNELS 1 - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* Identifying number of each ADC channel: Variable Resistor. - * - * {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 15}; - */ - -#ifdef CONFIG_STM32_ADC1 -static const uint8_t g_chanlist[ADC1_NCHANNELS] = - { - 3 - }; - -/* Configurations of pins used byte each ADC channels - * - * {GPIO_ADC1_IN1, GPIO_ADC1_IN2, GPIO_ADC1_IN3, GPIO_ADC1_IN4, - * GPIO_ADC1_IN5, GPIO_ADC1_IN6, GPIO_ADC1_IN7, GPIO_ADC1_IN8, - * GPIO_ADC1_IN9, GPIO_ADC1_IN10, GPIO_ADC1_IN11, GPIO_ADC1_IN12, - * GPIO_ADC1_IN13, GPIO_ADC1_IN15}; - */ - -static const uint32_t g_pinlist[ADC1_NCHANNELS] = - { - GPIO_ADC1_IN3 - }; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_adc_setup - * - * Description: - * Initialize ADC and register the ADC driver. - * - ****************************************************************************/ - -int stm32_adc_setup(void) -{ -#ifdef CONFIG_STM32_ADC1 - static bool initialized = false; - struct adc_dev_s *adc; - int ret; - int i; - - /* Check if we have already initialized */ - - if (!initialized) - { - /* Configure the pins as analog inputs for the selected channels */ - - for (i = 0; i < ADC1_NCHANNELS; i++) - { - if (g_pinlist[i] != 0) - { - stm32_configgpio(g_pinlist[i]); - } - } - - /* Call stm32_adcinitialize() to get an instance of the ADC interface */ - - adc = stm32_adc_initialize(1, g_chanlist, ADC1_NCHANNELS); - if (adc == NULL) - { - aerr("ERROR: Failed to get ADC interface\n"); - return -ENODEV; - } - - /* Register the ADC driver at "/dev/adc0" */ - - ret = adc_register("/dev/adc0", adc); - if (ret < 0) - { - aerr("ERROR: adc_register failed: %d\n", ret); - return ret; - } - - /* Now we are initialized */ - - initialized = true; - } - - return OK; -#else - return -ENOSYS; -#endif -} - -#endif /* CONFIG_STM32_ADC1 || CONFIG_STM32_ADC2 || CONFIG_STM32_ADC3 */ -#endif /* CONFIG_ADC */ diff --git a/boards/arm/stm32/nucleo-f429zi/src/stm32_autoleds.c b/boards/arm/stm32/nucleo-f429zi/src/stm32_autoleds.c deleted file mode 100644 index 9dedddc80a92a..0000000000000 --- a/boards/arm/stm32/nucleo-f429zi/src/stm32_autoleds.c +++ /dev/null @@ -1,170 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f429zi/src/stm32_autoleds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include - -#include -#include - -#include "stm32_gpio.h" -#include "nucleo-144.h" -#ifdef CONFIG_ARCH_LEDS - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* Indexed by BOARD_LED_ */ - -static const uint32_t g_ledmap[BOARD_NLEDS] = -{ - GPIO_LED_GREEN, - GPIO_LED_BLUE, - GPIO_LED_RED, -}; - -static bool g_initialized; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -static void phy_set_led(int led, bool state) -{ - /* Active High */ - - stm32_gpiowrite(g_ledmap[led], state); -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_autoled_initialize - ****************************************************************************/ - -void board_autoled_initialize(void) -{ - int i; - - /* Configure the LD1 GPIO for output. Initial state is OFF */ - - for (i = 0; i < nitems(g_ledmap); i++) - { - stm32_configgpio(g_ledmap[i]); - } -} - -/**************************************************************************** - * Name: board_autoled_on - ****************************************************************************/ - -void board_autoled_on(int led) -{ - switch (led) - { - default: - break; - - case LED_HEAPALLOCATE: - phy_set_led(BOARD_LED_BLUE, true); - break; - - case LED_IRQSENABLED: - phy_set_led(BOARD_LED_BLUE, false); - phy_set_led(BOARD_LED_GREEN, true); - break; - - case LED_STACKCREATED: - phy_set_led(BOARD_LED_GREEN, true); - phy_set_led(BOARD_LED_BLUE, true); - g_initialized = true; - break; - - case LED_INIRQ: - phy_set_led(BOARD_LED_BLUE, true); - break; - - case LED_SIGNAL: - phy_set_led(BOARD_LED_GREEN, true); - break; - - case LED_ASSERTION: - phy_set_led(BOARD_LED_RED, true); - phy_set_led(BOARD_LED_BLUE, true); - break; - - case LED_PANIC: - phy_set_led(BOARD_LED_RED, true); - break; - - case LED_IDLE : /* IDLE */ - phy_set_led(BOARD_LED_RED, true); - break; - } -} - -/**************************************************************************** - * Name: board_autoled_off - ****************************************************************************/ - -void board_autoled_off(int led) -{ - switch (led) - { - default: - break; - - case LED_SIGNAL: - phy_set_led(BOARD_LED_GREEN, false); - break; - - case LED_INIRQ: - phy_set_led(BOARD_LED_BLUE, false); - break; - - case LED_ASSERTION: - phy_set_led(BOARD_LED_RED, false); - phy_set_led(BOARD_LED_BLUE, false); - break; - - case LED_PANIC: - phy_set_led(BOARD_LED_RED, false); - break; - - case LED_IDLE : /* IDLE */ - phy_set_led(BOARD_LED_RED, false); - break; - } -} - -#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/nucleo-f429zi/src/stm32_bbsram.c b/boards/arm/stm32/nucleo-f429zi/src/stm32_bbsram.c deleted file mode 100644 index bef0916275945..0000000000000 --- a/boards/arm/stm32/nucleo-f429zi/src/stm32_bbsram.c +++ /dev/null @@ -1,519 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f429zi/src/stm32_bbsram.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include - -#include - -#include "arm_internal.h" -#include "stm32_bbsram.h" - -#include "nucleo-144.h" - -#ifdef CONFIG_STM32_BBSRAM - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -#define FREEZE_STR(s) #s -#define STRINGIFY(s) FREEZE_STR(s) -#define HARDFAULT_FILENO 3 -#define HARDFAULT_PATH BBSRAM_PATH""STRINGIFY(HARDFAULT_FILENO) -#define HARDFAULT_REBOOT_ FILENO 0 -#define HARDFAULT_REBOOT_PATH BBSRAM_PATH""STRINGIFY(HARDFAULT_REBOOT_FILENO) - -#define BBSRAM_SIZE_FN0 (sizeof(int)) -#define BBSRAM_SIZE_FN1 384 -#define BBSRAM_SIZE_FN2 384 -#define BBSRAM_SIZE_FN3 - 1 - -/* The following guides in the amount of the user and interrupt stack - * data we can save. The amount of storage left will dictate the actual - * number of entries of the user stack data saved. If it is too big - * It will be truncated by the call to stm32_bbsram_savepanic - */ -#define BBSRAM_HEADER_SIZE 20 /* This is an assumption */ -#define BBSRAM_USED ((4*BBSRAM_HEADER_SIZE)+ \ - (BBSRAM_SIZE_FN0+BBSRAM_SIZE_FN1+ \ - BBSRAM_SIZE_FN2)) -#define BBSRAM_REAMINING (STM32_BBSRAM_SIZE-BBSRAM_USED) -#if CONFIG_ARCH_INTERRUPTSTACK <= 3 -# define BBSRAM_NUMBER_STACKS 1 -#else -# define BBSRAM_NUMBER_STACKS 2 -#endif -#define BBSRAM_FIXED_ELEMENTS_SIZE (sizeof(info_t)) -#define BBSRAM_LEFTOVER (BBSRAM_REAMINING-\ - BBSRAM_FIXED_ELEMENTS_SIZE) - -#define CONFIG_ISTACK_SIZE (BBSRAM_LEFTOVER/BBSRAM_NUMBER_STACKS/ \ - sizeof(stack_word_t)) -#define CONFIG_USTACK_SIZE (BBSRAM_LEFTOVER/BBSRAM_NUMBER_STACKS/ \ - sizeof(stack_word_t)) - -/* The path to the Battery Backed up SRAM */ - -#define BBSRAM_PATH "/fs/bbr" - -/* The sizes of the files to create (-1) use rest of BBSRAM memory */ - -#define BSRAM_FILE_SIZES \ -{ \ - BBSRAM_SIZE_FN0, \ - BBSRAM_SIZE_FN1, \ - BBSRAM_SIZE_FN2, \ - BBSRAM_SIZE_FN3, \ - 0 \ -} - -/* For Assert keep this much of the file name */ - -#define MAX_FILE_PATH_LENGTH 40 - -#define HEADER_TIME_FMT "%Y-%m-%d-%H:%M:%S" -#define HEADER_TIME_FMT_NUM (2+ 0+ 0+ 0+ 0+ 0) -#define HEADER_TIME_FMT_LEN (((nitems(HEADER_TIME_FMT)-1) + \ - HEADER_TIME_FMT_NUM)) - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* Used for stack frame storage */ - -typedef uint32_t stack_word_t; - -/* Stack related data */ - -typedef struct -{ - uint32_t sp; - uint32_t top; - uint32_t size; -} _stack_t; - -typedef struct -{ - _stack_t user; -#if CONFIG_ARCH_INTERRUPTSTACK > 3 - _stack_t interrupt; -#endif -} stacks_t; - -/* Not Used for reference only */ - -typedef struct -{ - uint32_t r0; - uint32_t r1; - uint32_t r2; - uint32_t r3; - uint32_t r4; - uint32_t r5; - uint32_t r6; - uint32_t r7; - uint32_t r8; - uint32_t r9; - uint32_t r10; - uint32_t r11; - uint32_t r12; - uint32_t sp; - uint32_t lr; - uint32_t pc; - uint32_t xpsr; - uint32_t d0; - uint32_t d1; - uint32_t d2; - uint32_t d3; - uint32_t d4; - uint32_t d5; - uint32_t d6; - uint32_t d7; - uint32_t d8; - uint32_t d9; - uint32_t d10; - uint32_t d11; - uint32_t d12; - uint32_t d13; - uint32_t d14; - uint32_t d15; - uint32_t fpscr; - uint32_t sp_main; - uint32_t sp_process; - uint32_t apsr; - uint32_t ipsr; - uint32_t epsr; - uint32_t primask; - uint32_t basepri; - uint32_t faultmask; - uint32_t control; - uint32_t s0; - uint32_t s1; - uint32_t s2; - uint32_t s3; - uint32_t s4; - uint32_t s5; - uint32_t s6; - uint32_t s7; - uint32_t s8; - uint32_t s9; - uint32_t s10; - uint32_t s11; - uint32_t s12; - uint32_t s13; - uint32_t s14; - uint32_t s15; - uint32_t s16; - uint32_t s17; - uint32_t s18; - uint32_t s19; - uint32_t s20; - uint32_t s21; - uint32_t s22; - uint32_t s23; - uint32_t s24; - uint32_t s25; - uint32_t s26; - uint32_t s27; - uint32_t s28; - uint32_t s29; - uint32_t s30; - uint32_t s31; -} proc_regs_t; - -/* Flags to identify what is in the dump */ - -typedef enum -{ - REGS_PRESENT = 0x01, - USERSTACK_PRESENT = 0x02, - INTSTACK_PRESENT = 0x04, - INVALID_USERSTACK_PTR = 0x20, - INVALID_INTSTACK_PTR = 0x40, -} fault_flags_t; - -typedef struct -{ - fault_flags_t flags; /* What is in the dump */ - uintptr_t current_regs; /* Used to validate the dump */ - int lineno; /* __LINE__ to up_assert */ - pid_t pid; /* Process ID */ - uint32_t regs[XCPTCONTEXT_REGS]; /* Interrupt register save area */ - stack_t stacks; /* Stack info */ - char name[CONFIG_TASK_NAME_SIZE + 1]; /* Task name (with NULL - * terminator) */ - char filename[MAX_FILE_PATH_LENGTH]; /* the Last of chars in - * __FILE__ to up_assert */ -} info_t; - -typedef struct -{ - info_t info; /* The info */ -#if CONFIG_ARCH_INTERRUPTSTACK > 3 - /* The amount of stack data is compile time - * sized backed on what is left after the - * other BBSRAM files are defined - * The order is such that only the - * ustack should be truncated - */ - stack_word_t istack[CONFIG_USTACK_SIZE]; -#endif - stack_word_t ustack[CONFIG_ISTACK_SIZE]; -} fullcontext_t; - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -static uint8_t g_sdata[STM32_BBSRAM_SIZE]; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: hardfault_get_desc - ****************************************************************************/ - -static int hardfault_get_desc(struct bbsramd_s *desc) -{ - struct file filestruct; - int ret; - - ret = file_open(&filestruct, HARDFAULT_PATH, O_RDONLY); - if (ret < 0) - { - syslog(LOG_INFO, "stm32 bbsram: Failed to open Fault Log file [%s] " - "(%d)\n", HARDFAULT_PATH, ret); - } - else - { - ret = file_ioctl(&filestruct, STM32_BBSRAM_GETDESC_IOCTL, - (unsigned long)((uintptr_t)desc)); - file_close(&filestruct); - - if (ret < 0) - { - syslog(LOG_INFO, "stm32 bbsram:" - "Failed to get Fault Log descriptor" "(%d)\n", ret); - } - } - - return ret; -} - -/**************************************************************************** - * Name: copy_reverse - ****************************************************************************/ - -#if defined(CONFIG_STM32_SAVE_CRASHDUMP) -static void copy_reverse(stack_word_t *dest, stack_word_t *src, int size) -{ - while (size--) - { - *dest++ = *src--; - } -} -#endif /* CONFIG_STM32_SAVE_CRASHDUMP */ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_bbsram_int - ****************************************************************************/ - -int stm32_bbsram_int(void) -{ - int filesizes[CONFIG_STM32_BBSRAM_FILES + 1] = BSRAM_FILE_SIZES; - char buf[HEADER_TIME_FMT_LEN + 1]; - struct bbsramd_s desc; - int rv; - int state; - struct tm tt; - time_t time_sec; - - /* Using Battery Backed Up SRAM */ - - stm32_bbsraminitialize(BBSRAM_PATH, filesizes); - -#if defined(CONFIG_STM32_SAVE_CRASHDUMP) - /* Panic Logging in Battery Backed Up Files - * Do we have an hard fault in BBSRAM? - */ - - rv = hardfault_get_desc(&desc); - if (rv >= OK) - { - syslog(LOG_EMERG, "There is a hard fault logged.\n"); - state = (desc.lastwrite.tv_sec || desc.lastwrite.tv_nsec) ? OK : 1; - - syslog(LOG_INFO, "Fault Log info File No %d Length %d flags:0x%02x " - "state:%d\n", (unsigned int)desc.fileno, (unsigned int) desc.len, - (unsigned int)desc.flags, state); - - if (state == OK) - { - time_sec = desc.lastwrite.tv_sec + (desc.lastwrite.tv_nsec / 1e9); - gmtime_r(&time_sec, &tt); - strftime(buf, HEADER_TIME_FMT_LEN , HEADER_TIME_FMT , &tt); - - syslog(LOG_INFO, "Fault Logged on %s - Valid\n", buf); - } - - rv = nx_unlink(HARDFAULT_PATH); - if (rv < 0) - { - syslog(LOG_INFO, "stm32 bbsram: Failed to unlink Fault Log file" - "[%s] (%d)\n", HARDFAULT_PATH, rv); - } - } -#endif /* CONFIG_STM32_SAVE_CRASHDUMP */ - - return rv; -} - -/**************************************************************************** - * Name: board_crashdump - ****************************************************************************/ - -#if defined(CONFIG_STM32_SAVE_CRASHDUMP) -void board_crashdump(uintptr_t sp, struct tcb_s *tcb, - const char *filename, int lineno, - const char *msg, void *regs) -{ - fullcontext_t *pdump = (fullcontext_t *)&g_sdata; - int rv; - - enter_critical_section(); - - /* Zero out everything */ - - memset(pdump, 0, sizeof(fullcontext_t)); - - /* Save Info */ - - pdump->info.lineno = lineno; - - if (filename) - { - int offset = 0; - unsigned int len = strlen((char *)filename) + 1; - - if (len > sizeof(pdump->info.filename)) - { - offset = len - sizeof(pdump->info.filename); - } - - strlcpy(pdump->info.filename, (char *)&filename[offset], - sizeof(pdump->info.filename)); - } - - /* Save the value of the pointer for current_regs as debugging info. - * It should be NULL in case of an ASSERT and will aid in cross - * checking the validity of system memory at the time of the - * fault. - */ - - pdump->info.current_regs = (uintptr_t)running_regs(); - - /* Save Context */ - - strlcpy(pdump->info.name, get_task_name(tcb), sizeof(pdump->info.name)); - - pdump->info.pid = tcb->pid; - - if (up_interrupt_context()) - { - pdump->info.stacks.interrupt.sp = sp; - pdump->info.flags |= (REGS_PRESENT | USERSTACK_PRESENT | - INTSTACK_PRESENT); - memcpy(pdump->info.regs, running_regs(), - sizeof(pdump->info.regs)); - pdump->info.stacks.user.sp = pdump->info.regs[REG_R13]; - } - else - { - /* users context */ - - pdump->info.flags |= USERSTACK_PRESENT; - pdump->info.stacks.user.sp = sp; - } - - pdump->info.stacks.user.top = (uint32_t)tcb->stack_base_ptr + - tcb->adj_stack_size; - pdump->info.stacks.user.size = (uint32_t)tcb->adj_stack_size; - -#if CONFIG_ARCH_INTERRUPTSTACK > 3 - /* Get the limits on the interrupt stack memory */ - - pdump->info.stacks.interrupt.top = (uint32_t)g_intstacktop; - pdump->info.stacks.interrupt.size = (CONFIG_ARCH_INTERRUPTSTACK & ~3); - - /* If In interrupt Context save the interrupt stack data centered - * about the interrupt stack pointer - */ - - if ((pdump->info.flags & INTSTACK_PRESENT) != 0) - { - stack_word_t *ps = (stack_word_t *) pdump->info.stacks.interrupt.sp; - copy_reverse(pdump->istack, &ps[nitems(pdump->istack) / 2], - nitems(pdump->istack)); - } - - /* Is it Invalid? */ - - if (!(pdump->info.stacks.interrupt.sp - <= pdump->info.stacks.interrupt.top && - pdump->info.stacks.interrupt.sp > pdump->info.stacks.interrupt.top - - pdump->info.stacks.interrupt.size)) - { - pdump->info.flags |= INVALID_INTSTACK_PTR; - } - -#endif - /* If In interrupt context or User save the user stack data centered - * about the user stack pointer - */ - - if ((pdump->info.flags & USERSTACK_PRESENT) != 0) - { - stack_word_t *ps = (stack_word_t *) pdump->info.stacks.user.sp; - copy_reverse(pdump->ustack, &ps[nitems(pdump->ustack) / 2], - nitems(pdump->ustack)); - } - - /* Is it Invalid? */ - - if (!(pdump->info.stacks.user.sp <= pdump->info.stacks.user.top && - pdump->info.stacks.user.sp > pdump->info.stacks.user.top - - pdump->info.stacks.user.size)) - { - pdump->info.flags |= INVALID_USERSTACK_PTR; - } - - rv = stm32_bbsram_savepanic(HARDFAULT_FILENO, (uint8_t *)pdump, - sizeof(fullcontext_t)); - - /* Test if memory got wiped because of using _sdata */ - - if (rv == -ENXIO) - { - char *dead = "Memory wiped - dump not saved!"; - - while (*dead) - { - arm_lowputc(*dead++); - } - } - else if (rv == -ENOSPC) - { - /* hard fault again */ - - arm_lowputc('!'); - } -} -#endif /* CONFIG_STM32_SAVE_CRASHDUMP */ - -#endif /* CONFIG_STM32_BBSRAM */ diff --git a/boards/arm/stm32/nucleo-f429zi/src/stm32_boot.c b/boards/arm/stm32/nucleo-f429zi/src/stm32_boot.c deleted file mode 100644 index f6131a8308b42..0000000000000 --- a/boards/arm/stm32/nucleo-f429zi/src/stm32_boot.c +++ /dev/null @@ -1,252 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f429zi/src/stm32_boot.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include -#include - -#include -#include -#include -#include - -#include "arm_internal.h" -#include "nucleo-144.h" - -#ifdef CONFIG_STM32_ROMFS -#include "stm32_romfs.h" -#endif - -#ifdef CONFIG_SENSORS_AMG88XX -#include "stm32_amg88xx.h" -#endif - -#if defined(CONFIG_I2C) && defined(CONFIG_SYSTEM_I2CTOOL) -# include "stm32_i2c.h" -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_i2c_register - * - * Description: - * Register one I2C drivers for the I2C tool. - * - ****************************************************************************/ - -#if defined(CONFIG_I2C) && defined(CONFIG_SYSTEM_I2CTOOL) -static void stm32_i2c_register(int bus) -{ - struct i2c_master_s *i2c; - int ret; - - i2c = stm32_i2cbus_initialize(bus); - if (i2c == NULL) - { - syslog(LOG_ERR, "ERROR: Failed to get I2C%d interface\n", bus); - } - else - { - ret = i2c_register(i2c, bus); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: Failed to register I2C%d driver: %d\n", - bus, ret); - stm32_i2cbus_uninitialize(i2c); - } - } -} -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_boardinitialize - * - * Description: - * All STM32 architectures must provide the following entry point. - * This entry point is called early in the initialization - * after all memory has been configured and mapped but - * before any devices have been initialized. - * - ****************************************************************************/ - -void stm32_boardinitialize(void) -{ -#ifdef CONFIG_ARCH_LEDS - /* Configure on-board LEDs if LED support has been selected. */ - - board_autoled_initialize(); -#endif - -#if defined(CONFIG_STM32_OTGFS) || defined(CONFIG_STM32_HOST) - stm32_usbinitialize(); -#endif - -#if defined(CONFIG_SPI) - /* Configure SPI chip selects */ - - stm32_spidev_initialize(); -#endif -} - -/**************************************************************************** - * Name: board_late_initialize - * - * Description: - * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional - * initialization call will be performed in the boot-up sequence to a - * function called board_late_initialize(). board_late_initialize() - * will be called immediately after up_initialize() is called and - * just before the initial application is started. This additional - * initialization phase may be used, for example, to initialize - * board-specific device drivers. - * - ****************************************************************************/ - -#ifdef CONFIG_BOARD_LATE_INITIALIZE -void board_late_initialize(void) -{ - int ret; - -#ifdef CONFIG_FS_PROCFS - /* Mount the procfs file system */ - - ret = nx_mount(NULL, STM32_PROCFS_MOUNTPOINT, "procfs", 0, NULL); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: Failed to mount procfs at %s: %d\n", - STM32_PROCFS_MOUNTPOINT, ret); - } -#endif - -#ifdef CONFIG_STM32_ROMFS - /* Mount the romfs partition */ - - ret = stm32_romfs_initialize(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: Failed to mount romfs at %s: %d\n", - CONFIG_STM32_ROMFS_MOUNTPOINT, ret); - } -#endif - -#ifdef CONFIG_DEV_GPIO - /* Register the GPIO driver */ - - ret = stm32_gpio_initialize(); - if (ret < 0) - { - syslog(LOG_ERR, "Failed to initialize GPIO Driver: %d\n", ret); - return; - } -#endif - -#if !defined(CONFIG_ARCH_LEDS) && defined(CONFIG_USERLED_LOWER) - /* Register the LED driver */ - - ret = userled_lower_initialize(LED_DRIVER_PATH); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: userled_lower_initialize() failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_ADC - /* Initialize ADC and register the ADC driver. */ - - ret = stm32_adc_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_adc_setup failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_STM32_BBSRAM - /* Initialize battery-backed RAM */ - - stm32_bbsram_int(); -#endif - -#if defined(CONFIG_FAT_DMAMEMORY) - if (stm32_dma_alloc_init() < 0) - { - syslog(LOG_ERR, "DMA alloc FAILED"); - } -#endif - -#if defined(CONFIG_NUCLEO_SPI_TEST) - /* Create SPI interfaces */ - - ret = stm32_spidev_bus_test(); - if (ret != OK) - { - syslog(LOG_ERR, "ERROR: Failed to initialize SPI interfaces: %d\n", - ret); - return; - } -#endif - -#if defined(CONFIG_MMCSD) - /* Initialize the SDIO block driver */ - - ret = stm32_sdio_initialize(); - if (ret != OK) - { - ferr("ERROR: Failed to initialize MMC/SD driver: %d\n", ret); - return; - } -#endif - -#if defined(CONFIG_PWM) - /* Initialize PWM and register the PWM device */ - - ret = stm32_pwm_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_pwm_setup() failed: %d\n", ret); - } -#endif - -#if defined(CONFIG_I2C) && defined(CONFIG_SYSTEM_I2CTOOL) - stm32_i2c_register(1); -#endif - -#ifdef CONFIG_SENSORS_AMG88XX - board_amg88xx_initialize(1); -#endif - - UNUSED(ret); -} -#endif diff --git a/boards/arm/stm32/nucleo-f429zi/src/stm32_buttons.c b/boards/arm/stm32/nucleo-f429zi/src/stm32_buttons.c deleted file mode 100644 index 656f3e42fc7f8..0000000000000 --- a/boards/arm/stm32/nucleo-f429zi/src/stm32_buttons.c +++ /dev/null @@ -1,110 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f429zi/src/stm32_buttons.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include - -#include - -#include "stm32_gpio.h" -#include "nucleo-144.h" - -#ifdef CONFIG_ARCH_BUTTONS - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_button_initialize - * - * Description: - * board_button_initialize() must be called to initialize button resources. - * After that, board_buttons() may be called to collect the current state - * of all buttons or board_button_irq() may be called to register button - * interrupt handlers. - * - ****************************************************************************/ - -uint32_t board_button_initialize(void) -{ - stm32_configgpio(GPIO_BTN_USER); - return NUM_BUTTONS; -} - -/**************************************************************************** - * Name: board_buttons - ****************************************************************************/ - -uint32_t board_buttons(void) -{ - return stm32_gpioread(GPIO_BTN_USER) ? 1 : 0; -} - -/**************************************************************************** - * Button support. - * - * Description: - * board_button_initialize() must be called to initialize button resources. - * After that, board_buttons() may be called to collect the current - * state of all buttons or board_button_irq() may be called to register - * button interrupt handlers. - * - * After board_button_initialize() has been called, board_buttons() - * may be called to collect the state of all buttons. board_buttons() - * returns an 32-bit bit set with each bit associated with a button. - * See the BUTTON_*_BIT definitions in board.h for the meaning of each - * bit. - * - * board_button_irq() may be called to register an interrupt handler that - * will be called when a button is depressed or released. The ID value - * is a button enumeration value that uniquely identifies a button - * resource. See the BUTTON_* definitions in board.h for the meaning of - * enumeration value. - * - ****************************************************************************/ - -#ifdef CONFIG_ARCH_IRQBUTTONS -int board_button_irq(int id, xcpt_t irqhandler, void *arg) -{ - int ret = -EINVAL; - - if (id == BUTTON_USER) - { - ret = stm32_gpiosetevent(GPIO_BTN_USER, - true, true, true, - irqhandler, arg); - } - - return ret; -} -#endif -#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/stm32/nucleo-f429zi/src/stm32_gpio.c b/boards/arm/stm32/nucleo-f429zi/src/stm32_gpio.c deleted file mode 100644 index b1de5bf8c1663..0000000000000 --- a/boards/arm/stm32/nucleo-f429zi/src/stm32_gpio.c +++ /dev/null @@ -1,323 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f429zi/src/stm32_gpio.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include -#include - -#include - -#include "chip.h" -#include "stm32_gpio.h" -#include "nucleo-144.h" - -#if defined(CONFIG_DEV_GPIO) && !defined(CONFIG_GPIO_LOWER_HALF) - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -struct stm32gpio_dev_s -{ - struct gpio_dev_s gpio; - uint8_t id; -}; - -struct stm32gpint_dev_s -{ - struct stm32gpio_dev_s stm32gpio; - pin_interrupt_t callback; -}; - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -static int gpin_read(struct gpio_dev_s *dev, bool *value); -static int gpout_read(struct gpio_dev_s *dev, bool *value); -static int gpout_write(struct gpio_dev_s *dev, bool value); -static int gpint_read(struct gpio_dev_s *dev, bool *value); -static int gpint_attach(struct gpio_dev_s *dev, - pin_interrupt_t callback); -static int gpint_enable(struct gpio_dev_s *dev, bool enable); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -static const struct gpio_operations_s gpin_ops = -{ - .go_read = gpin_read, - .go_write = NULL, - .go_attach = NULL, - .go_enable = NULL, -}; - -static const struct gpio_operations_s gpout_ops = -{ - .go_read = gpout_read, - .go_write = gpout_write, - .go_attach = NULL, - .go_enable = NULL, -}; - -static const struct gpio_operations_s gpint_ops = -{ - .go_read = gpint_read, - .go_write = NULL, - .go_attach = gpint_attach, - .go_enable = gpint_enable, -}; - -#if BOARD_NGPIOIN > 0 -/* This array maps the GPIO pins used as INPUT */ - -static const uint32_t g_gpioinputs[BOARD_NGPIOIN] = -{ - GPIO_IN1, -}; - -static struct stm32gpio_dev_s g_gpin[BOARD_NGPIOIN]; -#endif - -#if BOARD_NGPIOOUT -/* This array maps the GPIO pins used as OUTPUT */ - -static const uint32_t g_gpiooutputs[BOARD_NGPIOOUT] = -{ - GPIO_OUT1, -}; - -static struct stm32gpio_dev_s g_gpout[BOARD_NGPIOOUT]; -#endif - -#if BOARD_NGPIOINT > 0 -/* This array maps the GPIO pins used as INTERRUPT INPUTS */ - -static const uint32_t g_gpiointinputs[BOARD_NGPIOINT] = -{ - GPIO_INT1, -}; - -static struct stm32gpint_dev_s g_gpint[BOARD_NGPIOINT]; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -static int stm32gpio_interrupt(int irq, void *context, void *arg) -{ - struct stm32gpint_dev_s *stm32gpint = - (struct stm32gpint_dev_s *)arg; - - DEBUGASSERT(stm32gpint != NULL && stm32gpint->callback != NULL); - gpioinfo("Interrupt! callback=%p\n", stm32gpint->callback); - - stm32gpint->callback(&stm32gpint->stm32gpio.gpio, - stm32gpint->stm32gpio.id); - return OK; -} - -static int gpin_read(struct gpio_dev_s *dev, bool *value) -{ - struct stm32gpio_dev_s *stm32gpio = - (struct stm32gpio_dev_s *)dev; - - DEBUGASSERT(stm32gpio != NULL && value != NULL); - DEBUGASSERT(stm32gpio->id < BOARD_NGPIOIN); - gpioinfo("Reading...\n"); - - *value = stm32_gpioread(g_gpioinputs[stm32gpio->id]); - return OK; -} - -static int gpout_read(struct gpio_dev_s *dev, bool *value) -{ - struct stm32gpio_dev_s *stm32gpio = - (struct stm32gpio_dev_s *)dev; - - DEBUGASSERT(stm32gpio != NULL && value != NULL); - DEBUGASSERT(stm32gpio->id < BOARD_NGPIOOUT); - gpioinfo("Reading...\n"); - - *value = stm32_gpioread(g_gpiooutputs[stm32gpio->id]); - return OK; -} - -static int gpout_write(struct gpio_dev_s *dev, bool value) -{ - struct stm32gpio_dev_s *stm32gpio = - (struct stm32gpio_dev_s *)dev; - - DEBUGASSERT(stm32gpio != NULL); - DEBUGASSERT(stm32gpio->id < BOARD_NGPIOOUT); - gpioinfo("Writing %d\n", (int)value); - - stm32_gpiowrite(g_gpiooutputs[stm32gpio->id], value); - return OK; -} - -static int gpint_read(struct gpio_dev_s *dev, bool *value) -{ - struct stm32gpint_dev_s *stm32gpint = - (struct stm32gpint_dev_s *)dev; - - DEBUGASSERT(stm32gpint != NULL && value != NULL); - DEBUGASSERT(stm32gpint->stm32gpio.id < BOARD_NGPIOINT); - gpioinfo("Reading int pin...\n"); - - *value = stm32_gpioread(g_gpiointinputs[stm32gpint->stm32gpio.id]); - return OK; -} - -static int gpint_attach(struct gpio_dev_s *dev, - pin_interrupt_t callback) -{ - struct stm32gpint_dev_s *stm32gpint = - (struct stm32gpint_dev_s *)dev; - - gpioinfo("Attaching the callback\n"); - - /* Make sure the interrupt is disabled */ - - stm32_gpiosetevent(g_gpiointinputs[stm32gpint->stm32gpio.id], false, - false, false, NULL, NULL); - - gpioinfo("Attach %p\n", callback); - stm32gpint->callback = callback; - return OK; -} - -static int gpint_enable(struct gpio_dev_s *dev, bool enable) -{ - struct stm32gpint_dev_s *stm32gpint = - (struct stm32gpint_dev_s *)dev; - - if (enable) - { - if (stm32gpint->callback != NULL) - { - gpioinfo("Enabling the interrupt\n"); - - /* Configure the interrupt for rising edge */ - - stm32_gpiosetevent(g_gpiointinputs[stm32gpint->stm32gpio.id], - true, false, false, stm32gpio_interrupt, - &g_gpint[stm32gpint->stm32gpio.id]); - } - } - else - { - gpioinfo("Disable the interrupt\n"); - stm32_gpiosetevent(g_gpiointinputs[stm32gpint->stm32gpio.id], - false, false, false, NULL, NULL); - } - - return OK; -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_gpio_initialize - * - * Description: - * Initialize GPIO drivers for use with /apps/examples/gpio - * - ****************************************************************************/ - -int stm32_gpio_initialize(void) -{ - int i; - int pincount = 0; - -#if BOARD_NGPIOIN > 0 - for (i = 0; i < BOARD_NGPIOIN; i++) - { - /* Setup and register the GPIO pin */ - - g_gpin[i].gpio.gp_pintype = GPIO_INPUT_PIN; - g_gpin[i].gpio.gp_ops = &gpin_ops; - g_gpin[i].id = i; - gpio_pin_register(&g_gpin[i].gpio, pincount); - - /* Configure the pin that will be used as input */ - - stm32_configgpio(g_gpioinputs[i]); - - pincount++; - } -#endif - -#if BOARD_NGPIOOUT > 0 - for (i = 0; i < BOARD_NGPIOOUT; i++) - { - /* Setup and register the GPIO pin */ - - g_gpout[i].gpio.gp_pintype = GPIO_OUTPUT_PIN; - g_gpout[i].gpio.gp_ops = &gpout_ops; - g_gpout[i].id = i; - gpio_pin_register(&g_gpout[i].gpio, pincount); - - /* Configure the pin that will be used as output */ - - stm32_gpiowrite(g_gpiooutputs[i], 0); - stm32_configgpio(g_gpiooutputs[i]); - - pincount++; - } -#endif - -#if BOARD_NGPIOINT > 0 - for (i = 0; i < BOARD_NGPIOINT; i++) - { - /* Setup and register the GPIO pin */ - - g_gpint[i].stm32gpio.gpio.gp_pintype = GPIO_INTERRUPT_PIN; - g_gpint[i].stm32gpio.gpio.gp_ops = &gpint_ops; - g_gpint[i].stm32gpio.id = i; - gpio_pin_register(&g_gpint[i].stm32gpio.gpio, pincount); - - /* Configure the pin that will be used as interrupt input */ - - stm32_configgpio(g_gpiointinputs[i]); - - pincount++; - } -#endif - - return 0; -} -#endif /* CONFIG_DEV_GPIO && !CONFIG_GPIO_LOWER_HALF */ diff --git a/boards/arm/stm32/nucleo-f429zi/src/stm32_pwm.c b/boards/arm/stm32/nucleo-f429zi/src/stm32_pwm.c deleted file mode 100644 index 53f1ec4ebd7d7..0000000000000 --- a/boards/arm/stm32/nucleo-f429zi/src/stm32_pwm.c +++ /dev/null @@ -1,149 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f429zi/src/stm32_pwm.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32_pwm.h" -#include "nucleo-144.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#define HAVE_PWM 1 -#ifndef CONFIG_PWM -# undef HAVE_PWM -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_pwm_setup - * - * Description: - * Initialize PWM and register the PWM device. - * - ****************************************************************************/ - -int stm32_pwm_setup(void) -{ -#ifdef HAVE_PWM - static bool initialized = false; - struct pwm_lowerhalf_s *pwm; - int ret; - - /* Have we already initialized? */ - - if (!initialized) - { - /* Call stm32_pwminitialize() to get an instance of the PWM interface */ - -#if defined(CONFIG_STM32_TIM1_PWM) - pwm = stm32_pwminitialize(1); - if (!pwm) - { - aerr("ERROR: Failed to get the STM32F4 PWM lower half\n"); - return -ENODEV; - } - - ret = pwm_register("/dev/pwm0", pwm); - if (ret < 0) - { - aerr("ERROR: pwm_register failed: %d\n", ret); - return ret; - } -#endif - -#if defined(CONFIG_STM32_TIM2_PWM) - pwm = stm32_pwminitialize(2); - if (!pwm) - { - aerr("ERROR: Failed to get the STM32F4 PWM lower half\n"); - return -ENODEV; - } - - ret = pwm_register("/dev/pwm1", pwm); - if (ret < 0) - { - aerr("ERROR: pwm_register failed: %d\n", ret); - return ret; - } -#endif - -#if defined(CONFIG_STM32_TIM3_PWM) - pwm = stm32_pwminitialize(3); - if (!pwm) - { - aerr("ERROR: Failed to get the STM32F4 PWM lower half\n"); - return -ENODEV; - } - - ret = pwm_register("/dev/pwm2", pwm); - if (ret < 0) - { - aerr("ERROR: pwm_register failed: %d\n", ret); - return ret; - } -#endif - -#if defined(CONFIG_STM32_TIM4_PWM) - pwm = stm32_pwminitialize(4); - if (!pwm) - { - aerr("ERROR: Failed to get the STM32F4 PWM lower half\n"); - return -ENODEV; - } - - ret = pwm_register("/dev/pwm3", pwm); - if (ret < 0) - { - aerr("ERROR: pwm_register failed: %d\n", ret); - return ret; - } - -#endif - /* Now we are initialized */ - - initialized = true; - } - - return OK; -#else - return -ENODEV; -#endif -} diff --git a/boards/arm/stm32/nucleo-f429zi/src/stm32_reset.c b/boards/arm/stm32/nucleo-f429zi/src/stm32_reset.c deleted file mode 100644 index 80a5399c8cd0f..0000000000000 --- a/boards/arm/stm32/nucleo-f429zi/src/stm32_reset.c +++ /dev/null @@ -1,64 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f429zi/src/stm32_reset.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#ifdef CONFIG_BOARDCTL_RESET - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_reset - * - * Description: - * Reset board. Support for this function is required by board-level - * logic if CONFIG_BOARDCTL_RESET is selected. - * - * Input Parameters: - * status - Status information provided with the reset event. This - * meaning of this status information is board-specific. If not - * used by a board, the value zero may be provided in calls to - * board_reset(). - * - * Returned Value: - * If this function returns, then it was not possible to power-off the - * board due to some constraints. The return value int this case is a - * board-specific reason for the failure to shutdown. - * - ****************************************************************************/ - -int board_reset(int status) -{ - up_systemreset(); - return 0; -} - -#endif /* CONFIG_BOARDCTL_RESET */ diff --git a/boards/arm/stm32/nucleo-f429zi/src/stm32_romfs.h b/boards/arm/stm32/nucleo-f429zi/src/stm32_romfs.h deleted file mode 100644 index bd2b62c985499..0000000000000 --- a/boards/arm/stm32/nucleo-f429zi/src/stm32_romfs.h +++ /dev/null @@ -1,63 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f429zi/src/stm32_romfs.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __BOARDS_ARM_STM32F4_NUCLEOF429ZI_SRC_STM32_ROMFS_H -#define __BOARDS_ARM_STM32F4_NUCLEOF429ZI_SRC_STM32_ROMFS_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#ifdef CONFIG_STM32_ROMFS - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#define ROMFS_SECTOR_SIZE 64 - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_romfs_initialize - * - * Description: - * Registers built-in ROMFS image as block device and mounts it. - * - * Returned Value: - * Zero (OK) on success, a negated errno value on error. - * - * Assumptions/Limitations: - * Memory addresses [romfs_data_begin .. romfs_data_end) should contain - * ROMFS volume data, as included in the assembly snippet above (l. 84). - * - ****************************************************************************/ - -int stm32_romfs_initialize(void); - -#endif /* CONFIG_STM32_ROMFS */ - -#endif /* __BOARDS_ARM_STM32F4_NUCLEOF429ZI_SRC_STM32_ROMFS_H */ diff --git a/boards/arm/stm32/nucleo-f429zi/src/stm32_romfs_initialize.c b/boards/arm/stm32/nucleo-f429zi/src/stm32_romfs_initialize.c deleted file mode 100644 index ac86209be361f..0000000000000 --- a/boards/arm/stm32/nucleo-f429zi/src/stm32_romfs_initialize.c +++ /dev/null @@ -1,141 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f429zi/src/stm32_romfs_initialize.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* This file provides contents of an optional ROMFS volume, mounted at boot */ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include - -#include -#include -#include "stm32_romfs.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#ifndef CONFIG_STM32_ROMFS -# error "CONFIG_STM32_ROMFS must be defined" -#else - -#ifndef CONFIG_STM32_ROMFS_IMAGEFILE -# error "CONFIG_STM32_ROMFS_IMAGEFILE must be defined" -#endif - -#ifndef CONFIG_STM32_ROMFS_DEV_MINOR -# error "CONFIG_STM32_ROMFS_DEV_MINOR must be defined" -#endif - -#ifndef CONFIG_STM32_ROMFS_MOUNTPOINT -# error "CONFIG_STM32_ROMFS_MOUNTPOINT must be defined" -#endif - -#define NSECTORS(size) (((size) + ROMFS_SECTOR_SIZE - 1)/ROMFS_SECTOR_SIZE) - -#define STR2(m) #m -#define STR(m) STR2(m) - -#define MKMOUNT_DEVNAME(m) "/dev/ram" STR(m) -#define MOUNT_DEVNAME MKMOUNT_DEVNAME(CONFIG_STM32_ROMFS_DEV_MINOR) - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -__asm__ ( - " .section .rodata, \"a\" \n" - " .balign 16 \n" - " .globl romfs_data_begin \n" - "romfs_data_begin: \n" - " .incbin " STR(CONFIG_STM32_ROMFS_IMAGEFILE)"\n" - " .balign " STR(ROMFS_SECTOR_SIZE) "\n" - " .globl romfs_data_end \n" - "romfs_data_end: \n" - ); - -extern const uint8_t romfs_data_begin[]; -extern const uint8_t romfs_data_end[]; - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_romfs_initialize - * - * Description: - * Registers the aboveincluded binary file as block device. - * Then mounts the block device as ROMFS filesystems. - * - * Returned Value: - * Zero (OK) on success, a negated errno value on error. - * - * Assumptions/Limitations: - * Memory addresses [romfs_data_begin .. romfs_data_end) should contain - * ROMFS volume data, as included in the assembly snippet above (l. 84). - * - ****************************************************************************/ - -int stm32_romfs_initialize(void) -{ - size_t romfs_data_len; - int ret; - - /* Create a ROM disk for the /etc filesystem */ - - romfs_data_len = romfs_data_end - romfs_data_begin; - - ret = romdisk_register(CONFIG_STM32_ROMFS_DEV_MINOR, romfs_data_begin, - NSECTORS(romfs_data_len), ROMFS_SECTOR_SIZE); - if (ret < 0) - { - ferr("ERROR: romdisk_register failed: %d\n", -ret); - return ret; - } - - /* Mount the file system */ - - finfo("Mounting ROMFS filesystem at target=%s with source=%s\n", - CONFIG_STM32_ROMFS_MOUNTPOINT, MOUNT_DEVNAME); - - ret = nx_mount(MOUNT_DEVNAME, CONFIG_STM32_ROMFS_MOUNTPOINT, - "romfs", MS_RDONLY, NULL); - if (ret < 0) - { - ferr("ERROR: nx_mount(%s,%s,romfs) failed: %d\n", - MOUNT_DEVNAME, CONFIG_STM32_ROMFS_MOUNTPOINT, ret); - return ret; - } - - return OK; -} - -#endif /* CONFIG_STM32_ROMFS */ diff --git a/boards/arm/stm32/nucleo-f429zi/src/stm32_sdio.c b/boards/arm/stm32/nucleo-f429zi/src/stm32_sdio.c deleted file mode 100644 index 48a4f79442036..0000000000000 --- a/boards/arm/stm32/nucleo-f429zi/src/stm32_sdio.c +++ /dev/null @@ -1,163 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f429zi/src/stm32_sdio.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include - -#include -#include - -#include "chip.h" -#include "nucleo-144.h" -#include "stm32_gpio.h" -#include "stm32_sdmmc.h" - -#ifdef CONFIG_MMCSD - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -/* Card detections requires card support and a card detection GPIO */ - -#define HAVE_NCD 1 -#if !defined(GPIO_SDMMC1_NCD) -# undef HAVE_NCD -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -static struct sdio_dev_s *g_sdio_dev; -#ifdef HAVE_NCD -static bool g_sd_inserted; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_ncd_interrupt - * - * Description: - * Card detect interrupt handler. - * - ****************************************************************************/ - -#ifdef HAVE_NCD -static int stm32_ncd_interrupt(int irq, void *context) -{ - bool present; - - present = !stm32_gpioread(GPIO_SDMMC1_NCD); - if (g_sdio_dev && present != g_sd_inserted) - { - sdio_mediachange(g_sdio_dev, present); - g_sd_inserted = present; - } - - return OK; -} -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_sdio_initialize - * - * Description: - * Initialize SDIO-based MMC/SD card support - * - ****************************************************************************/ - -int stm32_sdio_initialize(void) -{ - int ret; - -#ifdef HAVE_NCD - /* Configure the card detect GPIO */ - - stm32_configgpio(GPIO_SDMMC1_NCD); - - /* Register an interrupt handler for the card detect pin */ - - stm32_gpiosetevent(GPIO_SDMMC1_NCD, true, true, true, - stm32_ncd_interrupt, NULL); -#endif - - /* Mount the SDIO-based MMC/SD block driver - * First, get an instance of the SDIO interface - */ - - finfo("Initializing SDIO slot %d\n", SDIO_SLOTNO); - - g_sdio_dev = sdio_initialize(SDIO_SLOTNO); - if (!g_sdio_dev) - { - ferr("ERROR: Failed to initialize SDIO slot %d\n", SDIO_SLOTNO); - return -ENODEV; - } - - /* Now bind the SDIO interface to the MMC/SD driver */ - - finfo("Bind SDIO to the MMC/SD driver, minor=%d\n", SDIO_MINOR); - - ret = mmcsd_slotinitialize(SDIO_MINOR, g_sdio_dev); - if (ret != OK) - { - ferr("ERROR: Failed to bind SDIO to the MMC/SD driver: %d\n", ret); - return ret; - } - - finfo("Successfully bound SDIO to the MMC/SD driver\n"); - -#ifdef HAVE_NCD - /* Use SD card detect pin to check if a card is g_sd_inserted */ - - g_sd_inserted = !stm32_gpioread(GPIO_SDMMC1_NCD); - finfo("Card detect : %d\n", g_sd_inserted); - - sdio_mediachange(g_sdio_dev, g_sd_inserted); -#else - /* Assume that the SD card is inserted. What choice do we have? */ - - sdio_mediachange(g_sdio_dev, true); -#endif - - return OK; -} - -#endif /* HAVE_SDIO */ diff --git a/boards/arm/stm32/nucleo-f429zi/src/stm32_spi.c b/boards/arm/stm32/nucleo-f429zi/src/stm32_spi.c deleted file mode 100644 index 70e933f51ca08..0000000000000 --- a/boards/arm/stm32/nucleo-f429zi/src/stm32_spi.c +++ /dev/null @@ -1,496 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f429zi/src/stm32_spi.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include - -#include - -#include -#include - -#include "arm_internal.h" -#include "chip.h" -#include "stm32_gpio.h" -#include "stm32_spi.h" - -#include "nucleo-144.h" - -#if defined(CONFIG_SPI) - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#if defined(CONFIG_NUCLEO_SPI1_TEST) -# if defined(CONFIG_NUCLEO_SPI1_TEST_MODE0) -# define CONFIG_NUCLEO_SPI1_TEST_MODE SPIDEV_MODE0 -# elif defined(CONFIG_NUCLEO_SPI1_TEST_MODE1) -# define CONFIG_NUCLEO_SPI1_TEST_MODE SPIDEV_MODE1 -# elif defined(CONFIG_NUCLEO_SPI1_TEST_MODE2) -# define CONFIG_NUCLEO_SPI1_TEST_MODE SPIDEV_MODE2 -# elif defined(CONFIG_NUCLEO_SPI1_TEST_MODE3) -# define CONFIG_NUCLEO_SPI1_TEST_MODE SPIDEV_MODE3 -# else -# error "No CONFIG_NUCLEO_SPI1_TEST_MODEx defined" -# endif -#endif - -#if defined(CONFIG_NUCLEO_SPI2_TEST) -# if defined(CONFIG_NUCLEO_SPI2_TEST_MODE0) -# define CONFIG_NUCLEO_SPI2_TEST_MODE SPIDEV_MODE0 -# elif defined(CONFIG_NUCLEO_SPI2_TEST_MODE1) -# define CONFIG_NUCLEO_SPI2_TEST_MODE SPIDEV_MODE1 -# elif defined(CONFIG_NUCLEO_SPI2_TEST_MODE2) -# define CONFIG_NUCLEO_SPI2_TEST_MODE SPIDEV_MODE2 -# elif defined(CONFIG_NUCLEO_SPI2_TEST_MODE3) -# define CONFIG_NUCLEO_SPI2_TEST_MODE SPIDEV_MODE3 -# else -# error "No CONFIG_NUCLEO_SPI2_TEST_MODEx defined" -# endif -#endif - -#if defined(CONFIG_NUCLEO_SPI3_TEST) -# if defined(CONFIG_NUCLEO_SPI3_TEST_MODE0) -# define CONFIG_NUCLEO_SPI3_TEST_MODE SPIDEV_MODE0 -# elif defined(CONFIG_NUCLEO_SPI3_TEST_MODE1) -# define CONFIG_NUCLEO_SPI3_TEST_MODE SPIDEV_MODE1 -# elif defined(CONFIG_NUCLEO_SPI3_TEST_MODE2) -# define CONFIG_NUCLEO_SPI3_TEST_MODE SPIDEV_MODE2 -# elif defined(CONFIG_NUCLEO_SPI3_TEST_MODE3) -# define CONFIG_NUCLEO_SPI3_TEST_MODE SPIDEV_MODE3 -# else -# error "No CONFIG_NUCLEO_SPI3_TEST_MODEx defined" -# endif -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -#if defined(CONFIG_STM32_SPI1) -static const uint32_t g_spi1gpio[] = -{ -# if defined(GPIO_SPI1_CS0) - GPIO_SPI1_CS0, -# else - 0, -# endif -# if defined(GPIO_SPI1_CS1) - GPIO_SPI1_CS1, -# else - 0, -# endif -# if defined(GPIO_SPI1_CS2) - GPIO_SPI1_CS2, -# else - 0, -# endif -# if defined(GPIO_SPI1_CS3) - GPIO_SPI1_CS3 -# else - 0 -# endif -}; -#endif - -#if defined(CONFIG_STM32_SPI2) -static const uint32_t g_spi2gpio[] = -{ -# if defined(GPIO_SPI2_CS0) - GPIO_SPI2_CS0, -# else - 0, -# endif -# if defined(GPIO_SPI2_CS1) - GPIO_SPI2_CS1, -# else - 0, -# endif -# if defined(GPIO_SPI2_CS2) - GPIO_SPI2_CS2, -# else - 0, -# endif -# if defined(GPIO_SPI2_CS3) - GPIO_SPI2_CS3 -# else - 0 -# endif -}; -#endif - -#if defined(CONFIG_STM32_SPI3) -static const uint32_t g_spi3gpio[] = -{ -# if defined(GPIO_SPI3_CS0) - GPIO_SPI3_CS0, -# else - 0, -# endif -# if defined(GPIO_SPI3_CS1) - GPIO_SPI3_CS1, -# else - 0, -# endif -# if defined(GPIO_SPI3_CS2) - GPIO_SPI3_CS2, -# else - 0, -# endif -# if defined(GPIO_SPI3_CS3) - GPIO_SPI3_CS3 -# else - 0 -# endif -}; -#endif - -#if defined(CONFIG_NUCLEO_SPI_TEST) -# if defined(CONFIG_STM32_SPI1) -struct spi_dev_s *spi1; -# endif -# if defined(CONFIG_STM32_SPI2) -struct spi_dev_s *spi2; -# endif -# if defined(CONFIG_STM32_SPI3) -struct spi_dev_s *spi3; -# endif -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_spidev_initialize - * - * Description: - * Called to configure SPI chip select GPIO pins for the Nucleo-144 board. - * - ****************************************************************************/ - -void weak_function stm32_spidev_initialize(void) -{ - /* Configure SPI CS GPIO for output */ - -#if defined(CONFIG_STM32_SPI1) - for (int i = 0; i < nitems(g_spi1gpio); i++) - { - if (g_spi1gpio[i] != 0) - { - stm32_configgpio(g_spi1gpio[i]); - } - } -#endif - -#if defined(CONFIG_STM32_SPI2) - for (int i = 0; i < nitems(g_spi2gpio); i++) - { - if (g_spi2gpio[i] != 0) - { - stm32_configgpio(g_spi2gpio[i]); - } - } -#endif - -#if defined(CONFIG_STM32_SPI3) - for (int i = 0; i < nitems(g_spi3gpio); i++) - { - if (g_spi3gpio[i] != 0) - { - stm32_configgpio(g_spi3gpio[i]); - } - } -#endif -} - -/**************************************************************************** - * Name: stm32_spi1/2/3/4/5/6select and stm32_spi1/2/3/4/5/6status - * - * Description: - * The external functions, stm32_spi1/2/3/4/5/6select and - * stm32_spi1/2/3/4/5/6status must be provided by board-specific logic. - * They are implementations of the select and status methods of - * the SPI interface defined by struct spi_ops_s - * (see include/nuttx/spi/spi.h). All other methods - * (including stm32_spibus_initialize()) are provided by common - * STM32 logic. To use this common SPI logic on your board: - * - * 1. Provide logic in stm32_boardinitialize() to configure SPI chip select - * pins. - * 2. Provide stm32_spi1/2/3/4/5/6select() and stm32_spi1/2/3/4/5/6status() - * functions in your board-specific logic. These functions will - * perform chip selection and status operations using GPIOs in - * the way your board is configured. - * 3. Add a calls to stm32_spibus_initialize() in your low level - * application initialization logic - * 4. The handle returned by stm32_spibus_initialize() may then be - * used to bind the SPI driver to higher level logic (e.g., calling - * mmcsd_spislotinitialize(), for example, will bind the SPI - * driver to the SPI MMC/SD driver). - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_SPI1 -void stm32_spi1select(struct spi_dev_s *dev, - uint32_t devid, bool selected) -{ - uint32_t index = SPIDEVID_INDEX(devid); - - spiinfo("devid: %d CS: %s\n", - (int)devid, selected ? "assert" : "de-assert"); - - if (g_spi1gpio[index] != 0) - { - stm32_gpiowrite(g_spi1gpio[index], !selected); - } -} - -uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) -{ - return 0; -} -#endif - -#ifdef CONFIG_STM32_SPI2 -void stm32_spi2select(struct spi_dev_s *dev, - uint32_t devid, bool selected) -{ - uint32_t index = SPIDEVID_INDEX(devid); - - spiinfo("devid: %d CS: %s\n", - (int)devid, selected ? "assert" : "de-assert"); - - if (g_spi2gpio[index] != 0) - { - stm32_gpiowrite(g_spi2gpio[index], !selected); - } -} - -uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) -{ - return 0; -} -#endif - -#ifdef CONFIG_STM32_SPI3 -void stm32_spi3select(struct spi_dev_s *dev, - uint32_t devid, bool selected) -{ - uint32_t index = SPIDEVID_INDEX(devid); - - spiinfo("devid: %d CS: %s\n", - (int)devid, selected ? "assert" : "de-assert"); - - if (g_spi3gpio[index] != 0) - { - stm32_gpiowrite(g_spi3gpio[index], !selected); - } -} - -uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid) -{ - return 0; -} -#endif - -#ifdef CONFIG_STM32_SPI4 -void stm32_spi4select(struct spi_dev_s *dev, - uint32_t devid, bool selected) -{ - spiinfo("devid: %d CS: %s\n", - (int)devid, selected ? "assert" : "de-assert"); -} - -uint8_t stm32_spi4status(struct spi_dev_s *dev, uint32_t devid) -{ - return 0; -} -#endif - -#ifdef CONFIG_STM32_SPI5 -void stm32_spi5select(struct spi_dev_s *dev, - uint32_t devid, bool selected) -{ - spiinfo("devid: %d CS: %s\n", - (int)devid, selected ? "assert" : "de-assert"); -} - -uint8_t stm32_spi5status(struct spi_dev_s *dev, uint32_t devid) -{ - return 0; -} -#endif - -#ifdef CONFIG_STM32_SPI6 -void stm32_spi6select(struct spi_dev_s *dev, - uint32_t devid, bool selected) -{ - spiinfo("devid: %d CS: %s\n", - (int)devid, selected ? "assert" : "de-assert"); -} - -uint8_t stm32_spi6status(struct spi_dev_s *dev, uint32_t devid) -{ - return 0; -} -#endif - -/**************************************************************************** - * Name: stm32_spi1/2/3/4/5/6cmddata - * - * Description: - * Set or clear the SH1101A A0 or SD1306 D/C n bit to select data (true) - * or command (false). This function must be provided by platform-specific - * logic. This is an implementation of the cmddata method of the SPI - * interface defined by struct spi_ops_s (see include/nuttx/spi/spi.h). - * - * Input Parameters: - * - * spi - SPI device that controls the bus the device that requires the CMD/ - * DATA selection. - * devid - If there are multiple devices on the bus, this selects which one - * to select cmd or data. NOTE: This design restricts, for example, - * one one SPI display per SPI bus. - * cmd - true: select command; false: select data - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef CONFIG_SPI_CMDDATA -#ifdef CONFIG_STM32_SPI1 -int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) -{ - return -ENODEV; -} -#endif - -#ifdef CONFIG_STM32_SPI2 -int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) -{ - return -ENODEV; -} -#endif - -#ifdef CONFIG_STM32_SPI3 -int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) -{ - return -ENODEV; -} -#endif - -#ifdef CONFIG_STM32_SPI4 -int stm32_spi4cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) -{ - return -ENODEV; -} -#endif - -#ifdef CONFIG_STM32_SPI5 -int stm32_spi5cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) -{ - return -ENODEV; -} -#endif - -#ifdef CONFIG_STM32_SPI6 -int stm32_spi6cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) -{ - return -ENODEV; -} -#endif - -#endif /* CONFIG_SPI_CMDDATA */ - -#if defined(CONFIG_NUCLEO_SPI_TEST) -int stm32_spidev_bus_test(void) -{ - /* Configure and test SPI */ - - uint8_t *tx = (uint8_t *)CONFIG_NUCLEO_SPI_TEST_MESSAGE; - -#if defined(CONFIG_NUCLEO_SPI1_TEST) - spi1 = stm32_spibus_initialize(1); - - if (!spi1) - { - syslog(LOG_ERR, "ERROR Failed to initialize SPI port 1\n"); - return -ENODEV; - } - - /* Default SPI1 to NUCLEO_SPI1_FREQ and mode */ - - SPI_SETFREQUENCY(spi1, CONFIG_NUCLEO_SPI1_TEST_FREQ); - SPI_SETBITS(spi1, CONFIG_NUCLEO_SPI1_TEST_BITS); - SPI_SETMODE(spi1, CONFIG_NUCLEO_SPI1_TEST_MODE); - SPI_EXCHANGE(spi1, tx, NULL, nitems(CONFIG_NUCLEO_SPI_TEST_MESSAGE)); -#endif - -#if defined(CONFIG_NUCLEO_SPI2_TEST) - spi2 = stm32_spibus_initialize(2); - - if (!spi2) - { - syslog(LOG_ERR, "ERROR Failed to initialize SPI port 2\n"); - return -ENODEV; - } - - /* Default SPI2 to NUCLEO_SPI2_FREQ and mode */ - - SPI_SETFREQUENCY(spi2, CONFIG_NUCLEO_SPI2_TEST_FREQ); - SPI_SETBITS(spi2, CONFIG_NUCLEO_SPI2_TEST_BITS); - SPI_SETMODE(spi2, CONFIG_NUCLEO_SPI2_TEST_MODE); - SPI_EXCHANGE(spi2, tx, NULL, nitems(CONFIG_NUCLEO_SPI_TEST_MESSAGE)); -#endif - -#if defined(CONFIG_NUCLEO_SPI3_TEST) - spi3 = stm32_spibus_initialize(3); - - if (!spi3) - { - syslog(LOG_ERR, "ERROR Failed to initialize SPI port 2\n"); - return -ENODEV; - } - - /* Default SPI3 to NUCLEO_SPI3_FREQ and mode */ - - SPI_SETFREQUENCY(spi3, CONFIG_NUCLEO_SPI3_TEST_FREQ); - SPI_SETBITS(spi3, CONFIG_NUCLEO_SPI3_TEST_BITS); - SPI_SETMODE(spi3, CONFIG_NUCLEO_SPI3_TEST_MODE); - SPI_EXCHANGE(spi3, tx, NULL, nitems(CONFIG_NUCLEO_SPI_TEST_MESSAGE)); -#endif - - return OK; -} -#endif /* NUCLEO_SPI_TEST */ -#endif /* defined(CONFIG_SPI) */ diff --git a/boards/arm/stm32/nucleo-f429zi/src/stm32_usb.c b/boards/arm/stm32/nucleo-f429zi/src/stm32_usb.c deleted file mode 100644 index 7ad104a61f072..0000000000000 --- a/boards/arm/stm32/nucleo-f429zi/src/stm32_usb.c +++ /dev/null @@ -1,322 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f429zi/src/stm32_usb.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -#include "arm_internal.h" -#include "chip.h" -#include "stm32_gpio.h" -#include "stm32_otg.h" -#include "nucleo-144.h" - -#ifdef CONFIG_STM32_OTGFS - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#if defined(CONFIG_USBDEV) || defined(CONFIG_USBHOST) -# define HAVE_USB 1 -#else -# warning "CONFIG_STM32_OTGFS is enabled but neither CONFIG_USBDEV nor CONFIG_USBHOST" -# undef HAVE_USB -#endif - -#ifndef CONFIG_NUCLEO144_USBHOST_PRIO -# define CONFIG_NUCLEO144_USBHOST_PRIO 100 -#endif - -#ifndef CONFIG_NUCLEO_USBHOST_STACKSIZE -# define CONFIG_NUCLEO_USBHOST_STACKSIZE 1024 -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -#ifdef CONFIG_USBHOST -static struct usbhost_connection_s *g_usbconn; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: usbhost_waiter - * - * Description: - * Wait for USB devices to be connected. - * - ****************************************************************************/ - -#ifdef CONFIG_USBHOST -static int usbhost_waiter(int argc, char *argv[]) -{ - struct usbhost_hubport_s *hport; - - uinfo("Running\n"); - for (; ; ) - { - /* Wait for the device to change state */ - - DEBUGVERIFY(CONN_WAIT(g_usbconn, &hport)); - uinfo("%s\n", hport->connected ? "connected" : "disconnected"); - - /* Did we just become connected? */ - - if (hport->connected) - { - /* Yes.. enumerate the newly connected device */ - - CONN_ENUMERATE(g_usbconn, hport); - } - } - - /* Keep the compiler from complaining */ - - return 0; -} -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_usbinitialize - * - * Description: - * Called from stm32_usbinitialize very early in initialization - * to setup USB-related GPIO pins for the nucleo-144 board. - * - ****************************************************************************/ - -void stm32_usbinitialize(void) -{ - /* The OTG FS has an internal soft pull-up. - * No GPIO configuration is required - */ - - /* Configure the OTG FS VBUS sensing GPIO, - * Power On, and Overcurrent GPIOs - */ - -#ifdef CONFIG_STM32_OTGFS - stm32_configgpio(GPIO_OTGFS_VBUS); - stm32_configgpio(GPIO_OTGFS_PWRON); - stm32_configgpio(GPIO_OTGFS_OVER); -#endif -} - -/**************************************************************************** - * Name: stm32_usbhost_initialize - * - * Description: - * Called at application startup time to initialize the - * USB host functionality. This function will start a thread - * that will monitor for device connection/disconnection events. - * - ****************************************************************************/ - -#ifdef CONFIG_USBHOST -int stm32_usbhost_initialize(void) -{ - int ret; - - /* First, register all of the class drivers needed to support the drivers - * that we care about: - */ - - uinfo("Register class drivers\n"); - -#ifdef CONFIG_USBHOST_HUB - /* Initialize USB hub class support */ - - ret = usbhost_hub_initialize(); - if (ret < 0) - { - uerr("ERROR: usbhost_hub_initialize failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_USBHOST_MSC - /* Register the USB mass storage class class */ - - ret = usbhost_msc_initialize(); - if (ret != OK) - { - uerr("ERROR: Failed to register the mass storage class: %d\n", ret); - } -#endif - -#ifdef CONFIG_USBHOST_CDCACM - /* Register the CDC/ACM serial class */ - - ret = usbhost_cdcacm_initialize(); - if (ret != OK) - { - uerr("ERROR: Failed to register the CDC/ACM serial class: %d\n", ret); - } -#endif - -#ifdef CONFIG_USBHOST_HIDKBD - /* Initialize the HID keyboard class */ - - ret = usbhost_kbdinit(); - if (ret != OK) - { - uerr("ERROR: Failed to register the HID keyboard class\n"); - } -#endif - -#ifdef CONFIG_USBHOST_HIDMOUSE - /* Initialize the HID mouse class */ - - ret = usbhost_mouse_init(); - if (ret != OK) - { - uerr("ERROR: Failed to register the HID mouse class\n"); - } -#endif - - /* Then get an instance of the USB host interface */ - - uinfo("Initialize USB host\n"); - g_usbconn = stm32_otgfshost_initialize(0); - if (g_usbconn) - { - /* Start a thread to handle device connection. */ - - uinfo("Start usbhost_waiter\n"); - - ret = kthread_create("usbhost", CONFIG_STM32F4DISCO_USBHOST_PRIO, - CONFIG_STM32F4DISCO_USBHOST_STACKSIZE, - usbhost_waiter, NULL); - return ret < 0 ? -ENOEXEC : OK; - } - - return -ENODEV; -} -#endif - -/**************************************************************************** - * Name: stm32_usbhost_vbusdrive - * - * Description: - * Enable/disable driving of VBUS 5V output. This function - * must be provided be each platform that implements the - * STM32 OTG FS host interface - * - * "On-chip 5 V VBUS generation is not supported. For this reason, - * a charge pump or, if 5 V are available on the application board, - * a basic power switch, must be added externally to drive the 5 V - * VBUS line. The external charge pump can be driven by any GPIO - * output. When the application decides to power on VBUS using - * the chosen GPIO, it must also set the port power bit in the host port - * control and status register (PPWR bit in OTG_FS_HPRT). - * - * "The application uses this field to control power to this port, - * and the core clears this bit on an overcurrent condition." - * - * Input Parameters: - * iface - For future growth to handle multiple USB host interface. - * Should be zero. - * enable - true: enable VBUS power; false: disable VBUS power - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef CONFIG_USBHOST -void stm32_usbhost_vbusdrive(int iface, bool enable) -{ - DEBUGASSERT(iface == 0); - - /* Set the Power Switch by driving the active low enable pin */ - - stm32_gpiowrite(GPIO_OTGFS_PWRON, !enable); -} -#endif - -/**************************************************************************** - * Name: stm32_setup_overcurrent - * - * Description: - * Setup to receive an interrupt-level callback if an - * overcurrent condition is detected. - * - * Input Parameters: - * handler - New overcurrent interrupt handler - * arg - The argument provided for the interrupt handler - * - * Returned Value: - * Zero (OK) is returned on success. Otherwise, a negated errno - * value is returned to indicate the nature of the failure. - * - ****************************************************************************/ - -#ifdef CONFIG_USBHOST -int stm32_setup_overcurrent(xcpt_t handler, void *arg) -{ - return stm32_gpiosetevent(GPIO_OTGFS_OVER, true, true, true, handler, arg); -} -#endif - -/**************************************************************************** - * Name: stm32_usbsuspend - * - * Description: - * Board logic must provide the stm32_usbsuspend logic if the - * USBDEV driver is used. This function is called whenever the - * USB enters or leaves suspend mode. This is an opportunity - * for the board logic to shutdown clocks, power, etc. while the - * USB is suspended. - * - ****************************************************************************/ - -#ifdef CONFIG_USBDEV -void stm32_usbsuspend(struct usbdev_s *dev, bool resume) -{ - uinfo("resume: %d\n", resume); -} -#endif - -#endif /* CONFIG_STM32_OTGFS */ diff --git a/boards/arm/stm32/nucleo-f429zi/src/stm32_userleds.c b/boards/arm/stm32/nucleo-f429zi/src/stm32_userleds.c deleted file mode 100644 index 80d0f0247fc38..0000000000000 --- a/boards/arm/stm32/nucleo-f429zi/src/stm32_userleds.c +++ /dev/null @@ -1,128 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f429zi/src/stm32_userleds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include - -#include -#include - -#include "stm32_gpio.h" -#include "nucleo-144.h" - -#ifndef CONFIG_ARCH_LEDS - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* This array maps an LED number to GPIO pin configuration and is indexed by - * BOARD_LED_ - */ - -static const uint32_t g_ledcfg[BOARD_NLEDS] = -{ - GPIO_LED_GREEN, - GPIO_LED_BLUE, - GPIO_LED_RED, -}; - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_userled_initialize - * - * Description: - * If CONFIG_ARCH_LEDS is defined, then NuttX will control the on-board - * LEDs. If CONFIG_ARCH_LEDS is not defined, then the - * board_userled_initialize() is available to initialize the LED from user - * application logic. - * - ****************************************************************************/ - -uint32_t board_userled_initialize(void) -{ - int i; - - /* Configure LED1-3 GPIOs for output */ - - for (i = 0; i < nitems(g_ledcfg); i++) - { - stm32_configgpio(g_ledcfg[i]); - } - - return BOARD_NLEDS; -} - -/**************************************************************************** - * Name: board_userled - * - * Description: - * If CONFIG_ARCH_LEDS is defined, then NuttX will control the on-board - * LEDs. If CONFIG_ARCH_LEDS is not defined, then the board_userled() is - * available to control the LED from user application logic. - * - ****************************************************************************/ - -void board_userled(int led, bool ledon) -{ - if ((unsigned)led < nitems(g_ledcfg)) - { - stm32_gpiowrite(g_ledcfg[led], ledon); - } -} - -/**************************************************************************** - * Name: board_userled_all - * - * Description: - * If CONFIG_ARCH_LEDS is defined, then NuttX will control the on-board - * LEDs. If CONFIG_ARCH_LEDS is not defined, then the board_userled_all() - * is available to control the LED from user application logic. - * NOTE: since there is only a single LED on-board, this is function - * is not very useful. - * - ****************************************************************************/ - -void board_userled_all(uint32_t ledset) -{ - int i; - - /* Configure LED1-3 GPIOs for output */ - - for (i = 0; i < nitems(g_ledcfg); i++) - { - stm32_gpiowrite(g_ledcfg[i], (ledset & (1 << i)) != 0); - } -} - -#endif /* !CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/nucleo-f446re/CMakeLists.txt b/boards/arm/stm32/nucleo-f446re/CMakeLists.txt deleted file mode 100644 index 5b0efd703eb8b..0000000000000 --- a/boards/arm/stm32/nucleo-f446re/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/nucleo-f446re/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32/nucleo-f446re/Kconfig b/boards/arm/stm32/nucleo-f446re/Kconfig deleted file mode 100644 index 1e2e8b8e8b756..0000000000000 --- a/boards/arm/stm32/nucleo-f446re/Kconfig +++ /dev/null @@ -1,55 +0,0 @@ -# -# For a description of the syntax of this configuration file, -# see the file kconfig-language.txt in the NuttX tools repository. -# - -if ARCH_BOARD_NUCLEO_F446RE - -if SENSORS_QENCODER - -config NUCLEO_F446RE_QETIMER - int "Timer to use with QE encoder" - default 3 - -config NUCLEO_F446RE_QETIMER_TIM2_IHM08M1_MAP - bool "Use TIM2 QE pins to match IHM08M1 board pins" - default n - depends on STM32_TIM2_QE - -endif # SENSORS_QENCODER - -config NUCLEO_F446RE_AJOY_MINBUTTONS - bool "Minimal Joystick Buttons" - default STM32_USART1 - depends on INPUT_AJOYSTICK - ---help--- - The Itead Joystick shield supports analog X/Y position and up to 5 - buttons. Some of these buttons may conflict with other resources - (Button F, for example, conflicts with the default USART1 pin usage). - Selecting this option will return the number of buttons to the - minimal set: SELECT (joystick down), FIRE (BUTTON B), and JUMP - (BUTTON A). - -config STM32_ROMFS - bool "Automount baked-in ROMFS image" - default n - depends on FS_ROMFS - ---help--- - Select STM32_ROMFS_IMAGEFILE, STM32_ROMFS_DEV_MINOR, STM32_ROMFS_MOUNTPOINT - -config STM32_ROMFS_DEV_MINOR - int "Minor for the block device backing the data" - depends on STM32_ROMFS - default 64 - -config STM32_ROMFS_MOUNTPOINT - string "Mountpoint of the custom romfs image" - depends on STM32_ROMFS - default "/rom" - -config STM32_ROMFS_IMAGEFILE - string "ROMFS image file to include into build" - depends on STM32_ROMFS - default "../../../rom.img" - -endif # ARCH_BOARD_NUCLEO_F446RE diff --git a/boards/arm/stm32/nucleo-f446re/configs/adc/defconfig b/boards/arm/stm32/nucleo-f446re/configs/adc/defconfig deleted file mode 100644 index 20fde7d94c882..0000000000000 --- a/boards/arm/stm32/nucleo-f446re/configs/adc/defconfig +++ /dev/null @@ -1,56 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -# CONFIG_NSH_DISABLE_IFCONFIG is not set -# CONFIG_NSH_DISABLE_PS is not set -# CONFIG_STM32_FLASH_PREFETCH is not set -CONFIG_ADC=y -CONFIG_ANALOG=y -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="nucleo-f446re" -CONFIG_ARCH_BOARD_NUCLEO_F446RE=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F446R=y -CONFIG_ARCH_INTERRUPTSTACK=2048 -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=8499 -CONFIG_BUILTIN=y -CONFIG_EXAMPLES_ADC=y -CONFIG_EXAMPLES_ADC_GROUPSIZE=2 -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=131072 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=14 -CONFIG_START_MONTH=10 -CONFIG_START_YEAR=2014 -CONFIG_STM32_ADC1=y -CONFIG_STM32_ADC1_DMA=y -CONFIG_STM32_ADC1_SAMPLE_FREQUENCY=1 -CONFIG_STM32_DMA2=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_TIM1=y -CONFIG_STM32_TIM1_ADC=y -CONFIG_STM32_USART2=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/nucleo-f446re/configs/can/defconfig b/boards/arm/stm32/nucleo-f446re/configs/can/defconfig deleted file mode 100644 index f699366f92dc5..0000000000000 --- a/boards/arm/stm32/nucleo-f446re/configs/can/defconfig +++ /dev/null @@ -1,57 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -# CONFIG_NSH_DISABLE_IFCONFIG is not set -# CONFIG_NSH_DISABLE_PS is not set -# CONFIG_STM32_FLASH_PREFETCH is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="nucleo-f446re" -CONFIG_ARCH_BOARD_NUCLEO_F446RE=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F446R=y -CONFIG_ARCH_INTERRUPTSTACK=2048 -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=8499 -CONFIG_BUILTIN=y -CONFIG_EXAMPLES_CAN=y -CONFIG_EXAMPLES_CAN_NMSGS=100 -CONFIG_EXAMPLES_CAN_WRITE=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=131072 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_SPI=y -CONFIG_START_DAY=14 -CONFIG_START_MONTH=10 -CONFIG_START_YEAR=2014 -CONFIG_STM32_CAN1=y -CONFIG_STM32_CAN2=y -CONFIG_STM32_CAN_TSEG1=13 -CONFIG_STM32_CAN_TSEG2=2 -CONFIG_STM32_CRC=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_OTGFS=y -CONFIG_STM32_PWR=y -CONFIG_STM32_USART2=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/nucleo-f446re/configs/cansock/defconfig b/boards/arm/stm32/nucleo-f446re/configs/cansock/defconfig deleted file mode 100644 index 1ed153216c627..0000000000000 --- a/boards/arm/stm32/nucleo-f446re/configs/cansock/defconfig +++ /dev/null @@ -1,71 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_NET_ETHERNET is not set -# CONFIG_NET_IPv4 is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -# CONFIG_STM32_FLASH_PREFETCH is not set -CONFIG_ALLOW_BSD_COMPONENTS=y -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="nucleo-f446re" -CONFIG_ARCH_BOARD_NUCLEO_F446RE=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F446R=y -CONFIG_ARCH_INTERRUPTSTACK=2048 -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=8499 -CONFIG_BUILTIN=y -CONFIG_CANUTILS_CANDUMP=y -CONFIG_CANUTILS_CANSEND=y -CONFIG_CANUTILS_LIBCANUTILS=y -CONFIG_DEBUG_FULLOPT=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_FS_PROCFS=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_IOB_BUFSIZE=16 -CONFIG_IOB_NBUFFERS=1024 -CONFIG_LINE_MAX=64 -CONFIG_NET=y -CONFIG_NETDEV_IFINDEX=y -CONFIG_NETDEV_LATEINIT=y -CONFIG_NET_CAN=y -CONFIG_NET_CAN_EXTID=y -CONFIG_NET_SOCKOPTS=y -CONFIG_NET_STATISTICS=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_DISABLE_IFUPDOWN=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=131072 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_LPWORK=y -CONFIG_SCHED_LPWORKPRIORITY=176 -CONFIG_SCHED_WAITPID=y -CONFIG_SPI=y -CONFIG_START_DAY=14 -CONFIG_START_MONTH=10 -CONFIG_START_YEAR=2014 -CONFIG_STM32_CAN1=y -CONFIG_STM32_CAN_SOCKET=y -CONFIG_STM32_CAN_TSEG1=13 -CONFIG_STM32_CAN_TSEG2=2 -CONFIG_STM32_CRC=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_OTGFS=y -CONFIG_STM32_PWR=y -CONFIG_STM32_USART2=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/nucleo-f446re/configs/dac/defconfig b/boards/arm/stm32/nucleo-f446re/configs/dac/defconfig deleted file mode 100644 index 8b4215f22ec5d..0000000000000 --- a/boards/arm/stm32/nucleo-f446re/configs/dac/defconfig +++ /dev/null @@ -1,55 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -# CONFIG_NSH_DISABLE_IFCONFIG is not set -# CONFIG_NSH_DISABLE_PS is not set -# CONFIG_STM32_FLASH_PREFETCH is not set -CONFIG_ANALOG=y -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="nucleo-f446re" -CONFIG_ARCH_BOARD_NUCLEO_F446RE=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F446R=y -CONFIG_ARCH_INTERRUPTSTACK=2048 -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=8499 -CONFIG_BUILTIN=y -CONFIG_DAC=y -CONFIG_EXAMPLES_DAC=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=131072 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_SPI=y -CONFIG_START_DAY=14 -CONFIG_START_MONTH=10 -CONFIG_START_YEAR=2014 -CONFIG_STM32_CRC=y -CONFIG_STM32_DAC1=y -CONFIG_STM32_DAC1CH1=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_OTGFS=y -CONFIG_STM32_PWR=y -CONFIG_STM32_USART2=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/nucleo-f446re/configs/gpio/defconfig b/boards/arm/stm32/nucleo-f446re/configs/gpio/defconfig deleted file mode 100644 index 7436007b48370..0000000000000 --- a/boards/arm/stm32/nucleo-f446re/configs/gpio/defconfig +++ /dev/null @@ -1,51 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -# CONFIG_NSH_DISABLE_IFCONFIG is not set -# CONFIG_NSH_DISABLE_PS is not set -# CONFIG_STM32_FLASH_PREFETCH is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="nucleo-f446re" -CONFIG_ARCH_BOARD_NUCLEO_F446RE=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F446R=y -CONFIG_ARCH_INTERRUPTSTACK=2048 -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=8499 -CONFIG_BUILTIN=y -CONFIG_DEV_GPIO=y -CONFIG_EXAMPLES_GPIO=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=131072 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=14 -CONFIG_START_MONTH=10 -CONFIG_START_YEAR=2014 -CONFIG_STM32_CRC=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_OTGFS=y -CONFIG_STM32_PWR=y -CONFIG_STM32_USART2=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/nucleo-f446re/configs/ihm08m1_b16/defconfig b/boards/arm/stm32/nucleo-f446re/configs/ihm08m1_b16/defconfig deleted file mode 100644 index 2c152f31e767a..0000000000000 --- a/boards/arm/stm32/nucleo-f446re/configs/ihm08m1_b16/defconfig +++ /dev/null @@ -1,90 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_DISABLE_MQUEUE is not set -# CONFIG_DISABLE_PTHREAD is not set -CONFIG_ADC=y -CONFIG_ADC_FIFOSIZE=3 -CONFIG_ANALOG=y -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="nucleo-f446re" -CONFIG_ARCH_BOARD_COMMON=y -CONFIG_ARCH_BOARD_NUCLEO_F446RE=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F446R=y -CONFIG_ARCH_INTERRUPTSTACK=1024 -CONFIG_ARCH_IRQBUTTONS=y -CONFIG_ARMV7M_LIBM=y -CONFIG_BOARDCTL=y -CONFIG_BOARD_LOOPSPERMSEC=8499 -CONFIG_BOARD_STM32_IHM08M1=y -CONFIG_BOARD_STM32_IHM08M1_POT=y -CONFIG_BOARD_STM32_IHM08M1_VBUS=y -CONFIG_BUILTIN=y -CONFIG_DEBUG_FULLOPT=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_DEFAULT_SMALL=y -CONFIG_DEFAULT_TASK_STACKSIZE=1024 -CONFIG_EXAMPLES_FOC=y -CONFIG_EXAMPLES_FOC_ADC_MAX=4095 -CONFIG_EXAMPLES_FOC_ADC_VREF=3300 -CONFIG_EXAMPLES_FOC_CONTROL_STACKSIZE=2048 -CONFIG_EXAMPLES_FOC_FIXED16_INST=1 -CONFIG_EXAMPLES_FOC_HAVE_BUTTON=y -CONFIG_EXAMPLES_FOC_RAMP_ACC=200000 -CONFIG_EXAMPLES_FOC_RAMP_DEC=200000 -CONFIG_EXAMPLES_FOC_RAMP_THR=10000 -CONFIG_EXAMPLES_FOC_SETPOINT_ADC=y -CONFIG_EXAMPLES_FOC_VBUS_ADC=y -CONFIG_EXAMPLES_FOC_VBUS_SCALE=19152 -CONFIG_INDUSTRY_FOC=y -CONFIG_INDUSTRY_FOC_FIXED16=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INPUT=y -CONFIG_INPUT_BUTTONS=y -CONFIG_INPUT_BUTTONS_LOWER=y -CONFIG_INTELHEX_BINARY=y -CONFIG_LIBC_FLOATINGPOINT=y -CONFIG_LIBM=y -CONFIG_MOTOR=y -CONFIG_MOTOR_FOC=y -CONFIG_MOTOR_FOC_TRACE=y -CONFIG_MQ_MAXMSGSIZE=5 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_RAM_SIZE=16386 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=14 -CONFIG_START_MONTH=10 -CONFIG_START_YEAR=2014 -CONFIG_STM32_ADC1_ANIOC_TRIGGER=1 -CONFIG_STM32_ADC1_DMA=y -CONFIG_STM32_ADC1_DMA_CFG=1 -CONFIG_STM32_ADC1_INJECTED_CHAN=3 -CONFIG_STM32_DMA1=y -CONFIG_STM32_DMA2=y -CONFIG_STM32_FOC=y -CONFIG_STM32_FOC_FOC0=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_TIM1_CH1MODE=0 -CONFIG_STM32_TIM1_CH1NPOL=1 -CONFIG_STM32_TIM1_CH2MODE=0 -CONFIG_STM32_TIM1_CH2NPOL=1 -CONFIG_STM32_TIM1_CH3MODE=0 -CONFIG_STM32_TIM1_CH3NPOL=1 -CONFIG_STM32_TIM1_MODE=2 -CONFIG_STM32_TIM2=y -CONFIG_STM32_USART1=y -CONFIG_STM32_USART2=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART2_SERIAL_CONSOLE=y -CONFIG_USART2_TXDMA=y diff --git a/boards/arm/stm32/nucleo-f446re/configs/ihm08m1_f32/defconfig b/boards/arm/stm32/nucleo-f446re/configs/ihm08m1_f32/defconfig deleted file mode 100644 index 5b3e84da6ad8a..0000000000000 --- a/boards/arm/stm32/nucleo-f446re/configs/ihm08m1_f32/defconfig +++ /dev/null @@ -1,90 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_DISABLE_MQUEUE is not set -# CONFIG_DISABLE_PTHREAD is not set -CONFIG_ADC=y -CONFIG_ADC_FIFOSIZE=3 -CONFIG_ANALOG=y -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="nucleo-f446re" -CONFIG_ARCH_BOARD_COMMON=y -CONFIG_ARCH_BOARD_NUCLEO_F446RE=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F446R=y -CONFIG_ARCH_INTERRUPTSTACK=1024 -CONFIG_ARCH_IRQBUTTONS=y -CONFIG_ARMV7M_LIBM=y -CONFIG_BOARDCTL=y -CONFIG_BOARD_LOOPSPERMSEC=8499 -CONFIG_BOARD_STM32_IHM08M1=y -CONFIG_BOARD_STM32_IHM08M1_POT=y -CONFIG_BOARD_STM32_IHM08M1_VBUS=y -CONFIG_BUILTIN=y -CONFIG_DEBUG_FULLOPT=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_DEFAULT_SMALL=y -CONFIG_DEFAULT_TASK_STACKSIZE=1024 -CONFIG_EXAMPLES_FOC=y -CONFIG_EXAMPLES_FOC_ADC_MAX=4095 -CONFIG_EXAMPLES_FOC_ADC_VREF=3300 -CONFIG_EXAMPLES_FOC_CONTROL_STACKSIZE=2048 -CONFIG_EXAMPLES_FOC_FLOAT_INST=1 -CONFIG_EXAMPLES_FOC_HAVE_BUTTON=y -CONFIG_EXAMPLES_FOC_RAMP_ACC=200000 -CONFIG_EXAMPLES_FOC_RAMP_DEC=200000 -CONFIG_EXAMPLES_FOC_RAMP_THR=10000 -CONFIG_EXAMPLES_FOC_SETPOINT_ADC=y -CONFIG_EXAMPLES_FOC_VBUS_ADC=y -CONFIG_EXAMPLES_FOC_VBUS_SCALE=19152 -CONFIG_INDUSTRY_FOC=y -CONFIG_INDUSTRY_FOC_FLOAT=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INPUT=y -CONFIG_INPUT_BUTTONS=y -CONFIG_INPUT_BUTTONS_LOWER=y -CONFIG_INTELHEX_BINARY=y -CONFIG_LIBC_FLOATINGPOINT=y -CONFIG_LIBM=y -CONFIG_MOTOR=y -CONFIG_MOTOR_FOC=y -CONFIG_MOTOR_FOC_TRACE=y -CONFIG_MQ_MAXMSGSIZE=5 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_RAM_SIZE=16386 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=14 -CONFIG_START_MONTH=10 -CONFIG_START_YEAR=2014 -CONFIG_STM32_ADC1_ANIOC_TRIGGER=1 -CONFIG_STM32_ADC1_DMA=y -CONFIG_STM32_ADC1_DMA_CFG=1 -CONFIG_STM32_ADC1_INJECTED_CHAN=3 -CONFIG_STM32_DMA1=y -CONFIG_STM32_DMA2=y -CONFIG_STM32_FOC=y -CONFIG_STM32_FOC_FOC0=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_TIM1_CH1MODE=0 -CONFIG_STM32_TIM1_CH1NPOL=1 -CONFIG_STM32_TIM1_CH2MODE=0 -CONFIG_STM32_TIM1_CH2NPOL=1 -CONFIG_STM32_TIM1_CH3MODE=0 -CONFIG_STM32_TIM1_CH3NPOL=1 -CONFIG_STM32_TIM1_MODE=2 -CONFIG_STM32_TIM2=y -CONFIG_STM32_USART1=y -CONFIG_STM32_USART2=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART2_SERIAL_CONSOLE=y -CONFIG_USART2_TXDMA=y diff --git a/boards/arm/stm32/nucleo-f446re/configs/jumbo/defconfig b/boards/arm/stm32/nucleo-f446re/configs/jumbo/defconfig deleted file mode 100644 index e553a334ca160..0000000000000 --- a/boards/arm/stm32/nucleo-f446re/configs/jumbo/defconfig +++ /dev/null @@ -1,54 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -# CONFIG_NSH_DISABLE_IFCONFIG is not set -# CONFIG_NSH_DISABLE_PS is not set -# CONFIG_STM32_FLASH_PREFETCH is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="nucleo-f446re" -CONFIG_ARCH_BOARD_NUCLEO_F446RE=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F446R=y -CONFIG_ARCH_INTERRUPTSTACK=2048 -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=8499 -CONFIG_BUILTIN=y -CONFIG_EXAMPLES_PULSECOUNT=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=131072 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_SPI=y -CONFIG_START_DAY=14 -CONFIG_START_MONTH=10 -CONFIG_START_YEAR=2014 -CONFIG_STM32_CRC=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_OTGFS=y -CONFIG_STM32_PWR=y -CONFIG_STM32_TIM8=y -CONFIG_STM32_TIM8_PULSECOUNT=y -CONFIG_STM32_USART2=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_TESTING_OSTEST=y -CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/nucleo-f446re/configs/lcd/defconfig b/boards/arm/stm32/nucleo-f446re/configs/lcd/defconfig deleted file mode 100644 index 2c85afecb9f49..0000000000000 --- a/boards/arm/stm32/nucleo-f446re/configs/lcd/defconfig +++ /dev/null @@ -1,58 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -# CONFIG_NSH_DISABLE_IFCONFIG is not set -# CONFIG_NSH_DISABLE_PS is not set -# CONFIG_STM32_FLASH_PREFETCH is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="nucleo-f446re" -CONFIG_ARCH_BOARD_NUCLEO_F446RE=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F446R=y -CONFIG_ARCH_INTERRUPTSTACK=2048 -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=8499 -CONFIG_BUILTIN=y -CONFIG_DRIVERS_VIDEO=y -CONFIG_EXAMPLES_FB=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LCD=y -CONFIG_LCD_FRAMEBUFFER=y -CONFIG_LCD_ILI9225=y -CONFIG_LCD_PORTRAIT=y -CONFIG_LINE_MAX=64 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=131072 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_SPI_CMDDATA=y -CONFIG_START_DAY=14 -CONFIG_START_MONTH=10 -CONFIG_START_YEAR=2014 -CONFIG_STM32_CRC=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_OTGFS=y -CONFIG_STM32_PWR=y -CONFIG_STM32_SPI3=y -CONFIG_STM32_USART2=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART2_SERIAL_CONSOLE=y -CONFIG_VIDEO_FB=y diff --git a/boards/arm/stm32/nucleo-f446re/configs/nsh/defconfig b/boards/arm/stm32/nucleo-f446re/configs/nsh/defconfig deleted file mode 100644 index 1dd5ff9cb1776..0000000000000 --- a/boards/arm/stm32/nucleo-f446re/configs/nsh/defconfig +++ /dev/null @@ -1,51 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -# CONFIG_NSH_DISABLE_IFCONFIG is not set -# CONFIG_NSH_DISABLE_PS is not set -# CONFIG_STM32_FLASH_PREFETCH is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="nucleo-f446re" -CONFIG_ARCH_BOARD_NUCLEO_F446RE=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F446R=y -CONFIG_ARCH_INTERRUPTSTACK=2048 -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=8499 -CONFIG_BUILTIN=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=131072 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_SPI=y -CONFIG_START_DAY=14 -CONFIG_START_MONTH=10 -CONFIG_START_YEAR=2014 -CONFIG_STM32_CRC=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_OTGFS=y -CONFIG_STM32_PWR=y -CONFIG_STM32_USART2=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_TESTING_OSTEST=y -CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/nucleo-f446re/configs/pwm/defconfig b/boards/arm/stm32/nucleo-f446re/configs/pwm/defconfig deleted file mode 100644 index 64d5b681a44e8..0000000000000 --- a/boards/arm/stm32/nucleo-f446re/configs/pwm/defconfig +++ /dev/null @@ -1,55 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -# CONFIG_NSH_DISABLE_IFCONFIG is not set -# CONFIG_NSH_DISABLE_PS is not set -# CONFIG_STM32_FLASH_PREFETCH is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="nucleo-f446re" -CONFIG_ARCH_BOARD_NUCLEO_F446RE=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F446R=y -CONFIG_ARCH_INTERRUPTSTACK=2048 -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=8499 -CONFIG_BUILTIN=y -CONFIG_EXAMPLES_PWM=y -CONFIG_EXAMPLES_PWM_DEVPATH="/dev/pwm2" -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_PWM=y -CONFIG_RAM_SIZE=131072 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=14 -CONFIG_START_MONTH=10 -CONFIG_START_YEAR=2014 -CONFIG_STM32_CRC=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_OTGFS=y -CONFIG_STM32_PWR=y -CONFIG_STM32_TIM3=y -CONFIG_STM32_TIM3_CH1OUT=y -CONFIG_STM32_TIM3_PWM=y -CONFIG_STM32_USART2=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/nucleo-f446re/configs/qenco/defconfig b/boards/arm/stm32/nucleo-f446re/configs/qenco/defconfig deleted file mode 100644 index d0da232ae1bc8..0000000000000 --- a/boards/arm/stm32/nucleo-f446re/configs/qenco/defconfig +++ /dev/null @@ -1,50 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="nucleo-f446re" -CONFIG_ARCH_BOARD_COMMON=y -CONFIG_ARCH_BOARD_NUCLEO_F446RE=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F446R=y -CONFIG_ARCH_INTERRUPTSTACK=1024 -CONFIG_ARCH_IRQPRIO=y -CONFIG_BOARD_LOOPSPERMSEC=8499 -CONFIG_BUILTIN=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_EXAMPLES_QENCODER=y -CONFIG_EXAMPLES_QENCODER_HAVE_MAXPOS=y -CONFIG_EXAMPLES_QENCODER_MAXPOS=8192 -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_MQ_MAXMSGSIZE=5 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NUCLEO_F446RE_QETIMER=2 -CONFIG_NUCLEO_F446RE_QETIMER_TIM2_IHM08M1_MAP=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=16386 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_SENSORS=y -CONFIG_SENSORS_QENCODER=y -CONFIG_START_DAY=14 -CONFIG_START_MONTH=10 -CONFIG_START_YEAR=2014 -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_QENCODER_DISABLE_EXTEND16BTIMERS=y -CONFIG_STM32_QENCODER_SAMPLE_FDTS_2=y -CONFIG_STM32_TIM2=y -CONFIG_STM32_TIM2_QE=y -CONFIG_STM32_TIM2_QEPSC=0 -CONFIG_STM32_USART2=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/nucleo-f446re/configs/systemview/defconfig b/boards/arm/stm32/nucleo-f446re/configs/systemview/defconfig deleted file mode 100644 index 01ea37491e5ab..0000000000000 --- a/boards/arm/stm32/nucleo-f446re/configs/systemview/defconfig +++ /dev/null @@ -1,51 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_DRIVERS_NOTERAM is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -# CONFIG_NSH_DISABLE_IFCONFIG is not set -# CONFIG_NSH_DISABLE_PS is not set -# CONFIG_STM32_FLASH_PREFETCH is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="nucleo-f446re" -CONFIG_ARCH_BOARD_NUCLEO_F446RE=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F446R=y -CONFIG_ARCH_INTERRUPTSTACK=2048 -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=8499 -CONFIG_BUILTIN=y -CONFIG_DRIVERS_NOTE=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=131072 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_INSTRUMENTATION=y -CONFIG_SCHED_INSTRUMENTATION_IRQHANDLER=y -CONFIG_SCHED_WAITPID=y -CONFIG_SEGGER_SYSVIEW=y -CONFIG_START_DAY=14 -CONFIG_START_MONTH=10 -CONFIG_START_YEAR=2014 -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_USART2=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=32 -CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/nucleo-f446re/include/board.h b/boards/arm/stm32/nucleo-f446re/include/board.h deleted file mode 100644 index 3e4b1ed17570c..0000000000000 --- a/boards/arm/stm32/nucleo-f446re/include/board.h +++ /dev/null @@ -1,444 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f446re/include/board.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __BOARDS_ARM_STM32_NUCLEO_F446RE_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32_NUCLEO_F446RE_INCLUDE_BOARD_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#ifndef __ASSEMBLY__ -# include -#endif - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Clocking *****************************************************************/ - -/* The NUCLEOF446RE supports both HSE and LSE crystals (X2 and X3). - * However, as shipped, the X2 and X3 crystals are not populated. - * Therefore the Nucleo-FF446RE will need to run off the 16MHz HSI clock. - * - * System Clock source : PLL (HSI) - * SYSCLK(Hz) : 180000000 Determined by PLL config - * HCLK(Hz) : 180000000 (STM32_RCC_CFGR_HPRE) - * AHB Prescaler : 1 (STM32_RCC_CFGR_HPRE) - * APB1 Prescaler : 2 (STM32_RCC_CFGR_PPRE1) - * APB2 Prescaler : 1 (STM32_RCC_CFGR_PPRE2) - * HSI Frequency(Hz) : 16000000 (nominal) - * PLLM : 8 (STM32_PLLCFG_PLLM) - * PLLN : 216 (STM32_PLLCFG_PLLN) - * PLLP : 4 (STM32_PLLCFG_PLLP) - * PLLQ : 9 (STM32_PLLCFG_PPQ) - * Flash Latency(WS) : 4 - * Prefetch Buffer : OFF - * Instruction cache : ON - * Data cache : ON - * Require 48MHz for USB OTG FS, : Enabled - * SDIO and RNG clock - */ - -/* HSI - 16 MHz RC factory-trimmed - * LSI - 32 KHz RC - * HSE - not installed - * LSE - not installed - */ - -#define STM32_HSI_FREQUENCY 16000000ul -#define STM32_LSI_FREQUENCY 32000 -#define STM32_BOARD_USEHSI 1 - -/* Main PLL Configuration. - * - * Formulae: - * - * target 180 MHz, source 16 MHz -> ratio = 11.25 = 22.5 x 2 = 45 x 4 - * so we can select a divider of 4 and a multiplier of 45 - * However multiplier must be between 50 and 432 - * so we double again to choose a multiplier of 90, and a divider of 8 - * VCO output frequency must be in range 100...432 MHz - * - * VCO input frequency = PLL input clock frequency / PLLM, - * 2 <= PLLM <= 63 - * VCO output frequency = VCO input frequency × PLLN, - * 50 <= PLLN <= 432 (50-99 only if VCO input > 1 MHz) - * PLL output clock frequency = VCO frequency / PLLP, - * PLLP = 2, 4, 6, or 8 - * USB OTG FS clock frequency = VCO frequency / PLLQ, - * 2 <= PLLQ <= 15 - * - - * PLLQ = 7.5 PLLP = 2 PLLN=90 PLLM=4 - * - * We will configure like this - * - * PLL source is HSI - * PLL_VCO = (STM32_HSI_FREQUENCY / PLLM) * PLLN - * = (16,000,000 / 4) * 90 - * = 360 MHz - * SYSCLK = PLL_VCO / PLLP - * = 360,000,000 / 2 = 180,000,000 - * USB OTG FS and SDIO Clock - * = TODO 7.5 is not possible - * - * REVISIT: Trimming of the HSI is not yet supported. - */ - -#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(4) -#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(90) -#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_2 -#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(15) - -#define STM32_SYSCLK_FREQUENCY 180000000ul - -/* AHB clock (HCLK) is SYSCLK (104MHz) */ - -#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ -#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY - -/* APB1 clock (PCLK1) is HCLK/2 (52MHz) */ - -#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd2 /* PCLK1 = HCLK / 2 */ -#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/2) - -/* Timers driven from APB1 will be twice PCLK1 (REVISIT) */ - -#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) - -/* APB2 clock (PCLK2) is HCLK (104MHz) */ - -#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ -#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/1) - -/* Timers driven from APB1 will be twice PCLK1 */ - -#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM9_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM10_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM11_CLKIN (STM32_PCLK2_FREQUENCY) - -/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx - * otherwise frequency is 2xAPBx. - * Note: TIM1,8 are on APB2, others on APB1 - */ - -#define BOARD_TIM1_FREQUENCY (STM32_PCLK2_FREQUENCY) -#define BOARD_TIM2_FREQUENCY (2*STM32_PCLK1_FREQUENCY) -#define BOARD_TIM3_FREQUENCY (2*STM32_PCLK1_FREQUENCY) -#define BOARD_TIM4_FREQUENCY (2*STM32_PCLK1_FREQUENCY) -#define BOARD_TIM5_FREQUENCY (2*STM32_PCLK1_FREQUENCY) -#define BOARD_TIM6_FREQUENCY (2*STM32_PCLK1_FREQUENCY) -#define BOARD_TIM7_FREQUENCY (2*STM32_PCLK1_FREQUENCY) -#define BOARD_TIM8_FREQUENCY (STM32_PCLK2_FREQUENCY) - -/* SDIO dividers. Note that slower clocking is required when DMA is disabled - * in order to avoid RX overrun/TX underrun errors due to delayed responses - * to service FIFOs in interrupt driven mode. These values have not been - * tuned!!! - * - * HCLK=72MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(178+2)=400 KHz - * - * REVISIT - */ - -#define SDIO_INIT_CLKDIV (178 << SDIO_CLKCR_CLKDIV_SHIFT) - -/* DMA ON: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(2+2)=18 MHz - * DMA OFF: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(3+2)=14.4 MHz - * - * REVISIT - */ - -#ifdef CONFIG_SDIO_DMA -# define SDIO_MMCXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT) -#else -# define SDIO_MMCXFR_CLKDIV (3 << SDIO_CLKCR_CLKDIV_SHIFT) -#endif - -/* DMA ON: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(1+2)=24 MHz - * DMA OFF: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(3+2)=14.4 MHz - * - * REVISIT - */ - -#ifdef CONFIG_SDIO_DMA -# define SDIO_SDXFR_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT) -#else -# define SDIO_SDXFR_CLKDIV (3 << SDIO_CLKCR_CLKDIV_SHIFT) -#endif - -/* DMA Channel/Stream Selections ********************************************/ - -/* Stream selections are arbitrary for now but might become important in the - * future is we set aside more DMA channels/streams. - * - * SDIO DMA - *   DMAMAP_SDIO_1 = Channel 4, Stream 3 <- may later be used by SPI DMA - *   DMAMAP_SDIO_2 = Channel 4, Stream 6 - */ - -#define DMAMAP_SDIO DMAMAP_SDIO_1 - -/* Need to VERIFY fwb */ - -#define DMACHAN_SPI1_RX DMAMAP_SPI1_RX_1 -#define DMACHAN_SPI1_TX DMAMAP_SPI1_TX_1 -#define DMACHAN_SPI2_RX DMAMAP_SPI2_RX -#define DMACHAN_SPI2_TX DMAMAP_SPI2_TX - -/* ADC 1 */ - -#define ADC1_DMA_CHAN DMAMAP_ADC1_1 - -/* Alternate function pin selections ****************************************/ - -/* USART1: - * RXD: PA10 CN9 pin 3, CN10 pin 33 - * PB7 CN7 pin 21 - * TXD: PA9 CN5 pin 1, CN10 pin 21 - * PB6 CN5 pin 3, CN10 pin 17 - */ - -#if !defined(CONFIG_BOARD_STM32_IHM08M1) -# define GPIO_USART1_RX (GPIO_USART1_RX_1|GPIO_SPEED_100MHz) /* PA10 */ -# define GPIO_USART1_TX (GPIO_USART1_TX_1|GPIO_SPEED_100MHz) /* PA9 */ -#else -# define GPIO_USART1_RX (GPIO_USART1_RX_2|GPIO_SPEED_100MHz) /* PB7 */ -# define GPIO_USART1_TX (GPIO_USART1_TX_2|GPIO_SPEED_100MHz) /* PB6 */ -#endif - -/* USART2: - * RXD: PA3 CN9 pin 1 (See SB13, 14, 62, 63). CN10 pin 37 - * PD6 - * TXD: PA2 CN9 pin 2(See SB13, 14, 62, 63). CN10 pin 35 - * PD5 - */ - -#define GPIO_USART2_RX (GPIO_USART2_RX_1|GPIO_SPEED_100MHz) /* PA3 */ -#define GPIO_USART2_TX (GPIO_USART2_TX_1|GPIO_SPEED_100MHz) /* PA2 */ -#define GPIO_USART2_RTS GPIO_USART2_RTS_2 -#define GPIO_USART2_CTS GPIO_USART2_CTS_2 - -/* USART6: - * RXD: PC7 CN5 pin2, CN10 pin 19 - * PA12 CN10, pin 12 - * TXD: PC6 CN10, pin 4 - * PA11 CN10, pin 14 - */ - -#define GPIO_USART6_RX (GPIO_USART6_RX_1|GPIO_SPEED_100MHz) /* PC7 */ -#define GPIO_USART6_TX (GPIO_USART6_TX_1|GPIO_SPEED_100MHz) /* PC6 */ - -/* UART RX DMA configurations */ - -#define DMAMAP_USART1_RX DMAMAP_USART1_RX_2 -#define DMAMAP_USART6_RX DMAMAP_USART6_RX_2 - -/* I2C - * - * The optional _GPIO configurations allow the I2C driver to manually - * reset the bus to clear stuck slaves. They match the pin configuration, - * but are normally-high GPIOs. - */ - -#define GPIO_I2C1_SCL (GPIO_I2C1_SCL_2|GPIO_SPEED_50MHz) -#define GPIO_I2C1_SDA (GPIO_I2C1_SDA_2|GPIO_SPEED_50MHz) -#define GPIO_I2C1_SCL_GPIO \ - (GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET| \ - GPIO_PORTB|GPIO_PIN8) -#define GPIO_I2C1_SDA_GPIO \ - (GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET| \ - GPIO_PORTB|GPIO_PIN9) - -#define GPIO_I2C2_SCL (GPIO_I2C2_SCL_1|GPIO_SPEED_50MHz) -#define GPIO_I2C2_SDA (GPIO_I2C2_SDA_1|GPIO_SPEED_50MHz) -#define GPIO_I2C2_SCL_GPIO \ - (GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET| \ - GPIO_PORTB|GPIO_PIN10) -#define GPIO_I2C2_SDA_GPIO \ - (GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET| \ - GPIO_PORTB|GPIO_PIN11) - -/* SPI - * - * There are sensors on SPI1, and SPI2 is connected to the FRAM. - */ - -#define GPIO_SPI1_MISO (GPIO_SPI1_MISO_1|GPIO_SPEED_50MHz) -#define GPIO_SPI1_MOSI (GPIO_SPI1_MOSI_1|GPIO_SPEED_50MHz) -#define GPIO_SPI1_SCK (GPIO_SPI1_SCK_1|GPIO_SPEED_50MHz) - -#define GPIO_SPI2_MISO (GPIO_SPI2_MISO_1|GPIO_SPEED_50MHz) -#define GPIO_SPI2_MOSI (GPIO_SPI2_MOSI_1|GPIO_SPEED_50MHz) -#define GPIO_SPI2_SCK (GPIO_SPI2_SCK_2|GPIO_SPEED_50MHz) - -#define GPIO_SPI3_MISO (GPIO_SPI3_MISO_1|GPIO_SPEED_50MHz) -#define GPIO_SPI3_MOSI (GPIO_SPI3_MOSI_1|GPIO_SPEED_50MHz) -#define GPIO_SPI3_SCK (GPIO_SPI3_SCK_1|GPIO_SPEED_50MHz) - -/* CAN */ - -#define GPIO_CAN1_RX (GPIO_CAN1_RX_2|GPIO_SPEED_50MHz) -#define GPIO_CAN1_TX (GPIO_CAN1_TX_2|GPIO_SPEED_50MHz) - -#define GPIO_CAN2_RX (GPIO_CAN2_RX_2|GPIO_SPEED_50MHz) -#define GPIO_CAN2_TX (GPIO_CAN2_TX_2|GPIO_SPEED_50MHz) - -/* LEDs - * - * The Nucleo F446RE and F411RE boards provide a single user LED, LD2. LD2 - * is the green LED connected to Arduino signal D13 corresponding to MCU I/O - * PA5 (pin 21) or PB13 (pin 34) depending on the STM32 target. - * - * - When the I/O is HIGH value, the LED is on. - * - When the I/O is LOW, the LED is off. - */ - -/* LED index values for use with board_userled() */ - -#define BOARD_LD2 0 -#define BOARD_NLEDS 1 - -/* LED bits for use with board_userled_all() */ - -#define BOARD_LD2_BIT (1 << BOARD_LD2) - -/* These LEDs are not used by the board port unless CONFIG_ARCH_LEDS is - * defined. In that case, the usage by the board port is defined in - * include/board.h and src/sam_leds.c. The LEDs are used to encode OS-related - * events as follows when the red LED (PE24) is available: - * - * SYMBOL Meaning LD2 - * ------------------- ----------------------- ----------- - * LED_STARTED NuttX has been started OFF - * LED_HEAPALLOCATE Heap has been allocated OFF - * LED_IRQSENABLED Interrupts enabled OFF - * LED_STACKCREATED Idle stack created ON - * LED_INIRQ In an interrupt No change - * LED_SIGNAL In a signal handler No change - * LED_ASSERTION An assertion failed No change - * LED_PANIC The system has crashed Blinking - * LED_IDLE MCU is in sleep mode Not used - * - * Thus if LD2, NuttX has successfully booted and is, apparently, running - * normally. If LD2 is flashing at approximately 2Hz, then a fatal error - * has been detected and the system has halted. - */ - -#define LED_STARTED 0 -#define LED_HEAPALLOCATE 0 -#define LED_IRQSENABLED 0 -#define LED_STACKCREATED 1 -#define LED_INIRQ 2 -#define LED_SIGNAL 2 -#define LED_ASSERTION 2 -#define LED_PANIC 1 - -/* Buttons - * - * B1 USER: the user button is connected to the I/O PC13 (pin 2) of - * the STM32 microcontroller. - */ - -#define BUTTON_USER 0 -#define NUM_BUTTONS 1 - -#define BUTTON_USER_BIT (1 << BUTTON_USER) - -/* TIM2 input ***************************************************************/ - -#ifndef CONFIG_NUCLEO_F446RE_QETIMER_TIM2_IHM08M1_MAP -# define GPIO_TIM2_CH1IN (GPIO_TIM2_CH1IN_1 | GPIO_PULLUP | GPIO_SPEED_50MHz) /* PA8 */ -# define GPIO_TIM2_CH2IN (GPIO_TIM2_CH2IN_1 | GPIO_PULLUP | GPIO_SPEED_50MHz) /* PB0 */ -#else -# define GPIO_TIM2_CH1IN (GPIO_TIM2_CH1IN_2 | GPIO_PULLUP | GPIO_SPEED_50MHz) /* PA15 */ -# define GPIO_TIM2_CH2IN (GPIO_TIM2_CH2IN_2 | GPIO_PULLUP | GPIO_SPEED_50MHz) /* PB3 */ -#endif - -/* TIM3 configuration *******************************************************/ - -#define GPIO_TIM3_CH1OUT (GPIO_TIM3_CH1OUT_1|GPIO_SPEED_50MHz) - -/* TIM8 configuration *******************************************************/ - -#define GPIO_TIM8_CH1OUT (GPIO_TIM8_CH1OUT_1|GPIO_SPEED_50MHz) /* PC6 */ - -#ifdef CONFIG_BOARD_STM32_IHM08M1 - -/* Configuration specific to the X-NUCLEO-IHM08M1 expansion board with - * the L6398 gate drivers. - */ - -/* TIM1 configuration *******************************************************/ - -#define GPIO_TIM1_CH1OUT (GPIO_TIM1_CH1OUT_1|GPIO_SPEED_50MHz) /* TIM1 CH1 - PA8 - U high */ -#define GPIO_TIM1_CH1NOUT GPIO_TIM1_CH1N_1 /* TIM1 CH1N - PA7 - U low */ -#define GPIO_TIM1_CH2OUT (GPIO_TIM1_CH2OUT_1|GPIO_SPEED_50MHz) /* TIM1 CH2 - PA9 - V high */ -#define GPIO_TIM1_CH2NOUT GPIO_TIM1_CH2N_1 /* TIM1 CH2N - PB0 - V low */ -#define GPIO_TIM1_CH3OUT (GPIO_TIM1_CH3OUT_1|GPIO_SPEED_50MHz) /* TIM1 CH3 - PA10 - W high */ -#define GPIO_TIM1_CH3NOUT GPIO_TIM1_CH3N_1 /* TIM1 CH3N - PB1 - W low */ -#define GPIO_TIM1_CH4OUT 0 /* not used as output */ - -/* Board LED */ - -# define GPIO_FOC_LED2 (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz| \ - GPIO_OUTPUT_CLEAR|GPIO_PORTB|GPIO_PIN2) - -/* Debug pin */ - -# define GPIO_FOC_DEBUG0 (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz| \ - GPIO_OUTPUT_CLEAR|GPIO_PORTB|GPIO_PIN12) -# define GPIO_FOC_DEBUG1 (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz| \ - GPIO_OUTPUT_CLEAR|GPIO_PORTB|GPIO_PIN9) -# define GPIO_FOC_DEBUG2 (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz| \ - GPIO_OUTPUT_CLEAR|GPIO_PORTC|GPIO_PIN6) -# define GPIO_FOC_DEBUG3 (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz| \ - GPIO_OUTPUT_CLEAR|GPIO_PORTB|GPIO_PIN5) - -#endif /* CONFIG_BOARD_STM32_IHM08M1 */ - -/* DAC */ - -#define GPIO_DAC1_OUT1 GPIO_DAC1_OUT1_0 -#define GPIO_DAC1_OUT2 GPIO_DAC1_OUT2_0 - -/* USB OTG FS */ - -#define GPIO_OTGFS_DM (GPIO_OTGFS_DM_0|GPIO_SPEED_100MHz) -#define GPIO_OTGFS_DP (GPIO_OTGFS_DP_0|GPIO_SPEED_100MHz) -#define GPIO_OTGFS_ID (GPIO_OTGFS_ID_0|GPIO_SPEED_100MHz) -#define GPIO_OTGFS_SOF (GPIO_OTGFS_SOF_0|GPIO_SPEED_100MHz) - -#endif /* __BOARDS_ARM_STM32_NUCLEO_F446RE_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32/nucleo-f446re/scripts/Make.defs b/boards/arm/stm32/nucleo-f446re/scripts/Make.defs deleted file mode 100644 index 3ce0409127a70..0000000000000 --- a/boards/arm/stm32/nucleo-f446re/scripts/Make.defs +++ /dev/null @@ -1,42 +0,0 @@ -############################################################################ -# boards/arm/stm32/nucleo-f446re/scripts/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/.config -include $(TOPDIR)/tools/Config.mk -include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs - -LDSCRIPT = f446re.ld -ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) - -ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 - -CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) -CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) -CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -AFLAGS := $(CFLAGS) -D__ASSEMBLY__ - -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections -LDNXFLATFLAGS = -e main -s 2048 - diff --git a/boards/arm/stm32/nucleo-f446re/src/CMakeLists.txt b/boards/arm/stm32/nucleo-f446re/src/CMakeLists.txt deleted file mode 100644 index f9d569a51e955..0000000000000 --- a/boards/arm/stm32/nucleo-f446re/src/CMakeLists.txt +++ /dev/null @@ -1,79 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/nucleo-f446re/src/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -set(SRCS stm32_boot.c stm32_bringup.c stm32_spi.c) - -if(CONFIG_ARCH_LEDS) - list(APPEND SRCS stm32_autoleds.c) -else() - list(APPEND SRCS stm32_userleds.c) -endif() - -if(CONFIG_ARCH_BUTTONS) - list(APPEND SRCS stm32_buttons.c) -endif() - -if(CONFIG_LCD_ILI9225) - list(APPEND SRCS stm32_ili9225.c) -endif() - -if(NOT CONFIG_STM32_FOC) - if(CONFIG_ADC) - list(APPEND SRCS stm32_adc.c) - if(CONFIG_INPUT_AJOYSTICK) - list(APPEND SRCS stm32_ajoystick.c) - endif() - endif() -endif() - -if(CONFIG_STM32_CAN) - if(CONFIG_STM32_CAN_CHARDRIVER) - list(APPEND SRCS stm32_can.c) - endif() - if(CONFIG_STM32_CAN_SOCKET) - list(APPEND SRCS stm32_cansock.c) - endif() -endif() - -if(CONFIG_STM32_PWM) - list(APPEND SRCS stm32_pwm.c) -endif() - -if(CONFIG_DEV_GPIO) - list(APPEND SRCS stm32_gpio.c) -endif() - -if(CONFIG_DAC) - list(APPEND SRCS stm32_dac.c) -endif() - -if(CONFIG_BOARD_STM32_IHM08M1) - list(APPEND SRCS stm32_foc_ihm08m1.c) -endif() - -if(CONFIG_STM32_ROMFS) - list(APPEND SRCS stm32_romfs_initialize.c) -endif() - -target_sources(board PRIVATE ${SRCS}) - -set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/f446re.ld") diff --git a/boards/arm/stm32/nucleo-f446re/src/Make.defs b/boards/arm/stm32/nucleo-f446re/src/Make.defs deleted file mode 100644 index 968930b97673e..0000000000000 --- a/boards/arm/stm32/nucleo-f446re/src/Make.defs +++ /dev/null @@ -1,81 +0,0 @@ -############################################################################ -# boards/arm/stm32/nucleo-f446re/src/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/Make.defs - -CSRCS = stm32_boot.c stm32_bringup.c stm32_spi.c - -ifeq ($(CONFIG_ARCH_LEDS),y) -CSRCS += stm32_autoleds.c -else -CSRCS += stm32_userleds.c -endif - -ifeq ($(CONFIG_ARCH_BUTTONS),y) -CSRCS += stm32_buttons.c -endif - -ifeq ($(CONFIG_LCD_ILI9225),y) -CSRCS += stm32_ili9225.c -endif - -ifneq ($(CONFIG_STM32_FOC),y) -ifeq ($(CONFIG_ADC),y) -CSRCS += stm32_adc.c -ifeq ($(CONFIG_INPUT_AJOYSTICK),y) -CSRCS += stm32_ajoystick.c -endif -endif -endif - -ifeq ($(CONFIG_STM32_CAN),y) -ifeq ($(CONFIG_STM32_CAN_CHARDRIVER),y) -CSRCS += stm32_can.c -endif -ifeq ($(CONFIG_STM32_CAN_SOCKET),y) -CSRCS += stm32_cansock.c -endif -endif - -ifeq ($(CONFIG_STM32_PWM),y) -CSRCS += stm32_pwm.c -endif - -ifeq ($(CONFIG_DEV_GPIO),y) -CSRCS += stm32_gpio.c -endif - -ifeq ($(CONFIG_DAC),y) -CSRCS += stm32_dac.c -endif - -ifeq ($(CONFIG_BOARD_STM32_IHM08M1),y) -CSRCS += stm32_foc_ihm08m1.c -endif - -ifeq ($(CONFIG_STM32_ROMFS),y) -CSRCS += stm32_romfs_initialize.c -endif - -DEPPATH += --dep-path board -VPATH += :board -CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/nucleo-f446re/src/stm32_adc.c b/boards/arm/stm32/nucleo-f446re/src/stm32_adc.c deleted file mode 100644 index 5ae9b9dc8efac..0000000000000 --- a/boards/arm/stm32/nucleo-f446re/src/stm32_adc.c +++ /dev/null @@ -1,142 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f446re/src/stm32_adc.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32_pwm.h" -#include "nucleo-f446re.h" - -#ifdef CONFIG_STM32_ADC1 - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* The number of ADC channels in the conversion list */ - -#ifdef CONFIG_STM32_ADC1_DMA -# define ADC1_NCHANNELS 2 -#else -# define ADC1_NCHANNELS 1 -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* Identifying number of each ADC channel. */ - -#ifdef CONFIG_STM32_ADC1_DMA -/* The Itead analog joystick gets inputs on ADC_IN0 and ADC_IN1 */ - -static const uint8_t g_adc1_chanlist[ADC1_NCHANNELS] = -{ - 0, 1 -}; - -/* Configurations of pins used byte each ADC channels */ - -static const uint32_t g_adc1_pinlist[ADC1_NCHANNELS] = -{ - GPIO_ADC1_IN0_0, - GPIO_ADC1_IN1_0 -}; - -#else -/* Without DMA, only a single channel can be supported */ - -/* The Itead analog joystick gets input on ADC_IN0 */ - -static const uint8_t g_adc1_chanlist[ADC1_NCHANNELS] = -{ - 0 -}; - -/* Configurations of pins used byte each ADC channels */ - -static const uint32_t g_adc1_pinlist[ADC1_NCHANNELS] = -{ - GPIO_ADC1_IN0_0 -}; - -#endif /* CONFIG_STM32_ADC1_DMA */ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_adc_setup - * - * Description: - * Initialize ADC and register the ADC driver. - * - ****************************************************************************/ - -int stm32_adc_setup(void) -{ - struct adc_dev_s *adc; - int ret; - int i; - - /* Configure the pins as analog inputs for the selected channels */ - - for (i = 0; i < ADC1_NCHANNELS; i++) - { - stm32_configgpio(g_adc1_pinlist[i]); - } - - /* Call stm32_adcinitialize() to get an instance of the ADC interface */ - - adc = stm32_adcinitialize(1, g_adc1_chanlist, ADC1_NCHANNELS); - if (adc == NULL) - { - aerr("ERROR: Failed to get ADC interface\n"); - return -ENODEV; - } - - /* Register the ADC driver at "/dev/adc0" */ - - ret = adc_register("/dev/adc0", adc); - if (ret < 0) - { - aerr("ERROR: adc_register failed: %d\n", ret); - return ret; - } - - return OK; -} - -#endif /* CONFIG_STM32_ADC1 */ diff --git a/boards/arm/stm32/nucleo-f446re/src/stm32_ajoystick.c b/boards/arm/stm32/nucleo-f446re/src/stm32_ajoystick.c deleted file mode 100644 index 8e78f8d1adb99..0000000000000 --- a/boards/arm/stm32/nucleo-f446re/src/stm32_ajoystick.c +++ /dev/null @@ -1,491 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f446re/src/stm32_ajoystick.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include - -#include -#include -#include -#include -#include - -#include "stm32_gpio.h" -#include "stm32_adc.h" -#include "hardware/stm32_adc.h" -#include "nucleo-f446re.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Check for pre-requisites and pin conflicts */ - -#ifdef CONFIG_INPUT_AJOYSTICK -# if !defined(CONFIG_ADC) -# error CONFIG_ADC is required for the Itead joystick -# undef CONFIG_INPUT_AJOYSTICK -# elif !defined(CONFIG_STM32_ADC1) -# error CONFIG_STM32_ADC1 is required for Itead joystick -# undef CONFIG_INPUT_AJOYSTICK -# endif -#endif /* CONFIG_INPUT_AJOYSTICK */ - -#ifdef CONFIG_INPUT_AJOYSTICK - -/* A no-ADC, buttons only version can be built for testing */ - -#undef NO_JOYSTICK_ADC - -/* Maximum number of ADC channels */ - -#define MAX_ADC_CHANNELS 8 - -/* Dual channel ADC support requires DMA */ - -#ifdef CONFIG_ADC_DMA -# define NJOYSTICK_CHANNELS 2 -#else -# define NJOYSTICK_CHANNELS 1 -#endif - -#ifdef CONFIG_NUCLEO_F401RE_AJOY_MINBUTTONS -/* Number of Joystick buttons */ - -# define AJOY_NGPIOS 3 - -/* Bitset of supported Joystick buttons */ - -# define AJOY_SUPPORTED (AJOY_BUTTON_1_BIT | AJOY_BUTTON_2_BIT | \ - AJOY_BUTTON_3_BIT) -#else -/* Number of Joystick buttons */ - -# define AJOY_NGPIOS 7 - -/* Bitset of supported Joystick buttons */ - -# define AJOY_SUPPORTED (AJOY_BUTTON_1_BIT | AJOY_BUTTON_2_BIT | \ - AJOY_BUTTON_3_BIT | AJOY_BUTTON_4_BIT | \ - AJOY_BUTTON_5_BIT | AJOY_BUTTON_6_BIT | \ - AJOY_BUTTON_7_BIT ) -#endif - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -static ajoy_buttonset_t -ajoy_supported(const struct ajoy_lowerhalf_s *lower); -static int ajoy_sample(const struct ajoy_lowerhalf_s *lower, - struct ajoy_sample_s *sample); -static ajoy_buttonset_t -ajoy_buttons(const struct ajoy_lowerhalf_s *lower); -static void -ajoy_enable(const struct ajoy_lowerhalf_s *lower, - ajoy_buttonset_t press, ajoy_buttonset_t release, - ajoy_handler_t handler, void *arg); - -static void ajoy_disable(void); -static int ajoy_interrupt(int irq, void *context, void *arg); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* Pin configuration for each Itead joystick button. Index using AJOY_* - * button definitions in include/nuttx/input/ajoystick.h. - */ - -#ifdef CONFIG_NUCLEO_F401RE_AJOY_MINBUTTONS -static const uint32_t g_joygpio[AJOY_NGPIOS] = -{ - GPIO_BUTTON_1, GPIO_BUTTON_2, GPIO_BUTTON_3 -}; -#else -static const uint32_t g_joygpio[AJOY_NGPIOS] = -{ - GPIO_BUTTON_1, GPIO_BUTTON_2, GPIO_BUTTON_3, GPIO_BUTTON_4, - GPIO_BUTTON_5, GPIO_BUTTON_6, GPIO_BUTTON_7 -}; -#endif - -/* This is the button joystick lower half driver interface */ - -static const struct ajoy_lowerhalf_s g_ajoylower = -{ - .al_supported = ajoy_supported, - .al_sample = ajoy_sample, - .al_buttons = ajoy_buttons, - .al_enable = ajoy_enable, -}; - -#ifndef NO_JOYSTICK_ADC -/* Thread-independent file structure for the open ADC driver */ - -static struct file g_adcfile; -#endif - -/* Current interrupt handler and argument */ - -static ajoy_handler_t g_ajoyhandler; -static void *g_ajoyarg; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: ajoy_supported - * - * Description: - * Return the set of buttons supported on the button joystick device - * - ****************************************************************************/ - -static ajoy_buttonset_t -ajoy_supported(const struct ajoy_lowerhalf_s *lower) -{ - iinfo("Supported: %02x\n", AJOY_SUPPORTED); - return (ajoy_buttonset_t)AJOY_SUPPORTED; -} - -/**************************************************************************** - * Name: ajoy_sample - * - * Description: - * Return the current state of all button joystick buttons - * - ****************************************************************************/ - -static int ajoy_sample(const struct ajoy_lowerhalf_s *lower, - struct ajoy_sample_s *sample) -{ -#ifndef NO_JOYSTICK_ADC - struct adc_msg_s adcmsg[MAX_ADC_CHANNELS]; - struct adc_msg_s *ptr; - ssize_t nread; - ssize_t offset; - int have; - int i; - - /* Read all of the available samples (handling the case where additional - * channels are enabled). - */ - - nread = file_read(&g_adcfile, adcmsg, - MAX_ADC_CHANNELS * sizeof(struct adc_msg_s)); - if (nread < 0) - { - if (nread != -EINTR) - { - ierr("ERROR: read failed: %d\n", (int)nread); - } - - return nread; - } - else if (nread < NJOYSTICK_CHANNELS * sizeof(struct adc_msg_s)) - { - ierr("ERROR: read too small: %ld\n", (long)nread); - return -EIO; - } - - /* Sample and the raw analog inputs */ - -#ifdef CONFIG_ADC_DMA - have = 0; - -#else - /* If DMA is not supported, then we will have only a single ADC channel */ - - have = 2; - sample->as_y = 0; -#endif - - for (i = 0, offset = 0; - i < MAX_ADC_CHANNELS && offset < nread && have != 3; - i++, offset += sizeof(struct adc_msg_s)) - { - ptr = &adcmsg[i]; - - /* Is this one of the channels that we need? */ - - if ((have & 1) == 0 && ptr->am_channel == 0) - { - int32_t tmp = ptr->am_data; - sample->as_x = (int16_t)tmp; - have |= 1; - - iinfo("X sample: %ld -> %d\n", (long)tmp, (int)sample->as_x); - } - -#ifdef CONFIG_ADC_DMA - if ((have & 2) == 0 && ptr->am_channel == 1) - { - int32_t tmp = ptr->am_data; - sample->as_y = (int16_t)tmp; - have |= 2; - - iinfo("Y sample: %ld -> %d\n", (long)tmp, (int)sample->as_y); - } -#endif - } - - if (have != 3) - { - ierr("ERROR: Could not find joystick channels\n"); - return -EIO; - } - -#else - /* ADC support is disabled */ - - sample->as_x = 0; - sample->as_y = 0; -#endif - - /* Sample the discrete button inputs */ - - sample->as_buttons = ajoy_buttons(lower); - iinfo("Returning: %02x\n", sample->as_buttons); - return OK; -} - -/**************************************************************************** - * Name: ajoy_buttons - * - * Description: - * Return the current state of button data (only) - * - ****************************************************************************/ - -static ajoy_buttonset_t -ajoy_buttons(const struct ajoy_lowerhalf_s *lower) -{ - ajoy_buttonset_t ret = 0; - int i; - - /* Read each joystick GPIO value */ - - for (i = 0; i < AJOY_NGPIOS; i++) - { - /* Button outputs are pulled high. So a sensed low level means that the - * button is pressed. - */ - - if (!stm32_gpioread(g_joygpio[i])) - { - ret |= (1 << i); - } - } - - iinfo("Returning: %02x\n", ret); - return ret; -} - -/**************************************************************************** - * Name: ajoy_enable - * - * Description: - * Enable interrupts on the selected set of joystick buttons. And empty - * set will disable all interrupts. - * - ****************************************************************************/ - -static void ajoy_enable(const struct ajoy_lowerhalf_s *lower, - ajoy_buttonset_t press, ajoy_buttonset_t release, - ajoy_handler_t handler, void *arg) -{ - irqstate_t flags; - ajoy_buttonset_t either = press | release; - ajoy_buttonset_t bit; - bool rising; - bool falling; - int i; - - /* Start with all interrupts disabled */ - - flags = enter_critical_section(); - ajoy_disable(); - - iinfo("press: %02x release: %02x handler: %p arg: %p\n", - press, release, handler, arg); - - /* If no events are indicated or if no handler is provided, then this - * must really be a request to disable interrupts. - */ - - if (either && handler) - { - /* Save the new the handler and argument */ - - g_ajoyhandler = handler; - g_ajoyarg = arg; - - /* Check each GPIO. */ - - for (i = 0; i < AJOY_NGPIOS; i++) - { - /* Enable interrupts on each pin that has either a press or - * release event associated with it. - */ - - bit = (1 << i); - if ((either & bit) != 0) - { - /* Active low so a press corresponds to a falling edge and - * a release corresponds to a rising edge. - */ - - falling = ((press & bit) != 0); - rising = ((release & bit) != 0); - - iinfo("GPIO %d: rising: %d falling: %d\n", - i, rising, falling); - - stm32_gpiosetevent(g_joygpio[i], rising, falling, - true, ajoy_interrupt, NULL); - } - } - } - - leave_critical_section(flags); -} - -/**************************************************************************** - * Name: ajoy_disable - * - * Description: - * Disable all joystick interrupts - * - ****************************************************************************/ - -static void ajoy_disable(void) -{ - irqstate_t flags; - int i; - - /* Disable each joystick interrupt */ - - flags = enter_critical_section(); - for (i = 0; i < AJOY_NGPIOS; i++) - { - stm32_gpiosetevent(g_joygpio[i], false, false, false, NULL, NULL); - } - - leave_critical_section(flags); - - /* Nullify the handler and argument */ - - g_ajoyhandler = NULL; - g_ajoyarg = NULL; -} - -/**************************************************************************** - * Name: ajoy_interrupt - * - * Description: - * Discrete joystick interrupt handler - * - ****************************************************************************/ - -static int ajoy_interrupt(int irq, void *context, void *arg) -{ - DEBUGASSERT(g_ajoyhandler); - - if (g_ajoyhandler) - { - g_ajoyhandler(&g_ajoylower, g_ajoyarg); - } - - return OK; -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_ajoy_initialize - * - * Description: - * Initialize and register the button joystick driver - * - ****************************************************************************/ - -int board_ajoy_initialize(void) -{ - int ret; - int i; - -#ifndef NO_JOYSTICK_ADC - iinfo("Initialize ADC driver: /dev/adc0\n"); - - /* Open the ADC driver for reading. - * NOTE: The ADC driver was initialized earlier in the bring-up sequence. - */ - - ret = file_open(&g_adcfile, "/dev/adc0", O_RDONLY); - if (ret < 0) - { - ierr("ERROR: Failed to open /dev/adc0: %d\n", ret); - return ret; - } -#endif - - /* Configure the GPIO pins as interrupting inputs. NOTE: This is - * unnecessary for interrupting pins since it will also be done by - * stm32_gpiosetevent(). - */ - - for (i = 0; i < AJOY_NGPIOS; i++) - { - /* Configure the PIO as an input */ - - stm32_configgpio(g_joygpio[i]); - } - - /* Register the joystick device as /dev/ajoy0 */ - - iinfo("Initialize joystick driver: /dev/ajoy0\n"); - - ret = ajoy_register("/dev/ajoy0", &g_ajoylower); - if (ret < 0) - { - ierr("ERROR: ajoy_register failed: %d\n", ret); -#ifndef NO_JOYSTICK_ADC - file_close(&g_adcfile); -#endif - } - - return ret; -} - -#endif /* CONFIG_INPUT_AJOYSTICK */ diff --git a/boards/arm/stm32/nucleo-f446re/src/stm32_autoleds.c b/boards/arm/stm32/nucleo-f446re/src/stm32_autoleds.c deleted file mode 100644 index 5ef67f5e802f4..0000000000000 --- a/boards/arm/stm32/nucleo-f446re/src/stm32_autoleds.c +++ /dev/null @@ -1,82 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f446re/src/stm32_autoleds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32.h" -#include "nucleo-f446re.h" - -#ifdef CONFIG_ARCH_LEDS - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_autoled_initialize - ****************************************************************************/ - -void board_autoled_initialize(void) -{ - /* Configure LD2 GPIO for output */ - - stm32_configgpio(GPIO_LD2); -} - -/**************************************************************************** - * Name: board_autoled_on - ****************************************************************************/ - -void board_autoled_on(int led) -{ - if (led == 1) - { - stm32_gpiowrite(GPIO_LD2, true); - } -} - -/**************************************************************************** - * Name: board_autoled_off - ****************************************************************************/ - -void board_autoled_off(int led) -{ - if (led == 1) - { - stm32_gpiowrite(GPIO_LD2, false); - } -} - -#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/nucleo-f446re/src/stm32_boot.c b/boards/arm/stm32/nucleo-f446re/src/stm32_boot.c deleted file mode 100644 index a3af05f05271e..0000000000000 --- a/boards/arm/stm32/nucleo-f446re/src/stm32_boot.c +++ /dev/null @@ -1,103 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f446re/src/stm32_boot.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include -#include -#include - -#include - -#include "arm_internal.h" -#include "nucleo-f446re.h" - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_boardinitialize - * - * Description: - * All STM32 architectures must provide the following entry point. This - * entry point is called early in the initialization -- after all memory - * has been configured and mapped but before any devices have been - * initialized. - * - ****************************************************************************/ - -void stm32_boardinitialize(void) -{ -#ifdef CONFIG_ARCH_LEDS - /* Configure on-board LEDs if LED support has been selected. */ - - board_autoled_initialize(); -#endif - -#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || \ - defined(CONFIG_STM32_SPI3) - /* Configure SPI chip selects if 1) SP2 is not disabled, and 2) the weak - * function stm32_spidev_initialize() has been brought into the link. - */ - - stm32_spidev_initialize(); -#endif - -#if defined(CONFIG_USBDEV) && defined(CONFIG_STM32_USB) - /* Initialize USB is 1) USBDEV is selected, 2) the USB controller is not - * disabled, and 3) the weak function stm32_usbinitialize() has been - * broughtvinto the build. - */ - - stm32_usbinitialize(); -#endif -} - -/**************************************************************************** - * Name: board_late_initialize - * - * Description: - * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional - * initialization call will be performed in the boot-up sequence to a - * function called board_late_initialize(). board_late_initialize() will - * be called immediately after up_initialize() is called and just before - * the initial application is started. This additional initialization - * phase may be used, for example, to initialize board-specific device - * drivers. - * - ****************************************************************************/ - -#ifdef CONFIG_BOARD_LATE_INITIALIZE -void board_late_initialize(void) -{ - /* Perform board-specific initialization */ - - stm32_bringup(); -} -#endif diff --git a/boards/arm/stm32/nucleo-f446re/src/stm32_bringup.c b/boards/arm/stm32/nucleo-f446re/src/stm32_bringup.c deleted file mode 100644 index 893fe82510275..0000000000000 --- a/boards/arm/stm32/nucleo-f446re/src/stm32_bringup.c +++ /dev/null @@ -1,302 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f446re/src/stm32_bringup.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include -#include -#include - -#include - -#include - -#ifdef CONFIG_PULSECOUNT -# include "stm32_pulsecount.h" -#endif - -#ifdef CONFIG_INPUT_BUTTONS -# include -#endif - -#ifdef CONFIG_SENSORS_QENCODER -# include "board_qencoder.h" -#endif - -#ifdef CONFIG_SENSORS_HALL3PHASE -# include "board_hall3ph.h" -#endif - -#ifdef CONFIG_VIDEO_FB -# include -#endif - -#ifdef CONFIG_USERLED -# include -#endif - -#include "stm32_romfs.h" -#include "nucleo-f446re.h" - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_bringup - * - * Description: - * Perform architecture-specific initialization - * - * CONFIG_BOARD_LATE_INITIALIZE=y : - * Called from board_late_initialize(). - * - ****************************************************************************/ - -int stm32_bringup(void) -{ -#ifdef CONFIG_PULSECOUNT - struct pulsecount_lowerhalf_s *pulsecount; -#endif - int ret = OK; - -#ifdef CONFIG_FS_PROCFS - /* Mount the procfs file system */ - - ret = nx_mount(NULL, STM32_PROCFS_MOUNTPOINT, "procfs", 0, NULL); - if (ret < 0) - { - syslog(LOG_ERR, - "ERROR: Failed to mount the PROC filesystem: %d\n", ret); - } -#endif /* CONFIG_FS_PROCFS */ - -#ifdef CONFIG_STM32_ROMFS - ret = stm32_romfs_initialize(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: Failed to mount romfs at %s: %d\n", - CONFIG_STM32_ROMFS_MOUNTPOINT, ret); - } -#endif - -#ifdef CONFIG_INPUT_BUTTONS - /* Register the BUTTON driver */ - - ret = btn_lower_initialize("/dev/buttons"); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: btn_lower_initialize() failed: %d\n", ret); - } -#endif - -#ifdef HAVE_MMCSD - /* First, get an instance of the SDIO interface */ - - g_sdio = sdio_initialize(CONFIG_NSH_MMCSDSLOTNO); - if (!g_sdio) - { - syslog(LOG_ERR, "ERROR: Failed to initialize SDIO slot %d\n", - CONFIG_NSH_MMCSDSLOTNO); - return -ENODEV; - } - - /* Now bind the SDIO interface to the MMC/SD driver */ - - ret = mmcsd_slotinitialize(CONFIG_NSH_MMCSDMINOR, g_sdio); - if (ret != OK) - { - syslog(LOG_ERR, - "ERROR: Failed to bind SDIO to the MMC/SD driver: %d\n", - ret); - return ret; - } - - /* Then let's guess and say that there is a card in the slot. There is no - * card detect GPIO. - */ - - sdio_mediachange(g_sdio, true); - - syslog(LOG_INFO, "[boot] Initialized SDIO\n"); -#endif - -#ifdef CONFIG_STM32_FOC - /* Initialize and register the FOC device */ - - ret = stm32_foc_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_foc_setup failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_ADC - /* Initialize ADC and register the ADC driver. */ - - ret = stm32_adc_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_adc_setup failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_PULSECOUNT - /* Initialize and register the pulse count driver. */ - - pulsecount = stm32_pulsecountinitialize(8); - if (pulsecount == NULL) - { - syslog(LOG_ERR, "ERROR: stm32_pulsecountinitialize failed\n"); - return -ENODEV; - } - - ret = pulsecount_register("/dev/pulsecount0", pulsecount); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: pulsecount_register failed: %d\n", ret); - return ret; - } -#endif - -#ifdef CONFIG_STM32_CAN_CHARDRIVER - /* Initialize CAN and register the CAN driver. */ - - ret = stm32_can_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_can_setup failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_STM32_CAN_SOCKET - /* Initialize CAN socket interface */ - - ret = stm32_cansock_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_cansock_setup failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_VIDEO_FB - /* Initialize and register the framebuffer driver */ - - ret = fb_register(0, 0); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: fb_register() failed %d\n", ret); - } -#endif - -#ifdef CONFIG_SENSORS_QENCODER - /* Initialize and register the qencoder driver */ - - ret = board_qencoder_initialize(0, CONFIG_NUCLEO_F446RE_QETIMER); - if (ret != OK) - { - syslog(LOG_ERR, - "ERROR: Failed to register the qencoder: %d\n", - ret); - return ret; - } -#endif - -#ifdef CONFIG_SENSORS_HALL3PHASE - /* Initialize and register the 3-phase Hall effect sensor driver */ - - ret = board_hall3ph_initialize(0, GPIO_HALL_PHA, GPIO_HALL_PHB, - GPIO_HALL_PHC); - if (ret != OK) - { - syslog(LOG_ERR, - "ERROR: Failed to register the hall : %d\n", - ret); - return ret; - } -#endif - -#ifdef CONFIG_INPUT_AJOYSTICK - /* Initialize and register the joystick driver */ - - ret = board_ajoy_initialize(); - if (ret != OK) - { - syslog(LOG_ERR, - "ERROR: Failed to register the joystick driver: %d\n", - ret); - return ret; - } -#endif - -#ifdef CONFIG_PWM - /* Initialize PWM and register the PWM device */ - - ret = stm32_pwm_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_pwm_setup() failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_DEV_GPIO - /* Initialize GPIO driver */ - - ret = stm32_gpio_initialize(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_gpio_initialize() failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_USERLED - /* Register the LED driver */ - - ret = userled_lower_initialize("/dev/userleds"); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: userled_lower_initialize() failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_DAC - /* Initialize DAC and register the DAC driver. */ - - ret = stm32_dac_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: Failed to start ADC1: %d\n", ret); - } -#endif - - return ret; -} diff --git a/boards/arm/stm32/nucleo-f446re/src/stm32_buttons.c b/boards/arm/stm32/nucleo-f446re/src/stm32_buttons.c deleted file mode 100644 index c7e976e49baaf..0000000000000 --- a/boards/arm/stm32/nucleo-f446re/src/stm32_buttons.c +++ /dev/null @@ -1,115 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f446re/src/stm32_buttons.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include -#include - -#include "nucleo-f446re.h" - -#ifdef CONFIG_ARCH_BUTTONS - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_button_initialize - * - * Description: - * board_button_initialize() must be called to initialize button resources. - * After that, board_buttons() may be called to collect the current state - * of all buttons or board_button_irq() may be called to register button - * interrupt handlers. - * - ****************************************************************************/ - -uint32_t board_button_initialize(void) -{ - /* Configure the single button as an input. NOTE that EXTI interrupts are - * also configured for the pin. - */ - - stm32_configgpio(GPIO_BTN_USER); - return NUM_BUTTONS; -} - -/**************************************************************************** - * Name: board_buttons - ****************************************************************************/ - -uint32_t board_buttons(void) -{ - /* Check that state of each USER button. A LOW value means that the key is - * pressed. - */ - - bool released = stm32_gpioread(GPIO_BTN_USER); - return !released; -} - -/**************************************************************************** - * Button support. - * - * Description: - * board_button_initialize() must be called to initialize button resources. - * After that, board_buttons() may be called to collect the current state - * of all buttons or board_button_irq() may be called to register button - * interrupt handlers. - * - * After board_button_initialize() has been called, board_buttons() may be - * called to collect the state of all buttons. board_buttons() returns an - * 32-bit bit set with each bit associated with a button. See the - * BUTTON_*_BIT definitions in board.h for the meaning of each bit. - * - * board_button_irq() may be called to register an interrupt handler that - * will be called when a button is depressed or released. The ID value is - * a button enumeration value that uniquely identifies a button resource. - * See the BUTTON_* definitions in board.h for the meaning of enumeration - * value. - * - ****************************************************************************/ - -#ifdef CONFIG_ARCH_IRQBUTTONS -int board_button_irq(int id, xcpt_t irqhandler, void *arg) -{ - int ret = -EINVAL; - - if (id == BUTTON_USER) - { - ret = stm32_gpiosetevent(GPIO_BTN_USER, true, true, true, irqhandler, - arg); - } - - return ret; -} -#endif -#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/stm32/nucleo-f446re/src/stm32_can.c b/boards/arm/stm32/nucleo-f446re/src/stm32_can.c deleted file mode 100644 index dd2c75c98b0c2..0000000000000 --- a/boards/arm/stm32/nucleo-f446re/src/stm32_can.c +++ /dev/null @@ -1,117 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f446re/src/stm32_can.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32.h" -#include "stm32_can.h" -#include "nucleo-f446re.h" - -#ifdef CONFIG_CAN - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -#if !defined(CONFIG_STM32_CAN1) && !defined(CONFIG_STM32_CAN2) -# error "No CAN is enable. Please enable at least one CAN device" -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_can_setup - * - * Description: - * Initialize CAN and register the CAN device - * - ****************************************************************************/ - -int stm32_can_setup(void) -{ - struct can_dev_s *can; - int ret; - -#ifdef CONFIG_STM32_CAN1 - - /* Call stm32_caninitialize() to get an instance of the CAN interface */ - - can = stm32_caninitialize(1); - if (can == NULL) - { - canerr("ERROR: Failed to get CAN interface\n"); - return -ENODEV; - } - - /* Register the CAN driver at "/dev/can0" */ - - ret = can_register("/dev/can0", can); - if (ret < 0) - { - canerr("ERROR: can_register failed: %d\n", ret); - return ret; - } - -#endif -#ifdef CONFIG_STM32_CAN2 - - /* Call stm32_caninitialize() to get an instance of the CAN interface */ - - can = stm32_caninitialize(2); - if (can == NULL) - { - canerr("ERROR: Failed to get CAN interface\n"); - return -ENODEV; - } - - /* Register the CAN driver at "/dev/can1" */ - - ret = can_register("/dev/can1", can); - if (ret < 0) - { - canerr("ERROR: can_register failed: %d\n", ret); - return ret; - } - -#endif - UNUSED(ret); - UNUSED(can); - return OK; -} - -#endif /* CONFIG_CAN */ diff --git a/boards/arm/stm32/nucleo-f446re/src/stm32_cansock.c b/boards/arm/stm32/nucleo-f446re/src/stm32_cansock.c deleted file mode 100644 index e0ea15be89fe6..0000000000000 --- a/boards/arm/stm32/nucleo-f446re/src/stm32_cansock.c +++ /dev/null @@ -1,85 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f446re/src/stm32_cansock.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include "stm32_can.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -#if !defined(CONFIG_STM32_CAN1) && !defined(CONFIG_STM32_CAN2) -# error "No CAN is enable. Please enable at least one CAN device" -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_cansock_setup - * - * Description: - * Initialize CAN socket interface - * - ****************************************************************************/ - -int stm32_cansock_setup(void) -{ - int ret = OK; - - UNUSED(ret); - -#ifdef CONFIG_STM32_CAN1 - /* Call stm32_caninitialize() to get an instance of the CAN interface */ - - ret = stm32_cansockinitialize(1); - if (ret < 0) - { - canerr("ERROR: Failed to get CAN interface %d\n", ret); - goto errout; - } -#endif - -#ifdef CONFIG_STM32_CAN2 - /* Call stm32_caninitialize() to get an instance of the CAN interface */ - - ret = stm32_cansockinitialize(2); - if (ret < 0) - { - canerr("ERROR: Failed to get CAN interface %d\n", ret); - goto errout; - } -#endif - -errout: - return ret; -} diff --git a/boards/arm/stm32/nucleo-f446re/src/stm32_dac.c b/boards/arm/stm32/nucleo-f446re/src/stm32_dac.c deleted file mode 100644 index 1cb743db573d2..0000000000000 --- a/boards/arm/stm32/nucleo-f446re/src/stm32_dac.c +++ /dev/null @@ -1,112 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f446re/src/stm32_dac.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include -#include - -#include -#include - -#include "stm32_dac.h" -#include "nucleo-f446re.h" - -#ifdef CONFIG_DAC - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -#ifdef CONFIG_STM32_DAC1CH1 -static struct dac_dev_s *g_dac1; -#endif - -#ifdef CONFIG_STM32_DAC1CH2 -static struct dac_dev_s *g_dac2; -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_dac_setup - * - * Description: - * Initialize and register the DAC driver. - * - * Input parameters: - * devpath - The full path to the driver to register. E.g., "/dev/dac0" - * - * Returned Value: - * Zero (OK) on success; a negated errno value on failure. - * - ****************************************************************************/ - -int stm32_dac_setup(void) -{ - int ret; -#ifdef CONFIG_STM32_DAC1CH1 - g_dac1 = stm32_dacinitialize(1); - if (g_dac1 == NULL) - { - aerr("ERROR: Failed to get DAC interface\n"); - return -ENODEV; - } - - /* Register the DAC driver at "/dev/dac0" */ - - ret = dac_register("/dev/dac0", g_dac1); - if (ret < 0) - { - aerr("ERROR: dac_register() failed: %d\n", ret); - return ret; - } - -#endif -#ifdef CONFIG_STM32_DAC1CH2 - g_dac2 = stm32_dacinitialize(2); - if (g_dac2 == NULL) - { - aerr("ERROR: Failed to get DAC interface\n"); - return -ENODEV; - } - - /* Register the DAC driver at "/dev/dac1" */ - - ret = dac_register("/dev/dac1", g_dac2); - if (ret < 0) - { - aerr("ERROR: dac_register() failed: %d\n", ret); - return ret; - } -#endif - - UNUSED(ret); - return OK; -} - -#endif /* CONFIG_DAC */ diff --git a/boards/arm/stm32/nucleo-f446re/src/stm32_gpio.c b/boards/arm/stm32/nucleo-f446re/src/stm32_gpio.c deleted file mode 100644 index 43ceabb8ca309..0000000000000 --- a/boards/arm/stm32/nucleo-f446re/src/stm32_gpio.c +++ /dev/null @@ -1,343 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f446re/src/stm32_gpio.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include -#include - -#include - -#include "chip.h" -#include "stm32.h" -#include "nucleo-f446re.h" - -#if defined(CONFIG_DEV_GPIO) && !defined(CONFIG_GPIO_LOWER_HALF) - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -struct stm32gpio_dev_s -{ - struct gpio_dev_s gpio; - uint8_t id; -}; - -struct stm32gpint_dev_s -{ - struct stm32gpio_dev_s stm32gpio; - pin_interrupt_t callback; -}; - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -#if BOARD_NGPIOIN > 0 -static int gpin_read(struct gpio_dev_s *dev, bool *value); -#endif -#if BOARD_NGPIOOUT > 0 -static int gpout_read(struct gpio_dev_s *dev, bool *value); -static int gpout_write(struct gpio_dev_s *dev, bool value); -#endif -#if BOARD_NGPIOINT > 0 -static int gpint_read(struct gpio_dev_s *dev, bool *value); -static int gpint_attach(struct gpio_dev_s *dev, - pin_interrupt_t callback); -static int gpint_enable(struct gpio_dev_s *dev, bool enable); -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -#if BOARD_NGPIOIN > 0 -static const struct gpio_operations_s gpin_ops = -{ - .go_read = gpin_read, - .go_write = NULL, - .go_attach = NULL, - .go_enable = NULL, -}; -#endif - -#if BOARD_NGPIOOUT > 0 -static const struct gpio_operations_s gpout_ops = -{ - .go_read = gpout_read, - .go_write = gpout_write, - .go_attach = NULL, - .go_enable = NULL, -}; -#endif - -#if BOARD_NGPIOINT > 0 -static const struct gpio_operations_s gpint_ops = -{ - .go_read = gpint_read, - .go_write = NULL, - .go_attach = gpint_attach, - .go_enable = gpint_enable, -}; -#endif - -#if BOARD_NGPIOIN > 0 -/* This array maps the GPIO pins used as INPUT */ - -static const uint32_t g_gpioinputs[BOARD_NGPIOIN] = -{ - GPIO_IN1, -}; - -static struct stm32gpio_dev_s g_gpin[BOARD_NGPIOIN]; -#endif - -#if BOARD_NGPIOOUT -/* This array maps the GPIO pins used as OUTPUT */ - -static const uint32_t g_gpiooutputs[BOARD_NGPIOOUT] = -{ - GPIO_OUT1, -}; - -static struct stm32gpio_dev_s g_gpout[BOARD_NGPIOOUT]; -#endif - -#if BOARD_NGPIOINT > 0 -/* This array maps the GPIO pins used as INTERRUPT INPUTS */ - -static const uint32_t g_gpiointinputs[BOARD_NGPIOINT] = -{ - GPIO_INT1, -}; - -static struct stm32gpint_dev_s g_gpint[BOARD_NGPIOINT]; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -#if BOARD_NGPIOINT > 0 -static int stm32gpio_interrupt(int irq, void *context, void *arg) -{ - struct stm32gpint_dev_s *stm32gpint = - (struct stm32gpint_dev_s *)arg; - - DEBUGASSERT(stm32gpint != NULL && stm32gpint->callback != NULL); - gpioinfo("Interrupt! callback=%p\n", stm32gpint->callback); - - stm32gpint->callback(&stm32gpint->stm32gpio.gpio, - stm32gpint->stm32gpio.id); - return OK; -} -#endif - -#if BOARD_NGPIOIN > 0 -static int gpin_read(struct gpio_dev_s *dev, bool *value) -{ - struct stm32gpio_dev_s *stm32gpio = - (struct stm32gpio_dev_s *)dev; - - DEBUGASSERT(stm32gpio != NULL && value != NULL); - DEBUGASSERT(stm32gpio->id < BOARD_NGPIOIN); - gpioinfo("Reading...\n"); - - *value = stm32_gpioread(g_gpioinputs[stm32gpio->id]); - return OK; -} -#endif - -#if BOARD_NGPIOOUT > 0 -static int gpout_read(struct gpio_dev_s *dev, bool *value) -{ - struct stm32gpio_dev_s *stm32gpio = - (struct stm32gpio_dev_s *)dev; - - DEBUGASSERT(stm32gpio != NULL && value != NULL); - DEBUGASSERT(stm32gpio->id < BOARD_NGPIOOUT); - gpioinfo("Reading...\n"); - - *value = stm32_gpioread(g_gpiooutputs[stm32gpio->id]); - return OK; -} - -static int gpout_write(struct gpio_dev_s *dev, bool value) -{ - struct stm32gpio_dev_s *stm32gpio = - (struct stm32gpio_dev_s *)dev; - - DEBUGASSERT(stm32gpio != NULL); - DEBUGASSERT(stm32gpio->id < BOARD_NGPIOOUT); - gpioinfo("Writing %d\n", (int)value); - - stm32_gpiowrite(g_gpiooutputs[stm32gpio->id], value); - return OK; -} -#endif - -#if BOARD_NGPIOINT > 0 -static int gpint_read(struct gpio_dev_s *dev, bool *value) -{ - struct stm32gpint_dev_s *stm32gpint = - (struct stm32gpint_dev_s *)dev; - - DEBUGASSERT(stm32gpint != NULL && value != NULL); - DEBUGASSERT(stm32gpint->stm32gpio.id < BOARD_NGPIOINT); - gpioinfo("Reading int pin...\n"); - - *value = stm32_gpioread(g_gpiointinputs[stm32gpint->stm32gpio.id]); - return OK; -} - -static int gpint_attach(struct gpio_dev_s *dev, - pin_interrupt_t callback) -{ - struct stm32gpint_dev_s *stm32gpint = - (struct stm32gpint_dev_s *)dev; - - gpioinfo("Attaching the callback\n"); - - /* Make sure the interrupt is disabled */ - - stm32_gpiosetevent(g_gpiointinputs[stm32gpint->stm32gpio.id], false, - false, false, NULL, NULL); - - gpioinfo("Attach %p\n", callback); - stm32gpint->callback = callback; - return OK; -} - -static int gpint_enable(struct gpio_dev_s *dev, bool enable) -{ - struct stm32gpint_dev_s *stm32gpint = - (struct stm32gpint_dev_s *)dev; - - if (enable) - { - if (stm32gpint->callback != NULL) - { - gpioinfo("Enabling the interrupt\n"); - - /* Configure the interrupt for rising edge */ - - stm32_gpiosetevent(g_gpiointinputs[stm32gpint->stm32gpio.id], - true, false, false, stm32gpio_interrupt, - &g_gpint[stm32gpint->stm32gpio.id]); - } - } - else - { - gpioinfo("Disable the interrupt\n"); - stm32_gpiosetevent(g_gpiointinputs[stm32gpint->stm32gpio.id], - false, false, false, NULL, NULL); - } - - return OK; -} -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_gpio_initialize - * - * Description: - * Initialize GPIO drivers for use with /apps/examples/gpio - * - ****************************************************************************/ - -int stm32_gpio_initialize(void) -{ - int i; - int pincount = 0; - -#if BOARD_NGPIOIN > 0 - for (i = 0; i < BOARD_NGPIOIN; i++) - { - /* Setup and register the GPIO pin */ - - g_gpin[i].gpio.gp_pintype = GPIO_INPUT_PIN; - g_gpin[i].gpio.gp_ops = &gpin_ops; - g_gpin[i].id = i; - gpio_pin_register(&g_gpin[i].gpio, pincount); - - /* Configure the pin that will be used as input */ - - stm32_configgpio(g_gpioinputs[i]); - - pincount++; - } -#endif - -#if BOARD_NGPIOOUT > 0 - for (i = 0; i < BOARD_NGPIOOUT; i++) - { - /* Setup and register the GPIO pin */ - - g_gpout[i].gpio.gp_pintype = GPIO_OUTPUT_PIN; - g_gpout[i].gpio.gp_ops = &gpout_ops; - g_gpout[i].id = i; - gpio_pin_register(&g_gpout[i].gpio, pincount); - - /* Configure the pin that will be used as output */ - - stm32_gpiowrite(g_gpiooutputs[i], 0); - stm32_configgpio(g_gpiooutputs[i]); - - pincount++; - } -#endif - -#if BOARD_NGPIOINT > 0 - for (i = 0; i < BOARD_NGPIOINT; i++) - { - /* Setup and register the GPIO pin */ - - g_gpint[i].stm32gpio.gpio.gp_pintype = GPIO_INTERRUPT_PIN; - g_gpint[i].stm32gpio.gpio.gp_ops = &gpint_ops; - g_gpint[i].stm32gpio.id = i; - gpio_pin_register(&g_gpint[i].stm32gpio.gpio, pincount); - - /* Configure the pin that will be used as interrupt input */ - - stm32_configgpio(g_gpiointinputs[i]); - - pincount++; - } -#endif - - return 0; -} -#endif /* CONFIG_DEV_GPIO && !CONFIG_GPIO_LOWER_HALF */ diff --git a/boards/arm/stm32/nucleo-f446re/src/stm32_pwm.c b/boards/arm/stm32/nucleo-f446re/src/stm32_pwm.c deleted file mode 100644 index 9279bbe6630d5..0000000000000 --- a/boards/arm/stm32/nucleo-f446re/src/stm32_pwm.c +++ /dev/null @@ -1,134 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f446re/src/stm32_pwm.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32_pwm.h" -#include "nucleo-f446re.h" - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_pwm_setup - * - * Description: - * Initialize PWM and register the PWM device. - * - * Return Value: - * OK on success; a negated errno value on failure. - * - ****************************************************************************/ - -int stm32_pwm_setup(void) -{ -#ifdef CONFIG_PWM - struct pwm_lowerhalf_s *pwm; - int ret; - - /* Call stm32_pwminitialize() to get an instance of the PWM interface */ - -#if defined(CONFIG_STM32_TIM1_PWM) - pwm = stm32_pwminitialize(1); - if (!pwm) - { - pwmerr("ERROR: Failed to get the STM32 PWM lower half\n"); - return -ENODEV; - } - - ret = pwm_register("/dev/pwm0", pwm); - if (ret < 0) - { - pwmerr("ERROR: pwm_register failed: %d\n", ret); - return ret; - } -#endif - -#if defined(CONFIG_STM32_TIM2_PWM) - pwm = stm32_pwminitialize(2); - if (!pwm) - { - pwmerr("ERROR: Failed to get the STM32 PWM lower half\n"); - return -ENODEV; - } - - ret = pwm_register("/dev/pwm1", pwm); - if (ret < 0) - { - pwmerr("ERROR: pwm_register failed: %d\n", ret); - return ret; - } -#endif - -#if defined(CONFIG_STM32_TIM3_PWM) - pwm = stm32_pwminitialize(3); - if (!pwm) - { - pwmerr("ERROR: Failed to get the STM32 PWM lower half\n"); - return -ENODEV; - } - - ret = pwm_register("/dev/pwm2", pwm); - if (ret < 0) - { - pwmerr("ERROR: pwm_register failed: %d\n", ret); - return ret; - } -#endif - -#if defined(CONFIG_STM32_TIM4_PWM) - pwm = stm32_pwminitialize(4); - if (!pwm) - { - pwmerr("ERROR: Failed to get the STM32 PWM lower half\n"); - return -ENODEV; - } - - ret = pwm_register("/dev/pwm3", pwm); - if (ret < 0) - { - pwmerr("ERROR: pwm_register failed: %d\n", ret); - return ret; - } - -#endif - - return OK; -#else - return -ENODEV; -#endif -} diff --git a/boards/arm/stm32/nucleo-f446re/src/stm32_romfs.h b/boards/arm/stm32/nucleo-f446re/src/stm32_romfs.h deleted file mode 100644 index edb106e917d84..0000000000000 --- a/boards/arm/stm32/nucleo-f446re/src/stm32_romfs.h +++ /dev/null @@ -1,63 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f446re/src/stm32_romfs.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __BOARDS_ARM_STM32_NUCLEO_F446RE_SRC_STM32_ROMFS_H -#define __BOARDS_ARM_STM32_NUCLEO_F446RE_SRC_STM32_ROMFS_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#ifdef CONFIG_STM32_ROMFS - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#define ROMFS_SECTOR_SIZE 64 - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_romfs_initialize - * - * Description: - * Registers built-in ROMFS image as block device and mounts it. - * - * Returned Value: - * Zero (OK) on success, a negated errno value on error. - * - * Assumptions/Limitations: - * Memory addresses [romfs_data_begin .. romfs_data_begin) should contain - * ROMFS volume data, as included in the assembly snippet above (l. 84). - * - ****************************************************************************/ - -int stm32_romfs_initialize(void); - -#endif /* CONFIG_STM32_ROMFS */ - -#endif /* __BOARDS_ARM_STM32_NUCLEO_F446RE_SRC_STM32_ROMFS_H */ diff --git a/boards/arm/stm32/nucleo-f446re/src/stm32_romfs_initialize.c b/boards/arm/stm32/nucleo-f446re/src/stm32_romfs_initialize.c deleted file mode 100644 index 97b4fd238c999..0000000000000 --- a/boards/arm/stm32/nucleo-f446re/src/stm32_romfs_initialize.c +++ /dev/null @@ -1,141 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f446re/src/stm32_romfs_initialize.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* This file provides contents of an optional ROMFS volume, mounted at boot */ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include - -#include -#include -#include "stm32_romfs.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#ifndef CONFIG_STM32_ROMFS -# error "CONFIG_STM32_ROMFS must be defined" -#else - -#ifndef CONFIG_STM32_ROMFS_IMAGEFILE -# error "CONFIG_STM32_ROMFS_IMAGEFILE must be defined" -#endif - -#ifndef CONFIG_STM32_ROMFS_DEV_MINOR -# error "CONFIG_STM32_ROMFS_DEV_MINOR must be defined" -#endif - -#ifndef CONFIG_STM32_ROMFS_MOUNTPOINT -# error "CONFIG_STM32_ROMFS_MOUNTPOINT must be defined" -#endif - -#define NSECTORS(size) (((size) + ROMFS_SECTOR_SIZE - 1)/ROMFS_SECTOR_SIZE) - -#define STR2(m) #m -#define STR(m) STR2(m) - -#define MKMOUNT_DEVNAME(m) "/dev/ram" STR(m) -#define MOUNT_DEVNAME MKMOUNT_DEVNAME(CONFIG_STM32_ROMFS_DEV_MINOR) - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -__asm__ ( - " .section .rodata, \"a\" \n" - " .balign 16 \n" - " .globl romfs_data_begin \n" - "romfs_data_begin: \n" - " .incbin " STR(CONFIG_STM32_ROMFS_IMAGEFILE)"\n" - " .balign " STR(ROMFS_SECTOR_SIZE) "\n" - " .globl romfs_data_end \n" - "romfs_data_end: \n" - ); - -extern const uint8_t romfs_data_begin[]; -extern const uint8_t romfs_data_end[]; - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_romfs_initialize - * - * Description: - * Registers the aboveincluded binary file as block device. - * Then mounts the block device as ROMFS filesystems. - * - * Returned Value: - * Zero (OK) on success, a negated errno value on error. - * - * Assumptions/Limitations: - * Memory addresses [&romfs_data_begin .. &romfs_data_begin) should contain - * ROMFS volume data, as included in the assembly snippet above (l. 84). - * - ****************************************************************************/ - -int stm32_romfs_initialize(void) -{ - uintptr_t romfs_data_len; - int ret; - - /* Create a ROM disk for the /etc filesystem */ - - romfs_data_len = (uintptr_t)romfs_data_end - (uintptr_t)romfs_data_begin; - - ret = romdisk_register(CONFIG_STM32_ROMFS_DEV_MINOR, romfs_data_begin, - NSECTORS(romfs_data_len), ROMFS_SECTOR_SIZE); - if (ret < 0) - { - ferr("ERROR: romdisk_register failed: %d\n", -ret); - return ret; - } - - /* Mount the file system */ - - finfo("Mounting ROMFS filesystem at target=%s with source=%s\n", - CONFIG_STM32_ROMFS_MOUNTPOINT, MOUNT_DEVNAME); - - ret = nx_mount(MOUNT_DEVNAME, CONFIG_STM32_ROMFS_MOUNTPOINT, - "romfs", MS_RDONLY, NULL); - if (ret < 0) - { - ferr("ERROR: nx_mount(%s,%s,romfs) failed: %d\n", - MOUNT_DEVNAME, CONFIG_STM32_ROMFS_MOUNTPOINT, ret); - return ret; - } - - return OK; -} - -#endif /* CONFIG_STM32_ROMFS */ diff --git a/boards/arm/stm32/nucleo-f446re/src/stm32_spi.c b/boards/arm/stm32/nucleo-f446re/src/stm32_spi.c deleted file mode 100644 index e713d51ed0ca6..0000000000000 --- a/boards/arm/stm32/nucleo-f446re/src/stm32_spi.c +++ /dev/null @@ -1,236 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f446re/src/stm32_spi.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include - -#include -#include - -#include "arm_internal.h" -#include "chip.h" -#include "stm32.h" - -#include "nucleo-f446re.h" - -#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || \ - defined(CONFIG_STM32_SPI3) - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/* Global driver instances */ - -#ifdef CONFIG_STM32_SPI1 -struct spi_dev_s *g_spi1; -#endif -#ifdef CONFIG_STM32_SPI2 -struct spi_dev_s *g_spi2; -#endif -#ifdef CONFIG_STM32_SPI3 -struct spi_dev_s *g_spi3; -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_spidev_initialize - * - * Description: - * Called to configure SPI chip select GPIO pins for the Nucleo-F401RE and - * Nucleo-F411RE boards. - * - ****************************************************************************/ - -void weak_function stm32_spidev_initialize(void) -{ -#ifdef CONFIG_STM32_SPI1 - /* Configure SPI-based devices */ - - g_spi1 = stm32_spibus_initialize(1); - if (!g_spi1) - { - spierr("ERROR: FAILED to initialize SPI port 1\n"); - } - -#ifdef HAVE_MMCSD - stm32_configgpio(GPIO_SPI_CS_SD_CARD); -#endif -#endif - -#ifdef CONFIG_STM32_SPI2 - /* Configure SPI-based devices */ - - g_spi2 = stm32_spibus_initialize(2); -#endif - -#ifdef CONFIG_STM32_SPI3 - /* Configure SPI-based devices */ - - g_spi3 = stm32_spibus_initialize(3); - -#ifdef HAVE_LCD - stm32_configgpio(GPIO_LCD_CS); - stm32_configgpio(GPIO_LCD_RS); -#endif - -#endif -} - -/**************************************************************************** - * Name: stm32_spi1/2/3select and stm32_spi1/2/3status - * - * Description: - * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status - * must be provided by board-specific logic. They are implementations of - * the select and status methods of the SPI interface defined by struct - * spi_ops_s (see include/nuttx/spi/spi.h). All other methods (including - * stm32_spibus_initialize()) are provided by common STM32 logic. To use - * this common SPI logic on your board: - * - * 1. Provide logic in stm32_boardinitialize() to configure SPI chip - * select pins. - * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() functions - * in your board-specific logic. These functions will perform chip - * selection and status operations using GPIOs in the way your board is - * configured. - * 3. Add a calls to stm32_spibus_initialize() in your low level - * application initialization logic - * 4. The handle returned by stm32_spibus_initialize() may then be used to - * bind the SPI driver to higher level logic (e.g., calling - * mmcsd_spislotinitialize(), for example, will bind the SPI driver to - * the SPI MMC/SD driver). - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_SPI1 -void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, - bool selected) -{ - spiinfo("devid: %d CS: %s\n", - (int)devid, selected ? "assert" : "de-assert"); - -#ifdef HAVE_MMCSD - if (devid == SPIDEV_MMCSD(0)) - { - stm32_gpiowrite(GPIO_SPI_CS_SD_CARD, !selected); - } -#endif -} - -uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) -{ - return 0; -} -#endif - -#ifdef CONFIG_STM32_SPI2 -void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid, - bool selected) -{ - spiinfo("devid: %d CS: %s\n", - (int)devid, selected ? "assert" : "de-assert"); -} - -uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) -{ - return 0; -} -#endif - -#ifdef CONFIG_STM32_SPI3 -void stm32_spi3select(struct spi_dev_s *dev, uint32_t devid, - bool selected) -{ - spiinfo("devid: %d CS: %s\n", - (int)devid, selected ? "assert" : "de-assert"); - -#ifdef HAVE_LCD - stm32_gpiowrite(GPIO_LCD_CS, !selected); -#endif -} - -uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid) -{ - return 0; -} -#endif - -/**************************************************************************** - * Name: stm32_spi1cmddata - * - * Description: - * Set or clear the SH1101A A0 or SD1306 D/C n bit to select data (true) - * or command (false). This function must be provided by platform-specific - * logic. This is an implementation of the cmddata method of the SPI - * interface defined by struct spi_ops_s (see include/nuttx/spi/spi.h). - * - * Input Parameters: - * - * spi - SPI device that controls the bus the device that requires the CMD/ - * DATA selection. - * devid - If there are multiple devices on the bus, this selects which one - * to select cmd or data. NOTE: This design restricts, for example, - * one one SPI display per SPI bus. - * cmd - true: select command; false: select data - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef CONFIG_SPI_CMDDATA -#ifdef CONFIG_STM32_SPI1 -int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) -{ - return OK; -} -#endif - -#ifdef CONFIG_STM32_SPI2 -int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) -{ - return OK; -} -#endif - -#ifdef CONFIG_STM32_SPI3 -int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) -{ - stm32_gpiowrite(GPIO_LCD_RS, !cmd); - return OK; -} -#endif -#endif /* CONFIG_SPI_CMDDATA */ - -#endif /* CONFIG_STM32_SPI1 || CONFIG_STM32_SPI2 || CONFIG_STM32_SPI3 */ diff --git a/boards/arm/stm32/nucleo-f446re/src/stm32_userleds.c b/boards/arm/stm32/nucleo-f446re/src/stm32_userleds.c deleted file mode 100644 index 4a75e98c49689..0000000000000 --- a/boards/arm/stm32/nucleo-f446re/src/stm32_userleds.c +++ /dev/null @@ -1,105 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f446re/src/stm32_userleds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include - -#include -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32.h" -#include "nucleo-f446re.h" - -#ifndef CONFIG_ARCH_LEDS - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* This array maps an LED number to GPIO pin configuration */ - -static const uint32_t g_ledcfg[BOARD_NLEDS] = -{ - GPIO_LD2, -}; - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_userled_initialize - ****************************************************************************/ - -uint32_t board_userled_initialize(void) -{ - int i; - - /* Configure LED GPIOs for output */ - - for (i = 0; i < BOARD_NLEDS; i++) - { - stm32_configgpio(g_ledcfg[i]); - } - - return BOARD_NLEDS; -} - -/**************************************************************************** - * Name: board_userled - ****************************************************************************/ - -void board_userled(int led, bool ledon) -{ - if ((unsigned)led < BOARD_NLEDS) - { - stm32_gpiowrite(g_ledcfg[led], ledon); - } -} - -/**************************************************************************** - * Name: board_userled_all - ****************************************************************************/ - -void board_userled_all(uint32_t ledset) -{ - int i; - - /* Configure LED GPIOs for output */ - - for (i = 0; i < BOARD_NLEDS; i++) - { - stm32_gpiowrite(g_ledcfg[i], (ledset & (1 << i)) != 0); - } -} - -#endif /* !CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/nucleo-g431kb/CMakeLists.txt b/boards/arm/stm32/nucleo-g431kb/CMakeLists.txt deleted file mode 100644 index ce86b7005c12d..0000000000000 --- a/boards/arm/stm32/nucleo-g431kb/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/nucleo-g431kb/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32/nucleo-g431kb/configs/comp/defconfig b/boards/arm/stm32/nucleo-g431kb/configs/comp/defconfig deleted file mode 100644 index 5631b4f1a607b..0000000000000 --- a/boards/arm/stm32/nucleo-g431kb/configs/comp/defconfig +++ /dev/null @@ -1,48 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -CONFIG_ANALOG=y -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="nucleo-g431kb" -CONFIG_ARCH_BOARD_NUCLEO_G431KB=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32G431K=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=5483 -CONFIG_BUILTIN=y -CONFIG_COMP=y -CONFIG_DAC=y -CONFIG_DEFAULT_SMALL=y -CONFIG_EXAMPLES_DAC=y -CONFIG_EXAMPLES_DAC_DEVPATH="/dev/dac5" -CONFIG_FILE_STREAM=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_RAM_SIZE=22528 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=15 -CONFIG_START_MONTH=6 -CONFIG_START_YEAR=2021 -CONFIG_STM32_COMP2=y -CONFIG_STM32_COMP2_HYST=3 -CONFIG_STM32_COMP2_INM=4 -CONFIG_STM32_COMP2_OUT=y -CONFIG_STM32_DAC3=y -CONFIG_STM32_DAC3CH2=y -CONFIG_STM32_DAC3CH2_MODE=3 -CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32_FORCEPOWER=y -CONFIG_STM32_JTAG_FULL_ENABLE=y -CONFIG_STM32_USART2=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/nucleo-g431kb/configs/nsh/defconfig b/boards/arm/stm32/nucleo-g431kb/configs/nsh/defconfig deleted file mode 100644 index 2470af3cfacf1..0000000000000 --- a/boards/arm/stm32/nucleo-g431kb/configs/nsh/defconfig +++ /dev/null @@ -1,47 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -# CONFIG_NSH_DISABLE_IFCONFIG is not set -# CONFIG_NSH_DISABLE_PS is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="nucleo-g431kb" -CONFIG_ARCH_BOARD_NUCLEO_G431KB=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32G431K=y -CONFIG_ARCH_INTERRUPTSTACK=2048 -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=8499 -CONFIG_BUILTIN=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_LTO_FULL=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=22528 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=14 -CONFIG_START_MONTH=10 -CONFIG_START_YEAR=2014 -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_USART2=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_TESTING_OSTEST=y -CONFIG_TESTING_OSTEST_STACKSIZE=1024 -CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/nucleo-g431kb/configs/pwm/defconfig b/boards/arm/stm32/nucleo-g431kb/configs/pwm/defconfig deleted file mode 100644 index b8e9c1184c3ee..0000000000000 --- a/boards/arm/stm32/nucleo-g431kb/configs/pwm/defconfig +++ /dev/null @@ -1,40 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="nucleo-g431kb" -CONFIG_ARCH_BOARD_NUCLEO_G431KB=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32G431K=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=5483 -CONFIG_BUILTIN=y -CONFIG_DEFAULT_SMALL=y -CONFIG_EXAMPLES_PWM=y -CONFIG_FILE_STREAM=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_PWM=y -CONFIG_RAM_SIZE=22528 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=14 -CONFIG_START_YEAR=2021 -CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32_FORCEPOWER=y -CONFIG_STM32_JTAG_FULL_ENABLE=y -CONFIG_STM32_TIM1=y -CONFIG_STM32_TIM1_CH1OUT=y -CONFIG_STM32_TIM1_PWM=y -CONFIG_STM32_USART2=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/nucleo-g431kb/include/board.h b/boards/arm/stm32/nucleo-g431kb/include/board.h deleted file mode 100644 index c5e339abd031c..0000000000000 --- a/boards/arm/stm32/nucleo-g431kb/include/board.h +++ /dev/null @@ -1,258 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-g431kb/include/board.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __BOARDS_ARM_STM32_NUCLEO_G431KB_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32_NUCLEO_G431KB_INCLUDE_BOARD_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Clocking *****************************************************************/ - -/* The Nucleo-G431KB supports four ways to configure high-speed clock - * - * - HSI configuration (default): 16 MHz high-speed internal RC oscillator. - * - HSE bypass configuration (from ST-LINK): The input clock is the - * ST-LINK MCO output. The frequency is fixed to 25 MHz, and connected - * to the PF0-OSC_IN of the STM32G4 microcontroller. - * - HSE bypass configuration (from ARDUINO D7): The clock is coming from - * an external oscillator through the pin PF0 (ARDUINO D7 pin 10 of the - * CN4 connector). - * - HSE oscillator configuration: The clock is provided by an external - * 24MHz crystal (X2) available in the PCB. - */ - -#define STM32_BOARD_XTAL 24000000ul /* 24MHz */ - -#define STM32_HSI_FREQUENCY 16000000ul /* 16MHz */ -#define STM32_LSI_FREQUENCY 32000 /* 32kHz */ -#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL -#undef STM32_LSE_FREQUENCY /* Not available on this board */ - -/* Main PLL Configuration. - * - * PLL source is HSI = 16MHz - * PLLN = 85, PLLM = 4, PLLP = 10, PLLQ = 2, PLLR = 2 - * - * f(VCO Clock) = f(PLL Clock Input) x (PLLN / PLLM) - * f(PLL_P) = f(VCO Clock) / PLLP - * f(PLL_Q) = f(VCO Clock) / PLLQ - * f(PLL_R) = f(VCO Clock) / PLLR - * - * Where: - * 8 <= PLLN <= 127 - * 1 <= PLLM <= 16 - * PLLP = 2 through 31 - * PLLQ = 2, 4, 6, or 8 - * PLLR = 2, 4, 6, or 8 - * - * Do not exceed 170MHz on f(PLL_P), f(PLL_Q), or f(PLL_R). - * 64MHz <= f(VCO Clock) <= 344MHz. - * - * Given the above: - * - * f(VCO Clock) = HSI x PLLN / PLLM - * = 16MHz x 85 / 4 - * = 340MHz - * - * PLLPCLK = f(VCO Clock) / PLLP - * = 340MHz / 10 - * = 34MHz - * (May be used for ADC) - * - * PLLQCLK = f(VCO Clock) / PLLQ - * = 340MHz / 2 - * = 170MHz - * (May be used for QUADSPI, FDCAN, SAI1, I2S3. If set to - * 48MHz, may be used for USB, RNG.) - * - * PLLRCLK = f(VCO Clock) / PLLR - * = 340MHz / 2 - * = 170MHz - * (May be used for SYSCLK and most peripherals.) - */ - -#define STM32_PLLCFGR_PLLSRC RCC_PLLCFGR_PLLSRC_HSI -#define STM32_PLLCFGR_PLLCFG (RCC_PLLCFGR_PLLPEN | \ - RCC_PLLCFGR_PLLQEN | \ - RCC_PLLCFGR_PLLREN) - -#define STM32_PLLCFGR_PLLN RCC_PLLCFGR_PLLN(85) -#define STM32_PLLCFGR_PLLM RCC_PLLCFGR_PLLM(4) -#define STM32_PLLCFGR_PLLP RCC_PLLCFGR_PLLPDIV(10) -#define STM32_PLLCFGR_PLLQ RCC_PLLCFGR_PLLQ_2 -#define STM32_PLLCFGR_PLLR RCC_PLLCFGR_PLLR_2 - -#define STM32_VCO_FREQUENCY ((STM32_HSI_FREQUENCY / 4) * 85) -#define STM32_PLLP_FREQUENCY (STM32_VCO_FREQUENCY / 10) -#define STM32_PLLQ_FREQUENCY (STM32_VCO_FREQUENCY / 2) -#define STM32_PLLR_FREQUENCY (STM32_VCO_FREQUENCY / 2) - -/* Use the PLL and set the SYSCLK source to be PLLR (170MHz) */ - -#define STM32_SYSCLK_SW RCC_CFGR_SW_PLL -#define STM32_SYSCLK_SWS RCC_CFGR_SWS_PLL -#define STM32_SYSCLK_FREQUENCY STM32_PLLR_FREQUENCY - -/* AHB clock (HCLK) is SYSCLK (170MHz) */ - -#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK -#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY - -/* APB1 clock (PCLK1) is HCLK (170MHz) */ - -#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK -#define STM32_PCLK1_FREQUENCY STM32_HCLK_FREQUENCY - -/* APB2 clock (PCLK2) is HCLK (170MHz) */ - -#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK -#define STM32_PCLK2_FREQUENCY STM32_HCLK_FREQUENCY - -/* APB2 timers 1, 8, 20 and 15-17 will receive PCLK2. */ - -/* Timers driven from APB2 will be PCLK2 */ - -#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB1_TIM15_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB1_TIM16_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB1_TIM17_CLKIN (STM32_PCLK2_FREQUENCY) - -/* APB1 timers 2-7 will be twice PCLK1 */ - -#define STM32_APB1_TIM2_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM4_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (STM32_PCLK1_FREQUENCY) - -/* USB divider -- Divide PLL clock by 1.5 */ - -#define STM32_CFGR_USBPRE 0 - -/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx - * otherwise frequency is 2xAPBx. - */ - -#define BOARD_TIM1_FREQUENCY (STM32_PCLK2_FREQUENCY) -#define BOARD_TIM2_FREQUENCY (STM32_PCLK1_FREQUENCY) -#define BOARD_TIM3_FREQUENCY (STM32_PCLK1_FREQUENCY) -#define BOARD_TIM4_FREQUENCY (STM32_PCLK1_FREQUENCY) -#define BOARD_TIM5_FREQUENCY (STM32_PCLK1_FREQUENCY) -#define BOARD_TIM6_FREQUENCY (STM32_PCLK1_FREQUENCY) -#define BOARD_TIM7_FREQUENCY (STM32_PCLK1_FREQUENCY) -#define BOARD_TIM8_FREQUENCY (STM32_PCLK2_FREQUENCY) -#define BOARD_TIM15_FREQUENCY (STM32_PCLK2_FREQUENCY) -#define BOARD_TIM16_FREQUENCY (STM32_PCLK2_FREQUENCY) -#define BOARD_TIM17_FREQUENCY (STM32_PCLK2_FREQUENCY) -#define BOARD_TIM20_FREQUENCY (STM32_PCLK2_FREQUENCY) - -/* LED definitions **********************************************************/ - -/* The Nucleo-G431KB board has only one user LED, LD2. LD2 is a green LED - * connected to the following STM32G4 pins - * - PB8 (default) - * - PB3 - * It is also connected to Arduino signal D13. - * - * If CONFIG_ARCH_LEDS is not defined, then the user can control this LED in - * any way. The following definitions are used to access individual LEDs. - */ - -/* LED index values for use with board_userled() */ - -#define BOARD_LED2 0 /* User LD2 */ -#define BOARD_NLEDS 1 - -/* LED bits for use with board_userled_all() */ - -#define BOARD_LED2_BIT (1 << BOARD_LED2) - -/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the LED on board - * the Nucleo-G431KB. The following definitions describe how NuttX controls - * the LED: - * - * SYMBOL Meaning LED1 state - * ------------------ ----------------------- ---------- - * LED_STARTED NuttX has been started OFF - * LED_HEAPALLOCATE Heap has been allocated OFF - * LED_IRQSENABLED Interrupts enabled OFF - * LED_STACKCREATED Idle stack created ON - * LED_INIRQ In an interrupt No change - * LED_SIGNAL In a signal handler No change - * LED_ASSERTION An assertion failed No change - * LED_PANIC The system has crashed Blinking - * LED_IDLE STM32 is in sleep mode Not used - */ - -#define LED_STARTED 0 -#define LED_HEAPALLOCATE 0 -#define LED_IRQSENABLED 0 -#define LED_STACKCREATED 1 -#define LED_INIRQ 2 -#define LED_SIGNAL 2 -#define LED_ASSERTION 2 -#define LED_PANIC 1 - -/* Button definitions *******************************************************/ - -/* The Nucleo G431KB don't have buttons that are controllable by software: - * - * B1 RESET: push button connected to NRST is used to RESET the - * STM32G431KB. - */ - -/* Alternate function pin selections ****************************************/ - -/* USART2 (STLINK Virtual COM Port) */ - -#define GPIO_USART2_TX GPIO_USART2_TX_1 /* PA2 */ -#define GPIO_USART2_RX GPIO_USART2_RX_1 /* PA3 */ - -/* PWM configuration ********************************************************/ - -/* TIM1 PWM */ - -#define GPIO_TIM1_CH1OUT (GPIO_TIM1_CH1OUT_1|GPIO_SPEED_50MHz) /* PA8 */ - -/* Comparators configuration ************************************************/ - -#define GPIO_COMP2_OUT GPIO_COMP2_OUT_3 /* PA12 */ -#define GPIO_COMP2_INP GPIO_COMP2_INP_2 /* PA7 */ -#define GPIO_COMP2_INM GPIO_COMP2_INM_2 /* PA5 check solder bridge SB2 */ - -/* DMA channels *************************************************************/ - -/* USART2 */ - -#define DMACHAN_USART2_TX DMAMAP_DMA12_USART2TX_0 /* DMA1 */ -#define DMACHAN_USART2_RX DMAMAP_DMA12_USART2RX_0 /* DMA1 */ - -#endif /* __BOARDS_ARM_STM32_NUCLEO_G431KB_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32/nucleo-g431kb/scripts/Make.defs b/boards/arm/stm32/nucleo-g431kb/scripts/Make.defs deleted file mode 100644 index 569fe825159c5..0000000000000 --- a/boards/arm/stm32/nucleo-g431kb/scripts/Make.defs +++ /dev/null @@ -1,51 +0,0 @@ -############################################################################ -# boards/arm/stm32/nucleo-g431kb/scripts/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/.config -include $(TOPDIR)/tools/Config.mk -include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs - -ifeq ($(CONFIG_STM32_DFU),y) - LDSCRIPT = ld.script.dfu -else - LDSCRIPT = ld.script -endif - -ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) - -ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 - -CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) -CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) -CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -AFLAGS := $(CFLAGS) -D__ASSEMBLY__ - -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections -LDNXFLATFLAGS = -e main -s 2048 - -# Embed absolute path to source file in debug information so that Eclipse -# source level debugging won't get confused. See: -# https://stackoverflow.com/questions/1275476/gcc-gdb-how-to-embed-absolute-path-to-source-file-in-debug-information -CFLAGS += -fdebug-prefix-map=..=$(readlink -f ..) diff --git a/boards/arm/stm32/nucleo-g431kb/scripts/ld.script b/boards/arm/stm32/nucleo-g431kb/scripts/ld.script deleted file mode 100644 index b7f4d0667e9eb..0000000000000 --- a/boards/arm/stm32/nucleo-g431kb/scripts/ld.script +++ /dev/null @@ -1,139 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-g431kb/scripts/ld.script - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* The STM32G431KB has 128 KiB of FLASH beginning at address 0x0800:0000. - * - * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 - * where the code expects to begin execution by jumping to the entry point in - * the 0x0800:0000 address range. - * - * The STM32G431KB has a total of 32 KiB of SRAM in three separate areas: - * - * 1) 16 KiB SRAM1 mapped at 0x2000:0000 thru 0x2000:3fff. - * 2) 6 KiB SRAM2 mapped at 0x2000:4000 thru 0x2000:57ff. - * - * CCM SRAM (Routine Booster): - * - * 3) 10 KiB CCM SRAM mapped at 0x1000:0000 thru 0x1000:27ff - * but also aliased at at 0x2000:5800 thru 0x2000:7fff to be contiguous - * with the SRAM1 and SRAM2. - * - * Because SRAM1 and SRAM2 are contiguous, they are treated as one region - * by this logic. - * - * CCM SRAM is also contiguous to SRAM1 and SRAM2, however it is excluded - * from this linker script, to keep it reserved for special uses in code. - * REVISIT: Is this the correct way to handle CCM SRAM? - */ - -MEMORY -{ - flash (rx) : ORIGIN = 0x08000000, LENGTH = 128K - sram (rwx) : ORIGIN = 0x20000000, LENGTH = 22K -} - -OUTPUT_ARCH(arm) -EXTERN(_vectors) -ENTRY(_stext) - -SECTIONS -{ - .text : { - _stext = ABSOLUTE(.); - *(.vectors) - *(.text .text.*) - *(.fixup) - *(.gnu.warning) - *(.rodata .rodata.*) - *(.gnu.linkonce.t.*) - *(.glue_7) - *(.glue_7t) - *(.got) - *(.gcc_except_table) - *(.gnu.linkonce.r.*) - _etext = ABSOLUTE(.); - } > flash - - .init_section : ALIGN(4) { - _sinit = ABSOLUTE(.); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) - KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) - _einit = ABSOLUTE(.); - } > flash - - .ARM.extab : ALIGN(4) { - *(.ARM.extab*) - } > flash - - .ARM.exidx : ALIGN(4) { - __exidx_start = ABSOLUTE(.); - *(.ARM.exidx*) - __exidx_end = ABSOLUTE(.); - } > flash - - .tdata : { - _stdata = ABSOLUTE(.); - *(.tdata .tdata.* .gnu.linkonce.td.*); - _etdata = ABSOLUTE(.); - } > flash - - .tbss : { - _stbss = ABSOLUTE(.); - *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); - _etbss = ABSOLUTE(.); - } > flash - - _eronly = ABSOLUTE(.); - - .data : ALIGN(4) { - _sdata = ABSOLUTE(.); - *(.data .data.*) - *(.gnu.linkonce.d.*) - CONSTRUCTORS - . = ALIGN(4); - _edata = ABSOLUTE(.); - } > sram AT > flash - - .bss : ALIGN(4) { - _sbss = ABSOLUTE(.); - *(.bss .bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - . = ALIGN(4); - _ebss = ABSOLUTE(.); - } > sram - - /* Stabs debugging sections. */ - - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_info 0 : { *(.debug_info) } - .debug_line 0 : { *(.debug_line) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_aranges 0 : { *(.debug_aranges) } -} diff --git a/boards/arm/stm32/nucleo-g431kb/src/CMakeLists.txt b/boards/arm/stm32/nucleo-g431kb/src/CMakeLists.txt deleted file mode 100644 index e45962dfe2070..0000000000000 --- a/boards/arm/stm32/nucleo-g431kb/src/CMakeLists.txt +++ /dev/null @@ -1,45 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/nucleo-g431kb/src/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -set(SRCS stm32_boot.c stm32_bringup.c) - -if(CONFIG_ARCH_LEDS) - list(APPEND SRCS stm32_autoleds.c) -else() - list(APPEND SRCS stm32_userleds.c) -endif() - -if(CONFIG_PWM) - list(APPEND SRCS stm32_pwm.c) -endif() - -if(CONFIG_STM32_COMP) - list(APPEND SRCS stm32_comp.c) -endif() - -if(CONFIG_STM32_DAC) - list(APPEND SRCS stm32_dac.c) -endif() - -target_sources(board PRIVATE ${SRCS}) - -set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/ld.script") diff --git a/boards/arm/stm32/nucleo-g431kb/src/Make.defs b/boards/arm/stm32/nucleo-g431kb/src/Make.defs deleted file mode 100644 index 7aa1045c6a8c3..0000000000000 --- a/boards/arm/stm32/nucleo-g431kb/src/Make.defs +++ /dev/null @@ -1,48 +0,0 @@ -############################################################################ -# boards/arm/stm32/nucleo-g431kb/src/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/Make.defs - -ASRCS = -CSRCS = stm32_boot.c stm32_bringup.c - -ifeq ($(CONFIG_ARCH_LEDS),y) -CSRCS += stm32_autoleds.c -else -CSRCS += stm32_userleds.c -endif - -ifeq ($(CONFIG_PWM),y) -CSRCS += stm32_pwm.c -endif - -ifeq ($(CONFIG_STM32_COMP),y) -CSRCS += stm32_comp.c -endif - -ifeq ($(CONFIG_STM32_DAC),y) -CSRCS += stm32_dac.c -endif - -DEPPATH += --dep-path board -VPATH += :board -CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/nucleo-g431kb/src/stm32_autoleds.c b/boards/arm/stm32/nucleo-g431kb/src/stm32_autoleds.c deleted file mode 100644 index fbb97ddcaeb99..0000000000000 --- a/boards/arm/stm32/nucleo-g431kb/src/stm32_autoleds.c +++ /dev/null @@ -1,80 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-g431kb/src/stm32_autoleds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include "stm32.h" -#include "nucleo-g431kb.h" - -#if defined(CONFIG_ARCH_LEDS) - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_autoled_initialize - ****************************************************************************/ - -void board_autoled_initialize(void) -{ - /* Configure LED GPIOs for output */ - - stm32_configgpio(GPIO_LED1); -} - -/**************************************************************************** - * Name: board_autoled_on - ****************************************************************************/ - -void board_autoled_on(int led) -{ - if (led == BOARD_LED2) - { - stm32_gpiowrite(GPIO_LED1, true); - } -} - -/**************************************************************************** - * Name: board_autoled_off - ****************************************************************************/ - -void board_autoled_off(int led) -{ - if (led == BOARD_LED2) - { - stm32_gpiowrite(GPIO_LED1, false); - } -} - -#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/nucleo-g431kb/src/stm32_boot.c b/boards/arm/stm32/nucleo-g431kb/src/stm32_boot.c deleted file mode 100644 index 4a75293c2de5b..0000000000000 --- a/boards/arm/stm32/nucleo-g431kb/src/stm32_boot.c +++ /dev/null @@ -1,95 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-g431kb/src/stm32_boot.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include "nucleo-g431kb.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_boardinitialize - * - * Description: - * All STM32 architectures must provide the following entry point. This - * entry point is called early in the initialization -- after all memory - * has been configured and mapped but before any devices have been - * initialized. - * - ****************************************************************************/ - -void stm32_boardinitialize(void) -{ - /* Configure on-board LEDs if LED support has been selected. */ - -#ifdef CONFIG_ARCH_LEDS - board_autoled_initialize(); -#endif -} - -/**************************************************************************** - * Name: board_late_initialize - * - * Description: - * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional - * initialization call will be performed in the boot-up sequence to a - * function called board_late_initialize(). board_late_initialize() will - * be called immediately after up_initialize() is called and just before - * the initial application is started. This additional initialization - * phase may be used, for example, to initialize board-specific device - * drivers. - * - ****************************************************************************/ - -#ifdef CONFIG_BOARD_LATE_INITIALIZE -void board_late_initialize(void) -{ - /* Perform board-specific initialization */ - - stm32_bringup(); -} -#endif diff --git a/boards/arm/stm32/nucleo-g431kb/src/stm32_bringup.c b/boards/arm/stm32/nucleo-g431kb/src/stm32_bringup.c deleted file mode 100644 index 7def155d6554a..0000000000000 --- a/boards/arm/stm32/nucleo-g431kb/src/stm32_bringup.c +++ /dev/null @@ -1,112 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-g431kb/src/stm32_bringup.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include - -#ifdef CONFIG_USERLED -# include -#endif - -#include "nucleo-g431kb.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#undef HAVE_LEDS - -#if !defined(CONFIG_ARCH_LEDS) && defined(CONFIG_USERLED_LOWER) -# define HAVE_LEDS 1 -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_bringup - * - * Description: - * Perform architecture-specific initialization - * - * CONFIG_BOARD_LATE_INITIALIZE=y : - * Called from board_late_initialize(). - * - ****************************************************************************/ - -int stm32_bringup(void) -{ - int ret; - -#ifdef HAVE_LEDS - /* Register the LED driver */ - - ret = userled_lower_initialize(LED_DRIVER_PATH); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: userled_lower_initialize() failed: %d\n", ret); - return ret; - } -#endif - -#ifdef CONFIG_PWM - /* Initialize PWM and register the PWM driver. */ - - ret = stm32_pwm_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_pwm_setup failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_STM32_COMP - /* Initialize and register the COMP driver. */ - - ret = stm32_comp_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_comp_setup failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_DAC - /* Initialize and register the DAC driver. */ - - ret = stm32_dac_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_dac_setup failed: %d\n", ret); - } -#endif - - UNUSED(ret); - return OK; -} diff --git a/boards/arm/stm32/nucleo-g431kb/src/stm32_comp.c b/boards/arm/stm32/nucleo-g431kb/src/stm32_comp.c deleted file mode 100644 index 077454afccd8f..0000000000000 --- a/boards/arm/stm32/nucleo-g431kb/src/stm32_comp.c +++ /dev/null @@ -1,148 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-g431kb/src/stm32_comp.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include "stm32.h" - -#if defined(CONFIG_STM32_COMP) && (defined(CONFIG_STM32_COMP1) || \ - defined(CONFIG_STM32_COMP2) || \ - defined(CONFIG_STM32_COMP3) || \ - defined(CONFIG_STM32_COMP4)) - -#ifdef CONFIG_STM32_COMP1 -# if defined(CONFIG_STM32_COMP2) || \ - defined(CONFIG_STM32_COMP3) || \ - defined(CONFIG_STM32_COMP4) -# error "Currently only one COMP device supported" -# endif -#elif CONFIG_STM32_COMP2 -# if defined(CONFIG_STM32_COMP1) || \ - defined(CONFIG_STM32_COMP3) || \ - defined(CONFIG_STM32_COMP4) -# error "Currently only one COMP device supported" -# endif -#elif CONFIG_STM32_COMP3 -# if defined(CONFIG_STM32_COMP1) || \ - defined(CONFIG_STM32_COMP2) || \ - defined(CONFIG_STM32_COMP4) -# error "Currently only one COMP device supported" -# endif -#elif CONFIG_STM32_COMP4 -# if defined(CONFIG_STM32_COMP1) || \ - defined(CONFIG_STM32_COMP2) || \ - defined(CONFIG_STM32_COMP3) -# error "Currently only one COMP device supported" -# endif -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_comp_setup - * - * Description: - * Initialize COMP - * - ****************************************************************************/ - -int stm32_comp_setup(void) -{ - static bool initialized = false; - struct comp_dev_s *comp = NULL; - int ret = OK; - - if (!initialized) - { - /* Get the comparator interface */ - -#ifdef CONFIG_STM32_COMP1 - comp = stm32_compinitialize(1); - if (comp == NULL) - { - aerr("ERROR: Failed to get COMP%d interface\n", 1); - return -ENODEV; - } -#endif - -#ifdef CONFIG_STM32_COMP2 - comp = stm32_compinitialize(2); - if (comp == NULL) - { - aerr("ERROR: Failed to get COMP%d interface\n", 2); - return -ENODEV; - } -#endif - -#ifdef CONFIG_STM32_COMP3 - comp = stm32_compinitialize(3); - if (comp == NULL) - { - aerr("ERROR: Failed to get COMP%d interface\n", 3); - return -ENODEV; - } -#endif - -#ifdef CONFIG_STM32_COMP4 - comp = stm32_compinitialize(4); - if (comp == NULL) - { - aerr("ERROR: Failed to get COMP%d interface\n", 4); - return -ENODEV; - } -#endif - -#ifdef CONFIG_COMP - - /* Register the comparator character driver at /dev/comp0 */ - - ret = comp_register("/dev/comp0", comp); - if (ret < 0) - { - aerr("ERROR: comp_register failed: %d\n", ret); - return ret; - } -#endif - - initialized = true; - } - - return ret; -} - -#endif /* CONFIG_COMP && (CONFIG_STM32_COMP1 || - * CONFIG_STM32_COMP2 || - * CONFIG_STM32_COMP3 || - * CONFIG_STM32_COMP4) */ diff --git a/boards/arm/stm32/nucleo-g431kb/src/stm32_dac.c b/boards/arm/stm32/nucleo-g431kb/src/stm32_dac.c deleted file mode 100644 index 97790997116e4..0000000000000 --- a/boards/arm/stm32/nucleo-g431kb/src/stm32_dac.c +++ /dev/null @@ -1,114 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-g431kb/src/stm32_dac.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include -#include - -#include -#include - -#include "stm32_dac.h" -#include "nucleo-g431kb.h" - -#ifdef CONFIG_DAC - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -#ifdef CONFIG_STM32_DAC1CH1 -static struct dac_dev_s *g_dac1; -#endif - -#ifdef CONFIG_STM32_DAC3CH2 -static struct dac_dev_s *g_dac5; -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_dac_setup - * - * Description: - * Initialize and register the DAC driver. - * - * Input parameters: - * devpath - The full path to the driver to register. E.g., "/dev/dac0" - * - * Returned Value: - * Zero (OK) on success; a negated errno value on failure. - * - ****************************************************************************/ - -int stm32_dac_setup(void) -{ - int ret; -#ifdef CONFIG_STM32_DAC1CH1 - g_dac1 = stm32_dacinitialize(1); - if (g_dac1 == NULL) - { - aerr("ERROR: Failed to get DAC interface\n"); - return -ENODEV; - } - - /* Register the DAC driver at "/dev/dac0" */ - - ret = dac_register("/dev/dac0", g_dac1); - if (ret < 0) - { - aerr("ERROR: dac_register() failed: %d\n", ret); - return ret; - } - -#endif - -#ifdef CONFIG_STM32_DAC3CH2 - g_dac5 = stm32_dacinitialize(5); - if (g_dac5 == NULL) - { - aerr("ERROR: Failed to get DAC interface\n"); - return -ENODEV; - } - - /* Register the DAC driver at "/dev/dac5" */ - - ret = dac_register("/dev/dac5", g_dac5); - if (ret < 0) - { - aerr("ERROR: dac_register() failed: %d\n", ret); - return ret; - } - -#endif - - UNUSED(ret); - return OK; -} - -#endif /* CONFIG_DAC */ diff --git a/boards/arm/stm32/nucleo-g431kb/src/stm32_pwm.c b/boards/arm/stm32/nucleo-g431kb/src/stm32_pwm.c deleted file mode 100644 index 01ae0c9276541..0000000000000 --- a/boards/arm/stm32/nucleo-g431kb/src/stm32_pwm.c +++ /dev/null @@ -1,86 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-g431kb/src/stm32_pwm.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32_pwm.h" -#include "nucleo-g431kb.h" - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_pwm_setup - * - * Description: - * Initialize PWM and register the PWM device. - * - ****************************************************************************/ - -int stm32_pwm_setup(void) -{ - static bool initialized = false; - struct pwm_lowerhalf_s *pwm; - int ret; - - /* Have we already initialized? */ - - if (!initialized) - { - /* Call stm32_pwminitialize() to get an instance of the PWM interface */ - - pwm = stm32_pwminitialize(NUCLEOG431KB_PWM_TIMER); - if (!pwm) - { - tmrerr("Failed to get the STM32 PWM lower half\n"); - return -ENODEV; - } - - /* Register the PWM driver at "/dev/pwm0" */ - - ret = pwm_register(NUCLEOG431KB_PWM_PATH, pwm); - if (ret < 0) - { - tmrerr("pwm_register failed: %d\n", ret); - return ret; - } - - /* Now we are initialized */ - - initialized = true; - } - - return OK; -} diff --git a/boards/arm/stm32/nucleo-g431kb/src/stm32_userleds.c b/boards/arm/stm32/nucleo-g431kb/src/stm32_userleds.c deleted file mode 100644 index 072ae0166ae0a..0000000000000 --- a/boards/arm/stm32/nucleo-g431kb/src/stm32_userleds.c +++ /dev/null @@ -1,77 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-g431kb/src/stm32_userleds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include - -#include "stm32.h" -#include "nucleo-g431kb.h" - -#if !defined(CONFIG_ARCH_LEDS) - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_userled_initialize - ****************************************************************************/ - -uint32_t board_userled_initialize(void) -{ - /* Configure LED GPIOs for output */ - - stm32_configgpio(GPIO_LED1); - return BOARD_NLEDS; -} - -/**************************************************************************** - * Name: board_userled - ****************************************************************************/ - -void board_userled(int led, bool ledon) -{ - if (led == BOARD_LED1) - { - stm32_gpiowrite(GPIO_LED1, ledon); - } -} - -/**************************************************************************** - * Name: board_userled_all - ****************************************************************************/ - -void board_userled_all(uint32_t ledset) -{ - stm32_gpiowrite(GPIO_LED1, (ledset & BOARD_LED1_BIT) != 0); -} - -#endif /* !CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/nucleo-g431rb/CMakeLists.txt b/boards/arm/stm32/nucleo-g431rb/CMakeLists.txt deleted file mode 100644 index c8eda596831a3..0000000000000 --- a/boards/arm/stm32/nucleo-g431rb/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/nucleo-g431rb/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32/nucleo-g431rb/configs/adc/defconfig b/boards/arm/stm32/nucleo-g431rb/configs/adc/defconfig deleted file mode 100644 index 143878d3afd82..0000000000000 --- a/boards/arm/stm32/nucleo-g431rb/configs/adc/defconfig +++ /dev/null @@ -1,91 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_SYSTEM_DD is not set -CONFIG_ADC=y -CONFIG_ANALOG=y -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="nucleo-g431rb" -CONFIG_ARCH_BOARD_NUCLEO_G431RB=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32G431R=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_DISABLE_ENVIRON=y -CONFIG_DISABLE_MQUEUE=y -CONFIG_DISABLE_POSIX_TIMERS=y -CONFIG_DISABLE_PTHREAD=y -CONFIG_FDCLONE_STDIO=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INIT_STACKSIZE=1024 -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_NAME_MAX=16 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_DISABLE_BASENAME=y -CONFIG_NSH_DISABLE_CAT=y -CONFIG_NSH_DISABLE_CD=y -CONFIG_NSH_DISABLE_CMP=y -CONFIG_NSH_DISABLE_CP=y -CONFIG_NSH_DISABLE_DF=y -CONFIG_NSH_DISABLE_DIRNAME=y -CONFIG_NSH_DISABLE_EXEC=y -CONFIG_NSH_DISABLE_EXIT=y -CONFIG_NSH_DISABLE_GET=y -CONFIG_NSH_DISABLE_HEXDUMP=y -CONFIG_NSH_DISABLE_KILL=y -CONFIG_NSH_DISABLE_LOSETUP=y -CONFIG_NSH_DISABLE_LS=y -CONFIG_NSH_DISABLE_MKDIR=y -CONFIG_NSH_DISABLE_MKRD=y -CONFIG_NSH_DISABLE_MOUNT=y -CONFIG_NSH_DISABLE_MV=y -CONFIG_NSH_DISABLE_PUT=y -CONFIG_NSH_DISABLE_PWD=y -CONFIG_NSH_DISABLE_RM=y -CONFIG_NSH_DISABLE_RMDIR=y -CONFIG_NSH_DISABLE_SET=y -CONFIG_NSH_DISABLE_SLEEP=y -CONFIG_NSH_DISABLE_SOURCE=y -CONFIG_NSH_DISABLE_TEST=y -CONFIG_NSH_DISABLE_TIME=y -CONFIG_NSH_DISABLE_UMOUNT=y -CONFIG_NSH_DISABLE_UNAME=y -CONFIG_NSH_DISABLE_UNSET=y -CONFIG_NSH_DISABLE_USLEEP=y -CONFIG_NSH_DISABLE_WGET=y -CONFIG_NSH_DISABLE_XD=y -CONFIG_NSH_FILEIOSIZE=256 -CONFIG_NSH_READLINE=y -CONFIG_POSIX_SPAWN_DEFAULT_STACKSIZE=512 -CONFIG_PTHREAD_STACK_DEFAULT=1024 -CONFIG_PTHREAD_STACK_MIN=1024 -CONFIG_RAM_SIZE=22528 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=6 -CONFIG_START_MONTH=12 -CONFIG_START_YEAR=2011 -CONFIG_STM32_ADC1=y -CONFIG_STM32_ADC1_DMA=y -CONFIG_STM32_ADC2=y -CONFIG_STM32_DMA1=y -CONFIG_STM32_DMAMUX1=y -CONFIG_STM32_FORCEPOWER=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_TIM1=y -CONFIG_STM32_TIM1_ADC=y -CONFIG_STM32_USART2=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/nucleo-g431rb/configs/can/defconfig b/boards/arm/stm32/nucleo-g431rb/configs/can/defconfig deleted file mode 100644 index 4796db68b7df9..0000000000000 --- a/boards/arm/stm32/nucleo-g431rb/configs/can/defconfig +++ /dev/null @@ -1,54 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -# CONFIG_NSH_DISABLE_IFCONFIG is not set -# CONFIG_NSH_DISABLE_PS is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="nucleo-g431rb" -CONFIG_ARCH_BOARD_NUCLEO_G431RB=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32G431R=y -CONFIG_ARCH_INTERRUPTSTACK=2048 -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=8499 -CONFIG_BOARD_NUCLEO_G431RB_USE_HSE=y -CONFIG_BUILTIN=y -CONFIG_CAN_ERRORS=y -CONFIG_CAN_EXTID=y -CONFIG_DEBUG_FULLOPT=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_EXAMPLES_CAN=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=22528 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=14 -CONFIG_START_MONTH=10 -CONFIG_START_YEAR=2014 -CONFIG_STDIO_BUFFER_SIZE=512 -CONFIG_STM32_FDCAN1=y -CONFIG_STM32_FDCAN1_BITRATE=250000 -CONFIG_STM32_FDCAN1_NTSEG1=71 -CONFIG_STM32_FDCAN1_NTSEG2=24 -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_USART2=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/nucleo-g431rb/configs/cansock/defconfig b/boards/arm/stm32/nucleo-g431rb/configs/cansock/defconfig deleted file mode 100644 index dbca1ec3f65f3..0000000000000 --- a/boards/arm/stm32/nucleo-g431rb/configs/cansock/defconfig +++ /dev/null @@ -1,59 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_NET_ETHERNET is not set -# CONFIG_NET_IPv4 is not set -CONFIG_ALLOW_BSD_COMPONENTS=y -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="nucleo-g431rb" -CONFIG_ARCH_BOARD_NUCLEO_G431RB=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32G431R=y -CONFIG_ARCH_INTERRUPTSTACK=1024 -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=8499 -CONFIG_BOARD_NUCLEO_G431RB_USE_HSE=y -CONFIG_BUILTIN=y -CONFIG_CANUTILS_CANDUMP=y -CONFIG_CANUTILS_CANSEND=y -CONFIG_CANUTILS_LIBCANUTILS=y -CONFIG_FS_PROCFS=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_IOB_BUFSIZE=128 -CONFIG_IOB_NBUFFERS=10 -CONFIG_LINE_MAX=64 -CONFIG_NET=y -CONFIG_NETDEV_IFINDEX=y -CONFIG_NETDEV_LATEINIT=y -CONFIG_NET_CAN=y -CONFIG_NET_SOCKOPTS=y -CONFIG_NET_STATISTICS=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_RAM_SIZE=22528 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_LPWORK=y -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=14 -CONFIG_START_MONTH=10 -CONFIG_START_YEAR=2014 -CONFIG_STM32_FDCAN1=y -CONFIG_STM32_FDCAN1_BITRATE=250000 -CONFIG_STM32_FDCAN1_NTSEG1=71 -CONFIG_STM32_FDCAN1_NTSEG2=24 -CONFIG_STM32_FDCAN_SOCKET=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_USART2=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/nucleo-g431rb/configs/cordic/defconfig b/boards/arm/stm32/nucleo-g431rb/configs/cordic/defconfig deleted file mode 100644 index 105f0e801d73e..0000000000000 --- a/boards/arm/stm32/nucleo-g431rb/configs/cordic/defconfig +++ /dev/null @@ -1,51 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -# CONFIG_NSH_DISABLE_IFCONFIG is not set -# CONFIG_NSH_DISABLE_PS is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="nucleo-g431rb" -CONFIG_ARCH_BOARD_NUCLEO_G431RB=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32G431R=y -CONFIG_ARCH_INTERRUPTSTACK=2048 -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=8499 -CONFIG_BUILTIN=y -CONFIG_DEBUG_FULLOPT=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_EXAMPLES_CORDIC=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LIBC_FLOATINGPOINT=y -CONFIG_LINE_MAX=64 -CONFIG_MATH_CORDIC=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=22528 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=14 -CONFIG_START_MONTH=10 -CONFIG_START_YEAR=2014 -CONFIG_STM32_CORDIC=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_USART2=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/nucleo-g431rb/configs/ihm16m1_b16/defconfig b/boards/arm/stm32/nucleo-g431rb/configs/ihm16m1_b16/defconfig deleted file mode 100644 index 198ec5e96451f..0000000000000 --- a/boards/arm/stm32/nucleo-g431rb/configs/ihm16m1_b16/defconfig +++ /dev/null @@ -1,87 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_DISABLE_MQUEUE is not set -# CONFIG_DISABLE_PTHREAD is not set -CONFIG_ADC=y -CONFIG_ADC_FIFOSIZE=3 -CONFIG_ANALOG=y -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="nucleo-g431rb" -CONFIG_ARCH_BOARD_COMMON=y -CONFIG_ARCH_BOARD_NUCLEO_G431RB=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32G431R=y -CONFIG_ARCH_INTERRUPTSTACK=1024 -CONFIG_ARCH_IRQBUTTONS=y -CONFIG_ARMV7M_LIBM=y -CONFIG_BOARDCTL=y -CONFIG_BOARD_LOOPSPERMSEC=8499 -CONFIG_BOARD_STM32_IHM16M1=y -CONFIG_BOARD_STM32_IHM16M1_POT=y -CONFIG_BOARD_STM32_IHM16M1_VBUS=y -CONFIG_BUILTIN=y -CONFIG_DEBUG_FULLOPT=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_DEFAULT_SMALL=y -CONFIG_DEFAULT_TASK_STACKSIZE=1024 -CONFIG_EXAMPLES_FOC=y -CONFIG_EXAMPLES_FOC_ADC_MAX=4095 -CONFIG_EXAMPLES_FOC_ADC_VREF=3300 -CONFIG_EXAMPLES_FOC_CONTROL_STACKSIZE=2048 -CONFIG_EXAMPLES_FOC_FIXED16_INST=1 -CONFIG_EXAMPLES_FOC_HAVE_BUTTON=y -CONFIG_EXAMPLES_FOC_NOTIFIER_FREQ=10000 -CONFIG_EXAMPLES_FOC_PWM_FREQ=20000 -CONFIG_EXAMPLES_FOC_RAMP_ACC=1000000 -CONFIG_EXAMPLES_FOC_RAMP_DEC=1000000 -CONFIG_EXAMPLES_FOC_RAMP_THR=10000 -CONFIG_EXAMPLES_FOC_SETPOINT_ADC=y -CONFIG_EXAMPLES_FOC_VBUS_ADC=y -CONFIG_EXAMPLES_FOC_VBUS_SCALE=16000 -CONFIG_INDUSTRY_FOC=y -CONFIG_INDUSTRY_FOC_FIXED16=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INPUT=y -CONFIG_INPUT_BUTTONS=y -CONFIG_INPUT_BUTTONS_LOWER=y -CONFIG_INTELHEX_BINARY=y -CONFIG_LIBM=y -CONFIG_MOTOR=y -CONFIG_MOTOR_FOC=y -CONFIG_MOTOR_FOC_TRACE=y -CONFIG_MQ_MAXMSGSIZE=5 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_RAM_SIZE=22528 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=14 -CONFIG_START_MONTH=10 -CONFIG_START_YEAR=2014 -CONFIG_STM32_ADC1_ANIOC_TRIGGER=1 -CONFIG_STM32_ADC1_DMA=y -CONFIG_STM32_ADC1_DMA_CFG=1 -CONFIG_STM32_ADC1_INJECTED_CHAN=3 -CONFIG_STM32_DMA1=y -CONFIG_STM32_DMA2=y -CONFIG_STM32_DMAMUX1=y -CONFIG_STM32_FOC=y -CONFIG_STM32_FOC_FOC0=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_TIM1_CH1MODE=0 -CONFIG_STM32_TIM1_CH2MODE=0 -CONFIG_STM32_TIM1_CH3MODE=0 -CONFIG_STM32_TIM1_MODE=2 -CONFIG_STM32_USART2=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART2_SERIAL_CONSOLE=y -CONFIG_USART2_TXDMA=y diff --git a/boards/arm/stm32/nucleo-g431rb/configs/ihm16m1_f32/defconfig b/boards/arm/stm32/nucleo-g431rb/configs/ihm16m1_f32/defconfig deleted file mode 100644 index 54b46c61d05c2..0000000000000 --- a/boards/arm/stm32/nucleo-g431rb/configs/ihm16m1_f32/defconfig +++ /dev/null @@ -1,87 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_DISABLE_MQUEUE is not set -# CONFIG_DISABLE_PTHREAD is not set -CONFIG_ADC=y -CONFIG_ADC_FIFOSIZE=3 -CONFIG_ANALOG=y -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="nucleo-g431rb" -CONFIG_ARCH_BOARD_COMMON=y -CONFIG_ARCH_BOARD_NUCLEO_G431RB=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32G431R=y -CONFIG_ARCH_INTERRUPTSTACK=1024 -CONFIG_ARCH_IRQBUTTONS=y -CONFIG_ARMV7M_LIBM=y -CONFIG_BOARDCTL=y -CONFIG_BOARD_LOOPSPERMSEC=8499 -CONFIG_BOARD_STM32_IHM16M1=y -CONFIG_BOARD_STM32_IHM16M1_POT=y -CONFIG_BOARD_STM32_IHM16M1_VBUS=y -CONFIG_BUILTIN=y -CONFIG_DEBUG_FULLOPT=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_DEFAULT_SMALL=y -CONFIG_DEFAULT_TASK_STACKSIZE=1024 -CONFIG_EXAMPLES_FOC=y -CONFIG_EXAMPLES_FOC_ADC_MAX=4095 -CONFIG_EXAMPLES_FOC_ADC_VREF=3300 -CONFIG_EXAMPLES_FOC_CONTROL_STACKSIZE=2048 -CONFIG_EXAMPLES_FOC_FLOAT_INST=1 -CONFIG_EXAMPLES_FOC_HAVE_BUTTON=y -CONFIG_EXAMPLES_FOC_NOTIFIER_FREQ=10000 -CONFIG_EXAMPLES_FOC_PWM_FREQ=20000 -CONFIG_EXAMPLES_FOC_RAMP_ACC=1000000 -CONFIG_EXAMPLES_FOC_RAMP_DEC=1000000 -CONFIG_EXAMPLES_FOC_RAMP_THR=10000 -CONFIG_EXAMPLES_FOC_SETPOINT_ADC=y -CONFIG_EXAMPLES_FOC_VBUS_ADC=y -CONFIG_EXAMPLES_FOC_VBUS_SCALE=16000 -CONFIG_INDUSTRY_FOC=y -CONFIG_INDUSTRY_FOC_FLOAT=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INPUT=y -CONFIG_INPUT_BUTTONS=y -CONFIG_INPUT_BUTTONS_LOWER=y -CONFIG_INTELHEX_BINARY=y -CONFIG_LIBM=y -CONFIG_MOTOR=y -CONFIG_MOTOR_FOC=y -CONFIG_MOTOR_FOC_TRACE=y -CONFIG_MQ_MAXMSGSIZE=5 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_RAM_SIZE=22528 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=14 -CONFIG_START_MONTH=10 -CONFIG_START_YEAR=2014 -CONFIG_STM32_ADC1_ANIOC_TRIGGER=1 -CONFIG_STM32_ADC1_DMA=y -CONFIG_STM32_ADC1_DMA_CFG=1 -CONFIG_STM32_ADC1_INJECTED_CHAN=3 -CONFIG_STM32_DMA1=y -CONFIG_STM32_DMA2=y -CONFIG_STM32_DMAMUX1=y -CONFIG_STM32_FOC=y -CONFIG_STM32_FOC_FOC0=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_TIM1_CH1MODE=0 -CONFIG_STM32_TIM1_CH2MODE=0 -CONFIG_STM32_TIM1_CH3MODE=0 -CONFIG_STM32_TIM1_MODE=2 -CONFIG_STM32_USART2=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART2_SERIAL_CONSOLE=y -CONFIG_USART2_TXDMA=y diff --git a/boards/arm/stm32/nucleo-g431rb/configs/nsh/defconfig b/boards/arm/stm32/nucleo-g431rb/configs/nsh/defconfig deleted file mode 100644 index b28e171393d61..0000000000000 --- a/boards/arm/stm32/nucleo-g431rb/configs/nsh/defconfig +++ /dev/null @@ -1,48 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -# CONFIG_NSH_DISABLE_IFCONFIG is not set -# CONFIG_NSH_DISABLE_PS is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="nucleo-g431rb" -CONFIG_ARCH_BOARD_NUCLEO_G431RB=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32G431R=y -CONFIG_ARCH_INTERRUPTSTACK=2048 -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=8499 -CONFIG_BUILTIN=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_LTO_FULL=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=22528 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=14 -CONFIG_START_MONTH=10 -CONFIG_START_YEAR=2014 -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_USART2=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_TESTING_OSTEST=y -CONFIG_TESTING_OSTEST_STACKSIZE=1024 -CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/nucleo-g431rb/configs/pwm/defconfig b/boards/arm/stm32/nucleo-g431rb/configs/pwm/defconfig deleted file mode 100644 index 8f56b95cda311..0000000000000 --- a/boards/arm/stm32/nucleo-g431rb/configs/pwm/defconfig +++ /dev/null @@ -1,61 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="nucleo-g431rb" -CONFIG_ARCH_BOARD_NUCLEO_G431RB=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32G431R=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=5483 -CONFIG_BUILTIN=y -CONFIG_DEBUG_FULLOPT=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_DEFAULT_SMALL=y -CONFIG_EXAMPLES_PWM=y -CONFIG_FILE_STREAM=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=80 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=1024 -CONFIG_PWM=y -CONFIG_PWM_NCHANNELS=4 -CONFIG_RAM_SIZE=22528 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_HPWORKPRIORITY=192 -CONFIG_SCHED_WAITPID=y -CONFIG_SERIAL_TERMIOS=y -CONFIG_START_DAY=5 -CONFIG_START_MONTH=7 -CONFIG_START_YEAR=2011 -CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32_FORCEPOWER=y -CONFIG_STM32_JTAG_FULL_ENABLE=y -CONFIG_STM32_PWM_MULTICHAN=y -CONFIG_STM32_TIM1=y -CONFIG_STM32_TIM1_CH1NOUT=y -CONFIG_STM32_TIM1_CH1OUT=y -CONFIG_STM32_TIM1_CH2NOUT=y -CONFIG_STM32_TIM1_CH2OUT=y -CONFIG_STM32_TIM1_CH3NOUT=y -CONFIG_STM32_TIM1_CH3OUT=y -CONFIG_STM32_TIM1_CH4OUT=y -CONFIG_STM32_TIM1_CHANNEL1=y -CONFIG_STM32_TIM1_CHANNEL2=y -CONFIG_STM32_TIM1_CHANNEL3=y -CONFIG_STM32_TIM1_CHANNEL4=y -CONFIG_STM32_TIM1_PWM=y -CONFIG_STM32_USART2=y -CONFIG_SYMTAB_ORDEREDBYNAME=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/nucleo-g431rb/configs/qenco/defconfig b/boards/arm/stm32/nucleo-g431rb/configs/qenco/defconfig deleted file mode 100644 index a3b86c5b5b5be..0000000000000 --- a/boards/arm/stm32/nucleo-g431rb/configs/qenco/defconfig +++ /dev/null @@ -1,56 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -# CONFIG_NSH_DISABLE_IFCONFIG is not set -# CONFIG_NSH_DISABLE_PS is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="nucleo-g431rb" -CONFIG_ARCH_BOARD_COMMON=y -CONFIG_ARCH_BOARD_NUCLEO_G431RB=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32G431R=y -CONFIG_ARCH_INTERRUPTSTACK=2048 -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=8499 -CONFIG_BUILTIN=y -CONFIG_EXAMPLES_QENCODER=y -CONFIG_EXAMPLES_QENCODER_HAVE_MAXPOS=y -CONFIG_EXAMPLES_QENCODER_MAXPOS=8192 -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=22528 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_SENSORS=y -CONFIG_SENSORS_QENCODER=y -CONFIG_START_DAY=14 -CONFIG_START_MONTH=10 -CONFIG_START_YEAR=2014 -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_QENCODER_DISABLE_EXTEND16BTIMERS=y -CONFIG_STM32_QENCODER_SAMPLE_FDTS_2=y -CONFIG_STM32_TIM2=y -CONFIG_STM32_TIM2_QE=y -CONFIG_STM32_TIM2_QEPSC=0 -CONFIG_STM32_USART2=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/nucleo-g431rb/include/board.h b/boards/arm/stm32/nucleo-g431rb/include/board.h deleted file mode 100644 index d0276b130af4f..0000000000000 --- a/boards/arm/stm32/nucleo-g431rb/include/board.h +++ /dev/null @@ -1,399 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-g431rb/include/board.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __BOARDS_ARM_STM32_NUCLEO_G431RB_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32_NUCLEO_G431RB_INCLUDE_BOARD_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Clocking *****************************************************************/ - -#define STM32_BOARD_XTAL 24000000 /* 8MHz */ - -#define STM32_HSI_FREQUENCY 16000000ul /* 16MHz */ -#define STM32_LSI_FREQUENCY 32000 /* 32kHz */ -#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL -#undef STM32_LSE_FREQUENCY /* Not available on this board */ - -#ifdef CONFIG_BOARD_NUCLEO_G431RB_USE_HSI - -/* Main PLL Configuration. - * - * PLL source is HSI = 16MHz - * PLLN = 85, PLLM = 4, PLLP = 10, PLLQ = 2, PLLR = 2 - * - * f(VCO Clock) = f(PLL Clock Input) x (PLLN / PLLM) - * f(PLL_P) = f(VCO Clock) / PLLP - * f(PLL_Q) = f(VCO Clock) / PLLQ - * f(PLL_R) = f(VCO Clock) / PLLR - * - * Where: - * 8 <= PLLN <= 127 - * 1 <= PLLM <= 16 - * PLLP = 2 through 31 - * PLLQ = 2, 4, 6, or 8 - * PLLR = 2, 4, 6, or 8 - * - * Do not exceed 170MHz on f(PLL_P), f(PLL_Q), or f(PLL_R). - * 64MHz <= f(VCO Clock) <= 344MHz. - * - * Given the above: - * - * f(VCO Clock) = HSI x PLLN / PLLM - * = 16MHz x 85 / 4 - * = 340MHz - * - * PLLPCLK = f(VCO Clock) / PLLP - * = 340MHz / 10 - * = 34MHz - * (May be used for ADC) - * - * PLLQCLK = f(VCO Clock) / PLLQ - * = 340MHz / 2 - * = 170MHz - * (May be used for QUADSPI, FDCAN, SAI1, I2S3. If set to - * 48MHz, may be used for USB, RNG.) - * - * PLLRCLK = f(VCO Clock) / PLLR - * = 340MHz / 2 - * = 170MHz - * (May be used for SYSCLK and most peripherals.) - */ - -#define STM32_PLLCFGR_PLLSRC RCC_PLLCFGR_PLLSRC_HSI -#define STM32_PLLCFGR_PLLCFG (RCC_PLLCFGR_PLLPEN | \ - RCC_PLLCFGR_PLLQEN | \ - RCC_PLLCFGR_PLLREN) - -#define STM32_PLLCFGR_PLLN RCC_PLLCFGR_PLLN(85) -#define STM32_PLLCFGR_PLLM RCC_PLLCFGR_PLLM(4) -#define STM32_PLLCFGR_PLLP RCC_PLLCFGR_PLLPDIV(10) -#define STM32_PLLCFGR_PLLQ RCC_PLLCFGR_PLLQ_2 -#define STM32_PLLCFGR_PLLR RCC_PLLCFGR_PLLR_2 - -#define STM32_VCO_FREQUENCY ((STM32_HSI_FREQUENCY / 4) * 85) -#define STM32_PLLP_FREQUENCY (STM32_VCO_FREQUENCY / 10) -#define STM32_PLLQ_FREQUENCY (STM32_VCO_FREQUENCY / 2) -#define STM32_PLLR_FREQUENCY (STM32_VCO_FREQUENCY / 2) - -/* Use the PLL and set the SYSCLK source to be PLLR (170MHz) */ - -#define STM32_SYSCLK_SW RCC_CFGR_SW_PLL -#define STM32_SYSCLK_SWS RCC_CFGR_SWS_PLL -#define STM32_SYSCLK_FREQUENCY STM32_PLLR_FREQUENCY - -/* AHB clock (HCLK) is SYSCLK (170MHz) */ - -#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK -#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY - -/* APB1 clock (PCLK1) is HCLK (170MHz) */ - -#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK -#define STM32_PCLK1_FREQUENCY STM32_HCLK_FREQUENCY - -/* APB2 clock (PCLK2) is HCLK (170MHz) */ - -#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK -#define STM32_PCLK2_FREQUENCY STM32_HCLK_FREQUENCY - -#endif /* CONFIG_BOARD_NUCLEO_G431RB_USE_HSI */ - -#ifdef CONFIG_BOARD_NUCLEO_G431RB_USE_HSE - -/* Main PLL Configuration. - * - * PLL source is HSE = 24MHz - * PLLN = 86, PLLM = 6, PLLP = 10, PLLQ = 2, PLLR = 2 - * - * f(VCO Clock) = f(PLL Clock Input) x (PLLN / PLLM) - * f(PLL_P) = f(VCO Clock) / PLLP - * f(PLL_Q) = f(VCO Clock) / PLLQ - * f(PLL_R) = f(VCO Clock) / PLLR - * - * Where: - * 8 <= PLLN <= 127 - * 1 <= PLLM <= 16 - * PLLP = 2 through 31 - * PLLQ = 2, 4, 6, or 8 - * PLLR = 2, 4, 6, or 8 - * - * Do not exceed 170MHz on f(PLL_P), f(PLL_Q), or f(PLL_R). - * 64MHz <= f(VCO Clock) <= 344MHz. - * - * Given the above: - * - * f(VCO Clock) = HSE x PLLN / PLLM - * = 24MHz x 86 / 6 - * = 340MHz - * - * PLLPCLK = f(VCO Clock) / PLLP - * = 340MHz / 10 - * = 34MHz - * (May be used for ADC) - * - * PLLQCLK = f(VCO Clock) / PLLQ - * = 340MHz / 2 - * = 170MHz - * (May be used for QUADSPI, FDCAN, SAI1, I2S3. If set to - * 48MHz, may be used for USB, RNG.) - * - * PLLRCLK = f(VCO Clock) / PLLR - * = 340MHz / 2 - * = 170MHz - * (May be used for SYSCLK and most peripherals.) - */ - -#define STM32_PLLCFGR_PLLSRC RCC_PLLCFGR_PLLSRC_HSE -#define STM32_PLLCFGR_PLLCFG (RCC_PLLCFGR_PLLPEN | \ - RCC_PLLCFGR_PLLQEN | \ - RCC_PLLCFGR_PLLREN) - -#define STM32_PLLCFGR_PLLN RCC_PLLCFGR_PLLN(86) -#define STM32_PLLCFGR_PLLM RCC_PLLCFGR_PLLM(6) -#define STM32_PLLCFGR_PLLP RCC_PLLCFGR_PLLPDIV(10) -#define STM32_PLLCFGR_PLLQ RCC_PLLCFGR_PLLQ_2 -#define STM32_PLLCFGR_PLLR RCC_PLLCFGR_PLLR_2 - -#define STM32_VCO_FREQUENCY ((STM32_HSI_FREQUENCY / 4) * 85) -#define STM32_PLLP_FREQUENCY (STM32_VCO_FREQUENCY / 10) -#define STM32_PLLQ_FREQUENCY (STM32_VCO_FREQUENCY / 2) -#define STM32_PLLR_FREQUENCY (STM32_VCO_FREQUENCY / 2) - -/* Use the PLL and set the SYSCLK source to be PLLR (170MHz) */ - -#define STM32_SYSCLK_SW RCC_CFGR_SW_PLL -#define STM32_SYSCLK_SWS RCC_CFGR_SWS_PLL -#define STM32_SYSCLK_FREQUENCY STM32_PLLR_FREQUENCY - -/* AHB clock (HCLK) is SYSCLK (170MHz) */ - -#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK -#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY - -/* APB1 clock (PCLK1) is HCLK (170MHz) */ - -#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK -#define STM32_PCLK1_FREQUENCY STM32_HCLK_FREQUENCY - -/* APB2 clock (PCLK2) is HCLK (170MHz) */ - -#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK -#define STM32_PCLK2_FREQUENCY STM32_HCLK_FREQUENCY - -#endif /* CONFIG_BOARD_NUCLEO_G431RB_USE_HSE */ - -/* APB2 timers 1, 8, 20 and 15-17 will receive PCLK2. */ - -/* Timers driven from APB2 will be PCLK2 */ - -#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB1_TIM15_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB1_TIM16_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB1_TIM17_CLKIN (STM32_PCLK2_FREQUENCY) - -/* APB1 timers 2-7 will be twice PCLK1 */ - -#define STM32_APB1_TIM2_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM4_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (STM32_PCLK1_FREQUENCY) - -/* USB divider -- Divide PLL clock by 1.5 */ - -#define STM32_CFGR_USBPRE 0 - -/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx - * otherwise frequency is 2xAPBx. - */ - -#define BOARD_TIM1_FREQUENCY (STM32_PCLK2_FREQUENCY) -#define BOARD_TIM2_FREQUENCY (STM32_PCLK1_FREQUENCY) -#define BOARD_TIM3_FREQUENCY (STM32_PCLK1_FREQUENCY) -#define BOARD_TIM4_FREQUENCY (STM32_PCLK1_FREQUENCY) -#define BOARD_TIM5_FREQUENCY (STM32_PCLK1_FREQUENCY) -#define BOARD_TIM6_FREQUENCY (STM32_PCLK1_FREQUENCY) -#define BOARD_TIM7_FREQUENCY (STM32_PCLK1_FREQUENCY) -#define BOARD_TIM8_FREQUENCY (STM32_PCLK2_FREQUENCY) -#define BOARD_TIM15_FREQUENCY (STM32_PCLK2_FREQUENCY) -#define BOARD_TIM16_FREQUENCY (STM32_PCLK2_FREQUENCY) -#define BOARD_TIM17_FREQUENCY (STM32_PCLK2_FREQUENCY) -#define BOARD_TIM20_FREQUENCY (STM32_PCLK2_FREQUENCY) - -#ifdef CONFIG_STM32_FDCAN -# ifdef CONFIG_BOARD_NUCLEO_G431RB_USE_HSE -# define STM32_CCIPR_FDCANSRC (RCC_CCIPR_FDCANSEL_HSE) -# define STM32_FDCAN_FREQUENCY (STM32_HSE_FREQUENCY) -# else -# error For now FDCAN supported only if HSE enabled -# endif -#endif - -/* LED definitions **********************************************************/ - -/* The NUCLEO-G431RB has four user LEDs. - * - * If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs in - * any way. The following definitions are used to access individual LEDs. - */ - -/* LED index values for use with board_userled() */ - -#define BOARD_LED1 0 /* User LD2 */ -#define BOARD_NLEDS 1 - -/* LED bits for use with board_userled_all() */ - -#define BOARD_LED1_BIT (1 << BOARD_LED1) - -/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the LED on board - * the Nucleo G431RB. The following definitions describe how NuttX controls - * the LED: - * - * SYMBOL Meaning LED1 state - * ------------------ ----------------------- ---------- - * LED_STARTED NuttX has been started OFF - * LED_HEAPALLOCATE Heap has been allocated OFF - * LED_IRQSENABLED Interrupts enabled OFF - * LED_STACKCREATED Idle stack created ON - * LED_INIRQ In an interrupt No change - * LED_SIGNAL In a signal handler No change - * LED_ASSERTION An assertion failed No change - * LED_PANIC The system has crashed Blinking - * LED_IDLE STM32 is in sleep mode Not used - */ - -#define LED_STARTED 0 -#define LED_HEAPALLOCATE 0 -#define LED_IRQSENABLED 0 -#define LED_STACKCREATED 1 -#define LED_INIRQ 2 -#define LED_SIGNAL 2 -#define LED_ASSERTION 2 -#define LED_PANIC 1 - -/* Button definitions *******************************************************/ - -/* The Nucleo G431RB supports two buttons; only one button is controllable - * by software: - * - * B1 USER: user button connected to the I/O PC13 of the STM32G431RB. - * B2 RESET: push button connected to NRST is used to RESET the - * STM32G431RB. - */ - -#define BUTTON_USER 0 -#define NUM_BUTTONS 1 - -#define BUTTON_USER_BIT (1 << BUTTON_USER) - -/* Alternate function pin selections ****************************************/ - -/* TIM2 input ***************************************************************/ - -#define GPIO_TIM2_CH1IN (GPIO_TIM2_CH1IN_3 | GPIO_PULLUP | GPIO_SPEED_50MHz) /* PA15 */ -#define GPIO_TIM2_CH2IN (GPIO_TIM2_CH2IN_2 | GPIO_PULLUP | GPIO_SPEED_50MHz) /* PB3 */ - -/* USART2 (STLINK Virtual COM Port) */ - -#define GPIO_USART2_TX GPIO_USART2_TX_1 /* PA2 */ -#define GPIO_USART2_RX GPIO_USART2_RX_1 /* PA3 */ - -/* PWM configuration ********************************************************/ - -/* TIM1 PWM */ - -#define GPIO_TIM1_CH1OUT (GPIO_TIM1_CH1OUT_1|GPIO_SPEED_50MHz) /* PA8 */ -#define GPIO_TIM1_CH1NOUT (GPIO_TIM1_CH1NOUT_2|GPIO_SPEED_50MHz) /* PA11 */ -#define GPIO_TIM1_CH2OUT (GPIO_TIM1_CH2OUT_1|GPIO_SPEED_50MHz) /* PA9 */ -#define GPIO_TIM1_CH2NOUT (GPIO_TIM1_CH2NOUT_1|GPIO_SPEED_50MHz) /* PA12 */ -#define GPIO_TIM1_CH3OUT (GPIO_TIM1_CH3OUT_1|GPIO_SPEED_50MHz) /* PA10 */ -#define GPIO_TIM1_CH3NOUT (GPIO_TIM1_CH3NOUT_1|GPIO_SPEED_50MHz) /* PB1 */ -#define GPIO_TIM1_CH4OUT (GPIO_TIM1_CH4OUT_2|GPIO_SPEED_50MHz) /* PC3 */ - -/* CAN configuration ********************************************************/ - -#define GPIO_FDCAN1_RX (GPIO_FDCAN1_RX_2|GPIO_SPEED_50MHz) /* PB8 */ -#define GPIO_FDCAN1_TX (GPIO_FDCAN1_TX_2|GPIO_SPEED_50MHz) /* PB9 */ - -/* DMA channels *************************************************************/ - -/* ADC */ - -#define ADC1_DMA_CHAN DMAMAP_DMA12_ADC1_0 /* DMA1 */ - -/* USART2 */ - -#define DMACHAN_USART2_TX DMAMAP_DMA12_USART2TX_0 /* DMA1 */ -#define DMACHAN_USART2_RX DMAMAP_DMA12_USART2RX_0 /* DMA1 */ - -#ifdef CONFIG_BOARD_STM32_IHM16M1 - -/* Configuration specific for the X-NUCLEO-IHM16M1 expansion board with - * the STSPIN830 driver. - */ - -/* TIM1 configuration *******************************************************/ - -# define GPIO_TIM1_CH1OUT (GPIO_TIM1_CH1OUT_1|GPIO_SPEED_50MHz) /* TIM1 CH1 - PA8 - U high */ -# define GPIO_TIM1_CH2OUT (GPIO_TIM1_CH2OUT_1|GPIO_SPEED_50MHz) /* TIM1 CH2 - PA9 - V high */ -# define GPIO_TIM1_CH3OUT (GPIO_TIM1_CH3OUT_1|GPIO_SPEED_50MHz) /* TIM1 CH3 - PA10 - W high */ -# define GPIO_TIM1_CH4OUT 0 /* not used as output */ - -/* UVW ENABLE */ - -# define GPIO_FOC_EN_U (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz| \ - GPIO_OUTPUT_CLEAR|GPIO_PORTB|GPIO_PIN13) -# define GPIO_FOC_EN_V (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz| \ - GPIO_OUTPUT_CLEAR|GPIO_PORTB|GPIO_PIN14) -# define GPIO_FOC_EN_W (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz| \ - GPIO_OUTPUT_CLEAR|GPIO_PORTB|GPIO_PIN15) - -/* EN_FAULT */ - -# define GPIO_FOC_ENFAULT (GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz| \ - GPIO_OUTPUT_CLEAR|GPIO_PORTB|GPIO_PIN12) - -/* Debug pins */ - -# define GPIO_FOC_DEBUG0 (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz| \ - GPIO_OUTPUT_CLEAR|GPIO_PORTB|GPIO_PIN8) -# define GPIO_FOC_DEBUG1 (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz| \ - GPIO_OUTPUT_CLEAR|GPIO_PORTB|GPIO_PIN9) -# define GPIO_FOC_DEBUG2 (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz| \ - GPIO_OUTPUT_CLEAR|GPIO_PORTC|GPIO_PIN6) -# define GPIO_FOC_DEBUG3 (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz| \ - GPIO_OUTPUT_CLEAR|GPIO_PORTA|GPIO_PIN12) - -#endif /* CONFIG_BOARD_STM32_IHM16M1 */ - -#endif /* __BOARDS_ARM_STM32_NUCLEO_G431RB_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32/nucleo-g431rb/scripts/Make.defs b/boards/arm/stm32/nucleo-g431rb/scripts/Make.defs deleted file mode 100644 index 43067ac1b191b..0000000000000 --- a/boards/arm/stm32/nucleo-g431rb/scripts/Make.defs +++ /dev/null @@ -1,51 +0,0 @@ -############################################################################ -# boards/arm/stm32/nucleo-g431rb/scripts/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/.config -include $(TOPDIR)/tools/Config.mk -include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs - -ifeq ($(CONFIG_STM32_DFU),y) - LDSCRIPT = ld.script.dfu -else - LDSCRIPT = ld.script -endif - -ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) - -ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 - -CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) -CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) -CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -AFLAGS := $(CFLAGS) -D__ASSEMBLY__ - -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections -LDNXFLATFLAGS = -e main -s 2048 - -# Embed absolute path to source file in debug information so that Eclipse -# source level debugging won't get confused. See: -# https://stackoverflow.com/questions/1275476/gcc-gdb-how-to-embed-absolute-path-to-source-file-in-debug-information -CFLAGS += -fdebug-prefix-map=..=$(readlink -f ..) diff --git a/boards/arm/stm32/nucleo-g431rb/scripts/ld.script b/boards/arm/stm32/nucleo-g431rb/scripts/ld.script deleted file mode 100644 index 75cdcb94d4751..0000000000000 --- a/boards/arm/stm32/nucleo-g431rb/scripts/ld.script +++ /dev/null @@ -1,139 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-g431rb/scripts/ld.script - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* The STM32G431RB has 128 KiB of FLASH beginning at address 0x0800:0000. - * - * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 - * where the code expects to begin execution by jumping to the entry point in - * the 0x0800:0000 address range. - * - * The STM32G431RB has a total of 32 KiB of SRAM in three separate areas: - * - * 1) 16 KiB SRAM1 mapped at 0x2000:0000 thru 0x2000:3fff. - * 2) 6 KiB SRAM2 mapped at 0x2000:4000 thru 0x2000:57ff. - * - * CCM SRAM (Routine Booster): - * - * 3) 10 KiB CCM SRAM mapped at 0x1000:0000 thru 0x1000:27ff - * but also aliased at at 0x2000:5800 thru 0x2000:7fff to be contiguous - * with the SRAM1 and SRAM2. - * - * Because SRAM1 and SRAM2 are contiguous, they are treated as one region - * by this logic. - * - * CCM SRAM is also contiguous to SRAM1 and SRAM2, however it is excluded - * from this linker script, to keep it reserved for special uses in code. - * REVISIT: Is this the correct way to handle CCM SRAM? - */ - -MEMORY -{ - flash (rx) : ORIGIN = 0x08000000, LENGTH = 128K - sram (rwx) : ORIGIN = 0x20000000, LENGTH = 22K -} - -OUTPUT_ARCH(arm) -EXTERN(_vectors) -ENTRY(_stext) - -SECTIONS -{ - .text : { - _stext = ABSOLUTE(.); - *(.vectors) - *(.text .text.*) - *(.fixup) - *(.gnu.warning) - *(.rodata .rodata.*) - *(.gnu.linkonce.t.*) - *(.glue_7) - *(.glue_7t) - *(.got) - *(.gcc_except_table) - *(.gnu.linkonce.r.*) - _etext = ABSOLUTE(.); - } > flash - - .init_section : ALIGN(4) { - _sinit = ABSOLUTE(.); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) - KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) - _einit = ABSOLUTE(.); - } > flash - - .ARM.extab : ALIGN(4) { - *(.ARM.extab*) - } > flash - - .ARM.exidx : ALIGN(4) { - __exidx_start = ABSOLUTE(.); - *(.ARM.exidx*) - __exidx_end = ABSOLUTE(.); - } > flash - - .tdata : { - _stdata = ABSOLUTE(.); - *(.tdata .tdata.* .gnu.linkonce.td.*); - _etdata = ABSOLUTE(.); - } > flash - - .tbss : { - _stbss = ABSOLUTE(.); - *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); - _etbss = ABSOLUTE(.); - } > flash - - _eronly = ABSOLUTE(.); - - .data : ALIGN(4) { - _sdata = ABSOLUTE(.); - *(.data .data.*) - *(.gnu.linkonce.d.*) - CONSTRUCTORS - . = ALIGN(4); - _edata = ABSOLUTE(.); - } > sram AT > flash - - .bss : ALIGN(4) { - _sbss = ABSOLUTE(.); - *(.bss .bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - . = ALIGN(4); - _ebss = ABSOLUTE(.); - } > sram - - /* Stabs debugging sections. */ - - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_info 0 : { *(.debug_info) } - .debug_line 0 : { *(.debug_line) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_aranges 0 : { *(.debug_aranges) } -} diff --git a/boards/arm/stm32/nucleo-g431rb/src/CMakeLists.txt b/boards/arm/stm32/nucleo-g431rb/src/CMakeLists.txt deleted file mode 100644 index f25dfbffa4954..0000000000000 --- a/boards/arm/stm32/nucleo-g431rb/src/CMakeLists.txt +++ /dev/null @@ -1,64 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/nucleo-g431rb/src/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -set(SRCS stm32_boot.c stm32_bringup.c) - -if(CONFIG_ARCH_LEDS) - list(APPEND SRCS stm32_autoleds.c) -else() - list(APPEND SRCS stm32_userleds.c) -endif() - -if(CONFIG_ARCH_BUTTONS) - list(APPEND SRCS stm32_buttons.c) -endif() - -if(NOT CONFIG_STM32_FOC) - if(CONFIG_PWM) - list(APPEND SRCS stm32_pwm.c) - endif() - - if(CONFIG_ADC) - list(APPEND SRCS stm32_adc.c) - endif() -endif() - -if(CONFIG_BOARD_STM32_IHM16M1) - list(APPEND SRCS stm32_foc_ihm16m1.c) -endif() - -if(CONFIG_MATH_CORDIC) - list(APPEND SRCS stm32_cordic.c) -endif() - -if(CONFIG_STM32_FDCAN) - if(CONFIG_STM32_FDCAN_CHARDRIVER) - list(APPEND SRCS stm32_can.c) - endif() - if(CONFIG_STM32_FDCAN_SOCKET) - list(APPEND SRCS stm32_cansock.c) - endif() -endif() - -target_sources(board PRIVATE ${SRCS}) - -set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/ld.script") diff --git a/boards/arm/stm32/nucleo-g431rb/src/Make.defs b/boards/arm/stm32/nucleo-g431rb/src/Make.defs deleted file mode 100644 index 14403c2270048..0000000000000 --- a/boards/arm/stm32/nucleo-g431rb/src/Make.defs +++ /dev/null @@ -1,67 +0,0 @@ -############################################################################ -# boards/arm/stm32/nucleo-g431rb/src/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/Make.defs - -ASRCS = -CSRCS = stm32_boot.c stm32_bringup.c - -ifeq ($(CONFIG_ARCH_LEDS),y) -CSRCS += stm32_autoleds.c -else -CSRCS += stm32_userleds.c -endif - -ifeq ($(CONFIG_ARCH_BUTTONS),y) -CSRCS += stm32_buttons.c -endif - -ifneq ($(CONFIG_STM32_FOC),y) -ifeq ($(CONFIG_PWM),y) -CSRCS += stm32_pwm.c -endif - -ifeq ($(CONFIG_ADC),y) -CSRCS += stm32_adc.c -endif -endif - -ifeq ($(CONFIG_BOARD_STM32_IHM16M1),y) -CSRCS += stm32_foc_ihm16m1.c -endif - -ifeq ($(CONFIG_MATH_CORDIC),y) -CSRCS += stm32_cordic.c -endif - -ifeq ($(CONFIG_STM32_FDCAN),y) -ifeq ($(CONFIG_STM32_FDCAN_CHARDRIVER),y) -CSRCS += stm32_can.c -endif -ifeq ($(CONFIG_STM32_FDCAN_SOCKET),y) -CSRCS += stm32_cansock.c -endif -endif - -DEPPATH += --dep-path board -VPATH += :board -CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/nucleo-g431rb/src/stm32_adc.c b/boards/arm/stm32/nucleo-g431rb/src/stm32_adc.c deleted file mode 100644 index c2b993d18fe6c..0000000000000 --- a/boards/arm/stm32/nucleo-g431rb/src/stm32_adc.c +++ /dev/null @@ -1,240 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-g431rb/src/stm32_adc.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include "stm32.h" - -#if defined(CONFIG_ADC) && (defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2)) - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -/* 1 or 2 ADC devices (DEV1, DEV2) */ - -#if defined(CONFIG_STM32_ADC1) -# define DEV1_PORT 1 -#endif - -#if defined(CONFIG_STM32_ADC2) -# if defined(DEV1_PORT) -# define DEV2_PORT 2 -# else -# define DEV1_PORT 2 -# endif -#endif - -/* The number of ADC channels in the conversion list */ - -#define ADC1_NCHANNELS 3 -#define ADC2_NCHANNELS 3 - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* DEV 1 */ - -#if DEV1_PORT == 1 - -#define DEV1_NCHANNELS ADC1_NCHANNELS - -/* Identifying number of each ADC channel (even if NCHANNELS is less ) */ - -static const uint8_t g_chanlist1[3] = -{ - 1, - 2, - 15 -}; - -/* Configurations of pins used by each ADC channel */ - -static const uint32_t g_pinlist1[3] = -{ - GPIO_ADC1_IN1_0, /* PA0/A0 */ - GPIO_ADC1_IN2_0, /* PA1/A1 */ - GPIO_ADC1_IN15_0, /* PB0/A3 */ -}; - -#elif DEV1_PORT == 2 - -#define DEV1_NCHANNELS ADC2_NCHANNELS - -/* Identifying number of each ADC channel */ - -static const uint8_t g_chanlist1[3] = -{ - 17, - 7, - 6 -}; - -/* Configurations of pins used by each ADC channel */ - -static const uint32_t g_pinlist1[3] = -{ - GPIO_ADC2_IN17_0, /* PA4/A2 */ - GPIO_ADC2_IN7_0, /* PC1/A4 */ - GPIO_ADC2_IN6_0, /* PC0/A5 */ -}; - -#endif /* DEV1_PORT == 1 */ - -#ifdef DEV2_PORT - -/* DEV 2 */ - -#if DEV2_PORT == 2 - -#define DEV2_NCHANNELS ADC2_NCHANNELS - -/* Identifying number of each ADC channel */ - -static const uint8_t g_chanlist2[3] = -{ - 17, - 7, - 6 -}; - -/* Configurations of pins used by each ADC channel */ - -static const uint32_t g_pinlist2[3] = -{ - GPIO_ADC2_IN17_0, /* PA4/A2 */ - GPIO_ADC2_IN7_0, /* PC1/A4 */ - GPIO_ADC2_IN6_0, /* PC0/A5 */ -}; - -#endif /* DEV2_PORT == 2 */ -#endif /* DEV2_PORT */ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_adc_setup - * - * Description: - * Initialize ADC and register the ADC driver. - * - ****************************************************************************/ - -int stm32_adc_setup(void) -{ - static bool initialized = false; - struct adc_dev_s *adc; - int ret; - int i; - - /* Check if we have already initialized */ - - if (!initialized) - { - /* DEV1 */ - - /* Configure the pins as analog inputs for the selected channels */ - - for (i = 0; i < DEV1_NCHANNELS; i++) - { - stm32_configgpio(g_pinlist1[i]); - } - - /* Call stm32_adcinitialize() to get an instance of the ADC interface */ - - adc = stm32_adcinitialize(DEV1_PORT, g_chanlist1, DEV1_NCHANNELS); - if (adc == NULL) - { - aerr("Failed to get ADC interface 1\n"); - return -ENODEV; - } - - /* Register the ADC driver at "/dev/adc0" */ - - ret = adc_register("/dev/adc0", adc); - if (ret < 0) - { - aerr("adc_register /dev/adc0 failed: %d\n", ret); - return ret; - } - -#ifdef DEV2_PORT - - /* DEV2 */ - - /* Configure the pins as analog inputs for the selected channels */ - - for (i = 0; i < DEV2_NCHANNELS; i++) - { - stm32_configgpio(g_pinlist2[i]); - } - - /* Call stm32_adcinitialize() to get an instance of the ADC interface */ - - adc = stm32_adcinitialize(DEV2_PORT, g_chanlist2, DEV2_NCHANNELS); - if (adc == NULL) - { - aerr("Failed to get ADC interface 2\n"); - return -ENODEV; - } - - /* Register the ADC driver at "/dev/adc1" */ - - ret = adc_register("/dev/adc1", adc); - if (ret < 0) - { - aerr("adc_register /dev/adc1 failed: %d\n", ret); - return ret; - } -#endif - - initialized = true; - } - - return OK; -} - -#endif /* CONFIG_ADC && (CONFIG_STM32_ADC1 || CONFIG_STM32_ADC2) */ diff --git a/boards/arm/stm32/nucleo-g431rb/src/stm32_autoleds.c b/boards/arm/stm32/nucleo-g431rb/src/stm32_autoleds.c deleted file mode 100644 index 4c599539d004c..0000000000000 --- a/boards/arm/stm32/nucleo-g431rb/src/stm32_autoleds.c +++ /dev/null @@ -1,80 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-g431rb/src/stm32_autoleds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include "stm32.h" -#include "nucleo-g431rb.h" - -#if defined(CONFIG_ARCH_LEDS) - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_autoled_initialize - ****************************************************************************/ - -void board_autoled_initialize(void) -{ - /* Configure LED GPIOs for output */ - - stm32_configgpio(GPIO_LED1); -} - -/**************************************************************************** - * Name: board_autoled_on - ****************************************************************************/ - -void board_autoled_on(int led) -{ - if (led == BOARD_LED1) - { - stm32_gpiowrite(GPIO_LED1, true); - } -} - -/**************************************************************************** - * Name: board_autoled_off - ****************************************************************************/ - -void board_autoled_off(int led) -{ - if (led == BOARD_LED1) - { - stm32_gpiowrite(GPIO_LED1, false); - } -} - -#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/nucleo-g431rb/src/stm32_boot.c b/boards/arm/stm32/nucleo-g431rb/src/stm32_boot.c deleted file mode 100644 index 9cddcb3b09346..0000000000000 --- a/boards/arm/stm32/nucleo-g431rb/src/stm32_boot.c +++ /dev/null @@ -1,95 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-g431rb/src/stm32_boot.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include "nucleo-g431rb.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_boardinitialize - * - * Description: - * All STM32 architectures must provide the following entry point. This - * entry point is called early in the initialization -- after all memory - * has been configured and mapped but before any devices have been - * initialized. - * - ****************************************************************************/ - -void stm32_boardinitialize(void) -{ - /* Configure on-board LEDs if LED support has been selected. */ - -#ifdef CONFIG_ARCH_LEDS - board_autoled_initialize(); -#endif -} - -/**************************************************************************** - * Name: board_late_initialize - * - * Description: - * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional - * initialization call will be performed in the boot-up sequence to a - * function called board_late_initialize(). board_late_initialize() will - * be called immediately after up_initialize() is called and just before - * the initial application is started. This additional initialization - * phase may be used, for example, to initialize board-specific device - * drivers. - * - ****************************************************************************/ - -#ifdef CONFIG_BOARD_LATE_INITIALIZE -void board_late_initialize(void) -{ - /* Perform board-specific initialization */ - - stm32_bringup(); -} -#endif diff --git a/boards/arm/stm32/nucleo-g431rb/src/stm32_bringup.c b/boards/arm/stm32/nucleo-g431rb/src/stm32_bringup.c deleted file mode 100644 index 5eabcf6079811..0000000000000 --- a/boards/arm/stm32/nucleo-g431rb/src/stm32_bringup.c +++ /dev/null @@ -1,185 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-g431rb/src/stm32_bringup.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include - -#ifdef CONFIG_USERLED -# include -#endif - -#ifdef CONFIG_INPUT_BUTTONS -# include -#endif - -#ifdef CONFIG_SENSORS_QENCODER -# include "board_qencoder.h" -#endif - -#include "nucleo-g431rb.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#undef HAVE_LEDS - -#if !defined(CONFIG_ARCH_LEDS) && defined(CONFIG_USERLED_LOWER) -# define HAVE_LEDS 1 -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_bringup - * - * Description: - * Perform architecture-specific initialization - * - * CONFIG_BOARD_LATE_INITIALIZE=y : - * Called from board_late_initialize(). - * - ****************************************************************************/ - -int stm32_bringup(void) -{ - int ret; - -#ifdef CONFIG_FS_PROCFS - /* Mount the procfs file system */ - - ret = nx_mount(NULL, STM32_PROCFS_MOUNTPOINT, "procfs", 0, NULL); - if (ret < 0) - { - syslog(LOG_ERR, - "ERROR: Failed to mount the PROC filesystem: %d\n", ret); - } -#endif /* CONFIG_FS_PROCFS */ - -#ifdef CONFIG_INPUT_BUTTONS - /* Register the BUTTON driver */ - - ret = btn_lower_initialize("/dev/buttons"); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: btn_lower_initialize() failed: %d\n", ret); - } -#endif - -#ifdef HAVE_LEDS - /* Register the LED driver */ - - ret = userled_lower_initialize(LED_DRIVER_PATH); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: userled_lower_initialize() failed: %d\n", ret); - return ret; - } -#endif - -#ifdef CONFIG_PWM - /* Initialize PWM and register the PWM driver. */ - - ret = stm32_pwm_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_pwm_setup failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_STM32_FOC - /* Initialize and register the FOC device - must be before ADC setup */ - - ret = stm32_foc_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_foc_setup failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_ADC - /* Initialize ADC and register the ADC driver. */ - - ret = stm32_adc_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_adc_setup failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_MATH_CORDIC - /* Initialize CORDIC and register the CORDIC driver. */ - - ret = stm32_cordic_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_cordic_setup failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_SENSORS_QENCODER - /* Initialize and register the qencoder driver */ - - ret = board_qencoder_initialize(0, CONFIG_NUCLEO_G431RB_QETIMER); - if (ret != OK) - { - syslog(LOG_ERR, - "ERROR: Failed to register the qencoder: %d\n", - ret); - return ret; - } -#endif - -#ifdef CONFIG_STM32_FDCAN_CHARDRIVER - /* Initialize CAN and register the CAN driver. */ - - ret = stm32_can_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_fdcan_setup failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_STM32_FDCAN_SOCKET - /* Initialize CAN socket interface */ - - ret = stm32_cansock_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_cansock_setup failed: %d\n", ret); - } -#endif - - UNUSED(ret); - return OK; -} diff --git a/boards/arm/stm32/nucleo-g431rb/src/stm32_buttons.c b/boards/arm/stm32/nucleo-g431rb/src/stm32_buttons.c deleted file mode 100644 index 462f70b091a77..0000000000000 --- a/boards/arm/stm32/nucleo-g431rb/src/stm32_buttons.c +++ /dev/null @@ -1,113 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-g431rb/src/stm32_buttons.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include "stm32.h" -#include "nucleo-g431rb.h" - -#ifdef CONFIG_ARCH_BUTTONS - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_button_initialize - * - * Description: - * board_button_initialize() must be called to initialize button - * resources. After that, board_buttons() may be called to collect the - * current state of all buttons or board_button_irq() may be called to - * register button interrupt handlers. - * - ****************************************************************************/ - -uint32_t board_button_initialize(void) -{ - /* Configure the single button as an input. NOTE that EXTI interrupts are - * also configured for the pin. - */ - - stm32_configgpio(GPIO_BTN_USER); - return NUM_BUTTONS; -} - -/**************************************************************************** - * Name: board_buttons - * - * Description: - * After board_button_initialize() has been called, board_buttons() may be - * called to collect the state of all buttons. board_buttons() returns an - * 32-bit unsigned integer with each bit associated with a button. See the - * BUTTON_*_BIT definitions in board.h for the meaning of each bit. - * - ****************************************************************************/ - -uint32_t board_buttons(void) -{ - /* Check the state of the USER button. A HIGH value means that the key is - * pressed. - */ - - return stm32_gpioread(GPIO_BTN_USER) ? BUTTON_USER_BIT : 0; -} - -/**************************************************************************** - * Name: board_button_irq - * - * Description: - * board_button_irq() may be called to register an interrupt handler that - * will be called when a button is depressed or released. The ID value is - * a button enumeration value that uniquely identifies a button resource. - * See the BUTTON_* definitions in board.h for the meaning of the - * enumeration value. - * - ****************************************************************************/ - -#ifdef CONFIG_ARCH_IRQBUTTONS -int board_button_irq(int id, xcpt_t irqhandler, void *arg) -{ - int ret = -EINVAL; - - if (id == BUTTON_USER) - { - ret = stm32_gpiosetevent(GPIO_BTN_USER, true, true, true, irqhandler, - arg); - } - - return ret; -} -#endif - -#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/stm32/nucleo-g431rb/src/stm32_can.c b/boards/arm/stm32/nucleo-g431rb/src/stm32_can.c deleted file mode 100644 index 6f777f22c6148..0000000000000 --- a/boards/arm/stm32/nucleo-g431rb/src/stm32_can.c +++ /dev/null @@ -1,91 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-g431rb/src/stm32_can.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32.h" -#include "stm32_fdcan.h" -#include "nucleo-g431rb.h" - -#ifdef CONFIG_CAN - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -#if !defined(CONFIG_STM32_FDCAN1) -# error "No CAN is enable. Please enable at least one CAN device" -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_can_setup - * - * Description: - * Initialize CAN and register the CAN device - * - ****************************************************************************/ - -int stm32_can_setup(void) -{ - struct can_dev_s *can; - int ret; - - /* Call stm32_fdcaninitialize() to get an instance of the CAN interface */ - - can = stm32_fdcaninitialize(1); - if (can == NULL) - { - canerr("ERROR: Failed to get CAN interface\n"); - return -ENODEV; - } - - /* Register the CAN driver at "/dev/can0" */ - - ret = can_register("/dev/can0", can); - if (ret < 0) - { - canerr("ERROR: can_register failed: %d\n", ret); - return ret; - } - - return OK; -} - -#endif /* CONFIG_CAN */ diff --git a/boards/arm/stm32/nucleo-g431rb/src/stm32_cansock.c b/boards/arm/stm32/nucleo-g431rb/src/stm32_cansock.c deleted file mode 100644 index 72b03dc2324b0..0000000000000 --- a/boards/arm/stm32/nucleo-g431rb/src/stm32_cansock.c +++ /dev/null @@ -1,59 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-g431rb/src/stm32_cansock.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include "stm32_fdcan.h" - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_cansock_setup - * - * Description: - * Initialize CAN socket interface - * - ****************************************************************************/ - -int stm32_cansock_setup(void) -{ - int ret; - - /* Call stm32_fdcaninitialize() to get an instance of the FDCAN interface */ - - ret = stm32_fdcansockinitialize(1); - if (ret < 0) - { - canerr("ERROR: Failed to get FDCAN interface %d\n", ret); - return ret; - } - - return OK; -} diff --git a/boards/arm/stm32/nucleo-g431rb/src/stm32_cordic.c b/boards/arm/stm32/nucleo-g431rb/src/stm32_cordic.c deleted file mode 100644 index aa3a53201768c..0000000000000 --- a/boards/arm/stm32/nucleo-g431rb/src/stm32_cordic.c +++ /dev/null @@ -1,89 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-g431rb/src/stm32_cordic.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include - -#include "stm32_cordic.h" - -#include "nucleo-g431rb.h" - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_cordic_setup - * - * Description: - * Initialize CORDIC and register the CORDIC device. - * - ****************************************************************************/ - -int stm32_cordic_setup(void) -{ - struct cordic_lowerhalf_s *cordic = NULL; - static bool initialized = false; - int ret = OK; - - /* Have we already initialized? */ - - if (!initialized) - { - /* Call stm32_cordicinitialize() to get an instance of the CORDIC - * interface - */ - - cordic = stm32_cordicinitialize(); - if (!cordic) - { - tmrerr("Failed to get the STM32 CORDIC lower half\n"); - ret = -ENODEV; - goto errout; - } - - /* Register the CORDIC driver at "/dev/cordic0" */ - - ret = cordic_register("/dev/cordic0", cordic); - if (ret < 0) - { - tmrerr("cordic_register failed: %d\n", ret); - goto errout; - } - - /* Now we are initialized */ - - initialized = true; - } - -errout: - return ret; -} diff --git a/boards/arm/stm32/nucleo-g431rb/src/stm32_pwm.c b/boards/arm/stm32/nucleo-g431rb/src/stm32_pwm.c deleted file mode 100644 index ce64c50083ba4..0000000000000 --- a/boards/arm/stm32/nucleo-g431rb/src/stm32_pwm.c +++ /dev/null @@ -1,86 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-g431rb/src/stm32_pwm.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32_pwm.h" -#include "nucleo-g431rb.h" - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_pwm_setup - * - * Description: - * Initialize PWM and register the PWM device. - * - ****************************************************************************/ - -int stm32_pwm_setup(void) -{ - static bool initialized = false; - struct pwm_lowerhalf_s *pwm; - int ret; - - /* Have we already initialized? */ - - if (!initialized) - { - /* Call stm32_pwminitialize() to get an instance of the PWM interface */ - - pwm = stm32_pwminitialize(NUCLEOG431RB_PWMTIMER); - if (!pwm) - { - tmrerr("Failed to get the STM32 PWM lower half\n"); - return -ENODEV; - } - - /* Register the PWM driver at "/dev/pwm0" */ - - ret = pwm_register("/dev/pwm0", pwm); - if (ret < 0) - { - tmrerr("pwm_register failed: %d\n", ret); - return ret; - } - - /* Now we are initialized */ - - initialized = true; - } - - return OK; -} diff --git a/boards/arm/stm32/nucleo-g431rb/src/stm32_userleds.c b/boards/arm/stm32/nucleo-g431rb/src/stm32_userleds.c deleted file mode 100644 index 43528165fb31c..0000000000000 --- a/boards/arm/stm32/nucleo-g431rb/src/stm32_userleds.c +++ /dev/null @@ -1,77 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-g431rb/src/stm32_userleds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include - -#include "stm32.h" -#include "nucleo-g431rb.h" - -#if !defined(CONFIG_ARCH_LEDS) - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_userled_initialize - ****************************************************************************/ - -uint32_t board_userled_initialize(void) -{ - /* Configure LED GPIOs for output */ - - stm32_configgpio(GPIO_LED1); - return BOARD_NLEDS; -} - -/**************************************************************************** - * Name: board_userled - ****************************************************************************/ - -void board_userled(int led, bool ledon) -{ - if (led == BOARD_LED1) - { - stm32_gpiowrite(GPIO_LED1, ledon); - } -} - -/**************************************************************************** - * Name: board_userled_all - ****************************************************************************/ - -void board_userled_all(uint32_t ledset) -{ - stm32_gpiowrite(GPIO_LED1, (ledset & BOARD_LED1_BIT) != 0); -} - -#endif /* !CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/nucleo-g474re/CMakeLists.txt b/boards/arm/stm32/nucleo-g474re/CMakeLists.txt deleted file mode 100644 index 7fcedbbbecbf8..0000000000000 --- a/boards/arm/stm32/nucleo-g474re/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/nucleo-g474re/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32/nucleo-g474re/configs/lpuartnsh/defconfig b/boards/arm/stm32/nucleo-g474re/configs/lpuartnsh/defconfig deleted file mode 100644 index bbfd0aa9b5223..0000000000000 --- a/boards/arm/stm32/nucleo-g474re/configs/lpuartnsh/defconfig +++ /dev/null @@ -1,46 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_LEDS is not set -# CONFIG_DISABLE_OS_API is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="nucleo-g474re" -CONFIG_ARCH_BOARD_NUCLEO_G474RE=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32G474R=y -CONFIG_ARCH_HIPRI_INTERRUPT=y -CONFIG_ARCH_RAMVECTORS=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_ARMV7M_LIBM=y -CONFIG_ARMV7M_MEMCPY=y -CONFIG_BOARD_LOOPSPERMSEC=0 -CONFIG_DEBUG_FEATURES=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_LIBM=y -CONFIG_LINE_MAX=64 -CONFIG_LPUART1_SERIAL_CONSOLE=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PRIORITY_INHERITANCE=y -CONFIG_RAM_SIZE=98304 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_LPWORK=y -CONFIG_SCHED_WAITPID=y -CONFIG_STM32_DMA1=y -CONFIG_STM32_DMA2=y -CONFIG_STM32_DMAMUX1=y -CONFIG_STM32_FLASH_CONFIG_E=y -CONFIG_STM32_LPUART1=y -CONFIG_STM32_USART3=y -CONFIG_SYSTEM_NSH=y -CONFIG_USERLED=y -CONFIG_USERLED_LOWER=y diff --git a/boards/arm/stm32/nucleo-g474re/configs/nsh/defconfig b/boards/arm/stm32/nucleo-g474re/configs/nsh/defconfig deleted file mode 100644 index 0850c88d054b0..0000000000000 --- a/boards/arm/stm32/nucleo-g474re/configs/nsh/defconfig +++ /dev/null @@ -1,41 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_LEDS is not set -# CONFIG_DISABLE_OS_API is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="nucleo-g474re" -CONFIG_ARCH_BOARD_NUCLEO_G474RE=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32G474R=y -CONFIG_ARCH_HIPRI_INTERRUPT=y -CONFIG_ARCH_RAMVECTORS=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_ARMV7M_LIBM=y -CONFIG_ARMV7M_MEMCPY=y -CONFIG_BOARD_LOOPSPERMSEC=0 -CONFIG_DEBUG_FEATURES=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_LIBM=y -CONFIG_LINE_MAX=64 -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PRIORITY_INHERITANCE=y -CONFIG_RAM_SIZE=98304 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_LPWORK=y -CONFIG_SCHED_WAITPID=y -CONFIG_STM32_USART3=y -CONFIG_SYSTEM_NSH=y -CONFIG_USART3_SERIAL_CONSOLE=y -CONFIG_USERLED=y -CONFIG_USERLED_LOWER=y diff --git a/boards/arm/stm32/nucleo-g474re/configs/usbserial/defconfig b/boards/arm/stm32/nucleo-g474re/configs/usbserial/defconfig deleted file mode 100644 index e93dcf5ab625f..0000000000000 --- a/boards/arm/stm32/nucleo-g474re/configs/usbserial/defconfig +++ /dev/null @@ -1,51 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_LEDS is not set -# CONFIG_DISABLE_OS_API is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="nucleo-g474re" -CONFIG_ARCH_BOARD_NUCLEO_G474RE=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32G474R=y -CONFIG_ARCH_HIPRI_INTERRUPT=y -CONFIG_ARCH_RAMVECTORS=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_ARMV7M_LIBM=y -CONFIG_ARMV7M_MEMCPY=y -CONFIG_BOARD_LOOPSPERMSEC=0 -CONFIG_CDCACM=y -CONFIG_DEBUG_FEATURES=y -CONFIG_DEBUG_HARDFAULT_INFO=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_DEBUG_USB=y -CONFIG_DEBUG_USB_ERROR=y -CONFIG_DEBUG_USB_WARN=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_LIBM=y -CONFIG_LINE_MAX=64 -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PRIORITY_INHERITANCE=y -CONFIG_RAM_SIZE=98304 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_LPWORK=y -CONFIG_SCHED_WAITPID=y -CONFIG_STM32_USART3=y -CONFIG_STM32_USBFS=y -CONFIG_SYSTEM_NSH=y -CONFIG_USART3_SERIAL_CONSOLE=y -CONFIG_USBDEV_BUSPOWERED=y -CONFIG_USBDEV_DUALSPEED=y -CONFIG_USBDEV_ISOCHRONOUS=y -CONFIG_USBDEV_MAXPOWER=500 -CONFIG_USERLED=y -CONFIG_USERLED_LOWER=y diff --git a/boards/arm/stm32/nucleo-g474re/include/board.h b/boards/arm/stm32/nucleo-g474re/include/board.h deleted file mode 100644 index bbc4cf8cf354b..0000000000000 --- a/boards/arm/stm32/nucleo-g474re/include/board.h +++ /dev/null @@ -1,191 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-g474re/include/board.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __BOARDS_ARM_STM32_NUCLEO-G474RE_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32_NUCLEO-G474RE_INCLUDE_BOARD_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Clocking *****************************************************************/ - -#undef STM32_BOARD_XTAL /* Not installed by default */ - -#define STM32_HSI_FREQUENCY 16000000ul /* 16MHz */ -#define STM32_LSI_FREQUENCY 32000 /* 32kHz */ -#undef STM32_HSE_FREQUENCY /* Not installed by default */ -#undef STM32_LSE_FREQUENCY /* Not available on this board */ - -/* Main PLL Configuration. - * - * PLL source is HSI = 16MHz - * PLLN = 85, PLLM = 4, PLLP = 10, PLLQ = 2, PLLR = 2 - * - * f(VCO Clock) = f(PLL Clock Input) x (PLLN / PLLM) - * f(PLL_P) = f(VCO Clock) / PLLP - * f(PLL_Q) = f(VCO Clock) / PLLQ - * f(PLL_R) = f(VCO Clock) / PLLR - * - * Where: - * 8 <= PLLN <= 127 - * 1 <= PLLM <= 16 - * PLLP = 2 through 31 - * PLLQ = 2, 4, 6, or 8 - * PLLR = 2, 4, 6, or 8 - * - * Do not exceed 170MHz on f(PLL_P), f(PLL_Q), or f(PLL_R). - * 64MHz <= f(VCO Clock) <= 344MHz. - * - * Given the above: - * - * f(VCO Clock) = HSI x PLLN / PLLM - * = 16MHz x 85 / 4 - * = 340MHz - * - * PLLPCLK = f(VCO Clock) / PLLP - * = 340MHz / 10 - * = 34MHz - * (May be used for ADC) - * - * PLLQCLK = f(VCO Clock) / PLLQ - * = 340MHz / 2 - * = 170MHz - * (May be used for QUADSPI, FDCAN, SAI1, I2S3. If set to - * 48MHz, may be used for USB, RNG.) - * - * PLLRCLK = f(VCO Clock) / PLLR - * = 340MHz / 2 - * = 170MHz - * (May be used for SYSCLK and most peripherals.) - */ - -#define STM32_PLLCFGR_PLLSRC RCC_PLLCFGR_PLLSRC_HSI -#define STM32_PLLCFGR_PLLCFG (RCC_PLLCFGR_PLLPEN | \ - RCC_PLLCFGR_PLLQEN | \ - RCC_PLLCFGR_PLLREN) - -#define STM32_PLLCFGR_PLLN RCC_PLLCFGR_PLLN(85) -#define STM32_PLLCFGR_PLLM RCC_PLLCFGR_PLLM(4) -#define STM32_PLLCFGR_PLLP RCC_PLLCFGR_PLLPDIV(10) -#define STM32_PLLCFGR_PLLQ RCC_PLLCFGR_PLLQ_2 -#define STM32_PLLCFGR_PLLR RCC_PLLCFGR_PLLR_2 - -#define STM32_VCO_FREQUENCY ((STM32_HSI_FREQUENCY / 4) * 85) -#define STM32_PLLP_FREQUENCY (STM32_VCO_FREQUENCY / 10) -#define STM32_PLLQ_FREQUENCY (STM32_VCO_FREQUENCY / 2) -#define STM32_PLLR_FREQUENCY (STM32_VCO_FREQUENCY / 2) - -/* Use the PLL and set the SYSCLK source to be PLLR (170MHz) */ - -#define STM32_SYSCLK_SW RCC_CFGR_SW_PLL -#define STM32_SYSCLK_SWS RCC_CFGR_SWS_PLL -#define STM32_SYSCLK_FREQUENCY STM32_PLLR_FREQUENCY - -/* AHB clock (HCLK) is SYSCLK (170MHz) */ - -#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK -#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY - -/* APB1 clock (PCLK1) is HCLK (170MHz) */ - -#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK -#define STM32_PCLK1_FREQUENCY STM32_HCLK_FREQUENCY - -/* APB2 clock (PCLK2) is HCLK (170MHz) */ - -#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK -#define STM32_PCLK2_FREQUENCY STM32_HCLK_FREQUENCY - -/* LED definitions **********************************************************/ - -/* The NucleoG474RE board has one user LED. - * - * If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs in - * any way. The following definitions are used to access individual LEDs. - */ - -/* LED index values for use with board_userled() */ - -#define BOARD_LED1 0 /* LD2 (Green) */ -#define BOARD_NLEDS 1 - -/* LED bits for use with board_userled_all() */ - -#define BOARD_LED1_BIT (1 << BOARD_LED1) - -/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the 4 user LEDs - * on the board. The following definitions describe how NuttX controls the - * LEDs: - * - * |--------------------|-------------------------|------------| - * | SYMBOL | Meaning | LED states | - * |--------------------|-------------------------|------------| - * | LED_STARTED | NuttX has been started | 0 0 0 0 | - * | LED_HEAPALLOCATE | Heap has been allocated | 0 0 0 0 | - * | LED_IRQSENABLED | Interrupts enabled | 0 0 0 0 | - * | LED_STACKCREATED | Idle stack created | 1 0 0 0 | - * | LED_INIRQ | In an interrupt | No change | - * | LED_SIGNAL | In a signal handler | No change | - * | LED_ASSERTION | An assertion failed | No change | - * | LED_PANIC | The system has crashed | 0 B 0 0 | - * | LED_IDLE | STM32 is in sleep mode | Not used | - * |--------------------|-------------------------|------------| - * - * LED states legend: - * 0 = off - * 1 = on - * B = blink - */ - -#define LED_STARTED 0 -#define LED_HEAPALLOCATE 0 -#define LED_IRQSENABLED 0 -#define LED_STACKCREATED 1 -#define LED_INIRQ 2 -#define LED_SIGNAL 2 -#define LED_ASSERTION 2 -#define LED_PANIC 3 - -/* Button definitions *******************************************************/ - -/* Alternate function pin selections ****************************************/ - -/* LPUART1 (ST LINK V3E Virtual Console) */ -#define GPIO_LPUART1_TX GPIO_LPUART1_TX_1 /* PA2 */ -#define GPIO_LPUART1_RX GPIO_LPUART1_RX_1 /* PA3 */ -#define GPIO_LPUART1_CTS GPIO_LPUART1_CTS_1 /* PA6 */ -#define GPIO_LPUART1_RTS GPIO_LPUART1_RTS_1 /* PB1 */ - -/* USART3 Pins CN7 Pins 1 and 2 */ -#define GPIO_USART3_TX GPIO_USART3_TX_3 /* PC10 */ -#define GPIO_USART3_RX GPIO_USART3_RX_3 /* PC11 */ - -/* Pin Multiplexing Disambiguation ******************************************/ - -#endif /* __BOARDS_ARM_STM32_NUCLEO_G474RE_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32/nucleo-g474re/scripts/Make.defs b/boards/arm/stm32/nucleo-g474re/scripts/Make.defs deleted file mode 100644 index 977ae0d4707bb..0000000000000 --- a/boards/arm/stm32/nucleo-g474re/scripts/Make.defs +++ /dev/null @@ -1,51 +0,0 @@ -############################################################################ -# boards/arm/stm32/nucleo-g474re/scripts/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/.config -include $(TOPDIR)/tools/Config.mk -include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs - -ifeq ($(CONFIG_STM32_DFU),y) - LDSCRIPT = ld.script.dfu -else - LDSCRIPT = ld.script -endif - -ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) - -ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 - -CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) -CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) -CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -AFLAGS := $(CFLAGS) -D__ASSEMBLY__ - -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections -LDNXFLATFLAGS = -e main -s 2048 - -# Embed absolute path to source file in debug information so that Eclipse -# source level debugging won't get confused. See: -# https://stackoverflow.com/questions/1275476/gcc-gdb-how-to-embed-absolute-path-to-source-file-in-debug-information -CFLAGS += -fdebug-prefix-map=..=$(readlink -f ..) diff --git a/boards/arm/stm32/nucleo-g474re/scripts/ld.script b/boards/arm/stm32/nucleo-g474re/scripts/ld.script deleted file mode 100644 index 6ed340018bc45..0000000000000 --- a/boards/arm/stm32/nucleo-g474re/scripts/ld.script +++ /dev/null @@ -1,139 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-g474re/scripts/ld.script - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* The STM32G474RE has 512 KiB of FLASH beginning at address 0x0800:0000. - * - * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 - * where the code expects to begin execution by jumping to the entry point in - * the 0x0800:0000 address range. - * - * The STM32G474RE has a total of 128 KiB of SRAM in three separate areas: - * - * 1) 80 KiB SRAM1 mapped at 0x2000:0000 thru 0x2001:3fff. - * 2) 16 KiB SRAM2 mapped at 0x2001:4000 thru 0x2001:7fff. - * - * CCM SRAM (Routine Booster): - * - * 3) 32 KiB CCM SRAM mapped at 0x1000:0000 thru 0x1000:7fff - * but also aliased at at 0x2001:8000 thru 0x2001:ffff to be contiguous - * with the SRAM1 and SRAM2. - * - * Because SRAM1 and SRAM2 are contiguous, they are treated as one region - * by this logic. - * - * CCM SRAM is also contiguous to SRAM1 and SRAM2, however it is excluded - * from this linker script, to keep it reserved for special uses in code. - * REVISIT: Is this the correct way to handle CCM SRAM? - */ - -MEMORY -{ - flash (rx) : ORIGIN = 0x08000000, LENGTH = 512K - sram (rwx) : ORIGIN = 0x20000000, LENGTH = 96K -} - -OUTPUT_ARCH(arm) -EXTERN(_vectors) -ENTRY(_stext) - -SECTIONS -{ - .text : { - _stext = ABSOLUTE(.); - *(.vectors) - *(.text .text.*) - *(.fixup) - *(.gnu.warning) - *(.rodata .rodata.*) - *(.gnu.linkonce.t.*) - *(.glue_7) - *(.glue_7t) - *(.got) - *(.gcc_except_table) - *(.gnu.linkonce.r.*) - _etext = ABSOLUTE(.); - } > flash - - .init_section : ALIGN(4) { - _sinit = ABSOLUTE(.); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) - KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) - _einit = ABSOLUTE(.); - } > flash - - .ARM.extab : ALIGN(4) { - *(.ARM.extab*) - } > flash - - .ARM.exidx : ALIGN(4) { - __exidx_start = ABSOLUTE(.); - *(.ARM.exidx*) - __exidx_end = ABSOLUTE(.); - } > flash - - .tdata : { - _stdata = ABSOLUTE(.); - *(.tdata .tdata.* .gnu.linkonce.td.*); - _etdata = ABSOLUTE(.); - } > flash - - .tbss : { - _stbss = ABSOLUTE(.); - *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); - _etbss = ABSOLUTE(.); - } > flash - - _eronly = ABSOLUTE(.); - - .data : ALIGN(4) { - _sdata = ABSOLUTE(.); - *(.data .data.*) - *(.gnu.linkonce.d.*) - CONSTRUCTORS - . = ALIGN(4); - _edata = ABSOLUTE(.); - } > sram AT > flash - - .bss : ALIGN(4) { - _sbss = ABSOLUTE(.); - *(.bss .bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - . = ALIGN(4); - _ebss = ABSOLUTE(.); - } > sram - - /* Stabs debugging sections. */ - - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_info 0 : { *(.debug_info) } - .debug_line 0 : { *(.debug_line) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_aranges 0 : { *(.debug_aranges) } -} diff --git a/boards/arm/stm32/nucleo-g474re/scripts/ld.script.dfu b/boards/arm/stm32/nucleo-g474re/scripts/ld.script.dfu deleted file mode 100644 index e35b09cec8937..0000000000000 --- a/boards/arm/stm32/nucleo-g474re/scripts/ld.script.dfu +++ /dev/null @@ -1,142 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-g474re/scripts/ld.script - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* The STM32G474RE has 512 KiB of FLASH beginning at address 0x0800:0000. - * - * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 - * where the code expects to begin execution by jumping to the entry point in - * the 0x0800:0000 address range. The FLASH bootloader is located there and - * allocated up to 24KiB (6 pages of 4k if single bank mode or 12 pages of 2k - * if dual bank mode), so our executable will begin at 0x0800:6000, leaving - * 488KiB. - * - * The STM32G474RE has a total of 128 KiB of SRAM in three separate areas: - * - * 1) 80 KiB SRAM1 mapped at 0x2000:0000 thru 0x2001:3fff. - * 2) 16 KiB SRAM2 mapped at 0x2001:4000 thru 0x2001:7fff. - * - * CCM SRAM (Routine Booster): - * - * 3) 32 KiB CCM SRAM mapped at 0x1000:0000 thru 0x1000:7fff - * but also aliased at at 0x2001:8000 thru 0x2001:ffff to be contiguous - * with the SRAM1 and SRAM2. - * - * Because SRAM1 and SRAM2 are contiguous, they are treated as one region - * by this logic. - * - * CCM SRAM is also contiguous to SRAM1 and SRAM2, however it is excluded - * from this linker script, to keep it reserved for special uses in code. - * REVISIT: Is this the correct way to handle CCM SRAM? - */ - -MEMORY -{ - flash (rx) : ORIGIN = 0x08006000, LENGTH = 488K - sram (rwx) : ORIGIN = 0x20000000, LENGTH = 96K -} - -OUTPUT_ARCH(arm) -EXTERN(_vectors) -ENTRY(_stext) - -SECTIONS -{ - .text : { - _stext = ABSOLUTE(.); - *(.vectors) - *(.text .text.*) - *(.fixup) - *(.gnu.warning) - *(.rodata .rodata.*) - *(.gnu.linkonce.t.*) - *(.glue_7) - *(.glue_7t) - *(.got) - *(.gcc_except_table) - *(.gnu.linkonce.r.*) - _etext = ABSOLUTE(.); - } > flash - - .init_section : ALIGN(4) { - _sinit = ABSOLUTE(.); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) - KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) - _einit = ABSOLUTE(.); - } > flash - - .ARM.extab : ALIGN(4) { - *(.ARM.extab*) - } > flash - - .ARM.exidx : ALIGN(4) { - __exidx_start = ABSOLUTE(.); - *(.ARM.exidx*) - __exidx_end = ABSOLUTE(.); - } > flash - - .tdata : { - _stdata = ABSOLUTE(.); - *(.tdata .tdata.* .gnu.linkonce.td.*); - _etdata = ABSOLUTE(.); - } > flash - - .tbss : { - _stbss = ABSOLUTE(.); - *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); - _etbss = ABSOLUTE(.); - } > flash - - _eronly = ABSOLUTE(.); - - .data : ALIGN(4) { - _sdata = ABSOLUTE(.); - *(.data .data.*) - *(.gnu.linkonce.d.*) - CONSTRUCTORS - . = ALIGN(4); - _edata = ABSOLUTE(.); - } > sram AT > flash - - .bss : ALIGN(4) { - _sbss = ABSOLUTE(.); - *(.bss .bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - . = ALIGN(4); - _ebss = ABSOLUTE(.); - } > sram - - /* Stabs debugging sections. */ - - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_info 0 : { *(.debug_info) } - .debug_line 0 : { *(.debug_line) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_aranges 0 : { *(.debug_aranges) } -} diff --git a/boards/arm/stm32/nucleo-g474re/src/CMakeLists.txt b/boards/arm/stm32/nucleo-g474re/src/CMakeLists.txt deleted file mode 100644 index 53f5643fc8bab..0000000000000 --- a/boards/arm/stm32/nucleo-g474re/src/CMakeLists.txt +++ /dev/null @@ -1,37 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/nucleo-g474re/src/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -set(SRCS stm32_boot.c stm32_bringup.c) - -if(CONFIG_ARCH_LEDS) - list(APPEND SRCS stm32_autoleds.c) -else() - list(APPEND SRCS stm32_userleds.c) -endif() - -if(CONFIG_USBDEV) - list(APPEND SRCS stm32_usbdev.c) -endif() - -target_sources(board PRIVATE ${SRCS}) - -set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/ld.script") diff --git a/boards/arm/stm32/nucleo-g474re/src/Make.defs b/boards/arm/stm32/nucleo-g474re/src/Make.defs deleted file mode 100644 index b27f9af351497..0000000000000 --- a/boards/arm/stm32/nucleo-g474re/src/Make.defs +++ /dev/null @@ -1,40 +0,0 @@ -############################################################################ -# boards/arm/stm32/nucleo-g474re/src/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/Make.defs - -ASRCS = -CSRCS = stm32_boot.c stm32_bringup.c - -ifeq ($(CONFIG_ARCH_LEDS),y) -CSRCS += stm32_autoleds.c -else -CSRCS += stm32_userleds.c -endif - -ifeq ($(CONFIG_USBDEV),y) - CSRCS += stm32_usbdev.c -endif - -DEPPATH += --dep-path board -VPATH += :board -CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/nucleo-g474re/src/stm32_autoleds.c b/boards/arm/stm32/nucleo-g474re/src/stm32_autoleds.c deleted file mode 100644 index c06b2fb11b508..0000000000000 --- a/boards/arm/stm32/nucleo-g474re/src/stm32_autoleds.c +++ /dev/null @@ -1,84 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-g474re/src/stm32_autoleds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include "stm32.h" -#include "nucleo-g474re.h" - -#if defined(CONFIG_ARCH_LEDS) - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_autoled_initialize - ****************************************************************************/ - -void board_autoled_initialize(void) -{ - /* Configure LED1 GPIO for output */ - - stm32_configgpio(GPIO_LED1); -} - -/**************************************************************************** - * Name: board_autoled_on - ****************************************************************************/ - -void board_autoled_on(int led) -{ - switch (led) - { - case BOARD_LED1: - stm32_gpiowrite(GPIO_LED1, true); - break; - } -} - -/**************************************************************************** - * Name: board_autoled_off - ****************************************************************************/ - -void board_autoled_off(int led) -{ - switch (led) - { - case BOARD_LED1: - stm32_gpiowrite(GPIO_LED1, false); - break; - } -} - -#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/nucleo-g474re/src/stm32_boot.c b/boards/arm/stm32/nucleo-g474re/src/stm32_boot.c deleted file mode 100644 index 8f134c1cd9efa..0000000000000 --- a/boards/arm/stm32/nucleo-g474re/src/stm32_boot.c +++ /dev/null @@ -1,93 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-g474re/src/stm32_boot.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include "nucleo-g474re.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_boardinitialize - * - * Description: - * All STM32 architectures must provide the following entry point. This - * entry point is called early in the initialization -- after all memory - * has been configured and mapped but before any devices have been - * initialized. - * - ****************************************************************************/ - -void stm32_boardinitialize(void) -{ -#if defined(CONFIG_ARCH_LEDS) - /* Configure on-board LEDs if LED support has been selected. */ - - board_autoled_initialize(); -#endif -} - -/**************************************************************************** - * Name: board_late_initialize - * - * Description: - * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional - * initialization call will be performed in the boot-up sequence to a - * function called board_late_initialize(). board_late_initialize() - * will be called immediately after up_initialize() is called and just - * before the initial application is started. - * This additional initialization phase may be used, for example, to - * initialize board-specific device drivers. - * - ****************************************************************************/ - -#ifdef CONFIG_BOARD_LATE_INITIALIZE -void board_late_initialize(void) -{ - stm32_bringup(); -} -#endif diff --git a/boards/arm/stm32/nucleo-g474re/src/stm32_bringup.c b/boards/arm/stm32/nucleo-g474re/src/stm32_bringup.c deleted file mode 100644 index bc3c6aa900739..0000000000000 --- a/boards/arm/stm32/nucleo-g474re/src/stm32_bringup.c +++ /dev/null @@ -1,92 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-g474re/src/stm32_bringup.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include -#include - -#include "nucleo-g474re.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#undef HAVE_LEDS - -#if !defined(CONFIG_ARCH_LEDS) && defined(CONFIG_USERLED_LOWER) -# define HAVE_LEDS 1 -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_bringup - * - * Description: - * Perform architecture-specific initialization - * - * CONFIG_BOARD_LATE_INITIALIZE=y : - * Called from board_late_initialize(). - * - ****************************************************************************/ - -int stm32_bringup(void) -{ - int ret; - -#if defined(HAVE_LEDS) - /* Register the LED driver */ - - ret = userled_lower_initialize(LED_DRIVER_PATH); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: userled_lower_initialize() failed: %d\n", ret); - return ret; - } -#endif - -#if defined(CONFIG_CDCACM) && !defined(CONFIG_CDCACM_CONSOLE) - /* Initialize CDCACM */ - - syslog(LOG_INFO, "Initialize CDCACM device\n"); - - ret = cdcacm_initialize(0, NULL); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: cdcacm_initialize failed: %d\n", ret); - } -#endif /* CONFIG_CDCACM & !CONFIG_CDCACM_CONSOLE */ - - UNUSED(ret); - return OK; -} diff --git a/boards/arm/stm32/nucleo-g474re/src/stm32_usbdev.c b/boards/arm/stm32/nucleo-g474re/src/stm32_usbdev.c deleted file mode 100644 index 898d118a8e708..0000000000000 --- a/boards/arm/stm32/nucleo-g474re/src/stm32_usbdev.c +++ /dev/null @@ -1,59 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-g474re/src/stm32_usbdev.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include - -#include -#include - -#include "arm_internal.h" -#include "stm32.h" -#include "nucleo-g474re.h" - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_usbsuspend - * - * Description: - * Board logic must provide the stm32_usbsuspend logic if the USBDEV driver - * is used. This function is called whenever the USB enters or leaves - * suspend mode. This is an opportunity for the board logic to shutdown - * clocks, power, etc. while the USB is suspended. - * - ****************************************************************************/ - -void stm32_usbsuspend(struct usbdev_s *dev, bool resume) -{ - uinfo("resume: %d\n", resume); -} diff --git a/boards/arm/stm32/nucleo-g474re/src/stm32_userleds.c b/boards/arm/stm32/nucleo-g474re/src/stm32_userleds.c deleted file mode 100644 index 2b7b61b153a2e..0000000000000 --- a/boards/arm/stm32/nucleo-g474re/src/stm32_userleds.c +++ /dev/null @@ -1,106 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-g474re/src/stm32_userleds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include - -#include "stm32.h" -#include "nucleo-g474re.h" - -#if !defined(CONFIG_ARCH_LEDS) - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_userled_initialize - * - * Description: - * Initialize the user LEDs before use. Note: For this function to be - * available to user application logic, CONFIG_ARCH_LEDS must not be - * defined. - ****************************************************************************/ - -uint32_t board_userled_initialize(void) -{ - /* Configure LED GPIOs for output */ - - stm32_configgpio(GPIO_LED1); - return BOARD_NLEDS; -} - -/**************************************************************************** - * Name: board_userled - * - * Description: - * Allow user application logic to control LEDs one at a time. Note: For - * this function to be available to user application logic, - * CONFIG_ARCH_LEDS must not be defined. - * - * Parameters: - * led: Index to the LED, which may be one of the defines BOARD_LED1, - * BOARD_LED2, BOARD_LED3, or BOARD_LED4. - * ledon: true to turn the LED on, false to turn it off. - ****************************************************************************/ - -void board_userled(int led, bool ledon) -{ - switch (led) - { - case BOARD_LED1: - stm32_gpiowrite(GPIO_LED1, ledon); - break; - } -} - -/**************************************************************************** - * Name: board_userled_all - * - * Description: - * Allow user application logic to control all LEDs in one function call. - * Note: For this function to be available to user application logic, - * CONFIG_ARCH_LEDS must not be defined. - * - * Parameters: - * ledset: Bitmask indicating the new state for all LEDs, where a set bit - * indicates LED on and a clear bit indicates LED off. To - * construct the bitmask, using a bitwise OR of the defines - * BOARD_LED1_BIT, BOARD_LED2_BIT, BOARD_LED3_BIT, and/or - * BOARD_LED4_BIT. - ****************************************************************************/ - -void board_userled_all(uint32_t ledset) -{ - stm32_gpiowrite(GPIO_LED1, (ledset & BOARD_LED1_BIT) != 0); -} - -#endif /* !CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/nucleo-l152re/CMakeLists.txt b/boards/arm/stm32/nucleo-l152re/CMakeLists.txt deleted file mode 100644 index 5a90572fa08db..0000000000000 --- a/boards/arm/stm32/nucleo-l152re/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/nucleo-l152re/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32/nucleo-l152re/configs/lcd/defconfig b/boards/arm/stm32/nucleo-l152re/configs/lcd/defconfig deleted file mode 100644 index 5695f7ee012f2..0000000000000 --- a/boards/arm/stm32/nucleo-l152re/configs/lcd/defconfig +++ /dev/null @@ -1,71 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NX_DISABLE_16BPP is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="nucleo-l152re" -CONFIG_ARCH_BOARD_NUCLEO_L152RE=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32L152RE=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=2796 -CONFIG_BUILTIN=y -CONFIG_DEBUG_FULLOPT=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_DISABLE_ENVIRON=y -CONFIG_EXAMPLES_HELLO=y -CONFIG_EXAMPLES_NX=y -CONFIG_EXAMPLES_NXDEMO=y -CONFIG_EXAMPLES_NXDEMO_BPP=16 -CONFIG_EXAMPLES_NX_BPP=16 -CONFIG_FS_PROCFS=y -CONFIG_FS_PROCFS_REGISTER=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INIT_STACKSIZE=1536 -CONFIG_INTELHEX_BINARY=y -CONFIG_LCD=y -CONFIG_LCD_EXTERNINIT=y -CONFIG_LCD_FRAMEBUFFER=y -CONFIG_LCD_ILI9341=y -CONFIG_LCD_ILI9341_IFACE0=y -CONFIG_LCD_ILI9341_IFACE0_PORTRAIT=y -CONFIG_LCD_PORTRAIT=y -CONFIG_LINE_MAX=64 -CONFIG_MQ_MAXMSGSIZE=64 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_NUNGET_CHARS=0 -CONFIG_NX=y -CONFIG_NXFONT_MONO5X8=y -CONFIG_NXFONT_SANS22X29B=y -CONFIG_NXFONT_SANS23X27=y -CONFIG_NX_BLOCKING=y -CONFIG_POSIX_SPAWN_DEFAULT_STACKSIZE=1536 -CONFIG_PREALLOC_TIMERS=4 -CONFIG_PTHREAD_MUTEX_UNSAFE=y -CONFIG_PTHREAD_STACK_DEFAULT=1536 -CONFIG_RAM_SIZE=81920 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=19 -CONFIG_START_MONTH=5 -CONFIG_START_YEAR=2013 -CONFIG_STDIO_DISABLE_BUFFERING=y -CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_PWR=y -CONFIG_STM32_USART2=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/nucleo-l152re/configs/nsh/defconfig b/boards/arm/stm32/nucleo-l152re/configs/nsh/defconfig deleted file mode 100644 index 4232102fb6154..0000000000000 --- a/boards/arm/stm32/nucleo-l152re/configs/nsh/defconfig +++ /dev/null @@ -1,53 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_NSH_ARGCAT is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="nucleo-l152re" -CONFIG_ARCH_BOARD_NUCLEO_L152RE=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32L152RE=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=2796 -CONFIG_BUILTIN=y -CONFIG_DEBUG_FULLOPT=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_DISABLE_ENVIRON=y -CONFIG_DISABLE_MOUNTPOINT=y -CONFIG_DISABLE_MQUEUE=y -CONFIG_DISABLE_POSIX_TIMERS=y -CONFIG_DISABLE_PSEUDOFS_OPERATIONS=y -CONFIG_EXAMPLES_HELLO=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INIT_STACKSIZE=1536 -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=64 -CONFIG_NSH_READLINE=y -CONFIG_NUNGET_CHARS=0 -CONFIG_POSIX_SPAWN_DEFAULT_STACKSIZE=1536 -CONFIG_PTHREAD_MUTEX_UNSAFE=y -CONFIG_PTHREAD_STACK_DEFAULT=1536 -CONFIG_RAM_SIZE=81920 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=19 -CONFIG_START_MONTH=5 -CONFIG_START_YEAR=2013 -CONFIG_STDIO_DISABLE_BUFFERING=y -CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_PWR=y -CONFIG_STM32_USART2=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/nucleo-l152re/include/board.h b/boards/arm/stm32/nucleo-l152re/include/board.h deleted file mode 100644 index 1c9ff4c06a5bd..0000000000000 --- a/boards/arm/stm32/nucleo-l152re/include/board.h +++ /dev/null @@ -1,227 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-l152re/include/board.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __BOARDS_ARM_STM32_NUCLEOL152RE_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32_NUCLEOL152RE_INCLUDE_BOARD_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#ifndef __ASSEMBLY__ -# include -# include -#endif - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Clocking *****************************************************************/ - -/* Four different clock sources can be used to drive the system clock - * (SYSCLK): - * - * - HSI high-speed internal oscillator clock - * Generated from an internal 16 MHz RC oscillator - * - HSE high-speed external oscillator clock. 8 MHz from MCO output of - * ST-LINK. - * - PLL clock - * - MSI multispeed internal oscillator clock - * The MSI clock signal is generated from an internal RC oscillator. - * Seven frequency ranges are available: 65.536 kHz, 131.072 kHz, - * 262.144 kHz, 524.288 kHz, 1.048 MHz, 2.097 MHz (default value) - * and 4.194 MHz. - * - * The devices have the following two secondary clock sources - * - LSI low-speed internal RC clock - * Drives the watchdog and RTC. Approximately 37KHz - * - LSE low-speed external oscillator clock - * Driven by 32.768KHz crystal (X2) on the OSC32_IN and OSC32_OUT pins. - */ - -#define STM32_BOARD_XTAL 8000000ul - -#define STM32_HSI_FREQUENCY 16000000ul -#define STM32_LSI_FREQUENCY 37000 /* Approximately 37KHz */ -#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL -#define STM32_LSE_FREQUENCY 32768 /* X2 on board */ - -/* PLL Configuration - * - * - PLL source is HSE -> 8MHz - * - PLL multiplier is 12 -> 96MHz PLL VCO clock output - * - PLL output divider 3 -> 32MHz divided down PLL VCO clock output - * - * Resulting SYSCLK frequency is 8MHz x 12 / 3 = 32MHz - * - * USB/SDIO: - * If the USB or SDIO interface is used in the application, the PLL VCO - * clock (defined by STM32_CFGR_PLLMUL) must be programmed to output a 96 - * MHz frequency. This is required to provide a 48 MHz clock to the USB or - * SDIO (SDIOCLK or USBCLK = PLLVCO/2). - * SYSCLK - * The system clock is derived from the PLL VCO divided by the output - * division factor. - * Limitations: - * 96 MHz as PLLVCO when the product is in range 1 (1.8V), - * 48 MHz as PLLVCO when the product is in range 2 (1.5V), - * 24 MHz when the product is in range 3 (1.2V). - * Output division to avoid exceeding 32 MHz as SYSCLK. - * The minimum input clock frequency for PLL is 2 MHz (when using HSE as - * PLL source). - */ - -#if 1 -#define STM32_CFGR_PLLSRC RCC_CFGR_PLLSRC /* PLL clocked by the HSE */ -#define STM32_HSEBYP_ENABLE 1 -#define STM32_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx12 /* PLLMUL = 12 */ -#define STM32_CFGR_PLLDIV RCC_CFGR_PLLDIV_3 /* PLLDIV = 3 */ -#define STM32_PLL_FREQUENCY (12*STM32_BOARD_XTAL) /* PLL VCO Frequency is 96MHz */ -#else -#define STM32_CFGR_PLLSRC 0 /* PLL clocked by the HSI RC */ -#define STM32_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx6 /* PLLMUL = 6 */ -#define STM32_CFGR_PLLDIV RCC_CFGR_PLLDIV_3 /* PLLDIV = 3 */ -#define STM32_PLL_FREQUENCY (6*STM32_HSI_FREQUENCY) /* PLL VCO Frequency is 96MHz */ -#endif - -/* Use the PLL and set the SYSCLK source to be the divided down PLL VCO - * output frequency (STM32_PLL_FREQUENCY divided by the PLLDIV value). - */ - -#define STM32_SYSCLK_SW RCC_CFGR_SW_PLL -#define STM32_SYSCLK_SWS RCC_CFGR_SWS_PLL -#define STM32_SYSCLK_FREQUENCY (STM32_PLL_FREQUENCY/3) - -/* AHB clock (HCLK) is SYSCLK (32MHz) */ - -#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK -#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY - -/* APB2 clock (PCLK2) is HCLK (32MHz) */ - -#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK -#define STM32_PCLK2_FREQUENCY STM32_HCLK_FREQUENCY -#define STM32_APB2_CLKIN STM32_PCLK2_FREQUENCY - -/* APB1 clock (PCLK1) is HCLK (32MHz) */ - -#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK -#define STM32_PCLK1_FREQUENCY STM32_HCLK_FREQUENCY - -/* TODO: Timers */ - -/* LED definitions **********************************************************/ - -/* The Nucleo L152RE board has three LEDs. Two of these are controlled by - * logic on the board and are not available for software control: - * - * LD1 COM: LD1 default status is red. LD1 turns to green to indicate that - * communications are in progress between the PC and the - * ST-LINK/V2-1. - * LD3 PWR: red LED indicates that the board is powered. - * - * And one can be controlled by software: - * - * User LD2: green LED is a user LED connected to the I/O PA5 of the - * STM32L152RET6. - * - * If CONFIG_ARCH_LEDS is not defined, then the user can control the LED in - * any way. The following definition is used to access the LED. - */ - -/* LED index values for use with board_userled() */ - -#define BOARD_LED1 0 /* User LD2 */ -#define BOARD_NLEDS 1 - -/* LED bits for use with board_userled_all() */ - -#define BOARD_LED1_BIT (1 << BOARD_LED1) - -/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the LED on board - * the Nucleo L152RE. The following definitions describe how NuttX controls - * the LED: - * - * SYMBOL Meaning LED1 state - * ------------------ ----------------------- ---------- - * LED_STARTED NuttX has been started OFF - * LED_HEAPALLOCATE Heap has been allocated OFF - * LED_IRQSENABLED Interrupts enabled OFF - * LED_STACKCREATED Idle stack created ON - * LED_INIRQ In an interrupt No change - * LED_SIGNAL In a signal handler No change - * LED_ASSERTION An assertion failed No change - * LED_PANIC The system has crashed Blinking - * LED_IDLE STM32 is in sleep mode Not used - */ - -#define LED_STARTED 0 -#define LED_HEAPALLOCATE 0 -#define LED_IRQSENABLED 0 -#define LED_STACKCREATED 1 -#define LED_INIRQ 2 -#define LED_SIGNAL 2 -#define LED_ASSERTION 2 -#define LED_PANIC 1 - -/* Button definitions *******************************************************/ - -/* The Nucleo L152RE supports two buttons; only one button is controllable - * by software: - * - * B1 USER: user button connected to the I/O PC13 of the STM32L152RET6. - * B2 RESET: push button connected to NRST is used to RESET the - * STM32L152RET6. - */ - -#define BUTTON_USER 0 -#define NUM_BUTTONS 1 - -#define BUTTON_USER_BIT (1 << BUTTON_USER) - -/* Alternate function pin selections ****************************************/ - -/* USART */ - -/* By default the USART2 is connected to STLINK Virtual COM Port: - * USART2_RX - PA3 - * USART2_TX - PA2 - */ - -#define GPIO_USART2_RX (GPIO_USART2_RX_1|GPIO_SPEED_40MHz) /* PA3 */ -#define GPIO_USART2_TX (GPIO_USART2_TX_1|GPIO_SPEED_40MHz) /* PA2 */ - -/* SPI1 */ - -#define GPIO_SPI1_MOSI GPIO_SPI1_MOSI_2 -#define GPIO_SPI1_MISO GPIO_SPI1_MISO_2 -#define GPIO_SPI1_SCK GPIO_SPI1_SCK_1 - -/* I2C1 */ - -#define GPIO_I2C1_SCL (GPIO_I2C1_SCL_2|GPIO_SPEED_40MHz) /* PB8 CN5 pin 10, D15 */ -#define GPIO_I2C1_SDA (GPIO_I2C1_SDA_2|GPIO_SPEED_40MHz) /* PB9 CN5 pin 9, D14 */ - -#endif /* __BOARDS_ARM_STM32_NUCLEO_L152RE_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32/nucleo-l152re/scripts/Make.defs b/boards/arm/stm32/nucleo-l152re/scripts/Make.defs deleted file mode 100644 index 2eb2354673a80..0000000000000 --- a/boards/arm/stm32/nucleo-l152re/scripts/Make.defs +++ /dev/null @@ -1,41 +0,0 @@ -############################################################################ -# boards/arm/stm32/nucleo-l152re/scripts/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/.config -include $(TOPDIR)/tools/Config.mk -include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs - -LDSCRIPT = ld.script -ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) - -ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 - -CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) -CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) -CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -AFLAGS := $(CFLAGS) -D__ASSEMBLY__ - -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections -LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32/nucleo-l152re/scripts/ld.script b/boards/arm/stm32/nucleo-l152re/scripts/ld.script deleted file mode 100644 index 51325adba9348..0000000000000 --- a/boards/arm/stm32/nucleo-l152re/scripts/ld.script +++ /dev/null @@ -1,127 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-l152re/scripts/ld.script - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* The STM32L152RET6 has 512Kb of FLASH beginning at address 0x0800:0000, - * 80Kb of SRAM, and 16Kb of EEPROM. - * - * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 - * where the code expects to begin execution by jumping to the entry point in - * the 0x0800:0000 address range. - */ - -MEMORY -{ - flash (rx) : ORIGIN = 0x08000000, LENGTH = 512K - sram (rwx) : ORIGIN = 0x20000000, LENGTH = 80K -} - -OUTPUT_ARCH(arm) -EXTERN(_vectors) -ENTRY(_stext) -SECTIONS -{ - .text : { - _stext = ABSOLUTE(.); - *(.vectors) - *(.text .text.*) - *(.fixup) - *(.gnu.warning) - *(.rodata .rodata.*) - *(.gnu.linkonce.t.*) - *(.glue_7) - *(.glue_7t) - *(.got) - *(.gcc_except_table) - *(.gnu.linkonce.r.*) - _etext = ABSOLUTE(.); - } > flash - - .init_section : ALIGN(4) { - _sinit = ABSOLUTE(.); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) - KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) - _einit = ABSOLUTE(.); - } > flash - - .ARM.extab : ALIGN(4) { - *(.ARM.extab*) - } > flash - - .ARM.exidx : ALIGN(4) { - __exidx_start = ABSOLUTE(.); - *(.ARM.exidx*) - __exidx_end = ABSOLUTE(.); - } > flash - - .tdata : { - _stdata = ABSOLUTE(.); - *(.tdata .tdata.* .gnu.linkonce.td.*); - _etdata = ABSOLUTE(.); - } > flash - - .tbss : { - _stbss = ABSOLUTE(.); - *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); - _etbss = ABSOLUTE(.); - } > flash - - _eronly = ABSOLUTE(.); - - /* The RAM vector table (if present) should lie at the beginning of SRAM */ - - .ram_vectors : { - *(.ram_vectors) - } > sram - - .data : ALIGN(4) { - _sdata = ABSOLUTE(.); - *(.data .data.*) - *(.gnu.linkonce.d.*) - CONSTRUCTORS - . = ALIGN(4); - _edata = ABSOLUTE(.); - } > sram AT > flash - - .bss : ALIGN(4) { - _sbss = ABSOLUTE(.); - *(.bss .bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - . = ALIGN(4); - _ebss = ABSOLUTE(.); - } > sram - - /* Stabs debugging sections. */ - - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_info 0 : { *(.debug_info) } - .debug_line 0 : { *(.debug_line) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_aranges 0 : { *(.debug_aranges) } -} diff --git a/boards/arm/stm32/nucleo-l152re/src/CMakeLists.txt b/boards/arm/stm32/nucleo-l152re/src/CMakeLists.txt deleted file mode 100644 index c8bbc27e2fe41..0000000000000 --- a/boards/arm/stm32/nucleo-l152re/src/CMakeLists.txt +++ /dev/null @@ -1,49 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/nucleo-l152re/src/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -set(SRCS stm32_boot.c) - -if(CONFIG_ARCH_LEDS) - list(APPEND SRCS stm32_autoleds.c) -else() - list(APPEND SRCS stm32_userleds.c) -endif() - -if(CONFIG_ARCH_BUTTONS) - list(APPEND SRCS stm32_buttons.c) -endif() - -if(CONFIG_LCD_ILI9341) - list(APPEND SRCS stm32_ili93418b.c) -endif() - -if(CONFIG_MMCSD_SPI) - list(APPEND SRCS stm32_spisd.c) -endif() - -if(CONFIG_STM32_SPI) - list(APPEND SRCS stm32_spi.c) -endif() - -target_sources(board PRIVATE ${SRCS}) - -set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/ld.script") diff --git a/boards/arm/stm32/nucleo-l152re/src/Make.defs b/boards/arm/stm32/nucleo-l152re/src/Make.defs deleted file mode 100644 index 3eafd51d2e9c2..0000000000000 --- a/boards/arm/stm32/nucleo-l152re/src/Make.defs +++ /dev/null @@ -1,51 +0,0 @@ -############################################################################ -# boards/arm/stm32/nucleo-l152re/src/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/Make.defs - -CSRCS = stm32_boot.c - -ifeq ($(CONFIG_ARCH_LEDS),y) -CSRCS += stm32_autoleds.c -else -CSRCS += stm32_userleds.c -endif - -ifeq ($(CONFIG_ARCH_BUTTONS),y) -CSRCS += stm32_buttons.c -endif - -ifeq ($(CONFIG_LCD_ILI9341),y) -CSRCS += stm32_ili93418b.c -endif - -ifeq ($(CONFIG_MMCSD_SPI),y) -CSRCS += stm32_spisd.c -endif - -ifeq ($(CONFIG_STM32_SPI),y) -CSRCS += stm32_spi.c -endif - -DEPPATH += --dep-path board -VPATH += :board -CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/nucleo-l152re/src/stm32_autoleds.c b/boards/arm/stm32/nucleo-l152re/src/stm32_autoleds.c deleted file mode 100644 index 69c14c5f96f34..0000000000000 --- a/boards/arm/stm32/nucleo-l152re/src/stm32_autoleds.c +++ /dev/null @@ -1,80 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-l152re/src/stm32_autoleds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include "stm32.h" -#include "nucleo-l152re.h" - -#ifdef CONFIG_ARCH_LEDS - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_autoled_initialize - ****************************************************************************/ - -void board_autoled_initialize(void) -{ - /* Configure LED1 GPIO for output */ - - stm32_configgpio(GPIO_LED1); -} - -/**************************************************************************** - * Name: board_autoled_on - ****************************************************************************/ - -void board_autoled_on(int led) -{ - if (led == BOARD_LED1) - { - stm32_gpiowrite(GPIO_LED1, true); - } -} - -/**************************************************************************** - * Name: board_autoled_off - ****************************************************************************/ - -void board_autoled_off(int led) -{ - if (led == BOARD_LED1) - { - stm32_gpiowrite(GPIO_LED1, false); - } -} - -#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/nucleo-l152re/src/stm32_boot.c b/boards/arm/stm32/nucleo-l152re/src/stm32_boot.c deleted file mode 100644 index f9b3cd5843394..0000000000000 --- a/boards/arm/stm32/nucleo-l152re/src/stm32_boot.c +++ /dev/null @@ -1,197 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-l152re/src/stm32_boot.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include -#include -#include - -#include "stm32_i2c.h" - -#include "nucleo-l152re.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#undef HAVE_LEDS -#undef HAVE_DAC - -#if !defined(CONFIG_ARCH_LEDS) && defined(CONFIG_USERLED_LOWER) -# define HAVE_LEDS 1 -#endif - -#if defined(CONFIG_DAC) -# define HAVE_DAC 1 -#endif - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_boardinitialize - * - * Description: - * All STM32 architectures must provide the following entry point. This - * entry point is called early in the initialization -- after all memory - * has been configured and mapped but before any devices have been - * initialized. - * - ****************************************************************************/ - -void stm32_boardinitialize(void) -{ - /* Configure on-board LEDs if LED support has been selected. */ - -#ifdef CONFIG_ARCH_LEDS - board_autoled_initialize(); -#endif -} - -/**************************************************************************** - * Name: board_late_initialize - * - * Description: - * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional - * initialization call will be performed in the boot-up sequence to a - * function called board_late_initialize(). board_late_initialize() will be - * called immediately after up_initialize() is called and just before the - * initial application is started. This additional initialization phase - * may be used, for example, to initialize board-specific device drivers. - * - ****************************************************************************/ - -#ifdef CONFIG_BOARD_LATE_INITIALIZE -void board_late_initialize(void) -{ - int ret; -#ifdef CONFIG_STM32_I2C1 - struct i2c_master_s *i2c1; -#endif -#ifdef CONFIG_STM32_I2C2 - struct i2c_master_s *i2c2; -#endif - -#ifdef CONFIG_STM32_I2C1 - /* Get the I2C lower half instance */ - - i2c1 = stm32_i2cbus_initialize(1); - if (i2c1 == NULL) - { - i2cerr("ERROR: Initialize I2C1: %d\n", ret); - } - else - { - /* Register the I2C character driver */ - - ret = i2c_register(i2c1, 1); - if (ret < 0) - { - i2cerr("ERROR: Failed to register I2C1 device: %d\n", ret); - } - } -#endif - -#ifdef CONFIG_STM32_I2C2 - /* Get the I2C lower half instance */ - - i2c2 = stm32_i2cbus_initialize(2); - if (i2c2 == NULL) - { - i2cerr("ERROR: Initialize I2C2: %d\n", ret); - } - else - { - /* Register the I2C character driver */ - - ret = i2c_register(i2c2, 2); - if (ret < 0) - { - i2cerr("ERROR: Failed to register I2C2 device: %d\n", ret); - } - } -#endif - -#ifdef CONFIG_STM32_SPI - stm32_spiinitialize(); -#endif - -#ifdef HAVE_LEDS - /* Register the LED driver */ - - ret = userled_lower_initialize(LED_DRIVER_PATH); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: userled_lower_initialize() failed: %d\n", ret); - return; - } -#endif - -#ifdef CONFIG_FS_PROCFS - /* Mount the procfs file system */ - - ret = nx_mount(0, STM32_PROCFS_MOUNTPOINT, "procfs", 0, 0); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: Failed to mount procfs at %s: %d\n", - STM32_PROCFS_MOUNTPOINT, ret); - } -#endif - -#ifdef CONFIG_MMCSD_SPI - - /* Initialize the MMC/SD SPI driver (SPI1 is used) */ - - ret = stm32_spisd_initialize(1, CONFIG_NSH_MMCSDMINOR); - if (ret < 0) - { - syslog(LOG_ERR, "Failed to initialize SD slot %d: %d\n", - CONFIG_NSH_MMCSDMINOR, ret); - } -#endif - - UNUSED(ret); -} -#endif diff --git a/boards/arm/stm32/nucleo-l152re/src/stm32_buttons.c b/boards/arm/stm32/nucleo-l152re/src/stm32_buttons.c deleted file mode 100644 index 47366db118cd9..0000000000000 --- a/boards/arm/stm32/nucleo-l152re/src/stm32_buttons.c +++ /dev/null @@ -1,113 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-l152re/src/stm32_buttons.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include "stm32.h" -#include "nucleo-l152re.h" - -#ifdef CONFIG_ARCH_BUTTONS - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_button_initialize - * - * Description: - * board_button_initialize() must be called to initialize button - * resources. After that, board_buttons() may be called to collect the - * current state of all buttons or board_button_irq() may be called to - * register button interrupt handlers. - * - ****************************************************************************/ - -uint32_t board_button_initialize(void) -{ - /* Configure the single button as an input. NOTE that EXTI interrupts are - * also configured for the pin. - */ - - stm32_configgpio(GPIO_BTN_USER); - return NUM_BUTTONS; -} - -/**************************************************************************** - * Name: board_buttons - * - * Description: - * After board_button_initialize() has been called, board_buttons() may be - * called to collect the state of all buttons. board_buttons() returns an - * 32-bit unsigned integer with each bit associated with a button. See the - * BUTTON_*_BIT definitions in board.h for the meaning of each bit. - * - ****************************************************************************/ - -uint32_t board_buttons(void) -{ - /* Check the state of the USER button. A LOW value means that the key is - * pressed. - */ - - return stm32_gpioread(GPIO_BTN_USER) ? 0 : BUTTON_USER_BIT; -} - -/**************************************************************************** - * Name: board_button_irq - * - * Description: - * board_button_irq() may be called to register an interrupt handler that - * will be called when a button is depressed or released. The ID value is - * a button enumeration value that uniquely identifies a button resource. - * See the BUTTON_* definitions in board.h for the meaning of the - * enumeration value. - * - ****************************************************************************/ - -#ifdef CONFIG_ARCH_IRQBUTTONS -int board_button_irq(int id, xcpt_t irqhandler, void *arg) -{ - int ret = -EINVAL; - - if (id == BUTTON_USER) - { - ret = stm32_gpiosetevent(GPIO_BTN_USER, true, true, true, irqhandler, - arg); - } - - return ret; -} -#endif - -#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/stm32/nucleo-l152re/src/stm32_spi.c b/boards/arm/stm32/nucleo-l152re/src/stm32_spi.c deleted file mode 100644 index 5d59d781d635f..0000000000000 --- a/boards/arm/stm32/nucleo-l152re/src/stm32_spi.c +++ /dev/null @@ -1,268 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-l152re/src/stm32_spi.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include -#include - -#include "arm_internal.h" -#include "chip.h" -#include "stm32_gpio.h" -#include "stm32_spi.h" - -#include "nucleo-l152re.h" - -#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || defined(CONFIG_STM32_SPI3) - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/* Global driver instances */ - -#ifdef CONFIG_STM32_SPI1 - struct spi_dev_s *g_spi1; -#endif -#ifdef CONFIG_STM32_SPI2 - struct spi_dev_s *g_spi2; -#endif -#ifdef CONFIG_STM32_SPI3 - struct spi_dev_s *g_spi3; -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_spiinitialize - * - * Description: - * Called to configure SPI chip select GPIO pins. - * - ****************************************************************************/ - -void weak_function stm32_spiinitialize(void) -{ - int ret; -#ifdef CONFIG_STM32_SPI1 - /* Initialize the SPI1 bus */ - - g_spi1 = stm32_spibus_initialize(1); - if (g_spi1 == NULL) - { - spierr("ERROR: Initialize SPI1: \n"); - } - -#ifdef CONFIG_SPI_DRIVER - /* Register the SPI1 character driver */ - - ret = spi_register(g_spi1, 1); - if (ret < 0) - { - spierr("ERROR: Failed to register SPI1 device: %d\n", ret); - } -#endif -#endif - -#ifdef CONFIG_STM32_SPI2 - /* Initialize the SPI2 bus */ - - g_spi2 = stm32_spibus_initialize(2); - if (g_spi2 == NULL) - { - spierr("ERROR: Initialize SPI2: \n"); - } - -#ifdef CONFIG_SPI_DRIVER - /* Register the SPI2 character driver */ - - ret = spi_register(g_spi2, 2); - if (ret < 0) - { - spierr("ERROR: Failed to register SPI2 device: %d\n", ret); - } -#endif -#endif - -#ifdef CONFIG_STM32_SPI3 - /* Initialize the SPI3 bus */ - - g_spi3 = stm32_spibus_initialize(3); - if (g_spi3 == NULL) - { - spierr("ERROR: Initialize SPI3: \n"); - } - -#ifdef CONFIG_SPI_DRIVER - /* Register the SPI3 character driver */ - - ret = spi_register(g_spi3, 3); - if (ret < 0) - { - spierr("ERROR: Failed to register SPI3 device: %d\n", ret); - } -#endif -#endif -} - -/**************************************************************************** - * Name: stm32_spi1/2/3select and stm32_spi1/2/3status - * - * Description: - * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status - * must be provided by board-specific logic. They are implementations of - * the select and status methods of the SPI interface defined by struct - * spi_ops_s (see include/nuttx/spi/spi.h). All other methods (including - * stm32_spibus_initialize()) are provided by common STM32 logic. To use - * this common SPI logic on your board: - * - * 1. Provide logic in stm32_boardinitialize() to configure SPI chip select - * pins. - * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() functions - * in your board-specific logic. These functions will perform chip - * selection and status operations using GPIOs in the way your board - * is configured. - * 3. Add a calls to stm32_spibus_initialize() in your low level - * application initialization logic - * 4. The handle returned by stm32_spibus_initialize() may then be used to - * bind the SPI driver to higher level logic (e.g., calling - * mmcsd_spislotinitialize(), for example, will bind the SPI driver to - * the SPI MMC/SD driver). - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_SPI1 -void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, - bool selected) -{ - spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : - "de-assert"); - -#if defined(CONFIG_MMCSD_SPI) - if (devid == SPIDEV_MMCSD(0)) - { - stm32_gpiowrite(GPIO_SPI1_CS, !selected); - } -#endif -} - -uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) -{ - uint8_t status = 0; -#if defined(CONFIG_MMCSD_SPI) - if (devid == SPIDEV_MMCSD(0)) - { - status |= SPI_STATUS_PRESENT; - } -#endif - - return status; -} -#endif - -#ifdef CONFIG_STM32_SPI2 -void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid, - bool selected) -{ - spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : - "de-assert"); -} - -uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) -{ - return 0; -} -#endif - -#ifdef CONFIG_STM32_SPI3 -void stm32_spi3select(struct spi_dev_s *dev, uint32_t devid, - bool selected) -{ - spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : - "de-assert"); -} - -uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid) -{ - return 0; -} - -#endif - -/**************************************************************************** - * Name: stm32_spi1cmddata - * - * Description: - * Set or clear the SH1101A A0 or SD1306 D/C n bit to select data (true) - * or command (false). This function must be provided by platform-specific - * logic. This is an implementation of the cmddata method of the SPI - * interface defined by struct spi_ops_s (see include/nuttx/spi/spi.h). - * - * Input Parameters: - * - * spi - SPI device that controls the bus the device that requires the CMD/ - * DATA selection. - * devid - If there are multiple devices on the bus, this selects which one - * to select cmd or data. NOTE: This design restricts, for example, - * one one SPI display per SPI bus. - * cmd - true: select command; false: select data - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef CONFIG_SPI_CMDDATA -#ifdef CONFIG_STM32_SPI1 -int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) -{ - return -ENODEV; -} -#endif - -#ifdef CONFIG_STM32_SPI2 -int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) -{ - return -ENODEV; -} -#endif - -#ifdef CONFIG_STM32_SPI3 -int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) -{ - return -ENODEV; -} -#endif -#endif /* CONFIG_SPI_CMDDATA */ - -#endif /* CONFIG_STM32_SPI1 || CONFIG_STM32_SPI2 || CONFIG_STM32_SPI3 */ diff --git a/boards/arm/stm32/nucleo-l152re/src/stm32_userleds.c b/boards/arm/stm32/nucleo-l152re/src/stm32_userleds.c deleted file mode 100644 index 4ed85198d21e5..0000000000000 --- a/boards/arm/stm32/nucleo-l152re/src/stm32_userleds.c +++ /dev/null @@ -1,77 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-l152re/src/stm32_userleds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include - -#include "stm32.h" -#include "nucleo-l152re.h" - -#ifndef CONFIG_ARCH_LEDS - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_userled_initialize - ****************************************************************************/ - -uint32_t board_userled_initialize(void) -{ - /* Configure LED1 GPIO for output */ - - stm32_configgpio(GPIO_LED1); - return BOARD_NLEDS; -} - -/**************************************************************************** - * Name: board_userled - ****************************************************************************/ - -void board_userled(int led, bool ledon) -{ - if (led == BOARD_LED1) - { - stm32_gpiowrite(GPIO_LED1, ledon); - } -} - -/**************************************************************************** - * Name: board_userled_all - ****************************************************************************/ - -void board_userled_all(uint32_t ledset) -{ - stm32_gpiowrite(GPIO_LED1, (ledset & BOARD_LED1_BIT) != 0); -} - -#endif /* !CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/odrive36/CMakeLists.txt b/boards/arm/stm32/odrive36/CMakeLists.txt deleted file mode 100644 index 430752bb2ce04..0000000000000 --- a/boards/arm/stm32/odrive36/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/odrive36/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32/odrive36/configs/nsh/defconfig b/boards/arm/stm32/odrive36/configs/nsh/defconfig deleted file mode 100644 index 2f27a769673b4..0000000000000 --- a/boards/arm/stm32/odrive36/configs/nsh/defconfig +++ /dev/null @@ -1,42 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="odrive36" -CONFIG_ARCH_BOARD_ODRIVE36=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F405RG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=15272 -CONFIG_BUILTIN=y -CONFIG_EXAMPLES_HELLO=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_MM_REGIONS=2 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=6 -CONFIG_START_MONTH=12 -CONFIG_START_YEAR=2011 -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_USART2=y -CONFIG_SYSTEM_NSH=y -CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/odrive36/configs/usbnsh/defconfig b/boards/arm/stm32/odrive36/configs/usbnsh/defconfig deleted file mode 100644 index c0b74daa75366..0000000000000 --- a/boards/arm/stm32/odrive36/configs/usbnsh/defconfig +++ /dev/null @@ -1,54 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_DEV_CONSOLE is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="odrive36" -CONFIG_ARCH_BOARD_ODRIVE36=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F405RG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARDCTL_USBDEVCTRL=y -CONFIG_BOARD_LOOPSPERMSEC=15272 -CONFIG_BUILTIN=y -CONFIG_CDCACM=y -CONFIG_CDCACM_CONSOLE=y -CONFIG_CDCACM_RXBUFSIZE=256 -CONFIG_CDCACM_TXBUFSIZE=256 -CONFIG_DEBUG_FULLOPT=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_EXAMPLES_HELLO=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_IDLETHREAD_STACKSIZE=2048 -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_MM_REGIONS=2 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAMLOG=y -CONFIG_RAMLOG_BUFSIZE=4096 -CONFIG_RAMLOG_SYSLOG=y -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_STACK_COLORATION=y -CONFIG_START_DAY=27 -CONFIG_START_YEAR=2013 -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_OTGFS=y -CONFIG_STM32_PWR=y -CONFIG_STM32_USART2=y -CONFIG_SYSTEM_NSH=y -CONFIG_USBDEV=y diff --git a/boards/arm/stm32/odrive36/include/board.h b/boards/arm/stm32/odrive36/include/board.h deleted file mode 100644 index 87d431fa5c4d7..0000000000000 --- a/boards/arm/stm32/odrive36/include/board.h +++ /dev/null @@ -1,212 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/odrive36/include/board.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __BOARDS_ARM_STM32_ODRIVE36_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32_ODRIVE36_INCLUDE_BOARD_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#ifndef __ASSEMBLY__ -# include -#endif -#include "stm32_rcc.h" -#include "stm32.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Clocking *****************************************************************/ - -/* HSI - 16 MHz RC factory-trimmed - * LSI - 32 KHz RC (30-60KHz, uncalibrated) - * HSE - On-board crystal frequency is 8MHz - * LSE - 32.768 kHz - */ - -#define STM32_BOARD_XTAL 8000000ul - -#define STM32_HSI_FREQUENCY 16000000ul -#define STM32_LSI_FREQUENCY 32000 -#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL -#define STM32_LSE_FREQUENCY 32768 - -/* Main PLL Configuration. - * - * PLL source is HSE - * PLL_VCO = (STM32_HSE_FREQUENCY / PLLM) * PLLN - * = (8,000,000 / 8) * 336 - * = 336,000,000 - * SYSCLK = PLL_VCO / PLLP - * = 336,000,000 / 2 = 168,000,000 - * USB OTG FS, SDIO and RNG Clock - * = PLL_VCO / PLLQ - * = 48,000,000 - */ - -#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(8) -#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(336) -#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_2 -#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(7) - -#define STM32_SYSCLK_FREQUENCY 168000000ul - -/* AHB clock (HCLK) is SYSCLK (168MHz) */ - -#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ -#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY - -/* APB1 clock (PCLK1) is HCLK/4 (42MHz) */ - -#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd4 /* PCLK1 = HCLK / 4 */ -#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/4) - -/* Timers driven from APB1 will be twice PCLK1 */ - -#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) - -/* APB2 clock (PCLK2) is HCLK/2 (84MHz) */ - -#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLKd2 /* PCLK2 = HCLK / 2 */ -#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/2) - -/* Timers driven from APB2 will be twice PCLK2 */ - -#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM9_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM10_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM11_CLKIN (2*STM32_PCLK2_FREQUENCY) - -/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx - * otherwise frequency is 2xAPBx. - * Note: TIM1,8 are on APB2, others on APB1 - */ - -#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM2_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM3_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM4_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM5_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM6_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM7_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY - -/* DMA Channel/Stream Selections ********************************************/ - -/* ADC 1 */ - -#define ADC1_DMA_CHAN DMAMAP_ADC1_1 - -/* Alternate function pin selections ****************************************/ - -/* ADC */ - -#define GPIO_ADC1_IN4 GPIO_ADC1_IN4_0 -#define GPIO_ADC1_IN5 GPIO_ADC1_IN5_0 -#define GPIO_ADC1_IN6 GPIO_ADC1_IN6_0 -#define GPIO_ADC1_IN15 GPIO_ADC1_IN15_0 - -#define GPIO_ADC2_IN10 GPIO_ADC2_IN10_0 -#define GPIO_ADC2_IN11 GPIO_ADC2_IN11_0 -#define GPIO_ADC2_IN12 GPIO_ADC2_IN13_0 - -#define GPIO_ADC3_IN12 GPIO_ADC3_IN12_0 -#define GPIO_ADC3_IN13 GPIO_ADC3_IN13_0 - -/* USART2: - * USART2_TX - PA2 - GPIO_3 - * USART2_RX - PA3 - GPIO_4 - */ - -#define GPIO_USART2_RX (GPIO_USART2_RX_1|GPIO_SPEED_100MHz) -#define GPIO_USART2_TX (GPIO_USART2_TX_1|GPIO_SPEED_100MHz) - -/* CAN: - * CAN_R - PB8 - * CAN_T - PB9 - */ - -#define GPIO_CAN1_RX (GPIO_CAN1_RX_2|GPIO_SPEED_50MHz) -#define GPIO_CAN1_TX (GPIO_CAN1_TX_2|GPIO_SPEED_50MHz) - -/* SPI3 - connected to DRV8301 - * SPI3_SCK - PC10 - * SPI3_MISO - PC11 - * SPI3_MOSI - PC12 - */ - -#define GPIO_SPI3_SCK (GPIO_SPI3_SCK_2|GPIO_SPEED_50MHz) -#define GPIO_SPI3_MISO (GPIO_SPI3_MISO_2|GPIO_SPEED_50MHz) -#define GPIO_SPI3_MOSI (GPIO_SPI3_MOSI_2|GPIO_SPEED_50MHz) - -/* USBDEV */ - -#define GPIO_OTGFS_DM (GPIO_OTGFS_DM_0|GPIO_SPEED_100MHz) -#define GPIO_OTGFS_DP (GPIO_OTGFS_DP_0|GPIO_SPEED_100MHz) -#define GPIO_OTGFS_ID (GPIO_OTGFS_ID_0|GPIO_SPEED_100MHz) - -/* Dual FOC configuration */ - -/* TIM1 configuration *******************************************************/ - -#define GPIO_TIM1_CH1OUT (GPIO_TIM1_CH1OUT_1|GPIO_SPEED_100MHz) /* TIM1 CH1 - PA8 - U high */ -#define GPIO_TIM1_CH1NOUT (GPIO_TIM1_CH1N_2|GPIO_SPEED_100MHz) /* TIM1 CH1N - PB13 - U low */ -#define GPIO_TIM1_CH2OUT (GPIO_TIM1_CH2OUT_1|GPIO_SPEED_100MHz) /* TIM1 CH2 - PA9 - V high */ -#define GPIO_TIM1_CH2NOUT (GPIO_TIM1_CH2N_2|GPIO_SPEED_100MHz) /* TIM1 CH2N - PB14 - V low */ -#define GPIO_TIM1_CH3OUT (GPIO_TIM1_CH3OUT_1|GPIO_SPEED_100MHz) /* TIM1 CH3 - PA10 - W high */ -#define GPIO_TIM1_CH3NOUT (GPIO_TIM1_CH3N_2|GPIO_SPEED_100MHz) /* TIM1 CH3N - PB15 - W low */ -#define GPIO_TIM1_CH4OUT 0 /* not used as output */ - -/* TIM8 configuration *******************************************************/ - -#define GPIO_TIM8_CH1OUT (GPIO_TIM8_CH1OUT_1|GPIO_SPEED_100MHz) /* TIM8 CH1 - PC6 - U high */ -#define GPIO_TIM8_CH1NOUT (GPIO_TIM8_CH1N_2|GPIO_SPEED_100MHz) /* TIM8 CH1N - PA7 - U low */ -#define GPIO_TIM8_CH2OUT (GPIO_TIM8_CH2OUT_1|GPIO_SPEED_100MHz) /* TIM8 CH2 - PC7 - V high */ -#define GPIO_TIM8_CH2NOUT (GPIO_TIM8_CH2N_1|GPIO_SPEED_100MHz) /* TIM8 CH2N - PB0 - V low */ -#define GPIO_TIM8_CH3OUT (GPIO_TIM8_CH3OUT_1|GPIO_SPEED_100MHz) /* TIM8 CH3 - PC8 - W high */ -#define GPIO_TIM8_CH3NOUT (GPIO_TIM8_CH3N_1|GPIO_SPEED_100MHz) /* TIM8 CH3N - PB1 - W low */ -#define GPIO_TIM8_CH4OUT 0 /* not used as output */ - -/* QEN3 configuration *******************************************************/ - -#define GPIO_TIM3_CH1IN (GPIO_TIM3_CH1IN_2|GPIO_SPEED_50MHz) /* TIM3 CH1IN - PB4 */ -#define GPIO_TIM3_CH2IN (GPIO_TIM3_CH2IN_2|GPIO_SPEED_50MHz) /* TIM3 CH2IN - PB5 */ - -/* QEN4 configuration *******************************************************/ - -#define GPIO_TIM4_CH1IN (GPIO_TIM4_CH1IN_1|GPIO_SPEED_50MHz) /* TIM4 CH1IN - PB6 */ -#define GPIO_TIM4_CH2IN (GPIO_TIM4_CH2IN_1|GPIO_SPEED_50MHz) /* TIM4 CH2IN - PB7 */ - -#endif /* __BOARDS_ARM_STM32_ODRIVE36_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32/odrive36/scripts/Make.defs b/boards/arm/stm32/odrive36/scripts/Make.defs deleted file mode 100644 index fc9a05f91d22d..0000000000000 --- a/boards/arm/stm32/odrive36/scripts/Make.defs +++ /dev/null @@ -1,42 +0,0 @@ -############################################################################ -# boards/arm/stm32/odrive36/scripts/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/.config -include $(TOPDIR)/tools/Config.mk -include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs - -LDSCRIPT = ld.script - -ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) - -ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 - -CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) -CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) -CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -AFLAGS := $(CFLAGS) -D__ASSEMBLY__ - -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections -LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32/odrive36/scripts/ld.script b/boards/arm/stm32/odrive36/scripts/ld.script deleted file mode 100644 index 7e28d6544342d..0000000000000 --- a/boards/arm/stm32/odrive36/scripts/ld.script +++ /dev/null @@ -1,125 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/odrive36/scripts/ld.script - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* The STM32F405RGT6 has 1024Kb of FLASH beginning at address 0x0800:0000 and - * 192Kb of SRAM. SRAM is split up into two blocks: - * - * 1) 112Kb of SRAM beginning at address 0x2000:0000 - * 2) 16Kb of SRAM beginning at address 0x2001:c000 - * 3) 64Kb of SRAM beginning at address 0x2002:0000 - * - * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 - * where the code expects to begin execution by jumping to the entry point in - * the 0x0800:0000 address - * range. - */ - -MEMORY -{ - flash (rx) : ORIGIN = 0x08000000, LENGTH = 1024K - sram (rwx) : ORIGIN = 0x20000000, LENGTH = 112K -} - -OUTPUT_ARCH(arm) -EXTERN(_vectors) -ENTRY(_stext) -SECTIONS -{ - .text : { - _stext = ABSOLUTE(.); - *(.vectors) - *(.text .text.*) - *(.fixup) - *(.gnu.warning) - *(.rodata .rodata.*) - *(.gnu.linkonce.t.*) - *(.glue_7) - *(.glue_7t) - *(.got) - *(.gcc_except_table) - *(.gnu.linkonce.r.*) - _etext = ABSOLUTE(.); - } > flash - - .init_section : ALIGN(4) { - _sinit = ABSOLUTE(.); - KEEP(*(.init_array .init_array.*)) - _einit = ABSOLUTE(.); - } > flash - - .ARM.extab : ALIGN(4) { - *(.ARM.extab*) - } > flash - - .ARM.exidx : ALIGN(4) { - __exidx_start = ABSOLUTE(.); - *(.ARM.exidx*) - __exidx_end = ABSOLUTE(.); - } > flash - - .tdata : { - _stdata = ABSOLUTE(.); - *(.tdata .tdata.* .gnu.linkonce.td.*); - _etdata = ABSOLUTE(.); - } > flash - - .tbss : { - _stbss = ABSOLUTE(.); - *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); - _etbss = ABSOLUTE(.); - } > flash - - _eronly = ABSOLUTE(.); - - .data : ALIGN(4) { - _sdata = ABSOLUTE(.); - *(.data .data.*) - *(.gnu.linkonce.d.*) - CONSTRUCTORS - . = ALIGN(4); - _edata = ABSOLUTE(.); - } > sram AT > flash - - .bss : ALIGN(4) { - _sbss = ABSOLUTE(.); - *(.bss .bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - . = ALIGN(4); - _ebss = ABSOLUTE(.); - } > sram - - /* Stabs debugging sections. */ - - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_info 0 : { *(.debug_info) } - .debug_line 0 : { *(.debug_line) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_aranges 0 : { *(.debug_aranges) } -} diff --git a/boards/arm/stm32/odrive36/src/CMakeLists.txt b/boards/arm/stm32/odrive36/src/CMakeLists.txt deleted file mode 100644 index fb8dbb343df0c..0000000000000 --- a/boards/arm/stm32/odrive36/src/CMakeLists.txt +++ /dev/null @@ -1,39 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/odrive36/src/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -set(SRCS stm32_boot.c stm32_bringup.c) - -if(CONFIG_STM32_SPI) - list(APPEND SRCS stm32_spi.c) -endif() - -if(CONFIG_STM32_FOC) - list(APPEND SRCS stm32_foc.c) -endif() - -if(CONFIG_STM32_OTGFS) - list(APPEND SRCS stm32_usb.c) -endif() - -target_sources(board PRIVATE ${SRCS}) - -set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/ld.script") diff --git a/boards/arm/stm32/odrive36/src/Make.defs b/boards/arm/stm32/odrive36/src/Make.defs deleted file mode 100644 index 4074cab81c508..0000000000000 --- a/boards/arm/stm32/odrive36/src/Make.defs +++ /dev/null @@ -1,41 +0,0 @@ -############################################################################ -# boards/arm/stm32/odrive36/src/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/Make.defs - -CSRCS = stm32_boot.c stm32_bringup.c - -ifeq ($(CONFIG_STM32_SPI),y) -CSRCS += stm32_spi.c -endif - -ifeq ($(CONFIG_STM32_FOC),y) -CSRCS += stm32_foc.c -endif - -ifeq ($(CONFIG_STM32_OTGFS),y) -CSRCS += stm32_usb.c -endif - -DEPPATH += --dep-path board -VPATH += :board -CFLAGS += $(shell $(INCDIR) "$(CC)" $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board) diff --git a/boards/arm/stm32/odrive36/src/stm32_boot.c b/boards/arm/stm32/odrive36/src/stm32_boot.c deleted file mode 100644 index bb3bb54f71f1b..0000000000000 --- a/boards/arm/stm32/odrive36/src/stm32_boot.c +++ /dev/null @@ -1,107 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/odrive36/src/stm32_boot.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include -#include -#include - -#include - -#include "arm_internal.h" -#include "odrive.h" - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_boardinitialize - * - * Description: - * All STM32 architectures must provide the following entry point. This - * entry point is called early in the initialization -- after all memory - * has been configured and mapped but before any devices have been - * initialized. - * - ****************************************************************************/ - -void stm32_boardinitialize(void) -{ -#ifdef CONFIG_SEGGER_SYSVIEW - up_perf_init((void *)STM32_SYSCLK_FREQUENCY); -#endif - -#ifdef CONFIG_ARCH_LEDS - /* Configure on-board LEDs if LED support has been selected. */ - - board_autoled_initialize(); -#endif - -#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || \ - defined(CONFIG_STM32_SPI3) - /* Configure SPI chip selects if 1) SP2 is not disabled, and 2) the weak - * function stm32_spidev_initialize() has been brought into the link. - */ - - stm32_spidev_initialize(); -#endif - -#ifdef CONFIG_STM32_OTGFS - /* Initialize USB is 1) USBDEV is selected, 2) the USB controller is not - * disabled, and 3) the weak function stm32_usbinitialize() has been - * brought into the build. - */ - - stm32_usbinitialize(); -#endif -} - -/**************************************************************************** - * Name: board_late_initialize - * - * Description: - * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional - * initialization call will be performed in the boot-up sequence to a - * function called board_late_initialize(). board_late_initialize() will - * be called immediately after up_initialize() is called and just before - * the initial application is started. This additional initialization - * phase may be used, for example, to initialize board-specific device - * drivers. - * - ****************************************************************************/ - -#ifdef CONFIG_BOARD_LATE_INITIALIZE -void board_late_initialize(void) -{ - /* Perform board-specific initialization */ - - stm32_bringup(); -} -#endif diff --git a/boards/arm/stm32/odrive36/src/stm32_bringup.c b/boards/arm/stm32/odrive36/src/stm32_bringup.c deleted file mode 100644 index ab2bb6f29b8df..0000000000000 --- a/boards/arm/stm32/odrive36/src/stm32_bringup.c +++ /dev/null @@ -1,140 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/odrive36/src/stm32_bringup.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include - -#include -#include - -#ifdef CONFIG_SENSORS_QENCODER -# include "board_qencoder.h" -# include "stm32_qencoder.h" -#endif - -#include "odrive.h" - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_bringup - * - * Description: - * Perform architecture-specific initialization - * - * CONFIG_BOARD_LATE_INITIALIZE=y : - * Called from board_late_initialize(). - * - ****************************************************************************/ - -int stm32_bringup(void) -{ - int ret = OK; - -#ifdef CONFIG_FS_PROCFS - /* Mount the procfs file system */ - - ret = nx_mount(NULL, STM32_PROCFS_MOUNTPOINT, "procfs", 0, NULL); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: Failed to mount the PROC filesystem: %d\n", - ret); - } -#endif /* CONFIG_FS_PROCFS */ - -#if defined(CONFIG_CDCACM) && !defined(CONFIG_CDCACM_CONSOLE) - /* Initialize CDCACM */ - - ret = cdcacm_initialize(0, NULL); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: cdcacm_initialize failed: %d\n", ret); - } -#endif /* CONFIG_CDCACM & !CONFIG_CDCACM_CONSOLE */ - -#if defined(CONFIG_STM32_TIM3_QE) && defined(CONFIG_SENSORS_QENCODER) - /* Initialize and register the qencoder driver - TIM3 */ - - ret = board_qencoder_initialize(0, 3); - if (ret != OK) - { - syslog(LOG_ERR, "ERROR: Failed to register the qencoder: %d\n", ret); - } - - /* Connect QE index pin */ - - ret = stm32_qe_index_init(3, GPIO_QE3_INDEX); - if (ret != OK) - { - syslog(LOG_ERR, "ERROR: Failed to register qe index pin: %d\n", ret); - } -#endif - -#if defined(CONFIG_STM32_TIM4_QE) && defined(CONFIG_SENSORS_QENCODER) - /* Initialize and register the qencoder driver - TIM4 */ - - ret = board_qencoder_initialize(1, 4); - if (ret != OK) - { - syslog(LOG_ERR, "ERROR: Failed to register the qencoder: %d\n", ret); - } - - /* Connect QE index pin */ - - ret = stm32_qe_index_init(4, GPIO_QE4_INDEX); - if (ret != OK) - { - syslog(LOG_ERR, "ERROR: Failed to register qe index pin: %d\n", ret); - } -#endif - -#ifdef CONFIG_ADC - /* Initialize ADC and register the ADC driver. */ - - ret = stm32_adc_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_adc_setup failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_STM32_FOC - /* Initialize and register FOC devices */ - - ret = stm32_foc_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_foc_setup failed: %d\n", ret); - } -#endif - - return ret; -} diff --git a/boards/arm/stm32/odrive36/src/stm32_foc.c b/boards/arm/stm32/odrive36/src/stm32_foc.c deleted file mode 100644 index 7107a31b61a55..0000000000000 --- a/boards/arm/stm32/odrive36/src/stm32_foc.c +++ /dev/null @@ -1,962 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/odrive36/src/stm32_foc.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include - -#include -#include -#include - -#include -#include - -#include "stm32_foc.h" -#include "stm32_gpio.h" -#ifdef CONFIG_ADC -# include "stm32_adc.h" -#endif - -#include "odrive.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#ifndef CONFIG_ODRIVE_HW_VOLTAGE_56 -# error Tested only for ODrive 56V version -#endif - -/* Supported FOC instances */ - -#ifdef CONFIG_ODRIVE_FOC_FOC0 -# define ODRIVE_FOC_FOC0 1 -#else -# define ODRIVE_FOC_FOC0 0 -#endif - -#ifdef CONFIG_ODRIVE_FOC_FOC1 -# define ODRIVE_FOC_FOC1 1 -#else -# define ODRIVE_FOC_FOC1 0 -#endif - -#define ODRIVE_FOC_INST (ODRIVE_FOC_FOC0 + ODRIVE_FOC_FOC1) - -#ifdef CONFIG_ODRIVE_FOC_FOC0 -# define ODRIVE32_FOC0_DEVPATH "/dev/foc0" -# define ODRIVE32_FOC0_INST (0) -#endif - -#ifdef CONFIG_ODRIVE_FOC_FOC1 -# define ODRIVE32_FOC1_DEVPATH "/dev/foc1" -# define ODRIVE32_FOC1_INST (1) -#endif - -/* Must match upper-half configuration */ - -#if ODRIVE_FOC_INST != CONFIG_MOTOR_FOC_INST -# error Invalid configuration -#endif - -/* Only 2-shunt configuration supported by board */ - -#if CONFIG_MOTOR_FOC_SHUNTS != 2 -# error For now only 2-shunts configuration is supported -#endif - -/* Configuration specific for DRV8301: - * 1. PWM channels must have positive polarity - * 2. PWM complementary channels must have positive polarity - */ - -#ifndef CONFIG_STM32_FOC_HAS_PWM_COMPLEMENTARY -# error -#endif - -#ifdef CONFIG_ODRIVE_FOC_FOC0 - -# if CONFIG_STM32_TIM1_CH1POL != 0 -# error -# endif -# if CONFIG_STM32_TIM1_CH2POL != 0 -# error -# endif -# if CONFIG_STM32_TIM1_CH3POL != 0 -# error -# endif -# if CONFIG_STM32_TIM1_CH1NPOL != 0 -# error -# endif -# if CONFIG_STM32_TIM1_CH2NPOL != 0 -# error -# endif -# if CONFIG_STM32_TIM1_CH3NPOL != 0 -# error -# endif - -/* FOC0 uses ADC2 */ - -# ifndef CONFIG_STM32_FOC_FOC0_ADC2 -# error -# endif - -# if CONFIG_STM32_ADC2_RESOLUTION != 0 -# error -# endif - -#endif /* CONFIG_ODRIVE_FOC_FOC0 */ - -#ifdef CONFIG_ODRIVE_FOC_FOC1 - -# if CONFIG_STM32_TIM8_CH1POL != 0 -# error -# endif -# if CONFIG_STM32_TIM8_CH2POL != 0 -# error -# endif -# if CONFIG_STM32_TIM8_CH3POL != 0 -# error -# endif -# if CONFIG_STM32_TIM8_CH1NPOL != 0 -# error -# endif -# if CONFIG_STM32_TIM8_CH2NPOL != 0 -# error -# endif -# if CONFIG_STM32_TIM8_CH3NPOL != 0 -# error -# endif - -/* FOC1 uses ADC3 */ - -# ifndef CONFIG_STM32_FOC_FOC1_ADC3 -# error -# endif - -# if CONFIG_STM32_ADC3_RESOLUTION != 0 -# error -# endif - -#endif /* CONFIG_ODRIVE_FOC_FOC1 */ - -/* Aux ADC needs DMA enabled */ - -#ifdef CONFIG_ADC -# ifndef CONFIG_STM32_ADC1_DMA -# error -# endif -# ifndef CONFIG_STM32_ADC1_SCAN -# error -# endif -#endif - -/* TODO: */ - -#define PWM_DEADTIME (50) -#define PWM_DEADTIME_NS (320) - -/* Board parameters: - * Current shunt resistance = 0.0005 - * Current sense gain = (10/20/40/80) - * Vbus min = 12V - * Vbus max = 24V or 56V - * Iout max = 40A (no cooling for - * MOSFETs) - * IPHASE_RATIO = 1/(R_shunt*gain) - * ADC_REF_VOLTAGE = 3.3 - * ADC_VAL_MAX = 4095 - * ADC_TO_VOLT = ADC_REF_VOLTAGE / ADC_VAL_MAX - * IPHASE_ADC = IPHASE_RATIO * ADC_TO_VOLT = 0.02014 (gain=80) - * VBUS_RATIO = 1/VBUS_gain = 11 or 19 - */ - -#define ADC_VOLT_REF 3300000 /* micro volt */ -#define ADC_VAL_MAX 4095 -#define R_SHUNT 500 /* micro ohm */ - -/* Center-aligned PWM duty cycle limits */ - -#define MAX_DUTY_B16 ftob16(0.95f) - -/* ADC configuration */ - -#define CURRENT_SAMPLE_TIME ADC_SMPR_3 -#define VBUS_SAMPLE_TIME ADC_SMPR_15 -#define TEMP_SAMPLE_TIME ADC_SMPR_15 - -#define ODRIVE_ADC_AUX (1) -#define ODRIVE_ADC_FOC0 (2) -#define ODRIVE_ADC_FOC1 (3) - -#ifdef CONFIG_ODRIVE_FOC_VBUS -# define ODRIVE_FOC_VBUS 1 -#else -# define ODRIVE_FOC_VBUS 0 -#endif -#ifdef CONFIG_ODRIVE_FOC_TEMP -# define ODRIVE_FOC_TEMP 3 -#else -# define ODRIVE_FOC_TEMP 0 -#endif - -#ifdef CONFIG_ADC -# define ODRIVE_ADC_AUX_DEVPATH "/dev/adc0" -# define ODRIVE_ADC_AUX_NCHAN (ODRIVE_FOC_VBUS + ODRIVE_FOC_TEMP) -#endif - -#define ADC1_INJECTED (0) -#define ADC1_REGULAR (0) -#define ADC1_NCHANNELS (ADC1_INJECTED + ADC1_REGULAR) - -#define ADC2_INJECTED (CONFIG_MOTOR_FOC_SHUNTS) -#define ADC2_REGULAR (0) -#define ADC2_NCHANNELS (ADC2_INJECTED + ADC2_REGULAR) - -#define ADC3_INJECTED (CONFIG_MOTOR_FOC_SHUNTS) -#define ADC3_REGULAR (0) -#define ADC3_NCHANNELS (ADC3_INJECTED + ADC3_REGULAR) - -#if ADC1_INJECTED != CONFIG_STM32_ADC1_INJECTED_CHAN -# error -#endif - -#if ADC2_INJECTED != CONFIG_STM32_ADC2_INJECTED_CHAN -# error -#endif - -#if ADC3_INJECTED != CONFIG_STM32_ADC3_INJECTED_CHAN -# error -#endif - -/* DRV8301 configuration */ - -#ifndef CONFIG_STM32_SPI3 -# error -#endif - -#define DRV8301_0_SPI (3) -#define DRV8301_1_SPI (3) - -#define DRV8301_FREQUENCY (500000) - -/* Qenco configuration */ - -#ifdef CONFIG_SENSORS_QENCODER -# ifndef CONFIG_STM32_QENCODER_DISABLE_EXTEND16BTIMERS -# error Invalid configuration -# endif -# ifndef CONFIG_STM32_QENCODER_INDEX_PIN -# error Invalid configuration -# endif -# ifdef CONFIG_STM32_TIM3_QE -# if CONFIG_STM32_TIM3_QEPSC != 0 -# error Invalid TIM3 QEPSC value -# endif -# endif -# ifdef CONFIG_STM32_TIM4_QE -# if CONFIG_STM32_TIM4_QEPSC != 0 -# error Invalid TIM4 QEPSC value -# endif -# endif -#endif - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/**************************************************************************** - * Private Function Protototypes - ****************************************************************************/ - -static int board_foc_setup(struct foc_dev_s *dev); -static int board_foc_shutdown(struct foc_dev_s *dev); -static int board_foc_calibration(struct foc_dev_s *dev, bool state); -static int board_foc_fault_clear(struct foc_dev_s *dev); -static int board_foc_pwm_start(struct foc_dev_s *dev, bool state); -static int board_foc_current_get(struct foc_dev_s *dev, int16_t *curr_raw, - foc_current_t *curr); -static int board_foc_info_get(struct foc_dev_s *dev, - struct foc_info_s *info); -static int board_foc_ioctl(struct foc_dev_s *dev, int cmd, - unsigned long arg); -#ifdef CONFIG_MOTOR_FOC_TRACE -static int board_foc_trace_init(struct foc_dev_s *dev); -static void board_foc_trace(struct foc_dev_s *dev, int type, bool state); -#endif - -static int stm32_foc_drv8301_fault_attach(struct focpwr_dev_s *dev, - xcpt_t isr, void *arg); -static int stm32_foc_drv8301_gate_enable(struct focpwr_dev_s *dev, - bool enable); -static void stm32_foc_drv8301_fault_handle(struct focpwr_dev_s *dev); - -static int stm32_focdev_setup(int devno, int spino, - struct stm32_foc_board_s *board); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* Board specific ops */ - -static struct stm32_foc_board_ops_s g_stm32_foc_board_ops = -{ - .setup = board_foc_setup, - .shutdown = board_foc_shutdown, - .calibration = board_foc_calibration, - .fault_clear = board_foc_fault_clear, - .pwm_start = board_foc_pwm_start, - .current_get = board_foc_current_get, - .info_get = board_foc_info_get, - .ioctl = board_foc_ioctl, -#ifdef CONFIG_MOTOR_FOC_TRACE - .trace_init = board_foc_trace_init, - .trace = board_foc_trace -#endif -}; - -/* Board specific ADC configuration - * - * AUX (only VBUS used): - * VBUS - ADC1 - ADC1_IN6 (PA6) - * M0_TEMP - ADC1 - ADC1_IN15 (PC5) - * M1_TEMP - ADC1 - ADC1_IN4 (PA4) - * AUX_TEMP - ADC1 - ADC1_IN5 (PA5) - * - * FOC device 0: - * Phase 1 - ADC2 - ADC2_IN10 (PC0) - * Phase 2 - ADC2 - ADC2_IN11 (PC1) - * - * FOC device 1: - * Phase 1 - ADC3 - ADC3_IN13 (PC3) - * Phase 2 - ADC3 - ADC3_IN12 (PC2) - * - */ - -#ifdef CONFIG_ADC - -/* AUX ADC configuration */ - -static uint8_t g_adc_aux_chan[] = -{ -#ifdef CONFIG_ODRIVE_FOC_VBUS - 6, -#endif -#ifdef ODRIVE_ADC_TEMP - 15, - 4, - 5 -#endif -}; - -static uint32_t g_adc_aux_pins[] = -{ -#ifdef CONFIG_ODRIVE_FOC_VBUS - GPIO_ADC1_IN6, -#endif -#ifdef ODRIVE_ADC_TEMP - GPIO_ADC1_IN15, - GPIO_ADC1_IN4, - GPIO_ADC1_IN5 -#endif -}; - -static adc_channel_t g_adc_aux_stime[] = -{ -#ifdef CONFIG_ODRIVE_FOC_VBUS - { - .channel = 6, - .sample_time = VBUS_SAMPLE_TIME - }, -#endif -#ifdef ODRIVE_ADC_TEMP - { - .channel = 15, - .sample_time = TEMP_SAMPLE_TIME - }, - { - .channel = 4, - .sample_time = TEMP_SAMPLE_TIME - }, - { - .channel = 5, - .sample_time = TEMP_SAMPLE_TIME - } -#endif -}; -#endif - -#ifdef CONFIG_ODRIVE_FOC_FOC0 -/* Board specific ADC configuration for FOC device 0 */ - -static uint8_t g_adc_foc0_chan[] = -{ - 10, - 11 -}; - -static uint32_t g_adc_foc0_pins[] = -{ - GPIO_ADC2_IN10, - GPIO_ADC2_IN11, -}; - -static adc_channel_t g_adc_foc0_stime[] = -{ - { - .channel = 10, - .sample_time = CURRENT_SAMPLE_TIME - }, - { - .channel = 11, - .sample_time = CURRENT_SAMPLE_TIME - } -}; - -static struct stm32_foc_adc_s g_adc_foc0_cfg = -{ - .chan = g_adc_foc0_chan, - .pins = g_adc_foc0_pins, - .stime = g_adc_foc0_stime, - .nchan = ADC2_NCHANNELS, - .regch = ADC2_REGULAR, - .intf = ODRIVE_ADC_FOC0 -}; -#endif - -#ifdef CONFIG_ODRIVE_FOC_FOC1 -/* Board specific ADC configuration for FOC device 1 */ - -static uint8_t g_adc_foc1_chan[] = -{ - 13, - 12 -}; - -static uint32_t g_adc_foc1_pins[] = -{ - GPIO_ADC3_IN13, - GPIO_ADC3_IN12, -}; - -static adc_channel_t g_adc_foc1_stime[] = -{ - { - .channel = 13, - .sample_time = CURRENT_SAMPLE_TIME - }, - { - .channel = 12, - .sample_time = CURRENT_SAMPLE_TIME - } -}; - -static struct stm32_foc_adc_s g_adc_foc1_cfg = -{ - .chan = g_adc_foc1_chan, - .pins = g_adc_foc1_pins, - .stime = g_adc_foc1_stime, - .nchan = ADC3_NCHANNELS, - .regch = ADC3_REGULAR, - .intf = ODRIVE_ADC_FOC1 -}; -#endif - -#ifdef CONFIG_ODRIVE_FOC_FOC0 -/* Board specific data - FOC 0 */ - -static struct stm32_foc_board_data_s g_stm32_foc0_board_data = -{ - .adc_cfg = &g_adc_foc0_cfg, - .pwm_dt = (PWM_DEADTIME), -}; - -/* Board specific configuration */ - -static struct stm32_foc_board_s g_stm32_foc0_board = -{ - .data = &g_stm32_foc0_board_data, - .ops = &g_stm32_foc_board_ops, -}; -#endif - -#ifdef CONFIG_ODRIVE_FOC_FOC1 -/* Board specific data - FOC 1 */ - -static struct stm32_foc_board_data_s g_stm32_foc1_board_data = -{ - .adc_cfg = &g_adc_foc1_cfg, - .pwm_dt = (PWM_DEADTIME), -}; - -/* Board specific configuration */ - -static struct stm32_foc_board_s g_stm32_foc1_board = -{ - .data = &g_stm32_foc1_board_data, - .ops = &g_stm32_foc_board_ops, -}; -#endif - -/* DRV8301 board ops */ - -static struct drv8301_ops_s g_drv8301_board_ops = -{ - .fault_attach = stm32_foc_drv8301_fault_attach, - .gate_enable = stm32_foc_drv8301_gate_enable, - .fault_handle = stm32_foc_drv8301_fault_handle -}; - -/* Global data */ - -static mutex_t g_common_lock = NXMUTEX_INITIALIZER; -static bool g_fault_attached = false; -static bool g_gate_enabled = false; - -static struct foc_dev_s *g_foc_dev[2] = -{ - NULL, - NULL -}; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_foc_setup - ****************************************************************************/ - -static int board_foc_setup(struct foc_dev_s *dev) -{ - DEBUGASSERT(dev); - DEBUGASSERT(dev->pwr); - - return dev->pwr->ops->setup(dev->pwr); -} - -/**************************************************************************** - * Name: board_foc_shutdown - ****************************************************************************/ - -static int board_foc_shutdown(struct foc_dev_s *dev) -{ - DEBUGASSERT(dev); - DEBUGASSERT(dev->pwr); - - return dev->pwr->ops->shutdown(dev->pwr); -} - -/**************************************************************************** - * Name: board_foc_calibration - ****************************************************************************/ - -static int board_foc_calibration(struct foc_dev_s *dev, bool state) -{ - DEBUGASSERT(dev); - DEBUGASSERT(dev->pwr); - - return dev->pwr->ops->calibration(dev->pwr, state); -} - -/**************************************************************************** - * Name: board_foc_fault_clear - ****************************************************************************/ - -static int board_foc_fault_clear(struct foc_dev_s *dev) -{ - DEBUGASSERT(dev); - - UNUSED(dev); - - /* TODO: clear DRV8301 faults */ - - return OK; -} - -/**************************************************************************** - * Name: board_foc_pwm_start - ****************************************************************************/ - -static int board_foc_pwm_start(struct foc_dev_s *dev, bool state) -{ - DEBUGASSERT(dev); - - return OK; -} - -/**************************************************************************** - * Name: board_foc_current_get - ****************************************************************************/ - -static int board_foc_current_get(struct foc_dev_s *dev, int16_t *curr_raw, - foc_current_t *curr) -{ - DEBUGASSERT(dev); - DEBUGASSERT(curr_raw); - DEBUGASSERT(curr); - - /* Get currents */ - - curr[1] = curr_raw[0]; - curr[2] = curr_raw[1]; - - /* From Kirchhoff's current law: ia = -(ib + ic) */ - - curr[0] = -(curr[1] + curr[2]); - - return OK; -} - -/**************************************************************************** - * Name: board_foc_info_get - ****************************************************************************/ - -static int board_foc_info_get(struct foc_dev_s *dev, - struct foc_info_s *info) -{ - struct foc_get_boardcfg_s cfg; - - DEBUGASSERT(dev); - DEBUGASSERT(info); - - UNUSED(dev); - - /* PWM */ - - info->hw_cfg.pwm_dt_ns = PWM_DEADTIME_NS; - info->hw_cfg.pwm_max = MAX_DUTY_B16; - - /* Get power stage configuration */ - - board_foc_ioctl(dev, MTRIOC_GET_BOARDCFG, (unsigned long)&cfg); - - /* ADC Current */ - - info->hw_cfg.iphase_max = 40000; - - info->hw_cfg.iphase_scale = ((100000ul * (ADC_VOLT_REF / ADC_VAL_MAX)) / - (cfg.gain * R_SHUNT)); - - return OK; -} - -/**************************************************************************** - * Name: board_foc_ioctl - ****************************************************************************/ - -static int board_foc_ioctl(struct foc_dev_s *dev, int cmd, unsigned long arg) -{ - DEBUGASSERT(dev); - DEBUGASSERT(dev->pwr); - - return dev->pwr->ops->ioctl(dev->pwr, cmd, arg); -} - -#ifdef CONFIG_MOTOR_FOC_TRACE -/**************************************************************************** - * Name: board_foc_trace_init - ****************************************************************************/ - -static int board_foc_trace_init(struct foc_dev_s *dev) -{ - DEBUGASSERT(dev); - - UNUSED(dev); - - /* Not supported */ - - return -1; -} - -/**************************************************************************** - * Name: board_foc_trace - ****************************************************************************/ - -static void board_foc_trace(struct foc_dev_s *dev, int type, bool state) -{ - DEBUGASSERT(dev); - - UNUSED(dev); -} -#endif - -/**************************************************************************** - * Name: stm32_foc_drv8301_fault_attach - ****************************************************************************/ - -static int stm32_foc_drv8301_fault_attach(struct focpwr_dev_s *dev, - xcpt_t isr, void *arg) -{ - int ret = OK; - - nxmutex_lock(&g_common_lock); - - /* nFAULT is common for both FOC instances */ - - if (g_fault_attached != (bool) isr) - { - ret = stm32_gpiosetevent(GPIO_DRV8301_NFAULT, false, true, false, - isr, arg); - - g_fault_attached = (bool) isr; - } - - nxmutex_unlock(&g_common_lock); - - return ret; -} - -/**************************************************************************** - * Name: stm32_foc_drv8301_gate_enable - ****************************************************************************/ - -static int stm32_foc_drv8301_gate_enable(struct focpwr_dev_s *dev, - bool enable) -{ - /* ENGATE is common for both FOC instances */ - - nxmutex_lock(&g_common_lock); - - if (enable != g_gate_enabled) - { - stm32_gpiowrite(GPIO_DRV8301_ENGATE, enable); - - g_gate_enabled = enable; - } - - nxmutex_unlock(&g_common_lock); - - return OK; -} - -/**************************************************************************** - * Name: stm32_foc_drv8301_fault_handle - ****************************************************************************/ - -static void stm32_foc_drv8301_fault_handle(struct focpwr_dev_s *dev) -{ - UNUSED(dev); - - /* Set fault state for both instances */ - -#ifdef CONFIG_ODRIVE_FOC_FOC0 - g_foc_dev[0]->state.fault |= FOC_FAULT_BOARD; -#endif - -#ifdef CONFIG_ODRIVE_FOC_FOC1 - g_foc_dev[1]->state.fault |= FOC_FAULT_BOARD; -#endif - - /* Disable gates for both instances */ - - stm32_gpiowrite(GPIO_DRV8301_ENGATE, false); -} - -/**************************************************************************** - * Name: stm32_focdev_setup - ****************************************************************************/ - -static int stm32_focdev_setup(int devno, int spino, - struct stm32_foc_board_s *board) -{ - struct drv8301_cfg_s drv8301_cfg; - struct drv8301_board_s drv8301_board; - struct spi_dev_s *spi = NULL; - struct foc_dev_s *foc = NULL; - int ret = OK; - char devpath[20]; - - /* Initialize arch specific FOC 0 lower-half */ - - foc = stm32_foc_initialize(devno, board); - if (foc == NULL) - { - ret = -errno; - mtrerr("Failed to initialize STM32 FOC: %d\n", ret); - goto errout; - } - - DEBUGASSERT(foc->lower); - - /* Get devpath */ - - snprintf(devpath, sizeof(devpath), "/dev/foc%d", devno); - - /* Get SPI device */ - - spi = stm32_spibus_initialize(spino); - if (spi == NULL) - { - ret = -errno; - goto errout; - } - - /* DRV8301 configuration */ - - drv8301_cfg.freq = DRV8301_FREQUENCY; - drv8301_cfg.gate_curr = DRV8301_GATECURR_1p7; - drv8301_cfg.gain = DRV8301_GAIN_80; - drv8301_cfg.pwm_mode = DRV8301_PWM_6IN; - drv8301_cfg.oc_adj = DRV8301_OCADJ_DEFAULT; - - /* DRV8301 board data */ - - drv8301_board.spi = spi; - drv8301_board.ops = &g_drv8301_board_ops; - drv8301_board.cfg = &drv8301_cfg; - drv8301_board.devno = devno; - - /* Register DRV8301 device */ - - ret = drv8301_register(devpath, foc, &drv8301_board); - if (ret < 0) - { - mtrerr("Failed to register drv8301 device: %d\n", ret); - goto errout; - } - -errout: - return ret; -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_foc_setup - * - * Description: - * Setup FOC devices - * - * Returned Value: - * 0 on success, a negated errno value on failure - * - ****************************************************************************/ - -int stm32_foc_setup(void) -{ - int ret = OK; - - /* Configure common EN_GATE */ - - stm32_configgpio(GPIO_DRV8301_ENGATE); - -#ifdef CONFIG_ODRIVE_FOC_FOC0 - ret = stm32_focdev_setup(0, DRV8301_0_SPI, &g_stm32_foc0_board); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_focdev_setup 0 failed: %d\n", ret); - goto errout; - } -#endif - -#ifdef CONFIG_ODRIVE_FOC_FOC1 - ret = stm32_focdev_setup(1, DRV8301_1_SPI, &g_stm32_foc1_board); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_focdev_setup 1 failed: %d\n", ret); - goto errout; - } -#endif - -errout: - return ret; -} - -#ifdef CONFIG_ADC -/**************************************************************************** - * Name: stm32_adc_setup - * - * Description: - * Initialize ADC and register the ADC driver. - * - ****************************************************************************/ - -int stm32_adc_setup(void) -{ - struct adc_dev_s *adc = NULL; - struct stm32_adc_dev_s *stm32_adc = NULL; - struct adc_sample_time_s stime; - int i = 0; - int ret = OK; - - /* Configure pins */ - - for (i = 0; i < ODRIVE_ADC_AUX_NCHAN; i += 1) - { - stm32_configgpio(g_adc_aux_pins[i]); - } - - /* Initialize ADC */ - - adc = stm32_adcinitialize(ODRIVE_ADC_AUX, g_adc_aux_chan, - ODRIVE_ADC_AUX_NCHAN); - if (adc == NULL) - { - aerr("ERROR: Failed to get ADC interface %d\n", ODRIVE_ADC_AUX); - ret = -ENODEV; - goto errout; - } - - /* Register ADC */ - - ret = adc_register(ODRIVE_ADC_AUX_DEVPATH, adc); - if (ret < 0) - { - aerr("ERROR: adc_register %s failed: %d\n", - ODRIVE_ADC_AUX_DEVPATH, ret); - goto errout; - } - - /* Get lower-half ADC */ - - stm32_adc = (struct stm32_adc_dev_s *)adc->ad_priv; - DEBUGASSERT(stm32_adc); - - /* Configure ADC sample time */ - - memset(&stime, 0, sizeof(struct adc_sample_time_s)); - - stime.channels_nbr = ODRIVE_ADC_AUX_NCHAN; - stime.channel = g_adc_aux_stime; - - STM32_ADC_SAMPLETIME_SET(stm32_adc, &stime); - STM32_ADC_SAMPLETIME_WRITE(stm32_adc); - - ret = OK; - -errout: - return ret; -} -#endif diff --git a/boards/arm/stm32/odrive36/src/stm32_spi.c b/boards/arm/stm32/odrive36/src/stm32_spi.c deleted file mode 100644 index dd3c358b0706e..0000000000000 --- a/boards/arm/stm32/odrive36/src/stm32_spi.c +++ /dev/null @@ -1,198 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/odrive36/src/stm32_spi.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include - -#include -#include - -#include "arm_internal.h" -#include "chip.h" -#include "stm32.h" - -#include "odrive.h" - -#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || defined(CONFIG_STM32_SPI3) - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_spidev_initialize - * - * Description: - * Called to configure SPI chip select GPIO pins for the stm32f4discovery - * board. - * - ****************************************************************************/ - -void weak_function stm32_spidev_initialize(void) -{ -#ifdef CONFIG_MOTOR_FOC -# ifdef CONFIG_ODRIVE_FOC_FOC0 - stm32_configgpio(GPIO_GATEDRV0_CS); -# endif -# ifdef CONFIG_ODRIVE_FOC_FOC1 - stm32_configgpio(GPIO_GATEDRV1_CS); -# endif -#endif /* CONFIG_MOTOR_FOC */ -} - -/**************************************************************************** - * Name: stm32_spi1/2/3select and stm32_spi1/2/3status - * - * Description: - * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status - * must be provided by board-specific logic. They are implementations of - * the select and status methods of the SPI interface defined by struct - * spi_ops_s (see include/nuttx/spi/spi.h). All other methods (including - * stm32_spibus_initialize()) are provided by common STM32 logic. To use - * this common SPI logic on your board: - * - * 1. Provide logic in stm32_boardinitialize() to configure SPI chip select - * pins. - * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() functions - * in your board-specific logic. These functions will perform chip - * selection and status operations using GPIOs in the way your board - * is configured. - * 3. Add a calls to stm32_spibus_initialize() in your low level - * application initialization logic - * 4. The handle returned by stm32_spibus_initialize() may then be used to - * bind the SPI driver to higher level logic (e.g., calling - * mmcsd_spislotinitialize(), for example, will bind the SPI driver to - * the SPI MMC/SD driver). - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_SPI1 -void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, bool selected) -{ - spiinfo("devid: %d CS: %s\n", - (int)devid, selected ? "assert" : "de-assert"); -} - -uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) -{ - return 0; -} -#endif - -#ifdef CONFIG_STM32_SPI2 -void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid, - bool selected) -{ - spiinfo("devid: %d CS: %s\n", - (int)devid, selected ? "assert" : "de-assert"); -} - -uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) -{ - return 0; -} -#endif - -#ifdef CONFIG_STM32_SPI3 -void stm32_spi3select(struct spi_dev_s *dev, uint32_t devid, bool selected) -{ - spiinfo("devid: %d CS: %s\n", - (int)devid, selected ? "assert" : "de-assert"); - -#ifdef CONFIG_MOTOR_FOC -# ifdef CONFIG_ODRIVE_FOC_FOC0 - if (devid == SPIDEV_MOTOR(0)) - { - stm32_gpiowrite(GPIO_GATEDRV0_CS, !selected); - } -# endif - -# ifdef CONFIG_ODRIVE_FOC_FOC1 - if (devid == SPIDEV_MOTOR(1)) - { - stm32_gpiowrite(GPIO_GATEDRV1_CS, !selected); - } -# endif -#endif /* CONFIG_MOTOR_FOC */ -} - -uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid) -{ - return 0; -} -#endif - -/**************************************************************************** - * Name: stm32_spi1cmddata - * - * Description: - * Set or clear the SH1101A A0 or SD1306 D/C n bit to select data (true) - * or command (false). This function must be provided by platform-specific - * logic. This is an implementation of the cmddata method of the SPI - * interface defined by struct spi_ops_s (see include/nuttx/spi/spi.h). - * - * Input Parameters: - * - * spi - SPI device that controls the bus the device that requires the CMD/ - * DATA selection. - * devid - If there are multiple devices on the bus, this selects which one - * to select cmd or data. NOTE: This design restricts, for example, - * one one SPI display per SPI bus. - * cmd - true: select command; false: select data - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef CONFIG_SPI_CMDDATA -#ifdef CONFIG_STM32_SPI1 -int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) -{ - return -ENODEV; -} -#endif - -#ifdef CONFIG_STM32_SPI2 -int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) -{ - return -ENODEV; -} -#endif - -#ifdef CONFIG_STM32_SPI3 -int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) -{ - return -ENODEV; -} -#endif -#endif /* CONFIG_SPI_CMDDATA */ - -#endif /* CONFIG_STM32_SPI1 || CONFIG_STM32_SPI2 || CONFIG_STM32_SPI3 */ diff --git a/boards/arm/stm32/odrive36/src/stm32_usb.c b/boards/arm/stm32/odrive36/src/stm32_usb.c deleted file mode 100644 index 6b622e0768b5a..0000000000000 --- a/boards/arm/stm32/odrive36/src/stm32_usb.c +++ /dev/null @@ -1,105 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/odrive36/src/stm32_usb.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -#include "arm_internal.h" -#include "stm32.h" -#include "stm32_otgfs.h" -#include "odrive.h" - -#ifdef CONFIG_STM32_OTGFS - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#if defined(CONFIG_USBDEV) -# define HAVE_USB 1 -#else -# warning "CONFIG_STM32_OTGFS is enabled but neither CONFIG_USBDEV" -# undef HAVE_USB -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_usbinitialize - * - * Description: - * Called from stm32_usbinitialize very early in initialization to setup - * USB-related GPIO pins for the STM32F4Discovery board. - * - ****************************************************************************/ - -void stm32_usbinitialize(void) -{ - /* The OTG FS has an internal soft pull-up. - * No GPIO configuration is required - */ -} - -/**************************************************************************** - * Name: stm32_usbsuspend - * - * Description: - * Board logic must provide the stm32_usbsuspend logic if the USBDEV - * driver is used. This function is called whenever the USB enters or - * leaves suspend mode. This is an opportunity for the board logic to - * shutdown clocks, power, etc. while the USB is suspended. - * - ****************************************************************************/ - -#ifdef CONFIG_USBDEV -void stm32_usbsuspend(struct usbdev_s *dev, bool resume) -{ - uinfo("resume: %d\n", resume); -} -#endif - -#endif /* CONFIG_STM32_OTGFS */ diff --git a/boards/arm/stm32/olimex-stm32-e407/CMakeLists.txt b/boards/arm/stm32/olimex-stm32-e407/CMakeLists.txt deleted file mode 100644 index 33d4a70518187..0000000000000 --- a/boards/arm/stm32/olimex-stm32-e407/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/olimex-stm32-e407/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32/olimex-stm32-e407/configs/bmp180/defconfig b/boards/arm/stm32/olimex-stm32-e407/configs/bmp180/defconfig deleted file mode 100644 index d5df1ff53bac9..0000000000000 --- a/boards/arm/stm32/olimex-stm32-e407/configs/bmp180/defconfig +++ /dev/null @@ -1,56 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="olimex-stm32-e407" -CONFIG_ARCH_BOARD_COMMON=y -CONFIG_ARCH_BOARD_OLIMEX_STM32E407=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F407ZG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARDCTL_USBDEVCTRL=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_CDCACM=y -CONFIG_CDCACM_CONSOLE=y -CONFIG_EXAMPLES_BMP180=y -CONFIG_EXAMPLES_HELLO=y -CONFIG_FS_PROCFS=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_MM_REGIONS=2 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_SENSORS=y -CONFIG_SENSORS_BMP180=y -CONFIG_START_DAY=6 -CONFIG_START_MONTH=12 -CONFIG_START_YEAR=2011 -CONFIG_STM32_I2C1=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_OTGFS=y -CONFIG_STM32_PWR=y -CONFIG_STM32_USART2=y -CONFIG_SYSTEM_NSH=y -CONFIG_USART2_RXBUFSIZE=128 -CONFIG_USART2_TXBUFSIZE=128 -CONFIG_USBDEV=y diff --git a/boards/arm/stm32/olimex-stm32-e407/configs/dac/defconfig b/boards/arm/stm32/olimex-stm32-e407/configs/dac/defconfig deleted file mode 100644 index 19fe331945263..0000000000000 --- a/boards/arm/stm32/olimex-stm32-e407/configs/dac/defconfig +++ /dev/null @@ -1,57 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -CONFIG_ANALOG=y -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="olimex-stm32-e407" -CONFIG_ARCH_BOARD_OLIMEX_STM32E407=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F407ZG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARDCTL_USBDEVCTRL=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_CDCACM=y -CONFIG_CDCACM_CONSOLE=y -CONFIG_DAC=y -CONFIG_EXAMPLES_DAC=y -CONFIG_EXAMPLES_HELLO=y -CONFIG_EXAMPLES_HELLOXX=y -CONFIG_FS_PROCFS=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_MM_REGIONS=2 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=6 -CONFIG_START_MONTH=12 -CONFIG_START_YEAR=2011 -CONFIG_STM32_DAC1=y -CONFIG_STM32_DAC1CH1=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_OTGFS=y -CONFIG_STM32_PWR=y -CONFIG_STM32_USART3=y -CONFIG_SYSTEM_NSH=y -CONFIG_USART3_RXBUFSIZE=128 -CONFIG_USART3_TXBUFSIZE=128 -CONFIG_USBDEV=y diff --git a/boards/arm/stm32/olimex-stm32-e407/configs/discover/defconfig b/boards/arm/stm32/olimex-stm32-e407/configs/discover/defconfig deleted file mode 100644 index a83bf4730a9c9..0000000000000 --- a/boards/arm/stm32/olimex-stm32-e407/configs/discover/defconfig +++ /dev/null @@ -1,70 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="olimex-stm32-e407" -CONFIG_ARCH_BOARD_OLIMEX_STM32E407=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F407ZG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_ARM_TOOLCHAIN_BUILDROOT=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_DEBUG_FULLOPT=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_ETH0_PHY_LAN8720=y -CONFIG_EXAMPLES_DISCOVER=y -CONFIG_EXAMPLES_DISCOVER_DHCPC=y -CONFIG_EXAMPLES_DISCOVER_DRIPADDR=0xc0a80101 -CONFIG_EXAMPLES_DISCOVER_NOMAC=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_INIT_ENTRYPOINT="discover_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_MM_REGIONS=2 -CONFIG_NET=y -CONFIG_NET_ARP_IPIN=y -CONFIG_NET_BROADCAST=y -CONFIG_NET_ICMP_SOCKET=y -CONFIG_NET_MAX_LISTENPORTS=40 -CONFIG_NET_STATISTICS=y -CONFIG_NET_TCP=y -CONFIG_NET_TCP_PREALLOC_CONNS=40 -CONFIG_NET_UDP=y -CONFIG_NET_UDP_CHECKSUMS=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_WAITPID=y -CONFIG_SPI=y -CONFIG_START_DAY=6 -CONFIG_START_MONTH=12 -CONFIG_START_YEAR=2011 -CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32_ETHMAC=y -CONFIG_STM32_JTAG_FULL_ENABLE=y -CONFIG_STM32_PHYADDR=0 -CONFIG_STM32_PHYSR=31 -CONFIG_STM32_PHYSR_100FD=0x0018 -CONFIG_STM32_PHYSR_100HD=0x0008 -CONFIG_STM32_PHYSR_10FD=0x0014 -CONFIG_STM32_PHYSR_10HD=0x0004 -CONFIG_STM32_PHYSR_ALTCONFIG=y -CONFIG_STM32_PHYSR_ALTMODE=0x001c -CONFIG_STM32_PWR=y -CONFIG_STM32_RMII_EXTCLK=y -CONFIG_STM32_USART2=y -CONFIG_SYSTEM_PING=y -CONFIG_USART2_RXBUFSIZE=128 -CONFIG_USART2_SERIAL_CONSOLE=y -CONFIG_USART2_TXBUFSIZE=128 diff --git a/boards/arm/stm32/olimex-stm32-e407/configs/ina219/defconfig b/boards/arm/stm32/olimex-stm32-e407/configs/ina219/defconfig deleted file mode 100644 index e406cc5fb0235..0000000000000 --- a/boards/arm/stm32/olimex-stm32-e407/configs/ina219/defconfig +++ /dev/null @@ -1,57 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_DEV_CONSOLE is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="olimex-stm32-e407" -CONFIG_ARCH_BOARD_COMMON=y -CONFIG_ARCH_BOARD_OLIMEX_STM32E407=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F407ZG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARDCTL_USBDEVCTRL=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_CDCACM=y -CONFIG_CDCACM_CONSOLE=y -CONFIG_CDCACM_RXBUFSIZE=256 -CONFIG_CDCACM_TXBUFSIZE=256 -CONFIG_EXAMPLES_HELLO=y -CONFIG_EXAMPLES_INA219=y -CONFIG_FS_PROCFS=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_IDLETHREAD_STACKSIZE=2048 -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_MM_REGIONS=2 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_SENSORS=y -CONFIG_SENSORS_INA219=y -CONFIG_START_DAY=27 -CONFIG_START_YEAR=2013 -CONFIG_STM32_I2C1=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_OTGFS=y -CONFIG_STM32_PWR=y -CONFIG_STM32_USART2=y -CONFIG_SYSLOG_CHAR=y -CONFIG_SYSLOG_DEVPATH="/dev/ttyS0" -CONFIG_SYSTEM_NSH=y -CONFIG_USBDEV=y diff --git a/boards/arm/stm32/olimex-stm32-e407/configs/mrf24j40-6lowpan/defconfig b/boards/arm/stm32/olimex-stm32-e407/configs/mrf24j40-6lowpan/defconfig deleted file mode 100644 index c0f90c9741115..0000000000000 --- a/boards/arm/stm32/olimex-stm32-e407/configs/mrf24j40-6lowpan/defconfig +++ /dev/null @@ -1,103 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_NET_ETHERNET is not set -# CONFIG_NET_IPv4 is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="olimex-stm32-e407" -CONFIG_ARCH_BOARD_OLIMEX_STM32E407=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F407ZG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARDCTL_USBDEVCTRL=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_CDCACM=y -CONFIG_CDCACM_CONSOLE=y -CONFIG_DEBUG_FEATURES=y -CONFIG_DEBUG_NET=y -CONFIG_DEBUG_NET_ERROR=y -CONFIG_DEBUG_NET_INFO=y -CONFIG_DEBUG_NET_WARN=y -CONFIG_DEBUG_WIRELESS=y -CONFIG_DEBUG_WIRELESS_ERROR=y -CONFIG_DEBUG_WIRELESS_INFO=y -CONFIG_DEBUG_WIRELESS_WARN=y -CONFIG_DRIVERS_IEEE802154=y -CONFIG_DRIVERS_WIRELESS=y -CONFIG_FS_PROCFS=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_IEEE802154_I8SAK=y -CONFIG_IEEE802154_MAC=y -CONFIG_IEEE802154_MACDEV=y -CONFIG_IEEE802154_MRF24J40=y -CONFIG_IEEE802154_NETDEV=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_IOB_BUFSIZE=128 -CONFIG_IOB_NBUFFERS=32 -CONFIG_IOB_NCHAINS=16 -CONFIG_LINE_MAX=64 -CONFIG_MAC802154_NTXDESC=32 -CONFIG_MM_REGIONS=2 -CONFIG_NET=y -CONFIG_NETDEV_IFINDEX=y -CONFIG_NETDEV_LATEINIT=y -CONFIG_NETDEV_PHY_IOCTL=y -CONFIG_NETDEV_STATISTICS=y -CONFIG_NETDEV_WIRELESS_IOCTL=y -CONFIG_NETUTILS_TELNETD=y -CONFIG_NET_6LOWPAN=y -CONFIG_NET_6LOWPAN_COMPRESSION_THRESHOLD=500 -CONFIG_NET_6LOWPAN_EXTENDEDADDR=y -CONFIG_NET_BROADCAST=y -CONFIG_NET_ICMPv6=y -CONFIG_NET_ICMPv6_AUTOCONF=y -CONFIG_NET_ICMPv6_NEIGHBOR=y -CONFIG_NET_ICMPv6_ROUTER=y -CONFIG_NET_ICMPv6_SOCKET=y -CONFIG_NET_IPv6=y -CONFIG_NET_PROMISCUOUS=y -CONFIG_NET_ROUTE=y -CONFIG_NET_SOCKOPTS=y -CONFIG_NET_STATISTICS=y -CONFIG_NET_TCP=y -CONFIG_NET_TCP_WRITE_BUFFERS=y -CONFIG_NET_UDP=y -CONFIG_NET_UDP_WRITE_BUFFERS=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_LPWORK=y -CONFIG_START_DAY=6 -CONFIG_START_MONTH=12 -CONFIG_START_YEAR=2011 -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_OTGFS=y -CONFIG_STM32_PWR=y -CONFIG_STM32_SPI1=y -CONFIG_STM32_USART3=y -CONFIG_SYSTEM_NSH=y -CONFIG_SYSTEM_PING6=y -CONFIG_SYSTEM_SYSTEM=y -CONFIG_USART3_RXBUFSIZE=128 -CONFIG_USART3_TXBUFSIZE=128 -CONFIG_USBDEV=y -CONFIG_WIRELESS=y -CONFIG_WIRELESS_IEEE802154=y diff --git a/boards/arm/stm32/olimex-stm32-e407/configs/mrf24j40-mac/defconfig b/boards/arm/stm32/olimex-stm32-e407/configs/mrf24j40-mac/defconfig deleted file mode 100644 index a9221bfba48c3..0000000000000 --- a/boards/arm/stm32/olimex-stm32-e407/configs/mrf24j40-mac/defconfig +++ /dev/null @@ -1,62 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="olimex-stm32-e407" -CONFIG_ARCH_BOARD_OLIMEX_STM32E407=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F407ZG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_DEBUG_FEATURES=y -CONFIG_DEBUG_WIRELESS=y -CONFIG_DEBUG_WIRELESS_ERROR=y -CONFIG_DEBUG_WIRELESS_INFO=y -CONFIG_DEBUG_WIRELESS_WARN=y -CONFIG_DRIVERS_IEEE802154=y -CONFIG_DRIVERS_WIRELESS=y -CONFIG_FS_PROCFS=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_IEEE802154_I8SAK=y -CONFIG_IEEE802154_MAC=y -CONFIG_IEEE802154_MACDEV=y -CONFIG_IEEE802154_MRF24J40=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_MM_REGIONS=2 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_LPWORK=y -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=6 -CONFIG_START_MONTH=12 -CONFIG_START_YEAR=2011 -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_PWR=y -CONFIG_STM32_SPI1=y -CONFIG_STM32_USART3=y -CONFIG_SYSTEM_NSH=y -CONFIG_USART3_RXBUFSIZE=128 -CONFIG_USART3_SERIAL_CONSOLE=y -CONFIG_USART3_TXBUFSIZE=128 -CONFIG_WIRELESS=y -CONFIG_WIRELESS_IEEE802154=y diff --git a/boards/arm/stm32/olimex-stm32-e407/configs/netnsh/defconfig b/boards/arm/stm32/olimex-stm32-e407/configs/netnsh/defconfig deleted file mode 100644 index 2e75fb27370b4..0000000000000 --- a/boards/arm/stm32/olimex-stm32-e407/configs/netnsh/defconfig +++ /dev/null @@ -1,75 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="olimex-stm32-e407" -CONFIG_ARCH_BOARD_OLIMEX_STM32E407=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F407ZG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_ARM_TOOLCHAIN_BUILDROOT=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_DEBUG_FULLOPT=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_ETH0_PHY_LAN8720=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_MM_REGIONS=2 -CONFIG_NET=y -CONFIG_NETDB_DNSCLIENT=y -CONFIG_NETINIT_DHCPC=y -CONFIG_NETINIT_DRIPADDR=0xc0a80101 -CONFIG_NETINIT_NOMAC=y -CONFIG_NETUTILS_DHCPC=y -CONFIG_NETUTILS_DISCOVER=y -CONFIG_NETUTILS_TELNETD=y -CONFIG_NET_ARP_IPIN=y -CONFIG_NET_BROADCAST=y -CONFIG_NET_ICMP_SOCKET=y -CONFIG_NET_MAX_LISTENPORTS=40 -CONFIG_NET_STATISTICS=y -CONFIG_NET_TCP=y -CONFIG_NET_TCP_PREALLOC_CONNS=40 -CONFIG_NET_UDP=y -CONFIG_NET_UDP_CHECKSUMS=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_WAITPID=y -CONFIG_SPI=y -CONFIG_START_DAY=6 -CONFIG_START_MONTH=12 -CONFIG_START_YEAR=2011 -CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32_ETHMAC=y -CONFIG_STM32_JTAG_FULL_ENABLE=y -CONFIG_STM32_PHYADDR=0 -CONFIG_STM32_PHYSR=31 -CONFIG_STM32_PHYSR_100FD=0x0018 -CONFIG_STM32_PHYSR_100HD=0x0008 -CONFIG_STM32_PHYSR_10FD=0x0014 -CONFIG_STM32_PHYSR_10HD=0x0004 -CONFIG_STM32_PHYSR_ALTCONFIG=y -CONFIG_STM32_PHYSR_ALTMODE=0x001c -CONFIG_STM32_PWR=y -CONFIG_STM32_RMII_EXTCLK=y -CONFIG_STM32_USART2=y -CONFIG_SYSTEM_NSH=y -CONFIG_SYSTEM_PING=y -CONFIG_USART2_RXBUFSIZE=128 -CONFIG_USART2_SERIAL_CONSOLE=y -CONFIG_USART2_TXBUFSIZE=128 diff --git a/boards/arm/stm32/olimex-stm32-e407/configs/nsh/defconfig b/boards/arm/stm32/olimex-stm32-e407/configs/nsh/defconfig deleted file mode 100644 index 571f8a9adb70a..0000000000000 --- a/boards/arm/stm32/olimex-stm32-e407/configs/nsh/defconfig +++ /dev/null @@ -1,48 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="olimex-stm32-e407" -CONFIG_ARCH_BOARD_OLIMEX_STM32E407=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F407ZG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_EXAMPLES_HELLO=y -CONFIG_EXAMPLES_HELLOXX=y -CONFIG_FS_PROCFS=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_MM_REGIONS=2 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=6 -CONFIG_START_MONTH=12 -CONFIG_START_YEAR=2011 -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_PWR=y -CONFIG_STM32_USART2=y -CONFIG_SYSTEM_NSH=y -CONFIG_USART2_RXBUFSIZE=128 -CONFIG_USART2_SERIAL_CONSOLE=y -CONFIG_USART2_TXBUFSIZE=128 diff --git a/boards/arm/stm32/olimex-stm32-e407/configs/telnetd/defconfig b/boards/arm/stm32/olimex-stm32-e407/configs/telnetd/defconfig deleted file mode 100644 index 6a11a0f3b3939..0000000000000 --- a/boards/arm/stm32/olimex-stm32-e407/configs/telnetd/defconfig +++ /dev/null @@ -1,78 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="olimex-stm32-e407" -CONFIG_ARCH_BOARD_OLIMEX_STM32E407=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F407ZG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_ARM_TOOLCHAIN_BUILDROOT=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_DEBUG_FULLOPT=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_ETH0_PHY_LAN8720=y -CONFIG_EXAMPLES_TELNETD=y -CONFIG_EXAMPLES_TELNETD_CLIENTPRIO=128 -CONFIG_EXAMPLES_TELNETD_DAEMONPRIO=128 -CONFIG_EXAMPLES_TELNETD_DRIPADDR=0xc0a80101 -CONFIG_EXAMPLES_TELNETD_IPADDR=0xc0a80185 -CONFIG_EXAMPLES_TELNETD_NOMAC=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_INIT_ENTRYPOINT="telnetd_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_MM_REGIONS=2 -CONFIG_NET=y -CONFIG_NETDB_DNSCLIENT=y -CONFIG_NETUTILS_DHCPC=y -CONFIG_NETUTILS_DISCOVER=y -CONFIG_NETUTILS_TELNETD=y -CONFIG_NET_ARP_IPIN=y -CONFIG_NET_BROADCAST=y -CONFIG_NET_ICMP_SOCKET=y -CONFIG_NET_MAX_LISTENPORTS=40 -CONFIG_NET_STATISTICS=y -CONFIG_NET_TCP=y -CONFIG_NET_TCP_PREALLOC_CONNS=40 -CONFIG_NET_UDP=y -CONFIG_NET_UDP_CHECKSUMS=y -CONFIG_NSH_LIBRARY=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_WAITPID=y -CONFIG_SPI=y -CONFIG_START_DAY=6 -CONFIG_START_MONTH=12 -CONFIG_START_YEAR=2011 -CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32_ETHMAC=y -CONFIG_STM32_JTAG_FULL_ENABLE=y -CONFIG_STM32_PHYADDR=0 -CONFIG_STM32_PHYSR=31 -CONFIG_STM32_PHYSR_100FD=0x0018 -CONFIG_STM32_PHYSR_100HD=0x0008 -CONFIG_STM32_PHYSR_10FD=0x0014 -CONFIG_STM32_PHYSR_10HD=0x0004 -CONFIG_STM32_PHYSR_ALTCONFIG=y -CONFIG_STM32_PHYSR_ALTMODE=0x001c -CONFIG_STM32_PWR=y -CONFIG_STM32_RMII_EXTCLK=y -CONFIG_STM32_USART2=y -CONFIG_SYSTEM_PING=y -CONFIG_SYSTEM_READLINE=y -CONFIG_USART2_RXBUFSIZE=128 -CONFIG_USART2_SERIAL_CONSOLE=y -CONFIG_USART2_TXBUFSIZE=128 diff --git a/boards/arm/stm32/olimex-stm32-e407/configs/timer/defconfig b/boards/arm/stm32/olimex-stm32-e407/configs/timer/defconfig deleted file mode 100644 index 98aa59ace4cd6..0000000000000 --- a/boards/arm/stm32/olimex-stm32-e407/configs/timer/defconfig +++ /dev/null @@ -1,53 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="olimex-stm32-e407" -CONFIG_ARCH_BOARD_OLIMEX_STM32E407=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F407ZG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARDCTL_USBDEVCTRL=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_CDCACM=y -CONFIG_CDCACM_CONSOLE=y -CONFIG_EXAMPLES_HELLO=y -CONFIG_FS_PROCFS=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_MM_REGIONS=2 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=6 -CONFIG_START_MONTH=12 -CONFIG_START_YEAR=2011 -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_OTGFS=y -CONFIG_STM32_PWR=y -CONFIG_STM32_TIM1=y -CONFIG_STM32_USART3=y -CONFIG_SYSTEM_NSH=y -CONFIG_TIMER=y -CONFIG_USART3_RXBUFSIZE=128 -CONFIG_USART3_TXBUFSIZE=128 -CONFIG_USBDEV=y diff --git a/boards/arm/stm32/olimex-stm32-e407/configs/usbnsh/defconfig b/boards/arm/stm32/olimex-stm32-e407/configs/usbnsh/defconfig deleted file mode 100644 index 93de54935666f..0000000000000 --- a/boards/arm/stm32/olimex-stm32-e407/configs/usbnsh/defconfig +++ /dev/null @@ -1,54 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_DEV_CONSOLE is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="olimex-stm32-e407" -CONFIG_ARCH_BOARD_OLIMEX_STM32E407=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F407ZG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARDCTL_USBDEVCTRL=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_CDCACM=y -CONFIG_CDCACM_CONSOLE=y -CONFIG_CDCACM_RXBUFSIZE=256 -CONFIG_CDCACM_TXBUFSIZE=256 -CONFIG_EXAMPLES_HELLO=y -CONFIG_EXAMPLES_HELLOXX=y -CONFIG_FS_PROCFS=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_IDLETHREAD_STACKSIZE=2048 -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_MM_REGIONS=2 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_SPI=y -CONFIG_START_DAY=27 -CONFIG_START_YEAR=2013 -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_OTGFS=y -CONFIG_STM32_PWR=y -CONFIG_STM32_USART2=y -CONFIG_SYSLOG_CHAR=y -CONFIG_SYSLOG_DEVPATH="/dev/ttyS0" -CONFIG_SYSTEM_NSH=y -CONFIG_USBDEV=y diff --git a/boards/arm/stm32/olimex-stm32-e407/configs/webserver/defconfig b/boards/arm/stm32/olimex-stm32-e407/configs/webserver/defconfig deleted file mode 100644 index f01bcc9c11cac..0000000000000 --- a/boards/arm/stm32/olimex-stm32-e407/configs/webserver/defconfig +++ /dev/null @@ -1,72 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="olimex-stm32-e407" -CONFIG_ARCH_BOARD_OLIMEX_STM32E407=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F407ZG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_ARM_TOOLCHAIN_BUILDROOT=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_DEBUG_FULLOPT=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_ETH0_PHY_LAN8720=y -CONFIG_EXAMPLES_WEBSERVER=y -CONFIG_EXAMPLES_WEBSERVER_DRIPADDR=0xc0a80101 -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_INIT_ENTRYPOINT="webserver_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_MM_REGIONS=2 -CONFIG_NET=y -CONFIG_NETDB_DNSCLIENT=y -CONFIG_NETUTILS_DHCPC=y -CONFIG_NETUTILS_DISCOVER=y -CONFIG_NETUTILS_WEBSERVER=y -CONFIG_NET_ARP_IPIN=y -CONFIG_NET_BROADCAST=y -CONFIG_NET_ICMP_SOCKET=y -CONFIG_NET_MAX_LISTENPORTS=40 -CONFIG_NET_STATISTICS=y -CONFIG_NET_TCP=y -CONFIG_NET_TCP_PREALLOC_CONNS=40 -CONFIG_NET_UDP=y -CONFIG_NET_UDP_CHECKSUMS=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_WAITPID=y -CONFIG_SPI=y -CONFIG_START_DAY=6 -CONFIG_START_MONTH=12 -CONFIG_START_YEAR=2011 -CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32_ETHMAC=y -CONFIG_STM32_JTAG_FULL_ENABLE=y -CONFIG_STM32_PHYADDR=0 -CONFIG_STM32_PHYSR=31 -CONFIG_STM32_PHYSR_100FD=0x0018 -CONFIG_STM32_PHYSR_100HD=0x0008 -CONFIG_STM32_PHYSR_10FD=0x0014 -CONFIG_STM32_PHYSR_10HD=0x0004 -CONFIG_STM32_PHYSR_ALTCONFIG=y -CONFIG_STM32_PHYSR_ALTMODE=0x001c -CONFIG_STM32_PWR=y -CONFIG_STM32_RMII_EXTCLK=y -CONFIG_STM32_USART2=y -CONFIG_SYSTEM_PING=y -CONFIG_USART2_RXBUFSIZE=128 -CONFIG_USART2_SERIAL_CONSOLE=y -CONFIG_USART2_TXBUFSIZE=128 diff --git a/boards/arm/stm32/olimex-stm32-e407/include/board.h b/boards/arm/stm32/olimex-stm32-e407/include/board.h deleted file mode 100644 index 2ea3adb4e42b0..0000000000000 --- a/boards/arm/stm32/olimex-stm32-e407/include/board.h +++ /dev/null @@ -1,280 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/olimex-stm32-e407/include/board.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __BOARDS_ARM_STM32_OLIMEX_STM32_E407_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32_OLIMEX_STM32_E407_INCLUDE_BOARD_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#ifndef __ASSEMBLY__ -# include -# include -#endif - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Clocking *****************************************************************/ - -/* The Olimex-STM32-E407 board features a 12MHz crystal and - * a 32kHz RTC backup crystal. - * - * This is the canonical configuration: - * System Clock source : PLL (HSE) - * SYSCLK(Hz) : 168000000 Determined by PLL configuration - * HCLK(Hz) : 168000000 (STM32_RCC_CFGR_HPRE) - * AHB Prescaler : 1 (STM32_RCC_CFGR_HPRE) - * APB1 Prescaler : 4 (STM32_RCC_CFGR_PPRE1) - * APB2 Prescaler : 2 (STM32_RCC_CFGR_PPRE2) - * HSE Frequency(Hz) : 8000000 (STM32_BOARD_XTAL) - * PLLM : 8 (STM32_PLLCFG_PLLM) - * PLLN : 336 (STM32_PLLCFG_PLLN) - * PLLP : 2 (STM32_PLLCFG_PLLP) - * PLLQ : 7 (STM32_PLLCFG_PLLQ) - * Main regulator output - * voltage : Scale1 mode Needed for high speed SYSCLK - * Flash Latency(WS) : 5 - * Prefetch Buffer : OFF - * Instruction cache : ON - * Data cache : ON - * Require 48MHz for : Enabled - * USB OTG FS, - * SDIO and RNG clock - */ - -/* HSI - 16 MHz RC factory-trimmed - * LSI - 32 KHz RC (30-60KHz, uncalibrated) - * HSE - On-board crystal frequency is 12MHz - * LSE - 32.768 kHz - * STM32F407ZGT6 - too 168Mhz - */ - -#define STM32_BOARD_XTAL 12000000ul - -#define STM32_HSI_FREQUENCY 16000000ul -#define STM32_LSI_FREQUENCY 32000 -#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL -#define STM32_LSE_FREQUENCY 32768 - -/* Main PLL Configuration. - * - * PLL source is HSE - * PLL_VCO = (STM32_HSE_FREQUENCY / PLLM) * PLLN - * = (25,000,000 / 12) * 360 - * = 240,000,000 - * SYSCLK = PLL_VCO / PLLP - * = 240,000,000 / 2 = 120,000,000 - * USB OTG FS, SDIO and RNG Clock - * = PLL_VCO / PLLQ - * = 240,000,000 / 5 = 48,000,000 - * = 48,000,000 - * - * Xtal /M *n /P SysClk AHB HCLK APB1 PCLK1 - * 12Mhz HSE /12 336 /2 PLLCLK 168Mhz /1 168 /4 42Mhz - * 12Mhz HSE /6 168 /2 PLLCLK 168Mhz /1 168 /4 42Mhz - */ - -#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(3) -#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(84) -#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_2 -#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(5) -#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(7) - -#define STM32_SYSCLK_FREQUENCY 168000000ul - -/* AHB clock (HCLK) is SYSCLK (168MHz) */ - -#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ -#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY - -/* APB1 clock (PCLK1) is HCLK/4 (42MHz) */ - -#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd4 /* PCLK1 = HCLK / 4 */ -#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/4) - -/* Timers driven from APB1 will be twice PCLK1 */ - -#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) - -/* APB2 clock (PCLK2) is HCLK/2 */ - -#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLKd2 /* PCLK2 = HCLK / 2 */ -#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/2) - -/* Timers driven from APB2 will be twice PCLK2 */ - -#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM9_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM10_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM11_CLKIN (2*STM32_PCLK2_FREQUENCY) - -/* Timer Frequencies, if APBx is set to 1, frequency is same as APBx - * otherwise frequency is 2xAPBx. - * Note: TIM1,8 are on APB2, others on APB1 - */ - -#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM2_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM3_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM4_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM5_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM6_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM7_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY - -/* LED definitions **********************************************************/ - -/* If CONFIG_ARCH_LEDS is not defined, then the user can control the status - * LED in any way. - * The following definitions are used to access individual LEDs. - */ - -/* LED index values for use with board_userled() */ - -#define BOARD_LED_STATUS 0 -#define BOARD_NLEDS 1 - -/* LED bits for use with board_userled_all() */ - -#define BOARD_LED_STATUS_BIT (1 << BOARD_LED1) - -/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the status LED of - * the Olimex STM32-E405. - * The following definitions describe how NuttX controls the LEDs: - */ - -#define LED_STARTED 0 /* LED_STATUS on */ -#define LED_HEAPALLOCATE 1 /* no change */ -#define LED_IRQSENABLED 2 /* no change */ -#define LED_STACKCREATED 3 /* no change */ -#define LED_INIRQ 4 /* no change */ -#define LED_SIGNAL 5 /* no change */ -#define LED_ASSERTION 6 /* LED_STATUS off */ -#define LED_PANIC 7 /* LED_STATUS blinking */ - -/* Button definitions *******************************************************/ - -/* The Olimex STM32-E405 supports one buttons: */ - -#define BUTTON_BUT 0 -#define NUM_BUTTONS 1 - -#define BUTTON_BUT_BIT (1 << BUTTON_BUT) - -/* Alternate function pin selections ****************************************/ - -/* USART1 */ - -#define GPIO_USART1_RX (GPIO_USART1_RX_2|GPIO_SPEED_100MHz) /* PB7 */ -#define GPIO_USART1_TX (GPIO_USART1_TX_2|GPIO_SPEED_100MHz) /* PB6 */ - -/* USART2 */ - -#define GPIO_USART2_RX (GPIO_USART2_RX_2|GPIO_SPEED_100MHz) /* PD6 */ -#define GPIO_USART2_TX (GPIO_USART2_TX_2|GPIO_SPEED_100MHz) /* PD5 */ - -/* USART3 */ - -#define GPIO_USART3_RX (GPIO_USART3_RX_1|GPIO_SPEED_100MHz) /* PB11 */ -#define GPIO_USART3_TX (GPIO_USART3_TX_1|GPIO_SPEED_100MHz) /* PB10 */ - -/* CAN */ - -#define GPIO_CAN1_RX (GPIO_CAN1_RX_2|GPIO_SPEED_50MHz) /* PB8 */ -#define GPIO_CAN1_TX (GPIO_CAN1_TX_2|GPIO_SPEED_50MHz) /* PB9 */ - -/* I2C */ - -#define GPIO_I2C1_SCL (GPIO_I2C1_SCL_1|GPIO_SPEED_50MHz) /* PB6 */ -#define GPIO_I2C1_SDA (GPIO_I2C1_SDA_1|GPIO_SPEED_50MHz) /* PB7 */ - -/* SPI1 */ - -#define GPIO_SPI1_SCK (GPIO_SPI1_SCK_1|GPIO_SPEED_50MHz) /* PA5 */ -#define GPIO_SPI1_MOSI (GPIO_SPI1_MOSI_2|GPIO_SPEED_50MHz) /* PB5 */ -#define GPIO_SPI1_MISO (GPIO_SPI1_MISO_1|GPIO_SPEED_50MHz) /* PA6 */ - -/* Ethernet *****************************************************************/ - -#if defined(CONFIG_STM32_ETHMAC) -/* RMII interface to the LAN8710 PHY (works with LAN8720 driver) */ - -# ifndef CONFIG_STM32_RMII -# error CONFIG_STM32_RMII must be defined -# endif - -/* Clocking is provided by an external 50Mhz XTAL */ - -# ifndef CONFIG_STM32_RMII_EXTCLK -# error CONFIG_STM32_RMII_EXTCLK must be defined -# endif - -/* Pin disambiguation */ - -# define GPIO_ETH_MII_COL (GPIO_ETH_MII_COL_1|GPIO_SPEED_100MHz) /* PA3 */ -# define GPIO_ETH_RMII_TXD0 (GPIO_ETH_RMII_TXD0_2|GPIO_SPEED_100MHz) /* PG13 */ -# define GPIO_ETH_RMII_TXD1 (GPIO_ETH_RMII_TXD1_2|GPIO_SPEED_100MHz) /* PG14 */ -# define GPIO_ETH_RMII_TX_EN (GPIO_ETH_RMII_TX_EN_2|GPIO_SPEED_100MHz) /* PG11 */ - -#endif - -/* ETH MII/RMII inputs and MDC/MDIO (referenced by arch driver) */ - -#define GPIO_ETH_MDC (GPIO_ETH_MDC_0|GPIO_SPEED_100MHz) -#define GPIO_ETH_MDIO (GPIO_ETH_MDIO_0|GPIO_SPEED_100MHz) -#define GPIO_ETH_MII_RX_CLK (GPIO_ETH_MII_RX_CLK_0|GPIO_SPEED_100MHz) -#define GPIO_ETH_MII_RX_DV (GPIO_ETH_MII_RX_DV_0|GPIO_SPEED_100MHz) -#define GPIO_ETH_MII_RXD0 (GPIO_ETH_MII_RXD0_0|GPIO_SPEED_100MHz) -#define GPIO_ETH_MII_RXD1 (GPIO_ETH_MII_RXD1_0|GPIO_SPEED_100MHz) -#define GPIO_ETH_RMII_CRS_DV (GPIO_ETH_RMII_CRS_DV_0|GPIO_SPEED_100MHz) -#define GPIO_ETH_RMII_REF_CLK (GPIO_ETH_RMII_REF_CLK_0|GPIO_SPEED_100MHz) -#define GPIO_ETH_RMII_RXD0 (GPIO_ETH_RMII_RXD0_0|GPIO_SPEED_100MHz) -#define GPIO_ETH_RMII_RXD1 (GPIO_ETH_RMII_RXD1_0|GPIO_SPEED_100MHz) -#define GPIO_MCO1 (GPIO_MCO1_0|GPIO_SPEED_100MHz) - -/* DAC */ - -#define GPIO_DAC1_OUT1 GPIO_DAC1_OUT1_0 -#define GPIO_DAC1_OUT2 GPIO_DAC1_OUT2_0 - -/* USB OTG FS */ - -#define GPIO_OTGFS_DM (GPIO_OTGFS_DM_0|GPIO_SPEED_100MHz) -#define GPIO_OTGFS_DP (GPIO_OTGFS_DP_0|GPIO_SPEED_100MHz) -#define GPIO_OTGFS_ID (GPIO_OTGFS_ID_0|GPIO_SPEED_100MHz) -#define GPIO_OTGFS_SOF (GPIO_OTGFS_SOF_0|GPIO_SPEED_100MHz) - -#endif /* __BOARDS_ARM_STM32_OLIMEX_STM32_E407_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32/olimex-stm32-e407/scripts/Make.defs b/boards/arm/stm32/olimex-stm32-e407/scripts/Make.defs deleted file mode 100644 index 4d7247871dc24..0000000000000 --- a/boards/arm/stm32/olimex-stm32-e407/scripts/Make.defs +++ /dev/null @@ -1,46 +0,0 @@ -############################################################################ -# boards/arm/stm32/olimex-stm32-e407/scripts/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/.config -include $(TOPDIR)/tools/Config.mk -include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs - -ifeq ($(CONFIG_ARCH_CHIP_STM32F407ZE),y) -LDSCRIPT = f407ze.ld -else ifeq ($(CONFIG_ARCH_CHIP_STM32F407ZG),y) -LDSCRIPT = f407zg.ld -endif - -ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) - -ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 - -CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) -CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) -CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -AFLAGS := $(CFLAGS) -D__ASSEMBLY__ - -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections -LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32/olimex-stm32-e407/src/CMakeLists.txt b/boards/arm/stm32/olimex-stm32-e407/src/CMakeLists.txt deleted file mode 100644 index 152d38216dde5..0000000000000 --- a/boards/arm/stm32/olimex-stm32-e407/src/CMakeLists.txt +++ /dev/null @@ -1,77 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/olimex-stm32-e407/src/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -set(SRCS stm32_boot.c stm32_bringup.c stm32_spi.c) - -if(CONFIG_ARCH_LEDS) - list(APPEND SRCS stm32_autoleds.c) -else() - list(APPEND SRCS stm32_userleds.c) -endif() - -if(CONFIG_ARCH_BUTTONS) - list(APPEND SRCS stm32_buttons.c) -endif() - -if(CONFIG_ARCH_IDLE_CUSTOM) - list(APPEND SRCS stm32_idle.c) -endif() - -if(CONFIG_STM32_FSMC) - list(APPEND SRCS stm32_extmem.c) -endif() - -if(CONFIG_STM32_OTGFS) - list(APPEND SRCS stm32_usb.c) -endif() - -if(CONFIG_STM32_OTGHS) - list(APPEND SRCS stm32_usb.c) -endif() - -if(CONFIG_ADC) - list(APPEND SRCS stm32_adc.c) -endif() - -if(CONFIG_CAN) - list(APPEND SRCS stm32_can.c) -endif() - -if(CONFIG_DAC) - list(APPEND SRCS stm32_dac.c) -endif() - -if(CONFIG_TIMER) - list(APPEND SRCS stm32_timer.c) -endif() - -if(CONFIG_IEEE802154_MRF24J40) - list(APPEND SRCS stm32_mrf24j40.c) -endif() - -target_sources(board PRIVATE ${SRCS}) - -if(CONFIG_ARCH_CHIP_STM32F407ZE) - set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/f407ze.ld") -else() - set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/f407zg.ld") -endif() diff --git a/boards/arm/stm32/olimex-stm32-e407/src/Make.defs b/boards/arm/stm32/olimex-stm32-e407/src/Make.defs deleted file mode 100644 index e5b1f17edc3de..0000000000000 --- a/boards/arm/stm32/olimex-stm32-e407/src/Make.defs +++ /dev/null @@ -1,75 +0,0 @@ -############################################################################ -# boards/arm/stm32/olimex-stm32-e407/src/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/Make.defs - -CSRCS = stm32_boot.c stm32_bringup.c stm32_spi.c - -ifeq ($(CONFIG_ARCH_LEDS),y) -CSRCS += stm32_autoleds.c -else -CSRCS += stm32_userleds.c -endif - -ifeq ($(CONFIG_ARCH_BUTTONS),y) -CSRCS += stm32_buttons.c -endif - -ifeq ($(CONFIG_ARCH_IDLE_CUSTOM),y) -CSRCS += stm32_idle.c -endif - -ifeq ($(CONFIG_STM32_FSMC),y) -CSRCS += stm32_extmem.c -endif - -ifeq ($(CONFIG_STM32_OTGFS),y) -CSRCS += stm32_usb.c -endif - -ifeq ($(CONFIG_STM32_OTGHS),y) -CSRCS += stm32_usb.c -endif - -ifeq ($(CONFIG_ADC),y) -CSRCS += stm32_adc.c -endif - -ifeq ($(CONFIG_CAN),y) -CSRCS += stm32_can.c -endif - -ifeq ($(CONFIG_DAC),y) -CSRCS += stm32_dac.c -endif - -ifeq ($(CONFIG_TIMER),y) -CSRCS += stm32_timer.c -endif - -ifeq ($(CONFIG_IEEE802154_MRF24J40),y) -CSRCS += stm32_mrf24j40.c -endif - -DEPPATH += --dep-path board -VPATH += :board -CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/olimex-stm32-e407/src/stm32_adc.c b/boards/arm/stm32/olimex-stm32-e407/src/stm32_adc.c deleted file mode 100644 index f97001b1243da..0000000000000 --- a/boards/arm/stm32/olimex-stm32-e407/src/stm32_adc.c +++ /dev/null @@ -1,166 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/olimex-stm32-e407/src/stm32_adc.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include -#include - -#include "chip.h" -#include "stm32_adc.h" -#include "olimex-stm32-e407.h" - -#ifdef CONFIG_ADC - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -/* Up to 3 ADC interfaces are supported */ - -#if STM32_NADC < 3 -# undef CONFIG_STM32_ADC3 -#endif - -#if STM32_NADC < 2 -# undef CONFIG_STM32_ADC2 -#endif - -#if STM32_NADC < 1 -# undef CONFIG_STM32_ADC1 -#endif - -#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) || defined(CONFIG_STM32_ADC3) -#ifndef CONFIG_STM32_ADC1 -# warning "Channel information only available for ADC1" -#endif - -/* The number of ADC channels in the conversion list */ - -#define ADC1_NCHANNELS 1//14 - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* The Olimex STM32-P405 has a 10 Kohm potentiometer AN_TR connected to PC0 - * ADC123_IN10 - */ - -/* Identifying number of each ADC channel: Variable Resistor. - * - * {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 15}; - */ - -#ifdef CONFIG_STM32_ADC1 -static const uint8_t g_chanlist[ADC1_NCHANNELS] = -{ - 1 -}; - -/* Configurations of pins used byte each ADC channels - * - * {GPIO_ADC1_IN1, GPIO_ADC1_IN2, GPIO_ADC1_IN3, - * GPIO_ADC1_IN4, GPIO_ADC1_IN5, GPIO_ADC1_IN6, - * GPIO_ADC1_IN7, GPIO_ADC1_IN8, GPIO_ADC1_IN9, - * GPIO_ADC1_IN10, GPIO_ADC1_IN11, GPIO_ADC1_IN12, - * GPIO_ADC1_IN13, GPIO_ADC1_IN15}; - */ - -static const uint32_t g_pinlist[ADC1_NCHANNELS] = -{ - GPIO_ADC1_IN1 -}; -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_adc_setup - * - * Description: - * Initialize ADC and register the ADC driver. - * - ****************************************************************************/ - -int stm32_adc_setup(void) -{ -#ifdef CONFIG_STM32_ADC1 - static bool initialized = false; - struct adc_dev_s *adc; - int ret; - int i; - - /* Check if we have already initialized */ - - if (!initialized) - { - /* Configure the pins as analog inputs for the selected channels */ - - for (i = 0; i < ADC1_NCHANNELS; i++) - { - stm32_configgpio(g_pinlist[i]); - } - - /* Call stm32_adcinitialize() to get an instance of the ADC interface */ - - adc = stm32_adcinitialize(1, g_chanlist, ADC1_NCHANNELS); - if (adc == NULL) - { - adbg("ERROR: Failed to get ADC interface\n"); - return -ENODEV; - } - - /* Register the ADC driver at "/dev/adc0" */ - - ret = adc_register("/dev/adc0", adc); - if (ret < 0) - { - adbg("adc_register failed: %d\n", ret); - return ret; - } - - /* Now we are initialized */ - - initialized = true; - } - - return OK; -#else - return -ENOSYS; -#endif -} - -#endif /* CONFIG_STM32_ADC1 || CONFIG_STM32_ADC2 || CONFIG_STM32_ADC3 */ -#endif /* CONFIG_ADC */ diff --git a/boards/arm/stm32/olimex-stm32-e407/src/stm32_autoleds.c b/boards/arm/stm32/olimex-stm32-e407/src/stm32_autoleds.c deleted file mode 100644 index 89766c7191e4c..0000000000000 --- a/boards/arm/stm32/olimex-stm32-e407/src/stm32_autoleds.c +++ /dev/null @@ -1,92 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/olimex-stm32-e407/src/stm32_autoleds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32.h" -#include "olimex-stm32-e407.h" - -#ifdef CONFIG_ARCH_LEDS - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_autoled_initialize - ****************************************************************************/ - -void board_autoled_initialize(void) -{ - /* Configure LED_STATUS GPIO for output */ - - stm32_configgpio(GPIO_LED_STATUS); -} - -/**************************************************************************** - * Name: board_autoled_on - ****************************************************************************/ - -void board_autoled_on(int led) -{ - if (led == LED_STARTED) - { - stm32_gpiowrite(GPIO_LED_STATUS, true); - } - - if (led == LED_ASSERTION || led == LED_PANIC) - { - stm32_gpiowrite(GPIO_LED_STATUS, false); - } -} - -/**************************************************************************** - * Name: board_autoled_off - ****************************************************************************/ - -void board_autoled_off(int led) -{ - if (led == LED_STARTED) - { - stm32_gpiowrite(GPIO_LED_STATUS, false); - } - - if (led == LED_ASSERTION || led == LED_PANIC) - { - stm32_gpiowrite(GPIO_LED_STATUS, true); - } -} - -#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/olimex-stm32-e407/src/stm32_boot.c b/boards/arm/stm32/olimex-stm32-e407/src/stm32_boot.c deleted file mode 100644 index 9c52967acfcdd..0000000000000 --- a/boards/arm/stm32/olimex-stm32-e407/src/stm32_boot.c +++ /dev/null @@ -1,105 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/olimex-stm32-e407/src/stm32_boot.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include -#include -#include - -#include "arm_internal.h" -#include "stm32_ccm.h" -#include "stm32.h" -#include "stm32_i2c.h" - -#include "olimex-stm32-e407.h" - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_boardinitialize - * - * Description: - * All STM32 architectures must provide the following entry point. This - * entry point is called early in the initialization -- after all memory - * has been configured and mapped but before any devices have been - * initialized. - * - ****************************************************************************/ - -void stm32_boardinitialize(void) -{ -#if defined(CONFIG_STM32_OTGFS) || defined(CONFIG_STM32_OTGHS) - /* Initialize USB if the 1) OTG FS controller is in the configuration and - * 2) disabled, and 3) the weak function stm32_usbinitialize() has been - * brought into the build. Presumably either CONFIG_USBDEV is also - * selected. - */ - - if (stm32_usbinitialize) - { - stm32_usbinitialize(); - } -#endif - -#ifdef CONFIG_ARCH_LEDS - /* Configure on-board LEDs if LED support has been selected. */ - - board_autoled_initialize(); -#endif - -#ifdef CONFIG_ARCH_BUTTONS - /* Configure on-board BUTTONs if BUTTON support has been selected. */ - - board_button_initialize(); -#endif -} - -/**************************************************************************** - * Name: board_late_initialize - * - * Description: - * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional - * initialization call will be performed in the boot-up sequence to a - * function called board_late_initialize(). board_late_initialize() will be - * called immediately after up_initialize() is called and just before the - * initial application is started. This additional initialization phase - * may be used, for example, to initialize board-specific device drivers. - * - ****************************************************************************/ - -#ifdef CONFIG_BOARD_LATE_INITIALIZE -void board_late_initialize(void) -{ - /* Perform board-specific initialization */ - - stm32_bringup(); -} -#endif diff --git a/boards/arm/stm32/olimex-stm32-e407/src/stm32_bringup.c b/boards/arm/stm32/olimex-stm32-e407/src/stm32_bringup.c deleted file mode 100644 index 5636dad261832..0000000000000 --- a/boards/arm/stm32/olimex-stm32-e407/src/stm32_bringup.c +++ /dev/null @@ -1,283 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/olimex-stm32-e407/src/stm32_bringup.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include - -#include - -#ifdef CONFIG_USBMONITOR -# include -#endif - -#ifdef CONFIG_STM32_OTGFS -# include "stm32_usbhost.h" -#endif - -#include "stm32.h" -#include "olimex-stm32-e407.h" - -/* The following are includes from board-common logic */ - -#ifdef CONFIG_SENSORS_BMP180 -#include "stm32_bmp180.h" -#endif - -#ifdef CONFIG_SENSORS_INA219 -#include "stm32_ina219.h" -#endif - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -#define HAVE_USBDEV 1 -#define HAVE_USBHOST 1 -#define HAVE_USBMONITOR 1 -/* #define HAVE_I2CTOOL 1 */ - -/* Can't support USB host or device features if USB OTG HS is not enabled */ - -#ifndef CONFIG_STM32_OTGHS -# undef HAVE_USBDEV -# undef HAVE_USBHOST -#endif - -/* Can't support USB device USB device is not enabled */ - -#ifndef CONFIG_USBDEV -# undef HAVE_USBDEV -#endif - -/* Can't support USB host is USB host is not enabled */ - -#ifndef CONFIG_USBHOST -# undef HAVE_USBHOST -#endif - -/* Check if we should enable the USB monitor before starting NSH */ - -#ifndef CONFIG_USBMONITOR -# undef HAVE_USBMONITOR -#endif - -#ifndef HAVE_USBDEV -# undef CONFIG_USBDEV_TRACE -#endif - -#ifndef HAVE_USBHOST -# undef CONFIG_USBHOST_TRACE -#endif - -#if !defined(CONFIG_USBDEV_TRACE) && !defined(CONFIG_USBHOST_TRACE) -# undef HAVE_USBMONITOR -#endif - -#if !defined(CONFIG_STM32_CAN1) && !defined(CONFIG_STM32_CAN2) -# undef CONFIG_CAN -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_i2c_register - * - * Description: - * Register one I2C drivers for the I2C tool. - * - ****************************************************************************/ - -#ifdef HAVE_I2CTOOL -static void stm32_i2c_register(int bus) -{ - struct i2c_master_s *i2c; - int ret; - - i2c = stm32_i2cbus_initialize(bus); - if (i2c == NULL) - { - _err("ERROR: Failed to get I2C%d interface\n", bus); - } - else - { - ret = i2c_register(i2c, bus); - if (ret < 0) - { - _err("ERROR: Failed to register I2C%d driver: %d\n", bus, ret); - stm32_i2cbus_uninitialize(i2c); - } - } -} -#endif - -/**************************************************************************** - * Name: stm32_i2ctool - * - * Description: - * Register I2C drivers for the I2C tool. - * - ****************************************************************************/ - -#ifdef HAVE_I2CTOOL -static void stm32_i2ctool(void) -{ -#ifdef CONFIG_STM32_I2C1 - stm32_i2c_register(1); -#endif -#ifdef CONFIG_STM32_I2C2 - stm32_i2c_register(2); -#endif -#ifdef CONFIG_STM32_I2C3 - stm32_i2c_register(3); -#endif -} -#else -# define stm32_i2ctool() -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_bringup - * - * Description: - * Perform architecture-specific initialization - * - * CONFIG_BOARD_LATE_INITIALIZE=y : - * Called from board_late_initialize(). - * - ****************************************************************************/ - -int stm32_bringup(void) -{ - int ret; - - /* Register I2C drivers on behalf of the I2C tool */ - - stm32_i2ctool(); - -#ifdef CONFIG_CAN - /* Initialize CAN and register the CAN driver. */ - - ret = stm32_can_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_can_setup failed: %d\n", ret); - } -#endif - -#ifdef HAVE_USBHOST - /* Initialize USB host operation. stm32_usbhost_initialize() starts a - * thread will monitor for USB connection and disconnection events. - */ - - ret = stm32_usbhost_initialize(); - if (ret != OK) - { - syslog(LOG_ERR, "ERROR: Failed to initialize USB host: %d\n", ret); - return ret; - } -#endif - -#ifdef HAVE_USBMONITOR - /* Start the USB Monitor */ - - ret = usbmonitor_start(); - if (ret != OK) - { - syslog(LOG_ERR, "ERROR: Failed to start USB monitor: %d\n", ret); - } -#endif - -#ifdef CONFIG_SENSORS_BMP180 - /* Initialize the BMP180 pressure sensor. */ - - ret = board_bmp180_initialize(0, 1); - if (ret < 0) - { - syslog(LOG_ERR, "Failed to initialize BMP180, error %d\n", ret); - return ret; - } -#endif - -#ifdef CONFIG_DAC - /* Initialize DAC and register the DAC driver. */ - - ret = stm32_dac_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: Failed to start ADC1: %d\n", ret); - } -#endif - -#ifdef CONFIG_SENSORS_INA219 - /* Configure and initialize the INA219 sensor */ - - ret = board_ina219_initialize(0, 1); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_ina219initialize() failed: %d\n", ret); - } -#endif - -#if defined(CONFIG_TIMER) - /* Initialize the timer, at this moment it's only Timer 1,2,3 */ - - #if defined(CONFIG_STM32_TIM1) - stm32_timer_driver_setup("/dev/timer1", 1); - #endif - #if defined(CONFIG_STM32_TIM2) - stm32_timer_driver_setup("/dev/timer2", 2); - #endif - #if defined(CONFIG_STM32_TIM3) - stm32_timer_driver_setup("/dev/timer3", 3); - #endif -#endif - -#ifdef CONFIG_IEEE802154_MRF24J40 - /* Configure MRF24J40 wireless */ - - ret = stm32_mrf24j40_initialize(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_mrf24j40_initialize() failed:" - " %d\n", ret); - } -#endif - - UNUSED(ret); - return OK; -} diff --git a/boards/arm/stm32/olimex-stm32-e407/src/stm32_buttons.c b/boards/arm/stm32/olimex-stm32-e407/src/stm32_buttons.c deleted file mode 100644 index 8964bd3c7b4a7..0000000000000 --- a/boards/arm/stm32/olimex-stm32-e407/src/stm32_buttons.c +++ /dev/null @@ -1,140 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/olimex-stm32-e407/src/stm32_buttons.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include -#include - -#include "olimex-stm32-e407.h" - -#ifdef CONFIG_ARCH_BUTTONS - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* Pin configuration for each Olimex-STM32-H405 button. This array is - * indexed by the BUTTON_* definitions in board.h - */ - -static const uint32_t g_buttons[NUM_BUTTONS] = -{ - GPIO_BTN_BUT -}; - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_button_initialize - * - * Description: - * board_button_initialize() must be called to initialize button resources. - * After that, board_buttons() may be called to collect the current state - * of all buttons or board_button_irq() may be called to register button - * interrupt handlers. - * - ****************************************************************************/ - -uint32_t board_button_initialize(void) -{ - int i; - - /* Configure the GPIO pins as inputs. NOTE that EXTI interrupts are - * configured for all pins. - */ - - for (i = 0; i < NUM_BUTTONS; i++) - { - stm32_configgpio(g_buttons[i]); - } - - return NUM_BUTTONS; -} - -/**************************************************************************** - * Name: board_buttons - ****************************************************************************/ - -uint32_t board_buttons(void) -{ - uint32_t ret = 0; - - /* Check that state of each key */ - - if (!stm32_gpioread(g_buttons[BUTTON_BUT])) - { - ret |= BUTTON_BUT_BIT; - } - - return ret; -} - -/**************************************************************************** - * Button support. - * - * Description: - * board_button_initialize() must be called to initialize button resources. - * After that, board_buttons() may be called to collect the current state - * of all buttons or board_button_irq() may be called to register button - * interrupt handlers. - * - * After board_button_initialize() has been called, board_buttons() may be - * called to collect the state of all buttons. board_buttons() returns an - * 32-bit bit set with each bit associated with a button. See the - * BUTTON_*_BIT definitions in board.h for the meaning of each bit. - * - * board_button_irq() may be called to register an interrupt handler that - * will be called when a button is depressed or released. The ID value is - * a button enumeration value that uniquely identifies a button resource. - * See the BUTTON_* definitions in board.h for the meaning of enumeration - * value. - * - ****************************************************************************/ - -#ifdef CONFIG_ARCH_IRQBUTTONS -int board_button_irq(int id, xcpt_t irqhandler, void *arg) -{ - int ret = -EINVAL; - - /* The following should be atomic */ - - if (id >= MIN_IRQBUTTON && id <= MAX_IRQBUTTON) - { - ret = stm32_gpiosetevent(g_buttons[id], true, true, true, irqhandler, - arg); - } - - return ret; -} -#endif -#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/stm32/olimex-stm32-e407/src/stm32_can.c b/boards/arm/stm32/olimex-stm32-e407/src/stm32_can.c deleted file mode 100644 index 468129ff98d1f..0000000000000 --- a/boards/arm/stm32/olimex-stm32-e407/src/stm32_can.c +++ /dev/null @@ -1,100 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/olimex-stm32-e407/src/stm32_can.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include - -#include "stm32.h" -#include "stm32_can.h" -#include "olimex-stm32-e407.h" - -#ifdef CONFIG_CAN - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -#if defined(CONFIG_STM32_CAN1) && defined(CONFIG_STM32_CAN2) -# warning "Both CAN1 and CAN2 are enabled. Only CAN1 is used." -# undef CONFIG_STM32_CAN2 -#endif - -#ifdef CONFIG_STM32_CAN1 -# define CAN_PORT 1 -#else -# define CAN_PORT 2 -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_can_setup - * - * Description: - * Initialize CAN and register the CAN device - * - ****************************************************************************/ - -int stm32_can_setup(void) -{ -#if defined(CONFIG_STM32_CAN1) || defined(CONFIG_STM32_CAN2) - struct can_dev_s *can; - int ret; - - /* Call stm32_caninitialize() to get an instance of the CAN interface */ - - can = stm32_caninitialize(CAN_PORT); - if (can == NULL) - { - candbg("ERROR: Failed to get CAN interface\n"); - return -ENODEV; - } - - /* Register the CAN driver at "/dev/can0" */ - - ret = can_register("/dev/can0", can); - if (ret < 0) - { - candbg("ERROR: can_register failed: %d\n", ret); - return ret; - } - - return OK; -#else - return -ENODEV; -#endif -} - -#endif /* CONFIG_CAN */ diff --git a/boards/arm/stm32/olimex-stm32-e407/src/stm32_dac.c b/boards/arm/stm32/olimex-stm32-e407/src/stm32_dac.c deleted file mode 100644 index b98658b4eb0cb..0000000000000 --- a/boards/arm/stm32/olimex-stm32-e407/src/stm32_dac.c +++ /dev/null @@ -1,110 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/olimex-stm32-e407/src/stm32_dac.c - * - * SPDX-License-Identifier: BSD-3-Clause - * SPDX-FileCopyrightText: 2019 Acutronics Robotics All rights reserved. - * SPDX-FileContributor: Juan Flores - * SPDX-FileContributor: Juha Niskanen - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include -#include - -#include -#include - -#include "stm32_dac.h" -#include "olimex-stm32-e407.h" - -#include - -#if defined(CONFIG_DAC) - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -static struct dac_dev_s *g_dac; - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_dac_setup - * - * Description: - * Initialize and register the DAC0 of the microcontroller. - * - * Input parameters: - * devpath - The full path to the driver to register. E.g., "/dev/dac0" - * - * Returned Value: - * Zero (OK) on success; a negated errno value on failure. - * - ****************************************************************************/ - -int stm32_dac_setup(void) -{ - static bool initialized = false; - - if (!initialized) - { - int ret; - - g_dac = stm32_dacinitialize(1); - if (g_dac == NULL) - { - aerr("ERROR: Failed to get DAC interface\n"); - return -ENODEV; - } - - /* Register the DAC driver at "/dev/dac0" */ - - ret = dac_register("/dev/dac0", g_dac); - if (ret < 0) - { - aerr("ERROR: dac_register failed: %d\n", ret); - return ret; - } - - initialized = true; - } - - return OK; -} - -#endif diff --git a/boards/arm/stm32/olimex-stm32-e407/src/stm32_mrf24j40.c b/boards/arm/stm32/olimex-stm32-e407/src/stm32_mrf24j40.c deleted file mode 100644 index 7659f5432a767..0000000000000 --- a/boards/arm/stm32/olimex-stm32-e407/src/stm32_mrf24j40.c +++ /dev/null @@ -1,279 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/olimex-stm32-e407/src/stm32_mrf24j40.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -#include "stm32_gpio.h" -#include "stm32_exti.h" -#include "stm32_spi.h" - -#include "olimex-stm32-e407.h" - -#ifdef CONFIG_IEEE802154_MRF24J40 - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -struct stm32_priv_s -{ - struct mrf24j40_lower_s dev; - xcpt_t handler; - void *arg; - uint32_t intcfg; - uint8_t spidev; -}; - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -/* IRQ/GPIO access callbacks. These operations all hidden behind callbacks - * to isolate the MRF24J40 driver from differences in GPIO interrupt handling - * varying boards and MCUs. - * - * irq_attach - Attach the MRF24J40 interrupt handler to the GPIO - * interrupt - * irq_enable - Enable or disable the GPIO interrupt - */ - -static int stm32_attach_irq(const struct mrf24j40_lower_s *lower, - xcpt_t handler, void *arg); -static void stm32_enable_irq(const struct mrf24j40_lower_s *lower, - bool state); -static int stm32_mrf24j40_devsetup(struct stm32_priv_s *priv); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* A reference to a structure of this type must be passed to the MRF24J40 - * driver. This structure provides information about the configuration - * of the MRF24J40 and provides some board-specific hooks. - * - * Memory for this structure is provided by the caller. It is not copied - * by the driver and is presumed to persist while the driver is active. The - * memory must be writable because, under certain circumstances, the driver - * may modify frequency or X plate resistance values. - */ - -static struct stm32_priv_s g_mrf24j40_mb1_priv = -{ - .dev.attach = stm32_attach_irq, - .dev.enable = stm32_enable_irq, - .handler = NULL, - .arg = NULL, - .intcfg = GPIO_MRF24J40_INT, - .spidev = 1, -}; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/* IRQ/GPIO access callbacks. These operations all hidden behind - * callbacks to isolate the MRF24J40 driver from differences in GPIO - * interrupt handling by varying boards and MCUs. If possible, - * interrupts should be configured on both rising and falling edges - * so that contact and loss-of-contact events can be detected. - * - * irq_attach - Attach the MRF24J40 interrupt handler to the GPIO - * interrupt - * irq_enable - Enable or disable the GPIO interrupt - */ - -static int stm32_attach_irq(const struct mrf24j40_lower_s *lower, - xcpt_t handler, void *arg) -{ - struct stm32_priv_s *priv = (struct stm32_priv_s *)lower; - - DEBUGASSERT(priv != NULL); - - /* Just save the handler for use when the interrupt is enabled */ - - priv->handler = handler; - priv->arg = arg; - return OK; -} - -static void stm32_enable_irq(const struct mrf24j40_lower_s *lower, - bool state) -{ - struct stm32_priv_s *priv = (struct stm32_priv_s *)lower; - - /* The caller should not attempt to enable interrupts if the handler - * has not yet been 'attached' - */ - - DEBUGASSERT(priv != NULL && (priv->handler != NULL || !state)); - - wlinfo("state:%d\n", (int)state); - - /* Attach and enable, or detach and disable */ - - if (state) - { - stm32_gpiosetevent(priv->intcfg, false, true, true, - priv->handler, priv->arg); - } - else - { - stm32_gpiosetevent(priv->intcfg, false, false, false, - NULL, NULL); - } -} - -/**************************************************************************** - * Name: stm32_mrf24j40_devsetup - * - * Description: - * Initialize one the MRF24J40 device in one mikroBUS slot - * - * Returned Value: - * Zero is returned on success. Otherwise, a negated errno value is - * returned to indicate the nature of the failure. - * - ****************************************************************************/ - -static int stm32_mrf24j40_devsetup(struct stm32_priv_s *priv) -{ - struct ieee802154_radio_s *radio; - MACHANDLE mac; - struct spi_dev_s *spi; - int ret; - - /* Configure the interrupt pin */ - - stm32_configgpio(priv->intcfg); - - /* Initialize the SPI bus and get an instance of the SPI interface */ - - spi = stm32_spibus_initialize(priv->spidev); - if (spi == NULL) - { - wlerr("ERROR: Failed to initialize SPI bus %d\n", priv->spidev); - return -ENODEV; - } - - /* Initialize and register the SPI MRF24J40 device */ - - radio = mrf24j40_init(spi, &priv->dev); - if (radio == NULL) - { - wlerr("ERROR: Failed to initialize SPI bus %d\n", priv->spidev); - return -ENODEV; - } - - /* Create a 802.15.4 MAC device from a 802.15.4 compatible radio device. */ - - mac = mac802154_create(radio); - if (mac == NULL) - { - wlerr("ERROR: Failed to initialize IEEE802.15.4 MAC\n"); - return -ENODEV; - } - -#ifdef CONFIG_IEEE802154_NETDEV - /* Use the IEEE802.15.4 MAC interface instance to create a 6LoWPAN - * network interface by wrapping the MAC interface instance in a - * network device driver via mac802154dev_register(). - */ - - ret = mac802154netdev_register(mac); - if (ret < 0) - { - wlerr("ERROR: Failed to register the MAC network driver wpan%d: %d\n", - 0, ret); - return ret; - } -#endif - -#ifdef CONFIG_IEEE802154_MACDEV - /* If want to call these APIs from userspace, you have to wrap the MAC - * interface in a character device viamac802154dev_register(). - */ - - ret = mac802154dev_register(mac, 0); - if (ret < 0) - { - wlerr("ERROR: " - "Failed to register the MAC character driver /dev/ieee%d: %d\n", - 0, ret); - return ret; - } -#endif - - UNUSED(ret); - return OK; -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_mrf24j40_initialize - * - * Description: - * Initialize the MRF24J40 device. - * - * Returned Value: - * Zero is returned on success. Otherwise, a negated errno value is - * returned to indicate the nature of the failure. - * - ****************************************************************************/ - -int stm32_mrf24j40_initialize(void) -{ - int ret; - - wlinfo("Configuring MRF24J40\n"); - - ret = stm32_mrf24j40_devsetup(&g_mrf24j40_mb1_priv); - if (ret < 0) - { - wlerr("ERROR: Failed to initialize BD in mikroBUS1: %d\n", ret); - } - - UNUSED(ret); - return OK; -} -#endif /* CONFIG_IEEE802154_MRF24J40 */ diff --git a/boards/arm/stm32/olimex-stm32-e407/src/stm32_spi.c b/boards/arm/stm32/olimex-stm32-e407/src/stm32_spi.c deleted file mode 100644 index 8f81e1556a2ff..0000000000000 --- a/boards/arm/stm32/olimex-stm32-e407/src/stm32_spi.c +++ /dev/null @@ -1,303 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/olimex-stm32-e407/src/stm32_spi.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include "arm_internal.h" -#include "chip.h" -#include "stm32.h" -#include "olimex-stm32-e407.h" - -#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_spidev_initialize - * - * Description: - * Called to configure SPI chip select GPIO pins for the Olimex-STM32-E407 - * board. - * - ****************************************************************************/ - -void stm32_spidev_initialize(void) -{ - /* NOTE: Clocking for SPI1 and/or SPI2 was already provided in stm32_rcc.c. - * Configurations of SPI pins is performed in stm32_spi.c. - * Here, we only initialize chip select pins unique to the board - * architecture. - */ - -#ifdef CONFIG_MTD_W25 - stm32_configgpio(FLASH_SPI1_CS); /* FLASH chip select */ -#endif - -#ifdef CONFIG_CAN_MCP2515 - stm32_configgpio(GPIO_MCP2515_CS); /* MCP2515 chip select */ -#endif - -#ifdef CONFIG_CL_MFRC522 - stm32_configgpio(GPIO_CS_MFRC522); /* MFRC522 chip select */ -#endif - -#if defined(CONFIG_SENSORS_MAX6675) - stm32_configgpio(GPIO_MAX6675_CS); /* MAX6675 chip select */ -#endif - -#ifdef CONFIG_LCD_MAX7219 - stm32_configgpio(STM32_LCD_CS); /* MAX7219 chip select */ -#endif - -#ifdef CONFIG_LCD_ST7567 - stm32_configgpio(STM32_LCD_CS); /* ST7567 chip select */ -#endif - -#ifdef CONFIG_LCD_PCD8544 - stm32_configgpio(STM32_LCD_CS); /* ST7567 chip select */ -#endif - -#ifdef CONFIG_WL_NRF24L01 - stm32_configgpio(GPIO_NRF24L01_CS); /* nRF24L01 chip select */ -#endif - -#ifdef CONFIG_MMCSD_SPI - stm32_configgpio(GPIO_SDCARD_CS); /* SD/MMC Card chip select */ -#endif - -#ifdef CONFIG_IEEE802154_MRF24J40 - stm32_configgpio(GPIO_MRF24J40_CS); /* MRF24J40 chip select */ -#endif -} - -/**************************************************************************** - * Name: stm32_spi1/2select and stm32_spi1/2status - * - * Description: - * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status - * must be provided by board-specific logic. They are implementations of - * the select and status methods of the SPI interface defined by struct - * spi_ops_s (see include/nuttx/spi/spi.h). All other methods (including - * stm32_spibus_initialize()) are provided by common STM32 logic. To use - * this common SPI logic on your board: - * - * 1. Provide logic in stm32_boardinitialize() to configure SPI chip select - * pins. - * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() functions - * in your board-specific logic. These functions will perform chip - * selection and status operations using GPIOs in the way your board is - * configured. - * 3. Add a calls to stm32_spibus_initialize() in your low level - * application initialization logic - * 4. The handle returned by stm32_spibus_initialize() may then be used to - * bind the SPI driver to higher level logic (e.g., calling - * mmcsd_spislotinitialize(), for example, will bind the SPI driver to - * the SPI MMC/SD driver). - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_SPI1 -void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, - bool selected) -{ -#if defined(CONFIG_CAN_MCP2515) - if (devid == SPIDEV_CANBUS(0)) - { - stm32_gpiowrite(GPIO_MCP2515_CS, !selected); - } -#endif - -#if defined(CONFIG_CL_MFRC522) - if (devid == SPIDEV_CONTACTLESS(0)) - { - stm32_gpiowrite(GPIO_CS_MFRC522, !selected); - } -#endif - -#ifdef CONFIG_IEEE802154_MRF24J40 - if (devid == SPIDEV_IEEE802154(0)) - { - stm32_gpiowrite(GPIO_MRF24J40_CS, !selected); - } -#endif - -#if defined(CONFIG_IEEE802154_XBEE) - if (devid == SPIDEV_IEEE802154(0)) - { - stm32_gpiowrite(GPIO_XBEE_CS, !selected); - } -#endif - -#if defined(CONFIG_SENSORS_MAX6675) - if (devid == SPIDEV_TEMPERATURE(0)) - { - stm32_gpiowrite(GPIO_MAX6675_CS, !selected); - } -#endif - -#ifdef CONFIG_LCD_MAX7219 - if (devid == SPIDEV_DISPLAY(0)) - { - stm32_gpiowrite(STM32_LCD_CS, !selected); - } -#endif - -#ifdef CONFIG_LCD_PCD8544 - if (devid == SPIDEV_DISPLAY(0)) - { - stm32_gpiowrite(STM32_LCD_CS, !selected); - } -#endif - -#ifdef CONFIG_LCD_ST7567 - if (devid == SPIDEV_DISPLAY(0)) - { - stm32_gpiowrite(STM32_LCD_CS, !selected); - } -#endif - -#ifdef CONFIG_WL_NRF24L01 - if (devid == SPIDEV_WIRELESS(0)) - { - stm32_gpiowrite(GPIO_NRF24L01_CS, !selected); - } -#endif - -#ifdef CONFIG_MMCSD_SPI - if (devid == SPIDEV_MMCSD(0)) - { - stm32_gpiowrite(GPIO_SDCARD_CS, !selected); - } -#endif - -#ifdef CONFIG_MTD_W25 - stm32_gpiowrite(FLASH_SPI1_CS, !selected); -#endif -} - -uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) -{ - uint8_t status = 0; - -#ifdef CONFIG_WL_NRF24L01 - if (devid == SPIDEV_WIRELESS(0)) - { - status |= SPI_STATUS_PRESENT; - } -#endif - -#ifdef CONFIG_MMCSD_SPI - if (devid == SPIDEV_MMCSD(0)) - { - status |= SPI_STATUS_PRESENT; - } -#endif - - return status; -} -#endif - -#ifdef CONFIG_STM32_SPI2 -void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid, - bool selected) -{ -} - -uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) -{ - return 0; -} -#endif - -/**************************************************************************** - * Name: stm32_spi1cmddata - * - * Description: - * Set or clear the SH1101A A0 or SD1306 D/C n bit to select data (true) - * or command (false). This function must be provided by platform-specific - * logic. This is an implementation of the cmddata method of the SPI - * interface defined by struct spi_ops_s (see include/nuttx/spi/spi.h). - * - * Input Parameters: - * - * spi - SPI device that controls the bus the device that requires the CMD/ - * DATA selection. - * devid - If there are multiple devices on the bus, this selects which one - * to select cmd or data. NOTE: This design restricts, for example, - * one one SPI display per SPI bus. - * cmd - true: select command; false: select data - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef CONFIG_SPI_CMDDATA -#ifdef CONFIG_STM32_SPI1 -int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, - bool cmd) -{ -#ifdef CONFIG_LCD_ST7567 - if (devid == SPIDEV_DISPLAY(0)) - { - /* This is the Data/Command control pad which determines whether the - * data bits are data or a command. - */ - - stm32_gpiowrite(STM32_LCD_RS, !cmd); - - return OK; - } -#endif - -#ifdef CONFIG_LCD_PCD8544 - if (devid == SPIDEV_DISPLAY(0)) - { - /* This is the Data/Command control pad which determines whether the - * data bits are data or a command. - */ - - stm32_gpiowrite(STM32_LCD_CD, !cmd); - - return OK; - } -#endif - - return -ENODEV; -} -#endif -#endif - -#endif /* CONFIG_STM32_SPI1 || CONFIG_STM32_SPI2 */ diff --git a/boards/arm/stm32/olimex-stm32-e407/src/stm32_timer.c b/boards/arm/stm32/olimex-stm32-e407/src/stm32_timer.c deleted file mode 100644 index 5bc17c864d089..0000000000000 --- a/boards/arm/stm32/olimex-stm32-e407/src/stm32_timer.c +++ /dev/null @@ -1,63 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/olimex-stm32-e407/src/stm32_timer.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include - -#include - -#include "stm32_tim.h" -#include "olimex-stm32-e407.h" - -#ifdef CONFIG_TIMER - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_timer_driver_setup - * - * Description: - * Configure the timer driver. - * - * Input Parameters: - * devpath - The full path to the timer device. This should be of the - * form /dev/timer0 - * timer - The timer's number. - * - * Returned Values: - * Zero (OK) is returned on success; A negated errno value is returned - * to indicate the nature of any failure. - * - ****************************************************************************/ - -int stm32_timer_driver_setup(const char *devpath, int timer) -{ - return stm32_timer_initialize(devpath, timer); -} - -#endif diff --git a/boards/arm/stm32/olimex-stm32-e407/src/stm32_usb.c b/boards/arm/stm32/olimex-stm32-e407/src/stm32_usb.c deleted file mode 100644 index 4df415385ef59..0000000000000 --- a/boards/arm/stm32/olimex-stm32-e407/src/stm32_usb.c +++ /dev/null @@ -1,329 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/olimex-stm32-e407/src/stm32_usb.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -#include "arm_internal.h" -#include "stm32.h" -#include "stm32_otgfs.h" -#include "olimex-stm32-e407.h" - -#ifdef CONFIG_STM32_OTGFS - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#if defined(CONFIG_USBDEV) || defined(CONFIG_USBHOST) -# define HAVE_USB 1 -#else -# warning "CONFIG_STM32_OTGFS is enabled but neither CONFIG_USBDEV nor CONFIG_USBHOST" -# undef HAVE_USB -#endif - -#ifndef CONFIG_STM32F4DISCO_USBHOST_PRIO -# define CONFIG_STM32F4DISCO_USBHOST_PRIO 100 -#endif - -#ifndef CONFIG_STM32F4DISCO_USBHOST_STACKSIZE -# define CONFIG_STM32F4DISCO_USBHOST_STACKSIZE 1024 -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -#ifdef CONFIG_USBHOST -static struct usbhost_connection_s *g_usbconn; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: usbhost_waiter - * - * Description: - * Wait for USB devices to be connected. - * - ****************************************************************************/ - -#ifdef CONFIG_USBHOST -static int usbhost_waiter(int argc, char *argv[]) -{ - struct usbhost_hubport_s *hport; - - uinfo("Running\n"); - for (; ; ) - { - /* Wait for the device to change state */ - - DEBUGVERIFY(CONN_WAIT(g_usbconn, &hport)); - uinfo("%s\n", hport->connected ? "connected" : "disconnected"); - - /* Did we just become connected? */ - - if (hport->connected) - { - /* Yes.. enumerate the newly connected device */ - - CONN_ENUMERATE(g_usbconn, hport); - } - } - - /* Keep the compiler from complaining */ - - return 0; -} -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_usbinitialize - * - * Description: - * Called from stm32_usbinitialize very early in initialization to setup - * USB-related GPIO pins for the STM32F4Discovery board. - * - ****************************************************************************/ - -void stm32_usbinitialize(void) -{ - /* The OTG FS has an internal soft pull-up. - * No GPIO configuration is required - */ - - /* Configure the OTG FS VBUS sensing GPIO, - * Power On, and Overcurrent GPIOs - */ - -#ifdef CONFIG_STM32_OTGFS - stm32_configgpio(GPIO_OTGFS_VBUS); - stm32_configgpio(GPIO_OTGFS_PWRON); - stm32_configgpio(GPIO_OTGFS_OVER); -#endif -} - -/**************************************************************************** - * Name: stm32_usbhost_initialize - * - * Description: - * Called at application startup time to initialize the USB host - * functionality. This function will start a thread that will monitor - * for device connection/disconnection events. - * - ****************************************************************************/ - -#ifdef CONFIG_USBHOST -int stm32_usbhost_initialize(void) -{ - int ret; - - /* First, register all of the class drivers needed to support the drivers - * that we care about: - */ - - uvdbg("Register class drivers\n"); - -#ifdef CONFIG_USBHOST_HUB - /* Initialize USB hub class support */ - - ret = usbhost_hub_initialize(); - if (ret < 0) - { - uerr("ERROR: usbhost_hub_initialize failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_USBHOST_MSC - /* Register the USB mass storage class class */ - - ret = usbhost_msc_initialize(); - if (ret != OK) - { - uerr("ERROR: Failed to register the mass storage class: %d\n", ret); - } -#endif - -#ifdef CONFIG_USBHOST_CDCACM - /* Register the CDC/ACM serial class */ - - ret = usbhost_cdcacm_initialize(); - if (ret != OK) - { - uerr("ERROR: Failed to register the CDC/ACM serial class: %d\n", ret); - } -#endif - -#ifdef CONFIG_USBHOST_HIDKBD - /* Initialize the HID keyboard class */ - - ret = usbhost_kbdinit(); - if (ret != OK) - { - uerr("Failed to register the HID keyboard class\n"); - } -#endif - -#ifdef CONFIG_USBHOST_HIDMOUSE - /* Initialize the HID mouse class */ - - ret = usbhost_mouse_init(); - if (ret != OK) - { - uerr("Failed to register the HID mouse class\n"); - } -#endif - - /* Then get an instance of the USB host interface */ - - uinfo("Initialize USB host\n"); - g_usbconn = stm32_otgfshost_initialize(0); - if (g_usbconn) - { - /* Start a thread to handle device connection. */ - - uinfo("Start usbhost_waiter\n"); - - ret = kthread_create("usbhost", CONFIG_STM32F4DISCO_USBHOST_PRIO, - CONFIG_STM32F4DISCO_USBHOST_STACKSIZE, - usbhost_waiter, NULL); - return ret < 0 ? -ENOEXEC : OK; - } - - return -ENODEV; -} -#endif - -/**************************************************************************** - * Name: stm32_usbhost_vbusdrive - * - * Description: - * Enable/disable driving of VBUS 5V output. This function must be - * provided be each platform that implements the STM32 OTG FS host - * interface - * - * "On-chip 5 V VBUS generation is not supported. For this reason, a - * charge pump or, if 5 V are available on the application board, a - * basic power switch, must be added externally to drive the 5 V VBUS - * line. The external charge pump can be driven by any GPIO output. - * When the application decides to power on VBUS using the chosen GPIO, - * it must also set the port power bit in the host port control and - * status register (PPWR bit in OTG_FS_HPRT). - * - * "The application uses this field to control power to this port, andi - * the core clears this bit on an overcurrent condition." - * - * Input Parameters: - * iface - For future growth to handle multiple USB host interface. - * Should be zero. - * enable - true: enable VBUS power; false: disable VBUS power - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef CONFIG_USBHOST -void stm32_usbhost_vbusdrive(int iface, bool enable) -{ - DEBUGASSERT(iface == 0); - - if (enable) - { - /* Enable the Power Switch by driving the enable pin low */ - - stm32_gpiowrite(GPIO_OTGFS_PWRON, false); - } - else - { - /* Disable the Power Switch by driving the enable pin high */ - - stm32_gpiowrite(GPIO_OTGFS_PWRON, true); - } -} -#endif - -/**************************************************************************** - * Name: stm32_setup_overcurrent - * - * Description: - * Setup to receive an interrupt-level callback if an overcurrent - * condition is detected. - * - * Input Parameters: - * handler - New overcurrent interrupt handler - * arg - The argument provided for the interrupt handler - * - * Returned Value: - * Zero (OK) is returned on success. Otherwise, a negated errno value is - * returned to indicate the nature of the failure. - * - ****************************************************************************/ - -#ifdef CONFIG_USBHOST -int stm32_setup_overcurrent(xcpt_t handler, void *arg) -{ - return stm32_gpiosetevent(GPIO_OTGFS_OVER, true, true, true, handler, arg); -} -#endif - -/**************************************************************************** - * Name: stm32_usbsuspend - * - * Description: - * Board logic must provide the stm32_usbsuspend logic if the USBDEV - * driver is used. This function is called whenever the USB enters or - * leaves suspend mode. This is an opportunity for the board logic to - * shutdown clocks, power, etc. while the USB is suspended. - * - ****************************************************************************/ - -#ifdef CONFIG_USBDEV -void stm32_usbsuspend(struct usbdev_s *dev, bool resume) -{ - uinfo("resume: %d\n", resume); -} -#endif - -#endif /* CONFIG_STM32_OTGFS */ diff --git a/boards/arm/stm32/olimex-stm32-e407/src/stm32_userleds.c b/boards/arm/stm32/olimex-stm32-e407/src/stm32_userleds.c deleted file mode 100644 index d9e198ee1993f..0000000000000 --- a/boards/arm/stm32/olimex-stm32-e407/src/stm32_userleds.c +++ /dev/null @@ -1,95 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/olimex-stm32-e407/src/stm32_userleds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32.h" -#include "olimex-stm32-e407.h" - -#ifndef CONFIG_ARCH_LEDS - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* This array maps an LED number to GPIO pin configuration */ - -static uint32_t g_ledcfg[BOARD_NLEDS] = -{ - GPIO_LED_STATUS -}; - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_userled_initialize - ****************************************************************************/ - -uint32_t board_userled_initialize(void) -{ - /* Configure LED1-4 GPIOs for output */ - - stm32_configgpio(GPIO_LED_STATUS); - return BOARD_NLEDS; -} - -/**************************************************************************** - * Name: board_userled - ****************************************************************************/ - -void board_userled(int led, bool ledon) -{ - if ((unsigned)led < BOARD_NLEDS) - { - stm32_gpiowrite(g_ledcfg[led], ledon); - } -} - -/**************************************************************************** - * Name: board_userled_all - ****************************************************************************/ - -void board_userled_all(uint32_t ledset) -{ - stm32_gpiowrite(GPIO_LED_STATUS, (ledset & BOARD_LED1_BIT) != 0); -} - -#endif /* !CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/olimex-stm32-h405/CMakeLists.txt b/boards/arm/stm32/olimex-stm32-h405/CMakeLists.txt deleted file mode 100644 index 58cb6b3682885..0000000000000 --- a/boards/arm/stm32/olimex-stm32-h405/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/olimex-stm32-h405/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32/olimex-stm32-h405/configs/usbnsh/defconfig b/boards/arm/stm32/olimex-stm32-h405/configs/usbnsh/defconfig deleted file mode 100644 index 302f0bd148fb0..0000000000000 --- a/boards/arm/stm32/olimex-stm32-h405/configs/usbnsh/defconfig +++ /dev/null @@ -1,67 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_DEV_CONSOLE is not set -# CONFIG_NSH_DISABLE_IFCONFIG is not set -# CONFIG_NSH_DISABLE_PS is not set -CONFIG_ADC=y -CONFIG_ANALOG=y -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="olimex-stm32-h405" -CONFIG_ARCH_BOARD_OLIMEX_STM32H405=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F405RG=y -CONFIG_ARCH_IRQBUTTONS=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_ARM_TOOLCHAIN_BUILDROOT=y -CONFIG_BOARDCTL_USBDEVCTRL=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_CDCACM=y -CONFIG_CDCACM_CONSOLE=y -CONFIG_CDCACM_RXBUFSIZE=256 -CONFIG_CDCACM_TXBUFSIZE=256 -CONFIG_DEBUG_SYMBOLS=y -CONFIG_EXAMPLES_ADC=y -CONFIG_EXAMPLES_CAN=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_MM_REGIONS=2 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_DISABLE_GET=y -CONFIG_NSH_DISABLE_PUT=y -CONFIG_NSH_DISABLE_WGET=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_HPWORKPRIORITY=192 -CONFIG_SCHED_WAITPID=y -CONFIG_START_YEAR=2013 -CONFIG_STM32_ADC1=y -CONFIG_STM32_CAN1=y -CONFIG_STM32_CAN_TSEG2=8 -CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_OTGFS=y -CONFIG_STM32_PWR=y -CONFIG_STM32_TIM1=y -CONFIG_STM32_TIM1_ADC=y -CONFIG_STM32_USART3=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USBDEV=y diff --git a/boards/arm/stm32/olimex-stm32-h405/include/board.h b/boards/arm/stm32/olimex-stm32-h405/include/board.h deleted file mode 100644 index 81bdf2420020d..0000000000000 --- a/boards/arm/stm32/olimex-stm32-h405/include/board.h +++ /dev/null @@ -1,187 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/olimex-stm32-h405/include/board.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __BOARDS_ARM_STM32_OLIMEX_STM32_H405_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32_OLIMEX_STM32_H405_INCLUDE_BOARD_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#ifndef __ASSEMBLY__ -# include -#endif - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Clocking *****************************************************************/ - -/* HSI - 16 MHz RC factory-trimmed - * LSI - 32 KHz RC (30-60KHz, uncalibrated) - * HSE - On-board crystal frequency is 8MHz - * LSE - 32.768 kHz - */ - -#define STM32_BOARD_XTAL 8000000ul - -#define STM32_HSI_FREQUENCY 16000000ul -#define STM32_LSI_FREQUENCY 32000 -#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL -#define STM32_LSE_FREQUENCY 32768 - -/* Main PLL Configuration. - * - * PLL source is HSE - * PLL_VCO = (STM32_HSE_FREQUENCY / PLLM) * PLLN - * = (25,000,000 / 12) * 360 - * = 240,000,000 - * SYSCLK = PLL_VCO / PLLP - * = 240,000,000 / 2 = 120,000,000 - * USB OTG FS, SDIO and RNG Clock - * = PLL_VCO / PLLQ - * = 240,000,000 / 5 = 48,000,000 - * = 48,000,000 - */ - -#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(12) -#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(360) -#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_2 -#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(5) - -#define STM32_SYSCLK_FREQUENCY 120000000ul - -/* AHB clock (HCLK) is SYSCLK (120MHz) */ - -#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ -#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY - -/* APB1 clock (PCLK1) is HCLK/4 (30MHz) */ - -#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd4 /* PCLK1 = HCLK / 4 */ -#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/4) - -/* Timers driven from APB1 will be twice PCLK1 (60Mhz) */ - -#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) - -/* APB2 clock (PCLK2) is HCLK/2 (60MHz) */ - -#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLKd2 /* PCLK2 = HCLK / 2 */ -#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/2) - -/* Timers driven from APB2 will be twice PCLK2 (120Mhz) */ - -#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM9_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM10_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM11_CLKIN (2*STM32_PCLK2_FREQUENCY) - -/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx - * otherwise frequency is 2xAPBx. - * Note: TIM1,8 are on APB2, others on APB1 - */ - -#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM2_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM3_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM4_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM5_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM6_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM7_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY - -/* LED definitions **********************************************************/ - -/* If CONFIG_ARCH_LEDS is not defined, then the user can control the status - * LED in any way. - * The following definitions are used to access individual LEDs. - */ - -/* LED index values for use with board_userled() */ - -#define BOARD_LED_STATUS 0 -#define BOARD_NLEDS 1 - -/* LED bits for use with board_userled_all() */ - -#define BOARD_LED_STATUS_BIT (1 << BOARD_LED1) - -/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the status LED of - * the Olimex STM32-H405. - * The following definitions describe how NuttX controls the LEDs: - */ - -#define LED_STARTED 0 /* LED_STATUS on */ -#define LED_HEAPALLOCATE 1 /* no change */ -#define LED_IRQSENABLED 2 /* no change */ -#define LED_STACKCREATED 3 /* no change */ -#define LED_INIRQ 4 /* no change */ -#define LED_SIGNAL 5 /* no change */ -#define LED_ASSERTION 6 /* LED_STATUS off */ -#define LED_PANIC 7 /* LED_STATUS blinking */ - -/* Button definitions *******************************************************/ - -/* The Olimex STM32-H405 supports one buttons: */ - -#define BUTTON_BUT 0 -#define NUM_BUTTONS 1 - -#define BUTTON_BUT_BIT (1 << BUTTON_BUT) - -/* Alternate function pin selections ****************************************/ - -/* USART3: */ - -#define GPIO_USART3_RX (GPIO_USART3_RX_1|GPIO_SPEED_100MHz) /* PB11 */ -#define GPIO_USART3_TX (GPIO_USART3_TX_1|GPIO_SPEED_100MHz) /* PB10 */ -#define GPIO_USART3_CTS GPIO_USART3_CTS_1 /* PB13 */ -#define GPIO_USART3_RTS GPIO_USART3_RTS_1 /* PB14 */ - -/* CAN: */ - -#define GPIO_CAN1_RX (GPIO_CAN1_RX_2|GPIO_SPEED_50MHz) /* PB8 */ -#define GPIO_CAN1_TX (GPIO_CAN1_TX_2|GPIO_SPEED_50MHz) /* PB9 */ -#define GPIO_CAN2_RX (GPIO_CAN1_RX_2|GPIO_SPEED_50MHz) /* PB5 */ -#define GPIO_CAN2_TX (GPIO_CAN1_TX_2|GPIO_SPEED_50MHz) /* PB6 */ - -/* USB OTG FS */ - -#define GPIO_OTGFS_DM (GPIO_OTGFS_DM_0|GPIO_SPEED_100MHz) -#define GPIO_OTGFS_DP (GPIO_OTGFS_DP_0|GPIO_SPEED_100MHz) -#define GPIO_OTGFS_ID (GPIO_OTGFS_ID_0|GPIO_SPEED_100MHz) -#define GPIO_OTGFS_SOF (GPIO_OTGFS_SOF_0|GPIO_SPEED_100MHz) - -#endif /* __BOARDS_ARM_STM32_OLIMEX_STM32_H405_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32/olimex-stm32-h405/scripts/Make.defs b/boards/arm/stm32/olimex-stm32-h405/scripts/Make.defs deleted file mode 100644 index ecd20a669ce6a..0000000000000 --- a/boards/arm/stm32/olimex-stm32-h405/scripts/Make.defs +++ /dev/null @@ -1,41 +0,0 @@ -############################################################################ -# boards/arm/stm32/olimex-stm32-h405/scripts/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/.config -include $(TOPDIR)/tools/Config.mk -include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs - -LDSCRIPT = ld.script -ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) - -ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 - -CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) -CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) -CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -AFLAGS := $(CFLAGS) -D__ASSEMBLY__ - -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-gotoff.ld -no-check-sections -LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32/olimex-stm32-h405/scripts/ld.script b/boards/arm/stm32/olimex-stm32-h405/scripts/ld.script deleted file mode 100644 index 37a944a3efbba..0000000000000 --- a/boards/arm/stm32/olimex-stm32-h405/scripts/ld.script +++ /dev/null @@ -1,126 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/olimex-stm32-h405/scripts/ld.script - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* The STM32F405RGT6 has 1024Kb of FLASH beginning at address 0x0800:0000 and - * 192Kb of SRAM. SRAM is split up into two blocks: - * - * 1) 112Kb of SRAM beginning at address 0x2000:0000 - * 2) 16Kb of SRAM beginning at address 0x2001:c000 - * 3) 64Kb of SRAM beginning at address 0x2002:0000 - * - * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 - * where the code expects to begin execution by jumping to the entry point in - * the 0x0800:0000 address - * range. - */ - -MEMORY -{ - flash (rx) : ORIGIN = 0x08000000, LENGTH = 1024K - sram (rwx) : ORIGIN = 0x20000000, LENGTH = 112K -} - -OUTPUT_ARCH(arm) -EXTERN(_vectors) -ENTRY(_stext) -SECTIONS -{ - .text : { - _stext = ABSOLUTE(.); - *(.vectors) - *(.text .text.*) - *(.fixup) - *(.gnu.warning) - *(.rodata .rodata.*) - *(.gnu.linkonce.t.*) - *(.glue_7) - *(.glue_7t) - *(.got) - *(.gcc_except_table) - *(.gnu.linkonce.r.*) - _etext = ABSOLUTE(.); - } > flash - - .init_section : ALIGN(4) { - _sinit = ABSOLUTE(.); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) - KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) - _einit = ABSOLUTE(.); - } > flash - - .ARM.extab : ALIGN(4) { - *(.ARM.extab*) - } > flash - - .ARM.exidx : ALIGN(4) { - __exidx_start = ABSOLUTE(.); - *(.ARM.exidx*) - __exidx_end = ABSOLUTE(.); - } > flash - - .tdata : { - _stdata = ABSOLUTE(.); - *(.tdata .tdata.* .gnu.linkonce.td.*); - _etdata = ABSOLUTE(.); - } > flash - - .tbss : { - _stbss = ABSOLUTE(.); - *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); - _etbss = ABSOLUTE(.); - } > flash - - _eronly = ABSOLUTE(.); - - .data : ALIGN(4) { - _sdata = ABSOLUTE(.); - *(.data .data.*) - *(.gnu.linkonce.d.*) - CONSTRUCTORS - . = ALIGN(4); - _edata = ABSOLUTE(.); - } > sram AT > flash - - .bss : ALIGN(4) { - _sbss = ABSOLUTE(.); - *(.bss .bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - . = ALIGN(4); - _ebss = ABSOLUTE(.); - } > sram - - /* Stabs debugging sections. */ - - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_info 0 : { *(.debug_info) } - .debug_line 0 : { *(.debug_line) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_aranges 0 : { *(.debug_aranges) } -} diff --git a/boards/arm/stm32/olimex-stm32-h405/src/CMakeLists.txt b/boards/arm/stm32/olimex-stm32-h405/src/CMakeLists.txt deleted file mode 100644 index 0fb338eadb597..0000000000000 --- a/boards/arm/stm32/olimex-stm32-h405/src/CMakeLists.txt +++ /dev/null @@ -1,49 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/olimex-stm32-h405/src/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -set(SRCS stm32_boot.c) - -if(CONFIG_ARCH_LEDS) - list(APPEND SRCS stm32_autoleds.c) -else() - list(APPEND SRCS stm32_userleds.c) -endif() - -if(CONFIG_ARCH_BUTTONS) - list(APPEND SRCS stm32_buttons.c) -endif() - -if(CONFIG_STM32_OTGFS) - list(APPEND SRCS stm32_usb.c) -endif() - -if(CONFIG_ADC) - list(APPEND SRCS stm32_adc.c) -endif() - -if(CONFIG_STM32_CAN_CHARDRIVER) - list(APPEND SRCS stm32_can.c) -endif() - -target_sources(board PRIVATE ${SRCS}) - -set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/ld.script") diff --git a/boards/arm/stm32/olimex-stm32-h405/src/Make.defs b/boards/arm/stm32/olimex-stm32-h405/src/Make.defs deleted file mode 100644 index 82df67a1c2ddd..0000000000000 --- a/boards/arm/stm32/olimex-stm32-h405/src/Make.defs +++ /dev/null @@ -1,51 +0,0 @@ -############################################################################ -# boards/arm/stm32/olimex-stm32-h405/src/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/Make.defs - -CSRCS = stm32_boot.c - -ifeq ($(CONFIG_ARCH_LEDS),y) -CSRCS += stm32_autoleds.c -else -CSRCS += stm32_userleds.c -endif - -ifeq ($(CONFIG_ARCH_BUTTONS),y) -CSRCS += stm32_buttons.c -endif - -ifeq ($(CONFIG_STM32_OTGFS),y) -CSRCS += stm32_usb.c -endif - -ifeq ($(CONFIG_ADC),y) -CSRCS += stm32_adc.c -endif - -ifeq ($(CONFIG_STM32_CAN_CHARDRIVER),y) -CSRCS += stm32_can.c -endif - -DEPPATH += --dep-path board -VPATH += :board -CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/olimex-stm32-h405/src/stm32_adc.c b/boards/arm/stm32/olimex-stm32-h405/src/stm32_adc.c deleted file mode 100644 index f741f3255f9f7..0000000000000 --- a/boards/arm/stm32/olimex-stm32-h405/src/stm32_adc.c +++ /dev/null @@ -1,170 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/olimex-stm32-h405/src/stm32_adc.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include -#include - -#include "chip.h" -#include "stm32_adc.h" -#include "olimex-stm32-h405.h" - -#ifdef CONFIG_ADC - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -/* Up to 3 ADC interfaces are supported */ - -#if STM32_NADC < 3 -# undef CONFIG_STM32_ADC3 -#endif - -#if STM32_NADC < 2 -# undef CONFIG_STM32_ADC2 -#endif - -#if STM32_NADC < 1 -# undef CONFIG_STM32_ADC1 -#endif - -#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) || defined(CONFIG_STM32_ADC3) -#ifndef CONFIG_STM32_ADC1 -# warning "Channel information only available for ADC1" -#endif - -/* The number of ADC channels in the conversion list */ - -#define ADC1_NCHANNELS 1//14 - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* The Olimex STM32-P405 has a 10 Kohm potentiometer AN_TR connected to PC0 - * ADC123_IN10 - */ - -/* Identifying number of each ADC channel: Variable Resistor. */ - -#ifdef CONFIG_STM32_ADC1 -static const uint8_t g_chanlist[ADC1_NCHANNELS] = -{ - 1 -}; -/* , 2, 3, - * 4, 5, 6, - * 7, 8, 9, - * 10, 11, 12, - * 13, 15 - * }; - */ - -/* Configurations of pins used byte each ADC channels */ - -static const uint32_t g_pinlist[ADC1_NCHANNELS] = -{ - GPIO_ADC1_IN1_0 -}; -/* , GPIO_ADC1_IN2_0, GPIO_ADC1_IN3_0, - * GPIO_ADC1_IN4_0, GPIO_ADC1_IN5_0, GPIO_ADC1_IN6_0, - * GPIO_ADC1_IN7_0, GPIO_ADC1_IN8_0, GPIO_ADC1_IN9_0, - * GPIO_ADC1_IN10_0, GPIO_ADC1_IN11_0, GPIO_ADC1_IN12_0, - * GPIO_ADC1_IN13_0, GPIO_ADC1_IN15_0 - * }; - */ -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_adc_setup - * - * Description: - * Initialize ADC and register the ADC driver. - * - ****************************************************************************/ - -int stm32_adc_setup(void) -{ -#ifdef CONFIG_STM32_ADC1 - static bool initialized = false; - struct adc_dev_s *adc; - int ret; - int i; - - /* Check if we have already initialized */ - - if (!initialized) - { - /* Configure the pins as analog inputs for the selected channels */ - - for (i = 0; i < ADC1_NCHANNELS; i++) - { - stm32_configgpio(g_pinlist[i]); - } - - /* Call stm32_adcinitialize() to get an instance of the ADC interface */ - - adc = stm32_adcinitialize(1, g_chanlist, ADC1_NCHANNELS); - if (adc == NULL) - { - aerr("ERROR: Failed to get ADC interface\n"); - return -ENODEV; - } - - /* Register the ADC driver at "/dev/adc0" */ - - ret = adc_register("/dev/adc0", adc); - if (ret < 0) - { - aerr("ERROR: adc_register failed: %d\n", ret); - return ret; - } - - /* Now we are initialized */ - - initialized = true; - } - - return OK; -#else - return -ENOSYS; -#endif -} - -#endif /* CONFIG_STM32_ADC1 || CONFIG_STM32_ADC2 || CONFIG_STM32_ADC3 */ -#endif /* CONFIG_ADC */ diff --git a/boards/arm/stm32/olimex-stm32-h405/src/stm32_autoleds.c b/boards/arm/stm32/olimex-stm32-h405/src/stm32_autoleds.c deleted file mode 100644 index 7dc946d460e4e..0000000000000 --- a/boards/arm/stm32/olimex-stm32-h405/src/stm32_autoleds.c +++ /dev/null @@ -1,90 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/olimex-stm32-h405/src/stm32_autoleds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include "stm32.h" -#include "olimex-stm32-h405.h" - -#ifdef CONFIG_ARCH_LEDS - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_autoled_initialize - ****************************************************************************/ - -void board_autoled_initialize(void) -{ - /* Configure LED_STATUS GPIO for output */ - - stm32_configgpio(GPIO_LED_STATUS); -} - -/**************************************************************************** - * Name: board_autoled_on - ****************************************************************************/ - -void board_autoled_on(int led) -{ - if (led == LED_STARTED) - { - stm32_gpiowrite(GPIO_LED_STATUS, true); - } - - if (led == LED_ASSERTION || led == LED_PANIC) - { - stm32_gpiowrite(GPIO_LED_STATUS, false); - } -} - -/**************************************************************************** - * Name: board_autoled_off - ****************************************************************************/ - -void board_autoled_off(int led) -{ - if (led == LED_STARTED) - { - stm32_gpiowrite(GPIO_LED_STATUS, false); - } - - if (led == LED_ASSERTION || led == LED_PANIC) - { - stm32_gpiowrite(GPIO_LED_STATUS, true); - } -} - -#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/olimex-stm32-h405/src/stm32_boot.c b/boards/arm/stm32/olimex-stm32-h405/src/stm32_boot.c deleted file mode 100644 index f7b9a5410e369..0000000000000 --- a/boards/arm/stm32/olimex-stm32-h405/src/stm32_boot.c +++ /dev/null @@ -1,142 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/olimex-stm32-h405/src/stm32_boot.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include -#include -#include -#include - -#include -#include -#include - -#ifdef CONFIG_USBMONITOR -# include -#endif - -#ifdef CONFIG_STM32_OTGFS -# include "stm32_usbhost.h" -#endif - -#include "stm32.h" -#include "olimex-stm32-h405.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#if !defined(CONFIG_STM32_CAN1) && !defined(CONFIG_STM32_CAN2) -# undef CONFIG_CAN -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_boardinitialize - * - * Description: - * All STM32 architectures must provide the following entry point. - * This entry point is called early in the initialization -- after all - * memory has been configured and mapped but before any devices have been - * initialized. - * - ****************************************************************************/ - -void stm32_boardinitialize(void) -{ - /* Initialize USB if the 1) OTG FS controller is in the configuration and - * 2) disabled, and 3) the weak function stm32_usbinitialize() has been - * brought into the build. Presumably either CONFIG_USBDEV is also - * selected. - */ - -#ifdef CONFIG_STM32_OTGFS - if (stm32_usbinitialize) - { - stm32_usbinitialize(); - } -#endif - - /* Configure on-board LEDs if LED support has been selected. */ - -#ifdef CONFIG_ARCH_LEDS - board_autoled_initialize(); -#endif - - /* Configure on-board BUTTONs if BUTTON support has been selected. */ - -#ifdef CONFIG_ARCH_BUTTONS - board_button_initialize(); -#endif -} - -/**************************************************************************** - * Name: board_late_initialize - * - * Description: - * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional - * initialization call will be performed in the boot-up sequence to a - * function called board_late_initialize(). board_late_initialize() will be - * called immediately after up_intitialize() is called and just before the - * initial application is started. This additional initialization phase - * may be used, for example, to initialize board-specific device drivers. - * - ****************************************************************************/ - -#ifdef CONFIG_BOARD_LATE_INITIALIZE -void board_late_initialize(void) -{ - int ret; - -#ifdef CONFIG_ADC - /* Initialize ADC and register the ADC driver. */ - - ret = stm32_adc_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_adc_setup failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_STM32_CAN_CHARDRIVER - /* Initialize CAN and register the CAN driver. */ - - ret = stm32_can_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_can_setup failed: %d\n", ret); - } -#endif - - UNUSED(ret); -} -#endif diff --git a/boards/arm/stm32/olimex-stm32-h405/src/stm32_buttons.c b/boards/arm/stm32/olimex-stm32-h405/src/stm32_buttons.c deleted file mode 100644 index 5a2e348ea2e84..0000000000000 --- a/boards/arm/stm32/olimex-stm32-h405/src/stm32_buttons.c +++ /dev/null @@ -1,140 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/olimex-stm32-h405/src/stm32_buttons.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include -#include - -#include "olimex-stm32-h405.h" - -#ifdef CONFIG_ARCH_BUTTONS - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* Pin configuration for each Olimex-STM32-H405 button. This array is indexed - * by the BUTTON_* definitions in board.h - */ - -static const uint32_t g_buttons[NUM_BUTTONS] = -{ - GPIO_BTN_BUT -}; - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_button_initialize - * - * Description: - * board_button_initialize() must be called to initialize button resources. - * After that, board_buttons() may be called to collect the current state - * of all buttons or board_button_irq() may be called to register button - * interrupt handlers. - * - ****************************************************************************/ - -uint32_t board_button_initialize(void) -{ - int i; - - /* Configure the GPIO pins as inputs. NOTE that EXTI interrupts are - * configured for all pins. - */ - - for (i = 0; i < NUM_BUTTONS; i++) - { - stm32_configgpio(g_buttons[i]); - } - - return NUM_BUTTONS; -} - -/**************************************************************************** - * Name: board_buttons - ****************************************************************************/ - -uint32_t board_buttons(void) -{ - uint32_t ret = 0; - - /* Check that state of each key */ - - if (!stm32_gpioread(g_buttons[BUTTON_BUT])) - { - ret |= BUTTON_BUT_BIT; - } - - return ret; -} - -/**************************************************************************** - * Button support. - * - * Description: - * board_button_initialize() must be called to initialize button resources. - * After that, board_buttons() may be called to collect the current state - * of all buttons or board_button_irq() may be called to register button - * interrupt handlers. - * - * After board_button_initialize() has been called, board_buttons() may be - * called to collect the state of all buttons. board_buttons() returns an - * 32-bit bit set with each bit associated with a button. See the - * BUTTON_*_BIT definitions in board.h for the meaning of each bit. - * - * board_button_irq() may be called to register an interrupt handler that - * will be called when a button is depressed or released. The ID value is a - * button enumeration value that uniquely identifies a button resource. See - * the BUTTON_* definitions in board.h for the meaning of enumeration - * value. - * - ****************************************************************************/ - -#ifdef CONFIG_ARCH_IRQBUTTONS -int board_button_irq(int id, xcpt_t irqhandler, void *arg) -{ - int ret = -EINVAL; - - /* The following should be atomic */ - - if (id >= MIN_IRQBUTTON && id <= MAX_IRQBUTTON) - { - ret = stm32_gpiosetevent(g_buttons[id], true, true, true, - irqhandler, arg); - } - - return ret; -} -#endif -#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/stm32/olimex-stm32-h405/src/stm32_can.c b/boards/arm/stm32/olimex-stm32-h405/src/stm32_can.c deleted file mode 100644 index 64bbe3f5b0cfe..0000000000000 --- a/boards/arm/stm32/olimex-stm32-h405/src/stm32_can.c +++ /dev/null @@ -1,101 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/olimex-stm32-h405/src/stm32_can.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include - -#include - -#include "stm32.h" -#include "stm32_can.h" -#include "olimex-stm32-h405.h" - -#ifdef CONFIG_CAN - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -#if defined(CONFIG_STM32_CAN1) && defined(CONFIG_STM32_CAN2) -# warning "Both CAN1 and CAN2 are enabled. Only CAN1 is used." -# undef CONFIG_STM32_CAN2 -#endif - -#ifdef CONFIG_STM32_CAN1 -# define CAN_PORT 1 -#else -# define CAN_PORT 2 -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_can_setup - * - * Description: - * Initialize CAN and register the CAN device - * - ****************************************************************************/ - -int stm32_can_setup(void) -{ -#if defined(CONFIG_STM32_CAN1) || defined(CONFIG_STM32_CAN2) - struct can_dev_s *can; - int ret; - - /* Call stm32_caninitialize() to get an instance of the CAN interface */ - - can = stm32_caninitialize(CAN_PORT); - if (can == NULL) - { - canerr("ERROR: Failed to get CAN interface\n"); - return -ENODEV; - } - - /* Register the CAN driver at "/dev/can0" */ - - ret = can_register("/dev/can0", can); - if (ret < 0) - { - canerr("ERROR: can_register failed: %d\n", ret); - return ret; - } - - return OK; -#else - return -ENODEV; -#endif -} - -#endif /* CONFIG_CAN */ diff --git a/boards/arm/stm32/olimex-stm32-h405/src/stm32_usb.c b/boards/arm/stm32/olimex-stm32-h405/src/stm32_usb.c deleted file mode 100644 index ce10acef66425..0000000000000 --- a/boards/arm/stm32/olimex-stm32-h405/src/stm32_usb.c +++ /dev/null @@ -1,108 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/olimex-stm32-h405/src/stm32_usb.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include - -#include -#include -#include -#include "stm32.h" -#include "stm32_otgfs.h" -#include "olimex-stm32-h405.h" - -#ifdef CONFIG_STM32_OTGFS - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#if defined(CONFIG_USBDEV) -# define HAVE_USB 1 -#else -# warning "CONFIG_STM32_OTGFS is enabled but not CONFIG_USBDEV" -# undef HAVE_USB -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_usbinitialize - * - * Description: - * Called from stm32_usbinitialize very early in initialization to setup - * USB-related GPIO pins for the STM32F4Discovery board. - * - ****************************************************************************/ - -void stm32_usbinitialize(void) -{ - /* The OTG FS has an internal soft pull-up. - * No GPIO configuration is required - */ - - /* Configure the OTG FS VBUS sensing GPIO */ - -#ifdef CONFIG_STM32_OTGFS - stm32_configgpio(GPIO_OTGFS_VBUS); -#endif -} - -/**************************************************************************** - * Name: stm32_usbsuspend - * - * Description: - * Board logic must provide the stm32_usbsuspend logic if the USBDEV - * driver is used. This function is called whenever the USB enters or - * leaves suspend mode. - * This is an opportunity for the board logic to shutdown clocks, power, - * etc. while the USB is suspended. - * - ****************************************************************************/ - -#ifdef CONFIG_USBDEV -void stm32_usbsuspend(struct usbdev_s *dev, bool resume) -{ - uinfo("resume: %d\n", resume); -} -#endif - -#endif /* CONFIG_STM32_OTGFS */ diff --git a/boards/arm/stm32/olimex-stm32-h405/src/stm32_userleds.c b/boards/arm/stm32/olimex-stm32-h405/src/stm32_userleds.c deleted file mode 100644 index 8b80592954273..0000000000000 --- a/boards/arm/stm32/olimex-stm32-h405/src/stm32_userleds.c +++ /dev/null @@ -1,86 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/olimex-stm32-h405/src/stm32_userleds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include "stm32.h" -#include "olimex-stm32-h405.h" - -#ifndef CONFIG_ARCH_LEDS - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* This array maps an LED number to GPIO pin configuration */ - -static uint32_t g_ledcfg[BOARD_NLEDS] = -{ - GPIO_LED_STATUS -}; - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_userled_initialize - ****************************************************************************/ - -uint32_t board_userled_initialize(void) -{ - /* Configure LED1-4 GPIOs for output */ - - stm32_configgpio(GPIO_LED_STATUS); - return BOARD_NLEDS; -} - -/**************************************************************************** - * Name: board_userled - ****************************************************************************/ - -void board_userled(int led, bool ledon) -{ - if ((unsigned)led < BOARD_NLEDS) - { - stm32_gpiowrite(g_ledcfg[led], ledon); - } -} - -/**************************************************************************** - * Name: board_userled_all - ****************************************************************************/ - -void board_userled_all(uint32_t ledset) -{ - stm32_gpiowrite(GPIO_LED_STATUS, (ledset & BOARD_LED1_BIT) != 0); -} - -#endif /* !CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/olimex-stm32-h407/CMakeLists.txt b/boards/arm/stm32/olimex-stm32-h407/CMakeLists.txt deleted file mode 100644 index 37624d8016fb5..0000000000000 --- a/boards/arm/stm32/olimex-stm32-h407/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/olimex-stm32-h407/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32/olimex-stm32-h407/configs/nsh/defconfig b/boards/arm/stm32/olimex-stm32-h407/configs/nsh/defconfig deleted file mode 100644 index b2e63d079be3f..0000000000000 --- a/boards/arm/stm32/olimex-stm32-h407/configs/nsh/defconfig +++ /dev/null @@ -1,49 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -# CONFIG_SPI_EXCHANGE is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="olimex-stm32-h407" -CONFIG_ARCH_BOARD_OLIMEX_STM32H407=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F407ZG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_DEBUG_FULLOPT=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_FS_PROCFS=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_MM_REGIONS=2 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_SPI=y -CONFIG_START_YEAR=2016 -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_OTGFS=y -CONFIG_STM32_PWR=y -CONFIG_STM32_USART2=y -CONFIG_SYSTEM_NSH=y -CONFIG_USART2_RXBUFSIZE=128 -CONFIG_USART2_SERIAL_CONSOLE=y -CONFIG_USART2_TXBUFSIZE=128 diff --git a/boards/arm/stm32/olimex-stm32-h407/configs/nsh_uext/defconfig b/boards/arm/stm32/olimex-stm32-h407/configs/nsh_uext/defconfig deleted file mode 100644 index 2095476d0ef07..0000000000000 --- a/boards/arm/stm32/olimex-stm32-h407/configs/nsh_uext/defconfig +++ /dev/null @@ -1,48 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -# CONFIG_SPI_EXCHANGE is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="olimex-stm32-h407" -CONFIG_ARCH_BOARD_OLIMEX_STM32H407=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F407ZG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_DEBUG_FULLOPT=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_FS_PROCFS=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_MM_REGIONS=2 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_SPI=y -CONFIG_START_YEAR=2016 -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_OTGFS=y -CONFIG_STM32_PWR=y -CONFIG_STM32_USART2=y -CONFIG_STM32_USART6=y -CONFIG_SYSTEM_NSH=y -CONFIG_USART2_RXBUFSIZE=128 -CONFIG_USART2_TXBUFSIZE=128 -CONFIG_USART6_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/olimex-stm32-h407/include/board.h b/boards/arm/stm32/olimex-stm32-h407/include/board.h deleted file mode 100644 index e585d6a451dd5..0000000000000 --- a/boards/arm/stm32/olimex-stm32-h407/include/board.h +++ /dev/null @@ -1,287 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/olimex-stm32-h407/include/board.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __BOARDS_ARM_STM32_OLIMEX_STM32_H407_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32_OLIMEX_STM32_H407_INCLUDE_BOARD_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#ifndef __ASSEMBLY__ -# include -# include -#endif - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Clocking *****************************************************************/ - -/* The Olimex-STM32-H407 board features a 12MHz crystal and - * a 32kHz RTC backup crystal. - * - * This is the canonical configuration: - * System Clock source : PLL (HSE) - * SYSCLK(Hz) : 168000000 Determined by PLL configuration - * HCLK(Hz) : 168000000 (STM32_RCC_CFGR_HPRE) - * AHB Prescaler : 1 (STM32_RCC_CFGR_HPRE) - * APB1 Prescaler : 4 (STM32_RCC_CFGR_PPRE1) - * APB2 Prescaler : 2 (STM32_RCC_CFGR_PPRE2) - * HSE Frequency(Hz) : 8000000 (STM32_BOARD_XTAL) - * PLLM : 8 (STM32_PLLCFG_PLLM) - * PLLN : 336 (STM32_PLLCFG_PLLN) - * PLLP : 2 (STM32_PLLCFG_PLLP) - * PLLQ : 7 (STM32_PLLCFG_PLLQ) - * Main regulator output - * voltage : Scale1 mode Needed for high speed SYSCLK - * Flash Latency(WS) : 5 - * Prefetch Buffer : OFF - * Instruction cache : ON - * Data cache : ON - * Require 48MHz for - * USB OTG FS, - * SDIO and RNG clock : Enabled - */ - -/* HSI - 16 MHz RC factory-trimmed - * LSI - 32 KHz RC (30-60KHz, uncalibrated) - * HSE - On-board crystal frequency is 12MHz - * LSE - 32.768 kHz - * STM32F407ZGT6 - too 168Mhz - */ - -#define STM32_BOARD_XTAL 12000000ul - -#define STM32_HSI_FREQUENCY 16000000ul -#define STM32_LSI_FREQUENCY 32000 -#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL -#define STM32_LSE_FREQUENCY 32768 - -/* Main PLL Configuration. - * - * PLL source is HSE - * PLL_VCO = (STM32_HSE_FREQUENCY / PLLM) * PLLN - * = (25,000,000 / 12) * 360 - * = 240,000,000 - * SYSCLK = PLL_VCO / PLLP - * = 240,000,000 / 2 = 120,000,000 - * USB OTG FS, SDIO and RNG Clock - * = PLL_VCO / PLLQ - * = 240,000,000 / 5 = 48,000,000 - * = 48,000,000 - * - * Xtal /M *n /P SysClk AHB HCLK APB1 PCLK1 - * 12Mhz HSE /12 336 /2 PLLCLK 168Mhz /1 168 /4 42Mhz - * 12Mhz HSE /6 168 /2 PLLCLK 168Mhz /1 168 /4 42Mhz - */ - -#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(3) -#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(84) -#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_2 -#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(5) -#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(7) - -#define STM32_SYSCLK_FREQUENCY 168000000ul - -/* AHB clock (HCLK) is SYSCLK (168MHz) */ - -#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ -#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY - -/* APB1 clock (PCLK1) is HCLK/4 (42MHz) */ - -#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd4 /* PCLK1 = HCLK / 4 */ -#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/4) - -/* Timers driven from APB1 will be twice PCLK1 */ - -#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) - -/* APB2 clock (PCLK2) is HCLK/2 */ - -#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLKd2 /* PCLK2 = HCLK / 2 */ -#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/2) - -/* Timers driven from APB2 will be twice PCLK2 */ - -#define STM32_APB2_TIM1_CLKIN (2 * STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM8_CLKIN (2 * STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM9_CLKIN (2 * STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM10_CLKIN (2 * STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM11_CLKIN (2 * STM32_PCLK2_FREQUENCY) - -/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx - * otherwise frequency is 2xAPBx. - * Note: TIM1,8 are on APB2, others on APB1 - */ - -#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM2_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM3_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM4_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM5_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM6_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM7_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY - -/* SDIO dividers. Note that slower clocking is required when DMA is disabled - * in order to avoid RX overrun/TX underrun errors due to delayed responses - * to service FIFOs in interrupt driven mode. These values have not been - * tuned!!! - * - * SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(118+2)=400 KHz - */ - -#define SDIO_INIT_CLKDIV (118 << SDIO_CLKCR_CLKDIV_SHIFT) - -/* DMA ON: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(1+2)=16 MHz - * DMA OFF: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(2+2)=12 MHz - */ - -#ifdef CONFIG_SDIO_DMA -# define SDIO_MMCXFR_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT) -#else -# define SDIO_MMCXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT) -#endif - -/* DMA ON: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(1+2)=16 MHz - * DMA OFF: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(2+2)=12 MHz - */ - -#ifdef CONFIG_SDIO_DMA -# define SDIO_SDXFR_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT) -#else -# define SDIO_SDXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT) -#endif - -/* LED definitions **********************************************************/ - -/* If CONFIG_ARCH_LEDS is not defined, then the user can control the status - * LED in any way. - * The following definitions are used to access individual LEDs. - */ - -/* LED index values for use with board_userled() */ - -#define BOARD_LED_STATUS 0 -#define BOARD_NLEDS 1 - -/* LED bits for use with board_userled_all() */ - -#define BOARD_LED_STATUS_BIT (1 << BOARD_LED_STATUS) - -/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the status LED of - * the Olimex STM32-H405. - * The following definitions describe how NuttX controls the LEDs: - */ - -#define LED_STARTED 0 /* LED_STATUS on */ -#define LED_HEAPALLOCATE 1 /* no change */ -#define LED_IRQSENABLED 2 /* no change */ -#define LED_STACKCREATED 3 /* no change */ -#define LED_INIRQ 4 /* no change */ -#define LED_SIGNAL 5 /* no change */ -#define LED_ASSERTION 6 /* LED_STATUS off */ -#define LED_PANIC 7 /* LED_STATUS blinking */ - -/* Button definitions *******************************************************/ - -/* The Olimex STM32-H405 supports one buttons: */ - -#define BUTTON_BUT 0 -#define NUM_BUTTONS 1 - -#define BUTTON_BUT_BIT (1 << BUTTON_BUT) - -/* Alternate function pin selections ****************************************/ - -/* USART3: */ - -#if 0 -#define GPIO_USART3_RX (GPIO_USART3_RX_1|GPIO_SPEED_100MHz) /* PB11 */ -#define GPIO_USART3_TX (GPIO_USART3_TX_1|GPIO_SPEED_100MHz) /* PB10 */ -#define GPIO_USART3_CTS GPIO_USART3_CTS_1 /* PB13 */ -#define GPIO_USART3_RTS GPIO_USART3_RTS_1 /* PB14 */ -#endif - -/* USART2: */ - -#define GPIO_USART2_RX (GPIO_USART2_RX_1|GPIO_SPEED_100MHz) -#define GPIO_USART2_TX (GPIO_USART2_TX_1|GPIO_SPEED_100MHz) -#define GPIO_USART2_CTS GPIO_USART2_CTS_1 -#define GPIO_USART2_RTS GPIO_USART2_RTS_1 - -/* USART6: (UEXT connector) */ - -#define GPIO_USART6_RX (GPIO_USART6_RX_1|GPIO_SPEED_100MHz) -#define GPIO_USART6_TX (GPIO_USART6_TX_1|GPIO_SPEED_100MHz) - -/* GPIO_USART6_CTS and GPIO_USART6_RTS aren't used for UEXT */ - -/* CAN: */ - -#define GPIO_CAN1_RX (GPIO_CAN1_RX_2|GPIO_SPEED_50MHz) /* PB8 */ -#define GPIO_CAN1_TX (GPIO_CAN1_TX_2|GPIO_SPEED_50MHz) /* PB9 */ -#define GPIO_CAN2_RX (GPIO_CAN1_RX_2|GPIO_SPEED_50MHz) /* PB5 */ -#define GPIO_CAN2_TX (GPIO_CAN1_TX_2|GPIO_SPEED_50MHz) /* PB6 */ - -/* SDIO */ - -#define GPIO_SDIO_CK (GPIO_SDIO_CK_0|GPIO_SPEED_50MHz) -#define GPIO_SDIO_CMD (GPIO_SDIO_CMD_0|GPIO_SPEED_50MHz) -#define GPIO_SDIO_D0 (GPIO_SDIO_D0_0|GPIO_SPEED_50MHz) -#define GPIO_SDIO_D1 (GPIO_SDIO_D1_0|GPIO_SPEED_50MHz) -#define GPIO_SDIO_D2 (GPIO_SDIO_D2_0|GPIO_SPEED_50MHz) -#define GPIO_SDIO_D3 (GPIO_SDIO_D3_0|GPIO_SPEED_50MHz) - -/* USB OTG FS */ - -#define GPIO_OTGFS_DM (GPIO_OTGFS_DM_0|GPIO_SPEED_100MHz) -#define GPIO_OTGFS_DP (GPIO_OTGFS_DP_0|GPIO_SPEED_100MHz) -#define GPIO_OTGFS_ID (GPIO_OTGFS_ID_0|GPIO_SPEED_100MHz) -#define GPIO_OTGFS_SOF (GPIO_OTGFS_SOF_0|GPIO_SPEED_100MHz) - -/* DMA Channel/Stream Selections ********************************************/ - -/* Stream selections are arbitrary for now but might become important in the - * future if we set aside more DMA channels/streams. - * - * SDIO DMA - * DMAMAP_SDIO_1 = Channel 4, Stream 3 - * DMAMAP_SDIO_2 = Channel 4, Stream 6 - */ - -#define DMAMAP_SDIO DMAMAP_SDIO_1 - -#endif /* __BOARDS_ARM_STM32_OLIMEX_STM32_H407_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32/olimex-stm32-h407/scripts/Make.defs b/boards/arm/stm32/olimex-stm32-h407/scripts/Make.defs deleted file mode 100644 index 6dae53fb984eb..0000000000000 --- a/boards/arm/stm32/olimex-stm32-h407/scripts/Make.defs +++ /dev/null @@ -1,41 +0,0 @@ -############################################################################ -# boards/arm/stm32/olimex-stm32-h407/scripts/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/.config -include $(TOPDIR)/tools/Config.mk -include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs - -LDSCRIPT = ld.script -ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) - -ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 - -CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) -CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) -CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -AFLAGS := $(CFLAGS) -D__ASSEMBLY__ - -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections -LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32/olimex-stm32-h407/scripts/ld.script b/boards/arm/stm32/olimex-stm32-h407/scripts/ld.script deleted file mode 100644 index 2d0c8e0704f54..0000000000000 --- a/boards/arm/stm32/olimex-stm32-h407/scripts/ld.script +++ /dev/null @@ -1,125 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/olimex-stm32-h407/scripts/ld.script - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* The STM32F407ZGT6 has 1024Kb of FLASH beginning at address 0x0800:0000 and - * 192Kb of SRAM. SRAM is split up into two blocks: - * - * 1) 112Kb of SRAM beginning at address 0x2000:0000 - * 2) 16Kb of SRAM beginning at address 0x2001:c000 - * 3) 64Kb of SRAM beginning at address 0x2002:0000 - * - * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 - * where the code expects to begin execution by jumping to the entry point in - * the 0x0800:0000 address - * range. - */ - -MEMORY -{ - flash (rx) : ORIGIN = 0x08000000, LENGTH = 1024K - sram (rwx) : ORIGIN = 0x20000000, LENGTH = 112K -} - -OUTPUT_ARCH(arm) -ENTRY(_stext) -SECTIONS -{ - .text : { - _stext = ABSOLUTE(.); - *(.vectors) - *(.text .text.*) - *(.fixup) - *(.gnu.warning) - *(.rodata .rodata.*) - *(.gnu.linkonce.t.*) - *(.glue_7) - *(.glue_7t) - *(.got) - *(.gcc_except_table) - *(.gnu.linkonce.r.*) - _etext = ABSOLUTE(.); - } > flash - - .init_section : ALIGN(4) { - _sinit = ABSOLUTE(.); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) - KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) - _einit = ABSOLUTE(.); - } > flash - - .ARM.extab : ALIGN(4) { - *(.ARM.extab*) - } > flash - - .ARM.exidx : ALIGN(4) { - __exidx_start = ABSOLUTE(.); - *(.ARM.exidx*) - __exidx_end = ABSOLUTE(.); - } > flash - - .tdata : { - _stdata = ABSOLUTE(.); - *(.tdata .tdata.* .gnu.linkonce.td.*); - _etdata = ABSOLUTE(.); - } > flash - - .tbss : { - _stbss = ABSOLUTE(.); - *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); - _etbss = ABSOLUTE(.); - } > flash - - _eronly = ABSOLUTE(.); - - .data : ALIGN(4) { - _sdata = ABSOLUTE(.); - *(.data .data.*) - *(.gnu.linkonce.d.*) - CONSTRUCTORS - . = ALIGN(4); - _edata = ABSOLUTE(.); - } > sram AT > flash - - .bss : ALIGN(4) { - _sbss = ABSOLUTE(.); - *(.bss .bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - . = ALIGN(4); - _ebss = ABSOLUTE(.); - } > sram - - /* Stabs debugging sections. */ - - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_info 0 : { *(.debug_info) } - .debug_line 0 : { *(.debug_line) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_aranges 0 : { *(.debug_aranges) } -} diff --git a/boards/arm/stm32/olimex-stm32-h407/src/CMakeLists.txt b/boards/arm/stm32/olimex-stm32-h407/src/CMakeLists.txt deleted file mode 100644 index 4f687f840f77a..0000000000000 --- a/boards/arm/stm32/olimex-stm32-h407/src/CMakeLists.txt +++ /dev/null @@ -1,65 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/olimex-stm32-h407/src/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -set(SRCS stm32_boot.c stm32_bringup.c) - -if(CONFIG_ARCH_LEDS) - list(APPEND SRCS stm32_autoleds.c) -else() - list(APPEND SRCS stm32_userleds.c) -endif() - -if(CONFIG_ARCH_BUTTONS) - list(APPEND SRCS stm32_buttons.c) -endif() - -if(CONFIG_ARCH_IDLE_CUSTOM) - list(APPEND SRCS stm32_idle.c) -endif() - -if(CONFIG_STM32_FSMC) - list(APPEND SRCS stm32_extmem.c) -endif() - -if(CONFIG_STM32_OTGFS) - list(APPEND SRCS stm32_usb.c) -endif() - -if(CONFIG_STM32_OTGHS) - list(APPEND SRCS stm32_usb.c) -endif() - -if(CONFIG_ADC) - list(APPEND SRCS stm32_adc.c) -endif() - -if(CONFIG_STM32_CAN_CHARDRIVER) - list(APPEND SRCS stm32_can.c) -endif() - -if(CONFIG_STM32_SDIO) - list(APPEND SRCS stm32_sdio.c) -endif() - -target_sources(board PRIVATE ${SRCS}) - -set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/ld.script") diff --git a/boards/arm/stm32/olimex-stm32-h407/src/Make.defs b/boards/arm/stm32/olimex-stm32-h407/src/Make.defs deleted file mode 100644 index 9e3959c58c9d8..0000000000000 --- a/boards/arm/stm32/olimex-stm32-h407/src/Make.defs +++ /dev/null @@ -1,67 +0,0 @@ -############################################################################ -# boards/arm/stm32/olimex-stm32-h407/src/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/Make.defs - -CSRCS = stm32_boot.c stm32_bringup.c - -ifeq ($(CONFIG_ARCH_LEDS),y) -CSRCS += stm32_autoleds.c -else -CSRCS += stm32_userleds.c -endif - -ifeq ($(CONFIG_ARCH_BUTTONS),y) -CSRCS += stm32_buttons.c -endif - -ifeq ($(CONFIG_ARCH_IDLE_CUSTOM),y) -CSRCS += stm32_idle.c -endif - -ifeq ($(CONFIG_STM32_FSMC),y) -CSRCS += stm32_extmem.c -endif - -ifeq ($(CONFIG_STM32_OTGFS),y) -CSRCS += stm32_usb.c -endif - -ifeq ($(CONFIG_STM32_OTGHS),y) -CSRCS += stm32_usb.c -endif - -ifeq ($(CONFIG_ADC),y) -CSRCS += stm32_adc.c -endif - -ifeq ($(CONFIG_STM32_CAN_CHARDRIVER),y) -CSRCS += stm32_can.c -endif - -ifeq ($(CONFIG_STM32_SDIO),y) -CSRCS += stm32_sdio.c -endif - -DEPPATH += --dep-path board -VPATH += :board -CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/olimex-stm32-h407/src/stm32_adc.c b/boards/arm/stm32/olimex-stm32-h407/src/stm32_adc.c deleted file mode 100644 index 6ec856172e30f..0000000000000 --- a/boards/arm/stm32/olimex-stm32-h407/src/stm32_adc.c +++ /dev/null @@ -1,165 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/olimex-stm32-h407/src/stm32_adc.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include -#include - -#include "chip.h" -#include "stm32_adc.h" -#include "olimex-stm32-h407.h" - -#ifdef CONFIG_ADC - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -/* Up to 3 ADC interfaces are supported */ - -#if STM32_NADC < 3 -# undef CONFIG_STM32_ADC3 -#endif - -#if STM32_NADC < 2 -# undef CONFIG_STM32_ADC2 -#endif - -#if STM32_NADC < 1 -# undef CONFIG_STM32_ADC1 -#endif - -#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) || defined(CONFIG_STM32_ADC3) -#ifndef CONFIG_STM32_ADC1 -# warning "Channel information only available for ADC1" -#endif - -/* The number of ADC channels in the conversion list */ - -#define ADC1_NCHANNELS 1//14 - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* The Olimex STM32-P405 has a 10 Kohm potentiometer AN_TR connected to PC0 - * ADC123_IN10 - */ - -/* Identifying number of each ADC channel: Variable Resistor. - * - * {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 15}; - */ - -#ifdef CONFIG_STM32_ADC1 -static const uint8_t g_chanlist[ADC1_NCHANNELS] = -{ - 1 -}; - -/* Configurations of pins used byte each ADC channels - * - * {GPIO_ADC1_IN1, GPIO_ADC1_IN2, GPIO_ADC1_IN3, GPIO_ADC1_IN4, - * GPIO_ADC1_IN5, GPIO_ADC1_IN6, GPIO_ADC1_IN7, GPIO_ADC1_IN8, - * GPIO_ADC1_IN9, GPIO_ADC1_IN10, GPIO_ADC1_IN11, GPIO_ADC1_IN12, - * GPIO_ADC1_IN13, GPIO_ADC1_IN15}; - */ - -static const uint32_t g_pinlist[ADC1_NCHANNELS] = -{ - GPIO_ADC1_IN1 -}; -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_adc_setup - * - * Description: - * Initialize ADC and register the ADC driver. - * - ****************************************************************************/ - -int stm32_adc_setup(void) -{ -#ifdef CONFIG_STM32_ADC1 - static bool initialized = false; - struct adc_dev_s *adc; - int ret; - int i; - - /* Check if we have already initialized */ - - if (!initialized) - { - /* Configure the pins as analog inputs for the selected channels */ - - for (i = 0; i < ADC1_NCHANNELS; i++) - { - stm32_configgpio(g_pinlist[i]); - } - - /* Call stm32_adcinitialize() to get an instance of the ADC interface */ - - adc = stm32_adcinitialize(1, g_chanlist, ADC1_NCHANNELS); - if (adc == NULL) - { - aerr("ERROR: Failed to get ADC interface\n"); - return -ENODEV; - } - - /* Register the ADC driver at "/dev/adc0" */ - - ret = adc_register("/dev/adc0", adc); - if (ret < 0) - { - aerr("ERROR: adc_register failed: %d\n", ret); - return ret; - } - - /* Now we are initialized */ - - initialized = true; - } - - return OK; -#else - return -ENOSYS; -#endif -} - -#endif /* CONFIG_STM32_ADC1 || CONFIG_STM32_ADC2 || CONFIG_STM32_ADC3 */ -#endif /* CONFIG_ADC */ diff --git a/boards/arm/stm32/olimex-stm32-h407/src/stm32_autoleds.c b/boards/arm/stm32/olimex-stm32-h407/src/stm32_autoleds.c deleted file mode 100644 index 8b8236d5ea945..0000000000000 --- a/boards/arm/stm32/olimex-stm32-h407/src/stm32_autoleds.c +++ /dev/null @@ -1,92 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/olimex-stm32-h407/src/stm32_autoleds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32.h" -#include "olimex-stm32-h407.h" - -#ifdef CONFIG_ARCH_LEDS - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_autoled_initialize - ****************************************************************************/ - -void board_autoled_initialize(void) -{ - /* Configure LED_STATUS GPIO for output */ - - stm32_configgpio(GPIO_LED_STATUS); -} - -/**************************************************************************** - * Name: board_autoled_on - ****************************************************************************/ - -void board_autoled_on(int led) -{ - if (led == LED_STARTED) - { - stm32_gpiowrite(GPIO_LED_STATUS, true); - } - - if (led == LED_ASSERTION || led == LED_PANIC) - { - stm32_gpiowrite(GPIO_LED_STATUS, false); - } -} - -/**************************************************************************** - * Name: board_autoled_off - ****************************************************************************/ - -void board_autoled_off(int led) -{ - if (led == LED_STARTED) - { - stm32_gpiowrite(GPIO_LED_STATUS, false); - } - - if (led == LED_ASSERTION || led == LED_PANIC) - { - stm32_gpiowrite(GPIO_LED_STATUS, true); - } -} - -#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/olimex-stm32-h407/src/stm32_boot.c b/boards/arm/stm32/olimex-stm32-h407/src/stm32_boot.c deleted file mode 100644 index a2f2c02ed66f9..0000000000000 --- a/boards/arm/stm32/olimex-stm32-h407/src/stm32_boot.c +++ /dev/null @@ -1,100 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/olimex-stm32-h407/src/stm32_boot.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include -#include -#include - -#include "arm_internal.h" -#include "olimex-stm32-h407.h" -#include "stm32_ccm.h" - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_boardinitialize - * - * Description: - * All STM32 architectures must provide the following entry point. - * This entry point is called early in the initialization -- after all - * memory has been configured and mapped but before any devices have been - * initialized. - * - ****************************************************************************/ - -void stm32_boardinitialize(void) -{ -#if defined(CONFIG_STM32_OTGFS) || defined(CONFIG_STM32_OTGHS) - /* Initialize USB if the 1) OTG FS controller is in the configuration and - * 2) disabled, and 3) the weak function stm32_usbinitialize() has been - * brought into the build. - * Presumably either CONFIG_USBDEV is also selected. - */ - - if (stm32_usbinitialize) - { - stm32_usbinitialize(); - } -#endif - -#ifdef CONFIG_ARCH_LEDS - /* Configure on-board LEDs if LED support has been selected. */ - - board_autoled_initialize(); -#endif - -#ifdef CONFIG_ARCH_BUTTONS - /* Configure on-board BUTTONs if BUTTON support has been selected. */ - - board_button_initialize(); -#endif -} - -/**************************************************************************** - * Name: board_late_initialize - * - * Description: - * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional - * initialization call will be performed in the boot-up sequence to a - * function called board_late_initialize(). board_late_initialize() will be - * called immediately after up_intitialize() is called and just before the - * initial application is started. This additional initialization phase - * may be used, for example, to initialize board-specific device drivers. - * - ****************************************************************************/ - -#ifdef CONFIG_BOARD_LATE_INITIALIZE -void board_late_initialize(void) -{ - stm32_bringup(); -} -#endif diff --git a/boards/arm/stm32/olimex-stm32-h407/src/stm32_bringup.c b/boards/arm/stm32/olimex-stm32-h407/src/stm32_bringup.c deleted file mode 100644 index 7a4e99655bdab..0000000000000 --- a/boards/arm/stm32/olimex-stm32-h407/src/stm32_bringup.c +++ /dev/null @@ -1,168 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/olimex-stm32-h407/src/stm32_bringup.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include - -#include - -#ifdef CONFIG_USBMONITOR -# include -#endif - -#ifdef CONFIG_STM32_OTGFS -# include "stm32_usbhost.h" -#endif - -#include "stm32.h" -#include "olimex-stm32-h407.h" - -/* Conditional logic in olimex-stm32-h407.h will determine if certain - * features are supported. - * Tests for these features need to be made after including - * olimex-stm32-h407.h. - */ - -#ifdef HAVE_RTC_DRIVER -# include -# include "stm32_rtc.h" -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_bringup - * - * Description: - * Perform architecture specific initialization - * - * CONFIG_BOARD_LATE_INITIALIZE=y: - * Called from board_late_initialize(). - * - * Otherwise, bad news: Never called - * - ****************************************************************************/ - -int stm32_bringup(void) -{ -#ifdef HAVE_RTC_DRIVER - struct rtc_lowerhalf_s *lower; -#endif - int ret; - -#ifdef CONFIG_STM32_CAN_CHARDRIVER - /* Initialize CAN and register the CAN driver. */ - - ret = stm32_can_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_can_setup failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_ADC - /* Initialize ADC and register the ADC driver. */ - - ret = stm32_adc_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_adc_setup failed: %d\n", ret); - } -#endif - -#ifdef HAVE_SDIO - /* Initialize the SDIO block driver */ - - ret = stm32_sdio_initialize(); - if (ret != OK) - { - syslog(LOG_ERR, - "ERROR: Failed to initialize MMC/SD driver: %d\n", - ret); - } -#endif - -#ifdef HAVE_USBHOST - /* Initialize USB host operation. - * stm32_usbhost_initialize() starts a thread will monitor for USB - * connection and disconnection events. - */ - - ret = stm32_usbhost_initialize(); - if (ret != OK) - { - syslog(LOG_ERR, - "ERROR: Failed to initialize USB host: %d\n", - ret); - } -#endif - -#ifdef HAVE_USBMONITOR - /* Start the USB Monitor */ - - ret = usbmonitor_start(); - if (ret != OK) - { - syslog(LOG_ERR, - "ERROR: Failed to start USB monitor: %d\n", - ret); - } -#endif - -#ifdef HAVE_RTC_DRIVER - /* Instantiate the STM32 lower-half RTC driver */ - - lower = stm32_rtc_lowerhalf(); - if (!lower) - { - syslog(LOG_ERR, - "ERROR: Failed to instantiate the RTC lower-half driver\n"); - } - else - { - /* Bind the lower half driver and register the combined RTC driver - * as /dev/rtc0 - */ - - ret = rtc_initialize(0, lower); - if (ret < 0) - { - syslog(LOG_ERR, - "ERROR: Failed to bind/register the RTC driver: %d\n", - ret); - } - } -#endif - - UNUSED(ret); - return OK; -} diff --git a/boards/arm/stm32/olimex-stm32-h407/src/stm32_buttons.c b/boards/arm/stm32/olimex-stm32-h407/src/stm32_buttons.c deleted file mode 100644 index f8eefa4d76fa2..0000000000000 --- a/boards/arm/stm32/olimex-stm32-h407/src/stm32_buttons.c +++ /dev/null @@ -1,140 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/olimex-stm32-h407/src/stm32_buttons.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include -#include - -#include "olimex-stm32-h407.h" - -#ifdef CONFIG_ARCH_BUTTONS - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* Pin configuration for each Olimex-STM32-H405 button. This array is indexed - * by the BUTTON_* definitions in board.h - */ - -static const uint32_t g_buttons[NUM_BUTTONS] = -{ - GPIO_BTN_BUT -}; - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_button_initialize - * - * Description: - * board_button_initialize() must be called to initialize button resources. - * After that, board_buttons() may be called to collect the current state - * of all buttons or board_button_irq() may be called to register button - * interrupt handlers. - * - ****************************************************************************/ - -uint32_t board_button_initialize(void) -{ - int i; - - /* Configure the GPIO pins as inputs. NOTE that EXTI interrupts are - * configured for all pins. - */ - - for (i = 0; i < NUM_BUTTONS; i++) - { - stm32_configgpio(g_buttons[i]); - } - - return NUM_BUTTONS; -} - -/**************************************************************************** - * Name: board_buttons - ****************************************************************************/ - -uint32_t board_buttons(void) -{ - uint32_t ret = 0; - - /* Check that state of each key */ - - if (!stm32_gpioread(g_buttons[BUTTON_BUT])) - { - ret |= BUTTON_BUT_BIT; - } - - return ret; -} - -/**************************************************************************** - * Button support. - * - * Description: - * board_button_initialize() must be called to initialize button resources. - * After that, board_buttons() may be called to collect the current state - * of all buttons or board_button_irq() may be called to register button - * interrupt handlers. - * - * After board_button_initialize() has been called, board_buttons() may be - * called to collect the state of all buttons. board_buttons() returns an - * 32-bit bit set with each bit associated with a button. See the - * BUTTON_*_BIT definitions in board.h for the meaning of each bit. - * - * board_button_irq() may be called to register an interrupt handler that - * will be called when a button is depressed or released. The ID value is - * a button enumeration value that uniquely identifies a button resource. - * See the BUTTON_* definitions in board.h for the meaning of enumeration - * value. - * - ****************************************************************************/ - -#ifdef CONFIG_ARCH_IRQBUTTONS -int board_button_irq(int id, xcpt_t irqhandler, void *arg) -{ - int ret = -EINVAL; - - /* The following should be atomic */ - - if (id >= MIN_IRQBUTTON && id <= MAX_IRQBUTTON) - { - ret = stm32_gpiosetevent(g_buttons[id], true, true, true, irqhandler, - arg); - } - - return ret; -} -#endif -#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/stm32/olimex-stm32-h407/src/stm32_can.c b/boards/arm/stm32/olimex-stm32-h407/src/stm32_can.c deleted file mode 100644 index c9cc0fc267886..0000000000000 --- a/boards/arm/stm32/olimex-stm32-h407/src/stm32_can.c +++ /dev/null @@ -1,100 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/olimex-stm32-h407/src/stm32_can.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include - -#include "stm32.h" -#include "stm32_can.h" -#include "olimex-stm32-h407.h" - -#ifdef CONFIG_CAN - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -#if defined(CONFIG_STM32_CAN1) && defined(CONFIG_STM32_CAN2) -# warning "Both CAN1 and CAN2 are enabled. Only CAN1 is used." -# undef CONFIG_STM32_CAN2 -#endif - -#ifdef CONFIG_STM32_CAN1 -# define CAN_PORT 1 -#else -# define CAN_PORT 2 -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_can_setup - * - * Description: - * Initialize CAN and register the CAN device - * - ****************************************************************************/ - -int stm32_can_setup(void) -{ -#if defined(CONFIG_STM32_CAN1) || defined(CONFIG_STM32_CAN2) - struct can_dev_s *can; - int ret; - - /* Call stm32_caninitialize() to get an instance of the CAN interface */ - - can = stm32_caninitialize(CAN_PORT); - if (can == NULL) - { - canerr("ERROR: Failed to get CAN interface\n"); - return -ENODEV; - } - - /* Register the CAN driver at "/dev/can0" */ - - ret = can_register("/dev/can0", can); - if (ret < 0) - { - canerr("ERROR: can_register failed: %d\n", ret); - return ret; - } - - return OK; -#else - return -ENODEV; -#endif -} - -#endif /* CONFIG_CAN */ diff --git a/boards/arm/stm32/olimex-stm32-h407/src/stm32_sdio.c b/boards/arm/stm32/olimex-stm32-h407/src/stm32_sdio.c deleted file mode 100644 index 7752b2a054d29..0000000000000 --- a/boards/arm/stm32/olimex-stm32-h407/src/stm32_sdio.c +++ /dev/null @@ -1,161 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/olimex-stm32-h407/src/stm32_sdio.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include - -#include -#include - -#include "stm32.h" -#include "olimex-stm32-h407.h" - -#ifdef HAVE_SDIO - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -/* Card detections requires card support and a card detection GPIO */ - -#define HAVE_NCD 1 -#if !defined(HAVE_SDIO) || !defined(GPIO_SDIO_NCD) -# undef HAVE_NCD -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -static struct sdio_dev_s *g_sdio_dev; -#ifdef HAVE_NCD -static bool g_sd_inserted; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_ncd_interrupt - * - * Description: - * Card detect interrupt handler. - * - ****************************************************************************/ - -#ifdef HAVE_NCD -static int stm32_ncd_interrupt(int irq, void *context) -{ - bool present; - - present = !stm32_gpioread(GPIO_SDIO_NCD); - if (present != g_sd_inserted) - { - sdio_mediachange(g_sdio_dev, present); - g_sd_inserted = present; - } - - return OK; -} -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_sdio_initialize - * - * Description: - * Initialize SDIO-based MMC/SD card support - * - ****************************************************************************/ - -int stm32_sdio_initialize(void) -{ - int ret; - -#ifdef HAVE_NCD - /* Configure the card detect GPIO */ - - stm32_configgpio(GPIO_SDIO_NCD); - - /* Register an interrupt handler for the card detect pin */ - - stm32_gpiosetevent(GPIO_SDIO_NCD, true, true, true, - stm32_ncd_interrupt, NULL); -#endif - - /* Mount the SDIO-based MMC/SD block driver */ - - /* First, get an instance of the SDIO interface */ - - finfo("Initializing SDIO slot %d\n", SDIO_SLOTNO); - - g_sdio_dev = sdio_initialize(SDIO_SLOTNO); - if (!g_sdio_dev) - { - ferr("ERROR: Failed to initialize SDIO slot %d\n", SDIO_SLOTNO); - return -ENODEV; - } - - /* Now bind the SDIO interface to the MMC/SD driver */ - - finfo("Bind SDIO to the MMC/SD driver, minor=%d\n", SDIO_MINOR); - - ret = mmcsd_slotinitialize(SDIO_MINOR, g_sdio_dev); - if (ret != OK) - { - ferr("ERROR: Failed to bind SDIO to the MMC/SD driver: %d\n", ret); - return ret; - } - - finfo("Successfully bound SDIO to the MMC/SD driver\n"); - -#ifdef HAVE_NCD - /* Use SD card detect pin to check if a card is g_sd_inserted */ - - g_sd_inserted = !stm32_gpioread(GPIO_SDIO_NCD); - finfo("Card detect : %d\n", g_sd_inserted); - - sdio_mediachange(g_sdio_dev, g_sd_inserted); -#else - /* Assume that the SD card is inserted. What choice do we have? */ - - sdio_mediachange(g_sdio_dev, true); -#endif - - return OK; -} - -#endif /* HAVE_SDIO */ diff --git a/boards/arm/stm32/olimex-stm32-h407/src/stm32_usb.c b/boards/arm/stm32/olimex-stm32-h407/src/stm32_usb.c deleted file mode 100644 index 2da446dbe0791..0000000000000 --- a/boards/arm/stm32/olimex-stm32-h407/src/stm32_usb.c +++ /dev/null @@ -1,311 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/olimex-stm32-h407/src/stm32_usb.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -#include "arm_internal.h" -#include "stm32.h" -#include "stm32_otgfs.h" -#include "stm32_otghs.h" -#include "olimex-stm32-h407.h" - -#ifdef CONFIG_STM32_OTGHS - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#if defined(CONFIG_USBDEV) || defined(CONFIG_USBHOST) -# define HAVE_USB 1 -#else -# warning "CONFIG_STM32_OTGHS is enabled but neither CONFIG_USBDEV nor CONFIG_USBHOST" -# undef HAVE_USB -#endif - -#ifndef CONFIG_STM32F407_USBHOST_PRIO -# define CONFIG_STM32F407_USBHOST_PRIO 100 -#endif - -#ifndef CONFIG_STM32F407_USBHOST_STACKSIZE -# define CONFIG_STM32F407_USBHOST_STACKSIZE 1024 -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -#ifdef CONFIG_USBHOST -static struct usbhost_connection_s *g_usbconn; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: usbhost_waiter - * - * Description: - * Wait for USB devices to be connected. - * - ****************************************************************************/ - -#ifdef CONFIG_USBHOST -static int usbhost_waiter(int argc, char *argv[]) -{ - struct usbhost_hubport_s *hport; - - uinfo("Running\n"); - for (; ; ) - { - /* Wait for the device to change state */ - - DEBUGVERIFY(CONN_WAIT(g_usbconn, &hport)); - uinfo("%s\n", hport->connected ? "connected" : "disconnected"); - - /* Did we just become connected? */ - - if (hport->connected) - { - /* Yes.. enumerate the newly connected device */ - - CONN_ENUMERATE(g_usbconn, hport); - } - } - - /* Keep the compiler from complaining */ - - return 0; -} -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_usbinitialize - * - * Description: - * Called from stm32_usbinitialize very early in initialization to setup - * USB-related GPIO pins for the STM32F4Discovery board. - * - ****************************************************************************/ - -void stm32_usbinitialize(void) -{ - /* The OTG FS has an internal soft pull-up. - * No GPIO configuration is required - */ - - /* Configure the OTG FS VBUS sensing GPIO, - * Power On, and Overcurrent GPIOs - */ - -#ifdef CONFIG_STM32_OTGHS - stm32_configgpio(GPIO_OTGHS_VBUS); - stm32_configgpio(GPIO_OTGHS_PWRON); - stm32_configgpio(GPIO_OTGHS_OVER); -#endif -} - -/**************************************************************************** - * Name: stm32_usbhost_initialize - * - * Description: - * Called at application startup time to initialize the USB host - * functionality. - * This function will start a thread that will monitor for device - * connection/disconnection events. - * - ****************************************************************************/ - -#ifdef CONFIG_USBHOST -int stm32_usbhost_initialize(void) -{ - int ret; - - /* First, register all of the class drivers needed to support the drivers - * that we care about: - */ - - uinfo("Register class drivers\n"); - -#ifdef CONFIG_USBHOST_HUB - /* Initialize USB hub class support */ - - ret = usbhost_hub_initialize(); - if (ret < 0) - { - uerr("ERROR: usbhost_hub_initialize failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_USBHOST_MSC - /* Register the USB mass storage class class */ - - ret = usbhost_msc_initialize(); - if (ret != OK) - { - uerr("ERROR: Failed to register the mass storage class: %d\n", ret); - } -#endif - -#ifdef CONFIG_USBHOST_CDCACM - /* Register the CDC/ACM serial class */ - - ret = usbhost_cdcacm_initialize(); - if (ret != OK) - { - uerr("ERROR: Failed to register the CDC/ACM serial class: %d\n", ret); - } -#endif - - /* Then get an instance of the USB host interface */ - - uinfo("Initialize USB host\n"); - g_usbconn = stm32_otghshost_initialize(0); - if (g_usbconn) - { - /* Start a thread to handle device connection. */ - - uinfo("Start usbhost_waiter\n"); - - ret = kthread_create("usbhost", CONFIG_STM32H407_USBHOST_PRIO, - CONFIG_STM32H407_USBHOST_STACKSIZE, - usbhost_waiter, NULL); - return ret < 0 ? -ENOEXEC : OK; - } - - return -ENODEV; -} -#endif - -/**************************************************************************** - * Name: stm32_usbhost_vbusdrive - * - * Description: - * Enable/disable driving of VBUS 5V output. This function must be - * provided be each platform that implements the STM32 OTG FS host - * interface - * - * "On-chip 5 V VBUS generation is not supported. For this reason, a - * charge pump or, if 5 V are available on the application board, a - * basic power switch, must be added externally to drive the 5 V VBUS - * line. The external charge pump can be driven by any GPIO output. - * When the application decides to power on VBUS using the chosen GPIO, - * it must also set the port power bit in the host port control and - * status register (PPWR bit in OTG_FS_HPRT). - * - * "The application uses this field to control power to this port, - * and the core clears this bit on an overcurrent condition." - * - * Input Parameters: - * iface - For future growth to handle multiple USB host interface. - * Should be zero. - * enable - true: enable VBUS power; false: disable VBUS power - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef CONFIG_USBHOST -void stm32_usbhost_vbusdrive(int iface, bool enable) -{ - DEBUGASSERT(iface == 0); - - if (enable) - { - /* Enable the Power Switch by driving the enable pin low */ - - stm32_gpiowrite(GPIO_OTGHS_PWRON, false); - } - else - { - /* Disable the Power Switch by driving the enable pin high */ - - stm32_gpiowrite(GPIO_OTGHS_PWRON, true); - } -} -#endif - -/**************************************************************************** - * Name: stm32_setup_overcurrent - * - * Description: - * Setup to receive an interrupt-level callback if an overcurrent - * condition is detected. - * - * Input Parameters: - * handler - New overcurrent interrupt handler - * arg - The argument provided for the interrupt handler - * - * Returned Value: - * Zero (OK) is returned on success. Otherwise, a negated errno value - * is returned to indicate the nature of the failure. - * - ****************************************************************************/ - -#ifdef CONFIG_USBHOST -int stm32_setup_overcurrent(xcpt_t handler, void *arg) -{ - return stm32_gpiosetevent(GPIO_OTGHS_OVER, true, true, true, handler, arg); -} -#endif - -/**************************************************************************** - * Name: stm32_usbsuspend - * - * Description: - * Board logic must provide the stm32_usbsuspend logic if the USBDEV - * driver is used. This function is called whenever the USB enters or - * leaves suspend mode. This is an opportunity for the board logic to - * shutdown clocks, power, etc. while the USB is suspended. - * - ****************************************************************************/ - -#ifdef CONFIG_USBDEV -void stm32_usbsuspend(struct usbdev_s *dev, bool resume) -{ - uinfo("resume: %d\n", resume); -} -#endif - -#endif /* CONFIG_STM32_OTGHS */ diff --git a/boards/arm/stm32/olimex-stm32-h407/src/stm32_userleds.c b/boards/arm/stm32/olimex-stm32-h407/src/stm32_userleds.c deleted file mode 100644 index 7f7b316204499..0000000000000 --- a/boards/arm/stm32/olimex-stm32-h407/src/stm32_userleds.c +++ /dev/null @@ -1,91 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/olimex-stm32-h407/src/stm32_userleds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32.h" -#include "olimex-stm32-h407.h" - -#ifndef CONFIG_ARCH_LEDS - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* This array maps an LED number to GPIO pin configuration */ - -static uint32_t g_ledcfg[BOARD_NLEDS] = -{ - GPIO_LED_STATUS -}; - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_userled_initialize - ****************************************************************************/ - -uint32_t board_userled_initialize(void) -{ - /* Configure LED1-4 GPIOs for output */ - - stm32_configgpio(GPIO_LED_STATUS); - return BOARD_NLEDS; -} - -/**************************************************************************** - * Name: board_userled - ****************************************************************************/ - -void board_userled(int led, bool ledon) -{ - if ((unsigned)led < BOARD_NLEDS) - { - stm32_gpiowrite(g_ledcfg[led], ledon); - } -} - -/**************************************************************************** - * Name: board_userled_all - ****************************************************************************/ - -void board_userled_all(uint32_t ledset) -{ - stm32_gpiowrite(GPIO_LED_STATUS, (ledset & BOARD_LED1_BIT) != 0); -} - -#endif /* !CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/olimex-stm32-p107/CMakeLists.txt b/boards/arm/stm32/olimex-stm32-p107/CMakeLists.txt deleted file mode 100644 index 714fc64c28c14..0000000000000 --- a/boards/arm/stm32/olimex-stm32-p107/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/olimex-stm32-p107/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32/olimex-stm32-p107/configs/nsh/defconfig b/boards/arm/stm32/olimex-stm32-p107/configs/nsh/defconfig deleted file mode 100644 index 0e6f00bff3bca..0000000000000 --- a/boards/arm/stm32/olimex-stm32-p107/configs/nsh/defconfig +++ /dev/null @@ -1,66 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_MMCSD_HAVE_CARDDETECT is not set -# CONFIG_MMCSD_MMCSUPPORT is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_DISABLE_IFCONFIG is not set -# CONFIG_NSH_DISABLE_PS is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="olimex-stm32-p107" -CONFIG_ARCH_BOARD_OLIMEX_STM32P107=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F107VC=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=5483 -CONFIG_BUILTIN=y -CONFIG_CAN=y -CONFIG_ETH0_PHY_KS8721=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_MMCSD=y -CONFIG_MTD=y -CONFIG_NET=y -CONFIG_NETDB_DNSCLIENT=y -CONFIG_NETINIT_DRIPADDR=0xc0a80201 -CONFIG_NETINIT_IPADDR=0xc0a80232 -CONFIG_NETINIT_NOMAC=y -CONFIG_NETUTILS_TFTPC=y -CONFIG_NETUTILS_WEBCLIENT=y -CONFIG_NET_ETH_PKTSIZE=650 -CONFIG_NET_ICMP_SOCKET=y -CONFIG_NET_MAX_LISTENPORTS=40 -CONFIG_NET_TCP=y -CONFIG_NET_TCP_PREALLOC_CONNS=40 -CONFIG_NET_UDP=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=65536 -CONFIG_RAM_START=0x20000000 -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_HPWORKPRIORITY=192 -CONFIG_SCHED_HPWORKSTACKSIZE=1024 -CONFIG_START_DAY=21 -CONFIG_START_MONTH=9 -CONFIG_START_YEAR=2009 -CONFIG_STM32_ETHMAC=y -CONFIG_STM32_JTAG_FULL_ENABLE=y -CONFIG_STM32_PHYSR=16 -CONFIG_STM32_PHYSR_100MBPS=0x0000 -CONFIG_STM32_PHYSR_FULLDUPLEX=0x0004 -CONFIG_STM32_PHYSR_MODE=0x0004 -CONFIG_STM32_PHYSR_SPEED=0x0002 -CONFIG_STM32_PWR=y -CONFIG_STM32_USART2=y -CONFIG_STM32_USART2_REMAP=y -CONFIG_SYSTEM_NSH=y -CONFIG_SYSTEM_PING=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/olimex-stm32-p107/include/board.h b/boards/arm/stm32/olimex-stm32-p107/include/board.h deleted file mode 100644 index 2af99acd922b2..0000000000000 --- a/boards/arm/stm32/olimex-stm32-p107/include/board.h +++ /dev/null @@ -1,145 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/olimex-stm32-p107/include/board.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __BOARDS_ARM_STM32_OLIMEX_STM32_P107_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32_OLIMEX_STM32_P107_INCLUDE_BOARD_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#ifndef __ASSEMBLY__ -# include -#endif - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Clocking *****************************************************************/ - -/* HSI - 8 MHz RC factory-trimmed - * LSI - 40 KHz RC (30-60KHz, uncalibrated) - * HSE - On-board crystal frequency is 25MHz - * LSE - 32.768 kHz - */ - -#define STM32_BOARD_XTAL 25000000ul - -#define STM32_HSI_FREQUENCY 8000000ul -#define STM32_LSI_FREQUENCY 40000 -#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL -#define STM32_LSE_FREQUENCY 32768 - -/* PLL output is 72MHz */ - -#define STM32_PLL_PREDIV2 RCC_CFGR2_PREDIV2d5 /* 25MHz / 5 => 5MHz */ -#define STM32_PLL_PLL2MUL RCC_CFGR2_PLL2MULx8 /* 5MHz * 8 => 40MHz */ -#define STM32_PLL_PREDIV1 RCC_CFGR2_PREDIV1d5 /* 40MHz / 5 => 8MHz */ -#define STM32_PLL_PLLMUL RCC_CFGR_PLLMUL_CLKx9 /* 8MHz * 9 => 72Mhz */ -#define STM32_PLL_FREQUENCY (72000000) - -/* SYCLLK and HCLK are the PLL frequency */ - -#define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY -#define STM32_HCLK_FREQUENCY STM32_PLL_FREQUENCY - -/* APB2 clock (PCLK2) is HCLK (72MHz) */ - -#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK -#define STM32_PCLK2_FREQUENCY STM32_HCLK_FREQUENCY -#define STM32_APB2_CLKIN (STM32_PCLK2_FREQUENCY) /* Timers 2-7, 12-14 */ - -/* APB2 timers 1 and 8 will receive PCLK2. */ - -#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) - -/* APB1 clock (PCLK1) is HCLK/2 (36MHz) */ - -#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd2 -#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/2) - -/* APB1 timers 2-7 will be twice PCLK1 */ - -#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) - -/* MCO output driven by PLL3. From above, we already have PLL3 input - * frequency as: - * - * STM32_PLL_PREDIV2 = 5, 25MHz / 5 => 5MHz - */ - -#if defined(CONFIG_STM32_MII_MCO) || defined(CONFIG_STM32_RMII_MCO) -# define BOARD_CFGR_MCO_SOURCE RCC_CFGR_PLL3CLK /* Source: PLL3 */ -# define STM32_PLL_PLL3MUL RCC_CFGR2_PLL3MULx10 /* MCO 5MHz * 10 = 50MHz */ -#endif - -/* Alternate function pin selections (auto-aliased for new pinmap) */ - -/* USART2 */ - -#define GPIO_USART2_TX GPIO_ADJUST_MODE(GPIO_USART2_TX_0, GPIO_MODE_50MHz) -#define GPIO_USART2_RX GPIO_USART2_RX_0 -#define GPIO_USART2_CTS GPIO_USART2_CTS_0 -#define GPIO_USART2_RTS GPIO_ADJUST_MODE(GPIO_USART2_RTS_0, GPIO_MODE_50MHz) -#define GPIO_USART2_CK GPIO_ADJUST_MODE(GPIO_USART2_CK_0, GPIO_MODE_50MHz) - -/* MCO */ - -#define GPIO_MCO GPIO_ADJUST_MODE(GPIO_MCO_0, GPIO_MODE_50MHz) - -/* Ethernet (MII/RMII) */ - -#define GPIO_ETH_MDC GPIO_ADJUST_MODE(GPIO_ETH_MDC_0, GPIO_MODE_50MHz) -#define GPIO_ETH_MDIO GPIO_ADJUST_MODE(GPIO_ETH_MDIO_0, GPIO_MODE_50MHz) -#define GPIO_ETH_MII_COL GPIO_ETH_MII_COL_0 -#define GPIO_ETH_MII_CRS GPIO_ETH_MII_CRS_0 -#define GPIO_ETH_MII_RX_CLK GPIO_ETH_MII_RX_CLK_0 -#define GPIO_ETH_MII_RXD0 GPIO_ETH_MII_RXD0_0 -#define GPIO_ETH_MII_RXD1 GPIO_ETH_MII_RXD1_0 -#define GPIO_ETH_MII_RXD2 GPIO_ETH_MII_RXD2_0 -#define GPIO_ETH_MII_RXD3 GPIO_ETH_MII_RXD3_0 -#define GPIO_ETH_MII_RX_DV GPIO_ETH_MII_RX_DV_0 -#define GPIO_ETH_MII_RX_ER GPIO_ETH_MII_RX_ER_0 -#define GPIO_ETH_MII_TX_CLK GPIO_ETH_MII_TX_CLK_0 -#define GPIO_ETH_MII_TXD0 GPIO_ADJUST_MODE(GPIO_ETH_MII_TXD0_0, GPIO_MODE_50MHz) -#define GPIO_ETH_MII_TXD1 GPIO_ADJUST_MODE(GPIO_ETH_MII_TXD1_0, GPIO_MODE_50MHz) -#define GPIO_ETH_MII_TXD2 GPIO_ADJUST_MODE(GPIO_ETH_MII_TXD2_0, GPIO_MODE_50MHz) -#define GPIO_ETH_MII_TXD3 GPIO_ADJUST_MODE(GPIO_ETH_MII_TXD3_0, GPIO_MODE_50MHz) -#define GPIO_ETH_MII_TX_EN GPIO_ADJUST_MODE(GPIO_ETH_MII_TX_EN_0, GPIO_MODE_50MHz) -#define GPIO_ETH_RMII_CRS_DV GPIO_ETH_RMII_CRS_DV_0 -#define GPIO_ETH_RMII_REF_CLK GPIO_ETH_RMII_REF_CLK_0 -#define GPIO_ETH_RMII_RXD0 GPIO_ETH_RMII_RXD0_0 -#define GPIO_ETH_RMII_RXD1 GPIO_ETH_RMII_RXD1_0 -#define GPIO_ETH_RMII_TXD0 GPIO_ADJUST_MODE(GPIO_ETH_RMII_TXD0_0, GPIO_MODE_50MHz) -#define GPIO_ETH_RMII_TXD1 GPIO_ADJUST_MODE(GPIO_ETH_RMII_TXD1_0, GPIO_MODE_50MHz) -#define GPIO_ETH_RMII_TX_EN GPIO_ADJUST_MODE(GPIO_ETH_RMII_TX_EN_0, GPIO_MODE_50MHz) - -#endif /* __BOARDS_ARM_STM32_OLIMEX_STM32_P107_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32/olimex-stm32-p107/scripts/Make.defs b/boards/arm/stm32/olimex-stm32-p107/scripts/Make.defs deleted file mode 100644 index 340d9862478fd..0000000000000 --- a/boards/arm/stm32/olimex-stm32-p107/scripts/Make.defs +++ /dev/null @@ -1,46 +0,0 @@ -############################################################################ -# boards/arm/stm32/olimex-stm32-p107/scripts/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/.config -include $(TOPDIR)/tools/Config.mk -include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs - -ifeq ($(CONFIG_STM32_DFU),y) - LDSCRIPT = ld.script.dfu -else - LDSCRIPT = ld.script -endif - -ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) - -ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 - -CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) -CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) -CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -AFLAGS := $(CFLAGS) -D__ASSEMBLY__ - -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-gotoff.ld -no-check-sections -LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32/olimex-stm32-p107/scripts/ld.script b/boards/arm/stm32/olimex-stm32-p107/scripts/ld.script deleted file mode 100644 index a0144f22e74c8..0000000000000 --- a/boards/arm/stm32/olimex-stm32-p107/scripts/ld.script +++ /dev/null @@ -1,115 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/olimex-stm32-p107/scripts/ld.script - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -MEMORY -{ - flash (rx) : ORIGIN = 0x08000000, LENGTH = 256K - sram (rwx) : ORIGIN = 0x20000000, LENGTH = 64K -} - -OUTPUT_ARCH(arm) -EXTERN(_vectors) -ENTRY(_stext) -SECTIONS -{ - .text : { - _stext = ABSOLUTE(.); - *(.vectors) - *(.text .text.*) - *(.fixup) - *(.gnu.warning) - *(.rodata .rodata.*) - *(.gnu.linkonce.t.*) - *(.glue_7) - *(.glue_7t) - *(.got) - *(.gcc_except_table) - *(.gnu.linkonce.r.*) - _etext = ABSOLUTE(.); - } > flash - - .init_section : ALIGN(4) { - _sinit = ABSOLUTE(.); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) - KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) - _einit = ABSOLUTE(.); - } > flash - - .ARM.extab : ALIGN(4) { - *(.ARM.extab*) - } > flash - - .ARM.exidx : ALIGN(4) { - __exidx_start = ABSOLUTE(.); - *(.ARM.exidx*) - __exidx_end = ABSOLUTE(.); - } > flash - - .tdata : { - _stdata = ABSOLUTE(.); - *(.tdata .tdata.* .gnu.linkonce.td.*); - _etdata = ABSOLUTE(.); - } > flash - - .tbss : { - _stbss = ABSOLUTE(.); - *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); - _etbss = ABSOLUTE(.); - } > flash - - _eronly = ABSOLUTE(.); - - /* The STM32F107VC has 64Kb of SRAM beginning at the following address */ - - .data : ALIGN(4) { - _sdata = ABSOLUTE(.); - *(.data .data.*) - *(.gnu.linkonce.d.*) - CONSTRUCTORS - . = ALIGN(4); - _edata = ABSOLUTE(.); - } > sram AT > flash - - .bss : ALIGN(4) { - _sbss = ABSOLUTE(.); - *(.bss .bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - . = ALIGN(4); - _ebss = ABSOLUTE(.); - } > sram - - /* Stabs debugging sections. */ - - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_info 0 : { *(.debug_info) } - .debug_line 0 : { *(.debug_line) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_aranges 0 : { *(.debug_aranges) } -} diff --git a/boards/arm/stm32/olimex-stm32-p107/scripts/ld.script.dfu b/boards/arm/stm32/olimex-stm32-p107/scripts/ld.script.dfu deleted file mode 100644 index 9a2251caf1a65..0000000000000 --- a/boards/arm/stm32/olimex-stm32-p107/scripts/ld.script.dfu +++ /dev/null @@ -1,101 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/olimex-stm32-p107/scripts/ld.script.dfu - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* Don't know if this is correct. Just 256K-48K (not testet) */ -MEMORY -{ - flash (rx) : ORIGIN = 0x08003000, LENGTH = 208K - sram (rwx) : ORIGIN = 0x20000000, LENGTH = 64K -} - -OUTPUT_ARCH(arm) -EXTERN(_vectors) -ENTRY(_stext) -SECTIONS -{ - .text : { - _stext = ABSOLUTE(.); - *(.vectors) - *(.text .text.*) - *(.fixup) - *(.gnu.warning) - *(.rodata .rodata.*) - *(.gnu.linkonce.t.*) - *(.glue_7) - *(.glue_7t) - *(.got) - *(.gcc_except_table) - *(.gnu.linkonce.r.*) - _etext = ABSOLUTE(.); - } > flash - - .init_section : ALIGN(4) { - _sinit = ABSOLUTE(.); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) - KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) - _einit = ABSOLUTE(.); - } > flash - - .ARM.extab : ALIGN(4) { - *(.ARM.extab*) - } > flash - - .ARM.exidx : ALIGN(4) { - __exidx_start = ABSOLUTE(.); - *(.ARM.exidx*) - __exidx_end = ABSOLUTE(.); - } > flash - - _eronly = ABSOLUTE(.); - - /* The STM32F103Z has 64Kb of SRAM beginning at the following address */ - - .data : ALIGN(4) { - _sdata = ABSOLUTE(.); - *(.data .data.*) - *(.gnu.linkonce.d.*) - CONSTRUCTORS - _edata = ABSOLUTE(.); - } > sram AT > flash - - .bss : ALIGN(4) { - _sbss = ABSOLUTE(.); - *(.bss .bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - _ebss = ABSOLUTE(.); - } > sram - - /* Stabs debugging sections. */ - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_info 0 : { *(.debug_info) } - .debug_line 0 : { *(.debug_line) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_aranges 0 : { *(.debug_aranges) } -} diff --git a/boards/arm/stm32/olimex-stm32-p107/src/CMakeLists.txt b/boards/arm/stm32/olimex-stm32-p107/src/CMakeLists.txt deleted file mode 100644 index 0e5286c799dbe..0000000000000 --- a/boards/arm/stm32/olimex-stm32-p107/src/CMakeLists.txt +++ /dev/null @@ -1,35 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/olimex-stm32-p107/src/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -set(SRCS stm32_boot.c stm32_spi.c) - -if(CONFIG_STM32_CAN_CHARDRIVER) - list(APPEND SRCS stm32_can.c) -endif() - -if(CONFIG_ENCX24J600) - list(APPEND SRCS stm32_encx24j600.c) -endif() - -target_sources(board PRIVATE ${SRCS}) - -set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/ld.script") diff --git a/boards/arm/stm32/olimex-stm32-p107/src/Make.defs b/boards/arm/stm32/olimex-stm32-p107/src/Make.defs deleted file mode 100644 index d7aa1806f7391..0000000000000 --- a/boards/arm/stm32/olimex-stm32-p107/src/Make.defs +++ /dev/null @@ -1,37 +0,0 @@ -############################################################################ -# boards/arm/stm32/olimex-stm32-p107/src/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/Make.defs - -CSRCS = stm32_boot.c stm32_spi.c - -ifeq ($(CONFIG_STM32_CAN_CHARDRIVER),y) -CSRCS += stm32_can.c -endif - -ifeq ($(CONFIG_ENCX24J600),y) -CSRCS += stm32_encx24j600.c -endif - -DEPPATH += --dep-path board -VPATH += :board -CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/olimex-stm32-p107/src/stm32_boot.c b/boards/arm/stm32/olimex-stm32-p107/src/stm32_boot.c deleted file mode 100644 index 729ccbe7e16eb..0000000000000 --- a/boards/arm/stm32/olimex-stm32-p107/src/stm32_boot.c +++ /dev/null @@ -1,99 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/olimex-stm32-p107/src/stm32_boot.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include -#include - -#include -#include -#include - -#include "stm32.h" -#include "arm_internal.h" -#include "olimex-stm32-p107.h" - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_boardinitialize - * - * Description: - * All STM32 architectures must provide the following entry point. - * This entry point is called early in the initialization -- after all - * memory has been configured and mapped but before any devices have been - * initialized. - * - ****************************************************************************/ - -void stm32_boardinitialize(void) -{ - /* Configure SPI chip selects if 1) SPI is not disabled, and 2) the weak - * function stm32_spidev_initialize() has been brought into the link. - */ - -#if defined(CONFIG_STM32_SPI3) - if (stm32_spidev_initialize) - { - stm32_spidev_initialize(); - } -#endif -} - -/**************************************************************************** - * Name: board_late_initialize - * - * Description: - * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional - * initialization call will be performed in the boot-up sequence to a - * function called board_late_initialize(). board_late_initialize() will - * be called immediately after up_initialize() is called and just before - * the initial application is started. - * This additional initialization phase may be used, for example, to - * initialize board-specific device drivers. - * - ****************************************************************************/ - -#ifdef CONFIG_BOARD_LATE_INITIALIZE -void board_late_initialize(void) -{ - int ret; - -#ifdef CONFIG_STM32_CAN_CHARDRIVER - /* Initialize CAN and register the CAN driver. */ - - ret = stm32_can_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_can_setup failed: %d\n", ret); - } -#endif - - UNUSED(ret); -} -#endif diff --git a/boards/arm/stm32/olimex-stm32-p107/src/stm32_can.c b/boards/arm/stm32/olimex-stm32-p107/src/stm32_can.c deleted file mode 100644 index 1836835c4bcc5..0000000000000 --- a/boards/arm/stm32/olimex-stm32-p107/src/stm32_can.c +++ /dev/null @@ -1,103 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/olimex-stm32-p107/src/stm32_can.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32.h" -#include "stm32_can.h" - -#ifdef CONFIG_CAN - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -/* The STM32F107VC supports CAN1 and CAN2 */ - -#if defined(CONFIG_STM32_CAN1) && defined(CONFIG_STM32_CAN2) -# warning "Both CAN1 and CAN2 are enabled. Only CAN1 is used." -# undef CONFIG_STM32_CAN2 -#endif - -#ifdef CONFIG_STM32_CAN1 -# define CAN_PORT 1 -#else -# define CAN_PORT 2 -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_can_setup - * - * Description: - * Initialize CAN and register the CAN device - * - ****************************************************************************/ - -int stm32_can_setup(void) -{ -#if defined(CONFIG_STM32_CAN1) || defined(CONFIG_STM32_CAN2) - struct can_dev_s *can; - int ret; - - /* Call stm32_caninitialize() to get an instance of the CAN interface */ - - can = stm32_caninitialize(CAN_PORT); - if (can == NULL) - { - canerr("ERROR: Failed to get CAN interface\n"); - return -ENODEV; - } - - /* Register the CAN driver at "/dev/can0" */ - - ret = can_register("/dev/can0", can); - if (ret < 0) - { - canerr("ERROR: can_register failed: %d\n", ret); - return ret; - } - - return OK; -#else - return -ENODEV; -#endif -} - -#endif /* CONFIG_CAN */ diff --git a/boards/arm/stm32/olimex-stm32-p107/src/stm32_spi.c b/boards/arm/stm32/olimex-stm32-p107/src/stm32_spi.c deleted file mode 100644 index 62ae40b65edd0..0000000000000 --- a/boards/arm/stm32/olimex-stm32-p107/src/stm32_spi.c +++ /dev/null @@ -1,121 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/olimex-stm32-p107/src/stm32_spi.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include "arm_internal.h" -#include "chip.h" -#include "stm32.h" - -#include "olimex-stm32-p107.h" - -#if defined(CONFIG_STM32_SPI3) - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_spidev_initialize - * - * Description: - * Called to configure SPI chip select GPIO pins for the Olimex stm32-p107 - * board. - * - ****************************************************************************/ - -void weak_function stm32_spidev_initialize(void) -{ - /* NOTE: Clocking for SPI3 was already provided in stm32_rcc.c. - * Configurations of SPI pins is performed in stm32_spi.c. - * Here, we only initialize chip select pins unique to the board - * architecture. - */ - - /* Configure ENCX24J600 SPI1 CS (also RESET and interrupt pins) */ - -#if defined(CONFIG_ENCX24J600) && defined(CONFIG_STM32_SPI3) - stm32_configgpio(GPIO_ENCX24J600_CS); - stm32_configgpio(GPIO_ENCX24J600_INTR); -#endif -} - -/**************************************************************************** - * Name: stm32_spi1/2/3select and stm32_spi1/2/3status - * - * Description: - * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status - * must be provided by board-specific logic. They are implementations of - * the select and status methods of the SPI interface defined by struct - * spi_ops_s (see include/nuttx/spi/spi.h). All other methods - * (including stm32_spibus_initialize()) are provided by common STM32 - * logic. To use this common SPI logic on your board: - * - * 1. Provide logic in stm32_boardinitialize() to configure SPI chip select - * pins. - * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() functions - * in your board-specific logic. These functions will perform chip - * selection and status operations using GPIOs in the way your board is - * configured. - * 3. Add a calls to stm32_spibus_initialize() in your low level - * application initialization logic - * 4. The handle returned by stm32_spibus_initialize() may then be used to - * bind the SPI driver to higher level logic (e.g., calling - * mmcsd_spislotinitialize(), for example, will bind the SPI driver to - * the SPI MMC/SD driver). - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_SPI3 -void stm32_spi3select(struct spi_dev_s *dev, - uint32_t devid, - bool selected) -{ - spiinfo("devid: %d CS: %s\n", - (int)devid, selected ? "assert" : "de-assert"); - - if (devid == SPIDEV_ETHERNET(0)) - { - /* Set the GPIO low to select and high to de-select */ - - stm32_gpiowrite(GPIO_ENCX24J600_CS, !selected); - } -} - -uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid) -{ - return SPI_STATUS_PRESENT; -} -#endif - -#endif /* CONFIG_STM32_SPI3 */ diff --git a/boards/arm/stm32/olimex-stm32-p207/CMakeLists.txt b/boards/arm/stm32/olimex-stm32-p207/CMakeLists.txt deleted file mode 100644 index e80a16fed32e0..0000000000000 --- a/boards/arm/stm32/olimex-stm32-p207/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/olimex-stm32-p207/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32/olimex-stm32-p207/configs/nsh/defconfig b/boards/arm/stm32/olimex-stm32-p207/configs/nsh/defconfig deleted file mode 100644 index 4e50e59cce329..0000000000000 --- a/boards/arm/stm32/olimex-stm32-p207/configs/nsh/defconfig +++ /dev/null @@ -1,81 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_NSH_DISABLE_IFCONFIG is not set -# CONFIG_NSH_DISABLE_PS is not set -CONFIG_ADC=y -CONFIG_ANALOG=y -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="olimex-stm32-p207" -CONFIG_ARCH_BOARD_OLIMEX_STM32P207=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F207ZE=y -CONFIG_ARCH_IRQBUTTONS=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_ARM_TOOLCHAIN_BUILDROOT=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_ETH0_PHY_KS8721=y -CONFIG_EXAMPLES_ADC=y -CONFIG_EXAMPLES_ADC_GROUPSIZE=1 -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_MM_REGIONS=2 -CONFIG_NET=y -CONFIG_NETDB_DNSCLIENT=y -CONFIG_NETINIT_DRIPADDR=0xa0000001 -CONFIG_NETINIT_IPADDR=0xa0000002 -CONFIG_NETINIT_NOMAC=y -CONFIG_NET_ICMP_SOCKET=y -CONFIG_NET_STATISTICS=y -CONFIG_NET_TCP=y -CONFIG_NET_UDP=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_DISABLE_GET=y -CONFIG_NSH_DISABLE_PUT=y -CONFIG_NSH_DISABLE_WGET=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_HPWORKPRIORITY=192 -CONFIG_SCHED_WAITPID=y -CONFIG_START_YEAR=2013 -CONFIG_STM32_ADC1=y -CONFIG_STM32_CAN1=y -CONFIG_STM32_CAN_TSEG2=8 -CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32_ETHMAC=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_OTGFS=y -CONFIG_STM32_PHYSR=31 -CONFIG_STM32_PHYSR_100FD=0x18 -CONFIG_STM32_PHYSR_100HD=0x8 -CONFIG_STM32_PHYSR_10FD=0x14 -CONFIG_STM32_PHYSR_10HD=0x4 -CONFIG_STM32_PHYSR_ALTCONFIG=y -CONFIG_STM32_PHYSR_ALTMODE=0x1c -CONFIG_STM32_PWR=y -CONFIG_STM32_RMII_EXTCLK=y -CONFIG_STM32_TIM1=y -CONFIG_STM32_TIM1_ADC=y -CONFIG_STM32_USART3=y -CONFIG_SYSTEM_NSH=y -CONFIG_SYSTEM_PING=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART3_SERIAL_CONSOLE=y -CONFIG_USBHOST=y diff --git a/boards/arm/stm32/olimex-stm32-p207/include/board.h b/boards/arm/stm32/olimex-stm32-p207/include/board.h deleted file mode 100644 index 6a632373c9bc5..0000000000000 --- a/boards/arm/stm32/olimex-stm32-p207/include/board.h +++ /dev/null @@ -1,241 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/olimex-stm32-p207/include/board.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __BOARDS_ARM_STM32_OLIMEX_STM32_P207_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32_OLIMEX_STM32_P207_INCLUDE_BOARD_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#ifndef __ASSEMBLY__ -# include -#endif - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Clocking *****************************************************************/ - -/* HSI - 16 MHz RC factory-trimmed - * LSI - 32 KHz RC (30-60KHz, uncalibrated) - * HSE - On-board crystal frequency is 25MHz - * LSE - 32.768 kHz - */ - -#define STM32_BOARD_XTAL 25000000ul - -#define STM32_HSI_FREQUENCY 16000000ul -#define STM32_LSI_FREQUENCY 32000 -#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL -#define STM32_LSE_FREQUENCY 32768 - -/* Main PLL Configuration. - * - * PLL source is HSE - * PLL_VCO = (STM32_HSE_FREQUENCY / PLLM) * PLLN - * = (25,000,000 / 25) * 240 - * = 240,000,000 - * SYSCLK = PLL_VCO / PLLP - * = 240,000,000 / 2 = 120,000,000 - * USB OTG FS, SDIO and RNG Clock - * = PLL_VCO / PLLQ - * = 240,000,000 / 5 = 48,000,000 - * = 48,000,000 - */ - -#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(25) -#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(240) -#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_2 -#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(5) - -#define STM32_SYSCLK_FREQUENCY 120000000ul - -/* AHB clock (HCLK) is SYSCLK (120MHz) */ - -#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ -#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY - -/* APB1 clock (PCLK1) is HCLK/4 (30MHz) */ - -#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd4 /* PCLK1 = HCLK / 4 */ -#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/4) - -/* Timers driven from APB1 will be twice PCLK1 (60Mhz) */ - -#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) - -/* APB2 clock (PCLK2) is HCLK/2 (60MHz) */ - -#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLKd2 /* PCLK2 = HCLK / 2 */ -#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/2) - -/* Timers driven from APB2 will be twice PCLK2 (120Mhz) */ - -#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM9_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM10_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM11_CLKIN (2*STM32_PCLK2_FREQUENCY) - -/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx - * otherwise frequency is 2xAPBx. - * Note: TIM1,8 are on APB2, others on APB1 - */ - -#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM2_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM3_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM4_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM5_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM6_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM7_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY - -/* LED definitions **********************************************************/ - -/* If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs in - * any way. The following definitions are used to access individual LEDs. - */ - -/* LED index values for use with board_userled() */ - -#define BOARD_LED1 0 -#define BOARD_LED2 1 -#define BOARD_LED3 2 -#define BOARD_LED4 3 -#define BOARD_NLEDS 4 - -#define BOARD_LED_GREEN1 BOARD_LED1 -#define BOARD_LED_YELLOW BOARD_LED2 -#define BOARD_LED_RED BOARD_LED3 -#define BOARD_LED_GREEN2 BOARD_LED4 - -/* LED bits for use with board_userled_all() */ - -#define BOARD_LED1_BIT (1 << BOARD_LED1) -#define BOARD_LED2_BIT (1 << BOARD_LED2) -#define BOARD_LED3_BIT (1 << BOARD_LED3) -#define BOARD_LED4_BIT (1 << BOARD_LED4) - -/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the 4 LEDs on - * board the Olimex STM32-P207. - * The following definitions describe how NuttX controls the LEDs: - */ - -#define LED_STARTED 0 /* LED1 */ -#define LED_HEAPALLOCATE 1 /* LED2 */ -#define LED_IRQSENABLED 2 /* LED1 + LED2 */ -#define LED_STACKCREATED 3 /* LED3 */ -#define LED_INIRQ 4 /* LED1 + LED3 */ -#define LED_SIGNAL 5 /* LED2 + LED3 */ -#define LED_ASSERTION 6 /* LED1 + LED2 + LED3 */ -#define LED_PANIC 7 /* N/C + N/C + N/C + LED4 */ - -/* Button definitions *******************************************************/ - -/* The Olimex STM32-P207 supports seven buttons: */ - -#define BUTTON_TAMPER 0 -#define BUTTON_WKUP 1 -#define BUTTON_RIGHT 2 -#define BUTTON_UP 3 -#define BUTTON_LEFT 4 -#define BUTTON_DOWN 5 -#define BUTTON_CENTER 6 - -#define NUM_BUTTONS 7 - -#define BUTTON_TAMPER_BIT (1 << BUTTON_TAMPER) -#define BUTTON_WKUP_BIT (1 << BUTTON_WKUP) -#define BUTTON_RIGHT_BIT (1 << BUTTON_RIGHT) -#define BUTTON_UP_BIT (1 << BUTTON_UP) -#define BUTTON_LEFT_BIT (1 << BUTTON_LEFT) -#define BUTTON_DOWN_BIT (1 << BUTTON_DOWN) -#define BUTTON_CENTER_BIT (1 << BUTTON_CENTER) - -/* Alternate function pin selections ****************************************/ - -/* USART3: */ -#define GPIO_USART3_RX (GPIO_USART3_RX_3|GPIO_SPEED_100MHz) /* PD9 */ -#define GPIO_USART3_TX (GPIO_USART3_TX_3|GPIO_SPEED_100MHz) /* PD8 */ -#define GPIO_USART3_CTS GPIO_USART3_CTS_2 /* PD11 */ -#define GPIO_USART3_RTS GPIO_USART3_RTS_2 /* PD12 */ - -/* CAN: */ -#define GPIO_CAN1_RX (GPIO_CAN1_RX_2|GPIO_SPEED_50MHz) /* PB8 */ -#define GPIO_CAN1_TX (GPIO_CAN1_TX_2|GPIO_SPEED_50MHz) /* PB9 */ - -/* Ethernet: */ - -/* - PA2 is ETH_MDIO - * - PC1 is ETH_MDC - * - PB5 is ETH_PPS_OUT - NC (not connected) - * - PA0 is ETH_MII_CRS - NC - * - PA3 is ETH_MII_COL - NC - * - PB10 is ETH_MII_RX_ER - NC - * - PB0 is ETH_MII_RXD2 - NC - * - PH7 is ETH_MII_RXD3 - NC - * - PC3 is ETH_MII_TX_CLK - NC - * - PC2 is ETH_MII_TXD2 - NC - * - PB8 is ETH_MII_TXD3 - NC - * - PA1 is ETH_MII_RX_CLK/ETH_RMII_REF_CLK - * - PA7 is ETH_MII_RX_DV/ETH_RMII_CRS_DV - * - PC4 is ETH_MII_RXD0/ETH_RMII_RXD0 - * - PC5 is ETH_MII_RXD1/ETH_RMII_RXD1 - * - PB11 is ETH_MII_TX_EN/ETH_RMII_TX_EN - * - PG13 is ETH_MII_TXD0/ETH_RMII_TXD0 - * - PG14 is ETH_MII_TXD1/ETH_RMII_TXD1 - */ - -#define GPIO_ETH_MDC (GPIO_ETH_MDC_0|GPIO_SPEED_100MHz) -#define GPIO_ETH_MDIO (GPIO_ETH_MDIO_0|GPIO_SPEED_100MHz) -#define GPIO_ETH_RMII_CRS_DV (GPIO_ETH_RMII_CRS_DV_0|GPIO_SPEED_100MHz) -#define GPIO_ETH_RMII_REF_CLK (GPIO_ETH_RMII_REF_CLK_0|GPIO_SPEED_100MHz) -#define GPIO_ETH_RMII_RXD0 (GPIO_ETH_RMII_RXD0_0|GPIO_SPEED_100MHz) -#define GPIO_ETH_RMII_RXD1 (GPIO_ETH_RMII_RXD1_0|GPIO_SPEED_100MHz) -#define GPIO_ETH_PPS_OUT (GPIO_ETH_PPS_OUT_1|GPIO_SPEED_100MHz) -#define GPIO_ETH_MII_CRS (GPIO_ETH_MII_CRS_1|GPIO_SPEED_100MHz) -#define GPIO_ETH_MII_COL (GPIO_ETH_MII_COL_1|GPIO_SPEED_100MHz) -#define GPIO_ETH_MII_RX_ER (GPIO_ETH_MII_RX_ER_1|GPIO_SPEED_100MHz) -#define GPIO_ETH_MII_RXD2 (GPIO_ETH_MII_RXD2_1|GPIO_SPEED_100MHz) -#define GPIO_ETH_MII_RXD3 (GPIO_ETH_MII_RXD3_1|GPIO_SPEED_100MHz) -#define GPIO_ETH_MII_TXD3 (GPIO_ETH_MII_TXD3_1|GPIO_SPEED_100MHz) -#define GPIO_ETH_MII_TX_EN (GPIO_ETH_MII_TX_EN_2|GPIO_SPEED_100MHz) -#define GPIO_ETH_MII_TXD0 (GPIO_ETH_MII_TXD0_2|GPIO_SPEED_100MHz) -#define GPIO_ETH_MII_TXD1 (GPIO_ETH_MII_TXD1_2|GPIO_SPEED_100MHz) -#define GPIO_ETH_RMII_TX_EN (GPIO_ETH_RMII_TX_EN_1|GPIO_SPEED_100MHz) -#define GPIO_ETH_RMII_TXD0 (GPIO_ETH_RMII_TXD0_2|GPIO_SPEED_100MHz) -#define GPIO_ETH_RMII_TXD1 (GPIO_ETH_RMII_TXD1_2|GPIO_SPEED_100MHz) - -#endif /* __BOARDS_ARM_STM32_OLIMEX_STM32_P207_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32/olimex-stm32-p207/scripts/Make.defs b/boards/arm/stm32/olimex-stm32-p207/scripts/Make.defs deleted file mode 100644 index 9aaebcbad7a64..0000000000000 --- a/boards/arm/stm32/olimex-stm32-p207/scripts/Make.defs +++ /dev/null @@ -1,41 +0,0 @@ -############################################################################ -# boards/arm/stm32/olimex-stm32-p207/scripts/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/.config -include $(TOPDIR)/tools/Config.mk -include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs - -LDSCRIPT = ld.script -ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) - -ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 - -CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) -CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) -CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -AFLAGS := $(CFLAGS) -D__ASSEMBLY__ - -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-gotoff.ld -no-check-sections -LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32/olimex-stm32-p207/scripts/ld.script b/boards/arm/stm32/olimex-stm32-p207/scripts/ld.script deleted file mode 100644 index d8e4a95fc739c..0000000000000 --- a/boards/arm/stm32/olimex-stm32-p207/scripts/ld.script +++ /dev/null @@ -1,125 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/olimex-stm32-p207/scripts/ld.script - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* The STM32F207ZET6 has 512Kb of FLASH beginning at address 0x0800:0000 and - * 128Kb of SRAM. SRAM is split up into two blocks: - * - * 1) 112Kb of SRAM beginning at address 0x2000:0000 - * 2) 16Kb of SRAM beginning at address 0x2001:c000 - * - * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 - * where the code expects to begin execution by jumping to the entry point in - * the 0x0800:0000 address - * range. - */ - -MEMORY -{ - flash (rx) : ORIGIN = 0x08000000, LENGTH = 512K - sram (rwx) : ORIGIN = 0x20000000, LENGTH = 112K -} - -OUTPUT_ARCH(arm) -EXTERN(_vectors) -ENTRY(_stext) -SECTIONS -{ - .text : { - _stext = ABSOLUTE(.); - *(.vectors) - *(.text .text.*) - *(.fixup) - *(.gnu.warning) - *(.rodata .rodata.*) - *(.gnu.linkonce.t.*) - *(.glue_7) - *(.glue_7t) - *(.got) - *(.gcc_except_table) - *(.gnu.linkonce.r.*) - _etext = ABSOLUTE(.); - } > flash - - .init_section : ALIGN(4) { - _sinit = ABSOLUTE(.); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) - KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) - _einit = ABSOLUTE(.); - } > flash - - .ARM.extab : ALIGN(4) { - *(.ARM.extab*) - } > flash - - .ARM.exidx : ALIGN(4) { - __exidx_start = ABSOLUTE(.); - *(.ARM.exidx*) - __exidx_end = ABSOLUTE(.); - } > flash - - .tdata : { - _stdata = ABSOLUTE(.); - *(.tdata .tdata.* .gnu.linkonce.td.*); - _etdata = ABSOLUTE(.); - } > flash - - .tbss : { - _stbss = ABSOLUTE(.); - *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); - _etbss = ABSOLUTE(.); - } > flash - - _eronly = ABSOLUTE(.); - - .data : ALIGN(4) { - _sdata = ABSOLUTE(.); - *(.data .data.*) - *(.gnu.linkonce.d.*) - CONSTRUCTORS - . = ALIGN(4); - _edata = ABSOLUTE(.); - } > sram AT > flash - - .bss : ALIGN(4) { - _sbss = ABSOLUTE(.); - *(.bss .bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - . = ALIGN(4); - _ebss = ABSOLUTE(.); - } > sram - - /* Stabs debugging sections. */ - - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_info 0 : { *(.debug_info) } - .debug_line 0 : { *(.debug_line) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_aranges 0 : { *(.debug_aranges) } -} diff --git a/boards/arm/stm32/olimex-stm32-p207/src/CMakeLists.txt b/boards/arm/stm32/olimex-stm32-p207/src/CMakeLists.txt deleted file mode 100644 index 98fcae67692dc..0000000000000 --- a/boards/arm/stm32/olimex-stm32-p207/src/CMakeLists.txt +++ /dev/null @@ -1,49 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/olimex-stm32-p207/src/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -set(SRCS stm32_boot.c) - -if(CONFIG_ARCH_LEDS) - list(APPEND SRCS stm32_autoleds.c) -else() - list(APPEND SRCS stm32_userleds.c) -endif() - -if(CONFIG_ARCH_BUTTONS) - list(APPEND SRCS stm32_buttons.c) -endif() - -if(CONFIG_STM32_OTGFS) - list(APPEND SRCS stm32_usb.c) -endif() - -if(CONFIG_ADC) - list(APPEND SRCS stm32_adc.c) -endif() - -if(CONFIG_STM32_CAN_CHARDRIVER) - list(APPEND SRCS stm32_can.c) -endif() - -target_sources(board PRIVATE ${SRCS}) - -set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/ld.script") diff --git a/boards/arm/stm32/olimex-stm32-p207/src/Make.defs b/boards/arm/stm32/olimex-stm32-p207/src/Make.defs deleted file mode 100644 index 42ceed74368d7..0000000000000 --- a/boards/arm/stm32/olimex-stm32-p207/src/Make.defs +++ /dev/null @@ -1,51 +0,0 @@ -############################################################################ -# boards/arm/stm32/olimex-stm32-p207/src/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/Make.defs - -CSRCS = stm32_boot.c - -ifeq ($(CONFIG_ARCH_LEDS),y) -CSRCS += stm32_autoleds.c -else -CSRCS += stm32_userleds.c -endif - -ifeq ($(CONFIG_ARCH_BUTTONS),y) -CSRCS += stm32_buttons.c -endif - -ifeq ($(CONFIG_STM32_OTGFS),y) -CSRCS += stm32_usb.c -endif - -ifeq ($(CONFIG_ADC),y) -CSRCS += stm32_adc.c -endif - -ifeq ($(CONFIG_STM32_CAN_CHARDRIVER),y) -CSRCS += stm32_can.c -endif - -DEPPATH += --dep-path board -VPATH += :board -CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/olimex-stm32-p207/src/stm32_adc.c b/boards/arm/stm32/olimex-stm32-p207/src/stm32_adc.c deleted file mode 100644 index 8224185440092..0000000000000 --- a/boards/arm/stm32/olimex-stm32-p207/src/stm32_adc.c +++ /dev/null @@ -1,156 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/olimex-stm32-p207/src/stm32_adc.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include -#include - -#include "chip.h" -#include "stm32_adc.h" -#include "olimex-stm32-p207.h" - -#ifdef CONFIG_ADC - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -/* Up to 3 ADC interfaces are supported */ - -#if STM32_NADC < 3 -# undef CONFIG_STM32_ADC3 -#endif - -#if STM32_NADC < 2 -# undef CONFIG_STM32_ADC2 -#endif - -#if STM32_NADC < 1 -# undef CONFIG_STM32_ADC1 -#endif - -#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) || defined(CONFIG_STM32_ADC3) -#ifndef CONFIG_STM32_ADC1 -# warning "Channel information only available for ADC1" -#endif - -/* The number of ADC channels in the conversion list */ - -#define ADC1_NCHANNELS 1 - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* The Olimex STM32-P207 has a 10 Kohm potentiometer AN_TR connected to PC0 - * ADC123_IN10 - */ - -/* Identifying number of each ADC channel: Variable Resistor. */ - -#ifdef CONFIG_STM32_ADC1 -static const uint8_t g_chanlist[ADC1_NCHANNELS] = -{ - 10 -}; - -/* Configurations of pins used byte each ADC channels */ - -static const uint32_t g_pinlist[ADC1_NCHANNELS] = -{ - GPIO_ADC1_IN10_0 -}; -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_adc_setup - * - * Description: - * Initialize ADC and register the ADC driver. - * - ****************************************************************************/ - -int stm32_adc_setup(void) -{ -#ifdef CONFIG_STM32_ADC1 - static bool initialized = false; - struct adc_dev_s *adc; - int ret; - int i; - - /* Check if we have already initialized */ - - if (!initialized) - { - /* Configure the pins as analog inputs for the selected channels */ - - for (i = 0; i < ADC1_NCHANNELS; i++) - { - stm32_configgpio(g_pinlist[i]); - } - - /* Call stm32_adcinitialize() to get an instance of the ADC interface */ - - adc = stm32_adcinitialize(1, g_chanlist, ADC1_NCHANNELS); - if (adc == NULL) - { - aerr("ERROR: Failed to get ADC interface\n"); - return -ENODEV; - } - - /* Register the ADC driver at "/dev/adc0" */ - - ret = adc_register("/dev/adc0", adc); - if (ret < 0) - { - aerr("ERROR: adc_register failed: %d\n", ret); - return ret; - } - - /* Now we are initialized */ - - initialized = true; - } - - return OK; -#else - return -ENOSYS; -#endif -} - -#endif /* CONFIG_STM32_ADC1 || CONFIG_STM32_ADC2 || CONFIG_STM32_ADC3 */ -#endif /* CONFIG_ADC */ diff --git a/boards/arm/stm32/olimex-stm32-p207/src/stm32_autoleds.c b/boards/arm/stm32/olimex-stm32-p207/src/stm32_autoleds.c deleted file mode 100644 index 7455e3582f3c9..0000000000000 --- a/boards/arm/stm32/olimex-stm32-p207/src/stm32_autoleds.c +++ /dev/null @@ -1,160 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/olimex-stm32-p207/src/stm32_autoleds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include "stm32.h" -#include "olimex-stm32-p207.h" - -#ifdef CONFIG_ARCH_LEDS - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* The following definitions map the encoded LED setting to GPIO settings */ - -#define LED_STARTED_BITS (BOARD_LED1_BIT) -#define LED_HEAPALLOCATE_BITS (BOARD_LED2_BIT) -#define LED_IRQSENABLED_BITS (BOARD_LED1_BIT | BOARD_LED2_BIT) -#define LED_STACKCREATED_BITS (BOARD_LED3_BIT) -#define LED_INIRQ_BITS (BOARD_LED1_BIT | BOARD_LED3_BIT) -#define LED_SIGNAL_BITS (BOARD_LED2_BIT | BOARD_LED3_BIT) -#define LED_ASSERTION_BITS (BOARD_LED1_BIT | BOARD_LED2_BIT | BOARD_LED3_BIT) -#define LED_PANIC_BITS (BOARD_LED4_BIT) - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -static const unsigned int g_ledbits[8] = -{ - LED_STARTED_BITS, - LED_HEAPALLOCATE_BITS, - LED_IRQSENABLED_BITS, - LED_STACKCREATED_BITS, - LED_INIRQ_BITS, - LED_SIGNAL_BITS, - LED_ASSERTION_BITS, - LED_PANIC_BITS -}; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -static inline void led_clrbits(unsigned int clrbits) -{ - if ((clrbits & BOARD_LED1_BIT) != 0) - { - stm32_gpiowrite(GPIO_LED1, false); - } - - if ((clrbits & BOARD_LED2_BIT) != 0) - { - stm32_gpiowrite(GPIO_LED2, false); - } - - if ((clrbits & BOARD_LED3_BIT) != 0) - { - stm32_gpiowrite(GPIO_LED3, false); - } - - if ((clrbits & BOARD_LED4_BIT) != 0) - { - stm32_gpiowrite(GPIO_LED4, false); - } -} - -static inline void led_setbits(unsigned int setbits) -{ - if ((setbits & BOARD_LED1_BIT) != 0) - { - stm32_gpiowrite(GPIO_LED1, true); - } - - if ((setbits & BOARD_LED2_BIT) != 0) - { - stm32_gpiowrite(GPIO_LED2, true); - } - - if ((setbits & BOARD_LED3_BIT) != 0) - { - stm32_gpiowrite(GPIO_LED3, true); - } - - if ((setbits & BOARD_LED4_BIT) != 0) - { - stm32_gpiowrite(GPIO_LED4, true); - } -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_autoled_initialize - ****************************************************************************/ - -void board_autoled_initialize(void) -{ - /* Configure LED1-4 GPIOs for output */ - - stm32_configgpio(GPIO_LED1); - stm32_configgpio(GPIO_LED2); - stm32_configgpio(GPIO_LED3); - stm32_configgpio(GPIO_LED4); -} - -/**************************************************************************** - * Name: board_autoled_on - ****************************************************************************/ - -void board_autoled_on(int led) -{ - led_clrbits(BOARD_LED1_BIT | BOARD_LED2_BIT | - BOARD_LED3_BIT | BOARD_LED4_BIT); - led_setbits(g_ledbits[led]); -} - -/**************************************************************************** - * Name: board_autoled_off - ****************************************************************************/ - -void board_autoled_off(int led) -{ - led_clrbits(g_ledbits[led]); -} - -#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/olimex-stm32-p207/src/stm32_boot.c b/boards/arm/stm32/olimex-stm32-p207/src/stm32_boot.c deleted file mode 100644 index 3ce6df06ea461..0000000000000 --- a/boards/arm/stm32/olimex-stm32-p207/src/stm32_boot.c +++ /dev/null @@ -1,205 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/olimex-stm32-p207/src/stm32_boot.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include -#include -#include -#include - -#include -#include -#include - -#ifdef CONFIG_USBMONITOR -# include -#endif - -#ifdef CONFIG_STM32_OTGFS -# include "stm32_usbhost.h" -#endif - -#include "stm32.h" -#include "olimex-stm32-p207.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -#define HAVE_USBDEV 1 -#define HAVE_USBHOST 1 -#define HAVE_USBMONITOR 1 - -/* Can't support USB host or device features if USB OTG FS is not enabled */ - -#ifndef CONFIG_STM32_OTGFS -# undef HAVE_USBDEV -# undef HAVE_USBHOST -#endif - -/* Can't support USB device if USB device is not enabled */ - -#ifndef CONFIG_USBDEV -# undef HAVE_USBDEV -#endif - -/* Can't support USB host is USB host is not enabled */ - -#ifndef CONFIG_STM32_USBHOST -# undef CONFIG_USBHOST -# undef HAVE_USBHOST -#endif - -/* Check if we should enable the USB monitor before starting NSH */ - -#ifndef CONFIG_USBMONITOR -# undef HAVE_USBMONITOR -#endif - -#ifndef HAVE_USBDEV -# undef CONFIG_USBDEV_TRACE -#endif - -#ifndef HAVE_USBHOST -# undef CONFIG_USBHOST_TRACE -#endif - -#if !defined(CONFIG_USBDEV_TRACE) && !defined(CONFIG_USBHOST_TRACE) -# undef HAVE_USBMONITOR -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_boardinitialize - * - * Description: - * All STM32 architectures must provide the following entry point. - * This entry point is called early in the initialization -- after all - * memory has been configured and mapped but before any devices have been - * initialized. - * - ****************************************************************************/ - -void stm32_boardinitialize(void) -{ - /* Initialize USB if the 1) OTG FS controller is in the configuration and - * 2) disabled, and 3) the weak function stm32_usbinitialize() has been - * brought into the build. - * Presumably either CONFIG_USBDEV or CONFIG_USBHOST is also selected. - */ - -#ifdef CONFIG_STM32_OTGFS - if (stm32_usbinitialize) - { - stm32_usbinitialize(); - } -#endif - - /* Configure on-board LEDs if LED support has been selected. */ - -#ifdef CONFIG_ARCH_LEDS - board_autoled_initialize(); -#endif - - /* Configure on-board BUTTONs if BUTTON support has been selected. */ - -#ifdef CONFIG_ARCH_BUTTONS - board_button_initialize(); -#endif -} - -/**************************************************************************** - * Name: board_late_initialize - * - * Description: - * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional - * initialization call will be performed in the boot-up sequence to a - * function called board_late_initialize(). board_late_initialize() will be - * called immediately after up_initialize() is called and just before the - * initial application is started. This additional initialization phase - * may be used, for example, to initialize board-specific device drivers. - * - ****************************************************************************/ - -#ifdef CONFIG_BOARD_LATE_INITIALIZE -void board_late_initialize(void) -{ - int ret; - -#ifdef CONFIG_STM32_CAN_CHARDRIVER - /* Initialize CAN and register the CAN driver. */ - - ret = stm32_can_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_can_setup failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_ADC - /* Initialize ADC and register the ADC driver. */ - - ret = stm32_adc_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_adc_setup failed: %d\n", ret); - } -#endif - -#ifdef HAVE_USBHOST - /* Initialize USB host operation. stm32_usbhost_initialize() starts a - * thread will monitor for USB connection and disconnection events. - */ - - ret = stm32_usbhost_initialize(); - if (ret != OK) - { - syslog(LOG_ERR, "ERROR: Failed to initialize USB host: %d\n", ret); - return; - } -#endif - -#ifdef HAVE_USBMONITOR - /* Start the USB Monitor */ - - ret = usbmonitor_start(); - if (ret != OK) - { - syslog(LOG_ERR, "ERROR: Failed to start USB monitor: %d\n", ret); - } -#endif - - UNUSED(ret); -} -#endif diff --git a/boards/arm/stm32/olimex-stm32-p207/src/stm32_buttons.c b/boards/arm/stm32/olimex-stm32-p207/src/stm32_buttons.c deleted file mode 100644 index fbf2d1236ba66..0000000000000 --- a/boards/arm/stm32/olimex-stm32-p207/src/stm32_buttons.c +++ /dev/null @@ -1,176 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/olimex-stm32-p207/src/stm32_buttons.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include -#include - -#include "olimex-stm32-p207.h" - -#ifdef CONFIG_ARCH_BUTTONS - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* Pin configuration for each STM32F4 Discovery button. This array is indexed - * by the BUTTON_* definitions in board.h - */ - -static const uint32_t g_buttons[NUM_BUTTONS] = -{ - GPIO_BTN_TAMPER, - GPIO_BTN_WKUP, - GPIO_BTN_RIGHT, - GPIO_BTN_UP, - GPIO_BTN_LEFT, - GPIO_BTN_DOWN, - GPIO_BTN_CENTER -}; - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_button_initialize - * - * Description: - * board_button_initialize() must be called to initialize button resources. - * After that, board_buttons() may be called to collect the current state - * of all buttons or board_button_irq() may be called to register button - * interrupt handlers. - * - ****************************************************************************/ - -uint32_t board_button_initialize(void) -{ - int i; - - /* Configure the GPIO pins as inputs. NOTE that EXTI interrupts are - * configured for all pins. - */ - - for (i = 0; i < NUM_BUTTONS; i++) - { - stm32_configgpio(g_buttons[i]); - } - - return NUM_BUTTONS; -} - -/**************************************************************************** - * Name: board_buttons - ****************************************************************************/ - -uint32_t board_buttons(void) -{ - uint32_t ret = 0; - - /* Check that state of each key */ - - if (!stm32_gpioread(g_buttons[BUTTON_TAMPER])) - { - ret |= BUTTON_TAMPER_BIT; - } - - if (stm32_gpioread(g_buttons[BUTTON_WKUP])) - { - ret |= BUTTON_WKUP_BIT; - } - - if (stm32_gpioread(g_buttons[BUTTON_RIGHT])) - { - ret |= BUTTON_RIGHT_BIT; - } - - if (stm32_gpioread(g_buttons[BUTTON_UP])) - { - ret |= BUTTON_UP_BIT; - } - - if (stm32_gpioread(g_buttons[BUTTON_LEFT])) - { - ret |= BUTTON_LEFT_BIT; - } - - if (stm32_gpioread(g_buttons[BUTTON_DOWN])) - { - ret |= BUTTON_DOWN_BIT; - } - - if (stm32_gpioread(g_buttons[BUTTON_CENTER])) - { - ret |= BUTTON_CENTER_BIT; - } - - return ret; -} - -/**************************************************************************** - * Button support. - * - * Description: - * board_button_initialize() must be called to initialize button resources. - * After that, board_buttons() may be called to collect the current state - * of all buttons or board_button_irq() may be called to register button - * interrupt handlers. - * - * After board_button_initialize() has been called, board_buttons() may be - * called to collect the state of all buttons. board_buttons() returns an - * 32-bit bit set with each bit associated with a button. See the - * BUTTON_*_BIT definitions in board.h for the meaning of each bit. - * - * board_button_irq() may be called to register an interrupt handler that - * will be called when a button is depressed or released. The ID value is a - * button enumeration value that uniquely identifies a button resource. See - * the BUTTON_* definitions in board.h for the meaning of enumeration - * value. - * - ****************************************************************************/ - -#ifdef CONFIG_ARCH_IRQBUTTONS -int board_button_irq(int id, xcpt_t irqhandler, void *arg) -{ - int ret = -EINVAL; - - /* The following should be atomic */ - - if (id >= MIN_IRQBUTTON && id <= MAX_IRQBUTTON) - { - ret = stm32_gpiosetevent(g_buttons[id], true, true, true, - irqhandler, arg); - } - - return ret; -} -#endif -#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/stm32/olimex-stm32-p207/src/stm32_can.c b/boards/arm/stm32/olimex-stm32-p207/src/stm32_can.c deleted file mode 100644 index b2bf59dacf7ef..0000000000000 --- a/boards/arm/stm32/olimex-stm32-p207/src/stm32_can.c +++ /dev/null @@ -1,100 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/olimex-stm32-p207/src/stm32_can.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include - -#include "stm32.h" -#include "stm32_can.h" -#include "olimex-stm32-p207.h" - -#ifdef CONFIG_CAN - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -#if defined(CONFIG_STM32_CAN1) && defined(CONFIG_STM32_CAN2) -# warning "Both CAN1 and CAN2 are enabled. Only CAN1 is connected." -# undef CONFIG_STM32_CAN2 -#endif - -#ifdef CONFIG_STM32_CAN1 -# define CAN_PORT 1 -#else -# define CAN_PORT 2 -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_can_setup - * - * Description: - * Initialize CAN and register the CAN device - * - ****************************************************************************/ - -int stm32_can_setup(void) -{ -#if defined(CONFIG_STM32_CAN1) || defined(CONFIG_STM32_CAN2) - struct can_dev_s *can; - int ret; - - /* Call stm32_caninitialize() to get an instance of the CAN interface */ - - can = stm32_caninitialize(CAN_PORT); - if (can == NULL) - { - canerr("ERROR: Failed to get CAN interface\n"); - return -ENODEV; - } - - /* Register the CAN driver at "/dev/can0" */ - - ret = can_register("/dev/can0", can); - if (ret < 0) - { - canerr("ERROR: can_register failed: %d\n", ret); - return ret; - } - - return OK; -#else - return -ENODEV; -#endif -} - -#endif /* CONFIG_CAN */ diff --git a/boards/arm/stm32/olimex-stm32-p207/src/stm32_usb.c b/boards/arm/stm32/olimex-stm32-p207/src/stm32_usb.c deleted file mode 100644 index 0217d0bdfd1c3..0000000000000 --- a/boards/arm/stm32/olimex-stm32-p207/src/stm32_usb.c +++ /dev/null @@ -1,313 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/olimex-stm32-p207/src/stm32_usb.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -#include "stm32.h" -#include "stm32_otgfs.h" -#include "olimex-stm32-p207.h" - -#ifdef CONFIG_STM32_OTGFS - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#if defined(CONFIG_USBDEV) || defined(CONFIG_USBHOST) -# define HAVE_USB 1 -#else -# warning "CONFIG_STM32_OTGFS is enabled but neither CONFIG_USBDEV nor CONFIG_USBHOST" -# undef HAVE_USB -#endif - -#ifndef CONFIG_USBHOST_DEFPRIO -# define CONFIG_USBHOST_DEFPRIO 50 -#endif - -#ifndef CONFIG_USBHOST_STACKSIZE -# ifdef CONFIG_USBHOST_HUB -# define CONFIG_USBHOST_STACKSIZE 1536 -# else -# define CONFIG_USBHOST_STACKSIZE 1024 -# endif -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -#ifdef CONFIG_STM32_USBHOST -static struct usbhost_connection_s *g_usbconn; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: usbhost_waiter - * - * Description: - * Wait for USB devices to be connected. - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_USBHOST -static int usbhost_waiter(int argc, char *argv[]) -{ - struct usbhost_hubport_s *hport; - - uinfo("Running\n"); - for (; ; ) - { - /* Wait for the device to change state */ - - DEBUGVERIFY(CONN_WAIT(g_usbconn, &hport)); - uinfo("%s\n", hport->connected ? "connected" : "disconnected"); - - /* Did we just become connected? */ - - if (hport->connected) - { - /* Yes.. enumerate the newly connected device */ - - CONN_ENUMERATE(g_usbconn, hport); - } - } - - /* Keep the compiler from complaining */ - - return 0; -} -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_usbinitialize - * - * Description: - * Called from stm32_usbinitialize very early in initialization to setup - * USB-related GPIO pins for the STM32F4Discovery board. - * - ****************************************************************************/ - -void stm32_usbinitialize(void) -{ - /* The OTG FS has an internal soft pull-up. - * No GPIO configuration is required - */ - - /* Configure the OTG FS VBUS sensing GPIO, - * Power On, and Overcurrent GPIOs - */ - -#ifdef CONFIG_STM32_OTGFS - stm32_configgpio(GPIO_OTGFS_VBUS); - stm32_configgpio(GPIO_OTGFS_PWRON); - stm32_configgpio(GPIO_OTGFS_OVER); -#endif -} - -/**************************************************************************** - * Name: stm32_usbhost_initialize - * - * Description: - * Called at application startup time to initialize the USB host - * functionality. - * This function will start a thread that will monitor for device - * connection/disconnection events. - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_USBHOST -int stm32_usbhost_initialize(void) -{ - int ret; - - /* First, register all of the class drivers needed to support the drivers - * that we care about: - */ - - uinfo("Register class drivers\n"); - -#ifdef CONFIG_USBHOST_HUB - /* Initialize USB hub class support */ - - ret = usbhost_hub_initialize(); - if (ret < 0) - { - uerr("ERROR: usbhost_hub_initialize failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_USBHOST_MSC - /* Register the USB host Mass Storage Class */ - - ret = usbhost_msc_initialize(); - if (ret != OK) - { - uerr("ERROR: Failed to register the mass storage class: %d\n", ret); - } -#endif - -#ifdef CONFIG_USBHOST_CDCACM - /* Register the CDC/ACM serial class */ - - ret = usbhost_cdcacm_initialize(); - if (ret != OK) - { - uerr("ERROR: Failed to register the CDC/ACM serial class: %d\n", ret); - } -#endif - - /* Then get an instance of the USB host interface */ - - uinfo("Initialize USB host\n"); - g_usbconn = stm32_otgfshost_initialize(0); - if (g_usbconn) - { - /* Start a thread to handle device connection. */ - - uinfo("Start usbhost_waiter\n"); - - ret = kthread_create("usbhost", CONFIG_USBHOST_DEFPRIO, - CONFIG_USBHOST_STACKSIZE, - usbhost_waiter, NULL); - return ret < 0 ? -ENOEXEC : OK; - } - - return -ENODEV; -} -#endif - -/**************************************************************************** - * Name: stm32_setup_overcurrent - * - * Description: - * Setup to receive an interrupt-level callback if an overcurrent - * condition is detected. - * - * Input Parameters: - * handler - New overcurrent interrupt handler - * arg - The argument provided for the interrupt handler - * - * Returned Value: - * Zero (OK) is returned on success. Otherwise, a negated errno value - * is returned to indicate the nature of the failure. - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_USBHOST -int stm32_setup_overcurrent(xcpt_t handler, void *arg) -{ - return stm32_gpiosetevent(GPIO_OTGFS_OVER, true, true, true, handler, arg); -} -#endif - -/**************************************************************************** - * Name: stm32_usbhost_vbusdrive - * - * Description: - * Enable/disable driving of VBUS 5V output. This function must be - * provided be each platform that implements the STM32 OTG FS host - * interface - * - * "On-chip 5 V VBUS generation is not supported. For this reason, a - * charge pump or, if 5 V are available on the application board, a - * basic power switch, must be added externally to drive the 5 V VBUS - * line. The external charge pump can be driven by any GPIO output. - * When the application decides to power on VBUS using the chosen GPIO, - * it must also set the port power bit in the host port control and - * status register (PPWR bit in OTG_FS_HPRT). - * - * "The application uses this field to control power to this port, - * and the core clears this bit on an overcurrent condition." - * - * Input Parameters: - * iface - For future growth to handle multiple USB host interface. - * Should be zero. - * enable - true: enable VBUS power; false: disable VBUS power - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_USBHOST -void stm32_usbhost_vbusdrive(int iface, bool enable) -{ - DEBUGASSERT(iface == 0); - - if (enable) - { - /* Enable the Power Switch by driving the enable pin low */ - - stm32_gpiowrite(GPIO_OTGFS_PWRON, false); - } - else - { - /* Disable the Power Switch by driving the enable pin high */ - - stm32_gpiowrite(GPIO_OTGFS_PWRON, true); - } -} -#endif - -/**************************************************************************** - * Name: stm32_usbsuspend - * - * Description: - * Board logic must provide the stm32_usbsuspend logic if the USBDEV - * driver is used. This function is called whenever the USB enters or - * leaves suspend mode. This is an opportunity for the board logic to - * shutdown clocks, power, etc. while the USB is suspended. - * - ****************************************************************************/ - -#ifdef CONFIG_USBDEV -void stm32_usbsuspend(struct usbdev_s *dev, bool resume) -{ - uinfo("resume: %d\n", resume); -} -#endif - -#endif /* CONFIG_STM32_OTGFS */ diff --git a/boards/arm/stm32/olimex-stm32-p207/src/stm32_userleds.c b/boards/arm/stm32/olimex-stm32-p207/src/stm32_userleds.c deleted file mode 100644 index 044ff84794de1..0000000000000 --- a/boards/arm/stm32/olimex-stm32-p207/src/stm32_userleds.c +++ /dev/null @@ -1,104 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/olimex-stm32-p207/src/stm32_userleds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include "stm32.h" -#include "olimex-stm32-p207.h" - -#ifndef CONFIG_ARCH_LEDS - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* This array maps an LED number to GPIO pin configuration */ - -static uint32_t g_ledcfg[BOARD_NLEDS] = -{ - GPIO_LED1, GPIO_LED2, GPIO_LED3, GPIO_LED4 -}; - -/**************************************************************************** - * Private Function Protototypes - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_userled_initialize - ****************************************************************************/ - -uint32_t board_userled_initialize(void) -{ - /* Configure LED1-4 GPIOs for output */ - - stm32_configgpio(GPIO_LED1); - stm32_configgpio(GPIO_LED2); - stm32_configgpio(GPIO_LED3); - stm32_configgpio(GPIO_LED4); - return BOARD_NLEDS; -} - -/**************************************************************************** - * Name: board_userled - ****************************************************************************/ - -void board_userled(int led, bool ledon) -{ - if ((unsigned)led < BOARD_NLEDS) - { - stm32_gpiowrite(g_ledcfg[led], ledon); - } -} - -/**************************************************************************** - * Name: board_userled_all - ****************************************************************************/ - -void board_userled_all(uint32_t ledset) -{ - stm32_gpiowrite(GPIO_LED1, (ledset & BOARD_LED1_BIT) != 0); - stm32_gpiowrite(GPIO_LED2, (ledset & BOARD_LED2_BIT) != 0); - stm32_gpiowrite(GPIO_LED3, (ledset & BOARD_LED3_BIT) != 0); - stm32_gpiowrite(GPIO_LED4, (ledset & BOARD_LED4_BIT) != 0); -} - -#endif /* !CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/olimex-stm32-p407/CMakeLists.txt b/boards/arm/stm32/olimex-stm32-p407/CMakeLists.txt deleted file mode 100644 index 9932d6545d588..0000000000000 --- a/boards/arm/stm32/olimex-stm32-p407/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/olimex-stm32-p407/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32/olimex-stm32-p407/configs/audio/defconfig b/boards/arm/stm32/olimex-stm32-p407/configs/audio/defconfig deleted file mode 100644 index 1d4015c480202..0000000000000 --- a/boards/arm/stm32/olimex-stm32-p407/configs/audio/defconfig +++ /dev/null @@ -1,67 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="olimex-stm32-p407" -CONFIG_ARCH_BOARD_OLIMEX_STM32P407=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F407ZG=y -CONFIG_ARCH_IRQBUTTONS=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_AUDIO=y -CONFIG_AUDIO_CS4344=y -CONFIG_AUDIO_EXCLUDE_TONE=y -CONFIG_AUDIO_EXCLUDE_VOLUME=y -CONFIG_AUDIO_I2S=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_DRIVERS_AUDIO=y -CONFIG_FAT_LCNAMES=y -CONFIG_FAT_LFN=y -CONFIG_FS_FAT=y -CONFIG_FS_PROCFS=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_DISABLE_GET=y -CONFIG_NSH_DISABLE_IFUPDOWN=y -CONFIG_NSH_DISABLE_PUT=y -CONFIG_NSH_DISABLE_WGET=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_NXPLAYER_DEFAULT_MEDIADIR="/mnt/music" -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=131072 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_HPWORKPRIORITY=192 -CONFIG_SCHED_WAITPID=y -CONFIG_START_YEAR=2013 -CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32_DMA1=y -CONFIG_STM32_I2S3=y -CONFIG_STM32_I2S3_TX=y -CONFIG_STM32_I2S_MCK=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_OTGFS=y -CONFIG_STM32_PWR=y -CONFIG_STM32_SPI3=y -CONFIG_STM32_SPI3_DMA=y -CONFIG_STM32_USART3=y -CONFIG_STM32_USBHOST=y -CONFIG_SYSTEM_NSH=y -CONFIG_SYSTEM_NXPLAYER=y -CONFIG_TASK_NAME_SIZE=32 -CONFIG_USART3_SERIAL_CONSOLE=y -CONFIG_USBHOST_MSC=y diff --git a/boards/arm/stm32/olimex-stm32-p407/configs/dhtxx/defconfig b/boards/arm/stm32/olimex-stm32-p407/configs/dhtxx/defconfig deleted file mode 100644 index 1ec9ec6df1f4e..0000000000000 --- a/boards/arm/stm32/olimex-stm32-p407/configs/dhtxx/defconfig +++ /dev/null @@ -1,61 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="olimex-stm32-p407" -CONFIG_ARCH_BOARD_COMMON=y -CONFIG_ARCH_BOARD_OLIMEX_STM32P407=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F407ZG=y -CONFIG_ARCH_IRQBUTTONS=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARDCTL_USBDEVCTRL=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_CDCACM=y -CONFIG_CDCACM_CONSOLE=y -CONFIG_EXAMPLES_DHTXX=y -CONFIG_FAT_LCNAMES=y -CONFIG_FAT_LFN=y -CONFIG_FS_FAT=y -CONFIG_FS_PROCFS=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_DISABLE_GET=y -CONFIG_NSH_DISABLE_IFUPDOWN=y -CONFIG_NSH_DISABLE_PUT=y -CONFIG_NSH_DISABLE_WGET=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=131072 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_HPWORKPRIORITY=192 -CONFIG_SCHED_WAITPID=y -CONFIG_SENSORS=y -CONFIG_SENSORS_DHTXX=y -CONFIG_START_YEAR=2013 -CONFIG_STM32_CCMEXCLUDE=y -CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32_FREERUN=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_OTGFS=y -CONFIG_STM32_PWR=y -CONFIG_STM32_TIM1=y -CONFIG_STM32_USART3=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=32 -CONFIG_USBDEV=y diff --git a/boards/arm/stm32/olimex-stm32-p407/configs/hidkbd/defconfig b/boards/arm/stm32/olimex-stm32-p407/configs/hidkbd/defconfig deleted file mode 100644 index ed45a26523b3c..0000000000000 --- a/boards/arm/stm32/olimex-stm32-p407/configs/hidkbd/defconfig +++ /dev/null @@ -1,55 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="olimex-stm32-p407" -CONFIG_ARCH_BOARD_OLIMEX_STM32P407=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F407ZG=y -CONFIG_ARCH_IRQBUTTONS=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_EXAMPLES_HIDKBD=y -CONFIG_FAT_LCNAMES=y -CONFIG_FAT_LFN=y -CONFIG_FS_FAT=y -CONFIG_FS_PROCFS=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_DISABLE_GET=y -CONFIG_NSH_DISABLE_IFUPDOWN=y -CONFIG_NSH_DISABLE_PUT=y -CONFIG_NSH_DISABLE_WGET=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=131072 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_HPWORKPRIORITY=192 -CONFIG_SCHED_WAITPID=y -CONFIG_START_YEAR=2013 -CONFIG_STM32_CCMEXCLUDE=y -CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_OTGFS=y -CONFIG_STM32_PWR=y -CONFIG_STM32_USART3=y -CONFIG_STM32_USBHOST=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=32 -CONFIG_USART3_SERIAL_CONSOLE=y -CONFIG_USBHOST_HIDKBD=y diff --git a/boards/arm/stm32/olimex-stm32-p407/configs/kelf/Make.defs b/boards/arm/stm32/olimex-stm32-p407/configs/kelf/Make.defs deleted file mode 100644 index b8256a1439968..0000000000000 --- a/boards/arm/stm32/olimex-stm32-p407/configs/kelf/Make.defs +++ /dev/null @@ -1,41 +0,0 @@ -############################################################################ -# boards/arm/stm32/olimex-stm32-p407/configs/kelf/Make.defs -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/.config -include $(TOPDIR)/tools/Config.mk -include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs - -ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)memory.ld -ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)kernel-space.ld - -ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 - -CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) -CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) -CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -AFLAGS := $(CFLAGS) -D__ASSEMBLY__ - -# NXFLAT module definitions - -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)$(DELIM)binfmt$(DELIM)libnxflat$(DELIM)gnu-nxflat-pcrel.ld -no-check-sections -LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32/olimex-stm32-p407/configs/kelf/defconfig b/boards/arm/stm32/olimex-stm32-p407/configs/kelf/defconfig deleted file mode 100644 index bb4a056ff466a..0000000000000 --- a/boards/arm/stm32/olimex-stm32-p407/configs/kelf/defconfig +++ /dev/null @@ -1,58 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="olimex-stm32-p407" -CONFIG_ARCH_BOARD_OLIMEX_STM32P407=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F407ZG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_ARM_MPU=y -CONFIG_BINFMT_CONSTRUCTORS=y -CONFIG_BOARDCTL=y -CONFIG_BOARDCTL_ROMDISK=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILD_PROTECTED=y -CONFIG_CONSOLE_SYSLOG=y -CONFIG_ELF=y -CONFIG_ELF_STACKSIZE=4096 -CONFIG_EXAMPLES_ELF=y -CONFIG_EXAMPLES_ELF_DEVPATH="/dev/sda" -CONFIG_EXAMPLES_ELF_FSREMOVEABLE=y -CONFIG_FAT_LCNAMES=y -CONFIG_FAT_LFN=y -CONFIG_FS_FAT=y -CONFIG_HAVE_CXX=y -CONFIG_INIT_ENTRYPOINT="elf_main" -CONFIG_INIT_STACKSIZE=4096 -CONFIG_INTELHEX_BINARY=y -CONFIG_LIBC_ENVPATH=y -CONFIG_MM_KERNEL_HEAPSIZE=16384 -CONFIG_MM_REGIONS=2 -CONFIG_NUTTX_USERSPACE=0x08020000 -CONFIG_PASS1_BUILDIR="boards/arm/stm32/olimex-stm32-p407/kernel" -CONFIG_PATH_INITIAL="/mnt/vfat" -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=4 -CONFIG_START_MONTH=8 -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_OTGFS=y -CONFIG_STM32_RNG=y -CONFIG_STM32_SDIO=y -CONFIG_STM32_USART3=y -CONFIG_STM32_USBHOST=y -CONFIG_SYMTAB_ORDEREDBYNAME=y -CONFIG_USART3_SERIAL_CONSOLE=y -CONFIG_USBHOST_ISOC_DISABLE=y -CONFIG_USBHOST_MSC=y diff --git a/boards/arm/stm32/olimex-stm32-p407/configs/kmodule/Make.defs b/boards/arm/stm32/olimex-stm32-p407/configs/kmodule/Make.defs deleted file mode 100644 index 03291ccbb7842..0000000000000 --- a/boards/arm/stm32/olimex-stm32-p407/configs/kmodule/Make.defs +++ /dev/null @@ -1,41 +0,0 @@ -############################################################################ -# boards/arm/stm32/olimex-stm32-p407/configs/kmodule/Make.defs -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/.config -include $(TOPDIR)/tools/Config.mk -include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs - -ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)memory.ld -ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)kernel-space.ld - -ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 - -CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) -CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) -CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -AFLAGS := $(CFLAGS) -D__ASSEMBLY__ - -# NXFLAT module definitions - -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)$(DELIM)binfmt$(DELIM)libnxflat$(DELIM)gnu-nxflat-pcrel.ld -no-check-sections -LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32/olimex-stm32-p407/configs/kmodule/defconfig b/boards/arm/stm32/olimex-stm32-p407/configs/kmodule/defconfig deleted file mode 100644 index cde47ac79db37..0000000000000 --- a/boards/arm/stm32/olimex-stm32-p407/configs/kmodule/defconfig +++ /dev/null @@ -1,54 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="olimex-stm32-p407" -CONFIG_ARCH_BOARD_OLIMEX_STM32P407=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F407ZG=y -CONFIG_ARCH_INTERRUPTSTACK=2048 -CONFIG_ARCH_IRQBUTTONS=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_ARM_MPU=y -CONFIG_BOARDCTL=y -CONFIG_BOARDCTL_ROMDISK=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILD_PROTECTED=y -CONFIG_EXAMPLES_MODULE=y -CONFIG_EXAMPLES_MODULE_DEVPATH="/dev/sda" -CONFIG_EXAMPLES_MODULE_FSREMOVEABLE=y -CONFIG_FAT_LCNAMES=y -CONFIG_FAT_LFN=y -CONFIG_FS_FAT=y -CONFIG_FS_PROCFS=y -CONFIG_INIT_ENTRYPOINT="module_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_MM_KERNEL_HEAPSIZE=16384 -CONFIG_MM_REGIONS=2 -CONFIG_MODULE=y -CONFIG_NUTTX_USERSPACE=0x08020000 -CONFIG_PASS1_BUILDIR="boards/arm/stm32/olimex-stm32-p407/kernel" -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=5 -CONFIG_START_MONTH=8 -CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_OTGFS=y -CONFIG_STM32_PWR=y -CONFIG_STM32_USART3=y -CONFIG_STM32_USBHOST=y -CONFIG_SYMTAB_ORDEREDBYNAME=y -CONFIG_USART3_SERIAL_CONSOLE=y -CONFIG_USBHOST_ISOC_DISABLE=y -CONFIG_USBHOST_MSC=y diff --git a/boards/arm/stm32/olimex-stm32-p407/configs/knsh/Make.defs b/boards/arm/stm32/olimex-stm32-p407/configs/knsh/Make.defs deleted file mode 100644 index e933d297972bd..0000000000000 --- a/boards/arm/stm32/olimex-stm32-p407/configs/knsh/Make.defs +++ /dev/null @@ -1,42 +0,0 @@ -############################################################################ -# boards/arm/stm32/olimex-stm32-p407/configs/knsh/Make.defs -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/.config -include $(TOPDIR)/tools/Config.mk -include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs - -LDSCRIPT1 = memory.ld -LDSCRIPT2 = kernel-space.ld - -ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT1) -ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT2) - -ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 - -CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) -CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) -CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -AFLAGS := $(CFLAGS) -D__ASSEMBLY__ - -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-gotoff.ld -no-check-sections -LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32/olimex-stm32-p407/configs/knsh/defconfig b/boards/arm/stm32/olimex-stm32-p407/configs/knsh/defconfig deleted file mode 100644 index 7be5a978eda06..0000000000000 --- a/boards/arm/stm32/olimex-stm32-p407/configs/knsh/defconfig +++ /dev/null @@ -1,54 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_SYSTEM_DD is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="olimex-stm32-p407" -CONFIG_ARCH_BOARD_OLIMEX_STM32P407=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F407ZG=y -CONFIG_ARCH_IRQBUTTONS=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_ARM_MPU=y -CONFIG_BOARDCTL=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILD_PROTECTED=y -CONFIG_FS_PROCFS=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_MM_KERNEL_HEAPSIZE=16384 -CONFIG_NSH_DISABLE_GET=y -CONFIG_NSH_DISABLE_IFUPDOWN=y -CONFIG_NSH_DISABLE_MKRD=y -CONFIG_NSH_DISABLE_PUT=y -CONFIG_NSH_DISABLE_WGET=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_NUTTX_USERSPACE=0x08020000 -CONFIG_PASS1_BUILDIR="boards/arm/stm32/olimex-stm32-p407/kernel" -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=131072 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_HPWORKPRIORITY=192 -CONFIG_SCHED_WAITPID=y -CONFIG_START_YEAR=2013 -CONFIG_STM32_CCMEXCLUDE=y -CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_PWR=y -CONFIG_STM32_USART3=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=32 -CONFIG_USART3_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/olimex-stm32-p407/configs/module/defconfig b/boards/arm/stm32/olimex-stm32-p407/configs/module/defconfig deleted file mode 100644 index 7157051491cb3..0000000000000 --- a/boards/arm/stm32/olimex-stm32-p407/configs/module/defconfig +++ /dev/null @@ -1,48 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="olimex-stm32-p407" -CONFIG_ARCH_BOARD_OLIMEX_STM32P407=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F407ZG=y -CONFIG_ARCH_INTERRUPTSTACK=2048 -CONFIG_ARCH_IRQBUTTONS=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARDCTL_ROMDISK=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_EXAMPLES_MODULE=y -CONFIG_FAT_LCNAMES=y -CONFIG_FAT_LFN=y -CONFIG_FS_FAT=y -CONFIG_FS_PROCFS=y -CONFIG_FS_ROMFS=y -CONFIG_HOST_WINDOWS=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_LINE_MAX=64 -CONFIG_MODULE=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_DISABLE_IFUPDOWN=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=393216 -CONFIG_RAM_START=0x20400000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_WAITPID=y -CONFIG_START_MONTH=6 -CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_PWR=y -CONFIG_STM32_USART3=y -CONFIG_SYSTEM_NSH=y -CONFIG_USART3_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/olimex-stm32-p407/configs/mqttc/defconfig b/boards/arm/stm32/olimex-stm32-p407/configs/mqttc/defconfig deleted file mode 100644 index 76e96ce5920c8..0000000000000 --- a/boards/arm/stm32/olimex-stm32-p407/configs/mqttc/defconfig +++ /dev/null @@ -1,82 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_STM32_AUTONEG is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="olimex-stm32-p407" -CONFIG_ARCH_BOARD_OLIMEX_STM32P407=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F407ZG=y -CONFIG_ARCH_IRQBUTTONS=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_ETH0_PHY_KS8721=y -CONFIG_EXAMPLES_MQTTC=y -CONFIG_FAT_LCNAMES=y -CONFIG_FAT_LFN=y -CONFIG_FS_FAT=y -CONFIG_FS_PROCFS=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_HTS221_DEBUG=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LIBM=y -CONFIG_LINE_MAX=64 -CONFIG_NET=y -CONFIG_NETDB_DNSCLIENT=y -CONFIG_NETDB_DNSSERVER_IPv4ADDR=0xc0a80101 -CONFIG_NETINIT_DRIPADDR=0xc0a80101 -CONFIG_NETINIT_IPADDR=0xc0a801e1 -CONFIG_NETINIT_NOMAC=y -CONFIG_NETUTILS_MQTTC=y -CONFIG_NETUTILS_TELNETD=y -CONFIG_NET_ICMP_SOCKET=y -CONFIG_NET_STATISTICS=y -CONFIG_NET_TCP=y -CONFIG_NET_TCP_NOTIFIER=y -CONFIG_NET_TCP_WRITE_BUFFERS=y -CONFIG_NET_UDP=y -CONFIG_NET_UDP_WRITE_BUFFERS=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_DISABLE_GET=y -CONFIG_NSH_DISABLE_IFUPDOWN=y -CONFIG_NSH_DISABLE_PUT=y -CONFIG_NSH_DISABLE_WGET=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=131072 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_READLINE_CMD_HISTORY=y -CONFIG_READLINE_TABCOMPLETION=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_HPWORKPRIORITY=192 -CONFIG_SCHED_WAITPID=y -CONFIG_SENSORS=y -CONFIG_SENSORS_HTS221=y -CONFIG_START_YEAR=2013 -CONFIG_STM32_CCMEXCLUDE=y -CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32_ETH100MBPS=y -CONFIG_STM32_ETHFD=y -CONFIG_STM32_ETHMAC=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_PWR=y -CONFIG_STM32_RMII_EXTCLK=y -CONFIG_STM32_USART6=y -CONFIG_SYSTEM_NETDB=y -CONFIG_SYSTEM_NSH=y -CONFIG_SYSTEM_PING=y -CONFIG_SYSTEM_TELNET_CLIENT=y -CONFIG_TASK_NAME_SIZE=32 -CONFIG_USART6_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/olimex-stm32-p407/configs/nsh/defconfig b/boards/arm/stm32/olimex-stm32-p407/configs/nsh/defconfig deleted file mode 100644 index bb3cbd8e78037..0000000000000 --- a/boards/arm/stm32/olimex-stm32-p407/configs/nsh/defconfig +++ /dev/null @@ -1,54 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="olimex-stm32-p407" -CONFIG_ARCH_BOARD_OLIMEX_STM32P407=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F407ZG=y -CONFIG_ARCH_IRQBUTTONS=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_FAT_LCNAMES=y -CONFIG_FAT_LFN=y -CONFIG_FS_FAT=y -CONFIG_FS_PROCFS=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_DISABLE_GET=y -CONFIG_NSH_DISABLE_IFUPDOWN=y -CONFIG_NSH_DISABLE_PUT=y -CONFIG_NSH_DISABLE_WGET=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=131072 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_HPWORKPRIORITY=192 -CONFIG_SCHED_WAITPID=y -CONFIG_START_YEAR=2013 -CONFIG_STM32_CCMEXCLUDE=y -CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_OTGFS=y -CONFIG_STM32_PWR=y -CONFIG_STM32_USART3=y -CONFIG_STM32_USBHOST=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=32 -CONFIG_USART3_SERIAL_CONSOLE=y -CONFIG_USBHOST_MSC=y diff --git a/boards/arm/stm32/olimex-stm32-p407/configs/zmodem/defconfig b/boards/arm/stm32/olimex-stm32-p407/configs/zmodem/defconfig deleted file mode 100644 index 7c2ccb8cb1f0d..0000000000000 --- a/boards/arm/stm32/olimex-stm32-p407/configs/zmodem/defconfig +++ /dev/null @@ -1,72 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="olimex-stm32-p407" -CONFIG_ARCH_BOARD_OLIMEX_STM32P407=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F407ZG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_FAT_LCNAMES=y -CONFIG_FAT_LFN=y -CONFIG_FS_FAT=y -CONFIG_FS_PROCFS=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_I2C=y -CONFIG_I2C_POLLED=y -CONFIG_I2C_RESET=y -CONFIG_I2S=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_MM_REGIONS=2 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_WAITPID=y -CONFIG_SERIAL_IFLOWCONTROL_LOWER_WATERMARK=25 -CONFIG_SERIAL_IFLOWCONTROL_UPPER_WATERMARK=75 -CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS=y -CONFIG_SERIAL_TERMIOS=y -CONFIG_SPI=y -CONFIG_START_DAY=26 -CONFIG_START_MONTH=5 -CONFIG_STM32_CCMEXCLUDE=y -CONFIG_STM32_FLOWCONTROL_BROKEN=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_OTGFS=y -CONFIG_STM32_PWR=y -CONFIG_STM32_USART3=y -CONFIG_STM32_USART6=y -CONFIG_STM32_USBHOST=y -CONFIG_SYSTEM_NSH=y -CONFIG_SYSTEM_ZMODEM=y -CONFIG_SYSTEM_ZMODEM_DEVNAME="/dev/ttyS1" -CONFIG_SYSTEM_ZMODEM_IFLOW=y -CONFIG_SYSTEM_ZMODEM_MOUNTPOINT="/mnt" -CONFIG_SYSTEM_ZMODEM_OFLOW=y -CONFIG_SYSTEM_ZMODEM_PKTBUFSIZE=1024 -CONFIG_USART3_BAUD=9600 -CONFIG_USART3_IFLOWCONTROL=y -CONFIG_USART3_OFLOWCONTROL=y -CONFIG_USART3_RXBUFSIZE=512 -CONFIG_USART6_SERIAL_CONSOLE=y -CONFIG_USBHOST_ISOC_DISABLE=y -CONFIG_USBHOST_MSC=y diff --git a/boards/arm/stm32/olimex-stm32-p407/include/board.h b/boards/arm/stm32/olimex-stm32-p407/include/board.h deleted file mode 100644 index 92a26895aadca..0000000000000 --- a/boards/arm/stm32/olimex-stm32-p407/include/board.h +++ /dev/null @@ -1,453 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/olimex-stm32-p407/include/board.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __BOARDS_ARM_STM32_OLIMEX_STM32_P407_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32_OLIMEX_STM32_P407_INCLUDE_BOARD_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#ifndef __ASSEMBLY__ -# include -#endif - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Clocking *****************************************************************/ - -/* HSI - 16 MHz RC factory-trimmed - * LSI - 32 KHz RC (30-60KHz, uncalibrated) - * HSE - On-board crystal frequency is 25MHz - * LSE - 32.768 kHz - */ - -#define STM32_BOARD_XTAL 25000000ul - -#define STM32_HSI_FREQUENCY 16000000ul -#define STM32_LSI_FREQUENCY 32000 -#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL -#define STM32_LSE_FREQUENCY 32768 - -/* Main PLL Configuration. - * - * PLL source is HSE - * PLL_VCO = (STM32_HSE_FREQUENCY / PLLM) * PLLN - * = (25,000,000 / 25) * 336 - * = 336,000,000 - * SYSCLK = PLL_VCO / PLLP - * = 336,000,000 / 2 = 168,000,000 - * USB OTG FS, SDIO and RNG Clock - * = PLL_VCO / PLLQ - * = 48,000,000 - */ - -#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(25) -#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(336) -#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_2 -#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(7) - -#define STM32_SYSCLK_FREQUENCY 168000000ul - -/* AHB clock (HCLK) is SYSCLK (168MHz) */ - -#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ -#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY - -/* APB1 clock (PCLK1) is HCLK/4 (42MHz) */ - -#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd4 /* PCLK1 = HCLK / 4 */ -#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/4) - -/* Timers driven from APB1 will be twice PCLK1 */ - -#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) - -/* APB2 clock (PCLK2) is HCLK/2 (84MHz) */ - -#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLKd2 /* PCLK2 = HCLK / 2 */ -#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/2) - -/* Timers driven from APB2 will be twice PCLK2 */ - -#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM9_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM10_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM11_CLKIN (2*STM32_PCLK2_FREQUENCY) - -/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx - * otherwise frequency is 2xAPBx. - * Note: TIM1,8 are on APB2, others on APB1 - */ - -#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM2_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM3_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM4_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM5_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM6_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM7_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY - -/* SDIO dividers. Note that slower clocking is required when DMA is disabled - * in order to avoid RX overrun/TX underrun errors due to delayed responses - * to service FIFOs in interrupt driven mode. These values have not been - * tuned!!! - * - * SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(118+2)=400 KHz - */ - -#define SDIO_INIT_CLKDIV (118 << SDIO_CLKCR_CLKDIV_SHIFT) - -/* DMA ON: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(1+2)=16 MHz - * DMA OFF: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(2+2)=12 MHz - */ - -#ifdef CONFIG_SDIO_DMA -# define SDIO_MMCXFR_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT) -#else -# define SDIO_MMCXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT) -#endif - -/* DMA ON: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(1+2)=16 MHz - * DMA OFF: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(2+2)=12 MHz - */ - -#ifdef CONFIG_SDIO_DMA -# define SDIO_SDXFR_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT) -#else -# define SDIO_SDXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT) -#endif - -/* LED definitions **********************************************************/ - -/* If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs - * in any way. The following definitions are used to access individual LEDs. - */ - -/* LED index values for use with board_userled() */ - -#define BOARD_LED1 0 -#define BOARD_LED2 1 -#define BOARD_LED3 2 -#define BOARD_LED4 3 -#define BOARD_NLEDS 4 - -#define BOARD_LED_GREEN1 BOARD_LED1 -#define BOARD_LED_YELLOW BOARD_LED2 -#define BOARD_LED_RED BOARD_LED3 -#define BOARD_LED_GREEN2 BOARD_LED4 - -/* LED bits for use with board_userled_all() */ - -#define BOARD_LED1_BIT (1 << BOARD_LED1) -#define BOARD_LED2_BIT (1 << BOARD_LED2) -#define BOARD_LED3_BIT (1 << BOARD_LED3) -#define BOARD_LED4_BIT (1 << BOARD_LED4) - -/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the 4 LEDs on - * board the Olimex STM32-P407. The following definitions describe how - * NuttX controls the LEDs: - */ - -#define LED_STARTED 0 /* LED1 */ -#define LED_HEAPALLOCATE 1 /* LED2 */ -#define LED_IRQSENABLED 2 /* LED1 + LED2 */ -#define LED_STACKCREATED 3 /* LED3 */ -#define LED_INIRQ 4 /* LED1 + LED3 */ -#define LED_SIGNAL 5 /* LED2 + LED3 */ -#define LED_ASSERTION 6 /* LED1 + LED2 + LED3 */ -#define LED_PANIC 7 /* N/C + N/C + N/C + LED4 */ - -/* Button definitions *******************************************************/ - -/* The Olimex STM32-P407 supports seven buttons: */ - -#define BUTTON_TAMPER 0 -#define BUTTON_WKUP 1 - -#ifdef CONFIG_INPUT_DJOYSTICK -# define NUM_BUTTONS 2 -#else -# define JOYSTICK_RIGHT 2 -# define JOYSTICK_UP 3 -# define JOYSTICK_LEFT 4 -# define JOYSTICK_DOWN 5 -# define JOYSTICK_CENTER 6 - -# define NUM_BUTTONS 7 -#endif - -#define BUTTON_TAMPER_BIT (1 << BUTTON_TAMPER) -#define BUTTON_WKUP_BIT (1 << BUTTON_WKUP) - -#ifndef CONFIG_INPUT_DJOYSTICK -# define JOYSTICK_RIGHT_BIT (1 << JOYSTICK_RIGHT) -# define JOYSTICK_UP_BIT (1 << JOYSTICK_UP) -# define JOYSTICK_LEFT_BIT (1 << JOYSTICK_LEFT) -# define JOYSTICK_DOWN_BIT (1 << JOYSTICK_DOWN) -# define JOYSTICK_CENTER_BIT (1 << JOYSTICK_CENTER) -#endif - -/* Alternate function pin selections ****************************************/ - -/* USART3: */ - -#define GPIO_USART3_RX (GPIO_USART3_RX_3|GPIO_SPEED_100MHz) /* PD9 */ -#define GPIO_USART3_TX (GPIO_USART3_TX_3|GPIO_SPEED_100MHz) /* PD8 */ -#define GPIO_USART3_CTS GPIO_USART3_CTS_2 /* PD11 */ -#define GPIO_USART3_RTS GPIO_USART3_RTS_2 /* PD12 */ - -/* UEXT USART3: This will redefine the above macros if enabled. */ - -#ifdef CONFIG_STM32_OLIMEXP407_UEXT_USART3 -# undef GPIO_USART3_RX (GPIO_USART3_RX_3|GPIO_SPEED_100MHz) -# undef GPIO_USART3_TX (GPIO_USART3_TX_3|GPIO_SPEED_100MHz) -# undef GPIO_USART3_CTS GPIO_USART3_CTS_2 -# undef GPIO_USART3_RTS GPIO_USART3_RTS_2 - -# define GPIO_USART3_RX (GPIO_USART3_RX_2|GPIO_SPEED_100MHz) /* PC11 */ -# define GPIO_USART3_TX (GPIO_USART3_TX_2|GPIO_SPEED_100MHz) /* PC10 */ -#endif - -/* USART6: */ - -#define GPIO_USART6_RX (GPIO_USART6_RX_2|GPIO_SPEED_100MHz) /* PG9 */ -#define GPIO_USART6_TX (GPIO_USART6_TX_1|GPIO_SPEED_100MHz) /* PC6 */ - -/* CAN: */ - -#define GPIO_CAN1_RX (GPIO_CAN1_RX_2|GPIO_SPEED_50MHz) /* PB8 */ -#define GPIO_CAN1_TX (GPIO_CAN1_TX_2|GPIO_SPEED_50MHz) /* PB9 */ - -/* microSD Connector: - * - * ----------------- ----------------- ------------------------ - * SD/MMC CONNECTOR BOARD GPIO CONFIGURATION(s - * PIN SIGNAL SIGNAL (no remapping) - * --- ------------- ----------------- ------------------------- - * 1 DAT2/RES SD_D2/USART3_TX/ PC10 GPIO_SDIO_D2 - * SPI3_SCK - * 2 CD/DAT3/CS SD_D3/USART3_RX/ PC11 GPIO_SDIO_D3 - * SPI3_MISO - * 3 CMD/DI SD_CMD PD2 GPIO_SDIO_CMD - * 4 VDD N/A N/A - * 5 CLK/SCLK SD_CLK/SPI3_MOSI PC12 GPIO_SDIO_CK - * 6 VSS N/A N/A - * 7 DAT0/D0 SD_D0/DCMI_D2 PC8 GPIO_SDIO_D0 - * 8 DAT1/RES SD_D1/DCMI_D3 PC9 GPIO_SDIO_D1 - * --- ------------- ----------------- ------------------------- - * - * NOTES: - * 1. DAT4, DAT4, DAT6, and DAT7 not connected. - * 2. There are no alternative pin selections. - * 3. There is no card detect (CD) GPIO input so we will not - * sense if there is a card in the SD slot or not. This will - * make usage very awkward. - */ - -/* Ethernet: - * - * - PA2 is ETH_MDIO - * - PC1 is ETH_MDC - * - PB5 is ETH_PPS_OUT - NC (not connected) - * - PA0 is ETH_MII_CRS - NC - * - PA3 is ETH_MII_COL - NC - * - PB10 is ETH_MII_RX_ER - NC - * - PB0 is ETH_MII_RXD2 - NC - * - PH7 is ETH_MII_RXD3 - NC - * - PC3 is ETH_MII_TX_CLK - NC - * - PC2 is ETH_MII_TXD2 - NC - * - PB8 is ETH_MII_TXD3 - NC - * - PA1 is ETH_MII_RX_CLK/ETH_RMII_REF_CLK - * - PA7 is ETH_MII_RX_DV/ETH_RMII_CRS_DV - * - PC4 is ETH_MII_RXD0/ETH_RMII_RXD0 - * - PC5 is ETH_MII_RXD1/ETH_RMII_RXD1 - * - PB11 is ETH_MII_TX_EN/ETH_RMII_TX_EN - * - PG13 is ETH_MII_TXD0/ETH_RMII_TXD0 - * - PG14 is ETH_MII_TXD1/ETH_RMII_TXD1 - */ - -#define GPIO_ETH_PPS_OUT (GPIO_ETH_PPS_OUT_1|GPIO_SPEED_100MHz) -#define GPIO_ETH_MII_CRS (GPIO_ETH_MII_CRS_1|GPIO_SPEED_100MHz) -#define GPIO_ETH_MII_COL (GPIO_ETH_MII_COL_1|GPIO_SPEED_100MHz) -#define GPIO_ETH_MII_RX_ER (GPIO_ETH_MII_RX_ER_1|GPIO_SPEED_100MHz) -#define GPIO_ETH_MII_RXD2 (GPIO_ETH_MII_RXD2_1|GPIO_SPEED_100MHz) -#define GPIO_ETH_MII_RXD3 (GPIO_ETH_MII_RXD3_1|GPIO_SPEED_100MHz) -#define GPIO_ETH_MII_TXD3 (GPIO_ETH_MII_TXD3_1|GPIO_SPEED_100MHz) -#define GPIO_ETH_MII_TX_EN (GPIO_ETH_MII_TX_EN_2|GPIO_SPEED_100MHz) -#define GPIO_ETH_MII_TXD0 (GPIO_ETH_MII_TXD0_2|GPIO_SPEED_100MHz) -#define GPIO_ETH_MII_TXD1 (GPIO_ETH_MII_TXD1_2|GPIO_SPEED_100MHz) -#define GPIO_ETH_RMII_TX_EN (GPIO_ETH_RMII_TX_EN_1|GPIO_SPEED_100MHz) -#define GPIO_ETH_RMII_TXD0 (GPIO_ETH_RMII_TXD0_2|GPIO_SPEED_100MHz) -#define GPIO_ETH_RMII_TXD1 (GPIO_ETH_RMII_TXD1_2|GPIO_SPEED_100MHz) - -/* DMA Channel/Stream Selections ********************************************/ - -/* Stream selections are arbitrary for now but might become important in - * the future if we set aside more DMA channels/streams. - * - * SDIO DMA - * DMAMAP_SDIO_1 = Channel 4, Stream 3 - * DMAMAP_SDIO_2 = Channel 4, Stream 6 - */ - -#define DMAMAP_SDIO DMAMAP_SDIO_1 - -/* USART6 - * - * DMAMAP_USART6_RX_1 = Channel 5, Stream1 - * DMAMAP_USART6_RX_2 = Channel 5, Stream2 - * DMAMAP_USART6_TX_1 = Channel 5, Stream6 - * DMAMAP_USART6_TX_2 = Channel 5, Stream7 - */ - -#define DMAMAP_USART6_RX DMAMAP_USART6_RX_1 -#define DMAMAP_USART6_TX DMAMAP_USART6_TX_1 - -/* DHTxx pin configuration */ - -#define GPIO_DHTXX_PIN (GPIO_PORTG|GPIO_PIN9) -#define GPIO_DHTXX_PIN_OUTPUT (GPIO_OUTPUT|GPIO_FLOAT|GPIO_SPEED_100MHz|GPIO_DHTXX_PIN) -#define GPIO_DHTXX_PIN_INPUT (GPIO_INPUT|GPIO_FLOAT|GPIO_DHTXX_PIN) - -#define BOARD_DHTXX_GPIO_INPUT GPIO_DHTXX_PIN_INPUT -#define BOARD_DHTXX_GPIO_OUTPUT GPIO_DHTXX_PIN_OUTPUT -#define BOARD_DHTXX_FRTIMER 1 /* Free-run timer 1 */ - -/* SPI3 - As present in the UEXT header */ - -#define GPIO_SPI3_MISO (GPIO_SPI3_MISO_2|GPIO_SPEED_50MHz) -#define GPIO_SPI3_MOSI (GPIO_SPI3_MOSI_2|GPIO_SPEED_50MHz) -#define GPIO_SPI3_SCK (GPIO_SPI3_SCK_2|GPIO_SPEED_50MHz) - -#define DMACHAN_SPI3_RX DMAMAP_SPI3_RX_1 -#define DMACHAN_SPI3_TX DMAMAP_SPI3_TX_1 - -/* I2S3 - CS4344 configuration uses I2S3 */ - -#define GPIO_I2S3_SD GPIO_I2S3_SD_1 -#define GPIO_I2S3_CK GPIO_I2S3_CK_1 -#define GPIO_I2S3_WS GPIO_I2S3_WS_2 -#define GPIO_I2S3_MCK GPIO_I2S3_MCK_0 - -#define DMACHAN_I2S3_RX DMAMAP_SPI3_RX_2 -#define DMACHAN_I2S3_TX DMAMAP_SPI3_TX_2 - -/* ETH MII/RMII inputs and MDC/MDIO (referenced by arch driver) */ - -#define GPIO_ETH_MDC (GPIO_ETH_MDC_0|GPIO_SPEED_100MHz) -#define GPIO_ETH_MDIO (GPIO_ETH_MDIO_0|GPIO_SPEED_100MHz) -#define GPIO_ETH_MII_RX_CLK (GPIO_ETH_MII_RX_CLK_0|GPIO_SPEED_100MHz) -#define GPIO_ETH_MII_RX_DV (GPIO_ETH_MII_RX_DV_0|GPIO_SPEED_100MHz) -#define GPIO_ETH_MII_RXD0 (GPIO_ETH_MII_RXD0_0|GPIO_SPEED_100MHz) -#define GPIO_ETH_MII_RXD1 (GPIO_ETH_MII_RXD1_0|GPIO_SPEED_100MHz) -#define GPIO_ETH_MII_TX_CLK (GPIO_ETH_MII_TX_CLK_0|GPIO_SPEED_100MHz) -#define GPIO_ETH_MII_TXD2 (GPIO_ETH_MII_TXD2_0|GPIO_SPEED_100MHz) -#define GPIO_ETH_RMII_CRS_DV (GPIO_ETH_RMII_CRS_DV_0|GPIO_SPEED_100MHz) -#define GPIO_ETH_RMII_REF_CLK (GPIO_ETH_RMII_REF_CLK_0|GPIO_SPEED_100MHz) -#define GPIO_ETH_RMII_RXD0 (GPIO_ETH_RMII_RXD0_0|GPIO_SPEED_100MHz) -#define GPIO_ETH_RMII_RXD1 (GPIO_ETH_RMII_RXD1_0|GPIO_SPEED_100MHz) -#define GPIO_MCO1 (GPIO_MCO1_0|GPIO_SPEED_100MHz) - -/* SDIO */ - -#define GPIO_SDIO_CK (GPIO_SDIO_CK_0|GPIO_SPEED_50MHz) -#define GPIO_SDIO_CMD (GPIO_SDIO_CMD_0|GPIO_SPEED_50MHz) -#define GPIO_SDIO_D0 (GPIO_SDIO_D0_0|GPIO_SPEED_50MHz) -#define GPIO_SDIO_D1 (GPIO_SDIO_D1_0|GPIO_SPEED_50MHz) -#define GPIO_SDIO_D2 (GPIO_SDIO_D2_0|GPIO_SPEED_50MHz) -#define GPIO_SDIO_D3 (GPIO_SDIO_D3_0|GPIO_SPEED_50MHz) - -/* USB OTG FS */ - -#define GPIO_OTGFS_DM (GPIO_OTGFS_DM_0|GPIO_SPEED_100MHz) -#define GPIO_OTGFS_DP (GPIO_OTGFS_DP_0|GPIO_SPEED_100MHz) -#define GPIO_OTGFS_ID (GPIO_OTGFS_ID_0|GPIO_SPEED_100MHz) -#define GPIO_OTGFS_SOF (GPIO_OTGFS_SOF_0|GPIO_SPEED_100MHz) - -/* FSMC SRAM */ - -#define GPIO_FSMC_A0 (GPIO_FSMC_A0_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A1 (GPIO_FSMC_A1_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A2 (GPIO_FSMC_A2_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A3 (GPIO_FSMC_A3_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A4 (GPIO_FSMC_A4_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A5 (GPIO_FSMC_A5_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A6 (GPIO_FSMC_A6_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A7 (GPIO_FSMC_A7_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A8 (GPIO_FSMC_A8_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A9 (GPIO_FSMC_A9_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A10 (GPIO_FSMC_A10_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A11 (GPIO_FSMC_A11_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A12 (GPIO_FSMC_A12_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A13 (GPIO_FSMC_A13_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A14 (GPIO_FSMC_A14_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A15 (GPIO_FSMC_A15_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A16 (GPIO_FSMC_A16_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A17 (GPIO_FSMC_A17_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A18 (GPIO_FSMC_A18_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A19 (GPIO_FSMC_A19_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A20 (GPIO_FSMC_A20_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A21 (GPIO_FSMC_A21_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A22 (GPIO_FSMC_A22_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A23 (GPIO_FSMC_A23_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A24 (GPIO_FSMC_A24_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A25 (GPIO_FSMC_A25_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_D0 (GPIO_FSMC_D0_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_D1 (GPIO_FSMC_D1_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_D2 (GPIO_FSMC_D2_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_D3 (GPIO_FSMC_D3_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_D4 (GPIO_FSMC_D4_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_D5 (GPIO_FSMC_D5_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_D6 (GPIO_FSMC_D6_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_D7 (GPIO_FSMC_D7_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_D8 (GPIO_FSMC_D8_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_D9 (GPIO_FSMC_D9_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_D10 (GPIO_FSMC_D10_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_D11 (GPIO_FSMC_D11_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_D12 (GPIO_FSMC_D12_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_D13 (GPIO_FSMC_D13_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_D14 (GPIO_FSMC_D14_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_D15 (GPIO_FSMC_D15_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_NOE (GPIO_FSMC_NOE_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_NWE (GPIO_FSMC_NWE_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_NE1 (GPIO_FSMC_NE1_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_NE2 (GPIO_FSMC_NE2_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_NE3 (GPIO_FSMC_NE3_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_NBL0 (GPIO_FSMC_NBL0_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_NBL1 (GPIO_FSMC_NBL1_0|GPIO_SPEED_100MHz) - -#endif /* __BOARDS_ARM_STM32_OLIMEX_STM32_P407_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32/olimex-stm32-p407/kernel/Makefile b/boards/arm/stm32/olimex-stm32-p407/kernel/Makefile deleted file mode 100644 index 4590512f13460..0000000000000 --- a/boards/arm/stm32/olimex-stm32-p407/kernel/Makefile +++ /dev/null @@ -1,94 +0,0 @@ -############################################################################ -# boards/arm/stm32/olimex-stm32-p407/kernel/Makefile -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/Make.defs - -# The entry point name (if none is provided in the .config file) - -CONFIG_INIT_ENTRYPOINT ?= user_start -ENTRYPT = $(patsubst "%",%,$(CONFIG_INIT_ENTRYPOINT)) - -# Get the paths to the libraries and the links script path in format that -# is appropriate for the host OS - -USER_LIBPATHS = $(addprefix -L,$(call CONVERT_PATH,$(addprefix $(TOPDIR)$(DELIM),$(dir $(USERLIBS))))) -USER_LDSCRIPT = -T $(call CONVERT_PATH,$(BOARD_DIR)$(DELIM)scripts$(DELIM)memory.ld) -USER_LDSCRIPT += -T $(call CONVERT_PATH,$(BOARD_DIR)$(DELIM)scripts$(DELIM)user-space.ld) -USER_HEXFILE += $(call CONVERT_PATH,$(TOPDIR)$(DELIM)nuttx_user.hex) -USER_SRECFILE += $(call CONVERT_PATH,$(TOPDIR)$(DELIM)nuttx_user.srec) -USER_BINFILE += $(call CONVERT_PATH,$(TOPDIR)$(DELIM)nuttx_user.bin) - -USER_LDFLAGS = --undefined=$(ENTRYPT) --entry=$(ENTRYPT) $(USER_LDSCRIPT) -USER_LDLIBS = $(patsubst lib%,-l%,$(basename $(notdir $(USERLIBS)))) -USER_LIBGCC = "${shell "$(CC)" $(ARCHCPUFLAGS) -print-libgcc-file-name}" - -# Source files - -CSRCS = stm32_userspace.c -COBJS = $(CSRCS:.c=$(OBJEXT)) -OBJS = $(COBJS) - -# Targets: - -all: $(TOPDIR)$(DELIM)nuttx_user.elf $(TOPDIR)$(DELIM)User.map -.PHONY: nuttx_user.elf depend clean distclean - -$(COBJS): %$(OBJEXT): %.c - $(call COMPILE, $<, $@) - -# Create the nuttx_user.elf file containing all of the user-mode code - -nuttx_user.elf: $(OBJS) - $(Q) $(LD) -o $@ $(USER_LDFLAGS) $(USER_LIBPATHS) $(OBJS) --start-group $(USER_LDLIBS) --end-group $(USER_LIBGCC) - -$(TOPDIR)$(DELIM)nuttx_user.elf: nuttx_user.elf - @echo "LD: nuttx_user.elf" - $(Q) cp -a nuttx_user.elf $(TOPDIR)$(DELIM)nuttx_user.elf -ifeq ($(CONFIG_INTELHEX_BINARY),y) - @echo "CP: nuttx_user.hex" - $(Q) $(OBJCOPY) $(OBJCOPYARGS) -O ihex nuttx_user.elf $(USER_HEXFILE) -endif -ifeq ($(CONFIG_MOTOROLA_SREC),y) - @echo "CP: nuttx_user.srec" - $(Q) $(OBJCOPY) $(OBJCOPYARGS) -O srec nuttx_user.elf $(USER_SRECFILE) -endif -ifeq ($(CONFIG_RAW_BINARY),y) - @echo "CP: nuttx_user.bin" - $(Q) $(OBJCOPY) $(OBJCOPYARGS) -O binary nuttx_user.elf $(USER_BINFILE) -endif - -$(TOPDIR)$(DELIM)User.map: nuttx_user.elf - @echo "MK: User.map" - $(Q) $(NM) nuttx_user.elf >$(TOPDIR)$(DELIM)User.map - $(Q) $(CROSSDEV)size nuttx_user.elf - -.depend: - -depend: .depend - -clean: - $(call DELFILE, nuttx_user.elf) - $(call DELFILE, "$(TOPDIR)$(DELIM)nuttx_user.*") - $(call DELFILE, "$(TOPDIR)$(DELIM)User.map") - $(call CLEAN) - -distclean: clean diff --git a/boards/arm/stm32/olimex-stm32-p407/kernel/stm32_userspace.c b/boards/arm/stm32/olimex-stm32-p407/kernel/stm32_userspace.c deleted file mode 100644 index 9741858be5840..0000000000000 --- a/boards/arm/stm32/olimex-stm32-p407/kernel/stm32_userspace.c +++ /dev/null @@ -1,111 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/olimex-stm32-p407/kernel/stm32_userspace.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include -#include -#include -#include - -#if defined(CONFIG_BUILD_PROTECTED) && !defined(__KERNEL__) - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -#ifndef CONFIG_NUTTX_USERSPACE -# error "CONFIG_NUTTX_USERSPACE not defined" -#endif - -#if CONFIG_NUTTX_USERSPACE != 0x08020000 -# error "CONFIG_NUTTX_USERSPACE must be 0x08020000 to match memory.ld" -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -static struct userspace_data_s g_userspace_data = -{ - .us_heap = &g_mmheap, -}; - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/* These 'addresses' of these values are setup by the linker script. */ - -extern uint8_t _stext[]; /* Start of .text */ -extern uint8_t _etext[]; /* End_1 of .text + .rodata */ -extern const uint8_t _eronly[]; /* End+1 of read only section (.text + .rodata) */ -extern uint8_t _sdata[]; /* Start of .data */ -extern uint8_t _edata[]; /* End+1 of .data */ -extern uint8_t _sbss[]; /* Start of .bss */ -extern uint8_t _ebss[]; /* End+1 of .bss */ - -const struct userspace_s userspace locate_data(".userspace") = -{ - /* General memory map */ - - .us_entrypoint = CONFIG_INIT_ENTRYPOINT, - .us_textstart = (uintptr_t)_stext, - .us_textend = (uintptr_t)_etext, - .us_datasource = (uintptr_t)_eronly, - .us_datastart = (uintptr_t)_sdata, - .us_dataend = (uintptr_t)_edata, - .us_bssstart = (uintptr_t)_sbss, - .us_bssend = (uintptr_t)_ebss, - - /* User data memory structure */ - - .us_data = &g_userspace_data, - - /* Task/thread startup routines */ - - .task_startup = nxtask_startup, - - /* Signal handler trampoline */ - - .signal_handler = up_signal_handler, - - /* User-space work queue support (declared in include/nuttx/wqueue.h) */ - -#ifdef CONFIG_LIBC_USRWORK - .work_usrstart = work_usrstart, -#endif -}; - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -#endif /* CONFIG_BUILD_PROTECTED && !__KERNEL__ */ diff --git a/boards/arm/stm32/olimex-stm32-p407/scripts/Make.defs b/boards/arm/stm32/olimex-stm32-p407/scripts/Make.defs deleted file mode 100644 index c617c730ec81f..0000000000000 --- a/boards/arm/stm32/olimex-stm32-p407/scripts/Make.defs +++ /dev/null @@ -1,41 +0,0 @@ -############################################################################ -# boards/arm/stm32/olimex-stm32-p407/scripts/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/.config -include $(TOPDIR)/tools/Config.mk -include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs - -LDSCRIPT = flash.ld -ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) - -ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 - -CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) -CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) -CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -AFLAGS := $(CFLAGS) -D__ASSEMBLY__ - -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-gotoff.ld -no-check-sections -LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32/olimex-stm32-p407/scripts/flash.ld b/boards/arm/stm32/olimex-stm32-p407/scripts/flash.ld deleted file mode 100644 index 75ab5f6cdf4a3..0000000000000 --- a/boards/arm/stm32/olimex-stm32-p407/scripts/flash.ld +++ /dev/null @@ -1,124 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/olimex-stm32-p407/scripts/flash.ld - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* The STM32F407VG has 1024Kb of FLASH beginning at address 0x0800:0000 and - * 192Kb of SRAM. SRAM is split up into three blocks: - * - * 1) 112Kb of SRAM beginning at address 0x2000:0000 - * 2) 16Kb of SRAM beginning at address 0x2001:c000 - * 3) 64Kb of CCM SRAM beginning at address 0x1000:0000 - * - * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 - * where the code expects to begin execution by jumping to the entry point in - * the 0x0800:0000 address range. - */ - -MEMORY -{ - flash (rx) : ORIGIN = 0x08000000, LENGTH = 1024K - sram (rwx) : ORIGIN = 0x20000000, LENGTH = 112K -} - -OUTPUT_ARCH(arm) -EXTERN(_vectors) -ENTRY(_stext) -SECTIONS -{ - .text : { - _stext = ABSOLUTE(.); - *(.vectors) - *(.text .text.*) - *(.fixup) - *(.gnu.warning) - *(.rodata .rodata.*) - *(.gnu.linkonce.t.*) - *(.glue_7) - *(.glue_7t) - *(.got) - *(.gcc_except_table) - *(.gnu.linkonce.r.*) - _etext = ABSOLUTE(.); - } > flash - - .init_section : { - _sinit = ABSOLUTE(.); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) - KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) - _einit = ABSOLUTE(.); - } > flash - - .ARM.extab : { - *(.ARM.extab*) - } > flash - - __exidx_start = ABSOLUTE(.); - .ARM.exidx : { - *(.ARM.exidx*) - } > flash - __exidx_end = ABSOLUTE(.); - - .tdata : { - _stdata = ABSOLUTE(.); - *(.tdata .tdata.* .gnu.linkonce.td.*); - _etdata = ABSOLUTE(.); - } > flash - - .tbss : { - _stbss = ABSOLUTE(.); - *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); - _etbss = ABSOLUTE(.); - } > flash - - _eronly = ABSOLUTE(.); - - .data : { - _sdata = ABSOLUTE(.); - *(.data .data.*) - *(.gnu.linkonce.d.*) - CONSTRUCTORS - . = ALIGN(4); - _edata = ABSOLUTE(.); - } > sram AT > flash - - .bss : { - _sbss = ABSOLUTE(.); - *(.bss .bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - . = ALIGN(8); - _ebss = ABSOLUTE(.); - } > sram - - /* Stabs debugging sections. */ - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_info 0 : { *(.debug_info) } - .debug_line 0 : { *(.debug_line) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_aranges 0 : { *(.debug_aranges) } -} diff --git a/boards/arm/stm32/olimex-stm32-p407/scripts/kernel-space.ld b/boards/arm/stm32/olimex-stm32-p407/scripts/kernel-space.ld deleted file mode 100644 index 38a91fff9864f..0000000000000 --- a/boards/arm/stm32/olimex-stm32-p407/scripts/kernel-space.ld +++ /dev/null @@ -1,101 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/olimex-stm32-p407/scripts/kernel-space.ld - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* NOTE: This depends on the memory.ld script having been included prior to - * this script. - */ - -OUTPUT_ARCH(arm) -EXTERN(_vectors) -ENTRY(_stext) - -SECTIONS -{ - .text : { - _stext = ABSOLUTE(.); - *(.vectors) - *(.text .text.*) - *(.fixup) - *(.gnu.warning) - *(.rodata .rodata.*) - *(.gnu.linkonce.t.*) - *(.glue_7) - *(.glue_7t) - *(.got) - *(.gcc_except_table) - *(.gnu.linkonce.r.*) - _etext = ABSOLUTE(.); - } > kflash - - .init_section : { - _sinit = ABSOLUTE(.); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) - KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) - _einit = ABSOLUTE(.); - } > kflash - - .ARM.extab : { - *(.ARM.extab*) - } > kflash - - __exidx_start = ABSOLUTE(.); - .ARM.exidx : { - *(.ARM.exidx*) - } > kflash - - __exidx_end = ABSOLUTE(.); - - _eronly = ABSOLUTE(.); - - .data : { - _sdata = ABSOLUTE(.); - *(.data .data.*) - *(.gnu.linkonce.d.*) - CONSTRUCTORS - . = ALIGN(4); - _edata = ABSOLUTE(.); - } > ksram AT > kflash - - .bss : { - _sbss = ABSOLUTE(.); - *(.bss .bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - . = ALIGN(8); - _ebss = ABSOLUTE(.); - } > ksram - - /* Stabs debugging sections */ - - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_info 0 : { *(.debug_info) } - .debug_line 0 : { *(.debug_line) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_aranges 0 : { *(.debug_aranges) } -} diff --git a/boards/arm/stm32/olimex-stm32-p407/scripts/memory.ld b/boards/arm/stm32/olimex-stm32-p407/scripts/memory.ld deleted file mode 100644 index f877525caa1cc..0000000000000 --- a/boards/arm/stm32/olimex-stm32-p407/scripts/memory.ld +++ /dev/null @@ -1,100 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/olimex-stm32-p407/scripts/memory.ld - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* The STM32F407VG has 1024Kb of FLASH beginning at address 0x0800:0000 and - * 192Kb of SRAM. SRAM is split up into three blocks: - * - * 1) 112KB of SRAM beginning at address 0x2000:0000 - * 2) 16KB of SRAM beginning at address 0x2001:c000 - * 3) 64KB of CCM SRAM beginning at address 0x1000:0000 - * - * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 - * where the code expects to begin execution by jumping to the entry point in - * the 0x0800:0000 address range. - * - * For MPU support, the kernel-mode NuttX section is assumed to be 128Kb of - * FLASH and 8Kb of SRAM. (See boards/stm32f4discovery/scripts/kernel-space.ld). - * Allowing additional memory permitis configuring debug instrumentation to - * be added to the kernel space without overflowing the partition. This could - * just as easily be set to 256Kb or even 512Kb. - * - * Alignment of the user space FLASH partition is also a critical factor: - * The user space FLASH partition will be spanned with a single region of - * size 2**n bytes. The alignment of the user-space region must be the same. - * As a consequence, as the user-space increases in size, the alignment - * requirement also increases. - * - * This alignment requirement means that the largest user space FLASH region - * you can have will be 512KB at it would have to be positioned at - * 0x08800000 (it cannot be positioned at 0x0800000 because vectors power-up - * reset vectors are places at the beginning of that range). If you change - * this address, don't forget to change the CONFIG_NUTTX_USERSPACE - * configuration setting to match and to modify the check in kernel/userspace.c. - * - * With 112Kb of SRAM a 64Kb user heap would seem possible but it is not in - * the current organization of SRAM memory (that could be changed with a - * little effort). The current ordering of SRAM is: (1) kernel .bss/.data, - * (2) user .bss/.data, (3) kernel heap (determined by CONFIG_MM_KERNEL_HEAPSIZE), - * and (4) the user heap. The maximum size of the user space heap is then - * limited to 32Kb beginning at address 0x20008000. - * - * Both of these alignment limitations could be reduced by using multiple - * regions to map the FLASH/SDRAM range or perhaps with some clever use of - * subregions or with multiple MPU regions per memory region. - * - * NOTE: The MPU is used in a mode where mappings are not required for - * kernel addresses and, hence, there are not alignment issues for those - * case. Only the user address spaces suffer from alignment requirements. - * However, in order to exploit this fact, we would still need to change - * the ordering of memory regions in SRAM. - * - * A detailed memory map for the 112KB SRAM region is as follows: - * - * 0x2000 0000: Kernel .data region. Typical size: 0.1KB - * ------ ---- Kernel .bss region. Typical size: 1.8KB - * 0x2000 0800: Kernel IDLE thread stack (approximate). Size is - * determined by CONFIG_IDLETHREAD_STACKSIZE and - * adjustments for alignment. Typical is 1KB. - * ------ ---- Padded to 8KB - * 0x2000 2000: User .data region. Size is variable. - * ------ ---- User .bss region Size is variable. - * 0x2000 4000: Beginning of kernel heap. Size determined by - * CONFIG_MM_KERNEL_HEAPSIZE which must be set to 16Kb. - * 0x2000 8000: Beginning of 32Kb user heap. - * 0x2001 0000: The remainder of SRAM is, unfortunately, wasted. - * 0x2001 c000: End+1 of CPU RAM - */ - -MEMORY -{ - /* 1024Kb FLASH */ - - kflash (rx) : ORIGIN = 0x08000000, LENGTH = 128K - uflash (rx) : ORIGIN = 0x08020000, LENGTH = 128K - xflash (rx) : ORIGIN = 0x08040000, LENGTH = 768K - - /* 112Kb of contiguous SRAM */ - - ksram (rwx) : ORIGIN = 0x20000000, LENGTH = 16K - usram (rwx) : ORIGIN = 0x20004000, LENGTH = 16K - xsram (rwx) : ORIGIN = 0x2000a000, LENGTH = 80K -} diff --git a/boards/arm/stm32/olimex-stm32-p407/scripts/user-space.ld b/boards/arm/stm32/olimex-stm32-p407/scripts/user-space.ld deleted file mode 100644 index c0c286e10c953..0000000000000 --- a/boards/arm/stm32/olimex-stm32-p407/scripts/user-space.ld +++ /dev/null @@ -1,114 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/olimex-stm32-p407/scripts/user-space.ld - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* NOTE: This depends on the memory.ld script having been included prior to - * this script. - */ - -/* Make sure that the critical memory management functions are in user-space. - * the user heap memory manager will reside in user-space but be usable both - * by kernel- and user-space code - */ - -EXTERN(umm_initialize) -EXTERN(umm_addregion) - -EXTERN(malloc) -EXTERN(realloc) -EXTERN(zalloc) -EXTERN(free) - -OUTPUT_ARCH(arm) -SECTIONS -{ - .userspace : { - *(.userspace) - } > uflash - - .text : { - _stext = ABSOLUTE(.); - *(.text .text.*) - *(.fixup) - *(.gnu.warning) - *(.rodata .rodata.*) - *(.gnu.linkonce.t.*) - *(.glue_7) - *(.glue_7t) - *(.got) - *(.gcc_except_table) - *(.gnu.linkonce.r.*) - _etext = ABSOLUTE(.); - } > uflash - - .init_section : { - _sinit = ABSOLUTE(.); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) - KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) - _einit = ABSOLUTE(.); - } > uflash - - .ARM.extab : { - *(.ARM.extab*) - } > uflash - - __exidx_start = ABSOLUTE(.); - .ARM.exidx : { - *(.ARM.exidx*) - } > uflash - - __exidx_end = ABSOLUTE(.); - - _eronly = ABSOLUTE(.); - - .data : { - _sdata = ABSOLUTE(.); - *(.data .data.*) - *(.gnu.linkonce.d.*) - CONSTRUCTORS - . = ALIGN(4); - _edata = ABSOLUTE(.); - } > usram AT > uflash - - .bss : { - _sbss = ABSOLUTE(.); - *(.bss .bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - . = ALIGN(8); - _ebss = ABSOLUTE(.); - } > usram - - /* Stabs debugging sections */ - - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_info 0 : { *(.debug_info) } - .debug_line 0 : { *(.debug_line) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_aranges 0 : { *(.debug_aranges) } -} diff --git a/boards/arm/stm32/olimex-stm32-p407/src/CMakeLists.txt b/boards/arm/stm32/olimex-stm32-p407/src/CMakeLists.txt deleted file mode 100644 index f10df30fa1f73..0000000000000 --- a/boards/arm/stm32/olimex-stm32-p407/src/CMakeLists.txt +++ /dev/null @@ -1,61 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/olimex-stm32-p407/src/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -set(SRCS stm32_boot.c stm32_bringup.c stm32_spi.c stm32_st7735.c) - -if(CONFIG_ARCH_LEDS) - list(APPEND SRCS stm32_autoleds.c) -else() - list(APPEND SRCS stm32_userleds.c) -endif() - -if(CONFIG_ARCH_BUTTONS) - list(APPEND SRCS stm32_buttons.c) -endif() - -if(CONFIG_STM32_FSMC) - list(APPEND SRCS stm32_sram.c) -endif() - -if(CONFIG_STM32_OTGFS) - list(APPEND SRCS stm32_usb.c) -endif() - -if(CONFIG_ADC) - list(APPEND SRCS stm32_adc.c) -endif() - -if(CONFIG_STM32_CAN_CHARDRIVER) - list(APPEND SRCS stm32_can.c) -endif() - -if(CONFIG_AUDIO_CS4344) - list(APPEND SRCS stm32_cs4344.c) -endif() - -if(CONFIG_INPUT_DJOYSTICK) - list(APPEND SRCS stm32_djoystick.c) -endif() - -target_sources(board PRIVATE ${SRCS}) - -set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/flash.ld") diff --git a/boards/arm/stm32/olimex-stm32-p407/src/Make.defs b/boards/arm/stm32/olimex-stm32-p407/src/Make.defs deleted file mode 100644 index 8d0d261b5fb06..0000000000000 --- a/boards/arm/stm32/olimex-stm32-p407/src/Make.defs +++ /dev/null @@ -1,63 +0,0 @@ -############################################################################ -# boards/arm/stm32/olimex-stm32-p407/src/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/Make.defs - -CSRCS = stm32_boot.c stm32_bringup.c stm32_spi.c stm32_st7735.c - -ifeq ($(CONFIG_ARCH_LEDS),y) - CSRCS += stm32_autoleds.c -else - CSRCS += stm32_userleds.c -endif - -ifeq ($(CONFIG_ARCH_BUTTONS),y) - CSRCS += stm32_buttons.c -endif - -ifeq ($(CONFIG_STM32_FSMC),y) - CSRCS += stm32_sram.c -endif - -ifeq ($(CONFIG_STM32_OTGFS),y) - CSRCS += stm32_usb.c -endif - -ifeq ($(CONFIG_ADC),y) - CSRCS += stm32_adc.c -endif - -ifeq ($(CONFIG_STM32_CAN_CHARDRIVER),y) - CSRCS += stm32_can.c -endif - -ifeq ($(CONFIG_AUDIO_CS4344),y) - CSRCS += stm32_cs4344.c -endif - -ifeq ($(CONFIG_INPUT_DJOYSTICK),y) - CSRCS += stm32_djoystick.c -endif - -DEPPATH += --dep-path board -VPATH += :board -CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/olimex-stm32-p407/src/stm32_adc.c b/boards/arm/stm32/olimex-stm32-p407/src/stm32_adc.c deleted file mode 100644 index 37fddf81d0e38..0000000000000 --- a/boards/arm/stm32/olimex-stm32-p407/src/stm32_adc.c +++ /dev/null @@ -1,156 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/olimex-stm32-p407/src/stm32_adc.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include -#include - -#include "chip.h" -#include "stm32_adc.h" -#include "olimex-stm32-p407.h" - -#ifdef CONFIG_ADC - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -/* Up to 3 ADC interfaces are supported */ - -#if STM32_NADC < 3 -# undef CONFIG_STM32_ADC3 -#endif - -#if STM32_NADC < 2 -# undef CONFIG_STM32_ADC2 -#endif - -#if STM32_NADC < 1 -# undef CONFIG_STM32_ADC1 -#endif - -#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) || defined(CONFIG_STM32_ADC3) -#ifndef CONFIG_STM32_ADC1 -# warning "Channel information only available for ADC1" -#endif - -/* The number of ADC channels in the conversion list */ - -#define ADC1_NCHANNELS 1 - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* The Olimex STM32-P407 has a 10 Kohm potentiometer AN_TR connected to PC0 - * ADC123_IN10 - */ - -/* Identifying number of each ADC channel: Variable Resistor. */ - -#ifdef CONFIG_STM32_ADC1 -static const uint8_t g_chanlist[ADC1_NCHANNELS] = -{ - 10 -}; - -/* Configurations of pins used byte each ADC channels */ - -static const uint32_t g_pinlist[ADC1_NCHANNELS] = -{ - GPIO_ADC1_IN10 -}; -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_adc_setup - * - * Description: - * Initialize ADC and register the ADC driver. - * - ****************************************************************************/ - -int stm32_adc_setup(void) -{ -#ifdef CONFIG_STM32_ADC1 - static bool initialized = false; - struct adc_dev_s *adc; - int ret; - int i; - - /* Check if we have already initialized */ - - if (!initialized) - { - /* Configure the pins as analog inputs for the selected channels */ - - for (i = 0; i < ADC1_NCHANNELS; i++) - { - stm32_configgpio(g_pinlist[i]); - } - - /* Call stm32_adcinitialize() to get an instance of the ADC interface */ - - adc = stm32_adcinitialize(1, g_chanlist, ADC1_NCHANNELS); - if (adc == NULL) - { - aerr("ERROR: Failed to get ADC interface\n"); - return -ENODEV; - } - - /* Register the ADC driver at "/dev/adc0" */ - - ret = adc_register("/dev/adc0", adc); - if (ret < 0) - { - aerr("ERROR: adc_register failed: %d\n", ret); - return ret; - } - - /* Now we are initialized */ - - initialized = true; - } - - return OK; -#else - return -ENOSYS; -#endif -} - -#endif /* CONFIG_STM32_ADC1 || CONFIG_STM32_ADC2 || CONFIG_STM32_ADC3 */ -#endif /* CONFIG_ADC */ diff --git a/boards/arm/stm32/olimex-stm32-p407/src/stm32_autoleds.c b/boards/arm/stm32/olimex-stm32-p407/src/stm32_autoleds.c deleted file mode 100644 index a77daaf0ea9ee..0000000000000 --- a/boards/arm/stm32/olimex-stm32-p407/src/stm32_autoleds.c +++ /dev/null @@ -1,160 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/olimex-stm32-p407/src/stm32_autoleds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include "stm32.h" -#include "olimex-stm32-p407.h" - -#ifdef CONFIG_ARCH_LEDS - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* The following definitions map the encoded LED setting to GPIO settings */ - -#define LED_STARTED_BITS (BOARD_LED1_BIT) -#define LED_HEAPALLOCATE_BITS (BOARD_LED2_BIT) -#define LED_IRQSENABLED_BITS (BOARD_LED1_BIT | BOARD_LED2_BIT) -#define LED_STACKCREATED_BITS (BOARD_LED3_BIT) -#define LED_INIRQ_BITS (BOARD_LED1_BIT | BOARD_LED3_BIT) -#define LED_SIGNAL_BITS (BOARD_LED2_BIT | BOARD_LED3_BIT) -#define LED_ASSERTION_BITS (BOARD_LED1_BIT | BOARD_LED2_BIT | BOARD_LED3_BIT) -#define LED_PANIC_BITS (BOARD_LED4_BIT) - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -static const unsigned int g_ledbits[8] = -{ - LED_STARTED_BITS, - LED_HEAPALLOCATE_BITS, - LED_IRQSENABLED_BITS, - LED_STACKCREATED_BITS, - LED_INIRQ_BITS, - LED_SIGNAL_BITS, - LED_ASSERTION_BITS, - LED_PANIC_BITS -}; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -static inline void led_clrbits(unsigned int clrbits) -{ - if ((clrbits & BOARD_LED1_BIT) != 0) - { - stm32_gpiowrite(GPIO_LED1, false); - } - - if ((clrbits & BOARD_LED2_BIT) != 0) - { - stm32_gpiowrite(GPIO_LED2, false); - } - - if ((clrbits & BOARD_LED3_BIT) != 0) - { - stm32_gpiowrite(GPIO_LED3, false); - } - - if ((clrbits & BOARD_LED4_BIT) != 0) - { - stm32_gpiowrite(GPIO_LED4, false); - } -} - -static inline void led_setbits(unsigned int setbits) -{ - if ((setbits & BOARD_LED1_BIT) != 0) - { - stm32_gpiowrite(GPIO_LED1, true); - } - - if ((setbits & BOARD_LED2_BIT) != 0) - { - stm32_gpiowrite(GPIO_LED2, true); - } - - if ((setbits & BOARD_LED3_BIT) != 0) - { - stm32_gpiowrite(GPIO_LED3, true); - } - - if ((setbits & BOARD_LED4_BIT) != 0) - { - stm32_gpiowrite(GPIO_LED4, true); - } -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_autoled_initialize - ****************************************************************************/ - -void board_autoled_initialize(void) -{ - /* Configure LED1-4 GPIOs for output */ - - stm32_configgpio(GPIO_LED1); - stm32_configgpio(GPIO_LED2); - stm32_configgpio(GPIO_LED3); - stm32_configgpio(GPIO_LED4); -} - -/**************************************************************************** - * Name: board_autoled_on - ****************************************************************************/ - -void board_autoled_on(int led) -{ - led_clrbits(BOARD_LED1_BIT | BOARD_LED2_BIT | - BOARD_LED3_BIT | BOARD_LED4_BIT); - led_setbits(g_ledbits[led]); -} - -/**************************************************************************** - * Name: board_autoled_off - ****************************************************************************/ - -void board_autoled_off(int led) -{ - led_clrbits(g_ledbits[led]); -} - -#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/olimex-stm32-p407/src/stm32_boot.c b/boards/arm/stm32/olimex-stm32-p407/src/stm32_boot.c deleted file mode 100644 index 77a521816a5cc..0000000000000 --- a/boards/arm/stm32/olimex-stm32-p407/src/stm32_boot.c +++ /dev/null @@ -1,116 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/olimex-stm32-p407/src/stm32_boot.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include -#include -#include - -#include "olimex-stm32-p407.h" - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_boardinitialize - * - * Description: - * All STM32 architectures must provide the following entry point. - * This entry point is called early in the initialization -- after all - * memory has been configured and mapped but before any devices have been - * initialized. - * - ****************************************************************************/ - -void stm32_boardinitialize(void) -{ -#ifdef CONFIG_STM32_FSMC - /* If the FSMC is enabled, then enable SRAM access */ - - stm32_stram_configure(); -#endif - -#ifdef CONFIG_STM32_OTGFS - /* Initialize USB if the 1) OTG FS controller is in the configuration - * and 2) disabled, and 3) the weak function stm32_usb_configure() has been - * brought into the build. Presumably either CONFIG_USBDEV or - * CONFIG_USBHOST is also selected. - */ - - stm32_usb_configure(); -#endif - - /* Configure on-board LEDs if LED support has been selected. */ - -#ifdef CONFIG_ARCH_LEDS - board_autoled_initialize(); -#endif - - /* Configure on-board BUTTONs if BUTTON support has been selected. */ - -#ifdef CONFIG_ARCH_BUTTONS - board_button_initialize(); -#endif - - /* Configure SPI chip selects if 1) SPI is not disabled, and 2) the weak - * function stm32_spidev_initialize() has been brought into the link. - */ - -#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) ||\ - defined(CONFIG_STM32_SPI3) - if (stm32_spidev_initialize) - { - stm32_spidev_initialize(); - } -#endif -} - -/**************************************************************************** - * Name: board_late_initialize - * - * Description: - * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional - * initialization call will be performed in the boot-up sequence to a - * function called board_late_initialize(). board_late_initialize() will - * be called immediately after up_initialize() is called and just before - * the initial application is started. This additional initialization - * phase may be used, for example, to initialize board-specific device - * drivers. - * - ****************************************************************************/ - -#ifdef CONFIG_BOARD_LATE_INITIALIZE -void board_late_initialize(void) -{ - /* Perform board-specific initialization here if so configured */ - - stm32_bringup(); -} -#endif diff --git a/boards/arm/stm32/olimex-stm32-p407/src/stm32_bringup.c b/boards/arm/stm32/olimex-stm32-p407/src/stm32_bringup.c deleted file mode 100644 index af02950de4527..0000000000000 --- a/boards/arm/stm32/olimex-stm32-p407/src/stm32_bringup.c +++ /dev/null @@ -1,219 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/olimex-stm32-p407/src/stm32_bringup.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include - -#include -#include -#include -#include - -#ifdef CONFIG_USBMONITOR -# include -#endif - -#ifdef CONFIG_MODULE -# include -#endif - -#ifdef CONFIG_STM32_OTGFS -# include "stm32_usbhost.h" -#endif - -#include "stm32.h" -#include "olimex-stm32-p407.h" - -#ifdef CONFIG_SENSORS_DHTXX -#include "stm32_dhtxx.h" -#endif - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -#ifdef HAVE_MODSYMS -extern const struct symtab_s MODSYMS_SYMTAB_ARRAY[]; -extern const int MODSYMS_NSYMBOLS_VAR; -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_bringup - * - * Description: - * Perform architecture-specific initialization - * - * CONFIG_BOARD_LATE_INITIALIZE=y : - * Called from board_late_initialize(). - * - ****************************************************************************/ - -int stm32_bringup(void) -{ -#ifdef HAVE_MMCSD - struct sdio_dev_s *sdio; -#endif - int ret; - -#ifdef CONFIG_FS_PROCFS - /* Mount the procfs file system */ - - ret = nx_mount(NULL, "/proc", "procfs", 0, NULL); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: Failed to mount procfs at /proc: %d\n", ret); - } -#endif - -#ifdef HAVE_MODSYMS - /* Install the module symbol table */ - - libelf_setsymtab(MODSYMS_SYMTAB_ARRAY, MODSYMS_NSYMBOLS_VAR); -#endif - -#ifdef HAVE_MMCSD - /* Mount the SDIO-based MMC/SD block driver */ - - /* First, get an instance of the SDIO interface */ - - sdio = sdio_initialize(MMCSD_SLOTNO); - if (!sdio) - { - syslog(LOG_ERR, - "ERROR: Failed to initialize SDIO slot %d\n", - MMCSD_SLOTNO); - return -ENODEV; - } - - /* Now bind the SDIO interface to the MMC/SD driver */ - - ret = mmcsd_slotinitialize(MMCSD_MINOR, sdio); - if (ret != OK) - { - syslog(LOG_ERR, - "ERROR: Failed to bind SDIO to the MMC/SD driver: %d\n", - ret); - return ret; - } - - /* Then let's guess and say that there is a card in the slot. The Olimex - * STM32 P407 does not support a GPIO to detect if there is a card in - * the slot so we are reduced to guessing. - */ - - sdio_mediachange(sdio, true); -#endif - -#ifdef CONFIG_STM32_CAN_CHARDRIVER - /* Initialize CAN and register the CAN driver. */ - - ret = stm32_can_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_can_setup failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_ADC - /* Initialize ADC and register the ADC driver. */ - - ret = stm32_adc_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_adc_setup failed: %d\n", ret); - } -#endif - -#ifdef HAVE_USBHOST - /* Initialize USB host operation. stm32_usbhost_setup() starts a thread - * will monitor for USB connection and disconnection events. - */ - - ret = stm32_usbhost_setup(); - if (ret != OK) - { - syslog(LOG_ERR, "ERROR: Failed to initialize USB host: %d\n", ret); - return ret; - } -#endif - -#ifdef HAVE_USBMONITOR - /* Start the USB Monitor */ - - ret = usbmonitor_start(); - if (ret != OK) - { - syslog(LOG_ERR, "ERROR: Failed to start USB monitor: %d\n", ret); - } -#endif - -#ifdef CONFIG_INPUT_BUTTONS - /* Register the BUTTON driver */ - - ret = btn_lower_initialize("/dev/buttons"); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: btn_lower_initialize() failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_SENSORS_DHTXX - ret = board_dhtxx_initialize(0); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_dhtxx_initialize() failed: %d\n", ret); - } -#endif - -#ifdef HAVE_CS4344 - /* Configure CS4344 audio */ - - ret = stm32_cs4344_initialize(1); - if (ret != OK) - { - syslog(LOG_ERR, "Failed to initialize CS4344 audio: %d\n", ret); - } -#endif - -#ifdef CONFIG_INPUT_DJOYSTICK - ret = stm32_djoy_initialize(); - if (ret != OK) - { - syslog(LOG_ERR, "Failed to register djoystick driver: %d\n", ret); - } -#endif - - UNUSED(ret); - return OK; -} diff --git a/boards/arm/stm32/olimex-stm32-p407/src/stm32_buttons.c b/boards/arm/stm32/olimex-stm32-p407/src/stm32_buttons.c deleted file mode 100644 index a17716582e138..0000000000000 --- a/boards/arm/stm32/olimex-stm32-p407/src/stm32_buttons.c +++ /dev/null @@ -1,188 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/olimex-stm32-p407/src/stm32_buttons.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include -#include - -#include "stm32_gpio.h" - -#include "olimex-stm32-p407.h" - -#ifdef CONFIG_ARCH_BUTTONS - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* Pin configuration for each STM32F4 Discovery button. This array is indexed - * by the BUTTON_* definitions in board.h - */ - -static const uint32_t g_buttons[NUM_BUTTONS] = -{ - GPIO_BTN_TAMPER, - GPIO_BTN_WKUP, - - /* The Joystick is treated like the other buttons unless - * CONFIG_INPUT_DJOYSTICK is defined, then it is assumed that they should - * be used by the discrete joystick driver. - */ - -#ifndef CONFIG_INPUT_DJOYSTICK - GPIO_JOY_RIGHT, - GPIO_JOY_UP, - GPIO_JOY_LEFT, - GPIO_JOY_DOWN, - GPIO_JOY_CENTER -#endif -}; - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_button_initialize - * - * Description: - * board_button_initialize() must be called to initialize button resources. - * After that, board_buttons() may be called to collect the current state - * of all buttons or board_button_irq() may be called to register button - * interrupt handlers. - * - ****************************************************************************/ - -uint32_t board_button_initialize(void) -{ - int i; - - /* Configure the GPIO pins as inputs. NOTE that EXTI interrupts are - * configured for all pins. - */ - - for (i = 0; i < NUM_BUTTONS; i++) - { - stm32_configgpio(g_buttons[i]); - } - - return NUM_BUTTONS; -} - -/**************************************************************************** - * Name: board_buttons - ****************************************************************************/ - -uint32_t board_buttons(void) -{ - uint32_t ret = 0; - - /* Check that state of each key */ - - if (!stm32_gpioread(g_buttons[BUTTON_TAMPER])) - { - ret |= BUTTON_TAMPER_BIT; - } - - if (stm32_gpioread(g_buttons[BUTTON_WKUP])) - { - ret |= BUTTON_WKUP_BIT; - } - -#ifndef CONFIG_INPUT_DJOYSTICK - if (stm32_gpioread(g_buttons[JOYSTICK_RIGHT])) - { - ret |= JOYSTICK_RIGHT_BIT; - } - - if (stm32_gpioread(g_buttons[JOYSTICK_UP])) - { - ret |= JOYSTICK_UP_BIT; - } - - if (stm32_gpioread(g_buttons[JOYSTICK_LEFT])) - { - ret |= JOYSTICK_LEFT_BIT; - } - - if (stm32_gpioread(g_buttons[JOYSTICK_DOWN])) - { - ret |= JOYSTICK_DOWN_BIT; - } - - if (stm32_gpioread(g_buttons[JOYSTICK_CENTER])) - { - ret |= JOYSTICK_CENTER_BIT; - } -#endif - - return ret; -} - -/**************************************************************************** - * Button support. - * - * Description: - * board_button_initialize() must be called to initialize button resources. - * After that, board_buttons() may be called to collect the current state - * of all buttons or board_button_irq() may be called to register button - * interrupt handlers. - * - * After board_button_initialize() has been called, board_buttons() may be - * called to collect the state of all buttons. board_buttons() returns an - * 32-bit bit set with each bit associated with a button. See the - * BUTTON_*_BIT definitions in board.h for the meaning of each bit. - * - * board_button_irq() may be called to register an interrupt handler that - * will be called when a button is depressed or released. The ID value is a - * button enumeration value that uniquely identifies a button resource. See - * the BUTTON_* definitions in board.h for the meaning of enumeration - * value. - * - ****************************************************************************/ - -#ifdef CONFIG_ARCH_IRQBUTTONS -int board_button_irq(int id, xcpt_t irqhandler, void *arg) -{ - int ret = -EINVAL; - - /* The following should be atomic */ - - if (id >= MIN_IRQBUTTON && id <= MAX_IRQBUTTON) - { - ret = stm32_gpiosetevent(g_buttons[id], true, true, true, - irqhandler, arg); - } - - return ret; -} -#endif -#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/stm32/olimex-stm32-p407/src/stm32_can.c b/boards/arm/stm32/olimex-stm32-p407/src/stm32_can.c deleted file mode 100644 index 71bc50e3bc67e..0000000000000 --- a/boards/arm/stm32/olimex-stm32-p407/src/stm32_can.c +++ /dev/null @@ -1,100 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/olimex-stm32-p407/src/stm32_can.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include - -#include "stm32.h" -#include "stm32_can.h" -#include "olimex-stm32-p407.h" - -#ifdef CONFIG_CAN - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -#if defined(CONFIG_STM32_CAN1) && defined(CONFIG_STM32_CAN2) -# warning "Both CAN1 and CAN2 are enabled. Only CAN1 is connected." -# undef CONFIG_STM32_CAN2 -#endif - -#ifdef CONFIG_STM32_CAN1 -# define CAN_PORT 1 -#else -# define CAN_PORT 2 -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_can_setup - * - * Description: - * Initialize CAN and register the CAN device - * - ****************************************************************************/ - -int stm32_can_setup(void) -{ -#if defined(CONFIG_STM32_CAN1) || defined(CONFIG_STM32_CAN2) - struct can_dev_s *can; - int ret; - - /* Call stm32_caninitialize() to get an instance of the CAN interface */ - - can = stm32_caninitialize(CAN_PORT); - if (can == NULL) - { - canerr("ERROR: Failed to get CAN interface\n"); - return -ENODEV; - } - - /* Register the CAN driver at "/dev/can0" */ - - ret = can_register("/dev/can0", can); - if (ret < 0) - { - canerr("ERROR: can_register failed: %d\n", ret); - return ret; - } - - return OK; -#else - return -ENODEV; -#endif -} - -#endif /* CONFIG_CAN */ diff --git a/boards/arm/stm32/olimex-stm32-p407/src/stm32_cs4344.c b/boards/arm/stm32/olimex-stm32-p407/src/stm32_cs4344.c deleted file mode 100644 index fdef20aabf027..0000000000000 --- a/boards/arm/stm32/olimex-stm32-p407/src/stm32_cs4344.c +++ /dev/null @@ -1,172 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/olimex-stm32-p407/src/stm32_cs4344.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -#include - -#include "stm32.h" -#include "olimex-stm32-p407.h" - -#ifdef HAVE_CS4344 - -/**************************************************************************** - * Pre-Processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_cs4344_initialize - * - * Description: - * This function is called by platform-specific, setup logic to configure - * and register the CS4344 device. This function will register the driver - * as /dev/audio/pcm[x] where x is determined by the minor device number. - * - * Input Parameters: - * minor - The input device minor number - * - * Returned Value: - * Zero is returned on success. Otherwise, a negated errno value is - * returned to indicate the nature of the failure. - * - ****************************************************************************/ - -int stm32_cs4344_initialize(int minor) -{ - struct audio_lowerhalf_s *cs4344; - struct audio_lowerhalf_s *pcm; - struct i2s_dev_s *i2s; - static bool initialized = false; - char devname[12]; - int ret; - - audinfo("minor %d\n", minor); - DEBUGASSERT(minor >= 0 && minor <= 25); - - /* Have we already initialized? Since we never uninitialize we must - * prevent multiple initializations. This is necessary, for example, - * when the touchscreen example is used as a built-in application in - * NSH and can be called numerous time. It will attempt to initialize - * each time. - */ - - if (!initialized) - { - /* Get an instance of the I2S interface for the CS4344 data channel */ - - i2s = stm32_i2sbus_initialize(CS4344_I2S_BUS); - if (!i2s) - { - auderr("ERROR: Failed to initialize I2S%d\n", CS4344_I2S_BUS); - ret = -ENODEV; - goto errout; - } - - /* Now we can use this I2S interface to initialize the CS4344 which - * will return an audio interface. - */ - - cs4344 = cs4344_initialize(i2s); - if (!cs4344) - { - auderr("ERROR: Failed to initialize the CS4344\n"); - ret = -ENODEV; - goto errout; - } - - /* No we can embed the CS4344/I2S conglomerate into a PCM decoder - * instance so that we will have a PCM front end for the CS4344 - * driver. - */ - - pcm = pcm_decode_initialize(cs4344); - if (!pcm) - { - auderr("ERROR: Failed create the PCM decoder\n"); - ret = -ENODEV; - goto errout; - } - - /* Create a device name */ - - snprintf(devname, sizeof(devname), "pcm%d", minor); - - /* Finally, we can register the PCM/CS4344/I2S audio device. - * - * Is anyone young enough to remember Rube Goldberg? - */ - - ret = audio_register(devname, pcm); - if (ret < 0) - { - auderr("ERROR: Failed to register /dev/%s device: %d\n", - devname, ret); - goto errout; - } - - /* Now we are initialized */ - - initialized = true; - } - - return OK; - -errout: - return ret; -} - -#endif /* HAVE_CS4344 */ diff --git a/boards/arm/stm32/olimex-stm32-p407/src/stm32_djoystick.c b/boards/arm/stm32/olimex-stm32-p407/src/stm32_djoystick.c deleted file mode 100644 index 4f96e0bff419e..0000000000000 --- a/boards/arm/stm32/olimex-stm32-p407/src/stm32_djoystick.c +++ /dev/null @@ -1,299 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/olimex-stm32-p407/src/stm32_djoystick.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include -#include -#include - -#include "stm32_gpio.h" -#include "olimex-stm32-p407.h" - -#ifdef CONFIG_INPUT_DJOYSTICK - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Number of Joystick discretes */ - -#define DJOY_NGPIOS 5 - -/* Bitset of supported Joystick discretes */ - -#define DJOY_SUPPORTED (DJOY_UP_BIT | DJOY_DOWN_BIT | DJOY_LEFT_BIT | \ - DJOY_RIGHT_BIT | DJOY_BUTTON_SELECT_BIT) - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -static djoy_buttonset_t - djoy_supported(const struct djoy_lowerhalf_s *lower); -static djoy_buttonset_t - djoy_sample(const struct djoy_lowerhalf_s *lower); -static void djoy_enable(const struct djoy_lowerhalf_s *lower, - djoy_buttonset_t press, djoy_buttonset_t release, - djoy_interrupt_t handler, void *arg); - -static void djoy_disable(void); -static int djoy_interrupt(int irq, void *context, void *arg); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* Pin configuration for each Olimex-P407 joystick "button." Index using - * DJOY_* definitions in include/nuttx/input/djoystick.h. - */ - -static const uint16_t g_joygpio[DJOY_NGPIOS] = -{ - GPIO_JOY_UP, GPIO_JOY_DOWN, GPIO_JOY_LEFT, GPIO_JOY_RIGHT, GPIO_JOY_CENTER -}; - -/* Current interrupt handler and argument */ - -static djoy_interrupt_t g_djoyhandler; -static void *g_djoyarg; - -/* This is the discrete joystick lower half driver interface */ - -static const struct djoy_lowerhalf_s g_djoylower = -{ - .dl_supported = djoy_supported, - .dl_sample = djoy_sample, - .dl_enable = djoy_enable, -}; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: djoy_supported - * - * Description: - * Return the set of buttons supported on the discrete joystick device - * - ****************************************************************************/ - -static djoy_buttonset_t - djoy_supported(const struct djoy_lowerhalf_s *lower) -{ - iinfo("Supported: %02x\n", DJOY_SUPPORTED); - return (djoy_buttonset_t)DJOY_SUPPORTED; -} - -/**************************************************************************** - * Name: djoy_sample - * - * Description: - * Return the current state of all discrete joystick buttons - * - ****************************************************************************/ - -static djoy_buttonset_t djoy_sample(const struct djoy_lowerhalf_s *lower) -{ - djoy_buttonset_t ret = 0; - int i; - - /* Read each joystick GPIO value */ - - for (i = 0; i < DJOY_NGPIOS; i++) - { - bool released = stm32_gpioread(g_joygpio[i]); - if (!released) - { - ret |= (1 << i); - } - } - - iinfo("Retuning: %02x\n", DJOY_SUPPORTED); - return ret; -} - -/**************************************************************************** - * Name: djoy_enable - * - * Description: - * Enable interrupts on the selected set of joystick buttons. And empty - * set will disable all interrupts. - * - ****************************************************************************/ - -static void djoy_enable(const struct djoy_lowerhalf_s *lower, - djoy_buttonset_t press, djoy_buttonset_t release, - djoy_interrupt_t handler, void *arg) -{ - irqstate_t flags; - djoy_buttonset_t either = press | release; - djoy_buttonset_t bit; - bool rising; - bool falling; - int i; - - /* Start with all interrupts disabled */ - - flags = enter_critical_section(); - djoy_disable(); - - iinfo("press: %02x release: %02x handler: %p arg: %p\n", - press, release, handler, arg); - - /* If no events are indicated or if no handler is provided, then this - * must really be a request to disable interrupts. - */ - - if (either && handler) - { - /* Save the new the handler and argument */ - - g_djoyhandler = handler; - g_djoyarg = arg; - - /* Check each GPIO. */ - - for (i = 0; i < DJOY_NGPIOS; i++) - { - /* Enable interrupts on each pin that has either a press or - * release event associated with it. - */ - - bit = (1 << i); - if ((either & bit) != 0) - { - /* Active low so a press corresponds to a falling edge and - * a release corresponds to a rising edge. - */ - - falling = ((press & bit) != 0); - rising = ((release & bit) != 0); - - iinfo("GPIO %d: rising: %d falling: %d\n", - i, rising, falling); - - stm32_gpiosetevent(g_joygpio[i], rising, falling, - true, djoy_interrupt, NULL); - } - } - } - - leave_critical_section(flags); -} - -/**************************************************************************** - * Name: djoy_disable - * - * Description: - * Disable all joystick interrupts - * - ****************************************************************************/ - -static void djoy_disable(void) -{ - irqstate_t flags; - int i; - - /* Disable each joystick interrupt */ - - flags = enter_critical_section(); - for (i = 0; i < DJOY_NGPIOS; i++) - { - stm32_gpiosetevent(g_joygpio[i], false, false, false, NULL, NULL); - } - - leave_critical_section(flags); - - /* Nullify the handler and argument */ - - g_djoyhandler = NULL; - g_djoyarg = NULL; -} - -/**************************************************************************** - * Name: djoy_interrupt - * - * Description: - * Discrete joystick interrupt handler - * - ****************************************************************************/ - -static int djoy_interrupt(int irq, void *context, void *arg) -{ - DEBUGASSERT(g_djoyhandler); - if (g_djoyhandler) - { - g_djoyhandler(&g_djoylower, g_djoyarg); - } - - return OK; -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_djoy_initialize - * - * Description: - * Initialize and register the discrete joystick driver - * - ****************************************************************************/ - -int stm32_djoy_initialize(void) -{ - int i; - - /* Configure the GPIO pins as inputs. NOTE: This is unnecessary for - * interrupting pins since it will also be done by stm32_gpiosetevent(). - */ - - for (i = 0; i < DJOY_NGPIOS; i++) - { - stm32_configgpio(g_joygpio[i]); - } - - /* Make sure that all interrupts are disabled */ - - djoy_disable(); - - /* Register the joystick device as /dev/djoy0 */ - - return djoy_register("/dev/djoy0", &g_djoylower); -} - -#endif /* CONFIG_INPUT_DJOYSTICK */ diff --git a/boards/arm/stm32/olimex-stm32-p407/src/stm32_spi.c b/boards/arm/stm32/olimex-stm32-p407/src/stm32_spi.c deleted file mode 100644 index 75b6ec8f9723c..0000000000000 --- a/boards/arm/stm32/olimex-stm32-p407/src/stm32_spi.c +++ /dev/null @@ -1,197 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/olimex-stm32-p407/src/stm32_spi.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include - -#include -#include - -#include "arm_internal.h" -#include "chip.h" -#include "stm32.h" - -#include "olimex-stm32-p407.h" - -#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) ||\ - defined(CONFIG_STM32_SPI3) - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_spidev_initialize - * - * Description: - * Called to configure SPI chip select GPIO pins for the olimex - * board. - * - ****************************************************************************/ - -void weak_function stm32_spidev_initialize(void) -{ - stm32_configgpio(GPIO_ST7735_CS); -} - -/**************************************************************************** - * Name: stm32_spi1/2/3select and stm32_spi1/2/3status - * - * Description: - * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status - * must be provided by board-specific logic. They are implementations of - * the select and status methods of the SPI interface defined by struct - * spi_ops_s (see include/nuttx/spi/spi.h). All other methods (including - * stm32_spibus_initialize()) are provided by common STM32 logic. To use - * this common SPI logic on your board: - * - * 1. Provide logic in stm32_boardinitialize() to configure SPI chip select - * pins. - * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() functions - * in your board-specific logic. These functions will perform chip - * selection and status operations using GPIOs in the way your board - * is configured. - * 3. Add a call to stm32_spibus_initialize() in your low level application - * initialization logic - * 4. The handle returned by stm32_spibus_initialize() may then be used to - * bind the SPI driver to higher level logic (e.g., calling - * mmcsd_spislotinitialize(), for example, will bind the SPI driver to - * the SPI MMC/SD driver). - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_SPI1 -void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, - bool selected) -{ - spiinfo("devid: %d CS: %s\n", - (int)devid, selected ? "assert" : "de-assert"); -} - -uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) -{ - return 0; -} -#endif - -#ifdef CONFIG_STM32_SPI2 -void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid, - bool selected) -{ - spiinfo("devid: %d CS: %s\n", - (int)devid, selected ? "assert" : "de-assert"); -} - -uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) -{ - return 0; -} -#endif - -#ifdef CONFIG_STM32_SPI3 -void stm32_spi3select(struct spi_dev_s *dev, uint32_t devid, - bool selected) -{ - spiinfo("devid: %d CS: %s\n", - (int)devid, selected ? "assert" : "de-assert"); - -#ifdef CONFIG_LCD_ST7735 - if (devid == SPIDEV_DISPLAY(0)) - { - stm32_gpiowrite(GPIO_ST7735_CS, !selected); - } -#endif -} - -uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid) -{ - return 0; -} -#endif - -/**************************************************************************** - * Name: stm32_spi1cmddata - * - * Description: - * Set or clear the SH1101A A0 or SD1306 D/C n bit to select data (true) - * or command (false). This function must be provided by platform-specific - * logic. This is an implementation of the cmddata method of the SPI - * interface defined by struct spi_ops_s (see include/nuttx/spi/spi.h). - * - * Input Parameters: - * - * spi - SPI device that controls the bus the device that requires the CMD/ - * DATA selection. - * devid - If there are multiple devices on the bus, this selects which one - * to select cmd or data. NOTE: This design restricts, for example, - * one one SPI display per SPI bus. - * cmd - true: select command; false: select data - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef CONFIG_SPI_CMDDATA -#ifdef CONFIG_STM32_SPI1 -int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) -{ - return -ENODEV; -} -#endif - -#ifdef CONFIG_STM32_SPI2 -int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) -{ - return -ENODEV; -} -#endif - -#ifdef CONFIG_STM32_SPI3 -int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) -{ - /* This is the Data/Command control pad which determines whether the - * data bits are data or a command. - */ - -#ifdef CONFIG_LCD_ST7735 - if (devid == SPIDEV_DISPLAY(0)) - { - stm32_gpiowrite(GPIO_ST7735_AO, !cmd); - return OK; - } -#endif - - return -ENODEV; -} -#endif -#endif /* CONFIG_SPI_CMDDATA */ - -#endif /* CONFIG_STM32_SPI1 || CONFIG_STM32_SPI2 */ diff --git a/boards/arm/stm32/olimex-stm32-p407/src/stm32_usb.c b/boards/arm/stm32/olimex-stm32-p407/src/stm32_usb.c deleted file mode 100644 index a21739968a7c6..0000000000000 --- a/boards/arm/stm32/olimex-stm32-p407/src/stm32_usb.c +++ /dev/null @@ -1,330 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/olimex-stm32-p407/src/stm32_usb.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -#include "arm_internal.h" -#include "stm32.h" -#include "stm32_otgfs.h" -#include "olimex-stm32-p407.h" - -#ifdef CONFIG_STM32_OTGFS - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#if defined(CONFIG_USBDEV) || defined(CONFIG_USBHOST) -# define HAVE_USB 1 -#else -# warning "CONFIG_STM32_OTGFS is enabled but neither CONFIG_USBDEV nor CONFIG_USBHOST" -# undef HAVE_USB -#endif - -#ifndef CONFIG_OLIMEXP407_USBHOST_PRIO -# define CONFIG_OLIMEXP407_USBHOST_PRIO 100 -#endif - -#ifndef CONFIG_OLIMEXP407_USBHOST_STACKSIZE -# define CONFIG_OLIMEXP407_USBHOST_STACKSIZE 1024 -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -#ifdef CONFIG_USBHOST -static struct usbhost_connection_s *g_usbconn; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: usbhost_waiter - * - * Description: - * Wait for USB devices to be connected. - * - ****************************************************************************/ - -#ifdef CONFIG_USBHOST -static int usbhost_waiter(int argc, char *argv[]) -{ - struct usbhost_hubport_s *hport; - - uinfo("Running\n"); - for (; ; ) - { - /* Wait for the device to change state */ - - DEBUGVERIFY(CONN_WAIT(g_usbconn, &hport)); - uinfo("%s\n", hport->connected ? "connected" : "disconnected"); - - /* Did we just become connected? */ - - if (hport->connected) - { - /* Yes.. enumerate the newly connected device */ - - CONN_ENUMERATE(g_usbconn, hport); - } - } - - /* Keep the compiler from complaining */ - - return 0; -} -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_usb_configure - * - * Description: - * Called from stm32_usb_configure very early in initialization to setup - * USB-related GPIO pins for the Olimex STM32 P407 board. - * - ****************************************************************************/ - -void stm32_usb_configure(void) -{ -#ifdef CONFIG_STM32_OTGFS - /* The OTG FS has an internal soft pull-up. - * No GPIO configuration is required - */ - - /* Configure the OTG FS VBUS sensing GPIO, - * Power On, and Overcurrent GPIOs - */ - - stm32_configgpio(GPIO_OTGFS_VBUS); - stm32_configgpio(GPIO_OTGFS_PWRON); - stm32_configgpio(GPIO_OTGFS_OVER); -#endif -} - -/**************************************************************************** - * Name: stm32_usbhost_setup - * - * Description: - * Called at application startup time to initialize the USB host - * functionality. - * This function will start a thread that will monitor for device - * connection/disconnection events. - * - ****************************************************************************/ - -#ifdef CONFIG_USBHOST -int stm32_usbhost_setup(void) -{ - int ret; - - /* First, register all of the class drivers needed to support the drivers - * that we care about: - */ - - uinfo("Register class drivers\n"); - -#ifdef CONFIG_USBHOST_HUB - /* Initialize USB hub class support */ - - ret = usbhost_hub_initialize(); - if (ret < 0) - { - uerr("ERROR: usbhost_hub_initialize failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_USBHOST_MSC - /* Register the USB mass storage class class */ - - ret = usbhost_msc_initialize(); - if (ret != OK) - { - uerr("ERROR: Failed to register the mass storage class: %d\n", ret); - } -#endif - -#ifdef CONFIG_USBHOST_CDCACM - /* Register the CDC/ACM serial class */ - - ret = usbhost_cdcacm_initialize(); - if (ret != OK) - { - uerr("ERROR: Failed to register the CDC/ACM serial class: %d\n", ret); - } -#endif - -#ifdef CONFIG_USBHOST_HIDKBD - /* Initialize the HID keyboard class */ - - ret = usbhost_kbdinit(); - if (ret != OK) - { - uerr("ERROR: Failed to register the HID keyboard class\n"); - } -#endif - -#ifdef CONFIG_USBHOST_HIDMOUSE - /* Initialize the HID mouse class */ - - ret = usbhost_mouse_init(); - if (ret != OK) - { - uerr("ERROR: Failed to register the HID mouse class\n"); - } -#endif - - /* Then get an instance of the USB host interface */ - - uinfo("Initialize USB host\n"); - g_usbconn = stm32_otgfshost_initialize(0); - if (g_usbconn) - { - /* Start a thread to handle device connection. */ - - uinfo("Start usbhost_waiter\n"); - - ret = kthread_create("usbhost", CONFIG_OLIMEXP407_USBHOST_PRIO, - CONFIG_OLIMEXP407_USBHOST_STACKSIZE, - usbhost_waiter, NULL); - return ret < 0 ? -ENOEXEC : OK; - } - - return -ENODEV; -} -#endif - -/**************************************************************************** - * Name: stm32_usbhost_vbusdrive - * - * Description: - * Enable/disable driving of VBUS 5V output. This function must be - * provided be each platform that implements the STM32 OTG FS host - * interface - * - * "On-chip 5 V VBUS generation is not supported. For this reason, a - * charge pump or, if 5 V are available on the application board, a - * basic power switch, must be added externally to drive the 5 V VBUS - * line. The external charge pump can be driven by any GPIO output. - * When the application decides to power on VBUS using the chosen GPIO, - * it must also set the port power bit in the host port control and - * status register (PPWR bit in OTG_FS_HPRT). - * - * "The application uses this field to control power to this port, - * and the core clears this bit on an overcurrent condition." - * - * Input Parameters: - * iface - For future growth to handle multiple USB host interface. - * Should be zero. - * enable - true: enable VBUS power; false: disable VBUS power - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef CONFIG_USBHOST -void stm32_usbhost_vbusdrive(int iface, bool enable) -{ - DEBUGASSERT(iface == 0); - - if (enable) - { - /* Enable the Power Switch by driving the enable pin low */ - - stm32_gpiowrite(GPIO_OTGFS_PWRON, false); - } - else - { - /* Disable the Power Switch by driving the enable pin high */ - - stm32_gpiowrite(GPIO_OTGFS_PWRON, true); - } -} -#endif - -/**************************************************************************** - * Name: stm32_setup_overcurrent - * - * Description: - * Setup to receive an interrupt-level callback if an overcurrent - * condition is detected. - * - * Input Parameters: - * handler - New overcurrent interrupt handler - * arg - The argument provided for the interrupt handler - * - * Returned Value: - * Zero (OK) is returned on success. Otherwise, a negated errno value - * is returned to indicate the nature of the failure. - * - ****************************************************************************/ - -#ifdef CONFIG_USBHOST -int stm32_setup_overcurrent(xcpt_t handler, void *arg) -{ - return stm32_gpiosetevent(GPIO_OTGFS_OVER, true, true, true, handler, arg); -} -#endif - -/**************************************************************************** - * Name: stm32_usbsuspend - * - * Description: - * Board logic must provide the stm32_usbsuspend logic if the USBDEV - * driver is used. This function is called whenever the USB enters or - * leaves suspend mode. This is an opportunity for the board logic to - * shutdown clocks, power, etc. while the USB is suspended. - * - ****************************************************************************/ - -#ifdef CONFIG_USBDEV -void stm32_usbsuspend(struct usbdev_s *dev, bool resume) -{ - uinfo("resume: %d\n", resume); -} -#endif - -#endif /* CONFIG_STM32_OTGFS */ diff --git a/boards/arm/stm32/olimex-stm32-p407/src/stm32_userleds.c b/boards/arm/stm32/olimex-stm32-p407/src/stm32_userleds.c deleted file mode 100644 index 2a7ceec92a30a..0000000000000 --- a/boards/arm/stm32/olimex-stm32-p407/src/stm32_userleds.c +++ /dev/null @@ -1,104 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/olimex-stm32-p407/src/stm32_userleds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include "stm32.h" -#include "olimex-stm32-p407.h" - -#ifndef CONFIG_ARCH_LEDS - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* This array maps an LED number to GPIO pin configuration */ - -static uint32_t g_ledcfg[BOARD_NLEDS] = -{ - GPIO_LED1, GPIO_LED2, GPIO_LED3, GPIO_LED4 -}; - -/**************************************************************************** - * Private Function Protototypes - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_userled_initialize - ****************************************************************************/ - -uint32_t board_userled_initialize(void) -{ - /* Configure LED1-4 GPIOs for output */ - - stm32_configgpio(GPIO_LED1); - stm32_configgpio(GPIO_LED2); - stm32_configgpio(GPIO_LED3); - stm32_configgpio(GPIO_LED4); - return BOARD_NLEDS; -} - -/**************************************************************************** - * Name: board_userled - ****************************************************************************/ - -void board_userled(int led, bool ledon) -{ - if ((unsigned)led < BOARD_NLEDS) - { - stm32_gpiowrite(g_ledcfg[led], ledon); - } -} - -/**************************************************************************** - * Name: board_userled_all - ****************************************************************************/ - -void board_userled_all(uint32_t ledset) -{ - stm32_gpiowrite(GPIO_LED1, (ledset & BOARD_LED1_BIT) != 0); - stm32_gpiowrite(GPIO_LED2, (ledset & BOARD_LED2_BIT) != 0); - stm32_gpiowrite(GPIO_LED3, (ledset & BOARD_LED3_BIT) != 0); - stm32_gpiowrite(GPIO_LED4, (ledset & BOARD_LED4_BIT) != 0); -} - -#endif /* !CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/olimexino-stm32/CMakeLists.txt b/boards/arm/stm32/olimexino-stm32/CMakeLists.txt deleted file mode 100644 index bf93e02b885aa..0000000000000 --- a/boards/arm/stm32/olimexino-stm32/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/olimexino-stm32/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32/olimexino-stm32/configs/can/defconfig b/boards/arm/stm32/olimexino-stm32/configs/can/defconfig deleted file mode 100644 index d02669c55029d..0000000000000 --- a/boards/arm/stm32/olimexino-stm32/configs/can/defconfig +++ /dev/null @@ -1,98 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_DISABLE_OS_API is not set -# CONFIG_DISABLE_PSEUDOFS_OPERATIONS is not set -# CONFIG_NSH_DISABLE_CMP is not set -# CONFIG_NSH_DISABLE_DF is not set -# CONFIG_NSH_DISABLE_EXEC is not set -# CONFIG_NSH_DISABLE_GET is not set -# CONFIG_NSH_DISABLE_HEXDUMP is not set -# CONFIG_NSH_DISABLE_PS is not set -# CONFIG_NSH_DISABLE_PUT is not set -# CONFIG_NSH_DISABLE_XD is not set -CONFIG_ANALOG=y -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="olimexino-stm32" -CONFIG_ARCH_BOARD_OLIMEXINO_STM32=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F103RB=y -CONFIG_ARCH_HIPRI_INTERRUPT=y -CONFIG_ARCH_INTERRUPTSTACK=340 -CONFIG_ARCH_IRQBUTTONS=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=5483 -CONFIG_BUILTIN=y -CONFIG_CAN_EXTID=y -CONFIG_CAN_LOOPBACK=y -CONFIG_DEBUG_FULLOPT=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_DEFAULT_SMALL=y -CONFIG_EXAMPLES_CAN=y -CONFIG_EXAMPLES_HELLOXX=y -CONFIG_FAT_LCNAMES=y -CONFIG_FAT_LFN=y -CONFIG_FAT_MAXFNAME=12 -CONFIG_FILE_STREAM=y -CONFIG_FS_FAT=y -CONFIG_FS_FATTIME=y -CONFIG_FS_NAMED_SEMAPHORES=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_I2C=y -CONFIG_I2C_RESET=y -CONFIG_IDLETHREAD_STACKSIZE=300 -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INIT_STACKSIZE=880 -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=40 -CONFIG_MM_SMALL=y -CONFIG_NAME_MAX=8 -CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=5 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_CODECS_BUFSIZE=0 -CONFIG_NSH_FILEIOSIZE=128 -CONFIG_NSH_NESTDEPTH=0 -CONFIG_POSIX_SPAWN_DEFAULT_STACKSIZE=768 -CONFIG_PREALLOC_TIMERS=2 -CONFIG_PRIORITY_INHERITANCE=y -CONFIG_PTHREAD_STACK_DEFAULT=464 -CONFIG_RAM_SIZE=20480 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SERIAL_TERMIOS=y -CONFIG_STACK_COLORATION=y -CONFIG_START_YEAR=2014 -CONFIG_STM32_ADC1=y -CONFIG_STM32_CAN1=y -CONFIG_STM32_CAN1_REMAP1=y -CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32_FLOWCONTROL_BROKEN=y -CONFIG_STM32_FORCEPOWER=y -CONFIG_STM32_I2C2=y -CONFIG_STM32_I2C_DUTY16_9=y -CONFIG_STM32_I2C_DYNTIMEO=y -CONFIG_STM32_I2C_DYNTIMEO_STARTSTOP=10 -CONFIG_STM32_I2C_DYNTIMEO_USECPERBYTE=40 -CONFIG_STM32_JTAG_FULL_ENABLE=y -CONFIG_STM32_PWR=y -CONFIG_STM32_SERIAL_DISABLE_REORDERING=y -CONFIG_STM32_SPI2=y -CONFIG_STM32_TIM1=y -CONFIG_STM32_TIM1_PARTIAL_REMAP=y -CONFIG_STM32_TIM3=y -CONFIG_STM32_TIM3_PARTIAL_REMAP=y -CONFIG_STM32_USART1=y -CONFIG_SYMTAB_ORDEREDBYNAME=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=12 -CONFIG_USART1_RXBUFSIZE=32 -CONFIG_USART1_SERIAL_CONSOLE=y -CONFIG_USART1_TXBUFSIZE=32 diff --git a/boards/arm/stm32/olimexino-stm32/configs/composite/defconfig b/boards/arm/stm32/olimexino-stm32/configs/composite/defconfig deleted file mode 100644 index ce360b21b9464..0000000000000 --- a/boards/arm/stm32/olimexino-stm32/configs/composite/defconfig +++ /dev/null @@ -1,132 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_DISABLE_OS_API is not set -# CONFIG_DISABLE_PSEUDOFS_OPERATIONS is not set -# CONFIG_MMCSD_HAVE_CARDDETECT is not set -# CONFIG_NSH_DISABLEBG is not set -# CONFIG_NSH_DISABLESCRIPT is not set -# CONFIG_NSH_DISABLE_CMP is not set -# CONFIG_NSH_DISABLE_DF is not set -# CONFIG_NSH_DISABLE_EXEC is not set -# CONFIG_NSH_DISABLE_EXIT is not set -# CONFIG_NSH_DISABLE_GET is not set -# CONFIG_NSH_DISABLE_HEXDUMP is not set -# CONFIG_NSH_DISABLE_IFCONFIG is not set -# CONFIG_NSH_DISABLE_ITEF is not set -# CONFIG_NSH_DISABLE_LOOPS is not set -# CONFIG_NSH_DISABLE_LOSETUP is not set -# CONFIG_NSH_DISABLE_MKRD is not set -# CONFIG_NSH_DISABLE_PS is not set -# CONFIG_NSH_DISABLE_PUT is not set -# CONFIG_NSH_DISABLE_SEMICOLON is not set -# CONFIG_NSH_DISABLE_WGET is not set -# CONFIG_NSH_DISABLE_XD is not set -# CONFIG_SPI_CALLBACK is not set -CONFIG_ANALOG=y -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="olimexino-stm32" -CONFIG_ARCH_BOARD_OLIMEXINO_STM32=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F103RB=y -CONFIG_ARCH_HIPRI_INTERRUPT=y -CONFIG_ARCH_INTERRUPTSTACK=340 -CONFIG_ARCH_IRQBUTTONS=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=5483 -CONFIG_BUILTIN=y -CONFIG_CDCACM=y -CONFIG_CDCACM_COMPOSITE=y -CONFIG_CDCACM_NRDREQS=2 -CONFIG_CDCACM_NWRREQS=2 -CONFIG_CDCACM_RXBUFSIZE=96 -CONFIG_CDCACM_TXBUFSIZE=96 -CONFIG_COMPOSITE_IAD=y -CONFIG_COMPOSITE_PRODUCTID=0x2022 -CONFIG_COMPOSITE_PRODUCTSTR="Composite Device" -CONFIG_COMPOSITE_VENDORID=0x03eb -CONFIG_DEBUG_FULLOPT=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_DEFAULT_SMALL=y -CONFIG_EXAMPLES_HELLOXX=y -CONFIG_FAT_LCNAMES=y -CONFIG_FAT_LFN=y -CONFIG_FAT_MAXFNAME=12 -CONFIG_FILE_STREAM=y -CONFIG_FS_FAT=y -CONFIG_FS_FATTIME=y -CONFIG_FS_NAMED_SEMAPHORES=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_IDLETHREAD_STACKSIZE=300 -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INIT_STACKSIZE=880 -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=40 -CONFIG_MMCSD=y -CONFIG_MM_SMALL=y -CONFIG_NAME_MAX=8 -CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=5 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_CODECS_BUFSIZE=0 -CONFIG_NSH_FILEIOSIZE=128 -CONFIG_POSIX_SPAWN_DEFAULT_STACKSIZE=768 -CONFIG_PREALLOC_TIMERS=2 -CONFIG_PRIORITY_INHERITANCE=y -CONFIG_PTHREAD_STACK_DEFAULT=464 -CONFIG_RAM_SIZE=20480 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SERIAL_TERMIOS=y -CONFIG_STACK_COLORATION=y -CONFIG_STM32_ADC1=y -CONFIG_STM32_BKP=y -CONFIG_STM32_CRC=y -CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32_DMA1=y -CONFIG_STM32_DMA2=y -CONFIG_STM32_DMACAPABLE=y -CONFIG_STM32_FLOWCONTROL_BROKEN=y -CONFIG_STM32_FORCEPOWER=y -CONFIG_STM32_I2C2=y -CONFIG_STM32_I2C_DUTY16_9=y -CONFIG_STM32_I2C_DYNTIMEO=y -CONFIG_STM32_I2C_DYNTIMEO_STARTSTOP=10 -CONFIG_STM32_I2C_DYNTIMEO_USECPERBYTE=40 -CONFIG_STM32_JTAG_FULL_ENABLE=y -CONFIG_STM32_PWR=y -CONFIG_STM32_RTC=y -CONFIG_STM32_SERIAL_DISABLE_REORDERING=y -CONFIG_STM32_SPI1=y -CONFIG_STM32_SPI2=y -CONFIG_STM32_TIM1=y -CONFIG_STM32_TIM1_PARTIAL_REMAP=y -CONFIG_STM32_TIM3=y -CONFIG_STM32_TIM3_PARTIAL_REMAP=y -CONFIG_STM32_USART1=y -CONFIG_STM32_USART2=y -CONFIG_STM32_USB=y -CONFIG_SYMTAB_ORDEREDBYNAME=y -CONFIG_SYSTEM_COMPOSITE=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=12 -CONFIG_USART1_RXBUFSIZE=32 -CONFIG_USART1_SERIAL_CONSOLE=y -CONFIG_USART1_TXBUFSIZE=32 -CONFIG_USART2_RXBUFSIZE=32 -CONFIG_USART2_TXBUFSIZE=32 -CONFIG_USBDEV_COMPOSITE=y -CONFIG_USBMSC=y -CONFIG_USBMSC_COMPOSITE=y -CONFIG_USBMSC_NRDREQS=2 -CONFIG_USBMSC_NWRREQS=2 -CONFIG_USBMSC_REMOVABLE=y -CONFIG_USBMSC_SCSI_STACKSIZE=340 -CONFIG_WATCHDOG=y diff --git a/boards/arm/stm32/olimexino-stm32/configs/nsh/defconfig b/boards/arm/stm32/olimexino-stm32/configs/nsh/defconfig deleted file mode 100644 index 7fac8d7932b9f..0000000000000 --- a/boards/arm/stm32/olimexino-stm32/configs/nsh/defconfig +++ /dev/null @@ -1,113 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_DISABLE_OS_API is not set -# CONFIG_DISABLE_PSEUDOFS_OPERATIONS is not set -# CONFIG_MMCSD_HAVE_CARDDETECT is not set -# CONFIG_NSH_DISABLEBG is not set -# CONFIG_NSH_DISABLESCRIPT is not set -# CONFIG_NSH_DISABLE_CMP is not set -# CONFIG_NSH_DISABLE_DF is not set -# CONFIG_NSH_DISABLE_EXEC is not set -# CONFIG_NSH_DISABLE_EXIT is not set -# CONFIG_NSH_DISABLE_GET is not set -# CONFIG_NSH_DISABLE_HEXDUMP is not set -# CONFIG_NSH_DISABLE_IFCONFIG is not set -# CONFIG_NSH_DISABLE_ITEF is not set -# CONFIG_NSH_DISABLE_LOOPS is not set -# CONFIG_NSH_DISABLE_LOSETUP is not set -# CONFIG_NSH_DISABLE_MKRD is not set -# CONFIG_NSH_DISABLE_PS is not set -# CONFIG_NSH_DISABLE_PUT is not set -# CONFIG_NSH_DISABLE_SEMICOLON is not set -# CONFIG_NSH_DISABLE_WGET is not set -# CONFIG_NSH_DISABLE_XD is not set -# CONFIG_SPI_CALLBACK is not set -CONFIG_ANALOG=y -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="olimexino-stm32" -CONFIG_ARCH_BOARD_OLIMEXINO_STM32=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F103RB=y -CONFIG_ARCH_HIPRI_INTERRUPT=y -CONFIG_ARCH_INTERRUPTSTACK=340 -CONFIG_ARCH_IRQBUTTONS=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=5483 -CONFIG_BUILTIN=y -CONFIG_DEBUG_FULLOPT=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_DEFAULT_SMALL=y -CONFIG_EXAMPLES_HELLOXX=y -CONFIG_FAT_LCNAMES=y -CONFIG_FAT_LFN=y -CONFIG_FAT_MAXFNAME=12 -CONFIG_FILE_STREAM=y -CONFIG_FS_FAT=y -CONFIG_FS_FATTIME=y -CONFIG_FS_NAMED_SEMAPHORES=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_IDLETHREAD_STACKSIZE=300 -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INIT_STACKSIZE=880 -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=40 -CONFIG_MMCSD=y -CONFIG_MM_SMALL=y -CONFIG_NAME_MAX=8 -CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=5 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_CODECS_BUFSIZE=0 -CONFIG_NSH_FILEIOSIZE=128 -CONFIG_POSIX_SPAWN_DEFAULT_STACKSIZE=768 -CONFIG_PREALLOC_TIMERS=2 -CONFIG_PRIORITY_INHERITANCE=y -CONFIG_PTHREAD_STACK_DEFAULT=464 -CONFIG_RAM_SIZE=20480 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SERIAL_TERMIOS=y -CONFIG_STACK_COLORATION=y -CONFIG_STM32_ADC1=y -CONFIG_STM32_BKP=y -CONFIG_STM32_CRC=y -CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32_DMA1=y -CONFIG_STM32_DMA2=y -CONFIG_STM32_DMACAPABLE=y -CONFIG_STM32_FLOWCONTROL_BROKEN=y -CONFIG_STM32_FORCEPOWER=y -CONFIG_STM32_I2C2=y -CONFIG_STM32_I2C_DUTY16_9=y -CONFIG_STM32_I2C_DYNTIMEO=y -CONFIG_STM32_I2C_DYNTIMEO_STARTSTOP=10 -CONFIG_STM32_I2C_DYNTIMEO_USECPERBYTE=40 -CONFIG_STM32_JTAG_FULL_ENABLE=y -CONFIG_STM32_PWR=y -CONFIG_STM32_RTC=y -CONFIG_STM32_SERIAL_DISABLE_REORDERING=y -CONFIG_STM32_SPI1=y -CONFIG_STM32_SPI2=y -CONFIG_STM32_TIM1=y -CONFIG_STM32_TIM1_PARTIAL_REMAP=y -CONFIG_STM32_TIM3=y -CONFIG_STM32_TIM3_PARTIAL_REMAP=y -CONFIG_STM32_USART1=y -CONFIG_STM32_USART2=y -CONFIG_SYMTAB_ORDEREDBYNAME=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=12 -CONFIG_USART1_RXBUFSIZE=32 -CONFIG_USART1_SERIAL_CONSOLE=y -CONFIG_USART1_TXBUFSIZE=32 -CONFIG_USART2_RXBUFSIZE=32 -CONFIG_USART2_TXBUFSIZE=32 -CONFIG_WATCHDOG=y diff --git a/boards/arm/stm32/olimexino-stm32/configs/smallnsh/defconfig b/boards/arm/stm32/olimexino-stm32/configs/smallnsh/defconfig deleted file mode 100644 index 9e47e5a1c4add..0000000000000 --- a/boards/arm/stm32/olimexino-stm32/configs/smallnsh/defconfig +++ /dev/null @@ -1,75 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_DISABLE_OS_API is not set -# CONFIG_DISABLE_PSEUDOFS_OPERATIONS is not set -# CONFIG_NSH_DISABLE_HEXDUMP is not set -# CONFIG_NSH_DISABLE_PS is not set -# CONFIG_NSH_DISABLE_XD is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="olimexino-stm32" -CONFIG_ARCH_BOARD_OLIMEXINO_STM32=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F103RB=y -CONFIG_ARCH_HIPRI_INTERRUPT=y -CONFIG_ARCH_INTERRUPTSTACK=340 -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=5483 -CONFIG_BUILTIN=y -CONFIG_CAN_EXTID=y -CONFIG_CAN_LOOPBACK=y -CONFIG_DEBUG_FULLOPT=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_DEFAULT_SMALL=y -CONFIG_EXAMPLES_CAN=y -CONFIG_FDCLONE_STDIO=y -CONFIG_FILE_STREAM=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_IDLETHREAD_STACKSIZE=300 -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INIT_STACKSIZE=880 -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=40 -CONFIG_MM_SMALL=y -CONFIG_NAME_MAX=8 -CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=5 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_CODECS_BUFSIZE=0 -CONFIG_NSH_FILEIOSIZE=128 -CONFIG_NSH_NESTDEPTH=0 -CONFIG_POSIX_SPAWN_DEFAULT_STACKSIZE=768 -CONFIG_PREALLOC_TIMERS=2 -CONFIG_PRIORITY_INHERITANCE=y -CONFIG_PTHREAD_STACK_DEFAULT=464 -CONFIG_RAM_SIZE=20480 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_HPWORKSTACKSIZE=758 -CONFIG_STACK_COLORATION=y -CONFIG_START_YEAR=2014 -CONFIG_STM32_CAN1=y -CONFIG_STM32_CAN1_REMAP1=y -CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32_FORCEPOWER=y -CONFIG_STM32_JTAG_FULL_ENABLE=y -CONFIG_STM32_PWR=y -CONFIG_STM32_SERIAL_DISABLE_REORDERING=y -CONFIG_STM32_SPI2=y -CONFIG_STM32_TIM1=y -CONFIG_STM32_TIM1_PARTIAL_REMAP=y -CONFIG_STM32_TIM3=y -CONFIG_STM32_TIM3_PARTIAL_REMAP=y -CONFIG_STM32_USART1=y -CONFIG_SYMTAB_ORDEREDBYNAME=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=12 -CONFIG_USART1_RXBUFSIZE=32 -CONFIG_USART1_SERIAL_CONSOLE=y -CONFIG_USART1_TXBUFSIZE=32 diff --git a/boards/arm/stm32/olimexino-stm32/configs/tiny/defconfig b/boards/arm/stm32/olimexino-stm32/configs/tiny/defconfig deleted file mode 100644 index 34a814085c57a..0000000000000 --- a/boards/arm/stm32/olimexino-stm32/configs/tiny/defconfig +++ /dev/null @@ -1,74 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_LEDS is not set -# CONFIG_DISABLE_OS_API is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="olimexino-stm32" -CONFIG_ARCH_BOARD_OLIMEXINO_STM32=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F103RB=y -CONFIG_ARCH_HIPRI_INTERRUPT=y -CONFIG_ARCH_INTERRUPTSTACK=340 -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARDCTL=y -CONFIG_BOARD_LOOPSPERMSEC=5483 -CONFIG_BUILTIN=y -CONFIG_CAN_EXTID=y -CONFIG_CAN_LOOPBACK=y -CONFIG_CONSOLE_SYSLOG=y -CONFIG_DEBUG_FULLOPT=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_DEFAULT_SMALL=y -CONFIG_DISABLE_MOUNTPOINT=y -CONFIG_EXAMPLES_CAN=y -CONFIG_FDCLONE_DISABLE=y -CONFIG_FDCLONE_STDIO=y -CONFIG_FILE_STREAM=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_IDLETHREAD_STACKSIZE=300 -CONFIG_INIT_ENTRYPOINT="can_main" -CONFIG_INIT_STACKSIZE=880 -CONFIG_INTELHEX_BINARY=y -CONFIG_MM_SMALL=y -CONFIG_NAME_MAX=8 -CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=5 -CONFIG_POSIX_SPAWN_DEFAULT_STACKSIZE=768 -CONFIG_PREALLOC_TIMERS=2 -CONFIG_PRIORITY_INHERITANCE=y -CONFIG_PTHREAD_STACK_DEFAULT=464 -CONFIG_RAM_SIZE=20480 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_HPWORKSTACKSIZE=758 -CONFIG_SCHED_LPWORK=y -CONFIG_SCHED_LPWORKSTACKSIZE=768 -CONFIG_STACK_COLORATION=y -CONFIG_START_YEAR=2014 -CONFIG_STM32_CAN1=y -CONFIG_STM32_CAN1_REMAP1=y -CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32_FLOWCONTROL_BROKEN=y -CONFIG_STM32_FORCEPOWER=y -CONFIG_STM32_JTAG_FULL_ENABLE=y -CONFIG_STM32_PWR=y -CONFIG_STM32_SERIAL_DISABLE_REORDERING=y -CONFIG_STM32_SPI2=y -CONFIG_STM32_TIM1=y -CONFIG_STM32_TIM1_PARTIAL_REMAP=y -CONFIG_STM32_TIM3=y -CONFIG_STM32_TIM3_PARTIAL_REMAP=y -CONFIG_STM32_USART1=y -CONFIG_SYMTAB_ORDEREDBYNAME=y -CONFIG_SYSTEM_READLINE=y -CONFIG_TASK_NAME_SIZE=12 -CONFIG_USART1_RXBUFSIZE=32 -CONFIG_USART1_SERIAL_CONSOLE=y -CONFIG_USART1_TXBUFSIZE=32 diff --git a/boards/arm/stm32/olimexino-stm32/include/board.h b/boards/arm/stm32/olimexino-stm32/include/board.h deleted file mode 100644 index 219e6256517b7..0000000000000 --- a/boards/arm/stm32/olimexino-stm32/include/board.h +++ /dev/null @@ -1,252 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/olimexino-stm32/include/board.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __BOARDS_ARM_STM32_OLIMEXINO_STM32_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32_OLIMEXINO_STM32_INCLUDE_BOARD_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#ifndef __ASSEMBLY__ -# include -#endif - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Clocking *****************************************************************/ - -/* HSI - 8 MHz RC factory-trimmed - * LSI - 40 KHz RC (30-60KHz, uncalibrated) - * HSE - On-board crystal frequency is 8MHz - * LSE - 32.768 kHz - */ - -#define STM32_BOARD_XTAL 8000000ul - -#define STM32_HSI_FREQUENCY 8000000ul -#define STM32_LSI_FREQUENCY 40000 -#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL -#define STM32_LSE_FREQUENCY 32768 - -/* PLL source is HSE/1, - * PLL multiplier is 9: - * PLL frequency is 8MHz (XTAL) x 9 = 72MHz - */ - -#define STM32_CFGR_PLLSRC RCC_CFGR_PLLSRC -#define STM32_CFGR_PLLXTPRE 0 -#define STM32_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx9 -#define STM32_PLL_FREQUENCY (9*STM32_BOARD_XTAL) - -/* Use the PLL and set the SYSCLK source to be the PLL */ - -#define STM32_SYSCLK_SW RCC_CFGR_SW_PLL -#define STM32_SYSCLK_SWS RCC_CFGR_SWS_PLL -#define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY - -/* AHB clock (HCLK) is SYSCLK (72MHz) */ - -#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK -#define STM32_HCLK_FREQUENCY STM32_PLL_FREQUENCY - -/* APB2 clock (PCLK2) is HCLK (72MHz) */ - -#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK -#define STM32_PCLK2_FREQUENCY STM32_HCLK_FREQUENCY - -/* APB2 timers 1 and 8 will receive PCLK2. */ - -#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) - -/* APB1 clock (PCLK1) is HCLK/2 (36MHz) */ - -#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd2 -#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/2) - -/* APB1 timers 2-7 will be twice PCLK1 */ - -#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) - -/* USB divider -- Divide PLL clock by 1.5 */ - -#define STM32_CFGR_USBPRE 0 - -/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx - * otherwise frequency is 2xAPBx. - * Note: TIM1,8 are on APB2, others on APB1 - */ - -#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM2_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM3_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM4_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM5_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM6_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM7_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY - -/* Buttons ******************************************************************/ - -#define BUTTON_BOOT0_BIT (0) -#define BUTTON_BOOT0_MASK (1< flash - - .init_section : ALIGN(4) { - _sinit = ABSOLUTE(.); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) - KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) - _einit = ABSOLUTE(.); - } > flash - - .ARM.extab : ALIGN(4) { - *(.ARM.extab*) - } > flash - - .ARM.exidx : ALIGN(4) { - __exidx_start = ABSOLUTE(.); - *(.ARM.exidx*) - __exidx_end = ABSOLUTE(.); - } > flash - - .tdata : { - _stdata = ABSOLUTE(.); - *(.tdata .tdata.* .gnu.linkonce.td.*); - _etdata = ABSOLUTE(.); - } > flash - - .tbss : { - _stbss = ABSOLUTE(.); - *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); - _etbss = ABSOLUTE(.); - } > flash - - _eronly = ABSOLUTE(.); - - .data : ALIGN(4) { - _sdata = ABSOLUTE(.); - *(.data .data.*) - *(.gnu.linkonce.d.*) - CONSTRUCTORS - . = ALIGN(4); - _edata = ABSOLUTE(.); - } > sram AT > flash - - .bss : ALIGN(4) { - _sbss = ABSOLUTE(.); - *(.bss .bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - . = ALIGN(4); - _ebss = ABSOLUTE(.); - } > sram - - /* Stabs debugging sections. */ - - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_info 0 : { *(.debug_info) } - .debug_line 0 : { *(.debug_line) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_aranges 0 : { *(.debug_aranges) } -} diff --git a/boards/arm/stm32/olimexino-stm32/scripts/ld.script.dfu b/boards/arm/stm32/olimexino-stm32/scripts/ld.script.dfu deleted file mode 100644 index 5cb7d690bfac1..0000000000000 --- a/boards/arm/stm32/olimexino-stm32/scripts/ld.script.dfu +++ /dev/null @@ -1,113 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/olimexino-stm32/scripts/ld.script.dfu - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* Don't know if this is correct. Just 256K-48K (not tested) */ -MEMORY -{ - flash (rx) : ORIGIN = 0x08003000, LENGTH = 208K - sram (rwx) : ORIGIN = 0x20000000, LENGTH = 64K -} - -OUTPUT_ARCH(arm) -EXTERN(_vectors) -ENTRY(_stext) -SECTIONS -{ - .text : { - _stext = ABSOLUTE(.); - *(.vectors) - *(.text .text.*) - *(.fixup) - *(.gnu.warning) - *(.rodata .rodata.*) - *(.gnu.linkonce.t.*) - *(.glue_7) - *(.glue_7t) - *(.got) - *(.gcc_except_table) - *(.gnu.linkonce.r.*) - _etext = ABSOLUTE(.); - } > flash - - .init_section : ALIGN(4) { - _sinit = ABSOLUTE(.); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) - KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) - _einit = ABSOLUTE(.); - } > flash - - .ARM.extab : ALIGN(4) { - *(.ARM.extab*) - } > flash - - .ARM.exidx : ALIGN(4) { - __exidx_start = ABSOLUTE(.); - *(.ARM.exidx*) - __exidx_end = ABSOLUTE(.); - } > flash - - .tdata : { - _stdata = ABSOLUTE(.); - *(.tdata .tdata.* .gnu.linkonce.td.*); - _etdata = ABSOLUTE(.); - } > flash - - .tbss : { - _stbss = ABSOLUTE(.); - *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); - _etbss = ABSOLUTE(.); - } > flash - - _eronly = ABSOLUTE(.); - - /* The STM32F103Z has 64Kb of SRAM beginning at the following address */ - - .data : ALIGN(4) { - _sdata = ABSOLUTE(.); - *(.data .data.*) - *(.gnu.linkonce.d.*) - CONSTRUCTORS - _edata = ABSOLUTE(.); - } > sram AT > flash - - .bss : ALIGN(4) { - _sbss = ABSOLUTE(.); - *(.bss .bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - _ebss = ABSOLUTE(.); - } > sram - - /* Stabs debugging sections. */ - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_info 0 : { *(.debug_info) } - .debug_line 0 : { *(.debug_line) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_aranges 0 : { *(.debug_aranges) } -} diff --git a/boards/arm/stm32/olimexino-stm32/src/CMakeLists.txt b/boards/arm/stm32/olimexino-stm32/src/CMakeLists.txt deleted file mode 100644 index 9457b7258b78a..0000000000000 --- a/boards/arm/stm32/olimexino-stm32/src/CMakeLists.txt +++ /dev/null @@ -1,47 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/olimexino-stm32/src/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -set(SRCS stm32_boot.c stm32_spi.c stm32_leds.c) - -if(CONFIG_STM32_CAN_CHARDRIVER) - list(APPEND SRCS stm32_can.c) -endif() - -if(CONFIG_USBMSC) - list(APPEND SRCS stm32_usbmsc.c) -endif() - -if(CONFIG_USBDEV_COMPOSITE) - list(APPEND SRCS stm32_composite.c) -endif() - -if(CONFIG_USBDEV) - list(APPEND SRCS stm32_usbdev.c) -endif() - -if(CONFIG_ARCH_BUTTONS) - list(APPEND SRCS stm32_buttons.c) -endif() - -target_sources(board PRIVATE ${SRCS}) - -set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/ld.script") diff --git a/boards/arm/stm32/olimexino-stm32/src/Make.defs b/boards/arm/stm32/olimexino-stm32/src/Make.defs deleted file mode 100644 index 65205d7152800..0000000000000 --- a/boards/arm/stm32/olimexino-stm32/src/Make.defs +++ /dev/null @@ -1,49 +0,0 @@ -############################################################################ -# boards/arm/stm32/olimexino-stm32/src/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/Make.defs - -CSRCS = stm32_boot.c stm32_spi.c stm32_leds.c - -ifeq ($(CONFIG_STM32_CAN_CHARDRIVER),y) -CSRCS += stm32_can.c -endif - -ifeq ($(CONFIG_USBMSC),y) -CSRCS += stm32_usbmsc.c -endif - -ifeq ($(CONFIG_USBDEV_COMPOSITE),y) -CSRCS += stm32_composite.c -endif - -ifeq ($(CONFIG_USBDEV),y) -CSRCS += stm32_usbdev.c -endif - -ifeq ($(CONFIG_ARCH_BUTTONS),y) -CSRCS += stm32_buttons.c -endif - -DEPPATH += --dep-path board -VPATH += :board -CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/olimexino-stm32/src/stm32_boot.c b/boards/arm/stm32/olimexino-stm32/src/stm32_boot.c deleted file mode 100644 index b4d93ced9dc22..0000000000000 --- a/boards/arm/stm32/olimexino-stm32/src/stm32_boot.c +++ /dev/null @@ -1,166 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/olimexino-stm32/src/stm32_boot.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include -#include -#include -#include - -#include -#include -#include -#include - -#ifdef CONFIG_USBMONITOR -# include -#endif - -#ifdef CONFIG_USBDEV -# include "stm32_usbdev.h" -#endif - -#include "stm32.h" -#include "olimexino-stm32.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: vbus_handler - ****************************************************************************/ - -#if defined(CONFIG_USBDEV) -static int vbus_handler(int irq, void *context, void *arg) -{ - return OK; -} -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_boardinitialize - * - * Description: - * All STM32 architectures must provide the following entry point. - * This entry point is called early in the initialization -- after all - * memory has been configured and mapped but before any devices have been - * initialized. - * - ****************************************************************************/ - -void stm32_boardinitialize(void) -{ -#ifdef CONFIG_ARCH_LEDS - /* Configure on-board LEDs if LED support has been selected. */ - - stm32_led_initialize(); -#endif - -#ifdef CONFIG_ARCH_BUTTONS - /* Configure on-board buttons. */ - - board_button_initialize(); -#endif - -#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || \ - defined(CONFIG_STM32_SPI3) - /* Configure SPI chip selects if 1) SP2 is not disabled, and 2) the weak - * function stm32_spidev_initialize() has been brought into the link. - */ - - if (stm32_spidev_initialize) - { - stm32_spidev_initialize(); - } -#endif - -#if defined(CONFIG_USBDEV) && defined(CONFIG_STM32_USB) - /* Initialize USB is 1) USBDEV is selected, 2) the USB controller is not - * disabled, and 3) the weak function stm32_usbinitialize() has been - * brought into the build. - */ - - stm32_usbinitialize(); -#endif -} - -/**************************************************************************** - * Name: board_late_initialize - * - * Description: - * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional - * initialization call will be performed in the boot-up sequence to a - * function called board_late_initialize(). board_late_initialize() will be - * called immediately after up_initialize() is called and just before the - * initial application is started. This additional initialization phase - * may be used, for example, to initialize board-specific device drivers. - * - ****************************************************************************/ - -#ifdef CONFIG_BOARD_LATE_INITIALIZE -void board_late_initialize(void) -{ - int ret = OK; - -#ifdef CONFIG_USBMSC -#if !defined(CONFIG_NSH_BUILTIN_APPS) && !defined(CONFIG_SYSTEM_USBMSC) - ret = board_usbmsc_initialize(0); -#endif -#endif - -#if !defined(CONFIG_NSH_BUILTIN_APPS) && defined(CONFIG_USBDEV_COMPOSITE) - ret = board_composite_initialize(0); -#endif - -#ifdef CONFIG_STM32_CAN_CHARDRIVER - /* Initialize CAN and register the CAN driver. */ - - ret = stm32_can_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_can_setup failed: %d\n", ret); - } -#endif - - UNUSED(ret); - -#if defined(CONFIG_USBDEV) - stm32_usb_set_pwr_callback(vbus_handler); -#endif -} -#endif diff --git a/boards/arm/stm32/olimexino-stm32/src/stm32_buttons.c b/boards/arm/stm32/olimexino-stm32/src/stm32_buttons.c deleted file mode 100644 index 026ef07e68ef3..0000000000000 --- a/boards/arm/stm32/olimexino-stm32/src/stm32_buttons.c +++ /dev/null @@ -1,126 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/olimexino-stm32/src/stm32_buttons.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include -#include - -#include "olimexino-stm32.h" - -#ifdef CONFIG_ARCH_BUTTONS - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Button support. - * - * Description: - * board_button_initialize() must be called to initialize button resources. - * - * After board_button_initialize() has been called, board_buttons() may be - * called to collect the state of all buttons. board_buttons() returns an - * 32-bit bit set with each bit associated with a button. - * See the BUTTON_*_BIT definitions in board.h for the meaning of each bit. - * - * board_button_irq() may be called to register an interrupt handler that - * will be called when a button is depressed or released. The ID value is - * a button enumeration value that uniquely identifies a button resource. - * See the BUTTON_* definitions in board.h for the meaning of enumeration - * value. - * - ****************************************************************************/ - -/**************************************************************************** - * Name: board_button_initialize - * - * Description: - * board_button_initialize() must be called to initialize button resources. - * After that, board_buttons() may be called to collect the current state - * of all buttons or board_button_irq() may be called to register button - * interrupt handlers. - * - ****************************************************************************/ - -uint32_t board_button_initialize(void) -{ - stm32_configgpio(BUTTON_BOOT0N); - return 1; -} - -/**************************************************************************** - * Name: board_buttons - * - * Description: - * - * After board_button_initialize() has been called, board_buttons() may be - * called to collect the state of all buttons. board_buttons() returns an - * 32-bit bit set with each bit associated with a button. - * See the BUTTON_*_BIT definitions in board.h for the meaning of each bit. - * - ****************************************************************************/ - -uint32_t board_buttons(void) -{ - return stm32_gpioread(BUTTON_BOOT0N) ? 0 : BUTTON_BOOT0_MASK; -} - -/**************************************************************************** - * Name: board_button_irq - * - * Description: - * - * board_button_irq() may be called to register an interrupt handler that - * will be called when a button is depressed or released. The ID value is - * a button enumeration value that uniquely identifies a button resource. - * See the BUTTON_* definitions in board.h for the meaning of enumeration - * value. - * - ****************************************************************************/ - -#ifdef CONFIG_ARCH_IRQBUTTONS -int board_button_irq(int id, xcpt_t irqhandler, void *arg) -{ - int ret = -EINVAL; - - /* The following should be atomic */ - - if (id == IRQBUTTON) - { - ret = stm32_gpiosetevent(BUTTON_BOOT0N, true, true, true, - irqhandler, arg); - } - - return ret; -} -#endif -#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/stm32/olimexino-stm32/src/stm32_can.c b/boards/arm/stm32/olimexino-stm32/src/stm32_can.c deleted file mode 100644 index 64164af8b235a..0000000000000 --- a/boards/arm/stm32/olimexino-stm32/src/stm32_can.c +++ /dev/null @@ -1,105 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/olimexino-stm32/src/stm32_can.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32.h" -#include "stm32_can.h" - -#include "olimexino-stm32.h" - -#ifdef CONFIG_CAN - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -/* The STM32F107VC supports CAN1 and CAN2 */ - -#if defined(CONFIG_STM32_CAN1) && defined(CONFIG_STM32_CAN2) -# warning "Both CAN1 and CAN2 are enabled. Only CAN1 is connected." -# undef CONFIG_STM32_CAN2 -#endif - -#ifdef CONFIG_STM32_CAN1 -# define CAN_PORT 1 -#else -# define CAN_PORT 2 -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_can_setup - * - * Description: - * Initialize CAN and register the CAN device - * - ****************************************************************************/ - -int stm32_can_setup(void) -{ -#if defined(CONFIG_STM32_CAN1) || defined(CONFIG_STM32_CAN2) - struct can_dev_s *can; - int ret; - - /* Call stm32_caninitialize() to get an instance of the CAN interface */ - - can = stm32_caninitialize(CAN_PORT); - if (can == NULL) - { - canerr("ERROR: Failed to get CAN interface\n"); - return -ENODEV; - } - - /* Register the CAN driver at "/dev/can0" */ - - ret = can_register("/dev/can0", can); - if (ret < 0) - { - canerr("ERROR: can_register failed: %d\n", ret); - return ret; - } - - return OK; -#else - return -ENODEV; -#endif -} - -#endif /* CONFIG_CAN */ diff --git a/boards/arm/stm32/olimexino-stm32/src/stm32_composite.c b/boards/arm/stm32/olimexino-stm32/src/stm32_composite.c deleted file mode 100644 index dbc418009f57f..0000000000000 --- a/boards/arm/stm32/olimexino-stm32/src/stm32_composite.c +++ /dev/null @@ -1,448 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/olimexino-stm32/src/stm32_composite.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include - -#include "stm32.h" -#include "olimexino-stm32.h" - -/* There is nothing to do here if SPI support is not selected. */ - -#if defined(CONFIG_BOARDCTL_USBDEVCTRL) && defined(CONFIG_USBDEV_COMPOSITE) - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* No SPI? Then no USB MSC device in composite */ - -#ifndef CONFIG_STM32_SPI -# undef CONFIG_USBMSC_COMPOSITE -#endif - -/* SLOT number(s) could depend on the board configuration */ - -#ifdef CONFIG_ARCH_BOARD_OLIMEXINO_STM32 -# undef OLIMEXINO_STM32_MMCSDSLOTNO -# define OLIMEXINO_STM32_MMCSDSLOTNO 0 -# undef OLIMEXINO_STM32_MMCSDSPIPORTNO -# define OLIMEXINO_STM32_MMCSDSPIPORTNO 2 -#else -/* Add configuration for new STM32 boards here */ - -# error "Unrecognized STM32 board" -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -#ifdef CONFIG_USBMSC_COMPOSITE -static void *g_mschandle; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_mscclassobject - * - * Description: - * If the mass storage class driver is part of composite device, then - * its instantiation and configuration is a multi-step, board-specific, - * process (See comments for usbmsc_configure below). In this case, - * board-specific logic must provide board_mscclassobject(). - * - * board_mscclassobject() is called from the composite driver. It must - * encapsulate the instantiation and configuration of the mass storage - * class and the return the mass storage device's class driver instance - * to the composite driver. - * - * Input Parameters: - * classdev - The location to return the mass storage class' device - * instance. - * - * Returned Value: - * 0 on success; a negated errno on failure - * - ****************************************************************************/ - -#ifdef CONFIG_USBMSC_COMPOSITE -static int board_mscclassobject(int minor, - struct usbdev_devinfo_s *devinfo, - struct usbdevclass_driver_s **classdev) -{ - int ret; - - DEBUGASSERT(g_mschandle == NULL); - - /* Configure the mass storage device */ - - uinfo("Configuring with NLUNS=1\n"); - ret = usbmsc_configure(1, &g_mschandle); - if (ret < 0) - { - uerr("ERROR: usbmsc_configure failed: %d\n", -ret); - return ret; - } - - uinfo("MSC handle=%p\n", g_mschandle); - - /* Bind the LUN(s) */ - - uinfo("Bind LUN=0 to /dev/mmcsd0\n"); - ret = usbmsc_bindlun(g_mschandle, "/dev/mmcsd0", 0, 0, 0, false); - if (ret < 0) - { - uerr("ERROR: usbmsc_bindlun failed for LUN 1 at /dev/mmcsd0: %d\n", - ret); - usbmsc_uninitialize(g_mschandle); - g_mschandle = NULL; - return ret; - } - - /* Get the mass storage device's class object */ - - ret = usbmsc_classobject(g_mschandle, devinfo, classdev); - if (ret < 0) - { - uerr("ERROR: usbmsc_classobject failed: %d\n", -ret); - usbmsc_uninitialize(g_mschandle); - g_mschandle = NULL; - } - - return ret; -} -#endif - -/**************************************************************************** - * Name: board_mscuninitialize - * - * Description: - * Un-initialize the USB storage class driver. This is just an - * application specific wrapper aboutn usbmsc_unitialize() that is called - * form the composite device logic. - * - * Input Parameters: - * classdev - The class driver instance previously given to the composite - * driver by board_mscclassobject(). - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef CONFIG_USBMSC_COMPOSITE -static void board_mscuninitialize(struct usbdevclass_driver_s *classdev) -{ - DEBUGASSERT(g_mschandle != NULL); - usbmsc_uninitialize(g_mschandle); - g_mschandle = NULL; -} -#endif - -/**************************************************************************** - * Name: board_composite0_connect - * - * Description: - * Connect the USB composite device on the specified USB device port for - * configuration 0. - * - * Input Parameters: - * port - The USB device port. - * - * Returned Value: - * A non-NULL handle value is returned on success. NULL is returned on - * any failure. - * - ****************************************************************************/ - -#ifdef CONFIG_USBMSC_COMPOSITE -static void *board_composite0_connect(int port) -{ - /* Here we are composing the configuration of the usb composite device. - * - * The standard is to use one CDC/ACM and one USB mass storage device. - */ - - struct composite_devdesc_s dev[2]; - int ifnobase = 0; - int strbase = COMPOSITE_NSTRIDS; - - /* Configure the CDC/ACM device */ - - /* Ask the cdcacm driver to fill in the constants we didn't - * know here. - */ - - cdcacm_get_composite_devdesc(&dev[0]); - - /* Overwrite and correct some values... */ - - /* The callback functions for the CDC/ACM class */ - - dev[0].classobject = cdcacm_classobject; - dev[0].uninitialize = cdcacm_uninitialize; - - /* Interfaces */ - - dev[0].devinfo.ifnobase = ifnobase; /* Offset to Interface-IDs */ - dev[0].minor = 0; /* The minor interface number */ - - /* Strings */ - - dev[0].devinfo.strbase = strbase; /* Offset to String Numbers */ - - /* Endpoints */ - - dev[0].devinfo.epno[CDCACM_EP_INTIN_IDX] = 1; - dev[0].devinfo.epno[CDCACM_EP_BULKIN_IDX] = 2; - dev[0].devinfo.epno[CDCACM_EP_BULKOUT_IDX] = 3; - - /* Count up the base numbers */ - - ifnobase += dev[0].devinfo.ninterfaces; - strbase += dev[0].devinfo.nstrings; - - /* Configure the mass storage device device */ - - /* Ask the usbmsc driver to fill in the constants we didn't - * know here. - */ - - usbmsc_get_composite_devdesc(&dev[1]); - - /* Overwrite and correct some values... */ - - /* The callback functions for the USBMSC class */ - - dev[1].classobject = board_mscclassobject; - dev[1].uninitialize = board_mscuninitialize; - - /* Interfaces */ - - dev[1].devinfo.ifnobase = ifnobase; /* Offset to Interface-IDs */ - dev[1].minor = 0; /* The minor interface number */ - - /* Strings */ - - dev[1].devinfo.strbase = strbase; /* Offset to String Numbers */ - - /* Endpoints */ - - dev[1].devinfo.epno[USBMSC_EP_BULKIN_IDX] = 5; - dev[1].devinfo.epno[USBMSC_EP_BULKOUT_IDX] = 4; - - /* Count up the base numbers */ - - ifnobase += dev[1].devinfo.ninterfaces; - strbase += dev[1].devinfo.nstrings; - - return composite_initialize(composite_getdevdescs(), dev, 2); -} -#endif - -/**************************************************************************** - * Name: board_composite1_connect - * - * Description: - * Connect the USB composite device on the specified USB device port for - * configuration 1. - * - * Input Parameters: - * port - The USB device port. - * - * Returned Value: - * A non-NULL handle value is returned on success. NULL is returned on - * any failure. - * - ****************************************************************************/ - -static void *board_composite1_connect(int port) -{ - /* REVISIT: This configuration currently fails. stm32_epallocpma() fails - * allocate a buffer for the 6th endpoint. Currently it supports 7x64 byte - * buffers, two required for EP0, leaving only buffers for 5 additional - * endpoints. - */ - -#if 0 - struct composite_devdesc_s dev[2]; - int strbase = COMPOSITE_NSTRIDS; - int ifnobase = 0; - int epno; - int i; - - for (i = 0, epno = 1; i < 2; i++) - { - /* Ask the cdcacm driver to fill in the constants we didn't know here */ - - cdcacm_get_composite_devdesc(&dev[i]); - - /* Overwrite and correct some values... */ - - /* The callback functions for the CDC/ACM class */ - - dev[i].classobject = cdcacm_classobject; - dev[i].uninitialize = cdcacm_uninitialize; - - dev[i].minor = i; /* The minor interface number */ - - /* Interfaces */ - - dev[i].devinfo.ifnobase = ifnobase; /* Offset to Interface-IDs */ - - /* Strings */ - - dev[i].devinfo.strbase = strbase; /* Offset to String Numbers */ - - /* Endpoints */ - - dev[i].devinfo.epno[CDCACM_EP_INTIN_IDX] = epno++; - dev[i].devinfo.epno[CDCACM_EP_BULKIN_IDX] = epno++; - dev[i].devinfo.epno[CDCACM_EP_BULKOUT_IDX] = epno++; - - ifnobase += dev[i].devinfo.ninterfaces; - strbase += dev[i].devinfo.nstrings; - } - - return composite_initialize(composite_getdevdescs(), dev, 2); -#else - return NULL; -#endif -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_composite_initialize - * - * Description: - * Perform architecture specific initialization of a composite USB device. - * - ****************************************************************************/ - -int board_composite_initialize(int port) -{ - /* If system/composite is built as an NSH command, then SD slot should - * already have been initialized. - * In this case, there is nothing further to be done here. - */ - - struct spi_dev_s *spi; - int ret; - - /* First, get an instance of the SPI interface */ - - syslog(LOG_INFO, "Initializing SPI port %d\n", - OLIMEXINO_STM32_MMCSDSPIPORTNO); - - spi = stm32_spibus_initialize(OLIMEXINO_STM32_MMCSDSPIPORTNO); - if (!spi) - { - syslog(LOG_ERR, "ERROR: Failed to initialize SPI port %d\n", - OLIMEXINO_STM32_MMCSDSPIPORTNO); - return -ENODEV; - } - - syslog(LOG_INFO, "Successfully initialized SPI port %d\n", - OLIMEXINO_STM32_MMCSDSPIPORTNO); - - /* Now bind the SPI interface to the MMC/SD driver */ - - syslog(LOG_INFO, "Bind SPI to the MMC/SD driver, minor=0 slot=%d\n", - OLIMEXINO_STM32_MMCSDSLOTNO); - - ret = mmcsd_spislotinitialize(0, OLIMEXINO_STM32_MMCSDSLOTNO, spi); - if (ret != OK) - { - syslog(LOG_ERR, - "ERROR: Failed to bind SPI port %d to MMC/SD minor=0 slot=%d %d\n", - OLIMEXINO_STM32_MMCSDSPIPORTNO, OLIMEXINO_STM32_MMCSDSLOTNO, - ret); - return ret; - } - - syslog(LOG_INFO, "Successfully bound SPI to the MMC/SD driver\n"); - - return OK; -} - -/**************************************************************************** - * Name: board_composite_connect - * - * Description: - * Connect the USB composite device on the specified USB device port using - * the specified configuration. The interpretation of the configid is - * board specific. - * - * Input Parameters: - * port - The USB device port. - * configid - The USB composite configuration - * - * Returned Value: - * A non-NULL handle value is returned on success. NULL is returned on - * any failure. - * - ****************************************************************************/ - -void *board_composite_connect(int port, int configid) -{ - if (configid == 0) - { -#ifdef CONFIG_USBMSC_COMPOSITE - return board_composite0_connect(port); -#else - return NULL; -#endif - } - else if (configid == 1) - { - return board_composite1_connect(port); - } - else - { - return NULL; - } -} - -#endif /* CONFIG_BOARDCTL_USBDEVCTRL && CONFIG_USBDEV_COMPOSITE */ diff --git a/boards/arm/stm32/olimexino-stm32/src/stm32_leds.c b/boards/arm/stm32/olimexino-stm32/src/stm32_leds.c deleted file mode 100644 index f0a2df6beffd9..0000000000000 --- a/boards/arm/stm32/olimexino-stm32/src/stm32_leds.c +++ /dev/null @@ -1,183 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/olimexino-stm32/src/stm32_leds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include "stm32.h" -#include "olimexino-stm32.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Dump GPIO registers */ - -#ifdef CONFIG_DEBUG_LEDS_INFO -# define led_dumpgpio(m) stm32_dumpgpio(GPIO_LED_GREEN, m) -#else -# define led_dumpgpio(m) -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -#ifdef CONFIG_ARCH_LEDS -static bool g_initialized = false; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_led_initialize/board_userled_initialize - ****************************************************************************/ - -#ifdef CONFIG_ARCH_LEDS -uint32_t stm32_led_initialize(void) -#else -uint32_t board_userled_initialize(void) -#endif -{ - /* Configure all LED GPIO lines */ - - led_dumpgpio("board_*led_initialize() Entry)"); - - stm32_configgpio(GPIO_LED_YELLOW); - stm32_configgpio(GPIO_LED_GREEN); - - led_dumpgpio("board_*led_initialize() Exit"); - return BOARD_NLEDS; -} - -/**************************************************************************** - * Name: board_userled - ****************************************************************************/ - -#ifndef CONFIG_ARCH_LEDS -void board_userled(int led, bool ledon) -{ - if (led == BOARD_LED_GREEN) - { - stm32_gpiowrite(GPIO_LED_GREEN, !ledon); - } - else if (led == BOARD_LED_YELLOW) - { - stm32_gpiowrite(GPIO_LED_YELLOW, !ledon); - } -} -#endif - -/**************************************************************************** - * Name: board_userled_all - ****************************************************************************/ - -#ifndef CONFIG_ARCH_LEDS -void board_userled_all(uint32_t ledset) -{ - stm32_gpiowrite(GPIO_LED_GREEN, (ledset & BOARD_LED_YELLOW_BIT) == 0); - stm32_gpiowrite(GPIO_LED_YELLOW, (ledset & BOARD_LED_YELLOW_BIT) == 0); -} -#endif - -/**************************************************************************** - * Name: board_autoled_on - ****************************************************************************/ - -#ifdef CONFIG_ARCH_LEDS -void board_autoled_on(int led) -{ - switch (led) - { - default: - case LED_STARTED: - case LED_HEAPALLOCATE: - case LED_IRQSENABLED: - stm32_gpiowrite(GPIO_LED_GREEN, false); - stm32_gpiowrite(GPIO_LED_YELLOW, false); - break; - - case LED_STACKCREATED: - stm32_gpiowrite(GPIO_LED_GREEN, true); - stm32_gpiowrite(GPIO_LED_YELLOW, false); - g_initialized = true; - break; - - case LED_INIRQ: - case LED_SIGNAL: - case LED_ASSERTION: - case LED_PANIC: - stm32_gpiowrite(GPIO_LED_YELLOW, true); - break; - - case LED_IDLE : /* IDLE */ - stm32_gpiowrite(GPIO_LED_GREEN, false); - break; - } -} -#endif - -/**************************************************************************** - * Name: board_autoled_off - ****************************************************************************/ - -#ifdef CONFIG_ARCH_LEDS -void board_autoled_off(int led) -{ - switch (led) - { - default: - case LED_STARTED: - case LED_HEAPALLOCATE: - case LED_IRQSENABLED: - case LED_STACKCREATED: - stm32_gpiowrite(GPIO_LED_GREEN, false); - - case LED_INIRQ: - case LED_SIGNAL: - case LED_ASSERTION: - case LED_PANIC: - stm32_gpiowrite(GPIO_LED_YELLOW, false); - break; - - case LED_IDLE: /* IDLE */ - stm32_gpiowrite(GPIO_LED_GREEN, g_initialized); - break; - } -} -#endif diff --git a/boards/arm/stm32/olimexino-stm32/src/stm32_spi.c b/boards/arm/stm32/olimexino-stm32/src/stm32_spi.c deleted file mode 100644 index 43053e5ccbe0d..0000000000000 --- a/boards/arm/stm32/olimexino-stm32/src/stm32_spi.c +++ /dev/null @@ -1,195 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/olimexino-stm32/src/stm32_spi.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include - -#include -#include - -#include -#include "chip.h" -#include "stm32.h" -#include "olimexino-stm32.h" - -#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || defined(CONFIG_STM32_SPI3) - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_spidev_initialize - * - * Description: - * Called to configure SPI chip select GPIO pins for the board. - * - ****************************************************************************/ - -void weak_function stm32_spidev_initialize(void) -{ - /* Setup CS */ - -#ifdef CONFIG_STM32_SPI1 - stm32_configgpio(USER_CSN); -#endif - -#ifdef CONFIG_STM32_SPI2 - stm32_configgpio(MMCSD_CSN); -#endif -} - -/**************************************************************************** - * Name: stm32_spi1/2/3select and stm32_spi1/2/3status - * - * Description: - * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status - * must be provided by board-specific logic. They are implementations of - * the select and status methods of the SPI interface defined by struct - * spi_ops_s (see include/nuttx/spi/spi.h). All other methods (including - * stm32_spibus_initialize()) are provided by common STM32 logic. - * To use this common SPI logic on your board: - * - * 1. Provide logic in stm32_boardinitialize() to configure SPI chip - * select pins. - * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() - * functions in your board-specific logic. These functions will perform - * chip selection and status operations using GPIOs in the way your - * board is configured. - * 3. Add a calls to stm32_spibus_initialize() in your low level - * application initialization logic - * 4. The handle returned by stm32_spibus_initialize() may then be used - * to bind the SPI driver to higher level logic (e.g., calling - * mmcsd_spislotinitialize(), for example, will bind the SPI driver - * to the SPI MMC/SD driver). - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_SPI1 -void stm32_spi1select(struct spi_dev_s *dev, - uint32_t devid, bool selected) -{ - spiinfo("devid: %d CS: %s\n", - (int)devid, selected ? "assert" : "de-assert"); - if (devid == SPIDEV_USER(0)) - { - stm32_gpiowrite(USER_CSN, !selected); - } -} - -uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) -{ - return 0; -} -#endif - -#ifdef CONFIG_STM32_SPI2 -void stm32_spi2select(struct spi_dev_s *dev, - uint32_t devid, bool selected) -{ - spiinfo("devid: %d CS: %s\n", - (int)devid, selected ? "assert" : "de-assert"); -#if defined(CONFIG_MMCSD) - if (devid == SPIDEV_MMCSD(0)) - { - stm32_gpiowrite(MMCSD_CSN, !selected); - } -#endif -} - -uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) -{ - /* No switch on SD card socket so assume it is here */ - - return SPI_STATUS_PRESENT; -} -#endif - -#ifdef CONFIG_STM32_SPI3 -void stm32_spi3select(struct spi_dev_s *dev, - uint32_t devid, bool selected) -{ - spiinfo("devid: %d CS: %s\n", - (int)devid, selected ? "assert" : "de-assert"); -} - -uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid) -{ - return 0; -} -#endif - -/**************************************************************************** - * Name: stm32_spi1cmddata - * - * Description: - * Set or clear the SH1101A A0 or SD1306 D/C n bit to select data (true) - * or command (false). This function must be provided by platform-specific - * logic. This is an implementation of the cmddata method of the SPI - * interface defined by struct spi_ops_s (see include/nuttx/spi/spi.h). - * - * Input Parameters: - * - * spi - SPI device that controls the bus the device that requires the CMD/ - * DATA selection. - * devid - If there are multiple devices on the bus, this selects which one - * to select cmd or data. NOTE: This design restricts, for example, - * one one SPI display per SPI bus. - * cmd - true: select command; false: select data - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef CONFIG_SPI_CMDDATA -#ifdef CONFIG_STM32_SPI1 -int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) -{ - return OK; -} -#endif - -#ifdef CONFIG_STM32_SPI2 -int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) -{ - return OK; -} -#endif - -#ifdef CONFIG_STM32_SPI3 -int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) -{ - return -ENODEV; -} -#endif -#endif /* CONFIG_SPI_CMDDATA */ - -#endif /* CONFIG_STM32_SPI1 || CONFIG_STM32_SPI2 */ diff --git a/boards/arm/stm32/olimexino-stm32/src/stm32_usbdev.c b/boards/arm/stm32/olimexino-stm32/src/stm32_usbdev.c deleted file mode 100644 index da1a423330fde..0000000000000 --- a/boards/arm/stm32/olimexino-stm32/src/stm32_usbdev.c +++ /dev/null @@ -1,121 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/olimexino-stm32/src/stm32_usbdev.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include - -#include -#include - -#include - -#include "stm32.h" -#include "olimexino-stm32.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_usb_set_pwr_callback() - * - * Description: - * Input Parameters: - * pwr_changed_handler: An interrupt handler that will be called on VBUS - * power state changes. - * - ****************************************************************************/ - -void stm32_usb_set_pwr_callback(xcpt_t pwr_changed_handler) -{ - stm32_gpiosetevent(GPIO_USB_VBUS, true, true, true, - pwr_changed_handler, NULL); -} - -/**************************************************************************** - * Name: stm32_usbinitialize - * - * Description: - * Called to setup USB-related GPIO pins. - * - ****************************************************************************/ - -void stm32_usbinitialize(void) -{ - uinfo("called\n"); - - /* USB Soft Connect Pullup */ - - stm32_configgpio(GPIO_USB_PULLUPN); -} - -/**************************************************************************** - * Name: stm32_usbpullup - * - * Description: - * If USB is supported and the board supports a pullup via GPIO (for USB - * software connect and disconnect), then the board software must provide - * stm32_pullup. - * See include/nuttx/usb/usbdev.h for additional description of this - * method. Alternatively, if no pull-up GPIO the following EXTERN can - * be redefined to be NULL. - * - ****************************************************************************/ - -int stm32_usbpullup(struct usbdev_s *dev, bool enable) -{ - usbtrace(TRACE_DEVPULLUP, (uint16_t)enable); - stm32_gpiowrite(GPIO_USB_PULLUPN, !enable); - return OK; -} - -/**************************************************************************** - * Name: stm32_usbsuspend - * - * Description: - * Board logic must provide the stm32_usbsuspend logic if the USBDEV - * driver is used. This function is called whenever the USB enters or - * leaves suspend mode. This is an opportunity for the board logic to - * shutdown clocks, power, etc. while the USB is suspended. - * - ****************************************************************************/ - -void stm32_usbsuspend(struct usbdev_s *dev, bool resume) -{ - uinfo("resume: %d\n", resume); -} diff --git a/boards/arm/stm32/olimexino-stm32/src/stm32_usbmsc.c b/boards/arm/stm32/olimexino-stm32/src/stm32_usbmsc.c deleted file mode 100644 index 8af999fdb60fb..0000000000000 --- a/boards/arm/stm32/olimexino-stm32/src/stm32_usbmsc.c +++ /dev/null @@ -1,126 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/olimexino-stm32/src/stm32_usbmsc.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include -#include - -#include "stm32.h" -#include "olimexino-stm32.h" - -/* There is nothing to do here if SPI support is not selected. */ - -#ifdef CONFIG_STM32_SPI - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -#ifndef CONFIG_SYSTEM_USBMSC_DEVMINOR1 -# define CONFIG_SYSTEM_USBMSC_DEVMINOR1 0 -#endif - -/* SLOT number(s) could depend on the board configuration */ - -#ifdef CONFIG_ARCH_BOARD_OLIMEXINO_STM32 -# undef OLIMEXINO_STM32_MMCSDSLOTNO -# define OLIMEXINO_STM32_MMCSDSLOTNO 0 -# undef OLIMEXINO_STM32_MMCSDSPIPORTNO -# define OLIMEXINO_STM32_MMCSDSPIPORTNO 2 -#else -/* Add configuration for new STM32 boards here */ - -# error "Unrecognized STM32 board" -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_usbmsc_initialize - * - * Description: - * Perform architecture specific initialization of the USB MSC device. - * - ****************************************************************************/ - -int board_usbmsc_initialize(int port) -{ - /* If system/usbmsc is built as an NSH command, then SD slot should - * already have been initialized. - * In this case, there is nothing further to be done here. - */ - - struct spi_dev_s *spi; - int ret; - - /* First, get an instance of the SPI interface */ - - syslog(LOG_INFO, "Initializing SPI port %d\n", - OLIMEXINO_STM32_MMCSDSPIPORTNO); - - spi = stm32_spibus_initialize(OLIMEXINO_STM32_MMCSDSPIPORTNO); - if (!spi) - { - syslog(LOG_ERR, "ERROR: Failed to initialize SPI port %d\n", - OLIMEXINO_STM32_MMCSDSPIPORTNO); - return -ENODEV; - } - - syslog(LOG_INFO, "Successfully initialized SPI port %d\n", - OLIMEXINO_STM32_MMCSDSPIPORTNO); - - /* Now bind the SPI interface to the MMC/SD driver */ - - syslog(LOG_INFO, "Bind SPI to the MMC/SD driver, minor=%d slot=%d\n", - CONFIG_SYSTEM_USBMSC_DEVMINOR1, OLIMEXINO_STM32_MMCSDSLOTNO); - - ret = mmcsd_spislotinitialize(CONFIG_SYSTEM_USBMSC_DEVMINOR1, - OLIMEXINO_STM32_MMCSDSLOTNO, spi); - if (ret < 0) - { - syslog(LOG_ERR, - "ERROR: Failed to bind SPI port %d to MMC/SD minor=%d slot=%d %d\n", - OLIMEXINO_STM32_MMCSDSPIPORTNO, CONFIG_SYSTEM_USBMSC_DEVMINOR1, - OLIMEXINO_STM32_MMCSDSLOTNO, ret); - return ret; - } - - syslog(LOG_INFO, "Successfully bound SPI to the MMC/SD driver\n"); - - return OK; -} - -#endif /* CONFIG_STM32_SPI */ diff --git a/boards/arm/stm32/omnibusf4/CMakeLists.txt b/boards/arm/stm32/omnibusf4/CMakeLists.txt deleted file mode 100644 index bf326c7306af0..0000000000000 --- a/boards/arm/stm32/omnibusf4/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/omnibusf4/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32/omnibusf4/Kconfig b/boards/arm/stm32/omnibusf4/Kconfig deleted file mode 100644 index ba690b483338e..0000000000000 --- a/boards/arm/stm32/omnibusf4/Kconfig +++ /dev/null @@ -1,30 +0,0 @@ -# -# For a description of the syntax of this configuration file, -# see the file kconfig-language.txt in the NuttX tools repository. -# - -if ARCH_BOARD_OMNIBUSF4 - -config STM32_ROMFS - bool "Automount baked-in ROMFS image" - default n - depends on FS_ROMFS - ---help--- - Select STM32_ROMFS_IMAGEFILE, STM32_ROMFS_DEV_MINOR, STM32_ROMFS_MOUNTPOINT - -config STM32_ROMFS_DEV_MINOR - int "Minor for the block device backing the data" - depends on STM32_ROMFS - default 64 - -config STM32_ROMFS_MOUNTPOINT - string "Mountpoint of the custom romfs image" - depends on STM32_ROMFS - default "/rom" - -config STM32_ROMFS_IMAGEFILE - string "ROMFS image file to include into build" - depends on STM32_ROMFS - default "../../../rom.img" - -endif diff --git a/boards/arm/stm32/omnibusf4/configs/nsh/defconfig b/boards/arm/stm32/omnibusf4/configs/nsh/defconfig deleted file mode 100644 index 3c35b9f82b28d..0000000000000 --- a/boards/arm/stm32/omnibusf4/configs/nsh/defconfig +++ /dev/null @@ -1,123 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_LEDS is not set -# CONFIG_MMCSD_HAVE_CARDDETECT is not set -# CONFIG_MMCSD_HAVE_WRITEPROTECT is not set -# CONFIG_MMCSD_MMCSUPPORT is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_SPI_CALLBACK is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="omnibusf4" -CONFIG_ARCH_BOARD_OMNIBUSF4=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F405RG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARDCTL_IOCTL=y -CONFIG_BOARDCTL_RESET=y -CONFIG_BOARDCTL_USBDEVCTRL=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_DEBUG_FEATURES=y -CONFIG_DEV_GPIO=y -CONFIG_DEV_URANDOM=y -CONFIG_DRIVERS_VIDEO=y -CONFIG_EXAMPLES_HELLO=y -CONFIG_EXAMPLES_HELLOXX=y -CONFIG_EXAMPLES_LEDS=y -CONFIG_EXAMPLES_LEDS_LEDSET=0x1 -CONFIG_EXAMPLES_LEDS_STACKSIZE=512 -CONFIG_EXAMPLES_PWM=y -CONFIG_EXAMPLES_SERIALRX=y -CONFIG_EXAMPLES_SERIALRX_PRINTHEX=y -CONFIG_FAT_LCNAMES=y -CONFIG_FAT_LFN=y -CONFIG_FS_FAT=y -CONFIG_FS_PROCFS=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_IOB_NBUFFERS=24 -CONFIG_IOB_NCHAINS=8 -CONFIG_LIBC_HOSTNAME="omnibusf4" -CONFIG_LIBM=y -CONFIG_LINE_MAX=64 -CONFIG_M25P_SPIFREQUENCY=75000000 -CONFIG_MMCSD=y -CONFIG_MM_IOB=y -CONFIG_MM_REGIONS=2 -CONFIG_MPU60X0_EXTI=y -CONFIG_MTD=y -CONFIG_MTD_M25P=y -CONFIG_MTD_SECT512=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_MMCSDSPIPORTNO=2 -CONFIG_NSH_PROMPT_STRING="omnibusf4> " -CONFIG_NSH_READLINE=y -CONFIG_PIPES=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_PWM=y -CONFIG_PWM_NCHANNELS=4 -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_LPWORK=y -CONFIG_SCHED_WAITPID=y -CONFIG_SENSORS=y -CONFIG_SENSORS_MPU60X0=y -CONFIG_START_DAY=6 -CONFIG_START_MONTH=12 -CONFIG_START_YEAR=2011 -CONFIG_STM32_CCMDATARAM=y -CONFIG_STM32_CCMEXCLUDE=y -CONFIG_STM32_DFU=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_OTGFS=y -CONFIG_STM32_PWM_MULTICHAN=y -CONFIG_STM32_PWR=y -CONFIG_STM32_SPI1=y -CONFIG_STM32_SPI2=y -CONFIG_STM32_SPI3=y -CONFIG_STM32_TIM10=y -CONFIG_STM32_TIM12=y -CONFIG_STM32_TIM1=y -CONFIG_STM32_TIM2=y -CONFIG_STM32_TIM2_CH3OUT=y -CONFIG_STM32_TIM2_CH4OUT=y -CONFIG_STM32_TIM2_CHANNEL3=y -CONFIG_STM32_TIM2_CHANNEL4=y -CONFIG_STM32_TIM2_PWM=y -CONFIG_STM32_TIM3=y -CONFIG_STM32_TIM3_CH3OUT=y -CONFIG_STM32_TIM3_CH4OUT=y -CONFIG_STM32_TIM3_CHANNEL3=y -CONFIG_STM32_TIM3_CHANNEL4=y -CONFIG_STM32_TIM3_PWM=y -CONFIG_STM32_TIM4=y -CONFIG_STM32_TIM5=y -CONFIG_STM32_TIM8=y -CONFIG_STM32_TIM9=y -CONFIG_STM32_USART1=y -CONFIG_STM32_USART3=y -CONFIG_STM32_USART6=y -CONFIG_SYSTEM_NSH=y -CONFIG_SYSTEM_ZMODEM=y -CONFIG_USART3_SERIAL_CONSOLE=y -CONFIG_USBDEV=y -CONFIG_USBDEV_BUSPOWERED=y -CONFIG_USBDEV_DMA=y -CONFIG_USBDEV_DUALSPEED=y -CONFIG_USBDEV_MAXPOWER=500 -CONFIG_USERLED=y -CONFIG_USERLED_LOWER=y -CONFIG_VIDEO_MAX7456=y -CONFIG_WQUEUE_NOTIFIER=y diff --git a/boards/arm/stm32/omnibusf4/include/board.h b/boards/arm/stm32/omnibusf4/include/board.h deleted file mode 100644 index 89ac84283a104..0000000000000 --- a/boards/arm/stm32/omnibusf4/include/board.h +++ /dev/null @@ -1,262 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/omnibusf4/include/board.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __BOARDS_ARM_STM32_OMNIBUSF4_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32_OMNIBUSF4_INCLUDE_BOARD_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#ifndef __ASSEMBLY__ -# include -# include -#endif - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Clocking *****************************************************************/ - -/* The OMNIBUSF4 board uses a single 8MHz crystal. - * - * This is the canonical configuration: - * System Clock source : PLL (HSE) - * SYSCLK(Hz) : 168000000 Determined by PLL configuration - * HCLK(Hz) : 168000000 (STM32_RCC_CFGR_HPRE) - * AHB Prescaler : 1 (STM32_RCC_CFGR_HPRE) - * APB1 Prescaler : 4 (STM32_RCC_CFGR_PPRE1) - * APB2 Prescaler : 2 (STM32_RCC_CFGR_PPRE2) - * HSE Frequency(Hz) : 8000000 (STM32_BOARD_XTAL) - * PLLM : 8 (STM32_PLLCFG_PLLM) - * PLLN : 336 (STM32_PLLCFG_PLLN) - * PLLP : 2 (STM32_PLLCFG_PLLP) - * PLLQ : 7 (STM32_PLLCFG_PLLQ) - * Main regulator - * output voltage : Scale1 mode Needed for high speed SYSCLK - * Flash Latency(WS) : 5 - * Prefetch Buffer : OFF - * Instruction cache : ON - * Data cache : ON - * Require 48MHz for - * USB OTG FS, : Enabled - * SDIO and RNG clock - */ - -/* HSI - 16 MHz RC factory-trimmed - * LSI - 32 KHz RC - * HSE - On-board crystal frequency is 8MHz - * LSE - 32.768 kHz - */ - -#define STM32_BOARD_XTAL 8000000ul - -#define STM32_HSI_FREQUENCY 16000000ul -#define STM32_LSI_FREQUENCY 32000 -#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL -#define STM32_LSE_FREQUENCY 32768 - -/* Main PLL Configuration. - * - * PLL source is HSE - * PLL_VCO = (STM32_HSE_FREQUENCY / PLLM) * PLLN - * = (8,000,000 / 8) * 336 - * = 336,000,000 - * SYSCLK = PLL_VCO / PLLP - * = 336,000,000 / 2 = 168,000,000 - * USB OTG FS, SDIO and RNG Clock - * = PLL_VCO / PLLQ - * = 48,000,000 - */ - -#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(8) -#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(336) -#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_2 -#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(7) - -#define STM32_SYSCLK_FREQUENCY 168000000ul - -/* AHB clock (HCLK) is SYSCLK (168MHz) */ - -#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ -#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY - -/* APB1 clock (PCLK1) is HCLK/4 (42MHz) */ - -#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd4 /* PCLK1 = HCLK / 4 */ -#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/4) - -/* Timers driven from APB1 will be twice PCLK1 */ - -#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) - -/* APB2 clock (PCLK2) is HCLK/2 (84MHz) */ - -#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLKd2 /* PCLK2 = HCLK / 2 */ -#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/2) - -/* Timers driven from APB2 will be twice PCLK2 */ - -#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM9_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM10_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM11_CLKIN (2*STM32_PCLK2_FREQUENCY) - -/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx - * otherwise frequency is 2xAPBx. - * Note: TIM1,8 are on APB2, others on APB1 - */ - -#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM2_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM3_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM4_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM5_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM6_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM7_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY - -/* Pin configurations *******************************************************/ - -#define BOARD_NLEDS 2 /* One literal LED, one beeper */ -#define GPIO_LED1 (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_50MHz |\ - GPIO_OUTPUT_CLEAR | GPIO_PORTB | GPIO_PIN5) -#define GPIO_BEEPER1 (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_50MHz |\ - GPIO_OUTPUT_CLEAR | GPIO_PORTB|GPIO_PIN4) - -/* USART1: */ - -#if 0 -#define INVERTER_PIN_USART1 PC0 /* DYS F4 Pro, Omnibus F4 AIO 1st Gen only */ -#endif -#define GPIO_USART1_RX (GPIO_USART1_RX_1|GPIO_SPEED_100MHz) /* PA10 */ -#define GPIO_USART1_TX (GPIO_USART1_TX_1|GPIO_SPEED_100MHz) /* PA9 */ - -/* USART2: - * - * TODO: Do OMNIBUSF4 targets use USART2? - */ - -/* USART3: */ - -#define GPIO_USART3_TX (GPIO_USART3_TX_1|GPIO_SPEED_100MHz) /* PB10 */ -#define GPIO_USART3_RX (GPIO_USART3_RX_1|GPIO_SPEED_100MHz) /* PB11 */ - -/* USART4: */ - -/* USART6: */ - -#if 0 -#define INVERTER_PIN_UART6 PC8 /* Omnibus F4 V3 and later, EXUAVF4PRO */ -#endif -#define GPIO_USART6_RX (GPIO_USART6_RX_1|GPIO_SPEED_100MHz) /* PC7 */ -#define GPIO_USART6_TX (GPIO_USART6_TX_1|GPIO_SPEED_100MHz) /* PC6 */ - -/* PWM - motor outputs, etc. are on these pins: */ - -#define GPIO_TIM3_CH3OUT (GPIO_TIM3_CH3OUT_1|GPIO_SPEED_50MHz) /* S1_OUT PB0 */ -#define GPIO_TIM3_CH4OUT (GPIO_TIM3_CH4OUT_1|GPIO_SPEED_50MHz) /* S2_OUT PB1 */ -#define GPIO_TIM2_CH4OUT (GPIO_TIM2_CH4OUT_1|GPIO_SPEED_50MHz) /* S3_OUT PA3 */ -#define GPIO_TIM2_CH3OUT (GPIO_TIM3_CH3OUT_1|GPIO_SPEED_50MHz) /* S4_OUT PA2 */ - -/* SPI1 : - * - * MPU6000 6-axis motion sensor (accelerometer + gyroscope), or - * MPU6500 6-Axis MEMS MotionTracking Device with DMP - * - * MPU6000 interrupts - * #define USE_GYRO_EXTI - * #define GYRO_1_EXTI_PIN PC4 - * #define USE_MPU_DATA_READY_SIGNAL - * - * #define GYRO_1_ALIGN CW270_DEG - * #define ACC_1_ALIGN CW270_DEG - */ - -#define GPIO_SPI1_MISO (GPIO_SPI1_MISO_1|GPIO_SPEED_50MHz) /* PA6 */ -#define GPIO_SPI1_MOSI (GPIO_SPI1_MOSI_1|GPIO_SPEED_50MHz) /* PA7 */ -#define GPIO_SPI1_SCK (GPIO_SPI1_SCK_1|GPIO_SPEED_50MHz) /* PA5 */ -#if 0 -#define GPIO_SPI1_NSS (GPIO_SPI1_NSS_2|GPIO_SPEED_50MHz) /* PA4 */ -#endif -#define DMACHAN_SPI1_RX DMAMAP_SPI1_RX_1 /* 2:0:3 */ -#define DMACHAN_SPI1_TX DMAMAP_SPI1_TX_1 /* 2:3:3 */ - -/* SPI2 : - * - * Used for MMC/SD on OMNIBUSF4SD. - */ - -#define GPIO_SPI2_MISO (GPIO_SPI2_MISO_1|GPIO_SPEED_50MHz) /* PB14 */ -#define GPIO_SPI2_MOSI (GPIO_SPI2_MOSI_1|GPIO_SPEED_50MHz) /* PB15 */ -#define GPIO_SPI2_NSS (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_50MHz | \ - GPIO_OUTPUT_SET | GPIO_PORTB | GPIO_PIN12) -#define GPIO_SPI2_SCK (GPIO_SPI2_SCK_2|GPIO_SPEED_50MHz) /* PB13 */ -#define DMACHAN_SPI2_RX DMAMAP_SPI2_RX /* 1:3:0 */ -#define DMACHAN_SPI2_TX DMAMAP_SPI2_TX /* 1:4:0 */ - -#define GPIO_MMCSD_NSS GPIO_SPI2_NSS -#define GPIO_MMCSD_NCD (GPIO_INPUT | GPIO_FLOAT | GPIO_EXTI | \ - GPIO_PORTB | GPIO_PIN7) /* PB7 SD_DET */ - -/* SPI3 : - * - * OMNIBUSF4SD targets use PA15 for NSS; others use PB4 - * (? BF code says "PB3"). - * define GPIO_SPI3_NSS GPIO_SPI3_NSS_2 PB4 - * - * Barometer and/or MAX7456, depending on the target. - * (OMNIBUSF4BASE targets appear to have a cyrf6936 device.) - */ - -#define GPIO_SPI3_MISO (GPIO_SPI3_MISO_2|GPIO_SPEED_50MHz) /* PC11 */ -#define GPIO_SPI3_MOSI (GPIO_SPI3_MOSI_2|GPIO_SPEED_50MHz) /* PC12 */ -#define GPIO_SPI3_NSS (GPIO_SPI3_NSS_1|GPIO_SPEED_50MHz) /* PA15 */ /* TODO: doesn't work like a chip select */ -#define GPIO_SPI3_SCK (GPIO_SPI3_SCK_2|GPIO_SPEED_50MHz) /* PC10 */ - -#if 0 -/* I2C : */ - -#define GPIO_I2C1_SCL (GPIO_I2C1_SCL_1|GPIO_SPEED_50MHz) -#define GPIO_I2C1_SDA (GPIO_I2C1_SDA_2|GPIO_SPEED_50MHz) -#endif - -/* USB OTG FS */ - -#define GPIO_OTGFS_DM (GPIO_OTGFS_DM_0|GPIO_SPEED_100MHz) -#define GPIO_OTGFS_DP (GPIO_OTGFS_DP_0|GPIO_SPEED_100MHz) -#define GPIO_OTGFS_ID (GPIO_OTGFS_ID_0|GPIO_SPEED_100MHz) -#define GPIO_OTGFS_SOF (GPIO_OTGFS_SOF_0|GPIO_SPEED_100MHz) - -#endif /* __BOARDS_ARM_STM32_OMNIBUSF4_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32/omnibusf4/kernel/Makefile b/boards/arm/stm32/omnibusf4/kernel/Makefile deleted file mode 100644 index 75b08bc56a65b..0000000000000 --- a/boards/arm/stm32/omnibusf4/kernel/Makefile +++ /dev/null @@ -1,94 +0,0 @@ -############################################################################ -# boards/arm/stm32/omnibusf4/kernel/Makefile -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/Make.defs - -# The entry point name (if none is provided in the .config file) - -CONFIG_INIT_ENTRYPOINT ?= user_start -ENTRYPT = $(patsubst "%",%,$(CONFIG_INIT_ENTRYPOINT)) - -# Get the paths to the libraries and the links script path in format that -# is appropriate for the host OS - -USER_LIBPATHS = $(addprefix -L,$(call CONVERT_PATH,$(addprefix $(TOPDIR)$(DELIM),$(dir $(USERLIBS))))) -USER_LDSCRIPT = -T $(call CONVERT_PATH,$(BOARD_DIR)$(DELIM)scripts$(DELIM)memory.ld) -USER_LDSCRIPT += -T $(call CONVERT_PATH,$(BOARD_DIR)$(DELIM)scripts$(DELIM)user-space.ld) -USER_HEXFILE += $(call CONVERT_PATH,$(TOPDIR)$(DELIM)nuttx_user.hex) -USER_SRECFILE += $(call CONVERT_PATH,$(TOPDIR)$(DELIM)nuttx_user.srec) -USER_BINFILE += $(call CONVERT_PATH,$(TOPDIR)$(DELIM)nuttx_user.bin) - -USER_LDFLAGS = --undefined=$(ENTRYPT) --entry=$(ENTRYPT) $(USER_LDSCRIPT) -USER_LDLIBS = $(patsubst lib%,-l%,$(basename $(notdir $(USERLIBS)))) -USER_LIBGCC = "${shell "$(CC)" $(ARCHCPUFLAGS) -print-libgcc-file-name}" - -# Source files - -CSRCS = stm32_userspace.c -COBJS = $(CSRCS:.c=$(OBJEXT)) -OBJS = $(COBJS) - -# Targets: - -all: $(TOPDIR)$(DELIM)nuttx_user.elf $(TOPDIR)$(DELIM)User.map -.PHONY: nuttx_user.elf depend clean distclean - -$(COBJS): %$(OBJEXT): %.c - $(call COMPILE, $<, $@) - -# Create the nuttx_user.elf file containing all of the user-mode code - -nuttx_user.elf: $(OBJS) - $(Q) $(LD) -o $@ $(USER_LDFLAGS) $(USER_LIBPATHS) $(OBJS) --start-group $(USER_LDLIBS) --end-group $(USER_LIBGCC) - -$(TOPDIR)$(DELIM)nuttx_user.elf: nuttx_user.elf - @echo "LD: nuttx_user.elf" - $(Q) cp -a nuttx_user.elf $(TOPDIR)$(DELIM)nuttx_user.elf -ifeq ($(CONFIG_INTELHEX_BINARY),y) - @echo "CP: nuttx_user.hex" - $(Q) $(OBJCOPY) $(OBJCOPYARGS) -O ihex nuttx_user.elf $(USER_HEXFILE) -endif -ifeq ($(CONFIG_MOTOROLA_SREC),y) - @echo "CP: nuttx_user.srec" - $(Q) $(OBJCOPY) $(OBJCOPYARGS) -O srec nuttx_user.elf $(USER_SRECFILE) -endif -ifeq ($(CONFIG_RAW_BINARY),y) - @echo "CP: nuttx_user.bin" - $(Q) $(OBJCOPY) $(OBJCOPYARGS) -O binary nuttx_user.elf $(USER_BINFILE) -endif - -$(TOPDIR)$(DELIM)User.map: nuttx_user.elf - @echo "MK: User.map" - $(Q) $(NM) nuttx_user.elf >$(TOPDIR)$(DELIM)User.map - $(Q) $(CROSSDEV)size nuttx_user.elf - -.depend: - -depend: .depend - -clean: - $(call DELFILE, nuttx_user.elf) - $(call DELFILE, "$(TOPDIR)$(DELIM)nuttx_user.*") - $(call DELFILE, "$(TOPDIR)$(DELIM)User.map") - $(call CLEAN) - -distclean: clean diff --git a/boards/arm/stm32/omnibusf4/kernel/stm32_userspace.c b/boards/arm/stm32/omnibusf4/kernel/stm32_userspace.c deleted file mode 100644 index 4f26f3b6fa7b2..0000000000000 --- a/boards/arm/stm32/omnibusf4/kernel/stm32_userspace.c +++ /dev/null @@ -1,111 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/omnibusf4/kernel/stm32_userspace.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include -#include -#include -#include - -#if defined(CONFIG_BUILD_PROTECTED) && !defined(__KERNEL__) - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -#ifndef CONFIG_NUTTX_USERSPACE -# error "CONFIG_NUTTX_USERSPACE not defined" -#endif - -#if CONFIG_NUTTX_USERSPACE != 0x08020000 -# error "CONFIG_NUTTX_USERSPACE must be 0x08020000 to match memory.ld" -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -static struct userspace_data_s g_userspace_data = -{ - .us_heap = &g_mmheap, -}; - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/* These 'addresses' of these values are setup by the linker script. */ - -extern uint8_t _stext[]; /* Start of .text */ -extern uint8_t _etext[]; /* End_1 of .text + .rodata */ -extern const uint8_t _eronly[]; /* End+1 of read only section (.text + .rodata) */ -extern uint8_t _sdata[]; /* Start of .data */ -extern uint8_t _edata[]; /* End+1 of .data */ -extern uint8_t _sbss[]; /* Start of .bss */ -extern uint8_t _ebss[]; /* End+1 of .bss */ - -const struct userspace_s userspace locate_data(".userspace") = -{ - /* General memory map */ - - .us_entrypoint = CONFIG_INIT_ENTRYPOINT, - .us_textstart = (uintptr_t)_stext, - .us_textend = (uintptr_t)_etext, - .us_datasource = (uintptr_t)_eronly, - .us_datastart = (uintptr_t)_sdata, - .us_dataend = (uintptr_t)_edata, - .us_bssstart = (uintptr_t)_sbss, - .us_bssend = (uintptr_t)_ebss, - - /* User data memory structure */ - - .us_data = &g_userspace_data, - - /* Task/thread startup routines */ - - .task_startup = nxtask_startup, - - /* Signal handler trampoline */ - - .signal_handler = up_signal_handler, - - /* User-space work queue support (declared in include/nuttx/wqueue.h) */ - -#ifdef CONFIG_LIBC_USRWORK - .work_usrstart = work_usrstart, -#endif -}; - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -#endif /* CONFIG_BUILD_PROTECTED && !__KERNEL__ */ diff --git a/boards/arm/stm32/omnibusf4/scripts/Make.defs b/boards/arm/stm32/omnibusf4/scripts/Make.defs deleted file mode 100644 index fb493131e67b4..0000000000000 --- a/boards/arm/stm32/omnibusf4/scripts/Make.defs +++ /dev/null @@ -1,41 +0,0 @@ -############################################################################ -# boards/arm/stm32/omnibusf4/scripts/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/.config -include $(TOPDIR)/tools/Config.mk -include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs - -LDSCRIPT = ld.script -ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) - -ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 - -CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) -CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) -CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -AFLAGS := $(CFLAGS) -D__ASSEMBLY__ - -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections -LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32/omnibusf4/scripts/kernel-space.ld b/boards/arm/stm32/omnibusf4/scripts/kernel-space.ld deleted file mode 100644 index 05813d380150b..0000000000000 --- a/boards/arm/stm32/omnibusf4/scripts/kernel-space.ld +++ /dev/null @@ -1,99 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/omnibusf4/scripts/kernel-space.ld - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* NOTE: This depends on the memory.ld script having been included prior to - * this script. - */ - -OUTPUT_ARCH(arm) -ENTRY(_stext) -SECTIONS -{ - .text : { - _stext = ABSOLUTE(.); - *(.vectors) - *(.text .text.*) - *(.fixup) - *(.gnu.warning) - *(.rodata .rodata.*) - *(.gnu.linkonce.t.*) - *(.glue_7) - *(.glue_7t) - *(.got) - *(.gcc_except_table) - *(.gnu.linkonce.r.*) - _etext = ABSOLUTE(.); - } > kflash - - .init_section : { - _sinit = ABSOLUTE(.); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) - KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) - _einit = ABSOLUTE(.); - } > kflash - - .ARM.extab : { - *(.ARM.extab*) - } > kflash - - __exidx_start = ABSOLUTE(.); - .ARM.exidx : { - *(.ARM.exidx*) - } > kflash - - __exidx_end = ABSOLUTE(.); - - _eronly = ABSOLUTE(.); - - .data : { - _sdata = ABSOLUTE(.); - *(.data .data.*) - *(.gnu.linkonce.d.*) - CONSTRUCTORS - . = ALIGN(4); - _edata = ABSOLUTE(.); - } > ksram AT > kflash - - .bss : { - _sbss = ABSOLUTE(.); - *(.bss .bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - . = ALIGN(8); - _ebss = ABSOLUTE(.); - } > ksram - - /* Stabs debugging sections */ - - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_info 0 : { *(.debug_info) } - .debug_line 0 : { *(.debug_line) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_aranges 0 : { *(.debug_aranges) } -} diff --git a/boards/arm/stm32/omnibusf4/scripts/ld.script b/boards/arm/stm32/omnibusf4/scripts/ld.script deleted file mode 100644 index a4e200f91e90e..0000000000000 --- a/boards/arm/stm32/omnibusf4/scripts/ld.script +++ /dev/null @@ -1,126 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/omnibusf4/scripts/ld.script - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* The STM32F407VG has 1024Kb of FLASH beginning at address 0x0800:0000 and - * 192Kb of SRAM. SRAM is split up into three blocks: - * - * 1) 112Kb of SRAM beginning at address 0x2000:0000 - * 2) 16Kb of SRAM beginning at address 0x2001:c000 - * 3) 64Kb of CCM SRAM beginning at address 0x1000:0000 - * - * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 - * where the code expects to begin execution by jumping to the entry point in - * the 0x0800:0000 address - * range. - */ - -MEMORY -{ - flash (rx) : ORIGIN = 0x08000000, LENGTH = 1024K - sram (rwx) : ORIGIN = 0x20000000, LENGTH = 112K -} - -OUTPUT_ARCH(arm) -ENTRY(_stext) -EXTERN(_vectors) -SECTIONS -{ - .text : { - _stext = ABSOLUTE(.); - *(.vectors) - *(.text .text.*) - *(.fixup) - *(.gnu.warning) - *(.rodata .rodata.*) - *(.gnu.linkonce.t.*) - *(.glue_7) - *(.glue_7t) - *(.got) - *(.gcc_except_table) - *(.gnu.linkonce.r.*) - _etext = ABSOLUTE(.); - } > flash - - .init_section : ALIGN(4) { - _sinit = ABSOLUTE(.); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) - KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) - _einit = ABSOLUTE(.); - } > flash - - .ARM.extab : ALIGN(4) { - *(.ARM.extab*) - } > flash - - .ARM.exidx : ALIGN(4) { - __exidx_start = ABSOLUTE(.); - *(.ARM.exidx*) - __exidx_end = ABSOLUTE(.); - } > flash - - .tdata : { - _stdata = ABSOLUTE(.); - *(.tdata .tdata.* .gnu.linkonce.td.*); - _etdata = ABSOLUTE(.); - } > flash - - .tbss : { - _stbss = ABSOLUTE(.); - *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); - _etbss = ABSOLUTE(.); - } > flash - - _eronly = ABSOLUTE(.); - - .data : ALIGN(4) { - _sdata = ABSOLUTE(.); - *(.data .data.*) - *(.gnu.linkonce.d.*) - CONSTRUCTORS - . = ALIGN(4); - _edata = ABSOLUTE(.); - } > sram AT > flash - - .bss : ALIGN(4) { - _sbss = ABSOLUTE(.); - *(.bss .bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - . = ALIGN(4); - _ebss = ABSOLUTE(.); - } > sram - - /* Stabs debugging sections. */ - - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_info 0 : { *(.debug_info) } - .debug_line 0 : { *(.debug_line) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_aranges 0 : { *(.debug_aranges) } -} diff --git a/boards/arm/stm32/omnibusf4/scripts/memory.ld b/boards/arm/stm32/omnibusf4/scripts/memory.ld deleted file mode 100644 index ff462c1e469af..0000000000000 --- a/boards/arm/stm32/omnibusf4/scripts/memory.ld +++ /dev/null @@ -1,87 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/omnibusf4/scripts/memory.ld - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* The STM32F407VG has 1024Kb of FLASH beginning at address 0x0800:0000 and - * 192Kb of SRAM. SRAM is split up into three blocks: - * - * 1) 112KB of SRAM beginning at address 0x2000:0000 - * 2) 16KB of SRAM beginning at address 0x2001:c000 - * 3) 64KB of CCM SRAM beginning at address 0x1000:0000 - * - * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 - * where the code expects to begin execution by jumping to the entry point in - * the 0x0800:0000 address range. - * - * For MPU support, the kernel-mode NuttX section is assumed to be 128Kb of - * FLASH and 4Kb of SRAM. That is an excessive amount for the kernel which - * should fit into 64KB and, of course, can be optimized as needed (See - * also boards/arm/stm32/omnibusf4/scripts/kernel-space.ld). Allowing the - * additional does permit addition debug instrumentation to be added to the - * kernel space without overflowing the partition. - * - * Alignment of the user space FLASH partition is also a critical factor: - * The user space FLASH partition will be spanned with a single region of - * size 2**n bytes. The alignment of the user-space region must be the same. - * As a consequence, as the user-space increases in size, the alignment - * requirement also increases. - * - * This alignment requirement means that the largest user space FLASH region - * you can have will be 512KB at it would have to be positioned at - * 0x08800000. If you change this address, don't forget to change the - * CONFIG_NUTTX_USERSPACE configuration setting to match and to modify - * the check in kernel/userspace.c. - * - * For the same reasons, the maximum size of the SRAM mapping is limited to - * 4KB. Both of these alignment limitations could be reduced by using - * multiple regions to map the FLASH/SDRAM range or perhaps with some - * clever use of subregions. - * - * A detailed memory map for the 112KB SRAM region is as follows: - * - * 0x20000 0000: Kernel .data region. Typical size: 0.1KB - * ------- ---- Kernel .bss region. Typical size: 1.8KB - * 0x20000 0800: Kernel IDLE thread stack (approximate). Size is - * determined by CONFIG_IDLETHREAD_STACKSIZE and - * adjustments for alignment. Typical is 1KB. - * ------- ---- Padded to 4KB - * 0x20000 1000: User .data region. Size is variable. - * ------- ---- User .bss region Size is variable. - * 0x20000 2000: Beginning of kernel heap. Size determined by - * CONFIG_MM_KERNEL_HEAPSIZE. - * ------- ---- Beginning of user heap. Can vary with other settings. - * 0x20001 c000: End+1 of CPU RAM - */ - -MEMORY -{ - /* 1024Kb FLASH */ - - kflash (rx) : ORIGIN = 0x08000000, LENGTH = 128K - uflash (rx) : ORIGIN = 0x08020000, LENGTH = 128K - xflash (rx) : ORIGIN = 0x08040000, LENGTH = 768K - - /* 112Kb of contiguous SRAM */ - - ksram (rwx) : ORIGIN = 0x20000000, LENGTH = 4K - usram (rwx) : ORIGIN = 0x20001000, LENGTH = 4K - xsram (rwx) : ORIGIN = 0x20002000, LENGTH = 104K -} diff --git a/boards/arm/stm32/omnibusf4/scripts/user-space.ld b/boards/arm/stm32/omnibusf4/scripts/user-space.ld deleted file mode 100644 index 83c52fe4f9f96..0000000000000 --- a/boards/arm/stm32/omnibusf4/scripts/user-space.ld +++ /dev/null @@ -1,101 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/omnibusf4/scripts/user-space.ld - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* NOTE: This depends on the memory.ld script having been included prior to - * this script. - */ - -OUTPUT_ARCH(arm) -SECTIONS -{ - .userspace : { - *(.userspace) - } > uflash - - .text : { - _stext = ABSOLUTE(.); - *(.text .text.*) - *(.fixup) - *(.gnu.warning) - *(.rodata .rodata.*) - *(.gnu.linkonce.t.*) - *(.glue_7) - *(.glue_7t) - *(.got) - *(.gcc_except_table) - *(.gnu.linkonce.r.*) - _etext = ABSOLUTE(.); - } > uflash - - .init_section : { - _sinit = ABSOLUTE(.); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) - KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) - _einit = ABSOLUTE(.); - } > uflash - - .ARM.extab : { - *(.ARM.extab*) - } > uflash - - __exidx_start = ABSOLUTE(.); - .ARM.exidx : { - *(.ARM.exidx*) - } > uflash - - __exidx_end = ABSOLUTE(.); - - _eronly = ABSOLUTE(.); - - .data : { - _sdata = ABSOLUTE(.); - *(.data .data.*) - *(.gnu.linkonce.d.*) - CONSTRUCTORS - . = ALIGN(4); - _edata = ABSOLUTE(.); - } > usram AT > uflash - - .bss : { - _sbss = ABSOLUTE(.); - *(.bss .bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - . = ALIGN(8); - _ebss = ABSOLUTE(.); - } > usram - - /* Stabs debugging sections */ - - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_info 0 : { *(.debug_info) } - .debug_line 0 : { *(.debug_line) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_aranges 0 : { *(.debug_aranges) } -} diff --git a/boards/arm/stm32/omnibusf4/src/CMakeLists.txt b/boards/arm/stm32/omnibusf4/src/CMakeLists.txt deleted file mode 100644 index 9be173575b5ee..0000000000000 --- a/boards/arm/stm32/omnibusf4/src/CMakeLists.txt +++ /dev/null @@ -1,83 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/omnibusf4/src/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -set(SRCS stm32_boot.c stm32_bringup.c stm32_spi.c stm32_userleds.c) - -if(CONFIG_SENSORS_MPU60X0) - list(APPEND SRCS stm32_mpu6000.c) -endif() - -if(CONFIG_VIDEO_MAX7456) - list(APPEND SRCS stm32_max7456.c) -endif() - -if(CONFIG_STM32_OTGFS) - list(APPEND SRCS stm32_usb.c) -endif() - -if(CONFIG_NETDEVICES) - list(APPEND SRCS stm32_netinit.c) -endif() - -if(CONFIG_PWM) - list(APPEND SRCS stm32_pwm.c) -endif() - -if(CONFIG_BOARDCTL_RESET) - list(APPEND SRCS stm32_reset.c) -endif() - -if(CONFIG_BOARDCTL_IOCTL) - list(APPEND SRCS stm32_ioctl.c) -endif() - -if(CONFIG_ARCH_CUSTOM_PMINIT) - list(APPEND SRCS stm32_pm.c) -endif() - -if(CONFIG_ARCH_IDLE_CUSTOM) - list(APPEND SRCS stm32_idle.c) -endif() - -if(CONFIG_TIMER) - list(APPEND SRCS stm32_timer.c) -endif() - -if(CONFIG_STM32_ROMFS) - list(APPEND SRCS stm32_romfs_initialize.c) -endif() - -if(CONFIG_BOARDCTL_UNIQUEID) - list(APPEND SRCS stm32_uid.c) -endif() - -if(CONFIG_USBMSC) - list(APPEND SRCS stm32_usbmsc.c) -endif() - -if(CONFIG_MMCSD) - list(APPEND SRCS stm32_mmcsd.c) -endif() - -target_sources(board PRIVATE ${SRCS}) - -set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/ld.script") diff --git a/boards/arm/stm32/omnibusf4/src/Make.defs b/boards/arm/stm32/omnibusf4/src/Make.defs deleted file mode 100644 index 6fa1d9b08b85a..0000000000000 --- a/boards/arm/stm32/omnibusf4/src/Make.defs +++ /dev/null @@ -1,84 +0,0 @@ -############################################################################ -# boards/arm/stm32/omnibusf4/src/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/Make.defs - -CSRCS = stm32_boot.c stm32_bringup.c stm32_spi.c stm32_userleds.c - -ifeq ($(CONFIG_SENSORS_MPU60X0),y) -CSRCS += stm32_mpu6000.c -endif - -ifeq ($(CONFIG_VIDEO_MAX7456),y) -CSRCS += stm32_max7456.c -endif - -ifeq ($(CONFIG_STM32_OTGFS),y) -CSRCS += stm32_usb.c -endif - -ifeq ($(CONFIG_NETDEVICES),y) -CSRCS += stm32_netinit.c -endif - -ifeq ($(CONFIG_PWM),y) -CSRCS += stm32_pwm.c -endif - -ifeq ($(CONFIG_BOARDCTL_RESET),y) -CSRCS += stm32_reset.c -endif -ifeq ($(CONFIG_BOARDCTL_IOCTL),y) -CSRCS += stm32_ioctl.c -endif - -ifeq ($(CONFIG_ARCH_CUSTOM_PMINIT),y) -CSRCS += stm32_pm.c -endif - -ifeq ($(CONFIG_ARCH_IDLE_CUSTOM),y) -CSRCS += stm32_idle.c -endif - -ifeq ($(CONFIG_TIMER),y) -CSRCS += stm32_timer.c -endif - -ifeq ($(CONFIG_STM32_ROMFS),y) -CSRCS += stm32_romfs_initialize.c -endif - -ifeq ($(CONFIG_BOARDCTL_UNIQUEID),y) -CSRCS += stm32_uid.c -endif - -ifeq ($(CONFIG_USBMSC),y) -CSRCS += stm32_usbmsc.c -endif - -ifeq ($(CONFIG_MMCSD),y) -CSRCS += stm32_mmcsd.c -endif - -DEPPATH += --dep-path board -VPATH += :board -CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/omnibusf4/src/stm32_boot.c b/boards/arm/stm32/omnibusf4/src/stm32_boot.c deleted file mode 100644 index 651df187d8134..0000000000000 --- a/boards/arm/stm32/omnibusf4/src/stm32_boot.c +++ /dev/null @@ -1,127 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/omnibusf4/src/stm32_boot.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include -#include - -#include "arm_internal.h" -#include "nvic.h" -#include "itm.h" - -#include "stm32.h" -#include "omnibusf4.h" - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_boardinitialize - * - * Description: - * All STM32 architectures must provide the following entry point. This - * entry point is called early in the initialization -- after all memory - * has been configured and mapped but before any devices have been - * initialized. - * - ****************************************************************************/ - -void stm32_boardinitialize(void) -{ -#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || defined(CONFIG_STM32_SPI3) - /* Configure SPI chip selects if 1) SPI is not disabled, and 2) the weak - * function stm32_spidev_initialize() has been brought into the link. - */ - - if (stm32_spidev_initialize) - { - stm32_spidev_initialize(); - } -#endif - -#ifdef CONFIG_STM32_OTGFS - /* Initialize USB if the - * 1) OTG FS controller is in the configuration and - * 2) disabled, and - * 3) the weak function stm32_usbinitialize() has been brought into the - * build. Presumably either CONFIG_USBDEV or CONFIG_USBHOST is also - * selected. - */ - - if (stm32_usbinitialize) - { - stm32_usbinitialize(); - } -#endif - -#ifdef HAVE_NETMONITOR - /* Configure board resources to support networking. */ - - if (stm32_netinitialize) - { - stm32_netinitialize(); - } -#endif - -#ifdef CONFIG_ARCH_LEDS - /* Configure on-board LEDs if LED support has been selected. */ - - board_autoled_initialize(); -#endif - -#ifdef HAVE_CCM_HEAP - /* Initialize CCM allocator */ - - ccm_initialize(); -#endif -} - -/**************************************************************************** - * Name: board_late_initialize - * - * Description: - * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional - * initialization call will be performed in the boot-up sequence to a - * function called board_late_initialize(). board_late_initialize() will - * be called immediately after up_initialize() is called and just before - * the initial application is started. This additional initialization - * phase may be used, for example, to initialize board-specific device - * drivers. - * - ****************************************************************************/ - -#ifdef CONFIG_BOARD_LATE_INITIALIZE -void board_late_initialize(void) -{ - /* Perform board-specific initialization */ - - stm32_bringup(); -} -#endif diff --git a/boards/arm/stm32/omnibusf4/src/stm32_bringup.c b/boards/arm/stm32/omnibusf4/src/stm32_bringup.c deleted file mode 100644 index bbda6f831f851..0000000000000 --- a/boards/arm/stm32/omnibusf4/src/stm32_bringup.c +++ /dev/null @@ -1,292 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/omnibusf4/src/stm32_bringup.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include - -#include - -#ifdef CONFIG_USBMONITOR -# include -#endif - -#include "stm32.h" -#include "stm32_romfs.h" - -#ifdef CONFIG_STM32_OTGFS -# include "stm32_usbhost.h" -#endif - -#ifdef CONFIG_USERLED -# include -#endif - -#ifdef CONFIG_RNDIS -# include -#endif - -#include "omnibusf4.h" - -/* Conditional logic in omnibusf4.h will determine if certain features - * are supported. Tests for these features need to be made after including - * omnibusf4.h. - */ - -#ifdef HAVE_RTC_DRIVER -# include -# include "stm32_rtc.h" -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_i2c_register - * - * Description: - * Register one I2C drivers for the I2C tool. - * - ****************************************************************************/ - -#if defined(CONFIG_I2C) && defined(CONFIG_SYSTEM_I2CTOOL) -static void stm32_i2c_register(int bus) -{ - struct i2c_master_s *i2c; - int ret; - - i2c = stm32_i2cbus_initialize(bus); - if (i2c == NULL) - { - syslog(LOG_ERR, "ERROR: Failed to get I2C%d interface\n", bus); - } - else - { - ret = i2c_register(i2c, bus); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: Failed to register I2C%d driver: %d\n", - bus, ret); - stm32_i2cbus_uninitialize(i2c); - } - } -} -#endif - -/**************************************************************************** - * Name: stm32_i2ctool - * - * Description: - * Register I2C drivers for the I2C tool. - * - ****************************************************************************/ - -#if defined(CONFIG_I2C) && defined(CONFIG_SYSTEM_I2CTOOL) -static void stm32_i2ctool(void) -{ - stm32_i2c_register(1); -#if 0 - stm32_i2c_register(1); - stm32_i2c_register(2); -#endif -} -#else -# define stm32_i2ctool() -#endif - -/**************************************************************************** - * Name: stm32_bringup - * - * Description: - * Perform architecture-specific initialization - * - * CONFIG_BOARD_INITIALIZE=y : - * Called from board_initialize(). - * - * CONFIG_BOARD_INITIALIZE=n && CONFIG_BOARDCTL=y : - * Called from the NSH library - * - ****************************************************************************/ - -int stm32_bringup(void) -{ -#ifdef HAVE_RTC_DRIVER - struct rtc_lowerhalf_s *lower; -#endif - int ret = OK; - -#if defined(CONFIG_I2C) && defined(CONFIG_SYSTEM_I2CTOOL) - stm32_i2ctool(); -#endif - -#ifdef HAVE_USBHOST - /* Initialize USB host operation. stm32_usbhost_initialize() starts a - * thread will monitor for USB connection and disconnection events. - */ - - ret = stm32_usbhost_initialize(); - if (ret != OK) - { - uerr("ERROR: Failed to initialize USB host: %d\n", ret); - return ret; - } -#endif - -#ifdef HAVE_USBMONITOR - /* Start the USB Monitor */ - - ret = usbmonitor_start(); - if (ret != OK) - { - uerr("ERROR: Failed to start USB monitor: %d\n", ret); - return ret; - } -#endif - -#ifdef CONFIG_MMCSD_SPI - /* Our MMC/SD port is on SPI2. */ - - ret = stm32_mmcsd_initialize(2, CONFIG_NSH_MMCSDMINOR); - if (ret < 0) - { - syslog(LOG_ERR, "Failed to initialize SD slot %d: %d\n", - CONFIG_NSH_MMCSDMINOR, ret); - } -#endif - -#ifdef CONFIG_PWM - ret = stm32_pwm_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_pwm_setup() failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_STM32_CAN_CHARDRIVER - /* Initialize CAN and register the CAN driver. */ - - ret = stm32_can_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_can_setup failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_SENSORS_MPU60X0 - /* Initialize the MPU6000 device. */ - - ret = stm32_mpu6000_initialize(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_mpu6000_initialize() failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_VIDEO_MAX7456 - /* Initialize the MAX7456 OSD device. */ - - ret = stm32_max7456_initialize(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_max7456_initialize() failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_USERLED - /* Register the LED driver */ - - ret = userled_lower_initialize("/dev/userleds"); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: userled_lower_initialize() failed: %d\n", ret); - } -#endif - -#ifdef HAVE_RTC_DRIVER - /* Instantiate the STM32 lower-half RTC driver */ - - lower = stm32_rtc_lowerhalf(); - if (!lower) - { - serr("ERROR: Failed to instantiate the RTC lower-half driver\n"); - return -ENOMEM; - } - else - { - /* Bind the lower half driver and register the combined RTC driver - * as /dev/rtc0 - */ - - ret = rtc_initialize(0, lower); - if (ret < 0) - { - serr("ERROR: Failed to bind/register the RTC driver: %d\n", ret); - return ret; - } - } -#endif - -#ifdef CONFIG_FS_PROCFS - /* Mount the procfs file system */ - - ret = nx_mount(NULL, STM32_PROCFS_MOUNTPOINT, "procfs", 0, NULL); - if (ret < 0) - { - serr("ERROR: Failed to mount procfs at %s: %d\n", - STM32_PROCFS_MOUNTPOINT, ret); - } -#endif - -#ifdef CONFIG_STM32_ROMFS - /* Initialize and mount ROMFS. */ - - ret = stm32_romfs_initialize(); - if (ret < 0) - { - serr("ERROR: Failed to mount romfs at %s: %d\n", - CONFIG_STM32_ROMFS_MOUNTPOINT, ret); - } -#endif - -#if defined(CONFIG_RNDIS) - /* Set up a MAC address for the RNDIS device. */ - - uint8_t mac[6]; - mac[0] = 0xa0; /* TODO */ - mac[1] = (CONFIG_NETINIT_MACADDR_2 >> (8 * 0)) & 0xff; - mac[2] = (CONFIG_NETINIT_MACADDR_1 >> (8 * 3)) & 0xff; - mac[3] = (CONFIG_NETINIT_MACADDR_1 >> (8 * 2)) & 0xff; - mac[4] = (CONFIG_NETINIT_MACADDR_1 >> (8 * 1)) & 0xff; - mac[5] = (CONFIG_NETINIT_MACADDR_1 >> (8 * 0)) & 0xff; - usbdev_rndis_initialize(mac); -#endif - - return ret; -} diff --git a/boards/arm/stm32/omnibusf4/src/stm32_idle.c b/boards/arm/stm32/omnibusf4/src/stm32_idle.c deleted file mode 100644 index a21bc28cff65b..0000000000000 --- a/boards/arm/stm32/omnibusf4/src/stm32_idle.c +++ /dev/null @@ -1,260 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/omnibusf4/src/stm32_idle.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include - -#include - -#include -#include -#include -#include - -#include - -#include "arm_internal.h" -#include "stm32_pm.h" -#include "stm32_rcc.h" -#include "stm32_exti.h" - -#include "omnibusf4.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -/* Does the board support an IDLE LED to indicate that the board is in the - * IDLE state? - */ - -#if defined(CONFIG_ARCH_LEDS) && defined(LED_IDLE) -# define BEGIN_IDLE() board_autoled_on(LED_IDLE) -# define END_IDLE() board_autoled_off(LED_IDLE) -#else -# define BEGIN_IDLE() -# define END_IDLE() -#endif - -/* Values for the RTC Alarm to wake up from the PM_STANDBY mode */ - -#ifndef CONFIG_PM_ALARM_SEC -# define CONFIG_PM_ALARM_SEC 3 -#endif - -#ifndef CONFIG_PM_ALARM_NSEC -# define CONFIG_PM_ALARM_NSEC 0 -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -#if 0 /* Not used */ -static void up_alarmcb(void); -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_idlepm - * - * Description: - * Perform IDLE state power management. - * - ****************************************************************************/ - -#ifdef CONFIG_PM -static void stm32_idlepm(void) -{ - static enum pm_state_e oldstate = PM_NORMAL; - enum pm_state_e newstate; - irqstate_t flags; - int ret; - - /* Decide, which power saving level can be obtained */ - - newstate = pm_checkstate(PM_IDLE_DOMAIN); - - /* Check for state changes */ - - if (newstate != oldstate) - { - sinfo("newstate= %d oldstate=%d\n", newstate, oldstate); - - flags = enter_critical_section(); - - /* Force the global state change */ - - ret = pm_changestate(PM_IDLE_DOMAIN, newstate); - if (ret < 0) - { - /* The new state change failed, revert to the preceding state */ - - pm_changestate(PM_IDLE_DOMAIN, oldstate); - - /* No state change... */ - - goto errout; - } - - /* Then perform board-specific, state-dependent logic here */ - - switch (newstate) - { - case PM_NORMAL: - { - } - break; - - case PM_IDLE: - { - } - break; - - case PM_STANDBY: - { -#ifdef CONFIG_RTC_ALARM - /* Disable RTC Alarm interrupt */ - -#warning "missing logic" - - /* Configure the RTC alarm to Auto Wake the system */ - -#warning "missing logic" - - /* The tv_nsec value must not exceed 1,000,000,000. That - * would be an invalid time. - */ - -#warning "missing logic" - - /* Set the alarm */ - -#warning "missing logic" -#endif - /* Call the STM32 stop mode */ - - stm32_pmstop(true); - - /* We have been re-awakened by some even: A button press? - * An alarm? Cancel any pending alarm and resume the normal - * operation. - */ - -#ifdef CONFIG_RTC_ALARM -#warning "missing logic" -#endif - /* Resume normal operation */ - - pm_changestate(PM_IDLE_DOMAIN, PM_NORMAL); - newstate = PM_NORMAL; - } - break; - - case PM_SLEEP: - { - /* We should not return from standby mode. The only way out - * of standby is via the reset path. - */ - - stm32_pmstandby(); - } - break; - - default: - break; - } - - /* Save the new state */ - - oldstate = newstate; - -errout: - leave_critical_section(flags); - } -} -#else -# define stm32_idlepm() -#endif - -/**************************************************************************** - * Name: up_alarmcb - * - * Description: - * RTC alarm service routine - * - ****************************************************************************/ - -#if 0 /* Not used */ -static void up_alarmcb(void) -{ - /* This alarm occurs because there wasn't any EXTI interrupt during the - * PM_STANDBY period. So just go to sleep. - */ - - pm_changestate(PM_IDLE_DOMAIN, PM_SLEEP); -} -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: up_idle - * - * Description: - * up_idle() is the logic that will be executed when their is no other - * ready-to-run task. This is processor idle time and will continue until - * some interrupt occurs to cause a context switch from the idle task. - * - * Processing in this state may be processor-specific. e.g., this is where - * power management operations might be performed. - * - ****************************************************************************/ - -void up_idle(void) -{ -#if defined(CONFIG_SUPPRESS_INTERRUPTS) || defined(CONFIG_SUPPRESS_TIMER_INTS) - /* If the system is idle and there are no timer interrupts, then process - * "fake" timer interrupts. Hopefully, something will wake up. - */ - - nxsched_process_timer(); -#else - - /* Perform IDLE mode power management */ - - BEGIN_IDLE(); - stm32_idlepm(); - END_IDLE(); -#endif -} diff --git a/boards/arm/stm32/omnibusf4/src/stm32_mmcsd.c b/boards/arm/stm32/omnibusf4/src/stm32_mmcsd.c deleted file mode 100644 index 2d6e436022ad2..0000000000000 --- a/boards/arm/stm32/omnibusf4/src/stm32_mmcsd.c +++ /dev/null @@ -1,105 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/omnibusf4/src/stm32_mmcsd.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include -#include -#include -#include -#include -#include -#include - -#include "arm_internal.h" -#include "chip.h" -#include "stm32.h" - -#include -#include "omnibusf4.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#ifdef CONFIG_DISABLE_MOUNTPOINT -# error "SD driver requires CONFIG_DISABLE_MOUNTPOINT to be disabled" -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_spi1register - * - * Description: - * Registers media change callback - ****************************************************************************/ - -int stm32_spi2register(struct spi_dev_s *dev, spi_mediachange_t callback, - void *arg) -{ - /* TODO: media change callback */ - - return OK; -} - -/**************************************************************************** - * Name: stm32_mmcsd_initialize - * - * Description: - * Initialize SPI-based SD card and card detect thread. - ****************************************************************************/ - -int stm32_mmcsd_initialize(int port, int minor) -{ - struct spi_dev_s *spi; - int rv; - - stm32_configgpio(GPIO_MMCSD_NCD); /* SD_DET */ - stm32_configgpio(GPIO_MMCSD_NSS); /* CS */ - - mcinfo("INFO: Initializing mmcsd port %d minor %d SD_DET %x\n", - port, minor, stm32_gpioread(GPIO_MMCSD_NCD)); - - spi = stm32_spibus_initialize(port); - if (spi == NULL) - { - mcerr("ERROR: Failed to initialize SPI port %d\n", port); - return -ENODEV; - } - - rv = mmcsd_spislotinitialize(minor, minor, spi); - if (rv < 0) - { - mcerr("ERROR: Failed to bind SPI port %d to SD slot %d\n", - port, minor); - return rv; - } - - spiinfo("INFO: mmcsd card has been initialized successfully\n"); - return OK; -} diff --git a/boards/arm/stm32/omnibusf4/src/stm32_netinit.c b/boards/arm/stm32/omnibusf4/src/stm32_netinit.c deleted file mode 100644 index 459c12b540ffb..0000000000000 --- a/boards/arm/stm32/omnibusf4/src/stm32_netinit.c +++ /dev/null @@ -1,41 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/omnibusf4/src/stm32_netinit.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: arm_netinitialize - ****************************************************************************/ - -#if defined(CONFIG_NET) && !defined(CONFIG_NETDEV_LATEINIT) -void arm_netinitialize(void) -{ -} -#endif diff --git a/boards/arm/stm32/omnibusf4/src/stm32_pm.c b/boards/arm/stm32/omnibusf4/src/stm32_pm.c deleted file mode 100644 index 1192f27edccda..0000000000000 --- a/boards/arm/stm32/omnibusf4/src/stm32_pm.c +++ /dev/null @@ -1,75 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/omnibusf4/src/stm32_pm.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include - -#include "arm_internal.h" -#include "stm32_pm.h" -#include "omnibusf4.h" - -#ifdef CONFIG_PM - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_pminitialize - * - * Description: - * This function is called by MCU-specific logic at power-on reset in - * order to provide one-time initialization the power management subsystem. - * This function must be called *very* early in the initialization sequence - * *before* any other device drivers are initialized (since they may - * attempt to register with the power management subsystem). - * - * Input Parameters: - * None. - * - * Returned Value: - * None. - * - ****************************************************************************/ - -void arm_pminitialize(void) -{ - /* Initialize the NuttX power management subsystem proper */ - - pm_initialize(); - -#if defined(CONFIG_ARCH_IDLE_CUSTOM) && defined(CONFIG_PM_BUTTONS) - /* Initialize the buttons to wake up the system from low power modes */ - - stm32_pm_buttons(); -#endif - - /* Initialize the LED PM */ - - stm32_led_pminitialize(); -} - -#endif /* CONFIG_PM */ diff --git a/boards/arm/stm32/omnibusf4/src/stm32_pwm.c b/boards/arm/stm32/omnibusf4/src/stm32_pwm.c deleted file mode 100644 index 110d82016bbb3..0000000000000 --- a/boards/arm/stm32/omnibusf4/src/stm32_pwm.c +++ /dev/null @@ -1,113 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/omnibusf4/src/stm32_pwm.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include - -#include -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32_pwm.h" -#include "omnibusf4.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_pwm_setup - * - * Description: - * - * Initialize PWM and register Omnibus F4's TIM2 and TIM3 PWM devices: - * - * TIM3 CH3 PB0 S1_OUT - * TIM3 CH4 PB1 S2_OUT - * TIM2 CH4 PA3 S3_OUT - * TIM2 CH3 PA2 S4_OUT - * - ****************************************************************************/ - -int stm32_pwm_setup(void) -{ - int npwm = 0; /* hardware device enumerator */ - const char *ppwm = NULL; /* pointer to PWM device name */ - struct pwm_lowerhalf_s *pwm = NULL; /* lower-half driver handle */ - - /* Initialize TIM2 and TIM3. - * - * Ihe underlying STM32 driver "knows" there are up to four channels - * available for each timer device, so we don't have to do anything - * special here to export the two channels each that we're - * interested in. The user will want to avoid the channels that - * aren't connected to anything, however, or risk death by boredom - * from resulting non-response. - */ - - for (npwm = 2; npwm <= 3; npwm++) - { - pwm = stm32_pwminitialize(npwm); - - /* If we can't get the lower-half handle, skip and keep going. */ - - if (!pwm) - { - continue; - } - - /* Translate the peripheral number to a device name. */ - - switch (npwm) - { - case 2: - ppwm = "/dev/pwm2"; - break; - - case 3: - ppwm = "/dev/pwm3"; - break; - - /* Skip missing names. */ - - default: - continue; - } - - pwm_register(ppwm, pwm); - } - - return 0; -} diff --git a/boards/arm/stm32/omnibusf4/src/stm32_reset.c b/boards/arm/stm32/omnibusf4/src/stm32_reset.c deleted file mode 100644 index 9ce6cdc4963ca..0000000000000 --- a/boards/arm/stm32/omnibusf4/src/stm32_reset.c +++ /dev/null @@ -1,56 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/omnibusf4/src/stm32_reset.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include "stm32_dfumode.h" - -#ifdef CONFIG_BOARDCTL_RESET - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -int board_reset(int mode) -{ - if (mode == 0) - { - /* Normal reset */ - - up_systemreset(); - } - else - { - /* DFU reset */ - - stm32_dfumode(); - } -} - -#endif /* CONFIG_BOARDCTL_RESET */ diff --git a/boards/arm/stm32/omnibusf4/src/stm32_romfs.h b/boards/arm/stm32/omnibusf4/src/stm32_romfs.h deleted file mode 100644 index a626fd2ac2731..0000000000000 --- a/boards/arm/stm32/omnibusf4/src/stm32_romfs.h +++ /dev/null @@ -1,77 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/omnibusf4/src/stm32_romfs.h - * - * SPDX-License-Identifier: BSD-3-Clause - * SPDX-FileCopyrightText: 2017 Tomasz Wozniak. All rights reserved. - * SPDX-FileContributor: Tomasz Wozniak - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -#ifndef __BOARDS_ARM_STM32_OMNIBUSF4_SRC_STM32_ROMFS_H -#define __BOARDS_ARM_STM32_OMNIBUSF4_SRC_STM32_ROMFS_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#ifdef CONFIG_STM32_ROMFS - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#define ROMFS_SECTOR_SIZE 64 - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_romfs_initialize - * - * Description: - * Registers built-in ROMFS image as block device and mounts it. - * - * Returned Value: - * Zero (OK) on success, a negated errno value on error. - * - * Assumptions/Limitations: - * Memory addresses [romfs_data_begin .. romfs_data_end) should contain - * ROMFS volume data, as included in the assembly snippet above (l. 84). - * - ****************************************************************************/ - -int stm32_romfs_initialize(void); - -#endif /* CONFIG_STM32_ROMFS */ - -#endif /* __BOARDS_ARM_STM32_OMNIBUSF4_SRC_STM32_ROMFS_H */ diff --git a/boards/arm/stm32/omnibusf4/src/stm32_romfs_initialize.c b/boards/arm/stm32/omnibusf4/src/stm32_romfs_initialize.c deleted file mode 100644 index 3111816d8ef3c..0000000000000 --- a/boards/arm/stm32/omnibusf4/src/stm32_romfs_initialize.c +++ /dev/null @@ -1,153 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/omnibusf4/src/stm32_romfs_initialize.c - * - * SPDX-License-Identifier: BSD-3-Clause - * SPDX-FileCopyrightText: 2017 Tomasz Wozniak. All rights reserved. - * SPDX-FileContributor: Tomasz Wozniak - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include - -#include -#include -#include "stm32_romfs.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#ifndef CONFIG_STM32_ROMFS -# error "CONFIG_STM32_ROMFS must be defined" -#else - -#ifndef CONFIG_STM32_ROMFS_IMAGEFILE -# error "CONFIG_STM32_ROMFS_IMAGEFILE must be defined" -#endif - -#ifndef CONFIG_STM32_ROMFS_DEV_MINOR -# error "CONFIG_STM32_ROMFS_DEV_MINOR must be defined" -#endif - -#ifndef CONFIG_STM32_ROMFS_MOUNTPOINT -# error "CONFIG_STM32_ROMFS_MOUNTPOINT must be defined" -#endif - -#define NSECTORS(size) (((size) + ROMFS_SECTOR_SIZE - 1)/ROMFS_SECTOR_SIZE) - -#define STR2(m) #m -#define STR(m) STR2(m) - -#define MKMOUNT_DEVNAME(m) "/dev/ram" STR(m) -#define MOUNT_DEVNAME MKMOUNT_DEVNAME(CONFIG_STM32_ROMFS_DEV_MINOR) - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -__asm__ ( - ".section .rodata, \"a\"\n" - ".balign 16\n" - ".globl romfs_data_begin\n" -"romfs_data_begin:\n" - ".incbin " STR(CONFIG_STM32_ROMFS_IMAGEFILE) "\n"\ - \ - ".balign " STR(ROMFS_SECTOR_SIZE) "\n" - ".globl romfs_data_end\n" -"romfs_data_end:\n"); - -extern const uint8_t romfs_data_begin[]; -extern const uint8_t romfs_data_end[]; - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_romfs_initialize - * - * Description: - * Registers the aboveincluded binary file as block device. - * Then mounts the block device as ROMFS filesystems. - * - * Returned Value: - * Zero (OK) on success, a negated errno value on error. - * - * Assumptions/Limitations: - * Memory addresses [romfs_data_begin .. romfs_data_end) should contain - * ROMFS volume data, as included in the assembly snippet above (l. 84). - * - ****************************************************************************/ - -int stm32_romfs_initialize(void) -{ - size_t romfs_data_len - int ret; - - /* Create a ROM disk for the /etc filesystem */ - - romfs_data_len = romfs_data_end - romfs_data_begin; - - ret = romdisk_register(CONFIG_STM32_ROMFS_DEV_MINOR, romfs_data_begin, - NSECTORS(romfs_data_len), ROMFS_SECTOR_SIZE); - if (ret < 0) - { - ferr("ERROR: romdisk_register failed: %d\n", -ret); - return ret; - } - - /* Mount the file system */ - - finfo("Mounting ROMFS filesystem at target=%s with source=%s\n", - CONFIG_STM32_ROMFS_MOUNTPOINT, MOUNT_DEVNAME); - - ret = nx_mount(MOUNT_DEVNAME, CONFIG_STM32_ROMFS_MOUNTPOINT, - "romfs", MS_RDONLY, NULL); - if (ret < 0) - { - ferr("ERROR: nx_mount(%s,%s,romfs) failed: %d\n", - MOUNT_DEVNAME, CONFIG_STM32_ROMFS_MOUNTPOINT, ret); - return ret; - } - - return OK; -} - -#endif /* CONFIG_STM32_ROMFS */ diff --git a/boards/arm/stm32/omnibusf4/src/stm32_spi.c b/boards/arm/stm32/omnibusf4/src/stm32_spi.c deleted file mode 100644 index 525a8781df7ba..0000000000000 --- a/boards/arm/stm32/omnibusf4/src/stm32_spi.c +++ /dev/null @@ -1,155 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/omnibusf4/src/stm32_spi.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include - -#include -#include - -#include "arm_internal.h" -#include "chip.h" -#include "stm32.h" - -#include "omnibusf4.h" - -#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || \ - defined(CONFIG_STM32_SPI3) - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_spidev_initialize - * - * Description: - * Called to configure SPI chip select GPIO pins for the omnibusf4 board. - * - ****************************************************************************/ - -void weak_function stm32_spidev_initialize(void) -{ -#ifdef CONFIG_STM32_SPI1 - stm32_configgpio(GPIO_CS_MPU6000); - stm32_configgpio(GPIO_EXTI_MPU6000); -#endif -#ifdef CONFIG_STM32_SPI3 - stm32_configgpio(GPIO_CS_MAX7456); -#endif -#if defined(CONFIG_MMCSD_SPI) - stm32_configgpio(GPIO_MMCSD_NCD); /* SD_DET */ - stm32_configgpio(GPIO_MMCSD_NSS); /* CS */ -#endif -} - -/**************************************************************************** - * Name: stm32_spi1/2/3select and stm32_spi1/2/3status - * - * Description: - * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status - * must be provided by board-specific logic. They are implementations of - * the select and status methods of the SPI interface defined by struct - * spi_ops_s (see include/nuttx/spi/spi.h). All other methods (including - * stm32_spibus_initialize()) are provided by common STM32 logic. To use - * this common SPI logic on your board: - * - * 1. Provide logic in stm32_boardinitialize() to configure SPI chip select - * pins. - * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() functions - * in your board-specific logic. These functions will perform chip - * selection and - * status operations using GPIOs in the way your board is configured. - * 3. Add a calls to stm32_spibus_initialize() in your low level - * application initialization logic - * 4. The handle returned by stm32_spibus_initialize() may then be used to - * bind the SPI driver to higher level logic (e.g., calling - * mmcsd_spislotinitialize(), for example, will bind the SPI driver to - * the SPI MMC/SD driver). - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_SPI1 -void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, - bool selected) -{ - spiinfo("devid: %d CS: %s\n", - (int)devid, selected ? "assert" : "de-assert"); - - /* Note: CS is active-low. */ - - stm32_gpiowrite(GPIO_CS_MPU6000, !selected); -} - -uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) -{ - return 0; -} -#endif - -#ifdef CONFIG_STM32_SPI2 -void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid, - bool selected) -{ - spiinfo("devid: %d CS: %s\n", - (int)devid, selected ? "assert" : "de-assert"); - - /* Note: NSS is active-low. */ - - stm32_gpiowrite(GPIO_MMCSD_NSS, selected ? 0 : 1); -} - -uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) -{ - /* Note: SD_DET is pulled high when there's no SD card present. */ - - return stm32_gpioread(GPIO_MMCSD_NCD) ? 0 : 1; -} -#endif - -#ifdef CONFIG_STM32_SPI3 -void stm32_spi3select(struct spi_dev_s *dev, uint32_t devid, - bool selected) -{ - spiinfo("devid: %d %s\n", - (int)devid, selected ? "assert" : "de-assert"); - - /* Note: MAX7456 CS is active-low. */ - - stm32_gpiowrite(GPIO_CS_MAX7456, selected ? 0 : 1); -} - -uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid) -{ - return 0; -} -#endif - -#endif /* CONFIG_STM32_SPI1 || CONFIG_STM32_SPI2 || CONFIG_STM32_SPI3 */ diff --git a/boards/arm/stm32/omnibusf4/src/stm32_timer.c b/boards/arm/stm32/omnibusf4/src/stm32_timer.c deleted file mode 100644 index 0d6e5b1b5d371..0000000000000 --- a/boards/arm/stm32/omnibusf4/src/stm32_timer.c +++ /dev/null @@ -1,63 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/omnibusf4/src/stm32_timer.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include - -#include - -#include "stm32_tim.h" -#include "omnibusf4.h" - -#ifdef CONFIG_TIMER - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_timer_driver_setup - * - * Description: - * Configure the timer driver. - * - * Input Parameters: - * devpath - The full path to the timer device. This should be of the - * form /dev/timer0 - * timer - The timer's number. - * - * Returned Value: - * Zero (OK) is returned on success; A negated errno value is returned - * to indicate the nature of any failure. - * - ****************************************************************************/ - -int stm32_timer_driver_setup(const char *devpath, int timer) -{ - return stm32_timer_initialize(devpath, timer); -} - -#endif diff --git a/boards/arm/stm32/omnibusf4/src/stm32_uid.c b/boards/arm/stm32/omnibusf4/src/stm32_uid.c deleted file mode 100644 index 892821fa4536f..0000000000000 --- a/boards/arm/stm32/omnibusf4/src/stm32_uid.c +++ /dev/null @@ -1,68 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/omnibusf4/src/stm32_uid.c - * - * SPDX-License-Identifier: BSD-3-Clause - * SPDX-FileCopyrightText: 2015 Marawan Ragab. All rights reserved. - * SPDX-FileContributor: Marawan Ragab - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include "stm32_uid.h" - -#include - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -#if defined(CONFIG_BOARDCTL_UNIQUEID) -int board_uniqueid(uint8_t *uniqueid) -{ - if (uniqueid == NULL) - { - return -EINVAL; - } - - stm32_get_uniqueid(uniqueid); - return OK; -} -#endif diff --git a/boards/arm/stm32/omnibusf4/src/stm32_usb.c b/boards/arm/stm32/omnibusf4/src/stm32_usb.c deleted file mode 100644 index 94f60081162c0..0000000000000 --- a/boards/arm/stm32/omnibusf4/src/stm32_usb.c +++ /dev/null @@ -1,338 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/omnibusf4/src/stm32_usb.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -#include "arm_internal.h" -#include "stm32.h" -#include "stm32_otgfs.h" -#include "omnibusf4.h" - -#ifdef CONFIG_STM32_OTGFS - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#if defined(CONFIG_USBDEV) || defined(CONFIG_USBHOST) -# define HAVE_USB 1 -#else -# warning "CONFIG_STM32_OTGFS is enabled but neither CONFIG_USBDEV nor CONFIG_USBHOST" -# undef HAVE_USB -#endif - -#ifndef CONFIG_OMNIBUSF4_USBHOST_PRIO -# define CONFIG_OMNIBUSF4_USBHOST_PRIO 100 -#endif - -#ifndef CONFIG_OMNIBUSF4_USBHOST_STACKSIZE -# define CONFIG_OMNIBUSF4_USBHOST_STACKSIZE 1024 -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -#ifdef CONFIG_USBHOST -static struct usbhost_connection_s *g_usbconn; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: usbhost_waiter - * - * Description: - * Wait for USB devices to be connected. - * - ****************************************************************************/ - -#ifdef CONFIG_USBHOST -static int usbhost_waiter(int argc, char *argv[]) -{ - struct usbhost_hubport_s *hport; - - uinfo("Running\n"); - for (; ; ) - { - /* Wait for the device to change state */ - - DEBUGVERIFY(CONN_WAIT(g_usbconn, &hport)); - uinfo("%s\n", hport->connected ? "connected" : "disconnected"); - - /* Did we just become connected? */ - - if (hport->connected) - { - /* Yes.. enumerate the newly connected device */ - - CONN_ENUMERATE(g_usbconn, hport); - } - } - - /* Keep the compiler from complaining */ - - return 0; -} -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_usbinitialize - * - * Description: - * Called from stm32_usbinitialize very early in initialization to setup - * USB-related GPIO pins for the Omnibusf4 board. - * - ****************************************************************************/ - -void stm32_usbinitialize(void) -{ - /* The OTG FS has an internal soft pull-up. - * No GPIO configuration is required - */ - - /* Configure the OTG FS VBUS sensing GPIO, - * Power On, and Overcurrent GPIOs - */ - -#ifdef CONFIG_STM32_OTGFS - stm32_configgpio(GPIO_OTGFS_VBUS); -#endif -} - -/**************************************************************************** - * Name: stm32_usbhost_initialize - * - * Description: - * Called at application startup time to initialize the USB host - * functionality. - * This function will start a thread that will monitor for device - * connection/disconnection events. - * - ****************************************************************************/ - -#ifdef CONFIG_USBHOST -int stm32_usbhost_initialize(void) -{ - int ret; - - /* First, register all of the class drivers needed to support the drivers - * that we care about: - */ - - uinfo("Register class drivers\n"); - -#ifdef CONFIG_USBHOST_HUB - /* Initialize USB hub class support */ - - ret = usbhost_hub_initialize(); - if (ret < 0) - { - uerr("ERROR: usbhost_hub_initialize failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_USBHOST_MSC - /* Register the USB mass storage class class */ - - ret = usbhost_msc_initialize(); - if (ret != OK) - { - uerr("ERROR: Failed to register the mass storage class: %d\n", ret); - } -#endif - -#ifdef CONFIG_USBHOST_CDCACM - /* Register the CDC/ACM serial class */ - - ret = usbhost_cdcacm_initialize(); - if (ret != OK) - { - uerr("ERROR: Failed to register the CDC/ACM serial class: %d\n", ret); - } -#endif - -#ifdef CONFIG_USBHOST_HIDKBD - /* Initialize the HID keyboard class */ - - ret = usbhost_kbdinit(); - if (ret != OK) - { - uerr("ERROR: Failed to register the HID keyboard class\n"); - } -#endif - -#ifdef CONFIG_USBHOST_HIDMOUSE - /* Initialize the HID mouse class */ - - ret = usbhost_mouse_init(); - if (ret != OK) - { - uerr("ERROR: Failed to register the HID mouse class\n"); - } -#endif - -#ifdef CONFIG_USBHOST_XBOXCONTROLLER - /* Initialize the HID mouse class */ - - ret = usbhost_xboxcontroller_init(); - if (ret != OK) - { - uerr("ERROR: Failed to register the XBox Controller class\n"); - } -#endif - - /* Then get an instance of the USB host interface */ - - uinfo("Initialize USB host\n"); - g_usbconn = stm32_otgfshost_initialize(0); - if (g_usbconn) - { - /* Start a thread to handle device connection. */ - - uinfo("Start usbhost_waiter\n"); - - ret = kthread_create("usbhost", CONFIG_OMNIBUSF4_USBHOST_PRIO, - CONFIG_OMNIBUSF4_USBHOST_STACKSIZE, - usbhost_waiter, NULL); - return ret < 0 ? -ENOEXEC : OK; - } - - return -ENODEV; -} -#endif - -/**************************************************************************** - * Name: stm32_usbhost_vbusdrive - * - * Description: - * Enable/disable driving of VBUS 5V output. This function must be - * provided be each platform that implements the STM32 OTG FS host - * interface - * - * "On-chip 5 V VBUS generation is not supported. For this reason, a - * charge pump or, if 5 V are available on the application board, a - * basic power switch, must be added externally to drive the 5 V VBUS - * line. The external charge pump can be driven by any GPIO output. - * When the application decides to power on VBUS using the chosen GPIO, - * it must also set the port power bit in the host port control and - * status register (PPWR bit in OTG_FS_HPRT). - * - * "The application uses this field to control power to this port, - * and the core clears this bit on an overcurrent condition." - * - * Input Parameters: - * iface - For future growth to handle multiple USB host interface. - * Should be zero. - * enable - true: enable VBUS power; false: disable VBUS power - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef CONFIG_USBHOST -void stm32_usbhost_vbusdrive(int iface, bool enable) -{ - DEBUGASSERT(iface == 0); - - if (enable) - { - /* Enable the Power Switch by driving the enable pin low */ - - stm32_gpiowrite(GPIO_OTGFS_PWRON, false); - } - else - { - /* Disable the Power Switch by driving the enable pin high */ - - stm32_gpiowrite(GPIO_OTGFS_PWRON, true); - } -} -#endif - -/**************************************************************************** - * Name: stm32_setup_overcurrent - * - * Description: - * Setup to receive an interrupt-level callback if an overcurrent - * condition is detected. - * - * Input Parameters: - * handler - New overcurrent interrupt handler - * arg - The argument provided for the interrupt handler - * - * Returned Value: - * Zero (OK) is returned on success. Otherwise, a negated errno value - * is returned to indicate the nature of the failure. - * - ****************************************************************************/ - -#ifdef CONFIG_USBHOST -int stm32_setup_overcurrent(xcpt_t handler, void *arg) -{ - return stm32_gpiosetevent(GPIO_OTGFS_OVER, true, true, true, handler, arg); -} -#endif - -/**************************************************************************** - * Name: stm32_usbsuspend - * - * Description: - * Board logic must provide the stm32_usbsuspend logic if the USBDEV - * driver is used. This function is called whenever the USB enters or - * leaves suspend mode. This is an opportunity for the board logic to - * shutdown clocks, power, etc. while the USB is suspended. - * - ****************************************************************************/ - -#ifdef CONFIG_USBDEV -void stm32_usbsuspend(struct usbdev_s *dev, bool resume) -{ - uinfo("resume: %d\n", resume); -} -#endif - -#endif /* CONFIG_STM32_OTGFS */ diff --git a/boards/arm/stm32/omnibusf4/src/stm32_usbmsc.c b/boards/arm/stm32/omnibusf4/src/stm32_usbmsc.c deleted file mode 100644 index b3c093ab6a166..0000000000000 --- a/boards/arm/stm32/omnibusf4/src/stm32_usbmsc.c +++ /dev/null @@ -1,71 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/omnibusf4/src/stm32_usbmsc.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include - -#include "stm32.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -#ifndef CONFIG_SYSTEM_USBMSC_DEVMINOR1 -# define CONFIG_SYSTEM_USBMSC_DEVMINOR1 0 -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_usbmsc_initialize - * - * Description: - * Perform architecture specific initialization of the USB MSC device. - * - ****************************************************************************/ - -int board_usbmsc_initialize(int port) -{ - /* If system/usbmsc is built as an NSH command, then SD slot should - * already have been initialized. - * In this case, there is nothing further to be done here. - */ - -#ifndef CONFIG_NSH_BUILTIN_APPS - return stm32_sdinitialize(CONFIG_SYSTEM_USBMSC_DEVMINOR1); -#else - return OK; -#endif -} diff --git a/boards/arm/stm32/omnibusf4/src/stm32_userleds.c b/boards/arm/stm32/omnibusf4/src/stm32_userleds.c deleted file mode 100644 index 2d624f27610fe..0000000000000 --- a/boards/arm/stm32/omnibusf4/src/stm32_userleds.c +++ /dev/null @@ -1,217 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/omnibusf4/src/stm32_userleds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32.h" -#include "omnibusf4.h" - -#ifndef CONFIG_ARCH_LEDS - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* This array maps an LED number to GPIO pin configuration */ - -static uint32_t g_ledcfg[BOARD_NLEDS] = -{ - GPIO_LED1, - GPIO_BEEPER1 -}; - -/**************************************************************************** - * Private Function Protototypes - ****************************************************************************/ - -/* LED Power Management */ - -#ifdef CONFIG_PM -static void led_pm_notify(struct pm_callback_s *cb, int domain, - enum pm_state_e pmstate); -static int led_pm_prepare(struct pm_callback_s *cb, int domain, - enum pm_state_e pmstate); -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -#ifdef CONFIG_PM -static struct pm_callback_s g_ledscb = -{ - .notify = led_pm_notify, - .prepare = led_pm_prepare, -}; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: led_pm_notify - * - * Description: - * Notify the driver of new power state. This callback is called after - * all drivers have had the opportunity to prepare for the new power state. - * - ****************************************************************************/ - -#ifdef CONFIG_PM -static void led_pm_notify(struct pm_callback_s *cb, int domain, - enum pm_state_e pmstate) -{ - switch (pmstate) - { - case PM_NORMAL: - { - /* Restore normal LEDs operation */ - } - break; - - case PM_IDLE: - { - /* Entering IDLE mode - Turn leds off */ - } - break; - - case PM_STANDBY: - { - /* Entering STANDBY mode - Logic for PM_STANDBY goes here */ - } - break; - - case PM_SLEEP: - { - /* Entering SLEEP mode - Logic for PM_SLEEP goes here */ - } - break; - - default: - { - /* Should not get here */ - } - break; - } -} -#endif - -/**************************************************************************** - * Name: led_pm_prepare - * - * Description: - * Request the driver to prepare for a new power state. This is a warning - * that the system is about to enter into a new power state. The driver - * should begin whatever operations that may be required to enter power - * state. The driver may abort the state change mode by returning a - * non-zero value from the callback function. - * - ****************************************************************************/ - -#ifdef CONFIG_PM -static int led_pm_prepare(struct pm_callback_s *cb, int domain, - enum pm_state_e pmstate) -{ - /* No preparation to change power modes is required by the LEDs driver. - * We always accept the state change by returning OK. - */ - - return OK; -} -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_userled_initialize - ****************************************************************************/ - -uint32_t board_userled_initialize(void) -{ - for (unsigned wled = 0; wled < BOARD_NLEDS; wled++) - { - stm32_configgpio(g_ledcfg[wled]); - } - - return BOARD_NLEDS; -} - -/**************************************************************************** - * Name: board_userled - ****************************************************************************/ - -void board_userled(int led, bool ledon) -{ - if ((unsigned)led < BOARD_NLEDS) - { - stm32_gpiowrite(g_ledcfg[led], ledon); - } -} - -/**************************************************************************** - * Name: board_userled_all - ****************************************************************************/ - -void board_userled_all(uint32_t ledset) -{ - for (unsigned wled = 0; wled < BOARD_NLEDS; wled++) - { - stm32_gpiowrite(g_ledcfg[wled], - (ledset & (1 << wled)) == 0 ? 1 : 0); - } -} - -/**************************************************************************** - * Name: stm32_led_pminitialize - ****************************************************************************/ - -#ifdef CONFIG_PM -void stm32_led_pminitialize(void) -{ - /* Register to receive power management callbacks */ - - int ret = pm_register(&g_ledscb); - if (ret != OK) - { - board_autoled_on(LED_ASSERTION); - } -} -#endif /* CONFIG_PM */ - -#endif /* !CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/photon/CMakeLists.txt b/boards/arm/stm32/photon/CMakeLists.txt deleted file mode 100644 index 2bb4205c977cb..0000000000000 --- a/boards/arm/stm32/photon/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/photon/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32/photon/configs/adb/defconfig b/boards/arm/stm32/photon/configs/adb/defconfig deleted file mode 100644 index 1cd0b1d4e0f8e..0000000000000 --- a/boards/arm/stm32/photon/configs/adb/defconfig +++ /dev/null @@ -1,70 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_LEDS is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -CONFIG_ADBD_AUTHENTICATION=y -CONFIG_ADBD_AUTH_PUBKEY=y -CONFIG_ADBD_DEVICE_ID="serialno" -CONFIG_ADBD_FILE_SERVICE=y -CONFIG_ADBD_LOGCAT_SERVICE=y -CONFIG_ADBD_SHELL_SERVICE=y -CONFIG_ADBD_USB_SERVER=y -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="photon" -CONFIG_ARCH_BOARD_PHOTON=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F205RG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_DEBUG_FEATURES=y -CONFIG_DEV_URANDOM=y -CONFIG_FS_PROCFS=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_INIT_ENTRYPOINT="adbd_main" -CONFIG_INIT_STACKSIZE=3072 -CONFIG_INTELHEX_BINARY=y -CONFIG_LIBC_EXECFUNCS=y -CONFIG_LIBUV=y -CONFIG_LINE_MAX=64 -CONFIG_MM_REGIONS=2 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PHOTON_DFU_BOOTLOADER=y -CONFIG_PHOTON_IWDG=y -CONFIG_PHOTON_WDG_THREAD=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_PSEUDOTERM=y -CONFIG_RAMLOG=y -CONFIG_RAMLOG_BUFSIZE=2048 -CONFIG_RAMLOG_SYSLOG=y -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_CHILD_STATUS=y -CONFIG_SCHED_HAVE_PARENT=y -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=6 -CONFIG_START_MONTH=12 -CONFIG_START_YEAR=2011 -CONFIG_STM32_IWDG=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_OTGHS=y -CONFIG_STM32_USART1=y -CONFIG_SYSTEM_ADBD=y -CONFIG_SYSTEM_NSH=y -CONFIG_TLS_TASK_NELEM=4 -CONFIG_USART1_SERIAL_CONSOLE=y -CONFIG_USBADB=y -CONFIG_USBDEV=y -CONFIG_USBDEV_BUSPOWERED=y diff --git a/boards/arm/stm32/photon/configs/nsh/defconfig b/boards/arm/stm32/photon/configs/nsh/defconfig deleted file mode 100644 index e0e25c7c346f3..0000000000000 --- a/boards/arm/stm32/photon/configs/nsh/defconfig +++ /dev/null @@ -1,46 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_LEDS is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="photon" -CONFIG_ARCH_BOARD_PHOTON=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F205RG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_FS_PROCFS=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_MM_REGIONS=2 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PHOTON_DFU_BOOTLOADER=y -CONFIG_PHOTON_IWDG=y -CONFIG_PHOTON_WDG_THREAD=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=6 -CONFIG_START_MONTH=12 -CONFIG_START_YEAR=2011 -CONFIG_STM32_IWDG=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_USART1=y -CONFIG_SYSTEM_NSH=y -CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/photon/configs/rgbled/defconfig b/boards/arm/stm32/photon/configs/rgbled/defconfig deleted file mode 100644 index d1096c8a84d31..0000000000000 --- a/boards/arm/stm32/photon/configs/rgbled/defconfig +++ /dev/null @@ -1,68 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_LEDS is not set -# CONFIG_DEV_CONSOLE is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="photon" -CONFIG_ARCH_BOARD_PHOTON=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F205RG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARDCTL_USBDEVCTRL=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_CDCACM=y -CONFIG_CDCACM_CONSOLE=y -CONFIG_EXAMPLES_RGBLED=y -CONFIG_FS_PROCFS=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_MM_REGIONS=2 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PHOTON_DFU_BOOTLOADER=y -CONFIG_PHOTON_IWDG=y -CONFIG_PHOTON_WDG_THREAD=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_PWM=y -CONFIG_PWM_NCHANNELS=4 -CONFIG_RAMLOG=y -CONFIG_RAMLOG_BUFSIZE=8192 -CONFIG_RAMLOG_SYSLOG=y -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RGBLED=y -CONFIG_RGBLED_INVERT=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=6 -CONFIG_START_MONTH=12 -CONFIG_START_YEAR=2011 -CONFIG_STM32_IWDG=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_OTGHS=y -CONFIG_STM32_PWM_MULTICHAN=y -CONFIG_STM32_TIM2=y -CONFIG_STM32_TIM2_CH2OUT=y -CONFIG_STM32_TIM2_CH3OUT=y -CONFIG_STM32_TIM2_CH4OUT=y -CONFIG_STM32_TIM2_CHANNEL2=y -CONFIG_STM32_TIM2_CHANNEL3=y -CONFIG_STM32_TIM2_CHANNEL4=y -CONFIG_STM32_TIM2_PWM=y -CONFIG_STM32_USART1=y -CONFIG_SYSTEM_NSH=y -CONFIG_USBDEV=y diff --git a/boards/arm/stm32/photon/configs/usbnsh/defconfig b/boards/arm/stm32/photon/configs/usbnsh/defconfig deleted file mode 100644 index 860b33017022a..0000000000000 --- a/boards/arm/stm32/photon/configs/usbnsh/defconfig +++ /dev/null @@ -1,52 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_DEV_CONSOLE is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="photon" -CONFIG_ARCH_BOARD_PHOTON=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F205RG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARDCTL_USBDEVCTRL=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_CDCACM=y -CONFIG_CDCACM_CONSOLE=y -CONFIG_FS_PROCFS=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_MM_REGIONS=2 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PHOTON_DFU_BOOTLOADER=y -CONFIG_PHOTON_IWDG=y -CONFIG_PHOTON_WDG_THREAD=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=6 -CONFIG_START_MONTH=12 -CONFIG_START_YEAR=2011 -CONFIG_STM32_IWDG=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_OTGHS=y -CONFIG_STM32_USART1=y -CONFIG_SYSLOG_CHAR=y -CONFIG_SYSLOG_DEVPATH="/dev/ttyS0" -CONFIG_SYSTEM_NSH=y -CONFIG_USBDEV=y diff --git a/boards/arm/stm32/photon/configs/wlan-perf/defconfig b/boards/arm/stm32/photon/configs/wlan-perf/defconfig deleted file mode 100644 index d6a02110e3b7c..0000000000000 --- a/boards/arm/stm32/photon/configs/wlan-perf/defconfig +++ /dev/null @@ -1,88 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_LEDS is not set -# CONFIG_IEEE80211_BROADCOM_FWFILES is not set -# CONFIG_MMCSD_HAVE_CARDDETECT is not set -# CONFIG_MMCSD_MMCSUPPORT is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="photon" -CONFIG_ARCH_BOARD_PHOTON=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F205RG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_DFU_BASE=0x8020000 -CONFIG_DFU_BINARY=y -CONFIG_DFU_PID=0xd006 -CONFIG_DFU_VID=0x2b04 -CONFIG_DRIVERS_IEEE80211=y -CONFIG_DRIVERS_WIRELESS=y -CONFIG_FS_PROCFS=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_IEEE80211_BROADCOM_BCM43362=y -CONFIG_IEEE80211_BROADCOM_DMABUF_ALIGNMENT=16 -CONFIG_IEEE80211_BROADCOM_FRAME_POOL_SIZE=32 -CONFIG_IEEE80211_BROADCOM_FULLMAC_SDIO=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LIBM=y -CONFIG_LINE_MAX=64 -CONFIG_MMCSD=y -CONFIG_MMCSD_SDIO=y -CONFIG_MM_REGIONS=2 -CONFIG_NET=y -CONFIG_NETDB_DNSCLIENT=y -CONFIG_NETDEV_LATEINIT=y -CONFIG_NETDEV_WIRELESS_IOCTL=y -CONFIG_NETINIT_DHCPC=y -CONFIG_NETINIT_DRIPADDR=0xc0a80001 -CONFIG_NETUTILS_DHCPC=y -CONFIG_NETUTILS_IPERF=y -CONFIG_NETUTILS_TELNETD=y -CONFIG_NET_BROADCAST=y -CONFIG_NET_ETH_PKTSIZE=1514 -CONFIG_NET_ICMP_SOCKET=y -CONFIG_NET_PKT=y -CONFIG_NET_TCP=y -CONFIG_NET_UDP=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PHOTON_DFU_BOOTLOADER=y -CONFIG_PHOTON_IWDG=y -CONFIG_PHOTON_WDG_THREAD=y -CONFIG_PHOTON_WLAN=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_WAITPID=y -CONFIG_SDIO_BLOCKSETUP=y -CONFIG_START_DAY=6 -CONFIG_START_MONTH=12 -CONFIG_START_YEAR=2011 -CONFIG_STM32_DMA2=y -CONFIG_STM32_IWDG=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_SDIO=y -CONFIG_STM32_SDIO_CARD=y -CONFIG_STM32_USART1=y -CONFIG_SYSLOG_CHAR=y -CONFIG_SYSLOG_DEVPATH="/dev/ttyS0" -CONFIG_SYSTEM_NSH=y -CONFIG_SYSTEM_PING=y -CONFIG_USART1_SERIAL_CONSOLE=y -CONFIG_USERLED=y -CONFIG_WIRELESS_WAPI=y -CONFIG_WIRELESS_WAPI_CMDTOOL=y diff --git a/boards/arm/stm32/photon/configs/wlan/defconfig b/boards/arm/stm32/photon/configs/wlan/defconfig deleted file mode 100644 index c2cf5294c3b44..0000000000000 --- a/boards/arm/stm32/photon/configs/wlan/defconfig +++ /dev/null @@ -1,100 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_LEDS is not set -# CONFIG_IEEE80211_BROADCOM_FWFILES is not set -# CONFIG_MMCSD_HAVE_CARDDETECT is not set -# CONFIG_MMCSD_MMCSUPPORT is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="photon" -CONFIG_ARCH_BOARD_PHOTON=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F205RG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_DEBUG_ASSERTIONS=y -CONFIG_DEBUG_FEATURES=y -CONFIG_DEBUG_FULLOPT=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_DFU_BASE=0x8020000 -CONFIG_DFU_BINARY=y -CONFIG_DFU_PID=0xd006 -CONFIG_DFU_VID=0x2b04 -CONFIG_DRIVERS_IEEE80211=y -CONFIG_DRIVERS_WIRELESS=y -CONFIG_FS_PROCFS=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_IEEE80211_BROADCOM_BCM43362=y -CONFIG_IEEE80211_BROADCOM_DMABUF_ALIGNMENT=16 -CONFIG_IEEE80211_BROADCOM_FRAME_POOL_SIZE=16 -CONFIG_IEEE80211_BROADCOM_FULLMAC_SDIO=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LIBM=y -CONFIG_LINE_MAX=64 -CONFIG_MMCSD=y -CONFIG_MMCSD_SDIO=y -CONFIG_MMCSD_SDIOWAIT_WRCOMPLETE=y -CONFIG_MM_REGIONS=2 -CONFIG_NDEBUG=y -CONFIG_NET=y -CONFIG_NETDB_DNSCLIENT=y -CONFIG_NETDEV_LATEINIT=y -CONFIG_NETDEV_WIRELESS_IOCTL=y -CONFIG_NETINIT_DHCPC=y -CONFIG_NETINIT_DRIPADDR=0xc0a80001 -CONFIG_NETUTILS_IPERF=y -CONFIG_NETUTILS_TELNETD=y -CONFIG_NET_BROADCAST=y -CONFIG_NET_ETH_PKTSIZE=1518 -CONFIG_NET_GUARDSIZE=32 -CONFIG_NET_ICMP_SOCKET=y -CONFIG_NET_PKT=y -CONFIG_NET_TCP=y -CONFIG_NET_UDP=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PHOTON_DFU_BOOTLOADER=y -CONFIG_PHOTON_IWDG=y -CONFIG_PHOTON_WDG_THREAD=y -CONFIG_PHOTON_WLAN=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_WAITPID=y -CONFIG_SDIO_BLOCKSETUP=y -CONFIG_START_DAY=6 -CONFIG_START_MONTH=12 -CONFIG_START_YEAR=2011 -CONFIG_STM32_DMA2=y -CONFIG_STM32_IWDG=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_SDIO=y -CONFIG_STM32_SDIO_CARD=y -CONFIG_STM32_USART1=y -CONFIG_SYSLOG_BUFFER=y -CONFIG_SYSLOG_CHAR=y -CONFIG_SYSLOG_CONSOLE=y -CONFIG_SYSLOG_DEVPATH="/dev/ttyS0" -CONFIG_SYSLOG_INTBUFFER=y -CONFIG_SYSLOG_PROCESSID=y -CONFIG_SYSLOG_TIMESTAMP=y -CONFIG_SYSTEM_DHCPC_RENEW=y -CONFIG_SYSTEM_NSH=y -CONFIG_SYSTEM_PING=y -CONFIG_USART1_SERIAL_CONSOLE=y -CONFIG_USERLED=y -CONFIG_WIRELESS_WAPI=y -CONFIG_WIRELESS_WAPI_CMDTOOL=y diff --git a/boards/arm/stm32/photon/include/board.h b/boards/arm/stm32/photon/include/board.h deleted file mode 100644 index 6c5ac34d01c1e..0000000000000 --- a/boards/arm/stm32/photon/include/board.h +++ /dev/null @@ -1,311 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/photon/include/board.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __BOARDS_ARM_STM32_PHOTON_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32_PHOTON_INCLUDE_BOARD_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#ifndef __ASSEMBLY__ -# include -#endif - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Clocking *****************************************************************/ - -/* The Particle photon board features a single 26MHz crystal. - * - * This is the canonical configuration: - * System Clock source : PLL (HSE) - * SYSCLK(Hz) : 120000000 Determined by PLL - * configuration - * HCLK(Hz) : 120000000 (STM32_RCC_CFGR_HPRE) - * AHB Prescaler : 1 (STM32_RCC_CFGR_HPRE) - * APB1 Prescaler : 4 (STM32_RCC_CFGR_PPRE1) - * APB2 Prescaler : 2 (STM32_RCC_CFGR_PPRE2) - * HSE Frequency(Hz) : 26000000 (STM32_BOARD_XTAL) - * PLLM : 26 (STM32_PLLCFG_PLLM) - * PLLN : 240 (STM32_PLLCFG_PLLN) - * PLLP : 2 (STM32_PLLCFG_PLLP) - * PLLQ : 5 (STM32_PLLCFG_PLLQ) - * Main regulator output voltage : Scale1 mode Needed for high speed - * SYSCLK - * Flash Latency(WS) : 3 - * Prefetch Buffer : OFF - * Instruction cache : ON - * Data cache : ON - * Require 48MHz for USB OTG HS : Enabled - * SDIO and RNG clock - */ - -/* HSI - 16 MHz RC factory-trimmed - * LSI - 32 KHz RC - * HSE - On-board crystal frequency is 26MHz - * LSE - 32.768 kHz - */ - -#define STM32_BOARD_XTAL 26000000ul - -#define STM32_HSI_FREQUENCY 16000000ul -#define STM32_LSI_FREQUENCY 32000 -#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL -#define STM32_LSE_FREQUENCY 32768 - -/* Main PLL Configuration. - * - * PLL source is HSE - * PLL_VCO = (STM32_HSE_FREQUENCY / PLLM) * PLLN - * = (26,000,000 / 26) * 240 - * = 240,000,000 - * SYSCLK = PLL_VCO / PLLP - * = 240,000,000 / 2 = 120,000,000 - * USB OTG FS, SDIO and RNG Clock - * = PLL_VCO / PLLQ - * = 48,000,000 - */ - -#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(26) -#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(240) -#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_2 -#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(5) - -#define STM32_SYSCLK_FREQUENCY 120000000ul - -/* AHB clock (HCLK) is SYSCLK (120MHz) */ - -#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ -#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY - -/* APB1 clock (PCLK1) is HCLK/4 (30MHz) */ - -#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd4 /* PCLK1 = HCLK / 4 */ -#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/4) - -/* Timers driven from APB1 will be twice PCLK1 */ - -#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) - -/* APB2 clock (PCLK2) is HCLK/2 (60MHz) */ - -#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLKd2 /* PCLK2 = HCLK / 2 */ -#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/2) - -/* Timers driven from APB2 will be twice PCLK2 */ - -#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM9_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM10_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM11_CLKIN (2*STM32_PCLK2_FREQUENCY) - -/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx - * otherwise frequency is 2xAPBx. - * Note: TIM1,8 are on APB2, others on APB1 - */ - -#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM2_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM3_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM4_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM5_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM6_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM7_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY - -/* USB OTG HS definitions ***************************************************/ - -/* Do not enable external PHY clock or OTG_HS module will not work */ - -#undef BOARD_ENABLE_USBOTG_HSULPI - -/* LED definitions **********************************************************/ - -/* LEDs - * - * A single LED is available driven by PA13. - */ - -/* LED index values for use with board_userled() */ - -#define BOARD_LED1 0 -#define BOARD_NLEDS 1 - -/* LED bits for use with board_userled_all() */ - -#define BOARD_LED1_BIT (1 << BOARD_LED1) - -/* These LEDs are not used by the board port unless CONFIG_ARCH_LEDS is - * defined. In that case, the usage by the board port is defined in - * include/board.h and src/sam_autoleds.c. The LEDs are used to encode - * OS-related events as follows: - * - * ------------------- ---------------------------- ------ - * SYMBOL Meaning LED - * ------------------- ---------------------------- ------ - */ - -#define LED_STARTED 0 /* NuttX has been started OFF */ -#define LED_HEAPALLOCATE 0 /* Heap has been allocated OFF */ -#define LED_IRQSENABLED 0 /* Interrupts enabled OFF */ -#define LED_STACKCREATED 1 /* Idle stack created ON */ -#define LED_INIRQ 2 /* In an interrupt N/C */ -#define LED_SIGNAL 2 /* In a signal handler N/C */ -#define LED_ASSERTION 2 /* An assertion failed N/C */ -#define LED_PANIC 3 /* The system has crashed FLASH */ -#undef LED_IDLE /* MCU is in sleep mode Not used */ - -/* Thus if LED is statically on, NuttX has successfully booted and is, - * apparently, running normally. If LED is flashing at approximately - * 2Hz, then a fatal error has been detected and the system has halted. - */ - -/* TIM */ - -#define GPIO_TIM2_CH2OUT (GPIO_TIM2_CH2OUT_1|GPIO_SPEED_50MHz) -#define GPIO_TIM2_CH3OUT (GPIO_TIM2_CH3OUT_1|GPIO_SPEED_50MHz) -#define GPIO_TIM2_CH4OUT (GPIO_TIM2_CH4OUT_1|GPIO_SPEED_50MHz) - -/* RGB LED - * - * R = TIM2 CH2 on PA1 | G = TIM2 CH3 on PA2 | B = TIM4 CH4 on PA3 - * - * Note: Pin boards: GPIO_TIM2_CH2OUT ; GPIO_TIM2_CH3OUT ; GPIO_TIM2_CH4OUT - */ - -#define RGBLED_RPWMTIMER 2 -#define RGBLED_RPWMCHANNEL 2 -#define RGBLED_GPWMTIMER 2 -#define RGBLED_GPWMCHANNEL 3 -#define RGBLED_BPWMTIMER 2 -#define RGBLED_BPWMCHANNEL 4 - -/* Button definitions *******************************************************/ - -#define BOARD_BUTTON1 0 -#define NUM_BUTTONS 1 -#define BOARD_BUTTON1_BIT (1 << BOARD_BUTTON1) - -/* Alternate function pin selections ****************************************/ - -/* UART1 */ - -#ifdef CONFIG_STM32_USART1 -# define GPIO_USART1_RX (GPIO_USART1_RX_1|GPIO_SPEED_100MHz) -# define GPIO_USART1_TX (GPIO_USART1_TX_1|GPIO_SPEED_100MHz) -#endif - -/* SPI1 */ - -#define GPIO_SPI1_MISO (GPIO_SPI1_MISO_1|GPIO_SPEED_50MHz) /* PA6 */ -#define GPIO_SPI1_MOSI (GPIO_SPI1_MOSI_1|GPIO_SPEED_50MHz) /* PA7 */ -#define GPIO_SPI1_SCK (GPIO_SPI1_SCK_1|GPIO_SPEED_50MHz) /* PA5 */ - -/* SPI3 */ - -#define GPIO_SPI3_MISO (GPIO_SPI3_MISO_1|GPIO_SPEED_50MHz) /* PB4 */ -#define GPIO_SPI3_MOSI (GPIO_SPI3_MOSI_1|GPIO_SPEED_50MHz) /* PB5 */ -#define GPIO_SPI3_SCK (GPIO_SPI3_SCK_1|GPIO_SPEED_50MHz) /* PB3 */ - -/* SDIO */ - -#define GPIO_SDIO_CK (GPIO_SDIO_CK_0|GPIO_SPEED_50MHz) -#define GPIO_SDIO_CMD (GPIO_SDIO_CMD_0|GPIO_SPEED_50MHz) -#define GPIO_SDIO_D0 (GPIO_SDIO_D0_0|GPIO_SPEED_50MHz) -#define GPIO_SDIO_D1 (GPIO_SDIO_D1_0|GPIO_SPEED_50MHz) -#define GPIO_SDIO_D2 (GPIO_SDIO_D2_0|GPIO_SPEED_50MHz) -#define GPIO_SDIO_D3 (GPIO_SDIO_D3_0|GPIO_SPEED_50MHz) - -/* OTG FS */ - -#define GPIO_OTGFS_DM (GPIO_OTGFS_DM_0|GPIO_SPEED_100MHz) -#define GPIO_OTGFS_DP (GPIO_OTGFS_DP_0|GPIO_SPEED_100MHz) -#define GPIO_OTGFS_ID (GPIO_OTGFS_ID_0|GPIO_SPEED_100MHz) -#define GPIO_OTGFS_SOF (GPIO_OTGFS_SOF_0|GPIO_SPEED_100MHz) - -/* OTG HS */ - -#define GPIO_OTGHS_DM (GPIO_OTGHS_DM_0|GPIO_SPEED_100MHz) -#define GPIO_OTGHS_DP (GPIO_OTGHS_DP_0|GPIO_SPEED_100MHz) -#define GPIO_OTGHS_ID GPIO_OTGHS_ID_0 -#define GPIO_OTGHS_SOF GPIO_OTGHS_SOF_0 - -/* SDIO definitions *********************************************************/ - -/* Note that slower clocking is required when DMA is disabled in order - * to avoid RX overrun/TX underrun errors due to delayed responses - * to service FIFOs in interrupt driven mode. - * - * These values have not been tuned!!! - * - * SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(118+2)=400 KHz - */ - -#define SDIO_INIT_CLKDIV (118 << SDIO_CLKCR_CLKDIV_SHIFT) - -/* DMA ON: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(1+2)=16 MHz - * DMA OFF: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(2+2)=12 MHz - */ - -#ifdef CONFIG_SDIO_DMA -# define SDIO_MMCXFR_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT) -#else -# define SDIO_MMCXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT) -#endif - -/* DMA ON: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(1+2)=16 MHz - * DMA OFF: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(2+2)=12 MHz - */ - -#ifdef CONFIG_SDIO_DMA -# define SDIO_SDXFR_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT) -#else -# define SDIO_SDXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT) -#endif - -/* DMA Channel/Stream Selections ********************************************/ - -/* Stream selections are arbitrary for now but might become important in the - * future if we set aside more DMA channels/streams. - * - * SDIO DMA - * DMAMAP_SDIO_1 = Channel 4, Stream 3 - * DMAMAP_SDIO_2 = Channel 4, Stream 6 - */ - -#define DMAMAP_SDIO DMAMAP_SDIO_1 - -#endif /* __BOARDS_ARM_STM32_PHOTON_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32/photon/scripts/Make.defs b/boards/arm/stm32/photon/scripts/Make.defs deleted file mode 100644 index 12f4622680f7f..0000000000000 --- a/boards/arm/stm32/photon/scripts/Make.defs +++ /dev/null @@ -1,68 +0,0 @@ -############################################################################ -# boards/arm/stm32/photon/scripts/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/.config -include $(TOPDIR)/tools/Config.mk -include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs - -ifeq ($(CONFIG_PHOTON_DFU_BOOTLOADER),y) -LDSCRIPT = photon_dfu.ld -else -LDSCRIPT = photon_jtag.ld -endif - -ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) - -# See http://dfu-util.sourceforge.net/ - -DFUSUFFIX = dfu-suffix -DFUUTIL = dfu-util - -ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 - -CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) -CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) -CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -AFLAGS := $(CFLAGS) -D__ASSEMBLY__ - -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections -LDNXFLATFLAGS = -e main -s 2048 - -ifeq ($(CONFIG_DFU_BINARY),y) - -define FLASH - $(Q) echo "DFUSUFFIX: $(1).dfu" - $(Q) $(OBJCOPY) $(OBJCOPYARGS) -O binary $(1) $(1).dfu - $(Q) $(DFUSUFFIX) -v $(subst 0x,,$(CONFIG_DFU_VID)) -p $(subst 0x,,$(CONFIG_DFU_PID)) -a $(1).dfu - $(Q) $(DFUUTIL) -d $(CONFIG_DFU_VID):$(CONFIG_DFU_PID) -a 0 -s $(CONFIG_DFU_BASE) -D $(1).dfu -endef - -else - -define FLASH - $(Q) $(ECHO) "Photon firmware upload through JTAG is not supported" -endef - -endif diff --git a/boards/arm/stm32/photon/src/CMakeLists.txt b/boards/arm/stm32/photon/src/CMakeLists.txt deleted file mode 100644 index e6e55c00a003c..0000000000000 --- a/boards/arm/stm32/photon/src/CMakeLists.txt +++ /dev/null @@ -1,68 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/photon/src/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -set(SRCS stm32_boot.c stm32_bringup.c stm32_spi.c) - -if(CONFIG_PHOTON_DFU_BOOTLOADER) - list(APPEND SRCS dfu_signature.c) -endif() - -if(CONFIG_INPUT_BUTTONS) - list(APPEND SRCS stm32_buttons.c) -endif() - -if(CONFIG_ARCH_LEDS) - list(APPEND SRCS stm32_autoleds.c) -else() - list(APPEND SRCS stm32_userleds.c) -endif() - -if(CONFIG_PHOTON_WDG) - list(APPEND SRCS stm32_wdt.c) -endif() - -if(CONFIG_PHOTON_WLAN) - list(APPEND SRCS stm32_wlan.c) - list(APPEND SRCS stm32_wlan_firmware.c) -endif() - -if(CONFIG_STM32_OTGHS) - list(APPEND SRCS stm32_usb.c) -endif() - -if(CONFIG_RGBLED) - list(APPEND SRCS stm32_rgbled.c) -endif() - -if(CONFIG_USBDEV_COMPOSITE) - list(APPEND SRCS stm32_composite.c) -endif() - -target_sources(board PRIVATE ${SRCS}) - -if(CONFIG_PHOTON_DFU_BOOTLOADER) - set_property(GLOBAL PROPERTY LD_SCRIPT - "${NUTTX_BOARD_DIR}/scripts/photon_dfu.ld") -else() - set_property(GLOBAL PROPERTY LD_SCRIPT - "${NUTTX_BOARD_DIR}/scripts/photon_jtag.ld") -endif() diff --git a/boards/arm/stm32/photon/src/Make.defs b/boards/arm/stm32/photon/src/Make.defs deleted file mode 100644 index 6edf5dce2d9a9..0000000000000 --- a/boards/arm/stm32/photon/src/Make.defs +++ /dev/null @@ -1,64 +0,0 @@ -############################################################################ -# boards/arm/stm32/photon/src/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/Make.defs - -CSRCS = stm32_boot.c stm32_bringup.c stm32_spi.c - -ifeq ($(CONFIG_PHOTON_DFU_BOOTLOADER),y) -CSRCS += dfu_signature.c -endif - -ifeq ($(CONFIG_INPUT_BUTTONS),y) -CSRCS += stm32_buttons.c -endif - -ifeq ($(CONFIG_ARCH_LEDS),y) -CSRCS += stm32_autoleds.c -else -CSRCS += stm32_userleds.c -endif - -ifeq ($(CONFIG_PHOTON_WDG),y) -CSRCS += stm32_wdt.c -endif - -ifeq ($(CONFIG_PHOTON_WLAN),y) -CSRCS += stm32_wlan.c -CSRCS += stm32_wlan_firmware.c -endif - -ifeq ($(CONFIG_STM32_OTGHS),y) -CSRCS += stm32_usb.c -endif - -ifeq ($(CONFIG_RGBLED),y) - CSRCS += stm32_rgbled.c -endif - -ifeq ($(CONFIG_USBDEV_COMPOSITE),y) -CSRCS += stm32_composite.c -endif - -DEPPATH += --dep-path board -VPATH += :board -CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/photon/src/stm32_autoleds.c b/boards/arm/stm32/photon/src/stm32_autoleds.c deleted file mode 100644 index f78cd9a89a0af..0000000000000 --- a/boards/arm/stm32/photon/src/stm32_autoleds.c +++ /dev/null @@ -1,103 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/photon/src/stm32_autoleds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* LEDs - * - * A single LED is available driven by PA13. - * - * These LEDs are not used by the board port unless CONFIG_ARCH_LEDS is - * defined. In that case, the usage by the board port is defined in - * include/board.h and src/sam_autoleds.c. The LEDs are used to encode - * OS-related events as follows: - * - * ------------------- ----------------------- ------ - * SYMBOL Meaning LED - * ------------------- ----------------------- ------ - * LED_STARTED NuttX has been started OFF - * LED_HEAPALLOCATE Heap has been allocated OFF - * LED_IRQSENABLED Interrupts enabled OFF - * LED_STACKCREATED Idle stack created ON - * LED_INIRQ In an interrupt N/C - * LED_SIGNAL In a signal handler N/C - * LED_ASSERTION An assertion failed N/C - * LED_PANIC The system has crashed FLASH - * - * Thus is LED is statically on, NuttX has successfully booted and is, - * apparently, running normally. If LED is flashing at approximately - * 2Hz, then a fatal error has been detected and the system has halted. - */ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include - -#include -#include - -#include "stm32_gpio.h" -#include "photon.h" - -#ifdef CONFIG_ARCH_LEDS - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_autoled_initialize - ****************************************************************************/ - -void board_autoled_initialize(void) -{ - /* Configure Photon LED gpio as output */ - - stm32_configgpio(GPIO_LED1); -} - -/**************************************************************************** - * Name: board_autoled_on - ****************************************************************************/ - -void board_autoled_on(int led) -{ - if (led == 1 || led == 3) - { - stm32_gpiowrite(GPIO_LED1, true); - } -} - -/**************************************************************************** - * Name: board_autoled_off - ****************************************************************************/ - -void board_autoled_off(int led) -{ - if (led == 3) - { - stm32_gpiowrite(GPIO_LED1, false); - } -} - -#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/photon/src/stm32_boot.c b/boards/arm/stm32/photon/src/stm32_boot.c deleted file mode 100644 index 631df3142d6a5..0000000000000 --- a/boards/arm/stm32/photon/src/stm32_boot.c +++ /dev/null @@ -1,106 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/photon/src/stm32_boot.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include "arm_internal.h" -#include "photon.h" - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_boardinitialize - * - * Description: - * All STM32 architectures must provide the following entry point. This - * entry point is called early in the initialization -- after all memory - * has been configured and mapped but before any devices have been - * initialized. - * - ****************************************************************************/ - -void stm32_boardinitialize(void) -{ -#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || defined(CONFIG_STM32_SPI3) - /* Configure SPI chip selects if 1) SPI is not disabled, and 2) the weak - * function stm32_spidev_initialize() has been brought into the link. - */ - - if (stm32_spidev_initialize) - { - stm32_spidev_initialize(); - } -#endif - -#ifdef CONFIG_STM32_OTGHS - /* Initialize USB if the - * 1) OTG HS controller is in the configuration and - * 2) disabled, and - * 3) the weak function stm32_usbinitialize() has been brought into - * the build. Presumably either CONFIG_USBDEV or CONFIG_USBHOST is also - * selected. - */ - - if (stm32_usbinitialize) - { - stm32_usbinitialize(); - } -#endif - -#ifdef CONFIG_ARCH_LEDS - /* Configure on-board LEDs if LED support has been selected. */ - - board_autoled_initialize(); -#endif -} - -/**************************************************************************** - * Name: board_late_initialize - * - * Description: - * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional - * initialization call will be performed in the boot-up sequence to a - * function called board_late_initialize(). board_late_initialize() will - * be called immediately after up_initialize() is called and just before - * the initial application is started. This additional initialization - * phase may be used, for example, to initialize board-specific device - * drivers. - * - ****************************************************************************/ - -#ifdef CONFIG_BOARD_LATE_INITIALIZE -void board_late_initialize(void) -{ - /* Perform board initialization */ - - stm32_bringup(); -} -#endif /* CONFIG_BOARD_LATE_INITIALIZE */ diff --git a/boards/arm/stm32/photon/src/stm32_bringup.c b/boards/arm/stm32/photon/src/stm32_bringup.c deleted file mode 100644 index 5096dad8d0b5b..0000000000000 --- a/boards/arm/stm32/photon/src/stm32_bringup.c +++ /dev/null @@ -1,167 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/photon/src/stm32_bringup.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include -#include -#include - -#include - -#include "photon.h" -#include "stm32_wdg.h" - -#ifdef CONFIG_USBADB -# include -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_bringup - * - * Description: - * This function initializes and configures all on-board features - * appropriate for the selected configuration. - * - ****************************************************************************/ - -int stm32_bringup(void) -{ - int ret = OK; - -#ifdef CONFIG_FS_PROCFS - /* Mount the procfs file system */ - - ret = nx_mount(NULL, "/proc", "procfs", 0, NULL); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: Failed to mount procfs at /proc: %d\n", ret); - } -#endif - -#if defined(CONFIG_USERLED) && !defined(CONFIG_ARCH_LEDS) -#ifdef CONFIG_USERLED_LOWER - /* Register the LED driver */ - - ret = userled_lower_initialize("/dev/userleds"); - if (ret != OK) - { - syslog(LOG_ERR, "ERROR: userled_lower_initialize() failed: %d\n", ret); - return ret; - } -#else - /* Enable USER LED support for some other purpose */ - - board_userled_initialize(); -#endif /* CONFIG_USERLED_LOWER */ -#endif /* CONFIG_USERLED && !CONFIG_ARCH_LEDS */ - -#ifdef CONFIG_INPUT_BUTTONS -#ifdef CONFIG_INPUT_BUTTONS_LOWER - /* Register the BUTTON driver */ - - ret = btn_lower_initialize("/dev/buttons"); - if (ret != OK) - { - syslog(LOG_ERR, "ERROR: btn_lower_initialize() failed: %d\n", ret); - return ret; - } -#else - /* Enable BUTTON support for some other purpose */ - - board_button_initialize(); -#endif /* CONFIG_INPUT_BUTTONS_LOWER */ -#endif /* CONFIG_INPUT_BUTTONS */ - -#ifdef CONFIG_STM32_IWDG - /* Initialize the watchdog timer */ - - stm32_iwdginitialize("/dev/watchdog0", STM32_LSI_FREQUENCY); -#endif - -#ifdef CONFIG_PHOTON_WDG - /* Start WDG kicker thread */ - - ret = photon_watchdog_initialize(); - if (ret != OK) - { - syslog(LOG_ERR, "Failed to start watchdog thread: %d\n", ret); - return ret; - } -#endif - -#ifdef CONFIG_RGBLED - /* Configure and initialize the RGB LED. */ - - ret = stm32_rgbled_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_rgbled_setup() failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_PHOTON_WLAN - /* Initialize wlan driver and hardware */ - - ret = photon_wlan_initialize(); - if (ret != OK) - { - syslog(LOG_ERR, "Failed to initialize wlan: %d\n", ret); - return ret; - } -#endif - -#ifdef CONFIG_USBDEV_COMPOSITE - -#ifndef CONFIG_BOARDCTL_USBDEVCTRL - ret = board_composite_initialize(0); - if (ret != OK) - { - syslog(LOG_ERR, "Failed to initialize composite: %d\n", ret); - return ret; - } - - if (board_composite_connect(0, 0) == NULL) - { - syslog(LOG_ERR, "Failed to connect composite: %d\n", ret); - return ret; - } -#endif /* !CONFIG_BOARDCTL_USBDEVCTRL */ -#else -#ifdef CONFIG_USBADB - usbdev_adb_initialize(); -#endif -#endif /* CONFIG_USBDEV_COMPOSITE */ - return ret; -} diff --git a/boards/arm/stm32/photon/src/stm32_buttons.c b/boards/arm/stm32/photon/src/stm32_buttons.c deleted file mode 100644 index 9288ec789f6a9..0000000000000 --- a/boards/arm/stm32/photon/src/stm32_buttons.c +++ /dev/null @@ -1,88 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/photon/src/stm32_buttons.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include "photon.h" - -#include "stm32_gpio.h" - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_button_initialize - ****************************************************************************/ - -uint32_t board_button_initialize(void) -{ - /* Configure Photon button gpio as input */ - - stm32_configgpio(GPIO_BUTTON1); - return NUM_BUTTONS; -} - -/**************************************************************************** - * Name: board_buttons - ****************************************************************************/ - -uint32_t board_buttons(void) -{ - /* Check the state of the only button */ - - if (stm32_gpioread(GPIO_BUTTON1)) - { - return BOARD_BUTTON1_BIT; - } - - return 0; -} - -/**************************************************************************** - * Name: board_button_irq - ****************************************************************************/ - -#ifdef CONFIG_ARCH_IRQBUTTONS -int board_button_irq(int id, xcpt_t irqhandler, void *arg) -{ - if (id != BOARD_BUTTON1) - { - /* Invalid button id */ - - return -EINVAL; - } - - /* Configure interrupt on falling edge only */ - - return stm32_gpiosetevent(GPIO_BUTTON1, false, true, false, - irqhandler, arg); -} -#endif /* CONFIG_ARCH_IRQBUTTONS */ diff --git a/boards/arm/stm32/photon/src/stm32_composite.c b/boards/arm/stm32/photon/src/stm32_composite.c deleted file mode 100644 index f0eec287904cf..0000000000000 --- a/boards/arm/stm32/photon/src/stm32_composite.c +++ /dev/null @@ -1,166 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/photon/src/stm32_composite.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include -#include -#include - -#include "stm32.h" - -#if defined(CONFIG_BOARDCTL_USBDEVCTRL) && defined(CONFIG_USBDEV_COMPOSITE) - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_composite0_connect - * - * Description: - * Connect the USB composite device on the specified USB device port for - * configuration 0. - * - * Input Parameters: - * port - The USB device port. - * - * Returned Value: - * A non-NULL handle value is returned on success. NULL is returned on - * any failure. - * - ****************************************************************************/ - -static void *board_composite0_connect(int port) -{ - /* Here we are composing the configuration of the usb composite device. - * - * The standard is to use one CDC/ACM and one USB mass storage device. - */ - - /* Change "dev" array size to add more composite devs */ - - struct composite_devdesc_s dev[1]; - int ifnobase = 0; - int strbase = (COMPOSITE_NSTRIDS) - 1; - - int dev_idx = 0; - -#ifdef CONFIG_USBADB - /* Configure the ADB USB device */ - - /* Ask the adb driver to fill in the constants we didn't - * know here. - */ - - usbdev_adb_get_composite_devdesc(&dev[dev_idx]); - - /* Interfaces */ - - dev[dev_idx].devinfo.ifnobase = ifnobase; /* Offset to Interface-IDs */ - dev[dev_idx].minor = 0; /* The minor interface number */ - - /* Strings */ - - dev[dev_idx].devinfo.strbase = strbase; /* Offset to String Numbers */ - - /* Endpoints */ - - dev[dev_idx].devinfo.epno[USBADB_EP_BULKIN_IDX] = 1; - dev[dev_idx].devinfo.epno[USBADB_EP_BULKOUT_IDX] = 2; - - /* Count up the base numbers */ - - ifnobase += dev[dev_idx].devinfo.ninterfaces; - strbase += dev[dev_idx].devinfo.nstrings; - - dev_idx += 1; -#endif - - /* Add other composite devices here */ - - return composite_initialize(composite_getdevdescs(), dev, dev_idx); -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_composite_initialize - * - * Description: - * Perform architecture specific initialization of a composite USB device. - * - ****************************************************************************/ - -int board_composite_initialize(int port) -{ - return OK; -} - -/**************************************************************************** - * Name: board_composite_connect - * - * Description: - * Connect the USB composite device on the specified USB device port using - * the specified configuration. The interpretation of the configid is - * board specific. - * - * Input Parameters: - * port - The USB device port. - * configid - The USB composite configuration - * - * Returned Value: - * A non-NULL handle value is returned on success. NULL is returned on - * any failure. - * - ****************************************************************************/ - -void *board_composite_connect(int port, int configid) -{ - if (configid == 0) - { - return board_composite0_connect(port); - } - - return NULL; -} - -#endif /* CONFIG_BOARDCTL_USBDEVCTRL && CONFIG_USBDEV_COMPOSITE */ diff --git a/boards/arm/stm32/photon/src/stm32_rgbled.c b/boards/arm/stm32/photon/src/stm32_rgbled.c deleted file mode 100644 index c43f21b604ba1..0000000000000 --- a/boards/arm/stm32/photon/src/stm32_rgbled.c +++ /dev/null @@ -1,169 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/photon/src/stm32_rgbled.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include - -#include -#include -#include -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32_pwm.h" -#include "photon.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -#define HAVE_RGBLED 1 - -#ifndef CONFIG_PWM -# undef HAVE_RGBLED -#endif - -#ifndef CONFIG_STM32_TIM2 -# undef HAVE_RGBLED -#endif - -#ifndef CONFIG_STM32_TIM2_PWM -# undef HAVE_RGBLED -#endif - -#ifndef CONFIG_STM32_TIM2_CHANNEL2 -# undef HAVE_PWM -#endif - -#ifndef CONFIG_STM32_TIM2_CHANNEL3 -# undef HAVE_PWM -#endif - -#ifndef CONFIG_STM32_TIM2_CHANNEL4 -# undef HAVE_PWM -#endif - -#ifdef HAVE_RGBLED - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_rgbled_setup - * - * Description: - * Initial for support of a connected RGB LED using PWM. - * - ****************************************************************************/ - -int stm32_rgbled_setup(void) -{ - static bool initialized = false; - struct pwm_lowerhalf_s *ledr; - struct pwm_lowerhalf_s *ledg; - struct pwm_lowerhalf_s *ledb; - struct file file; - int ret; - - /* Have we already initialized? */ - - if (!initialized) - { - /* Call stm32_pwminitialize() to get an instance of the PWM interface */ - - ledr = stm32_pwminitialize(RGBLED_RPWMTIMER); - if (!ledr) - { - lederr("ERROR: Failed to get the STM32 PWM lower half to LEDR\n"); - return -ENODEV; - } - - ledr->ops->setup(ledr); - - /* Call stm32_pwminitialize() to get an instance of the PWM interface */ - - ledg = stm32_pwminitialize(RGBLED_GPWMTIMER); - if (!ledg) - { - lederr("ERROR: Failed to get the STM32 PWM lower half to LEDG\n"); - return -ENODEV; - } - - ledg->ops->setup(ledg); - - /* Call stm32_pwminitialize() to get an instance of the PWM interface */ - - ledb = stm32_pwminitialize(RGBLED_BPWMTIMER); - if (!ledb) - { - lederr("ERROR: Failed to get the STM32 PWM lower half to LEDB\n"); - return -ENODEV; - } - - ledb->ops->setup(ledb); - - /* Register the RGB LED diver at "/dev/rgbled0" */ - - ret = rgbled_register("/dev/rgbled0", ledr, ledg, ledb, - RGBLED_RPWMCHANNEL, RGBLED_GPWMCHANNEL, - RGBLED_BPWMCHANNEL); - if (ret < 0) - { - lederr("ERROR: rgbled_register failed: %d\n", ret); - return ret; - } - - ret = file_open(&file, "/dev/rgbled0", O_WRONLY); - if (ret < 0) - { - lederr("ERROR: open failed: %d\n", ret); - return ret; - } - - /* Initialize led off */ - - file_write(&file, "#000000", 8); - file_close(&file); - - /* Now we are initialized */ - - initialized = true; - } - - return OK; -} - -#else -# error "HAVE_RGBLED is undefined" -#endif /* HAVE_RGBLED */ diff --git a/boards/arm/stm32/photon/src/stm32_spi.c b/boards/arm/stm32/photon/src/stm32_spi.c deleted file mode 100644 index 618331bb43dd2..0000000000000 --- a/boards/arm/stm32/photon/src/stm32_spi.c +++ /dev/null @@ -1,186 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/photon/src/stm32_spi.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include - -#include -#include - -#include "arm_internal.h" -#include "chip.h" -#include "stm32.h" - -#include "photon.h" - -#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || defined(CONFIG_STM32_SPI3) - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_spidev_initialize - * - * Description: - * Called to configure SPI chip select GPIO pins for the Mikroe Clicker2 - * STM32 board. - * - ****************************************************************************/ - -void weak_function stm32_spidev_initialize(void) -{ -} - -/**************************************************************************** - * Name: stm32_spi1/2/3select and stm32_spi1/2/3status - * - * Description: - * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status - * must be provided by board-specific logic. They are implementations of - * the select and status methods of the SPI interface defined by struct - * spi_ops_s (see include/nuttx/spi/spi.h). All other methods (including - * stm32_spibus_initialize()) are provided by common STM32 logic. - * To use this common SPI logic on your board: - * - * 1. Provide logic in stm32_boardinitialize() to configure SPI chip select - * pins. - * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() functions - * in your board-specific logic. These functions will perform chip - * selection and status operations using GPIOs in the way your board is - * configured. - * 3. Add a calls to stm32_spibus_initialize() in your low level - * application initialization logic - * 4. The handle returned by stm32_spibus_initialize() may then be used to - * bind the SPI driver to higher level logic (e.g., calling - * mmcsd_spislotinitialize(), for example, will bind the SPI driver to - * the SPI MMC/SD driver). - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_SPI1 -void stm32_spi1select(struct spi_dev_s *dev, - uint32_t devid, bool selected) -{ - spiinfo("devid: %d CS: %s\n", - (int)devid, selected ? "assert" : "de-assert"); -} - -uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) -{ - return 0; -} -#endif - -#ifdef CONFIG_STM32_SPI2 -void stm32_spi2select(struct spi_dev_s *dev, - uint32_t devid, bool selected) -{ - spiinfo("devid: %d CS: %s\n", - (int)devid, selected ? "assert" : "de-assert"); -} - -uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) -{ - return 0; -} -#endif - -#ifdef CONFIG_STM32_SPI3 -void stm32_spi3select(struct spi_dev_s *dev, - uint32_t devid, bool selected) -{ - spiinfo("devid: %d CS: %s\n", - (int)devid, selected ? "assert" : "de-assert"); -} - -uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid) -{ - switch (devid) - { - default: - break; - } - - return 0; -} -#endif - -/**************************************************************************** - * Name: stm32_spi1cmddata - * - * Description: - * Set or clear the SH1101A A0 or SD1306 D/C n bit to select data (true) - * or command (false). This function must be provided by platform-specific - * logic. This is an implementation of the cmddata method of the SPI - * interface defined by struct spi_ops_s (see include/nuttx/spi/spi.h). - * - * Input Parameters: - * - * spi - SPI device that controls the bus the device that requires the CMD/ - * DATA selection. - * devid - If there are multiple devices on the bus, this selects which one - * to select cmd or data. NOTE: This design restricts, for example, - * one one SPI display per SPI bus. - * cmd - true: select command; false: select data - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef CONFIG_SPI_CMDDATA -#ifdef CONFIG_STM32_SPI1 -int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) -{ - return -ENODEV; -} -#endif - -#ifdef CONFIG_STM32_SPI2 -int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) -{ - /* To be provided */ - - return -ENODEV; -} -#endif - -#ifdef CONFIG_STM32_SPI3 -int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) -{ - /* To be provided */ - - return -ENODEV; -} -#endif -#endif /* CONFIG_SPI_CMDDATA */ - -#endif /* CONFIG_STM32_SPI1 || CONFIG_STM32_SPI2 */ diff --git a/boards/arm/stm32/photon/src/stm32_usb.c b/boards/arm/stm32/photon/src/stm32_usb.c deleted file mode 100644 index d8f5862485465..0000000000000 --- a/boards/arm/stm32/photon/src/stm32_usb.c +++ /dev/null @@ -1,68 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/photon/src/stm32_usb.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include "photon.h" -#include - -#include -#include - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_usbinitialize - * - * Description: - * Called from stm32_usbinitialize very early in initialization to setup - * USB-related GPIO pins for the Photon board. - * - ****************************************************************************/ - -void stm32_usbinitialize(void) -{ -} - -/**************************************************************************** - * Name: stm32_usbsuspend - * - * Description: - * Board logic must provide the stm32_usbsuspend logic if the USBDEV driver - * is used. - * This function is called whenever the USB enters or leaves suspend mode. - * This is an opportunity for the board logic to shutdown clocks, power, - * etc. while the USB is suspended. - * - ****************************************************************************/ - -#ifdef CONFIG_USBDEV -void stm32_usbsuspend(struct usbdev_s *dev, bool resume) -{ - uinfo("resume: %d\n", resume); -} -#endif diff --git a/boards/arm/stm32/photon/src/stm32_userleds.c b/boards/arm/stm32/photon/src/stm32_userleds.c deleted file mode 100644 index 1d78b7ecd2ab6..0000000000000 --- a/boards/arm/stm32/photon/src/stm32_userleds.c +++ /dev/null @@ -1,74 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/photon/src/stm32_userleds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include - -#include -#include "photon.h" - -#include "stm32_gpio.h" - -#ifndef CONFIG_ARCH_LEDS - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_userled_initialize - ****************************************************************************/ - -uint32_t board_userled_initialize(void) -{ - /* Configure Photon LED gpio as output */ - - stm32_configgpio(GPIO_LED1); - return BOARD_NLEDS; -} - -/**************************************************************************** - * Name: board_userled - ****************************************************************************/ - -void board_userled(int led, bool ledon) -{ - if (led == BOARD_LED1) - { - stm32_gpiowrite(GPIO_LED1, ledon); - } -} - -/**************************************************************************** - * Name: board_userled_all - ****************************************************************************/ - -void board_userled_all(uint32_t ledset) -{ - stm32_gpiowrite(GPIO_LED1, !!(ledset & BOARD_LED1_BIT)); -} - -#endif /* !CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/photon/src/stm32_wlan.c b/boards/arm/stm32/photon/src/stm32_wlan.c deleted file mode 100644 index 2c0edcbca37d5..0000000000000 --- a/boards/arm/stm32/photon/src/stm32_wlan.c +++ /dev/null @@ -1,157 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/photon/src/stm32_wlan.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include -#include - -#include - -#include "stm32_gpio.h" -#include "stm32_sdio.h" - -#include "photon.h" - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -static struct sdio_dev_s *g_sdio_dev; - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: bcmf_board_reset - ****************************************************************************/ - -void bcmf_board_reset(int minor, bool reset) -{ - if (minor != SDIO_WLAN0_MINOR) - { - return; - } - - stm32_gpiowrite(GPIO_WLAN0_RESET, !reset); -} - -/**************************************************************************** - * Name: bcmf_board_power - ****************************************************************************/ - -void bcmf_board_power(int minor, bool power) -{ - /* Power signal is not used on Photon board */ -} - -/**************************************************************************** - * Name: bcmf_board_initialize - ****************************************************************************/ - -void bcmf_board_initialize(int minor) -{ - if (minor != SDIO_WLAN0_MINOR) - { - return; - } - - /* Configure reset pin */ - - stm32_configgpio(GPIO_WLAN0_RESET); - - /* Put wlan chip in reset state */ - - bcmf_board_reset(minor, true); -} - -/**************************************************************************** - * Name: bcmf_board_setup_oob_irq - ****************************************************************************/ - -void bcmf_board_setup_oob_irq(int minor, int (*func)(void *), void *arg) -{ - if (minor != SDIO_WLAN0_MINOR) - { - return; - } - - /* Configure SDIO card in-band interrupt callback */ - - if (g_sdio_dev != NULL) - { - sdio_set_sdio_card_isr(g_sdio_dev, func, arg); - } -} - -/**************************************************************************** - * Name: bcmf_board_etheraddr - ****************************************************************************/ - -bool bcmf_board_etheraddr(struct ether_addr *ethaddr) -{ - return false; -} - -/**************************************************************************** - * Name: photon_wlan_initialize - ****************************************************************************/ - -int photon_wlan_initialize() -{ - int ret; - - /* Initialize sdio interface */ - - wlinfo("Initializing SDIO slot %d\n", SDIO_WLAN0_SLOTNO); - - g_sdio_dev = sdio_initialize(SDIO_WLAN0_SLOTNO); - - if (!g_sdio_dev) - { - wlerr("ERROR: Failed to initialize SDIO with slot %d\n", - SDIO_WLAN0_SLOTNO); - return ERROR; - } - - /* Bind the SDIO interface to the bcmf driver */ - - ret = bcmf_sdio_initialize(SDIO_WLAN0_MINOR, g_sdio_dev); - - if (ret != OK) - { - wlerr("ERROR: Failed to bind SDIO to bcmf driver\n"); - - /* FIXME deinitialize sdio device */ - - return ERROR; - } - - return OK; -} diff --git a/boards/arm/stm32/shenzhou/CMakeLists.txt b/boards/arm/stm32/shenzhou/CMakeLists.txt deleted file mode 100644 index afc3a6116339b..0000000000000 --- a/boards/arm/stm32/shenzhou/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/shenzhou/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32/shenzhou/configs/nsh/defconfig b/boards/arm/stm32/shenzhou/configs/nsh/defconfig deleted file mode 100644 index 3cad521d66645..0000000000000 --- a/boards/arm/stm32/shenzhou/configs/nsh/defconfig +++ /dev/null @@ -1,76 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_NSH_DISABLE_IFCONFIG is not set -# CONFIG_NSH_DISABLE_PS is not set -# CONFIG_SPI_CALLBACK is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="shenzhou" -CONFIG_ARCH_BOARD_SHENZHOU=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F107VC=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=5483 -CONFIG_BUILTIN=y -CONFIG_ETH0_PHY_DM9161=y -CONFIG_FAT_LCNAMES=y -CONFIG_FAT_LFN=y -CONFIG_FS_FAT=y -CONFIG_HAVE_CXX=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_MMCSD=y -CONFIG_MMCSD_SPICLOCK=12500000 -CONFIG_NET=y -CONFIG_NETDB_DNSCLIENT=y -CONFIG_NETDB_DNSSERVER_NOADDR=y -CONFIG_NETINIT_NOMAC=y -CONFIG_NETUTILS_TELNETD=y -CONFIG_NETUTILS_TFTPC=y -CONFIG_NETUTILS_WEBCLIENT=y -CONFIG_NET_ICMP_SOCKET=y -CONFIG_NET_MAX_LISTENPORTS=40 -CONFIG_NET_STATISTICS=y -CONFIG_NET_TCP=y -CONFIG_NET_TCP_PREALLOC_CONNS=40 -CONFIG_NET_UDP=y -CONFIG_NET_UDP_CHECKSUMS=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_MMCSDSPIPORTNO=1 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=65536 -CONFIG_RAM_START=0x20000000 -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_WAITPID=y -CONFIG_STM32_BKP=y -CONFIG_STM32_ETHMAC=y -CONFIG_STM32_ETH_REMAP=y -CONFIG_STM32_JTAG_FULL_ENABLE=y -CONFIG_STM32_PHYADDR=0 -CONFIG_STM32_PHYSR=17 -CONFIG_STM32_PHYSR_100FD=0x8000 -CONFIG_STM32_PHYSR_100HD=0x4000 -CONFIG_STM32_PHYSR_10FD=0x2000 -CONFIG_STM32_PHYSR_10HD=0x1000 -CONFIG_STM32_PHYSR_ALTCONFIG=y -CONFIG_STM32_PHYSR_ALTMODE=0xf000 -CONFIG_STM32_PWR=y -CONFIG_STM32_RTC=y -CONFIG_STM32_SPI1=y -CONFIG_STM32_USART2=y -CONFIG_STM32_USART2_REMAP=y -CONFIG_SYSTEM_NSH=y -CONFIG_SYSTEM_PING=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART2_RXBUFSIZE=128 -CONFIG_USART2_SERIAL_CONSOLE=y -CONFIG_USART2_TXBUFSIZE=128 diff --git a/boards/arm/stm32/shenzhou/configs/nxwm/defconfig b/boards/arm/stm32/shenzhou/configs/nxwm/defconfig deleted file mode 100644 index 815572c9038c3..0000000000000 --- a/boards/arm/stm32/shenzhou/configs/nxwm/defconfig +++ /dev/null @@ -1,125 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -# CONFIG_NSH_DISABLE_IFCONFIG is not set -# CONFIG_NSH_DISABLE_PS is not set -# CONFIG_NXFONTS_DISABLE_16BPP is not set -# CONFIG_NXTK_DEFAULT_BORDERCOLORS is not set -# CONFIG_NX_DISABLE_16BPP is not set -# CONFIG_NX_PACKEDMSFIRST is not set -CONFIG_ADS7843E_SPIDEV=3 -CONFIG_ADS7843E_SWAPXY=y -CONFIG_ADS7843E_THRESHX=39 -CONFIG_ADS7843E_THRESHY=51 -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="shenzhou" -CONFIG_ARCH_BOARD_SHENZHOU=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F107VC=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=5483 -CONFIG_ETH0_PHY_DM9161=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_HOST_WINDOWS=y -CONFIG_INIT_ENTRYPOINT="nxwm_main" -CONFIG_INIT_STACKSIZE=1024 -CONFIG_INPUT=y -CONFIG_INPUT_ADS7843E=y -CONFIG_INTELHEX_BINARY=y -CONFIG_LCD=y -CONFIG_LCD_MAXCONTRAST=1 -CONFIG_LCD_NOGETRUN=y -CONFIG_LCD_SSD1289=y -CONFIG_LIBC_MAX_EXITFUNS=1 -CONFIG_LINE_MAX=64 -CONFIG_MQ_MAXMSGSIZE=64 -CONFIG_NET=y -CONFIG_NETDB_DNSCLIENT=y -CONFIG_NETDB_DNSCLIENT_ENTRIES=4 -CONFIG_NETDB_DNSSERVER_NOADDR=y -CONFIG_NETINIT_NOMAC=y -CONFIG_NETUTILS_TELNETD=y -CONFIG_NETUTILS_TFTPC=y -CONFIG_NETUTILS_WEBCLIENT=y -CONFIG_NET_ICMP_SOCKET=y -CONFIG_NET_MAX_LISTENPORTS=16 -CONFIG_NET_STATISTICS=y -CONFIG_NET_TCP=y -CONFIG_NET_TCP_PREALLOC_CONNS=16 -CONFIG_NET_UDP=y -CONFIG_NET_UDP_CHECKSUMS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_LIBRARY=y -CONFIG_NSH_READLINE=y -CONFIG_NX=y -CONFIG_NXFONT_SANS22X29B=y -CONFIG_NXFONT_SANS23X27=y -CONFIG_NXTERM=y -CONFIG_NXTERM_CACHESIZE=32 -CONFIG_NXTERM_CURSORCHAR=95 -CONFIG_NXTERM_MXCHARS=325 -CONFIG_NXTERM_NXKBDIN=y -CONFIG_NXTK_BORDERCOLOR1=0x5cb7 -CONFIG_NXTK_BORDERCOLOR2=0x21c9 -CONFIG_NXTK_BORDERCOLOR3=0xffdf -CONFIG_NXWIDGETS=y -CONFIG_NXWIDGETS_BPP=16 -CONFIG_NXWIDGETS_LISTENERSTACK=1596 -CONFIG_NXWIDGETS_SIZEOFCHAR=1 -CONFIG_NXWM=y -CONFIG_NXWM_BACKGROUND_IMAGE="" -CONFIG_NXWM_CALIBRATION_LISTENERSTACK=1024 -CONFIG_NXWM_HEXCALCULATOR_CUSTOM_FONTID=y -CONFIG_NXWM_HEXCALCULATOR_FONTID=5 -CONFIG_NXWM_KEYBOARD=y -CONFIG_NXWM_KEYBOARD_LISTENERPRIO=100 -CONFIG_NXWM_KEYBOARD_LISTENERSTACK=1024 -CONFIG_NXWM_NXTERM_STACKSIZE=1596 -CONFIG_NXWM_STARTWINDOW_STACKSIZE=1596 -CONFIG_NXWM_TASKBAR_LEFT=y -CONFIG_NXWM_TASKBAR_VSPACING=4 -CONFIG_NXWM_TOUCHSCREEN_LISTENERPRIO=101 -CONFIG_NXWM_TOUCHSCREEN_LISTENERSTACK=1596 -CONFIG_NX_BLOCKING=y -CONFIG_NX_KBD=y -CONFIG_NX_XYINPUT_TOUCHSCREEN=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_PTHREAD_STACK_DEFAULT=1024 -CONFIG_RAM_SIZE=65536 -CONFIG_RAM_START=0x20000000 -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_HPWORKPRIORITY=192 -CONFIG_SCHED_HPWORKSTACKSIZE=1024 -CONFIG_START_DAY=26 -CONFIG_START_MONTH=9 -CONFIG_START_YEAR=2012 -CONFIG_STM32_ETHMAC=y -CONFIG_STM32_ETH_REMAP=y -CONFIG_STM32_JTAG_FULL_ENABLE=y -CONFIG_STM32_PHYADDR=0 -CONFIG_STM32_PHYSR=17 -CONFIG_STM32_PHYSR_100FD=0x8000 -CONFIG_STM32_PHYSR_100HD=0x4000 -CONFIG_STM32_PHYSR_10FD=0x2000 -CONFIG_STM32_PHYSR_10HD=0x1000 -CONFIG_STM32_PHYSR_ALTCONFIG=y -CONFIG_STM32_PHYSR_ALTMODE=0xf000 -CONFIG_STM32_SPI3=y -CONFIG_STM32_SPI3_REMAP=y -CONFIG_STM32_USART2=y -CONFIG_STM32_USART2_REMAP=y -CONFIG_SYSTEM_PING=y -CONFIG_SYSTEM_TELNETD_SESSION_STACKSIZE=1596 -CONFIG_SYSTEM_TELNETD_STACKSIZE=1596 -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART2_RXBUFSIZE=128 -CONFIG_USART2_SERIAL_CONSOLE=y -CONFIG_USART2_TXBUFSIZE=128 diff --git a/boards/arm/stm32/shenzhou/configs/thttpd/defconfig b/boards/arm/stm32/shenzhou/configs/thttpd/defconfig deleted file mode 100644 index 7a6bad14a95a7..0000000000000 --- a/boards/arm/stm32/shenzhou/configs/thttpd/defconfig +++ /dev/null @@ -1,89 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_NSH_DISABLE_IFCONFIG is not set -# CONFIG_NSH_DISABLE_PS is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="shenzhou" -CONFIG_ARCH_BOARD_SHENZHOU=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F107VC=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_ARM_TOOLCHAIN_BUILDROOT=y -CONFIG_BOARD_LOOPSPERMSEC=5483 -CONFIG_BUILTIN=y -CONFIG_ETH0_PHY_DM9161=y -CONFIG_EXAMPLES_THTTPD=y -CONFIG_EXAMPLES_THTTPD_DRIPADDR=0xc0a80001 -CONFIG_EXAMPLES_THTTPD_NOMAC=y -CONFIG_FS_NXFFS=y -CONFIG_FS_ROMFS=y -CONFIG_HAVE_CXX=y -CONFIG_INIT_ENTRYPOINT="thttp_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_MTD=y -CONFIG_MTD_W25=y -CONFIG_NET=y -CONFIG_NETDB_DNSCLIENT=y -CONFIG_NETDB_DNSSERVER_NOADDR=y -CONFIG_NETINIT_DRIPADDR=0xc0a80001 -CONFIG_NETINIT_IPADDR=0xc0a80032 -CONFIG_NETINIT_NOMAC=y -CONFIG_NETUTILS_TELNETD=y -CONFIG_NETUTILS_TFTPC=y -CONFIG_NETUTILS_THTTPD=y -CONFIG_NETUTILS_WEBCLIENT=y -CONFIG_NET_BROADCAST=y -CONFIG_NET_ETH_PKTSIZE=768 -CONFIG_NET_ICMP_SOCKET=y -CONFIG_NET_MAX_LISTENPORTS=40 -CONFIG_NET_STATISTICS=y -CONFIG_NET_TCP=y -CONFIG_NET_TCP_PREALLOC_CONNS=40 -CONFIG_NET_UDP=y -CONFIG_NET_UDP_CHECKSUMS=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_NXFLAT=y -CONFIG_PIPES=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=65536 -CONFIG_RAM_START=0x20000000 -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_WAITPID=y -CONFIG_STM32_BKP=y -CONFIG_STM32_ETHMAC=y -CONFIG_STM32_ETH_REMAP=y -CONFIG_STM32_JTAG_FULL_ENABLE=y -CONFIG_STM32_PHYSR=17 -CONFIG_STM32_PHYSR_100FD=0x8000 -CONFIG_STM32_PHYSR_100HD=0x4000 -CONFIG_STM32_PHYSR_10FD=0x2000 -CONFIG_STM32_PHYSR_10HD=0x1000 -CONFIG_STM32_PHYSR_ALTCONFIG=y -CONFIG_STM32_PHYSR_ALTMODE=0xf000 -CONFIG_STM32_PWR=y -CONFIG_STM32_RTC=y -CONFIG_STM32_SPI1=y -CONFIG_STM32_USART2=y -CONFIG_STM32_USART2_REMAP=y -CONFIG_SYMTAB_ORDEREDBYNAME=y -CONFIG_SYSTEM_NSH=y -CONFIG_SYSTEM_PING=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_THTTPD_CGI_BYTECOUNT=20000 -CONFIG_THTTPD_CGI_PRIORITY=50 -CONFIG_THTTPD_CGI_STACKSIZE=1024 -CONFIG_THTTPD_IOBUFFERSIZE=1024 -CONFIG_THTTPD_IPADDR=0xc0a80032 -CONFIG_USART2_RXBUFSIZE=128 -CONFIG_USART2_SERIAL_CONSOLE=y -CONFIG_USART2_TXBUFSIZE=128 diff --git a/boards/arm/stm32/shenzhou/include/board.h b/boards/arm/stm32/shenzhou/include/board.h deleted file mode 100644 index 394f305ee9868..0000000000000 --- a/boards/arm/stm32/shenzhou/include/board.h +++ /dev/null @@ -1,463 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/shenzhou/include/board.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __BOARDS_ARM_STM32_SHENZHOU_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32_SHENZHOU_INCLUDE_BOARD_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#ifndef __ASSEMBLY__ -# include -#endif - -#include - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Clocking *****************************************************************/ - -/* HSI - 8 MHz RC factory-trimmed - * LSI - 40 KHz RC (30-60KHz, uncalibrated) - * HSE - On-board crystal frequency is 25MHz - * LSE - 32.768 kHz - */ - -#define STM32_BOARD_XTAL 25000000ul - -#define STM32_HSI_FREQUENCY 8000000ul -#define STM32_LSI_FREQUENCY 40000 -#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL -#define STM32_LSE_FREQUENCY 32768 - -/* PLL output is 72MHz */ - -#define STM32_PLL_PREDIV2 RCC_CFGR2_PREDIV2d5 /* 25MHz / 5 => 5MHz */ -#define STM32_PLL_PLL2MUL RCC_CFGR2_PLL2MULx8 /* 5MHz * 8 => 40MHz */ -#define STM32_PLL_PREDIV1 RCC_CFGR2_PREDIV1d5 /* 40MHz / 5 => 8MHz */ -#define STM32_PLL_PLLMUL RCC_CFGR_PLLMUL_CLKx9 /* 8MHz * 9 => 72Mhz */ -#define STM32_PLL_FREQUENCY (72000000) - -/* SYCLLK and HCLK are the PLL frequency */ - -#define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY -#define STM32_HCLK_FREQUENCY STM32_PLL_FREQUENCY - -/* APB2 clock (PCLK2) is HCLK (72MHz) */ - -#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK -#define STM32_PCLK2_FREQUENCY STM32_HCLK_FREQUENCY -#define STM32_APB2_CLKIN (STM32_PCLK2_FREQUENCY) /* Timers 2-7, 12-14 */ - -/* APB2 timers 1 and 8 will receive PCLK2. */ - -#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) - -/* APB1 clock (PCLK1) is HCLK/2 (36MHz) */ - -#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd2 -#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/2) - -/* APB1 timers 2-7 will be twice PCLK1 */ - -#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) - -/* MCO output driven by PLL3. - * From above, we already have PLL3 input frequency as: - * - * STM32_PLL_PREDIV2 = 5, 25MHz / 5 => 5MHz - */ - -#if defined(CONFIG_STM32_MII_MCO) || defined(CONFIG_STM32_RMII_MCO) -# define BOARD_CFGR_MCO_SOURCE RCC_CFGR_PLL3CLK /* Source: PLL3 */ -# define STM32_PLL_PLL3MUL RCC_CFGR2_PLL3MULx10 /* MCO 5MHz * 10 = 50MHz */ -#endif - -/* LED definitions **********************************************************/ - -/* If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs in - * any way. The following definitions are used to access individual LEDs. - */ - -/* LED index values for use with board_userled() */ - -#define BOARD_LED1 0 -#define BOARD_LED2 1 -#define BOARD_LED3 2 -#define BOARD_LED4 3 -#define BOARD_NLEDS 4 - -/* LED bits for use with board_userled_all() */ - -#define BOARD_LED1_BIT (1 << BOARD_LED1) -#define BOARD_LED2_BIT (1 << BOARD_LED2) -#define BOARD_LED3_BIT (1 << BOARD_LED3) -#define BOARD_LED4_BIT (1 << BOARD_LED4) - -/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the 4 LEDs on - * board the STM3240G-EVAL. - * The following definitions describe how NuttX controls the LEDs: - */ - -#define LED_STARTED 0 /* LED1 */ -#define LED_HEAPALLOCATE 1 /* LED2 */ -#define LED_IRQSENABLED 2 /* LED1 + LED2 */ -#define LED_STACKCREATED 3 /* LED3 */ -#define LED_INIRQ 4 /* LED1 + LED3 */ -#define LED_SIGNAL 5 /* LED2 + LED3 */ -#define LED_ASSERTION 6 /* LED1 + LED2 + LED3 */ -#define LED_PANIC 7 /* N/C + N/C + N/C + LED4 */ - -/* Button definitions *******************************************************/ - -/* The STM3240G-EVAL supports three buttons: */ - -#define BUTTON_KEY1 0 /* Name printed on board */ -#define BUTTON_KEY2 1 -#define BUTTON_KEY3 2 -#define BUTTON_KEY4 3 -#define NUM_BUTTONS 4 - -#define BUTTON_USERKEY2 BUTTON_KEY1 /* Names in schematic */ -#define BUTTON_USERKEY BUTTON_KEY2 -#define BUTTON_TAMPER BUTTON_KEY3 -#define BUTTON_WAKEUP BUTTON_KEY4 - -#define BUTTON_KEY1_BIT (1 << BUTTON_KEY1) -#define BUTTON_KEY2_BIT (1 << BUTTON_KEY2) -#define BUTTON_KEY3_BIT (1 << BUTTON_KEY3) -#define BUTTON_KEY4_BIT (1 << BUTTON_KEY4) - -#define BUTTON_USERKEY2_BIT BUTTON_KEY1_BIT -#define BUTTON_USERKEY_BIT BUTTON_KEY2_BIT -#define BUTTON_TAMPER_BIT BUTTON_KEY3_BIT -#define BUTTON_WAKEUP_BIT BUTTON_KEY4_BIT - -/* Relays */ - -#define NUM_RELAYS 2 - -/* Pin selections ***********************************************************/ - -/* Ethernet - * - * -- ---- -------------- --------------------------------------------------- - * PN NAME SIGNAL NOTES - * -- ---- -------------- --------------------------------------------------- - * 24 PA1 MII_RX_CLK Ethernet PHY NOTE: Despite the MII labeling of - * RMII_REF_CLK Ethernet PHY these signals, the DM916AEP is - * 25 PA2 MII_MDIO Ethernet PHY actually configured to work in RMII - * 48 PB11 MII_TX_EN Ethernet PHY mode. - * 51 PB12 MII_TXD0 Ethernet PHY - * 52 PB13 MII_TXD1 Ethernet PHY - * 16 PC1 MII_MDC Ethernet PHY - * 34 PC5 MII_INT Ethernet PHY - * 55 PD8 MII_RX_DV Ethernet PHY. Requires CONFIG_STM32_ETH_REMAP - * 55 PD8 RMII_CRSDV Ethernet PHY. Requires CONFIG_STM32_ETH_REMAP - * 56 PD9 MII_RXD0 Ethernet PHY. Requires CONFIG_STM32_ETH_REMAP - * 57 PD10 MII_RXD1 Ethernet PHY. Requires CONFIG_STM32_ETH_REMAP - * - * The board desdign can support a 50MHz external clock to drive the PHY - * (U9). However, on my board, U9 is not present. - * - * 67 PA8 MCO DM9161AEP - */ - -#ifdef CONFIG_STM32_ETHMAC -# ifndef CONFIG_STM32_ETH_REMAP -# error "STM32 Ethernet requires CONFIG_STM32_ETH_REMAP" -# endif -# ifndef CONFIG_STM32_RMII -# error "STM32 Ethernet requires CONFIG_STM32_RMII" -# endif -# ifndef CONFIG_STM32_RMII_MCO -# error "STM32 Ethernet requires CONFIG_STM32_RMII_MCO" -# endif -#endif - -/* USB - * - * -- ---- -------------- --------------------------------------------------- - * PN NAME SIGNAL NOTES - * -- ---- -------------- --------------------------------------------------- - * 68 PA9 USB_VBUS MINI-USB-AB. JP3 - * 69 PA10 USB_ID MINI-USB-AB. JP5 - * 70 PA11 USB_DM MINI-USB-AB - * 71 PA12 USB_DP MINI-USB-AB - * 95 PB8 USB_PWR Drives USB VBUS - */ - -/* UARTS/USARTS - * - * -- ---- -------------- --------------------------------------------------- - * PN NAME SIGNAL NOTES - * -- ---- -------------- --------------------------------------------------- - * 68 PA9 USART1_TX MAX3232 to CN5. Requires CONFIG_STM32_USART1_REMAP - * 69 PA10 USART1_RX MAX3232 to CN5. Requires CONFIG_STM32_USART1_REMAP - * 86 PD5 USART2_TX MAX3232 to CN6. Requires CONFIG_STM32_USART2_REMAP - * 87 PD6 USART2_RX MAX3232 to CN6. Requires CONFIG_STM32_USART2_REMAP - * 86 PD5 485_TX Same as USART2_TX but goes to SP3485 - * 87 PD6 485_RX Save as USART2_RX but goes to SP3485 (see JP4) - */ - -#if defined(CONFIG_STM32_USART1) && !defined(CONFIG_STM32_USART1_REMAP) -# error "CONFIG_STM32_USART1 requires CONFIG_STM32_USART1_REMAP" -#endif - -#if defined(CONFIG_STM32_USART2) && !defined(CONFIG_STM32_USART2_REMAP) -# error "CONFIG_STM32_USART2 requires CONFIG_STM32_USART2_REMAP" -#endif - -/* SPI - * - * -- ---- -------------- --------------------------------------------------- - * PN NAME SIGNAL NOTES - * -- ---- -------------- --------------------------------------------------- - * 30 PA5 SPI1_SCK To the SD card, SPI FLASH. - * Requires !CONFIG_STM32_SPI1_REMAP - * 31 PA6 SPI1_MISO To the SD card, SPI FLASH. - * Requires !CONFIG_STM32_SPI1_REMAP - * 32 PA7 SPI1_MOSI To the SD card, SPI FLASH. - * Requires !CONFIG_STM32_SPI1_REMAP - * 78 PC10 SPI3_SCK To TFT LCD (CN13), - * the NRF24L01 2.4G wireless module. - * Requires CONFIG_STM32_SPI3_REMAP. - * 79 PC11 SPI3_MISO To TFT LCD (CN13), - * the NRF24L01 2.4G wireless module. - * Requires CONFIG_STM32_SPI3_REMAP. - * 80 PC12 SPI3_MOSI To TFT LCD (CN13), - * the NRF24L01 2.4G wireless module. - * Requires CONFIG_STM32_SPI3_REMAP. - */ - -#if defined(CONFIG_STM32_SPI1) && defined(CONFIG_STM32_SPI1_REMAP) -# error "CONFIG_STM32_SPI1 must not have CONFIG_STM32_SPI1_REMAP" -#endif - -#if defined(CONFIG_STM32_SPI3) && !defined(CONFIG_STM32_SPI3_REMAP) -# error "CONFIG_STM32_SPI3 requires CONFIG_STM32_SPI3_REMAP" -#endif - -/* DAC - * - * -- ---- -------------- --------------------------------------------------- - * PN NAME SIGNAL NOTES - * -- ---- -------------- --------------------------------------------------- - * 29 PA4 DAC_OUT1 To CON5(CN14) - * 30 PA5 DAC_OUT2 To CON5(CN14). JP10 - */ - -/* ADC - * - * -- ---- -------------- --------------------------------------------------- - * PN NAME SIGNAL NOTES - * -- ---- -------------- --------------------------------------------------- - * 35 PB0 ADC_IN1 GPIO_ADC12_IN8. To CON5(CN14) - * 36 PB1 ADC_IN2 GPIO_ADC12_IN9. To CON5(CN14) - * 15 PC0 POTENTIO_METER GPIO_ADC12_IN10 - */ - -/* CAN - * - * -- ---- -------------- --------------------------------------------------- - * PN NAME SIGNAL NOTES - * -- ---- -------------- --------------------------------------------------- - * 91 PB5 CAN2_RX Requires CONFIG_STM32_CAN2_REMAP. - * 92 PB6 CAN2_TX Requires CONFIG_STM32_CAN2_REMAP. See also JP11 - * 81 PD0 CAN1_RX Requires CONFIG_STM32_CAN1_REMAP2. - * 82 PD1 CAN1_TX Requires CONFIG_STM32_CAN1_REMAP2. - */ - -#if defined(CONFIG_STM32_CAN1) && !defined(CONFIG_STM32_CAN1_REMAP2) -# error "CONFIG_STM32_CAN1 requires CONFIG_STM32_CAN1_REMAP2" -#endif - -#if defined(CONFIG_STM32_CAN2) && !defined(CONFIG_STM32_CAN2_REMAP) -# error "CONFIG_STM32_CAN2 requires CONFIG_STM32_CAN2_REMAP" -#endif - -/* I2C - * - * -- ---- -------------- --------------------------------------------------- - * PN NAME SIGNAL NOTES - * -- ---- -------------- --------------------------------------------------- - * 92 PB6 I2C1_SCL Requires !CONFIG_STM32_I2C1_REMAP - * 93 PB7 I2C1_SDA - */ - -#if defined(CONFIG_STM32_I2C1) && defined(CONFIG_STM32_I2C1_REMAP) -# error "CONFIG_STM32_I2C1 must not have CONFIG_STM32_I2C1_REMAP" -#endif - -/* I2S - * - * -- ---- -------------- --------------------------------------------------- - * PN NAME SIGNAL NOTES - * -- ---- -------------- --------------------------------------------------- - * 51 PB12 I2S_WS GPIO_I2S2_WS. Audio DAC - * 52 PB13 I2S_CK GPIO_I2S2_CK. Audio DAC - * 54 PB15 I2S_DIN ??? Audio DAC data in. - * 63 PC6 I2S_MCK GPIO_I2S2_MCK. Audio DAC. Active low: Pulled high - */ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -#ifndef __ASSEMBLY__ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_lcdclear - * - * Description: - * This is a non-standard LCD interface just for the Shenzhou board. - * Because of the various rotations, clearing the display in the normal way - * by writing a sequences of runs that covers the entire display can be - * very slow. Here the display is cleared by simply setting all GRAM - * memory to the specified color. - * - ****************************************************************************/ - -void stm32_lcdclear(uint16_t color); - -/**************************************************************************** - * Relay control functions - * - * Description: - * Non-standard functions for relay control from the Shenzhou board. - * - * NOTE: These must match the prototypes in include/nuttx/arch.h - * - ****************************************************************************/ - -#ifdef CONFIG_ARCH_RELAYS -void up_relaysinit(void); -void relays_setstat(int relays, bool stat); -bool relays_getstat(int relays); -void relays_setstats(uint32_t relays_stat); -uint32_t relays_getstats(void); -void relays_onoff(int relays, uint32_t mdelay); -void relays_onoffs(uint32_t relays_stat, uint32_t mdelay); -void relays_resetmode(int relays); -void relays_powermode(int relays); -void relays_resetmodes(uint32_t relays_stat); -void relays_powermodes(uint32_t relays_stat); -#endif - -/**************************************************************************** - * Chip ID functions - * - * Description: - * Non-standard functions to obtain chip ID information. - * - ****************************************************************************/ - -const char *stm32_getchipid(void); -const char *stm32_getchipid_string(void); - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ - -/* Alternate function pin selections (auto-aliased for new pinmap) */ - -/* USART2 */ - -#define GPIO_USART2_TX GPIO_ADJUST_MODE(GPIO_USART2_TX_0, GPIO_MODE_50MHz) -#define GPIO_USART2_RX GPIO_USART2_RX_0 -#define GPIO_USART2_CTS GPIO_USART2_CTS_0 -#define GPIO_USART2_RTS GPIO_ADJUST_MODE(GPIO_USART2_RTS_0, GPIO_MODE_50MHz) -#define GPIO_USART2_CK GPIO_ADJUST_MODE(GPIO_USART2_CK_0, GPIO_MODE_50MHz) - -/* SPI1 */ - -#define GPIO_SPI1_NSS GPIO_ADJUST_MODE(GPIO_SPI1_NSS_0, GPIO_MODE_50MHz) -#define GPIO_SPI1_SCK GPIO_ADJUST_MODE(GPIO_SPI1_SCK_0, GPIO_MODE_50MHz) -#define GPIO_SPI1_MISO GPIO_ADJUST_MODE(GPIO_SPI1_MISO_0, GPIO_MODE_50MHz) -#define GPIO_SPI1_MOSI GPIO_ADJUST_MODE(GPIO_SPI1_MOSI_0, GPIO_MODE_50MHz) - -/* SPI3 */ - -#define GPIO_SPI3_NSS GPIO_ADJUST_MODE(GPIO_SPI3_NSS_0, GPIO_MODE_50MHz) -#define GPIO_SPI3_SCK GPIO_ADJUST_MODE(GPIO_SPI3_SCK_0, GPIO_MODE_50MHz) -#define GPIO_SPI3_MISO GPIO_ADJUST_MODE(GPIO_SPI3_MISO_0, GPIO_MODE_50MHz) -#define GPIO_SPI3_MOSI GPIO_ADJUST_MODE(GPIO_SPI3_MOSI_0, GPIO_MODE_50MHz) - -/* MCO */ - -#define GPIO_MCO GPIO_ADJUST_MODE(GPIO_MCO_0, GPIO_MODE_50MHz) - -/* Ethernet (MII/RMII) */ - -#define GPIO_ETH_MDC GPIO_ADJUST_MODE(GPIO_ETH_MDC_0, GPIO_MODE_50MHz) -#define GPIO_ETH_MDIO GPIO_ADJUST_MODE(GPIO_ETH_MDIO_0, GPIO_MODE_50MHz) -#define GPIO_ETH_MII_COL GPIO_ETH_MII_COL_0 -#define GPIO_ETH_MII_CRS GPIO_ETH_MII_CRS_0 -#define GPIO_ETH_MII_RX_CLK GPIO_ETH_MII_RX_CLK_0 -#define GPIO_ETH_MII_RXD0 GPIO_ETH_MII_RXD0_0 -#define GPIO_ETH_MII_RXD1 GPIO_ETH_MII_RXD1_0 -#define GPIO_ETH_MII_RXD2 GPIO_ETH_MII_RXD2_0 -#define GPIO_ETH_MII_RXD3 GPIO_ETH_MII_RXD3_0 -#define GPIO_ETH_MII_RX_DV GPIO_ETH_MII_RX_DV_0 -#define GPIO_ETH_MII_RX_ER GPIO_ETH_MII_RX_ER_0 -#define GPIO_ETH_MII_TX_CLK GPIO_ETH_MII_TX_CLK_0 -#define GPIO_ETH_MII_TXD0 GPIO_ADJUST_MODE(GPIO_ETH_MII_TXD0_0, GPIO_MODE_50MHz) -#define GPIO_ETH_MII_TXD1 GPIO_ADJUST_MODE(GPIO_ETH_MII_TXD1_0, GPIO_MODE_50MHz) -#define GPIO_ETH_MII_TXD2 GPIO_ADJUST_MODE(GPIO_ETH_MII_TXD2_0, GPIO_MODE_50MHz) -#define GPIO_ETH_MII_TXD3 GPIO_ADJUST_MODE(GPIO_ETH_MII_TXD3_0, GPIO_MODE_50MHz) -#define GPIO_ETH_MII_TX_EN GPIO_ADJUST_MODE(GPIO_ETH_MII_TX_EN_0, GPIO_MODE_50MHz) -#define GPIO_ETH_RMII_CRS_DV GPIO_ETH_RMII_CRS_DV_0 -#define GPIO_ETH_RMII_REF_CLK GPIO_ETH_RMII_REF_CLK_0 -#define GPIO_ETH_RMII_RXD0 GPIO_ETH_RMII_RXD0_0 -#define GPIO_ETH_RMII_RXD1 GPIO_ETH_RMII_RXD1_0 -#define GPIO_ETH_RMII_TXD0 GPIO_ADJUST_MODE(GPIO_ETH_RMII_TXD0_0, GPIO_MODE_50MHz) -#define GPIO_ETH_RMII_TXD1 GPIO_ADJUST_MODE(GPIO_ETH_RMII_TXD1_0, GPIO_MODE_50MHz) -#define GPIO_ETH_RMII_TX_EN GPIO_ADJUST_MODE(GPIO_ETH_RMII_TX_EN_0, GPIO_MODE_50MHz) - -#endif /* __BOARDS_ARM_STM32_SHENZHOU_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32/shenzhou/scripts/Make.defs b/boards/arm/stm32/shenzhou/scripts/Make.defs deleted file mode 100644 index 920c3f3fc2511..0000000000000 --- a/boards/arm/stm32/shenzhou/scripts/Make.defs +++ /dev/null @@ -1,53 +0,0 @@ -############################################################################ -# boards/arm/stm32/shenzhou/scripts/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/.config -include $(TOPDIR)/tools/Config.mk -include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs - -# Pick the linker script - -ifeq ($(CONFIG_STM32_DFU),y) - LDSCRIPT = ld.script.dfu -else - LDSCRIPT = ld.script -endif - -ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) - -MKNXFLAT = mknxflat -LDNXFLAT = ldnxflat - -ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 - -CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) -CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) -CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -AFLAGS := $(CFLAGS) -D__ASSEMBLY__ - -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-gotoff.ld -no-check-sections -#NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections - -LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32/shenzhou/scripts/ld.script b/boards/arm/stm32/shenzhou/scripts/ld.script deleted file mode 100644 index 92929e25eb28c..0000000000000 --- a/boards/arm/stm32/shenzhou/scripts/ld.script +++ /dev/null @@ -1,119 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/shenzhou/scripts/ld.script - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* The STM32F107VC has 256K of FLASH beginning at address 0x0800:0000 and - * 64K of SRAM beginning at address 0x2000:0000. - */ - -MEMORY -{ - flash (rx) : ORIGIN = 0x08000000, LENGTH = 256K - sram (rwx) : ORIGIN = 0x20000000, LENGTH = 64K -} - -OUTPUT_ARCH(arm) -EXTERN(_vectors) -ENTRY(_stext) -SECTIONS -{ - .text : { - _stext = ABSOLUTE(.); - *(.vectors) - *(.text .text.*) - *(.fixup) - *(.gnu.warning) - *(.rodata .rodata.*) - *(.gnu.linkonce.t.*) - *(.glue_7) - *(.glue_7t) - *(.got) - *(.gcc_except_table) - *(.gnu.linkonce.r.*) - _etext = ABSOLUTE(.); - } > flash - - .init_section : ALIGN(4) { - _sinit = ABSOLUTE(.); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) - KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) - _einit = ABSOLUTE(.); - } > flash - - .ARM.extab : ALIGN(4) { - *(.ARM.extab*) - } > flash - - .ARM.exidx : ALIGN(4) { - __exidx_start = ABSOLUTE(.); - *(.ARM.exidx*) - __exidx_end = ABSOLUTE(.); - } > flash - - .tdata : { - _stdata = ABSOLUTE(.); - *(.tdata .tdata.* .gnu.linkonce.td.*); - _etdata = ABSOLUTE(.); - } > flash - - .tbss : { - _stbss = ABSOLUTE(.); - *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); - _etbss = ABSOLUTE(.); - } > flash - - _eronly = ABSOLUTE(.); - - /* The STM32F107VC has 64Kb of SRAM beginning at the following address */ - - .data : ALIGN(4) { - _sdata = ABSOLUTE(.); - *(.data .data.*) - *(.gnu.linkonce.d.*) - CONSTRUCTORS - . = ALIGN(4); - _edata = ABSOLUTE(.); - } > sram AT > flash - - .bss : ALIGN(4) { - _sbss = ABSOLUTE(.); - *(.bss .bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - . = ALIGN(4); - _ebss = ABSOLUTE(.); - } > sram - - /* Stabs debugging sections. */ - - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_info 0 : { *(.debug_info) } - .debug_line 0 : { *(.debug_line) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_aranges 0 : { *(.debug_aranges) } -} diff --git a/boards/arm/stm32/shenzhou/scripts/ld.script.dfu b/boards/arm/stm32/shenzhou/scripts/ld.script.dfu deleted file mode 100644 index 63eb3ea049173..0000000000000 --- a/boards/arm/stm32/shenzhou/scripts/ld.script.dfu +++ /dev/null @@ -1,118 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/shenzhou/scripts/ld.script.dfu - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* The STM32F107VC has 256K of FLASH beginning at address 0x0800:0000 and - * 64K of SRAM beginning at address 0x2000:0000. Here we assume that the - * STMicro DFU bootloader is being used. In that case, the correct load .text - * load address is 0x08003000 (leaving 208K). - */ - -MEMORY -{ - flash (rx) : ORIGIN = 0x08003000, LENGTH = 208K - sram (rwx) : ORIGIN = 0x20000000, LENGTH = 64K -} - -OUTPUT_ARCH(arm) -EXTERN(_vectors) -ENTRY(_stext) -SECTIONS -{ - .text : { - _stext = ABSOLUTE(.); - *(.vectors) - *(.text .text.*) - *(.fixup) - *(.gnu.warning) - *(.rodata .rodata.*) - *(.gnu.linkonce.t.*) - *(.glue_7) - *(.glue_7t) - *(.got) - *(.gcc_except_table) - *(.gnu.linkonce.r.*) - _etext = ABSOLUTE(.); - } > flash - - .init_section : ALIGN(4) { - _sinit = ABSOLUTE(.); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) - KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) - _einit = ABSOLUTE(.); - } > flash - - .ARM.extab : ALIGN(4) { - *(.ARM.extab*) - } > flash - - .ARM.exidx : ALIGN(4) { - __exidx_start = ABSOLUTE(.); - *(.ARM.exidx*) - __exidx_end = ABSOLUTE(.); - } > flash - - .tdata : { - _stdata = ABSOLUTE(.); - *(.tdata .tdata.* .gnu.linkonce.td.*); - _etdata = ABSOLUTE(.); - } > flash - - .tbss : { - _stbss = ABSOLUTE(.); - *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); - _etbss = ABSOLUTE(.); - } > flash - - _eronly = ABSOLUTE(.); - - /* The STM32F107VC has 64Kb of SRAM beginning at the following address */ - - .data : ALIGN(4) { - _sdata = ABSOLUTE(.); - *(.data .data.*) - *(.gnu.linkonce.d.*) - CONSTRUCTORS - _edata = ABSOLUTE(.); - } > sram AT > flash - - .bss : ALIGN(4) { - _sbss = ABSOLUTE(.); - *(.bss .bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - _ebss = ABSOLUTE(.); - } > sram - - /* Stabs debugging sections. */ - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_info 0 : { *(.debug_info) } - .debug_line 0 : { *(.debug_line) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_aranges 0 : { *(.debug_aranges) } -} diff --git a/boards/arm/stm32/shenzhou/src/CMakeLists.txt b/boards/arm/stm32/shenzhou/src/CMakeLists.txt deleted file mode 100644 index fe1037ab0f8d4..0000000000000 --- a/boards/arm/stm32/shenzhou/src/CMakeLists.txt +++ /dev/null @@ -1,73 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/shenzhou/src/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -set(SRCS stm32_boot.c stm32_spi.c stm32_mmcsd.c stm32_chipid.c) - -if(CONFIG_ARCH_LEDS) - list(APPEND SRCS stm32_autoleds.c) -else() - list(APPEND SRCS stm32_userleds.c) -endif() - -if(CONFIG_ARCH_BUTTONS) - list(APPEND SRCS stm32_buttons.c) -endif() - -if(CONFIG_ARCH_RELAYS) - list(APPEND SRCS stm32_relays.c) -endif() - -if(CONFIG_STM32_OTGFS) - list(APPEND SRCS stm32_usb.c) -endif() - -if(CONFIG_MTD_W25) - list(APPEND SRCS stm32_w25.c) -endif() - -if(CONFIG_USBMSC) - list(APPEND SRCS stm32_usbmsc.c) -endif() - -if(CONFIG_STM32_CAN_CHARDRIVER) - list(APPEND SRCS stm32_can.c) -endif() - -if(CONFIG_ADC) - list(APPEND SRCS stm32_adc.c) -endif() - -# NOTE: SSD1289 is not supported on the board - -if(CONFIG_LCD_SSD1289) - list(APPEND SRCS stm32_ssd1289.c) -else() - list(APPEND SRCS stm32_ili93xx.c) -endif() - -if(CONFIG_INPUT_ADS7843E) - list(APPEND SRCS stm32_touchscreen.c) -endif() - -target_sources(board PRIVATE ${SRCS}) - -set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/ld.script") diff --git a/boards/arm/stm32/shenzhou/src/Make.defs b/boards/arm/stm32/shenzhou/src/Make.defs deleted file mode 100644 index 86db238f76e14..0000000000000 --- a/boards/arm/stm32/shenzhou/src/Make.defs +++ /dev/null @@ -1,75 +0,0 @@ -############################################################################ -# boards/arm/stm32/shenzhou/src/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/Make.defs - -CSRCS = stm32_boot.c stm32_spi.c stm32_mmcsd.c stm32_chipid.c - -ifeq ($(CONFIG_ARCH_LEDS),y) -CSRCS += stm32_autoleds.c -else -CSRCS += stm32_userleds.c -endif - -ifeq ($(CONFIG_ARCH_BUTTONS),y) -CSRCS += stm32_buttons.c -endif - -ifeq ($(CONFIG_ARCH_RELAYS),y) -CSRCS += stm32_relays.c -endif - -ifeq ($(CONFIG_STM32_OTGFS),y) -CSRCS += stm32_usb.c -endif - -ifeq ($(CONFIG_MTD_W25),y) -CSRCS += stm32_w25.c -endif - -ifeq ($(CONFIG_USBMSC),y) -CSRCS += stm32_usbmsc.c -endif - -ifeq ($(CONFIG_STM32_CAN_CHARDRIVER),y) -CSRCS += stm32_can.c -endif - -ifeq ($(CONFIG_ADC),y) -CSRCS += stm32_adc.c -endif - -# NOTE: SSD1289 is not supported on the board - -ifeq ($(CONFIG_LCD_SSD1289),y) -CSRCS += stm32_ssd1289.c -else -CSRCS += stm32_ili93xx.c -endif - -ifeq ($(CONFIG_INPUT_ADS7843E),y) -CSRCS += stm32_touchscreen.c -endif - -DEPPATH += --dep-path board -VPATH += :board -CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/shenzhou/src/stm32_adc.c b/boards/arm/stm32/shenzhou/src/stm32_adc.c deleted file mode 100644 index 95cd3ac7accfa..0000000000000 --- a/boards/arm/stm32/shenzhou/src/stm32_adc.c +++ /dev/null @@ -1,166 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/shenzhou/src/stm32_adc.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32_pwm.h" -#include "shenzhou.h" - -#ifdef CONFIG_ADC - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -/* Up to 3 ADC interfaces are supported */ - -#if STM32_NADC < 3 -# undef CONFIG_STM32_ADC3 -#endif - -#if STM32_NADC < 2 -# undef CONFIG_STM32_ADC2 -#endif - -#if STM32_NADC < 1 -# undef CONFIG_STM32_ADC1 -#endif - -#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) || defined(CONFIG_STM32_ADC3) -#ifndef CONFIG_STM32_ADC1 -# warning "Channel information only available for ADC1" -#endif - -/* The number of ADC channels in the conversion list */ - -#define ADC1_NCHANNELS 1 - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* Identifying number of each ADC channel. - * The only internal signal for ADC testing is the potentiometer input: - * - * ADC1_IN10(PC0) Potentiometer - * - * External signals are also available on CON5 CN14: - * - * ADC_IN8 (PB0) CON5 CN14 Pin2 - * ADC_IN9 (PB1) CON5 CN14 Pin1 - */ - -#ifdef CONFIG_STM32_ADC1 -static const uint8_t g_chanlist[ADC1_NCHANNELS] = -{ - 10 -}; - -/* {10, 8, 9}; */ - -/* Configurations of pins used by each ADC channel */ - -static const uint32_t g_pinlist[ADC1_NCHANNELS] = -{ - GPIO_ADC12_IN10 -}; - -/* {GPIO_ADC12_IN10, GPIO_ADC12_IN8, GPIO_ADC12_IN9}; */ -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_adc_setup - * - * Description: - * Initialize ADC and register the ADC driver. - * - ****************************************************************************/ - -int stm32_adc_setup(void) -{ -#ifdef CONFIG_STM32_ADC1 - static bool initialized = false; - struct adc_dev_s *adc; - int ret; - int i; - - /* Check if we have already initialized */ - - if (!initialized) - { - /* Configure the pins as analog inputs for the selected channels */ - - for (i = 0; i < ADC1_NCHANNELS; i++) - { - stm32_configgpio(g_pinlist[i]); - } - - /* Call stm32_adcinitialize() to get an instance of the ADC interface */ - - adc = stm32_adcinitialize(1, g_chanlist, ADC1_NCHANNELS); - if (adc == NULL) - { - aerr("ERROR: Failed to get ADC interface\n"); - return -ENODEV; - } - - /* Register the ADC driver at "/dev/adc0" */ - - ret = adc_register("/dev/adc0", adc); - if (ret < 0) - { - aerr("ERROR: adc_register failed: %d\n", ret); - return ret; - } - - /* Now we are initialized */ - - initialized = true; - } - - return OK; -#else - return -ENOSYS; -#endif -} - -#endif /* CONFIG_STM32_ADC1 || CONFIG_STM32_ADC2 || CONFIG_STM32_ADC3 */ -#endif /* CONFIG_ADC */ diff --git a/boards/arm/stm32/shenzhou/src/stm32_autoleds.c b/boards/arm/stm32/shenzhou/src/stm32_autoleds.c deleted file mode 100644 index cae0688a9f3f9..0000000000000 --- a/boards/arm/stm32/shenzhou/src/stm32_autoleds.c +++ /dev/null @@ -1,376 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/shenzhou/src/stm32_autoleds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32.h" -#include "shenzhou.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* The following definitions map the encoded LED setting to GPIO settings */ - -#define SHENZHOU_LED1 (1 << 0) -#define SHENZHOU_LED2 (1 << 1) -#define SHENZHOU_LED3 (1 << 2) -#define SHENZHOU_LED4 (1 << 3) - -#define ON_SETBITS_SHIFT (0) -#define ON_CLRBITS_SHIFT (4) -#define OFF_SETBITS_SHIFT (8) -#define OFF_CLRBITS_SHIFT (12) - -#define ON_BITS(v) ((v) & 0xff) -#define OFF_BITS(v) (((v) >> 8) & 0x0ff) -#define SETBITS(b) ((b) & 0x0f) -#define CLRBITS(b) (((b) >> 4) & 0x0f) - -#define ON_SETBITS(v) (SETBITS(ON_BITS(v)) -#define ON_CLRBITS(v) (CLRBITS(ON_BITS(v)) -#define OFF_SETBITS(v) (SETBITS(OFF_BITS(v)) -#define OFF_CLRBITS(v) (CLRBITS(OFF_BITS(v)) - -#define LED_STARTED_ON_SETBITS ((SHENZHOU_LED1) << ON_SETBITS_SHIFT) -#define LED_STARTED_ON_CLRBITS ((SHENZHOU_LED2|SHENZHOU_LED3|SHENZHOU_LED4) << ON_CLRBITS_SHIFT) -#define LED_STARTED_OFF_SETBITS (0 << OFF_SETBITS_SHIFT) -#define LED_STARTED_OFF_CLRBITS ((SHENZHOU_LED1|SHENZHOU_LED2|SHENZHOU_LED3|SHENZHOU_LED4) << OFF_CLRBITS_SHIFT) - -#define LED_HEAPALLOCATE_ON_SETBITS ((SHENZHOU_LED2) << ON_SETBITS_SHIFT) -#define LED_HEAPALLOCATE_ON_CLRBITS ((SHENZHOU_LED1|SHENZHOU_LED3|SHENZHOU_LED4) << ON_CLRBITS_SHIFT) -#define LED_HEAPALLOCATE_OFF_SETBITS ((SHENZHOU_LED1) << OFF_SETBITS_SHIFT) -#define LED_HEAPALLOCATE_OFF_CLRBITS ((SHENZHOU_LED2|SHENZHOU_LED3|SHENZHOU_LED4) << OFF_CLRBITS_SHIFT) - -#define LED_IRQSENABLED_ON_SETBITS ((SHENZHOU_LED1|SHENZHOU_LED2) << ON_SETBITS_SHIFT) -#define LED_IRQSENABLED_ON_CLRBITS ((SHENZHOU_LED3|SHENZHOU_LED4) << ON_CLRBITS_SHIFT) -#define LED_IRQSENABLED_OFF_SETBITS ((SHENZHOU_LED2) << OFF_SETBITS_SHIFT) -#define LED_IRQSENABLED_OFF_CLRBITS ((SHENZHOU_LED1|SHENZHOU_LED3|SHENZHOU_LED4) << OFF_CLRBITS_SHIFT) - -#define LED_STACKCREATED_ON_SETBITS ((SHENZHOU_LED3) << ON_SETBITS_SHIFT) -#define LED_STACKCREATED_ON_CLRBITS ((SHENZHOU_LED1|SHENZHOU_LED2|SHENZHOU_LED4) << ON_CLRBITS_SHIFT) -#define LED_STACKCREATED_OFF_SETBITS ((SHENZHOU_LED1|SHENZHOU_LED2) << OFF_SETBITS_SHIFT) -#define LED_STACKCREATED_OFF_CLRBITS ((SHENZHOU_LED3|SHENZHOU_LED4) << OFF_CLRBITS_SHIFT) - -#define LED_INIRQ_ON_SETBITS ((SHENZHOU_LED1) << ON_SETBITS_SHIFT) -#define LED_INIRQ_ON_CLRBITS ((0) << ON_CLRBITS_SHIFT) -#define LED_INIRQ_OFF_SETBITS ((0) << OFF_SETBITS_SHIFT) -#define LED_INIRQ_OFF_CLRBITS ((SHENZHOU_LED1) << OFF_CLRBITS_SHIFT) - -#define LED_SIGNAL_ON_SETBITS ((SHENZHOU_LED2) << ON_SETBITS_SHIFT) -#define LED_SIGNAL_ON_CLRBITS ((0) << ON_CLRBITS_SHIFT) -#define LED_SIGNAL_OFF_SETBITS ((0) << OFF_SETBITS_SHIFT) -#define LED_SIGNAL_OFF_CLRBITS ((SHENZHOU_LED2) << OFF_CLRBITS_SHIFT) - -#define LED_ASSERTION_ON_SETBITS ((SHENZHOU_LED4) << ON_SETBITS_SHIFT) -#define LED_ASSERTION_ON_CLRBITS ((0) << ON_CLRBITS_SHIFT) -#define LED_ASSERTION_OFF_SETBITS ((0) << OFF_SETBITS_SHIFT) -#define LED_ASSERTION_OFF_CLRBITS ((SHENZHOU_LED4) << OFF_CLRBITS_SHIFT) - -#define LED_PANIC_ON_SETBITS ((SHENZHOU_LED4) << ON_SETBITS_SHIFT) -#define LED_PANIC_ON_CLRBITS ((0) << ON_CLRBITS_SHIFT) -#define LED_PANIC_OFF_SETBITS ((0) << OFF_SETBITS_SHIFT) -#define LED_PANIC_OFF_CLRBITS ((SHENZHOU_LED4) << OFF_CLRBITS_SHIFT) - -/**************************************************************************** - * Private Function Protototypes - ****************************************************************************/ - -/* LED State Controls */ - -static inline void led_clrbits(unsigned int clrbits); -static inline void led_setbits(unsigned int setbits); -static void led_setonoff(unsigned int bits); - -/* LED Power Management */ - -#ifdef CONFIG_PM -static void led_pm_notify(struct pm_callback_s *cb, int domain, - enum pm_state_e pmstate); -static int led_pm_prepare(struct pm_callback_s *cb, int domain, - enum pm_state_e pmstate); -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -static const uint16_t g_ledbits[8] = -{ - (LED_STARTED_ON_SETBITS | LED_STARTED_ON_CLRBITS | - LED_STARTED_OFF_SETBITS | LED_STARTED_OFF_CLRBITS), - - (LED_HEAPALLOCATE_ON_SETBITS | LED_HEAPALLOCATE_ON_CLRBITS | - LED_HEAPALLOCATE_OFF_SETBITS | LED_HEAPALLOCATE_OFF_CLRBITS), - - (LED_IRQSENABLED_ON_SETBITS | LED_IRQSENABLED_ON_CLRBITS | - LED_IRQSENABLED_OFF_SETBITS | LED_IRQSENABLED_OFF_CLRBITS), - - (LED_STACKCREATED_ON_SETBITS | LED_STACKCREATED_ON_CLRBITS | - LED_STACKCREATED_OFF_SETBITS | LED_STACKCREATED_OFF_CLRBITS), - - (LED_INIRQ_ON_SETBITS | LED_INIRQ_ON_CLRBITS | - LED_INIRQ_OFF_SETBITS | LED_INIRQ_OFF_CLRBITS), - - (LED_SIGNAL_ON_SETBITS | LED_SIGNAL_ON_CLRBITS | - LED_SIGNAL_OFF_SETBITS | LED_SIGNAL_OFF_CLRBITS), - - (LED_ASSERTION_ON_SETBITS | LED_ASSERTION_ON_CLRBITS | - LED_ASSERTION_OFF_SETBITS | LED_ASSERTION_OFF_CLRBITS), - - (LED_PANIC_ON_SETBITS | LED_PANIC_ON_CLRBITS | - LED_PANIC_OFF_SETBITS | LED_PANIC_OFF_CLRBITS) -}; - -#ifdef CONFIG_PM -static struct pm_callback_s g_ledscb = -{ - .notify = led_pm_notify, - .prepare = led_pm_prepare, -}; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: led_clrbits - * - * Description: - * Clear all LEDs to the bit encoded state - * - ****************************************************************************/ - -static inline void led_clrbits(unsigned int clrbits) -{ - /* All LEDs are pulled up and, hence, active low */ - - if ((clrbits & SHENZHOU_LED1) != 0) - { - stm32_gpiowrite(GPIO_LED1, true); - } - - if ((clrbits & SHENZHOU_LED2) != 0) - { - stm32_gpiowrite(GPIO_LED2, true); - } - - if ((clrbits & SHENZHOU_LED3) != 0) - { - stm32_gpiowrite(GPIO_LED3, true); - } - - if ((clrbits & SHENZHOU_LED4) != 0) - { - stm32_gpiowrite(GPIO_LED4, true); - } -} - -/**************************************************************************** - * Name: led_setbits - * - * Description: - * Set all LEDs to the bit encoded state - * - ****************************************************************************/ - -static inline void led_setbits(unsigned int setbits) -{ - /* All LEDs are pulled up and, hence, active low */ - - if ((setbits & SHENZHOU_LED1) != 0) - { - stm32_gpiowrite(GPIO_LED1, false); - } - - if ((setbits & SHENZHOU_LED2) != 0) - { - stm32_gpiowrite(GPIO_LED2, false); - } - - if ((setbits & SHENZHOU_LED3) != 0) - { - stm32_gpiowrite(GPIO_LED3, false); - } - - if ((setbits & SHENZHOU_LED4) != 0) - { - stm32_gpiowrite(GPIO_LED4, false); - } -} - -/**************************************************************************** - * Name: led_setonoff - * - * Description: - * Set/clear all LEDs to the bit encoded state - * - ****************************************************************************/ - -static void led_setonoff(unsigned int bits) -{ - led_clrbits(CLRBITS(bits)); - led_setbits(SETBITS(bits)); -} - -/**************************************************************************** - * Name: led_pm_notify - * - * Description: - * Notify the driver of new power state. This callback is called after - * all drivers have had the opportunity to prepare for the new power state. - * - ****************************************************************************/ - -#ifdef CONFIG_PM -static void led_pm_notify(struct pm_callback_s *cb, int domain, - enum pm_state_e pmstate) -{ - switch (pmstate) - { - case PM_NORMAL: - { - /* Restore normal LEDs operation */ - } - break; - - case PM_IDLE: - { - /* Entering IDLE mode - Turn leds off */ - } - break; - - case PM_STANDBY: - { - /* Entering STANDBY mode - Logic for PM_STANDBY goes here */ - } - break; - - case PM_SLEEP: - { - /* Entering SLEEP mode - Logic for PM_SLEEP goes here */ - } - break; - - default: - { - /* Should not get here */ - } - break; - } -} -#endif - -/**************************************************************************** - * Name: led_pm_prepare - * - * Description: - * Request the driver to prepare for a new power state. This is a warning - * that the system is about to enter into a new power state. The driver - * should begin whatever operations that may be required to enter power - * state. The driver may abort the state change mode by returning a - * non-zero value from the callback function. - * - ****************************************************************************/ - -#ifdef CONFIG_PM -static int led_pm_prepare(struct pm_callback_s *cb, int domain, - enum pm_state_e pmstate) -{ - /* No preparation to change power modes is required by the LEDs driver. - * We always accept the state change by returning OK. - */ - - return OK; -} -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_autoled_initialize - ****************************************************************************/ - -#ifdef CONFIG_ARCH_LEDS -void board_autoled_initialize(void) -{ - /* Configure LED1-4 GPIOs for output */ - - stm32_configgpio(GPIO_LED1); - stm32_configgpio(GPIO_LED2); - stm32_configgpio(GPIO_LED3); - stm32_configgpio(GPIO_LED4); -} - -/**************************************************************************** - * Name: board_autoled_on - ****************************************************************************/ - -void board_autoled_on(int led) -{ - led_setonoff(ON_BITS(g_ledbits[led])); -} - -/**************************************************************************** - * Name: board_autoled_off - ****************************************************************************/ - -void board_autoled_off(int led) -{ - led_setonoff(OFF_BITS(g_ledbits[led])); -} - -/**************************************************************************** - * Name: up_ledpminitialize - ****************************************************************************/ - -#ifdef CONFIG_PM -void up_ledpminitialize(void) -{ - /* Register to receive power management callbacks */ - - int ret = pm_register(&g_ledscb); - if (ret != OK) - { - board_autoled_on(LED_ASSERTION); - } -} -#endif /* CONFIG_PM */ - -#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/shenzhou/src/stm32_boot.c b/boards/arm/stm32/shenzhou/src/stm32_boot.c deleted file mode 100644 index b4aa743dcb07b..0000000000000 --- a/boards/arm/stm32/shenzhou/src/stm32_boot.c +++ /dev/null @@ -1,270 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/shenzhou/src/stm32_boot.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include -#include -#include -#include - -#include -#include - -#include "arm_internal.h" -#include "stm32.h" -#include "shenzhou.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -/* Assume that we support everything until convinced otherwise */ - -#define HAVE_MMCSD 1 -#define HAVE_USBDEV 1 -#define HAVE_USBHOST 1 -#define HAVE_W25 1 - -/* Configuration ************************************************************/ - -/* SPI1 connects to the SD CARD (and to the SPI FLASH) */ - -#define STM32_MMCSDSPIPORTNO 1 /* SPI1 */ -#define STM32_MMCSDSLOTNO 0 /* Only one slot */ - -#ifndef CONFIG_STM32_SPI1 -# undef HAVE_MMCSD -#endif - -/* Can't support MMC/SD features if mountpoints are disabled */ - -#ifdef CONFIG_DISABLE_MOUNTPOINT -# undef HAVE_MMCSD -#endif - -/* Default MMC/SD minor number */ - -#ifdef HAVE_MMCSD -# ifndef CONFIG_NSH_MMCSDMINOR -# define CONFIG_NSH_MMCSDMINOR 0 -# endif - -/* Default MMC/SD SLOT number */ - -# if defined(CONFIG_NSH_MMCSDSLOTNO) && CONFIG_NSH_MMCSDSLOTNO != STM32_MMCSDSLOTNO -# error "Only one MMC/SD slot: Slot 0" -# endif - -/* Verify configured SPI port number */ - -# if defined(CONFIG_NSH_MMCSDSPIPORTNO) && CONFIG_NSH_MMCSDSPIPORTNO != STM32_MMCSDSPIPORTNO -# error "Only one MMC/SD port: SPI1" -# endif -#endif - -/* Can't support the W25 device if it SPI1 or W25 support is not enabled */ - -#if !defined(CONFIG_STM32_SPI1) || !defined(CONFIG_MTD_W25) -# undef HAVE_W25 -#endif - -/* Can't support W25 features if mountpoints are disabled */ - -#ifdef CONFIG_DISABLE_MOUNTPOINT -# undef HAVE_W25 -#endif - -/* Default W25 minor number */ - -#if defined(HAVE_W25) && !defined(CONFIG_NSH_W25MINOR) -# define CONFIG_NSH_W25MINOR 0 -#endif - -/* Can't support USB host or device features if USB OTG FS is not enabled */ - -#ifndef CONFIG_STM32_OTGFS -# undef HAVE_USBDEV -# undef HAVE_USBHOST -#endif - -/* Can't support USB device is USB device is not enabled */ - -#ifndef CONFIG_USBDEV -# undef HAVE_USBDEV -#endif - -/* Can't support USB host is USB host is not enabled */ - -#ifndef CONFIG_USBHOST -# undef HAVE_USBHOST -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_boardinitialize - * - * Description: - * All STM32 architectures must provide the following entry point. - * This entry point is called early in the initialization -- after all - * memory has been configured and mapped but before any devices have been - * initialized. - * - ****************************************************************************/ - -void stm32_boardinitialize(void) -{ - /* Configure SPI chip selects if 1) SPI is not disabled, and 2) the weak - * function stm32_spidev_initialize() has been brought into the link. - */ - -#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI3) - if (stm32_spidev_initialize) - { - stm32_spidev_initialize(); - } -#endif - - /* Initialize USB is 1) USBDEV is selected, 2) the USB controller is not - * disabled, and 3) the weak function stm32_usbinitialize() has been - * brought into the build. - */ - -#if defined(CONFIG_USBDEV) && defined(CONFIG_STM32_USB) - if (stm32_usbinitialize) - { - stm32_usbinitialize(); - } -#endif - - /* Configure on-board LEDs if LED support has been selected. */ - -#ifdef CONFIG_ARCH_LEDS - board_autoled_initialize(); -#endif -} - -/**************************************************************************** - * Name: board_late_initialize - * - * Description: - * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional - * initialization call will be performed in the boot-up sequence to a - * function called board_late_initialize(). board_late_initialize() will - * be called immediately after up_initialize() is called and just before - * the initial application is started. This additional initialization - * phase may be used, for example, to initialize board-specific device - * drivers. - * - ****************************************************************************/ - -#ifdef CONFIG_BOARD_LATE_INITIALIZE -void board_late_initialize(void) -{ - int ret; - -#ifdef HAVE_W25 - /* Initialize and register the W25 FLASH file system. */ - - ret = stm32_w25initialize(CONFIG_NSH_W25MINOR); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: Failed to initialize W25 minor %d: %d\n", - CONFIG_NSH_W25MINOR, ret); - return; - } -#endif - -#ifdef HAVE_MMCSD - /* Initialize the SPI-based MMC/SD slot */ - - ret = stm32_sdinitialize(CONFIG_NSH_MMCSDMINOR); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: Failed to initialize MMC/SD slot %d: %d\n", - STM32_MMCSDSLOTNO, ret); - return; - } -#endif - -#ifdef HAVE_USBHOST - /* Initialize USB host operation. - * stm32_usbhost_initialize() starts a thread will monitor - * for USB connection and disconnection events. - */ - - ret = stm32_usbhost_initialize(); - if (ret != OK) - { - syslog(LOG_ERR, "ERROR: Failed to initialize USB host: %d\n", ret); - return; - } -#endif - -#ifdef CONFIG_INPUT_ADS7843E - /* Initialize the touchscreen */ - - ret = stm32_tsc_setup(0); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_tsc_setup failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_ADC - /* Initialize ADC and register the ADC driver. */ - - ret = stm32_adc_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_adc_setup failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_STM32_CAN_CHARDRIVER - /* Initialize CAN and register the CAN driver. */ - - ret = stm32_can_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_can_setup failed: %d\n", ret); - } -#endif - - UNUSED(ret); -} -#endif diff --git a/boards/arm/stm32/shenzhou/src/stm32_buttons.c b/boards/arm/stm32/shenzhou/src/stm32_buttons.c deleted file mode 100644 index 0081e708c365b..0000000000000 --- a/boards/arm/stm32/shenzhou/src/stm32_buttons.c +++ /dev/null @@ -1,157 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/shenzhou/src/stm32_buttons.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include -#include - -#include "shenzhou.h" - -#ifdef CONFIG_ARCH_BUTTONS - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* Pin configuration for each Shenzhou button. This array is indexed by - * the BUTTON_* definitions in board.h - */ - -static const uint32_t g_buttons[NUM_BUTTONS] = -{ - GPIO_BTN_USERKEY2, GPIO_BTN_USERKEY, GPIO_BTN_TAMPER, GPIO_BTN_WAKEUP -}; - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_button_initialize - * - * Description: - * board_button_initialize() must be called to initialize button resources. - * After that, board_buttons() may be called to collect the current state - * of all buttons or board_button_irq() may be called to register button - * interrupt handlers. - * - ****************************************************************************/ - -uint32_t board_button_initialize(void) -{ - int i; - - /* Configure the GPIO pins as inputs. NOTE that EXTI interrupts are - * configured for some pins but NOT used in this file - */ - - for (i = 0; i < NUM_BUTTONS; i++) - { - stm32_configgpio(g_buttons[i]); - } - - return NUM_BUTTONS; -} - -/**************************************************************************** - * Name: board_buttons - ****************************************************************************/ - -uint32_t board_buttons(void) -{ - uint32_t ret = 0; - int i; - - /* Check that state of each key */ - - for (i = 0; i < NUM_BUTTONS; i++) - { - /* A LOW value means that the key is pressed for most keys. - * The exception is the WAKEUP button. - */ - - bool released = stm32_gpioread(g_buttons[i]); - if (i == BUTTON_WAKEUP) - { - released = !released; - } - - /* Accumulate the set of depressed (not released) keys */ - - if (!released) - { - ret |= (1 << i); - } - } - - return ret; -} - -/**************************************************************************** - * Button support. - * - * Description: - * board_button_initialize() must be called to initialize button resources. - * After that, board_buttons() may be called to collect the current state - * of all buttons or board_button_irq() may be called to register button - * interrupt handlers. - * - * After board_button_initialize() has been called, board_buttons() may be - * called to collect the state of all buttons. board_buttons() returns an - * 32-bit bit set with each bit associated with a button. See the - * BUTTON_*_BIT and JOYSTICK_*_BIT definitions in board.h for the meaning - * of each bit. - * - * board_button_irq() may be called to register an interrupt handler that - * will be called when a button is depressed or released. The ID value is a - * button enumeration value that uniquely identifies a button resource. See - * the BUTTON_* and JOYSTICK_* definitions in board.h for the meaning of - * enumeration value. - * - ****************************************************************************/ - -#ifdef CONFIG_ARCH_IRQBUTTONS -int board_button_irq(int id, xcpt_t irqhandler, void *arg) -{ - int ret = -EINVAL; - - /* The following should be atomic */ - - if (id >= MIN_IRQBUTTON && id <= MAX_IRQBUTTON) - { - ret = stm32_gpiosetevent(g_buttons[id], true, true, true, - irqhandler, arg); - } - - return ret; -} -#endif -#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/stm32/shenzhou/src/stm32_can.c b/boards/arm/stm32/shenzhou/src/stm32_can.c deleted file mode 100644 index 8a32d419a42ea..0000000000000 --- a/boards/arm/stm32/shenzhou/src/stm32_can.c +++ /dev/null @@ -1,104 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/shenzhou/src/stm32_can.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32.h" -#include "stm32_can.h" -#include "shenzhou.h" - -#ifdef CONFIG_CAN - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -/* The STM32F107VC supports CAN1 and CAN2 */ - -#if defined(CONFIG_STM32_CAN1) && defined(CONFIG_STM32_CAN2) -# warning "Both CAN1 and CAN2 are enabled. Only CAN1 is connected." -# undef CONFIG_STM32_CAN2 -#endif - -#ifdef CONFIG_STM32_CAN1 -# define CAN_PORT 1 -#else -# define CAN_PORT 2 -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_can_setup - * - * Description: - * Initialize CAN and register the CAN device - * - ****************************************************************************/ - -int stm32_can_setup(void) -{ -#if defined(CONFIG_STM32_CAN1) || defined(CONFIG_STM32_CAN2) - struct can_dev_s *can; - int ret; - - /* Call stm32_caninitialize() to get an instance of the CAN interface */ - - can = stm32_caninitialize(CAN_PORT); - if (can == NULL) - { - canerr("ERROR: Failed to get CAN interface\n"); - return -ENODEV; - } - - /* Register the CAN driver at "/dev/can0" */ - - ret = can_register("/dev/can0", can); - if (ret < 0) - { - canerr("ERROR: can_register failed: %d\n", ret); - return ret; - } - - return OK; -#else - return -ENODEV; -#endif -} - -#endif /* CONFIG_CAN */ diff --git a/boards/arm/stm32/shenzhou/src/stm32_chipid.c b/boards/arm/stm32/shenzhou/src/stm32_chipid.c deleted file mode 100644 index 8ad2d692034be..0000000000000 --- a/boards/arm/stm32/shenzhou/src/stm32_chipid.c +++ /dev/null @@ -1,79 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/shenzhou/src/stm32_chipid.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include - -#include "arm_internal.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -const char *stm32_getchipid(void) -{ - static char cpuid[12]; - int i; - - for (i = 0; i < 12; i++) - { - cpuid[i] = getreg8(0x1ffff7e8 + i); - } - - return cpuid; -} - -const char *stm32_getchipid_string(void) -{ - static char cpuid[27]; - int c; - int i; - - for (i = 0, c = 0; i < 12; i++) - { - snprintf(&cpuid[c], sizeof(cpuid) - c, - "%02X", getreg8(0x1ffff7e8 + 11 - i)); - c += 2; - if (i % 4 == 3) - { - cpuid[c++] = '-'; - } - } - - cpuid[26] = '\0'; - return cpuid; -} diff --git a/boards/arm/stm32/shenzhou/src/stm32_mmcsd.c b/boards/arm/stm32/shenzhou/src/stm32_mmcsd.c deleted file mode 100644 index 283527e5d118b..0000000000000 --- a/boards/arm/stm32/shenzhou/src/stm32_mmcsd.c +++ /dev/null @@ -1,116 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/shenzhou/src/stm32_mmcsd.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include "stm32_spi.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -/* SPI1 connects to the SD CARD (and to the SPI FLASH) */ - -#define HAVE_MMCSD 1 /* Assume that we have SD support */ -#define STM32_MMCSDSPIPORTNO 1 /* Port is SPI1 */ -#define STM32_MMCSDSLOTNO 0 /* There is only one slot */ - -#ifndef CONFIG_STM32_SPI1 -# undef HAVE_MMCSD -#endif - -/* Can't support MMC/SD features if MMC/SD driver support is not selected */ - -#ifndef CONFIG_MMCSD -# undef HAVE_MMCSD -#endif - -/* Can't support MMC/SD features if mountpoints are disabled */ - -#ifdef CONFIG_DISABLE_MOUNTPOINT -# undef HAVE_MMCSD -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_sdinitialize - * - * Description: - * Initialize the SPI-based SD card. Requires CONFIG_DISABLE_MOUNTPOINT=n - * and CONFIG_STM32_SPI1=y - * - ****************************************************************************/ - -int stm32_sdinitialize(int minor) -{ -#ifdef HAVE_MMCSD - struct spi_dev_s *spi; - int ret; - - /* Get the SPI port */ - - finfo("Initializing SPI port %d\n", STM32_MMCSDSPIPORTNO); - - spi = stm32_spibus_initialize(STM32_MMCSDSPIPORTNO); - if (!spi) - { - ferr("ERROR: Failed to initialize SPI port %d\n", - STM32_MMCSDSPIPORTNO); - return -ENODEV; - } - - finfo("Successfully initialized SPI port %d\n", STM32_MMCSDSPIPORTNO); - - /* Bind the SPI port to the slot */ - - finfo("Binding SPI port %d to MMC/SD slot %d\n", - STM32_MMCSDSPIPORTNO, STM32_MMCSDSLOTNO); - - ret = mmcsd_spislotinitialize(minor, STM32_MMCSDSLOTNO, spi); - if (ret < 0) - { - ferr("ERROR: Failed to bind SPI port %d to MMC/SD slot %d: %d\n", - STM32_MMCSDSPIPORTNO, STM32_MMCSDSLOTNO, ret); - return ret; - } - - finfo("Successfully bound SPI port %d to MMC/SD slot %d\n", - STM32_MMCSDSPIPORTNO, STM32_MMCSDSLOTNO); -#endif - return OK; -} diff --git a/boards/arm/stm32/shenzhou/src/stm32_relays.c b/boards/arm/stm32/shenzhou/src/stm32_relays.c deleted file mode 100644 index fab227889369d..0000000000000 --- a/boards/arm/stm32/shenzhou/src/stm32_relays.c +++ /dev/null @@ -1,274 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/shenzhou/src/stm32_relays.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include -#include - -#include "shenzhou.h" - -#ifdef CONFIG_ARCH_RELAYS - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#define RELAYS_MIN_RESET_TIME 5 -#define RELAYS_RESET_MTIME 5 -#define RELAYS_POWER_MTIME 50 - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -static uint32_t g_relays_stat = 0; -static bool g_relays_init = false; - -static const uint16_t g_relays[NUM_RELAYS] = -{ - GPIO_RELAYS_R00 -#ifdef GPIO_RELAYS_R01 - , GPIO_RELAYS_R01 -#endif -#ifdef GPIO_RELAYS_R02 - , GPIO_RELAYS_R02 -#endif -#ifdef GPIO_RELAYS_R03 - , GPIO_RELAYS_R03 -#endif -#ifdef GPIO_RELAYS_R04 - , GPIO_RELAYS_R04 -#endif -#ifdef GPIO_RELAYS_R05 - , GPIO_RELAYS_R05 -#endif -#ifdef GPIO_RELAYS_R06 - , GPIO_RELAYS_R06 -#endif -#ifdef GPIO_RELAYS_R07 - , GPIO_RELAYS_R07 -#endif -#ifdef GPIO_RELAYS_R08 - , GPIO_RELAYS_R08 -#endif -#ifdef GPIO_RELAYS_R09 - , GPIO_RELAYS_R09 -#endif -#ifdef GPIO_RELAYS_R10 - , GPIO_RELAYS_R10 -#endif -#ifdef GPIO_RELAYS_R11 - , GPIO_RELAYS_R11 -#endif -#ifdef GPIO_RELAYS_R12 - , GPIO_RELAYS_R12 -#endif -#ifdef GPIO_RELAYS_R13 - , GPIO_RELAYS_R13 -#endif -#ifdef GPIO_RELAYS_R14 - , GPIO_RELAYS_R14 -#endif -#ifdef GPIO_RELAYS_R15 - , GPIO_RELAYS_R15 -#endif -#ifdef GPIO_RELAYS_R16 - , GPIO_RELAYS_R16 -#endif -#ifdef GPIO_RELAYS_R17 - , GPIO_RELAYS_R17 -#endif -#ifdef GPIO_RELAYS_R18 - , GPIO_RELAYS_R18 -#endif -#ifdef GPIO_RELAYS_R19 - , GPIO_RELAYS_R19 -#endif -#ifdef GPIO_RELAYS_R20 - , GPIO_RELAYS_R20 -#endif -#ifdef GPIO_RELAYS_R21 - , GPIO_RELAYS_R21 -#endif -#ifdef GPIO_RELAYS_R22 - , GPIO_RELAYS_R22 -#endif -#ifdef GPIO_RELAYS_R23 - , GPIO_RELAYS_R23 -#endif -#ifdef GPIO_RELAYS_R24 - , GPIO_RELAYS_R24 -#endif -#ifdef GPIO_RELAYS_R25 - , GPIO_RELAYS_R25 -#endif -#ifdef GPIO_RELAYS_R26 - , GPIO_RELAYS_R26 -#endif -#ifdef GPIO_RELAYS_R27 - , GPIO_RELAYS_R27 -#endif -#ifdef GPIO_RELAYS_R28 - , GPIO_RELAYS_R28 -#endif -#ifdef GPIO_RELAYS_R29 - , GPIO_RELAYS_R29 -#endif -#ifdef GPIO_RELAYS_R30 - , GPIO_RELAYS_R30 -#endif -#ifdef GPIO_RELAYS_R31 - , GPIO_RELAYS_R31 -#endif -}; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -void up_relaysinit(void) -{ - int i; - - if (g_relays_init) - { - return; - } - - /* Configure the GPIO pins as inputs. NOTE that EXTI interrupts are - * configured for some pins but NOT used in this file - */ - - for (i = 0; i < NUM_RELAYS; i++) - { - stm32_configgpio(g_relays[i]); - stm32_gpiowrite(g_relays[i], false); - } - - g_relays_init = true; -} - -void relays_setstat(int relays, bool stat) -{ - if ((unsigned)relays < NUM_RELAYS) - { - stm32_gpiowrite(g_relays[relays], stat); - if (!stat) - { - g_relays_stat &= ~(1 << relays); - } - else - { - g_relays_stat |= (1 << relays); - } - } -} - -bool relays_getstat(int relays) -{ - if ((unsigned)relays < NUM_RELAYS) - { - return (g_relays_stat & (1 << relays)) != 0; - } - - return false; -} - -void relays_setstats(uint32_t relays_stat) -{ - int i; - - for (i = 0; i < NUM_RELAYS; i++) - { - relays_setstat(i, (relays_stat & (1 << i)) != 0); - } -} - -uint32_t relays_getstats(void) -{ - return (uint32_t)g_relays_stat; -} - -void relays_onoff(int relays, uint32_t mdelay) -{ - if ((unsigned)relays < NUM_RELAYS) - { - if (mdelay > 0) - { - if (relays_getstat(relays)) - { - relays_setstat(relays, false); - nxsched_usleep(RELAYS_MIN_RESET_TIME * 1000 * 1000); - } - - relays_setstat(relays, true); - nxsched_usleep(mdelay * 100 * 1000); - relays_setstat(relays, false); - } - } -} - -void relays_onoffs(uint32_t relays_stat, uint32_t mdelay) -{ - int i; - - for (i = 0; i < NUM_RELAYS; i++) - { - relays_onoff(i, mdelay); - } -} - -void relays_resetmode(int relays) -{ - relays_onoff(relays, RELAYS_RESET_MTIME); -} - -void relays_powermode(int relays) -{ - relays_onoff(relays, RELAYS_POWER_MTIME); -} - -void relays_resetmodes(uint32_t relays_stat) -{ - relays_onoffs(relays_stat, RELAYS_RESET_MTIME); -} - -void relays_powermodes(uint32_t relays_stat) -{ - relays_onoffs(relays_stat, RELAYS_POWER_MTIME); -} - -#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/stm32/shenzhou/src/stm32_spi.c b/boards/arm/stm32/shenzhou/src/stm32_spi.c deleted file mode 100644 index 43629080b141c..0000000000000 --- a/boards/arm/stm32/shenzhou/src/stm32_spi.c +++ /dev/null @@ -1,189 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/shenzhou/src/stm32_spi.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include "arm_internal.h" -#include "chip.h" -#include "stm32.h" -#include "shenzhou.h" - -#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI3) - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_spidev_initialize - * - * Description: - * Called to configure SPI chip select GPIO pins for the Shenzhou board. - * - ****************************************************************************/ - -void weak_function stm32_spidev_initialize(void) -{ - /* NOTE: Clocking for SPI1 and/or SPI3 was already provided in stm32_rcc.c. - * Configurations of SPI pins is performed in stm32_spi.c. - * Here, we only initialize chip select pins unique to the board - * architecture. - */ - - /* SPI1 connects to the SD CARD and to the SPI FLASH */ - -#ifdef CONFIG_STM32_SPI1 - stm32_configgpio(GPIO_SD_CS); /* SD card chip select */ - stm32_configgpio(GPIO_SD_CD); /* SD card detect */ - stm32_configgpio(GPIO_FLASH_CS); /* FLASH chip select */ -#endif - - /* SPI3 connects to TFT LCD module and the RF24L01 2.4G wireless module */ - -#ifdef CONFIG_STM32_SPI3 - stm32_configgpio(GPIO_TP_CS); /* Touchscreen chip select */ - stm32_configgpio(GPIO_LCDDF_CS); /* Data flash chip select (on the LCD module) */ - stm32_configgpio(GPIO_LCDSD_CS); /* SD chip select (on the LCD module) */ - stm32_configgpio(GPIO_WIRELESS_CS); /* Wireless chip select */ -#endif -} - -/**************************************************************************** - * Name: stm32_spi1/2/3select and stm32_spi1/2/3status - * - * Description: - * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status - * must be provided by board-specific logic. They are implementations of - * the select and status methods of the SPI interface defined by struct - * spi_ops_s (see include/nuttx/spi/spi.h). - * All other methods (including stm32_spibus_initialize()) are provided by - * common STM32 logic. - * To use this common SPI logic on your board: - * - * 1. Provide logic in stm32_boardinitialize() to configure SPI chip select - * pins. - * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() functions - * in your board-specific logic. These functions will perform chip - * selection and status operations using GPIOs in the way your board is - * configured. - * 3. Add a calls to stm32_spibus_initialize() in your low level - * application initialization logic - * 4. The handle returned by stm32_spibus_initialize() may then be used to - * bind the SPI driver to higher level logic (e.g., calling - * mmcsd_spislotinitialize(), for example, will bind the SPI driver to - * the SPI MMC/SD driver). - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_SPI1 -void stm32_spi1select(struct spi_dev_s *dev, - uint32_t devid, bool selected) -{ - spiinfo("devid: %d CS: %s\n", - (int)devid, selected ? "assert" : "de-assert"); - - /* SPI1 connects to the SD CARD and to the SPI FLASH */ - - if (devid == SPIDEV_MMCSD(0)) - { - /* Set the GPIO low to select and high to de-select */ - - stm32_gpiowrite(GPIO_SD_CS, !selected); - } - else if (devid == SPIDEV_FLASH(0)) - { - /* Set the GPIO low to select and high to de-select */ - - stm32_gpiowrite(GPIO_FLASH_CS, !selected); - } -} - -uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) -{ - /* The card detect pin is pulled up so that we detect the presence of a - * card by see a low value on the input pin. - */ - - if (stm32_gpioread(GPIO_SD_CD)) - { - return 0; - } - - return SPI_STATUS_PRESENT; -} -#endif - -#ifdef CONFIG_STM32_SPI3 -void stm32_spi3select(struct spi_dev_s *dev, - uint32_t devid, bool selected) -{ - spiinfo("devid: %d CS: %s\n", - (int)devid, selected ? "assert" : "de-assert"); - - /* SPI3 connects to TFT LCD (for touchscreen and SD) and the RF24L01 2.4G - * wireless module. - */ - - if (devid == SPIDEV_TOUCHSCREEN(0)) - { - /* Set the GPIO low to select and high to de-select */ - - stm32_gpiowrite(GPIO_TP_CS, !selected); - } - else if (devid == SPIDEV_MMCSD(0)) - { - /* Set the GPIO low to select and high to de-select */ - - stm32_gpiowrite(GPIO_LCDDF_CS, !selected); - } - else if (devid == SPIDEV_FLASH(0)) - { - /* Set the GPIO low to select and high to de-select */ - - stm32_gpiowrite(GPIO_LCDSD_CS, !selected); - } - else if (devid == SPIDEV_WIRELESS(0)) - { - /* Set the GPIO low to select and high to de-select */ - - stm32_gpiowrite(GPIO_WIRELESS_CS, !selected); - } -} - -uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid) -{ - return 0; -} -#endif - -#endif /* CONFIG_STM32_SPI1 || CONFIG_STM32_SPI3 */ diff --git a/boards/arm/stm32/shenzhou/src/stm32_ssd1289.c b/boards/arm/stm32/shenzhou/src/stm32_ssd1289.c deleted file mode 100644 index c8b22220d7420..0000000000000 --- a/boards/arm/stm32/shenzhou/src/stm32_ssd1289.c +++ /dev/null @@ -1,597 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/shenzhou/src/stm32_ssd1289.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include - -#include - -#include "arm_internal.h" -#include "stm32.h" -#include "shenzhou.h" - -#ifdef CONFIG_LCD_SSD1289 - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -#undef CONFIG_LCD_FASTCONFIG -#define CONFIG_LCD_FASTCONFIG 1 - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/* This structure describes the state of this driver */ - -struct stm32_lower_s -{ - struct ssd1289_lcd_s dev; /* This is externally visible the driver state */ - struct lcd_dev_s *drvr; /* The saved instance of the LCD driver */ - bool output; /* True: Configured for output */ -}; - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -/* Helpers */ - -#ifdef CONFIG_LCD_REGDEBUG -static void stm32_lcdshow(struct stm32_lower_s *priv, - const char *msg); -#else -# define stm32_lcdshow(p,m) -#endif - -static void stm32_wrdata(struct stm32_lower_s *priv, uint16_t data); -#ifndef CONFIG_LCD_NOGETRUN -static inline uint16_t stm32_rddata(struct stm32_lower_s *priv); -#endif - -/* Low Level LCD access */ - -static void stm32_select(struct ssd1289_lcd_s *dev); -static void stm32_deselect(struct ssd1289_lcd_s *dev); -static void stm32_index(struct ssd1289_lcd_s *dev, uint8_t index); -#ifndef CONFIG_LCD_NOGETRUN -static uint16_t stm32_read(struct ssd1289_lcd_s *dev); -#endif -static void stm32_write(struct ssd1289_lcd_s *dev, uint16_t data); -static void stm32_backlight(struct ssd1289_lcd_s *dev, int power); - -/* Initialization */ - -#ifndef CONFIG_LCD_NOGETRUN -static void stm32_lcdinput(struct stm32_lower_s *priv); -#endif -static void stm32_lcdoutput(struct stm32_lower_s *priv); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* TFT LCD - * - * -- ---- -------------- --------------------------------------------------- - * PN NAME SIGNAL NOTES - * -- ---- -------------- --------------------------------------------------- - * 37 PB2 DATA_LE To TFT LCD (CN13, ping 28) - * 96 PB9 F_CS To both the TFT LCD (CN13, pin 30) and - * to the W25X16 SPI FLASH - * 34 PC5 TP_INT JP6. To TFT LCD (CN13) module (CN13, pin 26) - * 65 PC8 LCD_CS Active low: Pulled high (CN13, pin 19) - * 66 PC9 TP_CS Active low: Pulled high (CN13, pin 31) - * 78 PC10 SPI3_SCK To TFT LCD (CN13, pin 29) - * 79 PC11 SPI3_MISO To TFT LCD (CN13, pin 25) - * 80 PC12 SPI3_MOSI To TFT LCD (CN13, pin 27) - * 58 PD11 SD_CS Active low: Pulled high - * (See also TFT LCD CN13, pin 32) - * 60 PD13 LCD_RS To TFT LCD (CN13, pin 20) - * 61 PD14 LCD_WR To TFT LCD (CN13, pin 21). - * Schematic is wrong LCD_WR is PB14. - * 62 PD15 LCD_RD To TFT LCD (CN13, pin 22) - * 97 PE0 DB00 To TFT LCD (CN13, pin 3) - * 98 PE1 DB01 To TFT LCD (CN13, pin 4) - * 1 PE2 DB02 To TFT LCD (CN13, pin 5) - * 2 PE3 DB03 To TFT LCD (CN13, pin 6) - * 3 PE4 DB04 To TFT LCD (CN13, pin 7) - * 4 PE5 DB05 To TFT LCD (CN13, pin 8) - * 5 PE6 DB06 To TFT LCD (CN13, pin 9) - * 38 PE7 DB07 To TFT LCD (CN13, pin 10) - * 39 PE8 DB08 To TFT LCD (CN13, pin 11) - * 40 PE9 DB09 To TFT LCD (CN13, pin 12) - * 41 PE10 DB10 To TFT LCD (CN13, pin 13) - * 42 PE11 DB11 To TFT LCD (CN13, pin 16) - * 43 PE12 DB12 To TFT LCD (CN13, pin 15) - * 44 PE13 DB13 To TFT LCD (CN13, pin 16) - * 45 PE14 DB14 To TFT LCD (CN13, pin 17) - * 46 PE15 DB15 To TFT LCD (CN13, pin 18) - * - * NOTE: - * The backlight signl NC_BL (CN13, pin 24) is pulled high and not under - * software control - * - * On LCD module: - * -- -------------- -------------------------------------------------------- - * PN SIGNAL NOTES - * -- -------------- -------------------------------------------------------- - * 3 DB01 To LCD DB1 - * 4 DB00 To LCD DB0 - * 5 DB03 To LCD DB3 - * 6 DB02 To LCD DB2 - * 7 DB05 To LCD DB5 - * 8 DB04 To LCD DB4 - * 9 DB07 To LCD DB7 - * 10 DB06 To LCD DB6 - * 11 DB09 To LCD DB9 - * 12 DB08 To LCD DB8 - * 13 DB11 To LCD DB11 - * 14 DB10 To LCD DB10 - * 15 DB13 To LCD DB13 - * 16 DB12 To LCD DB12 - * 17 DB15 To LCD DB15 - * 18 DB14 To LCD DB14 - * 19 RS To LCD RS - * 20 /LCD_CS To LCD CS - * 21 /RD To LCD RD - * 22 /WR To LCD WR - * 23 BL_EN (Not referenced) - * 24 /RESET - * 25 /INT To Touch IC /INT - * 26 MISO To Touch IC DOUT; To AT45DB161B SO; To SD card DAT0 - * 27 LE To 74HC573 that controls LCD 8-bit/16-bit mode - * 28 MOSI To Touch IC DIN; To AT45DB161B SI; To SD card CMD - * 29 /DF_CS To AT45DB161B Data Flash /CS - * 30 SCLK To Touch IC DCLK; To AT45DB161B SCK; To SD card CLK - * 31 /SD_CS To SD card /CS - * 31 /TP_CS To Touch IC CS - */ - -/* LCD GPIO configurations */ - -#ifndef CONFIG_LCD_FASTCONFIG -static const uint32_t g_lcdout[16] = -{ - GPIO_LCD_D0OUT, GPIO_LCD_D1OUT, - GPIO_LCD_D2OUT, GPIO_LCD_D3OUT, - GPIO_LCD_D4OUT, GPIO_LCD_D5OUT, - GPIO_LCD_D6OUT, GPIO_LCD_D7OUT, - GPIO_LCD_D8OUT, GPIO_LCD_D9OUT, - GPIO_LCD_D10OUT, GPIO_LCD_D11OUT, - GPIO_LCD_D12OUT, GPIO_LCD_D13OUT, - GPIO_LCD_D14OUT, GPIO_LCD_D15OUT -}; - -static const uint32_t g_lcdin[16] = -{ - GPIO_LCD_D0IN, GPIO_LCD_D1IN, - GPIO_LCD_D2IN, GPIO_LCD_D3IN, - GPIO_LCD_D4IN, GPIO_LCD_D5IN, - GPIO_LCD_D6IN, GPIO_LCD_D7IN, - GPIO_LCD_D8IN, GPIO_LCD_D9IN, - GPIO_LCD_D10IN, GPIO_LCD_D11IN, - GPIO_LCD_D12IN, GPIO_LCD_D13IN, - GPIO_LCD_D14IN, GPIO_LCD_D15IN -}; -#endif - -static const uint32_t g_lcdconfig[] = -{ - GPIO_LCD_RS, GPIO_LCD_CS, - GPIO_LCD_RD, GPIO_LCD_WR, - GPIO_LCD_LE, -}; -#define NLCD_CONFIG (sizeof(g_lcdconfig)/sizeof(uint32_t)) - -/* Driver state structure (only supports one LCD) */ - -static struct stm32_lower_s g_lcdlower = -{ - { - .select = stm32_select, - .deselect = stm32_deselect, - .index = stm32_index, -#ifndef CONFIG_LCD_NOGETRUN - .read = stm32_read, -#endif - .write = stm32_write, - .backlight = stm32_backlight - }, - .drvr = NULL, - .output = false -}; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_lcdshow - * - * Description: - * Show the state of the interface - * - ****************************************************************************/ - -#ifdef CONFIG_LCD_REGDEBUG -static void stm32_lcdshow(struct stm32_lower_s *priv, - const char *msg) -{ - _info("%s:\n", msg); - _info(" CRTL RS: %d CS: %d RD: %d WR: %d LE: %d\n", - getreg32(LCD_RS_READ), getreg32(LCD_CS_READ), getreg32(LCD_RD_READ), - getreg32(LCD_WR_READ), getreg32(LCD_LE_READ)); - _info(" DATA CR: %08x %08x\n", getreg32(LCD_CRL), getreg32(LCD_CRH)); - if (priv->output) - { - _info(" OUTPUT: %08x\n", getreg32(LCD_ODR)); - } - else - { - _info(" INPUT: %08x\n", getreg32(LCD_IDR)); - } -} -#endif - -/**************************************************************************** - * Name: stm32_wrdata - * - * Description: - * Latch data on D0-D15 and toggle the WR line. - * - ****************************************************************************/ - -static void stm32_wrdata(struct stm32_lower_s *priv, uint16_t data) -{ - /* Make sure D0-D15 are configured as outputs */ - - stm32_lcdoutput(priv); - - /* Latch the 16-bit LCD data and toggle the WR line */ - - putreg32(1, LCD_WR_CLEAR); - putreg32((uint32_t)data, LCD_ODR); - - /* Total WR pulse with should be 50ns wide. */ - - putreg32(1, LCD_WR_SET); -} - -/**************************************************************************** - * Name: stm32_rddata - * - * Description: - * Latch data on D0-D15 and toggle the WR line. - * - ****************************************************************************/ - -#ifndef CONFIG_LCD_NOGETRUN -static inline uint16_t stm32_rddata(struct stm32_lower_s *priv) -{ - uint16_t regval; - - /* Make sure D0-D15 are configured as inputs */ - - stm32_lcdinput(priv); - - /* Toggle the RD line to latch the 16-bit LCD data */ - - putreg32(1, LCD_RD_CLEAR); - - /* Data should appear 250ns after RD. - * Total RD pulse width should be 500nS - */ - - __asm__ __volatile__(" nop\n nop\n nop\n nop\n"); - regval = (uint16_t)getreg32(LCD_IDR); - putreg32(1, LCD_RD_SET); - return regval; -} -#endif - -/**************************************************************************** - * Name: stm32_select - * - * Description: - * Select the LCD device - * - ****************************************************************************/ - -static void stm32_select(struct ssd1289_lcd_s *dev) -{ - /* Select the LCD by setting the LCD_CS low */ - - putreg32(1, LCD_CS_CLEAR); -} - -/**************************************************************************** - * Name: stm32_deselect - * - * Description: - * De-select the LCD device - * - ****************************************************************************/ - -static void stm32_deselect(struct ssd1289_lcd_s *dev) -{ - /* De-select the LCD by setting the LCD_CS high */ - - putreg32(1, LCD_CS_SET); -} - -/**************************************************************************** - * Name: stm32_index - * - * Description: - * Set the index register - * - ****************************************************************************/ - -static void stm32_index(struct ssd1289_lcd_s *dev, uint8_t index) -{ - struct stm32_lower_s *priv = (struct stm32_lower_s *)dev; - - /* Clear the RS signal to select the index address */ - - putreg32(1, LCD_RS_CLEAR); - - /* And write the index */ - - stm32_wrdata(priv, (uint16_t)index); -} - -/**************************************************************************** - * Name: stm32_read - * - * Description: - * Read LCD data (GRAM data or register contents) - * - ****************************************************************************/ - -#ifndef CONFIG_LCD_NOGETRUN -static uint16_t stm32_read(struct ssd1289_lcd_s *dev) -{ - struct stm32_lower_s *priv = (struct stm32_lower_s *)dev; - - /* Set the RS signal to select the data address */ - - putreg32(1, LCD_RS_SET); - - /* Read and return the data */ - - return stm32_rddata(priv); -} -#endif - -/**************************************************************************** - * Name: stm32_write - * - * Description: - * Write LCD data (GRAM data or register contents) - * - ****************************************************************************/ - -static void stm32_write(struct ssd1289_lcd_s *dev, uint16_t data) -{ - struct stm32_lower_s *priv = (struct stm32_lower_s *)dev; - - /* Set the RS signal to select the data address */ - - putreg32(1, LCD_RS_SET); - - /* And write the data */ - - stm32_wrdata(priv, data); -} - -/**************************************************************************** - * Name: stm32_backlight - * - * Description: - * Write LCD data (GRAM data or register contents) - * - ****************************************************************************/ - -static void stm32_backlight(struct ssd1289_lcd_s *dev, int power) -{ - /* There is no software control over the backlight */ -} - -/**************************************************************************** - * Name: stm32_lcdinput - * - * Description: - * Config data lines for input operations. - * - ****************************************************************************/ - -#ifndef CONFIG_LCD_NOGETRUN -static void stm32_lcdinput(struct stm32_lower_s *priv) -{ -#ifndef CONFIG_LCD_FASTCONFIG - int i; -#endif - - /* Check if we are already configured for input */ - - if (priv->output) - { - /* Configure GPIO data lines as inputs */ - -#ifdef CONFIG_LCD_FASTCONFIG - putreg32(LCD_INPUT, LCD_CRL); - putreg32(LCD_INPUT, LCD_CRH); -#else - for (i = 0; i < 16; i++) - { - stm32_configgpio(g_lcdin[i]); - } -#endif - - /* No longer configured for output */ - - priv->output = false; - } -} -#endif - -/**************************************************************************** - * Name: stm32_lcdoutput - * - * Description: - * Config data lines for output operations. - * - ****************************************************************************/ - -static void stm32_lcdoutput(struct stm32_lower_s *priv) -{ -#ifndef CONFIG_LCD_FASTCONFIG - int i; -#endif - - /* Check if we are already configured for output */ - - if (!priv->output) - { - /* Configure GPIO data lines as outputs */ - -#ifdef CONFIG_LCD_FASTCONFIG - putreg32(LCD_OUTPUT, LCD_CRL); - putreg32(LCD_OUTPUT, LCD_CRH); -#else - for (i = 0; i < 16; i++) - { - stm32_configgpio(g_lcdout[i]); - } -#endif - - /* Now we are configured for output */ - - priv->output = true; - } -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_lcd_initialize - * - * Description: - * Initialize the LCD video hardware. - * The initial state of the LCD is fully initialized, display memory - * cleared, and the LCD ready to use, but with the power setting at 0 - * (full off). - * - ****************************************************************************/ - -int board_lcd_initialize(void) -{ - struct stm32_lower_s *priv = &g_lcdlower; - int i; - - /* Only initialize the driver once */ - - if (!priv->drvr) - { - lcdinfo("Initializing\n"); - - /* Configure GPIO pins */ - - stm32_lcdoutput(priv); - for (i = 0; i < NLCD_CONFIG; i++) - { - stm32_configgpio(g_lcdconfig[i]); - } - - /* Configure and enable the LCD */ - - priv->drvr = ssd1289_lcdinitialize(&priv->dev); - if (!priv->drvr) - { - lcderr("ERROR: ssd1289_lcdinitialize failed\n"); - return -ENODEV; - } - } - - /* Turn the display off */ - - priv->drvr->setpower(priv->drvr, 0); - return OK; -} - -/**************************************************************************** - * Name: board_lcd_getdev - * - * Description: - * Return a a reference to the LCD object for the specified LCD. - * This allows support for multiple LCD devices. - * - ****************************************************************************/ - -struct lcd_dev_s *board_lcd_getdev(int lcddev) -{ - struct stm32_lower_s *priv = &g_lcdlower; - DEBUGASSERT(lcddev == 0); - return priv->drvr; -} - -/**************************************************************************** - * Name: board_lcd_uninitialize - * - * Description: - * Uninitialize the LCD support - * - ****************************************************************************/ - -void board_lcd_uninitialize(void) -{ - struct stm32_lower_s *priv = &g_lcdlower; - - /* Turn the display off */ - - priv->drvr->setpower(priv->drvr, 0); -} - -#endif /* CONFIG_LCD_SSD1289 */ diff --git a/boards/arm/stm32/shenzhou/src/stm32_touchscreen.c b/boards/arm/stm32/shenzhou/src/stm32_touchscreen.c deleted file mode 100644 index 537e004b629c5..0000000000000 --- a/boards/arm/stm32/shenzhou/src/stm32_touchscreen.c +++ /dev/null @@ -1,276 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/shenzhou/src/stm32_touchscreen.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include - -#include "stm32.h" -#include "shenzhou.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -#ifdef CONFIG_INPUT_ADS7843E -#ifndef CONFIG_INPUT -# error "Touchscreen support requires CONFIG_INPUT" -#endif - -#ifndef CONFIG_STM32_SPI3 -# error "Touchscreen support requires CONFIG_STM32_SPI3" -#endif - -#ifndef CONFIG_ADS7843E_FREQUENCY -# define CONFIG_ADS7843E_FREQUENCY 500000 -#endif - -#ifndef CONFIG_ADS7843E_SPIDEV -# define CONFIG_ADS7843E_SPIDEV 3 -#endif - -#if CONFIG_ADS7843E_SPIDEV != 3 -# error "CONFIG_ADS7843E_SPIDEV must be three" -#endif - -#ifndef CONFIG_ADS7843E_DEVMINOR -# define CONFIG_ADS7843E_DEVMINOR 0 -#endif - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -struct stm32_config_s -{ - struct ads7843e_config_s dev; - xcpt_t handler; -}; - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -/* IRQ/GPIO access callbacks. These operations all hidden behind - * callbacks to isolate the ADS7843E driver from differences in GPIO - * interrupt handling by varying boards and MCUs. If possible, - * interrupts should be configured on both rising and falling edges - * so that contact and loss-of-contact events can be detected. - * - * attach - Attach the ADS7843E interrupt handler to the GPIO interrupt - * enable - Enable or disable the GPIO interrupt - * clear - Acknowledge/clear any pending GPIO interrupt - * pendown - Return the state of the pen down GPIO input - */ - -static int tsc_attach(struct ads7843e_config_s *state, xcpt_t isr); -static void tsc_enable(struct ads7843e_config_s *state, bool enable); -static void tsc_clear(struct ads7843e_config_s *state); -static bool tsc_busy(struct ads7843e_config_s *state); -static bool tsc_pendown(struct ads7843e_config_s *state); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* A reference to a structure of this type must be passed to the ADS7843E - * driver. This structure provides information about the configuration - * of the ADS7843E and provides some board-specific hooks. - * - * Memory for this structure is provided by the caller. It is not copied - * by the driver and is presumed to persist while the driver is active. The - * memory must be writable because, under certain circumstances, the driver - * may modify frequency or X plate resistance values. - */ - -static struct stm32_config_s g_tscinfo = -{ - { - .frequency = CONFIG_ADS7843E_FREQUENCY, - .attach = tsc_attach, - .enable = tsc_enable, - .clear = tsc_clear, - .busy = tsc_busy, - .pendown = tsc_pendown, - }, - .handler = NULL, -}; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/* IRQ/GPIO access callbacks. These operations all hidden behind - * callbacks to isolate the ADS7843E driver from differences in GPIO - * interrupt handling by varying boards and MCUs. If possible, - * interrupts should be configured on both rising and falling edges - * so that contact and loss-of-contact events can be detected. - * - * attach - Attach the ADS7843E interrupt handler to the GPIO interrupt - * enable - Enable or disable the GPIO interrupt - * clear - Acknowledge/clear any pending GPIO interrupt - * pendown - Return the state of the pen down GPIO input - */ - -static int tsc_attach(struct ads7843e_config_s *state, xcpt_t handler) -{ - struct stm32_config_s *priv = (struct stm32_config_s *)state; - - /* Just save the handler for use when the interrupt is enabled */ - - priv->handler = handler; - return OK; -} - -static void tsc_enable(struct ads7843e_config_s *state, bool enable) -{ - struct stm32_config_s *priv = (struct stm32_config_s *)state; - - /* The caller should not attempt to enable interrupts if the handler - * has not yet been 'attached' - */ - - DEBUGASSERT(priv->handler || !enable); - - /* Attach and enable, or detach and disable */ - - iinfo("enable:%d\n", enable); - if (enable) - { - stm32_gpiosetevent(GPIO_TP_INT, true, true, false, - priv->handler, NULL); - } - else - { - stm32_gpiosetevent(GPIO_TP_INT, false, false, false, - NULL, NULL); - } -} - -static void tsc_clear(struct ads7843e_config_s *state) -{ - /* Does nothing */ -} - -static bool tsc_busy(struct ads7843e_config_s *state) -{ - /* Hmmm... The ADS7843E BUSY pin is not brought out on the Shenzhou board. - * We will most certainly have to revisit this. There is this cryptic - * statement in the XPT2046 spec: "No DCLK delay required with dedicated - * serial port." - * - * The busy state is used by the ADS7843E driver to control the delay - * between sending the command, then reading the returned data. - */ - - return false; -} - -static bool tsc_pendown(struct ads7843e_config_s *state) -{ - /* XPT2046 uses an an internal pullup resistor. The PENIRQ output goes low - * due to the current path through the touch screen to ground, which - * initiates an interrupt to the processor via TP_INT. - */ - - bool pendown = !stm32_gpioread(GPIO_TP_INT); - iinfo("pendown:%d\n", pendown); - return pendown; -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_tsc_setup - * - * Description: - * This function is called by board-bringup logic to configure the - * touchscreen device. This function will register the driver as - * /dev/inputN where N is the minor device number. - * - * Input Parameters: - * minor - The input device minor number - * - * Returned Value: - * Zero is returned on success. Otherwise, a negated errno value is - * returned to indicate the nature of the failure. - * - ****************************************************************************/ - -int stm32_tsc_setup(int minor) -{ - struct spi_dev_s *dev; - int ret; - - iinfo("minor %d\n", minor); - DEBUGASSERT(minor == 0); - - /* Configure and enable the ADS7843E interrupt pin as an input. */ - - stm32_configgpio(GPIO_TP_INT); - - /* Get an instance of the SPI interface */ - - dev = stm32_spibus_initialize(CONFIG_ADS7843E_SPIDEV); - if (!dev) - { - ierr("ERROR: Failed to initialize SPI bus %d\n", - CONFIG_ADS7843E_SPIDEV); - return -ENODEV; - } - - /* Initialize and register the SPI touschscreen device */ - - ret = ads7843e_register(dev, &g_tscinfo.dev, - CONFIG_ADS7843E_DEVMINOR); - if (ret < 0) - { - ierr("ERROR: Failed to initialize SPI bus %d\n", - CONFIG_ADS7843E_SPIDEV); - - /* up_spiuninitialize(dev); */ - - return -ENODEV; - } - - return OK; -} - -#endif /* CONFIG_INPUT_ADS7843E */ diff --git a/boards/arm/stm32/shenzhou/src/stm32_usb.c b/boards/arm/stm32/shenzhou/src/stm32_usb.c deleted file mode 100644 index 6660fca6bf810..0000000000000 --- a/boards/arm/stm32/shenzhou/src/stm32_usb.c +++ /dev/null @@ -1,304 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/shenzhou/src/stm32_usb.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -#include "arm_internal.h" -#include "stm32.h" -#include "stm32_otgfs.h" -#include "shenzhou.h" - -#ifdef CONFIG_STM32_OTGFS - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#if defined(CONFIG_USBDEV) || defined(CONFIG_USBHOST) -# define HAVE_USB 1 -#else -# warning "CONFIG_STM32_OTGFS is enabled but neither CONFIG_USBDEV nor CONFIG_USBHOST" -# undef HAVE_USB -#endif - -#ifndef CONFIG_USBHOST_DEFPRIO -# define CONFIG_USBHOST_DEFPRIO 50 -#endif - -#ifndef CONFIG_USBHOST_STACKSIZE -# ifdef CONFIG_USBHOST_HUB -# define CONFIG_USBHOST_STACKSIZE 1536 -# else -# define CONFIG_USBHOST_STACKSIZE 1024 -# endif -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -#ifdef CONFIG_USBHOST -static struct usbhost_connection_s *g_usbconn; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: usbhost_waiter - * - * Description: - * Wait for USB devices to be connected. - * - ****************************************************************************/ - -#ifdef CONFIG_USBHOST -static int usbhost_waiter(int argc, char *argv[]) -{ - struct usbhost_hubport_s *hport; - - uinfo("Running\n"); - for (; ; ) - { - /* Wait for the device to change state */ - - DEBUGVERIFY(CONN_WAIT(g_usbconn, &hport)); - uinfo("%s\n", hport->connected ? "connected" : "disconnected"); - - /* Did we just become connected? */ - - if (hport->connected) - { - /* Yes.. enumerate the newly connected device */ - - CONN_ENUMERATE(g_usbconn, hport); - } - } - - /* Keep the compiler from complaining */ - - return 0; -} -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_usbinitialize - * - * Description: - * Called from stm32_usbinitialize very early in initialization to setup - * USB-related GPIO pins for the STM3240G-EVAL board. - * - ****************************************************************************/ - -void stm32_usbinitialize(void) -{ - /* The OTG FS has an internal soft pull-up. - * No GPIO configuration is required - */ - - /* Configure the OTG FS VBUS sensing GPIO, - * Power On, and Overcurrent GPIOs - */ - -#ifdef CONFIG_STM32_OTGFS - stm32_configgpio(GPIO_OTGFS_VBUS); - stm32_configgpio(GPIO_OTGFS_PWRON); - stm32_configgpio(GPIO_OTGFS_OVER); -#endif -} - -/**************************************************************************** - * Name: stm32_usbhost_initialize - * - * Description: - * Called at application startup time to initialize the USB host - * functionality. - * This function will start a thread that will monitor for device - * connection/disconnection events. - * - ****************************************************************************/ - -#ifdef CONFIG_USBHOST -int stm32_usbhost_initialize(void) -{ - int ret; - - /* First, register all of the class drivers needed to support the drivers - * that we care about: - */ - - uinfo("Register class drivers\n"); - -#ifdef CONFIG_USBHOST_MSC - /* Register the USB mass storage class class */ - - ret = usbhost_msc_initialize(); - if (ret != OK) - { - uerr("ERROR: Failed to register the mass storage class: %d\n", ret); - } -#endif - -#ifdef CONFIG_USBHOST_CDCACM - /* Register the CDC/ACM serial class */ - - ret = usbhost_cdcacm_initialize(); - if (ret != OK) - { - uerr("ERROR: Failed to register the CDC/ACM serial class: %d\n", ret); - } -#endif - - /* Then get an instance of the USB host interface */ - - uinfo("Initialize USB host\n"); - g_usbconn = stm32_otgfshost_initialize(0); - if (g_usbconn) - { - /* Start a thread to handle device connection. */ - - uinfo("Start usbhost_waiter\n"); - - ret = kthread_create("usbhost", CONFIG_USBHOST_DEFPRIO, - CONFIG_USBHOST_STACKSIZE, - usbhost_waiter, NULL); - return ret < 0 ? -ENOEXEC : OK; - } - - return -ENODEV; -} -#endif - -/**************************************************************************** - * Name: stm32_usbhost_vbusdrive - * - * Description: - * Enable/disable driving of VBUS 5V output. This function must be - * provided be each platform that implements the STM32 OTG FS host - * interface - * - * "On-chip 5 V VBUS generation is not supported. For this reason, a - * charge pump or, if 5 V are available on the application board, a - * basic power switch, must be added externally to drive the 5 V VBUS - * line. The external charge pump can be driven by any GPIO output. - * When the application decides to power on VBUS using the chosen GPIO, - * it must also set the port power bit in the host port control and - * status register (PPWR bit in OTG_FS_HPRT). - * - * "The application uses this field to control power to this port, - * and the core clears this bit on an overcurrent condition." - * - * Input Parameters: - * iface - For future growth to handle multiple USB host interface. - * Should be zero. - * enable - true: enable VBUS power; false: disable VBUS power - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef CONFIG_USBHOST -void stm32_usbhost_vbusdrive(int iface, bool enable) -{ - DEBUGASSERT(iface == 0); - - if (enable) - { - /* Enable the Power Switch by driving the enable pin low */ - - stm32_gpiowrite(GPIO_OTGFS_PWRON, false); - } - else - { - /* Disable the Power Switch by driving the enable pin high */ - - stm32_gpiowrite(GPIO_OTGFS_PWRON, true); - } -} -#endif - -/**************************************************************************** - * Name: stm32_setup_overcurrent - * - * Description: - * Setup to receive an interrupt-level callback if an overcurrent - * condition is detected. - * - * Input Parameters: - * handler - New overcurrent interrupt handler - * arg - The argument provided for the interrupt handler - * - * Returned Value: - * Zero (OK) is returned on success. Otherwise, a negated errno value - * is returned to indicate the nature of the failure. - * - ****************************************************************************/ - -#ifdef CONFIG_USBHOST -int stm32_setup_overcurrent(xcpt_t handler, void *arg) -{ - return -ENOSYS; -} -#endif - -/**************************************************************************** - * Name: stm32_usbsuspend - * - * Description: - * Board logic must provide the stm32_usbsuspend logic if the USBDEV - * driver is used. This function is called whenever the USB enters or - * leaves suspend mode. This is an opportunity for the board logic to - * shutdown clocks, power, etc. while the USB is suspended. - * - ****************************************************************************/ - -#ifdef CONFIG_USBDEV -void stm32_usbsuspend(struct usbdev_s *dev, bool resume) -{ - uinfo("resume: %d\n", resume); -} -#endif - -#endif /* CONFIG_STM32_OTGFS */ diff --git a/boards/arm/stm32/shenzhou/src/stm32_usbmsc.c b/boards/arm/stm32/shenzhou/src/stm32_usbmsc.c deleted file mode 100644 index 4e9f496f1320a..0000000000000 --- a/boards/arm/stm32/shenzhou/src/stm32_usbmsc.c +++ /dev/null @@ -1,72 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/shenzhou/src/stm32_usbmsc.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include - -#include "stm32.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -#ifndef CONFIG_SYSTEM_USBMSC_DEVMINOR1 -# define CONFIG_SYSTEM_USBMSC_DEVMINOR1 0 -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_usbmsc_initialize - * - * Description: - * Perform architecture specific initialization as needed to establish - * the mass storage device that will be exported by the USB MSC device. - * - ****************************************************************************/ - -int board_usbmsc_initialize(int port) -{ - /* If system/usbmsc is built as an NSH command, then SD slot should - * already have been initialized. - * In this case, there is nothing further to be done here. - */ - -#ifndef CONFIG_NSH_BUILTIN_APPS - return stm32_sdinitialize(CONFIG_SYSTEM_USBMSC_DEVMINOR1); -#else - return OK; -#endif -} diff --git a/boards/arm/stm32/shenzhou/src/stm32_userleds.c b/boards/arm/stm32/shenzhou/src/stm32_userleds.c deleted file mode 100644 index 52d3107e2fa91..0000000000000 --- a/boards/arm/stm32/shenzhou/src/stm32_userleds.c +++ /dev/null @@ -1,96 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/shenzhou/src/stm32_userleds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32.h" -#include "shenzhou.h" - -#ifndef CONFIG_ARCH_LEDS - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* This array maps an LED number to GPIO pin configuration */ - -static uint32_t g_ledcfg[BOARD_NLEDS] = -{ - GPIO_LED1, GPIO_LED2, GPIO_LED3, GPIO_LED4 -}; - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_userled_initialize - ****************************************************************************/ - -uint32_t board_userled_initialize(void) -{ - /* Configure LED1-4 GPIOs for output */ - - stm32_configgpio(GPIO_LED1); - stm32_configgpio(GPIO_LED2); - stm32_configgpio(GPIO_LED3); - stm32_configgpio(GPIO_LED4); - return BOARD_NLEDS; -} - -/**************************************************************************** - * Name: board_userled - ****************************************************************************/ - -void board_userled(int led, bool ledon) -{ - if ((unsigned)led < BOARD_NLEDS) - { - stm32_gpiowrite(g_ledcfg[led], ledon); - } -} - -/**************************************************************************** - * Name: board_userled_all - ****************************************************************************/ - -void board_userled_all(uint32_t ledset) -{ - stm32_gpiowrite(GPIO_LED1, (ledset & BOARD_LED1_BIT) == 0); - stm32_gpiowrite(GPIO_LED2, (ledset & BOARD_LED2_BIT) == 0); - stm32_gpiowrite(GPIO_LED3, (ledset & BOARD_LED3_BIT) == 0); - stm32_gpiowrite(GPIO_LED4, (ledset & BOARD_LED4_BIT) == 0); -} - -#endif /* !CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/shenzhou/src/stm32_w25.c b/boards/arm/stm32/shenzhou/src/stm32_w25.c deleted file mode 100644 index 861d79a855098..0000000000000 --- a/boards/arm/stm32/shenzhou/src/stm32_w25.c +++ /dev/null @@ -1,145 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/shenzhou/src/stm32_w25.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include - -#ifdef CONFIG_STM32_SPI1 -# include -# include -# include -# include - -# include "stm32_spi.h" -#endif - -#include "shenzhou.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -/* Can't support the W25 device if it SPI1 or W25 support is not enabled */ - -#define HAVE_W25 1 -#if !defined(CONFIG_STM32_SPI1) || !defined(CONFIG_MTD_W25) -# undef HAVE_W25 -#endif - -/* Can't support W25 features if mountpoints are disabled */ - -#if defined(CONFIG_DISABLE_MOUNTPOINT) -# undef HAVE_W25 -#endif - -/* Can't support both FAT and NXFFS */ - -#if defined(CONFIG_FS_FAT) && defined(CONFIG_FS_NXFFS) -# warning "Can't support both FAT and NXFFS -- using FAT" -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_w25initialize - * - * Description: - * Initialize and register the W25 FLASH file system. - * - ****************************************************************************/ - -int stm32_w25initialize(int minor) -{ -#ifdef HAVE_W25 - struct spi_dev_s *spi; - struct mtd_dev_s *mtd; -#ifdef CONFIG_FS_NXFFS - char devname[12]; -#endif - int ret; - - /* Get the SPI port */ - - spi = stm32_spibus_initialize(1); - if (!spi) - { - ferr("ERROR: Failed to initialize SPI port 2\n"); - return -ENODEV; - } - - /* Now bind the SPI interface to the W25 SPI FLASH driver */ - - mtd = w25_initialize(spi); - if (!mtd) - { - ferr("ERROR: Failed to bind SPI port 2 to the SST 25 FLASH driver\n"); - return -ENODEV; - } - -#ifndef CONFIG_FS_NXFFS - /* Register the MTD driver */ - - char path[32]; - snprintf(path, sizeof(path), "/dev/mtdblock%d", minor); - ret = register_mtddriver(path, mtd, 0755, NULL); - if (ret < 0) - { - ferr("ERROR: Failed to register the MTD driver %s, ret %d\n", - path, ret); - return ret; - } -#else - /* Initialize to provide NXFFS on the MTD interface */ - - ret = nxffs_initialize(mtd); - if (ret < 0) - { - ferr("ERROR: NXFFS initialization failed: %d\n", -ret); - return ret; - } - - /* Mount the file system at /mnt/w25 */ - - snprintf(devname, sizeof(devname), "/mnt/w25%c", 'a' + minor); - ret = nx_mount(NULL, devname, "nxffs", 0, NULL); - if (ret < 0) - { - ferr("ERROR: Failed to mount the NXFFS volume: %d\n", ret); - return ret; - } -#endif -#endif - - return OK; -} diff --git a/boards/arm/stm32/shenzhou/tools/oocd.sh b/boards/arm/stm32/shenzhou/tools/oocd.sh deleted file mode 100755 index 136a792c6f9ef..0000000000000 --- a/boards/arm/stm32/shenzhou/tools/oocd.sh +++ /dev/null @@ -1,90 +0,0 @@ -#!/usr/bin/env bash - -# Get command line parameters - -USAGE="USAGE: $0 [-dh] " -ADVICE="Try '$0 -h' for more information" - -unset DEBUG - -while [ ! -z "$1" ]; do - case $1 in - -d ) - set -x - DEBUG=-d3 - ;; - -h ) - echo "$0 is a tool for generation of proper version files for the NuttX build" - echo "" - echo $USAGE - echo "" - echo "Where:" - echo " -d" - echo " Enable script debug" - echo " -h" - echo " show this help message and exit" - echo " Use the OpenOCD 0.4.0" - echo " " - echo " The full path to the top-level NuttX directory" - exit 0 - ;; - * ) - break; - ;; - esac - shift -done - -TOPDIR=$1 -if [ -z "${TOPDIR}" ]; then - echo "Missing argument" - echo $USAGE - echo $ADVICE - exit 1 -fi - -# This script *probably* only works with the following versions of OpenOCD: - -# Local search directory and configurations - -OPENOCD_SEARCHDIR="${TOPDIR}/boards/arm/stm32/shenzhou/tools" -OPENOCD_WSEARCHDIR="`cygpath -w ${OPENOCD_SEARCHDIR}`" - -OPENOCD_PATH="/cygdrive/c/Program Files (x86)/OpenOCD/0.4.0/bin" -OPENOCD_EXE=openocd.exe -OPENOCD_INTERFACE="olimex-arm-usb-ocd.cfg" - -OPENOCD_TARGET="stm32.cfg" -OPENOCD_ARGS="${DEBUG} -s ${OPENOCD_WSEARCHDIR} -f ${OPENOCD_INTERFACE} -f ${OPENOCD_TARGET}" - -echo "Trying OpenOCD 0.4.0 path: ${OPENOCD_PATH}/${OPENOCD_EXE}" - -# Verify that everything is what it claims it is and is located where it claims it is. - -if [ ! -x "${OPENOCD_PATH}/${OPENOCD_EXE}" ]; then - echo "OpenOCD executable does not exist: ${OPENOCD_PATH}/${OPENOCD_EXE}" - exit 1 -fi -if [ ! -f "${OPENOCD_SEARCHDIR}/${OPENOCD_TARGET}" ]; then - echo "OpenOCD target config file does not exist: ${OPENOCD_SEARCHDIR}/${OPENOCD_TARGET}" - exit 1 -fi -if [ ! -f "${OPENOCD_SEARCHDIR}/${OPENOCD_INTERFACE}" ]; then - echo "OpenOCD interface config file does not exist: ${OPENOCD_SEARCHDIR}/${OPENOCD_INTERFACE}" - exit 1 -fi - -# Enable debug if so requested - -if [ "X$2" = "X-d" ]; then - OPENOCD_ARGS=$OPENOCD_ARGS" -d3" - set -x -fi - -# Okay... do it! - -echo "Starting OpenOCD" -"${OPENOCD_PATH}/${OPENOCD_EXE}" ${OPENOCD_ARGS} & -echo "OpenOCD daemon started" -ps -ef | grep openocd -echo "In GDB: target remote localhost:3333" diff --git a/boards/arm/stm32/stm3210e-eval/CMakeLists.txt b/boards/arm/stm32/stm3210e-eval/CMakeLists.txt deleted file mode 100644 index 7bbea8e4a973f..0000000000000 --- a/boards/arm/stm32/stm3210e-eval/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/stm3210e-eval/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32/stm3210e-eval/configs/composite/defconfig b/boards/arm/stm32/stm3210e-eval/configs/composite/defconfig deleted file mode 100644 index 82259cb815680..0000000000000 --- a/boards/arm/stm32/stm3210e-eval/configs/composite/defconfig +++ /dev/null @@ -1,65 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_MMCSD_HAVE_CARDDETECT is not set -# CONFIG_MMCSD_MMCSUPPORT is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm3210e-eval" -CONFIG_ARCH_BOARD_STM3210E_EVAL=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F103ZE=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARDCTL=y -CONFIG_BOARD_LOOPSPERMSEC=5483 -CONFIG_CDCACM=y -CONFIG_CDCACM_COMPOSITE=y -CONFIG_CDCACM_RXBUFSIZE=256 -CONFIG_CDCACM_TXBUFSIZE=256 -CONFIG_COMPOSITE_CONFIGSTR="system/composite" -CONFIG_COMPOSITE_IAD=y -CONFIG_COMPOSITE_PRODUCTID=0x2022 -CONFIG_COMPOSITE_PRODUCTSTR="Composite Device" -CONFIG_COMPOSITE_SERIALSTR="12345" -CONFIG_COMPOSITE_VENDORID=0x03eb -CONFIG_HOST_WINDOWS=y -CONFIG_INIT_ENTRYPOINT="conn_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_MMCSD=y -CONFIG_MMCSD_SDIO=y -CONFIG_MTD=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=65536 -CONFIG_RAM_START=0x20000000 -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_HPWORKPRIORITY=192 -CONFIG_SCHED_HPWORKSTACKSIZE=1024 -CONFIG_START_DAY=30 -CONFIG_START_MONTH=11 -CONFIG_START_YEAR=2009 -CONFIG_STM32_DFU=y -CONFIG_STM32_DMA2=y -CONFIG_STM32_FSMC=y -CONFIG_STM32_JTAG_FULL_ENABLE=y -CONFIG_STM32_SDIO=y -CONFIG_STM32_USART1=y -CONFIG_STM32_USART2=y -CONFIG_STM32_USB=y -CONFIG_SYMTAB_ORDEREDBYNAME=y -CONFIG_SYSTEM_COMPOSITE=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART1_SERIAL_CONSOLE=y -CONFIG_USBDEV_COMPOSITE=y -CONFIG_USBMSC=y -CONFIG_USBMSC_BULKINREQLEN=256 -CONFIG_USBMSC_BULKOUTREQLEN=256 -CONFIG_USBMSC_COMPOSITE=y -CONFIG_USBMSC_NRDREQS=2 -CONFIG_USBMSC_NWRREQS=2 -CONFIG_USBMSC_REMOVABLE=y -CONFIG_USBMSC_VERSIONNO=0x0399 diff --git a/boards/arm/stm32/stm3210e-eval/configs/nsh/defconfig b/boards/arm/stm32/stm3210e-eval/configs/nsh/defconfig deleted file mode 100644 index 315e9136cf1a8..0000000000000 --- a/boards/arm/stm32/stm3210e-eval/configs/nsh/defconfig +++ /dev/null @@ -1,52 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_MMCSD_HAVE_CARDDETECT is not set -# CONFIG_MMCSD_MMCSUPPORT is not set -# CONFIG_NSH_DISABLE_IFCONFIG is not set -# CONFIG_NSH_DISABLE_PS is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm3210e-eval" -CONFIG_ARCH_BOARD_STM3210E_EVAL=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F103ZE=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_ARM_TOOLCHAIN_BUILDROOT=y -CONFIG_BOARD_LOOPSPERMSEC=5483 -CONFIG_FAT_LCNAMES=y -CONFIG_FS_FAT=y -CONFIG_HOST_WINDOWS=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_MMCSD=y -CONFIG_MMCSD_SDIO=y -CONFIG_MTD=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=65536 -CONFIG_RAM_START=0x20000000 -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_HPWORKPRIORITY=192 -CONFIG_SCHED_HPWORKSTACKSIZE=1024 -CONFIG_START_DAY=21 -CONFIG_START_MONTH=9 -CONFIG_START_YEAR=2009 -CONFIG_STM32_DFU=y -CONFIG_STM32_DMA2=y -CONFIG_STM32_FSMC=y -CONFIG_STM32_JTAG_FULL_ENABLE=y -CONFIG_STM32_SDIO=y -CONFIG_STM32_USART1=y -CONFIG_STM32_USART2=y -CONFIG_STM32_USB=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/stm3210e-eval/configs/nsh2/defconfig b/boards/arm/stm32/stm3210e-eval/configs/nsh2/defconfig deleted file mode 100644 index 0f9b059c5d238..0000000000000 --- a/boards/arm/stm32/stm3210e-eval/configs/nsh2/defconfig +++ /dev/null @@ -1,109 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_EXAMPLES_NXHELLO_DEFAULT_COLORS is not set -# CONFIG_EXAMPLES_NXHELLO_DEFAULT_FONT is not set -# CONFIG_EXAMPLES_NX_DEFAULT_COLORS is not set -# CONFIG_EXAMPLES_NX_DEFAULT_FONT is not set -# CONFIG_MMCSD_HAVE_CARDDETECT is not set -# CONFIG_MMCSD_MMCSUPPORT is not set -# CONFIG_NSH_DISABLE_IFCONFIG is not set -# CONFIG_NSH_DISABLE_PS is not set -# CONFIG_NXFONTS_DISABLE_16BPP is not set -# CONFIG_NXTK_DEFAULT_BORDERCOLORS is not set -# CONFIG_NX_DISABLE_16BPP is not set -# CONFIG_NX_PACKEDMSFIRST is not set -# CONFIG_NX_WRITEONLY is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm3210e-eval" -CONFIG_ARCH_BOARD_STM3210E_EVAL=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F103ZE=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=5483 -CONFIG_BUILTIN=y -CONFIG_EXAMPLES_NX=y -CONFIG_EXAMPLES_NXHELLO=y -CONFIG_EXAMPLES_NXHELLO_BGCOLOR=0x0011 -CONFIG_EXAMPLES_NXHELLO_BPP=16 -CONFIG_EXAMPLES_NXHELLO_FONTCOLOR=0xffdf -CONFIG_EXAMPLES_NXHELLO_FONTID=6 -CONFIG_EXAMPLES_NX_BGCOLOR=0x0011 -CONFIG_EXAMPLES_NX_BPP=16 -CONFIG_EXAMPLES_NX_COLOR1=0xaedc -CONFIG_EXAMPLES_NX_COLOR2=0xe7ff -CONFIG_EXAMPLES_NX_FONTCOLOR=0x0000 -CONFIG_EXAMPLES_NX_FONTID=0 -CONFIG_EXAMPLES_NX_TBCOLOR=0xd69a -CONFIG_FAT_LCNAMES=y -CONFIG_FAT_LFN=y -CONFIG_FS_FAT=y -CONFIG_HOST_WINDOWS=y -CONFIG_I2C=y -CONFIG_I2CTOOL_DEFFREQ=100000 -CONFIG_I2CTOOL_MAXBUS=2 -CONFIG_I2CTOOL_MINBUS=1 -CONFIG_I2C_POLLED=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LCD_MAXCONTRAST=1 -CONFIG_LCD_NOGETRUN=y -CONFIG_LCD_RPORTRAIT=y -CONFIG_LINE_MAX=64 -CONFIG_MMCSD=y -CONFIG_MMCSD_SDIO=y -CONFIG_MQ_MAXMSGSIZE=64 -CONFIG_MTD=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_NX=y -CONFIG_NXFONT_SANS23X27=y -CONFIG_NXFONT_SANS28X37B=y -CONFIG_NXTK_BORDERCOLOR1=0xd69a -CONFIG_NXTK_BORDERCOLOR2=0xad55 -CONFIG_NX_BLOCKING=y -CONFIG_NX_KBD=y -CONFIG_NX_XYINPUT_MOUSE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=65536 -CONFIG_RAM_START=0x20000000 -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_HPWORKPRIORITY=192 -CONFIG_SCHED_HPWORKSTACKSIZE=1024 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=5 -CONFIG_START_MONTH=7 -CONFIG_START_YEAR=2011 -CONFIG_STM3210E_LCD=y -CONFIG_STM3210E_R61580_DISABLE=y -CONFIG_STM32_DFU=y -CONFIG_STM32_DMA2=y -CONFIG_STM32_FSMC=y -CONFIG_STM32_I2C1=y -CONFIG_STM32_JTAG_FULL_ENABLE=y -CONFIG_STM32_SDIO=y -CONFIG_STM32_USART1=y -CONFIG_STM32_USART2=y -CONFIG_STM32_USB=y -CONFIG_SYSTEM_I2CTOOL=y -CONFIG_SYSTEM_NSH=y -CONFIG_SYSTEM_USBMSC=y -CONFIG_SYSTEM_USBMSC_DEVMINOR1=0 -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART1_SERIAL_CONSOLE=y -CONFIG_USBMSC=y -CONFIG_USBMSC_BULKINREQLEN=256 -CONFIG_USBMSC_BULKOUTREQLEN=256 -CONFIG_USBMSC_EPBULKIN=5 -CONFIG_USBMSC_NRDREQS=2 -CONFIG_USBMSC_NWRREQS=2 -CONFIG_USBMSC_PRODUCTSTR="USBdev Storage" -CONFIG_USBMSC_REMOVABLE=y -CONFIG_USBMSC_VERSIONNO=0x0399 diff --git a/boards/arm/stm32/stm3210e-eval/configs/nx/defconfig b/boards/arm/stm32/stm3210e-eval/configs/nx/defconfig deleted file mode 100644 index f221932c7c707..0000000000000 --- a/boards/arm/stm32/stm3210e-eval/configs/nx/defconfig +++ /dev/null @@ -1,71 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_EXAMPLES_NX_DEFAULT_COLORS is not set -# CONFIG_EXAMPLES_NX_DEFAULT_FONT is not set -# CONFIG_NXFONTS_DISABLE_16BPP is not set -# CONFIG_NXTK_DEFAULT_BORDERCOLORS is not set -# CONFIG_NX_DISABLE_16BPP is not set -# CONFIG_NX_PACKEDMSFIRST is not set -# CONFIG_NX_WRITEONLY is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm3210e-eval" -CONFIG_ARCH_BOARD_STM3210E_EVAL=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F103ZE=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=5483 -CONFIG_CONSOLE_SYSLOG=y -CONFIG_DISABLE_ENVIRON=y -CONFIG_DISABLE_MOUNTPOINT=y -CONFIG_DISABLE_POSIX_TIMERS=y -CONFIG_EXAMPLES_NX=y -CONFIG_EXAMPLES_NX_BGCOLOR=0x0011 -CONFIG_EXAMPLES_NX_BPP=16 -CONFIG_EXAMPLES_NX_COLOR1=0xaedc -CONFIG_EXAMPLES_NX_COLOR2=0xe7ff -CONFIG_EXAMPLES_NX_FONTCOLOR=0x0000 -CONFIG_EXAMPLES_NX_FONTID=0 -CONFIG_EXAMPLES_NX_TBCOLOR=0xd69a -CONFIG_HOST_WINDOWS=y -CONFIG_INIT_ENTRYPOINT="nx_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LCD_MAXCONTRAST=1 -CONFIG_LCD_NOGETRUN=y -CONFIG_LCD_RPORTRAIT=y -CONFIG_MQ_MAXMSGSIZE=64 -CONFIG_NX=y -CONFIG_NXFONT_SANS23X27=y -CONFIG_NXTK_BORDERCOLOR1=0xad55 -CONFIG_NXTK_BORDERCOLOR2=0x6b4d -CONFIG_NXTK_BORDERCOLOR3=0xdedb -CONFIG_NX_BLOCKING=y -CONFIG_NX_KBD=y -CONFIG_NX_XYINPUT_MOUSE=y -CONFIG_RAM_SIZE=65536 -CONFIG_RAM_START=0x20000000 -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_HPWORKPRIORITY=192 -CONFIG_SCHED_HPWORKSTACKSIZE=1024 -CONFIG_START_DAY=5 -CONFIG_START_MONTH=7 -CONFIG_START_YEAR=2011 -CONFIG_STM3210E_LCD=y -CONFIG_STM3210E_R61580_DISABLE=y -CONFIG_STM32_DFU=y -CONFIG_STM32_DMA2=y -CONFIG_STM32_FSMC=y -CONFIG_STM32_I2C1=y -CONFIG_STM32_JTAG_FULL_ENABLE=y -CONFIG_STM32_USART1=y -CONFIG_STM32_USART2=y -CONFIG_STM32_USB=y -CONFIG_SYMTAB_ORDEREDBYNAME=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/stm3210e-eval/configs/nxterm/defconfig b/boards/arm/stm32/stm3210e-eval/configs/nxterm/defconfig deleted file mode 100644 index 395633cb5f030..0000000000000 --- a/boards/arm/stm32/stm3210e-eval/configs/nxterm/defconfig +++ /dev/null @@ -1,67 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_NSH_DISABLE_IFCONFIG is not set -# CONFIG_NSH_DISABLE_PS is not set -# CONFIG_NXFONTS_DISABLE_16BPP is not set -# CONFIG_NXTK_DEFAULT_BORDERCOLORS is not set -# CONFIG_NX_DISABLE_16BPP is not set -# CONFIG_NX_PACKEDMSFIRST is not set -# CONFIG_NX_WRITEONLY is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm3210e-eval" -CONFIG_ARCH_BOARD_STM3210E_EVAL=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F103ZE=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=5483 -CONFIG_BUILTIN=y -CONFIG_EXAMPLES_NXTERM=y -CONFIG_HOST_WINDOWS=y -CONFIG_INIT_ENTRYPOINT="nxterm_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LCD_MAXCONTRAST=1 -CONFIG_LCD_NOGETRUN=y -CONFIG_LINE_MAX=64 -CONFIG_MQ_MAXMSGSIZE=64 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_LIBRARY=y -CONFIG_NSH_READLINE=y -CONFIG_NX=y -CONFIG_NXFONT_SANS23X27=y -CONFIG_NXTERM=y -CONFIG_NXTERM_CACHESIZE=32 -CONFIG_NXTERM_CURSORCHAR=95 -CONFIG_NXTERM_MXCHARS=256 -CONFIG_NXTK_BORDERCOLOR1=0xad55 -CONFIG_NXTK_BORDERCOLOR2=0x6b4d -CONFIG_NXTK_BORDERCOLOR3=0xdedb -CONFIG_NX_BLOCKING=y -CONFIG_NX_KBD=y -CONFIG_NX_XYINPUT_MOUSE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=65536 -CONFIG_RAM_START=0x20000000 -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_HPWORKPRIORITY=192 -CONFIG_SCHED_HPWORKSTACKSIZE=1024 -CONFIG_START_DAY=29 -CONFIG_START_MONTH=3 -CONFIG_START_YEAR=2012 -CONFIG_STM3210E_LCD=y -CONFIG_STM3210E_R61580_DISABLE=y -CONFIG_STM32_DFU=y -CONFIG_STM32_DMA2=y -CONFIG_STM32_FSMC=y -CONFIG_STM32_JTAG_FULL_ENABLE=y -CONFIG_STM32_USART1=y -CONFIG_STM32_USART2=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/stm3210e-eval/configs/pm/defconfig b/boards/arm/stm32/stm3210e-eval/configs/pm/defconfig deleted file mode 100644 index 4fd1d15afc423..0000000000000 --- a/boards/arm/stm32/stm3210e-eval/configs/pm/defconfig +++ /dev/null @@ -1,94 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_EXAMPLES_NXHELLO_DEFAULT_COLORS is not set -# CONFIG_EXAMPLES_NXHELLO_DEFAULT_FONT is not set -# CONFIG_EXAMPLES_NX_DEFAULT_COLORS is not set -# CONFIG_EXAMPLES_NX_DEFAULT_FONT is not set -# CONFIG_NSH_DISABLE_IFCONFIG is not set -# CONFIG_NSH_DISABLE_PS is not set -# CONFIG_NXFONTS_DISABLE_16BPP is not set -# CONFIG_NXTK_DEFAULT_BORDERCOLORS is not set -# CONFIG_NX_DISABLE_16BPP is not set -# CONFIG_NX_PACKEDMSFIRST is not set -# CONFIG_NX_WRITEONLY is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm3210e-eval" -CONFIG_ARCH_BOARD_STM3210E_EVAL=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F103ZE=y -CONFIG_ARCH_CUSTOM_PMINIT=y -CONFIG_ARCH_IDLE_CUSTOM=y -CONFIG_ARCH_IRQBUTTONS=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=5483 -CONFIG_BUILTIN=y -CONFIG_EXAMPLES_NX=y -CONFIG_EXAMPLES_NXHELLO=y -CONFIG_EXAMPLES_NXHELLO_BGCOLOR=0x0011 -CONFIG_EXAMPLES_NXHELLO_BPP=16 -CONFIG_EXAMPLES_NXHELLO_FONTCOLOR=0xffdf -CONFIG_EXAMPLES_NXHELLO_FONTID=6 -CONFIG_EXAMPLES_NX_BGCOLOR=0x0011 -CONFIG_EXAMPLES_NX_BPP=16 -CONFIG_EXAMPLES_NX_COLOR1=0xaedc -CONFIG_EXAMPLES_NX_COLOR2=0xe7ff -CONFIG_EXAMPLES_NX_FONTCOLOR=0x0000 -CONFIG_EXAMPLES_NX_FONTID=0 -CONFIG_EXAMPLES_NX_TBCOLOR=0xd69a -CONFIG_HOST_WINDOWS=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LCD_MAXCONTRAST=100 -CONFIG_LCD_MAXPOWER=100 -CONFIG_LCD_NOGETRUN=y -CONFIG_LCD_RPORTRAIT=y -CONFIG_LINE_MAX=64 -CONFIG_MQ_MAXMSGSIZE=64 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_NX=y -CONFIG_NXFONT_SANS23X27=y -CONFIG_NXFONT_SANS28X37B=y -CONFIG_NXTK_BORDERCOLOR1=0xad55 -CONFIG_NXTK_BORDERCOLOR2=0x6b4d -CONFIG_NXTK_BORDERCOLOR3=0xdedb -CONFIG_NX_BLOCKING=y -CONFIG_NX_KBD=y -CONFIG_NX_XYINPUT_TOUCHSCREEN=y -CONFIG_PM=y -CONFIG_PM_BUTTONS=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=65536 -CONFIG_RAM_START=0x20000000 -CONFIG_RR_INTERVAL=200 -CONFIG_RTC_ALARM=y -CONFIG_RTC_FREQUENCY=16384 -CONFIG_RTC_HIRES=y -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_HPWORKPRIORITY=192 -CONFIG_SCHED_HPWORKSTACKSIZE=1024 -CONFIG_SCHED_WAITPID=y -CONFIG_STM3210E_LCD=y -CONFIG_STM3210E_LCD_BACKLIGHT=y -CONFIG_STM3210E_LCD_PWM=y -CONFIG_STM3210E_R61580_DISABLE=y -CONFIG_STM32_BKP=y -CONFIG_STM32_DFU=y -CONFIG_STM32_FSMC=y -CONFIG_STM32_JTAG_FULL_ENABLE=y -CONFIG_STM32_PWR=y -CONFIG_STM32_RTC=y -CONFIG_STM32_TIM1=y -CONFIG_STM32_USART1=y -CONFIG_STM32_USART2=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/stm3210e-eval/configs/usbmsc/defconfig b/boards/arm/stm32/stm3210e-eval/configs/usbmsc/defconfig deleted file mode 100644 index 976438a23932a..0000000000000 --- a/boards/arm/stm32/stm3210e-eval/configs/usbmsc/defconfig +++ /dev/null @@ -1,54 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_MMCSD_HAVE_CARDDETECT is not set -# CONFIG_MMCSD_MMCSUPPORT is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm3210e-eval" -CONFIG_ARCH_BOARD_STM3210E_EVAL=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F103ZE=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_ARM_TOOLCHAIN_BUILDROOT=y -CONFIG_BOARDCTL=y -CONFIG_BOARD_LOOPSPERMSEC=5483 -CONFIG_INIT_ENTRYPOINT="msconn_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_MMCSD=y -CONFIG_MMCSD_SDIO=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=65536 -CONFIG_RAM_START=0x20000000 -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_HPWORKPRIORITY=192 -CONFIG_SCHED_HPWORKSTACKSIZE=1024 -CONFIG_START_DAY=30 -CONFIG_START_MONTH=11 -CONFIG_START_YEAR=2009 -CONFIG_STM32_DFU=y -CONFIG_STM32_DMA2=y -CONFIG_STM32_FSMC=y -CONFIG_STM32_JTAG_FULL_ENABLE=y -CONFIG_STM32_SDIO=y -CONFIG_STM32_USART1=y -CONFIG_STM32_USART2=y -CONFIG_STM32_USB=y -CONFIG_SYSTEM_USBMSC=y -CONFIG_SYSTEM_USBMSC_DEVMINOR1=0 -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART1_SERIAL_CONSOLE=y -CONFIG_USBMSC=y -CONFIG_USBMSC_BULKINREQLEN=256 -CONFIG_USBMSC_BULKOUTREQLEN=256 -CONFIG_USBMSC_EPBULKIN=5 -CONFIG_USBMSC_NRDREQS=2 -CONFIG_USBMSC_NWRREQS=2 -CONFIG_USBMSC_PRODUCTSTR="USBdev Storage" -CONFIG_USBMSC_REMOVABLE=y -CONFIG_USBMSC_VERSIONNO=0x0399 diff --git a/boards/arm/stm32/stm3210e-eval/configs/usbserial/defconfig b/boards/arm/stm32/stm3210e-eval/configs/usbserial/defconfig deleted file mode 100644 index 205b97bbc4ebd..0000000000000 --- a/boards/arm/stm32/stm3210e-eval/configs/usbserial/defconfig +++ /dev/null @@ -1,40 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm3210e-eval" -CONFIG_ARCH_BOARD_STM3210E_EVAL=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F103ZE=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_ARM_TOOLCHAIN_BUILDROOT_OABI=y -CONFIG_BOARDCTL=y -CONFIG_BOARD_LOOPSPERMSEC=5483 -CONFIG_DISABLE_MOUNTPOINT=y -CONFIG_EXAMPLES_USBSERIAL=y -CONFIG_INIT_ENTRYPOINT="usbserial_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_PL2303=y -CONFIG_PL2303_PRODUCTSTR="USBdev Serial" -CONFIG_PL2303_RXBUFSIZE=512 -CONFIG_PL2303_TXBUFSIZE=512 -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=65536 -CONFIG_RAM_START=0x20000000 -CONFIG_RR_INTERVAL=200 -CONFIG_START_DAY=23 -CONFIG_START_MONTH=10 -CONFIG_START_YEAR=2009 -CONFIG_STM32_DFU=y -CONFIG_STM32_FSMC=y -CONFIG_STM32_JTAG_FULL_ENABLE=y -CONFIG_STM32_USART1=y -CONFIG_STM32_USART2=y -CONFIG_STM32_USB=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/stm3210e-eval/include/board.h b/boards/arm/stm32/stm3210e-eval/include/board.h deleted file mode 100644 index 6f3c44144929d..0000000000000 --- a/boards/arm/stm32/stm3210e-eval/include/board.h +++ /dev/null @@ -1,402 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm3210e-eval/include/board.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __BOARDS_ARM_STM32_STM3210E_EVAL_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32_STM3210E_EVAL_INCLUDE_BOARD_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#ifndef __ASSEMBLY__ -# include -#endif - -/* Logic in arch/arm/src and boards/ may need to include these file prior to - * including board.h: stm32_rcc.h, stm32_sdio.h, stm32.h. They cannot be - * included here because board.h is used in other contexts where the STM32 - * internal header files are not available. - */ - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Clocking *****************************************************************/ - -/* On-board crystal frequency is 8MHz (HSE) */ - -#define STM32_BOARD_XTAL 8000000ul - -/* PLL source is HSE/1, PLL multiplier is 9: - * PLL frequency is 8MHz (XTAL) x 9 = 72MHz - */ - -#define STM32_CFGR_PLLSRC RCC_CFGR_PLLSRC -#define STM32_CFGR_PLLXTPRE 0 -#define STM32_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx9 -#define STM32_PLL_FREQUENCY (9*STM32_BOARD_XTAL) - -/* Use the PLL and set the SYSCLK source to be the PLL */ - -#define STM32_SYSCLK_SW RCC_CFGR_SW_PLL -#define STM32_SYSCLK_SWS RCC_CFGR_SWS_PLL -#define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY - -/* AHB clock (HCLK) is SYSCLK (72MHz) */ - -#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK -#define STM32_HCLK_FREQUENCY STM32_PLL_FREQUENCY - -/* APB2 clock (PCLK2) is HCLK (72MHz) */ - -#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK -#define STM32_PCLK2_FREQUENCY STM32_HCLK_FREQUENCY -#define STM32_APB2_CLKIN (STM32_PCLK2_FREQUENCY) /* Timers 2-7, 12-14 */ - -/* APB2 timers 1 and 8 will receive PCLK2. */ - -#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) - -/* APB1 clock (PCLK1) is HCLK/2 (36MHz) */ - -#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd2 -#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/2) - -/* APB1 timers 2-7 will be twice PCLK1 */ - -#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) - -/* USB divider -- Divide PLL clock by 1.5 */ - -#define STM32_CFGR_USBPRE 0 - -/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx - * otherwise frequency is 2xAPBx. - * Note: TIM1,8 are on APB2, others on APB1 - */ - -#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM2_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM3_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM4_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM5_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM6_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM7_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY - -/* SDIO dividers. Note that slower clocking is required when DMA is disabled - * in order to avoid RX overrun/TX underrun errors due to delayed responses - * to service FIFOs in interrupt driven mode. These values have not been - * tuned!!! - * - * HCLK=72MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(178+2)=400 KHz - */ - -#define SDIO_INIT_CLKDIV (178 << SDIO_CLKCR_CLKDIV_SHIFT) - -/* DMA ON: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(2+2)=18 MHz - * DMA OFF: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(3+2)=14.4 MHz - */ - -#ifdef CONFIG_SDIO_DMA -# define SDIO_MMCXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT) -#else -# define SDIO_MMCXFR_CLKDIV (3 << SDIO_CLKCR_CLKDIV_SHIFT) -#endif - -/* DMA ON: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(1+2)=24 MHz - * DMA OFF: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(3+2)=14.4 MHz - */ - -#ifdef CONFIG_SDIO_DMA -# define SDIO_SDXFR_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT) -#else -# define SDIO_SDXFR_CLKDIV (3 << SDIO_CLKCR_CLKDIV_SHIFT) -#endif - -/* SRAM definitions *********************************************************/ - -/* The 8 Mbit SRAM is provided on the PT3 board using the FSMC_NE3 chip - * select. - */ - -/* This is the Bank1 SRAM3 address: */ - -#define BOARD_SRAM_BASE 0x68000000 /* Bank2 SRAM3 base address */ -#define BOARD_SRAM_SIZE (1*1024*1024) /* 8-Mbit = 1-Mbyte */ - -/* LED definitions **********************************************************/ - -/* The STM3210E-EVAL board has 4 LEDs that we will encode as: */ - -#define LED_STARTED 0 /* LED1 */ -#define LED_HEAPALLOCATE 1 /* LED2 */ -#define LED_IRQSENABLED 2 /* LED1 + LED2 */ -#define LED_STACKCREATED 3 /* LED3 */ -#define LED_INIRQ 4 /* LED1 + LED3 */ -#define LED_SIGNAL 5 /* LED2 + LED3 */ -#define LED_ASSERTION 6 /* LED1 + LED2 + LED3 */ -#define LED_PANIC 7 /* N/C + N/C + N/C + LED4 */ - -/* The STM3210E-EVAL supports several buttons - * - * Reset -- Connected to NRST - * Wakeup -- Connected to PA.0 - * Tamper -- Connected to PC.13 - * Key -- Connected to PG.8 - * - * And a Joystick - * - * Joystick center -- Connected to PG.7 - * Joystick down -- Connected to PD.3 - * Joystick left -- Connected to PG.14 - * Joystick right -- Connected to PG.13 - * Joystick up -- Connected to PG.15 - * - * The Joystick is treated like the other buttons unless - * CONFIG_INPUT_DJOYSTICK is defined, then it is assumed that they should be - * used by the discrete joystick driver. - */ - -#define BUTTON_WAKEUP 0 -#define BUTTON_TAMPER 1 -#define BUTTON_KEY 2 - -#ifdef CONFIG_INPUT_DJOYSTICK -# define NUM_BUTTONS 3 -#else -# define JOYSTICK_SEL 3 -# define JOYSTICK_DOWN 4 -# define JOYSTICK_LEFT 5 -# define JOYSTICK_RIGHT 6 -# define JOYSTICK_UP 7 - -# define NUM_BUTTONS 8 -#endif - -#define BUTTON_WAKEUP_BIT (1 << BUTTON_WAKEUP) -#define BUTTON_TAMPER_BIT (1 << BUTTON_TAMPER) -#define BUTTON_KEY_BIT (1 << BUTTON_KEY) - -#ifndef CONFIG_INPUT_DJOYSTICK -# define JOYSTICK_SEL_BIT (1 << JOYSTICK_SEL) -# define JOYSTICK_DOWN_BIT (1 << JOYSTICK_DOWN) -# define JOYSTICK_LEFT_BIT (1 << JOYSTICK_LEFT) -# define JOYSTICK_RIGHT_BIT (1 << JOYSTICK_RIGHT) -# define JOYSTICK_UP_BIT (1 << JOYSTICK_UP) -#endif - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -#ifndef __ASSEMBLY__ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: stm3210e_lcdclear - * - * Description: - * This is a non-standard LCD interface just for the STM3210E-EVAL board. - * Because of the various rotations, clearing the display in the normal - * way by writing a sequences of runs that covers the entire display can - * be very slow. Here the display is cleared by simply setting all GRAM - * memory to the specified color. - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_FSMC -void stm3210e_lcdclear(uint16_t color); -#endif - -/**************************************************************************** - * Name: stm32_lm75initialize - * - * Description: - * Initialize and register the LM-75 Temperature Sensor driver. - * - * Input Parameters: - * devpath - The full path to the driver to register. E.g., "/dev/temp0" - * - * Returned Value: - * Zero (OK) on success; a negated errno value on failure. - * - ****************************************************************************/ - -#if defined(CONFIG_I2C) && defined(CONFIG_LM75_I2C) && defined(CONFIG_STM32_I2C1) -int stm32_lm75initialize(const char *devpath); -#endif - -/**************************************************************************** - * Name: stm32_lm75attach - * - * Description: - * Attach the LM-75 interrupt handler - * - * Input Parameters: - * irqhandler - the LM-75 interrupt handler - * arg - The argument that will accompany the interrupt - * - * Returned Value: - * Zero (OK) returned on success; a negated errno value is returned on - * failure. - * - ****************************************************************************/ - -#if defined(CONFIG_I2C) && defined(CONFIG_LM75_I2C) && defined(CONFIG_STM32_I2C1) -int stm32_lm75attach(xcpt_t irqhandler, void *arg); -#endif - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ - -/* Alternate function pin selections (auto-aliased for new pinmap) */ - -/* USART1 */ - -#define GPIO_USART1_TX GPIO_ADJUST_MODE(GPIO_USART1_TX_0, GPIO_MODE_50MHz) -#define GPIO_USART1_RX GPIO_USART1_RX_0 - -/* USART2 */ - -#define GPIO_USART2_TX GPIO_ADJUST_MODE(GPIO_USART2_TX_0, GPIO_MODE_50MHz) -#define GPIO_USART2_RX GPIO_USART2_RX_0 -#define GPIO_USART2_CTS GPIO_USART2_CTS_0 -#define GPIO_USART2_RTS GPIO_ADJUST_MODE(GPIO_USART2_RTS_0, GPIO_MODE_50MHz) -#define GPIO_USART2_CK GPIO_ADJUST_MODE(GPIO_USART2_CK_0, GPIO_MODE_50MHz) - -/* I2C1 */ - -#define GPIO_I2C1_SCL GPIO_ADJUST_MODE(GPIO_I2C1_SCL_0, GPIO_MODE_50MHz) -#define GPIO_I2C1_SDA GPIO_ADJUST_MODE(GPIO_I2C1_SDA_0, GPIO_MODE_50MHz) - -/* SPI1 */ - -#define GPIO_SPI1_NSS GPIO_ADJUST_MODE(GPIO_SPI1_NSS_0, GPIO_MODE_50MHz) -#define GPIO_SPI1_SCK GPIO_ADJUST_MODE(GPIO_SPI1_SCK_0, GPIO_MODE_50MHz) -#define GPIO_SPI1_MISO GPIO_ADJUST_MODE(GPIO_SPI1_MISO_0, GPIO_MODE_50MHz) -#define GPIO_SPI1_MOSI GPIO_ADJUST_MODE(GPIO_SPI1_MOSI_0, GPIO_MODE_50MHz) - -/* USB */ - -#define GPIO_USB_DM GPIO_USB_DM_0 -#define GPIO_USB_DP GPIO_USB_DP_0 - -/* SDIO */ - -#define GPIO_SDIO_CK GPIO_ADJUST_MODE(GPIO_SDIO_CK_0, GPIO_MODE_50MHz) -#define GPIO_SDIO_CMD GPIO_ADJUST_MODE(GPIO_SDIO_CMD_0, GPIO_MODE_50MHz) -#define GPIO_SDIO_D0 GPIO_ADJUST_MODE(GPIO_SDIO_D0_0, GPIO_MODE_50MHz) -#define GPIO_SDIO_D1 GPIO_ADJUST_MODE(GPIO_SDIO_D1_0, GPIO_MODE_50MHz) -#define GPIO_SDIO_D2 GPIO_ADJUST_MODE(GPIO_SDIO_D2_0, GPIO_MODE_50MHz) -#define GPIO_SDIO_D3 GPIO_ADJUST_MODE(GPIO_SDIO_D3_0, GPIO_MODE_50MHz) - -/* TIM1 */ - -#define GPIO_TIM1_CH1IN GPIO_TIM1_CH1IN_0 -#define GPIO_TIM1_CH1OUT GPIO_ADJUST_MODE(GPIO_TIM1_CH1OUT_0, GPIO_MODE_50MHz) -#define GPIO_TIM1_CH2IN GPIO_TIM1_CH2IN_0 -#define GPIO_TIM1_CH2OUT GPIO_ADJUST_MODE(GPIO_TIM1_CH2OUT_0, GPIO_MODE_50MHz) -#define GPIO_TIM1_CH3IN GPIO_TIM1_CH3IN_0 -#define GPIO_TIM1_CH3OUT GPIO_ADJUST_MODE(GPIO_TIM1_CH3OUT_0, GPIO_MODE_50MHz) -#define GPIO_TIM1_CH4IN GPIO_TIM1_CH4IN_0 -#define GPIO_TIM1_CH4OUT GPIO_ADJUST_MODE(GPIO_TIM1_CH4OUT_0, GPIO_MODE_50MHz) -#define GPIO_TIM1_BKIN GPIO_TIM1_BKIN_0 -#define GPIO_TIM1_ETR GPIO_TIM1_ETR_0 -#define GPIO_TIM1_CH1NOUT GPIO_ADJUST_MODE(GPIO_TIM1_CH1NOUT_0, GPIO_MODE_50MHz) -#define GPIO_TIM1_CH2NOUT GPIO_ADJUST_MODE(GPIO_TIM1_CH2NOUT_0, GPIO_MODE_50MHz) -#define GPIO_TIM1_CH3NOUT GPIO_ADJUST_MODE(GPIO_TIM1_CH3NOUT_0, GPIO_MODE_50MHz) - -/* FSMC NPS pins (used by board srcs) */ - -#define GPIO_NPS_A0 GPIO_ADJUST_MODE(GPIO_NPS_A0_0, GPIO_MODE_50MHz) -#define GPIO_NPS_A1 GPIO_ADJUST_MODE(GPIO_NPS_A1_0, GPIO_MODE_50MHz) -#define GPIO_NPS_A10 GPIO_ADJUST_MODE(GPIO_NPS_A10_0, GPIO_MODE_50MHz) -#define GPIO_NPS_A11 GPIO_ADJUST_MODE(GPIO_NPS_A11_0, GPIO_MODE_50MHz) -#define GPIO_NPS_A12 GPIO_ADJUST_MODE(GPIO_NPS_A12_0, GPIO_MODE_50MHz) -#define GPIO_NPS_A13 GPIO_ADJUST_MODE(GPIO_NPS_A13_0, GPIO_MODE_50MHz) -#define GPIO_NPS_A14 GPIO_ADJUST_MODE(GPIO_NPS_A14_0, GPIO_MODE_50MHz) -#define GPIO_NPS_A15 GPIO_ADJUST_MODE(GPIO_NPS_A15_0, GPIO_MODE_50MHz) -#define GPIO_NPS_A16 GPIO_ADJUST_MODE(GPIO_NPS_A16_0, GPIO_MODE_50MHz) -#define GPIO_NPS_A17 GPIO_ADJUST_MODE(GPIO_NPS_A17_0, GPIO_MODE_50MHz) -#define GPIO_NPS_A18 GPIO_ADJUST_MODE(GPIO_NPS_A18_0, GPIO_MODE_50MHz) -#define GPIO_NPS_A19 GPIO_ADJUST_MODE(GPIO_NPS_A19_0, GPIO_MODE_50MHz) -#define GPIO_NPS_A2 GPIO_ADJUST_MODE(GPIO_NPS_A2_0, GPIO_MODE_50MHz) -#define GPIO_NPS_A20 GPIO_ADJUST_MODE(GPIO_NPS_A20_0, GPIO_MODE_50MHz) -#define GPIO_NPS_A21 GPIO_ADJUST_MODE(GPIO_NPS_A21_0, GPIO_MODE_50MHz) -#define GPIO_NPS_A22 GPIO_ADJUST_MODE(GPIO_NPS_A22_0, GPIO_MODE_50MHz) -#define GPIO_NPS_A3 GPIO_ADJUST_MODE(GPIO_NPS_A3_0, GPIO_MODE_50MHz) -#define GPIO_NPS_A4 GPIO_ADJUST_MODE(GPIO_NPS_A4_0, GPIO_MODE_50MHz) -#define GPIO_NPS_A5 GPIO_ADJUST_MODE(GPIO_NPS_A5_0, GPIO_MODE_50MHz) -#define GPIO_NPS_A6 GPIO_ADJUST_MODE(GPIO_NPS_A6_0, GPIO_MODE_50MHz) -#define GPIO_NPS_A7 GPIO_ADJUST_MODE(GPIO_NPS_A7_0, GPIO_MODE_50MHz) -#define GPIO_NPS_A8 GPIO_ADJUST_MODE(GPIO_NPS_A8_0, GPIO_MODE_50MHz) -#define GPIO_NPS_A9 GPIO_ADJUST_MODE(GPIO_NPS_A9_0, GPIO_MODE_50MHz) -#define GPIO_NPS_D0 GPIO_ADJUST_MODE(GPIO_NPS_D0_0, GPIO_MODE_50MHz) -#define GPIO_NPS_D1 GPIO_ADJUST_MODE(GPIO_NPS_D1_0, GPIO_MODE_50MHz) -#define GPIO_NPS_D10 GPIO_ADJUST_MODE(GPIO_NPS_D10_0, GPIO_MODE_50MHz) -#define GPIO_NPS_D11 GPIO_ADJUST_MODE(GPIO_NPS_D11_0, GPIO_MODE_50MHz) -#define GPIO_NPS_D12 GPIO_ADJUST_MODE(GPIO_NPS_D12_0, GPIO_MODE_50MHz) -#define GPIO_NPS_D13 GPIO_ADJUST_MODE(GPIO_NPS_D13_0, GPIO_MODE_50MHz) -#define GPIO_NPS_D14 GPIO_ADJUST_MODE(GPIO_NPS_D14_0, GPIO_MODE_50MHz) -#define GPIO_NPS_D15 GPIO_ADJUST_MODE(GPIO_NPS_D15_0, GPIO_MODE_50MHz) -#define GPIO_NPS_D2 GPIO_ADJUST_MODE(GPIO_NPS_D2_0, GPIO_MODE_50MHz) -#define GPIO_NPS_D3 GPIO_ADJUST_MODE(GPIO_NPS_D3_0, GPIO_MODE_50MHz) -#define GPIO_NPS_D4 GPIO_ADJUST_MODE(GPIO_NPS_D4_0, GPIO_MODE_50MHz) -#define GPIO_NPS_D5 GPIO_ADJUST_MODE(GPIO_NPS_D5_0, GPIO_MODE_50MHz) -#define GPIO_NPS_D6 GPIO_ADJUST_MODE(GPIO_NPS_D6_0, GPIO_MODE_50MHz) -#define GPIO_NPS_D7 GPIO_ADJUST_MODE(GPIO_NPS_D7_0, GPIO_MODE_50MHz) -#define GPIO_NPS_D8 GPIO_ADJUST_MODE(GPIO_NPS_D8_0, GPIO_MODE_50MHz) -#define GPIO_NPS_D9 GPIO_ADJUST_MODE(GPIO_NPS_D9_0, GPIO_MODE_50MHz) -#define GPIO_NPS_NBL0 GPIO_ADJUST_MODE(GPIO_NPS_NBL0_0, GPIO_MODE_50MHz) -#define GPIO_NPS_NBL1 GPIO_ADJUST_MODE(GPIO_NPS_NBL1_0, GPIO_MODE_50MHz) -#define GPIO_NPS_NE2 GPIO_ADJUST_MODE(GPIO_NPS_NE2_0, GPIO_MODE_50MHz) -#define GPIO_NPS_NE3 GPIO_ADJUST_MODE(GPIO_NPS_NE3_0, GPIO_MODE_50MHz) -#define GPIO_NPS_NE4 GPIO_ADJUST_MODE(GPIO_NPS_NE4_0, GPIO_MODE_50MHz) -#define GPIO_NPS_NOE GPIO_ADJUST_MODE(GPIO_NPS_NOE_0, GPIO_MODE_50MHz) -#define GPIO_NPS_NWE GPIO_ADJUST_MODE(GPIO_NPS_NWE_0, GPIO_MODE_50MHz) - -#endif /* __BOARDS_ARM_STM32_STM3210E_EVAL_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32/stm3210e-eval/scripts/Make.defs b/boards/arm/stm32/stm3210e-eval/scripts/Make.defs deleted file mode 100644 index 7087042362d61..0000000000000 --- a/boards/arm/stm32/stm3210e-eval/scripts/Make.defs +++ /dev/null @@ -1,46 +0,0 @@ -############################################################################ -# boards/arm/stm32/stm3210e-eval/scripts/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/.config -include $(TOPDIR)/tools/Config.mk -include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs - -ifeq ($(CONFIG_STM32_DFU),y) - LDSCRIPT = ld.script.dfu -else - LDSCRIPT = ld.script -endif - -ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) - -ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 - -CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) -CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) -CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -AFLAGS := $(CFLAGS) -D__ASSEMBLY__ - -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections -LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32/stm3210e-eval/scripts/ld.script b/boards/arm/stm32/stm3210e-eval/scripts/ld.script deleted file mode 100644 index afebfee8ace82..0000000000000 --- a/boards/arm/stm32/stm3210e-eval/scripts/ld.script +++ /dev/null @@ -1,122 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm3210e-eval/scripts/ld.script - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* The STM32F103ZET6 has 512Kb of FLASH beginning at address 0x0800:0000 and - * 64Kb of SRAM beginning at address 0x2000:0000. When booting from FLASH, - * FLASH memory is aliased to address 0x0000:0000 where the code expects to - * begin execution by jumping to the entry point in the 0x0800:0000 address - * range. - */ - -MEMORY -{ - flash (rx) : ORIGIN = 0x08000000, LENGTH = 512K - sram (rwx) : ORIGIN = 0x20000000, LENGTH = 64K -} - -OUTPUT_ARCH(arm) -EXTERN(_vectors) -ENTRY(_stext) -SECTIONS -{ - .text : { - _stext = ABSOLUTE(.); - *(.vectors) - *(.text .text.*) - *(.fixup) - *(.gnu.warning) - *(.rodata .rodata.*) - *(.gnu.linkonce.t.*) - *(.glue_7) - *(.glue_7t) - *(.got) - *(.gcc_except_table) - *(.gnu.linkonce.r.*) - _etext = ABSOLUTE(.); - } > flash - - .init_section : ALIGN(4) { - _sinit = ABSOLUTE(.); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) - KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) - _einit = ABSOLUTE(.); - } > flash - - .ARM.extab : ALIGN(4) { - *(.ARM.extab*) - } > flash - - .ARM.exidx : ALIGN(4) { - __exidx_start = ABSOLUTE(.); - *(.ARM.exidx*) - __exidx_end = ABSOLUTE(.); - } > flash - - .tdata : { - _stdata = ABSOLUTE(.); - *(.tdata .tdata.* .gnu.linkonce.td.*); - _etdata = ABSOLUTE(.); - } > flash - - .tbss : { - _stbss = ABSOLUTE(.); - *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); - _etbss = ABSOLUTE(.); - } > flash - - _eronly = ABSOLUTE(.); - - /* The STM32F103Z has 64Kb of SRAM beginning at the following address */ - - .data : ALIGN(4) { - _sdata = ABSOLUTE(.); - *(.data .data.*) - *(.gnu.linkonce.d.*) - CONSTRUCTORS - . = ALIGN(4); - _edata = ABSOLUTE(.); - } > sram AT > flash - - .bss : ALIGN(4) { - _sbss = ABSOLUTE(.); - *(.bss .bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - . = ALIGN(4); - _ebss = ABSOLUTE(.); - } > sram - - /* Stabs debugging sections. */ - - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_info 0 : { *(.debug_info) } - .debug_line 0 : { *(.debug_line) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_aranges 0 : { *(.debug_aranges) } -} diff --git a/boards/arm/stm32/stm3210e-eval/scripts/ld.script.dfu b/boards/arm/stm32/stm3210e-eval/scripts/ld.script.dfu deleted file mode 100644 index 24bf37b6b6be4..0000000000000 --- a/boards/arm/stm32/stm3210e-eval/scripts/ld.script.dfu +++ /dev/null @@ -1,118 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm3210e-eval/scripts/ld.script.dfu - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* The STM32F103ZET6 has 512Kb of FLASH beginning at address 0x0800:0000 and - * 64Kb of SRAM beginning at address 0x2000:0000. Here we assume that the - * STM3210E-EVAL's DFU bootloader is being used. In that case, the correct - * load .text load address is 0x08003000 (leaving 464Kb). - */ - -MEMORY -{ - flash (rx) : ORIGIN = 0x08003000, LENGTH = 464K - sram (rwx) : ORIGIN = 0x20000000, LENGTH = 64K -} - -OUTPUT_ARCH(arm) -EXTERN(_vectors) -ENTRY(_stext) -SECTIONS -{ - .text : { - _stext = ABSOLUTE(.); - *(.vectors) - *(.text .text.*) - *(.fixup) - *(.gnu.warning) - *(.rodata .rodata.*) - *(.gnu.linkonce.t.*) - *(.glue_7) - *(.glue_7t) - *(.got) - *(.gcc_except_table) - *(.gnu.linkonce.r.*) - _etext = ABSOLUTE(.); - } > flash - - .init_section : ALIGN(4) { - _sinit = ABSOLUTE(.); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) - KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) - _einit = ABSOLUTE(.); - } > flash - - .ARM.extab : ALIGN(4) { - *(.ARM.extab*) - } > flash - - .ARM.exidx : ALIGN(4) { - __exidx_start = ABSOLUTE(.); - *(.ARM.exidx*) - __exidx_end = ABSOLUTE(.); - } > flash - - .tdata : { - _stdata = ABSOLUTE(.); - *(.tdata .tdata.* .gnu.linkonce.td.*); - _etdata = ABSOLUTE(.); - } > flash - - .tbss : { - _stbss = ABSOLUTE(.); - *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); - _etbss = ABSOLUTE(.); - } > flash - - _eronly = ABSOLUTE(.); - - /* The STM32F103Z has 64Kb of SRAM beginning at the following address */ - - .data : ALIGN(4) { - _sdata = ABSOLUTE(.); - *(.data .data.*) - *(.gnu.linkonce.d.*) - CONSTRUCTORS - _edata = ABSOLUTE(.); - } > sram AT > flash - - .bss : ALIGN(4) { - _sbss = ABSOLUTE(.); - *(.bss .bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - _ebss = ABSOLUTE(.); - } > sram - - /* Stabs debugging sections. */ - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_info 0 : { *(.debug_info) } - .debug_line 0 : { *(.debug_line) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_aranges 0 : { *(.debug_aranges) } -} diff --git a/boards/arm/stm32/stm3210e-eval/src/CMakeLists.txt b/boards/arm/stm32/stm3210e-eval/src/CMakeLists.txt deleted file mode 100644 index b870c533c1ce4..0000000000000 --- a/boards/arm/stm32/stm3210e-eval/src/CMakeLists.txt +++ /dev/null @@ -1,70 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/stm3210e-eval/src/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -set(SRCS stm32_boot.c stm32_bringup.c stm32_leds.c stm32_spi.c stm32_usbdev.c) - -if(CONFIG_STM32_FSMC) - list(APPEND SRCS stm32_lcd.c stm32_extcontext.c stm32_extmem.c - stm32_selectnor.c) - list(APPEND SRCS stm32_deselectnor.c stm32_selectsram.c stm32_deselectsram.c) - list(APPEND SRCS stm32_selectlcd.c stm32_deselectlcd.c) -endif() - -if(CONFIG_ADC) - list(APPEND SRCS stm32_adc.c) -endif() - -if(CONFIG_USBMSC) - list(APPEND SRCS stm32_usbmsc.c) -endif() - -if(CONFIG_USBDEV_COMPOSITE) - list(APPEND SRCS stm32_composite.c) -endif() - -if(CONFIG_STM32_CAN_CHARDRIVER) - list(APPEND SRCS stm32_can.c) -endif() - -if(CONFIG_ARCH_CUSTOM_PMINIT) - list(APPEND SRCS stm32_pm.c) -endif() - -if(CONFIG_ARCH_BUTTONS) - list(APPEND SRCS stm32_buttons.c) - - if(CONFIG_PM_BUTTONS) - list(APPEND SRCS stm32_pmbuttons.c) - endif() -endif() - -if(CONFIG_INPUT_DJOYSTICK) - list(APPEND SRCS stm32_djoystick.c) -endif() - -if(CONFIG_ARCH_IDLE_CUSTOM) - list(APPEND SRCS stm32_idle.c) -endif() - -target_sources(board PRIVATE ${SRCS}) - -set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/ld.script") diff --git a/boards/arm/stm32/stm3210e-eval/src/Make.defs b/boards/arm/stm32/stm3210e-eval/src/Make.defs deleted file mode 100644 index 9815a6acb2d43..0000000000000 --- a/boards/arm/stm32/stm3210e-eval/src/Make.defs +++ /dev/null @@ -1,71 +0,0 @@ -############################################################################ -# boards/arm/stm32/stm3210e-eval/src/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/Make.defs - -CSRCS = stm32_boot.c stm32_bringup.c stm32_leds.c stm32_spi.c stm32_usbdev.c - -ifeq ($(CONFIG_STM32_FSMC),y) -CSRCS += stm32_lcd.c stm32_extcontext.c stm32_extmem.c stm32_selectnor.c -CSRCS += stm32_deselectnor.c stm32_selectsram.c stm32_deselectsram.c -CSRCS += stm32_selectlcd.c stm32_deselectlcd.c -endif - -ifeq ($(CONFIG_ADC),y) -CSRCS += stm32_adc.c -endif - -ifeq ($(CONFIG_USBMSC),y) -CSRCS += stm32_usbmsc.c -endif - -ifeq ($(CONFIG_USBDEV_COMPOSITE),y) -CSRCS += stm32_composite.c -endif - -ifeq ($(CONFIG_STM32_CAN_CHARDRIVER),y) -CSRCS += stm32_can.c -endif - -ifeq ($(CONFIG_ARCH_CUSTOM_PMINIT),y) -CSRCS += stm32_pm.c -endif - -ifeq ($(CONFIG_ARCH_BUTTONS),y) -CSRCS += stm32_buttons.c - -ifeq ($(CONFIG_PM_BUTTONS),y) -CSRCS += stm32_pmbuttons.c -endif -endif - -ifeq ($(CONFIG_INPUT_DJOYSTICK),y) -CSRCS += stm32_djoystick.c -endif - -ifeq ($(CONFIG_ARCH_IDLE_CUSTOM),y) -CSRCS += stm32_idle.c -endif - -DEPPATH += --dep-path board -VPATH += :board -CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/stm3210e-eval/src/stm32_adc.c b/boards/arm/stm32/stm3210e-eval/src/stm32_adc.c deleted file mode 100644 index fc374d2a837c3..0000000000000 --- a/boards/arm/stm32/stm3210e-eval/src/stm32_adc.c +++ /dev/null @@ -1,153 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm3210e-eval/src/stm32_adc.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32_pwm.h" -#include "stm3210e-eval.h" - -#ifdef CONFIG_ADC - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -/* Up to 3 ADC interfaces are supported */ - -#if STM32_NADC < 3 -# undef CONFIG_STM32_ADC3 -#endif - -#if STM32_NADC < 2 -# undef CONFIG_STM32_ADC2 -#endif - -#if STM32_NADC < 1 -# undef CONFIG_STM32_ADC1 -#endif - -#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) || defined(CONFIG_STM32_ADC3) -#ifndef CONFIG_STM32_ADC1 -# warning "Channel information only available for ADC1" -#endif - -/* The number of ADC channels in the conversion list */ - -#define ADC1_NCHANNELS 1 - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* Identifying number of each ADC channel: Variable Resistor */ - -#ifdef CONFIG_STM32_ADC1 -static const uint8_t g_chanlist[ADC1_NCHANNELS] = -{ - 14 -}; - -/* Configurations of pins used byte each ADC channels */ - -static const uint32_t g_pinlist[ADC1_NCHANNELS] = -{ - GPIO_ADC1_IN14 -}; -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_adc_setup - * - * Description: - * Initialize ADC and register the ADC driver. - * - ****************************************************************************/ - -int stm32_adc_setup(void) -{ -#ifdef CONFIG_STM32_ADC1 - static bool initialized = false; - struct adc_dev_s *adc; - int ret; - int i; - - /* Check if we have already initialized */ - - if (!initialized) - { - /* Configure the pins as analog inputs for the selected channels */ - - for (i = 0; i < ADC1_NCHANNELS; i++) - { - stm32_configgpio(g_pinlist[i]); - } - - /* Call stm32_adcinitialize() to get an instance of the ADC interface */ - - adc = stm32_adcinitialize(1, g_chanlist, ADC1_NCHANNELS); - if (adc == NULL) - { - aerr("ERROR: Failed to get ADC interface\n"); - return -ENODEV; - } - - /* Register the ADC driver at "/dev/adc0" */ - - ret = adc_register("/dev/adc0", adc); - if (ret < 0) - { - aerr("ERROR: adc_register failed: %d\n", ret); - return ret; - } - - /* Now we are initialized */ - - initialized = true; - } - - return OK; -#else - return -ENOSYS; -#endif -} - -#endif /* CONFIG_STM32_ADC1 || CONFIG_STM32_ADC2 || CONFIG_STM32_ADC3 */ -#endif /* CONFIG_ADC */ diff --git a/boards/arm/stm32/stm3210e-eval/src/stm32_boot.c b/boards/arm/stm32/stm3210e-eval/src/stm32_boot.c deleted file mode 100644 index e4a1125248afe..0000000000000 --- a/boards/arm/stm32/stm3210e-eval/src/stm32_boot.c +++ /dev/null @@ -1,118 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm3210e-eval/src/stm32_boot.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include -#include - -#include "arm_internal.h" -#include "stm3210e-eval.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_boardinitialize - * - * Description: - * All STM32 architectures must provide the following entry point. - * This entry point is called early in the initialization -- after all - * memory has been configured and mapped but before any devices have been - * initialized. - * - ****************************************************************************/ - -void stm32_boardinitialize(void) -{ - /* If the FSMC and external RAM are selected, then enable SRAM access */ - -#if defined(CONFIG_STM32_FSMC) && defined(CONFIG_STM32_EXTERNAL_RAM) - stm32_selectsram(); -#endif - - /* Configure SPI chip selects if 1) SPI is not disabled, and 2) the weak - * function stm32_spidev_initialize() has been brought into the link. - */ - -#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) - if (stm32_spidev_initialize) - { - stm32_spidev_initialize(); - } -#endif - - /* Initialize USB is 1) USBDEV is selected, 2) the USB controller is not - * disabled, and 3) the weak function stm32_usbinitialize() has been - * brought into the build. - */ - -#if defined(CONFIG_USBDEV) && defined(CONFIG_STM32_USB) - if (stm32_usbinitialize) - { - stm32_usbinitialize(); - } -#endif - - /* Configure on-board LEDs if LED support has been selected. */ - -#ifdef CONFIG_ARCH_LEDS - board_autoled_initialize(); -#endif -} - -/**************************************************************************** - * Name: board_late_initialize - * - * Description: - * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional - * initialization call will be performed in the boot-up sequence to a - * function called board_late_initialize(). board_late_initialize() will be - * called immediately after up_initialize() is called and just before the - * initial application is started. This additional initialization phase - * may be used, for example, to initialize board-specific device drivers. - * - ****************************************************************************/ - -#ifdef CONFIG_BOARD_LATE_INITIALIZE -void board_late_initialize(void) -{ - /* Perform board-specific initialization */ - - stm32_bringup(); -} -#endif diff --git a/boards/arm/stm32/stm3210e-eval/src/stm32_bringup.c b/boards/arm/stm32/stm3210e-eval/src/stm32_bringup.c deleted file mode 100644 index 3a6d49c8f43ac..0000000000000 --- a/boards/arm/stm32/stm3210e-eval/src/stm32_bringup.c +++ /dev/null @@ -1,317 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm3210e-eval/src/stm32_bringup.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include - -#include -#include - -#ifdef CONFIG_STM32_SPI1 -# include -# include -#endif - -#ifdef CONFIG_STM32_SDIO -# include -# include -#endif - -#ifdef CONFIG_VIDEO_FB -# include -#endif - -#include "stm32.h" -#include "stm32_i2c.h" -#include "stm3210e-eval.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -/* For now, don't build in any SPI1 support -- NSH is not using it */ - -#undef CONFIG_STM32_SPI1 - -/* PORT and SLOT number probably depend on the board configuration */ - -#ifdef CONFIG_ARCH_BOARD_STM3210E_EVAL -# define NSH_HAVEUSBDEV 1 -# define NSH_HAVEMMCSD 1 -# if defined(CONFIG_NSH_MMCSDSLOTNO) && CONFIG_NSH_MMCSDSLOTNO != 0 -# error "Only one MMC/SD slot" -# undef CONFIG_NSH_MMCSDSLOTNO -# endif -# ifndef CONFIG_NSH_MMCSDSLOTNO -# define CONFIG_NSH_MMCSDSLOTNO 0 -# endif -#else - -/* Add configuration for new STM32 boards here */ - -# error "Unrecognized STM32 board" -# undef NSH_HAVEUSBDEV -# undef NSH_HAVEMMCSD -#endif - -/* Can't support USB features if USB is not enabled */ - -#ifndef CONFIG_USBDEV -# undef NSH_HAVEUSBDEV -#endif - -/* Can't support MMC/SD features if mountpoints are disabled or if SDIO - * support is not enabled. - */ - -#if defined(CONFIG_DISABLE_MOUNTPOINT) || !defined(CONFIG_STM32_SDIO) -# undef NSH_HAVEMMCSD -#endif - -#ifndef CONFIG_NSH_MMCSDMINOR -# define CONFIG_NSH_MMCSDMINOR 0 -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_i2c_register - * - * Description: - * Register one I2C drivers for the I2C tool. - * - ****************************************************************************/ - -#ifdef HAVE_I2CTOOL -static void stm32_i2c_register(int bus) -{ - struct i2c_master_s *i2c; - int ret; - - i2c = stm32_i2cbus_initialize(bus); - if (i2c == NULL) - { - _err("ERROR: Failed to get I2C%d interface\n", bus); - } - else - { - ret = i2c_register(i2c, bus); - if (ret < 0) - { - _err("ERROR: Failed to register I2C%d driver: %d\n", bus, ret); - stm32_i2cbus_uninitialize(i2c); - } - } -} -#endif - -/**************************************************************************** - * Name: stm32_i2ctool - * - * Description: - * Register I2C drivers for the I2C tool. - * - ****************************************************************************/ - -#ifdef HAVE_I2CTOOL -static void stm32_i2ctool(void) -{ -#ifdef CONFIG_STM32_I2C1 - stm32_i2c_register(1); -#endif -#ifdef CONFIG_STM32_I2C2 - stm32_i2c_register(2); -#endif -#ifdef CONFIG_STM32_I2C3 - stm32_i2c_register(3); -#endif -} -#else -# define stm32_i2ctool() -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_bringup - * - * Description: - * Perform architecture-specific initialization - * - * CONFIG_BOARD_LATE_INITIALIZE=y : - * Called from board_late_initialize(). - * - ****************************************************************************/ - -int stm32_bringup(void) -{ -#ifdef CONFIG_STM32_SPI1 - struct spi_dev_s *spi; - struct mtd_dev_s *mtd; -#endif -#ifdef NSH_HAVEMMCSD - struct sdio_dev_s *sdio; -#endif - int ret; - - /* Register I2C drivers on behalf of the I2C tool */ - - stm32_i2ctool(); - - /* Configure SPI-based devices */ - -#ifdef CONFIG_STM32_SPI1 - /* Get the SPI port */ - - syslog(LOG_INFO, "Initializing SPI port 1\n"); - spi = stm32_spibus_initialize(1); - if (!spi) - { - syslog(LOG_ERR, "ERROR: Failed to initialize SPI port 1\n"); - return -ENODEV; - } - - syslog(LOG_INFO, "Successfully initialized SPI port 1\n"); - - /* Now bind the SPI interface to the M25P64/128 SPI FLASH driver */ - - syslog(LOG_INFO, "Bind SPI to the SPI flash driver\n"); - - mtd = m25p_initialize(spi); - if (!mtd) - { - syslog(LOG_ERR, - "ERROR: Failed to bind SPI port 0 to the SPI FLASH driver\n"); - return -ENODEV; - } - - syslog(LOG_INFO, - "Successfully bound SPI port 0 to the SPI FLASH driver\n"); -#warning "Now what are we going to do with this SPI FLASH driver?" -#endif - - /* Create the SPI FLASH MTD instance */ - - /* The M25Pxx is not a give media to implement a file system.. - * its block sizes are too large - */ - - /* Mount the SDIO-based MMC/SD block driver */ - -#ifdef NSH_HAVEMMCSD - /* First, get an instance of the SDIO interface */ - - syslog(LOG_INFO, "Initializing SDIO slot %d\n", - CONFIG_NSH_MMCSDSLOTNO); - - sdio = sdio_initialize(CONFIG_NSH_MMCSDSLOTNO); - if (!sdio) - { - syslog(LOG_ERR, "ERROR: Failed to initialize SDIO slot %d\n", - CONFIG_NSH_MMCSDSLOTNO); - return -ENODEV; - } - - /* Now bind the SDIO interface to the MMC/SD driver */ - - syslog(LOG_INFO, "Bind SDIO to the MMC/SD driver, minor=%d\n", - CONFIG_NSH_MMCSDMINOR); - - ret = mmcsd_slotinitialize(CONFIG_NSH_MMCSDMINOR, sdio); - if (ret != OK) - { - syslog(LOG_ERR, - "ERROR: Failed to bind SDIO to the MMC/SD driver: %d\n", ret); - return ret; - } - - syslog(LOG_INFO, "Successfully bound SDIO to the MMC/SD driver\n"); - - /* Then let's guess and say that there is a card in the slot. - * I need to check to see if the STM3210E-EVAL board supports a GPIO - * to detect if there is a card in the slot. - */ - - sdio_mediachange(sdio, true); -#endif - -#ifdef CONFIG_ADC - /* Initialize ADC and register the ADC driver. */ - - ret = stm32_adc_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_adc_setup failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_STM32_CAN_CHARDRIVER - /* Initialize CAN and register the CAN driver. */ - - ret = stm32_can_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_can_setup failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_VIDEO_FB - /* Initialize and register the simulated framebuffer driver */ - - ret = fb_register(0, 0); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: fb_register() failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_INPUT_DJOYSTICK - /* Initialize and register the joystick driver */ - - ret = stm32_djoy_initialization(); - if (ret != OK) - { - syslog(LOG_ERR, - "ERROR: Failed to register the joystick driver: %d\n", ret); - return ret; - } - - syslog(LOG_INFO, "Successfully registered the joystick driver\n"); -#endif - - UNUSED(ret); - return OK; -} diff --git a/boards/arm/stm32/stm3210e-eval/src/stm32_buttons.c b/boards/arm/stm32/stm3210e-eval/src/stm32_buttons.c deleted file mode 100644 index c60b60a4d50d7..0000000000000 --- a/boards/arm/stm32/stm3210e-eval/src/stm32_buttons.c +++ /dev/null @@ -1,171 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm3210e-eval/src/stm32_buttons.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include -#include - -#include "stm32_gpio.h" -#include "stm3210e-eval.h" - -#ifdef CONFIG_ARCH_BUTTONS - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* Pin configuration for each STM3210E-EVAL button. This array is indexed by - * the BUTTON_* and JOYSTICK_* definitions in board.h - */ - -static const uint32_t g_buttons[NUM_BUTTONS] = -{ - GPIO_BTN_WAKEUP, GPIO_BTN_TAMPER, GPIO_BTN_KEY, - - /* The Joystick is treated like the other buttons unless - * CONFIG_INPUT_DJOYSTICK is defined, then it is assumed that they should - * be used by the discrete joystick driver. - */ - -#ifndef CONFIG_INPUT_DJOYSTICK - GPIO_JOY_SEL, GPIO_JOY_DOWN, GPIO_JOY_LEFT, GPIO_JOY_RIGHT, GPIO_JOY_UP -#endif -}; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_button_initialize - * - * Description: - * board_button_initialize() must be called to initialize button resources. - * After that, board_buttons() may be called to collect the current state - * of all buttons or board_button_irq() may be called to register button - * interrupt handlers. - * - ****************************************************************************/ - -uint32_t board_button_initialize(void) -{ - int i; - - /* Configure the GPIO pins as inputs. NOTE that EXTI interrupts are - * configured for some pins but NOT used in this file - */ - - for (i = 0; i < NUM_BUTTONS; i++) - { - stm32_configgpio(g_buttons[i]); - } - - return NUM_BUTTONS; -} - -/**************************************************************************** - * Name: board_buttons - ****************************************************************************/ - -uint32_t board_buttons(void) -{ - uint32_t ret = 0; - int i; - - /* Check that state of each key */ - - for (i = 0; i < NUM_BUTTONS; i++) - { - /* A LOW value means that the key is pressed for most keys. - * The exception is the WAKEUP button. - */ - - bool released = stm32_gpioread(g_buttons[i]); - if (i == BUTTON_WAKEUP) - { - released = !released; - } - - /* Accumulate the set of depressed (not released) keys */ - - if (!released) - { - ret |= (1 << i); - } - } - - return ret; -} - -/**************************************************************************** - * Button support. - * - * Description: - * board_button_initialize() must be called to initialize button resources. - * After that, board_buttons() may be called to collect the current state - * of all buttons or board_button_irq() may be called to register button - * interrupt handlers. - * - * After board_button_initialize() has been called, board_buttons() may be - * called to collect the state of all buttons. board_buttons() returns an - * 32-bit bit set with each bit associated with a button. See the - * BUTTON_*_BIT and JOYSTICK_*_BIT definitions in board.h for the meaning - * of each bit. - * - * board_button_irq() may be called to register an interrupt handler that - * will be called when a button is depressed or released. The ID value is a - * button enumeration value that uniquely identifies a button resource. See - * the BUTTON_* and JOYSTICK_* definitions in board.h for the meaning of - * enumeration value. - * - ****************************************************************************/ - -#ifdef CONFIG_ARCH_IRQBUTTONS -int board_button_irq(int id, xcpt_t irqhandler, void *arg) -{ - int ret = -EINVAL; - - /* The following should be atomic */ - - if (id >= MIN_IRQBUTTON && id <= MAX_IRQBUTTON) - { - ret = stm32_gpiosetevent(g_buttons[id], true, true, true, - irqhandler, arg); - } - - return ret; -} -#endif -#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/stm32/stm3210e-eval/src/stm32_can.c b/boards/arm/stm32/stm3210e-eval/src/stm32_can.c deleted file mode 100644 index 9ef1ed802793e..0000000000000 --- a/boards/arm/stm32/stm3210e-eval/src/stm32_can.c +++ /dev/null @@ -1,95 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm3210e-eval/src/stm32_can.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32.h" -#include "stm32_can.h" -#include "stm3210e-eval.h" - -#ifdef CONFIG_CAN - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -/* The STM32F103ZE supports only CAN1 */ - -#define CAN_PORT 1 - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_can_setup - * - * Description: - * Initialize CAN and register the CAN device - * - ****************************************************************************/ - -int stm32_can_setup(void) -{ -#ifdef CONFIG_STM32_CAN1 - struct can_dev_s *can; - int ret; - - /* Call stm32_caninitialize() to get an instance of the CAN interface */ - - can = stm32_caninitialize(CAN_PORT); - if (can == NULL) - { - canerr("ERROR: Failed to get CAN interface\n"); - return -ENODEV; - } - - /* Register the CAN driver at "/dev/can0" */ - - ret = can_register("/dev/can0", can); - if (ret < 0) - { - canerr("ERROR: can_register failed: %d\n", ret); - return ret; - } - - return OK; -#else - return -ENODEV; -#endif -} - -#endif /* CONFIG_CAN */ diff --git a/boards/arm/stm32/stm3210e-eval/src/stm32_composite.c b/boards/arm/stm32/stm3210e-eval/src/stm32_composite.c deleted file mode 100644 index b955808ef1ba0..0000000000000 --- a/boards/arm/stm32/stm3210e-eval/src/stm32_composite.c +++ /dev/null @@ -1,450 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm3210e-eval/src/stm32_composite.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include - -#include "stm32.h" - -#if defined(CONFIG_BOARDCTL_USBDEVCTRL) && defined(CONFIG_USBDEV_COMPOSITE) - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* No SDIO? Then no USB MSC device in composite */ - -#ifndef CONFIG_STM32_SDIO -# undef CONFIG_USBMSC_COMPOSITE -#endif - -/* SLOT number(s) could depend on the board configuration */ - -#ifdef CONFIG_ARCH_BOARD_STM3210E_EVAL -# undef STM32_MMCSDSLOTNO -# define STM32_MMCSDSLOTNO 0 -#else -/* Add configuration for new STM32 boards here */ - -# error "Unrecognized STM32 board" -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -#ifdef CONFIG_USBMSC_COMPOSITE -static void *g_mschandle; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_mscclassobject - * - * Description: - * If the mass storage class driver is part of composite device, then - * its instantiation and configuration is a multi-step, board-specific, - * process (See comments for usbmsc_configure below). In this case, - * board-specific logic must provide board_mscclassobject(). - * - * board_mscclassobject() is called from the composite driver. It must - * encapsulate the instantiation and configuration of the mass storage - * class and the return the mass storage device's class driver instance - * to the composite driver. - * - * Input Parameters: - * classdev - The location to return the mass storage class' device - * instance. - * - * Returned Value: - * 0 on success; a negated errno on failure - * - ****************************************************************************/ - -#ifdef CONFIG_USBMSC_COMPOSITE -static int board_mscclassobject(int minor, - struct usbdev_devinfo_s *devinfo, - struct usbdevclass_driver_s **classdev) -{ - int ret; - - DEBUGASSERT(g_mschandle == NULL); - - /* Configure the mass storage device */ - - uinfo("Configuring with NLUNS=1\n"); - ret = usbmsc_configure(1, &g_mschandle); - if (ret < 0) - { - uerr("ERROR: usbmsc_configure failed: %d\n", -ret); - return ret; - } - - uinfo("MSC handle=%p\n", g_mschandle); - - /* Bind the LUN(s) */ - - uinfo("Bind LUN=0 to /dev/mmcsd0\n"); - ret = usbmsc_bindlun(g_mschandle, "/dev/mmcsd0", 0, 0, 0, false); - if (ret < 0) - { - uerr("ERROR: usbmsc_bindlun failed for LUN 1 at /dev/mmcsd0: %d\n", - ret); - usbmsc_uninitialize(g_mschandle); - g_mschandle = NULL; - return ret; - } - - /* Get the mass storage device's class object */ - - ret = usbmsc_classobject(g_mschandle, devinfo, classdev); - if (ret < 0) - { - uerr("ERROR: usbmsc_classobject failed: %d\n", -ret); - usbmsc_uninitialize(g_mschandle); - g_mschandle = NULL; - } - - return ret; -} -#endif - -/**************************************************************************** - * Name: board_mscuninitialize - * - * Description: - * Un-initialize the USB storage class driver. - * This is just an application- specific wrapper about usbmsc_unitialize() - * that is called form the composite device logic. - * - * Input Parameters: - * classdev - The class driver instance previously given to the composite - * driver by board_mscclassobject(). - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef CONFIG_USBMSC_COMPOSITE -static void board_mscuninitialize(struct usbdevclass_driver_s *classdev) -{ - DEBUGASSERT(g_mschandle != NULL); - usbmsc_uninitialize(g_mschandle); - g_mschandle = NULL; -} -#endif - -/**************************************************************************** - * Name: board_composite0_connect - * - * Description: - * Connect the USB composite device on the specified USB device port for - * configuration 0. - * - * Input Parameters: - * port - The USB device port. - * - * Returned Value: - * A non-NULL handle value is returned on success. NULL is returned on - * any failure. - * - ****************************************************************************/ - -#ifdef CONFIG_USBMSC_COMPOSITE -static void *board_composite0_connect(int port) -{ - /* Here we are composing the configuration of the usb composite device. - * - * The standard is to use one CDC/ACM and one USB mass storage device. - */ - - struct composite_devdesc_s dev[2]; - int ifnobase = 0; - int strbase = COMPOSITE_NSTRIDS; - - /* Configure the CDC/ACM device */ - - /* Ask the cdcacm driver to fill in the constants we didn't - * know here. - */ - - cdcacm_get_composite_devdesc(&dev[0]); - - /* Overwrite and correct some values... */ - - /* The callback functions for the CDC/ACM class */ - - dev[0].classobject = cdcacm_classobject; - dev[0].uninitialize = cdcacm_uninitialize; - - /* Interfaces */ - - dev[0].devinfo.ifnobase = ifnobase; /* Offset to Interface-IDs */ - dev[0].minor = 0; /* The minor interface number */ - - /* Strings */ - - dev[0].devinfo.strbase = strbase; /* Offset to String Numbers */ - - /* Endpoints */ - - dev[0].devinfo.epno[CDCACM_EP_INTIN_IDX] = 1; - dev[0].devinfo.epno[CDCACM_EP_BULKIN_IDX] = 2; - dev[0].devinfo.epno[CDCACM_EP_BULKOUT_IDX] = 3; - - /* Count up the base numbers */ - - ifnobase += dev[0].devinfo.ninterfaces; - strbase += dev[0].devinfo.nstrings; - - /* Configure the mass storage device device */ - - /* Ask the usbmsc driver to fill in the constants we didn't - * know here. - */ - - usbmsc_get_composite_devdesc(&dev[1]); - - /* Overwrite and correct some values... */ - - /* The callback functions for the USBMSC class */ - - dev[1].classobject = board_mscclassobject; - dev[1].uninitialize = board_mscuninitialize; - - /* Interfaces */ - - dev[1].devinfo.ifnobase = ifnobase; /* Offset to Interface-IDs */ - dev[1].minor = 0; /* The minor interface number */ - - /* Strings */ - - dev[1].devinfo.strbase = strbase; /* Offset to String Numbers */ - - /* Endpoints */ - - dev[1].devinfo.epno[USBMSC_EP_BULKIN_IDX] = 5; - dev[1].devinfo.epno[USBMSC_EP_BULKOUT_IDX] = 4; - - /* Count up the base numbers */ - - ifnobase += dev[1].devinfo.ninterfaces; - strbase += dev[1].devinfo.nstrings; - - return composite_initialize(composite_getdevdescs(), dev, 2); -} -#endif - -/**************************************************************************** - * Name: board_composite1_connect - * - * Description: - * Connect the USB composite device on the specified USB device port for - * configuration 1. - * - * Input Parameters: - * port - The USB device port. - * - * Returned Value: - * A non-NULL handle value is returned on success. NULL is returned on - * any failure. - * - ****************************************************************************/ - -static void *board_composite1_connect(int port) -{ - /* REVISIT: This configuration currently fails. stm32_epallocpma() fails - * allocate a buffer for the 6th endpoint. Currently it supports 7x64 byte - * buffers, two required for EP0, leaving only buffers for 5 additional - * endpoints. - */ - -#if 0 - struct composite_devdesc_s dev[2]; - int strbase = COMPOSITE_NSTRIDS; - int ifnobase = 0; - int epno; - int i; - - for (i = 0, epno = 1; i < 2; i++) - { - /* Ask the cdcacm driver to fill in the constants we didn't know here */ - - cdcacm_get_composite_devdesc(&dev[i]); - - /* Overwrite and correct some values... */ - - /* The callback functions for the CDC/ACM class */ - - dev[i].classobject = cdcacm_classobject; - dev[i].uninitialize = cdcacm_uninitialize; - - dev[i].minor = i; /* The minor interface number */ - - /* Interfaces */ - - dev[i].devinfo.ifnobase = ifnobase; /* Offset to Interface-IDs */ - - /* Strings */ - - dev[i].devinfo.strbase = strbase; /* Offset to String Numbers */ - - /* Endpoints */ - - dev[i].devinfo.epno[CDCACM_EP_INTIN_IDX] = epno++; - dev[i].devinfo.epno[CDCACM_EP_BULKIN_IDX] = epno++; - dev[i].devinfo.epno[CDCACM_EP_BULKOUT_IDX] = epno++; - - ifnobase += dev[i].devinfo.ninterfaces; - strbase += dev[i].devinfo.nstrings; - } - - return composite_initialize(composite_getdevdescs(), dev, 2); -#else - return NULL; -#endif -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_composite_initialize - * - * Description: - * Perform architecture specific initialization of a composite USB device. - * - ****************************************************************************/ - -int board_composite_initialize(int port) -{ - /* If system/composite is built as an NSH command, then SD slot should - * already have been initialized. - * In this case, there is nothing further to be done here. - * - * NOTE: CONFIG_NSH_BUILTIN_APPS is not a fool-proof indication that NSH - * was built. - */ - -#ifndef CONFIG_NSH_BUILTIN_APPS - struct sdio_dev_s *sdio; - int ret; - - /* First, get an instance of the SDIO interface */ - - syslog(LOG_INFO, "Initializing SDIO slot %d\n", STM32_MMCSDSLOTNO); - - sdio = sdio_initialize(STM32_MMCSDSLOTNO); - if (!sdio) - { - syslog(LOG_ERR, "ERROR: Failed to initialize SDIO slot %d\n", - STM32_MMCSDSLOTNO); - return -ENODEV; - } - - /* Now bind the SDIO interface to the MMC/SD driver */ - - syslog(LOG_INFO, "Bind SDIO to the MMC/SD driver, minor=0\n"); - - ret = mmcsd_slotinitialize(0, sdio); - if (ret != OK) - { - syslog(LOG_ERR, - "ERROR: Failed to bind SDIO to the MMC/SD driver: %d\n", - ret); - return ret; - } - - syslog(LOG_INFO, "Successfully bound SDIO to the MMC/SD driver\n"); - - /* Then let's guess and say that there is a card in the slot. I need to - * check to see if the STM3210E-EVAL board supports a GPIO to detect if - * there is a card in the slot. - */ - - sdio_mediachange(sdio, true); - -#endif /* CONFIG_NSH_BUILTIN_APPS */ - - return OK; -} - -/**************************************************************************** - * Name: board_composite_connect - * - * Description: - * Connect the USB composite device on the specified USB device port using - * the specified configuration. The interpretation of the configid is - * board specific. - * - * Input Parameters: - * port - The USB device port. - * configid - The USB composite configuration - * - * Returned Value: - * A non-NULL handle value is returned on success. NULL is returned on - * any failure. - * - ****************************************************************************/ - -void *board_composite_connect(int port, int configid) -{ - if (configid == 0) - { -#ifdef CONFIG_USBMSC_COMPOSITE - return board_composite0_connect(port); -#else - return NULL; -#endif - } - else if (configid == 1) - { - return board_composite1_connect(port); - } - else - { - return NULL; - } -} - -#endif /* CONFIG_BOARDCTL_USBDEVCTRL && CONFIG_USBDEV_COMPOSITE */ diff --git a/boards/arm/stm32/stm3210e-eval/src/stm32_deselectlcd.c b/boards/arm/stm32/stm3210e-eval/src/stm32_deselectlcd.c deleted file mode 100644 index 4b10bfee096ea..0000000000000 --- a/boards/arm/stm32/stm3210e-eval/src/stm32_deselectlcd.c +++ /dev/null @@ -1,80 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm3210e-eval/src/stm32_deselectlcd.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include "arm_internal.h" -#include "stm32.h" -#include "stm3210e-eval.h" - -#ifdef CONFIG_STM32_FSMC - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_deselectlcd - * - * Description: - * Disable the LCD - * - ****************************************************************************/ - -void stm32_deselectlcd(void) -{ - /* Restore registers to their power up settings */ - - putreg32(0xffffffff, STM32_FSMC_BCR4); - - /* Bank1 NOR/SRAM timing register configuration */ - - putreg32(0x0fffffff, STM32_FSMC_BTR4); - - /* Disable AHB clocking to the FSMC */ - - stm32_fsmc_disable(); -} - -#endif /* CONFIG_STM32_FSMC */ diff --git a/boards/arm/stm32/stm3210e-eval/src/stm32_deselectsram.c b/boards/arm/stm32/stm3210e-eval/src/stm32_deselectsram.c deleted file mode 100644 index 42bed7c9f852e..0000000000000 --- a/boards/arm/stm32/stm3210e-eval/src/stm32_deselectsram.c +++ /dev/null @@ -1,80 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm3210e-eval/src/stm32_deselectsram.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include "arm_internal.h" -#include "stm32.h" -#include "stm3210e-eval.h" - -#ifdef CONFIG_STM32_FSMC - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_deselectsram - * - * Description: - * Disable NOR FLASH - * - ****************************************************************************/ - -void stm32_deselectsram(void) -{ - /* Restore registers to their power up settings */ - - putreg32(0x000030d2, STM32_FSMC_BCR3); - - /* Bank1 NOR/SRAM timing register configuration */ - - putreg32(0x0fffffff, STM32_FSMC_BTR3); - - /* Disable AHB clocking to the FSMC */ - - stm32_fsmc_disable(); -} - -#endif /* CONFIG_STM32_FSMC */ diff --git a/boards/arm/stm32/stm3210e-eval/src/stm32_djoystick.c b/boards/arm/stm32/stm3210e-eval/src/stm32_djoystick.c deleted file mode 100644 index acd4aa605df31..0000000000000 --- a/boards/arm/stm32/stm3210e-eval/src/stm32_djoystick.c +++ /dev/null @@ -1,299 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm3210e-eval/src/stm32_djoystick.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include -#include -#include - -#include "stm32_gpio.h" -#include "stm3210e-eval.h" - -#ifdef CONFIG_INPUT_DJOYSTICK - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Number of Joystick discretes */ - -#define DJOY_NGPIOS 5 - -/* Bitset of supported Joystick discretes */ - -#define DJOY_SUPPORTED (DJOY_UP_BIT | DJOY_DOWN_BIT | DJOY_LEFT_BIT | \ - DJOY_RIGHT_BIT | DJOY_BUTTON_SELECT_BIT) - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -static djoy_buttonset_t -djoy_supported(const struct djoy_lowerhalf_s *lower); -static djoy_buttonset_t -djoy_sample(const struct djoy_lowerhalf_s *lower); -static void djoy_enable(const struct djoy_lowerhalf_s *lower, - djoy_buttonset_t press, djoy_buttonset_t release, - djoy_interrupt_t handler, void *arg); - -static void djoy_disable(void); -static int djoy_interrupt(int irq, void *context, void *arg); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* Pin configuration for each STM3210E-EVAL joystick "button." Index using - * DJOY_* definitions in include/nuttx/input/djoystick.h. - */ - -static const uint16_t g_joygpio[DJOY_NGPIOS] = -{ - GPIO_JOY_UP, GPIO_JOY_DOWN, GPIO_JOY_LEFT, GPIO_JOY_RIGHT, GPIO_JOY_SEL -}; - -/* Current interrupt handler and argument */ - -static djoy_interrupt_t g_djoyhandler; -static void *g_djoyarg; - -/* This is the discrete joystick lower half driver interface */ - -static const struct djoy_lowerhalf_s g_djoylower = -{ - .dl_supported = djoy_supported, - .dl_sample = djoy_sample, - .dl_enable = djoy_enable, -}; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: djoy_supported - * - * Description: - * Return the set of buttons supported on the discrete joystick device - * - ****************************************************************************/ - -static djoy_buttonset_t -djoy_supported(const struct djoy_lowerhalf_s *lower) -{ - iinfo("Supported: %02x\n", DJOY_SUPPORTED); - return (djoy_buttonset_t)DJOY_SUPPORTED; -} - -/**************************************************************************** - * Name: djoy_sample - * - * Description: - * Return the current state of all discrete joystick buttons - * - ****************************************************************************/ - -static djoy_buttonset_t djoy_sample(const struct djoy_lowerhalf_s *lower) -{ - djoy_buttonset_t ret = 0; - int i; - - /* Read each joystick GPIO value */ - - for (i = 0; i < DJOY_NGPIOS; i++) - { - bool released = stm32_gpioread(g_joygpio[i]); - if (!released) - { - ret |= (1 << i); - } - } - - iinfo("Retuning: %02x\n", DJOY_SUPPORTED); - return ret; -} - -/**************************************************************************** - * Name: djoy_enable - * - * Description: - * Enable interrupts on the selected set of joystick buttons. And empty - * set will disable all interrupts. - * - ****************************************************************************/ - -static void djoy_enable(const struct djoy_lowerhalf_s *lower, - djoy_buttonset_t press, djoy_buttonset_t release, - djoy_interrupt_t handler, void *arg) -{ - irqstate_t flags; - djoy_buttonset_t either = press | release; - djoy_buttonset_t bit; - bool rising; - bool falling; - int i; - - /* Start with all interrupts disabled */ - - flags = enter_critical_section(); - djoy_disable(); - - iinfo("press: %02x release: %02x handler: %p arg: %p\n", - press, release, handler, arg); - - /* If no events are indicated or if no handler is provided, then this - * must really be a request to disable interrupts. - */ - - if (either && handler) - { - /* Save the new the handler and argument */ - - g_djoyhandler = handler; - g_djoyarg = arg; - - /* Check each GPIO. */ - - for (i = 0; i < DJOY_NGPIOS; i++) - { - /* Enable interrupts on each pin that has either a press or - * release event associated with it. - */ - - bit = (1 << i); - if ((either & bit) != 0) - { - /* Active low so a press corresponds to a falling edge and - * a release corresponds to a rising edge. - */ - - falling = ((press & bit) != 0); - rising = ((release & bit) != 0); - - iinfo("GPIO %d: rising: %d falling: %d\n", - i, rising, falling); - - stm32_gpiosetevent(g_joygpio[i], rising, falling, - true, djoy_interrupt, NULL); - } - } - } - - leave_critical_section(flags); -} - -/**************************************************************************** - * Name: djoy_disable - * - * Description: - * Disable all joystick interrupts - * - ****************************************************************************/ - -static void djoy_disable(void) -{ - irqstate_t flags; - int i; - - /* Disable each joystick interrupt */ - - flags = enter_critical_section(); - for (i = 0; i < DJOY_NGPIOS; i++) - { - stm32_gpiosetevent(g_joygpio[i], false, false, false, NULL, NULL); - } - - leave_critical_section(flags); - - /* Nullify the handler and argument */ - - g_djoyhandler = NULL; - g_djoyarg = NULL; -} - -/**************************************************************************** - * Name: djoy_interrupt - * - * Description: - * Discrete joystick interrupt handler - * - ****************************************************************************/ - -static int djoy_interrupt(int irq, void *context, void *arg) -{ - DEBUGASSERT(g_djoyhandler); - if (g_djoyhandler) - { - g_djoyhandler(&g_djoylower, g_djoyarg); - } - - return OK; -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_djoy_initialization - * - * Description: - * Initialize and register the discrete joystick driver - * - ****************************************************************************/ - -int stm32_djoy_initialization(void) -{ - int i; - - /* Configure the GPIO pins as inputs. NOTE: This is unnecessary for - * interrupting pins since it will also be done by stm32_gpiosetevent(). - */ - - for (i = 0; i < DJOY_NGPIOS; i++) - { - stm32_configgpio(g_joygpio[i]); - } - - /* Make sure that all interrupts are disabled */ - - djoy_disable(); - - /* Register the joystick device as /dev/djoy0 */ - - return djoy_register("/dev/djoy0", &g_djoylower); -} - -#endif /* CONFIG_INPUT_DJOYSTICK */ diff --git a/boards/arm/stm32/stm3210e-eval/src/stm32_extmem.c b/boards/arm/stm32/stm3210e-eval/src/stm32_extmem.c deleted file mode 100644 index e40b69a09856b..0000000000000 --- a/boards/arm/stm32/stm3210e-eval/src/stm32_extmem.c +++ /dev/null @@ -1,137 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm3210e-eval/src/stm32_extmem.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32_gpio.h" -#include "stm32.h" -#include "stm3210e-eval.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#ifndef CONFIG_STM32_FSMC -# warning "FSMC is not enabled" -#endif - -#if STM32_NGPIO_PORTS < 6 -# error "Required GPIO ports not enabled" -#endif - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/* 512Kx16 SRAM is connected to bank2 of the FSMC interface and both 8- and - * 16-bit accesses are allowed by BLN0 and BLN1 connected to BLE and BHE of - * SRAM, respectively. - * - * Pin Usage (per schematic) - * - * FLASH SRAM NAND LCD - * D[0..15] [0..15] [0..15] [0..7] [0..15] - * A[0..23] [0..22] [0..18] [16,17] [0] - * FSMC_NBL0 PE0 OUT ~BLE --- --- --- - * FSMC_NBL1 PE1 OUT ~BHE --- --- --- - * FSMC_NE2 PG9 OUT --- ~E --- --- - * FSMC_NE3 PG10 OUT ~CE --- --- --- - * FSMC_NE4 PG12 OUT --- --- --- ~CS - * FSMC_NWE PD5 OUT ~WE ~W ~W ~WR/SCL - * FSMC_NOE PD4 OUT ~OE ~G ~R ~RD - * FSMC_NWAIT PD6 IN --- R~B --- --- - * FSMC_INT2 PG6* IN --- --- R~B --- - * - * *JP7 will switch to PD6 - */ - -/* It would be much more efficient to brute force these all into the - * the appropriate registers. Just a little tricky. - */ - -/* GPIO configurations common to SRAM and NOR Flash */ - -const uint16_t g_commonconfig[NCOMMON_CONFIG] = -{ - /* A0... A18 */ - - GPIO_NPS_A0, GPIO_NPS_A1, GPIO_NPS_A2, GPIO_NPS_A3, - GPIO_NPS_A4, GPIO_NPS_A5, GPIO_NPS_A6, GPIO_NPS_A7, - GPIO_NPS_A8, GPIO_NPS_A9, GPIO_NPS_A10, GPIO_NPS_A11, - GPIO_NPS_A12, GPIO_NPS_A13, GPIO_NPS_A14, GPIO_NPS_A15, - GPIO_NPS_A16, GPIO_NPS_A17, GPIO_NPS_A18, - - /* D0... D15 */ - - GPIO_NPS_D0, GPIO_NPS_D1, GPIO_NPS_D2, GPIO_NPS_D3, - GPIO_NPS_D4, GPIO_NPS_D5, GPIO_NPS_D6, GPIO_NPS_D7, - GPIO_NPS_D8, GPIO_NPS_D9, GPIO_NPS_D10, GPIO_NPS_D11, - GPIO_NPS_D12, GPIO_NPS_D13, GPIO_NPS_D14, GPIO_NPS_D15, - - /* NOE, NWE */ - - GPIO_NPS_NOE, GPIO_NPS_NWE -}; - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_extmemgpios - * - * Description: - * Initialize GPIOs for NOR or SRAM - * - ****************************************************************************/ - -void stm32_extmemgpios(const uint16_t *gpios, int ngpios) -{ - int i; - - /* Configure GPIOs */ - - for (i = 0; i < ngpios; i++) - { - stm32_configgpio(gpios[i]); - } -} diff --git a/boards/arm/stm32/stm3210e-eval/src/stm32_idle.c b/boards/arm/stm32/stm3210e-eval/src/stm32_idle.c deleted file mode 100644 index 6420bf627a4e7..0000000000000 --- a/boards/arm/stm32/stm3210e-eval/src/stm32_idle.c +++ /dev/null @@ -1,437 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm3210e-eval/src/stm32_idle.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include -#include -#include - -#include - -#include -#include - -#include "arm_internal.h" -#include "stm32_pm.h" -#include "stm32_rcc.h" -#include "stm32_exti.h" -#include "stm32_rtc.h" - -#include "stm3210e-eval.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -/* Does the board support an IDLE LED to indicate that the board is in the - * IDLE state? - */ - -#if defined(CONFIG_ARCH_LEDS) && defined(LED_IDLE) -# define BEGIN_IDLE() board_autoled_on(LED_IDLE) -# define END_IDLE() board_autoled_off(LED_IDLE) -#else -# define BEGIN_IDLE() -# define END_IDLE() -#endif - -/* Values for the RTC Alarm to wake up from the PM_STANDBY mode - * (which corresponds to STM32 stop mode). If this alarm expires, - * the logic in this file will wakeup from PM_STANDBY mode and - * transition to PM_SLEEP mode (STM32 standby mode). - */ - -#ifndef CONFIG_PM_ALARM_SEC -# define CONFIG_PM_ALARM_SEC 15 -#endif - -#ifndef CONFIG_PM_ALARM_NSEC -# define CONFIG_PM_ALARM_NSEC 0 -#endif - -/* Values for the RTC Alarm to reset from the PM_SLEEP mode (STM32 - * standby mode). If CONFIG_PM_SLEEP_WAKEUP is defined in the - * configuration, then the logic in this file will program the RTC - * alarm to wakeup the processor after an a delay. - * - * This feature might be useful, for example, in a system that needs to - * use minimal power but awake up to perform some task at periodic - * intervals. - */ - -#ifdef CONFIG_PM_SLEEP_WAKEUP - -# ifndef CONFIG_RTC_ALARM -# error "CONFIG_RTC_ALARM should be enabled to use CONFIG_PM_SLEEP_WAKEUP" -# endif - -/* If CONFIG_PM_SLEEP_WAKEUP is defined, then CONFIG_PM_SLEEP_WAKEUP_SEC - * and CONFIG_PM_SLEEP_WAKEUP_NSEC define the delay until the STM32 - * awakens from PM_SLEEP mode. - */ - -# ifndef CONFIG_PM_SLEEP_WAKEUP_SEC -# define CONFIG_PM_SLEEP_WAKEUP_SEC 10 -# endif - -# ifndef CONFIG_PM_SLEEP_WAKEUP_NSEC -# define CONFIG_PM_SLEEP_WAKEUP_NSEC 0 -# endif -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -#if defined(CONFIG_PM) && defined(CONFIG_RTC_ALARM) -static volatile bool g_alarmwakeup; /* Wakeup Alarm indicator */ -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_alarmcb - * - * Description: - * RTC alarm callback - * - ****************************************************************************/ - -#if defined(CONFIG_PM) && defined(CONFIG_RTC_ALARM) -static void stm32_alarmcb(void) -{ - /* Note that we were awaken by an alarm */ - - g_alarmwakeup = true; -} -#endif - -/**************************************************************************** - * Name: stm32_alarm_exti - * - * Description: - * RTC alarm EXTI interrupt service routine - * - ****************************************************************************/ - -#if defined(CONFIG_PM) && defined(CONFIG_RTC_ALARM) -static int stm32_alarm_exti(int irq, void *context, void *arg) -{ - stm32_alarmcb(); - return OK; -} -#endif - -/**************************************************************************** - * Name: stm32_exti_cancel - * - * Description: - * Disable the ALARM EXTI interrupt - * - ****************************************************************************/ - -#if defined(CONFIG_PM) && defined(CONFIG_RTC_ALARM) -static void stm32_exti_cancel(void) -{ - stm32_exti_alarm(false, false, false, NULL, NULL); -} -#endif - -/**************************************************************************** - * Name: stm32_rtc_alarm - * - * Description: - * Set the alarm - * - ****************************************************************************/ - -#if defined(CONFIG_PM) && defined(CONFIG_RTC_ALARM) -static int stm32_rtc_alarm(time_t tv_sec, time_t tv_nsec, bool exti) -{ - struct timespec alarmtime; - int ret; - - /* Configure to receive RTC Alarm EXTI interrupt */ - - if (exti) - { - /* TODO: Make sure that that is no pending EXTI interrupt */ - - stm32_exti_alarm(true, true, true, stm32_alarm_exti, NULL); - } - - /* Configure the RTC alarm to Auto Wake the system */ - - up_rtc_gettime(&alarmtime); - - alarmtime.tv_sec += tv_sec; - alarmtime.tv_nsec += tv_nsec; - - /* The tv_nsec value must not exceed 1,000,000,000. That - * would be an invalid time. - */ - - if (alarmtime.tv_nsec >= NSEC_PER_SEC) - { - /* Carry to the seconds */ - - alarmtime.tv_sec++; - alarmtime.tv_nsec -= NSEC_PER_SEC; - } - - /* Set the alarm */ - - g_alarmwakeup = false; - ret = stm32_rtc_setalarm(&alarmtime, stm32_alarmcb); - if (ret < 0) - { - serr("ERROR: Warning: The alarm is already set\n"); - } - - return ret; -} -#endif - -/**************************************************************************** - * Name: stm32_idlepm - * - * Description: - * Perform IDLE state power management. - * - ****************************************************************************/ - -#ifdef CONFIG_PM -static void stm32_idlepm(void) -{ - static enum pm_state_e oldstate = PM_NORMAL; - enum pm_state_e newstate; - int ret; - - /* The following is logic that is done after the wake-up from PM_STANDBY - * state. It decides whether to go back to the PM_NORMAL or to the deeper - * power-saving mode PM_SLEEP: If the alarm expired with no "normal" - * wake-up event, then PM_SLEEP is entered. - * - * Logically, this code belongs at the end of the PM_STANDBY case below, - * does not work in the position for some unknown reason. - */ - - if (oldstate == PM_STANDBY) - { - /* Were we awakened by the alarm? */ - -#ifdef CONFIG_RTC_ALARM - if (g_alarmwakeup) - { - /* Yes.. Go to SLEEP mode */ - - newstate = PM_SLEEP; - } - else -#endif - { - /* Resume normal operation */ - - newstate = PM_NORMAL; - } - } - else - { - /* Let the PM system decide, which power saving level can be obtained */ - - newstate = pm_checkstate(PM_IDLE_DOMAIN); - } - - /* Check for state changes */ - - if (newstate != oldstate) - { - _info("newstate= %d oldstate=%d\n", newstate, oldstate); - - sched_lock(); - - /* Force the global state change */ - - ret = pm_changestate(PM_IDLE_DOMAIN, newstate); - if (ret < 0) - { - /* The new state change failed, revert to the preceding state */ - - pm_changestate(PM_IDLE_DOMAIN, oldstate); - - /* No state change... */ - - goto errout; - } - - /* Then perform board-specific, state-dependent logic here */ - - switch (newstate) - { - case PM_NORMAL: - { - /* If we just awakened from PM_STANDBY mode, then reconfigure - * clocking. - */ - - if (oldstate == PM_STANDBY) - { - /* Re-enable clocking */ - - stm32_clockenable(); - - /* The system timer was disabled while in PM_STANDBY or - * PM_SLEEP modes. But the RTC has still be running: Reset - * the system time the current RTC time. - */ - -#ifdef CONFIG_RTC - clock_synchronize(NULL); -#endif - } - } - break; - - case PM_IDLE: - { - } - break; - - case PM_STANDBY: - { - /* Set the alarm as an EXTI Line */ - -#ifdef CONFIG_RTC_ALARM - stm32_rtc_alarm(CONFIG_PM_ALARM_SEC, CONFIG_PM_ALARM_NSEC, true); -#endif - /* Wait 10ms */ - - up_mdelay(10); - - /* Enter the STM32 stop mode */ - - stm32_pmstop(false); - - /* We have been re-awakened by some even: A button press? - * An alarm? Cancel any pending alarm and resume the normal - * operation. - */ - -#ifdef CONFIG_RTC_ALARM - stm32_exti_cancel(); - ret = stm32_rtc_cancelalarm(); - if (ret < 0) - { - swarn("WARNING: Cancel alarm failed\n"); - } -#endif - - /* Note: See the additional PM_STANDBY related logic at the - * beginning of this function. That logic is executed after - * this point. - */ - } - break; - - case PM_SLEEP: - { - /* We should not return from standby mode. The only way out - * of standby is via the reset path. - */ - - /* Configure the RTC alarm to Auto Reset the system */ - -#ifdef CONFIG_PM_SLEEP_WAKEUP - stm32_rtc_alarm(CONFIG_PM_SLEEP_WAKEUP_SEC, - CONFIG_PM_SLEEP_WAKEUP_NSEC, false); -#endif - /* Wait 10ms */ - - up_mdelay(10); - - /* Enter the STM32 standby mode */ - - stm32_pmstandby(); - } - break; - - default: - break; - } - - /* Save the new state */ - - oldstate = newstate; - -errout: - sched_unlock(); - } -} -#else -# define stm32_idlepm() -#endif /* CONFIG_PM */ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: up_idle - * - * Description: - * up_idle() is the logic that will be executed when their is no other - * ready-to-run task. This is processor idle time and will continue until - * some interrupt occurs to cause a context switch from the idle task. - * - * Processing in this state may be processor-specific. e.g., this is where - * power management operations might be performed. - * - ****************************************************************************/ - -void up_idle(void) -{ -#if defined(CONFIG_SUPPRESS_INTERRUPTS) || defined(CONFIG_SUPPRESS_TIMER_INTS) - /* If the system is idle and there are no timer interrupts, then process - * "fake" timer interrupts. Hopefully, something will wake up. - */ - - nxsched_process_timer(); -#else - - /* Perform IDLE mode power management */ - - BEGIN_IDLE(); - stm32_idlepm(); - END_IDLE(); -#endif -} diff --git a/boards/arm/stm32/stm3210e-eval/src/stm32_lcd.c b/boards/arm/stm32/stm3210e-eval/src/stm32_lcd.c deleted file mode 100644 index 9195f4a7c88e0..0000000000000 --- a/boards/arm/stm32/stm3210e-eval/src/stm32_lcd.c +++ /dev/null @@ -1,1841 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm3210e-eval/src/stm32_lcd.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* This driver supports the following LCDs: - * - * 1. Ampire AM-240320LTNQW00H - * 2. Orise Tech SPFD5408B - * 3. RenesasSP R61580 - * - * The driver dynamically selects the LCD based on the reported LCD ID value. - * However, code size can be reduced by suppressing support for individual - * LCDs using: - * - * CONFIG_STM3210E_AM240320_DISABLE - * CONFIG_STM3210E_SPFD5408B_DISABLE - * CONFIG_STM3210E_R61580_DISABLE - * - * Omitting the above (or setting them to "n") enables support for the LCD. - * Setting any of the above to "y" will disable support for the - * corresponding LCD. - */ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -#include -#include - -#include "arm_internal.h" -#include "stm32.h" -#include "stm3210e-eval.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -/* Check contrast selection */ - -#if !defined(CONFIG_LCD_MAXCONTRAST) -# define CONFIG_LCD_MAXCONTRAST 1 -#endif - -/* Backlight */ - -#ifndef CONFIG_STM3210E_LCD_BACKLIGHT -# undef CONFIG_STM3210E_LCD_PWM -#endif - -#if defined(CONFIG_STM3210E_LCD_BACKLIGHT) && defined(CONFIG_STM3210E_LCD_PWM) -# if !defined(CONFIG_STM32_TIM1) -# warning "CONFIG_STM3210E_LCD_PWM requires CONFIG_STM32_TIM1" -# undef CONFIG_STM3210E_LCD_PWM -# endif -# if defined(CONFIG_STM32_TIM1_FULL_REMAP) -# warning "PA8 cannot be configured as TIM1 CH1 with full remap" -# undef CONFIG_STM3210E_LCD_PWM -# endif -#endif - -#if defined(CONFIG_STM3210E_LCD_BACKLIGHT) && defined(CONFIG_STM3210E_LCD_PWM) -# if CONFIG_LCD_MAXPOWER < 2 -# warning "A larger value of CONFIG_LCD_MAXPOWER is recommended" -# endif -#endif - -/* Check power setting */ - -#if !defined(CONFIG_LCD_MAXPOWER) || CONFIG_LCD_MAXPOWER < 1 -# undef CONFIG_LCD_MAXPOWER -# if defined(CONFIG_STM3210E_LCD_BACKLIGHT) && defined(CONFIG_STM3210E_LCD_PWM) -# define CONFIG_LCD_MAXPOWER 100 -# else -# define CONFIG_LCD_MAXPOWER 1 -# endif -#endif - -#if CONFIG_LCD_MAXPOWER > 255 -# error "CONFIG_LCD_MAXPOWER must be less than 256 to fit in uint8_t" -#endif - -/* PWM Frequency */ - -#ifndef CONFIG_STM3210E_LCD_PWMFREQUENCY -# define CONFIG_STM3210E_LCD_PWMFREQUENCY 100 -#endif - -/* Check orientation */ - -#if defined(CONFIG_LCD_PORTRAIT) -# if defined(CONFIG_LCD_LANDSCAPE) || defined(CONFIG_LCD_RPORTRAIT) -# error "Cannot define both portrait and any other orientations" -# endif -#elif defined(CONFIG_LCD_RPORTRAIT) -# if defined(CONFIG_LCD_LANDSCAPE) || defined(CONFIG_LCD_PORTRAIT) -# error "Cannot define both rportrait and any other orientations" -# endif -#elif !defined(CONFIG_LCD_LANDSCAPE) -# define CONFIG_LCD_LANDSCAPE 1 -#endif - -/* When reading 16-bit gram data, there may some shifts in the returned data - * and/or there may be some colors in the incorrect posisions: - * - * - SPFD5408B: There appears to be a 5-bit shift in the returned data. - * Red and green appear to be swapped on read-back as well - * - R61580: There is a 16-bit (1 pixel) shift in the returned data. - * - AM240320: Unknown -- assume colors are correct for now. - */ - -#define SPFD5408B_RDSHIFT 5 - -/* Display/Color Properties *************************************************/ - -/* Display Resolution */ - -#ifdef CONFIG_LCD_LANDSCAPE -# define STM3210E_XRES 320 -# define STM3210E_YRES 240 -#else -# define STM3210E_XRES 240 -# define STM3210E_YRES 320 -#endif - -/* Color depth and format */ - -#define STM3210E_BPP 16 -#define STM3210E_COLORFMT FB_FMT_RGB16_565 - -/* STM3210E-EVAL LCD Hardware Definitions ***********************************/ - -/* LCD /CS is CE4, Bank 4 of NOR/SRAM Bank 1~4 */ - -#define STM3210E_LCDBASE ((uint32_t)(0x60000000 | 0x0c000000)) -#define LCD ((struct lcd_regs_s *) STM3210E_LCDBASE) - -#define LCD_REG_0 0x00 -#define LCD_REG_1 0x01 -#define LCD_REG_2 0x02 -#define LCD_REG_3 0x03 -#define LCD_REG_4 0x04 -#define LCD_REG_5 0x05 -#define LCD_REG_6 0x06 -#define LCD_REG_7 0x07 -#define LCD_REG_8 0x08 -#define LCD_REG_9 0x09 -#define LCD_REG_10 0x0a -#define LCD_REG_12 0x0c -#define LCD_REG_13 0x0d -#define LCD_REG_14 0x0e -#define LCD_REG_15 0x0f -#define LCD_REG_16 0x10 -#define LCD_REG_17 0x11 -#define LCD_REG_18 0x12 -#define LCD_REG_19 0x13 -#define LCD_REG_20 0x14 -#define LCD_REG_21 0x15 -#define LCD_REG_22 0x16 -#define LCD_REG_23 0x17 -#define LCD_REG_24 0x18 -#define LCD_REG_25 0x19 -#define LCD_REG_26 0x1a -#define LCD_REG_27 0x1b -#define LCD_REG_28 0x1c -#define LCD_REG_29 0x1d -#define LCD_REG_30 0x1e -#define LCD_REG_31 0x1f -#define LCD_REG_32 0x20 -#define LCD_REG_33 0x21 -#define LCD_REG_34 0x22 -#define LCD_REG_36 0x24 -#define LCD_REG_37 0x25 -#define LCD_REG_40 0x28 -#define LCD_REG_41 0x29 -#define LCD_REG_43 0x2b -#define LCD_REG_45 0x2d -#define LCD_REG_48 0x30 -#define LCD_REG_49 0x31 -#define LCD_REG_50 0x32 -#define LCD_REG_51 0x33 -#define LCD_REG_52 0x34 -#define LCD_REG_53 0x35 -#define LCD_REG_54 0x36 -#define LCD_REG_55 0x37 -#define LCD_REG_56 0x38 -#define LCD_REG_57 0x39 -#define LCD_REG_58 0x3a -#define LCD_REG_59 0x3b -#define LCD_REG_60 0x3c -#define LCD_REG_61 0x3d -#define LCD_REG_62 0x3e -#define LCD_REG_63 0x3f -#define LCD_REG_64 0x40 -#define LCD_REG_65 0x41 -#define LCD_REG_66 0x42 -#define LCD_REG_67 0x43 -#define LCD_REG_68 0x44 -#define LCD_REG_69 0x45 -#define LCD_REG_70 0x46 -#define LCD_REG_71 0x47 -#define LCD_REG_72 0x48 -#define LCD_REG_73 0x49 -#define LCD_REG_74 0x4a -#define LCD_REG_75 0x4b -#define LCD_REG_76 0x4c -#define LCD_REG_77 0x4d -#define LCD_REG_78 0x4e -#define LCD_REG_79 0x4f -#define LCD_REG_80 0x50 -#define LCD_REG_81 0x51 -#define LCD_REG_82 0x52 -#define LCD_REG_83 0x53 -#define LCD_REG_96 0x60 -#define LCD_REG_97 0x61 -#define LCD_REG_106 0x6a -#define LCD_REG_118 0x76 -#define LCD_REG_128 0x80 -#define LCD_REG_129 0x81 -#define LCD_REG_130 0x82 -#define LCD_REG_131 0x83 -#define LCD_REG_132 0x84 -#define LCD_REG_133 0x85 -#define LCD_REG_134 0x86 -#define LCD_REG_135 0x87 -#define LCD_REG_136 0x88 -#define LCD_REG_137 0x89 -#define LCD_REG_139 0x8b -#define LCD_REG_140 0x8c -#define LCD_REG_141 0x8d -#define LCD_REG_143 0x8f -#define LCD_REG_144 0x90 -#define LCD_REG_145 0x91 -#define LCD_REG_146 0x92 -#define LCD_REG_147 0x93 -#define LCD_REG_148 0x94 -#define LCD_REG_149 0x95 -#define LCD_REG_150 0x96 -#define LCD_REG_151 0x97 -#define LCD_REG_152 0x98 -#define LCD_REG_153 0x99 -#define LCD_REG_154 0x9a -#define LCD_REG_157 0x9d -#define LCD_REG_164 0xa4 -#define LCD_REG_192 0xc0 -#define LCD_REG_193 0xc1 -#define LCD_REG_229 0xe5 - -/* LCD IDs */ - -#define SPFD5408B_ID 0x5408 -#define R61580_ID 0x1580 - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/* LCD type */ - -enum lcd_type_e -{ - LCD_TYPE_UNKNOWN = 0, - LCD_TYPE_SPFD5408B, - LCD_TYPE_R61580, - LCD_TYPE_AM240320 -}; - -/* This structure describes the LCD registers */ - -struct lcd_regs_s -{ - volatile uint16_t address; - volatile uint16_t value; -}; - -/* This structure describes the state of this driver */ - -struct stm3210e_dev_s -{ - /* Publicly visible device structure */ - - struct lcd_dev_s dev; - -#if defined(CONFIG_STM3210E_LCD_BACKLIGHT) && defined(CONFIG_STM3210E_LCD_PWM) - uint32_t reload; -#endif - - /* Private LCD-specific information follows */ - - uint8_t type; /* LCD type. See enum lcd_type_e */ - uint8_t power; /* Current power setting */ -}; - -/**************************************************************************** - * Private Function Protototypes - ****************************************************************************/ - -/* Low Level LCD access */ - -static void stm3210e_writereg(uint8_t regaddr, uint16_t regval); -static uint16_t stm3210e_readreg(uint8_t regaddr); -static inline void stm3210e_gramselect(void); -static inline void stm3210e_writegram(uint16_t rgbval); -static void stm3210e_readsetup(uint16_t *accum); -#ifndef CONFIG_STM3210E_AM240320_DISABLE -static void stm3210e_readnosetup(uint16_t *accum); -#endif -static uint16_t stm3210e_readshift(uint16_t *accum); -static uint16_t stm3210e_readnoshift(uint16_t *accum); -static void stm3210e_setcursor(uint16_t col, uint16_t row); - -/* LCD Data Transfer Methods */ - -static int stm3210e_putrun(struct lcd_dev_s *dev, - fb_coord_t row, fb_coord_t col, - const uint8_t *buffer, - size_t npixels); -static int stm3210e_getrun(struct lcd_dev_s *dev, - fb_coord_t row, fb_coord_t col, - uint8_t *buffer, - size_t npixels); - -/* LCD Configuration */ - -static int stm3210e_getvideoinfo(struct lcd_dev_s *dev, - struct fb_videoinfo_s *vinfo); -static int stm3210e_getplaneinfo(struct lcd_dev_s *dev, - unsigned int planeno, - struct lcd_planeinfo_s *pinfo); - -/* LCD RGB Mapping */ - -#ifdef CONFIG_FB_CMAP -# error "RGB color mapping not supported by this driver" -#endif - -/* Cursor Controls */ - -#ifdef CONFIG_FB_HWCURSOR -# error "Cursor control not supported by this driver" -#endif - -/* LCD Specific Controls */ - -static int stm3210e_getpower(struct lcd_dev_s *dev); -static int stm3210e_setpower(struct lcd_dev_s *dev, int power); -static int stm3210e_getcontrast(struct lcd_dev_s *dev); -static int stm3210e_setcontrast(struct lcd_dev_s *dev, - unsigned int contrast); - -/* LCD Power Management */ - -#ifdef CONFIG_PM -static void stm3210e_pm_notify(struct pm_callback_s *cb, int domain, - enum pm_state_e pmstate); -static int stm3210e_pm_prepare(struct pm_callback_s *cb, int domain, - enum pm_state_e pmstate); -#endif - -/* Initialization */ - -static inline void stm3210e_lcdinitialize(void); -#ifdef CONFIG_STM3210E_LCD_BACKLIGHT -static void stm3210e_backlight(void); -#else -# define stm3210e_backlight() -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* This is working memory allocated by the LCD driver for each LCD device - * and for each color plane. This memory will hold one raster line of data. - * The size of the allocated run buffer must therefore be at least - * (bpp * xres / 8). Actual alignment of the buffer must conform to the - * bitwidth of the underlying pixel type. - * - * If there are multiple planes, they may share the same working buffer - * because different planes will not be operate on concurrently. However, - * if there are multiple LCD devices, they must each have unique run buffers. - */ - -static uint16_t g_runbuffer[STM3210E_XRES]; - -/* This structure describes the overall LCD video controller */ - -static const struct fb_videoinfo_s g_videoinfo = -{ - .fmt = STM3210E_COLORFMT, /* Color format: RGB16-565: RRRR RGGG GGGB BBBB */ - .xres = STM3210E_XRES, /* Horizontal resolution in pixel columns */ - .yres = STM3210E_YRES, /* Vertical resolution in pixel rows */ - .nplanes = 1, /* Number of color planes supported */ -}; - -/* This is the standard, NuttX Plane information object */ - -static const struct lcd_planeinfo_s g_planeinfo = -{ - .putrun = stm3210e_putrun, /* Put a run into LCD memory */ - .getrun = stm3210e_getrun, /* Get a run from LCD memory */ - .buffer = (uint8_t *)g_runbuffer, /* Run scratch buffer */ - .bpp = STM3210E_BPP, /* Bits-per-pixel */ -}; - -/* This is the standard, NuttX LCD driver object */ - -static struct stm3210e_dev_s g_lcddev = -{ - .dev = - { - /* LCD Configuration */ - - .getvideoinfo = stm3210e_getvideoinfo, - .getplaneinfo = stm3210e_getplaneinfo, - - /* LCD RGB Mapping -- Not supported */ - - /* Cursor Controls -- Not supported */ - - /* LCD Specific Controls */ - - .getpower = stm3210e_getpower, - .setpower = stm3210e_setpower, - .getcontrast = stm3210e_getcontrast, - .setcontrast = stm3210e_setcontrast, - }, -}; - -#ifdef CONFIG_PM -static struct pm_callback_s g_lcdcb = -{ - .notify = stm3210e_pm_notify, - .prepare = stm3210e_pm_prepare, -}; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm3210e_writereg - * - * Description: - * Write to an LCD register - * - ****************************************************************************/ - -static void stm3210e_writereg(uint8_t regaddr, uint16_t regval) -{ - /* Write the register address then write the register value */ - - LCD->address = regaddr; - LCD->value = regval; -} - -/**************************************************************************** - * Name: stm3210e_readreg - * - * Description: - * Read from an LCD register - * - ****************************************************************************/ - -static uint16_t stm3210e_readreg(uint8_t regaddr) -{ - /* Write the register address then read the register value */ - - LCD->address = regaddr; - return LCD->value; -} - -/**************************************************************************** - * Name: stm3210e_gramselect - * - * Description: - * Setup to read or write multiple pixels to the GRAM memory - * - ****************************************************************************/ - -static inline void stm3210e_gramselect(void) -{ - LCD->address = LCD_REG_34; -} - -/**************************************************************************** - * Name: stm3210e_writegram - * - * Description: - * Write one pixel to the GRAM memory - * - ****************************************************************************/ - -static inline void stm3210e_writegram(uint16_t rgbval) -{ - /* Write the value (GRAM register already selected) */ - - LCD->value = rgbval; -} - -/**************************************************************************** - * Name: stm3210e_readsetup / stm3210e_readnosetup - * - * Description: - * Prime the operation by reading one pixel from the GRAM memory if - * necessary for this LCD type. When reading 16-bit gram data, there may - * be some shifts in the returned data: - * - * - SPFD5408B: There appears to be a 5-bit shift in the returned data. - * - R61580: There is a 16-bit (1 pixel) shift in the returned data. - * - AM240320: Unknown -- assuming no shift in the return data - * - ****************************************************************************/ - -/* Used for SPFD5408B and R61580 */ - -#if !defined(CONFIG_STM3210E_SPFD5408B_DISABLE) || !defined(CONFIG_STM3210E_R61580_DISABLE) -static void stm3210e_readsetup(uint16_t *accum) -{ - /* Read-ahead one pixel */ - - *accum = LCD->value; -} -#endif - -/* Used only for AM240320 */ - -#ifndef CONFIG_STM3210E_AM240320_DISABLE -static void stm3210e_readnosetup(uint16_t *accum) -{ -} -#endif - -/**************************************************************************** - * Name: stm3210e_readshift / stm3210e_readnoshift - * - * Description: - * Read one correctly aligned pixel from the GRAM memory. Possibly - * shifting the data and possibly swapping red and green components. - * - * - SPFD5408B: There appears to be a 5-bit shift in the returned data. - * Red and green appear to be swapped on read-back as well - * - R61580: There is a 16-bit (1 pixel) shift in the returned data. - * All colors in the normal order - * - AM240320: Unknown -- assuming colors are in the color order - * - ****************************************************************************/ - -/* This version is used only for the SPFD5408B. It shifts the data by - * 5-bits and swaps red and green - */ - -#ifndef CONFIG_STM3210E_SPFD5408B_DISABLE -static uint16_t stm3210e_readshift(uint16_t *accum) -{ - uint16_t red; - uint16_t green; - uint16_t blue; - - /* Read the value (GRAM register already selected) */ - - uint16_t next = LCD->value; - - /* Return previous bits 0-10 as bits 6-15 and next data bits 11-15 as - * bits 0-5 - * - * xxxx xPPP PPPP PPPP - * NNNN Nxxx xxxx xxxx - * - * Assuming that SPFD5408B_RDSHIFT == 5 - */ - - uint16_t value = *accum << SPFD5408B_RDSHIFT | - next >> (16 - SPFD5408B_RDSHIFT); - - /* Save the value for the next time we are called */ - - *accum = next; - - /* Tear the RGB655 apart. Swap read and green */ - - red = (value << (11 - 5)) & 0xf800; /* Move bits 5-9 to 11-15 */ - green = (value >> (10 - 5)) & 0x07e0; /* Move bits 10-15 to bits 5-10 */ - blue = value & 0x001f; /* Blue is in the right place */ - - /* And put the RGB565 back together */ - - value = red | green | blue; - - /* This is weird... If blue is zero, then red+green values are off by 0x20. - * Except that both 0x0000 and 0x0020 can map to 0x0000. Need to revisit - * this!!!!!!!!!!! I might be misinterpreting some of the data that I - * have. - */ - -#if 0 /* REVISIT */ - if (value != 0 && blue == 0) - { - value += 0x20; - } -#endif - - return value; -} -#endif - -/* This version is used for the R61580 and for the AM240320. It neither - * shifts nor swaps colors. - */ - -#if !defined(CONFIG_STM3210E_R61580_DISABLE) || !defined(CONFIG_STM3210E_AM240320_DISABLE) -static uint16_t stm3210e_readnoshift(uint16_t *accum) -{ - /* Read the value (GRAM register already selected) */ - - return LCD->value; -} -#endif - -/**************************************************************************** - * Name: stm3210e_setcursor - * - * Description: - * Set the cursor position. In landscape mode, the "column" is actually - * the physical Y position and the "row" is the physical X position. - * - ****************************************************************************/ - -static void stm3210e_setcursor(uint16_t col, uint16_t row) -{ - stm3210e_writereg(LCD_REG_32, row); /* GRAM horizontal address */ - stm3210e_writereg(LCD_REG_33, col); /* GRAM vertical address */ -} - -/**************************************************************************** - * Name: stm3210e_putrun - * - * Description: - * This method can be used to write a partial raster line to the LCD: - * - * dev - The lcd device - * row - Starting row to write to (range: 0 <= row < yres) - * col - Starting column to write to (range: 0 <= col <= xres-npixels) - * buffer - The buffer containing the run to be written to the LCD - * npixels - The number of pixels to write to the LCD - * (range: 0 < npixels <= xres-col) - * - ****************************************************************************/ - -static int stm3210e_putrun(struct lcd_dev_s *dev, - fb_coord_t row, fb_coord_t col, - const uint8_t *buffer, - size_t npixels) -{ - const uint16_t *src = (const uint16_t *)buffer; - int i; - - /* Buffer must be provided and aligned to a 16-bit address boundary */ - - lcdinfo("row: %d col: %d npixels: %d\n", row, col, npixels); - DEBUGASSERT(buffer && ((uintptr_t)buffer & 1) == 0); - - /* Write the run to GRAM. */ - -#ifdef CONFIG_LCD_LANDSCAPE - /* Convert coordinates -- Which edge of the display is the "top?" Here the - * edge with the simplest conversion is used. - */ - - col = (STM3210E_XRES - 1) - col; - - /* Set the cursor position */ - - stm3210e_setcursor(col, row); - - /* Then write the GRAM data, auto-decrementing X */ - - stm3210e_gramselect(); - for (i = 0; i < npixels; i++) - { - /* Write the next pixel to this position (auto-decrements to the next - * column) - */ - - stm3210e_writegram(*src++); - } -#elif defined(CONFIG_LCD_PORTRAIT) - /* Convert coordinates. (Swap row and column. This is done implicitly). */ - - /* Then write the GRAM data, manually incrementing Y (which is col) */ - - for (i = 0; i < npixels; i++) - { - /* Write the next pixel to this position */ - - stm3210e_setcursor(row, col); - stm3210e_gramselect(); - stm3210e_writegram(*src++); - - /* Increment to next column */ - - col++; - } -#else /* CONFIG_LCD_RPORTRAIT */ - /* Convert coordinates. (Swap row and column. This is done implicitly). - * Which edge of the display is the "top"? - */ - - col = (STM3210E_XRES - 1) - col; - row = (STM3210E_YRES - 1) - row; - - /* Then write the GRAM data, manually incrementing Y (which is col) */ - - for (i = 0; i < npixels; i++) - { - /* Write the next pixel to this position */ - - stm3210e_setcursor(row, col); - stm3210e_gramselect(); - stm3210e_writegram(*src++); - - /* Decrement to next column */ - - col--; - } -#endif - - return OK; -} - -/**************************************************************************** - * Name: stm3210e_getrun - * - * Description: - * This method can be used to read a partial raster line from the LCD: - * - * dev - The lcd device - * row - Starting row to read from (range: 0 <= row < yres) - * col - Starting column to read read (range: 0 <= col <= xres-npixels) - * buffer - The buffer in which to return the run read from the LCD - * npixels - The number of pixels to read from the LCD - * (range: 0 < npixels <= xres-col) - * - ****************************************************************************/ - -static int stm3210e_getrun(struct lcd_dev_s *dev, - fb_coord_t row, fb_coord_t col, - uint8_t *buffer, - size_t npixels) -{ - uint16_t *dest = (uint16_t *)buffer; - void (*readsetup)(uint16_t *accum); - uint16_t (*readgram)(uint16_t *accum); - uint16_t accum; - int i; - - /* Buffer must be provided and aligned to a 16-bit address boundary */ - - lcdinfo("row: %d col: %d npixels: %d\n", row, col, npixels); - DEBUGASSERT(buffer && ((uintptr_t)buffer & 1) == 0); - - /* Configure according to the LCD type */ - - switch (g_lcddev.type) - { -#ifndef CONFIG_STM3210E_SPFD5408B_DISABLE - case LCD_TYPE_SPFD5408B: - readsetup = stm3210e_readsetup; - readgram = stm3210e_readshift; - break; -#endif - -#ifndef CONFIG_STM3210E_R61580_DISABLE - case LCD_TYPE_R61580: - readsetup = stm3210e_readsetup; - readgram = stm3210e_readnoshift; - break; -#endif - -#ifndef CONFIG_STM3210E_AM240320_DISABLE - case LCD_TYPE_AM240320: - readsetup = stm3210e_readnosetup; - readgram = stm3210e_readnoshift; - break; -#endif - - default: /* Shouldn't happen */ - return -ENOSYS; - } - - /* Read the run from GRAM. */ - -#ifdef CONFIG_LCD_LANDSCAPE - /* Convert coordinates -- Which edge of the display is the "top?" Here the - * edge with the simplest conversion is used. - */ - - col = (STM3210E_XRES - 1) - col; - - /* Set the cursor position */ - - stm3210e_setcursor(col, row); - - /* Then read the GRAM data, auto-decrementing Y */ - - stm3210e_gramselect(); - - /* Prime the pump for unaligned read data */ - - readsetup(&accum); - - for (i = 0; i < npixels; i++) - { - /* Read the next pixel from this position (autoincrements to the next - * row) - */ - - *dest++ = readgram(&accum); - } -#elif defined(CONFIG_LCD_PORTRAIT) - /* Convert coordinates (Swap row and column. This is done implicitly). */ - - /* Then read the GRAM data, manually incrementing Y (which is col) */ - - for (i = 0; i < npixels; i++) - { - /* Read the next pixel from this position */ - - stm3210e_setcursor(row, col); - stm3210e_gramselect(); - readsetup(&accum); - *dest++ = readgram(&accum); - - /* Increment to next column */ - - col++; - } -#else /* CONFIG_LCD_RPORTRAIT */ - /* Convert coordinates. (Swap row and column. This is done implicitly). - * Which edge of the display is the "top"? - */ - - col = (STM3210E_XRES - 1) - col; - row = (STM3210E_YRES - 1) - row; - - /* Then write the GRAM data, manually incrementing Y (which is col) */ - - for (i = 0; i < npixels; i++) - { - /* Write the next pixel to this position */ - - stm3210e_setcursor(row, col); - stm3210e_gramselect(); - readsetup(&accum); - *dest++ = readgram(&accum); - - /* Decrement to next column */ - - col--; - } -#endif - - return OK; -} - -/**************************************************************************** - * Name: stm3210e_getvideoinfo - * - * Description: - * Get information about the LCD video controller configuration. - * - ****************************************************************************/ - -static int stm3210e_getvideoinfo(struct lcd_dev_s *dev, - struct fb_videoinfo_s *vinfo) -{ - DEBUGASSERT(dev && vinfo); - ginfo("fmt: %d xres: %d yres: %d nplanes: %d\n", - g_videoinfo.fmt, g_videoinfo.xres, - g_videoinfo.yres, g_videoinfo.nplanes); - memcpy(vinfo, &g_videoinfo, sizeof(struct fb_videoinfo_s)); - return OK; -} - -/**************************************************************************** - * Name: stm3210e_getplaneinfo - * - * Description: - * Get information about the configuration of each LCD color plane. - * - ****************************************************************************/ - -static int stm3210e_getplaneinfo(struct lcd_dev_s *dev, - unsigned int planeno, - struct lcd_planeinfo_s *pinfo) -{ - DEBUGASSERT(dev && pinfo && planeno == 0); - ginfo("planeno: %d bpp: %d\n", planeno, g_planeinfo.bpp); - memcpy(pinfo, &g_planeinfo, sizeof(struct lcd_planeinfo_s)); - pinfo->dev = dev; - return OK; -} - -/**************************************************************************** - * Name: stm3210e_getpower - * - * Description: - * Get the LCD panel power status (0: full off - CONFIG_LCD_MAXPOWER: - * full on). On backlit LCDs, this setting may correspond to the backlight - * setting. - * - ****************************************************************************/ - -static int stm3210e_getpower(struct lcd_dev_s *dev) -{ - ginfo("power: %d\n", 0); - return g_lcddev.power; -} - -/**************************************************************************** - * Name: stm3210e_poweroff - * - * Description: - * Enable/disable LCD panel power (0: full off - CONFIG_LCD_MAXPOWER: - * full on). On backlit LCDs, this setting may correspond to the backlight - * setting. - * - ****************************************************************************/ - -static int stm3210e_poweroff(void) -{ - /* Turn the display off */ - - stm3210e_writereg(LCD_REG_7, 0); - - /* Disable timer 1 clocking */ - -#if defined(CONFIG_STM3210E_LCD_BACKLIGHT) -# if defined(CONFIG_STM3210E_LCD_PWM) - modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM1EN, 0); -# endif - - /* Configure the PA8 pin as an output */ - - stm32_configgpio(GPIO_LCD_BACKLIGHT); - - /* Turn the backlight off */ - - stm32_gpiowrite(GPIO_LCD_BACKLIGHT, false); -#endif - - /* Remember the power off state */ - - g_lcddev.power = 0; - return OK; -} - -/**************************************************************************** - * Name: stm3210e_setpower - * - * Description: - * Enable/disable LCD panel power (0: full off - CONFIG_LCD_MAXPOWER: - * full on). On backlit LCDs, this setting may correspond to the backlight - * setting. - * - ****************************************************************************/ - -static int stm3210e_setpower(struct lcd_dev_s *dev, int power) -{ - ginfo("power: %d\n", power); - DEBUGASSERT((unsigned)power <= CONFIG_LCD_MAXPOWER); - - /* Set new power level */ - - if (power > 0) - { -#if defined(CONFIG_STM3210E_LCD_BACKLIGHT) && defined(CONFIG_STM3210E_LCD_PWM) - uint32_t frac; - uint32_t duty; - - /* If we are coming up from the power off state, then re-configure - * the timer - */ - - if (g_lcddev.power == 0) - { - stm3210e_backlight(); - } - - /* Make sure that the power value is within range */ - - if (power > CONFIG_LCD_MAXPOWER) - { - power = CONFIG_LCD_MAXPOWER; - } - - /* Calculate the new backlight duty. It is a faction of the timer1 - * period based on the ration of the current power setting to the - * maximum power setting. - */ - - frac = (power << 16) / CONFIG_LCD_MAXPOWER; - duty = (g_lcddev.reload * frac) >> 16; - if (duty > 0) - { - duty--; - } - - putreg16((uint16_t)duty, STM32_TIM1_CCR1); -#else - /* Turn the backlight on */ - - stm32_gpiowrite(GPIO_LCD_BACKLIGHT, true); -#endif - /* Then turn the display on */ - -#ifndef CONFIG_STM3210E_AM240320_DISABLE -# if !defined (CONFIG_STM3210E_SPFD5408B_DISABLE) || !defined(CONFIG_STM3210E_R61580_DISABLE) - stm3210e_writereg(LCD_REG_7, - g_lcddev.type == LCD_TYPE_AM240320 ? - 0x0173 : 0x0112); -# else - stm3210e_writereg(LCD_REG_7, 0x0173); -# endif -#else - stm3210e_writereg(LCD_REG_7, 0x0112); -#endif - g_lcddev.power = power; - } - else - { - /* Turn the display off */ - - stm3210e_poweroff(); - } - - return OK; -} - -/**************************************************************************** - * Name: stm3210e_getcontrast - * - * Description: - * Get the current contrast setting (0-CONFIG_LCD_MAXCONTRAST). - * - ****************************************************************************/ - -static int stm3210e_getcontrast(struct lcd_dev_s *dev) -{ - ginfo("Not implemented\n"); - return -ENOSYS; -} - -/**************************************************************************** - * Name: stm3210e_setcontrast - * - * Description: - * Set LCD panel contrast (0-CONFIG_LCD_MAXCONTRAST). - * - ****************************************************************************/ - -static int stm3210e_setcontrast(struct lcd_dev_s *dev, unsigned int contrast) -{ - ginfo("contrast: %d\n", contrast); - return -ENOSYS; -} - -/**************************************************************************** - * Name: stm3210e_pm_notify - * - * Description: - * Notify the driver of new power state. This callback is called after - * all drivers have had the opportunity to prepare for the new power state. - * - * Input Parameters: - * - * cb - Returned to the driver. The driver version of the callback - * structure may include additional, driver-specific state data at - * the end of the structure. - * - * pmstate - Identifies the new PM state - * - * Returned Value: - * None - The driver already agreed to transition to the low power - * consumption state when when it returned OK to the prepare() call. - * - * - ****************************************************************************/ - -#ifdef CONFIG_PM -static void stm3210e_pm_notify(struct pm_callback_s *cb, int domain, - enum pm_state_e pmstate) -{ -#ifdef CONFIG_STM3210E_LCD_PWM - uint32_t frac; - uint32_t duty; -#endif - - switch (pmstate) - { - case PM_NORMAL: - { - /* Restore normal LCD operation */ - -#ifdef CONFIG_STM3210E_LCD_PWM - frac = (g_lcddev.power << 16) / CONFIG_LCD_MAXPOWER; - duty = (g_lcddev.reload * frac) >> 16; - if (duty > 0) - { - duty--; - } - - putreg16((uint16_t)duty, STM32_TIM1_CCR1); -#endif - } - break; - - case PM_IDLE: - { - /* Entering IDLE mode - Reduce LCD light */ - -#ifdef CONFIG_STM3210E_LCD_PWM - frac = (g_lcddev.power << 16) / CONFIG_LCD_MAXPOWER; - duty = (g_lcddev.reload * frac) >> 16; - if (duty > 0) - { - duty--; - } - - /* Reduce the LCD backlight to 50% of the MAXPOWER */ - - duty >>= 1; - putreg16((uint16_t)duty, STM32_TIM1_CCR1); -#endif - } - break; - - case PM_STANDBY: - { - /* Entering STANDBY mode - Turn display backlight off */ - -#ifdef CONFIG_STM3210E_LCD_PWM - putreg16(0, STM32_TIM1_CCR1); -#endif - } - break; - - case PM_SLEEP: - { - /* Entering SLEEP mode - Turn off LCD */ - - if (g_lcddev.type == LCD_TYPE_AM240320) - { - /* Display off sequence */ - - stm3210e_writereg(LCD_REG_0, 0xa0); /* White display mode setting */ - up_mdelay(10); /* Wait for 2 frame scan */ - stm3210e_writereg(LCD_REG_59, 0x00); /* Gate scan stop */ - - /* Power off sequence */ - - stm3210e_writereg(LCD_REG_30, 0x09); /* VCOM stop */ - stm3210e_writereg(LCD_REG_27, 0x0e); /* VS/VDH turn off */ - stm3210e_writereg(LCD_REG_24, 0xc0); /* CP1, CP2, CP3 turn off */ - up_mdelay(10); /* wait 10 ms */ - - stm3210e_writereg(LCD_REG_24, 0x00); /* VR1 / VR2 off */ - stm3210e_writereg(LCD_REG_28, 0x30); /* Step up circuit operating current stop */ - up_mdelay(10); - - stm3210e_poweroff(); - stm3210e_writereg(LCD_REG_0, 0xa0); /* White display mode setting */ - up_mdelay(10); /* Wait for 2 frame scan */ - - stm3210e_writereg(LCD_REG_59, 0x00); /* Gate scan stop */ - } - else - { - stm3210e_poweroff(); - } - } - break; - - default: - { - /* Should not get here */ - } - break; - } -} -#endif - -/**************************************************************************** - * Name: stm3210e_pm_prepare - * - * Description: - * Request the driver to prepare for a new power state. This is a warning - * that the system is about to enter into a new power state. The driver - * should begin whatever operations that may be required to enter power - * state. The driver may abort the state change mode by returning a - * non-zero value from the callback function. - * - * Input Parameters: - * - * cb - Returned to the driver. The driver version of the callback - * structure may include additional, driver-specific state data at - * the end of the structure. - * - * pmstate - Identifies the new PM state - * - * Returned Value: - * Zero - (OK) means the event was successfully processed and that the - * driver is prepared for the PM state change. - * - * Non-zero - means that the driver is not prepared to perform the tasks - * needed achieve this power setting and will cause the state - * change to be aborted. NOTE: The prepare() method will also - * be called when reverting from lower back to higher power - * consumption modes (say because another driver refused a - * lower power state change). Drivers are not permitted to - * return non-zero values when reverting back to higher power - * consumption modes! - * - * - ****************************************************************************/ - -#ifdef CONFIG_PM -static int stm3210e_pm_prepare(struct pm_callback_s *cb, int domain, - enum pm_state_e pmstate) -{ - /* No preparation to change power modes is required by the LCD driver. - * We always accept the state change by returning OK. - */ - - return OK; -} -#endif - -/**************************************************************************** - * Name: stm3210e_lcdinitialize - * - * Description: - * Set LCD panel contrast (0-CONFIG_LCD_MAXCONTRAST). - * - ****************************************************************************/ - -static inline void stm3210e_lcdinitialize(void) -{ - uint16_t id; - - /* Check if the LCD is Orise Tech SPFD5408B Controller (or the compatible - * RenesasSP R61580). - */ - - id = stm3210e_readreg(LCD_REG_0); - lcdinfo("LCD ID: %04x\n", id); - - /* Check if the ID is for the SPFD5408B */ - -#if !defined(CONFIG_STM3210E_SPFD5408B_DISABLE) - if (id == SPFD5408B_ID) - { - /* Set the LCD type for the SPFD5408B */ - - g_lcddev.type = LCD_TYPE_SPFD5408B; - lcdinfo("LCD type: %d\n", g_lcddev.type); - - /* Start Initial Sequence */ - - stm3210e_writereg(LCD_REG_1, 0x0100); /* Set SS bit */ - stm3210e_writereg(LCD_REG_2, 0x0700); /* Set 1 line inversion */ - stm3210e_writereg(LCD_REG_3, 0x1030); /* Set GRAM write direction and BGR=1. */ - stm3210e_writereg(LCD_REG_4, 0x0000); /* Resize register */ - stm3210e_writereg(LCD_REG_8, 0x0202); /* Set the back porch and front porch */ - stm3210e_writereg(LCD_REG_9, 0x0000); /* Set non-display area refresh cycle ISC[3:0] */ - stm3210e_writereg(LCD_REG_10, 0x0000); /* FMARK function */ - stm3210e_writereg(LCD_REG_12, 0x0000); /* RGB 18-bit System interface setting */ - stm3210e_writereg(LCD_REG_13, 0x0000); /* Frame marker Position */ - stm3210e_writereg(LCD_REG_15, 0x0000); /* RGB interface polarity, no impact */ - - /* Power On sequence */ - - stm3210e_writereg(LCD_REG_16, 0x0000); /* SAP, BT[3:0], AP, DSTB, SLP, STB */ - stm3210e_writereg(LCD_REG_17, 0x0000); /* DC1[2:0], DC0[2:0], VC[2:0] */ - stm3210e_writereg(LCD_REG_18, 0x0000); /* VREG1OUT voltage */ - stm3210e_writereg(LCD_REG_19, 0x0000); /* VDV[4:0] for VCOM amplitude */ - up_mdelay(200); /* Dis-charge capacitor power voltage (200ms) */ - - stm3210e_writereg(LCD_REG_17, 0x0007); /* DC1[2:0], DC0[2:0], VC[2:0] */ - up_mdelay(50); - - stm3210e_writereg(LCD_REG_16, 0x12b0); /* SAP, BT[3:0], AP, DSTB, SLP, STB */ - up_mdelay(50); - - stm3210e_writereg(LCD_REG_18, 0x01bd); /* External reference voltage= Vci */ - up_mdelay(50); - - stm3210e_writereg(LCD_REG_19, 0x1400); /* VDV[4:0] for VCOM amplitude */ - stm3210e_writereg(LCD_REG_41, 0x000e); /* VCM[4:0] for VCOMH */ - up_mdelay(50); - - stm3210e_writereg(LCD_REG_32, 0x0000); /* GRAM horizontal Address */ - stm3210e_writereg(LCD_REG_33, 0x013f); /* GRAM Vertical Address */ - - /* Adjust the Gamma Curve (SPFD5408B) */ - - stm3210e_writereg(LCD_REG_48, 0x0b0d); - stm3210e_writereg(LCD_REG_49, 0x1923); - stm3210e_writereg(LCD_REG_50, 0x1c26); - stm3210e_writereg(LCD_REG_51, 0x261c); - stm3210e_writereg(LCD_REG_52, 0x2419); - stm3210e_writereg(LCD_REG_53, 0x0d0b); - stm3210e_writereg(LCD_REG_54, 0x1006); - stm3210e_writereg(LCD_REG_55, 0x0610); - stm3210e_writereg(LCD_REG_56, 0x0706); - stm3210e_writereg(LCD_REG_57, 0x0304); - stm3210e_writereg(LCD_REG_58, 0x0e05); - stm3210e_writereg(LCD_REG_59, 0x0e01); - stm3210e_writereg(LCD_REG_60, 0x010e); - stm3210e_writereg(LCD_REG_61, 0x050e); - stm3210e_writereg(LCD_REG_62, 0x0403); - stm3210e_writereg(LCD_REG_63, 0x0607); - - /* Set GRAM area */ - - stm3210e_writereg(LCD_REG_80, 0x0000); /* Horizontal GRAM Start Address */ - stm3210e_writereg(LCD_REG_81, 0x00ef); /* Horizontal GRAM End Address */ - stm3210e_writereg(LCD_REG_82, 0x0000); /* Vertical GRAM Start Address */ - stm3210e_writereg(LCD_REG_83, 0x013f); /* Vertical GRAM End Address */ - stm3210e_writereg(LCD_REG_96, 0xa700); /* Gate Scan Line */ - stm3210e_writereg(LCD_REG_97, 0x0001); /* NDL, VLE, REV */ - stm3210e_writereg(LCD_REG_106, 0x0000); /* set scrolling line */ - - /* Partial Display Control */ - - stm3210e_writereg(LCD_REG_128, 0x0000); - stm3210e_writereg(LCD_REG_129, 0x0000); - stm3210e_writereg(LCD_REG_130, 0x0000); - stm3210e_writereg(LCD_REG_131, 0x0000); - stm3210e_writereg(LCD_REG_132, 0x0000); - stm3210e_writereg(LCD_REG_133, 0x0000); - - /* Panel Control */ - - stm3210e_writereg(LCD_REG_144, 0x0010); - stm3210e_writereg(LCD_REG_146, 0x0000); - stm3210e_writereg(LCD_REG_147, 0x0003); - stm3210e_writereg(LCD_REG_149, 0x0110); - stm3210e_writereg(LCD_REG_151, 0x0000); - stm3210e_writereg(LCD_REG_152, 0x0000); - - /* Set GRAM write direction and BGR=1 - * I/D=01 (Horizontal : increment, Vertical : decrement) - * AM=1 (address is updated in vertical writing direction) - */ - - stm3210e_writereg(LCD_REG_3, 0x1018); - stm3210e_writereg(LCD_REG_7, 0); /* Display OFF */ - } - else -#endif - - /* Check if the ID is for the almost compatible R61580 */ - -#if !defined(CONFIG_STM3210E_R61580_DISABLE) - if (id == R61580_ID) - { - /* Set the LCD type for the R61580 */ - - g_lcddev.type = LCD_TYPE_R61580; - lcdinfo("LCD type: %d\n", g_lcddev.type); - - /* Start Initial Sequence */ - - stm3210e_writereg(LCD_REG_0, 0x0000); - stm3210e_writereg(LCD_REG_0, 0x0000); - up_mdelay(100); - stm3210e_writereg(LCD_REG_0, 0x0000); - stm3210e_writereg(LCD_REG_0, 0x0000); - stm3210e_writereg(LCD_REG_0, 0x0000); - stm3210e_writereg(LCD_REG_0, 0x0000); - stm3210e_writereg(LCD_REG_164, 0x0001); - up_mdelay(100); - stm3210e_writereg(LCD_REG_96, 0xa700); - stm3210e_writereg(LCD_REG_8, 0x0808); - - /* Gamma Setting */ - - stm3210e_writereg(LCD_REG_48, 0x0203); - stm3210e_writereg(LCD_REG_49, 0x080f); - stm3210e_writereg(LCD_REG_50, 0x0401); - stm3210e_writereg(LCD_REG_51, 0x050b); - stm3210e_writereg(LCD_REG_52, 0x3330); - stm3210e_writereg(LCD_REG_53, 0x0b05); - stm3210e_writereg(LCD_REG_54, 0x0005); - stm3210e_writereg(LCD_REG_55, 0x0f08); - stm3210e_writereg(LCD_REG_56, 0x0302); - stm3210e_writereg(LCD_REG_57, 0x3033); - - /* Power Setting */ - - stm3210e_writereg(LCD_REG_144, 0x0018); /* 80Hz */ - stm3210e_writereg(LCD_REG_16, 0x0530); /* BT, AP */ - stm3210e_writereg(LCD_REG_17, 0x0237); /* DC1,DC0,VC */ - stm3210e_writereg(LCD_REG_18, 0x01bf); - stm3210e_writereg(LCD_REG_19, 0x1000); /* VCOM */ - up_mdelay(200); - - stm3210e_writereg(LCD_REG_1, 0x0100); /* Set SS bit */ - stm3210e_writereg(LCD_REG_2, 0x0200); - stm3210e_writereg(LCD_REG_3, 0x1030); /* Set GRAM write direction and BGR=1. */ - stm3210e_writereg(LCD_REG_9, 0x0001); - stm3210e_writereg(LCD_REG_10, 0x0008); - stm3210e_writereg(LCD_REG_12, 0x0000); /* RGB 18-bit System interface setting */ - stm3210e_writereg(LCD_REG_13, 0xd000); - stm3210e_writereg(LCD_REG_14, 0x0030); - stm3210e_writereg(LCD_REG_15, 0x0000); /* RGB interface polarity, no impact */ - stm3210e_writereg(LCD_REG_32, 0x0000); /* H Start */ - stm3210e_writereg(LCD_REG_33, 0x0000); /* V Start */ - stm3210e_writereg(LCD_REG_41, 0x002e); - stm3210e_writereg(LCD_REG_80, 0x0000); /* Horizontal GRAM Start Address */ - stm3210e_writereg(LCD_REG_81, 0x00ef); /* Horizontal GRAM End Address */ - stm3210e_writereg(LCD_REG_82, 0x0000); /* Vertical GRAM Start Address */ - stm3210e_writereg(LCD_REG_83, 0x013f); /* Vertical GRAM End Address */ - stm3210e_writereg(LCD_REG_97, 0x0001); /* NDL, VLE, REV */ - stm3210e_writereg(LCD_REG_106, 0x0000); /* set scrolling line */ - stm3210e_writereg(LCD_REG_128, 0x0000); - stm3210e_writereg(LCD_REG_129, 0x0000); - stm3210e_writereg(LCD_REG_130, 0x005f); - stm3210e_writereg(LCD_REG_147, 0x0701); - - stm3210e_writereg(LCD_REG_7, 0x0000); /* Display OFF */ - } - else -#endif - { -#ifndef CONFIG_STM3210E_AM240320_DISABLE - /* Set the LCD type for the AM240320 */ - - g_lcddev.type = LCD_TYPE_AM240320; - lcdinfo("LCD type: %d\n", g_lcddev.type); - - /* Start Initial Sequence */ - - stm3210e_writereg(LCD_REG_229, 0x8000); /* Set the internal vcore voltage */ - stm3210e_writereg(LCD_REG_0, 0x0001); /* Start internal OSC. */ - stm3210e_writereg(LCD_REG_1, 0x0100); /* Set SS and SM bit */ - stm3210e_writereg(LCD_REG_2, 0x0700); /* Set 1 line inversion */ - stm3210e_writereg(LCD_REG_3, 0x1030); /* Set GRAM write direction and BGR=1. */ - stm3210e_writereg(LCD_REG_4, 0x0000); /* Resize register */ - stm3210e_writereg(LCD_REG_8, 0x0202); /* Set the back porch and front porch */ - stm3210e_writereg(LCD_REG_9, 0x0000); /* Set non-display area refresh cycle ISC[3:0] */ - stm3210e_writereg(LCD_REG_10, 0x0000); /* FMARK function */ - stm3210e_writereg(LCD_REG_12, 0x0000); /* RGB interface setting */ - stm3210e_writereg(LCD_REG_13, 0x0000); /* Frame marker Position */ - stm3210e_writereg(LCD_REG_15, 0x0000); /* RGB interface polarity */ - - /* Power On sequence */ - - stm3210e_writereg(LCD_REG_16, 0x0000); /* SAP, BT[3:0], AP, DSTB, SLP, STB */ - stm3210e_writereg(LCD_REG_17, 0x0000); /* DC1[2:0], DC0[2:0], VC[2:0] */ - stm3210e_writereg(LCD_REG_18, 0x0000); /* VREG1OUT voltage */ - stm3210e_writereg(LCD_REG_19, 0x0000); /* VDV[4:0] for VCOM amplitude */ - up_mdelay(200); /* Dis-charge capacitor power voltage (200ms) */ - - stm3210e_writereg(LCD_REG_16, 0x17b0); /* SAP, BT[3:0], AP, DSTB, SLP, STB */ - stm3210e_writereg(LCD_REG_17, 0x0137); /* DC1[2:0], DC0[2:0], VC[2:0] */ - up_mdelay(50); - - stm3210e_writereg(LCD_REG_18, 0x0139); /* VREG1OUT voltage */ - up_mdelay(50); - - stm3210e_writereg(LCD_REG_19, 0x1d00); /* VDV[4:0] for VCOM amplitude */ - stm3210e_writereg(LCD_REG_41, 0x0013); /* VCM[4:0] for VCOMH */ - up_mdelay(50); - - stm3210e_writereg(LCD_REG_32, 0x0000); /* GRAM horizontal Address */ - stm3210e_writereg(LCD_REG_33, 0x0000); /* GRAM Vertical Address */ - - /* Adjust the Gamma Curve */ - - stm3210e_writereg(LCD_REG_48, 0x0006); - stm3210e_writereg(LCD_REG_49, 0x0101); - stm3210e_writereg(LCD_REG_50, 0x0003); - stm3210e_writereg(LCD_REG_53, 0x0106); - stm3210e_writereg(LCD_REG_54, 0x0b02); - stm3210e_writereg(LCD_REG_55, 0x0302); - stm3210e_writereg(LCD_REG_56, 0x0707); - stm3210e_writereg(LCD_REG_57, 0x0007); - stm3210e_writereg(LCD_REG_60, 0x0600); - stm3210e_writereg(LCD_REG_61, 0x020b); - - /* Set GRAM area */ - - stm3210e_writereg(LCD_REG_80, 0x0000); /* Horizontal GRAM Start Address */ - stm3210e_writereg(LCD_REG_81, 0x00ef); /* Horizontal GRAM End Address */ - stm3210e_writereg(LCD_REG_82, 0x0000); /* Vertical GRAM Start Address */ - stm3210e_writereg(LCD_REG_83, 0x013f); /* Vertical GRAM End Address */ - stm3210e_writereg(LCD_REG_96, 0x2700); /* Gate Scan Line */ - stm3210e_writereg(LCD_REG_97, 0x0001); /* NDL,VLE, REV */ - stm3210e_writereg(LCD_REG_106, 0x0000); /* Set scrolling line */ - - /* Partial Display Control */ - - stm3210e_writereg(LCD_REG_128, 0x0000); - stm3210e_writereg(LCD_REG_129, 0x0000); - stm3210e_writereg(LCD_REG_130, 0x0000); - stm3210e_writereg(LCD_REG_131, 0x0000); - stm3210e_writereg(LCD_REG_132, 0x0000); - stm3210e_writereg(LCD_REG_133, 0x0000); - - /* Panel Control */ - - stm3210e_writereg(LCD_REG_144, 0x0010); - stm3210e_writereg(LCD_REG_146, 0x0000); - stm3210e_writereg(LCD_REG_147, 0x0003); - stm3210e_writereg(LCD_REG_149, 0x0110); - stm3210e_writereg(LCD_REG_151, 0x0000); - stm3210e_writereg(LCD_REG_152, 0x0000); - - /* Set GRAM write direction and BGR = 1 - * - * I/D=01 (Horizontal : increment, Vertical : decrement) - * AM=1 (address is updated in vertical writing direction) - */ - - stm3210e_writereg(LCD_REG_3, 0x1018); - stm3210e_writereg(LCD_REG_7, 0); /* Display off */ -#else - lcderr("ERROR: Unsupported LCD type\n"); -#endif - } -} - -/**************************************************************************** - * Name: stm3210e_backlight - * - * Description: - * The LCD backlight is driven from PA8 which must be configured as TIM1 - * CH1. TIM1 must then be configured to output a clock on PA8; the duty - * of the clock determineds the backlight level. - * - ****************************************************************************/ - -#ifdef CONFIG_STM3210E_LCD_BACKLIGHT -static void stm3210e_backlight(void) -{ -#ifdef CONFIG_STM3210E_LCD_PWM - uint32_t prescaler; - uint32_t reload; - uint32_t timclk; - uint16_t bdtr; - uint16_t ccmr; - uint16_t ccer; - uint16_t cr2; - - /* Calculate the TIM1 prescaler value */ - - prescaler = (STM32_PCLK2_FREQUENCY / CONFIG_STM3210E_LCD_PWMFREQUENCY + - 65534) / 65535; - if (prescaler < 1) - { - prescaler = 1; - } - else if (prescaler > 65536) - { - prescaler = 65536; - } - - /* Calculate the TIM1 reload value */ - - timclk = STM32_PCLK2_FREQUENCY / prescaler; - reload = timclk / CONFIG_STM3210E_LCD_PWMFREQUENCY; - - if (reload < 1) - { - reload = 1; - } - else if (reload > 65535) - { - reload = 65535; - } - - g_lcddev.reload = reload; - - /* Configure PA8 as TIM1 CH1 output */ - - stm32_configgpio(GPIO_TIM1_CH1OUT); - - /* Enabled timer 1 clocking */ - - modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM1EN); - - /* Reset timer 1 */ - - modifyreg32(STM32_RCC_APB2RSTR, 0, RCC_APB2RSTR_TIM1RST); - modifyreg32(STM32_RCC_APB2RSTR, RCC_APB2RSTR_TIM1RST, 0); - - /* Reset the Counter Mode and set the clock division */ - - putreg16(0, STM32_TIM1_CR1); - - /* Set the Autoreload value */ - - putreg16(reload - 1, STM32_TIM1_ARR); - - /* Set the Prescaler value */ - - putreg16(prescaler - 1, STM32_TIM1_PSC); - - /* Generate an update event to reload the Prescaler value immediately */ - - putreg16(ATIM_EGR_UG, STM32_TIM1_EGR); - - /* Reset the Repetition Counter value */ - - putreg16(0, STM32_TIM1_RCR); - - /* Set the main output enable (MOE) bit and clear the OSSI and OSSR - * bits in the BDTR register. - */ - - bdtr = getreg16(STM32_TIM1_BDTR); - bdtr &= ~(ATIM_BDTR_OSSI | ATIM_BDTR_OSSR); - bdtr |= ATIM_BDTR_MOE; - putreg16(bdtr, STM32_TIM1_BDTR); - - /* Disable the Channel 1 */ - - ccer = getreg16(STM32_TIM1_CCER); - ccer &= ~ATIM_CCER_CC1E; - putreg16(ccer, STM32_TIM1_CCER); - - /* Get the TIM1 CR2 register value */ - - cr2 = getreg16(STM32_TIM1_CR2); - - /* Select the Output Compare Mode Bits */ - - ccmr = getreg16(STM32_TIM1_CCMR1); - ccmr &= ATIM_CCMR1_OC1M_MASK; - ccmr |= (ATIM_CCMR_MODE_PWM1 << ATIM_CCMR1_OC1M_SHIFT); - ccmr |= (ATIM_CCMR_CCS_CCOUT << ATIM_CCMR1_CC1S_SHIFT); - - /* Set the power to the minimum value */ - - g_lcddev.power = 0; - putreg16(0, STM32_TIM1_CCR1); - - /* Select the output polarity level == LOW and enable */ - - ccer |= (ATIM_CCER_CC1E); - - /* Reset the Output N Polarity level */ - - ccer &= ~(ATIM_CCER_CC1NP | ATIM_CCER_CC1NE); - - /* Reset the Output Compare and Output Compare N IDLE State */ - - cr2 &= ~(ATIM_CR2_OIS1 | ATIM_CR2_OIS1N); - - /* Write the timer configuration */ - - putreg16(cr2, STM32_TIM1_CR2); - putreg16(ccmr, STM32_TIM1_CCMR1); - putreg16(ccer, STM32_TIM1_CCER); - - /* Set the auto preload enable bit */ - - modifyreg16(STM32_TIM1_CR1, 0, ATIM_CR1_ARPE); - - /* Enable Backlight Timer */ - - ccer |= ATIM_CR1_CEN; - putreg16(ccer, STM32_TIM1_CR1); - - /* Dump timer1 registers */ - - lcdinfo("APB2ENR: %08" PRIx32 "\n", getreg32(STM32_RCC_APB2ENR)); - lcdinfo("CR1: %04" PRIx32 "\n", getreg32(STM32_TIM1_CR1)); - lcdinfo("CR2: %04" PRIx32 "\n", getreg32(STM32_TIM1_CR2)); - lcdinfo("SMCR: %04" PRIx32 "\n", getreg32(STM32_TIM1_SMCR)); - lcdinfo("DIER: %04" PRIx32 "\n", getreg32(STM32_TIM1_DIER)); - lcdinfo("SR: %04" PRIx32 "\n", getreg32(STM32_TIM1_SR)); - lcdinfo("BDTR: %04" PRIx32 "\n", getreg32(STM32_TIM1_BDTR)); - lcdinfo("CCMR1: %04" PRIx32 "\n", getreg32(STM32_TIM1_CCMR1)); - lcdinfo("CCMR2: %04" PRIx32 "\n", getreg32(STM32_TIM1_CCMR2)); - lcdinfo("CCER: %04" PRIx32 "\n", getreg32(STM32_TIM1_CCER)); - lcdinfo("CNT: %04" PRIx32 "\n", getreg32(STM32_TIM1_CNT)); - lcdinfo("PSC: %04" PRIx32 "\n", getreg32(STM32_TIM1_PSC)); - lcdinfo("ARR: %04" PRIx32 "\n", getreg32(STM32_TIM1_ARR)); - lcdinfo("RCR: %04" PRIx32 "\n", getreg32(STM32_TIM1_RCR)); - lcdinfo("CCR1: %04" PRIx32 "\n", getreg32(STM32_TIM1_CCR1)); - lcdinfo("CCR2: %04" PRIx32 "\n", getreg32(STM32_TIM1_CCR2)); - lcdinfo("CCR3: %04" PRIx32 "\n", getreg32(STM32_TIM1_CCR3)); - lcdinfo("CCR4: %04" PRIx32 "\n", getreg32(STM32_TIM1_CCR4)); - lcdinfo("DMAR: %04" PRIx32 "\n", getreg32(STM32_TIM1_DMAR)); -#endif -} -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_lcd_initialize - * - * Description: - * Initialize the LCD video hardware. The initial state of the LCD is - * fully initialized, display memory cleared, and the LCD ready to use, - * but with the power setting at 0 (full off). - * - ****************************************************************************/ - -int board_lcd_initialize(void) -{ -#ifdef CONFIG_PM - int ret; -#endif - - ginfo("Initializing\n"); - - /* Register to receive power management callbacks */ - -#ifdef CONFIG_PM - ret = pm_register(&g_lcdcb); - if (ret != OK) - { - lcderr("ERROR: pm_register failed: %d\n", ret); - } -#endif - - /* Configure GPIO pins and configure the FSMC to support the LCD */ - - stm32_selectlcd(); - - /* Configure and enable LCD */ - - up_mdelay(50); - stm3210e_lcdinitialize(); - - /* Clear the display (setting it to the color 0=black) */ - - stm3210e_lcdclear(0); - - /* Turn the backlight off */ - - stm3210e_poweroff(); - return OK; -} - -/**************************************************************************** - * Name: board_lcd_getdev - * - * Description: - * Return a a reference to the LCD object for the specified LCD. This - * allows support for multiple LCD devices. - * - ****************************************************************************/ - -struct lcd_dev_s *board_lcd_getdev(int lcddev) -{ - DEBUGASSERT(lcddev == 0); - return &g_lcddev.dev; -} - -/**************************************************************************** - * Name: board_lcd_uninitialize - * - * Description: - * Uninitialize the LCD support - * - ****************************************************************************/ - -void board_lcd_uninitialize(void) -{ - stm3210e_poweroff(); - stm32_deselectlcd(); -} - -/**************************************************************************** - * Name: stm3210e_lcdclear - * - * Description: - * This is a non-standard LCD interface just for the STM3210E-EVAL board. - * Because of the various rotations, clearing the display in the normal - * way by writing a sequences of runs that covers the entire display can - * be very slow. Here the display is cleared by simply setting all GRAM - * memory to the specified color. - * - ****************************************************************************/ - -void stm3210e_lcdclear(uint16_t color) -{ - uint32_t i = 0; - - stm3210e_setcursor(0, STM3210E_XRES - 1); - stm3210e_gramselect(); - for (i = 0; i < STM3210E_XRES * STM3210E_YRES; i++) - { - LCD->value = color; - } -} diff --git a/boards/arm/stm32/stm3210e-eval/src/stm32_leds.c b/boards/arm/stm32/stm3210e-eval/src/stm32_leds.c deleted file mode 100644 index 56d005a627cd3..0000000000000 --- a/boards/arm/stm32/stm3210e-eval/src/stm32_leds.c +++ /dev/null @@ -1,372 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm3210e-eval/src/stm32_leds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32.h" -#include "stm3210e-eval.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* The following definitions map the encoded LED setting to GPIO settings */ - -#define STM3210E_LED1 (1 << 0) -#define STM3210E_LED2 (1 << 1) -#define STM3210E_LED3 (1 << 2) -#define STM3210E_LED4 (1 << 3) - -#define ON_SETBITS_SHIFT (0) -#define ON_CLRBITS_SHIFT (4) -#define OFF_SETBITS_SHIFT (8) -#define OFF_CLRBITS_SHIFT (12) - -#define ON_BITS(v) ((v) & 0xff) -#define OFF_BITS(v) (((v) >> 8) & 0x0ff) -#define SETBITS(b) ((b) & 0x0f) -#define CLRBITS(b) (((b) >> 4) & 0x0f) - -#define ON_SETBITS(v) (SETBITS(ON_BITS(v)) -#define ON_CLRBITS(v) (CLRBITS(ON_BITS(v)) -#define OFF_SETBITS(v) (SETBITS(OFF_BITS(v)) -#define OFF_CLRBITS(v) (CLRBITS(OFF_BITS(v)) - -#define LED_STARTED_ON_SETBITS ((STM3210E_LED1) << ON_SETBITS_SHIFT) -#define LED_STARTED_ON_CLRBITS ((STM3210E_LED2|STM3210E_LED3|STM3210E_LED4) << ON_CLRBITS_SHIFT) -#define LED_STARTED_OFF_SETBITS (0 << OFF_SETBITS_SHIFT) -#define LED_STARTED_OFF_CLRBITS ((STM3210E_LED1|STM3210E_LED2|STM3210E_LED3|STM3210E_LED4) << OFF_CLRBITS_SHIFT) - -#define LED_HEAPALLOCATE_ON_SETBITS ((STM3210E_LED2) << ON_SETBITS_SHIFT) -#define LED_HEAPALLOCATE_ON_CLRBITS ((STM3210E_LED1|STM3210E_LED3|STM3210E_LED4) << ON_CLRBITS_SHIFT) -#define LED_HEAPALLOCATE_OFF_SETBITS ((STM3210E_LED1) << OFF_SETBITS_SHIFT) -#define LED_HEAPALLOCATE_OFF_CLRBITS ((STM3210E_LED2|STM3210E_LED3|STM3210E_LED4) << OFF_CLRBITS_SHIFT) - -#define LED_IRQSENABLED_ON_SETBITS ((STM3210E_LED1|STM3210E_LED2) << ON_SETBITS_SHIFT) -#define LED_IRQSENABLED_ON_CLRBITS ((STM3210E_LED3|STM3210E_LED4) << ON_CLRBITS_SHIFT) -#define LED_IRQSENABLED_OFF_SETBITS ((STM3210E_LED2) << OFF_SETBITS_SHIFT) -#define LED_IRQSENABLED_OFF_CLRBITS ((STM3210E_LED1|STM3210E_LED3|STM3210E_LED4) << OFF_CLRBITS_SHIFT) - -#define LED_STACKCREATED_ON_SETBITS ((STM3210E_LED3) << ON_SETBITS_SHIFT) -#define LED_STACKCREATED_ON_CLRBITS ((STM3210E_LED1|STM3210E_LED2|STM3210E_LED4) << ON_CLRBITS_SHIFT) -#define LED_STACKCREATED_OFF_SETBITS ((STM3210E_LED1|STM3210E_LED2) << OFF_SETBITS_SHIFT) -#define LED_STACKCREATED_OFF_CLRBITS ((STM3210E_LED3|STM3210E_LED4) << OFF_CLRBITS_SHIFT) - -#define LED_INIRQ_ON_SETBITS ((STM3210E_LED1) << ON_SETBITS_SHIFT) -#define LED_INIRQ_ON_CLRBITS ((0) << ON_CLRBITS_SHIFT) -#define LED_INIRQ_OFF_SETBITS ((0) << OFF_SETBITS_SHIFT) -#define LED_INIRQ_OFF_CLRBITS ((STM3210E_LED1) << OFF_CLRBITS_SHIFT) - -#define LED_SIGNAL_ON_SETBITS ((STM3210E_LED2) << ON_SETBITS_SHIFT) -#define LED_SIGNAL_ON_CLRBITS ((0) << ON_CLRBITS_SHIFT) -#define LED_SIGNAL_OFF_SETBITS ((0) << OFF_SETBITS_SHIFT) -#define LED_SIGNAL_OFF_CLRBITS ((STM3210E_LED2) << OFF_CLRBITS_SHIFT) - -#define LED_ASSERTION_ON_SETBITS ((STM3210E_LED4) << ON_SETBITS_SHIFT) -#define LED_ASSERTION_ON_CLRBITS ((0) << ON_CLRBITS_SHIFT) -#define LED_ASSERTION_OFF_SETBITS ((0) << OFF_SETBITS_SHIFT) -#define LED_ASSERTION_OFF_CLRBITS ((STM3210E_LED4) << OFF_CLRBITS_SHIFT) - -#define LED_PANIC_ON_SETBITS ((STM3210E_LED4) << ON_SETBITS_SHIFT) -#define LED_PANIC_ON_CLRBITS ((0) << ON_CLRBITS_SHIFT) -#define LED_PANIC_OFF_SETBITS ((0) << OFF_SETBITS_SHIFT) -#define LED_PANIC_OFF_CLRBITS ((STM3210E_LED4) << OFF_CLRBITS_SHIFT) - -/**************************************************************************** - * Private Function Protototypes - ****************************************************************************/ - -/* LED State Controls */ - -static inline void led_clrbits(unsigned int clrbits); -static inline void led_setbits(unsigned int setbits); -static void led_setonoff(unsigned int bits); - -/* LED Power Management */ - -#ifdef CONFIG_PM -static void led_pm_notify(struct pm_callback_s *cb, int domain, - enum pm_state_e pmstate); -static int led_pm_prepare(struct pm_callback_s *cb, int domain, - enum pm_state_e pmstate); -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -static const uint16_t g_ledbits[8] = -{ - (LED_STARTED_ON_SETBITS | LED_STARTED_ON_CLRBITS | - LED_STARTED_OFF_SETBITS | LED_STARTED_OFF_CLRBITS), - - (LED_HEAPALLOCATE_ON_SETBITS | LED_HEAPALLOCATE_ON_CLRBITS | - LED_HEAPALLOCATE_OFF_SETBITS | LED_HEAPALLOCATE_OFF_CLRBITS), - - (LED_IRQSENABLED_ON_SETBITS | LED_IRQSENABLED_ON_CLRBITS | - LED_IRQSENABLED_OFF_SETBITS | LED_IRQSENABLED_OFF_CLRBITS), - - (LED_STACKCREATED_ON_SETBITS | LED_STACKCREATED_ON_CLRBITS | - LED_STACKCREATED_OFF_SETBITS | LED_STACKCREATED_OFF_CLRBITS), - - (LED_INIRQ_ON_SETBITS | LED_INIRQ_ON_CLRBITS | - LED_INIRQ_OFF_SETBITS | LED_INIRQ_OFF_CLRBITS), - - (LED_SIGNAL_ON_SETBITS | LED_SIGNAL_ON_CLRBITS | - LED_SIGNAL_OFF_SETBITS | LED_SIGNAL_OFF_CLRBITS), - - (LED_ASSERTION_ON_SETBITS | LED_ASSERTION_ON_CLRBITS | - LED_ASSERTION_OFF_SETBITS | LED_ASSERTION_OFF_CLRBITS), - - (LED_PANIC_ON_SETBITS | LED_PANIC_ON_CLRBITS | - LED_PANIC_OFF_SETBITS | LED_PANIC_OFF_CLRBITS) -}; - -#ifdef CONFIG_PM -static struct pm_callback_s g_ledscb = -{ - .notify = led_pm_notify, - .prepare = led_pm_prepare, -}; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: led_clrbits - * - * Description: - * Clear all LEDs to the bit encoded state - * - ****************************************************************************/ - -static inline void led_clrbits(unsigned int clrbits) -{ - if ((clrbits & STM3210E_LED1) != 0) - { - stm32_gpiowrite(GPIO_LED1, false); - } - - if ((clrbits & STM3210E_LED2) != 0) - { - stm32_gpiowrite(GPIO_LED2, false); - } - - if ((clrbits & STM3210E_LED3) != 0) - { - stm32_gpiowrite(GPIO_LED3, false); - } - - if ((clrbits & STM3210E_LED4) != 0) - { - stm32_gpiowrite(GPIO_LED4, false); - } -} - -/**************************************************************************** - * Name: led_setbits - * - * Description: - * Set all LEDs to the bit encoded state - * - ****************************************************************************/ - -static inline void led_setbits(unsigned int setbits) -{ - if ((setbits & STM3210E_LED1) != 0) - { - stm32_gpiowrite(GPIO_LED1, true); - } - - if ((setbits & STM3210E_LED2) != 0) - { - stm32_gpiowrite(GPIO_LED2, true); - } - - if ((setbits & STM3210E_LED3) != 0) - { - stm32_gpiowrite(GPIO_LED3, true); - } - - if ((setbits & STM3210E_LED4) != 0) - { - stm32_gpiowrite(GPIO_LED4, true); - } -} - -/**************************************************************************** - * Name: led_setonoff - * - * Description: - * Set/clear all LEDs to the bit encoded state - * - ****************************************************************************/ - -static void led_setonoff(unsigned int bits) -{ - led_clrbits(CLRBITS(bits)); - led_setbits(SETBITS(bits)); -} - -/**************************************************************************** - * Name: led_pm_notify - * - * Description: - * Notify the driver of new power state. This callback is called after - * all drivers have had the opportunity to prepare for the new power state. - * - ****************************************************************************/ - -#ifdef CONFIG_PM -static void led_pm_notify(struct pm_callback_s *cb, int domain, - enum pm_state_e pmstate) -{ - switch (pmstate) - { - case PM_NORMAL: - { - /* Restore normal LEDs operation */ - } - break; - - case PM_IDLE: - { - /* Entering IDLE mode - Turn leds off */ - } - break; - - case PM_STANDBY: - { - /* Entering STANDBY mode - Logic for PM_STANDBY goes here */ - } - break; - - case PM_SLEEP: - { - /* Entering SLEEP mode - Logic for PM_SLEEP goes here */ - } - break; - - default: - { - /* Should not get here */ - } - break; - } -} -#endif - -/**************************************************************************** - * Name: led_pm_prepare - * - * Description: - * Request the driver to prepare for a new power state. This is a warning - * that the system is about to enter into a new power state. The driver - * should begin whatever operations that may be required to enter power - * state. The driver may abort the state change mode by returning a - * non-zero value from the callback function. - * - ****************************************************************************/ - -#ifdef CONFIG_PM -static int led_pm_prepare(struct pm_callback_s *cb, int domain, - enum pm_state_e pmstate) -{ - /* No preparation to change power modes is required by the LEDs driver. - * We always accept the state change by returning OK. - */ - - return OK; -} -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_autoled_initialize - ****************************************************************************/ - -#ifdef CONFIG_ARCH_LEDS -void board_autoled_initialize(void) -{ - /* Configure LED1-4 GPIOs for output */ - - stm32_configgpio(GPIO_LED1); - stm32_configgpio(GPIO_LED2); - stm32_configgpio(GPIO_LED3); - stm32_configgpio(GPIO_LED4); -} - -/**************************************************************************** - * Name: board_autoled_on - ****************************************************************************/ - -void board_autoled_on(int led) -{ - led_setonoff(ON_BITS(g_ledbits[led])); -} - -/**************************************************************************** - * Name: board_autoled_off - ****************************************************************************/ - -void board_autoled_off(int led) -{ - led_setonoff(OFF_BITS(g_ledbits[led])); -} - -/**************************************************************************** - * Name: stm32_ledpminitialize - ****************************************************************************/ - -#ifdef CONFIG_PM -void stm32_ledpminitialize(void) -{ - /* Register to receive power management callbacks */ - - int ret = pm_register(&g_ledscb); - if (ret != OK) - { - board_autoled_on(LED_ASSERTION); - } -} -#endif /* CONFIG_PM */ - -#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/stm3210e-eval/src/stm32_pm.c b/boards/arm/stm32/stm3210e-eval/src/stm32_pm.c deleted file mode 100644 index 867ea413b5c35..0000000000000 --- a/boards/arm/stm32/stm3210e-eval/src/stm32_pm.c +++ /dev/null @@ -1,75 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm3210e-eval/src/stm32_pm.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include - -#include "arm_internal.h" -#include "stm32_pm.h" -#include "stm3210e-eval.h" - -#ifdef CONFIG_PM - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: arm_pminitialize - * - * Description: - * This function is called by MCU-specific logic at power-on reset in - * order to provide one-time initialization the power management subsystem. - * This function must be called *very* early in the initialization sequence - * *before* any other device drivers are initialized (since they may - * attempt to register with the power management subsystem). - * - * Input Parameters: - * None. - * - * Returned Value: - * None. - * - ****************************************************************************/ - -void arm_pminitialize(void) -{ - /* Initialize the NuttX power management subsystem proper */ - - pm_initialize(); - -#if defined(CONFIG_ARCH_IDLE_CUSTOM) && defined(CONFIG_PM_BUTTONS) - /* Initialize the buttons to wake up the system from low power modes */ - - stm32_pmbuttons(); -#endif - - /* Initialize the LED PM */ - - stm32_ledpminitialize(); -} - -#endif /* CONFIG_PM */ diff --git a/boards/arm/stm32/stm3210e-eval/src/stm32_pmbuttons.c b/boards/arm/stm32/stm3210e-eval/src/stm32_pmbuttons.c deleted file mode 100644 index 20fd76a4af25f..0000000000000 --- a/boards/arm/stm32/stm3210e-eval/src/stm32_pmbuttons.c +++ /dev/null @@ -1,181 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm3210e-eval/src/stm32_pmbuttons.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include - -#include -#include -#include - -#include -#include -#include - -#include "arm_internal.h" -#include "nvic.h" -#include "stm32_pwr.h" -#include "stm32_pm.h" -#include "stm3210e-eval.h" - -#if defined(CONFIG_PM) && defined(CONFIG_ARCH_IDLE_CUSTOM) && defined(CONFIG_PM_BUTTONS) - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -#ifndef CONFIG_ARCH_BUTTONS -# error "CONFIG_ARCH_BUTTONS is not defined in the configuration" -#endif - -#define BUTTON_MIN 0 -#ifdef CONFIG_INPUT_DJOYSTICK -# define BUTTON_MAX 2 -#else -# define BUTTON_MAX 7 -#endif - -#ifndef CONFIG_PM_BUTTONS_MIN -# define CONFIG_PM_BUTTONS_MIN BUTTON_MIN -#endif -#ifndef CONFIG_PM_BUTTONS_MAX -# define CONFIG_PM_BUTTONS_MAX BUTTON_MAX -#endif - -#if CONFIG_PM_BUTTONS_MIN > CONFIG_PM_BUTTONS_MAX -# error "CONFIG_PM_BUTTONS_MIN > CONFIG_PM_BUTTONS_MAX" -#endif - -#if CONFIG_PM_BUTTONS_MAX > BUTTON_MAX -# error "CONFIG_PM_BUTTONS_MAX > BUTTON_MAX" -#endif - -#ifndef CONFIG_ARCH_IRQBUTTONS -# warning "CONFIG_ARCH_IRQBUTTONS is not defined in the configuration" -#endif - -#ifndef CONFIG_PM_IRQBUTTONS_MIN -# define CONFIG_PM_IRQBUTTONS_MIN CONFIG_PM_BUTTONS_MIN -#endif - -#ifndef CONFIG_PM_IRQBUTTONS_MAX -# define CONFIG_PM_IRQBUTTONS_MAX CONFIG_PM_BUTTONS_MAX -#endif - -#if CONFIG_PM_IRQBUTTONS_MIN > CONFIG_PM_IRQBUTTONS_MAX -# error "CONFIG_PM_IRQBUTTONS_MIN > CONFIG_PM_IRQBUTTONS_MAX" -#endif - -#if CONFIG_PM_IRQBUTTONS_MAX > 7 -# error "CONFIG_PM_IRQBUTTONS_MAX > 7" -#endif - -#ifndef CONFIG_PM_BUTTON_ACTIVITY -# define CONFIG_PM_BUTTON_ACTIVITY 10 -#endif - -/* Miscellaneous Definitions ************************************************/ - -#define MIN_BUTTON MIN(CONFIG_PM_BUTTONS_MIN, CONFIG_PM_IRQBUTTONS_MIN) -#define MAX_BUTTON MAX(CONFIG_PM_BUTTONS_MAX, CONFIG_PM_IRQBUTTONS_MAX) - -#define NUM_PMBUTTONS (MAX_BUTTON - MIN_BUTTON + 1) -#define BUTTON_INDEX(b) ((b)-MIN_BUTTON) - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -#ifdef CONFIG_ARCH_IRQBUTTONS -/**************************************************************************** - * Name: button_handler - * - * Description: - * Handle a button wake-up interrupt - * - ****************************************************************************/ - -static int button_handler(int irq, void *context, void *arg) -{ - /* At this point the MCU should have already awakened. The state - * change will be handled in the IDLE loop when the system is re-awakened - * The button interrupt handler should be totally ignorant of the PM - * activities and should report button activity as if nothing - * special happened. - */ - - pm_activity(PM_IDLE_DOMAIN, CONFIG_PM_BUTTON_ACTIVITY); - return 0; -} -#endif /* CONFIG_ARCH_IRQBUTTONS */ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_pmbuttons - * - * Description: - * Configure all the buttons of the STM3210e-eval board as EXTI, - * so any button is able to wakeup the MCU from the PM_STANDBY mode - * - ****************************************************************************/ - -void stm32_pmbuttons(void) -{ -#ifdef CONFIG_ARCH_IRQBUTTONS - int ret; - int i; -#endif - - /* Initialize the button GPIOs */ - - board_button_initialize(); - -#ifdef CONFIG_ARCH_IRQBUTTONS - for (i = CONFIG_PM_IRQBUTTONS_MIN; i <= CONFIG_PM_IRQBUTTONS_MAX; i++) - { - ret = board_button_irq(i, button_handler, (void *)i); - if (ret < 0) - { - serr("ERROR: board_button_irq failed: %d\n", ret); - } - } -#endif -} - -#endif /* defined(CONFIG_PM) && defined(CONFIG_ARCH_IDLE_CUSTOM) && defined(CONFIG_PM_BUTTONS) */ diff --git a/boards/arm/stm32/stm3210e-eval/src/stm32_selectlcd.c b/boards/arm/stm32/stm3210e-eval/src/stm32_selectlcd.c deleted file mode 100644 index d128d108edd35..0000000000000 --- a/boards/arm/stm32/stm3210e-eval/src/stm32_selectlcd.c +++ /dev/null @@ -1,134 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm3210e-eval/src/stm32_selectlcd.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32.h" -#include -#include "stm3210e-eval.h" - -#ifdef CONFIG_STM32_FSMC - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#if STM32_NGPIO_PORTS < 6 -# error "Required GPIO ports not enabled" -#endif - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* 512Kx16 SRAM is connected to bank2 of the FSMC interface and both 8- and - * 16-bit accesses are allowed by BLN0 and BLN1 connected to BLE and BHE of - * SRAM, respectively. - * - * Pin Usage (per schematic) - * FLASH SRAM NAND LCD - * D[0..15] [0..15] [0..15] [0..7] [0..15] - * A[0..23] [0..22] [0..18] [16,17] [0] - * FSMC_NBL0 PE0 OUT ~BLE --- --- --- - * FSMC_NBL1 PE1 OUT ~BHE --- --- --- - * FSMC_NE2 PG9 OUT --- ~E --- --- - * FSMC_NE3 PG10 OUT ~CE --- --- --- - * FSMC_NE4 PG12 OUT --- --- --- ~CS - * FSMC_NWE PD5 OUT ~WE ~W ~W ~WR/SCL - * FSMC_NOE PD4 OUT ~OE ~G ~R ~RD - * FSMC_NWAIT PD6 IN --- R~B --- --- - * FSMC_INT2 PG6* IN --- --- R~B --- - * - * *JP7 will switch to PD6 - */ - -/* GPIO configurations unique to the LCD */ - -static const uint16_t g_lcdconfig[] = -{ - /* NE4 */ - - GPIO_NPS_NE4 -}; -#define NLCD_CONFIG (sizeof(g_lcdconfig)/sizeof(uint16_t)) - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_selectlcd - * - * Description: - * Initialize to the LCD - * - ****************************************************************************/ - -void stm32_selectlcd(void) -{ - /* Configure new GPIO state */ - - stm32_extmemgpios(g_commonconfig, NCOMMON_CONFIG); - stm32_extmemgpios(g_lcdconfig, NLCD_CONFIG); - - /* Enable AHB clocking to the FSMC */ - - stm32_fsmc_enable(); - - /* Bank4 NOR/SRAM control register configuration */ - - putreg32(FSMC_BCR_SRAM | FSMC_BCR_MWID16 | - FSMC_BCR_WREN, STM32_FSMC_BCR4); - - /* Bank4 NOR/SRAM timing register configuration */ - - putreg32(FSMC_BTR_ADDSET(1) | FSMC_BTR_ADDHLD(1) | - FSMC_BTR_DATAST(2) | FSMC_BTR_BUSTURN(1) | - FSMC_BTR_CLKDIV(1) | FSMC_BTR_DATLAT(2) | - FSMC_BTR_ACCMODA, STM32_FSMC_BTR4); - - putreg32(0xffffffff, STM32_FSMC_BWTR4); - - /* Enable the bank by setting the MBKEN bit */ - - putreg32(FSMC_BCR_MBKEN | FSMC_BCR_SRAM | - FSMC_BCR_MWID16 | FSMC_BCR_WREN, STM32_FSMC_BCR4); -} - -#endif /* CONFIG_STM32_FSMC */ diff --git a/boards/arm/stm32/stm3210e-eval/src/stm32_selectsram.c b/boards/arm/stm32/stm3210e-eval/src/stm32_selectsram.c deleted file mode 100644 index 3569e423e7c53..0000000000000 --- a/boards/arm/stm32/stm3210e-eval/src/stm32_selectsram.c +++ /dev/null @@ -1,133 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm3210e-eval/src/stm32_selectsram.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32.h" -#include -#include "stm3210e-eval.h" - -#ifdef CONFIG_STM32_FSMC - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#if STM32_NGPIO_PORTS < 6 -# error "Required GPIO ports not enabled" -#endif - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* 512Kx16 SRAM is connected to bank2 of the FSMC interface and both 8- and - * 16-bit accesses are allowed by BLN0 and BLN1 connected to BLE and BHE of - * SRAM, respectively. - * - * Pin Usage (per schematic) - * FLASH SRAM NAND LCD - * D[0..15] [0..15] [0..15] [0..7] [0..15] - * A[0..23] [0..22] [0..18] [16,17] [0] - * FSMC_NBL0 PE0 OUT ~BLE --- --- --- - * FSMC_NBL1 PE1 OUT ~BHE --- --- --- - * FSMC_NE2 PG9 OUT --- ~E --- --- - * FSMC_NE3 PG10 OUT ~CE --- --- --- - * FSMC_NE4 PG12 OUT --- --- --- ~CS - * FSMC_NWE PD5 OUT ~WE ~W ~W ~WR/SCL - * FSMC_NOE PD4 OUT ~OE ~G ~R ~RD - * FSMC_NWAIT PD6 IN --- R~B --- --- - * FSMC_INT2 PG6* IN --- --- R~B --- - * - * *JP7 will switch to PD6 - */ - -/* GPIO configurations unique to SRAM */ - -static const uint16_t g_sramconfig[] = -{ - /* NE3, NBL0, NBL1, */ - - GPIO_NPS_NE3, GPIO_NPS_NBL0, GPIO_NPS_NBL1 -}; -#define NSRAM_CONFIG (sizeof(g_sramconfig)/sizeof(uint16_t)) - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_selectsram - * - * Description: - * Initialize to access external SRAM - * - ****************************************************************************/ - -void stm32_selectsram(void) -{ - /* Configure new GPIO state */ - - stm32_extmemgpios(g_commonconfig, NCOMMON_CONFIG); - stm32_extmemgpios(g_sramconfig, NSRAM_CONFIG); - - /* Enable AHB clocking to the FSMC */ - - stm32_fsmc_enable(); - - /* Bank1 NOR/SRAM control register configuration */ - - putreg32(FSMC_BCR_MWID16 | FSMC_BCR_WREN, STM32_FSMC_BCR3); - - /* Bank1 NOR/SRAM timing register configuration */ - - putreg32(FSMC_BTR_ADDSET(1) | FSMC_BTR_ADDHLD(1) | - FSMC_BTR_DATAST(3) | FSMC_BTR_BUSTURN(1) | - FSMC_BTR_CLKDIV(1) | FSMC_BTR_DATLAT(2) | - FSMC_BTR_ACCMODA, STM32_FSMC_BTR3); - - putreg32(0xffffffff, STM32_FSMC_BWTR3); - - /* Enable the bank */ - - putreg32(FSMC_BCR_MBKEN | FSMC_BCR_MWID16 | - FSMC_BCR_WREN, STM32_FSMC_BCR3); -} - -#endif /* CONFIG_STM32_FSMC */ diff --git a/boards/arm/stm32/stm3210e-eval/src/stm32_spi.c b/boards/arm/stm32/stm3210e-eval/src/stm32_spi.c deleted file mode 100644 index 61a21c6674ab2..0000000000000 --- a/boards/arm/stm32/stm3210e-eval/src/stm32_spi.c +++ /dev/null @@ -1,146 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm3210e-eval/src/stm32_spi.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include "arm_internal.h" -#include "chip.h" -#include "stm32.h" -#include "stm3210e-eval.h" - -#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_spidev_initialize - * - * Description: - * Called to configure SPI chip select GPIO pins for the STM3210E-EVAL - * board. - * - ****************************************************************************/ - -void weak_function stm32_spidev_initialize(void) -{ - /* NOTE: Clocking for SPI1 and/or SPI2 was already provided in stm32_rcc.c. - * Configurations of SPI pins is performed in stm32_spi.c. - * Here, we only initialize chip select pins unique to the board - * architecture. - */ - -#ifdef CONFIG_STM32_SPI1 - /* Configure the SPI-based FLASH CS GPIO */ - - stm32_configgpio(GPIO_FLASH_CS); -#endif -} - -/**************************************************************************** - * Name: stm32_spi1/2/3select and stm32_spi1/2/3status - * - * Description: - * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status - * must be provided by board-specific logic. They are implementations of - * the select and status methods of the SPI interface defined by struct - * spi_ops_s (see include/nuttx/spi/spi.h). All other methods - * (including stm32_spibus_initialize()) are provided by common STM32 logic. - * To use this common SPI logic on your board: - * - * 1. Provide logic in stm32_boardinitialize() to configure SPI chip select - * pins. - * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() functions - * in your board-specific logic. These functions will perform chip - * selection and status operations using GPIOs in the way your board is - * configured. - * 3. Add a calls to stm32_spibus_initialize() in your low level - * application initialization logic - * 4. The handle returned by stm32_spibus_initialize() may then be used to - * bind the SPI driver to higher level logic (e.g., calling - * mmcsd_spislotinitialize(), for example, will bind the SPI driver to - * the SPI MMC/SD driver). - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_SPI1 -void stm32_spi1select(struct spi_dev_s *dev, - uint32_t devid, bool selected) -{ - spiinfo("devid: %d CS: %s\n", - (int)devid, selected ? "assert" : "de-assert"); - - if (devid == SPIDEV_FLASH(0)) - { - /* Set the GPIO low to select and high to de-select */ - - stm32_gpiowrite(GPIO_FLASH_CS, !selected); - } -} - -uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) -{ - return SPI_STATUS_PRESENT; -} -#endif - -#ifdef CONFIG_STM32_SPI2 -void stm32_spi2select(struct spi_dev_s *dev, - uint32_t devid, bool selected) -{ - spiinfo("devid: %d CS: %s\n", - (int)devid, selected ? "assert" : "de-assert"); -} - -uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) -{ - return SPI_STATUS_PRESENT; -} -#endif - -#ifdef CONFIG_STM32_SPI3 -void stm32_spi3select(struct spi_dev_s *dev, - uint32_t devid, bool selected) -{ - spiinfo("devid: %d CS: %s\n", - (int)devid, selected ? "assert" : "de-assert"); -} - -uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid) -{ - return SPI_STATUS_PRESENT; -} -#endif - -#endif /* CONFIG_STM32_SPI1 || CONFIG_STM32_SPI2 */ diff --git a/boards/arm/stm32/stm3210e-eval/src/stm32_usbdev.c b/boards/arm/stm32/stm3210e-eval/src/stm32_usbdev.c deleted file mode 100644 index ba8518ef085f2..0000000000000 --- a/boards/arm/stm32/stm3210e-eval/src/stm32_usbdev.c +++ /dev/null @@ -1,102 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm3210e-eval/src/stm32_usbdev.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include - -#include -#include - -#include "arm_internal.h" -#include "stm32.h" -#include "stm3210e-eval.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_usbinitialize - * - * Description: - * Called to setup USB-related GPIO pins for the STM3210E-EVAL board. - * - ****************************************************************************/ - -void stm32_usbinitialize(void) -{ - /* USB Soft Connect Pullup: PB.14 */ - - stm32_configgpio(GPIO_USB_PULLUP); -} - -/**************************************************************************** - * Name: stm32_usbpullup - * - * Description: - * If USB is supported and the board supports a pullup via GPIO (for USB - * software connect and disconnect), then the board software must provide - * stm32_pullup. - * See include/nuttx/usb/usbdev.h for additional description of this - * method. Alternatively, if no pull-up GPIO the following EXTERN can be - * redefined to be NULL. - * - ****************************************************************************/ - -int stm32_usbpullup(struct usbdev_s *dev, bool enable) -{ - usbtrace(TRACE_DEVPULLUP, (uint16_t)enable); - stm32_gpiowrite(GPIO_USB_PULLUP, !enable); - return OK; -} - -/**************************************************************************** - * Name: stm32_usbsuspend - * - * Description: - * Board logic must provide the stm32_usbsuspend logic if the USBDEV driver - * is used. This function is called whenever the USB enters or leaves - * suspend mode. This is an opportunity for the board logic to shutdown - * clocks, power, etc. while the USB is suspended. - * - ****************************************************************************/ - -void stm32_usbsuspend(struct usbdev_s *dev, bool resume) -{ - uinfo("resume: %d\n", resume); -} diff --git a/boards/arm/stm32/stm3210e-eval/src/stm32_usbmsc.c b/boards/arm/stm32/stm3210e-eval/src/stm32_usbmsc.c deleted file mode 100644 index 6abb8c388fe2f..0000000000000 --- a/boards/arm/stm32/stm3210e-eval/src/stm32_usbmsc.c +++ /dev/null @@ -1,141 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm3210e-eval/src/stm32_usbmsc.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include -#include - -#include "stm32.h" - -/* There is nothing to do here if SDIO support is not selected. */ - -#ifdef CONFIG_STM32_SDIO - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -#ifndef CONFIG_SYSTEM_USBMSC_DEVMINOR1 -# define CONFIG_SYSTEM_USBMSC_DEVMINOR1 0 -#endif - -/* SLOT number(s) could depend on the board configuration */ - -#ifdef CONFIG_ARCH_BOARD_STM3210E_EVAL -# undef STM32_MMCSDSLOTNO -# define STM32_MMCSDSLOTNO 0 -#else -/* Add configuration for new STM32 boards here */ - -# error "Unrecognized STM32 board" -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_bringup - * - * Description: - * Perform architecture-specific initialization - * - * CONFIG_BOARD_LATE_INITIALIZE=y : - * Called from board_late_initialize(). - * - ****************************************************************************/ - -int stm32_bringup(void); - -/**************************************************************************** - * Name: board_usbmsc_initialize - * - * Description: - * Perform architecture specific initialization as needed to establish - * the mass storage device that will be exported by the USB MSC device. - * - ****************************************************************************/ - -int board_usbmsc_initialize(int port) -{ - /* If system/usbmsc is built as an NSH command, then SD slot should - * already have been initialized. - * In this case, there is nothing further to be done here. - */ - -#ifndef CONFIG_NSH_BUILTIN_APPS - struct sdio_dev_s *sdio; - int ret; - - /* First, get an instance of the SDIO interface */ - - syslog(LOG_INFO, "Initializing SDIO slot %d\n", STM32_MMCSDSLOTNO); - - sdio = sdio_initialize(STM32_MMCSDSLOTNO); - if (!sdio) - { - syslog(LOG_ERR, "ERROR: Failed to initialize SDIO slot %d\n", - STM32_MMCSDSLOTNO); - return -ENODEV; - } - - /* Now bind the SDIO interface to the MMC/SD driver */ - - syslog(LOG_INFO, "Bind SDIO to the MMC/SD driver, minor=%d\n", - CONFIG_SYSTEM_USBMSC_DEVMINOR1); - - ret = mmcsd_slotinitialize(CONFIG_SYSTEM_USBMSC_DEVMINOR1, sdio); - if (ret != OK) - { - syslog(LOG_ERR, - "ERROR: Failed to bind SDIO to the MMC/SD driver: %d\n", - ret); - return ret; - } - - syslog(LOG_INFO, "Successfully bound SDIO to the MMC/SD driver\n"); - - /* Then let's guess and say that there is a card in the slot. - * I need to check to see if the STM3210E-EVAL board supports a GPIO to - * detect if there is a card in the slot. - */ - - sdio_mediachange(sdio, true); - -#endif /* CONFIG_NSH_BUILTIN_APPS */ - - return OK; -} - -#endif /* CONFIG_STM32_SDIO */ diff --git a/boards/arm/stm32/stm3210e-eval/tools/oocd.sh b/boards/arm/stm32/stm3210e-eval/tools/oocd.sh deleted file mode 100755 index 66a7cca63d08a..0000000000000 --- a/boards/arm/stm32/stm3210e-eval/tools/oocd.sh +++ /dev/null @@ -1,87 +0,0 @@ -#!/usr/bin/env bash - -# Get command line parameters - -USAGE="USAGE: $0 [-dh] " -ADVICE="Try '$0 -h' for more information" - -while [ ! -z "$1" ]; do - case $1 in - -d ) - set -x - ;; - -h ) - echo "$0 is a tool for generation of proper version files for the NuttX build" - echo "" - echo $USAGE - echo "" - echo "Where:" - echo " -d" - echo " Enable script debug" - echo " -h" - echo " show this help message and exit" - echo " Use the OpenOCD 0.4.0" - echo " " - echo " The full path to the top-level NuttX directory" - exit 0 - ;; - * ) - break; - ;; - esac - shift -done - -TOPDIR=$1 -if [ -z "${TOPDIR}" ]; then - echo "Missing argument" - echo $USAGE - echo $ADVICE - exit 1 -fi - -# This script *probably* only works with the following versions of OpenOCD: - -# Local search directory and configurations - -OPENOCD_SEARCHDIR="${TOPDIR}/boards/arm/stm32/stm3210e-eval/tools" -OPENOCD_WSEARCHDIR="`cygpath -w ${OPENOCD_SEARCHDIR}`" - -OPENOCD_PATH="/cygdrive/c/Program Files (x86)/OpenOCD/0.4.0/bin" -OPENOCD_EXE=openocd.exe -OPENOCD_INTERFACE="olimex-arm-usb-ocd.cfg" - -OPENOCD_TARGET="stm32.cfg" -OPENOCD_ARGS="-s ${OPENOCD_WSEARCHDIR} -f ${OPENOCD_INTERFACE} -f ${OPENOCD_TARGET}" - -echo "Trying OpenOCD 0.4.0 path: ${OPENOCD_PATH}/${OPENOCD_EXE}" - -# Verify that everything is what it claims it is and is located where it claims it is. - -if [ ! -x "${OPENOCD_PATH}/${OPENOCD_EXE}" ]; then - echo "OpenOCD executable does not exist: ${OPENOCD_PATH}/${OPENOCD_EXE}" - exit 1 -fi -if [ ! -f "${OPENOCD_SEARCHDIR}/${OPENOCD_TARGET}" ]; then - echo "OpenOCD target config file does not exist: ${OPENOCD_SEARCHDIR}/${OPENOCD_TARGET}" - exit 1 -fi -if [ ! -f "${OPENOCD_SEARCHDIR}/${OPENOCD_INTERFACE}" ]; then - echo "OpenOCD interface config file does not exist: ${OPENOCD_SEARCHDIR}/${OPENOCD_INTERFACE}" - exit 1 -fi - -# Enable debug if so requested - -if [ "X$2" = "X-d" ]; then - OPENOCD_ARGS=$OPENOCD_ARGS" -d3" - set -x -fi - -# Okay... do it! - -echo "Starting OpenOCD" -"${OPENOCD_PATH}/${OPENOCD_EXE}" ${OPENOCD_ARGS} & -echo "OpenOCD daemon started" -ps -ef | grep openocd -echo "In GDB: target remote localhost:3333" diff --git a/boards/arm/stm32/stm3220g-eval/CMakeLists.txt b/boards/arm/stm32/stm3220g-eval/CMakeLists.txt deleted file mode 100644 index 70278d3238c1b..0000000000000 --- a/boards/arm/stm32/stm3220g-eval/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/stm3220g-eval/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32/stm3220g-eval/configs/dhcpd/defconfig b/boards/arm/stm32/stm3220g-eval/configs/dhcpd/defconfig deleted file mode 100644 index 4765c757824ab..0000000000000 --- a/boards/arm/stm32/stm3220g-eval/configs/dhcpd/defconfig +++ /dev/null @@ -1,60 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_NETUTILS_DHCPD_IGNOREBROADCAST is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm3220g-eval" -CONFIG_ARCH_BOARD_STM3220G_EVAL=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F207IG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=10926 -CONFIG_DISABLE_ENVIRON=y -CONFIG_DISABLE_MOUNTPOINT=y -CONFIG_DISABLE_MQUEUE=y -CONFIG_DISABLE_PTHREAD=y -CONFIG_ETH0_PHY_DP83848C=y -CONFIG_EXAMPLES_DHCPD=y -CONFIG_EXAMPLES_DHCPD_NOMAC=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_HOST_WINDOWS=y -CONFIG_INIT_ENTRYPOINT="dhcpd_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_MM_REGIONS=2 -CONFIG_NET=y -CONFIG_NETUTILS_DHCPD=y -CONFIG_NETUTILS_NETLIB=y -CONFIG_NET_BROADCAST=y -CONFIG_NET_SOCKOPTS=y -CONFIG_NET_UDP=y -CONFIG_NET_UDP_CHECKSUMS=y -CONFIG_NUNGET_CHARS=0 -CONFIG_RAM_SIZE=196608 -CONFIG_RAM_START=0x20000000 -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=13 -CONFIG_START_MONTH=12 -CONFIG_START_YEAR=2012 -CONFIG_STDIO_DISABLE_BUFFERING=y -CONFIG_STM32_DFU=y -CONFIG_STM32_ETHMAC=y -CONFIG_STM32_JTAG_FULL_ENABLE=y -CONFIG_STM32_MII=y -CONFIG_STM32_PHYSR=16 -CONFIG_STM32_PHYSR_100MBPS=0x0000 -CONFIG_STM32_PHYSR_FULLDUPLEX=0x0004 -CONFIG_STM32_PHYSR_MODE=0x0004 -CONFIG_STM32_PHYSR_SPEED=0x0002 -CONFIG_STM32_USART3=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART3_RXBUFSIZE=128 -CONFIG_USART3_SERIAL_CONSOLE=y -CONFIG_USART3_TXBUFSIZE=128 diff --git a/boards/arm/stm32/stm3220g-eval/configs/nettest/defconfig b/boards/arm/stm32/stm3220g-eval/configs/nettest/defconfig deleted file mode 100644 index ad6101db81811..0000000000000 --- a/boards/arm/stm32/stm3220g-eval/configs/nettest/defconfig +++ /dev/null @@ -1,59 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm3220g-eval" -CONFIG_ARCH_BOARD_STM3220G_EVAL=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F207IG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=10926 -CONFIG_CONSOLE_SYSLOG=y -CONFIG_DISABLE_ENVIRON=y -CONFIG_DISABLE_MOUNTPOINT=y -CONFIG_DISABLE_MQUEUE=y -CONFIG_DISABLE_PTHREAD=y -CONFIG_ETH0_PHY_DP83848C=y -CONFIG_EXAMPLES_NETTEST=y -CONFIG_EXAMPLES_NETTEST_NOMAC=y -CONFIG_EXAMPLES_NETTEST_PERFORMANCE=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_HOST_WINDOWS=y -CONFIG_INIT_ENTRYPOINT="nettest_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_NET=y -CONFIG_NETUTILS_NETLIB=y -CONFIG_NET_MAX_LISTENPORTS=40 -CONFIG_NET_SOCKOPTS=y -CONFIG_NET_TCP=y -CONFIG_NET_TCP_PREALLOC_CONNS=40 -CONFIG_NUNGET_CHARS=0 -CONFIG_RAM_SIZE=196608 -CONFIG_RAM_START=0x20000000 -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=6 -CONFIG_START_MONTH=12 -CONFIG_START_YEAR=2012 -CONFIG_STDIO_DISABLE_BUFFERING=y -CONFIG_STM32_DFU=y -CONFIG_STM32_ETHMAC=y -CONFIG_STM32_JTAG_FULL_ENABLE=y -CONFIG_STM32_MII=y -CONFIG_STM32_PHYSR=16 -CONFIG_STM32_PHYSR_100MBPS=0x0000 -CONFIG_STM32_PHYSR_FULLDUPLEX=0x0004 -CONFIG_STM32_PHYSR_MODE=0x0004 -CONFIG_STM32_PHYSR_SPEED=0x0002 -CONFIG_STM32_USART3=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART3_RXBUFSIZE=128 -CONFIG_USART3_SERIAL_CONSOLE=y -CONFIG_USART3_TXBUFSIZE=128 diff --git a/boards/arm/stm32/stm3220g-eval/configs/nsh/defconfig b/boards/arm/stm32/stm3220g-eval/configs/nsh/defconfig deleted file mode 100644 index 45e7aca47f147..0000000000000 --- a/boards/arm/stm32/stm3220g-eval/configs/nsh/defconfig +++ /dev/null @@ -1,74 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_MMCSD_HAVE_CARDDETECT is not set -# CONFIG_MMCSD_MMCSUPPORT is not set -# CONFIG_NSH_DISABLE_IFCONFIG is not set -# CONFIG_NSH_DISABLE_PS is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm3220g-eval" -CONFIG_ARCH_BOARD_STM3220G_EVAL=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F207IG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=10926 -CONFIG_BUILTIN=y -CONFIG_ETH0_PHY_DP83848C=y -CONFIG_FAT_LCNAMES=y -CONFIG_FAT_LFN=y -CONFIG_FS_FAT=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_I2C=y -CONFIG_I2C_POLLED=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_MMCSD=y -CONFIG_MMCSD_MULTIBLOCK_LIMIT=1 -CONFIG_MTD=y -CONFIG_NET=y -CONFIG_NETDB_DNSCLIENT=y -CONFIG_NETUTILS_TFTPC=y -CONFIG_NETUTILS_WEBCLIENT=y -CONFIG_NET_BROADCAST=y -CONFIG_NET_ICMP_SOCKET=y -CONFIG_NET_MAX_LISTENPORTS=40 -CONFIG_NET_STATISTICS=y -CONFIG_NET_TCP=y -CONFIG_NET_TCP_PREALLOC_CONNS=40 -CONFIG_NET_UDP=y -CONFIG_NET_UDP_CHECKSUMS=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=196608 -CONFIG_RAM_START=0x20000000 -CONFIG_RR_INTERVAL=200 -CONFIG_RTC_DATETIME=y -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_WAITPID=y -CONFIG_STM32_DFU=y -CONFIG_STM32_ETHMAC=y -CONFIG_STM32_I2C1=y -CONFIG_STM32_JTAG_FULL_ENABLE=y -CONFIG_STM32_MII=y -CONFIG_STM32_PHYSR=16 -CONFIG_STM32_PHYSR_100MBPS=0x0000 -CONFIG_STM32_PHYSR_FULLDUPLEX=0x0004 -CONFIG_STM32_PHYSR_MODE=0x0004 -CONFIG_STM32_PHYSR_SPEED=0x0002 -CONFIG_STM32_PWR=y -CONFIG_STM32_RTC=y -CONFIG_STM32_USART3=y -CONFIG_SYMTAB_ORDEREDBYNAME=y -CONFIG_SYSTEM_NSH=y -CONFIG_SYSTEM_PING=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART3_RXBUFSIZE=128 -CONFIG_USART3_SERIAL_CONSOLE=y -CONFIG_USART3_TXBUFSIZE=128 diff --git a/boards/arm/stm32/stm3220g-eval/configs/nsh2/defconfig b/boards/arm/stm32/stm3220g-eval/configs/nsh2/defconfig deleted file mode 100644 index 25cbc3ad5eb00..0000000000000 --- a/boards/arm/stm32/stm3220g-eval/configs/nsh2/defconfig +++ /dev/null @@ -1,88 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_DEV_CONSOLE is not set -# CONFIG_MMCSD_HAVE_CARDDETECT is not set -# CONFIG_MMCSD_MMCSUPPORT is not set -# CONFIG_NSH_CONSOLE is not set -# CONFIG_NSH_DISABLE_IFCONFIG is not set -# CONFIG_NSH_DISABLE_PS is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm3220g-eval" -CONFIG_ARCH_BOARD_STM3220G_EVAL=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F207IG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=10926 -CONFIG_BUILTIN=y -CONFIG_ETH0_PHY_DP83848C=y -CONFIG_FAT_LCNAMES=y -CONFIG_FAT_LFN=y -CONFIG_FS_FAT=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_HOST_WINDOWS=y -CONFIG_I2C=y -CONFIG_I2CTOOL_DEFFREQ=100000 -CONFIG_I2CTOOL_MINBUS=1 -CONFIG_I2C_POLLED=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_MMCSD=y -CONFIG_MMCSD_MULTIBLOCK_LIMIT=1 -CONFIG_MMCSD_SDIO=y -CONFIG_MTD=y -CONFIG_NET=y -CONFIG_NETDB_DNSCLIENT=y -CONFIG_NETDB_DNSCLIENT_ENTRIES=4 -CONFIG_NETDB_DNSSERVER_NOADDR=y -CONFIG_NETINIT_NOMAC=y -CONFIG_NETUTILS_TELNETD=y -CONFIG_NETUTILS_TFTPC=y -CONFIG_NETUTILS_WEBCLIENT=y -CONFIG_NET_BROADCAST=y -CONFIG_NET_ICMP_SOCKET=y -CONFIG_NET_MAX_LISTENPORTS=40 -CONFIG_NET_STATISTICS=y -CONFIG_NET_TCP=y -CONFIG_NET_TCP_PREALLOC_CONNS=40 -CONFIG_NET_UDP=y -CONFIG_NET_UDP_CHECKSUMS=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAMLOG=y -CONFIG_RAMLOG_SYSLOG=y -CONFIG_RAM_SIZE=196608 -CONFIG_RAM_START=0x20000000 -CONFIG_RR_INTERVAL=200 -CONFIG_RTC_DATETIME=y -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_HPWORKPRIORITY=192 -CONFIG_SCHED_WAITPID=y -CONFIG_STM32_DFU=y -CONFIG_STM32_DMA2=y -CONFIG_STM32_ETHMAC=y -CONFIG_STM32_I2C1=y -CONFIG_STM32_JTAG_FULL_ENABLE=y -CONFIG_STM32_MII=y -CONFIG_STM32_PHYSR=16 -CONFIG_STM32_PHYSR_100MBPS=0x0000 -CONFIG_STM32_PHYSR_FULLDUPLEX=0x0004 -CONFIG_STM32_PHYSR_MODE=0x0004 -CONFIG_STM32_PHYSR_SPEED=0x0002 -CONFIG_STM32_PWR=y -CONFIG_STM32_RTC=y -CONFIG_STM32_SDIO=y -CONFIG_SYMTAB_ORDEREDBYNAME=y -CONFIG_SYSTEM_I2CTOOL=y -CONFIG_SYSTEM_NSH=y -CONFIG_SYSTEM_PING=y -CONFIG_TASK_NAME_SIZE=0 diff --git a/boards/arm/stm32/stm3220g-eval/configs/nxwm/defconfig b/boards/arm/stm32/stm3220g-eval/configs/nxwm/defconfig deleted file mode 100644 index 4756ef1512f6d..0000000000000 --- a/boards/arm/stm32/stm3220g-eval/configs/nxwm/defconfig +++ /dev/null @@ -1,125 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_MMCSD_HAVE_CARDDETECT is not set -# CONFIG_MMCSD_MMCSUPPORT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -# CONFIG_NSH_DISABLE_IFCONFIG is not set -# CONFIG_NSH_DISABLE_PS is not set -# CONFIG_NXFONTS_DISABLE_16BPP is not set -# CONFIG_NXTK_DEFAULT_BORDERCOLORS is not set -# CONFIG_NX_DISABLE_16BPP is not set -# CONFIG_NX_PACKEDMSFIRST is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm3220g-eval" -CONFIG_ARCH_BOARD_STM3220G_EVAL=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F207IG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=10926 -CONFIG_ETH0_PHY_DP83848C=y -CONFIG_FAT_LCNAMES=y -CONFIG_FAT_LFN=y -CONFIG_FS_FAT=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_HOST_WINDOWS=y -CONFIG_I2C_POLLED=y -CONFIG_INIT_ENTRYPOINT="nxwm_main" -CONFIG_INPUT=y -CONFIG_INPUT_STMPE811=y -CONFIG_INTELHEX_BINARY=y -CONFIG_LCD=y -CONFIG_LCD_MAXCONTRAST=1 -CONFIG_LCD_NOGETRUN=y -CONFIG_LIBC_MAX_EXITFUNS=1 -CONFIG_LINE_MAX=64 -CONFIG_MMCSD=y -CONFIG_MMCSD_MULTIBLOCK_LIMIT=1 -CONFIG_MQ_MAXMSGSIZE=64 -CONFIG_NET=y -CONFIG_NETINIT_NOMAC=y -CONFIG_NETUTILS_TELNETD=y -CONFIG_NETUTILS_TFTPC=y -CONFIG_NETUTILS_WEBCLIENT=y -CONFIG_NET_ICMP_SOCKET=y -CONFIG_NET_MAX_LISTENPORTS=40 -CONFIG_NET_STATISTICS=y -CONFIG_NET_TCP=y -CONFIG_NET_TCP_PREALLOC_CONNS=40 -CONFIG_NET_UDP=y -CONFIG_NET_UDP_CHECKSUMS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_LIBRARY=y -CONFIG_NSH_READLINE=y -CONFIG_NX=y -CONFIG_NXFONT_SANS22X29B=y -CONFIG_NXFONT_SANS23X27=y -CONFIG_NXTERM=y -CONFIG_NXTERM_CACHESIZE=32 -CONFIG_NXTERM_CURSORCHAR=95 -CONFIG_NXTERM_MXCHARS=325 -CONFIG_NXTERM_NXKBDIN=y -CONFIG_NXTK_BORDERCOLOR1=0x5cb7 -CONFIG_NXTK_BORDERCOLOR2=0x21c9 -CONFIG_NXTK_BORDERCOLOR3=0xffdf -CONFIG_NXWIDGETS=y -CONFIG_NXWIDGETS_BPP=16 -CONFIG_NXWIDGETS_CUSTOM_EDGECOLORS=y -CONFIG_NXWIDGETS_CUSTOM_FILLCOLORS=y -CONFIG_NXWIDGETS_DEFAULT_BACKGROUNDCOLOR=0x9dfb -CONFIG_NXWIDGETS_DEFAULT_HIGHLIGHTCOLOR=0xc618 -CONFIG_NXWIDGETS_DEFAULT_SELECTEDBACKGROUNDCOLOR=0xd73e -CONFIG_NXWIDGETS_DEFAULT_SHADOWEDGECOLOR=0x21e9 -CONFIG_NXWIDGETS_DEFAULT_SHINEEDGECOLOR=0xffdf -CONFIG_NXWIDGETS_SIZEOFCHAR=1 -CONFIG_NXWM=y -CONFIG_NXWM_BACKGROUND_IMAGE="" -CONFIG_NXWM_HEXCALCULATOR_CUSTOM_FONTID=y -CONFIG_NXWM_HEXCALCULATOR_FONTID=5 -CONFIG_NXWM_KEYBOARD=y -CONFIG_NXWM_KEYBOARD_LISTENERPRIO=100 -CONFIG_NXWM_TASKBAR_LEFT=y -CONFIG_NXWM_TASKBAR_VSPACING=4 -CONFIG_NXWM_TOUCHSCREEN_LISTENERPRIO=100 -CONFIG_NX_BLOCKING=y -CONFIG_NX_KBD=y -CONFIG_NX_XYINPUT_TOUCHSCREEN=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=196608 -CONFIG_RAM_START=0x20000000 -CONFIG_RR_INTERVAL=200 -CONFIG_RTC_DATETIME=y -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_HPWORKPRIORITY=192 -CONFIG_SCHED_WAITPID=y -CONFIG_STM32_DFU=y -CONFIG_STM32_ETHMAC=y -CONFIG_STM32_FSMC=y -CONFIG_STM32_I2C1=y -CONFIG_STM32_JTAG_FULL_ENABLE=y -CONFIG_STM32_MII=y -CONFIG_STM32_PHYSR=16 -CONFIG_STM32_PHYSR_100MBPS=0x0000 -CONFIG_STM32_PHYSR_FULLDUPLEX=0x0004 -CONFIG_STM32_PHYSR_MODE=0x0004 -CONFIG_STM32_PHYSR_SPEED=0x0002 -CONFIG_STM32_PWR=y -CONFIG_STM32_RTC=y -CONFIG_STM32_USART3=y -CONFIG_STMPE811_ACTIVELOW=y -CONFIG_STMPE811_EDGE=y -CONFIG_STMPE811_MULTIPLE=y -CONFIG_STMPE811_THRESHX=39 -CONFIG_STMPE811_THRESHY=51 -CONFIG_SYMTAB_ORDEREDBYNAME=y -CONFIG_SYSTEM_PING=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART3_RXBUFSIZE=128 -CONFIG_USART3_SERIAL_CONSOLE=y -CONFIG_USART3_TXBUFSIZE=128 diff --git a/boards/arm/stm32/stm3220g-eval/configs/telnetd/defconfig b/boards/arm/stm32/stm3220g-eval/configs/telnetd/defconfig deleted file mode 100644 index 7ca6a50bbac63..0000000000000 --- a/boards/arm/stm32/stm3220g-eval/configs/telnetd/defconfig +++ /dev/null @@ -1,61 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm3220g-eval" -CONFIG_ARCH_BOARD_STM3220G_EVAL=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F207IG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=10926 -CONFIG_CONSOLE_SYSLOG=y -CONFIG_DISABLE_ENVIRON=y -CONFIG_DISABLE_MOUNTPOINT=y -CONFIG_DISABLE_MQUEUE=y -CONFIG_DISABLE_PTHREAD=y -CONFIG_ETH0_PHY_DP83848C=y -CONFIG_EXAMPLES_TELNETD=y -CONFIG_EXAMPLES_TELNETD_CLIENTPRIO=128 -CONFIG_EXAMPLES_TELNETD_DAEMONPRIO=128 -CONFIG_EXAMPLES_TELNETD_NOMAC=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_INIT_ENTRYPOINT="telnetd_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_MM_REGIONS=2 -CONFIG_NET=y -CONFIG_NETUTILS_TELNETD=y -CONFIG_NET_MAX_LISTENPORTS=40 -CONFIG_NET_SOCKOPTS=y -CONFIG_NET_TCP=y -CONFIG_NET_TCP_PREALLOC_CONNS=40 -CONFIG_NSH_LIBRARY=y -CONFIG_NUNGET_CHARS=0 -CONFIG_RAM_SIZE=196608 -CONFIG_RAM_START=0x20000000 -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=6 -CONFIG_START_MONTH=12 -CONFIG_START_YEAR=2012 -CONFIG_STM32_DFU=y -CONFIG_STM32_ETHMAC=y -CONFIG_STM32_JTAG_FULL_ENABLE=y -CONFIG_STM32_MII=y -CONFIG_STM32_PHYSR=16 -CONFIG_STM32_PHYSR_100MBPS=0x0000 -CONFIG_STM32_PHYSR_FULLDUPLEX=0x0004 -CONFIG_STM32_PHYSR_MODE=0x0004 -CONFIG_STM32_PHYSR_SPEED=0x0002 -CONFIG_STM32_USART3=y -CONFIG_SYSTEM_READLINE=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART3_RXBUFSIZE=128 -CONFIG_USART3_SERIAL_CONSOLE=y -CONFIG_USART3_TXBUFSIZE=128 diff --git a/boards/arm/stm32/stm3220g-eval/include/board.h b/boards/arm/stm32/stm3220g-eval/include/board.h deleted file mode 100644 index 86ebef53bb08b..0000000000000 --- a/boards/arm/stm32/stm3220g-eval/include/board.h +++ /dev/null @@ -1,552 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm3220g-eval/include/board.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __BOARDS_ARM_STM32_STM3220G_EVAL_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32_STM3220G_EVAL_INCLUDE_BOARD_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#ifndef __ASSEMBLY__ -# include -#endif - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Clocking *****************************************************************/ - -/* Four clock sources are available on STM3220G-EVAL evaluation board for - * STM32F207IGH6 and RTC embedded: - * - * X1, 25 MHz crystal for ethernet PHY with socket. - * It can be removed when clock is provided by MCO pin of the MCU - * X2, 26 MHz crystal for USB OTG HS PHY - * X3, 32 kHz crystal for embedded RTC - * X4, 25 MHz crystal with socket for STM32F207IGH6 microcontroller - * (It can be removed from socket when internal RC clock is used.) - * - * This is the "standard" configuration as set up by - * arch/arm/src/stm32f40xx_rcc.c: - * System Clock source : PLL (HSE) - * SYSCLK(Hz) : 120000000 Determined by PLL - * configuration - * HCLK(Hz) : 120000000 (STM32_RCC_CFGR_HPRE) - * AHB Prescaler : 1 (STM32_RCC_CFGR_HPRE) - * APB1 Prescaler : 4 (STM32_RCC_CFGR_PPRE1) - * APB2 Prescaler : 2 (STM32_RCC_CFGR_PPRE2) - * HSE Frequency(Hz) : 25000000 (STM32_BOARD_XTAL) - * PLLM : 25 (STM32_PLLCFG_PLLM) - * PLLN : 240 (STM32_PLLCFG_PLLN) - * PLLP : 2 (STM32_PLLCFG_PLLP) - * PLLQ : 5 (STM32_PLLCFG_PLLQ) - * Main regulator output voltage : Scale1 mode Needed for high speed - * SYSCLK - * Flash Latency(WS) : 5 - * Prefetch Buffer : OFF - * Instruction cache : ON - * Data cache : ON - * Require 48MHz for USB OTG FS, : Enabled - * SDIO and RNG clock - */ - -/* HSI - 16 MHz RC factory-trimmed - * LSI - 32 KHz RC - * HSE - On-board crystal frequency is 25MHz - * LSE - 32.768 kHz - */ - -#define STM32_BOARD_XTAL 25000000ul - -#define STM32_HSI_FREQUENCY 16000000ul -#define STM32_LSI_FREQUENCY 32000 -#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL -#define STM32_LSE_FREQUENCY 32768 - -/* Main PLL Configuration. - * - * PLL source is HSE - * PLL_VCO = (STM32_HSE_FREQUENCY / PLLM) * PLLN - * = (25,000,000 / 25) * 240 - * = 240,000,000 - * SYSCLK = PLL_VCO / PLLP - * = 240,000,000 / 2 = 120,000,000 - * USB OTG FS, SDIO and RNG Clock - * = PLL_VCO / PLLQ - * = 240,000,000 / 5 = 48,000,000 - * = 48,000,000 - */ - -#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(25) -#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(240) -#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_2 -#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(5) - -#define STM32_SYSCLK_FREQUENCY 120000000ul - -/* AHB clock (HCLK) is SYSCLK (120MHz) */ - -#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ -#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY - -/* APB1 clock (PCLK1) is HCLK/4 (30MHz) */ - -#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd4 /* PCLK1 = HCLK / 4 */ -#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/4) - -/* Timers driven from APB1 will be twice PCLK1 (60Mhz) */ - -#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) - -/* APB2 clock (PCLK2) is HCLK/2 (60MHz) */ - -#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLKd2 /* PCLK2 = HCLK / 2 */ -#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/2) - -/* Timers driven from APB2 will be twice PCLK2 (120Mhz) */ - -#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM9_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM10_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM11_CLKIN (2*STM32_PCLK2_FREQUENCY) - -/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx - * otherwise frequency is 2xAPBx. - * Note: TIM1,8 are on APB2, others on APB1 - */ - -#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM2_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM3_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM4_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM5_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM6_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM7_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY - -/* SDIO dividers. Note that slower clocking is required when DMA is disabled - * in order to avoid RX overrun/TX underrun errors due to delayed responses - * to service FIFOs in interrupt driven mode. These values have not been - * tuned!!! - * - * SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(118+2)=400 KHz - */ - -#define SDIO_INIT_CLKDIV (118 << SDIO_CLKCR_CLKDIV_SHIFT) - -/* DMA ON: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(1+2)=16 MHz - * DMA OFF: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(2+2)=12 MHz - */ - -#ifdef CONFIG_SDIO_DMA -# define SDIO_MMCXFR_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT) -#else -# define SDIO_MMCXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT) -#endif - -/* DMA ON: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(1+2)= 16 MHz - * DMA OFF: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(2+2)= 12 MHz - */ - -#ifdef CONFIG_SDIO_DMA -# define SDIO_SDXFR_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT) -#else -# define SDIO_SDXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT) -#endif - -/* Ethernet *****************************************************************/ - -/* We need to provide clocking to the MII PHY via MCO1 (PA8) */ - -#if defined(CONFIG_NET) && defined(CONFIG_STM32_ETHMAC) - -# if !defined(CONFIG_STM32_MII) -# warning "CONFIG_STM32_MII required for Ethernet" -# elif !defined(CONFIG_STM32_MII_MCO1) -# warning "CONFIG_STM32_MII_MCO1 required for Ethernet MII" -# else - - /* Output HSE clock (25MHz) on MCO1 pin (PA8) to clock the PHY */ - -# define BOARD_CFGR_MC01_SOURCE RCC_CFGR_MCO1_HSE -# define BOARD_CFGR_MC01_DIVIDER RCC_CFGR_MCO1PRE_NONE - -# endif -#endif - -/* LED definitions **********************************************************/ - -/* If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs in - * any way. The following definitions are used to access individual LEDs. - */ - -/* LED index values for use with board_userled() */ - -#define BOARD_LED1 0 -#define BOARD_LED2 1 -#define BOARD_LED3 2 -#define BOARD_LED4 3 -#define BOARD_NLEDS 4 - -/* LED bits for use with board_userled_all() */ - -#define BOARD_LED1_BIT (1 << BOARD_LED1) -#define BOARD_LED2_BIT (1 << BOARD_LED2) -#define BOARD_LED3_BIT (1 << BOARD_LED3) -#define BOARD_LED4_BIT (1 << BOARD_LED4) - -/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the 4 LEDs on - * board the STM3220G-EVAL. - * The following definitions describe how NuttX controls the LEDs: - */ - -#define LED_STARTED 0 /* LED1 */ -#define LED_HEAPALLOCATE 1 /* LED2 */ -#define LED_IRQSENABLED 2 /* LED1 + LED2 */ -#define LED_STACKCREATED 3 /* LED3 */ -#define LED_INIRQ 4 /* LED1 + LED3 */ -#define LED_SIGNAL 5 /* LED2 + LED3 */ -#define LED_ASSERTION 6 /* LED1 + LED2 + LED3 */ -#define LED_PANIC 7 /* N/C + N/C + N/C + LED4 */ - -/* Button definitions *******************************************************/ - -/* The STM3220G-EVAL supports three buttons: */ - -#define BUTTON_WAKEUP 0 -#define BUTTON_TAMPER 1 -#define BUTTON_USER 2 - -#define NUM_BUTTONS 3 - -#define BUTTON_WAKEUP_BIT (1 << BUTTON_WAKEUP) -#define BUTTON_TAMPER_BIT (1 << BUTTON_TAMPER) -#define BUTTON_USER_BIT (1 << BUTTON_USER) - -/* Alternate function pin selections ****************************************/ - -/* UART3: - * - * - PC11 is MicroSDCard_D3 & RS232/IrDA_RX (JP22 open) - * - PC10 is MicroSDCard_D2 & RSS232/IrDA_TX - */ - -#ifdef CONFIG_STM32_USART3 -# define GPIO_USART3_RX (GPIO_USART3_RX_2|GPIO_SPEED_100MHz) -# define GPIO_USART3_TX (GPIO_USART3_TX_2|GPIO_SPEED_100MHz) -#endif - -/* Ethernet: - * - * - PA2 is ETH_MDIO - * - PC1 is ETH_MDC - * - PB5 is ETH_PPS_OUT - * - PH2 is ETH_MII_CRS - * - PH3 is ETH_MII_COL - * - PI10 is ETH_MII_RX_ER - * - PH6 is ETH_MII_RXD2 - * - PH7 is ETH_MII_RXD3 - * - PC3 is ETH_MII_TX_CLK - * - PC2 is ETH_MII_TXD2 - * - PB8 is ETH_MII_TXD3 - * - PA1 is ETH_MII_RX_CLK/ETH_RMII_REF_CLK - * - PA7 is ETH_MII_RX_DV/ETH_RMII_CRS_DV - * - PC4 is ETH_MII_RXD0/ETH_RMII_RXD0 - * - PC5 is ETH_MII_RXD1/ETH_RMII_RXD1 - * - PG11 is ETH_MII_TX_EN/ETH_RMII_TX_EN - * - PG13 is ETH_MII_TXD0/ETH_RMII_TXD0 - * - PG14 is ETH_MII_TXD1/ETH_RMII_TXD1 - */ - -#define GPIO_MCO1 (GPIO_MCO1_0|GPIO_SPEED_100MHz) -#define GPIO_ETH_MDC (GPIO_ETH_MDC_0|GPIO_SPEED_100MHz) -#define GPIO_ETH_MDIO (GPIO_ETH_MDIO_0|GPIO_SPEED_100MHz) -#define GPIO_ETH_MII_RX_CLK (GPIO_ETH_MII_RX_CLK_0|GPIO_SPEED_100MHz) -#define GPIO_ETH_MII_RX_DV (GPIO_ETH_MII_RX_DV_0|GPIO_SPEED_100MHz) -#define GPIO_ETH_MII_RXD0 (GPIO_ETH_MII_RXD0_0|GPIO_SPEED_100MHz) -#define GPIO_ETH_MII_RXD1 (GPIO_ETH_MII_RXD1_0|GPIO_SPEED_100MHz) -#define GPIO_ETH_MII_TX_CLK (GPIO_ETH_MII_TX_CLK_0|GPIO_SPEED_100MHz) -#define GPIO_ETH_MII_TXD2 (GPIO_ETH_MII_TXD2_0|GPIO_SPEED_100MHz) -#define GPIO_ETH_RMII_CRS_DV (GPIO_ETH_RMII_CRS_DV_0|GPIO_SPEED_100MHz) -#define GPIO_ETH_RMII_REF_CLK (GPIO_ETH_RMII_REF_CLK_0|GPIO_SPEED_100MHz) -#define GPIO_ETH_RMII_RXD0 (GPIO_ETH_RMII_RXD0_0|GPIO_SPEED_100MHz) -#define GPIO_ETH_RMII_RXD1 (GPIO_ETH_RMII_RXD1_0|GPIO_SPEED_100MHz) -#define GPIO_ETH_PPS_OUT (GPIO_ETH_PPS_OUT_1|GPIO_SPEED_100MHz) -#define GPIO_ETH_MII_CRS (GPIO_ETH_MII_CRS_2|GPIO_SPEED_100MHz) -#define GPIO_ETH_MII_COL (GPIO_ETH_MII_COL_2|GPIO_SPEED_100MHz) -#define GPIO_ETH_MII_RX_ER (GPIO_ETH_MII_RX_ER_2|GPIO_SPEED_100MHz) -#define GPIO_ETH_MII_RXD2 (GPIO_ETH_MII_RXD2_2|GPIO_SPEED_100MHz) -#define GPIO_ETH_MII_RXD3 (GPIO_ETH_MII_RXD3_2|GPIO_SPEED_100MHz) -#define GPIO_ETH_MII_TXD3 (GPIO_ETH_MII_TXD3_1|GPIO_SPEED_100MHz) -#define GPIO_ETH_MII_TX_EN (GPIO_ETH_MII_TX_EN_2|GPIO_SPEED_100MHz) -#define GPIO_ETH_MII_TXD0 (GPIO_ETH_MII_TXD0_2|GPIO_SPEED_100MHz) -#define GPIO_ETH_MII_TXD1 (GPIO_ETH_MII_TXD1_2|GPIO_SPEED_100MHz) -#define GPIO_ETH_RMII_TX_EN (GPIO_ETH_RMII_TX_EN_2|GPIO_SPEED_100MHz) -#define GPIO_ETH_RMII_TXD0 (GPIO_ETH_RMII_TXD0_2|GPIO_SPEED_100MHz) -#define GPIO_ETH_RMII_TXD1 (GPIO_ETH_RMII_TXD1_2|GPIO_SPEED_100MHz) - -/* PWM - * - * The STM3220G-Eval has no real on-board PWM devices, but the board can be - * configured to output a pulse train using the following: - * - * If FSMC is not used: - * TIM4 CH2OUT: PD13 FSMC_A18 / MC_TIM4_CH2OUT - * Daughterboard Extension Connector, CN3, pin 32 - * Motor Control Connector CN15, - * pin 33 -- not available unless you bridge SB14. - * - * TIM1 CH1OUT: PE9 FSMC_D6 - * Daughterboard Extension Connector, CN2, pin 24 - * - * TIM1_CH2OUT: PE11 FSMC_D8 - * Daughterboard Extension Connector, CN2, pin 26 - * - * TIM1_CH3OUT: PE13 FSMC_D10 - * Daughterboard Extension Connector, CN2, pin 28 - * - * TIM1_CH4OUT: PE14 FSMC_D11 - * Daughterboard Extension Connector, CN2, pin 29 - * - * If OTG FS is not used - * - * TIM1_CH3OUT: PA10 OTG_FS_ID - * Daughterboard Extension Connector, CN3, pin 14 - * - * TIM1_CH4OUT: PA11 OTG_FS_DM - * Daughterboard Extension Connector, CN3, pin 11 - * - * If DMCI is not used - * - * TIM8 CH1OUT: PI5 DCMI_VSYNC & MC - * Daughterboard Extension Connector, CN4, pin 4 - * - * TIM8_CH2OUT: PI6 DCMI_D6 & MC - * Daughterboard Extension Connector, CN4, pin 3 - * - * TIM8_CH3OUT: PI7 DCMI_D7 & MC - * Daughterboard Extension Connector, CN4, pin 2 - * - * If SDIO is not used - * - * TIM8_CH3OUT: PC8 MicroSDCard_D0 & MC - * Daughterboard Extension Connector, CN3, pin 18 - * - * TIM8_CH4OUT: PC9 MicroSDCard_D1 & I2S_CKIN (Need JP16 open) - * Daughterboard Extension Connector, CN3, pin 17 - * - * Others - * - * TIM8 CH1OUT: PC6 I2S_MCK & Smartcard_IO (JP21 open) - */ - -#if !defined(CONFIG_STM32_FSMC) -# define GPIO_TIM4_CH2OUT (GPIO_TIM4_CH2OUT_2|GPIO_SPEED_50MHz) -# define GPIO_TIM1_CH1OUT (GPIO_TIM1_CH1OUT_2|GPIO_SPEED_50MHz) -# define GPIO_TIM1_CH2OUT (GPIO_TIM1_CH2OUT_2|GPIO_SPEED_50MHz) -# define GPIO_TIM1_CH3OUT (GPIO_TIM1_CH3OUT_2|GPIO_SPEED_50MHz) -# define GPIO_TIM1_CH4OUT (GPIO_TIM1_CH4OUT_2|GPIO_SPEED_50MHz) -#elif !defined(CONFIG_STM32_OTGFS) -# define GPIO_TIM1_CH3OUT (GPIO_TIM1_CH3OUT_1|GPIO_SPEED_50MHz) -# define GPIO_TIM1_CH4OUT (GPIO_TIM1_CH4OUT_1|GPIO_SPEED_50MHz) -#endif - -#if !defined(CONFIG_STM32_DCMI) -# define GPIO_TIM8_CH1OUT (GPIO_TIM8_CH1OUT_2|GPIO_SPEED_50MHz) -# define GPIO_TIM8_CH2OUT (GPIO_TIM8_CH2OUT_2|GPIO_SPEED_50MHz) -# define GPIO_TIM8_CH3OUT (GPIO_TIM8_CH3OUT_2|GPIO_SPEED_50MHz) -#else -# define GPIO_TIM8_CH1OUT (GPIO_TIM8_CH1OUT_1|GPIO_SPEED_50MHz) -# if !defined(CONFIG_STM32_SDIO) -# define GPIO_TIM8_CH3OUT (GPIO_TIM8_CH3OUT_1|GPIO_SPEED_50MHz) -# endif -#endif - -#if !defined(CONFIG_STM32_SDIO) -# define GPIO_TIM8_CH4OUT (GPIO_TIM8_CH4OUT_1|GPIO_SPEED_50MHz) -#endif - -/* CAN - * - * Connector 10 (CN10) - * is DB-9 male connector that can be used with CAN1 or CAN2. - * - * JP10 connects CAN1_RX or CAN2_RX to the CAN transceiver - * JP3 connects CAN1_TX or CAN2_TX to the CAN transceiver - * - * CAN signals are then available on CN10 pins: - * - * CN10 Pin 7 = CANH - * CN10 Pin 2 = CANL - * - * Mapping to STM32 GPIO pins: - * - * PD0 = FSMC_D2 & CAN1_RX - * PD1 = FSMC_D3 & CAN1_TX - * PB13 = ULPI_D6 & CAN2_TX - * PB5 = ULPI_D7 & CAN2_RX - */ - -#define GPIO_CAN1_RX (GPIO_CAN1_RX_3|GPIO_SPEED_50MHz) -#define GPIO_CAN1_TX (GPIO_CAN1_TX_3|GPIO_SPEED_50MHz) - -#define GPIO_CAN2_RX (GPIO_CAN2_RX_2|GPIO_SPEED_50MHz) -#define GPIO_CAN2_TX (GPIO_CAN2_TX_1|GPIO_SPEED_50MHz) - -/* I2C. - * Only I2C1 is available on the STM3220G-EVAL. I2C1_SCL and I2C1_SDA are - * available on the following pins: - * - * - PB6 is I2C1_SCL - * - PB9 is I2C1_SDA - */ - -#define GPIO_I2C1_SCL (GPIO_I2C1_SCL_1|GPIO_SPEED_50MHz) -#define GPIO_I2C1_SDA (GPIO_I2C1_SDA_2|GPIO_SPEED_50MHz) - -/* SDIO */ - -#define GPIO_SDIO_CK (GPIO_SDIO_CK_0|GPIO_SPEED_50MHz) -#define GPIO_SDIO_CMD (GPIO_SDIO_CMD_0|GPIO_SPEED_50MHz) -#define GPIO_SDIO_D0 (GPIO_SDIO_D0_0|GPIO_SPEED_50MHz) -#define GPIO_SDIO_D1 (GPIO_SDIO_D1_0|GPIO_SPEED_50MHz) -#define GPIO_SDIO_D2 (GPIO_SDIO_D2_0|GPIO_SPEED_50MHz) -#define GPIO_SDIO_D3 (GPIO_SDIO_D3_0|GPIO_SPEED_50MHz) - -/* FSMC (LCD/SRAM) */ - -#define GPIO_FSMC_NOE (GPIO_FSMC_NOE_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_NWE (GPIO_FSMC_NWE_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_NE2 (GPIO_FSMC_NE2_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_NE3 (GPIO_FSMC_NE3_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_NBL0 (GPIO_FSMC_NBL0_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_NBL1 (GPIO_FSMC_NBL1_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A0 (GPIO_FSMC_A0_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A1 (GPIO_FSMC_A1_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A2 (GPIO_FSMC_A2_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A3 (GPIO_FSMC_A3_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A4 (GPIO_FSMC_A4_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A5 (GPIO_FSMC_A5_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A6 (GPIO_FSMC_A6_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A7 (GPIO_FSMC_A7_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A8 (GPIO_FSMC_A8_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A9 (GPIO_FSMC_A9_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A10 (GPIO_FSMC_A10_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A11 (GPIO_FSMC_A11_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A12 (GPIO_FSMC_A12_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A13 (GPIO_FSMC_A13_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A14 (GPIO_FSMC_A14_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A15 (GPIO_FSMC_A15_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A16 (GPIO_FSMC_A16_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A17 (GPIO_FSMC_A17_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A18 (GPIO_FSMC_A18_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A19 (GPIO_FSMC_A19_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A20 (GPIO_FSMC_A20_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A21 (GPIO_FSMC_A21_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A22 (GPIO_FSMC_A22_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A23 (GPIO_FSMC_A23_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A24 (GPIO_FSMC_A24_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A25 (GPIO_FSMC_A25_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_D0 (GPIO_FSMC_D0_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_D1 (GPIO_FSMC_D1_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_D2 (GPIO_FSMC_D2_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_D3 (GPIO_FSMC_D3_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_D4 (GPIO_FSMC_D4_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_D5 (GPIO_FSMC_D5_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_D6 (GPIO_FSMC_D6_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_D7 (GPIO_FSMC_D7_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_D8 (GPIO_FSMC_D8_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_D9 (GPIO_FSMC_D9_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_D10 (GPIO_FSMC_D10_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_D11 (GPIO_FSMC_D11_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_D12 (GPIO_FSMC_D12_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_D13 (GPIO_FSMC_D13_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_D14 (GPIO_FSMC_D14_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_D15 (GPIO_FSMC_D15_0|GPIO_SPEED_100MHz) - -/* DMA Channel/Stream Selections ********************************************/ - -/* Stream selections are arbitrary for now but might become important in the - * future is we set aside more DMA channels/streams. - * - * SDIO DMA - * DMAMAP_SDIO_1 = Channel 4, Stream 3 - * DMAMAP_SDIO_2 = Channel 4, Stream 6 - */ - -#define DMAMAP_SDIO DMAMAP_SDIO_1 - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -#ifndef __ASSEMBLY__ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: stm3220g_lcdclear - * - * Description: - * This is a non-standard LCD interface just for the STM3210E-EVAL board. - * Because of the various rotations, clearing the display in the normal - * way by writing a sequences of runs that covers the entire display can be - * very slow. Here the display is cleared by simply setting all GRAM - * memory to the specified color. - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_FSMC -void stm3220g_lcdclear(uint16_t color); -#endif - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ -#endif /* __BOARDS_ARM_STM32_STM3220G_EVAL_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32/stm3220g-eval/scripts/Make.defs b/boards/arm/stm32/stm3220g-eval/scripts/Make.defs deleted file mode 100644 index f0aa8af0b8ece..0000000000000 --- a/boards/arm/stm32/stm3220g-eval/scripts/Make.defs +++ /dev/null @@ -1,41 +0,0 @@ -############################################################################ -# boards/arm/stm32/stm3220g-eval/scripts/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/.config -include $(TOPDIR)/tools/Config.mk -include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs - -LDSCRIPT = ld.script -ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) - -ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 - -CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) -CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) -CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -AFLAGS := $(CFLAGS) -D__ASSEMBLY__ - -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections -LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32/stm3220g-eval/scripts/ld.script b/boards/arm/stm32/stm3220g-eval/scripts/ld.script deleted file mode 100644 index 0133f9415af2a..0000000000000 --- a/boards/arm/stm32/stm3220g-eval/scripts/ld.script +++ /dev/null @@ -1,125 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm3220g-eval/scripts/ld.script - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* The STM32F207IGH6U has 1024Kb of FLASH beginning at address 0x0800:0000 and - * 128Kb of SRAM. SRAM is split up into two blocks: - * - * 1) 112Kb of SRAM beginning at address 0x2000:0000 - * 2) 16Kb of SRAM beginning at address 0x2001:c000 - * - * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 - * where the code expects to begin execution by jumping to the entry point in - * the 0x0800:0000 address - * range. - */ - -MEMORY -{ - flash (rx) : ORIGIN = 0x08000000, LENGTH = 1024K - sram (rwx) : ORIGIN = 0x20000000, LENGTH = 112K -} - -OUTPUT_ARCH(arm) -EXTERN(_vectors) -ENTRY(_stext) -SECTIONS -{ - .text : { - _stext = ABSOLUTE(.); - *(.vectors) - *(.text .text.*) - *(.fixup) - *(.gnu.warning) - *(.rodata .rodata.*) - *(.gnu.linkonce.t.*) - *(.glue_7) - *(.glue_7t) - *(.got) - *(.gcc_except_table) - *(.gnu.linkonce.r.*) - _etext = ABSOLUTE(.); - } > flash - - .init_section : ALIGN(4) { - _sinit = ABSOLUTE(.); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) - KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) - _einit = ABSOLUTE(.); - } > flash - - .ARM.extab : ALIGN(4) { - *(.ARM.extab*) - } > flash - - .ARM.exidx : ALIGN(4) { - __exidx_start = ABSOLUTE(.); - *(.ARM.exidx*) - __exidx_end = ABSOLUTE(.); - } > flash - - .tdata : { - _stdata = ABSOLUTE(.); - *(.tdata .tdata.* .gnu.linkonce.td.*); - _etdata = ABSOLUTE(.); - } > flash - - .tbss : { - _stbss = ABSOLUTE(.); - *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); - _etbss = ABSOLUTE(.); - } > flash - - _eronly = ABSOLUTE(.); - - .data : ALIGN(4) { - _sdata = ABSOLUTE(.); - *(.data .data.*) - *(.gnu.linkonce.d.*) - CONSTRUCTORS - . = ALIGN(4); - _edata = ABSOLUTE(.); - } > sram AT > flash - - .bss : ALIGN(4) { - _sbss = ABSOLUTE(.); - *(.bss .bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - . = ALIGN(4); - _ebss = ABSOLUTE(.); - } > sram - - /* Stabs debugging sections. */ - - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_info 0 : { *(.debug_info) } - .debug_line 0 : { *(.debug_line) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_aranges 0 : { *(.debug_aranges) } -} diff --git a/boards/arm/stm32/stm3220g-eval/src/CMakeLists.txt b/boards/arm/stm32/stm3220g-eval/src/CMakeLists.txt deleted file mode 100644 index 7f0321dd1b8b0..0000000000000 --- a/boards/arm/stm32/stm3220g-eval/src/CMakeLists.txt +++ /dev/null @@ -1,69 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/stm3220g-eval/src/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -set(SRCS stm32_boot.c stm32_spi.c) - -if(CONFIG_ARCH_LEDS) - list(APPEND SRCS stm32_autoleds.c) -else() - list(APPEND SRCS stm32_userleds.c) -endif() - -if(CONFIG_ARCH_BUTTONS) - list(APPEND SRCS stm32_buttons.c) -endif() - -if(CONFIG_STM32_OTGFS) - list(APPEND SRCS stm32_usb.c) -endif() - -if(CONFIG_STM32_FSMC) - list( - APPEND - SRCS - stm32_lcd.c - stm32_selectlcd.c - stm32_deselectlcd.c - stm32_selectsram.c - stm32_deselectsram.c - stm32_extmem.c) -endif() - -if(CONFIG_ADC) - list(APPEND SRCS stm32_adc.c) -endif() - -if(CONFIG_PWM) - list(APPEND SRCS stm32_pwm.c) -endif() - -if(CONFIG_STM32_CAN_CHARDRIVER) - list(APPEND SRCS stm32_can.c) -endif() - -if(CONFIG_INPUT_STMPE811) - list(APPEND SRCS stm32_stmpe811.c) -endif() - -target_sources(board PRIVATE ${SRCS}) - -set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/ld.script") diff --git a/boards/arm/stm32/stm3220g-eval/src/Make.defs b/boards/arm/stm32/stm3220g-eval/src/Make.defs deleted file mode 100644 index e77785ac6fa58..0000000000000 --- a/boards/arm/stm32/stm3220g-eval/src/Make.defs +++ /dev/null @@ -1,63 +0,0 @@ -############################################################################ -# boards/arm/stm32/stm3220g-eval/src/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/Make.defs - -CSRCS = stm32_boot.c stm32_spi.c - -ifeq ($(CONFIG_ARCH_LEDS),y) -CSRCS += stm32_autoleds.c -else -CSRCS += stm32_userleds.c -endif - -ifeq ($(CONFIG_ARCH_BUTTONS),y) -CSRCS += stm32_buttons.c -endif - -ifeq ($(CONFIG_STM32_OTGFS),y) -CSRCS += stm32_usb.c -endif - -ifeq ($(CONFIG_STM32_FSMC),y) -CSRCS += stm32_lcd.c stm32_selectlcd.c stm32_deselectlcd.c stm32_selectsram.c stm32_deselectsram.c stm32_extmem.c -endif - -ifeq ($(CONFIG_ADC),y) -CSRCS += stm32_adc.c -endif - -ifeq ($(CONFIG_PWM),y) -CSRCS += stm32_pwm.c -endif - -ifeq ($(CONFIG_STM32_CAN_CHARDRIVER),y) -CSRCS += stm32_can.c -endif - -ifeq ($(CONFIG_INPUT_STMPE811),y) -CSRCS += stm32_stmpe811.c -endif - -DEPPATH += --dep-path board -VPATH += :board -CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/stm3220g-eval/src/stm32_adc.c b/boards/arm/stm32/stm3220g-eval/src/stm32_adc.c deleted file mode 100644 index d3bfcd0a171d3..0000000000000 --- a/boards/arm/stm32/stm3220g-eval/src/stm32_adc.c +++ /dev/null @@ -1,157 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm3220g-eval/src/stm32_adc.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32_pwm.h" -#include "stm3220g-eval.h" - -#ifdef CONFIG_ADC - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -/* Up to 3 ADC interfaces are supported */ - -#if STM32_NADC < 3 -# undef CONFIG_STM32_ADC3 -#endif - -#if STM32_NADC < 2 -# undef CONFIG_STM32_ADC2 -#endif - -#if STM32_NADC < 1 -# undef CONFIG_STM32_ADC1 -#endif - -#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) || defined(CONFIG_STM32_ADC3) -#ifndef CONFIG_STM32_ADC3 -# warning "Channel information only available for ADC3" -#endif - -/* The number of ADC channels in the conversion list */ - -#define ADC3_NCHANNELS 1 - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* The STM3220G-EVAL has a 10 Kohm potentiometer RV1 connected to PF9 of - * STM32F207IGH6 on the board: TIM14_CH1/FSMC_CD/ADC3_IN7 - */ - -/* Identifying number of each ADC channel: Variable Resistor. */ - -#ifdef CONFIG_STM32_ADC3 -static const uint8_t g_chanlist[ADC3_NCHANNELS] = -{ - 7 -}; - -/* Configurations of pins used byte each ADC channels */ - -static const uint32_t g_pinlist[ADC3_NCHANNELS] = -{ - GPIO_ADC3_IN7 -}; -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_adc_setup - * - * Description: - * Initialize ADC and register the ADC driver. - * - ****************************************************************************/ - -int stm32_adc_setup(void) -{ -#ifdef CONFIG_STM32_ADC3 - static bool initialized = false; - struct adc_dev_s *adc; - int ret; - int i; - - /* Check if we have already initialized */ - - if (!initialized) - { - /* Configure the pins as analog inputs for the selected channels */ - - for (i = 0; i < ADC3_NCHANNELS; i++) - { - stm32_configgpio(g_pinlist[i]); - } - - /* Call stm32_adcinitialize() to get an instance of the ADC interface */ - - adc = stm32_adcinitialize(3, g_chanlist, ADC3_NCHANNELS); - if (adc == NULL) - { - aerr("ERROR: Failed to get ADC interface\n"); - return -ENODEV; - } - - /* Register the ADC driver at "/dev/adc0" */ - - ret = adc_register("/dev/adc0", adc); - if (ret < 0) - { - aerr("ERROR: adc_register failed: %d\n", ret); - return ret; - } - - /* Now we are initialized */ - - initialized = true; - } - - return OK; -#else - return -ENOSYS; -#endif -} - -#endif /* CONFIG_STM32_ADC1 || CONFIG_STM32_ADC2 || CONFIG_STM32_ADC3 */ -#endif /* CONFIG_ADC */ diff --git a/boards/arm/stm32/stm3220g-eval/src/stm32_autoleds.c b/boards/arm/stm32/stm3220g-eval/src/stm32_autoleds.c deleted file mode 100644 index 2cd09b07a13c2..0000000000000 --- a/boards/arm/stm32/stm3220g-eval/src/stm32_autoleds.c +++ /dev/null @@ -1,232 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm3220g-eval/src/stm32_autoleds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32.h" -#include "stm3220g-eval.h" - -#ifdef CONFIG_ARCH_LEDS - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* The following definitions map the encoded LED setting to GPIO settings */ - -#define STM3210E_LED1 (1 << 0) -#define STM3210E_LED2 (1 << 1) -#define STM3210E_LED3 (1 << 2) -#define STM3210E_LED4 (1 << 3) - -#define ON_SETBITS_SHIFT (0) -#define ON_CLRBITS_SHIFT (4) -#define OFF_SETBITS_SHIFT (8) -#define OFF_CLRBITS_SHIFT (12) - -#define ON_BITS(v) ((v) & 0xff) -#define OFF_BITS(v) (((v) >> 8) & 0x0ff) -#define SETBITS(b) ((b) & 0x0f) -#define CLRBITS(b) (((b) >> 4) & 0x0f) - -#define ON_SETBITS(v) (SETBITS(ON_BITS(v)) -#define ON_CLRBITS(v) (CLRBITS(ON_BITS(v)) -#define OFF_SETBITS(v) (SETBITS(OFF_BITS(v)) -#define OFF_CLRBITS(v) (CLRBITS(OFF_BITS(v)) - -#define LED_STARTED_ON_SETBITS ((STM3210E_LED1) << ON_SETBITS_SHIFT) -#define LED_STARTED_ON_CLRBITS ((STM3210E_LED2|STM3210E_LED3|STM3210E_LED4) << ON_CLRBITS_SHIFT) -#define LED_STARTED_OFF_SETBITS (0 << OFF_SETBITS_SHIFT) -#define LED_STARTED_OFF_CLRBITS ((STM3210E_LED1|STM3210E_LED2|STM3210E_LED3|STM3210E_LED4) << OFF_CLRBITS_SHIFT) - -#define LED_HEAPALLOCATE_ON_SETBITS ((STM3210E_LED2) << ON_SETBITS_SHIFT) -#define LED_HEAPALLOCATE_ON_CLRBITS ((STM3210E_LED1|STM3210E_LED3|STM3210E_LED4) << ON_CLRBITS_SHIFT) -#define LED_HEAPALLOCATE_OFF_SETBITS ((STM3210E_LED1) << OFF_SETBITS_SHIFT) -#define LED_HEAPALLOCATE_OFF_CLRBITS ((STM3210E_LED2|STM3210E_LED3|STM3210E_LED4) << OFF_CLRBITS_SHIFT) - -#define LED_IRQSENABLED_ON_SETBITS ((STM3210E_LED1|STM3210E_LED2) << ON_SETBITS_SHIFT) -#define LED_IRQSENABLED_ON_CLRBITS ((STM3210E_LED3|STM3210E_LED4) << ON_CLRBITS_SHIFT) -#define LED_IRQSENABLED_OFF_SETBITS ((STM3210E_LED2) << OFF_SETBITS_SHIFT) -#define LED_IRQSENABLED_OFF_CLRBITS ((STM3210E_LED1|STM3210E_LED3|STM3210E_LED4) << OFF_CLRBITS_SHIFT) - -#define LED_STACKCREATED_ON_SETBITS ((STM3210E_LED3) << ON_SETBITS_SHIFT) -#define LED_STACKCREATED_ON_CLRBITS ((STM3210E_LED1|STM3210E_LED2|STM3210E_LED4) << ON_CLRBITS_SHIFT) -#define LED_STACKCREATED_OFF_SETBITS ((STM3210E_LED1|STM3210E_LED2) << OFF_SETBITS_SHIFT) -#define LED_STACKCREATED_OFF_CLRBITS ((STM3210E_LED3|STM3210E_LED4) << OFF_CLRBITS_SHIFT) - -#define LED_INIRQ_ON_SETBITS ((STM3210E_LED1) << ON_SETBITS_SHIFT) -#define LED_INIRQ_ON_CLRBITS ((0) << ON_CLRBITS_SHIFT) -#define LED_INIRQ_OFF_SETBITS ((0) << OFF_SETBITS_SHIFT) -#define LED_INIRQ_OFF_CLRBITS ((STM3210E_LED1) << OFF_CLRBITS_SHIFT) - -#define LED_SIGNAL_ON_SETBITS ((STM3210E_LED2) << ON_SETBITS_SHIFT) -#define LED_SIGNAL_ON_CLRBITS ((0) << ON_CLRBITS_SHIFT) -#define LED_SIGNAL_OFF_SETBITS ((0) << OFF_SETBITS_SHIFT) -#define LED_SIGNAL_OFF_CLRBITS ((STM3210E_LED2) << OFF_CLRBITS_SHIFT) - -#define LED_ASSERTION_ON_SETBITS ((STM3210E_LED4) << ON_SETBITS_SHIFT) -#define LED_ASSERTION_ON_CLRBITS ((0) << ON_CLRBITS_SHIFT) -#define LED_ASSERTION_OFF_SETBITS ((0) << OFF_SETBITS_SHIFT) -#define LED_ASSERTION_OFF_CLRBITS ((STM3210E_LED4) << OFF_CLRBITS_SHIFT) - -#define LED_PANIC_ON_SETBITS ((STM3210E_LED4) << ON_SETBITS_SHIFT) -#define LED_PANIC_ON_CLRBITS ((0) << ON_CLRBITS_SHIFT) -#define LED_PANIC_OFF_SETBITS ((0) << OFF_SETBITS_SHIFT) -#define LED_PANIC_OFF_CLRBITS ((STM3210E_LED4) << OFF_CLRBITS_SHIFT) - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -static const uint16_t g_ledbits[8] = -{ - (LED_STARTED_ON_SETBITS | LED_STARTED_ON_CLRBITS | - LED_STARTED_OFF_SETBITS | LED_STARTED_OFF_CLRBITS), - - (LED_HEAPALLOCATE_ON_SETBITS | LED_HEAPALLOCATE_ON_CLRBITS | - LED_HEAPALLOCATE_OFF_SETBITS | LED_HEAPALLOCATE_OFF_CLRBITS), - - (LED_IRQSENABLED_ON_SETBITS | LED_IRQSENABLED_ON_CLRBITS | - LED_IRQSENABLED_OFF_SETBITS | LED_IRQSENABLED_OFF_CLRBITS), - - (LED_STACKCREATED_ON_SETBITS | LED_STACKCREATED_ON_CLRBITS | - LED_STACKCREATED_OFF_SETBITS | LED_STACKCREATED_OFF_CLRBITS), - - (LED_INIRQ_ON_SETBITS | LED_INIRQ_ON_CLRBITS | - LED_INIRQ_OFF_SETBITS | LED_INIRQ_OFF_CLRBITS), - - (LED_SIGNAL_ON_SETBITS | LED_SIGNAL_ON_CLRBITS | - LED_SIGNAL_OFF_SETBITS | LED_SIGNAL_OFF_CLRBITS), - - (LED_ASSERTION_ON_SETBITS | LED_ASSERTION_ON_CLRBITS | - LED_ASSERTION_OFF_SETBITS | LED_ASSERTION_OFF_CLRBITS), - - (LED_PANIC_ON_SETBITS | LED_PANIC_ON_CLRBITS | - LED_PANIC_OFF_SETBITS | LED_PANIC_OFF_CLRBITS) -}; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -static inline void led_clrbits(unsigned int clrbits) -{ - if ((clrbits & STM3210E_LED1) != 0) - { - stm32_gpiowrite(GPIO_LED1, false); - } - - if ((clrbits & STM3210E_LED2) != 0) - { - stm32_gpiowrite(GPIO_LED2, false); - } - - if ((clrbits & STM3210E_LED3) != 0) - { - stm32_gpiowrite(GPIO_LED3, false); - } - - if ((clrbits & STM3210E_LED4) != 0) - { - stm32_gpiowrite(GPIO_LED4, false); - } -} - -static inline void led_setbits(unsigned int setbits) -{ - if ((setbits & STM3210E_LED1) != 0) - { - stm32_gpiowrite(GPIO_LED1, true); - } - - if ((setbits & STM3210E_LED2) != 0) - { - stm32_gpiowrite(GPIO_LED2, true); - } - - if ((setbits & STM3210E_LED3) != 0) - { - stm32_gpiowrite(GPIO_LED3, true); - } - - if ((setbits & STM3210E_LED4) != 0) - { - stm32_gpiowrite(GPIO_LED4, true); - } -} - -static void led_setonoff(unsigned int bits) -{ - led_clrbits(CLRBITS(bits)); - led_setbits(SETBITS(bits)); -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_autoled_initialize - ****************************************************************************/ - -void board_autoled_initialize(void) -{ - /* Configure LED1-4 GPIOs for output */ - - stm32_configgpio(GPIO_LED1); - stm32_configgpio(GPIO_LED2); - stm32_configgpio(GPIO_LED3); - stm32_configgpio(GPIO_LED4); -} - -/**************************************************************************** - * Name: board_autoled_on - ****************************************************************************/ - -void board_autoled_on(int led) -{ - led_setonoff(ON_BITS(g_ledbits[led])); -} - -/**************************************************************************** - * Name: board_autoled_off - ****************************************************************************/ - -void board_autoled_off(int led) -{ - led_setonoff(OFF_BITS(g_ledbits[led])); -} - -#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/stm3220g-eval/src/stm32_boot.c b/boards/arm/stm32/stm3220g-eval/src/stm32_boot.c deleted file mode 100644 index a3693105506b6..0000000000000 --- a/boards/arm/stm32/stm3220g-eval/src/stm32_boot.c +++ /dev/null @@ -1,368 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm3220g-eval/src/stm32_boot.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include -#include -#include - -#include -#include -#include - -#ifdef CONFIG_STM32_SPI1 -# include -# include -#endif - -#ifdef CONFIG_STM32_SDIO -# include -# include -#endif - -#ifdef CONFIG_STM32_OTGFS -# include "stm32_usbhost.h" -#endif - -#include "arm_internal.h" -#include "stm32.h" -#include "stm32_i2c.h" -#include "stm3220g-eval.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -/* For now, don't build in any SPI1 support -- NSH is not using it */ - -#undef CONFIG_STM32_SPI1 - -/* MMCSD PORT and SLOT number probably depend on the board configuration */ - -#define HAVE_USBDEV 1 -#define HAVE_MMCSD 1 -#define HAVE_USBHOST 1 - -#if defined(CONFIG_NSH_MMCSDSLOTNO) && CONFIG_NSH_MMCSDSLOTNO != 0 -# error "Only one MMC/SD slot" -# undef CONFIG_NSH_MMCSDSLOTNO -#endif - -#ifndef CONFIG_NSH_MMCSDSLOTNO -# define CONFIG_NSH_MMCSDSLOTNO 0 -#endif - -/* Can't support MMC/SD features if mountpoints are disabled or if SDIO - * support is not enabled. - */ - -#if defined(CONFIG_DISABLE_MOUNTPOINT) || !defined(CONFIG_STM32_SDIO) -# undef HAVE_MMCSD -#endif - -#ifndef CONFIG_NSH_MMCSDMINOR -# define CONFIG_NSH_MMCSDMINOR 0 -#endif - -/* Can't support USB host or device features if USB OTG FS is not enabled */ - -#ifndef CONFIG_STM32_OTGFS -# undef HAVE_USBDEV -# undef HAVE_USBHOST -#endif - -/* Can't support USB device is USB device is not enabled */ - -#ifndef CONFIG_USBDEV -# undef HAVE_USBDEV -#endif - -/* Can't support USB host is USB host is not enabled */ - -#ifndef CONFIG_USBHOST -# undef HAVE_USBHOST -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_i2c_register - * - * Description: - * Register one I2C drivers for the I2C tool. - * - ****************************************************************************/ - -#ifdef HAVE_I2CTOOL -static void stm32_i2c_register(int bus) -{ - struct i2c_master_s *i2c; - int ret; - - i2c = stm32_i2cbus_initialize(bus); - if (i2c == NULL) - { - _err("ERROR: Failed to get I2C%d interface\n", bus); - } - else - { - ret = i2c_register(i2c, bus); - if (ret < 0) - { - _err("ERROR: Failed to register I2C%d driver: %d\n", bus, ret); - stm32_i2cbus_uninitialize(i2c); - } - } -} -#endif - -/**************************************************************************** - * Name: stm32_i2ctool - * - * Description: - * Register I2C drivers for the I2C tool. - * - ****************************************************************************/ - -#ifdef HAVE_I2CTOOL -static void stm32_i2ctool(void) -{ -#ifdef CONFIG_STM32_I2C1 - stm32_i2c_register(1); -#endif -#ifdef CONFIG_STM32_I2C2 - stm32_i2c_register(2); -#endif -#ifdef CONFIG_STM32_I2C3 - stm32_i2c_register(3); -#endif -} -#else -# define stm32_i2ctool() -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_boardinitialize - * - * Description: - * All STM32 architectures must provide the following entry point. - * This entry point is called early in the initialization -- after all - * memory has been configured and mapped but before any devices have been - * initialized. - * - ****************************************************************************/ - -void stm32_boardinitialize(void) -{ - /* Configure SPI chip selects if 1) SPI is not disabled, and 2) the weak - * function stm32_spidev_initialize() has been brought into the link. - */ - -#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || defined(CONFIG_STM32_SPI3) - if (stm32_spidev_initialize) - { - stm32_spidev_initialize(); - } -#endif - - /* If the FSMC is enabled, then enable SRAM access */ - -#ifdef CONFIG_STM32_FSMC - stm32_selectsram(); -#endif - - /* Initialize USB if the 1) OTG FS controller is in the configuration and - * 2) the weak function stm32_usbinitialize() has been brought into the - * build. - * Presumably either CONFIG_USBDEV or CONFIG_USBHOST is also selected. - */ - -#ifdef CONFIG_STM32_OTGFS - if (stm32_usbinitialize) - { - stm32_usbinitialize(); - } -#endif - - /* Configure on-board LEDs if LED support has been selected. */ - -#ifdef CONFIG_ARCH_LEDS - board_autoled_initialize(); -#endif -} - -/**************************************************************************** - * Name: board_late_initialize - * - * Description: - * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional - * initialization call will be performed in the boot-up sequence to a - * function called board_late_initialize(). board_late_initialize() will be - * called immediately after up_initialize() is called and just before the - * initial application is started. This additional initialization phase - * may be used, for example, to initialize board-specific device drivers. - * - ****************************************************************************/ - -#ifdef CONFIG_BOARD_LATE_INITIALIZE -void board_late_initialize(void) -{ -#ifdef CONFIG_STM32_SPI1 - struct spi_dev_s *spi; - struct mtd_dev_s *mtd; -#endif -#ifdef HAVE_MMCSD - struct sdio_dev_s *sdio; -#endif - int ret; - - /* Register I2C drivers on behalf of the I2C tool */ - - stm32_i2ctool(); - - /* Configure SPI-based devices */ - -#ifdef CONFIG_STM32_SPI1 - /* Get the SPI port */ - - spi = stm32_spibus_initialize(1); - if (!spi) - { - syslog(LOG_ERR, "ERROR: Failed to initialize SPI port 0\n"); - return; - } - - /* Now bind the SPI interface to the M25P64/128 SPI FLASH driver */ - - mtd = m25p_initialize(spi); - if (!mtd) - { - syslog(LOG_ERR, - "ERROR: Failed to bind SPI port 0 to the SPI FLASH driver\n"); - return; - } - -#warning "Now what are we going to do with this SPI FLASH driver?" -#endif - - /* Mount the SDIO-based MMC/SD block driver */ - -#ifdef HAVE_MMCSD - /* First, get an instance of the SDIO interface */ - - sdio = sdio_initialize(CONFIG_NSH_MMCSDSLOTNO); - if (!sdio) - { - syslog(LOG_ERR, "ERROR: Failed to initialize SDIO slot %d\n", - CONFIG_NSH_MMCSDSLOTNO); - return; - } - - /* Now bind the SDIO interface to the MMC/SD driver */ - - ret = mmcsd_slotinitialize(CONFIG_NSH_MMCSDMINOR, sdio); - if (ret != OK) - { - syslog(LOG_ERR, - "ERROR: Failed to bind SDIO to the MMC/SD driver: %d\n", ret); - return; - } - - /* Then let's guess and say that there is a card in the slot. I need to - * check to see if the STM3220G-EVAL board supports a GPIO to detect if - * there is a card in the slot. - */ - - sdio_mediachange(sdio, true); -#endif - - /* Initialize USB host operation. stm32_usbhost_initialize() starts a - * thread will monitor for USB connection and disconnection events. - */ - -#ifdef HAVE_USBHOST - ret = stm32_usbhost_initialize(); - if (ret != OK) - { - syslog(LOG_ERR, "ERROR: Failed to initialize USB host: %d\n", ret); - return; - } -#endif - -#ifdef CONFIG_INPUT_STMPE811 - /* Initialize the touchscreen */ - - ret = stm32_tsc_setup(0); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_tsc_setup failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_PWM - /* Initialize PWM and register the PWM device. */ - - ret = stm32_pwm_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_pwm_setup() failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_ADC - /* Initialize ADC and register the ADC driver. */ - - ret = stm32_adc_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_adc_setup failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_STM32_CAN_CHARDRIVER - /* Initialize CAN and register the CAN driver. */ - - ret = stm32_can_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_can_setup failed: %d\n", ret); - } -#endif - - UNUSED(ret); -} -#endif diff --git a/boards/arm/stm32/stm3220g-eval/src/stm32_buttons.c b/boards/arm/stm32/stm3220g-eval/src/stm32_buttons.c deleted file mode 100644 index 8c177aa3ed484..0000000000000 --- a/boards/arm/stm32/stm3220g-eval/src/stm32_buttons.c +++ /dev/null @@ -1,156 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm3220g-eval/src/stm32_buttons.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include -#include - -#include "stm3220g-eval.h" - -#ifdef CONFIG_ARCH_BUTTONS - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* Pin configuration for each STM3210E-EVAL button. This array is indexed by - * the BUTTON_* and JOYSTICK_* definitions in board.h - */ - -static const uint32_t g_buttons[NUM_BUTTONS] = -{ - GPIO_BTN_WAKEUP, GPIO_BTN_TAMPER, GPIO_BTN_USER -}; - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_button_initialize - * - * Description: - * board_button_initialize() must be called to initialize button resources. - * After that, board_buttons() may be called to collect the current state - * of all buttons or board_button_irq() may be called to register button - * interrupt handlers. - * - ****************************************************************************/ - -uint32_t board_button_initialize(void) -{ - int i; - - /* Configure the GPIO pins as inputs. NOTE that EXTI interrupts are - * configured for all pins. - */ - - for (i = 0; i < NUM_BUTTONS; i++) - { - stm32_configgpio(g_buttons[i]); - } - - return NUM_BUTTONS; -} - -/**************************************************************************** - * Name: board_buttons - ****************************************************************************/ - -uint32_t board_buttons(void) -{ - uint32_t ret = 0; - int i; - - /* Check that state of each key */ - - for (i = 0; i < NUM_BUTTONS; i++) - { - /* A LOW value means that the key is pressed for most keys. - * The exception is the WAKEUP button. - */ - - bool released = stm32_gpioread(g_buttons[i]); - if (i == BUTTON_WAKEUP) - { - released = !released; - } - - /* Accumulate the set of depressed (not released) keys */ - - if (!released) - { - ret |= (1 << i); - } - } - - return ret; -} - -/**************************************************************************** - * Button support. - * - * Description: - * board_button_initialize() must be called to initialize button resources. - * After that, board_buttons() may be called to collect the current state - * of all buttons or board_button_irq() may be called to register button - * interrupt handlers. - * - * After board_button_initialize() has been called, board_buttons() may be - * called to collect the state of all buttons. board_buttons() returns an - * 32-bit bit set with each bit associated with a button. See the - * BUTTON_*_BIT definitions in board.h for the meaning of each bit. - * - * board_button_irq() may be called to register an interrupt handler that - * will be called when a button is depressed or released. The ID value is a - * button enumeration value that uniquely identifies a button resource. See - * the BUTTON_* definitions in board.h for the meaning of enumeration - * value. - * - ****************************************************************************/ - -#ifdef CONFIG_ARCH_IRQBUTTONS -int board_button_irq(int id, xcpt_t irqhandler, void *arg) -{ - int ret = -EINVAL; - - /* The following should be atomic */ - - if (id >= MIN_IRQBUTTON && id <= MAX_IRQBUTTON) - { - ret = stm32_gpiosetevent(g_buttons[id], true, true, true, - irqhandler, arg); - } - - return ret; -} -#endif -#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/stm32/stm3220g-eval/src/stm32_can.c b/boards/arm/stm32/stm3220g-eval/src/stm32_can.c deleted file mode 100644 index 0145c3b0a5180..0000000000000 --- a/boards/arm/stm32/stm3220g-eval/src/stm32_can.c +++ /dev/null @@ -1,102 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm3220g-eval/src/stm32_can.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32.h" -#include "stm32_can.h" -#include "stm3220g-eval.h" - -#ifdef CONFIG_CAN - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -#if defined(CONFIG_STM32_CAN1) && defined(CONFIG_STM32_CAN2) -# warning "Both CAN1 and CAN2 are enabled. Assuming only CAN1." -# undef CONFIG_STM32_CAN2 -#endif - -#ifdef CONFIG_STM32_CAN1 -# define CAN_PORT 1 -#else -# define CAN_PORT 2 -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_can_setup - * - * Description: - * Initialize CAN and register the CAN device - * - ****************************************************************************/ - -int stm32_can_setup(void) -{ -#if defined(CONFIG_STM32_CAN1) || defined(CONFIG_STM32_CAN2) - struct can_dev_s *can; - int ret; - - /* Call stm32_caninitialize() to get an instance of the CAN interface */ - - can = stm32_caninitialize(CAN_PORT); - if (can == NULL) - { - canerr("ERROR: Failed to get CAN interface\n"); - return -ENODEV; - } - - /* Register the CAN driver at "/dev/can0" */ - - ret = can_register("/dev/can0", can); - if (ret < 0) - { - canerr("ERROR: can_register failed: %d\n", ret); - return ret; - } - - return OK; -#else - return -ENODEV; -#endif -} - -#endif /* CONFIG_CAN */ diff --git a/boards/arm/stm32/stm3220g-eval/src/stm32_deselectlcd.c b/boards/arm/stm32/stm3220g-eval/src/stm32_deselectlcd.c deleted file mode 100644 index a6239db7ecf93..0000000000000 --- a/boards/arm/stm32/stm3220g-eval/src/stm32_deselectlcd.c +++ /dev/null @@ -1,80 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm3220g-eval/src/stm32_deselectlcd.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include "arm_internal.h" -#include "stm32.h" -#include "stm3220g-eval.h" - -#ifdef CONFIG_STM32_FSMC - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_deselectlcd - * - * Description: - * Disable the LCD - * - ****************************************************************************/ - -void stm32_deselectlcd(void) -{ - /* Restore registers to their power up settings */ - - putreg32(0xffffffff, STM32_FSMC_BCR4); - - /* Bank1 NOR/SRAM timing register configuration */ - - putreg32(0x0fffffff, STM32_FSMC_BTR4); - - /* Disable AHB clocking to the FSMC */ - - stm32_fsmc_disable(); -} - -#endif /* CONFIG_STM32_FSMC */ diff --git a/boards/arm/stm32/stm3220g-eval/src/stm32_deselectsram.c b/boards/arm/stm32/stm3220g-eval/src/stm32_deselectsram.c deleted file mode 100644 index 9c0696c984911..0000000000000 --- a/boards/arm/stm32/stm3220g-eval/src/stm32_deselectsram.c +++ /dev/null @@ -1,80 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm3220g-eval/src/stm32_deselectsram.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include "arm_internal.h" -#include "stm32.h" -#include "stm3220g-eval.h" - -#ifdef CONFIG_STM32_FSMC - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_deselectsram - * - * Description: - * Disable SRAM - * - ****************************************************************************/ - -void stm32_deselectsram(void) -{ - /* Restore registers to their power up settings */ - - putreg32(FSMC_BCR_RSTVALUE, STM32_FSMC_BCR2); - - /* Bank1 NOR/SRAM timing register configuration */ - - putreg32(FSMC_BTR_RSTVALUE, STM32_FSMC_BTR2); - - /* Disable AHB clocking to the FSMC */ - - stm32_fsmc_disable(); -} - -#endif /* CONFIG_STM32_FSMC */ diff --git a/boards/arm/stm32/stm3220g-eval/src/stm32_extmem.c b/boards/arm/stm32/stm3220g-eval/src/stm32_extmem.c deleted file mode 100644 index 1b61bc8e50235..0000000000000 --- a/boards/arm/stm32/stm3220g-eval/src/stm32_extmem.c +++ /dev/null @@ -1,141 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm3220g-eval/src/stm32_extmem.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32_gpio.h" -#include "stm32.h" -#include "stm3220g-eval.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#ifndef CONFIG_STM32_FSMC -# warning "FSMC is not enabled" -#endif - -#if STM32_NGPIO_PORTS < 6 -# error "Required GPIO ports not enabled" -#endif - -#define STM32_FSMC_NADDRCONFIGS 26 -#define STM32_FSMC_NDATACONFIGS 16 - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/* GPIO configurations common to most external memories */ - -static const uint32_t g_addressconfig[STM32_FSMC_NADDRCONFIGS] = -{ - GPIO_FSMC_A0, GPIO_FSMC_A1, GPIO_FSMC_A2, - GPIO_FSMC_A3, GPIO_FSMC_A4, GPIO_FSMC_A5, - GPIO_FSMC_A6, GPIO_FSMC_A7, GPIO_FSMC_A8, - GPIO_FSMC_A9, GPIO_FSMC_A10, GPIO_FSMC_A11, - GPIO_FSMC_A12, GPIO_FSMC_A13, GPIO_FSMC_A14, - GPIO_FSMC_A15, GPIO_FSMC_A16, GPIO_FSMC_A17, - GPIO_FSMC_A18, GPIO_FSMC_A19, GPIO_FSMC_A20, - GPIO_FSMC_A21, GPIO_FSMC_A22, GPIO_FSMC_A23, - GPIO_FSMC_A24, GPIO_FSMC_A25 -}; - -static const uint32_t g_dataconfig[STM32_FSMC_NDATACONFIGS] = -{ - GPIO_FSMC_D0, GPIO_FSMC_D1, GPIO_FSMC_D2, - GPIO_FSMC_D3, GPIO_FSMC_D4, GPIO_FSMC_D5, - GPIO_FSMC_D6, GPIO_FSMC_D7, GPIO_FSMC_D8, - GPIO_FSMC_D9, GPIO_FSMC_D10, GPIO_FSMC_D11, - GPIO_FSMC_D12, GPIO_FSMC_D13, GPIO_FSMC_D14, - GPIO_FSMC_D15 -}; - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_extmemgpios - * - * Description: - * Initialize GPIOs for external memory usage - * - ****************************************************************************/ - -void stm32_extmemgpios(const uint32_t *gpios, int ngpios) -{ - int i; - - /* Configure GPIOs */ - - for (i = 0; i < ngpios; i++) - { - stm32_configgpio(gpios[i]); - } -} - -/**************************************************************************** - * Name: stm32_extmemaddr - * - * Description: - * Initialize address line GPIOs for external memory access - * - ****************************************************************************/ - -void stm32_extmemaddr(int naddrs) -{ - stm32_extmemgpios(g_addressconfig, naddrs); -} - -/**************************************************************************** - * Name: stm32_extmemdata - * - * Description: - * Initialize data line GPIOs for external memory access - * - ****************************************************************************/ - -void stm32_extmemdata(int ndata) -{ - stm32_extmemgpios(g_dataconfig, ndata); -} diff --git a/boards/arm/stm32/stm3220g-eval/src/stm32_lcd.c b/boards/arm/stm32/stm3220g-eval/src/stm32_lcd.c deleted file mode 100644 index 2828d7eb76848..0000000000000 --- a/boards/arm/stm32/stm3220g-eval/src/stm32_lcd.c +++ /dev/null @@ -1,1186 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm3220g-eval/src/stm32_lcd.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* This driver supports the following LCDs on the STM324xG_EVAL board: - * - * AM-240320L8TNQW00H (LCD_ILI9320 or LCD_ILI9321) OR - * AM-240320D5TOQW01H (LCD_ILI9325) - */ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -#include - -#include "arm_internal.h" -#include "stm32.h" -#include "stm3220g-eval.h" - -#if !defined(CONFIG_STM32_ILI9320_DISABLE) || !defined(CONFIG_STM32_ILI9325_DISABLE) - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -/* CONFIG_STM32_ILI9320_DISABLE may be defined to disabled the - * AM-240320L8TNQW00H (LCD_ILI9320 or LCD_ILI9321) - * CONFIG_STM32_ILI9325_DISABLE may be defined to disabled the - * AM-240320D5TOQW01H (LCD_ILI9325) - */ - -/* Check contrast selection */ - -#if !defined(CONFIG_LCD_MAXCONTRAST) -# define CONFIG_LCD_MAXCONTRAST 1 -#endif - -/* Check power setting */ - -#if !defined(CONFIG_LCD_MAXPOWER) || CONFIG_LCD_MAXPOWER < 1 -# define CONFIG_LCD_MAXPOWER 1 -#endif - -#if CONFIG_LCD_MAXPOWER > 255 -# error "CONFIG_LCD_MAXPOWER must be less than 256 to fit in uint8_t" -#endif - -/* Check orientation */ - -#if defined(CONFIG_LCD_PORTRAIT) -# if defined(CONFIG_LCD_LANDSCAPE) || defined(CONFIG_LCD_RLANDSCAPE) || defined(CONFIG_LCD_RPORTRAIT) -# error "Cannot define both portrait and any other orientations" -# endif -#elif defined(CONFIG_LCD_RPORTRAIT) -# if defined(CONFIG_LCD_LANDSCAPE) || defined(CONFIG_LCD_RLANDSCAPE) -# error "Cannot define both rportrait and any other orientations" -# endif -#elif defined(CONFIG_LCD_LANDSCAPE) -# ifdef CONFIG_LCD_RLANDSCAPE -# error "Cannot define both landscape and any other orientations" -# endif -#elif !defined(CONFIG_LCD_RLANDSCAPE) -# define CONFIG_LCD_LANDSCAPE 1 -#endif - -/* Display/Color Properties *************************************************/ - -/* Display Resolution */ - -#if defined(CONFIG_LCD_LANDSCAPE) || defined(CONFIG_LCD_RLANDSCAPE) -# define STM3220G_XRES 320 -# define STM3220G_YRES 240 -#else -# define STM3220G_XRES 240 -# define STM3220G_YRES 320 -#endif - -/* Color depth and format */ - -#define STM3220G_BPP 16 -#define STM3220G_COLORFMT FB_FMT_RGB16_565 - -/* STM3220G-EVAL LCD Hardware Definitions ***********************************/ - -/* LCD /CS is CE4, Bank 3 of NOR/SRAM Bank 1~4 */ - -#define STM3220G_LCDBASE ((uintptr_t)(0x60000000 | 0x08000000)) -#define LCD ((struct lcd_regs_s *)STM3220G_LCDBASE) - -#define LCD_REG_0 0x00 -#define LCD_REG_1 0x01 -#define LCD_REG_2 0x02 -#define LCD_REG_3 0x03 -#define LCD_REG_4 0x04 -#define LCD_REG_5 0x05 -#define LCD_REG_6 0x06 -#define LCD_REG_7 0x07 -#define LCD_REG_8 0x08 -#define LCD_REG_9 0x09 -#define LCD_REG_10 0x0a -#define LCD_REG_12 0x0c -#define LCD_REG_13 0x0d -#define LCD_REG_14 0x0e -#define LCD_REG_15 0x0f -#define LCD_REG_16 0x10 -#define LCD_REG_17 0x11 -#define LCD_REG_18 0x12 -#define LCD_REG_19 0x13 -#define LCD_REG_20 0x14 -#define LCD_REG_21 0x15 -#define LCD_REG_22 0x16 -#define LCD_REG_23 0x17 -#define LCD_REG_24 0x18 -#define LCD_REG_25 0x19 -#define LCD_REG_26 0x1a -#define LCD_REG_27 0x1b -#define LCD_REG_28 0x1c -#define LCD_REG_29 0x1d -#define LCD_REG_30 0x1e -#define LCD_REG_31 0x1f -#define LCD_REG_32 0x20 -#define LCD_REG_33 0x21 -#define LCD_REG_34 0x22 -#define LCD_REG_36 0x24 -#define LCD_REG_37 0x25 -#define LCD_REG_40 0x28 -#define LCD_REG_41 0x29 -#define LCD_REG_43 0x2b -#define LCD_REG_45 0x2d -#define LCD_REG_48 0x30 -#define LCD_REG_49 0x31 -#define LCD_REG_50 0x32 -#define LCD_REG_51 0x33 -#define LCD_REG_52 0x34 -#define LCD_REG_53 0x35 -#define LCD_REG_54 0x36 -#define LCD_REG_55 0x37 -#define LCD_REG_56 0x38 -#define LCD_REG_57 0x39 -#define LCD_REG_58 0x3a -#define LCD_REG_59 0x3b -#define LCD_REG_60 0x3c -#define LCD_REG_61 0x3d -#define LCD_REG_62 0x3e -#define LCD_REG_63 0x3f -#define LCD_REG_64 0x40 -#define LCD_REG_65 0x41 -#define LCD_REG_66 0x42 -#define LCD_REG_67 0x43 -#define LCD_REG_68 0x44 -#define LCD_REG_69 0x45 -#define LCD_REG_70 0x46 -#define LCD_REG_71 0x47 -#define LCD_REG_72 0x48 -#define LCD_REG_73 0x49 -#define LCD_REG_74 0x4a -#define LCD_REG_75 0x4b -#define LCD_REG_76 0x4c -#define LCD_REG_77 0x4d -#define LCD_REG_78 0x4e -#define LCD_REG_79 0x4f -#define LCD_REG_80 0x50 -#define LCD_REG_81 0x51 -#define LCD_REG_82 0x52 -#define LCD_REG_83 0x53 -#define LCD_REG_96 0x60 -#define LCD_REG_97 0x61 -#define LCD_REG_106 0x6a -#define LCD_REG_118 0x76 -#define LCD_REG_128 0x80 -#define LCD_REG_129 0x81 -#define LCD_REG_130 0x82 -#define LCD_REG_131 0x83 -#define LCD_REG_132 0x84 -#define LCD_REG_133 0x85 -#define LCD_REG_134 0x86 -#define LCD_REG_135 0x87 -#define LCD_REG_136 0x88 -#define LCD_REG_137 0x89 -#define LCD_REG_139 0x8b -#define LCD_REG_140 0x8c -#define LCD_REG_141 0x8d -#define LCD_REG_143 0x8f -#define LCD_REG_144 0x90 -#define LCD_REG_145 0x91 -#define LCD_REG_146 0x92 -#define LCD_REG_147 0x93 -#define LCD_REG_148 0x94 -#define LCD_REG_149 0x95 -#define LCD_REG_150 0x96 -#define LCD_REG_151 0x97 -#define LCD_REG_152 0x98 -#define LCD_REG_153 0x99 -#define LCD_REG_154 0x9a -#define LCD_REG_157 0x9d -#define LCD_REG_164 0xa4 -#define LCD_REG_192 0xc0 -#define LCD_REG_193 0xc1 -#define LCD_REG_229 0xe5 - -/* LCD IDs */ - -#define ILI9320_ID 0x9320 -#define ILI9321_ID 0x9321 -#define ILI9325_ID 0x9325 - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/* LCD type */ - -enum lcd_type_e -{ - LCD_TYPE_UNKNOWN = 0, - LCD_TYPE_ILI9320, - LCD_TYPE_ILI9325 -}; - -/* This structure describes the LCD registers */ - -struct lcd_regs_s -{ - volatile uint16_t address; - volatile uint16_t value; -}; - -/* This structure describes the state of this driver */ - -struct stm3220g_dev_s -{ - /* Publicly visible device structure */ - - struct lcd_dev_s dev; - - /* Private LCD-specific information follows */ - - uint8_t type; /* LCD type. See enum lcd_type_e */ - uint8_t power; /* Current power setting */ -}; - -/**************************************************************************** - * Private Function Protototypes - ****************************************************************************/ - -/* Low Level LCD access */ - -static void stm3220g_writereg(uint8_t regaddr, uint16_t regval); -static uint16_t stm3220g_readreg(uint8_t regaddr); -static inline void stm3220g_gramselect(void); -static inline void stm3220g_writegram(uint16_t rgbval); -static void stm3220g_readnosetup(uint16_t *accum); -static uint16_t stm3220g_readnoshift(uint16_t *accum); -static void stm3220g_setcursor(uint16_t col, uint16_t row); - -/* LCD Data Transfer Methods */ - -static int stm3220g_putrun(struct lcd_dev_s *dev, - fb_coord_t row, fb_coord_t col, - const uint8_t *buffer, size_t npixels); -static int stm3220g_getrun(struct lcd_dev_s *dev, - fb_coord_t row, fb_coord_t col, - uint8_t *buffer, size_t npixels); - -/* LCD Configuration */ - -static int stm3220g_getvideoinfo(struct lcd_dev_s *dev, - struct fb_videoinfo_s *vinfo); -static int stm3220g_getplaneinfo(struct lcd_dev_s *dev, - unsigned int planeno, - struct lcd_planeinfo_s *pinfo); - -/* LCD RGB Mapping */ - -#ifdef CONFIG_FB_CMAP -# error "RGB color mapping not supported by this driver" -#endif - -/* Cursor Controls */ - -#ifdef CONFIG_FB_HWCURSOR -# error "Cursor control not supported by this driver" -#endif - -/* LCD Specific Controls */ - -static int stm3220g_getpower(struct lcd_dev_s *dev); -static int stm3220g_setpower(struct lcd_dev_s *dev, int power); -static int stm3220g_getcontrast(struct lcd_dev_s *dev); -static int stm3220g_setcontrast(struct lcd_dev_s *dev, - unsigned int contrast); - -/* Initialization */ - -static inline void stm3220g_lcdinitialize(void); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* This is working memory allocated by the LCD driver for each LCD device - * and for each color plane. This memory will hold one raster line of data. - * The size of the allocated run buffer must therefore be at least - * (bpp * xres / 8). Actual alignment of the buffer must conform to the - * bitwidth of the underlying pixel type. - * - * If there are multiple planes, they may share the same working buffer - * because different planes will not be operate on concurrently. However, - * if there are multiple LCD devices, they must each have unique run buffers. - */ - -static uint16_t g_runbuffer[STM3220G_XRES]; - -/* This structure describes the overall LCD video controller */ - -static const struct fb_videoinfo_s g_videoinfo = -{ - .fmt = STM3220G_COLORFMT, /* Color format: RGB16-565: RRRR RGGG GGGB BBBB */ - .xres = STM3220G_XRES, /* Horizontal resolution in pixel columns */ - .yres = STM3220G_YRES, /* Vertical resolution in pixel rows */ - .nplanes = 1, /* Number of color planes supported */ -}; - -/* This is the standard, NuttX Plane information object */ - -static const struct lcd_planeinfo_s g_planeinfo = -{ - .putrun = stm3220g_putrun, /* Put a run into LCD memory */ - .getrun = stm3220g_getrun, /* Get a run from LCD memory */ - .buffer = (uint8_t *)g_runbuffer, /* Run scratch buffer */ - .bpp = STM3220G_BPP, /* Bits-per-pixel */ -}; - -/* This is the standard, NuttX LCD driver object */ - -static struct stm3220g_dev_s g_lcddev = -{ - .dev = - { - /* LCD Configuration */ - - .getvideoinfo = stm3220g_getvideoinfo, - .getplaneinfo = stm3220g_getplaneinfo, - - /* LCD RGB Mapping -- Not supported */ - - /* Cursor Controls -- Not supported */ - - /* LCD Specific Controls */ - - .getpower = stm3220g_getpower, - .setpower = stm3220g_setpower, - .getcontrast = stm3220g_getcontrast, - .setcontrast = stm3220g_setcontrast, - }, -}; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm3220g_writereg - * - * Description: - * Write to an LCD register - * - ****************************************************************************/ - -static void stm3220g_writereg(uint8_t regaddr, uint16_t regval) -{ - /* Write the register address then write the register value */ - - LCD->address = regaddr; - LCD->value = regval; -} - -/**************************************************************************** - * Name: stm3220g_readreg - * - * Description: - * Read from an LCD register - * - ****************************************************************************/ - -static uint16_t stm3220g_readreg(uint8_t regaddr) -{ - /* Write the register address then read the register value */ - - LCD->address = regaddr; - return LCD->value; -} - -/**************************************************************************** - * Name: stm3220g_gramselect - * - * Description: - * Setup to read or write multiple pixels to the GRAM memory - * - ****************************************************************************/ - -static inline void stm3220g_gramselect(void) -{ - LCD->address = LCD_REG_34; -} - -/**************************************************************************** - * Name: stm3220g_writegram - * - * Description: - * Write one pixel to the GRAM memory - * - ****************************************************************************/ - -static inline void stm3220g_writegram(uint16_t rgbval) -{ - /* Write the value (GRAM register already selected) */ - - LCD->value = rgbval; -} - -/**************************************************************************** - * Name: stm3220g_readnosetup - * - * Description: - * Prime the operation by reading one pixel from the GRAM memory if - * necessary for this LCD type. When reading 16-bit gram data, there may - * be some shifts in the returned data: - * - * - ILI932x: Discard first dummy read; no shift in the return data - * - ****************************************************************************/ - -static void stm3220g_readnosetup(uint16_t *accum) -{ - /* Read-ahead one pixel */ - - *accum = LCD->value; -} - -/**************************************************************************** - * Name: stm3220g_readnoshift - * - * Description: - * Read one correctly aligned pixel from the GRAM memory. - * Possibly shifting the data and possibly swapping red and green - * components. - * - * - ILI932x: Unknown -- assuming colors are in the color order - * - ****************************************************************************/ - -static uint16_t stm3220g_readnoshift(uint16_t *accum) -{ - /* Read the value (GRAM register already selected) */ - - return LCD->value; -} - -/**************************************************************************** - * Name: stm3220g_setcursor - * - * Description: - * Set the cursor position. In landscape mode, the "column" is actually - * the physical Y position and the "row" is the physical X position. - * - ****************************************************************************/ - -static void stm3220g_setcursor(uint16_t col, uint16_t row) -{ - stm3220g_writereg(LCD_REG_32, row); /* GRAM horizontal address */ - stm3220g_writereg(LCD_REG_33, col); /* GRAM vertical address */ -} - -/**************************************************************************** - * Name: stm3220g_putrun - * - * Description: - * This method can be used to write a partial raster line to the LCD: - * - * dev - The LCD device - * row - Starting row to write to (range: 0 <= row < yres) - * col - Starting column to write to (range: 0 <= col <= xres-npixels) - * buffer - The buffer containing the run to be written to the LCD - * npixels - The number of pixels to write to the LCD - * (range: 0 < npixels <= xres-col) - * - ****************************************************************************/ - -static int stm3220g_putrun(struct lcd_dev_s *dev, - fb_coord_t row, fb_coord_t col, - const uint8_t *buffer, size_t npixels) -{ - const uint16_t *src = (const uint16_t *)buffer; - int i; - - /* Buffer must be provided and aligned to a 16-bit address boundary */ - - lcdinfo("row: %d col: %d npixels: %d\n", row, col, npixels); - DEBUGASSERT(buffer && ((uintptr_t)buffer & 1) == 0); - - /* Write the run to GRAM. */ - -#ifdef CONFIG_LCD_LANDSCAPE - /* Convert coordinates -- Here the edge away from the row of buttons on - * the STM3220G-EVAL is used as the top. - */ - - /* Write the GRAM data, manually incrementing X */ - - for (i = 0; i < npixels; i++) - { - /* Write the next pixel to this position */ - - stm3220g_setcursor(col, row); - stm3220g_gramselect(); - stm3220g_writegram(*src++); - - /* Increment to next column */ - - col++; - } -#elif defined(CONFIG_LCD_RLANDSCAPE) - /* Convert coordinates -- Here the edge next to the row of buttons on - * the STM3220G-EVAL is used as the top. - */ - - col = (STM3220G_XRES - 1) - col; - row = (STM3220G_YRES - 1) - row; - - /* Set the cursor position */ - - stm3220g_setcursor(col, row); - - /* Then write the GRAM data, auto-decrementing X */ - - stm3220g_gramselect(); - for (i = 0; i < npixels; i++) - { - /* Write the next pixel to this position - * (auto-decrements to the next column) - */ - - stm3220g_writegram(*src++); - } -#elif defined(CONFIG_LCD_PORTRAIT) - /* Convert coordinates. - * In this configuration, the top of the display is to the left - * of the buttons (if the board is held so that the buttons are at the - * bottom of the board). - */ - - col = (STM3220G_XRES - 1) - col; - - /* Then write the GRAM data, manually incrementing Y (which is col) */ - - for (i = 0; i < npixels; i++) - { - /* Write the next pixel to this position */ - - stm3220g_setcursor(row, col); - stm3220g_gramselect(); - stm3220g_writegram(*src++); - - /* Increment to next column */ - - col--; - } -#else /* CONFIG_LCD_RPORTRAIT */ - /* Convert coordinates. - * In this configuration, the top of the display is to the right of the - * buttons (if the board is held so that the buttons are at the bottom of - * the board). - */ - - row = (STM3220G_YRES - 1) - row; - - /* Then write the GRAM data, manually incrementing Y (which is col) */ - - for (i = 0; i < npixels; i++) - { - /* Write the next pixel to this position */ - - stm3220g_setcursor(row, col); - stm3220g_gramselect(); - stm3220g_writegram(*src++); - - /* Decrement to next column */ - - col++; - } -#endif - - return OK; -} - -/**************************************************************************** - * Name: stm3220g_getrun - * - * Description: - * This method can be used to read a partial raster line from the LCD: - * - * dev - The LCD device - * row - Starting row to read from (range: 0 <= row < yres) - * col - Starting column to read read (range: 0 <= col <= xres-npixels) - * buffer - The buffer in which to return the run read from the LCD - * npixels - The number of pixels to read from the LCD - * (range: 0 < npixels <= xres-col) - * - ****************************************************************************/ - -static int stm3220g_getrun(struct lcd_dev_s *dev, - fb_coord_t row, fb_coord_t col, - uint8_t *buffer, size_t npixels) -{ - uint16_t *dest = (uint16_t *)buffer; - void (*readsetup)(uint16_t *accum); - uint16_t (*readgram)(uint16_t *accum); - uint16_t accum; - int i; - - /* Buffer must be provided and aligned to a 16-bit address boundary */ - - lcdinfo("row: %d col: %d npixels: %d\n", row, col, npixels); - DEBUGASSERT(buffer && ((uintptr_t)buffer & 1) == 0); - - /* Configure according to the LCD type. - * Kind of silly with only one LCD type. - */ - - switch (g_lcddev.type) - { - case LCD_TYPE_ILI9320: - case LCD_TYPE_ILI9325: - readsetup = stm3220g_readnosetup; - readgram = stm3220g_readnoshift; - break; - - default: /* Shouldn't happen */ - return -ENOSYS; - } - - /* Read the run from GRAM. */ - -#ifdef CONFIG_LCD_LANDSCAPE - /* Convert coordinates -- Here the edge away from the row of buttons on - * the STM3220G-EVAL is used as the top. - */ - - for (i = 0; i < npixels; i++) - { - /* Read the next pixel from this position */ - - stm3220g_setcursor(row, col); - stm3220g_gramselect(); - readsetup(&accum); - *dest++ = readgram(&accum); - - /* Increment to next column */ - - col++; - } -#elif defined(CONFIG_LCD_RLANDSCAPE) - /* Convert coordinates -- Here the edge next to the row of buttons on - * the STM3220G-EVAL is used as the top. - */ - - col = (STM3220G_XRES - 1) - col; - row = (STM3220G_YRES - 1) - row; - - /* Set the cursor position */ - - stm3220g_setcursor(col, row); - - /* Then read the GRAM data, auto-decrementing Y */ - - stm3220g_gramselect(); - - /* Prime the pump for unaligned read data */ - - readsetup(&accum); - - for (i = 0; i < npixels; i++) - { - /* Read the next pixel from this position - * (autoincrements to the next row) - */ - - *dest++ = readgram(&accum); - } -#elif defined(CONFIG_LCD_PORTRAIT) - /* Convert coordinates. - * In this configuration, the top of the display is to the left - * of the buttons (if the board is held so that the buttons are - * at the bottom of the board). - */ - - col = (STM3220G_XRES - 1) - col; - - /* Then read the GRAM data, manually incrementing Y (which is col) */ - - for (i = 0; i < npixels; i++) - { - /* Read the next pixel from this position */ - - stm3220g_setcursor(row, col); - stm3220g_gramselect(); - readsetup(&accum); - *dest++ = readgram(&accum); - - /* Increment to next column */ - - col--; - } -#else /* CONFIG_LCD_RPORTRAIT */ - /* Convert coordinates. - * In this configuration, the top of the display is to the right - * of the buttons (if the board is held so that the buttons are - * at the bottom of the board). - */ - - row = (STM3220G_YRES - 1) - row; - - /* Then write the GRAM data, manually incrementing Y (which is col) */ - - for (i = 0; i < npixels; i++) - { - /* Write the next pixel to this position */ - - stm3220g_setcursor(row, col); - stm3220g_gramselect(); - readsetup(&accum); - *dest++ = readgram(&accum); - - /* Decrement to next column */ - - col++; - } -#endif - - return OK; -} - -/**************************************************************************** - * Name: stm3220g_getvideoinfo - * - * Description: - * Get information about the LCD video controller configuration. - * - ****************************************************************************/ - -static int stm3220g_getvideoinfo(struct lcd_dev_s *dev, - struct fb_videoinfo_s *vinfo) -{ - DEBUGASSERT(dev && vinfo); - lcdinfo("fmt: %d xres: %d yres: %d nplanes: %d\n", - g_videoinfo.fmt, g_videoinfo.xres, - g_videoinfo.yres, g_videoinfo.nplanes); - memcpy(vinfo, &g_videoinfo, sizeof(struct fb_videoinfo_s)); - return OK; -} - -/**************************************************************************** - * Name: stm3220g_getplaneinfo - * - * Description: - * Get information about the configuration of each LCD color plane. - * - ****************************************************************************/ - -static int stm3220g_getplaneinfo(struct lcd_dev_s *dev, - unsigned int planeno, - struct lcd_planeinfo_s *pinfo) -{ - DEBUGASSERT(dev && pinfo && planeno == 0); - lcdinfo("planeno: %d bpp: %d\n", planeno, g_planeinfo.bpp); - memcpy(pinfo, &g_planeinfo, sizeof(struct lcd_planeinfo_s)); - pinfo->dev = dev; - return OK; -} - -/**************************************************************************** - * Name: stm3220g_getpower - * - * Description: - * Get the LCD panel power status - * (0: full off - CONFIG_LCD_MAXPOWER: full on). On backlit LCDs, - * this setting may correspond to the backlight setting. - * - ****************************************************************************/ - -static int stm3220g_getpower(struct lcd_dev_s *dev) -{ - lcdinfo("power: %d\n", 0); - return g_lcddev.power; -} - -/**************************************************************************** - * Name: stm3220g_poweroff - * - * Description: - * Enable/disable LCD panel power - * (0: full off - CONFIG_LCD_MAXPOWER: full on). On backlit LCDs, - * this setting may correspond to the backlight setting. - * - ****************************************************************************/ - -static int stm3220g_poweroff(void) -{ - /* Turn the display off */ - - stm3220g_writereg(LCD_REG_7, 0); - - /* Remember the power off state */ - - g_lcddev.power = 0; - return OK; -} - -/**************************************************************************** - * Name: stm3220g_setpower - * - * Description: - * Enable/disable LCD panel power - * (0: full off - CONFIG_LCD_MAXPOWER: full on). On backlit LCDs, - * this setting may correspond to the backlight setting. - * - ****************************************************************************/ - -static int stm3220g_setpower(struct lcd_dev_s *dev, int power) -{ - lcdinfo("power: %d\n", power); - DEBUGASSERT((unsigned)power <= CONFIG_LCD_MAXPOWER); - - /* Set new power level */ - - if (power > 0) - { - /* Then turn the display on */ - -#if !defined(CONFIG_STM32_ILI9320_DISABLE) || !defined(CONFIG_STM32_ILI9325_DISABLE) - stm3220g_writereg(LCD_REG_7, 0x0173); -#endif - g_lcddev.power = power; - } - else - { - /* Turn the display off */ - - stm3220g_poweroff(); - } - - return OK; -} - -/**************************************************************************** - * Name: stm3220g_getcontrast - * - * Description: - * Get the current contrast setting (0-CONFIG_LCD_MAXCONTRAST). - * - ****************************************************************************/ - -static int stm3220g_getcontrast(struct lcd_dev_s *dev) -{ - lcdinfo("Not implemented\n"); - return -ENOSYS; -} - -/**************************************************************************** - * Name: stm3220g_setcontrast - * - * Description: - * Set LCD panel contrast (0-CONFIG_LCD_MAXCONTRAST). - * - ****************************************************************************/ - -static int stm3220g_setcontrast(struct lcd_dev_s *dev, unsigned int contrast) -{ - lcdinfo("contrast: %d\n", contrast); - return -ENOSYS; -} - -/**************************************************************************** - * Name: stm3220g_lcdinitialize - * - * Description: - * Set LCD panel contrast (0-CONFIG_LCD_MAXCONTRAST). - * - ****************************************************************************/ - -static inline void stm3220g_lcdinitialize(void) -{ - uint16_t id; - - /* Check LCD ID */ - - id = stm3220g_readreg(LCD_REG_0); - lcdinfo("LCD ID: %04x\n", id); - - /* Check if the ID is for the STM32_ILI9320 (or ILI9321) or STM32_ILI9325 */ - -#if !defined(CONFIG_STM32_ILI9320_DISABLE) && !defined(CONFIG_STM32_ILI9325_DISABLE) - if (id == ILI9320_ID || id == ILI9321_ID || id == ILI9325_ID) -#elif !defined(CONFIG_STM32_ILI9320_DISABLE) && defined(CONFIG_STM32_ILI9325_DISABLE) - if (id == ILI9320_ID || id == ILI9321_ID) -#else /* if defined(CONFIG_STM32_ILI9320_DISABLE) && !defined(CONFIG_STM32_ILI9325_DISABLE)) */ - if (id == ILI9325_ID) -#endif - { - /* Save the LCD type (not actually used at for anything important) */ - -#if !defined(CONFIG_STM32_ILI9320_DISABLE) -# if !defined(CONFIG_STM32_ILI9325_DISABLE) - if (id == ILI9325_ID) - { - g_lcddev.type = LCD_TYPE_ILI9325; - } - else -# endif - { - g_lcddev.type = LCD_TYPE_ILI9320; - stm3220g_writereg(LCD_REG_229, 0x8000); /* Set the internal vcore voltage */ - } -#else /* if !defined(CONFIG_STM32_ILI9325_DISABLE) */ - g_lcddev.type = LCD_TYPE_ILI9325; -#endif - lcdinfo("LCD type: %d\n", g_lcddev.type); - - /* Start Initial Sequence */ - - stm3220g_writereg(LCD_REG_0, 0x0001); /* Start internal OSC. */ - stm3220g_writereg(LCD_REG_1, 0x0100); /* Set SS and SM bit */ - stm3220g_writereg(LCD_REG_2, 0x0700); /* Set 1 line inversion */ - stm3220g_writereg(LCD_REG_3, 0x1030); /* Set GRAM write direction and BGR=1. */ - - /* stm3220g_writereg(LCD_REG_3, 0x1018); - * Set GRAM write direction and BGR=1. - */ - - stm3220g_writereg(LCD_REG_4, 0x0000); /* Resize register */ - stm3220g_writereg(LCD_REG_8, 0x0202); /* Set the back porch and front porch */ - stm3220g_writereg(LCD_REG_9, 0x0000); /* Set non-display area refresh cycle ISC[3:0] */ - stm3220g_writereg(LCD_REG_10, 0x0000); /* FMARK function */ - stm3220g_writereg(LCD_REG_12, 0x0000); /* RGB interface setting */ - stm3220g_writereg(LCD_REG_13, 0x0000); /* Frame marker Position */ - stm3220g_writereg(LCD_REG_15, 0x0000); /* RGB interface polarity */ - - /* Power On sequence */ - - stm3220g_writereg(LCD_REG_16, 0x0000); /* SAP, BT[3:0], AP, DSTB, SLP, STB */ - stm3220g_writereg(LCD_REG_17, 0x0000); /* DC1[2:0], DC0[2:0], VC[2:0] */ - stm3220g_writereg(LCD_REG_18, 0x0000); /* VREG1OUT voltage */ - stm3220g_writereg(LCD_REG_19, 0x0000); /* VDV[4:0] for VCOM amplitude */ - up_mdelay(200); /* Dis-charge capacitor power voltage (200ms) */ - - stm3220g_writereg(LCD_REG_16, 0x17b0); /* SAP, BT[3:0], AP, DSTB, SLP, STB */ - stm3220g_writereg(LCD_REG_17, 0x0137); /* DC1[2:0], DC0[2:0], VC[2:0] */ - up_mdelay(50); - - stm3220g_writereg(LCD_REG_18, 0x0139); /* VREG1OUT voltage */ - up_mdelay(50); - - stm3220g_writereg(LCD_REG_19, 0x1d00); /* VDV[4:0] for VCOM amplitude */ - stm3220g_writereg(LCD_REG_41, 0x0013); /* VCM[4:0] for VCOMH */ - up_mdelay(50); - - stm3220g_writereg(LCD_REG_32, 0x0000); /* GRAM horizontal Address */ - stm3220g_writereg(LCD_REG_33, 0x0000); /* GRAM Vertical Address */ - - /* Adjust the Gamma Curve (ILI9320/1) */ - -#if !defined(CONFIG_STM32_ILI9320_DISABLE) -# if !defined(CONFIG_STM32_ILI9325_DISABLE) - if (g_lcddev.type == LCD_TYPE_ILI9320) -# endif - { - stm3220g_writereg(LCD_REG_48, 0x0006); - stm3220g_writereg(LCD_REG_49, 0x0101); - stm3220g_writereg(LCD_REG_50, 0x0003); - stm3220g_writereg(LCD_REG_53, 0x0106); - stm3220g_writereg(LCD_REG_54, 0x0b02); - stm3220g_writereg(LCD_REG_55, 0x0302); - stm3220g_writereg(LCD_REG_56, 0x0707); - stm3220g_writereg(LCD_REG_57, 0x0007); - stm3220g_writereg(LCD_REG_60, 0x0600); - stm3220g_writereg(LCD_REG_61, 0x020b); - } -#endif - - /* Adjust the Gamma Curve (ILI9325) */ - -#if !defined(CONFIG_STM32_ILI9325_DISABLE) -# if !defined(CONFIG_STM32_ILI9320_DISABLE) - else -# endif - { - stm3220g_writereg(LCD_REG_48, 0x0007); - stm3220g_writereg(LCD_REG_49, 0x0302); - stm3220g_writereg(LCD_REG_50, 0x0105); - stm3220g_writereg(LCD_REG_53, 0x0206); - stm3220g_writereg(LCD_REG_54, 0x0808); - stm3220g_writereg(LCD_REG_55, 0x0206); - stm3220g_writereg(LCD_REG_56, 0x0504); - stm3220g_writereg(LCD_REG_57, 0x0007); - stm3220g_writereg(LCD_REG_60, 0x0105); - stm3220g_writereg(LCD_REG_61, 0x0808); - } -#endif - - /* Set GRAM area */ - - stm3220g_writereg(LCD_REG_80, 0x0000); /* Horizontal GRAM Start Address */ - stm3220g_writereg(LCD_REG_81, 0x00ef); /* Horizontal GRAM End Address */ - stm3220g_writereg(LCD_REG_82, 0x0000); /* Vertical GRAM Start Address */ - stm3220g_writereg(LCD_REG_83, 0x013f); /* Vertical GRAM End Address */ - stm3220g_writereg(LCD_REG_96, 0x2700); /* Gate Scan Line */ - - /* stm3220g_writereg(LCD_REG_96, 0xa700); - * Gate Scan Line(GS=1, scan direction is G320~G1) - */ - - stm3220g_writereg(LCD_REG_97, 0x0001); /* NDL,VLE, REV */ - stm3220g_writereg(LCD_REG_106, 0x0000); /* Set scrolling line */ - - /* Partial Display Control */ - - stm3220g_writereg(LCD_REG_128, 0x0000); - stm3220g_writereg(LCD_REG_129, 0x0000); - stm3220g_writereg(LCD_REG_130, 0x0000); - stm3220g_writereg(LCD_REG_131, 0x0000); - stm3220g_writereg(LCD_REG_132, 0x0000); - stm3220g_writereg(LCD_REG_133, 0x0000); - - /* Panel Control */ - - stm3220g_writereg(LCD_REG_144, 0x0010); - stm3220g_writereg(LCD_REG_146, 0x0000); - stm3220g_writereg(LCD_REG_147, 0x0003); - stm3220g_writereg(LCD_REG_149, 0x0110); - stm3220g_writereg(LCD_REG_151, 0x0000); - stm3220g_writereg(LCD_REG_152, 0x0000); - - /* Set GRAM write direction and BGR = 1 - * - * I/D=01 (Horizontal : increment, Vertical : decrement) - * AM=1 (address is updated in vertical writing direction) - */ - - stm3220g_writereg(LCD_REG_3, 0x1018); - stm3220g_writereg(LCD_REG_7, 0); /* Display off */ - } - else - { - lcderr("ERROR: Unsupported LCD type\n"); - } -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_lcd_initialize - * - * Description: - * Initialize the LCD video hardware. - * The initial state of the LCD is fully initialized, display memory - * cleared, and the LCD ready to use, but with the power setting at 0 - * (full off). - * - ****************************************************************************/ - -int board_lcd_initialize(void) -{ - lcdinfo("Initializing\n"); - - /* Configure GPIO pins and configure the FSMC to support the LCD */ - - stm32_selectlcd(); - - /* Configure and enable LCD */ - - up_mdelay(50); - stm3220g_lcdinitialize(); - - /* Clear the display (setting it to the color 0=black) */ - - stm3220g_lcdclear(0); - - /* Turn the display off */ - - stm3220g_poweroff(); - return OK; -} - -/**************************************************************************** - * Name: board_lcd_getdev - * - * Description: - * Return a a reference to the LCD object for the specified LCD. - * This allows support for multiple LCD devices. - * - ****************************************************************************/ - -struct lcd_dev_s *board_lcd_getdev(int lcddev) -{ - DEBUGASSERT(lcddev == 0); - return &g_lcddev.dev; -} - -/**************************************************************************** - * Name: board_lcd_uninitialize - * - * Description: - * Uninitialize the LCD support - * - ****************************************************************************/ - -void board_lcd_uninitialize(void) -{ - stm3220g_poweroff(); - stm32_deselectlcd(); -} - -/**************************************************************************** - * Name: stm3220g_lcdclear - * - * Description: - * This is a non-standard LCD interface just for the stm3220g-EVAL board. - * Because of the various rotations, clearing the display in the normal - * way by writing a sequences of runs that covers the entire display can - * be very slow. Here the display is cleared by simply setting all GRAM - * memory to the specified color. - * - ****************************************************************************/ - -void stm3220g_lcdclear(uint16_t color) -{ - uint32_t i = 0; - - stm3220g_setcursor(0, STM3220G_XRES - 1); - stm3220g_gramselect(); - for (i = 0; i < STM3220G_XRES * STM3220G_YRES; i++) - { - LCD->value = color; - } -} - -#endif /* !CONFIG_STM32_ILI9320_DISABLE || !CONFIG_STM32_ILI9325_DISABLE */ diff --git a/boards/arm/stm32/stm3220g-eval/src/stm32_pwm.c b/boards/arm/stm32/stm3220g-eval/src/stm32_pwm.c deleted file mode 100644 index 546c8335f2d74..0000000000000 --- a/boards/arm/stm32/stm3220g-eval/src/stm32_pwm.c +++ /dev/null @@ -1,105 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm3220g-eval/src/stm32_pwm.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include - -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32_pwm.h" -#include "stm3220g-eval.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -/* PWM - * - * The STM3220G-Eval has no real on-board PWM devices, but the board can be - * configured to output a pulse train using variously unused pins on the - * board for PWM output (see board.h for details of pins). - */ - -#ifdef CONFIG_PWM - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_pwm_setup - * - * Description: - * Initialize PWM and register the PWM device. - * - ****************************************************************************/ - -int stm32_pwm_setup(void) -{ - static bool initialized = false; - struct pwm_lowerhalf_s *pwm; - int ret; - - /* Have we already initialized? */ - - if (!initialized) - { - /* Call stm32_pwminitialize() to get an instance of the PWM interface */ - - pwm = stm32_pwminitialize(STM3220G_EVAL_PWMTIMER); - if (!pwm) - { - aerr("ERROR: Failed to get the STM32 PWM lower half\n"); - return -ENODEV; - } - - /* Register the PWM driver at "/dev/pwm0" */ - - ret = pwm_register("/dev/pwm0", pwm); - if (ret < 0) - { - aerr("ERROR: pwm_register failed: %d\n", ret); - return ret; - } - - /* Now we are initialized */ - - initialized = true; - } - - return OK; -} - -#endif /* CONFIG_PWM */ diff --git a/boards/arm/stm32/stm3220g-eval/src/stm32_selectlcd.c b/boards/arm/stm32/stm3220g-eval/src/stm32_selectlcd.c deleted file mode 100644 index 45603a50da54c..0000000000000 --- a/boards/arm/stm32/stm3220g-eval/src/stm32_selectlcd.c +++ /dev/null @@ -1,155 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm3220g-eval/src/stm32_selectlcd.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32.h" -#include -#include "stm3220g-eval.h" - -#ifdef CONFIG_STM32_FSMC - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#if STM32_NGPIO_PORTS < 6 -# error "Required GPIO ports not enabled" -#endif - -/* SRAM pin definitions */ - -#define LCD_NADDRLINES 1 -#define LCD_NDATALINES 16 - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* Pin Usage (per schematic) - * SRAM LCD - * D[0..15] [0..15] [0..15] - * A[0..25] [0..22] [0] RS - * FSMC_NBL0 PE0 OUT --- --- - * FSMC_NBL1 PE1 OUT --- --- - * FSMC_NE2 PG9 OUT --- --- - * FSMC_NE3 PG10 OUT --- ~CS - * FSMC_NE4 PG12 OUT --- --- - * FSMC_NWE PD5 OUT --- ~WR/SCL - * FSMC_NOE PD4 OUT --- ~RD - * FSMC_NWAIT PD6 IN --- --- - * FSMC_INT2 PG6* IN --- --- - * FSMC_INT3 - * FSMC_INTR - * FSMC_CD - * FSMC_CLK - * FSMC_NCE2 - * FSMC_NCE3 - * FSMC_NCE4_1 - * FSMC_NCE4_2 - * FSMC_NIORD - * FSMC_NIOWR - * FSMC_NL - * FSMC_NREG - */ - -/* GPIO configurations unique to the LCD */ - -static const uint32_t g_lcdconfig[] = -{ - /* NOE, NWE, and NE3 */ - - GPIO_FSMC_NOE, GPIO_FSMC_NWE, GPIO_FSMC_NE3 -}; -#define NLCD_CONFIG (sizeof(g_lcdconfig)/sizeof(uint32_t)) - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_selectlcd - * - * Description: - * Initialize to the LCD - * - ****************************************************************************/ - -void stm32_selectlcd(void) -{ - /* Configure new GPIO pins */ - - stm32_extmemaddr(LCD_NADDRLINES); /* Common address lines: A0 */ - stm32_extmemdata(LCD_NDATALINES); /* Common data lines: D0-D15 */ - stm32_extmemgpios(g_lcdconfig, NLCD_CONFIG); /* LCD-specific control lines */ - - /* Enable AHB clocking to the FSMC */ - - stm32_fsmc_enable(); - - /* Color LCD configuration (LCD configured as follow): - * - * - Data/Address MUX = Disable "FSMC_BCR_MUXEN" just not enable it. - * - Extended Mode = Disable "FSMC_BCR_EXTMOD" - * - Memory Type = SRAM "FSMC_BCR_SRAM" - * - Data Width = 16bit "FSMC_BCR_MWID16" - * - Write Operation = Enable "FSMC_BCR_WREN" - * - Asynchronous Wait = Disable - */ - - /* Bank3 NOR/SRAM control register configuration */ - - putreg32(FSMC_BCR_SRAM | FSMC_BCR_MWID16 | FSMC_BCR_WREN, STM32_FSMC_BCR3); - - /* Bank3 NOR/SRAM timing register configuration */ - - putreg32(FSMC_BTR_ADDSET(5) | FSMC_BTR_ADDHLD(1) | - FSMC_BTR_DATAST(9) | FSMC_BTR_BUSTURN(1) | - FSMC_BTR_CLKDIV(1) | FSMC_BTR_DATLAT(2) | - FSMC_BTR_ACCMODA, STM32_FSMC_BTR3); - - putreg32(0xffffffff, STM32_FSMC_BWTR3); - - /* Enable the bank by setting the MBKEN bit */ - - putreg32(FSMC_BCR_MBKEN | FSMC_BCR_SRAM | - FSMC_BCR_MWID16 | FSMC_BCR_WREN, STM32_FSMC_BCR3); -} - -#endif /* CONFIG_STM32_FSMC */ diff --git a/boards/arm/stm32/stm3220g-eval/src/stm32_selectsram.c b/boards/arm/stm32/stm3220g-eval/src/stm32_selectsram.c deleted file mode 100644 index 5c1553a1aa4f5..0000000000000 --- a/boards/arm/stm32/stm3220g-eval/src/stm32_selectsram.c +++ /dev/null @@ -1,186 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm3220g-eval/src/stm32_selectsram.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32.h" -#include -#include "stm3220g-eval.h" - -#ifdef CONFIG_STM32_FSMC - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#if STM32_NGPIO_PORTS < 6 -# error "Required GPIO ports not enabled" -#endif - -/* SRAM Timing */ - -#define SRAM_ADDRESS_SETUP_TIME 3 -#define SRAM_ADDRESS_HOLD_TIME 1 -#define SRAM_DATA_SETUP_TIME 6 -#define SRAM_BUS_TURNAROUND_DURATION 1 -#define SRAM_CLK_DIVISION 1 -#define SRAM_DATA_LATENCY 2 - -/* SRAM pin definitions */ - -#define SRAM_NADDRLINES 21 -#define SRAM_NDATALINES 16 - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* GPIOs Configuration ****************************************************** - * PD0 <-> FSMC_D2 PE0 <-> FSMC_NBL0 PF0 <-> FSMC_A0 PG0 <-> FSMC_A10 - * PD1 <-> FSMC_D3 PE1 <-> FSMC_NBL1 PF1 <-> FSMC_A1 PG1 <-> FSMC_A11 - * PD4 <-> FSMC_NOE PE3 <-> FSMC_A19 PF2 <-> FSMC_A2 PG2 <-> FSMC_A12 - * PD5 <-> FSMC_NWE PE4 <-> FSMC_A20 PF3 <-> FSMC_A3 PG3 <-> FSMC_A13 - * PD8 <-> FSMC_D13 PE7 <-> FSMC_D4 PF4 <-> FSMC_A4 PG4 <-> FSMC_A14 - * PD9 <-> FSMC_D14 PE8 <-> FSMC_D5 PF5 <-> FSMC_A5 PG5 <-> FSMC_A15 - * PD10 <-> FSMC_D15 PE9 <-> FSMC_D6 PF12 <-> FSMC_A6 PG9 <-> FSMC_NE2 - * PD11 <-> FSMC_A16 PE10 <-> FSMC_D7 PF13 <-> FSMC_A7 - * PD12 <-> FSMC_A17 PE11 <-> FSMC_D8 PF14 <-> FSMC_A8 - * PD13 <-> FSMC_A18 PE12 <-> FSMC_D9 PF15 <-> FSMC_A9 - * PD14 <-> FSMC_D0 PE13 <-> FSMC_D10 - * PD15 <-> FSMC_D1 PE14 <-> FSMC_D11 - * PE15 <-> FSMC_D12 - */ - -/* GPIO configurations unique to SRAM */ - -static const uint32_t g_sramconfig[] = -{ - /* NE3, NBL0, NBL1, */ - - GPIO_FSMC_NOE, GPIO_FSMC_NWE, GPIO_FSMC_NBL0, GPIO_FSMC_NBL1, GPIO_FSMC_NE2 -}; -#define NSRAM_CONFIG (sizeof(g_sramconfig)/sizeof(uint32_t)) - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_selectsram - * - * Description: - * Initialize to access external SRAM. SRAM will be visible at the FSMC - * Bank NOR/SRAM2 base address (0x64000000) - * - * General transaction rules. The requested AHB transaction data size can - * be 8-, 16- or 32-bit wide whereas the SRAM has a fixed 16-bit data - * width. Some simple transaction rules must be followed: - * - * Case 1: AHB transaction width and SRAM data width are equal - * There is no issue in this case. - * Case 2: AHB transaction size is greater than the memory size - * In this case, the FSMC splits the AHB transaction into smaller - * consecutive memory accesses in order to meet the external data width. - * Case 3: AHB transaction size is smaller than the memory size. - * SRAM supports the byte select feature. - * a) FSMC allows write transactions accessing the right data through its - * byte lanes (NBL[1:0]) - * b) Read transactions are allowed (the controller reads the entire - * memory word and uses the needed byte only). The NBL[1:0] are always - * kept low during read transactions. - * - ****************************************************************************/ - -void stm32_selectsram(void) -{ - /* Configure new GPIO pins */ - - stm32_extmemaddr(SRAM_NADDRLINES); /* Common address lines: A0-A20 */ - stm32_extmemdata(SRAM_NDATALINES); /* Common data lines: D0-D15 */ - stm32_extmemgpios(g_sramconfig, NSRAM_CONFIG); /* SRAM-specific control lines */ - - /* Enable AHB clocking to the FSMC */ - - stm32_fsmc_enable(); - - /* Bank1 NOR/SRAM control register configuration - * - * Bank enable : Not yet - * Data address mux : Disabled - * Memory Type : PSRAM - * Data bus width : 16-bits - * Flash access : Disabled - * Burst access mode : Disabled - * Polarity : Low - * Wrapped burst mode : Disabled - * Write timing : Before state - * Write enable : Yes - * Wait signal : Disabled - * Extended mode : Disabled - * Asynchronous wait : Disabled - * Write burst : Disabled - */ - - putreg32((FSMC_BCR_PSRAM | FSMC_BCR_MWID16 | - FSMC_BCR_WREN), STM32_FSMC_BCR2); - - /* Bank1 NOR/SRAM timing register configuration */ - - putreg32((FSMC_BTR_ADDSET(SRAM_ADDRESS_SETUP_TIME) | - FSMC_BTR_ADDHLD(SRAM_ADDRESS_HOLD_TIME) | - FSMC_BTR_DATAST(SRAM_DATA_SETUP_TIME) | - FSMC_BTR_BUSTURN(SRAM_BUS_TURNAROUND_DURATION) | - FSMC_BTR_CLKDIV(SRAM_CLK_DIVISION) | - FSMC_BTR_DATLAT(SRAM_DATA_LATENCY) | - FSMC_BTR_ACCMODA), - STM32_FSMC_BTR2); - - /* Bank1 NOR/SRAM timing register for write configuration, - * if extended mode is used - */ - - putreg32(0xffffffff, STM32_FSMC_BWTR2); /* Extended mode not used */ - - /* Enable the bank */ - - putreg32((FSMC_BCR_MBKEN | FSMC_BCR_PSRAM | - FSMC_BCR_MWID16 | FSMC_BCR_WREN), STM32_FSMC_BCR2); -} - -#endif /* CONFIG_STM32_FSMC */ diff --git a/boards/arm/stm32/stm3220g-eval/src/stm32_spi.c b/boards/arm/stm32/stm3220g-eval/src/stm32_spi.c deleted file mode 100644 index 5d99e643455bc..0000000000000 --- a/boards/arm/stm32/stm3220g-eval/src/stm32_spi.c +++ /dev/null @@ -1,130 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm3220g-eval/src/stm32_spi.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include "arm_internal.h" -#include "chip.h" -#include "stm32.h" -#include "stm3220g-eval.h" - -#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || defined(CONFIG_STM32_SPI3) - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_spidev_initialize - * - * Description: - * Called to configure SPI chip select GPIO pins for the STM3220G-EVAL - * board. - * - ****************************************************************************/ - -void weak_function stm32_spidev_initialize(void) -{ -#warning "Missing logic" -} - -/**************************************************************************** - * Name: stm32_spi1/2/3select and stm32_spi1/2/3status - * - * Description: - * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status - * must be provided by board-specific logic. They are implementations of - * the select and status methods of the SPI interface defined by struct - * spi_ops_s (see include/nuttx/spi/spi.h). All other methods - * (including stm32_spibus_initialize()) are provided by common STM32 - * logic. - * To use this common SPI logic on your board: - * - * 1. Provide logic in stm32_boardinitialize() to configure SPI chip select - * pins. - * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() functions - * in your board-specific logic. These functions will perform chip - * selection and status operations using GPIOs in the way your board is - * configured. - * 3. Add a calls to stm32_spibus_initialize() in your low level - * application initialization logic - * 4. The handle returned by stm32_spibus_initialize() may then be used to - * bind the SPI driver to higher level logic (e.g., calling - * mmcsd_spislotinitialize(), for example, will bind the SPI driver to - * the SPI MMC/SD driver). - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_SPI1 -void stm32_spi1select(struct spi_dev_s *dev, - uint32_t devid, bool selected) -{ - spiinfo("devid: %d CS: %s\n", - (int)devid, selected ? "assert" : "de-assert"); -} - -uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) -{ - return SPI_STATUS_PRESENT; -} -#endif - -#ifdef CONFIG_STM32_SPI2 -void stm32_spi2select(struct spi_dev_s *dev, - uint32_t devid, bool selected) -{ - spiinfo("devid: %d CS: %s\n", - (int)devid, selected ? "assert" : "de-assert"); -} - -uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) -{ - return SPI_STATUS_PRESENT; -} -#endif - -#ifdef CONFIG_STM32_SPI3 -void stm32_spi3select(struct spi_dev_s *dev, - uint32_t devid, bool selected) -{ - spiinfo("devid: %d CS: %s\n", - (int)devid, selected ? "assert" : "de-assert"); -} - -uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid) -{ - return SPI_STATUS_PRESENT; -} -#endif - -#endif /* CONFIG_STM32_SPI1 || CONFIG_STM32_SPI2 */ diff --git a/boards/arm/stm32/stm3220g-eval/src/stm32_stmpe811.c b/boards/arm/stm32/stm3220g-eval/src/stm32_stmpe811.c deleted file mode 100644 index 190e897501de7..0000000000000 --- a/boards/arm/stm32/stm3220g-eval/src/stm32_stmpe811.c +++ /dev/null @@ -1,337 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm3220g-eval/src/stm32_stmpe811.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -#include - -#include "stm32.h" -#include "stm3220g-eval.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -#ifdef CONFIG_INPUT_STMPE811 -#ifndef CONFIG_INPUT -# error "STMPE811 support requires CONFIG_INPUT" -#endif - -#ifndef CONFIG_STM32_I2C1 -# error "STMPE811 support requires CONFIG_STM32_I2C1" -#endif - -#ifndef CONFIG_STMPE811_I2C -# error "Only the STMPE811 I2C interface is supported" -#endif - -#ifdef CONFIG_STMPE811_SPI -# error "Only the STMPE811 SPI interface is supported" -#endif - -#ifndef CONFIG_STMPE811_FREQUENCY -# define CONFIG_STMPE811_FREQUENCY 100000 -#endif - -#ifndef CONFIG_STMPE811_I2CDEV -# define CONFIG_STMPE811_I2CDEV 1 -#endif - -#if CONFIG_STMPE811_I2CDEV != 1 -# error "CONFIG_STMPE811_I2CDEV must be one" -#endif - -#ifndef CONFIG_STMPE811_DEVMINOR -# define CONFIG_STMPE811_DEVMINOR 0 -#endif - -/* Board definitions ********************************************************/ - -/* The STM3220G-EVAL has two STMPE811QTR I/O expanders on board both - * connected to the STM32 via I2C1. They share a common interrupt line: PI2. - * - * STMPE811 U24, I2C address 0x41 (7-bit) - * ------ ---- ---------------- -------------------------------------------- - * STPE11 PIN BOARD SIGNAL BOARD CONNECTION - * ------ ---- ---------------- -------------------------------------------- - * Y- TouchScreen_Y- LCD Connector XL - * X- TouchScreen_X- LCD Connector XR - * Y+ TouchScreen_Y+ LCD Connector XD - * X+ TouchScreen_X+ LCD Connector XU - * IN3 EXP_IO9 - * IN2 EXP_IO10 - * IN1 EXP_IO11 - * IN0 EXP_IO12 - * - * STMPE811 U29, I2C address 0x44 (7-bit) - * ------ ---- ---------------- -------------------------------------------- - * STPE11 PIN BOARD SIGNAL BOARD CONNECTION - * ------ ---- ---------------- -------------------------------------------- - * Y- EXP_IO1 - * X- EXP_IO2 - * Y+ EXP_IO3 - * X+ EXP_IO4 - * IN3 EXP_IO5 - * IN2 EXP_IO6 - * IN1 EXP_IO7 - * IN0 EXP_IO8 - */ - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -struct stm32_stmpe811config_s -{ - /* Configuration structure as seen by the STMPE811 driver */ - - struct stmpe811_config_s config; - - /* Additional private definitions only known to this driver */ - - STMPE811_HANDLE handle; /* The STMPE811 driver handle */ - xcpt_t handler; /* The STMPE811 interrupt handler */ - void *arg; /* Interrupt handler argument */ -}; - -/**************************************************************************** - * Static Function Prototypes - ****************************************************************************/ - -/* IRQ/GPIO access callbacks. These operations all hidden behind callbacks - * to isolate the STMPE811 driver from differences in GPIO - * interrupt handling by varying boards and MCUs.* so that contact and loss- - * of-contact events can be detected. - * - * attach - Attach the STMPE811 interrupt handler to the GPIO interrupt - * enable - Enable or disable the GPIO interrupt - * clear - Acknowledge/clear any pending GPIO interrupt - */ - -static int stmpe811_attach(struct stmpe811_config_s *state, xcpt_t isr, - void *arg); -static void stmpe811_enable(struct stmpe811_config_s *state, - bool enable); -static void stmpe811_clear(struct stmpe811_config_s *state); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* A reference to a structure of this type must be passed to the STMPE811 - * driver. This structure provides information about the configuration - * of the STMPE811 and provides some board-specific hooks. - * - * Memory for this structure is provided by the caller. It is not copied - * by the driver and is presumed to persist while the driver is active. The - * memory must be writable because, under certain circumstances, the driver - * may modify frequency or X plate resistance values. - */ - -#ifndef CONFIG_STMPE811_TSC_DISABLE -static struct stm32_stmpe811config_s g_stmpe811config = -{ - .config = - { -#ifdef CONFIG_STMPE811_I2C - .address = STMPE811_ADDR1, -#endif - .frequency = CONFIG_STMPE811_FREQUENCY, - -#ifdef CONFIG_STMPE811_MULTIPLE - .irq = STM32_IRQ_EXTI2, -#endif - .ctrl1 = (ADC_CTRL1_SAMPLE_TIME_80 | ADC_CTRL1_MOD_12B), - .ctrl2 = ADC_CTRL2_ADC_FREQ_3p25, - - .attach = stmpe811_attach, - .enable = stmpe811_enable, - .clear = stmpe811_clear, - }, - .handler = NULL, - .arg = NULL, -}; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/* IRQ/GPIO access callbacks. These operations all hidden behind - * callbacks to isolate the STMPE811 driver from differences in GPIO - * interrupt handling by varying boards and MCUs. - * - * attach - Attach the STMPE811 interrupt handler to the GPIO interrupt - * enable - Enable or disable the GPIO interrupt - * clear - Acknowledge/clear any pending GPIO interrupt - */ - -static int stmpe811_attach(struct stmpe811_config_s *state, xcpt_t isr, - void *arg) -{ - struct stm32_stmpe811config_s *priv = - (struct stm32_stmpe811config_s *)state; - - iinfo("Saving handler %p\n", isr); - DEBUGASSERT(priv); - - /* Just save the handler. We will use it when EXTI interruptsare enabled */ - - priv->handler = isr; - priv->arg = arg; - return OK; -} - -static void stmpe811_enable(struct stmpe811_config_s *state, bool enable) -{ - struct stm32_stmpe811config_s *priv = - (struct stm32_stmpe811config_s *)state; - irqstate_t flags; - - /* Attach and enable, or detach and disable. Enabling and disabling GPIO - * interrupts is a multi-step process so the safest thing is to keep - * interrupts disabled during the reconfiguration. - */ - - flags = enter_critical_section(); - if (enable) - { - /* Configure the EXTI interrupt using the SAVED handler */ - - stm32_gpiosetevent(GPIO_IO_EXPANDER, true, true, true, - priv->handler, priv->arg); - } - else - { - /* Configure the EXTI interrupt with a NULL handler to disable it */ - - stm32_gpiosetevent(GPIO_IO_EXPANDER, false, false, false, - NULL, NULL); - } - - leave_critical_section(flags); -} - -static void stmpe811_clear(struct stmpe811_config_s *state) -{ - /* Does nothing */ -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_tsc_setup - * - * Description: - * This function is called by board-bringup logic to configure the - * touchscreen device. This function will register the driver as - * /dev/inputN where N is the minor device number. - * - * Input Parameters: - * minor - The input device minor number - * - * Returned Value: - * Zero is returned on success. Otherwise, a negated errno value is - * returned to indicate the nature of the failure. - * - ****************************************************************************/ - -int stm32_tsc_setup(int minor) -{ -#ifndef CONFIG_STMPE811_TSC_DISABLE - struct i2c_master_s *dev; - int ret; - - iinfo("minor %d\n", minor); - DEBUGASSERT(minor == 0); - - /* Check if we are already initialized */ - - if (!g_stmpe811config.handle) - { - iinfo("Initializing\n"); - - /* Configure the STMPE811 interrupt pin as an input */ - - stm32_configgpio(GPIO_IO_EXPANDER); - - /* Get an instance of the I2C interface */ - - dev = stm32_i2cbus_initialize(CONFIG_STMPE811_I2CDEV); - if (!dev) - { - ierr("ERROR: Failed to initialize I2C bus %d\n", - CONFIG_STMPE811_I2CDEV); - return -ENODEV; - } - - /* Instantiate the STMPE811 driver */ - - g_stmpe811config.handle = - stmpe811_instantiate(dev, - (struct stmpe811_config_s *)&g_stmpe811config); - if (!g_stmpe811config.handle) - { - ierr("ERROR: Failed to instantiate the STMPE811 driver\n"); - return -ENODEV; - } - - /* Initialize and register the I2C touchscreen device */ - - ret = stmpe811_register(g_stmpe811config.handle, - CONFIG_STMPE811_DEVMINOR); - if (ret < 0) - { - ierr("ERROR: Failed to register STMPE driver: %d\n", ret); - - /* stm32_i2cbus_uninitialize(dev); */ - - return -ENODEV; - } - } - - return OK; -#else - return -ENOSYS; -#endif -} - -#endif /* CONFIG_INPUT_STMPE811 */ diff --git a/boards/arm/stm32/stm3220g-eval/src/stm32_usb.c b/boards/arm/stm32/stm3220g-eval/src/stm32_usb.c deleted file mode 100644 index 3252daf95d926..0000000000000 --- a/boards/arm/stm32/stm3220g-eval/src/stm32_usb.c +++ /dev/null @@ -1,304 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm3220g-eval/src/stm32_usb.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -#include "arm_internal.h" -#include "stm32.h" -#include "stm32_otgfs.h" -#include "stm3220g-eval.h" - -#ifdef CONFIG_STM32_OTGFS - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#if defined(CONFIG_USBDEV) || defined(CONFIG_USBHOST) -# define HAVE_USB 1 -#else -# warning "CONFIG_STM32_OTGFS is enabled but neither CONFIG_USBDEV nor CONFIG_USBHOST" -# undef HAVE_USB -#endif - -#ifndef CONFIG_USBHOST_DEFPRIO -# define CONFIG_USBHOST_DEFPRIO 50 -#endif - -#ifndef CONFIG_USBHOST_STACKSIZE -# ifdef CONFIG_USBHOST_HUB -# define CONFIG_USBHOST_STACKSIZE 1536 -# else -# define CONFIG_USBHOST_STACKSIZE 1024 -# endif -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -#ifdef CONFIG_USBHOST -static struct usbhost_connection_s *g_usbconn; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: usbhost_waiter - * - * Description: - * Wait for USB devices to be connected. - * - ****************************************************************************/ - -#ifdef CONFIG_USBHOST -static int usbhost_waiter(int argc, char *argv[]) -{ - struct usbhost_hubport_s *hport; - - uinfo("Running\n"); - for (; ; ) - { - /* Wait for the device to change state */ - - DEBUGVERIFY(CONN_WAIT(g_usbconn, &hport)); - uinfo("%s\n", hport->connected ? "connected" : "disconnected"); - - /* Did we just become connected? */ - - if (hport->connected) - { - /* Yes.. enumerate the newly connected device */ - - CONN_ENUMERATE(g_usbconn, hport); - } - } - - /* Keep the compiler from complaining */ - - return 0; -} -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_usbinitialize - * - * Description: - * Called from stm32_usbinitialize very early in initialization to setup - * USB-related GPIO pins for the STM3220G-EVAL board. - * - ****************************************************************************/ - -void stm32_usbinitialize(void) -{ -#ifdef HAVE_USB - /* The OTG FS has an internal soft pull-up. - * No GPIO configuration is required - */ - - /* Configure the OTG FS VBUS sensing GPIO, - * Power On, and Overcurrent GPIOs - */ - - stm32_configgpio(GPIO_OTGFS_VBUS); - stm32_configgpio(GPIO_OTGFS_PWRON); - stm32_configgpio(GPIO_OTGFS_OVER); -#endif -} - -/**************************************************************************** - * Name: stm32_usbhost_initialize - * - * Description: - * Called at application startup time to initialize the USB host - * functionality. - * This function will start a thread that will monitor for device - * connection/disconnection events. - * - ****************************************************************************/ - -#ifdef CONFIG_USBHOST -int stm32_usbhost_initialize(void) -{ - int ret; - - /* First, register all of the class drivers needed to support the drivers - * that we care about: - */ - - uinfo("Register class drivers\n"); - -#ifdef CONFIG_USBHOST_MSC - /* Register the USB mass storage class class */ - - ret = usbhost_msc_initialize(); - if (ret != OK) - { - uerr("ERROR: Failed to register the mass storage class: %d\n", ret); - } -#endif - -#ifdef CONFIG_USBHOST_CDCACM - /* Register the CDC/ACM serial class */ - - ret = usbhost_cdcacm_initialize(); - if (ret != OK) - { - uerr("ERROR: Failed to register the CDC/ACM serial class: %d\n", ret); - } -#endif - - /* Then get an instance of the USB host interface */ - - uinfo("Initialize USB host\n"); - g_usbconn = stm32_otgfshost_initialize(0); - if (g_usbconn) - { - /* Start a thread to handle device connection. */ - - uinfo("Start usbhost_waiter\n"); - - ret = kthread_create("usbhost", CONFIG_USBHOST_DEFPRIO, - CONFIG_USBHOST_STACKSIZE, - usbhost_waiter, NULL); - return ret < 0 ? -ENOEXEC : OK; - } - - return -ENODEV; -} -#endif - -/**************************************************************************** - * Name: stm32_usbhost_vbusdrive - * - * Description: - * Enable/disable driving of VBUS 5V output. This function must be - * provided be each platform that implements the STM32 OTG FS host - * interface - * - * "On-chip 5 V VBUS generation is not supported. For this reason, a - * charge pump or, if 5 V are available on the application board, a - * basic power switch, must be added externally to drive the 5 V VBUS - * line. The external charge pump can be driven by any GPIO output. - * When the application decides to power on VBUS using the chosen GPIO, - * it must also set the port power bit in the host port control and - * status register (PPWR bit in OTG_FS_HPRT). - * - * "The application uses this field to control power to this port, - * and the core clears this bit on an overcurrent condition." - * - * Input Parameters: - * iface - For future growth to handle multiple USB host interface. - * Should be zero. - * enable - true: enable VBUS power; false: disable VBUS power - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef CONFIG_USBHOST -void stm32_usbhost_vbusdrive(int iface, bool enable) -{ - DEBUGASSERT(iface == 0); - - if (enable) - { - /* Enable the Power Switch by driving the enable pin low */ - - stm32_gpiowrite(GPIO_OTGFS_PWRON, false); - } - else - { - /* Disable the Power Switch by driving the enable pin high */ - - stm32_gpiowrite(GPIO_OTGFS_PWRON, true); - } -} -#endif - -/**************************************************************************** - * Name: stm32_setup_overcurrent - * - * Description: - * Setup to receive an interrupt-level callback if an overcurrent - * condition is detected. - * - * Input Parameters: - * handler - New overcurrent interrupt handler - * arg - The argument provided for the interrupt handler - * - * Returned Value: - * Zero (OK) is returned on success. Otherwise, a negated errno value - * is returned to indicate the nature of the failure. - * - ****************************************************************************/ - -#ifdef CONFIG_USBHOST -int stm32_setup_overcurrent(xcpt_t handler, void *arg) -{ - return stm32_gpiosetevent(GPIO_OTGFS_OVER, true, true, true, handler, arg); -} -#endif - -/**************************************************************************** - * Name: stm32_usbsuspend - * - * Description: - * Board logic must provide the stm32_usbsuspend logic if the USBDEV - * driver is used. This function is called whenever the USB enters or - * leaves suspend mode. This is an opportunity for the board logic to - * shutdown clocks, power, etc. while the USB is suspended. - * - ****************************************************************************/ - -#ifdef CONFIG_USBDEV -void stm32_usbsuspend(struct usbdev_s *dev, bool resume) -{ - uinfo("resume: %d\n", resume); -} -#endif - -#endif /* CONFIG_STM32_OTGFS */ diff --git a/boards/arm/stm32/stm3220g-eval/src/stm32_userleds.c b/boards/arm/stm32/stm3220g-eval/src/stm32_userleds.c deleted file mode 100644 index 9a69e756ae071..0000000000000 --- a/boards/arm/stm32/stm3220g-eval/src/stm32_userleds.c +++ /dev/null @@ -1,96 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm3220g-eval/src/stm32_userleds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32.h" -#include "stm3220g-eval.h" - -#ifndef CONFIG_ARCH_LEDS - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* This array maps an LED number to GPIO pin configuration */ - -static uint32_t g_ledcfg[BOARD_NLEDS] = -{ - GPIO_LED1, GPIO_LED2, GPIO_LED3, GPIO_LED4 -}; - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_userled_initialize - ****************************************************************************/ - -uint32_t board_userled_initialize(void) -{ - /* Configure LED1-4 GPIOs for output */ - - stm32_configgpio(GPIO_LED1); - stm32_configgpio(GPIO_LED2); - stm32_configgpio(GPIO_LED3); - stm32_configgpio(GPIO_LED4); - return BOARD_NLEDS; -} - -/**************************************************************************** - * Name: board_userled - ****************************************************************************/ - -void board_userled(int led, bool ledon) -{ - if ((unsigned)led < BOARD_NLEDS) - { - stm32_gpiowrite(g_ledcfg[led], ledon); - } -} - -/**************************************************************************** - * Name: board_userled_all - ****************************************************************************/ - -void board_userled_all(uint32_t ledset) -{ - stm32_gpiowrite(GPIO_LED1, (ledset & BOARD_LED1_BIT) == 0); - stm32_gpiowrite(GPIO_LED2, (ledset & BOARD_LED2_BIT) == 0); - stm32_gpiowrite(GPIO_LED3, (ledset & BOARD_LED3_BIT) == 0); - stm32_gpiowrite(GPIO_LED4, (ledset & BOARD_LED4_BIT) == 0); -} - -#endif /* !CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/stm3220g-eval/tools/oocd.sh b/boards/arm/stm32/stm3220g-eval/tools/oocd.sh deleted file mode 100755 index 66a7cca63d08a..0000000000000 --- a/boards/arm/stm32/stm3220g-eval/tools/oocd.sh +++ /dev/null @@ -1,87 +0,0 @@ -#!/usr/bin/env bash - -# Get command line parameters - -USAGE="USAGE: $0 [-dh] " -ADVICE="Try '$0 -h' for more information" - -while [ ! -z "$1" ]; do - case $1 in - -d ) - set -x - ;; - -h ) - echo "$0 is a tool for generation of proper version files for the NuttX build" - echo "" - echo $USAGE - echo "" - echo "Where:" - echo " -d" - echo " Enable script debug" - echo " -h" - echo " show this help message and exit" - echo " Use the OpenOCD 0.4.0" - echo " " - echo " The full path to the top-level NuttX directory" - exit 0 - ;; - * ) - break; - ;; - esac - shift -done - -TOPDIR=$1 -if [ -z "${TOPDIR}" ]; then - echo "Missing argument" - echo $USAGE - echo $ADVICE - exit 1 -fi - -# This script *probably* only works with the following versions of OpenOCD: - -# Local search directory and configurations - -OPENOCD_SEARCHDIR="${TOPDIR}/boards/arm/stm32/stm3210e-eval/tools" -OPENOCD_WSEARCHDIR="`cygpath -w ${OPENOCD_SEARCHDIR}`" - -OPENOCD_PATH="/cygdrive/c/Program Files (x86)/OpenOCD/0.4.0/bin" -OPENOCD_EXE=openocd.exe -OPENOCD_INTERFACE="olimex-arm-usb-ocd.cfg" - -OPENOCD_TARGET="stm32.cfg" -OPENOCD_ARGS="-s ${OPENOCD_WSEARCHDIR} -f ${OPENOCD_INTERFACE} -f ${OPENOCD_TARGET}" - -echo "Trying OpenOCD 0.4.0 path: ${OPENOCD_PATH}/${OPENOCD_EXE}" - -# Verify that everything is what it claims it is and is located where it claims it is. - -if [ ! -x "${OPENOCD_PATH}/${OPENOCD_EXE}" ]; then - echo "OpenOCD executable does not exist: ${OPENOCD_PATH}/${OPENOCD_EXE}" - exit 1 -fi -if [ ! -f "${OPENOCD_SEARCHDIR}/${OPENOCD_TARGET}" ]; then - echo "OpenOCD target config file does not exist: ${OPENOCD_SEARCHDIR}/${OPENOCD_TARGET}" - exit 1 -fi -if [ ! -f "${OPENOCD_SEARCHDIR}/${OPENOCD_INTERFACE}" ]; then - echo "OpenOCD interface config file does not exist: ${OPENOCD_SEARCHDIR}/${OPENOCD_INTERFACE}" - exit 1 -fi - -# Enable debug if so requested - -if [ "X$2" = "X-d" ]; then - OPENOCD_ARGS=$OPENOCD_ARGS" -d3" - set -x -fi - -# Okay... do it! - -echo "Starting OpenOCD" -"${OPENOCD_PATH}/${OPENOCD_EXE}" ${OPENOCD_ARGS} & -echo "OpenOCD daemon started" -ps -ef | grep openocd -echo "In GDB: target remote localhost:3333" diff --git a/boards/arm/stm32/stm3240g-eval/CMakeLists.txt b/boards/arm/stm32/stm3240g-eval/CMakeLists.txt deleted file mode 100644 index 823f2be9fe84e..0000000000000 --- a/boards/arm/stm32/stm3240g-eval/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/stm3240g-eval/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32/stm3240g-eval/configs/dhcpd/defconfig b/boards/arm/stm32/stm3240g-eval/configs/dhcpd/defconfig deleted file mode 100644 index 1e1d4bae5c173..0000000000000 --- a/boards/arm/stm32/stm3240g-eval/configs/dhcpd/defconfig +++ /dev/null @@ -1,61 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_NETUTILS_DHCPD_IGNOREBROADCAST is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm3240g-eval" -CONFIG_ARCH_BOARD_STM3240G_EVAL=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F407IG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_DISABLE_ENVIRON=y -CONFIG_DISABLE_MOUNTPOINT=y -CONFIG_DISABLE_MQUEUE=y -CONFIG_DISABLE_PTHREAD=y -CONFIG_ETH0_PHY_DP83848C=y -CONFIG_EXAMPLES_DHCPD=y -CONFIG_EXAMPLES_DHCPD_NOMAC=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_HOST_WINDOWS=y -CONFIG_INIT_ENTRYPOINT="dhcpd_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_MM_REGIONS=2 -CONFIG_NET=y -CONFIG_NETUTILS_DHCPD=y -CONFIG_NETUTILS_NETLIB=y -CONFIG_NET_BROADCAST=y -CONFIG_NET_SOCKOPTS=y -CONFIG_NET_UDP=y -CONFIG_NET_UDP_CHECKSUMS=y -CONFIG_NUNGET_CHARS=0 -CONFIG_RAM_SIZE=196608 -CONFIG_RAM_START=0x20000000 -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=13 -CONFIG_START_MONTH=12 -CONFIG_START_YEAR=2011 -CONFIG_STDIO_DISABLE_BUFFERING=y -CONFIG_STM32_DFU=y -CONFIG_STM32_ETHMAC=y -CONFIG_STM32_JTAG_FULL_ENABLE=y -CONFIG_STM32_MII=y -CONFIG_STM32_PHYSR=16 -CONFIG_STM32_PHYSR_100MBPS=0x0000 -CONFIG_STM32_PHYSR_FULLDUPLEX=0x0004 -CONFIG_STM32_PHYSR_MODE=0x0004 -CONFIG_STM32_PHYSR_SPEED=0x0002 -CONFIG_STM32_USART3=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART3_RXBUFSIZE=128 -CONFIG_USART3_SERIAL_CONSOLE=y -CONFIG_USART3_TXBUFSIZE=128 diff --git a/boards/arm/stm32/stm3240g-eval/configs/discover/defconfig b/boards/arm/stm32/stm3240g-eval/configs/discover/defconfig deleted file mode 100644 index fa73ac6e959d5..0000000000000 --- a/boards/arm/stm32/stm3240g-eval/configs/discover/defconfig +++ /dev/null @@ -1,69 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm3240g-eval" -CONFIG_ARCH_BOARD_STM3240G_EVAL=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F407IG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_DISCOVER_DESCR="STM3240G-EVAL" -CONFIG_ETH0_PHY_DP83848C=y -CONFIG_EXAMPLES_DISCOVER=y -CONFIG_EXAMPLES_DISCOVER_DHCPC=y -CONFIG_EXAMPLES_DISCOVER_DRIPADDR=0xc0a80201 -CONFIG_EXAMPLES_DISCOVER_NOMAC=y -CONFIG_FAT_LCNAMES=y -CONFIG_FAT_LFN=y -CONFIG_FS_FAT=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_I2C=y -CONFIG_I2C_POLLED=y -CONFIG_INIT_ENTRYPOINT="discover_main" -CONFIG_MM_REGIONS=2 -CONFIG_NET=y -CONFIG_NETDB_DNSCLIENT_ENTRIES=4 -CONFIG_NET_ARP_IPIN=y -CONFIG_NET_BROADCAST=y -CONFIG_NET_ETH_PKTSIZE=650 -CONFIG_NET_ICMP_SOCKET=y -CONFIG_NET_MAX_LISTENPORTS=40 -CONFIG_NET_STATISTICS=y -CONFIG_NET_TCP=y -CONFIG_NET_TCP_PREALLOC_CONNS=40 -CONFIG_NET_UDP=y -CONFIG_NET_UDP_CHECKSUMS=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=196608 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=6 -CONFIG_START_MONTH=12 -CONFIG_START_YEAR=2011 -CONFIG_STM32_ETHMAC=y -CONFIG_STM32_I2C1=y -CONFIG_STM32_JTAG_FULL_ENABLE=y -CONFIG_STM32_MII=y -CONFIG_STM32_PHYSR=16 -CONFIG_STM32_PHYSR_100MBPS=0x0000 -CONFIG_STM32_PHYSR_FULLDUPLEX=0x0004 -CONFIG_STM32_PHYSR_MODE=0x0004 -CONFIG_STM32_PHYSR_SPEED=0x0002 -CONFIG_STM32_PWR=y -CONFIG_STM32_USART3=y -CONFIG_SYSTEM_PING=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART3_RXBUFSIZE=128 -CONFIG_USART3_SERIAL_CONSOLE=y -CONFIG_USART3_TXBUFSIZE=128 diff --git a/boards/arm/stm32/stm3240g-eval/configs/fb/defconfig b/boards/arm/stm32/stm3240g-eval/configs/fb/defconfig deleted file mode 100644 index 7db5d2ec714c4..0000000000000 --- a/boards/arm/stm32/stm3240g-eval/configs/fb/defconfig +++ /dev/null @@ -1,71 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm3240g-eval" -CONFIG_ARCH_BOARD_STM3240G_EVAL=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F407IG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_DRIVERS_VIDEO=y -CONFIG_EXAMPLES_FB=y -CONFIG_EXAMPLES_PDCURSES=y -CONFIG_FS_PROCFS=y -CONFIG_GRAPHICS_PDCURSES=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_HEAP2_BASE=0x64000000 -CONFIG_HEAP2_SIZE=2097152 -CONFIG_HOST_WINDOWS=y -CONFIG_I2C=y -CONFIG_I2C_POLLED=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LCD=y -CONFIG_LCD_FRAMEBUFFER=y -CONFIG_LCD_MAXCONTRAST=1 -CONFIG_LCD_NOGETRUN=y -CONFIG_LINE_MAX=64 -CONFIG_MM_REGIONS=3 -CONFIG_MQ_MAXMSGSIZE=64 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_DISABLE_IFUPDOWN=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_NXFONTS_DISABLE_1BPP=y -CONFIG_NXFONTS_DISABLE_24BPP=y -CONFIG_NXFONTS_DISABLE_2BPP=y -CONFIG_NXFONTS_DISABLE_32BPP=y -CONFIG_NXFONTS_DISABLE_4BPP=y -CONFIG_NXFONTS_DISABLE_8BPP=y -CONFIG_PDCURSES_FONT_6X9=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=196608 -CONFIG_RAM_START=0x20000000 -CONFIG_RR_INTERVAL=200 -CONFIG_RTC_DATETIME=y -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=17 -CONFIG_START_MONTH=9 -CONFIG_STM32_EXTERNAL_RAM=y -CONFIG_STM32_FSMC=y -CONFIG_STM32_I2C1=y -CONFIG_STM32_JTAG_FULL_ENABLE=y -CONFIG_STM32_PWR=y -CONFIG_STM32_RTC=y -CONFIG_STM32_USART3=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART3_RXBUFSIZE=128 -CONFIG_USART3_SERIAL_CONSOLE=y -CONFIG_USART3_TXBUFSIZE=128 -CONFIG_VIDEO_FB=y diff --git a/boards/arm/stm32/stm3240g-eval/configs/knxwm/Make.defs b/boards/arm/stm32/stm3240g-eval/configs/knxwm/Make.defs deleted file mode 100644 index c8ecd22e21e7c..0000000000000 --- a/boards/arm/stm32/stm3240g-eval/configs/knxwm/Make.defs +++ /dev/null @@ -1,40 +0,0 @@ -############################################################################ -# boards/arm/stm32/stm3240g-eval/configs/knxwm/Make.defs -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/.config -include $(TOPDIR)/tools/Config.mk -include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs - -ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)memory.ld -ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)kernel-space.ld - -ARCHCXXFLAGS += -fpermissive -ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 - -CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) -CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) -CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -AFLAGS := $(CFLAGS) -D__ASSEMBLY__ - -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections -LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32/stm3240g-eval/configs/knxwm/defconfig b/boards/arm/stm32/stm3240g-eval/configs/knxwm/defconfig deleted file mode 100644 index dc2de40c87105..0000000000000 --- a/boards/arm/stm32/stm3240g-eval/configs/knxwm/defconfig +++ /dev/null @@ -1,98 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_NXFONTS_DISABLE_16BPP is not set -# CONFIG_NXTK_DEFAULT_BORDERCOLORS is not set -# CONFIG_NXWM_NXTERM is not set -# CONFIG_NX_DISABLE_16BPP is not set -# CONFIG_NX_PACKEDMSFIRST is not set -# CONFIG_NX_WRITEONLY is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm3240g-eval" -CONFIG_ARCH_BOARD_STM3240G_EVAL=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F407IG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_ARM_MPU=y -CONFIG_ARM_TOOLCHAIN_BUILDROOT=y -CONFIG_BOARDCTL=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILD_PROTECTED=y -CONFIG_FAT_LCNAMES=y -CONFIG_FAT_LFN=y -CONFIG_FS_FAT=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_HOST_WINDOWS=y -CONFIG_I2C_POLLED=y -CONFIG_INIT_ENTRYPOINT="nxwm_main" -CONFIG_INPUT=y -CONFIG_INPUT_STMPE811=y -CONFIG_INTELHEX_BINARY=y -CONFIG_LCD=y -CONFIG_LCD_MAXCONTRAST=1 -CONFIG_LCD_NOGETRUN=y -CONFIG_LIBC_MAX_EXITFUNS=1 -CONFIG_LIBC_USRWORK=y -CONFIG_MM_REGIONS=2 -CONFIG_MQ_MAXMSGSIZE=64 -CONFIG_NUTTX_USERSPACE=0x08040000 -CONFIG_NX=y -CONFIG_NXFONT_SANS22X29B=y -CONFIG_NXFONT_SANS23X27=y -CONFIG_NXSTART_SERVERSTACK=1596 -CONFIG_NXTK_BORDERCOLOR1=0x5cb7 -CONFIG_NXTK_BORDERCOLOR2=0x21c9 -CONFIG_NXTK_BORDERCOLOR3=0xffdf -CONFIG_NXWIDGETS=y -CONFIG_NXWIDGETS_BPP=16 -CONFIG_NXWIDGETS_CUSTOM_EDGECOLORS=y -CONFIG_NXWIDGETS_CUSTOM_FILLCOLORS=y -CONFIG_NXWIDGETS_DEFAULT_BACKGROUNDCOLOR=0x9dfb -CONFIG_NXWIDGETS_DEFAULT_HIGHLIGHTCOLOR=0xc618 -CONFIG_NXWIDGETS_DEFAULT_SELECTEDBACKGROUNDCOLOR=0xd73e -CONFIG_NXWIDGETS_DEFAULT_SHADOWEDGECOLOR=0x21e9 -CONFIG_NXWIDGETS_DEFAULT_SHINEEDGECOLOR=0xffdf -CONFIG_NXWIDGETS_SIZEOFCHAR=1 -CONFIG_NXWM=y -CONFIG_NXWM_HEXCALCULATOR_CUSTOM_FONTID=y -CONFIG_NXWM_HEXCALCULATOR_FONTID=5 -CONFIG_NXWM_KEYBOARD=y -CONFIG_NXWM_TASKBAR_LEFT=y -CONFIG_NXWM_TASKBAR_VSPACING=4 -CONFIG_NX_BLOCKING=y -CONFIG_NX_KBD=y -CONFIG_NX_XYINPUT_TOUCHSCREEN=y -CONFIG_PASS1_BUILDIR="boards/arm/stm32/stm3240g-eval/kernel" -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=196608 -CONFIG_RAM_START=0x20000000 -CONFIG_RR_INTERVAL=200 -CONFIG_RTC_DATETIME=y -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_HPWORKPRIORITY=192 -CONFIG_SCHED_WAITPID=y -CONFIG_STM32_DFU=y -CONFIG_STM32_FSMC=y -CONFIG_STM32_I2C1=y -CONFIG_STM32_JTAG_FULL_ENABLE=y -CONFIG_STM32_PWR=y -CONFIG_STM32_RTC=y -CONFIG_STM32_USART3=y -CONFIG_STMPE811_ACTIVELOW=y -CONFIG_STMPE811_EDGE=y -CONFIG_STMPE811_MULTIPLE=y -CONFIG_STMPE811_THRESHX=39 -CONFIG_STMPE811_THRESHY=51 -CONFIG_SYMTAB_ORDEREDBYNAME=y -CONFIG_SYSTEM_READLINE=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART3_RXBUFSIZE=128 -CONFIG_USART3_SERIAL_CONSOLE=y -CONFIG_USART3_TXBUFSIZE=128 diff --git a/boards/arm/stm32/stm3240g-eval/configs/nettest/defconfig b/boards/arm/stm32/stm3240g-eval/configs/nettest/defconfig deleted file mode 100644 index cecabe2f65f31..0000000000000 --- a/boards/arm/stm32/stm3240g-eval/configs/nettest/defconfig +++ /dev/null @@ -1,61 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm3240g-eval" -CONFIG_ARCH_BOARD_STM3240G_EVAL=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F407IG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_CONSOLE_SYSLOG=y -CONFIG_DISABLE_ENVIRON=y -CONFIG_DISABLE_MOUNTPOINT=y -CONFIG_DISABLE_MQUEUE=y -CONFIG_DISABLE_PTHREAD=y -CONFIG_ETH0_PHY_DP83848C=y -CONFIG_EXAMPLES_NETTEST=y -CONFIG_EXAMPLES_NETTEST_NOMAC=y -CONFIG_EXAMPLES_NETTEST_PERFORMANCE=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_HOST_WINDOWS=y -CONFIG_INIT_ENTRYPOINT="nettest_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_MM_REGIONS=2 -CONFIG_NET=y -CONFIG_NETUTILS_NETLIB=y -CONFIG_NET_MAX_LISTENPORTS=40 -CONFIG_NET_SOCKOPTS=y -CONFIG_NET_TCP=y -CONFIG_NET_TCP_PREALLOC_CONNS=40 -CONFIG_NUNGET_CHARS=0 -CONFIG_RAM_SIZE=196608 -CONFIG_RAM_START=0x20000000 -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=6 -CONFIG_START_MONTH=12 -CONFIG_START_YEAR=2011 -CONFIG_STDIO_DISABLE_BUFFERING=y -CONFIG_STM32_DFU=y -CONFIG_STM32_ETHMAC=y -CONFIG_STM32_JTAG_FULL_ENABLE=y -CONFIG_STM32_MII=y -CONFIG_STM32_PHYSR=16 -CONFIG_STM32_PHYSR_100MBPS=0x0000 -CONFIG_STM32_PHYSR_FULLDUPLEX=0x0004 -CONFIG_STM32_PHYSR_MODE=0x0004 -CONFIG_STM32_PHYSR_SPEED=0x0002 -CONFIG_STM32_USART3=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART3_RXBUFSIZE=128 -CONFIG_USART3_SERIAL_CONSOLE=y -CONFIG_USART3_TXBUFSIZE=128 diff --git a/boards/arm/stm32/stm3240g-eval/configs/nsh/defconfig b/boards/arm/stm32/stm3240g-eval/configs/nsh/defconfig deleted file mode 100644 index e445c306c4d4e..0000000000000 --- a/boards/arm/stm32/stm3240g-eval/configs/nsh/defconfig +++ /dev/null @@ -1,81 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_NSH_DISABLE_IFCONFIG is not set -# CONFIG_NSH_DISABLE_PS is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm3240g-eval" -CONFIG_ARCH_BOARD_STM3240G_EVAL=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F407IG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_ETH0_PHY_DP83848C=y -CONFIG_FAT_LCNAMES=y -CONFIG_FAT_LFN=y -CONFIG_FS_FAT=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_HOST_WINDOWS=y -CONFIG_I2C=y -CONFIG_I2CTOOL_DEFFREQ=100000 -CONFIG_I2CTOOL_MINBUS=1 -CONFIG_I2C_POLLED=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_MM_REGIONS=2 -CONFIG_NET=y -CONFIG_NETDB_DNSCLIENT=y -CONFIG_NETDB_DNSCLIENT_ENTRIES=4 -CONFIG_NETDB_DNSSERVER_NOADDR=y -CONFIG_NETINIT_NOMAC=y -CONFIG_NETUTILS_TELNETD=y -CONFIG_NETUTILS_TFTPC=y -CONFIG_NETUTILS_WEBCLIENT=y -CONFIG_NET_BROADCAST=y -CONFIG_NET_ICMP_SOCKET=y -CONFIG_NET_MAX_LISTENPORTS=40 -CONFIG_NET_STATISTICS=y -CONFIG_NET_TCP=y -CONFIG_NET_TCP_PREALLOC_CONNS=40 -CONFIG_NET_UDP=y -CONFIG_NET_UDP_CHECKSUMS=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=196608 -CONFIG_RAM_START=0x20000000 -CONFIG_RR_INTERVAL=200 -CONFIG_RTC_DATETIME=y -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_WAITPID=y -CONFIG_STM32_ETHMAC=y -CONFIG_STM32_I2C1=y -CONFIG_STM32_JTAG_FULL_ENABLE=y -CONFIG_STM32_MII=y -CONFIG_STM32_PHYSR=16 -CONFIG_STM32_PHYSR_100MBPS=0x0000 -CONFIG_STM32_PHYSR_FULLDUPLEX=0x0004 -CONFIG_STM32_PHYSR_MODE=0x0004 -CONFIG_STM32_PHYSR_SPEED=0x0002 -CONFIG_STM32_PWR=y -CONFIG_STM32_RNG=y -CONFIG_STM32_RTC=y -CONFIG_STM32_USART3=y -CONFIG_SYMTAB_ORDEREDBYNAME=y -CONFIG_SYSTEM_I2CTOOL=y -CONFIG_SYSTEM_NSH=y -CONFIG_SYSTEM_PING=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART3_RXBUFSIZE=128 -CONFIG_USART3_SERIAL_CONSOLE=y -CONFIG_USART3_TXBUFSIZE=128 diff --git a/boards/arm/stm32/stm3240g-eval/configs/nsh2/defconfig b/boards/arm/stm32/stm3240g-eval/configs/nsh2/defconfig deleted file mode 100644 index 007647eefa558..0000000000000 --- a/boards/arm/stm32/stm3240g-eval/configs/nsh2/defconfig +++ /dev/null @@ -1,90 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_DEV_CONSOLE is not set -# CONFIG_MMCSD_HAVE_CARDDETECT is not set -# CONFIG_MMCSD_MMCSUPPORT is not set -# CONFIG_NSH_CONSOLE is not set -# CONFIG_NSH_DISABLE_IFCONFIG is not set -# CONFIG_NSH_DISABLE_PS is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm3240g-eval" -CONFIG_ARCH_BOARD_STM3240G_EVAL=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F407IG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_ETH0_PHY_DP83848C=y -CONFIG_FAT_LCNAMES=y -CONFIG_FAT_LFN=y -CONFIG_FS_FAT=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_HOST_WINDOWS=y -CONFIG_I2C=y -CONFIG_I2CTOOL_DEFFREQ=100000 -CONFIG_I2CTOOL_MINBUS=1 -CONFIG_I2C_POLLED=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_MMCSD=y -CONFIG_MMCSD_MULTIBLOCK_LIMIT=1 -CONFIG_MMCSD_SDIO=y -CONFIG_MTD=y -CONFIG_NET=y -CONFIG_NETDB_DNSCLIENT=y -CONFIG_NETDB_DNSCLIENT_ENTRIES=4 -CONFIG_NETDB_DNSSERVER_NOADDR=y -CONFIG_NETINIT_NOMAC=y -CONFIG_NETUTILS_TELNETD=y -CONFIG_NETUTILS_TFTPC=y -CONFIG_NETUTILS_WEBCLIENT=y -CONFIG_NET_BROADCAST=y -CONFIG_NET_ICMP_SOCKET=y -CONFIG_NET_MAX_LISTENPORTS=40 -CONFIG_NET_STATISTICS=y -CONFIG_NET_TCP=y -CONFIG_NET_TCP_PREALLOC_CONNS=40 -CONFIG_NET_UDP=y -CONFIG_NET_UDP_CHECKSUMS=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAMLOG=y -CONFIG_RAMLOG_SYSLOG=y -CONFIG_RAM_SIZE=196608 -CONFIG_RAM_START=0x20000000 -CONFIG_RR_INTERVAL=200 -CONFIG_RTC_DATETIME=y -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_HPWORKPRIORITY=192 -CONFIG_SCHED_HPWORKSTACKSIZE=1024 -CONFIG_SCHED_WAITPID=y -CONFIG_STM32_DFU=y -CONFIG_STM32_DMA2=y -CONFIG_STM32_ETHMAC=y -CONFIG_STM32_I2C1=y -CONFIG_STM32_JTAG_FULL_ENABLE=y -CONFIG_STM32_MII=y -CONFIG_STM32_PHYSR=16 -CONFIG_STM32_PHYSR_100MBPS=0x0000 -CONFIG_STM32_PHYSR_FULLDUPLEX=0x0004 -CONFIG_STM32_PHYSR_MODE=0x0004 -CONFIG_STM32_PHYSR_SPEED=0x0002 -CONFIG_STM32_PWR=y -CONFIG_STM32_RTC=y -CONFIG_STM32_SDIO=y -CONFIG_SYMTAB_ORDEREDBYNAME=y -CONFIG_SYSTEM_I2CTOOL=y -CONFIG_SYSTEM_NSH=y -CONFIG_SYSTEM_PING=y -CONFIG_TASK_NAME_SIZE=0 diff --git a/boards/arm/stm32/stm3240g-eval/configs/nxterm/defconfig b/boards/arm/stm32/stm3240g-eval/configs/nxterm/defconfig deleted file mode 100644 index cdf394741be44..0000000000000 --- a/boards/arm/stm32/stm3240g-eval/configs/nxterm/defconfig +++ /dev/null @@ -1,103 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_NSH_DISABLE_IFCONFIG is not set -# CONFIG_NSH_DISABLE_PS is not set -# CONFIG_NXFONTS_DISABLE_16BPP is not set -# CONFIG_NXTK_DEFAULT_BORDERCOLORS is not set -# CONFIG_NX_DISABLE_16BPP is not set -# CONFIG_NX_PACKEDMSFIRST is not set -# CONFIG_NX_WRITEONLY is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm3240g-eval" -CONFIG_ARCH_BOARD_STM3240G_EVAL=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F407IG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_ETH0_PHY_DP83848C=y -CONFIG_EXAMPLES_NXTERM=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_HEAP2_BASE=0x64000000 -CONFIG_HEAP2_SIZE=2097152 -CONFIG_HOST_WINDOWS=y -CONFIG_I2C=y -CONFIG_I2CTOOL_DEFFREQ=100000 -CONFIG_I2CTOOL_MINBUS=1 -CONFIG_I2C_POLLED=y -CONFIG_INIT_ENTRYPOINT="nxterm_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LCD=y -CONFIG_LCD_MAXCONTRAST=1 -CONFIG_LCD_NOGETRUN=y -CONFIG_LINE_MAX=64 -CONFIG_MM_REGIONS=3 -CONFIG_MQ_MAXMSGSIZE=64 -CONFIG_NET=y -CONFIG_NETDB_DNSCLIENT=y -CONFIG_NETDB_DNSCLIENT_ENTRIES=4 -CONFIG_NETDB_DNSSERVER_NOADDR=y -CONFIG_NETINIT_NOMAC=y -CONFIG_NETUTILS_TELNETD=y -CONFIG_NETUTILS_TFTPC=y -CONFIG_NETUTILS_WEBCLIENT=y -CONFIG_NET_BROADCAST=y -CONFIG_NET_ICMP_SOCKET=y -CONFIG_NET_MAX_LISTENPORTS=40 -CONFIG_NET_STATISTICS=y -CONFIG_NET_TCP=y -CONFIG_NET_TCP_PREALLOC_CONNS=40 -CONFIG_NET_UDP=y -CONFIG_NET_UDP_CHECKSUMS=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_LIBRARY=y -CONFIG_NSH_READLINE=y -CONFIG_NX=y -CONFIG_NXFONT_SANS23X27=y -CONFIG_NXTERM=y -CONFIG_NXTERM_CACHESIZE=32 -CONFIG_NXTERM_CURSORCHAR=95 -CONFIG_NXTERM_MXCHARS=256 -CONFIG_NXTK_BORDERCOLOR1=0xad55 -CONFIG_NXTK_BORDERCOLOR2=0x6b4d -CONFIG_NXTK_BORDERCOLOR3=0xdedb -CONFIG_NX_BLOCKING=y -CONFIG_NX_KBD=y -CONFIG_NX_XYINPUT_MOUSE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=196608 -CONFIG_RAM_START=0x20000000 -CONFIG_RR_INTERVAL=200 -CONFIG_RTC_DATETIME=y -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_WAITPID=y -CONFIG_STM32_DFU=y -CONFIG_STM32_ETHMAC=y -CONFIG_STM32_EXTERNAL_RAM=y -CONFIG_STM32_FSMC=y -CONFIG_STM32_I2C1=y -CONFIG_STM32_JTAG_FULL_ENABLE=y -CONFIG_STM32_MII=y -CONFIG_STM32_PHYSR=16 -CONFIG_STM32_PHYSR_100MBPS=0x0000 -CONFIG_STM32_PHYSR_FULLDUPLEX=0x0004 -CONFIG_STM32_PHYSR_MODE=0x0004 -CONFIG_STM32_PHYSR_SPEED=0x0002 -CONFIG_STM32_PWR=y -CONFIG_STM32_RTC=y -CONFIG_STM32_USART3=y -CONFIG_SYSTEM_I2CTOOL=y -CONFIG_SYSTEM_PING=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART3_RXBUFSIZE=128 -CONFIG_USART3_SERIAL_CONSOLE=y -CONFIG_USART3_TXBUFSIZE=128 diff --git a/boards/arm/stm32/stm3240g-eval/configs/nxwm/defconfig b/boards/arm/stm32/stm3240g-eval/configs/nxwm/defconfig deleted file mode 100644 index 550058e72ce9a..0000000000000 --- a/boards/arm/stm32/stm3240g-eval/configs/nxwm/defconfig +++ /dev/null @@ -1,122 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -# CONFIG_NSH_DISABLE_IFCONFIG is not set -# CONFIG_NSH_DISABLE_PS is not set -# CONFIG_NXFONTS_DISABLE_16BPP is not set -# CONFIG_NXTK_DEFAULT_BORDERCOLORS is not set -# CONFIG_NX_DISABLE_16BPP is not set -# CONFIG_NX_PACKEDMSFIRST is not set -# CONFIG_NX_WRITEONLY is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm3240g-eval" -CONFIG_ARCH_BOARD_STM3240G_EVAL=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F407IG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_FAT_LCNAMES=y -CONFIG_FAT_LFN=y -CONFIG_FS_FAT=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_HOST_WINDOWS=y -CONFIG_I2C_POLLED=y -CONFIG_INIT_ENTRYPOINT="nxwm_main" -CONFIG_INPUT=y -CONFIG_INPUT_STMPE811=y -CONFIG_INTELHEX_BINARY=y -CONFIG_LCD=y -CONFIG_LCD_MAXCONTRAST=1 -CONFIG_LCD_NOGETRUN=y -CONFIG_LIBC_MAX_EXITFUNS=1 -CONFIG_LINE_MAX=64 -CONFIG_MM_REGIONS=2 -CONFIG_MQ_MAXMSGSIZE=64 -CONFIG_NET=y -CONFIG_NETDB_DNSCLIENT=y -CONFIG_NETDB_DNSSERVER_NOADDR=y -CONFIG_NETINIT_NOMAC=y -CONFIG_NETUTILS_TELNETD=y -CONFIG_NETUTILS_TFTPC=y -CONFIG_NETUTILS_WEBCLIENT=y -CONFIG_NET_ICMP_SOCKET=y -CONFIG_NET_MAX_LISTENPORTS=40 -CONFIG_NET_STATISTICS=y -CONFIG_NET_TCP=y -CONFIG_NET_TCP_PREALLOC_CONNS=40 -CONFIG_NET_UDP=y -CONFIG_NET_UDP_CHECKSUMS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_LIBRARY=y -CONFIG_NSH_READLINE=y -CONFIG_NX=y -CONFIG_NXFONT_SANS22X29B=y -CONFIG_NXFONT_SANS23X27=y -CONFIG_NXTERM=y -CONFIG_NXTERM_CACHESIZE=32 -CONFIG_NXTERM_CURSORCHAR=95 -CONFIG_NXTERM_MXCHARS=325 -CONFIG_NXTERM_NXKBDIN=y -CONFIG_NXTK_BORDERCOLOR1=0x5cb7 -CONFIG_NXTK_BORDERCOLOR2=0x21c9 -CONFIG_NXTK_BORDERCOLOR3=0xffdf -CONFIG_NXWIDGETS=y -CONFIG_NXWIDGETS_BPP=16 -CONFIG_NXWIDGETS_CUSTOM_EDGECOLORS=y -CONFIG_NXWIDGETS_CUSTOM_FILLCOLORS=y -CONFIG_NXWIDGETS_DEFAULT_BACKGROUNDCOLOR=0x9dfb -CONFIG_NXWIDGETS_DEFAULT_HIGHLIGHTCOLOR=0xc618 -CONFIG_NXWIDGETS_DEFAULT_SELECTEDBACKGROUNDCOLOR=0xd73e -CONFIG_NXWIDGETS_DEFAULT_SHADOWEDGECOLOR=0x21e9 -CONFIG_NXWIDGETS_DEFAULT_SHINEEDGECOLOR=0xffdf -CONFIG_NXWIDGETS_SIZEOFCHAR=1 -CONFIG_NXWM=y -CONFIG_NXWM_HEXCALCULATOR_CUSTOM_FONTID=y -CONFIG_NXWM_HEXCALCULATOR_FONTID=5 -CONFIG_NXWM_KEYBOARD=y -CONFIG_NXWM_TASKBAR_LEFT=y -CONFIG_NXWM_TASKBAR_VSPACING=4 -CONFIG_NX_BLOCKING=y -CONFIG_NX_KBD=y -CONFIG_NX_XYINPUT_TOUCHSCREEN=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=196608 -CONFIG_RAM_START=0x20000000 -CONFIG_RR_INTERVAL=200 -CONFIG_RTC_DATETIME=y -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_HPWORKPRIORITY=192 -CONFIG_SCHED_WAITPID=y -CONFIG_STM32_DFU=y -CONFIG_STM32_ETHMAC=y -CONFIG_STM32_FSMC=y -CONFIG_STM32_I2C1=y -CONFIG_STM32_JTAG_FULL_ENABLE=y -CONFIG_STM32_MII=y -CONFIG_STM32_PHYSR=16 -CONFIG_STM32_PHYSR_100MBPS=0x0000 -CONFIG_STM32_PHYSR_FULLDUPLEX=0x0004 -CONFIG_STM32_PHYSR_MODE=0x0004 -CONFIG_STM32_PHYSR_SPEED=0x0002 -CONFIG_STM32_PWR=y -CONFIG_STM32_RTC=y -CONFIG_STM32_USART3=y -CONFIG_STMPE811_ACTIVELOW=y -CONFIG_STMPE811_EDGE=y -CONFIG_STMPE811_MULTIPLE=y -CONFIG_STMPE811_THRESHX=39 -CONFIG_STMPE811_THRESHY=51 -CONFIG_SYMTAB_ORDEREDBYNAME=y -CONFIG_SYSTEM_PING=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART3_RXBUFSIZE=128 -CONFIG_USART3_SERIAL_CONSOLE=y -CONFIG_USART3_TXBUFSIZE=128 diff --git a/boards/arm/stm32/stm3240g-eval/configs/telnetd/defconfig b/boards/arm/stm32/stm3240g-eval/configs/telnetd/defconfig deleted file mode 100644 index b34caaabfe6d3..0000000000000 --- a/boards/arm/stm32/stm3240g-eval/configs/telnetd/defconfig +++ /dev/null @@ -1,62 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm3240g-eval" -CONFIG_ARCH_BOARD_STM3240G_EVAL=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F407IG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_CONSOLE_SYSLOG=y -CONFIG_DISABLE_ENVIRON=y -CONFIG_DISABLE_MOUNTPOINT=y -CONFIG_DISABLE_MQUEUE=y -CONFIG_DISABLE_PTHREAD=y -CONFIG_ETH0_PHY_DP83848C=y -CONFIG_EXAMPLES_TELNETD=y -CONFIG_EXAMPLES_TELNETD_CLIENTPRIO=128 -CONFIG_EXAMPLES_TELNETD_DAEMONPRIO=128 -CONFIG_EXAMPLES_TELNETD_NOMAC=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_INIT_ENTRYPOINT="telnetd_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_MM_REGIONS=2 -CONFIG_NET=y -CONFIG_NETUTILS_TELNETD=y -CONFIG_NET_MAX_LISTENPORTS=40 -CONFIG_NET_SOCKOPTS=y -CONFIG_NET_TCP=y -CONFIG_NET_TCP_PREALLOC_CONNS=40 -CONFIG_NSH_LIBRARY=y -CONFIG_NUNGET_CHARS=0 -CONFIG_RAM_SIZE=196608 -CONFIG_RAM_START=0x20000000 -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=6 -CONFIG_START_MONTH=12 -CONFIG_START_YEAR=2011 -CONFIG_STM32_DFU=y -CONFIG_STM32_ETHMAC=y -CONFIG_STM32_JTAG_FULL_ENABLE=y -CONFIG_STM32_MII=y -CONFIG_STM32_PHYSR=16 -CONFIG_STM32_PHYSR_100MBPS=0x0000 -CONFIG_STM32_PHYSR_FULLDUPLEX=0x0004 -CONFIG_STM32_PHYSR_MODE=0x0004 -CONFIG_STM32_PHYSR_SPEED=0x0002 -CONFIG_STM32_USART3=y -CONFIG_SYSTEM_READLINE=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART3_RXBUFSIZE=128 -CONFIG_USART3_SERIAL_CONSOLE=y -CONFIG_USART3_TXBUFSIZE=128 diff --git a/boards/arm/stm32/stm3240g-eval/configs/webserver/defconfig b/boards/arm/stm32/stm3240g-eval/configs/webserver/defconfig deleted file mode 100644 index b50bf38bc9126..0000000000000 --- a/boards/arm/stm32/stm3240g-eval/configs/webserver/defconfig +++ /dev/null @@ -1,75 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -# CONFIG_NSH_DISABLE_IFCONFIG is not set -# CONFIG_NSH_DISABLE_PS is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm3240g-eval" -CONFIG_ARCH_BOARD_STM3240G_EVAL=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F407IG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_EXAMPLES_NETTEST=y -CONFIG_EXAMPLES_WEBSERVER=y -CONFIG_FAT_LCNAMES=y -CONFIG_FAT_LFN=y -CONFIG_FS_FAT=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_I2C=y -CONFIG_I2C_POLLED=y -CONFIG_INIT_ENTRYPOINT="webserver_main" -CONFIG_LINE_MAX=64 -CONFIG_MM_REGIONS=2 -CONFIG_MTD=y -CONFIG_NET=y -CONFIG_NETINIT_NOMAC=y -CONFIG_NETUTILS_TELNETD=y -CONFIG_NETUTILS_WEBSERVER=y -CONFIG_NET_ICMP_SOCKET=y -CONFIG_NET_MAX_LISTENPORTS=40 -CONFIG_NET_SOCKOPTS=y -CONFIG_NET_STATISTICS=y -CONFIG_NET_TCP=y -CONFIG_NET_TCP_PREALLOC_CONNS=40 -CONFIG_NET_UDP=y -CONFIG_NET_UDP_CHECKSUMS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_LIBRARY=y -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=196608 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_RTC_DATETIME=y -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_WAITPID=y -CONFIG_STM32_CCMEXCLUDE=y -CONFIG_STM32_ETHMAC=y -CONFIG_STM32_I2C1=y -CONFIG_STM32_JTAG_FULL_ENABLE=y -CONFIG_STM32_MII=y -CONFIG_STM32_PHYSR=16 -CONFIG_STM32_PHYSR_100MBPS=0x0000 -CONFIG_STM32_PHYSR_FULLDUPLEX=0x0004 -CONFIG_STM32_PHYSR_MODE=0x0004 -CONFIG_STM32_PHYSR_SPEED=0x0002 -CONFIG_STM32_PWR=y -CONFIG_STM32_RTC=y -CONFIG_STM32_USART3=y -CONFIG_SYMTAB_ORDEREDBYNAME=y -CONFIG_SYSTEM_PING=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART3_RXBUFSIZE=128 -CONFIG_USART3_SERIAL_CONSOLE=y -CONFIG_USART3_TXBUFSIZE=128 diff --git a/boards/arm/stm32/stm3240g-eval/configs/xmlrpc/defconfig b/boards/arm/stm32/stm3240g-eval/configs/xmlrpc/defconfig deleted file mode 100644 index ca17c0e962fb8..0000000000000 --- a/boards/arm/stm32/stm3240g-eval/configs/xmlrpc/defconfig +++ /dev/null @@ -1,69 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_DISABLE_OS_API is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm3240g-eval" -CONFIG_ARCH_BOARD_STM3240G_EVAL=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F407IG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_ETH0_PHY_DP83848C=y -CONFIG_EXAMPLES_XMLRPC=y -CONFIG_EXAMPLES_XMLRPC_DHCPC=y -CONFIG_EXAMPLES_XMLRPC_NOMAC=y -CONFIG_FAT_LCNAMES=y -CONFIG_FAT_LFN=y -CONFIG_FS_FAT=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_I2C=y -CONFIG_I2C_POLLED=y -CONFIG_INIT_ENTRYPOINT="xmlrpc_main" -CONFIG_INIT_STACKSIZE=4096 -CONFIG_MM_REGIONS=2 -CONFIG_NET=y -CONFIG_NETDB_DNSCLIENT_ENTRIES=4 -CONFIG_NET_ARP_IPIN=y -CONFIG_NET_BROADCAST=y -CONFIG_NET_ETH_PKTSIZE=650 -CONFIG_NET_ICMP_SOCKET=y -CONFIG_NET_MAX_LISTENPORTS=40 -CONFIG_NET_STATISTICS=y -CONFIG_NET_TCP=y -CONFIG_NET_TCP_PREALLOC_CONNS=40 -CONFIG_NET_UDP=y -CONFIG_NET_UDP_CHECKSUMS=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=196608 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=6 -CONFIG_START_MONTH=12 -CONFIG_START_YEAR=2011 -CONFIG_STM32_ETHMAC=y -CONFIG_STM32_I2C1=y -CONFIG_STM32_JTAG_FULL_ENABLE=y -CONFIG_STM32_MII=y -CONFIG_STM32_PHYSR=16 -CONFIG_STM32_PHYSR_100MBPS=0x0000 -CONFIG_STM32_PHYSR_FULLDUPLEX=0x0004 -CONFIG_STM32_PHYSR_MODE=0x0004 -CONFIG_STM32_PHYSR_SPEED=0x0002 -CONFIG_STM32_PWR=y -CONFIG_STM32_USART3=y -CONFIG_SYSTEM_PING=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART3_RXBUFSIZE=128 -CONFIG_USART3_SERIAL_CONSOLE=y -CONFIG_USART3_TXBUFSIZE=128 diff --git a/boards/arm/stm32/stm3240g-eval/include/board.h b/boards/arm/stm32/stm3240g-eval/include/board.h deleted file mode 100644 index 895059dfce0ec..0000000000000 --- a/boards/arm/stm32/stm3240g-eval/include/board.h +++ /dev/null @@ -1,603 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm3240g-eval/include/board.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __BOARD_ARM_STM32_STM3240G_EVAL_INCLUDE_BOARD_H -#define __BOARD_ARM_STM32_STM3240G_EVAL_INCLUDE_BOARD_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#ifndef __ASSEMBLY__ -# include -#endif - -/* Logic in arch/arm/src and boards/ may need to include these file prior to - * including board.h: stm32_rcc.h, stm32_sdio.h, stm32.h. They cannot be - * included here because board.h is used in other contexts where the STM32 - * internal header files are not available. - */ - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Clocking *****************************************************************/ - -/* Four clock sources are available on STM3240G-EVAL evaluation board for - * STM32F407IGH6 and RTC embedded: - * - * X1, 25 MHz crystal for Ethernet PHY with socket. - * It can be removed when clock is provided by MCO pin of the MCU - * X2, 26 MHz crystal for USB OTG HS PHY - * X3, 32 kHz crystal for embedded RTC - * X4, 25 MHz crystal with socket for STM32F407IGH6 microcontroller - * (It can be removed from socket when internal RC clock is used.) - * - * This is the "standard" configuration as set up by - * arch/arm/src/stm32f40xx_rcc.c: - * System Clock source : PLL (HSE) - * SYSCLK(Hz) : 168000000 Determined by PLL - * configuration - * HCLK(Hz) : 168000000 (STM32_RCC_CFGR_HPRE) - * AHB Prescaler : 1 (STM32_RCC_CFGR_HPRE) - * APB1 Prescaler : 4 (STM32_RCC_CFGR_PPRE1) - * APB2 Prescaler : 2 (STM32_RCC_CFGR_PPRE2) - * HSE Frequency(Hz) : 25000000 (STM32_BOARD_XTAL) - * PLLM : 25 (STM32_PLLCFG_PLLM) - * PLLN : 336 (STM32_PLLCFG_PLLN) - * PLLP : 2 (STM32_PLLCFG_PLLP) - * PLLQ : 7 (STM32_PLLCFG_PLLQ) - * Main regulator output voltage : Scale1 mode Needed for high speed - * SYSCLK - * Flash Latency(WS) : 5 - * Prefetch Buffer : OFF - * Instruction cache : ON - * Data cache : ON - * Require 48MHz for USB OTG FS, : Enabled - * SDIO and RNG clock - */ - -/* HSI - 16 MHz RC factory-trimmed - * LSI - 32 KHz RC - * HSE - On-board crystal frequency is 25MHz - * LSE - 32.768 kHz - */ - -#define STM32_BOARD_XTAL 25000000ul - -#define STM32_HSI_FREQUENCY 16000000ul -#define STM32_LSI_FREQUENCY 32000 -#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL -#define STM32_LSE_FREQUENCY 32768 - -/* Main PLL Configuration. - * - * PLL source is HSE - * PLL_VCO = (STM32_HSE_FREQUENCY / PLLM) * PLLN - * = (25,000,000 / 25) * 336 - * = 336,000,000 - * SYSCLK = PLL_VCO / PLLP - * = 336,000,000 / 2 = 168,000,000 - * USB OTG FS, SDIO and RNG Clock - * = PLL_VCO / PLLQ - * = 48,000,000 - */ - -#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(25) -#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(336) -#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_2 -#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(7) - -#define STM32_SYSCLK_FREQUENCY 168000000ul - -/* AHB clock (HCLK) is SYSCLK (168MHz) */ - -#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ -#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY - -/* APB1 clock (PCLK1) is HCLK/4 (42MHz) */ - -#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd4 /* PCLK1 = HCLK / 4 */ -#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/4) - -/* Timers driven from APB1 will be twice PCLK1 */ - -#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) - -/* APB2 clock (PCLK2) is HCLK/2 (84MHz) */ - -#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLKd2 /* PCLK2 = HCLK / 2 */ -#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/2) - -/* Timers driven from APB2 will be twice PCLK2 */ - -#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM9_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM10_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM11_CLKIN (2*STM32_PCLK2_FREQUENCY) - -/* Timer Frequencies, if APBx is set to 1, frequency is same as APBx - * otherwise frequency is 2xAPBx. - * Note: TIM1,8-11 are on APB2, others on APB1 - */ - -#define BOARD_TIM2_FREQUENCY    STM32_APB1_TIM2_CLKIN -#define BOARD_TIM3_FREQUENCY    STM32_APB1_TIM3_CLKIN -#define BOARD_TIM4_FREQUENCY    STM32_APB1_TIM4_CLKIN -#define BOARD_TIM5_FREQUENCY    STM32_APB1_TIM5_CLKIN -#define BOARD_TIM6_FREQUENCY    STM32_APB1_TIM6_CLKIN -#define BOARD_TIM7_FREQUENCY    STM32_APB1_TIM7_CLKIN -#define BOARD_TIM12_FREQUENCY   STM32_APB1_TIM12_CLKIN -#define BOARD_TIM13_FREQUENCY   STM32_APB1_TIM13_CLKIN -#define BOARD_TIM14_FREQUENCY   STM32_APB1_TIM14_CLKIN - -#define BOARD_TIM1_FREQUENCY    STM32_APB2_TIM1_CLKIN -#define BOARD_TIM8_FREQUENCY    STM32_APB2_TIM8_CLKIN -#define BOARD_TIM9_FREQUENCY    STM32_APB2_TIM9_CLKIN -#define BOARD_TIM10_FREQUENCY   STM32_APB2_TIM10_CLKIN -#define BOARD_TIM11_FREQUENCY   STM32_APB2_TIM11_CLKIN - -/* SDIO dividers. Note that slower clocking is required when DMA is disabled - * in order to avoid RX overrun/TX underrun errors due to delayed responses - * to service FIFOs in interrupt driven mode. These values have not been - * tuned!!! - * - * SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(118+2)=400 KHz - */ - -#define SDIO_INIT_CLKDIV (118 << SDIO_CLKCR_CLKDIV_SHIFT) - -/* DMA ON: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(1+2)=16 MHz - * DMA OFF: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(2+2)=12 MHz - */ - -#ifdef CONFIG_SDIO_DMA -# define SDIO_MMCXFR_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT) -#else -# define SDIO_MMCXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT) -#endif - -/* DMA ON: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(1+2)=16 MHz - * DMA OFF: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(2+2)=12 MHz - */ - -#ifdef CONFIG_SDIO_DMA -# define SDIO_SDXFR_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT) -#else -# define SDIO_SDXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT) -#endif - -/* Ethernet *****************************************************************/ - -/* We need to provide clocking to the MII PHY via MCO1 (PA8) */ - -#if defined(CONFIG_NET) && defined(CONFIG_STM32_ETHMAC) - -# if !defined(CONFIG_STM32_MII) -# warning "CONFIG_STM32_MII required for Ethernet" -# elif !defined(CONFIG_STM32_MII_MCO1) -# warning "CONFIG_STM32_MII_MCO1 required for Ethernet MII" -# else - - /* Output HSE clock (25MHz) on MCO1 pin (PA8) to clock the PHY */ - -# define BOARD_CFGR_MC01_SOURCE RCC_CFGR_MCO1_HSE -# define BOARD_CFGR_MC01_DIVIDER RCC_CFGR_MCO1PRE_NONE - -# endif -#endif - -/* LED definitions **********************************************************/ - -/* If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs in - * any way. The following definitions are used to access individual LEDs. - */ - -/* LED index values for use with board_userled() */ - -#define BOARD_LED1 0 -#define BOARD_LED2 1 -#define BOARD_LED3 2 -#define BOARD_LED4 3 -#define BOARD_NLEDS 4 - -/* LED bits for use with board_userled_all() */ - -#define BOARD_LED1_BIT (1 << BOARD_LED1) -#define BOARD_LED2_BIT (1 << BOARD_LED2) -#define BOARD_LED3_BIT (1 << BOARD_LED3) -#define BOARD_LED4_BIT (1 << BOARD_LED4) - -/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the 4 LEDs on - * board the STM3240G-EVAL. - * The following definitions describe how NuttX controls the LEDs: - */ - -#define LED_STARTED 0 /* LED1 */ -#define LED_HEAPALLOCATE 1 /* LED2 */ -#define LED_IRQSENABLED 2 /* LED1 + LED2 */ -#define LED_STACKCREATED 3 /* LED3 */ -#define LED_INIRQ 4 /* LED1 + LED3 */ -#define LED_SIGNAL 5 /* LED2 + LED3 */ -#define LED_ASSERTION 6 /* LED1 + LED2 + LED3 */ -#define LED_PANIC 7 /* N/C + N/C + N/C + LED4 */ - -/* Button definitions *******************************************************/ - -/* The STM3240G-EVAL supports three buttons: */ - -#define BUTTON_WAKEUP 0 -#define BUTTON_TAMPER 1 -#define BUTTON_USER 2 - -#define NUM_BUTTONS 3 - -#define BUTTON_WAKEUP_BIT (1 << BUTTON_WAKEUP) -#define BUTTON_TAMPER_BIT (1 << BUTTON_TAMPER) -#define BUTTON_USER_BIT (1 << BUTTON_USER) - -/* SRAM definitions *********************************************************/ - -/* The 16 Mbit SRAM is connected to the STM32F407IGH6 FSMC bus which shares - * the same I/Os with the CAN1 bus. Jumper settings: - * - * JP1: Connect PE4 to SRAM as A20 - * JP2: onnect PE3 to SRAM as A19 - * - * JP3 and JP10 must not be fitted for SRAM and LCD application. - * JP3 and JP10 select CAN1 or CAN2 if fitted; neither if not fitted. - */ - -#if defined(CONFIG_STM32_FSMC) && defined(CONFIG_STM32_EXTERNAL_RAM) -# if defined(CONFIG_STM32_CAN1) || defined(CONFIG_STM32_CAN2) -# error "The STM3240G-EVAL cannot support both CAN and FSMC SRAM" -# endif -#endif - -/* This is the Bank1 SRAM2 address: */ - -#define BOARD_SRAM_BASE 0x64000000 -#define BOARD_SRAM_SIZE (2*1024*1024) - -/* Alternate function pin selections ****************************************/ - -/* UART3: - * - * - PC11 is MicroSDCard_D3 & RS232/IrDA_RX (JP22 open) - * - PC10 is MicroSDCard_D2 & RSS232/IrDA_TX - */ - -#define GPIO_USART3_RX (GPIO_USART3_RX_2|GPIO_SPEED_100MHz) -#define GPIO_USART3_TX (GPIO_USART3_TX_2|GPIO_SPEED_100MHz) - -/* Ethernet: - * - * - PA2 is ETH_MDIO - * - PC1 is ETH_MDC - * - PB5 is ETH_PPS_OUT - * - PH2 is ETH_MII_CRS - * - PH3 is ETH_MII_COL - * - PI10 is ETH_MII_RX_ER - * - PH6 is ETH_MII_RXD2 - * - PH7 is ETH_MII_RXD3 - * - PC3 is ETH_MII_TX_CLK - * - PC2 is ETH_MII_TXD2 - * - PB8 is ETH_MII_TXD3 - * - PA1 is ETH_MII_RX_CLK/ETH_RMII_REF_CLK - * - PA7 is ETH_MII_RX_DV/ETH_RMII_CRS_DV - * - PC4 is ETH_MII_RXD0/ETH_RMII_RXD0 - * - PC5 is ETH_MII_RXD1/ETH_RMII_RXD1 - * - PG11 is ETH_MII_TX_EN/ETH_RMII_TX_EN - * - PG13 is ETH_MII_TXD0/ETH_RMII_TXD0 - * - PG14 is ETH_MII_TXD1/ETH_RMII_TXD1 - */ - -#define GPIO_ETH_PPS_OUT (GPIO_ETH_PPS_OUT_1|GPIO_SPEED_100MHz) -#define GPIO_ETH_MII_CRS (GPIO_ETH_MII_CRS_2|GPIO_SPEED_100MHz) -#define GPIO_ETH_MII_COL (GPIO_ETH_MII_COL_2|GPIO_SPEED_100MHz) -#define GPIO_ETH_MII_RX_ER (GPIO_ETH_MII_RX_ER_2|GPIO_SPEED_100MHz) -#define GPIO_ETH_MII_RXD2 (GPIO_ETH_MII_RXD2_2|GPIO_SPEED_100MHz) -#define GPIO_ETH_MII_RXD3 (GPIO_ETH_MII_RXD3_2|GPIO_SPEED_100MHz) -#define GPIO_ETH_MII_TXD3 (GPIO_ETH_MII_TXD3_1|GPIO_SPEED_100MHz) -#define GPIO_ETH_MII_TX_EN (GPIO_ETH_MII_TX_EN_2|GPIO_SPEED_100MHz) -#define GPIO_ETH_MII_TXD0 (GPIO_ETH_MII_TXD0_2|GPIO_SPEED_100MHz) -#define GPIO_ETH_MII_TXD1 (GPIO_ETH_MII_TXD1_2|GPIO_SPEED_100MHz) -#define GPIO_ETH_RMII_TX_EN (GPIO_ETH_RMII_TX_EN_2|GPIO_SPEED_100MHz) -#define GPIO_ETH_RMII_TXD0 (GPIO_ETH_RMII_TXD0_2|GPIO_SPEED_100MHz) -#define GPIO_ETH_RMII_TXD1 (GPIO_ETH_RMII_TXD1_2|GPIO_SPEED_100MHz) - -/* PWM - * - * The STM3240G-Eval has no real on-board PWM devices, but the board can be - * configured to output a pulse train using the following: - * - * If FSMC is not used: - * TIM4 CH2OUT: PD13 FSMC_A18 / MC_TIM4_CH2OUT - * Daughterboard Extension Connector, CN3, pin 32 - * Motor Control Connector CN15, - * pin 33 -- not available unless you bridge SB14. - * - * TIM1 CH1OUT: PE9 FSMC_D6 - * Daughterboard Extension Connector, CN2, pin 24 - * - * TIM1_CH2OUT: PE11 FSMC_D8 - * Daughterboard Extension Connector, CN2, pin 26 - * - * TIM1_CH3OUT: PE13 FSMC_D10 - * Daughterboard Extension Connector, CN2, pin 28 - * - * TIM1_CH4OUT: PE14 FSMC_D11 - * Daughterboard Extension Connector, CN2, pin 29 - * - * If OTG FS is not used - * - * TIM1_CH3OUT: PA10 OTG_FS_ID - * Daughterboard Extension Connector, CN3, pin 14 - * - * TIM1_CH4OUT: PA11 OTG_FS_DM - * Daughterboard Extension Connector, CN3, pin 11 - * - * If DMCI is not used - * - * TIM8 CH1OUT: PI5 DCMI_VSYNC & MC - * Daughterboard Extension Connector, CN4, pin 4 - * - * TIM8_CH2OUT: PI6 DCMI_D6 & MC - * Daughterboard Extension Connector, CN4, pin 3 - * - * TIM8_CH3OUT: PI7 DCMI_D7 & MC - * Daughterboard Extension Connector, CN4, pin 2 - * - * If SDIO is not used - * - * TIM8_CH3OUT: PC8 MicroSDCard_D0 & MC - * Daughterboard Extension Connector, CN3, pin 18 - * - * TIM8_CH4OUT: PC9 MicroSDCard_D1 & I2S_CKIN (Need JP16 open) - * Daughterboard Extension Connector, CN3, pin 17 - * - * Others - * - * TIM8 CH1OUT: PC6 I2S_MCK & Smartcard_IO (JP21 open) - */ - -#if !defined(CONFIG_STM32_FSMC) -# define GPIO_TIM4_CH2OUT (GPIO_TIM4_CH2OUT_2|GPIO_SPEED_50MHz) -# define GPIO_TIM1_CH1OUT (GPIO_TIM1_CH1OUT_2|GPIO_SPEED_50MHz) -# define GPIO_TIM1_CH2OUT (GPIO_TIM1_CH2OUT_2|GPIO_SPEED_50MHz) -# define GPIO_TIM1_CH3OUT (GPIO_TIM1_CH3OUT_2|GPIO_SPEED_50MHz) -# define GPIO_TIM1_CH4OUT (GPIO_TIM1_CH4OUT_2|GPIO_SPEED_50MHz) -#elif !defined(CONFIG_STM32_OTGFS) -# define GPIO_TIM1_CH3OUT (GPIO_TIM1_CH3OUT_1|GPIO_SPEED_50MHz) -# define GPIO_TIM1_CH4OUT (GPIO_TIM1_CH4OUT_1|GPIO_SPEED_50MHz) -#endif - -#if !defined(CONFIG_STM32_DCMI) -# define GPIO_TIM8_CH1OUT (GPIO_TIM8_CH1OUT_2|GPIO_SPEED_50MHz) -# define GPIO_TIM8_CH2OUT (GPIO_TIM8_CH2OUT_2|GPIO_SPEED_50MHz) -# define GPIO_TIM8_CH3OUT (GPIO_TIM8_CH3OUT_2|GPIO_SPEED_50MHz) -#else -# define GPIO_TIM8_CH1OUT (GPIO_TIM8_CH1OUT_1|GPIO_SPEED_50MHz) -# if !defined(CONFIG_STM32_SDIO) -# define GPIO_TIM8_CH3OUT (GPIO_TIM8_CH3OUT_1|GPIO_SPEED_50MHz) -# endif -#endif - -#if !defined(CONFIG_STM32_SDIO) -# define GPIO_TIM8_CH4OUT (GPIO_TIM8_CH4OUT_1|GPIO_SPEED_50MHz) -#endif - -/* CAN - * - * Connector 10 (CN10) - * is DB-9 male connector that can be used with CAN1 or CAN2. - * - * JP10 connects CAN1_RX or CAN2_RX to the CAN transceiver - * JP3 connects CAN1_TX or CAN2_TX to the CAN transceiver - * - * CAN signals are then available on CN10 pins: - * - * CN10 Pin 7 = CANH - * CN10 Pin 2 = CANL - * - * Mapping to STM32 GPIO pins: - * - * PD0 = FSMC_D2 & CAN1_RX - * PD1 = FSMC_D3 & CAN1_TX - * PB13 = ULPI_D6 & CAN2_TX - * PB5 = ULPI_D7 & CAN2_RX - */ - -#define GPIO_CAN1_RX (GPIO_CAN1_RX_3|GPIO_SPEED_50MHz) -#define GPIO_CAN1_TX (GPIO_CAN1_TX_3|GPIO_SPEED_50MHz) - -#define GPIO_CAN2_RX (GPIO_CAN2_RX_2|GPIO_SPEED_50MHz) -#define GPIO_CAN2_TX (GPIO_CAN2_TX_1|GPIO_SPEED_50MHz) - -/* I2C. - * Only I2C1 is available on the STM3240G-EVAL. I2C1_SCL and I2C1_SDA are - * available on the following pins: - * - * - PB6 is I2C1_SCL - * - PB9 is I2C1_SDA - */ - -#define GPIO_I2C1_SCL (GPIO_I2C1_SCL_1|GPIO_SPEED_50MHz) -#define GPIO_I2C1_SDA (GPIO_I2C1_SDA_2|GPIO_SPEED_50MHz) - -/* DMA Channel/Stream Selections ********************************************/ - -/* Stream selections are arbitrary for now but might become important in the - * future if we set aside more DMA channels/streams. - * - * SDIO DMA - * DMAMAP_SDIO_1 = Channel 4, Stream 3 - * DMAMAP_SDIO_2 = Channel 4, Stream 6 - */ - -#define DMAMAP_SDIO DMAMAP_SDIO_1 - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -#ifndef __ASSEMBLY__ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: stm3240g_lcdclear - * - * Description: - * This is a non-standard LCD interface just for the STM3210E-EVAL board. - * Because of the various rotations, clearing the display in the normal - * way by writing a sequences of runs that covers the entire display can be - * very slow. Here the display is cleared by simply setting all GRAM - * memory to the specified color. - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_FSMC -void stm3240g_lcdclear(uint16_t color); -#endif - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ - -/* ETH MII/RMII inputs and MDC/MDIO + MCO1 */ - -#define GPIO_MCO1 (GPIO_MCO1_0|GPIO_SPEED_100MHz) -#define GPIO_ETH_MDC (GPIO_ETH_MDC_0|GPIO_SPEED_100MHz) -#define GPIO_ETH_MDIO (GPIO_ETH_MDIO_0|GPIO_SPEED_100MHz) -#define GPIO_ETH_MII_RX_CLK (GPIO_ETH_MII_RX_CLK_0|GPIO_SPEED_100MHz) -#define GPIO_ETH_MII_RX_DV (GPIO_ETH_MII_RX_DV_0|GPIO_SPEED_100MHz) -#define GPIO_ETH_MII_RXD0 (GPIO_ETH_MII_RXD0_0|GPIO_SPEED_100MHz) -#define GPIO_ETH_MII_RXD1 (GPIO_ETH_MII_RXD1_0|GPIO_SPEED_100MHz) -#define GPIO_ETH_MII_TX_CLK (GPIO_ETH_MII_TX_CLK_0|GPIO_SPEED_100MHz) -#define GPIO_ETH_MII_TXD2 (GPIO_ETH_MII_TXD2_0|GPIO_SPEED_100MHz) -#define GPIO_ETH_RMII_CRS_DV (GPIO_ETH_RMII_CRS_DV_0|GPIO_SPEED_100MHz) -#define GPIO_ETH_RMII_REF_CLK (GPIO_ETH_RMII_REF_CLK_0|GPIO_SPEED_100MHz) -#define GPIO_ETH_RMII_RXD0 (GPIO_ETH_RMII_RXD0_0|GPIO_SPEED_100MHz) -#define GPIO_ETH_RMII_RXD1 (GPIO_ETH_RMII_RXD1_0|GPIO_SPEED_100MHz) - -/* SDIO */ - -#define GPIO_SDIO_CK (GPIO_SDIO_CK_0|GPIO_SPEED_50MHz) -#define GPIO_SDIO_CMD (GPIO_SDIO_CMD_0|GPIO_SPEED_50MHz) -#define GPIO_SDIO_D0 (GPIO_SDIO_D0_0|GPIO_SPEED_50MHz) -#define GPIO_SDIO_D1 (GPIO_SDIO_D1_0|GPIO_SPEED_50MHz) -#define GPIO_SDIO_D2 (GPIO_SDIO_D2_0|GPIO_SPEED_50MHz) -#define GPIO_SDIO_D3 (GPIO_SDIO_D3_0|GPIO_SPEED_50MHz) - -/* USB OTG FS */ - -#define GPIO_OTGFS_DM (GPIO_OTGFS_DM_0|GPIO_SPEED_100MHz) -#define GPIO_OTGFS_DP (GPIO_OTGFS_DP_0|GPIO_SPEED_100MHz) -#define GPIO_OTGFS_ID (GPIO_OTGFS_ID_0|GPIO_SPEED_100MHz) -#define GPIO_OTGFS_SOF (GPIO_OTGFS_SOF_0|GPIO_SPEED_100MHz) - -/* DAC */ - -#define GPIO_DAC1_OUT1 GPIO_DAC1_OUT1_0 -#define GPIO_DAC1_OUT2 GPIO_DAC1_OUT2_0 - -/* FSMC SRAM/LCD */ - -#define GPIO_FSMC_A0 (GPIO_FSMC_A0_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A1 (GPIO_FSMC_A1_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A2 (GPIO_FSMC_A2_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A3 (GPIO_FSMC_A3_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A4 (GPIO_FSMC_A4_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A5 (GPIO_FSMC_A5_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A6 (GPIO_FSMC_A6_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A7 (GPIO_FSMC_A7_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A8 (GPIO_FSMC_A8_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A9 (GPIO_FSMC_A9_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A10 (GPIO_FSMC_A10_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A11 (GPIO_FSMC_A11_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A12 (GPIO_FSMC_A12_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A13 (GPIO_FSMC_A13_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A14 (GPIO_FSMC_A14_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A15 (GPIO_FSMC_A15_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A16 (GPIO_FSMC_A16_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A17 (GPIO_FSMC_A17_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A18 (GPIO_FSMC_A18_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A19 (GPIO_FSMC_A19_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A20 (GPIO_FSMC_A20_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A21 (GPIO_FSMC_A21_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A22 (GPIO_FSMC_A22_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A23 (GPIO_FSMC_A23_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A24 (GPIO_FSMC_A24_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A25 (GPIO_FSMC_A25_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_D0 (GPIO_FSMC_D0_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_D1 (GPIO_FSMC_D1_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_D2 (GPIO_FSMC_D2_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_D3 (GPIO_FSMC_D3_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_D4 (GPIO_FSMC_D4_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_D5 (GPIO_FSMC_D5_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_D6 (GPIO_FSMC_D6_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_D7 (GPIO_FSMC_D7_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_D8 (GPIO_FSMC_D8_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_D9 (GPIO_FSMC_D9_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_D10 (GPIO_FSMC_D10_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_D11 (GPIO_FSMC_D11_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_D12 (GPIO_FSMC_D12_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_D13 (GPIO_FSMC_D13_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_D14 (GPIO_FSMC_D14_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_D15 (GPIO_FSMC_D15_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_NOE (GPIO_FSMC_NOE_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_NWE (GPIO_FSMC_NWE_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_NE1 (GPIO_FSMC_NE1_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_NE2 (GPIO_FSMC_NE2_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_NE3 (GPIO_FSMC_NE3_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_NE4 (GPIO_FSMC_NE4_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_NBL0 (GPIO_FSMC_NBL0_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_NBL1 (GPIO_FSMC_NBL1_0|GPIO_SPEED_100MHz) - -#endif /* __BOARD_ARM_STM32_STM3240G_EVAL_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32/stm3240g-eval/kernel/Makefile b/boards/arm/stm32/stm3240g-eval/kernel/Makefile deleted file mode 100644 index 3aba5389f39f0..0000000000000 --- a/boards/arm/stm32/stm3240g-eval/kernel/Makefile +++ /dev/null @@ -1,94 +0,0 @@ -############################################################################ -# boards/arm/stm32/stm3240g-eval/kernel/Makefile -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/Make.defs - -# The entry point name (if none is provided in the .config file) - -CONFIG_INIT_ENTRYPOINT ?= user_start -ENTRYPT = $(patsubst "%",%,$(CONFIG_INIT_ENTRYPOINT)) - -# Get the paths to the libraries and the links script path in format that -# is appropriate for the host OS - -USER_LIBPATHS = $(addprefix -L,$(call CONVERT_PATH,$(addprefix $(TOPDIR)$(DELIM),$(dir $(USERLIBS))))) -USER_LDSCRIPT = -T $(call CONVERT_PATH,$(BOARD_DIR)$(DELIM)scripts$(DELIM)memory.ld) -USER_LDSCRIPT += -T $(call CONVERT_PATH,$(BOARD_DIR)$(DELIM)scripts$(DELIM)user-space.ld) -USER_HEXFILE += $(call CONVERT_PATH,$(TOPDIR)$(DELIM)nuttx_user.hex) -USER_SRECFILE += $(call CONVERT_PATH,$(TOPDIR)$(DELIM)nuttx_user.srec) -USER_BINFILE += $(call CONVERT_PATH,$(TOPDIR)$(DELIM)nuttx_user.bin) - -USER_LDFLAGS = --undefined=$(ENTRYPT) --entry=$(ENTRYPT) $(USER_LDSCRIPT) -USER_LDLIBS = $(patsubst lib%,-l%,$(basename $(notdir $(USERLIBS)))) -USER_LIBGCC = "${shell "$(CC)" $(ARCHCPUFLAGS) -print-libgcc-file-name}" - -# Source files - -CSRCS = stm32_userspace.c -COBJS = $(CSRCS:.c=$(OBJEXT)) -OBJS = $(COBJS) - -# Targets: - -all: $(TOPDIR)$(DELIM)nuttx_user.elf $(TOPDIR)$(DELIM)User.map -.PHONY: nuttx_user.elf depend clean distclean - -$(COBJS): %$(OBJEXT): %.c - $(call COMPILE, $<, $@) - -# Create the nuttx_user.elf file containing all of the user-mode code - -nuttx_user.elf: $(OBJS) - $(Q) $(LD) -o $@ $(USER_LDFLAGS) $(USER_LIBPATHS) $(OBJS) --start-group $(USER_LDLIBS) --end-group $(USER_LIBGCC) - -$(TOPDIR)$(DELIM)nuttx_user.elf: nuttx_user.elf - @echo "LD: nuttx_user.elf" - $(Q) cp -a nuttx_user.elf $(TOPDIR)$(DELIM)nuttx_user.elf -ifeq ($(CONFIG_INTELHEX_BINARY),y) - @echo "CP: nuttx_user.hex" - $(Q) $(OBJCOPY) $(OBJCOPYARGS) -O ihex nuttx_user.elf $(USER_HEXFILE) -endif -ifeq ($(CONFIG_MOTOROLA_SREC),y) - @echo "CP: nuttx_user.srec" - $(Q) $(OBJCOPY) $(OBJCOPYARGS) -O srec nuttx_user.elf $(USER_SRECFILE) -endif -ifeq ($(CONFIG_RAW_BINARY),y) - @echo "CP: nuttx_user.bin" - $(Q) $(OBJCOPY) $(OBJCOPYARGS) -O binary nuttx_user.elf $(USER_BINFILE) -endif - -$(TOPDIR)$(DELIM)User.map: nuttx_user.elf - @echo "MK: User.map" - $(Q) $(NM) nuttx_user.elf >$(TOPDIR)$(DELIM)User.map - $(Q) $(CROSSDEV)size nuttx_user.elf - -.depend: - -depend: .depend - -clean: - $(call DELFILE, nuttx_user.elf) - $(call DELFILE, "$(TOPDIR)$(DELIM)nuttx_user.*") - $(call DELFILE, "$(TOPDIR)$(DELIM)User.map") - $(call CLEAN) - -distclean: clean diff --git a/boards/arm/stm32/stm3240g-eval/kernel/stm32_userspace.c b/boards/arm/stm32/stm3240g-eval/kernel/stm32_userspace.c deleted file mode 100644 index f50a59be45218..0000000000000 --- a/boards/arm/stm32/stm3240g-eval/kernel/stm32_userspace.c +++ /dev/null @@ -1,110 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm3240g-eval/kernel/stm32_userspace.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include -#include -#include - -#if defined(CONFIG_BUILD_PROTECTED) && !defined(__KERNEL__) - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -#ifndef CONFIG_NUTTX_USERSPACE -# error "CONFIG_NUTTX_USERSPACE not defined" -#endif - -#if CONFIG_NUTTX_USERSPACE != 0x08040000 -# error "CONFIG_NUTTX_USERSPACE must be 0x08040000 to match memory.ld" -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -static struct userspace_data_s g_userspace_data = -{ - .us_heap = &g_mmheap, -}; - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/* These 'addresses' of these values are setup by the linker script. */ - -extern uint8_t _stext[]; /* Start of .text */ -extern uint8_t _etext[]; /* End_1 of .text + .rodata */ -extern const uint8_t _eronly[]; /* End+1 of read only section (.text + .rodata) */ -extern uint8_t _sdata[]; /* Start of .data */ -extern uint8_t _edata[]; /* End+1 of .data */ -extern uint8_t _sbss[]; /* Start of .bss */ -extern uint8_t _ebss[]; /* End+1 of .bss */ - -const struct userspace_s userspace locate_data(".userspace") = -{ - /* General memory map */ - - .us_entrypoint = CONFIG_INIT_ENTRYPOINT, - .us_textstart = (uintptr_t)_stext, - .us_textend = (uintptr_t)_etext, - .us_datasource = (uintptr_t)_eronly, - .us_datastart = (uintptr_t)_sdata, - .us_dataend = (uintptr_t)_edata, - .us_bssstart = (uintptr_t)_sbss, - .us_bssend = (uintptr_t)_ebss, - - /* User data memory structure */ - - .us_data = &g_userspace_data, - - /* Task/thread startup routines */ - - .task_startup = nxtask_startup, - - /* Signal handler trampoline */ - - .signal_handler = up_signal_handler, - - /* User-space work queue support (declared in include/nuttx/wqueue.h) */ - -#ifdef CONFIG_LIBC_USRWORK - .work_usrstart = work_usrstart, -#endif -}; - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -#endif /* CONFIG_BUILD_PROTECTED && !__KERNEL__ */ diff --git a/boards/arm/stm32/stm3240g-eval/scripts/Make.defs b/boards/arm/stm32/stm3240g-eval/scripts/Make.defs deleted file mode 100644 index 091ebb2629a44..0000000000000 --- a/boards/arm/stm32/stm3240g-eval/scripts/Make.defs +++ /dev/null @@ -1,41 +0,0 @@ -############################################################################ -# boards/arm/stm32/stm3240g-eval/scripts/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/.config -include $(TOPDIR)/tools/Config.mk -include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs - -LDSCRIPT = ld.script -ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) - -ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 - -CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) -CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) -CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -AFLAGS := $(CFLAGS) -D__ASSEMBLY__ - -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections -LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32/stm3240g-eval/scripts/kernel-space.ld b/boards/arm/stm32/stm3240g-eval/scripts/kernel-space.ld deleted file mode 100644 index 92d718a435cb1..0000000000000 --- a/boards/arm/stm32/stm3240g-eval/scripts/kernel-space.ld +++ /dev/null @@ -1,100 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm3240g-eval/scripts/kernel-space.ld - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* NOTE: This depends on the memory.ld script having been included prior to - * this script. - */ - -OUTPUT_ARCH(arm) -EXTERN(_vectors) -ENTRY(_stext) -SECTIONS -{ - .text : { - _stext = ABSOLUTE(.); - *(.vectors) - *(.text .text.*) - *(.fixup) - *(.gnu.warning) - *(.rodata .rodata.*) - *(.gnu.linkonce.t.*) - *(.glue_7) - *(.glue_7t) - *(.got) - *(.gcc_except_table) - *(.gnu.linkonce.r.*) - _etext = ABSOLUTE(.); - } > kflash - - .init_section : { - _sinit = ABSOLUTE(.); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) - KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) - _einit = ABSOLUTE(.); - } > kflash - - .ARM.extab : { - *(.ARM.extab*) - } > kflash - - __exidx_start = ABSOLUTE(.); - .ARM.exidx : { - *(.ARM.exidx*) - } > kflash - - __exidx_end = ABSOLUTE(.); - - _eronly = ABSOLUTE(.); - - .data : { - _sdata = ABSOLUTE(.); - *(.data .data.*) - *(.gnu.linkonce.d.*) - CONSTRUCTORS - . = ALIGN(4); - _edata = ABSOLUTE(.); - } > ksram AT > kflash - - .bss : { - _sbss = ABSOLUTE(.); - *(.bss .bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - . = ALIGN(8); - _ebss = ABSOLUTE(.); - } > ksram - - /* Stabs debugging sections */ - - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_info 0 : { *(.debug_info) } - .debug_line 0 : { *(.debug_line) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_aranges 0 : { *(.debug_aranges) } -} diff --git a/boards/arm/stm32/stm3240g-eval/scripts/ld.script b/boards/arm/stm32/stm3240g-eval/scripts/ld.script deleted file mode 100644 index 250db269b1f74..0000000000000 --- a/boards/arm/stm32/stm3240g-eval/scripts/ld.script +++ /dev/null @@ -1,126 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm3240g-eval/scripts/ld.script - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* The STM32F407VG has 1024Kb of FLASH beginning at address 0x0800:0000 and - * 192Kb of SRAM. SRAM is split up into three blocks: - * - * 1) 112Kb of SRAM beginning at address 0x2000:0000 - * 2) 16Kb of SRAM beginning at address 0x2001:c000 - * 3) 64Kb of CCM SRAM beginning at address 0x1000:0000 - * - * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 - * where the code expects to begin execution by jumping to the entry point in - * the 0x0800:0000 address - * range. - */ - -MEMORY -{ - flash (rx) : ORIGIN = 0x08000000, LENGTH = 1024K - sram (rwx) : ORIGIN = 0x20000000, LENGTH = 112K -} - -OUTPUT_ARCH(arm) -EXTERN(_vectors) -ENTRY(_stext) -SECTIONS -{ - .text : { - _stext = ABSOLUTE(.); - *(.vectors) - *(.text .text.*) - *(.fixup) - *(.gnu.warning) - *(.rodata .rodata.*) - *(.gnu.linkonce.t.*) - *(.glue_7) - *(.glue_7t) - *(.got) - *(.gcc_except_table) - *(.gnu.linkonce.r.*) - _etext = ABSOLUTE(.); - } > flash - - .init_section : ALIGN(4) { - _sinit = ABSOLUTE(.); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) - KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) - _einit = ABSOLUTE(.); - } > flash - - .ARM.extab : ALIGN(4) { - *(.ARM.extab*) - } > flash - - .ARM.exidx : ALIGN(4) { - __exidx_start = ABSOLUTE(.); - *(.ARM.exidx*) - __exidx_end = ABSOLUTE(.); - } > flash - - .tdata : { - _stdata = ABSOLUTE(.); - *(.tdata .tdata.* .gnu.linkonce.td.*); - _etdata = ABSOLUTE(.); - } > flash - - .tbss : { - _stbss = ABSOLUTE(.); - *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); - _etbss = ABSOLUTE(.); - } > flash - - _eronly = ABSOLUTE(.); - - .data : ALIGN(4) { - _sdata = ABSOLUTE(.); - *(.data .data.*) - *(.gnu.linkonce.d.*) - CONSTRUCTORS - . = ALIGN(4); - _edata = ABSOLUTE(.); - } > sram AT > flash - - .bss : ALIGN(4) { - _sbss = ABSOLUTE(.); - *(.bss .bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - . = ALIGN(4); - _ebss = ABSOLUTE(.); - } > sram - - /* Stabs debugging sections. */ - - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_info 0 : { *(.debug_info) } - .debug_line 0 : { *(.debug_line) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_aranges 0 : { *(.debug_aranges) } -} diff --git a/boards/arm/stm32/stm3240g-eval/scripts/memory.ld b/boards/arm/stm32/stm3240g-eval/scripts/memory.ld deleted file mode 100644 index 7eeff47560d99..0000000000000 --- a/boards/arm/stm32/stm3240g-eval/scripts/memory.ld +++ /dev/null @@ -1,87 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm3240g-eval/scripts/memory.ld - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* The STM32F407VG has 1024Kb of FLASH beginning at address 0x0800:0000 and - * 192Kb of SRAM. SRAM is split up into three blocks: - * - * 1) 112KB of SRAM beginning at address 0x2000:0000 - * 2) 16KB of SRAM beginning at address 0x2001:c000 - * 3) 64KB of CCM SRAM beginning at address 0x1000:0000 - * - * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 - * where the code expects to begin execution by jumping to the entry point in - * the 0x0800:0000 address range. - * - * For MPU support, the kernel-mode NuttX section is assumed to be 256Kb of - * FLASH and 4Kb of SRAM. That is an excessive amount for the kernel which - * should fit into 64KB and, of course, can be optimized as needed (See - * also boards/arm/stm32/stm3240g-eval/scripts/kernel-space.ld). Allowing the - * additional does permit addition debug instrumentation to be added to the - * kernel space without overflowing the partition. - * - * Alignment of the user space FLASH partition is also a critical factor: - * The user space FLASH partition will be spanned with a single region of - * size 2**n bytes. The alignment of the user-space region must be the same. - * As a consequence, as the user-space increases in size, the alignment - * requirement also increases. - * - * This alignment requirement means that the largest user space FLASH region - * you can have will be 512KB at it would have to be positioned at - * 0x08800000. If you change this address, don't forget to change the - * CONFIG_NUTTX_USERSPACE configuration setting to match and to modify - * the check in kernel/userspace.c. - * - * For the same reasons, the maximum size of the SRAM mapping is limited to - * 4KB. Both of these alignment limitations could be reduced by using - * multiple regions to map the FLASH/SDRAM range or perhaps with some - * clever use of subregions. - * - * A detailed memory map for the 112KB SRAM region is as follows: - * - * 0x20000 0000: Kernel .data region. Typical size: 0.1KB - * ------- ---- Kernel .bss region. Typical size: 1.8KB - * 0x20000 0800: Kernel IDLE thread stack (approximate). Size is - * determined by CONFIG_IDLETHREAD_STACKSIZE and - * adjustments for alignment. Typical is 1KB. - * ------- ---- Padded to 4KB - * 0x20000 1000: User .data region. Size is variable. - * ------- ---- User .bss region Size is variable. - * 0x20000 2000: Beginning of kernel heap. Size determined by - * CONFIG_MM_KERNEL_HEAPSIZE. - * ------- ---- Beginning of user heap. Can vary with other settings. - * 0x20001 c000: End+1 of CPU RAM - */ - -MEMORY -{ - /* 1024Kb FLASH */ - - kflash (rx) : ORIGIN = 0x08000000, LENGTH = 256K - uflash (rx) : ORIGIN = 0x08040000, LENGTH = 256K - xflash (rx) : ORIGIN = 0x08080000, LENGTH = 512K - - /* 112Kb of contiguous SRAM */ - - ksram (rwx) : ORIGIN = 0x20000000, LENGTH = 6K - usram (rwx) : ORIGIN = 0x20001800, LENGTH = 4K - xsram (rwx) : ORIGIN = 0x20002800, LENGTH = 102K -} diff --git a/boards/arm/stm32/stm3240g-eval/scripts/user-space.ld b/boards/arm/stm32/stm3240g-eval/scripts/user-space.ld deleted file mode 100644 index 80a6572aa6493..0000000000000 --- a/boards/arm/stm32/stm3240g-eval/scripts/user-space.ld +++ /dev/null @@ -1,101 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm3240g-eval/scripts/user-space.ld - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* NOTE: This depends on the memory.ld script having been included prior to - * this script. - */ - -OUTPUT_ARCH(arm) -SECTIONS -{ - .userspace : { - *(.userspace) - } > uflash - - .text : { - _stext = ABSOLUTE(.); - *(.text .text.*) - *(.fixup) - *(.gnu.warning) - *(.rodata .rodata.*) - *(.gnu.linkonce.t.*) - *(.glue_7) - *(.glue_7t) - *(.got) - *(.gcc_except_table) - *(.gnu.linkonce.r.*) - _etext = ABSOLUTE(.); - } > uflash - - .init_section : { - _sinit = ABSOLUTE(.); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) - KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) - _einit = ABSOLUTE(.); - } > uflash - - .ARM.extab : { - *(.ARM.extab*) - } > uflash - - __exidx_start = ABSOLUTE(.); - .ARM.exidx : { - *(.ARM.exidx*) - } > uflash - - __exidx_end = ABSOLUTE(.); - - _eronly = ABSOLUTE(.); - - .data : { - _sdata = ABSOLUTE(.); - *(.data .data.*) - *(.gnu.linkonce.d.*) - CONSTRUCTORS - . = ALIGN(4); - _edata = ABSOLUTE(.); - } > usram AT > uflash - - .bss : { - _sbss = ABSOLUTE(.); - *(.bss .bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - . = ALIGN(8); - _ebss = ABSOLUTE(.); - } > usram - - /* Stabs debugging sections */ - - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_info 0 : { *(.debug_info) } - .debug_line 0 : { *(.debug_line) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_aranges 0 : { *(.debug_aranges) } -} diff --git a/boards/arm/stm32/stm3240g-eval/src/CMakeLists.txt b/boards/arm/stm32/stm3240g-eval/src/CMakeLists.txt deleted file mode 100644 index c8c5aa4f724e1..0000000000000 --- a/boards/arm/stm32/stm3240g-eval/src/CMakeLists.txt +++ /dev/null @@ -1,62 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/stm3240g-eval/src/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -set(SRCS stm32_boot.c stm32_bringup.c stm32_spi.c) - -if(CONFIG_ARCH_LEDS) - list(APPEND SRCS stm32_autoleds.c) -else() - list(APPEND SRCS stm32_userleds.c) -endif() - -if(CONFIG_ARCH_BUTTONS) - list(APPEND SRCS stm32_buttons.c) -endif() - -if(CONFIG_STM32_OTGFS) - list(APPEND SRCS stm32_usb.c) -endif() - -if(CONFIG_STM32_FSMC) - list(APPEND SRCS stm32_lcd.c stm32_selectlcd.c stm32_deselectlcd.c) - list(APPEND SRCS stm32_selectsram.c stm32_deselectsram.c stm32_extmem.c) -endif() - -if(CONFIG_ADC) - list(APPEND SRCS stm32_adc.c) -endif() - -if(CONFIG_PWM) - list(APPEND SRCS stm32_pwm.c) -endif() - -if(CONFIG_STM32_CAN_CHARDRIVER) - list(APPEND SRCS stm32_can.c) -endif() - -if(CONFIG_INPUT_STMPE811) - list(APPEND SRCS stm32_stmpe811.c) -endif() - -target_sources(board PRIVATE ${SRCS}) - -set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/ld.script") diff --git a/boards/arm/stm32/stm3240g-eval/src/Make.defs b/boards/arm/stm32/stm3240g-eval/src/Make.defs deleted file mode 100644 index 04d1ecfdd0b22..0000000000000 --- a/boards/arm/stm32/stm3240g-eval/src/Make.defs +++ /dev/null @@ -1,64 +0,0 @@ -############################################################################ -# boards/arm/stm32/stm3240g-eval/src/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/Make.defs - -CSRCS = stm32_boot.c stm32_bringup.c stm32_spi.c - -ifeq ($(CONFIG_ARCH_LEDS),y) -CSRCS += stm32_autoleds.c -else -CSRCS += stm32_userleds.c -endif - -ifeq ($(CONFIG_ARCH_BUTTONS),y) -CSRCS += stm32_buttons.c -endif - -ifeq ($(CONFIG_STM32_OTGFS),y) -CSRCS += stm32_usb.c -endif - -ifeq ($(CONFIG_STM32_FSMC),y) -CSRCS += stm32_lcd.c stm32_selectlcd.c stm32_deselectlcd.c -CSRCS += stm32_selectsram.c stm32_deselectsram.c stm32_extmem.c -endif - -ifeq ($(CONFIG_ADC),y) -CSRCS += stm32_adc.c -endif - -ifeq ($(CONFIG_PWM),y) -CSRCS += stm32_pwm.c -endif - -ifeq ($(CONFIG_STM32_CAN_CHARDRIVER),y) -CSRCS += stm32_can.c -endif - -ifeq ($(CONFIG_INPUT_STMPE811),y) -CSRCS += stm32_stmpe811.c -endif - -DEPPATH += --dep-path board -VPATH += :board -CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/stm3240g-eval/src/stm32_adc.c b/boards/arm/stm32/stm3240g-eval/src/stm32_adc.c deleted file mode 100644 index bfeaca3cf336d..0000000000000 --- a/boards/arm/stm32/stm3240g-eval/src/stm32_adc.c +++ /dev/null @@ -1,157 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm3240g-eval/src/stm32_adc.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32_pwm.h" -#include "stm3240g-eval.h" - -#ifdef CONFIG_ADC - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -/* Up to 3 ADC interfaces are supported */ - -#if STM32_NADC < 3 -# undef CONFIG_STM32_ADC3 -#endif - -#if STM32_NADC < 2 -# undef CONFIG_STM32_ADC2 -#endif - -#if STM32_NADC < 1 -# undef CONFIG_STM32_ADC1 -#endif - -#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) || defined(CONFIG_STM32_ADC3) -#ifndef CONFIG_STM32_ADC3 -# warning "Channel information only available for ADC3" -#endif - -/* The number of ADC channels in the conversion list */ - -#define ADC3_NCHANNELS 1 - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* The STM3240G-EVAL has a 10 Kohm potentiometer RV1 connected to PF9 of - * STM32F407IGH6 on the board: TIM14_CH1/FSMC_CD/ADC3_IN7 - */ - -/* Identifying number of each ADC channel: Variable Resistor. */ - -#ifdef CONFIG_STM32_ADC3 -static const uint8_t g_chanlist[ADC3_NCHANNELS] = -{ - 7 -}; - -/* Configurations of pins used byte each ADC channels */ - -static const uint32_t g_pinlist[ADC3_NCHANNELS] = -{ - GPIO_ADC3_IN7 -}; -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_adc_setup - * - * Description: - * Initialize ADC and register the ADC driver. - * - ****************************************************************************/ - -int stm32_adc_setup(void) -{ -#ifdef CONFIG_STM32_ADC3 - static bool initialized = false; - struct adc_dev_s *adc; - int ret; - int i; - - /* Check if we have already initialized */ - - if (!initialized) - { - /* Configure the pins as analog inputs for the selected channels */ - - for (i = 0; i < ADC3_NCHANNELS; i++) - { - stm32_configgpio(g_pinlist[i]); - } - - /* Call stm32_adcinitialize() to get an instance of the ADC interface */ - - adc = stm32_adcinitialize(3, g_chanlist, ADC3_NCHANNELS); - if (adc == NULL) - { - aerr("ERROR: Failed to get ADC interface\n"); - return -ENODEV; - } - - /* Register the ADC driver at "/dev/adc0" */ - - ret = adc_register("/dev/adc0", adc); - if (ret < 0) - { - aerr("ERROR: adc_register failed: %d\n", ret); - return ret; - } - - /* Now we are initialized */ - - initialized = true; - } - - return OK; -#else - return -ENOSYS; -#endif -} - -#endif /* CONFIG_STM32_ADC1 || CONFIG_STM32_ADC2 || CONFIG_STM32_ADC3 */ -#endif /* CONFIG_ADC */ diff --git a/boards/arm/stm32/stm3240g-eval/src/stm32_autoleds.c b/boards/arm/stm32/stm3240g-eval/src/stm32_autoleds.c deleted file mode 100644 index fc90a9ad31930..0000000000000 --- a/boards/arm/stm32/stm3240g-eval/src/stm32_autoleds.c +++ /dev/null @@ -1,232 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm3240g-eval/src/stm32_autoleds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32.h" -#include "stm3240g-eval.h" - -#ifdef CONFIG_ARCH_LEDS - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* The following definitions map the encoded LED setting to GPIO settings */ - -#define STM3210E_LED1 (1 << 0) -#define STM3210E_LED2 (1 << 1) -#define STM3210E_LED3 (1 << 2) -#define STM3210E_LED4 (1 << 3) - -#define ON_SETBITS_SHIFT (0) -#define ON_CLRBITS_SHIFT (4) -#define OFF_SETBITS_SHIFT (8) -#define OFF_CLRBITS_SHIFT (12) - -#define ON_BITS(v) ((v) & 0xff) -#define OFF_BITS(v) (((v) >> 8) & 0x0ff) -#define SETBITS(b) ((b) & 0x0f) -#define CLRBITS(b) (((b) >> 4) & 0x0f) - -#define ON_SETBITS(v) (SETBITS(ON_BITS(v)) -#define ON_CLRBITS(v) (CLRBITS(ON_BITS(v)) -#define OFF_SETBITS(v) (SETBITS(OFF_BITS(v)) -#define OFF_CLRBITS(v) (CLRBITS(OFF_BITS(v)) - -#define LED_STARTED_ON_SETBITS ((STM3210E_LED1) << ON_SETBITS_SHIFT) -#define LED_STARTED_ON_CLRBITS ((STM3210E_LED2|STM3210E_LED3|STM3210E_LED4) << ON_CLRBITS_SHIFT) -#define LED_STARTED_OFF_SETBITS (0 << OFF_SETBITS_SHIFT) -#define LED_STARTED_OFF_CLRBITS ((STM3210E_LED1|STM3210E_LED2|STM3210E_LED3|STM3210E_LED4) << OFF_CLRBITS_SHIFT) - -#define LED_HEAPALLOCATE_ON_SETBITS ((STM3210E_LED2) << ON_SETBITS_SHIFT) -#define LED_HEAPALLOCATE_ON_CLRBITS ((STM3210E_LED1|STM3210E_LED3|STM3210E_LED4) << ON_CLRBITS_SHIFT) -#define LED_HEAPALLOCATE_OFF_SETBITS ((STM3210E_LED1) << OFF_SETBITS_SHIFT) -#define LED_HEAPALLOCATE_OFF_CLRBITS ((STM3210E_LED2|STM3210E_LED3|STM3210E_LED4) << OFF_CLRBITS_SHIFT) - -#define LED_IRQSENABLED_ON_SETBITS ((STM3210E_LED1|STM3210E_LED2) << ON_SETBITS_SHIFT) -#define LED_IRQSENABLED_ON_CLRBITS ((STM3210E_LED3|STM3210E_LED4) << ON_CLRBITS_SHIFT) -#define LED_IRQSENABLED_OFF_SETBITS ((STM3210E_LED2) << OFF_SETBITS_SHIFT) -#define LED_IRQSENABLED_OFF_CLRBITS ((STM3210E_LED1|STM3210E_LED3|STM3210E_LED4) << OFF_CLRBITS_SHIFT) - -#define LED_STACKCREATED_ON_SETBITS ((STM3210E_LED3) << ON_SETBITS_SHIFT) -#define LED_STACKCREATED_ON_CLRBITS ((STM3210E_LED1|STM3210E_LED2|STM3210E_LED4) << ON_CLRBITS_SHIFT) -#define LED_STACKCREATED_OFF_SETBITS ((STM3210E_LED1|STM3210E_LED2) << OFF_SETBITS_SHIFT) -#define LED_STACKCREATED_OFF_CLRBITS ((STM3210E_LED3|STM3210E_LED4) << OFF_CLRBITS_SHIFT) - -#define LED_INIRQ_ON_SETBITS ((STM3210E_LED1) << ON_SETBITS_SHIFT) -#define LED_INIRQ_ON_CLRBITS ((0) << ON_CLRBITS_SHIFT) -#define LED_INIRQ_OFF_SETBITS ((0) << OFF_SETBITS_SHIFT) -#define LED_INIRQ_OFF_CLRBITS ((STM3210E_LED1) << OFF_CLRBITS_SHIFT) - -#define LED_SIGNAL_ON_SETBITS ((STM3210E_LED2) << ON_SETBITS_SHIFT) -#define LED_SIGNAL_ON_CLRBITS ((0) << ON_CLRBITS_SHIFT) -#define LED_SIGNAL_OFF_SETBITS ((0) << OFF_SETBITS_SHIFT) -#define LED_SIGNAL_OFF_CLRBITS ((STM3210E_LED2) << OFF_CLRBITS_SHIFT) - -#define LED_ASSERTION_ON_SETBITS ((STM3210E_LED4) << ON_SETBITS_SHIFT) -#define LED_ASSERTION_ON_CLRBITS ((0) << ON_CLRBITS_SHIFT) -#define LED_ASSERTION_OFF_SETBITS ((0) << OFF_SETBITS_SHIFT) -#define LED_ASSERTION_OFF_CLRBITS ((STM3210E_LED4) << OFF_CLRBITS_SHIFT) - -#define LED_PANIC_ON_SETBITS ((STM3210E_LED4) << ON_SETBITS_SHIFT) -#define LED_PANIC_ON_CLRBITS ((0) << ON_CLRBITS_SHIFT) -#define LED_PANIC_OFF_SETBITS ((0) << OFF_SETBITS_SHIFT) -#define LED_PANIC_OFF_CLRBITS ((STM3210E_LED4) << OFF_CLRBITS_SHIFT) - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -static const uint16_t g_ledbits[8] = -{ - (LED_STARTED_ON_SETBITS | LED_STARTED_ON_CLRBITS | - LED_STARTED_OFF_SETBITS | LED_STARTED_OFF_CLRBITS), - - (LED_HEAPALLOCATE_ON_SETBITS | LED_HEAPALLOCATE_ON_CLRBITS | - LED_HEAPALLOCATE_OFF_SETBITS | LED_HEAPALLOCATE_OFF_CLRBITS), - - (LED_IRQSENABLED_ON_SETBITS | LED_IRQSENABLED_ON_CLRBITS | - LED_IRQSENABLED_OFF_SETBITS | LED_IRQSENABLED_OFF_CLRBITS), - - (LED_STACKCREATED_ON_SETBITS | LED_STACKCREATED_ON_CLRBITS | - LED_STACKCREATED_OFF_SETBITS | LED_STACKCREATED_OFF_CLRBITS), - - (LED_INIRQ_ON_SETBITS | LED_INIRQ_ON_CLRBITS | - LED_INIRQ_OFF_SETBITS | LED_INIRQ_OFF_CLRBITS), - - (LED_SIGNAL_ON_SETBITS | LED_SIGNAL_ON_CLRBITS | - LED_SIGNAL_OFF_SETBITS | LED_SIGNAL_OFF_CLRBITS), - - (LED_ASSERTION_ON_SETBITS | LED_ASSERTION_ON_CLRBITS | - LED_ASSERTION_OFF_SETBITS | LED_ASSERTION_OFF_CLRBITS), - - (LED_PANIC_ON_SETBITS | LED_PANIC_ON_CLRBITS | - LED_PANIC_OFF_SETBITS | LED_PANIC_OFF_CLRBITS) -}; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -static inline void led_clrbits(unsigned int clrbits) -{ - if ((clrbits & STM3210E_LED1) != 0) - { - stm32_gpiowrite(GPIO_LED1, false); - } - - if ((clrbits & STM3210E_LED2) != 0) - { - stm32_gpiowrite(GPIO_LED2, false); - } - - if ((clrbits & STM3210E_LED3) != 0) - { - stm32_gpiowrite(GPIO_LED3, false); - } - - if ((clrbits & STM3210E_LED4) != 0) - { - stm32_gpiowrite(GPIO_LED4, false); - } -} - -static inline void led_setbits(unsigned int setbits) -{ - if ((setbits & STM3210E_LED1) != 0) - { - stm32_gpiowrite(GPIO_LED1, true); - } - - if ((setbits & STM3210E_LED2) != 0) - { - stm32_gpiowrite(GPIO_LED2, true); - } - - if ((setbits & STM3210E_LED3) != 0) - { - stm32_gpiowrite(GPIO_LED3, true); - } - - if ((setbits & STM3210E_LED4) != 0) - { - stm32_gpiowrite(GPIO_LED4, true); - } -} - -static void led_setonoff(unsigned int bits) -{ - led_clrbits(CLRBITS(bits)); - led_setbits(SETBITS(bits)); -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_led_initialize - ****************************************************************************/ - -void stm32_led_initialize(void) -{ - /* Configure LED1-4 GPIOs for output */ - - stm32_configgpio(GPIO_LED1); - stm32_configgpio(GPIO_LED2); - stm32_configgpio(GPIO_LED3); - stm32_configgpio(GPIO_LED4); -} - -/**************************************************************************** - * Name: board_autoled_on - ****************************************************************************/ - -void board_autoled_on(int led) -{ - led_setonoff(ON_BITS(g_ledbits[led])); -} - -/**************************************************************************** - * Name: board_autoled_off - ****************************************************************************/ - -void board_autoled_off(int led) -{ - led_setonoff(OFF_BITS(g_ledbits[led])); -} - -#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/stm3240g-eval/src/stm32_boot.c b/boards/arm/stm32/stm3240g-eval/src/stm32_boot.c deleted file mode 100644 index 4f59c13c407ec..0000000000000 --- a/boards/arm/stm32/stm3240g-eval/src/stm32_boot.c +++ /dev/null @@ -1,118 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm3240g-eval/src/stm32_boot.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include - -#include "stm3240g-eval.h" - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_boardinitialize - * - * Description: - * All STM32 architectures must provide the following entry point. - * This entry point is called early in the initialization -- after all - * memory has been configured and mapped but before any devices have been - * initialized. - * - ****************************************************************************/ - -void stm32_boardinitialize(void) -{ -#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || defined(CONFIG_STM32_SPI3) - /* Configure SPI chip selects if 1) SPI is not disabled, and 2) - * the weak function stm32_spidev_initialize() has been brought into the - * link. - */ - - if (stm32_spidev_initialize) - { - stm32_spidev_initialize(); - } -#endif - -#ifdef CONFIG_STM32_FSMC - /* If the FSMC is enabled, then enable SRAM access */ - - stm32_selectsram(); -#endif - -#ifdef CONFIG_STM32_OTGFS - /* Initialize USB if the 1) OTG FS controller is in the configuration and - * 2) disabled, and 3) the weak function stm32_usbinitialize() has been - * brought the weak function stm32_usbinitialize() has been brought into - * the build. - * Presumably either CONFIG_USBDEV or CONFIG_USBHOST is also selected. - */ - - if (stm32_usbinitialize) - { - stm32_usbinitialize(); - } -#endif - -#ifdef CONFIG_ARCH_LEDS - /* Configure on-board LEDs if LED support has been selected. */ - - stm32_led_initialize(); -#endif -} - -/**************************************************************************** - * Name: board_late_initialize - * - * Description: - * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional - * initialization call will be performed in the boot-up sequence to a - * function called board_late_initialize(). board_late_initialize() will be - * called immediately after up_initialize() is called and just before the - * initial application is started. This additional initialization phase - * may be used, for example, to initialize board-specific device drivers. - * - ****************************************************************************/ - -#ifdef CONFIG_BOARD_LATE_INITIALIZE -void board_late_initialize(void) -{ - /* Perform the board initialization on the start-up thread. Some - * initializations may fail in this case due to the limited capability of - * the start-up thread. - */ - - stm32_bringup(); -} -#endif diff --git a/boards/arm/stm32/stm3240g-eval/src/stm32_bringup.c b/boards/arm/stm32/stm3240g-eval/src/stm32_bringup.c deleted file mode 100644 index 016041c919078..0000000000000 --- a/boards/arm/stm32/stm3240g-eval/src/stm32_bringup.c +++ /dev/null @@ -1,390 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm3240g-eval/src/stm32_bringup.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include - -#include -#include -#include - -#ifdef CONFIG_STM32_SPI1 -# include -# include -#endif - -#ifdef CONFIG_STM32_SDIO -# include -# include -#endif - -#ifdef CONFIG_STM32_OTGFS -# include "stm32_usbhost.h" -#endif - -#ifdef CONFIG_RTC_DRIVER -# include -# include "stm32_rtc.h" -#endif - -#ifdef CONFIG_VIDEO_FB -# include -#endif - -#ifdef CONFIG_INPUT_STMPE811 -# include -#endif - -#include "stm32.h" -#include "stm32_i2c.h" -#include "stm3240g-eval.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -/* For now, don't build in any SPI1 support -- NSH is not using it */ - -#undef CONFIG_STM32_SPI1 - -/* Assume that we support everything until convinced otherwise */ - -#define HAVE_MMCSD 1 -#define HAVE_USBDEV 1 -#define HAVE_USBHOST 1 -#define HAVE_RTC_DRIVER 1 - -/* Can't support MMC/SD features if mountpoints are disabled or if SDIO - * support is not enabled. - */ - -#if defined(CONFIG_DISABLE_MOUNTPOINT) || !defined(CONFIG_STM32_SDIO) -# undef HAVE_MMCSD -#endif - -/* Default MMC/SD minor number */ - -#ifdef HAVE_MMCSD -# ifndef CONFIG_NSH_MMCSDMINOR -# define CONFIG_NSH_MMCSDMINOR 0 -# endif - -/* Default MMC/SD SLOT number */ - -# if defined(CONFIG_NSH_MMCSDSLOTNO) && CONFIG_NSH_MMCSDSLOTNO != 0 -# error "Only one MMC/SD slot" -# undef CONFIG_NSH_MMCSDSLOTNO -# endif - -# ifndef CONFIG_NSH_MMCSDSLOTNO -# define CONFIG_NSH_MMCSDSLOTNO 0 -# endif -#endif - -/* Can't support USB host or device features if USB OTG FS is not enabled */ - -#ifndef CONFIG_STM32_OTGFS -# undef HAVE_USBDEV -# undef HAVE_USBHOST -#endif - -/* Can't support USB device is USB device is not enabled */ - -#ifndef CONFIG_USBDEV -# undef HAVE_USBDEV -#endif - -/* Can't support USB host is USB host is not enabled */ - -#ifndef CONFIG_USBHOST -# undef HAVE_USBHOST -#endif - -/* Check if we can support the RTC driver */ - -#if !defined(CONFIG_RTC) || !defined(CONFIG_RTC_DRIVER) -# undef HAVE_RTC_DRIVER -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_i2c_register - * - * Description: - * Register one I2C drivers for the I2C tool. - * - ****************************************************************************/ - -#ifdef HAVE_I2CTOOL -static void stm32_i2c_register(int bus) -{ - struct i2c_master_s *i2c; - int ret; - - i2c = stm32_i2cbus_initialize(bus); - if (i2c == NULL) - { - _err("ERROR: Failed to get I2C%d interface\n", bus); - } - else - { - ret = i2c_register(i2c, bus); - if (ret < 0) - { - _err("ERROR: Failed to register I2C%d driver: %d\n", bus, ret); - stm32_i2cbus_uninitialize(i2c); - } - } -} -#endif - -/**************************************************************************** - * Name: stm32_i2ctool - * - * Description: - * Register I2C drivers for the I2C tool. - * - ****************************************************************************/ - -#ifdef HAVE_I2CTOOL -static void stm32_i2ctool(void) -{ -#ifdef CONFIG_STM32_I2C1 - stm32_i2c_register(1); -#endif -#ifdef CONFIG_STM32_I2C2 - stm32_i2c_register(2); -#endif -#ifdef CONFIG_STM32_I2C3 - stm32_i2c_register(3); -#endif -} -#else -# define stm32_i2ctool() -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_bringup - * - * Description: - * Perform architecture-specific initialization - * - * CONFIG_BOARD_LATE_INITIALIZE=y : - * Called from board_late_initialize(). - * - ****************************************************************************/ - -int stm32_bringup(void) -{ -#ifdef HAVE_RTC_DRIVER - struct rtc_lowerhalf_s *lower; -#endif -#ifdef CONFIG_STM32_SPI1 - struct spi_dev_s *spi; - struct mtd_dev_s *mtd; -#endif -#ifdef HAVE_MMCSD - struct sdio_dev_s *sdio; -#endif - int ret; - - /* Register I2C drivers on behalf of the I2C tool */ - - stm32_i2ctool(); - -#ifdef HAVE_RTC_DRIVER - /* Instantiate the STM32 lower-half RTC driver */ - - lower = stm32_rtc_lowerhalf(); - if (!lower) - { - syslog(LOG_ERR, - "ERROR: Failed to instantiate the RTC lower-half driver\n"); - } - else - { - /* Bind the lower half driver and register the combined RTC driver - * as /dev/rtc0 - */ - - ret = rtc_initialize(0, lower); - if (ret < 0) - { - syslog(LOG_ERR, - "ERROR: Failed to bind/register the RTC driver: %d\n", - ret); - } - } -#endif - - /* Configure SPI-based devices */ - -#ifdef CONFIG_STM32_SPI1 - /* Get the SPI port */ - - spi = stm32_spibus_initialize(1); - if (!spi) - { - syslog(LOG_ERR, "ERROR: Failed to initialize SPI port 0\n"); - } - else - { - /* Now bind the SPI interface to the M25P64/128 SPI FLASH driver */ - - mtd = m25p_initialize(spi); - if (!mtd) - { - syslog(LOG_ERR, - "ERROR: Failed to bind SPI port 0 to SPI FLASH driver\n"); - } - } - -#warning "Now what are we going to do with this SPI FLASH driver?" -#endif - -#ifdef HAVE_MMCSD - /* Mount the SDIO-based MMC/SD block driver */ - - /* First, get an instance of the SDIO interface */ - - sdio = sdio_initialize(CONFIG_NSH_MMCSDSLOTNO); - if (!sdio) - { - syslog(LOG_ERR, - "ERROR: Failed to initialize SDIO slot %d\n", - CONFIG_NSH_MMCSDSLOTNO); - } - else - { - /* Now bind the SDIO interface to the MMC/SD driver */ - - ret = mmcsd_slotinitialize(CONFIG_NSH_MMCSDMINOR, sdio); - if (ret != OK) - { - syslog(LOG_ERR, - "ERROR: Failed to bind SDIO to the MMC/SD driver: %d\n", - ret); - } - - /* Then let's guess and say that there is a card in the slot. I need - * to check to see if the STM3240G-EVAL board supports a GPIO to - * detect if there is a card in the slot. - */ - - sdio_mediachange(sdio, true); - } -#endif - -#ifdef CONFIG_FS_PROCFS - /* Mount the procfs file system */ - - ret = nx_mount(NULL, "/proc", "procfs", 0, NULL); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: Failed to mount procfs at /proc: %d\n", ret); - } -#endif - -#ifdef HAVE_USBHOST - /* Initialize USB host operation. stm32_usbhost_initialize() starts a - * thread that will monitor for USB connection and disconnection events. - */ - - ret = stm32_usbhost_initialize(); - if (ret != OK) - { - syslog(LOG_ERR, "ERROR: Failed to initialize USB host: %d\n", ret); - } -#endif - -#ifdef CONFIG_VIDEO_FB - /* Initialize and register the simulated framebuffer driver */ - - ret = fb_register(0, 0); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: fb_register() failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_INPUT_STMPE811 - /* Initialize the touchscreen. - * WARNING: stm32_tsc_setup() cannot be called from the IDLE thread. - */ - - ret = stm32_tsc_setup(0); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_tsc_setup failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_PWM - /* Initialize PWM and register the PWM device. */ - - ret = stm32_pwm_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_pwm_setup() failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_ADC - /* Initialize ADC and register the ADC driver. */ - - ret = stm32_adc_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_adc_setup failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_STM32_CAN_CHARDRIVER - /* Initialize CAN and register the CAN driver. */ - - ret = stm32_can_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_can_setup failed: %d\n", ret); - } -#endif - - UNUSED(ret); - return OK; -} diff --git a/boards/arm/stm32/stm3240g-eval/src/stm32_buttons.c b/boards/arm/stm32/stm3240g-eval/src/stm32_buttons.c deleted file mode 100644 index 66f45af683705..0000000000000 --- a/boards/arm/stm32/stm3240g-eval/src/stm32_buttons.c +++ /dev/null @@ -1,164 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm3240g-eval/src/stm32_buttons.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include -#include - -#include "stm3240g-eval.h" - -#ifdef CONFIG_ARCH_BUTTONS - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/* Pin configuration for each STM3210E-EVAL button. This array is indexed by - * the BUTTON_* and JOYSTICK_* definitions in board.h - */ - -static const uint32_t g_buttons[NUM_BUTTONS] = -{ - GPIO_BTN_WAKEUP, GPIO_BTN_TAMPER, GPIO_BTN_USER -}; - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_button_initialize - * - * Description: - * board_button_initialize() must be called to initialize button resources. - * After that, board_buttons() may be called to collect the current state - * of all buttons or board_button_irq() may be called to register button - * interrupt handlers. - * - ****************************************************************************/ - -uint32_t board_button_initialize(void) -{ - int i; - - /* Configure the GPIO pins as inputs. NOTE that EXTI interrupts are - * configured for all pins. - */ - - for (i = 0; i < NUM_BUTTONS; i++) - { - stm32_configgpio(g_buttons[i]); - } - - return NUM_BUTTONS; -} - -/**************************************************************************** - * Name: board_buttons - ****************************************************************************/ - -uint32_t board_buttons(void) -{ - uint32_t ret = 0; - int i; - - /* Check that state of each key */ - - for (i = 0; i < NUM_BUTTONS; i++) - { - /* A LOW value means that the key is pressed for most keys. - * The exception is the WAKEUP button. - */ - - bool released = stm32_gpioread(g_buttons[i]); - if (i == BUTTON_WAKEUP) - { - released = !released; - } - - /* Accumulate the set of depressed (not released) keys */ - - if (!released) - { - ret |= (1 << i); - } - } - - return ret; -} - -/**************************************************************************** - * Button support. - * - * Description: - * board_button_initialize() must be called to initialize button resources. - * After that, board_buttons() may be called to collect the current state - * of all buttons or board_button_irq() may be called to register button - * interrupt handlers. - * - * After board_button_initialize() has been called, board_buttons() may be - * called to collect the state of all buttons. board_buttons() returns an - * 32-bit bit set with each bit associated with a button. See the - * BUTTON_*_BIT definitions in board.h for the meaning of each bit. - * - * board_button_irq() may be called to register an interrupt handler that - * will be called when a button is depressed or released. The ID value is a - * button enumeration value that uniquely identifies a button resource. See - * the BUTTON_* definitions in board.h for the meaning of enumeration - * value. - * - ****************************************************************************/ - -#ifdef CONFIG_ARCH_IRQBUTTONS -int board_button_irq(int id, xcpt_t irqhandler, void *arg) -{ - int ret = -EINVAL; - - /* The following should be atomic */ - - if (id >= MIN_IRQBUTTON && id <= MAX_IRQBUTTON) - { - ret = stm32_gpiosetevent(g_buttons[id], true, true, true, - irqhandler, arg); - } - - return ret; -} -#endif -#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/stm32/stm3240g-eval/src/stm32_can.c b/boards/arm/stm32/stm3240g-eval/src/stm32_can.c deleted file mode 100644 index 53e357df19c8e..0000000000000 --- a/boards/arm/stm32/stm3240g-eval/src/stm32_can.c +++ /dev/null @@ -1,102 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm3240g-eval/src/stm32_can.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32.h" -#include "stm32_can.h" -#include "stm3240g-eval.h" - -#ifdef CONFIG_CAN - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -#if defined(CONFIG_STM32_CAN1) && defined(CONFIG_STM32_CAN2) -# warning "Both CAN1 and CAN2 are enabled. Assuming only CAN1." -# undef CONFIG_STM32_CAN2 -#endif - -#ifdef CONFIG_STM32_CAN1 -# define CAN_PORT 1 -#else -# define CAN_PORT 2 -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_can_setup - * - * Description: - * Initialize CAN and register the CAN device - * - ****************************************************************************/ - -int stm32_can_setup(void) -{ -#if defined(CONFIG_STM32_CAN1) || defined(CONFIG_STM32_CAN2) - struct can_dev_s *can; - int ret; - - /* Call stm32_caninitialize() to get an instance of the CAN interface */ - - can = stm32_caninitialize(CAN_PORT); - if (can == NULL) - { - canerr("ERROR: Failed to get CAN interface\n"); - return -ENODEV; - } - - /* Register the CAN driver at "/dev/can0" */ - - ret = can_register("/dev/can0", can); - if (ret < 0) - { - canerr("ERROR: can_register failed: %d\n", ret); - return ret; - } - - return OK; -#else - return -ENODEV; -#endif -} - -#endif /* CONFIG_CAN */ diff --git a/boards/arm/stm32/stm3240g-eval/src/stm32_deselectlcd.c b/boards/arm/stm32/stm3240g-eval/src/stm32_deselectlcd.c deleted file mode 100644 index dc9cee810b60a..0000000000000 --- a/boards/arm/stm32/stm3240g-eval/src/stm32_deselectlcd.c +++ /dev/null @@ -1,80 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm3240g-eval/src/stm32_deselectlcd.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include "arm_internal.h" -#include "stm32.h" -#include "stm3240g-eval.h" - -#ifdef CONFIG_STM32_FSMC - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_deselectlcd - * - * Description: - * Disable the LCD - * - ****************************************************************************/ - -void stm32_deselectlcd(void) -{ - /* Restore registers to their power up settings */ - - putreg32(0xffffffff, STM32_FSMC_BCR4); - - /* Bank1 NOR/SRAM timing register configuration */ - - putreg32(0x0fffffff, STM32_FSMC_BTR4); - - /* Disable AHB clocking to the FSMC */ - - stm32_fsmc_disable(); -} - -#endif /* CONFIG_STM32_FSMC */ diff --git a/boards/arm/stm32/stm3240g-eval/src/stm32_deselectsram.c b/boards/arm/stm32/stm3240g-eval/src/stm32_deselectsram.c deleted file mode 100644 index 6f8840bedfb60..0000000000000 --- a/boards/arm/stm32/stm3240g-eval/src/stm32_deselectsram.c +++ /dev/null @@ -1,80 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm3240g-eval/src/stm32_deselectsram.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include "arm_internal.h" -#include "stm32.h" -#include "stm3240g-eval.h" - -#ifdef CONFIG_STM32_FSMC - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_deselectsram - * - * Description: - * Disable SRAM - * - ****************************************************************************/ - -void stm32_deselectsram(void) -{ - /* Restore registers to their power up settings */ - - putreg32(FSMC_BCR_RSTVALUE, STM32_FSMC_BCR2); - - /* Bank1 NOR/SRAM timing register configuration */ - - putreg32(FSMC_BTR_RSTVALUE, STM32_FSMC_BTR2); - - /* Disable AHB clocking to the FSMC */ - - stm32_fsmc_disable(); -} - -#endif /* CONFIG_STM32_FSMC */ diff --git a/boards/arm/stm32/stm3240g-eval/src/stm32_extmem.c b/boards/arm/stm32/stm3240g-eval/src/stm32_extmem.c deleted file mode 100644 index dd6d6b4163f87..0000000000000 --- a/boards/arm/stm32/stm3240g-eval/src/stm32_extmem.c +++ /dev/null @@ -1,141 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm3240g-eval/src/stm32_extmem.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32_gpio.h" -#include "stm32.h" -#include "stm3240g-eval.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#ifndef CONFIG_STM32_FSMC -# warning "FSMC is not enabled" -#endif - -#if STM32_NGPIO_PORTS < 6 -# error "Required GPIO ports not enabled" -#endif - -#define STM32_FSMC_NADDRCONFIGS 26 -#define STM32_FSMC_NDATACONFIGS 16 - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/* GPIO configurations common to most external memories */ - -static const uint32_t g_addressconfig[STM32_FSMC_NADDRCONFIGS] = -{ - GPIO_FSMC_A0, GPIO_FSMC_A1, GPIO_FSMC_A2, - GPIO_FSMC_A3, GPIO_FSMC_A4, GPIO_FSMC_A5, - GPIO_FSMC_A6, GPIO_FSMC_A7, GPIO_FSMC_A8, - GPIO_FSMC_A9, GPIO_FSMC_A10, GPIO_FSMC_A11, - GPIO_FSMC_A12, GPIO_FSMC_A13, GPIO_FSMC_A14, - GPIO_FSMC_A15, GPIO_FSMC_A16, GPIO_FSMC_A17, - GPIO_FSMC_A18, GPIO_FSMC_A19, GPIO_FSMC_A20, - GPIO_FSMC_A21, GPIO_FSMC_A22, GPIO_FSMC_A23, - GPIO_FSMC_A24, GPIO_FSMC_A25 -}; - -static const uint32_t g_dataconfig[STM32_FSMC_NDATACONFIGS] = -{ - GPIO_FSMC_D0, GPIO_FSMC_D1, GPIO_FSMC_D2, - GPIO_FSMC_D3, GPIO_FSMC_D4, GPIO_FSMC_D5, - GPIO_FSMC_D6, GPIO_FSMC_D7, GPIO_FSMC_D8, - GPIO_FSMC_D9, GPIO_FSMC_D10, GPIO_FSMC_D11, - GPIO_FSMC_D12, GPIO_FSMC_D13, GPIO_FSMC_D14, - GPIO_FSMC_D15 -}; - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_extmemgpios - * - * Description: - * Initialize GPIOs for external memory usage - * - ****************************************************************************/ - -void stm32_extmemgpios(const uint32_t *gpios, int ngpios) -{ - int i; - - /* Configure GPIOs */ - - for (i = 0; i < ngpios; i++) - { - stm32_configgpio(gpios[i]); - } -} - -/**************************************************************************** - * Name: stm32_extmemaddr - * - * Description: - * Initialize address line GPIOs for external memory access - * - ****************************************************************************/ - -void stm32_extmemaddr(int naddrs) -{ - stm32_extmemgpios(g_addressconfig, naddrs); -} - -/**************************************************************************** - * Name: stm32_extmemdata - * - * Description: - * Initialize data line GPIOs for external memory access - * - ****************************************************************************/ - -void stm32_extmemdata(int ndata) -{ - stm32_extmemgpios(g_dataconfig, ndata); -} diff --git a/boards/arm/stm32/stm3240g-eval/src/stm32_lcd.c b/boards/arm/stm32/stm3240g-eval/src/stm32_lcd.c deleted file mode 100644 index 8ab6c22e6addb..0000000000000 --- a/boards/arm/stm32/stm3240g-eval/src/stm32_lcd.c +++ /dev/null @@ -1,1188 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm3240g-eval/src/stm32_lcd.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* This driver supports the following LCDs on the STM324xG_EVAL board: - * - * AM-240320L8TNQW00H (LCD_ILI9320 or LCD_ILI9321) OR - * AM-240320D5TOQW01H (LCD_ILI9325) - */ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -#include - -#include "arm_internal.h" -#include "stm32.h" -#include "stm3240g-eval.h" - -#if !defined(CONFIG_STM3240G_ILI9320_DISABLE) || !defined(CONFIG_STM3240G_ILI9325_DISABLE) - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -/* CONFIG_STM3240G_ILI9320_DISABLE may be defined to disabled the - * AM-240320L8TNQW00H(LCD_ILI9320 or LCD_ILI9321) - * CONFIG_STM3240G_ILI9325_DISABLE may be defined to disabled the - * AM-240320D5TOQW01H(LCD_ILI9325) - */ - -/* Check contrast selection */ - -#if !defined(CONFIG_LCD_MAXCONTRAST) -# define CONFIG_LCD_MAXCONTRAST 1 -#endif - -/* Check power setting */ - -#if !defined(CONFIG_LCD_MAXPOWER) || CONFIG_LCD_MAXPOWER < 1 -# define CONFIG_LCD_MAXPOWER 1 -#endif - -#if CONFIG_LCD_MAXPOWER > 255 -# error "CONFIG_LCD_MAXPOWER must be less than 256 to fit in uint8_t" -#endif - -/* Check orientation */ - -#if defined(CONFIG_LCD_PORTRAIT) -# if defined(CONFIG_LCD_LANDSCAPE) || defined(CONFIG_LCD_RLANDSCAPE) || defined(CONFIG_LCD_RPORTRAIT) -# error "Cannot define both portrait and any other orientations" -# endif -#elif defined(CONFIG_LCD_RPORTRAIT) -# if defined(CONFIG_LCD_LANDSCAPE) || defined(CONFIG_LCD_RLANDSCAPE) -# error "Cannot define both rportrait and any other orientations" -# endif -#elif defined(CONFIG_LCD_LANDSCAPE) -# ifdef CONFIG_LCD_RLANDSCAPE -# error "Cannot define both landscape and any other orientations" -# endif -#elif !defined(CONFIG_LCD_RLANDSCAPE) -# define CONFIG_LCD_LANDSCAPE 1 -#endif - -/* Display/Color Properties *************************************************/ - -/* Display Resolution */ - -#if defined(CONFIG_LCD_LANDSCAPE) || defined(CONFIG_LCD_RLANDSCAPE) -# define STM3240G_XRES 320 -# define STM3240G_YRES 240 -#else -# define STM3240G_XRES 240 -# define STM3240G_YRES 320 -#endif - -/* Color depth and format */ - -#define STM3240G_BPP 16 -#define STM3240G_COLORFMT FB_FMT_RGB16_565 - -/* STM3240G-EVAL LCD Hardware Definitions ***********************************/ - -/* LCD /CS is CE4, Bank 3 of NOR/SRAM Bank 1~4 */ - -#define STM3240G_LCDBASE ((uintptr_t)(0x60000000 | 0x08000000)) -#define LCD ((struct lcd_regs_s *)STM3240G_LCDBASE) - -#define LCD_REG_0 0x00 -#define LCD_REG_1 0x01 -#define LCD_REG_2 0x02 -#define LCD_REG_3 0x03 -#define LCD_REG_4 0x04 -#define LCD_REG_5 0x05 -#define LCD_REG_6 0x06 -#define LCD_REG_7 0x07 -#define LCD_REG_8 0x08 -#define LCD_REG_9 0x09 -#define LCD_REG_10 0x0a -#define LCD_REG_12 0x0c -#define LCD_REG_13 0x0d -#define LCD_REG_14 0x0e -#define LCD_REG_15 0x0f -#define LCD_REG_16 0x10 -#define LCD_REG_17 0x11 -#define LCD_REG_18 0x12 -#define LCD_REG_19 0x13 -#define LCD_REG_20 0x14 -#define LCD_REG_21 0x15 -#define LCD_REG_22 0x16 -#define LCD_REG_23 0x17 -#define LCD_REG_24 0x18 -#define LCD_REG_25 0x19 -#define LCD_REG_26 0x1a -#define LCD_REG_27 0x1b -#define LCD_REG_28 0x1c -#define LCD_REG_29 0x1d -#define LCD_REG_30 0x1e -#define LCD_REG_31 0x1f -#define LCD_REG_32 0x20 -#define LCD_REG_33 0x21 -#define LCD_REG_34 0x22 -#define LCD_REG_36 0x24 -#define LCD_REG_37 0x25 -#define LCD_REG_40 0x28 -#define LCD_REG_41 0x29 -#define LCD_REG_43 0x2b -#define LCD_REG_45 0x2d -#define LCD_REG_48 0x30 -#define LCD_REG_49 0x31 -#define LCD_REG_50 0x32 -#define LCD_REG_51 0x33 -#define LCD_REG_52 0x34 -#define LCD_REG_53 0x35 -#define LCD_REG_54 0x36 -#define LCD_REG_55 0x37 -#define LCD_REG_56 0x38 -#define LCD_REG_57 0x39 -#define LCD_REG_58 0x3a -#define LCD_REG_59 0x3b -#define LCD_REG_60 0x3c -#define LCD_REG_61 0x3d -#define LCD_REG_62 0x3e -#define LCD_REG_63 0x3f -#define LCD_REG_64 0x40 -#define LCD_REG_65 0x41 -#define LCD_REG_66 0x42 -#define LCD_REG_67 0x43 -#define LCD_REG_68 0x44 -#define LCD_REG_69 0x45 -#define LCD_REG_70 0x46 -#define LCD_REG_71 0x47 -#define LCD_REG_72 0x48 -#define LCD_REG_73 0x49 -#define LCD_REG_74 0x4a -#define LCD_REG_75 0x4b -#define LCD_REG_76 0x4c -#define LCD_REG_77 0x4d -#define LCD_REG_78 0x4e -#define LCD_REG_79 0x4f -#define LCD_REG_80 0x50 -#define LCD_REG_81 0x51 -#define LCD_REG_82 0x52 -#define LCD_REG_83 0x53 -#define LCD_REG_96 0x60 -#define LCD_REG_97 0x61 -#define LCD_REG_106 0x6a -#define LCD_REG_118 0x76 -#define LCD_REG_128 0x80 -#define LCD_REG_129 0x81 -#define LCD_REG_130 0x82 -#define LCD_REG_131 0x83 -#define LCD_REG_132 0x84 -#define LCD_REG_133 0x85 -#define LCD_REG_134 0x86 -#define LCD_REG_135 0x87 -#define LCD_REG_136 0x88 -#define LCD_REG_137 0x89 -#define LCD_REG_139 0x8b -#define LCD_REG_140 0x8c -#define LCD_REG_141 0x8d -#define LCD_REG_143 0x8f -#define LCD_REG_144 0x90 -#define LCD_REG_145 0x91 -#define LCD_REG_146 0x92 -#define LCD_REG_147 0x93 -#define LCD_REG_148 0x94 -#define LCD_REG_149 0x95 -#define LCD_REG_150 0x96 -#define LCD_REG_151 0x97 -#define LCD_REG_152 0x98 -#define LCD_REG_153 0x99 -#define LCD_REG_154 0x9a -#define LCD_REG_157 0x9d -#define LCD_REG_164 0xa4 -#define LCD_REG_192 0xc0 -#define LCD_REG_193 0xc1 -#define LCD_REG_229 0xe5 - -/* LCD IDs */ - -#define ILI9320_ID 0x9320 -#define ILI9321_ID 0x9321 -#define ILI9325_ID 0x9325 - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/* LCD type */ - -enum lcd_type_e -{ - LCD_TYPE_UNKNOWN = 0, - LCD_TYPE_ILI9320, - LCD_TYPE_ILI9325 -}; - -/* This structure describes the LCD registers */ - -struct lcd_regs_s -{ - volatile uint16_t address; - volatile uint16_t value; -}; - -/* This structure describes the state of this driver */ - -struct stm3240g_dev_s -{ - /* Publicly visible device structure */ - - struct lcd_dev_s dev; - - /* Private LCD-specific information follows */ - - uint8_t type; /* LCD type. See enum lcd_type_e */ - uint8_t power; /* Current power setting */ -}; - -/**************************************************************************** - * Private Function Protototypes - ****************************************************************************/ - -/* Low Level LCD access */ - -static void stm3240g_writereg(uint8_t regaddr, uint16_t regval); -static uint16_t stm3240g_readreg(uint8_t regaddr); -static inline void stm3240g_gramselect(void); -static inline void stm3240g_writegram(uint16_t rgbval); -static void stm3240g_readnosetup(uint16_t *accum); -static uint16_t stm3240g_readnoshift(uint16_t *accum); -static void stm3240g_setcursor(uint16_t col, uint16_t row); - -/* LCD Data Transfer Methods */ - -static int stm3240g_putrun(struct lcd_dev_s *dev, - fb_coord_t row, fb_coord_t col, - const uint8_t *buffer, size_t npixels); -static int stm3240g_getrun(struct lcd_dev_s *dev, - fb_coord_t row, fb_coord_t col, - uint8_t *buffer, size_t npixels); - -/* LCD Configuration */ - -static int stm3240g_getvideoinfo(struct lcd_dev_s *dev, - struct fb_videoinfo_s *vinfo); -static int stm3240g_getplaneinfo(struct lcd_dev_s *dev, - unsigned int planeno, - struct lcd_planeinfo_s *pinfo); - -/* LCD RGB Mapping */ - -#ifdef CONFIG_FB_CMAP -# error "RGB color mapping not supported by this driver" -#endif - -/* Cursor Controls */ - -#ifdef CONFIG_FB_HWCURSOR -# error "Cursor control not supported by this driver" -#endif - -/* LCD Specific Controls */ - -static int stm3240g_getpower(struct lcd_dev_s *dev); -static int stm3240g_setpower(struct lcd_dev_s *dev, int power); -static int stm3240g_getcontrast(struct lcd_dev_s *dev); -static int stm3240g_setcontrast(struct lcd_dev_s *dev, - unsigned int contrast); - -/* Initialization */ - -static inline void stm3240g_lcdinitialize(void); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* This is working memory allocated by the LCD driver for each LCD device - * and for each color plane. This memory will hold one raster line of data. - * The size of the allocated run buffer must therefore be at least - * (bpp * xres / 8). Actual alignment of the buffer must conform to the - * bitwidth of the underlying pixel type. - * - * If there are multiple planes, they may share the same working buffer - * because different planes will not be operate on concurrently. However, - * if there are multiple LCD devices, they must each have unique run buffers. - */ - -static uint16_t g_runbuffer[STM3240G_XRES]; - -/* This structure describes the overall LCD video controller */ - -static const struct fb_videoinfo_s g_videoinfo = -{ - .fmt = STM3240G_COLORFMT, /* Color format: RGB16-565: RRRR RGGG GGGB BBBB */ - .xres = STM3240G_XRES, /* Horizontal resolution in pixel columns */ - .yres = STM3240G_YRES, /* Vertical resolution in pixel rows */ - .nplanes = 1, /* Number of color planes supported */ -}; - -/* This is the standard, NuttX Plane information object */ - -static const struct lcd_planeinfo_s g_planeinfo = -{ - .putrun = stm3240g_putrun, /* Put a run into LCD memory */ - .getrun = stm3240g_getrun, /* Get a run from LCD memory */ - .buffer = (uint8_t *)g_runbuffer, /* Run scratch buffer */ - .bpp = STM3240G_BPP, /* Bits-per-pixel */ -}; - -/* This is the standard, NuttX LCD driver object */ - -static struct stm3240g_dev_s g_lcddev = -{ - .dev = - { - /* LCD Configuration */ - - .getvideoinfo = stm3240g_getvideoinfo, - .getplaneinfo = stm3240g_getplaneinfo, - - /* LCD RGB Mapping -- Not supported */ - - /* Cursor Controls -- Not supported */ - - /* LCD Specific Controls */ - - .getpower = stm3240g_getpower, - .setpower = stm3240g_setpower, - .getcontrast = stm3240g_getcontrast, - .setcontrast = stm3240g_setcontrast, - }, -}; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm3240g_writereg - * - * Description: - * Write to an LCD register - * - ****************************************************************************/ - -static void stm3240g_writereg(uint8_t regaddr, uint16_t regval) -{ - /* Write the register address then write the register value */ - - LCD->address = regaddr; - LCD->value = regval; -} - -/**************************************************************************** - * Name: stm3240g_readreg - * - * Description: - * Read from an LCD register - * - ****************************************************************************/ - -static uint16_t stm3240g_readreg(uint8_t regaddr) -{ - /* Write the register address then read the register value */ - - LCD->address = regaddr; - return LCD->value; -} - -/**************************************************************************** - * Name: stm3240g_gramselect - * - * Description: - * Setup to read or write multiple pixels to the GRAM memory - * - ****************************************************************************/ - -static inline void stm3240g_gramselect(void) -{ - LCD->address = LCD_REG_34; -} - -/**************************************************************************** - * Name: stm3240g_writegram - * - * Description: - * Write one pixel to the GRAM memory - * - ****************************************************************************/ - -static inline void stm3240g_writegram(uint16_t rgbval) -{ - /* Write the value (GRAM register already selected) */ - - LCD->value = rgbval; -} - -/**************************************************************************** - * Name: stm3240g_readnosetup - * - * Description: - * Prime the operation by reading one pixel from the GRAM memory if - * necessary for this LCD type. When reading 16-bit gram data, there may - * be some shifts in the returned data: - * - * - ILI932x: Discard first dummy read; no shift in the return data - * - ****************************************************************************/ - -static void stm3240g_readnosetup(uint16_t *accum) -{ - /* Read-ahead one pixel */ - - *accum = LCD->value; -} - -/**************************************************************************** - * Name: stm3240g_readnoshift - * - * Description: - * Read one correctly aligned pixel from the GRAM memory. Possibly - * shifting the data and possibly swapping red and green components. - * - * - ILI932x: Unknown -- assuming colors are in the color order - * - ****************************************************************************/ - -static uint16_t stm3240g_readnoshift(uint16_t *accum) -{ - /* Read the value (GRAM register already selected) */ - - return LCD->value; -} - -/**************************************************************************** - * Name: stm3240g_setcursor - * - * Description: - * Set the cursor position. In landscape mode, the "column" is actually - * the physical Y position and the "row" is the physical X position. - * - ****************************************************************************/ - -static void stm3240g_setcursor(uint16_t col, uint16_t row) -{ - stm3240g_writereg(LCD_REG_32, row); /* GRAM horizontal address */ - stm3240g_writereg(LCD_REG_33, col); /* GRAM vertical address */ -} - -/**************************************************************************** - * Name: stm3240g_putrun - * - * Description: - * This method can be used to write a partial raster line to the LCD: - * - * dev - The lcd device - * row - Starting row to write to (range: 0 <= row < yres) - * col - Starting column to write to (range: 0 <= col <= xres-npixels) - * buffer - The buffer containing the run to be written to the LCD - * npixels - The number of pixels to write to the LCD - * (range: 0 < npixels <= xres-col) - * - ****************************************************************************/ - -static int stm3240g_putrun(struct lcd_dev_s *dev, - fb_coord_t row, fb_coord_t col, - const uint8_t *buffer, size_t npixels) -{ - const uint16_t *src = (const uint16_t *)buffer; - int i; - - /* Buffer must be provided and aligned to a 16-bit address boundary */ - - lcdinfo("row: %d col: %d npixels: %d\n", row, col, npixels); - DEBUGASSERT(buffer && ((uintptr_t)buffer & 1) == 0); - - /* Write the run to GRAM. */ - -#ifdef CONFIG_LCD_LANDSCAPE - /* Convert coordinates -- Here the edge away from the row of buttons on - * the STM3240G-EVAL is used as the top. - */ - - /* Write the GRAM data, manually incrementing X */ - - for (i = 0; i < npixels; i++) - { - /* Write the next pixel to this position */ - - stm3240g_setcursor(col, row); - stm3240g_gramselect(); - stm3240g_writegram(*src++); - - /* Increment to next column */ - - col++; - } -#elif defined(CONFIG_LCD_RLANDSCAPE) - /* Convert coordinates -- Here the edge next to the row of buttons on - * the STM3240G-EVAL is used as the top. - */ - - col = (STM3240G_XRES - 1) - col; - row = (STM3240G_YRES - 1) - row; - - /* Set the cursor position */ - - stm3240g_setcursor(col, row); - - /* Then write the GRAM data, auto-decrementing X */ - - stm3240g_gramselect(); - for (i = 0; i < npixels; i++) - { - /* Write the next pixel to this position - * (auto-decrements to the next column) - */ - - stm3240g_writegram(*src++); - } -#elif defined(CONFIG_LCD_PORTRAIT) - - /* Convert coordinates. - * In this configuration, the top of the display is to the left of the - * buttons (if the board is held so that the buttons are at the bottom of - * the board). - */ - - col = (STM3240G_XRES - 1) - col; - - /* Then write the GRAM data, manually incrementing Y (which is col) */ - - for (i = 0; i < npixels; i++) - { - /* Write the next pixel to this position */ - - stm3240g_setcursor(row, col); - stm3240g_gramselect(); - stm3240g_writegram(*src++); - - /* Increment to next column */ - - col--; - } -#else /* CONFIG_LCD_RPORTRAIT */ - - /* Convert coordinates. - * In this configuration, the top of the display is to the right of the - * buttons (if the board is held so that the buttons are at the bottom of - * the board). - */ - - row = (STM3240G_YRES - 1) - row; - - /* Then write the GRAM data, manually incrementing Y (which is col) */ - - for (i = 0; i < npixels; i++) - { - /* Write the next pixel to this position */ - - stm3240g_setcursor(row, col); - stm3240g_gramselect(); - stm3240g_writegram(*src++); - - /* Decrement to next column */ - - col++; - } -#endif - - return OK; -} - -/**************************************************************************** - * Name: stm3240g_getrun - * - * Description: - * This method can be used to read a partial raster line from the LCD: - * - * dev - The lcd device - * row - Starting row to read from (range: 0 <= row < yres) - * col - Starting column to read read (range: 0 <= col <= xres-npixels) - * buffer - The buffer in which to return the run read from the LCD - * npixels - The number of pixels to read from the LCD - * (range: 0 < npixels <= xres-col) - * - ****************************************************************************/ - -static int stm3240g_getrun(struct lcd_dev_s *dev, - fb_coord_t row, fb_coord_t col, - uint8_t *buffer, size_t npixels) -{ - uint16_t *dest = (uint16_t *)buffer; - void (*readsetup)(uint16_t *accum); - uint16_t (*readgram)(uint16_t *accum); - uint16_t accum; - int i; - - /* Buffer must be provided and aligned to a 16-bit address boundary */ - - lcdinfo("row: %d col: %d npixels: %d\n", row, col, npixels); - DEBUGASSERT(buffer && ((uintptr_t)buffer & 1) == 0); - - /* Configure according to the LCD type. - * Kind of silly with only one LCD type. - */ - - switch (g_lcddev.type) - { - case LCD_TYPE_ILI9320: - case LCD_TYPE_ILI9325: - readsetup = stm3240g_readnosetup; - readgram = stm3240g_readnoshift; - break; - - default: /* Shouldn't happen */ - return -ENOSYS; - } - - /* Read the run from GRAM. */ - -#ifdef CONFIG_LCD_LANDSCAPE - /* Convert coordinates -- Here the edge away from the row of buttons on - * the STM3240G-EVAL is used as the top. - */ - - for (i = 0; i < npixels; i++) - { - /* Read the next pixel from this position */ - - stm3240g_setcursor(row, col); - stm3240g_gramselect(); - readsetup(&accum); - *dest++ = readgram(&accum); - - /* Increment to next column */ - - col++; - } -#elif defined(CONFIG_LCD_RLANDSCAPE) - /* Convert coordinates -- Here the edge next to the row of buttons on - * the STM3240G-EVAL is used as the top. - */ - - col = (STM3240G_XRES - 1) - col; - row = (STM3240G_YRES - 1) - row; - - /* Set the cursor position */ - - stm3240g_setcursor(col, row); - - /* Then read the GRAM data, auto-decrementing Y */ - - stm3240g_gramselect(); - - /* Prime the pump for unaligned read data */ - - readsetup(&accum); - - for (i = 0; i < npixels; i++) - { - /* Read the next pixel from this position - * (autoincrements to the next row) - */ - - *dest++ = readgram(&accum); - } -#elif defined(CONFIG_LCD_PORTRAIT) - /* Convert coordinates. - * In this configuration, the top of the display is to the left of the - * buttons (if the board is held so that the buttons are at the bottom of - * the board). - */ - - col = (STM3240G_XRES - 1) - col; - - /* Then read the GRAM data, manually incrementing Y (which is col) */ - - for (i = 0; i < npixels; i++) - { - /* Read the next pixel from this position */ - - stm3240g_setcursor(row, col); - stm3240g_gramselect(); - readsetup(&accum); - *dest++ = readgram(&accum); - - /* Increment to next column */ - - col--; - } -#else /* CONFIG_LCD_RPORTRAIT */ - /* Convert coordinates. - * In this configuration, the top of the display is to the right of the - * buttons (if the board is held so that the buttons are at the bottom of - * the board). - */ - - row = (STM3240G_YRES - 1) - row; - - /* Then write the GRAM data, manually incrementing Y (which is col) */ - - for (i = 0; i < npixels; i++) - { - /* Write the next pixel to this position */ - - stm3240g_setcursor(row, col); - stm3240g_gramselect(); - readsetup(&accum); - *dest++ = readgram(&accum); - - /* Decrement to next column */ - - col++; - } -#endif - - return OK; -} - -/**************************************************************************** - * Name: stm3240g_getvideoinfo - * - * Description: - * Get information about the LCD video controller configuration. - * - ****************************************************************************/ - -static int stm3240g_getvideoinfo(struct lcd_dev_s *dev, - struct fb_videoinfo_s *vinfo) -{ - DEBUGASSERT(dev && vinfo); - lcdinfo("fmt: %d xres: %d yres: %d nplanes: %d\n", - g_videoinfo.fmt, g_videoinfo.xres, - g_videoinfo.yres, g_videoinfo.nplanes); - memcpy(vinfo, &g_videoinfo, sizeof(struct fb_videoinfo_s)); - return OK; -} - -/**************************************************************************** - * Name: stm3240g_getplaneinfo - * - * Description: - * Get information about the configuration of each LCD color plane. - * - ****************************************************************************/ - -static int stm3240g_getplaneinfo(struct lcd_dev_s *dev, - unsigned int planeno, - struct lcd_planeinfo_s *pinfo) -{ - DEBUGASSERT(dev && pinfo && planeno == 0); - lcdinfo("planeno: %d bpp: %d\n", planeno, g_planeinfo.bpp); - memcpy(pinfo, &g_planeinfo, sizeof(struct lcd_planeinfo_s)); - pinfo->dev = dev; - return OK; -} - -/**************************************************************************** - * Name: stm3240g_getpower - * - * Description: - * Get the LCD panel power status - * (0: full off - CONFIG_LCD_MAXPOWER: full on). On backlit LCDs, - * this setting may correspond to the backlight setting. - * - ****************************************************************************/ - -static int stm3240g_getpower(struct lcd_dev_s *dev) -{ - lcdinfo("power: %d\n", 0); - return g_lcddev.power; -} - -/**************************************************************************** - * Name: stm3240g_poweroff - * - * Description: - * Enable/disable LCD panel power - * (0: full off - CONFIG_LCD_MAXPOWER: full on). On backlit LCDs, - * this setting may correspond to the backlight setting. - * - ****************************************************************************/ - -static int stm3240g_poweroff(void) -{ - /* Turn the display off */ - - stm3240g_writereg(LCD_REG_7, 0); - - /* Remember the power off state */ - - g_lcddev.power = 0; - return OK; -} - -/**************************************************************************** - * Name: stm3240g_setpower - * - * Description: - * Enable/disable LCD panel power - * (0: full off - CONFIG_LCD_MAXPOWER: full on). On backlit LCDs, - * this setting may correspond to the backlight setting. - * - ****************************************************************************/ - -static int stm3240g_setpower(struct lcd_dev_s *dev, int power) -{ - lcdinfo("power: %d\n", power); - DEBUGASSERT((unsigned)power <= CONFIG_LCD_MAXPOWER); - - /* Set new power level */ - - if (power > 0) - { - /* Then turn the display on */ - -#if !defined(CONFIG_STM3240G_ILI9320_DISABLE) || !defined(CONFIG_STM3240G_ILI9325_DISABLE) - stm3240g_writereg(LCD_REG_7, 0x0173); -#endif - g_lcddev.power = power; - } - else - { - /* Turn the display off */ - - stm3240g_poweroff(); - } - - return OK; -} - -/**************************************************************************** - * Name: stm3240g_getcontrast - * - * Description: - * Get the current contrast setting (0-CONFIG_LCD_MAXCONTRAST). - * - ****************************************************************************/ - -static int stm3240g_getcontrast(struct lcd_dev_s *dev) -{ - lcdinfo("Not implemented\n"); - return -ENOSYS; -} - -/**************************************************************************** - * Name: stm3240g_setcontrast - * - * Description: - * Set LCD panel contrast (0-CONFIG_LCD_MAXCONTRAST). - * - ****************************************************************************/ - -static int stm3240g_setcontrast(struct lcd_dev_s *dev, unsigned int contrast) -{ - lcdinfo("contrast: %d\n", contrast); - return -ENOSYS; -} - -/**************************************************************************** - * Name: stm3240g_lcdinitialize - * - * Description: - * Set LCD panel contrast (0-CONFIG_LCD_MAXCONTRAST). - * - ****************************************************************************/ - -static inline void stm3240g_lcdinitialize(void) -{ - uint16_t id; - - /* Check LCD ID */ - - id = stm3240g_readreg(LCD_REG_0); - lcdinfo("LCD ID: %04x\n", id); - - /* Check if the ID is for the STM32_ILI9320 (or ILI9321) or STM32_ILI9325 */ - -#if !defined(CONFIG_STM3240G_ILI9320_DISABLE) && !defined(CONFIG_STM3240G_ILI9325_DISABLE) - if (id == ILI9320_ID || id == ILI9321_ID || id == ILI9325_ID) -#elif !defined(CONFIG_STM3240G_ILI9320_DISABLE) && defined(CONFIG_STM3240G_ILI9325_DISABLE) - if (id == ILI9320_ID || id == ILI9321_ID) -#else /* if defined(CONFIG_STM3240G_ILI9320_DISABLE) && !defined(CONFIG_STM3240G_ILI9325_DISABLE)) */ - if (id == ILI9325_ID) -#endif - { - /* Save the LCD type - * (not actually used at for anything important) - */ - -#if !defined(CONFIG_STM3240G_ILI9320_DISABLE) -# if !defined(CONFIG_STM3240G_ILI9325_DISABLE) - if (id == ILI9325_ID) - { - g_lcddev.type = LCD_TYPE_ILI9325; - } - else -# endif - { - g_lcddev.type = LCD_TYPE_ILI9320; - stm3240g_writereg(LCD_REG_229, 0x8000); /* Set the internal vcore voltage */ - } -#else /* if !defined(CONFIG_STM3240G_ILI9325_DISABLE) */ - g_lcddev.type = LCD_TYPE_ILI9325; -#endif - lcdinfo("LCD type: %d\n", g_lcddev.type); - - /* Start Initial Sequence */ - - stm3240g_writereg(LCD_REG_0, 0x0001); /* Start internal OSC. */ - stm3240g_writereg(LCD_REG_1, 0x0100); /* Set SS and SM bit */ - stm3240g_writereg(LCD_REG_2, 0x0700); /* Set 1 line inversion */ - stm3240g_writereg(LCD_REG_3, 0x1030); /* Set GRAM write direction and BGR=1. */ - - /* stm3240g_writereg(LCD_REG_3, 0x1018); - * Set GRAM write direction and BGR=1. - */ - - stm3240g_writereg(LCD_REG_4, 0x0000); /* Resize register */ - stm3240g_writereg(LCD_REG_8, 0x0202); /* Set the back porch and front porch */ - stm3240g_writereg(LCD_REG_9, 0x0000); /* Set non-display area refresh cycle ISC[3:0] */ - stm3240g_writereg(LCD_REG_10, 0x0000); /* FMARK function */ - stm3240g_writereg(LCD_REG_12, 0x0000); /* RGB interface setting */ - stm3240g_writereg(LCD_REG_13, 0x0000); /* Frame marker Position */ - stm3240g_writereg(LCD_REG_15, 0x0000); /* RGB interface polarity */ - - /* Power On sequence */ - - stm3240g_writereg(LCD_REG_16, 0x0000); /* SAP, BT[3:0], AP, DSTB, SLP, STB */ - stm3240g_writereg(LCD_REG_17, 0x0000); /* DC1[2:0], DC0[2:0], VC[2:0] */ - stm3240g_writereg(LCD_REG_18, 0x0000); /* VREG1OUT voltage */ - stm3240g_writereg(LCD_REG_19, 0x0000); /* VDV[4:0] for VCOM amplitude */ - up_mdelay(200); /* Dis-charge capacitor power voltage (200ms) */ - - stm3240g_writereg(LCD_REG_16, 0x17b0); /* SAP, BT[3:0], AP, DSTB, SLP, STB */ - stm3240g_writereg(LCD_REG_17, 0x0137); /* DC1[2:0], DC0[2:0], VC[2:0] */ - up_mdelay(50); - - stm3240g_writereg(LCD_REG_18, 0x0139); /* VREG1OUT voltage */ - up_mdelay(50); - - stm3240g_writereg(LCD_REG_19, 0x1d00); /* VDV[4:0] for VCOM amplitude */ - stm3240g_writereg(LCD_REG_41, 0x0013); /* VCM[4:0] for VCOMH */ - up_mdelay(50); - - stm3240g_writereg(LCD_REG_32, 0x0000); /* GRAM horizontal Address */ - stm3240g_writereg(LCD_REG_33, 0x0000); /* GRAM Vertical Address */ - - /* Adjust the Gamma Curve (ILI9320/1) */ - -#if !defined(CONFIG_STM3240G_ILI9320_DISABLE) -# if !defined(CONFIG_STM3240G_ILI9325_DISABLE) - if (g_lcddev.type == LCD_TYPE_ILI9320) -# endif - { - stm3240g_writereg(LCD_REG_48, 0x0006); - stm3240g_writereg(LCD_REG_49, 0x0101); - stm3240g_writereg(LCD_REG_50, 0x0003); - stm3240g_writereg(LCD_REG_53, 0x0106); - stm3240g_writereg(LCD_REG_54, 0x0b02); - stm3240g_writereg(LCD_REG_55, 0x0302); - stm3240g_writereg(LCD_REG_56, 0x0707); - stm3240g_writereg(LCD_REG_57, 0x0007); - stm3240g_writereg(LCD_REG_60, 0x0600); - stm3240g_writereg(LCD_REG_61, 0x020b); - } -#endif - - /* Adjust the Gamma Curve (ILI9325) */ - -#if !defined(CONFIG_STM3240G_ILI9325_DISABLE) -# if !defined(CONFIG_STM3240G_ILI9320_DISABLE) - else -# endif - { - stm3240g_writereg(LCD_REG_48, 0x0007); - stm3240g_writereg(LCD_REG_49, 0x0302); - stm3240g_writereg(LCD_REG_50, 0x0105); - stm3240g_writereg(LCD_REG_53, 0x0206); - stm3240g_writereg(LCD_REG_54, 0x0808); - stm3240g_writereg(LCD_REG_55, 0x0206); - stm3240g_writereg(LCD_REG_56, 0x0504); - stm3240g_writereg(LCD_REG_57, 0x0007); - stm3240g_writereg(LCD_REG_60, 0x0105); - stm3240g_writereg(LCD_REG_61, 0x0808); - } -#endif - - /* Set GRAM area */ - - stm3240g_writereg(LCD_REG_80, 0x0000); /* Horizontal GRAM Start Address */ - stm3240g_writereg(LCD_REG_81, 0x00ef); /* Horizontal GRAM End Address */ - stm3240g_writereg(LCD_REG_82, 0x0000); /* Vertical GRAM Start Address */ - stm3240g_writereg(LCD_REG_83, 0x013f); /* Vertical GRAM End Address */ - stm3240g_writereg(LCD_REG_96, 0x2700); /* Gate Scan Line */ - - /* stm3240g_writereg(LCD_REG_96, 0xa700); - * Gate Scan Line(GS=1, scan direction is G320~G1) - */ - - stm3240g_writereg(LCD_REG_97, 0x0001); /* NDL,VLE, REV */ - stm3240g_writereg(LCD_REG_106, 0x0000); /* Set scrolling line */ - - /* Partial Display Control */ - - stm3240g_writereg(LCD_REG_128, 0x0000); - stm3240g_writereg(LCD_REG_129, 0x0000); - stm3240g_writereg(LCD_REG_130, 0x0000); - stm3240g_writereg(LCD_REG_131, 0x0000); - stm3240g_writereg(LCD_REG_132, 0x0000); - stm3240g_writereg(LCD_REG_133, 0x0000); - - /* Panel Control */ - - stm3240g_writereg(LCD_REG_144, 0x0010); - stm3240g_writereg(LCD_REG_146, 0x0000); - stm3240g_writereg(LCD_REG_147, 0x0003); - stm3240g_writereg(LCD_REG_149, 0x0110); - stm3240g_writereg(LCD_REG_151, 0x0000); - stm3240g_writereg(LCD_REG_152, 0x0000); - - /* Set GRAM write direction and BGR = 1 - * - * I/D=01 (Horizontal : increment, Vertical : decrement) - * AM=1 (address is updated in vertical writing direction) - */ - - stm3240g_writereg(LCD_REG_3, 0x1018); - stm3240g_writereg(LCD_REG_7, 0); /* Display off */ - } - else - { - lcderr("ERROR: Unsupported LCD type\n"); - } -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_lcd_initialize - * - * Description: - * Initialize the LCD video hardware. The initial state of the LCD is - * fully initialized, display memory cleared, and the LCD ready to use, - * but with the power setting at 0 (full off). - * - ****************************************************************************/ - -int board_lcd_initialize(void) -{ - lcdinfo("Initializing\n"); - - /* Configure GPIO pins and configure the FSMC to support the LCD */ - - stm32_selectlcd(); - - /* Configure and enable LCD */ - - up_mdelay(50); - stm3240g_lcdinitialize(); - - /* Clear the display (setting it to the color 0=black) */ - - stm3240g_lcdclear(0); - - /* Turn the display off */ - - stm3240g_poweroff(); - return OK; -} - -/**************************************************************************** - * Name: board_lcd_getdev - * - * Description: - * Return a a reference to the LCD object for the specified LCD. - * This allows support for multiple LCD devices. - * - ****************************************************************************/ - -struct lcd_dev_s *board_lcd_getdev(int lcddev) -{ - DEBUGASSERT(lcddev == 0); - return &g_lcddev.dev; -} - -/**************************************************************************** - * Name: board_lcd_uninitialize - * - * Description: - * Uninitialize the LCD support - * - ****************************************************************************/ - -void board_lcd_uninitialize(void) -{ - stm3240g_poweroff(); - stm32_deselectlcd(); -} - -/**************************************************************************** - * Name: stm3240g_lcdclear - * - * Description: - * This is a non-standard LCD interface just for the stm3240g-EVAL board. - * Because of the various rotations, clearing the display in the normal way - * by writing a sequences of runs that covers the entire display can be - * very slow. Here the display is cleared by simply setting all GRAM - * memory to the specified color. - * - ****************************************************************************/ - -void stm3240g_lcdclear(uint16_t color) -{ - uint32_t i = 0; - - stm3240g_setcursor(0, STM3240G_XRES - 1); - stm3240g_gramselect(); - for (i = 0; i < STM3240G_XRES * STM3240G_YRES; i++) - { - LCD->value = color; - } -} - -#endif /* !CONFIG_STM3240G_ILI9320_DISABLE || !CONFIG_STM3240G_ILI9325_DISABLE */ diff --git a/boards/arm/stm32/stm3240g-eval/src/stm32_pwm.c b/boards/arm/stm32/stm3240g-eval/src/stm32_pwm.c deleted file mode 100644 index 2d4e6393779f2..0000000000000 --- a/boards/arm/stm32/stm3240g-eval/src/stm32_pwm.c +++ /dev/null @@ -1,105 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm3240g-eval/src/stm32_pwm.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include - -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32_pwm.h" -#include "stm3240g-eval.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -/* PWM - * - * The STM3240G-Eval has no real on-board PWM devices, but the board can be - * configured to output a pulse train using variously unused pins on the - * board for PWM output (see board.h for details of pins). - */ - -#ifdef CONFIG_PWM - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_pwm_setup - * - * Description: - * Initialize PWM and register the PWM device. - * - ****************************************************************************/ - -int stm32_pwm_setup(void) -{ - static bool initialized = false; - struct pwm_lowerhalf_s *pwm; - int ret; - - /* Have we already initialized? */ - - if (!initialized) - { - /* Call stm32_pwminitialize() to get an instance of the PWM interface */ - - pwm = stm32_pwminitialize(STM3240G_EVAL_PWMTIMER); - if (!pwm) - { - aerr("ERROR: Failed to get the STM32 PWM lower half\n"); - return -ENODEV; - } - - /* Register the PWM driver at "/dev/pwm0" */ - - ret = pwm_register("/dev/pwm0", pwm); - if (ret < 0) - { - aerr("ERROR: pwm_register failed: %d\n", ret); - return ret; - } - - /* Now we are initialized */ - - initialized = true; - } - - return OK; -} - -#endif /* CONFIG_PWM */ diff --git a/boards/arm/stm32/stm3240g-eval/src/stm32_selectlcd.c b/boards/arm/stm32/stm3240g-eval/src/stm32_selectlcd.c deleted file mode 100644 index c3c854d032088..0000000000000 --- a/boards/arm/stm32/stm3240g-eval/src/stm32_selectlcd.c +++ /dev/null @@ -1,155 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm3240g-eval/src/stm32_selectlcd.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32.h" -#include -#include "stm3240g-eval.h" - -#ifdef CONFIG_STM32_FSMC - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#if STM32_NGPIO_PORTS < 6 -# error "Required GPIO ports not enabled" -#endif - -/* SRAM pin definitions */ - -#define LCD_NADDRLINES 1 -#define LCD_NDATALINES 16 - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* Pin Usage (per schematic) - * SRAM LCD - * D[0..15] [0..15] [0..15] - * A[0..25] [0..22] [0] RS - * FSMC_NBL0 PE0 OUT --- --- - * FSMC_NBL1 PE1 OUT --- --- - * FSMC_NE2 PG9 OUT --- --- - * FSMC_NE3 PG10 OUT --- ~CS - * FSMC_NE4 PG12 OUT --- --- - * FSMC_NWE PD5 OUT --- ~WR/SCL - * FSMC_NOE PD4 OUT --- ~RD - * FSMC_NWAIT PD6 IN --- --- - * FSMC_INT2 PG6* IN --- --- - * FSMC_INT3 - * FSMC_INTR - * FSMC_CD - * FSMC_CLK - * FSMC_NCE2 - * FSMC_NCE3 - * FSMC_NCE4_1 - * FSMC_NCE4_2 - * FSMC_NIORD - * FSMC_NIOWR - * FSMC_NL - * FSMC_NREG - */ - -/* GPIO configurations unique to the LCD */ - -static const uint32_t g_lcdconfig[] = -{ - /* NOE, NWE, and NE3 */ - - GPIO_FSMC_NOE, GPIO_FSMC_NWE, GPIO_FSMC_NE3 -}; -#define NLCD_CONFIG (sizeof(g_lcdconfig)/sizeof(uint32_t)) - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_selectlcd - * - * Description: - * Initialize to the LCD - * - ****************************************************************************/ - -void stm32_selectlcd(void) -{ - /* Configure new GPIO pins */ - - stm32_extmemaddr(LCD_NADDRLINES); /* Common address lines: A0 */ - stm32_extmemdata(LCD_NDATALINES); /* Common data lines: D0-D15 */ - stm32_extmemgpios(g_lcdconfig, NLCD_CONFIG); /* LCD-specific control lines */ - - /* Enable AHB clocking to the FSMC */ - - stm32_fsmc_enable(); - - /* Color LCD configuration (LCD configured as follow): - * - * - Data/Address MUX = Disable "FSMC_BCR_MUXEN" just not enable it. - * - Extended Mode = Disable "FSMC_BCR_EXTMOD" - * - Memory Type = SRAM "FSMC_BCR_SRAM" - * - Data Width = 16bit "FSMC_BCR_MWID16" - * - Write Operation = Enable "FSMC_BCR_WREN" - * - Asynchronous Wait = Disable - */ - - /* Bank3 NOR/SRAM control register configuration */ - - putreg32(FSMC_BCR_SRAM | FSMC_BCR_MWID16 | FSMC_BCR_WREN, STM32_FSMC_BCR3); - - /* Bank3 NOR/SRAM timing register configuration */ - - putreg32(FSMC_BTR_ADDSET(5) | FSMC_BTR_ADDHLD(1) | - FSMC_BTR_DATAST(9) | FSMC_BTR_BUSTURN(1) | - FSMC_BTR_CLKDIV(1) | FSMC_BTR_DATLAT(2) | - FSMC_BTR_ACCMODA, STM32_FSMC_BTR3); - - putreg32(0xffffffff, STM32_FSMC_BWTR3); - - /* Enable the bank by setting the MBKEN bit */ - - putreg32(FSMC_BCR_MBKEN | FSMC_BCR_SRAM | - FSMC_BCR_MWID16 | FSMC_BCR_WREN, STM32_FSMC_BCR3); -} - -#endif /* CONFIG_STM32_FSMC */ diff --git a/boards/arm/stm32/stm3240g-eval/src/stm32_selectsram.c b/boards/arm/stm32/stm3240g-eval/src/stm32_selectsram.c deleted file mode 100644 index 7ffe0a673f738..0000000000000 --- a/boards/arm/stm32/stm3240g-eval/src/stm32_selectsram.c +++ /dev/null @@ -1,186 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm3240g-eval/src/stm32_selectsram.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32.h" -#include -#include "stm3240g-eval.h" - -#ifdef CONFIG_STM32_FSMC - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#if STM32_NGPIO_PORTS < 6 -# error "Required GPIO ports not enabled" -#endif - -/* SRAM Timing */ - -#define SRAM_ADDRESS_SETUP_TIME 3 -#define SRAM_ADDRESS_HOLD_TIME 1 -#define SRAM_DATA_SETUP_TIME 6 -#define SRAM_BUS_TURNAROUND_DURATION 1 -#define SRAM_CLK_DIVISION 1 -#define SRAM_DATA_LATENCY 2 - -/* SRAM pin definitions */ - -#define SRAM_NADDRLINES 21 -#define SRAM_NDATALINES 16 - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* GPIOs Configuration ****************************************************** - * PD0 <-> FSMC_D2 PE0 <-> FSMC_NBL0 PF0 <-> FSMC_A0 PG0 <-> FSMC_A10 - * PD1 <-> FSMC_D3 PE1 <-> FSMC_NBL1 PF1 <-> FSMC_A1 PG1 <-> FSMC_A11 - * PD4 <-> FSMC_NOE PE3 <-> FSMC_A19 PF2 <-> FSMC_A2 PG2 <-> FSMC_A12 - * PD5 <-> FSMC_NWE PE4 <-> FSMC_A20 PF3 <-> FSMC_A3 PG3 <-> FSMC_A13 - * PD8 <-> FSMC_D13 PE7 <-> FSMC_D4 PF4 <-> FSMC_A4 PG4 <-> FSMC_A14 - * PD9 <-> FSMC_D14 PE8 <-> FSMC_D5 PF5 <-> FSMC_A5 PG5 <-> FSMC_A15 - * PD10 <-> FSMC_D15 PE9 <-> FSMC_D6 PF12 <-> FSMC_A6 PG9 <-> FSMC_NE2 - * PD11 <-> FSMC_A16 PE10 <-> FSMC_D7 PF13 <-> FSMC_A7 - * PD12 <-> FSMC_A17 PE11 <-> FSMC_D8 PF14 <-> FSMC_A8 - * PD13 <-> FSMC_A18 PE12 <-> FSMC_D9 PF15 <-> FSMC_A9 - * PD14 <-> FSMC_D0 PE13 <-> FSMC_D10 - * PD15 <-> FSMC_D1 PE14 <-> FSMC_D11 - * PE15 <-> FSMC_D12 - */ - -/* GPIO configurations unique to SRAM */ - -static const uint32_t g_sramconfig[] = -{ - /* NE3, NBL0, NBL1, */ - - GPIO_FSMC_NOE, GPIO_FSMC_NWE, GPIO_FSMC_NBL0, GPIO_FSMC_NBL1, GPIO_FSMC_NE2 -}; -#define NSRAM_CONFIG (sizeof(g_sramconfig)/sizeof(uint32_t)) - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_selectsram - * - * Description: - * Initialize to access external SRAM. SRAM will be visible at the FSMC - * Bank NOR/SRAM2 base address (0x64000000) - * - * General transaction rules. The requested AHB transaction data size can - * be 8-, 16- or 32-bit wide whereas the SRAM has a fixed 16-bit data - * width. Some simple transaction rules must be followed: - * - * Case 1: AHB transaction width and SRAM data width are equal - * There is no issue in this case. - * Case 2: AHB transaction size is greater than the memory size - * In this case, the FSMC splits the AHB transaction into smaller - * consecutive memory accesses in order to meet the external data width. - * Case 3: AHB transaction size is smaller than the memory size. - * SRAM supports the byte select feature. - * a) FSMC allows write transactions accessing the right data through its - * byte lanes (NBL[1:0]) - * b) Read transactions are allowed (the controller reads the entire - * memory word and uses the needed byte only). The NBL[1:0] are always - * kept low during read transactions. - * - ****************************************************************************/ - -void stm32_selectsram(void) -{ - /* Configure new GPIO pins */ - - stm32_extmemaddr(SRAM_NADDRLINES); /* Common address lines: A0-A20 */ - stm32_extmemdata(SRAM_NDATALINES); /* Common data lines: D0-D15 */ - stm32_extmemgpios(g_sramconfig, NSRAM_CONFIG); /* SRAM-specific control lines */ - - /* Enable AHB clocking to the FSMC */ - - stm32_fsmc_enable(); - - /* Bank1 NOR/SRAM control register configuration - * - * Bank enable : Not yet - * Data address mux : Disabled - * Memory Type : PSRAM - * Data bus width : 16-bits - * Flash access : Disabled - * Burst access mode : Disabled - * Polarity : Low - * Wrapped burst mode : Disabled - * Write timing : Before state - * Write enable : Yes - * Wait signal : Disabled - * Extended mode : Disabled - * Asynchronous wait : Disabled - * Write burst : Disabled - */ - - putreg32((FSMC_BCR_PSRAM | FSMC_BCR_MWID16 | - FSMC_BCR_WREN), STM32_FSMC_BCR2); - - /* Bank1 NOR/SRAM timing register configuration */ - - putreg32((FSMC_BTR_ADDSET(SRAM_ADDRESS_SETUP_TIME) | - FSMC_BTR_ADDHLD(SRAM_ADDRESS_HOLD_TIME) | - FSMC_BTR_DATAST(SRAM_DATA_SETUP_TIME) | - FSMC_BTR_BUSTURN(SRAM_BUS_TURNAROUND_DURATION) | - FSMC_BTR_CLKDIV(SRAM_CLK_DIVISION) | - FSMC_BTR_DATLAT(SRAM_DATA_LATENCY) | - FSMC_BTR_ACCMODA), - STM32_FSMC_BTR2); - - /* Bank1 NOR/SRAM timing register for write configuration, - * if extended mode is used - */ - - putreg32(0xffffffff, STM32_FSMC_BWTR2); /* Extended mode not used */ - - /* Enable the bank */ - - putreg32((FSMC_BCR_MBKEN | FSMC_BCR_PSRAM | - FSMC_BCR_MWID16 | FSMC_BCR_WREN), STM32_FSMC_BCR2); -} - -#endif /* CONFIG_STM32_FSMC */ diff --git a/boards/arm/stm32/stm3240g-eval/src/stm32_spi.c b/boards/arm/stm32/stm3240g-eval/src/stm32_spi.c deleted file mode 100644 index c2ca8d2be6b16..0000000000000 --- a/boards/arm/stm32/stm3240g-eval/src/stm32_spi.c +++ /dev/null @@ -1,129 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm3240g-eval/src/stm32_spi.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include "arm_internal.h" -#include "chip.h" -#include "stm32.h" -#include "stm3240g-eval.h" - -#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || defined(CONFIG_STM32_SPI3) - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_spidev_initialize - * - * Description: - * Called to configure SPI chip select GPIO pins for the STM3240G-EVAL - * board. - * - ****************************************************************************/ - -void weak_function stm32_spidev_initialize(void) -{ -#warning "Missing logic" -} - -/**************************************************************************** - * Name: stm32_spi1/2/3select and stm32_spi1/2/3status - * - * Description: - * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status - * must be provided by board-specific logic. They are implementations of - * the select and status methods of the SPI interface defined by struct - * spi_ops_s (see include/nuttx/spi/spi.h). All other methods - * (including stm32_spibus_initialize()) are provided by common STM32 - * logic. To use this common SPI logic on your board: - * - * 1. Provide logic in stm32_boardinitialize() to configure SPI chip select - * pins. - * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() functions - * in your board-specific logic. These functions will perform chip - * selection and status operations using GPIOs in the way your board is - * configured. - * 3. Add a calls to stm32_spibus_initialize() in your low level - * application initialization logic - * 4. The handle returned by stm32_spibus_initialize() may then be used to - * bind the SPI driver to higher level logic (e.g., calling - * mmcsd_spislotinitialize(), for example, will bind the SPI driver to - * the SPI MMC/SD driver). - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_SPI1 -void stm32_spi1select(struct spi_dev_s *dev, - uint32_t devid, bool selected) -{ - spiinfo("devid: %d CS: %s\n", - (int)devid, selected ? "assert" : "de-assert"); -} - -uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) -{ - return SPI_STATUS_PRESENT; -} -#endif - -#ifdef CONFIG_STM32_SPI2 -void stm32_spi2select(struct spi_dev_s *dev, - uint32_t devid, bool selected) -{ - spiinfo("devid: %d CS: %s\n", - (int)devid, selected ? "assert" : "de-assert"); -} - -uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) -{ - return SPI_STATUS_PRESENT; -} -#endif - -#ifdef CONFIG_STM32_SPI3 -void stm32_spi3select(struct spi_dev_s *dev, - uint32_t devid, bool selected) -{ - spiinfo("devid: %d CS: %s\n", - (int)devid, selected ? "assert" : "de-assert"); -} - -uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid) -{ - return SPI_STATUS_PRESENT; -} -#endif - -#endif /* CONFIG_STM32_SPI1 || CONFIG_STM32_SPI2 */ diff --git a/boards/arm/stm32/stm3240g-eval/src/stm32_stmpe811.c b/boards/arm/stm32/stm3240g-eval/src/stm32_stmpe811.c deleted file mode 100644 index 87334017a2f77..0000000000000 --- a/boards/arm/stm32/stm3240g-eval/src/stm32_stmpe811.c +++ /dev/null @@ -1,340 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm3240g-eval/src/stm32_stmpe811.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -#include - -#include "stm32.h" -#include "stm3240g-eval.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -#ifdef CONFIG_INPUT_STMPE811 -#ifndef CONFIG_INPUT -# error "STMPE811 support requires CONFIG_INPUT" -#endif - -#ifndef CONFIG_STM32_I2C1 -# error "STMPE811 support requires CONFIG_STM32_I2C1" -#endif - -#ifndef CONFIG_STMPE811_I2C -# error "Only the STMPE811 I2C interface is supported" -#endif - -#ifdef CONFIG_STMPE811_SPI -# error "Only the STMPE811 SPI interface is supported" -#endif - -#ifndef CONFIG_STMPE811_FREQUENCY -# define CONFIG_STMPE811_FREQUENCY 100000 -#endif - -#ifndef CONFIG_STMPE811_I2CDEV -# define CONFIG_STMPE811_I2CDEV 1 -#endif - -#if CONFIG_STMPE811_I2CDEV != 1 -# error "CONFIG_STMPE811_I2CDEV must be one" -#endif - -#ifndef CONFIG_STMPE811_DEVMINOR -# define CONFIG_STMPE811_DEVMINOR 0 -#endif - -/* Board definitions ********************************************************/ - -/* The STM3240G-EVAL has two STMPE811QTR I/O expanders on board both - * connected to the STM32 via I2C1. - * They share a common interrupt line: PI2. - * - * STMPE811 U24, I2C address 0x41 (7-bit) - * ------ ---- ---------------- -------------------------------------------- - * STPE11 PIN BOARD SIGNAL BOARD CONNECTION - * ------ ---- ---------------- -------------------------------------------- - * Y- TouchScreen_Y- LCD Connector XL - * X- TouchScreen_X- LCD Connector XR - * Y+ TouchScreen_Y+ LCD Connector XD - * X+ TouchScreen_X+ LCD Connector XU - * IN3 EXP_IO9 - * IN2 EXP_IO10 - * IN1 EXP_IO11 - * IN0 EXP_IO12 - * - * STMPE811 U29, I2C address 0x44 (7-bit) - * ------ ---- ---------------- -------------------------------------------- - * STPE11 PIN BOARD SIGNAL BOARD CONNECTION - * ------ ---- ---------------- -------------------------------------------- - * Y- EXP_IO1 - * X- EXP_IO2 - * Y+ EXP_IO3 - * X+ EXP_IO4 - * IN3 EXP_IO5 - * IN2 EXP_IO6 - * IN1 EXP_IO7 - * IN0 EXP_IO8 - */ - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -struct stm32_stmpe811config_s -{ - /* Configuration structure as seen by the STMPE811 driver */ - - struct stmpe811_config_s config; - - /* Additional private definitions only known to this driver */ - - STMPE811_HANDLE handle; /* The STMPE811 driver handle */ - xcpt_t handler; /* The STMPE811 interrupt handler */ - void *arg; /* Interrupt handler argument */ -}; - -/**************************************************************************** - * Static Function Prototypes - ****************************************************************************/ - -/* IRQ/GPIO access callbacks. These operations all hidden behind callbacks - * to isolate the STMPE811 driver from differences in GPIO - * interrupt handling by varying boards and MCUs.* so that contact and - * loss-of-contact events can be detected. - * - * attach - Attach the STMPE811 interrupt handler to the GPIO interrupt - * enable - Enable or disable the GPIO interrupt - * clear - Acknowledge/clear any pending GPIO interrupt - */ - -static int stmpe811_attach(struct stmpe811_config_s *state, xcpt_t isr, - void *arg); -static void stmpe811_enable(struct stmpe811_config_s *state, - bool enable); -static void stmpe811_clear(struct stmpe811_config_s *state); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* A reference to a structure of this type must be passed to the STMPE811 - * driver. This structure provides information about the configuration - * of the STMPE811 and provides some board-specific hooks. - * - * Memory for this structure is provided by the caller. It is not copied - * by the driver and is presumed to persist while the driver is active. The - * memory must be writable because, under certain circumstances, the driver - * may modify frequency or X plate resistance values. - */ - -#ifndef CONFIG_STMPE811_TSC_DISABLE -static struct stm32_stmpe811config_s g_stmpe811config = -{ - .config = - { -#ifdef CONFIG_STMPE811_I2C - .address = STMPE811_ADDR1, -#endif - .frequency = CONFIG_STMPE811_FREQUENCY, - -#ifdef CONFIG_STMPE811_MULTIPLE - .irq = STM32_IRQ_EXTI2, -#endif - .ctrl1 = (ADC_CTRL1_SAMPLE_TIME_80 | ADC_CTRL1_MOD_12B), - .ctrl2 = ADC_CTRL2_ADC_FREQ_3p25, - - .attach = stmpe811_attach, - .enable = stmpe811_enable, - .clear = stmpe811_clear, - }, - .handler = NULL, - .arg = NULL, -}; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/* IRQ/GPIO access callbacks. These operations all hidden behind - * callbacks to isolate the STMPE811 driver from differences in GPIO - * interrupt handling by varying boards and MCUs. - * - * attach - Attach the STMPE811 interrupt handler to the GPIO interrupt - * enable - Enable or disable the GPIO interrupt - * clear - Acknowledge/clear any pending GPIO interrupt - */ - -static int stmpe811_attach(struct stmpe811_config_s *state, xcpt_t isr, - void *arg) -{ - struct stm32_stmpe811config_s *priv = - (struct stm32_stmpe811config_s *)state; - - iinfo("Saving handler %p\n", isr); - DEBUGASSERT(priv); - - /* Just save the handler. - * We will use it when EXTI interruptsare enabled - */ - - priv->handler = isr; - priv->arg = arg; - return OK; -} - -static void stmpe811_enable(struct stmpe811_config_s *state, bool enable) -{ - struct stm32_stmpe811config_s *priv = - (struct stm32_stmpe811config_s *)state; - irqstate_t flags; - - /* Attach and enable, or detach and disable. Enabling and disabling GPIO - * interrupts is a multi-step process so the safest thing is to keep - * interrupts disabled during the reconfiguration. - */ - - flags = enter_critical_section(); - if (enable) - { - /* Configure the EXTI interrupt using the SAVED handler */ - - stm32_gpiosetevent(GPIO_IO_EXPANDER, true, true, true, - priv->handler, priv->arg); - } - else - { - /* Configure the EXTI interrupt with a NULL handler to disable it */ - - stm32_gpiosetevent(GPIO_IO_EXPANDER, false, false, false, - NULL, NULL); - } - - leave_critical_section(flags); -} - -static void stmpe811_clear(struct stmpe811_config_s *state) -{ - /* Does nothing */ -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_tsc_setup - * - * Description: - * This function is called by board-bringup logic to configure the - * touchscreen device. This function will register the driver as - * /dev/inputN where N is the minor device number. - * - * Input Parameters: - * minor - The input device minor number - * - * Returned Value: - * Zero is returned on success. Otherwise, a negated errno value is - * returned to indicate the nature of the failure. - * - ****************************************************************************/ - -int stm32_tsc_setup(int minor) -{ -#ifndef CONFIG_STMPE811_TSC_DISABLE - struct i2c_master_s *dev; - int ret; - - iinfo("minor %d\n", minor); - DEBUGASSERT(minor == 0); - - /* Check if we are already initialized */ - - if (!g_stmpe811config.handle) - { - iinfo("Initializing\n"); - - /* Configure the STMPE811 interrupt pin as an input */ - - stm32_configgpio(GPIO_IO_EXPANDER); - - /* Get an instance of the I2C interface */ - - dev = stm32_i2cbus_initialize(CONFIG_STMPE811_I2CDEV); - if (!dev) - { - ierr("ERROR: Failed to initialize I2C bus %d\n", - CONFIG_STMPE811_I2CDEV); - return -ENODEV; - } - - /* Instantiate the STMPE811 driver */ - - g_stmpe811config.handle = - stmpe811_instantiate(dev, - (struct stmpe811_config_s *)&g_stmpe811config); - if (!g_stmpe811config.handle) - { - ierr("ERROR: Failed to instantiate the STMPE811 driver\n"); - return -ENODEV; - } - - /* Initialize and register the I2C touchscreen device */ - - ret = stmpe811_register(g_stmpe811config.handle, - CONFIG_STMPE811_DEVMINOR); - if (ret < 0) - { - ierr("ERROR: Failed to register STMPE driver: %d\n", ret); - - /* stm32_i2cbus_uninitialize(dev); */ - - return -ENODEV; - } - } - - return OK; -#else - return -ENOSYS; -#endif -} - -#endif /* CONFIG_INPUT_STMPE811 */ diff --git a/boards/arm/stm32/stm3240g-eval/src/stm32_usb.c b/boards/arm/stm32/stm3240g-eval/src/stm32_usb.c deleted file mode 100644 index e09730cee8fa4..0000000000000 --- a/boards/arm/stm32/stm3240g-eval/src/stm32_usb.c +++ /dev/null @@ -1,304 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm3240g-eval/src/stm32_usb.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -#include "arm_internal.h" -#include "stm32.h" -#include "stm32_otgfs.h" -#include "stm3240g-eval.h" - -#ifdef CONFIG_STM32_OTGFS - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#if defined(CONFIG_USBDEV) || defined(CONFIG_USBHOST) -# define HAVE_USB 1 -#else -# warning "CONFIG_STM32_OTGFS is enabled but neither CONFIG_USBDEV nor CONFIG_USBHOST" -# undef HAVE_USB -#endif - -#ifndef CONFIG_USBHOST_DEFPRIO -# define CONFIG_USBHOST_DEFPRIO 50 -#endif - -#ifndef CONFIG_USBHOST_STACKSIZE -# ifdef CONFIG_USBHOST_HUB -# define CONFIG_USBHOST_STACKSIZE 1536 -# else -# define CONFIG_USBHOST_STACKSIZE 1024 -# endif -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -#ifdef CONFIG_USBHOST -static struct usbhost_connection_s *g_usbconn; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: usbhost_waiter - * - * Description: - * Wait for USB devices to be connected. - * - ****************************************************************************/ - -#ifdef CONFIG_USBHOST -static int usbhost_waiter(int argc, char *argv[]) -{ - struct usbhost_hubport_s *hport; - - uinfo("Running\n"); - for (; ; ) - { - /* Wait for the device to change state */ - - DEBUGVERIFY(CONN_WAIT(g_usbconn, &hport)); - uinfo("%s\n", hport->connected ? "connected" : "disconnected"); - - /* Did we just become connected? */ - - if (hport->connected) - { - /* Yes.. enumerate the newly connected device */ - - CONN_ENUMERATE(g_usbconn, hport); - } - } - - /* Keep the compiler from complaining */ - - return 0; -} -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_usbinitialize - * - * Description: - * Called from stm32_usbinitialize very early in initialization to setup - * USB-related GPIO pins for the STM3240G-EVAL board. - * - ****************************************************************************/ - -void stm32_usbinitialize(void) -{ - /* The OTG FS has an internal soft pull-up. - * No GPIO configuration is required - */ - - /* Configure the OTG FS VBUS sensing GPIO, - * Power On, and Overcurrent GPIOs - */ - -#ifdef CONFIG_STM32_OTGFS - stm32_configgpio(GPIO_OTGFS_VBUS); - stm32_configgpio(GPIO_OTGFS_PWRON); - stm32_configgpio(GPIO_OTGFS_OVER); -#endif -} - -/**************************************************************************** - * Name: stm32_usbhost_initialize - * - * Description: - * Called at application startup time to initialize the USB host - * functionality. - * This function will start a thread that will monitor for device - * connection/disconnection events. - * - ****************************************************************************/ - -#ifdef CONFIG_USBHOST -int stm32_usbhost_initialize(void) -{ - int ret; - - /* First, register all of the class drivers needed to support the drivers - * that we care about: - */ - - uinfo("Register class drivers\n"); - -#ifdef CONFIG_USBHOST_MSC - /* Register the USB mass storage class class */ - - ret = usbhost_msc_initialize(); - if (ret != OK) - { - uerr("ERROR: Failed to register the mass storage class: %d\n", ret); - } -#endif - -#ifdef CONFIG_USBHOST_CDCACM - /* Register the CDC/ACM serial class */ - - ret = usbhost_cdcacm_initialize(); - if (ret != OK) - { - uerr("ERROR: Failed to register the CDC/ACM serial class: %d\n", ret); - } -#endif - - /* Then get an instance of the USB host interface */ - - uinfo("Initialize USB host\n"); - g_usbconn = stm32_otgfshost_initialize(0); - if (g_usbconn) - { - /* Start a thread to handle device connection. */ - - uinfo("Start usbhost_waiter\n"); - - ret = kthread_create("usbhost", CONFIG_USBHOST_DEFPRIO, - CONFIG_USBHOST_STACKSIZE, - usbhost_waiter, NULL); - return ret < 0 ? -ENOEXEC : OK; - } - - return -ENODEV; -} -#endif - -/**************************************************************************** - * Name: stm32_usbhost_vbusdrive - * - * Description: - * Enable/disable driving of VBUS 5V output. This function must be - * provided be each platform that implements the STM32 OTG FS host - * interface - * - * "On-chip 5 V VBUS generation is not supported. For this reason, a - * charge pump or, if 5 V are available on the application board, a - * basic power switch, must be added externally to drive the 5 V VBUS - * line. The external charge pump can be driven by any GPIO output. - * When the application decides to power on VBUS using the chosen GPIO, - * it must also set the port power bit in the host port control and - * status register (PPWR bit in OTG_FS_HPRT). - * - * "The application uses this field to control power to this port, - * and the core clears this bit on an overcurrent condition." - * - * Input Parameters: - * iface - For future growth to handle multiple USB host interface. - * Should be zero. - * enable - true: enable VBUS power; false: disable VBUS power - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef CONFIG_USBHOST -void stm32_usbhost_vbusdrive(int iface, bool enable) -{ - DEBUGASSERT(iface == 0); - - if (enable) - { - /* Enable the Power Switch by driving the enable pin low */ - - stm32_gpiowrite(GPIO_OTGFS_PWRON, false); - } - else - { - /* Disable the Power Switch by driving the enable pin high */ - - stm32_gpiowrite(GPIO_OTGFS_PWRON, true); - } -} -#endif - -/**************************************************************************** - * Name: stm32_setup_overcurrent - * - * Description: - * Setup to receive an interrupt-level callback if an overcurrent - * condition is detected. - * - * Input Parameters: - * handler - New overcurrent interrupt handler - * arg - The argument provided for the interrupt handler - * - * Returned Value: - * Zero (OK) is returned on success. Otherwise, a negated errno value - * is returned to indicate the nature of the failure. - * - ****************************************************************************/ - -#ifdef CONFIG_USBHOST -int stm32_setup_overcurrent(xcpt_t handler, void *arg) -{ - return stm32_gpiosetevent(GPIO_OTGFS_OVER, true, true, true, handler, arg); -} -#endif - -/**************************************************************************** - * Name: stm32_usbsuspend - * - * Description: - * Board logic must provide the stm32_usbsuspend logic if the USBDEV - * driver is used. This function is called whenever the USB enters or - * leaves suspend mode. This is an opportunity for the board logic to - * shutdown clocks, power, etc. while the USB is suspended. - * - ****************************************************************************/ - -#ifdef CONFIG_USBDEV -void stm32_usbsuspend(struct usbdev_s *dev, bool resume) -{ - uinfo("resume: %d\n", resume); -} -#endif - -#endif /* CONFIG_STM32_OTGFS */ diff --git a/boards/arm/stm32/stm3240g-eval/src/stm32_userleds.c b/boards/arm/stm32/stm3240g-eval/src/stm32_userleds.c deleted file mode 100644 index 61299ea969ecd..0000000000000 --- a/boards/arm/stm32/stm3240g-eval/src/stm32_userleds.c +++ /dev/null @@ -1,96 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm3240g-eval/src/stm32_userleds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32.h" -#include "stm3240g-eval.h" - -#ifndef CONFIG_ARCH_LEDS - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* This array maps an LED number to GPIO pin configuration */ - -static uint32_t g_ledcfg[BOARD_NLEDS] = -{ - GPIO_LED1, GPIO_LED2, GPIO_LED3, GPIO_LED4 -}; - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_userled_initialize - ****************************************************************************/ - -uint32_t board_userled_initialize(void) -{ - /* Configure LED1-4 GPIOs for output */ - - stm32_configgpio(GPIO_LED1); - stm32_configgpio(GPIO_LED2); - stm32_configgpio(GPIO_LED3); - stm32_configgpio(GPIO_LED4); - return BOARD_NLEDS; -} - -/**************************************************************************** - * Name: board_userled - ****************************************************************************/ - -void board_userled(int led, bool ledon) -{ - if ((unsigned)led < BOARD_NLEDS) - { - stm32_gpiowrite(g_ledcfg[led], ledon); - } -} - -/**************************************************************************** - * Name: board_userled_all - ****************************************************************************/ - -void board_userled_all(uint32_t ledset) -{ - stm32_gpiowrite(GPIO_LED1, (ledset & BOARD_LED1_BIT) == 0); - stm32_gpiowrite(GPIO_LED2, (ledset & BOARD_LED2_BIT) == 0); - stm32_gpiowrite(GPIO_LED3, (ledset & BOARD_LED3_BIT) == 0); - stm32_gpiowrite(GPIO_LED4, (ledset & BOARD_LED4_BIT) == 0); -} - -#endif /* !CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/stm32_tiny/CMakeLists.txt b/boards/arm/stm32/stm32_tiny/CMakeLists.txt deleted file mode 100644 index 6b35bfde309f2..0000000000000 --- a/boards/arm/stm32/stm32_tiny/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/stm32_tiny/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32/stm32_tiny/configs/nsh/defconfig b/boards/arm/stm32/stm32_tiny/configs/nsh/defconfig deleted file mode 100644 index 221484c5f5975..0000000000000 --- a/boards/arm/stm32/stm32_tiny/configs/nsh/defconfig +++ /dev/null @@ -1,57 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_DISABLE_OS_API is not set -# CONFIG_NSH_DISABLESCRIPT is not set -# CONFIG_NSH_DISABLE_EXEC is not set -# CONFIG_NSH_DISABLE_EXIT is not set -# CONFIG_NSH_DISABLE_GET is not set -# CONFIG_NSH_DISABLE_HEXDUMP is not set -# CONFIG_NSH_DISABLE_MKRD is not set -# CONFIG_NSH_DISABLE_PS is not set -# CONFIG_NSH_DISABLE_PUT is not set -# CONFIG_NSH_DISABLE_WGET is not set -# CONFIG_NSH_DISABLE_XD is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32_tiny" -CONFIG_ARCH_BOARD_COMMON=y -CONFIG_ARCH_BOARD_STM32_TINY=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F103C8=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_ARM_TOOLCHAIN_BUILDROOT=y -CONFIG_BOARD_LOOPSPERMSEC=5483 -CONFIG_BUILTIN=y -CONFIG_DEFAULT_SMALL=y -CONFIG_DRIVERS_WIRELESS=y -CONFIG_EXAMPLES_NRF24L01TERM=y -CONFIG_FILE_STREAM=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_LINE_MAX=80 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=1024 -CONFIG_RAM_SIZE=20480 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_HPWORKPRIORITY=192 -CONFIG_SCHED_WAITPID=y -CONFIG_SERIAL_TERMIOS=y -CONFIG_START_DAY=5 -CONFIG_START_MONTH=7 -CONFIG_START_YEAR=2011 -CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32_JTAG_FULL_ENABLE=y -CONFIG_STM32_SPI2=y -CONFIG_STM32_USART1=y -CONFIG_SYMTAB_ORDEREDBYNAME=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART1_SERIAL_CONSOLE=y -CONFIG_WL_NRF24L01=y diff --git a/boards/arm/stm32/stm32_tiny/configs/usbnsh/defconfig b/boards/arm/stm32/stm32_tiny/configs/usbnsh/defconfig deleted file mode 100644 index 39ded7939a64a..0000000000000 --- a/boards/arm/stm32/stm32_tiny/configs/usbnsh/defconfig +++ /dev/null @@ -1,55 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_DEV_CONSOLE is not set -# CONFIG_DISABLE_OS_API is not set -# CONFIG_NSH_DISABLEBG is not set -# CONFIG_NSH_DISABLESCRIPT is not set -# CONFIG_NSH_DISABLE_EXEC is not set -# CONFIG_NSH_DISABLE_EXIT is not set -# CONFIG_NSH_DISABLE_GET is not set -# CONFIG_NSH_DISABLE_HEXDUMP is not set -# CONFIG_NSH_DISABLE_MKRD is not set -# CONFIG_NSH_DISABLE_PS is not set -# CONFIG_NSH_DISABLE_PUT is not set -# CONFIG_NSH_DISABLE_WGET is not set -# CONFIG_NSH_DISABLE_XD is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32_tiny" -CONFIG_ARCH_BOARD_STM32_TINY=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F103C8=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARDCTL_USBDEVCTRL=y -CONFIG_BOARD_LOOPSPERMSEC=5483 -CONFIG_BUILTIN=y -CONFIG_CDCACM=y -CONFIG_CDCACM_CONSOLE=y -CONFIG_CDCACM_RXBUFSIZE=256 -CONFIG_CDCACM_TXBUFSIZE=256 -CONFIG_DEFAULT_SMALL=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_LINE_MAX=80 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=1024 -CONFIG_RAM_SIZE=20480 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=5 -CONFIG_START_MONTH=7 -CONFIG_START_YEAR=2011 -CONFIG_STM32_JTAG_FULL_ENABLE=y -CONFIG_STM32_USART1=y -CONFIG_STM32_USB=y -CONFIG_SYMTAB_ORDEREDBYNAME=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USBDEV_TRACE=y -CONFIG_USBDEV_TRACE_NRECORDS=32 diff --git a/boards/arm/stm32/stm32_tiny/include/board.h b/boards/arm/stm32/stm32_tiny/include/board.h deleted file mode 100644 index 26354257da2e5..0000000000000 --- a/boards/arm/stm32/stm32_tiny/include/board.h +++ /dev/null @@ -1,182 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32_tiny/include/board.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __BOARD_ARM_STM32_STM32_TINY_INCLUDE_BOARD_H -#define __BOARD_ARM_STM32_STM32_TINY_INCLUDE_BOARD_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#ifndef __ASSEMBLY__ -# include -#endif - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Clocking *****************************************************************/ - -/* On-board crystal frequency is 8MHz (HSE) */ - -#define STM32_BOARD_XTAL 8000000ul - -/* PLL source is HSE/1, PLL multiplier is 9: PLL frequency is - * 8MHz (XTAL) x 9 = 72MHz - */ - -#define STM32_CFGR_PLLSRC RCC_CFGR_PLLSRC -#define STM32_CFGR_PLLXTPRE 0 -#define STM32_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx9 -#define STM32_PLL_FREQUENCY (9*STM32_BOARD_XTAL) - -/* Use the PLL and set the SYSCLK source to be the PLL */ - -#define STM32_SYSCLK_SW RCC_CFGR_SW_PLL -#define STM32_SYSCLK_SWS RCC_CFGR_SWS_PLL -#define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY - -/* AHB clock (HCLK) is SYSCLK (72MHz) */ - -#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK -#define STM32_HCLK_FREQUENCY STM32_PLL_FREQUENCY - -/* APB2 clock (PCLK2) is HCLK (72MHz) */ - -#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK -#define STM32_PCLK2_FREQUENCY STM32_HCLK_FREQUENCY - -/* APB2 timers 1 and 8 will receive PCLK2. */ - -#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) - -/* APB1 clock (PCLK1) is HCLK/2 (36MHz) */ - -#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd2 -#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/2) - -/* APB1 timers 2-7 will be twice PCLK1 */ - -#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) - -/* USB divider -- Divide PLL clock by 1.5 */ - -#define STM32_CFGR_USBPRE 0 - -/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx - * otherwise frequency is 2xAPBx. - * Note: TIM1,8 are on APB2, others on APB1 - */ - -#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM2_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM3_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM4_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM5_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM6_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM7_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY - -/* SDIO dividers. Note that slower clocking is required when DMA is disabled - * in order to avoid RX overrun/TX underrun errors due to delayed responses - * to service FIFOs in interrupt driven mode. These values have not been - * tuned!!! - * - * HCLK=72MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(178+2)=400 KHz - */ - -#define SDIO_INIT_CLKDIV (178 << SDIO_CLKCR_CLKDIV_SHIFT) - -/* DMA ON: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(2+2)=18 MHz - * DMA OFF: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(3+2)=14.4 MHz - */ - -#ifdef CONFIG_SDIO_DMA -# define SDIO_MMCXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT) -#else -# define SDIO_MMCXFR_CLKDIV (3 << SDIO_CLKCR_CLKDIV_SHIFT) -#endif - -/* DMA ON: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(1+2)=24 MHz - * DMA OFF: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(3+2)=14.4 MHz - */ - -#ifdef CONFIG_SDIO_DMA -# define SDIO_SDXFR_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT) -#else -# define SDIO_SDXFR_CLKDIV (3 << SDIO_CLKCR_CLKDIV_SHIFT) -#endif - -/* LED definitions **********************************************************/ - -/* The board has only one controllable LED */ -#define LED_STARTED 0 /* No LEDs */ -#define LED_HEAPALLOCATE 1 /* LED1 on */ -#define LED_IRQSENABLED 2 /* LED2 on */ -#define LED_STACKCREATED 3 /* LED1 on */ -#define LED_INIRQ 4 /* LED1 off */ -#define LED_SIGNAL 5 /* LED2 on */ -#define LED_ASSERTION 6 /* LED1 + LED2 */ -#define LED_PANIC 7 /* LED1 / LED2 blinking */ - -/* NRF24L01 Driver **********************************************************/ - -/* NRF24L01 chip enable: PB.1 */ - -#define GPIO_NRF24L01_CE (GPIO_OUTPUT|GPIO_CNF_OUTPP|GPIO_MODE_50MHz|\ - GPIO_OUTPUT_CLEAR|GPIO_PORTB|GPIO_PIN1) - -/* NRF24L01 IRQ line: PA.0 */ - -#define GPIO_NRF24L01_IRQ (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_PORTA|GPIO_PIN0) - -#define BOARD_NRF24L01_GPIO_CE GPIO_NRF24L01_CE -#define BOARD_NRF24L01_GPIO_IRQ GPIO_NRF24L01_IRQ - -/* Alternate function pin selections (auto-aliased for new pinmap) */ - -/* USART1 */ - -#define GPIO_USART1_TX GPIO_ADJUST_MODE(GPIO_USART1_TX_0, GPIO_MODE_50MHz) -#define GPIO_USART1_RX GPIO_USART1_RX_0 - -/* SPI2 */ - -#define GPIO_SPI2_NSS GPIO_ADJUST_MODE(GPIO_SPI2_NSS_0, GPIO_MODE_50MHz) -#define GPIO_SPI2_SCK GPIO_ADJUST_MODE(GPIO_SPI2_SCK_0, GPIO_MODE_50MHz) -#define GPIO_SPI2_MISO GPIO_ADJUST_MODE(GPIO_SPI2_MISO_0, GPIO_MODE_50MHz) -#define GPIO_SPI2_MOSI GPIO_ADJUST_MODE(GPIO_SPI2_MOSI_0, GPIO_MODE_50MHz) - -/* USB */ - -#define GPIO_USB_DM GPIO_USB_DM_0 -#define GPIO_USB_DP GPIO_USB_DP_0 - -#endif /* __ARCH_ARM_STM32_STM32_TINY_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32/stm32_tiny/scripts/Make.defs b/boards/arm/stm32/stm32_tiny/scripts/Make.defs deleted file mode 100644 index 3093bfc93eed8..0000000000000 --- a/boards/arm/stm32/stm32_tiny/scripts/Make.defs +++ /dev/null @@ -1,41 +0,0 @@ -############################################################################ -# boards/arm/stm32/stm32_tiny/scripts/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/.config -include $(TOPDIR)/tools/Config.mk -include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs - -LDSCRIPT = ld.script -ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) - -ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 - -CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) -CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) -CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -AFLAGS := $(CFLAGS) -D__ASSEMBLY__ - -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections -LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32/stm32_tiny/scripts/ld.script b/boards/arm/stm32/stm32_tiny/scripts/ld.script deleted file mode 100644 index 4ce9e558389d1..0000000000000 --- a/boards/arm/stm32/stm32_tiny/scripts/ld.script +++ /dev/null @@ -1,122 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32_tiny/scripts/ld.script - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* The STM32F103C8T6 has 64Kb of FLASH beginning at address 0x0800:0000 and - * 20Kb of SRAM beginning at address 0x2000:0000. When booting from FLASH, - * FLASH memory is aliased to address 0x0000:0000 where the code expects to - * begin execution by jumping to the entry point in the 0x0800:0000 address - * range. - */ - -MEMORY -{ - flash (rx) : ORIGIN = 0x08000000, LENGTH = 64K - sram (rwx) : ORIGIN = 0x20000000, LENGTH = 20K -} - -OUTPUT_ARCH(arm) -EXTERN(_vectors) -ENTRY(_stext) -SECTIONS -{ - .text : { - _stext = ABSOLUTE(.); - *(.vectors) - *(.text .text.*) - *(.fixup) - *(.gnu.warning) - *(.rodata .rodata.*) - *(.gnu.linkonce.t.*) - *(.glue_7) - *(.glue_7t) - *(.got) - *(.gcc_except_table) - *(.gnu.linkonce.r.*) - _etext = ABSOLUTE(.); - } > flash - - .init_section : ALIGN(4) { - _sinit = ABSOLUTE(.); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) - KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) - _einit = ABSOLUTE(.); - } > flash - - .ARM.extab : ALIGN(4) { - *(.ARM.extab*) - } > flash - - .ARM.exidx : ALIGN(4) { - __exidx_start = ABSOLUTE(.); - *(.ARM.exidx*) - __exidx_end = ABSOLUTE(.); - } > flash - - .tdata : { - _stdata = ABSOLUTE(.); - *(.tdata .tdata.* .gnu.linkonce.td.*); - _etdata = ABSOLUTE(.); - } > flash - - .tbss : { - _stbss = ABSOLUTE(.); - *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); - _etbss = ABSOLUTE(.); - } > flash - - _eronly = ABSOLUTE(.); - - /* The STM32F103C8T6 has 20Kb of SRAM beginning at the following address */ - - .data : ALIGN(4) { - _sdata = ABSOLUTE(.); - *(.data .data.*) - *(.gnu.linkonce.d.*) - CONSTRUCTORS - . = ALIGN(4); - _edata = ABSOLUTE(.); - } > sram AT > flash - - .bss : ALIGN(4) { - _sbss = ABSOLUTE(.); - *(.bss .bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - . = ALIGN(4); - _ebss = ABSOLUTE(.); - } > sram - - /* Stabs debugging sections. */ - - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_info 0 : { *(.debug_info) } - .debug_line 0 : { *(.debug_line) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_aranges 0 : { *(.debug_aranges) } -} diff --git a/boards/arm/stm32/stm32_tiny/src/CMakeLists.txt b/boards/arm/stm32/stm32_tiny/src/CMakeLists.txt deleted file mode 100644 index c73b5cfb5bddf..0000000000000 --- a/boards/arm/stm32/stm32_tiny/src/CMakeLists.txt +++ /dev/null @@ -1,31 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/stm32_tiny/src/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -set(SRCS stm32_boot.c stm32_leds.c stm32_spi.c stm32_usbdev.c) - -if(CONFIG_PWM) - list(APPEND SRCS stm32_pwm.c) -endif() - -target_sources(board PRIVATE ${SRCS}) - -set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/ld.script") diff --git a/boards/arm/stm32/stm32_tiny/src/Make.defs b/boards/arm/stm32/stm32_tiny/src/Make.defs deleted file mode 100644 index a8268fc340102..0000000000000 --- a/boards/arm/stm32/stm32_tiny/src/Make.defs +++ /dev/null @@ -1,33 +0,0 @@ -############################################################################ -# boards/arm/stm32/stm32_tiny/src/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/Make.defs - -CSRCS = stm32_boot.c stm32_leds.c stm32_spi.c stm32_usbdev.c - -ifeq ($(CONFIG_PWM),y) -CSRCS += stm32_pwm.c -endif - -DEPPATH += --dep-path board -VPATH += :board -CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/stm32_tiny/src/stm32_boot.c b/boards/arm/stm32/stm32_tiny/src/stm32_boot.c deleted file mode 100644 index 978fee88af4d1..0000000000000 --- a/boards/arm/stm32/stm32_tiny/src/stm32_boot.c +++ /dev/null @@ -1,129 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32_tiny/src/stm32_boot.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include -#include - -#include -#include - -#include "arm_internal.h" -#include "stm32_tiny.h" - -#ifdef CONFIG_WL_NRF24L01 -#include "stm32_nrf24l01.h" -#endif - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_boardinitialize - * - * Description: - * All STM32 architectures must provide the following entry point. This - * entry point is called early in the initialization -- after all memory - * has been configured and mapped but before any devices have been - * initialized. - * - ****************************************************************************/ - -void stm32_boardinitialize(void) -{ - /* Configure on-board LEDs if LED support has been selected. */ - -#ifdef CONFIG_ARCH_LEDS - board_autoled_initialize(); -#endif - - /* Configure SPI chip selects if 1) SPI is not disabled, and 2) the weak - * function stm32_spidev_initialize() has been brought into the link. - */ - -#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) - stm32_spidev_initialize(); -#endif - - /* Initialize USB is 1) USBDEV is selected, 2) the USB controller is not - * disabled, and 3) the weak function stm32_usbinitialize() has been - * brought into the build. - */ - -#if defined(CONFIG_USBDEV) && defined(CONFIG_STM32_USB) - stm32_usbinitialize(); -#endif -} - -/**************************************************************************** - * Name: board_late_initialize - * - * Description: - * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional - * initialization call will be performed in the boot-up sequence to a - * function called board_late_initialize(). board_late_initialize() will - * be called immediately after up_initialize() is called and just before - * the initial application is started. This additional initialization - * phase may be used, for example, to initialize board-specific device - * drivers. - * - ****************************************************************************/ - -#ifdef CONFIG_BOARD_LATE_INITIALIZE -void board_late_initialize(void) -{ - int ret = OK; - -#ifdef CONFIG_PWM - /* Initialize PWM and register the PWM device. */ - - ret = stm32_pwm_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_pwm_setup() failed: %d\n", ret); - } -#endif - -#if defined(CONFIG_WL_NRF24L01) - /* Initialize the NRF24L01 wireless module */ - - ret = board_nrf24l01_initialize(2); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: board_nrf24l01_initialize failed: %d\n", ret); - } -#endif -} -#endif diff --git a/boards/arm/stm32/stm32_tiny/src/stm32_leds.c b/boards/arm/stm32/stm32_tiny/src/stm32_leds.c deleted file mode 100644 index 96ed9bf54df39..0000000000000 --- a/boards/arm/stm32/stm32_tiny/src/stm32_leds.c +++ /dev/null @@ -1,110 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32_tiny/src/stm32_leds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32.h" -#include "stm32_tiny.h" - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -static inline void set_led(bool v) -{ - ledinfo("Turn LED %s\n", v? "on":"off"); - stm32_gpiowrite(GPIO_LED, v); -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_autoled_initialize - ****************************************************************************/ - -#ifdef CONFIG_ARCH_LEDS -void board_autoled_initialize(void) -{ - /* Configure LED GPIO for output */ - - stm32_configgpio(GPIO_LED); -} - -/**************************************************************************** - * Name: board_autoled_on - ****************************************************************************/ - -void board_autoled_on(int led) -{ - ledinfo("board_autoled_on(%d)\n", led); - switch (led) - { - case LED_STARTED: - case LED_HEAPALLOCATE: - /* As the board provides only one soft controllable LED, - * we simply turn it on when the board boots - */ - - set_led(true); - break; - case LED_PANIC: - - /* For panic state, the LED is blinking */ - - set_led(true); - break; - } -} - -/**************************************************************************** - * Name: board_autoled_off - ****************************************************************************/ - -void board_autoled_off(int led) -{ - switch (led) - { - case LED_PANIC: - - /* For panic state, the LED is blinking */ - - set_led(false); - break; - } -} - -#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/stm32_tiny/src/stm32_pwm.c b/boards/arm/stm32/stm32_tiny/src/stm32_pwm.c deleted file mode 100644 index 3a4f9982399d0..0000000000000 --- a/boards/arm/stm32/stm32_tiny/src/stm32_pwm.c +++ /dev/null @@ -1,103 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32_tiny/src/stm32_pwm.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include - -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32_pwm.h" -#include "stm32_tiny.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -/* PWM - * - * The STM32 Tiny board provides a LED on GPIO line B5. - */ - -#ifdef CONFIG_PWM - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_pwm_setup - * - * Description: - * Initialize PWM and register the PWM device. - * - ****************************************************************************/ - -int stm32_pwm_setup(void) -{ - static bool initialized = false; - struct pwm_lowerhalf_s *pwm; - int ret; - - /* Have we already initialized? */ - - if (!initialized) - { - /* Call stm32_pwminitialize() to get an instance of the PWM interface */ - - pwm = stm32_pwminitialize(STM32TINY_PWMTIMER); - if (!pwm) - { - aerr("ERROR: Failed to get the STM32 PWM lower half\n"); - return -ENODEV; - } - - /* Register the PWM driver at "/dev/pwm0" */ - - ret = pwm_register("/dev/pwm0", pwm); - if (ret < 0) - { - aerr("ERROR: pwm_register failed: %d\n", ret); - return ret; - } - - /* Now we are initialized */ - - initialized = true; - } - - return OK; -} - -#endif /* CONFIG_PWM */ diff --git a/boards/arm/stm32/stm32_tiny/src/stm32_spi.c b/boards/arm/stm32/stm32_tiny/src/stm32_spi.c deleted file mode 100644 index ff9d37e515ab3..0000000000000 --- a/boards/arm/stm32/stm32_tiny/src/stm32_spi.c +++ /dev/null @@ -1,151 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32_tiny/src/stm32_spi.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include "arm_internal.h" -#include "chip.h" -#include "stm32.h" -#include "stm32_tiny.h" - -#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_spidev_initialize - * - * Description: - * Called to configure SPI chip select GPIO pins for the HY-MiniSTM32 - * board. - * - ****************************************************************************/ - -void stm32_spidev_initialize(void) -{ - /* NOTE: Clocking for SPI1 and/or SPI2 was already provided in stm32_rcc.c. - * Configurations of SPI pins is performed in stm32_spi.c. - * Here, we only initialize chip select pins unique to the board - * architecture. - */ - -#ifdef CONFIG_STM32_SPI2 -# ifdef CONFIG_WL_NRF24L01 - /* Configure the SPI-based NRF24L01 chip select GPIO */ - - spiinfo("Configure GPIO for SPI2/CS\n"); - stm32_configgpio(GPIO_NRF24L01_CS); -# endif -#endif -} - -/**************************************************************************** - * Name: stm32_spi1/2select and stm32_spi1/2status - * - * Description: - * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status - * must be provided by board-specific logic. They are implementations of - * the select and status methods of the SPI interface defined by struct - * spi_ops_s (see include/nuttx/spi/spi.h). All other methods (including - * stm32_spibus_initialize()) are provided by common STM32 logic. - * To use this common SPI logic on your board: - * - * 1. Provide logic in stm32_boardinitialize() to configure SPI chip - * select pins. - * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() functions - * in your board-specific logic. These functions will perform chip - * selection and status operations using GPIOs in the way your board is - * configured. - * 3. Add a calls to stm32_spibus_initialize() in your low level - * application initialization logic - * 4. The handle returned by stm32_spibus_initialize() may then be used to - * bind the SPI driver to higher level logic (e.g., calling - * mmcsd_spislotinitialize(), for example, will bind the SPI driver to - * the SPI MMC/SD driver). - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_SPI1 -void stm32_spi1select(struct spi_dev_s *dev, - uint32_t devid, bool selected) -{ -} - -uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) -{ - return 0; -} -#endif - -#ifdef CONFIG_STM32_SPI2 -void stm32_spi2select(struct spi_dev_s *dev, - uint32_t devid, bool selected) -{ - switch (devid) - { -#ifdef CONFIG_WL_NRF24L01 - case SPIDEV_WIRELESS(0): - spiinfo("nRF24L01 device %s\n", selected ? "asserted" : "de-asserted"); - - /* Set the GPIO low to select and high to de-select */ - - stm32_gpiowrite(GPIO_NRF24L01_CS, !selected); - break; -#endif - default: - break; - } -} - -uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) -{ - uint8_t status = 0; - switch (devid) - { -#ifdef CONFIG_WL_NRF24L01 - case SPIDEV_WIRELESS(0): - status |= SPI_STATUS_PRESENT; - break; -#endif - default: - break; - } - - return status; -} - -#endif - -#endif /* CONFIG_STM32_SPI1 || CONFIG_STM32_SPI2 */ diff --git a/boards/arm/stm32/stm32_tiny/src/stm32_usbdev.c b/boards/arm/stm32/stm32_tiny/src/stm32_usbdev.c deleted file mode 100644 index 34a13f0c6fc68..0000000000000 --- a/boards/arm/stm32/stm32_tiny/src/stm32_usbdev.c +++ /dev/null @@ -1,106 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32_tiny/src/stm32_usbdev.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include - -#include -#include - -#include "arm_internal.h" -#include "stm32.h" -#include "stm32_tiny.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_usbinitialize - * - * Description: - * Called to setup USB-related GPIO pins for the Hy-Mini STM32v board. - * - ****************************************************************************/ - -void stm32_usbinitialize(void) -{ - uinfo("called\n"); - - /* USB Soft Connect Pullup */ - - stm32_configgpio(GPIO_USB_PULLUP); -} - -/**************************************************************************** - * Name: stm32_usbpullup - * - * Description: - * If USB is supported and the board supports a pullup via GPIO (for USB - * software connect and disconnect), then the board software must provide - * stm32_pullup. - * See include/nuttx/usb/usbdev.h for additional description of this - * method. - * Alternatively, if no pull-up GPIO the following EXTERN can be redefined - * to be NULL. - * - ****************************************************************************/ - -int stm32_usbpullup(struct usbdev_s *dev, bool enable) -{ - usbtrace(TRACE_DEVPULLUP, (uint16_t)enable); - stm32_gpiowrite(GPIO_USB_PULLUP, !enable); - return OK; -} - -/**************************************************************************** - * Name: stm32_usbsuspend - * - * Description: - * Board logic must provide the stm32_usbsuspend logic if the USBDEV - * driver is used. This function is called whenever the USB enters or - * leaves suspend mode. - * This is an opportunity for the board logic to shutdown clocks, power, - * etc. while the USB is suspended. - * - ****************************************************************************/ - -void stm32_usbsuspend(struct usbdev_s *dev, bool resume) -{ - uinfo("resume: %d\n", resume); -} diff --git a/boards/arm/stm32/stm32butterfly2/CMakeLists.txt b/boards/arm/stm32/stm32butterfly2/CMakeLists.txt deleted file mode 100644 index 9daf994ef1404..0000000000000 --- a/boards/arm/stm32/stm32butterfly2/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/stm32butterfly2/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32/stm32butterfly2/configs/nsh/defconfig b/boards/arm/stm32/stm32butterfly2/configs/nsh/defconfig deleted file mode 100644 index 79655e199f1a4..0000000000000 --- a/boards/arm/stm32/stm32butterfly2/configs/nsh/defconfig +++ /dev/null @@ -1,71 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_DISABLE_OS_API is not set -# CONFIG_MMCSD_MMCSUPPORT is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_DISABLE_LOSMART is not set -CONFIG_ADC=y -CONFIG_ANALOG=y -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32butterfly2" -CONFIG_ARCH_BOARD_STM32_BUTTERFLY2=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F107VC=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_ARM_TOOLCHAIN_BUILDROOT=y -CONFIG_BOARD_LOOPSPERMSEC=5483 -CONFIG_BUILTIN=y -CONFIG_EXAMPLES_ADC=y -CONFIG_EXAMPLES_ADC_SWTRIG=y -CONFIG_EXAMPLES_HIDKBD=y -CONFIG_EXAMPLES_HIDKBD_DEFPRIO=50 -CONFIG_EXAMPLES_HIDKBD_STACKSIZE=1024 -CONFIG_EXAMPLES_MOUNT=y -CONFIG_FAT_LCNAMES=y -CONFIG_FAT_LFN=y -CONFIG_FS_FAT=y -CONFIG_FS_PROCFS=y -CONFIG_FS_PROCFS_REGISTER=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LIBC_STRERROR=y -CONFIG_LIBC_STRERROR_SHORT=y -CONFIG_MMCSD=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_MOTD=y -CONFIG_NSH_MOTD_STRING="stm32butterfly2 welcoms you" -CONFIG_NSH_READLINE=y -CONFIG_NSH_STRERROR=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=65536 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_READLINE_TABCOMPLETION=y -CONFIG_RR_INTERVAL=100 -CONFIG_SCHED_CPULOAD_SYSCLK=y -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_HPWORKPRIORITY=192 -CONFIG_SCHED_HPWORKSTACKSIZE=1024 -CONFIG_START_YEAR=1970 -CONFIG_STM32_ADC1=y -CONFIG_STM32_JTAG_FULL_ENABLE=y -CONFIG_STM32_OTGFS=y -CONFIG_STM32_PWR=y -CONFIG_STM32_SPI1=y -CONFIG_STM32_USART2=y -CONFIG_STM32_USART2_REMAP=y -CONFIG_STM32_USBHOST=y -CONFIG_SYSLOG_TIMESTAMP=y -CONFIG_SYSTEM_NSH=y -CONFIG_SYSTEM_VI=y -CONFIG_TESTING_RAMTEST=y -CONFIG_USART2_SERIAL_CONSOLE=y -CONFIG_USBHOST_HIDKBD=y -CONFIG_USBHOST_MSC=y diff --git a/boards/arm/stm32/stm32butterfly2/configs/nshnet/defconfig b/boards/arm/stm32/stm32butterfly2/configs/nshnet/defconfig deleted file mode 100644 index 762efdfdce220..0000000000000 --- a/boards/arm/stm32/stm32butterfly2/configs/nshnet/defconfig +++ /dev/null @@ -1,90 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_DISABLE_OS_API is not set -# CONFIG_MMCSD_MMCSUPPORT is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_DISABLE_LOSMART is not set -# CONFIG_STM32_AUTONEG is not set -CONFIG_ADC=y -CONFIG_ANALOG=y -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32butterfly2" -CONFIG_ARCH_BOARD_STM32_BUTTERFLY2=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F107VC=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_ARM_TOOLCHAIN_BUILDROOT=y -CONFIG_BOARD_LOOPSPERMSEC=5483 -CONFIG_BUILTIN=y -CONFIG_ETH0_PHY_DP83848C=y -CONFIG_EXAMPLES_ADC=y -CONFIG_EXAMPLES_ADC_SWTRIG=y -CONFIG_EXAMPLES_MOUNT=y -CONFIG_EXAMPLES_USBSERIAL=y -CONFIG_FAT_LCNAMES=y -CONFIG_FAT_LFN=y -CONFIG_FS_FAT=y -CONFIG_FS_PROCFS=y -CONFIG_FS_PROCFS_REGISTER=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LIBC_HOSTNAME="butterfly2" -CONFIG_LIBC_STRERROR=y -CONFIG_LIBC_STRERROR_SHORT=y -CONFIG_MMCSD=y -CONFIG_NET=y -CONFIG_NETINIT_DRIPADDR=0x0a010101 -CONFIG_NETINIT_IPADDR=0x0a010163 -CONFIG_NETINIT_NOMAC=y -CONFIG_NET_ARP_IPIN=y -CONFIG_NET_ETH_PKTSIZE=1500 -CONFIG_NET_ICMP_SOCKET=y -CONFIG_NET_LOCAL=y -CONFIG_NET_TCP=y -CONFIG_NET_UDP=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_MOTD=y -CONFIG_NSH_MOTD_STRING="stm32butterfly2 welcoms you" -CONFIG_NSH_READLINE=y -CONFIG_NSH_STRERROR=y -CONFIG_PL2303=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=65536 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_READLINE_TABCOMPLETION=y -CONFIG_RR_INTERVAL=100 -CONFIG_SCHED_CPULOAD_SYSCLK=y -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_HPWORKPRIORITY=192 -CONFIG_SCHED_HPWORKSTACKSIZE=1024 -CONFIG_START_YEAR=1970 -CONFIG_STM32_ADC1=y -CONFIG_STM32_ETH100MBPS=y -CONFIG_STM32_ETHFD=y -CONFIG_STM32_ETHMAC=y -CONFIG_STM32_ETH_REMAP=y -CONFIG_STM32_JTAG_FULL_ENABLE=y -CONFIG_STM32_MII=y -CONFIG_STM32_MII_EXTCLK=y -CONFIG_STM32_OTGFS=y -CONFIG_STM32_PWR=y -CONFIG_STM32_SPI1=y -CONFIG_STM32_USART2=y -CONFIG_STM32_USART2_REMAP=y -CONFIG_SYSLOG_TIMESTAMP=y -CONFIG_SYSTEM_NSH=y -CONFIG_SYSTEM_PING=y -CONFIG_SYSTEM_VI=y -CONFIG_TESTING_RAMTEST=y -CONFIG_USART2_SERIAL_CONSOLE=y -CONFIG_USBDEV=y -CONFIG_USBDEV_BUSPOWERED=y -CONFIG_USBDEV_MAXPOWER=500 diff --git a/boards/arm/stm32/stm32butterfly2/configs/nshusbdev/defconfig b/boards/arm/stm32/stm32butterfly2/configs/nshusbdev/defconfig deleted file mode 100644 index 294531d34d641..0000000000000 --- a/boards/arm/stm32/stm32butterfly2/configs/nshusbdev/defconfig +++ /dev/null @@ -1,70 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_DISABLE_OS_API is not set -# CONFIG_MMCSD_MMCSUPPORT is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_DISABLE_LOSMART is not set -CONFIG_ADC=y -CONFIG_ANALOG=y -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32butterfly2" -CONFIG_ARCH_BOARD_STM32_BUTTERFLY2=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F107VC=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_ARM_TOOLCHAIN_BUILDROOT=y -CONFIG_BOARD_LOOPSPERMSEC=5483 -CONFIG_BUILTIN=y -CONFIG_EXAMPLES_ADC=y -CONFIG_EXAMPLES_ADC_SWTRIG=y -CONFIG_EXAMPLES_MOUNT=y -CONFIG_EXAMPLES_USBSERIAL=y -CONFIG_FAT_LCNAMES=y -CONFIG_FAT_LFN=y -CONFIG_FS_FAT=y -CONFIG_FS_PROCFS=y -CONFIG_FS_PROCFS_REGISTER=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LIBC_STRERROR=y -CONFIG_LIBC_STRERROR_SHORT=y -CONFIG_MMCSD=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_MOTD=y -CONFIG_NSH_MOTD_STRING="stm32butterfly2 welcoms you" -CONFIG_NSH_READLINE=y -CONFIG_NSH_STRERROR=y -CONFIG_PL2303=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=65536 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_READLINE_TABCOMPLETION=y -CONFIG_RR_INTERVAL=100 -CONFIG_SCHED_CPULOAD_SYSCLK=y -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_HPWORKPRIORITY=192 -CONFIG_SCHED_HPWORKSTACKSIZE=1024 -CONFIG_START_YEAR=1970 -CONFIG_STM32_ADC1=y -CONFIG_STM32_JTAG_FULL_ENABLE=y -CONFIG_STM32_OTGFS=y -CONFIG_STM32_PWR=y -CONFIG_STM32_SPI1=y -CONFIG_STM32_USART2=y -CONFIG_STM32_USART2_REMAP=y -CONFIG_SYSLOG_TIMESTAMP=y -CONFIG_SYSTEM_NSH=y -CONFIG_SYSTEM_VI=y -CONFIG_TESTING_RAMTEST=y -CONFIG_USART2_SERIAL_CONSOLE=y -CONFIG_USBDEV=y -CONFIG_USBDEV_BUSPOWERED=y -CONFIG_USBDEV_MAXPOWER=500 diff --git a/boards/arm/stm32/stm32butterfly2/configs/nshusbhost/defconfig b/boards/arm/stm32/stm32butterfly2/configs/nshusbhost/defconfig deleted file mode 100644 index 79655e199f1a4..0000000000000 --- a/boards/arm/stm32/stm32butterfly2/configs/nshusbhost/defconfig +++ /dev/null @@ -1,71 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_DISABLE_OS_API is not set -# CONFIG_MMCSD_MMCSUPPORT is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_DISABLE_LOSMART is not set -CONFIG_ADC=y -CONFIG_ANALOG=y -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32butterfly2" -CONFIG_ARCH_BOARD_STM32_BUTTERFLY2=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F107VC=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_ARM_TOOLCHAIN_BUILDROOT=y -CONFIG_BOARD_LOOPSPERMSEC=5483 -CONFIG_BUILTIN=y -CONFIG_EXAMPLES_ADC=y -CONFIG_EXAMPLES_ADC_SWTRIG=y -CONFIG_EXAMPLES_HIDKBD=y -CONFIG_EXAMPLES_HIDKBD_DEFPRIO=50 -CONFIG_EXAMPLES_HIDKBD_STACKSIZE=1024 -CONFIG_EXAMPLES_MOUNT=y -CONFIG_FAT_LCNAMES=y -CONFIG_FAT_LFN=y -CONFIG_FS_FAT=y -CONFIG_FS_PROCFS=y -CONFIG_FS_PROCFS_REGISTER=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LIBC_STRERROR=y -CONFIG_LIBC_STRERROR_SHORT=y -CONFIG_MMCSD=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_MOTD=y -CONFIG_NSH_MOTD_STRING="stm32butterfly2 welcoms you" -CONFIG_NSH_READLINE=y -CONFIG_NSH_STRERROR=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=65536 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_READLINE_TABCOMPLETION=y -CONFIG_RR_INTERVAL=100 -CONFIG_SCHED_CPULOAD_SYSCLK=y -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_HPWORKPRIORITY=192 -CONFIG_SCHED_HPWORKSTACKSIZE=1024 -CONFIG_START_YEAR=1970 -CONFIG_STM32_ADC1=y -CONFIG_STM32_JTAG_FULL_ENABLE=y -CONFIG_STM32_OTGFS=y -CONFIG_STM32_PWR=y -CONFIG_STM32_SPI1=y -CONFIG_STM32_USART2=y -CONFIG_STM32_USART2_REMAP=y -CONFIG_STM32_USBHOST=y -CONFIG_SYSLOG_TIMESTAMP=y -CONFIG_SYSTEM_NSH=y -CONFIG_SYSTEM_VI=y -CONFIG_TESTING_RAMTEST=y -CONFIG_USART2_SERIAL_CONSOLE=y -CONFIG_USBHOST_HIDKBD=y -CONFIG_USBHOST_MSC=y diff --git a/boards/arm/stm32/stm32butterfly2/include/board.h b/boards/arm/stm32/stm32butterfly2/include/board.h deleted file mode 100644 index 47811ad89f006..0000000000000 --- a/boards/arm/stm32/stm32butterfly2/include/board.h +++ /dev/null @@ -1,219 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32butterfly2/include/board.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __BOARDS_ARM_STM32_STM32_BUTTERFLY2_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32_STM32_BUTTERFLY2_INCLUDE_BOARD_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#ifndef __ASSEMBLY__ -# include -#endif - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Clocking *****************************************************************/ - -/* HSI - 8 MHz RC factory-trimmed - * LSI - 40 KHz RC (30-60KHz, uncalibrated) - * HSE - On-board crystal frequency is 14.7456MHz - * LSE - LSE is not connected - */ - -#define STM32_BOARD_XTAL 14745600ul - -#define STM32_HSI_FREQUENCY 8000000ul -#define STM32_LSI_FREQUENCY 40000u -#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL -#define STM32_LSE_FREQUENCY 0 - -/* PLL output is 71.8848MHz */ - -#define STM32_PLL_PREDIV2 RCC_CFGR2_PREDIV2d4 -#define STM32_PLL_PLL2MUL RCC_CFGR2_PLL2MULx12 -#define STM32_PLL_PREDIV1 RCC_CFGR2_PREDIV1d4 -#define STM32_PLL_PLLMUL RCC_CFGR_PLLMUL_CLKx65 -#define STM32_PLL_FREQUENCY 71884800ul - -/* SYSCLK and HCLK adre the PLL frequency */ - -#define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY -#define STM32_HCLK_FREQUENCY STM32_PLL_FREQUENCY - -/* USB clock output is 47.9232MHz */ - -#define STM32_CFGR_OTGFSPRE RCC_CFGR_OTGFSPREd3 - -/* APB2 clock (PCLK2) is HCLK */ - -#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK -#define STM32_PCLK2_FREQUENCY STM32_HCLK_FREQUENCY -#define STM32_APB2_CLKIN STM32_PCLK2_FREQUENCY - -#define STM32APB_TIM1_CLKIN STM32_PCLK2_FREQUENCY - -/* APB1 clock (PCLK1) is HCLK/2 (35.9424MHz) */ - -#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd2 -#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/2) - -#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) - -/* LED definitions **********************************************************/ - -/* There are four LEDs on stm32butterfly2 board that can be controlled by - * software. - * All pulled high and van be illuminated by driving the output low. - * - * LED1 PB0 - * LED2 PB1 - * LED3 PC4 - * LED4 PC5 - */ - -/* LED index values for use with board_userled() */ - -#define BOARD_LED1 0 -#define BOARD_LED2 1 -#define BOARD_LED3 2 -#define BOARD_LED4 3 -#define BOARD_NLEDS 4 - -/* LED bits for use with board_userled_all() */ - -#define BOARD_LED1_BIT (1 << BOARD_LED1) -#define BOARD_LED2_BIT (1 << BOARD_LED2) -#define BOARD_LED3_BIT (1 << BOARD_LED3) -#define BOARD_LED4_BIT (1 << BOARD_LED4) - -/* These LEDs are not used by the board port unless CONFIG_ARCH_LEDS is - * defined. In thath case, the usage by the board port is defined in - * include/board.h and src/stm32_leds.c. The LEDs are used to encode - * OS-related events as follows: - * - * SYMBOL Val Meaning LED state - * LED1 LED2 LED3 LED4 - * ----------------- --- ----------------------- ---- ---- ---- ---- - */ - -#define LED_STARTED 0 /* NuttX has been started ON OFF OFF OFF */ -#define LED_HEAPALLOCATE 1 /* Heap has been allocated OFF ON OFF OFF */ -#define LED_IRQSENABLED 2 /* Interrupts enabled OFF OFF ON OFF */ -#define LED_STACKCREATED 3 /* Idle stack created OFF OFF OFF ON */ -#define LED_INIRQ 5 /* In an interrupt N/C N/C N/C GLOW */ -#define LED_SIGNAL 6 /* In a signal handler N/C N/C N/C GLOW */ -#define LED_ASSERTION 7 /* An assertion failed N/C N/C N/C GLOW */ -#define LED_PANIC 8 /* The system has crashed N/C N/C N/C FLASH */ -#undef LED_IDLE /* MCU is in sleep mode Not used */ - -/* After booting, LED1-3 are not longer used by the system and can be used - * for other purposes by the application (Of course, all LEDs are available - * to the application if CONFIG_ARCH_LEDS is not defined. - */ - -/* ADC configuration. Right now only ADC12_IN10 is supported - * (potentiometer) - */ - -#ifdef CONFIG_STM32_ADC2 -# error "CONFIG_STM32_ADC2 is not supported" -#endif - -/* SPI configuration. Only SPI1 is supported */ - -#ifdef CONFIG_STM32_SPI2 -# error "CONFIG_STM32_SPI2 is not supported" -#endif - -/* Alternate function pin selections (auto-aliased for new pinmap) */ - -/* USART2 */ - -#define GPIO_USART2_TX GPIO_ADJUST_MODE(GPIO_USART2_TX_0, GPIO_MODE_50MHz) -#define GPIO_USART2_RX GPIO_USART2_RX_0 -#define GPIO_USART2_CTS GPIO_USART2_CTS_0 -#define GPIO_USART2_RTS GPIO_ADJUST_MODE(GPIO_USART2_RTS_0, GPIO_MODE_50MHz) -#define GPIO_USART2_CK GPIO_ADJUST_MODE(GPIO_USART2_CK_0, GPIO_MODE_50MHz) - -/* SPI1 */ - -#define GPIO_SPI1_NSS GPIO_ADJUST_MODE(GPIO_SPI1_NSS_0, GPIO_MODE_50MHz) -#define GPIO_SPI1_SCK GPIO_ADJUST_MODE(GPIO_SPI1_SCK_0, GPIO_MODE_50MHz) -#define GPIO_SPI1_MISO GPIO_ADJUST_MODE(GPIO_SPI1_MISO_0, GPIO_MODE_50MHz) -#define GPIO_SPI1_MOSI GPIO_ADJUST_MODE(GPIO_SPI1_MOSI_0, GPIO_MODE_50MHz) - -/* USB */ - -#define GPIO_USB_DM GPIO_USB_DM_0 -#define GPIO_USB_DP GPIO_USB_DP_0 - -/* MCO */ - -#define GPIO_MCO GPIO_ADJUST_MODE(GPIO_MCO_0, GPIO_MODE_50MHz) - -/* Ethernet (MII/RMII) */ - -#define GPIO_ETH_MDC GPIO_ADJUST_MODE(GPIO_ETH_MDC_0, GPIO_MODE_50MHz) -#define GPIO_ETH_MDIO GPIO_ADJUST_MODE(GPIO_ETH_MDIO_0, GPIO_MODE_50MHz) -#define GPIO_ETH_MII_COL GPIO_ETH_MII_COL_0 -#define GPIO_ETH_MII_CRS GPIO_ETH_MII_CRS_0 -#define GPIO_ETH_MII_RX_CLK GPIO_ETH_MII_RX_CLK_0 -#define GPIO_ETH_MII_RXD0 GPIO_ETH_MII_RXD0_0 -#define GPIO_ETH_MII_RXD1 GPIO_ETH_MII_RXD1_0 -#define GPIO_ETH_MII_RXD2 GPIO_ETH_MII_RXD2_0 -#define GPIO_ETH_MII_RXD3 GPIO_ETH_MII_RXD3_0 -#define GPIO_ETH_MII_RX_DV GPIO_ETH_MII_RX_DV_0 -#define GPIO_ETH_MII_RX_ER GPIO_ETH_MII_RX_ER_0 -#define GPIO_ETH_MII_TX_CLK GPIO_ETH_MII_TX_CLK_0 -#define GPIO_ETH_MII_TXD0 GPIO_ADJUST_MODE(GPIO_ETH_MII_TXD0_0, GPIO_MODE_50MHz) -#define GPIO_ETH_MII_TXD1 GPIO_ADJUST_MODE(GPIO_ETH_MII_TXD1_0, GPIO_MODE_50MHz) -#define GPIO_ETH_MII_TXD2 GPIO_ADJUST_MODE(GPIO_ETH_MII_TXD2_0, GPIO_MODE_50MHz) -#define GPIO_ETH_MII_TXD3 GPIO_ADJUST_MODE(GPIO_ETH_MII_TXD3_0, GPIO_MODE_50MHz) -#define GPIO_ETH_MII_TX_EN GPIO_ADJUST_MODE(GPIO_ETH_MII_TX_EN_0, GPIO_MODE_50MHz) -#define GPIO_ETH_RMII_CRS_DV GPIO_ETH_RMII_CRS_DV_0 -#define GPIO_ETH_RMII_REF_CLK GPIO_ETH_RMII_REF_CLK_0 -#define GPIO_ETH_RMII_RXD0 GPIO_ETH_RMII_RXD0_0 -#define GPIO_ETH_RMII_RXD1 GPIO_ETH_RMII_RXD1_0 -#define GPIO_ETH_RMII_TXD0 GPIO_ADJUST_MODE(GPIO_ETH_RMII_TXD0_0, GPIO_MODE_50MHz) -#define GPIO_ETH_RMII_TXD1 GPIO_ADJUST_MODE(GPIO_ETH_RMII_TXD1_0, GPIO_MODE_50MHz) -#define GPIO_ETH_RMII_TX_EN GPIO_ADJUST_MODE(GPIO_ETH_RMII_TX_EN_0, GPIO_MODE_50MHz) - -/* USB OTG FS */ - -#define GPIO_OTGFS_DM GPIO_ADJUST_MODE(GPIO_OTGFS_DM_0, GPIO_MODE_50MHz) -#define GPIO_OTGFS_DP GPIO_ADJUST_MODE(GPIO_OTGFS_DP_0, GPIO_MODE_50MHz) -#define GPIO_OTGFS_ID GPIO_ADJUST_MODE(GPIO_OTGFS_ID_0, GPIO_MODE_50MHz) -#define GPIO_OTGFS_SOF GPIO_ADJUST_MODE(GPIO_OTGFS_SOF_0, GPIO_MODE_50MHz) -#define GPIO_OTGFS_VBUS GPIO_OTGFS_VBUS_0 - -#endif /* __BOARDS_ARM_STM32_STM32_BUTTERFLY2_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32/stm32butterfly2/scripts/Make.defs b/boards/arm/stm32/stm32butterfly2/scripts/Make.defs deleted file mode 100644 index 8fe66cdd72fe3..0000000000000 --- a/boards/arm/stm32/stm32butterfly2/scripts/Make.defs +++ /dev/null @@ -1,46 +0,0 @@ -############################################################################ -# boards/arm/stm32/stm32butterfly2/scripts/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/.config -include $(TOPDIR)/tools/Config.mk -include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs - -ifeq ($(CONFIG_STM32_DFU),y) - LDSCRIPT = dfu.ld -else - LDSCRIPT = flash.ld -endif - -ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) - -ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 - -CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) -CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) -CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -AFLAGS := $(CFLAGS) -D__ASSEMBLY__ - -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-gotoff.ld -no-check-sections -LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32/stm32butterfly2/scripts/dfu.ld b/boards/arm/stm32/stm32butterfly2/scripts/dfu.ld deleted file mode 100644 index 5901e67a90948..0000000000000 --- a/boards/arm/stm32/stm32butterfly2/scripts/dfu.ld +++ /dev/null @@ -1,118 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32butterfly2/scripts/dfu.ld - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -MEMORY -{ - flash (rx) : ORIGIN = 0x08003000, LENGTH = 208K - sram (rwx) : ORIGIN = 0x20000000, LENGTH = 64K -} - -OUTPUT_ARCH(arm) -EXTERN(_vectors) -ENTRY(_stext) -SECTIONS -{ - .text : { - _stext = ABSOLUTE(.); - *(.vectors) - *(.text .text.*) - *(.fixup) - *(.gnu.warning) - *(.rodata .rodata.*) - *(.gnu.linkonce.t.*) - *(.glue_7) - *(.glue_7t) - *(.got) - *(.gcc_except_table) - *(.gnu.linkonce.r.*) - _etext = ABSOLUTE(.); - } > flash - - .init_section : { - _sinit = ABSOLUTE(.); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) - KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) - _einit = ABSOLUTE(.); - } > flash - - .ARM.extab : { - *(.ARM.extab*) - } > flash - - __exidx_start = ABSOLUTE(.); - .ARM.exidx : { - *(.ARM.exidx*) - } > flash - __exidx_end = ABSOLUTE(.); - - .tdata : { - _stdata = ABSOLUTE(.); - *(.tdata .tdata.* .gnu.linkonce.td.*); - _etdata = ABSOLUTE(.); - } > flash - - .tbss : { - _stbss = ABSOLUTE(.); - *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); - _etbss = ABSOLUTE(.); - } > flash - - _eronly = ABSOLUTE(.); - - /* The RAM vector table (if present) should lie at the beginning of SRAM */ - - .ram_vectors : { - *(.ram_vectors) - } > sram - - .data : { - _sdata = ABSOLUTE(.); - *(.data .data.*) - *(.gnu.linkonce.d.*) - CONSTRUCTORS - . = ALIGN(4); - _edata = ABSOLUTE(.); - } > sram AT > flash - - .bss : { - _sbss = ABSOLUTE(.); - *(.bss .bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - . = ALIGN(8); - _ebss = ABSOLUTE(.); - } > sram - - /* Stabs debugging sections. */ - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_info 0 : { *(.debug_info) } - .debug_line 0 : { *(.debug_line) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_aranges 0 : { *(.debug_aranges) } -} diff --git a/boards/arm/stm32/stm32butterfly2/scripts/flash.ld b/boards/arm/stm32/stm32butterfly2/scripts/flash.ld deleted file mode 100644 index 57edf7919bc13..0000000000000 --- a/boards/arm/stm32/stm32butterfly2/scripts/flash.ld +++ /dev/null @@ -1,118 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32butterfly2/scripts/flash.ld - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -MEMORY -{ - flash (rx) : ORIGIN = 0x08000000, LENGTH = 256K - sram (rwx) : ORIGIN = 0x20000000, LENGTH = 64K -} - -OUTPUT_ARCH(arm) -EXTERN(_vectors) -ENTRY(_stext) -SECTIONS -{ - .text : { - _stext = ABSOLUTE(.); - *(.vectors) - *(.text .text.*) - *(.fixup) - *(.gnu.warning) - *(.rodata .rodata.*) - *(.gnu.linkonce.t.*) - *(.glue_7) - *(.glue_7t) - *(.got) - *(.gcc_except_table) - *(.gnu.linkonce.r.*) - _etext = ABSOLUTE(.); - } > flash - - .init_section : { - _sinit = ABSOLUTE(.); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) - KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) - _einit = ABSOLUTE(.); - } > flash - - .ARM.extab : { - *(.ARM.extab*) - } > flash - - __exidx_start = ABSOLUTE(.); - .ARM.exidx : { - *(.ARM.exidx*) - } > flash - __exidx_end = ABSOLUTE(.); - - .tdata : { - _stdata = ABSOLUTE(.); - *(.tdata .tdata.* .gnu.linkonce.td.*); - _etdata = ABSOLUTE(.); - } > flash - - .tbss : { - _stbss = ABSOLUTE(.); - *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); - _etbss = ABSOLUTE(.); - } > flash - - _eronly = ABSOLUTE(.); - - /* The RAM vector table (if present) should lie at the beginning of SRAM */ - - .ram_vectors : { - *(.ram_vectors) - } > sram - - .data : { - _sdata = ABSOLUTE(.); - *(.data .data.*) - *(.gnu.linkonce.d.*) - CONSTRUCTORS - . = ALIGN(4); - _edata = ABSOLUTE(.); - } > sram AT > flash - - .bss : { - _sbss = ABSOLUTE(.); - *(.bss .bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - . = ALIGN(8); - _ebss = ABSOLUTE(.); - } > sram - - /* Stabs debugging sections. */ - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_info 0 : { *(.debug_info) } - .debug_line 0 : { *(.debug_line) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_aranges 0 : { *(.debug_aranges) } -} diff --git a/boards/arm/stm32/stm32butterfly2/src/CMakeLists.txt b/boards/arm/stm32/stm32butterfly2/src/CMakeLists.txt deleted file mode 100644 index 6e3faeea1a225..0000000000000 --- a/boards/arm/stm32/stm32butterfly2/src/CMakeLists.txt +++ /dev/null @@ -1,55 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/stm32butterfly2/src/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -set(SRCS stm32_boot.c stm32_leds.c) - -if(CONFIG_STM32_ADC) - list(APPEND SRCS stm32_adc.c) -endif() - -if(CONFIG_STM32_SPI1) - list(APPEND SRCS stm32_spi.c) -endif() - -if(CONFIG_STM32_OTGFS) - list(APPEND SRCS stm32_usb.c) -endif() - -if(CONFIG_STM32_USBHOST) - list(APPEND SRCS stm32_usbhost.c) -endif() - -if(CONFIG_USBDEV) - list(APPEND SRCS stm32_usbdev.c) -endif() - -if(CONFIG_MMCSD) - list(APPEND SRCS stm32_mmcsd.c) -endif() - -if(CONFIG_ARCH_BUTTONS) - list(APPEND SRCS stm32_buttons.c) -endif() - -target_sources(board PRIVATE ${SRCS}) - -set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/flash.ld") diff --git a/boards/arm/stm32/stm32butterfly2/src/Make.defs b/boards/arm/stm32/stm32butterfly2/src/Make.defs deleted file mode 100644 index 04fda674517e8..0000000000000 --- a/boards/arm/stm32/stm32butterfly2/src/Make.defs +++ /dev/null @@ -1,57 +0,0 @@ -############################################################################ -# boards/arm/stm32/stm32butterfly2/src/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/Make.defs - -CSRCS = stm32_boot.c stm32_leds.c - -ifeq ($(CONFIG_STM32_ADC),y) -CSRCS += stm32_adc.c -endif - -ifeq ($(CONFIG_STM32_SPI1),y) -CSRCS += stm32_spi.c -endif - -ifeq ($(CONFIG_STM32_OTGFS),y) -CSRCS += stm32_usb.c -endif - -ifeq ($(CONFIG_STM32_USBHOST),y) -CSRCS += stm32_usbhost.c -endif - -ifeq ($(CONFIG_USBDEV),y) -CSRCS += stm32_usbdev.c -endif - -ifeq ($(CONFIG_MMCSD),y) -CSRCS += stm32_mmcsd.c -endif - -ifeq ($(CONFIG_ARCH_BUTTONS),y) -CSRCS += stm32_buttons.c -endif - -DEPPATH += --dep-path board -VPATH += :board -CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/stm32butterfly2/src/stm32_adc.c b/boards/arm/stm32/stm32butterfly2/src/stm32_adc.c deleted file mode 100644 index 1c15f9556a900..0000000000000 --- a/boards/arm/stm32/stm32butterfly2/src/stm32_adc.c +++ /dev/null @@ -1,78 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32butterfly2/src/stm32_adc.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include - -#include "chip.h" -#include "stm32_adc.h" - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_adc_setup - * - * Description: - * Initialize ADC and register the ADC driver. - * - ****************************************************************************/ - -int stm32_adc_setup(void) -{ - static bool initialized = false; - uint8_t channel[1] = - { - 10 - }; - - struct adc_dev_s *adc; - int rv; - - if (initialized) - { - return OK; - } - - ainfo("INFO: Initializing ADC12_IN10\n"); - stm32_configgpio(GPIO_ADC12_IN10_0); - if ((adc = stm32_adcinitialize(1, channel, 1)) == NULL) - { - aerr("ERROR: Failed to get adc interface\n"); - return -ENODEV; - } - - if ((rv = adc_register("/dev/adc0", adc)) < 0) - { - aerr("ERROR: adc_register failed: %d\n", rv); - return rv; - } - - initialized = true; - ainfo("INFO: ADC12_IN10 initialized successfully\n"); - return OK; -} diff --git a/boards/arm/stm32/stm32butterfly2/src/stm32_boot.c b/boards/arm/stm32/stm32butterfly2/src/stm32_boot.c deleted file mode 100644 index de6bf256cf4de..0000000000000 --- a/boards/arm/stm32/stm32butterfly2/src/stm32_boot.c +++ /dev/null @@ -1,100 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32butterfly2/src/stm32_boot.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include -#include - -#include "stm32_butterfly2.h" - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_boardinitialize - * - * Description: - * Initializes low level pins for the drivers. - ****************************************************************************/ - -void stm32_boardinitialize(void) -{ - stm32_led_initialize(); - stm32_spidev_initialize(); - stm32_usb_initialize(); -} - -/**************************************************************************** - * Name: board_late_initialize - * - * Description: - * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional - * initialization call will be performed in the boot-up sequence to a - * function called board_late_initialize(). board_late_initialize() will - * be called immediately after up_initialize() is called and just before - * the initial application is started. This additional initialization - * phase may be used, for example, to initialize board-specific device - * drivers. - * - ****************************************************************************/ - -#ifdef CONFIG_BOARD_LATE_INITIALIZE -void board_late_initialize(void) -{ - int ret = 0; - -#ifdef CONFIG_MMCSD - ret = stm32_mmcsd_initialize(CONFIG_NSH_MMCSDMINOR); - if (ret < 0) - { - syslog(LOG_ERR, "Failed to initialize SD slot: %d\n", ret); - return; - } -#endif - -#ifdef CONFIG_USBHOST - ret = stm32_usbhost_initialize(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: Failed to initialize USB host: %d\n", ret); - return; - } -#endif - -#ifdef CONFIG_ADC - /* Initialize ADC and register the ADC driver. */ - - ret = stm32_adc_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_adc_setup failed: %d\n", ret); - } -#endif - - UNUSED(ret); -} -#endif diff --git a/boards/arm/stm32/stm32butterfly2/src/stm32_buttons.c b/boards/arm/stm32/stm32butterfly2/src/stm32_buttons.c deleted file mode 100644 index 9de138b47b015..0000000000000 --- a/boards/arm/stm32/stm32butterfly2/src/stm32_buttons.c +++ /dev/null @@ -1,99 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32butterfly2/src/stm32_buttons.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include "stm32_gpio.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#define NUM_BUTTONS 5 - -#define GPIO_JOY_O (GPIO_INPUT | GPIO_CNF_INFLOAT | GPIO_MODE_INPUT |\ - GPIO_PORTC | GPIO_PIN7) -#define GPIO_JOY_U (GPIO_INPUT | GPIO_CNF_INFLOAT | GPIO_MODE_INPUT |\ - GPIO_PORTC | GPIO_PIN8) -#define GPIO_JOY_D (GPIO_INPUT | GPIO_CNF_INFLOAT | GPIO_MODE_INPUT |\ - GPIO_PORTC | GPIO_PIN9) -#define GPIO_JOY_R (GPIO_INPUT | GPIO_CNF_INFLOAT | GPIO_MODE_INPUT |\ - GPIO_PORTC | GPIO_PIN10) -#define GPIO_JOY_L (GPIO_INPUT | GPIO_CNF_INFLOAT | GPIO_MODE_INPUT |\ - GPIO_PORTC | GPIO_PIN11) - -/**************************************************************************** - * Private Declarations - ****************************************************************************/ - -static const uint32_t buttons[NUM_BUTTONS] = -{ - GPIO_JOY_O, GPIO_JOY_U, GPIO_JOY_D, GPIO_JOY_R, GPIO_JOY_L -}; - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_button_initialize - * - * Description: - * Initializes gpio pins for joystick buttons - ****************************************************************************/ - -uint32_t board_button_initialize(void) -{ - int i; - - for (i = 0; i != NUM_BUTTONS; ++i) - { - stm32_configgpio(buttons[i]); - } - - return NUM_BUTTONS; -} - -/**************************************************************************** - * Name: board_buttons - * - * Description: - * Reads keys - ****************************************************************************/ - -uint32_t board_buttons(void) -{ - uint32_t rv = 0; - int i; - - for (i = 0; i != NUM_BUTTONS; ++i) - { - if (stm32_gpioread(buttons[i]) == 0) - { - rv |= 1 << i; - } - } - - return rv; -} diff --git a/boards/arm/stm32/stm32butterfly2/src/stm32_leds.c b/boards/arm/stm32/stm32butterfly2/src/stm32_leds.c deleted file mode 100644 index c2d1d4b4f2682..0000000000000 --- a/boards/arm/stm32/stm32butterfly2/src/stm32_leds.c +++ /dev/null @@ -1,257 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32butterfly2/src/stm32_leds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include -#include -#include -#include - -#include "stm32_gpio.h" - -/**************************************************************************** - * Pre-processor definitions - ****************************************************************************/ - -#define GPIO_LED1 (GPIO_OUTPUT | GPIO_CNF_OUTPP | GPIO_MODE_50MHz |\ - GPIO_OUTPUT_SET | GPIO_PORTB | GPIO_PIN0) -#define GPIO_LED2 (GPIO_OUTPUT | GPIO_CNF_OUTPP | GPIO_MODE_50MHz |\ - GPIO_OUTPUT_SET | GPIO_PORTB | GPIO_PIN1) -#define GPIO_LED3 (GPIO_OUTPUT | GPIO_CNF_OUTPP | GPIO_MODE_50MHz |\ - GPIO_OUTPUT_SET | GPIO_PORTC | GPIO_PIN4) -#define GPIO_LED4 (GPIO_OUTPUT | GPIO_CNF_OUTPP | GPIO_MODE_50MHz |\ - GPIO_OUTPUT_SET | GPIO_PORTC | GPIO_PIN5) - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/* Identifies led state */ - -enum led_state -{ - LED_ON = false, - LED_OFF = true -}; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: led_state - * - * Description: - * Sets pack of leds to given state - ****************************************************************************/ - -static void led_state(enum led_state state, unsigned int leds) -{ - if (leds & BOARD_LED1_BIT) - { - stm32_gpiowrite(GPIO_LED1, state); - } - - if (leds & BOARD_LED2_BIT) - { - stm32_gpiowrite(GPIO_LED2, state); - } - - if (leds & BOARD_LED3_BIT) - { - stm32_gpiowrite(GPIO_LED3, state); - } - - if (leds & BOARD_LED4_BIT) - { - stm32_gpiowrite(GPIO_LED4, state); - } -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_led_initialize - * - * Description: - * Initializes low level gpio pins for board LEDS - ****************************************************************************/ - -void stm32_led_initialize(void) -{ - stm32_configgpio(GPIO_LED1); - stm32_configgpio(GPIO_LED2); - stm32_configgpio(GPIO_LED3); - stm32_configgpio(GPIO_LED4); -} - -#ifdef CONFIG_ARCH_LEDS - -/**************************************************************************** - * Name: board_autoled_on - * - * Description: - * Drives board leds when specific RTOS state led occurs. - * - * Input Parameters: - * led - This is actually RTOS state not led number of anything like that - ****************************************************************************/ - -void board_autoled_on(int led) -{ - switch (led) - { - case LED_STARTED: - led_state(LED_OFF, BOARD_LED2_BIT | BOARD_LED3_BIT | BOARD_LED4_BIT); - led_state(LED_ON, BOARD_LED1_BIT); - break; - - case LED_HEAPALLOCATE: - led_state(LED_OFF, BOARD_LED1_BIT | BOARD_LED3_BIT | BOARD_LED4_BIT); - led_state(LED_ON, BOARD_LED2_BIT); - break; - - case LED_IRQSENABLED: - led_state(LED_OFF, BOARD_LED1_BIT | BOARD_LED2_BIT | BOARD_LED4_BIT); - led_state(LED_ON, BOARD_LED3_BIT); - break; - - case LED_STACKCREATED: - led_state(LED_OFF, BOARD_LED1_BIT | BOARD_LED2_BIT | BOARD_LED3_BIT); - led_state(LED_ON, BOARD_LED4_BIT); - break; - - case LED_INIRQ: - case LED_SIGNAL: - case LED_ASSERTION: - case LED_PANIC: - led_state(LED_ON, BOARD_LED4_BIT); - break; - } -} - -/**************************************************************************** - * Name: board_autoled_off - * - * Description: - * Drives board leds when specific RTOS state led ends - * - * Input Parameters: - * led - This is actually RTOS state not led number of anything like that - ****************************************************************************/ - -void board_autoled_off(int led) -{ - switch (led) - { - case LED_STARTED: - led_state(LED_OFF, BOARD_LED1_BIT); - break; - - case LED_HEAPALLOCATE: - led_state(LED_OFF, BOARD_LED2_BIT); - break; - - case LED_IRQSENABLED: - led_state(LED_OFF, BOARD_LED3_BIT); - break; - - case LED_STACKCREATED: - case LED_INIRQ: - case LED_SIGNAL: - case LED_ASSERTION: - case LED_PANIC: - led_state(LED_OFF, BOARD_LED4_BIT); - break; - } -} -#endif - -/**************************************************************************** - * Name: board_userled_initialize - * - * Description: - * This function should initialize leds for user use, but on RTOS start we - * initialize every led for use by RTOS and at end, when RTOS is fully - * booted up, we give control of these specific leds for user. So that's - * why this function is empty. - ****************************************************************************/ - -uint32_t board_userled_initialize(void) -{ - /* Already initialized by stm32_led_initialize. */ - - return BOARD_NLEDS; -} - -/**************************************************************************** - * Name: board_userled - * - * Description: - * Sets led to ledon state. - * - * Input Parameters: - * led - Led to be set, indexed from 0 - * ledon - new state for the led. - ****************************************************************************/ - -void board_userled(int led, bool ledon) -{ - unsigned int ledbit; - -#ifndef CONFIG_ARCH_LEDS - if (led == BOARD_LED4) - { - return; - } -#endif - - ledbit = 1 << led; - led_state(ledon, ledbit); -} - -/**************************************************************************** - * Name: board_userled_all - * - * Description: - * Sets whole ledset to given state. - * - * Input Parameters: - * ledset - Led bits to be set on or off - ****************************************************************************/ - -void board_userled_all(uint32_t ledset) -{ -#ifdef CONFIG_ARCH_LEDS - led_state(LED_ON, ledset & ~BOARD_LED4_BIT); - led_state(LED_OFF, ~(ledset | BOARD_LED4_BIT)); -#else - led_state(LED_ON, ledset); - led_state(LED_OFF, ~ledset); -#endif -} diff --git a/boards/arm/stm32/stm32butterfly2/src/stm32_mmcsd.c b/boards/arm/stm32/stm32butterfly2/src/stm32_mmcsd.c deleted file mode 100644 index 50b5bc9ea60a5..0000000000000 --- a/boards/arm/stm32/stm32butterfly2/src/stm32_mmcsd.c +++ /dev/null @@ -1,203 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32butterfly2/src/stm32_mmcsd.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -#include "stm32.h" -#include "stm32_butterfly2.h" -#include "stm32_spi.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#ifndef CONFIG_STM32_SPI1 -# error "SD driver requires CONFIG_STM32_SPI1 to be enabled" -#endif - -#ifdef CONFIG_DISABLE_MOUNTPOINT -# error "SD driver requires CONFIG_DISABLE_MOUNTPOINT to be disabled" -#endif - -/**************************************************************************** - * Private Definitions - ****************************************************************************/ - -static const int SD_SPI_PORT = 1; /* SD is connected to SPI1 port */ -static const int SD_SLOT_NO = 0; /* There is only one SD slot */ - -/* Media changed callback */ - -static spi_mediachange_t g_chmediaclbk; - -/* Argument for media changed callback */ - -static void *g_chmediaarg; - -/* Semafor to inform stm32_cd_thread that card was inserted or pulled out */ - -static sem_t g_cdsem = SEM_INITIALIZER(0); - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_cd_thread - * - * Description: - * Working thread to call mediachanged function when card is inserted or - * pulled out. - ****************************************************************************/ - -static void *stm32_cd_thread(void *arg) -{ - spiinfo("INFO: Running card detect thread\n"); - while (1) - { - nxsem_wait(&g_cdsem); - spiinfo("INFO: Card has been inserted, initializing\n"); - - if (g_chmediaclbk) - { - /* Card doesn't seem to initialize properly without letting it to - * rest for a millisecond or so. - */ - - nxsched_usleep(1 * 1000); - g_chmediaclbk(g_chmediaarg); - } - } - - return NULL; -} - -/**************************************************************************** - * Name: stm32_cd - * - * Description: - * Card detect interrupt handler. - ****************************************************************************/ - -static int stm32_cd(int irq, void *context, void *arg) -{ - static const int debounce_time = 100; /* [ms] */ - static uint32_t now = 0; - static uint32_t prev = 0; - struct timespec tp; - - clock_systime_timespec(&tp); - now = tp.tv_sec * 1000 + tp.tv_nsec / 1000000; - - /* When inserting card, card detect plate might bounce causing this - * interrupt to be called many time on single card insert/deinsert. Thus - * we are allowing only one interrupt every 100ms. - */ - - if (now - debounce_time > prev) - { - prev = now; - nxsem_post(&g_cdsem); - } - - return OK; -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_spi1register - * - * Description: - * Registers media change callback - ****************************************************************************/ - -int stm32_spi1register(struct spi_dev_s *dev, spi_mediachange_t callback, - void *arg) -{ - spiinfo("INFO: Registering spi1 device\n"); - g_chmediaclbk = callback; - g_chmediaarg = arg; - return OK; -} - -/**************************************************************************** - * Name: stm32_mmcsd_initialize - * - * Description: - * Initialize SPI-based SD card and card detect thread. - ****************************************************************************/ - -int stm32_mmcsd_initialize(int minor) -{ - struct spi_dev_s *spi; - struct sched_param schparam; - pthread_attr_t pattr; - int rv; - - spiinfo("INFO: Initializing mmcsd card\n"); - if ((spi = stm32_spibus_initialize(SD_SPI_PORT)) == NULL) - { - ferr("failed to initialize SPI port %d\n", SD_SPI_PORT); - return -ENODEV; - } - - if ((rv = mmcsd_spislotinitialize(minor, SD_SLOT_NO, spi)) < 0) - { - ferr("failed to bind SPI port %d to SD slot %d\n", SD_SPI_PORT, - SD_SLOT_NO); - return rv; - } - - stm32_gpiosetevent(GPIO_SD_CD, true, true, true, stm32_cd, NULL); - - pthread_attr_init(&pattr); -#ifdef CONFIG_DEBUG_FS - pthread_attr_setstacksize(&pattr, 1024); -#else - pthread_attr_setstacksize(&pattr, 256); -#endif - - schparam.sched_priority = 50; - pthread_attr_setschedparam(&pattr, &schparam); - pthread_create(NULL, &pattr, stm32_cd_thread, NULL); - - spiinfo("INFO: mmcsd card has been initialized successfully\n"); - return OK; -} diff --git a/boards/arm/stm32/stm32butterfly2/src/stm32_spi.c b/boards/arm/stm32/stm32butterfly2/src/stm32_spi.c deleted file mode 100644 index 9044b910a783a..0000000000000 --- a/boards/arm/stm32/stm32butterfly2/src/stm32_spi.c +++ /dev/null @@ -1,98 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32butterfly2/src/stm32_spi.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include "stm32_butterfly2.h" -#include "stm32_gpio.h" -#include "stm32_spi.h" - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_spidev_initialize - * - * Description: - * Called to configure SPI chip select GPIO pins. - * - * Note: - * Here only CS pins are configured as SPI pins are configured by driver - * itself. - ****************************************************************************/ - -void stm32_spidev_initialize(void) -{ - spiinfo("INFO: Initializing spi gpio pins\n"); - - stm32_configgpio(GPIO_SD_CS); - stm32_configgpio(GPIO_SD_CD); -} - -/**************************************************************************** - * Name: stm32_spi1select - * - * Description: - * Function asserts given devid based on select - ****************************************************************************/ - -void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, - bool select) -{ - spiinfo("INFO: Selecting spi dev: %" PRId32 ", state: %d\n", - devid, select); - - if (devid == SPIDEV_MMCSD(0)) - { - stm32_gpiowrite(GPIO_SD_CS, !select); - } -} - -/**************************************************************************** - * Name: stm32_spi1status - * - * Description: - * Return status of devid - ****************************************************************************/ - -uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) -{ - spiinfo("INFO: Requesting info from spi dev: %" PRId32 "\n", devid); - - if (devid == SPIDEV_MMCSD(0)) - { - if (stm32_gpioread(GPIO_SD_CD) == 0) - { - return SPI_STATUS_PRESENT; - } - } - - return 0; -} diff --git a/boards/arm/stm32/stm32butterfly2/src/stm32_usb.c b/boards/arm/stm32/stm32butterfly2/src/stm32_usb.c deleted file mode 100644 index 56ebf480d7491..0000000000000 --- a/boards/arm/stm32/stm32butterfly2/src/stm32_usb.c +++ /dev/null @@ -1,51 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32butterfly2/src/stm32_usb.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "stm32_gpio.h" - -#include -#include "stm32_butterfly2.h" - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_usb_initialize - * - * Description: - * Initializes USB pins - ****************************************************************************/ - -void stm32_usb_initialize(void) -{ - uinfo("INFO: Initializing usb otgfs gpio pins\n"); - - stm32_configgpio(GPIO_OTGFS_VBUS); - stm32_configgpio(GPIO_OTGFS_PWRON); -} diff --git a/boards/arm/stm32/stm32butterfly2/src/stm32_usbdev.c b/boards/arm/stm32/stm32butterfly2/src/stm32_usbdev.c deleted file mode 100644 index 8bdb6fce116c9..0000000000000 --- a/boards/arm/stm32/stm32butterfly2/src/stm32_usbdev.c +++ /dev/null @@ -1,65 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32butterfly2/src/stm32_usbdev.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include -#include - -#include "stm32_otgfs.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#ifndef CONFIG_STM32_OTGFS -# error "CONFIG_USBDEV requires CONFIG_STM32_OTGFS to be enabled" -#endif - -#ifdef CONFIG_USBHOST -# error "CONFIG_USBDEV cannot be set alongside CONFIG_USBHOST" -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_usbsuspend - * - * Description: - * Board logic must provide the stm32_usbsuspend logic if the USBDEV driver - * is used. This function is called whenever the USB enters or leaves - * suspend mode. This is an opportunity for the board logic to shutdown - * clocks, power, etc. while the USB is suspended. - * - * TODO: - * - Well... implement those features like clock shutdown. - ****************************************************************************/ - -void stm32_usbsuspend(struct usbdev_s *dev, bool resume) -{ - uinfo("INFO: usb %s", resume ? "resumed" : "suspended"); -} diff --git a/boards/arm/stm32/stm32butterfly2/src/stm32_usbhost.c b/boards/arm/stm32/stm32butterfly2/src/stm32_usbhost.c deleted file mode 100644 index 7d5c6a160e4ae..0000000000000 --- a/boards/arm/stm32/stm32butterfly2/src/stm32_usbhost.c +++ /dev/null @@ -1,187 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32butterfly2/src/stm32_usbhost.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "stm32.h" -#include "stm32_butterfly2.h" -#include "stm32_otgfs.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#ifndef CONFIG_STM32_OTGFS -# error "CONFIG_USBHOST requires CONFIG_STM32_OTGFS to be enabled" -#endif - -#ifdef CONFIG_USBDEV -# error "CONFIG_USBHOST cannot be set alongside CONFIG_USBDEV" -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -static struct usbhost_connection_s *g_usbconn; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: usbhost_detect - * - * Description: - * Wait for USB devices to be connected. - ****************************************************************************/ - -static void *usbhost_detect(void *arg) -{ - struct usbhost_hubport_s *hport; - - uinfo("INFO: Starting usb detect thread\n"); - - for (; ; ) - { - CONN_WAIT(g_usbconn, &hport); - - if (hport->connected) - { - CONN_ENUMERATE(g_usbconn, hport); - } - } - - return 0; -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_usbhost_initialize - * - * Description: - * Initializes USB host functionality. - ****************************************************************************/ - -int stm32_usbhost_initialize(void) -{ - int rv; - -#ifdef CONFIG_USBHOST_MSC - uinfo("INFO: Initializing USB MSC class\n"); - - if ((rv = usbhost_msc_initialize()) < 0) - { - uerr("ERROR: Failed to register mass storage class: %d\n", rv); - } -#endif - -#ifdef CONFIG_USBHOST_CDACM - uinfo("INFO: Initializing CDCACM usb class\n"); - - if ((rv = usbhost_cdacm_initialize()) < 0) - { - uerr("ERROR: Failed to register CDC/ACM serial class: %d\n", rv); - } -#endif - -#ifdef CONFIG_USBHOST_HIDKBD - uinfo("INFO: Initializing HID Keyboard usb class\n"); - - if ((rv = usbhost_kbdinit()) < 0) - { - uerr("ERROR: Failed to register the KBD class: %d\n", rv); - } -#endif - -#ifdef CONFIG_USBHOST_HIDMOUSE - uinfo("INFO: Initializing HID Mouse usb class\n"); - - if ((rv = usbhost_mouse_init()) < 0) - { - uerr("ERROR: Failed to register the mouse class: %d\n", rv); - } -#endif - -#ifdef CONFIG_USBHOST_HUB - uinfo("INFO: Initializing USB HUB class\n"); - - if ((rv = usbhost_hub_initialize()) < 0) - { - uerr("ERROR: Failed to register hub class: %d\n", rv); - } -#endif - - if ((g_usbconn = stm32_otgfshost_initialize(0))) - { - pthread_attr_t pattr; - struct sched_param schparam; - - pthread_attr_init(&pattr); - pthread_attr_setstacksize(&pattr, 2048); - - schparam.sched_priority = 50; - pthread_attr_setschedparam(&pattr, &schparam); - - return pthread_create(NULL, &pattr, usbhost_detect, NULL); - } - - return -ENODEV; -} - -/**************************************************************************** - * Name: stm32_usbhost_vbusdrive - * - * Description: - * Enable/disable driving of VBUS 5V output. - * - * The application uses this field to control power to this port, and the - * core clears this bit on an overcurrent condition. - * - * Input Parameters: - * iface - For future growth to handle multiple USB host interface. - * Should be zero. - * enable - true: enable VBUS power; false: disable VBUS power - * - * Returned Value: - * None - ****************************************************************************/ - -void stm32_usbhost_vbusdrive(int iface, bool enable) -{ - stm32_gpiowrite(GPIO_OTGFS_PWRON, enable); -} diff --git a/boards/arm/stm32/stm32f103-minimum/CMakeLists.txt b/boards/arm/stm32/stm32f103-minimum/CMakeLists.txt deleted file mode 100644 index d4b2e558d3015..0000000000000 --- a/boards/arm/stm32/stm32f103-minimum/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/stm32f103-minimum/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32/stm32f103-minimum/configs/adb/defconfig b/boards/arm/stm32/stm32f103-minimum/configs/adb/defconfig deleted file mode 100644 index 493f2fdb00338..0000000000000 --- a/boards/arm/stm32/stm32f103-minimum/configs/adb/defconfig +++ /dev/null @@ -1,78 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_BINFMT_DISABLE is not set -# CONFIG_DISABLE_OS_API is not set -# CONFIG_FS_PROCFS_EXCLUDE_BLOCKS is not set -# CONFIG_FS_PROCFS_EXCLUDE_ENVIRON is not set -# CONFIG_FS_PROCFS_EXCLUDE_MEMDUMP is not set -# CONFIG_FS_PROCFS_EXCLUDE_MEMINFO is not set -# CONFIG_FS_PROCFS_EXCLUDE_MOUNT is not set -# CONFIG_FS_PROCFS_EXCLUDE_PROCESS is not set -# CONFIG_FS_PROCFS_EXCLUDE_UPTIME is not set -# CONFIG_FS_PROCFS_EXCLUDE_USAGE is not set -# CONFIG_FS_PROCFS_EXCLUDE_VERSION is not set -# CONFIG_FS_PROCFS_INCLUDE_PROGMEM is not set -# CONFIG_NSH_DISABLESCRIPT is not set -# CONFIG_NSH_DISABLE_EXEC is not set -# CONFIG_NSH_DISABLE_EXIT is not set -# CONFIG_NSH_DISABLE_GET is not set -# CONFIG_NSH_DISABLE_HEXDUMP is not set -# CONFIG_NSH_DISABLE_PUT is not set -# CONFIG_NSH_DISABLE_WGET is not set -# CONFIG_NSH_DISABLE_XD is not set -CONFIG_ADBD_DEVICE_ID="test" -CONFIG_ADBD_FILE_SERVICE=y -CONFIG_ADBD_SHELL_SERVICE=y -CONFIG_ADBD_USB_SERVER=y -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f103-minimum" -CONFIG_ARCH_BOARD_STM32F103_MINIMUM=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F103C8=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=5483 -CONFIG_BUILTIN=y -CONFIG_DEFAULT_SMALL=y -CONFIG_ENABLE_ALL_SIGNALS=y -CONFIG_EXAMPLES_HELLO=y -CONFIG_FILE_STREAM=y -CONFIG_FS_PROCFS=y -CONFIG_INIT_ENTRYPOINT="adbd_main" -CONFIG_INIT_STACKSIZE=1024 -CONFIG_LIBC_EXECFUNCS=y -CONFIG_LIBUV=y -CONFIG_LINE_MAX=80 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=1024 -CONFIG_PSEUDOTERM=y -CONFIG_RAM_SIZE=20480 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_CHILD_STATUS=y -CONFIG_SCHED_HAVE_PARENT=y -CONFIG_SCHED_WAITPID=y -CONFIG_SERIAL_TERMIOS=y -CONFIG_STACK_COLORATION=y -CONFIG_START_DAY=5 -CONFIG_START_MONTH=7 -CONFIG_START_YEAR=2011 -CONFIG_STM32_DFU=y -CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32_JTAG_FULL_ENABLE=y -CONFIG_STM32_USART1=y -CONFIG_STM32_USB=y -CONFIG_SYMTAB_ORDEREDBYNAME=y -CONFIG_SYSTEM_ADBD=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=8 -CONFIG_TLS_TASK_NELEM=4 -CONFIG_USART1_SERIAL_CONSOLE=y -CONFIG_USBADB=y -CONFIG_USBDEV_BUSPOWERED=y diff --git a/boards/arm/stm32/stm32f103-minimum/configs/apds9960/defconfig b/boards/arm/stm32/stm32f103-minimum/configs/apds9960/defconfig deleted file mode 100644 index 2789b752ecf43..0000000000000 --- a/boards/arm/stm32/stm32f103-minimum/configs/apds9960/defconfig +++ /dev/null @@ -1,60 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_DISABLE_OS_API is not set -# CONFIG_NSH_DISABLESCRIPT is not set -# CONFIG_NSH_DISABLE_EXEC is not set -# CONFIG_NSH_DISABLE_EXIT is not set -# CONFIG_NSH_DISABLE_GET is not set -# CONFIG_NSH_DISABLE_HEXDUMP is not set -# CONFIG_NSH_DISABLE_MKRD is not set -# CONFIG_NSH_DISABLE_PS is not set -# CONFIG_NSH_DISABLE_PUT is not set -# CONFIG_NSH_DISABLE_WGET is not set -# CONFIG_NSH_DISABLE_XD is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f103-minimum" -CONFIG_ARCH_BOARD_COMMON=y -CONFIG_ARCH_BOARD_STM32F103_MINIMUM=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F103C8=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=5483 -CONFIG_BUILTIN=y -CONFIG_DEFAULT_SMALL=y -CONFIG_EXAMPLES_APDS9960=y -CONFIG_FILE_STREAM=y -CONFIG_I2C_DRIVER=y -CONFIG_IDLETHREAD_STACKSIZE=512 -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_LINE_MAX=80 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=1024 -CONFIG_PTHREAD_STACK_MIN=512 -CONFIG_RAM_SIZE=20480 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_HPWORKPRIORITY=192 -CONFIG_SCHED_HPWORKSTACKSIZE=3072 -CONFIG_SCHED_WAITPID=y -CONFIG_SENSORS=y -CONFIG_SENSORS_APDS9960=y -CONFIG_SERIAL_TERMIOS=y -CONFIG_START_DAY=5 -CONFIG_START_MONTH=7 -CONFIG_START_YEAR=2011 -CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32_I2C1=y -CONFIG_STM32_JTAG_FULL_ENABLE=y -CONFIG_STM32_USART1=y -CONFIG_SYMTAB_ORDEREDBYNAME=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/stm32f103-minimum/configs/audio_tone/defconfig b/boards/arm/stm32/stm32f103-minimum/configs/audio_tone/defconfig deleted file mode 100644 index 6c6800df69d9d..0000000000000 --- a/boards/arm/stm32/stm32f103-minimum/configs/audio_tone/defconfig +++ /dev/null @@ -1,61 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_DISABLE_OS_API is not set -# CONFIG_NSH_DISABLESCRIPT is not set -# CONFIG_NSH_DISABLE_EXEC is not set -# CONFIG_NSH_DISABLE_EXIT is not set -# CONFIG_NSH_DISABLE_GET is not set -# CONFIG_NSH_DISABLE_HEXDUMP is not set -# CONFIG_NSH_DISABLE_MKRD is not set -# CONFIG_NSH_DISABLE_PS is not set -# CONFIG_NSH_DISABLE_PUT is not set -# CONFIG_NSH_DISABLE_WGET is not set -# CONFIG_NSH_DISABLE_XD is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f103-minimum" -CONFIG_ARCH_BOARD_COMMON=y -CONFIG_ARCH_BOARD_STM32F103_MINIMUM=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F103C8=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_AUDIO=y -CONFIG_AUDIO_TONE=y -CONFIG_BOARD_LOOPSPERMSEC=5483 -CONFIG_BUILTIN=y -CONFIG_DEFAULT_SMALL=y -CONFIG_DRIVERS_AUDIO=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_LINE_MAX=80 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=1024 -CONFIG_PWM=y -CONFIG_RAM_SIZE=20480 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_HPWORKPRIORITY=192 -CONFIG_SCHED_WAITPID=y -CONFIG_SERIAL_TERMIOS=y -CONFIG_START_DAY=5 -CONFIG_START_MONTH=7 -CONFIG_START_YEAR=2011 -CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32_JTAG_FULL_ENABLE=y -CONFIG_STM32_ONESHOT=y -CONFIG_STM32_TIM2=y -CONFIG_STM32_TIM2_CH2OUT=y -CONFIG_STM32_TIM2_CHANNEL=2 -CONFIG_STM32_TIM2_PWM=y -CONFIG_STM32_TIM3=y -CONFIG_STM32_USART1=y -CONFIG_SYMTAB_ORDEREDBYNAME=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/stm32f103-minimum/configs/buttons/defconfig b/boards/arm/stm32/stm32f103-minimum/configs/buttons/defconfig deleted file mode 100644 index 11c015562a8d0..0000000000000 --- a/boards/arm/stm32/stm32f103-minimum/configs/buttons/defconfig +++ /dev/null @@ -1,58 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_LEDS is not set -# CONFIG_DISABLE_OS_API is not set -# CONFIG_NSH_DISABLESCRIPT is not set -# CONFIG_NSH_DISABLE_EXEC is not set -# CONFIG_NSH_DISABLE_EXIT is not set -# CONFIG_NSH_DISABLE_GET is not set -# CONFIG_NSH_DISABLE_HEXDUMP is not set -# CONFIG_NSH_DISABLE_MKRD is not set -# CONFIG_NSH_DISABLE_PS is not set -# CONFIG_NSH_DISABLE_PUT is not set -# CONFIG_NSH_DISABLE_WGET is not set -# CONFIG_NSH_DISABLE_XD is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f103-minimum" -CONFIG_ARCH_BOARD_STM32F103_MINIMUM=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F103C8=y -CONFIG_ARCH_IRQBUTTONS=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=5483 -CONFIG_BUILTIN=y -CONFIG_DEFAULT_SMALL=y -CONFIG_EXAMPLES_BUTTONS=y -CONFIG_FILE_STREAM=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INPUT=y -CONFIG_INPUT_BUTTONS=y -CONFIG_INPUT_BUTTONS_LOWER=y -CONFIG_LINE_MAX=80 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=1024 -CONFIG_RAM_SIZE=20480 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_HPWORKPRIORITY=192 -CONFIG_SCHED_WAITPID=y -CONFIG_SERIAL_TERMIOS=y -CONFIG_START_DAY=5 -CONFIG_START_MONTH=7 -CONFIG_START_YEAR=2011 -CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_USART1=y -CONFIG_SYMTAB_ORDEREDBYNAME=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/stm32f103-minimum/configs/can/defconfig b/boards/arm/stm32/stm32f103-minimum/configs/can/defconfig deleted file mode 100644 index 8d76332f3deef..0000000000000 --- a/boards/arm/stm32/stm32f103-minimum/configs/can/defconfig +++ /dev/null @@ -1,73 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_DISABLE_OS_API is not set -# CONFIG_NSH_DISABLESCRIPT is not set -# CONFIG_NSH_DISABLE_CAT is not set -# CONFIG_NSH_DISABLE_CD is not set -# CONFIG_NSH_DISABLE_CP is not set -# CONFIG_NSH_DISABLE_ECHO is not set -# CONFIG_NSH_DISABLE_EXEC is not set -# CONFIG_NSH_DISABLE_EXIT is not set -# CONFIG_NSH_DISABLE_FREE is not set -# CONFIG_NSH_DISABLE_GET is not set -# CONFIG_NSH_DISABLE_HEXDUMP is not set -# CONFIG_NSH_DISABLE_LS is not set -# CONFIG_NSH_DISABLE_MKDIR is not set -# CONFIG_NSH_DISABLE_MOUNT is not set -# CONFIG_NSH_DISABLE_PS is not set -# CONFIG_NSH_DISABLE_PUT is not set -# CONFIG_NSH_DISABLE_PWD is not set -# CONFIG_NSH_DISABLE_RM is not set -# CONFIG_NSH_DISABLE_SLEEP is not set -# CONFIG_NSH_DISABLE_TEST is not set -# CONFIG_NSH_DISABLE_UMOUNT is not set -# CONFIG_NSH_DISABLE_UNAME is not set -# CONFIG_NSH_DISABLE_WGET is not set -# CONFIG_NSH_DISABLE_XD is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f103-minimum" -CONFIG_ARCH_BOARD_COMMON=y -CONFIG_ARCH_BOARD_STM32F103_MINIMUM=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F103C8=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=5483 -CONFIG_BUILTIN=y -CONFIG_CAN_ERRORS=y -CONFIG_CAN_EXTID=y -CONFIG_DEFAULT_SMALL=y -CONFIG_EXAMPLES_CAN=y -CONFIG_EXAMPLES_CAN_NMSGS=4 -CONFIG_EXAMPLES_CAN_WRITE=y -CONFIG_HOST_MACOS=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_LINE_MAX=80 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=1024 -CONFIG_RAM_SIZE=20480 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_HPWORKPRIORITY=192 -CONFIG_SCHED_WAITPID=y -CONFIG_SERIAL_TERMIOS=y -CONFIG_START_DAY=5 -CONFIG_START_MONTH=7 -CONFIG_START_YEAR=2011 -CONFIG_STM32_CAN1=y -CONFIG_STM32_CAN_TSEG1=13 -CONFIG_STM32_CAN_TSEG2=2 -CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32_JTAG_FULL_ENABLE=y -CONFIG_STM32_USART1=y -CONFIG_SYMTAB_ORDEREDBYNAME=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/stm32f103-minimum/configs/hello/defconfig b/boards/arm/stm32/stm32f103-minimum/configs/hello/defconfig deleted file mode 100644 index 029d1efc9443f..0000000000000 --- a/boards/arm/stm32/stm32f103-minimum/configs/hello/defconfig +++ /dev/null @@ -1,50 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_LEDS is not set -# CONFIG_NSH_DISABLEBG is not set -# CONFIG_NSH_DISABLE_DF is not set -# CONFIG_NSH_DISABLE_EXEC is not set -# CONFIG_NSH_DISABLE_EXIT is not set -# CONFIG_NSH_DISABLE_GET is not set -# CONFIG_NSH_DISABLE_HEXDUMP is not set -# CONFIG_NSH_DISABLE_PS is not set -# CONFIG_NSH_DISABLE_XD is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f103-minimum" -CONFIG_ARCH_BOARD_STM32F103_MINIMUM=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F103C8=y -CONFIG_BOARD_LOOPSPERMSEC=5483 -CONFIG_DEFAULT_SMALL=y -CONFIG_DISABLE_MOUNTPOINT=y -CONFIG_EXAMPLES_HELLO=y -CONFIG_FDCLONE_STDIO=y -CONFIG_INIT_ENTRYPOINT="hello_main" -CONFIG_INIT_STACKSIZE=1536 -CONFIG_LINE_MAX=80 -CONFIG_MM_SMALL=y -CONFIG_NSH_FILEIOSIZE=64 -CONFIG_NUNGET_CHARS=0 -CONFIG_POSIX_SPAWN_DEFAULT_STACKSIZE=1536 -CONFIG_PTHREAD_STACK_DEFAULT=1536 -CONFIG_RAM_SIZE=20480 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SERIAL_TERMIOS=y -CONFIG_START_DAY=5 -CONFIG_START_MONTH=7 -CONFIG_START_YEAR=2011 -CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32_JTAG_FULL_ENABLE=y -CONFIG_STM32_NOEXT_VECTORS=y -CONFIG_STM32_USART1=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/stm32f103-minimum/configs/jlx12864g/defconfig b/boards/arm/stm32/stm32f103-minimum/configs/jlx12864g/defconfig deleted file mode 100644 index 5eea66e1f1b5d..0000000000000 --- a/boards/arm/stm32/stm32f103-minimum/configs/jlx12864g/defconfig +++ /dev/null @@ -1,65 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_DISABLE_OS_API is not set -# CONFIG_NSH_DISABLESCRIPT is not set -# CONFIG_NSH_DISABLE_EXEC is not set -# CONFIG_NSH_DISABLE_EXIT is not set -# CONFIG_NSH_DISABLE_GET is not set -# CONFIG_NSH_DISABLE_HEXDUMP is not set -# CONFIG_NSH_DISABLE_MKRD is not set -# CONFIG_NSH_DISABLE_PS is not set -# CONFIG_NSH_DISABLE_PUT is not set -# CONFIG_NSH_DISABLE_WGET is not set -# CONFIG_NSH_DISABLE_XD is not set -# CONFIG_NX_DISABLE_1BPP is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f103-minimum" -CONFIG_ARCH_BOARD_STM32F103_MINIMUM=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F103C8=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=5483 -CONFIG_BUILTIN=y -CONFIG_DEFAULT_SMALL=y -CONFIG_EXAMPLES_NXHELLO=y -CONFIG_EXAMPLES_NXHELLO_BPP=1 -CONFIG_EXAMPLES_NXHELLO_LISTENER_STACKSIZE=1536 -CONFIG_EXAMPLES_NXHELLO_STACKSIZE=1536 -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_LCD=y -CONFIG_LCD_ST7567=y -CONFIG_LINE_MAX=80 -CONFIG_MQ_MAXMSGSIZE=64 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=1024 -CONFIG_NX=y -CONFIG_NXFONT_MONO5X8=y -CONFIG_NXTK_BORDERWIDTH=1 -CONFIG_NX_BLOCKING=y -CONFIG_NX_WRITEONLY=y -CONFIG_RAM_SIZE=20480 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_HPWORKPRIORITY=192 -CONFIG_SCHED_WAITPID=y -CONFIG_SERIAL_TERMIOS=y -CONFIG_SPI_CMDDATA=y -CONFIG_START_DAY=5 -CONFIG_START_MONTH=7 -CONFIG_START_YEAR=2011 -CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32_JTAG_FULL_ENABLE=y -CONFIG_STM32_SPI1=y -CONFIG_STM32_USART1=y -CONFIG_SYMTAB_ORDEREDBYNAME=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/stm32f103-minimum/configs/lcd1602/defconfig b/boards/arm/stm32/stm32f103-minimum/configs/lcd1602/defconfig deleted file mode 100644 index b91f9cca66b55..0000000000000 --- a/boards/arm/stm32/stm32f103-minimum/configs/lcd1602/defconfig +++ /dev/null @@ -1,62 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_DISABLE_OS_API is not set -# CONFIG_NSH_DISABLESCRIPT is not set -# CONFIG_NSH_DISABLE_EXEC is not set -# CONFIG_NSH_DISABLE_EXIT is not set -# CONFIG_NSH_DISABLE_GET is not set -# CONFIG_NSH_DISABLE_HEXDUMP is not set -# CONFIG_NSH_DISABLE_MKRD is not set -# CONFIG_NSH_DISABLE_PS is not set -# CONFIG_NSH_DISABLE_PUT is not set -# CONFIG_NSH_DISABLE_WGET is not set -# CONFIG_NSH_DISABLE_XD is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f103-minimum" -CONFIG_ARCH_BOARD_COMMON=y -CONFIG_ARCH_BOARD_STM32F103_MINIMUM=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F103C8=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=5483 -CONFIG_BUILTIN=y -CONFIG_DEFAULT_SMALL=y -CONFIG_EXAMPLES_SLCD=y -CONFIG_FILE_STREAM=y -CONFIG_I2C=y -CONFIG_I2CTOOL_DEFFREQ=100000 -CONFIG_I2CTOOL_MAXBUS=1 -CONFIG_I2CTOOL_MINBUS=1 -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_LCD_BACKPACK=y -CONFIG_LCD_LCD1602=y -CONFIG_LINE_MAX=80 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=1024 -CONFIG_RAM_SIZE=20480 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_HPWORKPRIORITY=192 -CONFIG_SCHED_WAITPID=y -CONFIG_SERIAL_TERMIOS=y -CONFIG_SLCD=y -CONFIG_START_DAY=5 -CONFIG_START_MONTH=7 -CONFIG_START_YEAR=2011 -CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32_I2C1=y -CONFIG_STM32_JTAG_FULL_ENABLE=y -CONFIG_STM32_USART1=y -CONFIG_SYMTAB_ORDEREDBYNAME=y -CONFIG_SYSTEM_I2CTOOL=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/stm32f103-minimum/configs/mcp2515/defconfig b/boards/arm/stm32/stm32f103-minimum/configs/mcp2515/defconfig deleted file mode 100644 index 9f2e614adb3ac..0000000000000 --- a/boards/arm/stm32/stm32f103-minimum/configs/mcp2515/defconfig +++ /dev/null @@ -1,59 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_DISABLE_OS_API is not set -# CONFIG_NSH_DISABLESCRIPT is not set -# CONFIG_NSH_DISABLE_EXEC is not set -# CONFIG_NSH_DISABLE_EXIT is not set -# CONFIG_NSH_DISABLE_GET is not set -# CONFIG_NSH_DISABLE_HEXDUMP is not set -# CONFIG_NSH_DISABLE_MKRD is not set -# CONFIG_NSH_DISABLE_PS is not set -# CONFIG_NSH_DISABLE_PUT is not set -# CONFIG_NSH_DISABLE_WGET is not set -# CONFIG_NSH_DISABLE_XD is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f103-minimum" -CONFIG_ARCH_BOARD_STM32F103_MINIMUM=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F103C8=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=5483 -CONFIG_BUILTIN=y -CONFIG_CAN=y -CONFIG_CANUTILS_CANLIB=y -CONFIG_CAN_MCP2515=y -CONFIG_CAN_TXREADY=y -CONFIG_DEFAULT_SMALL=y -CONFIG_EXAMPLES_CAN=y -CONFIG_EXAMPLES_CAN_READ=y -CONFIG_FILE_STREAM=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_LINE_MAX=80 -CONFIG_MCP2515_PHASESEG1=3 -CONFIG_MCP2515_PROPSEG=1 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=1024 -CONFIG_RAM_SIZE=20480 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORKPRIORITY=192 -CONFIG_SCHED_WAITPID=y -CONFIG_SERIAL_TERMIOS=y -CONFIG_START_DAY=5 -CONFIG_START_MONTH=7 -CONFIG_START_YEAR=2011 -CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32_JTAG_FULL_ENABLE=y -CONFIG_STM32_SPI1=y -CONFIG_STM32_USART1=y -CONFIG_SYMTAB_ORDEREDBYNAME=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/stm32f103-minimum/configs/nrf24/defconfig b/boards/arm/stm32/stm32f103-minimum/configs/nrf24/defconfig deleted file mode 100644 index ac06a6bc606b6..0000000000000 --- a/boards/arm/stm32/stm32f103-minimum/configs/nrf24/defconfig +++ /dev/null @@ -1,56 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_DISABLE_OS_API is not set -# CONFIG_NSH_DISABLESCRIPT is not set -# CONFIG_NSH_DISABLE_EXEC is not set -# CONFIG_NSH_DISABLE_EXIT is not set -# CONFIG_NSH_DISABLE_GET is not set -# CONFIG_NSH_DISABLE_HEXDUMP is not set -# CONFIG_NSH_DISABLE_MKRD is not set -# CONFIG_NSH_DISABLE_PS is not set -# CONFIG_NSH_DISABLE_PUT is not set -# CONFIG_NSH_DISABLE_WGET is not set -# CONFIG_NSH_DISABLE_XD is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f103-minimum" -CONFIG_ARCH_BOARD_COMMON=y -CONFIG_ARCH_BOARD_STM32F103_MINIMUM=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F103C8=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=5483 -CONFIG_BUILTIN=y -CONFIG_DEFAULT_SMALL=y -CONFIG_DRIVERS_WIRELESS=y -CONFIG_EXAMPLES_NRF24L01TERM=y -CONFIG_FILE_STREAM=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_LINE_MAX=80 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=1024 -CONFIG_RAM_SIZE=20480 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_HPWORKPRIORITY=192 -CONFIG_SCHED_WAITPID=y -CONFIG_SERIAL_TERMIOS=y -CONFIG_START_DAY=5 -CONFIG_START_MONTH=7 -CONFIG_START_YEAR=2011 -CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32_JTAG_FULL_ENABLE=y -CONFIG_STM32_SPI1=y -CONFIG_STM32_USART1=y -CONFIG_SYMTAB_ORDEREDBYNAME=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART1_SERIAL_CONSOLE=y -CONFIG_WL_NRF24L01=y diff --git a/boards/arm/stm32/stm32f103-minimum/configs/nsh/defconfig b/boards/arm/stm32/stm32f103-minimum/configs/nsh/defconfig deleted file mode 100644 index 3c704737ee264..0000000000000 --- a/boards/arm/stm32/stm32f103-minimum/configs/nsh/defconfig +++ /dev/null @@ -1,64 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_DISABLE_OS_API is not set -# CONFIG_NSH_DISABLESCRIPT is not set -# CONFIG_NSH_DISABLE_CAT is not set -# CONFIG_NSH_DISABLE_CD is not set -# CONFIG_NSH_DISABLE_CP is not set -# CONFIG_NSH_DISABLE_ECHO is not set -# CONFIG_NSH_DISABLE_EXEC is not set -# CONFIG_NSH_DISABLE_EXIT is not set -# CONFIG_NSH_DISABLE_FREE is not set -# CONFIG_NSH_DISABLE_GET is not set -# CONFIG_NSH_DISABLE_HEXDUMP is not set -# CONFIG_NSH_DISABLE_LS is not set -# CONFIG_NSH_DISABLE_MKDIR is not set -# CONFIG_NSH_DISABLE_MOUNT is not set -# CONFIG_NSH_DISABLE_PS is not set -# CONFIG_NSH_DISABLE_PUT is not set -# CONFIG_NSH_DISABLE_PWD is not set -# CONFIG_NSH_DISABLE_RM is not set -# CONFIG_NSH_DISABLE_SLEEP is not set -# CONFIG_NSH_DISABLE_TEST is not set -# CONFIG_NSH_DISABLE_UMOUNT is not set -# CONFIG_NSH_DISABLE_UNAME is not set -# CONFIG_NSH_DISABLE_WGET is not set -# CONFIG_NSH_DISABLE_XD is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f103-minimum" -CONFIG_ARCH_BOARD_COMMON=y -CONFIG_ARCH_BOARD_STM32F103_MINIMUM=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F103C8=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=5483 -CONFIG_BUILTIN=y -CONFIG_DEFAULT_SMALL=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_LINE_MAX=80 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=1024 -CONFIG_RAM_SIZE=20480 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_HPWORKPRIORITY=192 -CONFIG_SCHED_WAITPID=y -CONFIG_SERIAL_TERMIOS=y -CONFIG_START_DAY=5 -CONFIG_START_MONTH=7 -CONFIG_START_YEAR=2011 -CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32_JTAG_FULL_ENABLE=y -CONFIG_STM32_USART1=y -CONFIG_SYMTAB_ORDEREDBYNAME=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/stm32f103-minimum/configs/pwm/defconfig b/boards/arm/stm32/stm32f103-minimum/configs/pwm/defconfig deleted file mode 100644 index 8d0dda31037f1..0000000000000 --- a/boards/arm/stm32/stm32f103-minimum/configs/pwm/defconfig +++ /dev/null @@ -1,57 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_DISABLE_OS_API is not set -# CONFIG_NSH_DISABLESCRIPT is not set -# CONFIG_NSH_DISABLE_EXEC is not set -# CONFIG_NSH_DISABLE_EXIT is not set -# CONFIG_NSH_DISABLE_GET is not set -# CONFIG_NSH_DISABLE_HEXDUMP is not set -# CONFIG_NSH_DISABLE_MKRD is not set -# CONFIG_NSH_DISABLE_PS is not set -# CONFIG_NSH_DISABLE_PUT is not set -# CONFIG_NSH_DISABLE_WGET is not set -# CONFIG_NSH_DISABLE_XD is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f103-minimum" -CONFIG_ARCH_BOARD_STM32F103_MINIMUM=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F103C8=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=5483 -CONFIG_BUILTIN=y -CONFIG_DEFAULT_SMALL=y -CONFIG_EXAMPLES_PWM=y -CONFIG_FILE_STREAM=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_LINE_MAX=80 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=1024 -CONFIG_PWM=y -CONFIG_RAM_SIZE=20480 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_HPWORKPRIORITY=192 -CONFIG_SCHED_WAITPID=y -CONFIG_SERIAL_TERMIOS=y -CONFIG_START_DAY=5 -CONFIG_START_MONTH=7 -CONFIG_START_YEAR=2011 -CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32_JTAG_FULL_ENABLE=y -CONFIG_STM32_TIM3=y -CONFIG_STM32_TIM3_CH3OUT=y -CONFIG_STM32_TIM3_CHANNEL=3 -CONFIG_STM32_TIM3_PWM=y -CONFIG_STM32_USART1=y -CONFIG_SYMTAB_ORDEREDBYNAME=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/stm32f103-minimum/configs/rfid-rc522/defconfig b/boards/arm/stm32/stm32f103-minimum/configs/rfid-rc522/defconfig deleted file mode 100644 index 9b30668c97ea4..0000000000000 --- a/boards/arm/stm32/stm32f103-minimum/configs/rfid-rc522/defconfig +++ /dev/null @@ -1,55 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_DISABLE_OS_API is not set -# CONFIG_NSH_DISABLESCRIPT is not set -# CONFIG_NSH_DISABLE_EXEC is not set -# CONFIG_NSH_DISABLE_EXIT is not set -# CONFIG_NSH_DISABLE_GET is not set -# CONFIG_NSH_DISABLE_HEXDUMP is not set -# CONFIG_NSH_DISABLE_MKRD is not set -# CONFIG_NSH_DISABLE_PS is not set -# CONFIG_NSH_DISABLE_PUT is not set -# CONFIG_NSH_DISABLE_WGET is not set -# CONFIG_NSH_DISABLE_XD is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f103-minimum" -CONFIG_ARCH_BOARD_COMMON=y -CONFIG_ARCH_BOARD_STM32F103_MINIMUM=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F103C8=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=5483 -CONFIG_BUILTIN=y -CONFIG_CL_MFRC522=y -CONFIG_DEFAULT_SMALL=y -CONFIG_DRIVERS_CONTACTLESS=y -CONFIG_EXAMPLES_RFID_READUID=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_LINE_MAX=80 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=1024 -CONFIG_RAM_SIZE=20480 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_HPWORKPRIORITY=192 -CONFIG_SCHED_WAITPID=y -CONFIG_SERIAL_TERMIOS=y -CONFIG_START_DAY=5 -CONFIG_START_MONTH=7 -CONFIG_START_YEAR=2011 -CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32_JTAG_FULL_ENABLE=y -CONFIG_STM32_SPI1=y -CONFIG_STM32_USART1=y -CONFIG_SYMTAB_ORDEREDBYNAME=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/stm32f103-minimum/configs/rgbled/defconfig b/boards/arm/stm32/stm32f103-minimum/configs/rgbled/defconfig deleted file mode 100644 index cba32112192c0..0000000000000 --- a/boards/arm/stm32/stm32f103-minimum/configs/rgbled/defconfig +++ /dev/null @@ -1,69 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_DISABLE_OS_API is not set -# CONFIG_NSH_DISABLESCRIPT is not set -# CONFIG_NSH_DISABLE_EXEC is not set -# CONFIG_NSH_DISABLE_EXIT is not set -# CONFIG_NSH_DISABLE_GET is not set -# CONFIG_NSH_DISABLE_HEXDUMP is not set -# CONFIG_NSH_DISABLE_MKRD is not set -# CONFIG_NSH_DISABLE_PS is not set -# CONFIG_NSH_DISABLE_PUT is not set -# CONFIG_NSH_DISABLE_WGET is not set -# CONFIG_NSH_DISABLE_XD is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f103-minimum" -CONFIG_ARCH_BOARD_STM32F103_MINIMUM=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F103C8=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=5483 -CONFIG_BUILTIN=y -CONFIG_DEFAULT_SMALL=y -CONFIG_EXAMPLES_RGBLED=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_LINE_MAX=80 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=1024 -CONFIG_PWM=y -CONFIG_PWM_NCHANNELS=3 -CONFIG_RAM_SIZE=20480 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RGBLED=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_HPWORKPRIORITY=192 -CONFIG_SCHED_WAITPID=y -CONFIG_SERIAL_TERMIOS=y -CONFIG_START_DAY=5 -CONFIG_START_MONTH=7 -CONFIG_START_YEAR=2011 -CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32_JTAG_FULL_ENABLE=y -CONFIG_STM32_TIM1=y -CONFIG_STM32_TIM1_CH1OUT=y -CONFIG_STM32_TIM1_PWM=y -CONFIG_STM32_TIM2=y -CONFIG_STM32_TIM2_CH2OUT=y -CONFIG_STM32_TIM2_CHANNEL=2 -CONFIG_STM32_TIM2_PWM=y -CONFIG_STM32_TIM3=y -CONFIG_STM32_TIM3_CH3OUT=y -CONFIG_STM32_TIM3_CHANNEL=3 -CONFIG_STM32_TIM3_PWM=y -CONFIG_STM32_TIM4=y -CONFIG_STM32_TIM4_CH4OUT=y -CONFIG_STM32_TIM4_CHANNEL=4 -CONFIG_STM32_TIM4_PWM=y -CONFIG_STM32_USART1=y -CONFIG_SYMTAB_ORDEREDBYNAME=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/stm32f103-minimum/configs/sensors/defconfig b/boards/arm/stm32/stm32f103-minimum/configs/sensors/defconfig deleted file mode 100644 index 589d6e8d4ddff..0000000000000 --- a/boards/arm/stm32/stm32f103-minimum/configs/sensors/defconfig +++ /dev/null @@ -1,69 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_DEV_CONSOLE is not set -# CONFIG_DISABLE_OS_API is not set -# CONFIG_NSH_DISABLEBG is not set -# CONFIG_NSH_DISABLESCRIPT is not set -# CONFIG_NSH_DISABLE_EXEC is not set -# CONFIG_NSH_DISABLE_EXIT is not set -# CONFIG_NSH_DISABLE_MB is not set -# CONFIG_NSH_DISABLE_MH is not set -# CONFIG_NSH_DISABLE_MW is not set -# CONFIG_NSH_DISABLE_PS is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f103-minimum" -CONFIG_ARCH_BOARD_STM32F103_MINIMUM=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F103C8=y -CONFIG_BOARDCTL=y -CONFIG_BOARDCTL_USBDEVCTRL=y -CONFIG_BOARD_LOOPSPERMSEC=5483 -CONFIG_BUILTIN=y -CONFIG_CDCACM=y -CONFIG_CDCACM_CONSOLE=y -CONFIG_CDCACM_RXBUFSIZE=256 -CONFIG_CDCACM_TXBUFSIZE=256 -CONFIG_DEFAULT_SMALL=y -CONFIG_ENABLE_ALL_SIGNALS=y -CONFIG_I2C=y -CONFIG_I2C_DRIVER=y -CONFIG_I2C_RESET=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_LIBC_FLOATINGPOINT=y -CONFIG_LIBM_TOOLCHAIN=y -CONFIG_LINE_MAX=80 -CONFIG_LTO_FULL=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=1024 -CONFIG_RAM_SIZE=20480 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_SENSORS=y -CONFIG_SENSORS_DS18B20=y -CONFIG_SENSORS_DS18B20_POLL=y -CONFIG_SENSORS_HYT271=y -CONFIG_SENSORS_HYT271_POLL=y -CONFIG_SERIAL_TERMIOS=y -CONFIG_START_DAY=5 -CONFIG_START_MONTH=7 -CONFIG_START_YEAR=2011 -CONFIG_STM32_I2C2=y -CONFIG_STM32_JTAG_FULL_ENABLE=y -CONFIG_STM32_TIM1=y -CONFIG_STM32_TIM2=y -CONFIG_STM32_USART1=y -CONFIG_STM32_USART2=y -CONFIG_STM32_USART2_1WIREDRIVER=y -CONFIG_STM32_USART_SINGLEWIRE=y -CONFIG_STM32_USB=y -CONFIG_SYSTEM_NSH=y -CONFIG_SYSTEM_SENSORTEST=y -CONFIG_TASK_NAME_SIZE=0 diff --git a/boards/arm/stm32/stm32f103-minimum/configs/ssd1306/defconfig b/boards/arm/stm32/stm32f103-minimum/configs/ssd1306/defconfig deleted file mode 100644 index 8ab229454da28..0000000000000 --- a/boards/arm/stm32/stm32f103-minimum/configs/ssd1306/defconfig +++ /dev/null @@ -1,73 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_DISABLE_OS_API is not set -# CONFIG_NSH_DISABLESCRIPT is not set -# CONFIG_NSH_DISABLE_CAT is not set -# CONFIG_NSH_DISABLE_CD is not set -# CONFIG_NSH_DISABLE_CP is not set -# CONFIG_NSH_DISABLE_ECHO is not set -# CONFIG_NSH_DISABLE_EXEC is not set -# CONFIG_NSH_DISABLE_EXIT is not set -# CONFIG_NSH_DISABLE_FREE is not set -# CONFIG_NSH_DISABLE_GET is not set -# CONFIG_NSH_DISABLE_HEXDUMP is not set -# CONFIG_NSH_DISABLE_LS is not set -# CONFIG_NSH_DISABLE_MKDIR is not set -# CONFIG_NSH_DISABLE_MOUNT is not set -# CONFIG_NSH_DISABLE_PS is not set -# CONFIG_NSH_DISABLE_PUT is not set -# CONFIG_NSH_DISABLE_PWD is not set -# CONFIG_NSH_DISABLE_RM is not set -# CONFIG_NSH_DISABLE_SLEEP is not set -# CONFIG_NSH_DISABLE_TEST is not set -# CONFIG_NSH_DISABLE_UMOUNT is not set -# CONFIG_NSH_DISABLE_UNAME is not set -# CONFIG_NSH_DISABLE_WGET is not set -# CONFIG_NSH_DISABLE_XD is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f103-minimum" -CONFIG_ARCH_BOARD_COMMON=y -CONFIG_ARCH_BOARD_STM32F103_MINIMUM=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F103C8=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=5483 -CONFIG_BUILTIN=y -CONFIG_DEFAULT_SMALL=y -CONFIG_DRIVERS_VIDEO=y -CONFIG_EXAMPLES_FB=y -CONFIG_FILE_STREAM=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_LCD=y -CONFIG_LCD_FRAMEBUFFER=y -CONFIG_LCD_SSD1306_I2C=y -CONFIG_LCD_UG2864HSWEG01=y -CONFIG_LINE_MAX=80 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=1024 -CONFIG_RAM_SIZE=20480 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_HPWORKPRIORITY=192 -CONFIG_SCHED_WAITPID=y -CONFIG_SERIAL_TERMIOS=y -CONFIG_START_DAY=5 -CONFIG_START_MONTH=7 -CONFIG_START_YEAR=2011 -CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32_I2C1=y -CONFIG_STM32_JTAG_FULL_ENABLE=y -CONFIG_STM32_USART1=y -CONFIG_SYMTAB_ORDEREDBYNAME=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART1_SERIAL_CONSOLE=y -CONFIG_VIDEO_FB=y diff --git a/boards/arm/stm32/stm32f103-minimum/configs/usbnsh/defconfig b/boards/arm/stm32/stm32f103-minimum/configs/usbnsh/defconfig deleted file mode 100644 index a633b57853733..0000000000000 --- a/boards/arm/stm32/stm32f103-minimum/configs/usbnsh/defconfig +++ /dev/null @@ -1,55 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_DEV_CONSOLE is not set -# CONFIG_DISABLE_OS_API is not set -# CONFIG_NSH_DISABLEBG is not set -# CONFIG_NSH_DISABLESCRIPT is not set -# CONFIG_NSH_DISABLE_EXEC is not set -# CONFIG_NSH_DISABLE_EXIT is not set -# CONFIG_NSH_DISABLE_GET is not set -# CONFIG_NSH_DISABLE_HEXDUMP is not set -# CONFIG_NSH_DISABLE_MKRD is not set -# CONFIG_NSH_DISABLE_PS is not set -# CONFIG_NSH_DISABLE_PUT is not set -# CONFIG_NSH_DISABLE_WGET is not set -# CONFIG_NSH_DISABLE_XD is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f103-minimum" -CONFIG_ARCH_BOARD_STM32F103_MINIMUM=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F103C8=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARDCTL_USBDEVCTRL=y -CONFIG_BOARD_LOOPSPERMSEC=5483 -CONFIG_BUILTIN=y -CONFIG_CDCACM=y -CONFIG_CDCACM_CONSOLE=y -CONFIG_CDCACM_RXBUFSIZE=256 -CONFIG_CDCACM_TXBUFSIZE=256 -CONFIG_DEFAULT_SMALL=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_LINE_MAX=80 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=1024 -CONFIG_RAM_SIZE=20480 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=5 -CONFIG_START_MONTH=7 -CONFIG_START_YEAR=2011 -CONFIG_STM32_JTAG_FULL_ENABLE=y -CONFIG_STM32_USART1=y -CONFIG_STM32_USB=y -CONFIG_SYMTAB_ORDEREDBYNAME=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USBDEV_TRACE=y -CONFIG_USBDEV_TRACE_NRECORDS=32 diff --git a/boards/arm/stm32/stm32f103-minimum/configs/userled/defconfig b/boards/arm/stm32/stm32f103-minimum/configs/userled/defconfig deleted file mode 100644 index 931b29c9dede6..0000000000000 --- a/boards/arm/stm32/stm32f103-minimum/configs/userled/defconfig +++ /dev/null @@ -1,56 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_LEDS is not set -# CONFIG_DISABLE_OS_API is not set -# CONFIG_NSH_DISABLESCRIPT is not set -# CONFIG_NSH_DISABLE_EXEC is not set -# CONFIG_NSH_DISABLE_EXIT is not set -# CONFIG_NSH_DISABLE_GET is not set -# CONFIG_NSH_DISABLE_HEXDUMP is not set -# CONFIG_NSH_DISABLE_MKRD is not set -# CONFIG_NSH_DISABLE_PS is not set -# CONFIG_NSH_DISABLE_PUT is not set -# CONFIG_NSH_DISABLE_WGET is not set -# CONFIG_NSH_DISABLE_XD is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f103-minimum" -CONFIG_ARCH_BOARD_STM32F103_MINIMUM=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F103C8=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=5483 -CONFIG_BUILTIN=y -CONFIG_DEFAULT_SMALL=y -CONFIG_ENABLE_ALL_SIGNALS=y -CONFIG_EXAMPLES_LEDS=y -CONFIG_FILE_STREAM=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_LINE_MAX=80 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=1024 -CONFIG_RAM_SIZE=20480 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_HPWORKPRIORITY=192 -CONFIG_SCHED_WAITPID=y -CONFIG_SERIAL_TERMIOS=y -CONFIG_START_DAY=5 -CONFIG_START_MONTH=7 -CONFIG_START_YEAR=2011 -CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_USART1=y -CONFIG_SYMTAB_ORDEREDBYNAME=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART1_SERIAL_CONSOLE=y -CONFIG_USERLED=y -CONFIG_USERLED_LOWER=y diff --git a/boards/arm/stm32/stm32f103-minimum/configs/veml6070/defconfig b/boards/arm/stm32/stm32f103-minimum/configs/veml6070/defconfig deleted file mode 100644 index 3f439883df67f..0000000000000 --- a/boards/arm/stm32/stm32f103-minimum/configs/veml6070/defconfig +++ /dev/null @@ -1,54 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_DISABLE_OS_API is not set -# CONFIG_NSH_DISABLESCRIPT is not set -# CONFIG_NSH_DISABLE_EXEC is not set -# CONFIG_NSH_DISABLE_EXIT is not set -# CONFIG_NSH_DISABLE_GET is not set -# CONFIG_NSH_DISABLE_HEXDUMP is not set -# CONFIG_NSH_DISABLE_MKRD is not set -# CONFIG_NSH_DISABLE_PS is not set -# CONFIG_NSH_DISABLE_PUT is not set -# CONFIG_NSH_DISABLE_WGET is not set -# CONFIG_NSH_DISABLE_XD is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f103-minimum" -CONFIG_ARCH_BOARD_COMMON=y -CONFIG_ARCH_BOARD_STM32F103_MINIMUM=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F103C8=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=5483 -CONFIG_BUILTIN=y -CONFIG_DEFAULT_SMALL=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_LINE_MAX=80 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=1024 -CONFIG_RAM_SIZE=20480 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_HPWORKPRIORITY=192 -CONFIG_SCHED_WAITPID=y -CONFIG_SENSORS=y -CONFIG_SENSORS_VEML6070=y -CONFIG_SERIAL_TERMIOS=y -CONFIG_START_DAY=5 -CONFIG_START_MONTH=7 -CONFIG_START_YEAR=2011 -CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32_I2C1=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_USART1=y -CONFIG_SYMTAB_ORDEREDBYNAME=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/stm32f103-minimum/include/board.h b/boards/arm/stm32/stm32f103-minimum/include/board.h deleted file mode 100644 index 36ed8ae7f6979..0000000000000 --- a/boards/arm/stm32/stm32f103-minimum/include/board.h +++ /dev/null @@ -1,321 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f103-minimum/include/board.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __BOARDS_ARM_STM32_STM32F103_MINIMUM_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32_STM32F103_MINIMUM_INCLUDE_BOARD_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#ifndef __ASSEMBLY__ -# include -#endif - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Clocking *****************************************************************/ - -/* On-board crystal frequency is 8MHz (HSE) */ - -#define STM32_BOARD_XTAL 8000000ul - -/* PLL source is HSE/1, PLL multiplier is 9: PLL frequency is - * 8MHz (XTAL) x 9 = 72MHz - */ - -#define STM32_CFGR_PLLSRC RCC_CFGR_PLLSRC -#define STM32_CFGR_PLLXTPRE 0 -#define STM32_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx9 -#define STM32_PLL_FREQUENCY (9*STM32_BOARD_XTAL) - -/* Use the PLL and set the SYSCLK source to be the PLL */ - -#define STM32_SYSCLK_SW RCC_CFGR_SW_PLL -#define STM32_SYSCLK_SWS RCC_CFGR_SWS_PLL -#define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY - -/* AHB clock (HCLK) is SYSCLK (72MHz) */ - -#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK -#define STM32_HCLK_FREQUENCY STM32_PLL_FREQUENCY - -/* APB2 clock (PCLK2) is HCLK (72MHz) */ - -#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK -#define STM32_PCLK2_FREQUENCY STM32_HCLK_FREQUENCY - -/* APB2 timers 1 and 8 will receive PCLK2. */ - -#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) - -/* APB1 clock (PCLK1) is HCLK/2 (36MHz) */ - -#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd2 -#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/2) - -/* APB1 timers 2-7 will be twice PCLK1 */ - -#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) - -/* USB divider -- Divide PLL clock by 1.5 */ - -#define STM32_CFGR_USBPRE 0 - -/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx - * otherwise frequency is 2xAPBx. - * Note: TIM1,8 are on APB2, others on APB1 - */ - -#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM2_FREQUENCY STM32_PCLK1_FREQUENCY -#define BOARD_TIM3_FREQUENCY STM32_PCLK1_FREQUENCY -#define BOARD_TIM4_FREQUENCY STM32_PCLK1_FREQUENCY -#define BOARD_TIM5_FREQUENCY STM32_PCLK1_FREQUENCY -#define BOARD_TIM6_FREQUENCY STM32_PCLK1_FREQUENCY -#define BOARD_TIM7_FREQUENCY STM32_PCLK1_FREQUENCY -#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY - -/* SDIO dividers. Note that slower clocking is required when DMA is disabled - * in order to avoid RX overrun/TX underrun errors due to delayed responses - * to service FIFOs in interrupt driven mode. These values have not been - * tuned!!! - * - * HCLK=72MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(178+2)=400 KHz - */ - -#define SDIO_INIT_CLKDIV (178 << SDIO_CLKCR_CLKDIV_SHIFT) - -/* DMA ON: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(2+2)=18 MHz - * DMA OFF: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(3+2)=14.4 MHz - */ - -#ifdef CONFIG_SDIO_DMA -# define SDIO_MMCXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT) -#else -# define SDIO_MMCXFR_CLKDIV (3 << SDIO_CLKCR_CLKDIV_SHIFT) -#endif - -/* DMA ON: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(1+2)=24 MHz - * DMA OFF: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(3+2)=14.4 MHz - */ - -#ifdef CONFIG_SDIO_DMA -# define SDIO_SDXFR_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT) -#else -# define SDIO_SDXFR_CLKDIV (3 << SDIO_CLKCR_CLKDIV_SHIFT) -#endif - -/* BUTTON definitions *******************************************************/ - -#define NUM_BUTTONS 2 - -#define BUTTON_USER1 0 -#define BUTTON_USER2 1 -#define BUTTON_USER1_BIT (1 << BUTTON_USER1) -#define BUTTON_USER2_BIT (1 << BUTTON_USER2) - -/* LED definitions **********************************************************/ - -/* Define how many LEDs this board has (needed by userleds) */ - -#define BOARD_NLEDS 1 - -/* The board has only one controllable LED */ - -#define LED_STARTED 0 /* No LEDs */ -#define LED_HEAPALLOCATE 1 /* LED1 on */ -#define LED_IRQSENABLED 2 /* LED2 on */ -#define LED_STACKCREATED 3 /* LED1 on */ -#define LED_INIRQ 4 /* LED1 off */ -#define LED_SIGNAL 5 /* LED2 on */ -#define LED_ASSERTION 6 /* LED1 + LED2 */ -#define LED_PANIC 7 /* LED1 / LED2 blinking */ - -/* PWM - * - * The STM32F103-Minimum has no real on-board PWM devices, but the board can - * be configured to output a pulse train using TIM3 CH3 on PB0. - * - * Note: we don't need redefine GPIO_TIM3_CH3OUT because PB0 is not - * remap pin. - */ - -/* RGB LED - * - * R = TIM1 CH1 on PA8 | G = TIM2 CH2 on PA1 | B = TIM4 CH4 on PB9 - * - * Note: Pin boards: GPIO_TIM1_CH1OUT ; GPIO_TIM2_CH2OUT ; GPIO_TIM4_CH4OUT - */ - -#define RGBLED_RPWMTIMER 1 -#define RGBLED_RPWMCHANNEL 1 -#define RGBLED_GPWMTIMER 2 -#define RGBLED_GPWMCHANNEL 2 -#define RGBLED_BPWMTIMER 4 -#define RGBLED_BPWMCHANNEL 4 - -/* Tone Driver **************************************************************/ - -#define BOARD_TONE_PWM_TIM 2 /* PWM timer for tone generation */ -#define BOARD_TONE_PWM_CHANNEL 2 /* PWM channel for tone generation */ -#define BOARD_TONE_ONESHOT_TIM 3 /* Oneshot timer for note timings */ -#define BOARD_TONE_ONESHOT_TIM_RES 10 /* Oneshot timer resolution (us) */ - -/* NRF24L01 Driver **********************************************************/ - -/* Chip enable: PB.1 */ - -#define GPIO_NRF24L01_CE (GPIO_OUTPUT|GPIO_CNF_OUTPP|GPIO_MODE_50MHz|\ - GPIO_OUTPUT_CLEAR|GPIO_PORTB|GPIO_PIN1) - -/* IRQ line: PA.0 */ - -#define GPIO_NRF24L01_IRQ (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_PORTA|GPIO_PIN0) - -#define BOARD_NRF24L01_GPIO_CE GPIO_NRF24L01_CE -#define BOARD_NRF24L01_GPIO_IRQ GPIO_NRF24L01_IRQ - -/* HCSR04 driver */ - -/* Pins config to use with HC-SR04 sensor */ - -#define GPIO_HCSR04_INT (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_PORTA|GPIO_PIN0) -#define GPIO_HCSR04_TRIG (GPIO_OUTPUT|GPIO_CNF_OUTPP|GPIO_MODE_50MHz|\ - GPIO_OUTPUT_CLEAR|GPIO_PORTA|GPIO_PIN1) - -#define BOARD_HCSR04_GPIO_INT GPIO_HCSR04_INT -#define BOARD_HCSR04_GPIO_TRIG GPIO_HCSR04_TRIG -#define BOARD_HCSR04_FRTIMER 1 /* TIM1 as free running timer */ - -/* Pin for APDS-9960 sensor */ - -#define GPIO_APDS9960_INT (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_PORTA|GPIO_PIN0) - -#define BOARD_APDS9960_GPIO_INT GPIO_APDS9960_INT - -/* ZERO CROSS pin definition */ - -#define BOARD_ZEROCROSS_GPIO \ - (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_PORTA|GPIO_PIN0) - -/* Alternate function pin selections (auto-aliased for new pinmap) */ - -/* USART1 */ - -#define GPIO_USART1_TX GPIO_ADJUST_MODE(GPIO_USART1_TX_0, GPIO_MODE_50MHz) -#define GPIO_USART1_RX GPIO_USART1_RX_0 - -/* USART2 */ - -#define GPIO_USART2_TX GPIO_ADJUST_MODE(GPIO_USART2_TX_0, GPIO_MODE_50MHz) -#define GPIO_USART2_RX GPIO_USART2_RX_0 -#define GPIO_USART2_CTS GPIO_USART2_CTS_0 -#define GPIO_USART2_RTS GPIO_ADJUST_MODE(GPIO_USART2_RTS_0, GPIO_MODE_50MHz) -#define GPIO_USART2_CK GPIO_ADJUST_MODE(GPIO_USART2_CK_0, GPIO_MODE_50MHz) - -/* SPI1 */ - -#define GPIO_SPI1_NSS GPIO_ADJUST_MODE(GPIO_SPI1_NSS_0, GPIO_MODE_50MHz) -#define GPIO_SPI1_SCK GPIO_ADJUST_MODE(GPIO_SPI1_SCK_0, GPIO_MODE_50MHz) -#define GPIO_SPI1_MISO GPIO_ADJUST_MODE(GPIO_SPI1_MISO_0, GPIO_MODE_50MHz) -#define GPIO_SPI1_MOSI GPIO_ADJUST_MODE(GPIO_SPI1_MOSI_0, GPIO_MODE_50MHz) - -/* I2C1 */ - -#define GPIO_I2C1_SCL GPIO_ADJUST_MODE(GPIO_I2C1_SCL_0, GPIO_MODE_50MHz) -#define GPIO_I2C1_SDA GPIO_ADJUST_MODE(GPIO_I2C1_SDA_0, GPIO_MODE_50MHz) - -/* I2C2 */ - -#define GPIO_I2C2_SCL GPIO_ADJUST_MODE(GPIO_I2C2_SCL_0, GPIO_MODE_50MHz) -#define GPIO_I2C2_SDA GPIO_ADJUST_MODE(GPIO_I2C2_SDA_0, GPIO_MODE_50MHz) - -/* CAN1 */ - -#define GPIO_CAN1_RX GPIO_CAN1_RX_0 -#define GPIO_CAN1_TX GPIO_ADJUST_MODE(GPIO_CAN1_TX_0, GPIO_MODE_50MHz) - -/* USB */ - -#define GPIO_USB_DM GPIO_USB_DM_0 -#define GPIO_USB_DP GPIO_USB_DP_0 - -/* TIM1 */ - -#define GPIO_TIM1_CH1IN GPIO_TIM1_CH1IN_0 -#define GPIO_TIM1_CH1OUT GPIO_ADJUST_MODE(GPIO_TIM1_CH1OUT_0, GPIO_MODE_50MHz) -#define GPIO_TIM1_CH2IN GPIO_TIM1_CH2IN_0 -#define GPIO_TIM1_CH2OUT GPIO_ADJUST_MODE(GPIO_TIM1_CH2OUT_0, GPIO_MODE_50MHz) -#define GPIO_TIM1_CH3IN GPIO_TIM1_CH3IN_0 -#define GPIO_TIM1_CH3OUT GPIO_ADJUST_MODE(GPIO_TIM1_CH3OUT_0, GPIO_MODE_50MHz) -#define GPIO_TIM1_CH4IN GPIO_TIM1_CH4IN_0 -#define GPIO_TIM1_CH4OUT GPIO_ADJUST_MODE(GPIO_TIM1_CH4OUT_0, GPIO_MODE_50MHz) -#define GPIO_TIM1_BKIN GPIO_TIM1_BKIN_0 -#define GPIO_TIM1_ETR GPIO_TIM1_ETR_0 -#define GPIO_TIM1_CH1NOUT GPIO_ADJUST_MODE(GPIO_TIM1_CH1NOUT_0, GPIO_MODE_50MHz) -#define GPIO_TIM1_CH2NOUT GPIO_ADJUST_MODE(GPIO_TIM1_CH2NOUT_0, GPIO_MODE_50MHz) -#define GPIO_TIM1_CH3NOUT GPIO_ADJUST_MODE(GPIO_TIM1_CH3NOUT_0, GPIO_MODE_50MHz) - -/* TIM2 */ - -#define GPIO_TIM2_CH1IN GPIO_TIM2_CH1IN_0 -#define GPIO_TIM2_CH1OUT GPIO_ADJUST_MODE(GPIO_TIM2_CH1OUT_0, GPIO_MODE_50MHz) -#define GPIO_TIM2_CH2IN GPIO_TIM2_CH2IN_0 -#define GPIO_TIM2_CH2OUT GPIO_ADJUST_MODE(GPIO_TIM2_CH2OUT_0, GPIO_MODE_50MHz) -#define GPIO_TIM2_CH3IN GPIO_TIM2_CH3IN_0 -#define GPIO_TIM2_CH3OUT GPIO_ADJUST_MODE(GPIO_TIM2_CH3OUT_0, GPIO_MODE_50MHz) -#define GPIO_TIM2_CH4IN GPIO_TIM2_CH4IN_0 -#define GPIO_TIM2_CH4OUT GPIO_ADJUST_MODE(GPIO_TIM2_CH4OUT_0, GPIO_MODE_50MHz) - -/* TIM3 */ - -#define GPIO_TIM3_CH1IN GPIO_TIM3_CH1IN_0 -#define GPIO_TIM3_CH1OUT GPIO_ADJUST_MODE(GPIO_TIM3_CH1OUT_0, GPIO_MODE_50MHz) -#define GPIO_TIM3_CH2IN GPIO_TIM3_CH2IN_0 -#define GPIO_TIM3_CH2OUT GPIO_ADJUST_MODE(GPIO_TIM3_CH2OUT_0, GPIO_MODE_50MHz) -#define GPIO_TIM3_CH3IN GPIO_TIM3_CH3IN_0 -#define GPIO_TIM3_CH3OUT GPIO_ADJUST_MODE(GPIO_TIM3_CH3OUT_0, GPIO_MODE_50MHz) -#define GPIO_TIM3_CH4IN GPIO_TIM3_CH4IN_0 -#define GPIO_TIM3_CH4OUT GPIO_ADJUST_MODE(GPIO_TIM3_CH4OUT_0, GPIO_MODE_50MHz) - -/* TIM4 */ - -#define GPIO_TIM4_CH1IN GPIO_TIM4_CH1IN_0 -#define GPIO_TIM4_CH1OUT GPIO_ADJUST_MODE(GPIO_TIM4_CH1OUT_0, GPIO_MODE_50MHz) -#define GPIO_TIM4_CH2IN GPIO_TIM4_CH2IN_0 -#define GPIO_TIM4_CH2OUT GPIO_ADJUST_MODE(GPIO_TIM4_CH2OUT_0, GPIO_MODE_50MHz) -#define GPIO_TIM4_CH3IN GPIO_TIM4_CH3IN_0 -#define GPIO_TIM4_CH3OUT GPIO_ADJUST_MODE(GPIO_TIM4_CH3OUT_0, GPIO_MODE_50MHz) -#define GPIO_TIM4_CH4IN GPIO_TIM4_CH4IN_0 -#define GPIO_TIM4_CH4OUT GPIO_ADJUST_MODE(GPIO_TIM4_CH4OUT_0, GPIO_MODE_50MHz) - -#endif /* __BOARDS_ARM_STM32_STM32F103_MINIMUM_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32/stm32f103-minimum/scripts/Make.defs b/boards/arm/stm32/stm32f103-minimum/scripts/Make.defs deleted file mode 100644 index 6d4f1b4b8c916..0000000000000 --- a/boards/arm/stm32/stm32f103-minimum/scripts/Make.defs +++ /dev/null @@ -1,46 +0,0 @@ -############################################################################ -# boards/arm/stm32/stm32f103-minimum/scripts/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/.config -include $(TOPDIR)/tools/Config.mk -include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs - -ifeq ($(CONFIG_STM32_DFU),y) - LDSCRIPT = ld.script.dfu -else - LDSCRIPT = ld.script -endif - -ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) - -ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 - -CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) -CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) -CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -AFLAGS := $(CFLAGS) -D__ASSEMBLY__ - -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections -LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32/stm32f103-minimum/scripts/ld.script b/boards/arm/stm32/stm32f103-minimum/scripts/ld.script deleted file mode 100644 index 38b17fb89158d..0000000000000 --- a/boards/arm/stm32/stm32f103-minimum/scripts/ld.script +++ /dev/null @@ -1,127 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f103-minimum/scripts/ld.script - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* The STM32F103C8T6 has 64Kb of FLASH beginning at address 0x0800:0000 and - * 20Kb of SRAM beginning at address 0x2000:0000. When booting from FLASH, - * FLASH memory is aliased to address 0x0000:0000 where the code expects to - * begin execution by jumping to the entry point in the 0x0800:0000 address - * range. - * - * NOTE: While the STM32F103C8T6 states that the part has 64Kb of FLASH, - * all parts that I have seen do, in fact, have 128Kb of FLASH. That - * additional 64Kb of FLASH can be utilized by simply change the LENGTH - * of the flash region from 64K to 128K. - */ - -MEMORY -{ - flash (rx) : ORIGIN = 0x08000000, LENGTH = 128K - sram (rwx) : ORIGIN = 0x20000000, LENGTH = 20K -} - -OUTPUT_ARCH(arm) -EXTERN(_vectors) -ENTRY(_stext) -SECTIONS -{ - .text : { - _stext = ABSOLUTE(.); - *(.vectors) - *(.text .text.*) - *(.fixup) - *(.gnu.warning) - *(.rodata .rodata.*) - *(.gnu.linkonce.t.*) - *(.glue_7) - *(.glue_7t) - *(.got) - *(.gcc_except_table) - *(.gnu.linkonce.r.*) - _etext = ABSOLUTE(.); - } > flash - - .init_section : ALIGN(4) { - _sinit = ABSOLUTE(.); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) - KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) - _einit = ABSOLUTE(.); - } > flash - - .ARM.extab : ALIGN(4) { - *(.ARM.extab*) - } > flash - - .ARM.exidx : ALIGN(4) { - __exidx_start = ABSOLUTE(.); - *(.ARM.exidx*) - __exidx_end = ABSOLUTE(.); - } > flash - - .tdata : { - _stdata = ABSOLUTE(.); - *(.tdata .tdata.* .gnu.linkonce.td.*); - _etdata = ABSOLUTE(.); - } > flash - - .tbss : { - _stbss = ABSOLUTE(.); - *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); - _etbss = ABSOLUTE(.); - } > flash - - _eronly = LOADADDR(.data); - - /* The STM32F103C8T6 has 20Kb of SRAM beginning at the following address */ - - .data : ALIGN(4) { - _sdata = ABSOLUTE(.); - *(.data .data.*) - *(.gnu.linkonce.d.*) - CONSTRUCTORS - . = ALIGN(4); - _edata = ABSOLUTE(.); - } > sram AT > flash - - .bss : ALIGN(4) { - _sbss = ABSOLUTE(.); - *(.bss .bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - . = ALIGN(4); - _ebss = ABSOLUTE(.); - } > sram - - /* Stabs debugging sections. */ - - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_info 0 : { *(.debug_info) } - .debug_line 0 : { *(.debug_line) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_aranges 0 : { *(.debug_aranges) } -} diff --git a/boards/arm/stm32/stm32f103-minimum/scripts/ld.script.dfu b/boards/arm/stm32/stm32f103-minimum/scripts/ld.script.dfu deleted file mode 100644 index e9a9a6b75d242..0000000000000 --- a/boards/arm/stm32/stm32f103-minimum/scripts/ld.script.dfu +++ /dev/null @@ -1,118 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f103-minimum/scripts/ld.script.dfu - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* The STM32F103C8T6 has 64Kb of FLASH beginning at address 0x0800:0000 and - * 20Kb of SRAM beginning at address 0x2000:0000. Here we assume that the - * STM32duino bootloader is being used. In that case, the correct load .text - * address is 0x0800:2000 (leaving 56Kb). - */ - -MEMORY -{ - flash (rx) : ORIGIN = 0x08002000, LENGTH = 120K - sram (rwx) : ORIGIN = 0x20000000, LENGTH = 20K -} - -OUTPUT_ARCH(arm) -EXTERN(_vectors) -ENTRY(_stext) -SECTIONS -{ - .text : { - _stext = ABSOLUTE(.); - *(.vectors) - *(.text .text.*) - *(.fixup) - *(.gnu.warning) - *(.rodata .rodata.*) - *(.gnu.linkonce.t.*) - *(.glue_7) - *(.glue_7t) - *(.got) - *(.gcc_except_table) - *(.gnu.linkonce.r.*) - _etext = ABSOLUTE(.); - } > flash - - .init_section : ALIGN(4) { - _sinit = ABSOLUTE(.); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) - KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) - _einit = ABSOLUTE(.); - } > flash - - .ARM.extab : ALIGN(4) { - *(.ARM.extab*) - } > flash - - .ARM.exidx : ALIGN(4) { - __exidx_start = ABSOLUTE(.); - *(.ARM.exidx*) - __exidx_end = ABSOLUTE(.); - } > flash - - .tdata : { - _stdata = ABSOLUTE(.); - *(.tdata .tdata.* .gnu.linkonce.td.*); - _etdata = ABSOLUTE(.); - } > flash - - .tbss : { - _stbss = ABSOLUTE(.); - *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); - _etbss = ABSOLUTE(.); - } > flash - - _eronly = ABSOLUTE(.); - - /* The STM32F103C8T6 has 20Kb of SRAM beginning at the following address */ - - .data : ALIGN(4) { - _sdata = ABSOLUTE(.); - *(.data .data.*) - *(.gnu.linkonce.d.*) - CONSTRUCTORS - _edata = ABSOLUTE(.); - } > sram AT > flash - - .bss : ALIGN(4) { - _sbss = ABSOLUTE(.); - *(.bss .bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - _ebss = ABSOLUTE(.); - } > sram - - /* Stabs debugging sections. */ - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_info 0 : { *(.debug_info) } - .debug_line 0 : { *(.debug_line) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_aranges 0 : { *(.debug_aranges) } -} diff --git a/boards/arm/stm32/stm32f103-minimum/src/CMakeLists.txt b/boards/arm/stm32/stm32f103-minimum/src/CMakeLists.txt deleted file mode 100644 index 06607962aed7e..0000000000000 --- a/boards/arm/stm32/stm32f103-minimum/src/CMakeLists.txt +++ /dev/null @@ -1,120 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/stm32f103-minimum/src/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -set(SRCS stm32_boot.c stm32_bringup.c stm32_spi.c) - -if(CONFIG_BOARDCTL_RESET) - list(APPEND SRCS stm32_reset.c) -endif() - -if(CONFIG_ARCH_BUTTONS) - list(APPEND SRCS stm32_buttons.c) -endif() - -if(CONFIG_ARCH_LEDS) - list(APPEND SRCS stm32_autoleds.c) -else() - list(APPEND SRCS stm32_userleds.c) -endif() - -if(CONFIG_ADC) - list(APPEND SRCS stm32_adc.c) -endif() - -if(CONFIG_DEV_GPIO) - list(APPEND SRCS stm32_gpio.c) -endif() - -if(CONFIG_PWM) - list(APPEND SRCS stm32_pwm.c) -endif() - -if(CONFIG_SENSORS_HYT271) - list(APPEND SRCS stm32_hyt271.c) -endif() - -if(CONFIG_SENSORS_DS18B20) - list(APPEND SRCS stm32_ds18b20.c) -endif() - -if(CONFIG_RGBLED) - list(APPEND SRCS stm32_rgbled.c) -endif() - -if(CONFIG_MMCSD) - list(APPEND SRCS stm32_mmcsd.c) -endif() - -if(CONFIG_MTD_W25) - list(APPEND SRCS stm32_w25.c) -endif() - -if(CONFIG_MTD_AT24XX) - if(CONFIG_STM32_I2C1) - list(APPEND SRCS stm32_at24.c) - endif() -endif() - -if(CONFIG_CAN_MCP2515) - list(APPEND SRCS stm32_mcp2515.c) -endif() - -if(CONFIG_LCD_MAX7219) - list(APPEND SRCS stm32_max7219.c) -endif() - -if(CONFIG_INPUT_NUNCHUCK) - list(APPEND SRCS stm32_nunchuck.c) -endif() - -if(CONFIG_LCD_SSD1306_I2C) - list(APPEND SRCS stm32_lcd_ssd1306.c) -endif() - -if(CONFIG_LCD_ST7567) - list(APPEND SRCS stm32_lcd_st7567.c) -endif() - -if(CONFIG_LCD_PCD8544) - list(APPEND SRCS stm32_pcd8544.c) -endif() - -if(CONFIG_USBDEV) - list(APPEND SRCS stm32_usbdev.c) -endif() - -if(CONFIG_USBMSC) - list(APPEND SRCS stm32_usbmsc.c) -endif() - -if(CONFIG_STM32_CAN) - if(CONFIG_STM32_CAN_CHARDRIVER) - list(APPEND SRCS stm32_can.c) - endif() - if(CONFIG_STM32_CAN_SOCKET) - list(APPEND SRCS stm32_cansock.c) - endif() -endif() - -target_sources(board PRIVATE ${SRCS}) - -set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/ld.script") diff --git a/boards/arm/stm32/stm32f103-minimum/src/Make.defs b/boards/arm/stm32/stm32f103-minimum/src/Make.defs deleted file mode 100644 index a0fc84fc4eefb..0000000000000 --- a/boards/arm/stm32/stm32f103-minimum/src/Make.defs +++ /dev/null @@ -1,122 +0,0 @@ -############################################################################ -# boards/arm/stm32/stm32f103-minimum/src/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/Make.defs - -CSRCS = stm32_boot.c stm32_bringup.c stm32_spi.c - -ifeq ($(CONFIG_BOARDCTL_RESET),y) - CSRCS += stm32_reset.c -endif - -ifeq ($(CONFIG_ARCH_BUTTONS),y) - CSRCS += stm32_buttons.c -endif - -ifeq ($(CONFIG_ARCH_LEDS),y) - CSRCS += stm32_autoleds.c -else - CSRCS += stm32_userleds.c -endif - -ifeq ($(CONFIG_ADC),y) -CSRCS += stm32_adc.c -endif - -ifeq ($(CONFIG_DEV_GPIO),y) - CSRCS += stm32_gpio.c -endif - -ifeq ($(CONFIG_PWM),y) - CSRCS += stm32_pwm.c -endif - -ifeq ($(CONFIG_SENSORS_HYT271),y) - CSRCS += stm32_hyt271.c -endif - -ifeq ($(CONFIG_SENSORS_DS18B20),y) - CSRCS += stm32_ds18b20.c -endif - -ifeq ($(CONFIG_RGBLED),y) - CSRCS += stm32_rgbled.c -endif - -ifeq ($(CONFIG_MMCSD),y) - CSRCS += stm32_mmcsd.c -endif - -ifeq ($(CONFIG_MTD_W25),y) - CSRCS += stm32_w25.c -endif - -ifeq ($(CONFIG_MTD_AT24XX),y) -ifeq ($(CONFIG_STM32_I2C1),y) -CSRCS += stm32_at24.c -endif -endif - -ifeq ($(CONFIG_CAN_MCP2515),y) - CSRCS += stm32_mcp2515.c -endif - -ifeq ($(CONFIG_LCD_MAX7219),y) - CSRCS += stm32_max7219.c -endif - -ifeq ($(CONFIG_INPUT_NUNCHUCK),y) - CSRCS += stm32_nunchuck.c -endif - -ifeq ($(CONFIG_LCD_SSD1306_I2C),y) -CSRCS += stm32_lcd_ssd1306.c -endif - -ifeq ($(CONFIG_LCD_ST7567),y) - CSRCS += stm32_lcd_st7567.c -endif - -ifeq ($(CONFIG_LCD_PCD8544),y) - CSRCS += stm32_pcd8544.c -endif - -ifeq ($(CONFIG_USBDEV),y) - CSRCS += stm32_usbdev.c -endif - -ifeq ($(CONFIG_USBMSC),y) -CSRCS += stm32_usbmsc.c -endif - -ifeq ($(CONFIG_STM32_CAN),y) -ifeq ($(CONFIG_STM32_CAN_CHARDRIVER),y) -CSRCS += stm32_can.c -endif -ifeq ($(CONFIG_STM32_CAN_SOCKET),y) -CSRCS += stm32_cansock.c -endif -endif - -DEPPATH += --dep-path board -VPATH += :board -CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/stm32f103-minimum/src/stm32_adc.c b/boards/arm/stm32/stm32f103-minimum/src/stm32_adc.c deleted file mode 100644 index 2da9c070aff19..0000000000000 --- a/boards/arm/stm32/stm32f103-minimum/src/stm32_adc.c +++ /dev/null @@ -1,150 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f103-minimum/src/stm32_adc.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include -#include - -#include "chip.h" -#include "stm32_adc.h" -#include "stm32f103_minimum.h" - -#ifdef CONFIG_ADC - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -/* Up to 2 ADC interfaces are supported */ - -#if STM32_NADC < 2 -# undef CONFIG_STM32_ADC2 -#endif - -#if STM32_NADC < 1 -# undef CONFIG_STM32_ADC1 -#endif - -#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) -#ifndef CONFIG_STM32_ADC1 -# warning "Channel information only available for ADC1" -#endif - -/* The number of ADC channels in the conversion list */ - -#define ADC1_NCHANNELS 1 - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* Identifying number of each ADC channel to be used with Variable Resistor - * (Pontentiometer) - */ - -#ifdef CONFIG_STM32_ADC1 -static const uint8_t g_chanlist[ADC1_NCHANNELS] = -{ - 0 -}; /* ADC12_IN0 */ - -/* Configurations of pins used byte each ADC channels */ - -static const uint32_t g_pinlist[ADC1_NCHANNELS] = -{ - GPIO_ADC12_IN0 -}; -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_adc_setup - * - * Description: - * Initialize ADC and register the ADC driver. - * - ****************************************************************************/ - -int stm32_adc_setup(void) -{ -#ifdef CONFIG_STM32_ADC1 - static bool initialized = false; - struct adc_dev_s *adc; - int ret; - int i; - - /* Check if we have already initialized */ - - if (!initialized) - { - /* Configure the pins as analog inputs for the selected channels */ - - for (i = 0; i < ADC1_NCHANNELS; i++) - { - stm32_configgpio(g_pinlist[i]); - } - - /* Call stm32_adcinitialize() to get an instance of the ADC interface */ - - adc = stm32_adcinitialize(1, g_chanlist, ADC1_NCHANNELS); - if (adc == NULL) - { - aerr("ERROR: Failed to get ADC interface\n"); - return -ENODEV; - } - - /* Register the ADC driver at "/dev/adc0" */ - - ret = adc_register("/dev/adc0", adc); - if (ret < 0) - { - aerr("ERROR: adc_register failed: %d\n", ret); - return ret; - } - - /* Now we are initialized */ - - initialized = true; - } - - return OK; -#else - return -ENOSYS; -#endif -} - -#endif /* CONFIG_STM32_ADC1 || CONFIG_STM32_ADC2 || CONFIG_STM32_ADC3 */ -#endif /* CONFIG_ADC */ diff --git a/boards/arm/stm32/stm32f103-minimum/src/stm32_at24.c b/boards/arm/stm32/stm32f103-minimum/src/stm32_at24.c deleted file mode 100644 index 0204fcfa0de6f..0000000000000 --- a/boards/arm/stm32/stm32f103-minimum/src/stm32_at24.c +++ /dev/null @@ -1,135 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f103-minimum/src/stm32_at24.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include - -#include -#include -#include -#include - -#include "stm32_i2c.h" -#include "stm32f103_minimum.h" - -#ifdef HAVE_AT24 - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_at24_automount - * - * Description: - * Initialize and configure the AT24 serial EEPROM - * - ****************************************************************************/ - -int stm32_at24_automount(int minor) -{ - struct i2c_master_s *i2c; - struct mtd_dev_s *mtd; - static bool initialized = false; - int ret; - - /* Have we already initialized? */ - - if (!initialized) - { - /* No.. Get the I2C bus driver */ - - finfo("Initialize I2C%d\n", AT24_I2C_BUS); - i2c = stm32_i2cbus_initialize(AT24_I2C_BUS); - if (!i2c) - { - ferr("ERROR: Failed to initialize I2C%d\n", AT24_I2C_BUS); - return -ENODEV; - } - - /* Now bind the I2C interface to the AT24 I2C EEPROM driver */ - - finfo("Bind the AT24 EEPROM driver to I2C%d\n", AT24_I2C_BUS); - mtd = at24c_initialize(i2c); - if (!mtd) - { - ferr("ERROR: Failed to bind TWI%d to the AT24 EEPROM driver\n", - AT24_I2C_BUS); - return -ENODEV; - } - -#if defined(CONFIG_STM32F103MINIMUM_AT24_FTL) - /* Register the MTD driver */ - - char path[32]; - snprintf(path, sizeof(path), "/dev/mtdblock%d", AT24_MINOR); - ret = register_mtddriver(path, mtd, 0755, NULL); - if (ret < 0) - { - ferr("ERROR: Failed to register the MTD driver %s, ret %d\n", - path, ret); - return ret; - } - -#elif defined(CONFIG_STM32F103MINIMUM_AT24_NXFFS) - /* Initialize to provide NXFFS on the MTD interface */ - - finfo("Initialize the NXFFS file system\n"); - ret = nxffs_initialize(mtd); - if (ret < 0) - { - ferr("ERROR: NXFFS initialization failed: %d\n", ret); - return ret; - } - - /* Mount the file system at /mnt/at24 */ - - finfo("Mount the NXFFS file system at /dev/at24\n"); - ret = nx_mount(NULL, "/mnt/at24", "nxffs", 0, NULL); - if (ret < 0) - { - ferr("ERROR: Failed to mount the NXFFS volume: %d\n", ret); - return ret; - } -#endif - - /* Now we are initialized */ - - initialized = true; - } - - return OK; -} - -#endif /* HAVE_AT24 */ diff --git a/boards/arm/stm32/stm32f103-minimum/src/stm32_autoleds.c b/boards/arm/stm32/stm32f103-minimum/src/stm32_autoleds.c deleted file mode 100644 index 5a352af6e54cd..0000000000000 --- a/boards/arm/stm32/stm32f103-minimum/src/stm32_autoleds.c +++ /dev/null @@ -1,113 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f103-minimum/src/stm32_autoleds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32.h" -#include "stm32f103_minimum.h" - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -static inline void set_led(bool v) -{ - ledinfo("Turn LED %s\n", v? "on":"off"); - stm32_gpiowrite(GPIO_LED1, !v); -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_autoled_initialize - ****************************************************************************/ - -#ifdef CONFIG_ARCH_LEDS -void board_autoled_initialize(void) -{ - /* Configure LED GPIO for output */ - - stm32_configgpio(GPIO_LED1); -} - -/**************************************************************************** - * Name: board_autoled_on - ****************************************************************************/ - -void board_autoled_on(int led) -{ - ledinfo("board_autoled_on(%d)\n", led); - - switch (led) - { - case LED_STARTED: - case LED_HEAPALLOCATE: - - /* As the board provides only one soft controllable LED, we simply - * turn it on when the board boots. - */ - - set_led(true); - break; - - case LED_PANIC: - - /* For panic state, the LED is blinking */ - - set_led(true); - break; - } -} - -/**************************************************************************** - * Name: board_autoled_off - ****************************************************************************/ - -void board_autoled_off(int led) -{ - switch (led) - { - case LED_PANIC: - - /* For panic state, the LED is blinking */ - - set_led(false); - break; - } -} - -#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/stm32f103-minimum/src/stm32_boot.c b/boards/arm/stm32/stm32f103-minimum/src/stm32_boot.c deleted file mode 100644 index 0f4f0c9e0a520..0000000000000 --- a/boards/arm/stm32/stm32f103-minimum/src/stm32_boot.c +++ /dev/null @@ -1,101 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f103-minimum/src/stm32_boot.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include -#include - -#include -#include - -#include "arm_internal.h" -#include "stm32f103_minimum.h" - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_boardinitialize - * - * Description: - * All STM32 architectures must provide the following entry point. This - * entry point is called early in the initialization -- after all memory - * has been configured and mapped but before any devices have been - * initialized. - * - ****************************************************************************/ - -void stm32_boardinitialize(void) -{ - /* Configure on-board LEDs if LED support has been selected. */ - -#ifdef CONFIG_ARCH_LEDS - board_autoled_initialize(); -#endif - - /* Configure SPI chip selects if - * 1) SPI is not disabled, and - * 2) the weak function stm32_spidev_initialize() has been brought into - * the link. - */ - -#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) - stm32_spidev_initialize(); -#endif - - /* Initialize USB is - * 1) USBDEV is selected, - * 2) the USB controller is not disabled, and - * 3) the weak function stm32_usbinitialize() has been brought - * into the build. - */ - -#if defined(CONFIG_USBDEV) && defined(CONFIG_STM32_USB) - stm32_usbinitialize(); -#endif -} - -/**************************************************************************** - * Name: board_late_initialize - * - * Description: - * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional - * initialization call will be performed in the boot-up sequence to a - * function called board_late_initialize(). board_late_initialize() - * will be called immediately after up_initialize() is called and just - * before the initial application is started. This additional - * initialization phase may be used, for example, to initialize - * board-specific device drivers. - * - ****************************************************************************/ - -#ifdef CONFIG_BOARD_LATE_INITIALIZE -void board_late_initialize(void) -{ - stm32_bringup(); -} -#endif diff --git a/boards/arm/stm32/stm32f103-minimum/src/stm32_bringup.c b/boards/arm/stm32/stm32f103-minimum/src/stm32_bringup.c deleted file mode 100644 index 518bffcec4a06..0000000000000 --- a/boards/arm/stm32/stm32f103-minimum/src/stm32_bringup.c +++ /dev/null @@ -1,603 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f103-minimum/src/stm32_bringup.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include - -#include -#include -#include - -#ifdef CONFIG_USBMONITOR -# include -#endif - -#include "stm32.h" - -#ifdef CONFIG_STM32_OTGFS -# include "stm32_usbhost.h" -#endif - -#ifdef CONFIG_INPUT_BUTTONS -# include -#endif - -#ifdef CONFIG_USERLED -# include -#endif - -#ifdef CONFIG_VIDEO_FB -# include -#endif - -#ifdef CONFIG_CL_MFRC522 -#include "stm32_mfrc522.h" -#endif - -#include "stm32f103_minimum.h" - -/* Conditional logic in stm32f103_minimum.h will determine if certain - * features are supported. Tests for these features need to be made after - * including stm32f103_minimum.h. - */ - -#ifdef HAVE_RTC_DRIVER -# include -# include "stm32_rtc.h" -#endif - -/* The following are includes from board-common logic */ - -#ifdef CONFIG_SENSORS_BMP180 -#include "stm32_bmp180.h" -#endif - -#ifdef CONFIG_LEDS_APA102 -#include "stm32_apa102.h" -#endif - -#ifdef CONFIG_WS2812 -#include "stm32_ws2812.h" -#endif - -#ifdef CONFIG_SENSORS_MAX6675 -#include "stm32_max6675.h" -#endif - -#ifdef CONFIG_SENSORS_VEML6070 -#include "stm32_veml6070.h" -#endif - -#ifdef CONFIG_INPUT_NUNCHUCK -#include "stm32_nunchuck.h" -#endif - -#ifdef CONFIG_AUDIO_TONE -#include "stm32_tone.h" -#endif - -#ifdef CONFIG_SENSORS_LM75 -#include "stm32_lm75.h" -#endif - -#ifdef CONFIG_WL_NRF24L01 -#include "stm32_nrf24l01.h" -#endif - -#ifdef CONFIG_SENSORS_HCSR04 -#include "stm32_hcsr04.h" -#endif - -#ifdef CONFIG_SENSORS_APDS9960 -#include "stm32_apds9960.h" -#endif - -#ifdef CONFIG_SENSORS_ZEROCROSS -#include "stm32_zerocross.h" -#endif - -#ifdef CONFIG_SENSORS_QENCODER -#include "board_qencoder.h" -#endif - -#ifdef CONFIG_SENSORS_HYT271 -# define HAVE_SENSORS_DEVICE -#endif - -#ifdef CONFIG_SENSORS_DS18B20 -# define HAVE_SENSORS_DEVICE -#endif - -#ifdef CONFIG_LCD_BACKPACK -#include "stm32_lcd_backpack.h" -#endif - -#ifdef CONFIG_USBADB -#include -#endif - -#ifdef CONFIG_I2C_DRIVER -#include -#include "stm32_i2c.h" -#endif - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Checking needed by W25 Flash */ - -#define HAVE_W25 1 - -/* Can't support the W25 device if it SPI1 or W25 support is not enabled */ - -#if !defined(CONFIG_STM32_SPI1) || !defined(CONFIG_MTD_W25) -# undef HAVE_W25 -#endif - -/* Can't support W25 features if mountpoints are disabled */ - -#ifdef CONFIG_DISABLE_MOUNTPOINT -# undef HAVE_W25 -#endif - -/* Default W25 minor number */ - -#if defined(HAVE_W25) && !defined(CONFIG_NSH_W25MINOR) -# define CONFIG_NSH_W25MINOR 0 -#endif - -/* Checking needed by MMC/SDCard */ - -#ifdef CONFIG_NSH_MMCSDMINOR -# define MMCSD_MINOR CONFIG_NSH_MMCSDMINOR -#else -# define MMCSD_MINOR 0 -#endif - -/**************************************************************************** - * Name: stm32_i2c_register - * - * Description: - * Register one I2C drivers for the I2C tool. - * - ****************************************************************************/ -#ifdef CONFIG_I2C_DRIVER -static void stm32_i2c_register(int bus) -{ - struct i2c_master_s *i2c; - int ret; - - i2c = stm32_i2cbus_initialize(bus); - if (i2c == NULL) - { - syslog(LOG_ERR, "ERROR: Failed to get I2C%d interface\n", bus); - } - else - { - ret = i2c_register(i2c, bus); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: Failed to register I2C%d driver: %d\n", - bus, ret); - stm32_i2cbus_uninitialize(i2c); - } - } -} -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -#ifdef HAVE_SENSORS_DEVICE -static int g_sensor_devno; -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_bringup - * - * Description: - * Perform architecture-specific initialization - * - * CONFIG_BOARD_LATE_INITIALIZE=y : - * Called from board_late_initialize(). - * - ****************************************************************************/ - -int stm32_bringup(void) -{ -#ifdef CONFIG_ONESHOT - struct oneshot_lowerhalf_s *os = NULL; -#endif - int ret = OK; - -#ifdef CONFIG_DEV_GPIO - ret = stm32_gpio_initialize(); - if (ret < 0) - { - syslog(LOG_ERR, "Failed to initialize GPIO Driver: %d\n", ret); - return ret; - } -#endif - -#ifdef CONFIG_VIDEO_FB - /* Initialize and register the framebuffer driver */ - - ret = fb_register(0, 0); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: fb_register() failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_I2C_DRIVER - /* Register I2C drivers on behalf of the I2C tool */ - #ifdef CONFIG_STM32_I2C1 - stm32_i2c_register(1); - #endif - #ifdef CONFIG_STM32_I2C2 - stm32_i2c_register(2); - #endif - #ifdef CONFIG_STM32_I2C3 - stm32_i2c_register(3); - #endif -#endif - -#ifdef CONFIG_LCD_BACKPACK - /* slcd:0, i2c:1, rows=2, cols=16 */ - - ret = board_lcd_backpack_init(0, 1, 2, 16); - if (ret < 0) - { - syslog(LOG_ERR, "Failed to initialize PCF8574 LCD, error %d\n", ret); - return ret; - } -#endif - -#ifdef CONFIG_SENSORS_ZEROCROSS - /* Configure the zero-crossing driver */ - - ret = board_zerocross_initialize(0); - if (ret < 0) - { - syslog(LOG_ERR, "Failed to initialize Zero-Cross, error %d\n", ret); - return ret; - } -#endif - -#ifdef CONFIG_MMCSD - ret = stm32_mmcsd_initialize(MMCSD_MINOR); - if (ret < 0) - { - syslog(LOG_ERR, "Failed to initialize SD slot %d: %d\n", ret); - return ret; - } -#endif - -#ifdef CONFIG_SENSORS_BMP180 - /* Initialize the BMP180 pressure sensor. */ - - ret = board_bmp180_initialize(0, 1); - if (ret < 0) - { - syslog(LOG_ERR, "Failed to initialize BMP180, error %d\n", ret); - return ret; - } -#endif - -#ifdef HAVE_W25 - /* Initialize and register the W25 FLASH file system. */ - - ret = stm32_w25initialize(CONFIG_NSH_W25MINOR); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: Failed to initialize W25 minor %d: %d\n", - CONFIG_NSH_W25MINOR, ret); - return ret; - } -#endif - -#ifdef CONFIG_FS_PROCFS - /* Mount the procfs file system */ - - ret = nx_mount(NULL, STM32_PROCFS_MOUNTPOINT, "procfs", 0, NULL); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: Failed to mount procfs at %s: %d\n", - STM32_PROCFS_MOUNTPOINT, ret); - } -#endif - -#ifdef HAVE_AT24 - /* Initialize the AT24 driver */ - - ret = stm32_at24_automount(AT24_MINOR); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_at24_automount() failed: %d\n", ret); - return ret; - } -#endif /* HAVE_AT24 */ - -#ifdef CONFIG_PWM - /* Initialize PWM and register the PWM device. */ - - ret = stm32_pwm_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_pwm_setup() failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_AUDIO_TONE - /* Configure and initialize the tone generator. */ - - ret = board_tone_initialize(0); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: board_tone_initialize() failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_LEDS_APA102 - /* Configure and initialize the APA102 LED Strip. */ - - ret = board_apa102_initialize(0, 1); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: board_apa102_initialize() failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_WS2812 - /* Configure and initialize the WS2812 LEDs. */ - - ret = board_ws2812_initialize(0, WS2812_SPI, WS2812_NLEDS); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: board_ws2812_initialize() failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_SENSORS_HYT271 - /* Configure and initialize the HYT271 sensors */ - - ret = stm32_hyt271initialize(g_sensor_devno); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_hyt271initialize() failed: %d\n", ret); - } - else - { - g_sensor_devno += ret; - } -#endif - -#ifdef CONFIG_SENSORS_DS18B20 - /* Configure and initialize the DS18B20 sensors */ - - ret = stm32_ds18b20initialize(g_sensor_devno); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_ds18b20initialize() failed: %d\n", ret); - } - else - { - g_sensor_devno += ret; - } -#endif - -#ifdef CONFIG_LM75_I2C - /* Configure and initialize the LM75 sensor */ - - ret = board_lm75_initialize(0, 1); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: board_lm75_initialize() failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_RGBLED - /* Configure and initialize the RGB LED. */ - - ret = stm32_rgbled_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_rgbled_setup() failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_SENSORS_HCSR04 - /* Configure and initialize the HC-SR04 distance sensor */ - - ret = board_hcsr04_initialize(0); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: board_hcsr04_initialize() failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_SENSORS_MAX6675 - ret = board_max6675_initialize(0, 1); - if (ret < 0) - { - serr("ERROR: board_max6675_initialize() failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_CAN_MCP2515 - /* Configure and initialize the MCP2515 CAN device */ - - ret = stm32_mcp2515initialize("/dev/can0"); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_mcp2515initialize() failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_CL_MFRC522 - ret = stm32_mfrc522initialize("/dev/rfid0"); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_mfrc522initialize() failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_ONESHOT - os = oneshot_initialize(1, 10); - if (os) - { - ret = oneshot_register("/dev/oneshot", os); - } -#endif - -#ifdef CONFIG_INPUT_BUTTONS - /* Register the BUTTON driver */ - - ret = btn_lower_initialize("/dev/buttons"); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: btn_lower_initialize() failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_INPUT_NUNCHUCK - /* Register the Nunchuck driver */ - - ret = board_nunchuck_initialize(0, 1); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: board_nunchuck_initialize() failed: %d\n", - ret); - } -#endif - -#ifdef CONFIG_SENSORS_QENCODER - /* Initialize and register the qencoder driver */ - - ret = board_qencoder_initialize(0, - CONFIG_STM32F103MINIMUM_QETIMER); - if (ret != OK) - { - syslog(LOG_ERR, - "ERROR: Failed to register the qencoder: %d\n", - ret); - } -#endif - -#ifdef CONFIG_USERLED - /* Register the LED driver */ - - ret = userled_lower_initialize("/dev/userleds"); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: userled_lower_initialize() failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_SENSORS_APDS9960 - /* Register the APDS-9960 gesture sensor */ - - ret = board_apds9960_initialize(0, 1); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: board_apds9960_initialize() failed: %d\n", - ret); - } -#endif - -#ifdef CONFIG_SENSORS_VEML6070 - /* Register the UV-A light sensor */ - - ret = board_veml6070_initialize(0, 1); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: board_veml6070_initialize() failed: %d\n", - ret); - } -#endif - -#ifdef CONFIG_ADC - /* Initialize ADC and register the ADC driver. */ - - ret = stm32_adc_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_adc_setup() failed: %d\n", ret); - } -#endif - -#if defined(CONFIG_WL_NRF24L01) - /* Initialize the NRF24L01 wireless module */ - - ret = board_nrf24l01_initialize(1); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: board_nrf24l01_initialize() failed: %d\n", - ret); - } -#endif - -#ifdef CONFIG_USBADB - usbdev_adb_initialize(); -#endif - -#ifdef CONFIG_STM32_CAN_CHARDRIVER - /* Initialize CAN and register the CAN driver. */ - - ret = stm32_can_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_can_setup failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_STM32_CAN_SOCKET - /* Initialize CAN socket interface */ - - /* STM32F103C8 may not have enough Flash for SocketCAN; use a part with - * more Flash (e.g. STM32F103CB). - */ - - ret = stm32_cansock_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_cansock_setup failed: %d\n", ret); - } -#endif - - return ret; -} diff --git a/boards/arm/stm32/stm32f103-minimum/src/stm32_buttons.c b/boards/arm/stm32/stm32f103-minimum/src/stm32_buttons.c deleted file mode 100644 index 44fa04b7acef9..0000000000000 --- a/boards/arm/stm32/stm32f103-minimum/src/stm32_buttons.c +++ /dev/null @@ -1,160 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f103-minimum/src/stm32_buttons.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include -#include - -#include "stm32_gpio.h" -#include "stm32f103_minimum.h" - -#if defined(CONFIG_ARCH_BUTTONS) - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#if defined(CONFIG_INPUT_BUTTONS) && !defined(CONFIG_ARCH_IRQBUTTONS) -# error "The NuttX Buttons Driver depends on IRQ support to work!\n" -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/* Pin configuration for each STM32F3Discovery button. This array is indexed - * by the BUTTON_* definitions in board.h - */ - -static const uint32_t g_buttons[NUM_BUTTONS] = -{ - GPIO_BTN_USER1, GPIO_BTN_USER2 -}; - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_button_initialize - * - * Description: - * board_button_initialize() must be called to initialize button resources. - * After that, board_buttons() may be called to collect the current state - * of all buttons or board_button_irq() may be called to register button - * interrupt handlers. - * - ****************************************************************************/ - -uint32_t board_button_initialize(void) -{ - int i; - - /* Configure the GPIO pins as inputs. NOTE that EXTI interrupts are - * configured for all pins. - */ - - for (i = 0; i < NUM_BUTTONS; i++) - { - stm32_configgpio(g_buttons[i]); - } - - return NUM_BUTTONS; -} - -/**************************************************************************** - * Name: board_buttons - ****************************************************************************/ - -uint32_t board_buttons(void) -{ - uint32_t ret = 0; - int i; - - /* Check that state of each key */ - - for (i = 0; i < NUM_BUTTONS; i++) - { - /* A LOW value means that the key is pressed. */ - - bool released = stm32_gpioread(g_buttons[i]); - - /* Accumulate the set of depressed (not released) keys */ - - if (!released) - { - ret |= (1 << i); - } - } - - return ret; -} - -/**************************************************************************** - * Button support. - * - * Description: - * board_button_initialize() must be called to initialize button resources. - * After that, board_buttons() may be called to collect the current state - * of all buttons or board_button_irq() may be called to register button - * interrupt handlers. - * - * After board_button_initialize() has been called, board_buttons() may be - * called to collect the state of all buttons. board_buttons() returns - * an 32-bit bit set with each bit associated with a button. See the - * BUTTON_*_BIT definitions in board.h for the meaning of each bit. - * - * board_button_irq() may be called to register an interrupt handler that - * will be called when a button is depressed or released. The ID value is - * a button enumeration value that uniquely identifies a button resource. - * See the BUTTON_* definitions in board.h for the meaning of enumeration - * value. - * - ****************************************************************************/ - -#ifdef CONFIG_ARCH_IRQBUTTONS -int board_button_irq(int id, xcpt_t irqhandler, void *arg) -{ - int ret = -EINVAL; - - /* The following should be atomic */ - - if (id >= MIN_IRQBUTTON && id <= MAX_IRQBUTTON) - { - ret = stm32_gpiosetevent(g_buttons[id], true, true, true, irqhandler, - arg); - } - - return ret; -} -#endif - -#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/stm32/stm32f103-minimum/src/stm32_can.c b/boards/arm/stm32/stm32f103-minimum/src/stm32_can.c deleted file mode 100644 index 4d0d37d09c690..0000000000000 --- a/boards/arm/stm32/stm32f103-minimum/src/stm32_can.c +++ /dev/null @@ -1,69 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f103-minimum/src/stm32_can.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include - -#include "stm32.h" -#include "stm32_can.h" - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_can_setup - * - * Description: - * Initialize CAN and register the CAN device - * - ****************************************************************************/ - -int stm32_can_setup(void) -{ - struct can_dev_s *can; - int ret; - - can = stm32_caninitialize(1); - if (can == NULL) - { - canerr("ERROR: Failed to get CAN interface\n"); - return -ENODEV; - } - - ret = can_register("/dev/can0", can); - if (ret < 0) - { - canerr("ERROR: can_register failed: %d\n", ret); - return ret; - } - - return OK; -} diff --git a/boards/arm/stm32/stm32f103-minimum/src/stm32_cansock.c b/boards/arm/stm32/stm32f103-minimum/src/stm32_cansock.c deleted file mode 100644 index 47da3f32fb9df..0000000000000 --- a/boards/arm/stm32/stm32f103-minimum/src/stm32_cansock.c +++ /dev/null @@ -1,59 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f103-minimum/src/stm32_cansock.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include "stm32_can.h" - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_cansock_setup - * - * Description: - * Initialize CAN socket interface - * - ****************************************************************************/ - -int stm32_cansock_setup(void) -{ - int ret; - - /* Call stm32_cansockinitialize() to register the CAN network device */ - - ret = stm32_cansockinitialize(1); - if (ret < 0) - { - canerr("ERROR: Failed to get CAN interface %d\n", ret); - return ret; - } - - return OK; -} diff --git a/boards/arm/stm32/stm32f103-minimum/src/stm32_gpio.c b/boards/arm/stm32/stm32f103-minimum/src/stm32_gpio.c deleted file mode 100644 index 5806b9579bd4d..0000000000000 --- a/boards/arm/stm32/stm32f103-minimum/src/stm32_gpio.c +++ /dev/null @@ -1,343 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f103-minimum/src/stm32_gpio.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include -#include - -#include - -#include "chip.h" -#include "stm32.h" -#include "stm32f103_minimum.h" - -#if defined(CONFIG_DEV_GPIO) && !defined(CONFIG_GPIO_LOWER_HALF) - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -struct stm32gpio_dev_s -{ - struct gpio_dev_s gpio; - uint8_t id; -}; - -struct stm32gpint_dev_s -{ - struct stm32gpio_dev_s stm32gpio; - pin_interrupt_t callback; -}; - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -#if BOARD_NGPIOIN > 0 -static int gpin_read(struct gpio_dev_s *dev, bool *value); -#endif /* BOARD_NGPIOIN > 0 */ -#if BOARD_NGPIOOUT > 0 -static int gpout_read(struct gpio_dev_s *dev, bool *value); -static int gpout_write(struct gpio_dev_s *dev, bool value); -#endif /* BOARD_NGPIOOUT > 0 */ -#if BOARD_NGPIOINT > 0 -static int gpint_read(struct gpio_dev_s *dev, bool *value); -static int gpint_attach(struct gpio_dev_s *dev, - pin_interrupt_t callback); -static int gpint_enable(struct gpio_dev_s *dev, bool enable); -#endif /* BOARD_NGPIOINT > 0 */ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -#if BOARD_NGPIOIN > 0 -static const struct gpio_operations_s gpin_ops = -{ - .go_read = gpin_read, - .go_write = NULL, - .go_attach = NULL, - .go_enable = NULL, -}; -#endif /* BOARD_NGPIOIN > 0 */ - -#if BOARD_NGPIOOUT > 0 -static const struct gpio_operations_s gpout_ops = -{ - .go_read = gpout_read, - .go_write = gpout_write, - .go_attach = NULL, - .go_enable = NULL, -}; -#endif /* BOARD_NGPIOOUT > 0 */ - -#if BOARD_NGPIOINT > 0 -static const struct gpio_operations_s gpint_ops = -{ - .go_read = gpint_read, - .go_write = NULL, - .go_attach = gpint_attach, - .go_enable = gpint_enable, -}; -#endif /* BOARD_NGPIOINT > 0 */ - -#if BOARD_NGPIOIN > 0 -/* This array maps the GPIO pins used as INPUT */ - -static const uint32_t g_gpioinputs[BOARD_NGPIOIN] = -{ - GPIO_IN1, -}; - -static struct stm32gpio_dev_s g_gpin[BOARD_NGPIOIN]; -#endif - -#if BOARD_NGPIOOUT > 0 -/* This array maps the GPIO pins used as OUTPUT */ - -static const uint32_t g_gpiooutputs[BOARD_NGPIOOUT] = -{ - GPIO_OUT1, -}; - -static struct stm32gpio_dev_s g_gpout[BOARD_NGPIOOUT]; -#endif - -#if BOARD_NGPIOINT > 0 -/* This array maps the GPIO pins used as INTERRUPT INPUTS */ - -static const uint32_t g_gpiointinputs[BOARD_NGPIOINT] = -{ - GPIO_INT1, -}; - -static struct stm32gpint_dev_s g_gpint[BOARD_NGPIOINT]; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - - #if BOARD_NGPIOINT > 0 -static int stm32gpio_interrupt(int irq, void *context, void *arg) -{ - struct stm32gpint_dev_s *stm32gpint = - (struct stm32gpint_dev_s *)arg; - - DEBUGASSERT(stm32gpint != NULL && stm32gpint->callback != NULL); - gpioinfo("Interrupt! callback=%p\n", stm32gpint->callback); - - stm32gpint->callback(&stm32gpint->stm32gpio.gpio, - stm32gpint->stm32gpio.id); - return OK; -} -#endif /* BOARD_NGPIOINT > 0 */ - -#if BOARD_NGPIOIN > 0 -static int gpin_read(struct gpio_dev_s *dev, bool *value) -{ - struct stm32gpio_dev_s *stm32gpio = - (struct stm32gpio_dev_s *)dev; - - DEBUGASSERT(stm32gpio != NULL && value != NULL); - DEBUGASSERT(stm32gpio->id < BOARD_NGPIOIN); - gpioinfo("Reading...\n"); - - *value = stm32_gpioread(g_gpioinputs[stm32gpio->id]); - return OK; -} -#endif /* BOARD_NGPIOIN > 0*/ - -#if BOARD_NGPIOOUT > 0 -static int gpout_read(struct gpio_dev_s *dev, bool *value) -{ - struct stm32gpio_dev_s *stm32gpio = - (struct stm32gpio_dev_s *)dev; - - DEBUGASSERT(stm32gpio != NULL && value != NULL); - DEBUGASSERT(stm32gpio->id < BOARD_NGPIOOUT); - gpioinfo("Reading...\n"); - - *value = stm32_gpioread(g_gpiooutputs[stm32gpio->id]); - return OK; -} - -static int gpout_write(struct gpio_dev_s *dev, bool value) -{ - struct stm32gpio_dev_s *stm32gpio = - (struct stm32gpio_dev_s *)dev; - - DEBUGASSERT(stm32gpio != NULL); - DEBUGASSERT(stm32gpio->id < BOARD_NGPIOOUT); - gpioinfo("Writing %d\n", (int)value); - - stm32_gpiowrite(g_gpiooutputs[stm32gpio->id], value); - return OK; -} -#endif /* BOARD_NGPIOOUT > 0 */ - -#if BOARD_NGPIOINT > 0 -static int gpint_read(struct gpio_dev_s *dev, bool *value) -{ - struct stm32gpint_dev_s *stm32gpint = - (struct stm32gpint_dev_s *)dev; - - DEBUGASSERT(stm32gpint != NULL && value != NULL); - DEBUGASSERT(stm32gpint->stm32gpio.id < BOARD_NGPIOINT); - gpioinfo("Reading int pin...\n"); - - *value = stm32_gpioread(g_gpiointinputs[stm32gpint->stm32gpio.id]); - return OK; -} - -static int gpint_attach(struct gpio_dev_s *dev, - pin_interrupt_t callback) -{ - struct stm32gpint_dev_s *stm32gpint = - (struct stm32gpint_dev_s *)dev; - - gpioinfo("Attaching the callback\n"); - - /* Make sure the interrupt is disabled */ - - stm32_gpiosetevent(g_gpiointinputs[stm32gpint->stm32gpio.id], false, - false, false, NULL, NULL); - - gpioinfo("Attach %p\n", callback); - stm32gpint->callback = callback; - return OK; -} - -static int gpint_enable(struct gpio_dev_s *dev, bool enable) -{ - struct stm32gpint_dev_s *stm32gpint = - (struct stm32gpint_dev_s *)dev; - - if (enable) - { - if (stm32gpint->callback != NULL) - { - gpioinfo("Enabling the interrupt\n"); - - /* Configure the interrupt for rising edge */ - - stm32_gpiosetevent(g_gpiointinputs[stm32gpint->stm32gpio.id], - true, false, false, stm32gpio_interrupt, - &g_gpint[stm32gpint->stm32gpio.id]); - } - } - else - { - gpioinfo("Disable the interrupt\n"); - stm32_gpiosetevent(g_gpiointinputs[stm32gpint->stm32gpio.id], - false, false, false, NULL, NULL); - } - - return OK; -} -#endif /* BOARD_NGPIOINT > 0 */ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_gpio_initialize - * - * Description: - * Initialize GPIO drivers for use with /apps/examples/gpio - * - ****************************************************************************/ - -int stm32_gpio_initialize(void) -{ - int i; - int pincount = 0; - -#if BOARD_NGPIOIN > 0 - for (i = 0; i < BOARD_NGPIOIN; i++) - { - /* Setup and register the GPIO pin */ - - g_gpin[i].gpio.gp_pintype = GPIO_INPUT_PIN; - g_gpin[i].gpio.gp_ops = &gpin_ops; - g_gpin[i].id = i; - gpio_pin_register(&g_gpin[i].gpio, pincount); - - /* Configure the pin that will be used as input */ - - stm32_configgpio(g_gpioinputs[i]); - - pincount++; - } -#endif - -#if BOARD_NGPIOOUT > 0 - for (i = 0; i < BOARD_NGPIOOUT; i++) - { - /* Setup and register the GPIO pin */ - - g_gpout[i].gpio.gp_pintype = GPIO_OUTPUT_PIN; - g_gpout[i].gpio.gp_ops = &gpout_ops; - g_gpout[i].id = i; - gpio_pin_register(&g_gpout[i].gpio, pincount); - - /* Configure the pin that will be used as output */ - - stm32_gpiowrite(g_gpiooutputs[i], 0); - stm32_configgpio(g_gpiooutputs[i]); - - pincount++; - } -#endif - -#if BOARD_NGPIOINT > 0 - for (i = 0; i < BOARD_NGPIOINT; i++) - { - /* Setup and register the GPIO pin */ - - g_gpint[i].stm32gpio.gpio.gp_pintype = GPIO_INTERRUPT_PIN; - g_gpint[i].stm32gpio.gpio.gp_ops = &gpint_ops; - g_gpint[i].stm32gpio.id = i; - gpio_pin_register(&g_gpint[i].stm32gpio.gpio, pincount); - - /* Configure the pin that will be used as interrupt input */ - - stm32_configgpio(g_gpiointinputs[i]); - - pincount++; - } -#endif - - return 0; -} -#endif /* CONFIG_DEV_GPIO && !CONFIG_GPIO_LOWER_HALF */ diff --git a/boards/arm/stm32/stm32f103-minimum/src/stm32_lcd_ssd1306.c b/boards/arm/stm32/stm32f103-minimum/src/stm32_lcd_ssd1306.c deleted file mode 100644 index adff376b27902..0000000000000 --- a/boards/arm/stm32/stm32f103-minimum/src/stm32_lcd_ssd1306.c +++ /dev/null @@ -1,88 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f103-minimum/src/stm32_lcd_ssd1306.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include -#include -#include - -#include "stm32.h" -#include "stm32f103_minimum.h" - -#include "stm32_ssd1306.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#define OLED_I2C_PORT 1 /* OLED display connected to I2C1 */ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_lcd_initialize - ****************************************************************************/ - -int board_lcd_initialize(void) -{ - int ret; - - ret = board_ssd1306_initialize(OLED_I2C_PORT); - if (ret < 0) - { - lcderr("ERROR: Failed to initialize SSD1306\n"); - return ret; - } - - return OK; -} - -/**************************************************************************** - * Name: board_lcd_getdev - ****************************************************************************/ - -struct lcd_dev_s *board_lcd_getdev(int devno) -{ - return board_ssd1306_getdev(); -} - -/**************************************************************************** - * Name: board_lcd_uninitialize - ****************************************************************************/ - -void board_lcd_uninitialize(void) -{ - /* TO-FIX */ -} diff --git a/boards/arm/stm32/stm32f103-minimum/src/stm32_max7219.c b/boards/arm/stm32/stm32f103-minimum/src/stm32_max7219.c deleted file mode 100644 index 79dc5aa1120c2..0000000000000 --- a/boards/arm/stm32/stm32f103-minimum/src/stm32_max7219.c +++ /dev/null @@ -1,114 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f103-minimum/src/stm32_max7219.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include - -#include -#include -#include -#include -#include - -#include "stm32_gpio.h" -#include "stm32_spi.h" -#include "stm32f103_minimum.h" - -#ifdef CONFIG_NX_LCDDRIVER - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#define LCD_SPI_PORTNO 1 /* On SPI1 */ - -#ifndef CONFIG_LCD_CONTRAST -# define CONFIG_LCD_CONTRAST 60 -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -struct spi_dev_s *g_spidev; -struct lcd_dev_s *g_lcddev; - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_lcd_initialize - ****************************************************************************/ - -int board_lcd_initialize(void) -{ - g_spidev = stm32_spibus_initialize(LCD_SPI_PORTNO); - - if (!g_spidev) - { - lcderr("ERROR: Failed to initialize SPI port %d\n", LCD_SPI_PORTNO); - return -ENODEV; - } - - return OK; -} - -/**************************************************************************** - * Name: board_lcd_getdev - ****************************************************************************/ - -struct lcd_dev_s *board_lcd_getdev(int lcddev) -{ - g_lcddev = max7219_initialize(g_spidev, lcddev); - if (!g_lcddev) - { - lcderr("ERROR: Failed to bind SPI port 1 to LCD %d\n", lcddev); - } - else - { - lcdinfo("SPI port 1 bound to LCD %d\n", lcddev); - - return g_lcddev; - } - - return NULL; -} - -/**************************************************************************** - * Name: board_lcd_uninitialize - ****************************************************************************/ - -void board_lcd_uninitialize(void) -{ - /* TO-FIX */ -} - -#endif /* CONFIG_NX_LCDDRIVER */ diff --git a/boards/arm/stm32/stm32f103-minimum/src/stm32_mcp2515.c b/boards/arm/stm32/stm32f103-minimum/src/stm32_mcp2515.c deleted file mode 100644 index 71ba958c1551e..0000000000000 --- a/boards/arm/stm32/stm32f103-minimum/src/stm32_mcp2515.c +++ /dev/null @@ -1,241 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f103-minimum/src/stm32_mcp2515.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include "stm32.h" -#include "stm32_spi.h" -#include "stm32f103_minimum.h" - -#if defined(CONFIG_SPI) && defined(CONFIG_STM32_SPI1) && \ - defined(CONFIG_CAN_MCP2515) - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#define MCP2515_SPI_PORTNO 1 /* On SPI1 */ - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -struct stm32_mcp2515config_s -{ - /* Configuration structure as seen by the MCP2515 driver */ - - struct mcp2515_config_s config; - - /* Additional private definitions only known to this driver */ - - struct mcp2515_can_s *handle; /* The MCP2515 driver handle */ - mcp2515_handler_t handler; /* The MCP2515 interrupt handler */ - void *arg; /* Argument to pass to the interrupt handler */ -}; - -/**************************************************************************** - * Static Function Prototypes - ****************************************************************************/ - -/* IRQ/GPIO access callbacks. These operations all hidden behind callbacks - * to isolate the MCP2515 driver from differences in GPIO interrupt handling - * by varying boards and MCUs. - * - * attach - Attach the MCP2515 interrupt handler to the GPIO interrupt - */ - -static int mcp2515_attach(struct mcp2515_config_s *state, - mcp2515_handler_t handler, void *arg); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* A reference to a structure of this type must be passed to the MCP2515 - * driver. This structure provides information about the configuration - * of the MCP2515 and provides some board-specific hooks. - * - * Memory for this structure is provided by the caller. It is not copied - * by the driver and is presumed to persist while the driver is active. The - * memory must be writable because, under certain circumstances, the driver - * may modify frequency or X plate resistance values. - */ - -static struct stm32_mcp2515config_s g_mcp2515config = -{ - .config = - { - .spi = NULL, - .baud = 0, /* REVISIT. Probably broken by commit eb7373cedfa */ - .btp = 0, /* REVISIT. Probably broken by commit eb7373cedfa */ - .devid = 0, - .mode = 0, /* REVISIT. Probably broken by commit eb7373cedfa */ - .nfilters = 6, -#ifdef MCP2515_LOOPBACK - .loopback = false; -#endif - .attach = mcp2515_attach, - }, -}; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/* This is the MCP2515 Interrupt handler */ - -int mcp2515_interrupt(int irq, void *context, void *arg) -{ - struct stm32_mcp2515config_s *priv = - (struct stm32_mcp2515config_s *)arg; - - DEBUGASSERT(priv != NULL); - - /* Verify that we have a handler attached */ - - if (priv->handler) - { - /* Yes.. forward with interrupt along with its argument */ - - priv->handler(&priv->config, priv->arg); - } - - return OK; -} - -static int mcp2515_attach(struct mcp2515_config_s *state, - mcp2515_handler_t handler, void *arg) -{ - struct stm32_mcp2515config_s *priv = - (struct stm32_mcp2515config_s *)state; - irqstate_t flags; - - caninfo("Saving handler %p\n", handler); - - flags = enter_critical_section(); - - priv->handler = handler; - priv->arg = arg; - - /* Configure the interrupt for falling edge */ - - stm32_gpiosetevent(GPIO_MCP2515_IRQ, false, true, false, - mcp2515_interrupt, priv); - - leave_critical_section(flags); - - return OK; -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_mcp2515initialize - * - * Description: - * Initialize and register the MCP2515 RFID driver. - * - * Input Parameters: - * devpath - The full path to the driver to register. E.g., "/dev/rfid0" - * - * Returned Value: - * Zero (OK) on success; a negated errno value on failure. - * - ****************************************************************************/ - -int stm32_mcp2515initialize(const char *devpath) -{ - struct spi_dev_s *spi; - struct can_dev_s *can; - struct mcp2515_can_s *mcp2515; - int ret; - - /* Check if we are already initialized */ - - if (!g_mcp2515config.handle) - { - sninfo("Initializing\n"); - - /* Configure the MCP2515 interrupt pin as an input */ - - stm32_configgpio(GPIO_MCP2515_IRQ); - - spi = stm32_spibus_initialize(MCP2515_SPI_PORTNO); - - if (!spi) - { - return -ENODEV; - } - - /* Save the SPI instance in the mcp2515_config_s structure */ - - g_mcp2515config.config.spi = spi; - - /* Instantiate the MCP2515 CAN Driver */ - - mcp2515 = mcp2515_instantiate(&g_mcp2515config.config); - if (mcp2515 == NULL) - { - canerr("ERROR: Failed to get MCP2515 Driver Loaded\n"); - return -ENODEV; - } - - /* Save the opaque structure */ - - g_mcp2515config.handle = mcp2515; - - /* Initialize the CAN Device with the MCP2515 operations */ - - can = mcp2515_initialize(mcp2515); - if (can == NULL) - { - canerr("ERROR: Failed to get CAN interface\n"); - return -ENODEV; - } - - /* Register the CAN driver at "/dev/can0" */ - - ret = can_register(devpath, can); - if (ret < 0) - { - canerr("ERROR: can_register failed: %d\n", ret); - return ret; - } - } - - return OK; -} - -#endif /* CONFIG_SPI && CONFIG_CAN_MCP2515 */ diff --git a/boards/arm/stm32/stm32f103-minimum/src/stm32_mmcsd.c b/boards/arm/stm32/stm32f103-minimum/src/stm32_mmcsd.c deleted file mode 100644 index 96c77106410db..0000000000000 --- a/boards/arm/stm32/stm32f103-minimum/src/stm32_mmcsd.c +++ /dev/null @@ -1,116 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f103-minimum/src/stm32_mmcsd.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include -#include -#include -#include -#include -#include -#include - -#include "stm32.h" -#include "stm32f103_minimum.h" -#include "stm32_spi.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#ifndef CONFIG_STM32_SPI1 -# error "SD driver requires CONFIG_STM32_SPI1 to be enabled" -#endif - -#ifdef CONFIG_DISABLE_MOUNTPOINT -# error "SD driver requires CONFIG_DISABLE_MOUNTPOINT to be disabled" -#endif - -/**************************************************************************** - * Private Definitions - ****************************************************************************/ - -static const int SD_SPI_PORT = 1; /* SD is connected to SPI1 port */ -static const int SD_SLOT_NO = 0; /* There is only one SD slot */ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/* NOTE: We are using a SDCard adapter/module without Card Detect pin! - * Then we don't need to Card Detect callback here. - */ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_spi1register - * - * Description: - * Registers media change callback - ****************************************************************************/ - -int stm32_spi1register(struct spi_dev_s *dev, spi_mediachange_t callback, - void *arg) -{ - spiinfo("INFO: Registering spi1 device\n"); - return OK; -} - -/**************************************************************************** - * Name: stm32_mmcsd_initialize - * - * Description: - * Initialize SPI-based SD card and card detect thread. - ****************************************************************************/ - -int stm32_mmcsd_initialize(int minor) -{ - struct spi_dev_s *spi; - int rv; - - mcinfo("INFO: Initializing mmcsd card\n"); - - spi = stm32_spibus_initialize(SD_SPI_PORT); - if (spi == NULL) - { - mcerr("ERROR: Failed to initialize SPI port %d\n", SD_SPI_PORT); - return -ENODEV; - } - - rv = mmcsd_spislotinitialize(minor, SD_SLOT_NO, spi); - if (rv < 0) - { - mcerr("ERROR: Failed to bind SPI port %d to SD slot %d\n", - SD_SPI_PORT, SD_SLOT_NO); - return rv; - } - - spiinfo("INFO: mmcsd card has been initialized successfully\n"); - return OK; -} diff --git a/boards/arm/stm32/stm32f103-minimum/src/stm32_pwm.c b/boards/arm/stm32/stm32f103-minimum/src/stm32_pwm.c deleted file mode 100644 index fb7dc02e793eb..0000000000000 --- a/boards/arm/stm32/stm32f103-minimum/src/stm32_pwm.c +++ /dev/null @@ -1,127 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f103-minimum/src/stm32_pwm.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32_pwm.h" -#include "stm32f103_minimum.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -/* PWM - * - * The stm32f103-minimum has no real on-board PWM devices, but the board can - * be configured to output a pulse train using TIM4 CH2. - * This pin is used by FSMC is connect to CN5 just for this purpose: - * - * PB0 ADC12_IN8/TIM3_CH3 - * - */ - -#define HAVE_PWM 1 - -#ifndef CONFIG_PWM -# undef HAVE_PWM -#endif - -#ifndef CONFIG_STM32_TIM3 -# undef HAVE_PWM -#endif - -#ifndef CONFIG_STM32_TIM3_PWM -# undef HAVE_PWM -#endif - -#if !defined(CONFIG_STM32_TIM3_CHANNEL) || CONFIG_STM32_TIM3_CHANNEL != STM32F103MINIMUM_PWMCHANNEL -# undef HAVE_PWM -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_pwm_setup - * - * Description: - * Initialize PWM and register the PWM device. - * - ****************************************************************************/ - -int stm32_pwm_setup(void) -{ -#ifdef HAVE_PWM - static bool initialized = false; - struct pwm_lowerhalf_s *pwm; - int ret; - - /* Have we already initialized? */ - - if (!initialized) - { - /* Call stm32_pwminitialize() to get an instance of the PWM interface */ - - pwm = stm32_pwminitialize(STM32F103MINIMUM_PWMTIMER); - if (!pwm) - { - aerr("ERROR: Failed to get the STM32 PWM lower half\n"); - return -ENODEV; - } - - /* Register the PWM driver at "/dev/pwm0" */ - - ret = pwm_register("/dev/pwm0", pwm); - if (ret < 0) - { - aerr("ERROR: pwm_register failed: %d\n", ret); - return ret; - } - - /* Now we are initialized */ - - initialized = true; - } - - return OK; -#else - return -ENODEV; -#endif -} diff --git a/boards/arm/stm32/stm32f103-minimum/src/stm32_reset.c b/boards/arm/stm32/stm32f103-minimum/src/stm32_reset.c deleted file mode 100644 index 40e3e2659b8c0..0000000000000 --- a/boards/arm/stm32/stm32f103-minimum/src/stm32_reset.c +++ /dev/null @@ -1,66 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f103-minimum/src/stm32_reset.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_reset - * - * Description: - * Reset board. Support for this function is required by board-level - * logic if CONFIG_BOARDCTL_RESET is selected. - * - * Input Parameters: - * status - Status information provided with the reset event. This - * meaning of this status information is board-specific. If not - * used by a board, the value zero may be provided in calls to - * board_reset(). - * - * Returned Value: - * If this function returns, then it was not possible to power-off the - * board due to some constraints. The return value int this case is a - * board-specific reason for the failure to shutdown. - * - ****************************************************************************/ - -int board_reset(int status) -{ -#ifdef CONFIG_STM32_DFU - /* TODO handle reboot to bootloader */ - -#endif - - up_systemreset(); - return 0; -} - diff --git a/boards/arm/stm32/stm32f103-minimum/src/stm32_rgbled.c b/boards/arm/stm32/stm32f103-minimum/src/stm32_rgbled.c deleted file mode 100644 index 3ba2dc47d783c..0000000000000 --- a/boards/arm/stm32/stm32f103-minimum/src/stm32_rgbled.c +++ /dev/null @@ -1,185 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f103-minimum/src/stm32_rgbled.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32_pwm.h" -#include "stm32f103_minimum.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -#define HAVE_RGBLED 1 - -#ifndef CONFIG_PWM -# undef HAVE_RGBLED -#endif - -#ifndef CONFIG_STM32_TIM1 -# undef HAVE_RGBLED -#endif - -#ifndef CONFIG_STM32_TIM2 -# undef HAVE_RGBLED -#endif - -#ifndef CONFIG_STM32_TIM4 -# undef HAVE_RGBLED -#endif - -#ifndef CONFIG_STM32_TIM1_PWM -# undef HAVE_RGBLED -#endif - -#ifndef CONFIG_STM32_TIM2_PWM -# undef HAVE_RGBLED -#endif - -#ifndef CONFIG_STM32_TIM4_PWM -# undef HAVE_RGBLED -#endif - -#if CONFIG_STM32_TIM1_CHANNEL != RGBLED_RPWMCHANNEL -# undef HAVE_PWM -#endif - -#if CONFIG_STM32_TIM2_CHANNEL != RGBLED_GPWMCHANNEL -# undef HAVE_PWM -#endif - -#if CONFIG_STM32_TIM4_CHANNEL != RGBLED_BPWMCHANNEL -# undef HAVE_PWM -#endif - -#ifdef HAVE_RGBLED - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_rgbled_setup - * - * Description: - * Initial for support of a connected RGB LED using PWM. - * - ****************************************************************************/ - -int stm32_rgbled_setup(void) -{ - static bool initialized = false; - struct pwm_lowerhalf_s *ledr; - struct pwm_lowerhalf_s *ledg; - struct pwm_lowerhalf_s *ledb; - struct pwm_info_s info; - int ret; - - /* Have we already initialized? */ - - if (!initialized) - { - /* Call stm32_pwminitialize() to get an instance of the PWM interface */ - - ledr = stm32_pwminitialize(RGBLED_RPWMTIMER); - if (!ledr) - { - lederr("ERROR: Failed to get the STM32 PWM lower half to LEDR\n"); - return -ENODEV; - } - - /* Define frequency and duty cycle */ - - info.frequency = 100; - info.channels[0].duty = 0; - - /* Initialize LED R */ - - ledr->ops->setup(ledr); - ledr->ops->start(ledr, &info); - - /* Call stm32_pwminitialize() to get an instance of the PWM interface */ - - ledg = stm32_pwminitialize(RGBLED_GPWMTIMER); - if (!ledg) - { - lederr("ERROR: Failed to get the STM32 PWM lower half to LEDG\n"); - return -ENODEV; - } - - /* Initialize LED G */ - - ledg->ops->setup(ledg); - ledg->ops->start(ledg, &info); - - /* Call stm32_pwminitialize() to get an instance of the PWM interface */ - - ledb = stm32_pwminitialize(RGBLED_BPWMTIMER); - if (!ledb) - { - lederr("ERROR: Failed to get the STM32 PWM lower half to LEDB\n"); - return -ENODEV; - } - - /* Initialize LED B */ - - ledb->ops->setup(ledb); - ledb->ops->start(ledb, &info); - - /* Register the RGB LED diver at "/dev/rgbled0" */ - - ret = rgbled_register("/dev/rgbled0", ledr, ledg, ledb, - RGBLED_RPWMCHANNEL, RGBLED_GPWMCHANNEL, - RGBLED_BPWMCHANNEL); - if (ret < 0) - { - lederr("ERROR: rgbled_register failed: %d\n", ret); - return ret; - } - - /* Now we are initialized */ - - initialized = true; - } - - return OK; -} - -#else -# error "HAVE_RGBLED is undefined" -#endif /* HAVE_RGBLED */ diff --git a/boards/arm/stm32/stm32f103-minimum/src/stm32_spi.c b/boards/arm/stm32/stm32f103-minimum/src/stm32_spi.c deleted file mode 100644 index 4cb79126a6d63..0000000000000 --- a/boards/arm/stm32/stm32f103-minimum/src/stm32_spi.c +++ /dev/null @@ -1,285 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f103-minimum/src/stm32_spi.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include "arm_internal.h" -#include "chip.h" -#include "stm32.h" -#include "stm32f103_minimum.h" - -#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_spidev_initialize - * - * Description: - * Called to configure SPI chip select GPIO pins for the HY-MiniSTM32 - * board. - * - ****************************************************************************/ - -void stm32_spidev_initialize(void) -{ - /* NOTE: Clocking for SPI1 and/or SPI2 was already provided in stm32_rcc.c. - * Configurations of SPI pins is performed in stm32_spi.c. - * Here, we only initialize chip select pins unique to the board - * architecture. - */ - -#ifdef CONFIG_MTD_W25 - stm32_configgpio(FLASH_SPI1_CS); /* FLASH chip select */ -#endif - -#ifdef CONFIG_CAN_MCP2515 - stm32_configgpio(GPIO_MCP2515_CS); /* MCP2515 chip select */ -#endif - -#ifdef CONFIG_CL_MFRC522 - stm32_configgpio(GPIO_CS_MFRC522); /* MFRC522 chip select */ -#endif - -#if defined(CONFIG_SENSORS_MAX6675) - stm32_configgpio(GPIO_MAX6675_CS); /* MAX6675 chip select */ -#endif - -#ifdef CONFIG_LCD_MAX7219 - stm32_configgpio(STM32_LCD_CS); /* MAX7219 chip select */ -#endif - -#ifdef CONFIG_LCD_ST7567 - stm32_configgpio(STM32_LCD_CS); /* ST7567 chip select */ -#endif - -#ifdef CONFIG_LCD_PCD8544 - stm32_configgpio(STM32_LCD_CS); /* ST7567 chip select */ -#endif - -#ifdef CONFIG_WL_NRF24L01 - stm32_configgpio(GPIO_NRF24L01_CS); /* nRF24L01 chip select */ -#endif - -#ifdef CONFIG_MMCSD_SPI - stm32_configgpio(GPIO_SDCARD_CS); /* SD/MMC Card chip select */ -#endif -} - -/**************************************************************************** - * Name: stm32_spi1/2select and stm32_spi1/2status - * - * Description: - * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status - * must be provided by board-specific logic. They are implementations of - * the select and status methods of the SPI interface defined by struct - * spi_ops_s (see include/nuttx/spi/spi.h). All other methods (including - * stm32_spibus_initialize()) are provided by common STM32 logic. - * To use this common SPI logic on your board: - * - * 1. Provide logic in stm32_boardinitialize() to configure SPI chip select - * pins. - * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() functions - * in your board-specific logic. These functions will perform chip - * selection and status operations using GPIOs in the way your board is - * configured. - * 3. Add a calls to stm32_spibus_initialize() in your low level - * application initialization logic - * 4. The handle returned by stm32_spibus_initialize() may then be used to - * bind the SPI driver to higher level logic (e.g., calling - * mmcsd_spislotinitialize(), for example, will bind the SPI driver to - * the SPI MMC/SD driver). - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_SPI1 -void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, - bool selected) -{ -#if defined(CONFIG_CAN_MCP2515) - if (devid == SPIDEV_CANBUS(0)) - { - stm32_gpiowrite(GPIO_MCP2515_CS, !selected); - } -#endif - -#if defined(CONFIG_CL_MFRC522) - if (devid == SPIDEV_CONTACTLESS(0)) - { - stm32_gpiowrite(GPIO_CS_MFRC522, !selected); - } -#endif - -#if defined(CONFIG_SENSORS_MAX6675) - if (devid == SPIDEV_TEMPERATURE(0)) - { - stm32_gpiowrite(GPIO_MAX6675_CS, !selected); - } -#endif - -#ifdef CONFIG_LCD_MAX7219 - if (devid == SPIDEV_DISPLAY(0)) - { - stm32_gpiowrite(STM32_LCD_CS, !selected); - } -#endif - -#ifdef CONFIG_LCD_PCD8544 - if (devid == SPIDEV_DISPLAY(0)) - { - stm32_gpiowrite(STM32_LCD_CS, !selected); - } -#endif - -#ifdef CONFIG_LCD_ST7567 - if (devid == SPIDEV_DISPLAY(0)) - { - stm32_gpiowrite(STM32_LCD_CS, !selected); - } -#endif - -#ifdef CONFIG_WL_NRF24L01 - if (devid == SPIDEV_WIRELESS(0)) - { - stm32_gpiowrite(GPIO_NRF24L01_CS, !selected); - } -#endif - -#ifdef CONFIG_MMCSD_SPI - if (devid == SPIDEV_MMCSD(0)) - { - stm32_gpiowrite(GPIO_SDCARD_CS, !selected); - } -#endif - -#ifdef CONFIG_MTD_W25 - stm32_gpiowrite(FLASH_SPI1_CS, !selected); -#endif -} - -uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) -{ - uint8_t status = 0; - -#ifdef CONFIG_WL_NRF24L01 - if (devid == SPIDEV_WIRELESS(0)) - { - status |= SPI_STATUS_PRESENT; - } -#endif - -#ifdef CONFIG_MMCSD_SPI - if (devid == SPIDEV_MMCSD(0)) - { - status |= SPI_STATUS_PRESENT; - } -#endif - - return status; -} -#endif - -#ifdef CONFIG_STM32_SPI2 -void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid, - bool selected) -{ -} - -uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) -{ - return 0; -} -#endif - -/**************************************************************************** - * Name: stm32_spi1cmddata - * - * Description: - * Set or clear the SH1101A A0 or SD1306 D/C n bit to select data (true) - * or command (false). This function must be provided by platform-specific - * logic. This is an implementation of the cmddata method of the SPI - * interface defined by struct spi_ops_s (see include/nuttx/spi/spi.h). - * - * Input Parameters: - * - * spi - SPI device that controls the bus the device that requires the CMD/ - * DATA selection. - * devid - If there are multiple devices on the bus, this selects which one - * to select cmd or data. NOTE: This design restricts, for example, - * one one SPI display per SPI bus. - * cmd - true: select command; false: select data - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef CONFIG_SPI_CMDDATA -#ifdef CONFIG_STM32_SPI1 -int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, - bool cmd) -{ -#ifdef CONFIG_LCD_ST7567 - if (devid == SPIDEV_DISPLAY(0)) - { - /* This is the Data/Command control pad which determines whether the - * data bits are data or a command. - */ - - stm32_gpiowrite(STM32_LCD_RS, !cmd); - - return OK; - } -#endif - -#ifdef CONFIG_LCD_PCD8544 - if (devid == SPIDEV_DISPLAY(0)) - { - /* This is the Data/Command control pad which determines whether the - * data bits are data or a command. - */ - - stm32_gpiowrite(STM32_LCD_CD, !cmd); - - return OK; - } -#endif - - return -ENODEV; -} -#endif -#endif - -#endif /* CONFIG_STM32_SPI1 || CONFIG_STM32_SPI2 */ diff --git a/boards/arm/stm32/stm32f103-minimum/src/stm32_usbdev.c b/boards/arm/stm32/stm32f103-minimum/src/stm32_usbdev.c deleted file mode 100644 index 9cf25efa67ce3..0000000000000 --- a/boards/arm/stm32/stm32f103-minimum/src/stm32_usbdev.c +++ /dev/null @@ -1,93 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f103-minimum/src/stm32_usbdev.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include - -#include -#include - -#include "arm_internal.h" -#include "stm32.h" -#include "stm32f103_minimum.h" - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_usbinitialize - * - * Description: - * Called to setup USB-related GPIO pins for the STM32F103 Minimum board. - * - ****************************************************************************/ - -void stm32_usbinitialize(void) -{ - /* USB Soft Connect Pullup */ - - stm32_configgpio(GPIO_USB_PULLUP); -} - -/**************************************************************************** - * Name: stm32_usbpullup - * - * Description: - * If USB is supported and the board supports a pullup via GPIO (for USB - * software connect and disconnect), then the board software must provide - * stm32_pullup. See include/nuttx/usb/usbdev.h for additional description - * of this method. Alternatively, if no pull-up GPIO the following EXTERN - * can be redefined to be NULL. - * - ****************************************************************************/ - -int stm32_usbpullup(struct usbdev_s *dev, bool enable) -{ - usbtrace(TRACE_DEVPULLUP, (uint16_t)enable); - stm32_gpiowrite(GPIO_USB_PULLUP, enable); - return OK; -} - -/**************************************************************************** - * Name: stm32_usbsuspend - * - * Description: - * Board logic must provide the stm32_usbsuspend logic if the USBDEV driver - * is used. This function is called whenever the USB enters or leaves - * suspend mode. This is an opportunity for the board logic to shutdown - * clocks, power, etc. while the USB is suspended. - * - ****************************************************************************/ - -void stm32_usbsuspend(struct usbdev_s *dev, bool resume) -{ - uinfo("resume: %d\n", resume); -} diff --git a/boards/arm/stm32/stm32f103-minimum/src/stm32_usbmsc.c b/boards/arm/stm32/stm32f103-minimum/src/stm32_usbmsc.c deleted file mode 100644 index 3ab090b7c655c..0000000000000 --- a/boards/arm/stm32/stm32f103-minimum/src/stm32_usbmsc.c +++ /dev/null @@ -1,71 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f103-minimum/src/stm32_usbmsc.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include - -#include "stm32.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -#ifndef CONFIG_SYSTEM_USBMSC_DEVMINOR1 -# define CONFIG_SYSTEM_USBMSC_DEVMINOR1 0 -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_usbmsc_initialize - * - * Description: - * Perform architecture specific initialization of the USB MSC device. - * - ****************************************************************************/ - -int board_usbmsc_initialize(int port) -{ - /* If system/usbmsc is built as an NSH command, then SD slot should - * already have been initialized. - * In this case, there is nothing further to be done here. - */ - -#ifndef CONFIG_NSH_BUILTIN_APPS - return stm32_sdinitialize(CONFIG_SYSTEM_USBMSC_DEVMINOR1); -#else - return OK; -#endif -} diff --git a/boards/arm/stm32/stm32f103-minimum/src/stm32_userleds.c b/boards/arm/stm32/stm32f103-minimum/src/stm32_userleds.c deleted file mode 100644 index 7ae565c5719b7..0000000000000 --- a/boards/arm/stm32/stm32f103-minimum/src/stm32_userleds.c +++ /dev/null @@ -1,102 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f103-minimum/src/stm32_userleds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include - -#include "chip.h" -#include "stm32.h" -#include "stm32f103_minimum.h" - -#ifndef CONFIG_ARCH_LEDS - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* This array maps an LED number to GPIO pin configuration */ - -static const uint32_t g_ledcfg[BOARD_NLEDS] = -{ - GPIO_LED1, -}; - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_userled_initialize - ****************************************************************************/ - -uint32_t board_userled_initialize(void) -{ - int i; - - /* Configure LED GPIOs for output */ - - for (i = 0; i < BOARD_NLEDS; i++) - { - stm32_configgpio(g_ledcfg[i]); - } - - return BOARD_NLEDS; -} - -/**************************************************************************** - * Name: board_userled - ****************************************************************************/ - -void board_userled(int led, bool ledon) -{ - if ((unsigned)led < BOARD_NLEDS) - { - stm32_gpiowrite(g_ledcfg[led], ledon); - } -} - -/**************************************************************************** - * Name: board_userled_all - ****************************************************************************/ - -void board_userled_all(uint32_t ledset) -{ - int i; - - /* Configure LED GPIOs for output */ - - for (i = 0; i < BOARD_NLEDS; i++) - { - stm32_gpiowrite(g_ledcfg[i], (ledset & (1 << i)) != 0); - } -} - -#endif /* !CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/stm32f103-minimum/src/stm32_w25.c b/boards/arm/stm32/stm32f103-minimum/src/stm32_w25.c deleted file mode 100644 index 3303c6eabbf4b..0000000000000 --- a/boards/arm/stm32/stm32f103-minimum/src/stm32_w25.c +++ /dev/null @@ -1,279 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f103-minimum/src/stm32_w25.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include - -#ifdef CONFIG_STM32_SPI1 -# include -# include -# include -# include -#endif - -#include "stm32_spi.h" - -#include "stm32f103_minimum.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Debug ********************************************************************/ - -/* Non-standard debug that may be enabled just for testing the watchdog - * timer - */ - -#define W25_SPI_PORT 1 - -/* Configuration ************************************************************/ - -/* Can't support the W25 device if it SPI1 or W25 support is not enabled */ - -#define HAVE_W25 1 -#if !defined(CONFIG_STM32_SPI1) || !defined(CONFIG_MTD_W25) -# undef HAVE_W25 -#endif - -/* Can't support W25 features if mountpoints are disabled */ - -#if defined(CONFIG_DISABLE_MOUNTPOINT) -# undef HAVE_W25 -#endif - -/* Can't support both FAT and SMARTFS */ - -#if defined(CONFIG_FS_FAT) && defined(CONFIG_FS_SMARTFS) -# warning "Can't support both FAT and SMARTFS -- using FAT" -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_w25initialize - * - * Description: - * Initialize and register the W25 FLASH file system. - * - ****************************************************************************/ - -int stm32_w25initialize(int minor) -{ - int ret; -#ifdef HAVE_W25 - struct spi_dev_s *spi; - struct mtd_dev_s *mtd; - struct mtd_geometry_s geo; -#if defined(CONFIG_MTD_PARTITION_NAMES) - const char *partname = CONFIG_STM32F103MINIMUM_FLASH_PART_NAMES; -#endif - - /* Get the SPI port */ - - spi = stm32_spibus_initialize(W25_SPI_PORT); - if (!spi) - { - syslog(LOG_ERR, "ERROR: Failed to initialize SPI port %d\n", - W25_SPI_PORT); - return -ENODEV; - } - - /* Now bind the SPI interface to the W25 SPI FLASH driver */ - - mtd = w25_initialize(spi); - if (!mtd) - { - syslog(LOG_ERR, "ERROR: Failed to bind SPI port %d to the Winbond" - "W25 FLASH driver\n", W25_SPI_PORT); - return -ENODEV; - } - -#ifndef CONFIG_FS_SMARTFS - /* Register the MTD driver */ - - char path[32]; - snprintf(path, sizeof(path), "/dev/mtdblock%d", minor); - ret = register_mtddriver(path, mtd, 0755, NULL); - if (ret < 0) - { - syslog(LOG_ERR, - "ERROR: Failed to register the MTD driver %s, ret %d\n", - path, ret); - return ret; - } -#else - /* Initialize to provide SMARTFS on the MTD interface */ - - /* Get the geometry of the FLASH device */ - - ret = mtd->ioctl(mtd, MTDIOC_GEOMETRY, (unsigned long)((uintptr_t)&geo)); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: mtd->ioctl failed: %d\n", ret); - return ret; - } - -#ifdef CONFIG_STM32F103MINIMUM_FLASH_PART - { - int partno; - int partsize; - int partoffset; - int partszbytes; - int erasesize; - const char *partstring = CONFIG_STM32F103MINIMUM_FLASH_PART_LIST; - const char *ptr; - struct mtd_dev_s *mtd_part; - char partref[16]; - - /* Now create a partition on the FLASH device */ - - partno = 0; - ptr = partstring; - partoffset = 0; - - /* Get the Flash erase size */ - - erasesize = geo.erasesize; - - while (*ptr != '\0') - { - /* Get the partition size */ - - partsize = atoi(ptr); - partszbytes = (partsize << 10); /* partsize is defined in KB */ - - /* Check if partition size is bigger then erase block */ - - if (partszbytes < erasesize) - { - syslog(LOG_ERR, - "ERROR: Partition size is lesser than erasesize!\n"); - return -1; - } - - /* Check if partition size is multiple of erase block */ - - if ((partszbytes % erasesize) != 0) - { - syslog(LOG_ERR, - "ERROR: Partition size isn't multiple of erasesize!\n"); - return -1; - } - - mtd_part = mtd_partition(mtd, partoffset, partszbytes / erasesize); - partoffset += partszbytes / erasesize; - -#ifdef CONFIG_STM32F103MINIMUM_FLASH_CONFIG_PART - /* Test if this is the config partition */ - - if (CONFIG_STM32F103MINIMUM_FLASH_CONFIG_PART_NUMBER == partno) - { - /* Register the partition as the config device */ - - mtdconfig_register(mtd_part); - } - else -#endif - { - /* Now initialize a SMART Flash block device and bind it - * to the MTD device. - */ - -#if defined(CONFIG_MTD_SMART) && defined(CONFIG_FS_SMARTFS) - snprintf(partref, sizeof(partref), "p%d", partno); - smart_initialize(CONFIG_STM32F103MINIMUM_FLASH_MINOR, - mtd_part, partref); -#endif - } - - /* Set the partition name */ - -#if defined(CONFIG_MTD_PARTITION_NAMES) - if (!mtd_part) - { - syslog(LOG_ERR, "Error: failed to create partition %s\n", - partname); - return -1; - } - - mtd_setpartitionname(mtd_part, partname); - - /* Now skip to next name. We don't need to split the string here - * because the MTD partition logic will only display names up to - * the comma, thus allowing us to use a single static name - * in the code. - */ - - while (*partname != ',' && *partname != '\0') - { - /* Skip to next ',' */ - - partname++; - } - - if (*partname == ',') - { - partname++; - } -#endif - - /* Update the pointer to point to the next size in the list */ - - while ((*ptr >= '0') && (*ptr <= '9')) - { - ptr++; - } - - if (*ptr == ',') - { - ptr++; - } - - /* Increment the part number */ - - partno++; - } - } -#else /* CONFIG_STM32F103MINIMUM_FLASH_PART */ - - /* Configure the device with no partition support */ - - smart_initialize(CONFIG_STM32F103MINIMUM_FLASH_MINOR, mtd, NULL); - -#endif /* CONFIG_STM32F103MINIMUM_FLASH_PART */ -#endif /* CONFIG_FS_SMARTFS */ -#endif /* HAVE_W25 */ - - return OK; -} diff --git a/boards/arm/stm32/stm32f334-disco/CMakeLists.txt b/boards/arm/stm32/stm32f334-disco/CMakeLists.txt deleted file mode 100644 index 1d87be10fd0f0..0000000000000 --- a/boards/arm/stm32/stm32f334-disco/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/stm32f334-disco/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32/stm32f334-disco/configs/buckboost/defconfig b/boards/arm/stm32/stm32f334-disco/configs/buckboost/defconfig deleted file mode 100644 index 8c31ee1302b90..0000000000000 --- a/boards/arm/stm32/stm32f334-disco/configs/buckboost/defconfig +++ /dev/null @@ -1,128 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_SYSTEM_DD is not set -CONFIG_ADC=y -CONFIG_ANALOG=y -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f334-disco" -CONFIG_ARCH_BOARD_STM32F334_DISCO=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F334C8=y -CONFIG_ARCH_HIPRI_INTERRUPT=y -CONFIG_ARCH_RAMVECTORS=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARDCTL=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_DEBUG_FULLOPT=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_DISABLE_ENVIRON=y -CONFIG_DISABLE_MQUEUE=y -CONFIG_DISABLE_POSIX_TIMERS=y -CONFIG_DISABLE_PTHREAD=y -CONFIG_DRIVERS_SMPS=y -CONFIG_EXAMPLES_SMPS=y -CONFIG_EXAMPLES_SMPS_DEVPATH="/dev/smps0" -CONFIG_EXAMPLES_SMPS_IN_VOLTAGE_LIMIT=10000 -CONFIG_EXAMPLES_SMPS_OUT_CURRENT_LIMIT=100 -CONFIG_EXAMPLES_SMPS_OUT_POWER_LIMIT=100 -CONFIG_EXAMPLES_SMPS_OUT_VOLTAGE_DEFAULT=5000 -CONFIG_EXAMPLES_SMPS_OUT_VOLTAGE_LIMIT=10000 -CONFIG_EXAMPLES_SMPS_TIME_DEFAULT=10 -CONFIG_FDCLONE_STDIO=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INIT_STACKSIZE=1024 -CONFIG_INTELHEX_BINARY=y -CONFIG_LIBDSP=y -CONFIG_LIBM=y -CONFIG_LINE_MAX=64 -CONFIG_NAME_MAX=16 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_DISABLE_BASENAME=y -CONFIG_NSH_DISABLE_CAT=y -CONFIG_NSH_DISABLE_CD=y -CONFIG_NSH_DISABLE_CMP=y -CONFIG_NSH_DISABLE_CP=y -CONFIG_NSH_DISABLE_DF=y -CONFIG_NSH_DISABLE_DIRNAME=y -CONFIG_NSH_DISABLE_ECHO=y -CONFIG_NSH_DISABLE_EXEC=y -CONFIG_NSH_DISABLE_EXIT=y -CONFIG_NSH_DISABLE_FREE=y -CONFIG_NSH_DISABLE_GET=y -CONFIG_NSH_DISABLE_HELP=y -CONFIG_NSH_DISABLE_HEXDUMP=y -CONFIG_NSH_DISABLE_KILL=y -CONFIG_NSH_DISABLE_LOSETUP=y -CONFIG_NSH_DISABLE_LS=y -CONFIG_NSH_DISABLE_MKDIR=y -CONFIG_NSH_DISABLE_MKRD=y -CONFIG_NSH_DISABLE_MOUNT=y -CONFIG_NSH_DISABLE_MV=y -CONFIG_NSH_DISABLE_PUT=y -CONFIG_NSH_DISABLE_PWD=y -CONFIG_NSH_DISABLE_RM=y -CONFIG_NSH_DISABLE_RMDIR=y -CONFIG_NSH_DISABLE_SET=y -CONFIG_NSH_DISABLE_SLEEP=y -CONFIG_NSH_DISABLE_SOURCE=y -CONFIG_NSH_DISABLE_TEST=y -CONFIG_NSH_DISABLE_TIME=y -CONFIG_NSH_DISABLE_UMOUNT=y -CONFIG_NSH_DISABLE_UNAME=y -CONFIG_NSH_DISABLE_UNSET=y -CONFIG_NSH_DISABLE_USLEEP=y -CONFIG_NSH_DISABLE_WGET=y -CONFIG_NSH_DISABLE_XD=y -CONFIG_NSH_FILEIOSIZE=256 -CONFIG_NSH_READLINE=y -CONFIG_POSIX_SPAWN_DEFAULT_STACKSIZE=512 -CONFIG_PTHREAD_STACK_DEFAULT=1024 -CONFIG_PTHREAD_STACK_MIN=1024 -CONFIG_RAM_SIZE=12288 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_SMPS_HAVE_INPUT_VOLTAGE=y -CONFIG_SMPS_HAVE_OUTPUT_VOLTAGE=y -CONFIG_START_DAY=6 -CONFIG_START_MONTH=12 -CONFIG_START_YEAR=2011 -CONFIG_STDIO_BUFFER_SIZE=128 -CONFIG_STM32_ADC1=y -CONFIG_STM32_ADC1_INJECTED_CHAN=2 -CONFIG_STM32_ADC_CHANGE_SAMPLETIME=y -CONFIG_STM32_ADC_LL_OPS=y -CONFIG_STM32_ADC_NOIRQ=y -CONFIG_STM32_CCMEXCLUDE=y -CONFIG_STM32_HRTIM1=y -CONFIG_STM32_HRTIM_ADC1_TRG2=y -CONFIG_STM32_HRTIM_ADC=y -CONFIG_STM32_HRTIM_CLK_FROM_PLL=y -CONFIG_STM32_HRTIM_DEADTIME=y -CONFIG_STM32_HRTIM_DISABLE_CHARDRV=y -CONFIG_STM32_HRTIM_PWM=y -CONFIG_STM32_HRTIM_TIMA=y -CONFIG_STM32_HRTIM_TIMA_DT=y -CONFIG_STM32_HRTIM_TIMA_PWM=y -CONFIG_STM32_HRTIM_TIMA_PWM_CH1=y -CONFIG_STM32_HRTIM_TIMA_PWM_CH2=y -CONFIG_STM32_HRTIM_TIMB=y -CONFIG_STM32_HRTIM_TIMB_DT=y -CONFIG_STM32_HRTIM_TIMB_PWM=y -CONFIG_STM32_HRTIM_TIMB_PWM_CH1=y -CONFIG_STM32_HRTIM_TIMB_PWM_CH2=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_PWR=y -CONFIG_STM32_USART2=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/stm32f334-disco/configs/nsh/defconfig b/boards/arm/stm32/stm32f334-disco/configs/nsh/defconfig deleted file mode 100644 index db3bc11cbbb2d..0000000000000 --- a/boards/arm/stm32/stm32f334-disco/configs/nsh/defconfig +++ /dev/null @@ -1,88 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_SYSTEM_DD is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f334-disco" -CONFIG_ARCH_BOARD_STM32F334_DISCO=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F334C8=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_ARM_TOOLCHAIN_BUILDROOT=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_DEBUG_FEATURES=y -CONFIG_DEBUG_FULLOPT=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_DISABLE_ENVIRON=y -CONFIG_DISABLE_MQUEUE=y -CONFIG_DISABLE_POSIX_TIMERS=y -CONFIG_DISABLE_PTHREAD=y -CONFIG_EXAMPLES_HELLO=y -CONFIG_FDCLONE_STDIO=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INIT_STACKSIZE=1024 -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_NAME_MAX=16 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_DISABLE_BASENAME=y -CONFIG_NSH_DISABLE_CAT=y -CONFIG_NSH_DISABLE_CD=y -CONFIG_NSH_DISABLE_CMP=y -CONFIG_NSH_DISABLE_CP=y -CONFIG_NSH_DISABLE_DF=y -CONFIG_NSH_DISABLE_DIRNAME=y -CONFIG_NSH_DISABLE_EXEC=y -CONFIG_NSH_DISABLE_EXIT=y -CONFIG_NSH_DISABLE_GET=y -CONFIG_NSH_DISABLE_HEXDUMP=y -CONFIG_NSH_DISABLE_KILL=y -CONFIG_NSH_DISABLE_LOSETUP=y -CONFIG_NSH_DISABLE_LS=y -CONFIG_NSH_DISABLE_MKDIR=y -CONFIG_NSH_DISABLE_MKRD=y -CONFIG_NSH_DISABLE_MOUNT=y -CONFIG_NSH_DISABLE_MV=y -CONFIG_NSH_DISABLE_PUT=y -CONFIG_NSH_DISABLE_PWD=y -CONFIG_NSH_DISABLE_RM=y -CONFIG_NSH_DISABLE_RMDIR=y -CONFIG_NSH_DISABLE_SET=y -CONFIG_NSH_DISABLE_SLEEP=y -CONFIG_NSH_DISABLE_SOURCE=y -CONFIG_NSH_DISABLE_TEST=y -CONFIG_NSH_DISABLE_TIME=y -CONFIG_NSH_DISABLE_UMOUNT=y -CONFIG_NSH_DISABLE_UNAME=y -CONFIG_NSH_DISABLE_UNSET=y -CONFIG_NSH_DISABLE_USLEEP=y -CONFIG_NSH_DISABLE_WGET=y -CONFIG_NSH_DISABLE_XD=y -CONFIG_NSH_FILEIOSIZE=256 -CONFIG_NSH_READLINE=y -CONFIG_POSIX_SPAWN_DEFAULT_STACKSIZE=512 -CONFIG_PTHREAD_STACK_DEFAULT=1024 -CONFIG_PTHREAD_STACK_MIN=1024 -CONFIG_RAM_SIZE=12288 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=6 -CONFIG_START_MONTH=12 -CONFIG_START_YEAR=2011 -CONFIG_STM32_CCMEXCLUDE=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_PWR=y -CONFIG_STM32_USART2=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/stm32f334-disco/configs/powerled/defconfig b/boards/arm/stm32/stm32f334-disco/configs/powerled/defconfig deleted file mode 100644 index 10a5ed5968f49..0000000000000 --- a/boards/arm/stm32/stm32f334-disco/configs/powerled/defconfig +++ /dev/null @@ -1,98 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_DISABLE_POSIX_TIMERS is not set -# CONFIG_DISABLE_PSEUDOFS_OPERATIONS is not set -# CONFIG_NSH_DISABLEBG is not set -# CONFIG_NSH_DISABLESCRIPT is not set -# CONFIG_NSH_DISABLE_DMESG is not set -# CONFIG_NSH_DISABLE_ECHO is not set -# CONFIG_NSH_DISABLE_ENV is not set -# CONFIG_NSH_DISABLE_EXPORT is not set -# CONFIG_NSH_DISABLE_FREE is not set -# CONFIG_NSH_DISABLE_ITEF is not set -# CONFIG_NSH_DISABLE_LOOPS is not set -# CONFIG_NSH_DISABLE_LS is not set -# CONFIG_NSH_DISABLE_PRINTF is not set -# CONFIG_NSH_DISABLE_SEMICOLON is not set -# CONFIG_NSH_DISABLE_TRUNCATE is not set -# CONFIG_NSH_DISABLE_UPTIME is not set -CONFIG_ANALOG=y -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f334-disco" -CONFIG_ARCH_BOARD_STM32F334_DISCO=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F334C8=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_ARM_TOOLCHAIN_BUILDROOT=y -CONFIG_BOARDCTL=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_COMP=y -CONFIG_DAC=y -CONFIG_DEBUG_FULLOPT=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_DEFAULT_SMALL=y -CONFIG_DRIVERS_POWERLED=y -CONFIG_EXAMPLES_POWERLED=y -CONFIG_EXAMPLES_POWERLED_CURRENT_LIMIT=100 -CONFIG_EXAMPLES_POWERLED_DEVPATH="/dev/powerled0" -CONFIG_FDCLONE_STDIO=y -CONFIG_FILE_STREAM=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INIT_STACKSIZE=1024 -CONFIG_INTELHEX_BINARY=y -CONFIG_LIBC_FLOATINGPOINT=y -CONFIG_LIBM=y -CONFIG_NAME_MAX=16 -CONFIG_NSH_ARGCAT=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=256 -CONFIG_NSH_MAXARGUMENTS=16 -CONFIG_POSIX_SPAWN_DEFAULT_STACKSIZE=512 -CONFIG_PREALLOC_TIMERS=2 -CONFIG_PTHREAD_STACK_DEFAULT=1024 -CONFIG_PTHREAD_STACK_MIN=1024 -CONFIG_RAM_SIZE=12288 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_SIG_PREALLOC_IRQ_ACTIONS=8 -CONFIG_START_DAY=6 -CONFIG_START_MONTH=12 -CONFIG_START_YEAR=2011 -CONFIG_STM32_COMP4=y -CONFIG_STM32_DAC1=y -CONFIG_STM32_DAC1CH1=y -CONFIG_STM32_DAC1CH1_DMA=y -CONFIG_STM32_DAC1CH1_DMA_BUFFER_SIZE=5 -CONFIG_STM32_DAC1CH1_DMA_EXTERNAL=y -CONFIG_STM32_DMA1=y -CONFIG_STM32_HRTIM1=y -CONFIG_STM32_HRTIM_BURST=y -CONFIG_STM32_HRTIM_CLK_FROM_PLL=y -CONFIG_STM32_HRTIM_DISABLE_CHARDRV=y -CONFIG_STM32_HRTIM_DMA=y -CONFIG_STM32_HRTIM_EEV2=y -CONFIG_STM32_HRTIM_EVENTS=y -CONFIG_STM32_HRTIM_PWM=y -CONFIG_STM32_HRTIM_TIMC=y -CONFIG_STM32_HRTIM_TIMC_BURST=y -CONFIG_STM32_HRTIM_TIMC_BURST_CH1=y -CONFIG_STM32_HRTIM_TIMC_DMA=y -CONFIG_STM32_HRTIM_TIMC_PWM=y -CONFIG_STM32_HRTIM_TIMC_PWM_CH1=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_PWR=y -CONFIG_STM32_USART2=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/stm32f334-disco/include/board.h b/boards/arm/stm32/stm32f334-disco/include/board.h deleted file mode 100644 index b1b39e94d8f7c..0000000000000 --- a/boards/arm/stm32/stm32f334-disco/include/board.h +++ /dev/null @@ -1,337 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f334-disco/include/board.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __BOARDS_ARM_STM32_STM32F334_DISCO_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32_STM32F334_DISCO_INCLUDE_BOARD_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#ifndef __ASSEMBLY__ -# include -# include -#endif - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Clocking *****************************************************************/ - -/* HSI - Internal 8 MHz RC Oscillator - * LSI - 32 KHz RC - * HSE - 8 MHz from MCO output of ST-LINK - * LSE - 32.768 kHz - */ - -#define STM32_BOARD_XTAL 8000000ul - -#define STM32_HSI_FREQUENCY 8000000ul -#define STM32_LSI_FREQUENCY 32000 /* Between 30kHz and 60kHz */ -#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL -#define STM32_LSE_FREQUENCY 32768 /* X2 on board */ - -/* PLL source is HSE/1, PLL multiplier is 9: - * PLL frequency is 8MHz (XTAL) x 9 = 72MHz - */ - -#define STM32_CFGR_PLLSRC RCC_CFGR_PLLSRC -#define STM32_CFGR_PLLXTPRE 0 -#define STM32_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx9 -#define STM32_PLL_FREQUENCY (9*STM32_BOARD_XTAL) - -/* Use the PLL and set the SYSCLK source to be the PLL */ - -#define STM32_SYSCLK_SW RCC_CFGR_SW_PLL -#define STM32_SYSCLK_SWS RCC_CFGR_SWS_PLL -#define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY - -/* AHB clock (HCLK) is SYSCLK (72MHz) */ - -#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK -#define STM32_HCLK_FREQUENCY STM32_PLL_FREQUENCY - -/* APB2 clock (PCLK2) is HCLK (72MHz) */ - -#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK -#define STM32_PCLK2_FREQUENCY STM32_HCLK_FREQUENCY -#define STM32_APB2_CLKIN (STM32_PCLK2_FREQUENCY) - -/* APB2 timers 1, 8, 15-17 and HRTIM1 will receive PCLK2. */ - -/* Timers driven from APB2 will be PCLK2 */ - -#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB1_TIM15_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB1_TIM16_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB1_TIM17_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB1_THRTIM1_CLKIN (STM32_PCLK2_FREQUENCY) - -/* APB1 clock (PCLK1) is HCLK/2 (36MHz) */ - -#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd2 -#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/2) - -/* APB1 timers 2-7 will be twice PCLK1 */ - -#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) - -/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx - * otherwise frequency is 2xAPBx. - * Note: TIM1,8 are on APB2, others on APB1 - */ - -#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM15_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM16_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM17_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM2_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM3_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM5_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM6_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM7_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_HRTIM1_FREQUENCY STM32_HCLK_FREQUENCY - -/* LED definitions **********************************************************/ - -/* LED index values for use with board_userled() */ - -#define BOARD_LED1 0 -#define BOARD_LED2 1 -#define BOARD_LED3 2 -#define BOARD_LED4 3 -#define BOARD_NLEDS 4 - -/* LED bits for use with board_userled_all() */ - -#define BOARD_LED1_BIT (1 << BOARD_LED1) -#define BOARD_LED2_BIT (1 << BOARD_LED2) -#define BOARD_LED3_BIT (1 << BOARD_LED3) -#define BOARD_LED4_BIT (1 << BOARD_LED4) - -/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the 4 LEDs on - * board the stm32f334-disco. The following definitions describe how NuttX - * controls the LEDs: - */ - -#define LED_STARTED 0 /* LED1 */ -#define LED_HEAPALLOCATE 1 /* LED2 */ -#define LED_IRQSENABLED 2 /* LED1 + LED2 */ -#define LED_STACKCREATED 3 /* LED3 */ -#define LED_INIRQ 4 /* LED1 + LED3 */ -#define LED_SIGNAL 5 /* LED2 + LED3 */ -#define LED_ASSERTION 6 /* LED1 + LED2 + LED3 */ -#define LED_PANIC 7 /* N/C + N/C + N/C + LED4 */ - -/* Button definitions *******************************************************/ - -/* The STM32F334-DISCO supports two buttons; only one button is controllable - * by software: - * - * B1 USER: user button connected to the I/O PA0 of the STM32F334R8. - * B2 RESET: push button connected to NRST is used to RESET the - * STM32F334R8. - */ - -#define BUTTON_USER 0 -#define NUM_BUTTONS 1 - -#define BUTTON_USER_BIT (1 << BUTTON_USER) - -/* Alternate function pin selections ****************************************/ - -/* CAN */ - -#define GPIO_CAN1_RX (GPIO_CAN_RX_2|GPIO_SPEED_50MHz) -#define GPIO_CAN1_TX (GPIO_CAN_TX_2|GPIO_SPEED_50MHz) - -/* I2C */ - -#define GPIO_I2C1_SCL (GPIO_I2C1_SCL_3|GPIO_SPEED_50MHz) -#define GPIO_I2C1_SDA (GPIO_I2C1_SDA_3|GPIO_SPEED_50MHz) - -/* SPI */ - -#define GPIO_SPI1_MISO (GPIO_SPI1_MISO_1|GPIO_SPEED_50MHz) -#define GPIO_SPI1_MOSI (GPIO_SPI1_MOSI_1|GPIO_SPEED_50MHz) -#define GPIO_SPI1_SCK (GPIO_SPI1_SCK_1|GPIO_SPEED_50MHz) - -/* TIM */ - -#define GPIO_TIM2_CH2OUT (GPIO_TIM2_CH2OUT_2|GPIO_SPEED_50MHz) -#define GPIO_TIM2_CH3OUT (GPIO_TIM2_CH3OUT_3|GPIO_SPEED_50MHz) - -#define GPIO_TIM3_CH1OUT (GPIO_TIM3_CH1OUT_2|GPIO_SPEED_50MHz) -#define GPIO_TIM3_CH2OUT (GPIO_TIM3_CH2OUT_4|GPIO_SPEED_50MHz) - -#define GPIO_TIM4_CH1OUT (GPIO_TIM4_CH1OUT_2|GPIO_SPEED_50MHz) - -/* USART */ - -#define GPIO_USART2_RX (GPIO_USART2_RX_3|GPIO_SPEED_50MHz) /* PB4 */ -#define GPIO_USART2_TX (GPIO_USART2_TX_3|GPIO_SPEED_50MHz) /* PB3 */ - -/* Board configuration for powerled example: - * - Set HRTIM TIMC output 1 (PB12) on PERIOD. - * - Reset HRTIM TIMC output 1 on HRTIM EEV2. - * - HRTIM EEV2 is connected to COMP4 output which works as current limit. - * - COMP4 inverting input is connected to DAC1CH1 output. - * - COMP4 non-inverting input (PB1) is connected to current sense - * resistor (1 Ohm). - * - DAC1CH1 DMA transfer is triggered by HRTIM TIMC events, which is used - * to provide slope compensation. - */ - -#if defined(CONFIG_EXAMPLES_POWERLED) - -/* Comparators configuration ************************************************/ - -#define COMP4_INM COMP_INMSEL_DAC1CH1 - -/* HRTIM configuration ******************************************************/ - -#define HRTIM_TIMC_PRESCALER HRTIM_PRESCALER_1 -#define HRTIM_TIMC_MODE HRTIM_MODE_CONT -#define HRTIM_TIMC_DMA (HRTIM_DMA_REP|HRTIM_DMA_CMP1|HRTIM_DMA_CMP2| \ - HRTIM_DMA_CMP3|HRTIM_DMA_CMP4) -#define HRTIM_TIMC_CH1_SET HRTIM_OUT_SET_PER -#define HRTIM_TIMC_CH1_RST HRTIM_OUT_RST_EXTEVNT2 -#define HRTIM_TIMC_CH1_IDLE_STATE HRTIM_IDLE_INACTIVE - -#define HRTIM_EEV_SAMPLING HRTIM_EEV_SAMPLING_d1 -#define HRTIM_EEV2_SRC HRTIM_EEV_SRC_ANALOG -#define HRTIM_EEV2_FILTER HRTIM_EEV_DISABLE -#define HRTIM_EEV2_POL HRTIM_EEV_POL_HIGH -#define HRTIM_EEV2_SEN HRTIM_EEV_SEN_LEVEL -#define HRTIM_EEV2_MODE HRTIM_EEV_MODE_FAST - -#define HRTIM_BURST_CLOCK HRTIM_BURST_CLOCK_HRTIM -#define HRTIM_BURST_PRESCALER HRTIM_BURST_PRESCALER_1 -#define HRTIM_BURST_TRIGGERS 0 - -/* DMA channels *************************************************************/ - -/* DAC */ - -#define DAC1CH1_DMA_CHAN DMACHAN_HRTIM1_C - -#endif /* CONFIG_EXAMPLES_POWERLED */ - -/* Board configuration for SMPS example: - * PA8 - HRTIM_CHA1 - * PA9 - HRTIM_CHA2 - * PA10 - HRTIM_CHB1 - * PA11 - HRTIM_CHB2 - * VIN - ADC Channel 2 (PA1) - * VOUT - ADC Channel 4 (PA3) - */ - -#if defined(CONFIG_EXAMPLES_SMPS) - -/* HRTIM configuration ******************************************************/ - -/* Timer A configuration - Buck operations */ - -#define HRTIM_TIMA_PRESCALER HRTIM_PRESCALER_1 -#define HRTIM_TIMA_MODE HRTIM_MODE_CONT -#define HRTIM_TIMA_UPDATE 0 -#define HRTIM_TIMA_RESET 0 - -#define HRTIM_TIMA_CH1_SET HRTIM_OUT_SET_NONE -#define HRTIM_TIMA_CH1_RST HRTIM_OUT_RST_NONE -#define HRTIM_TIMA_CH2_SET HRTIM_OUT_SET_NONE -#define HRTIM_TIMA_CH2_RST HRTIM_OUT_RST_NONE - -#define HRTIM_TIMA_DT_FSLOCK HRTIM_DT_LOCK -#define HRTIM_TIMA_DT_RSLOCK HRTIM_DT_LOCK -#define HRTIM_TIMA_DT_FVLOCK HRTIM_DT_RW -#define HRTIM_TIMA_DT_RVLOCK HRTIM_DT_RW -#define HRTIM_TIMA_DT_FSIGN HRTIM_DT_SIGN_POSITIVE -#define HRTIM_TIMA_DT_RSIGN HRTIM_DT_SIGN_POSITIVE -#define HRTIM_TIMA_DT_PRESCALER HRTIM_DEADTIME_PRESCALER_1 - -/* Timer B configuration - Boost operations */ - -#define HRTIM_TIMB_PRESCALER HRTIM_PRESCALER_1 -#define HRTIM_TIMB_MODE HRTIM_MODE_CONT -#define HRTIM_TIMB_UPDATE 0 -#define HRTIM_TIMB_RESET 0 - -#define HRTIM_TIMB_CH1_SET HRTIM_OUT_SET_NONE -#define HRTIM_TIMB_CH1_RST HRTIM_OUT_RST_NONE -#define HRTIM_TIMB_CH2_SET HRTIM_OUT_SET_NONE -#define HRTIM_TIMB_CH2_RST HRTIM_OUT_RST_NONE - -#define HRTIM_TIMB_DT_FSLOCK HRTIM_DT_LOCK -#define HRTIM_TIMB_DT_RSLOCK HRTIM_DT_LOCK -#define HRTIM_TIMB_DT_FVLOCK HRTIM_DT_RW -#define HRTIM_TIMB_DT_RVLOCK HRTIM_DT_RW -#define HRTIM_TIMB_DT_FSIGN HRTIM_DT_SIGN_POSITIVE -#define HRTIM_TIMB_DT_RSIGN HRTIM_DT_SIGN_POSITIVE -#define HRTIM_TIMB_DT_PRESCALER HRTIM_DEADTIME_PRESCALER_1 - -#define HRTIM_ADC_TRG2 HRTIM_ADCTRG24_AC4 - -/* DMA channels *************************************************************/ - -#endif /* CONFIG_EXAMPLES_SMPS */ - -/* HRTIM1 */ - -#define GPIO_HRTIM1_CHA1 GPIO_HRTIM1_CHA1_0 -#define GPIO_HRTIM1_CHA2 GPIO_HRTIM1_CHA2_0 -#define GPIO_HRTIM1_CHB1 GPIO_HRTIM1_CHB1_0 -#define GPIO_HRTIM1_CHB2 GPIO_HRTIM1_CHB2_0 -#define GPIO_HRTIM1_CHC1 GPIO_HRTIM1_CHC1_0 -#define GPIO_HRTIM1_CHC2 GPIO_HRTIM1_CHC2_0 -#define GPIO_HRTIM1_CHD1 GPIO_HRTIM1_CHD1_0 -#define GPIO_HRTIM1_CHD2 GPIO_HRTIM1_CHD2_0 -#define GPIO_HRTIM1_CHE1 GPIO_HRTIM1_CHE1_0 -#define GPIO_HRTIM1_CHE2 GPIO_HRTIM1_CHE2_0 -#define GPIO_HRTIM1_EEV1 GPIO_HRTIM1_EEV1_0 -#define GPIO_HRTIM1_EEV2 GPIO_HRTIM1_EEV2_0 -#define GPIO_HRTIM1_EEV3 GPIO_HRTIM1_EEV3_0 -#define GPIO_HRTIM1_FLT1 GPIO_HRTIM1_FLT1_0 -#define GPIO_HRTIM1_FLT2 GPIO_HRTIM1_FLT2_0 -#define GPIO_HRTIM1_FLT3 GPIO_HRTIM1_FLT3_0 -#define GPIO_HRTIM1_FLT4 GPIO_HRTIM1_FLT4_0 -#define GPIO_HRTIM1_FLT5 GPIO_HRTIM1_FLT5_0 - -/* COMP */ - -#define GPIO_COMP2_INP GPIO_COMP2_INP_0 -#define GPIO_COMP4_INP GPIO_COMP4_INP_0 -#define GPIO_COMP6_INP GPIO_COMP6_INP_0 - -/* DAC */ - -#define GPIO_DAC1_OUT1 GPIO_DAC1_OUT1_0 -#define GPIO_DAC1_OUT2 GPIO_DAC1_OUT2_0 - -#endif /* __BOARDS_ARM_STM32_STM32F334_DISCO_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32/stm32f334-disco/scripts/Make.defs b/boards/arm/stm32/stm32f334-disco/scripts/Make.defs deleted file mode 100644 index 3312eb4725896..0000000000000 --- a/boards/arm/stm32/stm32f334-disco/scripts/Make.defs +++ /dev/null @@ -1,41 +0,0 @@ -############################################################################ -# boards/arm/stm32/stm32f334-disco/scripts/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/.config -include $(TOPDIR)/tools/Config.mk -include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs - -LDSCRIPT = ld.script -ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) - -ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 - -CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) -CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) -CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -AFLAGS := $(CFLAGS) -D__ASSEMBLY__ - -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections -LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32/stm32f334-disco/scripts/ld.script b/boards/arm/stm32/stm32f334-disco/scripts/ld.script deleted file mode 100644 index 4a28638fbc2ae..0000000000000 --- a/boards/arm/stm32/stm32f334-disco/scripts/ld.script +++ /dev/null @@ -1,127 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f334-disco/scripts/ld.script - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* The STM32F334C8 has 64Kb of FLASH beginning at address 0x0800:0000, - * 12Kb of SRAM and 4Kb of CCM SRAM. - * - * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 - * where the code expects to begin execution by jumping to the entry point in - * the 0x0800:0000 address range. - */ - -MEMORY -{ - flash (rx) : ORIGIN = 0x08000000, LENGTH = 64K - sram (rwx) : ORIGIN = 0x20000000, LENGTH = 12K -} - -OUTPUT_ARCH(arm) -EXTERN(_vectors) -ENTRY(_stext) -SECTIONS -{ - .text : { - _stext = ABSOLUTE(.); - *(.vectors) - *(.text .text.*) - *(.fixup) - *(.gnu.warning) - *(.rodata .rodata.*) - *(.gnu.linkonce.t.*) - *(.glue_7) - *(.glue_7t) - *(.got) - *(.gcc_except_table) - *(.gnu.linkonce.r.*) - _etext = ABSOLUTE(.); - } > flash - - .init_section : ALIGN(4) { - _sinit = ABSOLUTE(.); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) - KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) - _einit = ABSOLUTE(.); - } > flash - - .ARM.extab : ALIGN(4) { - *(.ARM.extab*) - } > flash - - .ARM.exidx : ALIGN(4) { - __exidx_start = ABSOLUTE(.); - *(.ARM.exidx*) - __exidx_end = ABSOLUTE(.); - } > flash - - .tdata : { - _stdata = ABSOLUTE(.); - *(.tdata .tdata.* .gnu.linkonce.td.*); - _etdata = ABSOLUTE(.); - } > flash - - .tbss : { - _stbss = ABSOLUTE(.); - *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); - _etbss = ABSOLUTE(.); - } > flash - - _eronly = ABSOLUTE(.); - - /* The RAM vector table (if present) should lie at the beginning of SRAM */ - - .ram_vectors : { - *(.ram_vectors) - } > sram - - .data : ALIGN(4) { - _sdata = ABSOLUTE(.); - *(.data .data.*) - *(.gnu.linkonce.d.*) - CONSTRUCTORS - . = ALIGN(4); - _edata = ABSOLUTE(.); - } > sram AT > flash - - .bss : ALIGN(4) { - _sbss = ABSOLUTE(.); - *(.bss .bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - . = ALIGN(4); - _ebss = ABSOLUTE(.); - } > sram - - /* Stabs debugging sections. */ - - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_info 0 : { *(.debug_info) } - .debug_line 0 : { *(.debug_line) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_aranges 0 : { *(.debug_aranges) } -} diff --git a/boards/arm/stm32/stm32f334-disco/src/CMakeLists.txt b/boards/arm/stm32/stm32f334-disco/src/CMakeLists.txt deleted file mode 100644 index b3e02b012c827..0000000000000 --- a/boards/arm/stm32/stm32f334-disco/src/CMakeLists.txt +++ /dev/null @@ -1,55 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/stm32f334-disco/src/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -set(SRCS stm32_boot.c) - -if(CONFIG_ARCH_LEDS) - list(APPEND SRCS stm32_autoleds.c) -endif() - -if(CONFIG_STM32_CAN_CHARDRIVER) - list(APPEND SRCS stm32_can.c) -endif() - -if(CONFIG_PWM) - list(APPEND SRCS stm32_pwm.c) -endif() - -if(CONFIG_SPI) - list(APPEND SRCS stm32_spi.c) -endif() - -if(CONFIG_TIMER) - list(APPEND SRCS stm32_timer.c) -endif() - -if(CONFIG_DRIVERS_POWERLED) - list(APPEND SRCS stm32_powerled.c) -endif() - -if(CONFIG_DRIVERS_SMPS) - list(APPEND SRCS stm32_smps.c) -endif() - -target_sources(board PRIVATE ${SRCS}) - -set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/ld.script") diff --git a/boards/arm/stm32/stm32f334-disco/src/Make.defs b/boards/arm/stm32/stm32f334-disco/src/Make.defs deleted file mode 100644 index df8d1b44b3755..0000000000000 --- a/boards/arm/stm32/stm32f334-disco/src/Make.defs +++ /dev/null @@ -1,57 +0,0 @@ -############################################################################ -# boards/arm/stm32/stm32f334-disco/src/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/Make.defs - -CSRCS = stm32_boot.c - -ifeq ($(CONFIG_ARCH_LEDS),y) -CSRCS += stm32_autoleds.c -endif - -ifeq ($(CONFIG_STM32_CAN_CHARDRIVER),y) -CSRCS += stm32_can.c -endif - -ifeq ($(CONFIG_PWM),y) -CSRCS += stm32_pwm.c -endif - -ifeq ($(CONFIG_SPI),y) -CSRCS += stm32_spi.c -endif - -ifeq ($(CONFIG_TIMER),y) -CSRCS += stm32_timer.c -endif - -ifeq ($(CONFIG_DRIVERS_POWERLED),y) -CSRCS += stm32_powerled.c -endif - -ifeq ($(CONFIG_DRIVERS_SMPS),y) -CSRCS += stm32_smps.c -endif - -DEPPATH += --dep-path board -VPATH += :board -CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/stm32f334-disco/src/stm32_adc.c b/boards/arm/stm32/stm32f334-disco/src/stm32_adc.c deleted file mode 100644 index 9d40e86bd6cca..0000000000000 --- a/boards/arm/stm32/stm32f334-disco/src/stm32_adc.c +++ /dev/null @@ -1,241 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f334-disco/src/stm32_adc.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include "stm32.h" - -#if defined(CONFIG_ADC) && (defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2)) - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -/* 1 or 2 ADC devices (DEV1, DEV2) */ - -#if defined(CONFIG_STM32_ADC1) -# define DEV1_PORT 1 -#endif - -#if defined(CONFIG_STM32_ADC2) -# if defined(DEV1_PORT) -# define DEV2_PORT 2 -# else -# define DEV1_PORT 2 -# endif -#endif - -/* The number of ADC channels in the conversion list */ - -/* TODO DMA */ - -#define ADC1_NCHANNELS 3 -#define ADC2_NCHANNELS 3 - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* DEV 1 */ - -#if DEV1_PORT == 1 - -#define DEV1_NCHANNELS ADC1_NCHANNELS - -/* Identifying number of each ADC channel (even if NCHANNELS is less ) */ - -static const uint8_t g_chanlist1[3] = -{ - 1, - 2, - 11 -}; - -/* Configurations of pins used by each ADC channel */ - -static const uint32_t g_pinlist1[3] = -{ - GPIO_ADC1_IN1_0, /* PA0/A0 */ - GPIO_ADC1_IN2_0, /* PA1/A1 */ - GPIO_ADC1_IN11_0, /* PB0/A3 */ -}; - -#elif DEV1_PORT == 2 - -#define DEV1_NCHANNELS ADC2_NCHANNELS - -/* Identifying number of each ADC channel */ - -static const uint8_t g_chanlist1[3] = -{ - 1, - 6, - 7 -}; - -/* Configurations of pins used by each ADC channel */ - -static const uint32_t g_pinlist1[3] = -{ - GPIO_ADC2_IN1_0, /* PA4/A2 */ - GPIO_ADC2_IN7_0, /* PC1/A4 */ - GPIO_ADC2_IN6_0, /* PC0/A5 */ -}; - -#endif /* DEV1_PORT == 1 */ - -#ifdef DEV2_PORT - -/* DEV 2 */ - -#if DEV2_PORT == 2 - -#define DEV2_NCHANNELS ADC2_NCHANNELS - -/* Identifying number of each ADC channel */ - -static const uint8_t g_chanlist2[1] = -{ - 1, - 6, - 7 -}; - -/* Configurations of pins used by each ADC channel */ - -static const uint32_t g_pinlist2[3] = -{ - GPIO_ADC2_IN1_0, /* PA4/A2 */ - GPIO_ADC2_IN7_0, /* PC1/A4 */ - GPIO_ADC2_IN6_0, /* PC0/A5 */ -}; - -#endif /* DEV2_PORT == 2 */ -#endif /* DEV2_PORT */ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_adc_setup - * - * Description: - * Initialize ADC and register the ADC driver. - * - ****************************************************************************/ - -int stm32_adc_setup(void) -{ - static bool initialized = false; - struct adc_dev_s *adc; - int ret; - int i; - - /* Check if we have already initialized */ - - if (!initialized) - { - /* DEV1 */ - - /* Configure the pins as analog inputs for the selected channels */ - - for (i = 0; i < DEV1_NCHANNELS; i++) - { - stm32_configgpio(g_pinlist1[i]); - } - - /* Call stm32_adcinitialize() to get an instance of the ADC interface */ - - adc = stm32_adcinitialize(DEV1_PORT, g_chanlist1, DEV1_NCHANNELS); - if (adc == NULL) - { - aerr("ERROR: Failed to get ADC interface 1\n"); - return -ENODEV; - } - - /* Register the ADC driver at "/dev/adc0" */ - - ret = adc_register("/dev/adc0", adc); - if (ret < 0) - { - aerr("ERROR: adc_register /dev/adc0 failed: %d\n", ret); - return ret; - } - -#ifdef DEV2_PORT - /* DEV2 */ - - /* Configure the pins as analog inputs for the selected channels */ - - for (i = 0; i < DEV2_NCHANNELS; i++) - { - stm32_configgpio(g_pinlist2[i]); - } - - /* Call stm32_adcinitialize() to get an instance of the ADC interface */ - - adc = stm32_adcinitialize(DEV2_PORT, g_chanlist2, DEV2_NCHANNELS); - if (adc == NULL) - { - aerr("ERROR: Failed to get ADC interface 2\n"); - return -ENODEV; - } - - /* Register the ADC driver at "/dev/adc1" */ - - ret = adc_register("/dev/adc1", adc); - if (ret < 0) - { - aerr("ERROR: adc_register /dev/adc1 failed: %d\n", ret); - return ret; - } -#endif - - initialized = true; - } - - return OK; -} - -#endif /* CONFIG_ADC && (CONFIG_STM32_ADC1 || CONFIG_STM32_ADC2) */ diff --git a/boards/arm/stm32/stm32f334-disco/src/stm32_autoleds.c b/boards/arm/stm32/stm32f334-disco/src/stm32_autoleds.c deleted file mode 100644 index 3cc43c8ee0a23..0000000000000 --- a/boards/arm/stm32/stm32f334-disco/src/stm32_autoleds.c +++ /dev/null @@ -1,80 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f334-disco/src/stm32_autoleds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include "stm32.h" -#include "stm32f334-disco.h" - -#ifdef CONFIG_ARCH_LEDS - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_autoled_initialize - ****************************************************************************/ - -void board_autoled_initialize(void) -{ - /* Configure LED1 GPIO for output */ - - stm32_configgpio(GPIO_LED1); -} - -/**************************************************************************** - * Name: board_autoled_on - ****************************************************************************/ - -void board_autoled_on(int led) -{ - if (led == BOARD_LED1) - { - stm32_gpiowrite(GPIO_LED1, true); - } -} - -/**************************************************************************** - * Name: board_autoled_off - ****************************************************************************/ - -void board_autoled_off(int led) -{ - if (led == BOARD_LED1) - { - stm32_gpiowrite(GPIO_LED1, false); - } -} - -#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/stm32f334-disco/src/stm32_boot.c b/boards/arm/stm32/stm32f334-disco/src/stm32_boot.c deleted file mode 100644 index 5aacb0f9f1109..0000000000000 --- a/boards/arm/stm32/stm32f334-disco/src/stm32_boot.c +++ /dev/null @@ -1,194 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f334-disco/src/stm32_boot.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include -#include - -#include "stm32f334-disco.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#undef HAVE_LEDS -#undef HAVE_DAC - -#if !defined(CONFIG_ARCH_LEDS) && defined(CONFIG_USERLED_LOWER) -# define HAVE_LEDS 1 -#endif - -#if defined(CONFIG_DAC) -# define HAVE_DAC1 1 -# define HAVE_DAC2 1 -#endif - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_boardinitialize - * - * Description: - * All STM32 architectures must provide the following entry point. This - * entry point is called early in the initialization -- after all memory - * has been configured and mapped but before any devices have been - * initialized. - * - ****************************************************************************/ - -void stm32_boardinitialize(void) -{ -#ifdef CONFIG_ARCH_LEDS - /* Configure on-board LEDs if LED support has been selected. */ - - board_autoled_initialize(); -#endif -} - -/**************************************************************************** - * Name: board_late_initialize - * - * Description: - * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional - * initialization call will be performed in the boot-up sequence to a - * function called board_late_initialize(). board_late_initialize() will - * be called immediately after up_initialize() is called and just before - * the initial application is started. This additional initialization - * phase may be used, for example, to initialize board-specific device - * drivers. - * - ****************************************************************************/ - -#ifdef CONFIG_BOARD_LATE_INITIALIZE -void board_late_initialize(void) -{ - int ret; - -#if !defined(CONFIG_DRIVERS_POWERLED) && !defined(CONFIG_DRIVERS_SMPS) -#ifdef HAVE_LEDS - /* Register the LED driver */ - - ret = userled_lower_initialize(LED_DRIVER_PATH); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: userled_lower_initialize() failed: %d\n", ret); - return; - } -#endif - -#ifdef CONFIG_ADC - /* Initialize ADC and register the ADC driver. */ - - ret = stm32_adc_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_adc_setup failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_DAC - /* Initialize DAC and register the DAC driver. */ - - ret = stm32_dac_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_dac_setup failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_COMP - /* Initialize COMP and register the COMP driver. */ - - ret = stm32_comp_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_comp_setup failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_OPAMP - /* Initialize OPAMP and register the OPAMP driver. */ - - ret = stm32_opamp_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_opamp_setup failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_STM32_HRTIM - /* Initialize HRTIM and register the HRTIM driver. */ - - ret = stm32_hrtim_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_hrtim_setup failed: %d\n", ret); - } -#endif -#endif - -#ifdef CONFIG_DRIVERS_POWERLED - /* Initialize powerled and register the powerled driver */ - - ret = stm32_powerled_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_powerled_setup failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_DRIVERS_SMPS - /* Initialize smps and register the smps driver */ - - ret = stm32_smps_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_smps_setup failed: %d\n", ret); - } -#endif - - UNUSED(ret); -} -#endif diff --git a/boards/arm/stm32/stm32f334-disco/src/stm32_comp.c b/boards/arm/stm32/stm32f334-disco/src/stm32_comp.c deleted file mode 100644 index d1f45f0ab7ab2..0000000000000 --- a/boards/arm/stm32/stm32f334-disco/src/stm32_comp.c +++ /dev/null @@ -1,122 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f334-disco/src/stm32_comp.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include "stm32.h" - -#if defined(CONFIG_COMP) && (defined(CONFIG_STM32_COMP2) || \ - defined(CONFIG_STM32_COMP4) || \ - defined(CONFIG_STM32_COMP6)) - -#ifdef CONFIG_STM32_COMP2 -# if defined(CONFIG_STM32_COMP4) || defined(CONFIG_STM32_COMP6) -# error "Currently only one COMP device supported" -# endif -#elif CONFIG_STM32_COMP4 -# if defined(CONFIG_STM32_COMP2) || defined(CONFIG_STM32_COMP6) -# error "Currently only one COMP device supported" -# endif -#elif CONFIG_STM32_COMP6 -# if defined(CONFIG_STM32_COMP2) || defined(CONFIG_STM32_COMP4) -# error "Currently only one COMP device supported" -# endif -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_comp_setup - * - * Description: - * Initialize COMP - * - ****************************************************************************/ - -int stm32_comp_setup(void) -{ - static bool initialized = false; - struct comp_dev_s *comp = NULL; - int ret; - - if (!initialized) - { - /* Get the comparator interface */ - -#ifdef CONFIG_STM32_COMP2 - comp = stm32_compinitialize(2); - if (comp == NULL) - { - aerr("ERROR: Failed to get COMP%d interface\n", 2); - return -ENODEV; - } -#endif - -#ifdef CONFIG_STM32_COMP4 - comp = stm32_compinitialize(4); - if (comp == NULL) - { - aerr("ERROR: Failed to get COMP%d interface\n", 4); - return -ENODEV; - } -#endif - -#ifdef CONFIG_STM32_COMP6 - comp = stm32_compinitialize(6); - if (comp == NULL) - { - aerr("ERROR: Failed to get COMP%d interface\n", 6); - return -ENODEV; - } -#endif - - /* Register the comparator character driver at /dev/comp0 */ - - ret = comp_register("/dev/comp0", comp); - if (ret < 0) - { - aerr("ERROR: comp_register failed: %d\n", ret); - return ret; - } - - initialized = true; - } - - return OK; -} - -#endif /* CONFIG_COMP && (CONFIG_STM32_COMP1 || - * CONFIG_STM32_COMP2 - * CONFIG_STM32_COMP6) */ diff --git a/boards/arm/stm32/stm32f334-disco/src/stm32_hrtim.c b/boards/arm/stm32/stm32f334-disco/src/stm32_hrtim.c deleted file mode 100644 index 381aa7549c39f..0000000000000 --- a/boards/arm/stm32/stm32f334-disco/src/stm32_hrtim.c +++ /dev/null @@ -1,86 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f334-disco/src/stm32_hrtim.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include - -#include "stm32_hrtim.h" - -#if defined(CONFIG_STM32_HRTIM) && defined(CONFIG_STM32_HRTIM1) - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_hrtim_setup - * - * Description: - * Initialize HRTIM driver - * - * Returned Value: - * 0 on success, a negated errno value on failure - * - ****************************************************************************/ - -int stm32_hrtim_setup(void) -{ - static bool initialized = false; - struct hrtim_dev_s *hrtim = NULL; - int ret; - - if (!initialized) - { - /* Get the HRTIM interface */ - - hrtim = stm32_hrtiminitialize(); - if (hrtim == NULL) - { - tmrerr("ERROR: Failed to get HRTIM1 interface\n"); - return -ENODEV; - } - - /* Register the HRTIM character driver at /dev/hrtim0 */ - - ret = hrtim_register("/dev/hrtim0", hrtim); - if (ret < 0) - { - tmrerr("ERROR: hrtim_register failed: %d\n", ret); - return ret; - } - - initialized = true; - } - - return OK; -} - -#endif /* CONFIG_STM32_HRTIM && CONFIG_STM32_HRTIM1 */ diff --git a/boards/arm/stm32/stm32f334-disco/src/stm32_opamp.c b/boards/arm/stm32/stm32f334-disco/src/stm32_opamp.c deleted file mode 100644 index 67ba3ad9f6783..0000000000000 --- a/boards/arm/stm32/stm32f334-disco/src/stm32_opamp.c +++ /dev/null @@ -1,86 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f334-disco/src/stm32_opamp.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include "stm32.h" - -#if defined(CONFIG_OPAMP) && defined(CONFIG_STM32_OPAMP2) - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_opamp_setup - * - * Description: - * Initialize OPAMP - * - ****************************************************************************/ - -int stm32_opamp_setup(void) -{ - static bool initialized = false; - struct opamp_dev_s *opamp = NULL; - int ret; - - if (!initialized) - { - /* Get the OPAMP interface */ - -#ifdef CONFIG_STM32_OPAMP2 - opamp = stm32_opampinitialize(2); - if (opamp == NULL) - { - aerr("ERROR: Failed to get OPAMP%d interface\n", 2); - return -ENODEV; - } -#endif - - /* Register the OPAMP character driver at /dev/opamp0 */ - - ret = opamp_register("/dev/opamp0", opamp); - if (ret < 0) - { - aerr("ERROR: opamp_register failed: %d\n", ret); - return ret; - } - - initialized = true; - } - - return OK; -} - -#endif /* CONFIG_OPAMP && CONFIG_STM32_OPAMP2 */ diff --git a/boards/arm/stm32/stm32f334-disco/src/stm32_smps.c b/boards/arm/stm32/stm32f334-disco/src/stm32_smps.c deleted file mode 100644 index 8c42a9c23cba9..0000000000000 --- a/boards/arm/stm32/stm32f334-disco/src/stm32_smps.c +++ /dev/null @@ -1,1143 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f334-disco/src/stm32_smps.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include - -#include - -#include "arm_internal.h" -#include "ram_vectors.h" - -#include "stm32_hrtim.h" -#include "stm32_adc.h" - -#include - -#if defined(CONFIG_EXAMPLES_SMPS) && defined(CONFIG_DRIVERS_SMPS) - -#ifndef CONFIG_LIBDSP -# error CONFIG_LIBDSP is required -#endif - -#ifndef CONFIG_ARCH_HIPRI_INTERRUPT -# error CONFIG_ARCH_HIPRI_INTERRUPT is required -#endif - -#ifndef CONFIG_ARCH_RAMVECTORS -# error CONFIG_ARCH_RAMVECTORS is required -#endif - -#ifndef CONFIG_ARCH_IRQPRIO -# error CONFIG_ARCH_IRQPRIO is required -#endif - -#ifndef CONFIG_ARCH_FPU -# warning Set CONFIG_ARCH_FPU for hardware FPU support -#endif - -#if !defined(CONFIG_STM32_HRTIM1) || !defined(CONFIG_STM32_HRTIM) -# error "SMPS example requires HRTIM1 support" -#endif - -#if !defined(CONFIG_STM32_ADC1) || !defined(CONFIG_ADC) -# error "SMPS example requires ADC1 support" -#endif - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* ADC1 channels used in this example */ - -#define ADC1_NCHANNELS 2 - -/* ADC1 injected channels numeration */ - -#define V_IN_ADC_INJ_CHANNEL 0 -#define V_OUT_ADC_INJ_CHANNEL 1 - -/* Voltage reference for ADC */ - -#define ADC_REF_VOLTAGE ((float)3.3) - -/* ADC resolution */ - -#define ADC_VAL_MAX 4095 - -/* Input voltage conversion ratio - 6.8k/(6.8k + 27k) */ - -#define V_IN_RATIO (float)((float)(6800+27000)/(float)6800) - -/* Output voltage conversion ratio - 3.3k/(3.3k + 13.3k) */ - -#define V_OUT_RATIO (float)((float)(3300+13300)/(float)3300) - -/* Some absolute limits */ - -#define SMPS_ABSOLUTE_OUT_CURRENT_LIMIT_mA 250 -#define SMPS_ABSOLUTE_OUT_VOLTAGE_LIMIT_mV 15000 -#define SMPS_ABSOLUTE_IN_VOLTAGE_LIMIT_mV 15000 - -#if CONFIG_EXAMPLES_SMPS_OUT_CURRENT_LIMIT > SMPS_ABSOLUTE_OUT_CURRENT_LIMIT_mA -# error "Output current limit great than absolute limit!" -#endif -#if CONFIG_EXAMPLES_SMPS_OUT_VOLTAGE_LIMIT > SMPS_ABSOLUTE_OUT_VOLTAGE_LIMIT_mV -# error "Output voltage limit greater than absolute limit!" -#endif -#if CONFIG_EXAMPLES_SMPS_IN_VOLTAGE_LIMIT > SMPS_ABSOLUTE_IN_VOLTAGE_LIMIT_mV -# error "Input voltage limit greater than absolute limit!" -#endif - -/* Maximum output voltage for boost converter in float */ - -#define BOOST_VOLT_MAX ((float)CONFIG_EXAMPLES_SMPS_OUT_VOLTAGE_LIMIT/1000.0) - -/* Current limit table dimension */ - -#define SMPS_CURRENT_LIMIT_TAB_DIM 15 - -/* At this time only PID controller implemented */ - -#define SMPS_CONTROLLER_PID 1 - -/* Converter's finite accuracy */ - -#define SMPS_VOLTAGE_ACCURACY ((float)0.01) - -/* Buck-boost mode threshold */ - -#define SMPS_BUCKBOOST_RANGE ((float)0.5) - -/* PID controller configuration */ - -#define PID_KP ((float)1.0) -#define PID_KI ((float)0.1) -#define PID_KD ((float)0.0) - -/* Converter frequencies: - * - TIMA_PWM_FREQ - buck converter 250kHz - * - TIMB_PWM_FREQ - boost converter 250kHz - */ - -#define TIMA_PWM_FREQ 250000 -#define TIMB_PWM_FREQ 250000 - -/* Deadtime configuration */ - -#define DT_RISING 0x0A0 -#define DT_FALLING 0x0A0 - -/* Helper macros */ - -#define HRTIM_ALL_OUTPUTS_ENABLE(hrtim, state) \ - HRTIM_OUTPUTS_ENABLE(hrtim, HRTIM_OUT_TIMA_CH1|HRTIM_OUT_TIMA_CH2| \ - HRTIM_OUT_TIMB_CH1|HRTIM_OUT_TIMB_CH2, state); - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/* Current converter mode */ - -enum converter_mode_e -{ - CONVERTER_MODE_INIT, /* Initial mode */ - CONVERTER_MODE_BUCK, /* Buck mode operations (V_in > V_out) */ - CONVERTER_MODE_BOOST, /* Boost mode operations (V_in < V_out) */ - CONVERTER_MODE_BUCKBOOST, /* Buck-boost operations (V_in near V_out) */ -}; - -/* SMPS lower drivers structure */ - -struct smps_lower_dev_s -{ - struct hrtim_dev_s *hrtim; /* PWM generation */ - struct stm32_adc_dev_s *adc; /* input and output voltage sense */ - struct comp_dev_s *comp; /* not used in this demo - only as reference */ - struct dac_dev_s *dac; /* not used in this demo - only as reference */ - struct opamp_dev_s *opamp; /* not used in this demo - only as reference */ -}; - -/* Private data for smps */ - -struct smps_priv_s -{ - uint8_t conv_mode; /* Converter mode */ - uint16_t v_in_raw; /* Voltage input RAW value */ - uint16_t v_out_raw; /* Voltage output RAW value */ - float v_in; /* Voltage input real value in V */ - float v_out; /* Voltage output real value in V */ - bool running; /* Running flag */ - pid_controller_f32_t pid; /* PID controller */ - float *c_limit_tab; /* Current limit tab */ -}; - -/**************************************************************************** - * Private Function Protototypes - ****************************************************************************/ - -static int smps_setup(struct smps_dev_s *dev); -static int smps_shutdown(struct smps_dev_s *dev); -static int smps_start(struct smps_dev_s *dev); -static int smps_stop(struct smps_dev_s *dev); -static int smps_params_set(struct smps_dev_s *dev, - struct smps_params_s *param); -static int smps_mode_set(struct smps_dev_s *dev, uint8_t mode); -static int smps_limits_set(struct smps_dev_s *dev, - struct smps_limits_s *limits); -static int smps_state_get(struct smps_dev_s *dev, - struct smps_state_s *state); -static int smps_fault_set(struct smps_dev_s *dev, uint8_t fault); -static int smps_fault_get(struct smps_dev_s *dev, - uint8_t *fault); -static int smps_fault_clean(struct smps_dev_s *dev, - uint8_t fault); -static int smps_ioctl(struct smps_dev_s *dev, int cmd, - unsigned long arg); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -struct smps_lower_dev_s g_smps_lower; -struct smps_priv_s g_smps_priv; -struct smps_s g_smps; - -struct smps_ops_s g_smps_ops = -{ - .setup = smps_setup, - .shutdown = smps_shutdown, - .start = smps_start, - .stop = smps_stop, - .params_set = smps_params_set, - .mode_set = smps_mode_set, - .limits_set = smps_limits_set, - .fault_set = smps_fault_set, - .state_get = smps_state_get, - .fault_get = smps_fault_get, - .fault_clean = smps_fault_clean, - .ioctl = smps_ioctl -}; - -struct smps_dev_s g_smps_dev = -{ - .ops = &g_smps_ops, - .priv = &g_smps, - .lower = NULL -}; - -/* ADC configuration: - * - Input voltage (V_IN) - ADC1 Channel 2 (PA1) - * - Output voltage (V_OUT) - ADC1 Channel 4 (PA3) - * - * ADC channels configured in injected mode. - * - * Transistors configuration in buck mode: - * - T5 - ON - * - T12 - OFF - * - T4 and T11 - buck operation - * Transistors configuration in boost mode: - * - T4 - ON - * - T11 - OFF - * - T5 and T12 - boost operation - * Transistors configuration in buck-boost mode: - * - T4, T11 - buck operation - * - T5 and T12 - boost operation - * - * HRTIM outputs configuration: - * - T4 -> PA8 -> HRTIM_CHA1 - * - T5 -> PA11 -> HRTIM_CHB2 - * - T11 -> PA9 -> HRTIM_CHA2 - * - T12 -> PA10 -> HRTIM_CHB1 - * - */ - -/* ADC channel list */ - -static const uint8_t g_adc1chan[ADC1_NCHANNELS] = -{ - 2, - 4 -}; - -/* Configurations of pins used by ADC channel */ - -static const uint32_t g_adc1pins[ADC1_NCHANNELS] = -{ - GPIO_ADC1_IN2_0, /* PA1 - V_IN */ - GPIO_ADC1_IN4_0, /* PA3 - V_OUT */ -}; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -static int smps_shutdown(struct smps_dev_s *dev) -{ - struct smps_s *smps = (struct smps_s *)dev->priv; - struct smps_priv_s *priv = (struct smps_priv_s *)smps->priv; - - /* Stop smps if running */ - - if (priv->running == true) - { - smps_stop(dev); - } - - /* Reset smps structure */ - - memset(smps, 0, sizeof(struct smps_s)); - - return OK; -} - -/**************************************************************************** - * Name: smps_setup - * - * Description: - * - * Returned Value: - * 0 on success, a negated errno value on failure - * - ****************************************************************************/ - -static int smps_setup(struct smps_dev_s *dev) -{ - struct smps_lower_dev_s *lower = dev->lower; - struct smps_s *smps = (struct smps_s *)dev->priv; - struct hrtim_dev_s *hrtim = NULL; - struct stm32_adc_dev_s *adc = NULL; - struct smps_priv_s *priv; - struct adc_channel_s channels[ADC1_NCHANNELS]; - struct adc_sample_time_s stime; - int ret = OK; - int i = 0; - - /* Initialize smps structure */ - - smps->opmode = SMPS_OPMODE_INIT; - smps->state.state = SMPS_STATE_INIT; - smps->priv = &g_smps_priv; - - /* Check lower half drivers */ - - hrtim = lower->hrtim; - if (hrtim == NULL) - { - pwrerr("ERROR: Failed to get hrtim "); - ret = ERROR; - goto errout; - } - - adc = lower->adc; - if (adc == NULL) - { - pwrerr("ERROR: Failed to get ADC lower level interface"); - ret = ERROR; - goto errout; - } - - /* Update ADC sample time */ - - for (i = 0; i < ADC1_NCHANNELS; i += 1) - { - channels[i].sample_time = ADC_SMPR_61p5; - channels[i].channel = g_adc1chan[i]; - } - - memset(&stime, 0, sizeof(struct adc_sample_time_s)); - - stime.channels_nbr = ADC1_NCHANNELS; - stime.channel = channels; - - STM32_ADC_SAMPLETIME_SET(adc, &stime); - STM32_ADC_SAMPLETIME_WRITE(adc); - - /* TODO: create current limit table */ - - UNUSED(priv); - -errout: - return ret; -} - -static int smps_start(struct smps_dev_s *dev) -{ - struct smps_lower_dev_s *lower = dev->lower; - struct smps_s *smps = (struct smps_s *)dev->priv; - struct smps_priv_s *priv = (struct smps_priv_s *)smps->priv; - struct hrtim_dev_s *hrtim = lower->hrtim; - struct stm32_adc_dev_s *adc = lower->adc; - volatile uint64_t per = 0; - uint64_t fclk = 0; - int ret = OK; - - /* Disable HRTIM outputs */ - - HRTIM_ALL_OUTPUTS_ENABLE(hrtim, false); - - /* Reset SMPS private structure */ - - memset(priv, 0, sizeof(struct smps_priv_s)); - -#ifdef SMPS_CONTROLLER_PID - /* Initialize PID controller */ - - pid_controller_init(&priv->pid, PID_KP, PID_KI, PID_KD); - - /* Set PID controller saturation */ - - pid_saturation_set(&priv->pid, 0.0, BOOST_VOLT_MAX); - - /* Reset PI integral if saturated */ - - pi_ireset_enable(&priv->pid, true); -#endif - - /* Get TIMA period value for given frequency */ - - fclk = HRTIM_FCLK_GET(hrtim, HRTIM_TIMER_TIMA); - per = fclk / TIMA_PWM_FREQ; - if (per > HRTIM_PER_MAX) - { - pwrerr("ERROR: Can not achieve tima pwm " - "freq=%" PRIu32 " if fclk=%" PRIu64 "\n", - (uint32_t)TIMA_PWM_FREQ, fclk); - ret = -EINVAL; - goto errout; - } - - /* Set TIMA period value */ - - HRTIM_PER_SET(hrtim, HRTIM_TIMER_TIMA, (uint16_t)per); - - /* Get TIMB period value for given frequency */ - - fclk = HRTIM_FCLK_GET(hrtim, HRTIM_TIMER_TIMB); - per = fclk / TIMB_PWM_FREQ; - if (per > HRTIM_PER_MAX) - { - pwrerr("ERROR: Can not achieve timb pwm " - "freq=%" PRIu32 " if fclk=%" PRIu64 "\n", - (uint32_t)TIMB_PWM_FREQ, fclk); - ret = -EINVAL; - goto errout; - } - - /* Set TIMB period value */ - - HRTIM_PER_SET(hrtim, HRTIM_TIMER_TIMB, (uint16_t)per); - - /* ADC trigger on TIMA CMP4 */ - - HRTIM_CMP_SET(hrtim, HRTIM_TIMER_TIMA, HRTIM_CMP4, 10000); - - /* Configure TIMER A and TIMER B deadtime mode - * - * NOTE: In deadtime mode we have to configure output 1 only - * (SETx1, RSTx1), output 2 configuration is not significant. - */ - - HRTIM_DEADTIME_UPDATE(hrtim, HRTIM_TIMER_TIMA, HRTIM_DT_EDGE_RISING, - DT_RISING); - HRTIM_DEADTIME_UPDATE(hrtim, HRTIM_TIMER_TIMA, HRTIM_DT_EDGE_FALLING, - DT_FALLING); - HRTIM_DEADTIME_UPDATE(hrtim, HRTIM_TIMER_TIMB, HRTIM_DT_EDGE_RISING, - DT_RISING); - HRTIM_DEADTIME_UPDATE(hrtim, HRTIM_TIMER_TIMB, HRTIM_DT_EDGE_FALLING, - DT_FALLING); - - /* Set T4 and T12 to a low state. - * Deadtime mode force T11 and T5 to a high state. - */ - - HRTIM_OUTPUT_SET_SET(hrtim, HRTIM_OUT_TIMA_CH1, HRTIM_OUT_SET_NONE); - HRTIM_OUTPUT_RST_SET(hrtim, HRTIM_OUT_TIMA_CH1, HRTIM_OUT_RST_PER); - - HRTIM_OUTPUT_SET_SET(hrtim, HRTIM_OUT_TIMB_CH1, HRTIM_OUT_SET_NONE); - HRTIM_OUTPUT_RST_SET(hrtim, HRTIM_OUT_TIMB_CH1, HRTIM_OUT_RST_PER); - - /* Set running flag */ - - priv->running = true; - - HRTIM_ALL_OUTPUTS_ENABLE(hrtim, true); - - /* Enable ADC JEOS interrupts */ - - STM32_ADC_INT_ENABLE(adc, ADC_INT_JEOS); - - /* Enable ADC12 interrupts */ - - up_enable_irq(STM32_IRQ_ADC12); - - /* Start injected conversion */ - - STM32_ADC_INJ_STARTCONV(adc, true); - -errout: - return ret; -} - -static int smps_stop(struct smps_dev_s *dev) -{ - struct smps_lower_dev_s *lower = dev->lower; - struct smps_s *smps = (struct smps_s *)dev->priv; - struct smps_priv_s *priv = (struct smps_priv_s *)smps->priv; - struct hrtim_dev_s *hrtim = lower->hrtim; - struct stm32_adc_dev_s *adc = lower->adc; - - /* Disable HRTIM outputs */ - - HRTIM_ALL_OUTPUTS_ENABLE(hrtim, false); - - /* Stop injected conversion */ - - STM32_ADC_INJ_STARTCONV(adc, false); - - /* Disable ADC JEOS interrupts */ - - STM32_ADC_INT_DISABLE(adc, ADC_INT_JEOS); - - /* Disable ADC12 interrupts */ - - up_disable_irq(STM32_IRQ_ADC12); - - /* Reset running flag */ - - priv->running = false; - - return OK; -} - -static int smps_params_set(struct smps_dev_s *dev, - struct smps_params_s *param) -{ - struct smps_s *smps = (struct smps_s *)dev->priv; - int ret = OK; - - /* Only output voltage */ - - smps->param.v_out = param->v_out; - - /* REVISIT: use current and power parameters ? */ - - if (param->i_out > 0) - { - pwrwarn("WARNING: Output current parameters not used in this demo\n"); - } - - if (param->p_out > 0) - { - pwrwarn("WARNING: Output power parameters not used in this demo\n"); - } - - return ret; -} - -static int smps_mode_set(struct smps_dev_s *dev, uint8_t mode) -{ - struct smps_s *smps = (struct smps_s *)dev->priv; - int ret = OK; - - /* Only constant voltage mode supported */ - - if (mode == SMPS_OPMODE_CV) - { - smps->opmode = mode; - } - else - { - pwrerr("ERROR: Unsupported SMPS mode %d!\n", mode); - ret = ERROR; - goto errout; - } - -errout: - return ret; -} - -static int smps_limits_set(struct smps_dev_s *dev, - struct smps_limits_s *limits) -{ - struct smps_s *smps = (struct smps_s *)dev->priv; - int ret = OK; - - /* Some assertions */ - - if (limits->v_out <= 0) - { - pwrerr("ERROR: Output voltage limit must be set!\n"); - ret = ERROR; - goto errout; - } - - if (limits->v_in <= 0) - { - pwrerr("ERROR: Input voltage limit must be set!\n"); - ret = ERROR; - goto errout; - } - - if (limits->i_out <= 0) - { - pwrerr("ERROR: Output current limit must be set!\n"); - ret = ERROR; - goto errout; - } - - if (limits->v_out * 1000 > CONFIG_EXAMPLES_SMPS_OUT_VOLTAGE_LIMIT) - { - limits->v_out = (float)CONFIG_EXAMPLES_SMPS_OUT_VOLTAGE_LIMIT / 1000.0; - pwrwarn("WARNING: " - "SMPS output voltage limiit > SMPS absolute output voltage " - "limit. Set output voltage limit to %.2f.\n", - limits->v_out); - } - - if (limits->v_in * 1000 > CONFIG_EXAMPLES_SMPS_IN_VOLTAGE_LIMIT) - { - limits->v_in = (float)CONFIG_EXAMPLES_SMPS_IN_VOLTAGE_LIMIT / 1000.0; - pwrwarn("WARNING: " - "SMPS input voltage limiit > SMPS absolute input voltage " - "limit. Set input voltage limit to %.2f.\n", - limits->v_in); - } - - if (limits->i_out * 1000 > CONFIG_EXAMPLES_SMPS_OUT_CURRENT_LIMIT) - { - limits->i_out = (float)CONFIG_EXAMPLES_SMPS_OUT_CURRENT_LIMIT / 1000.0; - pwrwarn("WARNING: " - "SMPS output current limiit > SMPS absolute output current " - "limit. Set output current limit to %.2f.\n", - limits->i_out); - } - - /* Set output voltage limit */ - - smps->limits.v_out = limits->v_out; - - /* Set input voltage limit */ - - smps->limits.v_in = limits->v_in; - - /* Set current limit */ - - smps->limits.i_out = limits->i_out; - - /* Lock limits */ - - smps->limits.lock = true; - -errout: - return ret; -} - -static int smps_state_get(struct smps_dev_s *dev, - struct smps_state_s *state) -{ - struct smps_s *smps = (struct smps_s *)dev->priv; - - /* Copy locally stored feedbacks data to status structure */ - - smps->state.fb.v_in = g_smps_priv.v_in; - smps->state.fb.v_out = g_smps_priv.v_out; - - /* Return state structure to caller */ - - memcpy(state, &smps->state, sizeof(struct smps_state_s)); - - return OK; -} - -static int smps_fault_set(struct smps_dev_s *dev, uint8_t fault) -{ - return OK; -} - -static int smps_fault_get(struct smps_dev_s *dev, uint8_t *fault) -{ - return OK; -} - -static int smps_fault_clean(struct smps_dev_s *dev, uint8_t fault) -{ - return OK; -} - -static int smps_ioctl(struct smps_dev_s *dev, int cmd, unsigned long arg) -{ - return OK; -} - -/**************************************************************************** - * Name: smps_controller - ****************************************************************************/ - -static float smps_controller(struct smps_priv_s *priv, float err) -{ - float out = 0.0; - -#ifdef SMPS_CONTROLLER_PID - out = pid_controller(&priv->pid, err); -#else -# error "At this time only PID controller implemented" -#endif - - return out; -} - -/**************************************************************************** - * Name: smps_duty_set - ****************************************************************************/ - -static void smps_duty_set(struct smps_priv_s *priv, - struct smps_lower_dev_s *lower, - float out) -{ - struct hrtim_dev_s *hrtim = lower->hrtim; - uint8_t mode = priv->conv_mode; - uint16_t cmp = 0; - float duty = 0.0; - uint16_t per = 0; - - switch (mode) - { - case CONVERTER_MODE_INIT: - { - /* Do nothing */ - - break; - } - - case CONVERTER_MODE_BUCK: - { - if (out >= priv->v_in) out = priv->v_in; - if (out < 0.0) out = 0.0; - - duty = out / priv->v_in; - -#warning TODO: current limit in buck mode - - per = HRTIM_PER_GET(hrtim, HRTIM_TIMER_TIMA); - - cmp = (uint16_t)(per * duty); - - if (cmp > per - 30) cmp = per - 30; - - /* Set T4 duty cycle. T11 is complementary to T4 */ - - HRTIM_CMP_SET(hrtim, HRTIM_TIMER_TIMA, HRTIM_CMP1, cmp); - - break; - } - - case CONVERTER_MODE_BOOST: - { - per = HRTIM_PER_GET(hrtim, HRTIM_TIMER_TIMA); - - if (out < priv->v_in) out = priv->v_in; - if (out >= BOOST_VOLT_MAX) out = BOOST_VOLT_MAX; - - duty = 1.0 - priv->v_in / out; - -#warning TODO: current limit in boost mode - - cmp = (uint16_t)(per * duty); - - /* Set T12 duty cycle. T5 is complementary to T12 */ - - HRTIM_CMP_SET(hrtim, HRTIM_TIMER_TIMB, HRTIM_CMP1, cmp); - - break; - } - - case CONVERTER_MODE_BUCKBOOST: - { - /* Buck converter is set to fixed duty cycle (80%). - * Now we need set boost converter - */ - - per = HRTIM_PER_GET(hrtim, HRTIM_TIMER_TIMA); - - if (out < priv->v_in) out = priv->v_in; - if (out >= BOOST_VOLT_MAX) out = BOOST_VOLT_MAX; - - duty = 1.0 - priv->v_in / out; - -#warning TODO: current limit in buck boost mode - - cmp = (uint16_t)(per * duty); - - /* Set T12 duty cycle. T5 is complementary to T12 */ - - HRTIM_CMP_SET(hrtim, HRTIM_TIMER_TIMB, HRTIM_CMP1, cmp); - - break; - } - - default: - { - pwrerr("ERROR: Unknown converter mode %d!\n", mode); - break; - } - } -} - -/**************************************************************************** - * Name: smps_conv_mode_set - * - * Description: - * Change converter mode (buck/boost/buck-boost). - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void smps_conv_mode_set(struct smps_priv_s *priv, - struct smps_lower_dev_s *lower, - uint8_t mode) -{ - struct hrtim_dev_s *hrtim = lower->hrtim; - - /* Disable all outputs */ - - HRTIM_ALL_OUTPUTS_ENABLE(hrtim, false); - - switch (mode) - { - case CONVERTER_MODE_INIT: - { - break; - } - - case CONVERTER_MODE_BUCK: - { - /* Set T12 low (T5 high) on the next PER */ - - HRTIM_OUTPUT_SET_SET(hrtim, HRTIM_OUT_TIMB_CH1, - HRTIM_OUT_SET_NONE); - HRTIM_OUTPUT_RST_SET(hrtim, HRTIM_OUT_TIMB_CH1, - HRTIM_OUT_RST_PER); - - /* Set T4 to a high state on PER and reset on CMP1. - * T11 is complementary to T4. - */ - - HRTIM_OUTPUT_SET_SET(hrtim, HRTIM_OUT_TIMA_CH1, - HRTIM_OUT_SET_PER); - HRTIM_OUTPUT_RST_SET(hrtim, HRTIM_OUT_TIMA_CH1, - HRTIM_OUT_RST_CMP1); - - break; - } - - case CONVERTER_MODE_BOOST: - { - /* Set T4 high (T11 low) on the next PER */ - - HRTIM_OUTPUT_SET_SET(hrtim, HRTIM_OUT_TIMA_CH1, - HRTIM_OUT_SET_PER); - HRTIM_OUTPUT_RST_SET(hrtim, HRTIM_OUT_TIMA_CH1, - HRTIM_OUT_RST_NONE); - - /* Set T12 to a high state on PER and reset on CMP1. - * T5 is complementary to T12. - */ - - HRTIM_OUTPUT_SET_SET(hrtim, HRTIM_OUT_TIMB_CH1, - HRTIM_OUT_SET_PER); - HRTIM_OUTPUT_RST_SET(hrtim, HRTIM_OUT_TIMB_CH1, - HRTIM_OUT_RST_CMP1); - - break; - } - - case CONVERTER_MODE_BUCKBOOST: - { - /* Set T4 to a high state on PER and reset on CMP1. - * T11 is complementary to T4. - */ - - HRTIM_OUTPUT_SET_SET(hrtim, HRTIM_OUT_TIMA_CH1, - HRTIM_OUT_SET_PER); - HRTIM_OUTPUT_RST_SET(hrtim, HRTIM_OUT_TIMA_CH1, - HRTIM_OUT_RST_CMP1); - - /* Set T12 to a high state on PER and reset on CMP1. - * T5 is complementary to T12. - */ - - HRTIM_OUTPUT_SET_SET(hrtim, HRTIM_OUT_TIMB_CH1, - HRTIM_OUT_SET_PER); - HRTIM_OUTPUT_RST_SET(hrtim, HRTIM_OUT_TIMB_CH1, - HRTIM_OUT_RST_CMP1); - - /* Set fixed duty cycle (80%) on buck converter (T4 and T11) */ - - HRTIM_CMP_SET(hrtim, HRTIM_TIMER_TIMA, HRTIM_CMP1, - 0.8 * ((uint16_t)HRTIM_PER_GET(hrtim, - HRTIM_TIMER_TIMA))); - - break; - } - - default: - { - pwrerr("ERROR: Unknown converter mode %d!\n", mode); - break; - } - } - - /* Set mode in private data */ - - priv->conv_mode = mode; - - /* Enable outputs */ - - HRTIM_ALL_OUTPUTS_ENABLE(hrtim, true); -} - -/**************************************************************************** - * Name: adc12_handler - ****************************************************************************/ - -static void adc12_handler(void) -{ - struct smps_dev_s *dev = &g_smps_dev; - struct smps_s *smps = (struct smps_s *)dev->priv; - struct smps_priv_s *priv = (struct smps_priv_s *)smps->priv; - struct smps_lower_dev_s *lower = dev->lower; - struct stm32_adc_dev_s *adc = lower->adc; - uint32_t pending; - float ref = ADC_REF_VOLTAGE; - float bit = ADC_VAL_MAX; - float err; - float out; - uint8_t mode; - - pending = STM32_ADC_INT_GET(adc); - - if (pending & ADC_INT_JEOC && priv->running == true) - { - /* Get raw ADC values */ - - priv->v_out_raw = STM32_ADC_INJDATA_GET(adc, V_OUT_ADC_INJ_CHANNEL); - priv->v_in_raw = STM32_ADC_INJDATA_GET(adc, V_IN_ADC_INJ_CHANNEL); - - /* Convert raw values to real values */ - - priv->v_out = (priv->v_out_raw * ref / bit) * V_OUT_RATIO; - priv->v_in = (priv->v_in_raw * ref / bit) * V_IN_RATIO; - - /* According to measured voltages we set converter - * in appropriate mode - */ - - if (smps->param.v_out > (priv->v_in + SMPS_BUCKBOOST_RANGE)) - { - /* Desired output voltage greater than input voltage - set - * boost converter - */ - - mode = CONVERTER_MODE_BOOST; - } - - else if (smps->param.v_out < (priv->v_in - SMPS_BUCKBOOST_RANGE)) - { - /* Desired output voltage lower than input voltage - set - * buck converter - */ - - mode = CONVERTER_MODE_BUCK; - } - - else - { - /* Desired output voltage close to input voltage - set - * buck-boost converter - */ - - mode = CONVERTER_MODE_BUCKBOOST; - } - - /* Configure converter to the new mode if needed */ - - if (priv->conv_mode != mode) - { - smps_conv_mode_set(priv, lower, mode); - } - - /* Get regulator error */ - - err = smps->param.v_out - priv->v_out; - - if (err >= SMPS_VOLTAGE_ACCURACY || err <= (-SMPS_VOLTAGE_ACCURACY)) - { - /* PID controller */ - - out = smps_controller(priv, err); - - /* Update duty cycle */ - - smps_duty_set(priv, lower, out); - } - } - - /* Clear pending */ - - STM32_ADC_INT_ACK(adc, pending); -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_smps_setup - * - * Description: - * Initialize SMPS driver. - * - * Returned Value: - * 0 on success, a negated errno value on failure - * - ****************************************************************************/ - -int stm32_smps_setup(void) -{ - struct smps_lower_dev_s *lower = &g_smps_lower; - struct smps_dev_s *smps = &g_smps_dev; - struct hrtim_dev_s *hrtim = NULL; - struct adc_dev_s *adc = NULL; - static bool initialized = false; - int ret = OK; - int i; - - /* Initialize only once */ - - if (!initialized) - { - /* Get the HRTIM interface */ - - hrtim = stm32_hrtiminitialize(); - if (hrtim == NULL) - { - pwrerr("ERROR: Failed to get HRTIM1 interface\n"); - return -ENODEV; - } - - /* Configure the pins as analog inputs for the selected channels */ - - for (i = 0; i < ADC1_NCHANNELS; i++) - { - stm32_configgpio(g_adc1pins[i]); - } - - /* Get the ADC interface */ - - adc = stm32_adcinitialize(1, g_adc1chan, ADC1_NCHANNELS); - if (adc == NULL) - { - pwrerr("ERROR: Failed to get ADC %d interface\n", 1); - return -ENODEV; - } - - /* Initialize SMPS lower driver interfaces */ - - lower->hrtim = hrtim; - lower->adc = adc->ad_priv; - lower->comp = NULL; - lower->dac = NULL; - lower->opamp = NULL; - - /* Attach ADC12 ram vector */ - - ret = arm_ramvec_attach(STM32_IRQ_ADC12, adc12_handler); - if (ret < 0) - { - pwrerr("ERROR: arm_ramvec_attach failed: %d\n", ret); - ret = EXIT_FAILURE; - goto errout; - } - - /* Set the priority of the ADC12 interrupt vector */ - - ret = up_prioritize_irq(STM32_IRQ_ADC12, NVIC_SYSH_HIGH_PRIORITY); - if (ret < 0) - { - pwrerr("ERROR: up_prioritize_irq failed: %d\n", ret); - ret = EXIT_FAILURE; - goto errout; - } - - /* Setup ADC hardware */ - - adc->ad_ops->ao_setup(adc); - - /* We do not need register character drivers for SMPS lower - * peripherals. All control should be done via SMPS character - * driver. - */ - - ret = smps_register(CONFIG_EXAMPLES_SMPS_DEVPATH, smps, (void *)lower); - if (ret < 0) - { - pwrerr("ERROR: smps_register failed: %d\n", ret); - return ret; - } - - initialized = true; - } - -errout: - return ret; -} - -#endif /* CONFIG_EXAMPLE_SMPS && CONFIG_DRIVERS_SMPS*/ diff --git a/boards/arm/stm32/stm32f3discovery/CMakeLists.txt b/boards/arm/stm32/stm32f3discovery/CMakeLists.txt deleted file mode 100644 index b5910c678d95d..0000000000000 --- a/boards/arm/stm32/stm32f3discovery/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/stm32f3discovery/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32/stm32f3discovery/configs/nsh/defconfig b/boards/arm/stm32/stm32f3discovery/configs/nsh/defconfig deleted file mode 100644 index 1973cf7321ab8..0000000000000 --- a/boards/arm/stm32/stm32f3discovery/configs/nsh/defconfig +++ /dev/null @@ -1,52 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_NSH_DISABLE_IFCONFIG is not set -# CONFIG_NSH_DISABLE_PS is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f3discovery" -CONFIG_ARCH_BOARD_STM32F3_DISCOVERY=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F303VC=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=6522 -CONFIG_BUILTIN=y -CONFIG_CDCACM=y -CONFIG_CDCACM_RXBUFSIZE=256 -CONFIG_CDCACM_TXBUFSIZE=256 -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_HOST_WINDOWS=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_MM_REGIONS=2 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=40960 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=6 -CONFIG_START_MONTH=12 -CONFIG_START_YEAR=2011 -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_PWR=y -CONFIG_STM32_USART2=y -CONFIG_STM32_USB=y -CONFIG_SYSTEM_CDCACM=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART2_RXBUFSIZE=128 -CONFIG_USART2_SERIAL_CONSOLE=y -CONFIG_USART2_TXBUFSIZE=128 diff --git a/boards/arm/stm32/stm32f3discovery/configs/usbnsh/defconfig b/boards/arm/stm32/stm32f3discovery/configs/usbnsh/defconfig deleted file mode 100644 index 5d388639fb48f..0000000000000 --- a/boards/arm/stm32/stm32f3discovery/configs/usbnsh/defconfig +++ /dev/null @@ -1,54 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_DEV_CONSOLE is not set -# CONFIG_NSH_DISABLE_IFCONFIG is not set -# CONFIG_NSH_DISABLE_PS is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f3discovery" -CONFIG_ARCH_BOARD_STM32F3_DISCOVERY=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F303VC=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARDCTL_USBDEVCTRL=y -CONFIG_BOARD_LOOPSPERMSEC=6522 -CONFIG_BUILTIN=y -CONFIG_CDCACM=y -CONFIG_CDCACM_CONSOLE=y -CONFIG_CDCACM_RXBUFSIZE=256 -CONFIG_CDCACM_TXBUFSIZE=256 -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_HOST_WINDOWS=y -CONFIG_IDLETHREAD_STACKSIZE=2048 -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_MM_REGIONS=2 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=40960 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=27 -CONFIG_START_YEAR=2013 -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_PWR=y -CONFIG_STM32_SPI1=y -CONFIG_STM32_USART2=y -CONFIG_STM32_USB=y -CONFIG_SYSLOG_CHAR=y -CONFIG_SYSLOG_DEVPATH="/dev/ttyS0" -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 diff --git a/boards/arm/stm32/stm32f3discovery/include/board.h b/boards/arm/stm32/stm32f3discovery/include/board.h deleted file mode 100644 index 2761c0cfb059d..0000000000000 --- a/boards/arm/stm32/stm32f3discovery/include/board.h +++ /dev/null @@ -1,275 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f3discovery/include/board.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __BOARDS_ARM_STM32_STM32F3DISCOVERY_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32_STM32F3DISCOVERY_INCLUDE_BOARD_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#ifndef __ASSEMBLY__ -# include -#endif - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Clocking *****************************************************************/ - -/* HSI - Internal 8 MHz RC Oscillator - * LSI - 32 KHz RC - * HSE - On-board crystal frequency is 8MHz - * LSE - 32.768 kHz - */ - -#define STM32_BOARD_XTAL 8000000ul /* X1 on board */ - -#define STM32_HSI_FREQUENCY 8000000ul -#define STM32_LSI_FREQUENCY 40000 /* Between 30kHz and 60kHz */ -#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL -#define STM32_LSE_FREQUENCY 32768 /* X2 on board */ - -/* PLL source is HSE/1, - * PLL multiplier is 9: - * PLL frequency is 8MHz (XTAL) x 9 = 72MHz - */ - -#define STM32_CFGR_PLLSRC RCC_CFGR_PLLSRC -#define STM32_CFGR_PLLXTPRE 0 -#define STM32_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx9 -#define STM32_PLL_FREQUENCY (9*STM32_BOARD_XTAL) - -/* Use the PLL and set the SYSCLK source to be the PLL */ - -#define STM32_SYSCLK_SW RCC_CFGR_SW_PLL -#define STM32_SYSCLK_SWS RCC_CFGR_SWS_PLL -#define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY - -/* AHB clock (HCLK) is SYSCLK (72MHz) */ - -#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK -#define STM32_HCLK_FREQUENCY STM32_PLL_FREQUENCY - -/* APB2 clock (PCLK2) is HCLK (72MHz) */ - -#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK -#define STM32_PCLK2_FREQUENCY STM32_HCLK_FREQUENCY -#define STM32_APB2_CLKIN (STM32_PCLK2_FREQUENCY) /* Timers 1 and 8, 15-17 */ - -/* APB2 timers 1 and 8, 15-17 will receive PCLK2. */ - -/* Timers driven from APB2 will be PCLK2 */ - -#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB1_TIM15_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB1_TIM16_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB1_TIM17_CLKIN (STM32_PCLK2_FREQUENCY) - -/* APB1 clock (PCLK1) is HCLK/2 (36MHz) */ - -#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd2 -#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/2) - -/* APB1 timers 2-7 will be twice PCLK1 */ - -#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) - -/* USB divider -- Divide PLL clock by 1.5 */ - -#define STM32_CFGR_USBPRE 0 - -/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx - * otherwise frequency is 2xAPBx. - * Note: TIM1,8 are on APB2, others on APB1 - */ - -#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM2_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM3_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM4_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM5_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM6_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM7_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY - -/* LED definitions **********************************************************/ - -/* The STM32F3Discovery board has ten LEDs. Two of these are controlled by - * logic on the board and are not available for software control: - * - * LD1 PWR: red LED indicates that the board is powered. - * LD2 COM: LD2 default status is red. LD2 turns to green to indicate that - * communications are in progress between the PC and the - * ST-LINK/V2. - * - * And eight can be controlled by software: - * - * User LEDs connected to the I/O of the STM32F303VCT6. - * User LD3: red LED is a user LED connected to the PE9 I/O. - * User LD4: blue LED is a user LED connected to the PE8 I/O. - * User LD5: orange LED is a user LED connected to the PE10 I/O. - * User LD6: green LED is a user LED connected to the PE15 I/O. - * User LD7: green LED is a user LED connected to the PE11 I/O. - * User LD8: orange LED is a user LED connected to the PE14 I/O. - * User LD9: blue LED is a user LED connected to the PE12 I/O. - * User LD10: red LED is a user LED connected to the PE13 I/O. - * - * If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs in - * any way. The following definitions are used to access individual LEDs. - */ - -/* LED index values for use with board_userled() */ - -#define BOARD_LED1 0 /* User LD3 */ -#define BOARD_LED2 1 /* User LD4 */ -#define BOARD_LED3 2 /* User LD5 */ -#define BOARD_LED4 3 /* User LD6 */ -#define BOARD_LED5 4 /* User LD7 */ -#define BOARD_LED6 5 /* User LD8 */ -#define BOARD_LED7 6 /* User LD9 */ -#define BOARD_LED8 7 /* User LD10 */ -#define BOARD_NLEDS 8 - -/* LED bits for use with board_userled_all() */ - -#define BOARD_LED1_BIT (1 << BOARD_LED1) -#define BOARD_LED2_BIT (1 << BOARD_LED2) -#define BOARD_LED3_BIT (1 << BOARD_LED3) -#define BOARD_LED4_BIT (1 << BOARD_LED4) -#define BOARD_LED5_BIT (1 << BOARD_LED5) -#define BOARD_LED6_BIT (1 << BOARD_LED6) -#define BOARD_LED7_BIT (1 << BOARD_LED7) -#define BOARD_LED8_BIT (1 << BOARD_LED8) - -/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the 8 LEDs on - * board the stm32f3discovery. - * The following definitions describe how NuttX controls the LEDs: - * - * SYMBOL Meaning LED state - * Initially all LEDs are OFF - * ------------------- ----------------------- ------------- ------------ - * LED_STARTED NuttX has been started LD3 ON - * LED_HEAPALLOCATE Heap has been allocated LD4 ON - * LED_IRQSENABLED Interrupts enabled LD4 ON - * LED_STACKCREATED Idle stack created LD6 ON - * LED_INIRQ In an interrupt LD7 should glow - * LED_SIGNAL In a signal handler LD8 might glow - * LED_ASSERTION An assertion failed LD9 ON while handling - * the assertion - * LED_PANIC The system has crashed LD10 Blinking at 2Hz - * LED_IDLE STM32 is in sleep mode (Optional, not used) - */ - -#define LED_STARTED 0 -#define LED_HEAPALLOCATE 1 -#define LED_IRQSENABLED 2 -#define LED_STACKCREATED 3 -#define LED_INIRQ 4 -#define LED_SIGNAL 5 -#define LED_ASSERTION 6 -#define LED_PANIC 7 - -/* Button definitions *******************************************************/ - -/* The STM32F3Discovery supports two buttons; only one button is controllable - * by software: - * - * B1 USER: - * user and wake-up button connected to the I/O PA0 of the - * STM32F303VCT6. - * B2 RESET: - * pushbutton connected to NRST is used to RESET the STM32F303VCT6. - */ - -#define BUTTON_USER 0 - -#define NUM_BUTTONS 1 - -#define BUTTON_USER_BIT (1 << BUTTON_USER) - -/* Alternate function pin selections ****************************************/ - -/* USART - * - * USART1: Hardwired to embedded STLinkV2 hardware debugger - * RX (PC5) - * TX (PC4) - * - * USART2: - * Connect to an external UART<->RS232 transceiver for use as console. - * RX (PA3) - * TX (PA2) - */ - -#define GPIO_USART2_RX (GPIO_USART2_RX_2|GPIO_SPEED_50MHz) -#define GPIO_USART2_TX (GPIO_USART2_TX_2|GPIO_SPEED_50MHz) - -/* SPI - * - * SPI1: Hardwired to ST L3GD20 MEMS device - * MISO (PA6) - * MSOI (PA7) - * SCK (PA5) - */ - -#define GPIO_SPI1_MISO GPIO_SPI1_MISO_1 -#define GPIO_SPI1_MOSI GPIO_SPI1_MOSI_1 -#define GPIO_SPI1_SCK GPIO_SPI1_SCK_1 - -/* I2C - * - * I2C1: Accessible via expansion headers - * SCL (PA15) - * SDA (PA14) - * SMBA (PB5) - * - * I2C2: Accessible via expansion headers - * SCL (PA9) - * SDA (PA10) - * SMBA (PB12) - */ - -#ifdef CONFIG_STM32_I2C1 -#define GPIO_I2C1_SCL (GPIO_I2C1_SCL_1|GPIO_SPEED_50MHz) -#define GPIO_I2C1_SDA (GPIO_I2C1_SDA_1|GPIO_SPEED_50MHz) -#endif - -#ifdef CONFIG_STM32_I2C2 -#define GPIO_I2C2_SCL (GPIO_I2C2_SCL_1|GPIO_SPEED_50MHz) -#define GPIO_I2C2_SDA (GPIO_I2C2_SDA_1|GPIO_SPEED_50MHz) -#endif - -/* USB */ - -#define GPIO_USB_DM (GPIO_USB_DM_0|GPIO_SPEED_50MHz) -#define GPIO_USB_DP (GPIO_USB_DP_0|GPIO_SPEED_50MHz) - -#endif /* __BOARDS_ARM_STM32_STM32F3DISCOVERY_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32/stm32f3discovery/scripts/Make.defs b/boards/arm/stm32/stm32f3discovery/scripts/Make.defs deleted file mode 100644 index f4a90c1997c83..0000000000000 --- a/boards/arm/stm32/stm32f3discovery/scripts/Make.defs +++ /dev/null @@ -1,41 +0,0 @@ -############################################################################ -# boards/arm/stm32/stm32f3discovery/scripts/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/.config -include $(TOPDIR)/tools/Config.mk -include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs - -LDSCRIPT = ld.script -ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) - -ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 - -CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) -CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) -CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -AFLAGS := $(CFLAGS) -D__ASSEMBLY__ - -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections -LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32/stm32f3discovery/scripts/ld.script b/boards/arm/stm32/stm32f3discovery/scripts/ld.script deleted file mode 100644 index eef4269081028..0000000000000 --- a/boards/arm/stm32/stm32f3discovery/scripts/ld.script +++ /dev/null @@ -1,121 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f3discovery/scripts/ld.script - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* The STM32F303VCT has 256Kb of FLASH beginning at address 0x0800:0000 and - * 40Kb of SRAM. - * - * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 - * where the code expects to begin execution by jumping to the entry point in - * the 0x0800:0000 address range. - */ - -MEMORY -{ - flash (rx) : ORIGIN = 0x08000000, LENGTH = 256K - sram (rwx) : ORIGIN = 0x20000000, LENGTH = 40K -} - -OUTPUT_ARCH(arm) -EXTERN(_vectors) -ENTRY(_stext) -SECTIONS -{ - .text : { - _stext = ABSOLUTE(.); - *(.vectors) - *(.text .text.*) - *(.fixup) - *(.gnu.warning) - *(.rodata .rodata.*) - *(.gnu.linkonce.t.*) - *(.glue_7) - *(.glue_7t) - *(.got) - *(.gcc_except_table) - *(.gnu.linkonce.r.*) - _etext = ABSOLUTE(.); - } > flash - - .init_section : ALIGN(4) { - _sinit = ABSOLUTE(.); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) - KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) - _einit = ABSOLUTE(.); - } > flash - - .ARM.extab : ALIGN(4) { - *(.ARM.extab*) - } > flash - - .ARM.exidx : ALIGN(4) { - __exidx_start = ABSOLUTE(.); - *(.ARM.exidx*) - __exidx_end = ABSOLUTE(.); - } > flash - - .tdata : { - _stdata = ABSOLUTE(.); - *(.tdata .tdata.* .gnu.linkonce.td.*); - _etdata = ABSOLUTE(.); - } > flash - - .tbss : { - _stbss = ABSOLUTE(.); - *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); - _etbss = ABSOLUTE(.); - } > flash - - _eronly = ABSOLUTE(.); - - .data : ALIGN(4) { - _sdata = ABSOLUTE(.); - *(.data .data.*) - *(.gnu.linkonce.d.*) - CONSTRUCTORS - . = ALIGN(4); - _edata = ABSOLUTE(.); - } > sram AT > flash - - .bss : ALIGN(4) { - _sbss = ABSOLUTE(.); - *(.bss .bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - . = ALIGN(4); - _ebss = ABSOLUTE(.); - } > sram - - /* Stabs debugging sections. */ - - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_info 0 : { *(.debug_info) } - .debug_line 0 : { *(.debug_line) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_aranges 0 : { *(.debug_aranges) } -} diff --git a/boards/arm/stm32/stm32f3discovery/src/CMakeLists.txt b/boards/arm/stm32/stm32f3discovery/src/CMakeLists.txt deleted file mode 100644 index a5f1196b8266a..0000000000000 --- a/boards/arm/stm32/stm32f3discovery/src/CMakeLists.txt +++ /dev/null @@ -1,45 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/stm32f3discovery/src/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -set(SRCS stm32_boot.c stm32_bringup.c stm32_spi.c) - -if(CONFIG_ARCH_LEDS) - list(APPEND SRCS stm32_autoleds.c) -else() - list(APPEND SRCS stm32_userleds.c) -endif() - -if(CONFIG_ARCH_BUTTONS) - list(APPEND SRCS stm32_buttons.c) -endif() - -if(CONFIG_STM32_USB) - list(APPEND SRCS stm32_usb.c) -endif() - -if(CONFIG_PWM) - list(APPEND SRCS stm32_pwm.c) -endif() - -target_sources(board PRIVATE ${SRCS}) - -set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/ld.script") diff --git a/boards/arm/stm32/stm32f3discovery/src/Make.defs b/boards/arm/stm32/stm32f3discovery/src/Make.defs deleted file mode 100644 index 5ab0f6b49b4dd..0000000000000 --- a/boards/arm/stm32/stm32f3discovery/src/Make.defs +++ /dev/null @@ -1,47 +0,0 @@ -############################################################################ -# boards/arm/stm32/stm32f3discovery/src/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/Make.defs - -CSRCS = stm32_boot.c stm32_bringup.c stm32_spi.c - -ifeq ($(CONFIG_ARCH_LEDS),y) -CSRCS += stm32_autoleds.c -else -CSRCS += stm32_userleds.c -endif - -ifeq ($(CONFIG_ARCH_BUTTONS),y) -CSRCS += stm32_buttons.c -endif - -ifeq ($(CONFIG_STM32_USB),y) -CSRCS += stm32_usb.c -endif - -ifeq ($(CONFIG_PWM),y) -CSRCS += stm32_pwm.c -endif - -DEPPATH += --dep-path board -VPATH += :board -CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/stm32f3discovery/src/stm32_autoleds.c b/boards/arm/stm32/stm32f3discovery/src/stm32_autoleds.c deleted file mode 100644 index fd2d12653cbcc..0000000000000 --- a/boards/arm/stm32/stm32f3discovery/src/stm32_autoleds.c +++ /dev/null @@ -1,108 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f3discovery/src/stm32_autoleds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include "chip.h" -#include "stm32.h" -#include "stm32f3discovery.h" - -#ifdef CONFIG_ARCH_LEDS - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* This array maps an LED number to GPIO pin configuration */ - -static const uint32_t g_ledcfg[BOARD_NLEDS] = -{ - GPIO_LED1, GPIO_LED2, GPIO_LED3, GPIO_LED4, - GPIO_LED5, GPIO_LED6, GPIO_LED7, GPIO_LED8 -}; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_autoled_onoff - ****************************************************************************/ - -void board_autoled_onoff(int led, bool state) -{ - if ((unsigned)led < BOARD_NLEDS) - { - stm32_gpiowrite(g_ledcfg[led], state); - } -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_autoled_initialize - ****************************************************************************/ - -void board_autoled_initialize(void) -{ - int i; - - /* Configure LED1-8 GPIOs for output */ - - for (i = 0; i < BOARD_NLEDS; i++) - { - stm32_configgpio(g_ledcfg[i]); - } -} - -/**************************************************************************** - * Name: board_autoled_on - ****************************************************************************/ - -void board_autoled_on(int led) -{ - board_autoled_onoff(led, true); -} - -/**************************************************************************** - * Name: board_autoled_off - ****************************************************************************/ - -void board_autoled_off(int led) -{ - board_autoled_onoff(led, false); -} - -#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/stm32f3discovery/src/stm32_boot.c b/boards/arm/stm32/stm32f3discovery/src/stm32_boot.c deleted file mode 100644 index fe33571227438..0000000000000 --- a/boards/arm/stm32/stm32f3discovery/src/stm32_boot.c +++ /dev/null @@ -1,105 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f3discovery/src/stm32_boot.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include -#include - -#include "arm_internal.h" -#include "stm32f3discovery.h" - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_boardinitialize - * - * Description: - * All STM32 architectures must provide the following entry point. - * This entry point is called early in the initialization -- after all - * memory has been configured and mapped but before any devices have been - * initialized. - * - ****************************************************************************/ - -void stm32_boardinitialize(void) -{ - /* Configure SPI chip selects if 1) SPI is not disabled, and 2) the weak - * function stm32_spidev_initialize() has been brought into the link. - */ - -#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || defined(CONFIG_STM32_SPI3) - if (stm32_spidev_initialize) - { - stm32_spidev_initialize(); - } -#endif - - /* Initialize USB if the 1) USB device controller is in the configuration - * and 2) disabled, and 3) the weak function stm32_usbinitialize() has - * been brought into the build. Presumably either CONFIG_USBDEV is also - * selected. - */ - -#ifdef CONFIG_STM32_USB - if (stm32_usbinitialize) - { - stm32_usbinitialize(); - } -#endif - - /* Configure on-board LEDs if LED support has been selected. */ - -#ifdef CONFIG_ARCH_LEDS - board_autoled_initialize(); -#endif -} - -/**************************************************************************** - * Name: board_late_initialize - * - * Description: - * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional - * initialization call will be performed in the boot-up sequence to a - * function called board_late_initialize(). board_late_initialize() will be - * called immediately after up_initialize() is called and just before the - * initial application is started. This additional initialization phase - * may be used, for example, to initialize board-specific device drivers. - * - ****************************************************************************/ - -#ifdef CONFIG_BOARD_LATE_INITIALIZE -void board_late_initialize(void) -{ - /* Perform board-specific initialization */ - - stm32_bringup(); -} -#endif diff --git a/boards/arm/stm32/stm32f3discovery/src/stm32_bringup.c b/boards/arm/stm32/stm32f3discovery/src/stm32_bringup.c deleted file mode 100644 index b0fc88f9be70b..0000000000000 --- a/boards/arm/stm32/stm32f3discovery/src/stm32_bringup.c +++ /dev/null @@ -1,141 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f3discovery/src/stm32_bringup.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include - -#include - -#ifdef CONFIG_USBMONITOR -# include -#endif - -#include "stm32.h" -#include "stm32f3discovery.h" - -#ifdef CONFIG_SENSORS_QENCODER -#include "board_qencoder.h" -#endif - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -#define HAVE_USBDEV 1 -#define HAVE_USBMONITOR 1 - -/* Can't support USB device features if the STM32 USB peripheral is not - * enabled. - */ - -#ifndef CONFIG_STM32_USB -# undef HAVE_USBDEV -#endif - -/* Can't support USB device is USB device is not enabled */ - -#ifndef CONFIG_USBDEV -# undef HAVE_USBDEV -#endif - -/* Check if we should enable the USB monitor before starting NSH */ - -#ifndef CONFIG_USBMONITOR -# undef HAVE_USBMONITOR -#endif - -#ifndef HAVE_USBDEV -# undef CONFIG_USBDEV_TRACE -#endif - -#ifndef HAVE_USBHOST -# undef CONFIG_USBHOST_TRACE -#endif - -#if !defined(CONFIG_USBDEV_TRACE) && !defined(CONFIG_USBHOST_TRACE) -# undef HAVE_USBMONITOR -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_bringup - * - * Description: - * Perform architecture-specific initialization - * - * CONFIG_BOARD_LATE_INITIALIZE=y : - * Called from board_late_initialize(). - * - ****************************************************************************/ - -int stm32_bringup(void) -{ - int ret = OK; - -#ifdef HAVE_USBMONITOR - /* Start the USB Monitor */ - - ret = usbmonitor_start(); - if (ret != OK) - { - syslog(LOG_ERR, "ERROR: Failed to start USB monitor: %d\n", ret); - } -#endif - -#ifdef CONFIG_PWM - /* Initialize PWM and register the PWM device. */ - - ret = stm32_pwm_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_pwm_setup() failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_SENSORS_QENCODER - /* Initialize and register the qencoder driver */ - - ret = board_qencoder_initialize(0, CONFIG_STM32F3DISCO_QETIMER); - if (ret != OK) - { - syslog(LOG_ERR, - "ERROR: Failed to register the qencoder: %d\n", - ret); - return ret; - } -#endif - - return ret; -} diff --git a/boards/arm/stm32/stm32f3discovery/src/stm32_buttons.c b/boards/arm/stm32/stm32f3discovery/src/stm32_buttons.c deleted file mode 100644 index ba6a750784797..0000000000000 --- a/boards/arm/stm32/stm32f3discovery/src/stm32_buttons.c +++ /dev/null @@ -1,150 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f3discovery/src/stm32_buttons.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include -#include - -#include "stm32f3discovery.h" - -#ifdef CONFIG_ARCH_BUTTONS - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* Pin configuration for each STM32F3Discovery button. This array is indexed - * by the BUTTON_* definitions in board.h - */ - -static const uint32_t g_buttons[NUM_BUTTONS] = -{ - GPIO_BTN_USER -}; - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_button_initialize - * - * Description: - * board_button_initialize() must be called to initialize button resources. - * After that, board_buttons() may be called to collect the current state - * of all buttons or board_button_irq() may be called to register button - * interrupt handlers. - * - ****************************************************************************/ - -uint32_t board_button_initialize(void) -{ - int i; - - /* Configure the GPIO pins as inputs. NOTE that EXTI interrupts are - * configured for all pins. - */ - - for (i = 0; i < NUM_BUTTONS; i++) - { - stm32_configgpio(g_buttons[i]); - } - - return NUM_BUTTONS; -} - -/**************************************************************************** - * Name: board_buttons - ****************************************************************************/ - -uint32_t board_buttons(void) -{ - uint32_t ret = 0; - int i; - - /* Check that state of each key */ - - for (i = 0; i < NUM_BUTTONS; i++) - { - /* A LOW value means that the key is pressed. */ - - bool released = stm32_gpioread(g_buttons[i]); - - /* Accumulate the set of depressed (not released) keys */ - - if (!released) - { - ret |= (1 << i); - } - } - - return ret; -} - -/**************************************************************************** - * Button support. - * - * Description: - * board_button_initialize() must be called to initialize button resources. - * After that, board_buttons() may be called to collect the current state - * of all buttons or board_button_irq() may be called to register button - * interrupt handlers. - * - * After board_button_initialize() has been called, board_buttons() may be - * called to collect the state of all buttons. board_buttons() returns an - * 32-bit bit set with each bit associated with a button. See the - * BUTTON_*_BIT definitions in board.h for the meaning of each bit. - * - * board_button_irq() may be called to register an interrupt handler that - * will be called when a button is depressed or released. The ID value is a - * button enumeration value that uniquely identifies a button resource. See - * the BUTTON_* definitions in board.h for the meaning of enumeration - * value. - * - ****************************************************************************/ - -#ifdef CONFIG_ARCH_IRQBUTTONS -int board_button_irq(int id, xcpt_t irqhandler, void *arg) -{ - int ret = -EINVAL; - - /* The following should be atomic */ - - if (id >= MIN_IRQBUTTON && id <= MAX_IRQBUTTON) - { - ret = stm32_gpiosetevent(g_buttons[id], true, true, true, - irqhandler, arg); - } - - return ret; -} -#endif -#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/stm32/stm32f3discovery/src/stm32_pwm.c b/boards/arm/stm32/stm32f3discovery/src/stm32_pwm.c deleted file mode 100644 index d929dcfd8ce89..0000000000000 --- a/boards/arm/stm32/stm32f3discovery/src/stm32_pwm.c +++ /dev/null @@ -1,127 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f3discovery/src/stm32_pwm.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include - -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32_pwm.h" -#include "stm32f3discovery.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -/* PWM - * - * The stm32f3discovery has no real on-board PWM devices, but the board can - * be configured to output a pulse train using TIM4 CH2. This pin is used - * by FSMC is connected to CN5 just for this purpose: - * - * PD13 FSMC_A18 / MC_TIM4_CH2OUT pin 33 (EnB) - * - * FSMC must be disabled in this case! - */ - -#define HAVE_PWM 1 - -#ifndef CONFIG_PWM -# undef HAVE_PWM -#endif - -#ifndef CONFIG_STM32_TIM4 -# undef HAVE_PWM -#endif - -#ifndef CONFIG_STM32_TIM4_PWM -# undef HAVE_PWM -#endif - -#if CONFIG_STM32_TIM4_CHANNEL != STM32F3DISCOVERY_PWMCHANNEL -# undef HAVE_PWM -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_pwm_setup - * - * Description: - * Initialize PWM and register the PWM device. - * - ****************************************************************************/ - -int stm32_pwm_setup(void) -{ -#ifdef HAVE_PWM - static bool initialized = false; - struct pwm_lowerhalf_s *pwm; - int ret; - - /* Have we already initialized? */ - - if (!initialized) - { - /* Call stm32_pwminitialize() to get an instance of the PWM interface */ - - pwm = stm32_pwminitialize(STM32F3DISCOVERY_PWMTIMER); - if (!pwm) - { - aerr("ERROR: Failed to get the STM32 PWM lower half\n"); - return -ENODEV; - } - - /* Register the PWM driver at "/dev/pwm0" */ - - ret = pwm_register("/dev/pwm0", pwm); - if (ret < 0) - { - aerr("ERROR: pwm_register failed: %d\n", ret); - return ret; - } - - /* Now we are initialized */ - - initialized = true; - } - - return OK; -#else - return -ENODEV; -#endif -} diff --git a/boards/arm/stm32/stm32f3discovery/src/stm32_spi.c b/boards/arm/stm32/stm32f3discovery/src/stm32_spi.c deleted file mode 100644 index b5a17433a8794..0000000000000 --- a/boards/arm/stm32/stm32f3discovery/src/stm32_spi.c +++ /dev/null @@ -1,182 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f3discovery/src/stm32_spi.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include - -#include -#include - -#include "arm_internal.h" -#include "chip.h" -#include "stm32.h" -#include "stm32f3discovery.h" - -#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || defined(CONFIG_STM32_SPI3) - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_spidev_initialize - * - * Description: - * Called to configure SPI chip select GPIO pins for the stm32f3discovery - * board. - * - ****************************************************************************/ - -void weak_function stm32_spidev_initialize(void) -{ -#ifdef CONFIG_STM32_SPI1 - stm32_configgpio(GPIO_MEMS_CS); /* MEMS chip select */ - stm32_configgpio(GPIO_MEMS_INT1); /* MEMS interrupts */ - stm32_configgpio(GPIO_MEMS_INT2); -#endif -} - -/**************************************************************************** - * Name: stm32_spi1/2/3select and stm32_spi1/2/3status - * - * Description: - * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status - * must be provided by board-specific logic. They are implementations of - * the select and status methods of the SPI interface defined by struct - * spi_ops_s (see include/nuttx/spi/spi.h). All other methods - * (including stm32_spibus_initialize()) are provided by common STM32 logic. - * To use this common SPI logic on your board: - * - * 1. Provide logic in stm32_boardinitialize() to configure SPI chip select - * pins. - * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() functions - * in your board-specific logic. These functions will perform chip - * selection and status operations using GPIOs in the way your board is - * configured. - * 3. Add a calls to stm32_spibus_initialize() in your low level - * application initialization logic - * 4. The handle returned by stm32_spibus_initialize() may then be used to - * bind the SPI driver to higher level logic (e.g., calling - * mmcsd_spislotinitialize(), for example, will bind the SPI driver to - * the SPI MMC/SD driver). - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_SPI1 -void stm32_spi1select(struct spi_dev_s *dev, - uint32_t devid, bool selected) -{ - spiinfo("devid: %d CS: %s\n", - (int)devid, selected ? "assert" : "de-assert"); - - stm32_gpiowrite(GPIO_MEMS_CS, !selected); -} - -uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) -{ - return 0; -} -#endif - -#ifdef CONFIG_STM32_SPI2 -void stm32_spi2select(struct spi_dev_s *dev, - uint32_t devid, bool selected) -{ - spiinfo("devid: %d CS: %s\n", - (int)devid, selected ? "assert" : "de-assert"); -} - -uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) -{ - return 0; -} -#endif - -#ifdef CONFIG_STM32_SPI3 -void stm32_spi3select(struct spi_dev_s *dev, - uint32_t devid, bool selected) -{ - spiinfo("devid: %d CS: %s\n", - (int)devid, selected ? "assert" : "de-assert"); -} - -uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid) -{ - return 0; -} -#endif - -/**************************************************************************** - * Name: stm32_spi1cmddata - * - * Description: - * Set or clear the SH1101A A0 or SD1306 D/C n bit to select data (true) - * or command (false). This function must be provided by platform-specific - * logic. This is an implementation of the cmddata method of the SPI - * interface defined by struct spi_ops_s (see include/nuttx/spi/spi.h). - * - * Input Parameters: - * - * spi - SPI device that controls the bus the device that requires the CMD/ - * DATA selection. - * devid - If there are multiple devices on the bus, this selects which one - * to select cmd or data. NOTE: This design restricts, for example, - * one one SPI display per SPI bus. - * cmd - true: select command; false: select data - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef CONFIG_SPI_CMDDATA -#ifdef CONFIG_STM32_SPI1 -int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) -{ - return -ENODEV; -} -#endif - -#ifdef CONFIG_STM32_SPI2 -int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) -{ - return -ENODEV; -} -#endif - -#ifdef CONFIG_STM32_SPI3 -int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) -{ - return -ENODEV; -} -#endif -#endif /* CONFIG_SPI_CMDDATA */ - -#endif /* CONFIG_STM32_SPI1 || CONFIG_STM32_SPI2 */ diff --git a/boards/arm/stm32/stm32f3discovery/src/stm32_usb.c b/boards/arm/stm32/stm32f3discovery/src/stm32_usb.c deleted file mode 100644 index 375d66d3408e4..0000000000000 --- a/boards/arm/stm32/stm32f3discovery/src/stm32_usb.c +++ /dev/null @@ -1,116 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f3discovery/src/stm32_usb.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include -#include - -#include -#include - -#include "arm_internal.h" -#include "stm32.h" -#include "stm32f3discovery.h" - -#ifdef CONFIG_STM32_USB - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#ifdef CONFIG_USBDEV -# define HAVE_USB 1 -#else -# warning "CONFIG_STM32_USB is enabled but CONFIG_USBDEV is not" -# undef HAVE_USB -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_usbinitialize - * - * Description: - * Called from stm32_usbinitialize very early in initialization to setup - * USB-related GPIO pins for the STM32F3Discovery board. - * - ****************************************************************************/ - -void stm32_usbinitialize(void) -{ - /* Does the STM32 F3 have an external soft pull-up? */ -} - -/**************************************************************************** - * Name: stm32_usbpullup - * - * Description: - * If USB is supported and the board supports a pullup via GPIO (for USB - * software connect and disconnect), then the board software must provide - * stm32_pullup. - * See include/nuttx/usb/usbdev.h for additional description of this - * method. - * - ****************************************************************************/ - -int stm32_usbpullup(struct usbdev_s *dev, bool enable) -{ - usbtrace(TRACE_DEVPULLUP, (uint16_t)enable); - return OK; -} - -/**************************************************************************** - * Name: stm32_usbsuspend - * - * Description: - * Board logic must provide the stm32_usbsuspend logic if the USBDEV driver - * is used. This function is called whenever the USB enters or leaves - * suspend mode. This is an opportunity for the board logic to shutdown - * clocks, power, etc. while the USB is suspended. - * - ****************************************************************************/ - -void stm32_usbsuspend(struct usbdev_s *dev, bool resume) -{ - uinfo("Resume: %d\n", resume); -} - -#endif /* CONFIG_STM32_USB */ diff --git a/boards/arm/stm32/stm32f3discovery/src/stm32_userleds.c b/boards/arm/stm32/stm32f3discovery/src/stm32_userleds.c deleted file mode 100644 index 38ff516b8cb31..0000000000000 --- a/boards/arm/stm32/stm32f3discovery/src/stm32_userleds.c +++ /dev/null @@ -1,103 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f3discovery/src/stm32_userleds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include - -#include "chip.h" -#include "stm32.h" -#include "stm32f3discovery.h" - -#ifndef CONFIG_ARCH_LEDS - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* This array maps an LED number to GPIO pin configuration */ - -static const uint32_t g_ledcfg[BOARD_NLEDS] = -{ - GPIO_LED1, GPIO_LED2, GPIO_LED3, GPIO_LED4, - GPIO_LED5, GPIO_LED6, GPIO_LED7, GPIO_LED8 -}; - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_userled_initialize - ****************************************************************************/ - -uint32_t board_userled_initialize(void) -{ - int i; - - /* Configure LED1-8 GPIOs for output */ - - for (i = 0; i < BOARD_NLEDS; i++) - { - stm32_configgpio(g_ledcfg[i]); - } - - return BOARD_NLEDS; -} - -/**************************************************************************** - * Name: board_userled - ****************************************************************************/ - -void board_userled(int led, bool ledon) -{ - if ((unsigned)led < BOARD_NLEDS) - { - stm32_gpiowrite(g_ledcfg[led], ledon); - } -} - -/**************************************************************************** - * Name: board_userled_all - ****************************************************************************/ - -void board_userled_all(uint32_t ledset) -{ - int i; - - /* Configure LED1-8 GPIOs for output */ - - for (i = 0; i < BOARD_NLEDS; i++) - { - stm32_gpiowrite(g_ledcfg[i], (ledset & (1 << i)) != 0); - } -} - -#endif /* !CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/stm32f401rc-rs485/CMakeLists.txt b/boards/arm/stm32/stm32f401rc-rs485/CMakeLists.txt deleted file mode 100644 index 0c3a3b0299f94..0000000000000 --- a/boards/arm/stm32/stm32f401rc-rs485/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/stm32f401rc-rs485/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32/stm32f401rc-rs485/configs/adc/defconfig b/boards/arm/stm32/stm32f401rc-rs485/configs/adc/defconfig deleted file mode 100644 index 2c10476201ee6..0000000000000 --- a/boards/arm/stm32/stm32f401rc-rs485/configs/adc/defconfig +++ /dev/null @@ -1,66 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -# CONFIG_NSH_DISABLE_IFCONFIG is not set -# CONFIG_NSH_DISABLE_PS is not set -CONFIG_ADC=y -CONFIG_ANALOG=y -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f401rc-rs485" -CONFIG_ARCH_BOARD_STM32F401RC_RS485=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F401RC=y -CONFIG_ARCH_INTERRUPTSTACK=2048 -CONFIG_ARCH_IRQBUTTONS=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARDCTL_USBDEVCTRL=y -CONFIG_BOARD_LOOPSPERMSEC=8499 -CONFIG_BUILTIN=y -CONFIG_CDCACM=y -CONFIG_CDCACM_CONSOLE=y -CONFIG_EXAMPLES_ADC=y -CONFIG_EXAMPLES_ADC_SWTRIG=y -CONFIG_EXAMPLES_BUTTONS=y -CONFIG_EXAMPLES_BUTTONS_NAME0="SW3" -CONFIG_EXAMPLES_BUTTONS_NAME1="SW4" -CONFIG_EXAMPLES_BUTTONS_NAME2="SW5" -CONFIG_EXAMPLES_BUTTONS_NAMES=y -CONFIG_EXAMPLES_BUTTONS_QTD=3 -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INPUT=y -CONFIG_INPUT_BUTTONS=y -CONFIG_INPUT_BUTTONS_LOWER=y -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=98304 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_SPI=y -CONFIG_START_DAY=5 -CONFIG_START_MONTH=5 -CONFIG_START_YEAR=2014 -CONFIG_STM32_ADC1=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_OTGFS=y -CONFIG_STM32_PWR=y -CONFIG_STM32_USART6=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USBDEV=y diff --git a/boards/arm/stm32/stm32f401rc-rs485/configs/bmp280/defconfig b/boards/arm/stm32/stm32f401rc-rs485/configs/bmp280/defconfig deleted file mode 100644 index ee0e197c2655d..0000000000000 --- a/boards/arm/stm32/stm32f401rc-rs485/configs/bmp280/defconfig +++ /dev/null @@ -1,68 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -# CONFIG_NSH_DISABLE_IFCONFIG is not set -# CONFIG_NSH_DISABLE_PS is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f401rc-rs485" -CONFIG_ARCH_BOARD_COMMON=y -CONFIG_ARCH_BOARD_STM32F401RC_RS485=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F401RC=y -CONFIG_ARCH_INTERRUPTSTACK=2048 -CONFIG_ARCH_IRQBUTTONS=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BMP280_I2C_ADDR_77=y -CONFIG_BOARDCTL_USBDEVCTRL=y -CONFIG_BOARD_LOOPSPERMSEC=8499 -CONFIG_BUILTIN=y -CONFIG_CDCACM=y -CONFIG_CDCACM_CONSOLE=y -CONFIG_EXAMPLES_BMP280=y -CONFIG_EXAMPLES_BUTTONS=y -CONFIG_EXAMPLES_BUTTONS_NAME0="SW3" -CONFIG_EXAMPLES_BUTTONS_NAME1="SW4" -CONFIG_EXAMPLES_BUTTONS_NAME2="SW5" -CONFIG_EXAMPLES_BUTTONS_NAMES=y -CONFIG_EXAMPLES_BUTTONS_QTD=3 -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INPUT=y -CONFIG_INPUT_BUTTONS=y -CONFIG_INPUT_BUTTONS_LOWER=y -CONFIG_INTELHEX_BINARY=y -CONFIG_LIBC_FLOATINGPOINT=y -CONFIG_LINE_MAX=64 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=98304 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_SENSORS=y -CONFIG_SENSORS_BMP280=y -CONFIG_SPI=y -CONFIG_START_DAY=5 -CONFIG_START_MONTH=5 -CONFIG_START_YEAR=2014 -CONFIG_STM32_I2C1=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_OTGFS=y -CONFIG_STM32_PWR=y -CONFIG_STM32_USART6=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USBDEV=y diff --git a/boards/arm/stm32/stm32f401rc-rs485/configs/dac/defconfig b/boards/arm/stm32/stm32f401rc-rs485/configs/dac/defconfig deleted file mode 100644 index 4487a2834aaa9..0000000000000 --- a/boards/arm/stm32/stm32f401rc-rs485/configs/dac/defconfig +++ /dev/null @@ -1,66 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -# CONFIG_NSH_DISABLE_IFCONFIG is not set -# CONFIG_NSH_DISABLE_PS is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f401rc-rs485" -CONFIG_ARCH_BOARD_STM32F401RC_RS485=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F401RC=y -CONFIG_ARCH_INTERRUPTSTACK=2048 -CONFIG_ARCH_IRQBUTTONS=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARDCTL_USBDEVCTRL=y -CONFIG_BOARD_LOOPSPERMSEC=8499 -CONFIG_BUILTIN=y -CONFIG_CDCACM=y -CONFIG_CDCACM_CONSOLE=y -CONFIG_EXAMPLES_BUTTONS=y -CONFIG_EXAMPLES_BUTTONS_NAME0="SW3" -CONFIG_EXAMPLES_BUTTONS_NAME1="SW4" -CONFIG_EXAMPLES_BUTTONS_NAME2="SW5" -CONFIG_EXAMPLES_BUTTONS_NAMES=y -CONFIG_EXAMPLES_BUTTONS_QTD=3 -CONFIG_EXAMPLES_PWM=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INPUT=y -CONFIG_INPUT_BUTTONS=y -CONFIG_INPUT_BUTTONS_LOWER=y -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_PWM=y -CONFIG_RAM_SIZE=98304 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_SPI=y -CONFIG_START_DAY=5 -CONFIG_START_MONTH=5 -CONFIG_START_YEAR=2014 -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_OTGFS=y -CONFIG_STM32_PWR=y -CONFIG_STM32_TIM3=y -CONFIG_STM32_TIM3_CH1OUT=y -CONFIG_STM32_TIM3_PWM=y -CONFIG_STM32_USART6=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USBDEV=y diff --git a/boards/arm/stm32/stm32f401rc-rs485/configs/hcsr04/defconfig b/boards/arm/stm32/stm32f401rc-rs485/configs/hcsr04/defconfig deleted file mode 100644 index 87491419a250a..0000000000000 --- a/boards/arm/stm32/stm32f401rc-rs485/configs/hcsr04/defconfig +++ /dev/null @@ -1,66 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -# CONFIG_NSH_DISABLE_IFCONFIG is not set -# CONFIG_NSH_DISABLE_PS is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f401rc-rs485" -CONFIG_ARCH_BOARD_COMMON=y -CONFIG_ARCH_BOARD_STM32F401RC_RS485=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F401RC=y -CONFIG_ARCH_INTERRUPTSTACK=2048 -CONFIG_ARCH_IRQBUTTONS=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARDCTL_USBDEVCTRL=y -CONFIG_BOARD_LOOPSPERMSEC=8499 -CONFIG_BUILTIN=y -CONFIG_CDCACM=y -CONFIG_CDCACM_CONSOLE=y -CONFIG_EXAMPLES_BUTTONS=y -CONFIG_EXAMPLES_BUTTONS_NAME0="SW3" -CONFIG_EXAMPLES_BUTTONS_NAME1="SW4" -CONFIG_EXAMPLES_BUTTONS_NAME2="SW5" -CONFIG_EXAMPLES_BUTTONS_NAMES=y -CONFIG_EXAMPLES_BUTTONS_QTD=3 -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INPUT=y -CONFIG_INPUT_BUTTONS=y -CONFIG_INPUT_BUTTONS_LOWER=y -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=98304 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_SENSORS=y -CONFIG_SENSORS_HCSR04=y -CONFIG_SPI=y -CONFIG_START_DAY=5 -CONFIG_START_MONTH=5 -CONFIG_START_YEAR=2014 -CONFIG_STM32_FREERUN=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_OTGFS=y -CONFIG_STM32_PWR=y -CONFIG_STM32_TIM1=y -CONFIG_STM32_USART6=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USBDEV=y diff --git a/boards/arm/stm32/stm32f401rc-rs485/configs/lcd1602/defconfig b/boards/arm/stm32/stm32f401rc-rs485/configs/lcd1602/defconfig deleted file mode 100644 index 68f78a2565b3a..0000000000000 --- a/boards/arm/stm32/stm32f401rc-rs485/configs/lcd1602/defconfig +++ /dev/null @@ -1,67 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -# CONFIG_NSH_DISABLE_IFCONFIG is not set -# CONFIG_NSH_DISABLE_PS is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f401rc-rs485" -CONFIG_ARCH_BOARD_COMMON=y -CONFIG_ARCH_BOARD_STM32F401RC_RS485=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F401RC=y -CONFIG_ARCH_INTERRUPTSTACK=2048 -CONFIG_ARCH_IRQBUTTONS=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARDCTL_USBDEVCTRL=y -CONFIG_BOARD_LOOPSPERMSEC=8499 -CONFIG_BUILTIN=y -CONFIG_CDCACM=y -CONFIG_CDCACM_CONSOLE=y -CONFIG_EXAMPLES_BUTTONS=y -CONFIG_EXAMPLES_BUTTONS_NAME0="SW3" -CONFIG_EXAMPLES_BUTTONS_NAME1="SW4" -CONFIG_EXAMPLES_BUTTONS_NAME2="SW5" -CONFIG_EXAMPLES_BUTTONS_NAMES=y -CONFIG_EXAMPLES_BUTTONS_QTD=3 -CONFIG_EXAMPLES_SLCD=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_I2C=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INPUT=y -CONFIG_INPUT_BUTTONS=y -CONFIG_INPUT_BUTTONS_LOWER=y -CONFIG_INTELHEX_BINARY=y -CONFIG_LCD_BACKPACK=y -CONFIG_LINE_MAX=64 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=98304 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_SLCD=y -CONFIG_SPI=y -CONFIG_START_DAY=5 -CONFIG_START_MONTH=5 -CONFIG_START_YEAR=2014 -CONFIG_STM32_I2C1=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_OTGFS=y -CONFIG_STM32_PWR=y -CONFIG_STM32_USART6=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USBDEV=y diff --git a/boards/arm/stm32/stm32f401rc-rs485/configs/lm75/defconfig b/boards/arm/stm32/stm32f401rc-rs485/configs/lm75/defconfig deleted file mode 100644 index b431f061e801c..0000000000000 --- a/boards/arm/stm32/stm32f401rc-rs485/configs/lm75/defconfig +++ /dev/null @@ -1,72 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -# CONFIG_NSH_DISABLE_IFCONFIG is not set -# CONFIG_NSH_DISABLE_PS is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f401rc-rs485" -CONFIG_ARCH_BOARD_COMMON=y -CONFIG_ARCH_BOARD_STM32F401RC_RS485=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F401RC=y -CONFIG_ARCH_INTERRUPTSTACK=2048 -CONFIG_ARCH_IRQBUTTONS=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARDCTL_USBDEVCTRL=y -CONFIG_BOARD_LOOPSPERMSEC=8499 -CONFIG_BUILTIN=y -CONFIG_CDCACM=y -CONFIG_CDCACM_CONSOLE=y -CONFIG_EXAMPLES_BUTTONS=y -CONFIG_EXAMPLES_BUTTONS_NAME0="SW3" -CONFIG_EXAMPLES_BUTTONS_NAME1="SW4" -CONFIG_EXAMPLES_BUTTONS_NAME2="SW5" -CONFIG_EXAMPLES_BUTTONS_NAMES=y -CONFIG_EXAMPLES_BUTTONS_QTD=3 -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_I2CTOOL_MAXBUS=1 -CONFIG_I2CTOOL_MINBUS=1 -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INPUT=y -CONFIG_INPUT_BUTTONS=y -CONFIG_INPUT_BUTTONS_LOWER=y -CONFIG_INTELHEX_BINARY=y -CONFIG_LIBC_FLOATINGPOINT=y -CONFIG_LINE_MAX=64 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=98304 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_SENSORS=y -CONFIG_SENSORS_LM75=y -CONFIG_SPI=y -CONFIG_START_DAY=5 -CONFIG_START_MONTH=5 -CONFIG_START_YEAR=2014 -CONFIG_STM32_I2C1=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_OTGFS=y -CONFIG_STM32_PWR=y -CONFIG_STM32_USART6=y -CONFIG_SYSTEM_I2CTOOL=y -CONFIG_SYSTEM_LM75=y -CONFIG_SYSTEM_LM75_CELSIUS=y -CONFIG_SYSTEM_LM75_DEVNAME="/dev/temp0" -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USBDEV=y diff --git a/boards/arm/stm32/stm32f401rc-rs485/configs/max7219/defconfig b/boards/arm/stm32/stm32f401rc-rs485/configs/max7219/defconfig deleted file mode 100644 index 100a1658edffc..0000000000000 --- a/boards/arm/stm32/stm32f401rc-rs485/configs/max7219/defconfig +++ /dev/null @@ -1,73 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -# CONFIG_NSH_DISABLE_IFCONFIG is not set -# CONFIG_NSH_DISABLE_PS is not set -# CONFIG_NX_DISABLE_1BPP is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f401rc-rs485" -CONFIG_ARCH_BOARD_COMMON=y -CONFIG_ARCH_BOARD_STM32F401RC_RS485=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F401RC=y -CONFIG_ARCH_INTERRUPTSTACK=2048 -CONFIG_ARCH_IRQBUTTONS=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARDCTL_USBDEVCTRL=y -CONFIG_BOARD_LOOPSPERMSEC=8499 -CONFIG_BUILTIN=y -CONFIG_CDCACM=y -CONFIG_CDCACM_CONSOLE=y -CONFIG_EXAMPLES_BUTTONS=y -CONFIG_EXAMPLES_BUTTONS_NAME0="SW3" -CONFIG_EXAMPLES_BUTTONS_NAME1="SW4" -CONFIG_EXAMPLES_BUTTONS_NAME2="SW5" -CONFIG_EXAMPLES_BUTTONS_NAMES=y -CONFIG_EXAMPLES_BUTTONS_QTD=3 -CONFIG_EXAMPLES_NXHELLO=y -CONFIG_EXAMPLES_NXHELLO_BPP=1 -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INPUT=y -CONFIG_INPUT_BUTTONS=y -CONFIG_INPUT_BUTTONS_LOWER=y -CONFIG_INTELHEX_BINARY=y -CONFIG_LCD=y -CONFIG_LCD_FRAMEBUFFER=y -CONFIG_LCD_MAX7219=y -CONFIG_LCD_NOGETRUN=y -CONFIG_LINE_MAX=64 -CONFIG_MQ_MAXMSGSIZE=64 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_NX=y -CONFIG_NXFONT_MONO5X8=y -CONFIG_NX_BLOCKING=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=98304 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=5 -CONFIG_START_MONTH=5 -CONFIG_START_YEAR=2014 -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_OTGFS=y -CONFIG_STM32_PWR=y -CONFIG_STM32_SPI1=y -CONFIG_STM32_USART6=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USBDEV=y diff --git a/boards/arm/stm32/stm32f401rc-rs485/configs/mfrc522/defconfig b/boards/arm/stm32/stm32f401rc-rs485/configs/mfrc522/defconfig deleted file mode 100644 index d24b43acad199..0000000000000 --- a/boards/arm/stm32/stm32f401rc-rs485/configs/mfrc522/defconfig +++ /dev/null @@ -1,65 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -# CONFIG_NSH_DISABLE_IFCONFIG is not set -# CONFIG_NSH_DISABLE_PS is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f401rc-rs485" -CONFIG_ARCH_BOARD_COMMON=y -CONFIG_ARCH_BOARD_STM32F401RC_RS485=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F401RC=y -CONFIG_ARCH_INTERRUPTSTACK=2048 -CONFIG_ARCH_IRQBUTTONS=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARDCTL_USBDEVCTRL=y -CONFIG_BOARD_LOOPSPERMSEC=8499 -CONFIG_BUILTIN=y -CONFIG_CDCACM=y -CONFIG_CDCACM_CONSOLE=y -CONFIG_CL_MFRC522=y -CONFIG_DRIVERS_CONTACTLESS=y -CONFIG_EXAMPLES_BUTTONS=y -CONFIG_EXAMPLES_BUTTONS_NAME0="SW3" -CONFIG_EXAMPLES_BUTTONS_NAME1="SW4" -CONFIG_EXAMPLES_BUTTONS_NAME2="SW5" -CONFIG_EXAMPLES_BUTTONS_NAMES=y -CONFIG_EXAMPLES_BUTTONS_QTD=3 -CONFIG_EXAMPLES_RFID_READUID=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INPUT=y -CONFIG_INPUT_BUTTONS=y -CONFIG_INPUT_BUTTONS_LOWER=y -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=98304 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=5 -CONFIG_START_MONTH=5 -CONFIG_START_YEAR=2014 -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_OTGFS=y -CONFIG_STM32_PWR=y -CONFIG_STM32_SPI1=y -CONFIG_STM32_USART6=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USBDEV=y diff --git a/boards/arm/stm32/stm32f401rc-rs485/configs/modbus_master/defconfig b/boards/arm/stm32/stm32f401rc-rs485/configs/modbus_master/defconfig deleted file mode 100644 index 2e5ad3de7e2fd..0000000000000 --- a/boards/arm/stm32/stm32f401rc-rs485/configs/modbus_master/defconfig +++ /dev/null @@ -1,76 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_MB_MASTER_FUNC_READWRITE_HOLDING_ENABLED is not set -# CONFIG_MB_MASTER_FUNC_READ_COILS_ENABLED is not set -# CONFIG_MB_MASTER_FUNC_READ_DISCRETE_INPUTS_ENABLED is not set -# CONFIG_MB_MASTER_FUNC_READ_INPUT_ENABLED is not set -# CONFIG_MB_MASTER_FUNC_WRITE_COIL_ENABLED is not set -# CONFIG_MB_MASTER_FUNC_WRITE_HOLDING_ENABLED is not set -# CONFIG_MB_MASTER_FUNC_WRITE_MULTIPLE_COILS_ENABLED is not set -# CONFIG_MB_MASTER_FUNC_WRITE_MULTIPLE_HOLDING_ENABLED is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -# CONFIG_NSH_DISABLE_IFCONFIG is not set -# CONFIG_NSH_DISABLE_PS is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f401rc-rs485" -CONFIG_ARCH_BOARD_STM32F401RC_RS485=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F401RC=y -CONFIG_ARCH_INTERRUPTSTACK=2048 -CONFIG_ARCH_IRQBUTTONS=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=8499 -CONFIG_BUILTIN=y -CONFIG_EXAMPLES_BUTTONS=y -CONFIG_EXAMPLES_BUTTONS_NAME0="SW3" -CONFIG_EXAMPLES_BUTTONS_NAME1="SW4" -CONFIG_EXAMPLES_BUTTONS_NAME2="SW5" -CONFIG_EXAMPLES_BUTTONS_NAME3="SW6" -CONFIG_EXAMPLES_BUTTONS_NAMES=y -CONFIG_EXAMPLES_BUTTONS_QTD=4 -CONFIG_EXAMPLES_MODBUSMASTER=y -CONFIG_EXAMPLES_MODBUSMASTER_SLAVEADDR=10 -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_INDUSTRY_MODBUS=y -CONFIG_INDUSTRY_MODBUS_MASTER=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INPUT=y -CONFIG_INPUT_BUTTONS=y -CONFIG_INPUT_BUTTONS_LOWER=y -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_MB_RTU_MASTER=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=98304 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_SPI=y -CONFIG_START_DAY=5 -CONFIG_START_MONTH=5 -CONFIG_START_YEAR=2014 -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_OTGFS=y -CONFIG_STM32_PWR=y -CONFIG_STM32_USART2=y -CONFIG_STM32_USART6=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART2_BAUD=38400 -CONFIG_USART2_PARITY=2 -CONFIG_USART2_RS485=y -CONFIG_USART6_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/stm32f401rc-rs485/configs/modbus_slave/defconfig b/boards/arm/stm32/stm32f401rc-rs485/configs/modbus_slave/defconfig deleted file mode 100644 index 199a6fe8f2321..0000000000000 --- a/boards/arm/stm32/stm32f401rc-rs485/configs/modbus_slave/defconfig +++ /dev/null @@ -1,69 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_MB_ASCII_ENABLED is not set -# CONFIG_MB_TCP_ENABLED is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -# CONFIG_NSH_DISABLE_IFCONFIG is not set -# CONFIG_NSH_DISABLE_PS is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f401rc-rs485" -CONFIG_ARCH_BOARD_STM32F401RC_RS485=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F401RC=y -CONFIG_ARCH_INTERRUPTSTACK=2048 -CONFIG_ARCH_IRQBUTTONS=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=8499 -CONFIG_BUILTIN=y -CONFIG_EXAMPLES_BUTTONS=y -CONFIG_EXAMPLES_BUTTONS_NAME0="SW3" -CONFIG_EXAMPLES_BUTTONS_NAME1="SW4" -CONFIG_EXAMPLES_BUTTONS_NAME2="SW5" -CONFIG_EXAMPLES_BUTTONS_NAME3="SW6" -CONFIG_EXAMPLES_BUTTONS_NAMES=y -CONFIG_EXAMPLES_BUTTONS_QTD=4 -CONFIG_EXAMPLES_MODBUS=y -CONFIG_EXAMPLES_MODBUS_PORT=1 -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_INDUSTRY_MODBUS=y -CONFIG_INDUSTRY_MODBUS_SLAVE=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INPUT=y -CONFIG_INPUT_BUTTONS=y -CONFIG_INPUT_BUTTONS_LOWER=y -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=98304 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_SPI=y -CONFIG_START_DAY=5 -CONFIG_START_MONTH=5 -CONFIG_START_YEAR=2014 -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_OTGFS=y -CONFIG_STM32_PWR=y -CONFIG_STM32_USART2=y -CONFIG_STM32_USART6=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART2_BAUD=38400 -CONFIG_USART2_PARITY=2 -CONFIG_USART2_RS485=y -CONFIG_USART6_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/stm32f401rc-rs485/configs/nsh/defconfig b/boards/arm/stm32/stm32f401rc-rs485/configs/nsh/defconfig deleted file mode 100644 index 4effd9f205643..0000000000000 --- a/boards/arm/stm32/stm32f401rc-rs485/configs/nsh/defconfig +++ /dev/null @@ -1,58 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -# CONFIG_NSH_DISABLE_IFCONFIG is not set -# CONFIG_NSH_DISABLE_PS is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f401rc-rs485" -CONFIG_ARCH_BOARD_STM32F401RC_RS485=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F401RC=y -CONFIG_ARCH_INTERRUPTSTACK=2048 -CONFIG_ARCH_IRQBUTTONS=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=8499 -CONFIG_BUILTIN=y -CONFIG_EXAMPLES_BUTTONS=y -CONFIG_EXAMPLES_BUTTONS_NAME0="SW3" -CONFIG_EXAMPLES_BUTTONS_NAME1="SW4" -CONFIG_EXAMPLES_BUTTONS_NAME2="SW5" -CONFIG_EXAMPLES_BUTTONS_NAMES=y -CONFIG_EXAMPLES_BUTTONS_QTD=3 -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INPUT=y -CONFIG_INPUT_BUTTONS=y -CONFIG_INPUT_BUTTONS_LOWER=y -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=98304 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_SPI=y -CONFIG_START_DAY=5 -CONFIG_START_MONTH=5 -CONFIG_START_YEAR=2014 -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_OTGFS=y -CONFIG_STM32_PWR=y -CONFIG_STM32_USART6=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART6_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/stm32f401rc-rs485/configs/qencoder/defconfig b/boards/arm/stm32/stm32f401rc-rs485/configs/qencoder/defconfig deleted file mode 100644 index 041d1063cf925..0000000000000 --- a/boards/arm/stm32/stm32f401rc-rs485/configs/qencoder/defconfig +++ /dev/null @@ -1,67 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -# CONFIG_NSH_DISABLE_IFCONFIG is not set -# CONFIG_NSH_DISABLE_PS is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f401rc-rs485" -CONFIG_ARCH_BOARD_COMMON=y -CONFIG_ARCH_BOARD_STM32F401RC_RS485=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F401RC=y -CONFIG_ARCH_INTERRUPTSTACK=2048 -CONFIG_ARCH_IRQBUTTONS=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARDCTL_USBDEVCTRL=y -CONFIG_BOARD_LOOPSPERMSEC=8499 -CONFIG_BUILTIN=y -CONFIG_CDCACM=y -CONFIG_CDCACM_CONSOLE=y -CONFIG_EXAMPLES_BUTTONS=y -CONFIG_EXAMPLES_BUTTONS_NAME0="SW3" -CONFIG_EXAMPLES_BUTTONS_NAME1="SW4" -CONFIG_EXAMPLES_BUTTONS_NAME2="SW5" -CONFIG_EXAMPLES_BUTTONS_NAMES=y -CONFIG_EXAMPLES_BUTTONS_QTD=3 -CONFIG_EXAMPLES_QENCODER=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INPUT=y -CONFIG_INPUT_BUTTONS=y -CONFIG_INPUT_BUTTONS_LOWER=y -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=98304 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_SENSORS=y -CONFIG_SENSORS_QENCODER=y -CONFIG_SPI=y -CONFIG_START_DAY=5 -CONFIG_START_MONTH=5 -CONFIG_START_YEAR=2014 -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_OTGFS=y -CONFIG_STM32_PWR=y -CONFIG_STM32_TIM3=y -CONFIG_STM32_TIM3_QE=y -CONFIG_STM32_USART6=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USBDEV=y diff --git a/boards/arm/stm32/stm32f401rc-rs485/configs/rndis/defconfig b/boards/arm/stm32/stm32f401rc-rs485/configs/rndis/defconfig deleted file mode 100644 index e6a0c65cdab01..0000000000000 --- a/boards/arm/stm32/stm32f401rc-rs485/configs/rndis/defconfig +++ /dev/null @@ -1,86 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f401rc-rs485" -CONFIG_ARCH_BOARD_STM32F401RC_RS485=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F401RC=y -CONFIG_ARCH_INTERRUPTSTACK=2048 -CONFIG_ARCH_IRQBUTTONS=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARDCTL_USBDEVCTRL=y -CONFIG_BOARD_LOOPSPERMSEC=8499 -CONFIG_BUILTIN=y -CONFIG_DEBUG_FULLOPT=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_EXAMPLES_BUTTONS=y -CONFIG_EXAMPLES_BUTTONS_NAME0="SW3" -CONFIG_EXAMPLES_BUTTONS_NAME1="SW4" -CONFIG_EXAMPLES_BUTTONS_NAME2="SW5" -CONFIG_EXAMPLES_BUTTONS_NAMES=y -CONFIG_EXAMPLES_BUTTONS_QTD=3 -CONFIG_FS_PROCFS=y -CONFIG_FS_TMPFS=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INPUT=y -CONFIG_INPUT_BUTTONS=y -CONFIG_INPUT_BUTTONS_LOWER=y -CONFIG_INTELHEX_BINARY=y -CONFIG_LIBC_MEMFD_ERROR=y -CONFIG_LINE_MAX=64 -CONFIG_NET=y -CONFIG_NETDB_DNSCLIENT=y -CONFIG_NETDB_DNSSERVER_IPv4ADDR=0x0 -CONFIG_NETDEV_LATEINIT=y -CONFIG_NETINIT_DHCPC=y -CONFIG_NETINIT_DRIPADDR=0x0 -CONFIG_NETINIT_NETMASK=0x0 -CONFIG_NETINIT_NOMAC=y -CONFIG_NETINIT_THREAD=y -CONFIG_NETUTILS_DHCPC=y -CONFIG_NETUTILS_TELNETD=y -CONFIG_NETUTILS_WEBCLIENT=y -CONFIG_NET_BROADCAST=y -CONFIG_NET_ICMP_SOCKET=y -CONFIG_NET_LOOPBACK=y -CONFIG_NET_STATISTICS=y -CONFIG_NET_TCP=y -CONFIG_NET_TCP_WRITE_BUFFERS=y -CONFIG_NET_UDP=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_DISABLE_IFUPDOWN=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=98304 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RNDIS=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_LPWORK=y -CONFIG_SCHED_WAITPID=y -CONFIG_SPI=y -CONFIG_START_DAY=5 -CONFIG_START_MONTH=5 -CONFIG_START_YEAR=2014 -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_OTGFS=y -CONFIG_STM32_PWR=y -CONFIG_STM32_USART6=y -CONFIG_SYSTEM_NSH=y -CONFIG_SYSTEM_PING=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART6_SERIAL_CONSOLE=y -CONFIG_USBDEV=y diff --git a/boards/arm/stm32/stm32f401rc-rs485/configs/sdcard/defconfig b/boards/arm/stm32/stm32f401rc-rs485/configs/sdcard/defconfig deleted file mode 100644 index bdd8cbb1b33f4..0000000000000 --- a/boards/arm/stm32/stm32f401rc-rs485/configs/sdcard/defconfig +++ /dev/null @@ -1,69 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_MMCSD_HAVE_WRITEPROTECT is not set -# CONFIG_MMCSD_SPI is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f401rc-rs485" -CONFIG_ARCH_BOARD_STM32F401RC_RS485=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F401RC=y -CONFIG_ARCH_INTERRUPTSTACK=2048 -CONFIG_ARCH_IRQBUTTONS=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=8499 -CONFIG_BUILTIN=y -CONFIG_EXAMPLES_BUTTONS=y -CONFIG_EXAMPLES_BUTTONS_NAME0="SW3" -CONFIG_EXAMPLES_BUTTONS_NAME1="SW4" -CONFIG_EXAMPLES_BUTTONS_NAME2="SW5" -CONFIG_EXAMPLES_BUTTONS_NAME3="SW6" -CONFIG_EXAMPLES_BUTTONS_NAMES=y -CONFIG_EXAMPLES_BUTTONS_QTD=4 -CONFIG_FAT_LCNAMES=y -CONFIG_FAT_LFN=y -CONFIG_FS_FAT=y -CONFIG_FS_PROCFS=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INPUT=y -CONFIG_INPUT_BUTTONS=y -CONFIG_INPUT_BUTTONS_LOWER=y -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_MMCSD=y -CONFIG_MMCSD_SDIO=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_DISABLE_IFUPDOWN=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=98304 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_WAITPID=y -CONFIG_SPI=y -CONFIG_START_DAY=5 -CONFIG_START_MONTH=5 -CONFIG_START_YEAR=2014 -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_OTGFS=y -CONFIG_STM32_PWR=y -CONFIG_STM32_SDIO=y -CONFIG_STM32_SDIO_CARD=y -CONFIG_STM32_USART6=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART6_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/stm32f401rc-rs485/configs/ssd1309/defconfig b/boards/arm/stm32/stm32f401rc-rs485/configs/ssd1309/defconfig deleted file mode 100644 index 0ebbf98d62c77..0000000000000 --- a/boards/arm/stm32/stm32f401rc-rs485/configs/ssd1309/defconfig +++ /dev/null @@ -1,69 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f401rc-rs485" -CONFIG_ARCH_BOARD_COMMON=y -CONFIG_ARCH_BOARD_STM32F401RC_RS485=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F401RC=y -CONFIG_ARCH_INTERRUPTSTACK=2048 -CONFIG_ARCH_IRQBUTTONS=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARDCTL_USBDEVCTRL=y -CONFIG_BOARD_LOOPSPERMSEC=8499 -CONFIG_BUILTIN=y -CONFIG_CDCACM=y -CONFIG_CDCACM_CONSOLE=y -CONFIG_DRIVERS_VIDEO=y -CONFIG_EXAMPLES_BUTTONS=y -CONFIG_EXAMPLES_BUTTONS_NAME0="SW3" -CONFIG_EXAMPLES_BUTTONS_NAME1="SW4" -CONFIG_EXAMPLES_BUTTONS_NAME2="SW5" -CONFIG_EXAMPLES_BUTTONS_NAMES=y -CONFIG_EXAMPLES_BUTTONS_QTD=3 -CONFIG_EXAMPLES_FB=y -CONFIG_FS_PROCFS=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INPUT=y -CONFIG_INPUT_BUTTONS=y -CONFIG_INPUT_BUTTONS_LOWER=y -CONFIG_INTELHEX_BINARY=y -CONFIG_LCD=y -CONFIG_LCD_DD12864WO4A=y -CONFIG_LCD_FRAMEBUFFER=y -CONFIG_LCD_NOGETRUN=y -CONFIG_LINE_MAX=64 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_DISABLE_IFUPDOWN=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=98304 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=5 -CONFIG_START_MONTH=5 -CONFIG_START_YEAR=2014 -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_OTGFS=y -CONFIG_STM32_PWR=y -CONFIG_STM32_SPI1=y -CONFIG_STM32_USART6=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USBDEV=y -CONFIG_VIDEO_FB=y diff --git a/boards/arm/stm32/stm32f401rc-rs485/configs/telnetd/defconfig b/boards/arm/stm32/stm32f401rc-rs485/configs/telnetd/defconfig deleted file mode 100644 index 38212b7cf512e..0000000000000 --- a/boards/arm/stm32/stm32f401rc-rs485/configs/telnetd/defconfig +++ /dev/null @@ -1,91 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -# CONFIG_SYSTEM_TELNETD is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f401rc-rs485" -CONFIG_ARCH_BOARD_STM32F401RC_RS485=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F401RC=y -CONFIG_ARCH_INTERRUPTSTACK=2048 -CONFIG_ARCH_IRQBUTTONS=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARDCTL_RESET=y -CONFIG_BOARDCTL_USBDEVCTRL=y -CONFIG_BOARD_LOOPSPERMSEC=8499 -CONFIG_BUILTIN=y -CONFIG_DEBUG_FULLOPT=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_EXAMPLES_BUTTONS=y -CONFIG_EXAMPLES_BUTTONS_NAME0="SW3" -CONFIG_EXAMPLES_BUTTONS_NAME1="SW4" -CONFIG_EXAMPLES_BUTTONS_NAME2="SW5" -CONFIG_EXAMPLES_BUTTONS_NAMES=y -CONFIG_EXAMPLES_BUTTONS_QTD=3 -CONFIG_EXAMPLES_TELNETD=y -CONFIG_EXAMPLES_TELNETD_DRIPADDR=0xC0A80101 -CONFIG_EXAMPLES_TELNETD_IPADDR=0xC0A80102 -CONFIG_FS_PROCFS=y -CONFIG_FS_TMPFS=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INPUT=y -CONFIG_INPUT_BUTTONS=y -CONFIG_INPUT_BUTTONS_LOWER=y -CONFIG_INTELHEX_BINARY=y -CONFIG_LIBC_MEMFD_ERROR=y -CONFIG_LINE_MAX=64 -CONFIG_NET=y -CONFIG_NETDB_DNSCLIENT=y -CONFIG_NETDB_DNSSERVER_IPv4ADDR=0x0 -CONFIG_NETDEV_LATEINIT=y -CONFIG_NETINIT_DRIPADDR=0xC0A80101 -CONFIG_NETINIT_IPADDR=0xC0A80102 -CONFIG_NETINIT_NETMASK=0xFFFFFF00 -CONFIG_NETINIT_NOMAC=y -CONFIG_NETINIT_THREAD=y -CONFIG_NETUTILS_DHCPC=y -CONFIG_NETUTILS_TELNETD=y -CONFIG_NETUTILS_WEBCLIENT=y -CONFIG_NET_BROADCAST=y -CONFIG_NET_ICMP_SOCKET=y -CONFIG_NET_LOOPBACK=y -CONFIG_NET_STATISTICS=y -CONFIG_NET_TCP=y -CONFIG_NET_TCP_WRITE_BUFFERS=y -CONFIG_NET_UDP=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_DISABLE_IFUPDOWN=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=98304 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RNDIS=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_LPWORK=y -CONFIG_SCHED_WAITPID=y -CONFIG_SPI=y -CONFIG_START_DAY=5 -CONFIG_START_MONTH=5 -CONFIG_START_YEAR=2014 -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_OTGFS=y -CONFIG_STM32_PWR=y -CONFIG_STM32_USART6=y -CONFIG_SYSTEM_NSH=y -CONFIG_SYSTEM_PING=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART6_SERIAL_CONSOLE=y -CONFIG_USBDEV=y diff --git a/boards/arm/stm32/stm32f401rc-rs485/configs/usbmsc/defconfig b/boards/arm/stm32/stm32f401rc-rs485/configs/usbmsc/defconfig deleted file mode 100644 index 8810cd175f3d1..0000000000000 --- a/boards/arm/stm32/stm32f401rc-rs485/configs/usbmsc/defconfig +++ /dev/null @@ -1,74 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_MMCSD_HAVE_WRITEPROTECT is not set -# CONFIG_MMCSD_SPI is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f401rc-rs485" -CONFIG_ARCH_BOARD_STM32F401RC_RS485=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F401RC=y -CONFIG_ARCH_INTERRUPTSTACK=2048 -CONFIG_ARCH_IRQBUTTONS=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=8499 -CONFIG_BUILTIN=y -CONFIG_EXAMPLES_BUTTONS=y -CONFIG_EXAMPLES_BUTTONS_NAME0="SW3" -CONFIG_EXAMPLES_BUTTONS_NAME1="SW4" -CONFIG_EXAMPLES_BUTTONS_NAME2="SW5" -CONFIG_EXAMPLES_BUTTONS_NAME3="SW6" -CONFIG_EXAMPLES_BUTTONS_NAMES=y -CONFIG_EXAMPLES_BUTTONS_QTD=4 -CONFIG_FAT_LCNAMES=y -CONFIG_FAT_LFN=y -CONFIG_FS_FAT=y -CONFIG_FS_PROCFS=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INPUT=y -CONFIG_INPUT_BUTTONS=y -CONFIG_INPUT_BUTTONS_LOWER=y -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_MMCSD=y -CONFIG_MMCSD_SDIO=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_DISABLE_IFUPDOWN=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=98304 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_WAITPID=y -CONFIG_SPI=y -CONFIG_START_DAY=5 -CONFIG_START_MONTH=5 -CONFIG_START_YEAR=2014 -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_OTGFS=y -CONFIG_STM32_PWR=y -CONFIG_STM32_SDIO=y -CONFIG_STM32_SDIO_CARD=y -CONFIG_STM32_USART6=y -CONFIG_SYSTEM_NSH=y -CONFIG_SYSTEM_USBMSC=y -CONFIG_SYSTEM_USBMSC_DEVMINOR1=0 -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART6_SERIAL_CONSOLE=y -CONFIG_USBDEV=y -CONFIG_USBMSC=y -CONFIG_USBMSC_REMOVABLE=y diff --git a/boards/arm/stm32/stm32f401rc-rs485/configs/usbnsh/defconfig b/boards/arm/stm32/stm32f401rc-rs485/configs/usbnsh/defconfig deleted file mode 100644 index 8394c946d47cd..0000000000000 --- a/boards/arm/stm32/stm32f401rc-rs485/configs/usbnsh/defconfig +++ /dev/null @@ -1,61 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -# CONFIG_NSH_DISABLE_IFCONFIG is not set -# CONFIG_NSH_DISABLE_PS is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f401rc-rs485" -CONFIG_ARCH_BOARD_STM32F401RC_RS485=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F401RC=y -CONFIG_ARCH_INTERRUPTSTACK=2048 -CONFIG_ARCH_IRQBUTTONS=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARDCTL_USBDEVCTRL=y -CONFIG_BOARD_LOOPSPERMSEC=8499 -CONFIG_BUILTIN=y -CONFIG_CDCACM=y -CONFIG_CDCACM_CONSOLE=y -CONFIG_EXAMPLES_BUTTONS=y -CONFIG_EXAMPLES_BUTTONS_NAME0="SW3" -CONFIG_EXAMPLES_BUTTONS_NAME1="SW4" -CONFIG_EXAMPLES_BUTTONS_NAME2="SW5" -CONFIG_EXAMPLES_BUTTONS_NAMES=y -CONFIG_EXAMPLES_BUTTONS_QTD=3 -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INPUT=y -CONFIG_INPUT_BUTTONS=y -CONFIG_INPUT_BUTTONS_LOWER=y -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=98304 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_SPI=y -CONFIG_START_DAY=5 -CONFIG_START_MONTH=5 -CONFIG_START_YEAR=2014 -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_OTGFS=y -CONFIG_STM32_PWR=y -CONFIG_STM32_USART6=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USBDEV=y diff --git a/boards/arm/stm32/stm32f401rc-rs485/configs/ws2812/defconfig b/boards/arm/stm32/stm32f401rc-rs485/configs/ws2812/defconfig deleted file mode 100644 index 7f4abba8eac5a..0000000000000 --- a/boards/arm/stm32/stm32f401rc-rs485/configs/ws2812/defconfig +++ /dev/null @@ -1,67 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -# CONFIG_NSH_DISABLE_IFCONFIG is not set -# CONFIG_NSH_DISABLE_PS is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f401rc-rs485" -CONFIG_ARCH_BOARD_COMMON=y -CONFIG_ARCH_BOARD_STM32F401RC_RS485=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F401RC=y -CONFIG_ARCH_INTERRUPTSTACK=2048 -CONFIG_ARCH_IRQBUTTONS=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARDCTL_USBDEVCTRL=y -CONFIG_BOARD_LOOPSPERMSEC=8499 -CONFIG_BUILTIN=y -CONFIG_CDCACM=y -CONFIG_CDCACM_CONSOLE=y -CONFIG_EXAMPLES_BUTTONS=y -CONFIG_EXAMPLES_BUTTONS_NAME0="SW3" -CONFIG_EXAMPLES_BUTTONS_NAME1="SW4" -CONFIG_EXAMPLES_BUTTONS_NAME2="SW5" -CONFIG_EXAMPLES_BUTTONS_NAMES=y -CONFIG_EXAMPLES_BUTTONS_QTD=3 -CONFIG_EXAMPLES_WS2812=y -CONFIG_EXAMPLES_WS2812_DEFAULT_DEV="/dev/leddrv0" -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INPUT=y -CONFIG_INPUT_BUTTONS=y -CONFIG_INPUT_BUTTONS_LOWER=y -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=98304 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=5 -CONFIG_START_MONTH=5 -CONFIG_START_YEAR=2014 -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_OTGFS=y -CONFIG_STM32_PWR=y -CONFIG_STM32_SPI1=y -CONFIG_STM32_USART6=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USBDEV=y -CONFIG_WS2812=y -CONFIG_WS2812_FREQUENCY=9000000 -CONFIG_WS2812_LED_COUNT=10 diff --git a/boards/arm/stm32/stm32f401rc-rs485/include/board.h b/boards/arm/stm32/stm32f401rc-rs485/include/board.h deleted file mode 100644 index 537c0650e1f76..0000000000000 --- a/boards/arm/stm32/stm32f401rc-rs485/include/board.h +++ /dev/null @@ -1,470 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f401rc-rs485/include/board.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __BOARDS_ARM_STM32F401RC_RS485_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32F401RC_RS485_INCLUDE_BOARD_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#ifndef __ASSEMBLY__ -# include -#endif - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Clocking *****************************************************************/ - -/* The STM32F401RC-RS485 uses an external 32kHz crystal (X2) to enable HSE - * clock. - * - * System Clock source : PLL (HSI) - * SYSCLK(Hz) : 84000000 Determined by PLL - * configuration - * HCLK(Hz) : 84000000 (STM32_RCC_CFGR_HPRE) - * AHB Prescaler : 1 (STM32_RCC_CFGR_HPRE) - * APB1 Prescaler : 2 (STM32_RCC_CFGR_PPRE1) - * APB2 Prescaler : 1 (STM32_RCC_CFGR_PPRE2) - * HSI Frequency(Hz) : 16000000 (nominal) - * PLLM : 16 (STM32_PLLCFG_PLLM) - * PLLN : 336 (STM32_PLLCFG_PLLN) - * PLLP : 4 (STM32_PLLCFG_PLLP) - * PLLQ : 7 (STM32_PLLCFG_PPQ) - * Flash Latency(WS) : 5 - * Prefetch Buffer : OFF - * Instruction cache : ON - * Data cache : ON - * Require 48MHz for USB OTG FS, : Enabled - * SDIO and RNG clock - */ - -/* HSI - 16 MHz RC factory-trimmed - * LSI - 32 KHz RC - * HSE - not installed - * LSE - not installed - */ - -#define STM32_HSI_FREQUENCY 16000000ul -#define STM32_LSI_FREQUENCY 32000 -#define STM32_BOARD_USEHSI 1 - -/* Main PLL Configuration. - * - * Formulae: - * - * VCO input frequency = PLL input clock frequency / PLLM, - * 2 <= PLLM <= 63 - * VCO output frequency = VCO input frequency × PLLN, - * 192 <= PLLN <= 432 - * PLL output clock frequency = VCO frequency / PLLP, - * PLLP = 2, 4, 6, or 8 - * USB OTG FS clock frequency = VCO frequency / PLLQ, - * 2 <= PLLQ <= 15 - * - * We would like to have SYSYCLK=84MHz and we must have the USB clock= 48MHz. - * Some possible solutions include: - * - * PLLN=210 PLLM=5 PLLP=8 PLLQ=14 SYSCLK=84000000 OTGFS=48000000 - * PLLN=210 PLLM=10 PLLP=4 PLLQ=7 SYSCLK=84000000 OTGFS=48000000 - * PLLN=336 PLLM=8 PLLP=8 PLLQ=14 SYSCLK=84000000 OTGFS=48000000 - * PLLN=336 PLLM=16 PLLP=4 PLLQ=7 SYSCLK=84000000 OTGFS=48000000 - * PLLN=420 PLLM=10 PLLP=8 PLLQ=14 SYSCLK=84000000 OTGFS=48000000 - * PLLN=420 PLLM=20 PLLP=4 PLLQ=7 SYSCLK=84000000 OTGFS=48000000 - * - * We will configure like this - * - * PLL source is HSI - * PLL_VCO = (STM32_HSI_FREQUENCY / PLLM) * PLLN - * = (16,000,000 / 16) * 336 - * = 336,000,000 - * SYSCLK = PLL_VCO / PLLP - * = 336,000,000 / 4 = 84,000,000 - * USB OTG FS and SDIO Clock - * = PLL_VCO / PLLQ - * = 336,000,000 / 7 = 48,000,000 - * - * REVISIT: Trimming of the HSI is not yet supported. - */ - -#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(16) -#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(336) -#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_4 -#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(7) - -#define STM32_SYSCLK_FREQUENCY 84000000ul - -/* AHB clock (HCLK) is SYSCLK (84MHz) */ - -#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ -#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY - -/* APB1 clock (PCLK1) is HCLK/2 (42MHz) */ - -#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd2 /* PCLK1 = HCLK / 2 */ -#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/2) - -/* Timers driven from APB1 will be twice PCLK1 */ - -/* REVISIT */ - -#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) - -/* APB2 clock (PCLK2) is HCLK (84MHz) */ - -#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ -#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/1) - -/* Timers driven from APB2 will be twice PCLK2 */ - -/* REVISIT */ - -#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM9_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB2_TIM10_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB2_TIM11_CLKIN (2*STM32_PCLK1_FREQUENCY) - -/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx - * otherwise frequency is 2xAPBx. - * Note: TIM1,8 are on APB2, others on APB1 - */ - -/* REVISIT */ - -#define BOARD_TIM1_FREQUENCY (2*STM32_PCLK2_FREQUENCY) -#define BOARD_TIM2_FREQUENCY (2*STM32_PCLK1_FREQUENCY) -#define BOARD_TIM3_FREQUENCY (2*STM32_PCLK1_FREQUENCY) -#define BOARD_TIM4_FREQUENCY (2*STM32_PCLK1_FREQUENCY) -#define BOARD_TIM5_FREQUENCY (2*STM32_PCLK1_FREQUENCY) -#define BOARD_TIM6_FREQUENCY (2*STM32_PCLK1_FREQUENCY) -#define BOARD_TIM7_FREQUENCY (2*STM32_PCLK1_FREQUENCY) -#define BOARD_TIM8_FREQUENCY (2*STM32_PCLK2_FREQUENCY) - -/* SDIO dividers. Note that slower clocking is required when DMA is disabled - * in order to avoid RX overrun/TX underrun errors due to delayed responses - * to service FIFOs in interrupt driven mode. These values have not been - * tuned!!! - * - * HCLK=72MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(178+2)=400 KHz - */ - -/* REVISIT */ - -#define SDIO_INIT_CLKDIV (178 << SDIO_CLKCR_CLKDIV_SHIFT) - -/* DMA ON: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(2+2)=18 MHz - * DMA OFF: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(3+2)=14.4 MHz - */ - -/* REVISIT */ - -#ifdef CONFIG_SDIO_DMA -# define SDIO_MMCXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT) -#else -# define SDIO_MMCXFR_CLKDIV (3 << SDIO_CLKCR_CLKDIV_SHIFT) -#endif - -/* DMA ON: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(1+2)=24 MHz - * DMA OFF: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(3+2)=14.4 MHz - */ - -/* REVISIT */ - -#ifdef CONFIG_SDIO_DMA -# define SDIO_SDXFR_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT) -#else -# define SDIO_SDXFR_CLKDIV (3 << SDIO_CLKCR_CLKDIV_SHIFT) -#endif - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -#ifndef __ASSEMBLY__ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* DMA Channel/Stream Selections ********************************************/ - -/* Stream selections are arbitrary for now but might become important in - * the future is we set aside more DMA channels/streams. - * - * SDIO DMA - *   DMAMAP_SDIO_1 = Channel 4, Stream 3 <- may later be used by SPI DMA - *   DMAMAP_SDIO_2 = Channel 4, Stream 6 - */ - -#define DMAMAP_SDIO DMAMAP_SDIO_1 - -/* Need to VERIFY fwb */ - -#define DMACHAN_SPI1_RX DMAMAP_SPI1_RX_1 -#define DMACHAN_SPI1_TX DMAMAP_SPI1_TX_1 -#define DMACHAN_SPI2_RX DMAMAP_SPI2_RX -#define DMACHAN_SPI2_TX DMAMAP_SPI2_TX - -/* Alternate function pin selections ****************************************/ - -/* USART2: - * RXD: PA3 CN4 pin 20 - * TXD: PA2 CN4 pin 18 - */ - -#ifdef CONFIG_USART2_RS485 - /* Lets use for RS485 */ - -# define GPIO_USART2_TX (GPIO_USART2_TX_1|GPIO_SPEED_100MHz) /* PA2 */ -# define GPIO_USART2_RX (GPIO_USART2_RX_1|GPIO_SPEED_100MHz) /* PA3 */ - - /* RS485 DIR pin: PA1 */ - -# define GPIO_USART2_RS485_DIR (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_50MHz |\ - GPIO_OUTPUT_CLEAR | GPIO_PORTA | GPIO_PIN1) - -#endif - -/* USART6: - * RXD: PC7 CN2 pin 15 - * TXD: PC6 CN2 pin 17 - */ - -#define GPIO_USART6_RX (GPIO_USART6_RX_1|GPIO_SPEED_100MHz) /* PC7 */ -#define GPIO_USART6_TX (GPIO_USART6_TX_1|GPIO_SPEED_100MHz) /* PC6 */ - -/* PWM - * - * The STM32F401RC-RS485 has no real on-board PWM devices, but the board - * can be configured to output a pulse train using TIM3 CH1 on PA6. - */ - -#define GPIO_TIM3_CH1OUT (GPIO_TIM3_CH1OUT_1|GPIO_SPEED_50MHz) - -/* Quadrature Encoder - * - * Use Timer 3 (TIM3) on channels 1 and 2 for QEncoder, using PB4 and PA7. - */ - -#define GPIO_TIM3_CH1IN GPIO_TIM3_CH1IN_2 -#define GPIO_TIM3_CH2IN GPIO_TIM3_CH2IN_1 - -/* HCSR04 driver */ - -/* Pins config to use with HC-SR04 sensor */ - -#define GPIO_HCSR04_INT (GPIO_INPUT |GPIO_FLOAT |GPIO_EXTI | GPIO_PORTB | GPIO_PIN1) -#define GPIO_HCSR04_TRIG (GPIO_OUTPUT_CLEAR | GPIO_OUTPUT | GPIO_SPEED_50MHz | GPIO_PORTB | GPIO_PIN0) - -#define BOARD_HCSR04_GPIO_INT GPIO_HCSR04_INT -#define BOARD_HCSR04_GPIO_TRIG GPIO_HCSR04_TRIG -#define BOARD_HCSR04_FRTIMER 1 /* TIM1 as free running timer */ - -/* I2C - * - * The optional _GPIO configurations allow the I2C driver to manually - * reset the bus to clear stuck slaves. They match the pin configuration, - * but are normally-high GPIOs. - */ - -#define GPIO_I2C1_SCL (GPIO_I2C1_SCL_2|GPIO_SPEED_50MHz) -#define GPIO_I2C1_SDA (GPIO_I2C1_SDA_1|GPIO_SPEED_50MHz) - -#define GPIO_I2C2_SCL (GPIO_I2C2_SCL_1|GPIO_SPEED_50MHz) -#define GPIO_I2C2_SDA (GPIO_I2C2_SDA_2|GPIO_SPEED_50MHz) - -/* SPI - * - * There are sensors on SPI1, and SPI2 is connected to the FRAM. - */ - -#define GPIO_SPI1_MISO (GPIO_SPI1_MISO_1|GPIO_SPEED_50MHz) -#define GPIO_SPI1_MOSI (GPIO_SPI1_MOSI_1|GPIO_SPEED_50MHz) -#define GPIO_SPI1_SCK (GPIO_SPI1_SCK_1|GPIO_SPEED_50MHz) - -#define GPIO_SPI2_MISO (GPIO_SPI2_MISO_1|GPIO_SPEED_50MHz) -#define GPIO_SPI2_MOSI (GPIO_SPI2_MOSI_1|GPIO_SPEED_50MHz) -#define GPIO_SPI2_SCK (GPIO_SPI2_SCK_2|GPIO_SPEED_50MHz) - -/* MAX7219 */ - -#define STM32_LCD_CS (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz|\ - GPIO_OUTPUT_SET|GPIO_PORTC|GPIO_PIN4) - -/* MFRC522 */ - -#define GPIO_RFID_CS (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz|\ - GPIO_OUTPUT_SET|GPIO_PORTC|GPIO_PIN5) - -/* MAX31855 */ - -#define GPIO_MAX31855_CS (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz|\ - GPIO_OUTPUT_SET|GPIO_PORTC|GPIO_PIN4) - -/* MAX6675 */ - -#define GPIO_MAX6675_CS (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz|\ - GPIO_OUTPUT_SET|GPIO_PORTC|GPIO_PIN5) -/* LEDs - * - * The STM32F401RC-RS485 boards provide 4 blue user LEDs. LD1, LD2, LD3 - * and LD4 that are connected to MCU I/O pins PC0, PC1, PC2 and PC3. - * - When the I/O is HIGH value, the LED is on. - * - When the I/O is LOW, the LED is off. - */ - -/* LED index values for use with board_userled() */ - -#define BOARD_LD1 0 -#define BOARD_LD2 1 -#define BOARD_LD3 2 -#define BOARD_LD4 3 -#define BOARD_NLEDS 4 - -/* LED bits for use with board_userled_all() */ - -#define BOARD_LED1_BIT (1 << BOARD_LD1) -#define BOARD_LED2_BIT (1 << BOARD_LD2) -#define BOARD_LED3_BIT (1 << BOARD_LD3) -#define BOARD_LED4_BIT (1 << BOARD_LD4) - -/* These LEDs are not used by the board port unless CONFIG_ARCH_LEDS is - * defined. In that case, the usage by the board port is defined in - * include/board.h and src/sam_leds.c. The LEDs are used to encode OS-related - * events as follows when the red LED (PE24) is available: - * - * SYMBOL Meaning LD2 - * ------------------- ----------------------- ----------- - * LED_STARTED NuttX has been started OFF - * LED_HEAPALLOCATE Heap has been allocated OFF - * LED_IRQSENABLED Interrupts enabled OFF - * LED_STACKCREATED Idle stack created ON - * LED_INIRQ In an interrupt No change - * LED_SIGNAL In a signal handler No change - * LED_ASSERTION An assertion failed No change - * LED_PANIC The system has crashed Blinking - * LED_IDLE MCU is in sleep mode Not used - * - * Thus if LD2, NuttX has successfully booted and is, apparently, running - * normally. If LD2 is flashing at approximately 2Hz, then a fatal error - * has been detected and the system has halted. - */ - -#define LED_STARTED 0 -#define LED_HEAPALLOCATE 0 -#define LED_IRQSENABLED 0 -#define LED_STACKCREATED 1 -#define LED_INIRQ 2 -#define LED_SIGNAL 2 -#define LED_ASSERTION 2 -#define LED_PANIC 1 - -/* Buttons - * The STM32F401RC-RS485 has 3 user buttons: SW3, SW4, and SW5. - * They are connected to PB13, PB14, and PB15 respectively. - */ - -#define BUTTON_SW3 0 -#define BUTTON_SW4 1 -#define BUTTON_SW5 2 -#define NUM_BUTTONS 3 - -#define BUTTON_SW3_BIT (1 << BUTTON_SW3) -#define BUTTON_SW4_BIT (1 << BUTTON_SW4) -#define BUTTON_SW5_BIT (1 << BUTTON_SW5) - -#define GPIO_TIM2_CH1IN (GPIO_TIM2_CH1IN_1 | GPIO_PULLUP | GPIO_SPEED_50MHz) -#define GPIO_TIM2_CH2IN (GPIO_TIM2_CH2IN_1 | GPIO_PULLUP | GPIO_SPEED_50MHz) - -/* Stepper Motor - DRV8266 */ - -#define GPIO_DIR (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz|\ - GPIO_OUTPUT_CLEAR|GPIO_PORTA|GPIO_PIN7) -#define GPIO_STEP (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz|\ - GPIO_OUTPUT_CLEAR|GPIO_PORTC|GPIO_PIN4) -#define GPIO_SLEEP (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz|\ - GPIO_OUTPUT_CLEAR|GPIO_PORTC|GPIO_PIN5) - -#define GPIO_M1 (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz|\ - GPIO_OUTPUT_CLEAR|GPIO_PORTB|GPIO_PIN0) -#define GPIO_M2 (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz|\ - GPIO_OUTPUT_CLEAR|GPIO_PORTB|GPIO_PIN1) -#define GPIO_M3 (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz|\ - GPIO_OUTPUT_CLEAR|GPIO_PORTB|GPIO_PIN2) - -#define GPIO_RESET (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz|\ - GPIO_OUTPUT_CLEAR|GPIO_PORTB|GPIO_PIN10) - -/* DAC */ - -#define GPIO_DAC1_OUT1 GPIO_DAC1_OUT1_0 -#define GPIO_DAC1_OUT2 GPIO_DAC1_OUT2_0 - -/* SDIO */ - -#define GPIO_SDIO_CK (GPIO_SDIO_CK_0|GPIO_SPEED_50MHz) -#define GPIO_SDIO_CMD (GPIO_SDIO_CMD_0|GPIO_SPEED_50MHz) -#define GPIO_SDIO_D0 (GPIO_SDIO_D0_0|GPIO_SPEED_50MHz) -#define GPIO_SDIO_D1 (GPIO_SDIO_D1_0|GPIO_SPEED_50MHz) -#define GPIO_SDIO_D2 (GPIO_SDIO_D2_0|GPIO_SPEED_50MHz) -#define GPIO_SDIO_D3 (GPIO_SDIO_D3_0|GPIO_SPEED_50MHz) - -/* USB OTG FS */ - -#define GPIO_OTGFS_DM (GPIO_OTGFS_DM_0|GPIO_SPEED_100MHz) -#define GPIO_OTGFS_DP (GPIO_OTGFS_DP_0|GPIO_SPEED_100MHz) -#define GPIO_OTGFS_ID (GPIO_OTGFS_ID_0|GPIO_SPEED_100MHz) -#define GPIO_OTGFS_SOF (GPIO_OTGFS_SOF_0|GPIO_SPEED_100MHz) - -#endif /* __BOARDS_ARM_STM32F401RC_RS485_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32/stm32f401rc-rs485/scripts/Make.defs b/boards/arm/stm32/stm32f401rc-rs485/scripts/Make.defs deleted file mode 100644 index ac4d63351981c..0000000000000 --- a/boards/arm/stm32/stm32f401rc-rs485/scripts/Make.defs +++ /dev/null @@ -1,46 +0,0 @@ -############################################################################ -# boards/arm/stm32/stm32f401rc-rs485/scripts/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/.config -include $(TOPDIR)/tools/Config.mk -include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs - -ifeq ($(CONFIG_ARCH_CHIP_STM32F401RC),y) -LDSCRIPT = ld.script -endif - -ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) - -ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 - -CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) -CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) -CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) - -AFLAGS := $(CFLAGS) -D__ASSEMBLY__ - -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections -LDNXFLATFLAGS = -e main -s 2048 - diff --git a/boards/arm/stm32/stm32f401rc-rs485/scripts/ld.script b/boards/arm/stm32/stm32f401rc-rs485/scripts/ld.script deleted file mode 100644 index 855e00562cec4..0000000000000 --- a/boards/arm/stm32/stm32f401rc-rs485/scripts/ld.script +++ /dev/null @@ -1,109 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f401rc-rs485/scripts/ld.script - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* The STM32F401RC has 256Kb of FLASH beginning at address 0x0800:0000 and - * 64Kb of SRAM beginning at address 0x2000:0000. When booting from FLASH, - * FLASH memory is aliased to address 0x0000:0000 where the code expects to - * begin execution by jumping to the entry point in the 0x0800:0000 address - * range. - */ - -MEMORY -{ - flash (rx) : ORIGIN = 0x08000000, LENGTH = 256K - sram (rwx) : ORIGIN = 0x20000000, LENGTH = 64K -} - -OUTPUT_ARCH(arm) -EXTERN(_vectors) -ENTRY(_stext) -SECTIONS -{ - .text : { - _stext = ABSOLUTE(.); - *(.vectors) - *(.text .text.*) - *(.fixup) - *(.gnu.warning) - *(.rodata .rodata.*) - *(.gnu.linkonce.t.*) - *(.glue_7) - *(.glue_7t) - *(.got) - *(.gcc_except_table) - *(.gnu.linkonce.r.*) - _etext = ABSOLUTE(.); - } > flash - - .init_section : { - _sinit = ABSOLUTE(.); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) - KEEP(*(.init_array .ctors)) - _einit = ABSOLUTE(.); - } > flash - - .ARM.extab : { - *(.ARM.extab*) - } > flash - - __exidx_start = ABSOLUTE(.); - .ARM.exidx : { - *(.ARM.exidx*) - } > flash - __exidx_end = ABSOLUTE(.); - - _eronly = ABSOLUTE(.); - - /* The STM32F401RC has 128Kb of SRAM beginning at the following address */ - - .data : { - _sdata = ABSOLUTE(.); - *(.data .data.*) - *(.gnu.linkonce.d.*) - CONSTRUCTORS - . = ALIGN(4); - _edata = ABSOLUTE(.); - } > sram AT > flash - - .bss : { - _sbss = ABSOLUTE(.); - *(.bss .bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - . = ALIGN(4); - _ebss = ABSOLUTE(.); - } > sram - - /* Stabs debugging sections. */ - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_info 0 : { *(.debug_info) } - .debug_line 0 : { *(.debug_line) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_aranges 0 : { *(.debug_aranges) } -} diff --git a/boards/arm/stm32/stm32f401rc-rs485/src/CMakeLists.txt b/boards/arm/stm32/stm32f401rc-rs485/src/CMakeLists.txt deleted file mode 100644 index bf67263f69295..0000000000000 --- a/boards/arm/stm32/stm32f401rc-rs485/src/CMakeLists.txt +++ /dev/null @@ -1,86 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/stm32f401rc-rs485/src/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -set(SRCS stm32_boot.c stm32_bringup.c) - -if(CONFIG_ARCH_LEDS) - list(APPEND SRCS stm32_autoleds.c) -endif() - -if(CONFIG_USERLED) - list(APPEND SRCS stm32_userleds.c) -endif() - -if(CONFIG_BOARDCTL_RESET) - list(APPEND SRCS stm32_reset.c) -endif() - -if(CONFIG_ARCH_BUTTONS) - list(APPEND SRCS stm32_buttons.c) -endif() - -if(CONFIG_ADC) - list(APPEND SRCS stm32_adc.c) -endif() - -if(CONFIG_STM32_SDIO) - list(APPEND SRCS stm32_sdio.c) -endif() - -if(CONFIG_STM32_OTGFS) - list(APPEND SRCS stm32_usb.c) -endif() - -if(CONFIG_STM32_CONFIG_I2C_EE_24XXEEPROM) - list(APPEND SRCS stm32_at24.c) -endif() - -if(CONFIG_STM32_PWM) - list(APPEND SRCS stm32_pwm.c) -endif() - -if(CONFIG_USBMSC) - list(APPEND SRCS stm32_usbmsc.c) -endif() - -if(CONFIG_DEV_GPIO) - list(APPEND SRCS stm32_gpio.c) -endif() - -if(CONFIG_VIDEO_FB) - if(CONFIG_LCD_SSD1306) - list(APPEND SRCS stm32_lcd_ssd1306.c) - endif() - if(CONFIG_LCD_ST7735) - list(APPEND SRCS stm32_lcd_st7735.c) - endif() -endif() - -if(CONFIG_ADC_HX711) - list(APPEND SRCS stm32_hx711.c) -endif() - -target_sources(board PRIVATE ${SRCS}) - -if(CONFIG_ARCH_CHIP_STM32F401RC) - set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/ld.script") -endif() diff --git a/boards/arm/stm32/stm32f401rc-rs485/src/Make.defs b/boards/arm/stm32/stm32f401rc-rs485/src/Make.defs deleted file mode 100644 index 122740343adba..0000000000000 --- a/boards/arm/stm32/stm32f401rc-rs485/src/Make.defs +++ /dev/null @@ -1,86 +0,0 @@ -############################################################################ -# boards/arm/stm32/stm32f401rc-rs485/src/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/Make.defs - -CSRCS = stm32_boot.c stm32_bringup.c stm32_spi.c - -ifeq ($(CONFIG_VIDEO_FB),y) - ifeq ($(CONFIG_LCD_SSD1306),y) - CSRCS += stm32_lcd_ssd1306.c - endif - ifeq ($(CONFIG_LCD_ST7735),y) - CSRCS += stm32_lcd_st7735.c - endif -endif - -ifeq ($(CONFIG_ARCH_LEDS),y) -CSRCS += stm32_autoleds.c -endif - -ifeq ($(CONFIG_USERLED),y) -CSRCS += stm32_userleds.c -endif - -ifeq ($(CONFIG_BOARDCTL_RESET),y) -CSRCS += stm32_reset.c -endif - -ifeq ($(CONFIG_ARCH_BUTTONS),y) -CSRCS += stm32_buttons.c -endif - -ifeq ($(CONFIG_ADC),y) -CSRCS += stm32_adc.c -endif - -ifeq ($(CONFIG_STM32_SDIO),y) -CSRCS += stm32_sdio.c -endif - -ifeq ($(CONFIG_STM32_OTGFS),y) -CSRCS += stm32_usb.c -endif - -ifeq ($(CONFIG_I2C_EE_24XX),y) -CSRCS += stm32_at24.c -endif - -ifeq ($(CONFIG_STM32_PWM),y) -CSRCS += stm32_pwm.c -endif - -ifeq ($(CONFIG_USBMSC),y) -CSRCS += stm32_usbmsc.c -endif - -ifeq ($(CONFIG_DEV_GPIO),y) -CSRCS += stm32_gpio.c -endif - -ifeq ($(CONFIG_ADC_HX711),y) -CSRCS += stm32_hx711.c -endif - -DEPPATH += --dep-path board -VPATH += :board -CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/stm32f401rc-rs485/src/stm32_adc.c b/boards/arm/stm32/stm32f401rc-rs485/src/stm32_adc.c deleted file mode 100644 index a8a60d7a591aa..0000000000000 --- a/boards/arm/stm32/stm32f401rc-rs485/src/stm32_adc.c +++ /dev/null @@ -1,119 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f401rc-rs485/src/stm32_adc.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32_pwm.h" -#include "stm32_adc.h" -#include "stm32f401rc-rs485.h" - -#ifdef CONFIG_STM32_ADC1 - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* The number of ADC channels in the conversion list */ - -#define ADC1_NCHANNELS 2 - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* Identifying number of each ADC channel. */ - -/* There are two trimpots on the board connected to ADC1_IN0 and ADC1_IN4 */ - -static const uint8_t g_adc1_chanlist[ADC1_NCHANNELS] = -{ - 0, 4 -}; - -/* Configurations of pins used byte each ADC channels */ - -static const uint32_t g_adc1_pinlist[ADC1_NCHANNELS] = -{ - GPIO_ADC\1_IN\2_0, - GPIO_ADC\1_IN\2_0 -}; - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_adc_setup - * - * Description: - * Initialize ADC and register the ADC driver. - * - ****************************************************************************/ - -int stm32_adc_setup(void) -{ - struct adc_dev_s *adc; - int ret; - int i; - - /* Configure the pins as analog inputs for the selected channels */ - - for (i = 0; i < ADC1_NCHANNELS; i++) - { - stm32_configgpio(g_adc1_pinlist[i]); - } - - /* Call stm32_adcinitialize() to get an instance of the ADC interface */ - - adc = stm32_adcinitialize(1, g_adc1_chanlist, ADC1_NCHANNELS); - if (adc == NULL) - { - aerr("ERROR: Failed to get ADC interface\n"); - return -ENODEV; - } - - /* Register the ADC driver at "/dev/adc0" */ - - ret = adc_register("/dev/adc0", adc); - if (ret < 0) - { - aerr("ERROR: adc_register failed: %d\n", ret); - return ret; - } - - return OK; -} - -#endif /* CONFIG_STM32_ADC1 */ diff --git a/boards/arm/stm32/stm32f401rc-rs485/src/stm32_at24.c b/boards/arm/stm32/stm32f401rc-rs485/src/stm32_at24.c deleted file mode 100644 index 4d37aa0c64f5d..0000000000000 --- a/boards/arm/stm32/stm32f401rc-rs485/src/stm32_at24.c +++ /dev/null @@ -1,97 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f401rc-rs485/src/stm32_at24.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include -#include -#include -#include - -#include -#include - -#include "stm32f401rc-rs485.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#define AT24_I2C_BUS 1 /* EEPROM chip is configured to use I2C1 */ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_at24_init - * - * Description: - * Initialize and configure the AT24 serial EEPROM - * - ****************************************************************************/ - -int stm32_at24_init(char *path) -{ - struct i2c_master_s *i2c; - static bool initialized = false; - int ret; - - /* Have we already initialized? */ - - if (!initialized) - { - /* No.. Get the I2C bus driver */ - - finfo("Initialize I2C%d\n", AT24_I2C_BUS); - i2c = stm32_i2cbus_initialize(AT24_I2C_BUS); - if (!i2c) - { - ferr("ERROR: Failed to initialize I2C%d\n", AT24_I2C_BUS); - return -ENODEV; - } - - /* Now bind the I2C interface to the AT24 I2C EEPROM driver */ - - finfo("Bind the AT24 EEPROM driver to I2C%d\n", AT24_I2C_BUS); - ret = ee24xx_initialize(i2c, 0x50, path, EEPROM_AT24CM02, false); - if (ret < 0) - { - ferr("ERROR: Failed to bind I2C%d to the AT24 EEPROM driver\n", - AT24_I2C_BUS); - return -ENODEV; - } - - /* Now we are initialized */ - - initialized = true; - } - - return OK; -} - diff --git a/boards/arm/stm32/stm32f401rc-rs485/src/stm32_autoleds.c b/boards/arm/stm32/stm32f401rc-rs485/src/stm32_autoleds.c deleted file mode 100644 index dd989cc1f1488..0000000000000 --- a/boards/arm/stm32/stm32f401rc-rs485/src/stm32_autoleds.c +++ /dev/null @@ -1,83 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f401rc-rs485/src/stm32_autoleds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32.h" -#include "stm32f401rc-rs485.h" - -#include - -#ifdef CONFIG_ARCH_LEDS - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_autoled_initialize - ****************************************************************************/ - -void board_autoled_initialize(void) -{ - /* Configure LD2 GPIO for output */ - - stm32_configgpio(GPIO_LED1); -} - -/**************************************************************************** - * Name: board_autoled_on - ****************************************************************************/ - -void board_autoled_on(int led) -{ - if (led == 1) - { - stm32_gpiowrite(GPIO_LED1, true); - } -} - -/**************************************************************************** - * Name: board_autoled_off - ****************************************************************************/ - -void board_autoled_off(int led) -{ - if (led == 1) - { - stm32_gpiowrite(GPIO_LED1, false); - } -} - -#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/stm32f401rc-rs485/src/stm32_boot.c b/boards/arm/stm32/stm32f401rc-rs485/src/stm32_boot.c deleted file mode 100644 index e4a5038168bbe..0000000000000 --- a/boards/arm/stm32/stm32f401rc-rs485/src/stm32_boot.c +++ /dev/null @@ -1,93 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f401rc-rs485/src/stm32_boot.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include - -#include - -#include "arm_internal.h" -#include "stm32f401rc-rs485.h" - -#include - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_boardinitialize - * - * Description: - * All STM32 architectures must provide the following entry point. - * This entry point is called early in the initialization -- after all - * memory has been configured and mapped but before any devices have been - * initialized. - * - ****************************************************************************/ - -void stm32_boardinitialize(void) -{ - /* Configure on-board LEDs if LED support has been selected. */ - -#ifdef CONFIG_ARCH_LEDS - board_autoled_initialize(); -#endif - - /* Configure SPI chip selects if - * 1) SPI is not disabled, and - * 2) the weak function stm32_spidev_initialize() has been brought into - * the link. - */ - -#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) - stm32_spidev_initialize(); -#endif -} - -/**************************************************************************** - * Name: board_late_initialize - * - * Description: - * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional - * initialization call will be performed in the boot-up sequence to a - * function called board_late_initialize(). board_late_initialize() will - * be called immediately after up_initialize() is called and just before - * the initial application is started. This additional initialization - * phase may be used, for example, to initialize board-specific device - * drivers. - * - ****************************************************************************/ - -#ifdef CONFIG_BOARD_LATE_INITIALIZE -void board_late_initialize(void) -{ - stm32_bringup(); -} -#endif diff --git a/boards/arm/stm32/stm32f401rc-rs485/src/stm32_bringup.c b/boards/arm/stm32/stm32f401rc-rs485/src/stm32_bringup.c deleted file mode 100644 index eaf5642cb8a2b..0000000000000 --- a/boards/arm/stm32/stm32f401rc-rs485/src/stm32_bringup.c +++ /dev/null @@ -1,404 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f401rc-rs485/src/stm32_bringup.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include - -#include -#include - -#include - -#ifdef CONFIG_USERLED -# include -#endif - -#ifdef CONFIG_INPUT_BUTTONS -# include -#endif - -#include "stm32f401rc-rs485.h" - -#include - -#ifdef CONFIG_SENSORS_LM75 -#include "stm32_lm75.h" -#endif - -#ifdef CONFIG_SENSORS_QENCODER -#include "board_qencoder.h" -#endif - -#ifdef CONFIG_RNDIS -# include -#endif - -#ifdef CONFIG_SENSORS_HCSR04 -#include "stm32_hcsr04.h" -#endif - -#ifdef CONFIG_LCD_MAX7219 -#include "stm32_max7219_matrix.h" -#endif - -#ifdef CONFIG_CL_MFRC522 -#include "stm32_mfrc522.h" -#endif - -#ifdef CONFIG_STEPPER_DRV8825 -#include "stm32_drv8266.h" -#endif - -#ifdef CONFIG_SENSORS_BMP280 -#include "stm32_bmp280.h" -#endif - -#ifdef CONFIG_LCD_BACKPACK -#include "stm32_lcd_backpack.h" -#endif - -#ifdef CONFIG_WS2812 -#include "stm32_ws2812.h" -#endif - -#ifdef CONFIG_SENSORS_BMP180 -#include "stm32_bmp180.h" -#endif - -#ifdef CONFIG_SENSORS_MAX31855 -#include "stm32_max31855.h" -#endif - -#ifdef CONFIG_SENSORS_MAX6675 -#include "stm32_max6675.h" -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_i2c_register - * - * Description: - * Register one I2C drivers for the I2C tool. - * - ****************************************************************************/ - -#if defined(CONFIG_I2C) && defined(CONFIG_SYSTEM_I2CTOOL) -static void stm32_i2c_register(int bus) -{ - struct i2c_master_s *i2c; - int ret; - - i2c = stm32_i2cbus_initialize(bus); - if (i2c == NULL) - { - syslog(LOG_ERR, "ERROR: Failed to get I2C%d interface\n", bus); - } - else - { - ret = i2c_register(i2c, bus); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: Failed to register I2C%d driver: %d\n", - bus, ret); - stm32_i2cbus_uninitialize(i2c); - } - } -} -#endif - -/**************************************************************************** - * Name: stm32_i2ctool - * - * Description: - * Register I2C drivers for the I2C tool. - * - ****************************************************************************/ - -#if defined(CONFIG_I2C) && defined(CONFIG_SYSTEM_I2CTOOL) -static void stm32_i2ctool(void) -{ - stm32_i2c_register(1); -#if 0 - stm32_i2c_register(1); - stm32_i2c_register(2); -#endif -} -#else -# define stm32_i2ctool() -#endif - -/**************************************************************************** - * Name: stm32_bringup - * - * Description: - * Perform architecture-specific initialization - * - * CONFIG_BOARD_LATE_INITIALIZE=y : - * Called from board_late_initialize(). - * - ****************************************************************************/ - -int stm32_bringup(void) -{ - int ret = OK; - -#ifdef CONFIG_USERLED - /* Register the LED driver */ - - ret = userled_lower_initialize("/dev/userleds"); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: userled_lower_initialize() failed: %d\n", ret); - } -#endif - -#if defined(CONFIG_I2C) && defined(CONFIG_SYSTEM_I2CTOOL) - stm32_i2ctool(); -#endif - -#ifdef CONFIG_SENSORS_MAX31855 - /* Register device 0 on spi channel 1 */ - - ret = board_max31855_initialize(0, 1); - if (ret < 0) - { - serr("ERROR: stm32_max31855initialize failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_SENSORS_MAX6675 - ret = board_max6675_initialize(0, 1); - if (ret < 0) - { - serr("ERROR: stm32_max6675initialize failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_I2C_EE_24XX - ret = stm32_at24_init("/dev/eeprom"); - if (ret < 0) - { - syslog(LOG_ERR, "Failed to initialize EEPROM HX24LCXXB: %d\n", ret); - return ret; - } -#endif - -#ifdef CONFIG_LM75_I2C - /* Configure and initialize the LM75 sensor */ - - ret = board_lm75_initialize(0, 1); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: board_lm75_initialize() failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_INPUT_BUTTONS - /* Register the BUTTON driver */ - - ret = btn_lower_initialize("/dev/buttons"); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: btn_lower_initialize() failed: %d\n", ret); - } -#endif - -#if defined(CONFIG_ADC) && defined(CONFIG_STM32_ADC1) - /* Initialize ADC and register the ADC driver. */ - - ret = stm32_adc_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_adc_setup failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_PWM - /* Initialize PWM and register the PWM device */ - - ret = stm32_pwm_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_pwm_setup() failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_LCD_MAX7219 - /* Configure and initialize the MAX7219 driver */ - - ret = board_max7219_matrix_initialize(1); - if (ret < 0) - { - syslog(LOG_ERR, \ - "ERROR: board_max7219_matrix_initialize failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_VIDEO_FB - /* Initialize and register the framebuffer driver */ - - ret = fb_register(0, 0); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: fb_register() failed: %d\n", ret); - } -#endif - -#ifdef HAVE_SDIO - /* Initialize the SDIO block driver */ - - ret = stm32_sdio_initialize(); - if (ret != OK) - { - syslog(LOG_ERR, "ERROR: Failed to initialize MMC/SD driver: %d\n", - ret); - return ret; - } -#endif - -#ifdef CONFIG_SENSORS_QENCODER - /* Initialize and register the qencoder driver */ - - ret = board_qencoder_initialize(0, STM32F401RCRS485_QETIMER); - if (ret != OK) - { - syslog(LOG_ERR, - "ERROR: Failed to register the qencoder: %d\n", - ret); - return ret; - } -#endif - -#if defined(CONFIG_RNDIS) && !defined(CONFIG_RNDIS_COMPOSITE) - uint8_t mac[6]; - mac[0] = 0xa0; /* TODO */ - mac[1] = (CONFIG_NETINIT_MACADDR_2 >> (8 * 0)) & 0xff; - mac[2] = (CONFIG_NETINIT_MACADDR_1 >> (8 * 3)) & 0xff; - mac[3] = (CONFIG_NETINIT_MACADDR_1 >> (8 * 2)) & 0xff; - mac[4] = (CONFIG_NETINIT_MACADDR_1 >> (8 * 1)) & 0xff; - mac[5] = (CONFIG_NETINIT_MACADDR_1 >> (8 * 0)) & 0xff; - usbdev_rndis_initialize(mac); -#endif - -#ifdef CONFIG_SENSORS_HCSR04 - /* Configure and initialize the HC-SR04 distance sensor */ - - ret = board_hcsr04_initialize(0); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: board_hcsr04_initialize() failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_STEPPER_DRV8825 - /* Configure and initialize the drv8825 driver */ - - ret = board_drv8825_initialize(0); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: board_drv8825_initialize failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_CL_MFRC522 - ret = stm32_mfrc522initialize("/dev/rfid0"); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_mfrc522initialize() failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_SENSORS_BMP280 - /* Initialize the BMP280 pressure sensor. */ - - ret = board_bmp280_initialize(0, 1); - if (ret < 0) - { - syslog(LOG_ERR, "Failed to initialize BMP280, error %d\n", ret); - return ret; - } -#endif - -#ifdef CONFIG_LCD_BACKPACK - /* slcd:0, i2c:1, rows=2, cols=16 */ - - ret = board_lcd_backpack_init(0, 1, 2, 16); - if (ret < 0) - { - syslog(LOG_ERR, "Failed to initialize PCF8574 LCD, error %d\n", ret); - return ret; - } -#endif - -#if defined(CONFIG_WS2812) && defined(CONFIG_WS2812_LED_COUNT) - /* Configure and initialize the WS2812 LEDs. */ - - ret = board_ws2812_initialize(0, WS2812_SPI, CONFIG_WS2812_LED_COUNT); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: board_ws2812_initialize() failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_DEV_GPIO - /* Initialize GPIO driver */ - - ret = stm32_gpio_initialize(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_gpio_initialize() failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_SENSORS_BMP180 - /* Initialize the BMP180 pressure sensor. */ - - ret = board_bmp180_initialize(0, 1); - if (ret < 0) - { - syslog(LOG_ERR, "Failed to initialize BMP180, error %d\n", ret); - return ret; - } -#endif - -#ifdef CONFIG_ADC_HX711 - ret = stm32_hx711_initialize(); - if (ret != OK) - { - aerr("ERROR: Failed to initialize hx711: %d\n", ret); - } -#endif - - return ret; -} diff --git a/boards/arm/stm32/stm32f401rc-rs485/src/stm32_buttons.c b/boards/arm/stm32/stm32f401rc-rs485/src/stm32_buttons.c deleted file mode 100644 index f8ac4d7ec25f1..0000000000000 --- a/boards/arm/stm32/stm32f401rc-rs485/src/stm32_buttons.c +++ /dev/null @@ -1,151 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f401rc-rs485/src/stm32_buttons.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include -#include - -#include "stm32.h" -#include "stm32f401rc-rs485.h" - -#ifdef CONFIG_ARCH_BUTTONS - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* Pin configuration for each STM32F401RC RS485 button. This array is indexed - * by the BUTTON_* definitions in board.h - */ - -static const uint32_t g_buttons[NUM_BUTTONS] = -{ - GPIO_BTN_SW3, GPIO_BTN_SW4, GPIO_BTN_SW5 -}; - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_button_initialize - * - * Description: - * board_button_initialize() must be called to initialize button resources. - * After that, board_buttons() may be called to collect the current state - * of all buttons or board_button_irq() may be called to register button - * interrupt handlers. - * - ****************************************************************************/ - -uint32_t board_button_initialize(void) -{ - int i; - - /* Configure the GPIO pins as inputs. NOTE that EXTI interrupts are - * configured for all pins. - */ - - for (i = 0; i < NUM_BUTTONS; i++) - { - stm32_configgpio(g_buttons[i]); - } - - return NUM_BUTTONS; -} - -/**************************************************************************** - * Name: board_buttons - ****************************************************************************/ - -uint32_t board_buttons(void) -{ - uint32_t ret = 0; - int i; - - /* Check that state of each key */ - - for (i = 0; i < NUM_BUTTONS; i++) - { - /* A LOW value means that the key is pressed. */ - - bool released = stm32_gpioread(g_buttons[i]); - - /* Accumulate the set of depressed (not released) keys */ - - if (!released) - { - ret |= (1 << i); - } - } - - return ret; -} - -/**************************************************************************** - * Button support. - * - * Description: - * board_button_initialize() must be called to initialize button resources. - * After that, board_buttons() may be called to collect the current state - * of all buttons or board_button_irq() may be called to register button - * interrupt handlers. - * - * After board_button_initialize() has been called, board_buttons() may be - * called to collect the state of all buttons. board_buttons() returns an - * 32-bit bit set with each bit associated with a button. See the - * BUTTON_*_BIT definitions in board.h for the meaning of each bit. - * - * board_button_irq() may be called to register an interrupt handler that - * will be called when a button is depressed or released. The ID value is a - * button enumeration value that uniquely identifies a button resource. See - * the BUTTON_* definitions in board.h for the meaning of enumeration - * value. - * - ****************************************************************************/ - -#ifdef CONFIG_ARCH_IRQBUTTONS -int board_button_irq(int id, xcpt_t irqhandler, void *arg) -{ - int ret = -EINVAL; - - /* The following should be atomic */ - - if (id >= MIN_IRQBUTTON && id <= MAX_IRQBUTTON) - { - ret = stm32_gpiosetevent(g_buttons[id], true, true, true, - irqhandler, arg); - } - - return ret; -} -#endif -#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/stm32/stm32f401rc-rs485/src/stm32_gpio.c b/boards/arm/stm32/stm32f401rc-rs485/src/stm32_gpio.c deleted file mode 100644 index fddefc25ae830..0000000000000 --- a/boards/arm/stm32/stm32f401rc-rs485/src/stm32_gpio.c +++ /dev/null @@ -1,343 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f401rc-rs485/src/stm32_gpio.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include -#include - -#include - -#include "chip.h" -#include "stm32.h" -#include "stm32f401rc-rs485.h" - -#if defined(CONFIG_DEV_GPIO) && !defined(CONFIG_GPIO_LOWER_HALF) - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -struct stm32gpio_dev_s -{ - struct gpio_dev_s gpio; - uint8_t id; -}; - -struct stm32gpint_dev_s -{ - struct stm32gpio_dev_s stm32gpio; - pin_interrupt_t callback; -}; - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -#if BOARD_NGPIOIN > 0 -static int gpin_read(struct gpio_dev_s *dev, bool *value); -#endif -#if BOARD_NGPIOOUT > 0 -static int gpout_read(struct gpio_dev_s *dev, bool *value); -static int gpout_write(struct gpio_dev_s *dev, bool value); -#endif -#if BOARD_NGPIOINT > 0 -static int gpint_read(struct gpio_dev_s *dev, bool *value); -static int gpint_attach(struct gpio_dev_s *dev, - pin_interrupt_t callback); -static int gpint_enable(struct gpio_dev_s *dev, bool enable); -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -#if BOARD_NGPIOIN > 0 -static const struct gpio_operations_s gpin_ops = -{ - .go_read = gpin_read, - .go_write = NULL, - .go_attach = NULL, - .go_enable = NULL, -}; -#endif - -#if BOARD_NGPIOOUT > 0 -static const struct gpio_operations_s gpout_ops = -{ - .go_read = gpout_read, - .go_write = gpout_write, - .go_attach = NULL, - .go_enable = NULL, -}; -#endif - -#if BOARD_NGPIOINT > 0 -static const struct gpio_operations_s gpint_ops = -{ - .go_read = gpint_read, - .go_write = NULL, - .go_attach = gpint_attach, - .go_enable = gpint_enable, -}; -#endif - -#if BOARD_NGPIOIN > 0 -/* This array maps the GPIO pins used as INPUT */ - -static const uint32_t g_gpioinputs[BOARD_NGPIOIN] = -{ - GPIO_IN1, -}; - -static struct stm32gpio_dev_s g_gpin[BOARD_NGPIOIN]; -#endif - -#if BOARD_NGPIOOUT -/* This array maps the GPIO pins used as OUTPUT */ - -static const uint32_t g_gpiooutputs[BOARD_NGPIOOUT] = -{ - GPIO_OUT1, -}; - -static struct stm32gpio_dev_s g_gpout[BOARD_NGPIOOUT]; -#endif - -#if BOARD_NGPIOINT > 0 -/* This array maps the GPIO pins used as INTERRUPT INPUTS */ - -static const uint32_t g_gpiointinputs[BOARD_NGPIOINT] = -{ - GPIO_INT1, -}; - -static struct stm32gpint_dev_s g_gpint[BOARD_NGPIOINT]; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -#if BOARD_NGPIOINT > 0 -static int stm32gpio_interrupt(int irq, void *context, void *arg) -{ - struct stm32gpint_dev_s *stm32gpint = - (struct stm32gpint_dev_s *)arg; - - DEBUGASSERT(stm32gpint != NULL && stm32gpint->callback != NULL); - gpioinfo("Interrupt! callback=%p\n", stm32gpint->callback); - - stm32gpint->callback(&stm32gpint->stm32gpio.gpio, - stm32gpint->stm32gpio.id); - return OK; -} -#endif - -#if BOARD_NGPIOIN > 0 -static int gpin_read(struct gpio_dev_s *dev, bool *value) -{ - struct stm32gpio_dev_s *stm32gpio = - (struct stm32gpio_dev_s *)dev; - - DEBUGASSERT(stm32gpio != NULL && value != NULL); - DEBUGASSERT(stm32gpio->id < BOARD_NGPIOIN); - gpioinfo("Reading...\n"); - - *value = stm32_gpioread(g_gpioinputs[stm32gpio->id]); - return OK; -} -#endif - -#if BOARD_NGPIOOUT > 0 -static int gpout_read(struct gpio_dev_s *dev, bool *value) -{ - struct stm32gpio_dev_s *stm32gpio = - (struct stm32gpio_dev_s *)dev; - - DEBUGASSERT(stm32gpio != NULL && value != NULL); - DEBUGASSERT(stm32gpio->id < BOARD_NGPIOOUT); - gpioinfo("Reading...\n"); - - *value = stm32_gpioread(g_gpiooutputs[stm32gpio->id]); - return OK; -} - -static int gpout_write(struct gpio_dev_s *dev, bool value) -{ - struct stm32gpio_dev_s *stm32gpio = - (struct stm32gpio_dev_s *)dev; - - DEBUGASSERT(stm32gpio != NULL); - DEBUGASSERT(stm32gpio->id < BOARD_NGPIOOUT); - gpioinfo("Writing %d\n", (int)value); - - stm32_gpiowrite(g_gpiooutputs[stm32gpio->id], value); - return OK; -} -#endif - -#if BOARD_NGPIOINT > 0 -static int gpint_read(struct gpio_dev_s *dev, bool *value) -{ - struct stm32gpint_dev_s *stm32gpint = - (struct stm32gpint_dev_s *)dev; - - DEBUGASSERT(stm32gpint != NULL && value != NULL); - DEBUGASSERT(stm32gpint->stm32gpio.id < BOARD_NGPIOINT); - gpioinfo("Reading int pin...\n"); - - *value = stm32_gpioread(g_gpiointinputs[stm32gpint->stm32gpio.id]); - return OK; -} - -static int gpint_attach(struct gpio_dev_s *dev, - pin_interrupt_t callback) -{ - struct stm32gpint_dev_s *stm32gpint = - (struct stm32gpint_dev_s *)dev; - - gpioinfo("Attaching the callback\n"); - - /* Make sure the interrupt is disabled */ - - stm32_gpiosetevent(g_gpiointinputs[stm32gpint->stm32gpio.id], false, - false, false, NULL, NULL); - - gpioinfo("Attach %p\n", callback); - stm32gpint->callback = callback; - return OK; -} - -static int gpint_enable(struct gpio_dev_s *dev, bool enable) -{ - struct stm32gpint_dev_s *stm32gpint = - (struct stm32gpint_dev_s *)dev; - - if (enable) - { - if (stm32gpint->callback != NULL) - { - gpioinfo("Enabling the interrupt\n"); - - /* Configure the interrupt for rising edge */ - - stm32_gpiosetevent(g_gpiointinputs[stm32gpint->stm32gpio.id], - true, false, false, stm32gpio_interrupt, - &g_gpint[stm32gpint->stm32gpio.id]); - } - } - else - { - gpioinfo("Disable the interrupt\n"); - stm32_gpiosetevent(g_gpiointinputs[stm32gpint->stm32gpio.id], - false, false, false, NULL, NULL); - } - - return OK; -} -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_gpio_initialize - * - * Description: - * Initialize GPIO drivers for use with /apps/examples/gpio - * - ****************************************************************************/ - -int stm32_gpio_initialize(void) -{ - int i; - int pincount = 0; - -#if BOARD_NGPIOIN > 0 - for (i = 0; i < BOARD_NGPIOIN; i++) - { - /* Setup and register the GPIO pin */ - - g_gpin[i].gpio.gp_pintype = GPIO_INPUT_PIN; - g_gpin[i].gpio.gp_ops = &gpin_ops; - g_gpin[i].id = i; - gpio_pin_register(&g_gpin[i].gpio, pincount); - - /* Configure the pin that will be used as input */ - - stm32_configgpio(g_gpioinputs[i]); - - pincount++; - } -#endif - -#if BOARD_NGPIOOUT > 0 - for (i = 0; i < BOARD_NGPIOOUT; i++) - { - /* Setup and register the GPIO pin */ - - g_gpout[i].gpio.gp_pintype = GPIO_OUTPUT_PIN; - g_gpout[i].gpio.gp_ops = &gpout_ops; - g_gpout[i].id = i; - gpio_pin_register(&g_gpout[i].gpio, pincount); - - /* Configure the pin that will be used as output */ - - stm32_gpiowrite(g_gpiooutputs[i], 0); - stm32_configgpio(g_gpiooutputs[i]); - - pincount++; - } -#endif - -#if BOARD_NGPIOINT > 0 - for (i = 0; i < BOARD_NGPIOINT; i++) - { - /* Setup and register the GPIO pin */ - - g_gpint[i].stm32gpio.gpio.gp_pintype = GPIO_INTERRUPT_PIN; - g_gpint[i].stm32gpio.gpio.gp_ops = &gpint_ops; - g_gpint[i].stm32gpio.id = i; - gpio_pin_register(&g_gpint[i].stm32gpio.gpio, pincount); - - /* Configure the pin that will be used as interrupt input */ - - stm32_configgpio(g_gpiointinputs[i]); - - pincount++; - } -#endif - - return 0; -} -#endif /* CONFIG_DEV_GPIO && !CONFIG_GPIO_LOWER_HALF */ diff --git a/boards/arm/stm32/stm32f401rc-rs485/src/stm32_hx711.c b/boards/arm/stm32/stm32f401rc-rs485/src/stm32_hx711.c deleted file mode 100644 index 929558c3b1c02..0000000000000 --- a/boards/arm/stm32/stm32f401rc-rs485/src/stm32_hx711.c +++ /dev/null @@ -1,104 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f401rc-rs485/src/stm32_hx711.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include -#include -#include -#include -#include - -#include "stm32_gpio.h" -#include "stm32f401rc-rs485.h" - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -static int stm32_hx711_clock_set(unsigned char minor, int value); -static int stm32_hx711_data_read(unsigned char minor); -static int stm32_hx711_data_irq(unsigned char minor, - xcpt_t handler, void *arg); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -struct hx711_lower_s g_lower = -{ - .data_read = stm32_hx711_data_read, - .clock_set = stm32_hx711_clock_set, - .data_irq = stm32_hx711_data_irq, - .cleanup = NULL -}; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -static int stm32_hx711_clock_set(unsigned char minor, int value) -{ - UNUSED(minor); - - stm32_gpiowrite(HX711_CLK_PIN, value); - return OK; -} - -static int stm32_hx711_data_read(unsigned char minor) -{ - UNUSED(minor); - - return stm32_gpioread(HX711_DATA_PIN); -} - -static int stm32_hx711_data_irq(unsigned char minor, - xcpt_t handler, void *arg) -{ - UNUSED(minor); - - return stm32_gpiosetevent(HX711_DATA_PIN, false, true, true, handler, arg); -}; - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -int stm32_hx711_initialize(void) -{ - int ret; - - stm32_configgpio(HX711_DATA_PIN); - stm32_configgpio(HX711_CLK_PIN); - - ret = hx711_register(0, &g_lower); - if (ret != 0) - { - aerr("ERROR: Failed to register hx711 device: %d\n", ret); - return -1; - } - - return OK; -} diff --git a/boards/arm/stm32/stm32f401rc-rs485/src/stm32_lcd_ssd1306.c b/boards/arm/stm32/stm32f401rc-rs485/src/stm32_lcd_ssd1306.c deleted file mode 100644 index f4fe30a4acc60..0000000000000 --- a/boards/arm/stm32/stm32f401rc-rs485/src/stm32_lcd_ssd1306.c +++ /dev/null @@ -1,105 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f401rc-rs485/src/stm32_lcd_ssd1306.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include - -#include -#include -#include -#include -#include - -#include "stm32.h" -#include "stm32f401rc-rs485.h" - -#include "stm32_ssd1306.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#define OLED_SPI_PORT 1 /* OLED display connected to SPI1 */ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_lcd_initialize - ****************************************************************************/ - -int board_lcd_initialize(void) -{ - int ret; - - /* Initialize the RESET and DC pins */ - - stm32_configgpio(GPIO_LCD_RESET); - stm32_configgpio(GPIO_LCD_DC); - - /* Reset the OLED display */ - - stm32_gpiowrite(GPIO_LCD_RESET, 0); - up_mdelay(1); - stm32_gpiowrite(GPIO_LCD_RESET, 1); - up_mdelay(120); - - ret = board_ssd1306_initialize(OLED_SPI_PORT); - if (ret < 0) - { - lcderr("ERROR: Failed to initialize SSD1306\n"); - return ret; - } - - return OK; -} - -/**************************************************************************** - * Name: board_lcd_getdev - ****************************************************************************/ - -struct lcd_dev_s *board_lcd_getdev(int devno) -{ - return board_ssd1306_getdev(); -} - -/**************************************************************************** - * Name: board_lcd_uninitialize - ****************************************************************************/ - -void board_lcd_uninitialize(void) -{ - /* TO-FIX */ -} diff --git a/boards/arm/stm32/stm32f401rc-rs485/src/stm32_pwm.c b/boards/arm/stm32/stm32f401rc-rs485/src/stm32_pwm.c deleted file mode 100644 index 885152e7b3312..0000000000000 --- a/boards/arm/stm32/stm32f401rc-rs485/src/stm32_pwm.c +++ /dev/null @@ -1,121 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f401rc-rs485/src/stm32_pwm.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32_pwm.h" -#include "stm32f401rc-rs485.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -/* PWM - * - * The STM32F401RC-RS485 has no real on-board PWM devices, but the board can - * be configured to output a pulse train using TIM3 CH1. - * - */ - -#define HAVE_PWM 1 - -#ifndef CONFIG_PWM -# undef HAVE_PWM -#endif - -#ifndef CONFIG_STM32_TIM3 -# undef HAVE_PWM -#endif - -#ifndef CONFIG_STM32_TIM3_PWM -# undef HAVE_PWM -#endif - -#if !defined(CONFIG_STM32_TIM3_CHANNEL) || CONFIG_STM32_TIM3_CHANNEL != STM32F401RCRS485_PWMCHANNEL -# undef HAVE_PWM -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_pwm_setup - * - * Description: - * Initialize PWM and register the PWM device. - * - ****************************************************************************/ - -int stm32_pwm_setup(void) -{ -#ifdef HAVE_PWM - static bool initialized = false; - struct pwm_lowerhalf_s *pwm; - int ret; - - /* Have we already initialized? */ - - if (!initialized) - { - /* Call stm32_pwminitialize() to get an instance of the PWM interface */ - - pwm = stm32_pwminitialize(STM32F401RCRS485_PWMTIMER); - if (!pwm) - { - aerr("ERROR: Failed to get the STM32 PWM lower half\n"); - return -ENODEV; - } - - /* Register the PWM driver at "/dev/pwm0" */ - - ret = pwm_register("/dev/pwm0", pwm); - if (ret < 0) - { - aerr("ERROR: pwm_register failed: %d\n", ret); - return ret; - } - - /* Now we are initialized */ - - initialized = true; - } - - return OK; -#else - return -ENODEV; -#endif -} diff --git a/boards/arm/stm32/stm32f401rc-rs485/src/stm32_reset.c b/boards/arm/stm32/stm32f401rc-rs485/src/stm32_reset.c deleted file mode 100644 index 7f140d6ee42ae..0000000000000 --- a/boards/arm/stm32/stm32f401rc-rs485/src/stm32_reset.c +++ /dev/null @@ -1,64 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f401rc-rs485/src/stm32_reset.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#ifdef CONFIG_BOARDCTL_RESET - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_reset - * - * Description: - * Reset board. Support for this function is required by board-level - * logic if CONFIG_BOARDCTL_RESET is selected. - * - * Input Parameters: - * status - Status information provided with the reset event. This - * meaning of this status information is board-specific. If not - * used by a board, the value zero may be provided in calls to - * board_reset(). - * - * Returned Value: - * If this function returns, then it was not possible to power-off the - * board due to some constraints. The return value int this case is a - * board-specific reason for the failure to shutdown. - * - ****************************************************************************/ - -int board_reset(int status) -{ - up_systemreset(); - return 0; -} - -#endif /* CONFIG_BOARDCTL_RESET */ diff --git a/boards/arm/stm32/stm32f401rc-rs485/src/stm32_sdio.c b/boards/arm/stm32/stm32f401rc-rs485/src/stm32_sdio.c deleted file mode 100644 index e7e4de294213c..0000000000000 --- a/boards/arm/stm32/stm32f401rc-rs485/src/stm32_sdio.c +++ /dev/null @@ -1,161 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f401rc-rs485/src/stm32_sdio.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include - -#include -#include - -#include "stm32.h" -#include "stm32f401rc-rs485.h" - -#ifdef HAVE_SDIO - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -/* Card detections requires card support and a card detection GPIO */ - -#define HAVE_NCD 1 -#if !defined(HAVE_SDIO) || !defined(GPIO_SDIO_NCD) -# undef HAVE_NCD -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -static struct sdio_dev_s *g_sdio_dev; -#ifdef HAVE_NCD -static bool g_sd_inserted; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_ncd_interrupt - * - * Description: - * Card detect interrupt handler. - * - ****************************************************************************/ - -#ifdef HAVE_NCD -static int stm32_ncd_interrupt(int irq, void *context, void *arg) -{ - bool present; - - present = !stm32_gpioread(GPIO_SDIO_NCD); - if (present != g_sd_inserted) - { - sdio_mediachange(g_sdio_dev, present); - g_sd_inserted = present; - } - - return OK; -} -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_sdio_initialize - * - * Description: - * Initialize SDIO-based MMC/SD card support - * - ****************************************************************************/ - -int stm32_sdio_initialize(void) -{ - int ret; - -#ifdef HAVE_NCD - /* Configure the card detect GPIO */ - - stm32_configgpio(GPIO_SDIO_NCD); - - /* Register an interrupt handler for the card detect pin */ - - stm32_gpiosetevent(GPIO_SDIO_NCD, true, true, true, - stm32_ncd_interrupt, NULL); -#endif - - /* Mount the SDIO-based MMC/SD block driver */ - - /* First, get an instance of the SDIO interface */ - - finfo("Initializing SDIO slot %d\n", SDIO_SLOTNO); - - g_sdio_dev = sdio_initialize(SDIO_SLOTNO); - if (!g_sdio_dev) - { - ferr("ERROR: Failed to initialize SDIO slot %d\n", SDIO_SLOTNO); - return -ENODEV; - } - - /* Now bind the SDIO interface to the MMC/SD driver */ - - finfo("Bind SDIO to the MMC/SD driver, minor=%d\n", SDIO_MINOR); - - ret = mmcsd_slotinitialize(SDIO_MINOR, g_sdio_dev); - if (ret != OK) - { - ferr("ERROR: Failed to bind SDIO to the MMC/SD driver: %d\n", ret); - return ret; - } - - finfo("Successfully bound SDIO to the MMC/SD driver\n"); - -#ifdef HAVE_NCD - /* Use SD card detect pin to check if a card is g_sd_inserted */ - - g_sd_inserted = !stm32_gpioread(GPIO_SDIO_NCD); - finfo("Card detect : %d\n", g_sd_inserted); - - sdio_mediachange(g_sdio_dev, g_sd_inserted); -#else - /* Assume that the SD card is inserted. What choice do we have? */ - - sdio_mediachange(g_sdio_dev, true); -#endif - - return OK; -} - -#endif /* HAVE_SDIO */ diff --git a/boards/arm/stm32/stm32f401rc-rs485/src/stm32_spi.c b/boards/arm/stm32/stm32f401rc-rs485/src/stm32_spi.c deleted file mode 100644 index ead5b4fcfcaea..0000000000000 --- a/boards/arm/stm32/stm32f401rc-rs485/src/stm32_spi.c +++ /dev/null @@ -1,243 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f401rc-rs485/src/stm32_spi.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include - -#include -#include - -#include "arm_internal.h" -#include "chip.h" -#include "stm32.h" -#include "stm32f401rc-rs485.h" - -#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || \ - defined(CONFIG_STM32_SPI3) - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_spidev_initialize - * - * Description: - * Called to configure SPI chip select GPIO pins for the stm32f401rc-rs485 - * board. - * - ****************************************************************************/ - -void weak_function stm32_spidev_initialize(void) -{ -#if defined(CONFIG_LCD_SSD1306) || defined(CONFIG_LCD_ST7735) - stm32_configgpio(GPIO_LCD_CS); /* LCD chip select */ -#endif - -#ifdef CONFIG_LCD_MAX7219 - stm32_configgpio(STM32_LCD_CS); /* MAX7219 chip select */ -#endif - -#ifdef CONFIG_CL_MFRC522 - stm32_configgpio(GPIO_RFID_CS); /* MFRC522 chip select */ -#endif - -#if defined(CONFIG_STM32_SPI1) && defined(CONFIG_SENSORS_MAX31855) - stm32_configgpio(GPIO_MAX31855_CS); /* MAX31855 chip select */ -#endif - -#if defined(CONFIG_STM32_SPI1) && defined(CONFIG_SENSORS_MAX66755) - stm32_configgpio(GPIO_MAX6675_CS); /* MAX6675 chip select */ -#endif -} - -/**************************************************************************** - * Name: stm32_spi1/2/3select and stm32_spi1/2/3status - * - * Description: - * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status - * must be provided by board-specific logic. They are implementations of - * the select and status methods of the SPI interface defined by struct - * spi_ops_s (see include/nuttx/spi/spi.h). All other methods - * (including stm32_spibus_initialize()) are provided by common STM32 logic. - * To use this common SPI logic on your board: - * - * 1. Provide logic in stm32_boardinitialize() to configure SPI chip select - * pins. - * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() functions - * in your board-specific logic. These functions will perform chip - * selection and status operations using GPIOs in the way your board is - * configured. - * 3. Add a calls to stm32_spibus_initialize() in your low level - * application initialization logic - * 4. The handle returned by stm32_spibus_initialize() may then be used to - * bind the SPI driver to higher level logic (e.g., calling - * mmcsd_spislotinitialize(), for example, will bind the SPI driver to - * the SPI MMC/SD driver). - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_SPI1 -void stm32_spi1select(struct spi_dev_s *dev, - uint32_t devid, bool selected) -{ - spiinfo("devid: %d CS: %s\n", - (int)devid, selected ? "assert" : "de-assert"); - - #if defined(CONFIG_LCD_SSD1306) || defined(CONFIG_LCD_ST7735) - if (devid == SPIDEV_DISPLAY(0)) - { - stm32_gpiowrite(GPIO_LCD_CS, !selected); - } - #endif - - #ifdef CONFIG_LCD_MAX7219 - if (devid == SPIDEV_DISPLAY(0)) - { - stm32_gpiowrite(STM32_LCD_CS, !selected); - } - #endif - - #if defined(CONFIG_CL_MFRC522) - if (devid == SPIDEV_CONTACTLESS(0)) - { - stm32_gpiowrite(GPIO_RFID_CS, !selected); - } - #endif - - #if defined(CONFIG_SENSORS_MAX31855) - if (devid == SPIDEV_TEMPERATURE(0)) - { - stm32_gpiowrite(GPIO_MAX31855_CS, !selected); - } - #endif - - #if defined(CONFIG_SENSORS_MAX6675) - if (devid == SPIDEV_TEMPERATURE(0)) - { - stm32_gpiowrite(GPIO_MAX6675_CS, !selected); - } - #endif -} - -uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) -{ - return 0; -} -#endif - -#ifdef CONFIG_STM32_SPI2 -void stm32_spi2select(struct spi_dev_s *dev, - uint32_t devid, bool selected) -{ - spiinfo("devid: %d CS: %s\n", - (int)devid, selected ? "assert" : "de-assert"); -} - -uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) -{ - return 0; -} -#endif - -#ifdef CONFIG_STM32_SPI3 -void stm32_spi3select(struct spi_dev_s *dev, - uint32_t devid, bool selected) -{ - spiinfo("devid: %d CS: %s\n", - (int)devid, selected ? "assert" : "de-assert"); -} - -uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid) -{ - return 0; -} -#endif - -/**************************************************************************** - * Name: stm32_spi1cmddata - * - * Description: - * Set or clear the SH1101A A0 or SD1306 D/C n bit to select data (true) - * or command (false). This function must be provided by platform-specific - * logic. This is an implementation of the cmddata method of the SPI - * interface defined by struct spi_ops_s (see include/nuttx/spi/spi.h). - * - * Input Parameters: - * - * spi - SPI device that controls the bus the device that requires the CMD/ - * DATA selection. - * devid - If there are multiple devices on the bus, this selects which one - * to select cmd or data. NOTE: This design restricts, for example, - * one one SPI display per SPI bus. - * cmd - true: select command; false: select data - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef CONFIG_SPI_CMDDATA -#ifdef CONFIG_STM32_SPI1 -int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) -{ -#if defined(CONFIG_LCD_SSD1306) || defined(CONFIG_LCD_ST7735) - if (devid == SPIDEV_DISPLAY(0)) - { - /* This is the Data/Command control pad which determines whether the - * data bits are data or a command. - */ - - stm32_gpiowrite(GPIO_LCD_DC, !cmd); - - return OK; - } -#endif - - return -ENODEV; -} -#endif - -#ifdef CONFIG_STM32_SPI2 -int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) -{ - return -ENODEV; -} -#endif - -#ifdef CONFIG_STM32_SPI3 -int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) -{ - return -ENODEV; -} -#endif -#endif /* CONFIG_SPI_CMDDATA */ - -#endif /* CONFIG_STM32_SPI1 || CONFIG_STM32_SPI2 */ diff --git a/boards/arm/stm32/stm32f401rc-rs485/src/stm32_usb.c b/boards/arm/stm32/stm32f401rc-rs485/src/stm32_usb.c deleted file mode 100644 index 317d1358bc63f..0000000000000 --- a/boards/arm/stm32/stm32f401rc-rs485/src/stm32_usb.c +++ /dev/null @@ -1,94 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f401rc-rs485/src/stm32_usb.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include - -#include "stm32_otgfs.h" -#include "stm32_gpio.h" -#include "stm32f401rc-rs485.h" - -#ifdef CONFIG_STM32_OTGFS - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#ifdef CONFIG_USBDEV -# define HAVE_USB 1 -#else -# warning "CONFIG_STM32_OTGFS is enabled but CONFIG_USBDEV is not" -# undef HAVE_USB -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_usb_configure - * - * Description: - * Called from stm32_boardinitialize very early in initialization to setup - * USB-related GPIO pins for the Olimex STM32 P407 board. - * - ****************************************************************************/ - -void stm32_usb_configure(void) -{ -#ifdef CONFIG_STM32_OTGFS - /* The OTG FS has an internal soft pull-up. - * No GPIO configuration is required - */ - - /* We don´t have the OTG FS VBUS sensing GPIO */ -#endif -} - -/**************************************************************************** - * Name: stm32_usbsuspend - * - * Description: - * Board logic must provide the stm32_usbsuspend logic if the USBDEV - * driver is used. This function is called whenever the USB enters or - * leaves suspend mode. - * This is an opportunity for the board logic to shutdown clocks, power, - * etc. while the USB is suspended. - * - ****************************************************************************/ - -#ifdef CONFIG_USBDEV -void stm32_usbsuspend(struct usbdev_s *dev, bool resume) -{ - uinfo("resume: %d\n", resume); -} -#endif - -#endif /* CONFIG_STM32_OTGFS */ diff --git a/boards/arm/stm32/stm32f401rc-rs485/src/stm32_usbmsc.c b/boards/arm/stm32/stm32f401rc-rs485/src/stm32_usbmsc.c deleted file mode 100644 index d5d633d8996be..0000000000000 --- a/boards/arm/stm32/stm32f401rc-rs485/src/stm32_usbmsc.c +++ /dev/null @@ -1,71 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f401rc-rs485/src/stm32_usbmsc.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include - -#include "stm32.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -#ifndef CONFIG_SYSTEM_USBMSC_DEVMINOR1 -# define CONFIG_SYSTEM_USBMSC_DEVMINOR1 0 -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_usbmsc_initialize - * - * Description: - * Perform architecture specific initialization of the USB MSC device. - * - ****************************************************************************/ - -int board_usbmsc_initialize(int port) -{ - /* If system/usbmsc is built as an NSH command, then SD slot should - * already have been initialized. - * In this case, there is nothing further to be done here. - */ - -#ifndef CONFIG_NSH_BUILTIN_APPS - return stm32_mmcsd_initialize(port, CONFIG_SYSTEM_USBMSC_DEVMINOR1); -#else - return OK; -#endif -} diff --git a/boards/arm/stm32/stm32f401rc-rs485/src/stm32_userleds.c b/boards/arm/stm32/stm32f401rc-rs485/src/stm32_userleds.c deleted file mode 100644 index b0b46ca4075e0..0000000000000 --- a/boards/arm/stm32/stm32f401rc-rs485/src/stm32_userleds.c +++ /dev/null @@ -1,216 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f401rc-rs485/src/stm32_userleds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32.h" -#include "stm32f401rc-rs485.h" - -#ifndef CONFIG_ARCH_LEDS - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* This array maps an LED number to GPIO pin configuration */ - -static uint32_t g_ledcfg[BOARD_NLEDS] = -{ - GPIO_LED1, GPIO_LED2, GPIO_LED3, GPIO_LED4 -}; - -/**************************************************************************** - * Private Function Protototypes - ****************************************************************************/ - -/* LED Power Management */ - -#ifdef CONFIG_PM -static void led_pm_notify(struct pm_callback_s *cb, int domain, - enum pm_state_e pmstate); -static int led_pm_prepare(struct pm_callback_s *cb, int domain, - enum pm_state_e pmstate); -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -#ifdef CONFIG_PM -static struct pm_callback_s g_ledscb = -{ - .notify = led_pm_notify, - .prepare = led_pm_prepare, -}; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: led_pm_notify - * - * Description: - * Notify the driver of new power state. This callback is called after - * all drivers have had the opportunity to prepare for the new power state. - * - ****************************************************************************/ - -#ifdef CONFIG_PM -static void led_pm_notify(struct pm_callback_s *cb, int domain, - enum pm_state_e pmstate) -{ - switch (pmstate) - { - case PM_NORMAL: - { - /* Restore normal LEDs operation */ - } - break; - - case PM_IDLE: - { - /* Entering IDLE mode - Turn leds off */ - } - break; - - case PM_STANDBY: - { - /* Entering STANDBY mode - Logic for PM_STANDBY goes here */ - } - break; - - case PM_SLEEP: - { - /* Entering SLEEP mode - Logic for PM_SLEEP goes here */ - } - break; - - default: - { - /* Should not get here */ - } - break; - } -} -#endif - -/**************************************************************************** - * Name: led_pm_prepare - * - * Description: - * Request the driver to prepare for a new power state. This is a warning - * that the system is about to enter into a new power state. The driver - * should begin whatever operations that may be required to enter power - * state. The driver may abort the state change mode by returning a - * non-zero value from the callback function. - * - ****************************************************************************/ - -#ifdef CONFIG_PM -static int led_pm_prepare(struct pm_callback_s *cb, int domain, - enum pm_state_e pmstate) -{ - /* No preparation to change power modes is required by the LEDs driver. - * We always accept the state change by returning OK. - */ - - return OK; -} -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_userled_initialize - ****************************************************************************/ - -uint32_t board_userled_initialize(void) -{ - /* Configure LED1-4 GPIOs for output */ - - stm32_configgpio(GPIO_LED1); - stm32_configgpio(GPIO_LED2); - stm32_configgpio(GPIO_LED3); - stm32_configgpio(GPIO_LED4); - return BOARD_NLEDS; -} - -/**************************************************************************** - * Name: board_userled - ****************************************************************************/ - -void board_userled(int led, bool ledon) -{ - if ((unsigned)led < BOARD_NLEDS) - { - stm32_gpiowrite(g_ledcfg[led], ledon); - } -} - -/**************************************************************************** - * Name: board_userled_all - ****************************************************************************/ - -void board_userled_all(uint32_t ledset) -{ - stm32_gpiowrite(GPIO_LED1, (ledset & BOARD_LED1_BIT) != 0); - stm32_gpiowrite(GPIO_LED2, (ledset & BOARD_LED2_BIT) != 0); - stm32_gpiowrite(GPIO_LED3, (ledset & BOARD_LED3_BIT) != 0); - stm32_gpiowrite(GPIO_LED4, (ledset & BOARD_LED4_BIT) != 0); -} - -/**************************************************************************** - * Name: stm32_led_pminitialize - ****************************************************************************/ - -#ifdef CONFIG_PM -void stm32_led_pminitialize(void) -{ - /* Register to receive power management callbacks */ - - int ret = pm_register(&g_ledscb); - if (ret != OK) - { - board_autoled_on(LED_ASSERTION); - } -} -#endif /* CONFIG_PM */ - -#endif /* !CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/stm32f411-minimum/CMakeLists.txt b/boards/arm/stm32/stm32f411-minimum/CMakeLists.txt deleted file mode 100644 index cc4e51625293c..0000000000000 --- a/boards/arm/stm32/stm32f411-minimum/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/stm32f411-minimum/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32/stm32f411-minimum/Kconfig b/boards/arm/stm32/stm32f411-minimum/Kconfig deleted file mode 100644 index 43f2f0018b8a8..0000000000000 --- a/boards/arm/stm32/stm32f411-minimum/Kconfig +++ /dev/null @@ -1,86 +0,0 @@ -# -# For a description of the syntax of this configuration file, -# see the file kconfig-language.txt in the NuttX tools repository. -# - -if ARCH_BOARD_STM32F411_MINIMUM - -config STM32F411MINIMUM_USBHOST_STACKSIZE - int "USB host waiter stack size" - default 1024 - depends on USBHOST - -config STM32F411MINIMUM_USBHOST_PRIO - int "USB host waiter task priority" - default 100 - depends on USBHOST - -config STM32F411MINIMUM_FLASH - bool "MTD driver for external 8Mbyte W25Q64FV FLASH on SPI1" - default n - select MTD - select MTD_W25 - select MTD_SMART - select FS_SMARTFS - select STM32_SPI1 - select MTD_BYTE_WRITE - ---help--- - Configures an MTD device for use with the onboard flash - -config STM32F411MINIMUM_FLASH_MINOR - int "Minor number for the FLASH /dev/smart entry" - default 0 - depends on STM32F411MINIMUM_FLASH - ---help--- - Sets the minor number for the FLASH MTD /dev entry - -menuconfig STM32F411MINIMUM_HX711 - bool "Enable hx711 scale sensor" - default n - select ADC_HX711 - -if STM32F411MINIMUM_HX711 - -choice - prompt "Select GPIO port for clock pin" - default STM32F411MINIMUM_HX711_CLK_PORTA - -config STM32F411MINIMUM_HX711_CLK_PORTA - bool "Port A" -config STM32F411MINIMUM_HX711_CLK_PORTB - bool "Port B" - -endchoice # Select GPIO port for clock pin - -config STM32F411MINIMUM_HX711_CLK_PIN - int "Select GPIO pin number for clock pin" - default 1 - range 0 15 - -choice - prompt "Select GPIO port for data pin" - default STM32F411MINIMUM_HX711_DATA_PORTA - -config STM32F411MINIMUM_HX711_DATA_PORTA - bool "Port A" -config STM32F411MINIMUM_HX711_DATA_PORTB - bool "Port B" - -endchoice # Select GPIO port for data pin - -config STM32F411MINIMUM_HX711_DATA_PIN - int "Select GPIO pin number for data pin" - default 2 - range 0 15 - -endif # STM32F411MINIMUM_HX711 - -menuconfig STM32F411MINIMUM_GPIO - select DEV_GPIO - bool "enable gpio subsystem" - -if STM32F411MINIMUM_GPIO -source "boards/arm/stm32/stm32f411-minimum/Kconfig.gpio" -endif - -endif diff --git a/boards/arm/stm32/stm32f411-minimum/configs/composite/defconfig b/boards/arm/stm32/stm32f411-minimum/configs/composite/defconfig deleted file mode 100644 index 3b481dfd674d8..0000000000000 --- a/boards/arm/stm32/stm32f411-minimum/configs/composite/defconfig +++ /dev/null @@ -1,66 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_DISABLE_OS_API is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -# CONFIG_NSH_DISABLE_IFCONFIG is not set -# CONFIG_NSH_DISABLE_PS is not set -# CONFIG_STM32_SYSCFG is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f411-minimum" -CONFIG_ARCH_BOARD_STM32F411_MINIMUM=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F411CE=y -CONFIG_ARCH_INTERRUPTSTACK=2048 -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=8499 -CONFIG_BUILTIN=y -CONFIG_CDCACM=y -CONFIG_CDCACM_COMPOSITE=y -CONFIG_COMPOSITE_IAD=y -CONFIG_COMPOSITE_PRODUCTID=0x2022 -CONFIG_COMPOSITE_VENDORID=0x03eb -CONFIG_HAVE_CXX=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_DISABLE_LOSMART=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_OTG_ID_GPIO_DISABLE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=131072 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=2 -CONFIG_START_MONTH=4 -CONFIG_START_YEAR=2023 -CONFIG_STM32F411MINIMUM_FLASH=y -CONFIG_STM32_FLASH_CONFIG_E=y -CONFIG_STM32_FLASH_PREFETCH=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_OTGFS=y -CONFIG_STM32_USART1=y -CONFIG_SYSTEM_CDCACM=y -CONFIG_SYSTEM_COMPOSITE=y -CONFIG_SYSTEM_NSH=y -CONFIG_SYSTEM_USBMSC=y -CONFIG_SYSTEM_USBMSC_DEVMINOR1=0 -CONFIG_SYSTEM_USBMSC_DEVPATH1="/dev/smart0" -CONFIG_TASK_NAME_SIZE=15 -CONFIG_USART1_SERIAL_CONSOLE=y -CONFIG_USBDEV=y -CONFIG_USBDEV_BUSPOWERED=y -CONFIG_USBDEV_COMPOSITE=y -CONFIG_USBMSC=y -CONFIG_USBMSC_COMPOSITE=y diff --git a/boards/arm/stm32/stm32f411-minimum/configs/nsh/defconfig b/boards/arm/stm32/stm32f411-minimum/configs/nsh/defconfig deleted file mode 100644 index 371cea88bf7a2..0000000000000 --- a/boards/arm/stm32/stm32f411-minimum/configs/nsh/defconfig +++ /dev/null @@ -1,46 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_DISABLE_OS_API is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -# CONFIG_NSH_DISABLE_IFCONFIG is not set -# CONFIG_NSH_DISABLE_PS is not set -# CONFIG_STM32_SYSCFG is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f411-minimum" -CONFIG_ARCH_BOARD_STM32F411_MINIMUM=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F411CE=y -CONFIG_ARCH_INTERRUPTSTACK=2048 -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=8499 -CONFIG_BUILTIN=y -CONFIG_HAVE_CXX=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=131072 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=6 -CONFIG_START_MONTH=6 -CONFIG_START_YEAR=2020 -CONFIG_STM32_FLASH_CONFIG_E=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_USART1=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/stm32f411-minimum/configs/pwm/defconfig b/boards/arm/stm32/stm32f411-minimum/configs/pwm/defconfig deleted file mode 100644 index 3f60dea548167..0000000000000 --- a/boards/arm/stm32/stm32f411-minimum/configs/pwm/defconfig +++ /dev/null @@ -1,52 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_DISABLE_OS_API is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -# CONFIG_NSH_DISABLE_IFCONFIG is not set -# CONFIG_NSH_DISABLE_PS is not set -# CONFIG_STM32_SYSCFG is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f411-minimum" -CONFIG_ARCH_BOARD_STM32F411_MINIMUM=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F411CE=y -CONFIG_ARCH_INTERRUPTSTACK=2048 -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=8499 -CONFIG_BUILTIN=y -CONFIG_EXAMPLES_PWM=y -CONFIG_HAVE_CXX=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_PWM=y -CONFIG_RAM_SIZE=131072 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=6 -CONFIG_START_MONTH=6 -CONFIG_START_YEAR=2020 -CONFIG_STM32_FLASH_CONFIG_E=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_TIM3=y -CONFIG_STM32_TIM3_CH3OUT=y -CONFIG_STM32_TIM3_CHANNEL=3 -CONFIG_STM32_TIM3_PWM=y -CONFIG_STM32_USART1=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/stm32f411-minimum/configs/rgbled/defconfig b/boards/arm/stm32/stm32f411-minimum/configs/rgbled/defconfig deleted file mode 100644 index c5ebec8a82b82..0000000000000 --- a/boards/arm/stm32/stm32f411-minimum/configs/rgbled/defconfig +++ /dev/null @@ -1,69 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_DISABLE_OS_API is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -# CONFIG_NSH_DISABLE_IFCONFIG is not set -# CONFIG_NSH_DISABLE_PS is not set -# CONFIG_STM32_SYSCFG is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f411-minimum" -CONFIG_ARCH_BOARD_STM32F411_MINIMUM=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F411CE=y -CONFIG_ARCH_INTERRUPTSTACK=2048 -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=8499 -CONFIG_BUILTIN=y -CONFIG_EXAMPLES_RGBLED=y -CONFIG_HAVE_CXX=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_PWM=y -CONFIG_PWM_NCHANNELS=3 -CONFIG_RAM_SIZE=131072 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RGBLED=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=6 -CONFIG_START_MONTH=6 -CONFIG_START_YEAR=2020 -CONFIG_STM32_FLASH_CONFIG_E=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_TIM1=y -CONFIG_STM32_TIM1_CH1OUT=y -CONFIG_STM32_TIM1_CHMODE=0 -CONFIG_STM32_TIM1_PWM=y -CONFIG_STM32_TIM2=y -CONFIG_STM32_TIM2_CH2OUT=y -CONFIG_STM32_TIM2_CHANNEL=2 -CONFIG_STM32_TIM2_CHMODE=0 -CONFIG_STM32_TIM2_PWM=y -CONFIG_STM32_TIM3=y -CONFIG_STM32_TIM3_CH3OUT=y -CONFIG_STM32_TIM3_CHANNEL=3 -CONFIG_STM32_TIM3_CHMODE=0 -CONFIG_STM32_TIM3_PWM=y -CONFIG_STM32_TIM4=y -CONFIG_STM32_TIM4_CH4OUT=y -CONFIG_STM32_TIM4_CHANNEL=4 -CONFIG_STM32_TIM4_CHMODE=0 -CONFIG_STM32_TIM4_PWM=y -CONFIG_STM32_USART1=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/stm32f411-minimum/configs/spifsnsh/defconfig b/boards/arm/stm32/stm32f411-minimum/configs/spifsnsh/defconfig deleted file mode 100644 index bc6985a1d4ce1..0000000000000 --- a/boards/arm/stm32/stm32f411-minimum/configs/spifsnsh/defconfig +++ /dev/null @@ -1,49 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_DISABLE_OS_API is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -# CONFIG_NSH_DISABLE_IFCONFIG is not set -# CONFIG_NSH_DISABLE_PS is not set -# CONFIG_STM32_SYSCFG is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f411-minimum" -CONFIG_ARCH_BOARD_STM32F411_MINIMUM=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F411CE=y -CONFIG_ARCH_INTERRUPTSTACK=2048 -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=8499 -CONFIG_BUILTIN=y -CONFIG_HAVE_CXX=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_DISABLE_LOSMART=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=131072 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=2 -CONFIG_START_MONTH=4 -CONFIG_START_YEAR=2023 -CONFIG_STM32F411MINIMUM_FLASH=y -CONFIG_STM32_FLASH_CONFIG_E=y -CONFIG_STM32_FLASH_PREFETCH=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_USART1=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=15 -CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/stm32f411-minimum/configs/usbmsc/defconfig b/boards/arm/stm32/stm32f411-minimum/configs/usbmsc/defconfig deleted file mode 100644 index 1d49a8275be78..0000000000000 --- a/boards/arm/stm32/stm32f411-minimum/configs/usbmsc/defconfig +++ /dev/null @@ -1,57 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_DISABLE_OS_API is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -# CONFIG_NSH_DISABLE_IFCONFIG is not set -# CONFIG_NSH_DISABLE_PS is not set -# CONFIG_STM32_SYSCFG is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f411-minimum" -CONFIG_ARCH_BOARD_STM32F411_MINIMUM=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F411CE=y -CONFIG_ARCH_INTERRUPTSTACK=2048 -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=8499 -CONFIG_BUILTIN=y -CONFIG_HAVE_CXX=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_DISABLE_LOSMART=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_OTG_ID_GPIO_DISABLE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=131072 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=2 -CONFIG_START_MONTH=4 -CONFIG_START_YEAR=2023 -CONFIG_STM32F411MINIMUM_FLASH=y -CONFIG_STM32_FLASH_CONFIG_E=y -CONFIG_STM32_FLASH_PREFETCH=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_OTGFS=y -CONFIG_STM32_USART1=y -CONFIG_SYSTEM_NSH=y -CONFIG_SYSTEM_USBMSC=y -CONFIG_SYSTEM_USBMSC_DEVMINOR1=0 -CONFIG_SYSTEM_USBMSC_DEVPATH1="/dev/smart0" -CONFIG_TASK_NAME_SIZE=15 -CONFIG_USART1_SERIAL_CONSOLE=y -CONFIG_USBDEV=y -CONFIG_USBDEV_BUSPOWERED=y -CONFIG_USBMSC=y diff --git a/boards/arm/stm32/stm32f411-minimum/include/board.h b/boards/arm/stm32/stm32f411-minimum/include/board.h deleted file mode 100644 index 5d353b961ca77..0000000000000 --- a/boards/arm/stm32/stm32f411-minimum/include/board.h +++ /dev/null @@ -1,363 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f411-minimum/include/board.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __BOARDS_ARM_STM32_STM32F411_MINIMUM_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32_STM32F411_MINIMUM_INCLUDE_BOARD_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#ifndef __ASSEMBLY__ -# include -#endif - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Clocking *****************************************************************/ - -/* System Clock source : PLLCLK (HSE) - * SYSCLK(Hz) : 96000000 Determined by PLL config - * HCLK(Hz) : 96000000 (STM32_RCC_CFGR_HPRE) - * AHB Prescaler : 1 (STM32_RCC_CFGR_HPRE) - * APB1 Prescaler : 4 (STM32_RCC_CFGR_PPRE1) - * APB2 Prescaler : 2 (STM32_RCC_CFGR_PPRE2) - * HSI Frequency(Hz) : 16000000 (nominal) - * PLLM : 4 (STM32_PLLCFG_PLLM) - * PLLN : 192 (STM32_PLLCFG_PLLN) - * PLLP : 4 (STM32_PLLCFG_PLLP) - * PLLQ : 8 (STM32_PLLCFG_PPQ) - * Flash Latency(WS) : 3 - * Prefetch Buffer : OFF - * Instruction cache : ON - * Data cache : ON - * Require 48MHz for USB OTG FS, : Enabled - * SDIO and RNG clock - */ - -/* HSI - 16 MHz RC factory-trimmed - * LSI - 32 KHz RC - * HSE - 25 MHz Crystal - * LSE - 32 KHz Crystal - */ - -#define STM32_BOARD_XTAL 25000000ul - -#define STM32_HSI_FREQUENCY 16000000ul -#define STM32_LSI_FREQUENCY 32000 -#define STM32_LSE_FREQUENCY 32768 -#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL - -/* Main PLL Configuration. - * - * Formulae: - * - * VCO input freq = PLL input clock freq/PLLM 2 <= PLLM <= 63 - * VCO output freq = VCO input freq × PLLN, 192 <= PLLN <= 432 - * PLL output clock freq = VCO freq / PLLP, PLLP = 2,4,6 or 8 - * USB OTG FS clock freq = VCO freq / PLLQ, 2 <= PLLQ <= 15 - * - * There is no config for 100 MHz and 48 MHz for usb, - * so we would like to have SYSYCLK=96MHz and we must have the USB - * clock = 48MHz - * - * PLLQ = 2 PLLP = 2 PLLN=192 PLLM=25 - * - * We will configure like this - * - * PLL source is HSE - * PLL_VCO = (STM32_HSE_FREQUENCY / PLLM) * PLLN - * = (25,000,000 / 25) * 192 - * = 192,000,000 - * SYSCLK = PLL_VCO / PLLP - * = 192,000,000 / 2 = 96,000,000 - * USB OTG FS and SDIO Clock - * = PLL_VCO / PLLQ - * = 96,000,000 / 2 = 48,000,000 - */ - -#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(25) -#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(192) -#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_2 -#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(2) - -#define STM32_SYSCLK_FREQUENCY 96000000ul - -/* AHB clock (HCLK) is SYSCLK (96MHz) */ - -#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ -#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY - -/* APB1 clock (PCLK1) is HCLK/4 (24MHz) */ - -#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd4 /* PCLK1 = HCLK / 4 */ -#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/4) - -/* Timers driven from APB1 will be twice PCLK1 */ - -/* REVISIT */ - -#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) - -/* APB2 clock (PCLK2) is HCLK (48MHz) */ - -#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLKd2 /* PCLK2 = HCLK / 2 */ -#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/2) - -/* Timers driven from APB2 will be twice PCLK2 */ - -#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM9_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB2_TIM10_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB2_TIM11_CLKIN (2*STM32_PCLK1_FREQUENCY) - -/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx - * otherwise frequency is 2xAPBx. - * Note: TIM1,8 are on APB2, others on APB1 - */ - -/* REVISIT */ - -#define BOARD_TIM1_FREQUENCY (2 * STM32_PCLK2_FREQUENCY) -#define BOARD_TIM2_FREQUENCY (2 * STM32_PCLK1_FREQUENCY) -#define BOARD_TIM3_FREQUENCY (2 * STM32_PCLK1_FREQUENCY) -#define BOARD_TIM4_FREQUENCY (2 * STM32_PCLK1_FREQUENCY) -#define BOARD_TIM5_FREQUENCY (2 * STM32_PCLK1_FREQUENCY) -#define BOARD_TIM6_FREQUENCY (2 * STM32_PCLK1_FREQUENCY) -#define BOARD_TIM7_FREQUENCY (2 * STM32_PCLK1_FREQUENCY) -#define BOARD_TIM8_FREQUENCY (2 * STM32_PCLK2_FREQUENCY) - -/* SDIO dividers. Note that slower clocking is required when DMA is disabled - * in order to avoid RX overrun/TX underrun errors due to delayed responses - * to service FIFOs in interrupt driven mode. These values have not been - * tuned!!! - * - * HCLK=72MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(178+2)=400 KHz - */ - -/* REVISIT */ - -#define SDIO_INIT_CLKDIV (178 << SDIO_CLKCR_CLKDIV_SHIFT) - -/* DMA ON: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(2+2)=18 MHz - * DMA OFF: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(3+2)=14.4 MHz - */ - -/* REVISIT */ - -#ifdef CONFIG_SDIO_DMA -# define SDIO_MMCXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT) -#else -# define SDIO_MMCXFR_CLKDIV (3 << SDIO_CLKCR_CLKDIV_SHIFT) -#endif - -/* DMA ON: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(1+2)=24 MHz - * DMA OFF: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(3+2)=14.4 MHz - */ - -/* REVISIT */ - -#ifdef CONFIG_SDIO_DMA -# define SDIO_SDXFR_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT) -#else -# define SDIO_SDXFR_CLKDIV (3 << SDIO_CLKCR_CLKDIV_SHIFT) -#endif - -/* DMA Channel/Stream Selections ********************************************/ - -/* Stream selections are arbitrary for now but might become important in the - * future is we set aside more DMA channels/streams. - * - * SDIO DMA - *   DMAMAP_SDIO_1 = Channel 4, Stream 3 <- may later be used by SPI DMA - *   DMAMAP_SDIO_2 = Channel 4, Stream 6 - */ - -#define DMAMAP_SDIO DMAMAP_SDIO_1 - -/* Need to VERIFY fwb */ - -#define DMACHAN_SPI1_RX DMAMAP_SPI1_RX_1 -#define DMACHAN_SPI1_TX DMAMAP_SPI1_TX_1 -#define DMACHAN_SPI2_RX DMAMAP_SPI2_RX -#define DMACHAN_SPI2_TX DMAMAP_SPI2_TX - -/* Alternate function pin selections ****************************************/ - -/* USART1: - * RXD: PA10 CN9 pin 3, CN10 pin 33 - * PB7 CN7 pin 21 - * TXD: PA9 CN5 pin 1, CN10 pin 21 - * PB6 CN5 pin 3, CN10 pin 17 - */ - -#if 1 -# define GPIO_USART1_RX (GPIO_USART1_RX_1|GPIO_SPEED_100MHz) /* PA10 */ -# define GPIO_USART1_TX (GPIO_USART1_TX_1|GPIO_SPEED_100MHz) /* PA9 */ -#else -# define GPIO_USART1_RX (GPIO_USART1_RX_2|GPIO_SPEED_100MHz) /* PB7 */ -# define GPIO_USART1_TX (GPIO_USART1_TX_2|GPIO_SPEED_100MHz) /* PB6 */ -#endif - -/* USART2: - * RXD: PA3 CN9 pin 1 (See SB13, 14, 62, 63). CN10 pin 37 - * PD6 - * TXD: PA2 CN9 pin 2(See SB13, 14, 62, 63). CN10 pin 35 - * PD5 - */ - -#define GPIO_USART2_RX (GPIO_USART2_RX_1|GPIO_SPEED_100MHz) /* PA3 */ -#define GPIO_USART2_TX (GPIO_USART2_TX_1|GPIO_SPEED_100MHz) /* PA2 */ -#define GPIO_USART2_RTS GPIO_USART2_RTS_2 -#define GPIO_USART2_CTS GPIO_USART2_CTS_2 - -/* USART6: - * RXD: PC7 CN5 pin2, CN10 pin 19 - * PA12 CN10, pin 12 - * TXD: PC6 CN10, pin 4 - * PA11 CN10, pin 14 - */ - -#define GPIO_USART6_RX (GPIO_USART6_RX_1|GPIO_SPEED_100MHz) /* PC7 */ -#define GPIO_USART6_TX (GPIO_USART6_TX_1|GPIO_SPEED_100MHz) /* PC6 */ - -/* PWM - * - * The STM32F4 Discovery has no real on-board PWM devices, but the board - * can be configured to output a pulse train using TIM4 CH2 on PD13. - */ -#define GPIO_TIM1_CH1OUT (GPIO_TIM1_CH1OUT_1|GPIO_SPEED_50MHz) //PA8 -#define GPIO_TIM2_CH2OUT (GPIO_TIM2_CH2OUT_1|GPIO_SPEED_50MHz) //PA1 -#define GPIO_TIM3_CH3OUT (GPIO_TIM3_CH3OUT_1|GPIO_SPEED_50MHz) //PB0 -#define GPIO_TIM4_CH4OUT (GPIO_TIM4_CH4OUT_1|GPIO_SPEED_50MHz) //PB9 - -/* RGB LED - * - * R = TIM1 CH1 on PA8 | G = TIM2 CH2 on PA1 | B = TIM4 CH4 on PB9 - * - * Note: Pin boards: GPIO_TIM1_CH1OUT ; GPIO_TIM2_CH2OUT ; GPIO_TIM4_CH4OUT - */ - -#define RGBLED_RPWMTIMER 1 -#define RGBLED_RPWMCHANNEL 1 -#define RGBLED_GPWMTIMER 2 -#define RGBLED_GPWMCHANNEL 2 -#define RGBLED_BPWMTIMER 4 -#define RGBLED_BPWMCHANNEL 4 - -/* UART RX DMA configurations */ - -#define DMAMAP_USART1_RX DMAMAP_USART1_RX_2 -#define DMAMAP_USART6_RX DMAMAP_USART6_RX_2 - -/* I2C - * - * The optional _GPIO configurations allow the I2C driver to manually - * reset the bus to clear stuck slaves. They match the pin configuration, - * but are normally-high GPIOs. - */ - -#define GPIO_I2C1_SCL (GPIO_I2C1_SCL_2|GPIO_SPEED_50MHz) -#define GPIO_I2C1_SDA (GPIO_I2C1_SDA_2|GPIO_SPEED_50MHz) -#define GPIO_I2C1_SCL_GPIO \ - (GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTB|GPIO_PIN8) -#define GPIO_I2C1_SDA_GPIO \ - (GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTB|GPIO_PIN9) - -#define GPIO_I2C2_SCL (GPIO_I2C2_SCL_1|GPIO_SPEED_50MHz) -#define GPIO_I2C2_SDA (GPIO_I2C2_SDA_1|GPIO_SPEED_50MHz) -#define GPIO_I2C2_SCL_GPIO \ - (GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTB|GPIO_PIN10) -#define GPIO_I2C2_SDA_GPIO \ - (GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTB|GPIO_PIN11) - -/* SPI - * - * There are sensors on SPI1, and SPI2 is connected to the FRAM. - */ - -#define GPIO_SPI1_MISO (GPIO_SPI1_MISO_1|GPIO_SPEED_50MHz) -#define GPIO_SPI1_MOSI (GPIO_SPI1_MOSI_1|GPIO_SPEED_50MHz) -#define GPIO_SPI1_SCK (GPIO_SPI1_SCK_1|GPIO_SPEED_50MHz) - -#define GPIO_SPI2_MISO (GPIO_SPI2_MISO_1|GPIO_SPEED_50MHz) -#define GPIO_SPI2_MOSI (GPIO_SPI2_MOSI_1|GPIO_SPEED_50MHz) -#define GPIO_SPI2_SCK (GPIO_SPI2_SCK_2|GPIO_SPEED_50MHz) - -/* LEDs - * - * The STM32F411-Minimum (aka BlackPill) has a LED on PC13 pin. - */ - -/* The board has only one controllable LED */ - -#define LED_STARTED 0 /* No LEDs */ -#define LED_HEAPALLOCATE 1 /* LED1 on */ -#define LED_IRQSENABLED 2 /* LED1 on */ -#define LED_STACKCREATED 3 /* LED1 on */ -#define LED_INIRQ 4 /* LED1 on */ -#define LED_SIGNAL 5 /* LED1 on */ -#define LED_ASSERTION 6 /* LED1 on */ -#define LED_PANIC 7 /* LED1 blinking */ - -/* LED index values for use with board_userled() */ - -#define BOARD_LED1 0 -#define BOARD_NLEDS 1 - -/* LED bits for use with board_userled_all() */ - -#define BOARD_LED1_BIT (1 << BOARD_LED1) - -/* Buttons - * - * B1 USER: the user button is connected to the I/O PA0 of the STM32 - * microcontroller. - */ - -#define BUTTON_USER 0 -#define BUTTON_EXTERNAL 1 //External user button connected to PA1 -#define NUM_BUTTONS 2 - -#define BUTTON_USER_BIT (1 << BUTTON_USER) -#define BUTTON_EXTERNAL_BIT (1 << BUTTON_EXTERNAL) - -/* USB OTG FS */ - -#define GPIO_OTGFS_DM (GPIO_OTGFS_DM_0|GPIO_SPEED_100MHz) -#define GPIO_OTGFS_DP (GPIO_OTGFS_DP_0|GPIO_SPEED_100MHz) -#define GPIO_OTGFS_ID (GPIO_OTGFS_ID_0|GPIO_SPEED_100MHz) -#define GPIO_OTGFS_SOF (GPIO_OTGFS_SOF_0|GPIO_SPEED_100MHz) - -#endif /* __BOARDS_ARM_STM32_STM32F411_MINIMUM_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32/stm32f411-minimum/scripts/Make.defs b/boards/arm/stm32/stm32f411-minimum/scripts/Make.defs deleted file mode 100644 index 3a41209051dfc..0000000000000 --- a/boards/arm/stm32/stm32f411-minimum/scripts/Make.defs +++ /dev/null @@ -1,41 +0,0 @@ -############################################################################ -# boards/arm/stm32/stm32f411-minimum/scripts/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/.config -include $(TOPDIR)/tools/Config.mk -include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs - -LDSCRIPT = stm32f411ce.ld -ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) - -ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 - -CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) -CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) -CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -AFLAGS := $(CFLAGS) -D__ASSEMBLY__ - -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections -LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32/stm32f411-minimum/src/CMakeLists.txt b/boards/arm/stm32/stm32f411-minimum/src/CMakeLists.txt deleted file mode 100644 index 67ae6a038bb8a..0000000000000 --- a/boards/arm/stm32/stm32f411-minimum/src/CMakeLists.txt +++ /dev/null @@ -1,76 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/stm32f411-minimum/src/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -set(SRCS stm32_boot.c stm32_bringup.c) - -if(CONFIG_ARCH_LEDS) - list(APPEND SRCS stm32_autoleds.c) -endif() - -if(CONFIG_USERLED) - list(APPEND SRCS stm32_userleds.c) -endif() - -if(CONFIG_ARCH_BUTTONS) - list(APPEND SRCS stm32_buttons.c) -endif() - -if(CONFIG_PWM) - list(APPEND SRCS stm32_pwm.c) -endif() - -if(CONFIG_RGBLED) - list(APPEND SRCS stm32_rgbled.c) -endif() - -if(CONFIG_SPI) - list(APPEND SRCS stm32_spi.c) -endif() - -if(CONFIG_MTD_W25) - list(APPEND SRCS stm32_w25.c) -endif() - -if(CONFIG_STM32_OTGFS) - list(APPEND SRCS stm32_usb.c) -endif() - -if(CONFIG_USBDEV_COMPOSITE) - list(APPEND SRCS stm32_composite.c) -endif() - -if(CONFIG_STM32F411MINIMUM_GPIO) - list(APPEND SRCS stm32_gpio.c) -endif() - -if(CONFIG_USBMSC) - list(APPEND SRCS stm32_usbmsc.c) -endif() - -if(CONFIG_ADC_HX711) - list(APPEND SRCS stm32_hx711.c) -endif() - -target_sources(board PRIVATE ${SRCS}) - -set_property(GLOBAL PROPERTY LD_SCRIPT - "${NUTTX_BOARD_DIR}/scripts/stm32f411ce.ld") diff --git a/boards/arm/stm32/stm32f411-minimum/src/Make.defs b/boards/arm/stm32/stm32f411-minimum/src/Make.defs deleted file mode 100644 index a221a572f16d4..0000000000000 --- a/boards/arm/stm32/stm32f411-minimum/src/Make.defs +++ /dev/null @@ -1,77 +0,0 @@ -############################################################################ -# boards/arm/stm32/stm32f411-minimum/src/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/Make.defs - -CSRCS = stm32_boot.c stm32_bringup.c - -ifeq ($(CONFIG_ARCH_LEDS),y) - CSRCS += stm32_autoleds.c -endif - -ifeq ($(CONFIG_USERLED),y) - CSRCS += stm32_userleds.c -endif - -ifeq ($(CONFIG_ARCH_BUTTONS),y) - CSRCS += stm32_buttons.c -endif - -ifeq ($(CONFIG_PWM),y) - CSRCS += stm32_pwm.c -endif - -ifeq ($(CONFIG_RGBLED),y) - CSRCS += stm32_rgbled.c -endif - -ifeq ($(CONFIG_ADC_HX711),y) - CSRCS += stm32_hx711.c -endif - -ifeq ($(CONFIG_SPI),y) - CSRCS += stm32_spi.c -endif - -ifeq ($(CONFIG_STM32F411MINIMUM_GPIO),y) - CSRCS += stm32_gpio.c -endif - -ifeq ($(CONFIG_MTD_W25),y) - CSRCS += stm32_w25.c -endif - -ifeq ($(CONFIG_STM32_OTGFS),y) - CSRCS += stm32_usb.c -endif - -ifeq ($(CONFIG_USBDEV_COMPOSITE),y) - CSRCS += stm32_composite.c -endif - -ifeq ($(CONFIG_USBMSC),y) -CSRCS += stm32_usbmsc.c -endif - -DEPPATH += --dep-path board -VPATH += :board -CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/stm32f411-minimum/src/stm32_autoleds.c b/boards/arm/stm32/stm32f411-minimum/src/stm32_autoleds.c deleted file mode 100644 index 9846714e8d892..0000000000000 --- a/boards/arm/stm32/stm32f411-minimum/src/stm32_autoleds.c +++ /dev/null @@ -1,112 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f411-minimum/src/stm32_autoleds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32.h" -#include "stm32f411-minimum.h" - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -static inline void set_led(bool v) -{ - ledinfo("Turn LED %s\n", v? "on":"off"); - stm32_gpiowrite(GPIO_LED1, !v); -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_autoled_initialize - ****************************************************************************/ - -#ifdef CONFIG_ARCH_LEDS -void board_autoled_initialize(void) -{ - /* Configure LED GPIO for output */ - - stm32_configgpio(GPIO_LED1); -} - -/**************************************************************************** - * Name: board_autoled_on - ****************************************************************************/ - -void board_autoled_on(int led) -{ - ledinfo("board_autoled_on(%d)\n", led); - - switch (led) - { - case LED_STARTED: - case LED_HEAPALLOCATE: - /* As the board provides only one soft controllable LED, we simply - * turn it on when the board boots. - */ - - set_led(true); - break; - - case LED_PANIC: - - /* For panic state, the LED is blinking */ - - set_led(true); - break; - } -} - -/**************************************************************************** - * Name: board_autoled_off - ****************************************************************************/ - -void board_autoled_off(int led) -{ - switch (led) - { - case LED_PANIC: - - /* For panic state, the LED is blinking */ - - set_led(false); - break; - } -} - -#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/stm32f411-minimum/src/stm32_boot.c b/boards/arm/stm32/stm32f411-minimum/src/stm32_boot.c deleted file mode 100644 index c37c11bf046ca..0000000000000 --- a/boards/arm/stm32/stm32f411-minimum/src/stm32_boot.c +++ /dev/null @@ -1,101 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f411-minimum/src/stm32_boot.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include -#include - -#include - -#include "arm_internal.h" -#include "stm32f411-minimum.h" - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_boardinitialize - * - * Description: - * All STM32 architectures must provide the following entry point. This - * entry point is called early in the initialization -- after all memory - * has been configured and mapped but before any devices have been - * initialized. - * - ****************************************************************************/ - -void stm32_boardinitialize(void) -{ -#ifdef CONFIG_ARCH_LEDS - /* Configure on-board LEDs if LED support has been selected. */ - - board_autoled_initialize(); -#endif - -#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || \ - defined(CONFIG_STM32_SPI3) - /* Configure SPI chip selects if 1) SP2 is not disabled, and 2) the - * weak function stm32_spidev_initialize() has been brought into the link. - */ - - stm32_spidev_initialize(); -#endif - -#ifdef CONFIG_STM32_OTGFS - /* Initialize USB if the OTG FS controller is in the configuration. - * Presumably either CONFIG_USBDEV or CONFIG_USBHOST is also selected. - */ - - stm32_usbinitialize(); -#endif -} - -/**************************************************************************** - * Name: board_late_initialize - * - * Description: - * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional - * initialization call will be performed in the boot-up sequence to a - * function called board_late_initialize(). board_late_initialize() will - * be called immediately after up_initialize() is called and just before - * the initial application is started. This additional initialization - * phase may be used, for example, to initialize board-specific device - * drivers. - * - ****************************************************************************/ - -#ifdef CONFIG_BOARD_LATE_INITIALIZE -void board_late_initialize(void) -{ - /* Perform board-specific initialization */ - - stm32_bringup(); -} -#endif diff --git a/boards/arm/stm32/stm32f411-minimum/src/stm32_bringup.c b/boards/arm/stm32/stm32f411-minimum/src/stm32_bringup.c deleted file mode 100644 index e81aad31989ab..0000000000000 --- a/boards/arm/stm32/stm32f411-minimum/src/stm32_bringup.c +++ /dev/null @@ -1,187 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f411-minimum/src/stm32_bringup.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include - -#include "stm32.h" - -#ifdef CONFIG_USERLED -# include -#endif - -#ifdef CONFIG_INPUT_BUTTONS -# include -#endif - -#ifdef CONFIG_STM32_OTGFS -# include "stm32_usbhost.h" -#endif - -#include "stm32f411-minimum.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Checking needed by W25 Flash */ - -#define HAVE_W25 1 - -/* Can't support the W25 device if it SPI1 or W25 support is not enabled */ - -#if !defined(CONFIG_STM32_SPI1) || !defined(CONFIG_MTD_W25) -# undef HAVE_W25 -#endif - -/* Can't support W25 features if mountpoints are disabled */ - -#ifdef CONFIG_DISABLE_MOUNTPOINT -# undef HAVE_W25 -#endif - -/* Default W25 minor number */ - -#if defined(HAVE_W25) && !defined(CONFIG_NSH_W25MINOR) -# define CONFIG_NSH_W25MINOR 0 -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_bringup - * - * Description: - * Perform architecture-specific initialization - * - * CONFIG_BOARD_LATE_INITIALIZE=y : - * Called from board_late_initialize(). - * - ****************************************************************************/ - -int stm32_bringup(void) -{ - int ret = OK; - -#ifdef CONFIG_USERLED - /* Register the LED driver */ - - ret = userled_lower_initialize("/dev/userleds"); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: userled_lower_initialize() failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_INPUT_BUTTONS - /* Register the BUTTON driver */ - - ret = btn_lower_initialize("/dev/buttons"); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: btn_lower_initialize() failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_PWM - /* Initialize PWM and register the PWM device. */ - - ret = stm32_pwm_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_pwm_setup() failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_RGBLED - /* Configure and initialize the RGB LED. */ - - ret = stm32_rgbled_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_rgbled_setup() failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO - ret = stm32_gpio_initialize(); - if (ret != OK) - { - gerr("ERROR: Failed to initialize gpio: %d\n", ret); - } -#endif - -#ifdef CONFIG_ADC_HX711 - ret = stm32_hx711_initialize(); - if (ret != OK) - { - aerr("ERROR: Failed to initialize hx711: %d\n", ret); - } -#endif - -#if defined(CONFIG_STM32_OTGFS) && defined(CONFIG_USBHOST) - /* Initialize USB host operation. stm32_usbhost_initialize() starts a - * thread will monitor for USB connection and disconnection events. - */ - - ret = stm32_usbhost_initialize(); - if (ret != OK) - { - uerr("ERROR: Failed to initialize USB host: %d\n", ret); - return ret; - } -#endif - -#ifdef HAVE_W25 - /* Initialize and register the W25 FLASH file system. */ - - ret = stm32_w25initialize(CONFIG_NSH_W25MINOR); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: Failed to initialize W25 minor %d: %d\n", - CONFIG_NSH_W25MINOR, ret); - return ret; - } -#endif - -#ifdef CONFIG_FS_PROCFS - /* Mount the procfs file system */ - - ret = nx_mount(NULL, STM32_PROCFS_MOUNTPOINT, "procfs", 0, NULL); - if (ret < 0) - { - ferr("ERROR: Failed to mount procfs at %s: %d\n", - STM32_PROCFS_MOUNTPOINT, ret); - } -#endif - - return ret; -} diff --git a/boards/arm/stm32/stm32f411-minimum/src/stm32_buttons.c b/boards/arm/stm32/stm32f411-minimum/src/stm32_buttons.c deleted file mode 100644 index ff1867283277c..0000000000000 --- a/boards/arm/stm32/stm32f411-minimum/src/stm32_buttons.c +++ /dev/null @@ -1,160 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f411-minimum/src/stm32_buttons.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include -#include - -#include "stm32_gpio.h" -#include "stm32f411-minimum.h" - -#if defined(CONFIG_ARCH_BUTTONS) - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#if defined(CONFIG_INPUT_BUTTONS) && !defined(CONFIG_ARCH_IRQBUTTONS) -# error "The NuttX Buttons Driver depends on IRQ support to work!\n" -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/* Pin configuration for each STM32F3Discovery button. This array is indexed - * by the BUTTON_* definitions in board.h - */ - -static const uint32_t g_buttons[NUM_BUTTONS] = -{ - GPIO_BTN_USER, GPIO_BTN_EXTERNAL -}; - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_button_initialize - * - * Description: - * board_button_initialize() must be called to initialize button resources. - * After that, board_buttons() may be called to collect the current state - * of all buttons or board_button_irq() may be called to register button - * interrupt handlers. - * - ****************************************************************************/ - -uint32_t board_button_initialize(void) -{ - int i; - - /* Configure the GPIO pins as inputs. NOTE that EXTI interrupts are - * configured for all pins. - */ - - for (i = 0; i < NUM_BUTTONS; i++) - { - stm32_configgpio(g_buttons[i]); - } - - return NUM_BUTTONS; -} - -/**************************************************************************** - * Name: board_buttons - ****************************************************************************/ - -uint32_t board_buttons(void) -{ - uint32_t ret = 0; - int i; - - /* Check that state of each key */ - - for (i = 0; i < NUM_BUTTONS; i++) - { - /* A LOW value means that the key is pressed. */ - - bool released = stm32_gpioread(g_buttons[i]); - - /* Accumulate the set of depressed (not released) keys */ - - if (!released) - { - ret |= (1 << i); - } - } - - return ret; -} - -/**************************************************************************** - * Button support. - * - * Description: - * board_button_initialize() must be called to initialize button resources. - * After that, board_buttons() may be called to collect the current state - * of all buttons or board_button_irq() may be called to register button - * interrupt handlers. - * - * After board_button_initialize() has been called, board_buttons() may be - * called to collect the state of all buttons. board_buttons() returns - * an 32-bit bit set with each bit associated with a button. See the - * BUTTON_*_BIT definitions in board.h for the meaning of each bit. - * - * board_button_irq() may be called to register an interrupt handler that - * will be called when a button is depressed or released. The ID value is - * a button enumeration value that uniquely identifies a button resource. - * See the BUTTON_* definitions in board.h for the meaning of enumeration - * value. - * - ****************************************************************************/ - -#ifdef CONFIG_ARCH_IRQBUTTONS -int board_button_irq(int id, xcpt_t irqhandler, void *arg) -{ - int ret = -EINVAL; - - /* The following should be atomic */ - - if (id >= MIN_IRQBUTTON && id <= MAX_IRQBUTTON) - { - ret = stm32_gpiosetevent(g_buttons[id], true, true, true, irqhandler, - arg); - } - - return ret; -} -#endif - -#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/stm32/stm32f411-minimum/src/stm32_composite.c b/boards/arm/stm32/stm32f411-minimum/src/stm32_composite.c deleted file mode 100644 index 78bd6f5a5b8cd..0000000000000 --- a/boards/arm/stm32/stm32f411-minimum/src/stm32_composite.c +++ /dev/null @@ -1,278 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f411-minimum/src/stm32_composite.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include -#include -#include - -#include -#include -#include -#include - -#if defined(CONFIG_BOARDCTL_USBDEVCTRL) && defined(CONFIG_USBDEV_COMPOSITE) - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -#ifdef CONFIG_USBMSC_COMPOSITE -static void *g_mschandle; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_mscclassobject - * - * Description: - * If the mass storage class driver is part of composite device, then - * its instantiation and configuration is a multi-step, board-specific, - * process (See comments for usbmsc_configure below). In this case, - * board-specific logic must provide board_mscclassobject(). - * - * board_mscclassobject() is called from the composite driver. It must - * encapsulate the instantiation and configuration of the mass storage - * class and the return the mass storage device's class driver instance - * to the composite driver. - * - * Input Parameters: - * classdev - The location to return the mass storage class' device - * instance. - * - * Returned Value: - * 0 on success; a negated errno on failure - * - ****************************************************************************/ - -#ifdef CONFIG_USBMSC_COMPOSITE -static int board_mscclassobject(int minor, - struct usbdev_devinfo_s *devinfo, - struct usbdevclass_driver_s **classdev) -{ - int ret; - - DEBUGASSERT(g_mschandle == NULL); - - /* Configure the mass storage device */ - - uinfo("Configuring with NLUNS=1\n"); - ret = usbmsc_configure(1, &g_mschandle); - if (ret < 0) - { - uerr("ERROR: usbmsc_configure failed: %d\n", -ret); - return ret; - } - - uinfo("MSC handle=%p\n", g_mschandle); - - /* Bind the LUN(s) */ - - uinfo("Bind LUN=0 to /dev/smart0\n"); - ret = usbmsc_bindlun(g_mschandle, "/dev/smart0", 0, 0, 0, false); - if (ret < 0) - { - uerr("ERROR: usbmsc_bindlun failed for LUN 1 at /dev/smart0: %d\n", - ret); - usbmsc_uninitialize(g_mschandle); - g_mschandle = NULL; - return ret; - } - - /* Get the mass storage device's class object */ - - ret = usbmsc_classobject(g_mschandle, devinfo, classdev); - if (ret < 0) - { - uerr("ERROR: usbmsc_classobject failed: %d\n", -ret); - usbmsc_uninitialize(g_mschandle); - g_mschandle = NULL; - } - - return ret; -} -#endif - -/**************************************************************************** - * Name: board_mscuninitialize - * - * Description: - * Un-initialize the USB storage class driver. - * This is just an application specific wrapper for usbmsc_unitialize() - * that is called form the composite device logic. - * - * Input Parameters: - * classdev - The class driver instance previously given to the composite - * driver by board_mscclassobject(). - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef CONFIG_USBMSC_COMPOSITE -static void board_mscuninitialize(struct usbdevclass_driver_s *classdev) -{ - if (g_mschandle) - { - usbmsc_uninitialize(g_mschandle); - } - - g_mschandle = NULL; -} -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_composite_initialize - * - * Description: - * Perform architecture specific initialization of a composite USB device. - * - ****************************************************************************/ - -int board_composite_initialize(int port) -{ - return OK; -} - -/**************************************************************************** - * Name: board_composite_connect - * - * Description: - * Connect the USB composite device on the specified USB device port using - * the specified configuration. The interpretation of the configid is - * board specific. - * - * Input Parameters: - * port - The USB device port. - * configid - The USB composite configuration - * - * Returned Value: - * A non-NULL handle value is returned on success. NULL is returned on - * any failure. - * - ****************************************************************************/ - -void *board_composite_connect(int port, int configid) -{ - /* Here we are composing the configuration of the usb composite device. - * - * The standard is to use one CDC/ACM and one USB mass storage device. - */ - - if (configid == 0) - { - struct composite_devdesc_s dev[2]; - int ifnobase = 0; - int strbase = COMPOSITE_NSTRIDS; - int dev_idx = 0; - -#ifdef CONFIG_USBMSC_COMPOSITE - /* Configure the mass storage device device */ - - /* Ask the usbmsc driver to fill in the constants we didn't - * know here. - */ - - usbmsc_get_composite_devdesc(&dev[dev_idx]); - - /* Overwrite and correct some values... */ - - /* The callback functions for the USBMSC class */ - - dev[dev_idx].classobject = board_mscclassobject; - dev[dev_idx].uninitialize = board_mscuninitialize; - - /* Interfaces */ - - dev[dev_idx].devinfo.ifnobase = ifnobase; /* Offset to Interface-IDs */ - dev[dev_idx].minor = 0; /* The minor interface number */ - - /* Strings */ - - dev[dev_idx].devinfo.strbase = strbase; /* Offset to String Numbers */ - - /* Endpoints */ - - dev[dev_idx].devinfo.epno[USBMSC_EP_BULKIN_IDX] = 3; - dev[dev_idx].devinfo.epno[USBMSC_EP_BULKOUT_IDX] = 3; - - /* Count up the base numbers */ - - ifnobase += dev[dev_idx].devinfo.ninterfaces; - strbase += dev[dev_idx].devinfo.nstrings; - dev_idx++; -#endif - -#ifdef CONFIG_CDCACM_COMPOSITE - /* Configure the CDC/ACM device */ - - /* Ask the cdcacm driver to fill in the constants we didn't - * know here. - */ - - cdcacm_get_composite_devdesc(&dev[dev_idx]); - - /* Overwrite and correct some values... */ - - /* The callback functions for the CDC/ACM class */ - - dev[dev_idx].classobject = cdcacm_classobject; - dev[dev_idx].uninitialize = cdcacm_uninitialize; - - /* Interfaces */ - - dev[dev_idx].devinfo.ifnobase = ifnobase; /* Offset to Interface-IDs */ - dev[dev_idx].minor = 0; /* The minor interface number */ - - /* Strings */ - - dev[dev_idx].devinfo.strbase = strbase; /* Offset to String Numbers */ - - /* Endpoints */ - - dev[dev_idx].devinfo.epno[CDCACM_EP_INTIN_IDX] = 1; - dev[dev_idx].devinfo.epno[CDCACM_EP_BULKIN_IDX] = 2; - dev[dev_idx].devinfo.epno[CDCACM_EP_BULKOUT_IDX] = 2; - dev_idx++; -#endif - - return composite_initialize(composite_getdevdescs(), dev, dev_idx); - } - else - { - return NULL; - } -} - -#endif /* CONFIG_BOARDCTL_USBDEVCTRL && CONFIG_USBDEV_COMPOSITE */ diff --git a/boards/arm/stm32/stm32f411-minimum/src/stm32_gpio.c b/boards/arm/stm32/stm32f411-minimum/src/stm32_gpio.c deleted file mode 100644 index 754e624d61a77..0000000000000 --- a/boards/arm/stm32/stm32f411-minimum/src/stm32_gpio.c +++ /dev/null @@ -1,741 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f411-minimum/src/stm32_gpio.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include -#include - -#include - -#include "chip.h" -#include "stm32.h" -#include "stm32f411-minimum.h" - -#if defined(CONFIG_DEV_GPIO) && !defined(CONFIG_GPIO_LOWER_HALF) - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -struct stm32gpio_dev_s -{ - struct gpio_dev_s gpio; - uint8_t id; -}; - -struct stm32gpint_dev_s -{ - struct stm32gpio_dev_s stm32gpio; - pin_interrupt_t callback; -}; - -struct stm32gpio_info_s -{ - uint32_t pin; - const char *pinname; /* Holds pin name like gpio_a0, gpio_custom_name */ -}; - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -#if BOARD_NGPIO_IN > 0 -static int gpin_read(struct gpio_dev_s *dev, bool *value); -#endif - -#if BOARD_NGPIO_OUT > 0 -static int gpout_read(struct gpio_dev_s *dev, bool *value); -static int gpout_write(struct gpio_dev_s *dev, bool value); -#endif - -#if BOARD_NGPIO_INT > 0 -static int gpint_read(struct gpio_dev_s *dev, bool *value); -static int gpint_enable(struct gpio_dev_s *dev, bool enable); -static int gpint_attach(struct gpio_dev_s *dev, pin_interrupt_t callback); -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -#if BOARD_NGPIO_IN > 0 -static const struct gpio_operations_s gpin_ops = -{ - .go_read = gpin_read, - .go_write = NULL, - .go_attach = NULL, - .go_enable = NULL, -}; - -static struct stm32gpio_dev_s g_gpin[BOARD_NGPIO_IN]; -static const struct stm32gpio_info_s g_gpio_inputs[BOARD_NGPIO_IN] = -{ -#ifdef CONFIG_STM32F411MINIMUM_GPIO_A0_IN - { .pin = GPIO_A0_IN, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A0_NAME }, -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO_A1_IN - { .pin = GPIO_A1_IN, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A1_NAME }, -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO_A2_IN - { .pin = GPIO_A2_IN, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A2_NAME }, -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO_A3_IN - { .pin = GPIO_A3_IN, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A3_NAME }, -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO_A4_IN - { .pin = GPIO_A4_IN, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A4_NAME }, -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO_A5_IN - { .pin = GPIO_A5_IN, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A5_NAME }, -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO_A6_IN - { .pin = GPIO_A6_IN, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A6_NAME }, -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO_A7_IN - { .pin = GPIO_A7_IN, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A7_NAME }, -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO_A8_IN - { .pin = GPIO_A8_IN, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A8_NAME }, -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO_A9_IN - { .pin = GPIO_A9_IN, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A9_NAME }, -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO_A10_IN - { .pin = GPIO_A10_IN, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A10_NAME }, -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO_A11_IN - { .pin = GPIO_A11_IN, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A11_NAME }, -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO_A12_IN - { .pin = GPIO_A12_IN, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A12_NAME }, -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO_A15_IN - { .pin = GPIO_A15_IN, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A15_NAME }, -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO_B0_IN - { .pin = GPIO_B0_IN, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B0_NAME }, -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO_B1_IN - { .pin = GPIO_B1_IN, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B1_NAME }, -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO_B2_IN - { .pin = GPIO_B2_IN, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B2_NAME }, -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO_B3_IN - { .pin = GPIO_B3_IN, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B3_NAME }, -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO_B4_IN - { .pin = GPIO_B4_IN, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B4_NAME }, -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO_B5_IN - { .pin = GPIO_B5_IN, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B5_NAME }, -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO_B6_IN - { .pin = GPIO_B6_IN, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B6_NAME }, -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO_B7_IN - { .pin = GPIO_B7_IN, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B7_NAME }, -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO_B8_IN - { .pin = GPIO_B8_IN, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B8_NAME }, -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO_B9_IN - { .pin = GPIO_B9_IN, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B9_NAME }, -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO_B10_IN - { .pin = GPIO_B10_IN, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B10_NAME }, -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO_B12_IN - { .pin = GPIO_B12_IN, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B12_NAME }, -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO_B13_IN - { .pin = GPIO_B13_IN, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B13_NAME }, -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO_B14_IN - { .pin = GPIO_B14_IN, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B14_NAME }, -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO_B15_IN - { .pin = GPIO_B15_IN, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B15_NAME }, -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO_C13_IN - { .pin = GPIO_C13_IN, .pinname = CONFIG_STM32F411MINIMUM_GPIO_C13_NAME }, -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO_C14_IN - { .pin = GPIO_C14_IN, .pinname = CONFIG_STM32F411MINIMUM_GPIO_C14_NAME }, -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO_C15_IN - { .pin = GPIO_C15_IN, .pinname = CONFIG_STM32F411MINIMUM_GPIO_C15_NAME }, -#endif -}; -#endif /* BOARD_NGPIO_IN > 0 */ - -#if BOARD_NGPIO_OUT > 0 -static const struct gpio_operations_s gpout_ops = -{ - .go_read = gpout_read, - .go_write = gpout_write, - .go_attach = NULL, - .go_enable = NULL, -}; - -static struct stm32gpio_dev_s g_gpout[BOARD_NGPIO_OUT]; -static const struct stm32gpio_info_s g_gpio_outputs[BOARD_NGPIO_OUT] = -{ -#ifdef CONFIG_STM32F411MINIMUM_GPIO_A0_OUT - { .pin = GPIO_A0_OUT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A0_NAME }, -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO_A1_OUT - { .pin = GPIO_A1_OUT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A1_NAME }, -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO_A2_OUT - { .pin = GPIO_A2_OUT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A2_NAME }, -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO_A3_OUT - { .pin = GPIO_A3_OUT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A3_NAME }, -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO_A4_OUT - { .pin = GPIO_A4_OUT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A4_NAME }, -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO_A5_OUT - { .pin = GPIO_A5_OUT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A5_NAME }, -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO_A6_OUT - { .pin = GPIO_A6_OUT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A6_NAME }, -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO_A7_OUT - { .pin = GPIO_A7_OUT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A7_NAME }, -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO_A8_OUT - { .pin = GPIO_A8_OUT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A8_NAME }, -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO_A9_OUT - { .pin = GPIO_A9_OUT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A9_NAME }, -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO_A10_OUT - { .pin = GPIO_A10_OUT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A10_NAME }, -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO_A11_OUT - { .pin = GPIO_A11_OUT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A11_NAME }, -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO_A12_OUT - { .pin = GPIO_A12_OUT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A12_NAME }, -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO_A15_OUT - { .pin = GPIO_A15_OUT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A15_NAME }, -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO_B0_OUT - { .pin = GPIO_B0_OUT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B0_NAME }, -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO_B1_OUT - { .pin = GPIO_B1_OUT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B1_NAME }, -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO_B2_OUT - { .pin = GPIO_B2_OUT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B2_NAME }, -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO_B3_OUT - { .pin = GPIO_B3_OUT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B3_NAME }, -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO_B4_OUT - { .pin = GPIO_B4_OUT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B4_NAME }, -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO_B5_OUT - { .pin = GPIO_B5_OUT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B5_NAME }, -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO_B6_OUT - { .pin = GPIO_B6_OUT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B6_NAME }, -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO_B7_OUT - { .pin = GPIO_B7_OUT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B7_NAME }, -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO_B8_OUT - { .pin = GPIO_B8_OUT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B8_NAME }, -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO_B9_OUT - { .pin = GPIO_B9_OUT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B9_NAME }, -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO_B10_OUT - { .pin = GPIO_B10_OUT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B10_NAME }, -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO_B12_OUT - { .pin = GPIO_B12_OUT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B12_NAME }, -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO_B13_OUT - { .pin = GPIO_B13_OUT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B13_NAME }, -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO_B14_OUT - { .pin = GPIO_B14_OUT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B14_NAME }, -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO_B15_OUT - { .pin = GPIO_B15_OUT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B15_NAME }, -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO_C13_OUT - { .pin = GPIO_C13_OUT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_C13_NAME }, -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO_C14_OUT - { .pin = GPIO_C14_OUT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_C14_NAME }, -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO_C15_OUT - { .pin = GPIO_C15_OUT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_C15_NAME }, -#endif -}; -#endif /* BOARD_NGPIO_OUT > 0 */ - -#if BOARD_NGPIO_INT > 0 -static const struct gpio_operations_s gpint_ops = -{ - .go_read = gpint_read, - .go_write = NULL, - .go_attach = gpint_attach, - .go_enable = gpint_enable, -}; - -static struct stm32gpint_dev_s g_gpint[BOARD_NGPIO_INT]; -static const struct stm32gpio_info_s g_gpio_int_inputs[BOARD_NGPIO_INT] = -{ -#ifdef CONFIG_STM32F411MINIMUM_GPIO_A0_INT - { .pin = GPIO_A0_INT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A0_NAME }, -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO_A1_INT - { .pin = GPIO_A1_INT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A1_NAME }, -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO_A2_INT - { .pin = GPIO_A2_INT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A2_NAME }, -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO_A3_INT - { .pin = GPIO_A3_INT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A3_NAME }, -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO_A4_INT - { .pin = GPIO_A4_INT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A4_NAME }, -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO_A5_INT - { .pin = GPIO_A5_INT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A5_NAME }, -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO_A6_INT - { .pin = GPIO_A6_INT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A6_NAME }, -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO_A7_INT - { .pin = GPIO_A7_INT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A7_NAME }, -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO_A8_INT - { .pin = GPIO_A8_INT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A8_NAME }, -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO_A9_INT - { .pin = GPIO_A9_INT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A9_NAME }, -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO_A10_INT - { .pin = GPIO_A10_INT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A10_NAME }, -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO_A11_INT - { .pin = GPIO_A11_INT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A11_NAME }, -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO_A12_INT - { .pin = GPIO_A12_INT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A12_NAME }, -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO_A15_INT - { .pin = GPIO_A15_INT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A15_NAME }, -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO_B0_INT - { .pin = GPIO_B0_INT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B0_NAME }, -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO_B1_INT - { .pin = GPIO_B1_INT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B1_NAME }, -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO_B2_INT - { .pin = GPIO_B2_INT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B2_NAME }, -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO_B3_INT - { .pin = GPIO_B3_INT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B3_NAME }, -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO_B4_INT - { .pin = GPIO_B4_INT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B4_NAME }, -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO_B5_INT - { .pin = GPIO_B5_INT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B5_NAME }, -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO_B6_INT - { .pin = GPIO_B6_INT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B6_NAME }, -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO_B7_INT - { .pin = GPIO_B7_INT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B7_NAME }, -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO_B8_INT - { .pin = GPIO_B8_INT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B8_NAME }, -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO_B9_INT - { .pin = GPIO_B9_INT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B9_NAME }, -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO_B10_INT - { .pin = GPIO_B10_INT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B10_NAME }, -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO_B12_INT - { .pin = GPIO_B12_INT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B12_NAME }, -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO_B13_INT - { .pin = GPIO_B13_INT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B13_NAME }, -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO_B14_INT - { .pin = GPIO_B14_INT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B14_NAME }, -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO_B15_INT - { .pin = GPIO_B15_INT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B15_NAME }, -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO_C13_INT - { .pin = GPIO_C13_INT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_C13_NAME }, -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO_C14_INT - { .pin = GPIO_C14_INT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_C14_NAME }, -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO_C15_INT - { .pin = GPIO_C15_INT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_C15_NAME }, -#endif -}; -#endif /* BOARD_NGPIO_INT > 0 */ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: gpin_read - ****************************************************************************/ - -#if BOARD_NGPIO_IN > 0 -static int gpin_read(struct gpio_dev_s *dev, bool *value) -{ - struct stm32gpio_dev_s *stm32gpio = - (struct stm32gpio_dev_s *)dev; - - DEBUGASSERT(stm32gpio != NULL && value != NULL); - DEBUGASSERT(stm32gpio->id < BOARD_NGPIO_IN); - gpioinfo("Reading...\n"); - - *value = stm32_gpioread(g_gpio_inputs[stm32gpio->id].pin); - return OK; -} -#endif - -/**************************************************************************** - * Name: gpout_read - ****************************************************************************/ - -#if BOARD_NGPIO_OUT > 0 -static int gpout_read(struct gpio_dev_s *dev, bool *value) -{ - struct stm32gpio_dev_s *stm32gpio = - (struct stm32gpio_dev_s *)dev; - - DEBUGASSERT(stm32gpio != NULL && value != NULL); - DEBUGASSERT(stm32gpio->id < BOARD_NGPIO_OUT); - gpioinfo("Reading...\n"); - - *value = stm32_gpioread(g_gpio_outputs[stm32gpio->id].pin); - return OK; -} -#endif - -/**************************************************************************** - * Name: gpout_write - ****************************************************************************/ - -#if BOARD_NGPIO_OUT > 0 -static int gpout_write(struct gpio_dev_s *dev, bool value) -{ - struct stm32gpio_dev_s *stm32gpio = - (struct stm32gpio_dev_s *)dev; - - DEBUGASSERT(stm32gpio != NULL); - DEBUGASSERT(stm32gpio->id < BOARD_NGPIO_OUT); - gpioinfo("Writing %d\n", (int)value); - - stm32_gpiowrite(g_gpio_outputs[stm32gpio->id].pin, value); - return OK; -} -#endif - -/**************************************************************************** - * Name: gpint_read - ****************************************************************************/ - -#if BOARD_NGPIO_INT > 0 -static int gpint_read(struct gpio_dev_s *dev, bool *value) -{ - struct stm32gpint_dev_s *stm32gpint = - (struct stm32gpint_dev_s *)dev; - - DEBUGASSERT(stm32gpint != NULL && value != NULL); - DEBUGASSERT(stm32gpint->stm32gpio.id < BOARD_NGPIO_INT); - gpioinfo("Reading int pin...\n"); - - *value = stm32_gpioread(g_gpio_int_inputs[stm32gpint->stm32gpio.id].pin); - return OK; -} -#endif - -/**************************************************************************** - * Name: stm32gpio_interrupt - ****************************************************************************/ - -#if BOARD_NGPIO_INT > 0 -static int stm32gpio_interrupt(int irq, void *context, void *arg) -{ - struct stm32gpint_dev_s *stm32gpint = - (struct stm32gpint_dev_s *)arg; - - DEBUGASSERT(stm32gpint != NULL && stm32gpint->callback != NULL); - gpioinfo("Interrupt! callback=%p\n", stm32gpint->callback); - - stm32gpint->callback(&stm32gpint->stm32gpio.gpio, - stm32gpint->stm32gpio.id); - return OK; -} -#endif - -/**************************************************************************** - * Name: gpint_attach - ****************************************************************************/ - -#if BOARD_NGPIO_INT > 0 -static int gpint_attach(struct gpio_dev_s *dev, - pin_interrupt_t callback) -{ - struct stm32gpint_dev_s *stm32gpint = - (struct stm32gpint_dev_s *)dev; - - gpioinfo("Attaching the callback\n"); - - /* Make sure the interrupt is disabled */ - - stm32_gpiosetevent(g_gpio_int_inputs[stm32gpint->stm32gpio.id].pin, false, - false, false, NULL, NULL); - - gpioinfo("Attach %p\n", callback); - stm32gpint->callback = callback; - return OK; -} -#endif - -/**************************************************************************** - * Name: gpint_enable - ****************************************************************************/ - -#if BOARD_NGPIO_INT > 0 -static int gpint_enable(struct gpio_dev_s *dev, bool enable) -{ - struct stm32gpint_dev_s *stm32gpint = - (struct stm32gpint_dev_s *)dev; - - if (enable) - { - if (stm32gpint->callback != NULL) - { - gpioinfo("Enabling the interrupt\n"); - - /* Configure the interrupt for rising edge */ - - stm32_gpiosetevent(g_gpio_int_inputs[stm32gpint->stm32gpio.id].pin, - true, false, false, stm32gpio_interrupt, - &g_gpint[stm32gpint->stm32gpio.id]); - } - } - else - { - gpioinfo("Disable the interrupt\n"); - stm32_gpiosetevent(g_gpio_int_inputs[stm32gpint->stm32gpio.id].pin, - false, false, false, NULL, NULL); - } - - return OK; -} -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_gpio_initialize - * - * Description: - * Initialize GPIO drivers - * - ****************************************************************************/ - -int stm32_gpio_initialize(void) -{ - int i; - -#if BOARD_NGPIO_IN > 0 - for (i = 0; i < BOARD_NGPIO_IN; i++) - { - /* Setup and register the GPIO pin */ - - g_gpin[i].gpio.gp_pintype = GPIO_INPUT_PIN; - g_gpin[i].gpio.gp_ops = &gpin_ops; - g_gpin[i].id = i; - gpio_pin_register_byname(&g_gpin[i].gpio, g_gpio_inputs[i].pinname); - - /* Configure the pin that will be used as input */ - - stm32_configgpio(g_gpio_inputs[i].pin); - } -#endif - -#if BOARD_NGPIO_OUT > 0 - for (i = 0; i < BOARD_NGPIO_OUT; i++) - { - /* Setup and register the GPIO pin */ - - g_gpout[i].gpio.gp_pintype = GPIO_OUTPUT_PIN; - g_gpout[i].gpio.gp_ops = &gpout_ops; - g_gpout[i].id = i; - gpio_pin_register_byname(&g_gpout[i].gpio, g_gpio_outputs[i].pinname); - - /* Configure the pin that will be used as output */ - - stm32_gpiowrite(g_gpio_outputs[i].pin, 0); - stm32_configgpio(g_gpio_outputs[i].pin); - } -#endif - -#if BOARD_NGPIO_INT > 0 - for (i = 0; i < BOARD_NGPIO_INT; i++) - { - /* Setup and register the GPIO pin */ - - g_gpint[i].stm32gpio.gpio.gp_pintype = GPIO_INTERRUPT_PIN; - g_gpint[i].stm32gpio.gpio.gp_ops = &gpint_ops; - g_gpint[i].stm32gpio.id = i; - gpio_pin_register_byname(&g_gpint[i].stm32gpio.gpio, - g_gpio_int_inputs[i].pinname); - - /* Configure the pin that will be used as interrupt input */ - - stm32_configgpio(g_gpio_int_inputs[i].pin); - } -#endif - - return 0; -} -#endif /* CONFIG_DEV_GPIO && !CONFIG_GPIO_LOWER_HALF */ diff --git a/boards/arm/stm32/stm32f411-minimum/src/stm32_hx711.c b/boards/arm/stm32/stm32f411-minimum/src/stm32_hx711.c deleted file mode 100644 index ce88a74bcbf18..0000000000000 --- a/boards/arm/stm32/stm32f411-minimum/src/stm32_hx711.c +++ /dev/null @@ -1,104 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f411-minimum/src/stm32_hx711.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include -#include -#include -#include -#include - -#include "stm32_gpio.h" -#include "stm32f411-minimum.h" - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -static int stm32_hx711_clock_set(unsigned char minor, int value); -static int stm32_hx711_data_read(unsigned char minor); -static int stm32_hx711_data_irq(unsigned char minor, - xcpt_t handler, void *arg); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -struct hx711_lower_s g_lower = -{ - .data_read = stm32_hx711_data_read, - .clock_set = stm32_hx711_clock_set, - .data_irq = stm32_hx711_data_irq, - .cleanup = NULL -}; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -static int stm32_hx711_clock_set(unsigned char minor, int value) -{ - UNUSED(minor); - - stm32_gpiowrite(HX711_CLK_PIN, value); - return OK; -} - -static int stm32_hx711_data_read(unsigned char minor) -{ - UNUSED(minor); - - return stm32_gpioread(HX711_DATA_PIN); -} - -static int stm32_hx711_data_irq(unsigned char minor, - xcpt_t handler, void *arg) -{ - UNUSED(minor); - - return stm32_gpiosetevent(HX711_DATA_PIN, false, true, true, handler, arg); -}; - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -int stm32_hx711_initialize(void) -{ - int ret; - - stm32_configgpio(HX711_DATA_PIN); - stm32_configgpio(HX711_CLK_PIN); - - ret = hx711_register(0, &g_lower); - if (ret != 0) - { - aerr("ERROR: Failed to register hx711 device: %d\n", ret); - return -1; - } - - return OK; -} diff --git a/boards/arm/stm32/stm32f411-minimum/src/stm32_pwm.c b/boards/arm/stm32/stm32f411-minimum/src/stm32_pwm.c deleted file mode 100644 index 6f7354477ca86..0000000000000 --- a/boards/arm/stm32/stm32f411-minimum/src/stm32_pwm.c +++ /dev/null @@ -1,127 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f411-minimum/src/stm32_pwm.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32_pwm.h" -#include "stm32f411-minimum.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -/* PWM - * - * The stm32f411-minimum has no real on-board PWM devices, but the board can - * be configured to output a pulse train using TIM4 CH2. - * This pin is used by FSMC is connect to CN5 just for this purpose: - * - * PB0 ADC12_IN8/TIM3_CH3 - * - */ - -#define HAVE_PWM 1 - -#ifndef CONFIG_PWM -# undef HAVE_PWM -#endif - -#ifndef CONFIG_STM32_TIM3 -# undef HAVE_PWM -#endif - -#ifndef CONFIG_STM32_TIM3_PWM -# undef HAVE_PWM -#endif - -#if !defined(CONFIG_STM32_TIM3_CHANNEL) || CONFIG_STM32_TIM3_CHANNEL != STM32F411MINIMUM_PWMCHANNEL -# undef HAVE_PWM -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_pwm_setup - * - * Description: - * Initialize PWM and register the PWM device. - * - ****************************************************************************/ - -int stm32_pwm_setup(void) -{ -#ifdef HAVE_PWM - static bool initialized = false; - struct pwm_lowerhalf_s *pwm; - int ret; - - /* Have we already initialized? */ - - if (!initialized) - { - /* Call stm32_pwminitialize() to get an instance of the PWM interface */ - - pwm = stm32_pwminitialize(STM32F411MINIMUM_PWMTIMER); - if (!pwm) - { - aerr("ERROR: Failed to get the STM32 PWM lower half\n"); - return -ENODEV; - } - - /* Register the PWM driver at "/dev/pwm0" */ - - ret = pwm_register("/dev/pwm0", pwm); - if (ret < 0) - { - aerr("ERROR: pwm_register failed: %d\n", ret); - return ret; - } - - /* Now we are initialized */ - - initialized = true; - } - - return OK; -#else - return -ENODEV; -#endif -} diff --git a/boards/arm/stm32/stm32f411-minimum/src/stm32_rgbled.c b/boards/arm/stm32/stm32f411-minimum/src/stm32_rgbled.c deleted file mode 100644 index faaa9e4871b94..0000000000000 --- a/boards/arm/stm32/stm32f411-minimum/src/stm32_rgbled.c +++ /dev/null @@ -1,185 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f411-minimum/src/stm32_rgbled.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32_pwm.h" -#include "stm32f411-minimum.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -#define HAVE_RGBLED 1 - -#ifndef CONFIG_PWM -# undef HAVE_RGBLED -#endif - -#ifndef CONFIG_STM32_TIM1 -# undef HAVE_RGBLED -#endif - -#ifndef CONFIG_STM32_TIM2 -# undef HAVE_RGBLED -#endif - -#ifndef CONFIG_STM32_TIM4 -# undef HAVE_RGBLED -#endif - -#ifndef CONFIG_STM32_TIM1_PWM -# undef HAVE_RGBLED -#endif - -#ifndef CONFIG_STM32_TIM2_PWM -# undef HAVE_RGBLED -#endif - -#ifndef CONFIG_STM32_TIM4_PWM -# undef HAVE_RGBLED -#endif - -#if CONFIG_STM32_TIM1_CHANNEL != RGBLED_RPWMCHANNEL -# undef HAVE_PWM -#endif - -#if CONFIG_STM32_TIM2_CHANNEL != RGBLED_GPWMCHANNEL -# undef HAVE_PWM -#endif - -#if CONFIG_STM32_TIM4_CHANNEL != RGBLED_BPWMCHANNEL -# undef HAVE_PWM -#endif - -#ifdef HAVE_RGBLED - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_rgbled_setup - * - * Description: - * Initial for support of a connected RGB LED using PWM. - * - ****************************************************************************/ - -int stm32_rgbled_setup(void) -{ - static bool initialized = false; - struct pwm_lowerhalf_s *ledr; - struct pwm_lowerhalf_s *ledg; - struct pwm_lowerhalf_s *ledb; - struct pwm_info_s info; - int ret; - - /* Have we already initialized? */ - - if (!initialized) - { - /* Call stm32_pwminitialize() to get an instance of the PWM interface */ - - ledr = stm32_pwminitialize(RGBLED_RPWMTIMER); - if (!ledr) - { - lederr("ERROR: Failed to get the STM32 PWM lower half to LEDR\n"); - return -ENODEV; - } - - /* Define frequency and duty cycle */ - - info.frequency = 100; - info.channels[0].duty = 0; - - /* Initialize LED R */ - - ledr->ops->setup(ledr); - ledr->ops->start(ledr, &info); - - /* Call stm32_pwminitialize() to get an instance of the PWM interface */ - - ledg = stm32_pwminitialize(RGBLED_GPWMTIMER); - if (!ledg) - { - lederr("ERROR: Failed to get the STM32 PWM lower half to LEDG\n"); - return -ENODEV; - } - - /* Initialize LED G */ - - ledg->ops->setup(ledg); - ledg->ops->start(ledg, &info); - - /* Call stm32_pwminitialize() to get an instance of the PWM interface */ - - ledb = stm32_pwminitialize(RGBLED_BPWMTIMER); - if (!ledb) - { - lederr("ERROR: Failed to get the STM32 PWM lower half to LEDB\n"); - return -ENODEV; - } - - /* Initialize LED B */ - - ledb->ops->setup(ledb); - ledb->ops->start(ledb, &info); - - /* Register the RGB LED diver at "/dev/rgbled0" */ - - ret = rgbled_register("/dev/rgbled0", ledr, ledg, ledb, - RGBLED_RPWMCHANNEL, RGBLED_GPWMCHANNEL, - RGBLED_BPWMCHANNEL); - if (ret < 0) - { - lederr("ERROR: rgbled_register failed: %d\n", ret); - return ret; - } - - /* Now we are initialized */ - - initialized = true; - } - - return OK; -} - -#else -# error "HAVE_RGBLED is undefined" -#endif /* HAVE_RGBLED */ diff --git a/boards/arm/stm32/stm32f411-minimum/src/stm32_spi.c b/boards/arm/stm32/stm32f411-minimum/src/stm32_spi.c deleted file mode 100644 index 890f8cc3db280..0000000000000 --- a/boards/arm/stm32/stm32f411-minimum/src/stm32_spi.c +++ /dev/null @@ -1,175 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f411-minimum/src/stm32_spi.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include "arm_internal.h" -#include "chip.h" -#include "stm32.h" -#include "stm32f411-minimum.h" - -#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_spidev_initialize - * - * Description: - * Called to configure SPI chip select GPIO pins - * for the WeAct Studio MiniF4 board. - * - ****************************************************************************/ - -void stm32_spidev_initialize(void) -{ - /* NOTE: Clocking for SPI1 and/or SPI2 was already provided in stm32_rcc.c. - * Configurations of SPI pins is performed in stm32_spi.c. - * Here, we only initialize chip select pins unique to the board - * architecture. - */ - -#ifdef CONFIG_MTD_W25 - stm32_configgpio(FLASH_SPI1_CS); /* FLASH chip select */ -#endif - -#ifdef CONFIG_MMCSD_SPI - stm32_configgpio(GPIO_SDCARD_CS); /* SD/MMC Card chip select */ -#endif -} - -/**************************************************************************** - * Name: stm32_spi1/2select and stm32_spi1/2status - * - * Description: - * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status - * must be provided by board-specific logic. They are implementations of - * the select and status methods of the SPI interface defined by struct - * spi_ops_s (see include/nuttx/spi/spi.h). All other methods (including - * stm32_spibus_initialize()) are provided by common STM32 logic. - * To use this common SPI logic on your board: - * - * 1. Provide logic in stm32_boardinitialize() to configure SPI chip select - * pins. - * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() functions - * in your board-specific logic. These functions will perform chip - * selection and status operations using GPIOs in the way your board is - * configured. - * 3. Add a calls to stm32_spibus_initialize() in your low level - * application initialization logic - * 4. The handle returned by stm32_spibus_initialize() may then be used to - * bind the SPI driver to higher level logic (e.g., calling - * mmcsd_spislotinitialize(), for example, will bind the SPI driver to - * the SPI MMC/SD driver). - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_SPI1 -void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, - bool selected) -{ -#ifdef CONFIG_MMCSD_SPI - if (devid == SPIDEV_MMCSD(0)) - { - stm32_gpiowrite(GPIO_SDCARD_CS, !selected); - } -#endif - -#ifdef CONFIG_MTD_W25 - stm32_gpiowrite(FLASH_SPI1_CS, !selected); -#endif -} - -uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) -{ - uint8_t status = 0; - -#ifdef CONFIG_MMCSD_SPI - if (devid == SPIDEV_MMCSD(0)) - { - status |= SPI_STATUS_PRESENT; - } -#endif - - return status; -} -#endif - -#ifdef CONFIG_STM32_SPI2 -void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid, - bool selected) -{ -} - -uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) -{ - return 0; -} -#endif - -/**************************************************************************** - * Name: stm32_spi1cmddata - * - * Description: - * Set or clear the SH1101A A0 or SD1306 D/C n bit to select data (true) - * or command (false). This function must be provided by platform-specific - * logic. This is an implementation of the cmddata method of the SPI - * interface defined by struct spi_ops_s (see include/nuttx/spi/spi.h). - * - * Input Parameters: - * - * spi - SPI device that controls the bus the device that requires the CMD/ - * DATA selection. - * devid - If there are multiple devices on the bus, this selects which one - * to select cmd or data. NOTE: This design restricts, for example, - * one one SPI display per SPI bus. - * cmd - true: select command; false: select data - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef CONFIG_SPI_CMDDATA -#ifdef CONFIG_STM32_SPI1 -int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, - bool cmd) -{ - return -ENODEV; -} -#endif -#endif - -#endif /* CONFIG_STM32_SPI1 || CONFIG_STM32_SPI2 */ diff --git a/boards/arm/stm32/stm32f411-minimum/src/stm32_usb.c b/boards/arm/stm32/stm32f411-minimum/src/stm32_usb.c deleted file mode 100644 index 08afc617c0cf9..0000000000000 --- a/boards/arm/stm32/stm32f411-minimum/src/stm32_usb.c +++ /dev/null @@ -1,329 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f411-minimum/src/stm32_usb.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -#include "arm_internal.h" -#include "stm32.h" -#include "stm32_otgfs.h" -#include "stm32f411-minimum.h" - -#ifdef CONFIG_STM32_OTGFS - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#if !defined(CONFIG_USBDEV) && !defined(CONFIG_USBHOST) -# warning "CONFIG_STM32_OTGFS is enabled but neither CONFIG_USBDEV nor CONFIG_USBHOST" -#endif - -#ifndef CONFIG_STM32F411MINIMUM_USBHOST_PRIO -# define CONFIG_STM32F411MINIMUM_USBHOST_PRIO 100 -#endif - -#ifndef CONFIG_STM32F411MINIMUM_USBHOST_STACKSIZE -# define CONFIG_STM32F411MINIMUM_USBHOST_STACKSIZE 1024 -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -#ifdef CONFIG_USBHOST -static struct usbhost_connection_s *g_usbconn; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: usbhost_waiter - * - * Description: - * Wait for USB devices to be connected. - * - ****************************************************************************/ - -#ifdef CONFIG_USBHOST -static int usbhost_waiter(int argc, char *argv[]) -{ - struct usbhost_hubport_s *hport; - - uinfo("Running\n"); - for (; ; ) - { - /* Wait for the device to change state */ - - DEBUGVERIFY(CONN_WAIT(g_usbconn, &hport)); - uinfo("%s\n", hport->connected ? "connected" : "disconnected"); - - /* Did we just become connected? */ - - if (hport->connected) - { - /* Yes.. enumerate the newly connected device */ - - CONN_ENUMERATE(g_usbconn, hport); - } - } - - /* Keep the compiler from complaining */ - - return 0; -} -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_usbinitialize - * - * Description: - * Called from stm32_boardinitialize very early in initialization to setup - * USB-related GPIO pins for the WeAct Studio MiniF4 board. - * - ****************************************************************************/ - -void stm32_usbinitialize(void) -{ - /* The OTG FS has an internal soft pull-up. No GPIO configuration is - * required - * This board has no connections for VBUS, Power On, or Overcurrent - * GPIOs - */ -} - -/**************************************************************************** - * Name: stm32_usbhost_initialize - * - * Description: - * Called at application startup time to initialize the USB host - * functionality. This function will start a thread that will monitor for - * device connection/disconnection events. - * - ****************************************************************************/ - -#ifdef CONFIG_USBHOST -int stm32_usbhost_initialize(void) -{ - int ret; - - /* First, register all of the class drivers needed to support the drivers - * that we care about: - */ - - uinfo("Register class drivers\n"); - -#ifdef CONFIG_USBHOST_HUB - /* Initialize USB hub class support */ - - ret = usbhost_hub_initialize(); - if (ret < 0) - { - uerr("ERROR: usbhost_hub_initialize failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_USBHOST_MSC - /* Register the USB mass storage class class */ - - ret = usbhost_msc_initialize(); - if (ret != OK) - { - uerr("ERROR: Failed to register the mass storage class: %d\n", ret); - } -#endif - -#ifdef CONFIG_USBHOST_CDCACM - /* Register the CDC/ACM serial class */ - - ret = usbhost_cdcacm_initialize(); - if (ret != OK) - { - uerr("ERROR: Failed to register the CDC/ACM serial class: %d\n", ret); - } -#endif - -#ifdef CONFIG_USBHOST_HIDKBD - /* Initialize the HID keyboard class */ - - ret = usbhost_kbdinit(); - if (ret != OK) - { - uerr("ERROR: Failed to register the HID keyboard class\n"); - } -#endif - -#ifdef CONFIG_USBHOST_HIDMOUSE - /* Initialize the HID mouse class */ - - ret = usbhost_mouse_init(); - if (ret != OK) - { - uerr("ERROR: Failed to register the HID mouse class\n"); - } -#endif - -#ifdef CONFIG_USBHOST_XBOXCONTROLLER - /* Initialize the HID mouse class */ - - ret = usbhost_xboxcontroller_init(); - if (ret != OK) - { - uerr("ERROR: Failed to register the XBox Controller class\n"); - } -#endif - - /* Then get an instance of the USB host interface */ - - uinfo("Initialize USB host\n"); - g_usbconn = stm32_otgfshost_initialize(0); - if (g_usbconn) - { - /* Start a thread to handle device connection. */ - - uinfo("Start usbhost_waiter\n"); - - ret = kthread_create("usbhost", CONFIG_STM32F411MINIMUM_USBHOST_PRIO, - CONFIG_STM32F411MINIMUM_USBHOST_STACKSIZE, - usbhost_waiter, NULL); - return ret < 0 ? -ENOEXEC : OK; - } - - return -ENODEV; -} -#endif - -/**************************************************************************** - * Name: stm32_usbhost_vbusdrive - * - * Description: - * Enable/disable driving of VBUS 5V output. This function must be - * provided be each platform that implements the STM32 OTG FS host - * interface - * - * "On-chip 5 V VBUS generation is not supported. For this reason, a charge - * pump or, if 5 V are available on the application board, a basic power - * switch, must be added externally to drive the 5 V VBUS line. The - * external charge pump can be driven by any GPIO output. When the - * application decides to power on VBUS using the chosen GPIO, it must - * also set the port power bit in the host port control and status - * register (PPWR bit in OTG_FS_HPRT). - * - * "The application uses this field to control power to this port, and the - * core clears this bit on an overcurrent condition." - * - * Input Parameters: - * iface - For future growth to handle multiple USB host interface. - * Should be zero. - * enable - true: enable VBUS power; false: disable VBUS power - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef CONFIG_USBHOST -void stm32_usbhost_vbusdrive(int iface, bool enable) -{ - DEBUGASSERT(iface == 0); - - if (enable) - { - /* Enable the Power Switch by driving the enable pin low */ - - stm32_gpiowrite(GPIO_OTGFS_PWRON, false); - } - else - { - /* Disable the Power Switch by driving the enable pin high */ - - stm32_gpiowrite(GPIO_OTGFS_PWRON, true); - } -} -#endif - -/**************************************************************************** - * Name: stm32_setup_overcurrent - * - * Description: - * Setup to receive an interrupt-level callback if an overcurrent condition - * is detected. - * - * Input Parameters: - * handler - New overcurrent interrupt handler - * arg - The argument provided for the interrupt handler - * - * Returned Value: - * Zero (OK) is returned on success. Otherwise, a negated errno value is - * returned to indicate the nature of the failure. - * - ****************************************************************************/ - -#ifdef CONFIG_USBHOST -int stm32_setup_overcurrent(xcpt_t handler, void *arg) -{ - return stm32_gpiosetevent(GPIO_OTGFS_OVER, true, true, true, handler, arg); -} -#endif - -/**************************************************************************** - * Name: stm32_usbsuspend - * - * Description: - * Board logic must provide the stm32_usbsuspend logic if the USBDEV - * driver is used. This function is called whenever the USB enters or - * leaves suspend mode. - * This is an opportunity for the board logic to shutdown clocks, power, - * etc. while the USB is suspended. - * - ****************************************************************************/ - -#ifdef CONFIG_USBDEV -void stm32_usbsuspend(struct usbdev_s *dev, bool resume) -{ - uinfo("resume: %d\n", resume); -} -#endif - -#endif /* CONFIG_STM32_OTGFS */ diff --git a/boards/arm/stm32/stm32f411-minimum/src/stm32_usbmsc.c b/boards/arm/stm32/stm32f411-minimum/src/stm32_usbmsc.c deleted file mode 100644 index 19084231667d2..0000000000000 --- a/boards/arm/stm32/stm32f411-minimum/src/stm32_usbmsc.c +++ /dev/null @@ -1,71 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f411-minimum/src/stm32_usbmsc.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include - -#include "stm32.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -#ifndef CONFIG_SYSTEM_USBMSC_DEVMINOR1 -# define CONFIG_SYSTEM_USBMSC_DEVMINOR1 0 -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_usbmsc_initialize - * - * Description: - * Perform architecture specific initialization of the USB MSC device. - * - ****************************************************************************/ - -int board_usbmsc_initialize(int port) -{ - /* If system/usbmsc is built as an NSH command, then SD slot should - * already have been initialized. - * In this case, there is nothing further to be done here. - */ - -#ifndef CONFIG_NSH_BUILTIN_APPS - return stm32_w25initialize(CONFIG_SYSTEM_USBMSC_DEVMINOR1); -#else - return OK; -#endif -} diff --git a/boards/arm/stm32/stm32f411-minimum/src/stm32_userleds.c b/boards/arm/stm32/stm32f411-minimum/src/stm32_userleds.c deleted file mode 100644 index 3abebf3e77c49..0000000000000 --- a/boards/arm/stm32/stm32f411-minimum/src/stm32_userleds.c +++ /dev/null @@ -1,102 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f411-minimum/src/stm32_userleds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include - -#include "chip.h" -#include "stm32.h" -#include "stm32f411-minimum.h" - -#ifndef CONFIG_ARCH_LEDS - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* This array maps an LED number to GPIO pin configuration */ - -static const uint32_t g_ledcfg[BOARD_NLEDS] = -{ - GPIO_LED1, -}; - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_userled_initialize - ****************************************************************************/ - -uint32_t board_userled_initialize(void) -{ - int i; - - /* Configure LED GPIOs for output */ - - for (i = 0; i < BOARD_NLEDS; i++) - { - stm32_configgpio(g_ledcfg[i]); - } - - return BOARD_NLEDS; -} - -/**************************************************************************** - * Name: board_userled - ****************************************************************************/ - -void board_userled(int led, bool ledon) -{ - if ((unsigned)led < BOARD_NLEDS) - { - stm32_gpiowrite(g_ledcfg[led], ledon); - } -} - -/**************************************************************************** - * Name: board_userled_all - ****************************************************************************/ - -void board_userled_all(uint32_t ledset) -{ - int i; - - /* Configure LED GPIOs for output */ - - for (i = 0; i < BOARD_NLEDS; i++) - { - stm32_gpiowrite(g_ledcfg[i], (ledset & (1 << i)) != 0); - } -} - -#endif /* !CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/stm32f411-minimum/src/stm32_w25.c b/boards/arm/stm32/stm32f411-minimum/src/stm32_w25.c deleted file mode 100644 index 17427b4e92684..0000000000000 --- a/boards/arm/stm32/stm32f411-minimum/src/stm32_w25.c +++ /dev/null @@ -1,156 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f411-minimum/src/stm32_w25.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include - -#ifdef CONFIG_STM32_SPI1 -# include -# include -# include -# include -#endif - -#include "stm32_spi.h" - -#include "stm32f411-minimum.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Debug ********************************************************************/ - -/* Non-standard debug that may be enabled just for testing the watchdog - * timer - */ - -#define W25_SPI_PORT 1 - -/* Configuration ************************************************************/ - -/* Can't support the W25 device if it SPI1 or W25 support is not enabled */ - -#define HAVE_W25 1 -#if !defined(CONFIG_STM32_SPI1) || !defined(CONFIG_MTD_W25) -# undef HAVE_W25 -#endif - -/* Can't support W25 features if mountpoints are disabled */ - -#if defined(CONFIG_DISABLE_MOUNTPOINT) -# undef HAVE_W25 -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_w25initialize - * - * Description: - * Initialize and register the W25 FLASH file system. - * - ****************************************************************************/ - -int stm32_w25initialize(int minor) -{ - int ret; -#ifdef HAVE_W25 - struct spi_dev_s *spi; - struct mtd_dev_s *mtd; - struct mtd_geometry_s geo; -#if defined(CONFIG_MTD_PARTITION_NAMES) - const char *partname = CONFIG_STM32F411MINIMUM_FLASH_PART_NAMES; -#endif - - /* Get the SPI port */ - - spi = stm32_spibus_initialize(W25_SPI_PORT); - if (!spi) - { - syslog(LOG_ERR, "ERROR: Failed to initialize SPI port %d\n", - W25_SPI_PORT); - return -ENODEV; - } - - /* Raise SPI frequency from default 400kHz to something usable - * SPI1 uses PCLK2 of 96MHz with DIV2 = 48Mbps max - * W25Q64 requires more dummy clocks above 26MHz - */ - - SPI_SETFREQUENCY(spi, 24000000); - - /* Now bind the SPI interface to the W25 SPI FLASH driver */ - - mtd = w25_initialize(spi); - if (!mtd) - { - syslog(LOG_ERR, "ERROR: Failed to bind SPI port %d to the Winbond" - "W25 FLASH driver\n", W25_SPI_PORT); - return -ENODEV; - } - -#ifndef CONFIG_FS_SMARTFS - /* Register the MTD driver */ - - char path[32]; - snprintf(path, sizeof(path), "/dev/mtdblock%d", minor); - ret = register_mtddriver(path, mtd, 0755, NULL); - if (ret < 0) - { - syslog(LOG_ERR, - "ERROR: Failed to register the MTD driver %s, ret %d\n", - path, ret); - return ret; - } -#else - /* Initialize to provide SMARTFS on the MTD interface */ - - /* Get the geometry of the FLASH device */ - - ret = mtd->ioctl(mtd, MTDIOC_GEOMETRY, (unsigned long)((uintptr_t)&geo)); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: mtd->ioctl failed: %d\n", ret); - return ret; - } - - /* Configure the device with no partition support */ - - smart_initialize(CONFIG_STM32F411MINIMUM_FLASH_MINOR, mtd, NULL); - -#endif /* CONFIG_FS_SMARTFS */ -#endif /* HAVE_W25 */ - - return OK; -} diff --git a/boards/arm/stm32/stm32f411e-disco/CMakeLists.txt b/boards/arm/stm32/stm32f411e-disco/CMakeLists.txt deleted file mode 100644 index 884177caaef25..0000000000000 --- a/boards/arm/stm32/stm32f411e-disco/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/stm32f411e-disco/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32/stm32f411e-disco/configs/nsh/defconfig b/boards/arm/stm32/stm32f411e-disco/configs/nsh/defconfig deleted file mode 100644 index 3a2397b01beab..0000000000000 --- a/boards/arm/stm32/stm32f411e-disco/configs/nsh/defconfig +++ /dev/null @@ -1,47 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_ARCH_LEDS is not set -# CONFIG_DISABLE_OS_API is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -# CONFIG_NSH_DISABLE_IFCONFIG is not set -# CONFIG_NSH_DISABLE_PS is not set -# CONFIG_STM32_SYSCFG is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f411e-disco" -CONFIG_ARCH_BOARD_STM32F411E_DISCO=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F411VE=y -CONFIG_ARCH_INTERRUPTSTACK=2048 -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=8499 -CONFIG_BUILTIN=y -CONFIG_HAVE_CXX=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=131072 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=14 -CONFIG_START_MONTH=10 -CONFIG_START_YEAR=2014 -CONFIG_STM32_FLASH_CONFIG_E=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_USART2=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/stm32f411e-disco/include/board.h b/boards/arm/stm32/stm32f411e-disco/include/board.h deleted file mode 100644 index 903bf73d31712..0000000000000 --- a/boards/arm/stm32/stm32f411e-disco/include/board.h +++ /dev/null @@ -1,358 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f411e-disco/include/board.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __BOARDS_ARM_STM32_STM32F411E_DISCO_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32_STM32F411E_DISCO_INCLUDE_BOARD_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#ifndef __ASSEMBLY__ -# include -#endif - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Clocking *****************************************************************/ - -/* System Clock source : PLLCLK (HSE) - * SYSCLK(Hz) : 96000000 Determined by PLL - * configuration - * HCLK(Hz) : 96000000 (STM32_RCC_CFGR_HPRE) - * AHB Prescaler : 1 (STM32_RCC_CFGR_HPRE) - * APB1 Prescaler : 4 (STM32_RCC_CFGR_PPRE1) - * APB2 Prescaler : 2 (STM32_RCC_CFGR_PPRE2) - * HSI Frequency(Hz) : 16000000 (nominal) - * PLLM : 4 (STM32_PLLCFG_PLLM) - * PLLN : 192 (STM32_PLLCFG_PLLN) - * PLLP : 4 (STM32_PLLCFG_PLLP) - * PLLQ : 8 (STM32_PLLCFG_PPQ) - * Flash Latency(WS) : 3 - * Prefetch Buffer : OFF - * Instruction cache : ON - * Data cache : ON - * Require 48MHz for USB OTG FS, : Enabled - * SDIO and RNG clock - */ - -/* HSI - 16 MHz RC factory-trimmed - * LSI - 32 KHz RC - * HSE - 8 MHz Crystal - * LSE - not installed - */ - -#define STM32_BOARD_XTAL 8000000ul - -#define STM32_HSI_FREQUENCY 16000000ul -#define STM32_LSI_FREQUENCY 32000 -#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL - -/* Main PLL Configuration. - * - * Formulae: - * - * VCO input frequency = PLL input clock frequency / PLLM, - * 2 <= PLLM <= 63 - * VCO output frequency = VCO input frequency × PLLN, - * 192 <= PLLN <= 432 - * PLL output clock frequency = VCO frequency / PLLP, - * PLLP = 2, 4, 6, or 8 - * USB OTG FS clock frequency = VCO frequency / PLLQ, - * 2 <= PLLQ <= 15 - * - * There is no config for 100 MHz and 48 MHz for usb, - * so we would like to have SYSYCLK=96MHz and we must have the - * USB clock= 48MHz. - * - * PLLQ = 8 PLLP = 4 PLLN=192 PLLM=4 - * - * We will configure like this - * - * PLL source is HSE - * PLL_VCO = (STM32_HSE_FREQUENCY / PLLM) * PLLN - * = (8,000,000 / 4) * 192 - * = 384,000,000 - * SYSCLK = PLL_VCO / PLLP - * = 384,000,000 / 4 = 96,000,000 - * USB OTG FS and SDIO Clock - * = PLL_VCO / PLLQ - * = 384,000,000 / 8 = 48,000,000 - */ - -#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(4) -#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(192) -#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_4 -#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(8) - -#define STM32_SYSCLK_FREQUENCY 96000000ul - -/* AHB clock (HCLK) is SYSCLK (96MHz) */ - -#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ -#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY - -/* APB1 clock (PCLK1) is HCLK/4 (24MHz) */ - -#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd4 /* PCLK1 = HCLK / 4 */ -#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/4) - -/* Timers driven from APB1 will be twice PCLK1 */ - -/* REVISIT */ - -#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) - -/* APB2 clock (PCLK2) is HCLK (48MHz) */ - -#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLKd2 /* PCLK2 = HCLK / 2 */ -#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/2) - -/* Timers driven from APB2 will be twice PCLK2 */ - -#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM9_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB2_TIM10_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB2_TIM11_CLKIN (2*STM32_PCLK1_FREQUENCY) - -/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx - * otherwise frequency is 2xAPBx. - * Note: TIM1,8 are on APB2, others on APB1 - */ - -/* REVISIT */ - -#define BOARD_TIM1_FREQUENCY (2 * STM32_PCLK2_FREQUENCY) -#define BOARD_TIM2_FREQUENCY (2 * STM32_PCLK1_FREQUENCY) -#define BOARD_TIM3_FREQUENCY (2 * STM32_PCLK1_FREQUENCY) -#define BOARD_TIM4_FREQUENCY (2 * STM32_PCLK1_FREQUENCY) -#define BOARD_TIM5_FREQUENCY (2 * STM32_PCLK1_FREQUENCY) -#define BOARD_TIM6_FREQUENCY (2 * STM32_PCLK1_FREQUENCY) -#define BOARD_TIM7_FREQUENCY (2 * STM32_PCLK1_FREQUENCY) -#define BOARD_TIM8_FREQUENCY (2 * STM32_PCLK2_FREQUENCY) - -/* SDIO dividers. Note that slower clocking is required when DMA is disabled - * in order to avoid RX overrun/TX underrun errors due to delayed responses - * to service FIFOs in interrupt driven mode. These values have not been - * tuned!!! - * - * HCLK=72MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(178+2)=400 KHz - */ - -/* REVISIT */ - -#define SDIO_INIT_CLKDIV (178 << SDIO_CLKCR_CLKDIV_SHIFT) - -/* DMA ON: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(2+2)=18 MHz - * DMA OFF: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(3+2)=14.4 MHz - */ - -/* REVISIT */ - -#ifdef CONFIG_SDIO_DMA -# define SDIO_MMCXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT) -#else -# define SDIO_MMCXFR_CLKDIV (3 << SDIO_CLKCR_CLKDIV_SHIFT) -#endif - -/* DMA ON: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(1+2)=24 MHz - * DMA OFF: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(3+2)=14.4 MHz - */ - -/* REVISIT */ - -#ifdef CONFIG_SDIO_DMA -# define SDIO_SDXFR_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT) -#else -# define SDIO_SDXFR_CLKDIV (3 << SDIO_CLKCR_CLKDIV_SHIFT) -#endif - -/* DMA Channel/Stream Selections ********************************************/ - -/* Stream selections are arbitrary for now but might become important in the - * future is we set aside more DMA channels/streams. - * - * SDIO DMA - *   DMAMAP_SDIO_1 = Channel 4, Stream 3 <- may later be used by SPI DMA - *   DMAMAP_SDIO_2 = Channel 4, Stream 6 - */ - -#define DMAMAP_SDIO DMAMAP_SDIO_1 - -/* Need to VERIFY fwb */ - -#define DMACHAN_SPI1_RX DMAMAP_SPI1_RX_1 -#define DMACHAN_SPI1_TX DMAMAP_SPI1_TX_1 -#define DMACHAN_SPI2_RX DMAMAP_SPI2_RX -#define DMACHAN_SPI2_TX DMAMAP_SPI2_TX - -/* Alternate function pin selections ****************************************/ - -/* USART1: - * RXD: PA10 CN9 pin 3, CN10 pin 33 - * PB7 CN7 pin 21 - * TXD: PA9 CN5 pin 1, CN10 pin 21 - * PB6 CN5 pin 3, CN10 pin 17 - */ - -#if 1 -# define GPIO_USART1_RX (GPIO_USART1_RX_1|GPIO_SPEED_100MHz) /* PA10 */ -# define GPIO_USART1_TX (GPIO_USART1_TX_1|GPIO_SPEED_100MHz) /* PA9 */ -#else -# define GPIO_USART1_RX (GPIO_USART1_RX_2|GPIO_SPEED_100MHz) /* PB7 */ -# define GPIO_USART1_TX (GPIO_USART1_TX_2|GPIO_SPEED_100MHz) /* PB6 */ -#endif - -/* USART2: - * RXD: PA3 CN9 pin 1 (See SB13, 14, 62, 63). CN10 pin 37 - * PD6 - * TXD: PA2 CN9 pin 2(See SB13, 14, 62, 63). CN10 pin 35 - * PD5 - */ - -#define GPIO_USART2_RX (GPIO_USART2_RX_1|GPIO_SPEED_100MHz) /* PA3 */ -#define GPIO_USART2_TX (GPIO_USART2_TX_1|GPIO_SPEED_100MHz) /* PA2 */ -#define GPIO_USART2_RTS GPIO_USART2_RTS_2 -#define GPIO_USART2_CTS GPIO_USART2_CTS_2 - -/* USART6: - * RXD: PC7 CN5 pin2, CN10 pin 19 - * PA12 CN10, pin 12 - * TXD: PC6 CN10, pin 4 - * PA11 CN10, pin 14 - */ - -#define GPIO_USART6_RX (GPIO_USART6_RX_1|GPIO_SPEED_100MHz) /* PC7 */ -#define GPIO_USART6_TX (GPIO_USART6_TX_1|GPIO_SPEED_100MHz) /* PC6 */ - -/* UART RX DMA configurations */ - -#define DMAMAP_USART1_RX DMAMAP_USART1_RX_2 -#define DMAMAP_USART6_RX DMAMAP_USART6_RX_2 - -/* I2C - * - * The optional _GPIO configurations allow the I2C driver to manually - * reset the bus to clear stuck slaves. They match the pin configuration, - * but are normally-high GPIOs. - */ - -#define GPIO_I2C1_SCL (GPIO_I2C1_SCL_2|GPIO_SPEED_50MHz) -#define GPIO_I2C1_SDA (GPIO_I2C1_SDA_2|GPIO_SPEED_50MHz) -#define GPIO_I2C1_SCL_GPIO \ - (GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTB|GPIO_PIN8) -#define GPIO_I2C1_SDA_GPIO \ - (GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTB|GPIO_PIN9) - -#define GPIO_I2C2_SCL (GPIO_I2C2_SCL_1|GPIO_SPEED_50MHz) -#define GPIO_I2C2_SDA (GPIO_I2C2_SDA_1|GPIO_SPEED_50MHz) -#define GPIO_I2C2_SCL_GPIO \ - (GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTB|GPIO_PIN10) -#define GPIO_I2C2_SDA_GPIO \ - (GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTB|GPIO_PIN11) - -/* SPI - * - * There are sensors on SPI1, and SPI2 is connected to the FRAM. - */ - -#define GPIO_SPI1_MISO (GPIO_SPI1_MISO_1|GPIO_SPEED_50MHz) -#define GPIO_SPI1_MOSI (GPIO_SPI1_MOSI_1|GPIO_SPEED_50MHz) -#define GPIO_SPI1_SCK (GPIO_SPI1_SCK_1|GPIO_SPEED_50MHz) - -#define GPIO_SPI2_MISO (GPIO_SPI2_MISO_1|GPIO_SPEED_50MHz) -#define GPIO_SPI2_MOSI (GPIO_SPI2_MOSI_1|GPIO_SPEED_50MHz) -#define GPIO_SPI2_SCK (GPIO_SPI2_SCK_2|GPIO_SPEED_50MHz) - -/* LEDs - * - * The STM32F411E Discovery board has four user leds - * LD3 connected to PD13. - * LD4 connected to PD12. - * LD5 connected to PD14. - * LD6 connected to PD15. - */ - -/* LED index values for use with board_userled() */ - -#define BOARD_LD3 0 -#define BOARD_LD4 1 -#define BOARD_LD5 2 -#define BOARD_LD6 3 -#define BOARD_NLEDS 4 - -/* LED bits for use with board_userled_all() */ - -#define BOARD_LD3_BIT (1 << BOARD_LD3) -#define BOARD_LD4_BIT (1 << BOARD_LD4) -#define BOARD_LD5_BIT (1 << BOARD_LD5) -#define BOARD_LD6_BIT (1 << BOARD_LD6) - -/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the LED on board. - * The following definitions describe how NuttX controls - * the LEDs: - * - * SYMBOL Meaning LED - * ------------------- ---------------------------- -------------------- - */ - -#define LED_STARTED 0 /* NuttX has been started None */ -#define LED_HEAPALLOCATE 1 /* Heap has been allocated ON(1), OFF(2) */ -#define LED_IRQSENABLED 2 /* Interrupts enabled OFF(1), ON(2) */ -#define LED_STACKCREATED 3 /* Idle stack created ON(1), ON(2) */ -#define LED_INIRQ 4 /* In an interrupt (no change) */ -#define LED_SIGNAL 5 /* In a signal handler (no change) */ -#define LED_ASSERTION 6 /* An assertion failed ON(3) */ -#define LED_PANIC 7 /* The system has crashed FLASH(1,2) */ -#define LED_IDLE 8 /* idle loop FLASH(4) */ - -/* Buttons - * - * B1 USER: the user button is connected to the I/O PA0 of the STM32 - * microcontroller. - */ - -#define BUTTON_USER 0 -#define NUM_BUTTONS 1 - -#define BUTTON_USER_BIT (1 << BUTTON_USER) - -/* USB OTG FS */ - -#define GPIO_OTGFS_DM (GPIO_OTGFS_DM_0|GPIO_SPEED_100MHz) -#define GPIO_OTGFS_DP (GPIO_OTGFS_DP_0|GPIO_SPEED_100MHz) -#define GPIO_OTGFS_ID (GPIO_OTGFS_ID_0|GPIO_SPEED_100MHz) -#define GPIO_OTGFS_SOF (GPIO_OTGFS_SOF_0|GPIO_SPEED_100MHz) - -#endif /* __BOARDS_ARM_STM32_STM32F411E_DISCO_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32/stm32f411e-disco/scripts/Make.defs b/boards/arm/stm32/stm32f411e-disco/scripts/Make.defs deleted file mode 100644 index 606d070f68d40..0000000000000 --- a/boards/arm/stm32/stm32f411e-disco/scripts/Make.defs +++ /dev/null @@ -1,41 +0,0 @@ -############################################################################ -# boards/arm/stm32/stm32f411e-disco/scripts/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/.config -include $(TOPDIR)/tools/Config.mk -include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs - -LDSCRIPT = f411ve.ld -ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) - -ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 - -CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) -CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) -CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -AFLAGS := $(CFLAGS) -D__ASSEMBLY__ - -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections -LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32/stm32f411e-disco/src/CMakeLists.txt b/boards/arm/stm32/stm32f411e-disco/src/CMakeLists.txt deleted file mode 100644 index 9f3433d0cc824..0000000000000 --- a/boards/arm/stm32/stm32f411e-disco/src/CMakeLists.txt +++ /dev/null @@ -1,31 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/stm32f411e-disco/src/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -set(SRCS stm32_boot.c stm32_bringup.c) - -if(CONFIG_STM32_OTGFS) - list(APPEND SRCS stm32_usb.c) -endif() - -target_sources(board PRIVATE ${SRCS}) - -set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/f411ve.ld") diff --git a/boards/arm/stm32/stm32f411e-disco/src/Make.defs b/boards/arm/stm32/stm32f411e-disco/src/Make.defs deleted file mode 100644 index cff6ead802f11..0000000000000 --- a/boards/arm/stm32/stm32f411e-disco/src/Make.defs +++ /dev/null @@ -1,43 +0,0 @@ -############################################################################ -# boards/arm/stm32/stm32f411e-disco/src/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/Make.defs - -CSRCS = stm32_boot.c stm32_bringup.c - -ifeq ($(CONFIG_ARCH_BUTTONS),y) - CSRCS += stm32_buttons.c -endif - -ifeq ($(CONFIG_ARCH_LEDS),y) - CSRCS += stm32_autoleds.c -else - CSRCS += stm32_userleds.c -endif - -ifeq ($(CONFIG_STM32_OTGFS),y) -CSRCS += stm32_usb.c -endif - -DEPPATH += --dep-path board -VPATH += :board -CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/stm32f411e-disco/src/stm32_autoleds.c b/boards/arm/stm32/stm32f411e-disco/src/stm32_autoleds.c deleted file mode 100644 index 07237023ba414..0000000000000 --- a/boards/arm/stm32/stm32f411e-disco/src/stm32_autoleds.c +++ /dev/null @@ -1,134 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f411e-disco/src/stm32_autoleds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32.h" -#include "stm32f411e-disco.h" - -#ifdef CONFIG_ARCH_LEDS - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_autoled_initialize - ****************************************************************************/ - -void board_autoled_initialize(void) -{ - /* Configure LED GPIO for output */ - - stm32_configgpio(GPIO_LD3); - stm32_configgpio(GPIO_LD4); - stm32_configgpio(GPIO_LD5); - stm32_configgpio(GPIO_LD6); -} - -/**************************************************************************** - * Name: board_autoled_on - ****************************************************************************/ - -void board_autoled_on(int led) -{ - switch (led) - { - case LED_HEAPALLOCATE: - { - stm32_gpiowrite(GPIO_LD3, true); - stm32_gpiowrite(GPIO_LD4, false); - } - break; - - case LED_IRQSENABLED: - { - stm32_gpiowrite(GPIO_LD3, false); - stm32_gpiowrite(GPIO_LD4, true); - } - break; - - case LED_STACKCREATED: - { - stm32_gpiowrite(GPIO_LD3, true); - stm32_gpiowrite(GPIO_LD4, true); - } - break; - - case LED_ASSERTION: - { - stm32_gpiowrite(GPIO_LD5, true); - } - break; - - case LED_PANIC: - { - stm32_gpiowrite(GPIO_LD3, true); - stm32_gpiowrite(GPIO_LD4, true); - } - break; - - case LED_IDLE: - { - stm32_gpiowrite(GPIO_LD6, true); - } - break; - } -} - -/**************************************************************************** - * Name: board_autoled_off - ****************************************************************************/ - -void board_autoled_off(int led) -{ - switch (led) - { - case LED_PANIC: - { - stm32_gpiowrite(GPIO_LD3, false); - stm32_gpiowrite(GPIO_LD4, false); - } - break; - - case LED_IDLE: - { - stm32_gpiowrite(GPIO_LD6, false); - } - break; - } -} - -#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/stm32f411e-disco/src/stm32_boot.c b/boards/arm/stm32/stm32f411e-disco/src/stm32_boot.c deleted file mode 100644 index 9aecad9bdee43..0000000000000 --- a/boards/arm/stm32/stm32f411e-disco/src/stm32_boot.c +++ /dev/null @@ -1,101 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f411e-disco/src/stm32_boot.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include -#include - -#include - -#include "arm_internal.h" -#include "stm32f411e-disco.h" - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_boardinitialize - * - * Description: - * All STM32 architectures must provide the following entry point. - * This entry point is called early in the initialization -- after all - * memory has been configured and mapped but before any devices have been - * initialized. - * - ****************************************************************************/ - -void stm32_boardinitialize(void) -{ -#ifdef CONFIG_ARCH_LEDS - /* Configure on-board LEDs if LED support has been selected. */ - - board_autoled_initialize(); -#endif - -#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || \ - defined(CONFIG_STM32_SPI3) - /* Configure SPI chip selects if 1) SP2 is not disabled, and 2) the - * weak function stm32_spidev_initialize() has been brought into the link. - */ - - stm32_spidev_initialize(); -#endif - -#ifdef CONFIG_STM32_OTGFS - /* Initialize USB if the OTG FS controller is in the configuration. - * Presumably either CONFIG_USBDEV or CONFIG_USBHOST is also selected. - */ - - stm32_usbinitialize(); -#endif -} - -/**************************************************************************** - * Name: board_late_initialize - * - * Description: - * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional - * initialization call will be performed in the boot-up sequence to a - * function called board_late_initialize(). board_late_initialize() will - * be called immediately after up_initialize() is called and just before - * the initial application is started. This additional initialization - * phase may be used, for example, to initialize board-specific device - * drivers. - * - ****************************************************************************/ - -#ifdef CONFIG_BOARD_LATE_INITIALIZE -void board_late_initialize(void) -{ - /* Perform board-specific initialization */ - - stm32_bringup(); -} -#endif diff --git a/boards/arm/stm32/stm32f411e-disco/src/stm32_bringup.c b/boards/arm/stm32/stm32f411e-disco/src/stm32_bringup.c deleted file mode 100644 index fe85d312f3e6b..0000000000000 --- a/boards/arm/stm32/stm32f411e-disco/src/stm32_bringup.c +++ /dev/null @@ -1,113 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f411e-disco/src/stm32_bringup.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include - -#include "stm32.h" - -#ifdef CONFIG_STM32_OTGFS -# include "stm32_usbhost.h" -#endif - -#ifdef CONFIG_INPUT_BUTTONS -# include -#endif - -#ifdef CONFIG_USERLED -# include -#endif - -#include "stm32f411e-disco.h" - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_bringup - * - * Description: - * Perform architecture-specific initialization - * - * CONFIG_BOARD_LATE_INITIALIZE=y : - * Called from board_late_initialize(). - * - ****************************************************************************/ - -int stm32_bringup(void) -{ - int ret = OK; - -#if defined(CONFIG_STM32_OTGFS) && defined(CONFIG_USBHOST) - /* Initialize USB host operation. stm32_usbhost_initialize() starts - * a thread will monitor for USB connection and disconnection events. - */ - - ret = stm32_usbhost_initialize(); - if (ret != OK) - { - uerr("ERROR: Failed to initialize USB host: %d\n", ret); - return ret; - } -#endif - -#ifdef CONFIG_FS_PROCFS - /* Mount the procfs file system */ - - ret = nx_mount(NULL, STM32_PROCFS_MOUNTPOINT, "procfs", 0, NULL); - if (ret < 0) - { - ferr("ERROR: Failed to mount procfs at %s: %d\n", - STM32_PROCFS_MOUNTPOINT, ret); - } -#endif - -#ifdef CONFIG_USERLED - /* Register the LED driver */ - - ret = userled_lower_initialize("/dev/userleds"); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: userled_lower_initialize() failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_INPUT_BUTTONS - /* Register the BUTTON driver */ - - ret = btn_lower_initialize("/dev/buttons"); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: btn_lower_initialize() failed: %d\n", ret); - } -#endif - - return ret; -} diff --git a/boards/arm/stm32/stm32f411e-disco/src/stm32_buttons.c b/boards/arm/stm32/stm32f411e-disco/src/stm32_buttons.c deleted file mode 100644 index ef990dc549be1..0000000000000 --- a/boards/arm/stm32/stm32f411e-disco/src/stm32_buttons.c +++ /dev/null @@ -1,160 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f411e-disco/src/stm32_buttons.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include -#include - -#include "stm32_gpio.h" -#include "stm32f411e-disco.h" - -#if defined(CONFIG_ARCH_BUTTONS) - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#if defined(CONFIG_INPUT_BUTTONS) && !defined(CONFIG_ARCH_IRQBUTTONS) -# error "The NuttX Buttons Driver depends on IRQ support to work!\n" -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/* Pin configuration for each STM32F3Discovery button. This array is indexed - * by the BUTTON_* definitions in board.h - */ - -static const uint32_t g_buttons[NUM_BUTTONS] = -{ - GPIO_BTN_USER -}; - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_button_initialize - * - * Description: - * board_button_initialize() must be called to initialize button resources. - * After that, board_buttons() may be called to collect the current state - * of all buttons or board_button_irq() may be called to register button - * interrupt handlers. - * - ****************************************************************************/ - -uint32_t board_button_initialize(void) -{ - int i; - - /* Configure the GPIO pins as inputs. NOTE that EXTI interrupts are - * configured for all pins. - */ - - for (i = 0; i < NUM_BUTTONS; i++) - { - stm32_configgpio(g_buttons[i]); - } - - return NUM_BUTTONS; -} - -/**************************************************************************** - * Name: board_buttons - ****************************************************************************/ - -uint32_t board_buttons(void) -{ - uint32_t ret = 0; - int i; - - /* Check that state of each key */ - - for (i = 0; i < NUM_BUTTONS; i++) - { - /* A LOW value means that the key is pressed. */ - - bool released = stm32_gpioread(g_buttons[i]); - - /* Accumulate the set of depressed (not released) keys */ - - if (!released) - { - ret |= (1 << i); - } - } - - return ret; -} - -/**************************************************************************** - * Button support. - * - * Description: - * board_button_initialize() must be called to initialize button resources. - * After that, board_buttons() may be called to collect the current state - * of all buttons or board_button_irq() may be called to register button - * interrupt handlers. - * - * After board_button_initialize() has been called, board_buttons() may be - * called to collect the state of all buttons. board_buttons() returns - * an 32-bit bit set with each bit associated with a button. See the - * BUTTON_*_BIT definitions in board.h for the meaning of each bit. - * - * board_button_irq() may be called to register an interrupt handler that - * will be called when a button is depressed or released. The ID value is - * a button enumeration value that uniquely identifies a button resource. - * See the BUTTON_* definitions in board.h for the meaning of enumeration - * value. - * - ****************************************************************************/ - -#ifdef CONFIG_ARCH_IRQBUTTONS -int board_button_irq(int id, xcpt_t irqhandler, void *arg) -{ - int ret = -EINVAL; - - /* The following should be atomic */ - - if (id >= MIN_IRQBUTTON && id <= MAX_IRQBUTTON) - { - ret = stm32_gpiosetevent(g_buttons[id], true, true, true, irqhandler, - arg); - } - - return ret; -} -#endif - -#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/stm32/stm32f411e-disco/src/stm32_usb.c b/boards/arm/stm32/stm32f411e-disco/src/stm32_usb.c deleted file mode 100644 index 83372a115e995..0000000000000 --- a/boards/arm/stm32/stm32f411e-disco/src/stm32_usb.c +++ /dev/null @@ -1,353 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f411e-disco/src/stm32_usb.c - * - * SPDX-License-Identifier: BSD-3-Clause - * SPDX-FileCopyrightText: 2017 Gregory Nutt. All rights reserved. - * SPDX-FileCopyrightText: 2017 Brian Webb. All rights reserved. - * SPDX-FileContributor: Gregory Nutt - * SPDX-FileContributor: Brian Webb - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -#include "arm_internal.h" -#include "stm32.h" -#include "stm32_otgfs.h" -#include "stm32f411e-disco.h" - -#ifdef CONFIG_STM32_OTGFS - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#if !defined(CONFIG_USBDEV) && !defined(CONFIG_USBHOST) -# warning "CONFIG_STM32_OTGFS is enabled but neither CONFIG_USBDEV nor CONFIG_USBHOST" -#endif - -#ifndef CONFIG_STM32F411DISCO_USBHOST_PRIO -# define CONFIG_STM32F411DISCO_USBHOST_PRIO 100 -#endif - -#ifndef CONFIG_STM32F411DISCO_USBHOST_STACKSIZE -# define CONFIG_STM32F411DISCO_USBHOST_STACKSIZE 1024 -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -#ifdef CONFIG_USBHOST -static struct usbhost_connection_s *g_usbconn; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: usbhost_waiter - * - * Description: - * Wait for USB devices to be connected. - * - ****************************************************************************/ - -#ifdef CONFIG_USBHOST -static int usbhost_waiter(int argc, char *argv[]) -{ - struct usbhost_hubport_s *hport; - - uinfo("Running\n"); - for (; ; ) - { - /* Wait for the device to change state */ - - DEBUGVERIFY(CONN_WAIT(g_usbconn, &hport)); - uinfo("%s\n", hport->connected ? "connected" : "disconnected"); - - /* Did we just become connected? */ - - if (hport->connected) - { - /* Yes.. enumerate the newly connected device */ - - CONN_ENUMERATE(g_usbconn, hport); - } - } - - /* Keep the compiler from complaining */ - - return 0; -} -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_usbinitialize - * - * Description: - * Called from stm32_usbinitialize very early in initialization to setup - * USB-related GPIO pins for the STM32F411 board. - * - ****************************************************************************/ - -void stm32_usbinitialize(void) -{ - /* The OTG FS has an internal soft pull-up. - * No GPIO configuration is required - */ - - /* Configure the OTG FS VBUS sensing GPIO, - * Power On, and Overcurrent GPIOs - */ - -#ifdef CONFIG_STM32_OTGFS - stm32_configgpio(GPIO_OTGFS_VBUS); - stm32_configgpio(GPIO_OTGFS_PWRON); - stm32_configgpio(GPIO_OTGFS_OVER); -#endif -} - -/**************************************************************************** - * Name: stm32_usbhost_initialize - * - * Description: - * Called at application startup time to initialize the USB host - * functionality. - * This function will start a thread that will monitor for device - * connection/disconnection events. - * - ****************************************************************************/ - -#ifdef CONFIG_USBHOST -int stm32_usbhost_initialize(void) -{ - int ret; - - /* First, register all of the class drivers needed to support the drivers - * that we care about: - */ - - uinfo("Register class drivers\n"); - -#ifdef CONFIG_USBHOST_HUB - /* Initialize USB hub class support */ - - ret = usbhost_hub_initialize(); - if (ret < 0) - { - uerr("ERROR: usbhost_hub_initialize failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_USBHOST_MSC - /* Register the USB mass storage class class */ - - ret = usbhost_msc_initialize(); - if (ret != OK) - { - uerr("ERROR: Failed to register the mass storage class: %d\n", ret); - } -#endif - -#ifdef CONFIG_USBHOST_CDCACM - /* Register the CDC/ACM serial class */ - - ret = usbhost_cdcacm_initialize(); - if (ret != OK) - { - uerr("ERROR: Failed to register the CDC/ACM serial class: %d\n", ret); - } -#endif - -#ifdef CONFIG_USBHOST_HIDKBD - /* Initialize the HID keyboard class */ - - ret = usbhost_kbdinit(); - if (ret != OK) - { - uerr("ERROR: Failed to register the HID keyboard class\n"); - } -#endif - -#ifdef CONFIG_USBHOST_HIDMOUSE - /* Initialize the HID mouse class */ - - ret = usbhost_mouse_init(); - if (ret != OK) - { - uerr("ERROR: Failed to register the HID mouse class\n"); - } -#endif - -#ifdef CONFIG_USBHOST_XBOXCONTROLLER - /* Initialize the HID mouse class */ - - ret = usbhost_xboxcontroller_init(); - if (ret != OK) - { - uerr("ERROR: Failed to register the XBox Controller class\n"); - } -#endif - - /* Then get an instance of the USB host interface */ - - uinfo("Initialize USB host\n"); - g_usbconn = stm32_otgfshost_initialize(0); - if (g_usbconn) - { - /* Start a thread to handle device connection. */ - - uinfo("Start usbhost_waiter\n"); - - ret = kthread_create("usbhost", CONFIG_STM32F411DISCO_USBHOST_PRIO, - CONFIG_STM32F411DISCO_USBHOST_STACKSIZE, - usbhost_waiter, NULL); - return ret < 0 ? -ENOEXEC : OK; - } - - return -ENODEV; -} -#endif - -/**************************************************************************** - * Name: stm32_usbhost_vbusdrive - * - * Description: - * Enable/disable driving of VBUS 5V output. This function must be - * provided be each platform that implements the STM32 OTG FS host - * interface - * - * "On-chip 5 V VBUS generation is not supported. For this reason, a - * charge pump or, if 5 V are available on the application board, a - * basic power switch, must be added externally to drive the 5 V VBUS - * line. The external charge pump can be driven by any GPIO output. - * When the application decides to power on VBUS using the chosen GPIO, - * it must also set the port power bit in the host port control and - * status register (PPWR bit in OTG_FS_HPRT). - * - * "The application uses this field to control power to this port, - * and the core clears this bit on an overcurrent condition." - * - * Input Parameters: - * iface - For future growth to handle multiple USB host interface. - * Should be zero. - * enable - true: enable VBUS power; false: disable VBUS power - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef CONFIG_USBHOST -void stm32_usbhost_vbusdrive(int iface, bool enable) -{ - DEBUGASSERT(iface == 0); - - if (enable) - { - /* Enable the Power Switch by driving the enable pin low */ - - stm32_gpiowrite(GPIO_OTGFS_PWRON, false); - } - else - { - /* Disable the Power Switch by driving the enable pin high */ - - stm32_gpiowrite(GPIO_OTGFS_PWRON, true); - } -} -#endif - -/**************************************************************************** - * Name: stm32_setup_overcurrent - * - * Description: - * Setup to receive an interrupt-level callback if an overcurrent - * condition is detected. - * - * Input Parameters: - * handler - New overcurrent interrupt handler - * arg - The argument provided for the interrupt handler - * - * Returned Value: - * Zero (OK) is returned on success. Otherwise, a negated errno value - * is returned to indicate the nature of the failure. - * - ****************************************************************************/ - -#ifdef CONFIG_USBHOST -int stm32_setup_overcurrent(xcpt_t handler, void *arg) -{ - return stm32_gpiosetevent(GPIO_OTGFS_OVER, true, true, true, handler, arg); -} -#endif - -/**************************************************************************** - * Name: stm32_usbsuspend - * - * Description: - * Board logic must provide the stm32_usbsuspend logic if the USBDEV - * driver is used. This function is called whenever the USB enters or - * leaves suspend mode. This is an opportunity for the board logic to - * shutdown clocks, power, etc. while the USB is suspended. - * - ****************************************************************************/ - -#ifdef CONFIG_USBDEV -void stm32_usbsuspend(struct usbdev_s *dev, bool resume) -{ - uinfo("resume: %d\n", resume); -} -#endif - -#endif /* CONFIG_STM32_OTGFS */ diff --git a/boards/arm/stm32/stm32f411e-disco/src/stm32_userleds.c b/boards/arm/stm32/stm32f411e-disco/src/stm32_userleds.c deleted file mode 100644 index a4b0a2bf7745a..0000000000000 --- a/boards/arm/stm32/stm32f411e-disco/src/stm32_userleds.c +++ /dev/null @@ -1,105 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f411e-disco/src/stm32_userleds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include - -#include "chip.h" -#include "stm32.h" -#include "stm32f411e-disco.h" - -#ifndef CONFIG_ARCH_LEDS - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* This array maps an LED number to GPIO pin configuration */ - -static const uint32_t g_ledcfg[BOARD_NLEDS] = -{ - GPIO_LD3, - GPIO_LD4, - GPIO_LD5, - GPIO_LD6, -}; - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_userled_initialize - ****************************************************************************/ - -uint32_t board_userled_initialize(void) -{ - int i; - - /* Configure LED GPIOs for output */ - - for (i = 0; i < BOARD_NLEDS; i++) - { - stm32_configgpio(g_ledcfg[i]); - } - - return BOARD_NLEDS; -} - -/**************************************************************************** - * Name: board_userled - ****************************************************************************/ - -void board_userled(int led, bool ledon) -{ - if ((unsigned)led < BOARD_NLEDS) - { - stm32_gpiowrite(g_ledcfg[led], ledon); - } -} - -/**************************************************************************** - * Name: board_userled_all - ****************************************************************************/ - -void board_userled_all(uint32_t ledset) -{ - int i; - - /* Configure LED GPIOs for output */ - - for (i = 0; i < BOARD_NLEDS; i++) - { - stm32_gpiowrite(g_ledcfg[i], (ledset & (1 << i)) != 0); - } -} - -#endif /* !CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/stm32f429i-disco/CMakeLists.txt b/boards/arm/stm32/stm32f429i-disco/CMakeLists.txt deleted file mode 100644 index 7e51cbd70df83..0000000000000 --- a/boards/arm/stm32/stm32f429i-disco/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/stm32f429i-disco/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32/stm32f429i-disco/configs/adc/defconfig b/boards/arm/stm32/stm32f429i-disco/configs/adc/defconfig deleted file mode 100644 index 2e4718deb92b3..0000000000000 --- a/boards/arm/stm32/stm32f429i-disco/configs/adc/defconfig +++ /dev/null @@ -1,62 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_STM32_CCMEXCLUDE is not set -# CONFIG_STM32_FLASH_PREFETCH is not set -CONFIG_ADC=y -CONFIG_ANALOG=y -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f429i-disco" -CONFIG_ARCH_BOARD_STM32F429I_DISCO=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F429Z=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_EXAMPLES_ADC=y -CONFIG_EXAMPLES_ADC_GROUPSIZE=3 -CONFIG_FS_PROCFS=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_HEAP2_BASE=0xD0000000 -CONFIG_HEAP2_SIZE=8388608 -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_MM_REGIONS=3 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=6 -CONFIG_START_MONTH=12 -CONFIG_START_YEAR=2011 -CONFIG_STM32_ADC1=y -CONFIG_STM32_ADC1_DMA=y -CONFIG_STM32_ADC3=y -CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32_DMA1=y -CONFIG_STM32_DMA2=y -CONFIG_STM32_EXTERNAL_RAM=y -CONFIG_STM32_FMC=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_PWR=y -CONFIG_STM32_TIM1=y -CONFIG_STM32_TIM1_ADC=y -CONFIG_STM32_USART1=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/stm32f429i-disco/configs/bootlogo/defconfig b/boards/arm/stm32/stm32f429i-disco/configs/bootlogo/defconfig deleted file mode 100644 index d9f7431a0247f..0000000000000 --- a/boards/arm/stm32/stm32f429i-disco/configs/bootlogo/defconfig +++ /dev/null @@ -1,83 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_STM32_FB_CMAP is not set -# CONFIG_STM32_FLASH_PREFETCH is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f429i-disco" -CONFIG_ARCH_BOARD_STM32F429I_DISCO=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F429Z=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_DRIVERS_VIDEO=y -CONFIG_EXAMPLES_FB=y -CONFIG_EXAMPLES_FBOVERLAY=y -CONFIG_EXAMPLES_TOUCHSCREEN=y -CONFIG_FB_OVERLAY_BLIT=y -CONFIG_FB_SYNC=y -CONFIG_FS_PROCFS=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_HEAP2_BASE=0xD0000000 -CONFIG_HEAP2_SIZE=7774208 -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INPUT=y -CONFIG_INPUT_STMPE811=y -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=128 -CONFIG_MM_REGIONS=2 -CONFIG_MQ_MAXMSGSIZE=64 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_MAXARGUMENTS=17 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_WAITPID=y -CONFIG_SPI_CMDDATA=y -CONFIG_START_DAY=15 -CONFIG_START_MONTH=11 -CONFIG_START_YEAR=2017 -CONFIG_STM32F429I_DISCO_ILI9341=y -CONFIG_STM32_CCMEXCLUDE=y -CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32_DMA2D=y -CONFIG_STM32_DMA2D_FB_BASE=0xD07B5000 -CONFIG_STM32_DMA2D_FB_SIZE=307200 -CONFIG_STM32_DMA2D_LAYER_PPLINE=240 -CONFIG_STM32_DMA2D_NLAYERS=2 -CONFIG_STM32_EXTERNAL_RAM=y -CONFIG_STM32_FMC=y -CONFIG_STM32_I2C3=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_LTDC=y -CONFIG_STM32_LTDC_FB_BASE=0xD076A000 -CONFIG_STM32_LTDC_FB_SIZE=307200 -CONFIG_STM32_PWR=y -CONFIG_STM32_SPI5=y -CONFIG_STM32_USART1=y -CONFIG_STMPE811_ACTIVELOW=y -CONFIG_STMPE811_EDGE=y -CONFIG_STMPE811_THRESHX=39 -CONFIG_STMPE811_THRESHY=51 -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART1_SERIAL_CONSOLE=y -CONFIG_VIDEO_FB=y -CONFIG_VIDEO_FB_SPLASHSCREEN=y -CONFIG_VIDEO_FB_SPLASHSCREEN_BPP16=y -CONFIG_VIDEO_FB_SPLASHSCREEN_DISP_TIME=2 diff --git a/boards/arm/stm32/stm32f429i-disco/configs/extflash/defconfig b/boards/arm/stm32/stm32f429i-disco/configs/extflash/defconfig deleted file mode 100644 index 6126452086010..0000000000000 --- a/boards/arm/stm32/stm32f429i-disco/configs/extflash/defconfig +++ /dev/null @@ -1,64 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_STM32_FLASH_PREFETCH is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f429i-disco" -CONFIG_ARCH_BOARD_STM32F429I_DISCO=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F429Z=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_FS_PROCFS=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_HEAP2_BASE=0xD0000000 -CONFIG_HEAP2_SIZE=8388608 -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_MM_REGIONS=3 -CONFIG_MTD_CONFIG=y -CONFIG_MTD_CONFIG_RAM_CONSOLIDATE=y -CONFIG_MTD_PARTITION=y -CONFIG_MTD_PARTITION_NAMES=y -CONFIG_MTD_SMART_SECTOR_SIZE=512 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PLATFORM_CONFIGDATA=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_SMARTFS_MULTI_ROOT_DIRS=y -CONFIG_START_DAY=6 -CONFIG_START_MONTH=12 -CONFIG_START_YEAR=2011 -CONFIG_STM32F429I_DISCO_FLASH=y -CONFIG_STM32F429I_DISCO_FLASH_PART=y -CONFIG_STM32F429I_DISCO_RAMMTD=y -CONFIG_STM32F429I_DISCO_RAMMTD_SIZE=256 -CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32_EXTERNAL_RAM=y -CONFIG_STM32_FMC=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_PWR=y -CONFIG_STM32_RNG=y -CONFIG_STM32_SPI5=y -CONFIG_STM32_USART1=y -CONFIG_SYSTEM_FLASH_ERASEALL=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/stm32f429i-disco/configs/fb/defconfig b/boards/arm/stm32/stm32f429i-disco/configs/fb/defconfig deleted file mode 100644 index f4449b5807ff3..0000000000000 --- a/boards/arm/stm32/stm32f429i-disco/configs/fb/defconfig +++ /dev/null @@ -1,80 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_STM32_FB_CMAP is not set -# CONFIG_STM32_FLASH_PREFETCH is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f429i-disco" -CONFIG_ARCH_BOARD_STM32F429I_DISCO=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F429Z=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_DRIVERS_VIDEO=y -CONFIG_EXAMPLES_FB=y -CONFIG_EXAMPLES_FBOVERLAY=y -CONFIG_EXAMPLES_TOUCHSCREEN=y -CONFIG_FB_OVERLAY_BLIT=y -CONFIG_FB_SYNC=y -CONFIG_FS_PROCFS=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_HEAP2_BASE=0xD0000000 -CONFIG_HEAP2_SIZE=7774208 -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INPUT=y -CONFIG_INPUT_STMPE811=y -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=128 -CONFIG_MM_REGIONS=2 -CONFIG_MQ_MAXMSGSIZE=64 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_MAXARGUMENTS=17 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_WAITPID=y -CONFIG_SPI_CMDDATA=y -CONFIG_START_DAY=15 -CONFIG_START_MONTH=11 -CONFIG_START_YEAR=2017 -CONFIG_STM32F429I_DISCO_ILI9341=y -CONFIG_STM32_CCMEXCLUDE=y -CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32_DMA2D=y -CONFIG_STM32_DMA2D_FB_BASE=0xD07B5000 -CONFIG_STM32_DMA2D_FB_SIZE=307200 -CONFIG_STM32_DMA2D_LAYER_PPLINE=240 -CONFIG_STM32_DMA2D_NLAYERS=2 -CONFIG_STM32_EXTERNAL_RAM=y -CONFIG_STM32_FMC=y -CONFIG_STM32_I2C3=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_LTDC=y -CONFIG_STM32_LTDC_FB_BASE=0xD076A000 -CONFIG_STM32_LTDC_FB_SIZE=307200 -CONFIG_STM32_PWR=y -CONFIG_STM32_SPI5=y -CONFIG_STM32_USART1=y -CONFIG_STMPE811_ACTIVELOW=y -CONFIG_STMPE811_EDGE=y -CONFIG_STMPE811_THRESHX=39 -CONFIG_STMPE811_THRESHY=51 -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART1_SERIAL_CONSOLE=y -CONFIG_VIDEO_FB=y diff --git a/boards/arm/stm32/stm32f429i-disco/configs/gdbstub/defconfig b/boards/arm/stm32/stm32f429i-disco/configs/gdbstub/defconfig deleted file mode 100644 index a2ae14866f206..0000000000000 --- a/boards/arm/stm32/stm32f429i-disco/configs/gdbstub/defconfig +++ /dev/null @@ -1,58 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_LIBC_FLOATINGPOINT is not set -# CONFIG_NSH_DISABLE_MW is not set -# CONFIG_STM32_FLASH_PREFETCH is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f429i-disco" -CONFIG_ARCH_BOARD_STM32F429I_DISCO=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F429Z=y -CONFIG_ARCH_INTERRUPTSTACK=4096 -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_DEBUG_FEATURES=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_FS_PROCFS=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_HEAP2_BASE=0xD0000000 -CONFIG_HEAP2_SIZE=8388608 -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LIB_GDBSTUB=y -CONFIG_LIB_GDBSTUB_DEBUG=y -CONFIG_LINE_MAX=64 -CONFIG_MM_REGIONS=3 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_SERIAL_GDBSTUB=y -CONFIG_SPI=y -CONFIG_START_DAY=6 -CONFIG_START_MONTH=12 -CONFIG_START_YEAR=2011 -CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32_EXTERNAL_RAM=y -CONFIG_STM32_FMC=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_PWR=y -CONFIG_STM32_USART1=y -CONFIG_STM32_USART3=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/stm32f429i-disco/configs/highpri/defconfig b/boards/arm/stm32/stm32f429i-disco/configs/highpri/defconfig deleted file mode 100644 index d8fe5c1b7d90b..0000000000000 --- a/boards/arm/stm32/stm32f429i-disco/configs/highpri/defconfig +++ /dev/null @@ -1,59 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_STM32_FLASH_PREFETCH is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f429i-disco" -CONFIG_ARCH_BOARD_STM32F429I_DISCO=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F429Z=y -CONFIG_ARCH_HIPRI_INTERRUPT=y -CONFIG_ARCH_RAMVECTORS=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_DEBUG_NOOPT=y -CONFIG_HAVE_CXX=y -CONFIG_HEAP2_BASE=0xD0000000 -CONFIG_HEAP2_SIZE=8388608 -CONFIG_INIT_ENTRYPOINT="highpri_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LIBM=y -CONFIG_MM_REGIONS=2 -CONFIG_PREALLOC_TIMERS=4 -CONFIG_PWM=y -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=6 -CONFIG_START_MONTH=12 -CONFIG_START_YEAR=2011 -CONFIG_STM32F429I_DISCO_HIGHPRI=y -CONFIG_STM32_ADC1=y -CONFIG_STM32_ADC1_DMA=y -CONFIG_STM32_ADC1_DMA_CFG=1 -CONFIG_STM32_ADC1_EXTSEL=y -CONFIG_STM32_ADC1_INJECTED_CHAN=1 -CONFIG_STM32_ADC_LL_OPS=y -CONFIG_STM32_ADC_NOIRQ=y -CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32_DMA2=y -CONFIG_STM32_EXTERNAL_RAM=y -CONFIG_STM32_FMC=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_PWM_LL_OPS=y -CONFIG_STM32_PWR=y -CONFIG_STM32_TIM1=y -CONFIG_STM32_TIM1_PWM=y -CONFIG_STM32_USART1=y -CONFIG_SYSTEM_READLINE=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/stm32f429i-disco/configs/lcd/defconfig b/boards/arm/stm32/stm32f429i-disco/configs/lcd/defconfig deleted file mode 100644 index 55ff0bb5b9f95..0000000000000 --- a/boards/arm/stm32/stm32f429i-disco/configs/lcd/defconfig +++ /dev/null @@ -1,65 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_NXFONTS_DISABLE_16BPP is not set -# CONFIG_NX_DISABLE_16BPP is not set -# CONFIG_STM32_FLASH_PREFETCH is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f429i-disco" -CONFIG_ARCH_BOARD_STM32F429I_DISCO=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F429Z=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_DEBUG_CUSTOMOPT=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_EXAMPLES_NX=y -CONFIG_EXAMPLES_NX_BPP=16 -CONFIG_FS_PROCFS=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_HEAP2_BASE=0xD0000000 -CONFIG_HEAP2_SIZE=8388608 -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LCD=y -CONFIG_LCD_ILI9341=y -CONFIG_LCD_ILI9341_IFACE0=y -CONFIG_LINE_MAX=64 -CONFIG_MM_REGIONS=3 -CONFIG_MQ_MAXMSGSIZE=64 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_NX=y -CONFIG_NXFONT_MONO5X8=y -CONFIG_NX_BLOCKING=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=6 -CONFIG_START_MONTH=12 -CONFIG_START_YEAR=2011 -CONFIG_STM32F429I_DISCO_ILI9341=y -CONFIG_STM32F429I_DISCO_ILI9341_SPIBITS16=y -CONFIG_STM32F429I_DISCO_ILI9341_SPIFREQUENCY=20000000 -CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32_EXTERNAL_RAM=y -CONFIG_STM32_FMC=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_PWR=y -CONFIG_STM32_USART1=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/stm32f429i-disco/configs/lvgl/defconfig b/boards/arm/stm32/stm32f429i-disco/configs/lvgl/defconfig deleted file mode 100644 index d4b2f40ad717c..0000000000000 --- a/boards/arm/stm32/stm32f429i-disco/configs/lvgl/defconfig +++ /dev/null @@ -1,83 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_LV_BUILD_EXAMPLES is not set -# CONFIG_STM32_FB_CMAP is not set -# CONFIG_STM32_FLASH_PREFETCH is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f429i-disco" -CONFIG_ARCH_BOARD_STM32F429I_DISCO=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F429Z=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_DEBUG_CUSTOMOPT=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_DRIVERS_VIDEO=y -CONFIG_EXAMPLES_FB=y -CONFIG_EXAMPLES_LVGLDEMO=y -CONFIG_EXAMPLES_TOUCHSCREEN=y -CONFIG_FB_OVERLAY=y -CONFIG_FS_PROCFS=y -CONFIG_GRAPHICS_LVGL=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_HEAP2_BASE=0xD0000000 -CONFIG_HEAP2_SIZE=8081408 -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INPUT=y -CONFIG_INPUT_STMPE811=y -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_LV_USE_CLIB_MALLOC=y -CONFIG_LV_USE_CLIB_SPRINTF=y -CONFIG_LV_USE_CLIB_STRING=y -CONFIG_LV_USE_DEMO_WIDGETS=y -CONFIG_LV_USE_LOG=y -CONFIG_LV_USE_NUTTX=y -CONFIG_LV_USE_NUTTX_TOUCHSCREEN=y -CONFIG_MM_REGIONS=2 -CONFIG_MQ_MAXMSGSIZE=64 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_WAITPID=y -CONFIG_SPI_CMDDATA=y -CONFIG_START_DAY=15 -CONFIG_START_MONTH=11 -CONFIG_START_YEAR=2017 -CONFIG_STM32F429I_DISCO_ILI9341=y -CONFIG_STM32_CCMEXCLUDE=y -CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32_EXTERNAL_RAM=y -CONFIG_STM32_FMC=y -CONFIG_STM32_I2C3=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_LTDC=y -CONFIG_STM32_LTDC_FB_BASE=0xD07B5000 -CONFIG_STM32_LTDC_FB_SIZE=307200 -CONFIG_STM32_PWR=y -CONFIG_STM32_SPI5=y -CONFIG_STM32_USART1=y -CONFIG_STMPE811_ACTIVELOW=y -CONFIG_STMPE811_EDGE=y -CONFIG_STMPE811_THRESHX=39 -CONFIG_STMPE811_THRESHY=51 -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART1_SERIAL_CONSOLE=y -CONFIG_VIDEO_FB=y diff --git a/boards/arm/stm32/stm32f429i-disco/configs/nsh/defconfig b/boards/arm/stm32/stm32f429i-disco/configs/nsh/defconfig deleted file mode 100644 index 1b17784c3aac4..0000000000000 --- a/boards/arm/stm32/stm32f429i-disco/configs/nsh/defconfig +++ /dev/null @@ -1,51 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_STM32_FLASH_PREFETCH is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f429i-disco" -CONFIG_ARCH_BOARD_STM32F429I_DISCO=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F429Z=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_FS_PROCFS=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_HEAP2_BASE=0xD0000000 -CONFIG_HEAP2_SIZE=8388608 -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_MM_REGIONS=3 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_SPI=y -CONFIG_START_DAY=6 -CONFIG_START_MONTH=12 -CONFIG_START_YEAR=2011 -CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32_EXTERNAL_RAM=y -CONFIG_STM32_FMC=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_PWR=y -CONFIG_STM32_USART1=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/stm32f429i-disco/configs/nxhello/defconfig b/boards/arm/stm32/stm32f429i-disco/configs/nxhello/defconfig deleted file mode 100644 index fc3c836a06499..0000000000000 --- a/boards/arm/stm32/stm32f429i-disco/configs/nxhello/defconfig +++ /dev/null @@ -1,75 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_ARCH_LEDS is not set -# CONFIG_NXFONTS_DISABLE_16BPP is not set -# CONFIG_NX_DISABLE_16BPP is not set -# CONFIG_STM32_FB_CMAP is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f429i-disco" -CONFIG_ARCH_BOARD_STM32F429I_DISCO=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F429Z=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_DEV_LOOP=y -CONFIG_DRIVERS_VIDEO=y -CONFIG_EXAMPLES_NXHELLO=y -CONFIG_EXAMPLES_NXHELLO_BPP=16 -CONFIG_EXAMPLES_NXHELLO_SERVERPRIO=110 -CONFIG_FS_PROCFS=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_HEAP2_BASE=0xD0000000 -CONFIG_HEAP2_SIZE=8388608 -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LIBC_MAX_EXITFUNS=1 -CONFIG_LINE_MAX=64 -CONFIG_MM_REGIONS=3 -CONFIG_MQ_MAXMSGSIZE=64 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_NX=y -CONFIG_NXFONT_SANS22X29B=y -CONFIG_NX_BLOCKING=y -CONFIG_NX_WRITEONLY=y -CONFIG_NX_XYINPUT_TOUCHSCREEN=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=214688 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=7 -CONFIG_START_MONTH=2 -CONFIG_START_YEAR=2019 -CONFIG_STM32F429I_DISCO_ILI9341=y -CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32_DMA2D=y -CONFIG_STM32_DMA2D_FB_BASE=0xD07B5000 -CONFIG_STM32_DMA2D_FB_SIZE=307200 -CONFIG_STM32_DMA2D_LAYER_PPLINE=240 -CONFIG_STM32_DMA2D_NLAYERS=2 -CONFIG_STM32_EXTERNAL_RAM=y -CONFIG_STM32_FMC=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_LTDC=y -CONFIG_STM32_LTDC_FB_BASE=0xD076A000 -CONFIG_STM32_LTDC_FB_SIZE=307200 -CONFIG_STM32_PWR=y -CONFIG_STM32_USART1=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART1_SERIAL_CONSOLE=y -CONFIG_VIDEO_FB=y diff --git a/boards/arm/stm32/stm32f429i-disco/configs/nxwm/defconfig b/boards/arm/stm32/stm32f429i-disco/configs/nxwm/defconfig deleted file mode 100644 index 819fa8d7df831..0000000000000 --- a/boards/arm/stm32/stm32f429i-disco/configs/nxwm/defconfig +++ /dev/null @@ -1,111 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_NXFONTS_DISABLE_16BPP is not set -# CONFIG_NXTK_DEFAULT_BORDERCOLORS is not set -# CONFIG_NX_DISABLE_16BPP is not set -# CONFIG_STM32_FLASH_PREFETCH is not set -# CONFIG_STM32_LTDC_L2 is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f429i-disco" -CONFIG_ARCH_BOARD_STM32F429I_DISCO=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F429Z=y -CONFIG_ARCH_INTERRUPTSTACK=2048 -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_DEBUG_CUSTOMOPT=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_DRIVERS_VIDEO=y -CONFIG_FAT_LCNAMES=y -CONFIG_FAT_LFN=y -CONFIG_FB_OVERLAY=y -CONFIG_FS_FAT=y -CONFIG_FS_PROCFS=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_HEAP2_BASE=0xd0000000 -CONFIG_HEAP2_SIZE=8081408 -CONFIG_INIT_ENTRYPOINT="nxwm_main" -CONFIG_INPUT=y -CONFIG_INPUT_STMPE811=y -CONFIG_INTELHEX_BINARY=y -CONFIG_LIBC_MAX_EXITFUNS=1 -CONFIG_LINE_MAX=64 -CONFIG_MM_REGIONS=2 -CONFIG_MQ_MAXMSGSIZE=64 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_LIBRARY=y -CONFIG_NSH_READLINE=y -CONFIG_NX=y -CONFIG_NXFONT_SANS22X29B=y -CONFIG_NXFONT_SANS23X27=y -CONFIG_NXTERM=y -CONFIG_NXTERM_CACHESIZE=32 -CONFIG_NXTERM_CURSORCHAR=95 -CONFIG_NXTERM_MXCHARS=325 -CONFIG_NXTERM_NXKBDIN=y -CONFIG_NXTK_BORDERCOLOR1=0x5cb7 -CONFIG_NXTK_BORDERCOLOR2=0x21c9 -CONFIG_NXTK_BORDERCOLOR3=0xffdf -CONFIG_NXWIDGETS=y -CONFIG_NXWIDGETS_BPP=16 -CONFIG_NXWIDGETS_CUSTOM_EDGECOLORS=y -CONFIG_NXWIDGETS_CUSTOM_FILLCOLORS=y -CONFIG_NXWIDGETS_DEFAULT_BACKGROUNDCOLOR=0x9dfb -CONFIG_NXWIDGETS_DEFAULT_HIGHLIGHTCOLOR=0xc618 -CONFIG_NXWIDGETS_DEFAULT_SELECTEDBACKGROUNDCOLOR=0xd73e -CONFIG_NXWIDGETS_DEFAULT_SHADOWEDGECOLOR=0x21e9 -CONFIG_NXWIDGETS_DEFAULT_SHINEEDGECOLOR=0xffdf -CONFIG_NXWIDGETS_SIZEOFCHAR=1 -CONFIG_NXWM=y -CONFIG_NXWM_CALIBRATION_AVERAGE=y -CONFIG_NXWM_CALIBRATION_MESSAGES=y -CONFIG_NXWM_CALIBRATION_NSAMPLES=2 -CONFIG_NXWM_HEXCALCULATOR_CUSTOM_FONTID=y -CONFIG_NXWM_HEXCALCULATOR_FONTID=5 -CONFIG_NXWM_KEYBOARD=y -CONFIG_NXWM_TASKBAR_LEFT=y -CONFIG_NXWM_TASKBAR_VSPACING=4 -CONFIG_NXWM_TOUCHSCREEN_LISTENERSTACK=1596 -CONFIG_NX_BLOCKING=y -CONFIG_NX_KBD=y -CONFIG_NX_XYINPUT_TOUCHSCREEN=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_HPWORKPRIORITY=192 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=15 -CONFIG_START_MONTH=11 -CONFIG_STM32F429I_DISCO_ILI9341=y -CONFIG_STM32_CCMEXCLUDE=y -CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32_EXTERNAL_RAM=y -CONFIG_STM32_FMC=y -CONFIG_STM32_I2C3=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_LTDC=y -CONFIG_STM32_LTDC_FB_BASE=0xD07B5000 -CONFIG_STM32_LTDC_FB_SIZE=307200 -CONFIG_STM32_PWR=y -CONFIG_STM32_USART1=y -CONFIG_STMPE811_ACTIVELOW=y -CONFIG_STMPE811_EDGE=y -CONFIG_STMPE811_THRESHX=39 -CONFIG_STMPE811_THRESHY=51 -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART1_SERIAL_CONSOLE=y -CONFIG_VIDEO_FB=y diff --git a/boards/arm/stm32/stm32f429i-disco/configs/ofloader/defconfig b/boards/arm/stm32/stm32f429i-disco/configs/ofloader/defconfig deleted file mode 100644 index e0d8d16cb0f9e..0000000000000 --- a/boards/arm/stm32/stm32f429i-disco/configs/ofloader/defconfig +++ /dev/null @@ -1,56 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_STM32_FLASH_PREFETCH is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f429i-disco" -CONFIG_ARCH_BOARD_STM32F429I_DISCO=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F429Z=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BCH=y -CONFIG_BOARDCTL=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_DEBUG_FULLOPT=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_DRVR_MKRD=y -CONFIG_FRAME_POINTER=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_HEAP2_BASE=0xD0000000 -CONFIG_HEAP2_SIZE=8388608 -CONFIG_INIT_ENTRYNAME="ofloader" -CONFIG_INIT_ENTRYPOINT="ofloader_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_MM_REGIONS=3 -CONFIG_MTD=y -CONFIG_MTD_PROGMEM=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=6 -CONFIG_START_MONTH=12 -CONFIG_START_YEAR=2011 -CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32_EXTERNAL_RAM=y -CONFIG_STM32_FLASH_CONFIG_I=y -CONFIG_STM32_FMC=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_USART1=y -CONFIG_SYSTEM_OFLOADER=y -CONFIG_SYSTEM_OFLOADER_BUFFERSIZE=4096 -CONFIG_SYSTEM_OFLOADER_DEBUG=y -CONFIG_SYSTEM_OFLOADER_TABLE="/dev/flash,0x08000000,0x20000" -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/stm32f429i-disco/configs/stack/defconfig b/boards/arm/stm32/stm32f429i-disco/configs/stack/defconfig deleted file mode 100644 index 03a81bfa4c32a..0000000000000 --- a/boards/arm/stm32/stm32f429i-disco/configs/stack/defconfig +++ /dev/null @@ -1,56 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_STM32_FLASH_PREFETCH is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f429i-disco" -CONFIG_ARCH_BOARD_STM32F429I_DISCO=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F429Z=y -CONFIG_ARCH_INSTRUMENT_ALL=y -CONFIG_ARCH_INTERRUPTSTACK=4096 -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_DEBUG_FULLOPT=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_FS_PROCFS=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_HEAP2_BASE=0xD0000000 -CONFIG_HEAP2_SIZE=8388608 -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_MM_REGIONS=3 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_BACKTRACE=y -CONFIG_SCHED_STACK_RECORD=32 -CONFIG_SCHED_WAITPID=y -CONFIG_SPI=y -CONFIG_START_DAY=6 -CONFIG_START_MONTH=12 -CONFIG_START_YEAR=2011 -CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32_EXTERNAL_RAM=y -CONFIG_STM32_FMC=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_PWR=y -CONFIG_STM32_USART1=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/stm32f429i-disco/configs/systemview/defconfig b/boards/arm/stm32/stm32f429i-disco/configs/systemview/defconfig deleted file mode 100644 index 2500bae8c273c..0000000000000 --- a/boards/arm/stm32/stm32f429i-disco/configs/systemview/defconfig +++ /dev/null @@ -1,67 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_DRIVERS_NOTERAM is not set -# CONFIG_SERIAL_RTT_CONSOLE is not set -# CONFIG_STANDARD_SERIAL is not set -# CONFIG_STM32_FLASH_PREFETCH is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f429i-disco" -CONFIG_ARCH_BOARD_STM32F429I_DISCO=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F429Z=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_DRIVERS_NOTE=y -CONFIG_DRIVERS_NOTE_TASKNAME_BUFSIZE=0 -CONFIG_EXAMPLES_NOTEPRINTF=y -CONFIG_FS_PROCFS=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_HEAP2_BASE=0xD0000000 -CONFIG_HEAP2_SIZE=8388608 -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_MM_REGIONS=3 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_INSTRUMENTATION=y -CONFIG_SCHED_INSTRUMENTATION_DUMP=y -CONFIG_SCHED_INSTRUMENTATION_HEAP=y -CONFIG_SCHED_INSTRUMENTATION_IRQHANDLER=y -CONFIG_SCHED_INSTRUMENTATION_SWITCH=y -CONFIG_SCHED_INSTRUMENTATION_WDOG=y -CONFIG_SEGGER_SYSVIEW=y -CONFIG_SERIAL_RTT0=y -CONFIG_SPI=y -CONFIG_START_DAY=6 -CONFIG_START_MONTH=12 -CONFIG_START_YEAR=2011 -CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32_EXTERNAL_RAM=y -CONFIG_STM32_FMC=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_PWR=y -CONFIG_STM32_USART1=y -CONFIG_SYSLOG_CHAR=y -CONFIG_SYSLOG_RTT=y -CONFIG_SYSTEM_NSH=y -CONFIG_SYSTEM_SYSTEM=y -CONFIG_TASK_NAME_SIZE=16 -CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/stm32f429i-disco/configs/usbmsc/defconfig b/boards/arm/stm32/stm32f429i-disco/configs/usbmsc/defconfig deleted file mode 100644 index 03447b3fac8b1..0000000000000 --- a/boards/arm/stm32/stm32f429i-disco/configs/usbmsc/defconfig +++ /dev/null @@ -1,57 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_STM32_FLASH_PREFETCH is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f429i-disco" -CONFIG_ARCH_BOARD_STM32F429I_DISCO=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F429Z=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_FS_FAT=y -CONFIG_FS_PROCFS=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_HEAP2_BASE=0xD0000000 -CONFIG_HEAP2_SIZE=8388608 -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_MM_REGIONS=3 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_HPWORKPRIORITY=192 -CONFIG_SCHED_WAITPID=y -CONFIG_SPI=y -CONFIG_START_DAY=6 -CONFIG_START_MONTH=12 -CONFIG_START_YEAR=2011 -CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32_EXTERNAL_RAM=y -CONFIG_STM32_FMC=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_OTGHS=y -CONFIG_STM32_PWR=y -CONFIG_STM32_USART1=y -CONFIG_STM32_USBHOST=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART1_SERIAL_CONSOLE=y -CONFIG_USBHOST_MSC=y diff --git a/boards/arm/stm32/stm32f429i-disco/configs/usbnsh/defconfig b/boards/arm/stm32/stm32f429i-disco/configs/usbnsh/defconfig deleted file mode 100644 index 7246fb6ffad44..0000000000000 --- a/boards/arm/stm32/stm32f429i-disco/configs/usbnsh/defconfig +++ /dev/null @@ -1,61 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_DEV_CONSOLE is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f429i-disco" -CONFIG_ARCH_BOARD_STM32F429I_DISCO=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F429Z=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARDCTL_USBDEVCTRL=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_CDCACM=y -CONFIG_CDCACM_CONSOLE=y -CONFIG_CDCACM_RXBUFSIZE=256 -CONFIG_CDCACM_TXBUFSIZE=256 -CONFIG_DEV_LOOP=y -CONFIG_FS_FAT=y -CONFIG_FS_PROCFS=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_HEAP2_BASE=0xD0000000 -CONFIG_HEAP2_SIZE=8388608 -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LIBC_PERROR_STDOUT=y -CONFIG_LIBC_STRERROR=y -CONFIG_LINE_MAX=64 -CONFIG_MM_REGIONS=3 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_SPI=y -CONFIG_START_DAY=6 -CONFIG_START_MONTH=12 -CONFIG_START_YEAR=2011 -CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32_EXTERNAL_RAM=y -CONFIG_STM32_FMC=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_OTGHS=y -CONFIG_STM32_PWR=y -CONFIG_STM32_USART1=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_TESTING_RAMTEST=y -CONFIG_USBDEV=y diff --git a/boards/arm/stm32/stm32f429i-disco/include/board.h b/boards/arm/stm32/stm32f429i-disco/include/board.h deleted file mode 100644 index 2bb3b57f0cf6e..0000000000000 --- a/boards/arm/stm32/stm32f429i-disco/include/board.h +++ /dev/null @@ -1,540 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f429i-disco/include/board.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __BOARDS_ARM_STM32_STM32F429I_DISCO_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32_STM32F429I_DISCO_INCLUDE_BOARD_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#ifndef __ASSEMBLY__ -# include -#endif - -/* DO NOT include STM32 internal header files here */ - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Clocking *****************************************************************/ - -/* The STM32F429I-DISCO board features a single 8MHz crystal. - * Space is provided for a 32kHz RTC backup crystal, but it is not stuffed. - * - * This is the canonical configuration: - * System Clock source : PLL (HSE) - * SYSCLK(Hz) : 180000000 Determined by PLL - * configuration - * HCLK(Hz) : 180000000 (STM32_RCC_CFGR_HPRE) - * AHB Prescaler : 1 (STM32_RCC_CFGR_HPRE) - * APB1 Prescaler : 4 (STM32_RCC_CFGR_PPRE1) - * APB2 Prescaler : 2 (STM32_RCC_CFGR_PPRE2) - * HSE Frequency(Hz) : 8000000 (STM32_BOARD_XTAL) - * PLLM : 8 (STM32_PLLCFG_PLLM) - * PLLN : 336 (STM32_PLLCFG_PLLN) - * PLLP : 2 (STM32_PLLCFG_PLLP) - * PLLQ : 7 (STM32_PLLCFG_PLLQ) - * Main regulator output voltage : Scale1 mode Needed for high speed - * SYSCLK - * Flash Latency(WS) : 5 - * Prefetch Buffer : OFF - * Instruction cache : ON - * Data cache : ON - * Require 48MHz for USB OTG FS, : Enabled - * SDIO and RNG clock - */ - -/* HSI - 16 MHz RC factory-trimmed - * LSI - 32 KHz RC - * HSE - On-board crystal frequency is 8MHz - * LSE - 32.768 kHz - */ - -#define STM32_BOARD_XTAL 8000000ul - -#define STM32_HSI_FREQUENCY 16000000ul -#define STM32_LSI_FREQUENCY 32000 -#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL -#define STM32_LSE_FREQUENCY 32768 - -/* Main PLL Configuration. - * - * PLL source is HSE - * PLL_VCO = (STM32_HSE_FREQUENCY / PLLM) * PLLN - * = (8,000,000 / 8) * 336 - * = 336,000,000 - * SYSCLK = PLL_VCO / PLLP - * = 336,000,000 / 2 = 168,000,000 - * USB OTG FS, SDIO and RNG Clock - * = PLL_VCO / PLLQ - * = 48,000,000 - */ - -#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(8) -#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(336) -#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_2 -#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(7) - -#define STM32_SYSCLK_FREQUENCY 168000000ul - -/* AHB clock (HCLK) is SYSCLK (168MHz) */ - -#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ -#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY - -/* APB1 clock (PCLK1) is HCLK/4 (42MHz) */ - -#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd4 /* PCLK1 = HCLK / 4 */ -#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/4) - -/* Timers driven from APB1 will be twice PCLK1 */ - -#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) - -/* APB2 clock (PCLK2) is HCLK/2 (84MHz) */ - -#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLKd2 /* PCLK2 = HCLK / 2 */ -#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/2) - -/* Timers driven from APB2 will be twice PCLK2 */ - -#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM9_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM10_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM11_CLKIN (2*STM32_PCLK2_FREQUENCY) - -/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx - * otherwise frequency is 2xAPBx. - * Note: TIM1,8 are on APB2, others on APB1 - */ - -#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM2_FREQUENCY (STM32_HCLK_FREQUENCY/2) -#define BOARD_TIM3_FREQUENCY (STM32_HCLK_FREQUENCY/2) -#define BOARD_TIM4_FREQUENCY (STM32_HCLK_FREQUENCY/2) -#define BOARD_TIM5_FREQUENCY (STM32_HCLK_FREQUENCY/2) -#define BOARD_TIM6_FREQUENCY (STM32_HCLK_FREQUENCY/2) -#define BOARD_TIM7_FREQUENCY (STM32_HCLK_FREQUENCY/2) -#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY - -/* LED definitions **********************************************************/ - -/* If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs in - * any way. The following definitions are used to access individual LEDs. - */ - -/* LED index values for use with board_userled() */ - -#define BOARD_LED1 0 -#define BOARD_LED2 1 -#define BOARD_NLEDS 2 - -#define BOARD_LED_GREEN BOARD_LED1 -#define BOARD_LED_ORANGE BOARD_LED2 - -/* LED bits for use with board_userled_all() */ - -#define BOARD_LED1_BIT (1 << BOARD_LED1) -#define BOARD_LED2_BIT (1 << BOARD_LED2) - -/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the 4 LEDs on - * board the stm32f429i-disco. - * The following definitions describe how NuttX controls the LEDs: - */ - -#define LED_STARTED 0 /* LED1 */ -#define LED_HEAPALLOCATE 1 /* LED2 */ -#define LED_IRQSENABLED 2 /* LED1 + LED2 */ -#define LED_STACKCREATED 3 /* LED3 */ -#define LED_INIRQ 4 /* LED1 + LED3 */ -#define LED_SIGNAL 5 /* LED2 + LED3 */ -#define LED_ASSERTION 6 /* LED1 + LED2 + LED3 */ -#define LED_PANIC 7 /* N/C + N/C + N/C + LED4 */ - -/* Button definitions *******************************************************/ - -/* The STM32F429I-DISCO supports one button: */ - -#define BUTTON_USER 0 - -#define NUM_BUTTONS 1 - -#define BUTTON_USER_BIT (1 << BUTTON_USER) - -/* Alternate function pin selections ****************************************/ - -/* USART1: - * - * The STM32F429I-DISCO has no on-board serial devices, but the console is - * brought out to PA9 (TX) and PA10 (RX) for connection to an external serial - * device. - */ - -#define GPIO_USART1_RX (GPIO_USART1_RX_1|GPIO_SPEED_100MHz) -#define GPIO_USART1_TX (GPIO_USART1_TX_1|GPIO_SPEED_100MHz) - -#define GPIO_USART3_RX (GPIO_USART3_RX_1|GPIO_SPEED_100MHz) -#define GPIO_USART3_TX (GPIO_USART3_TX_1|GPIO_SPEED_100MHz) - -/* CAN: */ - -#define GPIO_CAN1_RX (GPIO_CAN1_RX_2|GPIO_SPEED_50MHz) -#define GPIO_CAN1_TX (GPIO_CAN1_TX_2|GPIO_SPEED_50MHz) - -/* PWM - * - * The STM32F429I-DISCO has no real on-board PWM devices, but the board can - * be configured to output a pulse train using TIM4 CH2 on PD13. - */ - -#define GPIO_TIM4_CH2OUT (GPIO_TIM4_CH2OUT_2|GPIO_SPEED_50MHz) - -#define GPIO_TIM1_CH1OUT (GPIO_TIM1_CH1OUT_2|GPIO_SPEED_50MHz) /* PE9 */ -#define GPIO_TIM1_CH1NOUT GPIO_TIM1_CH1N_3 /* PE8 */ -#define GPIO_TIM1_CH2OUT (GPIO_TIM1_CH2OUT_2|GPIO_SPEED_50MHz) /* PE11 */ -#define GPIO_TIM1_CH2NOUT GPIO_TIM1_CH2N_3 /* PE10 */ -#define GPIO_TIM1_CH3OUT (GPIO_TIM1_CH3OUT_2|GPIO_SPEED_50MHz) /* PE13 */ -#define GPIO_TIM1_CH3NOUT GPIO_TIM1_CH3N_3 /* PE12 */ - -/* I2C - There is a STMPE811 TouchPanel on I2C3 using these pins: */ - -#define GPIO_I2C3_SCL (GPIO_I2C3_SCL_1|GPIO_SPEED_50MHz) -#define GPIO_I2C3_SDA (GPIO_I2C3_SDA_1|GPIO_SPEED_50MHz) - -/* SPI - There is a MEMS device on SPI5 using these pins: */ - -#define GPIO_SPI5_MISO (GPIO_SPI5_MISO_1|GPIO_SPEED_50MHz) -#define GPIO_SPI5_MOSI (GPIO_SPI5_MOSI_1|GPIO_SPEED_50MHz) -#define GPIO_SPI5_SCK (GPIO_SPI5_SCK_1|GPIO_SPEED_50MHz) - -/* SPI - External SPI flash may be connected on SPI4: */ - -#define GPIO_SPI4_MISO (GPIO_SPI4_MISO_1|GPIO_SPEED_50MHz) -#define GPIO_SPI4_MOSI (GPIO_SPI4_MOSI_1|GPIO_SPEED_50MHz) -#define GPIO_SPI4_SCK (GPIO_SPI4_SCK_1|GPIO_SPEED_50MHz) - -/* FMC - SDRAM */ - -#define GPIO_FMC_SDCKE1 (GPIO_FMC_SDCKE1_1|GPIO_SPEED_100MHz) -#define GPIO_FMC_SDNE1 (GPIO_FMC_SDNE1_1|GPIO_SPEED_100MHz) -#define GPIO_FMC_SDNWE (GPIO_FMC_SDNWE_1|GPIO_SPEED_100MHz) - -/* Timer Inputs/Outputs */ - -#define GPIO_TIM2_CH1IN (GPIO_TIM2_CH1IN_2|GPIO_SPEED_50MHz) -#define GPIO_TIM2_CH2IN (GPIO_TIM2_CH2IN_1|GPIO_SPEED_50MHz) - -#define GPIO_TIM8_CH1IN (GPIO_TIM8_CH1IN_1|GPIO_SPEED_50MHz) -#define GPIO_TIM8_CH2IN (GPIO_TIM8_CH2IN_1|GPIO_SPEED_50MHz) - -#ifdef CONFIG_STM32_LTDC -# ifdef CONFIG_STM32F429I_DISCO_ILI9341_FBIFACE - -/* LCD - * - * The STM32F429I-DISCO board contains an onboard TFT LCD connected to the - * LTDC interface of the uC. - * The LCD is 240x320 pixels. - * Define the parameters of the LCD and the interface here. - */ - -/* Panel configuration - * - * LCD Panel is Saef Technology Limited (SF-TC240T-9229A2-T) with integrated - * Ilitek ILI9341 LCD Single Chip Driver (240RGBx320) - * - * PLLSAI settings - * PLLSAIN : 192 - * PLLSAIR : 4 - * PLLSAIQ : 7 - * PLLSAIDIVR : 8 - * - * Timings - * Horizontal Front Porch : 10 (STM32_LTDC_HFP) - * Horizontal Back Porch : 20 (STM32_LTDC_HBP) - * Vertical Front Porch : 4 (STM32_LTDC_VFP) - * Vertical Back Porch : 2 (STM32_LTDC_VBP) - * - * Horizontal Sync : 10 (STM32_LTDC_HSYNC) - * Vertical Sync : 4 (STM32_LTDC_VSYNC) - * - * Active Width : 240 (STM32_LTDC_ACTIVEW) - * Active Height : 320 (STM32_LTDC_ACTIVEH) - */ - -/* LTDC PLL configuration - * - * PLLSAI_VCO = STM32_HSE_FREQUENCY / PLLM - * = 8000000ul / 8 - * = 1,000,000 - * - * PLL LCD clock output - * = PLLSAI_VCO * PLLSAIN / PLLSAIR / PLLSAIDIVR - * = 1,000,000 * 192 / 4 /8 - * = 6,000,000 - */ - -/* Defined panel settings */ - -#if defined(CONFIG_STM32F429I_DISCO_ILI9341_FBIFACE_LANDSCAPE) || \ - defined(CONFIG_STM32F429I_DISCO_ILI9341_FBIFACE_RLANDSCAPE) -# define BOARD_LTDC_WIDTH 320 -# define BOARD_LTDC_HEIGHT 240 -#else -# define BOARD_LTDC_WIDTH 240 -# define BOARD_LTDC_HEIGHT 320 -#endif - -#define BOARD_LTDC_OUTPUT_BPP 16 -#define BOARD_LTDC_HFP 10 -#define BOARD_LTDC_HBP 20 -#define BOARD_LTDC_VFP 4 -#define BOARD_LTDC_VBP 2 -#define BOARD_LTDC_HSYNC 10 -#define BOARD_LTDC_VSYNC 2 - -#define BOARD_LTDC_PLLSAIN 192 -#define BOARD_LTDC_PLLSAIR 4 -#define BOARD_LTDC_PLLSAIQ 7 - -/* Division factor for LCD clock */ - -#define STM32_RCC_DCKCFGR_PLLSAIDIVR RCC_DCKCFGR_PLLSAIDIVR_DIV8 - -/* Pixel Clock Polarity */ - -#define BOARD_LTDC_GCR_PCPOL 0 /* !LTDC_GCR_PCPOL */ - -/* Data Enable Polarity */ - -#define BOARD_LTDC_GCR_DEPOL 0 /* !LTDC_GCR_DEPOL */ - -/* Vertical Sync Polarity */ - -#define BOARD_LTDC_GCR_VSPOL 0 /* !LTDC_GCR_VSPOL */ - -/* Horizontal Sync Polarity */ - -#define BOARD_LTDC_GCR_HSPOL 0 /* !LTDC_GCR_HSPOL */ - -/* GPIO pinset */ - -#define GPIO_LTDC_PINS 18 /* 18-bit display */ - -#define GPIO_LTDC_R2 (GPIO_LTDC_R2_1|GPIO_SPEED_100MHz) -#define GPIO_LTDC_R3 (GPIO_LTDC_R3_1|GPIO_SPEED_100MHz) -#define GPIO_LTDC_R4 (GPIO_LTDC_R4_1|GPIO_SPEED_100MHz) -#define GPIO_LTDC_R5 (GPIO_LTDC_R5_1|GPIO_SPEED_100MHz) -#define GPIO_LTDC_R6 (GPIO_LTDC_R6_1|GPIO_SPEED_100MHz) -#define GPIO_LTDC_R7 (GPIO_LTDC_R7_1|GPIO_SPEED_100MHz) - -#define GPIO_LTDC_G2 (GPIO_LTDC_G2_1|GPIO_SPEED_100MHz) -#define GPIO_LTDC_G3 (GPIO_LTDC_G3_1|GPIO_SPEED_100MHz) -#define GPIO_LTDC_G4 (GPIO_LTDC_G4_1|GPIO_SPEED_100MHz) -#define GPIO_LTDC_G5 (GPIO_LTDC_G5_1|GPIO_SPEED_100MHz) -#define GPIO_LTDC_G6 (GPIO_LTDC_G6_1|GPIO_SPEED_100MHz) -#define GPIO_LTDC_G7 (GPIO_LTDC_G7_1|GPIO_SPEED_100MHz) - -#define GPIO_LTDC_B2 (GPIO_LTDC_B2_1|GPIO_SPEED_100MHz) -#define GPIO_LTDC_B3 (GPIO_LTDC_B3_1|GPIO_SPEED_100MHz) -#define GPIO_LTDC_B4 (GPIO_LTDC_B4_1|GPIO_SPEED_100MHz) -#define GPIO_LTDC_B5 (GPIO_LTDC_B5_1|GPIO_SPEED_100MHz) -#define GPIO_LTDC_B6 (GPIO_LTDC_B6_1|GPIO_SPEED_100MHz) -#define GPIO_LTDC_B7 (GPIO_LTDC_B7_1|GPIO_SPEED_100MHz) - -#define GPIO_LTDC_VSYNC GPIO_LTDC_VSYNC_1 -#define GPIO_LTDC_HSYNC GPIO_LTDC_HSYNC_1 -#define GPIO_LTDC_DE (GPIO_LTDC_DE_1|GPIO_SPEED_100MHz) -#define GPIO_LTDC_CLK GPIO_LTDC_CLK_1 - -#else -/* Custom LCD display configuration */ - -# define BOARD_LTDC_WIDTH ??? -# define BOARD_LTDC_HEIGHT ??? - -#define BOARD_LTDC_HFP ??? -#define BOARD_LTDC_HBP ??? -#define BOARD_LTDC_VFP ??? -#define BOARD_LTDC_VBP ??? -#define BOARD_LTDC_HSYNC ??? -#define BOARD_LTDC_VSYNC ??? - -#define BOARD_LTDC_PLLSAIN ??? -#define BOARD_LTDC_PLLSAIR ??? -#define BOARD_LTDC_PLLSAIQ ??? - -/* Division factor for LCD clock */ - -#define STM32_RCC_DCKCFGR_PLLSAIDIVR ??? - -/* Pixel Clock Polarity */ - -#define BOARD_LTDC_GCR_PCPOL ??? - -/* Data Enable Polarity */ - -#define BOARD_LTDC_GCR_DEPOL ??? - -/* Vertical Sync Polarity */ - -#define BOARD_LTDC_GCR_VSPOL ??? - -/* Horizontal Sync Polarity */ - -#define BOARD_LTDC_GCR_HSPOL ??? - -/* GPIO pinset */ - -#define GPIO_LTDC_PINS ??? - -#define GPIO_LTDC_R2 ??? -#define GPIO_LTDC_R3 ??? -#define GPIO_LTDC_R4 ??? -#define GPIO_LTDC_R5 ??? -#define GPIO_LTDC_R6 ??? -#define GPIO_LTDC_R7 ??? - -#define GPIO_LTDC_G2 ??? -#define GPIO_LTDC_G3 ??? -#define GPIO_LTDC_G4 ??? -#define GPIO_LTDC_G5 ??? -#define GPIO_LTDC_G6 ??? -#define GPIO_LTDC_G7 ??? - -#define GPIO_LTDC_B2 ??? -#define GPIO_LTDC_B3 ??? -#define GPIO_LTDC_B4 ??? -#define GPIO_LTDC_B5 ??? -#define GPIO_LTDC_B6 ??? -#define GPIO_LTDC_B7 ??? - -#define GPIO_LTDC_VSYNC ??? -#define GPIO_LTDC_HSYNC ??? -#define GPIO_LTDC_DE ??? -#define GPIO_LTDC_CLK ??? - -#endif /* Custom LCD display */ - -/* Configure PLLSAI */ - -#define STM32_RCC_PLLSAICFGR_PLLSAIN RCC_PLLSAICFGR_PLLSAIN(BOARD_LTDC_PLLSAIN) -#define STM32_RCC_PLLSAICFGR_PLLSAIR RCC_PLLSAICFGR_PLLSAIR(BOARD_LTDC_PLLSAIR) -#define STM32_RCC_PLLSAICFGR_PLLSAIQ RCC_PLLSAICFGR_PLLSAIQ(BOARD_LTDC_PLLSAIQ) - -#endif /* CONFIG_STM32_LTDC */ - -/* L3GD20 MEMS */ - -#define GPIO_L3GD20_DREADY (GPIO_INPUT|GPIO_FLOAT|GPIO_EXTI|GPIO_PORTA|GPIO_PIN2) -#define L3GD20_IRQ (2 + STM32_IRQ_EXTI0) - -#define BOARD_L3GD20_GPIO_DREADY GPIO_L3GD20_DREADY -#define BOARD_L3GD20_IRQ L3GD20_IRQ - -#define GPIO_LIS3DSH_EXT0 \ - (GPIO_INPUT|GPIO_FLOAT|GPIO_AF0|GPIO_SPEED_50MHz|GPIO_PORTE|GPIO_PIN0) - -#define BOARD_LIS3DSH_GPIO_EXT0 GPIO_LIS3DSH_EXT0 - -/* DMA **********************************************************************/ - -#define ADC1_DMA_CHAN DMAMAP_ADC1_1 - -/* USB OTG FS / OTG HS */ - -#define GPIO_OTGFS_DM (GPIO_OTGFS_DM_0|GPIO_SPEED_100MHz) -#define GPIO_OTGFS_DP (GPIO_OTGFS_DP_0|GPIO_SPEED_100MHz) -#define GPIO_OTGFS_ID (GPIO_OTGFS_ID_0|GPIO_SPEED_100MHz) -#define GPIO_OTGFS_SOF (GPIO_OTGFS_SOF_0|GPIO_SPEED_100MHz) -#define GPIO_OTGHS_DM (GPIO_OTGHS_DM_0|GPIO_SPEED_100MHz) -#define GPIO_OTGHS_DP (GPIO_OTGHS_DP_0|GPIO_SPEED_100MHz) -#define GPIO_OTGHS_ID GPIO_OTGHS_ID_0 -#define GPIO_OTGHS_SOF GPIO_OTGHS_SOF_0 - -/* SDIO */ - -#define GPIO_SDIO_CK (GPIO_SDIO_CK_0|GPIO_SPEED_50MHz) -#define GPIO_SDIO_CMD (GPIO_SDIO_CMD_0|GPIO_SPEED_50MHz) -#define GPIO_SDIO_D0 (GPIO_SDIO_D0_0|GPIO_SPEED_50MHz) -#define GPIO_SDIO_D1 (GPIO_SDIO_D1_0|GPIO_SPEED_50MHz) -#define GPIO_SDIO_D2 (GPIO_SDIO_D2_0|GPIO_SPEED_50MHz) -#define GPIO_SDIO_D3 (GPIO_SDIO_D3_0|GPIO_SPEED_50MHz) - -/* FMC SDRAM pins (referenced by board src) */ - -#define GPIO_FMC_D0 (GPIO_FMC_D0_0|GPIO_SPEED_100MHz) -#define GPIO_FMC_D1 (GPIO_FMC_D1_0|GPIO_SPEED_100MHz) -#define GPIO_FMC_D2 (GPIO_FMC_D2_0|GPIO_SPEED_100MHz) -#define GPIO_FMC_D3 (GPIO_FMC_D3_0|GPIO_SPEED_100MHz) -#define GPIO_FMC_D4 (GPIO_FMC_D4_0|GPIO_SPEED_100MHz) -#define GPIO_FMC_D5 (GPIO_FMC_D5_0|GPIO_SPEED_100MHz) -#define GPIO_FMC_D6 (GPIO_FMC_D6_0|GPIO_SPEED_100MHz) -#define GPIO_FMC_D7 (GPIO_FMC_D7_0|GPIO_SPEED_100MHz) -#define GPIO_FMC_D8 (GPIO_FMC_D8_0|GPIO_SPEED_100MHz) -#define GPIO_FMC_D9 (GPIO_FMC_D9_0|GPIO_SPEED_100MHz) -#define GPIO_FMC_D10 (GPIO_FMC_D10_0|GPIO_SPEED_100MHz) -#define GPIO_FMC_D11 (GPIO_FMC_D11_0|GPIO_SPEED_100MHz) -#define GPIO_FMC_D12 (GPIO_FMC_D12_0|GPIO_SPEED_100MHz) -#define GPIO_FMC_D13 (GPIO_FMC_D13_0|GPIO_SPEED_100MHz) -#define GPIO_FMC_D14 (GPIO_FMC_D14_0|GPIO_SPEED_100MHz) -#define GPIO_FMC_D15 (GPIO_FMC_D15_0|GPIO_SPEED_100MHz) -#define GPIO_FMC_A0 (GPIO_FMC_A0_0|GPIO_SPEED_100MHz) -#define GPIO_FMC_A1 (GPIO_FMC_A1_0|GPIO_SPEED_100MHz) -#define GPIO_FMC_A2 (GPIO_FMC_A2_0|GPIO_SPEED_100MHz) -#define GPIO_FMC_A3 (GPIO_FMC_A3_0|GPIO_SPEED_100MHz) -#define GPIO_FMC_A4 (GPIO_FMC_A4_0|GPIO_SPEED_100MHz) -#define GPIO_FMC_A5 (GPIO_FMC_A5_0|GPIO_SPEED_100MHz) -#define GPIO_FMC_A6 (GPIO_FMC_A6_0|GPIO_SPEED_100MHz) -#define GPIO_FMC_A7 (GPIO_FMC_A7_0|GPIO_SPEED_100MHz) -#define GPIO_FMC_A8 (GPIO_FMC_A8_0|GPIO_SPEED_100MHz) -#define GPIO_FMC_A9 (GPIO_FMC_A9_0|GPIO_SPEED_100MHz) -#define GPIO_FMC_A10 (GPIO_FMC_A10_0|GPIO_SPEED_100MHz) -#define GPIO_FMC_A11 (GPIO_FMC_A11_0|GPIO_SPEED_100MHz) -#define GPIO_FMC_NBL0 (GPIO_FMC_NBL0_0|GPIO_SPEED_100MHz) -#define GPIO_FMC_NBL1 (GPIO_FMC_NBL1_0|GPIO_SPEED_100MHz) -#define GPIO_FMC_SDCLK (GPIO_FMC_SDCLK_0|GPIO_SPEED_100MHz) -#define GPIO_FMC_SDNCAS (GPIO_FMC_SDNCAS_0|GPIO_SPEED_100MHz) -#define GPIO_FMC_SDNRAS (GPIO_FMC_SDNRAS_0|GPIO_SPEED_100MHz) -#define GPIO_FMC_BA0 (GPIO_FMC_BA0_0|GPIO_SPEED_100MHz) -#define GPIO_FMC_BA1 (GPIO_FMC_BA1_0|GPIO_SPEED_100MHz) - -/* USB OTGHSFS (HS in FS mode) */ - -#define GPIO_OTGHSFS_DM (GPIO_OTGHSFS_DM_0|GPIO_SPEED_100MHz) -#define GPIO_OTGHSFS_DP (GPIO_OTGHSFS_DP_0|GPIO_SPEED_100MHz) -#define GPIO_OTGHSFS_ID (GPIO_OTGHSFS_ID_0|GPIO_SPEED_100MHz) - -#endif /* __BOARDS_ARM_STM32_STM32F429I_DISCO_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32/stm32f429i-disco/scripts/Make.defs b/boards/arm/stm32/stm32f429i-disco/scripts/Make.defs deleted file mode 100644 index a88280f56b3af..0000000000000 --- a/boards/arm/stm32/stm32f429i-disco/scripts/Make.defs +++ /dev/null @@ -1,46 +0,0 @@ -############################################################################ -# boards/arm/stm32/stm32f429i-disco/scripts/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/.config -include $(TOPDIR)/tools/Config.mk -include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs - -ifeq ($(CONFIG_SYSTEM_OFLOADER),y) -LDSCRIPT = ofloader.ld -else -LDSCRIPT = ld.script -endif - -ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) - -ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 - -CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) -CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) -CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -AFLAGS := $(CFLAGS) -D__ASSEMBLY__ - -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections -LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32/stm32f429i-disco/scripts/kernel-space.ld b/boards/arm/stm32/stm32f429i-disco/scripts/kernel-space.ld deleted file mode 100644 index db9d9db676a05..0000000000000 --- a/boards/arm/stm32/stm32f429i-disco/scripts/kernel-space.ld +++ /dev/null @@ -1,100 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f429i-disco/scripts/kernel-space.ld - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* NOTE: This depends on the memory.ld script having been included prior to - * this script. - */ - -OUTPUT_ARCH(arm) -EXTERN(_vectors) -ENTRY(_stext) -SECTIONS -{ - .text : { - _stext = ABSOLUTE(.); - *(.vectors) - *(.text .text.*) - *(.fixup) - *(.gnu.warning) - *(.rodata .rodata.*) - *(.gnu.linkonce.t.*) - *(.glue_7) - *(.glue_7t) - *(.got) - *(.gcc_except_table) - *(.gnu.linkonce.r.*) - _etext = ABSOLUTE(.); - } > kflash - - .init_section : { - _sinit = ABSOLUTE(.); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) - KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) - _einit = ABSOLUTE(.); - } > kflash - - .ARM.extab : { - *(.ARM.extab*) - } > kflash - - __exidx_start = ABSOLUTE(.); - .ARM.exidx : { - *(.ARM.exidx*) - } > kflash - - __exidx_end = ABSOLUTE(.); - - _eronly = ABSOLUTE(.); - - .data : { - _sdata = ABSOLUTE(.); - *(.data .data.*) - *(.gnu.linkonce.d.*) - CONSTRUCTORS - . = ALIGN(4); - _edata = ABSOLUTE(.); - } > ksram AT > kflash - - .bss : { - _sbss = ABSOLUTE(.); - *(.bss .bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - . = ALIGN(8); - _ebss = ABSOLUTE(.); - } > ksram - - /* Stabs debugging sections */ - - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_info 0 : { *(.debug_info) } - .debug_line 0 : { *(.debug_line) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_aranges 0 : { *(.debug_aranges) } -} diff --git a/boards/arm/stm32/stm32f429i-disco/scripts/ld.script b/boards/arm/stm32/stm32f429i-disco/scripts/ld.script deleted file mode 100644 index f6fde30fd1e85..0000000000000 --- a/boards/arm/stm32/stm32f429i-disco/scripts/ld.script +++ /dev/null @@ -1,133 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f429i-disco/scripts/ld.script - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* The STM32F429ZIT6 has 2048Kb of FLASH beginning at address 0x0800:0000 and - * 256Kb of SRAM. SRAM is split up into four blocks: - * - * 1) 112Kb of SRAM beginning at address 0x2000:0000 - * 2) 16Kb of SRAM beginning at address 0x2001:c000 - * 3) 64Kb of SRAM beginning at address 0x2002:0000 - * 4) 64Kb of CCM SRAM beginning at address 0x1000:0000 - * - * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 - * where the code expects to begin execution by jumping to the entry point in - * the 0x0800:0000 address - * range. - */ - -MEMORY -{ - flash (rx) : ORIGIN = 0x08000000, LENGTH = 2048K - sram (rwx) : ORIGIN = 0x20000000, LENGTH = 112K -} - -OUTPUT_ARCH(arm) -EXTERN(_vectors) -ENTRY(_stext) -SECTIONS -{ - .text : { - _stext = ABSOLUTE(.); - *(.vectors) - *(.text .text.*) - *(.fixup) - *(.gnu.warning) - *(.rodata .rodata.*) - *(.gnu.linkonce.t.*) - *(.glue_7) - *(.glue_7t) - *(.got) - *(.gcc_except_table) - *(.gnu.linkonce.r.*) - _etext = ABSOLUTE(.); - } > flash - - .init_section : ALIGN(4) { - _sinit = ABSOLUTE(.); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) - KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) - _einit = ABSOLUTE(.); - } > flash - - .ARM.extab : ALIGN(4) { - *(.ARM.extab*) - } > flash - - .ARM.exidx : ALIGN(4) { - __exidx_start = ABSOLUTE(.); - *(.ARM.exidx*) - __exidx_end = ABSOLUTE(.); - } > flash - - .tdata : { - _stdata = ABSOLUTE(.); - *(.tdata .tdata.* .gnu.linkonce.td.*); - _etdata = ABSOLUTE(.); - } > flash - - .tbss : { - _stbss = ABSOLUTE(.); - *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); - _etbss = ABSOLUTE(.); - } > flash - - _eronly = ABSOLUTE(.); - - /* The RAM vector table (if present) should lie at the beginning of SRAM */ - - .ram_vectors : { - *(.ram_vectors) - } > sram - - .data : ALIGN(4) { - _sdata = ABSOLUTE(.); - *(.data .data.*) - *(.gnu.linkonce.d.*) - CONSTRUCTORS - . = ALIGN(4); - _edata = ABSOLUTE(.); - } > sram AT > flash - - .bss : ALIGN(4) { - _sbss = ABSOLUTE(.); - *(.bss .bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - . = ALIGN(4); - _ebss = ABSOLUTE(.); - } > sram - - /* Stabs debugging sections. */ - - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_info 0 : { *(.debug_info) } - .debug_line 0 : { *(.debug_line) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_aranges 0 : { *(.debug_aranges) } -} diff --git a/boards/arm/stm32/stm32f429i-disco/scripts/memory.ld b/boards/arm/stm32/stm32f429i-disco/scripts/memory.ld deleted file mode 100644 index 95ece2dbfe8a4..0000000000000 --- a/boards/arm/stm32/stm32f429i-disco/scripts/memory.ld +++ /dev/null @@ -1,88 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f429i-disco/scripts/memory.ld - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* The STM32F429ZIT has 2048Kb of FLASH beginning at address 0x0800:0000 and - * 256Kb of SRAM. SRAM is split up into four blocks: - * - * 1) 112KB of SRAM beginning at address 0x2000:0000 - * 2) 16KB of SRAM beginning at address 0x2001:c000 - * 3) 64KB of SRAM beginning at address 0x2002:0000 - * 4) 64KB of CCM SRAM beginning at address 0x1000:0000 - * - * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 - * where the code expects to begin execution by jumping to the entry point in - * the 0x0800:0000 address range. - * - * For MPU support, the kernel-mode NuttX section is assumed to be 128Kb of - * FLASH and 4Kb of SRAM. That is an excessive amount for the kernel which - * should fit into 64KB and, of course, can be optimized as needed (See - * also boards/arm/stm32/stm32f429i-disco/scripts/kernel-space.ld). Allowing the - * additional does permit addition debug instrumentation to be added to the - * kernel space without overflowing the partition. - * - * Alignment of the user space FLASH partition is also a critical factor: - * The user space FLASH partition will be spanned with a single region of - * size 2**n bytes. The alignment of the user-space region must be the same. - * As a consequence, as the user-space increases in size, the alignment - * requirement also increases. - * - * This alignment requirement means that the largest user space FLASH region - * you can have will be 512KB at it would have to be positioned at - * 0x08800000. If you change this address, don't forget to change the - * CONFIG_NUTTX_USERSPACE configuration setting to match and to modify - * the check in kernel/userspace.c. - * - * For the same reasons, the maximum size of the SRAM mapping is limited to - * 4KB. Both of these alignment limitations could be reduced by using - * multiple regions to map the FLASH/SDRAM range or perhaps with some - * clever use of subregions. - * - * A detailed memory map for the 112KB SRAM region is as follows: - * - * 0x20000 0000: Kernel .data region. Typical size: 0.1KB - * ------- ---- Kernel .bss region. Typical size: 1.8KB - * 0x20000 0800: Kernel IDLE thread stack (approximate). Size is - * determined by CONFIG_IDLETHREAD_STACKSIZE and - * adjustments for alignment. Typical is 1KB. - * ------- ---- Padded to 4KB - * 0x20000 1000: User .data region. Size is variable. - * ------- ---- User .bss region Size is variable. - * 0x20000 2000: Beginning of kernel heap. Size determined by - * CONFIG_MM_KERNEL_HEAPSIZE. - * ------- ---- Beginning of user heap. Can vary with other settings. - * 0x20001 c000: End+1 of CPU RAM - */ - -MEMORY -{ - /* 1024Kb FLASH */ - - kflash (rx) : ORIGIN = 0x08000000, LENGTH = 128K - uflash (rx) : ORIGIN = 0x08020000, LENGTH = 128K - xflash (rx) : ORIGIN = 0x08040000, LENGTH = 768K - - /* 112Kb of contiguous SRAM */ - - ksram (rwx) : ORIGIN = 0x20000000, LENGTH = 4K - usram (rwx) : ORIGIN = 0x20001000, LENGTH = 4K - xsram (rwx) : ORIGIN = 0x20002000, LENGTH = 104K -} diff --git a/boards/arm/stm32/stm32f429i-disco/scripts/user-space.ld b/boards/arm/stm32/stm32f429i-disco/scripts/user-space.ld deleted file mode 100644 index 3ee80c42f4651..0000000000000 --- a/boards/arm/stm32/stm32f429i-disco/scripts/user-space.ld +++ /dev/null @@ -1,114 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f429i-disco/scripts/user-space.ld - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* NOTE: This depends on the memory.ld script having been included prior to - * this script. - */ - -/* Make sure that the critical memory management functions are in user-space. - * the user heap memory manager will reside in user-space but be usable both - * by kernel- and user-space code - */ - -EXTERN(umm_initialize) -EXTERN(umm_addregion) - -EXTERN(malloc) -EXTERN(realloc) -EXTERN(zalloc) -EXTERN(free) - -OUTPUT_ARCH(arm) -SECTIONS -{ - .userspace : { - *(.userspace) - } > uflash - - .text : { - _stext = ABSOLUTE(.); - *(.text .text.*) - *(.fixup) - *(.gnu.warning) - *(.rodata .rodata.*) - *(.gnu.linkonce.t.*) - *(.glue_7) - *(.glue_7t) - *(.got) - *(.gcc_except_table) - *(.gnu.linkonce.r.*) - _etext = ABSOLUTE(.); - } > uflash - - .init_section : { - _sinit = ABSOLUTE(.); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) - KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) - _einit = ABSOLUTE(.); - } > uflash - - .ARM.extab : { - *(.ARM.extab*) - } > uflash - - __exidx_start = ABSOLUTE(.); - .ARM.exidx : { - *(.ARM.exidx*) - } > uflash - - __exidx_end = ABSOLUTE(.); - - _eronly = ABSOLUTE(.); - - .data : { - _sdata = ABSOLUTE(.); - *(.data .data.*) - *(.gnu.linkonce.d.*) - CONSTRUCTORS - . = ALIGN(4); - _edata = ABSOLUTE(.); - } > usram AT > uflash - - .bss : { - _sbss = ABSOLUTE(.); - *(.bss .bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - . = ALIGN(8); - _ebss = ABSOLUTE(.); - } > usram - - /* Stabs debugging sections */ - - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_info 0 : { *(.debug_info) } - .debug_line 0 : { *(.debug_line) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_aranges 0 : { *(.debug_aranges) } -} diff --git a/boards/arm/stm32/stm32f429i-disco/src/CMakeLists.txt b/boards/arm/stm32/stm32f429i-disco/src/CMakeLists.txt deleted file mode 100644 index fa9314f019bff..0000000000000 --- a/boards/arm/stm32/stm32f429i-disco/src/CMakeLists.txt +++ /dev/null @@ -1,79 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/stm32f429i-disco/src/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -set(SRCS stm32_boot.c stm32_bringup.c stm32_spi.c) - -if(CONFIG_ARCH_LEDS) - list(APPEND SRCS stm32_autoleds.c) -else() - list(APPEND SRCS stm32_userleds.c) -endif() - -if(CONFIG_ARCH_BUTTONS) - list(APPEND SRCS stm32_buttons.c) -endif() - -if(CONFIG_ARCH_IDLE_CUSTOM) - list(APPEND SRCS stm32_idle.c) -endif() - -if(CONFIG_STM32_FMC) - list(APPEND SRCS stm32_extmem.c) -endif() - -if(CONFIG_STM32_OTGHS) - list(APPEND SRCS stm32_usb.c) -endif() - -if(CONFIG_INPUT_STMPE811) - list(APPEND SRCS stm32_stmpe811.c) -endif() - -if(CONFIG_STM32F429I_DISCO_ILI9341) - list(APPEND SRCS stm32_ili93414ws.c) -endif() - -if(CONFIG_STM32F429I_DISCO_ILI9341_LCDIFACE - AND CONFIG_STM32F429I_DISCO_ILI9341_FBIFACE - AND CONFIG_STM32_LTDC) - list(APPEND SRCS stm32_lcd.c) -endif() - -if(CONFIG_PWM) - list(APPEND SRCS stm32_pwm.c) -endif() - -if(CONFIG_ADC) - list(APPEND SRCS stm32_adc.c) -endif() - -if(CONFIG_STM32_CAN_CHARDRIVER) - list(APPEND SRCS stm32_can.c) -endif() - -if(CONFIG_STM32F429I_DISCO_HIGHPRI) - list(APPEND SRCS stm32_highpri.c) -endif() - -target_sources(board PRIVATE ${SRCS}) - -set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/ld.script") diff --git a/boards/arm/stm32/stm32f429i-disco/src/Make.defs b/boards/arm/stm32/stm32f429i-disco/src/Make.defs deleted file mode 100644 index 5b7dd1fcbd2fd..0000000000000 --- a/boards/arm/stm32/stm32f429i-disco/src/Make.defs +++ /dev/null @@ -1,82 +0,0 @@ -############################################################################ -# boards/arm/stm32/stm32f429i-disco/src/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/Make.defs - -CSRCS = stm32_boot.c stm32_bringup.c stm32_spi.c - -ifeq ($(CONFIG_ARCH_LEDS),y) -CSRCS += stm32_autoleds.c -else -CSRCS += stm32_userleds.c -endif - -ifeq ($(CONFIG_ARCH_BUTTONS),y) -CSRCS += stm32_buttons.c -endif - -ifeq ($(CONFIG_ARCH_IDLE_CUSTOM),y) -CSRCS += stm32_idle.c -endif - -ifeq ($(CONFIG_STM32_FMC),y) -CSRCS += stm32_extmem.c -endif - -ifeq ($(CONFIG_STM32_OTGHS),y) -CSRCS += stm32_usb.c -endif - -ifeq ($(CONFIG_INPUT_STMPE811),y) -CSRCS += stm32_stmpe811.c -endif - -ifeq ($(CONFIG_STM32F429I_DISCO_ILI9341),y) -CSRCS += stm32_ili93414ws.c -endif - -ifeq ($(and \ - $(CONFIG_STM32F429I_DISCO_ILI9341_LCDIFACE), \ - $(CONFIG_STM32F429I_DISCO_ILI9341_FBIFACE), \ - $(CONFIG_STM32_LTDC)),) -CSRCS += stm32_lcd.c -endif - -ifeq ($(CONFIG_PWM),y) -CSRCS += stm32_pwm.c -endif - -ifeq ($(CONFIG_ADC),y) -CSRCS += stm32_adc.c -endif - -ifeq ($(CONFIG_STM32_CAN_CHARDRIVER),y) -CSRCS += stm32_can.c -endif - -ifeq ($(CONFIG_STM32F429I_DISCO_HIGHPRI),y) -CSRCS += stm32_highpri.c -endif - -DEPPATH += --dep-path board -VPATH += :board -CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/stm32f429i-disco/src/stm32_adc.c b/boards/arm/stm32/stm32f429i-disco/src/stm32_adc.c deleted file mode 100644 index 45b62589d27a9..0000000000000 --- a/boards/arm/stm32/stm32f429i-disco/src/stm32_adc.c +++ /dev/null @@ -1,237 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f429i-disco/src/stm32_adc.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include "stm32.h" - -#if defined(CONFIG_ADC) && (defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC3)) - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -/* 1 or 2 ADC devices (DEV1, DEV2). - * ADC1 and ADC3 supported for now. - */ - -#if defined(CONFIG_STM32_ADC1) -# define DEV1_PORT 1 -#endif - -#if defined(CONFIG_STM32_ADC3) -# if defined(DEV1_PORT) -# define DEV2_PORT 3 -# else -# define DEV1_PORT 3 -# endif -#endif - -/* The number of ADC channels in the conversion list */ - -/* TODO DMA */ - -#define ADC1_NCHANNELS 2 -#define ADC3_NCHANNELS 1 - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* DEV 1 */ - -#if DEV1_PORT == 1 - -#define DEV1_NCHANNELS ADC1_NCHANNELS - -/* Identifying number of each ADC channel (even if NCHANNELS is less ) */ - -static const uint8_t g_chanlist1[2] = -{ - 5, - 13, -}; - -/* Configurations of pins used by each ADC channel */ - -static const uint32_t g_pinlist1[2] = -{ - GPIO_ADC1_IN5_0, /* PA5 */ - GPIO_ADC1_IN13_0, /* PC3 */ -}; - -#elif DEV1_PORT == 3 - -#define DEV1_NCHANNELS ADC3_NCHANNELS - -/* Identifying number of each ADC channel */ - -static const uint8_t g_chanlist1[1] = -{ - 4, -}; - -/* Configurations of pins used by each ADC channel */ - -static const uint32_t g_pinlist1[1] = -{ - GPIO_ADC3_IN4_0, /* PF6 */ -}; - -#endif /* DEV1_PORT == 1 */ - -#ifdef DEV2_PORT - -/* DEV 2 */ - -#if DEV2_PORT == 3 - -#define DEV2_NCHANNELS ADC3_NCHANNELS - -/* Identifying number of each ADC channel */ - -static const uint8_t g_chanlist2[3] = -{ - 8, - 9, - 10 -}; - -/* Configurations of pins used by each ADC channel */ - -static const uint32_t g_pinlist2[3] = -{ - GPIO_ADC3_IN8_0, /* PD11/A3 */ - GPIO_ADC3_IN9_0, /* PD12/A4 */ - GPIO_ADC3_IN10_0, /* PD13/A5 */ -}; - -#endif /* DEV2_PORT == 3 */ -#endif /* DEV2_PORT */ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_adc_setup - * - * Description: - * Initialize ADC and register the ADC driver. - * - ****************************************************************************/ - -int stm32_adc_setup(void) -{ - static bool initialized = false; - struct adc_dev_s *adc; - int ret; - int i; - - /* Check if we have already initialized */ - - if (!initialized) - { - /* DEV1 */ - - /* Configure the pins as analog inputs for the selected channels */ - - for (i = 0; i < DEV1_NCHANNELS; i++) - { - stm32_configgpio(g_pinlist1[i]); - } - - /* Call stm32_adcinitialize() to get an instance of the ADC interface */ - - adc = stm32_adcinitialize(DEV1_PORT, g_chanlist1, DEV1_NCHANNELS); - if (adc == NULL) - { - aerr("ERROR: Failed to get ADC interface 1\n"); - return -ENODEV; - } - - /* Register the ADC driver at "/dev/adc0" */ - - ret = adc_register("/dev/adc0", adc); - if (ret < 0) - { - aerr("ERROR: adc_register /dev/adc0 failed: %d\n", ret); - return ret; - } - -#ifdef DEV2_PORT - /* DEV2 */ - - /* Configure the pins as analog inputs for the selected channels */ - - for (i = 0; i < DEV2_NCHANNELS; i++) - { - stm32_configgpio(g_pinlist2[i]); - } - - /* Call stm32_adcinitialize() to get an instance of the ADC interface */ - - adc = stm32_adcinitialize(DEV2_PORT, g_chanlist2, DEV2_NCHANNELS); - if (adc == NULL) - { - aerr("ERROR: Failed to get ADC interface 2\n"); - return -ENODEV; - } - - /* Register the ADC driver at "/dev/adc1" */ - - ret = adc_register("/dev/adc1", adc); - if (ret < 0) - { - aerr("ERROR: adc_register /dev/adc1 failed: %d\n", ret); - return ret; - } -#endif - - initialized = true; - } - - return OK; -} - -#endif /* CONFIG_ADC && (CONFIG_STM32_ADC1 || CONFIG_STM32_ADC3) */ diff --git a/boards/arm/stm32/stm32f429i-disco/src/stm32_autoleds.c b/boards/arm/stm32/stm32f429i-disco/src/stm32_autoleds.c deleted file mode 100644 index cdc48319a0246..0000000000000 --- a/boards/arm/stm32/stm32f429i-disco/src/stm32_autoleds.c +++ /dev/null @@ -1,208 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f429i-disco/src/stm32_autoleds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32.h" -#include "stm32f429i-disco.h" - -#ifdef CONFIG_ARCH_LEDS - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* The following definitions map the encoded LED setting to GPIO settings */ - -#define STM32F4_LED1 (1 << 0) -#define STM32F4_LED2 (1 << 1) - -#define ON_SETBITS_SHIFT (0) -#define ON_CLRBITS_SHIFT (4) -#define OFF_SETBITS_SHIFT (8) -#define OFF_CLRBITS_SHIFT (12) - -#define ON_BITS(v) ((v) & 0xff) -#define OFF_BITS(v) (((v) >> 8) & 0x0ff) -#define SETBITS(b) ((b) & 0x0f) -#define CLRBITS(b) (((b) >> 4) & 0x0f) - -#define ON_SETBITS(v) (SETBITS(ON_BITS(v)) -#define ON_CLRBITS(v) (CLRBITS(ON_BITS(v)) -#define OFF_SETBITS(v) (SETBITS(OFF_BITS(v)) -#define OFF_CLRBITS(v) (CLRBITS(OFF_BITS(v)) - -#define LED_STARTED_ON_SETBITS ((STM32F4_LED1) << ON_SETBITS_SHIFT) -#define LED_STARTED_ON_CLRBITS ((STM32F4_LED2) << ON_CLRBITS_SHIFT) -#define LED_STARTED_OFF_SETBITS (0 << OFF_SETBITS_SHIFT) -#define LED_STARTED_OFF_CLRBITS ((STM32F4_LED1|STM32F4_LED2) << OFF_CLRBITS_SHIFT) - -#define LED_HEAPALLOCATE_ON_SETBITS ((STM32F4_LED2) << ON_SETBITS_SHIFT) -#define LED_HEAPALLOCATE_ON_CLRBITS ((STM32F4_LED1) << ON_CLRBITS_SHIFT) -#define LED_HEAPALLOCATE_OFF_SETBITS ((STM32F4_LED1) << OFF_SETBITS_SHIFT) -#define LED_HEAPALLOCATE_OFF_CLRBITS ((STM32F4_LED2) << OFF_CLRBITS_SHIFT) - -#define LED_IRQSENABLED_ON_SETBITS ((STM32F4_LED1|STM32F4_LED2) << ON_SETBITS_SHIFT) -#define LED_IRQSENABLED_ON_CLRBITS ((STM32F4_LED2) << ON_CLRBITS_SHIFT) -#define LED_IRQSENABLED_OFF_SETBITS ((STM32F4_LED2) << OFF_SETBITS_SHIFT) -#define LED_IRQSENABLED_OFF_CLRBITS ((STM32F4_LED1) << OFF_CLRBITS_SHIFT) - -#define LED_STACKCREATED_ON_SETBITS ((STM32F4_LED1) << ON_SETBITS_SHIFT) -#define LED_STACKCREATED_ON_CLRBITS ((STM32F4_LED1|STM32F4_LED2) << ON_CLRBITS_SHIFT) -#define LED_STACKCREATED_OFF_SETBITS ((STM32F4_LED1|STM32F4_LED2) << OFF_SETBITS_SHIFT) -#define LED_STACKCREATED_OFF_CLRBITS ((STM32F4_LED1|STM32F4_LED2) << OFF_CLRBITS_SHIFT) - -#define LED_INIRQ_ON_SETBITS ((STM32F4_LED2) << ON_SETBITS_SHIFT) -#define LED_INIRQ_ON_CLRBITS ((0) << ON_CLRBITS_SHIFT) -#define LED_INIRQ_OFF_SETBITS ((0) << OFF_SETBITS_SHIFT) -#define LED_INIRQ_OFF_CLRBITS ((STM32F4_LED2) << OFF_CLRBITS_SHIFT) - -#define LED_SIGNAL_ON_SETBITS ((STM32F4_LED2) << ON_SETBITS_SHIFT) -#define LED_SIGNAL_ON_CLRBITS ((0) << ON_CLRBITS_SHIFT) -#define LED_SIGNAL_OFF_SETBITS ((0) << OFF_SETBITS_SHIFT) -#define LED_SIGNAL_OFF_CLRBITS ((STM32F4_LED2) << OFF_CLRBITS_SHIFT) - -#define LED_ASSERTION_ON_SETBITS ((STM32F4_LED2) << ON_SETBITS_SHIFT) -#define LED_ASSERTION_ON_CLRBITS ((0) << ON_CLRBITS_SHIFT) -#define LED_ASSERTION_OFF_SETBITS ((0) << OFF_SETBITS_SHIFT) -#define LED_ASSERTION_OFF_CLRBITS ((STM32F4_LED2) << OFF_CLRBITS_SHIFT) - -#define LED_PANIC_ON_SETBITS ((STM32F4_LED2) << ON_SETBITS_SHIFT) -#define LED_PANIC_ON_CLRBITS ((0) << ON_CLRBITS_SHIFT) -#define LED_PANIC_OFF_SETBITS ((0) << OFF_SETBITS_SHIFT) -#define LED_PANIC_OFF_CLRBITS ((STM32F4_LED2) << OFF_CLRBITS_SHIFT) - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -static const uint16_t g_ledbits[8] = -{ - (LED_STARTED_ON_SETBITS | LED_STARTED_ON_CLRBITS | - LED_STARTED_OFF_SETBITS | LED_STARTED_OFF_CLRBITS), - - (LED_HEAPALLOCATE_ON_SETBITS | LED_HEAPALLOCATE_ON_CLRBITS | - LED_HEAPALLOCATE_OFF_SETBITS | LED_HEAPALLOCATE_OFF_CLRBITS), - - (LED_IRQSENABLED_ON_SETBITS | LED_IRQSENABLED_ON_CLRBITS | - LED_IRQSENABLED_OFF_SETBITS | LED_IRQSENABLED_OFF_CLRBITS), - - (LED_STACKCREATED_ON_SETBITS | LED_STACKCREATED_ON_CLRBITS | - LED_STACKCREATED_OFF_SETBITS | LED_STACKCREATED_OFF_CLRBITS), - - (LED_INIRQ_ON_SETBITS | LED_INIRQ_ON_CLRBITS | - LED_INIRQ_OFF_SETBITS | LED_INIRQ_OFF_CLRBITS), - - (LED_SIGNAL_ON_SETBITS | LED_SIGNAL_ON_CLRBITS | - LED_SIGNAL_OFF_SETBITS | LED_SIGNAL_OFF_CLRBITS), - - (LED_ASSERTION_ON_SETBITS | LED_ASSERTION_ON_CLRBITS | - LED_ASSERTION_OFF_SETBITS | LED_ASSERTION_OFF_CLRBITS), - - (LED_PANIC_ON_SETBITS | LED_PANIC_ON_CLRBITS | - LED_PANIC_OFF_SETBITS | LED_PANIC_OFF_CLRBITS) -}; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -static inline void led_clrbits(unsigned int clrbits) -{ - if ((clrbits & STM32F4_LED1) != 0) - { - stm32_gpiowrite(GPIO_LED1, false); - } - - if ((clrbits & STM32F4_LED2) != 0) - { - stm32_gpiowrite(GPIO_LED2, false); - } -} - -static inline void led_setbits(unsigned int setbits) -{ - if ((setbits & STM32F4_LED1) != 0) - { - stm32_gpiowrite(GPIO_LED1, true); - } - - if ((setbits & STM32F4_LED2) != 0) - { - stm32_gpiowrite(GPIO_LED2, true); - } -} - -static void led_setonoff(unsigned int bits) -{ - led_clrbits(CLRBITS(bits)); - led_setbits(SETBITS(bits)); -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_autoled_initialize - ****************************************************************************/ - -void board_autoled_initialize(void) -{ - /* Configure LED1-4 GPIOs for output */ - - stm32_configgpio(GPIO_LED1); - stm32_configgpio(GPIO_LED2); -} - -/**************************************************************************** - * Name: board_autoled_on - ****************************************************************************/ - -void board_autoled_on(int led) -{ - led_setonoff(ON_BITS(g_ledbits[led])); -} - -/**************************************************************************** - * Name: board_autoled_off - ****************************************************************************/ - -void board_autoled_off(int led) -{ - led_setonoff(OFF_BITS(g_ledbits[led])); -} - -#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/stm32f429i-disco/src/stm32_boot.c b/boards/arm/stm32/stm32f429i-disco/src/stm32_boot.c deleted file mode 100644 index deabbc588b52a..0000000000000 --- a/boards/arm/stm32/stm32f429i-disco/src/stm32_boot.c +++ /dev/null @@ -1,119 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f429i-disco/src/stm32_boot.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include -#include - -#include "arm_internal.h" -#include "stm32f429i-disco.h" -#include "stm32_ccm.h" - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_boardinitialize - * - * Description: - * All STM32 architectures must provide the following entry point. - * This entry point is called early in the initialization -- after all - * memory has been configured and mapped but before any devices have been - * initialized. - * - ****************************************************************************/ - -void stm32_boardinitialize(void) -{ -#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || \ - defined(CONFIG_STM32_SPI3) || defined(CONFIG_STM32_SPI4) || \ - defined(CONFIG_STM32_SPI5) - - /* Configure SPI chip selects if 1) SPI is not disabled, and 2) the weak - * function stm32_spidev_initialize() has been brought into the link. - */ - - if (stm32_spidev_initialize) - { - stm32_spidev_initialize(); - } -#endif - -#ifdef CONFIG_STM32_OTGHS - /* Initialize USB if the 1) OTG HS controller is in the configuration and - * 2) disabled, and 3) the weak function stm32_usbinitialize() has been - * brought into the build. Presumably either CONFIG_USBDEV or - * CONFIG_USBHOST is also selected. - */ - - if (stm32_usbinitialize) - { - stm32_usbinitialize(); - } -#endif - -#ifdef CONFIG_ARCH_LEDS - /* Configure on-board LEDs if LED support has been selected. */ - - board_autoled_initialize(); -#endif - -#ifdef CONFIG_STM32_FMC - stm32_sdram_initialize(); -#endif - -#ifdef HAVE_CCM_HEAP - /* Initialize CCM allocator */ - - ccm_initialize(); -#endif -} - -/**************************************************************************** - * Name: board_late_initialize - * - * Description: - * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional - * initialization call will be performed in the boot-up sequence to a - * function called board_late_initialize(). board_late_initialize() will be - * called immediately after up_initialize() is called and just before the - * initial application is started. This additional initialization phase - * may be used, for example, to initialize board-specific device drivers. - * - ****************************************************************************/ - -#ifdef CONFIG_BOARD_LATE_INITIALIZE -void board_late_initialize(void) -{ - /* Perform board-specific initialization */ - - stm32_bringup(); -} -#endif diff --git a/boards/arm/stm32/stm32f429i-disco/src/stm32_bringup.c b/boards/arm/stm32/stm32f429i-disco/src/stm32_bringup.c deleted file mode 100644 index a00da867c599b..0000000000000 --- a/boards/arm/stm32/stm32f429i-disco/src/stm32_bringup.c +++ /dev/null @@ -1,429 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f429i-disco/src/stm32_bringup.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include - -#include -#include -#include - -#ifdef CONFIG_STM32_SPI4 -# include -#endif - -#if defined(CONFIG_MTD_SST25XX) || defined(CONFIG_MTD_PROGMEM) -# include -#endif - -#ifdef CONFIG_VIDEO_FB -# include -#endif - -#ifdef CONFIG_USBMONITOR -# include -#endif - -#ifndef CONFIG_STM32F429I_DISCO_FLASH_MINOR -#define CONFIG_STM32F429I_DISCO_FLASH_MINOR 0 -#endif - -#ifdef CONFIG_STM32F429I_DISCO_FLASH_CONFIG_PART -#ifdef CONFIG_PLATFORM_CONFIGDATA -# include -#endif -#endif - -#ifdef CONFIG_STM32_OTGHS -# include "stm32_usbhost.h" -#endif - -#include "stm32.h" -#include "stm32f429i-disco.h" - -#ifdef CONFIG_INPUT_BUTTONS_LOWER -# include -#endif - -#ifdef CONFIG_SENSORS_L3GD20 -#include "stm32_l3gd20.h" -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_bringup - * - * Description: - * Perform architecture-specific initialization - * - * CONFIG_BOARD_LATE_INITIALIZE=y : - * Called from board_late_initialize(). - * - ****************************************************************************/ - -int stm32_bringup(void) -{ -#if defined(CONFIG_STM32_SPI4) - struct spi_dev_s *spi; -#endif -#if defined(CONFIG_MTD) - struct mtd_dev_s *mtd; -#if defined (CONFIG_MTD_SST25XX) - struct mtd_geometry_s geo; -#endif -#endif -#if defined(CONFIG_MTD_PARTITION_NAMES) - const char *partname = CONFIG_STM32F429I_DISCO_FLASH_PART_NAMES; -#endif - int ret; - -#ifdef HAVE_PROC - /* mount the proc filesystem */ - - ret = nx_mount(NULL, CONFIG_NSH_PROC_MOUNTPOINT, "procfs", 0, NULL); - if (ret < 0) - { - syslog(LOG_ERR, - "ERROR: Failed to mount the PROC filesystem: %d\n", ret); - return ret; - } -#endif - - /* Configure SPI-based devices */ - -#if defined(CONFIG_MTD) && defined(CONFIG_MTD_PROGMEM) - mtd = progmem_initialize(); - if (mtd == NULL) - { - syslog(LOG_ERR, "ERROR: progmem_initialize\n"); - } - - ret = register_mtddriver("/dev/flash", mtd, 0, mtd); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: register_mtddriver() failed: %d\n", ret); - } - -#endif - -#ifdef CONFIG_STM32_SPI4 - /* Get the SPI port */ - - syslog(LOG_INFO, "Initializing SPI port 4\n"); - - spi = stm32_spibus_initialize(4); - if (!spi) - { - syslog(LOG_ERR, "ERROR: Failed to initialize SPI port 4\n"); - return -ENODEV; - } - - syslog(LOG_INFO, "Successfully initialized SPI port 4\n"); - - /* Now bind the SPI interface to the SST25F064 SPI FLASH driver. This - * is a FLASH device that has been added external to the board (i.e. - * the board does not ship from STM with any on-board FLASH. - */ - -#if defined(CONFIG_MTD) && defined(CONFIG_MTD_SST25XX) - syslog(LOG_INFO, "Bind SPI to the SPI flash driver\n"); - - mtd = sst25xx_initialize(spi); - if (!mtd) - { - syslog(LOG_ERR, "ERROR: Failed to bind SPI port 4 to the SPI FLASH" - " driver\n"); - } - else - { - syslog(LOG_INFO, "Successfully bound SPI port 4 to the SPI FLASH" - " driver\n"); - - /* Get the geometry of the FLASH device */ - - ret = mtd->ioctl(mtd, MTDIOC_GEOMETRY, - (unsigned long)((uintptr_t)&geo)); - if (ret < 0) - { - ferr("ERROR: mtd->ioctl failed: %d\n", ret); - return ret; - } - -#ifdef CONFIG_STM32F429I_DISCO_FLASH_PART - { - int partno; - int partsize; - int partoffset; - int partszbytes; - int erasesize; - const char *partstring = CONFIG_STM32F429I_DISCO_FLASH_PART_LIST; - const char *ptr; - struct mtd_dev_s *mtd_part; - char partref[16]; - - /* Now create a partition on the FLASH device */ - - partno = 0; - ptr = partstring; - partoffset = 0; - - /* Get the Flash erase size */ - - erasesize = geo.erasesize; - - while (*ptr != '\0') - { - /* Get the partition size */ - - partsize = atoi(ptr); - partszbytes = (partsize << 10); /* partsize is defined in KB */ - - /* Check if partition size is bigger then erase block */ - - if (partszbytes < erasesize) - { - ferr("ERROR: Partition size is lesser than erasesize!\n"); - return -1; - } - - /* Check if partition size is multiple of erase block */ - - if ((partszbytes % erasesize) != 0) - { - ferr("ERROR: Partition size is not multiple of" - " erasesize!\n"); - return -1; - } - - mtd_part = mtd_partition(mtd, partoffset, - partszbytes / erasesize); - partoffset += partszbytes / erasesize; - -#ifdef CONFIG_STM32F429I_DISCO_FLASH_CONFIG_PART - /* Test if this is the config partition */ - - if (CONFIG_STM32F429I_DISCO_FLASH_CONFIG_PART_NUMBER == partno) - { - /* Register the partition as the config device */ - - mtdconfig_register(mtd_part); - } - else -#endif - { - /* Now initialize a SMART Flash block device and bind it - * to the MTD device. - */ - -#if defined(CONFIG_MTD_SMART) && defined(CONFIG_FS_SMARTFS) - snprintf(partref, sizeof(partref), "p%d", partno); - smart_initialize(CONFIG_STM32F429I_DISCO_FLASH_MINOR, - mtd_part, partref); -#endif - } - -#if defined(CONFIG_MTD_PARTITION_NAMES) - /* Set the partition name */ - - if (mtd_part == NULL) - { - ferr("ERROR: failed to create partition %s\n", partname); - return -1; - } - - mtd_setpartitionname(mtd_part, partname); - - /* Now skip to next name. We don't need to split the string - * here because the MTD partition logic will only display names - * up to the comma, thus allowing us to use a single static - * name in the code. - */ - - while (*partname != ',' && *partname != '\0') - { - /* Skip to next ',' */ - - partname++; - } - - if (*partname == ',') - { - partname++; - } -#endif - - /* Update the pointer to point to the next size in the list */ - - while ((*ptr >= '0') && (*ptr <= '9')) - { - ptr++; - } - - if (*ptr == ',') - { - ptr++; - } - - /* Increment the part number */ - - partno++; - } - } -#else /* CONFIG_STM32F429I_DISCO_FLASH_PART */ - - /* Configure the device with no partition support */ - - smart_initialize(CONFIG_STM32F429I_DISCO_FLASH_MINOR, mtd, NULL); - -#endif /* CONFIG_STM32F429I_DISCO_FLASH_PART */ - } - -#endif /* CONFIG_MTD */ -#endif /* CONFIG_STM32_SPI4 */ - -#ifdef CONFIG_VIDEO_FB - /* Initialize and register the framebuffer driver */ - - ret = fb_register(0, 0); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: fb_register() failed: %d\n", ret); - } -#endif - -#if defined(CONFIG_RAMMTD) && defined(CONFIG_STM32F429I_DISCO_RAMMTD) - /* Create a RAM MTD device if configured */ - - { - uint8_t *start = - kmm_malloc(CONFIG_STM32F429I_DISCO_RAMMTD_SIZE * 1024); - mtd = rammtd_initialize(start, - CONFIG_STM32F429I_DISCO_RAMMTD_SIZE * 1024); - mtd->ioctl(mtd, MTDIOC_BULKERASE, 0); - - /* Now initialize a SMART Flash block device and bind it to the MTD - * device - */ - -#if defined(CONFIG_MTD_SMART) && defined(CONFIG_FS_SMARTFS) - smart_initialize(CONFIG_STM32F429I_DISCO_RAMMTD_MINOR, mtd, NULL); -#endif - } - -#endif /* CONFIG_RAMMTD && CONFIG_STM32F429I_DISCO_RAMMTD */ - -#ifdef HAVE_USBHOST - /* Initialize USB host operation. stm32_usbhost_initialize() starts a - * thread will monitor for USB connection and disconnection events. - */ - - ret = stm32_usbhost_initialize(); - if (ret != OK) - { - syslog(LOG_ERR, "ERROR: Failed to initialize USB host: %d\n", ret); - return ret; - } -#endif - -#ifdef HAVE_USBMONITOR - /* Start the USB Monitor */ - - ret = usbmonitor_start(); - if (ret != OK) - { - syslog(LOG_ERR, "ERROR: Failed to start USB monitor: %d\n", ret); - } -#endif - -#ifdef CONFIG_INPUT_BUTTONS_LOWER - /* Register the BUTTON driver */ - - ret = btn_lower_initialize("/dev/buttons"); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: btn_lower_initialize() failed: %d\n", ret); - } -#endif /* CONFIG_INPUT_BUTTONS_LOWER */ - -#ifdef CONFIG_INPUT_STMPE811 - /* Initialize the touchscreen */ - - ret = stm32_tsc_setup(0); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_tsc_setup failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_SENSORS_L3GD20 - ret = board_l3gd20_initialize(0, 5); - if (ret != OK) - { - syslog(LOG_ERR, "ERROR: Failed to initialize l3gd20 sensor:" - " %d\n", ret); - } -#endif - -#ifdef CONFIG_PWM - /* Initialize PWM and register the PWM device. */ - - ret = stm32_pwm_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_pwm_setup() failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_ADC - /* Initialize ADC and register the ADC device. */ - - ret = stm32_adc_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_adc_setup() failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_STM32_CAN_CHARDRIVER - /* Initialize CAN and register the CAN driver. */ - - ret = stm32_can_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_can_setup failed: %d\n", ret); - } -#endif - - UNUSED(ret); - return OK; -} diff --git a/boards/arm/stm32/stm32f429i-disco/src/stm32_buttons.c b/boards/arm/stm32/stm32f429i-disco/src/stm32_buttons.c deleted file mode 100644 index 314d14da7c97d..0000000000000 --- a/boards/arm/stm32/stm32f429i-disco/src/stm32_buttons.c +++ /dev/null @@ -1,150 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f429i-disco/src/stm32_buttons.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include -#include - -#include "stm32f429i-disco.h" - -#ifdef CONFIG_ARCH_BUTTONS - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* Pin configuration for each STM32F4 Discovery button. This array is indexed - * by the BUTTON_* definitions in board.h - */ - -static const uint32_t g_buttons[NUM_BUTTONS] = -{ - GPIO_BTN_USER -}; - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_button_initialize - * - * Description: - * board_button_initialize() must be called to initialize button resources. - * After that, board_buttons() may be called to collect the current state - * of all buttons or board_button_irq() may be called to register button - * interrupt handlers. - * - ****************************************************************************/ - -uint32_t board_button_initialize(void) -{ - int i; - - /* Configure the GPIO pins as inputs. NOTE that EXTI interrupts are - * configured for all pins. - */ - - for (i = 0; i < NUM_BUTTONS; i++) - { - stm32_configgpio(g_buttons[i]); - } - - return NUM_BUTTONS; -} - -/**************************************************************************** - * Name: board_buttons - ****************************************************************************/ - -uint32_t board_buttons(void) -{ - uint32_t ret = 0; - int i; - - /* Check that state of each key */ - - for (i = 0; i < NUM_BUTTONS; i++) - { - /* A LOW value means that the key is pressed. */ - - bool released = stm32_gpioread(g_buttons[i]); - - /* Accumulate the set of depressed (not released) keys */ - - if (!released) - { - ret |= (1 << i); - } - } - - return ret; -} - -/**************************************************************************** - * Button support. - * - * Description: - * board_button_initialize() must be called to initialize button resources. - * After that, board_buttons() may be called to collect the current state - * of all buttons or board_button_irq() may be called to register button - * interrupt handlers. - * - * After board_button_initialize() has been called, board_buttons() may be - * called to collect the state of all buttons. board_buttons() returns an - * 32-bit bit set with each bit associated with a button. See the - * BUTTON_*_BIT definitions in board.h for the meaning of each bit. - * - * board_button_irq() may be called to register an interrupt handler that - * will be called when a button is depressed or released. The ID value is a - * button enumeration value that uniquely identifies a button resource. See - * the BUTTON_* definitions in board.h for the meaning of enumeration - * value. - * - ****************************************************************************/ - -#ifdef CONFIG_ARCH_IRQBUTTONS -int board_button_irq(int id, xcpt_t irqhandler, void *arg) -{ - int ret = -EINVAL; - - /* The following should be atomic */ - - if (id >= MIN_IRQBUTTON && id <= MAX_IRQBUTTON) - { - ret = stm32_gpiosetevent(g_buttons[id], true, true, true, - irqhandler, arg); - } - - return ret; -} -#endif -#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/stm32/stm32f429i-disco/src/stm32_can.c b/boards/arm/stm32/stm32f429i-disco/src/stm32_can.c deleted file mode 100644 index 68464531cc54e..0000000000000 --- a/boards/arm/stm32/stm32f429i-disco/src/stm32_can.c +++ /dev/null @@ -1,102 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f429i-disco/src/stm32_can.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32.h" -#include "stm32_can.h" -#include "stm32f429i-disco.h" - -#ifdef CONFIG_CAN - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -#if defined(CONFIG_STM32_CAN1) && defined(CONFIG_STM32_CAN2) -# warning "Both CAN1 and CAN2 are enabled. Assuming only CAN1." -# undef CONFIG_STM32_CAN2 -#endif - -#ifdef CONFIG_STM32_CAN1 -# define CAN_PORT 1 -#else -# define CAN_PORT 2 -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_can_setup - * - * Description: - * Initialize CAN and register the CAN device - * - ****************************************************************************/ - -int stm32_can_setup(void) -{ -#if defined(CONFIG_STM32_CAN1) || defined(CONFIG_STM32_CAN2) - struct can_dev_s *can; - int ret; - - /* Call stm32_caninitialize() to get an instance of the CAN interface */ - - can = stm32_caninitialize(CAN_PORT); - if (can == NULL) - { - canerr("ERROR: Failed to get CAN interface\n"); - return -ENODEV; - } - - /* Register the CAN driver at "/dev/can0" */ - - ret = can_register("/dev/can0", can); - if (ret < 0) - { - canerr("ERROR: can_register failed: %d\n", ret); - return ret; - } - - return OK; -#else - return -ENODEV; -#endif -} - -#endif /* CONFIG_CAN */ diff --git a/boards/arm/stm32/stm32f429i-disco/src/stm32_extmem.c b/boards/arm/stm32/stm32f429i-disco/src/stm32_extmem.c deleted file mode 100644 index c74f2bb1ce9de..0000000000000 --- a/boards/arm/stm32/stm32f429i-disco/src/stm32_extmem.c +++ /dev/null @@ -1,178 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f429i-disco/src/stm32_extmem.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32.h" -#include "stm32f429i-disco.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#ifndef CONFIG_STM32_FMC -#warning "FMC is not enabled" -#endif - -#if STM32_NGPIO_PORTS < 6 -#error "Required GPIO ports not enabled" -#endif - -#define STM32_SDRAM_CLKEN FMC_SDCMR_CMD_CLK_ENABLE | FMC_SDCMR_BANK_2 - -#define STM32_SDRAM_PALL FMC_SDCMR_CMD_PALL | FMC_SDCMR_BANK_2 - -#define STM32_SDRAM_REFRESH FMC_SDCMR_CMD_AUTO_REFRESH | FMC_SDCMR_BANK_2 |\ - FMC_SDCMR_NRFS(4) - -#define STM32_SDRAM_MODEREG FMC_SDCMR_CMD_LOAD_MODE | FMC_SDCMR_BANK_2 |\ - FMC_SDCMR_MDR_BURST_LENGTH_2 | \ - FMC_SDCMR_MDR_BURST_TYPE_SEQUENTIAL |\ - FMC_SDCMR_MDR_CAS_LATENCY_3 |\ - FMC_SDCMR_MDR_WBL_SINGLE - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* GPIO configurations common to most external memories */ - -static const uint32_t g_sdram_config[] = -{ - /* 16 data lines */ - - GPIO_FMC_D0, GPIO_FMC_D1, GPIO_FMC_D2, GPIO_FMC_D3, - GPIO_FMC_D4, GPIO_FMC_D5, GPIO_FMC_D6, GPIO_FMC_D7, - GPIO_FMC_D8, GPIO_FMC_D9, GPIO_FMC_D10, GPIO_FMC_D11, - GPIO_FMC_D12, GPIO_FMC_D13, GPIO_FMC_D14, GPIO_FMC_D15, - - /* 12 address lines */ - - GPIO_FMC_A0, GPIO_FMC_A1, GPIO_FMC_A2, GPIO_FMC_A3, - GPIO_FMC_A4, GPIO_FMC_A5, GPIO_FMC_A6, GPIO_FMC_A7, - GPIO_FMC_A8, GPIO_FMC_A9, GPIO_FMC_A10, GPIO_FMC_A11, - - /* control lines */ - - GPIO_FMC_SDCKE1, GPIO_FMC_SDNE1, GPIO_FMC_SDNWE, GPIO_FMC_NBL0, - GPIO_FMC_SDNRAS, GPIO_FMC_NBL1, GPIO_FMC_BA0, GPIO_FMC_BA1, - GPIO_FMC_SDCLK, GPIO_FMC_SDNCAS, -}; - -#define NUM_SDRAM_GPIOS (sizeof(g_sdram_config) / sizeof(uint32_t)) - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_sdram_initialize - * - * Description: - * Called from stm32_bringup to initialize external SDRAM access. - * - ****************************************************************************/ - -void stm32_sdram_initialize(void) -{ - uint32_t val; - int i; - volatile int count; - - /* Enable GPIOs as FMC / memory pins */ - - for (i = 0; i < NUM_SDRAM_GPIOS; i++) - { - stm32_configgpio(g_sdram_config[i]); - } - - /* Enable AHB clocking to the FMC */ - - stm32_fmc_enable(); - - /* Configure and enable the SDRAM bank1 - * - * FMC clock = 180MHz/2 = 90MHz - * 90MHz = 11,11 ns - * All timings from the datasheet for Speedgrade -7 (=7ns) - */ - - val = FMC_SDCR_RPIPE_1 | /* rpipe = 1 hclk */ - FMC_SDCR_SDCLK_2X | /* sdclk = 2 hclk */ - FMC_SDCR_CAS_LATENCY_3 | /* cas latency = 3 cycles */ - FMC_SDCR_NBANKS_4 | /* 4 internal banks */ - FMC_SDCR_WIDTH_16 | /* width = 16 bits */ - FMC_SDCR_ROWS_12 | /* numrows = 12 */ - FMC_SDCR_COLS_8; /* numcols = 8 bits */ - stm32_fmc_sdram_set_control(1, val); - stm32_fmc_sdram_set_control(2, val); - - val = FMC_SDTR_TRCD(3) | /* tRCD min = 15ns */ - FMC_SDTR_TRP(3) | /* tRP min = 15ns */ - FMC_SDTR_TWR(3) | /* tWR = 2CLK */ - FMC_SDTR_TRC(8) | /* tRC min = 63ns */ - FMC_SDTR_TRAS(5) | /* tRAS min = 42ns */ - FMC_SDTR_TXSR(8) | /* tXSR min = 70ns */ - FMC_SDTR_TMRD(3); /* tMRD = 2CLK */ - stm32_fmc_sdram_set_timing(2, val); - - /* SDRAM Initialization sequence */ - - stm32_fmc_sdram_command(STM32_SDRAM_CLKEN); /* Clock enable command */ - for (count = 0; count < 10000; count++); /* Delay */ - stm32_fmc_sdram_command(STM32_SDRAM_PALL); /* Precharge ALL command */ - stm32_fmc_sdram_command(STM32_SDRAM_REFRESH); /* Auto refresh command */ - stm32_fmc_sdram_command(STM32_SDRAM_MODEREG); /* Mode Register program */ - - /* Set refresh count - * - * FMC_CLK = 90MHz - * Refresh_Rate = 7.81us - * Counter = (FMC_CLK * Refresh_Rate) - 20 - */ - - stm32_fmc_sdram_set_refresh_rate(683); - - /* Disable write protection */ - - /* stm32_fmc_sdram_write_protect(2, false); */ -} diff --git a/boards/arm/stm32/stm32f429i-disco/src/stm32_highpri.c b/boards/arm/stm32/stm32f429i-disco/src/stm32_highpri.c deleted file mode 100644 index 1a40a0bb80329..0000000000000 --- a/boards/arm/stm32/stm32f429i-disco/src/stm32_highpri.c +++ /dev/null @@ -1,535 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f429i-disco/src/stm32_highpri.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include - -#include -#include - -#include "arm_internal.h" -#include "ram_vectors.h" - -#include "stm32_pwm.h" -#include "stm32_adc.h" -#include "stm32_dma.h" - -#include -#ifdef CONFIG_STM32F429I_DISCO_HIGHPRI - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -#ifndef CONFIG_ARCH_HIPRI_INTERRUPT -# error CONFIG_ARCH_HIPRI_INTERRUPT is required -#endif - -#ifndef CONFIG_ARCH_RAMVECTORS -# error CONFIG_ARCH_RAMVECTORS is required -#endif - -#ifndef CONFIG_ARCH_IRQPRIO -# error CONFIG_ARCH_IRQPRIO is required -#endif - -#ifndef CONFIG_ARCH_FPU -# warning Set CONFIG_ARCH_FPU for hardware FPU support -#endif - -#ifdef CONFIG_STM32_ADC1_DMA -# if defined(CONFIG_STM32_TIM1_PWM) -# define HIGHPRI_HAVE_TIM1 -# endif -# if (CONFIG_STM32_ADC1_DMA_CFG != 1) -# error ADC1 DMA must be configured in Circular Mode -# endif -# if !defined(HIGHPRI_HAVE_TIM1) -# error "Needs TIM1 to trigger ADC DMA" -# endif -#endif - -#if (CONFIG_STM32_ADC1_INJECTED_CHAN > 0) -# if (CONFIG_STM32_ADC1_INJECTED_CHAN > 1) -# error Max 1 injected channels supported for now -# else -# define HIGHPRI_HAVE_INJECTED -# endif -#endif - -#ifdef HIGHPRI_HAVE_INJECTED -# define INJ_NCHANNELS CONFIG_STM32_ADC1_INJECTED_CHAN -#else -# define INJ_NCHANNELS (0) -#endif - -#ifndef CONFIG_STM32_ADC1_DMA -# define REG_NCHANNELS (1) -#else -# define REG_NCHANNELS (1) -#endif - -#define ADC1_NCHANNELS (REG_NCHANNELS + INJ_NCHANNELS) - -#define DEV1_PORT (1) -#define DEV1_NCHANNELS ADC1_NCHANNELS -#define ADC_REF_VOLTAGE (3.3f) -#define ADC_VAL_MAX (4095) - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/* High priority example private data */ - -struct highpri_s -{ - struct stm32_adc_dev_s *adc1; -#ifdef HIGHPRI_HAVE_TIM1 - struct stm32_pwm_dev_s *pwm; -#endif - volatile uint32_t cntr1; - volatile uint32_t cntr2; - volatile uint8_t current; - uint16_t r_val[REG_NCHANNELS]; - float r_volt[REG_NCHANNELS]; -#ifdef HIGHPRI_HAVE_INJECTED - uint16_t j_val[INJ_NCHANNELS]; - float j_volt[INJ_NCHANNELS]; -#endif - bool lock; -}; - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* ADC channel list */ - -static const uint8_t g_chanlist1[DEV1_NCHANNELS] = -{ - 5, -#if INJ_NCHANNELS > 0 - 13, -#endif -}; - -/* Configurations of pins used by ADC channel */ - -static const uint32_t g_pinlist1[DEV1_NCHANNELS] = -{ - GPIO_ADC1_IN5_0, /* PA5 */ -#if INJ_NCHANNELS > 0 - GPIO_ADC1_IN13_0, /* PC3 */ -#endif -}; - -static struct highpri_s g_highpri; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: adc12_handler - * - * Description: - * This is the handler for the high speed ADC interrupt. - * - ****************************************************************************/ - -#if !defined(CONFIG_STM32_ADC1_DMA) || defined(HIGHPRI_HAVE_INJECTED) -void adc_handler(void) -{ - struct stm32_adc_dev_s *adc = g_highpri.adc1; - float ref = ADC_REF_VOLTAGE; - float bit = ADC_VAL_MAX; - uint32_t pending; -#ifdef HIGHPRI_HAVE_INJECTED - int i = 0; -#endif - - /* Get pending ADC1 interrupts */ - - pending = STM32_ADC_INT_GET(adc); - - if (g_highpri.lock == true) - { - goto irq_out; - } - -#ifndef CONFIG_STM32_ADC1_DMA - /* Regular channel end of conversion */ - - if (pending & ADC_ISR_EOC) - { - /* Increase regular sequence counter */ - - g_highpri.cntr1 += 1; - - /* Get regular data */ - - g_highpri.r_val[g_highpri.current] = STM32_ADC_REGDATA_GET(adc); - - /* Do some floating point operations */ - - g_highpri.r_volt[g_highpri.current] = - (float)g_highpri.r_val[g_highpri.current] * ref / bit; - - if (g_highpri.current >= REG_NCHANNELS - 1) - { - g_highpri.current = 0; - } - else - { - g_highpri.current += 1; - } - } -#endif - -#ifdef HIGHPRI_HAVE_INJECTED - /* Injected channel end of sequence */ - - if (pending & ADC_ISR_JEOC) - { - /* Increase injected sequence counter */ - - g_highpri.cntr2 += 1; - - /* Get injected channels */ - - for (i = 0; i < INJ_NCHANNELS; i += 1) - { - g_highpri.j_val[i] = STM32_ADC_INJDATA_GET(adc, i); - } - - /* Do some floating point operations */ - - for (i = 0; i < INJ_NCHANNELS; i += 1) - { - g_highpri.j_volt[i] = (float)g_highpri.j_val[i] * ref / bit; - } - } -#endif - -irq_out: - - /* Clear ADC pending interrupts */ - - STM32_ADC_INT_ACK(adc, pending); -} -#endif - -/**************************************************************************** - * Name: dma2s0_handler - * - * Description: - * This is the handler for the high speed ADC interrupt using DMA transfer. - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_ADC1_DMA -void dma2s0_handler(void) -{ - float ref = ADC_REF_VOLTAGE; - float bit = ADC_VAL_MAX; - uint8_t pending; - int i; - - pending = stm32_dma_intget(DMA2, DMA_STREAM0); - - if (g_highpri.lock == true) - { - goto irq_out; - } - - /* Increase regular sequence counter */ - - g_highpri.cntr1 += 1; - - for (i = 0; i < REG_NCHANNELS; i += 1) - { - /* Do some floating point operations */ - - g_highpri.r_volt[i] = (float)g_highpri.r_val[i] * ref / bit; - } - -irq_out: - - /* Clear DMA pending interrupts */ - - stm32_dma_intack(DMA2, DMA_STREAM0, pending); -} -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: highpri_main - * - * Description: - * Main entry point in into the high priority interrupt test. - * - ****************************************************************************/ - -int highpri_main(int argc, char *argv[]) -{ -#ifdef HIGHPRI_HAVE_TIM1 - struct stm32_pwm_dev_s *pwm1; -#endif - struct adc_dev_s *adc1; - struct highpri_s *highpri; - int ret; - int i; - - highpri = &g_highpri; - - /* Initialize highpri structure */ - - memset(highpri, 0, sizeof(struct highpri_s)); - - printf("\nhighpri_main: Started\n"); - - /* Configure the pins as analog inputs for the selected channels */ - - for (i = 0; i < DEV1_NCHANNELS; i++) - { - stm32_configgpio(g_pinlist1[i]); - } - - /* Initialize ADC driver */ - - adc1 = stm32_adcinitialize(DEV1_PORT, g_chanlist1, DEV1_NCHANNELS); - if (adc1 == NULL) - { - aerr("ERROR: Failed to get ADC interface 1\n"); - ret = EXIT_FAILURE; - goto errout; - } - - highpri->adc1 = (struct stm32_adc_dev_s *)adc1->ad_priv; - -#ifdef HIGHPRI_HAVE_TIM1 - /* Initialize TIM1 */ - - pwm1 = (struct stm32_pwm_dev_s *) stm32_pwminitialize(1); - if (pwm1 == NULL) - { - printf("ERROR: Failed to get PWM1 interface\n"); - ret = EXIT_FAILURE; - goto errout; - } - - highpri->pwm = pwm1; - - /* Setup PWM device */ - - PWM_SETUP(pwm1); - - /* Set timer frequency */ - - PWM_FREQ_UPDATE(pwm1, 1000); - - /* Set CCR1 */ - - PWM_CCR_UPDATE(pwm1, 1, 0x0f00); - - /* Enable TIM1 OUT1 */ - - PWM_OUTPUTS_ENABLE(pwm1, STM32_PWM_OUT1, true); - -#ifdef CONFIG_DEBUG_PWM_INFO - /* Print debug */ - - PWM_DUMP_REGS(pwm1); -#endif - -#endif /* HIGHPRI_HAVE_TIM1 */ - -#if !defined(CONFIG_STM32_ADC1_DMA) || defined(HIGHPRI_HAVE_INJECTED) - /* Attach ADC ram vector if no DMA or injected channels support */ - - ret = arm_ramvec_attach(STM32_IRQ_ADC, adc_handler); - if (ret < 0) - { - fprintf(stderr, "highpri_main: ERROR: arm_ramvec_attach failed: %d\n", - ret); - ret = EXIT_FAILURE; - goto errout; - } - - /* Set the priority of the ADC interrupt vector */ - - ret = up_prioritize_irq(STM32_IRQ_ADC, NVIC_SYSH_HIGH_PRIORITY); - if (ret < 0) - { - fprintf(stderr, "highpri_main: ERROR: up_prioritize_irq failed: %d\n", - ret); - ret = EXIT_FAILURE; - goto errout; - } - - up_enable_irq(STM32_IRQ_ADC); -#endif - -#ifdef CONFIG_STM32_ADC1_DMA - /* Attach DMA2 STREAM0 ram vector if DMA */ - - ret = arm_ramvec_attach(STM32_IRQ_DMA2S0, dma2s0_handler); - if (ret < 0) - { - fprintf(stderr, "highpri_main: ERROR: arm_ramvec_attach failed: %d\n", - ret); - ret = EXIT_FAILURE; - goto errout; - } - - /* Set the priority of the DMA2 STREAM0 interrupt vector */ - - ret = up_prioritize_irq(STM32_IRQ_DMA2S0, NVIC_SYSH_HIGH_PRIORITY); - if (ret < 0) - { - fprintf(stderr, "highpri_main: ERROR: up_prioritize_irq failed: %d\n", - ret); - ret = EXIT_FAILURE; - goto errout; - } - - up_enable_irq(STM32_IRQ_DMA2S0); -#endif - - /* Setup ADC hardware */ - - adc1->ad_ops->ao_setup(adc1); - - /* Configure regular channels trigger to T1CC1 */ - - STM32_ADC_EXTCFG_SET(highpri->adc1, - ADC1_EXTSEL_T1CC1 | ADC_EXTREG_EXTEN_DEFAULT); - -#ifndef CONFIG_STM32_ADC1_DMA - /* Enable ADC regular conversion interrupts if no DMA */ - - STM32_ADC_INT_ENABLE(highpri->adc1, ADC_IER_EOC); -#else - /* Note: ADC and DMA must be reset after overrun occurs. - * For this example we assume that overrun will not occur. - * This is true only if DMA and ADC trigger are properly configured. - * DMA configuration must be done before ADC trigger starts! - */ - - /* Register ADC buffer for DMA transfer */ - - STM32_ADC_REGBUF_REGISTER(highpri->adc1, g_highpri.r_val, REG_NCHANNELS); -#endif - -#ifdef HIGHPRI_HAVE_INJECTED - /* Enable ADC injected channels end of conversion interrupts */ - - STM32_ADC_INT_ENABLE(highpri->adc1, ADC_IER_JEOC); -#endif - -#ifdef HIGHPRI_HAVE_TIM1 - /* Enable timer counter after ADC and DMA configuration */ - - PWM_TIM_ENABLE(pwm1, true); -#endif - - while (1) - { -#ifndef CONFIG_STM32_ADC1_DMA - /* Software trigger for regular sequence */ - - adc1->ad_ops->ao_ioctl(adc1, IO_TRIGGER_REG, 0); - - nxsched_usleep(100); -#endif - -#ifdef HIGHPRI_HAVE_INJECTED - /* Software trigger for injected sequence */ - - adc1->ad_ops->ao_ioctl(adc1, IO_TRIGGER_INJ, 0); - - nxsched_usleep(100); -#endif - /* Lock global data */ - - g_highpri.lock = true; - -#ifndef CONFIG_STM32_ADC1_DMA - printf("%" PRId32 " [%d] %0.3fV\n", g_highpri.cntr1, g_highpri.current, - g_highpri.r_volt[g_highpri.current]); -#else - printf("%" PRId32 " ", g_highpri.cntr1); - - for (i = 0; i < REG_NCHANNELS; i += 1) - { - printf("r:[%d] %0.3fV, ", i, g_highpri.r_volt[i]); - } - - printf("\n"); -#endif - -#ifdef HIGHPRI_HAVE_INJECTED - /* Print data from injected channels */ - - printf("%" PRId32 " ", g_highpri.cntr2); - - for (i = 0; i < INJ_NCHANNELS; i += 1) - { - printf("j:[%d] %0.3fV, ", i, g_highpri.j_volt[i]); - } - - printf("\n"); -#endif - /* Unlock global data */ - - g_highpri.lock = false; - - nxsched_sleep(1); - } - -errout: - return ret; -} - -#endif /* CONFIG_STM32F429I_DISCO_HIGHPRI */ diff --git a/boards/arm/stm32/stm32f429i-disco/src/stm32_idle.c b/boards/arm/stm32/stm32f429i-disco/src/stm32_idle.c deleted file mode 100644 index 2daac96d2b727..0000000000000 --- a/boards/arm/stm32/stm32f429i-disco/src/stm32_idle.c +++ /dev/null @@ -1,263 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f429i-disco/src/stm32_idle.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include - -#include - -#include -#include -#include -#include - -#include - -#include "arm_internal.h" -#include "stm32_pm.h" -#include "stm32_rcc.h" -#include "stm32_exti.h" - -#include "stm32f429i-disco.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -/* Does the board support an IDLE LED to indicate that the board is in the - * IDLE state? - */ - -#if defined(CONFIG_ARCH_LEDS) && defined(LED_IDLE) -# define BEGIN_IDLE() board_autoled_on(LED_IDLE) -# define END_IDLE() board_autoled_off(LED_IDLE) -#else -# define BEGIN_IDLE() -# define END_IDLE() -#endif - -/* Values for the RTC Alarm to wake up from the PM_STANDBY mode */ - -#ifndef CONFIG_PM_ALARM_SEC -# define CONFIG_PM_ALARM_SEC 3 -#endif - -#ifndef CONFIG_PM_ALARM_NSEC -# define CONFIG_PM_ALARM_NSEC 0 -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -#if defined(CONFIG_PM) && defined(CONFIG_RTC_ALARM) -static void stm32_alarmcb(void); -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_idlepm - * - * Description: - * Perform IDLE state power management. - * - ****************************************************************************/ - -#ifdef CONFIG_PM -static void stm32_idlepm(void) -{ -#ifdef CONFIG_RTC_ALARM - struct timespec alarmtime; -#endif - static enum pm_state_e oldstate = PM_NORMAL; - enum pm_state_e newstate; - irqstate_t flags; - int ret; - - /* Decide, which power saving level can be obtained */ - - newstate = pm_checkstate(PM_IDLE_DOMAIN); - - /* Check for state changes */ - - if (newstate != oldstate) - { - sinfo("newstate= %d oldstate=%d\n", newstate, oldstate); - - flags = enter_critical_section(); - - /* Force the global state change */ - - ret = pm_changestate(PM_IDLE_DOMAIN, newstate); - if (ret < 0) - { - /* The new state change failed, revert to the preceding state */ - - pm_changestate(PM_IDLE_DOMAIN, oldstate); - - /* No state change... */ - - goto errout; - } - - /* Then perform board-specific, state-dependent logic here */ - - switch (newstate) - { - case PM_NORMAL: - { - } - break; - - case PM_IDLE: - { - } - break; - - case PM_STANDBY: - { -#ifdef CONFIG_RTC_ALARM - /* Disable RTC Alarm interrupt */ - -#warning "missing logic" - - /* Configure the RTC alarm to Auto Wake the system */ - -#warning "missing logic" - - /* The tv_nsec value must not exceed 1,000,000,000. That - * would be an invalid time. - */ - -#warning "missing logic" - - /* Set the alarm */ - -#warning "missing logic" -#endif - /* Call the STM32 stop mode */ - - stm32_pmstop(true); - - /* We have been re-awakened by some even: A button press? - * An alarm? Cancel any pending alarm and resume the normal - * operation. - */ - -#ifdef CONFIG_RTC_ALARM -#warning "missing logic" -#endif - /* Resume normal operation */ - - pm_changestate(PM_IDLE_DOMAIN, PM_NORMAL); - newstate = PM_NORMAL; - } - break; - - case PM_SLEEP: - { - /* We should not return from standby mode. The only way out - * of standby is via the reset path. - */ - - stm32_pmstandby(); - } - break; - - default: - break; - } - - /* Save the new state */ - - oldstate = newstate; - -errout: - leave_critical_section(flags); - } -} -#else -# define stm32_idlepm() -#endif - -/**************************************************************************** - * Name: stm32_alarmcb - * - * Description: - * RTC alarm service routine - * - ****************************************************************************/ - -#if defined(CONFIG_PM) && defined(CONFIG_RTC_ALARM) -static void stm32_alarmcb(void) -{ - /* This alarm occurs because there wasn't any EXTI interrupt during the - * PM_STANDBY period. So just go to sleep. - */ - - pm_changestate(PM_IDLE_DOMAIN, PM_SLEEP); -} -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: up_idle - * - * Description: - * up_idle() is the logic that will be executed when their is no other - * ready-to-run task. This is processor idle time and will continue until - * some interrupt occurs to cause a context switch from the idle task. - * - * Processing in this state may be processor-specific. e.g., this is where - * power management operations might be performed. - * - ****************************************************************************/ - -void up_idle(void) -{ -#if defined(CONFIG_SUPPRESS_INTERRUPTS) || defined(CONFIG_SUPPRESS_TIMER_INTS) - /* If the system is idle and there are no timer interrupts, then process - * "fake" timer interrupts. Hopefully, something will wake up. - */ - - nxsched_process_timer(); -#else - - /* Perform IDLE mode power management */ - - BEGIN_IDLE(); - stm32_idlepm(); - END_IDLE(); -#endif -} diff --git a/boards/arm/stm32/stm32f429i-disco/src/stm32_lcd.c b/boards/arm/stm32/stm32f429i-disco/src/stm32_lcd.c deleted file mode 100644 index 07dd27571ebc6..0000000000000 --- a/boards/arm/stm32/stm32f429i-disco/src/stm32_lcd.c +++ /dev/null @@ -1,576 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f429i-disco/src/stm32_lcd.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include -#include -#include - -#include - -#include "arm_internal.h" -#include "stm32f429i-disco.h" -#include "stm32_ltdc.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#ifdef CONFIG_STM32F429I_DISCO_ILI9341_LCDDEVICE -# define ILI9341_LCD_DEVICE CONFIG_STM32F429I_DISCO_ILI9341_LCDDEVICE -#else -# define ILI9341_LCD_DEVICE 0 -#endif - -#ifdef CONFIG_STM32F429I_DISCO_ILI9341_FBIFACE - -/* Display settings */ - -/* Pixel Format Set (COLMOD) - * - * Note! RGB interface settings (DPI) is unimportant for the MCU interface - * mode but set the register to the defined state equal to the MCU interface - * pixel format. - * - * 16 Bit MCU: 01100101 / h65 - * - * DPI: 6 (RGB18-666 RGB interface) - * DBI: 5 (RGB16-565 MCU interface, not used set to default) - */ - -#define STM32_ILI9341_PIXSET_PARAM (ILI9341_PIXEL_FORMAT_SET_DPI(6) | \ - ILI9341_PIXEL_FORMAT_SET_DBI(5)) - -/* DE Mode RCM = 2, Sync Mode RCM = 3 - * Interface Mode Control - * - * EPL: 0 High enable for RGB interface - * DPL: 1 data fetched at the falling time - * HSPL: 0 Low level sync clock - * VSPL: 0 Low level sync clock - * RCM: 2 (DE Mode) - * ByPass_Mode: 1 (Memory) - */ - -#define STM32_ILI9341_IFMODE_PARAM (ILI9341_INTERFACE_CONTROL_DPL | \ - ILI9341_INTERFACE_CONTROL_RCM(2) | \ - ILI9341_INTERFACE_CONTROL_BPASS) - -/* Interface control (IFCTL) - * - * Parameter 1: 0x0001 - * MY_EOR: 0 - * MX_EOR: 0 - * MV_EOR: 0 - * BGR_EOR: 0 - * WEMODE: 1 Reset column and page if data transfer exceeds - */ - -#define STM32_ILI9341_IFCTL_PARAM1 (ILI9341_INTERFACE_CONTROL_WEMODE) - -/* Parameter 2: 0x0000 - * - * EPF: 0 65k color format for RGB interface - * MDT: 0 Display data transfer mode - * - */ -#define STM32_ILI9341_IFCTL_PARAM2 (ILI9341_INTERFACE_CONTROL_MDT(0) | \ - ILI9341_INTERFACE_CONTROL_EPF(0)) - -/* Parameter 3: 0x0000/0x0020 - * - * ENDIAN: 0 Big endian - * DM: 1 RGB Interface Mode - * RM: 1 RGB interface - * RIM: 0 18-bit 1 transfer/pixel RGB interface mode - * - */ -#define STM32_ILI9341_IFCTL_PARAM3 (ILI9341_INTERFACE_CONTROL_RM | \ - ILI9341_INTERFACE_CONTROL_DM(1)) - -/* Memory access control (MADCTL) */ - -/* Landscape: 00100000 / 00101000 / h28 - * - * MY: 0 - * MX: 0 - * MV: 1 - * ML: 0 - * BGR: 0/1 Depending on endian mode of the mcu? - * MH: 0 - */ - -#define ILI9341_MADCTL_LANDSCAPE_MY 0 -#define ILI9341_MADCTL_LANDSCAPE_MX 0 -#define ILI9341_MADCTL_LANDSCAPE_MV ILI9341_MEMORY_ACCESS_CONTROL_MV -#define ILI9341_MADCTL_LANDSCAPE_ML 0 -#ifdef CONFIG_ENDIAN_BIG -# define ILI9341_MADCTL_LANDSCAPE_BGR 0 -#else -# define ILI9341_MADCTL_LANDSCAPE_BGR ILI9341_MEMORY_ACCESS_CONTROL_BGR -#endif -#define ILI9341_MADCTL_LANDSCAPE_MH 0 - -#define ILI9341_MADCTL_LANDSCAPE_PARAM1 (ILI9341_MADCTL_LANDSCAPE_MY | \ - ILI9341_MADCTL_LANDSCAPE_MX | \ - ILI9341_MADCTL_LANDSCAPE_MV | \ - ILI9341_MADCTL_LANDSCAPE_ML | \ - ILI9341_MADCTL_LANDSCAPE_BGR | \ - ILI9341_MADCTL_LANDSCAPE_MH) - -/* Portrait: 00000000 / 00001000 / h08 - * - * MY: 0 - * MX: 0 - * MV: 0 - * ML: 0 - * BGR: 0/1 Depending on endian mode of the mcu? - * MH: 0 - */ - -#define ILI9341_MADCTL_PORTRAIT_MY 0 -#define ILI9341_MADCTL_PORTRAIT_MX ILI9341_MEMORY_ACCESS_CONTROL_MX -#define ILI9341_MADCTL_PORTRAIT_MV 0 -#define ILI9341_MADCTL_PORTRAIT_ML 0 -#ifdef CONFIG_ENDIAN_BIG -# define ILI9341_MADCTL_PORTRAIT_BGR 0 -#else -# define ILI9341_MADCTL_PORTRAIT_BGR ILI9341_MEMORY_ACCESS_CONTROL_BGR -#endif -#define ILI9341_MADCTL_PORTRAIT_MH 0 - -#define ILI9341_MADCTL_PORTRAIT_PARAM1 (ILI9341_MADCTL_PORTRAIT_MY | \ - ILI9341_MADCTL_PORTRAIT_MX | \ - ILI9341_MADCTL_PORTRAIT_MV | \ - ILI9341_MADCTL_PORTRAIT_ML | \ - ILI9341_MADCTL_PORTRAIT_BGR | \ - ILI9341_MADCTL_PORTRAIT_MH) - -/* RLandscape: 01100000 / 01101000 / h68 - * - * MY: 0 - * MX: 1 - * MV: 1 - * ML: 0 - * BGR: 0/1 Depending on endian mode of the mcu? - * MH: 0 - */ - -#define ILI9341_MADCTL_RLANDSCAPE_MY 0 -#define ILI9341_MADCTL_RLANDSCAPE_MX ILI9341_MEMORY_ACCESS_CONTROL_MX -#define ILI9341_MADCTL_RLANDSCAPE_MV ILI9341_MEMORY_ACCESS_CONTROL_MV -#define ILI9341_MADCTL_RLANDSCAPE_ML 0 -#ifdef CONFIG_ENDIAN_BIG -# define ILI9341_MADCTL_RLANDSCAPE_BGR 0 -#else -# define ILI9341_MADCTL_RLANDSCAPE_BGR ILI9341_MEMORY_ACCESS_CONTROL_BGR -#endif -#define ILI9341_MADCTL_RLANDSCAPE_MH 0 - -#define ILI9341_MADCTL_RLANDSCAPE_PARAM1 \ - (ILI9341_MADCTL_RLANDSCAPE_MY | \ - ILI9341_MADCTL_RLANDSCAPE_MX | \ - ILI9341_MADCTL_RLANDSCAPE_MV | \ - ILI9341_MADCTL_RLANDSCAPE_ML | \ - ILI9341_MADCTL_RLANDSCAPE_BGR | \ - ILI9341_MADCTL_RLANDSCAPE_MH) - -/* RPortrait: 11000000 / 11001000 / hc8 - * - * MY: 1 - * MX: 1 - * MV: 0 - * ML: 0 - * BGR: 0/1 Depending on endian mode of the mcu? - * MH: 0 - * - */ - -#define ILI9341_MADCTL_RPORTRAIT_MY ILI9341_MEMORY_ACCESS_CONTROL_MY -#define ILI9341_MADCTL_RPORTRAIT_MX 0 -#define ILI9341_MADCTL_RPORTRAIT_MV 0 -#define ILI9341_MADCTL_RPORTRAIT_ML 0 -#ifdef CONFIG_ENDIAN_BIG -# define ILI9341_MADCTL_RPORTRAIT_BGR 0 -#else -# define ILI9341_MADCTL_RPORTRAIT_BGR ILI9341_MEMORY_ACCESS_CONTROL_BGR -#endif -#define ILI9341_MADCTL_RPORTRAIT_MH 0 - -#define ILI9341_MADCTL_RPORTRAIT_PARAM1 (ILI9341_MADCTL_RPORTRAIT_MY | \ - ILI9341_MADCTL_RPORTRAIT_MX | \ - ILI9341_MADCTL_RPORTRAIT_MV | \ - ILI9341_MADCTL_RPORTRAIT_ML | \ - ILI9341_MADCTL_RPORTRAIT_BGR | \ - ILI9341_MADCTL_RPORTRAIT_MH) - -/* Set the display orientation */ - -#if defined(CONFIG_STM32F429I_DISCO_ILI9341_FBIFACE_LANDSCAPE) -# define STM32_ILI9341_MADCTL_PARAM ILI9341_MADCTL_LANDSCAPE_PARAM1 -# warning "ILI9341 doesn't support full landscape with RGB interface" -#elif defined(CONFIG_STM32F429I_DISCO_ILI9341_FBIFACE_PORTRAIT) -# define STM32_ILI9341_MADCTL_PARAM ILI9341_MADCTL_PORTRAIT_PARAM1 -#elif defined(CONFIG_STM32F429I_DISCO_ILI9341_FBIFACE_RLANDSCAPE) -# define STM32_ILI9341_MADCTL_PARAM ILI9341_MADCTL_RLANDSCAPE_PARAM1 -# warning "ILI9341 doesn't support full landscape with RGB interface" -#elif defined(CONFIG_STM32F429I_DISCO_ILI9341_FBIFACE_RPORTRAIT) -# define STM32_ILI9341_MADCTL_PARAM ILI9341_MADCTL_RPORTRAIT_PARAM1 -#else -# error "display orientation not defined" -#endif - -#define ILI9341_XRES BOARD_LTDC_WIDTH -#define ILI9341_YRES BOARD_LTDC_HEIGHT -#endif /* CONFIG_STM32F429I_DISCO_ILI9341_FBIFACE */ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -#ifdef CONFIG_STM32F429I_DISCO_ILI9341_LCDIFACE -struct lcd_dev_s *g_lcd = NULL; -#endif - -#ifdef CONFIG_STM32F429I_DISCO_ILI9341_FBIFACE -struct ili9341_lcd_s *g_ltdc = NULL; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -#ifdef CONFIG_STM32F429I_DISCO_ILI9341_FBIFACE -/**************************************************************************** - * Name: stm32_ili9341_initialize - * - * Description: - * Initialize the ili9341 LCD controller to the RGB interface mode. - * - ****************************************************************************/ - -static int stm32_ili9341_initialize(void) -{ - struct ili9341_lcd_s *lcd = g_ltdc; - - lcd = stm32_ili93414ws_initialize(); - - if (lcd == NULL) - { - return ENODEV; - } - - /* Select spi device */ - - lcdinfo("Initialize ili9341 lcd driver\n"); - lcd->select(lcd); - -#ifdef CONFIG_DEBUG_LCD_INFO - /* Read display identification */ - - uint8_t param; - lcd->sendcmd(lcd, ILI9341_READ_ID1); - lcd->recvparam(lcd, ¶m); - lcdinfo("ili9341 LCD driver: LCD modules manufacturer ID: %d\n", param); - - lcd->sendcmd(lcd, ILI9341_READ_ID2); - lcd->recvparam(lcd, ¶m); - lcdinfo("ili9341 LCD driver: LCD modules driver version ID: %d\n", param); - - lcd->sendcmd(lcd, ILI9341_READ_ID3); - lcd->recvparam(lcd, ¶m); - lcdinfo("ili9341 LCD driver: LCD modules driver ID: %d\n", param); -#endif - - /* Reset the lcd display to the default state */ - - lcdinfo("ili9341 LCD driver: Software Reset\n"); - lcd->sendcmd(lcd, ILI9341_SOFTWARE_RESET); - up_mdelay(5); - - lcdinfo("ili9341 LCD driver: set Memory Access Control %08x\n", - STM32_ILI9341_MADCTL_PARAM); - lcd->sendcmd(lcd, ILI9341_MEMORY_ACCESS_CONTROL); - lcd->sendparam(lcd, STM32_ILI9341_MADCTL_PARAM); - - /* Pixel Format */ - - lcdinfo("ili9341 LCD driver: Set Pixel Format: %02x\n", - STM32_ILI9341_PIXSET_PARAM); - lcd->sendcmd(lcd, ILI9341_PIXEL_FORMAT_SET); - lcd->sendparam(lcd, STM32_ILI9341_PIXSET_PARAM); - - /* Select column */ - - lcdinfo("ili9341 LCD driver: Set Column Address\n"); - lcd->sendcmd(lcd, ILI9341_COLUMN_ADDRESS_SET); - lcd->sendparam(lcd, 0); - lcd->sendparam(lcd, 0); - lcd->sendparam(lcd, (ILI9341_XRES >> 8)); - lcd->sendparam(lcd, (ILI9341_XRES & 0xff)); - - /* Select page */ - - lcdinfo("ili9341 LCD driver: Set Page Address\n"); - lcd->sendcmd(lcd, ILI9341_PAGE_ADDRESS_SET); - lcd->sendparam(lcd, 0); - lcd->sendparam(lcd, 0); - lcd->sendparam(lcd, (ILI9341_YRES >> 8)); - lcd->sendparam(lcd, (ILI9341_YRES & 0xff)); - - /* RGB Interface signal control */ - - lcdinfo("ili9341 LCD driver: Set RGB Interface signal control: %02x\n", - STM32_ILI9341_IFMODE_PARAM); - lcd->sendcmd(lcd, ILI9341_RGB_SIGNAL_CONTROL); - lcd->sendparam(lcd, STM32_ILI9341_IFMODE_PARAM); - - /* Interface control */ - - lcdinfo("ili9341 LCD driver: Set Interface control: %d:%d:%d\n", - STM32_ILI9341_IFCTL_PARAM1, - STM32_ILI9341_IFCTL_PARAM2, - STM32_ILI9341_IFCTL_PARAM3); - - lcd->sendcmd(lcd, ILI9341_INTERFACE_CONTROL); - lcd->sendparam(lcd, STM32_ILI9341_IFCTL_PARAM1); - lcd->sendparam(lcd, STM32_ILI9341_IFCTL_PARAM2); - lcd->sendparam(lcd, STM32_ILI9341_IFCTL_PARAM3); - - /* Sleep out set to the end */ - - lcdinfo("ili9341 LCD driver: Sleep Out\n"); - lcd->sendcmd(lcd, ILI9341_SLEEP_OUT); - up_mdelay(5); /* 120? */ - - /* Display on */ - - lcdinfo("ili9341 LCD driver: Display On\n"); - lcd->sendcmd(lcd, ILI9341_DISPLAY_ON); - - /* Deselect spi device */ - - lcd->deselect(lcd); - - return OK; -} -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -#ifdef CONFIG_STM32F429I_DISCO_ILI9341_LCDIFACE -/**************************************************************************** - * Name: board_lcd_uninitialize - * - * Description: - * Uninitialize the LCD Device. - * - * Input Parameters: - * - * Returned Value: - * - ****************************************************************************/ - -void board_lcd_uninitialize(void) -{ - /* Set display off */ - - g_lcd->setpower(g_lcd, 0); - - g_lcd = NULL; -} - -/**************************************************************************** - * Name: board_lcd_getdev - * - * Description: - * Return a reference to the LCD object for the specified LCD Device. - * This allows support for multiple LCD devices. - * - * Input Parameters: - * lcddev - Number of the LDC Device. - * - * Returned Value: - * Reference to the LCD object if exist otherwise NULL - * - ****************************************************************************/ - -struct lcd_dev_s *board_lcd_getdev(int lcddev) -{ - if (lcddev == ILI9341_LCD_DEVICE) - { - return g_lcd; - } - - return NULL; -} - -/**************************************************************************** - * Name: board_lcd_initialize - * - * Description: - * Initialize the LCD video hardware. The initial state of the LCD is - * fully initialized, display memory cleared, and the LCD ready to use, but - * with the power setting at 0 (full off). - * - * Input Parameters: - * - * Returned Value: - * On success - Ok - * On error - Error Code - * - ****************************************************************************/ - -int board_lcd_initialize(void) -{ - /* check if always initialized */ - - if (!g_lcd) - { - /* Initialize the sub driver structure */ - - struct ili9341_lcd_s *dev = stm32_ili93414ws_initialize(); - - /* Initialize public lcd driver structure */ - - if (dev) - { - /* Get a reference to valid lcd driver structure to avoid repeated - * initialization of the LCD Device. Also enables uninitializing of - * the LCD Device. - */ - - g_lcd = ili9341_initialize(dev, ILI9341_LCD_DEVICE); - if (g_lcd) - { - return OK; - } - } - - return -ENODEV; - } - - return OK; -} -#endif /* CONFIG_STM32F429I_DISCO_ILI9341_LCDIFACE */ - -#ifdef CONFIG_STM32_LTDC -/**************************************************************************** - * Name: up_fbinitialize - * - * Description: - * Initialize the framebuffer video hardware associated with the display. - * - * Input Parameters: - * display - In the case of hardware with multiple displays, this - * specifies the display. Normally this is zero. - * - * Returned Value: - * Zero is returned on success; a negated errno value is returned on any - * failure. - * - ****************************************************************************/ - -int up_fbinitialize(int display) -{ - static bool initialized = false; - int ret = OK; - - if (!initialized) - { -#ifdef CONFIG_STM32F429I_DISCO_ILI9341_FBIFACE - /* Initialize the ili9341 LCD controller */ - - ret = stm32_ili9341_initialize(); - if (ret >= OK) - { - ret = stm32_ltdcinitialize(); - } - -#else - /* Custom LCD display with RGB interface */ - - ret = stm32_ltdcinitialize(); -#endif - - initialized = (ret >= OK); - } - - return ret; -} - -/**************************************************************************** - * Name: up_fbgetvplane - * - * Description: - * Return a a reference to the framebuffer object for the specified video - * plane of the specified plane. - * Many OSDs support multiple planes of video. - * - * Input Parameters: - * display - In the case of hardware with multiple displays, this - * specifies the display. Normally this is zero. - * vplane - Identifies the plane being queried. - * - * Returned Value: - * A non-NULL pointer to the frame buffer access structure is returned on - * success; NULL is returned on any failure. - * - ****************************************************************************/ - -struct fb_vtable_s *up_fbgetvplane(int display, int vplane) -{ - return stm32_ltdcgetvplane(vplane); -} - -/**************************************************************************** - * Name: up_fbuninitialize - * - * Description: - * Uninitialize the framebuffer support for the specified display. - * - * Input Parameters: - * display - In the case of hardware with multiple displays, this - * specifies the display. Normally this is zero. - * - * Returned Value: - * None - * - ****************************************************************************/ - -void up_fbuninitialize(int display) -{ - stm32_ltdcuninitialize(); -} -#endif /* CONFIG_STM32_LTDC */ diff --git a/boards/arm/stm32/stm32f429i-disco/src/stm32_pwm.c b/boards/arm/stm32/stm32f429i-disco/src/stm32_pwm.c deleted file mode 100644 index 9ce1aab6c4229..0000000000000 --- a/boards/arm/stm32/stm32f429i-disco/src/stm32_pwm.c +++ /dev/null @@ -1,116 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f429i-disco/src/stm32_pwm.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32_pwm.h" -#include "stm32f429i-disco.h" - -#include - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -/* PWM Timer */ - -#define STM32F429IDISCO_PWMTIMER 1 - -#define HAVE_PWM 1 - -#ifndef CONFIG_PWM -# undef HAVE_PWM -#endif - -#ifndef CONFIG_STM32_TIM1 -# undef HAVE_PWM -#endif - -#ifndef CONFIG_STM32_TIM1_PWM -# undef HAVE_PWM -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_pwm_setup - * - * Description: - * Initialize PWM and register the PWM device. - * - ****************************************************************************/ - -int stm32_pwm_setup(void) -{ -#ifdef HAVE_PWM - static bool initialized = false; - struct pwm_lowerhalf_s *pwm; - int ret; - - /* Have we already initialized? */ - - if (!initialized) - { - /* Call stm32_pwminitialize() to get an instance of the PWM interface */ - - pwm = stm32_pwminitialize(STM32F429IDISCO_PWMTIMER); - if (!pwm) - { - tmrerr("ERROR: Failed to get the STM32 PWM lower half\n"); - return -ENODEV; - } - - /* Register the PWM driver at "/dev/pwm0" */ - - ret = pwm_register("/dev/pwm0", pwm); - if (ret < 0) - { - tmrerr("ERROR: pwm_register failed: %d\n", ret); - return ret; - } - - /* Now we are initialized */ - - initialized = true; - } - - return OK; -#else - return -ENODEV; -#endif -} diff --git a/boards/arm/stm32/stm32f429i-disco/src/stm32_spi.c b/boards/arm/stm32/stm32f429i-disco/src/stm32_spi.c deleted file mode 100644 index 940f4af472ae5..0000000000000 --- a/boards/arm/stm32/stm32f429i-disco/src/stm32_spi.c +++ /dev/null @@ -1,299 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f429i-disco/src/stm32_spi.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include - -#include -#include - -#include "arm_internal.h" -#include "chip.h" -#include "stm32.h" -#include "stm32f429i-disco.h" - -#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || defined(CONFIG_STM32_SPI3) ||\ - defined(CONFIG_STM32_SPI4) || defined(CONFIG_STM32_SPI5) - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -#ifdef CONFIG_STM32_SPI5 -struct spi_dev_s *g_spidev5 = NULL; -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_spidev_initialize - * - * Description: - * Called to configure SPI chip select GPIO pins for the stm32f429i-disco - * board. - * - ****************************************************************************/ - -void weak_function stm32_spidev_initialize(void) -{ -#ifdef CONFIG_STM32_SPI5 - stm32_configgpio(GPIO_CS_MEMS); /* MEMS chip select */ - stm32_configgpio(GPIO_CS_LCD); /* LCD chip select */ - stm32_configgpio(GPIO_LCD_DC); /* LCD Data/Command select */ - stm32_configgpio(GPIO_LCD_ENABLE); /* LCD enable select */ -#endif -#if defined(CONFIG_STM32_SPI4) && defined(CONFIG_MTD_SST25XX) - stm32_configgpio(GPIO_CS_SST25); /* SST25 FLASH chip select */ -#endif -} - -/**************************************************************************** - * Name: stm32_spi1/2/3/4/5select and stm32_spi1/2/3/4/5status - * - * Description: - * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status - * must be provided by board-specific logic. They are implementations of - * the select and status methods of the SPI interface defined by struct - * spi_ops_s (see include/nuttx/spi/spi.h). All other methods (including - * stm32_spibus_initialize()) are provided by common STM32 logic. - * To use this common SPI logic on your board: - * - * 1. Provide logic in stm32_boardinitialize() to configure SPI chip - * select pins. - * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() functions - * in your board-specific logic. These functions will perform chip - * selection and status operations using GPIOs in the way your board is - * configured. - * 3. Add a calls to stm32_spibus_initialize() in your low level - * application initialization logic - * 4. The handle returned by stm32_spibus_initialize() may then be used to - * bind the SPI driver to higher level logic (e.g., calling - * mmcsd_spislotinitialize(), for example, will bind the SPI driver to - * the SPI MMC/SD driver). - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_SPI1 -void stm32_spi1select(struct spi_dev_s *dev, - uint32_t devid, - bool selected) -{ - spiinfo("devid: %d CS: %s\n", - (int)devid, selected ? "assert" : "de-assert"); -} - -uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) -{ - return 0; -} -#endif - -#ifdef CONFIG_STM32_SPI2 -void stm32_spi2select(struct spi_dev_s *dev, - uint32_t devid, - bool selected) -{ - spiinfo("devid: %d CS: %s\n", - (int)devid, selected ? "assert" : "de-assert"); -} - -uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) -{ - return 0; -} -#endif - -#ifdef CONFIG_STM32_SPI3 -void stm32_spi3select(struct spi_dev_s *dev, - uint32_t devid, bool selected) -{ - spiinfo("devid: %d CS: %s\n", - (int)devid, selected ? "assert" : "de-assert"); -} - -uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid) -{ - return 0; -} -#endif - -#ifdef CONFIG_STM32_SPI4 -void stm32_spi4select(struct spi_dev_s *dev, - uint32_t devid, bool selected) -{ -#if defined(CONFIG_MTD_SST25XX) - if (devid == SPIDEV_FLASH(0)) - { - stm32_gpiowrite(GPIO_CS_SST25, !selected); - } -#endif -} - -uint8_t stm32_spi4status(struct spi_dev_s *dev, uint32_t devid) -{ - return 0; -} -#endif - -#ifdef CONFIG_STM32_SPI5 -void stm32_spi5select(struct spi_dev_s *dev, - uint32_t devid, bool selected) -{ - spiinfo("devid: %d CS: %s\n", - (int)devid, selected ? "assert" : "de-assert"); - -#if defined(CONFIG_STM32F429I_DISCO_ILI9341) - if (devid == SPIDEV_DISPLAY(0)) - { - stm32_gpiowrite(GPIO_CS_LCD, !selected); - } - else -#endif - - { - stm32_gpiowrite(GPIO_CS_MEMS, !selected); - } -} - -uint8_t stm32_spi5status(struct spi_dev_s *dev, uint32_t devid) -{ - return 0; -} -#endif - -/**************************************************************************** - * Name: stm32_spi1cmddata - * - * Description: - * Set or clear the SH1101A A0 or SD1306 D/C n bit to select data (true) - * or command (false). This function must be provided by platform-specific - * logic. This is an implementation of the cmddata method of the SPI - * interface defined by struct spi_ops_s (see include/nuttx/spi/spi.h). - * - * Input Parameters: - * - * spi - SPI device that controls the bus the device that requires the CMD/ - * DATA selection. - * devid - If there are multiple devices on the bus, this selects which one - * to select cmd or data. NOTE: This design restricts, for example, - * one one SPI display per SPI bus. - * cmd - true: select command; false: select data - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef CONFIG_SPI_CMDDATA -#ifdef CONFIG_STM32_SPI1 -int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) -{ - return -ENODEV; -} -#endif - -#ifdef CONFIG_STM32_SPI2 -int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) -{ - return -ENODEV; -} -#endif - -#ifdef CONFIG_STM32_SPI3 -int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) -{ - return -ENODEV; -} -#endif - -#ifdef CONFIG_STM32_SPI4 -int stm32_spi4cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) -{ - return -ENODEV; -} -#endif - -#ifdef CONFIG_STM32_SPI5 -int stm32_spi5cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) -{ -#if defined(CONFIG_STM32F429I_DISCO_ILI9341) - if (devid == SPIDEV_DISPLAY(0)) - { - /* This is the Data/Command control pad which determines whether the - * data bits are data or a command. - */ - - stm32_gpiowrite(GPIO_LCD_DC, !cmd); - - return OK; - } -#endif - - return -ENODEV; -} -#endif - -#endif /* CONFIG_SPI_CMDDATA */ - -/**************************************************************************** - * Name: stm32_spi5initialize - * - * Description: - * Initialize the selected SPI port. - * As long as the method stm32_spibus_initialize recognized the initialized - * state of the spi device by the spi enable flag of the cr1 register, it - * isn't safe to disable the spi device outside of the nuttx spi interface - * structure. But this has to be done as long as the nuttx spi interface - * doesn't support bidirectional data transfer for multiple devices share - * one spi bus. This wrapper does nothing else than store the initialized - * state of the spi device after the first initializing and should be used - * by each driver who shares the spi5 bus. - * - * Input Parameters: - * - * Returned Value: - * Valid SPI device structure reference on success; a NULL on failure - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_SPI5 -struct spi_dev_s *stm32_spi5initialize(void) -{ - if (!g_spidev5) - { - g_spidev5 = stm32_spibus_initialize(5); - } - - return g_spidev5; -} -#endif -#endif /* CONFIG_STM32_SPI1 || ... CONFIG_STM32_SPI5 */ diff --git a/boards/arm/stm32/stm32f429i-disco/src/stm32_stmpe811.c b/boards/arm/stm32/stm32f429i-disco/src/stm32_stmpe811.c deleted file mode 100644 index 9179d51fc3fb0..0000000000000 --- a/boards/arm/stm32/stm32f429i-disco/src/stm32_stmpe811.c +++ /dev/null @@ -1,337 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f429i-disco/src/stm32_stmpe811.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -#include - -#include "stm32.h" -#include "stm32f429i-disco.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -#ifdef CONFIG_INPUT_STMPE811 -#ifndef CONFIG_INPUT -# error "STMPE811 support requires CONFIG_INPUT" -#endif - -#ifndef CONFIG_STM32_I2C3 -# error "STMPE811 support requires CONFIG_STM32_I2C3" -#endif - -#ifndef CONFIG_STMPE811_I2C -# error "Only the STMPE811 I2C interface is supported" -#endif - -#ifdef CONFIG_STMPE811_SPI -# error "Only the STMPE811 SPI interface is supported" -#endif - -#ifndef CONFIG_STMPE811_FREQUENCY -# define CONFIG_STMPE811_FREQUENCY 100000 -#endif - -#ifndef CONFIG_STMPE811_I2CDEV -# define CONFIG_STMPE811_I2CDEV 3 -#endif - -#if CONFIG_STMPE811_I2CDEV != 3 -# error "CONFIG_STMPE811_I2CDEV must be three" -#endif - -#ifndef CONFIG_STMPE811_DEVMINOR -# define CONFIG_STMPE811_DEVMINOR 0 -#endif - -/* Board definitions ********************************************************/ - -/* The STM3240G-EVAL has two STMPE811QTR I/O expanders on board both - * connected to the STM32 via I2C1. They share a common interrupt line: PI2. - * - * STMPE811 U24, I2C address 0x41 (7-bit) - * ------ ---- ---------------- -------------------------------------------- - * STPE11 PIN BOARD SIGNAL BOARD CONNECTION - * ------ ---- ---------------- -------------------------------------------- - * Y- TouchScreen_Y- LCD Connector XL - * X- TouchScreen_X- LCD Connector XR - * Y+ TouchScreen_Y+ LCD Connector XD - * X+ TouchScreen_X+ LCD Connector XU - * IN3 EXP_IO9 - * IN2 EXP_IO10 - * IN1 EXP_IO11 - * IN0 EXP_IO12 - * - * STMPE811 U29, I2C address 0x44 (7-bit) - * ------ ---- ---------------- -------------------------------------------- - * STPE11 PIN BOARD SIGNAL BOARD CONNECTION - * ------ ---- ---------------- -------------------------------------------- - * Y- EXP_IO1 - * X- EXP_IO2 - * Y+ EXP_IO3 - * X+ EXP_IO4 - * IN3 EXP_IO5 - * IN2 EXP_IO6 - * IN1 EXP_IO7 - * IN0 EXP_IO8 - */ - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -struct stm32_stmpe811config_s -{ - /* Configuration structure as seen by the STMPE811 driver */ - - struct stmpe811_config_s config; - - /* Additional private definitions only known to this driver */ - - STMPE811_HANDLE handle; /* The STMPE811 driver handle */ - xcpt_t handler; /* The STMPE811 interrupt handler */ - void *arg; /* Interrupt handler argument */ -}; - -/**************************************************************************** - * Static Function Prototypes - ****************************************************************************/ - -/* IRQ/GPIO access callbacks. These operations all hidden behind callbacks - * to isolate the STMPE811 driver from differences in GPIO - * interrupt handling by varying boards and MCUs.* so that contact and loss- - * of-contact events can be detected. - * - * attach - Attach the STMPE811 interrupt handler to the GPIO interrupt - * enable - Enable or disable the GPIO interrupt - * clear - Acknowledge/clear any pending GPIO interrupt - */ - -static int stmpe811_attach(struct stmpe811_config_s *state, xcpt_t isr, - void *arg); -static void stmpe811_enable(struct stmpe811_config_s *state, - bool enable); -static void stmpe811_clear(struct stmpe811_config_s *state); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* A reference to a structure of this type must be passed to the STMPE811 - * driver. This structure provides information about the configuration - * of the STMPE811 and provides some board-specific hooks. - * - * Memory for this structure is provided by the caller. It is not copied - * by the driver and is presumed to persist while the driver is active. The - * memory must be writable because, under certain circumstances, the driver - * may modify frequency or X plate resistance values. - */ - -#ifndef CONFIG_STMPE811_TSC_DISABLE -static struct stm32_stmpe811config_s g_stmpe811config = -{ - .config = - { -#ifdef CONFIG_STMPE811_I2C - .address = STMPE811_ADDR1, -#endif - .frequency = CONFIG_STMPE811_FREQUENCY, - -#ifdef CONFIG_STMPE811_MULTIPLE - .irq = STM32_IRQ_EXTI2, -#endif - .ctrl1 = (ADC_CTRL1_SAMPLE_TIME_80 | ADC_CTRL1_MOD_12B), - .ctrl2 = ADC_CTRL2_ADC_FREQ_3p25, - - .attach = stmpe811_attach, - .enable = stmpe811_enable, - .clear = stmpe811_clear, - }, - .handler = NULL, - .arg = NULL, -}; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/* IRQ/GPIO access callbacks. These operations all hidden behind - * callbacks to isolate the STMPE811 driver from differences in GPIO - * interrupt handling by varying boards and MCUs. - * - * attach - Attach the STMPE811 interrupt handler to the GPIO interrupt - * enable - Enable or disable the GPIO interrupt - * clear - Acknowledge/clear any pending GPIO interrupt - */ - -static int stmpe811_attach(struct stmpe811_config_s *state, xcpt_t isr, - void *arg) -{ - struct stm32_stmpe811config_s *priv = - (struct stm32_stmpe811config_s *)state; - - iinfo("Saving handler %p\n", isr); - DEBUGASSERT(priv); - - /* Just save the handler. We will use it when EXTI interruptsare enabled */ - - priv->handler = isr; - priv->arg = arg; - return OK; -} - -static void stmpe811_enable(struct stmpe811_config_s *state, bool enable) -{ - struct stm32_stmpe811config_s *priv = - (struct stm32_stmpe811config_s *)state; - irqstate_t flags; - - /* Attach and enable, or detach and disable. Enabling and disabling GPIO - * interrupts is a multi-step process so the safest thing is to keep - * interrupts disabled during the reconfiguration. - */ - - flags = enter_critical_section(); - if (enable) - { - /* Configure the EXTI interrupt using the SAVED handler */ - - stm32_gpiosetevent(GPIO_IO_EXPANDER, true, true, true, - priv->handler, priv->arg); - } - else - { - /* Configure the EXTI interrupt with a NULL handler to disable it */ - - stm32_gpiosetevent(GPIO_IO_EXPANDER, false, false, false, - NULL, NULL); - } - - leave_critical_section(flags); -} - -static void stmpe811_clear(struct stmpe811_config_s *state) -{ - /* Does nothing */ -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_tsc_setup - * - * Description: - * This function is called by board-bringup logic to configure the - * touchscreen device. This function will register the driver as - * /dev/inputN where N is the minor device number. - * - * Input Parameters: - * minor - The input device minor number - * - * Returned Value: - * Zero is returned on success. Otherwise, a negated errno value is - * returned to indicate the nature of the failure. - * - ****************************************************************************/ - -int stm32_tsc_setup(int minor) -{ -#ifndef CONFIG_STMPE811_TSC_DISABLE - struct i2c_master_s *dev; - int ret; - - iinfo("minor %d\n", minor); - DEBUGASSERT(minor == 0); - - /* Check if we are already initialized */ - - if (!g_stmpe811config.handle) - { - iinfo("Initializing\n"); - - /* Configure the STMPE811 interrupt pin as an input */ - - stm32_configgpio(GPIO_IO_EXPANDER); - - /* Get an instance of the I2C interface */ - - dev = stm32_i2cbus_initialize(CONFIG_STMPE811_I2CDEV); - if (!dev) - { - ierr("ERROR: Failed to initialize I2C bus %d\n", - CONFIG_STMPE811_I2CDEV); - return -ENODEV; - } - - /* Instantiate the STMPE811 driver */ - - g_stmpe811config.handle = - stmpe811_instantiate(dev, - (struct stmpe811_config_s *)&g_stmpe811config); - if (!g_stmpe811config.handle) - { - ierr("ERROR: Failed to instantiate the STMPE811 driver\n"); - return -ENODEV; - } - - /* Initialize and register the I2C touchscreen device */ - - ret = stmpe811_register(g_stmpe811config.handle, - CONFIG_STMPE811_DEVMINOR); - if (ret < 0) - { - ierr("ERROR: Failed to register STMPE driver: %d\n", ret); - - /* stm32_i2cbus_uninitialize(dev); */ - - return -ENODEV; - } - } - - return OK; -#else - return -ENOSYS; -#endif -} - -#endif /* CONFIG_INPUT_STMPE811 */ diff --git a/boards/arm/stm32/stm32f429i-disco/src/stm32_usb.c b/boards/arm/stm32/stm32f429i-disco/src/stm32_usb.c deleted file mode 100644 index 3178d70af9ec4..0000000000000 --- a/boards/arm/stm32/stm32f429i-disco/src/stm32_usb.c +++ /dev/null @@ -1,310 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f429i-disco/src/stm32_usb.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -#include "arm_internal.h" -#include "stm32.h" -#include "stm32_otghs.h" -#include "stm32f429i-disco.h" - -#ifdef CONFIG_STM32_OTGHS - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#if defined(CONFIG_USBDEV) || defined(CONFIG_USBHOST) -# define HAVE_USB 1 -#else -# warning "CONFIG_STM32_OTGHS is enabled but neither CONFIG_USBDEV nor CONFIG_USBHOST" -# undef HAVE_USB -#endif - -#ifndef CONFIG_STM32F429IDISCO_USBHOST_PRIO -# define CONFIG_STM32F429IDISCO_USBHOST_PRIO 100 -#endif - -#ifndef CONFIG_STM32F429IDISCO_USBHOST_STACKSIZE -# define CONFIG_STM32F429IDISCO_USBHOST_STACKSIZE 1024 -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -#ifdef CONFIG_USBHOST -static struct usbhost_connection_s *g_usbconn; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: usbhost_waiter - * - * Description: - * Wait for USB devices to be connected. - * - ****************************************************************************/ - -#ifdef CONFIG_USBHOST -static int usbhost_waiter(int argc, char *argv[]) -{ - struct usbhost_hubport_s *hport; - - uinfo("Running\n"); - for (; ; ) - { - /* Wait for the device to change state */ - - DEBUGVERIFY(CONN_WAIT(g_usbconn, &hport)); - uinfo("%s\n", hport->connected ? "connected" : "disconnected"); - - /* Did we just become connected? */ - - if (hport->connected) - { - /* Yes.. enumerate the newly connected device */ - - CONN_ENUMERATE(g_usbconn, hport); - } - } - - /* Keep the compiler from complaining */ - - return 0; -} -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_usbinitialize - * - * Description: - * Called from stm32_usbinitialize very early in initialization to setup - * USB-related GPIO pins for the STM32F4Discovery board. - * - ****************************************************************************/ - -void stm32_usbinitialize(void) -{ - /* The OTG FS has an internal soft pull-up. - * No GPIO configuration is required - */ - - /* Configure the OTG FS VBUS sensing GPIO, - * Power On, and Overcurrent GPIOs - */ - -#ifdef CONFIG_STM32_OTGHS - stm32_configgpio(GPIO_OTGHS_VBUS); - stm32_configgpio(GPIO_OTGHS_PWRON); - stm32_configgpio(GPIO_OTGHS_OVER); -#endif -} - -/**************************************************************************** - * Name: stm32_usbhost_initialize - * - * Description: - * Called at application startup time to initialize the USB host - * functionality. - * This function will start a thread that will monitor for device - * connection/disconnection events. - * - ****************************************************************************/ - -#ifdef CONFIG_USBHOST -int stm32_usbhost_initialize(void) -{ - int ret; - - /* First, register all of the class drivers needed to support the drivers - * that we care about: - */ - - uinfo("Register class drivers\n"); - -#ifdef CONFIG_USBHOST_HUB - /* Initialize USB hub class support */ - - ret = usbhost_hub_initialize(); - if (ret < 0) - { - uerr("ERROR: usbhost_hub_initialize failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_USBHOST_MSC - /* Register the USB mass storage class class */ - - ret = usbhost_msc_initialize(); - if (ret != OK) - { - uerr("ERROR: Failed to register the mass storage class: %d\n", ret); - } -#endif - -#ifdef CONFIG_USBHOST_CDCACM - /* Register the CDC/ACM serial class */ - - ret = usbhost_cdcacm_initialize(); - if (ret != OK) - { - uerr("ERROR: Failed to register the CDC/ACM serial class: %d\n", ret); - } -#endif - - /* Then get an instance of the USB host interface */ - - uinfo("Initialize USB host\n"); - g_usbconn = stm32_otghshost_initialize(0); - if (g_usbconn) - { - /* Start a thread to handle device connection. */ - - uinfo("Start usbhost_waiter\n"); - - ret = kthread_create("usbhost", CONFIG_STM32F429IDISCO_USBHOST_PRIO, - CONFIG_STM32F429IDISCO_USBHOST_STACKSIZE, - usbhost_waiter, NULL); - return ret < 0 ? -ENOEXEC : OK; - } - - return -ENODEV; -} -#endif - -/**************************************************************************** - * Name: stm32_usbhost_vbusdrive - * - * Description: - * Enable/disable driving of VBUS 5V output. This function must be - * provided be each platform that implements the STM32 OTG FS host - * interface - * - * "On-chip 5 V VBUS generation is not supported. For this reason, a - * charge pump or, if 5 V are available on the application board, a - * basic power switch, must be added externally to drive the 5 V VBUS - * line. The external charge pump can be driven by any GPIO output. - * When the application decides to power on VBUS using the chosen GPIO, - * it must also set the port power bit in the host port control and - * status register (PPWR bit in OTG_FS_HPRT). - * - * "The application uses this field to control power to this port, - * and the core clears this bit on an overcurrent condition." - * - * Input Parameters: - * iface - For future growth to handle multiple USB host interface. - * Should be zero. - * enable - true: enable VBUS power; false: disable VBUS power - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef CONFIG_USBHOST -void stm32_usbhost_vbusdrive(int iface, bool enable) -{ - DEBUGASSERT(iface == 0); - - if (enable) - { - /* Enable the Power Switch by driving the enable pin low */ - - stm32_gpiowrite(GPIO_OTGHS_PWRON, false); - } - else - { - /* Disable the Power Switch by driving the enable pin high */ - - stm32_gpiowrite(GPIO_OTGHS_PWRON, true); - } -} -#endif - -/**************************************************************************** - * Name: stm32_setup_overcurrent - * - * Description: - * Setup to receive an interrupt-level callback if an overcurrent - * condition is detected. - * - * Input Parameters: - * handler - New overcurrent interrupt handler - * arg - The argument provided for the interrupt handler - * - * Returned Value: - * Zero (OK) is returned on success. Otherwise, a negated errno value - * is returned to indicate the nature of the failure. - * - ****************************************************************************/ - -#ifdef CONFIG_USBHOST -int stm32_setup_overcurrent(xcpt_t handler, void *arg) -{ - return stm32_gpiosetevent(GPIO_OTGHS_OVER, true, true, true, handler, arg); -} -#endif - -/**************************************************************************** - * Name: stm32_usbsuspend - * - * Description: - * Board logic must provide the stm32_usbsuspend logic if the USBDEV - * driver is used. This function is called whenever the USB enters or - * leaves suspend mode. This is an opportunity for the board logic to - * shutdown clocks, power, etc. while the USB is suspended. - * - ****************************************************************************/ - -#ifdef CONFIG_USBDEV -void stm32_usbsuspend(struct usbdev_s *dev, bool resume) -{ - uinfo("resume: %d\n", resume); -} -#endif - -#endif /* CONFIG_STM32_OTGHS */ diff --git a/boards/arm/stm32/stm32f429i-disco/src/stm32_userleds.c b/boards/arm/stm32/stm32f429i-disco/src/stm32_userleds.c deleted file mode 100644 index b3d122eb03906..0000000000000 --- a/boards/arm/stm32/stm32f429i-disco/src/stm32_userleds.c +++ /dev/null @@ -1,211 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f429i-disco/src/stm32_userleds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32.h" -#include "stm32f429i-disco.h" - -#ifndef CONFIG_ARCH_LEDS - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* This array maps an LED number to GPIO pin configuration */ - -static uint32_t g_ledcfg[BOARD_NLEDS] = -{ - GPIO_LED1, GPIO_LED2 -}; - -/**************************************************************************** - * Private Function Protototypes - ****************************************************************************/ - -/* LED Power Management */ - -#ifdef CONFIG_PM -static void led_pm_notify(struct pm_callback_s *cb, int domain, - enum pm_state_e pmstate); -static int led_pm_prepare(struct pm_callback_s *cb, int domain, - enum pm_state_e pmstate); -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -#ifdef CONFIG_PM -static struct pm_callback_s g_ledscb = -{ - .notify = led_pm_notify, - .prepare = led_pm_prepare, -}; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: led_pm_notify - * - * Description: - * Notify the driver of new power state. This callback is called after - * all drivers have had the opportunity to prepare for the new power state. - * - ****************************************************************************/ - -#ifdef CONFIG_PM -static void led_pm_notify(struct pm_callback_s *cb, int domain, - enum pm_state_e pmstate) -{ - switch (pmstate) - { - case PM_NORMAL: - { - /* Restore normal LEDs operation */ - } - break; - - case PM_IDLE: - { - /* Entering IDLE mode - Turn leds off */ - } - break; - - case PM_STANDBY: - { - /* Entering STANDBY mode - Logic for PM_STANDBY goes here */ - } - break; - - case PM_SLEEP: - { - /* Entering SLEEP mode - Logic for PM_SLEEP goes here */ - } - break; - - default: - { - /* Should not get here */ - } - break; - } -} -#endif - -/**************************************************************************** - * Name: led_pm_prepare - * - * Description: - * Request the driver to prepare for a new power state. This is a warning - * that the system is about to enter into a new power state. The driver - * should begin whatever operations that may be required to enter power - * state. The driver may abort the state change mode by returning a - * non-zero value from the callback function. - * - ****************************************************************************/ - -#ifdef CONFIG_PM -static int led_pm_prepare(struct pm_callback_s *cb, int domain, - enum pm_state_e pmstate) -{ - /* No preparation to change power modes is required by the LEDs driver. - * We always accept the state change by returning OK. - */ - - return OK; -} -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_userled_initialize - ****************************************************************************/ - -uint32_t board_userled_initialize(void) -{ - /* Configure LED1-4 GPIOs for output */ - - stm32_configgpio(GPIO_LED1); - stm32_configgpio(GPIO_LED2); - return BOARD_NLEDS; -} - -/**************************************************************************** - * Name: board_userled - ****************************************************************************/ - -void board_userled(int led, bool ledon) -{ - if ((unsigned)led < BOARD_NLEDS) - { - stm32_gpiowrite(g_ledcfg[led], ledon); - } -} - -/**************************************************************************** - * Name: board_userled_all - ****************************************************************************/ - -void board_userled_all(uint32_t ledset) -{ - stm32_gpiowrite(GPIO_LED1, (ledset & BOARD_LED1_BIT) == 0); - stm32_gpiowrite(GPIO_LED2, (ledset & BOARD_LED2_BIT) == 0); -} - -/**************************************************************************** - * Name: stm32_ledpminitialize - ****************************************************************************/ - -#ifdef CONFIG_PM -void stm32_ledpminitialize(void) -{ - /* Register to receive power management callbacks */ - - int ret = pm_register(&g_ledscb); - if (ret != OK) - { - board_autoled_on(LED_ASSERTION); - } -} -#endif /* CONFIG_PM */ - -#endif /* !CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/stm32f4discovery/CMakeLists.txt b/boards/arm/stm32/stm32f4discovery/CMakeLists.txt deleted file mode 100644 index 290b7c62f75f6..0000000000000 --- a/boards/arm/stm32/stm32f4discovery/CMakeLists.txt +++ /dev/null @@ -1,30 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/stm32f4discovery/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) - -if(NOT CONFIG_BUILD_FLAT) - add_subdirectory(kernel) - set_property( - GLOBAL PROPERTY LD_SCRIPT_USER ${CMAKE_CURRENT_LIST_DIR}/scripts/memory.ld - ${CMAKE_CURRENT_LIST_DIR}/scripts/user-space.ld) -endif() diff --git a/boards/arm/stm32/stm32f4discovery/Kconfig b/boards/arm/stm32/stm32f4discovery/Kconfig deleted file mode 100644 index 084ab04bc12b9..0000000000000 --- a/boards/arm/stm32/stm32f4discovery/Kconfig +++ /dev/null @@ -1,142 +0,0 @@ -# -# For a description of the syntax of this configuration file, -# see the file kconfig-language.txt in the NuttX tools repository. -# - -if ARCH_BOARD_STM32F4_DISCOVERY - -config STM32F4DISBB - bool "STM32F4DIS-BB base board" - default n - ---help--- - Select if you are using the STM32F4DIS-BB base board with the - STM32F4Discovery. - -config STM32_ROMFS - bool "Automount baked-in ROMFS image" - default n - depends on FS_ROMFS - ---help--- - Select STM32_ROMFS_IMAGEFILE, STM32_ROMFS_DEV_MINOR, STM32_ROMFS_MOUNTPOINT - -config STM32_ROMFS_DEV_MINOR - int "Minor for the block device backing the data" - depends on STM32_ROMFS - default 64 - -config STM32_ROMFS_MOUNTPOINT - string "Mountpoint of the custom romfs image" - depends on STM32_ROMFS - default "/rom" - -config STM32_ROMFS_IMAGEFILE - string "ROMFS image file to include into build" - depends on STM32_ROMFS - default "../../../../../rom.img" - -config STM32F4DISCO_USBHOST_STACKSIZE - int "USB host waiter stack size" - default 1024 - depends on USBHOST - -config STM32F4DISCO_USBHOST_PRIO - int "USB host waiter task priority" - default 100 - depends on USBHOST - -config STM32F4DISCO_QETIMER - int "Timer to use with QE encoder" - default 2 - depends on SENSORS_QENCODER - -config STM32F4DISCO_TIMER - int "Timer to use with timer driver" - default 4 - depends on TIMER - -config STM32F4DISCO_LIS3DSH - bool "Enable LIS3DSH driver for the IMU on STM32F4Discovery (rev. MB997C)" - default n - depends on SPI - depends on LIS3DSH - default n - select SENSORS_LIS3DSH - ---help--- - Select to create a LIS3DSH driver instance for the builtin accelerometer of - STM32F4Discovery. Provides /dev/acc0 device file. - Also see apps/examples/lis3dsh_reader. - The LIS3DSH is available on the STM32F4Discovery rev. MB997C (see the board manual). - -config PM_BUTTONS - bool "PM button support" - default n - depends on PM && ARCH_IRQBUTTONS - ---help--- - Enable PM button EXTI interrupts to support PM testing - -config PM_BUTTON_ACTIVITY - int "Button PM activity weight" - default 10 - depends on PM_BUTTONS - ---help--- - The activity weight to report to the power management subsystem when - a button is pressed. - -config PM_ALARM_SEC - int "PM_STANDBY delay (seconds)" - default 15 - depends on PM && RTC_ALARM - ---help--- - Number of seconds to wait in PM_STANDBY before going to PM_STANDBY - mode. - -config PM_ALARM_NSEC - int "PM_STANDBY delay (nanoseconds)" - default 0 - depends on PM && RTC_ALARM - ---help--- - Number of additional nanoseconds to wait in PM_STANDBY before going - to PM_STANDBY mode. - -config PM_SLEEP_WAKEUP - bool "PM_SLEEP wake-up alarm" - default n - depends on PM && RTC_ALARM - ---help--- - Wake-up of PM_SLEEP mode after a delay and resume normal operation. - -config PM_SLEEP_WAKEUP_SEC - int "PM_SLEEP delay (seconds)" - default 10 - depends on PM && RTC_ALARM - ---help--- - Number of seconds to wait in PM_SLEEP before going to PM_STANDBY mode. - -config PM_SLEEP_WAKEUP_NSEC - int "PM_SLEEP delay (nanoseconds)" - default 0 - depends on PM && RTC_ALARM - ---help--- - Number of additional nanoseconds to wait in PM_SLEEP before going to - PM_STANDBY mode. - -if INPUT_KMATRIX_I2C - -config STM32_KMATRIX_I2C_BUS - int "I2C Bus Number" - default 1 - ---help--- - I2C bus number to use for the keyboard matrix GPIO expander. - Common values: 1 or 2 (depends on available I2C interfaces). - -config STM32_KMATRIX_I2C_ADDR - hex "I2C Slave Address of GPIO Expander" - default 0x20 - ---help--- - I2C slave address of the GPIO expander (PCF8574 or MCP23017). - PCF8574/MCP23017 default addresses (7-bit): - 0x20-0x27: varies with A0-A2 pins (default is 0x20) - -endif # INPUT_KMATRIX_I2C - -endif diff --git a/boards/arm/stm32/stm32f4discovery/configs/adb/defconfig b/boards/arm/stm32/stm32f4discovery/configs/adb/defconfig deleted file mode 100644 index 70765999bf7d8..0000000000000 --- a/boards/arm/stm32/stm32f4discovery/configs/adb/defconfig +++ /dev/null @@ -1,72 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -CONFIG_ADBD_FILE_SERVICE=y -CONFIG_ADBD_SHELL_SERVICE=y -CONFIG_ADBD_USB_SERVER=y -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f4discovery" -CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F407VG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARDCTL_RESET=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_DEBUG_FULLOPT=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_DEV_URANDOM=y -CONFIG_ELF=y -CONFIG_EXAMPLES_HELLO=m -CONFIG_FAT_LFN=y -CONFIG_FS_FAT=y -CONFIG_FS_FATTIME=y -CONFIG_FS_PROCFS=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INIT_STACKSIZE=3072 -CONFIG_INTELHEX_BINARY=y -CONFIG_LIBC_EXECFUNCS=y -CONFIG_LIBUV=y -CONFIG_LINE_MAX=128 -CONFIG_MMCSD=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_PSEUDOTERM=y -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_SCHED_CHILD_STATUS=y -CONFIG_SCHED_HAVE_PARENT=y -CONFIG_SCHED_LPWORK=y -CONFIG_SCHED_WAITPID=y -CONFIG_SENSORS=y -CONFIG_STACK_COLORATION=y -CONFIG_START_DAY=17 -CONFIG_START_MONTH=12 -CONFIG_START_YEAR=2020 -CONFIG_STM32_DMA2=y -CONFIG_STM32_DMACAPABLE=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_OTGFS=y -CONFIG_STM32_PWR=y -CONFIG_STM32_SPI2=y -CONFIG_STM32_USART2=y -CONFIG_SYSTEM_ADBD=y -CONFIG_SYSTEM_NSH=y -CONFIG_TLS_TASK_NELEM=4 -CONFIG_USART2_SERIAL_CONSOLE=y -CONFIG_USBADB=y -CONFIG_USBDEV=y diff --git a/boards/arm/stm32/stm32f4discovery/configs/audio/defconfig b/boards/arm/stm32/stm32f4discovery/configs/audio/defconfig deleted file mode 100644 index 7a58739b22135..0000000000000 --- a/boards/arm/stm32/stm32f4discovery/configs/audio/defconfig +++ /dev/null @@ -1,74 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f4discovery" -CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F407VG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_AUDIO=y -CONFIG_AUDIO_CS43L22=y -CONFIG_AUDIO_CUSTOM_DEV_PATH=y -CONFIG_AUDIO_EXCLUDE_TONE=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_DRIVERS_AUDIO=y -CONFIG_FAT_LCNAMES=y -CONFIG_FAT_LFN=y -CONFIG_FS_FAT=y -CONFIG_FS_PROCFS=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_I2C=y -CONFIG_I2C_DRIVER=y -CONFIG_I2C_POLLED=y -CONFIG_I2C_RESET=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_MM_REGIONS=2 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_NXPLAYER_DEFAULT_MEDIADIR="/mnt/music" -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=6 -CONFIG_START_MONTH=12 -CONFIG_START_YEAR=2011 -CONFIG_STM32_DMA1=y -CONFIG_STM32_DMACAPABLE=y -CONFIG_STM32_I2C1=y -CONFIG_STM32_I2S3=y -CONFIG_STM32_I2S3_TX=y -CONFIG_STM32_I2S_MCK=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_OTGFS=y -CONFIG_STM32_OTGFS_SOFINTR=y -CONFIG_STM32_PWR=y -CONFIG_STM32_SPI1=y -CONFIG_STM32_SPI3=y -CONFIG_STM32_USART2=y -CONFIG_STM32_USBHOST=y -CONFIG_SYSTEM_NSH=y -CONFIG_SYSTEM_NXPLAYER=y -CONFIG_USART2_RXBUFSIZE=128 -CONFIG_USART2_SERIAL_CONSOLE=y -CONFIG_USART2_TXBUFSIZE=128 -CONFIG_USBHOST_ISOC_DISABLE=y -CONFIG_USBHOST_MSC=y diff --git a/boards/arm/stm32/stm32f4discovery/configs/brickmatch/defconfig b/boards/arm/stm32/stm32f4discovery/configs/brickmatch/defconfig deleted file mode 100644 index bb8d3b332702f..0000000000000 --- a/boards/arm/stm32/stm32f4discovery/configs/brickmatch/defconfig +++ /dev/null @@ -1,66 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -# CONFIG_STM32_CCMEXCLUDE is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f4discovery" -CONFIG_ARCH_BOARD_COMMON=y -CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F407VG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_DRIVERS_VIDEO=y -CONFIG_EXAMPLES_APDS9960=y -CONFIG_EXAMPLES_FB=y -CONFIG_EXAMPLES_FB_STACKSIZE=16000 -CONFIG_EXAMPLES_HELLO=y -CONFIG_FS_LARGEFILE=y -CONFIG_FS_PROCFS=y -CONFIG_GAMES_BRICKMATCH=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LCD=y -CONFIG_LCD_APA102=y -CONFIG_LCD_APA102_FREQUENCY=10000000 -CONFIG_LCD_FRAMEBUFFER=y -CONFIG_LINE_MAX=64 -CONFIG_MM_REGIONS=2 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_LPWORK=y -CONFIG_SCHED_WAITPID=y -CONFIG_SENSORS=y -CONFIG_SENSORS_APDS9960=y -CONFIG_START_DAY=6 -CONFIG_START_MONTH=12 -CONFIG_START_YEAR=2011 -CONFIG_STM32_DMA1=y -CONFIG_STM32_I2C1=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_PWR=y -CONFIG_STM32_SPI1=y -CONFIG_STM32_USART2=y -CONFIG_SYSTEM_NSH=y -CONFIG_USART2_RXBUFSIZE=128 -CONFIG_USART2_SERIAL_CONSOLE=y -CONFIG_USART2_TXBUFSIZE=128 -CONFIG_VIDEO_FB=y diff --git a/boards/arm/stm32/stm32f4discovery/configs/canard/defconfig b/boards/arm/stm32/stm32f4discovery/configs/canard/defconfig deleted file mode 100644 index 553cc77d00240..0000000000000 --- a/boards/arm/stm32/stm32f4discovery/configs/canard/defconfig +++ /dev/null @@ -1,52 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f4discovery" -CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F407VG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_CANUTILS_LIBDRONECAN=y -CONFIG_CAN_EXTID=y -CONFIG_EXAMPLES_DRONECAN=y -CONFIG_FS_PROCFS=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_MM_REGIONS=2 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=6 -CONFIG_START_MONTH=12 -CONFIG_START_YEAR=2011 -CONFIG_STM32_CAN1=y -CONFIG_STM32_CAN1_BAUD=500000 -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_PWR=y -CONFIG_STM32_SPI1=y -CONFIG_STM32_USART2=y -CONFIG_SYSTEM_NSH=y -CONFIG_USART2_RXBUFSIZE=128 -CONFIG_USART2_SERIAL_CONSOLE=y -CONFIG_USART2_TXBUFSIZE=128 diff --git a/boards/arm/stm32/stm32f4discovery/configs/composite/defconfig b/boards/arm/stm32/stm32f4discovery/configs/composite/defconfig deleted file mode 100644 index 8485892f11c54..0000000000000 --- a/boards/arm/stm32/stm32f4discovery/configs/composite/defconfig +++ /dev/null @@ -1,99 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -# CONFIG_SPI_CALLBACK is not set -CONFIG_ALLOW_BSD_COMPONENTS=y -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f4discovery" -CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F407VG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARDCTL_RESET=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_COMPOSITE_IAD=y -CONFIG_DEBUG_FULLOPT=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_ELF=y -CONFIG_EXAMPLES_HELLO=m -CONFIG_FAT_LCNAMES=y -CONFIG_FAT_LFN=y -CONFIG_FS_FAT=y -CONFIG_FS_PROCFS=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INIT_STACKSIZE=3072 -CONFIG_INTELHEX_BINARY=y -CONFIG_LIBC_ENVPATH=y -CONFIG_LIBC_EXECFUNCS=y -CONFIG_LINE_MAX=128 -CONFIG_MMCSD=y -CONFIG_NET=y -CONFIG_NETDB_DNSCLIENT=y -CONFIG_NETDB_DNSSERVER_IPv4ADDR=0x0 -CONFIG_NETINIT_DHCPC=y -CONFIG_NETINIT_DRIPADDR=0x0 -CONFIG_NETINIT_MACADDR_1=0xdeadcafe -CONFIG_NETINIT_NETMASK=0x0 -CONFIG_NETINIT_NOMAC=y -CONFIG_NETINIT_THREAD=y -CONFIG_NETUTILS_DHCPC=y -CONFIG_NETUTILS_IPERF=y -CONFIG_NETUTILS_TELNETD=y -CONFIG_NETUTILS_WEBCLIENT=y -CONFIG_NET_BROADCAST=y -CONFIG_NET_ICMP_SOCKET=y -CONFIG_NET_LOOPBACK=y -CONFIG_NET_STATISTICS=y -CONFIG_NET_TCP=y -CONFIG_NET_TCP_WRITE_BUFFERS=y -CONFIG_NET_UDP=y -CONFIG_NFS=y -CONFIG_NFS_STATISTICS=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_FILE_APPS=y -CONFIG_NSH_READLINE=y -CONFIG_NSH_SYMTAB=y -CONFIG_NSH_SYMTAB_ARRAYNAME="g_symtab" -CONFIG_NSH_SYMTAB_COUNTNAME="g_nsymbols" -CONFIG_PATH_INITIAL="/mnt/nfs/bin" -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RNDIS=y -CONFIG_RNDIS_COMPOSITE=y -CONFIG_SCHED_LPWORK=y -CONFIG_SCHED_WAITPID=y -CONFIG_SENSORS=y -CONFIG_START_DAY=13 -CONFIG_START_MONTH=9 -CONFIG_START_YEAR=2014 -CONFIG_STM32_DMA2=y -CONFIG_STM32_DMACAPABLE=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_OTGFS=y -CONFIG_STM32_PWR=y -CONFIG_STM32_SPI2=y -CONFIG_STM32_USART2=y -CONFIG_SYMTAB_ORDEREDBYNAME=y -CONFIG_SYSTEM_COMPOSITE=y -CONFIG_SYSTEM_NSH=y -CONFIG_SYSTEM_PING=y -CONFIG_USART2_SERIAL_CONSOLE=y -CONFIG_USBDEV=y -CONFIG_USBDEV_COMPOSITE=y -CONFIG_USBMSC=y -CONFIG_USBMSC_COMPOSITE=y diff --git a/boards/arm/stm32/stm32f4discovery/configs/cxx-oot-build/defconfig b/boards/arm/stm32/stm32f4discovery/configs/cxx-oot-build/defconfig deleted file mode 100644 index 6dd62ac3583a5..0000000000000 --- a/boards/arm/stm32/stm32f4discovery/configs/cxx-oot-build/defconfig +++ /dev/null @@ -1,47 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_ARCH_LEDS is not set -# CONFIG_DISABLE_OS_API is not set -# CONFIG_SYSTEM_DD is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f4discovery" -CONFIG_ARCH_BOARD_COMMON=y -CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F407VG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_CXX_EXCEPTION=y -CONFIG_CXX_STANDARD="c++17" -CONFIG_DRVR_MKRD=y -CONFIG_FS_PROCFS=y -CONFIG_HAVE_CXX=y -CONFIG_INIT_NONE=y -CONFIG_INTELHEX_BINARY=y -CONFIG_LIBCXXTOOLCHAIN=y -CONFIG_LINE_MAX=64 -CONFIG_MM_REGIONS=2 -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=6 -CONFIG_START_MONTH=12 -CONFIG_START_YEAR=2011 -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_PWR=y -CONFIG_STM32_SPI1=y -CONFIG_STM32_USART2=y -CONFIG_USART2_RXBUFSIZE=128 -CONFIG_USART2_SERIAL_CONSOLE=y -CONFIG_USART2_TXBUFSIZE=128 diff --git a/boards/arm/stm32/stm32f4discovery/configs/cxxtest/defconfig b/boards/arm/stm32/stm32f4discovery/configs/cxxtest/defconfig deleted file mode 100644 index 9784e9650a4f4..0000000000000 --- a/boards/arm/stm32/stm32f4discovery/configs/cxxtest/defconfig +++ /dev/null @@ -1,41 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -CONFIG_ALLOW_GPL_COMPONENTS=y -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f4discovery" -CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F407VG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_DISABLE_MOUNTPOINT=y -CONFIG_HAVE_CXX=y -CONFIG_HOST_WINDOWS=y -CONFIG_INIT_ENTRYPOINT="cxxtest_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LIBC_MAX_EXITFUNS=4 -CONFIG_LIBM=y -CONFIG_MM_REGIONS=2 -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_START_DAY=2 -CONFIG_START_MONTH=11 -CONFIG_START_YEAR=2012 -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_USART2=y -CONFIG_SYMTAB_ORDEREDBYNAME=y -CONFIG_TESTING_CXXTEST=y -CONFIG_UCLIBCXX=y -CONFIG_USART2_RXBUFSIZE=128 -CONFIG_USART2_SERIAL_CONSOLE=y -CONFIG_USART2_TXBUFSIZE=128 diff --git a/boards/arm/stm32/stm32f4discovery/configs/elf/defconfig b/boards/arm/stm32/stm32f4discovery/configs/elf/defconfig deleted file mode 100644 index d67f3e5aa69aa..0000000000000 --- a/boards/arm/stm32/stm32f4discovery/configs/elf/defconfig +++ /dev/null @@ -1,43 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f4discovery" -CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F407VG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BINFMT_CONSTRUCTORS=y -CONFIG_BOARDCTL=y -CONFIG_BOARDCTL_ROMDISK=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_CONSOLE_SYSLOG=y -CONFIG_ELF=y -CONFIG_ELF_STACKSIZE=4096 -CONFIG_EXAMPLES_ELF=y -CONFIG_FS_ROMFS=y -CONFIG_HAVE_CXX=y -CONFIG_INIT_ENTRYPOINT="elf_main" -CONFIG_INIT_STACKSIZE=4096 -CONFIG_INTELHEX_BINARY=y -CONFIG_LIBC_ENVPATH=y -CONFIG_MM_REGIONS=2 -CONFIG_PATH_INITIAL="/mnt/romfs" -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_START_DAY=26 -CONFIG_START_MONTH=10 -CONFIG_START_YEAR=2012 -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_USART2=y -CONFIG_SYMTAB_ORDEREDBYNAME=y -CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/stm32f4discovery/configs/ether_w5500/defconfig b/boards/arm/stm32/stm32f4discovery/configs/ether_w5500/defconfig deleted file mode 100644 index 41f42ad54d132..0000000000000 --- a/boards/arm/stm32/stm32f4discovery/configs/ether_w5500/defconfig +++ /dev/null @@ -1,73 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f4discovery" -CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F407VG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BCH=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_EXAMPLES_HELLO=y -CONFIG_FS_PROCFS=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_MM_REGIONS=2 -CONFIG_NET=y -CONFIG_NETDB_DNSCLIENT=y -CONFIG_NETDB_DNSSERVER_NOADDR=y -CONFIG_NETINIT_DRIPADDR=0xc0a80001 -CONFIG_NETINIT_IPADDR=0xc0a80010 -CONFIG_NETINIT_NOMAC=y -CONFIG_NETUTILS_TELNETD=y -CONFIG_NETUTILS_TFTPC=y -CONFIG_NETUTILS_WEBCLIENT=y -CONFIG_NET_BROADCAST=y -CONFIG_NET_ICMP_SOCKET=y -CONFIG_NET_MAX_LISTENPORTS=16 -CONFIG_NET_STATISTICS=y -CONFIG_NET_TCP=y -CONFIG_NET_TCP_PREALLOC_CONNS=16 -CONFIG_NET_UDP=y -CONFIG_NET_UDP_CHECKSUMS=y -CONFIG_NET_W5500=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_DISABLE_IFUPDOWN=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_HPWORKPRIORITY=192 -CONFIG_SCHED_HPWORKSTACKSIZE=1024 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=6 -CONFIG_START_MONTH=12 -CONFIG_START_YEAR=2011 -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_PWR=y -CONFIG_STM32_SPI1=y -CONFIG_STM32_USART2=y -CONFIG_SYSTEM_DHCPC_RENEW=y -CONFIG_SYSTEM_NSH=y -CONFIG_SYSTEM_PING=y -CONFIG_USART2_RXBUFSIZE=128 -CONFIG_USART2_SERIAL_CONSOLE=y -CONFIG_USART2_TXBUFSIZE=128 diff --git a/boards/arm/stm32/stm32f4discovery/configs/ipv6/defconfig b/boards/arm/stm32/stm32f4discovery/configs/ipv6/defconfig deleted file mode 100644 index 910ab3e1436d6..0000000000000 --- a/boards/arm/stm32/stm32f4discovery/configs/ipv6/defconfig +++ /dev/null @@ -1,88 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_MMCSD_MMCSUPPORT is not set -# CONFIG_MMCSD_SPI is not set -# CONFIG_NET_IPv4 is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f4discovery" -CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F407VG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_ETH0_PHY_LAN8720=y -CONFIG_FAT_LCNAMES=y -CONFIG_FAT_LFN=y -CONFIG_FS_FAT=y -CONFIG_FS_PROCFS=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_HOST_WINDOWS=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LIBC_HOSTNAME="STM32F4-Discovery" -CONFIG_LINE_MAX=64 -CONFIG_MMCSD=y -CONFIG_MMCSD_MULTIBLOCK_LIMIT=1 -CONFIG_MMCSD_SDIO=y -CONFIG_NET=y -CONFIG_NETINIT_IPv6NETMASK_8=0xff80 -CONFIG_NETINIT_NOMAC=y -CONFIG_NET_BROADCAST=y -CONFIG_NET_ICMPv6=y -CONFIG_NET_ICMPv6_NEIGHBOR=y -CONFIG_NET_ICMPv6_SOCKET=y -CONFIG_NET_IPv6=y -CONFIG_NET_SOCKOPTS=y -CONFIG_NET_SOLINGER=y -CONFIG_NET_TCP=y -CONFIG_NET_TCP_WRITE_BUFFERS=y -CONFIG_NET_UDP=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_HPWORKPRIORITY=192 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=13 -CONFIG_START_MONTH=9 -CONFIG_START_YEAR=2014 -CONFIG_STM32F4DISBB=y -CONFIG_STM32_DMA2=y -CONFIG_STM32_DMACAPABLE=y -CONFIG_STM32_ETHMAC=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_PHYADDR=0 -CONFIG_STM32_PHYSR=31 -CONFIG_STM32_PHYSR_100FD=0x0018 -CONFIG_STM32_PHYSR_100HD=0x0008 -CONFIG_STM32_PHYSR_10FD=0x0014 -CONFIG_STM32_PHYSR_10HD=0x0004 -CONFIG_STM32_PHYSR_ALTCONFIG=y -CONFIG_STM32_PHYSR_ALTMODE=0x001c -CONFIG_STM32_PWR=y -CONFIG_STM32_RMII_EXTCLK=y -CONFIG_STM32_SDIO=y -CONFIG_STM32_SPI1=y -CONFIG_STM32_USART6=y -CONFIG_SYSTEM_NSH=y -CONFIG_SYSTEM_PING6=y -CONFIG_USART6_RXBUFSIZE=64 -CONFIG_USART6_SERIAL_CONSOLE=y -CONFIG_USART6_TXBUFSIZE=64 diff --git a/boards/arm/stm32/stm32f4discovery/configs/kostest/Make.defs b/boards/arm/stm32/stm32f4discovery/configs/kostest/Make.defs deleted file mode 100644 index 8905673c9792d..0000000000000 --- a/boards/arm/stm32/stm32f4discovery/configs/kostest/Make.defs +++ /dev/null @@ -1,42 +0,0 @@ -############################################################################ -# boards/arm/stm32/stm32f4discovery/configs/kostest/Make.defs -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/.config -include $(TOPDIR)/tools/Config.mk -include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs - -LDSCRIPT1 = memory.ld -LDSCRIPT2 = kernel-space.ld - -ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT1) -ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT2) - -ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 - -CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) -CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) -CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -AFLAGS := $(CFLAGS) -D__ASSEMBLY__ - -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections -LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32/stm32f4discovery/configs/kostest/defconfig b/boards/arm/stm32/stm32f4discovery/configs/kostest/defconfig deleted file mode 100644 index cc106c43eb404..0000000000000 --- a/boards/arm/stm32/stm32f4discovery/configs/kostest/defconfig +++ /dev/null @@ -1,50 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f4discovery" -CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F407VG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_ARM_MPU=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILD_PROTECTED=y -CONFIG_CONSOLE_SYSLOG=y -CONFIG_DEBUG_FULLOPT=y -CONFIG_DEBUG_HARDFAULT_ALERT=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_DISABLE_ENVIRON=y -CONFIG_DISABLE_MOUNTPOINT=y -CONFIG_IDLETHREAD_STACKSIZE=2048 -CONFIG_INIT_ENTRYPOINT="ostest_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_MM_KERNEL_HEAPSIZE=16384 -CONFIG_MM_REGIONS=2 -CONFIG_NUTTX_USERSPACE=0x08020000 -CONFIG_PASS1_BUILDIR="boards/arm/stm32/stm32f4discovery/kernel" -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_STACK_COLORATION=y -CONFIG_START_DAY=22 -CONFIG_START_MONTH=3 -CONFIG_START_YEAR=2013 -CONFIG_STM32_CCMEXCLUDE=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_USART2=y -CONFIG_SYMTAB_ORDEREDBYNAME=y -CONFIG_TESTING_OSTEST=y -CONFIG_TESTING_OSTEST_NBARRIER_THREADS=3 -CONFIG_TESTING_OSTEST_STACKSIZE=2048 -CONFIG_USART2_RXBUFSIZE=128 -CONFIG_USART2_SERIAL_CONSOLE=y -CONFIG_USART2_TXBUFSIZE=128 diff --git a/boards/arm/stm32/stm32f4discovery/configs/lcd1602/defconfig b/boards/arm/stm32/stm32f4discovery/configs/lcd1602/defconfig deleted file mode 100644 index da7f85f99a7b6..0000000000000 --- a/boards/arm/stm32/stm32f4discovery/configs/lcd1602/defconfig +++ /dev/null @@ -1,55 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f4discovery" -CONFIG_ARCH_BOARD_COMMON=y -CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F407VG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_EXAMPLES_HELLO=y -CONFIG_EXAMPLES_SLCD=y -CONFIG_FS_PROCFS=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_I2C=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LCD_BACKPACK=y -CONFIG_LCD_LCD1602=y -CONFIG_LINE_MAX=64 -CONFIG_MM_REGIONS=2 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_SLCD=y -CONFIG_START_DAY=6 -CONFIG_START_MONTH=12 -CONFIG_START_YEAR=2011 -CONFIG_STM32_I2C1=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_PWR=y -CONFIG_STM32_SPI1=y -CONFIG_STM32_USART2=y -CONFIG_SYSTEM_NSH=y -CONFIG_USART2_RXBUFSIZE=128 -CONFIG_USART2_SERIAL_CONSOLE=y -CONFIG_USART2_TXBUFSIZE=128 diff --git a/boards/arm/stm32/stm32f4discovery/configs/lwl/defconfig b/boards/arm/stm32/stm32f4discovery/configs/lwl/defconfig deleted file mode 100644 index 562e7ffef0e7f..0000000000000 --- a/boards/arm/stm32/stm32f4discovery/configs/lwl/defconfig +++ /dev/null @@ -1,46 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -# CONFIG_SERIAL is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f4discovery" -CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F407VG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_EXAMPLES_HELLO=y -CONFIG_FS_PROCFS=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_LWL_CONSOLE=y -CONFIG_MM_REGIONS=2 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=6 -CONFIG_START_MONTH=12 -CONFIG_START_YEAR=2011 -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_PWR=y -CONFIG_STM32_SPI1=y -CONFIG_SYSTEM_NSH=y diff --git a/boards/arm/stm32/stm32f4discovery/configs/max31855/defconfig b/boards/arm/stm32/stm32f4discovery/configs/max31855/defconfig deleted file mode 100644 index 05486e4a8f735..0000000000000 --- a/boards/arm/stm32/stm32f4discovery/configs/max31855/defconfig +++ /dev/null @@ -1,53 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f4discovery" -CONFIG_ARCH_BOARD_COMMON=y -CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F407VG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_EXAMPLES_MAX31855=y -CONFIG_FS_PROCFS=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_HOST_WINDOWS=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_MM_REGIONS=2 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_SENSORS=y -CONFIG_SENSORS_MAX31855=y -CONFIG_START_DAY=6 -CONFIG_START_MONTH=12 -CONFIG_START_YEAR=2011 -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_PWR=y -CONFIG_STM32_SPI1=y -CONFIG_STM32_SPI2=y -CONFIG_STM32_USART2=y -CONFIG_SYSTEM_NSH=y -CONFIG_USART2_RXBUFSIZE=128 -CONFIG_USART2_SERIAL_CONSOLE=y -CONFIG_USART2_TXBUFSIZE=128 diff --git a/boards/arm/stm32/stm32f4discovery/configs/max7219/defconfig b/boards/arm/stm32/stm32f4discovery/configs/max7219/defconfig deleted file mode 100644 index 9be5d50f0b3ce..0000000000000 --- a/boards/arm/stm32/stm32f4discovery/configs/max7219/defconfig +++ /dev/null @@ -1,91 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_DISABLE_OS_API is not set -# CONFIG_DISABLE_PSEUDOFS_OPERATIONS is not set -# CONFIG_FS_PROCFS_EXCLUDE_BLOCKS is not set -# CONFIG_FS_PROCFS_EXCLUDE_ENVIRON is not set -# CONFIG_FS_PROCFS_EXCLUDE_MEMDUMP is not set -# CONFIG_FS_PROCFS_EXCLUDE_MEMINFO is not set -# CONFIG_FS_PROCFS_EXCLUDE_MOUNT is not set -# CONFIG_FS_PROCFS_EXCLUDE_MOUNTS is not set -# CONFIG_FS_PROCFS_EXCLUDE_PROCESS is not set -# CONFIG_FS_PROCFS_EXCLUDE_UPTIME is not set -# CONFIG_FS_PROCFS_EXCLUDE_USAGE is not set -# CONFIG_FS_PROCFS_EXCLUDE_VERSION is not set -# CONFIG_FS_PROCFS_INCLUDE_PROGMEM is not set -# CONFIG_NSH_DISABLEBG is not set -# CONFIG_NSH_DISABLESCRIPT is not set -# CONFIG_NSH_DISABLE_BASENAME is not set -# CONFIG_NSH_DISABLE_CMP is not set -# CONFIG_NSH_DISABLE_DF is not set -# CONFIG_NSH_DISABLE_DIRNAME is not set -# CONFIG_NSH_DISABLE_EXEC is not set -# CONFIG_NSH_DISABLE_EXIT is not set -# CONFIG_NSH_DISABLE_GET is not set -# CONFIG_NSH_DISABLE_HEXDUMP is not set -# CONFIG_NSH_DISABLE_ITEF is not set -# CONFIG_NSH_DISABLE_LOOPS is not set -# CONFIG_NSH_DISABLE_LOSETUP is not set -# CONFIG_NSH_DISABLE_MKRD is not set -# CONFIG_NSH_DISABLE_PUT is not set -# CONFIG_NSH_DISABLE_SEMICOLON is not set -# CONFIG_NSH_DISABLE_TIME is not set -# CONFIG_NSH_DISABLE_UNAME is not set -# CONFIG_NSH_DISABLE_WGET is not set -# CONFIG_NSH_DISABLE_XD is not set -# CONFIG_NX_DISABLE_1BPP is not set -# CONFIG_NX_WRITEONLY is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f4discovery" -CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F407VG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_DEFAULT_SMALL=y -CONFIG_EXAMPLES_NXHELLO=y -CONFIG_EXAMPLES_NXHELLO_BPP=1 -CONFIG_EXAMPLES_NXHELLO_LISTENER_STACKSIZE=1536 -CONFIG_EXAMPLES_NXHELLO_STACKSIZE=1536 -CONFIG_FS_PROCFS=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_LCD=y -CONFIG_LCD_FRAMEBUFFER=y -CONFIG_LCD_MAX7219=y -CONFIG_LCD_NOGETRUN=y -CONFIG_MAX7219_NHORIZONTALBLKS=4 -CONFIG_MM_REGIONS=2 -CONFIG_MQ_MAXMSGSIZE=64 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NX=y -CONFIG_NXFONT_MONO5X8=y -CONFIG_NXSTART_SERVERSTACK=1536 -CONFIG_NX_BLOCKING=y -CONFIG_NX_MXCLIENTMSGS=32 -CONFIG_PREALLOC_MQ_MSGS=16 -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_HPWORKPRIORITY=192 -CONFIG_SCHED_WAITPID=y -CONFIG_SERIAL_TERMIOS=y -CONFIG_START_DAY=21 -CONFIG_START_MONTH=4 -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_PWR=y -CONFIG_STM32_SPI1=y -CONFIG_STM32_USART2=y -CONFIG_SYSTEM_NSH=y -CONFIG_USART2_RXBUFSIZE=128 -CONFIG_USART2_SERIAL_CONSOLE=y -CONFIG_USART2_TXBUFSIZE=128 diff --git a/boards/arm/stm32/stm32f4discovery/configs/mmcsdspi/defconfig b/boards/arm/stm32/stm32f4discovery/configs/mmcsdspi/defconfig deleted file mode 100644 index 7c3b724bbedf9..0000000000000 --- a/boards/arm/stm32/stm32f4discovery/configs/mmcsdspi/defconfig +++ /dev/null @@ -1,70 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_MMCSD_HAVE_CARDDETECT is not set -# CONFIG_MMCSD_HAVE_WRITEPROTECT is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -# CONFIG_SPI_CALLBACK is not set -# CONFIG_STM32_CCMEXCLUDE is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f4discovery" -CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F407VG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARDCTL_RESET=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_CODECS_HASH_MD5=y -CONFIG_DEBUG_FULLOPT=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_EXAMPLES_HELLO=y -CONFIG_FAT_LFN=y -CONFIG_FS_FAT=y -CONFIG_FS_FATTIME=y -CONFIG_FS_PROCFS=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_HEAP_COLORATION=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_MMCSD=y -CONFIG_MM_REGIONS=2 -CONFIG_NETUTILS_CODECS=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_READLINE_CMD_HISTORY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_LPWORK=y -CONFIG_SCHED_LPWORKPRIORITY=30 -CONFIG_SCHED_WAITPID=y -CONFIG_SENDFILE_BUFSIZE=1024 -CONFIG_STACK_COLORATION=y -CONFIG_START_DAY=17 -CONFIG_START_MONTH=10 -CONFIG_START_YEAR=2019 -CONFIG_STM32_DMA1=y -CONFIG_STM32_DMA2=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_PWR=y -CONFIG_STM32_SPI2=y -CONFIG_STM32_USART2=y -CONFIG_SYSTEM_NSH=y -CONFIG_TESTING_OSTEST=y -CONFIG_USART2_RXBUFSIZE=128 -CONFIG_USART2_SERIAL_CONSOLE=y -CONFIG_USART2_TXBUFSIZE=128 diff --git a/boards/arm/stm32/stm32f4discovery/configs/modbus_slave/defconfig b/boards/arm/stm32/stm32f4discovery/configs/modbus_slave/defconfig deleted file mode 100644 index 7e4857ec739a2..0000000000000 --- a/boards/arm/stm32/stm32f4discovery/configs/modbus_slave/defconfig +++ /dev/null @@ -1,61 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_MB_TCP_ENABLED is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -# CONFIG_NSH_DISABLE_MB is not set -# CONFIG_NSH_DISABLE_MH is not set -# CONFIG_NSH_DISABLE_MW is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f4discovery" -CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F407VG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_EXAMPLES_HELLO=y -CONFIG_EXAMPLES_MODBUS=y -CONFIG_EXAMPLES_MODBUS_PORT=1 -CONFIG_FS_PROCFS=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_INDUSTRY_MODBUS=y -CONFIG_INDUSTRY_MODBUS_SLAVE=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_MM_REGIONS=2 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_SERIAL_TERMIOS=y -CONFIG_START_DAY=6 -CONFIG_START_MONTH=12 -CONFIG_START_YEAR=2011 -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_PWR=y -CONFIG_STM32_SPI1=y -CONFIG_STM32_USART1=y -CONFIG_STM32_USART2=y -CONFIG_SYSTEM_NSH=y -CONFIG_USART1_BAUD=38400 -CONFIG_USART1_PARITY=2 -CONFIG_USART1_RS485=y -CONFIG_USART2_RXBUFSIZE=128 -CONFIG_USART2_SERIAL_CONSOLE=y -CONFIG_USART2_TXBUFSIZE=128 diff --git a/boards/arm/stm32/stm32f4discovery/configs/module/defconfig b/boards/arm/stm32/stm32f4discovery/configs/module/defconfig deleted file mode 100644 index 3b84fd63e69e6..0000000000000 --- a/boards/arm/stm32/stm32f4discovery/configs/module/defconfig +++ /dev/null @@ -1,51 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f4discovery" -CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F407VG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARDCTL_ROMDISK=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_EXAMPLES_MODULE=y -CONFIG_FS_PROCFS=y -CONFIG_FS_ROMFS=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_MM_REGIONS=2 -CONFIG_MODULE=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=6 -CONFIG_START_MONTH=12 -CONFIG_START_YEAR=2011 -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_PWR=y -CONFIG_STM32_SPI1=y -CONFIG_STM32_USART2=y -CONFIG_SYSTEM_NSH=y -CONFIG_USART2_RXBUFSIZE=128 -CONFIG_USART2_SERIAL_CONSOLE=y -CONFIG_USART2_TXBUFSIZE=128 diff --git a/boards/arm/stm32/stm32f4discovery/configs/mpr121_keypad/defconfig b/boards/arm/stm32/stm32f4discovery/configs/mpr121_keypad/defconfig deleted file mode 100644 index c6b607db2870e..0000000000000 --- a/boards/arm/stm32/stm32f4discovery/configs/mpr121_keypad/defconfig +++ /dev/null @@ -1,57 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f4discovery" -CONFIG_ARCH_BOARD_COMMON=y -CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F407VG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_DEBUG_FEATURES=y -CONFIG_EXAMPLES_HELLO=y -CONFIG_EXAMPLES_KEYBOARD=y -CONFIG_EXAMPLES_KEYBOARD_DEVPATH="/dev/keypad0" -CONFIG_FS_PROCFS=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_I2C=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INPUT=y -CONFIG_INPUT_MPR121_KEYPAD=y -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_MM_REGIONS=2 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_LPWORK=y -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=6 -CONFIG_START_MONTH=12 -CONFIG_START_YEAR=2011 -CONFIG_STM32_I2C1=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_PWR=y -CONFIG_STM32_SPI1=y -CONFIG_STM32_USART2=y -CONFIG_SYSTEM_NSH=y -CONFIG_USART2_RXBUFSIZE=128 -CONFIG_USART2_SERIAL_CONSOLE=y -CONFIG_USART2_TXBUFSIZE=128 diff --git a/boards/arm/stm32/stm32f4discovery/configs/mt6816/defconfig b/boards/arm/stm32/stm32f4discovery/configs/mt6816/defconfig deleted file mode 100644 index 609bf1e8f072e..0000000000000 --- a/boards/arm/stm32/stm32f4discovery/configs/mt6816/defconfig +++ /dev/null @@ -1,55 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_DEBUG_ERROR is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f4discovery" -CONFIG_ARCH_BOARD_COMMON=y -CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F407VG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_DEBUG_FEATURES=y -CONFIG_DEBUG_SENSORS=y -CONFIG_EXAMPLES_HELLO=y -CONFIG_EXAMPLES_QENCODER=y -CONFIG_FS_PROCFS=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_MM_REGIONS=2 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_SENSORS=y -CONFIG_SENSORS_MT6816=y -CONFIG_START_DAY=6 -CONFIG_START_MONTH=12 -CONFIG_START_YEAR=2011 -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_PWR=y -CONFIG_STM32_SPI1=y -CONFIG_STM32_USART2=y -CONFIG_SYSTEM_NSH=y -CONFIG_USART2_RXBUFSIZE=128 -CONFIG_USART2_SERIAL_CONSOLE=y -CONFIG_USART2_TXBUFSIZE=128 diff --git a/boards/arm/stm32/stm32f4discovery/configs/netnsh/defconfig b/boards/arm/stm32/stm32f4discovery/configs/netnsh/defconfig deleted file mode 100644 index acf1c69a8867f..0000000000000 --- a/boards/arm/stm32/stm32f4discovery/configs/netnsh/defconfig +++ /dev/null @@ -1,91 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_MMCSD_MMCSUPPORT is not set -# CONFIG_MMCSD_SPI is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f4discovery" -CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F407VG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARDCTL_RESET=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_ETH0_PHY_LAN8720=y -CONFIG_FAT_LCNAMES=y -CONFIG_FAT_LFN=y -CONFIG_FS_FAT=y -CONFIG_FS_PROCFS=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_HOST_WINDOWS=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LIBC_HOSTNAME="STM32F4-Discovery" -CONFIG_LINE_MAX=64 -CONFIG_MMCSD=y -CONFIG_MMCSD_MULTIBLOCK_LIMIT=1 -CONFIG_MMCSD_SDIO=y -CONFIG_NET=y -CONFIG_NETDB_DNSCLIENT=y -CONFIG_NETDB_DNSSERVER_NOADDR=y -CONFIG_NETDEV_PHY_IOCTL=y -CONFIG_NETINIT_NOMAC=y -CONFIG_NETINIT_THREAD=y -CONFIG_NETUTILS_TELNETD=y -CONFIG_NETUTILS_TFTPC=y -CONFIG_NETUTILS_WEBCLIENT=y -CONFIG_NET_BROADCAST=y -CONFIG_NET_ICMP_SOCKET=y -CONFIG_NET_SOLINGER=y -CONFIG_NET_TCP=y -CONFIG_NET_TCP_WRITE_BUFFERS=y -CONFIG_NET_UDP=y -CONFIG_NET_UDP_CHECKSUMS=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_HPWORKPRIORITY=192 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=13 -CONFIG_START_MONTH=9 -CONFIG_START_YEAR=2014 -CONFIG_STM32F4DISBB=y -CONFIG_STM32_DMA2=y -CONFIG_STM32_DMACAPABLE=y -CONFIG_STM32_ETHMAC=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_PHYADDR=0 -CONFIG_STM32_PHYSR=31 -CONFIG_STM32_PHYSR_100FD=0x0018 -CONFIG_STM32_PHYSR_100HD=0x0008 -CONFIG_STM32_PHYSR_10FD=0x0014 -CONFIG_STM32_PHYSR_10HD=0x0004 -CONFIG_STM32_PHYSR_ALTCONFIG=y -CONFIG_STM32_PHYSR_ALTMODE=0x001c -CONFIG_STM32_PWR=y -CONFIG_STM32_RMII_EXTCLK=y -CONFIG_STM32_SDIO=y -CONFIG_STM32_SPI1=y -CONFIG_STM32_USART6=y -CONFIG_SYSTEM_NSH=y -CONFIG_SYSTEM_PING=y -CONFIG_USART6_RXBUFSIZE=64 -CONFIG_USART6_SERIAL_CONSOLE=y -CONFIG_USART6_TXBUFSIZE=64 diff --git a/boards/arm/stm32/stm32f4discovery/configs/nsh/defconfig b/boards/arm/stm32/stm32f4discovery/configs/nsh/defconfig deleted file mode 100644 index 27dc6222bebb4..0000000000000 --- a/boards/arm/stm32/stm32f4discovery/configs/nsh/defconfig +++ /dev/null @@ -1,49 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f4discovery" -CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F407VG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_EXAMPLES_HELLO=y -CONFIG_FS_PROCFS=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_HOST_WINDOWS=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_MM_REGIONS=2 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=6 -CONFIG_START_MONTH=12 -CONFIG_START_YEAR=2011 -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_PWR=y -CONFIG_STM32_SPI1=y -CONFIG_STM32_USART2=y -CONFIG_SYSTEM_NSH=y -CONFIG_USART2_RXBUFSIZE=128 -CONFIG_USART2_SERIAL_CONSOLE=y -CONFIG_USART2_TXBUFSIZE=128 diff --git a/boards/arm/stm32/stm32f4discovery/configs/nxlines/defconfig b/boards/arm/stm32/stm32f4discovery/configs/nxlines/defconfig deleted file mode 100644 index 8ecab5062eb96..0000000000000 --- a/boards/arm/stm32/stm32f4discovery/configs/nxlines/defconfig +++ /dev/null @@ -1,72 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_EXAMPLES_NXLINES_DEFAULT_COLORS is not set -# CONFIG_NXFONTS_DISABLE_16BPP is not set -# CONFIG_NXTK_DEFAULT_BORDERCOLORS is not set -# CONFIG_NX_DISABLE_16BPP is not set -# CONFIG_NX_PACKEDMSFIRST is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f4discovery" -CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F407VG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_EXAMPLES_NXLINES=y -CONFIG_EXAMPLES_NXLINES_BGCOLOR=0x0320 -CONFIG_EXAMPLES_NXLINES_BORDERCOLOR=0xffe0 -CONFIG_EXAMPLES_NXLINES_BORDERWIDTH=4 -CONFIG_EXAMPLES_NXLINES_BPP=16 -CONFIG_EXAMPLES_NXLINES_CIRCLECOLOR=0xf7bb -CONFIG_EXAMPLES_NXLINES_LINECOLOR=0xffe0 -CONFIG_FS_PROCFS=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_HOST_WINDOWS=y -CONFIG_INIT_ENTRYPOINT="nxlines_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LCD=y -CONFIG_LCD_MAXCONTRAST=1 -CONFIG_LCD_MAXPOWER=255 -CONFIG_LCD_SSD1289=y -CONFIG_LINE_MAX=64 -CONFIG_MM_REGIONS=2 -CONFIG_MQ_MAXMSGSIZE=64 -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_LIBRARY=y -CONFIG_NSH_READLINE=y -CONFIG_NX=y -CONFIG_NXFONT_SANS22X29B=y -CONFIG_NXFONT_SANS23X27=y -CONFIG_NXTK_BORDERCOLOR1=0x5cb7 -CONFIG_NXTK_BORDERCOLOR2=0x21c9 -CONFIG_NXTK_BORDERCOLOR3=0xffdf -CONFIG_NX_BLOCKING=y -CONFIG_NX_KBD=y -CONFIG_NX_XYINPUT_MOUSE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=6 -CONFIG_START_MONTH=12 -CONFIG_START_YEAR=2011 -CONFIG_STM32_FSMC=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_PWR=y -CONFIG_STM32_SPI1=y -CONFIG_STM32_USART2=y -CONFIG_SYMTAB_ORDEREDBYNAME=y -CONFIG_USART2_RXBUFSIZE=128 -CONFIG_USART2_SERIAL_CONSOLE=y -CONFIG_USART2_TXBUFSIZE=128 diff --git a/boards/arm/stm32/stm32f4discovery/configs/nxscope_cdcacm/defconfig b/boards/arm/stm32/stm32f4discovery/configs/nxscope_cdcacm/defconfig deleted file mode 100644 index efc7a7cfe4525..0000000000000 --- a/boards/arm/stm32/stm32f4discovery/configs/nxscope_cdcacm/defconfig +++ /dev/null @@ -1,61 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_DEV_CONSOLE is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f4discovery" -CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F407VG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARDCTL=y -CONFIG_BOARDCTL_MKRD=y -CONFIG_BOARDCTL_USBDEVCTRL=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_CDCACM=y -CONFIG_CDCACM_RXBUFSIZE=256 -CONFIG_CDCACM_TXBUFSIZE=2048 -CONFIG_DEBUG_FULLOPT=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_EXAMPLES_NXSCOPE=y -CONFIG_EXAMPLES_NXSCOPE_CDCACM=y -CONFIG_EXAMPLES_NXSCOPE_SERIAL_PATH="/dev/ttyACM0" -CONFIG_FS_PROCFS=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_IDLETHREAD_STACKSIZE=2048 -CONFIG_INIT_ENTRYPOINT="nxscope_main" -CONFIG_INIT_STACKSIZE=4096 -CONFIG_INTELHEX_BINARY=y -CONFIG_LOGGING_NXSCOPE=y -CONFIG_LOGGING_NXSCOPE_ACKFRAMES=y -CONFIG_LOGGING_NXSCOPE_DIVIDER=y -CONFIG_LOGGING_NXSCOPE_INTF_SERIAL=y -CONFIG_MM_REGIONS=2 -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAMLOG=y -CONFIG_RAMLOG_BUFSIZE=4096 -CONFIG_RAMLOG_SYSLOG=y -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_STACK_COLORATION=y -CONFIG_START_DAY=27 -CONFIG_START_YEAR=2013 -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_OTGFS=y -CONFIG_STM32_PWR=y -CONFIG_STM32_SPI1=y -CONFIG_STM32_USART2=y -CONFIG_SYSTEM_READLINE=y -CONFIG_USBDEV=y diff --git a/boards/arm/stm32/stm32f4discovery/configs/pm/defconfig b/boards/arm/stm32/stm32f4discovery/configs/pm/defconfig deleted file mode 100644 index 4f196c9c570b3..0000000000000 --- a/boards/arm/stm32/stm32f4discovery/configs/pm/defconfig +++ /dev/null @@ -1,55 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_ARCH_LEDS is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f4discovery" -CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F407VG=y -CONFIG_ARCH_CUSTOM_PMINIT=y -CONFIG_ARCH_IDLE_CUSTOM=y -CONFIG_ARCH_IRQBUTTONS=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_FS_PROCFS=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_HOST_WINDOWS=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_MM_REGIONS=2 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PM=y -CONFIG_PM_BUTTONS=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_RTC_ALARM=y -CONFIG_RTC_DATETIME=y -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_HPWORKPRIORITY=192 -CONFIG_SCHED_HPWORKSTACKSIZE=1024 -CONFIG_SCHED_WAITPID=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_PWR=y -CONFIG_STM32_RTC=y -CONFIG_STM32_TIM1=y -CONFIG_STM32_USART2=y -CONFIG_SYSTEM_NSH=y -CONFIG_USART2_RXBUFSIZE=128 -CONFIG_USART2_SERIAL_CONSOLE=y -CONFIG_USART2_TXBUFSIZE=128 diff --git a/boards/arm/stm32/stm32f4discovery/configs/posix_spawn/defconfig b/boards/arm/stm32/stm32f4discovery/configs/posix_spawn/defconfig deleted file mode 100644 index 9f49ec41573bd..0000000000000 --- a/boards/arm/stm32/stm32f4discovery/configs/posix_spawn/defconfig +++ /dev/null @@ -1,48 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f4discovery" -CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F407VG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BINFMT_CONSTRUCTORS=y -CONFIG_BOARDCTL=y -CONFIG_BOARDCTL_APP_SYMTAB=y -CONFIG_BOARDCTL_ROMDISK=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_CONSOLE_SYSLOG=y -CONFIG_ELF=y -CONFIG_EXAMPLES_POSIXSPAWN=y -CONFIG_EXECFUNCS_HAVE_SYMTAB=y -CONFIG_EXECFUNCS_NSYMBOLS_VAR="g_spawn_nexports" -CONFIG_EXECFUNCS_SYMTAB_ARRAY="g_spawn_exports" -CONFIG_FS_ROMFS=y -CONFIG_HAVE_CXX=y -CONFIG_INIT_ENTRYPOINT="posix_spawn_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LIBC_ENVPATH=y -CONFIG_LIBC_EXECFUNCS=y -CONFIG_MM_REGIONS=2 -CONFIG_PATH_INITIAL="/mnt/romfs" -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_START_DAY=26 -CONFIG_START_MONTH=10 -CONFIG_START_YEAR=2012 -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_USART2=y -CONFIG_SYMTAB_ORDEREDBYNAME=y -CONFIG_USART2_RXBUFSIZE=128 -CONFIG_USART2_SERIAL_CONSOLE=y -CONFIG_USART2_TXBUFSIZE=128 diff --git a/boards/arm/stm32/stm32f4discovery/configs/pseudoterm/defconfig b/boards/arm/stm32/stm32f4discovery/configs/pseudoterm/defconfig deleted file mode 100644 index 2deb457fa7783..0000000000000 --- a/boards/arm/stm32/stm32f4discovery/configs/pseudoterm/defconfig +++ /dev/null @@ -1,53 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f4discovery" -CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F407VG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_EXAMPLES_PTYTEST=y -CONFIG_EXAMPLES_PTYTEST_POLL=y -CONFIG_FS_PROCFS=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_MM_IOB=y -CONFIG_MM_REGIONS=2 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_PSEUDOTERM=y -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_SERIAL_TERMIOS=y -CONFIG_START_DAY=6 -CONFIG_START_MONTH=12 -CONFIG_START_YEAR=2011 -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_PWR=y -CONFIG_STM32_SPI1=y -CONFIG_STM32_USART2=y -CONFIG_STM32_USART3=y -CONFIG_SYSTEM_NSH=y -CONFIG_USART2_RXBUFSIZE=128 -CONFIG_USART2_SERIAL_CONSOLE=y -CONFIG_USART2_TXBUFSIZE=128 diff --git a/boards/arm/stm32/stm32f4discovery/configs/rgbled/defconfig b/boards/arm/stm32/stm32f4discovery/configs/rgbled/defconfig deleted file mode 100644 index 48ded7700ac78..0000000000000 --- a/boards/arm/stm32/stm32f4discovery/configs/rgbled/defconfig +++ /dev/null @@ -1,62 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f4discovery" -CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F407VG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_EXAMPLES_RGBLED=y -CONFIG_FS_PROCFS=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_INIT_ENTRYPOINT="rgbled_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_MM_REGIONS=2 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_PWM=y -CONFIG_PWM_NCHANNELS=3 -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RGBLED=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=6 -CONFIG_START_MONTH=12 -CONFIG_START_YEAR=2011 -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_OTGFS=y -CONFIG_STM32_PWR=y -CONFIG_STM32_SPI1=y -CONFIG_STM32_TIM1=y -CONFIG_STM32_TIM1_PWM=y -CONFIG_STM32_TIM2=y -CONFIG_STM32_TIM2_CH2OUT=y -CONFIG_STM32_TIM2_CHANNEL=2 -CONFIG_STM32_TIM2_PWM=y -CONFIG_STM32_TIM3=y -CONFIG_STM32_TIM3_CH3OUT=y -CONFIG_STM32_TIM3_CHANNEL=3 -CONFIG_STM32_TIM3_PWM=y -CONFIG_STM32_USART2=y -CONFIG_SYSTEM_NSH=y -CONFIG_USART2_RXBUFSIZE=128 -CONFIG_USART2_SERIAL_CONSOLE=y -CONFIG_USART2_TXBUFSIZE=128 diff --git a/boards/arm/stm32/stm32f4discovery/configs/rndis/defconfig b/boards/arm/stm32/stm32f4discovery/configs/rndis/defconfig deleted file mode 100644 index fde9264166505..0000000000000 --- a/boards/arm/stm32/stm32f4discovery/configs/rndis/defconfig +++ /dev/null @@ -1,92 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -CONFIG_ALLOW_BSD_COMPONENTS=y -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f4discovery" -CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F407VG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARDCTL_RESET=y -CONFIG_BOARDCTL_USBDEVCTRL=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_DEBUG_FULLOPT=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_ELF=y -CONFIG_EXAMPLES_HELLO=m -CONFIG_FAT_LCNAMES=y -CONFIG_FAT_LFN=y -CONFIG_FS_FAT=y -CONFIG_FS_PROCFS=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INIT_STACKSIZE=3072 -CONFIG_INTELHEX_BINARY=y -CONFIG_LIBC_ENVPATH=y -CONFIG_LIBC_EXECFUNCS=y -CONFIG_LINE_MAX=128 -CONFIG_NET=y -CONFIG_NETDB_DNSCLIENT=y -CONFIG_NETDB_DNSSERVER_IPv4ADDR=0x0 -CONFIG_NETINIT_DHCPC=y -CONFIG_NETINIT_DRIPADDR=0x0 -CONFIG_NETINIT_MACADDR_1=0xdeadcafe -CONFIG_NETINIT_NETMASK=0x0 -CONFIG_NETINIT_NOMAC=y -CONFIG_NETINIT_THREAD=y -CONFIG_NETUTILS_DHCPC=y -CONFIG_NETUTILS_IPERF=y -CONFIG_NETUTILS_TELNETD=y -CONFIG_NETUTILS_WEBCLIENT=y -CONFIG_NET_BROADCAST=y -CONFIG_NET_ICMP_SOCKET=y -CONFIG_NET_LOOPBACK=y -CONFIG_NET_STATISTICS=y -CONFIG_NET_TCP=y -CONFIG_NET_TCP_WRITE_BUFFERS=y -CONFIG_NET_UDP=y -CONFIG_NFS=y -CONFIG_NFS_STATISTICS=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_FILE_APPS=y -CONFIG_NSH_READLINE=y -CONFIG_NSH_SYMTAB=y -CONFIG_NSH_SYMTAB_ARRAYNAME="g_symtab" -CONFIG_NSH_SYMTAB_COUNTNAME="g_nsymbols" -CONFIG_PATH_INITIAL="/mnt/nfs/bin" -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RNDIS=y -CONFIG_SCHED_LPWORK=y -CONFIG_SCHED_WAITPID=y -CONFIG_SENSORS=y -CONFIG_START_DAY=13 -CONFIG_START_MONTH=9 -CONFIG_START_YEAR=2014 -CONFIG_STM32_DMA2=y -CONFIG_STM32_DMACAPABLE=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_OTGFS=y -CONFIG_STM32_PWR=y -CONFIG_STM32_SPI1=y -CONFIG_STM32_USART2=y -CONFIG_SYMTAB_ORDEREDBYNAME=y -CONFIG_SYSTEM_NSH=y -CONFIG_SYSTEM_PING=y -CONFIG_USART2_SERIAL_CONSOLE=y -CONFIG_USBDEV=y diff --git a/boards/arm/stm32/stm32f4discovery/configs/sbutton/defconfig b/boards/arm/stm32/stm32f4discovery/configs/sbutton/defconfig deleted file mode 100644 index 2dbb1e6193a64..0000000000000 --- a/boards/arm/stm32/stm32f4discovery/configs/sbutton/defconfig +++ /dev/null @@ -1,55 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_ASSERTIONS_FILENAME is not set -# CONFIG_NDEBUG is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f4discovery" -CONFIG_ARCH_BOARD_COMMON=y -CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F407VG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_EXAMPLES_HELLO=y -CONFIG_EXAMPLES_KEYBOARD=y -CONFIG_FS_PROCFS=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INPUT=y -CONFIG_INPUT_SBUTTON=y -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_MM_REGIONS=2 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=6 -CONFIG_START_MONTH=12 -CONFIG_START_YEAR=2011 -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_PWR=y -CONFIG_STM32_SPI1=y -CONFIG_STM32_USART2=y -CONFIG_SYSTEM_NSH=y -CONFIG_USART2_RXBUFSIZE=128 -CONFIG_USART2_SERIAL_CONSOLE=y -CONFIG_USART2_TXBUFSIZE=128 -CONFIG_WQUEUE_NOTIFIER=y diff --git a/boards/arm/stm32/stm32f4discovery/configs/sporadic/defconfig b/boards/arm/stm32/stm32f4discovery/configs/sporadic/defconfig deleted file mode 100644 index 3af85b79a137f..0000000000000 --- a/boards/arm/stm32/stm32f4discovery/configs/sporadic/defconfig +++ /dev/null @@ -1,49 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f4discovery" -CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F407VG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_FS_PROCFS=y -CONFIG_HOST_WINDOWS=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_MM_REGIONS=2 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_SCHED_SPORADIC=y -CONFIG_SCHED_SPORADIC_MAXREPL=5 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=6 -CONFIG_START_MONTH=3 -CONFIG_START_YEAR=2021 -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_PWR=y -CONFIG_STM32_SPI1=y -CONFIG_STM32_USART6=y -CONFIG_SYSTEM_NSH=y -CONFIG_TESTING_OSTEST=y -CONFIG_USART6_RXBUFSIZE=128 -CONFIG_USART6_SERIAL_CONSOLE=y -CONFIG_USART6_TXBUFSIZE=128 -CONFIG_USEC_PER_TICK=1000 diff --git a/boards/arm/stm32/stm32f4discovery/configs/st7567/defconfig b/boards/arm/stm32/stm32f4discovery/configs/st7567/defconfig deleted file mode 100644 index e3166d9e8a17d..0000000000000 --- a/boards/arm/stm32/stm32f4discovery/configs/st7567/defconfig +++ /dev/null @@ -1,62 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f4discovery" -CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F407VG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_DRIVERS_VIDEO=y -CONFIG_EXAMPLES_FB=y -CONFIG_EXAMPLES_HELLO=y -CONFIG_FS_PROCFS=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LCD=y -CONFIG_LCD_FRAMEBUFFER=y -CONFIG_LCD_NOGETRUN=y -CONFIG_LCD_ST7567=y -CONFIG_LINE_MAX=64 -CONFIG_MM_REGIONS=2 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_NXFONTS_DISABLE_1BPP=y -CONFIG_NXFONTS_DISABLE_24BPP=y -CONFIG_NXFONTS_DISABLE_2BPP=y -CONFIG_NXFONTS_DISABLE_32BPP=y -CONFIG_NXFONTS_DISABLE_4BPP=y -CONFIG_NXFONTS_DISABLE_8BPP=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_SPI_CMDDATA=y -CONFIG_START_DAY=6 -CONFIG_START_MONTH=12 -CONFIG_START_YEAR=2011 -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_PWR=y -CONFIG_STM32_SPI1=y -CONFIG_STM32_USART2=y -CONFIG_SYSTEM_NSH=y -CONFIG_USART2_RXBUFSIZE=128 -CONFIG_USART2_SERIAL_CONSOLE=y -CONFIG_USART2_TXBUFSIZE=128 -CONFIG_VIDEO_FB=y diff --git a/boards/arm/stm32/stm32f4discovery/configs/st7789/defconfig b/boards/arm/stm32/stm32f4discovery/configs/st7789/defconfig deleted file mode 100644 index 9d846ecf6a4bc..0000000000000 --- a/boards/arm/stm32/stm32f4discovery/configs/st7789/defconfig +++ /dev/null @@ -1,63 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f4discovery" -CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F407VG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_DRIVERS_VIDEO=y -CONFIG_EXAMPLES_FB=y -CONFIG_EXAMPLES_HELLO=y -CONFIG_FS_PROCFS=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LCD=y -CONFIG_LCD_FRAMEBUFFER=y -CONFIG_LCD_NOGETRUN=y -CONFIG_LCD_PORTRAIT=y -CONFIG_LCD_ST7789=y -CONFIG_LINE_MAX=64 -CONFIG_MM_REGIONS=2 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_NXFONTS_DISABLE_1BPP=y -CONFIG_NXFONTS_DISABLE_24BPP=y -CONFIG_NXFONTS_DISABLE_2BPP=y -CONFIG_NXFONTS_DISABLE_32BPP=y -CONFIG_NXFONTS_DISABLE_4BPP=y -CONFIG_NXFONTS_DISABLE_8BPP=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_SPI_CMDDATA=y -CONFIG_START_DAY=6 -CONFIG_START_MONTH=12 -CONFIG_START_YEAR=2011 -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_PWR=y -CONFIG_STM32_SPI1=y -CONFIG_STM32_USART2=y -CONFIG_SYSTEM_NSH=y -CONFIG_USART2_RXBUFSIZE=128 -CONFIG_USART2_SERIAL_CONSOLE=y -CONFIG_USART2_TXBUFSIZE=128 -CONFIG_VIDEO_FB=y diff --git a/boards/arm/stm32/stm32f4discovery/configs/testlibcxx/defconfig b/boards/arm/stm32/stm32f4discovery/configs/testlibcxx/defconfig deleted file mode 100644 index fd17d3158312a..0000000000000 --- a/boards/arm/stm32/stm32f4discovery/configs/testlibcxx/defconfig +++ /dev/null @@ -1,51 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f4discovery" -CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F407VG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_CXX_LOCALIZATION=y -CONFIG_CXX_WCHAR=y -CONFIG_DISABLE_MOUNTPOINT=y -CONFIG_EXAMPLES_HELLOXX=y -CONFIG_HAVE_CXX=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LIBCXX=y -CONFIG_LIBC_FLOATINGPOINT=y -CONFIG_LIBC_LOCALE=y -CONFIG_LIBC_LOCALTIME=y -CONFIG_LIBC_MAX_EXITFUNS=4 -CONFIG_LIBM=y -CONFIG_MM_REGIONS=2 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=2 -CONFIG_START_MONTH=11 -CONFIG_START_YEAR=2012 -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_USART2=y -CONFIG_SYMTAB_ORDEREDBYNAME=y -CONFIG_SYSTEM_NSH=y -CONFIG_TLS_NELEM=16 -CONFIG_TLS_TASK_NELEM=8 -CONFIG_USART2_RXBUFSIZE=128 -CONFIG_USART2_SERIAL_CONSOLE=y -CONFIG_USART2_TXBUFSIZE=128 diff --git a/boards/arm/stm32/stm32f4discovery/configs/usbmsc/defconfig b/boards/arm/stm32/stm32f4discovery/configs/usbmsc/defconfig deleted file mode 100644 index 0bc84e9ee02c1..0000000000000 --- a/boards/arm/stm32/stm32f4discovery/configs/usbmsc/defconfig +++ /dev/null @@ -1,59 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f4discovery" -CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F407VG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_FAT_LCNAMES=y -CONFIG_FAT_LFN=y -CONFIG_FS_FAT=y -CONFIG_FS_PROCFS=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_MM_REGIONS=2 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_DISABLE_IFUPDOWN=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_HPWORKPRIORITY=192 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=27 -CONFIG_START_YEAR=2013 -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_OTGFS=y -CONFIG_STM32_PWR=y -CONFIG_STM32_SPI1=y -CONFIG_STM32_USART2=y -CONFIG_SYSLOG_CHAR=y -CONFIG_SYSLOG_DEVPATH="/dev/ttyS0" -CONFIG_SYSTEM_NSH=y -CONFIG_SYSTEM_USBMSC=y -CONFIG_SYSTEM_USBMSC_DEVMINOR1=0 -CONFIG_SYSTEM_USBMSC_DEVPATH1="/dev/ram0" -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART2_SERIAL_CONSOLE=y -CONFIG_USBDEV=y -CONFIG_USBMSC=y -CONFIG_USBMSC_REMOVABLE=y diff --git a/boards/arm/stm32/stm32f4discovery/configs/usbnsh/defconfig b/boards/arm/stm32/stm32f4discovery/configs/usbnsh/defconfig deleted file mode 100644 index dce3e3d343b5c..0000000000000 --- a/boards/arm/stm32/stm32f4discovery/configs/usbnsh/defconfig +++ /dev/null @@ -1,57 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_DEV_CONSOLE is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f4discovery" -CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F407VG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARDCTL_USBDEVCTRL=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_CDCACM=y -CONFIG_CDCACM_CONSOLE=y -CONFIG_CDCACM_RXBUFSIZE=256 -CONFIG_CDCACM_TXBUFSIZE=256 -CONFIG_DEBUG_FULLOPT=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_EXAMPLES_HELLO=y -CONFIG_FS_PROCFS=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_IDLETHREAD_STACKSIZE=2048 -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_MM_REGIONS=2 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAMLOG=y -CONFIG_RAMLOG_BUFSIZE=4096 -CONFIG_RAMLOG_SYSLOG=y -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_STACK_COLORATION=y -CONFIG_START_DAY=27 -CONFIG_START_YEAR=2013 -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_OTGFS=y -CONFIG_STM32_PWR=y -CONFIG_STM32_SPI1=y -CONFIG_STM32_USART2=y -CONFIG_SYSTEM_NSH=y -CONFIG_USBDEV=y diff --git a/boards/arm/stm32/stm32f4discovery/configs/wifi/defconfig b/boards/arm/stm32/stm32f4discovery/configs/wifi/defconfig deleted file mode 100644 index 9867fcf30a580..0000000000000 --- a/boards/arm/stm32/stm32f4discovery/configs/wifi/defconfig +++ /dev/null @@ -1,102 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_MMCSD_HAVE_CARDDETECT is not set -# CONFIG_MMCSD_HAVE_WRITEPROTECT is not set -# CONFIG_NET_ARP is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -# CONFIG_SPI_CALLBACK is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f4discovery" -CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F407VG=y -CONFIG_ARCH_INTERRUPTSTACK=2048 -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARDCTL_RESET=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_CODECS_HASH_MD5=y -CONFIG_DEBUG_FULLOPT=y -CONFIG_DEBUG_HARDFAULT_ALERT=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_DRIVERS_WIRELESS=y -CONFIG_ELF=y -CONFIG_EXAMPLES_HELLO=m -CONFIG_EXAMPLES_WEBSERVER=y -CONFIG_FAT_LFN=y -CONFIG_FS_FAT=y -CONFIG_FS_FATTIME=y -CONFIG_FS_PROCFS=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_HEAP_COLORATION=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LIBC_ENVPATH=y -CONFIG_LIBC_EXECFUNCS=y -CONFIG_LINE_MAX=64 -CONFIG_MMCSD=y -CONFIG_MM_IOB=y -CONFIG_MM_REGIONS=2 -CONFIG_NET=y -CONFIG_NETDB_DNSCLIENT=y -CONFIG_NETINIT_NETLOCAL=y -CONFIG_NETUTILS_CODECS=y -CONFIG_NETUTILS_FTPC=y -CONFIG_NETUTILS_HTTPD_DIRLIST=y -CONFIG_NETUTILS_HTTPD_SENDFILE=y -CONFIG_NETUTILS_TELNETD=y -CONFIG_NETUTILS_WEBCLIENT=y -CONFIG_NETUTILS_WEBSERVER=y -CONFIG_NET_USRSOCK=y -CONFIG_NET_USRSOCK_PREALLOC_CONNS=16 -CONFIG_NET_USRSOCK_UDP=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_NSH_SYMTAB=y -CONFIG_NSH_SYMTAB_ARRAYNAME="g_symtab" -CONFIG_NSH_SYMTAB_COUNTNAME="g_nsymbols" -CONFIG_PATH_INITIAL="/mnt/sd0/bin" -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_READLINE_CMD_HISTORY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_LPWORKPRIORITY=30 -CONFIG_SCHED_WAITPID=y -CONFIG_SENDFILE_BUFSIZE=1024 -CONFIG_STACK_COLORATION=y -CONFIG_START_DAY=22 -CONFIG_START_MONTH=10 -CONFIG_START_YEAR=2019 -CONFIG_STM32_DMA1=y -CONFIG_STM32_DMA2=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_PWR=y -CONFIG_STM32_SPI2=y -CONFIG_STM32_SPI2_DMA=y -CONFIG_STM32_SPI3=y -CONFIG_STM32_SPI3_DMA=y -CONFIG_STM32_USART2=y -CONFIG_SYMTAB_ORDEREDBYNAME=y -CONFIG_SYSTEM_DHCPC_RENEW=y -CONFIG_SYSTEM_NSH=y -CONFIG_SYSTEM_NTPC=y -CONFIG_TESTING_OSTEST=y -CONFIG_USART2_RXBUFSIZE=128 -CONFIG_USART2_SERIAL_CONSOLE=y -CONFIG_USART2_TXBUFSIZE=128 -CONFIG_WIRELESS_GS2200M=y -CONFIG_WL_GS2200M=y -CONFIG_WL_GS2200M_DISABLE_DHCPC=y -CONFIG_WL_GS2200M_SPI_FREQUENCY=10000000 diff --git a/boards/arm/stm32/stm32f4discovery/configs/xen1210/defconfig b/boards/arm/stm32/stm32f4discovery/configs/xen1210/defconfig deleted file mode 100644 index e0237c63e672e..0000000000000 --- a/boards/arm/stm32/stm32f4discovery/configs/xen1210/defconfig +++ /dev/null @@ -1,55 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f4discovery" -CONFIG_ARCH_BOARD_COMMON=y -CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F407VG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_FS_PROCFS=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_MM_REGIONS=2 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_PWM=y -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_WAITPID=y -CONFIG_SENSORS=y -CONFIG_SENSORS_XEN1210=y -CONFIG_START_DAY=17 -CONFIG_START_MONTH=8 -CONFIG_START_YEAR=2016 -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_PWR=y -CONFIG_STM32_SPI1=y -CONFIG_STM32_TIM1=y -CONFIG_STM32_TIM1_CH1OUT=y -CONFIG_STM32_TIM1_PWM=y -CONFIG_STM32_USART2=y -CONFIG_SYSTEM_NSH=y -CONFIG_USART2_RXBUFSIZE=128 -CONFIG_USART2_SERIAL_CONSOLE=y -CONFIG_USART2_TXBUFSIZE=128 diff --git a/boards/arm/stm32/stm32f4discovery/include/board.h b/boards/arm/stm32/stm32f4discovery/include/board.h deleted file mode 100644 index 0287bd8a0fda8..0000000000000 --- a/boards/arm/stm32/stm32f4discovery/include/board.h +++ /dev/null @@ -1,650 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f4discovery/include/board.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __BOARDS_ARM_STM32_STM32F4DISCOVERY_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32_STM32F4DISCOVERY_INCLUDE_BOARD_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#ifndef __ASSEMBLY__ -# include -# include -#endif - -/* Do not include STM32-specific header files here */ - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Clocking *****************************************************************/ - -/* The STM32F4 Discovery board features a single 8MHz crystal. - * Space is provided for a 32kHz RTC backup crystal, but it is not stuffed. - * - * This is the canonical configuration: - * System Clock source : PLL (HSE) - * SYSCLK(Hz) : 168000000 Determined by PLL - * configuration - * HCLK(Hz) : 168000000 (STM32_RCC_CFGR_HPRE) - * AHB Prescaler : 1 (STM32_RCC_CFGR_HPRE) - * APB1 Prescaler : 4 (STM32_RCC_CFGR_PPRE1) - * APB2 Prescaler : 2 (STM32_RCC_CFGR_PPRE2) - * HSE Frequency(Hz) : 8000000 (STM32_BOARD_XTAL) - * PLLM : 8 (STM32_PLLCFG_PLLM) - * PLLN : 336 (STM32_PLLCFG_PLLN) - * PLLP : 2 (STM32_PLLCFG_PLLP) - * PLLQ : 7 (STM32_PLLCFG_PLLQ) - * Main regulator output voltage : Scale1 mode Needed for high speed - * SYSCLK - * Flash Latency(WS) : 5 - * Prefetch Buffer : OFF - * Instruction cache : ON - * Data cache : ON - * Require 48MHz for USB OTG FS, : Enabled - * SDIO and RNG clock - */ - -/* HSI - 16 MHz RC factory-trimmed - * LSI - 32 KHz RC - * HSE - On-board crystal frequency is 8MHz - * LSE - 32.768 kHz - */ - -#define STM32_BOARD_XTAL 8000000ul - -#define STM32_HSI_FREQUENCY 16000000ul -#define STM32_LSI_FREQUENCY 32000 -#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL -#define STM32_LSE_FREQUENCY 32768 - -/* Main PLL Configuration. - * - * PLL source is HSE - * PLL_VCO = (STM32_HSE_FREQUENCY / PLLM) * PLLN - * = (8,000,000 / 8) * 336 - * = 336,000,000 - * SYSCLK = PLL_VCO / PLLP - * = 336,000,000 / 2 = 168,000,000 - * USB OTG FS, SDIO and RNG Clock - * = PLL_VCO / PLLQ - * = 48,000,000 - */ - -#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(8) -#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(336) -#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_2 -#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(7) - -#define STM32_SYSCLK_FREQUENCY 168000000ul - -/* AHB clock (HCLK) is SYSCLK (168MHz) */ - -#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ -#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY - -/* APB1 clock (PCLK1) is HCLK/4 (42MHz) */ - -#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd4 /* PCLK1 = HCLK / 4 */ -#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/4) - -/* Timers driven from APB1 will be twice PCLK1 */ - -#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) - -/* APB2 clock (PCLK2) is HCLK/2 (84MHz) */ - -#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLKd2 /* PCLK2 = HCLK / 2 */ -#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/2) - -/* Timers driven from APB2 will be twice PCLK2 */ - -#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM9_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM10_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM11_CLKIN (2*STM32_PCLK2_FREQUENCY) - -/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx - * otherwise frequency is 2xAPBx. - * Note: TIM1,8 are on APB2, others on APB1 - */ - -#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM2_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM3_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM4_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM5_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM6_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM7_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY - -/* SDIO dividers. Note that slower clocking is required when DMA is disabled - * in order to avoid RX overrun/TX underrun errors due to delayed responses - * to service FIFOs in interrupt driven mode. These values have not been - * tuned!!! - * - * SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(118+2)=400 KHz - */ - -#define SDIO_INIT_CLKDIV (118 << SDIO_CLKCR_CLKDIV_SHIFT) - -/* DMA ON: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(1+2)=16 MHz - * DMA OFF: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(2+2)=12 MHz - */ - -#ifdef CONFIG_SDIO_DMA -# define SDIO_MMCXFR_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT) -#else -# define SDIO_MMCXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT) -#endif - -/* DMA ON: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(1+2)=16 MHz - * DMA OFF: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(2+2)=12 MHz - */ - -#ifdef CONFIG_SDIO_DMA -# define SDIO_SDXFR_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT) -#else -# define SDIO_SDXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT) -#endif - -/* LED definitions **********************************************************/ - -/* If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs - * in any way. The following definitions are used to access individual LEDs. - */ - -/* LED index values for use with board_userled() */ - -#define BOARD_LED1 0 -#define BOARD_LED2 1 -#define BOARD_LED3 2 -#define BOARD_LED4 3 -#define BOARD_NLEDS 4 - -#define BOARD_LED_GREEN BOARD_LED1 -#define BOARD_LED_ORANGE BOARD_LED2 -#define BOARD_LED_RED BOARD_LED3 -#define BOARD_LED_BLUE BOARD_LED4 - -/* LED bits for use with board_userled_all() */ - -#define BOARD_LED1_BIT (1 << BOARD_LED1) -#define BOARD_LED2_BIT (1 << BOARD_LED2) -#define BOARD_LED3_BIT (1 << BOARD_LED3) -#define BOARD_LED4_BIT (1 << BOARD_LED4) - -/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the 4 LEDs on - * board the stm32f4discovery. The following definitions describe how NuttX - * controls the LEDs: - */ - -#define LED_STARTED 0 /* LED1 */ -#define LED_HEAPALLOCATE 1 /* LED2 */ -#define LED_IRQSENABLED 2 /* LED1 + LED2 */ -#define LED_STACKCREATED 3 /* LED3 */ -#define LED_INIRQ 4 /* LED1 + LED3 */ -#define LED_SIGNAL 5 /* LED2 + LED3 */ -#define LED_ASSERTION 6 /* LED1 + LED2 + LED3 */ -#define LED_PANIC 7 /* N/C + N/C + N/C + LED4 */ - -/* Button definitions *******************************************************/ - -/* The STM32F4 Discovery supports one button: */ - -#define BUTTON_USER 0 -#define NUM_BUTTONS 1 -#define BUTTON_USER_BIT (1 << BUTTON_USER) - -/* Alternate function pin selections ****************************************/ - -/* CAN */ - -#ifndef CONFIG_STM32_FSMC -# define GPIO_CAN1_RX (GPIO_CAN1_RX_3|GPIO_SPEED_50MHz) -# define GPIO_CAN1_TX (GPIO_CAN1_TX_3|GPIO_SPEED_50MHz) -#endif - -#ifndef CONFIG_STM32_ETHMAC -# define GPIO_CAN2_RX (GPIO_CAN2_RX_1|GPIO_SPEED_50MHz) -# define GPIO_CAN2_TX (GPIO_CAN2_TX_1|GPIO_SPEED_50MHz) -#endif - -/* USART1 */ - -#ifdef CONFIG_USART1_RS485 - /* Lets use for RS485 on pins: PB6 and PB7 */ - -# define GPIO_USART1_TX (GPIO_USART1_TX_2|GPIO_SPEED_100MHz) -# define GPIO_USART1_RX (GPIO_USART1_RX_2|GPIO_SPEED_100MHz) - - /* RS485 DIR pin: PA15 */ - -# define GPIO_USART1_RS485_DIR (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_50MHz |\ - GPIO_OUTPUT_CLEAR | GPIO_PORTA | GPIO_PIN15) - -#endif - -/* USART2: - * - * The STM32F4 Discovery has no on-board serial devices, but the console is - * brought out to PA2 (TX) and PA3 (RX) for connection to an external serial - * device. - * - * These pins selections, however, conflict with pin usage on the - * STM32F4DIS-BB. - */ - -#ifndef CONFIG_STM32F4DISBB -# define GPIO_USART2_RX (GPIO_USART2_RX_1|GPIO_SPEED_100MHz) /* PA3, P1 pin 13 */ -# define GPIO_USART2_TX (GPIO_USART2_TX_1|GPIO_SPEED_100MHz) /* PA2, P1 pin 14 */ -# define GPIO_USART2_CTS GPIO_USART2_CTS_1 /* PA0, P1 pin 11 */ -# define GPIO_USART2_RTS GPIO_USART2_RTS_1 /* PA1, P1 pin 12 (conflict with USER button) */ -#endif - -/* USART3: - * - * Used in pseudoterm configuration and also with the BT860 HCI UART. - * RTS/CTS Flow control support is needed by the HCI UART. - * - * There are conflicts with the STM32F4DIS-BB Ethernet in this configuration - * when Ethernet is enabled: - * - * PB-11 conflicts with Ethernet TXEN - * PB-13 conflicts with Ethernet TXD1 - * - * UART3 TXD and RXD are available on CON4 PD8 and PD8 of the STM32F4DIS-BB, - * respectively, but not CTS or RTS. For now we assume that Ethernet is not - * enabled if USART3 is used in a configuration with the STM32F4DIS-BB. - */ - -#define GPIO_USART3_TX (GPIO_USART3_TX_1|GPIO_SPEED_100MHz) /* PB10, P1 pin 34 (also MP45DT02 CLK_IN) */ -#define GPIO_USART3_RX (GPIO_USART3_RX_1|GPIO_SPEED_100MHz) /* PB11, P1 pin 35 */ -#define GPIO_USART3_CTS GPIO_USART3_CTS_1 /* PB13, P1 pin 37 */ -#define GPIO_USART3_RTS GPIO_USART3_RTS_1 /* PB14, P1 pin 38 */ - -/* USART6: - * - * The STM32F4DIS-BB base board provides RS-232 drivers and a DB9 connector - * for USART6. This is the preferred serial console for use with the - * STM32F4DIS-BB. - * - * NOTE: CTS and RTS are not brought out to the RS-232 connector on the - * baseboard. - */ - -#define GPIO_USART6_RX (GPIO_USART6_RX_1|GPIO_SPEED_100MHz) /* PC7 (also I2S3_MCK and P2 pin 48) */ -#define GPIO_USART6_TX (GPIO_USART6_TX_1|GPIO_SPEED_100MHz) /* PC6 (also P2 pin 47) */ - -/* PWM - * - * The STM32F4 Discovery has no real on-board PWM devices, but the board - * can be configured to output a pulse train using TIM4 CH2 on PD13. - */ - -#define GPIO_TIM4_CH2OUT (GPIO_TIM4_CH2OUT_2|GPIO_SPEED_50MHz) - -/* Capture - * - * The STM32F4 Discovery has no real on-board pwm capture devices, but the - * board can be configured to capture pwm using TIM3 CH2 PB5. - */ - -#define GPIO_TIM3_CH2IN (GPIO_TIM3_CH2IN_2|GPIO_SPEED_50MHz) -#define GPIO_TIM3_CH1IN (GPIO_TIM3_CH2IN_2|GPIO_SPEED_50MHz) - -/* RGB LED - * - * R = TIM1 CH1 on PE9 | G = TIM2 CH2 on PA1 | B = TIM3 CH3 on PB0 - */ - -#define GPIO_TIM1_CH1OUT (GPIO_TIM1_CH1OUT_2|GPIO_SPEED_50MHz) -#define GPIO_TIM2_CH2OUT (GPIO_TIM2_CH2OUT_1|GPIO_SPEED_50MHz) -#define GPIO_TIM3_CH3OUT (GPIO_TIM3_CH3OUT_1|GPIO_SPEED_50MHz) - -/* SPI - There is a MEMS device on SPI1 using these pins: */ - -#define GPIO_SPI1_MISO (GPIO_SPI1_MISO_1|GPIO_SPEED_50MHz) -#define GPIO_SPI1_MOSI (GPIO_SPI1_MOSI_1|GPIO_SPEED_50MHz) -#define GPIO_SPI1_SCK (GPIO_SPI1_SCK_1|GPIO_SPEED_50MHz) - -/* SPI DMA -- As used for I2S DMA transfer with the audio configuration */ - -#define DMACHAN_SPI1_RX DMAMAP_SPI1_RX_1 -#define DMACHAN_SPI1_TX DMAMAP_SPI1_TX_1 - -/* SPI2 - Test MAX31855 on SPI2 PB10 = SCK, PB14 = MISO */ - -#define GPIO_SPI2_MISO (GPIO_SPI2_MISO_1|GPIO_SPEED_50MHz) -#define GPIO_SPI2_MOSI (GPIO_SPI2_MOSI_1|GPIO_SPEED_50MHz) -#define GPIO_SPI2_SCK (GPIO_SPI2_SCK_1|GPIO_SPEED_50MHz) - -/* SPI2 DMA -- As used for MMC/SD SPI */ - -#define DMACHAN_SPI2_RX DMAMAP_SPI2_RX -#define DMACHAN_SPI2_TX DMAMAP_SPI2_TX - -/* SPI3 DMA -- As used for I2S DMA transfer with the audio configuration */ - -#define GPIO_SPI3_MISO (GPIO_SPI3_MISO_1|GPIO_SPEED_50MHz) -#define GPIO_SPI3_MOSI (GPIO_SPI3_MOSI_1|GPIO_SPEED_50MHz) -#define GPIO_SPI3_SCK (GPIO_SPI3_SCK_1|GPIO_SPEED_50MHz) - -#define DMACHAN_SPI3_RX DMAMAP_SPI3_RX_1 -#define DMACHAN_SPI3_TX DMAMAP_SPI3_TX_1 - -/* I2S3 - CS43L22 configuration uses I2S3 */ - -#define GPIO_I2S3_SD GPIO_I2S3_SD_2 -#define GPIO_I2S3_CK GPIO_I2S3_CK_2 -#define GPIO_I2S3_WS GPIO_I2S3_WS_1 - -#define DMACHAN_I2S3_RX DMAMAP_SPI3_RX_2 -#define DMACHAN_I2S3_TX DMAMAP_SPI3_TX_2 - -/* I2C. Only I2C1 is available on the stm32f4discovery. I2C1_SCL and - * I2C1_SDA are available on the following pins: - * - * - PB6 is I2C1_SCL - * - PB9 is I2C1_SDA - */ - -#define GPIO_I2C1_SCL (GPIO_I2C1_SCL_1|GPIO_SPEED_50MHz) -#define GPIO_I2C1_SDA (GPIO_I2C1_SDA_2|GPIO_SPEED_50MHz) - -/* Timer Inputs/Outputs */ - -#define GPIO_TIM2_CH1IN (GPIO_TIM2_CH1IN_2|GPIO_SPEED_50MHz) -#define GPIO_TIM2_CH2IN (GPIO_TIM2_CH2IN_1|GPIO_SPEED_50MHz) - -#define GPIO_TIM8_CH1IN (GPIO_TIM8_CH1IN_1|GPIO_SPEED_50MHz) -#define GPIO_TIM8_CH2IN (GPIO_TIM8_CH2IN_1|GPIO_SPEED_50MHz) - -/* Ethernet *****************************************************************/ - -#if defined(CONFIG_STM32F4DISBB) && defined(CONFIG_STM32_ETHMAC) - /* RMII interface to the LAN8720 PHY */ - -# ifndef CONFIG_STM32_RMII -# error CONFIG_STM32_RMII must be defined -# endif - - /* Clocking is provided by an external 25Mhz XTAL */ - -# ifndef CONFIG_STM32_RMII_EXTCLK -# error CONFIG_STM32_RMII_EXTCLK must be defined -# endif - - /* Pin disambiguation */ - -# define GPIO_ETH_RMII_TX_EN (GPIO_ETH_RMII_TX_EN_1|GPIO_SPEED_100MHz) -# define GPIO_ETH_RMII_TXD0 (GPIO_ETH_RMII_TXD0_1|GPIO_SPEED_100MHz) -# define GPIO_ETH_RMII_TXD1 (GPIO_ETH_RMII_TXD1_1|GPIO_SPEED_100MHz) -# define GPIO_ETH_PPS_OUT (GPIO_ETH_PPS_OUT_1|GPIO_SPEED_100MHz) - -#endif - -#ifdef CONFIG_MMCSD_SPI -#define GPIO_MMCSD_NSS (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_50MHz | \ - GPIO_OUTPUT_SET | GPIO_PORTB | GPIO_PIN12) - -#define GPIO_MMCSD_NCD (GPIO_INPUT | GPIO_FLOAT | GPIO_EXTI | \ - GPIO_PORTC | GPIO_PIN1) -#endif - -/* DMA Channel/Stream Selections ********************************************/ - -/* Stream selections are arbitrary for now but might become important in the - * future if we set aside more DMA channels/streams. - * - * SDIO DMA - * DMAMAP_SDIO_1 = Channel 4, Stream 3 - * DMAMAP_SDIO_2 = Channel 4, Stream 6 - */ - -#define DMAMAP_SDIO DMAMAP_SDIO_1 - -/* ZERO CROSS pin definition */ - -#define BOARD_ZEROCROSS_GPIO \ - (GPIO_INPUT|GPIO_FLOAT|GPIO_EXTI|GPIO_PORTD|GPIO_PIN0) - -/* Pin for APDS-9960 sensor */ - -#define GPIO_APDS9960_INT \ - (GPIO_INPUT|GPIO_FLOAT|GPIO_EXTI|GPIO_PORTE|GPIO_PIN0) - -#define BOARD_APDS9960_GPIO_INT GPIO_APDS9960_INT - -/* IRQ Pin for MPR121 Capacitive Keypad */ - -#define GPIO_MPR121_INT \ - (GPIO_INPUT|GPIO_PULLUP|GPIO_EXTI|GPIO_PORTB|GPIO_PIN0) - -#define BOARD_MPR121_GPIO_INT GPIO_MPR121_INT - -/* Pin for Magnetic Encoder MT6816 */ - -#define GPIO_CS_MT6816 (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz|\ - GPIO_OUTPUT_SET|GPIO_PORTE|GPIO_PIN3) - -/* LIS3DSH */ - -#define GPIO_LIS3DSH_EXT0 \ - (GPIO_INPUT|GPIO_FLOAT|GPIO_AF0|GPIO_SPEED_50MHz|GPIO_PORTE|GPIO_PIN0) - -#define BOARD_LIS3DSH_GPIO_EXT0 GPIO_LIS3DSH_EXT0 - -/* XEN1210 magnetic sensor */ - -#define GPIO_XEN1210_INT (GPIO_INPUT|GPIO_FLOAT|GPIO_EXTI|\ - GPIO_OPENDRAIN|GPIO_PORTA|GPIO_PIN5) - -#define GPIO_CS_XEN1210 (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz|\ - GPIO_OUTPUT_SET|GPIO_PORTA|GPIO_PIN4) - -#define BOARD_XEN1210_GPIO_INT GPIO_XEN1210_INT - -#define BOARD_SBUTTON_GPIO_INT (GPIO_INPUT|GPIO_FLOAT|GPIO_EXTI|\ - GPIO_OPENDRAIN|GPIO_PORTA|GPIO_PIN0) - -/* Define what timer to use as XEN1210 CLK (will use channel 1) */ - -#define BOARD_XEN1210_PWMTIMER 1 - -/* Keyboard Matrix Configuration */ - -/* Define keyboard matrix row pins (outputs) */ - -#define GPIO_KMATRIX_ROW0 (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz|\ - GPIO_OUTPUT_CLEAR|GPIO_PORTE|GPIO_PIN7) -#define GPIO_KMATRIX_ROW1 (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz|\ - GPIO_OUTPUT_CLEAR|GPIO_PORTE|GPIO_PIN8) -#define GPIO_KMATRIX_ROW2 (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz|\ - GPIO_OUTPUT_CLEAR|GPIO_PORTE|GPIO_PIN9) -#define GPIO_KMATRIX_ROW3 (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz|\ - GPIO_OUTPUT_CLEAR|GPIO_PORTE|GPIO_PIN10) - -/* Row pins as inputs with pull-up for early diagnostics */ - -#define GPIO_KMATRIX_ROW0_IN (GPIO_INPUT|GPIO_PULLUP|GPIO_SPEED_50MHz|\ - GPIO_PORTE|GPIO_PIN7) -#define GPIO_KMATRIX_ROW1_IN (GPIO_INPUT|GPIO_PULLUP|GPIO_SPEED_50MHz|\ - GPIO_PORTE|GPIO_PIN8) -#define GPIO_KMATRIX_ROW2_IN (GPIO_INPUT|GPIO_PULLUP|GPIO_SPEED_50MHz|\ - GPIO_PORTE|GPIO_PIN9) -#define GPIO_KMATRIX_ROW3_IN (GPIO_INPUT|GPIO_PULLUP|GPIO_SPEED_50MHz|\ - GPIO_PORTE|GPIO_PIN10) - -/* Define keyboard matrix column pins (inputs) */ - -#define GPIO_KMATRIX_COL0 (GPIO_INPUT|GPIO_PULLUP|GPIO_SPEED_50MHz|\ - GPIO_PORTE|GPIO_PIN11) -#define GPIO_KMATRIX_COL1 (GPIO_INPUT|GPIO_PULLUP|GPIO_SPEED_50MHz|\ - GPIO_PORTE|GPIO_PIN13) -#define GPIO_KMATRIX_COL2 (GPIO_INPUT|GPIO_PULLUP|GPIO_SPEED_50MHz|\ - GPIO_PORTE|GPIO_PIN14) - -/* Column pins as outputs for diagnostics only */ - -#define GPIO_KMATRIX_COL0_OUT (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz|\ - GPIO_OUTPUT_CLEAR|GPIO_PORTE|GPIO_PIN11) -#define GPIO_KMATRIX_COL1_OUT (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz|\ - GPIO_OUTPUT_CLEAR|GPIO_PORTE|GPIO_PIN13) -#define GPIO_KMATRIX_COL2_OUT (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz|\ - GPIO_OUTPUT_CLEAR|GPIO_PORTE|GPIO_PIN14) - -/* Board-level KMATRIX pin definitions */ - -#define BOARD_KMATRIX_ROW0 GPIO_KMATRIX_ROW0 -#define BOARD_KMATRIX_ROW1 GPIO_KMATRIX_ROW1 -#define BOARD_KMATRIX_ROW2 GPIO_KMATRIX_ROW2 -#define BOARD_KMATRIX_ROW3 GPIO_KMATRIX_ROW3 - -#define BOARD_KMATRIX_ROW0_IN GPIO_KMATRIX_ROW0_IN -#define BOARD_KMATRIX_ROW1_IN GPIO_KMATRIX_ROW1_IN -#define BOARD_KMATRIX_ROW2_IN GPIO_KMATRIX_ROW2_IN -#define BOARD_KMATRIX_ROW3_IN GPIO_KMATRIX_ROW3_IN - -#define BOARD_KMATRIX_COL0 GPIO_KMATRIX_COL0 -#define BOARD_KMATRIX_COL1 GPIO_KMATRIX_COL1 -#define BOARD_KMATRIX_COL2 GPIO_KMATRIX_COL2 - -#define BOARD_KMATRIX_COL0_OUT GPIO_KMATRIX_COL0_OUT -#define BOARD_KMATRIX_COL1_OUT GPIO_KMATRIX_COL1_OUT -#define BOARD_KMATRIX_COL2_OUT GPIO_KMATRIX_COL2_OUT - -#ifdef CONFIG_INPUT_KMATRIX -int board_kmatrix_diag(int loops, int delay_ms); -#endif - -/* Keyboard Matrix I2C Configuration */ - -#define CONFIG_STM32_KMATRIX_I2C_BUS 1 /* I2C1 */ -#define CONFIG_STM32_KMATRIX_I2C_ADDR 0x20 /* MCP23X08/PCA9538 address */ -#define CONFIG_STM32_KMATRIX_I2C_FREQ 400000 /* 400 kHz */ - -/* MCO and ETH inputs (referenced by arch/eth driver) */ - -#define GPIO_MCO1 (GPIO_MCO1_0|GPIO_SPEED_100MHz) -#define GPIO_ETH_MDC (GPIO_ETH_MDC_0|GPIO_SPEED_100MHz) -#define GPIO_ETH_MDIO (GPIO_ETH_MDIO_0|GPIO_SPEED_100MHz) -#define GPIO_ETH_RMII_CRS_DV (GPIO_ETH_RMII_CRS_DV_0|GPIO_SPEED_100MHz) -#define GPIO_ETH_RMII_REF_CLK (GPIO_ETH_RMII_REF_CLK_0|GPIO_SPEED_100MHz) -#define GPIO_ETH_RMII_RXD0 (GPIO_ETH_RMII_RXD0_0|GPIO_SPEED_100MHz) -#define GPIO_ETH_RMII_RXD1 (GPIO_ETH_RMII_RXD1_0|GPIO_SPEED_100MHz) - -/* SDIO */ - -#define GPIO_SDIO_CK (GPIO_SDIO_CK_0|GPIO_SPEED_50MHz) -#define GPIO_SDIO_CMD (GPIO_SDIO_CMD_0|GPIO_SPEED_50MHz) -#define GPIO_SDIO_D0 (GPIO_SDIO_D0_0|GPIO_SPEED_50MHz) -#define GPIO_SDIO_D1 (GPIO_SDIO_D1_0|GPIO_SPEED_50MHz) -#define GPIO_SDIO_D2 (GPIO_SDIO_D2_0|GPIO_SPEED_50MHz) -#define GPIO_SDIO_D3 (GPIO_SDIO_D3_0|GPIO_SPEED_50MHz) - -/* USB OTG FS / OTG HS */ - -#define GPIO_OTGFS_DM (GPIO_OTGFS_DM_0|GPIO_SPEED_100MHz) -#define GPIO_OTGFS_DP (GPIO_OTGFS_DP_0|GPIO_SPEED_100MHz) -#define GPIO_OTGFS_ID (GPIO_OTGFS_ID_0|GPIO_SPEED_100MHz) -#define GPIO_OTGFS_SOF (GPIO_OTGFS_SOF_0|GPIO_SPEED_100MHz) -#define GPIO_OTGHSFS_DM (GPIO_OTGHSFS_DM_0|GPIO_SPEED_100MHz) -#define GPIO_OTGHSFS_DP (GPIO_OTGHSFS_DP_0|GPIO_SPEED_100MHz) -#define GPIO_OTGHSFS_ID (GPIO_OTGHSFS_ID_0|GPIO_SPEED_100MHz) - -/* DAC */ - -#define GPIO_DAC1_OUT1 GPIO_DAC1_OUT1_0 -#define GPIO_DAC1_OUT2 GPIO_DAC1_OUT2_0 - -/* I2S3 MCK (referenced by audio driver) */ - -#define GPIO_I2S3_MCK GPIO_I2S3_MCK_0 - -/* FSMC SRAM/LCD pins */ - -#define GPIO_FSMC_A0 (GPIO_FSMC_A0_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A1 (GPIO_FSMC_A1_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A2 (GPIO_FSMC_A2_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A3 (GPIO_FSMC_A3_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A4 (GPIO_FSMC_A4_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A5 (GPIO_FSMC_A5_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A6 (GPIO_FSMC_A6_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A7 (GPIO_FSMC_A7_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A8 (GPIO_FSMC_A8_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A9 (GPIO_FSMC_A9_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A10 (GPIO_FSMC_A10_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A11 (GPIO_FSMC_A11_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A12 (GPIO_FSMC_A12_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A13 (GPIO_FSMC_A13_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A14 (GPIO_FSMC_A14_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A15 (GPIO_FSMC_A15_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A16 (GPIO_FSMC_A16_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A17 (GPIO_FSMC_A17_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A18 (GPIO_FSMC_A18_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A19 (GPIO_FSMC_A19_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A20 (GPIO_FSMC_A20_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A21 (GPIO_FSMC_A21_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A22 (GPIO_FSMC_A22_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A23 (GPIO_FSMC_A23_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A24 (GPIO_FSMC_A24_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A25 (GPIO_FSMC_A25_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_D0 (GPIO_FSMC_D0_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_D1 (GPIO_FSMC_D1_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_D2 (GPIO_FSMC_D2_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_D3 (GPIO_FSMC_D3_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_D4 (GPIO_FSMC_D4_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_D5 (GPIO_FSMC_D5_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_D6 (GPIO_FSMC_D6_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_D7 (GPIO_FSMC_D7_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_D8 (GPIO_FSMC_D8_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_D9 (GPIO_FSMC_D9_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_D10 (GPIO_FSMC_D10_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_D11 (GPIO_FSMC_D11_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_D12 (GPIO_FSMC_D12_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_D13 (GPIO_FSMC_D13_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_D14 (GPIO_FSMC_D14_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_D15 (GPIO_FSMC_D15_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_NOE (GPIO_FSMC_NOE_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_NWE (GPIO_FSMC_NWE_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_NE1 (GPIO_FSMC_NE1_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_NE2 (GPIO_FSMC_NE2_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_NE3 (GPIO_FSMC_NE3_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_NE4 (GPIO_FSMC_NE4_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_NBL0 (GPIO_FSMC_NBL0_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_NBL1 (GPIO_FSMC_NBL1_0|GPIO_SPEED_100MHz) - -#endif /* __BOARDS_ARM_STM32_STM32F4DISCOVERY_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32/stm32f4discovery/kernel/CMakeLists.txt b/boards/arm/stm32/stm32f4discovery/kernel/CMakeLists.txt deleted file mode 100644 index 9691ef0269262..0000000000000 --- a/boards/arm/stm32/stm32f4discovery/kernel/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/stm32f4discovery/kernel/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -target_sources(nuttx_user PRIVATE stm32_userspace.c) diff --git a/boards/arm/stm32/stm32f4discovery/kernel/Makefile b/boards/arm/stm32/stm32f4discovery/kernel/Makefile deleted file mode 100644 index 1edb33f89baad..0000000000000 --- a/boards/arm/stm32/stm32f4discovery/kernel/Makefile +++ /dev/null @@ -1,94 +0,0 @@ -############################################################################ -# boards/arm/stm32/stm32f4discovery/kernel/Makefile -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/Make.defs - -# The entry point name (if none is provided in the .config file) - -CONFIG_INIT_ENTRYPOINT ?= user_start -ENTRYPT = $(patsubst "%",%,$(CONFIG_INIT_ENTRYPOINT)) - -# Get the paths to the libraries and the links script path in format that -# is appropriate for the host OS - -USER_LIBPATHS = $(addprefix -L,$(call CONVERT_PATH,$(addprefix $(TOPDIR)$(DELIM),$(dir $(USERLIBS))))) -USER_LDSCRIPT = -T $(call CONVERT_PATH,$(BOARD_DIR)$(DELIM)scripts$(DELIM)memory.ld) -USER_LDSCRIPT += -T $(call CONVERT_PATH,$(BOARD_DIR)$(DELIM)scripts$(DELIM)user-space.ld) -USER_HEXFILE += $(call CONVERT_PATH,$(TOPDIR)$(DELIM)nuttx_user.hex) -USER_SRECFILE += $(call CONVERT_PATH,$(TOPDIR)$(DELIM)nuttx_user.srec) -USER_BINFILE += $(call CONVERT_PATH,$(TOPDIR)$(DELIM)nuttx_user.bin) - -USER_LDFLAGS = --undefined=$(ENTRYPT) --entry=$(ENTRYPT) $(USER_LDSCRIPT) -USER_LDLIBS = $(patsubst lib%,-l%,$(basename $(notdir $(USERLIBS)))) -USER_LIBGCC = "${shell "$(CC)" $(ARCHCPUFLAGS) -print-libgcc-file-name}" - -# Source files - -CSRCS = stm32_userspace.c -COBJS = $(CSRCS:.c=$(OBJEXT)) -OBJS = $(COBJS) - -# Targets: - -all: $(TOPDIR)$(DELIM)nuttx_user.elf $(TOPDIR)$(DELIM)User.map -.PHONY: nuttx_user.elf depend clean distclean - -$(COBJS): %$(OBJEXT): %.c - $(call COMPILE, $<, $@) - -# Create the nuttx_user.elf file containing all of the user-mode code - -nuttx_user.elf: $(OBJS) - $(Q) $(LD) -o $@ $(USER_LDFLAGS) $(USER_LIBPATHS) $(OBJS) --start-group $(USER_LDLIBS) $(USER_LIBGCC) --end-group - -$(TOPDIR)$(DELIM)nuttx_user.elf: nuttx_user.elf - @echo "LD: nuttx_user.elf" - $(Q) cp -a nuttx_user.elf $(TOPDIR)$(DELIM)nuttx_user.elf -ifeq ($(CONFIG_INTELHEX_BINARY),y) - @echo "CP: nuttx_user.hex" - $(Q) $(OBJCOPY) $(OBJCOPYARGS) -O ihex nuttx_user.elf $(USER_HEXFILE) -endif -ifeq ($(CONFIG_MOTOROLA_SREC),y) - @echo "CP: nuttx_user.srec" - $(Q) $(OBJCOPY) $(OBJCOPYARGS) -O srec nuttx_user.elf $(USER_SRECFILE) -endif -ifeq ($(CONFIG_RAW_BINARY),y) - @echo "CP: nuttx_user.bin" - $(Q) $(OBJCOPY) $(OBJCOPYARGS) -O binary nuttx_user.elf $(USER_BINFILE) -endif - -$(TOPDIR)$(DELIM)User.map: nuttx_user.elf - @echo "MK: User.map" - $(Q) $(NM) nuttx_user.elf >$(TOPDIR)$(DELIM)User.map - $(Q) $(CROSSDEV)size nuttx_user.elf - -.depend: - -depend: .depend - -clean: - $(call DELFILE, nuttx_user.elf) - $(call DELFILE, "$(TOPDIR)$(DELIM)nuttx_user.*") - $(call DELFILE, "$(TOPDIR)$(DELIM)User.map") - $(call CLEAN) - -distclean: clean diff --git a/boards/arm/stm32/stm32f4discovery/kernel/stm32_userspace.c b/boards/arm/stm32/stm32f4discovery/kernel/stm32_userspace.c deleted file mode 100644 index ee6b7fab075d0..0000000000000 --- a/boards/arm/stm32/stm32f4discovery/kernel/stm32_userspace.c +++ /dev/null @@ -1,111 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f4discovery/kernel/stm32_userspace.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include -#include -#include -#include - -#if defined(CONFIG_BUILD_PROTECTED) && !defined(__KERNEL__) - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -#ifndef CONFIG_NUTTX_USERSPACE -# error "CONFIG_NUTTX_USERSPACE not defined" -#endif - -#if CONFIG_NUTTX_USERSPACE != 0x08020000 -# error "CONFIG_NUTTX_USERSPACE must be 0x08020000 to match memory.ld" -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -static struct userspace_data_s g_userspace_data = -{ - .us_heap = &g_mmheap, -}; - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/* These 'addresses' of these values are setup by the linker script. */ - -extern uint8_t _stext[]; /* Start of .text */ -extern uint8_t _etext[]; /* End_1 of .text + .rodata */ -extern const uint8_t _eronly[]; /* End+1 of read only section (.text + .rodata) */ -extern uint8_t _sdata[]; /* Start of .data */ -extern uint8_t _edata[]; /* End+1 of .data */ -extern uint8_t _sbss[]; /* Start of .bss */ -extern uint8_t _ebss[]; /* End+1 of .bss */ - -const struct userspace_s userspace locate_data(".userspace") = -{ - /* General memory map */ - - .us_entrypoint = CONFIG_INIT_ENTRYPOINT, - .us_textstart = (uintptr_t)_stext, - .us_textend = (uintptr_t)_etext, - .us_datasource = (uintptr_t)_eronly, - .us_datastart = (uintptr_t)_sdata, - .us_dataend = (uintptr_t)_edata, - .us_bssstart = (uintptr_t)_sbss, - .us_bssend = (uintptr_t)_ebss, - - /* User data memory structure */ - - .us_data = &g_userspace_data, - - /* Task/thread startup routines */ - - .task_startup = nxtask_startup, - - /* Signal handler trampoline */ - - .signal_handler = up_signal_handler, - - /* User-space work queue support (declared in include/nuttx/wqueue.h) */ - -#ifdef CONFIG_LIBC_USRWORK - .work_usrstart = work_usrstart, -#endif -}; - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -#endif /* CONFIG_BUILD_PROTECTED && !__KERNEL__ */ diff --git a/boards/arm/stm32/stm32f4discovery/scripts/Make.defs b/boards/arm/stm32/stm32f4discovery/scripts/Make.defs deleted file mode 100644 index 109235fb9cd97..0000000000000 --- a/boards/arm/stm32/stm32f4discovery/scripts/Make.defs +++ /dev/null @@ -1,41 +0,0 @@ -############################################################################ -# boards/arm/stm32/stm32f4discovery/scripts/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/.config -include $(TOPDIR)/tools/Config.mk -include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs - -LDSCRIPT = ld.script -ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) - -ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 - -CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) -CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) -CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -AFLAGS := $(CFLAGS) -D__ASSEMBLY__ - -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections -LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32/stm32f4discovery/scripts/kernel-space.ld b/boards/arm/stm32/stm32f4discovery/scripts/kernel-space.ld deleted file mode 100644 index b9bf5bf4bbb9d..0000000000000 --- a/boards/arm/stm32/stm32f4discovery/scripts/kernel-space.ld +++ /dev/null @@ -1,99 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f4discovery/scripts/kernel-space.ld - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* NOTE: This depends on the memory.ld script having been included prior to - * this script. - */ - -OUTPUT_ARCH(arm) -ENTRY(_stext) -SECTIONS -{ - .text : { - _stext = ABSOLUTE(.); - *(.vectors) - *(.text .text.*) - *(.fixup) - *(.gnu.warning) - *(.rodata .rodata.*) - *(.gnu.linkonce.t.*) - *(.glue_7) - *(.glue_7t) - *(.got) - *(.gcc_except_table) - *(.gnu.linkonce.r.*) - _etext = ABSOLUTE(.); - } > kflash - - .init_section : { - _sinit = ABSOLUTE(.); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) - KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) - _einit = ABSOLUTE(.); - } > kflash - - .ARM.extab : { - *(.ARM.extab*) - } > kflash - - __exidx_start = ABSOLUTE(.); - .ARM.exidx : { - *(.ARM.exidx*) - } > kflash - - __exidx_end = ABSOLUTE(.); - - _eronly = ABSOLUTE(.); - - .data : { - _sdata = ABSOLUTE(.); - *(.data .data.*) - *(.gnu.linkonce.d.*) - CONSTRUCTORS - . = ALIGN(4); - _edata = ABSOLUTE(.); - } > ksram AT > kflash - - .bss : { - _sbss = ABSOLUTE(.); - *(.bss .bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - . = ALIGN(8); - _ebss = ABSOLUTE(.); - } > ksram - - /* Stabs debugging sections */ - - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_info 0 : { *(.debug_info) } - .debug_line 0 : { *(.debug_line) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_aranges 0 : { *(.debug_aranges) } -} diff --git a/boards/arm/stm32/stm32f4discovery/scripts/ld.script b/boards/arm/stm32/stm32f4discovery/scripts/ld.script deleted file mode 100644 index 25abe6a015057..0000000000000 --- a/boards/arm/stm32/stm32f4discovery/scripts/ld.script +++ /dev/null @@ -1,126 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f4discovery/scripts/ld.script - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* The STM32F407VG has 1024Kb of FLASH beginning at address 0x0800:0000 and - * 192Kb of SRAM. SRAM is split up into three blocks: - * - * 1) 112Kb of SRAM beginning at address 0x2000:0000 - * 2) 16Kb of SRAM beginning at address 0x2001:c000 - * 3) 64Kb of CCM SRAM beginning at address 0x1000:0000 - * - * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 - * where the code expects to begin execution by jumping to the entry point in - * the 0x0800:0000 address - * range. - */ - -MEMORY -{ - flash (rx) : ORIGIN = 0x08000000, LENGTH = 1024K - sram (rwx) : ORIGIN = 0x20000000, LENGTH = 112K -} - -OUTPUT_ARCH(arm) -ENTRY(_stext) -EXTERN(_vectors) -SECTIONS -{ - .text : { - _stext = ABSOLUTE(.); - *(.vectors) - *(.text .text.*) - *(.fixup) - *(.gnu.warning) - *(.rodata .rodata.*) - *(.gnu.linkonce.t.*) - *(.glue_7) - *(.glue_7t) - *(.got) - *(.gcc_except_table) - *(.gnu.linkonce.r.*) - _etext = ABSOLUTE(.); - } > flash - - .init_section : ALIGN(4) { - _sinit = ABSOLUTE(.); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) - KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) - _einit = ABSOLUTE(.); - } > flash - - .ARM.extab : ALIGN(4) { - *(.ARM.extab*) - } > flash - - .ARM.exidx : ALIGN(4) { - __exidx_start = ABSOLUTE(.); - *(.ARM.exidx*) - __exidx_end = ABSOLUTE(.); - } > flash - - .tdata : { - _stdata = ABSOLUTE(.); - *(.tdata .tdata.* .gnu.linkonce.td.*); - _etdata = ABSOLUTE(.); - } > flash - - .tbss : { - _stbss = ABSOLUTE(.); - *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); - _etbss = ABSOLUTE(.); - } > flash - - _eronly = ABSOLUTE(.); - - .data : ALIGN(4) { - _sdata = ABSOLUTE(.); - *(.data .data.*) - *(.gnu.linkonce.d.*) - CONSTRUCTORS - . = ALIGN(4); - _edata = ABSOLUTE(.); - } > sram AT > flash - - .bss : ALIGN(4) { - _sbss = ABSOLUTE(.); - *(.bss .bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - . = ALIGN(4); - _ebss = ABSOLUTE(.); - } > sram - - /* Stabs debugging sections. */ - - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_info 0 : { *(.debug_info) } - .debug_line 0 : { *(.debug_line) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_aranges 0 : { *(.debug_aranges) } -} diff --git a/boards/arm/stm32/stm32f4discovery/scripts/memory.ld b/boards/arm/stm32/stm32f4discovery/scripts/memory.ld deleted file mode 100644 index d82501ffb65f7..0000000000000 --- a/boards/arm/stm32/stm32f4discovery/scripts/memory.ld +++ /dev/null @@ -1,88 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f4discovery/scripts/memory.ld - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* The STM32F407VG has 1024Kb of FLASH beginning at address 0x0800:0000 and - * 192Kb of SRAM. SRAM is split up into three blocks: - * - * 1) 112KB of SRAM beginning at address 0x2000:0000 - * 2) 16KB of SRAM beginning at address 0x2001:c000 - * 3) 64KB of CCM SRAM beginning at address 0x1000:0000 - * - * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 - * where the code expects to begin execution by jumping to the entry point in - * the 0x0800:0000 address range. - * - * For MPU support, the kernel-mode NuttX section is assumed to be 128Kb of - * FLASH and 4Kb of SRAM. That is an excessive amount for the kernel which - * should fit into 64KB and, of course, can be optimized as needed (See - * also boards/arm/stm32/stm32f4discovery/scripts/kernel-space.ld). Allowing the - * additional does permit addition debug instrumentation to be added to the - * kernel space without overflowing the partition. - * - * Alignment of the user space FLASH partition is also a critical factor: - * The user space FLASH partition will be spanned with a single region of - * size 2**n bytes. The alignment of the user-space region must be the same. - * As a consequence, as the user-space increases in size, the alignment - * requirement also increases. - * - * This alignment requirement means that the largest user space FLASH region - * you can have will be 512KB at it would have to be positioned at - * 0x08800000. If you change this address, don't forget to change the - * CONFIG_NUTTX_USERSPACE configuration setting to match and to modify - * the check in kernel/userspace.c. - * - * For the same reasons, the maximum size of the SRAM mapping is limited to - * 4KB. Both of these alignment limitations could be reduced by using - * multiple regions to map the FLASH/SDRAM range or perhaps with some - * clever use of subregions. - * - * A detailed memory map for the 112KB SRAM region is as follows: - * - * 0x2000 0000: Kernel .data region. Typical size: 0.1KB - * ------ ---- Kernel .bss region. Typical size: 1.8KB - * 0x2000 0800: Kernel IDLE thread stack (approximate). Size is - * determined by CONFIG_IDLETHREAD_STACKSIZE and - * adjustments for alignment. Typical is 1KB. - * ------ ---- Padded to 8KB - * 0x2000 2000: User .data region. Size is variable. - * ------ ---- User .bss region Size is variable. - * 0x2000 4000: Beginning of kernel heap. Size determined by - * CONFIG_MM_KERNEL_HEAPSIZE which must be set to 16Kb. - * 0x2000 8000: Beginning of 32Kb user heap. - * 0x2001 0000: The remainder of SRAM is, unfortunately, wasted. - * 0x2001 c000: End+1 of CPU RAM - */ - -MEMORY -{ - /* 1024Kb FLASH */ - - kflash (rx) : ORIGIN = 0x08000000, LENGTH = 128K - uflash (rx) : ORIGIN = 0x08020000, LENGTH = 128K - xflash (rx) : ORIGIN = 0x08040000, LENGTH = 768K - - /* 112Kb of contiguous SRAM */ - - ksram (rwx) : ORIGIN = 0x20000000, LENGTH = 16K - usram (rwx) : ORIGIN = 0x20004000, LENGTH = 16K - xsram (rwx) : ORIGIN = 0x20008000, LENGTH = 80K -} diff --git a/boards/arm/stm32/stm32f4discovery/scripts/user-space.ld b/boards/arm/stm32/stm32f4discovery/scripts/user-space.ld deleted file mode 100644 index 5e246bc28338f..0000000000000 --- a/boards/arm/stm32/stm32f4discovery/scripts/user-space.ld +++ /dev/null @@ -1,114 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f4discovery/scripts/user-space.ld - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* NOTE: This depends on the memory.ld script having been included prior to - * this script. - */ - -/* Make sure that the critical memory management functions are in user-space. - * the user heap memory manager will reside in user-space but be usable both - * by kernel- and user-space code - */ - -EXTERN(umm_initialize) -EXTERN(umm_addregion) - -EXTERN(malloc) -EXTERN(realloc) -EXTERN(zalloc) -EXTERN(free) - -OUTPUT_ARCH(arm) -SECTIONS -{ - .userspace : { - KEEP(*(.userspace)) - } > uflash - - .text : { - _stext = ABSOLUTE(.); - *(.text .text.*) - *(.fixup) - *(.gnu.warning) - *(.rodata .rodata.*) - *(.gnu.linkonce.t.*) - *(.glue_7) - *(.glue_7t) - *(.got) - *(.gcc_except_table) - *(.gnu.linkonce.r.*) - _etext = ABSOLUTE(.); - } > uflash - - .init_section : { - _sinit = ABSOLUTE(.); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) - KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) - _einit = ABSOLUTE(.); - } > uflash - - .ARM.extab : { - *(.ARM.extab*) - } > uflash - - __exidx_start = ABSOLUTE(.); - .ARM.exidx : { - *(.ARM.exidx*) - } > uflash - - __exidx_end = ABSOLUTE(.); - - _eronly = ABSOLUTE(.); - - .data : { - _sdata = ABSOLUTE(.); - *(.data .data.*) - *(.gnu.linkonce.d.*) - CONSTRUCTORS - . = ALIGN(4); - _edata = ABSOLUTE(.); - } > usram AT > uflash - - .bss : { - _sbss = ABSOLUTE(.); - *(.bss .bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - . = ALIGN(8); - _ebss = ABSOLUTE(.); - } > usram - - /* Stabs debugging sections */ - - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_info 0 : { *(.debug_info) } - .debug_line 0 : { *(.debug_line) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_aranges 0 : { *(.debug_aranges) } -} diff --git a/boards/arm/stm32/stm32f4discovery/src/CMakeLists.txt b/boards/arm/stm32/stm32f4discovery/src/CMakeLists.txt deleted file mode 100644 index e56c3f35a7d26..0000000000000 --- a/boards/arm/stm32/stm32f4discovery/src/CMakeLists.txt +++ /dev/null @@ -1,234 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/stm32f4discovery/src/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -set(SRCS stm32_boot.c stm32_bringup.c stm32_spi.c) - -if(CONFIG_ARCH_LEDS) - list(APPEND SRCS stm32_autoleds.c) -else() - list(APPEND SRCS stm32_userleds.c) -endif() - -if(CONFIG_AUDIO_CS43L22) - list(APPEND SRCS stm32_cs43l22.c) -endif() - -if(CONFIG_ARCH_BUTTONS) - list(APPEND SRCS stm32_buttons.c) -endif() - -if(CONFIG_STM32_CAN_CHARDRIVER) - list(APPEND SRCS stm32_can.c) -endif() - -if(CONFIG_STM32_OTGFS) - list(APPEND SRCS stm32_usb.c) -endif() - -if(CONFIG_LCD_ST7567) - list(APPEND SRCS stm32_st7567.c) -endif() - -if(CONFIG_ENC28J60) - list(APPEND SRCS stm32_enc28j60.c) -endif() - -if(CONFIG_LPWAN_SX127X) - list(APPEND SRCS stm32_sx127x.c) -endif() - -if(CONFIG_LCD_MAX7219) - list(APPEND SRCS stm32_max7219.c) -endif() - -if(CONFIG_LCD_ST7032) - list(APPEND SRCS stm32_st7032.c) -endif() - -if(CONFIG_PCA9635PW) - list(APPEND SRCS stm32_pca9635.c) -endif() - -if(CONFIG_STM32_SDIO) - list(APPEND SRCS stm32_sdio.c) -endif() - -if(CONFIG_STM32_ETHMAC) - list(APPEND SRCS stm32_ethernet.c) -endif() - -if(CONFIG_LEDS_MAX7219) - list(APPEND SRCS stm32_max7219_leds.c) -endif() - -if(CONFIG_RGBLED) - list(APPEND SRCS stm32_rgbled.c) -endif() - -if(CONFIG_RTC_DS1307) - list(APPEND SRCS stm32_ds1307.c) -endif() - -if(CONFIG_PWM) - list(APPEND SRCS stm32_pwm.c) -endif() - -if(CONFIG_BOARDCTL_RESET) - list(APPEND SRCS stm32_reset.c) -endif() - -if(CONFIG_ARCH_CUSTOM_PMINIT) - list(APPEND SRCS stm32_pm.c) -endif() - -if(CONFIG_PM_BUTTONS) - list(APPEND SRCS stm32_pmbuttons.c) -endif() - -if(CONFIG_ARCH_IDLE_CUSTOM) - list(APPEND SRCS stm32_idle.c) -endif() - -if(CONFIG_STM32_FSMC) - list(APPEND SRCS stm32_extmem.c) - - if(CONFIG_LCD_SSD1289) - list(APPEND SRCS stm32_ssd1289.c) - endif() -endif() - -if(CONFIG_LCD_SSD1351) - list(APPEND SRCS stm32_ssd1351.c) -endif() - -if(CONFIG_LCD_UG2864AMBAG01) - list(APPEND SRCS stm32_ug2864ambag01.c) -endif() - -if(CONFIG_LCD_UG2864HSWEG01) - list(APPEND SRCS stm32_ug2864hsweg01.c) -endif() - -if(CONFIG_TIMER) - list(APPEND SRCS stm32_timer.c) -endif() - -if(CONFIG_STM32_HCIUART) - if(CONFIG_BLUETOOTH_UART) - list(APPEND SRCS stm32_hciuart.c) - endif() -endif() - -if(CONFIG_STM32_ROMFS) - list(APPEND SRCS stm32_romfs_initialize.c) -endif() - -if(CONFIG_BOARDCTL_UNIQUEID) - list(APPEND SRCS stm32_uid.c) -endif() - -if(CONFIG_USBMSC) - list(APPEND SRCS stm32_usbmsc.c) -endif() - -if(NOT CONFIG_STM32_ETHMAC) - if(CONFIG_NETDEVICES) - list(APPEND SRCS stm32_netinit.c) - endif() -endif() - -if(CONFIG_MMCSD_SPI) - list(APPEND SRCS stm32_mmcsd.c) -endif() - -if(CONFIG_WL_GS2200M) - list(APPEND SRCS stm32_gs2200m.c) -endif() - -if(CONFIG_LCD_ST7789) - list(APPEND SRCS stm32_st7789.c) -endif() - -if(CONFIG_ADC_HX711) - list(APPEND SRCS stm32_hx711.c) -endif() - -target_sources(board PRIVATE ${SRCS}) - -# Set linker script based on build type -if(CONFIG_BUILD_PROTECTED) - set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/memory.ld" - "${NUTTX_BOARD_DIR}/scripts/kernel-space.ld") -else() - set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/ld.script") -endif() - -# TODO:move this to appropriate arch/toolchain level -set_property( - GLOBAL APPEND - PROPERTY COMPILE_OPTIONS $<$:-fno-strict-aliasing - -fomit-frame-pointer>) - -# TODO: see where to put pic flags set_property(TARGET nuttx APPEND PROPERTY -# NUTTX_COMPILE_OPTIONS $<$>:-fpic -msingle-pic-base -# -mpic-register=r10>) - -# ifeq ($(CONFIG_ARMV7M_TOOLCHAIN_CLANGL),y) ARCHCFLAGS += -nostdlib -# -ffreestanding ARCHCXXFLAGS += -nostdlib -ffreestanding else ARCHCFLAGS += -# -funwind-tables ARCHCXXFLAGS += -fno-rtti -funwind-tables ifneq -# ($(CONFIG_DEBUG_NOOPT),y) ARCHOPTIMIZATION += -fno-strength-reduce endif endif - -if(CONFIG_UNWINDER_ARM) - set_property( - TARGET nuttx - APPEND - PROPERTY NUTTX_COMPILE_OPTIONS -funwind-tables) - set_property(GLOBAL APPEND PROPERTY COMPILE_OPTIONS -fno-strength-reduce) -endif() - -# TODO: nxflat NXFLATLDFLAGS1 = -r -d -warn-common NXFLATLDFLAGS2 = -# $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -# -no-check-sections LDNXFLATFLAGS = -e main -s 2048 - -# Loadable module definitions - -set_property( - TARGET nuttx - APPEND - PROPERTY NUTTX_ELF_MODULE_COMPILE_OPTIONS -mlong-calls) -set_property( - TARGET nuttx - APPEND - PROPERTY NUTTX_ELF_MODULE_LINK_OPTIONS -r -e module_initialize -T - ${NUTTX_DIR}/libs/libc/elf/gnu-elf.ld) - -# ELF module definitions - -set_property( - TARGET nuttx - APPEND - PROPERTY NUTTX_ELF_APP_COMPILE_OPTIONS -mlong-calls) -set_property( - TARGET nuttx - APPEND - PROPERTY NUTTX_ELF_APP_LINK_OPTIONS -r -e main - -T${NUTTX_BOARD_DIR}/scripts/gnu-elf.ld) diff --git a/boards/arm/stm32/stm32f4discovery/src/Make.defs b/boards/arm/stm32/stm32f4discovery/src/Make.defs deleted file mode 100644 index d4a14a5c9f11b..0000000000000 --- a/boards/arm/stm32/stm32f4discovery/src/Make.defs +++ /dev/null @@ -1,195 +0,0 @@ -############################################################################ -# boards/arm/stm32/stm32f4discovery/src/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/Make.defs - -CSRCS = stm32_boot.c stm32_bringup.c stm32_spi.c - -ifeq ($(CONFIG_ARCH_LEDS),y) -CSRCS += stm32_autoleds.c -else -CSRCS += stm32_userleds.c -endif - -ifeq ($(CONFIG_AUDIO_CS43L22),y) -CSRCS += stm32_cs43l22.c -endif - -ifeq ($(CONFIG_ARCH_BUTTONS),y) -CSRCS += stm32_buttons.c -endif - -ifeq ($(CONFIG_STM32_CAN_CHARDRIVER),y) -CSRCS += stm32_can.c -endif - -ifeq ($(CONFIG_STM32_OTGFS),y) -CSRCS += stm32_usb.c -endif - -ifeq ($(CONFIG_LCD_ST7567),y) -CSRCS += stm32_st7567.c -endif - -ifeq ($(CONFIG_ENC28J60),y) -CSRCS += stm32_enc28j60.c -endif - -ifeq ($(CONFIG_NET_W5500),y) -CSRCS += stm32_w5500.c -endif - -ifeq ($(CONFIG_LPWAN_SX127X),y) -CSRCS += stm32_sx127x.c -endif - -ifeq ($(CONFIG_LCD_MAX7219),y) -CSRCS += stm32_max7219.c -endif - -ifeq ($(CONFIG_LCD_ST7032),y) -CSRCS += stm32_st7032.c -endif - -ifeq ($(CONFIG_PCA9635PW),y) -CSRCS += stm32_pca9635.c -endif - -ifeq ($(CONFIG_STM32_SDIO),y) -CSRCS += stm32_sdio.c -endif - -ifeq ($(CONFIG_STM32_ETHMAC),y) -CSRCS += stm32_ethernet.c -endif - -ifeq ($(CONFIG_LEDS_MAX7219),y) -CSRCS += stm32_max7219_leds.c -endif - -ifeq ($(CONFIG_RGBLED),y) -CSRCS += stm32_rgbled.c -endif - -ifeq ($(CONFIG_PWM),y) -CSRCS += stm32_pwm.c -endif - -ifeq ($(CONFIG_CAPTURE),y) -CSRCS += stm32_capture.c -endif - -ifeq ($(CONFIG_BOARDCTL_RESET),y) -CSRCS += stm32_reset.c -endif - -ifeq ($(CONFIG_ARCH_CUSTOM_PMINIT),y) -CSRCS += stm32_pm.c -endif - -ifeq ($(CONFIG_PM_BUTTONS),y) -CSRCS += stm32_pmbuttons.c -endif - -ifeq ($(CONFIG_ARCH_IDLE_CUSTOM),y) -CSRCS += stm32_idle.c -endif - -ifeq ($(CONFIG_STM32_FSMC),y) -CSRCS += stm32_extmem.c - -ifeq ($(CONFIG_LCD_SSD1289),y) -CSRCS += stm32_ssd1289.c -endif -endif - -ifeq ($(CONFIG_LCD_APA102),y) -CSRCS += stm32_apa102.c -endif - -ifeq ($(CONFIG_LCD_SSD1351),y) -CSRCS += stm32_ssd1351.c -endif - -ifeq ($(CONFIG_LCD_UG2864AMBAG01),y) -CSRCS += stm32_ug2864ambag01.c -endif - -ifeq ($(CONFIG_LCD_UG2864HSWEG01),y) -CSRCS += stm32_ug2864hsweg01.c -endif - -ifeq ($(CONFIG_TIMER),y) -CSRCS += stm32_timer.c -endif - -ifeq ($(CONFIG_STM32_HCIUART),y) -ifeq ($(CONFIG_BLUETOOTH_UART),y) -CSRCS += stm32_hciuart.c -endif -endif - -ifeq ($(CONFIG_STM32_ROMFS),y) -CSRCS += stm32_romfs_initialize.c -endif - -ifeq ($(CONFIG_BOARDCTL_UNIQUEID),y) -CSRCS += stm32_uid.c -endif - -ifeq ($(CONFIG_USBMSC),y) -CSRCS += stm32_usbmsc.c -endif - -ifneq ($(CONFIG_STM32_ETHMAC),y) -ifeq ($(CONFIG_NETDEVICES),y) -CSRCS += stm32_netinit.c -endif -endif - -ifeq ($(CONFIG_MMCSD_SPI),y) -CSRCS += stm32_mmcsd.c -endif - -ifeq ($(CONFIG_WL_GS2200M),y) -CSRCS += stm32_gs2200m.c -endif - -ifeq ($(CONFIG_LCD_ST7789),y) -CSRCS += stm32_st7789.c -endif - -ifeq ($(CONFIG_INPUT_DJOYSTICK),y) - CSRCS += stm32_djoystick.c -endif - -ifeq ($(CONFIG_USBDEV_COMPOSITE),y) - CSRCS += stm32_composite.c -endif - -ifeq ($(CONFIG_ADC_HX711),y) -CSRCS += stm32_hx711.c -endif - -DEPPATH += --dep-path board -VPATH += :board -CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/stm32f4discovery/src/stm32_apa102.c b/boards/arm/stm32/stm32f4discovery/src/stm32_apa102.c deleted file mode 100644 index 340db0bae338a..0000000000000 --- a/boards/arm/stm32/stm32f4discovery/src/stm32_apa102.c +++ /dev/null @@ -1,111 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f4discovery/src/stm32_apa102.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include - -#include -#include -#include -#include -#include - -#include "stm32_gpio.h" -#include "stm32_spi.h" -#include "stm32f4discovery.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#define LCD_SPI_PORTNO 1 /* On SPI1 */ - -#ifndef CONFIG_LCD_CONTRAST -# define CONFIG_LCD_CONTRAST 60 -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -struct spi_dev_s *g_spidev; -struct lcd_dev_s *g_lcddev; - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_lcd_initialize - ****************************************************************************/ - -int board_lcd_initialize(void) -{ - g_spidev = stm32_spibus_initialize(LCD_SPI_PORTNO); - - if (!g_spidev) - { - lcderr("ERROR: Failed to initialize SPI port %d\n", LCD_SPI_PORTNO); - return -ENODEV; - } - - return OK; -} - -/**************************************************************************** - * Name: board_lcd_getdev - ****************************************************************************/ - -struct lcd_dev_s *board_lcd_getdev(int lcddev) -{ - g_lcddev = apa102_initialize(g_spidev, lcddev); - if (!g_lcddev) - { - lcderr("ERROR: Failed to bind SPI port 1 to LCD %d\n", lcddev); - } - else - { - lcdinfo("SPI port 1 bound to LCD %d\n", lcddev); - - return g_lcddev; - } - - return NULL; -} - -/**************************************************************************** - * Name: board_lcd_uninitialize - ****************************************************************************/ - -void board_lcd_uninitialize(void) -{ - /* TO-FIX */ -} - diff --git a/boards/arm/stm32/stm32f4discovery/src/stm32_autoleds.c b/boards/arm/stm32/stm32f4discovery/src/stm32_autoleds.c deleted file mode 100644 index 2f886258095fa..0000000000000 --- a/boards/arm/stm32/stm32f4discovery/src/stm32_autoleds.c +++ /dev/null @@ -1,232 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f4discovery/src/stm32_autoleds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32.h" -#include "stm32f4discovery.h" - -#ifdef CONFIG_ARCH_LEDS - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* The following definitions map the encoded LED setting to GPIO settings */ - -#define STM32F4_LED1 (1 << 0) -#define STM32F4_LED2 (1 << 1) -#define STM32F4_LED3 (1 << 2) -#define STM32F4_LED4 (1 << 3) - -#define ON_SETBITS_SHIFT (0) -#define ON_CLRBITS_SHIFT (4) -#define OFF_SETBITS_SHIFT (8) -#define OFF_CLRBITS_SHIFT (12) - -#define ON_BITS(v) ((v) & 0xff) -#define OFF_BITS(v) (((v) >> 8) & 0x0ff) -#define SETBITS(b) ((b) & 0x0f) -#define CLRBITS(b) (((b) >> 4) & 0x0f) - -#define ON_SETBITS(v) (SETBITS(ON_BITS(v)) -#define ON_CLRBITS(v) (CLRBITS(ON_BITS(v)) -#define OFF_SETBITS(v) (SETBITS(OFF_BITS(v)) -#define OFF_CLRBITS(v) (CLRBITS(OFF_BITS(v)) - -#define LED_STARTED_ON_SETBITS ((STM32F4_LED1) << ON_SETBITS_SHIFT) -#define LED_STARTED_ON_CLRBITS ((STM32F4_LED2|STM32F4_LED3|STM32F4_LED4) << ON_CLRBITS_SHIFT) -#define LED_STARTED_OFF_SETBITS (0 << OFF_SETBITS_SHIFT) -#define LED_STARTED_OFF_CLRBITS ((STM32F4_LED1|STM32F4_LED2|STM32F4_LED3|STM32F4_LED4) << OFF_CLRBITS_SHIFT) - -#define LED_HEAPALLOCATE_ON_SETBITS ((STM32F4_LED2) << ON_SETBITS_SHIFT) -#define LED_HEAPALLOCATE_ON_CLRBITS ((STM32F4_LED1|STM32F4_LED3|STM32F4_LED4) << ON_CLRBITS_SHIFT) -#define LED_HEAPALLOCATE_OFF_SETBITS ((STM32F4_LED1) << OFF_SETBITS_SHIFT) -#define LED_HEAPALLOCATE_OFF_CLRBITS ((STM32F4_LED2|STM32F4_LED3|STM32F4_LED4) << OFF_CLRBITS_SHIFT) - -#define LED_IRQSENABLED_ON_SETBITS ((STM32F4_LED1|STM32F4_LED2) << ON_SETBITS_SHIFT) -#define LED_IRQSENABLED_ON_CLRBITS ((STM32F4_LED3|STM32F4_LED4) << ON_CLRBITS_SHIFT) -#define LED_IRQSENABLED_OFF_SETBITS ((STM32F4_LED2) << OFF_SETBITS_SHIFT) -#define LED_IRQSENABLED_OFF_CLRBITS ((STM32F4_LED1|STM32F4_LED3|STM32F4_LED4) << OFF_CLRBITS_SHIFT) - -#define LED_STACKCREATED_ON_SETBITS ((STM32F4_LED3) << ON_SETBITS_SHIFT) -#define LED_STACKCREATED_ON_CLRBITS ((STM32F4_LED1|STM32F4_LED2|STM32F4_LED4) << ON_CLRBITS_SHIFT) -#define LED_STACKCREATED_OFF_SETBITS ((STM32F4_LED1|STM32F4_LED2) << OFF_SETBITS_SHIFT) -#define LED_STACKCREATED_OFF_CLRBITS ((STM32F4_LED3|STM32F4_LED4) << OFF_CLRBITS_SHIFT) - -#define LED_INIRQ_ON_SETBITS ((STM32F4_LED1) << ON_SETBITS_SHIFT) -#define LED_INIRQ_ON_CLRBITS ((0) << ON_CLRBITS_SHIFT) -#define LED_INIRQ_OFF_SETBITS ((0) << OFF_SETBITS_SHIFT) -#define LED_INIRQ_OFF_CLRBITS ((STM32F4_LED1) << OFF_CLRBITS_SHIFT) - -#define LED_SIGNAL_ON_SETBITS ((STM32F4_LED2) << ON_SETBITS_SHIFT) -#define LED_SIGNAL_ON_CLRBITS ((0) << ON_CLRBITS_SHIFT) -#define LED_SIGNAL_OFF_SETBITS ((0) << OFF_SETBITS_SHIFT) -#define LED_SIGNAL_OFF_CLRBITS ((STM32F4_LED2) << OFF_CLRBITS_SHIFT) - -#define LED_ASSERTION_ON_SETBITS ((STM32F4_LED4) << ON_SETBITS_SHIFT) -#define LED_ASSERTION_ON_CLRBITS ((0) << ON_CLRBITS_SHIFT) -#define LED_ASSERTION_OFF_SETBITS ((0) << OFF_SETBITS_SHIFT) -#define LED_ASSERTION_OFF_CLRBITS ((STM32F4_LED4) << OFF_CLRBITS_SHIFT) - -#define LED_PANIC_ON_SETBITS ((STM32F4_LED4) << ON_SETBITS_SHIFT) -#define LED_PANIC_ON_CLRBITS ((0) << ON_CLRBITS_SHIFT) -#define LED_PANIC_OFF_SETBITS ((0) << OFF_SETBITS_SHIFT) -#define LED_PANIC_OFF_CLRBITS ((STM32F4_LED4) << OFF_CLRBITS_SHIFT) - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -static const uint16_t g_ledbits[8] = -{ - (LED_STARTED_ON_SETBITS | LED_STARTED_ON_CLRBITS | - LED_STARTED_OFF_SETBITS | LED_STARTED_OFF_CLRBITS), - - (LED_HEAPALLOCATE_ON_SETBITS | LED_HEAPALLOCATE_ON_CLRBITS | - LED_HEAPALLOCATE_OFF_SETBITS | LED_HEAPALLOCATE_OFF_CLRBITS), - - (LED_IRQSENABLED_ON_SETBITS | LED_IRQSENABLED_ON_CLRBITS | - LED_IRQSENABLED_OFF_SETBITS | LED_IRQSENABLED_OFF_CLRBITS), - - (LED_STACKCREATED_ON_SETBITS | LED_STACKCREATED_ON_CLRBITS | - LED_STACKCREATED_OFF_SETBITS | LED_STACKCREATED_OFF_CLRBITS), - - (LED_INIRQ_ON_SETBITS | LED_INIRQ_ON_CLRBITS | - LED_INIRQ_OFF_SETBITS | LED_INIRQ_OFF_CLRBITS), - - (LED_SIGNAL_ON_SETBITS | LED_SIGNAL_ON_CLRBITS | - LED_SIGNAL_OFF_SETBITS | LED_SIGNAL_OFF_CLRBITS), - - (LED_ASSERTION_ON_SETBITS | LED_ASSERTION_ON_CLRBITS | - LED_ASSERTION_OFF_SETBITS | LED_ASSERTION_OFF_CLRBITS), - - (LED_PANIC_ON_SETBITS | LED_PANIC_ON_CLRBITS | - LED_PANIC_OFF_SETBITS | LED_PANIC_OFF_CLRBITS) -}; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -static inline void led_clrbits(unsigned int clrbits) -{ - if ((clrbits & STM32F4_LED1) != 0) - { - stm32_gpiowrite(GPIO_LED1, false); - } - - if ((clrbits & STM32F4_LED2) != 0) - { - stm32_gpiowrite(GPIO_LED2, false); - } - - if ((clrbits & STM32F4_LED3) != 0) - { - stm32_gpiowrite(GPIO_LED3, false); - } - - if ((clrbits & STM32F4_LED4) != 0) - { - stm32_gpiowrite(GPIO_LED4, false); - } -} - -static inline void led_setbits(unsigned int setbits) -{ - if ((setbits & STM32F4_LED1) != 0) - { - stm32_gpiowrite(GPIO_LED1, true); - } - - if ((setbits & STM32F4_LED2) != 0) - { - stm32_gpiowrite(GPIO_LED2, true); - } - - if ((setbits & STM32F4_LED3) != 0) - { - stm32_gpiowrite(GPIO_LED3, true); - } - - if ((setbits & STM32F4_LED4) != 0) - { - stm32_gpiowrite(GPIO_LED4, true); - } -} - -static void led_setonoff(unsigned int bits) -{ - led_clrbits(CLRBITS(bits)); - led_setbits(SETBITS(bits)); -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_autoled_initialize - ****************************************************************************/ - -void board_autoled_initialize(void) -{ - /* Configure LED1-4 GPIOs for output */ - - stm32_configgpio(GPIO_LED1); - stm32_configgpio(GPIO_LED2); - stm32_configgpio(GPIO_LED3); - stm32_configgpio(GPIO_LED4); -} - -/**************************************************************************** - * Name: board_autoled_on - ****************************************************************************/ - -void board_autoled_on(int led) -{ - led_setonoff(ON_BITS(g_ledbits[led])); -} - -/**************************************************************************** - * Name: board_autoled_off - ****************************************************************************/ - -void board_autoled_off(int led) -{ - led_setonoff(OFF_BITS(g_ledbits[led])); -} - -#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/stm32f4discovery/src/stm32_boot.c b/boards/arm/stm32/stm32f4discovery/src/stm32_boot.c deleted file mode 100644 index b99a443e08df1..0000000000000 --- a/boards/arm/stm32/stm32f4discovery/src/stm32_boot.c +++ /dev/null @@ -1,118 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f4discovery/src/stm32_boot.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include -#include - -#include "arm_internal.h" -#include "nvic.h" -#include "itm.h" - -#include "stm32.h" -#include "stm32f4discovery.h" - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_boardinitialize - * - * Description: - * All STM32 architectures must provide the following entry point. This - * entry point is called early in the initialization -- after all memory - * has been configured and mapped but before any devices have been - * initialized. - * - ****************************************************************************/ - -void stm32_boardinitialize(void) -{ -#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || defined(CONFIG_STM32_SPI3) - /* Configure SPI chip selects if 1) SPI is not disabled, and 2) the weak - * function stm32_spidev_initialize() has been brought into the link. - */ - - if (stm32_spidev_initialize) - { - stm32_spidev_initialize(); - } -#endif - -#ifdef CONFIG_STM32_OTGFS - /* Initialize USB if the 1) OTG FS controller is in the configuration and - * 2) disabled, and 3) the weak function stm32_usbinitialize() has been - * brought into the build. Presumably either CONFIG_USBDEV or - * CONFIG_USBHOST is also selected. - */ - - if (stm32_usbinitialize) - { - stm32_usbinitialize(); - } -#endif - -#ifdef HAVE_NETMONITOR - /* Configure board resources to support networking. */ - - if (stm32_netinitialize) - { - stm32_netinitialize(); - } -#endif - -#ifdef CONFIG_ARCH_LEDS - /* Configure on-board LEDs if LED support has been selected. */ - - board_autoled_initialize(); -#endif -} - -/**************************************************************************** - * Name: board_late_initialize - * - * Description: - * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional - * initialization call will be performed in the boot-up sequence to a - * function called board_late_initialize(). board_late_initialize() will be - * called immediately after up_initialize() is called and just before the - * initial application is started. This additional initialization phase - * may be used, for example, to initialize board-specific device drivers. - * - ****************************************************************************/ - -#ifdef CONFIG_BOARD_LATE_INITIALIZE -void board_late_initialize(void) -{ - /* Perform board-specific initialization */ - - stm32_bringup(); -} -#endif diff --git a/boards/arm/stm32/stm32f4discovery/src/stm32_bringup.c b/boards/arm/stm32/stm32f4discovery/src/stm32_bringup.c deleted file mode 100644 index a5dae40aba65f..0000000000000 --- a/boards/arm/stm32/stm32f4discovery/src/stm32_bringup.c +++ /dev/null @@ -1,703 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f4discovery/src/stm32_bringup.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include - -#include - -#ifdef CONFIG_USBMONITOR -# include -#endif - -#include "stm32.h" -#include "stm32_romfs.h" - -#ifdef CONFIG_STM32_OTGFS -# include "stm32_usbhost.h" -#endif - -#ifdef CONFIG_INPUT_BUTTONS -# include -#endif - -#ifdef CONFIG_USERLED -# include -#endif - -#ifdef CONFIG_RNDIS -# include -#endif - -#ifdef CONFIG_SENSORS_APDS9960 -#include "stm32_apds9960.h" -#endif - -#ifdef CONFIG_SENSORS_MT6816 -#include "stm32_mt6816.h" -#endif - -#ifdef CONFIG_INPUT_MPR121_KEYPAD -#include "stm32_mpr121.h" -#endif - -#ifdef CONFIG_CL_MFRC522 -#include "stm32_mfrc522.h" -#endif - -#include "stm32f4discovery.h" - -/* Conditional logic in stm32f4discovery.h will determine if certain features - * are supported. Tests for these features need to be made after including - * stm32f4discovery.h. - */ - -#ifdef HAVE_RTC_DRIVER -# include -# include "stm32_rtc.h" -#endif - -/* The following are includes from board-common logic */ - -#ifdef CONFIG_SENSORS_BMP180 -#include "stm32_bmp180.h" -#endif - -#ifdef CONFIG_RTC_DS1307 -#include "stm32_ds1307.h" -#endif - -#ifdef CONFIG_SENSORS_MS56XX -#include "stm32_ms5611.h" -#endif - -#ifdef CONFIG_SENSORS_MAX6675 -#include "stm32_max6675.h" -#endif - -#ifdef CONFIG_INPUT_NUNCHUCK -#include "stm32_nunchuck.h" -#endif - -#ifdef CONFIG_INPUT_SBUTTON -#include "board_sbutton.h" -#endif - -#ifdef CONFIG_INPUT_KMATRIX -#include "stm32_kmatrix_gpio.h" -#endif - -#ifdef CONFIG_INPUT_KMATRIX_I2C -#include "stm32_kmatrix_i2c.h" -#endif - -#ifdef CONFIG_SENSORS_ZEROCROSS -#include "stm32_zerocross.h" -#endif - -#ifdef CONFIG_SENSORS_QENCODER -#include "board_qencoder.h" -#endif - -#ifdef CONFIG_SENSORS_BH1750FVI -#include "stm32_bh1750.h" -#endif - -#ifdef CONFIG_LIS3DSH -#include "stm32_lis3dsh.h" -#endif - -#ifdef CONFIG_LCD_BACKPACK -#include "stm32_lcd_backpack.h" -#endif - -#ifdef CONFIG_SENSORS_MAX31855 -#include "stm32_max31855.h" -#endif - -#ifdef CONFIG_SENSORS_MLX90614 -#include "stm32_mlx90614.h" -#endif - -#ifdef CONFIG_SENSORS_XEN1210 -#include "stm32_xen1210.h" -#endif - -#ifdef CONFIG_USBADB -# include -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_i2c_register - * - * Description: - * Register one I2C drivers for the I2C tool. - * - ****************************************************************************/ - -#if defined(CONFIG_I2C) && defined(CONFIG_SYSTEM_I2CTOOL) -static void stm32_i2c_register(int bus) -{ - struct i2c_master_s *i2c; - int ret; - - i2c = stm32_i2cbus_initialize(bus); - if (i2c == NULL) - { - syslog(LOG_ERR, "ERROR: Failed to get I2C%d interface\n", bus); - } - else - { - ret = i2c_register(i2c, bus); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: Failed to register I2C%d driver: %d\n", - bus, ret); - stm32_i2cbus_uninitialize(i2c); - } - } -} -#endif - -/**************************************************************************** - * Name: stm32_i2ctool - * - * Description: - * Register I2C drivers for the I2C tool. - * - ****************************************************************************/ - -#if defined(CONFIG_I2C) && defined(CONFIG_SYSTEM_I2CTOOL) -static void stm32_i2ctool(void) -{ - stm32_i2c_register(1); -#if 0 - stm32_i2c_register(1); - stm32_i2c_register(2); -#endif -} -#else -# define stm32_i2ctool() -#endif - -/**************************************************************************** - * Name: stm32_bringup - * - * Description: - * Perform architecture-specific initialization - * - * CONFIG_BOARD_LATE_INITIALIZE=y : - * Called from board_late_initialize(). - * - ****************************************************************************/ - -int stm32_bringup(void) -{ -#ifdef HAVE_RTC_DRIVER - struct rtc_lowerhalf_s *lower; -#endif - int ret = OK; - -#if defined(CONFIG_I2C) && defined(CONFIG_SYSTEM_I2CTOOL) - stm32_i2ctool(); -#endif - -#ifdef CONFIG_SENSORS_BMP180 - /* Initialize the BMP180 pressure sensor. */ - - ret = board_bmp180_initialize(0, 1); - if (ret < 0) - { - syslog(LOG_ERR, "Failed to initialize BMP180, error %d\n", ret); - return ret; - } -#endif - -#ifdef CONFIG_SENSORS_MS56XX - /* Initialize the MS5611 pressure sensor. */ - - ret = board_ms5611_initialize(0, 1); - if (ret < 0) - { - syslog(LOG_ERR, "Failed to initialize MS5611, error %d\n", ret); - return ret; - } -#endif - -#ifdef CONFIG_SENSORS_BH1750FVI - ret = board_bh1750_initialize(0, 1); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_bh1750initialize() failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_SENSORS_ZEROCROSS - /* Configure the zero-crossing driver */ - - board_zerocross_initialize(0); -#endif - -#ifdef CONFIG_SENSORS_MT6816 - /* Initialize MT6816 as /dev/qe0 on SPI1 */ - - ret = board_mt6816_initialize(0, 1); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: board_mt6816_initialize failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_LEDS_MAX7219 - ret = stm32_max7219init("/dev/numdisp0"); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: max7219_leds_register failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_INPUT_MPR121_KEYPAD - /* Initialize MPR121 using I2C1 bus to /dev/keypad0 */ - - ret = board_mpr121_initialize(0, 1); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: board_mpr121_initialize failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_LCD_ST7032 - ret = stm32_st7032init("/dev/slcd0"); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: st7032_register failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_RGBLED - /* Configure the RGB LED driver */ - - stm32_rgbled_setup(); -#endif - -#if defined(CONFIG_PCA9635PW) - /* Initialize the PCA9635 chip */ - - ret = stm32_pca9635_initialize(); - if (ret < 0) - { - serr("ERROR: stm32_pca9635_initialize failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_VIDEO_FB - /* Initialize and register the framebuffer driver */ - - ret = fb_register(0, 0); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: fb_register() failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_LCD_BACKPACK - /* slcd:0, i2c:1, rows=2, cols=16 */ - - ret = board_lcd_backpack_init(0, 1, 2, 16); - if (ret < 0) - { - syslog(LOG_ERR, "Failed to initialize PCF8574 LCD, error %d\n", ret); - return ret; - } -#endif - -#ifdef HAVE_SDIO - /* Initialize the SDIO block driver */ - - ret = stm32_sdio_initialize(); - if (ret != OK) - { - ferr("ERROR: Failed to initialize MMC/SD driver: %d\n", ret); - return ret; - } -#endif - -#ifdef CONFIG_MMCSD_SPI - /* Initialize the MMC/SD SPI driver (SPI2 is used) */ - - ret = stm32_mmcsd_initialize(2, CONFIG_NSH_MMCSDMINOR); - if (ret < 0) - { - syslog(LOG_ERR, "Failed to initialize SD slot %d: %d\n", - CONFIG_NSH_MMCSDMINOR, ret); - } -#endif - -#ifdef HAVE_USBHOST - /* Initialize USB host operation. stm32_usbhost_initialize() starts a - * thread will monitor for USB connection and disconnection events. - */ - - ret = stm32_usbhost_initialize(); - if (ret != OK) - { - uerr("ERROR: Failed to initialize USB host: %d\n", ret); - return ret; - } -#endif - -#ifdef HAVE_USBMONITOR - /* Start the USB Monitor */ - - ret = usbmonitor_start(); - if (ret != OK) - { - uerr("ERROR: Failed to start USB monitor: %d\n", ret); - return ret; - } -#endif - -#ifdef CONFIG_PWM - /* Initialize PWM and register the PWM device. */ - - ret = stm32_pwm_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_pwm_setup() failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_TIMER - /* Initialize TIMER and register the TIMER device. */ - - ret = stm32_timer_driver_setup("/dev/timer0", CONFIG_STM32F4DISCO_TIMER); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_timer_driver_setup() failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_CAPTURE - /* Initialize Capture and register the Capture driver. */ - - ret = stm32_capture_setup("/dev/capture0"); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_capture_setup failed: %d\n", ret); - return ret; - } -#endif - -#ifdef CONFIG_STM32_CAN_CHARDRIVER - /* Initialize CAN and register the CAN driver. */ - - ret = stm32_can_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_can_setup failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_INPUT_BUTTONS - /* Register the BUTTON driver */ - - ret = btn_lower_initialize("/dev/buttons"); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: btn_lower_initialize() failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_INPUT_DJOYSTICK - ret = stm32_djoy_initialize(); - if (ret != OK) - { - syslog(LOG_ERR, "Failed to register djoystick driver: %d\n", ret); - } -#endif - -#ifdef CONFIG_INPUT_KMATRIX - /* Initialize and register the keyboard matrix driver */ - - ret = board_kmatrix_initialize(CONFIG_INPUT_KMATRIX_DEVPATH); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: board_kmatrix_initialize() failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_INPUT_KMATRIX_I2C - /* Initialize and register the keyboard matrix driver via I2C expander */ - - ret = board_kmatrix_i2c_initialize("/dev/kbd0"); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: board_kmatrix_i2c_initialize() failed: %d\n", - ret); - } -#endif - -#ifdef CONFIG_INPUT_NUNCHUCK - /* Register the Nunchuck driver */ - - ret = board_nunchuck_initialize(0, 1); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: nunchuck_initialize() failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_SENSORS_MLX90614 - ret = board_mlx90614_initialize(0, 1); - if (ret < 0) - { - syslog(LOG_ERR, "Failed to initialize MLX90614, error %d\n", ret); - return ret; - } -#endif - -#if defined(CONFIG_STM32_QE) && defined(CONFIG_SENSORS_QENCODER) - /* Initialize and register the qencoder driver */ - - ret = board_qencoder_initialize(0, CONFIG_STM32F4DISCO_QETIMER); - if (ret != OK) - { - syslog(LOG_ERR, - "ERROR: Failed to register the qencoder: %d\n", - ret); - return ret; - } -#endif - -#ifdef CONFIG_USERLED - /* Register the LED driver */ - - ret = userled_lower_initialize("/dev/userleds"); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: userled_lower_initialize() failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_INPUT_SBUTTON - /* Register the Single Button Dual Action driver */ - - ret = board_sbutton_initialize(0); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: board_sbtn_initialize() failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_SENSORS_APDS9960 - /* Register the APDS-9960 gesture sensor */ - - ret = board_apds9960_initialize(0, 1); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: board_apds9960_initialize() failed: %d\n", - ret); - } -#endif - -#ifdef CONFIG_RTC_DS1307 - ret = board_ds1307_initialize(1); - if (ret < 0) - { - syslog(LOG_ERR, "Failed to initialize DS1307 RTC driver: %d\n", ret); - return ret; - } -#endif - -#ifdef HAVE_RTC_DRIVER - /* Instantiate the STM32 lower-half RTC driver */ - - lower = stm32_rtc_lowerhalf(); - if (!lower) - { - serr("ERROR: Failed to instantiate the RTC lower-half driver\n"); - return -ENOMEM; - } - else - { - /* Bind the lower half driver and register the combined RTC driver - * as /dev/rtc0 - */ - - ret = rtc_initialize(0, lower); - if (ret < 0) - { - serr("ERROR: Failed to bind/register the RTC driver: %d\n", ret); - return ret; - } - } -#endif - -#ifdef HAVE_CS43L22 - /* Configure CS43L22 audio */ - - ret = stm32_cs43l22_initialize(1); - if (ret != OK) - { - serr("Failed to initialize CS43L22 audio: %d\n", ret); - } -#endif - -#ifdef CONFIG_SENSORS_MAX31855 - /* Register device 0 on spi channel 2 */ - - ret = board_max31855_initialize(0, 2); - if (ret < 0) - { - serr("ERROR: stm32_max31855initialize failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_SENSORS_MAX6675 - ret = board_max6675_initialize(0, 2); - if (ret < 0) - { - serr("ERROR: stm32_max6675initialize failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_FS_PROCFS - /* Mount the procfs file system */ - - ret = nx_mount(NULL, STM32_PROCFS_MOUNTPOINT, "procfs", 0, NULL); - if (ret < 0) - { - serr("ERROR: Failed to mount procfs at %s: %d\n", - STM32_PROCFS_MOUNTPOINT, ret); - } -#endif - -#ifdef CONFIG_FS_TMPFS - /* Mount the tmpfs file system */ - - ret = nx_mount(NULL, CONFIG_LIBC_TMPDIR, "tmpfs", 0, NULL); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: Failed to mount tmpfs at %s: %d\n", - CONFIG_LIBC_TMPDIR, ret); - } -#endif - -#ifdef CONFIG_STM32_ROMFS - ret = stm32_romfs_initialize(); - if (ret < 0) - { - serr("ERROR: Failed to mount romfs at %s: %d\n", - CONFIG_STM32_ROMFS_MOUNTPOINT, ret); - } -#endif - -#ifdef CONFIG_SENSORS_XEN1210 - ret = board_xen1210_initialize(0, 1); - if (ret < 0) - { - serr("ERROR: xen1210_archinitialize failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_LIS3DSH - /* Create a lis3dsh driver instance fitting the chip built into - * stm32f4discovery - */ - - ret = board_lis3dsh_initialize(0, 1); - if (ret < 0) - { - serr("ERROR: Failed to initialize LIS3DSH driver: %d\n", ret); - } -#endif - -#ifdef HAVE_HCIUART - ret = hciuart_dev_initialize(); - if (ret < 0) - { - serr("ERROR: Failed to initialize HCI UART driver: %d\n", ret); - } -#endif - -#if defined(CONFIG_RNDIS) && !defined(CONFIG_RNDIS_COMPOSITE) - uint8_t mac[6]; - mac[0] = 0xa0; /* TODO */ - mac[1] = (CONFIG_NETINIT_MACADDR_2 >> (8 * 0)) & 0xff; - mac[2] = (CONFIG_NETINIT_MACADDR_1 >> (8 * 3)) & 0xff; - mac[3] = (CONFIG_NETINIT_MACADDR_1 >> (8 * 2)) & 0xff; - mac[4] = (CONFIG_NETINIT_MACADDR_1 >> (8 * 1)) & 0xff; - mac[5] = (CONFIG_NETINIT_MACADDR_1 >> (8 * 0)) & 0xff; - usbdev_rndis_initialize(mac); -#endif - -#ifdef CONFIG_WL_GS2200M - ret = stm32_gs2200m_initialize("/dev/gs2200m", 3); - if (ret < 0) - { - serr("ERROR: Failed to initialize GS2200M: %d\n", ret); - } -#endif - -#ifdef CONFIG_LPWAN_SX127X - ret = stm32_lpwaninitialize(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: Failed to initialize wireless driver:" - " %d\n", ret); - } -#endif /* CONFIG_LPWAN_SX127X */ - -#ifdef CONFIG_USBADB - usbdev_adb_initialize(); -#endif - -#ifdef CONFIG_CL_MFRC522 - ret = stm32_mfrc522initialize("/dev/rfid0"); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_mfrc522initialize() failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_ADC_HX711 - ret = stm32_hx711_initialize(); - if (ret != OK) - { - aerr("ERROR: Failed to initialize hx711: %d\n", ret); - } -#endif - - return ret; -} diff --git a/boards/arm/stm32/stm32f4discovery/src/stm32_buttons.c b/boards/arm/stm32/stm32f4discovery/src/stm32_buttons.c deleted file mode 100644 index 8e2150389e12d..0000000000000 --- a/boards/arm/stm32/stm32f4discovery/src/stm32_buttons.c +++ /dev/null @@ -1,151 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f4discovery/src/stm32_buttons.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include -#include - -#include "stm32.h" -#include "stm32f4discovery.h" - -#ifdef CONFIG_ARCH_BUTTONS - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* Pin configuration for each STM32F4 Discovery button. This array is indexed - * by the BUTTON_* definitions in board.h - */ - -static const uint32_t g_buttons[NUM_BUTTONS] = -{ - GPIO_BTN_USER -}; - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_button_initialize - * - * Description: - * board_button_initialize() must be called to initialize button resources. - * After that, board_buttons() may be called to collect the current state - * of all buttons or board_button_irq() may be called to register button - * interrupt handlers. - * - ****************************************************************************/ - -uint32_t board_button_initialize(void) -{ - int i; - - /* Configure the GPIO pins as inputs. NOTE that EXTI interrupts are - * configured for all pins. - */ - - for (i = 0; i < NUM_BUTTONS; i++) - { - stm32_configgpio(g_buttons[i]); - } - - return NUM_BUTTONS; -} - -/**************************************************************************** - * Name: board_buttons - ****************************************************************************/ - -uint32_t board_buttons(void) -{ - uint32_t ret = 0; - int i; - - /* Check that state of each key */ - - for (i = 0; i < NUM_BUTTONS; i++) - { - /* A LOW value means that the key is pressed. */ - - bool released = stm32_gpioread(g_buttons[i]); - - /* Accumulate the set of depressed (not released) keys */ - - if (!released) - { - ret |= (1 << i); - } - } - - return ret; -} - -/**************************************************************************** - * Button support. - * - * Description: - * board_button_initialize() must be called to initialize button resources. - * After that, board_buttons() may be called to collect the current state - * of all buttons or board_button_irq() may be called to register button - * interrupt handlers. - * - * After board_button_initialize() has been called, board_buttons() may be - * called to collect the state of all buttons. board_buttons() returns an - * 32-bit bit set with each bit associated with a button. See the - * BUTTON_*_BIT definitions in board.h for the meaning of each bit. - * - * board_button_irq() may be called to register an interrupt handler that - * will be called when a button is depressed or released. The ID value is a - * button enumeration value that uniquely identifies a button resource. See - * the BUTTON_* definitions in board.h for the meaning of enumeration - * value. - * - ****************************************************************************/ - -#ifdef CONFIG_ARCH_IRQBUTTONS -int board_button_irq(int id, xcpt_t irqhandler, void *arg) -{ - int ret = -EINVAL; - - /* The following should be atomic */ - - if (id >= MIN_IRQBUTTON && id <= MAX_IRQBUTTON) - { - ret = stm32_gpiosetevent(g_buttons[id], true, true, true, - irqhandler, arg); - } - - return ret; -} -#endif -#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/stm32/stm32f4discovery/src/stm32_can.c b/boards/arm/stm32/stm32f4discovery/src/stm32_can.c deleted file mode 100644 index b919bdc52ee70..0000000000000 --- a/boards/arm/stm32/stm32f4discovery/src/stm32_can.c +++ /dev/null @@ -1,102 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f4discovery/src/stm32_can.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32.h" -#include "stm32_can.h" -#include "stm32f4discovery.h" - -#ifdef CONFIG_CAN - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -#if defined(CONFIG_STM32_CAN1) && defined(CONFIG_STM32_CAN2) -# warning "Both CAN1 and CAN2 are enabled. Assuming only CAN1." -# undef CONFIG_STM32_CAN2 -#endif - -#ifdef CONFIG_STM32_CAN1 -# define CAN_PORT 1 -#else -# define CAN_PORT 2 -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_can_setup - * - * Description: - * Initialize CAN and register the CAN device - * - ****************************************************************************/ - -int stm32_can_setup(void) -{ -#if defined(CONFIG_STM32_CAN1) || defined(CONFIG_STM32_CAN2) - struct can_dev_s *can; - int ret; - - /* Call stm32_caninitialize() to get an instance of the CAN interface */ - - can = stm32_caninitialize(CAN_PORT); - if (can == NULL) - { - canerr("ERROR: Failed to get CAN interface\n"); - return -ENODEV; - } - - /* Register the CAN driver at "/dev/can0" */ - - ret = can_register("/dev/can0", can); - if (ret < 0) - { - canerr("ERROR: can_register failed: %d\n", ret); - return ret; - } - - return OK; -#else - return -ENODEV; -#endif -} - -#endif /* CONFIG_CAN */ diff --git a/boards/arm/stm32/stm32f4discovery/src/stm32_capture.c b/boards/arm/stm32/stm32f4discovery/src/stm32_capture.c deleted file mode 100644 index df94bdee2a6e1..0000000000000 --- a/boards/arm/stm32/stm32f4discovery/src/stm32_capture.c +++ /dev/null @@ -1,112 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f4discovery/src/stm32_capture.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include -#include -#include - -#include "chip.h" - -#include "stm32.h" -#include "stm32_capture.h" -#include "arm_internal.h" - -#include "stm32f4discovery.h" - -#if defined(CONFIG_CAPTURE) -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Capture - * - * The stm32f4discovery has no real on-board pwm capture devices, but the - * board can be configured to capture pwm using TIM3 CH2 PB5. - */ - -#define HAVE_CAPTURE 1 - -#ifndef CONFIG_CAPTURE -# undef HAVE_CAPTURE -#endif - -#ifndef CONFIG_STM32_TIM3 -# undef HAVE_CAPTURE -#endif - -#ifndef CONFIG_STM32_TIM3_CAP -# undef HAVE_CAPTURE -#endif - -#if !defined(CONFIG_STM32_TIM3_CHANNEL) || CONFIG_STM32_TIM3_CHANNEL != STM32F4DISCOVERY_CAPTURECHANNEL -# undef HAVE_CAPTURE -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_capture_setup - * - * Description: - * Initialize and register the pwm capture driver. - * - * Input parameters: - * devpath - The full path to the driver to register. E.g., "/dev/capture0" - * - * Returned Value: - * Zero (OK) on success; a negated errno value on failure. - * - ****************************************************************************/ - -int stm32_capture_setup(const char *devpath) -{ -#ifdef HAVE_CAPTURE - struct cap_lowerhalf_s *capture; - int ret; - - capture = stm32_cap_initialize(STM32F4DISCOVERY_CAPTURETIMER); - - /* Then register the pwm capture sensor */ - - ret = cap_register(devpath, capture); - if (ret < 0) - { - mtrerr("ERROR: Error registering capture\n"); - } - - return ret; -#else - return -ENODEV; -#endif -} - -#endif /* CONFIG_CAPTURE */ diff --git a/boards/arm/stm32/stm32f4discovery/src/stm32_composite.c b/boards/arm/stm32/stm32f4discovery/src/stm32_composite.c deleted file mode 100644 index 12531a29de342..0000000000000 --- a/boards/arm/stm32/stm32f4discovery/src/stm32_composite.c +++ /dev/null @@ -1,349 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f4discovery/src/stm32_composite.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include -#include -#include - -#include -#include -#include -#include -#include - -#include "stm32_otgfs.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#define COMPOSITE0_DEV (3) - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -#ifdef CONFIG_USBMSC_COMPOSITE -static void *g_mschandle; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_mscclassobject - * - * Description: - * If the mass storage class driver is part of composite device, then - * its instantiation and configuration is a multi-step, board-specific, - * process (See comments for usbmsc_configure below). In this case, - * board-specific logic must provide board_mscclassobject(). - * - * board_mscclassobject() is called from the composite driver. It must - * encapsulate the instantiation and configuration of the mass storage - * class and the return the mass storage device's class driver instance - * to the composite driver. - * - * Input Parameters: - * classdev - The location to return the mass storage class' device - * instance. - * - * Returned Value: - * 0 on success; a negated errno on failure - * - ****************************************************************************/ - -#ifdef CONFIG_USBMSC_COMPOSITE -static int board_mscclassobject(int minor, - struct usbdev_devinfo_s *devinfo, - struct usbdevclass_driver_s **classdev) -{ - int ret; - - DEBUGASSERT(g_mschandle == NULL); - - /* Configure the mass storage device */ - - uinfo("Configuring with NLUNS=1\n"); - ret = usbmsc_configure(1, &g_mschandle); - if (ret < 0) - { - uerr("ERROR: usbmsc_configure failed: %d\n", -ret); - return ret; - } - - uinfo("MSC handle=%p\n", g_mschandle); - - /* Bind the LUN(s) */ - - uinfo("Bind LUN=0 to /dev/mmcsd0\n"); - ret = usbmsc_bindlun(g_mschandle, "/dev/mmcsd0", 0, 0, 0, false); - if (ret < 0) - { - uerr("ERROR: usbmsc_bindlun failed for LUN 1 at /dev/mmcsd0: %d\n", - ret); - usbmsc_uninitialize(g_mschandle); - g_mschandle = NULL; - return ret; - } - - /* Get the mass storage device's class object */ - - ret = usbmsc_classobject(g_mschandle, devinfo, classdev); - if (ret < 0) - { - uerr("ERROR: usbmsc_classobject failed: %d\n", -ret); - usbmsc_uninitialize(g_mschandle); - g_mschandle = NULL; - } - - return ret; -} -#endif - -/**************************************************************************** - * Name: board_mscuninitialize - * - * Description: - * Un-initialize the USB storage class driver. - * This is just an application specific wrapper for usbmsc_unitialize() - * that is called form the composite device logic. - * - * Input Parameters: - * classdev - The class driver instance previously given to the composite - * driver by board_mscclassobject(). - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef CONFIG_USBMSC_COMPOSITE -static void board_mscuninitialize(struct usbdevclass_driver_s *classdev) -{ - if (g_mschandle) - { - usbmsc_uninitialize(g_mschandle); - } - - g_mschandle = NULL; -} -#endif - -/**************************************************************************** - * Name: board_composite_connect - * - * Description: - * Connect the USB composite device on the specified USB device port for - * configuration 0. - * - * Input Parameters: - * port - The USB device port. - * - * Returned Value: - * A non-NULL handle value is returned on success. NULL is returned on - * any failure. - * - ****************************************************************************/ - -static void *board_composite0_connect(int port) -{ - struct composite_devdesc_s dev[COMPOSITE0_DEV]; - int ifnobase = 0; - int strbase = COMPOSITE_NSTRIDS; - int dev_idx = 0; - int epin = 1; - int epout = 1; - -#ifdef CONFIG_RNDIS_COMPOSITE - /* Configure the RNDIS USB device */ - - /* Ask the rndis driver to fill in the constants we didn't - * know here. - */ - - usbdev_rndis_get_composite_devdesc(&dev[dev_idx]); - - /* Interfaces */ - - dev[dev_idx].devinfo.ifnobase = ifnobase; - dev[dev_idx].minor = 0; - - /* Strings */ - - dev[dev_idx].devinfo.strbase = strbase; - - /* Endpoints */ - - dev[dev_idx].devinfo.epno[RNDIS_EP_INTIN_IDX] = epin++; - dev[dev_idx].devinfo.epno[RNDIS_EP_BULKIN_IDX] = epin++; - dev[dev_idx].devinfo.epno[RNDIS_EP_BULKOUT_IDX] = epout++; - - /* Count up the base numbers */ - - ifnobase += dev[dev_idx].devinfo.ninterfaces; - strbase += dev[dev_idx].devinfo.nstrings; - - dev_idx += 1; -#endif - -#ifdef CONFIG_USBMSC_COMPOSITE - /* Configure the mass storage device device */ - - /* Ask the usbmsc driver to fill in the constants we didn't - * know here. - */ - - usbmsc_get_composite_devdesc(&dev[dev_idx]); - - /* Overwrite and correct some values... */ - - /* The callback functions for the USBMSC class */ - - dev[dev_idx].classobject = board_mscclassobject; - dev[dev_idx].uninitialize = board_mscuninitialize; - - /* Interfaces */ - - dev[dev_idx].devinfo.ifnobase = ifnobase; /* Offset to Interface-IDs */ - dev[dev_idx].minor = 0; /* The minor interface number */ - - /* Strings */ - - dev[dev_idx].devinfo.strbase = strbase; /* Offset to String Numbers */ - - /* Endpoints */ - - dev[dev_idx].devinfo.epno[USBMSC_EP_BULKIN_IDX] = epin++; - dev[dev_idx].devinfo.epno[USBMSC_EP_BULKOUT_IDX] = epout++; - - /* Count up the base numbers */ - - ifnobase += dev[dev_idx].devinfo.ninterfaces; - strbase += dev[dev_idx].devinfo.nstrings; - - dev_idx += 1; -#endif - -#ifdef CONFIG_CDCACM_COMPOSITE - /* Configure the CDC/ACM device */ - - /* Ask the cdcacm driver to fill in the constants we didn't - * know here. - */ - - cdcacm_get_composite_devdesc(&dev[dev_idx]); - - /* Overwrite and correct some values... */ - - /* The callback functions for the CDC/ACM class */ - - dev[dev_idx].classobject = cdcacm_classobject; - dev[dev_idx].uninitialize = cdcacm_uninitialize; - - /* Interfaces */ - - dev[dev_idx].devinfo.ifnobase = ifnobase; /* Offset to Interface-IDs */ - dev[dev_idx].minor = 0; /* The minor interface number */ - - /* Strings */ - - dev[dev_idx].devinfo.strbase = strbase; /* Offset to String Numbers */ - - /* Endpoints */ - - dev[dev_idx].devinfo.epno[CDCACM_EP_INTIN_IDX] = epin++; - dev[dev_idx].devinfo.epno[CDCACM_EP_BULKIN_IDX] = epin++; - dev[dev_idx].devinfo.epno[CDCACM_EP_BULKOUT_IDX] = epout++; - - /* Count up the base numbers */ - - ifnobase += dev[dev_idx].devinfo.ninterfaces; - strbase += dev[dev_idx].devinfo.nstrings; - - dev_idx += 1; -#endif - - /* Sanity checks */ - - DEBUGASSERT(epin < STM32_NENDPOINTS); - DEBUGASSERT(epout < STM32_NENDPOINTS); - - return composite_initialize(composite_getdevdescs(), dev, dev_idx); -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_composite_initialize - * - * Description: - * Perform architecture specific initialization of a composite USB device. - * - ****************************************************************************/ - -int board_composite_initialize(int port) -{ - return OK; -} - -/**************************************************************************** - * Name: board_composite_connect - * - * Description: - * Connect the USB composite device on the specified USB device port using - * the specified configuration. The interpretation of the configid is - * board specific. - * - * Input Parameters: - * port - The USB device port. - * configid - The USB composite configuration - * - * Returned Value: - * A non-NULL handle value is returned on success. NULL is returned on - * any failure. - * - ****************************************************************************/ - -void *board_composite_connect(int port, int configid) -{ - if (configid == 0) - { - return board_composite0_connect(port); - } - else - { - return NULL; - } -} diff --git a/boards/arm/stm32/stm32f4discovery/src/stm32_djoystick.c b/boards/arm/stm32/stm32f4discovery/src/stm32_djoystick.c deleted file mode 100644 index dbbd33c9a4775..0000000000000 --- a/boards/arm/stm32/stm32f4discovery/src/stm32_djoystick.c +++ /dev/null @@ -1,299 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f4discovery/src/stm32_djoystick.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include -#include -#include - -#include "stm32_gpio.h" -#include "stm32f4discovery.h" - -#ifdef CONFIG_INPUT_DJOYSTICK - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Number of Joystick discretes 5-WAY */ - -#define DJOY_NGPIOS 5 - -/* Bitset of supported Joystick discretes */ - -#define DJOY_SUPPORTED (DJOY_UP_BIT | DJOY_DOWN_BIT | DJOY_LEFT_BIT | \ - DJOY_RIGHT_BIT | DJOY_BUTTON_SELECT_BIT) - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -static djoy_buttonset_t - djoy_supported(const struct djoy_lowerhalf_s *lower); -static djoy_buttonset_t - djoy_sample(const struct djoy_lowerhalf_s *lower); -static void djoy_enable(const struct djoy_lowerhalf_s *lower, - djoy_buttonset_t press, djoy_buttonset_t release, - djoy_interrupt_t handler, void *arg); - -static void djoy_disable(void); -static int djoy_interrupt(int irq, void *context, void *arg); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* Pin configuration for each Olimex-P407 joystick "button." Index using - * DJOY_* definitions in include/nuttx/input/djoystick.h. - */ - -static const uint16_t g_joygpio[DJOY_NGPIOS] = -{ - GPIO_JOY_UP, GPIO_JOY_DOWN, GPIO_JOY_LEFT, GPIO_JOY_RIGHT, GPIO_JOY_CENTER -}; - -/* Current interrupt handler and argument */ - -static djoy_interrupt_t g_djoyhandler; -static void *g_djoyarg; - -/* This is the discrete joystick lower half driver interface */ - -static const struct djoy_lowerhalf_s g_djoylower = -{ - .dl_supported = djoy_supported, - .dl_sample = djoy_sample, - .dl_enable = djoy_enable, -}; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: djoy_supported - * - * Description: - * Return the set of buttons supported on the discrete joystick device - * - ****************************************************************************/ - -static djoy_buttonset_t - djoy_supported(const struct djoy_lowerhalf_s *lower) -{ - iinfo("Supported: %02x\n", DJOY_SUPPORTED); - return (djoy_buttonset_t)DJOY_SUPPORTED; -} - -/**************************************************************************** - * Name: djoy_sample - * - * Description: - * Return the current state of all discrete joystick buttons - * - ****************************************************************************/ - -static djoy_buttonset_t djoy_sample(const struct djoy_lowerhalf_s *lower) -{ - djoy_buttonset_t ret = 0; - int i; - - /* Read each joystick GPIO value */ - - for (i = 0; i < DJOY_NGPIOS; i++) - { - bool released = stm32_gpioread(g_joygpio[i]); - if (!released) - { - ret |= (1 << i); - } - } - - iinfo("Retuning: %02x\n", DJOY_SUPPORTED); - return ret; -} - -/**************************************************************************** - * Name: djoy_enable - * - * Description: - * Enable interrupts on the selected set of joystick buttons. And empty - * set will disable all interrupts. - * - ****************************************************************************/ - -static void djoy_enable(const struct djoy_lowerhalf_s *lower, - djoy_buttonset_t press, djoy_buttonset_t release, - djoy_interrupt_t handler, void *arg) -{ - irqstate_t flags; - djoy_buttonset_t either = press | release; - djoy_buttonset_t bit; - bool rising; - bool falling; - int i; - - /* Start with all interrupts disabled */ - - flags = enter_critical_section(); - djoy_disable(); - - iinfo("press: %02x release: %02x handler: %p arg: %p\n", - press, release, handler, arg); - - /* If no events are indicated or if no handler is provided, then this - * must really be a request to disable interrupts. - */ - - if (either && handler) - { - /* Save the new the handler and argument */ - - g_djoyhandler = handler; - g_djoyarg = arg; - - /* Check each GPIO. */ - - for (i = 0; i < DJOY_NGPIOS; i++) - { - /* Enable interrupts on each pin that has either a press or - * release event associated with it. - */ - - bit = (1 << i); - if ((either & bit) != 0) - { - /* Active low so a press corresponds to a falling edge and - * a release corresponds to a rising edge. - */ - - falling = ((press & bit) != 0); - rising = ((release & bit) != 0); - - iinfo("GPIO %d: rising: %d falling: %d\n", - i, rising, falling); - - stm32_gpiosetevent(g_joygpio[i], rising, falling, - true, djoy_interrupt, NULL); - } - } - } - - leave_critical_section(flags); -} - -/**************************************************************************** - * Name: djoy_disable - * - * Description: - * Disable all joystick interrupts - * - ****************************************************************************/ - -static void djoy_disable(void) -{ - irqstate_t flags; - int i; - - /* Disable each joystick interrupt */ - - flags = enter_critical_section(); - for (i = 0; i < DJOY_NGPIOS; i++) - { - stm32_gpiosetevent(g_joygpio[i], false, false, false, NULL, NULL); - } - - leave_critical_section(flags); - - /* Nullify the handler and argument */ - - g_djoyhandler = NULL; - g_djoyarg = NULL; -} - -/**************************************************************************** - * Name: djoy_interrupt - * - * Description: - * Discrete joystick interrupt handler - * - ****************************************************************************/ - -static int djoy_interrupt(int irq, void *context, void *arg) -{ - DEBUGASSERT(g_djoyhandler); - if (g_djoyhandler) - { - g_djoyhandler(&g_djoylower, g_djoyarg); - } - - return OK; -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_djoy_initialize - * - * Description: - * Initialize and register the discrete joystick driver - * - ****************************************************************************/ - -int stm32_djoy_initialize(void) -{ - int i; - - /* Configure the GPIO pins as inputs. NOTE: This is unnecessary for - * interrupting pins since it will also be done by stm32_gpiosetevent(). - */ - - for (i = 0; i < DJOY_NGPIOS; i++) - { - stm32_configgpio(g_joygpio[i]); - } - - /* Make sure that all interrupts are disabled */ - - djoy_disable(); - - /* Register the joystick device as /dev/djoy0 */ - - return djoy_register("/dev/djoy0", &g_djoylower); -} - -#endif /* CONFIG_INPUT_DJOYSTICK */ diff --git a/boards/arm/stm32/stm32f4discovery/src/stm32_enc28j60.c b/boards/arm/stm32/stm32f4discovery/src/stm32_enc28j60.c deleted file mode 100644 index 5e7994ce3d030..0000000000000 --- a/boards/arm/stm32/stm32f4discovery/src/stm32_enc28j60.c +++ /dev/null @@ -1,219 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f4discovery/src/stm32_enc28j60.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* 2MBit SPI FLASH OR ENC28J60 - * - * -- ---- ------------ ----------------------------------------------------- - * PIN NAME SIGNAL NOTES - * -- ---- ------------ ----------------------------------------------------- - * - * 29 PA4 PA4-SPI1-NSS 10Mbit ENC28J60, SPI 2M FLASH - * 30 PA5 PA5-SPI1-SCK 2.4" TFT + Touchscreen, 10Mbit ENC28J60, SPI 2M FLASH - * 31 PA6 PA6-SPI1-MISO 2.4" TFT + Touchscreen, 10Mbit ENC28J60, SPI 2M FLASH - * 32 PA7 PA7-SPI1-MOSI 2.4" TFT + Touchscreen, 10Mbit ENC28J60, SPI 2M FLASH - */ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include - -#include -#include - -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32_spi.h" - -#include "stm32f4discovery.h" - -#ifdef CONFIG_ENC28J60 - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -/* ENC28J60 - * - * --- ------ -------------- ------------------------------------------------ - * PIN NAME SIGNAL NOTES - * --- ------ -------------- ------------------------------------------------ - * - * 29 PA4 PA4-SPI1-NSS 10Mbit ENC28J60, SPI 2M FLASH - * 30 PA5 PA5-SPI1-SCK 2.4" TFT + Touchscreen, - * 10Mbit ENC28J60, SPI 2M FLASH - * 31 PA6 PA6-SPI1-MISO 2.4" TFT + Touchscreen, - * 10Mbit ENC28J60, SPI 2M FLASH - * 32 PA7 PA7-SPI1-MOSI 2.4" TFT + Touchscreen, - * 10Mbit ENC28J60, SPI 2M FLASH - * 98 PE1 PE1-FSMC_NBL1 2.4" TFT + Touchscreen, - * 10Mbit EN28J60 Reset - * 4 PE5 (no name) 10Mbps ENC28J60 Interrupt - */ - -/* ENC28J60 is on SPI1 */ - -#ifndef CONFIG_STM32_SPI1 -# error "Need CONFIG_STM32_SPI1 in the configuration" -#endif - -/* SPI Assumptions **********************************************************/ - -#define ENC28J60_SPI_PORTNO 1 /* On SPI1 */ -#define ENC28J60_DEVNO 0 /* Only one ENC28J60 */ - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -struct stm32_lower_s -{ - const struct enc_lower_s lower; /* Low-level MCU interface */ - xcpt_t handler; /* ENC28J60 interrupt handler */ - void *arg; /* Argument that accompanies the interrupt */ -}; - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -static int up_attach(const struct enc_lower_s *lower, xcpt_t handler, - void *arg); -static void up_enable(const struct enc_lower_s *lower); -static void up_disable(const struct enc_lower_s *lower); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* The ENC28J60 normal provides interrupts to the MCU via a GPIO pin. The - * following structure provides an MCU-independent mechanixm for controlling - * the ENC28J60 GPIO interrupt. - */ - -static struct stm32_lower_s g_enclower = -{ - .lower = - { - .attach = up_attach, - .enable = up_enable, - .disable = up_disable - }, - .handler = NULL, - .arg = NULL -}; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: struct enc_lower_s methods - ****************************************************************************/ - -static int up_attach(const struct enc_lower_s *lower, xcpt_t handler, - void *arg) -{ - struct stm32_lower_s *priv = (struct stm32_lower_s *)lower; - - /* Just save the handler for use when the interrupt is enabled */ - - priv->handler = handler; - priv->arg = arg; - return OK; -} - -static void up_enable(const struct enc_lower_s *lower) -{ - struct stm32_lower_s *priv = (struct stm32_lower_s *)lower; - - DEBUGASSERT(priv->handler); - stm32_gpiosetevent(GPIO_ENC28J60_INTR, false, true, true, - priv->handler, priv->arg); -} - -/* REVISIT: Since the interrupt is completely torn down, not just disabled, - * in interrupt requests that occurs while the interrupt is disabled will be - * lost. - */ - -static void up_disable(const struct enc_lower_s *lower) -{ - stm32_gpiosetevent(GPIO_ENC28J60_INTR, false, true, true, - NULL, NULL); -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: arm_netinitialize - ****************************************************************************/ - -void arm_netinitialize(void) -{ - struct spi_dev_s *spi; - int ret; - - /* Assumptions: - * 1) ENC28J60 pins were configured in up_spi.c early in the boot-up phase. - * 2) Clocking for the SPI1 peripheral was also provided earlier in - * boot-up. - */ - - spi = stm32_spibus_initialize(ENC28J60_SPI_PORTNO); - if (!spi) - { - nerr("ERROR: Failed to initialize SPI port %d\n", ENC28J60_SPI_PORTNO); - return; - } - - /* Take ENC28J60 out of reset (active low) */ - - stm32_gpiowrite(GPIO_ENC28J60_RESET, true); - - /* Bind the SPI port to the ENC28J60 driver */ - - ret = enc_initialize(spi, &g_enclower.lower, ENC28J60_DEVNO); - if (ret < 0) - { - nerr("ERROR: Failed to bind SPI port %d ENC28J60 device %d: %d\n", - ENC28J60_SPI_PORTNO, ENC28J60_DEVNO, ret); - return; - } - - ninfo("Bound SPI port %d to ENC28J60 device %d\n", - ENC28J60_SPI_PORTNO, ENC28J60_DEVNO); -} - -#endif /* CONFIG_ENC28J60 */ diff --git a/boards/arm/stm32/stm32f4discovery/src/stm32_extmem.c b/boards/arm/stm32/stm32f4discovery/src/stm32_extmem.c deleted file mode 100644 index 49bb57a9d9553..0000000000000 --- a/boards/arm/stm32/stm32f4discovery/src/stm32_extmem.c +++ /dev/null @@ -1,140 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f4discovery/src/stm32_extmem.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32.h" -#include "stm32f4discovery.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#ifndef CONFIG_STM32_FSMC -# warning "FSMC is not enabled" -#endif - -#if STM32_NGPIO_PORTS < 6 -# error "Required GPIO ports not enabled" -#endif - -#define STM32_FSMC_NADDRCONFIGS 26 -#define STM32_FSMC_NDATACONFIGS 16 - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/* GPIO configurations common to most external memories */ - -static const uint32_t g_addressconfig[STM32_FSMC_NADDRCONFIGS] = -{ - GPIO_FSMC_A0, GPIO_FSMC_A1, GPIO_FSMC_A2, - GPIO_FSMC_A3, GPIO_FSMC_A4, GPIO_FSMC_A5, - GPIO_FSMC_A6, GPIO_FSMC_A7, GPIO_FSMC_A8, - GPIO_FSMC_A9, GPIO_FSMC_A10, GPIO_FSMC_A11, - GPIO_FSMC_A12, GPIO_FSMC_A13, GPIO_FSMC_A14, - GPIO_FSMC_A15, GPIO_FSMC_A16, GPIO_FSMC_A17, - GPIO_FSMC_A18, GPIO_FSMC_A19, GPIO_FSMC_A20, - GPIO_FSMC_A21, GPIO_FSMC_A22, GPIO_FSMC_A23, - GPIO_FSMC_A24, GPIO_FSMC_A25 -}; - -static const uint32_t g_dataconfig[STM32_FSMC_NDATACONFIGS] = -{ - GPIO_FSMC_D0, GPIO_FSMC_D1, GPIO_FSMC_D2, - GPIO_FSMC_D3, GPIO_FSMC_D4, GPIO_FSMC_D5, - GPIO_FSMC_D6, GPIO_FSMC_D7, GPIO_FSMC_D8, - GPIO_FSMC_D9, GPIO_FSMC_D10, GPIO_FSMC_D11, - GPIO_FSMC_D12, GPIO_FSMC_D13, GPIO_FSMC_D14, - GPIO_FSMC_D15 -}; - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_extmemgpios - * - * Description: - * Initialize GPIOs for external memory usage - * - ****************************************************************************/ - -void stm32_extmemgpios(const uint32_t *gpios, int ngpios) -{ - int i; - - /* Configure GPIOs */ - - for (i = 0; i < ngpios; i++) - { - stm32_configgpio(gpios[i]); - } -} - -/**************************************************************************** - * Name: stm32_extmemaddr - * - * Description: - * Initialize address line GPIOs for external memory access - * - ****************************************************************************/ - -void stm32_extmemaddr(int naddrs) -{ - stm32_extmemgpios(g_addressconfig, naddrs); -} - -/**************************************************************************** - * Name: stm32_extmemdata - * - * Description: - * Initialize data line GPIOs for external memory access - * - ****************************************************************************/ - -void stm32_extmemdata(int ndata) -{ - stm32_extmemgpios(g_dataconfig, ndata); -} diff --git a/boards/arm/stm32/stm32f4discovery/src/stm32_hciuart.c b/boards/arm/stm32/stm32f4discovery/src/stm32_hciuart.c deleted file mode 100644 index 899face28a1df..0000000000000 --- a/boards/arm/stm32/stm32f4discovery/src/stm32_hciuart.c +++ /dev/null @@ -1,84 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f4discovery/src/stm32_hciuart.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include - -#include - -#include "stm32_hciuart.h" -#include "stm32f4discovery.h" - -#include - -#ifdef HAVE_HCIUART - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: hciuart_dev_initialize - * - * Description: - * This function is called by board initialization logic to configure the - * Bluetooth HCI UART driver - * - * Input Parameters: - * None - * - * Returned Value: - * Zero is returned on success. Otherwise, a negated errno value is - * returned to indicate the nature of the failure. - * - ****************************************************************************/ - -int hciuart_dev_initialize(void) -{ - int ret; - - /* Perform one-time initialization */ - - hciuart_initialize(); - - /* Instantiate the HCI UART lower half interface - * Then initialize the HCI UART upper half driver with the bluetooth stack - */ - - ret = btuart_register(hciuart_instantiate(HCIUART_SERDEV)); - if (ret < 0) - { - wlerr("ERROR: btuart_register() failed: %d\n", ret); - } - - return ret; -} - -#endif /* HAVE_HCIUART */ diff --git a/boards/arm/stm32/stm32f4discovery/src/stm32_hx711.c b/boards/arm/stm32/stm32f4discovery/src/stm32_hx711.c deleted file mode 100644 index 30ab88b32e4df..0000000000000 --- a/boards/arm/stm32/stm32f4discovery/src/stm32_hx711.c +++ /dev/null @@ -1,104 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f4discovery/src/stm32_hx711.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include -#include -#include -#include -#include - -#include "stm32_gpio.h" -#include "stm32f4discovery.h" - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -static int stm32_hx711_clock_set(unsigned char minor, int value); -static int stm32_hx711_data_read(unsigned char minor); -static int stm32_hx711_data_irq(unsigned char minor, - xcpt_t handler, void *arg); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -struct hx711_lower_s g_lower = -{ - .data_read = stm32_hx711_data_read, - .clock_set = stm32_hx711_clock_set, - .data_irq = stm32_hx711_data_irq, - .cleanup = NULL -}; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -static int stm32_hx711_clock_set(unsigned char minor, int value) -{ - UNUSED(minor); - - stm32_gpiowrite(HX711_CLK_PIN, value); - return OK; -} - -static int stm32_hx711_data_read(unsigned char minor) -{ - UNUSED(minor); - - return stm32_gpioread(HX711_DATA_PIN); -} - -static int stm32_hx711_data_irq(unsigned char minor, - xcpt_t handler, void *arg) -{ - UNUSED(minor); - - return stm32_gpiosetevent(HX711_DATA_PIN, false, true, true, handler, arg); -}; - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -int stm32_hx711_initialize(void) -{ - int ret; - - stm32_configgpio(HX711_DATA_PIN); - stm32_configgpio(HX711_CLK_PIN); - - ret = hx711_register(0, &g_lower); - if (ret != 0) - { - aerr("ERROR: Failed to register hx711 device: %d\n", ret); - return -1; - } - - return OK; -} diff --git a/boards/arm/stm32/stm32f4discovery/src/stm32_idle.c b/boards/arm/stm32/stm32f4discovery/src/stm32_idle.c deleted file mode 100644 index f4b5bf5bbb847..0000000000000 --- a/boards/arm/stm32/stm32f4discovery/src/stm32_idle.c +++ /dev/null @@ -1,260 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f4discovery/src/stm32_idle.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include - -#include - -#include -#include -#include -#include - -#include - -#include "arm_internal.h" -#include "stm32_pm.h" -#include "stm32_rcc.h" -#include "stm32_exti.h" - -#include "stm32f4discovery.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -/* Does the board support an IDLE LED to indicate that the board is in the - * IDLE state? - */ - -#if defined(CONFIG_ARCH_LEDS) && defined(LED_IDLE) -# define BEGIN_IDLE() board_autoled_on(LED_IDLE) -# define END_IDLE() board_autoled_off(LED_IDLE) -#else -# define BEGIN_IDLE() -# define END_IDLE() -#endif - -/* Values for the RTC Alarm to wake up from the PM_STANDBY mode */ - -#ifndef CONFIG_PM_ALARM_SEC -# define CONFIG_PM_ALARM_SEC 3 -#endif - -#ifndef CONFIG_PM_ALARM_NSEC -# define CONFIG_PM_ALARM_NSEC 0 -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -#if 0 /* Not used */ -static void up_alarmcb(void); -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_idlepm - * - * Description: - * Perform IDLE state power management. - * - ****************************************************************************/ - -#ifdef CONFIG_PM -static void stm32_idlepm(void) -{ - static enum pm_state_e oldstate = PM_NORMAL; - enum pm_state_e newstate; - irqstate_t flags; - int ret; - - /* Decide, which power saving level can be obtained */ - - newstate = pm_checkstate(PM_IDLE_DOMAIN); - - /* Check for state changes */ - - if (newstate != oldstate) - { - sinfo("newstate= %d oldstate=%d\n", newstate, oldstate); - - flags = enter_critical_section(); - - /* Force the global state change */ - - ret = pm_changestate(PM_IDLE_DOMAIN, newstate); - if (ret < 0) - { - /* The new state change failed, revert to the preceding state */ - - pm_changestate(PM_IDLE_DOMAIN, oldstate); - - /* No state change... */ - - goto errout; - } - - /* Then perform board-specific, state-dependent logic here */ - - switch (newstate) - { - case PM_NORMAL: - { - } - break; - - case PM_IDLE: - { - } - break; - - case PM_STANDBY: - { -#ifdef CONFIG_RTC_ALARM - /* Disable RTC Alarm interrupt */ - -#warning "missing logic" - - /* Configure the RTC alarm to Auto Wake the system */ - -#warning "missing logic" - - /* The tv_nsec value must not exceed 1,000,000,000. That - * would be an invalid time. - */ - -#warning "missing logic" - - /* Set the alarm */ - -#warning "missing logic" -#endif - /* Call the STM32 stop mode */ - - stm32_pmstop(true); - - /* We have been re-awakened by some even: A button press? - * An alarm? Cancel any pending alarm and resume the normal - * operation. - */ - -#ifdef CONFIG_RTC_ALARM -#warning "missing logic" -#endif - /* Resume normal operation */ - - pm_changestate(PM_IDLE_DOMAIN, PM_NORMAL); - newstate = PM_NORMAL; - } - break; - - case PM_SLEEP: - { - /* We should not return from standby mode. The only way out - * of standby is via the reset path. - */ - - stm32_pmstandby(); - } - break; - - default: - break; - } - - /* Save the new state */ - - oldstate = newstate; - -errout: - leave_critical_section(flags); - } -} -#else -# define stm32_idlepm() -#endif - -/**************************************************************************** - * Name: up_alarmcb - * - * Description: - * RTC alarm service routine - * - ****************************************************************************/ - -#if 0 /* Not used */ -static void up_alarmcb(void) -{ - /* This alarm occurs because there wasn't any EXTI interrupt during the - * PM_STANDBY period. So just go to sleep. - */ - - pm_changestate(PM_IDLE_DOMAIN, PM_SLEEP); -} -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: up_idle - * - * Description: - * up_idle() is the logic that will be executed when their is no other - * ready-to-run task. This is processor idle time and will continue until - * some interrupt occurs to cause a context switch from the idle task. - * - * Processing in this state may be processor-specific. e.g., this is where - * power management operations might be performed. - * - ****************************************************************************/ - -void up_idle(void) -{ -#if defined(CONFIG_SUPPRESS_INTERRUPTS) || defined(CONFIG_SUPPRESS_TIMER_INTS) - /* If the system is idle and there are no timer interrupts, then process - * "fake" timer interrupts. Hopefully, something will wake up. - */ - - nxsched_process_timer(); -#else - - /* Perform IDLE mode power management */ - - BEGIN_IDLE(); - stm32_idlepm(); - END_IDLE(); -#endif -} diff --git a/boards/arm/stm32/stm32f4discovery/src/stm32_max7219.c b/boards/arm/stm32/stm32f4discovery/src/stm32_max7219.c deleted file mode 100644 index 6c4905055d75c..0000000000000 --- a/boards/arm/stm32/stm32f4discovery/src/stm32_max7219.c +++ /dev/null @@ -1,114 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f4discovery/src/stm32_max7219.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include - -#include -#include -#include -#include -#include - -#include "stm32_gpio.h" -#include "stm32_spi.h" -#include "stm32f4discovery.h" - -#ifdef CONFIG_NX_LCDDRIVER - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#define LCD_SPI_PORTNO 1 /* On SPI1 */ - -#ifndef CONFIG_LCD_CONTRAST -# define CONFIG_LCD_CONTRAST 60 -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -struct spi_dev_s *g_spidev; -struct lcd_dev_s *g_lcddev; - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_lcd_initialize - ****************************************************************************/ - -int board_lcd_initialize(void) -{ - g_spidev = stm32_spibus_initialize(LCD_SPI_PORTNO); - - if (g_spidev == NULL) - { - lcderr("ERROR: Failed to initialize SPI port %d\n", LCD_SPI_PORTNO); - return -ENODEV; - } - - return OK; -} - -/**************************************************************************** - * Name: board_lcd_getdev - ****************************************************************************/ - -struct lcd_dev_s *board_lcd_getdev(int lcddev) -{ - g_lcddev = max7219_initialize(g_spidev, lcddev); - if (!g_lcddev) - { - lcderr("ERROR: Failed to bind SPI port 1 to LCD %d\n", lcddev); - } - else - { - lcdinfo("SPI port 1 bound to LCD %d\n", lcddev); - - return g_lcddev; - } - - return NULL; -} - -/**************************************************************************** - * Name: board_lcd_uninitialize - ****************************************************************************/ - -void board_lcd_uninitialize(void) -{ - /* TO-FIX */ -} - -#endif /* CONFIG_NX_LCDDRIVER */ diff --git a/boards/arm/stm32/stm32f4discovery/src/stm32_mmcsd.c b/boards/arm/stm32/stm32f4discovery/src/stm32_mmcsd.c deleted file mode 100644 index 980b52d497b62..0000000000000 --- a/boards/arm/stm32/stm32f4discovery/src/stm32_mmcsd.c +++ /dev/null @@ -1,106 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f4discovery/src/stm32_mmcsd.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include -#include -#include -#include -#include -#include -#include - -#include "arm_internal.h" -#include "chip.h" -#include "stm32.h" - -#include -#include "stm32f4discovery.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#ifdef CONFIG_DISABLE_MOUNTPOINT -# error "SD driver requires CONFIG_DISABLE_MOUNTPOINT to be disabled" -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_spi1register - * - * Description: - * Registers media change callback - ****************************************************************************/ - -int stm32_spi2register(struct spi_dev_s *dev, spi_mediachange_t callback, - void *arg) -{ - /* TODO: media change callback */ - - return OK; -} - -/**************************************************************************** - * Name: stm32_mmcsd_initialize - * - * Description: - * Initialize SPI-based SD card and card detect thread. - ****************************************************************************/ - -int stm32_mmcsd_initialize(int port, int minor) -{ - struct spi_dev_s *spi; - int rv; - - stm32_configgpio(GPIO_MMCSD_NCD); /* Assign SD_DET */ - stm32_configgpio(GPIO_MMCSD_NSS); /* Assign CS */ - stm32_gpiowrite(GPIO_MMCSD_NSS, 1); /* Ensure the CS is inactive */ - - mcinfo("INFO: Initializing mmcsd port %d minor %d\n", - port, minor); - - spi = stm32_spibus_initialize(port); - if (spi == NULL) - { - mcerr("ERROR: Failed to initialize SPI port %d\n", port); - return -ENODEV; - } - - rv = mmcsd_spislotinitialize(minor, minor, spi); - if (rv < 0) - { - mcerr("ERROR: Failed to bind SPI port %d to SD slot %d\n", - port, minor); - return rv; - } - - spiinfo("INFO: mmcsd card has been initialized successfully\n"); - return OK; -} diff --git a/boards/arm/stm32/stm32f4discovery/src/stm32_netinit.c b/boards/arm/stm32/stm32f4discovery/src/stm32_netinit.c deleted file mode 100644 index f6a8f0af711c1..0000000000000 --- a/boards/arm/stm32/stm32f4discovery/src/stm32_netinit.c +++ /dev/null @@ -1,41 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f4discovery/src/stm32_netinit.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: arm_netinitialize - ****************************************************************************/ - -#if defined(CONFIG_NET) && !defined(CONFIG_NETDEV_LATEINIT) -void arm_netinitialize(void) -{ -} -#endif diff --git a/boards/arm/stm32/stm32f4discovery/src/stm32_pm.c b/boards/arm/stm32/stm32f4discovery/src/stm32_pm.c deleted file mode 100644 index d9ac5804f38b8..0000000000000 --- a/boards/arm/stm32/stm32f4discovery/src/stm32_pm.c +++ /dev/null @@ -1,75 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f4discovery/src/stm32_pm.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include - -#include "arm_internal.h" -#include "stm32_pm.h" -#include "stm32f4discovery.h" - -#ifdef CONFIG_PM - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_pminitialize - * - * Description: - * This function is called by MCU-specific logic at power-on reset in - * order to provide one-time initialization the power management subsystem. - * This function must be called *very* early in the initialization sequence - * *before* any other device drivers are initialized (since they may - * attempt to register with the power management subsystem). - * - * Input Parameters: - * None. - * - * Returned Value: - * None. - * - ****************************************************************************/ - -void arm_pminitialize(void) -{ - /* Initialize the NuttX power management subsystem proper */ - - pm_initialize(); - -#if defined(CONFIG_ARCH_IDLE_CUSTOM) && defined(CONFIG_PM_BUTTONS) - /* Initialize the buttons to wake up the system from low power modes */ - - stm32_pm_buttons(); -#endif - - /* Initialize the LED PM */ - - stm32_led_pminitialize(); -} - -#endif /* CONFIG_PM */ diff --git a/boards/arm/stm32/stm32f4discovery/src/stm32_pmbuttons.c b/boards/arm/stm32/stm32f4discovery/src/stm32_pmbuttons.c deleted file mode 100644 index 2d67dc8dd9c3b..0000000000000 --- a/boards/arm/stm32/stm32f4discovery/src/stm32_pmbuttons.c +++ /dev/null @@ -1,122 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f4discovery/src/stm32_pmbuttons.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include - -#include -#include - -#include -#include -#include - -#include "arm_internal.h" -#include "nvic.h" -#include "stm32_pwr.h" -#include "stm32_pm.h" -#include "stm32f4discovery.h" - -#if defined(CONFIG_PM) && defined(CONFIG_ARCH_IDLE_CUSTOM) && defined(CONFIG_PM_BUTTONS) - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -#ifndef CONFIG_ARCH_BUTTONS -# error "CONFIG_ARCH_BUTTONS is not defined in the configuration" -#endif - -#ifndef CONFIG_ARCH_IRQBUTTONS -# warning "CONFIG_ARCH_IRQBUTTONS is not defined in the configuration" -#endif - -#ifndef CONFIG_PM_BUTTON_ACTIVITY -# define CONFIG_PM_BUTTON_ACTIVITY 10 -#endif - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -#ifdef CONFIG_ARCH_IRQBUTTONS -static int button_handler(int irq, void *context, void *arg); -#endif /* CONFIG_ARCH_IRQBUTTONS */ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: button_handler - * - * Description: - * Handle a button wake-up interrupt - * - ****************************************************************************/ - -#ifdef CONFIG_ARCH_IRQBUTTONS -static int button_handler(int irq, void *context, void *arg) -{ - /* At this point the MCU should have already awakened. The state - * change will be handled in the IDLE loop when the system is re-awakened - * The button interrupt handler should be totally ignorant of the PM - * activities and should report button activity as if nothing - * special happened. - */ - - pm_activity(PM_IDLE_DOMAIN, CONFIG_PM_BUTTON_ACTIVITY); - return OK; -} -#endif /* CONFIG_ARCH_IRQBUTTONS */ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_pm_buttons - * - * Description: - * Configure the user button of the STM32f4discovery board as EXTI, - * so it is able to wakeup the MCU from the PM_STANDBY mode - * - ****************************************************************************/ - -void stm32_pm_buttons(void) -{ - /* Initialize the button GPIOs */ - - board_button_initialize(); - -#ifdef CONFIG_ARCH_IRQBUTTONS - board_button_irq(0, button_handler, NULL); -#endif -} - -#endif /* CONFIG_PM && CONFIG_ARCH_IDLE_CUSTOM && CONFIG_PM_BUTTONS)*/ diff --git a/boards/arm/stm32/stm32f4discovery/src/stm32_pwm.c b/boards/arm/stm32/stm32f4discovery/src/stm32_pwm.c deleted file mode 100644 index 089b3a8c74d68..0000000000000 --- a/boards/arm/stm32/stm32f4discovery/src/stm32_pwm.c +++ /dev/null @@ -1,125 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f4discovery/src/stm32_pwm.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32_pwm.h" -#include "stm32f4discovery.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -/* PWM - * - * The stm32f4discovery has no real on-board PWM devices, but the board can - * be configured to output a pulse train using TIM4 CH2. This pin is used by - * FSMC is connected to CN5 just for this purpose: - * - * PD13 FSMC_A18 / MC_TIM4_CH2OUT pin 33 (EnB) - * - * FSMC must be disabled in this case! - */ - -#define HAVE_PWM 1 - -#ifndef CONFIG_PWM -# undef HAVE_PWM -#endif - -#ifndef CONFIG_STM32_TIM4 -# undef HAVE_PWM -#endif - -#ifndef CONFIG_STM32_TIM4_PWM -# undef HAVE_PWM -#endif - -#if !defined(CONFIG_STM32_TIM4_CHANNEL) || CONFIG_STM32_TIM4_CHANNEL != STM32F4DISCOVERY_PWMCHANNEL -# undef HAVE_PWM -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_pwm_setup - * - * Description: - * Initialize PWM and register the PWM device. - * - ****************************************************************************/ - -int stm32_pwm_setup(void) -{ -#ifdef HAVE_PWM - static bool initialized = false; - struct pwm_lowerhalf_s *pwm; - int ret; - - /* Have we already initialized? */ - - if (!initialized) - { - /* Call stm32_pwminitialize() to get an instance of the PWM interface */ - - pwm = stm32_pwminitialize(STM32F4DISCOVERY_PWMTIMER); - if (!pwm) - { - aerr("ERROR: Failed to get the STM32 PWM lower half\n"); - return -ENODEV; - } - - /* Register the PWM driver at "/dev/pwm0" */ - - ret = pwm_register("/dev/pwm0", pwm); - if (ret < 0) - { - aerr("ERROR: pwm_register failed: %d\n", ret); - return ret; - } - - /* Now we are initialized */ - - initialized = true; - } - - return OK; -#else - return -ENODEV; -#endif -} diff --git a/boards/arm/stm32/stm32f4discovery/src/stm32_reset.c b/boards/arm/stm32/stm32f4discovery/src/stm32_reset.c deleted file mode 100644 index 9edc36b2a3017..0000000000000 --- a/boards/arm/stm32/stm32f4discovery/src/stm32_reset.c +++ /dev/null @@ -1,64 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f4discovery/src/stm32_reset.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#ifdef CONFIG_BOARDCTL_RESET - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_reset - * - * Description: - * Reset board. Support for this function is required by board-level - * logic if CONFIG_BOARDCTL_RESET is selected. - * - * Input Parameters: - * status - Status information provided with the reset event. This - * meaning of this status information is board-specific. If not - * used by a board, the value zero may be provided in calls to - * board_reset(). - * - * Returned Value: - * If this function returns, then it was not possible to power-off the - * board due to some constraints. The return value int this case is a - * board-specific reason for the failure to shutdown. - * - ****************************************************************************/ - -int board_reset(int status) -{ - up_systemreset(); - return 0; -} - -#endif /* CONFIG_BOARDCTL_RESET */ diff --git a/boards/arm/stm32/stm32f4discovery/src/stm32_rgbled.c b/boards/arm/stm32/stm32f4discovery/src/stm32_rgbled.c deleted file mode 100644 index 983d11293bcab..0000000000000 --- a/boards/arm/stm32/stm32f4discovery/src/stm32_rgbled.c +++ /dev/null @@ -1,173 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f4discovery/src/stm32_rgbled.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32_pwm.h" -#include "stm32f4discovery.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -#define HAVE_RGBLED 1 - -#ifndef CONFIG_PWM -# undef HAVE_RGBLED -#endif - -#ifndef CONFIG_STM32_TIM1 -# undef HAVE_RGBLED -#endif - -#ifndef CONFIG_STM32_TIM2 -# undef HAVE_RGBLED -#endif - -#ifndef CONFIG_STM32_TIM3 -# undef HAVE_RGBLED -#endif - -#ifndef CONFIG_STM32_TIM1_PWM -# undef HAVE_RGBLED -#endif - -#ifndef CONFIG_STM32_TIM2_PWM -# undef HAVE_RGBLED -#endif - -#ifndef CONFIG_STM32_TIM3_PWM -# undef HAVE_RGBLED -#endif - -#ifdef HAVE_RGBLED - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_rgbled_setup - * - * Description: - * Configure the RGB LED. - * - ****************************************************************************/ - -int stm32_rgbled_setup(void) -{ - static bool initialized = false; - struct pwm_lowerhalf_s *ledr; - struct pwm_lowerhalf_s *ledg; - struct pwm_lowerhalf_s *ledb; - struct pwm_info_s info; - int ret; - - /* Have we already initialized? */ - - if (!initialized) - { - /* Call stm32_pwminitialize() to get an instance of the PWM interface */ - - ledr = stm32_pwminitialize(1); - if (!ledr) - { - lederr("ERROR: Failed to get the STM32 PWM lower half to LEDR\n"); - return -ENODEV; - } - - /* Define frequency and duty cycle */ - - info.frequency = 100; - info.channels[0].duty = 0; - - /* Initialize LED R */ - - ledr->ops->setup(ledr); - ledr->ops->start(ledr, &info); - - /* Call stm32_pwminitialize() to get an instance of the PWM interface */ - - ledg = stm32_pwminitialize(2); - if (!ledg) - { - lederr("ERROR: Failed to get the STM32 PWM lower half to LEDG\n"); - return -ENODEV; - } - - /* Initialize LED G */ - - ledg->ops->setup(ledg); - ledg->ops->start(ledg, &info); - - /* Call stm32_pwminitialize() to get an instance of the PWM interface */ - - ledb = stm32_pwminitialize(3); - if (!ledb) - { - lederr("ERROR: Failed to get the STM32 PWM lower half to LEDB\n"); - return -ENODEV; - } - - /* Initialize LED B */ - - ledb->ops->setup(ledb); - ledb->ops->start(ledb, &info); - - /* Register the RGB LED diver at "/dev/rgbled0" */ - - ret = rgbled_register("/dev/rgbled0", ledr, ledg, ledb, - 1, CONFIG_STM32_TIM2_CHANNEL, - CONFIG_STM32_TIM3_CHANNEL); - if (ret < 0) - { - lederr("ERROR: rgbled_register failed: %d\n", ret); - return ret; - } - - /* Now we are initialized */ - - initialized = true; - } - - return OK; -} - -#else -# error "HAVE_RGBLED is undefined" -#endif /* HAVE_RGBLED */ diff --git a/boards/arm/stm32/stm32f4discovery/src/stm32_romfs.h b/boards/arm/stm32/stm32f4discovery/src/stm32_romfs.h deleted file mode 100644 index 8e47a501f46d4..0000000000000 --- a/boards/arm/stm32/stm32f4discovery/src/stm32_romfs.h +++ /dev/null @@ -1,77 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f4discovery/src/stm32_romfs.h - * - * SPDX-License-Identifier: BSD-3-Clause - * SPDX-FileCopyrightText: 2017 Tomasz Wozniak. All rights reserved. - * SPDX-FileContributor: Tomasz Wozniak - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -#ifndef __BOARDS_ARM_STM32_STM32F4DISCOVERY_SRC_STM32_ROMFS_H -#define __BOARDS_ARM_STM32_STM32F4DISCOVERY_SRC_STM32_ROMFS_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#ifdef CONFIG_STM32_ROMFS - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#define ROMFS_SECTOR_SIZE 64 - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_romfs_initialize - * - * Description: - * Registers built-in ROMFS image as block device and mounts it. - * - * Returned Value: - * Zero (OK) on success, a negated errno value on error. - * - * Assumptions/Limitations: - * Memory addresses [romfs_data_begin .. romfs_data_end) should contain - * ROMFS volume data, as included in the assembly snippet above (l. 84). - * - ****************************************************************************/ - -int stm32_romfs_initialize(void); - -#endif /* CONFIG_STM32_ROMFS */ - -#endif /* __BOARDS_ARM_STM32_STM32F4DISCOVERY_SRC_STM32_ROMFS_H */ diff --git a/boards/arm/stm32/stm32f4discovery/src/stm32_romfs_initialize.c b/boards/arm/stm32/stm32f4discovery/src/stm32_romfs_initialize.c deleted file mode 100644 index 7f56897a821c6..0000000000000 --- a/boards/arm/stm32/stm32f4discovery/src/stm32_romfs_initialize.c +++ /dev/null @@ -1,154 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f4discovery/src/stm32_romfs_initialize.c - * This file provides contents of an optional ROMFS volume, mounted at boot. - * - * SPDX-License-Identifier: BSD-3-Clause - * SPDX-FileCopyrightText: 2017 Tomasz Wozniak. All rights reserved. - * SPDX-FileContributor: Tomasz Wozniak - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include - -#include -#include -#include "stm32_romfs.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#ifndef CONFIG_STM32_ROMFS -# error "CONFIG_STM32_ROMFS must be defined" -#else - -#ifndef CONFIG_STM32_ROMFS_IMAGEFILE -# error "CONFIG_STM32_ROMFS_IMAGEFILE must be defined" -#endif - -#ifndef CONFIG_STM32_ROMFS_DEV_MINOR -# error "CONFIG_STM32_ROMFS_DEV_MINOR must be defined" -#endif - -#ifndef CONFIG_STM32_ROMFS_MOUNTPOINT -# error "CONFIG_STM32_ROMFS_MOUNTPOINT must be defined" -#endif - -#define NSECTORS(size) (((size) + ROMFS_SECTOR_SIZE - 1)/ROMFS_SECTOR_SIZE) - -#define STR2(m) #m -#define STR(m) STR2(m) - -#define MKMOUNT_DEVNAME(m) "/dev/ram" STR(m) -#define MOUNT_DEVNAME MKMOUNT_DEVNAME(CONFIG_STM32_ROMFS_DEV_MINOR) - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -__asm__ ( - ".section .rodata, \"a\"\n" - ".balign 16\n" - ".globl romfs_data_begin\n" -"romfs_data_begin:\n" - ".incbin " STR(CONFIG_STM32_ROMFS_IMAGEFILE) "\n"\ - \ - ".balign " STR(ROMFS_SECTOR_SIZE) "\n" - ".globl romfs_data_end\n" -"romfs_data_end:\n"); - -extern const uint8_t romfs_data_begin[]; -extern const uint8_t romfs_data_end[]; - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_romfs_initialize - * - * Description: - * Registers the aboveincluded binary file as block device. - * Then mounts the block device as ROMFS filesystems. - * - * Returned Value: - * Zero (OK) on success, a negated errno value on error. - * - * Assumptions/Limitations: - * Memory addresses [romfs_data_begin .. romfs_data_end) should contain - * ROMFS volume data, as included in the assembly snippet above (l. 84). - * - ****************************************************************************/ - -int stm32_romfs_initialize(void) -{ - size_t romfs_data_len; - int ret; - - /* Create a ROM disk for the /etc filesystem */ - - romfs_data_len = romfs_data_end - romfs_data_begin; - - ret = romdisk_register(CONFIG_STM32_ROMFS_DEV_MINOR, romfs_data_begin, - NSECTORS(romfs_data_len), ROMFS_SECTOR_SIZE); - if (ret < 0) - { - ferr("ERROR: romdisk_register failed: %d\n", -ret); - return ret; - } - - /* Mount the file system */ - - finfo("Mounting ROMFS filesystem at target=%s with source=%s\n", - CONFIG_STM32_ROMFS_MOUNTPOINT, MOUNT_DEVNAME); - - ret = nx_mount(MOUNT_DEVNAME, CONFIG_STM32_ROMFS_MOUNTPOINT, - "romfs", MS_RDONLY, NULL); - if (ret < 0) - { - ferr("ERROR: nx_mount(%s,%s,romfs) failed: %d\n", - MOUNT_DEVNAME, CONFIG_STM32_ROMFS_MOUNTPOINT, ret); - return ret; - } - - return OK; -} - -#endif /* CONFIG_STM32_ROMFS */ diff --git a/boards/arm/stm32/stm32f4discovery/src/stm32_sdio.c b/boards/arm/stm32/stm32f4discovery/src/stm32_sdio.c deleted file mode 100644 index 9a604e0817c5e..0000000000000 --- a/boards/arm/stm32/stm32f4discovery/src/stm32_sdio.c +++ /dev/null @@ -1,161 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f4discovery/src/stm32_sdio.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include - -#include -#include - -#include "stm32.h" -#include "stm32f4discovery.h" - -#ifdef HAVE_SDIO - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -/* Card detections requires card support and a card detection GPIO */ - -#define HAVE_NCD 1 -#if !defined(HAVE_SDIO) || !defined(GPIO_SDIO_NCD) -# undef HAVE_NCD -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -static struct sdio_dev_s *g_sdio_dev; -#ifdef HAVE_NCD -static bool g_sd_inserted; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_ncd_interrupt - * - * Description: - * Card detect interrupt handler. - * - ****************************************************************************/ - -#ifdef HAVE_NCD -static int stm32_ncd_interrupt(int irq, void *context, void *arg) -{ - bool present; - - present = !stm32_gpioread(GPIO_SDIO_NCD); - if (present != g_sd_inserted) - { - sdio_mediachange(g_sdio_dev, present); - g_sd_inserted = present; - } - - return OK; -} -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_sdio_initialize - * - * Description: - * Initialize SDIO-based MMC/SD card support - * - ****************************************************************************/ - -int stm32_sdio_initialize(void) -{ - int ret; - -#ifdef HAVE_NCD - /* Configure the card detect GPIO */ - - stm32_configgpio(GPIO_SDIO_NCD); - - /* Register an interrupt handler for the card detect pin */ - - stm32_gpiosetevent(GPIO_SDIO_NCD, true, true, true, - stm32_ncd_interrupt, NULL); -#endif - - /* Mount the SDIO-based MMC/SD block driver */ - - /* First, get an instance of the SDIO interface */ - - finfo("Initializing SDIO slot %d\n", SDIO_SLOTNO); - - g_sdio_dev = sdio_initialize(SDIO_SLOTNO); - if (!g_sdio_dev) - { - ferr("ERROR: Failed to initialize SDIO slot %d\n", SDIO_SLOTNO); - return -ENODEV; - } - - /* Now bind the SDIO interface to the MMC/SD driver */ - - finfo("Bind SDIO to the MMC/SD driver, minor=%d\n", SDIO_MINOR); - - ret = mmcsd_slotinitialize(SDIO_MINOR, g_sdio_dev); - if (ret != OK) - { - ferr("ERROR: Failed to bind SDIO to the MMC/SD driver: %d\n", ret); - return ret; - } - - finfo("Successfully bound SDIO to the MMC/SD driver\n"); - -#ifdef HAVE_NCD - /* Use SD card detect pin to check if a card is g_sd_inserted */ - - g_sd_inserted = !stm32_gpioread(GPIO_SDIO_NCD); - finfo("Card detect : %d\n", g_sd_inserted); - - sdio_mediachange(g_sdio_dev, g_sd_inserted); -#else - /* Assume that the SD card is inserted. What choice do we have? */ - - sdio_mediachange(g_sdio_dev, true); -#endif - - return OK; -} - -#endif /* HAVE_SDIO */ diff --git a/boards/arm/stm32/stm32f4discovery/src/stm32_spi.c b/boards/arm/stm32/stm32f4discovery/src/stm32_spi.c deleted file mode 100644 index a1026359b9485..0000000000000 --- a/boards/arm/stm32/stm32f4discovery/src/stm32_spi.c +++ /dev/null @@ -1,376 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f4discovery/src/stm32_spi.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include - -#include -#include - -#include "arm_internal.h" -#include "chip.h" -#include "stm32.h" - -#include "stm32f4discovery.h" - -#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || defined(CONFIG_STM32_SPI3) - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_spidev_initialize - * - * Description: - * Called to configure SPI chip select GPIO pins for the stm32f4discovery - * board. - * - ****************************************************************************/ - -void weak_function stm32_spidev_initialize(void) -{ -#ifdef CONFIG_ENC28J60 - stm32_configgpio(GPIO_ENC28J60_CS); - stm32_configgpio(GPIO_ENC28J60_RESET); - stm32_configgpio(GPIO_ENC28J60_INTR); -#endif - -#ifdef CONFIG_NET_W5500 - stm32_configgpio(GPIO_W5500_CS); - stm32_configgpio(GPIO_W5500_RESET); - stm32_configgpio(GPIO_W5500_INTR); -#endif - -#if defined(CONFIG_STM32_SPI1) && defined(CONFIG_SENSORS_LIS3MDL) - stm32_configgpio(GPIO_CS_MEMS); /* MEMS chip select */ -#endif - -#if defined(CONFIG_STM32_SPI1) && defined(CONFIG_CL_MFRC522) - stm32_configgpio(GPIO_CS_MFRC522); /* MFRC522 chip select */ -#endif - -#if defined(CONFIG_STM32_SPI1) && defined(CONFIG_SENSORS_MT6816) - stm32_configgpio(GPIO_CS_MT6816); -#endif - -#if defined(CONFIG_STM32_SPI2) && defined(CONFIG_SENSORS_MAX31855) - stm32_configgpio(GPIO_MAX31855_CS); /* MAX31855 chip select */ -#endif -#if defined(CONFIG_LCD_MAX7219) || defined(CONFIG_LEDS_MAX7219) - stm32_configgpio(GPIO_MAX7219_CS); /* MAX7219 chip select */ -#endif -#ifdef CONFIG_LPWAN_SX127X - stm32_configgpio(GPIO_SX127X_CS); /* SX127x chip select */ -#endif - -#if defined(CONFIG_LCD_ST7567) || defined(CONFIG_LCD_ST7567) - stm32_configgpio(STM32_LCD_CS); /* ST7567/ST7789 chip select */ -#endif -#if defined(CONFIG_STM32_SPI2) && defined(CONFIG_SENSORS_MAX6675) - stm32_configgpio(GPIO_MAX6675_CS); /* MAX6675 chip select */ -#endif -#if defined(CONFIG_LCD_UG2864AMBAG01) || defined(CONFIG_LCD_UG2864HSWEG01) || \ - defined(CONFIG_LCD_SSD1351) - stm32_configgpio(GPIO_OLED_CS); /* OLED chip select */ -# if defined(CONFIG_LCD_UG2864AMBAG01) - stm32_configgpio(GPIO_OLED_A0); /* OLED Command/Data */ -# endif -# if defined(CONFIG_LCD_UG2864HSWEG01) || defined(CONFIG_LCD_SSD1351) - stm32_configgpio(GPIO_OLED_DC); /* OLED Command/Data */ -# endif -#endif -} - -/**************************************************************************** - * Name: stm32_spi1/2/3select and stm32_spi1/2/3status - * - * Description: - * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status - * must be provided by board-specific logic. They are implementations of - * the select and status methods of the SPI interface defined by struct - * spi_ops_s (see include/nuttx/spi/spi.h). All other methods (including - * stm32_spibus_initialize()) are provided by common STM32 logic. To use - * this common SPI logic on your board: - * - * 1. Provide logic in stm32_boardinitialize() to configure SPI chip select - * pins. - * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() functions - * in your board-specific logic. These functions will perform chip - * selection and status operations using GPIOs in the way your board - * is configured. - * 3. Add a calls to stm32_spibus_initialize() in your low level - * application initialization logic - * 4. The handle returned by stm32_spibus_initialize() may then be used to - * bind the SPI driver to higher level logic (e.g., calling - * mmcsd_spislotinitialize(), for example, will bind the SPI driver to - * the SPI MMC/SD driver). - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_SPI1 -void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, - bool selected) -{ - spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : - "de-assert"); - -#ifdef CONFIG_ENC28J60 - if (devid == SPIDEV_ETHERNET(0)) - { - /* Set the GPIO low to select and high to de-select */ - - stm32_gpiowrite(GPIO_ENC28J60_CS, !selected); - } -#endif - -#ifdef CONFIG_NET_W5500 - if (devid == SPIDEV_ETHERNET(0)) - { - /* Set the GPIO low to select and high to de-select */ - - stm32_gpiowrite(GPIO_W5500_CS, !selected); - } -#endif - -#ifdef CONFIG_LPWAN_SX127X - if (devid == SPIDEV_LPWAN(0)) - { - stm32_gpiowrite(GPIO_SX127X_CS, !selected); - } -#endif - -#if defined(CONFIG_LCD_ST7567) || defined(CONFIG_LCD_ST7789) - if (devid == SPIDEV_DISPLAY(0)) - { - stm32_gpiowrite(STM32_LCD_CS, !selected); - } -#endif - -#if defined(CONFIG_LCD_MAX7219) || defined(CONFIG_LEDS_MAX7219) - if (devid == SPIDEV_DISPLAY(0)) - { - stm32_gpiowrite(GPIO_MAX7219_CS, !selected); - } -#endif - -#if defined(CONFIG_LCD_UG2864AMBAG01) || defined(CONFIG_LCD_UG2864HSWEG01) || \ - defined(CONFIG_LCD_SSD1351) - if (devid == SPIDEV_DISPLAY(0)) - { - stm32_gpiowrite(GPIO_OLED_CS, !selected); - } -#endif - -#if defined (CONFIG_SENSORS_LIS3MDL) - if (devid == SPIDEV_ACCELEROMETER(0)) - { - stm32_gpiowrite(GPIO_CS_MEMS, !selected); - } -#endif - -#if defined (CONFIG_SENSORS_MT6816) - if (devid == SPIDEV_MAG_ENCODER(0)) - { - stm32_gpiowrite(GPIO_CS_MT6816, !selected); - } -#endif - -#if defined(CONFIG_CL_MFRC522) - if (devid == SPIDEV_CONTACTLESS(0)) - { - stm32_gpiowrite(GPIO_CS_MFRC522, !selected); - } -#endif -} - -uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) -{ - uint8_t status = 0; - -#ifdef CONFIG_LPWAN_SX127X - if (devid == SPIDEV_LPWAN(0)) - { - status |= SPI_STATUS_PRESENT; - } -#endif - - return status; -} -#endif - -#ifdef CONFIG_STM32_SPI2 -void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid, - bool selected) -{ - spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : - "de-assert"); - -#if defined(CONFIG_SENSORS_MAX31855) - if (devid == SPIDEV_TEMPERATURE(0)) - { - stm32_gpiowrite(GPIO_MAX31855_CS, !selected); - } -#endif - -#if defined(CONFIG_SENSORS_MAX6675) - if (devid == SPIDEV_TEMPERATURE(0)) - { - stm32_gpiowrite(GPIO_MAX6675_CS, !selected); - } -#endif - -#if defined(CONFIG_MMCSD_SPI) - if (devid == SPIDEV_MMCSD(0)) - { - stm32_gpiowrite(GPIO_MMCSD_NSS, !selected); - } -#endif -} - -uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) -{ - uint8_t ret = 0; -#if defined(CONFIG_MMCSD_SPI) - if (devid == SPIDEV_MMCSD(0)) - { - /* Note: SD_DET is pulled high when there's no SD card present. */ - - ret = stm32_gpioread(GPIO_MMCSD_NCD) ? 0 : 1; - } -#endif - - return ret; -} -#endif - -#ifdef CONFIG_STM32_SPI3 -void stm32_spi3select(struct spi_dev_s *dev, uint32_t devid, - bool selected) -{ - spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : - "de-assert"); - -#if defined(CONFIG_WL_GS2200M) - if (devid == SPIDEV_WIRELESS(0)) - { - stm32_gpiowrite(GPIO_GS2200M_CS, !selected); - } -#endif -} - -uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid) -{ - return 0; -} -#endif - -/**************************************************************************** - * Name: stm32_spi1cmddata - * - * Description: - * Set or clear the SH1101A A0 or SD1306 D/C n bit to select data (true) - * or command (false). This function must be provided by platform-specific - * logic. This is an implementation of the cmddata method of the SPI - * interface defined by struct spi_ops_s (see include/nuttx/spi/spi.h). - * - * Input Parameters: - * - * spi - SPI device that controls the bus the device that requires the CMD/ - * DATA selection. - * devid - If there are multiple devices on the bus, this selects which one - * to select cmd or data. NOTE: This design restricts, for example, - * one one SPI display per SPI bus. - * cmd - true: select command; false: select data - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef CONFIG_SPI_CMDDATA -#ifdef CONFIG_STM32_SPI1 -int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) -{ -#if defined(CONFIG_LCD_ST7567) || defined(CONFIG_LCD_ST7789) - if (devid == SPIDEV_DISPLAY(0)) - { - /* This is the Data/Command control pad which determines whether the - * data bits are data or a command. - */ - - stm32_gpiowrite(STM32_LCD_RS, !cmd); - - return OK; - } -#endif - -#if defined(CONFIG_LCD_UG2864AMBAG01) || defined(CONFIG_LCD_UG2864HSWEG01) || \ - defined(CONFIG_LCD_SSD1351) - if (devid == SPIDEV_DISPLAY(0)) - { - /* "This is the Data/Command control pad which determines whether the - * data bits are data or a command. - * - * A0 = "H": the inputs at D0 to D7 are treated as display data. - * A0 = "L": the inputs at D0 to D7 are transferred to the command - * registers." - */ - -# if defined(CONFIG_LCD_UG2864AMBAG01) - stm32_gpiowrite(GPIO_OLED_A0, !cmd); -# endif -# if defined(CONFIG_LCD_UG2864HSWEG01) || defined(CONFIG_LCD_SSD1351) - stm32_gpiowrite(GPIO_OLED_DC, !cmd); -# endif - return OK; - } -#endif - - return -ENODEV; -} -#endif - -#ifdef CONFIG_STM32_SPI2 -int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) -{ - return -ENODEV; -} -#endif - -#ifdef CONFIG_STM32_SPI3 -int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) -{ - return -ENODEV; -} -#endif -#endif /* CONFIG_SPI_CMDDATA */ - -#endif /* CONFIG_STM32_SPI1 || CONFIG_STM32_SPI2 */ diff --git a/boards/arm/stm32/stm32f4discovery/src/stm32_ssd1289.c b/boards/arm/stm32/stm32f4discovery/src/stm32_ssd1289.c deleted file mode 100644 index 9f51dc3545f9f..0000000000000 --- a/boards/arm/stm32/stm32f4discovery/src/stm32_ssd1289.c +++ /dev/null @@ -1,390 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f4discovery/src/stm32_ssd1289.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include - -#include - -#include "arm_internal.h" -#include "stm32.h" -#include "stm32f4discovery.h" - -#ifdef CONFIG_LCD_SSD1289 - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -#ifndef CONFIG_STM32_FSMC -# error "CONFIG_STM32_FSMC is required to use the LCD" -#endif - -/* STM32F4Discovery LCD Hardware Definitions ********************************/ - -/* LCD /CS is CE1 == NOR/SRAM Bank 1 - * - * Bank 1 = 0x60000000 | 0x00000000 - * Bank 2 = 0x60000000 | 0x04000000 - * Bank 3 = 0x60000000 | 0x08000000 - * Bank 4 = 0x60000000 | 0x0c000000 - * - * FSMC address bit 16 is used to distinguish command and data. - * FSMC address bits 0-24 correspond to ARM address bits 1-25. - */ - -#define STM32_LCDBASE ((uintptr_t)(0x60000000 | 0x00000000)) -#define LCD_INDEX (STM32_LCDBASE) -#define LCD_DATA (STM32_LCDBASE + 0x00020000) - -/* SRAM pin definitions */ - -#define LCD_NADDRLINES 1 /* A16 */ -#define LCD_NDATALINES 16 /* D0-15 */ - -/**************************************************************************** - * Private Function Protototypes - ****************************************************************************/ - -/* Low Level LCD access */ - -static void stm32_select(struct ssd1289_lcd_s *dev); -static void stm32_deselect(struct ssd1289_lcd_s *dev); -static void stm32_index(struct ssd1289_lcd_s *dev, uint8_t index); -#ifndef CONFIG_SSD1289_WRONLY -static uint16_t stm32_read(struct ssd1289_lcd_s *dev); -#endif -static void stm32_write(struct ssd1289_lcd_s *dev, uint16_t data); -static void stm32_backlight(struct ssd1289_lcd_s *dev, int power); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* LCD pin mapping - * MAPPING TO STM32 F4: - * - * ---------------- ------------- ---------------------------------- - * STM32 FUNCTION LCD PIN STM32F4Discovery PIN - * ---------------- ------------- ---------------------------------- - * FSMC_D0 D0 pin 4 PD14 P1 pin 46 Conflict (Note 1) - * FSMC_D1 D1 pin 3 PD15 P1 pin 47 Conflict (Note 2) - * FSMC_D2 D2 pin 6 PD0 P2 pin 36 Free I/O - * FSMC_D3 D3 pin 5 PD1 P2 pin 33 Free I/O - * FSMC_D4 D4 pin 8 PE7 P1 pin 25 Free I/O - * FSMC_D5 D5 pin 7 PE8 P1 pin 26 Free I/O - * FSMC_D6 D6 pin 10 PE9 P1 pin 27 Free I/O - * FSMC_D7 D7 pin 9 PE10 P1 pin 28 Free I/O - * FSMC_D8 D8 pin 12 PE11 P1 pin 29 Free I/O - * FSMC_D9 D9 pin 11 PE12 P1 pin 30 Free I/O - * FSMC_D10 D10 pin 14 PE13 P1 pin 31 Free I/O - * FSMC_D11 D11 pin 13 PE14 P1 pin 32 Free I/O - * FSMC_D12 D12 pin 16 PE15 P1 pin 33 Free I/O - * FSMC_D13 D13 pin 15 PD8 P1 pin 40 Free I/O - * FSMC_D14 D14 pin 18 PD9 P1 pin 41 Free I/O - * FSMC_D15 D15 pin 17 PD10 P1 pin 42 Free I/O - * FSMC_A16 RS pin 19 PD11 P1 pin 27 Free I/O - * FSMC_NE1 ~CS pin 10 PD7 P2 pin 27 Free I/O - * FSMC_NWE ~WR pin 22 PD5 P2 pin 29 Conflict (Note 3) - * FSMC_NOE ~RD pin 21 PD4 P2 pin 32 Conflict (Note 4) - * PC6 RESET pin 24 PC6 P2 pin 47 Free I/O - * ---------------- ------------- ---------------------------------- - * - * 1 Used for the RED LED - * 2 Used for the BLUE LED - * 3 Used for the RED LED and for OTG FS Overcurrent. It may be okay to - * use for the parallel interface if PC0 is held high (or floating). - * PC0 enables the STMPS2141STR IC power switch that drives the OTG FS - * host VBUS. - * 4 Also the reset pin for the CS43L22 audio Codec. - */ - -#define GPIO_LCD_RESET (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz|\ - GPIO_OUTPUT_SET|GPIO_PORTC|GPIO_PIN6) - -/* GPIO configurations unique to the LCD */ - -static const uint32_t g_lcdconfig[] = -{ - /* PC6(RESET), FSMC_A16, FSMC_NOE, FSMC_NWE, and FSMC_NE1 */ - - GPIO_LCD_RESET, GPIO_FSMC_A16, GPIO_FSMC_NOE, GPIO_FSMC_NWE, GPIO_FSMC_NE1 -}; -#define NLCD_CONFIG (sizeof(g_lcdconfig)/sizeof(uint32_t)) - -/* This is the driver state structure - * (there is no retained state information) - */ - -static struct ssd1289_lcd_s g_ssd1289 = -{ - .select = stm32_select, - .deselect = stm32_deselect, - .index = stm32_index, -#ifndef CONFIG_SSD1289_WRONLY - .read = stm32_read, -#endif - .write = stm32_write, - .backlight = stm32_backlight -}; - -/* The saved instance of the LCD driver */ - -static struct lcd_dev_s *g_ssd1289drvr; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_select - * - * Description: - * Select the LCD device - * - ****************************************************************************/ - -static void stm32_select(struct ssd1289_lcd_s *dev) -{ - /* Does not apply to this hardware */ -} - -/**************************************************************************** - * Name: stm32_deselect - * - * Description: - * De-select the LCD device - * - ****************************************************************************/ - -static void stm32_deselect(struct ssd1289_lcd_s *dev) -{ - /* Does not apply to this hardware */ -} - -/**************************************************************************** - * Name: stm32_deselect - * - * Description: - * Set the index register - * - ****************************************************************************/ - -static void stm32_index(struct ssd1289_lcd_s *dev, uint8_t index) -{ - putreg16((uint16_t)index, LCD_INDEX); -} - -/**************************************************************************** - * Name: stm32_read - * - * Description: - * Read LCD data (GRAM data or register contents) - * - ****************************************************************************/ - -#ifndef CONFIG_SSD1289_WRONLY -static uint16_t stm32_read(struct ssd1289_lcd_s *dev) -{ - return getreg16(LCD_DATA); -} -#endif - -/**************************************************************************** - * Name: stm32_write - * - * Description: - * Write LCD data (GRAM data or register contents) - * - ****************************************************************************/ - -static void stm32_write(struct ssd1289_lcd_s *dev, uint16_t data) -{ - putreg16((uint16_t)data, LCD_DATA); -} - -/**************************************************************************** - * Name: stm32_write - * - * Description: - * Write LCD data (GRAM data or register contents) - * - ****************************************************************************/ - -static void stm32_backlight(struct ssd1289_lcd_s *dev, int power) -{ -#warning "Missing logic" -} - -/**************************************************************************** - * Name: stm32_selectlcd - * - * Description: - * Initialize to the LCD - * - ****************************************************************************/ - -void stm32_selectlcd(void) -{ - /* Configure GPIO pins */ - - stm32_extmemdata(LCD_NDATALINES); /* Common data lines: D0-D15 */ - stm32_extmemgpios(g_lcdconfig, NLCD_CONFIG); /* LCD-specific control lines */ - - /* Enable AHB clocking to the FSMC */ - - stm32_fsmc_enable(); - - /* Color LCD configuration (LCD configured as follow): - * - * - Data/Address MUX = Disable "FSMC_BCR_MUXEN" just not enable it. - * - Extended Mode = Disable "FSMC_BCR_EXTMOD" - * - Memory Type = SRAM "FSMC_BCR_SRAM" - * - Data Width = 16bit "FSMC_BCR_MWID16" - * - Write Operation = Enable "FSMC_BCR_WREN" - * - Asynchronous Wait = Disable - */ - - /* Bank1 NOR/SRAM control register configuration */ - - putreg32(FSMC_BCR_SRAM | FSMC_BCR_MWID16 | FSMC_BCR_WREN, STM32_FSMC_BCR1); - - /* Bank1 NOR/SRAM timing register configuration */ - - putreg32(FSMC_BTR_ADDSET(5) | FSMC_BTR_ADDHLD(1) | - FSMC_BTR_DATAST(9) | FSMC_BTR_BUSTURN(1) | - FSMC_BTR_CLKDIV(1) | FSMC_BTR_DATLAT(2) | - FSMC_BTR_ACCMODA, STM32_FSMC_BTR1); - - putreg32(0xffffffff, STM32_FSMC_BWTR1); - - /* Enable the bank by setting the MBKEN bit */ - - putreg32(FSMC_BCR_MBKEN | FSMC_BCR_SRAM | - FSMC_BCR_MWID16 | FSMC_BCR_WREN, STM32_FSMC_BCR1); -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_lcd_initialize - * - * Description: - * Initialize the LCD video hardware. The initial state of the LCD is fully - * initialized, display memory cleared, and the LCD ready to use, but with - * the power setting at 0 (full off). - * - ****************************************************************************/ - -int board_lcd_initialize(void) -{ - /* Only initialize the driver once */ - - if (!g_ssd1289drvr) - { - lcdinfo("Initializing\n"); - - /* Configure GPIO pins and configure the FSMC to support the LCD */ - - stm32_selectlcd(); - - /* Reset the LCD (active low) */ - - stm32_gpiowrite(GPIO_LCD_RESET, false); - up_mdelay(5); - stm32_gpiowrite(GPIO_LCD_RESET, true); - - /* Configure and enable the LCD */ - - up_mdelay(50); - g_ssd1289drvr = ssd1289_lcdinitialize(&g_ssd1289); - if (!g_ssd1289drvr) - { - lcderr("ERROR: ssd1289_lcdinitialize failed\n"); - return -ENODEV; - } - } - - /* Clear the display (setting it to the color 0=black) */ - -#if 0 /* Already done in the driver */ - ssd1289_clear(g_ssd1289drvr, 0); -#endif - - /* Turn the display off */ - - g_ssd1289drvr->setpower(g_ssd1289drvr, 0); - return OK; -} - -/**************************************************************************** - * Name: board_lcd_getdev - * - * Description: - * Return a a reference to the LCD object for the specified LCD. - * This allows support for multiple LCD devices. - * - ****************************************************************************/ - -struct lcd_dev_s *board_lcd_getdev(int lcddev) -{ - DEBUGASSERT(lcddev == 0); - return g_ssd1289drvr; -} - -/**************************************************************************** - * Name: board_lcd_uninitialize - * - * Description: - * Uninitialize the LCD support - * - ****************************************************************************/ - -void board_lcd_uninitialize(void) -{ - /* Turn the display off */ - - g_ssd1289drvr->setpower(g_ssd1289drvr, 0); -} - -#endif /* CONFIG_LCD_SSD1289 */ diff --git a/boards/arm/stm32/stm32f4discovery/src/stm32_ssd1351.c b/boards/arm/stm32/stm32f4discovery/src/stm32_ssd1351.c deleted file mode 100644 index 6fc6f5a3b9c59..0000000000000 --- a/boards/arm/stm32/stm32f4discovery/src/stm32_ssd1351.c +++ /dev/null @@ -1,118 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f4discovery/src/stm32_ssd1351.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include -#include -#include -#include -#include - -#include "stm32_gpio.h" -#include "stm32_spi.h" - -#include "stm32f4discovery.h" - -#ifdef CONFIG_LCD_SSD1351 - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -/* The pin configurations here require that SPI1 is selected */ - -#ifndef CONFIG_STM32_SPI1 -# error "The OLED driver requires CONFIG_STM32_SPI1 in the configuration" -#endif - -#ifndef CONFIG_SSD1351_SPI4WIRE -# error "The configuration requires the SPI 4-wire interface" -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_graphics_setup - * - * Description: - * Called by NX initialization logic to configure the OLED. - * - ****************************************************************************/ - -struct lcd_dev_s *board_graphics_setup(unsigned int devno) -{ - struct spi_dev_s *spi; - struct lcd_dev_s *dev; - - /* Configure the OLED GPIOs. This initial configuration is RESET low, - * putting the OLED into reset state. - */ - - stm32_configgpio(GPIO_OLED_RESET); - - /* Wait a bit then release the OLED from the reset state */ - - up_mdelay(20); - stm32_gpiowrite(GPIO_OLED_RESET, true); - - /* Get the SPI1 port interface */ - - spi = stm32_spibus_initialize(1); - if (spi == NULL) - { - lcderr("ERROR: Failed to initialize SPI port 1\n"); - } - else - { - /* Bind the SPI port to the OLED */ - - dev = ssd1351_initialize(spi, devno); - if (dev == NULL) - { - lcderr("ERROR: Failed to bind SPI port 1 to OLED %d\n", devno); - } - else - { - lcdinfo("Bound SPI port 1 to OLED %d\n", devno); - - /* And turn the OLED on */ - - dev->setpower(dev, LCD_FULL_ON); - return dev; - } - } - - return NULL; -} - -#endif /* CONFIG_LCD_SSD1351 */ diff --git a/boards/arm/stm32/stm32f4discovery/src/stm32_sx127x.c b/boards/arm/stm32/stm32f4discovery/src/stm32_sx127x.c deleted file mode 100644 index 95dfed45d00d4..0000000000000 --- a/boards/arm/stm32/stm32f4discovery/src/stm32_sx127x.c +++ /dev/null @@ -1,203 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f4discovery/src/stm32_sx127x.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -#include "stm32_gpio.h" -#include "stm32_exti.h" -#include "stm32_spi.h" - -#include "stm32f4discovery.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* SX127X on SPI1 bus */ - -#define SX127X_SPI 1 - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -static void sx127x_chip_reset(void); -static int sx127x_opmode_change(int opmode); -static int sx127x_freq_select(uint32_t freq); -static int sx127x_pa_select(bool enable); -static int sx127x_irq0_attach(xcpt_t isr, void *arg); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -struct sx127x_lower_s lower = -{ - .irq0attach = sx127x_irq0_attach, - .reset = sx127x_chip_reset, - .opmode_change = sx127x_opmode_change, - .freq_select = sx127x_freq_select, - .pa_select = sx127x_pa_select, - .pa_force = false -}; - -static bool g_high_power_output = false; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: sx127x_irq0_attach - ****************************************************************************/ - -static int sx127x_irq0_attach(xcpt_t isr, void *arg) -{ - wlinfo("Attach DIO0 IRQ\n"); - - /* IRQ on rising edge */ - - stm32_gpiosetevent(GPIO_SX127X_DIO0, true, false, false, isr, arg); - return OK; -} - -/**************************************************************************** - * Name: sx127x_chip_reset - ****************************************************************************/ - -static void sx127x_chip_reset(void) -{ - wlinfo("SX127X RESET\n"); - - /* Configure reset as output */ - - stm32_configgpio(GPIO_SX127X_RESET); - - /* Set pin to zero */ - - stm32_gpiowrite(GPIO_SX127X_RESET, false); - - /* Wait 1 ms */ - - nxsched_usleep(1000); - - /* Configure reset as input */ - - stm32_configgpio(GPIO_SX127X_RESET | GPIO_INPUT | GPIO_FLOAT); - - /* Wait 10 ms */ - - nxsched_usleep(10000); -} - -/**************************************************************************** - * Name: sx127x_opmode_change - ****************************************************************************/ - -static int sx127x_opmode_change(int opmode) -{ - /* Nothing to do */ - - return OK; -} - -/**************************************************************************** - * Name: sx127x_freq_select - ****************************************************************************/ - -static int sx127x_freq_select(uint32_t freq) -{ - int ret = OK; - - /* Only HF supported (BAND3 - 860-930 MHz) */ - - if (freq < SX127X_HFBAND_THR) - { - ret = -EINVAL; - wlerr("LF band not supported\n"); - } - - return ret; -} - -/**************************************************************************** - * Name: sx127x_pa_select - ****************************************************************************/ - -static int sx127x_pa_select(bool enable) -{ - g_high_power_output = enable; - return OK; -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -int stm32_lpwaninitialize(void) -{ - struct spi_dev_s *spidev; - int ret = OK; - - wlinfo("Register the sx127x module\n"); - - /* Setup DIO0 */ - - stm32_configgpio(GPIO_SX127X_DIO0); - - /* Init SPI bus */ - - spidev = stm32_spibus_initialize(SX127X_SPI); - if (!spidev) - { - wlerr("ERROR: Failed to initialize SPI %d bus\n", SX127X_SPI); - ret = -ENODEV; - goto errout; - } - - /* Initialize SX127X */ - - ret = sx127x_register(spidev, &lower); - if (ret < 0) - { - wlerr("ERROR: Failed to register sx127x\n"); - goto errout; - } - -errout: - return ret; -} diff --git a/boards/arm/stm32/stm32f4discovery/src/stm32_timer.c b/boards/arm/stm32/stm32f4discovery/src/stm32_timer.c deleted file mode 100644 index e9f274bfbcaab..0000000000000 --- a/boards/arm/stm32/stm32f4discovery/src/stm32_timer.c +++ /dev/null @@ -1,67 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f4discovery/src/stm32_timer.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include - -#include - -#include "stm32_tim.h" -#include "stm32f4discovery.h" - -#ifdef CONFIG_TIMER - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_timer_driver_setup - * - * Description: - * Configure the timer driver. - * - * Input Parameters: - * devpath - The full path to the timer device. - * This should be of the form /dev/timer0 - * timer - The timer's number. - * - * Returned Value: - * Zero (OK) is returned on success; A negated errno value is returned - * to indicate the nature of any failure. - * - ****************************************************************************/ - -int stm32_timer_driver_setup(const char *devpath, int timer) -{ - return stm32_timer_initialize(devpath, timer); -} - -#endif diff --git a/boards/arm/stm32/stm32f4discovery/src/stm32_uid.c b/boards/arm/stm32/stm32f4discovery/src/stm32_uid.c deleted file mode 100644 index 32f51da6faaed..0000000000000 --- a/boards/arm/stm32/stm32f4discovery/src/stm32_uid.c +++ /dev/null @@ -1,68 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f4discovery/src/stm32_uid.c - * - * SPDX-License-Identifier: BSD-3-Clause - * SPDX-FileCopyrightText: 2015 Marawan Ragab. All rights reserved. - * SPDX-FileContributor: Marawan Ragab - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include "stm32_uid.h" - -#include - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -#if defined(CONFIG_BOARDCTL_UNIQUEID) -int board_uniqueid(uint8_t *uniqueid) -{ - if (uniqueid == NULL) - { - return -EINVAL; - } - - stm32_get_uniqueid(uniqueid); - return OK; -} -#endif diff --git a/boards/arm/stm32/stm32f4discovery/src/stm32_usb.c b/boards/arm/stm32/stm32f4discovery/src/stm32_usb.c deleted file mode 100644 index b8f70554c4899..0000000000000 --- a/boards/arm/stm32/stm32f4discovery/src/stm32_usb.c +++ /dev/null @@ -1,340 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f4discovery/src/stm32_usb.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -#include "arm_internal.h" -#include "stm32.h" -#include "stm32_otgfs.h" -#include "stm32f4discovery.h" - -#ifdef CONFIG_STM32_OTGFS - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#if defined(CONFIG_USBDEV) || defined(CONFIG_USBHOST) -# define HAVE_USB 1 -#else -# warning "CONFIG_STM32_OTGFS is enabled but neither CONFIG_USBDEV nor CONFIG_USBHOST" -# undef HAVE_USB -#endif - -#ifndef CONFIG_STM32F4DISCO_USBHOST_PRIO -# define CONFIG_STM32F4DISCO_USBHOST_PRIO 100 -#endif - -#ifndef CONFIG_STM32F4DISCO_USBHOST_STACKSIZE -# define CONFIG_STM32F4DISCO_USBHOST_STACKSIZE 1024 -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -#ifdef CONFIG_USBHOST -static struct usbhost_connection_s *g_usbconn; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: usbhost_waiter - * - * Description: - * Wait for USB devices to be connected. - * - ****************************************************************************/ - -#ifdef CONFIG_USBHOST -static int usbhost_waiter(int argc, char *argv[]) -{ - struct usbhost_hubport_s *hport; - - uinfo("Running\n"); - for (; ; ) - { - /* Wait for the device to change state */ - - DEBUGVERIFY(CONN_WAIT(g_usbconn, &hport)); - uinfo("%s\n", hport->connected ? "connected" : "disconnected"); - - /* Did we just become connected? */ - - if (hport->connected) - { - /* Yes.. enumerate the newly connected device */ - - CONN_ENUMERATE(g_usbconn, hport); - } - } - - /* Keep the compiler from complaining */ - - return 0; -} -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_usbinitialize - * - * Description: - * Called from stm32_usbinitialize very early in initialization to setup - * USB-related GPIO pins for the STM32F4Discovery board. - * - ****************************************************************************/ - -void stm32_usbinitialize(void) -{ - /* The OTG FS has an internal soft pull-up. - * No GPIO configuration is required - */ - - /* Configure the OTG FS VBUS sensing GPIO, - * Power On, and Overcurrent GPIOs - */ - -#ifdef CONFIG_STM32_OTGFS - stm32_configgpio(GPIO_OTGFS_VBUS); - stm32_configgpio(GPIO_OTGFS_PWRON); - stm32_configgpio(GPIO_OTGFS_OVER); -#endif -} - -/**************************************************************************** - * Name: stm32_usbhost_initialize - * - * Description: - * Called at application startup time to initialize the USB host - * functionality. - * This function will start a thread that will monitor for device - * connection/disconnection events. - * - ****************************************************************************/ - -#ifdef CONFIG_USBHOST -int stm32_usbhost_initialize(void) -{ - int ret; - - /* First, register all of the class drivers needed to support the drivers - * that we care about: - */ - - uinfo("Register class drivers\n"); - -#ifdef CONFIG_USBHOST_HUB - /* Initialize USB hub class support */ - - ret = usbhost_hub_initialize(); - if (ret < 0) - { - uerr("ERROR: usbhost_hub_initialize failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_USBHOST_MSC - /* Register the USB mass storage class class */ - - ret = usbhost_msc_initialize(); - if (ret != OK) - { - uerr("ERROR: Failed to register the mass storage class: %d\n", ret); - } -#endif - -#ifdef CONFIG_USBHOST_CDCACM - /* Register the CDC/ACM serial class */ - - ret = usbhost_cdcacm_initialize(); - if (ret != OK) - { - uerr("ERROR: Failed to register the CDC/ACM serial class: %d\n", ret); - } -#endif - -#ifdef CONFIG_USBHOST_HIDKBD - /* Initialize the HID keyboard class */ - - ret = usbhost_kbdinit(); - if (ret != OK) - { - uerr("ERROR: Failed to register the HID keyboard class\n"); - } -#endif - -#ifdef CONFIG_USBHOST_HIDMOUSE - /* Initialize the HID mouse class */ - - ret = usbhost_mouse_init(); - if (ret != OK) - { - uerr("ERROR: Failed to register the HID mouse class\n"); - } -#endif - -#ifdef CONFIG_USBHOST_XBOXCONTROLLER - /* Initialize the HID mouse class */ - - ret = usbhost_xboxcontroller_init(); - if (ret != OK) - { - uerr("ERROR: Failed to register the XBox Controller class\n"); - } -#endif - - /* Then get an instance of the USB host interface */ - - uinfo("Initialize USB host\n"); - g_usbconn = stm32_otgfshost_initialize(0); - if (g_usbconn) - { - /* Start a thread to handle device connection. */ - - uinfo("Start usbhost_waiter\n"); - - ret = kthread_create("usbhost", CONFIG_STM32F4DISCO_USBHOST_PRIO, - CONFIG_STM32F4DISCO_USBHOST_STACKSIZE, - usbhost_waiter, NULL); - return ret < 0 ? -ENOEXEC : OK; - } - - return -ENODEV; -} -#endif - -/**************************************************************************** - * Name: stm32_usbhost_vbusdrive - * - * Description: - * Enable/disable driving of VBUS 5V output. This function must be - * provided be each platform that implements the STM32 OTG FS host - * interface - * - * "On-chip 5 V VBUS generation is not supported. For this reason, a - * charge pump or, if 5 V are available on the application board, a - * basic power switch, must be added externally to drive the 5 V VBUS - * line. The external charge pump can be driven by any GPIO output. - * When the application decides to power on VBUS using the chosen GPIO, - * it must also set the port power bit in the host port control and - * status register (PPWR bit in OTG_FS_HPRT). - * - * "The application uses this field to control power to this port, - * and the core clears this bit on an overcurrent condition." - * - * Input Parameters: - * iface - For future growth to handle multiple USB host interface. - * Should be zero. - * enable - true: enable VBUS power; false: disable VBUS power - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef CONFIG_USBHOST -void stm32_usbhost_vbusdrive(int iface, bool enable) -{ - DEBUGASSERT(iface == 0); - - if (enable) - { - /* Enable the Power Switch by driving the enable pin low */ - - stm32_gpiowrite(GPIO_OTGFS_PWRON, false); - } - else - { - /* Disable the Power Switch by driving the enable pin high */ - - stm32_gpiowrite(GPIO_OTGFS_PWRON, true); - } -} -#endif - -/**************************************************************************** - * Name: stm32_setup_overcurrent - * - * Description: - * Setup to receive an interrupt-level callback if an overcurrent - * condition is detected. - * - * Input Parameters: - * handler - New overcurrent interrupt handler - * arg - The argument provided for the interrupt handler - * - * Returned Value: - * Zero (OK) is returned on success. Otherwise, a negated errno value - * is returned to indicate the nature of the failure. - * - ****************************************************************************/ - -#ifdef CONFIG_USBHOST -int stm32_setup_overcurrent(xcpt_t handler, void *arg) -{ - return stm32_gpiosetevent(GPIO_OTGFS_OVER, true, true, true, handler, arg); -} -#endif - -/**************************************************************************** - * Name: stm32_usbsuspend - * - * Description: - * Board logic must provide the stm32_usbsuspend logic if the USBDEV - * driver is used. This function is called whenever the USB enters or - * leaves suspend mode. This is an opportunity for the board logic to - * shutdown clocks, power, etc. while the USB is suspended. - * - ****************************************************************************/ - -#ifdef CONFIG_USBDEV -void stm32_usbsuspend(struct usbdev_s *dev, bool resume) -{ - uinfo("resume: %d\n", resume); -} -#endif - -#endif /* CONFIG_STM32_OTGFS */ diff --git a/boards/arm/stm32/stm32f4discovery/src/stm32_usbmsc.c b/boards/arm/stm32/stm32f4discovery/src/stm32_usbmsc.c deleted file mode 100644 index d4afdc4e95ebf..0000000000000 --- a/boards/arm/stm32/stm32f4discovery/src/stm32_usbmsc.c +++ /dev/null @@ -1,71 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f4discovery/src/stm32_usbmsc.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include - -#include "stm32.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -#ifndef CONFIG_SYSTEM_USBMSC_DEVMINOR1 -# define CONFIG_SYSTEM_USBMSC_DEVMINOR1 0 -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_usbmsc_initialize - * - * Description: - * Perform architecture specific initialization of the USB MSC device. - * - ****************************************************************************/ - -int board_usbmsc_initialize(int port) -{ - /* If system/usbmsc is built as an NSH command, then SD slot should - * already have been initialized. - * In this case, there is nothing further to be done here. - */ - -#ifndef CONFIG_NSH_BUILTIN_APPS - return stm32_mmcsd_initialize(2, CONFIG_SYSTEM_USBMSC_DEVMINOR1); -#else - return OK; -#endif -} diff --git a/boards/arm/stm32/stm32f4discovery/src/stm32_userleds.c b/boards/arm/stm32/stm32f4discovery/src/stm32_userleds.c deleted file mode 100644 index c2fc1756428d4..0000000000000 --- a/boards/arm/stm32/stm32f4discovery/src/stm32_userleds.c +++ /dev/null @@ -1,216 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f4discovery/src/stm32_userleds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32.h" -#include "stm32f4discovery.h" - -#ifndef CONFIG_ARCH_LEDS - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* This array maps an LED number to GPIO pin configuration */ - -static uint32_t g_ledcfg[BOARD_NLEDS] = -{ - GPIO_LED1, GPIO_LED2, GPIO_LED3, GPIO_LED4 -}; - -/**************************************************************************** - * Private Function Protototypes - ****************************************************************************/ - -/* LED Power Management */ - -#ifdef CONFIG_PM -static void led_pm_notify(struct pm_callback_s *cb, int domain, - enum pm_state_e pmstate); -static int led_pm_prepare(struct pm_callback_s *cb, int domain, - enum pm_state_e pmstate); -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -#ifdef CONFIG_PM -static struct pm_callback_s g_ledscb = -{ - .notify = led_pm_notify, - .prepare = led_pm_prepare, -}; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: led_pm_notify - * - * Description: - * Notify the driver of new power state. This callback is called after - * all drivers have had the opportunity to prepare for the new power state. - * - ****************************************************************************/ - -#ifdef CONFIG_PM -static void led_pm_notify(struct pm_callback_s *cb, int domain, - enum pm_state_e pmstate) -{ - switch (pmstate) - { - case PM_NORMAL: - { - /* Restore normal LEDs operation */ - } - break; - - case PM_IDLE: - { - /* Entering IDLE mode - Turn leds off */ - } - break; - - case PM_STANDBY: - { - /* Entering STANDBY mode - Logic for PM_STANDBY goes here */ - } - break; - - case PM_SLEEP: - { - /* Entering SLEEP mode - Logic for PM_SLEEP goes here */ - } - break; - - default: - { - /* Should not get here */ - } - break; - } -} -#endif - -/**************************************************************************** - * Name: led_pm_prepare - * - * Description: - * Request the driver to prepare for a new power state. This is a warning - * that the system is about to enter into a new power state. The driver - * should begin whatever operations that may be required to enter power - * state. The driver may abort the state change mode by returning a - * non-zero value from the callback function. - * - ****************************************************************************/ - -#ifdef CONFIG_PM -static int led_pm_prepare(struct pm_callback_s *cb, int domain, - enum pm_state_e pmstate) -{ - /* No preparation to change power modes is required by the LEDs driver. - * We always accept the state change by returning OK. - */ - - return OK; -} -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_userled_initialize - ****************************************************************************/ - -uint32_t board_userled_initialize(void) -{ - /* Configure LED1-4 GPIOs for output */ - - stm32_configgpio(GPIO_LED1); - stm32_configgpio(GPIO_LED2); - stm32_configgpio(GPIO_LED3); - stm32_configgpio(GPIO_LED4); - return BOARD_NLEDS; -} - -/**************************************************************************** - * Name: board_userled - ****************************************************************************/ - -void board_userled(int led, bool ledon) -{ - if ((unsigned)led < BOARD_NLEDS) - { - stm32_gpiowrite(g_ledcfg[led], ledon); - } -} - -/**************************************************************************** - * Name: board_userled_all - ****************************************************************************/ - -void board_userled_all(uint32_t ledset) -{ - stm32_gpiowrite(GPIO_LED1, (ledset & BOARD_LED1_BIT) == 0); - stm32_gpiowrite(GPIO_LED2, (ledset & BOARD_LED2_BIT) == 0); - stm32_gpiowrite(GPIO_LED3, (ledset & BOARD_LED3_BIT) == 0); - stm32_gpiowrite(GPIO_LED4, (ledset & BOARD_LED4_BIT) == 0); -} - -/**************************************************************************** - * Name: stm32_led_pminitialize - ****************************************************************************/ - -#ifdef CONFIG_PM -void stm32_led_pminitialize(void) -{ - /* Register to receive power management callbacks */ - - int ret = pm_register(&g_ledscb); - if (ret != OK) - { - board_autoled_on(LED_ASSERTION); - } -} -#endif /* CONFIG_PM */ - -#endif /* !CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/stm32ldiscovery/CMakeLists.txt b/boards/arm/stm32/stm32ldiscovery/CMakeLists.txt deleted file mode 100644 index bde3559ad0c87..0000000000000 --- a/boards/arm/stm32/stm32ldiscovery/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/stm32ldiscovery/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32/stm32ldiscovery/configs/chrono/defconfig b/boards/arm/stm32/stm32ldiscovery/configs/chrono/defconfig deleted file mode 100644 index 0167eac8ad0e2..0000000000000 --- a/boards/arm/stm32/stm32ldiscovery/configs/chrono/defconfig +++ /dev/null @@ -1,64 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_NSH_DISABLEBG is not set -# CONFIG_NSH_DISABLE_EXEC is not set -# CONFIG_NSH_DISABLE_EXIT is not set -# CONFIG_NSH_DISABLE_HEXDUMP is not set -# CONFIG_NSH_DISABLE_PS is not set -# CONFIG_NSH_DISABLE_XD is not set -# CONFIG_SERIAL is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32ldiscovery" -CONFIG_ARCH_BOARD_STM32L_DISCOVERY=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32L152RB=y -CONFIG_ARCH_IRQBUTTONS=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=2796 -CONFIG_BUILTIN=y -CONFIG_DEFAULT_SMALL=y -CONFIG_DISABLE_MOUNTPOINT=y -CONFIG_ENABLE_ALL_SIGNALS=y -CONFIG_EXAMPLES_CHRONO=y -CONFIG_EXAMPLES_SLCD=y -CONFIG_FILE_STREAM=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INIT_STACKSIZE=1536 -CONFIG_INPUT=y -CONFIG_INPUT_BUTTONS=y -CONFIG_INPUT_BUTTONS_LOWER=y -CONFIG_INTELHEX_BINARY=y -CONFIG_LCD=y -CONFIG_LIBC_SLCDCODEC=y -CONFIG_LWL_CONSOLE=y -CONFIG_MM_SMALL=y -CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=64 -CONFIG_NUNGET_CHARS=0 -CONFIG_POSIX_SPAWN_DEFAULT_STACKSIZE=1536 -CONFIG_PTHREAD_STACK_DEFAULT=1536 -CONFIG_RAM_SIZE=16384 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_RTC_DATETIME=y -CONFIG_SCHED_WAITPID=y -CONFIG_SLCD=y -CONFIG_START_DAY=19 -CONFIG_START_MONTH=5 -CONFIG_START_YEAR=2013 -CONFIG_STDIO_DISABLE_BUFFERING=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_LCD=y -CONFIG_STM32_PWR=y -CONFIG_STM32_RTC=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 diff --git a/boards/arm/stm32/stm32ldiscovery/configs/nsh/defconfig b/boards/arm/stm32/stm32ldiscovery/configs/nsh/defconfig deleted file mode 100644 index f6f307ffc1e2a..0000000000000 --- a/boards/arm/stm32/stm32ldiscovery/configs/nsh/defconfig +++ /dev/null @@ -1,50 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_NSH_DISABLEBG is not set -# CONFIG_NSH_DISABLE_EXEC is not set -# CONFIG_NSH_DISABLE_EXIT is not set -# CONFIG_NSH_DISABLE_HEXDUMP is not set -# CONFIG_NSH_DISABLE_PS is not set -# CONFIG_NSH_DISABLE_XD is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32ldiscovery" -CONFIG_ARCH_BOARD_STM32L_DISCOVERY=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32L152RB=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=2796 -CONFIG_DEFAULT_SMALL=y -CONFIG_DISABLE_MOUNTPOINT=y -CONFIG_HOST_WINDOWS=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INIT_STACKSIZE=1536 -CONFIG_INTELHEX_BINARY=y -CONFIG_MM_SMALL=y -CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 -CONFIG_NSH_FILEIOSIZE=64 -CONFIG_NUNGET_CHARS=0 -CONFIG_POSIX_SPAWN_DEFAULT_STACKSIZE=1536 -CONFIG_PTHREAD_STACK_DEFAULT=1536 -CONFIG_RAM_SIZE=16384 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=19 -CONFIG_START_MONTH=5 -CONFIG_START_YEAR=2013 -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_PWR=y -CONFIG_STM32_USART1=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART1_BAUD=57600 -CONFIG_USART1_RXBUFSIZE=64 -CONFIG_USART1_SERIAL_CONSOLE=y -CONFIG_USART1_TXBUFSIZE=64 diff --git a/boards/arm/stm32/stm32ldiscovery/include/board.h b/boards/arm/stm32/stm32ldiscovery/include/board.h deleted file mode 100644 index a36765cc66e2a..0000000000000 --- a/boards/arm/stm32/stm32ldiscovery/include/board.h +++ /dev/null @@ -1,307 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32ldiscovery/include/board.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __BOARDS_ARM_STM32_STM32LDISCOVERY_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32_STM32LDISCOVERY_INCLUDE_BOARD_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#ifndef __ASSEMBLY__ -# include -#endif - -#include - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Clocking *****************************************************************/ - -/* Four different clock sources can be used to drive the system clock - * (SYSCLK): - * - * - HSI high-speed internal oscillator clock - * Generated from an internal 16 MHz RC oscillator - * - HSE high-speed external oscillator clock - * Normally driven by an external crystal (X3). However, this crystal is - * not fitted on the STM32L-Discovery board. - * - PLL clock - * - MSI multispeed internal oscillator clock - * The MSI clock signal is generated from an internal RC oscillator. - * Seven frequency ranges are available: 65.536 kHz, 131.072 kHz, - * 262.144 kHz, 524.288 kHz, 1.048 MHz, 2.097 MHz (default value) and - * 4.194 MHz. - * - * The devices have the following two secondary clock sources - * - LSI low-speed internal RC clock - * Drives the watchdog and RTC. Approximately 37KHz - * - LSE low-speed external oscillator clock - * Driven by 32.768KHz crystal (X2) on the OSC32_IN and OSC32_OUT pins. - */ - -#define STM32_BOARD_XTAL 8000000ul /* X3 on board (not fitted)*/ - -#define STM32_HSI_FREQUENCY 16000000ul /* Approximately 16MHz */ -#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL -#define STM32_MSI_FREQUENCY 2097000 /* Default is approximately 2.097Mhz */ -#define STM32_LSI_FREQUENCY 37000 /* Approximately 37KHz */ -#define STM32_LSE_FREQUENCY 32768 /* X2 on board */ - -/* PLL Configuration - * - * - PLL source is HSI -> 16MHz input (nominal) - * - PLL multiplier is 6 -> 96MHz PLL VCO clock output (for USB) - * - PLL output divider 3 -> 32MHz divided down PLL VCO clock output - * - * Resulting SYSCLK frequency is 16MHz x 6 / 3 = 32MHz - * - * USB/SDIO: - * If the USB or SDIO interface is used in the application, the PLL VCO - * clock (defined by STM32_CFGR_PLLMUL) must be programmed to output a 96 - * MHz frequency. This is required to provide a 48 MHz clock to the USB or - * SDIO (SDIOCLK or USBCLK = PLLVCO/2). - * SYSCLK - * The system clock is derived from the PLL VCO divided by the output - * division factor. - * Limitations: - * 96 MHz as PLLVCO when the product is in range 1 (1.8V), - * 48 MHz as PLLVCO when the product is in range 2 (1.5V), - * 24 MHz when the product is in range 3 (1.2V). - * Output division to avoid exceeding 32 MHz as SYSCLK. - * The minimum input clock frequency for PLL is 2 MHz (when using HSE as - * PLL source). - */ - -#define STM32_CFGR_PLLSRC 0 /* Source is 16MHz HSI */ -#ifdef CONFIG_STM32_USB -# define STM32_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx6 /* PLLMUL = 6 */ -# define STM32_CFGR_PLLDIV RCC_CFGR_PLLDIV_3 /* PLLDIV = 3 */ -# define STM32_PLL_FREQUENCY (6*STM32_HSI_FREQUENCY) /* PLL VCO Frequency is 96MHz */ -#else -# define STM32_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx4 /* PLLMUL = 4 */ -# define STM32_CFGR_PLLDIV RCC_CFGR_PLLDIV_2 /* PLLDIV = 2 */ -# define STM32_PLL_FREQUENCY (4*STM32_HSI_FREQUENCY) /* PLL VCO Frequency is 64MHz */ -#endif - -/* Use the PLL and set the SYSCLK source to be the divided down PLL VCO - * output frequency (STM32_PLL_FREQUENCY divided by the PLLDIV value). - */ - -#define STM32_SYSCLK_SW RCC_CFGR_SW_PLL /* Use the PLL as the SYSCLK */ -#define STM32_SYSCLK_SWS RCC_CFGR_SWS_PLL -#ifdef CONFIG_STM32_USB -# define STM32_SYSCLK_FREQUENCY (STM32_PLL_FREQUENCY/3) /* SYSCLK frequency is 96MHz/PLLDIV = 32MHz */ -#else -# define STM32_SYSCLK_FREQUENCY (STM32_PLL_FREQUENCY/2) /* SYSCLK frequency is 64MHz/PLLDIV = 32MHz */ -#endif - -/* AHB clock (HCLK) is SYSCLK (32MHz) */ - -#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK -#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY - -/* APB2 clock (PCLK2) is HCLK (32MHz) */ - -#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK -#define STM32_PCLK2_FREQUENCY STM32_HCLK_FREQUENCY -#define STM32_APB2_CLKIN (STM32_PCLK2_FREQUENCY) - -/* APB2 timers 9, 10, and 11 will receive PCLK2. */ - -#define STM32_APB2_TIM9_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM10_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM11_CLKIN (STM32_PCLK2_FREQUENCY) - -/* APB1 clock (PCLK1) is HCLK (32MHz) */ - -#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK -#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY) - -/* APB1 timers 2-7 will receive PCLK1 */ - -#define STM32_APB1_TIM2_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM4_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM5_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (STM32_PCLK1_FREQUENCY) - -/* LED definitions **********************************************************/ - -/* The STM32L-Discovery board has four LEDs. Two of these are controlled by - * logic on the board and are not available for software control: - * - * LD1 COM: LD2 default status is red. LD2 turns to green to indicate - * that communications are in progress between the PC and the - * ST-LINK/V2. - * LD2 PWR: Red LED indicates that the board is powered. - * - * And two LEDs can be controlled by software: - * - * User LD3: Green LED is a user LED connected to the I/O PB7 of the - * STM32L152 MCU. - * User LD4: Blue LED is a user LED connected to the I/O PB6 of the - * STM32L152 MCU. - * - * If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs in - * any way. The following definitions are used to access individual LEDs. - */ - -/* LED index values for use with board_userled() */ - -#define BOARD_LED1 0 /* User LD3 */ -#define BOARD_LED2 1 /* User LD4 */ -#define BOARD_NLEDS 2 - -/* LED bits for use with board_userled_all() */ - -#define BOARD_LED1_BIT (1 << BOARD_LED1) -#define BOARD_LED2_BIT (1 << BOARD_LED2) - -/* If CONFIG_ARCH_LEDS is defined, then NuttX will control the 2 LEDs on - * board the STM32L-Discovery. The following definitions describe how NuttX - * controls the LEDs: - * - * SYMBOL Meaning LED state - * LED1 LED2 - * ------------------- ----------------------- -------- -------- - * LED_STARTED NuttX has been started OFF OFF - * LED_HEAPALLOCATE Heap has been allocated OFF OFF - * LED_IRQSENABLED Interrupts enabled OFF OFF - * LED_STACKCREATED Idle stack created ON OFF - * LED_INIRQ In an interrupt No change - * LED_SIGNAL In a signal handler No change - * LED_ASSERTION An assertion failed No change - * LED_PANIC The system has crashed OFF Blinking - * LED_IDLE STM32 is in sleep mode Not used - */ - -#define LED_STARTED 0 -#define LED_HEAPALLOCATE 0 -#define LED_IRQSENABLED 0 -#define LED_STACKCREATED 1 -#define LED_INIRQ 2 -#define LED_SIGNAL 2 -#define LED_ASSERTION 2 -#define LED_PANIC 3 - -/* Button definitions *******************************************************/ - -/* The STM32L-Discovery supports two buttons; only one button is controllable - * by software: - * - * B1 USER: user and wake-up button connected to the I/O PA0 of the - * STM32L152. - * B2 RESET: pushbutton connected to NRST is used to RESET the STM32L152. - */ - -#define BUTTON_USER 0 -#define NUM_BUTTONS 1 - -#define BUTTON_USER_BIT (1 << BUTTON_USER) - -/* Alternate Pin Functions **************************************************/ - -/* The STM32L-Discovery has no on-board RS-232 driver. Further, there - * are no USART pins that do not conflict with the on board resources, in - * particular, the LCD. Most USART pins are available if the LCD is enabled; - * USART2 may be used if either the LCD or the on-board LEDs are disabled. - * - * PA9 USART1_TX LCD glass COM1 P2, pin 22 - * PA10 USART1_RX LCD glass COM2 P2, pin 21 - * PB6 USART1_TX LED Blue P2, pin 8 - * PB7 USART1_RX LED Green P2, pin 7 - * - * PA2 USART2_TX LCD SEG1 P1, pin 17 - * PA3 USART2_RX LCD SEG2 P1, pin 18 - * - * PB10 USART3_TX LCD SEG6 P1, pin 22 - * PB11 USART3_RX LCD SEG7 P1, pin 23 - * PC10 USART3_TX LCD SEG22 P2, pin 15 - * PC11 USART3_RX LCD SEG23 P2, pin 14 - */ - -#if !defined(CONFIG_STM32_LCD) -/* Select PA9 and PA10 if the LCD is not enabled */ - -# define GPIO_USART1_RX (GPIO_USART1_RX_1|GPIO_SPEED_40MHz) /* PA10 */ -# define GPIO_USART1_TX (GPIO_USART1_TX_1|GPIO_SPEED_40MHz) /* PA9 */ - -/* This there are no other options for USART1 on this part */ - -# define GPIO_USART2_RX (GPIO_USART2_RX_1|GPIO_SPEED_40MHz) /* PA3 */ -# define GPIO_USART2_TX (GPIO_USART2_TX_1|GPIO_SPEED_40MHz) /* PA2 */ - -/* Arbitrarily select PB10 and PB11 */ - -# define GPIO_USART3_RX (GPIO_USART3_RX_1|GPIO_SPEED_40MHz) /* PB11 */ -# define GPIO_USART3_TX (GPIO_USART3_TX_1|GPIO_SPEED_40MHz) /* PB10 */ - -#elif !defined(CONFIG_ARCH_LEDS) - -/* Select PB6 and PB7 if the LEDs are not enabled */ - -# define GPIO_USART1_RX (GPIO_USART1_RX_2|GPIO_SPEED_40MHz) /* PB7 */ -# define GPIO_USART1_TX (GPIO_USART1_TX_2|GPIO_SPEED_40MHz) /* PB6 */ - -#endif - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -#ifndef __ASSEMBLY__ - -#undef EXTERN -#if defined(__cplusplus) -# define EXTERN extern "C" -extern "C" -{ -#else -# define EXTERN extern -#endif - -/**************************************************************************** - * Name: stm32_slcd_initialize - * - * Description: - * Initialize the STM32L-Discovery LCD hardware and register the character - * driver as /dev/slcd0. - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_LCD -int stm32_slcd_initialize(void); -#endif - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ -#endif /* __BOARDS_ARM_STM32_STM32LDISCOVERY_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32/stm32ldiscovery/scripts/Make.defs b/boards/arm/stm32/stm32ldiscovery/scripts/Make.defs deleted file mode 100644 index d9b35b396fa5c..0000000000000 --- a/boards/arm/stm32/stm32ldiscovery/scripts/Make.defs +++ /dev/null @@ -1,46 +0,0 @@ -############################################################################ -# boards/arm/stm32/stm32ldiscovery/scripts/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/.config -include $(TOPDIR)/tools/Config.mk -include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs - -ifeq ($(CONFIG_ARCH_CHIP_STM32L152RB),y) - LDSCRIPT = stm32l152rb.ld -else ifeq ($(CONFIG_ARCH_CHIP_STM32L152RC),y) - LDSCRIPT = stm32l152rc.ld -endif - -ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) - -ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 - -CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) -CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) -CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -AFLAGS := $(CFLAGS) -D__ASSEMBLY__ - -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections -LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32/stm32ldiscovery/src/CMakeLists.txt b/boards/arm/stm32/stm32ldiscovery/src/CMakeLists.txt deleted file mode 100644 index feae2b53ca12f..0000000000000 --- a/boards/arm/stm32/stm32ldiscovery/src/CMakeLists.txt +++ /dev/null @@ -1,51 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/stm32ldiscovery/src/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -set(SRCS stm32_boot.c stm32_bringup.c stm32_spi.c) - -if(CONFIG_ARCH_LEDS) - list(APPEND SRCS stm32_autoleds.c) -else() - list(APPEND SRCS stm32_userleds.c) -endif() - -if(CONFIG_ARCH_BUTTONS) - list(APPEND SRCS stm32_buttons.c) -endif() - -if(CONFIG_STM32_LCD) - list(APPEND SRCS stm32_lcd.c) -endif() - -if(CONFIG_PWM) - list(APPEND SRCS stm32_pwm.c) -endif() - -target_sources(board PRIVATE ${SRCS}) - -if(CONFIG_ARCH_CHIP_STM32L152RB) - set_property(GLOBAL PROPERTY LD_SCRIPT - "${NUTTX_BOARD_DIR}/scripts/stm32l152rb.ld") -else() - set_property(GLOBAL PROPERTY LD_SCRIPT - "${NUTTX_BOARD_DIR}/scripts/stm32l152rc.ld") -endif() diff --git a/boards/arm/stm32/stm32ldiscovery/src/Make.defs b/boards/arm/stm32/stm32ldiscovery/src/Make.defs deleted file mode 100644 index 0a07db0a932e5..0000000000000 --- a/boards/arm/stm32/stm32ldiscovery/src/Make.defs +++ /dev/null @@ -1,47 +0,0 @@ -############################################################################ -# boards/arm/stm32/stm32ldiscovery/src/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/Make.defs - -CSRCS = stm32_boot.c stm32_bringup.c stm32_spi.c - -ifeq ($(CONFIG_ARCH_LEDS),y) -CSRCS += stm32_autoleds.c -else -CSRCS += stm32_userleds.c -endif - -ifeq ($(CONFIG_ARCH_BUTTONS),y) -CSRCS += stm32_buttons.c -endif - -ifeq ($(CONFIG_STM32_LCD),y) -CSRCS += stm32_lcd.c -endif - -ifeq ($(CONFIG_PWM),y) -CSRCS += stm32_pwm.c -endif - -DEPPATH += --dep-path board -VPATH += :board -CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/stm32ldiscovery/src/stm32_autoleds.c b/boards/arm/stm32/stm32ldiscovery/src/stm32_autoleds.c deleted file mode 100644 index e251d0f2ead09..0000000000000 --- a/boards/arm/stm32/stm32ldiscovery/src/stm32_autoleds.c +++ /dev/null @@ -1,124 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32ldiscovery/src/stm32_autoleds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include "chip.h" -#include "stm32.h" -#include "stm32ldiscovery.h" - -#ifdef CONFIG_ARCH_LEDS - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* If CONFIG_ARCH_LEDS is defined, then NuttX will control the 2 LEDs on - * board the STM32L-Discovery. The following definitions describe how NuttX - * controls the LEDs: - * - * SYMBOL Meaning LED state - * LED1 LED2 - * ------------------- ----------------------- -------- -------- - * LED_STARTED NuttX has been started OFF OFF - * LED_HEAPALLOCATE Heap has been allocated OFF OFF - * LED_IRQSENABLED Interrupts enabled OFF OFF - * LED_STACKCREATED Idle stack created ON OFF - * LED_INIRQ In an interrupt No change - * LED_SIGNAL In a signal handler No change - * LED_ASSERTION An assertion failed No change - * LED_PANIC The system has crashed OFF Blinking - * LED_IDLE STM32 is in sleep mode Not used - */ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_autoled_initialize - ****************************************************************************/ - -void board_autoled_initialize(void) -{ - /* Configure LED1-2 GPIOs for output */ - - stm32_configgpio(GPIO_LED1); - stm32_configgpio(GPIO_LED2); -} - -/**************************************************************************** - * Name: board_autoled_on - ****************************************************************************/ - -void board_autoled_on(int led) -{ - bool led1on = false; - bool led2on = false; - - switch (led) - { - case 0: /* LED_STARTED, LED_HEAPALLOCATE, LED_IRQSENABLED */ - break; - - case 1: /* LED_STACKCREATED */ - led1on = true; - break; - - default: - case 2: /* LED_INIRQ, LED_SIGNAL, LED_ASSERTION */ - return; - - case 3: /* LED_PANIC */ - led2on = true; - break; - } - - stm32_gpiowrite(GPIO_LED1, led1on); - stm32_gpiowrite(GPIO_LED2, led2on); -} - -/**************************************************************************** - * Name: board_autoled_off - ****************************************************************************/ - -void board_autoled_off(int led) -{ - if (led != 2) - { - stm32_gpiowrite(GPIO_LED1, false); - stm32_gpiowrite(GPIO_LED2, false); - } -} - -#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/stm32ldiscovery/src/stm32_boot.c b/boards/arm/stm32/stm32ldiscovery/src/stm32_boot.c deleted file mode 100644 index 701fdbd303cc7..0000000000000 --- a/boards/arm/stm32/stm32ldiscovery/src/stm32_boot.c +++ /dev/null @@ -1,91 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32ldiscovery/src/stm32_boot.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include -#include - -#include "arm_internal.h" -#include "stm32ldiscovery.h" - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_boardinitialize - * - * Description: - * All STM32 architectures must provide the following entry point. - * This entry point is called early in the initialization -- after all - * memory has been configured and mapped but before any devices have been - * initialized. - * - ****************************************************************************/ - -void stm32_boardinitialize(void) -{ - /* Configure SPI chip selects if 1) SPI is not disabled, and 2) the weak - * function stm32_spidev_initialize() has been brought into the link. - */ - -#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || defined(CONFIG_STM32_SPI3) - if (stm32_spidev_initialize) - { - stm32_spidev_initialize(); - } -#endif - - /* Configure on-board LEDs if LED support has been selected. */ - -#ifdef CONFIG_ARCH_LEDS - board_autoled_initialize(); -#endif -} - -/**************************************************************************** - * Name: board_late_initialize - * - * Description: - * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional - * initialization call will be performed in the boot-up sequence to a - * function called board_late_initialize(). board_late_initialize() will - * be called immediately after up_initialize() is called and just before - * the initial application is started. This additional initialization - * phase may be used, for example, to initialize board-specific device - * drivers. - * - ****************************************************************************/ - -#ifdef CONFIG_BOARD_LATE_INITIALIZE -void board_late_initialize(void) -{ - stm32_bringup(); -} -#endif diff --git a/boards/arm/stm32/stm32ldiscovery/src/stm32_bringup.c b/boards/arm/stm32/stm32ldiscovery/src/stm32_bringup.c deleted file mode 100644 index be3ff1616ed44..0000000000000 --- a/boards/arm/stm32/stm32ldiscovery/src/stm32_bringup.c +++ /dev/null @@ -1,140 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32ldiscovery/src/stm32_bringup.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include -#include -#include - -#include - -#include "stm32ldiscovery.h" - -#ifdef CONFIG_SENSORS_QENCODER -# include "board_qencoder.h" -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_bringup - * - * Description: - * Perform architecture-specific initialization - * - * CONFIG_BOARD_LATE_INITIALIZE=y : - * Called from board_late_initialize(). - * - ****************************************************************************/ - -int stm32_bringup(void) -{ - int ret = OK; - -#ifdef CONFIG_FS_PROCFS - /* Mount the procfs file system */ - - ret = nx_mount(NULL, "/proc", "procfs", 0, NULL); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: Failed to mount procfs at /proc: %d\n", ret); - } -#endif - -#if defined(CONFIG_USERLED) && !defined(CONFIG_ARCH_LEDS) -#ifdef CONFIG_USERLED_LOWER - /* Register the LED driver */ - - ret = userled_lower_initialize("/dev/userleds"); - if (ret != OK) - { - syslog(LOG_ERR, "ERROR: userled_lower_initialize() failed: %d\n", ret); - } -#else - /* Enable USER LED support for some other purpose */ - - board_userled_initialize(); -#endif /* CONFIG_USERLED_LOWER */ -#endif /* CONFIG_USERLED && !CONFIG_ARCH_LEDS */ - -#ifdef CONFIG_INPUT_BUTTONS -#ifdef CONFIG_INPUT_BUTTONS_LOWER - /* Register the BUTTON driver */ - - ret = btn_lower_initialize("/dev/buttons"); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: btn_lower_initialize() failed: %d\n", ret); - } -#else - /* Enable BUTTON support for some other purpose */ - - board_button_initialize(); -#endif /* CONFIG_INPUT_BUTTONS_LOWER */ -#endif /* CONFIG_INPUT_BUTTONS */ - -#ifdef CONFIG_STM32_LCD - /* Initialize the SLCD and register the SLCD device as /dev/slcd0 */ - - ret = stm32_slcd_initialize(); - if (ret != OK) - { - syslog(LOG_ERR, "ERROR: stm32_slcd_initialize failed: %d\n", ret); - return ret; - } -#endif - -#ifdef CONFIG_PWM - /* Initialize PWM and register the PWM device. */ - - ret = stm32_pwm_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_pwm_setup() failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_SENSORS_QENCODER - /* Initialize and register the qencoder driver */ - - ret = board_qencoder_initialize(0, CONFIG_STM32LDISCO_QETIMER); - if (ret != OK) - { - syslog(LOG_ERR, - "ERROR: Failed to register the qencoder: %d\n", - ret); - } -#endif - - return ret; -} diff --git a/boards/arm/stm32/stm32ldiscovery/src/stm32_buttons.c b/boards/arm/stm32/stm32ldiscovery/src/stm32_buttons.c deleted file mode 100644 index 15071e1fe4083..0000000000000 --- a/boards/arm/stm32/stm32ldiscovery/src/stm32_buttons.c +++ /dev/null @@ -1,151 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32ldiscovery/src/stm32_buttons.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include -#include - -#include "stm32_gpio.h" -#include "stm32ldiscovery.h" - -#ifdef CONFIG_ARCH_BUTTONS - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* Pin configuration for each STM32F3Discovery button. This array is indexed - * by the BUTTON_* definitions in board.h - */ - -static const uint32_t g_buttons[NUM_BUTTONS] = -{ - GPIO_BTN_USER -}; - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_button_initialize - * - * Description: - * board_button_initialize() must be called to initialize button resources. - * After that, board_buttons() may be called to collect the current state - * of all buttons or board_button_irq() may be called to register button - * interrupt handlers. - * - ****************************************************************************/ - -uint32_t board_button_initialize(void) -{ - int i; - - /* Configure the GPIO pins as inputs. NOTE that EXTI interrupts are - * configured for all pins. - */ - - for (i = 0; i < NUM_BUTTONS; i++) - { - stm32_configgpio(g_buttons[i]); - } - - return NUM_BUTTONS; -} - -/**************************************************************************** - * Name: board_buttons - ****************************************************************************/ - -uint32_t board_buttons(void) -{ - uint32_t ret = 0; - int i; - - /* Check that state of each key */ - - for (i = 0; i < NUM_BUTTONS; i++) - { - /* A LOW value means that the key is pressed. */ - - bool released = stm32_gpioread(g_buttons[i]); - - /* Accumulate the set of depressed (not released) keys */ - - if (!released) - { - ret |= (1 << i); - } - } - - return ret; -} - -/**************************************************************************** - * Button support. - * - * Description: - * board_button_initialize() must be called to initialize button resources. - * After that, board_buttons() may be called to collect the current state - * of all buttons or board_button_irq() may be called to register button - * interrupt handlers. - * - * After board_button_initialize() has been called, board_buttons() may be - * called to collect the state of all buttons. board_buttons() returns an - * 32-bit bit set with each bit associated with a button. See the - * BUTTON_*_BIT definitions in board.h for the meaning of each bit. - * - * board_button_irq() may be called to register an interrupt handler that - * will be called when a button is depressed or released. The ID value is a - * button enumeration value that uniquely identifies a button resource. See - * the BUTTON_* definitions in board.h for the meaning of enumeration - * value. - * - ****************************************************************************/ - -#ifdef CONFIG_ARCH_IRQBUTTONS -int board_button_irq(int id, xcpt_t irqhandler, void *arg) -{ - int ret = -EINVAL; - - /* The following should be atomic */ - - if (id >= MIN_IRQBUTTON && id <= MAX_IRQBUTTON) - { - ret = stm32_gpiosetevent(g_buttons[id], true, true, true, - irqhandler, arg); - } - - return ret; -} -#endif -#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/stm32/stm32ldiscovery/src/stm32_lcd.c b/boards/arm/stm32/stm32ldiscovery/src/stm32_lcd.c deleted file mode 100644 index ff4119682da8f..0000000000000 --- a/boards/arm/stm32/stm32ldiscovery/src/stm32_lcd.c +++ /dev/null @@ -1,1599 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32ldiscovery/src/stm32_lcd.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* References: - * - Based on the NuttX LCD1602 driver. - * - "STM32L100xx, STM32L151xx, STM32L152xx and STM32L162xx advanced - * ARM-based 32-bit MCUs", STMicroelectronics, RM0038 - * - "STM32L1 discovery kits: STM32L-DISCOVERY and 32L152CDISCOVERY," - * STMicroelectronics, UM1079 - * - STM32L-Discovery Firmware Pack V1.0.2 (for character encoding) - */ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include - -#include "arm_internal.h" -#include "stm32_gpio.h" -#include "stm32_rcc.h" -#include "hardware/stm32_lcd.h" - -#include "stm32ldiscovery.h" - -#ifdef CONFIG_STM32_LCD - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -/* Define CONFIG_DEBUG_LCD_INFO to enable detailed LCD debug output. */ - -#ifndef CONFIG_LIBC_SLCDCODEC -# error "This SLCD driver requires CONFIG_LIBC_SLCDCODEC" -#endif - -/* LCD **********************************************************************/ - -/* LCD. The STM32L152RBT6 supports either a 4x32 or 8x28. The STM32L- - * Discovery has an LCD 24 segments, 4 commons. See stm32ldiscovery.h for - * the pin mapping. - */ - -/* Macro to convert an LCD register offset and bit number into a bit-band - * address: - */ - -#define SLCD_OFFSET (STM32_LCD_BASE - STM32_PERIPH_BASE) -#define SLCD_BBADDR(o,b) (STM32_PERIPHBB_BASE + ((SLCD_OFFSET + (o)) << 5) + ((b) << 2)) - -/* Some useful bit-band addresses */ - -#define SLCD_CR_LCDEN_BB SLCD_BBADDR(STM32_LCD_CR_OFFSET,0) -#define SLCD_SR_UDR_BB SLCD_BBADDR(STM32_LCD_SR_OFFSET,2) - -/* LCD characteristics */ - -#define SLCD_NROWS 1 -#define SLCD_NCHARS 6 -#define SLCD_MAXCONTRAST 7 - -/* An ASCII character may need to be decorated with a colon or decimal - * point - */ - -#define SLCD_DP 0x01 -#define SLCD_COLON 0x02 -#define SLCD_NBARS 4 - -/* Macros used for set/reset the LCD bar */ - -#define SLCD_BAR0_ON g_slcdstate.bar[1] |= 8 -#define SLCD_BAR0_OFF g_slcdstate.bar[1] &= ~8 -#define SLCD_BAR1_ON g_slcdstate.bar[0] |= 8 -#define SLCD_BAR1_OFF g_slcdstate.bar[0] &= ~8 -#define SLCD_BAR2_ON g_slcdstate.bar[1] |= 2 -#define SLCD_BAR2_OFF g_slcdstate.bar[1] &= ~2 -#define SLCD_BAR3_ON g_slcdstate.bar[0] |= 2 -#define SLCD_BAR3_OFF g_slcdstate.bar[0] &= ~2 - -/* These definitions support the logic of slcd_writemem() - * - * ---------- ----- ----- ----- ----- ------- - * LCD SIGNAL COM3 COM2 COM1 COM0 RAM BIT - * - * ---------- ----- ----- ----- ----- ------- - * LCD SEG0 1N 1P 1D 1E Bit 0 - * LCD SEG1 1DP 1COL 1C 1M Bit 1 - * LCD SEG2 2N 2P 2D 2E Bit 2 - * LCD SEG3 2DP 2COL 2C 2M Bit 7 - * LCD SEG4 3N 3P 3D 3E Bit 8 - * LCD SEG5 3DP 3COL 3C 3M Bit 9 - * LCD SEG6 4N 4P 4D 4E Bit 10 - * LCD SEG7 4DP 4COL 4C 4M Bit 11 - * LCD SEG8 5N 5P 5D 5E Bit 12 - * LCD SEG9 BAR2 BAR3 5C 5M Bit 13 - * LCD SEG10 6N 6P 6D 6E Bit 14 - * LCD SEG11 BAR0 BAR1 6C 6M Bit 15 - * LCD SEG12 6J 6K 6A 6B Bit 16 - * LCD SEG13 6H 6Q 6F 6G Bit 17 - * LCD SEG14 5J 5K 5A 5B Bit 18 - * LCD SEG15 5H 5Q 5F 5G Bit 19 - * LCD SEG16 4J 4K 4A 4B Bit 20 - * LCD SEG17 4H 4Q 4F 4G Bit 21 - * LCD SEG18 3J 3K 3A 3B Bit 24 - * LCD SEG19 3H 3Q 3F 3G Bit 25 - * LCD SEG20 2J 2K 2A 2B Bit 26 - * LCD SEG21 2H 2Q 2F 2G Bit 27 - * LCD SEG22 1J 1K 1A 1B Bit 28 - * LCD SEG23 1H 1Q 1F 1G Bit 29 - * ---------- ----- ----- ----- ----- -------- - - * ---------------- ------ ------ ------ ------- ------- -------------------- - * LCD CHAR 1 CHAR 2 CHAR 3 CHAR 4 CHAR 5 CHAR 6 MASKS - * SIGNAL 3210 3210 3210 3210 32 10 32 10 - * --------- ------ ------ ------ ------ -- --- -- --- -------------------- - * LCD SEG0 1 0 0 0 0 0 0 0 CHAR 1: 0xcffffffc - * LCD SEG1 0 0 0 0 0 0 0 0 CHAR 1: 0xcffffffc - * LCD SEG2 0 1 0 0 0 0 0 0 CHAR 2: 0xf3ffff7b - * LCD SEG3 0 1 0 0 0 0 0 0 CHAR 2: 0xf3ffff7b - * LCD SEG4 0 0 1 0 0 0 0 0 CHAR 3: 0xfcfffcff - * LCD SEG5 0 0 1 0 0 0 0 0 CHAR 3: 0xfcfffcff - * LCD SEG6 0 0 0 1 0 0 0 0 CHAR 4: 0xffcff3ff - * LCD SEG7 0 0 0 1 0 0 0 0 CHAR 4: 0xffcff3ff - * LCD SEG8 0 0 0 0 1 1 0 0 CHAR 5: 0xfff3cfff/ - * 0xfff3efff - * LCD SEG9 0 0 0 0 0 1 0 0 CHAR 5: 0xfff3cfff/ - * 0xfff3efff - * LCD SEG10 0 0 0 0 0 0 1 1 CHAR 6: 0xfffc3fff/ - * 0xfffcbfff - * LCD SEG11 0 0 0 0 0 0 0 1 CHAR 6: 0xfffc3fff/ - * 0xfffcbfff - * LCD SEG12 0 0 0 0 0 0 1 1 CHAR 6: 0xfffc3fff/ - * 0xfffcbfff - * LCD SEG13 0 0 0 0 0 0 1 1 CHAR 6: 0xfffc3fff/ - * 0xfffcbfff - * LCD SEG14 0 0 0 0 1 1 0 0 CHAR 5: 0xfff3cfff/ - * 0xfff3efff - * LCD SEG15 0 0 0 0 1 1 0 0 CHAR 5: 0xfff3cfff/ - * 0xfff3efff - * LCD SEG16 0 0 0 1 0 0 0 0 CHAR 4: 0xffcff3ff - * LCD SEG17 0 0 0 1 0 0 0 0 CHAR 4: 0xffcff3ff - * LCD SEG18 0 0 1 0 0 0 0 0 CHAR 3: 0xfcfffcff - * LCD SEG19 0 0 1 0 0 0 0 0 CHAR 3: 0xfcfffcff - * LCD SEG20 0 1 0 0 0 0 0 0 CHAR 2: 0xf3ffff7b - * LCD SEG21 0 1 0 0 0 0 0 0 CHAR 2: 0xf3ffff7b - * LCD SEG22 1 0 0 0 0 0 0 0 CHAR 1: 0xcffffffc - * LCD SEG23 1 0 0 0 0 0 0 0 CHAR 1: 0xcffffffc - * --------- ------ ------ ------ ------- ------- --------------------------- - */ - -/* SLCD_CHAR1_MASK COM0-3 0xcffffffc ..11 .... .... .... .... .... .... ..11 - */ - -#define SLCD_CHAR1_MASK0 0xcffffffc -#define SLCD_CHAR1_MASK1 SLCD_CHAR1_MASK0 -#define SLCD_CHAR1_MASK2 SLCD_CHAR1_MASK0 -#define SLCD_CHAR1_MASK3 SLCD_CHAR1_MASK0 -#define SLCD_CHAR1_UPDATE0(s) (((uint32_t)(s) & 0x0c) << 26) | \ - ((uint32_t)(s) & 0x03) -#define SLCD_CHAR1_UPDATE1(s) SLCD_CHAR1_UPDATE0(s) -#define SLCD_CHAR1_UPDATE2(s) SLCD_CHAR1_UPDATE0(s) -#define SLCD_CHAR1_UPDATE3(s) SLCD_CHAR1_UPDATE0(s) - -/* SLCD_CHAR2_MASK COM0-3 0xf3ffff03 .... 22.. .... .... .... .... 2... .2.. - */ - -#define SLCD_CHAR2_MASK0 0xf3ffff7b -#define SLCD_CHAR2_MASK1 SLCD_CHAR2_MASK0 -#define SLCD_CHAR2_MASK2 SLCD_CHAR2_MASK0 -#define SLCD_CHAR2_MASK3 SLCD_CHAR2_MASK0 -#define SLCD_CHAR2_UPDATE0(s) (((uint32_t)(s) & 0x0c) << 24) | \ - (((uint32_t)(s) & 0x02) << 6) | \ - (((uint32_t)(s) & 0x01) << 2) -#define SLCD_CHAR2_UPDATE1(s) SLCD_CHAR2_UPDATE0(s) -#define SLCD_CHAR2_UPDATE2(s) SLCD_CHAR2_UPDATE0(s) -#define SLCD_CHAR2_UPDATE3(s) SLCD_CHAR2_UPDATE0(s) - -/* SLCD_CHAR3_MASK COM0-3 0xfcfffcff .... ..33 .... .... .... ..33 .... .... - */ - -#define SLCD_CHAR3_MASK0 0xfcfffcff -#define SLCD_CHAR3_MASK1 SLCD_CHAR3_MASK0 -#define SLCD_CHAR3_MASK2 SLCD_CHAR3_MASK0 -#define SLCD_CHAR3_MASK3 SLCD_CHAR3_MASK0 -#define SLCD_CHAR3_UPDATE0(s) (((uint32_t)(s) & 0x0c) << 22) | \ - (((uint32_t)(s) & 0x03) << 8) -#define SLCD_CHAR3_UPDATE1(s) SLCD_CHAR3_UPDATE0(s) -#define SLCD_CHAR3_UPDATE2(s) SLCD_CHAR3_UPDATE0(s) -#define SLCD_CHAR3_UPDATE3(s) SLCD_CHAR3_UPDATE0(s) - -/* SLCD_CHAR4_MASK COM0-3 0xffcff3ff .... .... ..44 .... .... 44.. .... .... - */ - -#define SLCD_CHAR4_MASK0 0xffcff3ff -#define SLCD_CHAR4_MASK1 SLCD_CHAR4_MASK0 -#define SLCD_CHAR4_MASK2 SLCD_CHAR4_MASK0 -#define SLCD_CHAR4_MASK3 SLCD_CHAR4_MASK0 -#define SLCD_CHAR4_UPDATE0(s) (((uint32_t)(s) & 0x0c) << 18) | \ - (((uint32_t)(s) & 0x03) << 10) -#define SLCD_CHAR4_UPDATE1(s) SLCD_CHAR4_UPDATE0(s) -#define SLCD_CHAR4_UPDATE2(s) SLCD_CHAR4_UPDATE0(s) -#define SLCD_CHAR4_UPDATE3(s) SLCD_CHAR4_UPDATE0(s) - -/* SLCD_CHAR5_MASK COM0-1 0xfff3cfff .... .... .... 55.. ..55 .... .... .... - * COM2-3 0xfff3efff .... .... .... 55.. ...5 .... .... .... - */ - -#define SLCD_CHAR5_MASK0 0xfff3cfff -#define SLCD_CHAR5_MASK1 SLCD_CHAR5_MASK0 -#define SLCD_CHAR5_MASK2 0xfff3efff -#define SLCD_CHAR5_MASK3 SLCD_CHAR5_MASK2 -#define SLCD_CHAR5_UPDATE0(s) (((uint32_t)(s) & 0x0c) << 16) | \ - (((uint32_t)(s) & 0x03) << 12) -#define SLCD_CHAR5_UPDATE1(s) SLCD_CHAR5_UPDATE0(s) -#define SLCD_CHAR5_UPDATE2(s) (((uint32_t)(s) & 0x0c) << 16) | \ - (((uint32_t)(s) & 0x01) << 12) -#define SLCD_CHAR5_UPDATE3(s) SLCD_CHAR5_UPDATE2(s) - -/* SLCD_CHAR6_MASK COM0-1 0xfffc3fff .... .... .... ..66 66.. .... .... .... - * COM2-3 0xfffc3fff .... .... .... ..66 .6.. .... .... .... - */ - -#define SLCD_CHAR6_MASK0 0xfffc3fff -#define SLCD_CHAR6_MASK1 SLCD_CHAR6_MASK0 -#define SLCD_CHAR6_MASK2 0xfffcbfff -#define SLCD_CHAR6_MASK3 SLCD_CHAR6_MASK2 -#define SLCD_CHAR6_UPDATE0(s) (((uint32_t)(s) & 0x04) << 15) | \ - (((uint32_t)(s) & 0x08) << 13) | \ - (((uint32_t)(s) & 0x03) << 14) -#define SLCD_CHAR6_UPDATE1(s) SLCD_CHAR6_UPDATE0(s) -#define SLCD_CHAR6_UPDATE2(s) (((uint32_t)(s) & 0x04) << 15) | \ - (((uint32_t)(s) & 0x08) << 13) | \ - (((uint32_t)(s) & 0x03) << 14) -#define SLCD_CHAR6_UPDATE3(s) SLCD_CHAR6_UPDATE2(s) - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/* Global SLCD state */ - -struct stm32_slcdstate_s -{ - bool initialized; /* True: Completed initialization sequence */ - uint8_t curpos; /* The current cursor position */ - uint8_t buffer[SLCD_NCHARS]; /* SLCD ASCII content */ - uint8_t options[SLCD_NCHARS]; /* With colon or decimal point decoration */ - uint8_t bar[2]; /* Controls the bars on the far right of the SLCD */ -}; - -/**************************************************************************** - * Private Function Protototypes - ****************************************************************************/ - -/* Debug */ - -#ifdef CONFIG_DEBUG_LCD_INFO -static void slcd_dumpstate(const char *msg); -static void slcd_dumpslcd(const char *msg); -#else -# define slcd_dumpstate(msg) -# define slcd_dumpslcd(msg) -#endif - -/* Internal utilities */ - -static void slcd_clear(void); -static uint8_t slcd_getcontrast(void); -static int slcd_setcontrast(uint8_t contrast); -static void slcd_writebar(void); -static inline uint16_t slcd_mapch(uint8_t ch); -static inline void slcd_writemem(uint16_t segset, int curpos); -static void slcd_writech(uint8_t ch, uint8_t curpos, uint8_t options); -static void slcd_appendch(uint8_t ch, uint8_t options); -static void slcd_action(enum slcdcode_e code, uint8_t count); - -/* Character driver methods */ - -static ssize_t slcd_read(struct file *, char *, size_t); -static ssize_t slcd_write(struct file *, const char *, size_t); -static int slcd_ioctl(struct file *filep, int cmd, unsigned long arg); -static int slcd_poll(struct file *filep, struct pollfd *fds, - bool setup); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* This is the driver state structure (there is no retained state - * information) - */ - -static const struct file_operations g_slcdops = -{ - NULL, /* open */ - NULL, /* close */ - slcd_read, /* read */ - slcd_write, /* write */ - NULL, /* seek */ - slcd_ioctl, /* ioctl */ - NULL, /* mmap */ - NULL, /* truncate */ - slcd_poll /* poll */ -}; - -/* LCD state data */ - -static struct stm32_slcdstate_s g_slcdstate; - -/* LCD Mapping - * - * A - * --------- _ - * |\ |J /| |_| COL - * F| H | K |B - * | \ | / | _ - * --G-- --M-+ |_| COL - * | /| \ | - * E| Q | N |C - * | / |P \| _ - * --------- |_| DP - * D - * - * LCD character 16-bit-encoding: - * { E , D , P , N, M , C , COL , DP, B , A , K , J, G , F , Q , H } - */ - -#warning "Encodings for all punctuation are incomplete" - -/* Space and ASCII punctuation: 0x20-0x2f */ - -static const uint16_t g_slcdpunct1[ASCII_0 - ASCII_SPACE] = -{ - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /* ! " # $ % & ' */ - 0x0000, 0x0000, 0xa0dd, 0x0000, 0x0000, 0xa000, 0x0000, 0x00c0 /* () * + , - . / */ -}; - -/* ASCII numerals 0-9: 0x30-0x39 */ - -static const uint16_t g_slcdnummap[ASCII_COLON - ASCII_0] = -{ - 0x5f00, 0x4200, 0xf500, 0x6700, 0xea00, 0xaf00, 0xbf00, 0x4600, /* 0-7 */ - 0xff00, 0xef00 /* 8-9 */ -}; - -/* ASCII punctuation: 0x3a-0x40 */ - -static const uint16_t g_slcdpunct2[ASCII_A - ASCII_COLON] = -{ - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000 /* : ; < = > ? @ */ -}; - -/* Upper case letters A-Z: 0x41-0x5a. Also lower case letters a-z: - * 0x61-0x7a - */ - -static const uint16_t g_slcdalphamap[ASCII_LBRACKET - ASCII_A] = -{ - 0xfe00, 0x6714, 0x1d00, 0x4714, 0x9d00, 0x9c00, 0x3f00, 0xfa00, /* A-H */ - 0x0014, 0x5300, 0x9841, 0x1900, 0x5a48, 0x5a09, 0x5f00, 0xfc00, /* I-P */ - 0x5f01, 0xfc01, 0xaf00, 0x0414, 0x5b00, 0x18c0, 0x5a81, 0x00c9, /* Q-X */ - 0x0058, 0x05c0 /* y-Z */ -}; - -/* ASCII punctuation: 0x5b-0x60 */ - -static const uint16_t g_slcdpunct3[ASCII_a - ASCII_LBRACKET] = -{ - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000 /* [ \ ] ^ _ */ -}; - -/* ASCII punctuation: 0x7b-0x7e */ - -static const uint16_t g_slcdpunct4[ASCII_DEL - ASCII_LBRACE] = -{ - 0x0000, 0x0000, 0x0000, 0x0000 /* { | } ~ */ -}; - -/* All GPIOs that need to be configured for the STM32L-Discovery LCD */ - -static uint32_t g_slcdgpio[BOARD_SLCD_NGPIOS] = -{ - BOARD_SLCD_COM0, BOARD_SLCD_COM1, BOARD_SLCD_COM2, BOARD_SLCD_COM3, - - BOARD_SLCD_SEG0, BOARD_SLCD_SEG1, BOARD_SLCD_SEG2, BOARD_SLCD_SEG3, - BOARD_SLCD_SEG4, BOARD_SLCD_SEG5, BOARD_SLCD_SEG6, BOARD_SLCD_SEG7, - BOARD_SLCD_SEG8, BOARD_SLCD_SEG9, BOARD_SLCD_SEG10, BOARD_SLCD_SEG11, - BOARD_SLCD_SEG12, BOARD_SLCD_SEG13, BOARD_SLCD_SEG14, BOARD_SLCD_SEG15, - BOARD_SLCD_SEG16, BOARD_SLCD_SEG17, BOARD_SLCD_SEG18, BOARD_SLCD_SEG19, - BOARD_SLCD_SEG20, BOARD_SLCD_SEG21, BOARD_SLCD_SEG22, BOARD_SLCD_SEG23 -}; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: slcd_dumpstate - ****************************************************************************/ - -#ifdef CONFIG_DEBUG_LCD_INFO -static void slcd_dumpstate(const char *msg) -{ - lcdinfo("%s:\n", msg); - lcdinfo(" curpos: %d\n", - g_slcdstate.curpos); - lcdinfo(" Display: [%c%c%c%c%c%c]\n", - g_slcdstate.buffer[0], g_slcdstate.buffer[1], - g_slcdstate.buffer[2], g_slcdstate.buffer[3], - g_slcdstate.buffer[4], g_slcdstate.buffer[5]); - lcdinfo(" Options: [%d%d%d%d%d%d]\n", - g_slcdstate.options[0], g_slcdstate.options[1], - g_slcdstate.options[2], g_slcdstate.options[3], - g_slcdstate.options[4], g_slcdstate.options[5]); - lcdinfo(" Bar: %02x %02x\n", - g_slcdstate.bar[0], g_slcdstate.bar[1]); -} -#endif - -/**************************************************************************** - * Name: slcd_dumpslcd - ****************************************************************************/ - -#ifdef CONFIG_DEBUG_LCD_INFO -static void slcd_dumpslcd(const char *msg) -{ - lcdinfo("%s:\n", msg); - lcdinfo(" CR: %08x FCR: %08x SR: %08x CLR: %08x\n", - getreg32(STM32_LCD_CR), getreg32(STM32_LCD_FCR), - getreg32(STM32_LCD_SR), getreg32(STM32_LCD_CLR)); - lcdinfo(" RAM0L: %08x RAM1L: %08x RAM2L: %08x RAM3L: %08x\n", - getreg32(STM32_LCD_RAM0L), getreg32(STM32_LCD_RAM1L), - getreg32(STM32_LCD_RAM2L), getreg32(STM32_LCD_RAM3L)); -} -#endif - -/**************************************************************************** - * Name: slcd_clear - ****************************************************************************/ - -static void slcd_clear(void) -{ - uint32_t regaddr; - - linfo("Clearing\n"); - - /* Make sure that any previous transfer is complete. The firmware sets - * the UDR each it modifies the LCD_RAM. The UDR bit stays set until the - * end of the update. During this time the LCD_RAM is write protected. - */ - - while ((getreg32(STM32_LCD_SR) & LCD_SR_UDR) != 0); - - /* Write all zerios in to the LCD RAM */ - - for (regaddr = STM32_LCD_RAML(0); regaddr <= STM32_LCD_RAMH(7); regaddr++) - { - putreg32(0, regaddr); - } - - /* Set all buffered data to undecorated spaces and home the cursor */ - - memset(g_slcdstate.buffer, ' ', SLCD_NCHARS); - memset(g_slcdstate.options, 0, SLCD_NCHARS); - g_slcdstate.curpos = 0; - - /* Set the UDR bit to transfer the updated data to the second level - * buffer. - */ - - putreg32(1, SLCD_SR_UDR_BB); -} - -/**************************************************************************** - * Name: slcd_getcontrast - ****************************************************************************/ - -static uint8_t slcd_getcontrast(void) -{ - return (getreg32(STM32_LCD_FCR) & LCD_FCR_CC_MASK) >> LCD_FCR_CC_SHIFT; -} - -/**************************************************************************** - * Name: slcd_setcontrast - ****************************************************************************/ - -static int slcd_setcontrast(uint8_t contrast) -{ - uint32_t regval; - int ret = OK; - - /* Make sure that the contrast setting is within range */ - - if (contrast > 7) - { - contrast = 7; - ret = -ERANGE; - } - - regval = getreg32(STM32_LCD_FCR); - regval &= ~LCD_FCR_CC_MASK; - regval |= contrast << LCD_FCR_CC_SHIFT; - putreg32(regval, STM32_LCD_FCR); - - lcdinfo("contrast: %" PRId32 " FCR: %08x\n", - getreg32(STM32_LCD_FCR), contrast); - - return ret; -} - -/**************************************************************************** - * Name: slcd_writebar - ****************************************************************************/ - -static void slcd_writebar(void) -{ - uint32_t regval; - - lcdinfo("bar: %02x %02x\n", g_slcdstate.bar[0], g_slcdstate.bar[1]); - slcd_dumpslcd("BEFORE WRITE"); - - /* Make sure that any previous transfer is complete. The firmware sets - * the UDR each it modifies the LCD_RAM. The UDR bit stays set until the - * end of the update. During this time the LCD_RAM is write protected. - */ - - while ((getreg32(STM32_LCD_SR) & LCD_SR_UDR) != 0); - - /* Update the BAR */ - - regval = getreg32(STM32_LCD_RAM2L); - regval &= 0xffff5fff; - regval |= (uint32_t)(g_slcdstate.bar[0] << 12); - putreg32(regval, STM32_LCD_RAM2L); - - regval = getreg32(STM32_LCD_RAM3L); - regval &= 0xffff5fff; - regval |= (uint32_t)(g_slcdstate.bar[1] << 12); - putreg32(regval, STM32_LCD_RAM3L); - - /* Set the UDR bit to transfer the updated data to the second level - * buffer. - */ - - putreg32(1, SLCD_SR_UDR_BB); - slcd_dumpslcd("AFTER WRITE"); -} - -/**************************************************************************** - * Name: slcd_mapch - ****************************************************************************/ - -static inline uint16_t slcd_mapch(uint8_t ch) -{ - /* ASCII control characters, the forward delete character, period, colon, - * and all 8-bit ASCII character have already been handled prior to this - * function. - */ - - /* Return spaces all control characters (this should not happen) */ - - if (ch < ASCII_SPACE) - { - return 0x0000; - } - - /* Handle space and the first block of punctuation */ - - if (ch < ASCII_0) - { - return g_slcdpunct1[(int)ch - ASCII_SPACE]; - } - - /* Handle numbers */ - - else if (ch < ASCII_COLON) - { - return g_slcdnummap[(int)ch - ASCII_0]; - } - - /* Handle the next block of punctuation */ - - else if (ch < ASCII_A) - { - return g_slcdpunct2[(int)ch - ASCII_COLON]; - } - - /* Handle upper case letters */ - - else if (ch < ASCII_LBRACKET) - { - return g_slcdalphamap[(int)ch - ASCII_A]; - } - - /* Handle the next block of punctuation */ - - else if (ch < ASCII_a) - { - return g_slcdpunct3[(int)ch - ASCII_LBRACKET]; - } - - /* Handle lower case letters (by mapping them to upper case */ - - else if (ch < ASCII_LBRACE) - { - return g_slcdalphamap[(int)ch - ASCII_a]; - } - - /* Handle the final block of punctuation */ - - else if (ch < ASCII_DEL) - { - return g_slcdpunct4[(int)ch - ASCII_LBRACE]; - } - - /* Ignore 8-bit ASCII and DEL (this should not happen) */ - - return 0x0000; -} - -/**************************************************************************** - * Name: slcd_writemem - ****************************************************************************/ - -static inline void slcd_writemem(uint16_t segset, int curpos) -{ - uint8_t segments[4]; - uint32_t ram0; - uint32_t ram1; - uint32_t ram2; - uint32_t ram3; - int i; - int j; - - lcdinfo("segset: %04x curpos: %d\n", segset, curpos); - slcd_dumpslcd("BEFORE WRITE"); - - /* Isolate the least significant bits - * - * LCD character 16-bit-encoding: - * { E , D , P , N, M , C , COL , DP, B , A , K , J, G , F , Q , H } - * - * segments[0] = { E , D , P , N } - * segments[1] = { M , C , COL , DP } - * segments[2] = { B , A , K , J } - * segments[3] = { G , F , Q , H } - */ - - for (i = 12, j = 0; j < 4; i -= 4, j++) - { - segments[j] = (segset >> i) & 0x0f; - } - - lcdinfo("segments: %02x %02x %02x %02x\n", - segments[0], segments[1], segments[2], segments[3]); - - /* Make sure that any previous transfer is complete. The firmware sets - * the UDR each it modifies the LCD_RAM. The UDR bit stays set until the - * end of the update. During this time the LCD_RAM is write protected. - */ - - while ((getreg32(STM32_LCD_SR) & LCD_SR_UDR) != 0); - - /* Now update the SLCD memory for the character at this cursor position by - * decoding the bit-mapped value - */ - - ram0 = getreg32(STM32_LCD_RAM0L); - ram1 = getreg32(STM32_LCD_RAM1L); - ram2 = getreg32(STM32_LCD_RAM2L); - ram3 = getreg32(STM32_LCD_RAM3L); - - switch (curpos) - { - case 0: - ram0 &= SLCD_CHAR1_MASK0; - ram0 |= SLCD_CHAR1_UPDATE0(segments[0]); - - ram1 &= SLCD_CHAR1_MASK1; - ram1 |= SLCD_CHAR1_UPDATE1(segments[1]); - - ram2 &= SLCD_CHAR1_MASK2; - ram2 |= SLCD_CHAR1_UPDATE2(segments[2]); - - ram3 &= SLCD_CHAR1_MASK3; - ram3 |= SLCD_CHAR1_UPDATE3(segments[3]); - break; - - case 1: - ram0 &= SLCD_CHAR2_MASK0; - ram0 |= SLCD_CHAR2_UPDATE0(segments[0]); - - ram1 &= SLCD_CHAR2_MASK1; - ram1 |= SLCD_CHAR2_UPDATE1(segments[1]); - - ram2 &= SLCD_CHAR2_MASK2; - ram2 |= SLCD_CHAR2_UPDATE2(segments[2]); - - ram3 &= SLCD_CHAR2_MASK3; - ram3 |= SLCD_CHAR2_UPDATE3(segments[3]); - break; - - case 2: - ram0 &= SLCD_CHAR3_MASK0; - ram0 |= SLCD_CHAR3_UPDATE0(segments[0]); - - ram1 &= SLCD_CHAR3_MASK1; - ram1 |= SLCD_CHAR3_UPDATE1(segments[1]); - - ram2 &= SLCD_CHAR3_MASK2; - ram2 |= SLCD_CHAR3_UPDATE2(segments[2]); - - ram3 &= SLCD_CHAR3_MASK3; - ram3 |= SLCD_CHAR3_UPDATE3(segments[3]); - break; - - case 3: - ram0 &= SLCD_CHAR4_MASK0; - ram0 |= SLCD_CHAR4_UPDATE0(segments[0]); - - ram1 &= SLCD_CHAR4_MASK1; - ram1 |= SLCD_CHAR4_UPDATE1(segments[1]); - - ram2 &= SLCD_CHAR4_MASK2; - ram2 |= SLCD_CHAR4_UPDATE2(segments[2]); - - ram3 &= SLCD_CHAR4_MASK3; - ram3 |= SLCD_CHAR4_UPDATE3(segments[3]); - break; - - case 4: - ram0 &= SLCD_CHAR5_MASK0; - ram0 |= SLCD_CHAR5_UPDATE0(segments[0]); - - ram1 &= SLCD_CHAR5_MASK1; - ram1 |= SLCD_CHAR5_UPDATE1(segments[1]); - - ram2 &= SLCD_CHAR5_MASK2; - ram2 |= SLCD_CHAR5_UPDATE2(segments[2]); - - ram3 &= SLCD_CHAR5_MASK3; - ram3 |= SLCD_CHAR5_UPDATE3(segments[3]); - break; - - case 5: - ram0 &= SLCD_CHAR6_MASK0; - ram0 |= SLCD_CHAR6_UPDATE0(segments[0]); - - ram1 &= SLCD_CHAR6_MASK1; - ram1 |= SLCD_CHAR6_UPDATE1(segments[1]); - - ram2 &= SLCD_CHAR6_MASK2; - ram2 |= SLCD_CHAR6_UPDATE2(segments[2]); - - ram3 &= SLCD_CHAR6_MASK3; - ram3 |= SLCD_CHAR6_UPDATE3(segments[3]); - break; - - default: - return; - } - - putreg32(ram0, STM32_LCD_RAM0L); - putreg32(ram1, STM32_LCD_RAM1L); - putreg32(ram2, STM32_LCD_RAM2L); - putreg32(ram3, STM32_LCD_RAM3L); - - /* Set the UDR bit to transfer the updated data to the second level - * buffer. - */ - - putreg32(1, SLCD_SR_UDR_BB); - slcd_dumpslcd("AFTER WRITE"); -} - -/**************************************************************************** - * Name: slcd_writech - ****************************************************************************/ - -static void slcd_writech(uint8_t ch, uint8_t curpos, uint8_t options) -{ - uint16_t segset; - - /* Map the character code to a 16-bit encoded value */ - - segset = slcd_mapch(ch); - - /* Check if the character should be decorated with a decimal point or - * colon - */ - - if ((options & SLCD_DP) != 0) - { - segset |= 0x0002; - } - else if ((options & SLCD_COLON) != 0) - { - segset |= 0x0020; - } - - lcdinfo("ch: [%c] options: %02x segset: %04x\n", ch, options, segset); - - /* Decode the value and write it to the SLCD segment memory */ - - slcd_writemem(segset, curpos); - - /* Save these values in the state structure */ - - g_slcdstate.buffer[curpos] = ch; - g_slcdstate.options[curpos] = options; - - slcd_dumpstate("AFTER WRITE"); -} - -/**************************************************************************** - * Name: slcd_appendch - ****************************************************************************/ - -static void slcd_appendch(uint8_t ch, uint8_t options) -{ - lcdinfo("ch: [%c] options: %02x\n", ch, options); - - /* Write the character at the current cursor position */ - - slcd_writech(ch, g_slcdstate.curpos, options); - if (g_slcdstate.curpos < (SLCD_NCHARS - 1)) - { - g_slcdstate.curpos++; - } - - slcd_dumpstate("AFTER APPEND"); -} - -/**************************************************************************** - * Name: slcd_action - ****************************************************************************/ - -static void slcd_action(enum slcdcode_e code, uint8_t count) -{ - lcdinfo("Action: %d count: %d\n", code, count); - slcd_dumpstate("BEFORE ACTION"); - - switch (code) - { - /* Erasure */ - - case SLCDCODE_BACKDEL: /* Backspace (backward delete) N characters */ - { - int tmp; - - /* If we are at the home position or if the count is zero, then - * ignore the action - */ - - if (g_slcdstate.curpos < 1 || count < 1) - { - break; - } - - /* Otherwise, BACKDEL is like moving the cursor back N characters - * then doing a forward deletion. Decrement the cursor position - * and fall through. - */ - - tmp = (int)g_slcdstate.curpos - count; - if (tmp < 0) - { - tmp = 0; - count = g_slcdstate.curpos; - } - - /* Save the updated cursor positions */ - - g_slcdstate.curpos = tmp; - } - - case SLCDCODE_FWDDEL: /* DELete (forward delete) N characters moving text */ - if (count > 0) - { - int nchars; - int nmove; - int i; - - /* How many characters are to the right of the cursor position - * (including the one at the cursor position)? Then get the - * number of characters to move. - */ - - nchars = SLCD_NCHARS - g_slcdstate.curpos; - nmove = MIN(nchars, count) - 1; - - /* Move all characters after the current cursor position left - * by 'nmove' characters - */ - - for (i = g_slcdstate.curpos + nmove; i < SLCD_NCHARS - 1; i++) - { - slcd_writech(g_slcdstate.buffer[i - nmove], i, - g_slcdstate.options[i - nmove]); - } - - /* Erase the last 'nmove' characters on the display */ - - for (i = SLCD_NCHARS - nmove; i < SLCD_NCHARS; i++) - { - slcd_writech(' ', i, 0); - } - } - break; - - case SLCDCODE_ERASE: /* Erase N characters from the cursor position */ - if (count > 0) - { - int last; - int i; - - /* Get the last position to clear and make sure that the last - * position is on the SLCD. - */ - - last = g_slcdstate.curpos + count - 1; - if (last >= SLCD_NCHARS) - { - last = SLCD_NCHARS - 1; - } - - /* Erase N characters after the current cursor position left by - * one - */ - - for (i = g_slcdstate.curpos; i < last; i++) - { - slcd_writech(' ', i, 0); - } - } - break; - - case SLCDCODE_CLEAR: /* Home the cursor and erase the entire display */ - { - /* This is like HOME followed by ERASEEOL. Home the cursor and - * fall through. - */ - - g_slcdstate.curpos = 0; - } - - case SLCDCODE_ERASEEOL: /* Erase from the cursor position to the end of line */ - { - int i; - - /* Erase characters after the current cursor position to the end - * of the line - */ - - for (i = g_slcdstate.curpos; i < SLCD_NCHARS; i++) - { - slcd_writech(' ', i, 0); - } - } - break; - - /* Cursor movement */ - - case SLCDCODE_HOME: /* Cursor home */ - { - g_slcdstate.curpos = 0; - } - break; - - case SLCDCODE_END: /* Cursor end */ - { - g_slcdstate.curpos = SLCD_NCHARS - 1; - } - break; - - case SLCDCODE_LEFT: /* Cursor left by N characters */ - { - int tmp = (int)g_slcdstate.curpos - count; - - /* Don't permit movement past the beginning of the SLCD */ - - if (tmp < 0) - { - tmp = 0; - } - - /* Save the new cursor position */ - - g_slcdstate.curpos = (uint8_t)tmp; - } - break; - - case SLCDCODE_RIGHT: /* Cursor right by N characters */ - { - int tmp = (int)g_slcdstate.curpos + count; - - /* Don't permit movement past the end of the SLCD */ - - if (tmp >= SLCD_NCHARS) - { - tmp = SLCD_NCHARS - 1; - } - - /* Save the new cursor position */ - - g_slcdstate.curpos = (uint8_t)tmp; - } - break; - - case SLCDCODE_UP: /* Cursor up by N lines */ - case SLCDCODE_DOWN: /* Cursor down by N lines */ - case SLCDCODE_PAGEUP: /* Cursor up by N pages */ - case SLCDCODE_PAGEDOWN: /* Cursor down by N pages */ - break; /* Not supportable on this SLCD */ - - /* Blinking */ - - case SLCDCODE_BLINKSTART: /* Start blinking with current cursor position */ - case SLCDCODE_BLINKEND: /* End blinking after the current cursor position */ - case SLCDCODE_BLINKOFF: /* Turn blinking off */ - break; /* Not implemented */ - - /* These are actually unreportable errors */ - - default: - case SLCDCODE_NORMAL: /* Not a special keycode */ - break; - } - - slcd_dumpstate("AFTER ACTION"); -} - -/**************************************************************************** - * Name: slcd_read - ****************************************************************************/ - -static ssize_t slcd_read(struct file *filep, char *buffer, - size_t len) -{ - int ret = 0; - int i; - - /* Try to read the entire display. Notice that the seek offset - * (filep->f_pos) is ignored. It probably should be taken into account - * and also updated after each read and write. - */ - - for (i = 0; i < SLCD_NCHARS && ret < len; i++) - { - /* Return the character */ - - *buffer++ = g_slcdstate.buffer[i]; - ret++; - - /* Check if the character is decorated with a following period or - * colon - */ - - if (ret < len && g_slcdstate.buffer[i] != 0) - { - if ((g_slcdstate.buffer[i] & SLCD_DP) != 0) - { - *buffer++ = '.'; - ret++; - } - else if ((g_slcdstate.buffer[i] & SLCD_COLON) != 0) - { - *buffer++ = ':'; - ret++; - } - } - } - - slcd_dumpstate("READ"); - return ret; -} - -/**************************************************************************** - * Name: slcd_write - ****************************************************************************/ - -static ssize_t slcd_write(struct file *filep, - const char *buffer, size_t len) -{ - struct lib_meminstream_s instream; - struct slcdstate_s state; - enum slcdret_e result; - uint8_t ch; - uint8_t count; - uint8_t prev = ' '; - bool valid = false; - - /* Initialize the stream for use with the SLCD CODEC */ - - lib_meminstream(&instream, buffer, len); - - /* Prime the pump. This is messy, but necessary to handle decoration on a - * character based on any following period or colon. - */ - - memset(&state, 0, sizeof(struct slcdstate_s)); - result = slcd_decode(&instream.common, &state, &prev, &count); - - lcdinfo("slcd_decode returned result=%d char=%d count=%d\n", - result, prev, count); - - switch (result) - { - case SLCDRET_CHAR: - valid = true; - break; - - case SLCDRET_SPEC: - { - slcd_action((enum slcdcode_e)prev, count); - prev = ' '; - } - break; - - case SLCDRET_EOF: - return 0; - } - - /* Now decode and process every byte in the input buffer */ - - while ((result = slcd_decode(&instream.common, - &state, &ch, &count)) != SLCDRET_EOF) - { - lcdinfo("slcd_decode returned result=%d char=%d count=%d\n", - result, ch, count); - - if (result == SLCDRET_CHAR) /* A normal character was returned */ - { - /* Check for ASCII control characters */ - - if (ch < ASCII_SPACE) - { - /* All are ignored except for backspace and carriage return */ - - if (ch == ASCII_BS) - { - /* If there is a pending character, then output it now - * before performing the action. - */ - - if (valid) - { - slcd_appendch(prev, 0); - prev = ' '; - valid = false; - } - - /* Then perform the backward deletion */ - - slcd_action(SLCDCODE_BACKDEL, 1); - } - else if (ch == ASCII_CR) - { - /* If there is a pending character, then output it now - * before performing the action. - */ - - if (valid) - { - slcd_appendch(prev, 0); - prev = ' '; - valid = false; - } - - /* Then perform the carriage return */ - - slcd_action(SLCDCODE_HOME, 0); - } - } - - /* Handle characters decoreated with a period or a colon */ - - else if (ch == '.') - { - /* Write the previous character with the decimal point - * appended - */ - - slcd_appendch(prev, SLCD_DP); - prev = ' '; - valid = false; - } - else if (ch == ':') - { - /* Write the previous character with the colon appended */ - - slcd_appendch(prev, SLCD_COLON); - prev = ' '; - valid = false; - } - - /* Handle ASCII_DEL */ - - else if (ch == ASCII_DEL) - { - /* If there is a pending character, then output it now before - * performing the action. - */ - - if (valid) - { - slcd_appendch(prev, 0); - prev = ' '; - valid = false; - } - - /* Then perform the forward deletion */ - - slcd_action(SLCDCODE_FWDDEL, 1); - } - - /* The rest of the 7-bit ASCII characters are fair game */ - - else if (ch < 128) - { - /* Write the previous character if it valid */ - - if (valid) - { - slcd_appendch(prev, 0); - } - - /* There is now a valid output character */ - - prev = ch; - valid = true; - } - } - else /* (result == SLCDRET_SPEC) */ /* A special SLCD action was returned */ - { - /* If there is a pending character, then output it now before - * performing the action. - */ - - if (valid) - { - slcd_appendch(prev, 0); - prev = ' '; - valid = false; - } - - /* Then perform the action */ - - slcd_action((enum slcdcode_e)ch, count); - } - } - - /* Handle any unfinished output */ - - if (valid) - { - slcd_appendch(prev, 0); - } - - /* Assume that the entire input buffer was processed */ - - return (ssize_t)len; -} - -/**************************************************************************** - * Name: slcd_poll - ****************************************************************************/ - -static int slcd_ioctl(struct file *filep, int cmd, unsigned long arg) -{ - switch (cmd) - { - /* SLCDIOC_GETATTRIBUTES: Get the attributes of the SLCD - * - * argument: Pointer to struct slcd_attributes_s in which values - * will be returned - */ - - case SLCDIOC_GETATTRIBUTES: - { - struct slcd_attributes_s *attr = - (struct slcd_attributes_s *)((uintptr_t)arg); - - lcdinfo("SLCDIOC_GETATTRIBUTES:\n"); - - if (!attr) - { - return -EINVAL; - } - - attr->nrows = SLCD_NROWS; - attr->ncolumns = SLCD_NCHARS; - attr->nbars = SLCD_NBARS; - attr->maxcontrast = SLCD_MAXCONTRAST; - attr->maxbrightness = 0; - } - break; - - /* SLCDIOC_CURPOS: Get the SLCD cursor positioni (rows x characters) - * - * argument: Pointer to struct slcd_curpos_s in which values will be - * returned - */ - - case SLCDIOC_CURPOS: - { - struct slcd_curpos_s *curpos = - (struct slcd_curpos_s *)((uintptr_t)arg); - - lcdinfo("SLCDIOC_CURPOS: row=0 column=%d\n", g_slcdstate.curpos); - - if (!curpos) - { - return -EINVAL; - } - - curpos->row = 0; - curpos->column = g_slcdstate.curpos; - } - break; - - /* SLCDIOC_SETBAR: Set bars on a bar display - * - * argument: 32-bit bitset, with each bit corresponding to one bar. - */ - - case SLCDIOC_SETBAR: - { - lcdinfo("SLCDIOC_SETBAR: arg=0x%02lx\n", arg); - - /* Format the bar */ - - g_slcdstate.bar[0] = 0; - g_slcdstate.bar[1] = 0; - - if ((arg & 1) != 0) - { - SLCD_BAR0_ON; - } - - if ((arg & 2) != 0) - { - SLCD_BAR1_ON; - } - - if ((arg & 4) != 0) - { - SLCD_BAR2_ON; - } - - if ((arg & 8) != 0) - { - SLCD_BAR3_ON; - } - - /* Write the bar to SLCD memory */ - - slcd_writebar(); - } - break; - - /* SLCDIOC_GETCONTRAST: Get the current contrast setting - * - * argument: Pointer type int that will receive the current contrast - * setting - */ - - case SLCDIOC_GETCONTRAST: - { - int *contrast = (int *)((uintptr_t)arg); - if (!contrast) - { - return -EINVAL; - } - - *contrast = (int)slcd_getcontrast(); - lcdinfo("SLCDIOC_GETCONTRAST: contrast=%d\n", *contrast); - } - break; - - /* SLCDIOC_SETCONTRAST: Set the contrast to a new value - * - * argument: The new contrast value - */ - - case SLCDIOC_SETCONTRAST: - { - lcdinfo("SLCDIOC_SETCONTRAST: arg=%ld\n", arg); - - if (arg > SLCD_MAXCONTRAST) - { - return -ERANGE; - } - - return slcd_setcontrast((uint8_t)arg); - } - break; - - case SLCDIOC_GETBRIGHTNESS: /* Get the current brightness setting */ - case SLCDIOC_SETBRIGHTNESS: /* Set the brightness to a new value */ - default: - return -ENOTTY; - } - - return OK; -} - -/**************************************************************************** - * Name: slcd_poll - ****************************************************************************/ - -static int slcd_poll(struct file *filep, struct pollfd *fds, - bool setup) -{ - if (setup) - { - /* Data is always available to be read / Data can always be written */ - - poll_notify(&fds, 1, POLLIN | POLLOUT); - } - - return OK; -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_slcd_initialize - * - * Description: - * Initialize the STM32L-Discovery LCD hardware and register the character - * driver as /dev/slcd0. - * - ****************************************************************************/ - -int stm32_slcd_initialize(void) -{ - uint32_t regval; - int ret = OK; - int i; - - /* Only initialize the driver once. */ - - if (!g_slcdstate.initialized) - { - lcdinfo("Initializing\n"); - - /* Configure LCD GPIO pins */ - - for (i = 0; i < BOARD_SLCD_NGPIOS; i++) - { - stm32_configgpio(g_slcdgpio[i]); - } - - /* Enable the External Low-Speed (LSE) oscillator and select it as the - * LCD clock source. - * - * NOTE: LCD clocking should already be enabled in the RCC APB1ENR - * register. - */ - - stm32_rcc_enablelse(); - - lcdinfo("APB1ENR: %08" PRIx32 " CSR: %08" PRIx32 "\n", - getreg32(STM32_RCC_APB1ENR), getreg32(STM32_RCC_CSR)); - - /* Set the LCD prescaler and divider values */ - - regval = getreg32(STM32_LCD_FCR); - regval &= ~(LCD_FCR_DIV_MASK | LCD_FCR_PS_MASK); - regval |= (LCD_FCR_PS_DIV1 | LCD_FCR_DIV(31)); - putreg32(regval, STM32_LCD_FCR); - - /* Wait for the FCRSF flag to be set */ - - lcdinfo("Wait for FCRSF, FSR: %08" PRIx32 " SR: %08" PRIx32 "\n", - getreg32(STM32_LCD_FCR), getreg32(STM32_LCD_SR)); - - while ((getreg32(STM32_LCD_SR) & LCD_SR_FCRSF) == 0); - - /* Set the duty (1/4), bias (1/3), and the internal voltage source - * (VSEL=0) - */ - - regval = getreg32(STM32_LCD_CR); - regval &= ~(LCD_CR_BIAS_MASK | LCD_CR_DUTY_MASK | LCD_CR_VSEL); - regval |= (LCD_CR_DUTY_1TO4 | LCD_CR_BIAS_1TO3); - putreg32(regval, STM32_LCD_CR); - - /* SEG[31:28] are multiplexed with SEG[43:40] */ - - regval |= LCD_CR_MUX_SEG; - putreg32(regval, STM32_LCD_CR); - - /* Set the contrast to the mean value */ - - regval = getreg32(STM32_LCD_FCR); - regval &= ~LCD_FCR_CC_MASK; - regval |= LCD_FCR_CC_VLCD(4); - putreg32(regval, STM32_LCD_FCR); - - /* No dead time */ - - regval &= ~LCD_FCR_DEAD_MASK; - putreg32(regval, STM32_LCD_FCR); - - /* Set the pulse-on duration to 4/ck_ps */ - - regval &= ~LCD_FCR_PON_MASK; - regval |= LCD_FCR_PON(4); - putreg32(regval, STM32_LCD_FCR); - - /* Wait Until the LCD FCR register is synchronized */ - - lcdinfo("Wait for FCRSF, FSR: %08" PRIx32 " SR: %08" PRIx32 "\n", - getreg32(STM32_LCD_FCR), getreg32(STM32_LCD_SR)); - - while ((getreg32(STM32_LCD_SR) & LCD_SR_FCRSF) == 0); - - /* Enable LCD peripheral */ - - putreg32(1, SLCD_CR_LCDEN_BB); - - /* Wait Until the LCD is enabled and the LCD booster is ready */ - - lcdinfo("Wait for LCD_SR_ENS and LCD_SR_RDY, " - "CR: %08" PRIx32 " SR: %08" PRIx32 "\n", - getreg32(STM32_LCD_CR), getreg32(STM32_LCD_SR)); - - while ((getreg32(STM32_LCD_SR) & (LCD_SR_ENS | LCD_SR_RDY)) != - (LCD_SR_ENS | LCD_SR_RDY)); - - /* Disable blinking */ - - regval = getreg32(STM32_LCD_FCR); - regval &= ~(LCD_FCR_BLINKF_MASK | LCD_FCR_BLINK_MASK); - regval |= (LCD_FCR_BLINK_DISABLE | LCD_FCR_BLINKF_DIV32); - putreg32(regval, STM32_LCD_FCR); - - slcd_dumpslcd("AFTER INITIALIZATION"); - - /* Register the LCD device driver */ - - ret = register_driver("/dev/slcd0", &g_slcdops, 0644, &g_slcdstate); - g_slcdstate.initialized = true; - - /* Then clear the display */ - - slcd_clear(); - slcd_dumpstate("AFTER INITIALIZATION"); - } - - return ret; -} - -#endif /* CONFIG_STM32_LCD */ diff --git a/boards/arm/stm32/stm32ldiscovery/src/stm32_pwm.c b/boards/arm/stm32/stm32ldiscovery/src/stm32_pwm.c deleted file mode 100644 index 3857da41ec48f..0000000000000 --- a/boards/arm/stm32/stm32ldiscovery/src/stm32_pwm.c +++ /dev/null @@ -1,127 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32ldiscovery/src/stm32_pwm.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include - -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32_pwm.h" -#include "stm32ldiscovery.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -/* PWM - * - * The stm32ldiscovery has no real on-board PWM devices, but the board can - * be configured to output a pulse train using TIM4 CH2. - * This pin is used by FSMC is connected to CN5 just for this purpose: - * - * PD13 FSMC_A18 / MC_TIM4_CH2OUT pin 33 (EnB) - * - * FSMC must be disabled in this case! - */ - -#define HAVE_PWM 1 - -#ifndef CONFIG_PWM -# undef HAVE_PWM -#endif - -#ifndef CONFIG_STM32_TIM4 -# undef HAVE_PWM -#endif - -#ifndef CONFIG_STM32_TIM4_PWM -# undef HAVE_PWM -#endif - -#if CONFIG_STM32_TIM4_CHANNEL != STM32F3DISCOVERY_PWMCHANNEL -# undef HAVE_PWM -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_pwm_setup - * - * Description: - * Initialize PWM and register the PWM device. - * - ****************************************************************************/ - -int stm32_pwm_setup(void) -{ -#ifdef HAVE_PWM - static bool initialized = false; - struct pwm_lowerhalf_s *pwm; - int ret; - - /* Have we already initialized? */ - - if (!initialized) - { - /* Call stm32_pwminitialize() to get an instance of the PWM interface */ - - pwm = stm32_pwminitialize(STM32F3DISCOVERY_PWMTIMER); - if (!pwm) - { - _err("ERROR: Failed to get the STM32 PWM lower half\n"); - return -ENODEV; - } - - /* Register the PWM driver at "/dev/pwm0" */ - - ret = pwm_register("/dev/pwm0", pwm); - if (ret < 0) - { - aerr("ERROR: pwm_register failed: %d\n", ret); - return ret; - } - - /* Now we are initialized */ - - initialized = true; - } - - return OK; -#else - return -ENODEV; -#endif -} diff --git a/boards/arm/stm32/stm32ldiscovery/src/stm32_spi.c b/boards/arm/stm32/stm32ldiscovery/src/stm32_spi.c deleted file mode 100644 index 7263febe7ea70..0000000000000 --- a/boards/arm/stm32/stm32ldiscovery/src/stm32_spi.c +++ /dev/null @@ -1,182 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32ldiscovery/src/stm32_spi.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include - -#include -#include - -#include "arm_internal.h" -#include "chip.h" -#include "stm32.h" -#include "stm32ldiscovery.h" - -#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || defined(CONFIG_STM32_SPI3) - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_spidev_initialize - * - * Description: - * Called to configure SPI chip select GPIO pins for the stm32ldiscovery - * board. - * - ****************************************************************************/ - -void weak_function stm32_spidev_initialize(void) -{ -#ifdef CONFIG_STM32_SPI1 - stm32_configgpio(GPIO_MEMS_CS); /* MEMS chip select */ - stm32_configgpio(GPIO_MEMS_INT1); /* MEMS interrupts */ - stm32_configgpio(GPIO_MEMS_INT2); -#endif -} - -/**************************************************************************** - * Name: stm32_spi1/2/3select and stm32_spi1/2/3status - * - * Description: - * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status - * must be provided by board-specific logic. They are implementations of - * the select and status methods of the SPI interface defined by struct - * spi_ops_s (see include/nuttx/spi/spi.h). All other methods - * (including stm32_spibus_initialize()) are provided by common STM32 logic. - * To use this common SPI logic on your board: - * - * 1. Provide logic in stm32_boardinitialize() to configure SPI chip select - * pins. - * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() functions - * in your board-specific logic. These functions will perform chip - * selection and status operations using GPIOs in the way your board is - * configured. - * 3. Add a calls to stm32_spibus_initialize() in your low level - * application initialization logic - * 4. The handle returned by stm32_spibus_initialize() may then be used to - * bind the SPI driver to higher level logic (e.g., calling - * mmcsd_spislotinitialize(), for example, will bind the SPI driver to - * the SPI MMC/SD driver). - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_SPI1 -void stm32_spi1select(struct spi_dev_s *dev, - uint32_t devid, bool selected) -{ - spiinfo("devid: %d CS: %s\n", - (int)devid, selected ? "assert" : "de-assert"); - - stm32_gpiowrite(GPIO_MEMS_CS, !selected); -} - -uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) -{ - return 0; -} -#endif - -#ifdef CONFIG_STM32_SPI2 -void stm32_spi2select(struct spi_dev_s *dev, - uint32_t devid, bool selected) -{ - spiinfo("devid: %d CS: %s\n", - (int)devid, selected ? "assert" : "de-assert"); -} - -uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) -{ - return 0; -} -#endif - -#ifdef CONFIG_STM32_SPI3 -void stm32_spi3select(struct spi_dev_s *dev, - uint32_t devid, bool selected) -{ - spiinfo("devid: %d CS: %s\n", - (int)devid, selected ? "assert" : "de-assert"); -} - -uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid) -{ - return 0; -} -#endif - -/**************************************************************************** - * Name: stm32_spi1cmddata - * - * Description: - * Set or clear the SH1101A A0 or SD1306 D/C n bit to select data (true) - * or command (false). This function must be provided by platform-specific - * logic. This is an implementation of the cmddata method of the SPI - * interface defined by struct spi_ops_s (see include/nuttx/spi/spi.h). - * - * Input Parameters: - * - * spi - SPI device that controls the bus the device that requires the CMD/ - * DATA selection. - * devid - If there are multiple devices on the bus, this selects which one - * to select cmd or data. NOTE: This design restricts, for example, - * one one SPI display per SPI bus. - * cmd - true: select command; false: select data - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef CONFIG_SPI_CMDDATA -#ifdef CONFIG_STM32_SPI1 -int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) -{ - return -ENODEV; -} -#endif - -#ifdef CONFIG_STM32_SPI2 -int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) -{ - return -ENODEV; -} -#endif - -#ifdef CONFIG_STM32_SPI3 -int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) -{ - return -ENODEV; -} -#endif -#endif /* CONFIG_SPI_CMDDATA */ - -#endif /* CONFIG_STM32_SPI1 || CONFIG_STM32_SPI2 */ diff --git a/boards/arm/stm32/stm32ldiscovery/src/stm32_userleds.c b/boards/arm/stm32/stm32ldiscovery/src/stm32_userleds.c deleted file mode 100644 index 362209fa5999b..0000000000000 --- a/boards/arm/stm32/stm32ldiscovery/src/stm32_userleds.c +++ /dev/null @@ -1,97 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32ldiscovery/src/stm32_userleds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include - -#include "chip.h" -#include "stm32.h" -#include "stm32ldiscovery.h" - -#ifndef CONFIG_ARCH_LEDS - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_userled_initialize - ****************************************************************************/ - -uint32_t board_userled_initialize(void) -{ - /* Configure LED1-2 GPIOs for output */ - - stm32_configgpio(GPIO_LED1); - stm32_configgpio(GPIO_LED2); - return BOARD_NLEDS; -} - -/**************************************************************************** - * Name: board_userled - ****************************************************************************/ - -void board_userled(int led, bool ledon) -{ - uint32_t ledcfg; - - if (led == BOARD_LED1) - { - ledcfg = GPIO_LED1; - } - else if (led == BOARD_LED2) - { - ledcfg = GPIO_LED2; - } - else - { - return; - } - - stm32_gpiowrite(ledcfg, ledon); -} - -/**************************************************************************** - * Name: board_userled_all - ****************************************************************************/ - -void board_userled_all(uint32_t ledset) -{ - bool ledon; - - ledon = ((ledset & BOARD_LED1_BIT) != 0); - stm32_gpiowrite(GPIO_LED1, ledon); - - ledon = ((ledset & BOARD_LED2_BIT) != 0); - stm32_gpiowrite(GPIO_LED2, ledon); -} - -#endif /* !CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/stm32vldiscovery/CMakeLists.txt b/boards/arm/stm32/stm32vldiscovery/CMakeLists.txt deleted file mode 100644 index 0b290a9db7311..0000000000000 --- a/boards/arm/stm32/stm32vldiscovery/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/stm32vldiscovery/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32/stm32vldiscovery/configs/nsh/defconfig b/boards/arm/stm32/stm32vldiscovery/configs/nsh/defconfig deleted file mode 100644 index 58ac9e12dae02..0000000000000 --- a/boards/arm/stm32/stm32vldiscovery/configs/nsh/defconfig +++ /dev/null @@ -1,58 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_DISABLE_ENVIRON is not set -# CONFIG_DISABLE_POSIX_TIMERS is not set -# CONFIG_NSH_DISABLEBG is not set -# CONFIG_NSH_DISABLESCRIPT is not set -# CONFIG_NSH_DISABLE_EXEC is not set -# CONFIG_NSH_DISABLE_EXIT is not set -# CONFIG_NSH_DISABLE_GET is not set -# CONFIG_NSH_DISABLE_IFCONFIG is not set -# CONFIG_NSH_DISABLE_LOSETUP is not set -# CONFIG_NSH_DISABLE_MKRD is not set -# CONFIG_NSH_DISABLE_PS is not set -# CONFIG_NSH_DISABLE_PUT is not set -# CONFIG_NSH_DISABLE_WGET is not set -# CONFIG_NSH_DISABLE_XD is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32vldiscovery" -CONFIG_ARCH_BOARD_STM32VL_DISCOVERY=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F100RB=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=2398 -CONFIG_BUILTIN=y -CONFIG_DEBUG_FULLOPT=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_DEFAULT_SMALL=y -CONFIG_IDLETHREAD_STACKSIZE=128 -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INIT_STACKSIZE=768 -CONFIG_INTELHEX_BINARY=y -CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=4 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_PTHREAD_STACK_DEFAULT=128 -CONFIG_PTHREAD_STACK_MIN=128 -CONFIG_RAM_SIZE=8192 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_STDIO_BUFFER_SIZE=0 -CONFIG_STM32_BKP=y -CONFIG_STM32_JTAG_FULL_ENABLE=y -CONFIG_STM32_PWR=y -CONFIG_STM32_RTC=y -CONFIG_STM32_USART1=y -CONFIG_SYMTAB_ORDEREDBYNAME=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART1_RXBUFSIZE=128 -CONFIG_USART1_SERIAL_CONSOLE=y -CONFIG_USART1_TXBUFSIZE=128 diff --git a/boards/arm/stm32/stm32vldiscovery/include/board.h b/boards/arm/stm32/stm32vldiscovery/include/board.h deleted file mode 100644 index 2d6b6419de449..0000000000000 --- a/boards/arm/stm32/stm32vldiscovery/include/board.h +++ /dev/null @@ -1,142 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32vldiscovery/include/board.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __BOARDS_ARM_STM32_STM32VLDISCOVERY_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32_STM32VLDISCOVERY_INCLUDE_BOARD_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#ifndef __ASSEMBLY__ -# include -#endif - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Clocking *****************************************************************/ - -/* On-board crystal frequency is 8MHz (HSE) */ - -#define STM32_BOARD_XTAL 8000000ul - -/* PLL source is HSE / 1, - * PLL multiplier is 3: PLL output frequency is 8MHz (XTAL) x 3 = 24MHz - */ - -#define STM32_CFGR2_PREDIV1 RCC_CFGR2_PREDIV1d1 -#define STM32_CFGR_PLLSRC RCC_CFGR_PLLSRC -#define STM32_CFGR_PLLXTPRE 0 -#define STM32_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx3 -#define STM32_PLL_FREQUENCY (3 * STM32_BOARD_XTAL) - -/* Use the PLL and set the SYSCLK source to be the PLL */ - -#define STM32_SYSCLK_SW RCC_CFGR_SW_PLL -#define STM32_SYSCLK_SWS RCC_CFGR_SWS_PLL -#define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY - -/* AHB clock (HCLK) is SYSCLK (24MHz) */ - -#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK -#define STM32_HCLK_FREQUENCY STM32_PLL_FREQUENCY - -/* APB2 clock (PCLK2) is HCLK (24MHz) */ - -#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK -#define STM32_PCLK2_FREQUENCY STM32_HCLK_FREQUENCY - -/* APB2 timers (1, 15-17) will receive PCLK2. */ - -#define STM32_APB2_TIM1_CLKIN STM32_PCLK2_FREQUENCY -#define STM32_APB2_TIM15_CLKIN STM32_PCLK2_FREQUENCY -#define STM32_APB2_TIM16_CLKIN STM32_PCLK2_FREQUENCY -#define STM32_APB2_TIM17_CLKIN STM32_PCLK2_FREQUENCY - -/* APB1 clock (PCLK1) is HCLK (24MHz) */ - -#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK -#define STM32_PCLK1_FREQUENCY STM32_HCLK_FREQUENCY - -/* APB1 timers (2-7, 12-14) will receive PCLK1. */ - -#define STM32_APB1_TIM2_CLKIN STM32_PCLK1_FREQUENCY -#define STM32_APB1_TIM3_CLKIN STM32_PCLK1_FREQUENCY -#define STM32_APB1_TIM4_CLKIN STM32_PCLK1_FREQUENCY -#define STM32_APB1_TIM5_CLKIN STM32_PCLK1_FREQUENCY -#define STM32_APB1_TIM6_CLKIN STM32_PCLK1_FREQUENCY -#define STM32_APB1_TIM7_CLKIN STM32_PCLK1_FREQUENCY -#define STM32_APB1_TIM12_CLKIN STM32_PCLK1_FREQUENCY -#define STM32_APB1_TIM13_CLKIN STM32_PCLK1_FREQUENCY -#define STM32_APB1_TIM14_CLKIN STM32_PCLK1_FREQUENCY - -/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx - * otherwise frequency is 2xAPBx. - * Note: TIM1,15-17 are on APB2, others on APB1 - */ - -#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM2_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM3_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM4_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM5_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM6_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM7_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY - -/* LED definitions **********************************************************/ - -/* It is assumed that a generic board has 1 LED. Thus only two different - * states can be shown. Statuses defined as "1" will light the LED, the - * ones defined as "0" will turn the LED off. - */ - -#define LED_STARTED 1 -#define LED_HEAPALLOCATE 1 -#define LED_IRQSENABLED 1 -#define LED_STACKCREATED 1 -#define LED_INIRQ 1 -#define LED_SIGNAL 1 -#define LED_ASSERTION 0 -#define LED_PANIC 0 - -/* Button definitions *******************************************************/ - -/* It is assumed that a generic board has 1 button. */ - -#define BUTTON_0 0 - -#define NUM_BUTTONS 1 - -#define BUTTON_0_BIT (1 << BUTTON_0) - -/* Alternate function pin selections ****************************************/ - -/* USART1 */ - -#define GPIO_USART1_TX GPIO_ADJUST_MODE(GPIO_USART1_TX_0, GPIO_MODE_50MHz) -#define GPIO_USART1_RX GPIO_USART1_RX_0 - -#endif /* __BOARDS_ARM_STM32_STM32VLDISCOVERY_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32/stm32vldiscovery/scripts/Make.defs b/boards/arm/stm32/stm32vldiscovery/scripts/Make.defs deleted file mode 100644 index aba039baff4c1..0000000000000 --- a/boards/arm/stm32/stm32vldiscovery/scripts/Make.defs +++ /dev/null @@ -1,41 +0,0 @@ -############################################################################ -# boards/arm/stm32/stm32vldiscovery/scripts/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/.config -include $(TOPDIR)/tools/Config.mk -include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs - -LDSCRIPT = stm32vldiscovery.ld -ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) - -ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 - -CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) -CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) -CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -AFLAGS := $(CFLAGS) -D__ASSEMBLY__ - -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections -LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32/stm32vldiscovery/src/CMakeLists.txt b/boards/arm/stm32/stm32vldiscovery/src/CMakeLists.txt deleted file mode 100644 index ee0a0879fcae5..0000000000000 --- a/boards/arm/stm32/stm32vldiscovery/src/CMakeLists.txt +++ /dev/null @@ -1,28 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/stm32vldiscovery/src/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -set(SRCS stm32_boot.c stm32_bringup.c stm32_leds.c stm32_buttons.c) - -target_sources(board PRIVATE ${SRCS}) - -set_property(GLOBAL PROPERTY LD_SCRIPT - "${NUTTX_BOARD_DIR}/scripts/stm32vldiscovery.ld") diff --git a/boards/arm/stm32/stm32vldiscovery/src/Make.defs b/boards/arm/stm32/stm32vldiscovery/src/Make.defs deleted file mode 100644 index 9eef1f9e16dac..0000000000000 --- a/boards/arm/stm32/stm32vldiscovery/src/Make.defs +++ /dev/null @@ -1,29 +0,0 @@ -############################################################################ -# boards/arm/stm32/stm32vldiscovery/src/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/Make.defs - -CSRCS = stm32_boot.c stm32_bringup.c stm32_leds.c stm32_buttons.c - -DEPPATH += --dep-path board -VPATH += :board -CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/stm32vldiscovery/src/stm32_boot.c b/boards/arm/stm32/stm32vldiscovery/src/stm32_boot.c deleted file mode 100644 index cbdbe7788a83a..0000000000000 --- a/boards/arm/stm32/stm32vldiscovery/src/stm32_boot.c +++ /dev/null @@ -1,82 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32vldiscovery/src/stm32_boot.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include -#include - -#include "arm_internal.h" -#include "stm32vldiscovery.h" - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_boardinitialize - * - * Description: - * All STM32 architectures must provide the following entry point. - * This entry point is called early in the initialization -- after all - * memory has been configured and mapped but before any devices have been - * initialized. - * - ****************************************************************************/ - -void stm32_boardinitialize(void) -{ - /* Configure on-board LEDs if LED support has been selected. */ - -#ifdef CONFIG_ARCH_LEDS - stm32_led_initialize(); -#endif -} - -/**************************************************************************** - * Name: board_late_initialize - * - * Description: - * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional - * initialization call will be performed in the boot-up sequence to a - * function called board_late_initialize(). board_late_initialize() will - * be called immediately after up_initialize() is called and just before - * the initial application is started. This additional initialization - * phase may be used, for example, to initialize board-specific device - * drivers. - * - ****************************************************************************/ - -#ifdef CONFIG_BOARD_LATE_INITIALIZE -void board_late_initialize(void) -{ - /* Perform board-specific initialization */ - - stm32_bringup(); -} -#endif diff --git a/boards/arm/stm32/stm32vldiscovery/src/stm32_bringup.c b/boards/arm/stm32/stm32vldiscovery/src/stm32_bringup.c deleted file mode 100644 index bf078df319d9b..0000000000000 --- a/boards/arm/stm32/stm32vldiscovery/src/stm32_bringup.c +++ /dev/null @@ -1,96 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32vldiscovery/src/stm32_bringup.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#ifdef CONFIG_FS_PROCFS -# include -#endif - -#ifdef CONFIG_INPUT_BUTTONS -# include -#endif - -#ifdef CONFIG_USERLED -# include -#endif - -#include "stm32.h" -#include "stm32vldiscovery.h" - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_bringup - * - * Description: - * Perform architecture-specific initialization - * - * CONFIG_BOARD_LATE_INITIALIZE=y : - * Called from board_late_initialize(). - * - ****************************************************************************/ - -int stm32_bringup(void) -{ - int ret = OK; - -#ifdef CONFIG_INPUT_BUTTONS - /* Register the BUTTON driver */ - - ret = btn_lower_initialize("/dev/buttons"); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: btn_lower_initialize() failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_USERLED - /* Register the LED driver */ - - ret = userled_lower_initialize("/dev/userleds"); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: userled_lower_initialize() failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_FS_PROCFS - /* Mount the procfs file system */ - - ret = nx_mount(NULL, "/proc", "procfs", 0, NULL); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: Failed to mount procfs at /proc: %d\n", ret); - } -#endif - - return ret; -} diff --git a/boards/arm/stm32/stm32vldiscovery/src/stm32_buttons.c b/boards/arm/stm32/stm32vldiscovery/src/stm32_buttons.c deleted file mode 100644 index e5e62a4fa3428..0000000000000 --- a/boards/arm/stm32/stm32vldiscovery/src/stm32_buttons.c +++ /dev/null @@ -1,111 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32vldiscovery/src/stm32_buttons.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include -#include - -#include "stm32vldiscovery.h" - -#ifdef CONFIG_ARCH_BUTTONS - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_button_initialize - * - * Description: - * board_button_initialize() must be called to initialize button resources. - * After that, board_buttons() may be called to collect the current state - * of all buttons or board_button_irq() may be called to register button - * interrupt handlers. - * - ****************************************************************************/ - -uint32_t board_button_initialize(void) -{ - stm32_configgpio(GPIO_BTN_0); /* Configure the GPIO pins as inputs. */ - return NUM_BUTTONS; -} - -/**************************************************************************** - * Name: board_buttons - ****************************************************************************/ - -uint32_t board_buttons(void) -{ - uint32_t ret = 0; - - ret = (stm32_gpioread(GPIO_BTN_0) == false ? 1 : 0); - - return ret; -} - -/**************************************************************************** - * Button support. - * - * Description: - * board_button_initialize() must be called to initialize button resources. - * After that, board_buttons() may be called to collect the current state - * of all buttons or board_button_irq() may be called to register button - * interrupt handlers. - * - * After board_button_initialize() has been called, board_buttons() may be - * called to collect the state of all buttons. board_buttons() returns an - * 32-bit bit set with each bit associated with a button. See the - * BUTTON_*_BIT and JOYSTICK_*_BIT definitions in board.h for the meaning - * of each bit. - * - * board_button_irq() may be called to register an interrupt handler that - * will be called when a button is depressed or released. The ID value is a - * button enumeration value that uniquely identifies a button resource. See - * the BUTTON_* and JOYSTICK_* definitions in board.h for the meaning of - * enumeration value. - * - ****************************************************************************/ - -#ifdef CONFIG_ARCH_IRQBUTTONS -int board_button_irq(int id, xcpt_t irqhandler, void *arg) -{ - int ret = -EINVAL; - - if (id == 0) - { - ret = stm32_gpiosetevent(GPIO_BTN_0, true, true, true, - irqhandler, arg); - } - - return ret; -} -#endif -#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/stm32/stm32vldiscovery/src/stm32_leds.c b/boards/arm/stm32/stm32vldiscovery/src/stm32_leds.c deleted file mode 100644 index 0bb0c88732a86..0000000000000 --- a/boards/arm/stm32/stm32vldiscovery/src/stm32_leds.c +++ /dev/null @@ -1,79 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32vldiscovery/src/stm32_leds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32.h" -#include "stm32vldiscovery.h" - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_led_initialize - ****************************************************************************/ - -#ifdef CONFIG_ARCH_LEDS -void stm32_led_initialize(void) -{ - stm32_configgpio(GPIO_LED1); /* Configure LED1 GPIO for output */ -} - -/**************************************************************************** - * Name: board_autoled_on - ****************************************************************************/ - -void board_autoled_on(int led) -{ - if (led == 1) - { - stm32_gpiowrite(GPIO_LED1, true); - } -} - -/**************************************************************************** - * Name: board_autoled_off - ****************************************************************************/ - -void board_autoled_off(int led) -{ - if (led == 0) - { - stm32_gpiowrite(GPIO_LED1, false); - } -} - -#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/viewtool-stm32f107/CMakeLists.txt b/boards/arm/stm32/viewtool-stm32f107/CMakeLists.txt deleted file mode 100644 index 4fc77f37f5d26..0000000000000 --- a/boards/arm/stm32/viewtool-stm32f107/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/viewtool-stm32f107/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32/viewtool-stm32f107/configs/ft80x/defconfig b/boards/arm/stm32/viewtool-stm32f107/configs/ft80x/defconfig deleted file mode 100644 index f952c3ca348eb..0000000000000 --- a/boards/arm/stm32/viewtool-stm32f107/configs/ft80x/defconfig +++ /dev/null @@ -1,43 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="viewtool-stm32f107" -CONFIG_ARCH_BOARD_VIEWTOOL_STM32F107=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F107VC=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=5483 -CONFIG_BUILTIN=y -CONFIG_EXAMPLES_FT80X=y -CONFIG_FS_PROCFS=y -CONFIG_HOST_WINDOWS=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LCD=y -CONFIG_LCD_FT80X=y -CONFIG_LCD_FT80X_AUDIO_GPIOSHUTDOWN=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=65536 -CONFIG_RAM_START=0x20000000 -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORKPRIORITY=192 -CONFIG_SCHED_HPWORKSTACKSIZE=1024 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=24 -CONFIG_START_MONTH=2 -CONFIG_STM32_JTAG_FULL_ENABLE=y -CONFIG_STM32_PWR=y -CONFIG_STM32_SPI1=y -CONFIG_STM32_USART1=y -CONFIG_SYSTEM_NSH=y -CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/viewtool-stm32f107/configs/highpri/defconfig b/boards/arm/stm32/viewtool-stm32f107/configs/highpri/defconfig deleted file mode 100644 index 817e9d62fd4f3..0000000000000 --- a/boards/arm/stm32/viewtool-stm32f107/configs/highpri/defconfig +++ /dev/null @@ -1,38 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="viewtool-stm32f107" -CONFIG_ARCH_BOARD_VIEWTOOL_STM32F107=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F103VC=y -CONFIG_ARCH_HIPRI_INTERRUPT=y -CONFIG_ARCH_RAMVECTORS=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=5483 -CONFIG_HOST_WINDOWS=y -CONFIG_INIT_ENTRYPOINT="highpri_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=65536 -CONFIG_RAM_START=0x20000000 -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_HPWORKPRIORITY=192 -CONFIG_SCHED_HPWORKSTACKSIZE=1024 -CONFIG_START_DAY=22 -CONFIG_START_MONTH=12 -CONFIG_START_YEAR=2013 -CONFIG_STM32_JTAG_FULL_ENABLE=y -CONFIG_STM32_PWR=y -CONFIG_STM32_TIM6=y -CONFIG_STM32_USART1=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART1_SERIAL_CONSOLE=y -CONFIG_VIEWTOOL_HIGHPRI=y diff --git a/boards/arm/stm32/viewtool-stm32f107/configs/netnsh/defconfig b/boards/arm/stm32/viewtool-stm32f107/configs/netnsh/defconfig deleted file mode 100644 index 083ecf7359a96..0000000000000 --- a/boards/arm/stm32/viewtool-stm32f107/configs/netnsh/defconfig +++ /dev/null @@ -1,71 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="viewtool-stm32f107" -CONFIG_ARCH_BOARD_VIEWTOOL_STM32F107=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F107VC=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=5483 -CONFIG_BUILTIN=y -CONFIG_ETH0_PHY_DP83848C=y -CONFIG_FS_PROCFS=y -CONFIG_HOST_WINDOWS=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_IOB_NBUFFERS=24 -CONFIG_LIBC_HOSTNAME="Viewtool-STM32F107" -CONFIG_NET=y -CONFIG_NETDB_DNSCLIENT=y -CONFIG_NETDB_DNSSERVER_NOADDR=y -CONFIG_NETINIT_NOMAC=y -CONFIG_NETINIT_THREAD=y -CONFIG_NETUTILS_DHCPC=y -CONFIG_NETUTILS_TELNETD=y -CONFIG_NETUTILS_TFTPC=y -CONFIG_NETUTILS_WEBCLIENT=y -CONFIG_NET_BROADCAST=y -CONFIG_NET_ICMP_SOCKET=y -CONFIG_NET_ICMPv6=y -CONFIG_NET_ICMPv6_NEIGHBOR=y -CONFIG_NET_ICMPv6_SOCKET=y -CONFIG_NET_IPv6=y -CONFIG_NET_MAX_LISTENPORTS=40 -CONFIG_NET_ROUTE=y -CONFIG_NET_TCP=y -CONFIG_NET_TCP_PREALLOC_CONNS=40 -CONFIG_NET_TCP_WRITE_BUFFERS=y -CONFIG_NET_UDP=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=65536 -CONFIG_RAM_START=0x20000000 -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_HPWORKPRIORITY=192 -CONFIG_SCHED_HPWORKSTACKSIZE=1024 -CONFIG_START_DAY=23 -CONFIG_STM32_ETHMAC=y -CONFIG_STM32_JTAG_FULL_ENABLE=y -CONFIG_STM32_PHYSR=16 -CONFIG_STM32_PHYSR_100MBPS=0x0000 -CONFIG_STM32_PHYSR_FULLDUPLEX=0x0004 -CONFIG_STM32_PHYSR_MODE=0x0004 -CONFIG_STM32_PHYSR_SPEED=0x0002 -CONFIG_STM32_PWR=y -CONFIG_STM32_RMII_EXTCLK=y -CONFIG_STM32_USART1=y -CONFIG_SYSTEM_NSH=y -CONFIG_SYSTEM_PING6=y -CONFIG_SYSTEM_PING=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/viewtool-stm32f107/configs/nsh/defconfig b/boards/arm/stm32/viewtool-stm32f107/configs/nsh/defconfig deleted file mode 100644 index b68528e2301f8..0000000000000 --- a/boards/arm/stm32/viewtool-stm32f107/configs/nsh/defconfig +++ /dev/null @@ -1,40 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="viewtool-stm32f107" -CONFIG_ARCH_BOARD_VIEWTOOL_STM32F107=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F107VC=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=5483 -CONFIG_BUILTIN=y -CONFIG_FS_PROCFS=y -CONFIG_HOST_WINDOWS=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=65536 -CONFIG_RAM_START=0x20000000 -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_HPWORKPRIORITY=192 -CONFIG_SCHED_HPWORKSTACKSIZE=1024 -CONFIG_START_DAY=21 -CONFIG_START_MONTH=9 -CONFIG_START_YEAR=2009 -CONFIG_STM32_JTAG_FULL_ENABLE=y -CONFIG_STM32_PWR=y -CONFIG_STM32_USART1=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/viewtool-stm32f107/configs/tcpblaster/defconfig b/boards/arm/stm32/viewtool-stm32f107/configs/tcpblaster/defconfig deleted file mode 100644 index 1e3c72298e85f..0000000000000 --- a/boards/arm/stm32/viewtool-stm32f107/configs/tcpblaster/defconfig +++ /dev/null @@ -1,62 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="viewtool-stm32f107" -CONFIG_ARCH_BOARD_VIEWTOOL_STM32F107=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F107VC=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=5483 -CONFIG_BUILTIN=y -CONFIG_ETH0_PHY_DP83848C=y -CONFIG_EXAMPLES_TCPBLASTER=y -CONFIG_FS_PROCFS=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_IOB_NBUFFERS=50 -CONFIG_IOB_NCHAINS=12 -CONFIG_LIBC_HOSTNAME="Viewtool-STM32F107" -CONFIG_LIBM=y -CONFIG_NET=y -CONFIG_NETINIT_NOMAC=y -CONFIG_NETINIT_THREAD=y -CONFIG_NETUTILS_TELNETD=y -CONFIG_NET_ETH_PKTSIZE=1514 -CONFIG_NET_ICMP_SOCKET=y -CONFIG_NET_MAX_LISTENPORTS=40 -CONFIG_NET_ROUTE=y -CONFIG_NET_SOCKOPTS=y -CONFIG_NET_STATISTICS=y -CONFIG_NET_TCP=y -CONFIG_NET_TCP_PREALLOC_CONNS=40 -CONFIG_NET_TCP_WRITE_BUFFERS=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=65536 -CONFIG_RAM_START=0x20000000 -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_LPWORK=y -CONFIG_SCHED_LPWORKPRIORITY=120 -CONFIG_START_DAY=23 -CONFIG_STM32_ETHMAC=y -CONFIG_STM32_JTAG_FULL_ENABLE=y -CONFIG_STM32_PHYSR=16 -CONFIG_STM32_PHYSR_100MBPS=0x0000 -CONFIG_STM32_PHYSR_FULLDUPLEX=0x0004 -CONFIG_STM32_PHYSR_MODE=0x0004 -CONFIG_STM32_PHYSR_SPEED=0x0002 -CONFIG_STM32_PWR=y -CONFIG_STM32_RMII_EXTCLK=y -CONFIG_STM32_USART1=y -CONFIG_SYSTEM_NSH=y -CONFIG_SYSTEM_PING=y -CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/viewtool-stm32f107/include/board.h b/boards/arm/stm32/viewtool-stm32f107/include/board.h deleted file mode 100644 index 28494c647ccc1..0000000000000 --- a/boards/arm/stm32/viewtool-stm32f107/include/board.h +++ /dev/null @@ -1,166 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/viewtool-stm32f107/include/board.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __BOARDS_ARM_STM32_VIEWTOOL_STM32F107_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32_VIEWTOOL_STM32F107_INCLUDE_BOARD_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#ifndef __ASSEMBLY__ -# include -#endif - -/* Clocking *****************************************************************/ - -#if defined(CONFIG_ARCH_CHIP_STM32F107VC) -# include -#elif defined(CONFIG_ARCH_CHIP_STM32F103VC) -# include -#else -# error Unrecognized STM32 chip -#endif - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* LED definitions **********************************************************/ - -/* There are four LEDs on the ViewTool STM32F103/F107 board that can be - * controlled by software: LED1 through LED4. All pulled high and can be - * illuminated by driving the output to low - * - * LED1 PA6 - * LED2 PA7 - * LED3 PB12 - * LED4 PB13 - */ - -/* LED index values for use with board_userled() */ - -#define BOARD_LED1 0 -#define BOARD_LED2 1 -#define BOARD_LED3 2 -#define BOARD_LED4 3 -#define BOARD_NLEDS 4 - -/* LED bits for use with board_userled_all() */ - -#define BOARD_LED1_BIT (1 << BOARD_LED1) -#define BOARD_LED2_BIT (1 << BOARD_LED2) -#define BOARD_LED3_BIT (1 << BOARD_LED3) -#define BOARD_LED4_BIT (1 << BOARD_LED4) - -/* These LEDs are not used by the board port unless CONFIG_ARCH_LEDS is - * defined. In that case, the usage by the board port is defined in - * include/board.h and src/stm32_leds.c. The LEDs are used to encode - * OS-related events as follows: - * - * SYMBOL Val Meaning LED state - * LED1 LED2 LED3 LED4 - * ----------------- --- ----------------------- ---- ---- ---- ---- - */ -#define LED_STARTED 0 /* NuttX has been started ON OFF OFF OFF */ -#define LED_HEAPALLOCATE 1 /* Heap has been allocated OFF ON OFF OFF */ -#define LED_IRQSENABLED 2 /* Interrupts enabled ON ON OFF OFF */ -#define LED_STACKCREATED 3 /* Idle stack created OFF OFF ON OFF */ -#define LED_INIRQ 4 /* In an interrupt N/C N/C N/C GLOW */ -#define LED_SIGNAL 4 /* In a signal handler N/C N/C N/C GLOW */ -#define LED_ASSERTION 4 /* An assertion failed N/C N/C N/C GLOW */ -#define LED_PANIC 4 /* The system has crashed N/C N/C N/C FLASH */ -#undef LED_IDLE /* MCU is in sleep mode Not used */ - -/* After booting, LED1-3 are not longer used by the system and can be used - * for other purposes by the application (Of course, all LEDs are available - * to the application if CONFIG_ARCH_LEDS is not defined. - */ - -/* Buttons ******************************************************************/ - -/* All pulled high and will be sensed low when depressed. - * - * SW2 PC11 Needs J42 closed - * SW3 PC12 Needs J43 closed - * SW4 PA0 Needs J44 closed - */ - -#define BUTTON_SW2 0 -#define BUTTON_SW3 1 -#define BUTTON_SW4 2 -#define NUM_BUTTONS 3 - -#define BUTTON_SW2_BIT (1 << BUTTON_SW2) -#define BUTTON_SW3_BIT (1 << BUTTON_SW3) -#define BUTTON_SW4_BIT (1 << BUTTON_SW4) - -/* Alternate function pin selections (auto-aliased for new pinmap) */ - -/* USART1 */ - -#define GPIO_USART1_TX GPIO_ADJUST_MODE(GPIO_USART1_TX_0, GPIO_MODE_50MHz) -#define GPIO_USART1_RX GPIO_USART1_RX_0 - -/* SPI1 */ - -#define GPIO_SPI1_NSS GPIO_ADJUST_MODE(GPIO_SPI1_NSS_0, GPIO_MODE_50MHz) -#define GPIO_SPI1_SCK GPIO_ADJUST_MODE(GPIO_SPI1_SCK_0, GPIO_MODE_50MHz) -#define GPIO_SPI1_MISO GPIO_ADJUST_MODE(GPIO_SPI1_MISO_0, GPIO_MODE_50MHz) -#define GPIO_SPI1_MOSI GPIO_ADJUST_MODE(GPIO_SPI1_MOSI_0, GPIO_MODE_50MHz) - -/* MCO */ - -#define GPIO_MCO GPIO_ADJUST_MODE(GPIO_MCO_0, GPIO_MODE_50MHz) - -/* Ethernet (MII/RMII) */ - -#define GPIO_ETH_MDC GPIO_ADJUST_MODE(GPIO_ETH_MDC_0, GPIO_MODE_50MHz) -#define GPIO_ETH_MDIO GPIO_ADJUST_MODE(GPIO_ETH_MDIO_0, GPIO_MODE_50MHz) -#define GPIO_ETH_MII_COL GPIO_ETH_MII_COL_0 -#define GPIO_ETH_MII_CRS GPIO_ETH_MII_CRS_0 -#define GPIO_ETH_MII_RX_CLK GPIO_ETH_MII_RX_CLK_0 -#define GPIO_ETH_MII_RXD0 GPIO_ETH_MII_RXD0_0 -#define GPIO_ETH_MII_RXD1 GPIO_ETH_MII_RXD1_0 -#define GPIO_ETH_MII_RXD2 GPIO_ETH_MII_RXD2_0 -#define GPIO_ETH_MII_RXD3 GPIO_ETH_MII_RXD3_0 -#define GPIO_ETH_MII_RX_DV GPIO_ETH_MII_RX_DV_0 -#define GPIO_ETH_MII_RX_ER GPIO_ETH_MII_RX_ER_0 -#define GPIO_ETH_MII_TX_CLK GPIO_ETH_MII_TX_CLK_0 -#define GPIO_ETH_MII_TXD0 GPIO_ADJUST_MODE(GPIO_ETH_MII_TXD0_0, GPIO_MODE_50MHz) -#define GPIO_ETH_MII_TXD1 GPIO_ADJUST_MODE(GPIO_ETH_MII_TXD1_0, GPIO_MODE_50MHz) -#define GPIO_ETH_MII_TXD2 GPIO_ADJUST_MODE(GPIO_ETH_MII_TXD2_0, GPIO_MODE_50MHz) -#define GPIO_ETH_MII_TXD3 GPIO_ADJUST_MODE(GPIO_ETH_MII_TXD3_0, GPIO_MODE_50MHz) -#define GPIO_ETH_MII_TX_EN GPIO_ADJUST_MODE(GPIO_ETH_MII_TX_EN_0, GPIO_MODE_50MHz) -#define GPIO_ETH_RMII_CRS_DV GPIO_ETH_RMII_CRS_DV_0 -#define GPIO_ETH_RMII_REF_CLK GPIO_ETH_RMII_REF_CLK_0 -#define GPIO_ETH_RMII_RXD0 GPIO_ETH_RMII_RXD0_0 -#define GPIO_ETH_RMII_RXD1 GPIO_ETH_RMII_RXD1_0 -#define GPIO_ETH_RMII_TXD0 GPIO_ADJUST_MODE(GPIO_ETH_RMII_TXD0_0, GPIO_MODE_50MHz) -#define GPIO_ETH_RMII_TXD1 GPIO_ADJUST_MODE(GPIO_ETH_RMII_TXD1_0, GPIO_MODE_50MHz) -#define GPIO_ETH_RMII_TX_EN GPIO_ADJUST_MODE(GPIO_ETH_RMII_TX_EN_0, GPIO_MODE_50MHz) - -/* TIM6 has no GPIO pins (basic timer) */ - -#endif /* __BOARDS_ARM_STM32_VIEWTOOL_STM32F107_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32/viewtool-stm32f107/scripts/Make.defs b/boards/arm/stm32/viewtool-stm32f107/scripts/Make.defs deleted file mode 100644 index 1aa5da98b3fde..0000000000000 --- a/boards/arm/stm32/viewtool-stm32f107/scripts/Make.defs +++ /dev/null @@ -1,46 +0,0 @@ -############################################################################ -# boards/arm/stm32/viewtool-stm32f107/scripts/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/.config -include $(TOPDIR)/tools/Config.mk -include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs - -ifeq ($(CONFIG_STM32_DFU),y) - LDSCRIPT = dfu.ld -else - LDSCRIPT = flash.ld -endif - -ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) - -ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 - -CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) -CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) -CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -AFLAGS := $(CFLAGS) -D__ASSEMBLY__ - -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-gotoff.ld -no-check-sections -LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32/viewtool-stm32f107/scripts/dfu.ld b/boards/arm/stm32/viewtool-stm32f107/scripts/dfu.ld deleted file mode 100644 index 8dda638806342..0000000000000 --- a/boards/arm/stm32/viewtool-stm32f107/scripts/dfu.ld +++ /dev/null @@ -1,118 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/viewtool-stm32f107/scripts/dfu.ld - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -MEMORY -{ - flash (rx) : ORIGIN = 0x08003000, LENGTH = 208K - sram (rwx) : ORIGIN = 0x20000000, LENGTH = 64K -} - -OUTPUT_ARCH(arm) -EXTERN(_vectors) -ENTRY(_stext) -SECTIONS -{ - .text : { - _stext = ABSOLUTE(.); - *(.vectors) - *(.text .text.*) - *(.fixup) - *(.gnu.warning) - *(.rodata .rodata.*) - *(.gnu.linkonce.t.*) - *(.glue_7) - *(.glue_7t) - *(.got) - *(.gcc_except_table) - *(.gnu.linkonce.r.*) - _etext = ABSOLUTE(.); - } > flash - - .init_section : { - _sinit = ABSOLUTE(.); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) - KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) - _einit = ABSOLUTE(.); - } > flash - - .ARM.extab : { - *(.ARM.extab*) - } > flash - - __exidx_start = ABSOLUTE(.); - .ARM.exidx : { - *(.ARM.exidx*) - } > flash - __exidx_end = ABSOLUTE(.); - - .tdata : { - _stdata = ABSOLUTE(.); - *(.tdata .tdata.* .gnu.linkonce.td.*); - _etdata = ABSOLUTE(.); - } > flash - - .tbss : { - _stbss = ABSOLUTE(.); - *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); - _etbss = ABSOLUTE(.); - } > flash - - _eronly = ABSOLUTE(.); - - /* The RAM vector table (if present) should lie at the beginning of SRAM */ - - .ram_vectors : { - *(.ram_vectors) - } > sram - - .data : { - _sdata = ABSOLUTE(.); - *(.data .data.*) - *(.gnu.linkonce.d.*) - CONSTRUCTORS - . = ALIGN(4); - _edata = ABSOLUTE(.); - } > sram AT > flash - - .bss : { - _sbss = ABSOLUTE(.); - *(.bss .bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - . = ALIGN(8); - _ebss = ABSOLUTE(.); - } > sram - - /* Stabs debugging sections. */ - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_info 0 : { *(.debug_info) } - .debug_line 0 : { *(.debug_line) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_aranges 0 : { *(.debug_aranges) } -} diff --git a/boards/arm/stm32/viewtool-stm32f107/scripts/flash.ld b/boards/arm/stm32/viewtool-stm32f107/scripts/flash.ld deleted file mode 100644 index 5cd741cedc89c..0000000000000 --- a/boards/arm/stm32/viewtool-stm32f107/scripts/flash.ld +++ /dev/null @@ -1,118 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/viewtool-stm32f107/scripts/flash.ld - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -MEMORY -{ - flash (rx) : ORIGIN = 0x08000000, LENGTH = 256K - sram (rwx) : ORIGIN = 0x20000000, LENGTH = 64K -} - -OUTPUT_ARCH(arm) -EXTERN(_vectors) -ENTRY(_stext) -SECTIONS -{ - .text : { - _stext = ABSOLUTE(.); - *(.vectors) - *(.text .text.*) - *(.fixup) - *(.gnu.warning) - *(.rodata .rodata.*) - *(.gnu.linkonce.t.*) - *(.glue_7) - *(.glue_7t) - *(.got) - *(.gcc_except_table) - *(.gnu.linkonce.r.*) - _etext = ABSOLUTE(.); - } > flash - - .init_section : { - _sinit = ABSOLUTE(.); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) - KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) - _einit = ABSOLUTE(.); - } > flash - - .ARM.extab : { - *(.ARM.extab*) - } > flash - - __exidx_start = ABSOLUTE(.); - .ARM.exidx : { - *(.ARM.exidx*) - } > flash - __exidx_end = ABSOLUTE(.); - - .tdata : { - _stdata = ABSOLUTE(.); - *(.tdata .tdata.* .gnu.linkonce.td.*); - _etdata = ABSOLUTE(.); - } > flash - - .tbss : { - _stbss = ABSOLUTE(.); - *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); - _etbss = ABSOLUTE(.); - } > flash - - _eronly = ABSOLUTE(.); - - /* The RAM vector table (if present) should lie at the beginning of SRAM */ - - .ram_vectors : { - *(.ram_vectors) - } > sram - - .data : { - _sdata = ABSOLUTE(.); - *(.data .data.*) - *(.gnu.linkonce.d.*) - CONSTRUCTORS - . = ALIGN(4); - _edata = ABSOLUTE(.); - } > sram AT > flash - - .bss : { - _sbss = ABSOLUTE(.); - *(.bss .bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - . = ALIGN(8); - _ebss = ABSOLUTE(.); - } > sram - - /* Stabs debugging sections. */ - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_info 0 : { *(.debug_info) } - .debug_line 0 : { *(.debug_line) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_aranges 0 : { *(.debug_aranges) } -} diff --git a/boards/arm/stm32/viewtool-stm32f107/src/CMakeLists.txt b/boards/arm/stm32/viewtool-stm32f107/src/CMakeLists.txt deleted file mode 100644 index c994fa4536ce5..0000000000000 --- a/boards/arm/stm32/viewtool-stm32f107/src/CMakeLists.txt +++ /dev/null @@ -1,79 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/viewtool-stm32f107/src/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -set(SRCS stm32_boot.c stm32_bringup.c stm32_leds.c stm32_spi.c) - -if(CONFIG_STM32_CAN_CHARDRIVER) - list(APPEND SRCS stm32_can.c) -endif() - -if(CONFIG_MMCSD) - list(APPEND SRCS stm32_mmcsd.c) -endif() - -if(CONFIG_STM32_OTGFS) - list(APPEND SRCS stm32_usbdev.c) -else() - if(CONFIG_STM32_USB) - list(APPEND SRCS stm32_usbdev.c) - endif() -endif() - -if(CONFIG_INPUT_ADS7843E) - list(APPEND SRCS stm32_ads7843e.c) -endif() - -if(CONFIG_LCD_SSD1289) - list(APPEND SRCS stm32_ssd1289.c) -endif() - -if(CONFIG_USBMSC) - list(APPEND SRCS stm32_usbmsc.c) -endif() - -if(CONFIG_ARCH_BUTTONS) - list(APPEND SRCS stm32_buttons.c) -endif() - -if(CONFIG_VIEWTOOL_HIGHPRI) - list(APPEND SRCS stm32_highpri.c) -endif() - -if(CONFIG_VIEWTOOL_FT80X_SPI1) - list(APPEND SRCS stm32_ft80x.c) -elseif(CONFIG_VIEWTOOL_FT80X_SPI2) - list(APPEND SRCS stm32_ft80x.c) -endif() - -if(CONFIG_VIEWTOOL_MAX3421E_SPI1) - list(APPEND SRCS stm32_max3421e.c) -elseif(CONFIG_VIEWTOOL_MAX3421E_SPI2) - list(APPEND SRCS stm32_max3421e.c) -endif() - -target_sources(board PRIVATE ${SRCS}) - -if(CONFIG_STM32_DFU) - set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/dfu.ld") -else() - set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/flash.ld") -endif() diff --git a/boards/arm/stm32/viewtool-stm32f107/src/Make.defs b/boards/arm/stm32/viewtool-stm32f107/src/Make.defs deleted file mode 100644 index 260a9270b30a2..0000000000000 --- a/boards/arm/stm32/viewtool-stm32f107/src/Make.defs +++ /dev/null @@ -1,77 +0,0 @@ -############################################################################ -# boards/arm/stm32/viewtool-stm32f107/src/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/Make.defs - -CSRCS = stm32_boot.c stm32_bringup.c stm32_leds.c stm32_spi.c - -ifeq ($(CONFIG_STM32_CAN_CHARDRIVER),y) -CSRCS += stm32_can.c -endif - -ifeq ($(CONFIG_MMCSD),y) -CSRCS += stm32_mmcsd.c -endif - -ifeq ($(CONFIG_STM32_OTGFS),y) # F107 -CSRCS += stm32_usbdev.c -else -ifeq ($(CONFIG_STM32_USB),y) # F103 -CSRCS += stm32_usbdev.c -endif -endif - -ifeq ($(CONFIG_INPUT_ADS7843E),y) # F103 -CSRCS += stm32_ads7843e.c -endif - -ifeq ($(CONFIG_LCD_SSD1289),y) # F103 -CSRCS += stm32_ssd1289.c -endif - -ifeq ($(CONFIG_USBMSC),y) -CSRCS += stm32_usbmsc.c -endif - -ifeq ($(CONFIG_ARCH_BUTTONS),y) -CSRCS += stm32_buttons.c -endif - -ifeq ($(CONFIG_VIEWTOOL_HIGHPRI),y) -CSRCS += stm32_highpri.c -endif - -ifeq ($(CONFIG_VIEWTOOL_FT80X_SPI1),y) -CSRCS += stm32_ft80x.c -else ifeq ($(CONFIG_VIEWTOOL_FT80X_SPI2),y) -CSRCS += stm32_ft80x.c -endif - -ifeq ($(CONFIG_VIEWTOOL_MAX3421E_SPI1),y) -CSRCS += stm32_max3421e.c -else ifeq ($(CONFIG_VIEWTOOL_MAX3421E_SPI2),y) -CSRCS += stm32_max3421e.c -endif - -DEPPATH += --dep-path board -VPATH += :board -CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/viewtool-stm32f107/src/stm32_boot.c b/boards/arm/stm32/viewtool-stm32f107/src/stm32_boot.c deleted file mode 100644 index c7eada920982f..0000000000000 --- a/boards/arm/stm32/viewtool-stm32f107/src/stm32_boot.c +++ /dev/null @@ -1,99 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/viewtool-stm32f107/src/stm32_boot.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include -#include - -#include "arm_internal.h" -#include "viewtool_stm32f107.h" - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_boardinitialize - * - * Description: - * All STM32 architectures must provide the following entry point. This - * entry point is called early in the initialization -- after all memory - * has been configured and mapped but before any devices have been - * initialized. - * - ****************************************************************************/ - -void stm32_boardinitialize(void) -{ - /* Configure SPI chip selects if 1) SPI is not disabled, and 2) the weak - * function stm32_spidev_initialize() has been brought into the link. - */ - -#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || defined(CONFIG_STM32_SPI3) - if (stm32_spidev_initialize) - { - stm32_spidev_initialize(); - } -#endif - - /* Initialize USB is 1) USBDEV is selected, 2) the USB controller is not - * disabled, and 3) the weak function stm32_usbdev_initialize() has been - * brought into the build. - */ - -#if defined(CONFIG_STM32_OTGFS) && defined(CONFIG_USBDEV) - if (stm32_usbdev_initialize) - { - stm32_usbdev_initialize(); - } -#endif - - /* Configure on-board LEDs (unconditionally). */ - - stm32_led_initialize(); -} - -/**************************************************************************** - * Name: board_late_initialize - * - * Description: - * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional - * initialization call will be performed in the boot-up sequence to a - * function called board_late_initialize(). board_late_initialize() will be - * called immediately after up_initialize() is called and just before the - * initial application is started. This additional initialization phase - * may be used, for example, to initialize board-specific device drivers. - * - ****************************************************************************/ - -#ifdef CONFIG_BOARD_LATE_INITIALIZE -void board_late_initialize(void) -{ - /* Perform board-specific initialization */ - - stm32_bringup(); -} -#endif diff --git a/boards/arm/stm32/viewtool-stm32f107/src/stm32_bringup.c b/boards/arm/stm32/viewtool-stm32f107/src/stm32_bringup.c deleted file mode 100644 index c9cfd7c659111..0000000000000 --- a/boards/arm/stm32/viewtool-stm32f107/src/stm32_bringup.c +++ /dev/null @@ -1,202 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/viewtool-stm32f107/src/stm32_bringup.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#ifdef CONFIG_RTC_DRIVER -# include -# include "stm32_rtc.h" -#endif - -#include "viewtool_stm32f107.h" - -#ifdef CONFIG_SENSORS_MPL115A -#include "stm32_mpl115a.h" -#endif - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -/* Default MMC/SD SLOT number */ - -#ifdef HAVE_MMCSD -# if defined(CONFIG_NSH_MMCSDSLOTNO) && CONFIG_NSH_MMCSDSLOTNO != VIEWTOOL_MMCSD_SLOTNO -# error "Only one MMC/SD slot: VIEWTOOL_MMCSD_SLOTNO" -# undef CONFIG_NSH_MMCSDSLOTNO -# define CONFIG_NSH_MMCSDSLOTNO VIEWTOOL_MMCSD_SLOTNO -# endif - -# ifndef CONFIG_NSH_MMCSDSLOTNO -# define CONFIG_NSH_MMCSDSLOTNO VIEWTOOL_MMCSD_SLOTNO -# endif -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: rtc_driver_initialize - * - * Description: - * Initialize and register the RTC driver. - * - ****************************************************************************/ - -#ifdef HAVE_RTC_DRIVER -static int rtc_driver_initialize(void) -{ - struct rtc_lowerhalf_s *lower; - int ret; - - /* Instantiate the STM32 lower-half RTC driver */ - - lower = stm32_rtc_lowerhalf(); - if (lower == NULL) - { - serr("ERROR: Failed to instantiate the RTC lower-half driver\n"); - ret = -ENOMEM; - } - else - { - /* Bind the lower half driver and register the combined RTC driver - * as /dev/rtc0 - */ - - ret = rtc_initialize(0, lower); - if (ret < 0) - { - serr("ERROR: Failed to bind/register the RTC driver: %d\n", ret); - } - } - - return ret; -} -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_bringup - * - * Description: - * Perform architecture-specific initialization - * - * CONFIG_BOARD_LATE_INITIALIZE=y : - * Called from board_late_initialize(). - * - ****************************************************************************/ - -int stm32_bringup(void) -{ - int ret; - -#ifdef HAVE_RTC_DRIVER - ret = rtc_driver_initialize(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: rtc_driver_initialize failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_FS_PROCFS - /* Mount the procfs file system */ - - ret = nx_mount(NULL, STM32_PROCFS_MOUNTPOINT, "procfs", 0, NULL); - if (ret < 0) - { - serr("ERROR: Failed to mount procfs at %s: %d\n", - STM32_PROCFS_MOUNTPOINT, ret); - } -#endif - -#ifdef HAVE_MMCSD - ret = stm32_sdinitialize(CONFIG_NSH_MMCSDSLOTNO); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_sdinitialize failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_INPUT_ADS7843E - /* Initialize the touchscreen */ - - ret = stm32_tsc_setup(0); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_tsc_setup failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_STM32_CAN_CHARDRIVER - /* Initialize CAN and register the CAN driver. */ - - ret = stm32_can_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_can_setup failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_SENSORS_MPL115A - ret = board_mpl115a_initialize(0, 5); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_mpl115ainitialize failed: %d\n", ret); - } -#endif - -#if defined(CONFIG_VIEWTOOL_FT80X_SPI1) || defined(CONFIG_VIEWTOOL_FT80X_SPI2) - ret = stm32_ft80x_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_ft80x_setup failed: %d\n", ret); - } -#endif - -#if defined(CONFIG_VIEWTOOL_MAX3421E_SPI1) || defined(CONFIG_VIEWTOOL_MAX3421E_SPI2) - ret = stm32_max3421e_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_ft80x_setup failed: %d\n", ret); - } -#endif - - UNUSED(ret); - return OK; -} diff --git a/boards/arm/stm32/viewtool-stm32f107/src/stm32_buttons.c b/boards/arm/stm32/viewtool-stm32f107/src/stm32_buttons.c deleted file mode 100644 index 38d6fbedecf79..0000000000000 --- a/boards/arm/stm32/viewtool-stm32f107/src/stm32_buttons.c +++ /dev/null @@ -1,153 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/viewtool-stm32f107/src/stm32_buttons.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include -#include - -#include "viewtool_stm32f107.h" - -#ifdef CONFIG_ARCH_BUTTONS - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* Pin configuration for each STM3210E-EVAL button. This array is indexed by - * the BUTTON_* and JOYSTICK_* definitions in board.h - */ - -static const uint32_t g_buttons[NUM_BUTTONS] = -{ - GPIO_SW2, GPIO_SW3, GPIO_SW4 -}; - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_button_initialize - * - * Description: - * board_button_initialize() must be called to initialize button resources. - * After that, board_buttons() may be called to collect the current state - * of all buttons or board_button_irq() may be called to register button - * interrupt handlers. - * - ****************************************************************************/ - -uint32_t board_button_initialize(void) -{ - int i; - - /* Configure the GPIO pins as inputs. NOTE that EXTI interrupts are - * configured for some pins but NOT used in this file - */ - - for (i = 0; i < NUM_BUTTONS; i++) - { - stm32_configgpio(g_buttons[i]); - } - - return NUM_BUTTONS; -} - -/**************************************************************************** - * Name: board_buttons - ****************************************************************************/ - -uint32_t board_buttons(void) -{ - uint32_t ret = 0; - int i; - - /* Check that state of each key */ - - for (i = 0; i < NUM_BUTTONS; i++) - { - /* A LOW value means that the key is pressed for most keys. The - * exception is the WAKEUP button. - */ - - bool released = stm32_gpioread(g_buttons[i]); - - /* Accumulate the set of depressed (not released) keys */ - - if (!released) - { - ret |= (1 << i); - } - } - - return ret; -} - -/**************************************************************************** - * Button support. - * - * Description: - * board_button_initialize() must be called to initialize button resources. - * After that, board_buttons() may be called to collect the current state - * of all buttons or board_button_irq() may be called to register button - * interrupt handlers. - * - * After board_button_initialize() has been called, board_buttons() may be - * called to collect the state of all buttons. board_buttons() returns an - * 32-bit bit set with each bit associated with a button. See the - * BUTTON_*_BIT and JOYSTICK_*_BIT definitions in board.h for the meaning - * of each bit. - * - * board_button_irq() may be called to register an interrupt handler that - * will be called when a button is depressed or released. The ID value is a - * button enumeration value that uniquely identifies a button resource. See - * the BUTTON_* and JOYSTICK_* definitions in board.h for the meaning of - * enumeration value. - * - ****************************************************************************/ - -#ifdef CONFIG_ARCH_IRQBUTTONS -int board_button_irq(int id, xcpt_t irqhandler, void *arg) -{ - int ret = -EINVAL; - - /* The following should be atomic */ - - if (id >= MIN_IRQBUTTON && id <= MAX_IRQBUTTON) - { - ret = stm32_gpiosetevent(g_buttons[id], true, true, true, - irqhandler, arg); - } - - return ret; -} -#endif -#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/stm32/viewtool-stm32f107/src/stm32_can.c b/boards/arm/stm32/viewtool-stm32f107/src/stm32_can.c deleted file mode 100644 index ae2e41e792cf1..0000000000000 --- a/boards/arm/stm32/viewtool-stm32f107/src/stm32_can.c +++ /dev/null @@ -1,103 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/viewtool-stm32f107/src/stm32_can.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32.h" -#include "stm32_can.h" - -#ifdef CONFIG_CAN - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -/* The STM32F107VC supports CAN1 and CAN2 */ - -#if defined(CONFIG_STM32_CAN1) && defined(CONFIG_STM32_CAN2) -# warning "Both CAN1 and CAN2 are enabled. Assuming only CAN1." -# undef CONFIG_STM32_CAN2 -#endif - -#ifdef CONFIG_STM32_CAN1 -# define CAN_PORT 1 -#else -# define CAN_PORT 2 -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_can_setup - * - * Description: - * Initialize CAN and register the CAN device - * - ****************************************************************************/ - -int stm32_can_setup(void) -{ -#if defined(CONFIG_STM32_CAN1) || defined(CONFIG_STM32_CAN2) - struct can_dev_s *can; - int ret; - - /* Call stm32_caninitialize() to get an instance of the CAN interface */ - - can = stm32_caninitialize(CAN_PORT); - if (can == NULL) - { - canerr("ERROR: Failed to get CAN interface\n"); - return -ENODEV; - } - - /* Register the CAN driver at "/dev/can0" */ - - ret = can_register("/dev/can0", can); - if (ret < 0) - { - canerr("ERROR: can_register failed: %d\n", ret); - return ret; - } - - return OK; -#else - return -ENODEV; -#endif -} - -#endif /* CONFIG_CAN */ diff --git a/boards/arm/stm32/viewtool-stm32f107/src/stm32_highpri.c b/boards/arm/stm32/viewtool-stm32f107/src/stm32_highpri.c deleted file mode 100644 index b9d97434c7732..0000000000000 --- a/boards/arm/stm32/viewtool-stm32f107/src/stm32_highpri.c +++ /dev/null @@ -1,277 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/viewtool-stm32f107/src/stm32_highpri.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include - -#include -#include - -#include -#include - -#include "arm_internal.h" -#include "ram_vectors.h" -#include "stm32_tim.h" - -#include "viewtool_stm32f107.h" - -#include - -#ifdef CONFIG_VIEWTOOL_HIGHPRI - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -#ifndef CONFIG_ARCH_CHIP_STM32F103VC -# warning This only only been verified with CONFIG_ARCH_CHIP_STM32F103VC -#endif - -#ifndef CONFIG_ARCH_HIPRI_INTERRUPT -# error CONFIG_ARCH_HIPRI_INTERRUPT is required -#endif - -#ifndef CONFIG_ARCH_RAMVECTORS -# error CONFIG_ARCH_RAMVECTORS is required -#endif - -#ifndef CONFIG_STM32_TIM6 -# error CONFIG_STM32_TIM6 is required -#endif - -#ifndef CONFIG_VIEWTOOL_TIM6_FREQUENCY -# warning CONFIG_VIEWTOOL_TIM6_FREQUENCY defaulting to STM32_APB1_TIM6_CLKIN -# define CONFIG_VIEWTOOL_TIM6_FREQUENCY STM32_APB1_TIM6_CLKIN -#endif - -#ifndef CONFIG_VIEWTOOL_TIM6_PERIOD -# warning CONFIG_VIEWTOOL_TIM6_PERIOD defaulting to 1MS -# define CONFIG_VIEWTOOL_TIM6_PERIOD (CONFIG_VIEWTOOL_TIM6_FREQUENCY / 1000) -#endif - -#ifndef CONFIG_ARCH_IRQPRIO -# error CONFIG_ARCH_IRQPRIO is required -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -struct highpri_s -{ - struct stm32_tim_dev_s *dev; /* TIM6 driver instance */ - volatile uint64_t basepri[16]; - volatile uint64_t handler; - volatile uint64_t thread; -}; - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -static struct highpri_s g_highpri; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -static inline_function bool is_nesting_interrupt(void) -{ - return up_interrupt_context(); -} - -/**************************************************************************** - * Name: tim6_handler - * - * Description: - * This is the handler for the high speed TIM6 interrupt. - * - ****************************************************************************/ - -void tim6_handler(void) -{ - uint8_t basepri; - int index; - - /* Acknowledge the timer interrupt */ - - STM32_TIM_ACKINT(g_highpri.dev, ATIM_SR_UIF); - - /* Increment the count associated with the current basepri */ - - basepri = getbasepri(); - index = ((basepri >> 4) & 15); - g_highpri.basepri[index]++; - - /* Check if we are in an interrupt handle */ - - if (is_nesting_interrupt()) - { - g_highpri.handler++; - } - else - { - g_highpri.thread++; - } -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: highpri_main - * - * Description: - * Main entry point in into the high priority interrupt test. - * - ****************************************************************************/ - -int highpri_main(int argc, char *argv[]) -{ - struct stm32_tim_dev_s *dev; - uint64_t basepri[16]; - uint64_t handler; - uint64_t thread; - uint64_t total; - uint32_t seconds; - int prescaler; - int ret; - int i; - - printf("highpri_main: Started\n"); - - /* Configure basic timer TIM6 and enable interrupts */ - - dev = stm32_tim_init(6); - if (!dev) - { - fprintf(stderr, "highpri_main: ERROR: stm32_tim_init(6) failed\n"); - return EXIT_FAILURE; - } - - g_highpri.dev = dev; - - prescaler = STM32_TIM_SETCLOCK(dev, CONFIG_VIEWTOOL_TIM6_FREQUENCY); - printf("TIM6 CLKIN=%jd Hz, Frequency=%d Hz, prescaler=%d\n", - (uintmax_t)STM32_APB1_TIM6_CLKIN, CONFIG_VIEWTOOL_TIM6_FREQUENCY, - prescaler); - - STM32_TIM_SETPERIOD(dev, CONFIG_VIEWTOOL_TIM6_PERIOD); - printf("TIM6 period=%d cycles; interrupt rate=%d Hz\n", - CONFIG_VIEWTOOL_TIM6_PERIOD, - CONFIG_VIEWTOOL_TIM6_FREQUENCY / CONFIG_VIEWTOOL_TIM6_PERIOD); - - /* Attach TIM6 ram vector */ - - ret = arm_ramvec_attach(STM32_IRQ_TIM6, tim6_handler); - if (ret < 0) - { - fprintf(stderr, "highpri_main: ERROR: arm_ramvec_attach failed: %d\n", - ret); - return EXIT_FAILURE; - } - - /* Set the priority of the TIM6 interrupt vector */ - - ret = up_prioritize_irq(STM32_IRQ_TIM6, NVIC_SYSH_HIGH_PRIORITY); - if (ret < 0) - { - fprintf(stderr, "highpri_main: ERROR: up_prioritize_irq failed: %d\n", - ret); - return EXIT_FAILURE; - } - - /* Enable the timer interrupt at the NVIC and at TIM6 */ - - up_enable_irq(STM32_IRQ_TIM6); - STM32_TIM_ENABLEINT(dev, ATIM_DIER_UIE); - - /* Monitor interrupts */ - - seconds = 0; - for (; ; ) - { - /* Flush stdout and wait a bit */ - - fflush(stdout); - nxsched_sleep(1); - seconds++; - - /* Sample counts so that they are not volatile. Missing a count now - * and then is a normal consequence of this design. - */ - - for (i = 0; i < 16; i++) - { - basepri[i] = g_highpri.basepri[i]; - } - - handler = g_highpri.handler; - thread = g_highpri.thread; - - /* Then print out what is happening */ - - printf("Elapsed time: %" PRId32 " seconds\n\n", seconds); - for (i = 0, total = 0; i < 16; i++) - { - total += basepri[i]; - } - - if (total > 0) - { - for (i = 0; i < 16; i++) - { - if (basepri[i] > 0) - { - printf(" basepri[%02x]: %lld (%d%%)\n", - i << 4, basepri[i], - (int)((100 * basepri[i] + (total / 2)) / total)); - } - } - } - - total = handler + thread; - if (total > 0) - { - printf(" Handler: %lld (%d%%)\n", - handler, (int)((100*handler + (total / 2)) / total)); - printf(" Thread: %lld (%d%%)\n\n", - thread, (int)((100*thread + (total / 2)) / total)); - } - } - - return EXIT_SUCCESS; -} - -#endif /* CONFIG_VIEWTOOL_HIGHPRI */ diff --git a/boards/arm/stm32/viewtool-stm32f107/src/stm32_leds.c b/boards/arm/stm32/viewtool-stm32f107/src/stm32_leds.c deleted file mode 100644 index fb495d7e018e7..0000000000000 --- a/boards/arm/stm32/viewtool-stm32f107/src/stm32_leds.c +++ /dev/null @@ -1,280 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/viewtool-stm32f107/src/stm32_leds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include "stm32_gpio.h" -#include "viewtool_stm32f107.h" - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: led_onbits - * - * Description: - * Clear all LEDs to the bit encoded state - * - ****************************************************************************/ - -static void led_onbits(unsigned int clrbits) -{ - if ((clrbits & BOARD_LED1_BIT) != 0) - { - stm32_gpiowrite(GPIO_LED1, false); - } - - if ((clrbits & BOARD_LED2_BIT) != 0) - { - stm32_gpiowrite(GPIO_LED2, false); - } - - if ((clrbits & BOARD_LED3_BIT) != 0) - { - stm32_gpiowrite(GPIO_LED3, false); - } - - if ((clrbits & BOARD_LED4_BIT) != 0) - { - stm32_gpiowrite(GPIO_LED4, false); - } -} - -/**************************************************************************** - * Name: led_offbits - * - * Description: - * Clear all LEDs to the bit encoded state - * - ****************************************************************************/ - -static void led_offbits(unsigned int clrbits) -{ - if ((clrbits & BOARD_LED1_BIT) != 0) - { - stm32_gpiowrite(GPIO_LED1, true); - } - - if ((clrbits & BOARD_LED2_BIT) != 0) - { - stm32_gpiowrite(GPIO_LED2, true); - } - - if ((clrbits & BOARD_LED3_BIT) != 0) - { - stm32_gpiowrite(GPIO_LED3, true); - } - - if ((clrbits & BOARD_LED4_BIT) != 0) - { - stm32_gpiowrite(GPIO_LED4, true); - } -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_led_initialize - * - * Description: - * Configure LEDs. LEDs are left in the OFF state. - * - ****************************************************************************/ - -void stm32_led_initialize(void) -{ - /* Configure LED1-4 GPIOs for output. Initial state is OFF */ - - stm32_configgpio(GPIO_LED1); - stm32_configgpio(GPIO_LED2); - stm32_configgpio(GPIO_LED3); - stm32_configgpio(GPIO_LED4); -} - -/**************************************************************************** - * Name: board_autoled_on - * - * Description: - * Select the "logical" ON state: - * - * SYMBOL Val Meaning LED state - * LED1 LED2 LED3 LED4 - * ----------------- --- ----------------------- ---- ---- ---- ---- - * LED_STARTED 0 NuttX has been started ON OFF OFF OFF - * LED_HEAPALLOCATE 1 Heap has been allocated OFF ON OFF OFF - * LED_IRQSENABLED 2 Interrupts enabled ON ON OFF OFF - * LED_STACKCREATED 3 Idle stack created OFF OFF ON OFF - * LED_INIRQ 4 In an interrupt N/C N/C N/C GLOW - * LED_SIGNAL 4 In a signal handler N/C N/C N/C GLOW - * LED_ASSERTION 4 An assertion failed N/C N/C N/C GLOW - * LED_PANIC 4 The system has crashed N/C N/C N/C FLASH - * ED_IDLE MCU is in sleep mode Not used - * - ****************************************************************************/ - -#ifdef CONFIG_ARCH_LEDS -void board_autoled_on(int led) -{ - switch (led) - { - case 0: - led_offbits(BOARD_LED2_BIT | BOARD_LED3_BIT | BOARD_LED4_BIT); - led_onbits(BOARD_LED1_BIT); - break; - - case 1: - led_offbits(BOARD_LED1_BIT | BOARD_LED3_BIT | BOARD_LED4_BIT); - led_onbits(BOARD_LED2_BIT); - break; - - case 2: - led_offbits(BOARD_LED3_BIT | BOARD_LED4_BIT); - led_onbits(BOARD_LED1_BIT | BOARD_LED2_BIT); - break; - - case 3: - led_offbits(BOARD_LED1_BIT | BOARD_LED2_BIT | BOARD_LED4_BIT); - led_onbits(BOARD_LED3_BIT); - break; - - case 4: - stm32_gpiowrite(GPIO_LED4, false); - break; - } -} -#endif - -/**************************************************************************** - * Name: board_autoled_off - * - * Description: - * Select the "logical" OFF state: - * - * SYMBOL Val Meaning LED state - * LED1 LED2 LED3 LED4 - * ----------------- --- ----------------------- ---- ---- ---- ---- - * LED_STARTED 0 NuttX has been started ON OFF OFF OFF - * LED_HEAPALLOCATE 1 Heap has been allocated OFF ON OFF OFF - * LED_IRQSENABLED 2 Interrupts enabled ON ON OFF OFF - * LED_STACKCREATED 3 Idle stack created OFF OFF ON OFF - * LED_INIRQ 4 In an interrupt N/C N/C N/C GLOW - * LED_SIGNAL 4 In a signal handler N/C N/C N/C GLOW - * LED_ASSERTION 4 An assertion failed N/C N/C N/C GLOW - * LED_PANIC 4 The system has crashed N/C N/C N/C FLASH - * ED_IDLE MCU is in sleep mode Not used - * - ****************************************************************************/ - -#ifdef CONFIG_ARCH_LEDS -void board_autoled_off(int led) -{ - switch (led) - { - case 0: - case 1: - case 2: - case 3: - break; - - case 4: - stm32_gpiowrite(GPIO_LED4, true); - break; - } -} -#endif - -/**************************************************************************** - * Name: board_userled_initialize, board_userled, and board_userled_all - * - * Description: - * These interfaces allow user control of the board LEDs. - * - * If CONFIG_ARCH_LEDS is defined, then NuttX will control both on-board - * LEDs up until the completion of boot. The it will continue to control - * LED2; LED1 is available for application use. - * - * If CONFIG_ARCH_LEDS is not defined, then both LEDs are available for - * application use. - * - ****************************************************************************/ - -uint32_t board_userled_initialize(void) -{ - /* Already initialized by stm32_led_initialize */ - - return BOARD_NLEDS; -} - -void board_userled(int led, bool ledon) -{ - uint32_t pinset; - - switch (led) - { - case BOARD_LED1: - pinset = GPIO_LED1; - break; - - case BOARD_LED2: - pinset = GPIO_LED2; - break; - - case BOARD_LED3: - pinset = GPIO_LED3; - break; - - case BOARD_LED4: -#ifndef CONFIG_ARCH_LEDS - pinset = GPIO_LED4; - break; -#endif - default: - return; - } - - stm32_gpiowrite(pinset, !ledon); -} - -void board_userled_all(uint32_t ledset) -{ -#ifdef CONFIG_ARCH_LEDS - led_onbits(ledset & ~BOARD_LED4_BIT); - led_offbits(~(ledset | BOARD_LED4_BIT)); -#else - led_onbits(ledset); - led_offbits(~ledset); -#endif -} diff --git a/boards/arm/stm32/viewtool-stm32f107/src/stm32_mmcsd.c b/boards/arm/stm32/viewtool-stm32f107/src/stm32_mmcsd.c deleted file mode 100644 index 7720b136bfd1d..0000000000000 --- a/boards/arm/stm32/viewtool-stm32f107/src/stm32_mmcsd.c +++ /dev/null @@ -1,121 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/viewtool-stm32f107/src/stm32_mmcsd.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include "stm32_sdio.h" -#include "viewtool_stm32f107.h" - -/* Only the STM32F103 supports the SDIO interface */ - -#ifdef CONFIG_ARCH_CHIP_STM32F103VC - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -#define HAVE_MMCSD 1 /* Assume that we have SD support */ -#define STM32_MMCSDSLOTNO 0 /* There is only one slot */ - -/* Can't support MMC/SD features if the SDIO peripheral is disabled */ - -#ifndef CONFIG_STM32_SDIO -# undef HAVE_MMCSD -#endif - -/* Can't support MMC/SD features if mountpoints are disabled */ - -#ifdef CONFIG_DISABLE_MOUNTPOINT -# undef HAVE_MMCSD -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_sdinitialize - * - * Description: - * Initialize the SPI-based SD card. Requires CONFIG_DISABLE_MOUNTPOINT=n - * and CONFIG_STM32_SDIO=y - * - ****************************************************************************/ - -int stm32_sdinitialize(int minor) -{ -#ifdef HAVE_MMCSD - struct sdio_dev_s *sdio; - int ret; - - /* Configure the card-detect GPIO */ -#warning REVISIT: Missing logic - - /* First, get an instance of the SDIO interface */ - - sdio = sdio_initialize(STM32_MMCSDSLOTNO); - if (!sdio) - { - ferr("ERROR: Failed to initialize SDIO slot %d\n", STM32_MMCSDSLOTNO); - return -ENODEV; - } - - finfo("Initialized SDIO slot %d\n", STM32_MMCSDSLOTNO); - - /* Now bind the SDIO interface to the MMC/SD driver */ - - ret = mmcsd_slotinitialize(minor, sdio); - if (ret != OK) - { - ferr("ERROR:"); - ferr("Failed to bind SDIO slot %d to the MMC/SD driver, minor=%d\n", - STM32_MMCSDSLOTNO, minor); - } - - finfo("Bound SDIO slot %d to the MMC/SD driver, minor=%d\n", - STM32_MMCSDSLOTNO, minor); - - /* Then let's guess and say that there is a card in the slot. I need to - * check to see if the M3 Wildfire board supports a GPIO to detect if there - * is a card in the slot. - */ -#warning REVISIT: Need to read the current state of the card-detect pin -#warning REVISIT: Need to support interrupts from the card-detect pin - sdio_mediachange(sdio, true); -#endif - return OK; -} - -#endif /* CONFIG_ARCH_CHIP_STM32F103VC */ diff --git a/boards/arm/stm32/viewtool-stm32f107/src/stm32_spi.c b/boards/arm/stm32/viewtool-stm32f107/src/stm32_spi.c deleted file mode 100644 index 317acedc80942..0000000000000 --- a/boards/arm/stm32/viewtool-stm32f107/src/stm32_spi.c +++ /dev/null @@ -1,210 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/viewtool-stm32f107/src/stm32_spi.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include "arm_internal.h" -#include "chip.h" -#include "stm32.h" -#include "viewtool_stm32f107.h" - -#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || defined(CONFIG_STM32_SPI3) - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_spidev_initialize - * - * Description: - * Called to configure SPI chip select GPIO pins for the Viewtool - * stm32f103/107 board. - * - ****************************************************************************/ - -void weak_function stm32_spidev_initialize(void) -{ - /* NOTE: Clocking for SPIx was already provided in stm32_rcc.c. - * Configurations of SPI pins is performed in stm32_spi.c. - * Here, we only initialize chip select pins unique to the board - * architecture. - */ - -#if defined(CONFIG_STM32_SPI2) && defined(CONFIG_INPUT_ADS7843E) - /* Configure the XPT2046 SPI2 CS pin as an output */ - - stm32_configgpio(GPIO_LCDTP_CS); -#endif - -#if defined(CONFIG_STM32_SPI3) && defined(CONFIG_SENSORS_MPL115A) - /* Configure the MPL115A SPI3 CS pin as an output */ - - stm32_configgpio(GPIO_MPL115A_CS); -#endif - -#if defined(CONFIG_VIEWTOOL_FT80X_SPI1) || defined(CONFIG_VIEWTOOL_FT80X_SPI2) - /* Configure the FT80x CS pin as an input */ - - stm32_configgpio(GPIO_FT80X_CS); -#endif - -#if defined(CONFIG_VIEWTOOL_MAX3421E_SPI1) || defined(CONFIG_VIEWTOOL_MAX3421E_SPI2) - /* Configure the MAX3421E CS pin as an input */ - - stm32_configgpio(GPIO_MAX3421E_CS); -#endif -} - -/**************************************************************************** - * Name: stm32_spi1/2/3select and stm32_spi1/2/3status - * - * Description: - * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status - * must be provided by board-specific logic. They are implementations of - * the select and status methods of the SPI interface defined by struct - * spi_ops_s (see include/nuttx/spi/spi.h). All other methods - * (including stm32_spibus_initialize()) are provided by common STM32 logic. - * To use this common SPI logic on your board: - * - * 1. Provide logic in stm32_boardinitialize() to configure SPI chip - * select pins. - * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() functions - * in your board-specific logic. These functions will perform chip - * selection and status operations using GPIOs in the way your board is - * configured. - * 3. Add a calls to stm32_spibus_initialize() in your low level - * application initialization logic - * 4. The handle returned by stm32_spibus_initialize() may then be used to - * bind the SPI driver to higher level logic (e.g., calling - * mmcsd_spislotinitialize(), for example, will bind the SPI driver to - * the SPI MMC/SD driver). - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_SPI1 -void stm32_spi1select(struct spi_dev_s *dev, - uint32_t devid, bool selected) -{ - spiinfo("devid: %d CS: %s\n", - (int)devid, selected ? "assert" : "de-assert"); - -#ifdef CONFIG_VIEWTOOL_FT80X_SPI1 - /* Select/de-select the FT80x */ - - if (devid == SPIDEV_DISPLAY(0)) - { - stm32_gpiowrite(GPIO_FT80X_CS, !selected); - } - else -#endif -#ifdef CONFIG_VIEWTOOL_MAX3421E_SPI1 - /* Select/de-select the MAX3421E */ - - if (devid == SPIDEV_USBHOST(0)) - { - stm32_gpiowrite(GPIO_MAX3421E_CS, !selected); - } - else -#endif - { - spierr("ERROR: Unrecognized devid: %08lx\n", (unsigned long)devid); - } -} - -uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) -{ - return 0; -} -#endif - -#ifdef CONFIG_STM32_SPI2 -void stm32_spi2select(struct spi_dev_s *dev, - uint32_t devid, bool selected) -{ - spiinfo("devid: %d CS: %s\n", - (int)devid, selected ? "assert" : "de-assert"); - -#ifdef CONFIG_INPUT_ADS7843E - /* Select/de-select the touchscreen */ - - if (devid == SPIDEV_TOUCHSCREEN(0)) - { - stm32_gpiowrite(GPIO_LCDTP_CS, !selected); - } - else -#endif -#ifdef CONFIG_VIEWTOOL_FT80X_SPI2 - /* Select/de-select the FT80x */ - - if (devid == SPIDEV_DISPLAY(0)) - { - stm32_gpiowrite(GPIO_FT80X_CS, !selected); - } - else -#endif -#ifdef CONFIG_VIEWTOOL_MAX3421E_SPI2 - /* Select/de-select the MAX3421E */ - - if (devid == SPIDEV_USBHOST(0)) - { - stm32_gpiowrite(GPIO_MAX3421E_CS, !selected); - } - else -#endif - { - spierr("ERROR: Unrecognized devid: %08lx\n", (unsigned long)devid); - } -} - -uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) -{ - return 0; -} -#endif - -#ifdef CONFIG_STM32_SPI3 -void stm32_spi3select(struct spi_dev_s *dev, - uint32_t devid, bool selected) -{ - spiinfo("devid: %d CS: %s\n", - (int)devid, selected ? "assert" : "de-assert"); -} - -uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid) -{ - return 0; -} -#endif - -#endif /* CONFIG_STM32_SPI1 || CONFIG_STM32_SPI2 || CONFIG_STM32_SPI3*/ diff --git a/boards/arm/stm32/viewtool-stm32f107/src/stm32_ssd1289.c b/boards/arm/stm32/viewtool-stm32f107/src/stm32_ssd1289.c deleted file mode 100644 index 527956b6f1dfe..0000000000000 --- a/boards/arm/stm32/viewtool-stm32f107/src/stm32_ssd1289.c +++ /dev/null @@ -1,568 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/viewtool-stm32f107/src/stm32_ssd1289.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -#include - -#include "arm_internal.h" -#include "stm32.h" -#include "viewtool_stm32f107.h" - -#ifdef CONFIG_LCD_SSD1289 - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -#ifndef CONFIG_STM32_FSMC -# error "CONFIG_STM32_FSMC is required to use the LCD" -#endif - -/* Color depth and format */ - -#define LCD_BPP 16 -#define LCD_COLORFMT FB_FMT_RGB16_565 - -/* Display Resolution */ - -#if defined(CONFIG_LCD_LANDSCAPE) -# define LCD_XRES 320 -# define LCD_YRES 240 -#else -# define LCD_XRES 240 -# define LCD_YRES 320 -#endif - -#define LCD_BL_TIMER_PERIOD 8999 - -/* LCD is connected to the FSMC_Bank1_NOR/SRAM1 and NE1 is used as chip - * select signal - */ - -/* RS <==> A16 */ - -#define LCD_INDEX 0x60000000 /* RS = 0 */ -#define LCD_DATA 0x60020000 /* RS = 1 */ - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -/* Low Level LCD access */ - -static void stm32_select(struct ssd1289_lcd_s *dev); -static void stm32_deselect(struct ssd1289_lcd_s *dev); -static void stm32_index(struct ssd1289_lcd_s *dev, uint8_t index); -#ifndef CONFIG_SSD1289_WRONLY -static uint16_t stm32_read(struct ssd1289_lcd_s *dev); -#endif -static void stm32_write(struct ssd1289_lcd_s *dev, uint16_t data); -static void stm32_backlight(struct ssd1289_lcd_s *dev, int power); - -static void stm32_extmemgpios(const uint16_t *gpios, int ngpios); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* LCD - * - * An LCD may be connected via J11. Only the STM32F103 supports the FSMC - * signals needed to drive the LCD. - * - * The LCD features an (1) HY32D module with built-in SSD1289 LCD controller, - * and (a) a XPT2046 touch screen controller. - * - * LCD Connector - * ------------- - * - * ------------------------- --------------------- --------------- - * Connector J11 GPIO CONFIGURATION(s) - * PIN SIGNAL LEGEND (F103 only) LCD Module - * --- --------- ----------- --------------------- --------------- - * 1 VDD_5 NC N/A 5V --- - * 2 GND GND N/A GND --- - * 3 PD14 DATA0 GPIO_NPS_D0 D0 HY32D - * 4 PD15 DATA1 GPIO_NPS_D1 D1 HY32D - * 5 PD0 DATA2 GPIO_NPS_D2 D2 HY32D - * 6 PD1 DATA3 GPIO_NPS_D3 D3 HY32D - * 7 PE7 DATA4 GPIO_NPS_D4 D4 HY32D - * 8 PE8 DATA5 GPIO_NPS_D5 D5 HY32D - * 9 PE9 DATA6 GPIO_NPS_D6 D6 HY32D - * 10 PE10 DATA7 GPIO_NPS_D7 D7 HY32D - * 11 PE11 DATA8 GPIO_NPS_D8 D8 HY32D - * 12 PE12 DATA9 GPIO_NPS_D9 D9 HY32D - * 13 PE13 DATA10 GPIO_NPS_D10 D10 HY32D - * 14 PE14 DATA11 GPIO_NPS_D11 D11 HY32D - * 15 PE15 DATA12 GPIO_NPS_D12 D12 HY32D - * 16 PD8 DATA13 GPIO_NPS_D13 D13 HY32D - * 17 PD9 DATA14 GPIO_NPS_D14 D14 HY32D - * 18 PD10 DATA15 GPIO_NPS_D15 D15 HY32D - * 19 (3) LCD_CS GPIO_NPS_NE1 CS HY32D - * 20 PD11 LCD_RS GPIO_NPS_A16 RS HY32D - * 21 PD5 LCD_R/W GPIO_NPS_NWE WR HY32D - * 22 PD4 LCD_RD GPIO_NPS_NOE RD HY32D - * 23 PB1 LCD_RESET (GPIO) RESET HY32D - * 24 N/C NC N/A TE (unused?) - * 25 VDD_3.3 BL_VCC N/A BLVDD CA6219 - * (Drives LCD backlight) - * 26 GND BL_GND N/A BLGND CA6219 - * 27 PB0 BL_PWM GPIO_TIM3_CH3OUT(2) BL_CNT CA6219 - * 28 PC5 LCDTP_IRQ (GPIO) TP_IRQ XPT2046 - * 29 PC4 LCDTP_CS (GPIO) TP_CS XPT2046 - * 30 PB13 LCDTP_CLK GPIO_SPI2_SCK TP_SCK XPT2046 - * 31 PB15 LCDTP_DIN GPIO_SPI2_MOSI TP_SI XPT2046 - * 32 PB14 LCDTP_DOUT GPIO_SPI2_MISO TP_SO XPT2046 - * 33 VDD_3.3 VDD_3.3 N/A 3.3V --- - * 34 GND GND N/A GND --- - * --- --------- ----------- --------------------- --------------- - * - * NOTES: - * 1) Only the F103 version of the board supports the FSMC - * 2) No remap - * 3) LCD_CS is controlled by J13 JUMPER4 (under the LCD unfortunately): - * - * 1->2 : PD7 (GPIO_NPS_NE1) enables the multiplexor : 1E\ enable input - * (active LOW) - * 3->4 : PD13 provides 1A0 input (1A1 is grounded). : 1A0 address input - * So will chip enable to either LCD_CS or - * Flash_CS. - * 5->6 : 1Y0 output to LCD_CS : 1Y0 address output - * 7->8 : 1Y1 output to Flash_CE : 1Y1 address output - * - * Truth Table: - * 1E\ 1A0 1A1 1Y0 1Y1 - * --- --- --- --- --- - * HI N/A N/A HI HI - * LO LO LO LO HI - * LO HI LO HI LO - */ - -const uint16_t fsmc_gpios[] = -{ - /* A16... A23. REVISIT: only A16 is used by the LCD */ - - GPIO_NPS_A16, GPIO_NPS_A17, GPIO_NPS_A18, GPIO_NPS_A19, GPIO_NPS_A20, - GPIO_NPS_A21, GPIO_NPS_A22, GPIO_NPS_A23, - - /* D0... D15 */ - - GPIO_NPS_D0, GPIO_NPS_D1, GPIO_NPS_D2, GPIO_NPS_D3, GPIO_NPS_D4, - GPIO_NPS_D5, GPIO_NPS_D6, GPIO_NPS_D7, GPIO_NPS_D8, GPIO_NPS_D9, - GPIO_NPS_D10, GPIO_NPS_D11, GPIO_NPS_D12, GPIO_NPS_D13, GPIO_NPS_D14, - GPIO_NPS_D15, - - /* NOE, NWE, and NE1 */ - - GPIO_NPS_NOE, GPIO_NPS_NWE, GPIO_NPS_NE1 -}; - -#define NGPIOS (sizeof(fsmc_gpios)/sizeof(uint16_t)) - -/* This is the driver state structure */ - -static struct ssd1289_lcd_s g_ssd1289 = -{ - .select = stm32_select, - .deselect = stm32_deselect, - .index = stm32_index, -#ifndef CONFIG_SSD1289_WRONLY - .read = stm32_read, -#endif - .write = stm32_write, - .backlight = stm32_backlight -}; - -/* The saved instance of the LCD driver */ - -static struct lcd_dev_s *g_ssd1289drvr; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_select - * - * Description: - * Select the LCD device - * - ****************************************************************************/ - -static void stm32_select(struct ssd1289_lcd_s *dev) -{ - /* Does not apply to this hardware */ -} - -/**************************************************************************** - * Name: stm32_deselect - * - * Description: - * De-select the LCD device - * - ****************************************************************************/ - -static void stm32_deselect(struct ssd1289_lcd_s *dev) -{ - /* Does not apply to this hardware */ -} - -/**************************************************************************** - * Name: stm32_index - * - * Description: - * Set the index register - * - ****************************************************************************/ - -static void stm32_index(struct ssd1289_lcd_s *dev, uint8_t index) -{ - putreg16((uint16_t)index, LCD_INDEX); -} - -/**************************************************************************** - * Name: stm32_read - * - * Description: - * Read LCD data (GRAM data or register contents) - * - ****************************************************************************/ - -#ifndef CONFIG_SSD1289_WRONLY -static uint16_t stm32_read(struct ssd1289_lcd_s *dev) -{ - return getreg16(LCD_DATA); -} -#endif - -/**************************************************************************** - * Name: stm32_write - * - * Description: - * Write LCD data (GRAM data or register contents) - * - ****************************************************************************/ - -static void stm32_write(struct ssd1289_lcd_s *dev, uint16_t data) -{ - putreg16((uint16_t)data, LCD_DATA); -} - -/**************************************************************************** - * Name: stm32_backlight - * - * Description: - * Enable/disable LCD panel power - * (0: full off - CONFIG_LCD_MAXPOWER: full on). - * Used here to set pwm duty on timer used for backlight. - * - ****************************************************************************/ - -static void stm32_backlight(struct ssd1289_lcd_s *dev, int power) -{ - DEBUGASSERT(power <= CONFIG_LCD_MAXPOWER); - - /* Set new power level */ - - if (power > 0) - { - uint32_t duty; - - /* Calculate the new backlight duty. It is a fraction of the timer - * period based on the ration of the current power setting to the - * maximum power setting. - */ - - duty = ((uint32_t)LCD_BL_TIMER_PERIOD * - (uint32_t)power) / CONFIG_LCD_MAXPOWER; - if (duty >= LCD_BL_TIMER_PERIOD) - { - duty = LCD_BL_TIMER_PERIOD - 1; - } - - putreg16((uint16_t)duty, STM32_TIM3_CCR2); - } - else - { - putreg16((uint16_t)0, STM32_TIM3_CCR2); - } -} - -static void init_lcd_backlight(void) -{ - uint16_t ccmr; - uint16_t ccer; - - /* Configure PB5 as TIM3 CH2 output */ - - stm32_configgpio(GPIO_TIM3_CH2OUT); - - /* Enable timer 3 clocking */ - - modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM3EN); - - /* Reset timer 3 */ - - modifyreg32(STM32_RCC_APB1RSTR, 0, RCC_APB1RSTR_TIM3RST); - modifyreg32(STM32_RCC_APB1RSTR, RCC_APB1RSTR_TIM3RST, 0); - - /* Reset the Counter Mode and set the clock division */ - - putreg16(0, STM32_TIM3_CR1); - - /* Set the Autoreload value */ - - putreg16(LCD_BL_TIMER_PERIOD, STM32_TIM3_ARR); - - /* Set the Prescaler value */ - - putreg16(0, STM32_TIM3_PSC); - - /* Generate an update event to reload the Prescaler value immediately */ - - putreg16(ATIM_EGR_UG, STM32_TIM3_EGR); - - /* Disable the Channel 2 */ - - ccer = getreg16(STM32_TIM3_CCER); - ccer &= ~ATIM_CCER_CC2E; - putreg16(ccer, STM32_TIM3_CCER); - - /* Select the Output Compare Mode Bits */ - - ccmr = getreg16(STM32_TIM3_CCMR1); - ccmr &= ATIM_CCMR1_OC2M_MASK; - ccmr |= (ATIM_CCMR_MODE_PWM1 << ATIM_CCMR1_OC2M_SHIFT); - - putreg16(0, STM32_TIM3_CCR2); - - /* Select the output polarity level == HIGH */ - - ccer &= ~ATIM_CCER_CC2P; - - /* Enable channel 2 */ - - ccer |= ATIM_CCER_CC2E; - - /* Write the timer configuration */ - - putreg16(ccmr, STM32_TIM3_CCMR1); - putreg16(ccer, STM32_TIM3_CCER); - - /* Set the auto preload enable bit */ - - modifyreg16(STM32_TIM3_CR1, 0, ATIM_CR1_ARPE); - - /* Enable Backlight Timer !!!! */ - - modifyreg16(STM32_TIM3_CR1, 0, ATIM_CR1_CEN); - - /* Dump timer3 registers */ - - lcdinfo("APB1ENR: %08x\n", getreg32(STM32_RCC_APB1ENR)); - lcdinfo("CR1: %04x\n", getreg32(STM32_TIM3_CR1)); - lcdinfo("CR2: %04x\n", getreg32(STM32_TIM3_CR2)); - lcdinfo("SMCR: %04x\n", getreg32(STM32_TIM3_SMCR)); - lcdinfo("DIER: %04x\n", getreg32(STM32_TIM3_DIER)); - lcdinfo("SR: %04x\n", getreg32(STM32_TIM3_SR)); - lcdinfo("EGR: %04x\n", getreg32(STM32_TIM3_EGR)); - lcdinfo("CCMR1: %04x\n", getreg32(STM32_TIM3_CCMR1)); - lcdinfo("CCMR2: %04x\n", getreg32(STM32_TIM3_CCMR2)); - lcdinfo("CCER: %04x\n", getreg32(STM32_TIM3_CCER)); - lcdinfo("CNT: %04x\n", getreg32(STM32_TIM3_CNT)); - lcdinfo("PSC: %04x\n", getreg32(STM32_TIM3_PSC)); - lcdinfo("ARR: %04x\n", getreg32(STM32_TIM3_ARR)); - lcdinfo("CCR1: %04x\n", getreg32(STM32_TIM3_CCR1)); - lcdinfo("CCR2: %04x\n", getreg32(STM32_TIM3_CCR2)); - lcdinfo("CCR3: %04x\n", getreg32(STM32_TIM3_CCR3)); - lcdinfo("CCR4: %04x\n", getreg32(STM32_TIM3_CCR4)); - lcdinfo("CCR4: %04x\n", getreg32(STM32_TIM3_CCR4)); - lcdinfo("CCR4: %04x\n", getreg32(STM32_TIM3_CCR4)); - lcdinfo("DMAR: %04x\n", getreg32(STM32_TIM3_DMAR)); -} - -/**************************************************************************** - * Name: stm32_selectlcd - * - * Description: - * Initialize the memory controller (FSMC) - * - ****************************************************************************/ - -static void stm32_selectlcd(void) -{ - /* Configure new GPIO state */ - - stm32_extmemgpios(fsmc_gpios, NGPIOS); - - /* Enable AHB clocking to the FSMC */ - - stm32_fsmc_enable(); - - /* Bank1 NOR/SRAM control register configuration */ - - putreg32(FSMC_BCR_SRAM | FSMC_BCR_MWID16 | FSMC_BCR_WREN, STM32_FSMC_BCR1); - - /* Bank1 NOR/SRAM timing register configuration */ - - putreg32( - FSMC_BTR_ADDSET(1) | FSMC_BTR_ADDHLD(1) | - FSMC_BTR_DATAST(2) | FSMC_BTR_BUSTURN(1) | - FSMC_BTR_CLKDIV(1) | FSMC_BTR_DATLAT(2) | - FSMC_BTR_ACCMODA, - STM32_FSMC_BTR1); - - /* As ext mode is not active the write timing is ignored!! */ - - putreg32(0xffffffff, STM32_FSMC_BWTR1); - - /* Enable the bank by setting the MBKEN bit */ - - putreg32(FSMC_BCR_MBKEN | FSMC_BCR_SRAM | FSMC_BCR_MWID16 | FSMC_BCR_WREN, - STM32_FSMC_BCR1); - - /* Configure the LCD RESET pin. - * Initial value will take the LCD out of reset - */ - - stm32_configgpio(GPIO_LCD_RESET); -} - -/**************************************************************************** - * Name: stm32_extmemgpios - * - * Description: - * Initialize GPIOs for NOR or SRAM - * - ****************************************************************************/ - -static void stm32_extmemgpios(const uint16_t *gpios, int ngpios) -{ - int i; - - /* Configure GPIOs */ - - for (i = 0; i < ngpios; i++) - { - stm32_configgpio(gpios[i]); - } -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_lcd_initialize - * - * Description: - * Initialize the LCD video hardware. - * The initial state of the LCD is fully initialized, display memory - * cleared, and the LCD ready to use, but with the power setting at 0 - * (full off). - * - ****************************************************************************/ - -int board_lcd_initialize(void) -{ - /* Only initialize the driver once */ - - if (!g_ssd1289drvr) - { - lcdinfo("Initializing\n"); - - /* Initialize the backlight */ - - init_lcd_backlight(); - - /* Configure GPIO pins and configure the FSMC to support the LCD */ - - stm32_selectlcd(); - - /* Configure and enable the LCD */ - - up_mdelay(50); - g_ssd1289drvr = ssd1289_lcdinitialize(&g_ssd1289); - if (!g_ssd1289drvr) - { - lcderr("ERROR: ssd1289_lcdinitialize failed\n"); - return -ENODEV; - } - } - - /* Turn the display off */ - - g_ssd1289drvr->setpower(g_ssd1289drvr, 0); - return OK; -} - -/**************************************************************************** - * Name: board_lcd_getdev - * - * Description: - * Return a a reference to the LCD object for the specified LCD. - * This allows support for multiple LCD devices. - * - ****************************************************************************/ - -struct lcd_dev_s *board_lcd_getdev(int lcddev) -{ - DEBUGASSERT(lcddev == 0); - return g_ssd1289drvr; -} - -/**************************************************************************** - * Name: board_lcd_uninitialize - * - * Description: - * Uninitialize the LCD support - * - ****************************************************************************/ - -void board_lcd_uninitialize(void) -{ - /* Turn the display off */ - - g_ssd1289drvr->setpower(g_ssd1289drvr, 0); -} - -#endif /* CONFIG_LCD_SSD1289 */ diff --git a/boards/arm/stm32/viewtool-stm32f107/src/stm32_usbdev.c b/boards/arm/stm32/viewtool-stm32f107/src/stm32_usbdev.c deleted file mode 100644 index c0d3001b33921..0000000000000 --- a/boards/arm/stm32/viewtool-stm32f107/src/stm32_usbdev.c +++ /dev/null @@ -1,113 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/viewtool-stm32f107/src/stm32_usbdev.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include - -#include "stm32_otgfs.h" -#include "viewtool_stm32f107.h" - -#if defined(CONFIG_STM32_OTGFS) || defined(CONFIG_STM32_USB) - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_usbdev_initialize - * - * Description: - * Called from stm32_boardinitialize very early in initialization to setup - * USB related GPIO pins for the Viewtool STM32F107 board. - * - ****************************************************************************/ - -void stm32_usbdev_initialize(void) -{ - /* The OTG FS has an internal soft pull-up. - * No GPIO configuration is required - */ - -#ifdef CONFIG_ARCH_CHIP_STM32F103VC - stm32_configgpio(GPIO_USB_PULLUP); -#endif -} - -/**************************************************************************** - * Name: stm32_usbpullup - * - * Description: - * If USB is supported and the board supports a pullup via GPIO (for USB - * software connect and disconnect), then the board software must provide - * stm32_pullup. See include/nuttx/usb/usbdev.h for additional - * description of this method. Alternatively, if no pull-up GPIO the - * following EXTERN can be redefined to be NULL. - * - ****************************************************************************/ - -#ifdef CONFIG_ARCH_CHIP_STM32F103VC -int stm32_usbpullup(struct usbdev_s *dev, bool enable) -{ - usbtrace(TRACE_DEVPULLUP, (uint16_t)enable); - stm32_gpiowrite(GPIO_USB_PULLUP, !enable); - return OK; -} -#endif - -/**************************************************************************** - * Name: stm32_usbsuspend - * - * Description: - * Board logic must provide the stm32_usbsuspend logic if the USBDEV driver - * is used. This function is called whenever the USB enters or leaves - * suspend mode. This is an opportunity for the board logic to shutdown - * clocks, power, etc. while the USB is suspended. - * - ****************************************************************************/ - -void stm32_usbsuspend(struct usbdev_s *dev, bool resume) -{ - uinfo("resume: %d\n", resume); -} - -#endif /* CONFIG_STM32_OTGFS || CONFIG_STM32_USB*/ diff --git a/boards/arm/stm32/viewtool-stm32f107/src/stm32_usbmsc.c b/boards/arm/stm32/viewtool-stm32f107/src/stm32_usbmsc.c deleted file mode 100644 index 015af8a323d69..0000000000000 --- a/boards/arm/stm32/viewtool-stm32f107/src/stm32_usbmsc.c +++ /dev/null @@ -1,73 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/viewtool-stm32f107/src/stm32_usbmsc.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include - -#include "stm32.h" -#include "viewtool_stm32f107.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -#ifndef CONFIG_SYSTEM_USBMSC_DEVMINOR1 -# define CONFIG_SYSTEM_USBMSC_DEVMINOR1 VIEWTOOL_MMCSD_SLOTNO -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_usbmsc_initialize - * - * Description: - * Perform architecture specific initialization as needed to establish - * the mass storage device that will be exported by the USB MSC device. - * - ****************************************************************************/ - -int board_usbmsc_initialize(int port) -{ - /* If system/usbmsc is built as an NSH command, then SD slot should - * already have been initialized. - * In this case, there is nothing further to be done here. - */ - -#if defined(HAVE_MMCSD) && !defined(CONFIG_NSH_BUILTIN_APPS) - return stm32_sdinitialize(CONFIG_SYSTEM_USBMSC_DEVMINOR1); -#else - return OK; -#endif -} diff --git a/boards/arm/stm32c0/common/CMakeLists.txt b/boards/arm/stm32c0/common/CMakeLists.txt new file mode 100644 index 0000000000000..415c1f55334d5 --- /dev/null +++ b/boards/arm/stm32c0/common/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32c0/common/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(${NUTTX_DIR}/boards/arm/common/stm32 stm32_common) diff --git a/boards/arm/stm32c0/common/Kconfig b/boards/arm/stm32c0/common/Kconfig new file mode 100644 index 0000000000000..5c48f62a0258b --- /dev/null +++ b/boards/arm/stm32c0/common/Kconfig @@ -0,0 +1,6 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# + +source "boards/arm/common/stm32/Kconfig" diff --git a/boards/arm/stm32c0/common/Makefile b/boards/arm/stm32c0/common/Makefile new file mode 100644 index 0000000000000..ef355b1592aef --- /dev/null +++ b/boards/arm/stm32c0/common/Makefile @@ -0,0 +1,39 @@ +############################################################################# +# boards/arm/stm32c0/common/Makefile +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################# + +include $(TOPDIR)/Make.defs + +STM32_BOARD_COMMON_DIR := $(TOPDIR)$(DELIM)boards$(DELIM)arm$(DELIM)common$(DELIM)stm32 +STM32_COMMON_SRCDIR := $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)common$(DELIM)stm32 + +include board/Make.defs +include $(STM32_BOARD_COMMON_DIR)$(DELIM)src$(DELIM)Make.defs + +DEPPATH += --dep-path board + +include $(TOPDIR)/boards/Board.mk + +ARCHSRCDIR = $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src +BOARDDIR = $(ARCHSRCDIR)$(DELIM)board +CFLAGS += ${INCDIR_PREFIX}$(BOARDDIR)$(DELIM)include +CFLAGS += ${INCDIR_PREFIX}$(STM32_COMMON_SRCDIR) +CXXFLAGS += ${INCDIR_PREFIX}$(STM32_COMMON_SRCDIR) diff --git a/boards/arm/stm32c0/nucleo-c071rb/CMakeLists.txt b/boards/arm/stm32c0/nucleo-c071rb/CMakeLists.txt new file mode 100644 index 0000000000000..84bb8fe3c7be2 --- /dev/null +++ b/boards/arm/stm32c0/nucleo-c071rb/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32c0/nucleo-c071rb/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/arm/stm32f0l0g0/nucleo-c071rb/Kconfig b/boards/arm/stm32c0/nucleo-c071rb/Kconfig similarity index 100% rename from boards/arm/stm32f0l0g0/nucleo-c071rb/Kconfig rename to boards/arm/stm32c0/nucleo-c071rb/Kconfig diff --git a/boards/arm/stm32c0/nucleo-c071rb/configs/adcscope/defconfig b/boards/arm/stm32c0/nucleo-c071rb/configs/adcscope/defconfig new file mode 100644 index 0000000000000..c203fd3be4ddc --- /dev/null +++ b/boards/arm/stm32c0/nucleo-c071rb/configs/adcscope/defconfig @@ -0,0 +1,63 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_DEV_CONSOLE is not set +# CONFIG_SYSTEM_DD is not set +CONFIG_ADC=y +CONFIG_ANALOG=y +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nucleo-c071rb" +CONFIG_ARCH_BOARD_NUCLEO_C071RB=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32c0" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32C071RB=y +CONFIG_ARCH_CHIP_STM32C071XX=y +CONFIG_ARCH_CHIP_STM32C0=y +CONFIG_ARCH_IRQBUTTONS=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL=y +CONFIG_BOARDCTL_MKRD=y +CONFIG_BOARD_LOOPSPERMSEC=3997 +CONFIG_BUILTIN=y +CONFIG_DEBUG_ASSERTIONS=y +CONFIG_DEBUG_ASSERTIONS_EXPRESSION=y +CONFIG_DEBUG_CUSTOMOPT=y +CONFIG_DEBUG_FEATURES=y +CONFIG_DEBUG_OPTLEVEL="-O1" +CONFIG_DEBUG_SYMBOLS=y +CONFIG_INIT_ENTRYPOINT="adcscope_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_LOGGING_NXSCOPE=y +CONFIG_LOGGING_NXSCOPE_INTF_SERIAL=y +CONFIG_NDEBUG=y +CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 +CONFIG_NUNGET_CHARS=0 +CONFIG_PTHREAD_MUTEX_UNSAFE=y +CONFIG_RAM_SIZE=24576 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=19 +CONFIG_START_MONTH=5 +CONFIG_START_YEAR=2013 +CONFIG_STM32_ADC1=y +CONFIG_STM32_ADC1_DMA=y +CONFIG_STM32_ADC1_DMA_CFG=1 +CONFIG_STM32_ADC1_SAMPLE_FREQUENCY=10 +CONFIG_STM32_ADC1_TIMTRIG=3 +CONFIG_STM32_ADC_MAX_SAMPLES=6 +CONFIG_STM32_DMA1=y +CONFIG_STM32_TIM1=y +CONFIG_STM32_TIM1_ADC=y +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_ADCSCOPE=y +CONFIG_SYSTEM_ADCSCOPE_FETCH_INTERVAL=0 +CONFIG_SYSTEM_ADCSCOPE_SERIAL_PATH="/dev/ttyS0" +CONFIG_TASK_NAME_SIZE=32 diff --git a/boards/arm/stm32c0/nucleo-c071rb/configs/jumbo/defconfig b/boards/arm/stm32c0/nucleo-c071rb/configs/jumbo/defconfig new file mode 100644 index 0000000000000..6851bb112d3bb --- /dev/null +++ b/boards/arm/stm32c0/nucleo-c071rb/configs/jumbo/defconfig @@ -0,0 +1,94 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_ARGCAT is not set +CONFIG_ADC=y +CONFIG_ANALOG=y +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nucleo-c071rb" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_NUCLEO_C071RB=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32c0" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32C071RB=y +CONFIG_ARCH_CHIP_STM32C071XX=y +CONFIG_ARCH_CHIP_STM32C0=y +CONFIG_ARCH_IRQBUTTONS=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL=y +CONFIG_BOARD_LOOPSPERMSEC=3997 +CONFIG_BUILTIN=y +CONFIG_DEBUG_FEATURES=y +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_DEV_GPIO=y +CONFIG_DISABLE_ENVIRON=y +CONFIG_DISABLE_MOUNTPOINT=y +CONFIG_DISABLE_MQUEUE=y +CONFIG_DISABLE_POSIX_TIMERS=y +CONFIG_DISABLE_PSEUDOFS_OPERATIONS=y +CONFIG_EXAMPLES_ADC=y +CONFIG_EXAMPLES_ADC_GROUPSIZE=2 +CONFIG_EXAMPLES_ADC_SWTRIG=y +CONFIG_EXAMPLES_BUTTONS=y +CONFIG_EXAMPLES_HELLO=y +CONFIG_EXAMPLES_NXMBSERVER=y +CONFIG_EXAMPLES_PWM=y +CONFIG_EXAMPLES_PWM_DEVPATH="/dev/pwm13" +CONFIG_EXAMPLES_QENCODER=y +CONFIG_EXAMPLES_WATCHDOG=y +CONFIG_INDUSTRY_NXMODBUS=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=1536 +CONFIG_INPUT=y +CONFIG_INPUT_BUTTONS=y +CONFIG_INPUT_BUTTONS_DEBOUNCE_DELAY=10 +CONFIG_INPUT_BUTTONS_LOWER=y +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=64 +CONFIG_NSH_READLINE=y +CONFIG_NUNGET_CHARS=0 +CONFIG_NXMODBUS_CLIENT=y +CONFIG_POSIX_SPAWN_DEFAULT_STACKSIZE=1536 +CONFIG_PTHREAD_MUTEX_UNSAFE=y +CONFIG_PTHREAD_STACK_DEFAULT=1536 +CONFIG_PWM=y +CONFIG_RAM_SIZE=24576 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_SENSORS=y +CONFIG_SENSORS_QENCODER=y +CONFIG_SERIAL_TERMIOS=y +CONFIG_START_DAY=19 +CONFIG_START_MONTH=5 +CONFIG_START_YEAR=2013 +CONFIG_STDIO_DISABLE_BUFFERING=y +CONFIG_STM32_ADC1=y +CONFIG_STM32_ADC_MAX_SAMPLES=6 +CONFIG_STM32_DMA1=y +CONFIG_STM32_IWDG=y +CONFIG_STM32_PWM_MULTICHAN=y +CONFIG_STM32_TIM14=y +CONFIG_STM32_TIM14_CH1OUT=y +CONFIG_STM32_TIM14_CHANNEL1=y +CONFIG_STM32_TIM14_PWM=y +CONFIG_STM32_TIM3=y +CONFIG_STM32_TIM3_QE=y +CONFIG_STM32_USART1=y +CONFIG_STM32_USART2=y +CONFIG_STM32_WWDG=y +CONFIG_SYSTEM_NSH=y +CONFIG_SYSTEM_NXMBCLIENT=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART1_RS485=y +CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32c0/nucleo-c071rb/configs/nsh/defconfig b/boards/arm/stm32c0/nucleo-c071rb/configs/nsh/defconfig new file mode 100644 index 0000000000000..5849d3ab45d5d --- /dev/null +++ b/boards/arm/stm32c0/nucleo-c071rb/configs/nsh/defconfig @@ -0,0 +1,45 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nucleo-c071rb" +CONFIG_ARCH_BOARD_NUCLEO_C071RB=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32c0" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32C071RB=y +CONFIG_ARCH_CHIP_STM32C071XX=y +CONFIG_ARCH_CHIP_STM32C0=y +CONFIG_ARCH_IRQBUTTONS=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=3997 +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=1536 +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 +CONFIG_NSH_FILEIOSIZE=64 +CONFIG_NSH_READLINE=y +CONFIG_NUNGET_CHARS=0 +CONFIG_POSIX_SPAWN_DEFAULT_STACKSIZE=1536 +CONFIG_PTHREAD_MUTEX_UNSAFE=y +CONFIG_PTHREAD_STACK_DEFAULT=1536 +CONFIG_RAM_SIZE=24576 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=19 +CONFIG_START_MONTH=5 +CONFIG_START_YEAR=2013 +CONFIG_STDIO_DISABLE_BUFFERING=y +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32c0/nucleo-c071rb/include/board.h b/boards/arm/stm32c0/nucleo-c071rb/include/board.h new file mode 100644 index 0000000000000..500badf7dcb78 --- /dev/null +++ b/boards/arm/stm32c0/nucleo-c071rb/include/board.h @@ -0,0 +1,186 @@ +/**************************************************************************** + * boards/arm/stm32c0/nucleo-c071rb/include/board.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_STM32F0L0G0_NUCLEO_C071RB_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32F0L0G0_NUCLEO_C071RB_INCLUDE_BOARD_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#ifndef __ASSEMBLY__ +# include +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Clocking *****************************************************************/ + +/* HSI - Internal 48 MHz RC Oscillator + * LSI - 32 KHz RC + * HSE - 8 MHz from MCO output of ST-LINK (disabled by default) + * LSE - 32.768 kHz + */ + +#define STM32_BOARD_XTAL 8000000ul /* 8MHz */ + +#define STM32_HSI_FREQUENCY 48000000ul /* 48MHz */ +#define STM32_LSI_FREQUENCY 32000 /* Between 30kHz and 60kHz */ +#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL +#define STM32_LSE_FREQUENCY 32768 /* X2 on board */ + +/* Configure HSI48 clock division factor (48 MHz) */ + +#define STM32_RCC_HSIDIV RCC_CR_HSIDIV_HSI + +/* Use the HSI as SYSCLK source (48 MHz) */ + +#define STM32_SYSCLK_SW RCC_CFGR_SW_HSI +#define STM32_SYSCLK_SWS RCC_CFGR_SWS_HSI +#define STM32_SYSCLK_FREQUENCY (STM32_HSI_FREQUENCY) + +/* AHB clock (HCLK) is SYSCLK (48 MHz) */ + +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY + +/* APB1 clock (PCLK) is HCLK (48 MHz) */ + +#define STM32_RCC_CFGR_PPRE RCC_CFGR_PPRE_HCLK +#define STM32_PCLK1_FREQUENCY STM32_HCLK_FREQUENCY + +/* All timers on PCLK x1 (48 MHz) */ + +#define STM32_APB2_TIM1_CLKIN STM32_PCLK1_FREQUENCY +#define STM32_APB1_TIM2_CLKIN STM32_PCLK1_FREQUENCY +#define STM32_APB1_TIM3_CLKIN STM32_PCLK1_FREQUENCY +#define STM32_APB2_TIM14_CLKIN STM32_PCLK1_FREQUENCY +#define STM32_APB2_TIM15_CLKIN STM32_PCLK1_FREQUENCY +#define STM32_APB2_TIM16_CLKIN STM32_PCLK1_FREQUENCY +#define STM32_APB2_TIM17_CLKIN STM32_PCLK1_FREQUENCY + +/* LED definitions **********************************************************/ + +/* LED index values for use with board_userled() */ + +#define BOARD_LED1 0 /* User LD1 */ +#define BOARD_LED2 1 /* User LD2 */ +#define BOARD_NLEDS 2 + +/* LED bits for use with board_userled_all() */ + +#define BOARD_LED1_BIT (1 << BOARD_LED1) +#define BOARD_LED2_BIT (1 << BOARD_LED2) + +/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the LED on the + * board. The following definitions describe how NuttX controls + * the LED: + * + * SYMBOL Meaning LED1 state + * ------------------ ----------------------- ---------- + * LED_STARTED NuttX has been started OFF + * LED_HEAPALLOCATE Heap has been allocated OFF + * LED_IRQSENABLED Interrupts enabled OFF + * LED_STACKCREATED Idle stack created ON + * LED_INIRQ In an interrupt No change + * LED_SIGNAL In a signal handler No change + * LED_ASSERTION An assertion failed No change + * LED_PANIC The system has crashed Blinking + * LED_IDLE STM32 is in sleep mode Not used + */ + +#define LED_STARTED 0 +#define LED_HEAPALLOCATE 0 +#define LED_IRQSENABLED 0 +#define LED_STACKCREATED 1 +#define LED_INIRQ 2 +#define LED_SIGNAL 2 +#define LED_ASSERTION 2 +#define LED_PANIC 1 + +/* Button definitions *******************************************************/ + +/* Nucleo C071RB board supports two buttons; only one button is controllable + * by software: + * + * B1 USER: user button connected to STM32 I/O PC13. + * B2 RESET: push button connected to NRST; used to RESET the MCU. + */ + +#define BUTTON_USER 0 /* User B1 */ +#define NUM_BUTTONS 1 + +#define BUTTON_USER_BIT (1 << BUTTON_USER) + +/* Alternate function pin selections ****************************************/ + +/* USART */ + +/* USART1 at arduino D0/D1: + * USART1_RX - PB7 + * USART1_TX - PB6 + */ + +#define GPIO_USART1_RX (GPIO_USART1_RX_2|GPIO_SPEED_HIGH) /* PB7 */ +#define GPIO_USART1_TX (GPIO_USART1_TX_2|GPIO_SPEED_HIGH) /* PB6 */ + +/* USART1 RS485_DIR - PA8 (arduino D7) + * (compatible with RS485 Waveshare shield) + */ + +#define GPIO_USART1_RS485_DIR (GPIO_OUTPUT | GPIO_PUSHPULL | \ + GPIO_SPEED_HIGH | GPIO_OUTPUT_CLEAR | \ + GPIO_PORTA | GPIO_PIN8) + +/* By default the USART2 is connected to STLINK Virtual COM Port: + * USART2_RX - PA3 + * USART2_TX - PA2 + */ + +#define GPIO_USART2_RX (GPIO_USART2_RX_1|GPIO_SPEED_HIGH) /* PA3 */ +#define GPIO_USART2_TX (GPIO_USART2_TX_1|GPIO_SPEED_HIGH) /* PA2 */ + +/* Qencoder on TIM3: + * TIM3_CH1IN - PB4 (D5) + * TIM3_CH2IN - PC7 (D3) + */ + +#define GPIO_TIM3_CH1IN (GPIO_TIM3_CH1IN_2|GPIO_SPEED_HIGH) +#define GPIO_TIM3_CH2IN (GPIO_TIM3_CH2IN_6|GPIO_SPEED_HIGH) + +/* PWM on TIM14: + * TIM14_CH1 - PA7 (D11) + */ + +#define GPIO_TIM14_CH1OUT (GPIO_TIM14_CH1OUT_2|GPIO_SPEED_HIGH) + +/* DMA channels *************************************************************/ + +/* ADC */ + +#define ADC1_DMA_CHAN DMAMAP_DMA1_ADC1 /* DMA1 */ + +#endif /* __BOARDS_ARM_STM32F0L0G0_NUCLEO_C071RB_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32c0/nucleo-c071rb/scripts/Make.defs b/boards/arm/stm32c0/nucleo-c071rb/scripts/Make.defs new file mode 100644 index 0000000000000..50ef07255e8c7 --- /dev/null +++ b/boards/arm/stm32c0/nucleo-c071rb/scripts/Make.defs @@ -0,0 +1,41 @@ +############################################################################ +# boards/arm/stm32c0/nucleo-c071rb/scripts/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/.config +include $(TOPDIR)/tools/Config.mk +include $(TOPDIR)/arch/arm/src/armv6-m/Toolchain.defs + +LDSCRIPT = flash.ld +ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) + +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32c0/nucleo-c071rb/scripts/flash.ld b/boards/arm/stm32c0/nucleo-c071rb/scripts/flash.ld new file mode 100644 index 0000000000000..d8da09abcd0e3 --- /dev/null +++ b/boards/arm/stm32c0/nucleo-c071rb/scripts/flash.ld @@ -0,0 +1,111 @@ +/**************************************************************************** + * boards/arm/stm32c0/nucleo-c071rb/scripts/flash.ld + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* The STM32C071RBT6 has 128KB of FLASH beginning at address 0x0800:0000 and + * 24Kb of SRAM at address 0x20000000. + * + * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 + * where the code expects to begin execution by jumping to the entry point in + * the 0x0800:0000 address range. + */ + +MEMORY +{ + flash (rx) : ORIGIN = 0x08000000, LENGTH = 128K + sram (rwx) : ORIGIN = 0x20000000, LENGTH = 24K +} + +OUTPUT_ARCH(arm) +EXTERN(_vectors) +ENTRY(_stext) + +SECTIONS +{ + .text : + { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > flash + + .init_section : ALIGN(4) { + _sinit = ABSOLUTE(.); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) + _einit = ABSOLUTE(.); + } > flash + + .ARM.extab ALIGN(4): { + *(.ARM.extab*) + } > flash + + .ARM.exidx : ALIGN(4) { + __exidx_start = ABSOLUTE(.); + *(.ARM.exidx*) + __exidx_end = ABSOLUTE(.); + } > flash + + _eronly = ABSOLUTE(.); + + .data : ALIGN(4) { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > sram AT > flash + + .bss : ALIGN(4) { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(8); + _ebss = ABSOLUTE(.); + } > sram + + /* Stabs debugging sections. */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/stm32c0/nucleo-c071rb/src/CMakeLists.txt b/boards/arm/stm32c0/nucleo-c071rb/src/CMakeLists.txt new file mode 100644 index 0000000000000..0639871c1d3f9 --- /dev/null +++ b/boards/arm/stm32c0/nucleo-c071rb/src/CMakeLists.txt @@ -0,0 +1,41 @@ +# ############################################################################## +# boards/arm/stm32c0/nucleo-c071rb/src/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(SRCS stm32_boot.c stm32_bringup.c) + +if(CONFIG_ARCH_LEDS) + list(APPEND SRCS stm32_autoleds.c) +else() + list(APPEND SRCS stm32_userleds.c) +endif() + +if(CONFIG_ARCH_BUTTONS) + list(APPEND SRCS stm32_buttons.c) +endif() + +if(CONFIG_ADC) + list(APPEND SRCS stm32_adc.c) +endif() + +target_sources(board PRIVATE ${SRCS}) + +set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/flash.ld") diff --git a/boards/arm/stm32c0/nucleo-c071rb/src/Make.defs b/boards/arm/stm32c0/nucleo-c071rb/src/Make.defs new file mode 100644 index 0000000000000..335741d9e20d7 --- /dev/null +++ b/boards/arm/stm32c0/nucleo-c071rb/src/Make.defs @@ -0,0 +1,43 @@ +############################################################################ +# boards/arm/stm32c0/nucleo-c071rb/src/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +CSRCS = stm32_boot.c stm32_bringup.c + +ifeq ($(CONFIG_ARCH_LEDS),y) +CSRCS += stm32_autoleds.c +else +CSRCS += stm32_userleds.c +endif + +ifeq ($(CONFIG_ARCH_BUTTONS),y) +CSRCS += stm32_buttons.c +endif + +ifeq ($(CONFIG_ADC),y) +CSRCS += stm32_adc.c +endif + +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32f0l0g0/nucleo-c071rb/src/nucleo-c071rb.h b/boards/arm/stm32c0/nucleo-c071rb/src/nucleo-c071rb.h similarity index 98% rename from boards/arm/stm32f0l0g0/nucleo-c071rb/src/nucleo-c071rb.h rename to boards/arm/stm32c0/nucleo-c071rb/src/nucleo-c071rb.h index 62e686e1c56a1..58b351b36a32f 100644 --- a/boards/arm/stm32f0l0g0/nucleo-c071rb/src/nucleo-c071rb.h +++ b/boards/arm/stm32c0/nucleo-c071rb/src/nucleo-c071rb.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-c071rb/src/nucleo-c071rb.h + * boards/arm/stm32c0/nucleo-c071rb/src/nucleo-c071rb.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32c0/nucleo-c071rb/src/stm32_adc.c b/boards/arm/stm32c0/nucleo-c071rb/src/stm32_adc.c new file mode 100644 index 0000000000000..8b0e2ebc7b168 --- /dev/null +++ b/boards/arm/stm32c0/nucleo-c071rb/src/stm32_adc.c @@ -0,0 +1,137 @@ +/**************************************************************************** + * boards/arm/stm32c0/nucleo-c071rb/src/stm32_adc.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include + +#include + +#include "stm32.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* The number of ADC channels in the conversion list */ + +#define ADC1_NCHANNELS 6 + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* Identifying number of each ADC channel (even if NCHANNELS is less ) */ + +static const uint8_t g_chanlist1[ADC1_NCHANNELS] = +{ + 0, + 1, + 4, + 17, + 11, + 12, +}; + +/* Configurations of pins used by each ADC channel */ + +static const uint32_t g_pinlist1[ADC1_NCHANNELS] = +{ + GPIO_ADC1_IN0_0, /* PA0/A0 */ + GPIO_ADC1_IN1_0, /* PA1/A1 */ + GPIO_ADC1_IN4_0, /* PA4/A2 */ + GPIO_ADC1_IN17_0, /* PB0/A3 */ + GPIO_ADC1_IN11_0, /* PC4/A4 */ + GPIO_ADC1_IN12_0, /* PC5/A5 */ +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_adc_setup + * + * Description: + * Initialize ADC and register the ADC driver. + * + ****************************************************************************/ + +int stm32_adc_setup(void) +{ + static bool initialized = false; + struct adc_dev_s *adc; + int ret; + int i; + + /* Check if we have already initialized */ + + if (!initialized) + { + /* Configure the pins as analog inputs for the selected channels */ + + for (i = 0; i < ADC1_NCHANNELS; i++) + { + stm32_configgpio(g_pinlist1[i]); + } + + /* Call stm32_adcinitialize() to get an instance of the ADC interface */ + + adc = stm32_adcinitialize(1, g_chanlist1, ADC1_NCHANNELS); + if (adc == NULL) + { + aerr("ERROR: Failed to get ADC interface 1\n"); + return -ENODEV; + } + + /* Register the ADC driver at "/dev/adc0" */ + + ret = adc_register("/dev/adc0", adc); + if (ret < 0) + { + aerr("ERROR: adc_register /dev/adc0 failed: %d\n", ret); + return ret; + } + + initialized = true; + } + + return OK; +} diff --git a/boards/arm/stm32c0/nucleo-c071rb/src/stm32_autoleds.c b/boards/arm/stm32c0/nucleo-c071rb/src/stm32_autoleds.c new file mode 100644 index 0000000000000..aa077728f35e7 --- /dev/null +++ b/boards/arm/stm32c0/nucleo-c071rb/src/stm32_autoleds.c @@ -0,0 +1,93 @@ +/**************************************************************************** + * boards/arm/stm32c0/nucleo-c071rb/src/stm32_autoleds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32_gpio.h" +#include "nucleo-c071rb.h" + +#ifdef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_autoled_initialize + ****************************************************************************/ + +void board_autoled_initialize(void) +{ + /* Configure LD1 and LD2 GPIO for output */ + + stm32_configgpio(GPIO_LD1); + stm32_configgpio(GPIO_LD2); +} + +/**************************************************************************** + * Name: board_autoled_on + ****************************************************************************/ + +void board_autoled_on(int led) +{ + if (led == BOARD_LED1) + { + stm32_gpiowrite(GPIO_LD1, true); + } + + if (led == BOARD_LED2) + { + stm32_gpiowrite(GPIO_LD2, false); + } +} + +/**************************************************************************** + * Name: board_autoled_off + ****************************************************************************/ + +void board_autoled_off(int led) +{ + if (led == BOARD_LED1) + { + stm32_gpiowrite(GPIO_LD1, false); + } + + if (led == BOARD_LED2) + { + stm32_gpiowrite(GPIO_LD2, true); + } +} + +#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32c0/nucleo-c071rb/src/stm32_boot.c b/boards/arm/stm32c0/nucleo-c071rb/src/stm32_boot.c new file mode 100644 index 0000000000000..8750e2643175f --- /dev/null +++ b/boards/arm/stm32c0/nucleo-c071rb/src/stm32_boot.c @@ -0,0 +1,83 @@ +/**************************************************************************** + * boards/arm/stm32c0/nucleo-c071rb/src/stm32_boot.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include "nucleo-c071rb.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_boardinitialize + * + * Description: + * All STM32 architectures must provide the following entry point. This + * entry point is called early in the initialization -- after all memory + * has been configured and mapped but before any devices have been + * initialized. + * + ****************************************************************************/ + +void stm32_boardinitialize(void) +{ +#ifdef CONFIG_ARCH_LEDS + /* Configure on-board LEDs if LED support has been selected. */ + + board_autoled_initialize(); +#endif + +#ifdef CONFIG_STM32_SPI + /* Configure SPI chip selects */ + + stm32_spidev_initialize(); +#endif +} + +/**************************************************************************** + * Name: board_late_initialize + * + * Description: + * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_late_initialize(). board_late_initialize() will + * be called immediately after up_initialize() is called and just before + * the initial application is started. This additional initialization + * phase may be used, for example, to initialize board-specific device + * drivers. + * + ****************************************************************************/ + +#ifdef CONFIG_BOARD_LATE_INITIALIZE +void board_late_initialize(void) +{ + stm32_bringup(); +} +#endif diff --git a/boards/arm/stm32c0/nucleo-c071rb/src/stm32_bringup.c b/boards/arm/stm32c0/nucleo-c071rb/src/stm32_bringup.c new file mode 100644 index 0000000000000..d85f3e4d8d9db --- /dev/null +++ b/boards/arm/stm32c0/nucleo-c071rb/src/stm32_bringup.c @@ -0,0 +1,142 @@ +/**************************************************************************** + * boards/arm/stm32c0/nucleo-c071rb/src/stm32_bringup.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include + +#ifdef CONFIG_INPUT_BUTTONS +# include +#endif + +#ifdef CONFIG_USERLED +# include +#endif + +#ifdef CONFIG_STM32_IWDG +# include +#endif + +#ifdef CONFIG_SENSORS_QENCODER +# include "board_qencoder.h" +#endif + +#ifdef CONFIG_PWM +# include "board_pwm.h" +#endif + +#include + +#include "nucleo-c071rb.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_bringup + * + * Description: + * Perform architecture-specific initialization + * + * CONFIG_BOARD_LATE_INITIALIZE=y : + * Called from board_late_initialize(). + * + ****************************************************************************/ + +int stm32_bringup(void) +{ + int ret; + +#ifdef CONFIG_STM32_IWDG + /* Initialize the watchdog timer */ + + stm32_iwdginitialize("/dev/watchdog0", STM32_LSI_FREQUENCY); +#endif + +#if !defined(CONFIG_ARCH_LEDS) && defined(CONFIG_USERLED_LOWER) + /* Register the LED driver */ + + ret = userled_lower_initialize(LED_DRIVER_PATH); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: userled_lower_initialize() failed: %d\n", ret); + return ret; + } +#endif + +#ifdef CONFIG_INPUT_BUTTONS + /* Register the BUTTON driver */ + + ret = btn_lower_initialize("/dev/buttons"); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: btn_lower_initialize() failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_ADC + /* Initialize ADC and register the ADC driver. */ + + ret = stm32_adc_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_adc_setup failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_PWM + /* Initialize PWM and register the PWM device. */ + + ret = stm32_pwm_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_pwm_setup failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_SENSORS_QENCODER + /* Initialize and register the qencoder driver - TIM3 */ + + ret = board_qencoder_initialize(0, 3); + if (ret != OK) + { + syslog(LOG_ERR, + "ERROR: Failed to register the qencoder: %d\n", + ret); + return ret; + } +#endif + + UNUSED(ret); + return OK; +} diff --git a/boards/arm/stm32c0/nucleo-c071rb/src/stm32_buttons.c b/boards/arm/stm32c0/nucleo-c071rb/src/stm32_buttons.c new file mode 100644 index 0000000000000..82d2a8e704f96 --- /dev/null +++ b/boards/arm/stm32c0/nucleo-c071rb/src/stm32_buttons.c @@ -0,0 +1,117 @@ +/**************************************************************************** + * boards/arm/stm32c0/nucleo-c071rb/src/stm32_buttons.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include +#include + +#include "stm32_gpio.h" +#include "nucleo-c071rb.h" + +#ifdef CONFIG_ARCH_BUTTONS + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_button_initialize + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. + * + ****************************************************************************/ + +uint32_t board_button_initialize(void) +{ + /* Configure the single button as an input. NOTE that EXTI interrupts are + * also configured for the pin. + */ + + stm32_configgpio(GPIO_BTN_USER); + return NUM_BUTTONS; +} + +/**************************************************************************** + * Name: board_buttons + ****************************************************************************/ + +uint32_t board_buttons(void) +{ + /* Check that state of each USER button. A LOW value means that the key is + * pressed. + */ + + bool released = stm32_gpioread(GPIO_BTN_USER); + return !released; +} + +/**************************************************************************** + * Button support. + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. + * + * After board_button_initialize() has been called, board_buttons() may be + * called to collect the state of all buttons. board_buttons() returns an + * 32-bit bit set with each bit associated with a button. See the + * BUTTON_*_BIT definitions in board.h for the meaning of each bit. + * + * board_button_irq() may be called to register an interrupt handler that + * will be called when a button is depressed or released. The ID value is a + * button enumeration value that uniquely identifies a button resource. See + * the BUTTON_* definitions in board.h for the meaning of enumeration + * value. + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_IRQBUTTONS +int board_button_irq(int id, xcpt_t irqhandler, void *arg) +{ + int ret = -EINVAL; + + if (id == BUTTON_USER) + { + ret = stm32_gpiosetevent(GPIO_BTN_USER, true, true, true, + irqhandler, arg); + } + + return ret; +} +#endif +#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/stm32c0/nucleo-c071rb/src/stm32_userleds.c b/boards/arm/stm32c0/nucleo-c071rb/src/stm32_userleds.c new file mode 100644 index 0000000000000..525b126499279 --- /dev/null +++ b/boards/arm/stm32c0/nucleo-c071rb/src/stm32_userleds.c @@ -0,0 +1,172 @@ +/**************************************************************************** + * boards/arm/stm32c0/nucleo-c071rb/src/stm32_userleds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32_gpio.h" +#include "nucleo-c071rb.h" + +#ifndef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/* LED Power Management */ + +#ifdef CONFIG_PM +static void led_pm_notify(struct pm_callback_s *cb, int domain, + enum pm_state_e pmstate); +static int led_pm_prepare(struct pm_callback_s *cb, int domain, + enum pm_state_e pmstate); +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#ifdef CONFIG_PM +static struct pm_callback_s g_ledscb = +{ + .notify = led_pm_notify, + .prepare = led_pm_prepare, +}; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: led_pm_notify + * + * Description: + * Notify the driver of new power state. This callback is called after + * all drivers have had the opportunity to prepare for the new power state. + * + ****************************************************************************/ + +#ifdef CONFIG_PM +static void led_pm_notify(struct pm_callback_s *cb, int domain, + enum pm_state_e pmstate) +{ +} +#endif + +/**************************************************************************** + * Name: led_pm_prepare + * + * Description: + * Request the driver to prepare for a new power state. This is a warning + * that the system is about to enter into a new power state. The driver + * should begin whatever operations that may be required to enter power + * state. The driver may abort the state change mode by returning a + * non-zero value from the callback function. + * + ****************************************************************************/ + +#ifdef CONFIG_PM +static int led_pm_prepare(struct pm_callback_s *cb, int domain, + enum pm_state_e pmstate) +{ + /* No preparation to change power modes is required by the LEDs driver. + * We always accept the state change by returning OK. + */ + + return OK; +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_userled_initialize + ****************************************************************************/ + +uint32_t board_userled_initialize(void) +{ + /* Configure LD1 and LD2 GPIO for output */ + + stm32_configgpio(GPIO_LD1); + stm32_configgpio(GPIO_LD2); + return BOARD_NLEDS; +} + +/**************************************************************************** + * Name: board_userled + ****************************************************************************/ + +void board_userled(int led, bool ledon) +{ + if (led == BOARD_LED1) + { + stm32_gpiowrite(GPIO_LD1, ledon); + } + + if (led == BOARD_LED2) + { + stm32_gpiowrite(GPIO_LD2, !ledon); + } +} + +/**************************************************************************** + * Name: board_userled_all + ****************************************************************************/ + +void board_userled_all(uint32_t ledset) +{ + stm32_gpiowrite(GPIO_LD1, (ledset & BOARD_LED1_BIT) != 0); + stm32_gpiowrite(GPIO_LD2, (ledset & BOARD_LED2_BIT) == 0); +} + +/**************************************************************************** + * Name: stm32_led_pminitialize + ****************************************************************************/ + +#ifdef CONFIG_PM +void stm32_led_pminitialize(void) +{ + /* Register to receive power management callbacks */ + + int ret = pm_register(&g_ledscb); + DEBUGASSERT(ret == OK); + UNUSED(ret); +} +#endif /* CONFIG_PM */ + +#endif /* !CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32c0/nucleo-c092rc/CMakeLists.txt b/boards/arm/stm32c0/nucleo-c092rc/CMakeLists.txt new file mode 100644 index 0000000000000..a30b26ee4f4b6 --- /dev/null +++ b/boards/arm/stm32c0/nucleo-c092rc/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32c0/nucleo-c092rc/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/arm/stm32f0l0g0/nucleo-c092rc/Kconfig b/boards/arm/stm32c0/nucleo-c092rc/Kconfig similarity index 100% rename from boards/arm/stm32f0l0g0/nucleo-c092rc/Kconfig rename to boards/arm/stm32c0/nucleo-c092rc/Kconfig diff --git a/boards/arm/stm32c0/nucleo-c092rc/configs/can/defconfig b/boards/arm/stm32c0/nucleo-c092rc/configs/can/defconfig new file mode 100644 index 0000000000000..1a2ebdb418500 --- /dev/null +++ b/boards/arm/stm32c0/nucleo-c092rc/configs/can/defconfig @@ -0,0 +1,52 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nucleo-c092rc" +CONFIG_ARCH_BOARD_NUCLEO_C092RC=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32c0" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32C092RC=y +CONFIG_ARCH_CHIP_STM32C092XX=y +CONFIG_ARCH_CHIP_STM32C0=y +CONFIG_ARCH_IRQBUTTONS=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=3997 +CONFIG_BUILTIN=y +CONFIG_CAN_ERRORS=y +CONFIG_CAN_EXTID=y +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_EXAMPLES_CAN=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=1536 +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=64 +CONFIG_NSH_READLINE=y +CONFIG_POSIX_SPAWN_DEFAULT_STACKSIZE=1536 +CONFIG_PTHREAD_MUTEX_UNSAFE=y +CONFIG_PTHREAD_STACK_DEFAULT=1536 +CONFIG_RAM_SIZE=30720 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=19 +CONFIG_START_MONTH=5 +CONFIG_START_YEAR=2013 +CONFIG_STDIO_DISABLE_BUFFERING=y +CONFIG_STM32_FDCAN1=y +CONFIG_STM32_FDCAN1_BITRATE=250000 +CONFIG_STM32_FDCAN1_NTSEG1=143 +CONFIG_STM32_FDCAN1_NTSEG2=48 +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_NSH=y +CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32c0/nucleo-c092rc/configs/cansock/defconfig b/boards/arm/stm32c0/nucleo-c092rc/configs/cansock/defconfig new file mode 100644 index 0000000000000..57d858f02bd27 --- /dev/null +++ b/boards/arm/stm32c0/nucleo-c092rc/configs/cansock/defconfig @@ -0,0 +1,58 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NET_ETHERNET is not set +# CONFIG_NET_IPv4 is not set +CONFIG_ALLOW_BSD_COMPONENTS=y +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nucleo-c092rc" +CONFIG_ARCH_BOARD_NUCLEO_C092RC=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32c0" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32C092RC=y +CONFIG_ARCH_CHIP_STM32C092XX=y +CONFIG_ARCH_CHIP_STM32C0=y +CONFIG_ARCH_INTERRUPTSTACK=1024 +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=3997 +CONFIG_BUILTIN=y +CONFIG_CANUTILS_CANDUMP=y +CONFIG_CANUTILS_CANSEND=y +CONFIG_CANUTILS_LIBCANUTILS=y +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_IOB_BUFSIZE=128 +CONFIG_IOB_NBUFFERS=10 +CONFIG_LINE_MAX=64 +CONFIG_NET=y +CONFIG_NETDEV_IFINDEX=y +CONFIG_NETDEV_LATEINIT=y +CONFIG_NET_CAN=y +CONFIG_NET_SOCKOPTS=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_RAM_SIZE=30720 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_LPWORK=y +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=14 +CONFIG_START_MONTH=10 +CONFIG_START_YEAR=2014 +CONFIG_STM32_FDCAN1=y +CONFIG_STM32_FDCAN1_BITRATE=250000 +CONFIG_STM32_FDCAN1_NTSEG1=143 +CONFIG_STM32_FDCAN1_NTSEG2=48 +CONFIG_STM32_FDCAN_SOCKET=y +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_NSH=y +CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32c0/nucleo-c092rc/configs/jumbo/defconfig b/boards/arm/stm32c0/nucleo-c092rc/configs/jumbo/defconfig new file mode 100644 index 0000000000000..bd38abc3918d6 --- /dev/null +++ b/boards/arm/stm32c0/nucleo-c092rc/configs/jumbo/defconfig @@ -0,0 +1,90 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_ARGCAT is not set +CONFIG_ADC=y +CONFIG_ANALOG=y +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nucleo-c092rc" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_NUCLEO_C092RC=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32c0" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32C092RC=y +CONFIG_ARCH_CHIP_STM32C092XX=y +CONFIG_ARCH_CHIP_STM32C0=y +CONFIG_ARCH_IRQBUTTONS=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL=y +CONFIG_BOARD_LOOPSPERMSEC=3997 +CONFIG_BUILTIN=y +CONFIG_DEBUG_FEATURES=y +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_DEV_GPIO=y +CONFIG_DISABLE_ENVIRON=y +CONFIG_DISABLE_MOUNTPOINT=y +CONFIG_DISABLE_MQUEUE=y +CONFIG_DISABLE_POSIX_TIMERS=y +CONFIG_DISABLE_PSEUDOFS_OPERATIONS=y +CONFIG_EXAMPLES_ADC=y +CONFIG_EXAMPLES_ADC_GROUPSIZE=2 +CONFIG_EXAMPLES_ADC_SWTRIG=y +CONFIG_EXAMPLES_BUTTONS=y +CONFIG_EXAMPLES_HELLO=y +CONFIG_EXAMPLES_PULSECOUNT=y +CONFIG_EXAMPLES_PWM=y +CONFIG_EXAMPLES_PWM_DEVPATH="/dev/pwm13" +CONFIG_EXAMPLES_QENCODER=y +CONFIG_EXAMPLES_WATCHDOG=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=1536 +CONFIG_INPUT=y +CONFIG_INPUT_BUTTONS=y +CONFIG_INPUT_BUTTONS_DEBOUNCE_DELAY=10 +CONFIG_INPUT_BUTTONS_LOWER=y +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=64 +CONFIG_NSH_READLINE=y +CONFIG_NUNGET_CHARS=0 +CONFIG_POSIX_SPAWN_DEFAULT_STACKSIZE=1536 +CONFIG_PTHREAD_MUTEX_UNSAFE=y +CONFIG_PTHREAD_STACK_DEFAULT=1536 +CONFIG_PWM=y +CONFIG_RAM_SIZE=30720 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_SENSORS=y +CONFIG_SENSORS_QENCODER=y +CONFIG_START_DAY=19 +CONFIG_START_MONTH=5 +CONFIG_START_YEAR=2013 +CONFIG_STDIO_DISABLE_BUFFERING=y +CONFIG_STM32_ADC1=y +CONFIG_STM32_ADC_MAX_SAMPLES=2 +CONFIG_STM32_DMA1=y +CONFIG_STM32_IWDG=y +CONFIG_STM32_PWM_MULTICHAN=y +CONFIG_STM32_TIM14=y +CONFIG_STM32_TIM14_CH1OUT=y +CONFIG_STM32_TIM14_CHANNEL1=y +CONFIG_STM32_TIM14_PWM=y +CONFIG_STM32_TIM1=y +CONFIG_STM32_TIM1_PULSECOUNT=y +CONFIG_STM32_TIM3=y +CONFIG_STM32_TIM3_QE=y +CONFIG_STM32_USART2=y +CONFIG_STM32_WWDG=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32c0/nucleo-c092rc/configs/nsh/defconfig b/boards/arm/stm32c0/nucleo-c092rc/configs/nsh/defconfig new file mode 100644 index 0000000000000..718871956d30c --- /dev/null +++ b/boards/arm/stm32c0/nucleo-c092rc/configs/nsh/defconfig @@ -0,0 +1,45 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nucleo-c092rc" +CONFIG_ARCH_BOARD_NUCLEO_C092RC=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32c0" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32C092RC=y +CONFIG_ARCH_CHIP_STM32C092XX=y +CONFIG_ARCH_CHIP_STM32C0=y +CONFIG_ARCH_IRQBUTTONS=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=3997 +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=1536 +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 +CONFIG_NSH_FILEIOSIZE=64 +CONFIG_NSH_READLINE=y +CONFIG_NUNGET_CHARS=0 +CONFIG_POSIX_SPAWN_DEFAULT_STACKSIZE=1536 +CONFIG_PTHREAD_MUTEX_UNSAFE=y +CONFIG_PTHREAD_STACK_DEFAULT=1536 +CONFIG_RAM_SIZE=30720 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=19 +CONFIG_START_MONTH=5 +CONFIG_START_YEAR=2013 +CONFIG_STDIO_DISABLE_BUFFERING=y +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32c0/nucleo-c092rc/include/board.h b/boards/arm/stm32c0/nucleo-c092rc/include/board.h new file mode 100644 index 0000000000000..0422106dda396 --- /dev/null +++ b/boards/arm/stm32c0/nucleo-c092rc/include/board.h @@ -0,0 +1,202 @@ +/**************************************************************************** + * boards/arm/stm32c0/nucleo-c092rc/include/board.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_STM32F0L0G0_NUCLEO_C092RC_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32F0L0G0_NUCLEO_C092RC_INCLUDE_BOARD_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#ifndef __ASSEMBLY__ +# include +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Clocking *****************************************************************/ + +/* HSI - Internal 48 MHz RC Oscillator + * LSI - 32 KHz RC + * HSE - 8 MHz from MCO output of ST-LINK (disabled by default) + * LSE - 32.768 kHz + */ + +#define STM32_BOARD_XTAL 8000000ul /* 8MHz */ + +#define STM32_HSI_FREQUENCY 48000000ul /* 48MHz */ +#define STM32_LSI_FREQUENCY 32000 /* Between 30kHz and 60kHz */ +#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL +#define STM32_LSE_FREQUENCY 32768 /* X2 on board */ + +/* Configure HSI48 clock division factor (48 MHz) */ + +#define STM32_RCC_HSIDIV RCC_CR_HSIDIV_HSI + +/* Use the HSI as SYSCLK source (48 MHz) */ + +#define STM32_SYSCLK_SW RCC_CFGR_SW_HSI +#define STM32_SYSCLK_SWS RCC_CFGR_SWS_HSI +#define STM32_SYSCLK_FREQUENCY (STM32_HSI_FREQUENCY) + +/* AHB clock (HCLK) is SYSCLK (48 MHz) */ + +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY + +/* APB1 clock (PCLK) is HCLK (48 MHz) */ + +#define STM32_RCC_CFGR_PPRE RCC_CFGR_PPRE_HCLK +#define STM32_PCLK1_FREQUENCY STM32_HCLK_FREQUENCY + +/* FDCAN1 clock is PCLK (48 MHz) */ + +#define STM32_FDCAN1_SEL RCC_CCIPR1_FDCAN1SEL_PCLK +#define STM32_FDCAN_FREQUENCY STM32_PCLK1_FREQUENCY + +/* All timers on PCLK x1 (48 MHz) */ + +#define STM32_APB2_TIM1_CLKIN STM32_PCLK1_FREQUENCY +#define STM32_APB1_TIM2_CLKIN STM32_PCLK1_FREQUENCY +#define STM32_APB1_TIM3_CLKIN STM32_PCLK1_FREQUENCY +#define STM32_APB2_TIM14_CLKIN STM32_PCLK1_FREQUENCY +#define STM32_APB2_TIM15_CLKIN STM32_PCLK1_FREQUENCY +#define STM32_APB2_TIM16_CLKIN STM32_PCLK1_FREQUENCY +#define STM32_APB2_TIM17_CLKIN STM32_PCLK1_FREQUENCY + +/* LED definitions **********************************************************/ + +/* LED index values for use with board_userled() */ + +#define BOARD_LED1 0 /* User LD1 */ +#define BOARD_LED2 1 /* User LD2 */ +#define BOARD_NLEDS 2 + +/* LED bits for use with board_userled_all() */ + +#define BOARD_LED1_BIT (1 << BOARD_LED1) +#define BOARD_LED2_BIT (1 << BOARD_LED2) + +/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the LED on the + * board. The following definitions describe how NuttX controls + * the LED: + * + * SYMBOL Meaning LED1 state + * ------------------ ----------------------- ---------- + * LED_STARTED NuttX has been started OFF + * LED_HEAPALLOCATE Heap has been allocated OFF + * LED_IRQSENABLED Interrupts enabled OFF + * LED_STACKCREATED Idle stack created ON + * LED_INIRQ In an interrupt No change + * LED_SIGNAL In a signal handler No change + * LED_ASSERTION An assertion failed No change + * LED_PANIC The system has crashed Blinking + * LED_IDLE STM32 is in sleep mode Not used + */ + +#define LED_STARTED 0 +#define LED_HEAPALLOCATE 0 +#define LED_IRQSENABLED 0 +#define LED_STACKCREATED 1 +#define LED_INIRQ 2 +#define LED_SIGNAL 2 +#define LED_ASSERTION 2 +#define LED_PANIC 1 + +/* Button definitions *******************************************************/ + +/* Nucleo C092RC board supports two buttons; only one button is controllable + * by software: + * + * B1 USER: user button connected to STM32 I/O PC13. + * B2 RESET: push button connected to NRST; used to RESET the MCU. + */ + +#define BUTTON_USER 0 /* User B1 */ +#define NUM_BUTTONS 1 + +#define BUTTON_USER_BIT (1 << BUTTON_USER) + +/* Alternate function pin selections ****************************************/ + +/* USART */ + +/* USART1 at arduino D0/D1: + * USART1_RX - PB7 + * USART1_TX - PB6 + */ + +#define GPIO_USART1_RX (GPIO_USART1_RX_2|GPIO_SPEED_HIGH) /* PB7 */ +#define GPIO_USART1_TX (GPIO_USART1_TX_2|GPIO_SPEED_HIGH) /* PB6 */ + +/* USART1 RS485_DIR - PA8 (arduino D7) + * (compatible with RS485 Waveshare shield) + */ + +#define GPIO_USART1_RS485_DIR (GPIO_OUTPUT | GPIO_PUSHPULL | \ + GPIO_SPEED_HIGH | GPIO_OUTPUT_CLEAR | \ + GPIO_PORTA | GPIO_PIN8) + +/* By default the USART2 is connected to STLINK Virtual COM Port: + * USART2_RX - PA3 + * USART2_TX - PA2 + */ + +#define GPIO_USART2_RX (GPIO_USART2_RX_1|GPIO_SPEED_HIGH) /* PA3 */ +#define GPIO_USART2_TX (GPIO_USART2_TX_1|GPIO_SPEED_HIGH) /* PA2 */ + +/* FDCAN */ + +#define GPIO_FDCAN1_RX (GPIO_FDCAN1_RX_8|GPIO_SPEED_HIGH) /* PD0 */ +#define GPIO_FDCAN1_TX (GPIO_FDCAN1_TX_9|GPIO_SPEED_HIGH) /* PD1 */ + +/* Qencoder on TIM3: + * TIM3_CH1IN - PB4 (D5) + * TIM3_CH2IN - PC7 (D3) + */ + +#define GPIO_TIM3_CH1IN (GPIO_TIM3_CH1IN_2|GPIO_SPEED_HIGH) +#define GPIO_TIM3_CH2IN (GPIO_TIM3_CH2IN_6|GPIO_SPEED_HIGH) + +/* PWM on TIM14: + * TIM14_CH1 - PA7 (D11) + */ + +#define GPIO_TIM14_CH1OUT (GPIO_TIM14_CH1OUT_2|GPIO_SPEED_HIGH) + +/* Pulse count on TIM1: + * TIM1_CH1OUT - PA8 (D7) + */ + +#define GPIO_TIM1_CH1OUT (GPIO_TIM1_CH1OUT_3|GPIO_SPEED_HIGH) + +/* DMA channels *************************************************************/ + +/* ADC */ + +#define ADC1_DMA_CHAN DMAMAP_DMA1_ADC1 /* DMA1 */ + +#endif /* __BOARDS_ARM_STM32F0L0G0_NUCLEO_C092RC_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32c0/nucleo-c092rc/scripts/Make.defs b/boards/arm/stm32c0/nucleo-c092rc/scripts/Make.defs new file mode 100644 index 0000000000000..dad81a59c24fd --- /dev/null +++ b/boards/arm/stm32c0/nucleo-c092rc/scripts/Make.defs @@ -0,0 +1,41 @@ +############################################################################ +# boards/arm/stm32c0/nucleo-c092rc/scripts/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/.config +include $(TOPDIR)/tools/Config.mk +include $(TOPDIR)/arch/arm/src/armv6-m/Toolchain.defs + +LDSCRIPT = flash.ld +ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) + +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32c0/nucleo-c092rc/scripts/flash.ld b/boards/arm/stm32c0/nucleo-c092rc/scripts/flash.ld new file mode 100644 index 0000000000000..83f188550d842 --- /dev/null +++ b/boards/arm/stm32c0/nucleo-c092rc/scripts/flash.ld @@ -0,0 +1,111 @@ +/**************************************************************************** + * boards/arm/stm32c0/nucleo-c092rc/scripts/flash.ld + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* The STM32C092RCT6 has 256KB of FLASH beginning at address 0x0800:0000 and + * 30KB of SRAM at address 0x20000000. + * + * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 + * where the code expects to begin execution by jumping to the entry point in + * the 0x0800:0000 address range. + */ + +MEMORY +{ + flash (rx) : ORIGIN = 0x08000000, LENGTH = 256K + sram (rwx) : ORIGIN = 0x20000000, LENGTH = 30K +} + +OUTPUT_ARCH(arm) +EXTERN(_vectors) +ENTRY(_stext) + +SECTIONS +{ + .text : + { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > flash + + .init_section : ALIGN(4) { + _sinit = ABSOLUTE(.); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) + _einit = ABSOLUTE(.); + } > flash + + .ARM.extab : ALIGN(4) { + *(.ARM.extab*) + } > flash + + .ARM.exidx : ALIGN(4) { + __exidx_start = ABSOLUTE(.); + *(.ARM.exidx*) + __exidx_end = ABSOLUTE(.); + } > flash + + _eronly = ABSOLUTE(.); + + .data : ALIGN(4) { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > sram AT > flash + + .bss : ALIGN(4) { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(8); + _ebss = ABSOLUTE(.); + } > sram + + /* Stabs debugging sections. */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/stm32c0/nucleo-c092rc/src/CMakeLists.txt b/boards/arm/stm32c0/nucleo-c092rc/src/CMakeLists.txt new file mode 100644 index 0000000000000..0ab1b18faa21c --- /dev/null +++ b/boards/arm/stm32c0/nucleo-c092rc/src/CMakeLists.txt @@ -0,0 +1,50 @@ +# ############################################################################## +# boards/arm/stm32c0/nucleo-c092rc/src/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(SRCS stm32_boot.c stm32_bringup.c) + +if(CONFIG_ARCH_LEDS) + list(APPEND SRCS stm32_autoleds.c) +else() + list(APPEND SRCS stm32_userleds.c) +endif() + +if(CONFIG_ARCH_BUTTONS) + list(APPEND SRCS stm32_buttons.c) +endif() + +if(CONFIG_ADC) + list(APPEND SRCS stm32_adc.c) +endif() + +if(CONFIG_STM32_FDCAN) + if(CONFIG_STM32_FDCAN_CHARDRIVER) + list(APPEND SRCS stm32_can.c) + endif() + if(CONFIG_STM32_FDCAN_SOCKET) + list(APPEND SRCS stm32_cansock.c) + endif() +endif() + +target_sources(board PRIVATE ${SRCS}) + +set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/flash.ld") diff --git a/boards/arm/stm32c0/nucleo-c092rc/src/Make.defs b/boards/arm/stm32c0/nucleo-c092rc/src/Make.defs new file mode 100644 index 0000000000000..74c27aa25f718 --- /dev/null +++ b/boards/arm/stm32c0/nucleo-c092rc/src/Make.defs @@ -0,0 +1,52 @@ +############################################################################ +# boards/arm/stm32c0/nucleo-c092rc/src/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +CSRCS = stm32_boot.c stm32_bringup.c + +ifeq ($(CONFIG_ARCH_LEDS),y) +CSRCS += stm32_autoleds.c +else +CSRCS += stm32_userleds.c +endif + +ifeq ($(CONFIG_ARCH_BUTTONS),y) +CSRCS += stm32_buttons.c +endif + +ifeq ($(CONFIG_ADC),y) +CSRCS += stm32_adc.c +endif + +ifeq ($(CONFIG_STM32_FDCAN),y) +ifeq ($(CONFIG_STM32_FDCAN_CHARDRIVER),y) +CSRCS += stm32_can.c +endif +ifeq ($(CONFIG_STM32_FDCAN_SOCKET),y) +CSRCS += stm32_cansock.c +endif +endif + +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32f0l0g0/nucleo-c092rc/src/nucleo-c092rc.h b/boards/arm/stm32c0/nucleo-c092rc/src/nucleo-c092rc.h similarity index 96% rename from boards/arm/stm32f0l0g0/nucleo-c092rc/src/nucleo-c092rc.h rename to boards/arm/stm32c0/nucleo-c092rc/src/nucleo-c092rc.h index c802a74b0171b..85f594562c755 100644 --- a/boards/arm/stm32f0l0g0/nucleo-c092rc/src/nucleo-c092rc.h +++ b/boards/arm/stm32c0/nucleo-c092rc/src/nucleo-c092rc.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-c092rc/src/nucleo-c092rc.h + * boards/arm/stm32c0/nucleo-c092rc/src/nucleo-c092rc.h * * SPDX-License-Identifier: Apache-2.0 * @@ -116,7 +116,7 @@ int stm32_adc_setup(void); * ****************************************************************************/ -#ifdef CONFIG_STM32F0L0G0_FDCAN_CHARDRIVER +#ifdef CONFIG_STM32_FDCAN_CHARDRIVER int stm32_can_setup(void); #endif @@ -128,7 +128,7 @@ int stm32_can_setup(void); * ****************************************************************************/ -#ifdef CONFIG_STM32F0L0G0_FDCAN_SOCKET +#ifdef CONFIG_STM32_FDCAN_SOCKET int stm32_cansock_setup(void); #endif diff --git a/boards/arm/stm32c0/nucleo-c092rc/src/stm32_adc.c b/boards/arm/stm32c0/nucleo-c092rc/src/stm32_adc.c new file mode 100644 index 0000000000000..777e65c018e7d --- /dev/null +++ b/boards/arm/stm32c0/nucleo-c092rc/src/stm32_adc.c @@ -0,0 +1,129 @@ +/**************************************************************************** + * boards/arm/stm32c0/nucleo-c092rc/src/stm32_adc.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include + +#include + +#include "stm32.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* The number of ADC channels in the conversion list */ + +#define ADC1_NCHANNELS 2 + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* Identifying number of each ADC channel (even if NCHANNELS is less ) */ + +static const uint8_t g_chanlist1[2] = +{ + 0, + 1, +}; + +/* Configurations of pins used by each ADC channel */ + +static const uint32_t g_pinlist1[2] = +{ + GPIO_ADC1_IN0_0, /* PA0/A0 */ + GPIO_ADC1_IN1_0 /* PA1/A1 */ +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_adc_setup + * + * Description: + * Initialize ADC and register the ADC driver. + * + ****************************************************************************/ + +int stm32_adc_setup(void) +{ + static bool initialized = false; + struct adc_dev_s *adc; + int ret; + int i; + + /* Check if we have already initialized */ + + if (!initialized) + { + /* Configure the pins as analog inputs for the selected channels */ + + for (i = 0; i < ADC1_NCHANNELS; i++) + { + stm32_configgpio(g_pinlist1[i]); + } + + /* Call stm32_adcinitialize() to get an instance of the ADC interface */ + + adc = stm32_adcinitialize(1, g_chanlist1, ADC1_NCHANNELS); + if (adc == NULL) + { + aerr("ERROR: Failed to get ADC interface 1\n"); + return -ENODEV; + } + + /* Register the ADC driver at "/dev/adc0" */ + + ret = adc_register("/dev/adc0", adc); + if (ret < 0) + { + aerr("ERROR: adc_register /dev/adc0 failed: %d\n", ret); + return ret; + } + + initialized = true; + } + + return OK; +} diff --git a/boards/arm/stm32c0/nucleo-c092rc/src/stm32_autoleds.c b/boards/arm/stm32c0/nucleo-c092rc/src/stm32_autoleds.c new file mode 100644 index 0000000000000..e43d5cf6749c6 --- /dev/null +++ b/boards/arm/stm32c0/nucleo-c092rc/src/stm32_autoleds.c @@ -0,0 +1,93 @@ +/**************************************************************************** + * boards/arm/stm32c0/nucleo-c092rc/src/stm32_autoleds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32_gpio.h" +#include "nucleo-c092rc.h" + +#ifdef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_autoled_initialize + ****************************************************************************/ + +void board_autoled_initialize(void) +{ + /* Configure LD1 and LD2 GPIO for output */ + + stm32_configgpio(GPIO_LD1); + stm32_configgpio(GPIO_LD2); +} + +/**************************************************************************** + * Name: board_autoled_on + ****************************************************************************/ + +void board_autoled_on(int led) +{ + if (led == BOARD_LED1) + { + stm32_gpiowrite(GPIO_LD1, true); + } + + if (led == BOARD_LED2) + { + stm32_gpiowrite(GPIO_LD2, false); + } +} + +/**************************************************************************** + * Name: board_autoled_off + ****************************************************************************/ + +void board_autoled_off(int led) +{ + if (led == BOARD_LED1) + { + stm32_gpiowrite(GPIO_LD1, false); + } + + if (led == BOARD_LED2) + { + stm32_gpiowrite(GPIO_LD2, true); + } +} + +#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32c0/nucleo-c092rc/src/stm32_boot.c b/boards/arm/stm32c0/nucleo-c092rc/src/stm32_boot.c new file mode 100644 index 0000000000000..d60d9f20b372a --- /dev/null +++ b/boards/arm/stm32c0/nucleo-c092rc/src/stm32_boot.c @@ -0,0 +1,83 @@ +/**************************************************************************** + * boards/arm/stm32c0/nucleo-c092rc/src/stm32_boot.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include "nucleo-c092rc.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_boardinitialize + * + * Description: + * All STM32 architectures must provide the following entry point. This + * entry point is called early in the initialization -- after all memory + * has been configured and mapped but before any devices have been + * initialized. + * + ****************************************************************************/ + +void stm32_boardinitialize(void) +{ +#ifdef CONFIG_ARCH_LEDS + /* Configure on-board LEDs if LED support has been selected. */ + + board_autoled_initialize(); +#endif + +#ifdef CONFIG_STM32_SPI + /* Configure SPI chip selects */ + + stm32_spidev_initialize(); +#endif +} + +/**************************************************************************** + * Name: board_late_initialize + * + * Description: + * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_late_initialize(). board_late_initialize() will + * be called immediately after up_initialize() is called and just before + * the initial application is started. This additional initialization + * phase may be used, for example, to initialize board-specific device + * drivers. + * + ****************************************************************************/ + +#ifdef CONFIG_BOARD_LATE_INITIALIZE +void board_late_initialize(void) +{ + stm32_bringup(); +} +#endif diff --git a/boards/arm/stm32c0/nucleo-c092rc/src/stm32_bringup.c b/boards/arm/stm32c0/nucleo-c092rc/src/stm32_bringup.c new file mode 100644 index 0000000000000..8f631a46a2c43 --- /dev/null +++ b/boards/arm/stm32c0/nucleo-c092rc/src/stm32_bringup.c @@ -0,0 +1,188 @@ +/**************************************************************************** + * boards/arm/stm32c0/nucleo-c092rc/src/stm32_bringup.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include +#include + +#ifdef CONFIG_INPUT_BUTTONS +# include +#endif + +#ifdef CONFIG_USERLED +# include +#endif + +#ifdef CONFIG_STM32_IWDG +# include +#endif + +#ifdef CONFIG_PULSECOUNT +# include "stm32_pulsecount.h" +#endif + +#ifdef CONFIG_SENSORS_QENCODER +# include "board_qencoder.h" +#endif + +#ifdef CONFIG_PWM +# include "board_pwm.h" +#endif + +#include + +#include "nucleo-c092rc.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_bringup + * + * Description: + * Perform architecture-specific initialization + * + * CONFIG_BOARD_LATE_INITIALIZE=y : + * Called from board_late_initialize(). + * + ****************************************************************************/ + +int stm32_bringup(void) +{ +#ifdef CONFIG_PULSECOUNT + struct pulsecount_lowerhalf_s *pulsecount; +#endif + int ret; + +#ifdef CONFIG_STM32_IWDG + /* Initialize the watchdog timer */ + + stm32_iwdginitialize("/dev/watchdog0", STM32_LSI_FREQUENCY); +#endif + +#ifdef CONFIG_PULSECOUNT + /* Initialize and register the pulse count driver. */ + + pulsecount = stm32_pulsecountinitialize(1); + if (pulsecount == NULL) + { + syslog(LOG_ERR, "ERROR: stm32_pulsecountinitialize failed\n"); + return -ENODEV; + } + + ret = pulsecount_register("/dev/pulsecount0", pulsecount); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: pulsecount_register failed: %d\n", ret); + return ret; + } +#endif + +#if !defined(CONFIG_ARCH_LEDS) && defined(CONFIG_USERLED_LOWER) + /* Register the LED driver */ + + ret = userled_lower_initialize(LED_DRIVER_PATH); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: userled_lower_initialize() failed: %d\n", ret); + return ret; + } +#endif + +#ifdef CONFIG_INPUT_BUTTONS + /* Register the BUTTON driver */ + + ret = btn_lower_initialize("/dev/buttons"); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: btn_lower_initialize() failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_ADC + /* Initialize ADC and register the ADC driver. */ + + ret = stm32_adc_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_adc_setup failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_PWM + /* Initialize PWM and register the PWM device. */ + + ret = stm32_pwm_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_pwm_setup failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_STM32_FDCAN_CHARDRIVER + /* Initialize CAN and register the CAN driver. */ + + ret = stm32_can_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_fdcan_setup failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_STM32_FDCAN_SOCKET + /* Initialize CAN socket interface */ + + ret = stm32_cansock_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_cansock_setup failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_SENSORS_QENCODER + /* Initialize and register the qencoder driver - TIM3 */ + + ret = board_qencoder_initialize(0, 3); + if (ret != OK) + { + syslog(LOG_ERR, + "ERROR: Failed to register the qencoder: %d\n", + ret); + return ret; + } +#endif + + UNUSED(ret); + return OK; +} diff --git a/boards/arm/stm32c0/nucleo-c092rc/src/stm32_buttons.c b/boards/arm/stm32c0/nucleo-c092rc/src/stm32_buttons.c new file mode 100644 index 0000000000000..c5659c8f6cc90 --- /dev/null +++ b/boards/arm/stm32c0/nucleo-c092rc/src/stm32_buttons.c @@ -0,0 +1,117 @@ +/**************************************************************************** + * boards/arm/stm32c0/nucleo-c092rc/src/stm32_buttons.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include +#include + +#include "stm32_gpio.h" +#include "nucleo-c092rc.h" + +#ifdef CONFIG_ARCH_BUTTONS + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_button_initialize + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. + * + ****************************************************************************/ + +uint32_t board_button_initialize(void) +{ + /* Configure the single button as an input. NOTE that EXTI interrupts are + * also configured for the pin. + */ + + stm32_configgpio(GPIO_BTN_USER); + return NUM_BUTTONS; +} + +/**************************************************************************** + * Name: board_buttons + ****************************************************************************/ + +uint32_t board_buttons(void) +{ + /* Check that state of each USER button. A LOW value means that the key is + * pressed. + */ + + bool released = stm32_gpioread(GPIO_BTN_USER); + return !released; +} + +/**************************************************************************** + * Button support. + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. + * + * After board_button_initialize() has been called, board_buttons() may be + * called to collect the state of all buttons. board_buttons() returns an + * 32-bit bit set with each bit associated with a button. See the + * BUTTON_*_BIT definitions in board.h for the meaning of each bit. + * + * board_button_irq() may be called to register an interrupt handler that + * will be called when a button is depressed or released. The ID value is a + * button enumeration value that uniquely identifies a button resource. See + * the BUTTON_* definitions in board.h for the meaning of enumeration + * value. + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_IRQBUTTONS +int board_button_irq(int id, xcpt_t irqhandler, void *arg) +{ + int ret = -EINVAL; + + if (id == BUTTON_USER) + { + ret = stm32_gpiosetevent(GPIO_BTN_USER, true, true, true, + irqhandler, arg); + } + + return ret; +} +#endif +#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/stm32c0/nucleo-c092rc/src/stm32_can.c b/boards/arm/stm32c0/nucleo-c092rc/src/stm32_can.c new file mode 100644 index 0000000000000..d2ba35278e02a --- /dev/null +++ b/boards/arm/stm32c0/nucleo-c092rc/src/stm32_can.c @@ -0,0 +1,78 @@ +/**************************************************************************** + * boards/arm/stm32c0/nucleo-c092rc/src/stm32_can.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include "stm32_fdcan.h" +#include "nucleo-c092rc.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_can_setup + * + * Description: + * Initialize CAN and register the CAN device + * + ****************************************************************************/ + +int stm32_can_setup(void) +{ + struct can_dev_s *can; + int ret; + + /* Configure STBY pin for output */ + + stm32_configgpio(GPIO_FDCAN_STBY); + + /* Set STBY pin low */ + + stm32_gpiowrite(GPIO_FDCAN_STBY, false); + + /* Call stm32_fdcaninitialize() to get an instance of the CAN interface */ + + can = stm32_fdcaninitialize(1); + if (can == NULL) + { + canerr("ERROR: Failed to get CAN interface\n"); + return -ENODEV; + } + + /* Register the CAN driver at "/dev/can0" */ + + ret = can_register("/dev/can0", can); + if (ret < 0) + { + canerr("ERROR: can_register failed: %d\n", ret); + return ret; + } + + return OK; +} diff --git a/boards/arm/stm32c0/nucleo-c092rc/src/stm32_cansock.c b/boards/arm/stm32c0/nucleo-c092rc/src/stm32_cansock.c new file mode 100644 index 0000000000000..8a24931b13dfe --- /dev/null +++ b/boards/arm/stm32c0/nucleo-c092rc/src/stm32_cansock.c @@ -0,0 +1,68 @@ +/**************************************************************************** + * boards/arm/stm32c0/nucleo-c092rc/src/stm32_cansock.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include "stm32_fdcan.h" +#include "nucleo-c092rc.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_cansock_setup + * + * Description: + * Initialize CAN socket interface + * + ****************************************************************************/ + +int stm32_cansock_setup(void) +{ + int ret; + + /* Configure STBY pin for output */ + + stm32_configgpio(GPIO_FDCAN_STBY); + + /* Set STBY pin low */ + + stm32_gpiowrite(GPIO_FDCAN_STBY, false); + + /* Call stm32_fdcaninitialize() to get an instance of the FDCAN interface */ + + ret = stm32_fdcansockinitialize(1); + if (ret < 0) + { + canerr("ERROR: Failed to get FDCAN interface %d\n", ret); + return ret; + } + + return OK; +} diff --git a/boards/arm/stm32c0/nucleo-c092rc/src/stm32_userleds.c b/boards/arm/stm32c0/nucleo-c092rc/src/stm32_userleds.c new file mode 100644 index 0000000000000..5740dc20b9066 --- /dev/null +++ b/boards/arm/stm32c0/nucleo-c092rc/src/stm32_userleds.c @@ -0,0 +1,172 @@ +/**************************************************************************** + * boards/arm/stm32c0/nucleo-c092rc/src/stm32_userleds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32_gpio.h" +#include "nucleo-c092rc.h" + +#ifndef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/* LED Power Management */ + +#ifdef CONFIG_PM +static void led_pm_notify(struct pm_callback_s *cb, int domain, + enum pm_state_e pmstate); +static int led_pm_prepare(struct pm_callback_s *cb, int domain, + enum pm_state_e pmstate); +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#ifdef CONFIG_PM +static struct pm_callback_s g_ledscb = +{ + .notify = led_pm_notify, + .prepare = led_pm_prepare, +}; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: led_pm_notify + * + * Description: + * Notify the driver of new power state. This callback is called after + * all drivers have had the opportunity to prepare for the new power state. + * + ****************************************************************************/ + +#ifdef CONFIG_PM +static void led_pm_notify(struct pm_callback_s *cb, int domain, + enum pm_state_e pmstate) +{ +} +#endif + +/**************************************************************************** + * Name: led_pm_prepare + * + * Description: + * Request the driver to prepare for a new power state. This is a warning + * that the system is about to enter into a new power state. The driver + * should begin whatever operations that may be required to enter power + * state. The driver may abort the state change mode by returning a + * non-zero value from the callback function. + * + ****************************************************************************/ + +#ifdef CONFIG_PM +static int led_pm_prepare(struct pm_callback_s *cb, int domain, + enum pm_state_e pmstate) +{ + /* No preparation to change power modes is required by the LEDs driver. + * We always accept the state change by returning OK. + */ + + return OK; +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_userled_initialize + ****************************************************************************/ + +uint32_t board_userled_initialize(void) +{ + /* Configure LD1 and LD2 GPIO for output */ + + stm32_configgpio(GPIO_LD1); + stm32_configgpio(GPIO_LD2); + return BOARD_NLEDS; +} + +/**************************************************************************** + * Name: board_userled + ****************************************************************************/ + +void board_userled(int led, bool ledon) +{ + if (led == BOARD_LED1) + { + stm32_gpiowrite(GPIO_LD1, ledon); + } + + if (led == BOARD_LED2) + { + stm32_gpiowrite(GPIO_LD2, !ledon); + } +} + +/**************************************************************************** + * Name: board_userled_all + ****************************************************************************/ + +void board_userled_all(uint32_t ledset) +{ + stm32_gpiowrite(GPIO_LD1, (ledset & BOARD_LED1_BIT) != 0); + stm32_gpiowrite(GPIO_LD2, (ledset & BOARD_LED2_BIT) == 0); +} + +/**************************************************************************** + * Name: stm32_led_pminitialize + ****************************************************************************/ + +#ifdef CONFIG_PM +void stm32_led_pminitialize(void) +{ + /* Register to receive power management callbacks */ + + int ret = pm_register(&g_ledscb); + DEBUGASSERT(ret == OK); + UNUSED(ret); +} +#endif /* CONFIG_PM */ + +#endif /* !CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32f0/common/CMakeLists.txt b/boards/arm/stm32f0/common/CMakeLists.txt new file mode 100644 index 0000000000000..55e8f2f019110 --- /dev/null +++ b/boards/arm/stm32f0/common/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32f0/common/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(${NUTTX_DIR}/boards/arm/common/stm32 stm32_common) diff --git a/boards/arm/stm32f0/common/Kconfig b/boards/arm/stm32f0/common/Kconfig new file mode 100644 index 0000000000000..5c48f62a0258b --- /dev/null +++ b/boards/arm/stm32f0/common/Kconfig @@ -0,0 +1,6 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# + +source "boards/arm/common/stm32/Kconfig" diff --git a/boards/arm/stm32f0/common/Makefile b/boards/arm/stm32f0/common/Makefile new file mode 100644 index 0000000000000..160e05f23b9ae --- /dev/null +++ b/boards/arm/stm32f0/common/Makefile @@ -0,0 +1,39 @@ +############################################################################# +# boards/arm/stm32f0/common/Makefile +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################# + +include $(TOPDIR)/Make.defs + +STM32_BOARD_COMMON_DIR := $(TOPDIR)$(DELIM)boards$(DELIM)arm$(DELIM)common$(DELIM)stm32 +STM32_COMMON_SRCDIR := $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)common$(DELIM)stm32 + +include board/Make.defs +include $(STM32_BOARD_COMMON_DIR)$(DELIM)src$(DELIM)Make.defs + +DEPPATH += --dep-path board + +include $(TOPDIR)/boards/Board.mk + +ARCHSRCDIR = $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src +BOARDDIR = $(ARCHSRCDIR)$(DELIM)board +CFLAGS += ${INCDIR_PREFIX}$(BOARDDIR)$(DELIM)include +CFLAGS += ${INCDIR_PREFIX}$(STM32_COMMON_SRCDIR) +CXXFLAGS += ${INCDIR_PREFIX}$(STM32_COMMON_SRCDIR) diff --git a/boards/arm/stm32f0/nucleo-f072rb/CMakeLists.txt b/boards/arm/stm32f0/nucleo-f072rb/CMakeLists.txt new file mode 100644 index 0000000000000..f4c468079f835 --- /dev/null +++ b/boards/arm/stm32f0/nucleo-f072rb/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32f0/nucleo-f072rb/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/arm/stm32f0l0g0/nucleo-f072rb/Kconfig b/boards/arm/stm32f0/nucleo-f072rb/Kconfig similarity index 100% rename from boards/arm/stm32f0l0g0/nucleo-f072rb/Kconfig rename to boards/arm/stm32f0/nucleo-f072rb/Kconfig diff --git a/boards/arm/stm32f0/nucleo-f072rb/configs/nsh/defconfig b/boards/arm/stm32f0/nucleo-f072rb/configs/nsh/defconfig new file mode 100644 index 0000000000000..4a266b9184f3a --- /dev/null +++ b/boards/arm/stm32f0/nucleo-f072rb/configs/nsh/defconfig @@ -0,0 +1,60 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_FS_PROCFS_EXCLUDE_BLOCKS is not set +# CONFIG_FS_PROCFS_EXCLUDE_ENVIRON is not set +# CONFIG_FS_PROCFS_EXCLUDE_MEMDUMP is not set +# CONFIG_FS_PROCFS_EXCLUDE_MEMINFO is not set +# CONFIG_FS_PROCFS_EXCLUDE_MOUNT is not set +# CONFIG_FS_PROCFS_EXCLUDE_MOUNTS is not set +# CONFIG_FS_PROCFS_EXCLUDE_PROCESS is not set +# CONFIG_FS_PROCFS_EXCLUDE_UPTIME is not set +# CONFIG_FS_PROCFS_EXCLUDE_USAGE is not set +# CONFIG_FS_PROCFS_EXCLUDE_VERSION is not set +# CONFIG_NSH_DISABLEBG is not set +# CONFIG_NSH_DISABLE_EXEC is not set +# CONFIG_NSH_DISABLE_EXIT is not set +# CONFIG_NSH_DISABLE_HEXDUMP is not set +# CONFIG_NSH_DISABLE_XD is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nucleo-f072rb" +CONFIG_ARCH_BOARD_NUCLEO_F072RB=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f0" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F072RB=y +CONFIG_ARCH_CHIP_STM32F0=y +CONFIG_ARCH_IRQBUTTONS=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=2796 +CONFIG_BUILTIN=y +CONFIG_DEFAULT_SMALL=y +CONFIG_FS_PROCFS=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=1536 +CONFIG_MM_SMALL=y +CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=64 +CONFIG_NUNGET_CHARS=0 +CONFIG_POSIX_SPAWN_DEFAULT_STACKSIZE=1536 +CONFIG_PTHREAD_STACK_DEFAULT=1536 +CONFIG_RAM_SIZE=16384 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=19 +CONFIG_START_MONTH=5 +CONFIG_START_YEAR=2013 +CONFIG_STM32_PWR=y +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART2_RXBUFSIZE=32 +CONFIG_USART2_SERIAL_CONSOLE=y +CONFIG_USART2_TXBUFSIZE=32 diff --git a/boards/arm/stm32f0/nucleo-f072rb/include/board.h b/boards/arm/stm32f0/nucleo-f072rb/include/board.h new file mode 100644 index 0000000000000..ecbb09cd8db12 --- /dev/null +++ b/boards/arm/stm32f0/nucleo-f072rb/include/board.h @@ -0,0 +1,244 @@ +/**************************************************************************** + * boards/arm/stm32f0/nucleo-f072rb/include/board.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_STM32F0L0G0_NUCLEO_F072RB_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32F0L0G0_NUCLEO_F072RB_INCLUDE_BOARD_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#ifndef __ASSEMBLY__ +# include +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Clocking *****************************************************************/ + +/* Four different clock sources can be used to drive the system clock + * (SYSCLK): + * + * - HSI high-speed internal oscillator clock + * Generated from an internal 8 MHz RC oscillator + * - HSE high-speed external oscillator clock + * Normally driven by an external crystal (X3). However, this crystal is + * not fitted on the Nucleo-F072RB board. + * - PLL clock + * - MSI multispeed internal oscillator clock + * The MSI clock signal is generated from an internal RC oscillator. Seven + * frequency ranges are available: 65.536 kHz, 131.072 kHz, 262.144 kHz, + * 524.288 kHz, 1.048 MHz, 2.097 MHz (default value) and 4.194 MHz. + * + * The devices have the following two secondary clock sources + * - LSI low-speed internal RC clock + * Drives the watchdog and RTC. Approximately 37KHz + * - LSE low-speed external oscillator clock + * Driven by 32.768KHz crystal (X2) on the OSC32_IN and OSC32_OUT pins. + */ + +#define STM32_BOARD_XTAL 8000000ul /* X3 on board (not fitted)*/ + +#define STM32_HSI_FREQUENCY 8000000ul /* Approximately 8MHz */ +#define STM32_HSI14_FREQUENCY 14000000ul /* HSI14 for ADC */ +#define STM32_HSI48_FREQUENCY 48000000ul /* HSI48 for USB, only some STM32F0xx */ +#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL +#define STM32_LSI_FREQUENCY 40000 /* Approximately 40KHz */ +#define STM32_LSE_FREQUENCY 32768 /* X2 on board */ + +/* PLL Configuration + * + * - PLL source is HSI -> 8MHz input (nominal) + * - PLL source predivider 2 -> 4MHz divided down PLL VCO clock output + * - PLL multiplier is 12 -> 48MHz PLL VCO clock output (for USB) + * + * Resulting SYSCLK frequency is 8MHz x 12 / 2 = 48MHz + * + * USB: + * If the USB interface is used in the application, it requires a precise + * 48MHz clock which can be generated from either the (1) the internal + * main PLL with the HSE clock source using an HSE crystal oscillator. In + * this case, the PLL VCO clock (defined by STM32_CFGR_PLLMUL) must be + * programmed to output a 96 MHz frequency. This is required to provide a + * 48MHz clock to the (USBCLK = PLLVCO/2). Or (2) by using the internal + * 48MHz oscillator in automatic trimming mode. The synchronization for + * this oscillator can be taken from the USB data stream itself (SOF + * signalization) which allows crystal-less operation. + * SYSCLK + * The system clock is derived from the PLL VCO divided by the output + * division factor. + * Limitations: + * - 96 MHz as PLLVCO when the product is in range 1 (1.8V), + * - 48 MHz as PLLVCO when the product is in range 2 (1.5V), + * - 24 MHz when the product is in range 3 (1.2V). + * - Output division to avoid exceeding 32 MHz as SYSCLK. + * - The minimum input clock frequency for PLL is 2 MHz (when using HSE as + * PLL source). + */ + +#define STM32_CFGR_PLLSRC RCC_CFGR_PLLSRC_HSId2 /* Source is HSI/2 */ +#define STM32_PLLSRC_FREQUENCY (STM32_HSI_FREQUENCY/2) /* 8MHz / 2 = 4MHz */ +#ifdef CONFIG_STM32_USB +# undef STM32_CFGR2_PREDIV /* Not used with source HSI/2 */ +# define STM32_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx12 /* PLLMUL = 12 */ +# define STM32_PLL_FREQUENCY (12*STM32_PLLSRC_FREQUENCY) /* PLL VCO Frequency is 48MHz */ +#else +# undef STM32_CFGR2_PREDIV /* Not used with source HSI/2 */ +# define STM32_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx12 /* PLLMUL = 12 */ +# define STM32_PLL_FREQUENCY (12*STM32_PLLSRC_FREQUENCY) /* PLL VCO Frequency is 48MHz */ +#endif + +/* Use the PLL and set the SYSCLK source to be the divided down PLL VCO + * output frequency (STM32_PLL_FREQUENCY divided by the PLLDIV value). + */ + +#define STM32_SYSCLK_SW RCC_CFGR_SW_PLL /* Use the PLL as the SYSCLK */ +#define STM32_SYSCLK_SWS RCC_CFGR_SWS_PLL +#ifdef CONFIG_STM32_USB +# define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY /* SYSCLK frequency is PLL VCO = 48MHz */ +#else +# define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY /* SYSCLK frequency is PLL VCO = 48MHz */ +#endif + +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY + +/* APB1 clock (PCLK1) is HCLK (48MHz) */ + +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY) + +/* APB2 clock (PCLK2) is HCLK (48MHz) */ + +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK +#define STM32_PCLK2_FREQUENCY STM32_HCLK_FREQUENCY +#define STM32_APB2_CLKIN (STM32_PCLK2_FREQUENCY) + +/* APB1 timers 1-3, 6-7, and 14-17 will receive PCLK1 */ + +#define STM32_APB1_TIM1_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM2_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (STM32_PCLK1_FREQUENCY) + +#define STM32_APB1_TIM6_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (STM32_PCLK1_FREQUENCY) + +#define STM32_APB1_TIM14_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM15_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM16_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM17_CLKIN (STM32_PCLK1_FREQUENCY) + +/* LED definitions **********************************************************/ + +/* LEDs + * + * The Nucleo-64 board has one user controllable LED, User LD2. This green + * LED is a user LED connected to Arduino signal D13 corresponding to STM32 + * I/O PA5 (PB13 on other some other Nucleo-64 boards). + * + * - When the I/O is HIGH value, the LED is on + * - When the I/O is LOW, the LED is off + */ + +/* LED index values for use with board_userled() */ + +#define BOARD_LD2 0 +#define BOARD_NLEDS 1 + +/* LED bits for use with board_userled_all() */ + +#define BOARD_LD2_BIT (1 << BOARD_LD2) + +/* These LEDs are not used by the board port unless CONFIG_ARCH_LEDS is + * defined. In that case, the usage by the board port is defined in + * include/board.h and src/sam_leds.c. The LEDs are used to encode OS-related + * events as follows when the red LED (PE24) is available: + * + * SYMBOL Meaning LD2 + * ------------------- ----------------------- ----------- + * LED_STARTED NuttX has been started OFF + * LED_HEAPALLOCATE Heap has been allocated OFF + * LED_IRQSENABLED Interrupts enabled OFF + * LED_STACKCREATED Idle stack created ON + * LED_INIRQ In an interrupt No change + * LED_SIGNAL In a signal handler No change + * LED_ASSERTION An assertion failed No change + * LED_PANIC The system has crashed Blinking + * LED_IDLE MCU is in sleep mode Not used + * + * Thus if LD2, NuttX has successfully booted and is, apparently, running + * normally. If LD2 is flashing at approximately 2Hz, then a fatal error + * has been detected and the system has halted. + */ + +#define LED_STARTED 0 +#define LED_HEAPALLOCATE 0 +#define LED_IRQSENABLED 0 +#define LED_STACKCREATED 1 +#define LED_INIRQ 2 +#define LED_SIGNAL 2 +#define LED_ASSERTION 2 +#define LED_PANIC 1 + +/* Button definitions *******************************************************/ + +/* Buttons + * + * B1 USER: the user button is connected to the I/O PC13 (pin 2) of the STM32 + * microcontroller. + */ + +#define BUTTON_USER 0 +#define NUM_BUTTONS 1 + +#define BUTTON_USER_BIT (1 << BUTTON_USER) + +/* Alternate Pin Functions **************************************************/ + +/* USART 1 + * PA9 - CN10 pin 21 + * PA10 - CN10 pin 33 + */ + +#define GPIO_USART1_TX (GPIO_USART1_TX_2|GPIO_SPEED_HIGH) /* PA9 */ +#define GPIO_USART1_RX (GPIO_USART1_RX_2|GPIO_SPEED_HIGH) /* PA10 */ + +/* USART 2 - St-Link VCOM */ + +#define GPIO_USART2_TX (GPIO_USART2_TX_3|GPIO_SPEED_HIGH) /* PA2 */ +#define GPIO_USART2_RX (GPIO_USART2_RX_3|GPIO_SPEED_HIGH) /* PA3 */ + +/* I2C1 + * PB8 - CN5 pin 10, D15 + * PB9 - CN5 pin 9, D14 + */ + +#define GPIO_I2C1_SCL (GPIO_I2C1_SCL_2|GPIO_SPEED_LOW) /* PB8 */ +#define GPIO_I2C1_SDA (GPIO_I2C1_SDA_2|GPIO_SPEED_LOW) /* PB9 */ + +/* I2C2 */ + +#endif /* __BOARDS_ARM_STM32F0L0G0_NUCLEO_F072RB_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32f0/nucleo-f072rb/scripts/Make.defs b/boards/arm/stm32f0/nucleo-f072rb/scripts/Make.defs new file mode 100644 index 0000000000000..8565d214ef4e7 --- /dev/null +++ b/boards/arm/stm32f0/nucleo-f072rb/scripts/Make.defs @@ -0,0 +1,41 @@ +############################################################################ +# boards/arm/stm32f0/nucleo-f072rb/scripts/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/.config +include $(TOPDIR)/tools/Config.mk +include $(TOPDIR)/arch/arm/src/armv6-m/Toolchain.defs + +LDSCRIPT = flash.ld +ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) + +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32f0/nucleo-f072rb/scripts/flash.ld b/boards/arm/stm32f0/nucleo-f072rb/scripts/flash.ld new file mode 100644 index 0000000000000..ae6006b5cdbcb --- /dev/null +++ b/boards/arm/stm32f0/nucleo-f072rb/scripts/flash.ld @@ -0,0 +1,111 @@ +/**************************************************************************** + * boards/arm/stm32f0/nucleo-f072rb/scripts/flash.ld + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* The STM32F072RBT6 has 128KB of FLASH beginning at address 0x0800:0000 and + * 16Kb of SRAM at address 0x20000000. + * + * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 + * where the code expects to begin execution by jumping to the entry point in + * the 0x0800:0000 address range. + */ + +MEMORY +{ + flash (rx) : ORIGIN = 0x08000000, LENGTH = 128K + sram (rwx) : ORIGIN = 0x20000000, LENGTH = 16K +} + +OUTPUT_ARCH(arm) +EXTERN(_vectors) +ENTRY(_stext) + +SECTIONS +{ + .text : + { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > flash + + .init_section : ALIGN(4) { + _sinit = ABSOLUTE(.); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) + _einit = ABSOLUTE(.); + } > flash + + .ARM.extab ALIGN(4): { + *(.ARM.extab*) + } > flash + + .ARM.exidx : ALIGN(4) { + __exidx_start = ABSOLUTE(.); + *(.ARM.exidx*) + __exidx_end = ABSOLUTE(.); + } > flash + + _eronly = ABSOLUTE(.); + + .data : ALIGN(4) { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > sram AT > flash + + .bss : ALIGN(4) { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(8); + _ebss = ABSOLUTE(.); + } > sram + + /* Stabs debugging sections. */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/stm32f0/nucleo-f072rb/src/CMakeLists.txt b/boards/arm/stm32f0/nucleo-f072rb/src/CMakeLists.txt new file mode 100644 index 0000000000000..26e316b2b248e --- /dev/null +++ b/boards/arm/stm32f0/nucleo-f072rb/src/CMakeLists.txt @@ -0,0 +1,37 @@ +# ############################################################################## +# boards/arm/stm32f0/nucleo-f072rb/src/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(SRCS stm32_boot.c stm32_bringup.c) + +if(CONFIG_ARCH_LEDS) + list(APPEND SRCS stm32_autoleds.c) +else() + list(APPEND SRCS stm32_userleds.c) +endif() + +if(CONFIG_ARCH_BUTTONS) + list(APPEND SRCS stm32_buttons.c) +endif() + +target_sources(board PRIVATE ${SRCS}) + +set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/flash.ld") diff --git a/boards/arm/stm32f0/nucleo-f072rb/src/Make.defs b/boards/arm/stm32f0/nucleo-f072rb/src/Make.defs new file mode 100644 index 0000000000000..8d74dbfdb4c3f --- /dev/null +++ b/boards/arm/stm32f0/nucleo-f072rb/src/Make.defs @@ -0,0 +1,39 @@ +############################################################################ +# boards/arm/stm32f0/nucleo-f072rb/src/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +CSRCS = stm32_boot.c stm32_bringup.c + +ifeq ($(CONFIG_ARCH_LEDS),y) +CSRCS += stm32_autoleds.c +else +CSRCS += stm32_userleds.c +endif + +ifeq ($(CONFIG_ARCH_BUTTONS),y) +CSRCS += stm32_buttons.c +endif + +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32f0l0g0/nucleo-f072rb/src/nucleo-f072rb.h b/boards/arm/stm32f0/nucleo-f072rb/src/nucleo-f072rb.h similarity index 93% rename from boards/arm/stm32f0l0g0/nucleo-f072rb/src/nucleo-f072rb.h rename to boards/arm/stm32f0/nucleo-f072rb/src/nucleo-f072rb.h index 6fa9242000a11..d4bf7700d1023 100644 --- a/boards/arm/stm32f0l0g0/nucleo-f072rb/src/nucleo-f072rb.h +++ b/boards/arm/stm32f0/nucleo-f072rb/src/nucleo-f072rb.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-f072rb/src/nucleo-f072rb.h + * boards/arm/stm32f0/nucleo-f072rb/src/nucleo-f072rb.h * * SPDX-License-Identifier: Apache-2.0 * @@ -42,14 +42,14 @@ /* How many SPI modules does this chip support? */ #if STM32_NSPI < 1 -# undef CONFIG_STM32F0L0G0_SPI1 -# undef CONFIG_STM32F0L0G0_SPI2 -# undef CONFIG_STM32F0L0G0_SPI3 +# undef CONFIG_STM32_SPI1 +# undef CONFIG_STM32_SPI2 +# undef CONFIG_STM32_SPI3 #elif STM32_NSPI < 2 -# undef CONFIG_STM32F0L0G0_SPI2 -# undef CONFIG_STM32F0L0G0_SPI3 +# undef CONFIG_STM32_SPI2 +# undef CONFIG_STM32_SPI3 #elif STM32_NSPI < 3 -# undef CONFIG_STM32F0L0G0_SPI3 +# undef CONFIG_STM32_SPI3 #endif /* Nucleo-F072RB GPIOs ******************************************************/ diff --git a/boards/arm/stm32f0/nucleo-f072rb/src/stm32_autoleds.c b/boards/arm/stm32f0/nucleo-f072rb/src/stm32_autoleds.c new file mode 100644 index 0000000000000..dbd5f76182e73 --- /dev/null +++ b/boards/arm/stm32f0/nucleo-f072rb/src/stm32_autoleds.c @@ -0,0 +1,82 @@ +/**************************************************************************** + * boards/arm/stm32f0/nucleo-f072rb/src/stm32_autoleds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32_gpio.h" +#include "nucleo-f072rb.h" + +#ifdef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_autoled_initialize + ****************************************************************************/ + +void board_autoled_initialize(void) +{ + /* Configure LD2 GPIO for output */ + + stm32_configgpio(GPIO_LD2); +} + +/**************************************************************************** + * Name: board_autoled_on + ****************************************************************************/ + +void board_autoled_on(int led) +{ + if (led == 1) + { + stm32_gpiowrite(GPIO_LD2, true); + } +} + +/**************************************************************************** + * Name: board_autoled_off + ****************************************************************************/ + +void board_autoled_off(int led) +{ + if (led == 1) + { + stm32_gpiowrite(GPIO_LD2, false); + } +} + +#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32f0/nucleo-f072rb/src/stm32_boot.c b/boards/arm/stm32f0/nucleo-f072rb/src/stm32_boot.c new file mode 100644 index 0000000000000..e1c37566fda8b --- /dev/null +++ b/boards/arm/stm32f0/nucleo-f072rb/src/stm32_boot.c @@ -0,0 +1,81 @@ +/**************************************************************************** + * boards/arm/stm32f0/nucleo-f072rb/src/stm32_boot.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include +#include + +#include "arm_internal.h" +#include "nucleo-f072rb.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_boardinitialize + * + * Description: + * All STM32 architectures must provide the following entry point. + * This entry point is called early in the initialization -- after all + * memory has been configured and mapped but before any devices have been + * initialized. + * + ****************************************************************************/ + +void stm32_boardinitialize(void) +{ +#ifdef CONFIG_ARCH_LEDS + /* Configure on-board LEDs if LED support has been selected. */ + + board_autoled_initialize(); +#endif +} + +/**************************************************************************** + * Name: board_late_initialize + * + * Description: + * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_late_initialize(). board_late_initialize() will be + * called immediately after up_initialize() is called and just before the + * initial application is started. This additional initialization phase + * may be used, for example, to initialize board-specific device drivers. + * + ****************************************************************************/ + +#ifdef CONFIG_BOARD_LATE_INITIALIZE +void board_late_initialize(void) +{ + /* Perform board-specific initialization here if so configured */ + + stm32_bringup(); +} +#endif diff --git a/boards/arm/stm32f0/nucleo-f072rb/src/stm32_bringup.c b/boards/arm/stm32f0/nucleo-f072rb/src/stm32_bringup.c new file mode 100644 index 0000000000000..ccf38aeb624f8 --- /dev/null +++ b/boards/arm/stm32f0/nucleo-f072rb/src/stm32_bringup.c @@ -0,0 +1,101 @@ +/**************************************************************************** + * boards/arm/stm32f0/nucleo-f072rb/src/stm32_bringup.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include + +#include "stm32_i2c.h" +#include "nucleo-f072rb.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#undef HAVE_I2C_DRIVER +#if defined(CONFIG_STM32_I2C1) && defined(CONFIG_I2C_DRIVER) +# define HAVE_I2C_DRIVER 1 +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_bringup + * + * Description: + * Perform architecture-specific initialization + * + * CONFIG_BOARD_LATE_INITIALIZE=y : + * Called from board_late_initialize(). + * + ****************************************************************************/ + +int stm32_bringup(void) +{ +#ifdef HAVE_I2C_DRIVER + struct i2c_master_s *i2c; +#endif + int ret; + +#ifdef CONFIG_FS_PROCFS + /* Mount the procfs file system */ + + ret = nx_mount(NULL, "/proc", "procfs", 0, NULL); + if (ret < 0) + { + ferr("ERROR: Failed to mount procfs at /proc: %d\n", ret); + } +#endif + +#ifdef HAVE_I2C_DRIVER + /* Get the I2C lower half instance */ + + i2c = stm32_i2cbus_initialize(1); + if (i2c == NULL) + { + i2cerr("ERROR: Initialize I2C1: %d\n", ret); + } + else + { + /* Register the I2C character driver */ + + ret = i2c_register(i2c, 1); + if (ret < 0) + { + i2cerr("ERROR: Failed to register I2C1 device: %d\n", ret); + } + } +#endif + + UNUSED(ret); + return OK; +} diff --git a/boards/arm/stm32f0/nucleo-f072rb/src/stm32_buttons.c b/boards/arm/stm32f0/nucleo-f072rb/src/stm32_buttons.c new file mode 100644 index 0000000000000..8bca5ed46ca84 --- /dev/null +++ b/boards/arm/stm32f0/nucleo-f072rb/src/stm32_buttons.c @@ -0,0 +1,117 @@ +/**************************************************************************** + * boards/arm/stm32f0/nucleo-f072rb/src/stm32_buttons.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include +#include + +#include "stm32_gpio.h" +#include "nucleo-f072rb.h" + +#ifdef CONFIG_ARCH_BUTTONS + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_button_initialize + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. + * + ****************************************************************************/ + +uint32_t board_button_initialize(void) +{ + /* Configure the single button as an input. NOTE that EXTI interrupts are + * also configured for the pin. + */ + + stm32_configgpio(GPIO_BTN_USER); + return NUM_BUTTONS; +} + +/**************************************************************************** + * Name: board_buttons + ****************************************************************************/ + +uint32_t board_buttons(void) +{ + /* Check that state of each USER button. A LOW value means that the key is + * pressed. + */ + + bool released = stm32_gpioread(GPIO_BTN_USER); + return !released; +} + +/**************************************************************************** + * Button support. + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. + * + * After board_button_initialize() has been called, board_buttons() may be + * called to collect the state of all buttons. board_buttons() returns an + * 32-bit bit set with each bit associated with a button. See the + * BUTTON_*_BIT definitions in board.h for the meaning of each bit. + * + * board_button_irq() may be called to register an interrupt handler that + * will be called when a button is depressed or released. The ID value is a + * button enumeration value that uniquely identifies a button resource. See + * the BUTTON_* definitions in board.h for the meaning of enumeration + * value. + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_IRQBUTTONS +int board_button_irq(int id, xcpt_t irqhandler, void *arg) +{ + int ret = -EINVAL; + + if (id == BUTTON_USER) + { + ret = stm32_gpiosetevent(GPIO_BTN_USER, true, true, true, + irqhandler, arg); + } + + return ret; +} +#endif +#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/stm32f0/nucleo-f072rb/src/stm32_userleds.c b/boards/arm/stm32f0/nucleo-f072rb/src/stm32_userleds.c new file mode 100644 index 0000000000000..9715fe31a22dc --- /dev/null +++ b/boards/arm/stm32f0/nucleo-f072rb/src/stm32_userleds.c @@ -0,0 +1,197 @@ +/**************************************************************************** + * boards/arm/stm32f0/nucleo-f072rb/src/stm32_userleds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32_gpio.h" +#include "nucleo-f072rb.h" + +#ifndef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/* LED Power Management */ + +#ifdef CONFIG_PM +static void led_pm_notify(struct pm_callback_s *cb, int domain, + enum pm_state_e pmstate); +static int led_pm_prepare(struct pm_callback_s *cb, int domain, + enum pm_state_e pmstate); +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#ifdef CONFIG_PM +static struct pm_callback_s g_ledscb = +{ + .notify = led_pm_notify, + .prepare = led_pm_prepare, +}; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: led_pm_notify + * + * Description: + * Notify the driver of new power state. This callback is called after + * all drivers have had the opportunity to prepare for the new power state. + * + ****************************************************************************/ + +#ifdef CONFIG_PM +static void led_pm_notify(struct pm_callback_s *cb, int domain, + enum pm_state_e pmstate) +{ + switch (pmstate) + { + case PM_NORMAL: + { + /* Restore normal LEDs operation */ + } + break; + + case PM_IDLE: + { + /* Entering IDLE mode - Turn leds off */ + } + break; + + case PM_STANDBY: + { + /* Entering STANDBY mode - Logic for PM_STANDBY goes here */ + } + break; + + case PM_SLEEP: + { + /* Entering SLEEP mode - Logic for PM_SLEEP goes here */ + } + break; + + default: + { + /* Should not get here */ + } + break; + } +} +#endif + +/**************************************************************************** + * Name: led_pm_prepare + * + * Description: + * Request the driver to prepare for a new power state. This is a warning + * that the system is about to enter into a new power state. The driver + * should begin whatever operations that may be required to enter power + * state. The driver may abort the state change mode by returning a + * non-zero value from the callback function. + * + ****************************************************************************/ + +#ifdef CONFIG_PM +static int led_pm_prepare(struct pm_callback_s *cb, int domain, + enum pm_state_e pmstate) +{ + /* No preparation to change power modes is required by the LEDs driver. + * We always accept the state change by returning OK. + */ + + return OK; +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_userled_initialize + ****************************************************************************/ + +uint32_t board_userled_initialize(void) +{ + /* Configure LD2 GPIO for output */ + + stm32_configgpio(GPIO_LD2); + return BOARD_NLEDS; +} + +/**************************************************************************** + * Name: board_userled + ****************************************************************************/ + +void board_userled(int led, bool ledon) +{ + if (led == BOARD_LD2) + { + stm32_gpiowrite(GPIO_LD2, ledon); + } +} + +/**************************************************************************** + * Name: board_userled_all + ****************************************************************************/ + +void board_userled_all(uint32_t ledset) +{ + stm32_gpiowrite(GPIO_LD2, (ledset & BOARD_LD2_BIT) != 0); +} + +/**************************************************************************** + * Name: stm32_led_pminitialize + ****************************************************************************/ + +#ifdef CONFIG_PM +void stm32_led_pminitialize(void) +{ + /* Register to receive power management callbacks */ + + int ret = pm_register(&g_ledscb); + DEBUGASSERT(ret == OK); + UNUSED(ret); +} +#endif /* CONFIG_PM */ + +#endif /* !CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32f0/nucleo-f091rc/CMakeLists.txt b/boards/arm/stm32f0/nucleo-f091rc/CMakeLists.txt new file mode 100644 index 0000000000000..7b9d3c1af756e --- /dev/null +++ b/boards/arm/stm32f0/nucleo-f091rc/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32f0/nucleo-f091rc/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/arm/stm32f0l0g0/nucleo-f091rc/Kconfig b/boards/arm/stm32f0/nucleo-f091rc/Kconfig similarity index 100% rename from boards/arm/stm32f0l0g0/nucleo-f091rc/Kconfig rename to boards/arm/stm32f0/nucleo-f091rc/Kconfig diff --git a/boards/arm/stm32f0/nucleo-f091rc/configs/nsh/defconfig b/boards/arm/stm32f0/nucleo-f091rc/configs/nsh/defconfig new file mode 100644 index 0000000000000..1cd0f3abf3969 --- /dev/null +++ b/boards/arm/stm32f0/nucleo-f091rc/configs/nsh/defconfig @@ -0,0 +1,60 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_FS_PROCFS_EXCLUDE_BLOCKS is not set +# CONFIG_FS_PROCFS_EXCLUDE_ENVIRON is not set +# CONFIG_FS_PROCFS_EXCLUDE_MEMDUMP is not set +# CONFIG_FS_PROCFS_EXCLUDE_MEMINFO is not set +# CONFIG_FS_PROCFS_EXCLUDE_MOUNT is not set +# CONFIG_FS_PROCFS_EXCLUDE_MOUNTS is not set +# CONFIG_FS_PROCFS_EXCLUDE_PROCESS is not set +# CONFIG_FS_PROCFS_EXCLUDE_UPTIME is not set +# CONFIG_FS_PROCFS_EXCLUDE_USAGE is not set +# CONFIG_FS_PROCFS_EXCLUDE_VERSION is not set +# CONFIG_NSH_DISABLEBG is not set +# CONFIG_NSH_DISABLE_EXEC is not set +# CONFIG_NSH_DISABLE_EXIT is not set +# CONFIG_NSH_DISABLE_HEXDUMP is not set +# CONFIG_NSH_DISABLE_XD is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nucleo-f091rc" +CONFIG_ARCH_BOARD_NUCLEO_F091RC=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f0" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F091RC=y +CONFIG_ARCH_CHIP_STM32F0=y +CONFIG_ARCH_IRQBUTTONS=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=2796 +CONFIG_BUILTIN=y +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_DEFAULT_SMALL=y +CONFIG_FS_PROCFS=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=1536 +CONFIG_MM_SMALL=y +CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=64 +CONFIG_NUNGET_CHARS=0 +CONFIG_POSIX_SPAWN_DEFAULT_STACKSIZE=1536 +CONFIG_PTHREAD_STACK_DEFAULT=1536 +CONFIG_RAM_SIZE=32768 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=19 +CONFIG_START_MONTH=5 +CONFIG_START_YEAR=2013 +CONFIG_STM32_PWR=y +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f0/nucleo-f091rc/configs/sx127x/defconfig b/boards/arm/stm32f0/nucleo-f091rc/configs/sx127x/defconfig new file mode 100644 index 0000000000000..0298afca17958 --- /dev/null +++ b/boards/arm/stm32f0/nucleo-f091rc/configs/sx127x/defconfig @@ -0,0 +1,62 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_ARGCAT is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nucleo-f091rc" +CONFIG_ARCH_BOARD_NUCLEO_F091RC=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f0" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F091RC=y +CONFIG_ARCH_CHIP_STM32F0=y +CONFIG_ARCH_IRQBUTTONS=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=2796 +CONFIG_BUILTIN=y +CONFIG_DISABLE_ENVIRON=y +CONFIG_DISABLE_MOUNTPOINT=y +CONFIG_DISABLE_MQUEUE=y +CONFIG_DISABLE_POSIX_TIMERS=y +CONFIG_DISABLE_PSEUDOFS_OPERATIONS=y +CONFIG_DRIVERS_LPWAN=y +CONFIG_DRIVERS_WIRELESS=y +CONFIG_EXAMPLES_HELLO=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=1536 +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_LPWAN_SX127X=y +CONFIG_LPWAN_SX127X_FSKOOK=y +CONFIG_LPWAN_SX127X_MODULATION_DEFAULT=1 +CONFIG_LPWAN_SX127X_RXSUPPORT=y +CONFIG_LPWAN_SX127X_TXSUPPORT=y +CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=64 +CONFIG_NSH_READLINE=y +CONFIG_NUNGET_CHARS=0 +CONFIG_POSIX_SPAWN_DEFAULT_STACKSIZE=1536 +CONFIG_PTHREAD_MUTEX_UNSAFE=y +CONFIG_PTHREAD_STACK_DEFAULT=1536 +CONFIG_RAM_SIZE=20480 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_WAITPID=y +CONFIG_STACK_COLORATION=y +CONFIG_START_DAY=19 +CONFIG_START_MONTH=5 +CONFIG_START_YEAR=2013 +CONFIG_STDIO_DISABLE_BUFFERING=y +CONFIG_STM32_PWR=y +CONFIG_STM32_SPI1=y +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f0/nucleo-f091rc/include/board.h b/boards/arm/stm32f0/nucleo-f091rc/include/board.h new file mode 100644 index 0000000000000..745d8a6644332 --- /dev/null +++ b/boards/arm/stm32f0/nucleo-f091rc/include/board.h @@ -0,0 +1,245 @@ +/**************************************************************************** + * boards/arm/stm32f0/nucleo-f091rc/include/board.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_STM32F0L0G0_NUCLEO_F091RC_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32F0L0G0_NUCLEO_F091RC_INCLUDE_BOARD_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#ifndef __ASSEMBLY__ +# include +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Clocking *****************************************************************/ + +/* Four different clock sources can be used to drive the system clock + * (SYSCLK): + * + * - HSI high-speed internal oscillator clock + * Generated from an internal 8 MHz RC oscillator + * - HSE high-speed external oscillator clock + * Normally driven by an external crystal (X3). However, this crystal is + * not fitted on the Nucleo-F091RC board. + * - PLL clock + * - MSI multispeed internal oscillator clock + * The MSI clock signal is generated from an internal RC oscillator. Seven + * frequency ranges are available: 65.536 kHz, 131.072 kHz, 262.144 kHz, + * 524.288 kHz, 1.048 MHz, 2.097 MHz (default value) and 4.194 MHz. + * + * The devices have the following two secondary clock sources + * - LSI low-speed internal RC clock + * Drives the watchdog and RTC. Approximately 37KHz + * - LSE low-speed external oscillator clock + * Driven by 32.768KHz crystal (X2) on the OSC32_IN and OSC32_OUT pins. + */ + +#define STM32_BOARD_XTAL 8000000ul /* X3 on board (not fitted)*/ + +#define STM32_HSI_FREQUENCY 8000000ul /* Approximately 8MHz */ +#define STM32_HSI14_FREQUENCY 14000000ul /* HSI14 for ADC */ +#define STM32_HSI48_FREQUENCY 48000000ul /* HSI48 for USB, only some STM32F0xx */ +#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL +#define STM32_LSI_FREQUENCY 40000 /* Approximately 40KHz */ +#define STM32_LSE_FREQUENCY 32768 /* X2 on board */ + +/* PLL Configuration + * + * - PLL source is HSI -> 8MHz input (nominal) + * - PLL source predivider 2 -> 4MHz divided down PLL VCO clock output + * - PLL multiplier is 12 -> 48MHz PLL VCO clock output (for USB) + * + * Resulting SYSCLK frequency is 8MHz x 12 / 2 = 48MHz + * + * USB: + * If the USB interface is used in the application, it requires a precise + * 48MHz clock which can be generated from either the (1) the internal + * main PLL with the HSE clock source using an HSE crystal oscillator. In + * this case, the PLL VCO clock (defined by STM32_CFGR_PLLMUL) must be + * programmed to output a 96 MHz frequency. This is required to provide a + * 48MHz clock to the (USBCLK = PLLVCO/2). Or (2) by using the internal + * 48MHz oscillator in automatic trimming mode. The synchronization for + * this oscillator can be taken from the USB data stream itself (SOF + * signalization) which allows crystal-less operation. + * SYSCLK + * The system clock is derived from the PLL VCO divided by the output + * division factor. + * Limitations: + * - 96 MHz as PLLVCO when the product is in range 1 (1.8V), + * - 48 MHz as PLLVCO when the product is in range 2 (1.5V), + * - 24 MHz when the product is in range 3 (1.2V). + * - Output division to avoid exceeding 32 MHz as SYSCLK. + * - The minimum input clock frequency for PLL is 2 MHz (when using HSE as + * PLL source). + */ + +#define STM32_CFGR_PLLSRC RCC_CFGR_PLLSRC_HSId2 /* Source is HSI/2 */ +#define STM32_PLLSRC_FREQUENCY (STM32_HSI_FREQUENCY/2) /* 8MHz / 2 = 4MHz */ +#ifdef CONFIG_STM32_USB +# undef STM32_CFGR2_PREDIV /* Not used with source HSI/2 */ +# define STM32_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx12 /* PLLMUL = 12 */ +# define STM32_PLL_FREQUENCY (12*STM32_PLLSRC_FREQUENCY) /* PLL VCO Frequency is 48MHz */ +#else +# undef STM32_CFGR2_PREDIV /* Not used with source HSI/2 */ +# define STM32_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx12 /* PLLMUL = 12 */ +# define STM32_PLL_FREQUENCY (12*STM32_PLLSRC_FREQUENCY) /* PLL VCO Frequency is 48MHz */ +#endif + +/* Use the PLL and set the SYSCLK source to be the divided down PLL VCO + * output frequency (STM32_PLL_FREQUENCY divided by the PLLDIV value). + */ + +#define STM32_SYSCLK_SW RCC_CFGR_SW_PLL /* Use the PLL as the SYSCLK */ +#define STM32_SYSCLK_SWS RCC_CFGR_SWS_PLL +#ifdef CONFIG_STM32_USB +# define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY /* SYSCLK frequency is PLL VCO = 48MHz */ +#else +# define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY /* SYSCLK frequency is PLL VCO = 48MHz */ +#endif + +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY + +/* APB1 clock (PCLK1) is HCLK (48MHz) */ + +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY) + +/* APB2 clock (PCLK2) is HCLK (48MHz) */ + +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK +#define STM32_PCLK2_FREQUENCY STM32_HCLK_FREQUENCY +#define STM32_APB2_CLKIN (STM32_PCLK2_FREQUENCY) + +/* APB1 timers 1-3, 6-7, and 14-17 will receive PCLK1 */ + +#define STM32_APB1_TIM1_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM2_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (STM32_PCLK1_FREQUENCY) + +#define STM32_APB1_TIM6_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (STM32_PCLK1_FREQUENCY) + +#define STM32_APB1_TIM14_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM15_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM16_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM17_CLKIN (STM32_PCLK1_FREQUENCY) + +/* LED definitions **********************************************************/ + +/* LEDs + * + * The Nucleo-64 board has one user controllable LED, User LD2. This green + * LED is a user LED connected to Arduino signal D13 corresponding to STM32 + * I/O PA5 (PB13 on other some other Nucleo-64 boards). + * + * - When the I/O is HIGH value, the LED is on + * - When the I/O is LOW, the LED is off + */ + +/* LED index values for use with board_userled() */ + +#define BOARD_LD2 0 +#define BOARD_NLEDS 1 + +/* LED bits for use with board_userled_all() */ + +#define BOARD_LD2_BIT (1 << BOARD_LD2) + +/* These LEDs are not used by the board port unless CONFIG_ARCH_LEDS is + * defined. In that case, the usage by the board port is defined in + * include/board.h and src/sam_leds.c. The LEDs are used to encode OS-related + * events as follows when the red LED (PE24) is available: + * + * SYMBOL Meaning LD2 + * ------------------- ----------------------- ----------- + * LED_STARTED NuttX has been started OFF + * LED_HEAPALLOCATE Heap has been allocated OFF + * LED_IRQSENABLED Interrupts enabled OFF + * LED_STACKCREATED Idle stack created ON + * LED_INIRQ In an interrupt No change + * LED_SIGNAL In a signal handler No change + * LED_ASSERTION An assertion failed No change + * LED_PANIC The system has crashed Blinking + * LED_IDLE MCU is in sleep mode Not used + * + * Thus if LD2, NuttX has successfully booted and is, apparently, running + * normally. If LD2 is flashing at approximately 2Hz, then a fatal error + * has been detected and the system has halted. + */ + +#define LED_STARTED 0 +#define LED_HEAPALLOCATE 0 +#define LED_IRQSENABLED 0 +#define LED_STACKCREATED 1 +#define LED_INIRQ 2 +#define LED_SIGNAL 2 +#define LED_ASSERTION 2 +#define LED_PANIC 1 + +/* Button definitions *******************************************************/ + +/* Buttons + * + * B1 USER: the user button is connected to the I/O PC13 (pin 2) of the STM32 + * microcontroller. + */ + +#define BUTTON_USER 0 +#define NUM_BUTTONS 1 + +#define BUTTON_USER_BIT (1 << BUTTON_USER) + +/* Alternate Pin Functions **************************************************/ + +/* I2C + * PB8 - D15 + * PB9 - D14 + */ + +#define GPIO_I2C1_SCL (GPIO_I2C1_SCL_2|GPIO_SPEED_LOW) /* PB8 */ +#define GPIO_I2C1_SDA (GPIO_I2C1_SDA_2|GPIO_SPEED_LOW) /* PB9 */ + +/* SPI */ + +#define GPIO_SPI1_MISO (GPIO_SPI1_MISO_1|GPIO_SPEED_MEDIUM) /* D12 - PA6 */ +#define GPIO_SPI1_MOSI (GPIO_SPI1_MOSI_1|GPIO_SPEED_MEDIUM) /* D11 - PA7 */ +#define GPIO_SPI1_SCK (GPIO_SPI1_SCK_1|GPIO_SPEED_MEDIUM) /* D13 - PA5 */ + +/* USART 1 */ + +#define GPIO_USART1_TX (GPIO_USART1_TX_2|GPIO_SPEED_HIGH) /* PA9 */ +#define GPIO_USART1_RX (GPIO_USART1_RX_2|GPIO_SPEED_HIGH) /* PA10 */ + +/* USART 2 */ + +#define GPIO_USART2_TX (GPIO_USART2_TX_3|GPIO_SPEED_HIGH) /* PA2 */ +#define GPIO_USART2_RX (GPIO_USART2_RX_3|GPIO_SPEED_HIGH) /* PA3 */ + +#endif /* __BOARDS_ARM_STM32F0L0G0_NUCLEO_F091RC_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32f0/nucleo-f091rc/scripts/Make.defs b/boards/arm/stm32f0/nucleo-f091rc/scripts/Make.defs new file mode 100644 index 0000000000000..712d91084b71a --- /dev/null +++ b/boards/arm/stm32f0/nucleo-f091rc/scripts/Make.defs @@ -0,0 +1,41 @@ +############################################################################ +# boards/arm/stm32f0/nucleo-f091rc/scripts/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/.config +include $(TOPDIR)/tools/Config.mk +include $(TOPDIR)/arch/arm/src/armv6-m/Toolchain.defs + +LDSCRIPT = flash.ld +ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) + +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32f0/nucleo-f091rc/scripts/flash.ld b/boards/arm/stm32f0/nucleo-f091rc/scripts/flash.ld new file mode 100644 index 0000000000000..7d017d6432384 --- /dev/null +++ b/boards/arm/stm32f0/nucleo-f091rc/scripts/flash.ld @@ -0,0 +1,111 @@ +/**************************************************************************** + * boards/arm/stm32f0/nucleo-f091rc/scripts/flash.ld + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* The STM32F091RCT6 has 256Kb of FLASH beginning at address 0x0800:0000 and + * 32Kb of SRAM at address 0x20000000. + * + * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 + * where the code expects to begin execution by jumping to the entry point in + * the 0x0800:0000 address range. + */ + +MEMORY +{ + flash (rx) : ORIGIN = 0x08000000, LENGTH = 256K + sram (rwx) : ORIGIN = 0x20000000, LENGTH = 32K +} + +OUTPUT_ARCH(arm) +EXTERN(_vectors) +ENTRY(_stext) + +SECTIONS +{ + .text : + { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > flash + + .init_section : ALIGN(4) { + _sinit = ABSOLUTE(.); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) + _einit = ABSOLUTE(.); + } > flash + + .ARM.extab ALIGN(4): { + *(.ARM.extab*) + } > flash + + .ARM.exidx : ALIGN(4) { + __exidx_start = ABSOLUTE(.); + *(.ARM.exidx*) + __exidx_end = ABSOLUTE(.); + } > flash + + _eronly = ABSOLUTE(.); + + .data : ALIGN(4) { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > sram AT > flash + + .bss : ALIGN(4) { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(8); + _ebss = ABSOLUTE(.); + } > sram + + /* Stabs debugging sections. */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/stm32f0/nucleo-f091rc/src/CMakeLists.txt b/boards/arm/stm32f0/nucleo-f091rc/src/CMakeLists.txt new file mode 100644 index 0000000000000..3ca74165ebc68 --- /dev/null +++ b/boards/arm/stm32f0/nucleo-f091rc/src/CMakeLists.txt @@ -0,0 +1,45 @@ +# ############################################################################## +# boards/arm/stm32f0/nucleo-f091rc/src/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(SRCS stm32_boot.c stm32_bringup.c) + +if(CONFIG_ARCH_LEDS) + list(APPEND SRCS stm32_autoleds.c) +else() + list(APPEND SRCS stm32_userleds.c) +endif() + +if(CONFIG_ARCH_BUTTONS) + list(APPEND SRCS stm32_buttons.c) +endif() + +if(CONFIG_STM32_SPI) + list(APPEND SRCS stm32_spi.c) +endif() + +if(CONFIG_LPWAN_SX127X) + list(APPEND SRCS stm32_sx127x.c) +endif() + +target_sources(board PRIVATE ${SRCS}) + +set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/flash.ld") diff --git a/boards/arm/stm32f0/nucleo-f091rc/src/Make.defs b/boards/arm/stm32f0/nucleo-f091rc/src/Make.defs new file mode 100644 index 0000000000000..a79b2d81893fc --- /dev/null +++ b/boards/arm/stm32f0/nucleo-f091rc/src/Make.defs @@ -0,0 +1,47 @@ +############################################################################ +# boards/arm/stm32f0/nucleo-f091rc/src/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +CSRCS = stm32_boot.c stm32_bringup.c + +ifeq ($(CONFIG_ARCH_LEDS),y) +CSRCS += stm32_autoleds.c +else +CSRCS += stm32_userleds.c +endif + +ifeq ($(CONFIG_ARCH_BUTTONS),y) +CSRCS += stm32_buttons.c +endif + +ifeq ($(CONFIG_STM32_SPI),y) +CSRCS += stm32_spi.c +endif + +ifeq ($(CONFIG_LPWAN_SX127X),y) +CSRCS += stm32_sx127x.c +endif + +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32f0l0g0/nucleo-f091rc/src/nucleo-f091rc.h b/boards/arm/stm32f0/nucleo-f091rc/src/nucleo-f091rc.h similarity index 94% rename from boards/arm/stm32f0l0g0/nucleo-f091rc/src/nucleo-f091rc.h rename to boards/arm/stm32f0/nucleo-f091rc/src/nucleo-f091rc.h index d4798c5bd8799..e1f962c5270b5 100644 --- a/boards/arm/stm32f0l0g0/nucleo-f091rc/src/nucleo-f091rc.h +++ b/boards/arm/stm32f0/nucleo-f091rc/src/nucleo-f091rc.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-f091rc/src/nucleo-f091rc.h + * boards/arm/stm32f0/nucleo-f091rc/src/nucleo-f091rc.h * * SPDX-License-Identifier: Apache-2.0 * @@ -42,14 +42,14 @@ /* How many SPI modules does this chip support? */ #if STM32_NSPI < 1 -# undef CONFIG_STM32F0L0G0_SPI1 -# undef CONFIG_STM32F0L0G0_SPI2 -# undef CONFIG_STM32F0L0G0_SPI3 +# undef CONFIG_STM32_SPI1 +# undef CONFIG_STM32_SPI2 +# undef CONFIG_STM32_SPI3 #elif STM32_NSPI < 2 -# undef CONFIG_STM32F0L0G0_SPI2 -# undef CONFIG_STM32F0L0G0_SPI3 +# undef CONFIG_STM32_SPI2 +# undef CONFIG_STM32_SPI3 #elif STM32_NSPI < 3 -# undef CONFIG_STM32F0L0G0_SPI3 +# undef CONFIG_STM32_SPI3 #endif /* Nucleo-F091RC GPIOs ******************************************************/ @@ -126,7 +126,7 @@ int stm32_bringup(void); * ****************************************************************************/ -#ifdef CONFIG_STM32F0L0G0_SPI +#ifdef CONFIG_STM32_SPI void stm32_spidev_initialize(void); #endif diff --git a/boards/arm/stm32f0/nucleo-f091rc/src/stm32_autoleds.c b/boards/arm/stm32f0/nucleo-f091rc/src/stm32_autoleds.c new file mode 100644 index 0000000000000..c6905fbe01eb5 --- /dev/null +++ b/boards/arm/stm32f0/nucleo-f091rc/src/stm32_autoleds.c @@ -0,0 +1,82 @@ +/**************************************************************************** + * boards/arm/stm32f0/nucleo-f091rc/src/stm32_autoleds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32_gpio.h" +#include "nucleo-f091rc.h" + +#ifdef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_autoled_initialize + ****************************************************************************/ + +void board_autoled_initialize(void) +{ + /* Configure LD2 GPIO for output */ + + stm32_configgpio(GPIO_LD2); +} + +/**************************************************************************** + * Name: board_autoled_on + ****************************************************************************/ + +void board_autoled_on(int led) +{ + if (led == 1) + { + stm32_gpiowrite(GPIO_LD2, true); + } +} + +/**************************************************************************** + * Name: board_autoled_off + ****************************************************************************/ + +void board_autoled_off(int led) +{ + if (led == 1) + { + stm32_gpiowrite(GPIO_LD2, false); + } +} + +#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32f0/nucleo-f091rc/src/stm32_boot.c b/boards/arm/stm32f0/nucleo-f091rc/src/stm32_boot.c new file mode 100644 index 0000000000000..2d58bdb01f245 --- /dev/null +++ b/boards/arm/stm32f0/nucleo-f091rc/src/stm32_boot.c @@ -0,0 +1,87 @@ +/**************************************************************************** + * boards/arm/stm32f0/nucleo-f091rc/src/stm32_boot.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include +#include + +#include "arm_internal.h" +#include "nucleo-f091rc.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_boardinitialize + * + * Description: + * All STM32 architectures must provide the following entry point. + * This entry point is called early in the initialization -- after all + * memory has been configured and mapped but before any devices have been + * initialized. + * + ****************************************************************************/ + +void stm32_boardinitialize(void) +{ +#ifdef CONFIG_ARCH_LEDS + /* Configure on-board LEDs if LED support has been selected. */ + + board_autoled_initialize(); +#endif + +#ifdef CONFIG_STM32_SPI + /* Configure SPI chip selects */ + + stm32_spidev_initialize(); +#endif +} + +/**************************************************************************** + * Name: board_late_initialize + * + * Description: + * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_late_initialize(). board_late_initialize() will be + * called immediately after up_initialize() is called and just before the + * initial application is started. This additional initialization phase + * may be used, for example, to initialize board-specific device drivers. + * + ****************************************************************************/ + +#ifdef CONFIG_BOARD_LATE_INITIALIZE +void board_late_initialize(void) +{ + /* Perform board-specific initialization here if so configured */ + + stm32_bringup(); +} +#endif diff --git a/boards/arm/stm32f0/nucleo-f091rc/src/stm32_bringup.c b/boards/arm/stm32f0/nucleo-f091rc/src/stm32_bringup.c new file mode 100644 index 0000000000000..0a1f1e5eba1d5 --- /dev/null +++ b/boards/arm/stm32f0/nucleo-f091rc/src/stm32_bringup.c @@ -0,0 +1,76 @@ +/**************************************************************************** + * boards/arm/stm32f0/nucleo-f091rc/src/stm32_bringup.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include + +#include "nucleo-f091rc.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_bringup + * + * Description: + * Perform architecture-specific initialization + * + * CONFIG_BOARD_LATE_INITIALIZE=y : + * Called from board_late_initialize(). + * + ****************************************************************************/ + +int stm32_bringup(void) +{ + int ret; + +#ifdef CONFIG_FS_PROCFS + /* Mount the procfs file system */ + + ret = nx_mount(NULL, "/proc", "procfs", 0, NULL); + if (ret < 0) + { + ferr("ERROR: Failed to mount procfs at /proc: %d\n", ret); + } +#endif + +#ifdef CONFIG_LPWAN_SX127X + ret = stm32_lpwaninitialize(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to initialize wireless driver: %d\n", + ret); + } +#endif /* CONFIG_LPWAN_SX127X */ + + UNUSED(ret); + return OK; +} diff --git a/boards/arm/stm32f0/nucleo-f091rc/src/stm32_buttons.c b/boards/arm/stm32f0/nucleo-f091rc/src/stm32_buttons.c new file mode 100644 index 0000000000000..060097e42e6a7 --- /dev/null +++ b/boards/arm/stm32f0/nucleo-f091rc/src/stm32_buttons.c @@ -0,0 +1,117 @@ +/**************************************************************************** + * boards/arm/stm32f0/nucleo-f091rc/src/stm32_buttons.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include +#include + +#include "stm32_gpio.h" +#include "nucleo-f091rc.h" + +#ifdef CONFIG_ARCH_BUTTONS + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_button_initialize + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. + * + ****************************************************************************/ + +uint32_t board_button_initialize(void) +{ + /* Configure the single button as an input. NOTE that EXTI interrupts are + * also configured for the pin. + */ + + stm32_configgpio(GPIO_BTN_USER); + return NUM_BUTTONS; +} + +/**************************************************************************** + * Name: board_buttons + ****************************************************************************/ + +uint32_t board_buttons(void) +{ + /* Check that state of each USER button. A LOW value means that the key is + * pressed. + */ + + bool released = stm32_gpioread(GPIO_BTN_USER); + return !released; +} + +/**************************************************************************** + * Button support. + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. + * + * After board_button_initialize() has been called, board_buttons() may be + * called to collect the state of all buttons. board_buttons() returns an + * 32-bit bit set with each bit associated with a button. See the + * BUTTON_*_BIT definitions in board.h for the meaning of each bit. + * + * board_button_irq() may be called to register an interrupt handler that + * will be called when a button is depressed or released. The ID value is a + * button enumeration value that uniquely identifies a button resource. See + * the BUTTON_* definitions in board.h for the meaning of enumeration + * value. + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_IRQBUTTONS +int board_button_irq(int id, xcpt_t irqhandler, void *arg) +{ + int ret = -EINVAL; + + if (id == BUTTON_USER) + { + ret = stm32_gpiosetevent(GPIO_BTN_USER, true, true, true, + irqhandler, arg); + } + + return ret; +} +#endif +#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/stm32f0/nucleo-f091rc/src/stm32_spi.c b/boards/arm/stm32f0/nucleo-f091rc/src/stm32_spi.c new file mode 100644 index 0000000000000..253eae21e0df0 --- /dev/null +++ b/boards/arm/stm32f0/nucleo-f091rc/src/stm32_spi.c @@ -0,0 +1,189 @@ +/**************************************************************************** + * boards/arm/stm32f0/nucleo-f091rc/src/stm32_spi.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include + +#include "arm_internal.h" +#include "chip.h" +#include "stm32_gpio.h" +#include "stm32_spi.h" + +#include "nucleo-f091rc.h" +#include + +#ifdef CONFIG_STM32_SPI + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_spidev_initialize + * + * Description: + * Called to configure SPI chip select GPIO pins for the Nucleo-144 board. + * + ****************************************************************************/ + +void stm32_spidev_initialize(void) +{ + /* NOTE: Clocking for SPI1 and/or SPI3 was already provided in stm32_rcc.c. + * Configurations of SPI pins is performed in stm32_spi.c. + * Here, we only initialize chip select pins unique to the board + * architecture. + */ + +#ifdef CONFIG_STM32_SPI1 + +# ifdef CONFIG_LPWAN_SX127X + /* Configure the SPI-based SX127X chip select GPIO */ + + spiinfo("Configure GPIO for SX127X SPI1/CS\n"); + + stm32_configgpio(GPIO_SX127X_CS); + stm32_gpiowrite(GPIO_SX127X_CS, true); +# endif + +#endif /* CONFIG_STM32_SPI1 */ +} + +/**************************************************************************** + * Name: stm32_spi1/2/select and stm32_spi1/2/status + * + * Description: + * The external functions, stm32_spi1/2select and stm32_spi1/2status + * must be provided by board-specific logic. They are implementations of + * the select and status methods of the SPI interface defined by struct + * spi_ops_s (see include/nuttx/spi/spi.h). All other methods (including + * stm32_spibus_initialize()) are provided by common STM32 logic. + * To use this common SPI logic on your board: + * + * 1. Provide logic in stm32_boardinitialize() to configure SPI chip + * select pins. + * 2. Provide stm32_spi1/2select() and stm32_spi1/2status() functions + * in your board-specific logic. These functions will perform chip + * selection and status operations using GPIOs in the way your board is + * configured. + * 3. Add a calls to stm32_spibus_initialize() in your low level + * application initialization logic + * 4. The handle returned by stm32_spibus_initialize() may then be used to + * bind the SPI driver to higher level logic (e.g., calling + * mmcsd_spislotinitialize(), for example, will bind the SPI driver to + * the SPI MMC/SD driver). + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_SPI1 +void stm32_spi1select(struct spi_dev_s *dev, + uint32_t devid, bool selected) +{ + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); + + switch (devid) + { +#ifdef CONFIG_LPWAN_SX127X + case SPIDEV_LPWAN(0): + { + spiinfo("SX127X device %s\n", + selected ? "asserted" : "de-asserted"); + + /* Set the GPIO low to select and high to de-select */ + + stm32_gpiowrite(GPIO_SX127X_CS, !selected); + break; + } +#endif + + default: + { + break; + } + } +} + +uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) +{ + uint8_t status = 0; + + switch (devid) + { +#ifdef CONFIG_LPWAN_SX127X + case SPIDEV_LPWAN(0): + { + status |= SPI_STATUS_PRESENT; + break; + } +#endif + + default: + { + break; + } + } + + return status; +} +#endif /* CONFIG_STM32_SPI1 */ + +#ifdef CONFIG_STM32_SPI2 +void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid, + bool selected) +{ + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); +} + +uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} +#endif /* CONFIG_STM32_SPI2 */ + +#endif diff --git a/boards/arm/stm32f0/nucleo-f091rc/src/stm32_sx127x.c b/boards/arm/stm32f0/nucleo-f091rc/src/stm32_sx127x.c new file mode 100644 index 0000000000000..2f96bee994809 --- /dev/null +++ b/boards/arm/stm32f0/nucleo-f091rc/src/stm32_sx127x.c @@ -0,0 +1,212 @@ +/**************************************************************************** + * boards/arm/stm32f0/nucleo-f091rc/src/stm32_sx127x.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include "stm32_gpio.h" +#include "stm32_exti.h" +#include "stm32_spi.h" + +#include "nucleo-f091rc.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* SX127X on SPI1 bus */ + +#define SX127X_SPI 1 + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +static void sx127x_chip_reset(void); +static int sx127x_opmode_change(int opmode); +static int sx127x_freq_select(uint32_t freq); +static int sx127x_pa_select(bool enable); +static int sx127x_irq0_attach(xcpt_t isr, void *arg); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +struct sx127x_lower_s lower = +{ + .irq0attach = sx127x_irq0_attach, + .reset = sx127x_chip_reset, + .opmode_change = sx127x_opmode_change, + .freq_select = sx127x_freq_select, + .pa_select = sx127x_pa_select, + .pa_force = true +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: sx127x_irq0_attach + ****************************************************************************/ + +static int sx127x_irq0_attach(xcpt_t isr, void *arg) +{ + wlinfo("Attach DIO0 IRQ\n"); + + /* IRQ on rising edge */ + + stm32_gpiosetevent(GPIO_SX127X_DIO0, true, false, false, isr, arg); + return OK; +} + +/**************************************************************************** + * Name: sx127x_chip_reset + ****************************************************************************/ + +static void sx127x_chip_reset(void) +{ + wlinfo("SX127X RESET\n"); + + /* Configure reset as output */ + + stm32_configgpio(GPIO_SX127X_RESET | GPIO_OUTPUT | GPIO_SPEED_HIGH | + GPIO_OUTPUT_CLEAR); + + /* Set pin to zero */ + + stm32_gpiowrite(GPIO_SX127X_RESET, false); + + /* Wait 1 ms */ + + nxsched_usleep(1000); + + /* Configure reset as input */ + + stm32_configgpio(GPIO_SX127X_RESET | GPIO_INPUT | GPIO_FLOAT); + + /* Wait 10 ms */ + + nxsched_usleep(10000); +} + +/**************************************************************************** + * Name: sx127x_opmode_change + ****************************************************************************/ + +static int sx127x_opmode_change(int opmode) +{ + /* Do nothing */ + + return OK; +} + +/**************************************************************************** + * Name: sx127x_freq_select + ****************************************************************************/ + +static int sx127x_freq_select(uint32_t freq) +{ + int ret = OK; + + /* NOTE: this depends on your module version */ + + if (freq > SX127X_HFBAND_THR) + { + ret = -EINVAL; + wlerr("HF output not supported\n"); + } + + return ret; +} + +/**************************************************************************** + * Name: sx127x_pa_select + ****************************************************************************/ + +static int sx127x_pa_select(bool enable) +{ + int ret = OK; + + /* Only PA_BOOST output connected to antenna */ + + if (enable == false) + { + ret = -EINVAL; + wlerr("Module supports only PA_BOOST pin, " + "so PA_SELECT must be enabled!\n"); + } + + return ret; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +int stm32_lpwaninitialize(void) +{ + struct spi_dev_s *spidev; + int ret = OK; + + wlinfo("Register the sx127x module\n"); + + /* Setup DIO0 */ + + stm32_configgpio(GPIO_SX127X_DIO0); + + /* Init SPI bus */ + + spidev = stm32_spibus_initialize(SX127X_SPI); + if (!spidev) + { + wlerr("ERROR: Failed to initialize SPI %d bus\n", SX127X_SPI); + ret = -ENODEV; + goto errout; + } + + /* Initialize SX127X */ + + ret = sx127x_register(spidev, &lower); + if (ret < 0) + { + wlerr("ERROR: Failed to register sx127x\n"); + goto errout; + } + +errout: + return ret; +} diff --git a/boards/arm/stm32f0/nucleo-f091rc/src/stm32_userleds.c b/boards/arm/stm32f0/nucleo-f091rc/src/stm32_userleds.c new file mode 100644 index 0000000000000..92b0a4bcdd385 --- /dev/null +++ b/boards/arm/stm32f0/nucleo-f091rc/src/stm32_userleds.c @@ -0,0 +1,197 @@ +/**************************************************************************** + * boards/arm/stm32f0/nucleo-f091rc/src/stm32_userleds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32_gpio.h" +#include "nucleo-f091rc.h" + +#ifndef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/* LED Power Management */ + +#ifdef CONFIG_PM +static void led_pm_notify(struct pm_callback_s *cb, int domain, + enum pm_state_e pmstate); +static int led_pm_prepare(struct pm_callback_s *cb, int domain, + enum pm_state_e pmstate); +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#ifdef CONFIG_PM +static struct pm_callback_s g_ledscb = +{ + .notify = led_pm_notify, + .prepare = led_pm_prepare, +}; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: led_pm_notify + * + * Description: + * Notify the driver of new power state. This callback is called after + * all drivers have had the opportunity to prepare for the new power state. + * + ****************************************************************************/ + +#ifdef CONFIG_PM +static void led_pm_notify(struct pm_callback_s *cb, int domain, + enum pm_state_e pmstate) +{ + switch (pmstate) + { + case PM_NORMAL: + { + /* Restore normal LEDs operation */ + } + break; + + case PM_IDLE: + { + /* Entering IDLE mode - Turn leds off */ + } + break; + + case PM_STANDBY: + { + /* Entering STANDBY mode - Logic for PM_STANDBY goes here */ + } + break; + + case PM_SLEEP: + { + /* Entering SLEEP mode - Logic for PM_SLEEP goes here */ + } + break; + + default: + { + /* Should not get here */ + } + break; + } +} +#endif + +/**************************************************************************** + * Name: led_pm_prepare + * + * Description: + * Request the driver to prepare for a new power state. This is a warning + * that the system is about to enter into a new power state. The driver + * should begin whatever operations that may be required to enter power + * state. The driver may abort the state change mode by returning a + * non-zero value from the callback function. + * + ****************************************************************************/ + +#ifdef CONFIG_PM +static int led_pm_prepare(struct pm_callback_s *cb, int domain, + enum pm_state_e pmstate) +{ + /* No preparation to change power modes is required by the LEDs driver. + * We always accept the state change by returning OK. + */ + + return OK; +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_userled_initialize + ****************************************************************************/ + +uint32_t board_userled_initialize(void) +{ + /* Configure LD2 GPIO for output */ + + stm32_configgpio(GPIO_LD2); + return BOARD_NLEDS; +} + +/**************************************************************************** + * Name: board_userled + ****************************************************************************/ + +void board_userled(int led, bool ledon) +{ + if (led == BOARD_LD2) + { + stm32_gpiowrite(GPIO_LD2, ledon); + } +} + +/**************************************************************************** + * Name: board_userled_all + ****************************************************************************/ + +void board_userled_all(uint32_t ledset) +{ + stm32_gpiowrite(GPIO_LD2, (ledset & BOARD_LD2_BIT) != 0); +} + +/**************************************************************************** + * Name: stm32_led_pminitialize + ****************************************************************************/ + +#ifdef CONFIG_PM +void stm32_led_pminitialize(void) +{ + /* Register to receive power management callbacks */ + + int ret = pm_register(&g_ledscb); + DEBUGASSERT(ret == OK); + UNUSED(ret); +} +#endif /* CONFIG_PM */ + +#endif /* !CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32f0/stm32f051-discovery/CMakeLists.txt b/boards/arm/stm32f0/stm32f051-discovery/CMakeLists.txt new file mode 100644 index 0000000000000..82f56ec121ee1 --- /dev/null +++ b/boards/arm/stm32f0/stm32f051-discovery/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32f0/stm32f051-discovery/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/arm/stm32f0l0g0/stm32f051-discovery/Kconfig b/boards/arm/stm32f0/stm32f051-discovery/Kconfig similarity index 100% rename from boards/arm/stm32f0l0g0/stm32f051-discovery/Kconfig rename to boards/arm/stm32f0/stm32f051-discovery/Kconfig diff --git a/boards/arm/stm32f0/stm32f051-discovery/configs/nsh/defconfig b/boards/arm/stm32f0/stm32f051-discovery/configs/nsh/defconfig new file mode 100644 index 0000000000000..2e21e6e8d07ac --- /dev/null +++ b/boards/arm/stm32f0/stm32f051-discovery/configs/nsh/defconfig @@ -0,0 +1,47 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_DISABLEBG is not set +# CONFIG_NSH_DISABLE_EXEC is not set +# CONFIG_NSH_DISABLE_EXIT is not set +# CONFIG_NSH_DISABLE_HEXDUMP is not set +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_NSH_DISABLE_XD is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f051-discovery" +CONFIG_ARCH_BOARD_STM32F051_DISCOVERY=y +CONFIG_ARCH_CHIP="stm32f0" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F051R8=y +CONFIG_ARCH_CHIP_STM32F0=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=2796 +CONFIG_DEFAULT_SMALL=y +CONFIG_DISABLE_MOUNTPOINT=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=1536 +CONFIG_MM_SMALL=y +CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 +CONFIG_NSH_FILEIOSIZE=64 +CONFIG_NUNGET_CHARS=0 +CONFIG_POSIX_SPAWN_DEFAULT_STACKSIZE=1536 +CONFIG_PTHREAD_STACK_DEFAULT=1536 +CONFIG_RAM_SIZE=8192 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=19 +CONFIG_START_MONTH=5 +CONFIG_START_YEAR=2013 +CONFIG_STM32_PWR=y +CONFIG_STM32_USART1=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART1_RXBUFSIZE=32 +CONFIG_USART1_SERIAL_CONSOLE=y +CONFIG_USART1_TXBUFSIZE=32 diff --git a/boards/arm/stm32f0/stm32f051-discovery/include/board.h b/boards/arm/stm32f0/stm32f051-discovery/include/board.h new file mode 100644 index 0000000000000..64aa156add7cd --- /dev/null +++ b/boards/arm/stm32f0/stm32f051-discovery/include/board.h @@ -0,0 +1,241 @@ +/**************************************************************************** + * boards/arm/stm32f0/stm32f051-discovery/include/board.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_STM32F0L0G0_STM32F051_DISCOVERY_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32F0L0G0_STM32F051_DISCOVERY_INCLUDE_BOARD_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#ifndef __ASSEMBLY__ +# include +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Clocking *****************************************************************/ + +/* Four different clock sources can be used to drive the system clock + * (SYSCLK): + * + * - HSI high-speed internal oscillator clock + * Generated from an internal 8 MHz RC oscillator + * - HSE high-speed external oscillator clock + * Normally driven by an external crystal (X3). However, this crystal is + * not fitted on the STM32F0-Discovery board. + * - PLL clock + * - MSI multispeed internal oscillator clock + * The MSI clock signal is generated from an internal RC oscillator. Seven + * frequency ranges are available: 65.536 kHz, 131.072 kHz, 262.144 kHz, + * 524.288 kHz, 1.048 MHz, 2.097 MHz (default value) and 4.194 MHz. + * + * The devices have the following two secondary clock sources + * - LSI low-speed internal RC clock + * Drives the watchdog and RTC. Approximately 37KHz + * - LSE low-speed external oscillator clock + * Driven by 32.768KHz crystal (X2) on the OSC32_IN and OSC32_OUT pins. + */ + +#define STM32_BOARD_XTAL 8000000ul /* X3 on board (not fitted)*/ + +#define STM32_HSI_FREQUENCY 8000000ul /* Approximately 8MHz */ +#define STM32_HSI14_FREQUENCY 14000000ul /* HSI14 for ADC */ +#define STM32_HSI48_FREQUENCY 48000000ul /* HSI48 for USB, only some STM32F0xx */ +#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL +#define STM32_LSI_FREQUENCY 40000 /* Approximately 40KHz */ +#define STM32_LSE_FREQUENCY 32768 /* X2 on board */ + +/* PLL Configuration + * + * - PLL source is HSI -> 8MHz input (nominal) + * - PLL source predivider 2 -> 4MHz divided down PLL VCO clock output + * - PLL multiplier is 12 -> 48MHz PLL VCO clock output (for USB) + * + * Resulting SYSCLK frequency is 8MHz x 12 / 2 = 48MHz + * + * USB: + * If the USB interface is used in the application, it requires a precise + * 48MHz clock which can be generated from either the (1) the internal + * main PLL with the HSE clock source using an HSE crystal oscillator. In + * this case, the PLL VCO clock (defined by STM32_CFGR_PLLMUL) must be + * programmed to output a 96 MHz frequency. This is required to provide a + * 48MHz clock to the (USBCLK = PLLVCO/2). Or (2) by using the internal + * 48MHz oscillator in automatic trimming mode. The synchronization for + * this oscillator can be taken from the USB data stream itself (SOF + * signalization) which allows crystal-less operation. + * SYSCLK + * The system clock is derived from the PLL VCO divided by the output + * division factor. + * Limitations: + * - 96 MHz as PLLVCO when the product is in range 1 (1.8V), + * - 48 MHz as PLLVCO when the product is in range 2 (1.5V), + * - 24 MHz when the product is in range 3 (1.2V). + * - Output division to avoid exceeding 32 MHz as SYSCLK. + * - The minimum input clock frequency for PLL is 2 MHz (when using HSE as + * PLL source). + */ + +#define STM32_CFGR_PLLSRC RCC_CFGR_PLLSRC_HSId2 /* Source is HSI/2 */ +#define STM32_PLLSRC_FREQUENCY (STM32_HSI_FREQUENCY/2) /* 8MHz / 2 = 4MHz */ +#ifdef CONFIG_STM32_USB +# undef STM32_CFGR2_PREDIV /* Not used with source HSI/2 */ +# define STM32_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx12 /* PLLMUL = 12 */ +# define STM32_PLL_FREQUENCY (12*STM32_PLLSRC_FREQUENCY) /* PLL VCO Frequency is 48MHz */ +#else +# undef STM32_CFGR2_PREDIV /* Not used with source HSI/2 */ +# define STM32_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx12 /* PLLMUL = 12 */ +# define STM32_PLL_FREQUENCY (12*STM32_PLLSRC_FREQUENCY) /* PLL VCO Frequency is 48MHz */ +#endif + +/* Use the PLL and set the SYSCLK source to be the divided down PLL VCO + * output frequency (STM32_PLL_FREQUENCY divided by the PLLDIV value). + */ + +#define STM32_SYSCLK_SW RCC_CFGR_SW_PLL /* Use the PLL as the SYSCLK */ +#define STM32_SYSCLK_SWS RCC_CFGR_SWS_PLL +#ifdef CONFIG_STM32_USB +# define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY /* SYSCLK frequency is PLL VCO = 48MHz */ +#else +# define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY /* SYSCLK frequency is PLL VCO = 48MHz */ +#endif + +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY + +/* APB1 clock (PCLK1) is HCLK (48MHz) */ + +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY) + +/* APB2 clock (PCLK2) is HCLK (48MHz) */ + +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK +#define STM32_PCLK2_FREQUENCY STM32_HCLK_FREQUENCY +#define STM32_APB2_CLKIN (STM32_PCLK2_FREQUENCY) + +/* APB1 timers 1-3, 6-7, and 14-17 will receive PCLK1 */ + +#define STM32_APB1_TIM1_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM2_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (STM32_PCLK1_FREQUENCY) + +#define STM32_APB1_TIM6_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (STM32_PCLK1_FREQUENCY) + +#define STM32_APB1_TIM14_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM15_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM16_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM17_CLKIN (STM32_PCLK1_FREQUENCY) + +/* LED definitions **********************************************************/ + +/* The STM32F0-Discovery board has four LEDs. Two of these are controlled by + * logic on the board and are not available for software control: + * + * LD1 COM: LD2 default status is red. LD2 turns to green to indicate that + * communications are in progress between the PC and the + * ST-LINK/V2. + * LD2 PWR: Red LED indicates that the board is powered. + * + * And two LEDs can be controlled by software: + * + * User LD3: Green LED is a user LED connected to the I/O PB7 of the + * STM32F051R8 MCU. + * User LD4: Blue LED is a user LED connected to the I/O PB6 of the + * STM32F051R8 MCU. + * + * If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs in + * any way. The following definitions are used to access individual LEDs. + */ + +/* LED index values for use with board_userled() */ + +#define BOARD_LED1 0 /* User LD3 */ +#define BOARD_LED2 1 /* User LD4 */ +#define BOARD_NLEDS 2 + +/* LED bits for use with board_userled_all() */ + +#define BOARD_LED1_BIT (1 << BOARD_LED1) +#define BOARD_LED2_BIT (1 << BOARD_LED2) + +/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the 8 LEDs on + * board the STM32F0-Discovery. + * The following definitions describe how NuttX controls the LEDs: + * + * SYMBOL Meaning LED state + * LED1 LED2 + * ------------------- ----------------------- -------- -------- + * LED_STARTED NuttX has been started OFF OFF + * LED_HEAPALLOCATE Heap has been allocated OFF OFF + * LED_IRQSENABLED Interrupts enabled OFF OFF + * LED_STACKCREATED Idle stack created ON OFF + * LED_INIRQ In an interrupt No change + * LED_SIGNAL In a signal handler No change + * LED_ASSERTION An assertion failed No change + * LED_PANIC The system has crashed OFF Blinking + * LED_IDLE STM32 is in sleep mode Not used + */ + +#define LED_STARTED 0 +#define LED_HEAPALLOCATE 0 +#define LED_IRQSENABLED 0 +#define LED_STACKCREATED 1 +#define LED_INIRQ 2 +#define LED_SIGNAL 2 +#define LED_ASSERTION 2 +#define LED_PANIC 3 + +/* Button definitions *******************************************************/ + +/* The STM32F0-Discovery supports two buttons; only one button is + * controllable by software: + * + * B1 USER: + * user and wake-up button connected to the I/O PA0 of the STM32F051R8. + * B2 RESET: + * pushbutton connected to NRST is used to RESET the STM32F051R8. + */ + +#define BUTTON_USER 0 +#define NUM_BUTTONS 1 + +#define BUTTON_USER_BIT (1 << BUTTON_USER) + +/* Alternate Pin Functions **************************************************/ + +/* USART 1 */ + +#define GPIO_USART1_TX (GPIO_USART1_TX_1|GPIO_SPEED_HIGH) +#define GPIO_USART1_RX (GPIO_USART1_RX_1|GPIO_SPEED_HIGH) + +/* I2C pins definition */ + +#define GPIO_I2C1_SCL (GPIO_I2C1_SCL_1|GPIO_SPEED_LOW) +#define GPIO_I2C1_SDA (GPIO_I2C1_SDA_1|GPIO_SPEED_LOW) + +#endif /* __BOARDS_ARM_STM32F0L0G0_STM32F051_DISCOVERY_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32f0/stm32f051-discovery/scripts/Make.defs b/boards/arm/stm32f0/stm32f051-discovery/scripts/Make.defs new file mode 100644 index 0000000000000..101580bd303eb --- /dev/null +++ b/boards/arm/stm32f0/stm32f051-discovery/scripts/Make.defs @@ -0,0 +1,41 @@ +############################################################################ +# boards/arm/stm32f0/stm32f051-discovery/scripts/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/.config +include $(TOPDIR)/tools/Config.mk +include $(TOPDIR)/arch/arm/src/armv6-m/Toolchain.defs + +LDSCRIPT = flash.ld +ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) + +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32f0/stm32f051-discovery/scripts/flash.ld b/boards/arm/stm32f0/stm32f051-discovery/scripts/flash.ld new file mode 100644 index 0000000000000..7be00e78d9818 --- /dev/null +++ b/boards/arm/stm32f0/stm32f051-discovery/scripts/flash.ld @@ -0,0 +1,109 @@ +/**************************************************************************** + * boards/arm/stm32f0/stm32f051-discovery/scripts/flash.ld + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* The STM32F051R8T6 has 64KB of FLASH beginning at address 0x0800:0000 and + * 8Kb of SRAM at address 0x20000000. + * + * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 + * where the code expects to begin execution by jumping to the entry point in + * the 0x0800:0000 address range. + */ + +MEMORY +{ + flash (rx) : ORIGIN = 0x08000000, LENGTH = 64K + sram (rwx) : ORIGIN = 0x20000000, LENGTH = 8K +} + +OUTPUT_ARCH(arm) +EXTERN(_vectors) +ENTRY(_stext) + +SECTIONS +{ + .text : { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > flash + + .init_section : { + _sinit = ABSOLUTE(.); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) + _einit = ABSOLUTE(.); + } > flash + + .ARM.extab ALIGN(4): { + *(.ARM.extab*) + } > flash + + .ARM.exidx : { + __exidx_start = ABSOLUTE(.); + *(.ARM.exidx*) + __exidx_end = ABSOLUTE(.); + } > flash + + _eronly = ABSOLUTE(.); + + .data : ALIGN(4) { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > sram AT > flash + + .bss : ALIGN(4) { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(8); + _ebss = ABSOLUTE(.); + } > sram + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/stm32f0/stm32f051-discovery/src/CMakeLists.txt b/boards/arm/stm32f0/stm32f051-discovery/src/CMakeLists.txt new file mode 100644 index 0000000000000..ea0e96675cc3a --- /dev/null +++ b/boards/arm/stm32f0/stm32f051-discovery/src/CMakeLists.txt @@ -0,0 +1,49 @@ +# ############################################################################## +# boards/arm/stm32f0/stm32f051-discovery/src/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(SRCS stm32_boot.c stm32_bringup.c) + +if(CONFIG_ARCH_LEDS) + list(APPEND SRCS stm32_autoleds.c) +else() + list(APPEND SRCS stm32_userleds.c) +endif() + +if(CONFIG_ARCH_BUTTONS) + list(APPEND SRCS stm32_buttons.c) +endif() + +if(CONFIG_STM32_SPI) + list(APPEND SRCS stm32_spi.c) +endif() + +if(CONFIG_PWM) + list(APPEND SRCS stm32_pwm.c) +endif() + +if(CONFIG_SENSORS_QENCODER) + list(APPEND SRCS stm32_qencoder.c) +endif() + +target_sources(board PRIVATE ${SRCS}) + +set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/flash.ld") diff --git a/boards/arm/stm32f0/stm32f051-discovery/src/Make.defs b/boards/arm/stm32f0/stm32f051-discovery/src/Make.defs new file mode 100644 index 0000000000000..df3653b25acbc --- /dev/null +++ b/boards/arm/stm32f0/stm32f051-discovery/src/Make.defs @@ -0,0 +1,51 @@ +############################################################################ +# boards/arm/stm32f0/stm32f051-discovery/src/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +CSRCS = stm32_boot.c stm32_bringup.c + +ifeq ($(CONFIG_ARCH_LEDS),y) +CSRCS += stm32_autoleds.c +else +CSRCS += stm32_userleds.c +endif + +ifeq ($(CONFIG_ARCH_BUTTONS),y) +CSRCS += stm32_buttons.c +endif + +ifeq ($(CONFIG_STM32_SPI),y) +CSRCS += stm32_spi.c +endif + +ifeq ($(CONFIG_PWM),y) +CSRCS += stm32_pwm.c +endif + +ifeq ($(CONFIG_SENSORS_QENCODER),y) +CSRCS += stm32_qencoder.c +endif + +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32f0/stm32f051-discovery/src/stm32_autoleds.c b/boards/arm/stm32f0/stm32f051-discovery/src/stm32_autoleds.c new file mode 100644 index 0000000000000..db37ca075aa6e --- /dev/null +++ b/boards/arm/stm32f0/stm32f051-discovery/src/stm32_autoleds.c @@ -0,0 +1,123 @@ +/**************************************************************************** + * boards/arm/stm32f0/stm32f051-discovery/src/stm32_autoleds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "chip.h" +#include "stm32f051-discovery.h" + +#ifdef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the 2 LEDs on + * board the STM32L-Discovery. The following definitions describe how NuttX + * controls the LEDs: + * + * SYMBOL Meaning LED state + * LED1 LED2 + * ------------------- ----------------------- -------- -------- + * LED_STARTED NuttX has been started OFF OFF + * LED_HEAPALLOCATE Heap has been allocated OFF OFF + * LED_IRQSENABLED Interrupts enabled OFF OFF + * LED_STACKCREATED Idle stack created ON OFF + * LED_INIRQ In an interrupt No change + * LED_SIGNAL In a signal handler No change + * LED_ASSERTION An assertion failed No change + * LED_PANIC The system has crashed OFF Blinking + * LED_IDLE STM32 is in sleep mode Not used + */ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_autoled_initialize + ****************************************************************************/ + +void board_autoled_initialize(void) +{ + /* Configure LED1-2 GPIOs for output */ + + stm32_configgpio(GPIO_LED1); + stm32_configgpio(GPIO_LED2); +} + +/**************************************************************************** + * Name: board_autoled_on + ****************************************************************************/ + +void board_autoled_on(int led) +{ + bool led1on = false; + bool led2on = false; + + switch (led) + { + case 0: /* LED_STARTED, LED_HEAPALLOCATE, LED_IRQSENABLED */ + break; + + case 1: /* LED_STACKCREATED */ + led1on = true; + break; + + default: + case 2: /* LED_INIRQ, LED_SIGNAL, LED_ASSERTION */ + return; + + case 3: /* LED_PANIC */ + led2on = true; + break; + } + + stm32_gpiowrite(GPIO_LED1, led1on); + stm32_gpiowrite(GPIO_LED2, led2on); +} + +/**************************************************************************** + * Name: board_autoled_off + ****************************************************************************/ + +void board_autoled_off(int led) +{ + if (led != 2) + { + stm32_gpiowrite(GPIO_LED1, false); + stm32_gpiowrite(GPIO_LED2, false); + } +} + +#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32f0/stm32f051-discovery/src/stm32_boot.c b/boards/arm/stm32f0/stm32f051-discovery/src/stm32_boot.c new file mode 100644 index 0000000000000..94dafa4afee4f --- /dev/null +++ b/boards/arm/stm32f0/stm32f051-discovery/src/stm32_boot.c @@ -0,0 +1,81 @@ +/**************************************************************************** + * boards/arm/stm32f0/stm32f051-discovery/src/stm32_boot.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include +#include + +#include "arm_internal.h" +#include "stm32f051-discovery.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_boardinitialize + * + * Description: + * All STM32 architectures must provide the following entry point. + * This entry point is called early in the initialization -- after all + * memory has been configured and mapped but before any devices have been + * initialized. + * + ****************************************************************************/ + +void stm32_boardinitialize(void) +{ +#ifdef CONFIG_ARCH_LEDS + /* Configure on-board LEDs if LED support has been selected. */ + + board_autoled_initialize(); +#endif +} + +/**************************************************************************** + * Name: board_late_initialize + * + * Description: + * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_late_initialize(). board_late_initialize() will be + * called immediately after up_initialize() is called and just before the + * initial application is started. This additional initialization phase + * may be used, for example, to initialize board-specific device drivers. + * + ****************************************************************************/ + +#ifdef CONFIG_BOARD_LATE_INITIALIZE +void board_late_initialize(void) +{ + /* Perform board-specific initialization here if so configured */ + + stm32_bringup(); +} +#endif diff --git a/boards/arm/stm32f0/stm32f051-discovery/src/stm32_bringup.c b/boards/arm/stm32f0/stm32f051-discovery/src/stm32_bringup.c new file mode 100644 index 0000000000000..c3adb7ee280bf --- /dev/null +++ b/boards/arm/stm32f0/stm32f051-discovery/src/stm32_bringup.c @@ -0,0 +1,66 @@ +/**************************************************************************** + * boards/arm/stm32f0/stm32f051-discovery/src/stm32_bringup.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include + +#include "stm32f051-discovery.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_bringup + * + * Description: + * Perform architecture-specific initialization + * + * CONFIG_BOARD_LATE_INITIALIZE=y : + * Called from board_late_initialize(). + * + ****************************************************************************/ + +int stm32_bringup(void) +{ + int ret; + +#ifdef CONFIG_FS_PROCFS + /* Mount the procfs file system */ + + ret = nx_mount(NULL, "/proc", "procfs", 0, NULL); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to mount procfs at /proc: %d\n", ret); + } +#endif + + UNUSED(ret); + return OK; +} diff --git a/boards/arm/stm32f0/stm32f051-discovery/src/stm32_buttons.c b/boards/arm/stm32f0/stm32f051-discovery/src/stm32_buttons.c new file mode 100644 index 0000000000000..fefd449f40a1c --- /dev/null +++ b/boards/arm/stm32f0/stm32f051-discovery/src/stm32_buttons.c @@ -0,0 +1,150 @@ +/**************************************************************************** + * boards/arm/stm32f0/stm32f051-discovery/src/stm32_buttons.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include +#include + +#include "stm32f051-discovery.h" + +#ifdef CONFIG_ARCH_BUTTONS + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* Pin configuration for each STM32F3Discovery button. This array is indexed + * by the BUTTON_* definitions in board.h + */ + +static const uint32_t g_buttons[NUM_BUTTONS] = +{ + GPIO_BTN_USER +}; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_button_initialize + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. + * + ****************************************************************************/ + +uint32_t board_button_initialize(void) +{ + int i; + + /* Configure the GPIO pins as inputs. NOTE that EXTI interrupts are + * configured for all pins. + */ + + for (i = 0; i < NUM_BUTTONS; i++) + { + stm32_configgpio(g_buttons[i]); + } + + return NUM_BUTTONS; +} + +/**************************************************************************** + * Name: board_buttons + ****************************************************************************/ + +uint8_t board_buttons(void) +{ + uint8_t ret = 0; + int i; + + /* Check that state of each key */ + + for (i = 0; i < NUM_BUTTONS; i++) + { + /* A LOW value means that the key is pressed. */ + + bool released = stm32_gpioread(g_buttons[i]); + + /* Accumulate the set of depressed (not released) keys */ + + if (!released) + { + ret |= (1 << i); + } + } + + return ret; +} + +/**************************************************************************** + * Button support. + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. + * + * After board_button_initialize() has been called, board_buttons() may be + * called to collect the state of all buttons. board_buttons() returns an + * 8-bit bit set with each bit associated with a button. See the + * BUTTON_*_BIT definitions in board.h for the meaning of each bit. + * + * board_button_irq() may be called to register an interrupt handler that + * will be called when a button is depressed or released. The ID value is a + * button enumeration value that uniquely identifies a button resource. See + * the BUTTON_* definitions in board.h for the meaning of enumeration + * value. + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_IRQBUTTONS +int board_button_irq(int id, xcpt_t irqhandler, void *arg) +{ + int ret = -EINVAL; + + /* The following should be atomic */ + + if (id >= MIN_IRQBUTTON && id <= MAX_IRQBUTTON) + { + ret = stm32_gpiosetevent(g_buttons[id], true, true, true, + irqhandler, arg); + } + + return ret; +} +#endif +#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/stm32f0/stm32f051-discovery/src/stm32_userleds.c b/boards/arm/stm32f0/stm32f051-discovery/src/stm32_userleds.c new file mode 100644 index 0000000000000..973ab746680aa --- /dev/null +++ b/boards/arm/stm32f0/stm32f051-discovery/src/stm32_userleds.c @@ -0,0 +1,97 @@ +/**************************************************************************** + * boards/arm/stm32f0/stm32f051-discovery/src/stm32_userleds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include + +#include "chip.h" +#include "stm32.h" +#include "stm32f051-discovery.h" + +#ifndef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_userled_initialize + ****************************************************************************/ + +uint32_t board_userled_initialize(void) +{ + /* Configure LED1-2 GPIOs for output */ + + stm32_configgpio(GPIO_LED1); + stm32_configgpio(GPIO_LED2); + return BOARD_NLEDS; +} + +/**************************************************************************** + * Name: board_userled + ****************************************************************************/ + +void board_userled(int led, bool ledon) +{ + uint32_t ledcfg; + + if (led == BOARD_LED1) + { + ledcfg = GPIO_LED1; + } + else if (led == BOARD_LED2) + { + ledcfg = GPIO_LED2; + } + else + { + return; + } + + stm32_gpiowrite(ledcfg, ledon); +} + +/**************************************************************************** + * Name: board_userled_all + ****************************************************************************/ + +void board_userled_all(uint32_t ledset) +{ + bool ledon; + + ledon = ((ledset & BOARD_LED1_BIT) != 0); + stm32_gpiowrite(GPIO_LED1, ledon); + + ledon = ((ledset & BOARD_LED2_BIT) != 0); + stm32_gpiowrite(GPIO_LED2, ledon); +} + +#endif /* !CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32f0l0g0/stm32f051-discovery/src/stm32f051-discovery.h b/boards/arm/stm32f0/stm32f051-discovery/src/stm32f051-discovery.h similarity index 94% rename from boards/arm/stm32f0l0g0/stm32f051-discovery/src/stm32f051-discovery.h rename to boards/arm/stm32f0/stm32f051-discovery/src/stm32f051-discovery.h index 42d17d21bc050..46edd74b73963 100644 --- a/boards/arm/stm32f0l0g0/stm32f051-discovery/src/stm32f051-discovery.h +++ b/boards/arm/stm32f0/stm32f051-discovery/src/stm32f051-discovery.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/stm32f051-discovery/src/stm32f051-discovery.h + * boards/arm/stm32f0/stm32f051-discovery/src/stm32f051-discovery.h * * SPDX-License-Identifier: Apache-2.0 * @@ -42,14 +42,14 @@ /* How many SPI modules does this chip support? */ #if STM32_NSPI < 1 -# undef CONFIG_STM32F0L0G0_SPI1 -# undef CONFIG_STM32F0L0G0_SPI2 -# undef CONFIG_STM32F0L0G0_SPI3 +# undef CONFIG_STM32_SPI1 +# undef CONFIG_STM32_SPI2 +# undef CONFIG_STM32_SPI3 #elif STM32_NSPI < 2 -# undef CONFIG_STM32F0L0G0_SPI2 -# undef CONFIG_STM32F0L0G0_SPI3 +# undef CONFIG_STM32_SPI2 +# undef CONFIG_STM32_SPI3 #elif STM32_NSPI < 3 -# undef CONFIG_STM32F0L0G0_SPI3 +# undef CONFIG_STM32_SPI3 #endif /* STM32F0Discovery GPIOs ***************************************************/ diff --git a/boards/arm/stm32f0/stm32f072-discovery/CMakeLists.txt b/boards/arm/stm32f0/stm32f072-discovery/CMakeLists.txt new file mode 100644 index 0000000000000..2e72ceab91ad9 --- /dev/null +++ b/boards/arm/stm32f0/stm32f072-discovery/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32f0/stm32f072-discovery/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/arm/stm32f0l0g0/stm32f072-discovery/Kconfig b/boards/arm/stm32f0/stm32f072-discovery/Kconfig similarity index 100% rename from boards/arm/stm32f0l0g0/stm32f072-discovery/Kconfig rename to boards/arm/stm32f0/stm32f072-discovery/Kconfig diff --git a/boards/arm/stm32f0/stm32f072-discovery/configs/nsh/defconfig b/boards/arm/stm32f0/stm32f072-discovery/configs/nsh/defconfig new file mode 100644 index 0000000000000..8496c183dd9c7 --- /dev/null +++ b/boards/arm/stm32f0/stm32f072-discovery/configs/nsh/defconfig @@ -0,0 +1,47 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_DISABLEBG is not set +# CONFIG_NSH_DISABLE_EXEC is not set +# CONFIG_NSH_DISABLE_EXIT is not set +# CONFIG_NSH_DISABLE_HEXDUMP is not set +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_NSH_DISABLE_XD is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f072-discovery" +CONFIG_ARCH_BOARD_STM32F072_DISCOVERY=y +CONFIG_ARCH_CHIP="stm32f0" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F072RB=y +CONFIG_ARCH_CHIP_STM32F0=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=2796 +CONFIG_DEFAULT_SMALL=y +CONFIG_DISABLE_MOUNTPOINT=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=1536 +CONFIG_MM_SMALL=y +CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 +CONFIG_NSH_FILEIOSIZE=64 +CONFIG_NUNGET_CHARS=0 +CONFIG_POSIX_SPAWN_DEFAULT_STACKSIZE=1536 +CONFIG_PTHREAD_STACK_DEFAULT=1536 +CONFIG_RAM_SIZE=8192 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=19 +CONFIG_START_MONTH=5 +CONFIG_START_YEAR=2013 +CONFIG_STM32_PWR=y +CONFIG_STM32_USART1=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART1_RXBUFSIZE=32 +CONFIG_USART1_SERIAL_CONSOLE=y +CONFIG_USART1_TXBUFSIZE=32 diff --git a/boards/arm/stm32f0/stm32f072-discovery/include/board.h b/boards/arm/stm32f0/stm32f072-discovery/include/board.h new file mode 100644 index 0000000000000..52a339aee2a6f --- /dev/null +++ b/boards/arm/stm32f0/stm32f072-discovery/include/board.h @@ -0,0 +1,246 @@ +/**************************************************************************** + * boards/arm/stm32f0/stm32f072-discovery/include/board.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_STM32F0L0G0_STM32F072_DISCOVERY_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32F0L0G0_STM32F072_DISCOVERY_INCLUDE_BOARD_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#ifndef __ASSEMBLY__ +# include +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Clocking *****************************************************************/ + +/* Four different clock sources can be used to drive the system clock + * (SYSCLK): + * + * - HSI high-speed internal oscillator clock + * Generated from an internal 8 MHz RC oscillator + * - HSE high-speed external oscillator clock + * Normally driven by an external crystal (X3). However, this crystal is + * not fitted on the STM32F0-Discovery board. + * - PLL clock + * - MSI multispeed internal oscillator clock + * The MSI clock signal is generated from an internal RC oscillator. Seven + * frequency ranges are available: 65.536 kHz, 131.072 kHz, 262.144 kHz, + * 524.288 kHz, 1.048 MHz, 2.097 MHz (default value) and 4.194 MHz. + * + * The devices have the following two secondary clock sources + * - LSI low-speed internal RC clock + * Drives the watchdog and RTC. Approximately 37KHz + * - LSE low-speed external oscillator clock + * Driven by 32.768KHz crystal (X2) on the OSC32_IN and OSC32_OUT pins. + */ + +#define STM32_BOARD_XTAL 8000000ul /* X3 on board (not fitted)*/ + +#define STM32_HSI_FREQUENCY 8000000ul /* Approximately 8MHz */ +#define STM32_HSI14_FREQUENCY 14000000ul /* HSI14 for ADC */ +#define STM32_HSI48_FREQUENCY 48000000ul /* HSI48 for USB, only some STM32F0xx */ +#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL +#define STM32_LSI_FREQUENCY 40000 /* Approximately 40KHz */ +#define STM32_LSE_FREQUENCY 32768 /* X2 on board */ + +/* PLL Configuration + * + * - PLL source is HSI -> 8MHz input (nominal) + * - PLL source predivider 2 -> 4MHz divided down PLL VCO clock output + * - PLL multiplier is 12 -> 48MHz PLL VCO clock output (for USB) + * + * Resulting SYSCLK frequency is 8MHz x 12 / 2 = 48MHz + * + * USB: + * If the USB interface is used in the application, it requires a precise + * 48MHz clock which can be generated from either the (1) the internal + * main PLL with the HSE clock source using an HSE crystal oscillator. In + * this case, the PLL VCO clock (defined by STM32_CFGR_PLLMUL) must be + * programmed to output a 96 MHz frequency. This is required to provide a + * 48MHz clock to the (USBCLK = PLLVCO/2). Or (2) by using the internal + * 48MHz oscillator in automatic trimming mode. The synchronization for + * this oscillator can be taken from the USB data stream itself (SOF + * signalization) which allows crystal-less operation. + * SYSCLK + * The system clock is derived from the PLL VCO divided by the output + * division factor. + * Limitations: + * - 96 MHz as PLLVCO when the product is in range 1 (1.8V), + * - 48 MHz as PLLVCO when the product is in range 2 (1.5V), + * - 24 MHz when the product is in range 3 (1.2V). + * - Output division to avoid exceeding 32 MHz as SYSCLK. + * - The minimum input clock frequency for PLL is 2 MHz (when using HSE as + * PLL source). + */ + +#define STM32_CFGR_PLLSRC RCC_CFGR_PLLSRC_HSId2 /* Source is HSI/2 */ +#define STM32_PLLSRC_FREQUENCY (STM32_HSI_FREQUENCY/2) /* 8MHz / 2 = 4MHz */ +#ifdef CONFIG_STM32_USB +# undef STM32_CFGR2_PREDIV /* Not used with source HSI/2 */ +# define STM32_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx12 /* PLLMUL = 12 */ +# define STM32_PLL_FREQUENCY (12*STM32_PLLSRC_FREQUENCY) /* PLL VCO Frequency is 48MHz */ +#else +# undef STM32_CFGR2_PREDIV /* Not used with source HSI/2 */ +# define STM32_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx12 /* PLLMUL = 12 */ +# define STM32_PLL_FREQUENCY (12*STM32_PLLSRC_FREQUENCY) /* PLL VCO Frequency is 48MHz */ +#endif + +/* Use the PLL and set the SYSCLK source to be the divided down PLL VCO + * output frequency (STM32_PLL_FREQUENCY divided by the PLLDIV value). + */ + +#define STM32_SYSCLK_SW RCC_CFGR_SW_PLL /* Use the PLL as the SYSCLK */ +#define STM32_SYSCLK_SWS RCC_CFGR_SWS_PLL +#ifdef CONFIG_STM32_USB +# define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY /* SYSCLK frequency is PLL VCO = 48MHz */ +#else +# define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY /* SYSCLK frequency is PLL VCO = 48MHz */ +#endif + +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY + +/* APB1 clock (PCLK1) is HCLK (48MHz) */ + +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY) + +/* APB2 clock (PCLK2) is HCLK (48MHz) */ + +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK +#define STM32_PCLK2_FREQUENCY STM32_HCLK_FREQUENCY +#define STM32_APB2_CLKIN (STM32_PCLK2_FREQUENCY) + +/* APB1 timers 1-3, 6-7, and 14-17 will receive PCLK1 */ + +#define STM32_APB1_TIM1_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM2_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (STM32_PCLK1_FREQUENCY) + +#define STM32_APB1_TIM6_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (STM32_PCLK1_FREQUENCY) + +#define STM32_APB1_TIM14_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM15_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM16_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM17_CLKIN (STM32_PCLK1_FREQUENCY) + +/* LED definitions **********************************************************/ + +/* The STM32F0-Discovery board has four LEDs. Two of these are controlled by + * logic on the board and are not available for software control: + * + * LD1 COM: LD2 default status is red. LD2 turns to green to indicate that + * communications are in progress between the PC and the + * ST-LINK/V2. + * LD2 PWR: Red LED indicates that the board is powered. + * + * And two LEDs can be controlled by software: + * + * User LD3: Green LED is a user LED connected to the I/O PB7 of the + * STM32F072RB MCU. + * User LD4: Blue LED is a user LED connected to the I/O PB6 of the + * STM32F072RB MCU. + * + * If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs + * in any way. + * The following definitions are used to access individual LEDs. + */ + +/* LED index values for use with board_userled() */ + +#define BOARD_LED1 0 /* User LD_U */ +#define BOARD_LED2 1 /* User LD_D */ +#define BOARD_LED3 2 /* User LD_L */ +#define BOARD_LED4 3 /* User LD_R */ +#define BOARD_NLEDS 4 + +/* LED bits for use with board_userled_all() */ + +#define BOARD_LED1_BIT (1 << BOARD_LED1) +#define BOARD_LED2_BIT (1 << BOARD_LED2) +#define BOARD_LED3_BIT (1 << BOARD_LED3) +#define BOARD_LED4_BIT (1 << BOARD_LED4) + +/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the 8 LEDs on + * board the STM32F0-Discovery. + * The following definitions describe how NuttX controls the LEDs: + * + * SYMBOL Meaning LED state + * LED1 LED2 + * ------------------- ----------------------- -------- -------- + * LED_STARTED NuttX has been started OFF OFF + * LED_HEAPALLOCATE Heap has been allocated OFF OFF + * LED_IRQSENABLED Interrupts enabled OFF OFF + * LED_STACKCREATED Idle stack created ON OFF + * LED_INIRQ In an interrupt No change + * LED_SIGNAL In a signal handler No change + * LED_ASSERTION An assertion failed No change + * LED_PANIC The system has crashed OFF Blinking + * LED_IDLE STM32 is in sleep mode Not used + */ + +#define LED_STARTED 0 +#define LED_HEAPALLOCATE 0 +#define LED_IRQSENABLED 0 +#define LED_STACKCREATED 1 +#define LED_INIRQ 2 +#define LED_SIGNAL 2 +#define LED_ASSERTION 2 +#define LED_PANIC 3 + +/* Button definitions *******************************************************/ + +/* The STM32F0-Discovery supports two buttons; only one button is + * controllable by software: + * + * B1 USER: + * user and wake-up button connected to the I/O PA0 of the STM32F072RB. + * B2 RESET: + * pushbutton connected to NRST is used to RESET the STM32F072RB. + */ + +#define BUTTON_USER 0 +#define NUM_BUTTONS 1 + +#define BUTTON_USER_BIT (1 << BUTTON_USER) + +/* Alternate Pin Functions **************************************************/ + +/* USART 1 */ + +#define GPIO_USART1_TX (GPIO_USART1_TX_1|GPIO_SPEED_HIGH) +#define GPIO_USART1_RX (GPIO_USART1_RX_1|GPIO_SPEED_HIGH) + +/* I2C pins definition */ + +#define GPIO_I2C1_SCL (GPIO_I2C1_SCL_1|GPIO_SPEED_LOW) +#define GPIO_I2C1_SDA (GPIO_I2C1_SDA_1|GPIO_SPEED_LOW) + +#endif /* __BOARDS_ARM_STM32F0L0G0_STM32F072_DISCOVERY_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32f0/stm32f072-discovery/scripts/Make.defs b/boards/arm/stm32f0/stm32f072-discovery/scripts/Make.defs new file mode 100644 index 0000000000000..9796d338da43e --- /dev/null +++ b/boards/arm/stm32f0/stm32f072-discovery/scripts/Make.defs @@ -0,0 +1,41 @@ +############################################################################ +# boards/arm/stm32f0/stm32f072-discovery/scripts/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/.config +include $(TOPDIR)/tools/Config.mk +include $(TOPDIR)/arch/arm/src/armv6-m/Toolchain.defs + +LDSCRIPT = flash.ld +ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) + +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32f0/stm32f072-discovery/scripts/flash.ld b/boards/arm/stm32f0/stm32f072-discovery/scripts/flash.ld new file mode 100644 index 0000000000000..fc42f97036ae7 --- /dev/null +++ b/boards/arm/stm32f0/stm32f072-discovery/scripts/flash.ld @@ -0,0 +1,109 @@ +/**************************************************************************** + * boards/arm/stm32f0/stm32f072-discovery/scripts/flash.ld + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* The STM32F072RBT6 has 128KB of FLASH beginning at address 0x0800:0000 and + * 16Kb of SRAM at address 0x20000000. + * + * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 + * where the code expects to begin execution by jumping to the entry point in + * the 0x0800:0000 address range. + */ + +MEMORY +{ + flash (rx) : ORIGIN = 0x08000000, LENGTH = 128K + sram (rwx) : ORIGIN = 0x20000000, LENGTH = 16K +} + +OUTPUT_ARCH(arm) +EXTERN(_vectors) +ENTRY(_stext) + +SECTIONS +{ + .text : { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > flash + + .init_section : ALIGN(4) { + _sinit = ABSOLUTE(.); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) + _einit = ABSOLUTE(.); + } > flash + + .ARM.extab ALIGN(4): { + *(.ARM.extab*) + } > flash + + .ARM.exidx : ALIGN(4) { + __exidx_start = ABSOLUTE(.); + *(.ARM.exidx*) + __exidx_end = ABSOLUTE(.); + } > flash + + _eronly = ABSOLUTE(.); + + .data : ALIGN(4) { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > sram AT > flash + + .bss : ALIGN(4) { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(8); + _ebss = ABSOLUTE(.); + } > sram + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/stm32f0/stm32f072-discovery/src/CMakeLists.txt b/boards/arm/stm32f0/stm32f072-discovery/src/CMakeLists.txt new file mode 100644 index 0000000000000..4a75392b78b99 --- /dev/null +++ b/boards/arm/stm32f0/stm32f072-discovery/src/CMakeLists.txt @@ -0,0 +1,49 @@ +# ############################################################################## +# boards/arm/stm32f0/stm32f072-discovery/src/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(SRCS stm32_boot.c stm32_bringup.c) + +if(CONFIG_ARCH_LEDS) + list(APPEND SRCS stm32_autoleds.c) +else() + list(APPEND SRCS stm32_userleds.c) +endif() + +if(CONFIG_ARCH_BUTTONS) + list(APPEND SRCS stm32_buttons.c) +endif() + +if(CONFIG_STM32_SPI) + list(APPEND SRCS stm32_spi.c) +endif() + +if(CONFIG_PWM) + list(APPEND SRCS stm32_pwm.c) +endif() + +if(CONFIG_SENSORS_QENCODER) + list(APPEND SRCS stm32_qencoder.c) +endif() + +target_sources(board PRIVATE ${SRCS}) + +set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/flash.ld") diff --git a/boards/arm/stm32f0/stm32f072-discovery/src/Make.defs b/boards/arm/stm32f0/stm32f072-discovery/src/Make.defs new file mode 100644 index 0000000000000..e5b94f00634df --- /dev/null +++ b/boards/arm/stm32f0/stm32f072-discovery/src/Make.defs @@ -0,0 +1,51 @@ +############################################################################ +# boards/arm/stm32f0/stm32f072-discovery/src/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +CSRCS = stm32_boot.c stm32_bringup.c + +ifeq ($(CONFIG_ARCH_LEDS),y) +CSRCS += stm32_autoleds.c +else +CSRCS += stm32_userleds.c +endif + +ifeq ($(CONFIG_ARCH_BUTTONS),y) +CSRCS += stm32_buttons.c +endif + +ifeq ($(CONFIG_STM32_SPI),y) +CSRCS += stm32_spi.c +endif + +ifeq ($(CONFIG_PWM),y) +CSRCS += stm32_pwm.c +endif + +ifeq ($(CONFIG_SENSORS_QENCODER),y) +CSRCS += stm32_qencoder.c +endif + +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32f0/stm32f072-discovery/src/stm32_autoleds.c b/boards/arm/stm32f0/stm32f072-discovery/src/stm32_autoleds.c new file mode 100644 index 0000000000000..dc5246da6554a --- /dev/null +++ b/boards/arm/stm32f0/stm32f072-discovery/src/stm32_autoleds.c @@ -0,0 +1,123 @@ +/**************************************************************************** + * boards/arm/stm32f0/stm32f072-discovery/src/stm32_autoleds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "chip.h" +#include "stm32f072-discovery.h" + +#ifdef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the 2 LEDs on + * board the STM32L-Discovery. The following definitions describe how NuttX + * controls the LEDs: + * + * SYMBOL Meaning LED state + * LED1 LED2 + * ------------------- ----------------------- -------- -------- + * LED_STARTED NuttX has been started OFF OFF + * LED_HEAPALLOCATE Heap has been allocated OFF OFF + * LED_IRQSENABLED Interrupts enabled OFF OFF + * LED_STACKCREATED Idle stack created ON OFF + * LED_INIRQ In an interrupt No change + * LED_SIGNAL In a signal handler No change + * LED_ASSERTION An assertion failed No change + * LED_PANIC The system has crashed OFF Blinking + * LED_IDLE STM32 is in sleep mode Not used + */ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_autoled_initialize + ****************************************************************************/ + +void board_autoled_initialize(void) +{ + /* Configure LED1-2 GPIOs for output */ + + stm32_configgpio(GPIO_LED1); + stm32_configgpio(GPIO_LED2); +} + +/**************************************************************************** + * Name: board_autoled_on + ****************************************************************************/ + +void board_autoled_on(int led) +{ + bool led1on = false; + bool led2on = false; + + switch (led) + { + case 0: /* LED_STARTED, LED_HEAPALLOCATE, LED_IRQSENABLED */ + break; + + case 1: /* LED_STACKCREATED */ + led1on = true; + break; + + default: + case 2: /* LED_INIRQ, LED_SIGNAL, LED_ASSERTION */ + return; + + case 3: /* LED_PANIC */ + led2on = true; + break; + } + + stm32_gpiowrite(GPIO_LED1, led1on); + stm32_gpiowrite(GPIO_LED2, led2on); +} + +/**************************************************************************** + * Name: board_autoled_off + ****************************************************************************/ + +void board_autoled_off(int led) +{ + if (led != 2) + { + stm32_gpiowrite(GPIO_LED1, false); + stm32_gpiowrite(GPIO_LED2, false); + } +} + +#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32f0/stm32f072-discovery/src/stm32_boot.c b/boards/arm/stm32f0/stm32f072-discovery/src/stm32_boot.c new file mode 100644 index 0000000000000..5992d7a77ca33 --- /dev/null +++ b/boards/arm/stm32f0/stm32f072-discovery/src/stm32_boot.c @@ -0,0 +1,81 @@ +/**************************************************************************** + * boards/arm/stm32f0/stm32f072-discovery/src/stm32_boot.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include +#include + +#include "arm_internal.h" +#include "stm32f072-discovery.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_boardinitialize + * + * Description: + * All STM32 architectures must provide the following entry point. + * This entry point is called early in the initialization -- after all + * memory has been configured and mapped but before any devices have been + * initialized. + * + ****************************************************************************/ + +void stm32_boardinitialize(void) +{ +#ifdef CONFIG_ARCH_LEDS + /* Configure on-board LEDs if LED support has been selected. */ + + board_autoled_initialize(); +#endif +} + +/**************************************************************************** + * Name: board_late_initialize + * + * Description: + * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_late_initialize(). board_late_initialize() will be + * called immediately after up_initialize() is called and just before the + * initial application is started. This additional initialization phase + * may be used, for example, to initialize board-specific device drivers. + * + ****************************************************************************/ + +#ifdef CONFIG_BOARD_LATE_INITIALIZE +void board_late_initialize(void) +{ + /* Perform board-specific initialization here if so configured */ + + stm32_bringup(); +} +#endif diff --git a/boards/arm/stm32f0/stm32f072-discovery/src/stm32_bringup.c b/boards/arm/stm32f0/stm32f072-discovery/src/stm32_bringup.c new file mode 100644 index 0000000000000..48c86e9507bc9 --- /dev/null +++ b/boards/arm/stm32f0/stm32f072-discovery/src/stm32_bringup.c @@ -0,0 +1,66 @@ +/**************************************************************************** + * boards/arm/stm32f0/stm32f072-discovery/src/stm32_bringup.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include + +#include "stm32f072-discovery.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_bringup + * + * Description: + * Perform architecture-specific initialization + * + * CONFIG_BOARD_LATE_INITIALIZE=y : + * Called from board_late_initialize(). + * + ****************************************************************************/ + +int stm32_bringup(void) +{ + int ret; + +#ifdef CONFIG_FS_PROCFS + /* Mount the procfs file system */ + + ret = nx_mount(NULL, "/proc", "procfs", 0, NULL); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to mount procfs at /proc: %d\n", ret); + } +#endif + + UNUSED(ret); + return OK; +} diff --git a/boards/arm/stm32f0/stm32f072-discovery/src/stm32_buttons.c b/boards/arm/stm32f0/stm32f072-discovery/src/stm32_buttons.c new file mode 100644 index 0000000000000..a4c7fa265fddd --- /dev/null +++ b/boards/arm/stm32f0/stm32f072-discovery/src/stm32_buttons.c @@ -0,0 +1,150 @@ +/**************************************************************************** + * boards/arm/stm32f0/stm32f072-discovery/src/stm32_buttons.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include +#include + +#include "stm32f072-discovery.h" + +#ifdef CONFIG_ARCH_BUTTONS + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* Pin configuration for each STM32F3Discovery button. This array is + * indexed by the BUTTON_* definitions in board.h + */ + +static const uint32_t g_buttons[NUM_BUTTONS] = +{ + GPIO_BTN_USER +}; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_button_initialize + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. + * + ****************************************************************************/ + +uint32_t board_button_initialize(void) +{ + int i; + + /* Configure the GPIO pins as inputs. NOTE that EXTI interrupts are + * configured for all pins. + */ + + for (i = 0; i < NUM_BUTTONS; i++) + { + stm32_configgpio(g_buttons[i]); + } + + return NUM_BUTTONS; +} + +/**************************************************************************** + * Name: board_buttons + ****************************************************************************/ + +uint8_t board_buttons(void) +{ + uint8_t ret = 0; + int i; + + /* Check that state of each key */ + + for (i = 0; i < NUM_BUTTONS; i++) + { + /* A LOW value means that the key is pressed. */ + + bool released = stm32_gpioread(g_buttons[i]); + + /* Accumulate the set of depressed (not released) keys */ + + if (!released) + { + ret |= (1 << i); + } + } + + return ret; +} + +/**************************************************************************** + * Button support. + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. + * + * After board_button_initialize() has been called, board_buttons() may be + * called to collect the state of all buttons. board_buttons() returns an + * 8-bit bit set with each bit associated with a button. See the + * BUTTON_*_BIT definitions in board.h for the meaning of each bit. + * + * board_button_irq() may be called to register an interrupt handler that + * will be called when a button is depressed or released. The ID value is a + * button enumeration value that uniquely identifies a button resource. See + * the BUTTON_* definitions in board.h for the meaning of enumeration + * value. + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_IRQBUTTONS +int board_button_irq(int id, xcpt_t irqhandler, void *arg) +{ + int ret = -EINVAL; + + /* The following should be atomic */ + + if (id >= MIN_IRQBUTTON && id <= MAX_IRQBUTTON) + { + ret = stm32_gpiosetevent(g_buttons[id], true, true, true, + irqhandler, arg); + } + + return ret; +} +#endif +#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/stm32f0/stm32f072-discovery/src/stm32_userleds.c b/boards/arm/stm32f0/stm32f072-discovery/src/stm32_userleds.c new file mode 100644 index 0000000000000..30c6009348449 --- /dev/null +++ b/boards/arm/stm32f0/stm32f072-discovery/src/stm32_userleds.c @@ -0,0 +1,113 @@ +/**************************************************************************** + * boards/arm/stm32f0/stm32f072-discovery/src/stm32_userleds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include + +#include "chip.h" +#include "stm32.h" +#include "stm32f072-discovery.h" + +#ifndef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_userled_initialize + ****************************************************************************/ + +uint32_t board_userled_initialize(void) +{ + /* Configure LED1-2 GPIOs for output */ + + stm32_configgpio(GPIO_LED1); + stm32_configgpio(GPIO_LED2); + stm32_configgpio(GPIO_LED3); + stm32_configgpio(GPIO_LED4); + return BOARD_NLEDS; +} + +/**************************************************************************** + * Name: board_userled + ****************************************************************************/ + +void board_userled(int led, bool ledon) +{ + uint32_t ledcfg; + + if (led == BOARD_LED1) + { + ledcfg = GPIO_LED1; + } + else if (led == BOARD_LED2) + { + ledcfg = GPIO_LED2; + } + else if (led == BOARD_LED3) + { + ledcfg = GPIO_LED3; + } + else if (led == BOARD_LED4) + { + ledcfg = GPIO_LED4; + } + else + { + return; + } + + stm32_gpiowrite(ledcfg, ledon); +} + +/**************************************************************************** + * Name: board_userled_all + ****************************************************************************/ + +void board_userled_all(uint32_t ledset) +{ + bool ledon; + + ledon = ((ledset & BOARD_LED1_BIT) != 0); + stm32_gpiowrite(GPIO_LED1, ledon); + + ledon = ((ledset & BOARD_LED2_BIT) != 0); + stm32_gpiowrite(GPIO_LED2, ledon); + + ledon = ((ledset & BOARD_LED3_BIT) != 0); + stm32_gpiowrite(GPIO_LED3, ledon); + + ledon = ((ledset & BOARD_LED4_BIT) != 0); + stm32_gpiowrite(GPIO_LED4, ledon); +} + +#endif /* !CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32f0l0g0/stm32f072-discovery/src/stm32f072-discovery.h b/boards/arm/stm32f0/stm32f072-discovery/src/stm32f072-discovery.h similarity index 94% rename from boards/arm/stm32f0l0g0/stm32f072-discovery/src/stm32f072-discovery.h rename to boards/arm/stm32f0/stm32f072-discovery/src/stm32f072-discovery.h index f085bb693bd16..482517929693b 100644 --- a/boards/arm/stm32f0l0g0/stm32f072-discovery/src/stm32f072-discovery.h +++ b/boards/arm/stm32f0/stm32f072-discovery/src/stm32f072-discovery.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/stm32f072-discovery/src/stm32f072-discovery.h + * boards/arm/stm32f0/stm32f072-discovery/src/stm32f072-discovery.h * * SPDX-License-Identifier: Apache-2.0 * @@ -42,14 +42,14 @@ /* How many SPI modules does this chip support? */ #if STM32_NSPI < 1 -# undef CONFIG_STM32F0L0G0_SPI1 -# undef CONFIG_STM32F0L0G0_SPI2 -# undef CONFIG_STM32F0L0G0_SPI3 +# undef CONFIG_STM32_SPI1 +# undef CONFIG_STM32_SPI2 +# undef CONFIG_STM32_SPI3 #elif STM32_NSPI < 2 -# undef CONFIG_STM32F0L0G0_SPI2 -# undef CONFIG_STM32F0L0G0_SPI3 +# undef CONFIG_STM32_SPI2 +# undef CONFIG_STM32_SPI3 #elif STM32_NSPI < 3 -# undef CONFIG_STM32F0L0G0_SPI3 +# undef CONFIG_STM32_SPI3 #endif /* STM32F0Discovery GPIOs ***************************************************/ diff --git a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/CMakeLists.txt b/boards/arm/stm32f0l0g0/b-l072z-lrwan1/CMakeLists.txt deleted file mode 100644 index be95ff78863a5..0000000000000 --- a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32f0l0g0/b-l072z-lrwan1/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/configs/adc/defconfig b/boards/arm/stm32f0l0g0/b-l072z-lrwan1/configs/adc/defconfig deleted file mode 100644 index 29a75f2172428..0000000000000 --- a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/configs/adc/defconfig +++ /dev/null @@ -1,58 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_NSH_ARGCAT is not set -CONFIG_ADC=y -CONFIG_ANALOG=y -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="b-l072z-lrwan1" -CONFIG_ARCH_BOARD_B_L072Z_LRWAN1=y -CONFIG_ARCH_CHIP="stm32f0l0g0" -CONFIG_ARCH_CHIP_STM32L072CZ=y -CONFIG_ARCH_CHIP_STM32L072XX=y -CONFIG_ARCH_CHIP_STM32L0=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARDCTL=y -CONFIG_BOARD_LOOPSPERMSEC=2796 -CONFIG_BUILTIN=y -CONFIG_DISABLE_ENVIRON=y -CONFIG_DISABLE_MOUNTPOINT=y -CONFIG_DISABLE_MQUEUE=y -CONFIG_DISABLE_PSEUDOFS_OPERATIONS=y -CONFIG_EXAMPLES_ADC=y -CONFIG_EXAMPLES_ADC_SWTRIG=y -CONFIG_EXPERIMENTAL=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INIT_STACKSIZE=1536 -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=64 -CONFIG_NSH_READLINE=y -CONFIG_NUNGET_CHARS=0 -CONFIG_POSIX_SPAWN_DEFAULT_STACKSIZE=1536 -CONFIG_PREALLOC_TIMERS=0 -CONFIG_PTHREAD_MUTEX_UNSAFE=y -CONFIG_PTHREAD_STACK_DEFAULT=1536 -CONFIG_RAM_SIZE=20480 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=19 -CONFIG_START_MONTH=5 -CONFIG_START_YEAR=2013 -CONFIG_STDIO_DISABLE_BUFFERING=y -CONFIG_STM32F0L0G0_ADC1=y -CONFIG_STM32F0L0G0_ADC1_DMA=y -CONFIG_STM32F0L0G0_DMA1=y -CONFIG_STM32F0L0G0_PWR=y -CONFIG_STM32F0L0G0_USART2=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/configs/nsh/defconfig b/boards/arm/stm32f0l0g0/b-l072z-lrwan1/configs/nsh/defconfig deleted file mode 100644 index 5fd878ff4ff73..0000000000000 --- a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/configs/nsh/defconfig +++ /dev/null @@ -1,51 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_NSH_ARGCAT is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="b-l072z-lrwan1" -CONFIG_ARCH_BOARD_B_L072Z_LRWAN1=y -CONFIG_ARCH_CHIP="stm32f0l0g0" -CONFIG_ARCH_CHIP_STM32L072CZ=y -CONFIG_ARCH_CHIP_STM32L072XX=y -CONFIG_ARCH_CHIP_STM32L0=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=2796 -CONFIG_BUILTIN=y -CONFIG_DISABLE_ENVIRON=y -CONFIG_DISABLE_MOUNTPOINT=y -CONFIG_DISABLE_MQUEUE=y -CONFIG_DISABLE_POSIX_TIMERS=y -CONFIG_DISABLE_PSEUDOFS_OPERATIONS=y -CONFIG_EXAMPLES_HELLO=y -CONFIG_EXPERIMENTAL=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INIT_STACKSIZE=1536 -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=64 -CONFIG_NSH_READLINE=y -CONFIG_NUNGET_CHARS=0 -CONFIG_POSIX_SPAWN_DEFAULT_STACKSIZE=1536 -CONFIG_PTHREAD_MUTEX_UNSAFE=y -CONFIG_PTHREAD_STACK_DEFAULT=1536 -CONFIG_RAM_SIZE=20480 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=19 -CONFIG_START_MONTH=5 -CONFIG_START_YEAR=2013 -CONFIG_STDIO_DISABLE_BUFFERING=y -CONFIG_STM32F0L0G0_PWR=y -CONFIG_STM32F0L0G0_USART2=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/configs/nxlines_oled/defconfig b/boards/arm/stm32f0l0g0/b-l072z-lrwan1/configs/nxlines_oled/defconfig deleted file mode 100644 index bd5efbbb3c5ac..0000000000000 --- a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/configs/nxlines_oled/defconfig +++ /dev/null @@ -1,64 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_EXAMPLES_NXLINES_DEFAULT_COLORS is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NX_DISABLE_1BPP is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="b-l072z-lrwan1" -CONFIG_ARCH_BOARD_B_L072Z_LRWAN1=y -CONFIG_ARCH_BOARD_COMMON=y -CONFIG_ARCH_CHIP="stm32f0l0g0" -CONFIG_ARCH_CHIP_STM32L072CZ=y -CONFIG_ARCH_CHIP_STM32L072XX=y -CONFIG_ARCH_CHIP_STM32L0=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=2796 -CONFIG_BUILTIN=y -CONFIG_EXAMPLES_NXLINES=y -CONFIG_EXAMPLES_NXLINES_BORDERWIDTH=1 -CONFIG_EXAMPLES_NXLINES_BPP=1 -CONFIG_EXAMPLES_NXLINES_LINECOLOR=0xff -CONFIG_EXAMPLES_NXLINES_LINEWIDTH=1 -CONFIG_EXPERIMENTAL=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INIT_STACKSIZE=1536 -CONFIG_INTELHEX_BINARY=y -CONFIG_LCD=y -CONFIG_LCD_MAXCONTRAST=255 -CONFIG_LCD_SH1106_OLED_132=y -CONFIG_LCD_SSD1306_I2C=y -CONFIG_LINE_MAX=64 -CONFIG_MQ_MAXMSGSIZE=64 -CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=64 -CONFIG_NSH_READLINE=y -CONFIG_NUNGET_CHARS=0 -CONFIG_NX=y -CONFIG_NXFONT_MONO5X8=y -CONFIG_NX_BLOCKING=y -CONFIG_POSIX_SPAWN_DEFAULT_STACKSIZE=1536 -CONFIG_PREALLOC_TIMERS=0 -CONFIG_PTHREAD_MUTEX_UNSAFE=y -CONFIG_PTHREAD_STACK_DEFAULT=1536 -CONFIG_RAM_SIZE=20480 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=19 -CONFIG_START_MONTH=5 -CONFIG_START_YEAR=2013 -CONFIG_STDIO_DISABLE_BUFFERING=y -CONFIG_STM32F0L0G0_I2C1=y -CONFIG_STM32F0L0G0_PWR=y -CONFIG_STM32F0L0G0_USART2=y -CONFIG_SYSTEM_NSH=y -CONFIG_SYSTEM_NSH_STACKSIZE=1024 -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/configs/sx127x/defconfig b/boards/arm/stm32f0l0g0/b-l072z-lrwan1/configs/sx127x/defconfig deleted file mode 100644 index 7ed1d73f33808..0000000000000 --- a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/configs/sx127x/defconfig +++ /dev/null @@ -1,61 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_NSH_ARGCAT is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="b-l072z-lrwan1" -CONFIG_ARCH_BOARD_B_L072Z_LRWAN1=y -CONFIG_ARCH_CHIP="stm32f0l0g0" -CONFIG_ARCH_CHIP_STM32L072CZ=y -CONFIG_ARCH_CHIP_STM32L072XX=y -CONFIG_ARCH_CHIP_STM32L0=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=2796 -CONFIG_BUILTIN=y -CONFIG_DISABLE_ENVIRON=y -CONFIG_DISABLE_MOUNTPOINT=y -CONFIG_DISABLE_MQUEUE=y -CONFIG_DISABLE_POSIX_TIMERS=y -CONFIG_DISABLE_PSEUDOFS_OPERATIONS=y -CONFIG_DRIVERS_LPWAN=y -CONFIG_DRIVERS_WIRELESS=y -CONFIG_EXAMPLES_HELLO=y -CONFIG_EXAMPLES_SX127X=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INIT_STACKSIZE=1536 -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_LPWAN_SX127X=y -CONFIG_LPWAN_SX127X_FSKOOK=y -CONFIG_LPWAN_SX127X_MODULATION_DEFAULT=1 -CONFIG_LPWAN_SX127X_RFFREQ_DEFAULT=930000000 -CONFIG_LPWAN_SX127X_RXSUPPORT=y -CONFIG_LPWAN_SX127X_TXSUPPORT=y -CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=64 -CONFIG_NSH_READLINE=y -CONFIG_NUNGET_CHARS=0 -CONFIG_POSIX_SPAWN_DEFAULT_STACKSIZE=1536 -CONFIG_PTHREAD_MUTEX_UNSAFE=y -CONFIG_PTHREAD_STACK_DEFAULT=1536 -CONFIG_RAM_SIZE=20480 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=19 -CONFIG_START_MONTH=5 -CONFIG_START_YEAR=2013 -CONFIG_STDIO_DISABLE_BUFFERING=y -CONFIG_STM32F0L0G0_PWR=y -CONFIG_STM32F0L0G0_SPI1=y -CONFIG_STM32F0L0G0_USART2=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/include/board.h b/boards/arm/stm32f0l0g0/b-l072z-lrwan1/include/board.h deleted file mode 100644 index 7ce26a908b00c..0000000000000 --- a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/include/board.h +++ /dev/null @@ -1,270 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32f0l0g0/b-l072z-lrwan1/include/board.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __BOARDS_ARM_STM32F0L0G0_B_L072Z_LRWAN1_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32F0L0G0_B_L072Z_LRWAN1_INCLUDE_BOARD_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#ifndef __ASSEMBLY__ -# include -# include -#endif - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Clocking *****************************************************************/ - -/* HSI - Internal 16 MHz RC Oscillator - * LSI - 32 KHz RC - * HSE - 8 MHz from MCO output of ST-LINK (default OFF on board) - * LSE - 32.768 kHz - */ - -#define STM32_BOARD_XTAL 8000000ul - -#define STM32_HSI_FREQUENCY 16000000ul -#define STM32_LSI_FREQUENCY 32000 /* Between 30kHz and 60kHz */ -#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL -#define STM32_LSE_FREQUENCY 32768 /* X2 on board */ - -/* PLL source is HSI/1, PLL multiplier is 4: - * PLL frequency is 16MHz (XTAL) x 4 = 64MHz - */ - -#define STM32_CFGR_PLLSRC 0 -#define STM32_CFGR_PLLXTPRE 0 -#define STM32_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx4 -#define STM32_PLL_FREQUENCY (4*STM32_HSI_FREQUENCY) - -/* Use the PLL and set the SYSCLK source to be the PLL/2 (32MHz) */ - -#define STM32_SYSCLK_SW RCC_CFGR_SW_PLL -#define STM32_SYSCLK_SWS RCC_CFGR_SWS_PLL -#define STM32_CFGR_PLLDIV RCC_CFGR_PLLDIV_2 -#define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY/2 - -/* AHB clock (HCLK) is SYSCLK (32MHz) */ - -#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK -#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY - -/* APB2 clock (PCLK2) is HCLK (32MHz) */ - -#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK -#define STM32_PCLK2_FREQUENCY STM32_HCLK_FREQUENCY -#define STM32_APB2_CLKIN (STM32_PCLK2_FREQUENCY) - -/* APB1 clock (PCLK1) is HCLK/2 (16MHz) */ - -#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd2 -#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/2) - -/* 48MHz clock configuration */ - -#if defined(CONFIG_STM32F0L0G0_USB) || defined(CONFIG_STM32F0L0G0_RNG) -# define STM32_USE_CLK48 1 -# define STM32_CLK48_SEL RCC_CCIPR_CLK48SEL_HSI48 -# define STM32_HSI48_SYNCSRC SYNCSRC_NONE -#endif - -/* TODO: timers */ - -/* LED definitions **********************************************************/ - -/* The Nucleo LO73RZ board has three LEDs. Two of these are controlled by - * logic on the board and are not available for software control: - * - * LD1 COM: LD1 default status is red. LD1 turns to green to indicate that - * communications are in progress between the PC and the - * ST-LINK/V2-1. - * LD3 PWR: red LED indicates that the board is powered. - * - * And one can be controlled by software: - * - * User LD2: green LED is a user LED connected to the I/O PA5 of the - * STM32LO73RZ. - * - * If CONFIG_ARCH_LEDS is not defined, then the user can control the LED in - * any way. The following definition is used to access the LED. - */ - -/* LED index values for use with board_userled() */ - -#define BOARD_LED1 0 /* User LD2 */ -#define BOARD_NLEDS 1 - -/* LED bits for use with board_userled_all() */ - -#define BOARD_LED1_BIT (1 << BOARD_LED1) - -/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the LED on board - * the Nucleo LO73RZ. The following definitions describe how NuttX controls - * the LED: - * - * SYMBOL Meaning LED1 state - * ------------------ ----------------------- ---------- - * LED_STARTED NuttX has been started OFF - * LED_HEAPALLOCATE Heap has been allocated OFF - * LED_IRQSENABLED Interrupts enabled OFF - * LED_STACKCREATED Idle stack created ON - * LED_INIRQ In an interrupt No change - * LED_SIGNAL In a signal handler No change - * LED_ASSERTION An assertion failed No change - * LED_PANIC The system has crashed Blinking - * LED_IDLE STM32 is in sleep mode Not used - */ - -#define LED_STARTED 0 -#define LED_HEAPALLOCATE 0 -#define LED_IRQSENABLED 0 -#define LED_STACKCREATED 1 -#define LED_INIRQ 2 -#define LED_SIGNAL 2 -#define LED_ASSERTION 2 -#define LED_PANIC 1 - -/* Button definitions *******************************************************/ - -/* The Nucleo LO73RZ supports two buttons; only one button is controllable - * by software: - * - * B1 USER: user button connected to the I/O PB2/PA0 of the STM32LO73RZ. - * B2 RESET: push button connected to NRST is used to RESET the - * STM32LO73RZ. - */ - -#define BUTTON_USER 0 -#define NUM_BUTTONS 1 - -#define BUTTON_USER_BIT (1 << BUTTON_USER) - -/* Alternate function pin selections ****************************************/ - -/* CMWX1ZZABZ-091 module pinout and internal connections - * - * STM32L072CZ | Function - * ------------+----------- - * PC0 | SX1276_CE (NRESET) - * PA7 | SX1276_MOSI - * PA6 | SX1276_MISO - * PB3 | SX1276_SCK - * PA15 | SX1276_NSS - * PB4 | SX1276_DIO0 - * PB1 | SX1276_DIO1 - * PB0 | SX1276_DIO2 - * PC13 | SX1276_DIO3 - * PA5 | SX1276_DIO4 optional / LED5 - * PA4 | SX1276_DIO5 optional - * PA1 | CRF1 - * PC1 | CRF2 - * PC2 | CRF3 - * PA3 | STLINK Virtual COM RX - * PA2 | STLINK Virtual COM TX - * PA10 | USART1_RX - * PA9 | USART1_TX - * PB15 | SPI2_MOSI - * PB14 | SPI2_MISO - * PB13 | SPI2_SCK - * PB12 | SPI2_NSS - * PB5 | LPTIM1_INI / LED2 - * PB6 | LPTIM1_ETR / LED3 - * PB7 | LPTIM1_IN2 / LED4 - * PB2 | LPTIM1_OUT / BUTTON - * PA0 | BUTTON (optional) - * PB9 | I2C1_SDA - * PB8 | I2C1_SCL - * PA12 | USB_DP optional / TCXO_VCC - * PA11 | USB_DM optional - * - */ - -/* ADC */ - -#define GPIO_ADC1_IN0 (GPIO_ADC1_IN0_0) /* PA0 */ -#define GPIO_ADC1_IN1 (GPIO_ADC1_IN1_0) /* PA1 */ -#define GPIO_ADC1_IN2 (GPIO_ADC1_IN2_0) /* PA2 */ -#define GPIO_ADC1_IN3 (GPIO_ADC1_IN3_0) /* PA3 */ -#define GPIO_ADC1_IN4 (GPIO_ADC1_IN4_0) /* PA4 */ -#define GPIO_ADC1_IN5 (GPIO_ADC1_IN5_0) /* PA5 */ -#define GPIO_ADC1_IN6 (GPIO_ADC1_IN6_0) /* PA6 */ -#define GPIO_ADC1_IN7 (GPIO_ADC1_IN7_0) /* PA7 */ -#define GPIO_ADC1_IN8 (GPIO_ADC1_IN8_0) /* PB0 */ -#define GPIO_ADC1_IN9 (GPIO_ADC1_IN9_0) /* PB1 */ -#define GPIO_ADC1_IN10 (GPIO_ADC1_IN10_0) /* PC0 */ -#define GPIO_ADC1_IN11 (GPIO_ADC1_IN11_0) /* PC1 */ -#define GPIO_ADC1_IN12 (GPIO_ADC1_IN12_0) /* PC2 */ -#define GPIO_ADC1_IN13 (GPIO_ADC1_IN13_0) /* PC3 */ -#define GPIO_ADC1_IN14 (GPIO_ADC1_IN14_0) /* PC4 */ -#define GPIO_ADC1_IN15 (GPIO_ADC1_IN15_0) /* PC5 */ - -/* USART */ - -/* USART1 */ - -#define GPIO_USART1_RX (GPIO_USART1_RX_1|GPIO_SPEED_HIGH) /* PA10 */ -#define GPIO_USART1_TX (GPIO_USART1_TX_1|GPIO_SPEED_HIGH) /* PA9 */ - -/* By default the USART2 is connected to STLINK Virtual COM Port: - * USART2_RX - PA3 - * USART2_TX - PA2 - */ - -#define GPIO_USART2_RX (GPIO_USART2_RX_1|GPIO_SPEED_HIGH) /* PA3 */ -#define GPIO_USART2_TX (GPIO_USART2_TX_1|GPIO_SPEED_HIGH) /* PA2 */ - -/* SPI */ - -/* SPI1 is connected to SX1276 radio */ - -#define GPIO_SPI1_MOSI (GPIO_SPI1_MOSI_2|GPIO_SPEED_MEDIUM) /* PA7 */ -#define GPIO_SPI1_MISO (GPIO_SPI1_MISO_2|GPIO_SPEED_MEDIUM) /* PA6 */ -#define GPIO_SPI1_SCK (GPIO_SPI1_SCK_2|GPIO_SPEED_MEDIUM) /* PB3 */ -#define GPIO_SPI1_NSS (GPIO_SPI1_NSS_1|GPIO_SPEED_MEDIUM) /* PA15 */ - -/* SPI2 */ - -#define GPIO_SPI2_MOSI (GPIO_SPI2_MOSI_1|GPIO_SPEED_MEDIUM) /* PB15 */ -#define GPIO_SPI2_MISO (GPIO_SPI2_MISO_1|GPIO_SPEED_MEDIUM) /* PB14 */ -#define GPIO_SPI2_SCK (GPIO_SPI2_SCK_3|GPIO_SPEED_MEDIUM) /* PB13 */ -#define GPIO_SPI2_NSS (GPIO_SPI2_NSS_1|GPIO_SPEED_MEDIUM) /* PB12 */ - -/* I2C */ - -/* I2C1 */ - -#define GPIO_I2C1_SDA (GPIO_I2C1_SDA_2|GPIO_SPEED_LOW) /* PB9 */ -#define GPIO_I2C1_SCL (GPIO_I2C1_SCL_2|GPIO_SPEED_LOW) /* PB8 */ - -/* DMA channels *************************************************************/ - -/* ADC */ - -#define ADC1_DMA_CHAN DMACHAN_ADC1_1 /* DMA1_CH1 */ - -#endif /* __BOARDS_ARM_STM32F0L0G0_B_L072Z_LRWAN1_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/scripts/Make.defs b/boards/arm/stm32f0l0g0/b-l072z-lrwan1/scripts/Make.defs deleted file mode 100644 index cede66c2c8957..0000000000000 --- a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/scripts/Make.defs +++ /dev/null @@ -1,41 +0,0 @@ -############################################################################ -# boards/arm/stm32f0l0g0/b-l072z-lrwan1/scripts/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/.config -include $(TOPDIR)/tools/Config.mk -include $(TOPDIR)/arch/arm/src/armv6-m/Toolchain.defs - -LDSCRIPT = ld.script -ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) - -ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 - -CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) -CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) -CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -AFLAGS := $(CFLAGS) -D__ASSEMBLY__ - -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections -LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/scripts/ld.script b/boards/arm/stm32f0l0g0/b-l072z-lrwan1/scripts/ld.script deleted file mode 100644 index c95d535e86d18..0000000000000 --- a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/scripts/ld.script +++ /dev/null @@ -1,115 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32f0l0g0/b-l072z-lrwan1/scripts/ld.script - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* The STM32LO72CZ has 192Kb of FLASH beginning at address 0x0800:0000. - * 20Kb of SRAM and 6Kb of EEPROM - * - * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 - * where the code expects to begin execution by jumping to the entry point in - * the 0x0800:0000 address range. - */ - -MEMORY -{ - flash (rx) : ORIGIN = 0x08000000, LENGTH = 192K - sram (rwx) : ORIGIN = 0x20000000, LENGTH = 20K -} - -OUTPUT_ARCH(arm) -EXTERN(_vectors) -ENTRY(_stext) -SECTIONS -{ - .text : { - _stext = ABSOLUTE(.); - *(.vectors) - *(.text .text.*) - *(.fixup) - *(.gnu.warning) - *(.rodata .rodata.*) - *(.gnu.linkonce.t.*) - *(.glue_7) - *(.glue_7t) - *(.got) - *(.gcc_except_table) - *(.gnu.linkonce.r.*) - _etext = ABSOLUTE(.); - } > flash - - .init_section : ALIGN(4) { - _sinit = ABSOLUTE(.); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) - KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) - _einit = ABSOLUTE(.); - } > flash - - .ARM.extab : ALIGN(4) { - *(.ARM.extab*) - } > flash - - .ARM.exidx : ALIGN(4) { - __exidx_start = ABSOLUTE(.); - *(.ARM.exidx*) - __exidx_end = ABSOLUTE(.); - } > flash - - _eronly = ABSOLUTE(.); - - /* The RAM vector table (if present) should lie at the beginning of SRAM */ - - .ram_vectors : { - *(.ram_vectors) - } > sram - - .data : ALIGN(4) { - _sdata = ABSOLUTE(.); - *(.data .data.*) - *(.gnu.linkonce.d.*) - CONSTRUCTORS - . = ALIGN(4); - _edata = ABSOLUTE(.); - } > sram AT > flash - - .bss : ALIGN(4) { - _sbss = ABSOLUTE(.); - *(.bss .bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - . = ALIGN(4); - _ebss = ABSOLUTE(.); - } > sram - - /* Stabs debugging sections. */ - - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_info 0 : { *(.debug_info) } - .debug_line 0 : { *(.debug_line) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_aranges 0 : { *(.debug_aranges) } -} diff --git a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/CMakeLists.txt b/boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/CMakeLists.txt deleted file mode 100644 index 133c3298bce49..0000000000000 --- a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/CMakeLists.txt +++ /dev/null @@ -1,53 +0,0 @@ -# ############################################################################## -# boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -set(SRCS stm32_boot.c stm32_bringup.c) - -if(CONFIG_ARCH_LEDS) - list(APPEND SRCS stm32_autoleds.c) -else() - list(APPEND SRCS stm32_userleds.c) -endif() - -if(CONFIG_ARCH_BUTTONS) - list(APPEND SRCS stm32_buttons.c) -endif() - -if(CONFIG_STM32F0L0G0_SPI) - list(APPEND SRCS stm32_spi.c) -endif() - -if(CONFIG_LPWAN_SX127X) - list(APPEND SRCS stm32_sx127x.c) -endif() - -if(CONFIG_ADC) - list(APPEND SRCS stm32_adc.c) -endif() - -if(CONFIG_LCD_SSD1306) - list(APPEND SRCS stm32_lcd_ssd1306.c) -endif() - -target_sources(board PRIVATE ${SRCS}) - -set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/ld.script") diff --git a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/Make.defs b/boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/Make.defs deleted file mode 100644 index c1646dd2d1cd1..0000000000000 --- a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/Make.defs +++ /dev/null @@ -1,55 +0,0 @@ -############################################################################ -# boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/Make.defs - -CSRCS = stm32_boot.c stm32_bringup.c - -ifeq ($(CONFIG_ARCH_LEDS),y) -CSRCS += stm32_autoleds.c -else -CSRCS += stm32_userleds.c -endif - -ifeq ($(CONFIG_ARCH_BUTTONS),y) -CSRCS += stm32_buttons.c -endif - -ifeq ($(CONFIG_STM32F0L0G0_SPI),y) -CSRCS += stm32_spi.c -endif - -ifeq ($(CONFIG_LPWAN_SX127X),y) -CSRCS += stm32_sx127x.c -endif - -ifeq ($(CONFIG_ADC),y) -CSRCS += stm32_adc.c -endif - -ifeq ($(CONFIG_LCD_SSD1306),y) -CSRCS += stm32_lcd_ssd1306.c -endif - -DEPPATH += --dep-path board -VPATH += :board -CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/stm32_adc.c b/boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/stm32_adc.c deleted file mode 100644 index c28639ad262a3..0000000000000 --- a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/stm32_adc.c +++ /dev/null @@ -1,133 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/stm32_adc.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include - -#include - -#include "stm32.h" - -#if defined(CONFIG_ADC) && defined(CONFIG_STM32F0L0G0_ADC1) - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -/* The number of ADC channels in the conversion list */ - -#define ADC1_NCHANNELS 2 - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* Identifying number of each ADC channel (even if NCHANNELS is less ) */ - -static const uint8_t g_chanlist1[2] = -{ - 0, - 4, -}; - -/* Configurations of pins used by each ADC channel */ - -static const uint32_t g_pinlist1[2] = -{ - GPIO_ADC1_IN0, /* PA0/A0 */ - GPIO_ADC1_IN4 /* PA4/A2 */ -}; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_adc_setup - * - * Description: - * Initialize ADC and register the ADC driver. - * - ****************************************************************************/ - -int stm32_adc_setup(void) -{ - static bool initialized = false; - struct adc_dev_s *adc; - int ret; - int i; - - /* Check if we have already initialized */ - - if (!initialized) - { - /* Configure the pins as analog inputs for the selected channels */ - - for (i = 0; i < ADC1_NCHANNELS; i++) - { - stm32_configgpio(g_pinlist1[i]); - } - - /* Call stm32_adcinitialize() to get an instance of the ADC interface */ - - adc = stm32_adcinitialize(1, g_chanlist1, ADC1_NCHANNELS); - if (adc == NULL) - { - aerr("ERROR: Failed to get ADC interface 1\n"); - return -ENODEV; - } - - /* Register the ADC driver at "/dev/adc0" */ - - ret = adc_register("/dev/adc0", adc); - if (ret < 0) - { - aerr("ERROR: adc_register /dev/adc0 failed: %d\n", ret); - return ret; - } - - initialized = true; - } - - return OK; -} - -#endif /* CONFIG_ADC && CONFIG_STM32F0L0G0_ADC1 */ diff --git a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/stm32_autoleds.c b/boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/stm32_autoleds.c deleted file mode 100644 index c71e5764e6e57..0000000000000 --- a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/stm32_autoleds.c +++ /dev/null @@ -1,80 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/stm32_autoleds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include "stm32_gpio.h" -#include "b-l072z-lrwan1.h" - -#ifdef CONFIG_ARCH_LEDS - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_autoled_initialize - ****************************************************************************/ - -void board_autoled_initialize(void) -{ - /* Configure LED1 GPIO for output */ - - stm32_configgpio(GPIO_LED1); -} - -/**************************************************************************** - * Name: board_autoled_on - ****************************************************************************/ - -void board_autoled_on(int led) -{ - if (led == BOARD_LED1) - { - stm32_gpiowrite(GPIO_LED1, true); - } -} - -/**************************************************************************** - * Name: board_autoled_off - ****************************************************************************/ - -void board_autoled_off(int led) -{ - if (led == BOARD_LED1) - { - stm32_gpiowrite(GPIO_LED1, false); - } -} - -#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/stm32_boot.c b/boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/stm32_boot.c deleted file mode 100644 index 3df42fb83cb73..0000000000000 --- a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/stm32_boot.c +++ /dev/null @@ -1,101 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/stm32_boot.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include "b-l072z-lrwan1.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_boardinitialize - * - * Description: - * All STM32 architectures must provide the following entry point. This - * entry point is called early in the initialization -- after all memory - * has been configured and mapped but before any devices have been - * initialized. - * - ****************************************************************************/ - -void stm32_boardinitialize(void) -{ -#ifdef CONFIG_ARCH_LEDS - /* Configure on-board LEDs if LED support has been selected. */ - - board_autoled_initialize(); -#endif - -#ifdef CONFIG_STM32F0L0G0_SPI - /* Configure SPI chip selects */ - - stm32_spidev_initialize(); -#endif -} - -/**************************************************************************** - * Name: board_late_initialize - * - * Description: - * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional - * initialization call will be performed in the boot-up sequence to a - * function called board_late_initialize(). board_late_initialize() will - * be called immediately after up_initialize() is called and just before - * the initial application is started. This additional initialization - * phase may be used, for example, to initialize board-specific device - * drivers. - * - ****************************************************************************/ - -#ifdef CONFIG_BOARD_LATE_INITIALIZE -void board_late_initialize(void) -{ - /* Perform board-specific initialization */ - - stm32_bringup(); -} -#endif diff --git a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/stm32_bringup.c b/boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/stm32_bringup.c deleted file mode 100644 index 9cd2d49b180cd..0000000000000 --- a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/stm32_bringup.c +++ /dev/null @@ -1,173 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/stm32_bringup.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include - -#include "b-l072z-lrwan1.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#undef HAVE_LEDS -#undef HAVE_DAC - -#if !defined(CONFIG_ARCH_LEDS) && defined(CONFIG_USERLED_LOWER) -# define HAVE_LEDS 1 -#endif - -#if defined(CONFIG_DAC) -# define HAVE_DAC1 1 -# define HAVE_DAC2 1 -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_i2c_register - * - * Description: - * Register one I2C drivers for the I2C tool. - * - ****************************************************************************/ - -#if defined(CONFIG_I2C) && defined(CONFIG_SYSTEM_I2CTOOL) -static void stm32_i2c_register(int bus) -{ - struct i2c_master_s *i2c; - int ret; - - i2c = stm32_i2cbus_initialize(bus); - if (i2c == NULL) - { - syslog(LOG_ERR, "ERROR: Failed to get I2C%d interface\n", bus); - } - else - { - ret = i2c_register(i2c, bus); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: Failed to register I2C%d driver: %d\n", - bus, ret); - stm32_i2cbus_uninitialize(i2c); - } - } -} -#endif - -/**************************************************************************** - * Name: stm32_i2ctool - * - * Description: - * Register I2C drivers for the I2C tool. - * - ****************************************************************************/ - -#if defined(CONFIG_I2C) && defined(CONFIG_SYSTEM_I2CTOOL) -static void stm32_i2ctool(void) -{ -#ifdef CONFIG_STM32F0L0G0_I2C1 - stm32_i2c_register(1); -#endif -#ifdef CONFIG_STM32F0L0G0_I2C2 - stm32_i2c_register(2); -#endif -#ifdef CONFIG_STM32F0L0G0_I2C3 - stm32_i2c_register(3); -#endif -} -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_bringup - * - * Description: - * Perform architecture-specific initialization - * - * CONFIG_BOARD_LATE_INITIALIZE=y : - * Called from board_late_initialize(). - * - ****************************************************************************/ - -int stm32_bringup(void) -{ - int ret; - -#ifdef HAVE_LEDS - /* Register the LED driver */ - - ret = userled_lower_initialize(LED_DRIVER_PATH); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: userled_lower_initialize() failed: %d\n", ret); - return ret; - } -#endif - -#ifdef CONFIG_ADC - /* Initialize ADC and register the ADC driver. */ - - ret = stm32_adc_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_adc_setup failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_DAC - /* Initialize DAC and register the DAC driver. */ - - ret = stm32_dac_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_dac_setup failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_LPWAN_SX127X - ret = stm32_lpwaninitialize(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: Failed to initialize wireless driver: %d\n", - ret); - } -#endif /* CONFIG_LPWAN_SX127X */ - - UNUSED(ret); - return OK; -} diff --git a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/stm32_lcd_ssd1306.c b/boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/stm32_lcd_ssd1306.c deleted file mode 100644 index dcdae68aef25c..0000000000000 --- a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/stm32_lcd_ssd1306.c +++ /dev/null @@ -1,78 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/stm32_lcd_ssd1306.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include -#include -#include - -#include "stm32.h" -#include "b-l072z-lrwan1.h" - -#include "stm32_ssd1306.h" - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_lcd_initialize - ****************************************************************************/ - -int board_lcd_initialize(void) -{ - int ret; - - ret = board_ssd1306_initialize(OLED_I2C_PORT); - if (ret < 0) - { - lcderr("ERROR: Failed to initialize SSD1306\n"); - return ret; - } - - return OK; -} - -/**************************************************************************** - * Name: board_lcd_getdev - ****************************************************************************/ - -struct lcd_dev_s *board_lcd_getdev(int devno) -{ - return board_ssd1306_getdev(); -} - -/**************************************************************************** - * Name: board_lcd_uninitialize - ****************************************************************************/ - -void board_lcd_uninitialize(void) -{ - /* TO-FIX */ -} diff --git a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/stm32_spi.c b/boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/stm32_spi.c deleted file mode 100644 index 5e5040b0a86d0..0000000000000 --- a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/stm32_spi.c +++ /dev/null @@ -1,187 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/stm32_spi.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include - -#include - -#include "arm_internal.h" -#include "chip.h" -#include "stm32_gpio.h" -#include "stm32_spi.h" - -#include "b-l072z-lrwan1.h" -#include - -#ifdef CONFIG_STM32F0L0G0_SPI - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_spidev_initialize - * - * Description: - * Called to configure SPI chip select GPIO pins for the Nucleo-144 board. - * - ****************************************************************************/ - -void stm32_spidev_initialize(void) -{ - /* NOTE: Clocking for SPI1 and/or SPI2 was already provided in stm32_rcc.c. - * Configurations of SPI pins is performed in stm32_spi.c. - * Here, we only initialize chip select pins unique to the board - * architecture. - */ - -#ifdef CONFIG_STM32F0L0G0_SPI1 -# ifdef CONFIG_LPWAN_SX127X - /* Configure the SPI-based SX127X chip select GPIO */ - - spiinfo("Configure GPIO for SX127X SPI1/CS\n"); - - stm32_configgpio(GPIO_SX127X_CS); - stm32_gpiowrite(GPIO_SX127X_CS, true); -# endif -#endif -} - -/**************************************************************************** - * Name: stm32_spi1/2/select and stm32_spi1/2/status - * - * Description: - * The external functions, stm32_spi1/2select and stm32_spi1/2status - * must be provided by board-specific logic. They are implementations of - * the select and status methods of the SPI interface defined by struct - * spi_ops_s (see include/nuttx/spi/spi.h). All other methods (including - * stm32_spibus_initialize()) are provided by common STM32 logic. - * To use this common SPI logic on your board: - * - * 1. Provide logic in stm32_boardinitialize() to configure SPI chip select - * pins. - * 2. Provide stm32_spi1/2select() and stm32_spi1/2status() functions - * in your board-specific logic. These functions will perform chip - * selection and status operations using GPIOs in the way your board is - * configured. - * 3. Add a calls to stm32_spibus_initialize() in your low level - * application initialization logic - * 4. The handle returned by stm32_spibus_initialize() may then be used to - * bind the SPI driver to higher level logic (e.g., calling - * mmcsd_spislotinitialize(), for example, will bind the SPI driver to - * the SPI MMC/SD driver). - * - ****************************************************************************/ - -#ifdef CONFIG_STM32F0L0G0_SPI1 -void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, - bool selected) -{ - spiinfo("devid: %d CS: %s\n", - (int)devid, selected ? "assert" : "de-assert"); - - switch (devid) - { -#ifdef CONFIG_LPWAN_SX127X - case SPIDEV_LPWAN(0): - { - spiinfo("SX127X device %s\n", - selected ? "asserted" : "de-asserted"); - - /* Set the GPIO low to select and high to de-select */ - - stm32_gpiowrite(GPIO_SX127X_CS, !selected); - break; - } -#endif - - default: - { - break; - } - } -} - -uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) -{ - uint8_t status = 0; - - switch (devid) - { -#ifdef CONFIG_LPWAN_SX127X - case SPIDEV_LPWAN(0): - { - status |= SPI_STATUS_PRESENT; - break; - } -#endif - - default: - { - break; - } - } - - return status; -} -#endif /* CONFIG_STM32F0L0G0_SPI1 */ - -#ifdef CONFIG_STM32F0L0G0_SPI2 -void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid, - bool selected) -{ - spiinfo("devid: %d CS: %s\n", - (int)devid, selected ? "assert" : "de-assert"); -} - -uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) -{ - return 0; -} -#endif /* CONFIG_STM32F0L0G0_SPI2 */ - -#endif /* CONFIG_STM32F0L0G0_SPI */ diff --git a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/stm32_sx127x.c b/boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/stm32_sx127x.c deleted file mode 100644 index 32e9e6754068e..0000000000000 --- a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/stm32_sx127x.c +++ /dev/null @@ -1,277 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/stm32_sx127x.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -#include "stm32_gpio.h" -#include "stm32_exti.h" -#include "stm32_spi.h" - -#include "b-l072z-lrwan1.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* SX127X on SPI1 bus */ - -#define SX127X_SPI 1 - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -static void sx127x_chip_reset(void); -static int sx127x_opmode_change(int opmode); -static int sx127x_freq_select(uint32_t freq); -static int sx127x_pa_select(bool enable); -static int sx127x_irq0_attach(xcpt_t isr, void *arg); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -struct sx127x_lower_s lower = -{ - .irq0attach = sx127x_irq0_attach, - .reset = sx127x_chip_reset, - .opmode_change = sx127x_opmode_change, - .freq_select = sx127x_freq_select, - .pa_select = sx127x_pa_select, - .pa_force = false -}; - -static bool g_high_power_output = false; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: sx127x_irq0_attach - ****************************************************************************/ - -static int sx127x_irq0_attach(xcpt_t isr, void *arg) -{ - wlinfo("Attach DIO0 IRQ\n"); - - /* IRQ on rising edge */ - - stm32_gpiosetevent(GPIO_SX127X_DIO0, true, false, false, isr, arg); - return OK; -} - -/**************************************************************************** - * Name: sx127x_chip_reset - ****************************************************************************/ - -static void sx127x_chip_reset(void) -{ - wlinfo("SX127X RESET\n"); - - /* Configure reset as output */ - - stm32_configgpio(GPIO_SX127X_RESET | GPIO_OUTPUT | GPIO_SPEED_HIGH | - GPIO_OUTPUT_CLEAR); - - /* Set pin to zero */ - - stm32_gpiowrite(GPIO_SX127X_RESET, false); - - /* Wait 1 ms */ - - nxsched_usleep(1000); - - /* Configure reset as input */ - - stm32_configgpio(GPIO_SX127X_RESET | GPIO_INPUT | GPIO_FLOAT); - - /* Wait 10 ms */ - - nxsched_usleep(10000); -} - -/**************************************************************************** - * Name: sx127x_opmode_change - ****************************************************************************/ - -static int sx127x_opmode_change(int opmode) -{ - int ret = OK; - - /* Configure antena switch outputs in SLEEP mode */ - - if (opmode == SX127X_OPMODE_SLEEP) - { - stm32_gpiowrite(GPIO_SX127X_CRF1, false); - stm32_gpiowrite(GPIO_SX127X_CRF2, false); - stm32_gpiowrite(GPIO_SX127X_CRF3, false); - - stm32_configgpio(GPIO_SX127X_CRF1 | GPIO_ANALOG); - stm32_configgpio(GPIO_SX127X_CRF2 | GPIO_ANALOG); - stm32_configgpio(GPIO_SX127X_CRF3 | GPIO_ANALOG); - - goto errout; - } - - /* Configure antena switch outputs */ - - stm32_configgpio(GPIO_SX127X_CRF1 | GPIO_OUTPUT | GPIO_OUTPUT_CLEAR); - stm32_configgpio(GPIO_SX127X_CRF2 | GPIO_OUTPUT | GPIO_OUTPUT_CLEAR); - stm32_configgpio(GPIO_SX127X_CRF3 | GPIO_OUTPUT | GPIO_OUTPUT_CLEAR); - - stm32_gpiowrite(GPIO_SX127X_CRF1, false); - stm32_gpiowrite(GPIO_SX127X_CRF2, false); - stm32_gpiowrite(GPIO_SX127X_CRF3, false); - - switch (opmode) - { - case SX127X_OPMODE_STANDBY: - case SX127X_OPMODE_FSRX: - case SX127X_OPMODE_FSTX: - { - break; - } - - case SX127X_OPMODE_TX: - { - /* Set TX RFO or TX BOOST */ - - if (g_high_power_output == true) - { - wlinfo("SET CRF3\n"); - stm32_gpiowrite(GPIO_SX127X_CRF3, true); - } - else - { - wlinfo("SET CRF2\n"); - stm32_gpiowrite(GPIO_SX127X_CRF2, true); - } - - break; - } - - case SX127X_OPMODE_RX: - case SX127X_OPMODE_RXSINGLE: - case SX127X_OPMODE_CAD: - { - /* Set antena RX */ - - wlinfo("SET CRF1\n"); - stm32_gpiowrite(GPIO_SX127X_CRF1, true); - - break; - } - - default: - { - wlerr("ERROR: invalid mode %d\n", opmode); - ret = -EINVAL; - break; - } - } - -errout: - return ret; -} - -/**************************************************************************** - * Name: sx127x_freq_select - ****************************************************************************/ - -static int sx127x_freq_select(uint32_t freq) -{ - int ret = OK; - - /* Only HF supported (BAND3 - 860-930 MHz) */ - - if (freq < SX127X_HFBAND_THR) - { - ret = -EINVAL; - wlerr("LF band not supported\n"); - } - - return ret; -} - -/**************************************************************************** - * Name: sx127x_pa_select - ****************************************************************************/ - -static int sx127x_pa_select(bool enable) -{ - g_high_power_output = enable; - return OK; -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -int stm32_lpwaninitialize(void) -{ - struct spi_dev_s *spidev; - int ret = OK; - - wlinfo("Register the sx127x module\n"); - - /* Setup DIO0 */ - - stm32_configgpio(GPIO_SX127X_DIO0); - - /* Init SPI bus */ - - spidev = stm32_spibus_initialize(SX127X_SPI); - if (!spidev) - { - wlerr("ERROR: Failed to initialize SPI %d bus\n", SX127X_SPI); - ret = -ENODEV; - goto errout; - } - - /* Initialize SX127X */ - - ret = sx127x_register(spidev, &lower); - if (ret < 0) - { - wlerr("ERROR: Failed to register sx127x\n"); - goto errout; - } - -errout: - return ret; -} diff --git a/boards/arm/stm32f0l0g0/common/CMakeLists.txt b/boards/arm/stm32f0l0g0/common/CMakeLists.txt deleted file mode 100644 index 4741419517f6b..0000000000000 --- a/boards/arm/stm32f0l0g0/common/CMakeLists.txt +++ /dev/null @@ -1,24 +0,0 @@ -# ############################################################################## -# boards/arm/stm32f0l0g0/common/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) -target_include_directories(board PRIVATE include) diff --git a/boards/arm/stm32f0l0g0/common/Kconfig b/boards/arm/stm32f0l0g0/common/Kconfig deleted file mode 100644 index 18c7905aed7cf..0000000000000 --- a/boards/arm/stm32f0l0g0/common/Kconfig +++ /dev/null @@ -1,5 +0,0 @@ -# -# For a description of the syntax of this configuration file, -# see the file kconfig-language.txt in the NuttX tools repository. -# - diff --git a/boards/arm/stm32f0l0g0/common/Makefile b/boards/arm/stm32f0l0g0/common/Makefile deleted file mode 100644 index 7318baae08c34..0000000000000 --- a/boards/arm/stm32f0l0g0/common/Makefile +++ /dev/null @@ -1,35 +0,0 @@ -############################################################################# -# boards/arm/stm32f0l0g0/common/Makefile -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################# - -include $(TOPDIR)/Make.defs - -include board/Make.defs -include src/Make.defs - -DEPPATH += --dep-path board -DEPPATH += --dep-path src - -include $(TOPDIR)/boards/Board.mk - -ARCHSRCDIR = $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src -BOARDDIR = $(ARCHSRCDIR)$(DELIM)board -CFLAGS += ${INCDIR_PREFIX}$(BOARDDIR)$(DELIM)include diff --git a/boards/arm/stm32f0l0g0/common/include/board_qencoder.h b/boards/arm/stm32f0l0g0/common/include/board_qencoder.h deleted file mode 100644 index b16fbb020d089..0000000000000 --- a/boards/arm/stm32f0l0g0/common/include/board_qencoder.h +++ /dev/null @@ -1,63 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32f0l0g0/common/include/board_qencoder.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __BOARDS_ARM_STM32F0L0G0_COMMON_INCLUDE_BOARD_QENCODER_H -#define __BOARDS_ARM_STM32F0L0G0_COMMON_INCLUDE_BOARD_QENCODER_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -#ifdef __cplusplus -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: board_qencoder_initialize - * - * Description: - * Initialize the quadrature encoder driver for the given timer - * - ****************************************************************************/ - -int board_qencoder_initialize(int devno, int timerno); - -#undef EXTERN -#ifdef __cplusplus -} -#endif - -#endif /* __BOARDS_ARM_STM32F0L0G0_COMMON_INCLUDE_BOARD_QENCODER_H */ diff --git a/boards/arm/stm32f0l0g0/common/include/stm32_ssd1306.h b/boards/arm/stm32f0l0g0/common/include/stm32_ssd1306.h deleted file mode 100644 index 3831d23592bf2..0000000000000 --- a/boards/arm/stm32f0l0g0/common/include/stm32_ssd1306.h +++ /dev/null @@ -1,82 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32f0l0g0/common/include/stm32_ssd1306.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __BOARDS_ARM_STM32F0L0G0_COMMON_INCLUDE_STM32_SSD1306_H -#define __BOARDS_ARM_STM32F0L0G0_COMMON_INCLUDE_STM32_SSD1306_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -#ifdef __cplusplus -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: board_ssd1306_initialize - * - * Description: - * Initialize and register the device - * - * Input Parameters: - * busno - The I2C or SPI bus number - * - * Returned Value: - * Zero (OK) on success; a negated errno value on failure. - * - ****************************************************************************/ - -int board_ssd1306_initialize(int busno); - -/**************************************************************************** - * Name: board_ssd1306_getdev - * - * Description: - * Get the SSD1306 device driver instance - * - * Returned Value: - * Pointer to the instance - * - ****************************************************************************/ - -struct lcd_dev_s *board_ssd1306_getdev(void); - -#undef EXTERN -#ifdef __cplusplus -} -#endif - -#endif /* __BOARDS_ARM_STM32F0L0G0_COMMON_INCLUDE_STM32_SSD1306_H */ diff --git a/boards/arm/stm32f0l0g0/common/src/CMakeLists.txt b/boards/arm/stm32f0l0g0/common/src/CMakeLists.txt deleted file mode 100644 index 2b7dc2f3527bc..0000000000000 --- a/boards/arm/stm32f0l0g0/common/src/CMakeLists.txt +++ /dev/null @@ -1,38 +0,0 @@ -# ############################################################################## -# boards/arm/stm32f0l0g0/common/src/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -if(CONFIG_ARCH_BOARD_COMMON) - - if(CONFIG_LCD_SSD1306) - list(APPEND SRCS stm32_ssd1306.c) - endif() - - if(CONFIG_SENSORS_QENCODER) - list(APPEND SRCS board_qencoder.c) - endif() - - if(CONFIG_PWM) - list(APPEND SRCS board_pwm.c) - endif() - -endif() -target_sources(board PRIVATE ${SRCS}) diff --git a/boards/arm/stm32f0l0g0/common/src/Make.defs b/boards/arm/stm32f0l0g0/common/src/Make.defs deleted file mode 100644 index 972383a629149..0000000000000 --- a/boards/arm/stm32f0l0g0/common/src/Make.defs +++ /dev/null @@ -1,41 +0,0 @@ -############################################################################# -# boards/arm/stm32f0l0g0/common/src/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################# - -ifeq ($(CONFIG_ARCH_BOARD_COMMON),y) - -ifeq ($(CONFIG_LCD_SSD1306),y) - CSRCS += stm32_ssd1306.c -endif - -ifeq ($(CONFIG_SENSORS_QENCODER),y) - CSRCS += board_qencoder.c -endif - -ifeq ($(CONFIG_PWM),y) - CSRCS += board_pwm.c -endif - -DEPPATH += --dep-path src -VPATH += :src -CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)src - -endif diff --git a/boards/arm/stm32f0l0g0/common/src/stm32_ssd1306.c b/boards/arm/stm32f0l0g0/common/src/stm32_ssd1306.c deleted file mode 100644 index cf14f06f94338..0000000000000 --- a/boards/arm/stm32f0l0g0/common/src/stm32_ssd1306.c +++ /dev/null @@ -1,163 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32f0l0g0/common/src/stm32_ssd1306.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include -#include -#include -#include -#include - -#include "stm32_i2c.h" -#include "stm32_spi.h" - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -static struct lcd_dev_s *g_lcddev; - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_ssd1306_initialize - * - * Description: - * Initialize and register the device. I2C version. - * - * Input Parameters: - * busno - The I2C bus number - * - * Returned Value: - * Zero (OK) on success; a negated errno value on failure. - * - ****************************************************************************/ -#ifdef CONFIG_LCD_SSD1306_I2C -int board_ssd1306_initialize(int busno) -{ - struct i2c_master_s *i2c; - const int devno = 0; - - /* Initialize I2C */ - - i2c = stm32_i2cbus_initialize(busno); - if (!i2c) - { - lcderr("ERROR: Failed to initialize I2C port %d\n", busno); - return -ENODEV; - } - - /* Bind the I2C port to the OLED */ - - g_lcddev = ssd1306_initialize(i2c, NULL, devno); - if (!g_lcddev) - { - lcderr("ERROR: Failed to bind I2C port %d to OLED %d\n", busno, devno); - return -ENODEV; - } - else - { - lcdinfo("Bound I2C port %d to OLED %d\n", busno, devno); - - /* And turn the OLED on */ - - g_lcddev->setpower(g_lcddev, CONFIG_LCD_MAXPOWER); - return OK; - } -} -#endif - -/**************************************************************************** - * Name: board_ssd1306_initialize - * - * Description: - * Initialize and register the device. SPI version. - * - * Input Parameters: - * busno - The SPI bus number - * - * Returned Value: - * Zero (OK) on success; a negated errno value on failure. - * - ****************************************************************************/ -#ifdef CONFIG_LCD_SSD1306_SPI -int board_ssd1306_initialize(int busno) -{ - struct spi_dev_s *spi; - const int devno = 0; - - /* Initialize SPI */ - - spi = stm32_spibus_initialize(busno); - if (!spi) - { - lcderr("ERROR: Failed to initialize SPI port %d\n", busno); - return -ENODEV; - } - - /* Bind the SPI port to the OLED */ - - g_lcddev = ssd1306_initialize(spi, NULL, devno); - if (!g_lcddev) - { - lcderr("ERROR: Failed to bind SPI port %d to OLED %d\n", busno, devno); - return -ENODEV; - } - else - { - lcdinfo("Bound SPI port %d to OLED %d\n", busno, devno); - - /* And turn the OLED on */ - - g_lcddev->setpower(g_lcddev, CONFIG_LCD_MAXPOWER); - - ssd1306_fill(g_lcddev, 0xff); - - return OK; - } -} -#endif - -/**************************************************************************** - * Name: board_ssd1306_getdev - * - * Description: - * Get the SSD1306 device driver instance - * - * Returned Value: - * Pointer to the instance - * - ****************************************************************************/ - -struct lcd_dev_s *board_ssd1306_getdev(void) -{ - return g_lcddev; -} diff --git a/boards/arm/stm32f0l0g0/nucleo-c071rb/CMakeLists.txt b/boards/arm/stm32f0l0g0/nucleo-c071rb/CMakeLists.txt deleted file mode 100644 index 93b039d1da70c..0000000000000 --- a/boards/arm/stm32f0l0g0/nucleo-c071rb/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32f0l0g0/nucleo-c071rb/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32f0l0g0/nucleo-c071rb/configs/adcscope/defconfig b/boards/arm/stm32f0l0g0/nucleo-c071rb/configs/adcscope/defconfig deleted file mode 100644 index c2ff70981676b..0000000000000 --- a/boards/arm/stm32f0l0g0/nucleo-c071rb/configs/adcscope/defconfig +++ /dev/null @@ -1,62 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_DEV_CONSOLE is not set -# CONFIG_SYSTEM_DD is not set -CONFIG_ADC=y -CONFIG_ANALOG=y -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="nucleo-c071rb" -CONFIG_ARCH_BOARD_NUCLEO_C071RB=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32f0l0g0" -CONFIG_ARCH_CHIP_STM32C071RB=y -CONFIG_ARCH_CHIP_STM32C071XX=y -CONFIG_ARCH_CHIP_STM32C0=y -CONFIG_ARCH_IRQBUTTONS=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARDCTL=y -CONFIG_BOARDCTL_MKRD=y -CONFIG_BOARD_LOOPSPERMSEC=3997 -CONFIG_BUILTIN=y -CONFIG_DEBUG_ASSERTIONS=y -CONFIG_DEBUG_ASSERTIONS_EXPRESSION=y -CONFIG_DEBUG_CUSTOMOPT=y -CONFIG_DEBUG_FEATURES=y -CONFIG_DEBUG_OPTLEVEL="-O1" -CONFIG_DEBUG_SYMBOLS=y -CONFIG_INIT_ENTRYPOINT="adcscope_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_LOGGING_NXSCOPE=y -CONFIG_LOGGING_NXSCOPE_INTF_SERIAL=y -CONFIG_NDEBUG=y -CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 -CONFIG_NUNGET_CHARS=0 -CONFIG_PTHREAD_MUTEX_UNSAFE=y -CONFIG_RAM_SIZE=24576 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=19 -CONFIG_START_MONTH=5 -CONFIG_START_YEAR=2013 -CONFIG_STM32F0L0G0_ADC1=y -CONFIG_STM32F0L0G0_ADC1_DMA=y -CONFIG_STM32F0L0G0_ADC1_DMA_CFG=1 -CONFIG_STM32F0L0G0_ADC1_SAMPLE_FREQUENCY=10 -CONFIG_STM32F0L0G0_ADC1_TIMTRIG=3 -CONFIG_STM32F0L0G0_ADC_MAX_SAMPLES=6 -CONFIG_STM32F0L0G0_DMA1=y -CONFIG_STM32F0L0G0_TIM1=y -CONFIG_STM32F0L0G0_TIM1_ADC=y -CONFIG_STM32F0L0G0_USART2=y -CONFIG_SYSTEM_ADCSCOPE=y -CONFIG_SYSTEM_ADCSCOPE_FETCH_INTERVAL=0 -CONFIG_SYSTEM_ADCSCOPE_SERIAL_PATH="/dev/ttyS0" -CONFIG_TASK_NAME_SIZE=32 diff --git a/boards/arm/stm32f0l0g0/nucleo-c071rb/configs/jumbo/defconfig b/boards/arm/stm32f0l0g0/nucleo-c071rb/configs/jumbo/defconfig deleted file mode 100644 index effe787fe7515..0000000000000 --- a/boards/arm/stm32f0l0g0/nucleo-c071rb/configs/jumbo/defconfig +++ /dev/null @@ -1,93 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_NSH_ARGCAT is not set -CONFIG_ADC=y -CONFIG_ANALOG=y -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="nucleo-c071rb" -CONFIG_ARCH_BOARD_COMMON=y -CONFIG_ARCH_BOARD_NUCLEO_C071RB=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32f0l0g0" -CONFIG_ARCH_CHIP_STM32C071RB=y -CONFIG_ARCH_CHIP_STM32C071XX=y -CONFIG_ARCH_CHIP_STM32C0=y -CONFIG_ARCH_IRQBUTTONS=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARDCTL=y -CONFIG_BOARD_LOOPSPERMSEC=3997 -CONFIG_BUILTIN=y -CONFIG_DEBUG_FEATURES=y -CONFIG_DEBUG_FULLOPT=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_DEV_GPIO=y -CONFIG_DISABLE_ENVIRON=y -CONFIG_DISABLE_MOUNTPOINT=y -CONFIG_DISABLE_MQUEUE=y -CONFIG_DISABLE_POSIX_TIMERS=y -CONFIG_DISABLE_PSEUDOFS_OPERATIONS=y -CONFIG_EXAMPLES_ADC=y -CONFIG_EXAMPLES_ADC_GROUPSIZE=2 -CONFIG_EXAMPLES_ADC_SWTRIG=y -CONFIG_EXAMPLES_BUTTONS=y -CONFIG_EXAMPLES_HELLO=y -CONFIG_EXAMPLES_NXMBSERVER=y -CONFIG_EXAMPLES_PWM=y -CONFIG_EXAMPLES_PWM_DEVPATH="/dev/pwm13" -CONFIG_EXAMPLES_QENCODER=y -CONFIG_EXAMPLES_WATCHDOG=y -CONFIG_INDUSTRY_NXMODBUS=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INIT_STACKSIZE=1536 -CONFIG_INPUT=y -CONFIG_INPUT_BUTTONS=y -CONFIG_INPUT_BUTTONS_DEBOUNCE_DELAY=10 -CONFIG_INPUT_BUTTONS_LOWER=y -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=64 -CONFIG_NSH_READLINE=y -CONFIG_NUNGET_CHARS=0 -CONFIG_NXMODBUS_CLIENT=y -CONFIG_POSIX_SPAWN_DEFAULT_STACKSIZE=1536 -CONFIG_PTHREAD_MUTEX_UNSAFE=y -CONFIG_PTHREAD_STACK_DEFAULT=1536 -CONFIG_PWM=y -CONFIG_RAM_SIZE=24576 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_SENSORS=y -CONFIG_SENSORS_QENCODER=y -CONFIG_SERIAL_TERMIOS=y -CONFIG_START_DAY=19 -CONFIG_START_MONTH=5 -CONFIG_START_YEAR=2013 -CONFIG_STDIO_DISABLE_BUFFERING=y -CONFIG_STM32F0L0G0_ADC1=y -CONFIG_STM32F0L0G0_ADC_MAX_SAMPLES=6 -CONFIG_STM32F0L0G0_DMA1=y -CONFIG_STM32F0L0G0_IWDG=y -CONFIG_STM32F0L0G0_PWM_MULTICHAN=y -CONFIG_STM32F0L0G0_TIM14=y -CONFIG_STM32F0L0G0_TIM14_CH1OUT=y -CONFIG_STM32F0L0G0_TIM14_CHANNEL1=y -CONFIG_STM32F0L0G0_TIM14_PWM=y -CONFIG_STM32F0L0G0_TIM3=y -CONFIG_STM32F0L0G0_TIM3_QE=y -CONFIG_STM32F0L0G0_USART1=y -CONFIG_STM32F0L0G0_USART2=y -CONFIG_STM32F0L0G0_WWDG=y -CONFIG_SYSTEM_NSH=y -CONFIG_SYSTEM_NXMBCLIENT=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART1_RS485=y -CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f0l0g0/nucleo-c071rb/configs/nsh/defconfig b/boards/arm/stm32f0l0g0/nucleo-c071rb/configs/nsh/defconfig deleted file mode 100644 index af2948dd839e9..0000000000000 --- a/boards/arm/stm32f0l0g0/nucleo-c071rb/configs/nsh/defconfig +++ /dev/null @@ -1,44 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="nucleo-c071rb" -CONFIG_ARCH_BOARD_NUCLEO_C071RB=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32f0l0g0" -CONFIG_ARCH_CHIP_STM32C071RB=y -CONFIG_ARCH_CHIP_STM32C071XX=y -CONFIG_ARCH_CHIP_STM32C0=y -CONFIG_ARCH_IRQBUTTONS=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=3997 -CONFIG_DEBUG_FULLOPT=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INIT_STACKSIZE=1536 -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 -CONFIG_NSH_FILEIOSIZE=64 -CONFIG_NSH_READLINE=y -CONFIG_NUNGET_CHARS=0 -CONFIG_POSIX_SPAWN_DEFAULT_STACKSIZE=1536 -CONFIG_PTHREAD_MUTEX_UNSAFE=y -CONFIG_PTHREAD_STACK_DEFAULT=1536 -CONFIG_RAM_SIZE=24576 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=19 -CONFIG_START_MONTH=5 -CONFIG_START_YEAR=2013 -CONFIG_STDIO_DISABLE_BUFFERING=y -CONFIG_STM32F0L0G0_USART2=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f0l0g0/nucleo-c071rb/include/board.h b/boards/arm/stm32f0l0g0/nucleo-c071rb/include/board.h deleted file mode 100644 index 5ca9fdd6cfa3c..0000000000000 --- a/boards/arm/stm32f0l0g0/nucleo-c071rb/include/board.h +++ /dev/null @@ -1,186 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-c071rb/include/board.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __BOARDS_ARM_STM32F0L0G0_NUCLEO_C071RB_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32F0L0G0_NUCLEO_C071RB_INCLUDE_BOARD_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#ifndef __ASSEMBLY__ -# include -#endif - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Clocking *****************************************************************/ - -/* HSI - Internal 48 MHz RC Oscillator - * LSI - 32 KHz RC - * HSE - 8 MHz from MCO output of ST-LINK (disabled by default) - * LSE - 32.768 kHz - */ - -#define STM32_BOARD_XTAL 8000000ul /* 8MHz */ - -#define STM32_HSI_FREQUENCY 48000000ul /* 48MHz */ -#define STM32_LSI_FREQUENCY 32000 /* Between 30kHz and 60kHz */ -#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL -#define STM32_LSE_FREQUENCY 32768 /* X2 on board */ - -/* Configure HSI48 clock division factor (48 MHz) */ - -#define STM32_RCC_HSIDIV RCC_CR_HSIDIV_HSI - -/* Use the HSI as SYSCLK source (48 MHz) */ - -#define STM32_SYSCLK_SW RCC_CFGR_SW_HSI -#define STM32_SYSCLK_SWS RCC_CFGR_SWS_HSI -#define STM32_SYSCLK_FREQUENCY (STM32_HSI_FREQUENCY) - -/* AHB clock (HCLK) is SYSCLK (48 MHz) */ - -#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK -#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY - -/* APB1 clock (PCLK) is HCLK (48 MHz) */ - -#define STM32_RCC_CFGR_PPRE RCC_CFGR_PPRE_HCLK -#define STM32_PCLK1_FREQUENCY STM32_HCLK_FREQUENCY - -/* All timers on PCLK x1 (48 MHz) */ - -#define STM32_APB2_TIM1_CLKIN STM32_PCLK1_FREQUENCY -#define STM32_APB1_TIM2_CLKIN STM32_PCLK1_FREQUENCY -#define STM32_APB1_TIM3_CLKIN STM32_PCLK1_FREQUENCY -#define STM32_APB2_TIM14_CLKIN STM32_PCLK1_FREQUENCY -#define STM32_APB2_TIM15_CLKIN STM32_PCLK1_FREQUENCY -#define STM32_APB2_TIM16_CLKIN STM32_PCLK1_FREQUENCY -#define STM32_APB2_TIM17_CLKIN STM32_PCLK1_FREQUENCY - -/* LED definitions **********************************************************/ - -/* LED index values for use with board_userled() */ - -#define BOARD_LED1 0 /* User LD1 */ -#define BOARD_LED2 1 /* User LD2 */ -#define BOARD_NLEDS 2 - -/* LED bits for use with board_userled_all() */ - -#define BOARD_LED1_BIT (1 << BOARD_LED1) -#define BOARD_LED2_BIT (1 << BOARD_LED2) - -/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the LED on the - * board. The following definitions describe how NuttX controls - * the LED: - * - * SYMBOL Meaning LED1 state - * ------------------ ----------------------- ---------- - * LED_STARTED NuttX has been started OFF - * LED_HEAPALLOCATE Heap has been allocated OFF - * LED_IRQSENABLED Interrupts enabled OFF - * LED_STACKCREATED Idle stack created ON - * LED_INIRQ In an interrupt No change - * LED_SIGNAL In a signal handler No change - * LED_ASSERTION An assertion failed No change - * LED_PANIC The system has crashed Blinking - * LED_IDLE STM32 is in sleep mode Not used - */ - -#define LED_STARTED 0 -#define LED_HEAPALLOCATE 0 -#define LED_IRQSENABLED 0 -#define LED_STACKCREATED 1 -#define LED_INIRQ 2 -#define LED_SIGNAL 2 -#define LED_ASSERTION 2 -#define LED_PANIC 1 - -/* Button definitions *******************************************************/ - -/* Nucleo C071RB board supports two buttons; only one button is controllable - * by software: - * - * B1 USER: user button connected to STM32 I/O PC13. - * B2 RESET: push button connected to NRST; used to RESET the MCU. - */ - -#define BUTTON_USER 0 /* User B1 */ -#define NUM_BUTTONS 1 - -#define BUTTON_USER_BIT (1 << BUTTON_USER) - -/* Alternate function pin selections ****************************************/ - -/* USART */ - -/* USART1 at arduino D0/D1: - * USART1_RX - PB7 - * USART1_TX - PB6 - */ - -#define GPIO_USART1_RX (GPIO_USART1_RX_2|GPIO_SPEED_HIGH) /* PB7 */ -#define GPIO_USART1_TX (GPIO_USART1_TX_2|GPIO_SPEED_HIGH) /* PB6 */ - -/* USART1 RS485_DIR - PA8 (arduino D7) - * (compatible with RS485 Waveshare shield) - */ - -#define GPIO_USART1_RS485_DIR (GPIO_OUTPUT | GPIO_PUSHPULL | \ - GPIO_SPEED_HIGH | GPIO_OUTPUT_CLEAR | \ - GPIO_PORTA | GPIO_PIN8) - -/* By default the USART2 is connected to STLINK Virtual COM Port: - * USART2_RX - PA3 - * USART2_TX - PA2 - */ - -#define GPIO_USART2_RX (GPIO_USART2_RX_1|GPIO_SPEED_HIGH) /* PA3 */ -#define GPIO_USART2_TX (GPIO_USART2_TX_1|GPIO_SPEED_HIGH) /* PA2 */ - -/* Qencoder on TIM3: - * TIM3_CH1IN - PB4 (D5) - * TIM3_CH2IN - PC7 (D3) - */ - -#define GPIO_TIM3_CH1IN (GPIO_TIM3_CH1IN_2|GPIO_SPEED_HIGH) -#define GPIO_TIM3_CH2IN (GPIO_TIM3_CH2IN_6|GPIO_SPEED_HIGH) - -/* PWM on TIM14: - * TIM14_CH1 - PA7 (D11) - */ - -#define GPIO_TIM14_CH1OUT (GPIO_TIM14_CH1OUT_2|GPIO_SPEED_HIGH) - -/* DMA channels *************************************************************/ - -/* ADC */ - -#define ADC1_DMA_CHAN DMAMAP_DMA1_ADC1 /* DMA1 */ - -#endif /* __BOARDS_ARM_STM32F0L0G0_NUCLEO_C071RB_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32f0l0g0/nucleo-c071rb/scripts/Make.defs b/boards/arm/stm32f0l0g0/nucleo-c071rb/scripts/Make.defs deleted file mode 100644 index 1e325f2a9bfac..0000000000000 --- a/boards/arm/stm32f0l0g0/nucleo-c071rb/scripts/Make.defs +++ /dev/null @@ -1,41 +0,0 @@ -############################################################################ -# boards/arm/stm32f0l0g0/nucleo-c071rb/scripts/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/.config -include $(TOPDIR)/tools/Config.mk -include $(TOPDIR)/arch/arm/src/armv6-m/Toolchain.defs - -LDSCRIPT = flash.ld -ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) - -ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 - -CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) -CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) -CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -AFLAGS := $(CFLAGS) -D__ASSEMBLY__ - -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections -LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32f0l0g0/nucleo-c071rb/scripts/flash.ld b/boards/arm/stm32f0l0g0/nucleo-c071rb/scripts/flash.ld deleted file mode 100644 index a522204b0c1de..0000000000000 --- a/boards/arm/stm32f0l0g0/nucleo-c071rb/scripts/flash.ld +++ /dev/null @@ -1,111 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-c071rb/scripts/flash.ld - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* The STM32C071RBT6 has 128KB of FLASH beginning at address 0x0800:0000 and - * 24Kb of SRAM at address 0x20000000. - * - * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 - * where the code expects to begin execution by jumping to the entry point in - * the 0x0800:0000 address range. - */ - -MEMORY -{ - flash (rx) : ORIGIN = 0x08000000, LENGTH = 128K - sram (rwx) : ORIGIN = 0x20000000, LENGTH = 24K -} - -OUTPUT_ARCH(arm) -EXTERN(_vectors) -ENTRY(_stext) - -SECTIONS -{ - .text : - { - _stext = ABSOLUTE(.); - *(.vectors) - *(.text .text.*) - *(.fixup) - *(.gnu.warning) - *(.rodata .rodata.*) - *(.gnu.linkonce.t.*) - *(.glue_7) - *(.glue_7t) - *(.got) - *(.gcc_except_table) - *(.gnu.linkonce.r.*) - _etext = ABSOLUTE(.); - } > flash - - .init_section : ALIGN(4) { - _sinit = ABSOLUTE(.); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) - KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) - _einit = ABSOLUTE(.); - } > flash - - .ARM.extab ALIGN(4): { - *(.ARM.extab*) - } > flash - - .ARM.exidx : ALIGN(4) { - __exidx_start = ABSOLUTE(.); - *(.ARM.exidx*) - __exidx_end = ABSOLUTE(.); - } > flash - - _eronly = ABSOLUTE(.); - - .data : ALIGN(4) { - _sdata = ABSOLUTE(.); - *(.data .data.*) - *(.gnu.linkonce.d.*) - CONSTRUCTORS - . = ALIGN(4); - _edata = ABSOLUTE(.); - } > sram AT > flash - - .bss : ALIGN(4) { - _sbss = ABSOLUTE(.); - *(.bss .bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - . = ALIGN(8); - _ebss = ABSOLUTE(.); - } > sram - - /* Stabs debugging sections. */ - - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_info 0 : { *(.debug_info) } - .debug_line 0 : { *(.debug_line) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_aranges 0 : { *(.debug_aranges) } -} diff --git a/boards/arm/stm32f0l0g0/nucleo-c071rb/src/CMakeLists.txt b/boards/arm/stm32f0l0g0/nucleo-c071rb/src/CMakeLists.txt deleted file mode 100644 index 2d327d8c10698..0000000000000 --- a/boards/arm/stm32f0l0g0/nucleo-c071rb/src/CMakeLists.txt +++ /dev/null @@ -1,41 +0,0 @@ -# ############################################################################## -# boards/arm/stm32f0l0g0/nucleo-c071rb/src/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -set(SRCS stm32_boot.c stm32_bringup.c) - -if(CONFIG_ARCH_LEDS) - list(APPEND SRCS stm32_autoleds.c) -else() - list(APPEND SRCS stm32_userleds.c) -endif() - -if(CONFIG_ARCH_BUTTONS) - list(APPEND SRCS stm32_buttons.c) -endif() - -if(CONFIG_ADC) - list(APPEND SRCS stm32_adc.c) -endif() - -target_sources(board PRIVATE ${SRCS}) - -set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/flash.ld") diff --git a/boards/arm/stm32f0l0g0/nucleo-c071rb/src/Make.defs b/boards/arm/stm32f0l0g0/nucleo-c071rb/src/Make.defs deleted file mode 100644 index a89ade512165b..0000000000000 --- a/boards/arm/stm32f0l0g0/nucleo-c071rb/src/Make.defs +++ /dev/null @@ -1,43 +0,0 @@ -############################################################################ -# boards/arm/stm32f0l0g0/nucleo-c071rb/src/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/Make.defs - -CSRCS = stm32_boot.c stm32_bringup.c - -ifeq ($(CONFIG_ARCH_LEDS),y) -CSRCS += stm32_autoleds.c -else -CSRCS += stm32_userleds.c -endif - -ifeq ($(CONFIG_ARCH_BUTTONS),y) -CSRCS += stm32_buttons.c -endif - -ifeq ($(CONFIG_ADC),y) -CSRCS += stm32_adc.c -endif - -DEPPATH += --dep-path board -VPATH += :board -CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32f0l0g0/nucleo-c071rb/src/stm32_adc.c b/boards/arm/stm32f0l0g0/nucleo-c071rb/src/stm32_adc.c deleted file mode 100644 index 25a62741c1c9b..0000000000000 --- a/boards/arm/stm32f0l0g0/nucleo-c071rb/src/stm32_adc.c +++ /dev/null @@ -1,137 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-c071rb/src/stm32_adc.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include - -#include - -#include "stm32.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -/* The number of ADC channels in the conversion list */ - -#define ADC1_NCHANNELS 6 - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* Identifying number of each ADC channel (even if NCHANNELS is less ) */ - -static const uint8_t g_chanlist1[ADC1_NCHANNELS] = -{ - 0, - 1, - 4, - 17, - 11, - 12, -}; - -/* Configurations of pins used by each ADC channel */ - -static const uint32_t g_pinlist1[ADC1_NCHANNELS] = -{ - GPIO_ADC1_IN0_0, /* PA0/A0 */ - GPIO_ADC1_IN1_0, /* PA1/A1 */ - GPIO_ADC1_IN4_0, /* PA4/A2 */ - GPIO_ADC1_IN17_0, /* PB0/A3 */ - GPIO_ADC1_IN11_0, /* PC4/A4 */ - GPIO_ADC1_IN12_0, /* PC5/A5 */ -}; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_adc_setup - * - * Description: - * Initialize ADC and register the ADC driver. - * - ****************************************************************************/ - -int stm32_adc_setup(void) -{ - static bool initialized = false; - struct adc_dev_s *adc; - int ret; - int i; - - /* Check if we have already initialized */ - - if (!initialized) - { - /* Configure the pins as analog inputs for the selected channels */ - - for (i = 0; i < ADC1_NCHANNELS; i++) - { - stm32_configgpio(g_pinlist1[i]); - } - - /* Call stm32_adcinitialize() to get an instance of the ADC interface */ - - adc = stm32_adcinitialize(1, g_chanlist1, ADC1_NCHANNELS); - if (adc == NULL) - { - aerr("ERROR: Failed to get ADC interface 1\n"); - return -ENODEV; - } - - /* Register the ADC driver at "/dev/adc0" */ - - ret = adc_register("/dev/adc0", adc); - if (ret < 0) - { - aerr("ERROR: adc_register /dev/adc0 failed: %d\n", ret); - return ret; - } - - initialized = true; - } - - return OK; -} diff --git a/boards/arm/stm32f0l0g0/nucleo-c071rb/src/stm32_autoleds.c b/boards/arm/stm32f0l0g0/nucleo-c071rb/src/stm32_autoleds.c deleted file mode 100644 index 86ed1091a04a8..0000000000000 --- a/boards/arm/stm32f0l0g0/nucleo-c071rb/src/stm32_autoleds.c +++ /dev/null @@ -1,93 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-c071rb/src/stm32_autoleds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32_gpio.h" -#include "nucleo-c071rb.h" - -#ifdef CONFIG_ARCH_LEDS - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_autoled_initialize - ****************************************************************************/ - -void board_autoled_initialize(void) -{ - /* Configure LD1 and LD2 GPIO for output */ - - stm32_configgpio(GPIO_LD1); - stm32_configgpio(GPIO_LD2); -} - -/**************************************************************************** - * Name: board_autoled_on - ****************************************************************************/ - -void board_autoled_on(int led) -{ - if (led == BOARD_LED1) - { - stm32_gpiowrite(GPIO_LD1, true); - } - - if (led == BOARD_LED2) - { - stm32_gpiowrite(GPIO_LD2, false); - } -} - -/**************************************************************************** - * Name: board_autoled_off - ****************************************************************************/ - -void board_autoled_off(int led) -{ - if (led == BOARD_LED1) - { - stm32_gpiowrite(GPIO_LD1, false); - } - - if (led == BOARD_LED2) - { - stm32_gpiowrite(GPIO_LD2, true); - } -} - -#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32f0l0g0/nucleo-c071rb/src/stm32_boot.c b/boards/arm/stm32f0l0g0/nucleo-c071rb/src/stm32_boot.c deleted file mode 100644 index b12a1c64a71d5..0000000000000 --- a/boards/arm/stm32f0l0g0/nucleo-c071rb/src/stm32_boot.c +++ /dev/null @@ -1,83 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-c071rb/src/stm32_boot.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include "nucleo-c071rb.h" - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_boardinitialize - * - * Description: - * All STM32 architectures must provide the following entry point. This - * entry point is called early in the initialization -- after all memory - * has been configured and mapped but before any devices have been - * initialized. - * - ****************************************************************************/ - -void stm32_boardinitialize(void) -{ -#ifdef CONFIG_ARCH_LEDS - /* Configure on-board LEDs if LED support has been selected. */ - - board_autoled_initialize(); -#endif - -#ifdef CONFIG_STM32F0L0G0_SPI - /* Configure SPI chip selects */ - - stm32_spidev_initialize(); -#endif -} - -/**************************************************************************** - * Name: board_late_initialize - * - * Description: - * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional - * initialization call will be performed in the boot-up sequence to a - * function called board_late_initialize(). board_late_initialize() will - * be called immediately after up_initialize() is called and just before - * the initial application is started. This additional initialization - * phase may be used, for example, to initialize board-specific device - * drivers. - * - ****************************************************************************/ - -#ifdef CONFIG_BOARD_LATE_INITIALIZE -void board_late_initialize(void) -{ - stm32_bringup(); -} -#endif diff --git a/boards/arm/stm32f0l0g0/nucleo-c071rb/src/stm32_bringup.c b/boards/arm/stm32f0l0g0/nucleo-c071rb/src/stm32_bringup.c deleted file mode 100644 index 574a196b77861..0000000000000 --- a/boards/arm/stm32f0l0g0/nucleo-c071rb/src/stm32_bringup.c +++ /dev/null @@ -1,142 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-c071rb/src/stm32_bringup.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include - -#ifdef CONFIG_INPUT_BUTTONS -# include -#endif - -#ifdef CONFIG_USERLED -# include -#endif - -#ifdef CONFIG_STM32F0L0G0_IWDG -# include -#endif - -#ifdef CONFIG_SENSORS_QENCODER -# include "board_qencoder.h" -#endif - -#ifdef CONFIG_PWM -# include "board_pwm.h" -#endif - -#include - -#include "nucleo-c071rb.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_bringup - * - * Description: - * Perform architecture-specific initialization - * - * CONFIG_BOARD_LATE_INITIALIZE=y : - * Called from board_late_initialize(). - * - ****************************************************************************/ - -int stm32_bringup(void) -{ - int ret; - -#ifdef CONFIG_STM32F0L0G0_IWDG - /* Initialize the watchdog timer */ - - stm32_iwdginitialize("/dev/watchdog0", STM32_LSI_FREQUENCY); -#endif - -#if !defined(CONFIG_ARCH_LEDS) && defined(CONFIG_USERLED_LOWER) - /* Register the LED driver */ - - ret = userled_lower_initialize(LED_DRIVER_PATH); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: userled_lower_initialize() failed: %d\n", ret); - return ret; - } -#endif - -#ifdef CONFIG_INPUT_BUTTONS - /* Register the BUTTON driver */ - - ret = btn_lower_initialize("/dev/buttons"); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: btn_lower_initialize() failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_ADC - /* Initialize ADC and register the ADC driver. */ - - ret = stm32_adc_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_adc_setup failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_PWM - /* Initialize PWM and register the PWM device. */ - - ret = stm32_pwm_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_pwm_setup failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_SENSORS_QENCODER - /* Initialize and register the qencoder driver - TIM3 */ - - ret = board_qencoder_initialize(0, 3); - if (ret != OK) - { - syslog(LOG_ERR, - "ERROR: Failed to register the qencoder: %d\n", - ret); - return ret; - } -#endif - - UNUSED(ret); - return OK; -} diff --git a/boards/arm/stm32f0l0g0/nucleo-c071rb/src/stm32_buttons.c b/boards/arm/stm32f0l0g0/nucleo-c071rb/src/stm32_buttons.c deleted file mode 100644 index bc9ffb41367f3..0000000000000 --- a/boards/arm/stm32f0l0g0/nucleo-c071rb/src/stm32_buttons.c +++ /dev/null @@ -1,117 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-c071rb/src/stm32_buttons.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include -#include - -#include "stm32_gpio.h" -#include "nucleo-c071rb.h" - -#ifdef CONFIG_ARCH_BUTTONS - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_button_initialize - * - * Description: - * board_button_initialize() must be called to initialize button resources. - * After that, board_buttons() may be called to collect the current state - * of all buttons or board_button_irq() may be called to register button - * interrupt handlers. - * - ****************************************************************************/ - -uint32_t board_button_initialize(void) -{ - /* Configure the single button as an input. NOTE that EXTI interrupts are - * also configured for the pin. - */ - - stm32_configgpio(GPIO_BTN_USER); - return NUM_BUTTONS; -} - -/**************************************************************************** - * Name: board_buttons - ****************************************************************************/ - -uint32_t board_buttons(void) -{ - /* Check that state of each USER button. A LOW value means that the key is - * pressed. - */ - - bool released = stm32_gpioread(GPIO_BTN_USER); - return !released; -} - -/**************************************************************************** - * Button support. - * - * Description: - * board_button_initialize() must be called to initialize button resources. - * After that, board_buttons() may be called to collect the current state - * of all buttons or board_button_irq() may be called to register button - * interrupt handlers. - * - * After board_button_initialize() has been called, board_buttons() may be - * called to collect the state of all buttons. board_buttons() returns an - * 32-bit bit set with each bit associated with a button. See the - * BUTTON_*_BIT definitions in board.h for the meaning of each bit. - * - * board_button_irq() may be called to register an interrupt handler that - * will be called when a button is depressed or released. The ID value is a - * button enumeration value that uniquely identifies a button resource. See - * the BUTTON_* definitions in board.h for the meaning of enumeration - * value. - * - ****************************************************************************/ - -#ifdef CONFIG_ARCH_IRQBUTTONS -int board_button_irq(int id, xcpt_t irqhandler, void *arg) -{ - int ret = -EINVAL; - - if (id == BUTTON_USER) - { - ret = stm32_gpiosetevent(GPIO_BTN_USER, true, true, true, - irqhandler, arg); - } - - return ret; -} -#endif -#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/stm32f0l0g0/nucleo-c071rb/src/stm32_userleds.c b/boards/arm/stm32f0l0g0/nucleo-c071rb/src/stm32_userleds.c deleted file mode 100644 index 2ee610d173f62..0000000000000 --- a/boards/arm/stm32f0l0g0/nucleo-c071rb/src/stm32_userleds.c +++ /dev/null @@ -1,172 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-c071rb/src/stm32_userleds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include - -#include -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32_gpio.h" -#include "nucleo-c071rb.h" - -#ifndef CONFIG_ARCH_LEDS - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -/* LED Power Management */ - -#ifdef CONFIG_PM -static void led_pm_notify(struct pm_callback_s *cb, int domain, - enum pm_state_e pmstate); -static int led_pm_prepare(struct pm_callback_s *cb, int domain, - enum pm_state_e pmstate); -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -#ifdef CONFIG_PM -static struct pm_callback_s g_ledscb = -{ - .notify = led_pm_notify, - .prepare = led_pm_prepare, -}; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: led_pm_notify - * - * Description: - * Notify the driver of new power state. This callback is called after - * all drivers have had the opportunity to prepare for the new power state. - * - ****************************************************************************/ - -#ifdef CONFIG_PM -static void led_pm_notify(struct pm_callback_s *cb, int domain, - enum pm_state_e pmstate) -{ -} -#endif - -/**************************************************************************** - * Name: led_pm_prepare - * - * Description: - * Request the driver to prepare for a new power state. This is a warning - * that the system is about to enter into a new power state. The driver - * should begin whatever operations that may be required to enter power - * state. The driver may abort the state change mode by returning a - * non-zero value from the callback function. - * - ****************************************************************************/ - -#ifdef CONFIG_PM -static int led_pm_prepare(struct pm_callback_s *cb, int domain, - enum pm_state_e pmstate) -{ - /* No preparation to change power modes is required by the LEDs driver. - * We always accept the state change by returning OK. - */ - - return OK; -} -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_userled_initialize - ****************************************************************************/ - -uint32_t board_userled_initialize(void) -{ - /* Configure LD1 and LD2 GPIO for output */ - - stm32_configgpio(GPIO_LD1); - stm32_configgpio(GPIO_LD2); - return BOARD_NLEDS; -} - -/**************************************************************************** - * Name: board_userled - ****************************************************************************/ - -void board_userled(int led, bool ledon) -{ - if (led == BOARD_LED1) - { - stm32_gpiowrite(GPIO_LD1, ledon); - } - - if (led == BOARD_LED2) - { - stm32_gpiowrite(GPIO_LD2, !ledon); - } -} - -/**************************************************************************** - * Name: board_userled_all - ****************************************************************************/ - -void board_userled_all(uint32_t ledset) -{ - stm32_gpiowrite(GPIO_LD1, (ledset & BOARD_LED1_BIT) != 0); - stm32_gpiowrite(GPIO_LD2, (ledset & BOARD_LED2_BIT) == 0); -} - -/**************************************************************************** - * Name: stm32_led_pminitialize - ****************************************************************************/ - -#ifdef CONFIG_PM -void stm32_led_pminitialize(void) -{ - /* Register to receive power management callbacks */ - - int ret = pm_register(&g_ledscb); - DEBUGASSERT(ret == OK); - UNUSED(ret); -} -#endif /* CONFIG_PM */ - -#endif /* !CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32f0l0g0/nucleo-c092rc/CMakeLists.txt b/boards/arm/stm32f0l0g0/nucleo-c092rc/CMakeLists.txt deleted file mode 100644 index 1eaec21dd1a97..0000000000000 --- a/boards/arm/stm32f0l0g0/nucleo-c092rc/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32f0l0g0/nucleo-c092rc/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32f0l0g0/nucleo-c092rc/configs/can/defconfig b/boards/arm/stm32f0l0g0/nucleo-c092rc/configs/can/defconfig deleted file mode 100644 index e8640c01a5c45..0000000000000 --- a/boards/arm/stm32f0l0g0/nucleo-c092rc/configs/can/defconfig +++ /dev/null @@ -1,51 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="nucleo-c092rc" -CONFIG_ARCH_BOARD_NUCLEO_C092RC=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32f0l0g0" -CONFIG_ARCH_CHIP_STM32C092RC=y -CONFIG_ARCH_CHIP_STM32C092XX=y -CONFIG_ARCH_CHIP_STM32C0=y -CONFIG_ARCH_IRQBUTTONS=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=3997 -CONFIG_BUILTIN=y -CONFIG_CAN_ERRORS=y -CONFIG_CAN_EXTID=y -CONFIG_DEBUG_FULLOPT=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_EXAMPLES_CAN=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INIT_STACKSIZE=1536 -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=64 -CONFIG_NSH_READLINE=y -CONFIG_POSIX_SPAWN_DEFAULT_STACKSIZE=1536 -CONFIG_PTHREAD_MUTEX_UNSAFE=y -CONFIG_PTHREAD_STACK_DEFAULT=1536 -CONFIG_RAM_SIZE=30720 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=19 -CONFIG_START_MONTH=5 -CONFIG_START_YEAR=2013 -CONFIG_STDIO_DISABLE_BUFFERING=y -CONFIG_STM32F0L0G0_FDCAN1=y -CONFIG_STM32F0L0G0_FDCAN1_BITRATE=250000 -CONFIG_STM32F0L0G0_FDCAN1_NTSEG1=143 -CONFIG_STM32F0L0G0_FDCAN1_NTSEG2=48 -CONFIG_STM32F0L0G0_USART2=y -CONFIG_SYSTEM_NSH=y -CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f0l0g0/nucleo-c092rc/configs/cansock/defconfig b/boards/arm/stm32f0l0g0/nucleo-c092rc/configs/cansock/defconfig deleted file mode 100644 index 0be70e4919560..0000000000000 --- a/boards/arm/stm32f0l0g0/nucleo-c092rc/configs/cansock/defconfig +++ /dev/null @@ -1,57 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_NET_ETHERNET is not set -# CONFIG_NET_IPv4 is not set -CONFIG_ALLOW_BSD_COMPONENTS=y -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="nucleo-c092rc" -CONFIG_ARCH_BOARD_NUCLEO_C092RC=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32f0l0g0" -CONFIG_ARCH_CHIP_STM32C092RC=y -CONFIG_ARCH_CHIP_STM32C092XX=y -CONFIG_ARCH_CHIP_STM32C0=y -CONFIG_ARCH_INTERRUPTSTACK=1024 -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=3997 -CONFIG_BUILTIN=y -CONFIG_CANUTILS_CANDUMP=y -CONFIG_CANUTILS_CANSEND=y -CONFIG_CANUTILS_LIBCANUTILS=y -CONFIG_DEBUG_FULLOPT=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_IOB_BUFSIZE=128 -CONFIG_IOB_NBUFFERS=10 -CONFIG_LINE_MAX=64 -CONFIG_NET=y -CONFIG_NETDEV_IFINDEX=y -CONFIG_NETDEV_LATEINIT=y -CONFIG_NET_CAN=y -CONFIG_NET_SOCKOPTS=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_RAM_SIZE=30720 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_LPWORK=y -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=14 -CONFIG_START_MONTH=10 -CONFIG_START_YEAR=2014 -CONFIG_STM32F0L0G0_FDCAN1=y -CONFIG_STM32F0L0G0_FDCAN1_BITRATE=250000 -CONFIG_STM32F0L0G0_FDCAN1_NTSEG1=143 -CONFIG_STM32F0L0G0_FDCAN1_NTSEG2=48 -CONFIG_STM32F0L0G0_FDCAN_SOCKET=y -CONFIG_STM32F0L0G0_USART2=y -CONFIG_SYSTEM_NSH=y -CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f0l0g0/nucleo-c092rc/configs/jumbo/defconfig b/boards/arm/stm32f0l0g0/nucleo-c092rc/configs/jumbo/defconfig deleted file mode 100644 index c3a1f4f8b40f5..0000000000000 --- a/boards/arm/stm32f0l0g0/nucleo-c092rc/configs/jumbo/defconfig +++ /dev/null @@ -1,89 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_NSH_ARGCAT is not set -CONFIG_ADC=y -CONFIG_ANALOG=y -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="nucleo-c092rc" -CONFIG_ARCH_BOARD_COMMON=y -CONFIG_ARCH_BOARD_NUCLEO_C092RC=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32f0l0g0" -CONFIG_ARCH_CHIP_STM32C092RC=y -CONFIG_ARCH_CHIP_STM32C092XX=y -CONFIG_ARCH_CHIP_STM32C0=y -CONFIG_ARCH_IRQBUTTONS=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARDCTL=y -CONFIG_BOARD_LOOPSPERMSEC=3997 -CONFIG_BUILTIN=y -CONFIG_DEBUG_FEATURES=y -CONFIG_DEBUG_FULLOPT=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_DEV_GPIO=y -CONFIG_DISABLE_ENVIRON=y -CONFIG_DISABLE_MOUNTPOINT=y -CONFIG_DISABLE_MQUEUE=y -CONFIG_DISABLE_POSIX_TIMERS=y -CONFIG_DISABLE_PSEUDOFS_OPERATIONS=y -CONFIG_EXAMPLES_ADC=y -CONFIG_EXAMPLES_ADC_GROUPSIZE=2 -CONFIG_EXAMPLES_ADC_SWTRIG=y -CONFIG_EXAMPLES_BUTTONS=y -CONFIG_EXAMPLES_HELLO=y -CONFIG_EXAMPLES_PULSECOUNT=y -CONFIG_EXAMPLES_PWM=y -CONFIG_EXAMPLES_PWM_DEVPATH="/dev/pwm13" -CONFIG_EXAMPLES_QENCODER=y -CONFIG_EXAMPLES_WATCHDOG=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INIT_STACKSIZE=1536 -CONFIG_INPUT=y -CONFIG_INPUT_BUTTONS=y -CONFIG_INPUT_BUTTONS_DEBOUNCE_DELAY=10 -CONFIG_INPUT_BUTTONS_LOWER=y -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=64 -CONFIG_NSH_READLINE=y -CONFIG_NUNGET_CHARS=0 -CONFIG_POSIX_SPAWN_DEFAULT_STACKSIZE=1536 -CONFIG_PTHREAD_MUTEX_UNSAFE=y -CONFIG_PTHREAD_STACK_DEFAULT=1536 -CONFIG_PWM=y -CONFIG_RAM_SIZE=30720 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_SENSORS=y -CONFIG_SENSORS_QENCODER=y -CONFIG_START_DAY=19 -CONFIG_START_MONTH=5 -CONFIG_START_YEAR=2013 -CONFIG_STDIO_DISABLE_BUFFERING=y -CONFIG_STM32F0L0G0_ADC1=y -CONFIG_STM32F0L0G0_ADC_MAX_SAMPLES=2 -CONFIG_STM32F0L0G0_DMA1=y -CONFIG_STM32F0L0G0_IWDG=y -CONFIG_STM32F0L0G0_PWM_MULTICHAN=y -CONFIG_STM32F0L0G0_TIM14=y -CONFIG_STM32F0L0G0_TIM14_CH1OUT=y -CONFIG_STM32F0L0G0_TIM14_CHANNEL1=y -CONFIG_STM32F0L0G0_TIM14_PWM=y -CONFIG_STM32F0L0G0_TIM1=y -CONFIG_STM32F0L0G0_TIM1_PULSECOUNT=y -CONFIG_STM32F0L0G0_TIM3=y -CONFIG_STM32F0L0G0_TIM3_QE=y -CONFIG_STM32F0L0G0_USART2=y -CONFIG_STM32F0L0G0_WWDG=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f0l0g0/nucleo-c092rc/configs/nsh/defconfig b/boards/arm/stm32f0l0g0/nucleo-c092rc/configs/nsh/defconfig deleted file mode 100644 index ed0012322cc6f..0000000000000 --- a/boards/arm/stm32f0l0g0/nucleo-c092rc/configs/nsh/defconfig +++ /dev/null @@ -1,44 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="nucleo-c092rc" -CONFIG_ARCH_BOARD_NUCLEO_C092RC=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32f0l0g0" -CONFIG_ARCH_CHIP_STM32C092RC=y -CONFIG_ARCH_CHIP_STM32C092XX=y -CONFIG_ARCH_CHIP_STM32C0=y -CONFIG_ARCH_IRQBUTTONS=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=3997 -CONFIG_DEBUG_FULLOPT=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INIT_STACKSIZE=1536 -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 -CONFIG_NSH_FILEIOSIZE=64 -CONFIG_NSH_READLINE=y -CONFIG_NUNGET_CHARS=0 -CONFIG_POSIX_SPAWN_DEFAULT_STACKSIZE=1536 -CONFIG_PTHREAD_MUTEX_UNSAFE=y -CONFIG_PTHREAD_STACK_DEFAULT=1536 -CONFIG_RAM_SIZE=30720 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=19 -CONFIG_START_MONTH=5 -CONFIG_START_YEAR=2013 -CONFIG_STDIO_DISABLE_BUFFERING=y -CONFIG_STM32F0L0G0_USART2=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f0l0g0/nucleo-c092rc/include/board.h b/boards/arm/stm32f0l0g0/nucleo-c092rc/include/board.h deleted file mode 100644 index f85f0b12044b3..0000000000000 --- a/boards/arm/stm32f0l0g0/nucleo-c092rc/include/board.h +++ /dev/null @@ -1,202 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-c092rc/include/board.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __BOARDS_ARM_STM32F0L0G0_NUCLEO_C092RC_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32F0L0G0_NUCLEO_C092RC_INCLUDE_BOARD_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#ifndef __ASSEMBLY__ -# include -#endif - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Clocking *****************************************************************/ - -/* HSI - Internal 48 MHz RC Oscillator - * LSI - 32 KHz RC - * HSE - 8 MHz from MCO output of ST-LINK (disabled by default) - * LSE - 32.768 kHz - */ - -#define STM32_BOARD_XTAL 8000000ul /* 8MHz */ - -#define STM32_HSI_FREQUENCY 48000000ul /* 48MHz */ -#define STM32_LSI_FREQUENCY 32000 /* Between 30kHz and 60kHz */ -#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL -#define STM32_LSE_FREQUENCY 32768 /* X2 on board */ - -/* Configure HSI48 clock division factor (48 MHz) */ - -#define STM32_RCC_HSIDIV RCC_CR_HSIDIV_HSI - -/* Use the HSI as SYSCLK source (48 MHz) */ - -#define STM32_SYSCLK_SW RCC_CFGR_SW_HSI -#define STM32_SYSCLK_SWS RCC_CFGR_SWS_HSI -#define STM32_SYSCLK_FREQUENCY (STM32_HSI_FREQUENCY) - -/* AHB clock (HCLK) is SYSCLK (48 MHz) */ - -#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK -#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY - -/* APB1 clock (PCLK) is HCLK (48 MHz) */ - -#define STM32_RCC_CFGR_PPRE RCC_CFGR_PPRE_HCLK -#define STM32_PCLK1_FREQUENCY STM32_HCLK_FREQUENCY - -/* FDCAN1 clock is PCLK (48 MHz) */ - -#define STM32_FDCAN1_SEL RCC_CCIPR1_FDCAN1SEL_PCLK -#define STM32_FDCAN_FREQUENCY STM32_PCLK1_FREQUENCY - -/* All timers on PCLK x1 (48 MHz) */ - -#define STM32_APB2_TIM1_CLKIN STM32_PCLK1_FREQUENCY -#define STM32_APB1_TIM2_CLKIN STM32_PCLK1_FREQUENCY -#define STM32_APB1_TIM3_CLKIN STM32_PCLK1_FREQUENCY -#define STM32_APB2_TIM14_CLKIN STM32_PCLK1_FREQUENCY -#define STM32_APB2_TIM15_CLKIN STM32_PCLK1_FREQUENCY -#define STM32_APB2_TIM16_CLKIN STM32_PCLK1_FREQUENCY -#define STM32_APB2_TIM17_CLKIN STM32_PCLK1_FREQUENCY - -/* LED definitions **********************************************************/ - -/* LED index values for use with board_userled() */ - -#define BOARD_LED1 0 /* User LD1 */ -#define BOARD_LED2 1 /* User LD2 */ -#define BOARD_NLEDS 2 - -/* LED bits for use with board_userled_all() */ - -#define BOARD_LED1_BIT (1 << BOARD_LED1) -#define BOARD_LED2_BIT (1 << BOARD_LED2) - -/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the LED on the - * board. The following definitions describe how NuttX controls - * the LED: - * - * SYMBOL Meaning LED1 state - * ------------------ ----------------------- ---------- - * LED_STARTED NuttX has been started OFF - * LED_HEAPALLOCATE Heap has been allocated OFF - * LED_IRQSENABLED Interrupts enabled OFF - * LED_STACKCREATED Idle stack created ON - * LED_INIRQ In an interrupt No change - * LED_SIGNAL In a signal handler No change - * LED_ASSERTION An assertion failed No change - * LED_PANIC The system has crashed Blinking - * LED_IDLE STM32 is in sleep mode Not used - */ - -#define LED_STARTED 0 -#define LED_HEAPALLOCATE 0 -#define LED_IRQSENABLED 0 -#define LED_STACKCREATED 1 -#define LED_INIRQ 2 -#define LED_SIGNAL 2 -#define LED_ASSERTION 2 -#define LED_PANIC 1 - -/* Button definitions *******************************************************/ - -/* Nucleo C092RC board supports two buttons; only one button is controllable - * by software: - * - * B1 USER: user button connected to STM32 I/O PC13. - * B2 RESET: push button connected to NRST; used to RESET the MCU. - */ - -#define BUTTON_USER 0 /* User B1 */ -#define NUM_BUTTONS 1 - -#define BUTTON_USER_BIT (1 << BUTTON_USER) - -/* Alternate function pin selections ****************************************/ - -/* USART */ - -/* USART1 at arduino D0/D1: - * USART1_RX - PB7 - * USART1_TX - PB6 - */ - -#define GPIO_USART1_RX (GPIO_USART1_RX_2|GPIO_SPEED_HIGH) /* PB7 */ -#define GPIO_USART1_TX (GPIO_USART1_TX_2|GPIO_SPEED_HIGH) /* PB6 */ - -/* USART1 RS485_DIR - PA8 (arduino D7) - * (compatible with RS485 Waveshare shield) - */ - -#define GPIO_USART1_RS485_DIR (GPIO_OUTPUT | GPIO_PUSHPULL | \ - GPIO_SPEED_HIGH | GPIO_OUTPUT_CLEAR | \ - GPIO_PORTA | GPIO_PIN8) - -/* By default the USART2 is connected to STLINK Virtual COM Port: - * USART2_RX - PA3 - * USART2_TX - PA2 - */ - -#define GPIO_USART2_RX (GPIO_USART2_RX_1|GPIO_SPEED_HIGH) /* PA3 */ -#define GPIO_USART2_TX (GPIO_USART2_TX_1|GPIO_SPEED_HIGH) /* PA2 */ - -/* FDCAN */ - -#define GPIO_FDCAN1_RX (GPIO_FDCAN1_RX_8|GPIO_SPEED_HIGH) /* PD0 */ -#define GPIO_FDCAN1_TX (GPIO_FDCAN1_TX_9|GPIO_SPEED_HIGH) /* PD1 */ - -/* Qencoder on TIM3: - * TIM3_CH1IN - PB4 (D5) - * TIM3_CH2IN - PC7 (D3) - */ - -#define GPIO_TIM3_CH1IN (GPIO_TIM3_CH1IN_2|GPIO_SPEED_HIGH) -#define GPIO_TIM3_CH2IN (GPIO_TIM3_CH2IN_6|GPIO_SPEED_HIGH) - -/* PWM on TIM14: - * TIM14_CH1 - PA7 (D11) - */ - -#define GPIO_TIM14_CH1OUT (GPIO_TIM14_CH1OUT_2|GPIO_SPEED_HIGH) - -/* Pulse count on TIM1: - * TIM1_CH1OUT - PA8 (D7) - */ - -#define GPIO_TIM1_CH1OUT (GPIO_TIM1_CH1OUT_3|GPIO_SPEED_HIGH) - -/* DMA channels *************************************************************/ - -/* ADC */ - -#define ADC1_DMA_CHAN DMAMAP_DMA1_ADC1 /* DMA1 */ - -#endif /* __BOARDS_ARM_STM32F0L0G0_NUCLEO_C092RC_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32f0l0g0/nucleo-c092rc/scripts/Make.defs b/boards/arm/stm32f0l0g0/nucleo-c092rc/scripts/Make.defs deleted file mode 100644 index 58cbdee0271d3..0000000000000 --- a/boards/arm/stm32f0l0g0/nucleo-c092rc/scripts/Make.defs +++ /dev/null @@ -1,41 +0,0 @@ -############################################################################ -# boards/arm/stm32f0l0g0/nucleo-c092rc/scripts/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/.config -include $(TOPDIR)/tools/Config.mk -include $(TOPDIR)/arch/arm/src/armv6-m/Toolchain.defs - -LDSCRIPT = flash.ld -ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) - -ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 - -CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) -CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) -CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -AFLAGS := $(CFLAGS) -D__ASSEMBLY__ - -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections -LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32f0l0g0/nucleo-c092rc/scripts/flash.ld b/boards/arm/stm32f0l0g0/nucleo-c092rc/scripts/flash.ld deleted file mode 100644 index 675eb647b5b0b..0000000000000 --- a/boards/arm/stm32f0l0g0/nucleo-c092rc/scripts/flash.ld +++ /dev/null @@ -1,111 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-c092rc/scripts/flash.ld - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* The STM32C092RCT6 has 256KB of FLASH beginning at address 0x0800:0000 and - * 30KB of SRAM at address 0x20000000. - * - * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 - * where the code expects to begin execution by jumping to the entry point in - * the 0x0800:0000 address range. - */ - -MEMORY -{ - flash (rx) : ORIGIN = 0x08000000, LENGTH = 256K - sram (rwx) : ORIGIN = 0x20000000, LENGTH = 30K -} - -OUTPUT_ARCH(arm) -EXTERN(_vectors) -ENTRY(_stext) - -SECTIONS -{ - .text : - { - _stext = ABSOLUTE(.); - *(.vectors) - *(.text .text.*) - *(.fixup) - *(.gnu.warning) - *(.rodata .rodata.*) - *(.gnu.linkonce.t.*) - *(.glue_7) - *(.glue_7t) - *(.got) - *(.gcc_except_table) - *(.gnu.linkonce.r.*) - _etext = ABSOLUTE(.); - } > flash - - .init_section : ALIGN(4) { - _sinit = ABSOLUTE(.); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) - KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) - _einit = ABSOLUTE(.); - } > flash - - .ARM.extab : ALIGN(4) { - *(.ARM.extab*) - } > flash - - .ARM.exidx : ALIGN(4) { - __exidx_start = ABSOLUTE(.); - *(.ARM.exidx*) - __exidx_end = ABSOLUTE(.); - } > flash - - _eronly = ABSOLUTE(.); - - .data : ALIGN(4) { - _sdata = ABSOLUTE(.); - *(.data .data.*) - *(.gnu.linkonce.d.*) - CONSTRUCTORS - . = ALIGN(4); - _edata = ABSOLUTE(.); - } > sram AT > flash - - .bss : ALIGN(4) { - _sbss = ABSOLUTE(.); - *(.bss .bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - . = ALIGN(8); - _ebss = ABSOLUTE(.); - } > sram - - /* Stabs debugging sections. */ - - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_info 0 : { *(.debug_info) } - .debug_line 0 : { *(.debug_line) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_aranges 0 : { *(.debug_aranges) } -} diff --git a/boards/arm/stm32f0l0g0/nucleo-c092rc/src/CMakeLists.txt b/boards/arm/stm32f0l0g0/nucleo-c092rc/src/CMakeLists.txt deleted file mode 100644 index 163b6d6bb7c73..0000000000000 --- a/boards/arm/stm32f0l0g0/nucleo-c092rc/src/CMakeLists.txt +++ /dev/null @@ -1,50 +0,0 @@ -# ############################################################################## -# boards/arm/stm32f0l0g0/nucleo-c092rc/src/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -set(SRCS stm32_boot.c stm32_bringup.c) - -if(CONFIG_ARCH_LEDS) - list(APPEND SRCS stm32_autoleds.c) -else() - list(APPEND SRCS stm32_userleds.c) -endif() - -if(CONFIG_ARCH_BUTTONS) - list(APPEND SRCS stm32_buttons.c) -endif() - -if(CONFIG_ADC) - list(APPEND SRCS stm32_adc.c) -endif() - -if(CONFIG_STM32F0L0G0_FDCAN) - if(CONFIG_STM32F0L0G0_FDCAN_CHARDRIVER) - list(APPEND SRCS stm32_can.c) - endif() - if(CONFIG_STM32F0L0G0_FDCAN_SOCKET) - list(APPEND SRCS stm32_cansock.c) - endif() -endif() - -target_sources(board PRIVATE ${SRCS}) - -set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/flash.ld") diff --git a/boards/arm/stm32f0l0g0/nucleo-c092rc/src/Make.defs b/boards/arm/stm32f0l0g0/nucleo-c092rc/src/Make.defs deleted file mode 100644 index aa1ef14621960..0000000000000 --- a/boards/arm/stm32f0l0g0/nucleo-c092rc/src/Make.defs +++ /dev/null @@ -1,52 +0,0 @@ -############################################################################ -# boards/arm/stm32f0l0g0/nucleo-c092rc/src/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/Make.defs - -CSRCS = stm32_boot.c stm32_bringup.c - -ifeq ($(CONFIG_ARCH_LEDS),y) -CSRCS += stm32_autoleds.c -else -CSRCS += stm32_userleds.c -endif - -ifeq ($(CONFIG_ARCH_BUTTONS),y) -CSRCS += stm32_buttons.c -endif - -ifeq ($(CONFIG_ADC),y) -CSRCS += stm32_adc.c -endif - -ifeq ($(CONFIG_STM32F0L0G0_FDCAN),y) -ifeq ($(CONFIG_STM32F0L0G0_FDCAN_CHARDRIVER),y) -CSRCS += stm32_can.c -endif -ifeq ($(CONFIG_STM32F0L0G0_FDCAN_SOCKET),y) -CSRCS += stm32_cansock.c -endif -endif - -DEPPATH += --dep-path board -VPATH += :board -CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32f0l0g0/nucleo-c092rc/src/stm32_adc.c b/boards/arm/stm32f0l0g0/nucleo-c092rc/src/stm32_adc.c deleted file mode 100644 index 51a76e9d5912c..0000000000000 --- a/boards/arm/stm32f0l0g0/nucleo-c092rc/src/stm32_adc.c +++ /dev/null @@ -1,129 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-c092rc/src/stm32_adc.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include - -#include - -#include "stm32.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -/* The number of ADC channels in the conversion list */ - -#define ADC1_NCHANNELS 2 - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* Identifying number of each ADC channel (even if NCHANNELS is less ) */ - -static const uint8_t g_chanlist1[2] = -{ - 0, - 1, -}; - -/* Configurations of pins used by each ADC channel */ - -static const uint32_t g_pinlist1[2] = -{ - GPIO_ADC1_IN0_0, /* PA0/A0 */ - GPIO_ADC1_IN1_0 /* PA1/A1 */ -}; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_adc_setup - * - * Description: - * Initialize ADC and register the ADC driver. - * - ****************************************************************************/ - -int stm32_adc_setup(void) -{ - static bool initialized = false; - struct adc_dev_s *adc; - int ret; - int i; - - /* Check if we have already initialized */ - - if (!initialized) - { - /* Configure the pins as analog inputs for the selected channels */ - - for (i = 0; i < ADC1_NCHANNELS; i++) - { - stm32_configgpio(g_pinlist1[i]); - } - - /* Call stm32_adcinitialize() to get an instance of the ADC interface */ - - adc = stm32_adcinitialize(1, g_chanlist1, ADC1_NCHANNELS); - if (adc == NULL) - { - aerr("ERROR: Failed to get ADC interface 1\n"); - return -ENODEV; - } - - /* Register the ADC driver at "/dev/adc0" */ - - ret = adc_register("/dev/adc0", adc); - if (ret < 0) - { - aerr("ERROR: adc_register /dev/adc0 failed: %d\n", ret); - return ret; - } - - initialized = true; - } - - return OK; -} diff --git a/boards/arm/stm32f0l0g0/nucleo-c092rc/src/stm32_autoleds.c b/boards/arm/stm32f0l0g0/nucleo-c092rc/src/stm32_autoleds.c deleted file mode 100644 index 016eca350de0c..0000000000000 --- a/boards/arm/stm32f0l0g0/nucleo-c092rc/src/stm32_autoleds.c +++ /dev/null @@ -1,93 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-c092rc/src/stm32_autoleds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32_gpio.h" -#include "nucleo-c092rc.h" - -#ifdef CONFIG_ARCH_LEDS - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_autoled_initialize - ****************************************************************************/ - -void board_autoled_initialize(void) -{ - /* Configure LD1 and LD2 GPIO for output */ - - stm32_configgpio(GPIO_LD1); - stm32_configgpio(GPIO_LD2); -} - -/**************************************************************************** - * Name: board_autoled_on - ****************************************************************************/ - -void board_autoled_on(int led) -{ - if (led == BOARD_LED1) - { - stm32_gpiowrite(GPIO_LD1, true); - } - - if (led == BOARD_LED2) - { - stm32_gpiowrite(GPIO_LD2, false); - } -} - -/**************************************************************************** - * Name: board_autoled_off - ****************************************************************************/ - -void board_autoled_off(int led) -{ - if (led == BOARD_LED1) - { - stm32_gpiowrite(GPIO_LD1, false); - } - - if (led == BOARD_LED2) - { - stm32_gpiowrite(GPIO_LD2, true); - } -} - -#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32f0l0g0/nucleo-c092rc/src/stm32_boot.c b/boards/arm/stm32f0l0g0/nucleo-c092rc/src/stm32_boot.c deleted file mode 100644 index ceb6af10047d6..0000000000000 --- a/boards/arm/stm32f0l0g0/nucleo-c092rc/src/stm32_boot.c +++ /dev/null @@ -1,83 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-c092rc/src/stm32_boot.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include "nucleo-c092rc.h" - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_boardinitialize - * - * Description: - * All STM32 architectures must provide the following entry point. This - * entry point is called early in the initialization -- after all memory - * has been configured and mapped but before any devices have been - * initialized. - * - ****************************************************************************/ - -void stm32_boardinitialize(void) -{ -#ifdef CONFIG_ARCH_LEDS - /* Configure on-board LEDs if LED support has been selected. */ - - board_autoled_initialize(); -#endif - -#ifdef CONFIG_STM32F0L0G0_SPI - /* Configure SPI chip selects */ - - stm32_spidev_initialize(); -#endif -} - -/**************************************************************************** - * Name: board_late_initialize - * - * Description: - * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional - * initialization call will be performed in the boot-up sequence to a - * function called board_late_initialize(). board_late_initialize() will - * be called immediately after up_initialize() is called and just before - * the initial application is started. This additional initialization - * phase may be used, for example, to initialize board-specific device - * drivers. - * - ****************************************************************************/ - -#ifdef CONFIG_BOARD_LATE_INITIALIZE -void board_late_initialize(void) -{ - stm32_bringup(); -} -#endif diff --git a/boards/arm/stm32f0l0g0/nucleo-c092rc/src/stm32_bringup.c b/boards/arm/stm32f0l0g0/nucleo-c092rc/src/stm32_bringup.c deleted file mode 100644 index ba1c4751664b2..0000000000000 --- a/boards/arm/stm32f0l0g0/nucleo-c092rc/src/stm32_bringup.c +++ /dev/null @@ -1,188 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-c092rc/src/stm32_bringup.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include -#include - -#ifdef CONFIG_INPUT_BUTTONS -# include -#endif - -#ifdef CONFIG_USERLED -# include -#endif - -#ifdef CONFIG_STM32F0L0G0_IWDG -# include -#endif - -#ifdef CONFIG_PULSECOUNT -# include "stm32_pulsecount.h" -#endif - -#ifdef CONFIG_SENSORS_QENCODER -# include "board_qencoder.h" -#endif - -#ifdef CONFIG_PWM -# include "board_pwm.h" -#endif - -#include - -#include "nucleo-c092rc.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_bringup - * - * Description: - * Perform architecture-specific initialization - * - * CONFIG_BOARD_LATE_INITIALIZE=y : - * Called from board_late_initialize(). - * - ****************************************************************************/ - -int stm32_bringup(void) -{ -#ifdef CONFIG_PULSECOUNT - struct pulsecount_lowerhalf_s *pulsecount; -#endif - int ret; - -#ifdef CONFIG_STM32F0L0G0_IWDG - /* Initialize the watchdog timer */ - - stm32_iwdginitialize("/dev/watchdog0", STM32_LSI_FREQUENCY); -#endif - -#ifdef CONFIG_PULSECOUNT - /* Initialize and register the pulse count driver. */ - - pulsecount = stm32_pulsecountinitialize(1); - if (pulsecount == NULL) - { - syslog(LOG_ERR, "ERROR: stm32_pulsecountinitialize failed\n"); - return -ENODEV; - } - - ret = pulsecount_register("/dev/pulsecount0", pulsecount); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: pulsecount_register failed: %d\n", ret); - return ret; - } -#endif - -#if !defined(CONFIG_ARCH_LEDS) && defined(CONFIG_USERLED_LOWER) - /* Register the LED driver */ - - ret = userled_lower_initialize(LED_DRIVER_PATH); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: userled_lower_initialize() failed: %d\n", ret); - return ret; - } -#endif - -#ifdef CONFIG_INPUT_BUTTONS - /* Register the BUTTON driver */ - - ret = btn_lower_initialize("/dev/buttons"); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: btn_lower_initialize() failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_ADC - /* Initialize ADC and register the ADC driver. */ - - ret = stm32_adc_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_adc_setup failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_PWM - /* Initialize PWM and register the PWM device. */ - - ret = stm32_pwm_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_pwm_setup failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_STM32F0L0G0_FDCAN_CHARDRIVER - /* Initialize CAN and register the CAN driver. */ - - ret = stm32_can_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_fdcan_setup failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_STM32F0L0G0_FDCAN_SOCKET - /* Initialize CAN socket interface */ - - ret = stm32_cansock_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_cansock_setup failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_SENSORS_QENCODER - /* Initialize and register the qencoder driver - TIM3 */ - - ret = board_qencoder_initialize(0, 3); - if (ret != OK) - { - syslog(LOG_ERR, - "ERROR: Failed to register the qencoder: %d\n", - ret); - return ret; - } -#endif - - UNUSED(ret); - return OK; -} diff --git a/boards/arm/stm32f0l0g0/nucleo-c092rc/src/stm32_buttons.c b/boards/arm/stm32f0l0g0/nucleo-c092rc/src/stm32_buttons.c deleted file mode 100644 index 06501f3b4ff7c..0000000000000 --- a/boards/arm/stm32f0l0g0/nucleo-c092rc/src/stm32_buttons.c +++ /dev/null @@ -1,117 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-c092rc/src/stm32_buttons.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include -#include - -#include "stm32_gpio.h" -#include "nucleo-c092rc.h" - -#ifdef CONFIG_ARCH_BUTTONS - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_button_initialize - * - * Description: - * board_button_initialize() must be called to initialize button resources. - * After that, board_buttons() may be called to collect the current state - * of all buttons or board_button_irq() may be called to register button - * interrupt handlers. - * - ****************************************************************************/ - -uint32_t board_button_initialize(void) -{ - /* Configure the single button as an input. NOTE that EXTI interrupts are - * also configured for the pin. - */ - - stm32_configgpio(GPIO_BTN_USER); - return NUM_BUTTONS; -} - -/**************************************************************************** - * Name: board_buttons - ****************************************************************************/ - -uint32_t board_buttons(void) -{ - /* Check that state of each USER button. A LOW value means that the key is - * pressed. - */ - - bool released = stm32_gpioread(GPIO_BTN_USER); - return !released; -} - -/**************************************************************************** - * Button support. - * - * Description: - * board_button_initialize() must be called to initialize button resources. - * After that, board_buttons() may be called to collect the current state - * of all buttons or board_button_irq() may be called to register button - * interrupt handlers. - * - * After board_button_initialize() has been called, board_buttons() may be - * called to collect the state of all buttons. board_buttons() returns an - * 32-bit bit set with each bit associated with a button. See the - * BUTTON_*_BIT definitions in board.h for the meaning of each bit. - * - * board_button_irq() may be called to register an interrupt handler that - * will be called when a button is depressed or released. The ID value is a - * button enumeration value that uniquely identifies a button resource. See - * the BUTTON_* definitions in board.h for the meaning of enumeration - * value. - * - ****************************************************************************/ - -#ifdef CONFIG_ARCH_IRQBUTTONS -int board_button_irq(int id, xcpt_t irqhandler, void *arg) -{ - int ret = -EINVAL; - - if (id == BUTTON_USER) - { - ret = stm32_gpiosetevent(GPIO_BTN_USER, true, true, true, - irqhandler, arg); - } - - return ret; -} -#endif -#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/stm32f0l0g0/nucleo-c092rc/src/stm32_can.c b/boards/arm/stm32f0l0g0/nucleo-c092rc/src/stm32_can.c deleted file mode 100644 index b51e5ba4d4dcc..0000000000000 --- a/boards/arm/stm32f0l0g0/nucleo-c092rc/src/stm32_can.c +++ /dev/null @@ -1,78 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-c092rc/src/stm32_can.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include "stm32_fdcan.h" -#include "nucleo-c092rc.h" - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_can_setup - * - * Description: - * Initialize CAN and register the CAN device - * - ****************************************************************************/ - -int stm32_can_setup(void) -{ - struct can_dev_s *can; - int ret; - - /* Configure STBY pin for output */ - - stm32_configgpio(GPIO_FDCAN_STBY); - - /* Set STBY pin low */ - - stm32_gpiowrite(GPIO_FDCAN_STBY, false); - - /* Call stm32_fdcaninitialize() to get an instance of the CAN interface */ - - can = stm32_fdcaninitialize(1); - if (can == NULL) - { - canerr("ERROR: Failed to get CAN interface\n"); - return -ENODEV; - } - - /* Register the CAN driver at "/dev/can0" */ - - ret = can_register("/dev/can0", can); - if (ret < 0) - { - canerr("ERROR: can_register failed: %d\n", ret); - return ret; - } - - return OK; -} diff --git a/boards/arm/stm32f0l0g0/nucleo-c092rc/src/stm32_cansock.c b/boards/arm/stm32f0l0g0/nucleo-c092rc/src/stm32_cansock.c deleted file mode 100644 index a1a4bcb89b2cf..0000000000000 --- a/boards/arm/stm32f0l0g0/nucleo-c092rc/src/stm32_cansock.c +++ /dev/null @@ -1,68 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-c092rc/src/stm32_cansock.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include "stm32_fdcan.h" -#include "nucleo-c092rc.h" - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_cansock_setup - * - * Description: - * Initialize CAN socket interface - * - ****************************************************************************/ - -int stm32_cansock_setup(void) -{ - int ret; - - /* Configure STBY pin for output */ - - stm32_configgpio(GPIO_FDCAN_STBY); - - /* Set STBY pin low */ - - stm32_gpiowrite(GPIO_FDCAN_STBY, false); - - /* Call stm32_fdcaninitialize() to get an instance of the FDCAN interface */ - - ret = stm32_fdcansockinitialize(1); - if (ret < 0) - { - canerr("ERROR: Failed to get FDCAN interface %d\n", ret); - return ret; - } - - return OK; -} diff --git a/boards/arm/stm32f0l0g0/nucleo-c092rc/src/stm32_userleds.c b/boards/arm/stm32f0l0g0/nucleo-c092rc/src/stm32_userleds.c deleted file mode 100644 index 77b08b2f3a8ba..0000000000000 --- a/boards/arm/stm32f0l0g0/nucleo-c092rc/src/stm32_userleds.c +++ /dev/null @@ -1,172 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-c092rc/src/stm32_userleds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include - -#include -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32_gpio.h" -#include "nucleo-c092rc.h" - -#ifndef CONFIG_ARCH_LEDS - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -/* LED Power Management */ - -#ifdef CONFIG_PM -static void led_pm_notify(struct pm_callback_s *cb, int domain, - enum pm_state_e pmstate); -static int led_pm_prepare(struct pm_callback_s *cb, int domain, - enum pm_state_e pmstate); -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -#ifdef CONFIG_PM -static struct pm_callback_s g_ledscb = -{ - .notify = led_pm_notify, - .prepare = led_pm_prepare, -}; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: led_pm_notify - * - * Description: - * Notify the driver of new power state. This callback is called after - * all drivers have had the opportunity to prepare for the new power state. - * - ****************************************************************************/ - -#ifdef CONFIG_PM -static void led_pm_notify(struct pm_callback_s *cb, int domain, - enum pm_state_e pmstate) -{ -} -#endif - -/**************************************************************************** - * Name: led_pm_prepare - * - * Description: - * Request the driver to prepare for a new power state. This is a warning - * that the system is about to enter into a new power state. The driver - * should begin whatever operations that may be required to enter power - * state. The driver may abort the state change mode by returning a - * non-zero value from the callback function. - * - ****************************************************************************/ - -#ifdef CONFIG_PM -static int led_pm_prepare(struct pm_callback_s *cb, int domain, - enum pm_state_e pmstate) -{ - /* No preparation to change power modes is required by the LEDs driver. - * We always accept the state change by returning OK. - */ - - return OK; -} -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_userled_initialize - ****************************************************************************/ - -uint32_t board_userled_initialize(void) -{ - /* Configure LD1 and LD2 GPIO for output */ - - stm32_configgpio(GPIO_LD1); - stm32_configgpio(GPIO_LD2); - return BOARD_NLEDS; -} - -/**************************************************************************** - * Name: board_userled - ****************************************************************************/ - -void board_userled(int led, bool ledon) -{ - if (led == BOARD_LED1) - { - stm32_gpiowrite(GPIO_LD1, ledon); - } - - if (led == BOARD_LED2) - { - stm32_gpiowrite(GPIO_LD2, !ledon); - } -} - -/**************************************************************************** - * Name: board_userled_all - ****************************************************************************/ - -void board_userled_all(uint32_t ledset) -{ - stm32_gpiowrite(GPIO_LD1, (ledset & BOARD_LED1_BIT) != 0); - stm32_gpiowrite(GPIO_LD2, (ledset & BOARD_LED2_BIT) == 0); -} - -/**************************************************************************** - * Name: stm32_led_pminitialize - ****************************************************************************/ - -#ifdef CONFIG_PM -void stm32_led_pminitialize(void) -{ - /* Register to receive power management callbacks */ - - int ret = pm_register(&g_ledscb); - DEBUGASSERT(ret == OK); - UNUSED(ret); -} -#endif /* CONFIG_PM */ - -#endif /* !CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32f0l0g0/nucleo-f072rb/CMakeLists.txt b/boards/arm/stm32f0l0g0/nucleo-f072rb/CMakeLists.txt deleted file mode 100644 index 03f3ea5a66588..0000000000000 --- a/boards/arm/stm32f0l0g0/nucleo-f072rb/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32f0l0g0/nucleo-f072rb/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32f0l0g0/nucleo-f072rb/configs/nsh/defconfig b/boards/arm/stm32f0l0g0/nucleo-f072rb/configs/nsh/defconfig deleted file mode 100644 index fe6bd5a96bce0..0000000000000 --- a/boards/arm/stm32f0l0g0/nucleo-f072rb/configs/nsh/defconfig +++ /dev/null @@ -1,59 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_FS_PROCFS_EXCLUDE_BLOCKS is not set -# CONFIG_FS_PROCFS_EXCLUDE_ENVIRON is not set -# CONFIG_FS_PROCFS_EXCLUDE_MEMDUMP is not set -# CONFIG_FS_PROCFS_EXCLUDE_MEMINFO is not set -# CONFIG_FS_PROCFS_EXCLUDE_MOUNT is not set -# CONFIG_FS_PROCFS_EXCLUDE_MOUNTS is not set -# CONFIG_FS_PROCFS_EXCLUDE_PROCESS is not set -# CONFIG_FS_PROCFS_EXCLUDE_UPTIME is not set -# CONFIG_FS_PROCFS_EXCLUDE_USAGE is not set -# CONFIG_FS_PROCFS_EXCLUDE_VERSION is not set -# CONFIG_NSH_DISABLEBG is not set -# CONFIG_NSH_DISABLE_EXEC is not set -# CONFIG_NSH_DISABLE_EXIT is not set -# CONFIG_NSH_DISABLE_HEXDUMP is not set -# CONFIG_NSH_DISABLE_XD is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="nucleo-f072rb" -CONFIG_ARCH_BOARD_NUCLEO_F072RB=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32f0l0g0" -CONFIG_ARCH_CHIP_STM32F072RB=y -CONFIG_ARCH_CHIP_STM32F0=y -CONFIG_ARCH_IRQBUTTONS=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=2796 -CONFIG_BUILTIN=y -CONFIG_DEFAULT_SMALL=y -CONFIG_FS_PROCFS=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INIT_STACKSIZE=1536 -CONFIG_MM_SMALL=y -CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=64 -CONFIG_NUNGET_CHARS=0 -CONFIG_POSIX_SPAWN_DEFAULT_STACKSIZE=1536 -CONFIG_PTHREAD_STACK_DEFAULT=1536 -CONFIG_RAM_SIZE=16384 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=19 -CONFIG_START_MONTH=5 -CONFIG_START_YEAR=2013 -CONFIG_STM32F0L0G0_PWR=y -CONFIG_STM32F0L0G0_USART2=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART2_RXBUFSIZE=32 -CONFIG_USART2_SERIAL_CONSOLE=y -CONFIG_USART2_TXBUFSIZE=32 diff --git a/boards/arm/stm32f0l0g0/nucleo-f072rb/include/board.h b/boards/arm/stm32f0l0g0/nucleo-f072rb/include/board.h deleted file mode 100644 index fc01e4546cb0c..0000000000000 --- a/boards/arm/stm32f0l0g0/nucleo-f072rb/include/board.h +++ /dev/null @@ -1,244 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-f072rb/include/board.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __BOARDS_ARM_STM32F0L0G0_NUCLEO_F072RB_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32F0L0G0_NUCLEO_F072RB_INCLUDE_BOARD_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#ifndef __ASSEMBLY__ -# include -#endif - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Clocking *****************************************************************/ - -/* Four different clock sources can be used to drive the system clock - * (SYSCLK): - * - * - HSI high-speed internal oscillator clock - * Generated from an internal 8 MHz RC oscillator - * - HSE high-speed external oscillator clock - * Normally driven by an external crystal (X3). However, this crystal is - * not fitted on the Nucleo-F072RB board. - * - PLL clock - * - MSI multispeed internal oscillator clock - * The MSI clock signal is generated from an internal RC oscillator. Seven - * frequency ranges are available: 65.536 kHz, 131.072 kHz, 262.144 kHz, - * 524.288 kHz, 1.048 MHz, 2.097 MHz (default value) and 4.194 MHz. - * - * The devices have the following two secondary clock sources - * - LSI low-speed internal RC clock - * Drives the watchdog and RTC. Approximately 37KHz - * - LSE low-speed external oscillator clock - * Driven by 32.768KHz crystal (X2) on the OSC32_IN and OSC32_OUT pins. - */ - -#define STM32_BOARD_XTAL 8000000ul /* X3 on board (not fitted)*/ - -#define STM32_HSI_FREQUENCY 8000000ul /* Approximately 8MHz */ -#define STM32_HSI14_FREQUENCY 14000000ul /* HSI14 for ADC */ -#define STM32_HSI48_FREQUENCY 48000000ul /* HSI48 for USB, only some STM32F0xx */ -#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL -#define STM32_LSI_FREQUENCY 40000 /* Approximately 40KHz */ -#define STM32_LSE_FREQUENCY 32768 /* X2 on board */ - -/* PLL Configuration - * - * - PLL source is HSI -> 8MHz input (nominal) - * - PLL source predivider 2 -> 4MHz divided down PLL VCO clock output - * - PLL multiplier is 12 -> 48MHz PLL VCO clock output (for USB) - * - * Resulting SYSCLK frequency is 8MHz x 12 / 2 = 48MHz - * - * USB: - * If the USB interface is used in the application, it requires a precise - * 48MHz clock which can be generated from either the (1) the internal - * main PLL with the HSE clock source using an HSE crystal oscillator. In - * this case, the PLL VCO clock (defined by STM32_CFGR_PLLMUL) must be - * programmed to output a 96 MHz frequency. This is required to provide a - * 48MHz clock to the (USBCLK = PLLVCO/2). Or (2) by using the internal - * 48MHz oscillator in automatic trimming mode. The synchronization for - * this oscillator can be taken from the USB data stream itself (SOF - * signalization) which allows crystal-less operation. - * SYSCLK - * The system clock is derived from the PLL VCO divided by the output - * division factor. - * Limitations: - * - 96 MHz as PLLVCO when the product is in range 1 (1.8V), - * - 48 MHz as PLLVCO when the product is in range 2 (1.5V), - * - 24 MHz when the product is in range 3 (1.2V). - * - Output division to avoid exceeding 32 MHz as SYSCLK. - * - The minimum input clock frequency for PLL is 2 MHz (when using HSE as - * PLL source). - */ - -#define STM32_CFGR_PLLSRC RCC_CFGR_PLLSRC_HSId2 /* Source is HSI/2 */ -#define STM32_PLLSRC_FREQUENCY (STM32_HSI_FREQUENCY/2) /* 8MHz / 2 = 4MHz */ -#ifdef CONFIG_STM32F0L0G0_USB -# undef STM32_CFGR2_PREDIV /* Not used with source HSI/2 */ -# define STM32_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx12 /* PLLMUL = 12 */ -# define STM32_PLL_FREQUENCY (12*STM32_PLLSRC_FREQUENCY) /* PLL VCO Frequency is 48MHz */ -#else -# undef STM32_CFGR2_PREDIV /* Not used with source HSI/2 */ -# define STM32_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx12 /* PLLMUL = 12 */ -# define STM32_PLL_FREQUENCY (12*STM32_PLLSRC_FREQUENCY) /* PLL VCO Frequency is 48MHz */ -#endif - -/* Use the PLL and set the SYSCLK source to be the divided down PLL VCO - * output frequency (STM32_PLL_FREQUENCY divided by the PLLDIV value). - */ - -#define STM32_SYSCLK_SW RCC_CFGR_SW_PLL /* Use the PLL as the SYSCLK */ -#define STM32_SYSCLK_SWS RCC_CFGR_SWS_PLL -#ifdef CONFIG_STM32F0L0G0_USB -# define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY /* SYSCLK frequency is PLL VCO = 48MHz */ -#else -# define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY /* SYSCLK frequency is PLL VCO = 48MHz */ -#endif - -#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK -#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY - -/* APB1 clock (PCLK1) is HCLK (48MHz) */ - -#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK -#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY) - -/* APB2 clock (PCLK2) is HCLK (48MHz) */ - -#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK -#define STM32_PCLK2_FREQUENCY STM32_HCLK_FREQUENCY -#define STM32_APB2_CLKIN (STM32_PCLK2_FREQUENCY) - -/* APB1 timers 1-3, 6-7, and 14-17 will receive PCLK1 */ - -#define STM32_APB1_TIM1_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM2_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (STM32_PCLK1_FREQUENCY) - -#define STM32_APB1_TIM6_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (STM32_PCLK1_FREQUENCY) - -#define STM32_APB1_TIM14_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM15_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM16_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM17_CLKIN (STM32_PCLK1_FREQUENCY) - -/* LED definitions **********************************************************/ - -/* LEDs - * - * The Nucleo-64 board has one user controllable LED, User LD2. This green - * LED is a user LED connected to Arduino signal D13 corresponding to STM32 - * I/O PA5 (PB13 on other some other Nucleo-64 boards). - * - * - When the I/O is HIGH value, the LED is on - * - When the I/O is LOW, the LED is off - */ - -/* LED index values for use with board_userled() */ - -#define BOARD_LD2 0 -#define BOARD_NLEDS 1 - -/* LED bits for use with board_userled_all() */ - -#define BOARD_LD2_BIT (1 << BOARD_LD2) - -/* These LEDs are not used by the board port unless CONFIG_ARCH_LEDS is - * defined. In that case, the usage by the board port is defined in - * include/board.h and src/sam_leds.c. The LEDs are used to encode OS-related - * events as follows when the red LED (PE24) is available: - * - * SYMBOL Meaning LD2 - * ------------------- ----------------------- ----------- - * LED_STARTED NuttX has been started OFF - * LED_HEAPALLOCATE Heap has been allocated OFF - * LED_IRQSENABLED Interrupts enabled OFF - * LED_STACKCREATED Idle stack created ON - * LED_INIRQ In an interrupt No change - * LED_SIGNAL In a signal handler No change - * LED_ASSERTION An assertion failed No change - * LED_PANIC The system has crashed Blinking - * LED_IDLE MCU is in sleep mode Not used - * - * Thus if LD2, NuttX has successfully booted and is, apparently, running - * normally. If LD2 is flashing at approximately 2Hz, then a fatal error - * has been detected and the system has halted. - */ - -#define LED_STARTED 0 -#define LED_HEAPALLOCATE 0 -#define LED_IRQSENABLED 0 -#define LED_STACKCREATED 1 -#define LED_INIRQ 2 -#define LED_SIGNAL 2 -#define LED_ASSERTION 2 -#define LED_PANIC 1 - -/* Button definitions *******************************************************/ - -/* Buttons - * - * B1 USER: the user button is connected to the I/O PC13 (pin 2) of the STM32 - * microcontroller. - */ - -#define BUTTON_USER 0 -#define NUM_BUTTONS 1 - -#define BUTTON_USER_BIT (1 << BUTTON_USER) - -/* Alternate Pin Functions **************************************************/ - -/* USART 1 - * PA9 - CN10 pin 21 - * PA10 - CN10 pin 33 - */ - -#define GPIO_USART1_TX (GPIO_USART1_TX_2|GPIO_SPEED_HIGH) /* PA9 */ -#define GPIO_USART1_RX (GPIO_USART1_RX_2|GPIO_SPEED_HIGH) /* PA10 */ - -/* USART 2 - St-Link VCOM */ - -#define GPIO_USART2_TX (GPIO_USART2_TX_3|GPIO_SPEED_HIGH) /* PA2 */ -#define GPIO_USART2_RX (GPIO_USART2_RX_3|GPIO_SPEED_HIGH) /* PA3 */ - -/* I2C1 - * PB8 - CN5 pin 10, D15 - * PB9 - CN5 pin 9, D14 - */ - -#define GPIO_I2C1_SCL (GPIO_I2C1_SCL_2|GPIO_SPEED_LOW) /* PB8 */ -#define GPIO_I2C1_SDA (GPIO_I2C1_SDA_2|GPIO_SPEED_LOW) /* PB9 */ - -/* I2C2 */ - -#endif /* __BOARDS_ARM_STM32F0L0G0_NUCLEO_F072RB_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32f0l0g0/nucleo-f072rb/scripts/Make.defs b/boards/arm/stm32f0l0g0/nucleo-f072rb/scripts/Make.defs deleted file mode 100644 index cb4dd0432323b..0000000000000 --- a/boards/arm/stm32f0l0g0/nucleo-f072rb/scripts/Make.defs +++ /dev/null @@ -1,41 +0,0 @@ -############################################################################ -# boards/arm/stm32f0l0g0/nucleo-f072rb/scripts/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/.config -include $(TOPDIR)/tools/Config.mk -include $(TOPDIR)/arch/arm/src/armv6-m/Toolchain.defs - -LDSCRIPT = flash.ld -ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) - -ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 - -CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) -CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) -CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -AFLAGS := $(CFLAGS) -D__ASSEMBLY__ - -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections -LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32f0l0g0/nucleo-f072rb/scripts/flash.ld b/boards/arm/stm32f0l0g0/nucleo-f072rb/scripts/flash.ld deleted file mode 100644 index 5e638ee249884..0000000000000 --- a/boards/arm/stm32f0l0g0/nucleo-f072rb/scripts/flash.ld +++ /dev/null @@ -1,111 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-f072rb/scripts/flash.ld - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* The STM32F072RBT6 has 128KB of FLASH beginning at address 0x0800:0000 and - * 16Kb of SRAM at address 0x20000000. - * - * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 - * where the code expects to begin execution by jumping to the entry point in - * the 0x0800:0000 address range. - */ - -MEMORY -{ - flash (rx) : ORIGIN = 0x08000000, LENGTH = 128K - sram (rwx) : ORIGIN = 0x20000000, LENGTH = 16K -} - -OUTPUT_ARCH(arm) -EXTERN(_vectors) -ENTRY(_stext) - -SECTIONS -{ - .text : - { - _stext = ABSOLUTE(.); - *(.vectors) - *(.text .text.*) - *(.fixup) - *(.gnu.warning) - *(.rodata .rodata.*) - *(.gnu.linkonce.t.*) - *(.glue_7) - *(.glue_7t) - *(.got) - *(.gcc_except_table) - *(.gnu.linkonce.r.*) - _etext = ABSOLUTE(.); - } > flash - - .init_section : ALIGN(4) { - _sinit = ABSOLUTE(.); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) - KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) - _einit = ABSOLUTE(.); - } > flash - - .ARM.extab ALIGN(4): { - *(.ARM.extab*) - } > flash - - .ARM.exidx : ALIGN(4) { - __exidx_start = ABSOLUTE(.); - *(.ARM.exidx*) - __exidx_end = ABSOLUTE(.); - } > flash - - _eronly = ABSOLUTE(.); - - .data : ALIGN(4) { - _sdata = ABSOLUTE(.); - *(.data .data.*) - *(.gnu.linkonce.d.*) - CONSTRUCTORS - . = ALIGN(4); - _edata = ABSOLUTE(.); - } > sram AT > flash - - .bss : ALIGN(4) { - _sbss = ABSOLUTE(.); - *(.bss .bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - . = ALIGN(8); - _ebss = ABSOLUTE(.); - } > sram - - /* Stabs debugging sections. */ - - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_info 0 : { *(.debug_info) } - .debug_line 0 : { *(.debug_line) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_aranges 0 : { *(.debug_aranges) } -} diff --git a/boards/arm/stm32f0l0g0/nucleo-f072rb/src/CMakeLists.txt b/boards/arm/stm32f0l0g0/nucleo-f072rb/src/CMakeLists.txt deleted file mode 100644 index 16d4ed14c1224..0000000000000 --- a/boards/arm/stm32f0l0g0/nucleo-f072rb/src/CMakeLists.txt +++ /dev/null @@ -1,37 +0,0 @@ -# ############################################################################## -# boards/arm/stm32f0l0g0/nucleo-f072rb/src/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -set(SRCS stm32_boot.c stm32_bringup.c) - -if(CONFIG_ARCH_LEDS) - list(APPEND SRCS stm32_autoleds.c) -else() - list(APPEND SRCS stm32_userleds.c) -endif() - -if(CONFIG_ARCH_BUTTONS) - list(APPEND SRCS stm32_buttons.c) -endif() - -target_sources(board PRIVATE ${SRCS}) - -set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/flash.ld") diff --git a/boards/arm/stm32f0l0g0/nucleo-f072rb/src/Make.defs b/boards/arm/stm32f0l0g0/nucleo-f072rb/src/Make.defs deleted file mode 100644 index 27aae3fb3b131..0000000000000 --- a/boards/arm/stm32f0l0g0/nucleo-f072rb/src/Make.defs +++ /dev/null @@ -1,39 +0,0 @@ -############################################################################ -# boards/arm/stm32f0l0g0/nucleo-f072rb/src/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/Make.defs - -CSRCS = stm32_boot.c stm32_bringup.c - -ifeq ($(CONFIG_ARCH_LEDS),y) -CSRCS += stm32_autoleds.c -else -CSRCS += stm32_userleds.c -endif - -ifeq ($(CONFIG_ARCH_BUTTONS),y) -CSRCS += stm32_buttons.c -endif - -DEPPATH += --dep-path board -VPATH += :board -CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32f0l0g0/nucleo-f072rb/src/stm32_autoleds.c b/boards/arm/stm32f0l0g0/nucleo-f072rb/src/stm32_autoleds.c deleted file mode 100644 index 2738e92b21dca..0000000000000 --- a/boards/arm/stm32f0l0g0/nucleo-f072rb/src/stm32_autoleds.c +++ /dev/null @@ -1,82 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-f072rb/src/stm32_autoleds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32_gpio.h" -#include "nucleo-f072rb.h" - -#ifdef CONFIG_ARCH_LEDS - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_autoled_initialize - ****************************************************************************/ - -void board_autoled_initialize(void) -{ - /* Configure LD2 GPIO for output */ - - stm32_configgpio(GPIO_LD2); -} - -/**************************************************************************** - * Name: board_autoled_on - ****************************************************************************/ - -void board_autoled_on(int led) -{ - if (led == 1) - { - stm32_gpiowrite(GPIO_LD2, true); - } -} - -/**************************************************************************** - * Name: board_autoled_off - ****************************************************************************/ - -void board_autoled_off(int led) -{ - if (led == 1) - { - stm32_gpiowrite(GPIO_LD2, false); - } -} - -#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32f0l0g0/nucleo-f072rb/src/stm32_boot.c b/boards/arm/stm32f0l0g0/nucleo-f072rb/src/stm32_boot.c deleted file mode 100644 index fb79ff4c3a4cf..0000000000000 --- a/boards/arm/stm32f0l0g0/nucleo-f072rb/src/stm32_boot.c +++ /dev/null @@ -1,81 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-f072rb/src/stm32_boot.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include -#include - -#include "arm_internal.h" -#include "nucleo-f072rb.h" - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_boardinitialize - * - * Description: - * All STM32 architectures must provide the following entry point. - * This entry point is called early in the initialization -- after all - * memory has been configured and mapped but before any devices have been - * initialized. - * - ****************************************************************************/ - -void stm32_boardinitialize(void) -{ -#ifdef CONFIG_ARCH_LEDS - /* Configure on-board LEDs if LED support has been selected. */ - - board_autoled_initialize(); -#endif -} - -/**************************************************************************** - * Name: board_late_initialize - * - * Description: - * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional - * initialization call will be performed in the boot-up sequence to a - * function called board_late_initialize(). board_late_initialize() will be - * called immediately after up_initialize() is called and just before the - * initial application is started. This additional initialization phase - * may be used, for example, to initialize board-specific device drivers. - * - ****************************************************************************/ - -#ifdef CONFIG_BOARD_LATE_INITIALIZE -void board_late_initialize(void) -{ - /* Perform board-specific initialization here if so configured */ - - stm32_bringup(); -} -#endif diff --git a/boards/arm/stm32f0l0g0/nucleo-f072rb/src/stm32_bringup.c b/boards/arm/stm32f0l0g0/nucleo-f072rb/src/stm32_bringup.c deleted file mode 100644 index b742e7e62ecf6..0000000000000 --- a/boards/arm/stm32f0l0g0/nucleo-f072rb/src/stm32_bringup.c +++ /dev/null @@ -1,101 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-f072rb/src/stm32_bringup.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include - -#include "stm32_i2c.h" -#include "nucleo-f072rb.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#undef HAVE_I2C_DRIVER -#if defined(CONFIG_STM32F0L0G0_I2C1) && defined(CONFIG_I2C_DRIVER) -# define HAVE_I2C_DRIVER 1 -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_bringup - * - * Description: - * Perform architecture-specific initialization - * - * CONFIG_BOARD_LATE_INITIALIZE=y : - * Called from board_late_initialize(). - * - ****************************************************************************/ - -int stm32_bringup(void) -{ -#ifdef HAVE_I2C_DRIVER - struct i2c_master_s *i2c; -#endif - int ret; - -#ifdef CONFIG_FS_PROCFS - /* Mount the procfs file system */ - - ret = nx_mount(NULL, "/proc", "procfs", 0, NULL); - if (ret < 0) - { - ferr("ERROR: Failed to mount procfs at /proc: %d\n", ret); - } -#endif - -#ifdef HAVE_I2C_DRIVER - /* Get the I2C lower half instance */ - - i2c = stm32_i2cbus_initialize(1); - if (i2c == NULL) - { - i2cerr("ERROR: Initialize I2C1: %d\n", ret); - } - else - { - /* Register the I2C character driver */ - - ret = i2c_register(i2c, 1); - if (ret < 0) - { - i2cerr("ERROR: Failed to register I2C1 device: %d\n", ret); - } - } -#endif - - UNUSED(ret); - return OK; -} diff --git a/boards/arm/stm32f0l0g0/nucleo-f072rb/src/stm32_buttons.c b/boards/arm/stm32f0l0g0/nucleo-f072rb/src/stm32_buttons.c deleted file mode 100644 index 246f6a7a98e69..0000000000000 --- a/boards/arm/stm32f0l0g0/nucleo-f072rb/src/stm32_buttons.c +++ /dev/null @@ -1,117 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-f072rb/src/stm32_buttons.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include -#include - -#include "stm32_gpio.h" -#include "nucleo-f072rb.h" - -#ifdef CONFIG_ARCH_BUTTONS - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_button_initialize - * - * Description: - * board_button_initialize() must be called to initialize button resources. - * After that, board_buttons() may be called to collect the current state - * of all buttons or board_button_irq() may be called to register button - * interrupt handlers. - * - ****************************************************************************/ - -uint32_t board_button_initialize(void) -{ - /* Configure the single button as an input. NOTE that EXTI interrupts are - * also configured for the pin. - */ - - stm32_configgpio(GPIO_BTN_USER); - return NUM_BUTTONS; -} - -/**************************************************************************** - * Name: board_buttons - ****************************************************************************/ - -uint32_t board_buttons(void) -{ - /* Check that state of each USER button. A LOW value means that the key is - * pressed. - */ - - bool released = stm32_gpioread(GPIO_BTN_USER); - return !released; -} - -/**************************************************************************** - * Button support. - * - * Description: - * board_button_initialize() must be called to initialize button resources. - * After that, board_buttons() may be called to collect the current state - * of all buttons or board_button_irq() may be called to register button - * interrupt handlers. - * - * After board_button_initialize() has been called, board_buttons() may be - * called to collect the state of all buttons. board_buttons() returns an - * 32-bit bit set with each bit associated with a button. See the - * BUTTON_*_BIT definitions in board.h for the meaning of each bit. - * - * board_button_irq() may be called to register an interrupt handler that - * will be called when a button is depressed or released. The ID value is a - * button enumeration value that uniquely identifies a button resource. See - * the BUTTON_* definitions in board.h for the meaning of enumeration - * value. - * - ****************************************************************************/ - -#ifdef CONFIG_ARCH_IRQBUTTONS -int board_button_irq(int id, xcpt_t irqhandler, void *arg) -{ - int ret = -EINVAL; - - if (id == BUTTON_USER) - { - ret = stm32_gpiosetevent(GPIO_BTN_USER, true, true, true, - irqhandler, arg); - } - - return ret; -} -#endif -#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/stm32f0l0g0/nucleo-f072rb/src/stm32_userleds.c b/boards/arm/stm32f0l0g0/nucleo-f072rb/src/stm32_userleds.c deleted file mode 100644 index a64c333c331a4..0000000000000 --- a/boards/arm/stm32f0l0g0/nucleo-f072rb/src/stm32_userleds.c +++ /dev/null @@ -1,197 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-f072rb/src/stm32_userleds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include - -#include -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32_gpio.h" -#include "nucleo-f072rb.h" - -#ifndef CONFIG_ARCH_LEDS - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -/* LED Power Management */ - -#ifdef CONFIG_PM -static void led_pm_notify(struct pm_callback_s *cb, int domain, - enum pm_state_e pmstate); -static int led_pm_prepare(struct pm_callback_s *cb, int domain, - enum pm_state_e pmstate); -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -#ifdef CONFIG_PM -static struct pm_callback_s g_ledscb = -{ - .notify = led_pm_notify, - .prepare = led_pm_prepare, -}; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: led_pm_notify - * - * Description: - * Notify the driver of new power state. This callback is called after - * all drivers have had the opportunity to prepare for the new power state. - * - ****************************************************************************/ - -#ifdef CONFIG_PM -static void led_pm_notify(struct pm_callback_s *cb, int domain, - enum pm_state_e pmstate) -{ - switch (pmstate) - { - case PM_NORMAL: - { - /* Restore normal LEDs operation */ - } - break; - - case PM_IDLE: - { - /* Entering IDLE mode - Turn leds off */ - } - break; - - case PM_STANDBY: - { - /* Entering STANDBY mode - Logic for PM_STANDBY goes here */ - } - break; - - case PM_SLEEP: - { - /* Entering SLEEP mode - Logic for PM_SLEEP goes here */ - } - break; - - default: - { - /* Should not get here */ - } - break; - } -} -#endif - -/**************************************************************************** - * Name: led_pm_prepare - * - * Description: - * Request the driver to prepare for a new power state. This is a warning - * that the system is about to enter into a new power state. The driver - * should begin whatever operations that may be required to enter power - * state. The driver may abort the state change mode by returning a - * non-zero value from the callback function. - * - ****************************************************************************/ - -#ifdef CONFIG_PM -static int led_pm_prepare(struct pm_callback_s *cb, int domain, - enum pm_state_e pmstate) -{ - /* No preparation to change power modes is required by the LEDs driver. - * We always accept the state change by returning OK. - */ - - return OK; -} -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_userled_initialize - ****************************************************************************/ - -uint32_t board_userled_initialize(void) -{ - /* Configure LD2 GPIO for output */ - - stm32_configgpio(GPIO_LD2); - return BOARD_NLEDS; -} - -/**************************************************************************** - * Name: board_userled - ****************************************************************************/ - -void board_userled(int led, bool ledon) -{ - if (led == BOARD_LD2) - { - stm32_gpiowrite(GPIO_LD2, ledon); - } -} - -/**************************************************************************** - * Name: board_userled_all - ****************************************************************************/ - -void board_userled_all(uint32_t ledset) -{ - stm32_gpiowrite(GPIO_LD2, (ledset & BOARD_LD2_BIT) != 0); -} - -/**************************************************************************** - * Name: stm32_led_pminitialize - ****************************************************************************/ - -#ifdef CONFIG_PM -void stm32_led_pminitialize(void) -{ - /* Register to receive power management callbacks */ - - int ret = pm_register(&g_ledscb); - DEBUGASSERT(ret == OK); - UNUSED(ret); -} -#endif /* CONFIG_PM */ - -#endif /* !CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32f0l0g0/nucleo-f091rc/CMakeLists.txt b/boards/arm/stm32f0l0g0/nucleo-f091rc/CMakeLists.txt deleted file mode 100644 index a9ce71ece553b..0000000000000 --- a/boards/arm/stm32f0l0g0/nucleo-f091rc/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32f0l0g0/nucleo-f091rc/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32f0l0g0/nucleo-f091rc/configs/nsh/defconfig b/boards/arm/stm32f0l0g0/nucleo-f091rc/configs/nsh/defconfig deleted file mode 100644 index 039c992186b98..0000000000000 --- a/boards/arm/stm32f0l0g0/nucleo-f091rc/configs/nsh/defconfig +++ /dev/null @@ -1,59 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_FS_PROCFS_EXCLUDE_BLOCKS is not set -# CONFIG_FS_PROCFS_EXCLUDE_ENVIRON is not set -# CONFIG_FS_PROCFS_EXCLUDE_MEMDUMP is not set -# CONFIG_FS_PROCFS_EXCLUDE_MEMINFO is not set -# CONFIG_FS_PROCFS_EXCLUDE_MOUNT is not set -# CONFIG_FS_PROCFS_EXCLUDE_MOUNTS is not set -# CONFIG_FS_PROCFS_EXCLUDE_PROCESS is not set -# CONFIG_FS_PROCFS_EXCLUDE_UPTIME is not set -# CONFIG_FS_PROCFS_EXCLUDE_USAGE is not set -# CONFIG_FS_PROCFS_EXCLUDE_VERSION is not set -# CONFIG_NSH_DISABLEBG is not set -# CONFIG_NSH_DISABLE_EXEC is not set -# CONFIG_NSH_DISABLE_EXIT is not set -# CONFIG_NSH_DISABLE_HEXDUMP is not set -# CONFIG_NSH_DISABLE_XD is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="nucleo-f091rc" -CONFIG_ARCH_BOARD_NUCLEO_F091RC=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32f0l0g0" -CONFIG_ARCH_CHIP_STM32F091RC=y -CONFIG_ARCH_CHIP_STM32F0=y -CONFIG_ARCH_IRQBUTTONS=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=2796 -CONFIG_BUILTIN=y -CONFIG_DEBUG_FULLOPT=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_DEFAULT_SMALL=y -CONFIG_FS_PROCFS=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INIT_STACKSIZE=1536 -CONFIG_MM_SMALL=y -CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=64 -CONFIG_NUNGET_CHARS=0 -CONFIG_POSIX_SPAWN_DEFAULT_STACKSIZE=1536 -CONFIG_PTHREAD_STACK_DEFAULT=1536 -CONFIG_RAM_SIZE=32768 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=19 -CONFIG_START_MONTH=5 -CONFIG_START_YEAR=2013 -CONFIG_STM32F0L0G0_PWR=y -CONFIG_STM32F0L0G0_USART2=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f0l0g0/nucleo-f091rc/configs/sx127x/defconfig b/boards/arm/stm32f0l0g0/nucleo-f091rc/configs/sx127x/defconfig deleted file mode 100644 index 6637887a09c0c..0000000000000 --- a/boards/arm/stm32f0l0g0/nucleo-f091rc/configs/sx127x/defconfig +++ /dev/null @@ -1,61 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_NSH_ARGCAT is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="nucleo-f091rc" -CONFIG_ARCH_BOARD_NUCLEO_F091RC=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32f0l0g0" -CONFIG_ARCH_CHIP_STM32F091RC=y -CONFIG_ARCH_CHIP_STM32F0=y -CONFIG_ARCH_IRQBUTTONS=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=2796 -CONFIG_BUILTIN=y -CONFIG_DISABLE_ENVIRON=y -CONFIG_DISABLE_MOUNTPOINT=y -CONFIG_DISABLE_MQUEUE=y -CONFIG_DISABLE_POSIX_TIMERS=y -CONFIG_DISABLE_PSEUDOFS_OPERATIONS=y -CONFIG_DRIVERS_LPWAN=y -CONFIG_DRIVERS_WIRELESS=y -CONFIG_EXAMPLES_HELLO=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INIT_STACKSIZE=1536 -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_LPWAN_SX127X=y -CONFIG_LPWAN_SX127X_FSKOOK=y -CONFIG_LPWAN_SX127X_MODULATION_DEFAULT=1 -CONFIG_LPWAN_SX127X_RXSUPPORT=y -CONFIG_LPWAN_SX127X_TXSUPPORT=y -CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=64 -CONFIG_NSH_READLINE=y -CONFIG_NUNGET_CHARS=0 -CONFIG_POSIX_SPAWN_DEFAULT_STACKSIZE=1536 -CONFIG_PTHREAD_MUTEX_UNSAFE=y -CONFIG_PTHREAD_STACK_DEFAULT=1536 -CONFIG_RAM_SIZE=20480 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_WAITPID=y -CONFIG_STACK_COLORATION=y -CONFIG_START_DAY=19 -CONFIG_START_MONTH=5 -CONFIG_START_YEAR=2013 -CONFIG_STDIO_DISABLE_BUFFERING=y -CONFIG_STM32F0L0G0_PWR=y -CONFIG_STM32F0L0G0_SPI1=y -CONFIG_STM32F0L0G0_USART2=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f0l0g0/nucleo-f091rc/include/board.h b/boards/arm/stm32f0l0g0/nucleo-f091rc/include/board.h deleted file mode 100644 index 8c99f86513f12..0000000000000 --- a/boards/arm/stm32f0l0g0/nucleo-f091rc/include/board.h +++ /dev/null @@ -1,245 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-f091rc/include/board.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __BOARDS_ARM_STM32F0L0G0_NUCLEO_F091RC_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32F0L0G0_NUCLEO_F091RC_INCLUDE_BOARD_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#ifndef __ASSEMBLY__ -# include -#endif - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Clocking *****************************************************************/ - -/* Four different clock sources can be used to drive the system clock - * (SYSCLK): - * - * - HSI high-speed internal oscillator clock - * Generated from an internal 8 MHz RC oscillator - * - HSE high-speed external oscillator clock - * Normally driven by an external crystal (X3). However, this crystal is - * not fitted on the Nucleo-F091RC board. - * - PLL clock - * - MSI multispeed internal oscillator clock - * The MSI clock signal is generated from an internal RC oscillator. Seven - * frequency ranges are available: 65.536 kHz, 131.072 kHz, 262.144 kHz, - * 524.288 kHz, 1.048 MHz, 2.097 MHz (default value) and 4.194 MHz. - * - * The devices have the following two secondary clock sources - * - LSI low-speed internal RC clock - * Drives the watchdog and RTC. Approximately 37KHz - * - LSE low-speed external oscillator clock - * Driven by 32.768KHz crystal (X2) on the OSC32_IN and OSC32_OUT pins. - */ - -#define STM32_BOARD_XTAL 8000000ul /* X3 on board (not fitted)*/ - -#define STM32_HSI_FREQUENCY 8000000ul /* Approximately 8MHz */ -#define STM32_HSI14_FREQUENCY 14000000ul /* HSI14 for ADC */ -#define STM32_HSI48_FREQUENCY 48000000ul /* HSI48 for USB, only some STM32F0xx */ -#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL -#define STM32_LSI_FREQUENCY 40000 /* Approximately 40KHz */ -#define STM32_LSE_FREQUENCY 32768 /* X2 on board */ - -/* PLL Configuration - * - * - PLL source is HSI -> 8MHz input (nominal) - * - PLL source predivider 2 -> 4MHz divided down PLL VCO clock output - * - PLL multiplier is 12 -> 48MHz PLL VCO clock output (for USB) - * - * Resulting SYSCLK frequency is 8MHz x 12 / 2 = 48MHz - * - * USB: - * If the USB interface is used in the application, it requires a precise - * 48MHz clock which can be generated from either the (1) the internal - * main PLL with the HSE clock source using an HSE crystal oscillator. In - * this case, the PLL VCO clock (defined by STM32_CFGR_PLLMUL) must be - * programmed to output a 96 MHz frequency. This is required to provide a - * 48MHz clock to the (USBCLK = PLLVCO/2). Or (2) by using the internal - * 48MHz oscillator in automatic trimming mode. The synchronization for - * this oscillator can be taken from the USB data stream itself (SOF - * signalization) which allows crystal-less operation. - * SYSCLK - * The system clock is derived from the PLL VCO divided by the output - * division factor. - * Limitations: - * - 96 MHz as PLLVCO when the product is in range 1 (1.8V), - * - 48 MHz as PLLVCO when the product is in range 2 (1.5V), - * - 24 MHz when the product is in range 3 (1.2V). - * - Output division to avoid exceeding 32 MHz as SYSCLK. - * - The minimum input clock frequency for PLL is 2 MHz (when using HSE as - * PLL source). - */ - -#define STM32_CFGR_PLLSRC RCC_CFGR_PLLSRC_HSId2 /* Source is HSI/2 */ -#define STM32_PLLSRC_FREQUENCY (STM32_HSI_FREQUENCY/2) /* 8MHz / 2 = 4MHz */ -#ifdef CONFIG_STM32F0L0G0_USB -# undef STM32_CFGR2_PREDIV /* Not used with source HSI/2 */ -# define STM32_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx12 /* PLLMUL = 12 */ -# define STM32_PLL_FREQUENCY (12*STM32_PLLSRC_FREQUENCY) /* PLL VCO Frequency is 48MHz */ -#else -# undef STM32_CFGR2_PREDIV /* Not used with source HSI/2 */ -# define STM32_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx12 /* PLLMUL = 12 */ -# define STM32_PLL_FREQUENCY (12*STM32_PLLSRC_FREQUENCY) /* PLL VCO Frequency is 48MHz */ -#endif - -/* Use the PLL and set the SYSCLK source to be the divided down PLL VCO - * output frequency (STM32_PLL_FREQUENCY divided by the PLLDIV value). - */ - -#define STM32_SYSCLK_SW RCC_CFGR_SW_PLL /* Use the PLL as the SYSCLK */ -#define STM32_SYSCLK_SWS RCC_CFGR_SWS_PLL -#ifdef CONFIG_STM32F0L0G0_USB -# define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY /* SYSCLK frequency is PLL VCO = 48MHz */ -#else -# define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY /* SYSCLK frequency is PLL VCO = 48MHz */ -#endif - -#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK -#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY - -/* APB1 clock (PCLK1) is HCLK (48MHz) */ - -#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK -#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY) - -/* APB2 clock (PCLK2) is HCLK (48MHz) */ - -#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK -#define STM32_PCLK2_FREQUENCY STM32_HCLK_FREQUENCY -#define STM32_APB2_CLKIN (STM32_PCLK2_FREQUENCY) - -/* APB1 timers 1-3, 6-7, and 14-17 will receive PCLK1 */ - -#define STM32_APB1_TIM1_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM2_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (STM32_PCLK1_FREQUENCY) - -#define STM32_APB1_TIM6_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (STM32_PCLK1_FREQUENCY) - -#define STM32_APB1_TIM14_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM15_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM16_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM17_CLKIN (STM32_PCLK1_FREQUENCY) - -/* LED definitions **********************************************************/ - -/* LEDs - * - * The Nucleo-64 board has one user controllable LED, User LD2. This green - * LED is a user LED connected to Arduino signal D13 corresponding to STM32 - * I/O PA5 (PB13 on other some other Nucleo-64 boards). - * - * - When the I/O is HIGH value, the LED is on - * - When the I/O is LOW, the LED is off - */ - -/* LED index values for use with board_userled() */ - -#define BOARD_LD2 0 -#define BOARD_NLEDS 1 - -/* LED bits for use with board_userled_all() */ - -#define BOARD_LD2_BIT (1 << BOARD_LD2) - -/* These LEDs are not used by the board port unless CONFIG_ARCH_LEDS is - * defined. In that case, the usage by the board port is defined in - * include/board.h and src/sam_leds.c. The LEDs are used to encode OS-related - * events as follows when the red LED (PE24) is available: - * - * SYMBOL Meaning LD2 - * ------------------- ----------------------- ----------- - * LED_STARTED NuttX has been started OFF - * LED_HEAPALLOCATE Heap has been allocated OFF - * LED_IRQSENABLED Interrupts enabled OFF - * LED_STACKCREATED Idle stack created ON - * LED_INIRQ In an interrupt No change - * LED_SIGNAL In a signal handler No change - * LED_ASSERTION An assertion failed No change - * LED_PANIC The system has crashed Blinking - * LED_IDLE MCU is in sleep mode Not used - * - * Thus if LD2, NuttX has successfully booted and is, apparently, running - * normally. If LD2 is flashing at approximately 2Hz, then a fatal error - * has been detected and the system has halted. - */ - -#define LED_STARTED 0 -#define LED_HEAPALLOCATE 0 -#define LED_IRQSENABLED 0 -#define LED_STACKCREATED 1 -#define LED_INIRQ 2 -#define LED_SIGNAL 2 -#define LED_ASSERTION 2 -#define LED_PANIC 1 - -/* Button definitions *******************************************************/ - -/* Buttons - * - * B1 USER: the user button is connected to the I/O PC13 (pin 2) of the STM32 - * microcontroller. - */ - -#define BUTTON_USER 0 -#define NUM_BUTTONS 1 - -#define BUTTON_USER_BIT (1 << BUTTON_USER) - -/* Alternate Pin Functions **************************************************/ - -/* I2C - * PB8 - D15 - * PB9 - D14 - */ - -#define GPIO_I2C1_SCL (GPIO_I2C1_SCL_2|GPIO_SPEED_LOW) /* PB8 */ -#define GPIO_I2C1_SDA (GPIO_I2C1_SDA_2|GPIO_SPEED_LOW) /* PB9 */ - -/* SPI */ - -#define GPIO_SPI1_MISO (GPIO_SPI1_MISO_1|GPIO_SPEED_MEDIUM) /* D12 - PA6 */ -#define GPIO_SPI1_MOSI (GPIO_SPI1_MOSI_1|GPIO_SPEED_MEDIUM) /* D11 - PA7 */ -#define GPIO_SPI1_SCK (GPIO_SPI1_SCK_1|GPIO_SPEED_MEDIUM) /* D13 - PA5 */ - -/* USART 1 */ - -#define GPIO_USART1_TX (GPIO_USART1_TX_2|GPIO_SPEED_HIGH) /* PA9 */ -#define GPIO_USART1_RX (GPIO_USART1_RX_2|GPIO_SPEED_HIGH) /* PA10 */ - -/* USART 2 */ - -#define GPIO_USART2_TX (GPIO_USART2_TX_3|GPIO_SPEED_HIGH) /* PA2 */ -#define GPIO_USART2_RX (GPIO_USART2_RX_3|GPIO_SPEED_HIGH) /* PA3 */ - -#endif /* __BOARDS_ARM_STM32F0L0G0_NUCLEO_F091RC_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32f0l0g0/nucleo-f091rc/scripts/Make.defs b/boards/arm/stm32f0l0g0/nucleo-f091rc/scripts/Make.defs deleted file mode 100644 index 0ee77f57b23f8..0000000000000 --- a/boards/arm/stm32f0l0g0/nucleo-f091rc/scripts/Make.defs +++ /dev/null @@ -1,41 +0,0 @@ -############################################################################ -# boards/arm/stm32f0l0g0/nucleo-f091rc/scripts/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/.config -include $(TOPDIR)/tools/Config.mk -include $(TOPDIR)/arch/arm/src/armv6-m/Toolchain.defs - -LDSCRIPT = flash.ld -ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) - -ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 - -CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) -CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) -CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -AFLAGS := $(CFLAGS) -D__ASSEMBLY__ - -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections -LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32f0l0g0/nucleo-f091rc/scripts/flash.ld b/boards/arm/stm32f0l0g0/nucleo-f091rc/scripts/flash.ld deleted file mode 100644 index 4965225b11270..0000000000000 --- a/boards/arm/stm32f0l0g0/nucleo-f091rc/scripts/flash.ld +++ /dev/null @@ -1,111 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-f091rc/scripts/flash.ld - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* The STM32F091RCT6 has 256Kb of FLASH beginning at address 0x0800:0000 and - * 32Kb of SRAM at address 0x20000000. - * - * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 - * where the code expects to begin execution by jumping to the entry point in - * the 0x0800:0000 address range. - */ - -MEMORY -{ - flash (rx) : ORIGIN = 0x08000000, LENGTH = 256K - sram (rwx) : ORIGIN = 0x20000000, LENGTH = 32K -} - -OUTPUT_ARCH(arm) -EXTERN(_vectors) -ENTRY(_stext) - -SECTIONS -{ - .text : - { - _stext = ABSOLUTE(.); - *(.vectors) - *(.text .text.*) - *(.fixup) - *(.gnu.warning) - *(.rodata .rodata.*) - *(.gnu.linkonce.t.*) - *(.glue_7) - *(.glue_7t) - *(.got) - *(.gcc_except_table) - *(.gnu.linkonce.r.*) - _etext = ABSOLUTE(.); - } > flash - - .init_section : ALIGN(4) { - _sinit = ABSOLUTE(.); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) - KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) - _einit = ABSOLUTE(.); - } > flash - - .ARM.extab ALIGN(4): { - *(.ARM.extab*) - } > flash - - .ARM.exidx : ALIGN(4) { - __exidx_start = ABSOLUTE(.); - *(.ARM.exidx*) - __exidx_end = ABSOLUTE(.); - } > flash - - _eronly = ABSOLUTE(.); - - .data : ALIGN(4) { - _sdata = ABSOLUTE(.); - *(.data .data.*) - *(.gnu.linkonce.d.*) - CONSTRUCTORS - . = ALIGN(4); - _edata = ABSOLUTE(.); - } > sram AT > flash - - .bss : ALIGN(4) { - _sbss = ABSOLUTE(.); - *(.bss .bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - . = ALIGN(8); - _ebss = ABSOLUTE(.); - } > sram - - /* Stabs debugging sections. */ - - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_info 0 : { *(.debug_info) } - .debug_line 0 : { *(.debug_line) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_aranges 0 : { *(.debug_aranges) } -} diff --git a/boards/arm/stm32f0l0g0/nucleo-f091rc/src/CMakeLists.txt b/boards/arm/stm32f0l0g0/nucleo-f091rc/src/CMakeLists.txt deleted file mode 100644 index bfafa31ee78a0..0000000000000 --- a/boards/arm/stm32f0l0g0/nucleo-f091rc/src/CMakeLists.txt +++ /dev/null @@ -1,45 +0,0 @@ -# ############################################################################## -# boards/arm/stm32f0l0g0/nucleo-f091rc/src/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -set(SRCS stm32_boot.c stm32_bringup.c) - -if(CONFIG_ARCH_LEDS) - list(APPEND SRCS stm32_autoleds.c) -else() - list(APPEND SRCS stm32_userleds.c) -endif() - -if(CONFIG_ARCH_BUTTONS) - list(APPEND SRCS stm32_buttons.c) -endif() - -if(CONFIG_STM32F0L0G0_SPI) - list(APPEND SRCS stm32_spi.c) -endif() - -if(CONFIG_LPWAN_SX127X) - list(APPEND SRCS stm32_sx127x.c) -endif() - -target_sources(board PRIVATE ${SRCS}) - -set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/flash.ld") diff --git a/boards/arm/stm32f0l0g0/nucleo-f091rc/src/Make.defs b/boards/arm/stm32f0l0g0/nucleo-f091rc/src/Make.defs deleted file mode 100644 index b455d3605ef0e..0000000000000 --- a/boards/arm/stm32f0l0g0/nucleo-f091rc/src/Make.defs +++ /dev/null @@ -1,47 +0,0 @@ -############################################################################ -# boards/arm/stm32f0l0g0/nucleo-f091rc/src/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/Make.defs - -CSRCS = stm32_boot.c stm32_bringup.c - -ifeq ($(CONFIG_ARCH_LEDS),y) -CSRCS += stm32_autoleds.c -else -CSRCS += stm32_userleds.c -endif - -ifeq ($(CONFIG_ARCH_BUTTONS),y) -CSRCS += stm32_buttons.c -endif - -ifeq ($(CONFIG_STM32F0L0G0_SPI),y) -CSRCS += stm32_spi.c -endif - -ifeq ($(CONFIG_LPWAN_SX127X),y) -CSRCS += stm32_sx127x.c -endif - -DEPPATH += --dep-path board -VPATH += :board -CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32f0l0g0/nucleo-f091rc/src/stm32_autoleds.c b/boards/arm/stm32f0l0g0/nucleo-f091rc/src/stm32_autoleds.c deleted file mode 100644 index 6462ab5c8136b..0000000000000 --- a/boards/arm/stm32f0l0g0/nucleo-f091rc/src/stm32_autoleds.c +++ /dev/null @@ -1,82 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-f091rc/src/stm32_autoleds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32_gpio.h" -#include "nucleo-f091rc.h" - -#ifdef CONFIG_ARCH_LEDS - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_autoled_initialize - ****************************************************************************/ - -void board_autoled_initialize(void) -{ - /* Configure LD2 GPIO for output */ - - stm32_configgpio(GPIO_LD2); -} - -/**************************************************************************** - * Name: board_autoled_on - ****************************************************************************/ - -void board_autoled_on(int led) -{ - if (led == 1) - { - stm32_gpiowrite(GPIO_LD2, true); - } -} - -/**************************************************************************** - * Name: board_autoled_off - ****************************************************************************/ - -void board_autoled_off(int led) -{ - if (led == 1) - { - stm32_gpiowrite(GPIO_LD2, false); - } -} - -#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32f0l0g0/nucleo-f091rc/src/stm32_boot.c b/boards/arm/stm32f0l0g0/nucleo-f091rc/src/stm32_boot.c deleted file mode 100644 index 3c92121c7d10d..0000000000000 --- a/boards/arm/stm32f0l0g0/nucleo-f091rc/src/stm32_boot.c +++ /dev/null @@ -1,87 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-f091rc/src/stm32_boot.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include -#include - -#include "arm_internal.h" -#include "nucleo-f091rc.h" - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_boardinitialize - * - * Description: - * All STM32 architectures must provide the following entry point. - * This entry point is called early in the initialization -- after all - * memory has been configured and mapped but before any devices have been - * initialized. - * - ****************************************************************************/ - -void stm32_boardinitialize(void) -{ -#ifdef CONFIG_ARCH_LEDS - /* Configure on-board LEDs if LED support has been selected. */ - - board_autoled_initialize(); -#endif - -#ifdef CONFIG_STM32F0L0G0_SPI - /* Configure SPI chip selects */ - - stm32_spidev_initialize(); -#endif -} - -/**************************************************************************** - * Name: board_late_initialize - * - * Description: - * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional - * initialization call will be performed in the boot-up sequence to a - * function called board_late_initialize(). board_late_initialize() will be - * called immediately after up_initialize() is called and just before the - * initial application is started. This additional initialization phase - * may be used, for example, to initialize board-specific device drivers. - * - ****************************************************************************/ - -#ifdef CONFIG_BOARD_LATE_INITIALIZE -void board_late_initialize(void) -{ - /* Perform board-specific initialization here if so configured */ - - stm32_bringup(); -} -#endif diff --git a/boards/arm/stm32f0l0g0/nucleo-f091rc/src/stm32_bringup.c b/boards/arm/stm32f0l0g0/nucleo-f091rc/src/stm32_bringup.c deleted file mode 100644 index 02697f3f88848..0000000000000 --- a/boards/arm/stm32f0l0g0/nucleo-f091rc/src/stm32_bringup.c +++ /dev/null @@ -1,76 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-f091rc/src/stm32_bringup.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include - -#include "nucleo-f091rc.h" - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_bringup - * - * Description: - * Perform architecture-specific initialization - * - * CONFIG_BOARD_LATE_INITIALIZE=y : - * Called from board_late_initialize(). - * - ****************************************************************************/ - -int stm32_bringup(void) -{ - int ret; - -#ifdef CONFIG_FS_PROCFS - /* Mount the procfs file system */ - - ret = nx_mount(NULL, "/proc", "procfs", 0, NULL); - if (ret < 0) - { - ferr("ERROR: Failed to mount procfs at /proc: %d\n", ret); - } -#endif - -#ifdef CONFIG_LPWAN_SX127X - ret = stm32_lpwaninitialize(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: Failed to initialize wireless driver: %d\n", - ret); - } -#endif /* CONFIG_LPWAN_SX127X */ - - UNUSED(ret); - return OK; -} diff --git a/boards/arm/stm32f0l0g0/nucleo-f091rc/src/stm32_buttons.c b/boards/arm/stm32f0l0g0/nucleo-f091rc/src/stm32_buttons.c deleted file mode 100644 index 6bcff91cece11..0000000000000 --- a/boards/arm/stm32f0l0g0/nucleo-f091rc/src/stm32_buttons.c +++ /dev/null @@ -1,117 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-f091rc/src/stm32_buttons.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include -#include - -#include "stm32_gpio.h" -#include "nucleo-f091rc.h" - -#ifdef CONFIG_ARCH_BUTTONS - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_button_initialize - * - * Description: - * board_button_initialize() must be called to initialize button resources. - * After that, board_buttons() may be called to collect the current state - * of all buttons or board_button_irq() may be called to register button - * interrupt handlers. - * - ****************************************************************************/ - -uint32_t board_button_initialize(void) -{ - /* Configure the single button as an input. NOTE that EXTI interrupts are - * also configured for the pin. - */ - - stm32_configgpio(GPIO_BTN_USER); - return NUM_BUTTONS; -} - -/**************************************************************************** - * Name: board_buttons - ****************************************************************************/ - -uint32_t board_buttons(void) -{ - /* Check that state of each USER button. A LOW value means that the key is - * pressed. - */ - - bool released = stm32_gpioread(GPIO_BTN_USER); - return !released; -} - -/**************************************************************************** - * Button support. - * - * Description: - * board_button_initialize() must be called to initialize button resources. - * After that, board_buttons() may be called to collect the current state - * of all buttons or board_button_irq() may be called to register button - * interrupt handlers. - * - * After board_button_initialize() has been called, board_buttons() may be - * called to collect the state of all buttons. board_buttons() returns an - * 32-bit bit set with each bit associated with a button. See the - * BUTTON_*_BIT definitions in board.h for the meaning of each bit. - * - * board_button_irq() may be called to register an interrupt handler that - * will be called when a button is depressed or released. The ID value is a - * button enumeration value that uniquely identifies a button resource. See - * the BUTTON_* definitions in board.h for the meaning of enumeration - * value. - * - ****************************************************************************/ - -#ifdef CONFIG_ARCH_IRQBUTTONS -int board_button_irq(int id, xcpt_t irqhandler, void *arg) -{ - int ret = -EINVAL; - - if (id == BUTTON_USER) - { - ret = stm32_gpiosetevent(GPIO_BTN_USER, true, true, true, - irqhandler, arg); - } - - return ret; -} -#endif -#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/stm32f0l0g0/nucleo-f091rc/src/stm32_spi.c b/boards/arm/stm32f0l0g0/nucleo-f091rc/src/stm32_spi.c deleted file mode 100644 index e94166da23c19..0000000000000 --- a/boards/arm/stm32f0l0g0/nucleo-f091rc/src/stm32_spi.c +++ /dev/null @@ -1,189 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-f091rc/src/stm32_spi.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include - -#include - -#include "arm_internal.h" -#include "chip.h" -#include "stm32_gpio.h" -#include "stm32_spi.h" - -#include "nucleo-f091rc.h" -#include - -#ifdef CONFIG_STM32F0L0G0_SPI - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_spidev_initialize - * - * Description: - * Called to configure SPI chip select GPIO pins for the Nucleo-144 board. - * - ****************************************************************************/ - -void stm32_spidev_initialize(void) -{ - /* NOTE: Clocking for SPI1 and/or SPI3 was already provided in stm32_rcc.c. - * Configurations of SPI pins is performed in stm32_spi.c. - * Here, we only initialize chip select pins unique to the board - * architecture. - */ - -#ifdef CONFIG_STM32F0L0G0_SPI1 - -# ifdef CONFIG_LPWAN_SX127X - /* Configure the SPI-based SX127X chip select GPIO */ - - spiinfo("Configure GPIO for SX127X SPI1/CS\n"); - - stm32_configgpio(GPIO_SX127X_CS); - stm32_gpiowrite(GPIO_SX127X_CS, true); -# endif - -#endif /* CONFIG_STM32F0L0G0_SPI1 */ -} - -/**************************************************************************** - * Name: stm32_spi1/2/select and stm32_spi1/2/status - * - * Description: - * The external functions, stm32_spi1/2select and stm32_spi1/2status - * must be provided by board-specific logic. They are implementations of - * the select and status methods of the SPI interface defined by struct - * spi_ops_s (see include/nuttx/spi/spi.h). All other methods (including - * stm32_spibus_initialize()) are provided by common STM32 logic. - * To use this common SPI logic on your board: - * - * 1. Provide logic in stm32_boardinitialize() to configure SPI chip - * select pins. - * 2. Provide stm32_spi1/2select() and stm32_spi1/2status() functions - * in your board-specific logic. These functions will perform chip - * selection and status operations using GPIOs in the way your board is - * configured. - * 3. Add a calls to stm32_spibus_initialize() in your low level - * application initialization logic - * 4. The handle returned by stm32_spibus_initialize() may then be used to - * bind the SPI driver to higher level logic (e.g., calling - * mmcsd_spislotinitialize(), for example, will bind the SPI driver to - * the SPI MMC/SD driver). - * - ****************************************************************************/ - -#ifdef CONFIG_STM32F0L0G0_SPI1 -void stm32_spi1select(struct spi_dev_s *dev, - uint32_t devid, bool selected) -{ - spiinfo("devid: %d CS: %s\n", - (int)devid, selected ? "assert" : "de-assert"); - - switch (devid) - { -#ifdef CONFIG_LPWAN_SX127X - case SPIDEV_LPWAN(0): - { - spiinfo("SX127X device %s\n", - selected ? "asserted" : "de-asserted"); - - /* Set the GPIO low to select and high to de-select */ - - stm32_gpiowrite(GPIO_SX127X_CS, !selected); - break; - } -#endif - - default: - { - break; - } - } -} - -uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) -{ - uint8_t status = 0; - - switch (devid) - { -#ifdef CONFIG_LPWAN_SX127X - case SPIDEV_LPWAN(0): - { - status |= SPI_STATUS_PRESENT; - break; - } -#endif - - default: - { - break; - } - } - - return status; -} -#endif /* CONFIG_STM32F0L0G0_SPI1 */ - -#ifdef CONFIG_STM32F0L0G0_SPI2 -void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid, - bool selected) -{ - spiinfo("devid: %d CS: %s\n", - (int)devid, selected ? "assert" : "de-assert"); -} - -uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) -{ - return 0; -} -#endif /* CONFIG_STM32F0L0G0_SPI2 */ - -#endif diff --git a/boards/arm/stm32f0l0g0/nucleo-f091rc/src/stm32_sx127x.c b/boards/arm/stm32f0l0g0/nucleo-f091rc/src/stm32_sx127x.c deleted file mode 100644 index 2c674d8aa6423..0000000000000 --- a/boards/arm/stm32f0l0g0/nucleo-f091rc/src/stm32_sx127x.c +++ /dev/null @@ -1,212 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-f091rc/src/stm32_sx127x.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -#include "stm32_gpio.h" -#include "stm32_exti.h" -#include "stm32_spi.h" - -#include "nucleo-f091rc.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* SX127X on SPI1 bus */ - -#define SX127X_SPI 1 - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -static void sx127x_chip_reset(void); -static int sx127x_opmode_change(int opmode); -static int sx127x_freq_select(uint32_t freq); -static int sx127x_pa_select(bool enable); -static int sx127x_irq0_attach(xcpt_t isr, void *arg); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -struct sx127x_lower_s lower = -{ - .irq0attach = sx127x_irq0_attach, - .reset = sx127x_chip_reset, - .opmode_change = sx127x_opmode_change, - .freq_select = sx127x_freq_select, - .pa_select = sx127x_pa_select, - .pa_force = true -}; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: sx127x_irq0_attach - ****************************************************************************/ - -static int sx127x_irq0_attach(xcpt_t isr, void *arg) -{ - wlinfo("Attach DIO0 IRQ\n"); - - /* IRQ on rising edge */ - - stm32_gpiosetevent(GPIO_SX127X_DIO0, true, false, false, isr, arg); - return OK; -} - -/**************************************************************************** - * Name: sx127x_chip_reset - ****************************************************************************/ - -static void sx127x_chip_reset(void) -{ - wlinfo("SX127X RESET\n"); - - /* Configure reset as output */ - - stm32_configgpio(GPIO_SX127X_RESET | GPIO_OUTPUT | GPIO_SPEED_HIGH | - GPIO_OUTPUT_CLEAR); - - /* Set pin to zero */ - - stm32_gpiowrite(GPIO_SX127X_RESET, false); - - /* Wait 1 ms */ - - nxsched_usleep(1000); - - /* Configure reset as input */ - - stm32_configgpio(GPIO_SX127X_RESET | GPIO_INPUT | GPIO_FLOAT); - - /* Wait 10 ms */ - - nxsched_usleep(10000); -} - -/**************************************************************************** - * Name: sx127x_opmode_change - ****************************************************************************/ - -static int sx127x_opmode_change(int opmode) -{ - /* Do nothing */ - - return OK; -} - -/**************************************************************************** - * Name: sx127x_freq_select - ****************************************************************************/ - -static int sx127x_freq_select(uint32_t freq) -{ - int ret = OK; - - /* NOTE: this depends on your module version */ - - if (freq > SX127X_HFBAND_THR) - { - ret = -EINVAL; - wlerr("HF output not supported\n"); - } - - return ret; -} - -/**************************************************************************** - * Name: sx127x_pa_select - ****************************************************************************/ - -static int sx127x_pa_select(bool enable) -{ - int ret = OK; - - /* Only PA_BOOST output connected to antenna */ - - if (enable == false) - { - ret = -EINVAL; - wlerr("Module supports only PA_BOOST pin, " - "so PA_SELECT must be enabled!\n"); - } - - return ret; -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -int stm32_lpwaninitialize(void) -{ - struct spi_dev_s *spidev; - int ret = OK; - - wlinfo("Register the sx127x module\n"); - - /* Setup DIO0 */ - - stm32_configgpio(GPIO_SX127X_DIO0); - - /* Init SPI bus */ - - spidev = stm32_spibus_initialize(SX127X_SPI); - if (!spidev) - { - wlerr("ERROR: Failed to initialize SPI %d bus\n", SX127X_SPI); - ret = -ENODEV; - goto errout; - } - - /* Initialize SX127X */ - - ret = sx127x_register(spidev, &lower); - if (ret < 0) - { - wlerr("ERROR: Failed to register sx127x\n"); - goto errout; - } - -errout: - return ret; -} diff --git a/boards/arm/stm32f0l0g0/nucleo-f091rc/src/stm32_userleds.c b/boards/arm/stm32f0l0g0/nucleo-f091rc/src/stm32_userleds.c deleted file mode 100644 index cf8e3cccc45c2..0000000000000 --- a/boards/arm/stm32f0l0g0/nucleo-f091rc/src/stm32_userleds.c +++ /dev/null @@ -1,197 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-f091rc/src/stm32_userleds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include - -#include -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32_gpio.h" -#include "nucleo-f091rc.h" - -#ifndef CONFIG_ARCH_LEDS - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -/* LED Power Management */ - -#ifdef CONFIG_PM -static void led_pm_notify(struct pm_callback_s *cb, int domain, - enum pm_state_e pmstate); -static int led_pm_prepare(struct pm_callback_s *cb, int domain, - enum pm_state_e pmstate); -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -#ifdef CONFIG_PM -static struct pm_callback_s g_ledscb = -{ - .notify = led_pm_notify, - .prepare = led_pm_prepare, -}; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: led_pm_notify - * - * Description: - * Notify the driver of new power state. This callback is called after - * all drivers have had the opportunity to prepare for the new power state. - * - ****************************************************************************/ - -#ifdef CONFIG_PM -static void led_pm_notify(struct pm_callback_s *cb, int domain, - enum pm_state_e pmstate) -{ - switch (pmstate) - { - case PM_NORMAL: - { - /* Restore normal LEDs operation */ - } - break; - - case PM_IDLE: - { - /* Entering IDLE mode - Turn leds off */ - } - break; - - case PM_STANDBY: - { - /* Entering STANDBY mode - Logic for PM_STANDBY goes here */ - } - break; - - case PM_SLEEP: - { - /* Entering SLEEP mode - Logic for PM_SLEEP goes here */ - } - break; - - default: - { - /* Should not get here */ - } - break; - } -} -#endif - -/**************************************************************************** - * Name: led_pm_prepare - * - * Description: - * Request the driver to prepare for a new power state. This is a warning - * that the system is about to enter into a new power state. The driver - * should begin whatever operations that may be required to enter power - * state. The driver may abort the state change mode by returning a - * non-zero value from the callback function. - * - ****************************************************************************/ - -#ifdef CONFIG_PM -static int led_pm_prepare(struct pm_callback_s *cb, int domain, - enum pm_state_e pmstate) -{ - /* No preparation to change power modes is required by the LEDs driver. - * We always accept the state change by returning OK. - */ - - return OK; -} -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_userled_initialize - ****************************************************************************/ - -uint32_t board_userled_initialize(void) -{ - /* Configure LD2 GPIO for output */ - - stm32_configgpio(GPIO_LD2); - return BOARD_NLEDS; -} - -/**************************************************************************** - * Name: board_userled - ****************************************************************************/ - -void board_userled(int led, bool ledon) -{ - if (led == BOARD_LD2) - { - stm32_gpiowrite(GPIO_LD2, ledon); - } -} - -/**************************************************************************** - * Name: board_userled_all - ****************************************************************************/ - -void board_userled_all(uint32_t ledset) -{ - stm32_gpiowrite(GPIO_LD2, (ledset & BOARD_LD2_BIT) != 0); -} - -/**************************************************************************** - * Name: stm32_led_pminitialize - ****************************************************************************/ - -#ifdef CONFIG_PM -void stm32_led_pminitialize(void) -{ - /* Register to receive power management callbacks */ - - int ret = pm_register(&g_ledscb); - DEBUGASSERT(ret == OK); - UNUSED(ret); -} -#endif /* CONFIG_PM */ - -#endif /* !CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32f0l0g0/nucleo-g070rb/CMakeLists.txt b/boards/arm/stm32f0l0g0/nucleo-g070rb/CMakeLists.txt deleted file mode 100644 index 4427973ea2674..0000000000000 --- a/boards/arm/stm32f0l0g0/nucleo-g070rb/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32f0l0g0/nucleo-g070rb/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32f0l0g0/nucleo-g070rb/configs/nsh/defconfig b/boards/arm/stm32f0l0g0/nucleo-g070rb/configs/nsh/defconfig deleted file mode 100644 index 2f5e5cf0859f3..0000000000000 --- a/boards/arm/stm32f0l0g0/nucleo-g070rb/configs/nsh/defconfig +++ /dev/null @@ -1,106 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_NSH_ARGCAT is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="nucleo-g070rb" -CONFIG_ARCH_BOARD_NUCLEO_G070RB=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32f0l0g0" -CONFIG_ARCH_CHIP_STM32G070RB=y -CONFIG_ARCH_CHIP_STM32G0=y -CONFIG_ARCH_IRQBUTTONS=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=2796 -CONFIG_BUILTIN=y -CONFIG_DEBUG_FULLOPT=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_DEV_GPIO=y -CONFIG_DISABLE_ENVIRON=y -CONFIG_DISABLE_MOUNTPOINT=y -CONFIG_DISABLE_MQUEUE=y -CONFIG_DISABLE_POSIX_TIMERS=y -CONFIG_DISABLE_PSEUDOFS_OPERATIONS=y -CONFIG_EXAMPLES_BUTTONS=y -CONFIG_EXAMPLES_GPIO=y -CONFIG_EXAMPLES_HELLO=y -CONFIG_EXAMPLES_PWM=y -CONFIG_EXAMPLES_TIMER=y -CONFIG_I2C=y -CONFIG_I2CTOOL_MAXADDR=0xff -CONFIG_I2CTOOL_MINADDR=0x00 -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INIT_STACKSIZE=1536 -CONFIG_INPUT=y -CONFIG_INPUT_BUTTONS=y -CONFIG_INPUT_BUTTONS_LOWER=y -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=64 -CONFIG_NSH_READLINE=y -CONFIG_NUNGET_CHARS=0 -CONFIG_POSIX_SPAWN_DEFAULT_STACKSIZE=1536 -CONFIG_PTHREAD_MUTEX_UNSAFE=y -CONFIG_PTHREAD_STACK_DEFAULT=1536 -CONFIG_PWM=y -CONFIG_RAM_SIZE=20480 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=19 -CONFIG_START_MONTH=5 -CONFIG_START_YEAR=2013 -CONFIG_STDIO_DISABLE_BUFFERING=y -CONFIG_STM32F0L0G0_I2C1=y -CONFIG_STM32F0L0G0_PWM_MULTICHAN=y -CONFIG_STM32F0L0G0_PWR=y -CONFIG_STM32F0L0G0_TIM14=y -CONFIG_STM32F0L0G0_TIM14_CH1OUT=y -CONFIG_STM32F0L0G0_TIM14_CHANNEL1=y -CONFIG_STM32F0L0G0_TIM14_PWM=y -CONFIG_STM32F0L0G0_TIM15=y -CONFIG_STM32F0L0G0_TIM15_CH1OUT=y -CONFIG_STM32F0L0G0_TIM15_CHANNEL1=y -CONFIG_STM32F0L0G0_TIM15_PWM=y -CONFIG_STM32F0L0G0_TIM16=y -CONFIG_STM32F0L0G0_TIM16_CH1OUT=y -CONFIG_STM32F0L0G0_TIM16_CHANNEL1=y -CONFIG_STM32F0L0G0_TIM16_PWM=y -CONFIG_STM32F0L0G0_TIM17=y -CONFIG_STM32F0L0G0_TIM17_CH1OUT=y -CONFIG_STM32F0L0G0_TIM17_CHANNEL1=y -CONFIG_STM32F0L0G0_TIM17_PWM=y -CONFIG_STM32F0L0G0_TIM1=y -CONFIG_STM32F0L0G0_TIM1_CH1OUT=y -CONFIG_STM32F0L0G0_TIM1_CH2OUT=y -CONFIG_STM32F0L0G0_TIM1_CH3OUT=y -CONFIG_STM32F0L0G0_TIM1_CH4OUT=y -CONFIG_STM32F0L0G0_TIM1_CHANNEL1=y -CONFIG_STM32F0L0G0_TIM1_CHANNEL2=y -CONFIG_STM32F0L0G0_TIM1_CHANNEL3=y -CONFIG_STM32F0L0G0_TIM1_CHANNEL4=y -CONFIG_STM32F0L0G0_TIM1_PWM=y -CONFIG_STM32F0L0G0_TIM3=y -CONFIG_STM32F0L0G0_TIM3_CH1OUT=y -CONFIG_STM32F0L0G0_TIM3_CH2OUT=y -CONFIG_STM32F0L0G0_TIM3_CH3OUT=y -CONFIG_STM32F0L0G0_TIM3_CH4OUT=y -CONFIG_STM32F0L0G0_TIM3_CHANNEL1=y -CONFIG_STM32F0L0G0_TIM3_CHANNEL2=y -CONFIG_STM32F0L0G0_TIM3_CHANNEL3=y -CONFIG_STM32F0L0G0_TIM3_CHANNEL4=y -CONFIG_STM32F0L0G0_TIM3_PWM=y -CONFIG_STM32F0L0G0_TIM6=y -CONFIG_STM32F0L0G0_USART2=y -CONFIG_SYSTEM_I2CTOOL=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_TIMER=y -CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f0l0g0/nucleo-g070rb/include/board.h b/boards/arm/stm32f0l0g0/nucleo-g070rb/include/board.h deleted file mode 100644 index 5e09c65d50a1e..0000000000000 --- a/boards/arm/stm32f0l0g0/nucleo-g070rb/include/board.h +++ /dev/null @@ -1,246 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-g070rb/include/board.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __BOARDS_ARM_STM32F0L0G0_NUCLEO_G070RB_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32F0L0G0_NUCLEO_G070RB_INCLUDE_BOARD_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#ifndef __ASSEMBLY__ -# include -# include -#endif - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Clocking *****************************************************************/ - -/* HSI - Internal 16 MHz RC Oscillator - * LSI - 32 KHz RC - * HSE - 8 MHz from MCO output of ST-LINK (disabled by default) - * LSE - 32.768 kHz - */ - -#define STM32_BOARD_XTAL 8000000ul /* 8MHz */ - -#define STM32_HSI_FREQUENCY 16000000ul /* 16MHz */ -#define STM32_LSI_FREQUENCY 32000 /* Between 30kHz and 60kHz */ -#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL -#define STM32_LSE_FREQUENCY 32768 /* X2 on board */ - -/* Main PLL Configuration. - * - * PLL_VCO = (PLL_SOURCE_FREQUENCY / PLL_M) * PLL_N - * SYSCLK = PLLCLK = PLLR = PLL_VCO / PLL_DIV_R - * PLLP = PLL_VCO / PLL_DIV_P - * - * Subject to: - * - * PLL_SOURCE_FREQUENCY is one of {STM32_HSE_FREQUENCY, STM32_HSI_FREQUENCY} - * - * 1 <= PLL_DIV_M <= 8 - * 8 <= PLL_DIV_N <= 86 - * 2 <= PLL_DIV_P <= 32 - * 2 <= PLL_DIV_R <= 8 - * 4 MHz <= PLL_SOURCE_FREQUENCY <= 48 MHz - * 96 MHz <= PLL_VCO <= 344MHz - */ - -/* Considering: - * - PLL_SOURCE_FREQUENCY = STM32_HSI_FREQUENCY = 16,000,000 - * - PLL_DIV_M = 1 - * - PLL_DIV_N = 8 - * - PLL_DIV_R = 2 - * - PLL_DIV_P = 2 - * - * PLL_VCO = (16,000,000 / 1) * 8 = 128 MHz - * PLLP = (PLL_VCO / 2) = 64 MHz - * PLLR = (PLL_VCO / 2) = 64 MHz - */ - -#define STM32_PLLCFG_PLLSRC RCC_PLLCFG_PLLSRC_HSI -#define STM32_PLLCFG_PLLCFG (RCC_PLLCFG_PLLPEN | \ - RCC_PLLCFG_PLLREN) - -#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) -#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(8) -#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP(2) -#define STM32_PLLCFG_PLLR RCC_PLLCFG_PLLR(2) - -#define STM32_VCO_FREQUENCY ((STM32_HSI_FREQUENCY / 1) * 8) -#define STM32_PLLP_FREQUENCY (STM32_VCO_FREQUENCY / 2) -#define STM32_PLLR_FREQUENCY (STM32_VCO_FREQUENCY / 2) - -/* Use the PLL and set the SYSCLK source to be the PLLR (64 MHz) */ - -#define STM32_SYSCLK_SW RCC_CFGR_SW_PLL -#define STM32_SYSCLK_SWS RCC_CFGR_SWS_PLL -#define STM32_SYSCLK_FREQUENCY (STM32_PLLR_FREQUENCY) - -/* AHB clock (HCLK) is SYSCLK (64 MHz) */ - -#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK -#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY - -/* APB1 clock (PCLK1) is HCLK (64 MHz) */ - -#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK -#define STM32_PCLK1_FREQUENCY STM32_HCLK_FREQUENCY - -/* Timer clock frequencies */ - -/* Timers driven from APB1. Frequency = PCLK1 */ - -#define STM32_APB1_TIM3_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (STM32_PCLK1_FREQUENCY) - -/* Timers driven from APB2 is equal to PCLK1 */ - -#define STM32_APB2_TIM1_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB2_TIM14_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB2_TIM15_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB2_TIM16_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB2_TIM17_CLKIN (STM32_PCLK1_FREQUENCY) - -/* LED definitions **********************************************************/ - -/* Nucleo G070RB board has three LEDs. Two of these are controlled by - * logic on the board and are not available for software control: - * - * LD1 COM: LD1 default status is red. LD1 turns to green to indicate that - * communications are in progress between the PC and the - * ST-LINK/V2-1. - * LD3 5V_PWR: green LED indicates that the board is powered by a 5V source. - * - * And one can be controlled by software: - * - * User LD4: green LED is a user LED connected to STM32 I/O PA5. - * - * If CONFIG_ARCH_LEDS is not defined, then the user can control the LED in - * any way. The following definition is used to access the LED. - */ - -/* LED index values for use with board_userled() */ - -#define BOARD_LED1 0 /* User LD4 */ -#define BOARD_NLEDS 1 - -/* LED bits for use with board_userled_all() */ - -#define BOARD_LED1_BIT (1 << BOARD_LED1) - -/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the LED on the - * board. The following definitions describe how NuttX controls - * the LED: - * - * SYMBOL Meaning LED1 state - * ------------------ ----------------------- ---------- - * LED_STARTED NuttX has been started OFF - * LED_HEAPALLOCATE Heap has been allocated OFF - * LED_IRQSENABLED Interrupts enabled OFF - * LED_STACKCREATED Idle stack created ON - * LED_INIRQ In an interrupt No change - * LED_SIGNAL In a signal handler No change - * LED_ASSERTION An assertion failed No change - * LED_PANIC The system has crashed Blinking - * LED_IDLE STM32 is in sleep mode Not used - */ - -#define LED_STARTED 0 -#define LED_HEAPALLOCATE 0 -#define LED_IRQSENABLED 0 -#define LED_STACKCREATED 1 -#define LED_INIRQ 2 -#define LED_SIGNAL 2 -#define LED_ASSERTION 2 -#define LED_PANIC 1 - -/* Button definitions *******************************************************/ - -/* Nucleo G070RB board supports two buttons; only one button is controllable - * by software: - * - * B1 USER: user button connected to STM32 I/O PC13. - * B2 RESET: push button connected to NRST; used to RESET the MCU. - */ - -#define BUTTON_USER 0 /* User B1 */ -#define NUM_BUTTONS 1 - -#define BUTTON_USER_BIT (1 << BUTTON_USER) - -/* Alternate function pin selections ****************************************/ - -/* I2C */ - -#define GPIO_I2C1_SCL (GPIO_I2C1_SCL_3|GPIO_SPEED_LOW) /* PB8 */ -#define GPIO_I2C1_SDA (GPIO_I2C1_SDA_3|GPIO_SPEED_LOW) /* PB9 */ - -/* TIM */ - -#define GPIO_TIM1_CH1OUT (GPIO_TIM1_CH1OUT_1|GPIO_SPEED_LOW) /* PA8 */ -#define GPIO_TIM1_CH2OUT (GPIO_TIM1_CH2OUT_2|GPIO_SPEED_LOW) /* PB3 */ -#define GPIO_TIM1_CH3OUT (GPIO_TIM1_CH3OUT_2|GPIO_SPEED_LOW) /* PB6 */ -#define GPIO_TIM1_CH4OUT (GPIO_TIM1_CH4OUT_1|GPIO_SPEED_LOW) /* PA11 */ -#define GPIO_TIM1_CH1NOUT (GPIO_TIM1_CH1NOUT_2|GPIO_SPEED_LOW) /* PB13 */ -#define GPIO_TIM1_CH2NOUT (GPIO_TIM1_CH2NOUT_2|GPIO_SPEED_LOW) /* PB14 */ -#define GPIO_TIM1_CH3NOUT (GPIO_TIM1_CH3NOUT_2|GPIO_SPEED_LOW) /* PB15 */ - -#define GPIO_TIM3_CH1OUT (GPIO_TIM3_CH1OUT_2|GPIO_SPEED_LOW) /* PB4 */ -#define GPIO_TIM3_CH2OUT (GPIO_TIM3_CH2OUT_2|GPIO_SPEED_LOW) /* PB5 */ -#define GPIO_TIM3_CH3OUT (GPIO_TIM3_CH3OUT_1|GPIO_SPEED_LOW) /* PB0 */ -#define GPIO_TIM3_CH4OUT (GPIO_TIM3_CH4OUT_1|GPIO_SPEED_LOW) /* PB1 */ - -#define GPIO_TIM14_CH1OUT (GPIO_TIM14_CH1OUT_2|GPIO_SPEED_LOW) /* PA7 */ - -#define GPIO_TIM15_CH1OUT (GPIO_TIM15_CH1OUT_3|GPIO_SPEED_LOW) /* PC1 */ -#define GPIO_TIM15_CH2OUT (GPIO_TIM15_CH2OUT_3|GPIO_SPEED_LOW) /* PC2 */ -#define GPIO_TIM15_CH1NOUT (GPIO_TIM15_CH1NOUT_1|GPIO_SPEED_LOW) /* PA1 */ - -#define GPIO_TIM16_CH1OUT (GPIO_TIM16_CH1OUT_3|GPIO_SPEED_LOW) /* PD0 */ - -#define GPIO_TIM17_CH1OUT (GPIO_TIM17_CH1OUT_2|GPIO_SPEED_LOW) /* PD1 */ - -/* USART */ - -/* By default the USART2 is connected to STLINK Virtual COM Port: - * USART2_RX - PA3 - * USART2_TX - PA2 - */ - -#define GPIO_USART2_RX (GPIO_USART2_RX_1|GPIO_SPEED_HIGH) /* PA3 */ -#define GPIO_USART2_TX (GPIO_USART2_TX_1|GPIO_SPEED_HIGH) /* PA2 */ - -/* DMA channels *************************************************************/ - -/* ADC */ - -/* TODO ADC */ - -#endif /* __BOARDS_ARM_STM32F0L0G0_NUCLEO_G070RB_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32f0l0g0/nucleo-g070rb/scripts/Make.defs b/boards/arm/stm32f0l0g0/nucleo-g070rb/scripts/Make.defs deleted file mode 100644 index df8a4c75ba114..0000000000000 --- a/boards/arm/stm32f0l0g0/nucleo-g070rb/scripts/Make.defs +++ /dev/null @@ -1,41 +0,0 @@ -############################################################################ -# boards/arm/stm32f0l0g0/nucleo-g070rb/scripts/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/.config -include $(TOPDIR)/tools/Config.mk -include $(TOPDIR)/arch/arm/src/armv6-m/Toolchain.defs - -LDSCRIPT = ld.script -ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) - -ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 - -CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) -CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) -CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -AFLAGS := $(CFLAGS) -D__ASSEMBLY__ - -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections -LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32f0l0g0/nucleo-g070rb/scripts/ld.script b/boards/arm/stm32f0l0g0/nucleo-g070rb/scripts/ld.script deleted file mode 100644 index 3eddc960eb999..0000000000000 --- a/boards/arm/stm32f0l0g0/nucleo-g070rb/scripts/ld.script +++ /dev/null @@ -1,115 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-g070rb/scripts/ld.script - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* The STM32G070RB has 128Kb of FLASH beginning at address 0x0800:0000 and - * 32Kb/36Kb of SRAM. - * - * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 - * where the code expects to begin execution by jumping to the entry point in - * the 0x0800:0000 address range. - */ - -MEMORY -{ - flash (rx) : ORIGIN = 0x08000000, LENGTH = 128K - sram (rwx) : ORIGIN = 0x20000000, LENGTH = 36K -} - -OUTPUT_ARCH(arm) -EXTERN(_vectors) -ENTRY(_stext) -SECTIONS -{ - .text : { - _stext = ABSOLUTE(.); - *(.vectors) - *(.text .text.*) - *(.fixup) - *(.gnu.warning) - *(.rodata .rodata.*) - *(.gnu.linkonce.t.*) - *(.glue_7) - *(.glue_7t) - *(.got) - *(.gcc_except_table) - *(.gnu.linkonce.r.*) - _etext = ABSOLUTE(.); - } > flash - - .init_section : ALIGN(4) { - _sinit = ABSOLUTE(.); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) - KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) - _einit = ABSOLUTE(.); - } > flash - - .ARM.extab : ALIGN(4) { - *(.ARM.extab*) - } > flash - - .ARM.exidx : ALIGN(4) { - __exidx_start = ABSOLUTE(.); - *(.ARM.exidx*) - __exidx_end = ABSOLUTE(.); - } > flash - - _eronly = ABSOLUTE(.); - - /* The RAM vector table (if present) should lie at the beginning of SRAM */ - - .ram_vectors : { - *(.ram_vectors) - } > sram - - .data : ALIGN(4) { - _sdata = ABSOLUTE(.); - *(.data .data.*) - *(.gnu.linkonce.d.*) - CONSTRUCTORS - . = ALIGN(4); - _edata = ABSOLUTE(.); - } > sram AT > flash - - .bss : ALIGN(4) { - _sbss = ABSOLUTE(.); - *(.bss .bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - . = ALIGN(4); - _ebss = ABSOLUTE(.); - } > sram - - /* Stabs debugging sections. */ - - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_info 0 : { *(.debug_info) } - .debug_line 0 : { *(.debug_line) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_aranges 0 : { *(.debug_aranges) } -} diff --git a/boards/arm/stm32f0l0g0/nucleo-g070rb/src/CMakeLists.txt b/boards/arm/stm32f0l0g0/nucleo-g070rb/src/CMakeLists.txt deleted file mode 100644 index 08d07dd22c1c0..0000000000000 --- a/boards/arm/stm32f0l0g0/nucleo-g070rb/src/CMakeLists.txt +++ /dev/null @@ -1,49 +0,0 @@ -# ############################################################################## -# boards/arm/stm32f0l0g0/nucleo-g070rb/src/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -set(SRCS stm32_boot.c stm32_bringup.c) - -if(CONFIG_ARCH_LEDS) - list(APPEND SRCS stm32_autoleds.c) -else() - list(APPEND SRCS stm32_userleds.c) -endif() - -if(CONFIG_ARCH_BUTTONS) - list(APPEND SRCS stm32_buttons.c) -endif() - -if(CONFIG_DEV_GPIO) - list(APPEND SRCS stm32_gpio.c) -endif() - -if(CONFIG_PWM) - list(APPEND SRCS stm32_pwm.c) -endif() - -if(CONFIG_TIMER) - list(APPEND SRCS stm32_timer.c) -endif() - -target_sources(board PRIVATE ${SRCS}) - -set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/ld.script") diff --git a/boards/arm/stm32f0l0g0/nucleo-g070rb/src/Make.defs b/boards/arm/stm32f0l0g0/nucleo-g070rb/src/Make.defs deleted file mode 100644 index 3fcfafcf17fe3..0000000000000 --- a/boards/arm/stm32f0l0g0/nucleo-g070rb/src/Make.defs +++ /dev/null @@ -1,51 +0,0 @@ -############################################################################ -# boards/arm/stm32f0l0g0/nucleo-g070rb/src/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/Make.defs - -CSRCS = stm32_boot.c stm32_bringup.c - -ifeq ($(CONFIG_ARCH_LEDS),y) -CSRCS += stm32_autoleds.c -else -CSRCS += stm32_userleds.c -endif - -ifeq ($(CONFIG_ARCH_BUTTONS),y) -CSRCS += stm32_buttons.c -endif - -ifeq ($(CONFIG_DEV_GPIO),y) -CSRCS += stm32_gpio.c -endif - -ifeq ($(CONFIG_PWM),y) -CSRCS += stm32_pwm.c -endif - -ifeq ($(CONFIG_TIMER),y) -CSRCS += stm32_timer.c -endif - -DEPPATH += --dep-path board -VPATH += :board -CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32f0l0g0/nucleo-g070rb/src/stm32_autoleds.c b/boards/arm/stm32f0l0g0/nucleo-g070rb/src/stm32_autoleds.c deleted file mode 100644 index b96b3795bd0d7..0000000000000 --- a/boards/arm/stm32f0l0g0/nucleo-g070rb/src/stm32_autoleds.c +++ /dev/null @@ -1,81 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-g070rb/src/stm32_autoleds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include - -#include "stm32_gpio.h" -#include "nucleo-g070rb.h" - -#include - -#ifdef CONFIG_ARCH_LEDS - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_autoled_initialize - ****************************************************************************/ - -void board_autoled_initialize(void) -{ - /* Configure LED1 GPIO for output */ - - stm32_configgpio(GPIO_LED1); -} - -/**************************************************************************** - * Name: board_autoled_on - ****************************************************************************/ - -void board_autoled_on(int led) -{ - if (led == BOARD_LED1) - { - stm32_gpiowrite(GPIO_LED1, true); - } -} - -/**************************************************************************** - * Name: board_autoled_off - ****************************************************************************/ - -void board_autoled_off(int led) -{ - if (led == BOARD_LED1) - { - stm32_gpiowrite(GPIO_LED1, false); - } -} - -#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32f0l0g0/nucleo-g070rb/src/stm32_boot.c b/boards/arm/stm32f0l0g0/nucleo-g070rb/src/stm32_boot.c deleted file mode 100644 index 7783acec8ab67..0000000000000 --- a/boards/arm/stm32f0l0g0/nucleo-g070rb/src/stm32_boot.c +++ /dev/null @@ -1,83 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-g070rb/src/stm32_boot.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include "nucleo-g070rb.h" - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_boardinitialize - * - * Description: - * All STM32 architectures must provide the following entry point. This - * entry point is called early in the initialization -- after all memory - * has been configured and mapped but before any devices have been - * initialized. - * - ****************************************************************************/ - -void stm32_boardinitialize(void) -{ -#ifdef CONFIG_ARCH_LEDS - /* Configure on-board LEDs if LED support has been selected. */ - - board_autoled_initialize(); -#endif - -#ifdef CONFIG_STM32F0L0G0_SPI - /* Configure SPI chip selects */ - - stm32_spidev_initialize(); -#endif -} - -/**************************************************************************** - * Name: board_late_initialize - * - * Description: - * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional - * initialization call will be performed in the boot-up sequence to a - * function called board_late_initialize(). board_late_initialize() will - * be called immediately after up_initialize() is called and just before - * the initial application is started. This additional initialization - * phase may be used, for example, to initialize board-specific device - * drivers. - * - ****************************************************************************/ - -#ifdef CONFIG_BOARD_LATE_INITIALIZE -void board_late_initialize(void) -{ - stm32_bringup(); -} -#endif diff --git a/boards/arm/stm32f0l0g0/nucleo-g070rb/src/stm32_bringup.c b/boards/arm/stm32f0l0g0/nucleo-g070rb/src/stm32_bringup.c deleted file mode 100644 index 4d21f1918aec3..0000000000000 --- a/boards/arm/stm32f0l0g0/nucleo-g070rb/src/stm32_bringup.c +++ /dev/null @@ -1,213 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-g070rb/src/stm32_bringup.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include -#include - -#include "nucleo-g070rb.h" -#include "stm32_i2c.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#undef HAVE_LEDS -#undef HAVE_DAC - -#if !defined(CONFIG_ARCH_LEDS) && defined(CONFIG_USERLED_LOWER) -# define HAVE_LEDS 1 -#endif - -/* TODO ??? */ - -#if defined(CONFIG_DAC) -# define HAVE_DAC1 1 -# define HAVE_DAC2 1 -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_i2c_register - * - * Description: - * Register one I2C drivers for the I2C tool. - * - ****************************************************************************/ - -#if defined(CONFIG_I2C) && defined(CONFIG_SYSTEM_I2CTOOL) -static void stm32_i2c_register(int bus) -{ - struct i2c_master_s *i2c; - int ret; - - i2c = stm32_i2cbus_initialize(bus); - if (i2c == NULL) - { - syslog(LOG_ERR, "ERROR: Failed to get I2C%d interface\n", bus); - } - else - { - ret = i2c_register(i2c, bus); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: Failed to register I2C%d driver: %d\n", - bus, ret); - stm32_i2cbus_uninitialize(i2c); - } - } -} -#endif - -/**************************************************************************** - * Name: stm32_i2ctool - * - * Description: - * Register I2C drivers for the I2C tool. - * - ****************************************************************************/ - -#if defined(CONFIG_I2C) && defined(CONFIG_SYSTEM_I2CTOOL) -static void stm32_i2ctool(void) -{ -#ifdef CONFIG_STM32F0L0G0_I2C1 - stm32_i2c_register(1); -#endif -#ifdef CONFIG_STM32F0L0G0_I2C2 - stm32_i2c_register(2); -#endif -} -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_bringup - * - * Description: - * Perform architecture-specific initialization - * - * CONFIG_BOARD_LATE_INITIALIZE=y : - * Called from board_late_initialize(). - * - ****************************************************************************/ - -int stm32_bringup(void) -{ - int ret; - -#ifdef HAVE_LEDS - /* Register the LED driver */ - - ret = userled_lower_initialize(LED_DRIVER_PATH); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: userled_lower_initialize() failed: %d\n", ret); - return ret; - } -#endif - -#if defined(CONFIG_I2C) && defined(CONFIG_SYSTEM_I2CTOOL) - stm32_i2ctool(); -#endif - -#ifdef CONFIG_INPUT_BUTTONS - /* Register the BUTTON driver */ - - ret = btn_lower_initialize("/dev/buttons"); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: btn_lower_initialize() failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_DEV_GPIO - /* Register the GPIO driver */ - - ret = stm32_gpio_initialize(); - if (ret < 0) - { - syslog(LOG_ERR, "Failed to initialize GPIO Driver: %d\n", ret); - } -#endif - -#ifdef CONFIG_ADC - /* Initialize ADC and register the ADC driver. */ - - ret = stm32_adc_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_adc_setup failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_TIMER - /* Initialize basic timers */ - -#if defined(CONFIG_STM32F0L0G0_TIM6) - syslog(LOG_ERR, "Init timer\n"); - ret = stm32_timer_driver_setup("/dev/timer0", 6); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_timer_driver_setup failed. TIM6: %d\n", - ret); - } -#endif - -#if defined(CONFIG_STM32F0L0G0_TIM7) - ret = stm32_timer_driver_setup("/dev/timer1", 7); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_timer_driver_setup failed. TIM7: %d\n", - ret); - } - -#endif -#endif - -#if defined(CONFIG_PWM) - /* Initialize PWM and register the PWM device */ - - ret = stm32_pwm_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_pwm_setup() failed: %d\n", ret); - } -#endif - - UNUSED(ret); - return OK; -} diff --git a/boards/arm/stm32f0l0g0/nucleo-g070rb/src/stm32_buttons.c b/boards/arm/stm32f0l0g0/nucleo-g070rb/src/stm32_buttons.c deleted file mode 100644 index 9bd12c84dfa97..0000000000000 --- a/boards/arm/stm32f0l0g0/nucleo-g070rb/src/stm32_buttons.c +++ /dev/null @@ -1,118 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-g070rb/src/stm32_buttons.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include "stm32_gpio.h" -#include "nucleo-g070rb.h" - -#include - -#ifdef CONFIG_ARCH_BUTTONS - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_button_initialize - * - * Description: - * board_button_initialize() must be called to initialize button resources. - * After that, board_buttons() may be called to collect the current state - * of all buttons or board_button_irq() may be called to register button - * interrupt handlers. - * - ****************************************************************************/ - -uint32_t board_button_initialize(void) -{ - /* Configure the single button as an input. NOTE that EXTI interrupts are - * also configured for the pin. - */ - - stm32_configgpio(GPIO_BTN_USER); - return NUM_BUTTONS; -} - -/**************************************************************************** - * Name: board_buttons - ****************************************************************************/ - -uint32_t board_buttons(void) -{ - /* Check that state of each USER button. A LOW value means that the key is - * pressed. - */ - - bool released = stm32_gpioread(GPIO_BTN_USER); - return !released; -} - -/**************************************************************************** - * Button support. - * - * Description: - * board_button_initialize() must be called to initialize button resources. - * After that, board_buttons() may be called to collect the current state - * of all buttons or board_button_irq() may be called to register button - * interrupt handlers. - * - * After board_button_initialize() has been called, board_buttons() may be - * called to collect the state of all buttons. board_buttons() returns an - * 32-bit bit set with each bit associated with a button. See the - * BUTTON_*_BIT definitions in board.h for the meaning of each bit. - * - * board_button_irq() may be called to register an interrupt handler that - * will be called when a button is depressed or released. The ID value is a - * button enumeration value that uniquely identifies a button resource. See - * the BUTTON_* definitions in board.h for the meaning of enumeration - * value. - * - ****************************************************************************/ - -#ifdef CONFIG_ARCH_IRQBUTTONS -int board_button_irq(int id, xcpt_t irqhandler, void *arg) -{ - int ret = -EINVAL; - - if (id == BUTTON_USER) - { - ret = stm32_gpiosetevent(GPIO_BTN_USER, true, true, true, irqhandler, - arg); - } - - return ret; -} -#endif -#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/stm32f0l0g0/nucleo-g070rb/src/stm32_gpio.c b/boards/arm/stm32f0l0g0/nucleo-g070rb/src/stm32_gpio.c deleted file mode 100644 index ecd0da7f94444..0000000000000 --- a/boards/arm/stm32f0l0g0/nucleo-g070rb/src/stm32_gpio.c +++ /dev/null @@ -1,364 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-g070rb/src/stm32_gpio.c - * - * SPDX-License-Identifier: BSD-3-Clause - * SPDX-FileCopyrightText: Fundação CERTI. All rights reserved. - * SPDX-FileContributor: Daniel Pereira Volpato - * SPDX-FileContributor: Guillherme da Silva Amaral - * SPDX-FileContributor: Alan Carvalho de Assis - * SPDX-FileContributor: Philippe Coval - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include -#include - -#include - -#include "chip.h" -#include "stm32_gpio.h" -#include "nucleo-g070rb.h" - -#if defined(CONFIG_DEV_GPIO) && !defined(CONFIG_GPIO_LOWER_HALF) - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -struct stm32gpio_dev_s -{ - struct gpio_dev_s gpio; - uint8_t id; -}; - -struct stm32gpint_dev_s -{ - struct stm32gpio_dev_s stm32gpio; - pin_interrupt_t callback; -}; - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -static int gpin_read(struct gpio_dev_s *dev, bool *value); -static int gpout_read(struct gpio_dev_s *dev, bool *value); -static int gpout_write(struct gpio_dev_s *dev, bool value); -static int gpint_read(struct gpio_dev_s *dev, bool *value); -static int gpint_attach(struct gpio_dev_s *dev, - pin_interrupt_t callback); -static int gpint_enable(struct gpio_dev_s *dev, bool enable); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -static const struct gpio_operations_s gpin_ops = -{ - .go_read = gpin_read, - .go_write = NULL, - .go_attach = NULL, - .go_enable = NULL, -}; - -static const struct gpio_operations_s gpout_ops = -{ - .go_read = gpout_read, - .go_write = gpout_write, - .go_attach = NULL, - .go_enable = NULL, -}; - -static const struct gpio_operations_s gpint_ops = -{ - .go_read = gpint_read, - .go_write = NULL, - .go_attach = gpint_attach, - .go_enable = gpint_enable, -}; - -#if BOARD_NGPIOIN > 0 -/* This array maps the GPIO pins used as INPUT */ - -static const uint32_t g_gpioinputs[BOARD_NGPIOIN] = -{ - GPIO_IN1, -}; - -static struct stm32gpio_dev_s g_gpin[BOARD_NGPIOIN]; -#endif - -#if BOARD_NGPIOOUT > 0 -/* This array maps the GPIO pins used as OUTPUT */ - -static const uint32_t g_gpiooutputs[BOARD_NGPIOOUT] = -{ - GPIO_OUT1, -}; - -static struct stm32gpio_dev_s g_gpout[BOARD_NGPIOOUT]; -#endif - -#if BOARD_NGPIOINT > 0 -/* This array maps the GPIO pins used as INTERRUPT INPUTS */ - -static const uint32_t g_gpiointinputs[BOARD_NGPIOINT] = -{ - GPIO_INT1, -}; - -static struct stm32gpint_dev_s g_gpint[BOARD_NGPIOINT]; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -static int stm32gpio_interrupt(int irq, void *context, void *arg) -{ - struct stm32gpint_dev_s *stm32gpint = - (struct stm32gpint_dev_s *)arg; - - DEBUGASSERT(stm32gpint != NULL && stm32gpint->callback != NULL); - gpioinfo("Interrupt! callback=%p\n", stm32gpint->callback); - - stm32gpint->callback(&stm32gpint->stm32gpio.gpio, - stm32gpint->stm32gpio.id); - return OK; -} - -static int gpin_read(struct gpio_dev_s *dev, bool *value) -{ -#if BOARD_NGPIOIN > 0 - struct stm32gpio_dev_s *stm32gpio = - (struct stm32gpio_dev_s *)dev; - - DEBUGASSERT(stm32gpio != NULL && value != NULL); - DEBUGASSERT(stm32gpio->id < BOARD_NGPIOIN); - gpioinfo("Reading...\n"); - - *value = stm32_gpioread(g_gpioinputs[stm32gpio->id]); - return OK; -#else - return ERROR; -#endif -} - -static int gpout_read(struct gpio_dev_s *dev, bool *value) -{ -#if BOARD_NGPIOOUT > 0 - struct stm32gpio_dev_s *stm32gpio = - (struct stm32gpio_dev_s *)dev; - - DEBUGASSERT(stm32gpio != NULL && value != NULL); - DEBUGASSERT(stm32gpio->id < BOARD_NGPIOOUT); - gpioinfo("Reading...\n"); - - *value = stm32_gpioread(g_gpiooutputs[stm32gpio->id]); - return OK; -#else - return ERROR; -#endif -} - -static int gpout_write(struct gpio_dev_s *dev, bool value) -{ -#if BOARD_NGPIOOUT > 0 - struct stm32gpio_dev_s *stm32gpio = - (struct stm32gpio_dev_s *)dev; - - DEBUGASSERT(stm32gpio != NULL); - DEBUGASSERT(stm32gpio->id < BOARD_NGPIOOUT); - gpioinfo("Writing %d\n", (int)value); - - stm32_gpiowrite(g_gpiooutputs[stm32gpio->id], value); - return OK; -#else - return ERROR; -#endif -} - -static int gpint_read(struct gpio_dev_s *dev, bool *value) -{ -#if BOARD_NGPIOINT > 0 - struct stm32gpint_dev_s *stm32gpint = - (struct stm32gpint_dev_s *)dev; - - DEBUGASSERT(stm32gpint != NULL && value != NULL); - DEBUGASSERT(stm32gpint->stm32gpio.id < BOARD_NGPIOINT); - gpioinfo("Reading int pin...\n"); - - *value = stm32_gpioread(g_gpiointinputs[stm32gpint->stm32gpio.id]); - return OK; -#else - return ERROR; -#endif -} - -static int gpint_attach(struct gpio_dev_s *dev, - pin_interrupt_t callback) -{ -#if BOARD_NGPIOINT > 0 - struct stm32gpint_dev_s *stm32gpint = - (struct stm32gpint_dev_s *)dev; - - gpioinfo("Attaching the callback\n"); - - /* Make sure the interrupt is disabled */ - - stm32_gpiosetevent(g_gpiointinputs[stm32gpint->stm32gpio.id], false, - false, false, NULL, NULL); - - gpioinfo("Attach %p\n", callback); - stm32gpint->callback = callback; - return OK; -#else - return ERROR; -#endif -} - -static int gpint_enable(struct gpio_dev_s *dev, bool enable) -{ -#if BOARD_NGPIOINT > 0 - struct stm32gpint_dev_s *stm32gpint = - (struct stm32gpint_dev_s *)dev; - - if (enable) - { - if (stm32gpint->callback != NULL) - { - gpioinfo("Enabling the interrupt\n"); - - /* Configure the interrupt for rising edge */ - - stm32_gpiosetevent(g_gpiointinputs[stm32gpint->stm32gpio.id], - true, false, false, stm32gpio_interrupt, - &g_gpint[stm32gpint->stm32gpio.id]); - } - } - else - { - gpioinfo("Disable the interrupt\n"); - stm32_gpiosetevent(g_gpiointinputs[stm32gpint->stm32gpio.id], - false, false, false, NULL, NULL); - } - - return OK; -#else - return ERROR; -#endif -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_gpio_initialize - * - * Description: - * Initialize GPIO drivers for use with /apps/examples/gpio - * - ****************************************************************************/ - -int stm32_gpio_initialize(void) -{ - int i; - int pincount = 0; - -#if BOARD_NGPIOIN > 0 - for (i = 0; i < BOARD_NGPIOIN; i++) - { - /* Setup and register the GPIO pin */ - - g_gpin[i].gpio.gp_pintype = GPIO_INPUT_PIN; - g_gpin[i].gpio.gp_ops = &gpin_ops; - g_gpin[i].id = i; - gpio_pin_register(&g_gpin[i].gpio, pincount); - - /* Configure the pin that will be used as input */ - - stm32_configgpio(g_gpioinputs[i]); - - pincount++; - } -#endif - -#if BOARD_NGPIOOUT > 0 - for (i = 0; i < BOARD_NGPIOOUT; i++) - { - /* Setup and register the GPIO pin */ - - g_gpout[i].gpio.gp_pintype = GPIO_OUTPUT_PIN; - g_gpout[i].gpio.gp_ops = &gpout_ops; - g_gpout[i].id = i; - gpio_pin_register(&g_gpout[i].gpio, pincount); - - /* Configure the pin that will be used as output */ - - stm32_gpiowrite(g_gpiooutputs[i], 0); - stm32_configgpio(g_gpiooutputs[i]); - - pincount++; - } -#endif - -#if BOARD_NGPIOINT > 0 - for (i = 0; i < BOARD_NGPIOINT; i++) - { - /* Setup and register the GPIO pin */ - - g_gpint[i].stm32gpio.gpio.gp_pintype = GPIO_INTERRUPT_PIN; - g_gpint[i].stm32gpio.gpio.gp_ops = &gpint_ops; - g_gpint[i].stm32gpio.id = i; - gpio_pin_register(&g_gpint[i].stm32gpio.gpio, pincount); - - /* Configure the pin that will be used as interrupt input */ - - stm32_configgpio(g_gpiointinputs[i]); - - pincount++; - } -#endif - - return 0; -} -#endif /* CONFIG_DEV_GPIO && !CONFIG_GPIO_LOWER_HALF */ diff --git a/boards/arm/stm32f0l0g0/nucleo-g070rb/src/stm32_pwm.c b/boards/arm/stm32f0l0g0/nucleo-g070rb/src/stm32_pwm.c deleted file mode 100644 index 939713a65cb8a..0000000000000 --- a/boards/arm/stm32f0l0g0/nucleo-g070rb/src/stm32_pwm.c +++ /dev/null @@ -1,208 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-g070rb/src/stm32_pwm.c - * - * SPDX-License-Identifier: BSD-3-Clause - * SPDX-FileCopyrightText: Fundação CERTI. All rights reserved. - * SPDX-FileContributor: Daniel Pereira Volpato - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include "nucleo-g070rb.h" -#include "stm32_pwm.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#define HAVE_PWM 1 -#ifndef CONFIG_PWM -# undef HAVE_PWM -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_pwm_setup - * - * Description: - * Initialize PWM and register the PWM device. - * - ****************************************************************************/ - -int stm32_pwm_setup(void) -{ -#ifdef HAVE_PWM - static bool initialized = false; - struct pwm_lowerhalf_s *pwm; - int ret; - - /* Have we already initialized? */ - - if (!initialized) - { - /* Call stm32_pwminitialize() to get an instance of the PWM interface */ - -#if defined(CONFIG_STM32F0L0G0_TIM1_PWM) - pwm = stm32_pwminitialize(1); - if (!pwm) - { - aerr("ERROR: Failed to get the STM32 PWM lower half\n"); - return -ENODEV; - } - - ret = pwm_register("/dev/pwm0", pwm); - if (ret < 0) - { - aerr("ERROR: pwm_register failed: %d\n", ret); - return ret; - } -#endif - -#if defined(CONFIG_STM32F0L0G0_TIM2_PWM) - pwm = stm32_pwminitialize(2); - if (!pwm) - { - aerr("ERROR: Failed to get the STM32 PWM lower half\n"); - return -ENODEV; - } - - ret = pwm_register("/dev/pwm1", pwm); - if (ret < 0) - { - aerr("ERROR: pwm_register failed: %d\n", ret); - return ret; - } -#endif - -#if defined(CONFIG_STM32F0L0G0_TIM3_PWM) - pwm = stm32_pwminitialize(3); - if (!pwm) - { - aerr("ERROR: Failed to get the STM32 PWM lower half\n"); - return -ENODEV; - } - - ret = pwm_register("/dev/pwm2", pwm); - if (ret < 0) - { - aerr("ERROR: pwm_register failed: %d\n", ret); - return ret; - } -#endif - -#if defined(CONFIG_STM32F0L0G0_TIM14_PWM) - pwm = stm32_pwminitialize(14); - if (!pwm) - { - aerr("ERROR: Failed to get the STM32 PWM lower half\n"); - return -ENODEV; - } - - ret = pwm_register("/dev/pwm13", pwm); - if (ret < 0) - { - aerr("ERROR: pwm_register failed: %d\n", ret); - return ret; - } -#endif - -#if defined(CONFIG_STM32F0L0G0_TIM15_PWM) - pwm = stm32_pwminitialize(15); - if (!pwm) - { - aerr("ERROR: Failed to get the STM32 PWM lower half\n"); - return -ENODEV; - } - - ret = pwm_register("/dev/pwm14", pwm); - if (ret < 0) - { - aerr("ERROR: pwm_register failed: %d\n", ret); - return ret; - } -#endif - -#if defined(CONFIG_STM32F0L0G0_TIM16_PWM) - pwm = stm32_pwminitialize(16); - if (!pwm) - { - aerr("ERROR: Failed to get the STM32 PWM lower half\n"); - return -ENODEV; - } - - ret = pwm_register("/dev/pwm15", pwm); - if (ret < 0) - { - aerr("ERROR: pwm_register failed: %d\n", ret); - return ret; - } -#endif - -#if defined(CONFIG_STM32F0L0G0_TIM17_PWM) - pwm = stm32_pwminitialize(17); - if (!pwm) - { - aerr("ERROR: Failed to get the STM32 PWM lower half\n"); - return -ENODEV; - } - - ret = pwm_register("/dev/pwm16", pwm); - if (ret < 0) - { - aerr("ERROR: pwm_register failed: %d\n", ret); - return ret; - } -#endif - - /* Now we are initialized */ - - initialized = true; - } - - return OK; -#else - return -ENODEV; -#endif -} diff --git a/boards/arm/stm32f0l0g0/nucleo-g070rb/src/stm32_timer.c b/boards/arm/stm32f0l0g0/nucleo-g070rb/src/stm32_timer.c deleted file mode 100644 index 9442536d35ff2..0000000000000 --- a/boards/arm/stm32f0l0g0/nucleo-g070rb/src/stm32_timer.c +++ /dev/null @@ -1,81 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-g070rb/src/stm32_timer.c - * - * SPDX-License-Identifier: BSD-3-Clause - * SPDX-FileCopyrightText: Fundação CERTI. All rights reserved. - * SPDX-FileContributor: Daniel Pereira Volpato - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include - -#include - -#include "stm32_tim.h" -#include "nucleo-g070rb.h" - -#ifdef CONFIG_TIMER - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_timer_driver_setup - * - * Description: - * Configure the timer driver. - * - * Input Parameters: - * devpath - The full path to the timer device. This should be of the form - * /dev/timer0 - * timer - The timer's number. - * - * Returned Value: - * Zero (OK) is returned on success; A negated errno value is returned - * to indicate the nature of any failure. - * - ****************************************************************************/ - -int stm32_timer_driver_setup(const char *devpath, int timer) -{ - return stm32_timer_initialize(devpath, timer); -} - -#endif /* CONFIG_TIMER */ diff --git a/boards/arm/stm32f0l0g0/nucleo-g071rb/CMakeLists.txt b/boards/arm/stm32f0l0g0/nucleo-g071rb/CMakeLists.txt deleted file mode 100644 index b94721d67afc0..0000000000000 --- a/boards/arm/stm32f0l0g0/nucleo-g071rb/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32f0l0g0/nucleo-g071rb/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32f0l0g0/nucleo-g071rb/configs/nsh/defconfig b/boards/arm/stm32f0l0g0/nucleo-g071rb/configs/nsh/defconfig deleted file mode 100644 index ee39c1d282180..0000000000000 --- a/boards/arm/stm32f0l0g0/nucleo-g071rb/configs/nsh/defconfig +++ /dev/null @@ -1,49 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_NSH_ARGCAT is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="nucleo-g071rb" -CONFIG_ARCH_BOARD_NUCLEO_G071RB=y -CONFIG_ARCH_CHIP="stm32f0l0g0" -CONFIG_ARCH_CHIP_STM32G071RB=y -CONFIG_ARCH_CHIP_STM32G0=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=2796 -CONFIG_BUILTIN=y -CONFIG_DISABLE_ENVIRON=y -CONFIG_DISABLE_MOUNTPOINT=y -CONFIG_DISABLE_MQUEUE=y -CONFIG_DISABLE_POSIX_TIMERS=y -CONFIG_DISABLE_PSEUDOFS_OPERATIONS=y -CONFIG_EXAMPLES_HELLO=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INIT_STACKSIZE=1536 -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=64 -CONFIG_NSH_READLINE=y -CONFIG_NUNGET_CHARS=0 -CONFIG_POSIX_SPAWN_DEFAULT_STACKSIZE=1536 -CONFIG_PTHREAD_MUTEX_UNSAFE=y -CONFIG_PTHREAD_STACK_DEFAULT=1536 -CONFIG_RAM_SIZE=20480 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=19 -CONFIG_START_MONTH=5 -CONFIG_START_YEAR=2013 -CONFIG_STDIO_DISABLE_BUFFERING=y -CONFIG_STM32F0L0G0_PWR=y -CONFIG_STM32F0L0G0_USART2=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f0l0g0/nucleo-g071rb/include/board.h b/boards/arm/stm32f0l0g0/nucleo-g071rb/include/board.h deleted file mode 100644 index a6bba4ae7d9ea..0000000000000 --- a/boards/arm/stm32f0l0g0/nucleo-g071rb/include/board.h +++ /dev/null @@ -1,210 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-g071rb/include/board.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __BOARDS_ARM_STM32F0L0G0_NUCLEO_G071RB_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32F0L0G0_NUCLEO_G071RB_INCLUDE_BOARD_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#ifndef __ASSEMBLY__ -# include -# include -#endif - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Clocking *****************************************************************/ - -/* HSI - Internal 16 MHz RC Oscillator - * LSI - 32 KHz RC - * HSE - 8 MHz from MCO output of ST-LINK (disabled by default) - * LSE - 32.768 kHz - */ - -#define STM32_BOARD_XTAL 8000000ul - -#define STM32_HSI_FREQUENCY 16000000ul -#define STM32_LSI_FREQUENCY 32000 /* Between 30kHz and 60kHz */ -#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL -#define STM32_LSE_FREQUENCY 32768 /* X2 on board */ - -/* Main PLL Configuration. - * - * PLL source is HSI = 16,000,000 - * - * PLL_VCOx = (STM32_HSE_FREQUENCY / PLLM) * PLLN - * Subject to: - * - * 1 <= PLLM <= 8 - * 8 <= PLLN <= 86 - * 4 MHz <= PLL_IN <= 16MHz - * 64 MHz <= PLL_VCO <= 344MHz - * SYSCLK = PLLRCLK = PLL_VCO / PLLR - * - */ - -/* PLL source is HSI, PLLN=50, PLLM=4 - * PLLP enable, PLLQ enable, PLLR enable - * - * 2 <= PLLP <= 32 - * 2 <= PLLQ <= 8 - * 2 <= PLLR <= 8 - * - * PLLR <= 64MHz - * PLLQ <= 128MHz - * PLLP <= 128MHz - * - * PLL_VCO = (16,000,000 / 4) * 50 = 200 MHz - * - * PLLP = PLL_VCO/4 = 200 MHz / 4 = 40 MHz - * PLLQ = PLL_VCO/4 = 200 MHz / 4 = 40 MHz - * PLLR = PLL_VCO/4 = 200 MHz / 4 = 40 MHz - */ - -#define STM32_PLLCFG_PLLSRC RCC_PLLCFG_PLLSRC_HSI -#define STM32_PLLCFG_PLLCFG (RCC_PLLCFG_PLLPEN | \ - RCC_PLLCFG_PLLQEN | \ - RCC_PLLCFG_PLLREN) - -#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(4) -#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(50) -#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP(4) -#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(4) -#define STM32_PLLCFG_PLLR RCC_PLLCFG_PLLR(4) - -#define STM32_VCO_FREQUENCY ((STM32_HSE_FREQUENCY / 2) * 50) -#define STM32_PLLP_FREQUENCY (STM32_VCO_FREQUENCY / 4) -#define STM32_PLLQ_FREQUENCY (STM32_VCO_FREQUENCY / 4) -#define STM32_PLLR_FREQUENCY (STM32_VCO_FREQUENCY / 4) - -/* Use the PLL and set the SYSCLK source to be the PLLR (40MHz) */ - -#define STM32_SYSCLK_SW RCC_CFGR_SW_PLL -#define STM32_SYSCLK_SWS RCC_CFGR_SWS_PLL -#define STM32_SYSCLK_FREQUENCY (STM32_PLLR_FREQUENCY) - -/* AHB clock (HCLK) is SYSCLK (40MHz) */ - -#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK -#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY - -/* APB1 clock (PCLK1) is HCLK/2 (20MHz) */ - -#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd2 -#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/2) - -/* TODO: timers */ - -/* LED definitions **********************************************************/ - -/* The Nucleo LO73RZ board has three LEDs. Two of these are controlled by - * logic on the board and are not available for software control: - * - * LD1 COM: LD1 default status is red. LD1 turns to green to indicate that - * communications are in progress between the PC and the - * ST-LINK/V2-1. - * LD3 PWR: red LED indicates that the board is powered. - * - * And one can be controlled by software: - * - * User LD2: green LED is a user LED connected to the I/O PA5 of the - * STM32LO73RZ. - * - * If CONFIG_ARCH_LEDS is not defined, then the user can control the LED in - * any way. The following definition is used to access the LED. - */ - -/* LED index values for use with board_userled() */ - -#define BOARD_LED1 0 /* User LD2 */ -#define BOARD_NLEDS 1 - -/* LED bits for use with board_userled_all() */ - -#define BOARD_LED1_BIT (1 << BOARD_LED1) - -/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the LED on board - * the Nucleo LO73RZ. The following definitions describe how NuttX controls - * the LED: - * - * SYMBOL Meaning LED1 state - * ------------------ ----------------------- ---------- - * LED_STARTED NuttX has been started OFF - * LED_HEAPALLOCATE Heap has been allocated OFF - * LED_IRQSENABLED Interrupts enabled OFF - * LED_STACKCREATED Idle stack created ON - * LED_INIRQ In an interrupt No change - * LED_SIGNAL In a signal handler No change - * LED_ASSERTION An assertion failed No change - * LED_PANIC The system has crashed Blinking - * LED_IDLE STM32 is in sleep mode Not used - */ - -#define LED_STARTED 0 -#define LED_HEAPALLOCATE 0 -#define LED_IRQSENABLED 0 -#define LED_STACKCREATED 1 -#define LED_INIRQ 2 -#define LED_SIGNAL 2 -#define LED_ASSERTION 2 -#define LED_PANIC 1 - -/* Button definitions *******************************************************/ - -/* The Nucleo LO73RZ supports two buttons; only one button is controllable - * by software: - * - * B1 USER: user button connected to the I/O PC13 of the STM32LO73RZ. - * B2 RESET: push button connected to NRST is used to RESET the - * STM32LO73RZ. - */ - -#define BUTTON_USER 0 -#define NUM_BUTTONS 1 - -#define BUTTON_USER_BIT (1 << BUTTON_USER) - -/* Alternate function pin selections ****************************************/ - -/* USART */ - -/* By default the USART2 is connected to STLINK Virtual COM Port: - * USART2_RX - PA3 - * USART2_TX - PA2 - */ - -#define GPIO_USART2_RX (GPIO_USART2_RX_1|GPIO_SPEED_HIGH) /* PA3 */ -#define GPIO_USART2_TX (GPIO_USART2_TX_1|GPIO_SPEED_HIGH) /* PA2 */ - -/* DMA channels *************************************************************/ - -/* ADC */ - -#define ADC1_DMA_CHAN DMACHAN_ADC1 /* DMA1_CH1 */ - -#endif /* __BOARDS_ARM_STM32F0L0G0_NUCLEO_LO73RZ_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32f0l0g0/nucleo-g071rb/scripts/Make.defs b/boards/arm/stm32f0l0g0/nucleo-g071rb/scripts/Make.defs deleted file mode 100644 index e7c7c7f21aff5..0000000000000 --- a/boards/arm/stm32f0l0g0/nucleo-g071rb/scripts/Make.defs +++ /dev/null @@ -1,41 +0,0 @@ -############################################################################ -# boards/arm/stm32f0l0g0/nucleo-g071rb/scripts/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/.config -include $(TOPDIR)/tools/Config.mk -include $(TOPDIR)/arch/arm/src/armv6-m/Toolchain.defs - -LDSCRIPT = ld.script -ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) - -ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 - -CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) -CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) -CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -AFLAGS := $(CFLAGS) -D__ASSEMBLY__ - -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections -LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32f0l0g0/nucleo-g071rb/scripts/ld.script b/boards/arm/stm32f0l0g0/nucleo-g071rb/scripts/ld.script deleted file mode 100644 index b545dc383e750..0000000000000 --- a/boards/arm/stm32f0l0g0/nucleo-g071rb/scripts/ld.script +++ /dev/null @@ -1,115 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-g071rb/scripts/ld.script - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* The STM32GO71RB has 128Kb of FLASH beginning at address 0x0800:0000. - * 32Kb/36Kb of SRAM - * - * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 - * where the code expects to begin execution by jumping to the entry point in - * the 0x0800:0000 address range. - */ - -MEMORY -{ - flash (rx) : ORIGIN = 0x08000000, LENGTH = 128K - sram (rwx) : ORIGIN = 0x20000000, LENGTH = 36K -} - -OUTPUT_ARCH(arm) -EXTERN(_vectors) -ENTRY(_stext) -SECTIONS -{ - .text : { - _stext = ABSOLUTE(.); - *(.vectors) - *(.text .text.*) - *(.fixup) - *(.gnu.warning) - *(.rodata .rodata.*) - *(.gnu.linkonce.t.*) - *(.glue_7) - *(.glue_7t) - *(.got) - *(.gcc_except_table) - *(.gnu.linkonce.r.*) - _etext = ABSOLUTE(.); - } > flash - - .init_section : ALIGN(4) { - _sinit = ABSOLUTE(.); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) - KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) - _einit = ABSOLUTE(.); - } > flash - - .ARM.extab : ALIGN(4) { - *(.ARM.extab*) - } > flash - - .ARM.exidx : ALIGN(4) { - __exidx_start = ABSOLUTE(.); - *(.ARM.exidx*) - __exidx_end = ABSOLUTE(.); - } > flash - - _eronly = ABSOLUTE(.); - - /* The RAM vector table (if present) should lie at the beginning of SRAM */ - - .ram_vectors : { - *(.ram_vectors) - } > sram - - .data : ALIGN(4) { - _sdata = ABSOLUTE(.); - *(.data .data.*) - *(.gnu.linkonce.d.*) - CONSTRUCTORS - . = ALIGN(4); - _edata = ABSOLUTE(.); - } > sram AT > flash - - .bss : ALIGN(4) { - _sbss = ABSOLUTE(.); - *(.bss .bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - . = ALIGN(4); - _ebss = ABSOLUTE(.); - } > sram - - /* Stabs debugging sections. */ - - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_info 0 : { *(.debug_info) } - .debug_line 0 : { *(.debug_line) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_aranges 0 : { *(.debug_aranges) } -} diff --git a/boards/arm/stm32f0l0g0/nucleo-g071rb/src/CMakeLists.txt b/boards/arm/stm32f0l0g0/nucleo-g071rb/src/CMakeLists.txt deleted file mode 100644 index b0e6eae77fbcc..0000000000000 --- a/boards/arm/stm32f0l0g0/nucleo-g071rb/src/CMakeLists.txt +++ /dev/null @@ -1,37 +0,0 @@ -# ############################################################################## -# boards/arm/stm32f0l0g0/nucleo-g071rb/src/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -set(SRCS stm32_boot.c stm32_bringup.c) - -if(CONFIG_ARCH_LEDS) - list(APPEND SRCS stm32_autoleds.c) -else() - list(APPEND SRCS stm32_userleds.c) -endif() - -if(CONFIG_ARCH_BUTTONS) - list(APPEND SRCS stm32_buttons.c) -endif() - -target_sources(board PRIVATE ${SRCS}) - -set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/ld.script") diff --git a/boards/arm/stm32f0l0g0/nucleo-g071rb/src/Make.defs b/boards/arm/stm32f0l0g0/nucleo-g071rb/src/Make.defs deleted file mode 100644 index 75e78e8bc721c..0000000000000 --- a/boards/arm/stm32f0l0g0/nucleo-g071rb/src/Make.defs +++ /dev/null @@ -1,39 +0,0 @@ -############################################################################ -# boards/arm/stm32f0l0g0/nucleo-g071rb/src/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/Make.defs - -CSRCS = stm32_boot.c stm32_bringup.c - -ifeq ($(CONFIG_ARCH_LEDS),y) -CSRCS += stm32_autoleds.c -else -CSRCS += stm32_userleds.c -endif - -ifeq ($(CONFIG_ARCH_BUTTONS),y) -CSRCS += stm32_buttons.c -endif - -DEPPATH += --dep-path board -VPATH += :board -CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32f0l0g0/nucleo-g071rb/src/stm32_autoleds.c b/boards/arm/stm32f0l0g0/nucleo-g071rb/src/stm32_autoleds.c deleted file mode 100644 index e0c9af572f43e..0000000000000 --- a/boards/arm/stm32f0l0g0/nucleo-g071rb/src/stm32_autoleds.c +++ /dev/null @@ -1,81 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-g071rb/src/stm32_autoleds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include - -#include "stm32_gpio.h" -#include "nucleo-g071rb.h" - -#include - -#ifdef CONFIG_ARCH_LEDS - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_autoled_initialize - ****************************************************************************/ - -void board_autoled_initialize(void) -{ - /* Configure LED1 GPIO for output */ - - stm32_configgpio(GPIO_LED1); -} - -/**************************************************************************** - * Name: board_autoled_on - ****************************************************************************/ - -void board_autoled_on(int led) -{ - if (led == BOARD_LED1) - { - stm32_gpiowrite(GPIO_LED1, true); - } -} - -/**************************************************************************** - * Name: board_autoled_off - ****************************************************************************/ - -void board_autoled_off(int led) -{ - if (led == BOARD_LED1) - { - stm32_gpiowrite(GPIO_LED1, false); - } -} - -#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32f0l0g0/nucleo-g071rb/src/stm32_boot.c b/boards/arm/stm32f0l0g0/nucleo-g071rb/src/stm32_boot.c deleted file mode 100644 index a0104c3a648f4..0000000000000 --- a/boards/arm/stm32f0l0g0/nucleo-g071rb/src/stm32_boot.c +++ /dev/null @@ -1,85 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-g071rb/src/stm32_boot.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include "nucleo-g071rb.h" - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_boardinitialize - * - * Description: - * All STM32 architectures must provide the following entry point. This - * entry point is called early in the initialization -- after all memory - * has been configured and mapped but before any devices have been - * initialized. - * - ****************************************************************************/ - -void stm32_boardinitialize(void) -{ -#ifdef CONFIG_ARCH_LEDS - /* Configure on-board LEDs if LED support has been selected. */ - - board_autoled_initialize(); -#endif - -#ifdef CONFIG_STM32F0L0G0_SPI - /* Configure SPI chip selects */ - - stm32_spidev_initialize(); -#endif -} - -/**************************************************************************** - * Name: board_late_initialize - * - * Description: - * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional - * initialization call will be performed in the boot-up sequence to a - * function called board_late_initialize(). board_late_initialize() will - * be called immediately after up_initialize() is called and just before - * the initial application is started. This additional initialization - * phase may be used, for example, to initialize board-specific device - * drivers. - * - ****************************************************************************/ - -#ifdef CONFIG_BOARD_LATE_INITIALIZE -void board_late_initialize(void) -{ - /* Perform board-specific initialization */ - - stm32_bringup(); -} -#endif diff --git a/boards/arm/stm32f0l0g0/nucleo-g071rb/src/stm32_bringup.c b/boards/arm/stm32f0l0g0/nucleo-g071rb/src/stm32_bringup.c deleted file mode 100644 index cea5f3eab4e73..0000000000000 --- a/boards/arm/stm32f0l0g0/nucleo-g071rb/src/stm32_bringup.c +++ /dev/null @@ -1,152 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-g071rb/src/stm32_bringup.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include - -#include "nucleo-g071rb.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#undef HAVE_LEDS -#undef HAVE_DAC - -#if !defined(CONFIG_ARCH_LEDS) && defined(CONFIG_USERLED_LOWER) -# define HAVE_LEDS 1 -#endif - -#if defined(CONFIG_DAC) -# define HAVE_DAC1 1 -# define HAVE_DAC2 1 -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_bringup - * - * Description: - * Perform architecture-specific initialization - * - * CONFIG_BOARD_LATE_INITIALIZE=y : - * Called from board_late_initialize(). - * - ****************************************************************************/ - -int stm32_bringup(void) -{ - int ret; - -#ifdef HAVE_LEDS - /* Register the LED driver */ - - ret = userled_lower_initialize(LED_DRIVER_PATH); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: userled_lower_initialize() failed: %d\n", - ret); - return ret; - } -#endif - -#ifdef CONFIG_ADC - /* Initialize ADC and register the ADC driver. */ - - ret = stm32_adc_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_adc_setup failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_DAC - /* Initialize DAC and register the DAC driver. */ - - ret = stm32_dac_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_dac_setup failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_COMP - /* Initialize COMP and register the COMP driver. */ - - ret = stm32_comp_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_comp_setup failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_OPAMP - /* Initialize OPAMP and register the OPAMP driver. */ - - ret = stm32_opamp_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_opamp_setup failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_WL_NRF24L01 - ret = stm32_wlinitialize(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: Failed to initialize wireless driver: %d\n", - ret); - } -#endif /* CONFIG_WL_NRF24L01 */ - -#ifdef CONFIG_LPWAN_SX127X - ret = stm32_lpwaninitialize(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: Failed to initialize wireless driver: %d\n", - ret); - } -#endif /* CONFIG_LPWAN_SX127X */ - -#ifdef CONFIG_CL_MFRC522 - ret = stm32_mfrc522initialize("/dev/rfid0"); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_mfrc522initialize() failed: %d\n", ret); - } -#endif /* CONFIG_CL_MFRC522 */ - - UNUSED(ret); - return OK; -} diff --git a/boards/arm/stm32f0l0g0/nucleo-g071rb/src/stm32_buttons.c b/boards/arm/stm32f0l0g0/nucleo-g071rb/src/stm32_buttons.c deleted file mode 100644 index a8f4576836445..0000000000000 --- a/boards/arm/stm32f0l0g0/nucleo-g071rb/src/stm32_buttons.c +++ /dev/null @@ -1,118 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-g071rb/src/stm32_buttons.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include "stm32_gpio.h" -#include "nucleo-g071rb.h" - -#include - -#ifdef CONFIG_ARCH_BUTTONS - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_button_initialize - * - * Description: - * board_button_initialize() must be called to initialize button resources. - * After that, board_buttons() may be called to collect the current state - * of all buttons or board_button_irq() may be called to register button - * interrupt handlers. - * - ****************************************************************************/ - -uint32_t board_button_initialize(void) -{ - /* Configure the single button as an input. NOTE that EXTI interrupts are - * also configured for the pin. - */ - - stm32_configgpio(GPIO_BTN_USER); - return NUM_BUTTONS; -} - -/**************************************************************************** - * Name: board_buttons - ****************************************************************************/ - -uint32_t board_buttons(void) -{ - /* Check that state of each USER button. A LOW value means that the key is - * pressed. - */ - - bool released = stm32_gpioread(GPIO_BTN_USER); - return !released; -} - -/**************************************************************************** - * Button support. - * - * Description: - * board_button_initialize() must be called to initialize button resources. - * After that, board_buttons() may be called to collect the current state - * of all buttons or board_button_irq() may be called to register button - * interrupt handlers. - * - * After board_button_initialize() has been called, board_buttons() may be - * called to collect the state of all buttons. board_buttons() returns an - * 32-bit bit set with each bit associated with a button. See the - * BUTTON_*_BIT definitions in board.h for the meaning of each bit. - * - * board_button_irq() may be called to register an interrupt handler that - * will be called when a button is depressed or released. The ID value is a - * button enumeration value that uniquely identifies a button resource. See - * the BUTTON_* definitions in board.h for the meaning of enumeration - * value. - * - ****************************************************************************/ - -#ifdef CONFIG_ARCH_IRQBUTTONS -int board_button_irq(int id, xcpt_t irqhandler, void *arg) -{ - int ret = -EINVAL; - - if (id == BUTTON_USER) - { - ret = stm32_gpiosetevent(GPIO_BTN_USER, true, true, true, - irqhandler, arg); - } - - return ret; -} -#endif -#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/stm32f0l0g0/nucleo-g0b1re/CMakeLists.txt b/boards/arm/stm32f0l0g0/nucleo-g0b1re/CMakeLists.txt deleted file mode 100644 index f161ea4448aa7..0000000000000 --- a/boards/arm/stm32f0l0g0/nucleo-g0b1re/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32f0l0g0/nucleo-g0b1re/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32f0l0g0/nucleo-g0b1re/configs/adc/defconfig b/boards/arm/stm32f0l0g0/nucleo-g0b1re/configs/adc/defconfig deleted file mode 100644 index d56da04bd24d0..0000000000000 --- a/boards/arm/stm32f0l0g0/nucleo-g0b1re/configs/adc/defconfig +++ /dev/null @@ -1,56 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_NSH_ARGCAT is not set -CONFIG_ADC=y -CONFIG_ANALOG=y -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="nucleo-g0b1re" -CONFIG_ARCH_BOARD_NUCLEO_G0B1RE=y -CONFIG_ARCH_CHIP="stm32f0l0g0" -CONFIG_ARCH_CHIP_STM32G0=y -CONFIG_ARCH_CHIP_STM32G0B1RE=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=4164 -CONFIG_BUILTIN=y -CONFIG_DEBUG_FULLOPT=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_DISABLE_ENVIRON=y -CONFIG_DISABLE_MQUEUE=y -CONFIG_DISABLE_POSIX_TIMERS=y -CONFIG_DISABLE_PSEUDOFS_OPERATIONS=y -CONFIG_EXAMPLES_ADC=y -CONFIG_EXAMPLES_ADC_GROUPSIZE=1 -CONFIG_EXAMPLES_ADC_NSAMPLES=1 -CONFIG_EXAMPLES_HELLO=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INIT_STACKSIZE=1536 -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=64 -CONFIG_NSH_READLINE=y -CONFIG_NUNGET_CHARS=0 -CONFIG_POSIX_SPAWN_DEFAULT_STACKSIZE=1536 -CONFIG_PTHREAD_MUTEX_UNSAFE=y -CONFIG_PTHREAD_STACK_DEFAULT=1536 -CONFIG_RAM_SIZE=147456 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=19 -CONFIG_START_MONTH=5 -CONFIG_START_YEAR=2013 -CONFIG_STDIO_DISABLE_BUFFERING=y -CONFIG_STM32F0L0G0_ADC1=y -CONFIG_STM32F0L0G0_PWR=y -CONFIG_STM32F0L0G0_USART2=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f0l0g0/nucleo-g0b1re/configs/adc_dma/defconfig b/boards/arm/stm32f0l0g0/nucleo-g0b1re/configs/adc_dma/defconfig deleted file mode 100644 index e85080bc6dd61..0000000000000 --- a/boards/arm/stm32f0l0g0/nucleo-g0b1re/configs/adc_dma/defconfig +++ /dev/null @@ -1,67 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_NSH_ARGCAT is not set -CONFIG_ADC=y -CONFIG_ADC_FIFOSIZE=64 -CONFIG_ANALOG=y -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="nucleo-g0b1re" -CONFIG_ARCH_BOARD_NUCLEO_G0B1RE=y -CONFIG_ARCH_CHIP="stm32f0l0g0" -CONFIG_ARCH_CHIP_STM32G0=y -CONFIG_ARCH_CHIP_STM32G0B1RE=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARDCTL=y -CONFIG_BOARD_LOOPSPERMSEC=4164 -CONFIG_BUILTIN=y -CONFIG_DEBUG_FEATURES=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_DISABLE_ENVIRON=y -CONFIG_DISABLE_MOUNTPOINT=y -CONFIG_DISABLE_MQUEUE=y -CONFIG_DISABLE_POSIX_TIMERS=y -CONFIG_DISABLE_PSEUDOFS_OPERATIONS=y -CONFIG_EXAMPLES_ADC=y -CONFIG_EXAMPLES_ADC_NSAMPLES=1 -CONFIG_EXAMPLES_HELLO=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INIT_STACKSIZE=1536 -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=64 -CONFIG_NSH_READLINE=y -CONFIG_NUNGET_CHARS=0 -CONFIG_POSIX_SPAWN_DEFAULT_STACKSIZE=1536 -CONFIG_PTHREAD_MUTEX_UNSAFE=y -CONFIG_PTHREAD_STACK_DEFAULT=1536 -CONFIG_RAM_SIZE=147456 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=19 -CONFIG_START_MONTH=5 -CONFIG_START_YEAR=2013 -CONFIG_STDIO_DISABLE_BUFFERING=y -CONFIG_STM32F0L0G0_ADC1=y -CONFIG_STM32F0L0G0_ADC1_CONTINUOUS=y -CONFIG_STM32F0L0G0_ADC1_DMA=y -CONFIG_STM32F0L0G0_ADC1_DMA_CFG=1 -CONFIG_STM32F0L0G0_ADC_CHANGE_SAMPLETIME=y -CONFIG_STM32F0L0G0_ADC_LL_OPS=y -CONFIG_STM32F0L0G0_ADC_OVERSAMPLE=y -CONFIG_STM32F0L0G0_ADC_OVSR=7 -CONFIG_STM32F0L0G0_ADC_OVSS=4 -CONFIG_STM32F0L0G0_DMA1=y -CONFIG_STM32F0L0G0_PWR=y -CONFIG_STM32F0L0G0_USART2=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f0l0g0/nucleo-g0b1re/configs/nsh/defconfig b/boards/arm/stm32f0l0g0/nucleo-g0b1re/configs/nsh/defconfig deleted file mode 100644 index 5ac96442f86b0..0000000000000 --- a/boards/arm/stm32f0l0g0/nucleo-g0b1re/configs/nsh/defconfig +++ /dev/null @@ -1,49 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_NSH_ARGCAT is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="nucleo-g0b1re" -CONFIG_ARCH_BOARD_NUCLEO_G0B1RE=y -CONFIG_ARCH_CHIP="stm32f0l0g0" -CONFIG_ARCH_CHIP_STM32G0=y -CONFIG_ARCH_CHIP_STM32G0B1RE=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=4164 -CONFIG_BUILTIN=y -CONFIG_DISABLE_ENVIRON=y -CONFIG_DISABLE_MOUNTPOINT=y -CONFIG_DISABLE_MQUEUE=y -CONFIG_DISABLE_POSIX_TIMERS=y -CONFIG_DISABLE_PSEUDOFS_OPERATIONS=y -CONFIG_EXAMPLES_HELLO=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INIT_STACKSIZE=1536 -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=64 -CONFIG_NSH_READLINE=y -CONFIG_NUNGET_CHARS=0 -CONFIG_POSIX_SPAWN_DEFAULT_STACKSIZE=1536 -CONFIG_PTHREAD_MUTEX_UNSAFE=y -CONFIG_PTHREAD_STACK_DEFAULT=1536 -CONFIG_RAM_SIZE=147456 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=19 -CONFIG_START_MONTH=5 -CONFIG_START_YEAR=2013 -CONFIG_STDIO_DISABLE_BUFFERING=y -CONFIG_STM32F0L0G0_PWR=y -CONFIG_STM32F0L0G0_USART2=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f0l0g0/nucleo-g0b1re/include/board.h b/boards/arm/stm32f0l0g0/nucleo-g0b1re/include/board.h deleted file mode 100644 index 03888c49925dd..0000000000000 --- a/boards/arm/stm32f0l0g0/nucleo-g0b1re/include/board.h +++ /dev/null @@ -1,224 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-g0b1re/include/board.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __BOARDS_ARM_STM32F0L0G0_NUCLEO_G0B1RE_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32F0L0G0_NUCLEO_G0B1RE_INCLUDE_BOARD_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#ifndef __ASSEMBLY__ -# include -# include -#endif - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Clocking *****************************************************************/ - -/* HSI - Internal 16 MHz RC Oscillator - * LSI - 32 KHz RC - * HSE - 8 MHz from MCO output of ST-LINK (disabled by default) - * LSE - 32.768 kHz - */ - -#define STM32_BOARD_XTAL 8000000ul - -#define STM32_HSI_FREQUENCY 16000000ul -#define STM32_LSI_FREQUENCY 32000 /* Between 30kHz and 60kHz */ -#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL -#define STM32_LSE_FREQUENCY 32768 /* X2 on board */ - -/* Main PLL Configuration. - * - * PLL source is HSI = 16,000,000 - * - * PLL_VCOx = (STM32_HSE_FREQUENCY / PLLM) * PLLN - * Subject to: - * - * 1 <= PLLM <= 8 - * 8 <= PLLN <= 86 - * 4 MHz <= PLL_IN <= 16MHz - * 64 MHz <= PLL_VCO <= 344MHz - * SYSCLK = PLLRCLK = PLL_VCO / PLLR - * - */ - -/* PLL source is HSI, PLLN=50, PLLM=4 - * PLLP enable, PLLQ enable, PLLR enable - * - * 2 <= PLLP <= 32 - * 2 <= PLLQ <= 8 - * 2 <= PLLR <= 8 - * - * PLLR <= 64MHz - * PLLQ <= 64MHz - * PLLP <= 64MHz - * - * PLL_VCO = (16,000,000 / 2) * 32 = 256 MHz - * - * PLLP = PLL_VCO/4 = 256 MHz / 4 = 64 MHz - * PLLQ = PLL_VCO/4 = 256 MHz / 4 = 64 MHz - * PLLR = PLL_VCO/4 = 256 MHz / 4 = 64 MHz - */ - -#define STM32_PLLCFG_PLLSRC RCC_PLLCFG_PLLSRC_HSI -#define STM32_PLLCFG_PLLCFG (RCC_PLLCFG_PLLPEN | \ - RCC_PLLCFG_PLLQEN | \ - RCC_PLLCFG_PLLREN) - -#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(2) -#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(64) -#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP(4) -#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(4) -#define STM32_PLLCFG_PLLR RCC_PLLCFG_PLLR(4) - -#define STM32_VCO_FREQUENCY ((STM32_HSI_FREQUENCY / 2) * 64) -#define STM32_PLLP_FREQUENCY (STM32_VCO_FREQUENCY / 4) -#define STM32_PLLQ_FREQUENCY (STM32_VCO_FREQUENCY / 4) -#define STM32_PLLR_FREQUENCY (STM32_VCO_FREQUENCY / 4) - -/* Use the PLL and set the SYSCLK source to be the PLLR (40MHz) */ - -#define STM32_SYSCLK_SW RCC_CFGR_SW_PLL -#define STM32_SYSCLK_SWS RCC_CFGR_SWS_PLL -#define STM32_SYSCLK_FREQUENCY (STM32_PLLR_FREQUENCY) - -/* AHB clock (HCLK) is SYSCLK (40MHz) */ - -#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK -#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY - -/* APB1 clock (PCLK1) is HCLK/2 (20MHz) */ - -#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd2 -#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/2) - -/* ADC1 clock prescaled is SYSCLK (64MHz) / 2 = 32MHz */ - -#define STM32_ADC_CLK_FREQUENCY STM32_SYSCLK_FREQUENCY -#define STM32_RCC_CCIPR_ADCSEL RCC_CCIPR_ADCSEL_SYSCLK -#define STM32_ADC_CFGR2_CKMODE ADC_CFGR2_CKMODE_ADCCLK -#define STM32_ADC_CCR_PRESC ADC_CCR_PRESC_DIV2 - -/* LED definitions **********************************************************/ - -/* The Nucleo G0B1RE board has four LEDs. Three of these are controlled by - * logic on the board and are not available for software control: - * - * LD1 COM: LD1 default status is red. LD1 turns to green to indicate that - * communications are in progress between the PC and the - * ST-LINK/V2-1. - * - * LD2 5V_USB_CHG: Green LED is on when board is powered by 5V source. - * - * LD3 PWR: red LED indicates that the board is powered. - * - * And one can be controlled by software: - * - * User LD4: green LED is a user LED connected to the I/O PA5 of the - * STM32G0B1RE. - * - * If CONFIG_ARCH_LEDS is not defined, then the user can control the LED in - * any way. The following definition is used to access the LED. - */ - -/* LED index values for use with board_userled() */ - -#define BOARD_LED1 0 /* User LD4 */ -#define BOARD_NLEDS 1 - -/* LED bits for use with board_userled_all() */ - -#define BOARD_LED1_BIT (1 << BOARD_LED1) - -/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the LED on board - * the Nucleo G0B1RE. The following definitions describe how NuttX controls - * the LED: - * - * SYMBOL Meaning LED1 state - * ------------------ ----------------------- ---------- - * LED_STARTED NuttX has been started OFF - * LED_HEAPALLOCATE Heap has been allocated OFF - * LED_IRQSENABLED Interrupts enabled OFF - * LED_STACKCREATED Idle stack created ON - * LED_INIRQ In an interrupt No change - * LED_SIGNAL In a signal handler No change - * LED_ASSERTION An assertion failed No change - * LED_PANIC The system has crashed Blinking - * LED_IDLE STM32 is in sleep mode Not used - */ - -#define LED_STARTED 0 -#define LED_HEAPALLOCATE 0 -#define LED_IRQSENABLED 0 -#define LED_STACKCREATED 1 -#define LED_INIRQ 2 -#define LED_SIGNAL 2 -#define LED_ASSERTION 2 -#define LED_PANIC 1 - -/* Button definitions *******************************************************/ - -/* The Nucleo G0B1RE supports two buttons; only one button is controllable - * by software: - * - * B1 USER: user button connected to the I/O PC13 of the MCU. - * B2 RESET: push button connected to NRST is used to RESET the MCU. - */ - -#define BUTTON_USER 0 -#define NUM_BUTTONS 1 - -#define BUTTON_USER_BIT (1 << BUTTON_USER) - -/* Alternate function pin selections ****************************************/ - -/* USART */ - -/* By default the USART2 is connected to STLINK Virtual COM Port: - * USART2_RX - PA3 - * USART2_TX - PA2 - */ - -#define GPIO_USART2_RX (GPIO_USART2_RX_1|GPIO_SPEED_HIGH) /* PA3 */ -#define GPIO_USART2_TX (GPIO_USART2_TX_1|GPIO_SPEED_HIGH) /* PA2 */ - -/* ADC */ - -#define GPIO_ADC1_A0 GPIO_ADC1_IN0_1 -#define GPIO_ADC1_A1 GPIO_ADC1_IN1_1 -#define GPIO_ADC1_A2 GPIO_ADC1_IN4_1 -#define GPIO_ADC1_A3 GPIO_ADC1_IN9_1 - -/* DMA channels *************************************************************/ - -/* ADC */ - -#define ADC1_DMA_CHAN DMAMAP_DMA1_ADC1 - -#endif /* __BOARDS_ARM_STM32F0L0G0_NUCLEO_G0B1RE_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32f0l0g0/nucleo-g0b1re/scripts/Make.defs b/boards/arm/stm32f0l0g0/nucleo-g0b1re/scripts/Make.defs deleted file mode 100644 index 4f7c125818c27..0000000000000 --- a/boards/arm/stm32f0l0g0/nucleo-g0b1re/scripts/Make.defs +++ /dev/null @@ -1,41 +0,0 @@ -############################################################################ -# boards/arm/stm32f0l0g0/nucleo-g0b1re/scripts/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/.config -include $(TOPDIR)/tools/Config.mk -include $(TOPDIR)/arch/arm/src/armv6-m/Toolchain.defs - -LDSCRIPT = ld.script -ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) - -ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 - -CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) -CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) -CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -AFLAGS := $(CFLAGS) -D__ASSEMBLY__ - -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections -LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32f0l0g0/nucleo-g0b1re/scripts/ld.script b/boards/arm/stm32f0l0g0/nucleo-g0b1re/scripts/ld.script deleted file mode 100644 index efe5f8f915ead..0000000000000 --- a/boards/arm/stm32f0l0g0/nucleo-g0b1re/scripts/ld.script +++ /dev/null @@ -1,115 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-g0b1re/scripts/ld.script - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* The STM32GOB1RE has 512Kb of FLASH beginning at address 0x0800:0000. - * 128Kb (with parity) or 144Kb (without parity) of SRAM - * - * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 - * where the code expects to begin execution by jumping to the entry point in - * the 0x0800:0000 address range. - */ - -MEMORY -{ - flash (rx) : ORIGIN = 0x08000000, LENGTH = 512K - sram (rwx) : ORIGIN = 0x20000000, LENGTH = 144K -} - -OUTPUT_ARCH(arm) -EXTERN(_vectors) -ENTRY(_stext) -SECTIONS -{ - .text : { - _stext = ABSOLUTE(.); - *(.vectors) - *(.text .text.*) - *(.fixup) - *(.gnu.warning) - *(.rodata .rodata.*) - *(.gnu.linkonce.t.*) - *(.glue_7) - *(.glue_7t) - *(.got) - *(.gcc_except_table) - *(.gnu.linkonce.r.*) - _etext = ABSOLUTE(.); - } > flash - - .init_section : ALIGN(4) { - _sinit = ABSOLUTE(.); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) - KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) - _einit = ABSOLUTE(.); - } > flash - - .ARM.extab : ALIGN(4) { - *(.ARM.extab*) - } > flash - - .ARM.exidx : ALIGN(4) { - __exidx_start = ABSOLUTE(.); - *(.ARM.exidx*) - __exidx_end = ABSOLUTE(.); - } > flash - - _eronly = ABSOLUTE(.); - - /* The RAM vector table (if present) should lie at the beginning of SRAM */ - - .ram_vectors : { - *(.ram_vectors) - } > sram - - .data : ALIGN(4) { - _sdata = ABSOLUTE(.); - *(.data .data.*) - *(.gnu.linkonce.d.*) - CONSTRUCTORS - . = ALIGN(4); - _edata = ABSOLUTE(.); - } > sram AT > flash - - .bss : ALIGN(4) { - _sbss = ABSOLUTE(.); - *(.bss .bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - . = ALIGN(4); - _ebss = ABSOLUTE(.); - } > sram - - /* Stabs debugging sections. */ - - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_info 0 : { *(.debug_info) } - .debug_line 0 : { *(.debug_line) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_aranges 0 : { *(.debug_aranges) } -} diff --git a/boards/arm/stm32f0l0g0/nucleo-g0b1re/src/CMakeLists.txt b/boards/arm/stm32f0l0g0/nucleo-g0b1re/src/CMakeLists.txt deleted file mode 100644 index f6843c176e198..0000000000000 --- a/boards/arm/stm32f0l0g0/nucleo-g0b1re/src/CMakeLists.txt +++ /dev/null @@ -1,37 +0,0 @@ -# ############################################################################## -# boards/arm/stm32f0l0g0/nucleo-g0b1re/src/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -set(SRCS stm32_boot.c stm32_bringup.c) - -if(CONFIG_ARCH_LEDS) - list(APPEND SRCS stm32_autoleds.c) -else() - list(APPEND SRCS stm32_userleds.c) -endif() - -if(CONFIG_ARCH_BUTTONS) - list(APPEND SRCS stm32_buttons.c) -endif() - -target_sources(board PRIVATE ${SRCS}) - -set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/ld.script") diff --git a/boards/arm/stm32f0l0g0/nucleo-g0b1re/src/Make.defs b/boards/arm/stm32f0l0g0/nucleo-g0b1re/src/Make.defs deleted file mode 100644 index b3019b82f54fd..0000000000000 --- a/boards/arm/stm32f0l0g0/nucleo-g0b1re/src/Make.defs +++ /dev/null @@ -1,43 +0,0 @@ -############################################################################ -# boards/arm/stm32f0l0g0/nucleo-g0b1re/src/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/Make.defs - -CSRCS = stm32_boot.c stm32_bringup.c - -ifeq ($(CONFIG_ARCH_LEDS),y) -CSRCS += stm32_autoleds.c -else -CSRCS += stm32_userleds.c -endif - -ifeq ($(CONFIG_ARCH_BUTTONS),y) -CSRCS += stm32_buttons.c -endif - -ifeq ($(CONFIG_ADC),y) -CSRCS += stm32_adc.c -endif - -DEPPATH += --dep-path board -VPATH += :board -CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32f0l0g0/nucleo-g0b1re/src/stm32_adc.c b/boards/arm/stm32f0l0g0/nucleo-g0b1re/src/stm32_adc.c deleted file mode 100644 index 8d345718a0614..0000000000000 --- a/boards/arm/stm32f0l0g0/nucleo-g0b1re/src/stm32_adc.c +++ /dev/null @@ -1,137 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-g0b1re/src/stm32_adc.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include - -#include - -#include "stm32.h" - -#if defined(CONFIG_ADC) && defined(CONFIG_STM32F0L0G0_ADC1) - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -/* The number of ADC channels in the conversion list */ - -#define ADC1_NCHANNELS 4 - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* Identifying number of each ADC channel (even if NCHANNELS is less ) */ - -static const uint8_t g_chanlist1[ADC1_NCHANNELS] = -{ - 0, - 1, - 4, - 9 -}; - -/* Configurations of pins used by each ADC channel */ - -static const uint32_t g_pinlist1[ADC1_NCHANNELS] = -{ - GPIO_ADC1_A0, - GPIO_ADC1_A1, - GPIO_ADC1_A2, - GPIO_ADC1_A3 -}; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_adc_setup - * - * Description: - * Initialize ADC and register the ADC driver. - * - ****************************************************************************/ - -int stm32_adc_setup(void) -{ - static bool initialized = false; - struct adc_dev_s *adc; - int ret; - int i; - - /* Check if we have already initialized */ - - if (!initialized) - { - /* Configure the pins as analog inputs for the selected channels */ - - for (i = 0; i < ADC1_NCHANNELS; i++) - { - stm32_configgpio(g_pinlist1[i]); - } - - /* Call stm32_adcinitialize() to get an instance of the ADC interface */ - - adc = stm32_adcinitialize(1, g_chanlist1, ADC1_NCHANNELS); - if (adc == NULL) - { - aerr("ERROR: Failed to get ADC interface 1\n"); - return -ENODEV; - } - - /* Register the ADC driver at "/dev/adc0" */ - - ret = adc_register("/dev/adc0", adc); - if (ret < 0) - { - aerr("ERROR: adc_register /dev/adc0 failed: %d\n", ret); - return ret; - } - - initialized = true; - } - - return OK; -} - -#endif diff --git a/boards/arm/stm32f0l0g0/nucleo-g0b1re/src/stm32_autoleds.c b/boards/arm/stm32f0l0g0/nucleo-g0b1re/src/stm32_autoleds.c deleted file mode 100644 index 2ee5c55f2ade0..0000000000000 --- a/boards/arm/stm32f0l0g0/nucleo-g0b1re/src/stm32_autoleds.c +++ /dev/null @@ -1,81 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-g0b1re/src/stm32_autoleds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include - -#include "stm32_gpio.h" -#include "nucleo-g0b1re.h" - -#include - -#ifdef CONFIG_ARCH_LEDS - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_autoled_initialize - ****************************************************************************/ - -void board_autoled_initialize(void) -{ - /* Configure LED1 GPIO for output */ - - stm32_configgpio(GPIO_LED1); -} - -/**************************************************************************** - * Name: board_autoled_on - ****************************************************************************/ - -void board_autoled_on(int led) -{ - if (led == BOARD_LED1) - { - stm32_gpiowrite(GPIO_LED1, true); - } -} - -/**************************************************************************** - * Name: board_autoled_off - ****************************************************************************/ - -void board_autoled_off(int led) -{ - if (led == BOARD_LED1) - { - stm32_gpiowrite(GPIO_LED1, false); - } -} - -#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32f0l0g0/nucleo-g0b1re/src/stm32_boot.c b/boards/arm/stm32f0l0g0/nucleo-g0b1re/src/stm32_boot.c deleted file mode 100644 index 97a7c428eba35..0000000000000 --- a/boards/arm/stm32f0l0g0/nucleo-g0b1re/src/stm32_boot.c +++ /dev/null @@ -1,85 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-g0b1re/src/stm32_boot.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include "nucleo-g0b1re.h" - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_boardinitialize - * - * Description: - * All STM32 architectures must provide the following entry point. This - * entry point is called early in the initialization -- after all memory - * has been configured and mapped but before any devices have been - * initialized. - * - ****************************************************************************/ - -void stm32_boardinitialize(void) -{ -#ifdef CONFIG_ARCH_LEDS - /* Configure on-board LEDs if LED support has been selected. */ - - board_autoled_initialize(); -#endif - -#ifdef CONFIG_STM32F0L0G0_SPI - /* Configure SPI chip selects */ - - stm32_spidev_initialize(); -#endif -} - -/**************************************************************************** - * Name: board_late_initialize - * - * Description: - * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional - * initialization call will be performed in the boot-up sequence to a - * function called board_late_initialize(). board_late_initialize() will - * be called immediately after up_initialize() is called and just before - * the initial application is started. This additional initialization - * phase may be used, for example, to initialize board-specific device - * drivers. - * - ****************************************************************************/ - -#ifdef CONFIG_BOARD_LATE_INITIALIZE -void board_late_initialize(void) -{ - /* Perform board-specific initialization */ - - stm32_bringup(); -} -#endif diff --git a/boards/arm/stm32f0l0g0/nucleo-g0b1re/src/stm32_bringup.c b/boards/arm/stm32f0l0g0/nucleo-g0b1re/src/stm32_bringup.c deleted file mode 100644 index e9ca45a84d77d..0000000000000 --- a/boards/arm/stm32f0l0g0/nucleo-g0b1re/src/stm32_bringup.c +++ /dev/null @@ -1,156 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-g0b1re/src/stm32_bringup.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include - -#include -#include -#include -#include - -#include "nucleo-g0b1re.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#undef HAVE_LEDS -#undef HAVE_DAC - -#if !defined(CONFIG_ARCH_LEDS) && defined(CONFIG_USERLED_LOWER) -# define HAVE_LEDS 1 -#endif - -#if defined(CONFIG_DAC) -# define HAVE_DAC1 1 -# define HAVE_DAC2 1 -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_bringup - * - * Description: - * Perform architecture-specific initialization - * - * CONFIG_BOARD_LATE_INITIALIZE=y : - * Called from board_late_initialize(). - * - ****************************************************************************/ - -int stm32_bringup(void) -{ - int ret; - -#ifdef HAVE_LEDS - /* Register the LED driver */ - - ret = userled_lower_initialize(LED_DRIVER_PATH); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: userled_lower_initialize() failed: %d\n", - ret); - return ret; - } -#endif - -#ifdef CONFIG_ADC - /* Initialize ADC and register the ADC driver. */ - - ret = stm32_adc_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_adc_setup failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_DAC - /* Initialize DAC and register the DAC driver. */ - - ret = stm32_dac_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_dac_setup failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_COMP - /* Initialize COMP and register the COMP driver. */ - - ret = stm32_comp_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_comp_setup failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_OPAMP - /* Initialize OPAMP and register the OPAMP driver. */ - - ret = stm32_opamp_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_opamp_setup failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_WL_NRF24L01 - ret = stm32_wlinitialize(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: Failed to initialize wireless driver: %d\n", - ret); - } -#endif /* CONFIG_WL_NRF24L01 */ - -#ifdef CONFIG_LPWAN_SX127X - ret = stm32_lpwaninitialize(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: Failed to initialize wireless driver: %d\n", - ret); - } -#endif /* CONFIG_LPWAN_SX127X */ - -#ifdef CONFIG_CL_MFRC522 - ret = stm32_mfrc522initialize("/dev/rfid0"); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_mfrc522initialize() failed: %d\n", ret); - } -#endif /* CONFIG_CL_MFRC522 */ - - UNUSED(ret); - return OK; -} diff --git a/boards/arm/stm32f0l0g0/nucleo-g0b1re/src/stm32_buttons.c b/boards/arm/stm32f0l0g0/nucleo-g0b1re/src/stm32_buttons.c deleted file mode 100644 index 688327750b6ff..0000000000000 --- a/boards/arm/stm32f0l0g0/nucleo-g0b1re/src/stm32_buttons.c +++ /dev/null @@ -1,118 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-g0b1re/src/stm32_buttons.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include "stm32_gpio.h" -#include "nucleo-g0b1re.h" - -#include - -#ifdef CONFIG_ARCH_BUTTONS - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_button_initialize - * - * Description: - * board_button_initialize() must be called to initialize button resources. - * After that, board_buttons() may be called to collect the current state - * of all buttons or board_button_irq() may be called to register button - * interrupt handlers. - * - ****************************************************************************/ - -uint32_t board_button_initialize(void) -{ - /* Configure the single button as an input. NOTE that EXTI interrupts are - * also configured for the pin. - */ - - stm32_configgpio(GPIO_BTN_USER); - return NUM_BUTTONS; -} - -/**************************************************************************** - * Name: board_buttons - ****************************************************************************/ - -uint32_t board_buttons(void) -{ - /* Check that state of each USER button. A LOW value means that the key is - * pressed. - */ - - bool released = stm32_gpioread(GPIO_BTN_USER); - return !released; -} - -/**************************************************************************** - * Button support. - * - * Description: - * board_button_initialize() must be called to initialize button resources. - * After that, board_buttons() may be called to collect the current state - * of all buttons or board_button_irq() may be called to register button - * interrupt handlers. - * - * After board_button_initialize() has been called, board_buttons() may be - * called to collect the state of all buttons. board_buttons() returns an - * 32-bit bit set with each bit associated with a button. See the - * BUTTON_*_BIT definitions in board.h for the meaning of each bit. - * - * board_button_irq() may be called to register an interrupt handler that - * will be called when a button is depressed or released. The ID value is a - * button enumeration value that uniquely identifies a button resource. See - * the BUTTON_* definitions in board.h for the meaning of enumeration - * value. - * - ****************************************************************************/ - -#ifdef CONFIG_ARCH_IRQBUTTONS -int board_button_irq(int id, xcpt_t irqhandler, void *arg) -{ - int ret = -EINVAL; - - if (id == BUTTON_USER) - { - ret = stm32_gpiosetevent(GPIO_BTN_USER, true, true, true, - irqhandler, arg); - } - - return ret; -} -#endif -#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/stm32f0l0g0/nucleo-l073rz/CMakeLists.txt b/boards/arm/stm32f0l0g0/nucleo-l073rz/CMakeLists.txt deleted file mode 100644 index 79eec2b120d43..0000000000000 --- a/boards/arm/stm32f0l0g0/nucleo-l073rz/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32f0l0g0/nucleo-l073rz/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32f0l0g0/nucleo-l073rz/configs/nsh/defconfig b/boards/arm/stm32f0l0g0/nucleo-l073rz/configs/nsh/defconfig deleted file mode 100644 index 3daccc627d569..0000000000000 --- a/boards/arm/stm32f0l0g0/nucleo-l073rz/configs/nsh/defconfig +++ /dev/null @@ -1,51 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_NSH_ARGCAT is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="nucleo-l073rz" -CONFIG_ARCH_BOARD_NUCLEO_L073RZ=y -CONFIG_ARCH_CHIP="stm32f0l0g0" -CONFIG_ARCH_CHIP_STM32L073RZ=y -CONFIG_ARCH_CHIP_STM32L073XX=y -CONFIG_ARCH_CHIP_STM32L0=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=2796 -CONFIG_BUILTIN=y -CONFIG_DISABLE_ENVIRON=y -CONFIG_DISABLE_MOUNTPOINT=y -CONFIG_DISABLE_MQUEUE=y -CONFIG_DISABLE_POSIX_TIMERS=y -CONFIG_DISABLE_PSEUDOFS_OPERATIONS=y -CONFIG_EXAMPLES_HELLO=y -CONFIG_EXPERIMENTAL=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INIT_STACKSIZE=1536 -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=64 -CONFIG_NSH_READLINE=y -CONFIG_NUNGET_CHARS=0 -CONFIG_POSIX_SPAWN_DEFAULT_STACKSIZE=1536 -CONFIG_PTHREAD_MUTEX_UNSAFE=y -CONFIG_PTHREAD_STACK_DEFAULT=1536 -CONFIG_RAM_SIZE=20480 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=19 -CONFIG_START_MONTH=5 -CONFIG_START_YEAR=2013 -CONFIG_STDIO_DISABLE_BUFFERING=y -CONFIG_STM32F0L0G0_PWR=y -CONFIG_STM32F0L0G0_USART2=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f0l0g0/nucleo-l073rz/configs/sx127x/defconfig b/boards/arm/stm32f0l0g0/nucleo-l073rz/configs/sx127x/defconfig deleted file mode 100644 index 085ba16e7d1f2..0000000000000 --- a/boards/arm/stm32f0l0g0/nucleo-l073rz/configs/sx127x/defconfig +++ /dev/null @@ -1,61 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_NSH_ARGCAT is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="nucleo-l073rz" -CONFIG_ARCH_BOARD_NUCLEO_L073RZ=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32f0l0g0" -CONFIG_ARCH_CHIP_STM32L073RZ=y -CONFIG_ARCH_CHIP_STM32L073XX=y -CONFIG_ARCH_CHIP_STM32L0=y -CONFIG_ARCH_IRQBUTTONS=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=2796 -CONFIG_BUILTIN=y -CONFIG_DISABLE_ENVIRON=y -CONFIG_DISABLE_MOUNTPOINT=y -CONFIG_DISABLE_MQUEUE=y -CONFIG_DISABLE_POSIX_TIMERS=y -CONFIG_DISABLE_PSEUDOFS_OPERATIONS=y -CONFIG_DRIVERS_LPWAN=y -CONFIG_DRIVERS_WIRELESS=y -CONFIG_EXAMPLES_HELLO=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INIT_STACKSIZE=1536 -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_LPWAN_SX127X=y -CONFIG_LPWAN_SX127X_FSKOOK=y -CONFIG_LPWAN_SX127X_MODULATION_DEFAULT=1 -CONFIG_LPWAN_SX127X_RXSUPPORT=y -CONFIG_LPWAN_SX127X_TXSUPPORT=y -CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=64 -CONFIG_NSH_READLINE=y -CONFIG_NUNGET_CHARS=0 -CONFIG_POSIX_SPAWN_DEFAULT_STACKSIZE=1536 -CONFIG_PTHREAD_MUTEX_UNSAFE=y -CONFIG_PTHREAD_STACK_DEFAULT=1536 -CONFIG_RAM_SIZE=20480 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=19 -CONFIG_START_MONTH=5 -CONFIG_START_YEAR=2013 -CONFIG_STDIO_DISABLE_BUFFERING=y -CONFIG_STM32F0L0G0_PWR=y -CONFIG_STM32F0L0G0_SPI1=y -CONFIG_STM32F0L0G0_USART2=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f0l0g0/nucleo-l073rz/include/board.h b/boards/arm/stm32f0l0g0/nucleo-l073rz/include/board.h deleted file mode 100644 index cd1539a76b303..0000000000000 --- a/boards/arm/stm32f0l0g0/nucleo-l073rz/include/board.h +++ /dev/null @@ -1,203 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-l073rz/include/board.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __BOARDS_ARM_STM32F0L0G0_NUCLEO_L073RZ_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32F0L0G0_NUCLEO_L073RZ_INCLUDE_BOARD_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#ifndef __ASSEMBLY__ -# include -# include -#endif - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Clocking *****************************************************************/ - -/* HSI - Internal 8 MHz RC Oscillator - * LSI - 32 KHz RC - * HSE - 8 MHz from MCO output of ST-LINK - * LSE - 32.768 kHz - */ - -#define STM32_BOARD_XTAL 8000000ul - -#define STM32_HSEBYP_ENABLE -#define STM32_HSI_FREQUENCY 8000000ul -#define STM32_LSI_FREQUENCY 32000 /* Between 30kHz and 60kHz */ -#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL -#define STM32_LSE_FREQUENCY 32768 /* X2 on board */ - -/* PLL source is HSE/1, PLL multiplier is 8: - * PLL frequency is 8MHz (XTAL) x 8 = 64MHz - */ - -#define STM32_CFGR_PLLSRC RCC_CFGR_PLLSRC -#define STM32_CFGR_PLLXTPRE 0 -#define STM32_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx8 -#define STM32_PLL_FREQUENCY (8*STM32_BOARD_XTAL) - -/* Use the PLL and set the SYSCLK source to be the PLL/2 (32MHz) */ - -#define STM32_SYSCLK_SW RCC_CFGR_SW_PLL -#define STM32_SYSCLK_SWS RCC_CFGR_SWS_PLL -#define STM32_CFGR_PLLDIV RCC_CFGR_PLLDIV_2 -#define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY/2 - -/* AHB clock (HCLK) is SYSCLK (32MHz) */ - -#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK -#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY - -/* APB2 clock (PCLK2) is HCLK (32MHz) */ - -#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK -#define STM32_PCLK2_FREQUENCY STM32_HCLK_FREQUENCY -#define STM32_APB2_CLKIN (STM32_PCLK2_FREQUENCY) - -/* APB1 clock (PCLK1) is HCLK/2 (16MHz) */ - -#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd2 -#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/2) - -/* 48MHz clock configuration */ - -#if defined(CONFIG_STM32F0L0G0_USB) || defined(CONFIG_STM32F0L0G0_RNG) -# define STM32_USE_CLK48 1 -# define STM32_CLK48_SEL RCC_CCIPR_CLK48SEL_HSI48 -# define STM32_HSI48_SYNCSRC SYNCSRC_NONE -#endif - -/* TODO: timers */ - -/* LED definitions **********************************************************/ - -/* The Nucleo LO73RZ board has three LEDs. Two of these are controlled by - * logic on the board and are not available for software control: - * - * LD1 COM: LD1 default status is red. LD1 turns to green to indicate that - * communications are in progress between the PC and the - * ST-LINK/V2-1. - * LD3 PWR: red LED indicates that the board is powered. - * - * And one can be controlled by software: - * - * User LD2: green LED is a user LED connected to the I/O PA5 of the - * STM32LO73RZ. - * - * If CONFIG_ARCH_LEDS is not defined, then the user can control the LED in - * any way. The following definition is used to access the LED. - */ - -/* LED index values for use with board_userled() */ - -#define BOARD_LED1 0 /* User LD2 */ -#define BOARD_NLEDS 1 - -/* LED bits for use with board_userled_all() */ - -#define BOARD_LED1_BIT (1 << BOARD_LED1) - -/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the LED on board - * the Nucleo LO73RZ. The following definitions describe how NuttX controls - * the LED: - * - * SYMBOL Meaning LED1 state - * ------------------ ----------------------- ---------- - * LED_STARTED NuttX has been started OFF - * LED_HEAPALLOCATE Heap has been allocated OFF - * LED_IRQSENABLED Interrupts enabled OFF - * LED_STACKCREATED Idle stack created ON - * LED_INIRQ In an interrupt No change - * LED_SIGNAL In a signal handler No change - * LED_ASSERTION An assertion failed No change - * LED_PANIC The system has crashed Blinking - * LED_IDLE STM32 is in sleep mode Not used - */ - -#define LED_STARTED 0 -#define LED_HEAPALLOCATE 0 -#define LED_IRQSENABLED 0 -#define LED_STACKCREATED 1 -#define LED_INIRQ 2 -#define LED_SIGNAL 2 -#define LED_ASSERTION 2 -#define LED_PANIC 1 - -/* Button definitions *******************************************************/ - -/* The Nucleo LO73RZ supports two buttons; only one button is controllable - * by software: - * - * B1 USER: user button connected to the I/O PC13 of the STM32LO73RZ. - * B2 RESET: push button connected to NRST is used to RESET the - * STM32LO73RZ. - */ - -#define BUTTON_USER 0 -#define NUM_BUTTONS 1 - -#define BUTTON_USER_BIT (1 << BUTTON_USER) - -/* Alternate function pin selections ****************************************/ - -/* I2C */ - -#define GPIO_I2C1_SCL (GPIO_I2C1_SCL_2|GPIO_SPEED_LOW) /* D15 - PB8 */ -#define GPIO_I2C1_SDA (GPIO_I2C1_SDA_2|GPIO_SPEED_LOW) /* D14 - PB9 */ - -/* SPI1 */ - -#define GPIO_SPI1_MISO (GPIO_SPI1_MISO_2|GPIO_SPEED_MEDIUM) /* D12 - PA6 */ -#define GPIO_SPI1_MOSI (GPIO_SPI1_MOSI_2|GPIO_SPEED_MEDIUM) /* D11 - PA7 */ -#define GPIO_SPI1_SCK (GPIO_SPI1_SCK_1|GPIO_SPEED_MEDIUM) /* D13 - PA5 */ - -/* SPI2 */ - -#define GPIO_SPI2_MISO (GPIO_SPI2_MISO_1|GPIO_SPEED_MEDIUM) /* PB14 */ -#define GPIO_SPI2_MOSI (GPIO_SPI2_MOSI_1|GPIO_SPEED_MEDIUM) /* PB15 */ -#define GPIO_SPI2_SCK (GPIO_SPI2_SCK_1|GPIO_SPEED_MEDIUM) /* PB10 */ - -/* USART */ - -/* By default the USART2 is connected to STLINK Virtual COM Port: - * USART2_RX - PA3 - * USART2_TX - PA2 - */ - -#define GPIO_USART2_RX (GPIO_USART2_RX_1|GPIO_SPEED_HIGH) /* PA3 */ -#define GPIO_USART2_TX (GPIO_USART2_TX_1|GPIO_SPEED_HIGH) /* PA2 */ - -/* DMA channels *************************************************************/ - -/* ADC */ - -#define ADC1_DMA_CHAN DMACHAN_ADC1 /* DMA1_CH1 */ - -#endif /* __BOARDS_ARM_STM32F0L0G0_NUCLEO_LO73RZ_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32f0l0g0/nucleo-l073rz/scripts/Make.defs b/boards/arm/stm32f0l0g0/nucleo-l073rz/scripts/Make.defs deleted file mode 100644 index 0f50dc2d96b09..0000000000000 --- a/boards/arm/stm32f0l0g0/nucleo-l073rz/scripts/Make.defs +++ /dev/null @@ -1,41 +0,0 @@ -############################################################################ -# boards/arm/stm32f0l0g0/nucleo-l073rz/scripts/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/.config -include $(TOPDIR)/tools/Config.mk -include $(TOPDIR)/arch/arm/src/armv6-m/Toolchain.defs - -LDSCRIPT = ld.script -ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) - -ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 - -CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) -CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) -CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -AFLAGS := $(CFLAGS) -D__ASSEMBLY__ - -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections -LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32f0l0g0/nucleo-l073rz/scripts/ld.script b/boards/arm/stm32f0l0g0/nucleo-l073rz/scripts/ld.script deleted file mode 100644 index e0da80b38d57a..0000000000000 --- a/boards/arm/stm32f0l0g0/nucleo-l073rz/scripts/ld.script +++ /dev/null @@ -1,115 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-l073rz/scripts/ld.script - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* The STM32LO73RZ has 192Kb of FLASH beginning at address 0x0800:0000. - * 20Kb of SRAM and 6Kb of EEPROM - * - * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 - * where the code expects to begin execution by jumping to the entry point in - * the 0x0800:0000 address range. - */ - -MEMORY -{ - flash (rx) : ORIGIN = 0x08000000, LENGTH = 192K - sram (rwx) : ORIGIN = 0x20000000, LENGTH = 20K -} - -OUTPUT_ARCH(arm) -EXTERN(_vectors) -ENTRY(_stext) -SECTIONS -{ - .text : { - _stext = ABSOLUTE(.); - *(.vectors) - *(.text .text.*) - *(.fixup) - *(.gnu.warning) - *(.rodata .rodata.*) - *(.gnu.linkonce.t.*) - *(.glue_7) - *(.glue_7t) - *(.got) - *(.gcc_except_table) - *(.gnu.linkonce.r.*) - _etext = ABSOLUTE(.); - } > flash - - .init_section : ALIGN(4) { - _sinit = ABSOLUTE(.); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) - KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) - _einit = ABSOLUTE(.); - } > flash - - .ARM.extab : ALIGN(4) { - *(.ARM.extab*) - } > flash - - .ARM.exidx : ALIGN(4) { - __exidx_start = ABSOLUTE(.); - *(.ARM.exidx*) - __exidx_end = ABSOLUTE(.); - } > flash - - _eronly = ABSOLUTE(.); - - /* The RAM vector table (if present) should lie at the beginning of SRAM */ - - .ram_vectors : { - *(.ram_vectors) - } > sram - - .data : ALIGN(4) { - _sdata = ABSOLUTE(.); - *(.data .data.*) - *(.gnu.linkonce.d.*) - CONSTRUCTORS - . = ALIGN(4); - _edata = ABSOLUTE(.); - } > sram AT > flash - - .bss : ALIGN(4) { - _sbss = ABSOLUTE(.); - *(.bss .bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - . = ALIGN(4); - _ebss = ABSOLUTE(.); - } > sram - - /* Stabs debugging sections. */ - - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_info 0 : { *(.debug_info) } - .debug_line 0 : { *(.debug_line) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_aranges 0 : { *(.debug_aranges) } -} diff --git a/boards/arm/stm32f0l0g0/nucleo-l073rz/src/CMakeLists.txt b/boards/arm/stm32f0l0g0/nucleo-l073rz/src/CMakeLists.txt deleted file mode 100644 index c14a6c3588178..0000000000000 --- a/boards/arm/stm32f0l0g0/nucleo-l073rz/src/CMakeLists.txt +++ /dev/null @@ -1,53 +0,0 @@ -# ############################################################################## -# boards/arm/stm32f0l0g0/nucleo-l073rz/src/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -set(SRCS stm32_boot.c stm32_bringup.c) - -if(CONFIG_ARCH_LEDS) - list(APPEND SRCS stm32_autoleds.c) -else() - list(APPEND SRCS stm32_userleds.c) -endif() - -if(CONFIG_ARCH_BUTTONS) - list(APPEND SRCS stm32_buttons.c) -endif() - -if(CONFIG_STM32F0L0G0_SPI) - list(APPEND SRCS stm32_spi.c) -endif() - -if(CONFIG_WL_NRF24L01) - list(APPEND SRCS stm32_nrf24l01.c) -endif() - -if(CONFIG_LPWAN_SX127X) - list(APPEND SRCS stm32_sx127x.c) -endif() - -if(CONFIG_CL_MFRC522) - list(APPEND SRCS stm32_mfrc522.c) -endif() - -target_sources(board PRIVATE ${SRCS}) - -set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/ld.script") diff --git a/boards/arm/stm32f0l0g0/nucleo-l073rz/src/Make.defs b/boards/arm/stm32f0l0g0/nucleo-l073rz/src/Make.defs deleted file mode 100644 index bd4f63065bd7d..0000000000000 --- a/boards/arm/stm32f0l0g0/nucleo-l073rz/src/Make.defs +++ /dev/null @@ -1,55 +0,0 @@ -############################################################################ -# boards/arm/stm32f0l0g0/nucleo-l073rz/src/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/Make.defs - -CSRCS = stm32_boot.c stm32_bringup.c - -ifeq ($(CONFIG_ARCH_LEDS),y) -CSRCS += stm32_autoleds.c -else -CSRCS += stm32_userleds.c -endif - -ifeq ($(CONFIG_ARCH_BUTTONS),y) -CSRCS += stm32_buttons.c -endif - -ifeq ($(CONFIG_STM32F0L0G0_SPI),y) -CSRCS += stm32_spi.c -endif - -ifeq ($(CONFIG_WL_NRF24L01),y) -CSRCS += stm32_nrf24l01.c -endif - -ifeq ($(CONFIG_LPWAN_SX127X),y) -CSRCS += stm32_sx127x.c -endif - -ifeq ($(CONFIG_CL_MFRC522),y) -CSRCS += stm32_mfrc522.c -endif - -DEPPATH += --dep-path board -VPATH += :board -CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32f0l0g0/nucleo-l073rz/src/stm32_autoleds.c b/boards/arm/stm32f0l0g0/nucleo-l073rz/src/stm32_autoleds.c deleted file mode 100644 index 2f06c37702f38..0000000000000 --- a/boards/arm/stm32f0l0g0/nucleo-l073rz/src/stm32_autoleds.c +++ /dev/null @@ -1,81 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-l073rz/src/stm32_autoleds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include - -#include "stm32_gpio.h" -#include "nucleo-l073rz.h" - -#include - -#ifdef CONFIG_ARCH_LEDS - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_autoled_initialize - ****************************************************************************/ - -void board_autoled_initialize(void) -{ - /* Configure LED1 GPIO for output */ - - stm32_configgpio(GPIO_LED1); -} - -/**************************************************************************** - * Name: board_autoled_on - ****************************************************************************/ - -void board_autoled_on(int led) -{ - if (led == BOARD_LED1) - { - stm32_gpiowrite(GPIO_LED1, true); - } -} - -/**************************************************************************** - * Name: board_autoled_off - ****************************************************************************/ - -void board_autoled_off(int led) -{ - if (led == BOARD_LED1) - { - stm32_gpiowrite(GPIO_LED1, false); - } -} - -#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32f0l0g0/nucleo-l073rz/src/stm32_boot.c b/boards/arm/stm32f0l0g0/nucleo-l073rz/src/stm32_boot.c deleted file mode 100644 index ce6e4324bde83..0000000000000 --- a/boards/arm/stm32f0l0g0/nucleo-l073rz/src/stm32_boot.c +++ /dev/null @@ -1,101 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-l073rz/src/stm32_boot.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include "nucleo-l073rz.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_boardinitialize - * - * Description: - * All STM32 architectures must provide the following entry point. This - * entry point is called early in the initialization -- after all memory - * has been configured and mapped but before any devices have been - * initialized. - * - ****************************************************************************/ - -void stm32_boardinitialize(void) -{ -#ifdef CONFIG_ARCH_LEDS - /* Configure on-board LEDs if LED support has been selected. */ - - board_autoled_initialize(); -#endif - -#ifdef CONFIG_STM32F0L0G0_SPI - /* Configure SPI chip selects */ - - stm32_spidev_initialize(); -#endif -} - -/**************************************************************************** - * Name: board_late_initialize - * - * Description: - * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional - * initialization call will be performed in the boot-up sequence to a - * function called board_late_initialize(). board_late_initialize() will - * be called immediately after up_initialize() is called and just before - * the initial application is started. This additional initialization - * phase may be used, for example, to initialize board-specific device - * drivers. - * - ****************************************************************************/ - -#ifdef CONFIG_BOARD_LATE_INITIALIZE -void board_late_initialize(void) -{ - /* Perform board-specific initialization */ - - stm32_bringup(); -} -#endif diff --git a/boards/arm/stm32f0l0g0/nucleo-l073rz/src/stm32_bringup.c b/boards/arm/stm32f0l0g0/nucleo-l073rz/src/stm32_bringup.c deleted file mode 100644 index 35e5ae85e28b4..0000000000000 --- a/boards/arm/stm32f0l0g0/nucleo-l073rz/src/stm32_bringup.c +++ /dev/null @@ -1,151 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-l073rz/src/stm32_bringup.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include - -#include "nucleo-l073rz.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#undef HAVE_LEDS -#undef HAVE_DAC - -#if !defined(CONFIG_ARCH_LEDS) && defined(CONFIG_USERLED_LOWER) -# define HAVE_LEDS 1 -#endif - -#if defined(CONFIG_DAC) -# define HAVE_DAC1 1 -# define HAVE_DAC2 1 -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_bringup - * - * Description: - * Perform architecture-specific initialization - * - * CONFIG_BOARD_LATE_INITIALIZE=y : - * Called from board_late_initialize(). - * - ****************************************************************************/ - -int stm32_bringup(void) -{ - int ret; - -#ifdef HAVE_LEDS - /* Register the LED driver */ - - ret = userled_lower_initialize(LED_DRIVER_PATH); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: userled_lower_initialize() failed: %d\n", ret); - return ret; - } -#endif - -#ifdef CONFIG_ADC - /* Initialize ADC and register the ADC driver. */ - - ret = stm32_adc_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_adc_setup failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_DAC - /* Initialize DAC and register the DAC driver. */ - - ret = stm32_dac_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_dac_setup failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_COMP - /* Initialize COMP and register the COMP driver. */ - - ret = stm32_comp_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_comp_setup failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_OPAMP - /* Initialize OPAMP and register the OPAMP driver. */ - - ret = stm32_opamp_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_opamp_setup failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_WL_NRF24L01 - ret = stm32_wlinitialize(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: Failed to initialize wireless driver: %d\n", - ret); - } -#endif /* CONFIG_WL_NRF24L01 */ - -#ifdef CONFIG_LPWAN_SX127X - ret = stm32_lpwaninitialize(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: Failed to initialize wireless driver: %d\n", - ret); - } -#endif /* CONFIG_LPWAN_SX127X */ - -#ifdef CONFIG_CL_MFRC522 - ret = stm32_mfrc522initialize("/dev/rfid0"); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_mfrc522initialize() failed: %d\n", ret); - } -#endif /* CONFIG_CL_MFRC522 */ - - UNUSED(ret); - return OK; -} diff --git a/boards/arm/stm32f0l0g0/nucleo-l073rz/src/stm32_buttons.c b/boards/arm/stm32f0l0g0/nucleo-l073rz/src/stm32_buttons.c deleted file mode 100644 index 6fee37bc6e0f0..0000000000000 --- a/boards/arm/stm32f0l0g0/nucleo-l073rz/src/stm32_buttons.c +++ /dev/null @@ -1,118 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-l073rz/src/stm32_buttons.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include "stm32_gpio.h" -#include "nucleo-l073rz.h" - -#include - -#ifdef CONFIG_ARCH_BUTTONS - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_button_initialize - * - * Description: - * board_button_initialize() must be called to initialize button resources. - * After that, board_buttons() may be called to collect the current state - * of all buttons or board_button_irq() may be called to register button - * interrupt handlers. - * - ****************************************************************************/ - -uint32_t board_button_initialize(void) -{ - /* Configure the single button as an input. NOTE that EXTI interrupts are - * also configured for the pin. - */ - - stm32_configgpio(GPIO_BTN_USER); - return NUM_BUTTONS; -} - -/**************************************************************************** - * Name: board_buttons - ****************************************************************************/ - -uint32_t board_buttons(void) -{ - /* Check that state of each USER button. A LOW value means that the key is - * pressed. - */ - - bool released = stm32_gpioread(GPIO_BTN_USER); - return !released; -} - -/**************************************************************************** - * Button support. - * - * Description: - * board_button_initialize() must be called to initialize button resources. - * After that, board_buttons() may be called to collect the current state - * of all buttons or board_button_irq() may be called to register button - * interrupt handlers. - * - * After board_button_initialize() has been called, board_buttons() may be - * called to collect the state of all buttons. board_buttons() returns an - * 32-bit bit set with each bit associated with a button. See the - * BUTTON_*_BIT definitions in board.h for the meaning of each bit. - * - * board_button_irq() may be called to register an interrupt handler that - * will be called when a button is depressed or released. The ID value is a - * button enumeration value that uniquely identifies a button resource. See - * the BUTTON_* definitions in board.h for the meaning of enumeration - * value. - * - ****************************************************************************/ - -#ifdef CONFIG_ARCH_IRQBUTTONS -int board_button_irq(int id, xcpt_t irqhandler, void *arg) -{ - int ret = -EINVAL; - - if (id == BUTTON_USER) - { - ret = stm32_gpiosetevent(GPIO_BTN_USER, true, true, true, - irqhandler, arg); - } - - return ret; -} -#endif -#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/stm32f0l0g0/nucleo-l073rz/src/stm32_mfrc522.c b/boards/arm/stm32f0l0g0/nucleo-l073rz/src/stm32_mfrc522.c deleted file mode 100644 index eb49b42280431..0000000000000 --- a/boards/arm/stm32f0l0g0/nucleo-l073rz/src/stm32_mfrc522.c +++ /dev/null @@ -1,97 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-l073rz/src/stm32_mfrc522.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include - -#include "stm32.h" -#include "stm32_spi.h" -#include "nucleo-l073rz.h" - -#if defined(CONFIG_SPI) && defined(CONFIG_STM32F0L0G0_SPI2) && defined(CONFIG_CL_MFRC522) - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#define MFRC522_SPI_PORTNO 2 /* On SPI2 */ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_mfrc522initialize - * - * Description: - * Initialize and register the MFRC522 RFID driver. - * - * Input Parameters: - * devpath - The full path to the driver to register. E.g., "/dev/rfid0" - * - * Returned Value: - * Zero (OK) on success; a negated errno value on failure. - * - ****************************************************************************/ - -int stm32_mfrc522initialize(const char *devpath) -{ - struct spi_dev_s *spi; - int ret; - - /* Configure MFRC522 reset */ - - stm32_configgpio(GPIO_MFRC522_RESET); - - /* MFRC522 hardware reset on rising edge */ - - stm32_gpiowrite(GPIO_MFRC522_RESET, true); - - /* Initialize SPI */ - - spi = stm32_spibus_initialize(MFRC522_SPI_PORTNO); - if (!spi) - { - return -ENODEV; - } - - /* Then register the MFRC522 */ - - ret = mfrc522_register(devpath, spi); - if (ret < 0) - { - snerr("ERROR: Error registering MFRC522\n"); - } - - return ret; -} - -#endif /* CONFIG_SPI && CONFIG_MFRC522 */ diff --git a/boards/arm/stm32f0l0g0/nucleo-l073rz/src/stm32_nrf24l01.c b/boards/arm/stm32f0l0g0/nucleo-l073rz/src/stm32_nrf24l01.c deleted file mode 100644 index b8bb669ff793c..0000000000000 --- a/boards/arm/stm32f0l0g0/nucleo-l073rz/src/stm32_nrf24l01.c +++ /dev/null @@ -1,123 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-l073rz/src/stm32_nrf24l01.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include - -#include -#include -#include - -#include "arm_internal.h" -#include "chip.h" -#include "stm32.h" -#include "nucleo-l073rz.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#define NRF24L01_SPI 1 - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -static int nrf24l01_irq_attach(xcpt_t isr, void *arg); -static void nrf24l01_chip_enable(bool enable); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -static struct nrf24l01_config_s nrf_cfg = -{ - .irqattach = nrf24l01_irq_attach, - .chipenable = nrf24l01_chip_enable, -}; - -static xcpt_t g_isr; -static void *g_arg; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -static int nrf24l01_irq_attach(xcpt_t isr, void *arg) -{ - wlinfo("Attach IRQ\n"); - g_isr = isr; - g_arg = arg; - stm32_gpiosetevent(GPIO_NRF24L01_IRQ, false, true, false, g_isr, g_arg); - return OK; -} - -static void nrf24l01_chip_enable(bool enable) -{ - wlinfo("CE:%d\n", enable); - stm32_gpiowrite(GPIO_NRF24L01_CE, enable); -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -int stm32_wlinitialize(void) -{ - struct spi_dev_s *spidev; - int ret = OK; - - syslog(LOG_INFO, "Register the nRF24L01 module\n"); - - /* Setup CE & IRQ line IOs */ - - stm32_configgpio(GPIO_NRF24L01_CE); - stm32_configgpio(GPIO_NRF24L01_IRQ); - - /* Init SPI bus */ - - spidev = stm32_spibus_initialize(NRF24L01_SPI); - if (!spidev) - { - wlerr("ERROR: Failed to initialize SPI %d bus\n", NRF24L01_SPI); - ret = -ENODEV; - goto errout; - } - - ret = nrf24l01_register(spidev, &nrf_cfg); - if (ret != OK) - { - wlerr("ERROR: Failed to register initialize SPI bus\n"); - goto errout; - } - -errout: - return ret; -} diff --git a/boards/arm/stm32f0l0g0/nucleo-l073rz/src/stm32_spi.c b/boards/arm/stm32f0l0g0/nucleo-l073rz/src/stm32_spi.c deleted file mode 100644 index e9d0a74aae1d2..0000000000000 --- a/boards/arm/stm32f0l0g0/nucleo-l073rz/src/stm32_spi.c +++ /dev/null @@ -1,261 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-l073rz/src/stm32_spi.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include - -#include - -#include "arm_internal.h" -#include "chip.h" -#include "stm32_gpio.h" -#include "stm32_spi.h" - -#include "nucleo-l073rz.h" -#include - -#ifdef CONFIG_STM32F0L0G0_SPI - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_spidev_initialize - * - * Description: - * Called to configure SPI chip select GPIO pins for the Nucleo-144 board. - * - ****************************************************************************/ - -void stm32_spidev_initialize(void) -{ - /* NOTE: Clocking for SPI1 and/or SPI3 was already provided in stm32_rcc.c. - * Configurations of SPI pins is performed in stm32_spi.c. - * Here, we only initialize chip select pins unique to the board - * architecture. - */ - -#ifdef CONFIG_STM32F0L0G0_SPI1 - -# ifdef CONFIG_WL_NRF24L01 - /* Configure the SPI-based NRF24L01 chip select GPIO */ - - spiinfo("Configure GPIO for NRF24L01 SPI1/CS\n"); - - stm32_configgpio(GPIO_NRF24L01_CS); - stm32_gpiowrite(GPIO_NRF24L01_CS, true); -# endif - -# ifdef CONFIG_LPWAN_SX127X - /* Configure the SPI-based SX127X chip select GPIO */ - - spiinfo("Configure GPIO for SX127X SPI1/CS\n"); - - stm32_configgpio(GPIO_SX127X_CS); - stm32_gpiowrite(GPIO_SX127X_CS, true); -# endif - -#endif /* CONFIG_STM32F0L0G0_SPI1 */ - -#ifdef CONFIG_STM32F0L0G0_SPI2 - /* Configure the SPI-based MFRC522 chip select GPIO */ - -# ifdef CONFIG_CL_MFRC522 - stm32_configgpio(GPIO_MFRC522_CS); -# endif - -#endif /* CONFIG_STM32F0L0G0_SPI2 */ -} - -/**************************************************************************** - * Name: stm32_spi1/2/select and stm32_spi1/2/status - * - * Description: - * The external functions, stm32_spi1/2select and stm32_spi1/2status - * must be provided by board-specific logic. They are implementations of - * the select and status methods of the SPI interface defined by struct - * spi_ops_s (see include/nuttx/spi/spi.h). All other methods (including - * stm32_spibus_initialize()) are provided by common STM32 logic. - * To use this common SPI logic on your board: - * - * 1. Provide logic in stm32_boardinitialize() to configure SPI chip select - * pins. - * 2. Provide stm32_spi1/2select() and stm32_spi1/2status() functions - * in your board-specific logic. These functions will perform chip - * selection and status operations using GPIOs in the way your board is - * configured. - * 3. Add a calls to stm32_spibus_initialize() in your low level - * application initialization logic - * 4. The handle returned by stm32_spibus_initialize() may then be used to - * bind the SPI driver to higher level logic (e.g., calling - * mmcsd_spislotinitialize(), for example, will bind the SPI driver to - * the SPI MMC/SD driver). - * - ****************************************************************************/ - -#ifdef CONFIG_STM32F0L0G0_SPI1 -void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, - bool selected) -{ - spiinfo("devid: %d CS: %s\n", - (int)devid, selected ? "assert" : "de-assert"); - - switch (devid) - { -#ifdef CONFIG_WL_NRF24L01 - case SPIDEV_WIRELESS(0): - { - spiinfo("nRF24L01 device %s\n", - selected ? "asserted" : "de-asserted"); - - /* Set the GPIO low to select and high to de-select */ - - stm32_gpiowrite(GPIO_NRF24L01_CS, !selected); - break; - } -#endif - -#ifdef CONFIG_LPWAN_SX127X - case SPIDEV_LPWAN(0): - { - spiinfo("SX127X device %s\n", - selected ? "asserted" : "de-asserted"); - - /* Set the GPIO low to select and high to de-select */ - - stm32_gpiowrite(GPIO_SX127X_CS, !selected); - break; - } -#endif - - default: - { - break; - } - } -} - -uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) -{ - uint8_t status = 0; - - switch (devid) - { -#ifdef CONFIG_WL_NRF24L01 - case SPIDEV_WIRELESS(0): - { - status |= SPI_STATUS_PRESENT; - break; - } -#endif - -#ifdef CONFIG_LPWAN_SX127X - case SPIDEV_LPWAN(0): - { - status |= SPI_STATUS_PRESENT; - break; - } -#endif - - default: - { - break; - } - } - - return status; -} -#endif /* CONFIG_STM32F0L0G0_SPI1 */ - -#ifdef CONFIG_STM32F0L0G0_SPI2 -void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid, - bool selected) -{ - spiinfo("devid: %d CS: %s\n", - (int)devid, selected ? "assert" : "de-assert"); - - switch (devid) - { -#ifdef CONFIG_CL_MFRC522 - case SPIDEV_CONTACTLESS(0): - { - stm32_gpiowrite(GPIO_MFRC522_CS, !selected); - } -#endif - - default: - { - break; - } - } -} - -uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) -{ - uint8_t status = 0; - - switch (devid) - { -#ifdef CONFIG_CL_MFRC522 - case SPIDEV_CONTACTLESS(0): - { - status |= SPI_STATUS_PRESENT; - break; - } -#endif - - default: - { - break; - } - } - - return status; -} -#endif /* CONFIG_STM32F0L0G0_SPI2 */ - -#endif diff --git a/boards/arm/stm32f0l0g0/nucleo-l073rz/src/stm32_sx127x.c b/boards/arm/stm32f0l0g0/nucleo-l073rz/src/stm32_sx127x.c deleted file mode 100644 index a57868721089b..0000000000000 --- a/boards/arm/stm32f0l0g0/nucleo-l073rz/src/stm32_sx127x.c +++ /dev/null @@ -1,212 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-l073rz/src/stm32_sx127x.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -#include "stm32_gpio.h" -#include "stm32_exti.h" -#include "stm32_spi.h" - -#include "nucleo-l073rz.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* SX127X on SPI1 bus */ - -#define SX127X_SPI 1 - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -static void sx127x_chip_reset(void); -static int sx127x_opmode_change(int opmode); -static int sx127x_freq_select(uint32_t freq); -static int sx127x_pa_select(bool enable); -static int sx127x_irq0_attach(xcpt_t isr, void *arg); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -struct sx127x_lower_s lower = -{ - .irq0attach = sx127x_irq0_attach, - .reset = sx127x_chip_reset, - .opmode_change = sx127x_opmode_change, - .freq_select = sx127x_freq_select, - .pa_select = sx127x_pa_select, - .pa_force = true -}; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: sx127x_irq0_attach - ****************************************************************************/ - -static int sx127x_irq0_attach(xcpt_t isr, void *arg) -{ - wlinfo("Attach DIO0 IRQ\n"); - - /* IRQ on rising edge */ - - stm32_gpiosetevent(GPIO_SX127X_DIO0, true, false, false, isr, arg); - return OK; -} - -/**************************************************************************** - * Name: sx127x_chip_reset - ****************************************************************************/ - -static void sx127x_chip_reset(void) -{ - wlinfo("SX127X RESET\n"); - - /* Configure reset as output */ - - stm32_configgpio(GPIO_SX127X_RESET | GPIO_OUTPUT | GPIO_SPEED_HIGH | - GPIO_OUTPUT_CLEAR); - - /* Set pin to zero */ - - stm32_gpiowrite(GPIO_SX127X_RESET, false); - - /* Wait 1 ms */ - - nxsched_usleep(1000); - - /* Configure reset as input */ - - stm32_configgpio(GPIO_SX127X_RESET | GPIO_INPUT | GPIO_FLOAT); - - /* Wait 10 ms */ - - nxsched_usleep(10000); -} - -/**************************************************************************** - * Name: sx127x_opmode_change - ****************************************************************************/ - -static int sx127x_opmode_change(int opmode) -{ - /* Do nothing */ - - return OK; -} - -/**************************************************************************** - * Name: sx127x_freq_select - ****************************************************************************/ - -static int sx127x_freq_select(uint32_t freq) -{ - int ret = OK; - - /* NOTE: this depends on your module version */ - - if (freq > SX127X_HFBAND_THR) - { - ret = -EINVAL; - wlerr("HF band not supported\n"); - } - - return ret; -} - -/**************************************************************************** - * Name: sx127x_pa_select - ****************************************************************************/ - -static int sx127x_pa_select(bool enable) -{ - int ret = OK; - - /* Only PA_BOOST output connected to antenna */ - - if (enable == false) - { - ret = -EINVAL; - wlerr("Module supports only PA_BOOST pin, " - "so PA_SELECT must be enabled!\n"); - } - - return ret; -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -int stm32_lpwaninitialize(void) -{ - struct spi_dev_s *spidev; - int ret = OK; - - wlinfo("Register the sx127x module\n"); - - /* Setup DIO0 */ - - stm32_configgpio(GPIO_SX127X_DIO0); - - /* Init SPI bus */ - - spidev = stm32_spibus_initialize(SX127X_SPI); - if (!spidev) - { - wlerr("ERROR: Failed to initialize SPI %d bus\n", SX127X_SPI); - ret = -ENODEV; - goto errout; - } - - /* Initialize SX127X */ - - ret = sx127x_register(spidev, &lower); - if (ret < 0) - { - wlerr("ERROR: Failed to register sx127x\n"); - goto errout; - } - -errout: - return ret; -} diff --git a/boards/arm/stm32f0l0g0/stm32f051-discovery/CMakeLists.txt b/boards/arm/stm32f0l0g0/stm32f051-discovery/CMakeLists.txt deleted file mode 100644 index 3097fc40425d9..0000000000000 --- a/boards/arm/stm32f0l0g0/stm32f051-discovery/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32f0l0g0/stm32f051-discovery/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32f0l0g0/stm32f051-discovery/configs/nsh/defconfig b/boards/arm/stm32f0l0g0/stm32f051-discovery/configs/nsh/defconfig deleted file mode 100644 index 7539573f8bebb..0000000000000 --- a/boards/arm/stm32f0l0g0/stm32f051-discovery/configs/nsh/defconfig +++ /dev/null @@ -1,46 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_NSH_DISABLEBG is not set -# CONFIG_NSH_DISABLE_EXEC is not set -# CONFIG_NSH_DISABLE_EXIT is not set -# CONFIG_NSH_DISABLE_HEXDUMP is not set -# CONFIG_NSH_DISABLE_PS is not set -# CONFIG_NSH_DISABLE_XD is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f051-discovery" -CONFIG_ARCH_BOARD_STM32F051_DISCOVERY=y -CONFIG_ARCH_CHIP="stm32f0l0g0" -CONFIG_ARCH_CHIP_STM32F051R8=y -CONFIG_ARCH_CHIP_STM32F0=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=2796 -CONFIG_DEFAULT_SMALL=y -CONFIG_DISABLE_MOUNTPOINT=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INIT_STACKSIZE=1536 -CONFIG_MM_SMALL=y -CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 -CONFIG_NSH_FILEIOSIZE=64 -CONFIG_NUNGET_CHARS=0 -CONFIG_POSIX_SPAWN_DEFAULT_STACKSIZE=1536 -CONFIG_PTHREAD_STACK_DEFAULT=1536 -CONFIG_RAM_SIZE=8192 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=19 -CONFIG_START_MONTH=5 -CONFIG_START_YEAR=2013 -CONFIG_STM32F0L0G0_PWR=y -CONFIG_STM32F0L0G0_USART1=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART1_RXBUFSIZE=32 -CONFIG_USART1_SERIAL_CONSOLE=y -CONFIG_USART1_TXBUFSIZE=32 diff --git a/boards/arm/stm32f0l0g0/stm32f051-discovery/include/board.h b/boards/arm/stm32f0l0g0/stm32f051-discovery/include/board.h deleted file mode 100644 index 4436101e931c3..0000000000000 --- a/boards/arm/stm32f0l0g0/stm32f051-discovery/include/board.h +++ /dev/null @@ -1,241 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32f0l0g0/stm32f051-discovery/include/board.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __BOARDS_ARM_STM32F0L0G0_STM32F051_DISCOVERY_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32F0L0G0_STM32F051_DISCOVERY_INCLUDE_BOARD_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#ifndef __ASSEMBLY__ -# include -#endif - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Clocking *****************************************************************/ - -/* Four different clock sources can be used to drive the system clock - * (SYSCLK): - * - * - HSI high-speed internal oscillator clock - * Generated from an internal 8 MHz RC oscillator - * - HSE high-speed external oscillator clock - * Normally driven by an external crystal (X3). However, this crystal is - * not fitted on the STM32F0-Discovery board. - * - PLL clock - * - MSI multispeed internal oscillator clock - * The MSI clock signal is generated from an internal RC oscillator. Seven - * frequency ranges are available: 65.536 kHz, 131.072 kHz, 262.144 kHz, - * 524.288 kHz, 1.048 MHz, 2.097 MHz (default value) and 4.194 MHz. - * - * The devices have the following two secondary clock sources - * - LSI low-speed internal RC clock - * Drives the watchdog and RTC. Approximately 37KHz - * - LSE low-speed external oscillator clock - * Driven by 32.768KHz crystal (X2) on the OSC32_IN and OSC32_OUT pins. - */ - -#define STM32_BOARD_XTAL 8000000ul /* X3 on board (not fitted)*/ - -#define STM32_HSI_FREQUENCY 8000000ul /* Approximately 8MHz */ -#define STM32_HSI14_FREQUENCY 14000000ul /* HSI14 for ADC */ -#define STM32_HSI48_FREQUENCY 48000000ul /* HSI48 for USB, only some STM32F0xx */ -#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL -#define STM32_LSI_FREQUENCY 40000 /* Approximately 40KHz */ -#define STM32_LSE_FREQUENCY 32768 /* X2 on board */ - -/* PLL Configuration - * - * - PLL source is HSI -> 8MHz input (nominal) - * - PLL source predivider 2 -> 4MHz divided down PLL VCO clock output - * - PLL multiplier is 12 -> 48MHz PLL VCO clock output (for USB) - * - * Resulting SYSCLK frequency is 8MHz x 12 / 2 = 48MHz - * - * USB: - * If the USB interface is used in the application, it requires a precise - * 48MHz clock which can be generated from either the (1) the internal - * main PLL with the HSE clock source using an HSE crystal oscillator. In - * this case, the PLL VCO clock (defined by STM32_CFGR_PLLMUL) must be - * programmed to output a 96 MHz frequency. This is required to provide a - * 48MHz clock to the (USBCLK = PLLVCO/2). Or (2) by using the internal - * 48MHz oscillator in automatic trimming mode. The synchronization for - * this oscillator can be taken from the USB data stream itself (SOF - * signalization) which allows crystal-less operation. - * SYSCLK - * The system clock is derived from the PLL VCO divided by the output - * division factor. - * Limitations: - * - 96 MHz as PLLVCO when the product is in range 1 (1.8V), - * - 48 MHz as PLLVCO when the product is in range 2 (1.5V), - * - 24 MHz when the product is in range 3 (1.2V). - * - Output division to avoid exceeding 32 MHz as SYSCLK. - * - The minimum input clock frequency for PLL is 2 MHz (when using HSE as - * PLL source). - */ - -#define STM32_CFGR_PLLSRC RCC_CFGR_PLLSRC_HSId2 /* Source is HSI/2 */ -#define STM32_PLLSRC_FREQUENCY (STM32_HSI_FREQUENCY/2) /* 8MHz / 2 = 4MHz */ -#ifdef CONFIG_STM32F0L0G0_USB -# undef STM32_CFGR2_PREDIV /* Not used with source HSI/2 */ -# define STM32_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx12 /* PLLMUL = 12 */ -# define STM32_PLL_FREQUENCY (12*STM32_PLLSRC_FREQUENCY) /* PLL VCO Frequency is 48MHz */ -#else -# undef STM32_CFGR2_PREDIV /* Not used with source HSI/2 */ -# define STM32_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx12 /* PLLMUL = 12 */ -# define STM32_PLL_FREQUENCY (12*STM32_PLLSRC_FREQUENCY) /* PLL VCO Frequency is 48MHz */ -#endif - -/* Use the PLL and set the SYSCLK source to be the divided down PLL VCO - * output frequency (STM32_PLL_FREQUENCY divided by the PLLDIV value). - */ - -#define STM32_SYSCLK_SW RCC_CFGR_SW_PLL /* Use the PLL as the SYSCLK */ -#define STM32_SYSCLK_SWS RCC_CFGR_SWS_PLL -#ifdef CONFIG_STM32F0L0G0_USB -# define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY /* SYSCLK frequency is PLL VCO = 48MHz */ -#else -# define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY /* SYSCLK frequency is PLL VCO = 48MHz */ -#endif - -#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK -#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY - -/* APB1 clock (PCLK1) is HCLK (48MHz) */ - -#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK -#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY) - -/* APB2 clock (PCLK2) is HCLK (48MHz) */ - -#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK -#define STM32_PCLK2_FREQUENCY STM32_HCLK_FREQUENCY -#define STM32_APB2_CLKIN (STM32_PCLK2_FREQUENCY) - -/* APB1 timers 1-3, 6-7, and 14-17 will receive PCLK1 */ - -#define STM32_APB1_TIM1_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM2_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (STM32_PCLK1_FREQUENCY) - -#define STM32_APB1_TIM6_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (STM32_PCLK1_FREQUENCY) - -#define STM32_APB1_TIM14_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM15_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM16_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM17_CLKIN (STM32_PCLK1_FREQUENCY) - -/* LED definitions **********************************************************/ - -/* The STM32F0-Discovery board has four LEDs. Two of these are controlled by - * logic on the board and are not available for software control: - * - * LD1 COM: LD2 default status is red. LD2 turns to green to indicate that - * communications are in progress between the PC and the - * ST-LINK/V2. - * LD2 PWR: Red LED indicates that the board is powered. - * - * And two LEDs can be controlled by software: - * - * User LD3: Green LED is a user LED connected to the I/O PB7 of the - * STM32F051R8 MCU. - * User LD4: Blue LED is a user LED connected to the I/O PB6 of the - * STM32F051R8 MCU. - * - * If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs in - * any way. The following definitions are used to access individual LEDs. - */ - -/* LED index values for use with board_userled() */ - -#define BOARD_LED1 0 /* User LD3 */ -#define BOARD_LED2 1 /* User LD4 */ -#define BOARD_NLEDS 2 - -/* LED bits for use with board_userled_all() */ - -#define BOARD_LED1_BIT (1 << BOARD_LED1) -#define BOARD_LED2_BIT (1 << BOARD_LED2) - -/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the 8 LEDs on - * board the STM32F0-Discovery. - * The following definitions describe how NuttX controls the LEDs: - * - * SYMBOL Meaning LED state - * LED1 LED2 - * ------------------- ----------------------- -------- -------- - * LED_STARTED NuttX has been started OFF OFF - * LED_HEAPALLOCATE Heap has been allocated OFF OFF - * LED_IRQSENABLED Interrupts enabled OFF OFF - * LED_STACKCREATED Idle stack created ON OFF - * LED_INIRQ In an interrupt No change - * LED_SIGNAL In a signal handler No change - * LED_ASSERTION An assertion failed No change - * LED_PANIC The system has crashed OFF Blinking - * LED_IDLE STM32 is in sleep mode Not used - */ - -#define LED_STARTED 0 -#define LED_HEAPALLOCATE 0 -#define LED_IRQSENABLED 0 -#define LED_STACKCREATED 1 -#define LED_INIRQ 2 -#define LED_SIGNAL 2 -#define LED_ASSERTION 2 -#define LED_PANIC 3 - -/* Button definitions *******************************************************/ - -/* The STM32F0-Discovery supports two buttons; only one button is - * controllable by software: - * - * B1 USER: - * user and wake-up button connected to the I/O PA0 of the STM32F051R8. - * B2 RESET: - * pushbutton connected to NRST is used to RESET the STM32F051R8. - */ - -#define BUTTON_USER 0 -#define NUM_BUTTONS 1 - -#define BUTTON_USER_BIT (1 << BUTTON_USER) - -/* Alternate Pin Functions **************************************************/ - -/* USART 1 */ - -#define GPIO_USART1_TX (GPIO_USART1_TX_1|GPIO_SPEED_HIGH) -#define GPIO_USART1_RX (GPIO_USART1_RX_1|GPIO_SPEED_HIGH) - -/* I2C pins definition */ - -#define GPIO_I2C1_SCL (GPIO_I2C1_SCL_1|GPIO_SPEED_LOW) -#define GPIO_I2C1_SDA (GPIO_I2C1_SDA_1|GPIO_SPEED_LOW) - -#endif /* __BOARDS_ARM_STM32F0L0G0_STM32F051_DISCOVERY_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32f0l0g0/stm32f051-discovery/scripts/Make.defs b/boards/arm/stm32f0l0g0/stm32f051-discovery/scripts/Make.defs deleted file mode 100644 index 5d941d50d5a00..0000000000000 --- a/boards/arm/stm32f0l0g0/stm32f051-discovery/scripts/Make.defs +++ /dev/null @@ -1,41 +0,0 @@ -############################################################################ -# boards/arm/stm32f0l0g0/stm32f051-discovery/scripts/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/.config -include $(TOPDIR)/tools/Config.mk -include $(TOPDIR)/arch/arm/src/armv6-m/Toolchain.defs - -LDSCRIPT = flash.ld -ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) - -ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 - -CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) -CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) -CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -AFLAGS := $(CFLAGS) -D__ASSEMBLY__ - -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections -LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32f0l0g0/stm32f051-discovery/scripts/flash.ld b/boards/arm/stm32f0l0g0/stm32f051-discovery/scripts/flash.ld deleted file mode 100644 index bd4efbb45030b..0000000000000 --- a/boards/arm/stm32f0l0g0/stm32f051-discovery/scripts/flash.ld +++ /dev/null @@ -1,109 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32f0l0g0/stm32f051-discovery/scripts/flash.ld - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* The STM32F051R8T6 has 64KB of FLASH beginning at address 0x0800:0000 and - * 8Kb of SRAM at address 0x20000000. - * - * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 - * where the code expects to begin execution by jumping to the entry point in - * the 0x0800:0000 address range. - */ - -MEMORY -{ - flash (rx) : ORIGIN = 0x08000000, LENGTH = 64K - sram (rwx) : ORIGIN = 0x20000000, LENGTH = 8K -} - -OUTPUT_ARCH(arm) -EXTERN(_vectors) -ENTRY(_stext) - -SECTIONS -{ - .text : { - _stext = ABSOLUTE(.); - *(.vectors) - *(.text .text.*) - *(.fixup) - *(.gnu.warning) - *(.rodata .rodata.*) - *(.gnu.linkonce.t.*) - *(.glue_7) - *(.glue_7t) - *(.got) - *(.gcc_except_table) - *(.gnu.linkonce.r.*) - _etext = ABSOLUTE(.); - } > flash - - .init_section : { - _sinit = ABSOLUTE(.); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) - KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) - _einit = ABSOLUTE(.); - } > flash - - .ARM.extab ALIGN(4): { - *(.ARM.extab*) - } > flash - - .ARM.exidx : { - __exidx_start = ABSOLUTE(.); - *(.ARM.exidx*) - __exidx_end = ABSOLUTE(.); - } > flash - - _eronly = ABSOLUTE(.); - - .data : ALIGN(4) { - _sdata = ABSOLUTE(.); - *(.data .data.*) - *(.gnu.linkonce.d.*) - CONSTRUCTORS - . = ALIGN(4); - _edata = ABSOLUTE(.); - } > sram AT > flash - - .bss : ALIGN(4) { - _sbss = ABSOLUTE(.); - *(.bss .bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - . = ALIGN(8); - _ebss = ABSOLUTE(.); - } > sram - - /* Stabs debugging sections. */ - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_info 0 : { *(.debug_info) } - .debug_line 0 : { *(.debug_line) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_aranges 0 : { *(.debug_aranges) } -} diff --git a/boards/arm/stm32f0l0g0/stm32f051-discovery/src/CMakeLists.txt b/boards/arm/stm32f0l0g0/stm32f051-discovery/src/CMakeLists.txt deleted file mode 100644 index 185c0672fedfa..0000000000000 --- a/boards/arm/stm32f0l0g0/stm32f051-discovery/src/CMakeLists.txt +++ /dev/null @@ -1,49 +0,0 @@ -# ############################################################################## -# boards/arm/stm32f0l0g0/stm32f051-discovery/src/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -set(SRCS stm32_boot.c stm32_bringup.c) - -if(CONFIG_ARCH_LEDS) - list(APPEND SRCS stm32_autoleds.c) -else() - list(APPEND SRCS stm32_userleds.c) -endif() - -if(CONFIG_ARCH_BUTTONS) - list(APPEND SRCS stm32_buttons.c) -endif() - -if(CONFIG_STM32F0L0G0_SPI) - list(APPEND SRCS stm32_spi.c) -endif() - -if(CONFIG_PWM) - list(APPEND SRCS stm32_pwm.c) -endif() - -if(CONFIG_SENSORS_QENCODER) - list(APPEND SRCS stm32_qencoder.c) -endif() - -target_sources(board PRIVATE ${SRCS}) - -set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/flash.ld") diff --git a/boards/arm/stm32f0l0g0/stm32f051-discovery/src/Make.defs b/boards/arm/stm32f0l0g0/stm32f051-discovery/src/Make.defs deleted file mode 100644 index 520a4c8e8917b..0000000000000 --- a/boards/arm/stm32f0l0g0/stm32f051-discovery/src/Make.defs +++ /dev/null @@ -1,51 +0,0 @@ -############################################################################ -# boards/arm/stm32f0l0g0/stm32f051-discovery/src/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/Make.defs - -CSRCS = stm32_boot.c stm32_bringup.c - -ifeq ($(CONFIG_ARCH_LEDS),y) -CSRCS += stm32_autoleds.c -else -CSRCS += stm32_userleds.c -endif - -ifeq ($(CONFIG_ARCH_BUTTONS),y) -CSRCS += stm32_buttons.c -endif - -ifeq ($(CONFIG_STM32F0L0G0_SPI),y) -CSRCS += stm32_spi.c -endif - -ifeq ($(CONFIG_PWM),y) -CSRCS += stm32_pwm.c -endif - -ifeq ($(CONFIG_SENSORS_QENCODER),y) -CSRCS += stm32_qencoder.c -endif - -DEPPATH += --dep-path board -VPATH += :board -CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32f0l0g0/stm32f051-discovery/src/stm32_autoleds.c b/boards/arm/stm32f0l0g0/stm32f051-discovery/src/stm32_autoleds.c deleted file mode 100644 index 1528e56afd61f..0000000000000 --- a/boards/arm/stm32f0l0g0/stm32f051-discovery/src/stm32_autoleds.c +++ /dev/null @@ -1,123 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32f0l0g0/stm32f051-discovery/src/stm32_autoleds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include "chip.h" -#include "stm32f051-discovery.h" - -#ifdef CONFIG_ARCH_LEDS - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the 2 LEDs on - * board the STM32L-Discovery. The following definitions describe how NuttX - * controls the LEDs: - * - * SYMBOL Meaning LED state - * LED1 LED2 - * ------------------- ----------------------- -------- -------- - * LED_STARTED NuttX has been started OFF OFF - * LED_HEAPALLOCATE Heap has been allocated OFF OFF - * LED_IRQSENABLED Interrupts enabled OFF OFF - * LED_STACKCREATED Idle stack created ON OFF - * LED_INIRQ In an interrupt No change - * LED_SIGNAL In a signal handler No change - * LED_ASSERTION An assertion failed No change - * LED_PANIC The system has crashed OFF Blinking - * LED_IDLE STM32 is in sleep mode Not used - */ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_autoled_initialize - ****************************************************************************/ - -void board_autoled_initialize(void) -{ - /* Configure LED1-2 GPIOs for output */ - - stm32_configgpio(GPIO_LED1); - stm32_configgpio(GPIO_LED2); -} - -/**************************************************************************** - * Name: board_autoled_on - ****************************************************************************/ - -void board_autoled_on(int led) -{ - bool led1on = false; - bool led2on = false; - - switch (led) - { - case 0: /* LED_STARTED, LED_HEAPALLOCATE, LED_IRQSENABLED */ - break; - - case 1: /* LED_STACKCREATED */ - led1on = true; - break; - - default: - case 2: /* LED_INIRQ, LED_SIGNAL, LED_ASSERTION */ - return; - - case 3: /* LED_PANIC */ - led2on = true; - break; - } - - stm32_gpiowrite(GPIO_LED1, led1on); - stm32_gpiowrite(GPIO_LED2, led2on); -} - -/**************************************************************************** - * Name: board_autoled_off - ****************************************************************************/ - -void board_autoled_off(int led) -{ - if (led != 2) - { - stm32_gpiowrite(GPIO_LED1, false); - stm32_gpiowrite(GPIO_LED2, false); - } -} - -#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32f0l0g0/stm32f051-discovery/src/stm32_boot.c b/boards/arm/stm32f0l0g0/stm32f051-discovery/src/stm32_boot.c deleted file mode 100644 index bd53babb84aa0..0000000000000 --- a/boards/arm/stm32f0l0g0/stm32f051-discovery/src/stm32_boot.c +++ /dev/null @@ -1,81 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32f0l0g0/stm32f051-discovery/src/stm32_boot.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include -#include - -#include "arm_internal.h" -#include "stm32f051-discovery.h" - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_boardinitialize - * - * Description: - * All STM32 architectures must provide the following entry point. - * This entry point is called early in the initialization -- after all - * memory has been configured and mapped but before any devices have been - * initialized. - * - ****************************************************************************/ - -void stm32_boardinitialize(void) -{ -#ifdef CONFIG_ARCH_LEDS - /* Configure on-board LEDs if LED support has been selected. */ - - board_autoled_initialize(); -#endif -} - -/**************************************************************************** - * Name: board_late_initialize - * - * Description: - * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional - * initialization call will be performed in the boot-up sequence to a - * function called board_late_initialize(). board_late_initialize() will be - * called immediately after up_initialize() is called and just before the - * initial application is started. This additional initialization phase - * may be used, for example, to initialize board-specific device drivers. - * - ****************************************************************************/ - -#ifdef CONFIG_BOARD_LATE_INITIALIZE -void board_late_initialize(void) -{ - /* Perform board-specific initialization here if so configured */ - - stm32_bringup(); -} -#endif diff --git a/boards/arm/stm32f0l0g0/stm32f051-discovery/src/stm32_bringup.c b/boards/arm/stm32f0l0g0/stm32f051-discovery/src/stm32_bringup.c deleted file mode 100644 index 5ad5089520cc3..0000000000000 --- a/boards/arm/stm32f0l0g0/stm32f051-discovery/src/stm32_bringup.c +++ /dev/null @@ -1,66 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32f0l0g0/stm32f051-discovery/src/stm32_bringup.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include - -#include "stm32f051-discovery.h" - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_bringup - * - * Description: - * Perform architecture-specific initialization - * - * CONFIG_BOARD_LATE_INITIALIZE=y : - * Called from board_late_initialize(). - * - ****************************************************************************/ - -int stm32_bringup(void) -{ - int ret; - -#ifdef CONFIG_FS_PROCFS - /* Mount the procfs file system */ - - ret = nx_mount(NULL, "/proc", "procfs", 0, NULL); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: Failed to mount procfs at /proc: %d\n", ret); - } -#endif - - UNUSED(ret); - return OK; -} diff --git a/boards/arm/stm32f0l0g0/stm32f051-discovery/src/stm32_buttons.c b/boards/arm/stm32f0l0g0/stm32f051-discovery/src/stm32_buttons.c deleted file mode 100644 index 9fd07f705f527..0000000000000 --- a/boards/arm/stm32f0l0g0/stm32f051-discovery/src/stm32_buttons.c +++ /dev/null @@ -1,150 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32f0l0g0/stm32f051-discovery/src/stm32_buttons.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include -#include - -#include "stm32f051-discovery.h" - -#ifdef CONFIG_ARCH_BUTTONS - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* Pin configuration for each STM32F3Discovery button. This array is indexed - * by the BUTTON_* definitions in board.h - */ - -static const uint32_t g_buttons[NUM_BUTTONS] = -{ - GPIO_BTN_USER -}; - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_button_initialize - * - * Description: - * board_button_initialize() must be called to initialize button resources. - * After that, board_buttons() may be called to collect the current state - * of all buttons or board_button_irq() may be called to register button - * interrupt handlers. - * - ****************************************************************************/ - -uint32_t board_button_initialize(void) -{ - int i; - - /* Configure the GPIO pins as inputs. NOTE that EXTI interrupts are - * configured for all pins. - */ - - for (i = 0; i < NUM_BUTTONS; i++) - { - stm32_configgpio(g_buttons[i]); - } - - return NUM_BUTTONS; -} - -/**************************************************************************** - * Name: board_buttons - ****************************************************************************/ - -uint8_t board_buttons(void) -{ - uint8_t ret = 0; - int i; - - /* Check that state of each key */ - - for (i = 0; i < NUM_BUTTONS; i++) - { - /* A LOW value means that the key is pressed. */ - - bool released = stm32_gpioread(g_buttons[i]); - - /* Accumulate the set of depressed (not released) keys */ - - if (!released) - { - ret |= (1 << i); - } - } - - return ret; -} - -/**************************************************************************** - * Button support. - * - * Description: - * board_button_initialize() must be called to initialize button resources. - * After that, board_buttons() may be called to collect the current state - * of all buttons or board_button_irq() may be called to register button - * interrupt handlers. - * - * After board_button_initialize() has been called, board_buttons() may be - * called to collect the state of all buttons. board_buttons() returns an - * 8-bit bit set with each bit associated with a button. See the - * BUTTON_*_BIT definitions in board.h for the meaning of each bit. - * - * board_button_irq() may be called to register an interrupt handler that - * will be called when a button is depressed or released. The ID value is a - * button enumeration value that uniquely identifies a button resource. See - * the BUTTON_* definitions in board.h for the meaning of enumeration - * value. - * - ****************************************************************************/ - -#ifdef CONFIG_ARCH_IRQBUTTONS -int board_button_irq(int id, xcpt_t irqhandler, void *arg) -{ - int ret = -EINVAL; - - /* The following should be atomic */ - - if (id >= MIN_IRQBUTTON && id <= MAX_IRQBUTTON) - { - ret = stm32_gpiosetevent(g_buttons[id], true, true, true, - irqhandler, arg); - } - - return ret; -} -#endif -#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/stm32f0l0g0/stm32f051-discovery/src/stm32_userleds.c b/boards/arm/stm32f0l0g0/stm32f051-discovery/src/stm32_userleds.c deleted file mode 100644 index d0bda657d64fb..0000000000000 --- a/boards/arm/stm32f0l0g0/stm32f051-discovery/src/stm32_userleds.c +++ /dev/null @@ -1,97 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32f0l0g0/stm32f051-discovery/src/stm32_userleds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include - -#include "chip.h" -#include "stm32.h" -#include "stm32f051-discovery.h" - -#ifndef CONFIG_ARCH_LEDS - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_userled_initialize - ****************************************************************************/ - -uint32_t board_userled_initialize(void) -{ - /* Configure LED1-2 GPIOs for output */ - - stm32_configgpio(GPIO_LED1); - stm32_configgpio(GPIO_LED2); - return BOARD_NLEDS; -} - -/**************************************************************************** - * Name: board_userled - ****************************************************************************/ - -void board_userled(int led, bool ledon) -{ - uint32_t ledcfg; - - if (led == BOARD_LED1) - { - ledcfg = GPIO_LED1; - } - else if (led == BOARD_LED2) - { - ledcfg = GPIO_LED2; - } - else - { - return; - } - - stm32_gpiowrite(ledcfg, ledon); -} - -/**************************************************************************** - * Name: board_userled_all - ****************************************************************************/ - -void board_userled_all(uint32_t ledset) -{ - bool ledon; - - ledon = ((ledset & BOARD_LED1_BIT) != 0); - stm32_gpiowrite(GPIO_LED1, ledon); - - ledon = ((ledset & BOARD_LED2_BIT) != 0); - stm32_gpiowrite(GPIO_LED2, ledon); -} - -#endif /* !CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32f0l0g0/stm32f072-discovery/CMakeLists.txt b/boards/arm/stm32f0l0g0/stm32f072-discovery/CMakeLists.txt deleted file mode 100644 index 46b3a6cd11d6d..0000000000000 --- a/boards/arm/stm32f0l0g0/stm32f072-discovery/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32f0l0g0/stm32f072-discovery/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32f0l0g0/stm32f072-discovery/configs/nsh/defconfig b/boards/arm/stm32f0l0g0/stm32f072-discovery/configs/nsh/defconfig deleted file mode 100644 index 476c53cd1787f..0000000000000 --- a/boards/arm/stm32f0l0g0/stm32f072-discovery/configs/nsh/defconfig +++ /dev/null @@ -1,46 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_NSH_DISABLEBG is not set -# CONFIG_NSH_DISABLE_EXEC is not set -# CONFIG_NSH_DISABLE_EXIT is not set -# CONFIG_NSH_DISABLE_HEXDUMP is not set -# CONFIG_NSH_DISABLE_PS is not set -# CONFIG_NSH_DISABLE_XD is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f072-discovery" -CONFIG_ARCH_BOARD_STM32F072_DISCOVERY=y -CONFIG_ARCH_CHIP="stm32f0l0g0" -CONFIG_ARCH_CHIP_STM32F072RB=y -CONFIG_ARCH_CHIP_STM32F0=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=2796 -CONFIG_DEFAULT_SMALL=y -CONFIG_DISABLE_MOUNTPOINT=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INIT_STACKSIZE=1536 -CONFIG_MM_SMALL=y -CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 -CONFIG_NSH_FILEIOSIZE=64 -CONFIG_NUNGET_CHARS=0 -CONFIG_POSIX_SPAWN_DEFAULT_STACKSIZE=1536 -CONFIG_PTHREAD_STACK_DEFAULT=1536 -CONFIG_RAM_SIZE=8192 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=19 -CONFIG_START_MONTH=5 -CONFIG_START_YEAR=2013 -CONFIG_STM32F0L0G0_PWR=y -CONFIG_STM32F0L0G0_USART1=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART1_RXBUFSIZE=32 -CONFIG_USART1_SERIAL_CONSOLE=y -CONFIG_USART1_TXBUFSIZE=32 diff --git a/boards/arm/stm32f0l0g0/stm32f072-discovery/include/board.h b/boards/arm/stm32f0l0g0/stm32f072-discovery/include/board.h deleted file mode 100644 index 3ccd8972dfe2d..0000000000000 --- a/boards/arm/stm32f0l0g0/stm32f072-discovery/include/board.h +++ /dev/null @@ -1,246 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32f0l0g0/stm32f072-discovery/include/board.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __BOARDS_ARM_STM32F0L0G0_STM32F072_DISCOVERY_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32F0L0G0_STM32F072_DISCOVERY_INCLUDE_BOARD_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#ifndef __ASSEMBLY__ -# include -#endif - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Clocking *****************************************************************/ - -/* Four different clock sources can be used to drive the system clock - * (SYSCLK): - * - * - HSI high-speed internal oscillator clock - * Generated from an internal 8 MHz RC oscillator - * - HSE high-speed external oscillator clock - * Normally driven by an external crystal (X3). However, this crystal is - * not fitted on the STM32F0-Discovery board. - * - PLL clock - * - MSI multispeed internal oscillator clock - * The MSI clock signal is generated from an internal RC oscillator. Seven - * frequency ranges are available: 65.536 kHz, 131.072 kHz, 262.144 kHz, - * 524.288 kHz, 1.048 MHz, 2.097 MHz (default value) and 4.194 MHz. - * - * The devices have the following two secondary clock sources - * - LSI low-speed internal RC clock - * Drives the watchdog and RTC. Approximately 37KHz - * - LSE low-speed external oscillator clock - * Driven by 32.768KHz crystal (X2) on the OSC32_IN and OSC32_OUT pins. - */ - -#define STM32_BOARD_XTAL 8000000ul /* X3 on board (not fitted)*/ - -#define STM32_HSI_FREQUENCY 8000000ul /* Approximately 8MHz */ -#define STM32_HSI14_FREQUENCY 14000000ul /* HSI14 for ADC */ -#define STM32_HSI48_FREQUENCY 48000000ul /* HSI48 for USB, only some STM32F0xx */ -#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL -#define STM32_LSI_FREQUENCY 40000 /* Approximately 40KHz */ -#define STM32_LSE_FREQUENCY 32768 /* X2 on board */ - -/* PLL Configuration - * - * - PLL source is HSI -> 8MHz input (nominal) - * - PLL source predivider 2 -> 4MHz divided down PLL VCO clock output - * - PLL multiplier is 12 -> 48MHz PLL VCO clock output (for USB) - * - * Resulting SYSCLK frequency is 8MHz x 12 / 2 = 48MHz - * - * USB: - * If the USB interface is used in the application, it requires a precise - * 48MHz clock which can be generated from either the (1) the internal - * main PLL with the HSE clock source using an HSE crystal oscillator. In - * this case, the PLL VCO clock (defined by STM32_CFGR_PLLMUL) must be - * programmed to output a 96 MHz frequency. This is required to provide a - * 48MHz clock to the (USBCLK = PLLVCO/2). Or (2) by using the internal - * 48MHz oscillator in automatic trimming mode. The synchronization for - * this oscillator can be taken from the USB data stream itself (SOF - * signalization) which allows crystal-less operation. - * SYSCLK - * The system clock is derived from the PLL VCO divided by the output - * division factor. - * Limitations: - * - 96 MHz as PLLVCO when the product is in range 1 (1.8V), - * - 48 MHz as PLLVCO when the product is in range 2 (1.5V), - * - 24 MHz when the product is in range 3 (1.2V). - * - Output division to avoid exceeding 32 MHz as SYSCLK. - * - The minimum input clock frequency for PLL is 2 MHz (when using HSE as - * PLL source). - */ - -#define STM32_CFGR_PLLSRC RCC_CFGR_PLLSRC_HSId2 /* Source is HSI/2 */ -#define STM32_PLLSRC_FREQUENCY (STM32_HSI_FREQUENCY/2) /* 8MHz / 2 = 4MHz */ -#ifdef CONFIG_STM32F0L0G0_USB -# undef STM32_CFGR2_PREDIV /* Not used with source HSI/2 */ -# define STM32_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx12 /* PLLMUL = 12 */ -# define STM32_PLL_FREQUENCY (12*STM32_PLLSRC_FREQUENCY) /* PLL VCO Frequency is 48MHz */ -#else -# undef STM32_CFGR2_PREDIV /* Not used with source HSI/2 */ -# define STM32_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx12 /* PLLMUL = 12 */ -# define STM32_PLL_FREQUENCY (12*STM32_PLLSRC_FREQUENCY) /* PLL VCO Frequency is 48MHz */ -#endif - -/* Use the PLL and set the SYSCLK source to be the divided down PLL VCO - * output frequency (STM32_PLL_FREQUENCY divided by the PLLDIV value). - */ - -#define STM32_SYSCLK_SW RCC_CFGR_SW_PLL /* Use the PLL as the SYSCLK */ -#define STM32_SYSCLK_SWS RCC_CFGR_SWS_PLL -#ifdef CONFIG_STM32F0L0G0_USB -# define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY /* SYSCLK frequency is PLL VCO = 48MHz */ -#else -# define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY /* SYSCLK frequency is PLL VCO = 48MHz */ -#endif - -#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK -#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY - -/* APB1 clock (PCLK1) is HCLK (48MHz) */ - -#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK -#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY) - -/* APB2 clock (PCLK2) is HCLK (48MHz) */ - -#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK -#define STM32_PCLK2_FREQUENCY STM32_HCLK_FREQUENCY -#define STM32_APB2_CLKIN (STM32_PCLK2_FREQUENCY) - -/* APB1 timers 1-3, 6-7, and 14-17 will receive PCLK1 */ - -#define STM32_APB1_TIM1_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM2_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (STM32_PCLK1_FREQUENCY) - -#define STM32_APB1_TIM6_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (STM32_PCLK1_FREQUENCY) - -#define STM32_APB1_TIM14_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM15_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM16_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM17_CLKIN (STM32_PCLK1_FREQUENCY) - -/* LED definitions **********************************************************/ - -/* The STM32F0-Discovery board has four LEDs. Two of these are controlled by - * logic on the board and are not available for software control: - * - * LD1 COM: LD2 default status is red. LD2 turns to green to indicate that - * communications are in progress between the PC and the - * ST-LINK/V2. - * LD2 PWR: Red LED indicates that the board is powered. - * - * And two LEDs can be controlled by software: - * - * User LD3: Green LED is a user LED connected to the I/O PB7 of the - * STM32F072RB MCU. - * User LD4: Blue LED is a user LED connected to the I/O PB6 of the - * STM32F072RB MCU. - * - * If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs - * in any way. - * The following definitions are used to access individual LEDs. - */ - -/* LED index values for use with board_userled() */ - -#define BOARD_LED1 0 /* User LD_U */ -#define BOARD_LED2 1 /* User LD_D */ -#define BOARD_LED3 2 /* User LD_L */ -#define BOARD_LED4 3 /* User LD_R */ -#define BOARD_NLEDS 4 - -/* LED bits for use with board_userled_all() */ - -#define BOARD_LED1_BIT (1 << BOARD_LED1) -#define BOARD_LED2_BIT (1 << BOARD_LED2) -#define BOARD_LED3_BIT (1 << BOARD_LED3) -#define BOARD_LED4_BIT (1 << BOARD_LED4) - -/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the 8 LEDs on - * board the STM32F0-Discovery. - * The following definitions describe how NuttX controls the LEDs: - * - * SYMBOL Meaning LED state - * LED1 LED2 - * ------------------- ----------------------- -------- -------- - * LED_STARTED NuttX has been started OFF OFF - * LED_HEAPALLOCATE Heap has been allocated OFF OFF - * LED_IRQSENABLED Interrupts enabled OFF OFF - * LED_STACKCREATED Idle stack created ON OFF - * LED_INIRQ In an interrupt No change - * LED_SIGNAL In a signal handler No change - * LED_ASSERTION An assertion failed No change - * LED_PANIC The system has crashed OFF Blinking - * LED_IDLE STM32 is in sleep mode Not used - */ - -#define LED_STARTED 0 -#define LED_HEAPALLOCATE 0 -#define LED_IRQSENABLED 0 -#define LED_STACKCREATED 1 -#define LED_INIRQ 2 -#define LED_SIGNAL 2 -#define LED_ASSERTION 2 -#define LED_PANIC 3 - -/* Button definitions *******************************************************/ - -/* The STM32F0-Discovery supports two buttons; only one button is - * controllable by software: - * - * B1 USER: - * user and wake-up button connected to the I/O PA0 of the STM32F072RB. - * B2 RESET: - * pushbutton connected to NRST is used to RESET the STM32F072RB. - */ - -#define BUTTON_USER 0 -#define NUM_BUTTONS 1 - -#define BUTTON_USER_BIT (1 << BUTTON_USER) - -/* Alternate Pin Functions **************************************************/ - -/* USART 1 */ - -#define GPIO_USART1_TX (GPIO_USART1_TX_1|GPIO_SPEED_HIGH) -#define GPIO_USART1_RX (GPIO_USART1_RX_1|GPIO_SPEED_HIGH) - -/* I2C pins definition */ - -#define GPIO_I2C1_SCL (GPIO_I2C1_SCL_1|GPIO_SPEED_LOW) -#define GPIO_I2C1_SDA (GPIO_I2C1_SDA_1|GPIO_SPEED_LOW) - -#endif /* __BOARDS_ARM_STM32F0L0G0_STM32F072_DISCOVERY_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32f0l0g0/stm32f072-discovery/scripts/Make.defs b/boards/arm/stm32f0l0g0/stm32f072-discovery/scripts/Make.defs deleted file mode 100644 index 5d8a0c14523c9..0000000000000 --- a/boards/arm/stm32f0l0g0/stm32f072-discovery/scripts/Make.defs +++ /dev/null @@ -1,41 +0,0 @@ -############################################################################ -# boards/arm/stm32f0l0g0/stm32f072-discovery/scripts/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/.config -include $(TOPDIR)/tools/Config.mk -include $(TOPDIR)/arch/arm/src/armv6-m/Toolchain.defs - -LDSCRIPT = flash.ld -ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) - -ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 - -CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) -CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) -CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -AFLAGS := $(CFLAGS) -D__ASSEMBLY__ - -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections -LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32f0l0g0/stm32f072-discovery/scripts/flash.ld b/boards/arm/stm32f0l0g0/stm32f072-discovery/scripts/flash.ld deleted file mode 100644 index 5ae8a09a00d5f..0000000000000 --- a/boards/arm/stm32f0l0g0/stm32f072-discovery/scripts/flash.ld +++ /dev/null @@ -1,109 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32f0l0g0/stm32f072-discovery/scripts/flash.ld - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* The STM32F072RBT6 has 128KB of FLASH beginning at address 0x0800:0000 and - * 16Kb of SRAM at address 0x20000000. - * - * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 - * where the code expects to begin execution by jumping to the entry point in - * the 0x0800:0000 address range. - */ - -MEMORY -{ - flash (rx) : ORIGIN = 0x08000000, LENGTH = 128K - sram (rwx) : ORIGIN = 0x20000000, LENGTH = 16K -} - -OUTPUT_ARCH(arm) -EXTERN(_vectors) -ENTRY(_stext) - -SECTIONS -{ - .text : { - _stext = ABSOLUTE(.); - *(.vectors) - *(.text .text.*) - *(.fixup) - *(.gnu.warning) - *(.rodata .rodata.*) - *(.gnu.linkonce.t.*) - *(.glue_7) - *(.glue_7t) - *(.got) - *(.gcc_except_table) - *(.gnu.linkonce.r.*) - _etext = ABSOLUTE(.); - } > flash - - .init_section : ALIGN(4) { - _sinit = ABSOLUTE(.); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) - KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) - _einit = ABSOLUTE(.); - } > flash - - .ARM.extab ALIGN(4): { - *(.ARM.extab*) - } > flash - - .ARM.exidx : ALIGN(4) { - __exidx_start = ABSOLUTE(.); - *(.ARM.exidx*) - __exidx_end = ABSOLUTE(.); - } > flash - - _eronly = ABSOLUTE(.); - - .data : ALIGN(4) { - _sdata = ABSOLUTE(.); - *(.data .data.*) - *(.gnu.linkonce.d.*) - CONSTRUCTORS - . = ALIGN(4); - _edata = ABSOLUTE(.); - } > sram AT > flash - - .bss : ALIGN(4) { - _sbss = ABSOLUTE(.); - *(.bss .bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - . = ALIGN(8); - _ebss = ABSOLUTE(.); - } > sram - - /* Stabs debugging sections. */ - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_info 0 : { *(.debug_info) } - .debug_line 0 : { *(.debug_line) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_aranges 0 : { *(.debug_aranges) } -} diff --git a/boards/arm/stm32f0l0g0/stm32f072-discovery/src/CMakeLists.txt b/boards/arm/stm32f0l0g0/stm32f072-discovery/src/CMakeLists.txt deleted file mode 100644 index 0475024980bd0..0000000000000 --- a/boards/arm/stm32f0l0g0/stm32f072-discovery/src/CMakeLists.txt +++ /dev/null @@ -1,49 +0,0 @@ -# ############################################################################## -# boards/arm/stm32f0l0g0/stm32f072-discovery/src/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -set(SRCS stm32_boot.c stm32_bringup.c) - -if(CONFIG_ARCH_LEDS) - list(APPEND SRCS stm32_autoleds.c) -else() - list(APPEND SRCS stm32_userleds.c) -endif() - -if(CONFIG_ARCH_BUTTONS) - list(APPEND SRCS stm32_buttons.c) -endif() - -if(CONFIG_STM32F0L0G0_SPI) - list(APPEND SRCS stm32_spi.c) -endif() - -if(CONFIG_PWM) - list(APPEND SRCS stm32_pwm.c) -endif() - -if(CONFIG_SENSORS_QENCODER) - list(APPEND SRCS stm32_qencoder.c) -endif() - -target_sources(board PRIVATE ${SRCS}) - -set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/flash.ld") diff --git a/boards/arm/stm32f0l0g0/stm32f072-discovery/src/Make.defs b/boards/arm/stm32f0l0g0/stm32f072-discovery/src/Make.defs deleted file mode 100644 index 2963ffd2ae229..0000000000000 --- a/boards/arm/stm32f0l0g0/stm32f072-discovery/src/Make.defs +++ /dev/null @@ -1,51 +0,0 @@ -############################################################################ -# boards/arm/stm32f0l0g0/stm32f072-discovery/src/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/Make.defs - -CSRCS = stm32_boot.c stm32_bringup.c - -ifeq ($(CONFIG_ARCH_LEDS),y) -CSRCS += stm32_autoleds.c -else -CSRCS += stm32_userleds.c -endif - -ifeq ($(CONFIG_ARCH_BUTTONS),y) -CSRCS += stm32_buttons.c -endif - -ifeq ($(CONFIG_STM32F0L0G0_SPI),y) -CSRCS += stm32_spi.c -endif - -ifeq ($(CONFIG_PWM),y) -CSRCS += stm32_pwm.c -endif - -ifeq ($(CONFIG_SENSORS_QENCODER),y) -CSRCS += stm32_qencoder.c -endif - -DEPPATH += --dep-path board -VPATH += :board -CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32f0l0g0/stm32f072-discovery/src/stm32_autoleds.c b/boards/arm/stm32f0l0g0/stm32f072-discovery/src/stm32_autoleds.c deleted file mode 100644 index c6860f90f7a44..0000000000000 --- a/boards/arm/stm32f0l0g0/stm32f072-discovery/src/stm32_autoleds.c +++ /dev/null @@ -1,123 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32f0l0g0/stm32f072-discovery/src/stm32_autoleds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include "chip.h" -#include "stm32f072-discovery.h" - -#ifdef CONFIG_ARCH_LEDS - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the 2 LEDs on - * board the STM32L-Discovery. The following definitions describe how NuttX - * controls the LEDs: - * - * SYMBOL Meaning LED state - * LED1 LED2 - * ------------------- ----------------------- -------- -------- - * LED_STARTED NuttX has been started OFF OFF - * LED_HEAPALLOCATE Heap has been allocated OFF OFF - * LED_IRQSENABLED Interrupts enabled OFF OFF - * LED_STACKCREATED Idle stack created ON OFF - * LED_INIRQ In an interrupt No change - * LED_SIGNAL In a signal handler No change - * LED_ASSERTION An assertion failed No change - * LED_PANIC The system has crashed OFF Blinking - * LED_IDLE STM32 is in sleep mode Not used - */ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_autoled_initialize - ****************************************************************************/ - -void board_autoled_initialize(void) -{ - /* Configure LED1-2 GPIOs for output */ - - stm32_configgpio(GPIO_LED1); - stm32_configgpio(GPIO_LED2); -} - -/**************************************************************************** - * Name: board_autoled_on - ****************************************************************************/ - -void board_autoled_on(int led) -{ - bool led1on = false; - bool led2on = false; - - switch (led) - { - case 0: /* LED_STARTED, LED_HEAPALLOCATE, LED_IRQSENABLED */ - break; - - case 1: /* LED_STACKCREATED */ - led1on = true; - break; - - default: - case 2: /* LED_INIRQ, LED_SIGNAL, LED_ASSERTION */ - return; - - case 3: /* LED_PANIC */ - led2on = true; - break; - } - - stm32_gpiowrite(GPIO_LED1, led1on); - stm32_gpiowrite(GPIO_LED2, led2on); -} - -/**************************************************************************** - * Name: board_autoled_off - ****************************************************************************/ - -void board_autoled_off(int led) -{ - if (led != 2) - { - stm32_gpiowrite(GPIO_LED1, false); - stm32_gpiowrite(GPIO_LED2, false); - } -} - -#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32f0l0g0/stm32f072-discovery/src/stm32_boot.c b/boards/arm/stm32f0l0g0/stm32f072-discovery/src/stm32_boot.c deleted file mode 100644 index 623f491e91a00..0000000000000 --- a/boards/arm/stm32f0l0g0/stm32f072-discovery/src/stm32_boot.c +++ /dev/null @@ -1,81 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32f0l0g0/stm32f072-discovery/src/stm32_boot.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include -#include - -#include "arm_internal.h" -#include "stm32f072-discovery.h" - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_boardinitialize - * - * Description: - * All STM32 architectures must provide the following entry point. - * This entry point is called early in the initialization -- after all - * memory has been configured and mapped but before any devices have been - * initialized. - * - ****************************************************************************/ - -void stm32_boardinitialize(void) -{ -#ifdef CONFIG_ARCH_LEDS - /* Configure on-board LEDs if LED support has been selected. */ - - board_autoled_initialize(); -#endif -} - -/**************************************************************************** - * Name: board_late_initialize - * - * Description: - * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional - * initialization call will be performed in the boot-up sequence to a - * function called board_late_initialize(). board_late_initialize() will be - * called immediately after up_initialize() is called and just before the - * initial application is started. This additional initialization phase - * may be used, for example, to initialize board-specific device drivers. - * - ****************************************************************************/ - -#ifdef CONFIG_BOARD_LATE_INITIALIZE -void board_late_initialize(void) -{ - /* Perform board-specific initialization here if so configured */ - - stm32_bringup(); -} -#endif diff --git a/boards/arm/stm32f0l0g0/stm32f072-discovery/src/stm32_bringup.c b/boards/arm/stm32f0l0g0/stm32f072-discovery/src/stm32_bringup.c deleted file mode 100644 index 4302171b88103..0000000000000 --- a/boards/arm/stm32f0l0g0/stm32f072-discovery/src/stm32_bringup.c +++ /dev/null @@ -1,66 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32f0l0g0/stm32f072-discovery/src/stm32_bringup.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include - -#include "stm32f072-discovery.h" - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_bringup - * - * Description: - * Perform architecture-specific initialization - * - * CONFIG_BOARD_LATE_INITIALIZE=y : - * Called from board_late_initialize(). - * - ****************************************************************************/ - -int stm32_bringup(void) -{ - int ret; - -#ifdef CONFIG_FS_PROCFS - /* Mount the procfs file system */ - - ret = nx_mount(NULL, "/proc", "procfs", 0, NULL); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: Failed to mount procfs at /proc: %d\n", ret); - } -#endif - - UNUSED(ret); - return OK; -} diff --git a/boards/arm/stm32f0l0g0/stm32f072-discovery/src/stm32_buttons.c b/boards/arm/stm32f0l0g0/stm32f072-discovery/src/stm32_buttons.c deleted file mode 100644 index 6c894a4a375b5..0000000000000 --- a/boards/arm/stm32f0l0g0/stm32f072-discovery/src/stm32_buttons.c +++ /dev/null @@ -1,150 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32f0l0g0/stm32f072-discovery/src/stm32_buttons.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include -#include - -#include "stm32f072-discovery.h" - -#ifdef CONFIG_ARCH_BUTTONS - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* Pin configuration for each STM32F3Discovery button. This array is - * indexed by the BUTTON_* definitions in board.h - */ - -static const uint32_t g_buttons[NUM_BUTTONS] = -{ - GPIO_BTN_USER -}; - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_button_initialize - * - * Description: - * board_button_initialize() must be called to initialize button resources. - * After that, board_buttons() may be called to collect the current state - * of all buttons or board_button_irq() may be called to register button - * interrupt handlers. - * - ****************************************************************************/ - -uint32_t board_button_initialize(void) -{ - int i; - - /* Configure the GPIO pins as inputs. NOTE that EXTI interrupts are - * configured for all pins. - */ - - for (i = 0; i < NUM_BUTTONS; i++) - { - stm32_configgpio(g_buttons[i]); - } - - return NUM_BUTTONS; -} - -/**************************************************************************** - * Name: board_buttons - ****************************************************************************/ - -uint8_t board_buttons(void) -{ - uint8_t ret = 0; - int i; - - /* Check that state of each key */ - - for (i = 0; i < NUM_BUTTONS; i++) - { - /* A LOW value means that the key is pressed. */ - - bool released = stm32_gpioread(g_buttons[i]); - - /* Accumulate the set of depressed (not released) keys */ - - if (!released) - { - ret |= (1 << i); - } - } - - return ret; -} - -/**************************************************************************** - * Button support. - * - * Description: - * board_button_initialize() must be called to initialize button resources. - * After that, board_buttons() may be called to collect the current state - * of all buttons or board_button_irq() may be called to register button - * interrupt handlers. - * - * After board_button_initialize() has been called, board_buttons() may be - * called to collect the state of all buttons. board_buttons() returns an - * 8-bit bit set with each bit associated with a button. See the - * BUTTON_*_BIT definitions in board.h for the meaning of each bit. - * - * board_button_irq() may be called to register an interrupt handler that - * will be called when a button is depressed or released. The ID value is a - * button enumeration value that uniquely identifies a button resource. See - * the BUTTON_* definitions in board.h for the meaning of enumeration - * value. - * - ****************************************************************************/ - -#ifdef CONFIG_ARCH_IRQBUTTONS -int board_button_irq(int id, xcpt_t irqhandler, void *arg) -{ - int ret = -EINVAL; - - /* The following should be atomic */ - - if (id >= MIN_IRQBUTTON && id <= MAX_IRQBUTTON) - { - ret = stm32_gpiosetevent(g_buttons[id], true, true, true, - irqhandler, arg); - } - - return ret; -} -#endif -#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/stm32f0l0g0/stm32f072-discovery/src/stm32_userleds.c b/boards/arm/stm32f0l0g0/stm32f072-discovery/src/stm32_userleds.c deleted file mode 100644 index 555102839367f..0000000000000 --- a/boards/arm/stm32f0l0g0/stm32f072-discovery/src/stm32_userleds.c +++ /dev/null @@ -1,113 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32f0l0g0/stm32f072-discovery/src/stm32_userleds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include - -#include "chip.h" -#include "stm32.h" -#include "stm32f072-discovery.h" - -#ifndef CONFIG_ARCH_LEDS - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_userled_initialize - ****************************************************************************/ - -uint32_t board_userled_initialize(void) -{ - /* Configure LED1-2 GPIOs for output */ - - stm32_configgpio(GPIO_LED1); - stm32_configgpio(GPIO_LED2); - stm32_configgpio(GPIO_LED3); - stm32_configgpio(GPIO_LED4); - return BOARD_NLEDS; -} - -/**************************************************************************** - * Name: board_userled - ****************************************************************************/ - -void board_userled(int led, bool ledon) -{ - uint32_t ledcfg; - - if (led == BOARD_LED1) - { - ledcfg = GPIO_LED1; - } - else if (led == BOARD_LED2) - { - ledcfg = GPIO_LED2; - } - else if (led == BOARD_LED3) - { - ledcfg = GPIO_LED3; - } - else if (led == BOARD_LED4) - { - ledcfg = GPIO_LED4; - } - else - { - return; - } - - stm32_gpiowrite(ledcfg, ledon); -} - -/**************************************************************************** - * Name: board_userled_all - ****************************************************************************/ - -void board_userled_all(uint32_t ledset) -{ - bool ledon; - - ledon = ((ledset & BOARD_LED1_BIT) != 0); - stm32_gpiowrite(GPIO_LED1, ledon); - - ledon = ((ledset & BOARD_LED2_BIT) != 0); - stm32_gpiowrite(GPIO_LED2, ledon); - - ledon = ((ledset & BOARD_LED3_BIT) != 0); - stm32_gpiowrite(GPIO_LED3, ledon); - - ledon = ((ledset & BOARD_LED4_BIT) != 0); - stm32_gpiowrite(GPIO_LED4, ledon); -} - -#endif /* !CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32f0l0g0/stm32g071b-disco/CMakeLists.txt b/boards/arm/stm32f0l0g0/stm32g071b-disco/CMakeLists.txt deleted file mode 100644 index 9dcefda96ea37..0000000000000 --- a/boards/arm/stm32f0l0g0/stm32g071b-disco/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32f0l0g0/stm32g071b-disco/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32f0l0g0/stm32g071b-disco/configs/nsh/defconfig b/boards/arm/stm32f0l0g0/stm32g071b-disco/configs/nsh/defconfig deleted file mode 100644 index 3835900807616..0000000000000 --- a/boards/arm/stm32f0l0g0/stm32g071b-disco/configs/nsh/defconfig +++ /dev/null @@ -1,56 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_LEDS is not set -# CONFIG_NSH_ARGCAT is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32g071b-disco" -CONFIG_ARCH_BOARD_STM32G071B_DISCO=y -CONFIG_ARCH_CHIP="stm32f0l0g0" -CONFIG_ARCH_CHIP_STM32G071RB=y -CONFIG_ARCH_CHIP_STM32G0=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=2796 -CONFIG_BUILTIN=y -CONFIG_DISABLE_ENVIRON=y -CONFIG_DISABLE_MOUNTPOINT=y -CONFIG_DISABLE_MQUEUE=y -CONFIG_DISABLE_POSIX_TIMERS=y -CONFIG_DISABLE_PSEUDOFS_OPERATIONS=y -CONFIG_EXAMPLES_DJOYSTICK=y -CONFIG_EXAMPLES_HELLO=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INIT_STACKSIZE=1536 -CONFIG_INPUT=y -CONFIG_INPUT_DJOYSTICK=y -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_MM_SMALL=y -CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=64 -CONFIG_NSH_READLINE=y -CONFIG_NUNGET_CHARS=0 -CONFIG_POSIX_SPAWN_DEFAULT_STACKSIZE=1536 -CONFIG_PTHREAD_MUTEX_UNSAFE=y -CONFIG_PTHREAD_STACK_DEFAULT=1536 -CONFIG_RAM_SIZE=32760 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=19 -CONFIG_START_MONTH=5 -CONFIG_START_YEAR=2013 -CONFIG_STDIO_DISABLE_BUFFERING=y -CONFIG_STM32F0L0G0_PWR=y -CONFIG_STM32F0L0G0_USART3=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART3_SERIAL_CONSOLE=y -CONFIG_USERLED=y -CONFIG_USERLED_LOWER=y diff --git a/boards/arm/stm32f0l0g0/stm32g071b-disco/configs/oled/defconfig b/boards/arm/stm32f0l0g0/stm32g071b-disco/configs/oled/defconfig deleted file mode 100644 index a5ed5ebad7a6d..0000000000000 --- a/boards/arm/stm32f0l0g0/stm32g071b-disco/configs/oled/defconfig +++ /dev/null @@ -1,80 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_LEDS is not set -# CONFIG_EXAMPLES_NXLINES_DEFAULT_COLORS is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NX_DISABLE_1BPP is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32g071b-disco" -CONFIG_ARCH_BOARD_COMMON=y -CONFIG_ARCH_BOARD_STM32G071B_DISCO=y -CONFIG_ARCH_CHIP="stm32f0l0g0" -CONFIG_ARCH_CHIP_STM32G071RB=y -CONFIG_ARCH_CHIP_STM32G0=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=2796 -CONFIG_BUILTIN=y -CONFIG_DEBUG_FEATURES=y -CONFIG_DEBUG_FULLOPT=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_DISABLE_ENVIRON=y -CONFIG_DISABLE_MOUNTPOINT=y -CONFIG_DISABLE_POSIX_TIMERS=y -CONFIG_DISABLE_PSEUDOFS_OPERATIONS=y -CONFIG_EXAMPLES_DJOYSTICK=y -CONFIG_EXAMPLES_HELLO=y -CONFIG_EXAMPLES_NXHELLO=y -CONFIG_EXAMPLES_NXHELLO_BPP=1 -CONFIG_EXAMPLES_NXLINES=y -CONFIG_EXAMPLES_NXLINES_BORDERWIDTH=1 -CONFIG_EXAMPLES_NXLINES_BPP=1 -CONFIG_EXAMPLES_NXLINES_LINECOLOR=0xff -CONFIG_EXAMPLES_NXLINES_LINEWIDTH=1 -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INIT_STACKSIZE=1536 -CONFIG_INPUT=y -CONFIG_INPUT_DJOYSTICK=y -CONFIG_INTELHEX_BINARY=y -CONFIG_LCD=y -CONFIG_LCD_MAXCONTRAST=255 -CONFIG_LCD_RLANDSCAPE=y -CONFIG_LCD_SSD1306_CUSTOM=y -CONFIG_LINE_MAX=64 -CONFIG_MM_SMALL=y -CONFIG_MQ_MAXMSGSIZE=64 -CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=64 -CONFIG_NSH_READLINE=y -CONFIG_NUNGET_CHARS=0 -CONFIG_NX=y -CONFIG_NXFONTS_DISABLE_1BPP=y -CONFIG_NXFONT_MONO5X8=y -CONFIG_NX_BLOCKING=y -CONFIG_POSIX_SPAWN_DEFAULT_STACKSIZE=1536 -CONFIG_PTHREAD_MUTEX_UNSAFE=y -CONFIG_PTHREAD_STACK_DEFAULT=1536 -CONFIG_RAM_SIZE=32760 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_SPI_CMDDATA=y -CONFIG_START_DAY=19 -CONFIG_START_MONTH=5 -CONFIG_START_YEAR=2013 -CONFIG_STDIO_DISABLE_BUFFERING=y -CONFIG_STM32F0L0G0_PWR=y -CONFIG_STM32F0L0G0_SPI1=y -CONFIG_STM32F0L0G0_SPI1_COMMTYPE=1 -CONFIG_STM32F0L0G0_USART3=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART3_SERIAL_CONSOLE=y -CONFIG_USERLED=y -CONFIG_USERLED_LOWER=y diff --git a/boards/arm/stm32f0l0g0/stm32g071b-disco/include/board.h b/boards/arm/stm32f0l0g0/stm32g071b-disco/include/board.h deleted file mode 100644 index c3e14a3fe1d14..0000000000000 --- a/boards/arm/stm32f0l0g0/stm32g071b-disco/include/board.h +++ /dev/null @@ -1,180 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32f0l0g0/stm32g071b-disco/include/board.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __BOARDS_ARM_STM32F0L0G0_STM32G071B_DISCO_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32F0L0G0_STM32G071B_DISCO_INCLUDE_BOARD_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Clocking *****************************************************************/ - -/* HSI - Internal 16 MHz RC Oscillator - * LSI - 32 KHz RC - * HSE - 8 MHz from MCO output of ST-LINK - * LSE - 32.768 kHz - */ - -#define STM32_BOARD_XTAL 8000000ul - -#define STM32_HSI_FREQUENCY 16000000ul -#define STM32_LSI_FREQUENCY 32000 /* Between 30kHz and 60kHz */ -#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL -#define STM32_LSE_FREQUENCY 32768 /* X2 on board */ - -/* Main PLL Configuration. - * - * PLL source is HSI = 16,000,000 - * - * PLL_VCOx = (STM32_HSE_FREQUENCY / PLLM) * PLLN - * Subject to: - * - * 1 <= PLLM <= 8 - * 8 <= PLLN <= 86 - * 4 MHz <= PLL_IN <= 16MHz - * 64 MHz <= PLL_VCO <= 344MHz - * SYSCLK = PLLRCLK = PLL_VCO / PLLR - * - */ - -/* PLL source is HSI, PLLN=50, PLLM=4 - * PLLP enable, PLLQ enable, PLLR enable - * - * 2 <= PLLP <= 32 - * 2 <= PLLQ <= 8 - * 2 <= PLLR <= 8 - * - * PLLR <= 64MHz - * PLLQ <= 128MHz - * PLLP <= 128MHz - * - * PLL_VCO = (16,000,000 / 4) * 50 = 200 MHz - * - * PLLP = PLL_VCO/4 = 200 MHz / 4 = 40 MHz - * PLLQ = PLL_VCO/4 = 200 MHz / 4 = 40 MHz - * PLLR = PLL_VCO/4 = 200 MHz / 4 = 40 MHz - */ - -#define STM32_PLLCFG_PLLSRC RCC_PLLCFG_PLLSRC_HSI -#define STM32_PLLCFG_PLLCFG (RCC_PLLCFG_PLLPEN | \ - RCC_PLLCFG_PLLQEN | \ - RCC_PLLCFG_PLLREN) - -#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(4) -#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(50) -#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP(4) -#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(4) -#define STM32_PLLCFG_PLLR RCC_PLLCFG_PLLR(4) - -#define STM32_VCO_FREQUENCY ((STM32_HSE_FREQUENCY / 2) * 50) -#define STM32_PLLP_FREQUENCY (STM32_VCO_FREQUENCY / 4) -#define STM32_PLLQ_FREQUENCY (STM32_VCO_FREQUENCY / 4) -#define STM32_PLLR_FREQUENCY (STM32_VCO_FREQUENCY / 4) - -/* Use the PLL and set the SYSCLK source to be the PLLR (40MHz) */ - -#define STM32_SYSCLK_SW RCC_CFGR_SW_PLL -#define STM32_SYSCLK_SWS RCC_CFGR_SWS_PLL -#define STM32_SYSCLK_FREQUENCY (STM32_PLLR_FREQUENCY) -#define STM32_SYSCLK_FREQUENCY (STM32_PLLR_FREQUENCY) - -/* AHB clock (HCLK) is SYSCLK (40MHz) */ - -#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK -#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY - -/* APB1 clock (PCLK1) is HCLK/2 (20MHz) */ - -#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd2 -#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/2) - -/* LED definitions **********************************************************/ - -/* LED index values for use with board_userled() */ - -#define BOARD_LEDSINK 0 /* LD4: SINK mode LED */ -#define BOARD_LEDSOURCE 1 /* LD5: SOURCE mode LED */ -#define BOARD_LEDSPY 2 /* LD6: SPY mode LED */ -#define BOARD_LEDCC 3 /* LD7: CC mode LED */ -#define BOARD_NLEDS 4 - -/* LED bits for use with board_userled_all() */ - -#define BOARD_LEDSINK_BIT (1 << BOARD_LEDSINK) -#define BOARD_LEDSOURCE_BIT (1 << BOARD_LEDSOURCE) -#define BOARD_LEDSPY_BIT (1 << BOARD_LEDSPY) -#define BOARD_LEDCC_BIT (1 << BOARD_LEDCC) - -/* Button definitions *******************************************************/ - -/* The STM32G071B-DISO supports one buttons: - * - * B1 RESET: push button connected to NRST is used to RESET the - * STM32G071RB. - * - * and a Joystick: - * - * Joystick center - PC0 - * Joystick down - PC2 - * Joystick left - PC1 - * Joystick right - PC3 - * Joystick up - PC4 - */ - -/* Alternate function pin selections ****************************************/ - -/* USART */ - -/* By default the USART3 is connected to STLINK Virtual COM Port: - * USART3_RX - PC11 - * USART3_TX - PC10 - */ - -#define GPIO_USART3_RX (GPIO_USART3_RX_6|GPIO_SPEED_HIGH) /* PC11 */ -#define GPIO_USART3_TX (GPIO_USART3_TX_6|GPIO_SPEED_HIGH) /* PC10 */ - -/* I2C1 - * I2C1_SCL - PB6 - * I2C1_SDA - PB7 - */ - -#define GPIO_I2C1_SCL (GPIO_I2C1_SCL_2|GPIO_SPEED_LOW) /* PB6 */ -#define GPIO_I2C1_SDA (GPIO_I2C1_SDA_2|GPIO_SPEED_LOW) /* PB7 */ - -/* SPI1 - OLED display - * SPI1_MISO - not used - * SPI1_MOSI - PA2 - * SPI1_SCK - PA1 - */ - -#define GPIO_SPI1_MISO (0) /* Not used - simplex tx */ -#define GPIO_SPI1_MOSI (GPIO_SPI1_MOSI_1|GPIO_SPEED_MEDIUM) /* PA2 */ -#define GPIO_SPI1_SCK (GPIO_SPI1_SCK_1|GPIO_SPEED_MEDIUM) /* PA1 */ - -#endif /* __BOARDS_ARM_STM32F0L0G0_STM32G071B_DISCO_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32f0l0g0/stm32g071b-disco/scripts/Make.defs b/boards/arm/stm32f0l0g0/stm32g071b-disco/scripts/Make.defs deleted file mode 100644 index 8679bdc9fcdc3..0000000000000 --- a/boards/arm/stm32f0l0g0/stm32g071b-disco/scripts/Make.defs +++ /dev/null @@ -1,41 +0,0 @@ -############################################################################ -# boards/arm/stm32f0l0g0/stm32g071b-disco/scripts/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/.config -include $(TOPDIR)/tools/Config.mk -include $(TOPDIR)/arch/arm/src/armv6-m/Toolchain.defs - -LDSCRIPT = ld.script -ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) - -ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 - -CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) -CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) -CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -AFLAGS := $(CFLAGS) -D__ASSEMBLY__ - -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections -LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32f0l0g0/stm32g071b-disco/scripts/ld.script b/boards/arm/stm32f0l0g0/stm32g071b-disco/scripts/ld.script deleted file mode 100644 index 83336a8c174c1..0000000000000 --- a/boards/arm/stm32f0l0g0/stm32g071b-disco/scripts/ld.script +++ /dev/null @@ -1,115 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32f0l0g0/stm32g071b-disco/scripts/ld.script - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* The STM32GO71RB has 128Kb of FLASH beginning at address 0x0800:0000. - * 32Kb of SRAM - * - * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 - * where the code expects to begin execution by jumping to the entry point in - * the 0x0800:0000 address range. - */ - -MEMORY -{ - flash (rx) : ORIGIN = 0x08000000, LENGTH = 128K - sram (rwx) : ORIGIN = 0x20000000, LENGTH = 32K -} - -OUTPUT_ARCH(arm) -EXTERN(_vectors) -ENTRY(_stext) -SECTIONS -{ - .text : { - _stext = ABSOLUTE(.); - *(.vectors) - *(.text .text.*) - *(.fixup) - *(.gnu.warning) - *(.rodata .rodata.*) - *(.gnu.linkonce.t.*) - *(.glue_7) - *(.glue_7t) - *(.got) - *(.gcc_except_table) - *(.gnu.linkonce.r.*) - _etext = ABSOLUTE(.); - } > flash - - .init_section : ALIGN(4) { - _sinit = ABSOLUTE(.); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) - KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) - _einit = ABSOLUTE(.); - } > flash - - .ARM.extab : ALIGN(4) { - *(.ARM.extab*) - } > flash - - .ARM.exidx : ALIGN(4) { - __exidx_start = ABSOLUTE(.); - *(.ARM.exidx*) - __exidx_end = ABSOLUTE(.); - } > flash - - _eronly = ABSOLUTE(.); - - /* The RAM vector table (if present) should lie at the beginning of SRAM */ - - .ram_vectors : { - *(.ram_vectors) - } > sram - - .data : ALIGN(4) { - _sdata = ABSOLUTE(.); - *(.data .data.*) - *(.gnu.linkonce.d.*) - CONSTRUCTORS - . = ALIGN(4); - _edata = ABSOLUTE(.); - } > sram AT > flash - - .bss : ALIGN(4) { - _sbss = ABSOLUTE(.); - *(.bss .bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - . = ALIGN(4); - _ebss = ABSOLUTE(.); - } > sram - - /* Stabs debugging sections. */ - - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_info 0 : { *(.debug_info) } - .debug_line 0 : { *(.debug_line) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_aranges 0 : { *(.debug_aranges) } -} diff --git a/boards/arm/stm32f0l0g0/stm32g071b-disco/src/CMakeLists.txt b/boards/arm/stm32f0l0g0/stm32g071b-disco/src/CMakeLists.txt deleted file mode 100644 index 88d162b167978..0000000000000 --- a/boards/arm/stm32f0l0g0/stm32g071b-disco/src/CMakeLists.txt +++ /dev/null @@ -1,52 +0,0 @@ -# ############################################################################## -# boards/arm/stm32f0l0g0/stm32g071b-disco/src/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -set(SRCS stm32_boot.c stm32_bringup.c) - -# no auto leds -if(CONFIG_USERLED) - list(APPEND SRCS stm32_userleds.c) -endif() - -if(CONFIG_SPI) - list(APPEND SRCS stm32_spi.c) -endif() - -if(CONFIG_INPUT_DJOYSTICK) - list(APPEND SRCS stm32_djoystick.c) -endif() - -if(CONFIG_LCD_SSD1306) - list(APPEND SRCS stm32_lcd_ssd1306.c) -endif() - -if(CONFIG_SENSORS_INA226) - list(APPEND SRCS stm32_ina226.c) -endif() - -if(CONFIG_DEV_GPIO) - list(APPEND SRCS stm32_gpio.c) -endif() - -target_sources(board PRIVATE ${SRCS}) - -set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/ld.script") diff --git a/boards/arm/stm32f0l0g0/stm32g071b-disco/src/Make.defs b/boards/arm/stm32f0l0g0/stm32g071b-disco/src/Make.defs deleted file mode 100644 index 1f012b2515c36..0000000000000 --- a/boards/arm/stm32f0l0g0/stm32g071b-disco/src/Make.defs +++ /dev/null @@ -1,54 +0,0 @@ -############################################################################ -# boards/arm/stm32f0l0g0/stm32g071b-disco/src/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/Make.defs - -CSRCS = stm32_boot.c stm32_bringup.c - -# no auto leds -ifeq ($(CONFIG_USERLED),y) -CSRCS += stm32_userleds.c -endif - -ifeq ($(CONFIG_SPI),y) -CSRCS += stm32_spi.c -endif - -ifeq ($(CONFIG_INPUT_DJOYSTICK),y) -CSRCS += stm32_djoystick.c -endif - -ifeq ($(CONFIG_LCD_SSD1306),y) -CSRCS += stm32_lcd_ssd1306.c -endif - -ifeq ($(CONFIG_SENSORS_INA226),y) -CSRCS += stm32_ina226.c -endif - -ifeq ($(CONFIG_DEV_GPIO),y) -CSRCS += stm32_gpio.c -endif - -DEPPATH += --dep-path board -VPATH += :board -CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32f0l0g0/stm32g071b-disco/src/stm32_boot.c b/boards/arm/stm32f0l0g0/stm32g071b-disco/src/stm32_boot.c deleted file mode 100644 index fbd8501ea9f4f..0000000000000 --- a/boards/arm/stm32f0l0g0/stm32g071b-disco/src/stm32_boot.c +++ /dev/null @@ -1,85 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32f0l0g0/stm32g071b-disco/src/stm32_boot.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include "stm32g071b-disco.h" - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_boardinitialize - * - * Description: - * All STM32 architectures must provide the following entry point. This - * entry point is called early in the initialization -- after all memory - * has been configured and mapped but before any devices have been - * initialized. - * - ****************************************************************************/ - -void stm32_boardinitialize(void) -{ -#ifdef CONFIG_ARCH_LEDS - /* Configure on-board LEDs if LED support has been selected. */ - - board_autoled_initialize(); -#endif - -#ifdef CONFIG_STM32F0L0G0_SPI - /* Configure SPI chip selects */ - - stm32_spidev_initialize(); -#endif -} - -/**************************************************************************** - * Name: board_late_initialize - * - * Description: - * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional - * initialization call will be performed in the boot-up sequence to a - * function called board_late_initialize(). board_late_initialize() will - * be called immediately after up_initialize() is called and just before - * the initial application is started. This additional initialization - * phase may be used, for example, to initialize board-specific device - * drivers. - * - ****************************************************************************/ - -#ifdef CONFIG_BOARD_LATE_INITIALIZE -void board_late_initialize(void) -{ - /* Perform board-specific initialization */ - - stm32_bringup(); -} -#endif diff --git a/boards/arm/stm32f0l0g0/stm32g071b-disco/src/stm32_bringup.c b/boards/arm/stm32f0l0g0/stm32g071b-disco/src/stm32_bringup.c deleted file mode 100644 index c41a38d31a1f5..0000000000000 --- a/boards/arm/stm32f0l0g0/stm32g071b-disco/src/stm32_bringup.c +++ /dev/null @@ -1,114 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32f0l0g0/stm32g071b-disco/src/stm32_bringup.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include - -#include "stm32g071b-disco.h" - -#ifdef CONFIG_USERLED -# include -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_bringup - * - * Description: - * Perform architecture-specific initialization - * - * CONFIG_BOARD_LATE_INITIALIZE=y : - * Called from board_late_initialize(). - * - ****************************************************************************/ - -int stm32_bringup(void) -{ - int ret; - -#ifdef CONFIG_USERLED - /* Register the LED driver */ - - ret = userled_lower_initialize(LED_DRIVER_PATH); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: userled_lower_initialize() failed: %d\n", - ret); - return ret; - } -#endif - -#ifdef CONFIG_INPUT_DJOYSTICK - /* Initialize and register the joystick driver */ - - ret = stm32_djoy_initialization(); - if (ret != OK) - { - syslog(LOG_ERR, - "ERROR: Failed to register the joystick driver: %d\n", ret); - return ret; - } - - syslog(LOG_INFO, "Successfully registered the joystick driver\n"); -#endif - -#ifdef CONFIG_LCD_SSD1306_SPI - /* NOTE: SSD1315Z is compatible with the SSD1306 driver */ - - board_lcd_initialize(); -#endif - -#ifdef CONFIG_SENSORS_INA226 - /* Initialize and register the INA226 */ - - ret = stm32_ina226_initialization(); - if (ret != OK) - { - syslog(LOG_ERR, - "ERROR: Failed to register the INA226 drivers: %d\n", ret); - return ret; - } -#endif - -#ifdef CONFIG_DEV_GPIO - ret = stm32_gpio_initialize(); - if (ret < 0) - { - syslog(LOG_ERR, "Failed to initialize GPIO Driver: %d\n", ret); - return ret; - } -#endif - - UNUSED(ret); - return OK; -} diff --git a/boards/arm/stm32f0l0g0/stm32g071b-disco/src/stm32_djoystick.c b/boards/arm/stm32f0l0g0/stm32g071b-disco/src/stm32_djoystick.c deleted file mode 100644 index bd9171ece4a96..0000000000000 --- a/boards/arm/stm32f0l0g0/stm32g071b-disco/src/stm32_djoystick.c +++ /dev/null @@ -1,296 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32f0l0g0/stm32g071b-disco/src/stm32_djoystick.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include -#include -#include - -#include "stm32_gpio.h" -#include "stm32g071b-disco.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Number of Joystick discretes */ - -#define DJOY_NGPIOS 5 - -/* Bitset of supported Joystick discretes */ - -#define DJOY_SUPPORTED (DJOY_UP_BIT | DJOY_DOWN_BIT | DJOY_LEFT_BIT | \ - DJOY_RIGHT_BIT | DJOY_BUTTON_SELECT_BIT) - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -static djoy_buttonset_t -djoy_supported(const struct djoy_lowerhalf_s *lower); -static djoy_buttonset_t -djoy_sample(const struct djoy_lowerhalf_s *lower); -static void djoy_enable(const struct djoy_lowerhalf_s *lower, - djoy_buttonset_t press, djoy_buttonset_t release, - djoy_interrupt_t handler, void *arg); - -static void djoy_disable(void); -static int djoy_interrupt(int irq, void *context, void *arg); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* Pin configuration for each stm32g071b-disco joystick "button." - * Index using DJOY_* definitions in include/nuttx/input/djoystick.h. - */ - -static const uint32_t g_joygpio[DJOY_NGPIOS] = -{ - GPIO_JOY_UP, GPIO_JOY_DOWN, GPIO_JOY_LEFT, GPIO_JOY_RIGHT, GPIO_JOY_SEL -}; - -/* Current interrupt handler and argument */ - -static djoy_interrupt_t g_djoyhandler; -static void *g_djoyarg; - -/* This is the discrete joystick lower half driver interface */ - -static const struct djoy_lowerhalf_s g_djoylower = -{ - .dl_supported = djoy_supported, - .dl_sample = djoy_sample, - .dl_enable = djoy_enable, -}; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: djoy_supported - * - * Description: - * Return the set of buttons supported on the discrete joystick device - * - ****************************************************************************/ - -static djoy_buttonset_t -djoy_supported(const struct djoy_lowerhalf_s *lower) -{ - iinfo("Supported: %02x\n", DJOY_SUPPORTED); - return (djoy_buttonset_t)DJOY_SUPPORTED; -} - -/**************************************************************************** - * Name: djoy_sample - * - * Description: - * Return the current state of all discrete joystick buttons - * - ****************************************************************************/ - -static djoy_buttonset_t djoy_sample(const struct djoy_lowerhalf_s *lower) -{ - djoy_buttonset_t ret = 0; - int i; - bool released; - - /* Read each joystick GPIO value */ - - for (i = 0; i < DJOY_NGPIOS; i++) - { - released = stm32_gpioread(g_joygpio[i]); - if (!released) - { - ret |= (1 << i); - } - } - - iinfo("Retuning: %02x\n", DJOY_SUPPORTED); - return ret; -} - -/**************************************************************************** - * Name: djoy_enable - * - * Description: - * Enable interrupts on the selected set of joystick buttons. And empty - * set will disable all interrupts. - * - ****************************************************************************/ - -static void djoy_enable(const struct djoy_lowerhalf_s *lower, - djoy_buttonset_t press, djoy_buttonset_t release, - djoy_interrupt_t handler, void *arg) -{ - irqstate_t flags; - djoy_buttonset_t either = press | release; - djoy_buttonset_t bit; - bool rising; - bool falling; - int i; - - /* Start with all interrupts disabled */ - - flags = enter_critical_section(); - djoy_disable(); - - iinfo("press: %02x release: %02x handler: %p arg: %p\n", - press, release, handler, arg); - - /* If no events are indicated or if no handler is provided, then this - * must really be a request to disable interrupts. - */ - - if (either && handler) - { - /* Save the new the handler and argument */ - - g_djoyhandler = handler; - g_djoyarg = arg; - - /* Check each GPIO. */ - - for (i = 0; i < DJOY_NGPIOS; i++) - { - /* Enable interrupts on each pin that has either a press or - * release event associated with it. - */ - - bit = (1 << i); - if ((either & bit) != 0) - { - /* Active low so a press corresponds to a falling edge and - * a release corresponds to a rising edge. - */ - - falling = ((press & bit) != 0); - rising = ((release & bit) != 0); - - iinfo("GPIO %d: rising: %d falling: %d\n", - i, rising, falling); - - stm32_gpiosetevent(g_joygpio[i], rising, falling, - true, djoy_interrupt, NULL); - } - } - } - - leave_critical_section(flags); -} - -/**************************************************************************** - * Name: djoy_disable - * - * Description: - * Disable all joystick interrupts - * - ****************************************************************************/ - -static void djoy_disable(void) -{ - irqstate_t flags; - int i; - - /* Disable each joystick interrupt */ - - flags = enter_critical_section(); - for (i = 0; i < DJOY_NGPIOS; i++) - { - stm32_gpiosetevent(g_joygpio[i], false, false, false, NULL, NULL); - } - - leave_critical_section(flags); - - /* Nullify the handler and argument */ - - g_djoyhandler = NULL; - g_djoyarg = NULL; -} - -/**************************************************************************** - * Name: djoy_interrupt - * - * Description: - * Discrete joystick interrupt handler - * - ****************************************************************************/ - -static int djoy_interrupt(int irq, void *context, void *arg) -{ - DEBUGASSERT(g_djoyhandler); - if (g_djoyhandler) - { - g_djoyhandler(&g_djoylower, g_djoyarg); - } - - return OK; -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_djoy_initialization - * - * Description: - * Initialize and register the discrete joystick driver - * - ****************************************************************************/ - -int stm32_djoy_initialization(void) -{ - int i; - - /* Configure the GPIO pins as inputs. NOTE: This is unnecessary for - * interrupting pins since it will also be done by stm32_gpiosetevent(). - */ - - for (i = 0; i < DJOY_NGPIOS; i++) - { - stm32_configgpio(g_joygpio[i]); - } - - /* Make sure that all interrupts are disabled */ - - djoy_disable(); - - /* Register the joystick device as /dev/djoy0 */ - - return djoy_register("/dev/djoy0", &g_djoylower); -} diff --git a/boards/arm/stm32f0l0g0/stm32g071b-disco/src/stm32_gpio.c b/boards/arm/stm32f0l0g0/stm32g071b-disco/src/stm32_gpio.c deleted file mode 100644 index 310ba0bc75c4e..0000000000000 --- a/boards/arm/stm32f0l0g0/stm32g071b-disco/src/stm32_gpio.c +++ /dev/null @@ -1,322 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32f0l0g0/stm32g071b-disco/src/stm32_gpio.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include - -#include - -#include "stm32_gpio.h" - -#include "stm32g071b-disco.h" - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -struct stm32gpio_dev_s -{ - struct gpio_dev_s gpio; - uint8_t id; -}; - -struct stm32gpint_dev_s -{ - struct stm32gpio_dev_s stm32gpio; - pin_interrupt_t callback; -}; - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -static int gpin_read(struct gpio_dev_s *dev, bool *value); -static int gpout_read(struct gpio_dev_s *dev, bool *value); -static int gpout_write(struct gpio_dev_s *dev, bool value); -static int gpint_read(struct gpio_dev_s *dev, bool *value); -static int gpint_attach(struct gpio_dev_s *dev, - pin_interrupt_t callback); -static int gpint_enable(struct gpio_dev_s *dev, bool enable); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -static const struct gpio_operations_s gpin_ops = -{ - .go_read = gpin_read, - .go_write = NULL, - .go_attach = NULL, - .go_enable = NULL, -}; - -static const struct gpio_operations_s gpout_ops = -{ - .go_read = gpout_read, - .go_write = gpout_write, - .go_attach = NULL, - .go_enable = NULL, -}; - -static const struct gpio_operations_s gpint_ops = -{ - .go_read = gpint_read, - .go_write = NULL, - .go_attach = gpint_attach, - .go_enable = gpint_enable, -}; - -#if BOARD_NGPIOIN > 0 -/* This array maps the GPIO pins used as INPUT */ - -static const uint32_t g_gpioinputs[BOARD_NGPIOIN] = -{ - GPIO_IN1, - GPIO_IN2 -}; - -static struct stm32gpio_dev_s g_gpin[BOARD_NGPIOIN]; -#endif - -#if BOARD_NGPIOOUT -/* This array maps the GPIO pins used as OUTPUT */ - -static const uint32_t g_gpiooutputs[BOARD_NGPIOOUT] = -{ - GPIO_OUT1, - GPIO_OUT2, - GPIO_OUT3, - GPIO_OUT4 -}; - -static struct stm32gpio_dev_s g_gpout[BOARD_NGPIOOUT]; -#endif - -#if BOARD_NGPIOINT > 0 -/* This array maps the GPIO pins used as INTERRUPT INPUTS */ - -static const uint32_t g_gpiointinputs[BOARD_NGPIOINT] = -{ - GPIO_INT1, -}; - -static struct stm32gpint_dev_s g_gpint[BOARD_NGPIOINT]; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -static int stm32gpio_interrupt(int irq, void *context, void *arg) -{ - struct stm32gpint_dev_s *stm32gpint = - (struct stm32gpint_dev_s *)arg; - - DEBUGASSERT(stm32gpint != NULL && stm32gpint->callback != NULL); - gpioinfo("Interrupt! callback=%p\n", stm32gpint->callback); - - stm32gpint->callback(&stm32gpint->stm32gpio.gpio, - stm32gpint->stm32gpio.id); - return OK; -} - -static int gpin_read(struct gpio_dev_s *dev, bool *value) -{ - struct stm32gpio_dev_s *stm32gpio = - (struct stm32gpio_dev_s *)dev; - - DEBUGASSERT(stm32gpio != NULL && value != NULL); - DEBUGASSERT(stm32gpio->id < BOARD_NGPIOIN); - gpioinfo("Reading...\n"); - - *value = stm32_gpioread(g_gpioinputs[stm32gpio->id]); - return OK; -} - -static int gpout_read(struct gpio_dev_s *dev, bool *value) -{ - struct stm32gpio_dev_s *stm32gpio = - (struct stm32gpio_dev_s *)dev; - - DEBUGASSERT(stm32gpio != NULL && value != NULL); - DEBUGASSERT(stm32gpio->id < BOARD_NGPIOOUT); - gpioinfo("Reading...\n"); - - *value = stm32_gpioread(g_gpiooutputs[stm32gpio->id]); - return OK; -} - -static int gpout_write(struct gpio_dev_s *dev, bool value) -{ - struct stm32gpio_dev_s *stm32gpio = - (struct stm32gpio_dev_s *)dev; - - DEBUGASSERT(stm32gpio != NULL); - DEBUGASSERT(stm32gpio->id < BOARD_NGPIOOUT); - gpioinfo("Writing %d\n", (int)value); - - stm32_gpiowrite(g_gpiooutputs[stm32gpio->id], value); - return OK; -} - -static int gpint_read(struct gpio_dev_s *dev, bool *value) -{ - struct stm32gpint_dev_s *stm32gpint = - (struct stm32gpint_dev_s *)dev; - - DEBUGASSERT(stm32gpint != NULL && value != NULL); - DEBUGASSERT(stm32gpint->stm32gpio.id < BOARD_NGPIOINT); - gpioinfo("Reading int pin...\n"); - - *value = stm32_gpioread(g_gpiointinputs[stm32gpint->stm32gpio.id]); - return OK; -} - -static int gpint_attach(struct gpio_dev_s *dev, - pin_interrupt_t callback) -{ - struct stm32gpint_dev_s *stm32gpint = - (struct stm32gpint_dev_s *)dev; - - gpioinfo("Attaching the callback\n"); - - /* Make sure the interrupt is disabled */ - - stm32_gpiosetevent(g_gpiointinputs[stm32gpint->stm32gpio.id], false, - false, false, NULL, NULL); - - gpioinfo("Attach %p\n", callback); - stm32gpint->callback = callback; - return OK; -} - -static int gpint_enable(struct gpio_dev_s *dev, bool enable) -{ - struct stm32gpint_dev_s *stm32gpint = - (struct stm32gpint_dev_s *)dev; - - if (enable) - { - if (stm32gpint->callback != NULL) - { - gpioinfo("Enabling the interrupt\n"); - - /* Configure the interrupt for rising edge */ - - stm32_gpiosetevent(g_gpiointinputs[stm32gpint->stm32gpio.id], - true, false, false, stm32gpio_interrupt, - &g_gpint[stm32gpint->stm32gpio.id]); - } - } - else - { - gpioinfo("Disable the interrupt\n"); - stm32_gpiosetevent(g_gpiointinputs[stm32gpint->stm32gpio.id], - false, false, false, NULL, NULL); - } - - return OK; -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_gpio_initialize - * - * Description: - * Initialize GPIO drivers for use with /apps/examples/gpio - * - ****************************************************************************/ - -int stm32_gpio_initialize(void) -{ - int i; - int pincount = 0; - -#if BOARD_NGPIOIN > 0 - for (i = 0; i < BOARD_NGPIOIN; i++) - { - /* Setup and register the GPIO pin */ - - g_gpin[i].gpio.gp_pintype = GPIO_INPUT_PIN; - g_gpin[i].gpio.gp_ops = &gpin_ops; - g_gpin[i].id = i; - gpio_pin_register(&g_gpin[i].gpio, pincount); - - /* Configure the pin that will be used as input */ - - stm32_configgpio(g_gpioinputs[i]); - - pincount++; - } -#endif - -#if BOARD_NGPIOOUT > 0 - for (i = 0; i < BOARD_NGPIOOUT; i++) - { - /* Setup and register the GPIO pin */ - - g_gpout[i].gpio.gp_pintype = GPIO_OUTPUT_PIN; - g_gpout[i].gpio.gp_ops = &gpout_ops; - g_gpout[i].id = i; - gpio_pin_register(&g_gpout[i].gpio, pincount); - - /* Configure the pin that will be used as output */ - - stm32_gpiowrite(g_gpiooutputs[i], 0); - stm32_configgpio(g_gpiooutputs[i]); - - pincount++; - } -#endif - -#if BOARD_NGPIOINT > 0 - for (i = 0; i < BOARD_NGPIOINT; i++) - { - /* Setup and register the GPIO pin */ - - g_gpint[i].stm32gpio.gpio.gp_pintype = GPIO_INTERRUPT_PIN; - g_gpint[i].stm32gpio.gpio.gp_ops = &gpint_ops; - g_gpint[i].stm32gpio.id = i; - gpio_pin_register(&g_gpint[i].stm32gpio.gpio, pincount); - - /* Configure the pin that will be used as interrupt input */ - - stm32_configgpio(g_gpiointinputs[i]); - - pincount++; - } -#endif - - return 0; -} diff --git a/boards/arm/stm32f0l0g0/stm32g071b-disco/src/stm32_lcd_ssd1306.c b/boards/arm/stm32f0l0g0/stm32g071b-disco/src/stm32_lcd_ssd1306.c deleted file mode 100644 index ee25ef5734fdf..0000000000000 --- a/boards/arm/stm32f0l0g0/stm32g071b-disco/src/stm32_lcd_ssd1306.c +++ /dev/null @@ -1,103 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32f0l0g0/stm32g071b-disco/src/stm32_lcd_ssd1306.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include -#include -#include - -#include "stm32_gpio.h" - -#include "stm32g071b-disco.h" - -#include "stm32_ssd1306.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#define OLED_SPI_PORT 1 /* OLED display connected to SPI1 */ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_lcd_initialize - ****************************************************************************/ - -int board_lcd_initialize(void) -{ - int ret; - - /* Configure the OLED GPIOs. This initial configuration is RESET low, - * putting the OLED into reset state. - */ - - stm32_configgpio(GPIO_SSD1306_RST); - stm32_gpiowrite(GPIO_SSD1306_RST, 0); - - /* Wait a bit then release the OLED from the reset state */ - - up_mdelay(20); - stm32_gpiowrite(GPIO_SSD1306_RST, 1); - - /* Initialize OLED */ - - ret = board_ssd1306_initialize(OLED_SPI_PORT); - if (ret < 0) - { - lcderr("ERROR: Failed to initialize SSD1306\n"); - return ret; - } - - return OK; -} - -/**************************************************************************** - * Name: board_lcd_getdev - ****************************************************************************/ - -struct lcd_dev_s *board_lcd_getdev(int devno) -{ - return board_ssd1306_getdev(); -} - -/**************************************************************************** - * Name: board_lcd_uninitialize - ****************************************************************************/ - -void board_lcd_uninitialize(void) -{ - /* TO-FIX */ -} diff --git a/boards/arm/stm32f0l0g0/stm32g071b-disco/src/stm32_spi.c b/boards/arm/stm32f0l0g0/stm32g071b-disco/src/stm32_spi.c deleted file mode 100644 index fcac1bef78e58..0000000000000 --- a/boards/arm/stm32f0l0g0/stm32g071b-disco/src/stm32_spi.c +++ /dev/null @@ -1,213 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32f0l0g0/stm32g071b-disco/src/stm32_spi.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include - -#include - -#include "stm32_gpio.h" -#include "stm32_spi.h" - -#include - -#include "stm32g071b-disco.h" - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/* Global driver instances */ - -#ifdef CONFIG_STM32F0L0G0_SPI1 -struct spi_dev_s *g_spi1; -#endif -#ifdef CONFIG_STM32F0L0G0_SPI2 -struct spi_dev_s *g_spi2; -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_spidev_initialize - * - * Description: - * Called to configure SPI chip select GPIO pins for the Nucleo-F401RE and - * Nucleo-F411RE boards. - * - ****************************************************************************/ - -void weak_function stm32_spidev_initialize(void) -{ -#ifdef CONFIG_STM32F0L0G0_SPI1 - /* Configure SPI-based devices */ - - g_spi1 = stm32_spibus_initialize(1); - if (!g_spi1) - { - spierr("ERROR: FAILED to initialize SPI port 1\n"); - } -#endif - -#ifdef CONFIG_LCD_SSD1306_SPI - stm32_configgpio(GPIO_SSD1306_CS); /* SSD1306 chip select */ - stm32_configgpio(GPIO_SSD1306_CMD); /* SSD1306 data/!command */ -#endif -} - -/**************************************************************************** - * Name: stm32_spi1/2/3select and stm32_spi1/2/3status - * - * Description: - * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status - * must be provided by board-specific logic. They are implementations of - * the select and status methods of the SPI interface defined by struct - * spi_ops_s (see include/nuttx/spi/spi.h). All other methods (including - * stm32_spibus_initialize()) are provided by common STM32 logic. To use - * this common SPI logic on your board: - * - * 1. Provide logic in stm32_boardinitialize() to configure SPI chip select - * pins. - * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() functions - * in your board-specific logic. These functions will perform chip - * selection and status operations using GPIOs in the way your board is - * configured. - * 3. Add a calls to stm32_spibus_initialize() in your low level - * application initialization logic - * 4. The handle returned by stm32_spibus_initialize() may then be used to - * bind the SPI driver to higher level logic (e.g., calling - * mmcsd_spislotinitialize(), for example, will bind the SPI driver to - * the SPI MMC/SD driver). - * - ****************************************************************************/ - -#ifdef CONFIG_STM32F0L0G0_SPI1 -void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, - bool selected) -{ - spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : - "de-assert"); - -#if defined(CONFIG_LCD_SSD1306_SPI) - if (devid == SPIDEV_DISPLAY(0)) - { - stm32_gpiowrite(GPIO_SSD1306_CS, !selected); - } -#endif -} - -uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) -{ - return 0; -} -#endif - -#ifdef CONFIG_STM32F0L0G0_SPI2 -void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid, - bool selected) -{ - spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : - "de-assert"); -} - -uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) -{ - return 0; -} -#endif - -#ifdef CONFIG_STM32F0L0G0_SPI3 -void stm32_spi3select(struct spi_dev_s *dev, uint32_t devid, - bool selected) -{ - spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : - "de-assert"); -} - -uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid) -{ - return 0; -} -#endif - -/**************************************************************************** - * Name: stm32_spi1cmddata - * - * Description: - * Set or clear the SD1306 D/C n bit to select data (true) or command - * (false). This function must be provided by platform-specific - * logic. This is an implementation of the cmddata method of the SPI - * interface defined by struct spi_ops_s (see include/nuttx/spi/spi.h). - * - * Input Parameters: - * - * spi - SPI device that controls the bus the device that requires the CMD/ - * DATA selection. - * devid - If there are multiple devices on the bus, this selects which one - * to select cmd or data. NOTE: This design restricts, for example, - * one one SPI display per SPI bus. - * cmd - true: select command; false: select data - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef CONFIG_SPI_CMDDATA -#ifdef CONFIG_STM32F0L0G0_SPI1 -int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) -{ -#if defined(CONFIG_LCD_SSD1306_SPI) - if (devid == SPIDEV_DISPLAY(0)) - { - stm32_gpiowrite(GPIO_SSD1306_CMD, !cmd); - } -#endif - - return OK; -} -#endif - -#ifdef CONFIG_STM32F0L0G0_SPI2 -int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) -{ - return OK; -} -#endif - -#ifdef CONFIG_STM32F0L0G0_SPI3 -int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) -{ - return OK; -} -#endif -#endif /* CONFIG_SPI_CMDDATA */ diff --git a/boards/arm/stm32f0l0g0/stm32g071b-disco/src/stm32_userleds.c b/boards/arm/stm32f0l0g0/stm32g071b-disco/src/stm32_userleds.c deleted file mode 100644 index d8845d205d5bf..0000000000000 --- a/boards/arm/stm32f0l0g0/stm32g071b-disco/src/stm32_userleds.c +++ /dev/null @@ -1,92 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32f0l0g0/stm32g071b-disco/src/stm32_userleds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include - -#include "stm32_gpio.h" -#include "stm32g071b-disco.h" - -#include - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* This array maps an LED number to GPIO pin configuration */ - -static uint32_t g_ledcfg[BOARD_NLEDS] = -{ - GPIO_LEDSINK, GPIO_LEDSOURCE, GPIO_LEDSPY, GPIO_LEDCC -}; - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_userled_initialize - ****************************************************************************/ - -uint32_t board_userled_initialize(void) -{ - /* Configure LED GPIOs for output */ - - stm32_configgpio(GPIO_LEDSINK); - stm32_configgpio(GPIO_LEDSOURCE); - stm32_configgpio(GPIO_LEDSPY); - stm32_configgpio(GPIO_LEDCC); - - return BOARD_NLEDS; -} - -/**************************************************************************** - * Name: board_userled - ****************************************************************************/ - -void board_userled(int led, bool ledon) -{ - if ((unsigned)led < BOARD_NLEDS) - { - stm32_gpiowrite(g_ledcfg[led], !ledon); - } -} - -/**************************************************************************** - * Name: board_userled_all - ****************************************************************************/ - -void board_userled_all(uint32_t ledset) -{ - stm32_gpiowrite(GPIO_LEDSINK, (ledset & BOARD_LEDSINK_BIT) != 0); - stm32_gpiowrite(GPIO_LEDSOURCE, (ledset & BOARD_LEDSOURCE_BIT) != 0); - stm32_gpiowrite(GPIO_LEDSPY, (ledset & BOARD_LEDSPY_BIT) != 0); - stm32_gpiowrite(GPIO_LEDCC, (ledset & BOARD_LEDCC_BIT) != 0); -} diff --git a/boards/arm/stm32f0l0g0/stm32l0538-disco/CMakeLists.txt b/boards/arm/stm32f0l0g0/stm32l0538-disco/CMakeLists.txt deleted file mode 100644 index 367387d199b74..0000000000000 --- a/boards/arm/stm32f0l0g0/stm32l0538-disco/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32f0l0g0/stm32l0538-disco/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32f0l0g0/stm32l0538-disco/configs/nsh/defconfig b/boards/arm/stm32f0l0g0/stm32l0538-disco/configs/nsh/defconfig deleted file mode 100644 index 4510918393862..0000000000000 --- a/boards/arm/stm32f0l0g0/stm32l0538-disco/configs/nsh/defconfig +++ /dev/null @@ -1,48 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_SYSTEM_DD_STATS is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32l0538-disco" -CONFIG_ARCH_BOARD_STM32L0538_DISCO=y -CONFIG_ARCH_CHIP="stm32f0l0g0" -CONFIG_ARCH_CHIP_STM32L053C8=y -CONFIG_ARCH_CHIP_STM32L053XX=y -CONFIG_ARCH_CHIP_STM32L0=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=2796 -CONFIG_BUILTIN=y -CONFIG_DEBUG_FULLOPT=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_DEFAULT_TASK_STACKSIZE=1024 -CONFIG_DISABLE_ENVIRON=y -CONFIG_DISABLE_MOUNTPOINT=y -CONFIG_DISABLE_MQUEUE=y -CONFIG_DISABLE_POSIX_TIMERS=y -CONFIG_DISABLE_PSEUDOFS_OPERATIONS=y -CONFIG_EXAMPLES_HELLO=y -CONFIG_EXPERIMENTAL=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NUNGET_CHARS=0 -CONFIG_PTHREAD_MUTEX_UNSAFE=y -CONFIG_RAM_SIZE=8192 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=19 -CONFIG_START_MONTH=5 -CONFIG_START_YEAR=2013 -CONFIG_STDIO_DISABLE_BUFFERING=y -CONFIG_STM32F0L0G0_PWR=y -CONFIG_STM32F0L0G0_USART1=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f0l0g0/stm32l0538-disco/include/board.h b/boards/arm/stm32f0l0g0/stm32l0538-disco/include/board.h deleted file mode 100644 index 59333f53c8c9d..0000000000000 --- a/boards/arm/stm32f0l0g0/stm32l0538-disco/include/board.h +++ /dev/null @@ -1,195 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32f0l0g0/stm32l0538-disco/include/board.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __BOARDS_ARM_STM32F0L0G0_STM32L0538_DISCO_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32F0L0G0_STM32L0538_DISCO_INCLUDE_BOARD_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Clocking *****************************************************************/ - -/* HSI - Internal 16 MHz RC Oscillator - * LSI - 32 KHz RC - * HSE - 8 MHz from MCO output of ST-LINK - * LSE - 32.768 kHz - */ - -#define STM32_BOARD_XTAL 8000000ul - -#define STM32_HSEBYP_ENABLE -#define STM32_HSI_FREQUENCY 16000000ul -#define STM32_LSI_FREQUENCY 32000 /* Between 30kHz and 60kHz */ -#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL -#define STM32_LSE_FREQUENCY 32768 /* X2 on board */ - -/* PLL source is HSE/1, PLL multiplier is 8: - * PLL frequency is 8MHz (XTAL) x 8 = 64MHz - */ - -#define STM32_CFGR_PLLSRC RCC_CFGR_PLLSRC -#define STM32_CFGR_PLLXTPRE 0 -#define STM32_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx8 -#define STM32_PLL_FREQUENCY (8*STM32_BOARD_XTAL) - -/* Use the PLL and set the SYSCLK source to be the PLL/2 (32MHz) */ - -#define STM32_SYSCLK_SW RCC_CFGR_SW_PLL -#define STM32_SYSCLK_SWS RCC_CFGR_SWS_PLL -#define STM32_CFGR_PLLDIV RCC_CFGR_PLLDIV_2 -#define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY/2 - -/* AHB clock (HCLK) is SYSCLK (32MHz) */ - -#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK -#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY - -/* APB2 clock (PCLK2) is HCLK (32MHz) */ - -#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK -#define STM32_PCLK2_FREQUENCY STM32_HCLK_FREQUENCY -#define STM32_APB2_CLKIN (STM32_PCLK2_FREQUENCY) - -/* APB1 clock (PCLK1) is HCLK/2 (16MHz) */ - -#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd2 -#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/2) - -/* 48MHz clock configuration */ - -#if defined(CONFIG_STM32F0L0G0_USB) || defined(CONFIG_STM32F0L0G0_RNG) -# define STM32_USE_CLK48 1 -# define STM32_CLK48_SEL RCC_CCIPR_CLK48SEL_HSI48 -# define STM32_HSI48_SYNCSRC SYNCSRC_NONE -#endif - -/* TODO: timers */ - -/* LED definitions **********************************************************/ - -/* The STM32L0538-DISCO board has three LEDs. Two of these are controlled by - * logic on the board and are not available for software control: - * - * LD1 COM: LD1 default status is red. LD1 turns to green to indicate that - * communications are in progress between the PC and the - * ST-LINK/V2-1. - * LD3 PWR: red LED indicates that the board is powered. - * - * And one can be controlled by software: - * - * User LD2: green LED is a user LED connected to the I/O PA5 of the - * STM32L053C8T6. - * - * If CONFIG_ARCH_LEDS is not defined, then the user can control the LED in - * any way. The following definition is used to access the LED. - */ - -/* LED index values for use with board_userled() */ - -#define BOARD_LED1 0 /* User LD2 */ -#define BOARD_NLEDS 1 - -/* LED bits for use with board_userled_all() */ - -#define BOARD_LED1_BIT (1 << BOARD_LED1) - -/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the LED on board - * the STM32L0538-DISCO. The following definitions describe how NuttX - * controls the LED: - * - * SYMBOL Meaning LED1 state - * ------------------ ----------------------- ---------- - * LED_STARTED NuttX has been started OFF - * LED_HEAPALLOCATE Heap has been allocated OFF - * LED_IRQSENABLED Interrupts enabled OFF - * LED_STACKCREATED Idle stack created ON - * LED_INIRQ In an interrupt No change - * LED_SIGNAL In a signal handler No change - * LED_ASSERTION An assertion failed No change - * LED_PANIC The system has crashed Blinking - * LED_IDLE STM32 is in sleep mode Not used - */ - -#define LED_STARTED 0 -#define LED_HEAPALLOCATE 0 -#define LED_IRQSENABLED 0 -#define LED_STACKCREATED 1 -#define LED_INIRQ 2 -#define LED_SIGNAL 2 -#define LED_ASSERTION 2 -#define LED_PANIC 1 - -/* Button definitions *******************************************************/ - -/* The STM32L0538-DISCO supports two buttons; only one button is controllable - * by software: - * - * B1 USER: user button connected to the I/O PA0 of the STM32L053C8T6. - * B2 RESET: push button connected to NRST is used to RESET the - * STM32L053C8T6. - */ - -#define BUTTON_USER 0 -#define NUM_BUTTONS 1 - -#define BUTTON_USER_BIT (1 << BUTTON_USER) - -/* Alternate function pin selections ****************************************/ - -/* USART */ - -/* By default the USART1 is connected to STLINK Virtual COM Port: - * USART1_RX - PA10 - * USART1_TX - PA9 - */ - -#define GPIO_USART1_RX (GPIO_USART1_RX_1|GPIO_SPEED_HIGH) /* PA10 */ -#define GPIO_USART1_TX (GPIO_USART1_TX_1|GPIO_SPEED_HIGH) /* PA9 */ - -/* SPI1 - E-papper display: - * SPI1_MISO - not used - * SPI1_MOSI - PB5 - * SPI1_SCK - PB3 - */ - -#undef GPIO_SPI1_MISO /* Not used */ -#define GPIO_SPI1_MOSI (GPIO_SPI1_MOSI_3|GPIO_SPEED_MEDIUM) /* PB5 */ -#define GPIO_SPI1_SCK (GPIO_SPI1_SCK_2|GPIO_SPEED_MEDIUM) /* PB3 */ - -/* SPI2 - NFC connector: - * SPI2_MISO - PB14 - * SPI2_MOSI - PB15 - * SPI2_SCK - PB13 - */ - -#define GPIO_SPI2_MISO (GPIO_SPI2_MISO_1|GPIO_SPEED_MEDIUM) /* PB14 */ -#define GPIO_SPI2_MOSI (GPIO_SPI2_MOSI_1|GPIO_SPEED_MEDIUM) /* PB15 */ -#define GPIO_SPI2_SCK (GPIO_SPI2_SCK_3|GPIO_SPEED_MEDIUM) /* PB13 */ - -#endif /* __BOARDS_ARM_STM32F0L0G0_STM32L0538_DISCO_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32f0l0g0/stm32l0538-disco/scripts/Make.defs b/boards/arm/stm32f0l0g0/stm32l0538-disco/scripts/Make.defs deleted file mode 100644 index 5417678c0ce39..0000000000000 --- a/boards/arm/stm32f0l0g0/stm32l0538-disco/scripts/Make.defs +++ /dev/null @@ -1,43 +0,0 @@ -############################################################################ -# boards/arm/stm32f0l0g0/stm32l0538-disco/scripts/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/.config -include $(TOPDIR)/tools/Config.mk -include $(TOPDIR)/arch/arm/src/armv6-m/Toolchain.defs - -LDSCRIPT = ld.script -ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) - -ARCHWARNINGS = -Wall -Wstrict-prototypes -Wshadow -Wundef -ARCHWARNINGSXX = -Wall -Wshadow -Wundef -ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 - -CFLAGS := $(ARCHCFLAGS) $(ARCHWARNINGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) -CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHWARNINGSXX) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) -CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -AFLAGS := $(CFLAGS) -D__ASSEMBLY__ - -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections -LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32f0l0g0/stm32l0538-disco/scripts/ld.script b/boards/arm/stm32f0l0g0/stm32l0538-disco/scripts/ld.script deleted file mode 100644 index 3ab8df515ea8f..0000000000000 --- a/boards/arm/stm32f0l0g0/stm32l0538-disco/scripts/ld.script +++ /dev/null @@ -1,115 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32f0l0g0/stm32l0538-disco/scripts/ld.script - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* The STM32L0538-DISCO has 64Kb of FLASH beginning at address 0x0800:0000. - * 8Kb of SRAM and 6Kb of EEPROM - * - * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 - * where the code expects to begin execution by jumping to the entry point in - * the 0x0800:0000 address range. - */ - -MEMORY -{ - flash (rx) : ORIGIN = 0x08000000, LENGTH = 64K - sram (rwx) : ORIGIN = 0x20000000, LENGTH = 8K -} - -OUTPUT_ARCH(arm) -EXTERN(_vectors) -ENTRY(_stext) -SECTIONS -{ - .text : { - _stext = ABSOLUTE(.); - *(.vectors) - *(.text .text.*) - *(.fixup) - *(.gnu.warning) - *(.rodata .rodata.*) - *(.gnu.linkonce.t.*) - *(.glue_7) - *(.glue_7t) - *(.got) - *(.gcc_except_table) - *(.gnu.linkonce.r.*) - _etext = ABSOLUTE(.); - } > flash - - .init_section : ALIGN(4) { - _sinit = ABSOLUTE(.); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) - KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) - _einit = ABSOLUTE(.); - } > flash - - .ARM.extab : ALIGN(4) { - *(.ARM.extab*) - } > flash - - .ARM.exidx : ALIGN(4) { - __exidx_start = ABSOLUTE(.); - *(.ARM.exidx*) - __exidx_end = ABSOLUTE(.); - } > flash - - _eronly = ABSOLUTE(.); - - /* The RAM vector table (if present) should lie at the beginning of SRAM */ - - .ram_vectors : { - *(.ram_vectors) - } > sram - - .data : ALIGN(4) { - _sdata = ABSOLUTE(.); - *(.data .data.*) - *(.gnu.linkonce.d.*) - CONSTRUCTORS - . = ALIGN(4); - _edata = ABSOLUTE(.); - } > sram AT > flash - - .bss : ALIGN(4) { - _sbss = ABSOLUTE(.); - *(.bss .bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - . = ALIGN(4); - _ebss = ABSOLUTE(.); - } > sram - - /* Stabs debugging sections. */ - - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_info 0 : { *(.debug_info) } - .debug_line 0 : { *(.debug_line) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_aranges 0 : { *(.debug_aranges) } -} diff --git a/boards/arm/stm32f0l0g0/stm32l0538-disco/src/CMakeLists.txt b/boards/arm/stm32f0l0g0/stm32l0538-disco/src/CMakeLists.txt deleted file mode 100644 index 2d3a59a01db8e..0000000000000 --- a/boards/arm/stm32f0l0g0/stm32l0538-disco/src/CMakeLists.txt +++ /dev/null @@ -1,37 +0,0 @@ -# ############################################################################## -# boards/arm/stm32f0l0g0/stm32l0538-disco/src/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -set(SRCS stm32_boot.c stm32_bringup.c) - -if(CONFIG_ARCH_LEDS) - list(APPEND SRCS stm32_autoleds.c) -else() - list(APPEND SRCS stm32_userleds.c) -endif() - -if(CONFIG_ARCH_BUTTONS) - list(APPEND SRCS stm32_buttons.c) -endif() - -target_sources(board PRIVATE ${SRCS}) - -set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/ld.script") diff --git a/boards/arm/stm32f0l0g0/stm32l0538-disco/src/Make.defs b/boards/arm/stm32f0l0g0/stm32l0538-disco/src/Make.defs deleted file mode 100644 index 502d059a1057e..0000000000000 --- a/boards/arm/stm32f0l0g0/stm32l0538-disco/src/Make.defs +++ /dev/null @@ -1,39 +0,0 @@ -############################################################################ -# boards/arm/stm32f0l0g0/stm32l0538-disco/src/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/Make.defs - -CSRCS = stm32_boot.c stm32_bringup.c - -ifeq ($(CONFIG_ARCH_LEDS),y) -CSRCS += stm32_autoleds.c -else -CSRCS += stm32_userleds.c -endif - -ifeq ($(CONFIG_ARCH_BUTTONS),y) -CSRCS += stm32_buttons.c -endif - -DEPPATH += --dep-path board -VPATH += :board -CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32f0l0g0/stm32l0538-disco/src/stm32_autoleds.c b/boards/arm/stm32f0l0g0/stm32l0538-disco/src/stm32_autoleds.c deleted file mode 100644 index b7564b913121f..0000000000000 --- a/boards/arm/stm32f0l0g0/stm32l0538-disco/src/stm32_autoleds.c +++ /dev/null @@ -1,80 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32f0l0g0/stm32l0538-disco/src/stm32_autoleds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include - -#include "stm32_gpio.h" -#include "stm32l0538-disco.h" - -#include - -#ifdef CONFIG_ARCH_LEDS - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_autoled_initialize - ****************************************************************************/ - -void board_autoled_initialize(void) -{ - /* Configure LED1 GPIO for output */ - - stm32_configgpio(GPIO_LED1); -} - -/**************************************************************************** - * Name: board_autoled_on - ****************************************************************************/ - -void board_autoled_on(int led) -{ - if (led == BOARD_LED1) - { - stm32_gpiowrite(GPIO_LED1, true); - } -} - -/**************************************************************************** - * Name: board_autoled_off - ****************************************************************************/ - -void board_autoled_off(int led) -{ - if (led == BOARD_LED1) - { - stm32_gpiowrite(GPIO_LED1, false); - } -} - -#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32f0l0g0/stm32l0538-disco/src/stm32_boot.c b/boards/arm/stm32f0l0g0/stm32l0538-disco/src/stm32_boot.c deleted file mode 100644 index b760b793943a9..0000000000000 --- a/boards/arm/stm32f0l0g0/stm32l0538-disco/src/stm32_boot.c +++ /dev/null @@ -1,79 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32f0l0g0/stm32l0538-disco/src/stm32_boot.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include "stm32l0538-disco.h" - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_boardinitialize - * - * Description: - * All STM32 architectures must provide the following entry point. This - * entry point is called early in the initialization -- after all memory - * has been configured and mapped but before any devices have been - * initialized. - * - ****************************************************************************/ - -void stm32_boardinitialize(void) -{ -#ifdef CONFIG_ARCH_LEDS - /* Configure on-board LEDs if LED support has been selected. */ - - board_autoled_initialize(); -#endif -} - -/**************************************************************************** - * Name: board_late_initialize - * - * Description: - * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional - * initialization call will be performed in the boot-up sequence to a - * function called board_late_initialize(). board_late_initialize() will - * be called immediately after up_initialize() is called and just before - * the initial application is started. This additional initialization - * phase may be used, for example, to initialize board-specific device - * drivers. - * - ****************************************************************************/ - -#ifdef CONFIG_BOARD_LATE_INITIALIZE -void board_late_initialize(void) -{ - /* Perform board-specific initialization */ - - stm32_bringup(); -} -#endif diff --git a/boards/arm/stm32f0l0g0/stm32l0538-disco/src/stm32_bringup.c b/boards/arm/stm32f0l0g0/stm32l0538-disco/src/stm32_bringup.c deleted file mode 100644 index c4907ef7ac8c3..0000000000000 --- a/boards/arm/stm32f0l0g0/stm32l0538-disco/src/stm32_bringup.c +++ /dev/null @@ -1,84 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32f0l0g0/stm32l0538-disco/src/stm32_bringup.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include "stm32l0538-disco.h" - -#ifdef CONFIG_INPUT_BUTTONS -# include -#endif - -#ifdef CONFIG_USERLED -# include -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_bringup - * - * Description: - * Perform architecture-specific initialization - * - * CONFIG_BOARD_LATE_INITIALIZE=y : - * Called from board_late_initialize(). - * - ****************************************************************************/ - -int stm32_bringup(void) -{ - int ret; - -#ifdef CONFIG_INPUT_BUTTONS - /* Register the BUTTON driver */ - - ret = btn_lower_initialize("/dev/buttons"); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: btn_lower_initialize() failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_USERLED - /* Register the LED driver */ - - ret = userled_lower_initialize(LED_DRIVER_PATH); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: userled_lower_initialize() failed: %d\n", ret); - return ret; - } -#endif - - UNUSED(ret); - return OK; -} diff --git a/boards/arm/stm32f0l0g0/stm32l0538-disco/src/stm32_buttons.c b/boards/arm/stm32f0l0g0/stm32l0538-disco/src/stm32_buttons.c deleted file mode 100644 index f6cff70cb1942..0000000000000 --- a/boards/arm/stm32f0l0g0/stm32l0538-disco/src/stm32_buttons.c +++ /dev/null @@ -1,118 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32f0l0g0/stm32l0538-disco/src/stm32_buttons.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include "stm32_gpio.h" -#include "stm32l0538-disco.h" - -#include - -#ifdef CONFIG_ARCH_BUTTONS - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_button_initialize - * - * Description: - * board_button_initialize() must be called to initialize button resources. - * After that, board_buttons() may be called to collect the current state - * of all buttons or board_button_irq() may be called to register button - * interrupt handlers. - * - ****************************************************************************/ - -uint32_t board_button_initialize(void) -{ - /* Configure the single button as an input. NOTE that EXTI interrupts are - * also configured for the pin. - */ - - stm32_configgpio(GPIO_BTN_USER); - return NUM_BUTTONS; -} - -/**************************************************************************** - * Name: board_buttons - ****************************************************************************/ - -uint32_t board_buttons(void) -{ - /* Check that state of each USER button. A LOW value means that the key is - * pressed. - */ - - bool released = stm32_gpioread(GPIO_BTN_USER); - return !released; -} - -/**************************************************************************** - * Button support. - * - * Description: - * board_button_initialize() must be called to initialize button resources. - * After that, board_buttons() may be called to collect the current state - * of all buttons or board_button_irq() may be called to register button - * interrupt handlers. - * - * After board_button_initialize() has been called, board_buttons() may be - * called to collect the state of all buttons. board_buttons() returns an - * 32-bit bit set with each bit associated with a button. See the - * BUTTON_*_BIT definitions in board.h for the meaning of each bit. - * - * board_button_irq() may be called to register an interrupt handler that - * will be called when a button is depressed or released. The ID value is a - * button enumeration value that uniquely identifies a button resource. See - * the BUTTON_* definitions in board.h for the meaning of enumeration - * value. - * - ****************************************************************************/ - -#ifdef CONFIG_ARCH_IRQBUTTONS -int board_button_irq(int id, xcpt_t irqhandler, void *arg) -{ - int ret = -EINVAL; - - if (id == BUTTON_USER) - { - ret = stm32_gpiosetevent(GPIO_BTN_USER, true, true, true, - irqhandler, arg); - } - - return ret; -} -#endif -#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/stm32f1/cloudctrl/CMakeLists.txt b/boards/arm/stm32f1/cloudctrl/CMakeLists.txt new file mode 100644 index 0000000000000..63062e3011b14 --- /dev/null +++ b/boards/arm/stm32f1/cloudctrl/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32f1/cloudctrl/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/arm/stm32/cloudctrl/Kconfig b/boards/arm/stm32f1/cloudctrl/Kconfig similarity index 100% rename from boards/arm/stm32/cloudctrl/Kconfig rename to boards/arm/stm32f1/cloudctrl/Kconfig diff --git a/boards/arm/stm32f1/cloudctrl/configs/nsh/defconfig b/boards/arm/stm32f1/cloudctrl/configs/nsh/defconfig new file mode 100644 index 0000000000000..35a72832e26fc --- /dev/null +++ b/boards/arm/stm32f1/cloudctrl/configs/nsh/defconfig @@ -0,0 +1,79 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_SPI_CALLBACK is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="cloudctrl" +CONFIG_ARCH_BOARD_CLOUDCTRL=y +CONFIG_ARCH_CHIP="stm32f1" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F107VC=y +CONFIG_ARCH_CHIP_STM32F1=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=5483 +CONFIG_BUILTIN=y +CONFIG_ETH0_PHY_DM9161=y +CONFIG_FAT_LCNAMES=y +CONFIG_FAT_LFN=y +CONFIG_FS_FAT=y +CONFIG_HAVE_CXX=y +CONFIG_HOST_WINDOWS=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_MMCSD=y +CONFIG_MMCSD_SPICLOCK=12500000 +CONFIG_NET=y +CONFIG_NETDB_DNSCLIENT=y +CONFIG_NETDB_DNSSERVER_NOADDR=y +CONFIG_NETINIT_NOMAC=y +CONFIG_NETUTILS_TELNETD=y +CONFIG_NETUTILS_TFTPC=y +CONFIG_NETUTILS_WEBCLIENT=y +CONFIG_NET_ICMP_SOCKET=y +CONFIG_NET_MAX_LISTENPORTS=40 +CONFIG_NET_STATISTICS=y +CONFIG_NET_TCP=y +CONFIG_NET_TCP_PREALLOC_CONNS=40 +CONFIG_NET_UDP=y +CONFIG_NET_UDP_CHECKSUMS=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_MMCSDSPIPORTNO=1 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=65536 +CONFIG_RAM_START=0x20000000 +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_WAITPID=y +CONFIG_STM32_BKP=y +CONFIG_STM32_ETHMAC=y +CONFIG_STM32_ETH_REMAP=y +CONFIG_STM32_JTAG_FULL_ENABLE=y +CONFIG_STM32_PHYADDR=0 +CONFIG_STM32_PHYINIT=y +CONFIG_STM32_PHYSR=17 +CONFIG_STM32_PHYSR_100FD=0x8000 +CONFIG_STM32_PHYSR_100HD=0x4000 +CONFIG_STM32_PHYSR_10FD=0x2000 +CONFIG_STM32_PHYSR_10HD=0x1000 +CONFIG_STM32_PHYSR_ALTCONFIG=y +CONFIG_STM32_PHYSR_ALTMODE=0xf000 +CONFIG_STM32_PWR=y +CONFIG_STM32_RTC=y +CONFIG_STM32_SPI1=y +CONFIG_STM32_USART2=y +CONFIG_STM32_USART2_REMAP=y +CONFIG_SYSTEM_NSH=y +CONFIG_SYSTEM_PING=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART2_RXBUFSIZE=128 +CONFIG_USART2_SERIAL_CONSOLE=y +CONFIG_USART2_TXBUFSIZE=128 diff --git a/boards/arm/stm32f1/cloudctrl/include/board.h b/boards/arm/stm32f1/cloudctrl/include/board.h new file mode 100644 index 0000000000000..df0ae697667cd --- /dev/null +++ b/boards/arm/stm32f1/cloudctrl/include/board.h @@ -0,0 +1,409 @@ +/**************************************************************************** + * boards/arm/stm32f1/cloudctrl/include/board.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_STM32_CLOUDCTRL_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32_CLOUDCTRL_INCLUDE_BOARD_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#ifndef __ASSEMBLY__ +# include +#endif + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Clocking *****************************************************************/ + +/* HSI - 8 MHz RC factory-trimmed + * LSI - 40 KHz RC (30-60KHz, uncalibrated) + * HSE - On-board crystal frequency is 25MHz + * LSE - 32.768 kHz + */ + +#define STM32_BOARD_XTAL 25000000ul + +#define STM32_HSI_FREQUENCY 8000000ul +#define STM32_LSI_FREQUENCY 40000 +#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL +#define STM32_LSE_FREQUENCY 32768 + +/* PLL output is 72MHz */ + +#define STM32_PLL_PREDIV2 RCC_CFGR2_PREDIV2d5 /* 25MHz / 5 => 5MHz */ +#define STM32_PLL_PLL2MUL RCC_CFGR2_PLL2MULx8 /* 5MHz * 8 => 40MHz */ +#define STM32_PLL_PREDIV1 RCC_CFGR2_PREDIV1d5 /* 40MHz / 5 => 8MHz */ +#define STM32_PLL_PLLMUL RCC_CFGR_PLLMUL_CLKx9 /* 8MHz * 9 => 72Mhz */ +#define STM32_PLL_FREQUENCY (72000000) + +/* SYCLLK and HCLK are the PLL frequency */ + +#define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY +#define STM32_HCLK_FREQUENCY STM32_PLL_FREQUENCY + +/* APB2 clock (PCLK2) is HCLK (72MHz) */ + +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK +#define STM32_PCLK2_FREQUENCY STM32_HCLK_FREQUENCY +#define STM32_APB2_CLKIN (STM32_PCLK2_FREQUENCY) /* Timers 2-7, 12-14 */ + +/* APB2 timers 1 and 8 will receive PCLK2. */ + +#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) + +/* APB1 clock (PCLK1) is HCLK/2 (36MHz) */ + +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd2 +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/2) + +/* APB1 timers 2-7 will be twice PCLK1 */ + +#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) + +/* MCO output driven by PLL3. From above, we already have PLL3 input + * frequency as: + * + * STM32_PLL_PREDIV2 = 5, 25MHz / 5 => 5MHz + */ + +#if defined(CONFIG_STM32_MII_MCO) || defined(CONFIG_STM32_RMII_MCO) +# define BOARD_CFGR_MCO_SOURCE RCC_CFGR_PLL3CLK /* Source: PLL3 */ +# define STM32_PLL_PLL3MUL RCC_CFGR2_PLL3MULx10 /* MCO 5MHz * 10 = 50MHz */ +#endif + +/* LED definitions **********************************************************/ + +/* If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs in + * any way. The following definitions are used to access individual LEDs. + */ + +/* LED index values for use with board_userled() */ + +#define BOARD_LED1 0 +#define BOARD_LED2 1 +#define BOARD_LED3 2 +#define BOARD_LED4 3 +#define BOARD_NLEDS 4 + +/* LED bits for use with board_userled_all() */ + +#define BOARD_LED1_BIT (1 << BOARD_LED1) +#define BOARD_LED2_BIT (1 << BOARD_LED2) +#define BOARD_LED3_BIT (1 << BOARD_LED3) +#define BOARD_LED4_BIT (1 << BOARD_LED4) + +/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the 4 LEDs on + * board the STM3240G-EVAL. + * The following definitions describe how NuttX controls the LEDs: + */ + +#define LED_STARTED 0 /* LED1 */ +#define LED_HEAPALLOCATE 1 /* LED2 */ +#define LED_IRQSENABLED 2 /* LED1 + LED2 */ +#define LED_STACKCREATED 3 /* LED3 */ +#define LED_INIRQ 4 /* LED1 + LED3 */ +#define LED_SIGNAL 5 /* LED2 + LED3 */ +#define LED_ASSERTION 6 /* LED1 + LED2 + LED3 */ +#define LED_PANIC 7 /* N/C + N/C + N/C + LED4 */ + +/* Button definitions *******************************************************/ + +/* The STM3240G-EVAL supports three buttons: */ + +#define BUTTON_KEY1 0 /* Name printed on board */ +#define BUTTON_KEY2 1 +#define BUTTON_KEY3 2 +#define NUM_BUTTONS 3 + +#define BUTTON_USERKEY BUTTON_KEY1 /* Names in schematic */ +#define BUTTON_TAMPER BUTTON_KEY2 +#define BUTTON_WAKEUP BUTTON_KEY3 + +#define BUTTON_KEY1_BIT (1 << BUTTON_KEY1) +#define BUTTON_KEY2_BIT (1 << BUTTON_KEY2) +#define BUTTON_KEY3_BIT (1 << BUTTON_KEY3) + +#define BUTTON_USERKEY_BIT BUTTON_KEY1_BIT +#define BUTTON_TAMPER_BIT BUTTON_KEY2_BIT +#define BUTTON_WAKEUP_BIT BUTTON_KEY3_BIT + +/* Relays */ + +#define NUM_RELAYS 2 + +/* Pin selections ***********************************************************/ + +/* Ethernet + * + * -- ---- -------------- --------------------------------------------------- + * PN NAME SIGNAL NOTES + * -- ---- -------------- --------------------------------------------------- + * 24 PA1 MII_RX_CLK Ethernet PHY NOTE: Despite the MII labeling of + * RMII_REF_CLK Ethernet PHY these signals, the DM916AEP is + * 25 PA2 MII_MDIO Ethernet PHY actually configured to work in + * 48 PB11 MII_TX_EN Ethernet PHY RMII mode. + * 51 PB12 MII_TXD0 Ethernet PHY + * 52 PB13 MII_TXD1 Ethernet PHY + * 16 PC1 MII_MDC Ethernet PHY + * 34 PC5 MII_INT Ethernet PHY + * 55 PD8 MII_RX_DV Ethernet PHY. Requires CONFIG_STM32_ETH_REMAP + * 55 PD8 RMII_CRSDV Ethernet PHY. Requires CONFIG_STM32_ETH_REMAP + * 56 PD9 MII_RXD0 Ethernet PHY. Requires CONFIG_STM32_ETH_REMAP + * 57 PD10 MII_RXD1 Ethernet PHY. Requires CONFIG_STM32_ETH_REMAP + * + * The board desdign can support a 50MHz external clock to drive the PHY + * (U9). However, on my board, U9 is not present. + * + * 67 PA8 MCO DM9161AEP + */ + +#ifdef CONFIG_STM32_ETHMAC +# ifndef CONFIG_STM32_ETH_REMAP +# error "STM32 Ethernet requires CONFIG_STM32_ETH_REMAP" +# endif +# ifndef CONFIG_STM32_RMII +# error "STM32 Ethernet requires CONFIG_STM32_RMII" +# endif +# ifndef CONFIG_STM32_RMII_MCO +# error "STM32 Ethernet requires CONFIG_STM32_RMII_MCO" +# endif +#endif + +/* USB + * + * -- ---- -------------- --------------------------------------------------- + * PN NAME SIGNAL NOTES + * -- ---- -------------- --------------------------------------------------- + * 68 PA9 USB_VBUS MINI-USB-AB. JP3 + * 69 PA10 USB_ID MINI-USB-AB. JP5 + * 70 PA11 USB_DM MINI-USB-AB + * 71 PA12 USB_DP MINI-USB-AB + * 95 PB8 USB_PWR Drives USB VBUS + */ + +/* UARTS/USARTS + * + * -- ---- -------------- --------------------------------------------------- + * PN NAME SIGNAL NOTES + * -- ---- -------------- --------------------------------------------------- + * 68 PA9 USART1_TX MAX3232 to CN5. Requires CONFIG_STM32_USART1_REMAP + * 69 PA10 USART1_RX MAX3232 to CN5. Requires CONFIG_STM32_USART1_REMAP + * 86 PD5 USART2_TX MAX3232 to CN6. Requires CONFIG_STM32_USART2_REMAP + * 87 PD6 USART2_RX MAX3232 to CN6. Requires CONFIG_STM32_USART2_REMAP + * 86 PD5 485_TX Same as USART2_TX but goes to SP3485 + * 87 PD6 485_RX Save as USART2_RX but goes to SP3485 (see JP4) + */ + +#if defined(CONFIG_STM32_USART1) && !defined(CONFIG_STM32_USART1_REMAP) +# error "CONFIG_STM32_USART1 requires CONFIG_STM32_USART1_REMAP" +#endif + +#if defined(CONFIG_STM32_USART2) && !defined(CONFIG_STM32_USART2_REMAP) +# error "CONFIG_STM32_USART2 requires CONFIG_STM32_USART2_REMAP" +#endif + +/* SPI + * + * -- ---- -------------- --------------------------------------------------- + * PN NAME SIGNAL NOTES + * -- ---- -------------- --------------------------------------------------- + * 30 PA5 SPI1_SCK To the SD card, SPI FLASH. + * Requires !CONFIG_STM32_SPI1_REMAP + * 31 PA6 SPI1_MISO To the SD card, SPI FLASH. + * Requires !CONFIG_STM32_SPI1_REMAP + * 32 PA7 SPI1_MOSI To the SD card, SPI FLASH. + * Requires !CONFIG_STM32_SPI1_REMAP + * 78 PC10 SPI3_SCK To TFT LCD (CN13), + * the NRF24L01 2.4G wireless module. + * Requires CONFIG_STM32_SPI3_REMAP. + * 79 PC11 SPI3_MISO To TFT LCD (CN13), + * the NRF24L01 2.4G wireless module. + * Requires CONFIG_STM32_SPI3_REMAP. + * 80 PC12 SPI3_MOSI To TFT LCD (CN13), + * the NRF24L01 2.4G wireless module. + * Requires CONFIG_STM32_SPI3_REMAP. + */ + +#if defined(CONFIG_STM32_SPI1) && defined(CONFIG_STM32_SPI1_REMAP) +# error "CONFIG_STM32_SPI1 must not have CONFIG_STM32_SPI1_REMAP" +#endif + +#if defined(CONFIG_STM32_SPI3) && !defined(CONFIG_STM32_SPI3_REMAP) +# error "CONFIG_STM32_SPI3 requires CONFIG_STM32_SPI3_REMAP" +#endif + +/* DAC + * + * -- ---- -------------- --------------------------------------------------- + * PN NAME SIGNAL NOTES + * -- ---- -------------- --------------------------------------------------- + * 29 PA4 DAC_OUT1 To CON5(CN14) + * 30 PA5 DAC_OUT2 To CON5(CN14). JP10 + */ + +/* ADC + * + * -- ---- -------------- --------------------------------------------------- + * PN NAME SIGNAL NOTES + * -- ---- -------------- --------------------------------------------------- + * 35 PB0 ADC_IN1 GPIO_ADC12_IN8. To CON5(CN14) + * 36 PB1 ADC_IN2 GPIO_ADC12_IN9. To CON5(CN14) + * 15 PC0 POTENTIO_METER GPIO_ADC12_IN10 + */ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_lcdclear + * + * Description: + * This is a non-standard LCD interface just for the Shenzhou board. + * Because of the various rotations, clearing the display in the normal + * way by writing a sequences of runs that covers the entire display can + * be very slow. Here the display is cleared by simply setting all GRAM + * memory to the specified color. + * + ****************************************************************************/ + +void stm32_lcdclear(uint16_t color); + +/**************************************************************************** + * Relay control functions + * + * Description: + * Non-standard functions for relay control from the Shenzhou board. + * + * NOTE: These must match the prototypes in include/nuttx/arch.h + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_RELAYS +void up_relaysinit(void); +void relays_setstat(int relays, bool stat); +bool relays_getstat(int relays); +void relays_setstats(uint32_t relays_stat); +uint32_t relays_getstats(void); +void relays_onoff(int relays, uint32_t mdelay); +void relays_onoffs(uint32_t relays_stat, uint32_t mdelay); +void relays_resetmode(int relays); +void relays_powermode(int relays); +void relays_resetmodes(uint32_t relays_stat); +void relays_powermodes(uint32_t relays_stat); +#endif + +/**************************************************************************** + * Chip ID functions + * + * Description: + * Non-standard functions to obtain chip ID information. + * + ****************************************************************************/ + +const char *stm32_getchipid(void); +const char *stm32_getchipid_string(void); + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ + +/* Alternate function pin selections (auto-aliased for new pinmap) */ + +/* USART2 */ + +#define GPIO_USART2_TX GPIO_ADJUST_MODE(GPIO_USART2_TX_0, GPIO_MODE_50MHz) +#define GPIO_USART2_RX GPIO_USART2_RX_0 +#define GPIO_USART2_CTS GPIO_USART2_CTS_0 +#define GPIO_USART2_RTS GPIO_ADJUST_MODE(GPIO_USART2_RTS_0, GPIO_MODE_50MHz) +#define GPIO_USART2_CK GPIO_ADJUST_MODE(GPIO_USART2_CK_0, GPIO_MODE_50MHz) + +/* SPI1 */ + +#define GPIO_SPI1_NSS GPIO_ADJUST_MODE(GPIO_SPI1_NSS_0, GPIO_MODE_50MHz) +#define GPIO_SPI1_SCK GPIO_ADJUST_MODE(GPIO_SPI1_SCK_0, GPIO_MODE_50MHz) +#define GPIO_SPI1_MISO GPIO_ADJUST_MODE(GPIO_SPI1_MISO_0, GPIO_MODE_50MHz) +#define GPIO_SPI1_MOSI GPIO_ADJUST_MODE(GPIO_SPI1_MOSI_0, GPIO_MODE_50MHz) + +/* MCO */ + +#define GPIO_MCO GPIO_ADJUST_MODE(GPIO_MCO_0, GPIO_MODE_50MHz) + +/* Ethernet (MII/RMII) */ + +#define GPIO_ETH_MDC GPIO_ADJUST_MODE(GPIO_ETH_MDC_0, GPIO_MODE_50MHz) +#define GPIO_ETH_MDIO GPIO_ADJUST_MODE(GPIO_ETH_MDIO_0, GPIO_MODE_50MHz) +#define GPIO_ETH_MII_COL GPIO_ETH_MII_COL_0 +#define GPIO_ETH_MII_CRS GPIO_ETH_MII_CRS_0 +#define GPIO_ETH_MII_RX_CLK GPIO_ETH_MII_RX_CLK_0 +#define GPIO_ETH_MII_RXD0 GPIO_ETH_MII_RXD0_0 +#define GPIO_ETH_MII_RXD1 GPIO_ETH_MII_RXD1_0 +#define GPIO_ETH_MII_RXD2 GPIO_ETH_MII_RXD2_0 +#define GPIO_ETH_MII_RXD3 GPIO_ETH_MII_RXD3_0 +#define GPIO_ETH_MII_RX_DV GPIO_ETH_MII_RX_DV_0 +#define GPIO_ETH_MII_RX_ER GPIO_ETH_MII_RX_ER_0 +#define GPIO_ETH_MII_TX_CLK GPIO_ETH_MII_TX_CLK_0 +#define GPIO_ETH_MII_TXD0 GPIO_ADJUST_MODE(GPIO_ETH_MII_TXD0_0, GPIO_MODE_50MHz) +#define GPIO_ETH_MII_TXD1 GPIO_ADJUST_MODE(GPIO_ETH_MII_TXD1_0, GPIO_MODE_50MHz) +#define GPIO_ETH_MII_TXD2 GPIO_ADJUST_MODE(GPIO_ETH_MII_TXD2_0, GPIO_MODE_50MHz) +#define GPIO_ETH_MII_TXD3 GPIO_ADJUST_MODE(GPIO_ETH_MII_TXD3_0, GPIO_MODE_50MHz) +#define GPIO_ETH_MII_TX_EN GPIO_ADJUST_MODE(GPIO_ETH_MII_TX_EN_0, GPIO_MODE_50MHz) +#define GPIO_ETH_RMII_CRS_DV GPIO_ETH_RMII_CRS_DV_0 +#define GPIO_ETH_RMII_REF_CLK GPIO_ETH_RMII_REF_CLK_0 +#define GPIO_ETH_RMII_RXD0 GPIO_ETH_RMII_RXD0_0 +#define GPIO_ETH_RMII_RXD1 GPIO_ETH_RMII_RXD1_0 +#define GPIO_ETH_RMII_TXD0 GPIO_ADJUST_MODE(GPIO_ETH_RMII_TXD0_0, GPIO_MODE_50MHz) +#define GPIO_ETH_RMII_TXD1 GPIO_ADJUST_MODE(GPIO_ETH_RMII_TXD1_0, GPIO_MODE_50MHz) +#define GPIO_ETH_RMII_TX_EN GPIO_ADJUST_MODE(GPIO_ETH_RMII_TX_EN_0, GPIO_MODE_50MHz) + +#endif /* __BOARDS_ARM_STM32_CLOUDCTRL_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32f1/cloudctrl/scripts/Make.defs b/boards/arm/stm32f1/cloudctrl/scripts/Make.defs new file mode 100644 index 0000000000000..806f4f368af06 --- /dev/null +++ b/boards/arm/stm32f1/cloudctrl/scripts/Make.defs @@ -0,0 +1,48 @@ +############################################################################ +# boards/arm/stm32f1/cloudctrl/scripts/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/.config +include $(TOPDIR)/tools/Config.mk +include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs + +# Pick the linker script + +ifeq ($(CONFIG_STM32_DFU),y) + LDSCRIPT = cloudctrl-dfu.ld +else + LDSCRIPT = cloudctrl.ld +endif + +ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) + +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-gotoff.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32/cloudctrl/scripts/cloudctrl-dfu.ld b/boards/arm/stm32f1/cloudctrl/scripts/cloudctrl-dfu.ld similarity index 98% rename from boards/arm/stm32/cloudctrl/scripts/cloudctrl-dfu.ld rename to boards/arm/stm32f1/cloudctrl/scripts/cloudctrl-dfu.ld index f65e582ac706f..962101f605053 100644 --- a/boards/arm/stm32/cloudctrl/scripts/cloudctrl-dfu.ld +++ b/boards/arm/stm32f1/cloudctrl/scripts/cloudctrl-dfu.ld @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/cloudctrl/scripts/cloudctrl-dfu.ld + * boards/arm/stm32f1/cloudctrl/scripts/cloudctrl-dfu.ld * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/cloudctrl/scripts/cloudctrl.ld b/boards/arm/stm32f1/cloudctrl/scripts/cloudctrl.ld similarity index 98% rename from boards/arm/stm32/cloudctrl/scripts/cloudctrl.ld rename to boards/arm/stm32f1/cloudctrl/scripts/cloudctrl.ld index 1d6e63c1ec9ce..edbb31f7bf732 100644 --- a/boards/arm/stm32/cloudctrl/scripts/cloudctrl.ld +++ b/boards/arm/stm32f1/cloudctrl/scripts/cloudctrl.ld @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/cloudctrl/scripts/cloudctrl.ld + * boards/arm/stm32f1/cloudctrl/scripts/cloudctrl.ld * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f1/cloudctrl/src/CMakeLists.txt b/boards/arm/stm32f1/cloudctrl/src/CMakeLists.txt new file mode 100644 index 0000000000000..323760288c281 --- /dev/null +++ b/boards/arm/stm32f1/cloudctrl/src/CMakeLists.txt @@ -0,0 +1,67 @@ +# ############################################################################## +# boards/arm/stm32f1/cloudctrl/src/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(SRCS stm32_boot.c stm32_spi.c stm32_chipid.c) + +if(CONFIG_ARCH_LEDS) + list(APPEND SRCS stm32_autoleds.c) +else() + list(APPEND SRCS stm32_userleds.c) +endif() + +if(CONFIG_ARCH_BUTTONS) + list(APPEND SRCS stm32_buttons.c) +endif() + +if(CONFIG_ARCH_RELAYS) + list(APPEND SRCS stm32_relays.c) +endif() + +if(CONFIG_STM32_OTGFS) + list(APPEND SRCS stm32_usb.c) +endif() + +if(CONFIG_MTD_W25) + list(APPEND SRCS stm32_w25.c) +endif() + +if(CONFIG_USBMSC) + list(APPEND SRCS stm32_usbmsc.c) +endif() + +if(CONFIG_ADC) + list(APPEND SRCS stm32_adc.c) +endif() + +if(CONFIG_STM32_PHYINIT) + list(APPEND SRCS stm32_phyinit.c) +endif() + +target_sources(board PRIVATE ${SRCS}) + +if(CONFIG_STM32_DFU) + set_property(GLOBAL PROPERTY LD_SCRIPT + "${NUTTX_BOARD_DIR}/scripts/cloudctrl-dfu.ld") +else() + set_property(GLOBAL PROPERTY LD_SCRIPT + "${NUTTX_BOARD_DIR}/scripts/cloudctrl.ld") +endif() diff --git a/boards/arm/stm32f1/cloudctrl/src/Make.defs b/boards/arm/stm32f1/cloudctrl/src/Make.defs new file mode 100644 index 0000000000000..acb393d7f7e6c --- /dev/null +++ b/boards/arm/stm32f1/cloudctrl/src/Make.defs @@ -0,0 +1,63 @@ +############################################################################ +# boards/arm/stm32f1/cloudctrl/src/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +CSRCS = stm32_boot.c stm32_spi.c stm32_chipid.c + +ifeq ($(CONFIG_ARCH_LEDS),y) +CSRCS += stm32_autoleds.c +else +CSRCS += stm32_userleds.c +endif + +ifeq ($(CONFIG_ARCH_BUTTONS),y) +CSRCS += stm32_buttons.c +endif + +ifeq ($(CONFIG_ARCH_RELAYS),y) +CSRCS += stm32_relays.c +endif + +ifeq ($(CONFIG_STM32_OTGFS),y) +CSRCS += stm32_usb.c +endif + +ifeq ($(CONFIG_MTD_W25),y) +CSRCS += stm32_w25.c +endif + +ifeq ($(CONFIG_USBMSC),y) +CSRCS += stm32_usbmsc.c +endif + +ifeq ($(CONFIG_ADC),y) +CSRCS += stm32_adc.c +endif + +ifeq ($(CONFIG_STM32_PHYINIT),y) +CSRCS += stm32_phyinit.c +endif + +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/cloudctrl/src/cloudctrl.h b/boards/arm/stm32f1/cloudctrl/src/cloudctrl.h similarity index 99% rename from boards/arm/stm32/cloudctrl/src/cloudctrl.h rename to boards/arm/stm32f1/cloudctrl/src/cloudctrl.h index 58d98fabb4c98..00d0411160c75 100644 --- a/boards/arm/stm32/cloudctrl/src/cloudctrl.h +++ b/boards/arm/stm32f1/cloudctrl/src/cloudctrl.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/cloudctrl/src/cloudctrl.h + * boards/arm/stm32f1/cloudctrl/src/cloudctrl.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f1/cloudctrl/src/stm32_adc.c b/boards/arm/stm32f1/cloudctrl/src/stm32_adc.c new file mode 100644 index 0000000000000..dff3cb52e9833 --- /dev/null +++ b/boards/arm/stm32f1/cloudctrl/src/stm32_adc.c @@ -0,0 +1,164 @@ +/**************************************************************************** + * boards/arm/stm32f1/cloudctrl/src/stm32_adc.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32_pwm.h" +#include "cloudctrl.h" + +#ifdef CONFIG_ADC + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* Up to 3 ADC interfaces are supported */ + +#if STM32_NADC < 3 +# undef CONFIG_STM32_ADC3 +#endif + +#if STM32_NADC < 2 +# undef CONFIG_STM32_ADC2 +#endif + +#if STM32_NADC < 1 +# undef CONFIG_STM32_ADC1 +#endif + +#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) || defined(CONFIG_STM32_ADC3) +#ifndef CONFIG_STM32_ADC1 +# warning "Channel information only available for ADC1" +#endif + +/* The number of ADC channels in the conversion list */ + +#define ADC1_NCHANNELS 1 + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* Identifying number of each ADC channel. The only internal signal for ADC + * testing is the potentiometer input: + * + * ADC1_IN10(PC0) Potentiometer + * + * External signals are also available on CON5 CN14: + * + * ADC_IN8 (PB0) CON5 CN14 Pin2 + * ADC_IN9 (PB1) CON5 CN14 Pin1 + */ + +#ifdef CONFIG_STM32_ADC1 +static const uint8_t g_chanlist[ADC1_NCHANNELS] = +{ + 10 /* {10, 8, 9}; */ +}; + +/* Configurations of pins used by each ADC channel */ + +static const uint32_t g_pinlist[ADC1_NCHANNELS] = +{ + GPIO_ADC12_IN10 +}; + +/* {GPIO_ADC12_IN10, GPIO_ADC12_IN8, GPIO_ADC12_IN9}; */ +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_adc_setup + * + * Description: + * Initialize ADC and register the ADC driver. + * + ****************************************************************************/ + +int stm32_adc_setup(void) +{ +#ifdef CONFIG_STM32_ADC1 + static bool initialized = false; + struct adc_dev_s *adc; + int ret; + int i; + + /* Check if we have already initialized */ + + if (!initialized) + { + /* Configure the pins as analog inputs for the selected channels */ + + for (i = 0; i < ADC1_NCHANNELS; i++) + { + stm32_configgpio(g_pinlist[i]); + } + + /* Call stm32_adcinitialize() to get an instance of the ADC interface */ + + adc = stm32_adcinitialize(1, g_chanlist, ADC1_NCHANNELS); + if (adc == NULL) + { + aerr("ERROR: Failed to get ADC interface\n"); + return -ENODEV; + } + + /* Register the ADC driver at "/dev/adc0" */ + + ret = adc_register("/dev/adc0", adc); + if (ret < 0) + { + aerr("ERROR: adc_register failed: %d\n", ret); + return ret; + } + + /* Now we are initialized */ + + initialized = true; + } + + return OK; +#else + return -ENOSYS; +#endif +} + +#endif /* CONFIG_STM32_ADC1 || CONFIG_STM32_ADC2 || CONFIG_STM32_ADC3 */ +#endif /* CONFIG_ADC */ diff --git a/boards/arm/stm32f1/cloudctrl/src/stm32_autoleds.c b/boards/arm/stm32f1/cloudctrl/src/stm32_autoleds.c new file mode 100644 index 0000000000000..ba9fe2732c09f --- /dev/null +++ b/boards/arm/stm32f1/cloudctrl/src/stm32_autoleds.c @@ -0,0 +1,376 @@ +/**************************************************************************** + * boards/arm/stm32f1/cloudctrl/src/stm32_autoleds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32.h" +#include "cloudctrl.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* The following definitions map the encoded LED setting to GPIO settings */ + +#define CLOUDCTRL_LED1 (1 << 0) +#define CLOUDCTRL_LED2 (1 << 1) +#define CLOUDCTRL_LED3 (1 << 2) +#define CLOUDCTRL_LED4 (1 << 3) + +#define ON_SETBITS_SHIFT (0) +#define ON_CLRBITS_SHIFT (4) +#define OFF_SETBITS_SHIFT (8) +#define OFF_CLRBITS_SHIFT (12) + +#define ON_BITS(v) ((v) & 0xff) +#define OFF_BITS(v) (((v) >> 8) & 0x0ff) +#define SETBITS(b) ((b) & 0x0f) +#define CLRBITS(b) (((b) >> 4) & 0x0f) + +#define ON_SETBITS(v) (SETBITS(ON_BITS(v)) +#define ON_CLRBITS(v) (CLRBITS(ON_BITS(v)) +#define OFF_SETBITS(v) (SETBITS(OFF_BITS(v)) +#define OFF_CLRBITS(v) (CLRBITS(OFF_BITS(v)) + +#define LED_STARTED_ON_SETBITS ((CLOUDCTRL_LED1) << ON_SETBITS_SHIFT) +#define LED_STARTED_ON_CLRBITS ((CLOUDCTRL_LED2|CLOUDCTRL_LED3|CLOUDCTRL_LED4) << ON_CLRBITS_SHIFT) +#define LED_STARTED_OFF_SETBITS (0 << OFF_SETBITS_SHIFT) +#define LED_STARTED_OFF_CLRBITS ((CLOUDCTRL_LED1|CLOUDCTRL_LED2|CLOUDCTRL_LED3|CLOUDCTRL_LED4) << OFF_CLRBITS_SHIFT) + +#define LED_HEAPALLOCATE_ON_SETBITS ((CLOUDCTRL_LED2) << ON_SETBITS_SHIFT) +#define LED_HEAPALLOCATE_ON_CLRBITS ((CLOUDCTRL_LED1|CLOUDCTRL_LED3|CLOUDCTRL_LED4) << ON_CLRBITS_SHIFT) +#define LED_HEAPALLOCATE_OFF_SETBITS ((CLOUDCTRL_LED1) << OFF_SETBITS_SHIFT) +#define LED_HEAPALLOCATE_OFF_CLRBITS ((CLOUDCTRL_LED2|CLOUDCTRL_LED3|CLOUDCTRL_LED4) << OFF_CLRBITS_SHIFT) + +#define LED_IRQSENABLED_ON_SETBITS ((CLOUDCTRL_LED1|CLOUDCTRL_LED2) << ON_SETBITS_SHIFT) +#define LED_IRQSENABLED_ON_CLRBITS ((CLOUDCTRL_LED3|CLOUDCTRL_LED4) << ON_CLRBITS_SHIFT) +#define LED_IRQSENABLED_OFF_SETBITS ((CLOUDCTRL_LED2) << OFF_SETBITS_SHIFT) +#define LED_IRQSENABLED_OFF_CLRBITS ((CLOUDCTRL_LED1|CLOUDCTRL_LED3|CLOUDCTRL_LED4) << OFF_CLRBITS_SHIFT) + +#define LED_STACKCREATED_ON_SETBITS ((CLOUDCTRL_LED3) << ON_SETBITS_SHIFT) +#define LED_STACKCREATED_ON_CLRBITS ((CLOUDCTRL_LED1|CLOUDCTRL_LED2|CLOUDCTRL_LED4) << ON_CLRBITS_SHIFT) +#define LED_STACKCREATED_OFF_SETBITS ((CLOUDCTRL_LED1|CLOUDCTRL_LED2) << OFF_SETBITS_SHIFT) +#define LED_STACKCREATED_OFF_CLRBITS ((CLOUDCTRL_LED3|CLOUDCTRL_LED4) << OFF_CLRBITS_SHIFT) + +#define LED_INIRQ_ON_SETBITS ((CLOUDCTRL_LED1) << ON_SETBITS_SHIFT) +#define LED_INIRQ_ON_CLRBITS ((0) << ON_CLRBITS_SHIFT) +#define LED_INIRQ_OFF_SETBITS ((0) << OFF_SETBITS_SHIFT) +#define LED_INIRQ_OFF_CLRBITS ((CLOUDCTRL_LED1) << OFF_CLRBITS_SHIFT) + +#define LED_SIGNAL_ON_SETBITS ((CLOUDCTRL_LED2) << ON_SETBITS_SHIFT) +#define LED_SIGNAL_ON_CLRBITS ((0) << ON_CLRBITS_SHIFT) +#define LED_SIGNAL_OFF_SETBITS ((0) << OFF_SETBITS_SHIFT) +#define LED_SIGNAL_OFF_CLRBITS ((CLOUDCTRL_LED2) << OFF_CLRBITS_SHIFT) + +#define LED_ASSERTION_ON_SETBITS ((CLOUDCTRL_LED3) << ON_SETBITS_SHIFT) +#define LED_ASSERTION_ON_CLRBITS ((0) << ON_CLRBITS_SHIFT) +#define LED_ASSERTION_OFF_SETBITS ((0) << OFF_SETBITS_SHIFT) +#define LED_ASSERTION_OFF_CLRBITS ((CLOUDCTRL_LED3) << OFF_CLRBITS_SHIFT) + +#define LED_PANIC_ON_SETBITS ((CLOUDCTRL_LED3) << ON_SETBITS_SHIFT) +#define LED_PANIC_ON_CLRBITS ((0) << ON_CLRBITS_SHIFT) +#define LED_PANIC_OFF_SETBITS ((0) << OFF_SETBITS_SHIFT) +#define LED_PANIC_OFF_CLRBITS ((CLOUDCTRL_LED3) << OFF_CLRBITS_SHIFT) + +/**************************************************************************** + * Private Function Protototypes + ****************************************************************************/ + +/* LED State Controls */ + +static inline void led_clrbits(unsigned int clrbits); +static inline void led_setbits(unsigned int setbits); +static void led_setonoff(unsigned int bits); + +/* LED Power Management */ + +#ifdef CONFIG_PM +static void led_pm_notify(struct pm_callback_s *cb, int domain, + enum pm_state_e pmstate); +static int led_pm_prepare(struct pm_callback_s *cb, int domain, + enum pm_state_e pmstate); +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static const uint16_t g_ledbits[8] = +{ + (LED_STARTED_ON_SETBITS | LED_STARTED_ON_CLRBITS | + LED_STARTED_OFF_SETBITS | LED_STARTED_OFF_CLRBITS), + + (LED_HEAPALLOCATE_ON_SETBITS | LED_HEAPALLOCATE_ON_CLRBITS | + LED_HEAPALLOCATE_OFF_SETBITS | LED_HEAPALLOCATE_OFF_CLRBITS), + + (LED_IRQSENABLED_ON_SETBITS | LED_IRQSENABLED_ON_CLRBITS | + LED_IRQSENABLED_OFF_SETBITS | LED_IRQSENABLED_OFF_CLRBITS), + + (LED_STACKCREATED_ON_SETBITS | LED_STACKCREATED_ON_CLRBITS | + LED_STACKCREATED_OFF_SETBITS | LED_STACKCREATED_OFF_CLRBITS), + + (LED_INIRQ_ON_SETBITS | LED_INIRQ_ON_CLRBITS | + LED_INIRQ_OFF_SETBITS | LED_INIRQ_OFF_CLRBITS), + + (LED_SIGNAL_ON_SETBITS | LED_SIGNAL_ON_CLRBITS | + LED_SIGNAL_OFF_SETBITS | LED_SIGNAL_OFF_CLRBITS), + + (LED_ASSERTION_ON_SETBITS | LED_ASSERTION_ON_CLRBITS | + LED_ASSERTION_OFF_SETBITS | LED_ASSERTION_OFF_CLRBITS), + + (LED_PANIC_ON_SETBITS | LED_PANIC_ON_CLRBITS | + LED_PANIC_OFF_SETBITS | LED_PANIC_OFF_CLRBITS) +}; + +#ifdef CONFIG_PM +static struct pm_callback_s g_ledscb = +{ + .notify = led_pm_notify, + .prepare = led_pm_prepare, +}; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: led_clrbits + * + * Description: + * Clear all LEDs to the bit encoded state + * + ****************************************************************************/ + +static inline void led_clrbits(unsigned int clrbits) +{ + /* All LEDs are pulled up and, hence, active low */ + + if ((clrbits & CLOUDCTRL_LED1) != 0) + { + stm32_gpiowrite(GPIO_LED1, true); + } + + if ((clrbits & CLOUDCTRL_LED2) != 0) + { + stm32_gpiowrite(GPIO_LED2, true); + } + + if ((clrbits & CLOUDCTRL_LED3) != 0) + { + stm32_gpiowrite(GPIO_LED3, true); + } + + if ((clrbits & CLOUDCTRL_LED4) != 0) + { + stm32_gpiowrite(GPIO_LED4, true); + } +} + +/**************************************************************************** + * Name: led_setbits + * + * Description: + * Set all LEDs to the bit encoded state + * + ****************************************************************************/ + +static inline void led_setbits(unsigned int setbits) +{ + /* All LEDs are pulled up and, hence, active low */ + + if ((setbits & CLOUDCTRL_LED1) != 0) + { + stm32_gpiowrite(GPIO_LED1, false); + } + + if ((setbits & CLOUDCTRL_LED2) != 0) + { + stm32_gpiowrite(GPIO_LED2, false); + } + + if ((setbits & CLOUDCTRL_LED3) != 0) + { + stm32_gpiowrite(GPIO_LED3, false); + } + + if ((setbits & CLOUDCTRL_LED4) != 0) + { + stm32_gpiowrite(GPIO_LED4, false); + } +} + +/**************************************************************************** + * Name: led_setonoff + * + * Description: + * Set/clear all LEDs to the bit encoded state + * + ****************************************************************************/ + +static void led_setonoff(unsigned int bits) +{ + led_clrbits(CLRBITS(bits)); + led_setbits(SETBITS(bits)); +} + +/**************************************************************************** + * Name: led_pm_notify + * + * Description: + * Notify the driver of new power state. This callback is called after + * all drivers have had the opportunity to prepare for the new power state. + * + ****************************************************************************/ + +#ifdef CONFIG_PM +static void led_pm_notify(struct pm_callback_s *cb, int domain, + enum pm_state_e pmstate) +{ + switch (pmstate) + { + case PM_NORMAL: + { + /* Restore normal LEDs operation */ + } + break; + + case PM_IDLE: + { + /* Entering IDLE mode - Turn leds off */ + } + break; + + case PM_STANDBY: + { + /* Entering STANDBY mode - Logic for PM_STANDBY goes here */ + } + break; + + case PM_SLEEP: + { + /* Entering SLEEP mode - Logic for PM_SLEEP goes here */ + } + break; + + default: + { + /* Should not get here */ + } + break; + } +} +#endif + +/**************************************************************************** + * Name: led_pm_prepare + * + * Description: + * Request the driver to prepare for a new power state. This is a warning + * that the system is about to enter into a new power state. The driver + * should begin whatever operations that may be required to enter power + * state. The driver may abort the state change mode by returning a + * non-zero value from the callback function. + * + ****************************************************************************/ + +#ifdef CONFIG_PM +static int led_pm_prepare(struct pm_callback_s *cb, int domain, + enum pm_state_e pmstate) +{ + /* No preparation to change power modes is required by the LEDs driver. + * We always accept the state change by returning OK. + */ + + return OK; +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_autoled_initialize + ****************************************************************************/ + +#ifdef CONFIG_ARCH_LEDS +void board_autoled_initialize(void) +{ + /* Configure LED1-4 GPIOs for output */ + + stm32_configgpio(GPIO_LED1); + stm32_configgpio(GPIO_LED2); + stm32_configgpio(GPIO_LED3); + stm32_configgpio(GPIO_LED4); +} + +/**************************************************************************** + * Name: board_autoled_on + ****************************************************************************/ + +void board_autoled_on(int led) +{ + led_setonoff(ON_BITS(g_ledbits[led])); +} + +/**************************************************************************** + * Name: board_autoled_off + ****************************************************************************/ + +void board_autoled_off(int led) +{ + led_setonoff(OFF_BITS(g_ledbits[led])); +} + +/**************************************************************************** + * Name: up_ledpminitialize + ****************************************************************************/ + +#ifdef CONFIG_PM +void up_ledpminitialize(void) +{ + /* Register to receive power management callbacks */ + + int ret = pm_register(&g_ledscb); + if (ret != OK) + { + board_autoled_on(LED_ASSERTION); + } +} +#endif /* CONFIG_PM */ + +#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32f1/cloudctrl/src/stm32_boot.c b/boards/arm/stm32f1/cloudctrl/src/stm32_boot.c new file mode 100644 index 0000000000000..20d17470a6d55 --- /dev/null +++ b/boards/arm/stm32f1/cloudctrl/src/stm32_boot.c @@ -0,0 +1,200 @@ +/**************************************************************************** + * boards/arm/stm32f1/cloudctrl/src/stm32_boot.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include +#include +#include +#include + +#include +#include + +#include "arm_internal.h" +#include "stm32.h" +#include "cloudctrl.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* Assume that we support everything until convinced otherwise */ + +#define HAVE_USBDEV 1 +#define HAVE_USBHOST 1 +#define HAVE_W25 1 + +/* Can't support the W25 device if it SPI1 or W25 support is not enabled */ + +#if !defined(CONFIG_STM32_SPI1) || !defined(CONFIG_MTD_W25) +# undef HAVE_W25 +#endif + +/* Can't support W25 features if mountpoints are disabled */ + +#ifdef CONFIG_DISABLE_MOUNTPOINT +# undef HAVE_W25 +#endif + +/* Default W25 minor number */ + +#if defined(HAVE_W25) && !defined(CONFIG_NSH_W25MINOR) +# define CONFIG_NSH_W25MINOR 0 +#endif + +/* Can't support USB host or device features if USB OTG FS is not enabled */ + +#ifndef CONFIG_STM32_OTGFS +# undef HAVE_USBDEV +# undef HAVE_USBHOST +#endif + +/* Can't support USB device is USB device is not enabled */ + +#ifndef CONFIG_USBDEV +# undef HAVE_USBDEV +#endif + +/* Can't support USB host is USB host is not enabled */ + +#ifndef CONFIG_USBHOST +# undef HAVE_USBHOST +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_boardinitialize + * + * Description: + * All STM32 architectures must provide the following entry point. This + * entry point is called early in the initialization -- after all memory + * has been configured and mapped but before any devices have been + * initialized. + * + ****************************************************************************/ + +void stm32_boardinitialize(void) +{ + /* Configure SPI chip selects if 1) SPI is not disabled, and 2) the weak + * function stm32_spidev_initialize() has been brought into the link. + */ + +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI3) + if (stm32_spidev_initialize) + { + stm32_spidev_initialize(); + } +#endif + + /* Initialize USB is 1) USBDEV is selected, 2) the USB controller is not + * disabled, and 3) the weak function stm32_usbinitialize() has been + * brought into the build. + */ + +#if defined(CONFIG_USBDEV) && defined(CONFIG_STM32_USB) + if (stm32_usbinitialize) + { + stm32_usbinitialize(); + } +#endif + + /* Configure on-board LEDs if LED support has been selected. */ + +#ifdef CONFIG_ARCH_LEDS + board_autoled_initialize(); +#endif +} + +/**************************************************************************** + * Name: board_late_initialize + * + * Description: + * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_late_initialize(). board_late_initialize() will + * be called immediately after up_initialize() is called and just before + * the initial application is started. This additional initialization + * phase may be used, for example, to initialize board-specific device + * drivers. + * + ****************************************************************************/ + +#ifdef CONFIG_BOARD_LATE_INITIALIZE +void board_late_initialize(void) +{ + int ret; + + /* Initialize and register the W25 FLASH file system. */ + +#ifdef HAVE_W25 + ret = stm32_w25initialize(CONFIG_NSH_W25MINOR); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to initialize W25 minor %d: %d\n", + CONFIG_NSH_W25MINOR, ret); + return; + } +#endif + + /* Initialize USB host operation. stm32_usbhost_initialize() starts a + * thread will monitor for USB connection and disconnection events. + */ + +#ifdef HAVE_USBHOST + ret = stm32_usbhost_initialize(); + if (ret != OK) + { + syslog(LOG_ERR, "ERROR: Failed to initialize USB host: %d\n", ret); + return; + } +#endif + +#ifdef CONFIG_ADC + /* Initialize ADC and register the ADC driver. */ + + ret = stm32_adc_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_adc_setup failed: %d\n", ret); + return; + } +#endif + + UNUSED(ret); +} +#endif diff --git a/boards/arm/stm32f1/cloudctrl/src/stm32_buttons.c b/boards/arm/stm32f1/cloudctrl/src/stm32_buttons.c new file mode 100644 index 0000000000000..06b2467a8b292 --- /dev/null +++ b/boards/arm/stm32f1/cloudctrl/src/stm32_buttons.c @@ -0,0 +1,165 @@ +/**************************************************************************** + * boards/arm/stm32f1/cloudctrl/src/stm32_buttons.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include +#include + +#include "cloudctrl.h" + +#ifdef CONFIG_ARCH_BUTTONS + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* Pin configuration for each cloudctrl button. This array is indexed by + * the BUTTON_* definitions in board.h + */ + +static const uint32_t g_buttons[NUM_BUTTONS] = +{ + GPIO_BTN_USERKEY, GPIO_BTN_TAMPER, GPIO_BTN_WAKEUP +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_button_initialize + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. + * + ****************************************************************************/ + +uint32_t board_button_initialize(void) +{ + int i; + + /* Configure the GPIO pins as inputs. NOTE that EXTI interrupts are + * configured for some pins but NOT used in this file + */ + + for (i = 0; i < NUM_BUTTONS; i++) + { + stm32_configgpio(g_buttons[i]); + } + + return NUM_BUTTONS; +} + +/**************************************************************************** + * Name: board_buttons + ****************************************************************************/ + +uint32_t board_buttons(void) +{ + uint32_t ret = 0; + int i; + + /* Check that state of each key */ + + for (i = 0; i < NUM_BUTTONS; i++) + { + /* A LOW value means that the key is pressed for most keys. + * The exception is the WAKEUP button. + */ + + bool released = stm32_gpioread(g_buttons[i]); + if (i == BUTTON_WAKEUP) + { + released = !released; + } + + /* Accumulate the set of depressed (not released) keys */ + + if (!released) + { + ret |= (1 << i); + } + } + + return ret; +} + +/**************************************************************************** + * Button support. + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. + * + * After board_button_initialize() has been called, board_buttons() may be + * called to collect the state of all buttons. board_buttons() returns an + * 32-bit bit set with each bit associated with a button. See the + * BUTTON_*_BIT and JOYSTICK_*_BIT definitions in board.h for the meaning + * of each bit. + * + * board_button_irq() may be called to register an interrupt handler that + * will be called when a button is depressed or released. The ID value is a + * button enumeration value that uniquely identifies a button resource. See + * the BUTTON_* and JOYSTICK_* definitions in board.h for the meaning of + * enumeration value. + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_IRQBUTTONS +int board_button_irq(int id, xcpt_t irqhandler, void *arg) +{ + int ret = -EINVAL; + + /* The following should be atomic */ + + if (id >= MIN_IRQBUTTON && id <= MAX_IRQBUTTON) + { + ret = stm32_gpiosetevent(g_buttons[id], true, true, true, irqhandler, + arg); + } + + return ret; +} +#endif +#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/stm32f1/cloudctrl/src/stm32_chipid.c b/boards/arm/stm32f1/cloudctrl/src/stm32_chipid.c new file mode 100644 index 0000000000000..8abfb93176da9 --- /dev/null +++ b/boards/arm/stm32f1/cloudctrl/src/stm32_chipid.c @@ -0,0 +1,79 @@ +/**************************************************************************** + * boards/arm/stm32f1/cloudctrl/src/stm32_chipid.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include + +#include "arm_internal.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +const char *stm32_getchipid(void) +{ + static char cpuid[12]; + int i; + + for (i = 0; i < 12; i++) + { + cpuid[i] = getreg8(0x1ffff7e8 + i); + } + + return cpuid; +} + +const char *stm32_getchipid_string(void) +{ + static char cpuid[27]; + int c; + int i; + + for (i = 0, c = 0; i < 12; i++) + { + snprintf(&cpuid[c], sizeof(cpuid) - c, + "%02X", getreg8(0x1ffff7e8 + 11 - i)); + c += 2; + if (i % 4 == 3) + { + cpuid[c++] = '-'; + } + } + + cpuid[26] = '\0'; + return cpuid; +} diff --git a/boards/arm/stm32/cloudctrl/src/stm32_phyinit.c b/boards/arm/stm32f1/cloudctrl/src/stm32_phyinit.c similarity index 97% rename from boards/arm/stm32/cloudctrl/src/stm32_phyinit.c rename to boards/arm/stm32f1/cloudctrl/src/stm32_phyinit.c index 26b01ab9810f5..95382ef1a2235 100644 --- a/boards/arm/stm32/cloudctrl/src/stm32_phyinit.c +++ b/boards/arm/stm32f1/cloudctrl/src/stm32_phyinit.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/cloudctrl/src/stm32_phyinit.c + * boards/arm/stm32f1/cloudctrl/src/stm32_phyinit.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f1/cloudctrl/src/stm32_relays.c b/boards/arm/stm32f1/cloudctrl/src/stm32_relays.c new file mode 100644 index 0000000000000..e86a2345942c7 --- /dev/null +++ b/boards/arm/stm32f1/cloudctrl/src/stm32_relays.c @@ -0,0 +1,274 @@ +/**************************************************************************** + * boards/arm/stm32f1/cloudctrl/src/stm32_relays.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include +#include + +#include "cloudctrl.h" + +#ifdef CONFIG_ARCH_RELAYS + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define RELAYS_MIN_RESET_TIME 5 +#define RELAYS_RESET_MTIME 5 +#define RELAYS_POWER_MTIME 50 + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static uint32_t g_relays_stat = 0; +static bool g_relays_init = false; + +static const uint16_t g_relays[NUM_RELAYS] = +{ + GPIO_RELAYS_R00 +#ifdef GPIO_RELAYS_R01 + , GPIO_RELAYS_R01 +#endif +#ifdef GPIO_RELAYS_R02 + , GPIO_RELAYS_R02 +#endif +#ifdef GPIO_RELAYS_R03 + , GPIO_RELAYS_R03 +#endif +#ifdef GPIO_RELAYS_R04 + , GPIO_RELAYS_R04 +#endif +#ifdef GPIO_RELAYS_R05 + , GPIO_RELAYS_R05 +#endif +#ifdef GPIO_RELAYS_R06 + , GPIO_RELAYS_R06 +#endif +#ifdef GPIO_RELAYS_R07 + , GPIO_RELAYS_R07 +#endif +#ifdef GPIO_RELAYS_R08 + , GPIO_RELAYS_R08 +#endif +#ifdef GPIO_RELAYS_R09 + , GPIO_RELAYS_R09 +#endif +#ifdef GPIO_RELAYS_R10 + , GPIO_RELAYS_R10 +#endif +#ifdef GPIO_RELAYS_R11 + , GPIO_RELAYS_R11 +#endif +#ifdef GPIO_RELAYS_R12 + , GPIO_RELAYS_R12 +#endif +#ifdef GPIO_RELAYS_R13 + , GPIO_RELAYS_R13 +#endif +#ifdef GPIO_RELAYS_R14 + , GPIO_RELAYS_R14 +#endif +#ifdef GPIO_RELAYS_R15 + , GPIO_RELAYS_R15 +#endif +#ifdef GPIO_RELAYS_R16 + , GPIO_RELAYS_R16 +#endif +#ifdef GPIO_RELAYS_R17 + , GPIO_RELAYS_R17 +#endif +#ifdef GPIO_RELAYS_R18 + , GPIO_RELAYS_R18 +#endif +#ifdef GPIO_RELAYS_R19 + , GPIO_RELAYS_R19 +#endif +#ifdef GPIO_RELAYS_R20 + , GPIO_RELAYS_R20 +#endif +#ifdef GPIO_RELAYS_R21 + , GPIO_RELAYS_R21 +#endif +#ifdef GPIO_RELAYS_R22 + , GPIO_RELAYS_R22 +#endif +#ifdef GPIO_RELAYS_R23 + , GPIO_RELAYS_R23 +#endif +#ifdef GPIO_RELAYS_R24 + , GPIO_RELAYS_R24 +#endif +#ifdef GPIO_RELAYS_R25 + , GPIO_RELAYS_R25 +#endif +#ifdef GPIO_RELAYS_R26 + , GPIO_RELAYS_R26 +#endif +#ifdef GPIO_RELAYS_R27 + , GPIO_RELAYS_R27 +#endif +#ifdef GPIO_RELAYS_R28 + , GPIO_RELAYS_R28 +#endif +#ifdef GPIO_RELAYS_R29 + , GPIO_RELAYS_R29 +#endif +#ifdef GPIO_RELAYS_R30 + , GPIO_RELAYS_R30 +#endif +#ifdef GPIO_RELAYS_R31 + , GPIO_RELAYS_R31 +#endif +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +void up_relaysinit(void) +{ + int i; + + if (g_relays_init) + { + return; + } + + /* Configure the GPIO pins as inputs. NOTE that EXTI interrupts are + * configured for some pins but NOT used in this file + */ + + for (i = 0; i < NUM_RELAYS; i++) + { + stm32_configgpio(g_relays[i]); + stm32_gpiowrite(g_relays[i], false); + } + + g_relays_init = true; +} + +void relays_setstat(int relays, bool stat) +{ + if ((unsigned)relays < NUM_RELAYS) + { + stm32_gpiowrite(g_relays[relays], stat); + if (!stat) + { + g_relays_stat &= ~(1 << relays); + } + else + { + g_relays_stat |= (1 << relays); + } + } +} + +bool relays_getstat(int relays) +{ + if ((unsigned)relays < NUM_RELAYS) + { + return (g_relays_stat & (1 << relays)) != 0; + } + + return false; +} + +void relays_setstats(uint32_t relays_stat) +{ + int i; + + for (i = 0; i < NUM_RELAYS; i++) + { + relays_setstat(i, (relays_stat & (1 << i)) != 0); + } +} + +uint32_t relays_getstats(void) +{ + return (uint32_t)g_relays_stat; +} + +void relays_onoff(int relays, uint32_t mdelay) +{ + if ((unsigned)relays < NUM_RELAYS) + { + if (mdelay > 0) + { + if (relays_getstat(relays)) + { + relays_setstat(relays, false); + nxsched_usleep(RELAYS_MIN_RESET_TIME * 1000 * 1000); + } + + relays_setstat(relays, true); + nxsched_usleep(mdelay * 100 * 1000); + relays_setstat(relays, false); + } + } +} + +void relays_onoffs(uint32_t relays_stat, uint32_t mdelay) +{ + int i; + + for (i = 0; i < NUM_RELAYS; i++) + { + relays_onoff(i, mdelay); + } +} + +void relays_resetmode(int relays) +{ + relays_onoff(relays, RELAYS_RESET_MTIME); +} + +void relays_powermode(int relays) +{ + relays_onoff(relays, RELAYS_POWER_MTIME); +} + +void relays_resetmodes(uint32_t relays_stat) +{ + relays_onoffs(relays_stat, RELAYS_RESET_MTIME); +} + +void relays_powermodes(uint32_t relays_stat) +{ + relays_onoffs(relays_stat, RELAYS_POWER_MTIME); +} + +#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/stm32f1/cloudctrl/src/stm32_spi.c b/boards/arm/stm32f1/cloudctrl/src/stm32_spi.c new file mode 100644 index 0000000000000..d1aa4127a14ef --- /dev/null +++ b/boards/arm/stm32f1/cloudctrl/src/stm32_spi.c @@ -0,0 +1,139 @@ +/**************************************************************************** + * boards/arm/stm32f1/cloudctrl/src/stm32_spi.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "arm_internal.h" +#include "chip.h" +#include "stm32.h" +#include "cloudctrl.h" + +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI3) + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_spidev_initialize + * + * Description: + * Called to configure SPI chip select GPIO pins for the cloudctrl board. + * + ****************************************************************************/ + +void weak_function stm32_spidev_initialize(void) +{ + /* NOTE: Clocking for SPI1 and/or SPI3 was already provided in stm32_rcc.c. + * Configurations of SPI pins is performed in stm32_spi.c. + * Here, we only initialize chip select pins unique to the board + * architecture. + */ + + /* SPI1 connects to the SD CARD and to the SPI FLASH */ + +#ifdef CONFIG_STM32_SPI1 + stm32_configgpio(GPIO_FLASH_CS); /* FLASH chip select */ +#endif + + /* SPI3 connects to TFT LCD module and the RF24L01 2.4G wireless module */ + +#ifdef CONFIG_STM32_SPI3 + +#endif +} + +/**************************************************************************** + * Name: stm32_spi1/2/3select and stm32_spi1/2/3status + * + * Description: + * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status + * must be provided by board-specific logic. They are implementations of + * the select and status methods of the SPI interface defined by struct + * spi_ops_s (see include/nuttx/spi/spi.h). All other methods (including + * stm32_spibus_initialize()) are provided by common STM32 logic. + * To use this common SPI logic on your board: + * + * 1. Provide logic in stm32_boardinitialize() to configure SPI chip + * select pins. + * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() functions + * in your board-specific logic. These functions will perform chip + * selection and status operations using GPIOs in the way your board is + * configured. + * 3. Add a calls to stm32_spibus_initialize() in your low level + * application initialization logic + * 4. The handle returned by stm32_spibus_initialize() may then be used to + * bind the SPI driver to higher level logic (e.g., calling + * mmcsd_spislotinitialize(), for example, will bind the SPI driver to + * the SPI MMC/SD driver). + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_SPI1 +void stm32_spi1select(struct spi_dev_s *dev, + uint32_t devid, bool selected) +{ + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); + + /* SPI1 connects to the SD CARD and to the SPI FLASH */ + + if (devid == SPIDEV_FLASH(0)) + { + /* Set the GPIO low to select and high to de-select */ + + stm32_gpiowrite(GPIO_FLASH_CS, !selected); + } +} + +uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) +{ + return SPI_STATUS_PRESENT; +} +#endif + +#ifdef CONFIG_STM32_SPI3 +void stm32_spi3select(struct spi_dev_s *dev, + uint32_t devid, bool selected) +{ + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); +} + +uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} +#endif + +#endif /* CONFIG_STM32_SPI1 || CONFIG_STM32_SPI3 */ diff --git a/boards/arm/stm32f1/cloudctrl/src/stm32_usb.c b/boards/arm/stm32f1/cloudctrl/src/stm32_usb.c new file mode 100644 index 0000000000000..92b57904640c0 --- /dev/null +++ b/boards/arm/stm32f1/cloudctrl/src/stm32_usb.c @@ -0,0 +1,304 @@ +/**************************************************************************** + * boards/arm/stm32f1/cloudctrl/src/stm32_usb.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include "arm_internal.h" +#include "stm32.h" +#include "stm32_otgfs.h" +#include "cloudctrl.h" + +#ifdef CONFIG_STM32_OTGFS + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#if defined(CONFIG_USBDEV) || defined(CONFIG_USBHOST) +# define HAVE_USB 1 +#else +# warning "CONFIG_STM32_OTGFS is enabled but neither CONFIG_USBDEV nor CONFIG_USBHOST" +# undef HAVE_USB +#endif + +#ifndef CONFIG_USBHOST_DEFPRIO +# define CONFIG_USBHOST_DEFPRIO 50 +#endif + +#ifndef CONFIG_USBHOST_STACKSIZE +# ifdef CONFIG_USBHOST_HUB +# define CONFIG_USBHOST_STACKSIZE 1536 +# else +# define CONFIG_USBHOST_STACKSIZE 1024 +# endif +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +static struct usbhost_connection_s *g_usbconn; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: usbhost_waiter + * + * Description: + * Wait for USB devices to be connected. + * + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +static int usbhost_waiter(int argc, char *argv[]) +{ + struct usbhost_hubport_s *hport; + + uinfo("Running\n"); + for (; ; ) + { + /* Wait for the device to change state */ + + DEBUGVERIFY(CONN_WAIT(g_usbconn, &hport)); + uinfo("%s\n", hport->connected ? "connected" : "disconnected"); + + /* Did we just become connected? */ + + if (hport->connected) + { + /* Yes.. enumerate the newly connected device */ + + CONN_ENUMERATE(g_usbconn, hport); + } + } + + /* Keep the compiler from complaining */ + + return 0; +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_usbinitialize + * + * Description: + * Called from stm32_usbinitialize very early in initialization to setup + * USB-related GPIO pins for the STM3240G-EVAL board. + * + ****************************************************************************/ + +void stm32_usbinitialize(void) +{ + /* The OTG FS has an internal soft pull-up. + * No GPIO configuration is required + */ + + /* Configure the OTG FS VBUS sensing GPIO, + * Power On, and Overcurrent GPIOs + */ + +#ifdef CONFIG_STM32_OTGFS + stm32_configgpio(GPIO_OTGFS_VBUS); + stm32_configgpio(GPIO_OTGFS_PWRON); + stm32_configgpio(GPIO_OTGFS_OVER); +#endif +} + +/**************************************************************************** + * Name: stm32_usbhost_initialize + * + * Description: + * Called at application startup time to initialize the USB host + * functionality. + * This function will start a thread that will monitor for device + * connection/disconnection events. + * + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +int stm32_usbhost_initialize(void) +{ + int ret; + + /* First, register all of the class drivers needed to support the drivers + * that we care about: + */ + + uinfo("Register class drivers\n"); + +#ifdef CONFIG_USBHOST_MSC + /* Register the USB mass storage class */ + + ret = usbhost_msc_initialize(); + if (ret != OK) + { + uerr("ERROR: Failed to register the mass storage class\n"); + } +#endif + +#ifdef CONFIG_USBHOST_CDCACM + /* Register the CDC/ACM serial class */ + + ret = usbhost_cdcacm_initialize(); + if (ret != OK) + { + uerr("ERROR: Failed to register the CDC/ACM serial class\n"); + } +#endif + + /* Then get an instance of the USB host interface */ + + uinfo("Initialize USB host\n"); + g_usbconn = stm32_otgfshost_initialize(0); + if (g_usbconn) + { + /* Start a thread to handle device connection. */ + + uinfo("Start usbhost_waiter\n"); + + ret = kthread_create("usbhost", CONFIG_USBHOST_DEFPRIO, + CONFIG_USBHOST_STACKSIZE, + usbhost_waiter, NULL); + return ret < 0 ? -ENOEXEC : OK; + } + + return -ENODEV; +} +#endif + +/**************************************************************************** + * Name: stm32_usbhost_vbusdrive + * + * Description: + * Enable/disable driving of VBUS 5V output. This function must be + * provided be each platform that implements the STM32 OTG FS host + * interface + * + * "On-chip 5 V VBUS generation is not supported. For this reason, a + * charge pump or, if 5 V are available on the application board, a + * basic power switch, must be added externally to drive the 5 V VBUS + * line. The external charge pump can be driven by any GPIO output. + * When the application decides to power on VBUS using the chosen GPIO, + * it must also set the port power bit in the host port control and + * status register (PPWR bit in OTG_FS_HPRT). + * + * "The application uses this field to control power to this port, + * and the core clears this bit on an overcurrent condition." + * + * Input Parameters: + * iface - For future growth to handle multiple USB host interface. + * Should be zero. + * enable - true: enable VBUS power; false: disable VBUS power + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +void stm32_usbhost_vbusdrive(int iface, bool enable) +{ + DEBUGASSERT(iface == 0); + + if (enable) + { + /* Enable the Power Switch by driving the enable pin low */ + + stm32_gpiowrite(GPIO_OTGFS_PWRON, false); + } + else + { + /* Disable the Power Switch by driving the enable pin high */ + + stm32_gpiowrite(GPIO_OTGFS_PWRON, true); + } +} +#endif + +/**************************************************************************** + * Name: stm32_setup_overcurrent + * + * Description: + * Setup to receive an interrupt-level callback if an overcurrent + * condition is detected. + * + * Input Parameters: + * handler - New overcurrent interrupt handler + * arg - The argument provided for the interrupt handler + * + * Returned Value: + * Zero (OK) is returned on success. Otherwise, a negated errno value + * is returned to indicate the nature of the failure. + * + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +int stm32_setup_overcurrent(xcpt_t handler, void *arg) +{ + return -ENOSYS; +} +#endif + +/**************************************************************************** + * Name: stm32_usbsuspend + * + * Description: + * Board logic must provide the stm32_usbsuspend logic if the USBDEV + * driver is used. This function is called whenever the USB enters or + * leaves suspend mode. This is an opportunity for the board logic to + * shutdown clocks, power, etc. while the USB is suspended. + * + ****************************************************************************/ + +#ifdef CONFIG_USBDEV +void stm32_usbsuspend(struct usbdev_s *dev, bool resume) +{ + uinfo("resume: %d\n", resume); +} +#endif + +#endif /* CONFIG_STM32_OTGFS */ diff --git a/boards/arm/stm32f1/cloudctrl/src/stm32_usbmsc.c b/boards/arm/stm32f1/cloudctrl/src/stm32_usbmsc.c new file mode 100644 index 0000000000000..bde124645141a --- /dev/null +++ b/boards/arm/stm32f1/cloudctrl/src/stm32_usbmsc.c @@ -0,0 +1,71 @@ +/**************************************************************************** + * boards/arm/stm32f1/cloudctrl/src/stm32_usbmsc.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include + +#include "stm32.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +#ifndef CONFIG_SYSTEM_USBMSC_DEVMINOR1 +# define CONFIG_SYSTEM_USBMSC_DEVMINOR1 0 +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_usbmsc_initialize + * + * Description: + * Perform architecture specific initialization of the USB MSC device. + * + ****************************************************************************/ + +int board_usbmsc_initialize(int port) +{ + /* If system/usbmsc is built as an NSH command, then SD slot should + * already have been initialized. + * In this case, there is nothing further to be done here. + */ + +#ifndef CONFIG_NSH_BUILTIN_APPS + return stm32_sdinitialize(CONFIG_SYSTEM_USBMSC_DEVMINOR1); +#else + return OK; +#endif +} diff --git a/boards/arm/stm32f1/cloudctrl/src/stm32_userleds.c b/boards/arm/stm32f1/cloudctrl/src/stm32_userleds.c new file mode 100644 index 0000000000000..3fbcf5b60fb7a --- /dev/null +++ b/boards/arm/stm32f1/cloudctrl/src/stm32_userleds.c @@ -0,0 +1,96 @@ +/**************************************************************************** + * boards/arm/stm32f1/cloudctrl/src/stm32_userleds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32.h" +#include "cloudctrl.h" + +#ifndef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* This array maps an LED number to GPIO pin configuration */ + +static uint32_t g_ledcfg[BOARD_NLEDS] = +{ + GPIO_LED1, GPIO_LED2, GPIO_LED3, GPIO_LED4 +}; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_userled_initialize + ****************************************************************************/ + +uint32_t board_userled_initialize(void) +{ + /* Configure LED1-3 GPIOs for output */ + + stm32_configgpio(GPIO_LED1); + stm32_configgpio(GPIO_LED2); + stm32_configgpio(GPIO_LED3); + stm32_configgpio(GPIO_LED4); + return BOARD_NLEDS; +} + +/**************************************************************************** + * Name: board_userled + ****************************************************************************/ + +void board_userled(int led, bool ledon) +{ + if ((unsigned)led < BOARD_NLEDS) + { + stm32_gpiowrite(g_ledcfg[led], ledon); + } +} + +/**************************************************************************** + * Name: board_userled_all + ****************************************************************************/ + +void board_userled_all(uint32_t ledset) +{ + stm32_gpiowrite(GPIO_LED1, (ledset & BOARD_LED1_BIT) == 0); + stm32_gpiowrite(GPIO_LED2, (ledset & BOARD_LED2_BIT) == 0); + stm32_gpiowrite(GPIO_LED3, (ledset & BOARD_LED3_BIT) == 0); + stm32_gpiowrite(GPIO_LED4, (ledset & BOARD_LED4_BIT) == 0); +} + +#endif /* !CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32f1/cloudctrl/src/stm32_w25.c b/boards/arm/stm32f1/cloudctrl/src/stm32_w25.c new file mode 100644 index 0000000000000..16de2838d3a91 --- /dev/null +++ b/boards/arm/stm32f1/cloudctrl/src/stm32_w25.c @@ -0,0 +1,144 @@ +/**************************************************************************** + * boards/arm/stm32f1/cloudctrl/src/stm32_w25.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#ifdef CONFIG_STM32_SPI1 +# include +# include +# include +# include +#endif + +#include "stm32_spi.h" +#include "cloudctrl.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* Can't support the W25 device if it SPI1 or W25 support is not enabled */ + +#define HAVE_W25 1 +#if !defined(CONFIG_STM32_SPI1) || !defined(CONFIG_MTD_W25) +# undef HAVE_W25 +#endif + +/* Can't support W25 features if mountpoints are disabled */ + +#if defined(CONFIG_DISABLE_MOUNTPOINT) +# undef HAVE_W25 +#endif + +/* Can't support both FAT and NXFFS */ + +#if defined(CONFIG_FS_FAT) && defined(CONFIG_FS_NXFFS) +# warning "Can't support both FAT and NXFFS -- using FAT" +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_w25initialize + * + * Description: + * Initialize and register the W25 FLASH file system. + * + ****************************************************************************/ + +int stm32_w25initialize(int minor) +{ +#ifdef HAVE_W25 + struct spi_dev_s *spi; + struct mtd_dev_s *mtd; +#ifdef CONFIG_FS_NXFFS + char devname[12]; +#endif + int ret; + + /* Get the SPI port */ + + spi = stm32_spibus_initialize(1); + if (!spi) + { + ferr("ERROR: Failed to initialize SPI port 2\n"); + return -ENODEV; + } + + /* Now bind the SPI interface to the W25 SPI FLASH driver */ + + mtd = w25_initialize(spi); + if (!mtd) + { + ferr("ERROR: Failed to bind SPI port 2 to the SST 25 FLASH driver\n"); + return -ENODEV; + } + +#ifndef CONFIG_FS_NXFFS + /* Register the MTD driver */ + + char path[32]; + snprintf(path, sizeof(path), "/dev/mtdblock%d", minor); + ret = register_mtddriver(path, mtd, 0755, NULL); + if (ret < 0) + { + ferr("ERROR: Failed to register the MTD driver %s, ret %d\n", + path, ret); + return ret; + } +#else + /* Initialize to provide NXFFS on the MTD interface */ + + ret = nxffs_initialize(mtd); + if (ret < 0) + { + ferr("ERROR: NXFFS initialization failed: %d\n", -ret); + return ret; + } + + /* Mount the file system at /mnt/w25 */ + + snprintf(devname, sizeof(devname), "/mnt/w25%c", 'a' + minor); + ret = nx_mount(NULL, devname, "nxffs", 0, NULL); + if (ret < 0) + { + ferr("ERROR: Failed to mount the NXFFS volume: %d\n", ret); + return ret; + } +#endif +#endif + + return OK; +} diff --git a/boards/arm/stm32/cloudctrl/tools/olimex-arm-usb-ocd.cfg b/boards/arm/stm32f1/cloudctrl/tools/olimex-arm-usb-ocd.cfg similarity index 100% rename from boards/arm/stm32/cloudctrl/tools/olimex-arm-usb-ocd.cfg rename to boards/arm/stm32f1/cloudctrl/tools/olimex-arm-usb-ocd.cfg diff --git a/boards/arm/stm32/cloudctrl/tools/oocd.sh b/boards/arm/stm32f1/cloudctrl/tools/oocd.sh similarity index 100% rename from boards/arm/stm32/cloudctrl/tools/oocd.sh rename to boards/arm/stm32f1/cloudctrl/tools/oocd.sh diff --git a/boards/arm/stm32/cloudctrl/tools/stm32.cfg b/boards/arm/stm32f1/cloudctrl/tools/stm32.cfg similarity index 100% rename from boards/arm/stm32/cloudctrl/tools/stm32.cfg rename to boards/arm/stm32f1/cloudctrl/tools/stm32.cfg diff --git a/boards/arm/stm32/cloudctrl/tools/usb-driver.txt b/boards/arm/stm32f1/cloudctrl/tools/usb-driver.txt similarity index 100% rename from boards/arm/stm32/cloudctrl/tools/usb-driver.txt rename to boards/arm/stm32f1/cloudctrl/tools/usb-driver.txt diff --git a/boards/arm/stm32f1/common/CMakeLists.txt b/boards/arm/stm32f1/common/CMakeLists.txt new file mode 100644 index 0000000000000..b46b5b7c6779a --- /dev/null +++ b/boards/arm/stm32f1/common/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32f1/common/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(${NUTTX_DIR}/boards/arm/common/stm32 stm32_common) diff --git a/boards/arm/stm32f1/common/Kconfig b/boards/arm/stm32f1/common/Kconfig new file mode 100644 index 0000000000000..5c48f62a0258b --- /dev/null +++ b/boards/arm/stm32f1/common/Kconfig @@ -0,0 +1,6 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# + +source "boards/arm/common/stm32/Kconfig" diff --git a/boards/arm/stm32f1/common/Makefile b/boards/arm/stm32f1/common/Makefile new file mode 100644 index 0000000000000..f00fda1b6e974 --- /dev/null +++ b/boards/arm/stm32f1/common/Makefile @@ -0,0 +1,39 @@ +############################################################################# +# boards/arm/stm32f1/common/Makefile +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################# + +include $(TOPDIR)/Make.defs + +STM32_BOARD_COMMON_DIR := $(TOPDIR)$(DELIM)boards$(DELIM)arm$(DELIM)common$(DELIM)stm32 +STM32_COMMON_SRCDIR := $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)common$(DELIM)stm32 + +include board/Make.defs +include $(STM32_BOARD_COMMON_DIR)$(DELIM)src$(DELIM)Make.defs + +DEPPATH += --dep-path board + +include $(TOPDIR)/boards/Board.mk + +ARCHSRCDIR = $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src +BOARDDIR = $(ARCHSRCDIR)$(DELIM)board +CFLAGS += ${INCDIR_PREFIX}$(BOARDDIR)$(DELIM)include +CFLAGS += ${INCDIR_PREFIX}$(STM32_COMMON_SRCDIR) +CXXFLAGS += ${INCDIR_PREFIX}$(STM32_COMMON_SRCDIR) diff --git a/boards/arm/stm32f1/et-stm32-stamp/CMakeLists.txt b/boards/arm/stm32f1/et-stm32-stamp/CMakeLists.txt new file mode 100644 index 0000000000000..eb55f812bdab1 --- /dev/null +++ b/boards/arm/stm32f1/et-stm32-stamp/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32f1/et-stm32-stamp/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/arm/stm32/et-stm32-stamp/Kconfig b/boards/arm/stm32f1/et-stm32-stamp/Kconfig similarity index 100% rename from boards/arm/stm32/et-stm32-stamp/Kconfig rename to boards/arm/stm32f1/et-stm32-stamp/Kconfig diff --git a/boards/arm/stm32f1/et-stm32-stamp/configs/nsh/defconfig b/boards/arm/stm32f1/et-stm32-stamp/configs/nsh/defconfig new file mode 100644 index 0000000000000..33ca638408156 --- /dev/null +++ b/boards/arm/stm32f1/et-stm32-stamp/configs/nsh/defconfig @@ -0,0 +1,36 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="et-stm32-stamp" +CONFIG_ARCH_BOARD_ET_STM32_STAMP=y +CONFIG_ARCH_CHIP="stm32f1" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F103RE=y +CONFIG_ARCH_CHIP_STM32F1=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=5483 +CONFIG_BUILTIN=y +CONFIG_DEFAULT_SMALL=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_LIBC_RAND_ORDER=2 +CONFIG_LINE_MAX=80 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=1024 +CONFIG_PTHREAD_STACK_DEFAULT=1024 +CONFIG_RAM_SIZE=20480 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_START_DAY=23 +CONFIG_START_MONTH=10 +CONFIG_START_YEAR=2009 +CONFIG_STM32_USART1=y +CONFIG_SYMTAB_ORDEREDBYNAME=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f1/et-stm32-stamp/include/board.h b/boards/arm/stm32f1/et-stm32-stamp/include/board.h new file mode 100644 index 0000000000000..7cb521fadc8b8 --- /dev/null +++ b/boards/arm/stm32f1/et-stm32-stamp/include/board.h @@ -0,0 +1,155 @@ +/**************************************************************************** + * boards/arm/stm32f1/et-stm32-stamp/include/board.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_STM32_ET_STM32_STAMP_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32_ET_STM32_STAMP_INCLUDE_BOARD_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#ifndef __ASSEMBLY__ +# include +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Clocking *****************************************************************/ + +/* On-board crystal frequency is 8MHz (HSE) */ + +#define STM32_BOARD_XTAL 8000000ul + +/* PLL source is HSE/1, PLL multiplier is 9: + * PLL frequency is 8MHz (XTAL) x 9 = 72MHz + */ + +#define STM32_CFGR_PLLSRC RCC_CFGR_PLLSRC +#define STM32_CFGR_PLLXTPRE 0 +#define STM32_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx9 +#define STM32_PLL_FREQUENCY (9*STM32_BOARD_XTAL) + +/* Use the PLL and set the SYSCLK source to be the PLL */ + +#define STM32_SYSCLK_SW RCC_CFGR_SW_PLL +#define STM32_SYSCLK_SWS RCC_CFGR_SWS_PLL +#define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY + +/* AHB clock (HCLK) is SYSCLK (72MHz) */ + +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK +#define STM32_HCLK_FREQUENCY STM32_PLL_FREQUENCY + +/* APB2 clock (PCLK2) is HCLK (72MHz) */ + +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK +#define STM32_PCLK2_FREQUENCY STM32_HCLK_FREQUENCY + +/* APB2 timers 1 and 8 will receive PCLK2. */ + +#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) + +/* APB1 clock (PCLK1) is HCLK/2 (36MHz) */ + +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd2 +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/2) + +/* APB1 timers 2-7 will be twice PCLK1 */ + +#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) + +/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx + * otherwise frequency is 2xAPBx. + * Note: TIM1,8 are on APB2, others on APB1 + */ + +#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM2_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM3_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM4_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM5_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM6_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM7_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY + +/* SDIO dividers. Note that slower clocking is required when DMA is disabled + * in order to avoid RX overrun/TX underrun errors due to delayed responses + * to service FIFOs in interrupt driven mode. These values have not been + * tuned!!! + * + * HCLK=72MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(178+2)=400 KHz + */ + +#define SDIO_INIT_CLKDIV (178 << SDIO_CLKCR_CLKDIV_SHIFT) + +/* DMA ON: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(2+2)=18 MHz + * DMA OFF: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(3+2)=14.4 MHz + */ + +#ifdef CONFIG_SDIO_DMA +# define SDIO_MMCXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT) +#else +# define SDIO_MMCXFR_CLKDIV (3 << SDIO_CLKCR_CLKDIV_SHIFT) +#endif + +/* DMA ON: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(1+2)=24 MHz + * DMA OFF: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(3+2)=14.4 MHz + */ + +#ifdef CONFIG_SDIO_DMA +# define SDIO_SDXFR_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT) +#else +# define SDIO_SDXFR_CLKDIV (3 << SDIO_CLKCR_CLKDIV_SHIFT) +#endif + +/* LED definitions **********************************************************/ + +/* The ET-STM32 Stamp doesn't have an on-board LED. These innocent macros + * can still be here. + */ + +#define LED_STARTED 0 /* No LEDs */ +#define LED_HEAPALLOCATE 1 /* LED1 on */ +#define LED_IRQSENABLED 2 /* LED2 on */ +#define LED_STACKCREATED 3 /* LED1 on */ +#define LED_INIRQ 4 /* LED1 off */ +#define LED_SIGNAL 5 /* LED2 on */ +#define LED_ASSERTION 6 /* LED1 + LED2 */ +#define LED_PANIC 7 /* LED1 / LED2 blinking */ + +/* Alternate function pin selections (auto-aliased for new pinmap) */ + +/* USART1 */ + +#define GPIO_USART1_TX GPIO_ADJUST_MODE(GPIO_USART1_TX_0, GPIO_MODE_50MHz) +#define GPIO_USART1_RX GPIO_USART1_RX_0 + +#endif /* __BOARDS_ARM_STM32_ET_STM32_STAMP_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32f1/et-stm32-stamp/scripts/Make.defs b/boards/arm/stm32f1/et-stm32-stamp/scripts/Make.defs new file mode 100644 index 0000000000000..3470a34f64a50 --- /dev/null +++ b/boards/arm/stm32f1/et-stm32-stamp/scripts/Make.defs @@ -0,0 +1,41 @@ +############################################################################ +# boards/arm/stm32f1/et-stm32-stamp/scripts/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/.config +include $(TOPDIR)/tools/Config.mk +include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs + +LDSCRIPT = ld.script +ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) + +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32f1/et-stm32-stamp/scripts/ld.script b/boards/arm/stm32f1/et-stm32-stamp/scripts/ld.script new file mode 100644 index 0000000000000..6c11e86fc69bb --- /dev/null +++ b/boards/arm/stm32f1/et-stm32-stamp/scripts/ld.script @@ -0,0 +1,123 @@ +/**************************************************************************** + * boards/arm/stm32f1/et-stm32-stamp/scripts/ld.script + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + * + ****************************************************************************/ + +/* The STM32F103RE has 512Kb of FLASH beginning at address 0x0800:0000 and + * 64Kb of SRAM beginning at address 0x2000:0000. When booting from FLASH, + * FLASH memory is aliased to address 0x0000:0000 where the code expects to + * begin execution by jumping to the entry point in the 0x0800:0000 address + * range. + */ + +MEMORY +{ + flash (rx) : ORIGIN = 0x08000000, LENGTH = 512K + sram (rwx) : ORIGIN = 0x20000000, LENGTH = 64K +} + +OUTPUT_ARCH(arm) +EXTERN(_vectors) +ENTRY(_stext) +SECTIONS +{ + .text : { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > flash + + .init_section : ALIGN(4) { + _sinit = ABSOLUTE(.); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) + _einit = ABSOLUTE(.); + } > flash + + .ARM.extab : ALIGN(4) { + *(.ARM.extab*) + } > flash + + .ARM.exidx : ALIGN(4) { + __exidx_start = ABSOLUTE(.); + *(.ARM.exidx*) + __exidx_end = ABSOLUTE(.); + } > flash + + .tdata : { + _stdata = ABSOLUTE(.); + *(.tdata .tdata.* .gnu.linkonce.td.*); + _etdata = ABSOLUTE(.); + } > flash + + .tbss : { + _stbss = ABSOLUTE(.); + *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); + _etbss = ABSOLUTE(.); + } > flash + + _eronly = ABSOLUTE(.); + + /* The STM32F103RET6 has 64Kb of SRAM beginning at the following address */ + + .data : ALIGN(4) { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > sram AT > flash + + .bss : ALIGN(4) { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + _ebss = ABSOLUTE(.); + } > sram + + /* Stabs debugging sections. */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/stm32f1/et-stm32-stamp/src/CMakeLists.txt b/boards/arm/stm32f1/et-stm32-stamp/src/CMakeLists.txt new file mode 100644 index 0000000000000..b7aae37dd01da --- /dev/null +++ b/boards/arm/stm32f1/et-stm32-stamp/src/CMakeLists.txt @@ -0,0 +1,27 @@ +# ############################################################################## +# boards/arm/stm32f1/et-stm32-stamp/src/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(SRCS stm32_boot.c) + +target_sources(board PRIVATE ${SRCS}) + +set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/ld.script") diff --git a/boards/arm/stm32f1/et-stm32-stamp/src/Make.defs b/boards/arm/stm32f1/et-stm32-stamp/src/Make.defs new file mode 100644 index 0000000000000..d022a6aad9892 --- /dev/null +++ b/boards/arm/stm32f1/et-stm32-stamp/src/Make.defs @@ -0,0 +1,29 @@ +############################################################################ +# boards/arm/stm32f1/et-stm32-stamp/src/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +CSRCS = stm32_boot.c + +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/et-stm32-stamp/src/et-stm32-stamp.h b/boards/arm/stm32f1/et-stm32-stamp/src/et-stm32-stamp.h similarity index 96% rename from boards/arm/stm32/et-stm32-stamp/src/et-stm32-stamp.h rename to boards/arm/stm32f1/et-stm32-stamp/src/et-stm32-stamp.h index 4daca3f0bfb6c..81ca060fcaba8 100644 --- a/boards/arm/stm32/et-stm32-stamp/src/et-stm32-stamp.h +++ b/boards/arm/stm32f1/et-stm32-stamp/src/et-stm32-stamp.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/et-stm32-stamp/src/et-stm32-stamp.h + * boards/arm/stm32f1/et-stm32-stamp/src/et-stm32-stamp.h * * SPDX-License-Identifier: Apache-2.0 * @@ -32,7 +32,7 @@ #include -#include +#include /**************************************************************************** * Pre-processor Definitions diff --git a/boards/arm/stm32f1/et-stm32-stamp/src/stm32_boot.c b/boards/arm/stm32f1/et-stm32-stamp/src/stm32_boot.c new file mode 100644 index 0000000000000..498eae42453b9 --- /dev/null +++ b/boards/arm/stm32f1/et-stm32-stamp/src/stm32_boot.c @@ -0,0 +1,83 @@ +/**************************************************************************** + * boards/arm/stm32f1/et-stm32-stamp/src/stm32_boot.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include + +#include +#include + +#include "arm_internal.h" +#include "et-stm32-stamp.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_boardinitialize + * + * Description: + * All STM32 architectures must provide the following entry point. This + * entry point is called early in the initialization -- after all memory + * has been configured and mapped but before any devices have been + * initialized. + * + ****************************************************************************/ + +void stm32_boardinitialize(void) +{ + /* Empty for now. */ +} + +/**************************************************************************** + * Name: board_late_initialize + * + * Description: + * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_late_initialize(). board_late_initialize() will + * be called immediately after up_initialize() is called and just before + * the initial application is started. This additional initialization + * phase may be used, for example, to initialize board-specific device + * drivers. + * + ****************************************************************************/ + +#ifdef CONFIG_BOARD_LATE_INITIALIZE +void board_late_initialize(void) +{ +} +#endif diff --git a/boards/arm/stm32f1/fire-stm32v2/CMakeLists.txt b/boards/arm/stm32f1/fire-stm32v2/CMakeLists.txt new file mode 100644 index 0000000000000..aaab83b6d0dcc --- /dev/null +++ b/boards/arm/stm32f1/fire-stm32v2/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32f1/fire-stm32v2/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/arm/stm32/fire-stm32v2/Kconfig b/boards/arm/stm32f1/fire-stm32v2/Kconfig similarity index 100% rename from boards/arm/stm32/fire-stm32v2/Kconfig rename to boards/arm/stm32f1/fire-stm32v2/Kconfig diff --git a/boards/arm/stm32f1/fire-stm32v2/configs/nsh/defconfig b/boards/arm/stm32f1/fire-stm32v2/configs/nsh/defconfig new file mode 100644 index 0000000000000..a310a44055529 --- /dev/null +++ b/boards/arm/stm32f1/fire-stm32v2/configs/nsh/defconfig @@ -0,0 +1,89 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_MMCSD_HAVE_CARDDETECT is not set +# CONFIG_MMCSD_MMCSUPPORT is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_SPI_CALLBACK is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="fire-stm32v2" +CONFIG_ARCH_BOARD_FIRE_STM32=y +CONFIG_ARCH_CHIP="stm32f1" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F103VE=y +CONFIG_ARCH_CHIP_STM32F1=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=5483 +CONFIG_BUILTIN=y +CONFIG_ENC28J60=y +CONFIG_FAT_LCNAMES=y +CONFIG_FAT_LFN=y +CONFIG_FS_FAT=y +CONFIG_HOST_WINDOWS=y +CONFIG_I2C=y +CONFIG_I2CTOOL_DEFFREQ=100000 +CONFIG_I2CTOOL_MAXBUS=2 +CONFIG_I2CTOOL_MINBUS=1 +CONFIG_I2C_POLLED=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_MMCSD=y +CONFIG_MMCSD_SDIO=y +CONFIG_NET=y +CONFIG_NETDB_DNSCLIENT=y +CONFIG_NETDB_DNSSERVER_NOADDR=y +CONFIG_NETINIT_NOMAC=y +CONFIG_NETUTILS_TELNETD=y +CONFIG_NETUTILS_TFTPC=y +CONFIG_NETUTILS_WEBCLIENT=y +CONFIG_NET_BROADCAST=y +CONFIG_NET_ICMP_SOCKET=y +CONFIG_NET_MAX_LISTENPORTS=16 +CONFIG_NET_STATISTICS=y +CONFIG_NET_TCP=y +CONFIG_NET_TCP_PREALLOC_CONNS=16 +CONFIG_NET_UDP=y +CONFIG_NET_UDP_CHECKSUMS=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_RAM_SIZE=65536 +CONFIG_RAM_START=0x20000000 +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=192 +CONFIG_SCHED_HPWORKSTACKSIZE=1024 +CONFIG_SCHED_WAITPID=y +CONFIG_STM32_BKP=y +CONFIG_STM32_DMA2=y +CONFIG_STM32_I2C1=y +CONFIG_STM32_JTAG_FULL_ENABLE=y +CONFIG_STM32_PWR=y +CONFIG_STM32_RTC=y +CONFIG_STM32_SDIO=y +CONFIG_STM32_SPI1=y +CONFIG_STM32_USART1=y +CONFIG_STM32_USART2=y +CONFIG_STM32_USB=y +CONFIG_SYSTEM_I2CTOOL=y +CONFIG_SYSTEM_NSH=y +CONFIG_SYSTEM_PING=y +CONFIG_SYSTEM_USBMSC=y +CONFIG_SYSTEM_USBMSC_DEVMINOR1=0 +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART1_SERIAL_CONSOLE=y +CONFIG_USBMSC=y +CONFIG_USBMSC_BULKINREQLEN=256 +CONFIG_USBMSC_BULKOUTREQLEN=256 +CONFIG_USBMSC_EPBULKIN=5 +CONFIG_USBMSC_NRDREQS=2 +CONFIG_USBMSC_NWRREQS=2 +CONFIG_USBMSC_PRODUCTSTR="USBdev Storage" +CONFIG_USBMSC_REMOVABLE=y +CONFIG_USBMSC_VERSIONNO=0x0399 diff --git a/boards/arm/stm32f1/fire-stm32v2/include/board.h b/boards/arm/stm32f1/fire-stm32v2/include/board.h new file mode 100644 index 0000000000000..27e228b92572c --- /dev/null +++ b/boards/arm/stm32f1/fire-stm32v2/include/board.h @@ -0,0 +1,451 @@ +/**************************************************************************** + * boards/arm/stm32f1/fire-stm32v2/include/board.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_STM32_FIRE_STM32V2_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32_FIRE_STM32V2_INCLUDE_BOARD_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#ifndef __ASSEMBLY__ +# include +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Clocking *****************************************************************/ + +/* HSI - 8 MHz RC factory-trimmed + * LSI - 40 KHz RC (30-60KHz, uncalibrated) + * HSE - On-board crystal frequency is 8MHz + * LSE - 32.768 kHz crytal + */ + +#define STM32_BOARD_XTAL 8000000ul + +#define STM32_HSI_FREQUENCY 8000000ul +#define STM32_LSI_FREQUENCY 40000 +#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL +#define STM32_LSE_FREQUENCY 32768 + +/* PLL source is HSE/1, + * PLL multiplier is 9: + * PLL frequency is 8MHz (XTAL) x 9 = 72MHz + */ + +#define STM32_CFGR_PLLSRC RCC_CFGR_PLLSRC +#define STM32_CFGR_PLLXTPRE 0 +#define STM32_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx9 +#define STM32_PLL_FREQUENCY (9*STM32_BOARD_XTAL) + +/* Use the PLL and set the SYSCLK source to be the PLL */ + +#define STM32_SYSCLK_SW RCC_CFGR_SW_PLL +#define STM32_SYSCLK_SWS RCC_CFGR_SWS_PLL +#define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY + +/* AHB clock (HCLK) is SYSCLK (72MHz) */ + +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK +#define STM32_HCLK_FREQUENCY STM32_PLL_FREQUENCY + +/* APB2 clock (PCLK2) is HCLK (72MHz) */ + +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK +#define STM32_PCLK2_FREQUENCY STM32_HCLK_FREQUENCY +#define STM32_APB2_CLKIN (STM32_PCLK2_FREQUENCY) /* Timers 2-7, 12-14 */ + +/* APB2 timers 1 and 8 will receive PCLK2. */ + +#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) + +/* APB1 clock (PCLK1) is HCLK/2 (36MHz) */ + +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd2 +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/2) + +/* APB1 timers 2-7 will be twice PCLK1 */ + +#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) + +/* USB divider -- Divide PLL clock by 1.5 */ + +#define STM32_CFGR_USBPRE 0 + +/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx + * otherwise frequency is 2xAPBx. + * Note: TIM1,8 are on APB2, others on APB1 + */ + +#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM2_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM3_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM4_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM5_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM6_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM7_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY + +/* SDIO dividers. Note that slower clocking is required when DMA is disabled + * in order to avoid RX overrun/TX underrun errors due to delayed responses + * to service FIFOs in interrupt driven mode. These values have not been + * tuned!!! + * + * HCLK=72MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(178+2)=400 KHz + */ + +#define SDIO_INIT_CLKDIV (178 << SDIO_CLKCR_CLKDIV_SHIFT) + +/* DMA ON: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(2+2)=18 MHz + * DMA OFF: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(3+2)=14.4 MHz + */ + +#ifdef CONFIG_STM32_SDIO_DMA +# define SDIO_MMCXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT) +#else +# define SDIO_MMCXFR_CLKDIV (3 << SDIO_CLKCR_CLKDIV_SHIFT) +#endif + +/* DMA ON: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(1+2)=24 MHz + * DMA OFF: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(3+2)=14.4 MHz + */ + +#ifdef CONFIG_STM32_SDIO_DMA +# define SDIO_SDXFR_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT) +#else +# define SDIO_SDXFR_CLKDIV (3 << SDIO_CLKCR_CLKDIV_SHIFT) +#endif + +/* LED definitions **********************************************************/ + +/* The M3 Wildfire has 3 LEDs labeled LED1, LED2 and LED3. + * These LEDs are not used by the NuttX port unless CONFIG_ARCH_LEDS is + * defined. In that case, the usage by the board port is defined in + * include/board.h and src/up_autoleds.c. + * The LEDs are used to encode OS-related events as follows: + */ + + /* LED1 LED2 LED3 */ +#define LED_STARTED 0 /* OFF OFF OFF */ +#define LED_HEAPALLOCATE 1 /* ON OFF OFF */ +#define LED_IRQSENABLED 2 /* OFF ON OFF */ +#define LED_STACKCREATED 3 /* OFF OFF OFF */ + +#define LED_INIRQ 4 /* NC NC ON (momentary) */ +#define LED_SIGNAL 4 /* NC NC ON (momentary) */ +#define LED_ASSERTION 4 /* NC NC ON (momentary) */ +#define LED_PANIC 4 /* NC NC ON (2Hz flashing) */ +#undef LED_IDLE /* Sleep mode indication not supported */ + +/* The M3 Wildfire supports several two user buttons: KEY1 and KEY2 */ + +#define BUTTON_KEY1 0 +#define BUTTON_KEY2 1 +#define NUM_BUTTONS 2 + +#define BUTTON_KEY1_BIT (1 << BUTTON_KEY1) +#define BUTTON_KEY2_BIT (1 << BUTTON_KEY2) + +/* Pin Remapping ************************************************************/ + +/* USB 2.0 + * + * --- ------ -------------- ------------------------------------------------ + * PIN NAME SIGNAL NOTES + * --- ------ -------------- ------------------------------------------------ + * + * 70 PA11 PA11-USBDM USB2.0 + * 71 PA12 PA12-USBDP USB2.0 + * 2 PE3 PE3-USB-M USB2.0 + */ + +/* 2.4" TFT + Touchscreen + * + * --- ------ -------------- ------------------------------------------------ + * PIN NAME SIGNAL NOTES + * --- ------ -------------- ------------------------------------------------ + * + * 30 PA5 PA5-SPI1-SCK 2.4" TFT + Touchscreen, 10Mbit ENC28J60, + * SPI 2M FLASH + * 31 PA6 PA6-SPI1-MISO 2.4" TFT + Touchscreen, 10Mbit ENC28J60, + * SPI 2M FLASH + * 32 PA7 PA7-SPI1-MOSI 2.4" TFT + Touchscreen, 10Mbit ENC28J60, + * SPI 2M FLASH + * 92 PB6 PB6-I2C1-SCL 2.4" TFT + Touchscreen, AT24C02 + * 93 PB7 PB7-I2C1-SDA 2.4" TFT + Touchscreen, AT24C02 + * 81 PD0 PD0-FSMC_D2 2.4" TFT + Touchscreen + * 82 PD1 PD1-FSMC_D3 2.4" TFT + Touchscreen + * 85 PD4 PD4-FSMC_NOE 2.4" TFT + Touchscreen + * 86 PD5 PD5-FSMC_NWE 2.4" TFT + Touchscreen + * 88 PD7 PD7-FSMC_NE1 2.4" TFT + Touchscreen + * 55 PD8 PD8-FSMC_D13 2.4" TFT + Touchscreen + * 56 PD9 PD9-FSMC_D14 2.4" TFT + Touchscreen + * 57 PD10 PD10-FSMC_D15 2.4" TFT + Touchscreen + * 58 PD11 PD11-FSMC_A16 2.4" TFT + Touchscreen + * 60 PD13 PD13-LCD/LIGHT 2.4" TFT + Touchscreen + * 61 PD14 PD14-FSMC_D0 2.4" TFT + Touchscreen + * 62 PD15 PD15-FSMC_D1 2.4" TFT + Touchscreen + * 98 PE1 PE1-FSMC_NBL1 2.4" TFT + Touchscreen, 10Mbit EN28J60 Reset + * 38 PE7 PE7-FSMC_D4 2.4" TFT + Touchscreen + * 39 PE8 PE8-FSMC_D5 2.4" TFT + Touchscreen + * 40 PE9 PE9-FSMC_D6 2.4" TFT + Touchscreen + * 41 PE10 PE10-FSMC_D7 2.4" TFT + Touchscreen + * 42 PE11 PE11-FSMC_D8 2.4" TFT + Touchscreen + * 43 PE12 PE12-FSMC_D9 2.4" TFT + Touchscreen + * 44 PE13 PE13-FSMC_D10 2.4" TFT + Touchscreen + * 45 PE14 PE14-FSMC_D11 2.4" TFT + Touchscreen + * 46 PE15 PE15-FSMC_D12 2.4" TFT + Touchscreen + */ + +#if defined(CONFIG_STM32_SPI1) && defined(CONFIG_STM32_SPI1_REMAP) +# error "SPI1 requires CONFIG_STM32_SPI1_REMAP=n" +#endif + +#if defined(CONFIG_STM32_I2C1) && defined(CONFIG_STM32_I2C1_REMAP) +# error "SPI1 requires CONFIG_STM32_I2C1_REMAP=n" +#endif + +/* AT24C02 + * + * --- ------ -------------- ------------------------------------------------ + * PIN NAME SIGNAL NOTES + * --- ------ -------------- ------------------------------------------------ + * + * 92 PB6 PB6-I2C1-SCL 2.4" TFT + Touchscreen, AT24C02 + * 93 PB7 PB7-I2C1-SDA 2.4" TFT + Touchscreen, AT24C02 + */ + +#if defined(CONFIG_STM32_I2C1) && defined(CONFIG_STM32_I2C1_REMAP) +# error "SPI1 requires CONFIG_STM32_I2C1_REMAP=n" +#endif + +/* Potentiometer/ADC + * + * --- ------ -------------- ------------------------------------------------ + * PIN NAME SIGNAL NOTES + * --- ------ -------------- ------------------------------------------------ + * + * 16 PC1 PC1/ADC123-IN11 Potentiometer (R16) + * 24 PA1 PC1/ADC123-IN1 + */ + +/* USARTs + * + * --- ------ -------------- ------------------------------------------------ + * PIN NAME SIGNAL NOTES + * --- ------ -------------- ------------------------------------------------ + * + * 68 PA9 PA9-US1-TX MAX3232, DB9 D8, + * Requires !CONFIG_STM32_USART1_REMAP + * 69 PA10 PA10-US1-RX MAX3232, DB9 D8, + * Requires !CONFIG_STM32_USART1_REMAP + * 25 PA2 PA2-US2-TX MAX3232, DB9 D7, + * Requires !CONFIG_STM32_USART2_REMAP + * 26 PA3 PA3-US2-RX MAX3232, DB9 D7, + * Requires !CONFIG_STM32_USART2_REMAP + */ + +#if defined(CONFIG_STM32_USART1) && defined(CONFIG_STM32_USART1_REMAP) +# error "USART1 requires CONFIG_STM32_USART1_REMAP=n" +#endif + +#if defined(CONFIG_STM32_USART2) && defined(CONFIG_STM32_USART2_REMAP) +# error "USART2 requires CONFIG_STM32_USART2_REMAP=n" +#endif + +/* 2MBit SPI FLASH + * + * --- ------ -------------- ------------------------------------------------ + * PIN NAME SIGNAL NOTES + * --- ------ -------------- ------------------------------------------------ + * + * 29 PA4 PA4-SPI1-NSS 10Mbit ENC28J60, SPI 2M FLASH + * 30 PA5 PA5-SPI1-SCK 2.4" TFT + Touchscreen, 10Mbit ENC28J60, + * SPI 2M FLASH + * 31 PA6 PA6-SPI1-MISO 2.4" TFT + Touchscreen, 10Mbit ENC28J60, + * SPI 2M FLASH + * 32 PA7 PA7-SPI1-MOSI 2.4" TFT + Touchscreen, 10Mbit ENC28J60, + * SPI 2M FLASH + */ + +#if defined(CONFIG_STM32_SPI1) && defined(CONFIG_STM32_SPI1_REMAP) +# error "SPI1 requires CONFIG_STM32_SPI1_REMAP=n" +#endif + +/* ENC28J60 + * + * --- ------ -------------- ------------------------------------------------ + * PIN NAME SIGNAL NOTES + * --- ------ -------------- ------------------------------------------------ + * + * 29 PA4 PA4-SPI1-NSS 10Mbit ENC28J60, SPI 2M FLASH + * 30 PA5 PA5-SPI1-SCK 2.4" TFT + Touchscreen, 10Mbit ENC28J60, + * SPI 2M FLASH + * 31 PA6 PA6-SPI1-MISO 2.4" TFT + Touchscreen, 10Mbit ENC28J60, + * SPI 2M FLASH + * 32 PA7 PA7-SPI1-MOSI 2.4" TFT + Touchscreen, 10Mbit ENC28J60, + * SPI 2M FLASH + * 98 PE1 PE1-FSMC_NBL1 2.4" TFT + Touchscreen, 10Mbit EN28J60 Reset + * 4 PE5 (no name) 10Mbps ENC28J60 Interrupt + */ + +#if defined(CONFIG_STM32_SPI1) && defined(CONFIG_STM32_SPI1_REMAP) +# error "SPI1 requires CONFIG_STM32_SPI1_REMAP=n" +#endif + +/* MP3 + * + * --- ------ -------------- ------------------------------------------------ + * PIN NAME SIGNAL NOTES + * --- ------ -------------- ------------------------------------------------ + * + * 48 PB11 PB11-MP3-RST MP3 + * 51 PB12 PB12-SPI2-NSS MP3 + * 52 PB13 PB13-SPI2-SCK MP3 + * 53 PB14 PB14-SPI2-MISO MP3 + * 54 PB15 PB15-SPI2-MOSI MP3 + * 63 PC6 PC6-MP3-XDCS MP3 + * 64 PC7 PC7-MP3-DREQ MP3 + */ + +/* SD Card + * + * --- ------ -------------- ------------------------------------------------ + * PIN NAME SIGNAL NOTES + * --- ------ -------------- ------------------------------------------------ + * + * 65 PC8 PC8-SDIO-D0 SD card, pulled high + * 66 PC9 PC9-SDIO-D1 SD card, pulled high + * 78 PC10 PC10-SDIO-D2 SD card, pulled high + * 79 PC11 PC10-SDIO-D3 SD card, pulled high + * 80 PC12 PC12-SDIO-CLK SD card + * 83 PD2 PD2-SDIO-CMD SD card, pulled high + */ + +/* CAN + * + * --- ------ -------------- ------------------------------------------------ + * PIN NAME SIGNAL NOTES + * --- ------ -------------- ------------------------------------------------ + * + * 95 PB8 PB8-CAN-RX CAN transceiver, Header 2H + * 96 PB9 PB9-CAN-TX CAN transceiver, Header 2H + */ + +#if defined(CONFIG_STM32_CAN1) && !defined(CONFIG_STM32_CAN1_REMAP1) +# error "SPI1 requires CONFIG_STM32_CAN1_REMAP1=y" +#endif + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: fire_lcdclear + * + * Description: + * This is a non-standard LCD interface just for the M3 Wildfire board. + * Because of the various rotations, clearing the display in the normal + * way by writing a sequences of runs that covers the entire display can be + * very slow. Here the display is cleared by simply setting all GRAM + * memory to the specified color. + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_FSMC +void fire_lcdclear(uint16_t color); +#endif + +#if defined(__cplusplus) +} +#endif +#undef EXTERN + +#endif /* __ASSEMBLY__ */ + +/* Alternate function pin selections (auto-aliased for new pinmap) */ + +/* USART1 */ + +#define GPIO_USART1_TX GPIO_ADJUST_MODE(GPIO_USART1_TX_0, GPIO_MODE_50MHz) +#define GPIO_USART1_RX GPIO_USART1_RX_0 + +/* USART2 */ + +#define GPIO_USART2_TX GPIO_ADJUST_MODE(GPIO_USART2_TX_0, GPIO_MODE_50MHz) +#define GPIO_USART2_RX GPIO_USART2_RX_0 +#define GPIO_USART2_CTS GPIO_USART2_CTS_0 +#define GPIO_USART2_RTS GPIO_ADJUST_MODE(GPIO_USART2_RTS_0, GPIO_MODE_50MHz) +#define GPIO_USART2_CK GPIO_ADJUST_MODE(GPIO_USART2_CK_0, GPIO_MODE_50MHz) + +/* SPI1 */ + +#define GPIO_SPI1_NSS GPIO_ADJUST_MODE(GPIO_SPI1_NSS_0, GPIO_MODE_50MHz) +#define GPIO_SPI1_SCK GPIO_ADJUST_MODE(GPIO_SPI1_SCK_0, GPIO_MODE_50MHz) +#define GPIO_SPI1_MISO GPIO_ADJUST_MODE(GPIO_SPI1_MISO_0, GPIO_MODE_50MHz) +#define GPIO_SPI1_MOSI GPIO_ADJUST_MODE(GPIO_SPI1_MOSI_0, GPIO_MODE_50MHz) + +/* I2C1 */ + +#define GPIO_I2C1_SCL GPIO_ADJUST_MODE(GPIO_I2C1_SCL_0, GPIO_MODE_50MHz) +#define GPIO_I2C1_SDA GPIO_ADJUST_MODE(GPIO_I2C1_SDA_0, GPIO_MODE_50MHz) + +/* SDIO */ + +#define GPIO_SDIO_CK GPIO_ADJUST_MODE(GPIO_SDIO_CK_0, GPIO_MODE_50MHz) +#define GPIO_SDIO_CMD GPIO_ADJUST_MODE(GPIO_SDIO_CMD_0, GPIO_MODE_50MHz) +#define GPIO_SDIO_D0 GPIO_ADJUST_MODE(GPIO_SDIO_D0_0, GPIO_MODE_50MHz) +#define GPIO_SDIO_D1 GPIO_ADJUST_MODE(GPIO_SDIO_D1_0, GPIO_MODE_50MHz) +#define GPIO_SDIO_D2 GPIO_ADJUST_MODE(GPIO_SDIO_D2_0, GPIO_MODE_50MHz) +#define GPIO_SDIO_D3 GPIO_ADJUST_MODE(GPIO_SDIO_D3_0, GPIO_MODE_50MHz) + +/* USB */ + +#define GPIO_USB_DM GPIO_USB_DM_0 +#define GPIO_USB_DP GPIO_USB_DP_0 + +#endif /* __BOARDS_ARM_STM32_FIRE_STM32V2_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32f1/fire-stm32v2/scripts/Make.defs b/boards/arm/stm32f1/fire-stm32v2/scripts/Make.defs new file mode 100644 index 0000000000000..82ac28f1b37d3 --- /dev/null +++ b/boards/arm/stm32f1/fire-stm32v2/scripts/Make.defs @@ -0,0 +1,48 @@ +############################################################################ +# boards/arm/stm32f1/fire-stm32v2/scripts/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/.config +include $(TOPDIR)/tools/Config.mk +include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs + +# Pick the linker script + +ifeq ($(CONFIG_STM32_DFU),y) + LDSCRIPT = fire-stm32v2-dfu.ld +else + LDSCRIPT = fire-stm32v2.ld +endif + +ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) + +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32/fire-stm32v2/scripts/fire-stm32v2-dfu.ld b/boards/arm/stm32f1/fire-stm32v2/scripts/fire-stm32v2-dfu.ld similarity index 98% rename from boards/arm/stm32/fire-stm32v2/scripts/fire-stm32v2-dfu.ld rename to boards/arm/stm32f1/fire-stm32v2/scripts/fire-stm32v2-dfu.ld index 98e7d8a77d353..32ac24c4ef2f9 100644 --- a/boards/arm/stm32/fire-stm32v2/scripts/fire-stm32v2-dfu.ld +++ b/boards/arm/stm32f1/fire-stm32v2/scripts/fire-stm32v2-dfu.ld @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/fire-stm32v2/scripts/fire-stm32v2-dfu.ld + * boards/arm/stm32f1/fire-stm32v2/scripts/fire-stm32v2-dfu.ld * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/fire-stm32v2/scripts/fire-stm32v2.ld b/boards/arm/stm32f1/fire-stm32v2/scripts/fire-stm32v2.ld similarity index 98% rename from boards/arm/stm32/fire-stm32v2/scripts/fire-stm32v2.ld rename to boards/arm/stm32f1/fire-stm32v2/scripts/fire-stm32v2.ld index d9e527a239cbe..64ee682f7b682 100644 --- a/boards/arm/stm32/fire-stm32v2/scripts/fire-stm32v2.ld +++ b/boards/arm/stm32f1/fire-stm32v2/scripts/fire-stm32v2.ld @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/fire-stm32v2/scripts/fire-stm32v2.ld + * boards/arm/stm32f1/fire-stm32v2/scripts/fire-stm32v2.ld * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f1/fire-stm32v2/src/CMakeLists.txt b/boards/arm/stm32f1/fire-stm32v2/src/CMakeLists.txt new file mode 100644 index 0000000000000..a589de40419b0 --- /dev/null +++ b/boards/arm/stm32f1/fire-stm32v2/src/CMakeLists.txt @@ -0,0 +1,59 @@ +# ############################################################################## +# boards/arm/stm32f1/fire-stm32v2/src/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(SRCS stm32_boot.c stm32_spi.c stm32_usbdev.c stm32_mmcsd.c) + +if(CONFIG_STM32_FSMC) + list(APPEND SRCS stm32_lcd.c stm32_selectlcd.c) +endif() + +if(CONFIG_ARCH_LEDS) + list(APPEND SRCS stm32_autoleds.c) +else() + list(APPEND SRCS stm32_userleds.c) +endif() + +if(CONFIG_ARCH_BUTTONS) + list(APPEND SRCS stm32_buttons.c) +endif() + +if(CONFIG_ENC28J60) + list(APPEND SRCS stm32_enc28j60.c) +endif() + +if(CONFIG_MTD_W25) + list(APPEND SRCS stm32_w25.c) +endif() + +if(CONFIG_USBMSC) + list(APPEND SRCS stm32_usbmsc.c) +endif() + +target_sources(board PRIVATE ${SRCS}) + +if(CONFIG_STM32_DFU) + set_property(GLOBAL PROPERTY LD_SCRIPT + "${NUTTX_BOARD_DIR}/scripts/fire-stm32v2-dfu.ld") +else() + set_property(GLOBAL PROPERTY LD_SCRIPT + "${NUTTX_BOARD_DIR}/scripts/fire-stm32v2.ld") +endif() diff --git a/boards/arm/stm32f1/fire-stm32v2/src/Make.defs b/boards/arm/stm32f1/fire-stm32v2/src/Make.defs new file mode 100644 index 0000000000000..741b5125d192f --- /dev/null +++ b/boards/arm/stm32f1/fire-stm32v2/src/Make.defs @@ -0,0 +1,55 @@ +############################################################################ +# boards/arm/stm32f1/fire-stm32v2/src/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +CSRCS = stm32_boot.c stm32_spi.c stm32_usbdev.c stm32_mmcsd.c + +ifeq ($(CONFIG_STM32_FSMC),y) +CSRCS += stm32_lcd.c stm32_selectlcd.c +endif + +ifeq ($(CONFIG_ARCH_LEDS),y) +CSRCS += stm32_autoleds.c +else +CSRCS += stm32_userleds.c +endif + +ifeq ($(CONFIG_ARCH_BUTTONS),y) +CSRCS += stm32_buttons.c +endif + +ifeq ($(CONFIG_ENC28J60),y) +CSRCS += stm32_enc28j60.c +endif + +ifeq ($(CONFIG_MTD_W25),y) +CSRCS += stm32_w25.c +endif + +ifeq ($(CONFIG_USBMSC),y) +CSRCS += stm32_usbmsc.c +endif + +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/fire-stm32v2/src/fire-stm32v2.h b/boards/arm/stm32f1/fire-stm32v2/src/fire-stm32v2.h similarity index 99% rename from boards/arm/stm32/fire-stm32v2/src/fire-stm32v2.h rename to boards/arm/stm32f1/fire-stm32v2/src/fire-stm32v2.h index 7bfd672d81e86..8b6606826eec3 100644 --- a/boards/arm/stm32/fire-stm32v2/src/fire-stm32v2.h +++ b/boards/arm/stm32f1/fire-stm32v2/src/fire-stm32v2.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/fire-stm32v2/src/fire-stm32v2.h + * boards/arm/stm32f1/fire-stm32v2/src/fire-stm32v2.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f1/fire-stm32v2/src/stm32_autoleds.c b/boards/arm/stm32f1/fire-stm32v2/src/stm32_autoleds.c new file mode 100644 index 0000000000000..74380388b5092 --- /dev/null +++ b/boards/arm/stm32f1/fire-stm32v2/src/stm32_autoleds.c @@ -0,0 +1,359 @@ +/**************************************************************************** + * boards/arm/stm32f1/fire-stm32v2/src/stm32_autoleds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32.h" +#include "fire-stm32v2.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* The following definitions map the encoded LED setting to GPIO settings. + * + * OFFBITS ONBITS + * CLR SET CLR SET + * 210 210 210 210 + */ + +#define FIRE_LED1 (1 << 0) +#define FIRE_LED2 (1 << 1) +#define FIRE_LED3 (1 << 2) + +#define ON_SETBITS_SHIFT (0) +#define ON_CLRBITS_SHIFT (3) +#define OFF_SETBITS_SHIFT (6) +#define OFF_CLRBITS_SHIFT (9) + +#define ON_BITS(v) ((v) & 0x3f) +#define OFF_BITS(v) (((v) >> 6) & 0x03f) +#define SETBITS(b) ((b) & 0x07) +#define CLRBITS(b) (((b) >> 3) & 0x07) + +#define ON_SETBITS(v) (SETBITS(ON_BITS(v)) +#define ON_CLRBITS(v) (CLRBITS(ON_BITS(v)) +#define OFF_SETBITS(v) (SETBITS(OFF_BITS(v)) +#define OFF_CLRBITS(v) (CLRBITS(OFF_BITS(v)) + +/* ON OFF + * -------------------------- -- ------------------ ----------------- + * LED1 LED2 LED3 LED1 LED2 LED3 + * -------------------------- -- ------ ----- ----- ----- ----- ----- + * LED_STARTED 0 OFF OFF OFF OFF OFF OFF + * LED_HEAPALLOCATE 1 ON OFF OFF OFF OFF OFF + * LED_IRQSENABLED 2 OFF ON OFF ON OFF OFF + * LED_STACKCREATED 3 OFF OFF OFF OFF ON OFF + * + * LED_INIRQ 4 NC NC ON NC NC OFF + * LED_SIGNAL 4 NC NC ON NC NC OFF + * LED_ASSERTION 4 NC NC ON NC NC OFF + * LED_PANIC 4 NC NC ON NC NC OFF + * -------------------------- -- ------ ----- ----- ----- ----- ----- + */ + +#define LED_STARTED_ON_SETBITS (0) +#define LED_STARTED_ON_CLRBITS ((FIRE_LED1|FIRE_LED2|FIRE_LED3) << ON_CLRBITS_SHIFT) +#define LED_STARTED_OFF_SETBITS (0) +#define LED_STARTED_OFF_CLRBITS ((FIRE_LED1|FIRE_LED2|FIRE_LED3) << OFF_CLRBITS_SHIFT) + +#define LED_HEAPALLOCATE_ON_SETBITS ((FIRE_LED1) << ON_SETBITS_SHIFT) +#define LED_HEAPALLOCATE_ON_CLRBITS ((FIRE_LED2|FIRE_LED3) << ON_CLRBITS_SHIFT) +#define LED_HEAPALLOCATE_OFF_SETBITS (0) +#define LED_HEAPALLOCATE_OFF_CLRBITS ((FIRE_LED1|FIRE_LED2|FIRE_LED3) << OFF_CLRBITS_SHIFT) + +#define LED_IRQSENABLED_ON_SETBITS ((FIRE_LED2) << ON_SETBITS_SHIFT) +#define LED_IRQSENABLED_ON_CLRBITS ((FIRE_LED1|FIRE_LED3) << ON_CLRBITS_SHIFT) +#define LED_IRQSENABLED_OFF_SETBITS ((FIRE_LED1) << OFF_SETBITS_SHIFT) +#define LED_IRQSENABLED_OFF_CLRBITS ((FIRE_LED1|FIRE_LED2|FIRE_LED3) << OFF_CLRBITS_SHIFT) + +#define LED_STACKCREATED_ON_SETBITS (0) +#define LED_STACKCREATED_ON_CLRBITS ((FIRE_LED1|FIRE_LED2|FIRE_LED3) << ON_CLRBITS_SHIFT) +#define LED_STACKCREATED_OFF_SETBITS ((FIRE_LED2) << OFF_SETBITS_SHIFT) +#define LED_STACKCREATED_OFF_CLRBITS ((FIRE_LED1|FIRE_LED3) << OFF_CLRBITS_SHIFT) + +#define LED_FLASH_ON_SETBITS ((FIRE_LED3) << ON_SETBITS_SHIFT) +#define LED_FLASH_ON_CLRBITS ((0) << ON_CLRBITS_SHIFT) +#define LED_FLASH_OFF_SETBITS ((0) << OFF_SETBITS_SHIFT) +#define LED_FLASH_OFF_CLRBITS ((FIRE_LED3) << OFF_CLRBITS_SHIFT) + +/**************************************************************************** + * Private Function Protototypes + ****************************************************************************/ + +/* LED State Controls */ + +static inline void led_clrbits(unsigned int clrbits); +static inline void led_setbits(unsigned int setbits); +static void led_setonoff(unsigned int bits); + +/* LED Power Management */ + +#ifdef CONFIG_PM +static void led_pm_notify(struct pm_callback_s *cb, int domain, + enum pm_state_e pmstate); +static int led_pm_prepare(struct pm_callback_s *cb, int domain, + enum pm_state_e pmstate); +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static const uint16_t g_ledbits[8] = +{ + (LED_STARTED_ON_SETBITS | LED_STARTED_ON_CLRBITS | + LED_STARTED_OFF_SETBITS | LED_STARTED_OFF_CLRBITS), + + (LED_HEAPALLOCATE_ON_SETBITS | LED_HEAPALLOCATE_ON_CLRBITS | + LED_HEAPALLOCATE_OFF_SETBITS | LED_HEAPALLOCATE_OFF_CLRBITS), + + (LED_IRQSENABLED_ON_SETBITS | LED_IRQSENABLED_ON_CLRBITS | + LED_IRQSENABLED_OFF_SETBITS | LED_IRQSENABLED_OFF_CLRBITS), + + (LED_STACKCREATED_ON_SETBITS | LED_STACKCREATED_ON_CLRBITS | + LED_STACKCREATED_OFF_SETBITS | LED_STACKCREATED_OFF_CLRBITS), + + (LED_FLASH_ON_SETBITS | LED_FLASH_ON_CLRBITS | + LED_FLASH_OFF_SETBITS | LED_FLASH_OFF_CLRBITS) +}; + +#ifdef CONFIG_PM +static struct pm_callback_s g_ledscb = +{ + .notify = led_pm_notify, + .prepare = led_pm_prepare, +}; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: led_clrbits + * + * Description: + * Clear all LEDs to the bit encoded state. The LEDs are pulled up and, + * hence, active low. + * + ****************************************************************************/ + +static inline void led_clrbits(unsigned int clrbits) +{ + if ((clrbits & FIRE_LED1) != 0) + { + stm32_gpiowrite(GPIO_LED1, true); + } + + if ((clrbits & FIRE_LED2) != 0) + { + stm32_gpiowrite(GPIO_LED2, true); + } + + if ((clrbits & FIRE_LED3) != 0) + { + stm32_gpiowrite(GPIO_LED3, true); + } +} + +/**************************************************************************** + * Name: led_setbits + * + * Description: + * Set all LEDs to the bit encoded state. The LEDs are pulled up and, + * hence, active low. + * + ****************************************************************************/ + +static inline void led_setbits(unsigned int setbits) +{ + if ((setbits & FIRE_LED1) != 0) + { + stm32_gpiowrite(GPIO_LED1, false); + } + + if ((setbits & FIRE_LED2) != 0) + { + stm32_gpiowrite(GPIO_LED2, false); + } + + if ((setbits & FIRE_LED3) != 0) + { + stm32_gpiowrite(GPIO_LED3, false); + } +} + +/**************************************************************************** + * Name: led_setonoff + * + * Description: + * Set/clear all LEDs to the bit encoded state + * + ****************************************************************************/ + +static void led_setonoff(unsigned int bits) +{ + led_clrbits(CLRBITS(bits)); + led_setbits(SETBITS(bits)); +} + +/**************************************************************************** + * Name: led_pm_notify + * + * Description: + * Notify the driver of new power state. This callback is called after + * all drivers have had the opportunity to prepare for the new power state. + * + ****************************************************************************/ + +#ifdef CONFIG_PM +static void led_pm_notify(struct pm_callback_s *cb, int domain, + enum pm_state_e pmstate) +{ + switch (pmstate) + { + case PM_NORMAL: + { + /* Restore normal LEDs operation */ + } + break; + + case PM_IDLE: + { + /* Entering IDLE mode - Turn leds off */ + } + break; + + case PM_STANDBY: + { + /* Entering STANDBY mode - Logic for PM_STANDBY goes here */ + } + break; + + case PM_SLEEP: + { + /* Entering SLEEP mode - Logic for PM_SLEEP goes here */ + } + break; + + default: + { + /* Should not get here */ + } + break; + } +} +#endif + +/**************************************************************************** + * Name: led_pm_prepare + * + * Description: + * Request the driver to prepare for a new power state. This is a warning + * that the system is about to enter into a new power state. The driver + * should begin whatever operations that may be required to enter power + * state. The driver may abort the state change mode by returning a + * non-zero value from the callback function. + * + ****************************************************************************/ + +#ifdef CONFIG_PM +static int led_pm_prepare(struct pm_callback_s *cb, int domain, + enum pm_state_e pmstate) +{ + /* No preparation to change power modes is required by the LEDs driver. + * We always accept the state change by returning OK. + */ + + return OK; +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_autoled_initialize + ****************************************************************************/ + +#ifdef CONFIG_ARCH_LEDS +void board_autoled_initialize(void) +{ + /* Configure LED1-4 GPIOs for output */ + + stm32_configgpio(GPIO_LED1); + stm32_configgpio(GPIO_LED2); + stm32_configgpio(GPIO_LED3); +} + +/**************************************************************************** + * Name: board_autoled_on + ****************************************************************************/ + +void board_autoled_on(int led) +{ + led_setonoff(ON_BITS(g_ledbits[led])); +} + +/**************************************************************************** + * Name: board_autoled_off + ****************************************************************************/ + +void board_autoled_off(int led) +{ + led_setonoff(OFF_BITS(g_ledbits[led])); +} + +/**************************************************************************** + * Name: up_ledpminitialize + ****************************************************************************/ + +#ifdef CONFIG_PM +void up_ledpminitialize(void) +{ + /* Register to receive power management callbacks */ + + int ret = pm_register(&g_ledscb); + if (ret != OK) + { + board_autoled_on(LED_ASSERTION); + } +} +#endif /* CONFIG_PM */ + +#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32f1/fire-stm32v2/src/stm32_boot.c b/boards/arm/stm32f1/fire-stm32v2/src/stm32_boot.c new file mode 100644 index 0000000000000..0ab15a7fc136c --- /dev/null +++ b/boards/arm/stm32f1/fire-stm32v2/src/stm32_boot.c @@ -0,0 +1,277 @@ +/**************************************************************************** + * boards/arm/stm32f1/fire-stm32v2/src/stm32_boot.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include +#include +#include + +#include +#include +#include + +#include "stm32.h" +#include "stm32_i2c.h" +#include "arm_internal.h" +#include "fire-stm32v2.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* Assume that we support everything until convinced otherwise */ + +#define HAVE_MMCSD 1 +#define HAVE_USBDEV 1 +#define HAVE_W25 1 + +/* Configuration ************************************************************/ + +/* SPI1 connects to the SD CARD (and to the SPI FLASH) */ + +#define STM32_MMCSDSPIPORTNO 1 /* SPI1 */ +#define STM32_MMCSDSLOTNO 0 /* Only one slot */ + +/* Can't support MMC/SD features if the SDIO peripheral is disabled */ + +#ifndef CONFIG_STM32_SDIO +# undef HAVE_MMCSD +#endif + +/* Can't support MMC/SD features if mountpoints are disabled */ + +#ifdef CONFIG_DISABLE_MOUNTPOINT +# undef HAVE_MMCSD +#endif + +/* Default MMC/SD minor number */ + +#ifdef HAVE_MMCSD +# ifndef CONFIG_NSH_MMCSDMINOR +# define CONFIG_NSH_MMCSDMINOR 0 +# endif + +/* Default MMC/SD SLOT number */ + +# if defined(CONFIG_NSH_MMCSDSLOTNO) && CONFIG_NSH_MMCSDSLOTNO != STM32_MMCSDSLOTNO +# error "Only one MMC/SD slot: Slot 0" +# undef CONFIG_NSH_MMCSDSLOTNO +# define CONFIG_NSH_MMCSDSLOTNO STM32_MMCSDSLOTNO +# endif + +# ifndef CONFIG_NSH_MMCSDSLOTNO +# define CONFIG_NSH_MMCSDSLOTNO STM32_MMCSDSLOTNO +# endif +#endif + +/* Can't support the W25 device if it SPI1 or W25 support is not enabled */ + +#if !defined(CONFIG_STM32_SPI1) || !defined(CONFIG_MTD_W25) +# undef HAVE_W25 +#endif + +/* Can't support W25 features if mountpoints are disabled */ + +#if defined(CONFIG_DISABLE_MOUNTPOINT) +# undef HAVE_W25 +#endif + +/* Default W25 minor number */ + +#if defined(HAVE_W25) && !defined(CONFIG_NSH_W25MINOR) +# define CONFIG_NSH_W25MINOR 0 +#endif + +/* Can't support USB host or device features if the USB peripheral or the USB + * device infrastructure is not enabled + */ + +#if !defined(CONFIG_STM32_USB) || !defined(CONFIG_USBDEV) +# undef HAVE_USBDEV +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_i2c_register + * + * Description: + * Register one I2C drivers for the I2C tool. + * + ****************************************************************************/ + +#ifdef HAVE_I2CTOOL +static void stm32_i2c_register(int bus) +{ + struct i2c_master_s *i2c; + int ret; + + i2c = stm32_i2cbus_initialize(bus); + if (i2c == NULL) + { + _err("ERROR: Failed to get I2C%d interface\n", bus); + } + else + { + ret = i2c_register(i2c, bus); + if (ret < 0) + { + _err("ERROR: Failed to register I2C%d driver: %d\n", bus, ret); + stm32_i2cbus_uninitialize(i2c); + } + } +} +#endif + +/**************************************************************************** + * Name: stm32_i2ctool + * + * Description: + * Register I2C drivers for the I2C tool. + * + ****************************************************************************/ + +#ifdef HAVE_I2CTOOL +static void stm32_i2ctool(void) +{ +#ifdef CONFIG_STM32_I2C1 + stm32_i2c_register(1); +#endif +#ifdef CONFIG_STM32_I2C2 + stm32_i2c_register(2); +#endif +#ifdef CONFIG_STM32_I2C3 + stm32_i2c_register(3); +#endif +} +#else +# define stm32_i2ctool() +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_boardinitialize + * + * Description: + * All STM32 architectures must provide the following entry point. + * This entry point is called early in the initialization -- after all + * memory has been configured and mapped but before any devices have been + * initialized. + * + ****************************************************************************/ + +void stm32_boardinitialize(void) +{ + /* Configure SPI chip selects if 1) SPI is not disabled, and 2) the weak + * function stm32_spidev_initialize() has been brought into the link. + */ + +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) + if (stm32_spidev_initialize) + { + stm32_spidev_initialize(); + } +#endif + + /* Initialize USB is 1) USBDEV is selected, 2) the USB controller is not + * disabled, and 3) the weak function stm32_usbinitialize() has been + * brought into the build. + */ + +#if defined(CONFIG_USBDEV) && defined(CONFIG_STM32_USB) + if (stm32_usbinitialize) + { + stm32_usbinitialize(); + } +#endif + + /* Configure on-board LEDs if LED support has been selected. */ + +#ifdef CONFIG_ARCH_LEDS + board_autoled_initialize(); +#endif +} + +/**************************************************************************** + * Name: board_late_initialize + * + * Description: + * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_late_initialize(). board_late_initialize() will + * be called immediately after up_initialize() is called and just before + * the initial application is started. This additional initialization + * phase may be used, for example, to initialize board-specific device + * drivers. + * + ****************************************************************************/ + +#ifdef CONFIG_BOARD_LATE_INITIALIZE +void board_late_initialize(void) +{ +#if defined(HAVE_MMCSD) || defined(HAVE_W25) + int ret; +#endif + + /* Register I2C drivers on behalf of the I2C tool */ + + stm32_i2ctool(); + +#ifdef HAVE_W25 + /* Initialize and register the W25 FLASH file system. */ + + ret = stm32_w25initialize(CONFIG_NSH_W25MINOR); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to initialize W25 minor %d: %d\n", + CONFIG_NSH_W25MINOR, ret); + return; + } +#endif + +#ifdef HAVE_MMCSD + /* Initialize the SDIO-based MMC/SD slot */ + + ret = stm32_sdinitialize(CONFIG_NSH_MMCSDMINOR); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to initialize MMC/SD slot %d: %d\n", + CONFIG_NSH_MMCSDSLOTNO, ret); + return; + } +#endif +} +#endif diff --git a/boards/arm/stm32f1/fire-stm32v2/src/stm32_buttons.c b/boards/arm/stm32f1/fire-stm32v2/src/stm32_buttons.c new file mode 100644 index 0000000000000..24e083f6f65c9 --- /dev/null +++ b/boards/arm/stm32f1/fire-stm32v2/src/stm32_buttons.c @@ -0,0 +1,148 @@ +/**************************************************************************** + * boards/arm/stm32f1/fire-stm32v2/src/stm32_buttons.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include +#include + +#include "fire-stm32v2.h" + +#ifdef CONFIG_ARCH_BUTTONS + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_button_initialize + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. + * + ****************************************************************************/ + +uint32_t board_button_initialize(void) +{ + /* Configure the GPIO pins as inputs. NOTE that EXTI interrupts are + * configured for some pins but NOT used in this file + */ + + stm32_configgpio(GPIO_BTN_KEY1); + stm32_configgpio(GPIO_BTN_KEY2); + return NUM_BUTTONS; +} + +/**************************************************************************** + * Name: board_buttons + ****************************************************************************/ + +uint32_t board_buttons(void) +{ + uint32_t ret = 0; + + /* Check that state of each key. + * A LOW value means that the key is pressed. + */ + + if (!stm32_gpioread(GPIO_BTN_KEY1)) + { + ret |= BUTTON_KEY1_BIT; + } + + if (!stm32_gpioread(GPIO_BTN_KEY2)) + { + ret |= BUTTON_KEY2_BIT; + } + + return ret; +} + +/**************************************************************************** + * Button support. + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. + * + * After board_button_initialize() has been called, board_buttons() may be + * called to collect the state of all buttons. board_buttons() returns an + * 32-bit bit set with each bit associated with a button. See the + * BUTTON_*_BIT and JOYSTICK_*_BIT definitions in board.h for the meaning + * of each bit. + * + * board_button_irq() may be called to register an interrupt handler that + * will be called when a button is depressed or released. The ID value is a + * button enumeration value that uniquely identifies a button resource. See + * the BUTTON_* and JOYSTICK_* definitions in board.h for the meaning of + * enumeration values. + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_IRQBUTTONS +int board_button_irq(int id, xcpt_t irqhandler, void *arg) +{ + uint16_t gpio; + int ret; + + if (id == BUTTON_KEY1) + { + gpio = GPIO_KEY1; + } + else if (id == BUTTON_KEY2) + { + gpio = GPIO_KEY2; + } + else + { + return -EINVAL; + } + + return stm32_gpiosetevent(gpio, true, true, true, irqhandler, arg); +} +#endif +#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/stm32f1/fire-stm32v2/src/stm32_enc28j60.c b/boards/arm/stm32f1/fire-stm32v2/src/stm32_enc28j60.c new file mode 100644 index 0000000000000..f75a83fa181e9 --- /dev/null +++ b/boards/arm/stm32f1/fire-stm32v2/src/stm32_enc28j60.c @@ -0,0 +1,222 @@ +/**************************************************************************** + * boards/arm/stm32f1/fire-stm32v2/src/stm32_enc28j60.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* 2MBit SPI FLASH OR ENC28J60 + * + * --- ------ -------------- ------------------------------------------------ + * PIN NAME SIGNAL NOTES + * --- ------ -------------- ------------------------------------------------ + * + * 29 PA4 PA4-SPI1-NSS 10Mbit ENC28J60, SPI 2M FLASH + * 30 PA5 PA5-SPI1-SCK 2.4" TFT + Touchscreen, 10Mbit ENC28J60, + * SPI 2M FLASH + * 31 PA6 PA6-SPI1-MISO 2.4" TFT + Touchscreen, 10Mbit ENC28J60, + * SPI 2M FLASH + * 32 PA7 PA7-SPI1-MOSI 2.4" TFT + Touchscreen, 10Mbit ENC28J60, + * SPI 2M FLASH + */ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include + +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32_spi.h" + +#include "fire-stm32v2.h" + +#ifdef CONFIG_ENC28J60 + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* ENC28J60 + * + * --- ------ -------------- ------------------------------------------------ + * PIN NAME SIGNAL NOTES + * --- ------ -------------- ------------------------------------------------ + * + * 29 PA4 PA4-SPI1-NSS 10Mbit ENC28J60, SPI 2M FLASH + * 30 PA5 PA5-SPI1-SCK 2.4" TFT + Touchscreen, 10Mbit ENC28J60, + * SPI 2M FLASH + * 31 PA6 PA6-SPI1-MISO 2.4" TFT + Touchscreen, 10Mbit ENC28J60, + * SPI 2M FLASH + * 32 PA7 PA7-SPI1-MOSI 2.4" TFT + Touchscreen, 10Mbit ENC28J60, + * SPI 2M FLASH + * 98 PE1 PE1-FSMC_NBL1 2.4" TFT + Touchscreen, 10Mbit EN28J60 Reset + * 4 PE5 (no name) 10Mbps ENC28J60 Interrupt + */ + +/* ENC28J60 is on SPI1 */ + +#ifndef CONFIG_STM32_SPI1 +# error "Need CONFIG_STM32_SPI1 in the configuration" +#endif + +/* SPI Assumptions **********************************************************/ + +#define ENC28J60_SPI_PORTNO 1 /* On SPI1 */ +#define ENC28J60_DEVNO 0 /* Only one ENC28J60 */ + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +struct stm32_lower_s +{ + const struct enc_lower_s lower; /* Low-level MCU interface */ + xcpt_t handler; /* ENC28J60 interrupt handler */ + void *arg; /* Argument that accompanies the interrupt */ +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +static int up_attach(const struct enc_lower_s *lower, xcpt_t handler, + void *arg); +static void up_enable(const struct enc_lower_s *lower); +static void up_disable(const struct enc_lower_s *lower); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* The ENC28J60 normal provides interrupts to the MCU via a GPIO pin. The + * following structure provides an MCU-independent mechanixm for controlling + * the ENC28J60 GPIO interrupt. + */ + +static struct stm32_lower_s g_enclower = +{ + .lower = + { + .attach = up_attach, + .enable = up_enable, + .disable = up_disable + }, + .handler = NULL, + .arg = NULL +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: struct enc_lower_s methods + ****************************************************************************/ + +static int up_attach(const struct enc_lower_s *lower, xcpt_t handler, + void *arg) +{ + struct stm32_lower_s *priv = (struct stm32_lower_s *)lower; + + /* Just save the handler for use when the interrupt is enabled */ + + priv->handler = handler; + priv->arg = arg; + return OK; +} + +static void up_enable(const struct enc_lower_s *lower) +{ + struct stm32_lower_s *priv = (struct stm32_lower_s *)lower; + + DEBUGASSERT(priv->handler); + stm32_gpiosetevent(GPIO_ENC28J60_INTR, false, true, true, + priv->handler, priv->arg); +} + +/* REVISIT: Since the interrupt is completely torn down, not just disabled, + * in interrupt requests that occurs while the interrupt is disabled will be + * lost. + */ + +static void up_disable(const struct enc_lower_s *lower) +{ + stm32_gpiosetevent(GPIO_ENC28J60_INTR, false, true, true, + NULL, NULL); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: arm_netinitialize + ****************************************************************************/ + +void arm_netinitialize(void) +{ + struct spi_dev_s *spi; + int ret; + + /* Assumptions: + * 1) ENC28J60 pins were configured in up_spi.c early in the boot-up phase. + * 2) Clocking for the SPI1 peripheral was also provided earlier in + * boot-up. + */ + + spi = stm32_spibus_initialize(ENC28J60_SPI_PORTNO); + if (!spi) + { + nerr("ERROR: Failed to initialize SPI port %d\n", + ENC28J60_SPI_PORTNO); + return; + } + + /* Take ENC28J60 out of reset (active low) */ + + stm32_gpiowrite(GPIO_ENC28J60_RESET, true); + + /* Bind the SPI port to the ENC28J60 driver */ + + ret = enc_initialize(spi, &g_enclower.lower, ENC28J60_DEVNO); + if (ret < 0) + { + nerr("ERROR: Failed to bind SPI port %d ENC28J60 device %d: %d\n", + ENC28J60_SPI_PORTNO, ENC28J60_DEVNO, ret); + return; + } + + ninfo("Bound SPI port %d to ENC28J60 device %d\n", + ENC28J60_SPI_PORTNO, ENC28J60_DEVNO); +} + +#endif /* CONFIG_ENC28J60 */ diff --git a/boards/arm/stm32f1/fire-stm32v2/src/stm32_mmcsd.c b/boards/arm/stm32f1/fire-stm32v2/src/stm32_mmcsd.c new file mode 100644 index 0000000000000..7b24f9062cf3e --- /dev/null +++ b/boards/arm/stm32f1/fire-stm32v2/src/stm32_mmcsd.c @@ -0,0 +1,111 @@ +/**************************************************************************** + * boards/arm/stm32f1/fire-stm32v2/src/stm32_mmcsd.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "stm32_sdio.h" +#include "fire-stm32v2.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +#define HAVE_MMCSD 1 /* Assume that we have SD support */ +#define STM32_MMCSDSLOTNO 0 /* There is only one slot */ + +/* Can't support MMC/SD features if the SDIO peripheral is disabled */ + +#ifndef CONFIG_STM32_SDIO +# undef HAVE_MMCSD +#endif + +/* Can't support MMC/SD features if mountpoints are disabled */ + +#ifdef CONFIG_DISABLE_MOUNTPOINT +# undef HAVE_MMCSD +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_sdinitialize + * + * Description: + * Initialize the SPI-based SD card. Requires CONFIG_DISABLE_MOUNTPOINT=n + * and CONFIG_STM32_SDIO=y + * + ****************************************************************************/ + +int stm32_sdinitialize(int minor) +{ +#ifdef HAVE_MMCSD + struct sdio_dev_s *sdio; + int ret; + + /* First, get an instance of the SDIO interface */ + + sdio = sdio_initialize(STM32_MMCSDSLOTNO); + if (!sdio) + { + ferr("ERROR: Failed to initialize SDIO slot %d\n", STM32_MMCSDSLOTNO); + return -ENODEV; + } + + finfo("Initialized SDIO slot %d\n", STM32_MMCSDSLOTNO); + + /* Now bind the SDIO interface to the MMC/SD driver */ + + ret = mmcsd_slotinitialize(minor, sdio); + if (ret != OK) + { + ferr("ERROR:"); + ferr(" Failed to bind SDIO slot %d to the MMC/SD driver, minor=%d\n", + STM32_MMCSDSLOTNO, minor); + } + + finfo("Bound SDIO slot %d to the MMC/SD driver, minor=%d\n", + STM32_MMCSDSLOTNO, minor); + + /* Then let's guess and say that there is a card in the slot. + * I need to check to see if the M3 Wildfire board supports a GPIO to + * detect if there is a card in the slot. + */ + + sdio_mediachange(sdio, true); +#endif + return OK; +} diff --git a/boards/arm/stm32f1/fire-stm32v2/src/stm32_selectlcd.c b/boards/arm/stm32f1/fire-stm32v2/src/stm32_selectlcd.c new file mode 100644 index 0000000000000..153572749c569 --- /dev/null +++ b/boards/arm/stm32f1/fire-stm32v2/src/stm32_selectlcd.c @@ -0,0 +1,182 @@ +/**************************************************************************** + * boards/arm/stm32f1/fire-stm32v2/src/stm32_selectlcd.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32_gpio.h" +#include "stm32.h" +#include "fire-stm32v2.h" + +#ifdef CONFIG_STM32_FSMC + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifndef CONFIG_STM32_FSMC +# warning "FSMC is not enabled" +#endif + +#if STM32_NGPIO_PORTS < 6 +# error "Required GPIO ports not enabled" +#endif + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/* 2.4" TFT + Touchscreen. FSMC Bank1 + * + * --- ------ -------------- ------------------------------------------------ + * PIN NAME SIGNAL NOTES + * --- ------ -------------- ------------------------------------------------ + * + * 30 PA5 PA5-SPI1-SCK 2.4" TFT + Touchscreen, 10Mbit ENC28J60, + * SPI 2M FLASH + * 31 PA6 PA6-SPI1-MISO 2.4" TFT + Touchscreen, 10Mbit ENC28J60, + * SPI 2M FLASH + * 32 PA7 PA7-SPI1-MOSI 2.4" TFT + Touchscreen, 10Mbit ENC28J60, + * SPI 2M FLASH + * 92 PB6 PB6-I2C1-SCL 2.4" TFT + Touchscreen, AT24C02 + * 93 PB7 PB7-I2C1-SDA 2.4" TFT + Touchscreen, AT24C02 + * 81 PD0 PD0-FSMC_D2 2.4" TFT + Touchscreen + * 82 PD1 PD1-FSMC_D3 2.4" TFT + Touchscreen + * 85 PD4 PD4-FSMC_NOE 2.4" TFT + Touchscreen + * 86 PD5 PD5-FSMC_NWE 2.4" TFT + Touchscreen + * 88 PD7 PD7-FSMC_NE1 2.4" TFT + Touchscreen + * 55 PD8 PD8-FSMC_D13 2.4" TFT + Touchscreen + * 56 PD9 PD9-FSMC_D14 2.4" TFT + Touchscreen + * 57 PD10 PD10-FSMC_D15 2.4" TFT + Touchscreen + * 58 PD11 PD11-FSMC_A16 2.4" TFT + Touchscreen + * 60 PD13 PD13-LCD/LIGHT 2.4" TFT + Touchscreen + * 61 PD14 PD14-FSMC_D0 2.4" TFT + Touchscreen + * 62 PD15 PD15-FSMC_D1 2.4" TFT + Touchscreen + * 98 PE1 PE1-FSMC_NBL1 2.4" TFT + Touchscreen + * 38 PE7 PE7-FSMC_D4 2.4" TFT + Touchscreen + * 39 PE8 PE8-FSMC_D5 2.4" TFT + Touchscreen + * 40 PE9 PE9-FSMC_D6 2.4" TFT + Touchscreen + * 41 PE10 PE10-FSMC_D7 2.4" TFT + Touchscreen + * 42 PE11 PE11-FSMC_D8 2.4" TFT + Touchscreen + * 43 PE12 PE12-FSMC_D9 2.4" TFT + Touchscreen + * 44 PE13 PE13-FSMC_D10 2.4" TFT + Touchscreen + * 45 PE14 PE14-FSMC_D11 2.4" TFT + Touchscreen + * 46 PE15 PE15-FSMC_D12 2.4" TFT + Touchscreen + * + * NOTE: + * SPI and I2C pin configuration is controlled in the SPI and I2C drivers, + * respectively. + */ + +static const uint16_t g_lcdconfig[NCOMMON_CONFIG] = +{ + /* Address Lines: A16 only */ + + GPIO_NPS_A16, + + /* Data Lines: D0... D15 */ + + GPIO_NPS_D0, GPIO_NPS_D1, GPIO_NPS_D2, GPIO_NPS_D3, + GPIO_NPS_D4, GPIO_NPS_D5, GPIO_NPS_D6, GPIO_NPS_D7, + GPIO_NPS_D8, GPIO_NPS_D9, GPIO_NPS_D10, GPIO_NPS_D11, + GPIO_NPS_D12, GPIO_NPS_D13, GPIO_NPS_D14, GPIO_NPS_D15, + + /* NOE, NWE, NE1, NBL1 */ + + GPIO_NPS_NOE, GPIO_NPS_NWE, GPIO_NPS_NE1, GPIO_NPS_NBL1, + + /* Backlight GPIO */ + + GPIO_LCD_BACKLIGHT +}; +#define NLCD_CONFIG (sizeof(g_lcdconfig) / sizeof(uint16_t)) + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_selectlcd + * + * Description: + * Initialize to the LCD pin configuration. + * + ****************************************************************************/ + +void stm32_selectlcd(void) +{ + irqstate_t flags; + int i; + + /* Configure LCD GPIO pis */ + + flags = enter_critical_section(); + for (i = 0; i < NLCD_GPIOS; i++) + { + stm32_configgpio(g_lcdconfig[i]); + } + + /* Enable AHB clocking to the FSMC */ + + stm32_fsmc_enable(); + + /* Bank1 NOR/SRAM control register configuration */ + + putreg32(FSMC_BCR_SRAM | FSMC_BCR_MWID16 | FSMC_BCR_WREN, STM32_FSMC_BCR1); + + /* Bank1 NOR/SRAM timing register configuration */ + + putreg32(FSMC_BTR_ADDSET(1) | FSMC_BTR_ADDHLD(1) | + FSMC_BTR_DATAST(2) | FSMC_BTR_BUSTURN(1) | + FSMC_BTR_CLKDIV(1) | FSMC_BTR_DATLAT(2) | + FSMC_BTR_ACCMODA, STM32_FSMC_BTR1); + + putreg32(0xffffffff, STM32_FSMC_BWTR4); + + /* Enable the bank by setting the MBKEN bit */ + + putreg32(FSMC_BCR_MBKEN | FSMC_BCR_SRAM | + FSMC_BCR_MWID16 | FSMC_BCR_WREN, STM32_FSMC_BCR1); + leave_critical_section(flags); +} + +#endif /* CONFIG_STM32_FSMC */ diff --git a/boards/arm/stm32f1/fire-stm32v2/src/stm32_spi.c b/boards/arm/stm32f1/fire-stm32v2/src/stm32_spi.c new file mode 100644 index 0000000000000..42f31b0005e63 --- /dev/null +++ b/boards/arm/stm32f1/fire-stm32v2/src/stm32_spi.c @@ -0,0 +1,181 @@ +/**************************************************************************** + * boards/arm/stm32f1/fire-stm32v2/src/stm32_spi.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "arm_internal.h" +#include "chip.h" +#include "stm32.h" +#include "fire-stm32v2.h" + +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_spidev_initialize + * + * Description: + * Called to configure SPI chip select GPIO pins for the M3 Wildfire board. + * + ****************************************************************************/ + +void weak_function stm32_spidev_initialize(void) +{ + /* NOTE: Clocking for SPI1 and/or SPI2 was already provided in stm32_rcc.c. + * Configurations of SPI pins is performed in stm32_spi.c. + * Here, we only initialize chip select pins unique to the board + * architecture. + */ + +#ifdef CONFIG_STM32_SPI1 + /* Configure the TFT/Touchscreen CS GPIO */ + +#if 0 /* Need to study this */ + stm32_configgpio(GPIO_LCD_CS); +#endif + + /* Configure the TFT/Touchscreen and ENC28J60 or SPI-based FLASH PIOs */ + + /* Configure ENC28J60 SPI1 CS (also RESET and interrupt pins) */ + +#ifdef CONFIG_ENC28J60 + stm32_configgpio(GPIO_ENC28J60_CS); + stm32_configgpio(GPIO_ENC28J60_RESET); + stm32_configgpio(GPIO_ENC28J60_INTR); +#else + + /* Configure FLASH SPI1 CS */ + + stm32_configgpio(GPIO_FLASH_CS); +#endif + +#endif /* CONFIG_STM32_SPI1 */ + +#ifdef CONFIG_STM32_SPI2 + /* Configure the MP3 SPI2 CS GPIO */ + + stm32_configgpio(GPIO_MP3_CS); + +#endif /* CONFIG_STM32_SPI2 */ +} + +/**************************************************************************** + * Name: stm32_spi1/2/3select and stm32_spi1/2/3status + * + * Description: + * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status + * must be provided by board-specific logic. They are implementations of + * the select and status methods of the SPI interface defined by struct + * spi_ops_s (see include/nuttx/spi/spi.h). All other methods + * (including stm32_spibus_initialize()) are provided by common STM32 + * logic. To use this common SPI logic on your board: + * + * 1. Provide logic in stm32_boardinitialize() to configure SPI chip select + * pins. + * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() functions + * in your board-specific logic. These functions will perform chip + * selection and status operations using GPIOs in the way your board is + * configured. + * 3. Add a calls to stm32_spibus_initialize() in your low level + * application initialization logic + * 4. The handle returned by stm32_spibus_initialize() may then be used to + * bind the SPI driver to higher level logic (e.g., calling + * mmcsd_spislotinitialize(), for example, will bind the SPI driver to + * the SPI MMC/SD driver). + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_SPI1 +void stm32_spi1select(struct spi_dev_s *dev, + uint32_t devid, bool selected) +{ + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); + +#if 0 /* Need to study this */ + if (devid == SPIDEV_LCD) + { + /* Set the GPIO low to select and high to de-select */ + + stm32_gpiowrite(GPIO_LCD_CS, !selected); + } + else +#endif +#ifdef CONFIG_ENC28J60 + if (devid == SPIDEV_ETHERNET(0)) + { + /* Set the GPIO low to select and high to de-select */ + + stm32_gpiowrite(GPIO_ENC28J60_CS, !selected); + } +#else + if (devid == SPIDEV_FLASH(0)) + { + /* Set the GPIO low to select and high to de-select */ + + stm32_gpiowrite(GPIO_FLASH_CS, !selected); + } +#endif +} + +uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) +{ + return SPI_STATUS_PRESENT; +} +#endif + +#ifdef CONFIG_STM32_SPI2 +void stm32_spi2select(struct spi_dev_s *dev, + uint32_t devid, bool selected) +{ + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); + + if (devid == SPIDEV_AUDIO) + { + /* Set the GPIO low to select and high to de-select */ + + stm32_gpiowrite(GPIO_MP3_CS, !selected); + } +} + +uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) +{ + return SPI_STATUS_PRESENT; +} +#endif + +#endif /* CONFIG_STM32_SPI1 || CONFIG_STM32_SPI2 */ diff --git a/boards/arm/stm32f1/fire-stm32v2/src/stm32_usbdev.c b/boards/arm/stm32f1/fire-stm32v2/src/stm32_usbdev.c new file mode 100644 index 0000000000000..51fb1b1ab516c --- /dev/null +++ b/boards/arm/stm32f1/fire-stm32v2/src/stm32_usbdev.c @@ -0,0 +1,107 @@ +/**************************************************************************** + * boards/arm/stm32f1/fire-stm32v2/src/stm32_usbdev.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include + +#include "arm_internal.h" +#include "stm32.h" +#include "fire-stm32v2.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_usbinitialize + * + * Description: + * Called to setup USB-related GPIO pins for the M3 Wildfire board. + * + ****************************************************************************/ + +void stm32_usbinitialize(void) +{ + /* USB Soft Connect Pullup */ + +#if 0 /* REVISIT */ + stm32_configgpio(GPIO_USB_PULLUP); +#endif +} + +/**************************************************************************** + * Name: stm32_usbpullup + * + * Description: + * If USB is supported and the board supports a pullup via GPIO (for USB + * software connect and disconnect), then the board software must provide + * stm32_pullup. See include/nuttx/usb/usbdev.h for additional description + * of this method. + * Alternatively, if no pull-up GPIO the following EXTERN can be redefined + * to be NULL. + * + ****************************************************************************/ + +int stm32_usbpullup(struct usbdev_s *dev, bool enable) +{ + usbtrace(TRACE_DEVPULLUP, (uint16_t)enable); +#if 0 /* REVISIT */ + stm32_gpiowrite(GPIO_USB_PULLUP, !enable); +#endif + return OK; +} + +/**************************************************************************** + * Name: stm32_usbsuspend + * + * Description: + * Board logic must provide the stm32_usbsuspend logic if the USBDEV driver + * is used. This function is called whenever the USB enters or leaves + * suspend mode. + * This is an opportunity for the board logic to shutdown clocks, power, + * etc. while the USB is suspended. + * + ****************************************************************************/ + +void stm32_usbsuspend(struct usbdev_s *dev, bool resume) +{ + uinfo("resume: %d\n", resume); +} diff --git a/boards/arm/stm32f1/fire-stm32v2/src/stm32_usbmsc.c b/boards/arm/stm32f1/fire-stm32v2/src/stm32_usbmsc.c new file mode 100644 index 0000000000000..c34d41e68965c --- /dev/null +++ b/boards/arm/stm32f1/fire-stm32v2/src/stm32_usbmsc.c @@ -0,0 +1,71 @@ +/**************************************************************************** + * boards/arm/stm32f1/fire-stm32v2/src/stm32_usbmsc.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include + +#include "stm32.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +#ifndef CONFIG_SYSTEM_USBMSC_DEVMINOR1 +# define CONFIG_SYSTEM_USBMSC_DEVMINOR1 0 +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_usbmsc_initialize + * + * Description: + * Perform architecture specific initialization of the USB MSC device. + * + ****************************************************************************/ + +int board_usbmsc_initialize(int port) +{ + /* If system/usbmsc is built as an NSH command, then SD slot should + * already have been initialized. + * In this case, there is nothing further to be done here. + */ + +#ifndef CONFIG_NSH_BUILTIN_APPS + return stm32_sdinitialize(CONFIG_SYSTEM_USBMSC_DEVMINOR1); +#else + return OK; +#endif +} diff --git a/boards/arm/stm32f1/fire-stm32v2/src/stm32_userleds.c b/boards/arm/stm32f1/fire-stm32v2/src/stm32_userleds.c new file mode 100644 index 0000000000000..f94020021af18 --- /dev/null +++ b/boards/arm/stm32f1/fire-stm32v2/src/stm32_userleds.c @@ -0,0 +1,104 @@ +/**************************************************************************** + * boards/arm/stm32f1/fire-stm32v2/src/stm32_userleds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32.h" +#include "fire-stm32v2.h" + +#ifndef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* This array maps an LED number to GPIO pin configuration */ + +static uint32_t g_ledcfg[BOARD_NLEDS] = +{ + GPIO_LED1, GPIO_LED2, GPIO_LED3 +}; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_userled_initialize + ****************************************************************************/ + +uint32_t board_userled_initialize(void) +{ + /* Configure LED1-4 GPIOs for output */ + + stm32_configgpio(GPIO_LED1); + stm32_configgpio(GPIO_LED2); + stm32_configgpio(GPIO_LED3); + return 3; +} + +/**************************************************************************** + * Name: board_userled + * + * Description: + * Set one LED to the 'ledon' state. The LEDs are pulled up and, hence, + * active low. + * + ****************************************************************************/ + +void board_userled(int led, bool ledon) +{ + if ((unsigned)led < BOARD_NLEDS) + { + stm32_gpiowrite(g_ledcfg[led], !ledon); + } +} + +/**************************************************************************** + * Name: board_userled_all + * + * Description: + * Set each LED to the bit encoded state. The LEDs are pulled up and, + * hence, active low. + * + ****************************************************************************/ + +void board_userled_all(uint32_t ledset) +{ + stm32_gpiowrite(GPIO_LED1, (ledset & BOARD_LED1_BIT) == 0); + stm32_gpiowrite(GPIO_LED2, (ledset & BOARD_LED2_BIT) == 0); + stm32_gpiowrite(GPIO_LED3, (ledset & BOARD_LED3_BIT) == 0); +} + +#endif /* !CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32f1/fire-stm32v2/src/stm32_w25.c b/boards/arm/stm32f1/fire-stm32v2/src/stm32_w25.c new file mode 100644 index 0000000000000..56ed032c057b3 --- /dev/null +++ b/boards/arm/stm32f1/fire-stm32v2/src/stm32_w25.c @@ -0,0 +1,144 @@ +/**************************************************************************** + * boards/arm/stm32f1/fire-stm32v2/src/stm32_w25.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#ifdef CONFIG_STM32_SPI1 +# include +# include +# include +# include +#endif + +#include "stm32_spi.h" +#include "fire-stm32v2.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* Can't support the W25 device if it SPI1 or W25 support is not enabled */ + +#define HAVE_W25 1 +#if !defined(CONFIG_STM32_SPI1) || !defined(CONFIG_MTD_W25) +# undef HAVE_W25 +#endif + +/* Can't support W25 features if mountpoints are disabled */ + +#if defined(CONFIG_DISABLE_MOUNTPOINT) +# undef HAVE_W25 +#endif + +/* Can't support both FAT and NXFFS */ + +#if defined(CONFIG_FS_FAT) && defined(CONFIG_FS_NXFFS) +# warning "Can't support both FAT and NXFFS -- using FAT" +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_w25initialize + * + * Description: + * Initialize and register the W25 FLASH file system. + * + ****************************************************************************/ + +int stm32_w25initialize(int minor) +{ +#ifdef HAVE_W25 + struct spi_dev_s *spi; + struct mtd_dev_s *mtd; +#ifdef CONFIG_FS_NXFFS + char devname[12]; +#endif + int ret; + + /* Get the SPI port */ + + spi = stm32_spibus_initialize(1); + if (!spi) + { + ferr("ERROR: Failed to initialize SPI port 2\n"); + return -ENODEV; + } + + /* Now bind the SPI interface to the W25 SPI FLASH driver */ + + mtd = w25_initialize(spi); + if (!mtd) + { + ferr("ERROR: Failed to bind SPI port 2 to the SST 25 FLASH driver\n"); + return -ENODEV; + } + +#ifndef CONFIG_FS_NXFFS + /* Register the MTD driver */ + + char path[32]; + snprintf(path, sizeof(path), "/dev/mtdblock%d", minor); + ret = register_mtddriver(path, mtd, 0755, NULL); + if (ret < 0) + { + ferr("ERROR: Failed to register the MTD driver %s, ret %d\n", + path, ret); + return ret; + } +#else + /* Initialize to provide NXFFS on the MTD interface */ + + ret = nxffs_initialize(mtd); + if (ret < 0) + { + ferr("ERROR: NXFFS initialization failed: %d\n", -ret); + return ret; + } + + /* Mount the file system at /mnt/w25 */ + + snprintf(devname, sizeof(devname), "/mnt/w25%c", 'a' + minor); + ret = nx_mount(NULL, devname, "nxffs", 0, NULL); + if (ret < 0) + { + ferr("ERROR: Failed to mount the NXFFS volume: %d\n", ret); + return ret; + } +#endif +#endif + + return OK; +} diff --git a/boards/arm/stm32f1/hymini-stm32v/CMakeLists.txt b/boards/arm/stm32f1/hymini-stm32v/CMakeLists.txt new file mode 100644 index 0000000000000..4af2981effa4a --- /dev/null +++ b/boards/arm/stm32f1/hymini-stm32v/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32f1/hymini-stm32v/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/arm/stm32/hymini-stm32v/Kconfig b/boards/arm/stm32f1/hymini-stm32v/Kconfig similarity index 100% rename from boards/arm/stm32/hymini-stm32v/Kconfig rename to boards/arm/stm32f1/hymini-stm32v/Kconfig diff --git a/boards/arm/stm32f1/hymini-stm32v/configs/nsh/defconfig b/boards/arm/stm32f1/hymini-stm32v/configs/nsh/defconfig new file mode 100644 index 0000000000000..2b1d0d38fe169 --- /dev/null +++ b/boards/arm/stm32f1/hymini-stm32v/configs/nsh/defconfig @@ -0,0 +1,48 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="hymini-stm32v" +CONFIG_ARCH_BOARD_HYMINI_STM32V=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f1" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F103VC=y +CONFIG_ARCH_CHIP_STM32F1=y +CONFIG_ARCH_IRQBUTTONS=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BINFMT_DISABLE=y +CONFIG_BOARD_LOOPSPERMSEC=5483 +CONFIG_FAT_LCNAMES=y +CONFIG_FS_FAT=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_MMCSD=y +CONFIG_MMCSD_SDIO=y +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=49152 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=192 +CONFIG_SCHED_HPWORKSTACKSIZE=1024 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=5 +CONFIG_START_MONTH=7 +CONFIG_START_YEAR=2011 +CONFIG_STM32_BKP=y +CONFIG_STM32_DMA2=y +CONFIG_STM32_PWR=y +CONFIG_STM32_SDIO=y +CONFIG_STM32_USART1=y +CONFIG_SYMTAB_ORDEREDBYNAME=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f1/hymini-stm32v/configs/nsh2/defconfig b/boards/arm/stm32f1/hymini-stm32v/configs/nsh2/defconfig new file mode 100644 index 0000000000000..fda1334b5880a --- /dev/null +++ b/boards/arm/stm32f1/hymini-stm32v/configs/nsh2/defconfig @@ -0,0 +1,91 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_MMCSD_MMCSUPPORT is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_NXFONTS_DISABLE_16BPP is not set +# CONFIG_NX_DISABLE_16BPP is not set +# CONFIG_NX_PACKEDMSFIRST is not set +# CONFIG_SPI_CALLBACK is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="hymini-stm32v" +CONFIG_ARCH_BOARD_HYMINI_STM32V=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f1" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F103VC=y +CONFIG_ARCH_CHIP_STM32F1=y +CONFIG_ARCH_IRQBUTTONS=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=5483 +CONFIG_BUILTIN=y +CONFIG_EXAMPLES_NX=y +CONFIG_EXAMPLES_NXHELLO=y +CONFIG_EXAMPLES_NXHELLO_BPP=16 +CONFIG_EXAMPLES_NXIMAGE=y +CONFIG_EXAMPLES_NXIMAGE_BPP=16 +CONFIG_EXAMPLES_NX_BPP=16 +CONFIG_EXAMPLES_TOUCHSCREEN=y +CONFIG_FAT_LCNAMES=y +CONFIG_FAT_LFN=y +CONFIG_FS_FAT=y +CONFIG_FS_FATTIME=y +CONFIG_FS_ROMFS=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INPUT=y +CONFIG_INPUT_ADS7843E=y +CONFIG_LCD=y +CONFIG_LCD_MAXCONTRAST=1 +CONFIG_LCD_MAXPOWER=100 +CONFIG_LCD_SSD1289=y +CONFIG_MMCSD=y +CONFIG_MMCSD_SDIO=y +CONFIG_MQ_MAXMSGSIZE=64 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_READLINE=y +CONFIG_NX=y +CONFIG_NXFONT_SANS23X27=y +CONFIG_NXFONT_SANS28X37B=y +CONFIG_NX_BLOCKING=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=49152 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=192 +CONFIG_SCHED_HPWORKSTACKSIZE=1024 +CONFIG_SCHED_WAITPID=y +CONFIG_SSD1289_PROFILE2=y +CONFIG_STM32_BKP=y +CONFIG_STM32_DMA2=y +CONFIG_STM32_FSMC=y +CONFIG_STM32_PWR=y +CONFIG_STM32_RTC=y +CONFIG_STM32_SDIO=y +CONFIG_STM32_SPI1=y +CONFIG_STM32_TIM3=y +CONFIG_STM32_TIM3_PARTIAL_REMAP=y +CONFIG_STM32_USART1=y +CONFIG_STM32_USB=y +CONFIG_SYMTAB_ORDEREDBYNAME=y +CONFIG_SYSTEM_NSH=y +CONFIG_SYSTEM_USBMSC=y +CONFIG_SYSTEM_USBMSC_DEVMINOR1=0 +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART1_SERIAL_CONSOLE=y +CONFIG_USBDEV_TRACE=y +CONFIG_USBMSC=y +CONFIG_USBMSC_BULKINREQLEN=256 +CONFIG_USBMSC_BULKOUTREQLEN=256 +CONFIG_USBMSC_EPBULKIN=5 +CONFIG_USBMSC_NRDREQS=2 +CONFIG_USBMSC_NWRREQS=2 +CONFIG_USBMSC_PRODUCTSTR="USBdev Storage" +CONFIG_USBMSC_REMOVABLE=y +CONFIG_USBMSC_VERSIONNO=0x0399 diff --git a/boards/arm/stm32f1/hymini-stm32v/configs/usbmsc/defconfig b/boards/arm/stm32f1/hymini-stm32v/configs/usbmsc/defconfig new file mode 100644 index 0000000000000..3686bd67351e8 --- /dev/null +++ b/boards/arm/stm32f1/hymini-stm32v/configs/usbmsc/defconfig @@ -0,0 +1,53 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_MMCSD_HAVE_CARDDETECT is not set +# CONFIG_MMCSD_MMCSUPPORT is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="hymini-stm32v" +CONFIG_ARCH_BOARD_HYMINI_STM32V=y +CONFIG_ARCH_CHIP="stm32f1" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F103VC=y +CONFIG_ARCH_CHIP_STM32F1=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL=y +CONFIG_BOARD_LOOPSPERMSEC=5483 +CONFIG_INIT_ENTRYPOINT="msconn_main" +CONFIG_MMCSD=y +CONFIG_MMCSD_SDIO=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=49152 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=192 +CONFIG_SCHED_HPWORKSTACKSIZE=1024 +CONFIG_START_DAY=30 +CONFIG_START_MONTH=11 +CONFIG_START_YEAR=2009 +CONFIG_STM32_DMA2=y +CONFIG_STM32_FSMC=y +CONFIG_STM32_SDIO=y +CONFIG_STM32_USART1=y +CONFIG_STM32_USART2=y +CONFIG_STM32_USB=y +CONFIG_SYMTAB_ORDEREDBYNAME=y +CONFIG_SYSTEM_USBMSC=y +CONFIG_SYSTEM_USBMSC_DEVMINOR1=0 +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART1_SERIAL_CONSOLE=y +CONFIG_USBMSC=y +CONFIG_USBMSC_BULKINREQLEN=256 +CONFIG_USBMSC_BULKOUTREQLEN=256 +CONFIG_USBMSC_EPBULKIN=5 +CONFIG_USBMSC_NRDREQS=2 +CONFIG_USBMSC_NWRREQS=2 +CONFIG_USBMSC_PRODUCTSTR="USBdev Storage" +CONFIG_USBMSC_REMOVABLE=y +CONFIG_USBMSC_VERSIONNO=0x0399 diff --git a/boards/arm/stm32f1/hymini-stm32v/configs/usbnsh/defconfig b/boards/arm/stm32f1/hymini-stm32v/configs/usbnsh/defconfig new file mode 100644 index 0000000000000..1d4d819411950 --- /dev/null +++ b/boards/arm/stm32f1/hymini-stm32v/configs/usbnsh/defconfig @@ -0,0 +1,49 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="hymini-stm32v" +CONFIG_ARCH_BOARD_HYMINI_STM32V=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f1" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F103VC=y +CONFIG_ARCH_CHIP_STM32F1=y +CONFIG_ARCH_IRQBUTTONS=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BINFMT_DISABLE=y +CONFIG_BOARDCTL_USBDEVCTRL=y +CONFIG_BOARD_LOOPSPERMSEC=5483 +CONFIG_CDCACM=y +CONFIG_CDCACM_CONSOLE=y +CONFIG_CDCACM_RXBUFSIZE=256 +CONFIG_CDCACM_TXBUFSIZE=256 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=49152 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=192 +CONFIG_SCHED_HPWORKSTACKSIZE=1024 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=5 +CONFIG_START_MONTH=7 +CONFIG_START_YEAR=2011 +CONFIG_STM32_BKP=y +CONFIG_STM32_PWR=y +CONFIG_STM32_USART1=y +CONFIG_STM32_USB=y +CONFIG_SYMTAB_ORDEREDBYNAME=y +CONFIG_SYSLOG_CHAR=y +CONFIG_SYSLOG_DEVPATH="/dev/ttyS0" +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 diff --git a/boards/arm/stm32f1/hymini-stm32v/configs/usbserial/defconfig b/boards/arm/stm32f1/hymini-stm32v/configs/usbserial/defconfig new file mode 100644 index 0000000000000..488745ba2fb05 --- /dev/null +++ b/boards/arm/stm32f1/hymini-stm32v/configs/usbserial/defconfig @@ -0,0 +1,37 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="hymini-stm32v" +CONFIG_ARCH_BOARD_HYMINI_STM32V=y +CONFIG_ARCH_CHIP="stm32f1" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F103VC=y +CONFIG_ARCH_CHIP_STM32F1=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL=y +CONFIG_BOARD_LOOPSPERMSEC=5483 +CONFIG_DISABLE_MOUNTPOINT=y +CONFIG_EXAMPLES_USBSERIAL=y +CONFIG_INIT_ENTRYPOINT="usbserial_main" +CONFIG_PL2303=y +CONFIG_PL2303_PRODUCTSTR="USBdev Serial" +CONFIG_PL2303_RXBUFSIZE=512 +CONFIG_PL2303_TXBUFSIZE=512 +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=49152 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_START_DAY=23 +CONFIG_START_MONTH=10 +CONFIG_START_YEAR=2009 +CONFIG_STM32_USART1=y +CONFIG_STM32_USART2=y +CONFIG_STM32_USB=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f1/hymini-stm32v/include/board.h b/boards/arm/stm32f1/hymini-stm32v/include/board.h new file mode 100644 index 0000000000000..820d03a162b66 --- /dev/null +++ b/boards/arm/stm32f1/hymini-stm32v/include/board.h @@ -0,0 +1,242 @@ +/**************************************************************************** + * boards/arm/stm32f1/hymini-stm32v/include/board.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_STM32_HYMINI_STM32V_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32_HYMINI_STM32V_INCLUDE_BOARD_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Clocking *****************************************************************/ + +/* On-board crystal frequency is 8MHz (HSE) */ + +#define STM32_BOARD_XTAL 8000000ul + +/* PLL source is HSE/1, PLL multiplier is 9: + * PLL frequency is 8MHz (XTAL) x 9 = 72MHz + */ + +#define STM32_CFGR_PLLSRC RCC_CFGR_PLLSRC +#define STM32_CFGR_PLLXTPRE 0 +#define STM32_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx9 +#define STM32_PLL_FREQUENCY (9*STM32_BOARD_XTAL) + +/* Use the PLL and set the SYSCLK source to be the PLL */ + +#define STM32_SYSCLK_SW RCC_CFGR_SW_PLL +#define STM32_SYSCLK_SWS RCC_CFGR_SWS_PLL +#define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY + +/* AHB clock (HCLK) is SYSCLK (72MHz) */ + +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK +#define STM32_HCLK_FREQUENCY STM32_PLL_FREQUENCY + +/* APB2 clock (PCLK2) is HCLK (72MHz) */ + +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK +#define STM32_PCLK2_FREQUENCY STM32_HCLK_FREQUENCY + +/* APB2 timers 1 and 8 will receive PCLK2. */ + +#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) + +/* APB1 clock (PCLK1) is HCLK/2 (36MHz) */ + +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd2 +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/2) + +/* APB1 timers 2-7 will be twice PCLK1 */ + +#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) + +/* USB divider -- Divide PLL clock by 1.5 */ + +#define STM32_CFGR_USBPRE 0 + +/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx + * otherwise frequency is 2xAPBx. + * Note: TIM1,8 are on APB2, others on APB1 + */ + +#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM2_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM3_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM4_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM5_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM6_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM7_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY + +/* SDIO dividers. Note that slower clocking is required when DMA is disabled + * in order to avoid RX overrun/TX underrun errors due to delayed responses + * to service FIFOs in interrupt driven mode. These values have not been + * tuned!!! + * + * HCLK=72MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(178+2)=400 KHz + */ + +#define SDIO_INIT_CLKDIV (178 << SDIO_CLKCR_CLKDIV_SHIFT) + +/* DMA ON: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(2+2)=18 MHz + * DMA OFF: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(3+2)=14.4 MHz + */ + +#ifdef CONFIG_STM32_SDIO_DMA +# define SDIO_MMCXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT) +#else +# define SDIO_MMCXFR_CLKDIV (3 << SDIO_CLKCR_CLKDIV_SHIFT) +#endif + +/* DMA ON: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(1+2)=24 MHz + * DMA OFF: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(3+2)=14.4 MHz + */ + +#ifdef CONFIG_STM32_SDIO_DMA +# define SDIO_SDXFR_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT) +#else +# define SDIO_SDXFR_CLKDIV (3 << SDIO_CLKCR_CLKDIV_SHIFT) +#endif + +/* LED definitions **********************************************************/ + +/* The board has 2 LEDs that we will encode as: */ +#define LED_STARTED 0 /* No LEDs */ +#define LED_HEAPALLOCATE 1 /* LED1 on */ +#define LED_IRQSENABLED 2 /* LED2 on */ +#define LED_STACKCREATED 3 /* LED1 on */ +#define LED_INIRQ 4 /* LED1 off */ +#define LED_SIGNAL 5 /* LED2 on */ +#define LED_ASSERTION 6 /* LED1 + LED2 */ +#define LED_PANIC 7 /* LED1 / LED2 blinking */ + +/* The board supports two user buttons + * + * KeyA -- Connected to PC.13 + * KeyB -- Connected to PB.2 + */ + +#define BUTTON_KEYA 0 +#define BUTTON_KEYB 1 + +#define NUM_BUTTONS 2 + +#define BUTTON_KEYA_BIT (1 << BUTTON_KEYA) +#define BUTTON_KEYB_BIT (1 << BUTTON_KEYB) + +/* Alternate function pin selections (auto-aliased for new pinmap) */ + +/* USART1 */ + +#define GPIO_USART1_TX GPIO_ADJUST_MODE(GPIO_USART1_TX_0, GPIO_MODE_50MHz) +#define GPIO_USART1_RX GPIO_USART1_RX_0 + +/* USART2 */ + +#define GPIO_USART2_TX GPIO_ADJUST_MODE(GPIO_USART2_TX_0, GPIO_MODE_50MHz) +#define GPIO_USART2_RX GPIO_USART2_RX_0 +#define GPIO_USART2_CTS GPIO_USART2_CTS_0 +#define GPIO_USART2_RTS GPIO_ADJUST_MODE(GPIO_USART2_RTS_0, GPIO_MODE_50MHz) +#define GPIO_USART2_CK GPIO_ADJUST_MODE(GPIO_USART2_CK_0, GPIO_MODE_50MHz) + +/* SPI1 */ + +#define GPIO_SPI1_NSS GPIO_ADJUST_MODE(GPIO_SPI1_NSS_0, GPIO_MODE_50MHz) +#define GPIO_SPI1_SCK GPIO_ADJUST_MODE(GPIO_SPI1_SCK_0, GPIO_MODE_50MHz) +#define GPIO_SPI1_MISO GPIO_ADJUST_MODE(GPIO_SPI1_MISO_0, GPIO_MODE_50MHz) +#define GPIO_SPI1_MOSI GPIO_ADJUST_MODE(GPIO_SPI1_MOSI_0, GPIO_MODE_50MHz) + +/* USB */ + +#define GPIO_USB_DM GPIO_USB_DM_0 +#define GPIO_USB_DP GPIO_USB_DP_0 + +/* SDIO */ + +#define GPIO_SDIO_CK GPIO_ADJUST_MODE(GPIO_SDIO_CK_0, GPIO_MODE_50MHz) +#define GPIO_SDIO_CMD GPIO_ADJUST_MODE(GPIO_SDIO_CMD_0, GPIO_MODE_50MHz) +#define GPIO_SDIO_D0 GPIO_ADJUST_MODE(GPIO_SDIO_D0_0, GPIO_MODE_50MHz) +#define GPIO_SDIO_D1 GPIO_ADJUST_MODE(GPIO_SDIO_D1_0, GPIO_MODE_50MHz) +#define GPIO_SDIO_D2 GPIO_ADJUST_MODE(GPIO_SDIO_D2_0, GPIO_MODE_50MHz) +#define GPIO_SDIO_D3 GPIO_ADJUST_MODE(GPIO_SDIO_D3_0, GPIO_MODE_50MHz) + +/* TIM3 */ + +#define GPIO_TIM3_CH1IN GPIO_TIM3_CH1IN_0 +#define GPIO_TIM3_CH1OUT GPIO_ADJUST_MODE(GPIO_TIM3_CH1OUT_0, GPIO_MODE_50MHz) +#define GPIO_TIM3_CH2IN GPIO_TIM3_CH2IN_0 +#define GPIO_TIM3_CH2OUT GPIO_ADJUST_MODE(GPIO_TIM3_CH2OUT_0, GPIO_MODE_50MHz) +#define GPIO_TIM3_CH3IN GPIO_TIM3_CH3IN_0 +#define GPIO_TIM3_CH3OUT GPIO_ADJUST_MODE(GPIO_TIM3_CH3OUT_0, GPIO_MODE_50MHz) +#define GPIO_TIM3_CH4IN GPIO_TIM3_CH4IN_0 +#define GPIO_TIM3_CH4OUT GPIO_ADJUST_MODE(GPIO_TIM3_CH4OUT_0, GPIO_MODE_50MHz) + +/* FSMC NPS_A address pins (used by LCD srcs) */ + +#define GPIO_NPS_A16 GPIO_ADJUST_MODE(GPIO_NPS_A16_0, GPIO_MODE_50MHz) +#define GPIO_NPS_A17 GPIO_ADJUST_MODE(GPIO_NPS_A17_0, GPIO_MODE_50MHz) +#define GPIO_NPS_A18 GPIO_ADJUST_MODE(GPIO_NPS_A18_0, GPIO_MODE_50MHz) +#define GPIO_NPS_A19 GPIO_ADJUST_MODE(GPIO_NPS_A19_0, GPIO_MODE_50MHz) +#define GPIO_NPS_A20 GPIO_ADJUST_MODE(GPIO_NPS_A20_0, GPIO_MODE_50MHz) +#define GPIO_NPS_A21 GPIO_ADJUST_MODE(GPIO_NPS_A21_0, GPIO_MODE_50MHz) +#define GPIO_NPS_A22 GPIO_ADJUST_MODE(GPIO_NPS_A22_0, GPIO_MODE_50MHz) +#define GPIO_NPS_A23 GPIO_ADJUST_MODE(GPIO_NPS_A23_0, GPIO_MODE_50MHz) +#define GPIO_NPS_A24 GPIO_ADJUST_MODE(GPIO_NPS_A24_0, GPIO_MODE_50MHz) +#define GPIO_NPS_A25 GPIO_ADJUST_MODE(GPIO_NPS_A25_0, GPIO_MODE_50MHz) + +/* FSMC NPS_D pins (used by LCD srcs) */ + +#define GPIO_NPS_D0 GPIO_ADJUST_MODE(GPIO_NPS_D0_0, GPIO_MODE_50MHz) +#define GPIO_NPS_D1 GPIO_ADJUST_MODE(GPIO_NPS_D1_0, GPIO_MODE_50MHz) +#define GPIO_NPS_D10 GPIO_ADJUST_MODE(GPIO_NPS_D10_0, GPIO_MODE_50MHz) +#define GPIO_NPS_D11 GPIO_ADJUST_MODE(GPIO_NPS_D11_0, GPIO_MODE_50MHz) +#define GPIO_NPS_D12 GPIO_ADJUST_MODE(GPIO_NPS_D12_0, GPIO_MODE_50MHz) +#define GPIO_NPS_D13 GPIO_ADJUST_MODE(GPIO_NPS_D13_0, GPIO_MODE_50MHz) +#define GPIO_NPS_D14 GPIO_ADJUST_MODE(GPIO_NPS_D14_0, GPIO_MODE_50MHz) +#define GPIO_NPS_D15 GPIO_ADJUST_MODE(GPIO_NPS_D15_0, GPIO_MODE_50MHz) +#define GPIO_NPS_D2 GPIO_ADJUST_MODE(GPIO_NPS_D2_0, GPIO_MODE_50MHz) +#define GPIO_NPS_D3 GPIO_ADJUST_MODE(GPIO_NPS_D3_0, GPIO_MODE_50MHz) +#define GPIO_NPS_D4 GPIO_ADJUST_MODE(GPIO_NPS_D4_0, GPIO_MODE_50MHz) +#define GPIO_NPS_D5 GPIO_ADJUST_MODE(GPIO_NPS_D5_0, GPIO_MODE_50MHz) +#define GPIO_NPS_D6 GPIO_ADJUST_MODE(GPIO_NPS_D6_0, GPIO_MODE_50MHz) +#define GPIO_NPS_D7 GPIO_ADJUST_MODE(GPIO_NPS_D7_0, GPIO_MODE_50MHz) +#define GPIO_NPS_D8 GPIO_ADJUST_MODE(GPIO_NPS_D8_0, GPIO_MODE_50MHz) +#define GPIO_NPS_D9 GPIO_ADJUST_MODE(GPIO_NPS_D9_0, GPIO_MODE_50MHz) +#define GPIO_NPS_NE1 GPIO_ADJUST_MODE(GPIO_NPS_NE1_0, GPIO_MODE_50MHz) +#define GPIO_NPS_NOE GPIO_ADJUST_MODE(GPIO_NPS_NOE_0, GPIO_MODE_50MHz) +#define GPIO_NPS_NWE GPIO_ADJUST_MODE(GPIO_NPS_NWE_0, GPIO_MODE_50MHz) + +#endif /* __BOARDS_ARM_STM32_HYMINI_STM32V_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32f1/hymini-stm32v/scripts/Make.defs b/boards/arm/stm32f1/hymini-stm32v/scripts/Make.defs new file mode 100644 index 0000000000000..cc9f4fdc84e01 --- /dev/null +++ b/boards/arm/stm32f1/hymini-stm32v/scripts/Make.defs @@ -0,0 +1,46 @@ +############################################################################ +# boards/arm/stm32f1/hymini-stm32v/scripts/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/.config +include $(TOPDIR)/tools/Config.mk +include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs + +ifeq ($(CONFIG_STM32_DFU),y) + LDSCRIPT = ld.script.dfu +else + LDSCRIPT = ld.script +endif + +ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) + +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32f1/hymini-stm32v/scripts/ld.script b/boards/arm/stm32f1/hymini-stm32v/scripts/ld.script new file mode 100644 index 0000000000000..faa108e1d4b20 --- /dev/null +++ b/boards/arm/stm32f1/hymini-stm32v/scripts/ld.script @@ -0,0 +1,122 @@ +/**************************************************************************** + * boards/arm/stm32f1/hymini-stm32v/scripts/ld.script + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* The STM32F103VCT6 has 256Kb of FLASH beginning at address 0x0800:0000 and + * 48Kb of SRAM beginning at address 0x2000:0000. When booting from FLASH, + * FLASH memory is aliased to address 0x0000:0000 where the code expects to + * begin execution by jumping to the entry point in the 0x0800:0000 address + * range. + */ + +MEMORY +{ + flash (rx) : ORIGIN = 0x08000000, LENGTH = 256K + sram (rwx) : ORIGIN = 0x20000000, LENGTH = 48K +} + +OUTPUT_ARCH(arm) +EXTERN(_vectors) +ENTRY(_stext) +SECTIONS +{ + .text : { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > flash + + .init_section : ALIGN(4) { + _sinit = ABSOLUTE(.); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) + _einit = ABSOLUTE(.); + } > flash + + .ARM.extab : ALIGN(4) { + *(.ARM.extab*) + } > flash + + .ARM.exidx : ALIGN(4) { + __exidx_start = ABSOLUTE(.); + *(.ARM.exidx*) + __exidx_end = ABSOLUTE(.); + } > flash + + .tdata : { + _stdata = ABSOLUTE(.); + *(.tdata .tdata.* .gnu.linkonce.td.*); + _etdata = ABSOLUTE(.); + } > flash + + .tbss : { + _stbss = ABSOLUTE(.); + *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); + _etbss = ABSOLUTE(.); + } > flash + + _eronly = ABSOLUTE(.); + + /* The STM32F103VCT6 has 48Kb of SRAM beginning at the following address */ + + .data : ALIGN(4) { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > sram AT > flash + + .bss : ALIGN(4) { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + _ebss = ABSOLUTE(.); + } > sram + + /* Stabs debugging sections. */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/stm32f1/hymini-stm32v/src/CMakeLists.txt b/boards/arm/stm32f1/hymini-stm32v/src/CMakeLists.txt new file mode 100644 index 0000000000000..aa571e0ce0911 --- /dev/null +++ b/boards/arm/stm32f1/hymini-stm32v/src/CMakeLists.txt @@ -0,0 +1,43 @@ +# ############################################################################## +# boards/arm/stm32f1/hymini-stm32v/src/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(SRCS stm32_boot.c stm32_leds.c stm32_buttons.c stm32_spi.c stm32_usbdev.c) + +if(CONFIG_LCD_SSD1289) + list(APPEND SRCS stm32_ssd1289.c) +else() + if(CONFIG_LCD_R61505U) + list(APPEND SRCS stm32_r61505u.c) + endif() +endif() + +if(CONFIG_INPUT) + list(APPEND SRCS stm32_ts.c) +endif() + +if(CONFIG_USBMSC) + list(APPEND SRCS stm32_usbmsc.c) +endif() + +target_sources(board PRIVATE ${SRCS}) + +set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/ld.script") diff --git a/boards/arm/stm32f1/hymini-stm32v/src/Make.defs b/boards/arm/stm32f1/hymini-stm32v/src/Make.defs new file mode 100644 index 0000000000000..7285c60b44a59 --- /dev/null +++ b/boards/arm/stm32f1/hymini-stm32v/src/Make.defs @@ -0,0 +1,45 @@ +############################################################################ +# boards/arm/stm32f1/hymini-stm32v/src/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +CSRCS = stm32_boot.c stm32_leds.c stm32_buttons.c stm32_spi.c stm32_usbdev.c + +ifeq ($(CONFIG_LCD_SSD1289),y) +CSRCS += stm32_ssd1289.c +else +ifeq ($(CONFIG_LCD_R61505U),y) +CSRCS += stm32_r61505u.c +endif +endif + +ifeq ($(CONFIG_INPUT),y) +CSRCS += stm32_ts.c +endif + +ifeq ($(CONFIG_USBMSC),y) +CSRCS += stm32_usbmsc.c +endif + +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/hymini-stm32v/src/hymini-stm32v.h b/boards/arm/stm32f1/hymini-stm32v/src/hymini-stm32v.h similarity index 98% rename from boards/arm/stm32/hymini-stm32v/src/hymini-stm32v.h rename to boards/arm/stm32f1/hymini-stm32v/src/hymini-stm32v.h index e8966e76f0117..ba053fc552fff 100644 --- a/boards/arm/stm32/hymini-stm32v/src/hymini-stm32v.h +++ b/boards/arm/stm32f1/hymini-stm32v/src/hymini-stm32v.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/hymini-stm32v/src/hymini-stm32v.h + * boards/arm/stm32f1/hymini-stm32v/src/hymini-stm32v.h * * SPDX-License-Identifier: Apache-2.0 * @@ -32,7 +32,7 @@ #include -#include +#include /**************************************************************************** * Pre-processor Definitions diff --git a/boards/arm/stm32f1/hymini-stm32v/src/stm32_boot.c b/boards/arm/stm32f1/hymini-stm32v/src/stm32_boot.c new file mode 100644 index 0000000000000..934454ae8b896 --- /dev/null +++ b/boards/arm/stm32f1/hymini-stm32v/src/stm32_boot.c @@ -0,0 +1,264 @@ +/**************************************************************************** + * boards/arm/stm32f1/hymini-stm32v/src/stm32_boot.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include + +#include +#include +#include + +#include + +#ifdef CONFIG_STM32_SPI1 +# include +# include +#endif + +#ifdef CONFIG_STM32_SDIO +# include +# include +#endif + +#include "arm_internal.h" +#include "stm32.h" +#include "hymini-stm32v.h" + +#include /* Should always be included last due to dependencies */ + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* For now, don't build in any SPI1 support -- NSH is not using it */ + +#undef CONFIG_STM32_SPI1 + +/* Check if we can have USB device in NSH */ + +#define NSH_HAVEUSBDEV 1 + +/* Can't support USB features if USB is not enabled */ + +#ifndef CONFIG_USBDEV +# undef NSH_HAVEUSBDEV +#endif + +/* Check if we can have MMC/SD slot support in NSH */ + +#define NSH_HAVEMMCSD 1 + +/* Can't support MMC/SD features if mountpoints are disabled or if SDIO + * support is not enabled. + */ + +#if defined(CONFIG_DISABLE_MOUNTPOINT) || !defined(CONFIG_STM32_SDIO) +# undef NSH_HAVEMMCSD +#endif + +#ifdef NSH_HAVEMMCSD +# ifndef CONFIG_NSH_MMCSDMINOR +# define CONFIG_NSH_MMCSDMINOR 0 +# endif +# if defined(CONFIG_NSH_MMCSDSLOTNO) && CONFIG_NSH_MMCSDSLOTNO != 0 +# error "Only one MMC/SD slot" +# undef CONFIG_NSH_MMCSDSLOTNO +# endif +# ifndef CONFIG_NSH_MMCSDSLOTNO +# define CONFIG_NSH_MMCSDSLOTNO 0 +# endif +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#ifdef CONFIG_MMCSD +static struct sdio_dev_s *g_sdiodev; +static bool g_sd_inserted; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: nsh_cdinterrupt + * + * Description: + * Card detect interrupt handler. + * + ****************************************************************************/ + +#ifdef NSH_HAVEMMCSD +static int nsh_cdinterrupt(int irq, void *context, void *arg) +{ + bool present; + + present = !stm32_gpioread(GPIO_SD_CD); + if (present != g_sd_inserted) + { + sdio_mediachange(g_sdiodev, present); + g_sd_inserted = present; + } + + return OK; +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_boardinitialize + * + * Description: + * All STM32 architectures must provide the following entry point. This + * entry point is called early in the initialization -- after all memory + * has been configured and mapped but before any devices have been + * initialized. + * + ****************************************************************************/ + +void stm32_boardinitialize(void) +{ + /* Configure SPI chip selects if + * 1) SPI is not disabled, and + * 2) the weak function stm32_spidev_initialize() has been brought into + * the link. + */ + +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) + if (stm32_spidev_initialize) + { + stm32_spidev_initialize(); + } +#endif + + /* Initialize USB is 1) USBDEV is selected, 2) the USB controller is not + * disabled, and 3) the weak function stm32_usbinitialize() has been + * brought into the build. + */ + +#if defined(CONFIG_USBDEV) && defined(CONFIG_STM32_USB) + if (stm32_usbinitialize) + { + stm32_usbinitialize(); + } +#endif + + /* Configure on-board LEDs if LED support has been selected. */ + +#ifdef CONFIG_ARCH_LEDS + board_autoled_initialize(); +#endif +} + +/**************************************************************************** + * Name: board_late_initialize + * + * Description: + * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_late_initialize(). board_late_initialize() will + * be called immediately after up_initialize() is called and just before + * the initial application is started. This additional initialization + * phase may be used, for example, to initialize board-specific device + * drivers. + * + ****************************************************************************/ + +#ifdef CONFIG_BOARD_LATE_INITIALIZE +void board_late_initialize(void) +{ + int ret; + +#ifdef NSH_HAVEMMCSD + /* Configure the card detect GPIO */ + + stm32_configgpio(GPIO_SD_CD); + + /* Register an interrupt handler for the card detect pin */ + + stm32_gpiosetevent(GPIO_SD_CD, true, true, true, nsh_cdinterrupt, NULL); + + /* Mount the SDIO-based MMC/SD block driver */ + + /* First, get an instance of the SDIO interface */ + + syslog(LOG_INFO, "Initializing SDIO slot %d\n", + CONFIG_NSH_MMCSDSLOTNO); + + g_sdiodev = sdio_initialize(CONFIG_NSH_MMCSDSLOTNO); + if (!g_sdiodev) + { + syslog(LOG_ERR, "ERROR: Failed to initialize SDIO slot %d\n", + CONFIG_NSH_MMCSDSLOTNO); + return; + } + + /* Now bind the SDIO interface to the MMC/SD driver */ + + syslog(LOG_INFO, "Bind SDIO to the MMC/SD driver, minor=%d\n", + CONFIG_NSH_MMCSDMINOR); + + ret = mmcsd_slotinitialize(CONFIG_NSH_MMCSDMINOR, g_sdiodev); + if (ret != OK) + { + syslog(LOG_ERR, + "ERROR: Failed to bind SDIO to the MMC/SD driver: %d\n", + ret); + return; + } + + syslog(LOG_INFO, "Successfully bound SDIO to the MMC/SD driver\n"); + + /* Use SD card detect pin to check if a card is inserted */ + + g_sd_inserted = !stm32_gpioread(GPIO_SD_CD); + _info("Card detect : %hhu\n", g_sd_inserted); + + sdio_mediachange(g_sdiodev, g_sd_inserted); +#endif + +#ifdef CONFIG_INPUT + /* Initialize the touchscreen */ + + ret = stm32_tsc_setup(0); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_tsc_setup failed: %d\n", ret); + } +#endif + + UNUSED(ret); +} +#endif diff --git a/boards/arm/stm32f1/hymini-stm32v/src/stm32_buttons.c b/boards/arm/stm32f1/hymini-stm32v/src/stm32_buttons.c new file mode 100644 index 0000000000000..14082bc395a3e --- /dev/null +++ b/boards/arm/stm32f1/hymini-stm32v/src/stm32_buttons.c @@ -0,0 +1,140 @@ +/**************************************************************************** + * boards/arm/stm32f1/hymini-stm32v/src/stm32_buttons.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include + +#include "stm32_gpio.h" +#include "hymini-stm32v.h" + +#ifdef CONFIG_ARCH_BUTTONS + +#include /* Should always be included last due to dependencies */ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_button_initialize + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. + * + ****************************************************************************/ + +uint32_t board_button_initialize(void) +{ + stm32_configgpio(GPIO_BTN_KEYA); + stm32_configgpio(GPIO_BTN_KEYB); + return NUM_BUTTONS; +} + +/**************************************************************************** + * Name: board_buttons + ****************************************************************************/ + +uint32_t board_buttons(void) +{ + uint32_t ret = 0; + bool value; + + /* Check that state of each key */ + + /* Pin is pulled up */ + + value = stm32_gpioread(GPIO_BTN_KEYA); + if (!value) + { + /* Button pressed */ + + ret = 1 << BUTTON_KEYA; + } + + /* Pin is pulled down */ + + value = stm32_gpioread(GPIO_BTN_KEYB); + if (value) + { + /* Button pressed */ + + ret |= 1 << BUTTON_KEYB; + } + + return ret; +} + +/**************************************************************************** + * Button support. + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. + * + * After board_button_initialize() has been called, board_buttons() may be + * called to collect the state of all buttons. board_buttons() returns an + * 32-bit bit set with each bit associated with a button. See the + * BUTTON_*_BIT and JOYSTICK_*_BIT definitions in board.h for the meaning + * of each bit. + * + * board_button_irq() may be called to register an interrupt handler that + * will be called when a button is depressed or released. The ID value is a + * button enumeration value that uniquely identifies a button resource. See + * the BUTTON_* definitions in board.h for the meaning of enumeration + * value. + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_IRQBUTTONS +int board_button_irq(int id, xcpt_t irqhandler, void *arg) +{ + uint32_t pinset = GPIO_BTN_KEYA; + int ret = -EINVAL; + + if (id == 1) + { + pinset = GPIO_BTN_KEYB; + } + + if (id < 2) + { + ret = stm32_gpiosetevent(pinset, true, true, true, irqhandler, arg); + } + + return ret; +} +#endif +#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/stm32f1/hymini-stm32v/src/stm32_leds.c b/boards/arm/stm32f1/hymini-stm32v/src/stm32_leds.c new file mode 100644 index 0000000000000..166971c8b24e7 --- /dev/null +++ b/boards/arm/stm32f1/hymini-stm32v/src/stm32_leds.c @@ -0,0 +1,224 @@ +/**************************************************************************** + * boards/arm/stm32f1/hymini-stm32v/src/stm32_leds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32.h" +#include "hymini-stm32v.h" + +#include /* Should always be included last due to dependencies */ + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* The following definitions map the encoded LED setting to GPIO settings */ + +#define HYMINI_STM32_LED1 (1 << 0) +#define HYMINI_STM32_LED2 (1 << 1) + +#define ON_SETBITS_SHIFT (0) +#define ON_CLRBITS_SHIFT (4) +#define OFF_SETBITS_SHIFT (8) +#define OFF_CLRBITS_SHIFT (12) + +#define ON_BITS(v) ((v) & 0xff) +#define OFF_BITS(v) (((v) >> 8) & 0x0ff) +#define SETBITS(b) ((b) & 0x0f) +#define CLRBITS(b) (((b) >> 4) & 0x0f) + +#define ON_SETBITS(v) (SETBITS(ON_BITS(v)) +#define ON_CLRBITS(v) (CLRBITS(ON_BITS(v)) +#define OFF_SETBITS(v) (SETBITS(OFF_BITS(v)) +#define OFF_CLRBITS(v) (CLRBITS(OFF_BITS(v)) + +/* On: !LED1 + !LED2 Off: - */ + +#define LED_STARTED_ON_SETBITS ((0) << ON_SETBITS_SHIFT) +#define LED_STARTED_ON_CLRBITS ((HYMINI_STM32_LED1|HYMINI_STM32_LED2) << ON_CLRBITS_SHIFT) +#define LED_STARTED_OFF_SETBITS (0 << OFF_SETBITS_SHIFT) +#define LED_STARTED_OFF_CLRBITS (0 << OFF_CLRBITS_SHIFT) + +/* On: LED1+!LED2 Off: N/A */ + +#define LED_HEAPALLOCATE_ON_SETBITS ((HYMINI_STM32_LED1) << ON_SETBITS_SHIFT) +#define LED_HEAPALLOCATE_ON_CLRBITS ((HYMINI_STM32_LED2) << ON_CLRBITS_SHIFT) +#define LED_HEAPALLOCATE_OFF_SETBITS (0) +#define LED_HEAPALLOCATE_OFF_CLRBITS (0) + +/* On: LED2+!LED1 Off: N/A */ + +#define LED_IRQSENABLED_ON_SETBITS ((HYMINI_STM32_LED2) << ON_SETBITS_SHIFT) +#define LED_IRQSENABLED_ON_CLRBITS ((HYMINI_STM32_LED1) << ON_CLRBITS_SHIFT) +#define LED_IRQSENABLED_OFF_SETBITS (0) +#define LED_IRQSENABLED_OFF_CLRBITS (0) + +/* On: LED1+!LED2 Off: N/A */ + +#define LED_STACKCREATED_ON_SETBITS ((HYMINI_STM32_LED1) << ON_SETBITS_SHIFT) +#define LED_STACKCREATED_ON_CLRBITS ((HYMINI_STM32_LED2) << ON_CLRBITS_SHIFT) +#define LED_STACKCREATED_OFF_SETBITS (0) +#define LED_STACKCREATED_OFF_CLRBITS (0) + +/* On: !LED1 Off: LED1 */ + +#define LED_INIRQ_ON_SETBITS ((0) << ON_SETBITS_SHIFT) +#define LED_INIRQ_ON_CLRBITS ((HYMINI_STM32_LED1) << ON_CLRBITS_SHIFT) +#define LED_INIRQ_OFF_SETBITS ((HYMINI_STM32_LED1) << OFF_SETBITS_SHIFT) +#define LED_INIRQ_OFF_CLRBITS ((0) << OFF_CLRBITS_SHIFT) + +/* On: LED2 Off: !LED2 */ + +#define LED_SIGNAL_ON_SETBITS ((HYMINI_STM32_LED2) << ON_SETBITS_SHIFT) +#define LED_SIGNAL_ON_CLRBITS ((0) << ON_CLRBITS_SHIFT) +#define LED_SIGNAL_OFF_SETBITS ((0) << OFF_SETBITS_SHIFT) +#define LED_SIGNAL_OFF_CLRBITS ((HYMINI_STM32_LED2) << OFF_CLRBITS_SHIFT) + +/* On: LED1+LED2 Off: - */ + +#define LED_ASSERTION_ON_SETBITS ((HYMINI_STM32_LED2|HYMINI_STM32_LED2) << ON_SETBITS_SHIFT) +#define LED_ASSERTION_ON_CLRBITS ((0) << ON_CLRBITS_SHIFT) +#define LED_ASSERTION_OFF_SETBITS ((0) << OFF_SETBITS_SHIFT) +#define LED_ASSERTION_OFF_CLRBITS ((0) << OFF_CLRBITS_SHIFT) + +/* On: LED1 Off: LED2 */ + +#define LED_PANIC_ON_SETBITS ((HYMINI_STM32_LED1) << ON_SETBITS_SHIFT) +#define LED_PANIC_ON_CLRBITS ((HYMINI_STM32_LED2) << ON_CLRBITS_SHIFT) +#define LED_PANIC_OFF_SETBITS ((HYMINI_STM32_LED2) << OFF_SETBITS_SHIFT) +#define LED_PANIC_OFF_CLRBITS ((HYMINI_STM32_LED1) << OFF_CLRBITS_SHIFT) + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static const uint16_t g_ledbits[8] = +{ + (LED_STARTED_ON_SETBITS | LED_STARTED_ON_CLRBITS | + LED_STARTED_OFF_SETBITS | LED_STARTED_OFF_CLRBITS), + + (LED_HEAPALLOCATE_ON_SETBITS | LED_HEAPALLOCATE_ON_CLRBITS | + LED_HEAPALLOCATE_OFF_SETBITS | LED_HEAPALLOCATE_OFF_CLRBITS), + + (LED_IRQSENABLED_ON_SETBITS | LED_IRQSENABLED_ON_CLRBITS | + LED_IRQSENABLED_OFF_SETBITS | LED_IRQSENABLED_OFF_CLRBITS), + + (LED_STACKCREATED_ON_SETBITS | LED_STACKCREATED_ON_CLRBITS | + LED_STACKCREATED_OFF_SETBITS | LED_STACKCREATED_OFF_CLRBITS), + + (LED_INIRQ_ON_SETBITS | LED_INIRQ_ON_CLRBITS | + LED_INIRQ_OFF_SETBITS | LED_INIRQ_OFF_CLRBITS), + + (LED_SIGNAL_ON_SETBITS | LED_SIGNAL_ON_CLRBITS | + LED_SIGNAL_OFF_SETBITS | LED_SIGNAL_OFF_CLRBITS), + + (LED_ASSERTION_ON_SETBITS | LED_ASSERTION_ON_CLRBITS | + LED_ASSERTION_OFF_SETBITS | LED_ASSERTION_OFF_CLRBITS), + + (LED_PANIC_ON_SETBITS | LED_PANIC_ON_CLRBITS | + LED_PANIC_OFF_SETBITS | LED_PANIC_OFF_CLRBITS) +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +static inline void led_clrbits(unsigned int clrbits) +{ + if ((clrbits & HYMINI_STM32_LED1) != 0) + { + stm32_gpiowrite(GPIO_LED1, false); + } + + if ((clrbits & HYMINI_STM32_LED2) != 0) + { + stm32_gpiowrite(GPIO_LED2, false); + } +} + +static inline void led_setbits(unsigned int setbits) +{ + if ((setbits & HYMINI_STM32_LED1) != 0) + { + stm32_gpiowrite(GPIO_LED1, true); + } + + if ((setbits & HYMINI_STM32_LED2) != 0) + { + stm32_gpiowrite(GPIO_LED2, true); + } +} + +static void led_setonoff(unsigned int bits) +{ + led_clrbits(CLRBITS(bits)); + led_setbits(SETBITS(bits)); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_autoled_initialize + ****************************************************************************/ + +#ifdef CONFIG_ARCH_LEDS +void board_autoled_initialize(void) +{ + /* Configure LED1 & LED2 GPIOs for output */ + + stm32_configgpio(GPIO_LED1); + stm32_configgpio(GPIO_LED2); +} + +/**************************************************************************** + * Name: board_autoled_on + ****************************************************************************/ + +void board_autoled_on(int led) +{ + led_setonoff(ON_BITS(g_ledbits[led])); +} + +/**************************************************************************** + * Name: board_autoled_off + ****************************************************************************/ + +void board_autoled_off(int led) +{ + led_setonoff(OFF_BITS(g_ledbits[led])); +} + +#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/hymini-stm32v/src/stm32_r61505u.c b/boards/arm/stm32f1/hymini-stm32v/src/stm32_r61505u.c similarity index 99% rename from boards/arm/stm32/hymini-stm32v/src/stm32_r61505u.c rename to boards/arm/stm32f1/hymini-stm32v/src/stm32_r61505u.c index 531e96e91b571..a43d7b85e278f 100644 --- a/boards/arm/stm32/hymini-stm32v/src/stm32_r61505u.c +++ b/boards/arm/stm32f1/hymini-stm32v/src/stm32_r61505u.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/hymini-stm32v/src/stm32_r61505u.c + * boards/arm/stm32f1/hymini-stm32v/src/stm32_r61505u.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f1/hymini-stm32v/src/stm32_spi.c b/boards/arm/stm32f1/hymini-stm32v/src/stm32_spi.c new file mode 100644 index 0000000000000..6e88b17755f22 --- /dev/null +++ b/boards/arm/stm32f1/hymini-stm32v/src/stm32_spi.c @@ -0,0 +1,148 @@ +/**************************************************************************** + * boards/arm/stm32f1/hymini-stm32v/src/stm32_spi.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include + +#include "arm_internal.h" +#include "chip.h" +#include "stm32.h" +#include "hymini-stm32v.h" + +#include /* Should always be included last due to dependencies */ + +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_spidev_initialize + * + * Description: + * Called to configure SPI chip select GPIO pins for the HY-MiniSTM32 + * board. + * + ****************************************************************************/ + +void stm32_spidev_initialize(void) +{ + /* NOTE: Clocking for SPI1 and/or SPI2 was already provided in stm32_rcc.c. + * Configurations of SPI pins is performed in stm32_spi.c. + * Here, we only initialize chip select pins unique to the board + * architecture. + */ + +#ifdef CONFIG_STM32_SPI1 + /* Configure the SPI-based touch screen CS GPIO */ + + spiinfo("Configure GPIO for SPI1/CS\n"); + stm32_configgpio(GPIO_TS_CS); +#endif +} + +/**************************************************************************** + * Name: stm32_spi1/2/3select and stm32_spi1/2/3status + * + * Description: + * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status + * must be provided by board-specific logic. They are implementations of + * the select and status methods of the SPI interface defined by struct + * spi_ops_s (see include/nuttx/spi/spi.h). All other methods (including + * stm32_spibus_initialize()) are provided by common STM32 logic. + * To use this common SPI logic on your board: + * + * 1. Provide logic in stm32_boardinitialize() to configure SPI chip select + * pins. + * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() functions + * in your board-specific logic. These functions will perform chip + * selection and status operations using GPIOs in the way your board is + * configured. + * 3. Add a calls to stm32_spibus_initialize() in your low level + * application initialization logic + * 4. The handle returned by stm32_spibus_initialize() may then be used to + * bind the SPI driver to higher level logic (e.g., calling + * mmcsd_spislotinitialize(), for example, will bind the SPI driver to + * the SPI MMC/SD driver). + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_SPI1 +void stm32_spi1select(struct spi_dev_s *dev, + uint32_t devid, bool selected) +{ + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); + + if (devid == SPIDEV_TOUCHSCREEN(0)) + { + /* Set the GPIO low to select and high to de-select */ + + stm32_gpiowrite(GPIO_TS_CS, !selected); + } +} + +uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) +{ + return SPI_STATUS_PRESENT; +} +#endif + +#ifdef CONFIG_STM32_SPI2 +void stm32_spi2select(struct spi_dev_s *dev, + uint32_t devid, bool selected) +{ + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); +} + +uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) +{ + return SPI_STATUS_PRESENT; +} +#endif + +#ifdef CONFIG_STM32_SPI3 +void stm32_spi3select(struct spi_dev_s *dev, + uint32_t devid, bool selected) +{ + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); +} + +uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid) +{ + return SPI_STATUS_PRESENT; +} +#endif + +#endif /* CONFIG_STM32_SPI1 || CONFIG_STM32_SPI2 */ diff --git a/boards/arm/stm32f1/hymini-stm32v/src/stm32_ssd1289.c b/boards/arm/stm32f1/hymini-stm32v/src/stm32_ssd1289.c new file mode 100644 index 0000000000000..679d23535de72 --- /dev/null +++ b/boards/arm/stm32f1/hymini-stm32v/src/stm32_ssd1289.c @@ -0,0 +1,489 @@ +/**************************************************************************** + * boards/arm/stm32f1/hymini-stm32v/src/stm32_ssd1289.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include "arm_internal.h" +#include "stm32.h" +#include "hymini-stm32v.h" + +#include /* Should always be included last due to dependencies */ + +#ifdef CONFIG_LCD_SSD1289 + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +#ifndef CONFIG_STM32_FSMC +# error "CONFIG_STM32_FSMC is required to use the LCD" +#endif + +/* Color depth and format */ + +#define LCD_BPP 16 +#define LCD_COLORFMT FB_FMT_RGB16_565 + +/* Display Resolution */ + +#if defined(CONFIG_LCD_LANDSCAPE) +# define LCD_XRES 320 +# define LCD_YRES 240 +#else +# define LCD_XRES 240 +# define LCD_YRES 320 +#endif + +#define LCD_BL_TIMER_PERIOD 8999 + +/* LCD is connected to the FSMC_Bank1_NOR/SRAM1 and NE1 is used as ship + * select signal + */ + +/* RS <==> A16 */ + +#define LCD_INDEX 0x60000000 /* RS = 0 */ +#define LCD_DATA 0x60020000 /* RS = 1 */ + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/* Low Level LCD access */ + +static void stm32_select(struct ssd1289_lcd_s *dev); +static void stm32_deselect(struct ssd1289_lcd_s *dev); +static void stm32_index(struct ssd1289_lcd_s *dev, uint8_t index); +#ifndef CONFIG_SSD1289_WRONLY +static uint16_t stm32_read(struct ssd1289_lcd_s *dev); +#endif +static void stm32_write(struct ssd1289_lcd_s *dev, uint16_t data); +static void stm32_backlight(struct ssd1289_lcd_s *dev, int power); + +static void stm32_extmemgpios(const uint16_t *gpios, int ngpios); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +const uint16_t fsmc_gpios[] = +{ + /* A16... A24 */ + + GPIO_NPS_A16, GPIO_NPS_A17, GPIO_NPS_A18, GPIO_NPS_A19, GPIO_NPS_A20, + GPIO_NPS_A21, GPIO_NPS_A22, GPIO_NPS_A23, + + /* D0... D15 */ + + GPIO_NPS_D0, GPIO_NPS_D1, GPIO_NPS_D2, GPIO_NPS_D3, GPIO_NPS_D4, + GPIO_NPS_D5, GPIO_NPS_D6, GPIO_NPS_D7, GPIO_NPS_D8, GPIO_NPS_D9, + GPIO_NPS_D10, GPIO_NPS_D11, GPIO_NPS_D12, GPIO_NPS_D13, GPIO_NPS_D14, + GPIO_NPS_D15, + + /* NOE, NWE */ + + GPIO_NPS_NOE, GPIO_NPS_NWE, + + /* NE1 */ + + GPIO_NPS_NE1 +}; + +#define NGPIOS (sizeof(fsmc_gpios)/sizeof(uint16_t)) + +/* This is the driver state structure */ + +static struct ssd1289_lcd_s g_ssd1289 = +{ + .select = stm32_select, + .deselect = stm32_deselect, + .index = stm32_index, +#ifndef CONFIG_SSD1289_WRONLY + .read = stm32_read, +#endif + .write = stm32_write, + .backlight = stm32_backlight +}; + +/* The saved instance of the LCD driver */ + +static struct lcd_dev_s *g_ssd1289drvr; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_select + * + * Description: + * Select the LCD device + * + ****************************************************************************/ + +static void stm32_select(struct ssd1289_lcd_s *dev) +{ + /* Does not apply to this hardware */ +} + +/**************************************************************************** + * Name: stm32_deselect + * + * Description: + * De-select the LCD device + * + ****************************************************************************/ + +static void stm32_deselect(struct ssd1289_lcd_s *dev) +{ + /* Does not apply to this hardware */ +} + +/**************************************************************************** + * Name: stm32_index + * + * Description: + * Set the index register + * + ****************************************************************************/ + +static void stm32_index(struct ssd1289_lcd_s *dev, uint8_t index) +{ + putreg16((uint16_t)index, LCD_INDEX); +} + +/**************************************************************************** + * Name: stm32_read + * + * Description: + * Read LCD data (GRAM data or register contents) + * + ****************************************************************************/ + +#ifndef CONFIG_SSD1289_WRONLY +static uint16_t stm32_read(struct ssd1289_lcd_s *dev) +{ + return getreg16(LCD_DATA); +} +#endif + +/**************************************************************************** + * Name: stm32_write + * + * Description: + * Write LCD data (GRAM data or register contents) + * + ****************************************************************************/ + +static void stm32_write(struct ssd1289_lcd_s *dev, uint16_t data) +{ + putreg16((uint16_t)data, LCD_DATA); +} + +/**************************************************************************** + * Name: stm32_backlight + * + * Description: + * Enable/disable LCD panel power (0: full off - CONFIG_LCD_MAXPOWER: + * full on). + * Used here to set pwm duty on timer used for backlight. + * + ****************************************************************************/ + +static void stm32_backlight(struct ssd1289_lcd_s *dev, int power) +{ + DEBUGASSERT(power <= CONFIG_LCD_MAXPOWER); + + /* Set new power level */ + + if (power > 0) + { + uint32_t duty; + + /* Calculate the new backlight duty. It is a fraction of the timer + * period based on the ration of the current power setting to the + * maximum power setting. + */ + + duty = ((uint32_t)LCD_BL_TIMER_PERIOD * (uint32_t)power) / + CONFIG_LCD_MAXPOWER; + if (duty >= LCD_BL_TIMER_PERIOD) + { + duty = LCD_BL_TIMER_PERIOD - 1; + } + + putreg16((uint16_t)duty, STM32_TIM3_CCR2); + } + else + { + putreg16((uint16_t)0, STM32_TIM3_CCR2); + } +} + +static void init_lcd_backlight(void) +{ + uint16_t ccmr; + uint16_t ccer; + + /* Configure PB5 as TIM3 CH2 output */ + + stm32_configgpio(GPIO_TIM3_CH2OUT); + + /* Enable timer 3 clocking */ + + modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM3EN); + + /* Reset timer 3 */ + + modifyreg32(STM32_RCC_APB1RSTR, 0, RCC_APB1RSTR_TIM3RST); + modifyreg32(STM32_RCC_APB1RSTR, RCC_APB1RSTR_TIM3RST, 0); + + /* Reset the Counter Mode and set the clock division */ + + putreg16(0, STM32_TIM3_CR1); + + /* Set the Autoreload value */ + + putreg16(LCD_BL_TIMER_PERIOD, STM32_TIM3_ARR); + + /* Set the Prescaler value */ + + putreg16(0, STM32_TIM3_PSC); + + /* Generate an update event to reload the Prescaler value immediately */ + + putreg16(ATIM_EGR_UG, STM32_TIM3_EGR); + + /* Disable the Channel 2 */ + + ccer = getreg16(STM32_TIM3_CCER); + ccer &= ~ATIM_CCER_CC2E; + putreg16(ccer, STM32_TIM3_CCER); + + /* Select the Output Compare Mode Bits */ + + ccmr = getreg16(STM32_TIM3_CCMR1); + ccmr &= ATIM_CCMR1_OC2M_MASK; + ccmr |= (ATIM_CCMR_MODE_PWM1 << ATIM_CCMR1_OC2M_SHIFT); + + putreg16(0, STM32_TIM3_CCR2); + + /* Select the output polarity level == HIGH */ + + ccer &= ~ATIM_CCER_CC2P; + + /* Enable channel 2 */ + + ccer |= ATIM_CCER_CC2E; + + /* Write the timer configuration */ + + putreg16(ccmr, STM32_TIM3_CCMR1); + putreg16(ccer, STM32_TIM3_CCER); + + /* Set the auto preload enable bit */ + + modifyreg16(STM32_TIM3_CR1, 0, ATIM_CR1_ARPE); + + /* Enable Backlight Timer !!!! */ + + modifyreg16(STM32_TIM3_CR1, 0, ATIM_CR1_CEN); + + /* Dump timer3 registers */ + + lcdinfo("APB1ENR: %08" PRIx32 "\n", getreg32(STM32_RCC_APB1ENR)); + lcdinfo("CR1: %04" PRIx32 "\n", getreg32(STM32_TIM3_CR1)); + lcdinfo("CR2: %04" PRIx32 "\n", getreg32(STM32_TIM3_CR2)); + lcdinfo("SMCR: %04" PRIx32 "\n", getreg32(STM32_TIM3_SMCR)); + lcdinfo("DIER: %04" PRIx32 "\n", getreg32(STM32_TIM3_DIER)); + lcdinfo("SR: %04" PRIx32 "\n", getreg32(STM32_TIM3_SR)); + lcdinfo("EGR: %04" PRIx32 "\n", getreg32(STM32_TIM3_EGR)); + lcdinfo("CCMR1: %04" PRIx32 "\n", getreg32(STM32_TIM3_CCMR1)); + lcdinfo("CCMR2: %04" PRIx32 "\n", getreg32(STM32_TIM3_CCMR2)); + lcdinfo("CCER: %04" PRIx32 "\n", getreg32(STM32_TIM3_CCER)); + lcdinfo("CNT: %04" PRIx32 "\n", getreg32(STM32_TIM3_CNT)); + lcdinfo("PSC: %04" PRIx32 "\n", getreg32(STM32_TIM3_PSC)); + lcdinfo("ARR: %04" PRIx32 "\n", getreg32(STM32_TIM3_ARR)); + lcdinfo("CCR1: %04" PRIx32 "\n", getreg32(STM32_TIM3_CCR1)); + lcdinfo("CCR2: %04" PRIx32 "\n", getreg32(STM32_TIM3_CCR2)); + lcdinfo("CCR3: %04" PRIx32 "\n", getreg32(STM32_TIM3_CCR3)); + lcdinfo("CCR4: %04" PRIx32 "\n", getreg32(STM32_TIM3_CCR4)); + lcdinfo("CCR4: %04" PRIx32 "\n", getreg32(STM32_TIM3_CCR4)); + lcdinfo("CCR4: %04" PRIx32 "\n", getreg32(STM32_TIM3_CCR4)); + lcdinfo("DMAR: %04" PRIx32 "\n", getreg32(STM32_TIM3_DMAR)); +} + +/**************************************************************************** + * Name: stm32_selectlcd + * + * Description: + * Initialize the memory controller (FSMC) + * + ****************************************************************************/ + +static void stm32_selectlcd(void) +{ + /* Configure new GPIO state */ + + stm32_extmemgpios(fsmc_gpios, NGPIOS); + + /* Enable AHB clocking to the FSMC */ + + stm32_fsmc_enable(); + + /* Bank1 NOR/SRAM control register configuration */ + + putreg32(FSMC_BCR_SRAM | FSMC_BCR_MWID16 | FSMC_BCR_WREN, STM32_FSMC_BCR1); + + /* Bank1 NOR/SRAM timing register configuration */ + + putreg32(FSMC_BTR_ADDSET(1) | FSMC_BTR_ADDHLD(1) | FSMC_BTR_DATAST(2) | + FSMC_BTR_BUSTURN(1) | FSMC_BTR_CLKDIV(1) | FSMC_BTR_DATLAT(2) | + FSMC_BTR_ACCMODA, + STM32_FSMC_BTR1); + + /* As ext mode is not active the write timing is ignored!! */ + + putreg32(0xffffffff, STM32_FSMC_BWTR1); + + /* Enable the bank by setting the MBKEN bit */ + + putreg32(FSMC_BCR_MBKEN | FSMC_BCR_SRAM | FSMC_BCR_MWID16 | FSMC_BCR_WREN, + STM32_FSMC_BCR1); +} + +/**************************************************************************** + * Name: stm32_extmemgpios + * + * Description: + * Initialize GPIOs for NOR or SRAM + * + ****************************************************************************/ + +static void stm32_extmemgpios(const uint16_t *gpios, int ngpios) +{ + int i; + + /* Configure GPIOs */ + + for (i = 0; i < ngpios; i++) + { + stm32_configgpio(gpios[i]); + } +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_lcd_initialize + * + * Description: + * Initialize the LCD video hardware. The initial state of the LCD is + * fully initialized, display memory cleared, and the LCD ready to use, + * but with the power setting at 0 (full off). + * + ****************************************************************************/ + +int board_lcd_initialize(void) +{ + /* Only initialize the driver once */ + + if (!g_ssd1289drvr) + { + lcdinfo("Initializing\n"); + + init_lcd_backlight(); + + /* Configure GPIO pins and configure the FSMC to support the LCD */ + + stm32_selectlcd(); + + /* Configure and enable the LCD */ + + up_mdelay(50); + g_ssd1289drvr = ssd1289_lcdinitialize(&g_ssd1289); + if (!g_ssd1289drvr) + { + lcderr("ERROR: ssd1289_lcdinitialize failed\n"); + return -ENODEV; + } + } + + /* Turn the display off */ + + g_ssd1289drvr->setpower(g_ssd1289drvr, 0); + return OK; +} + +/**************************************************************************** + * Name: board_lcd_getdev + * + * Description: + * Return a a reference to the LCD object for the specified LCD. This + * allows support for multiple LCD devices. + * + ****************************************************************************/ + +struct lcd_dev_s *board_lcd_getdev(int lcddev) +{ + DEBUGASSERT(lcddev == 0); + return g_ssd1289drvr; +} + +/**************************************************************************** + * Name: board_lcd_uninitialize + * + * Description: + * Uninitialize the LCD support + * + ****************************************************************************/ + +void board_lcd_uninitialize(void) +{ + /* Turn the display off */ + + g_ssd1289drvr->setpower(g_ssd1289drvr, 0); +} + +#endif /* CONFIG_LCD_SSD1289 */ diff --git a/boards/arm/stm32/hymini-stm32v/src/stm32_ts.c b/boards/arm/stm32f1/hymini-stm32v/src/stm32_ts.c similarity index 98% rename from boards/arm/stm32/hymini-stm32v/src/stm32_ts.c rename to boards/arm/stm32f1/hymini-stm32v/src/stm32_ts.c index e7e7a8720c3f4..86b9a9137e8cb 100644 --- a/boards/arm/stm32/hymini-stm32v/src/stm32_ts.c +++ b/boards/arm/stm32f1/hymini-stm32v/src/stm32_ts.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/hymini-stm32v/src/stm32_ts.c + * boards/arm/stm32f1/hymini-stm32v/src/stm32_ts.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f1/hymini-stm32v/src/stm32_usbdev.c b/boards/arm/stm32f1/hymini-stm32v/src/stm32_usbdev.c new file mode 100644 index 0000000000000..108df51135fad --- /dev/null +++ b/boards/arm/stm32f1/hymini-stm32v/src/stm32_usbdev.c @@ -0,0 +1,105 @@ +/**************************************************************************** + * boards/arm/stm32f1/hymini-stm32v/src/stm32_usbdev.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include + +#include "arm_internal.h" +#include "stm32.h" +#include "hymini-stm32v.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_usbinitialize + * + * Description: + * Called to setup USB-related GPIO pins for the Hy-Mini STM32v board. + * + ****************************************************************************/ + +void stm32_usbinitialize(void) +{ + uinfo("called\n"); + + /* USB Soft Connect Pullup */ + + stm32_configgpio(GPIO_USB_PULLUP); +} + +/**************************************************************************** + * Name: stm32_usbpullup + * + * Description: + * If USB is supported and the board supports a pullup via GPIO + * (for USB software connect and disconnect), then the board software must + * provide stm32_pullup. + * See include/nuttx/usb/usbdev.h for additional description of this + * method. Alternatively, if no pull-up GPIO the following EXTERN can + * be redefined to be NULL. + * + ****************************************************************************/ + +int stm32_usbpullup(struct usbdev_s *dev, bool enable) +{ + usbtrace(TRACE_DEVPULLUP, (uint16_t)enable); + stm32_gpiowrite(GPIO_USB_PULLUP, !enable); + return OK; +} + +/**************************************************************************** + * Name: stm32_usbsuspend + * + * Description: + * Board logic must provide the stm32_usbsuspend logic if the USBDEV driver + * is used. This function is called whenever the USB enters or leaves + * suspend mode. + * This is an opportunity for the board logic to shutdown clocks, power, + * etc. while the USB is suspended. + * + ****************************************************************************/ + +void stm32_usbsuspend(struct usbdev_s *dev, bool resume) +{ + uinfo("resume: %d\n", resume); +} diff --git a/boards/arm/stm32f1/hymini-stm32v/src/stm32_usbmsc.c b/boards/arm/stm32f1/hymini-stm32v/src/stm32_usbmsc.c new file mode 100644 index 0000000000000..ed78a1b866504 --- /dev/null +++ b/boards/arm/stm32f1/hymini-stm32v/src/stm32_usbmsc.c @@ -0,0 +1,127 @@ +/**************************************************************************** + * boards/arm/stm32f1/hymini-stm32v/src/stm32_usbmsc.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include +#include + +#include "stm32.h" + +/* There is nothing to do here if SDIO support is not selected. */ + +#ifdef CONFIG_STM32_SDIO + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +#ifndef CONFIG_SYSTEM_USBMSC_DEVMINOR1 +# define CONFIG_SYSTEM_USBMSC_DEVMINOR1 0 +#endif + +/* SLOT number(s) could depend on the board configuration */ + +#ifdef CONFIG_ARCH_BOARD_HYMINI_STM32V +# undef STM32_MMCSDSLOTNO +# define STM32_MMCSDSLOTNO 0 +#else +/* Add configuration for new STM32 boards here */ + +# error "Unrecognized STM32 board" +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_usbmsc_initialize + * + * Description: + * Perform architecture specific initialization of the USB MSC device. + * + ****************************************************************************/ + +int board_usbmsc_initialize(int port) +{ + /* If system/usbmsc is built as an NSH command, then SD slot should + * already have been initialized. + * In this case, there is nothing further to be done here. + */ + +#ifndef CONFIG_NSH_BUILTIN_APPS + struct sdio_dev_s *sdio; + int ret; + + /* First, get an instance of the SDIO interface */ + + syslog(LOG_INFO, "Initializing SDIO slot %d\n", STM32_MMCSDSLOTNO); + + sdio = sdio_initialize(STM32_MMCSDSLOTNO); + if (!sdio) + { + syslog(LOG_ERR, "ERROR: Failed to initialize SDIO slot %d\n", + STM32_MMCSDSLOTNO); + return -ENODEV; + } + + /* Now bind the SDIO interface to the MMC/SD driver */ + + syslog(LOG_INFO, "Bind SDIO to the MMC/SD driver, minor=%d\n", + CONFIG_SYSTEM_USBMSC_DEVMINOR1); + + ret = mmcsd_slotinitialize(CONFIG_SYSTEM_USBMSC_DEVMINOR1, sdio); + if (ret != OK) + { + syslog(LOG_ERR, "" + "ERROR: Failed to bind SDIO to the MMC/SD driver: %d\n", + ret); + return ret; + } + + syslog(LOG_INFO, "Successfully bound SDIO to the MMC/SD driver\n"); + + /* Then let's guess and say that there is a card in the slot. + * I need to check to see if the Hy-Mini STM32v board supports a GPIO to + * detect if there is a card in the slot. + */ + + sdio_mediachange(sdio, true); + +#endif /* CONFIG_NSH_BUILTIN_APPS */ + + return OK; +} + +#endif /* CONFIG_STM32_SDIO */ diff --git a/boards/arm/stm32f1/maple/CMakeLists.txt b/boards/arm/stm32f1/maple/CMakeLists.txt new file mode 100644 index 0000000000000..c22e019a545c6 --- /dev/null +++ b/boards/arm/stm32f1/maple/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32f1/maple/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/arm/stm32/maple/Kconfig b/boards/arm/stm32f1/maple/Kconfig similarity index 100% rename from boards/arm/stm32/maple/Kconfig rename to boards/arm/stm32f1/maple/Kconfig diff --git a/boards/arm/stm32f1/maple/configs/nsh/defconfig b/boards/arm/stm32f1/maple/configs/nsh/defconfig new file mode 100644 index 0000000000000..619ff1f1dbf30 --- /dev/null +++ b/boards/arm/stm32f1/maple/configs/nsh/defconfig @@ -0,0 +1,55 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_DISABLE_OS_API is not set +# CONFIG_NSH_DISABLEBG is not set +# CONFIG_NSH_DISABLESCRIPT is not set +# CONFIG_NSH_DISABLE_CMP is not set +# CONFIG_NSH_DISABLE_EXEC is not set +# CONFIG_NSH_DISABLE_EXIT is not set +# CONFIG_NSH_DISABLE_GET is not set +# CONFIG_NSH_DISABLE_HEXDUMP is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_LOSETUP is not set +# CONFIG_NSH_DISABLE_MKRD is not set +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_NSH_DISABLE_PUT is not set +# CONFIG_NSH_DISABLE_WGET is not set +# CONFIG_NSH_DISABLE_XD is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="maple" +CONFIG_ARCH_BOARD_MAPLE=y +CONFIG_ARCH_CHIP="stm32f1" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F103CB=y +CONFIG_ARCH_CHIP_STM32F1=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=5483 +CONFIG_BUILTIN=y +CONFIG_DEFAULT_SMALL=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_LIBC_RAND_ORDER=2 +CONFIG_LINE_MAX=80 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=1024 +CONFIG_PTHREAD_STACK_DEFAULT=1024 +CONFIG_RAM_SIZE=20480 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_START_DAY=23 +CONFIG_START_MONTH=10 +CONFIG_START_YEAR=2009 +CONFIG_STM32_DFU=y +CONFIG_STM32_USART1=y +CONFIG_STM32_USB=y +CONFIG_SYMTAB_ORDEREDBYNAME=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART1_SERIAL_CONSOLE=y +CONFIG_USBDEV_TRACE=y +CONFIG_USBDEV_TRACE_NRECORDS=32 diff --git a/boards/arm/stm32f1/maple/configs/nx/defconfig b/boards/arm/stm32f1/maple/configs/nx/defconfig new file mode 100644 index 0000000000000..5d98c00a330c9 --- /dev/null +++ b/boards/arm/stm32f1/maple/configs/nx/defconfig @@ -0,0 +1,78 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_DEV_CONSOLE is not set +# CONFIG_DISABLE_OS_API is not set +# CONFIG_NSH_DISABLEBG is not set +# CONFIG_NSH_DISABLESCRIPT is not set +# CONFIG_NSH_DISABLE_CMP is not set +# CONFIG_NSH_DISABLE_EXEC is not set +# CONFIG_NSH_DISABLE_EXIT is not set +# CONFIG_NSH_DISABLE_GET is not set +# CONFIG_NSH_DISABLE_HEXDUMP is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_LOSETUP is not set +# CONFIG_NSH_DISABLE_MKRD is not set +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_NSH_DISABLE_PUT is not set +# CONFIG_NSH_DISABLE_WGET is not set +# CONFIG_NSH_DISABLE_XD is not set +# CONFIG_NX_DISABLE_1BPP is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="maple" +CONFIG_ARCH_BOARD_MAPLE=y +CONFIG_ARCH_CHIP="stm32f1" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F103CB=y +CONFIG_ARCH_CHIP_STM32F1=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=5483 +CONFIG_BUILTIN=y +CONFIG_CDCACM=y +CONFIG_CDCACM_CONSOLE=y +CONFIG_CDCACM_RXBUFSIZE=256 +CONFIG_CDCACM_TXBUFSIZE=256 +CONFIG_DEFAULT_SMALL=y +CONFIG_EXAMPLES_NX=y +CONFIG_EXAMPLES_NXHELLO=y +CONFIG_EXAMPLES_NXHELLO_BPP=1 +CONFIG_EXAMPLES_NX_BPP=1 +CONFIG_I2C=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_LCD=y +CONFIG_LCD_SHARP_MEMLCD=y +CONFIG_LIBC_RAND_ORDER=2 +CONFIG_LINE_MAX=80 +CONFIG_MQ_MAXMSGSIZE=64 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=1024 +CONFIG_NSH_USBCONSOLE=y +CONFIG_NX=y +CONFIG_NXFONT_MONO5X8=y +CONFIG_NX_BLOCKING=y +CONFIG_PTHREAD_STACK_DEFAULT=1024 +CONFIG_RAM_SIZE=20480 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SPI_BITORDER=y +CONFIG_START_DAY=23 +CONFIG_START_MONTH=10 +CONFIG_START_YEAR=2009 +CONFIG_STM32_DFU=y +CONFIG_STM32_I2C1=y +CONFIG_STM32_I2C2=y +CONFIG_STM32_I2CTIMEOSEC=1 +CONFIG_STM32_SPI1=y +CONFIG_STM32_TIM2=y +CONFIG_STM32_USART1=y +CONFIG_STM32_USB=y +CONFIG_SYMTAB_ORDEREDBYNAME=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=15 +CONFIG_USBDEV_TRACE=y +CONFIG_USBDEV_TRACE_NRECORDS=32 diff --git a/boards/arm/stm32f1/maple/configs/usbnsh/defconfig b/boards/arm/stm32f1/maple/configs/usbnsh/defconfig new file mode 100644 index 0000000000000..128d504fd3f56 --- /dev/null +++ b/boards/arm/stm32f1/maple/configs/usbnsh/defconfig @@ -0,0 +1,61 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_DEV_CONSOLE is not set +# CONFIG_DISABLE_OS_API is not set +# CONFIG_NSH_DISABLEBG is not set +# CONFIG_NSH_DISABLESCRIPT is not set +# CONFIG_NSH_DISABLE_CMP is not set +# CONFIG_NSH_DISABLE_EXEC is not set +# CONFIG_NSH_DISABLE_EXIT is not set +# CONFIG_NSH_DISABLE_GET is not set +# CONFIG_NSH_DISABLE_HEXDUMP is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_LOSETUP is not set +# CONFIG_NSH_DISABLE_MKRD is not set +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_NSH_DISABLE_PUT is not set +# CONFIG_NSH_DISABLE_WGET is not set +# CONFIG_NSH_DISABLE_XD is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="maple" +CONFIG_ARCH_BOARD_MAPLE=y +CONFIG_ARCH_CHIP="stm32f1" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F103CB=y +CONFIG_ARCH_CHIP_STM32F1=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=5483 +CONFIG_BUILTIN=y +CONFIG_CDCACM=y +CONFIG_CDCACM_CONSOLE=y +CONFIG_CDCACM_RXBUFSIZE=256 +CONFIG_CDCACM_TXBUFSIZE=256 +CONFIG_DEFAULT_SMALL=y +CONFIG_I2C=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_LIBC_RAND_ORDER=2 +CONFIG_LINE_MAX=80 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=1024 +CONFIG_NSH_USBCONSOLE=y +CONFIG_PTHREAD_STACK_DEFAULT=1024 +CONFIG_RAM_SIZE=20480 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_START_DAY=23 +CONFIG_START_MONTH=10 +CONFIG_START_YEAR=2009 +CONFIG_STM32_DFU=y +CONFIG_STM32_USART1=y +CONFIG_STM32_USB=y +CONFIG_SYMTAB_ORDEREDBYNAME=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USBDEV_TRACE=y +CONFIG_USBDEV_TRACE_NRECORDS=32 diff --git a/boards/arm/stm32f1/maple/include/board.h b/boards/arm/stm32f1/maple/include/board.h new file mode 100644 index 0000000000000..af797c5453d2b --- /dev/null +++ b/boards/arm/stm32f1/maple/include/board.h @@ -0,0 +1,190 @@ +/**************************************************************************** + * boards/arm/stm32f1/maple/include/board.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_STM32_MAPLE_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32_MAPLE_INCLUDE_BOARD_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#ifndef __ASSEMBLY__ +# include +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Clocking *****************************************************************/ + +/* On-board crystal frequency is 8MHz (HSE) */ + +#define STM32_BOARD_XTAL 8000000ul + +/* PLL source is HSE/1, PLL multiplier is 9: + * PLL frequency is 8MHz (XTAL) x 9 = 72MHz + */ + +#define STM32_CFGR_PLLSRC RCC_CFGR_PLLSRC +#define STM32_CFGR_PLLXTPRE 0 +#define STM32_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx9 +#define STM32_PLL_FREQUENCY (9*STM32_BOARD_XTAL) + +/* Use the PLL and set the SYSCLK source to be the PLL */ + +#define STM32_SYSCLK_SW RCC_CFGR_SW_PLL +#define STM32_SYSCLK_SWS RCC_CFGR_SWS_PLL +#define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY + +/* AHB clock (HCLK) is SYSCLK (72MHz) */ + +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK +#define STM32_HCLK_FREQUENCY STM32_PLL_FREQUENCY + +/* APB2 clock (PCLK2) is HCLK (72MHz) */ + +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK +#define STM32_PCLK2_FREQUENCY STM32_HCLK_FREQUENCY + +/* APB2 timers 1 and 8 will receive PCLK2. */ + +#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) + +/* APB1 clock (PCLK1) is HCLK/2 (36MHz) */ + +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd2 +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/2) + +/* APB1 timers 2-7 will be twice PCLK1 */ + +#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) + +/* USB divider -- Divide PLL clock by 1.5 */ + +#define STM32_CFGR_USBPRE 0 + +/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx + * otherwise frequency is 2xAPBx. + * Note: TIM1,8 are on APB2, others on APB1 + */ + +#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM2_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM3_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM4_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM5_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM6_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM7_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY + +/* SDIO dividers. Note that slower clocking is required when DMA is disabled + * in order to avoid RX overrun/TX underrun errors due to delayed responses + * to service FIFOs in interrupt driven mode. These values have not been + * tuned!!! + * + * HCLK=72MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(178+2)=400 KHz + */ + +#define SDIO_INIT_CLKDIV (178 << SDIO_CLKCR_CLKDIV_SHIFT) + +/* DMA ON: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(2+2)=18 MHz + * DMA OFF: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(3+2)=14.4 MHz + */ + +#ifdef CONFIG_SDIO_DMA +# define SDIO_MMCXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT) +#else +# define SDIO_MMCXFR_CLKDIV (3 << SDIO_CLKCR_CLKDIV_SHIFT) +#endif + +/* DMA ON: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(1+2)=24 MHz + * DMA OFF: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(3+2)=14.4 MHz + */ + +#ifdef CONFIG_SDIO_DMA +# define SDIO_SDXFR_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT) +#else +# define SDIO_SDXFR_CLKDIV (3 << SDIO_CLKCR_CLKDIV_SHIFT) +#endif + +/* LED definitions **********************************************************/ + +/* The board has only one controllable LED */ + +#define LED_STARTED 0 /* No LEDs */ +#define LED_HEAPALLOCATE 1 /* LED1 on */ +#define LED_IRQSENABLED 2 /* LED2 on */ +#define LED_STACKCREATED 3 /* LED1 on */ +#define LED_INIRQ 4 /* LED1 off */ +#define LED_SIGNAL 5 /* LED2 on */ +#define LED_ASSERTION 6 /* LED1 + LED2 */ +#define LED_PANIC 7 /* LED1 / LED2 blinking */ + +/* Alternate function pin selections (auto-aliased for new pinmap) */ + +/* USART1 */ + +#define GPIO_USART1_TX GPIO_ADJUST_MODE(GPIO_USART1_TX_0, GPIO_MODE_50MHz) +#define GPIO_USART1_RX GPIO_USART1_RX_0 + +/* SPI1 */ + +#define GPIO_SPI1_NSS GPIO_ADJUST_MODE(GPIO_SPI1_NSS_0, GPIO_MODE_50MHz) +#define GPIO_SPI1_SCK GPIO_ADJUST_MODE(GPIO_SPI1_SCK_0, GPIO_MODE_50MHz) +#define GPIO_SPI1_MISO GPIO_ADJUST_MODE(GPIO_SPI1_MISO_0, GPIO_MODE_50MHz) +#define GPIO_SPI1_MOSI GPIO_ADJUST_MODE(GPIO_SPI1_MOSI_0, GPIO_MODE_50MHz) + +/* I2C1 */ + +#define GPIO_I2C1_SCL GPIO_ADJUST_MODE(GPIO_I2C1_SCL_0, GPIO_MODE_50MHz) +#define GPIO_I2C1_SDA GPIO_ADJUST_MODE(GPIO_I2C1_SDA_0, GPIO_MODE_50MHz) + +/* I2C2 */ + +#define GPIO_I2C2_SCL GPIO_ADJUST_MODE(GPIO_I2C2_SCL_0, GPIO_MODE_50MHz) +#define GPIO_I2C2_SDA GPIO_ADJUST_MODE(GPIO_I2C2_SDA_0, GPIO_MODE_50MHz) + +/* USB */ + +#define GPIO_USB_DM GPIO_USB_DM_0 +#define GPIO_USB_DP GPIO_USB_DP_0 + +/* TIM2 */ + +#define GPIO_TIM2_CH1IN GPIO_TIM2_CH1IN_0 +#define GPIO_TIM2_CH1OUT GPIO_ADJUST_MODE(GPIO_TIM2_CH1OUT_0, GPIO_MODE_50MHz) +#define GPIO_TIM2_CH2IN GPIO_TIM2_CH2IN_0 +#define GPIO_TIM2_CH2OUT GPIO_ADJUST_MODE(GPIO_TIM2_CH2OUT_0, GPIO_MODE_50MHz) +#define GPIO_TIM2_CH3IN GPIO_TIM2_CH3IN_0 +#define GPIO_TIM2_CH3OUT GPIO_ADJUST_MODE(GPIO_TIM2_CH3OUT_0, GPIO_MODE_50MHz) +#define GPIO_TIM2_CH4IN GPIO_TIM2_CH4IN_0 +#define GPIO_TIM2_CH4OUT GPIO_ADJUST_MODE(GPIO_TIM2_CH4OUT_0, GPIO_MODE_50MHz) + +#endif /* __BOARDS_ARM_STM32_MAPLE_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32f1/maple/scripts/Make.defs b/boards/arm/stm32f1/maple/scripts/Make.defs new file mode 100644 index 0000000000000..659d183e62795 --- /dev/null +++ b/boards/arm/stm32f1/maple/scripts/Make.defs @@ -0,0 +1,46 @@ +############################################################################ +# boards/arm/stm32f1/maple/scripts/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/.config +include $(TOPDIR)/tools/Config.mk +include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs + +ifeq ($(CONFIG_STM32_DFU),y) + LDSCRIPT = ld.script.dfu +else + LDSCRIPT = ld.script +endif + +ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) + +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32f1/maple/scripts/ld.script b/boards/arm/stm32f1/maple/scripts/ld.script new file mode 100644 index 0000000000000..0a473342b7501 --- /dev/null +++ b/boards/arm/stm32f1/maple/scripts/ld.script @@ -0,0 +1,122 @@ +/**************************************************************************** + * boards/arm/stm32f1/maple/scripts/ld.script + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* The STM32F103xB has 128Kb of FLASH beginning at address 0x0800:0000 and + * 20Kb of SRAM beginning at address 0x2000:0000. When booting from FLASH, + * FLASH memory is aliased to address 0x0000:0000 where the code expects to + * begin execution by jumping to the entry point in the 0x0800:0000 address + * range. + */ + +MEMORY +{ + flash (rx) : ORIGIN = 0x08000000, LENGTH = 128K + sram (rwx) : ORIGIN = 0x20000000, LENGTH = 20K +} + +OUTPUT_ARCH(arm) +EXTERN(_vectors) +ENTRY(_stext) +SECTIONS +{ + .text : { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > flash + + .init_section : ALIGN(4) { + _sinit = ABSOLUTE(.); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) + _einit = ABSOLUTE(.); + } > flash + + .ARM.extab : ALIGN(4) { + *(.ARM.extab*) + } > flash + + .ARM.exidx : ALIGN(4) { + __exidx_start = ABSOLUTE(.); + *(.ARM.exidx*) + __exidx_end = ABSOLUTE(.); + } > flash + + .tdata : { + _stdata = ABSOLUTE(.); + *(.tdata .tdata.* .gnu.linkonce.td.*); + _etdata = ABSOLUTE(.); + } > flash + + .tbss : { + _stbss = ABSOLUTE(.); + *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); + _etbss = ABSOLUTE(.); + } > flash + + _eronly = ABSOLUTE(.); + + /* The STM32F103VCT6 has 48Kb of SRAM beginning at the following address */ + + .data : ALIGN(4) { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > sram AT > flash + + .bss : ALIGN(4) { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + _ebss = ABSOLUTE(.); + } > sram + + /* Stabs debugging sections. */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/stm32f1/maple/scripts/ld.script.dfu b/boards/arm/stm32f1/maple/scripts/ld.script.dfu new file mode 100644 index 0000000000000..c1b90e6d7aff7 --- /dev/null +++ b/boards/arm/stm32f1/maple/scripts/ld.script.dfu @@ -0,0 +1,107 @@ +/**************************************************************************** + * boards/arm/stm32f1/maple/scripts/ld.script.dfu + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* The STM32F103xB has 128Kb of FLASH beginning at address 0x0800:0000 and + * 20Kb of SRAM beginning at address 0x2000:0000. Here we assume that the + * maple's DFU bootloader is being used. In that case, the correct + * load .text load address is 0x0800:5000 (leaving 108Kb). + */ + +MEMORY +{ + flash (rx) : ORIGIN = 0x08005000, LENGTH = 108K + sram (rwx) : ORIGIN = 0x20000000, LENGTH = 20K +} + +OUTPUT_ARCH(arm) +EXTERN(_vectors) +ENTRY(_stext) + +SECTIONS +{ + .text : { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > flash + + .init_section : ALIGN(4) { + _sinit = ABSOLUTE(.); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) + _einit = ABSOLUTE(.); + } > flash + + .ARM.extab : ALIGN(4) { + *(.ARM.extab*) + } > flash + + .ARM.exidx : ALIGN(4) { + __exidx_start = ABSOLUTE(.); + *(.ARM.exidx*) + __exidx_end = ABSOLUTE(.); + } > flash + + _eronly = ABSOLUTE(.); + + /* The STM32F103VCT6 has 48Kb of SRAM beginning at the following address */ + + .data : ALIGN(4) { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + _edata = ABSOLUTE(.); + } > sram AT > flash + + .bss : ALIGN(4) { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + _ebss = ABSOLUTE(.); + } > sram + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/stm32f1/maple/src/CMakeLists.txt b/boards/arm/stm32f1/maple/src/CMakeLists.txt new file mode 100644 index 0000000000000..97ee99bae6293 --- /dev/null +++ b/boards/arm/stm32f1/maple/src/CMakeLists.txt @@ -0,0 +1,43 @@ +# ############################################################################## +# boards/arm/stm32f1/maple/src/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(SRCS stm32_boot.c stm32_leds.c stm32_usbdev.c stm32_spi.c) + +if(CONFIG_NX_LCDDRIVER) + list(APPEND SRCS stm32_lcd.c) +endif() + +if(CONFIG_BOARDCTL) + +endif() + +if(CONFIG_INPUT) + +endif() + +if(CONFIG_USBMSC) + +endif() + +target_sources(board PRIVATE ${SRCS}) + +set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/ld.script") diff --git a/boards/arm/stm32f1/maple/src/Make.defs b/boards/arm/stm32f1/maple/src/Make.defs new file mode 100644 index 0000000000000..1a04a2a8db646 --- /dev/null +++ b/boards/arm/stm32f1/maple/src/Make.defs @@ -0,0 +1,42 @@ +############################################################################ +# boards/arm/stm32f1/maple/src/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +CSRCS = stm32_boot.c stm32_leds.c stm32_usbdev.c stm32_spi.c + +ifeq ($(CONFIG_NX_LCDDRIVER),y) +CSRCS += stm32_lcd.c +endif + +ifeq ($(CONFIG_BOARDCTL),y) +endif + +ifeq ($(CONFIG_INPUT),y) +endif + +ifeq ($(CONFIG_USBMSC),y) +endif + +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/maple/src/maple.h b/boards/arm/stm32f1/maple/src/maple.h similarity index 98% rename from boards/arm/stm32/maple/src/maple.h rename to boards/arm/stm32f1/maple/src/maple.h index 01bb5e5758f2f..26626776fb6d6 100644 --- a/boards/arm/stm32/maple/src/maple.h +++ b/boards/arm/stm32f1/maple/src/maple.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/maple/src/maple.h + * boards/arm/stm32f1/maple/src/maple.h * * SPDX-License-Identifier: Apache-2.0 * @@ -32,7 +32,7 @@ #include -#include +#include /**************************************************************************** * Pre-processor Definitions diff --git a/boards/arm/stm32f1/maple/src/stm32_boot.c b/boards/arm/stm32f1/maple/src/stm32_boot.c new file mode 100644 index 0000000000000..cbf666746d35b --- /dev/null +++ b/boards/arm/stm32f1/maple/src/stm32_boot.c @@ -0,0 +1,109 @@ +/**************************************************************************** + * boards/arm/stm32f1/maple/src/stm32_boot.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include + +#include +#include + +#include "arm_internal.h" +#include "maple.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_boardinitialize + * + * Description: + * All STM32 architectures must provide the following entry point. This + * entry point is called early in the initialization -- after all memory + * has been configured and mapped but before any devices have been + * initialized. + * + ****************************************************************************/ + +void stm32_boardinitialize(void) +{ + /* Configure on-board LEDs if LED support has been selected. */ + +#ifdef CONFIG_ARCH_LEDS + board_autoled_initialize(); +#endif + + /* Configure SPI chip selects if 1) SPI is not disabled, and 2) the weak + * function stm32_spidev_initialize() has been brought into the link. + */ + +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) + stm32_spidev_initialize(); +#endif + + /* Initialize USB is 1) USBDEV is selected, 2) the USB controller is not + * disabled, and 3) the weak function stm32_usbinitialize() has been + * brought into the build. + */ + +#if defined(CONFIG_USBDEV) && defined(CONFIG_STM32_USB) + stm32_usbinitialize(); +#endif +} + +/**************************************************************************** + * Name: board_late_initialize + * + * Description: + * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_late_initialize(). board_late_initialize() will + * be called after up_initialize() and board_early_initialize() and just + * before the initial application is started. This additional + * initialization phase may be used, for example, to initialize board- + * specific device drivers for which board_early_initialize() is not + * suitable. + * + * Waiting for events, use of I2C, SPI, etc are permissible in the context + * of board_late_initialize(). That is because board_late_initialize() + * will run on a temporary, internal kernel thread. + * + ****************************************************************************/ + +#ifdef CONFIG_BOARD_LATE_INITIALIZE +void board_late_initialize(void) +{ +} +#endif diff --git a/boards/arm/stm32f1/maple/src/stm32_lcd.c b/boards/arm/stm32f1/maple/src/stm32_lcd.c new file mode 100644 index 0000000000000..58f5831a33fe8 --- /dev/null +++ b/boards/arm/stm32f1/maple/src/stm32_lcd.c @@ -0,0 +1,198 @@ +/**************************************************************************** + * boards/arm/stm32f1/maple/src/stm32_lcd.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32.h" +#include "maple.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +#define EXTCOMIN_FREQ 24 +#define TIMER_FREQ 1200 /* 72000000/60000 */ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static struct lcd_dev_s *l_lcddev; +static struct spi_dev_s *spi; +static struct stm32_tim_dev_s *tim; +static xcpt_t g_isr; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +static int up_lcdextcominisr(int irq, void *context, void *arg) +{ + STM32_TIM_ACKINT(tim, ATIM_SR_UIF); + if (g_isr == NULL) + { + lcderr("ERROR: error, irq not attached, disabled\n"); + STM32_TIM_DISABLEINT(tim, ATIM_DIER_UIE); + return OK; + } + + return g_isr(irq, context, arg); +} + +static int up_lcdirqattach(xcpt_t isr, void * arg) +{ + lcdinfo("%s IRQ\n", isr == NULL ? "Detach" : "Attach"); + + if (isr != NULL) + { + STM32_TIM_SETISR(tim, up_lcdextcominisr, arg, ATIM_SR_UIF); + g_isr = isr; + } + else + { + STM32_TIM_SETISR(tim, NULL, NULL, ATIM_SR_UIF); + g_isr = NULL; + } + + return OK; +} + +static void up_lcddispcontrol(bool on) +{ + lcdinfo("set: %s\n", on ? "on" : "off"); + + if (on) + { + stm32_gpiowrite(GPIO_MEMLCD_DISP, 1); + STM32_TIM_ENABLEINT(tim, ATIM_DIER_UIE); + } + else + { + stm32_gpiowrite(GPIO_MEMLCD_DISP, 0); + STM32_TIM_DISABLEINT(tim, ATIM_DIER_UIE); + } +} + +#ifndef CONFIG_MEMLCD_EXTCOMIN_MODE_HW +static void up_lcdsetpolarity(bool pol) +{ + stm32_gpiowrite(GPIO_LED, pol); + stm32_gpiowrite(GPIO_MEMLCD_EXTCOMIN, pol); +} +#endif + +static void up_lcdsetvcomfreq(unsigned int freq) +{ + lcdinfo("freq: %d\n", freq); + DEBUGASSERT(freq >= 1 && freq <= 60); + STM32_TIM_SETPERIOD(tim, TIMER_FREQ / freq); +} + +static struct memlcd_priv_s memlcd_priv = +{ + .attachirq = up_lcdirqattach, + .dispcontrol = up_lcddispcontrol, +#ifndef CONFIG_MEMLCD_EXTCOMIN_MODE_HW + .setpolarity = up_lcdsetpolarity, +#endif + .setvcomfreq = up_lcdsetvcomfreq, +}; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_lcd_initialize + * + * Description: + * Initialize the LCD video hardware. The initial state of the LCD is + * fully initialized, display memory cleared, and the LCD ready to use, + * but with the power setting at 0 (full off). + * + ****************************************************************************/ + +int board_lcd_initialize(void) +{ + lcdinfo("Initializing lcd\n"); + + lcdinfo("init spi1\n"); + spi = stm32_spibus_initialize(1); + DEBUGASSERT(spi); + + lcdinfo("configure related io\n"); + stm32_configgpio(GPIO_MEMLCD_EXTCOMIN); + stm32_configgpio(GPIO_MEMLCD_DISP); + + lcdinfo("configure EXTCOMIN timer\n"); + if (tim == NULL) + { + tim = stm32_tim_init(2); + DEBUGASSERT(tim); + STM32_TIM_SETPERIOD(tim, TIMER_FREQ / EXTCOMIN_FREQ); + STM32_TIM_SETCLOCK(tim, TIMER_FREQ); + STM32_TIM_SETMODE(tim, STM32_TIM_MODE_UP); + } + + lcdinfo("init lcd\n"); + l_lcddev = memlcd_initialize(spi, &memlcd_priv, 0); + DEBUGASSERT(l_lcddev); + + return OK; +} + +/**************************************************************************** + * Name: board_lcd_getdev + * + * Description: + * Return a a reference to the LCD object for the specified LCD. This + * allows support for multiple LCD devices. + * + ****************************************************************************/ + +struct lcd_dev_s *board_lcd_getdev(int lcddev) +{ + DEBUGASSERT(lcddev == 0); + return l_lcddev; +} diff --git a/boards/arm/stm32f1/maple/src/stm32_leds.c b/boards/arm/stm32f1/maple/src/stm32_leds.c new file mode 100644 index 0000000000000..61d8957f2e498 --- /dev/null +++ b/boards/arm/stm32f1/maple/src/stm32_leds.c @@ -0,0 +1,120 @@ +/**************************************************************************** + * boards/arm/stm32f1/maple/src/stm32_leds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32.h" +#include "maple.h" + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +static inline void set_led(bool v) +{ + ledinfo("Turn LED %s\n", v? "on":"off"); + stm32_gpiowrite(GPIO_LED, v); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_autoled_initialize + ****************************************************************************/ + +#ifdef CONFIG_ARCH_LEDS +void board_autoled_initialize(void) +{ + /* Configure LED GPIO for output */ + + stm32_configgpio(GPIO_LED); +} + +/**************************************************************************** + * Name: board_autoled_on + ****************************************************************************/ + +void board_autoled_on(int led) +{ + ledinfo("board_autoled_on(%d)\n", led); + switch (led) + { + case LED_STARTED: + case LED_HEAPALLOCATE: + /* As the board provides only one soft controllable LED, we simply turn + * it on when the board boots + */ + + set_led(true); + break; + + case LED_PANIC: + + /* For panic state, the LED is blinking */ + + set_led(true); + break; + + default: + break; + } +} + +/**************************************************************************** + * Name: board_autoled_off + ****************************************************************************/ + +void board_autoled_off(int led) +{ + ledinfo("board_autoled_off(%d)\n", led); + + switch (led) + { + case LED_STARTED: + case LED_PANIC: + + /* For panic state, the LED is blinking */ + + set_led(false); + break; + + default: + break; + } +} + +#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32f1/maple/src/stm32_spi.c b/boards/arm/stm32f1/maple/src/stm32_spi.c new file mode 100644 index 0000000000000..1b644a2eb7b90 --- /dev/null +++ b/boards/arm/stm32f1/maple/src/stm32_spi.c @@ -0,0 +1,138 @@ +/**************************************************************************** + * boards/arm/stm32f1/maple/src/stm32_spi.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include + +#include "arm_internal.h" +#include "chip.h" +#include "stm32.h" +#include "maple.h" + +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_spidev_initialize + * + * Description: + * Called to configure SPI chip select GPIO pins for the maple board. + * + ****************************************************************************/ + +void weak_function stm32_spidev_initialize(void) +{ + /* NOTE: Clocking for SPI1 and/or SPI2 was already provided in stm32_rcc.c. + * Configurations of SPI pins is performed in stm32_spi.c. + * Here, we only initialize chip select pins unique to the board + * architecture. + */ + + stm32_configgpio(GPIO_MEMLCD_CS); +} + +/**************************************************************************** + * Name: stm32_spi1/2select and stm32_spi1/2status + * + * Description: + * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status + * must be provided by board-specific logic. They are implementations of + * the select and status methods of the SPI interface defined by struct + * spi_ops_s (see include/nuttx/spi/spi.h). All other methods (including + * stm32_spibus_initialize()) are provided by common STM32 logic. + * To use this common SPI logic on your board: + * + * 1. Provide logic in stm32_boardinitialize() to configure SPI chip + * select pins. + * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() functions + * in your board-specific logic. These functions will perform chip + * selection and status operations using GPIOs in the way your board is + * configured. + * 3. Add a calls to stm32_spibus_initialize() in your low level + * application initialization logic + * 4. The handle returned by stm32_spibus_initialize() may then be used to + * bind the SPI driver to higher level logic (e.g., calling + * mmcsd_spislotinitialize(), for example, will bind the SPI driver to + * the SPI MMC/SD driver). + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_SPI1 +void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, + bool selected) +{ + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); + +# if defined(CONFIG_LCD_SHARP_MEMLCD) + if (devid == SPIDEV_DISPLAY(0)) + { + stm32_gpiowrite(GPIO_MEMLCD_CS, selected); + } +# endif +} + +uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} + +int stm32_spi1cmddata(struct spi_dev_s *dev, + uint32_t devid, bool cmd) +{ + return -ENODEV; +} +#endif + +#ifdef CONFIG_STM32_SPI2 +void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid, + bool selected) +{ +} + +uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} + +int stm32_spi1cmddata(struct spi_dev_s *dev, + uint32_t devid, bool cmd) +{ + return -ENODEV; +} +#endif + +#endif /* CONFIG_STM32_SPI1 || CONFIG_STM32_SPI2 */ diff --git a/boards/arm/stm32f1/maple/src/stm32_usbdev.c b/boards/arm/stm32f1/maple/src/stm32_usbdev.c new file mode 100644 index 0000000000000..301485eb42cf1 --- /dev/null +++ b/boards/arm/stm32f1/maple/src/stm32_usbdev.c @@ -0,0 +1,103 @@ +/**************************************************************************** + * boards/arm/stm32f1/maple/src/stm32_usbdev.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include + +#include "arm_internal.h" +#include "stm32.h" +#include "maple.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_usbinitialize + * + * Description: + * Called to setup USB-related GPIO pins. + * + ****************************************************************************/ + +void stm32_usbinitialize(void) +{ + uinfo("called\n"); + + /* USB Soft Connect Pullup */ + + stm32_configgpio(GPIO_USB_PULLUP); +} + +/**************************************************************************** + * Name: stm32_usbpullup + * + * Description: + * If USB is supported and the board supports a pullup via GPIO (for USB + * software connect and disconnect), then the board software must provide + * stm32_pullup. See include/nuttx/usb/usbdev.h for additional description + * of this method. Alternatively, if no pull-up GPIO the following EXTERN + * can be redefined to be NULL. + * + ****************************************************************************/ + +int stm32_usbpullup(struct usbdev_s *dev, bool enable) +{ + usbtrace(TRACE_DEVPULLUP, (uint16_t)enable); + stm32_gpiowrite(GPIO_USB_PULLUP, !enable); + return OK; +} + +/**************************************************************************** + * Name: stm32_usbsuspend + * + * Description: + * Board logic must provide the stm32_usbsuspend logic if the USBDEV driver + * is used. This function is called whenever the USB enters or leaves + * suspend mode. This is an opportunity for the board logic to shutdown + * clocks, power, etc. while the USB is suspended. + * + ****************************************************************************/ + +void stm32_usbsuspend(struct usbdev_s *dev, bool resume) +{ + uinfo("resume: %d\n", resume); +} diff --git a/boards/arm/stm32/maple/tools/dfu.sh b/boards/arm/stm32f1/maple/tools/dfu.sh similarity index 100% rename from boards/arm/stm32/maple/tools/dfu.sh rename to boards/arm/stm32f1/maple/tools/dfu.sh diff --git a/boards/arm/stm32/maple/tools/env.sh b/boards/arm/stm32f1/maple/tools/env.sh similarity index 100% rename from boards/arm/stm32/maple/tools/env.sh rename to boards/arm/stm32f1/maple/tools/env.sh diff --git a/boards/arm/stm32f1/nucleo-f103rb/CMakeLists.txt b/boards/arm/stm32f1/nucleo-f103rb/CMakeLists.txt new file mode 100644 index 0000000000000..2b4f584cf31b9 --- /dev/null +++ b/boards/arm/stm32f1/nucleo-f103rb/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32f1/nucleo-f103rb/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/arm/stm32/nucleo-f103rb/Kconfig b/boards/arm/stm32f1/nucleo-f103rb/Kconfig similarity index 100% rename from boards/arm/stm32/nucleo-f103rb/Kconfig rename to boards/arm/stm32f1/nucleo-f103rb/Kconfig diff --git a/boards/arm/stm32f1/nucleo-f103rb/configs/adc/defconfig b/boards/arm/stm32f1/nucleo-f103rb/configs/adc/defconfig new file mode 100644 index 0000000000000..03b0dc7c45924 --- /dev/null +++ b/boards/arm/stm32f1/nucleo-f103rb/configs/adc/defconfig @@ -0,0 +1,54 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +CONFIG_ADC=y +CONFIG_ADC_FIFOSIZE=4 +CONFIG_ANALOG=y +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nucleo-f103rb" +CONFIG_ARCH_BOARD_NUCLEO_F103RB=y +CONFIG_ARCH_CHIP="stm32f1" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F103RB=y +CONFIG_ARCH_CHIP_STM32F1=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=5483 +CONFIG_BUILTIN=y +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_DEFAULT_SMALL=y +CONFIG_FILE_STREAM=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=80 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=1024 +CONFIG_RAM_SIZE=20480 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=192 +CONFIG_SCHED_WAITPID=y +CONFIG_SERIAL_TERMIOS=y +CONFIG_START_DAY=5 +CONFIG_START_MONTH=7 +CONFIG_START_YEAR=2011 +CONFIG_STM32_ADC1=y +CONFIG_STM32_ADC1_DMA=y +CONFIG_STM32_ADC2=y +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_DMA1=y +CONFIG_STM32_FORCEPOWER=y +CONFIG_STM32_JTAG_FULL_ENABLE=y +CONFIG_STM32_TIM1=y +CONFIG_STM32_TIM1_ADC=y +CONFIG_STM32_USART2=y +CONFIG_SYMTAB_ORDEREDBYNAME=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f1/nucleo-f103rb/configs/ihm07m1_b16/defconfig b/boards/arm/stm32f1/nucleo-f103rb/configs/ihm07m1_b16/defconfig new file mode 100644 index 0000000000000..603393f380612 --- /dev/null +++ b/boards/arm/stm32f1/nucleo-f103rb/configs/ihm07m1_b16/defconfig @@ -0,0 +1,86 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_DISABLE_MQUEUE is not set +# CONFIG_DISABLE_PTHREAD is not set +CONFIG_ADC=y +CONFIG_ADC_FIFOSIZE=3 +CONFIG_ANALOG=y +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nucleo-f103rb" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_NUCLEO_F103RB=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f1" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F103RB=y +CONFIG_ARCH_CHIP_STM32F1=y +CONFIG_ARCH_INTERRUPTSTACK=1024 +CONFIG_ARCH_IRQBUTTONS=y +CONFIG_BOARDCTL=y +CONFIG_BOARD_LOOPSPERMSEC=8499 +CONFIG_BOARD_STM32_IHM07M1=y +CONFIG_BOARD_STM32_IHM07M1_POT=y +CONFIG_BOARD_STM32_IHM07M1_VBUS=y +CONFIG_BUILTIN=y +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_DEFAULT_SMALL=y +CONFIG_DEFAULT_TASK_STACKSIZE=1024 +CONFIG_EXAMPLES_FOC=y +CONFIG_EXAMPLES_FOC_ADC_MAX=4095 +CONFIG_EXAMPLES_FOC_ADC_VREF=3300 +CONFIG_EXAMPLES_FOC_CONTROL_STACKSIZE=2048 +CONFIG_EXAMPLES_FOC_FIXED16_INST=1 +CONFIG_EXAMPLES_FOC_HAVE_BUTTON=y +CONFIG_EXAMPLES_FOC_NOTIFIER_FREQ=5000 +CONFIG_EXAMPLES_FOC_PWM_FREQ=20000 +CONFIG_EXAMPLES_FOC_RAMP_ACC=1000000 +CONFIG_EXAMPLES_FOC_RAMP_DEC=1000000 +CONFIG_EXAMPLES_FOC_RAMP_THR=10000 +CONFIG_EXAMPLES_FOC_SETPOINT_ADC=y +CONFIG_EXAMPLES_FOC_VBUS_ADC=y +CONFIG_EXAMPLES_FOC_VBUS_SCALE=19152 +CONFIG_INDUSTRY_FOC=y +CONFIG_INDUSTRY_FOC_FIXED16=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INPUT=y +CONFIG_INPUT_BUTTONS=y +CONFIG_INPUT_BUTTONS_LOWER=y +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBM=y +CONFIG_MOTOR=y +CONFIG_MOTOR_FOC=y +CONFIG_MOTOR_FOC_TRACE=y +CONFIG_MQ_MAXMSGSIZE=5 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_RAM_SIZE=16386 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=14 +CONFIG_START_MONTH=10 +CONFIG_START_YEAR=2014 +CONFIG_STM32_ADC1_ANIOC_TRIGGER=1 +CONFIG_STM32_ADC1_DMA=y +CONFIG_STM32_ADC1_INJECTED_CHAN=3 +CONFIG_STM32_DMA1=y +CONFIG_STM32_DMA2=y +CONFIG_STM32_FOC=y +CONFIG_STM32_FOC_FOC0=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_TIM1_CH1MODE=0 +CONFIG_STM32_TIM1_CH2MODE=0 +CONFIG_STM32_TIM1_CH3MODE=0 +CONFIG_STM32_TIM1_MODE=2 +CONFIG_STM32_TIM1_PARTIAL_REMAP=y +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART2_SERIAL_CONSOLE=y +CONFIG_USART2_TXDMA=y diff --git a/boards/arm/stm32f1/nucleo-f103rb/configs/nsh/defconfig b/boards/arm/stm32f1/nucleo-f103rb/configs/nsh/defconfig new file mode 100644 index 0000000000000..c3f979d2d130b --- /dev/null +++ b/boards/arm/stm32f1/nucleo-f103rb/configs/nsh/defconfig @@ -0,0 +1,43 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nucleo-f103rb" +CONFIG_ARCH_BOARD_NUCLEO_F103RB=y +CONFIG_ARCH_CHIP="stm32f1" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F103RB=y +CONFIG_ARCH_CHIP_STM32F1=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=5483 +CONFIG_BUILTIN=y +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_DEFAULT_SMALL=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=80 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=1024 +CONFIG_RAM_SIZE=20480 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=192 +CONFIG_SCHED_WAITPID=y +CONFIG_SERIAL_TERMIOS=y +CONFIG_START_DAY=5 +CONFIG_START_MONTH=7 +CONFIG_START_YEAR=2011 +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_JTAG_FULL_ENABLE=y +CONFIG_STM32_USART2=y +CONFIG_SYMTAB_ORDEREDBYNAME=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f1/nucleo-f103rb/configs/pwm/defconfig b/boards/arm/stm32f1/nucleo-f103rb/configs/pwm/defconfig new file mode 100644 index 0000000000000..f581b347f7672 --- /dev/null +++ b/boards/arm/stm32f1/nucleo-f103rb/configs/pwm/defconfig @@ -0,0 +1,50 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nucleo-f103rb" +CONFIG_ARCH_BOARD_NUCLEO_F103RB=y +CONFIG_ARCH_CHIP="stm32f1" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F103RB=y +CONFIG_ARCH_CHIP_STM32F1=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=5483 +CONFIG_BUILTIN=y +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_DEFAULT_SMALL=y +CONFIG_EXAMPLES_PWM=y +CONFIG_FILE_STREAM=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=80 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=1024 +CONFIG_PWM=y +CONFIG_RAM_SIZE=20480 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=192 +CONFIG_SCHED_WAITPID=y +CONFIG_SERIAL_TERMIOS=y +CONFIG_START_DAY=5 +CONFIG_START_MONTH=7 +CONFIG_START_YEAR=2011 +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_FORCEPOWER=y +CONFIG_STM32_JTAG_FULL_ENABLE=y +CONFIG_STM32_TIM1=y +CONFIG_STM32_TIM1_CH1OUT=y +CONFIG_STM32_TIM1_PWM=y +CONFIG_STM32_USART2=y +CONFIG_SYMTAB_ORDEREDBYNAME=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f1/nucleo-f103rb/configs/qenco/defconfig b/boards/arm/stm32f1/nucleo-f103rb/configs/qenco/defconfig new file mode 100644 index 0000000000000..3e080577801b8 --- /dev/null +++ b/boards/arm/stm32f1/nucleo-f103rb/configs/qenco/defconfig @@ -0,0 +1,56 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nucleo-f103rb" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_NUCLEO_F103RB=y +CONFIG_ARCH_CHIP="stm32f1" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F103RB=y +CONFIG_ARCH_CHIP_STM32F1=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=5483 +CONFIG_BUILTIN=y +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_DEFAULT_SMALL=y +CONFIG_EXAMPLES_QENCODER=y +CONFIG_EXAMPLES_QENCODER_HAVE_MAXPOS=y +CONFIG_EXAMPLES_QENCODER_MAXPOS=8192 +CONFIG_FILE_STREAM=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=80 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=1024 +CONFIG_RAM_SIZE=20480 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=192 +CONFIG_SCHED_WAITPID=y +CONFIG_SENSORS=y +CONFIG_SENSORS_QENCODER=y +CONFIG_SERIAL_TERMIOS=y +CONFIG_START_DAY=5 +CONFIG_START_MONTH=7 +CONFIG_START_YEAR=2011 +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_QENCODER_DISABLE_EXTEND16BTIMERS=y +CONFIG_STM32_QENCODER_SAMPLE_FDTS_2=y +CONFIG_STM32_TIM2=y +CONFIG_STM32_TIM2_PARTIAL_REMAP_1=y +CONFIG_STM32_TIM2_QE=y +CONFIG_STM32_TIM2_QEPSC=0 +CONFIG_STM32_USART2=y +CONFIG_SYMTAB_ORDEREDBYNAME=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f1/nucleo-f103rb/include/board.h b/boards/arm/stm32f1/nucleo-f103rb/include/board.h new file mode 100644 index 0000000000000..508c91177a32b --- /dev/null +++ b/boards/arm/stm32f1/nucleo-f103rb/include/board.h @@ -0,0 +1,251 @@ +/**************************************************************************** + * boards/arm/stm32f1/nucleo-f103rb/include/board.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_STM32_NUCLEO_F103RB_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32_NUCLEO_F103RB_INCLUDE_BOARD_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#ifndef __ASSEMBLY__ +# include +# include +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Clocking *****************************************************************/ + +/* HSI - Internal 8 MHz RC Oscillator + * LSI - 32 KHz RC + * HSE - 8 MHz from MCO output of ST-LINK + * LSE - 32.768 kHz + */ + +#define STM32_BOARD_XTAL 8000000ul /* X1 on board */ + +#define STM32_HSI_FREQUENCY 8000000ul +#define STM32_LSI_FREQUENCY 40000 /* Between 30kHz and 60kHz */ +#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL +#define STM32_LSE_FREQUENCY 32768 /* X2 on board */ + +/* PLL source is HSE/1, PLL multiplier is 9: + * PLL frequency is 8MHz (XTAL) x 9 = 72MHz + */ + +#define STM32_CFGR_PLLSRC RCC_CFGR_PLLSRC +#define STM32_CFGR_PLLXTPRE 0 +#define STM32_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx9 +#define STM32_PLL_FREQUENCY (9*STM32_BOARD_XTAL) + +/* Use the PLL and set the SYSCLK source to be the PLL */ + +#define STM32_SYSCLK_SW RCC_CFGR_SW_PLL +#define STM32_SYSCLK_SWS RCC_CFGR_SWS_PLL +#define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY + +/* AHB clock (HCLK) is SYSCLK (72MHz) */ + +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY + +/* APB2 clock (PCLK2) is HCLK (72MHz) */ + +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK +#define STM32_PCLK2_FREQUENCY STM32_HCLK_FREQUENCY +#define STM32_APB2_CLKIN (STM32_PCLK2_FREQUENCY) /* Timers 1 and 8, 15-17 */ + +/* APB1 clock (PCLK1) is HCLK/2 (36MHz) */ + +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd2 +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/2) + +/* APB2 TIM 1 will receive PCLK2 (72MHz) */ + +#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) + +/* APB1 TIM 2-4 will be twice PCLK1 (72MHz) */ + +#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) + +/* LED definitions **********************************************************/ + +/* The Nucleo F103RB board has three LEDs. Two of these are controlled by + * logic on the board and are not available for software control: + * + * LD1 COM: LD1 default status is red. LD1 turns to green to indicate that + * communications are in progress between the PC and the + * ST-LINK/V2-1. + * LD3 PWR: red LED indicates that the board is powered. + * + * And one can be controlled by software: + * + * User LD2: green LED is a user LED connected to the I/O PA5 of the + * STM32F103RBT6. + * + * If CONFIG_ARCH_LEDS is not defined, then the user can control the LED in + * any way. The following definition is used to access the LED. + */ + +/* LED index values for use with board_userled() */ + +#define BOARD_LED1 0 /* User LD2 */ +#define BOARD_NLEDS 1 + +/* LED bits for use with board_userled_all() */ + +#define BOARD_LED1_BIT (1 << BOARD_LED1) + +/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the LED on board + * the Nucleo F103RB. The following definitions describe how NuttX controls + * the LED: + * + * SYMBOL Meaning LED1 state + * ------------------ ----------------------- ---------- + * LED_STARTED NuttX has been started OFF + * LED_HEAPALLOCATE Heap has been allocated OFF + * LED_IRQSENABLED Interrupts enabled OFF + * LED_STACKCREATED Idle stack created ON + * LED_INIRQ In an interrupt No change + * LED_SIGNAL In a signal handler No change + * LED_ASSERTION An assertion failed No change + * LED_PANIC The system has crashed Blinking + * LED_IDLE STM32 is in sleep mode Not used + */ + +#define LED_STARTED 0 +#define LED_HEAPALLOCATE 0 +#define LED_IRQSENABLED 0 +#define LED_STACKCREATED 1 +#define LED_INIRQ 2 +#define LED_SIGNAL 2 +#define LED_ASSERTION 2 +#define LED_PANIC 1 + +/* Button definitions *******************************************************/ + +/* The Nucleo F103RB supports two buttons; only one button is controllable + * by software: + * + * B1 USER: user button connected to the I/O PC13 of the STM32F103RBT6. + * B2 RESET: push button connected to NRST is used to RESET the + * STM32F103RBT6. + */ + +#define BUTTON_USER 0 +#define NUM_BUTTONS 1 + +#define BUTTON_USER_BIT (1 << BUTTON_USER) + +/* Alternate function pin selections ****************************************/ + +/* DMA channels *************************************************************/ + +/* ADC */ + +#define ADC1_DMA_CHAN DMACHAN_ADC1 /* DMA1_CH1 */ + +#ifdef CONFIG_BOARD_STM32_IHM07M1 + +/* Configuration specific for the X-NUCLEO-IHM07M1 expansion board with + * the L6230 gate drivers. + */ + +/* TIM1 configuration *******************************************************/ + +/* Configured in stm32/hardware/stm32f103r_pinmap.h */ + +/* UVW ENABLE */ + +# define GPIO_FOC_EN_U (GPIO_OUTPUT|GPIO_CNF_OUTPP|GPIO_MODE_50MHz| \ + GPIO_OUTPUT_CLEAR|GPIO_PORTC|GPIO_PIN10) +# define GPIO_FOC_EN_V (GPIO_OUTPUT|GPIO_CNF_OUTPP|GPIO_MODE_50MHz| \ + GPIO_OUTPUT_CLEAR|GPIO_PORTC|GPIO_PIN11) +# define GPIO_FOC_EN_W (GPIO_OUTPUT|GPIO_CNF_OUTPP|GPIO_MODE_50MHz| \ + GPIO_OUTPUT_CLEAR|GPIO_PORTC|GPIO_PIN12) + +/* DIAG/ENABLE */ + +# define GPIO_FOC_DIAGEN (GPIO_OUTPUT|GPIO_CNF_OUTOD|GPIO_MODE_50MHz| \ + GPIO_OUTPUT_CLEAR|GPIO_PORTA|GPIO_PIN11) + +# define GPIO_FOC_LED2 (GPIO_OUTPUT|GPIO_CNF_OUTPP|GPIO_MODE_50MHz| \ + GPIO_OUTPUT_CLEAR|GPIO_PORTB|GPIO_PIN2) + +/* Debug pins */ + +# define GPIO_FOC_DEBUG0 (GPIO_OUTPUT|GPIO_CNF_OUTPP|GPIO_MODE_50MHz| \ + GPIO_OUTPUT_CLEAR|GPIO_PORTB|GPIO_PIN8) +# define GPIO_FOC_DEBUG1 (GPIO_OUTPUT|GPIO_CNF_OUTPP|GPIO_MODE_50MHz| \ + GPIO_OUTPUT_CLEAR|GPIO_PORTB|GPIO_PIN9) +# define GPIO_FOC_DEBUG2 (GPIO_OUTPUT|GPIO_CNF_OUTPP|GPIO_MODE_50MHz| \ + GPIO_OUTPUT_CLEAR|GPIO_PORTC|GPIO_PIN6) +# define GPIO_FOC_DEBUG3 (GPIO_OUTPUT|GPIO_CNF_OUTPP|GPIO_MODE_50MHz| \ + GPIO_OUTPUT_CLEAR|GPIO_PORTC|GPIO_PIN5) + +#endif /* CONFIG_BOARD_STM32_IHM07M1 */ + +/* Alternate function pin selections (auto-aliased for new pinmap) */ + +/* USART2 */ + +#define GPIO_USART2_TX GPIO_ADJUST_MODE(GPIO_USART2_TX_0, GPIO_MODE_50MHz) +#define GPIO_USART2_RX GPIO_USART2_RX_0 +#define GPIO_USART2_CTS GPIO_USART2_CTS_0 +#define GPIO_USART2_RTS GPIO_ADJUST_MODE(GPIO_USART2_RTS_0, GPIO_MODE_50MHz) +#define GPIO_USART2_CK GPIO_ADJUST_MODE(GPIO_USART2_CK_0, GPIO_MODE_50MHz) + +/* TIM1 */ + +#define GPIO_TIM1_CH1IN GPIO_TIM1_CH1IN_0 +#define GPIO_TIM1_CH1OUT GPIO_ADJUST_MODE(GPIO_TIM1_CH1OUT_0, GPIO_MODE_50MHz) +#define GPIO_TIM1_CH2IN GPIO_TIM1_CH2IN_0 +#define GPIO_TIM1_CH2OUT GPIO_ADJUST_MODE(GPIO_TIM1_CH2OUT_0, GPIO_MODE_50MHz) +#define GPIO_TIM1_CH3IN GPIO_TIM1_CH3IN_0 +#define GPIO_TIM1_CH3OUT GPIO_ADJUST_MODE(GPIO_TIM1_CH3OUT_0, GPIO_MODE_50MHz) +#define GPIO_TIM1_CH4IN GPIO_TIM1_CH4IN_0 +#define GPIO_TIM1_CH4OUT GPIO_ADJUST_MODE(GPIO_TIM1_CH4OUT_0, GPIO_MODE_50MHz) +#define GPIO_TIM1_BKIN GPIO_TIM1_BKIN_0 +#define GPIO_TIM1_ETR GPIO_TIM1_ETR_0 +#define GPIO_TIM1_CH1NOUT GPIO_ADJUST_MODE(GPIO_TIM1_CH1NOUT_0, GPIO_MODE_50MHz) +#define GPIO_TIM1_CH2NOUT GPIO_ADJUST_MODE(GPIO_TIM1_CH2NOUT_0, GPIO_MODE_50MHz) +#define GPIO_TIM1_CH3NOUT GPIO_ADJUST_MODE(GPIO_TIM1_CH3NOUT_0, GPIO_MODE_50MHz) + +/* TIM2 */ + +#define GPIO_TIM2_CH1IN GPIO_TIM2_CH1IN_0 +#define GPIO_TIM2_CH1OUT GPIO_ADJUST_MODE(GPIO_TIM2_CH1OUT_0, GPIO_MODE_50MHz) +#define GPIO_TIM2_CH2IN GPIO_TIM2_CH2IN_0 +#define GPIO_TIM2_CH2OUT GPIO_ADJUST_MODE(GPIO_TIM2_CH2OUT_0, GPIO_MODE_50MHz) +#define GPIO_TIM2_CH3IN GPIO_TIM2_CH3IN_0 +#define GPIO_TIM2_CH3OUT GPIO_ADJUST_MODE(GPIO_TIM2_CH3OUT_0, GPIO_MODE_50MHz) +#define GPIO_TIM2_CH4IN GPIO_TIM2_CH4IN_0 +#define GPIO_TIM2_CH4OUT GPIO_ADJUST_MODE(GPIO_TIM2_CH4OUT_0, GPIO_MODE_50MHz) + +#endif /* __BOARDS_ARM_STM32_NUCLEO_F103RB_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32f1/nucleo-f103rb/scripts/Make.defs b/boards/arm/stm32f1/nucleo-f103rb/scripts/Make.defs new file mode 100644 index 0000000000000..cec74ca3dda8d --- /dev/null +++ b/boards/arm/stm32f1/nucleo-f103rb/scripts/Make.defs @@ -0,0 +1,41 @@ +############################################################################ +# boards/arm/stm32f1/nucleo-f103rb/scripts/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/.config +include $(TOPDIR)/tools/Config.mk +include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs + +LDSCRIPT = ld.script +ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) + +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32f1/nucleo-f103rb/scripts/ld.script b/boards/arm/stm32f1/nucleo-f103rb/scripts/ld.script new file mode 100644 index 0000000000000..2d8d8c9c134d7 --- /dev/null +++ b/boards/arm/stm32f1/nucleo-f103rb/scripts/ld.script @@ -0,0 +1,127 @@ +/**************************************************************************** + * boards/arm/stm32f1/nucleo-f103rb/scripts/ld.script + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* The STM32F103RBT6 has 128Kb of FLASH beginning at address 0x0800:0000 and + * 20Kb of SRAM. + * + * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 + * where the code expects to begin execution by jumping to the entry point in + * the 0x0800:0000 address range. + */ + +MEMORY +{ + flash (rx) : ORIGIN = 0x08000000, LENGTH = 128K + sram (rwx) : ORIGIN = 0x20000000, LENGTH = 20K +} + +OUTPUT_ARCH(arm) +EXTERN(_vectors) +ENTRY(_stext) +SECTIONS +{ + .text : { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > flash + + .init_section : ALIGN(4) { + _sinit = ABSOLUTE(.); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) + _einit = ABSOLUTE(.); + } > flash + + .ARM.extab : ALIGN(4) { + *(.ARM.extab*) + } > flash + + .ARM.exidx : ALIGN(4) { + __exidx_start = ABSOLUTE(.); + *(.ARM.exidx*) + __exidx_end = ABSOLUTE(.); + } > flash + + .tdata : { + _stdata = ABSOLUTE(.); + *(.tdata .tdata.* .gnu.linkonce.td.*); + _etdata = ABSOLUTE(.); + } > flash + + .tbss : { + _stbss = ABSOLUTE(.); + *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); + _etbss = ABSOLUTE(.); + } > flash + + _eronly = ABSOLUTE(.); + + /* The RAM vector table (if present) should lie at the beginning of SRAM */ + + .ram_vectors : { + *(.ram_vectors) + } > sram + + .data : ALIGN(4) { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > sram AT > flash + + .bss : ALIGN(4) { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + _ebss = ABSOLUTE(.); + } > sram + + /* Stabs debugging sections. */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/stm32f1/nucleo-f103rb/src/CMakeLists.txt b/boards/arm/stm32f1/nucleo-f103rb/src/CMakeLists.txt new file mode 100644 index 0000000000000..f8e649461b796 --- /dev/null +++ b/boards/arm/stm32f1/nucleo-f103rb/src/CMakeLists.txt @@ -0,0 +1,51 @@ +# ############################################################################## +# boards/arm/stm32f1/nucleo-f103rb/src/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(SRCS stm32_boot.c stm32_bringup.c) + +if(CONFIG_ARCH_LEDS) + list(APPEND SRCS stm32_autoleds.c) +else() + list(APPEND SRCS stm32_userleds.c) +endif() + +if(CONFIG_ARCH_BUTTONS) + list(APPEND SRCS stm32_buttons.c) +endif() + +if(NOT CONFIG_STM32_FOC) + if(CONFIG_ADC) + list(APPEND SRCS stm32_adc.c) + endif() + + if(CONFIG_PWM) + list(APPEND SRCS stm32_pwm.c) + endif() +endif() + +if(CONFIG_BOARD_STM32_IHM07M1) + list(APPEND SRCS stm32_foc_ihm07m1.c) +endif() + +target_sources(board PRIVATE ${SRCS}) + +set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/ld.script") diff --git a/boards/arm/stm32f1/nucleo-f103rb/src/Make.defs b/boards/arm/stm32f1/nucleo-f103rb/src/Make.defs new file mode 100644 index 0000000000000..f3c2bb7582290 --- /dev/null +++ b/boards/arm/stm32f1/nucleo-f103rb/src/Make.defs @@ -0,0 +1,53 @@ +############################################################################ +# boards/arm/stm32f1/nucleo-f103rb/src/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +CSRCS = stm32_boot.c stm32_bringup.c + +ifeq ($(CONFIG_ARCH_LEDS),y) +CSRCS += stm32_autoleds.c +else +CSRCS += stm32_userleds.c +endif + +ifeq ($(CONFIG_ARCH_BUTTONS),y) +CSRCS += stm32_buttons.c +endif + +ifneq ($(CONFIG_STM32_FOC),y) +ifeq ($(CONFIG_ADC),y) +CSRCS += stm32_adc.c +endif + +ifeq ($(CONFIG_PWM),y) +CSRCS += stm32_pwm.c +endif +endif + +ifeq ($(CONFIG_BOARD_STM32_IHM07M1),y) +CSRCS += stm32_foc_ihm07m1.c +endif + +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/nucleo-f103rb/src/nucleo-f103rb.h b/boards/arm/stm32f1/nucleo-f103rb/src/nucleo-f103rb.h similarity index 98% rename from boards/arm/stm32/nucleo-f103rb/src/nucleo-f103rb.h rename to boards/arm/stm32f1/nucleo-f103rb/src/nucleo-f103rb.h index d4cb2b2383add..09dd3b1dd5451 100644 --- a/boards/arm/stm32/nucleo-f103rb/src/nucleo-f103rb.h +++ b/boards/arm/stm32f1/nucleo-f103rb/src/nucleo-f103rb.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f103rb/src/nucleo-f103rb.h + * boards/arm/stm32f1/nucleo-f103rb/src/nucleo-f103rb.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f1/nucleo-f103rb/src/stm32_adc.c b/boards/arm/stm32f1/nucleo-f103rb/src/stm32_adc.c new file mode 100644 index 0000000000000..5b5ff6d6bc82c --- /dev/null +++ b/boards/arm/stm32f1/nucleo-f103rb/src/stm32_adc.c @@ -0,0 +1,242 @@ +/**************************************************************************** + * boards/arm/stm32f1/nucleo-f103rb/src/stm32_adc.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "stm32.h" + +#if defined(CONFIG_ADC) && (defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2)) + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* 1 or 2 ADC devices (DEV1, DEV2) */ + +#if defined(CONFIG_STM32_ADC1) +# define DEV1_PORT 1 +#endif + +#if defined(CONFIG_STM32_ADC2) +# if defined(DEV1_PORT) +# define DEV2_PORT 2 +# else +# define DEV1_PORT 2 +# endif +#endif + +/* The number of ADC channels in the conversion list */ + +/* TODO DMA */ + +#define ADC1_NCHANNELS 3 +#define ADC2_NCHANNELS 3 + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* DEV 1 */ + +#if DEV1_PORT == 1 + +#define DEV1_NCHANNELS ADC1_NCHANNELS + +/* Identifying number of each ADC channel (even if NCHANNELS is less) */ + +static const uint8_t g_chanlist1[3] = +{ + 0, + 1, + 4 +}; + +/* Configurations of pins used by each ADC channel */ + +static const uint32_t g_pinlist1[3] = +{ + GPIO_ADC123_IN0_0, /* PA0/A0 */ + GPIO_ADC123_IN1_0, /* PA1/A1 */ + GPIO_ADC12_IN4_0, /* PA4/A2 */ +}; + +#elif DEV1_PORT == 2 + +#define DEV1_NCHANNELS ADC2_NCHANNELS + +/* Identifying number of each ADC channel */ + +static const uint8_t g_chanlist1[3] = +{ + 8, + 11, + 10 +}; + +/* Configurations of pins used by each ADC channel */ + +static const uint32_t g_pinlist1[3] = +{ + GPIO_ADC12_IN8_0, /* PB0/A3 */ + GPIO_ADC123_IN11_0, /* PC1/A4 */ + GPIO_ADC123_IN10_0, /* PC0/A5 */ +}; + +#endif /* DEV1_PORT == 1 */ + +#ifdef DEV2_PORT + +/* DEV 2 */ + +#if DEV2_PORT == 2 + +#define DEV2_NCHANNELS ADC2_NCHANNELS + +/* Identifying number of each ADC channel */ + +static const uint8_t g_chanlist2[3] = +{ + 8, + 11, + 10 +}; + +/* Configurations of pins used by each ADC channel */ + +static const uint32_t g_pinlist2[3] = +{ + GPIO_ADC12_IN8_0, /* PB0/A3 */ + GPIO_ADC123_IN11_0, /* PC1/A4 */ + GPIO_ADC123_IN10_0, /* PC0/A5 */ +}; + +#endif /* DEV2_PORT == 2 */ +#endif /* DEV2_PORT */ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_adc_setup + * + * Description: + * Initialize ADC and register the ADC driver. + * + ****************************************************************************/ + +int stm32_adc_setup(void) +{ + static bool initialized = false; + struct adc_dev_s *adc; + int ret; + int i; + + /* Check if we have already initialized */ + + if (!initialized) + { + /* DEV1 */ + + /* Configure the pins as analog inputs for the selected channels */ + + for (i = 0; i < DEV1_NCHANNELS; i++) + { + stm32_configgpio(g_pinlist1[i]); + } + + /* Call stm32_adcinitialize() to get an instance of the ADC interface */ + + adc = stm32_adcinitialize(DEV1_PORT, g_chanlist1, DEV1_NCHANNELS); + if (adc == NULL) + { + aerr("ERROR: Failed to get ADC interface 1\n"); + return -ENODEV; + } + + /* Register the ADC driver at "/dev/adc0" */ + + ret = adc_register("/dev/adc0", adc); + if (ret < 0) + { + aerr("ERROR: adc_register /dev/adc0 failed: %d\n", ret); + return ret; + } + +#ifdef DEV2_PORT + + /* DEV2 */ + + /* Configure the pins as analog inputs for the selected channels */ + + for (i = 0; i < DEV2_NCHANNELS; i++) + { + stm32_configgpio(g_pinlist2[i]); + } + + /* Call stm32_adcinitialize() to get an instance of the ADC interface */ + + adc = stm32_adcinitialize(DEV2_PORT, g_chanlist2, DEV2_NCHANNELS); + if (adc == NULL) + { + aerr("ERROR: Failed to get ADC interface 2\n"); + return -ENODEV; + } + + /* Register the ADC driver at "/dev/adc1" */ + + ret = adc_register("/dev/adc1", adc); + if (ret < 0) + { + aerr("ERROR: adc_register /dev/adc1 failed: %d\n", ret); + return ret; + } +#endif + + initialized = true; + } + + return OK; +} + +#endif /* CONFIG_ADC && (CONFIG_STM32_ADC1 || CONFIG_STM32_ADC2) */ diff --git a/boards/arm/stm32f1/nucleo-f103rb/src/stm32_autoleds.c b/boards/arm/stm32f1/nucleo-f103rb/src/stm32_autoleds.c new file mode 100644 index 0000000000000..9185329bab1f7 --- /dev/null +++ b/boards/arm/stm32f1/nucleo-f103rb/src/stm32_autoleds.c @@ -0,0 +1,80 @@ +/**************************************************************************** + * boards/arm/stm32f1/nucleo-f103rb/src/stm32_autoleds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "stm32.h" +#include "nucleo-f103rb.h" + +#ifdef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_autoled_initialize + ****************************************************************************/ + +void board_autoled_initialize(void) +{ + /* Configure LED1 GPIO for output */ + + stm32_configgpio(GPIO_LED1); +} + +/**************************************************************************** + * Name: board_autoled_on + ****************************************************************************/ + +void board_autoled_on(int led) +{ + if (led == BOARD_LED1) + { + stm32_gpiowrite(GPIO_LED1, true); + } +} + +/**************************************************************************** + * Name: board_autoled_off + ****************************************************************************/ + +void board_autoled_off(int led) +{ + if (led == BOARD_LED1) + { + stm32_gpiowrite(GPIO_LED1, false); + } +} + +#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32f1/nucleo-f103rb/src/stm32_boot.c b/boards/arm/stm32f1/nucleo-f103rb/src/stm32_boot.c new file mode 100644 index 0000000000000..0084bba60a882 --- /dev/null +++ b/boards/arm/stm32f1/nucleo-f103rb/src/stm32_boot.c @@ -0,0 +1,95 @@ +/**************************************************************************** + * boards/arm/stm32f1/nucleo-f103rb/src/stm32_boot.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include "nucleo-f103rb.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_boardinitialize + * + * Description: + * All STM32 architectures must provide the following entry point. This + * entry point is called early in the initialization -- after all memory + * has been configured and mapped but before any devices have been + * initialized. + * + ****************************************************************************/ + +void stm32_boardinitialize(void) +{ + /* Configure on-board LEDs if LED support has been selected. */ + +#ifdef CONFIG_ARCH_LEDS + board_autoled_initialize(); +#endif +} + +/**************************************************************************** + * Name: board_late_initialize + * + * Description: + * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_late_initialize(). board_late_initialize() will + * be called immediately after up_initialize() is called and just before + * the initial application is started. This additional initialization + * phase may be used, for example, to initialize board-specific device + * drivers. + * + ****************************************************************************/ + +#ifdef CONFIG_BOARD_LATE_INITIALIZE +void board_late_initialize(void) +{ + /* Perform board-specific initialization */ + + stm32_bringup(); +} +#endif diff --git a/boards/arm/stm32f1/nucleo-f103rb/src/stm32_bringup.c b/boards/arm/stm32f1/nucleo-f103rb/src/stm32_bringup.c new file mode 100644 index 0000000000000..d4583edc58e9a --- /dev/null +++ b/boards/arm/stm32f1/nucleo-f103rb/src/stm32_bringup.c @@ -0,0 +1,143 @@ +/**************************************************************************** + * boards/arm/stm32f1/nucleo-f103rb/src/stm32_bringup.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include + +#ifdef CONFIG_USERLED +# include +#endif + +#ifdef CONFIG_INPUT_BUTTONS +# include +#endif + +#ifdef CONFIG_SENSORS_QENCODER +# include "board_qencoder.h" +#endif + +#include "nucleo-f103rb.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#undef HAVE_LEDS + +#if !defined(CONFIG_ARCH_LEDS) && defined(CONFIG_USERLED_LOWER) +# define HAVE_LEDS 1 +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_bringup + * + * Description: + * Perform architecture-specific initialization + * + * CONFIG_BOARD_LATE_INITIALIZE=y : + * Called from board_late_initialize(). + * + ****************************************************************************/ + +int stm32_bringup(void) +{ + int ret; + +#ifdef CONFIG_INPUT_BUTTONS + /* Register the BUTTON driver */ + + ret = btn_lower_initialize("/dev/buttons"); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: btn_lower_initialize() failed: %d\n", ret); + } +#endif + +#ifdef HAVE_LEDS + /* Register the LED driver */ + + ret = userled_lower_initialize(LED_DRIVER_PATH); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: userled_lower_initialize() failed: %d\n", ret); + return ret; + } +#endif + +#ifdef CONFIG_PWM + /* Initialize PWM and register the PWM device. */ + + ret = stm32_pwm_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_pwm_setup() failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_STM32_FOC + /* Initialize and register the FOC device */ + + ret = stm32_foc_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_foc_setup failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_ADC + /* Initialize ADC and register the ADC driver. */ + + ret = stm32_adc_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_adc_setup failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_SENSORS_QENCODER + /* Initialize and register the qencoder driver */ + + ret = board_qencoder_initialize(0, CONFIG_NUCLEO_F103RB_QETIMER); + if (ret != OK) + { + syslog(LOG_ERR, + "ERROR: Failed to register the qencoder: %d\n", + ret); + return ret; + } +#endif + + UNUSED(ret); + return OK; +} diff --git a/boards/arm/stm32f1/nucleo-f103rb/src/stm32_buttons.c b/boards/arm/stm32f1/nucleo-f103rb/src/stm32_buttons.c new file mode 100644 index 0000000000000..ce1e2da780ebf --- /dev/null +++ b/boards/arm/stm32f1/nucleo-f103rb/src/stm32_buttons.c @@ -0,0 +1,113 @@ +/**************************************************************************** + * boards/arm/stm32f1/nucleo-f103rb/src/stm32_buttons.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "stm32.h" +#include "nucleo-f103rb.h" + +#ifdef CONFIG_ARCH_BUTTONS + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_button_initialize + * + * Description: + * board_button_initialize() must be called to initialize button + * resources. After that, board_buttons() may be called to collect the + * current state of all buttons or board_button_irq() may be called to + * register button interrupt handlers. + * + ****************************************************************************/ + +uint32_t board_button_initialize(void) +{ + /* Configure the single button as an input. NOTE that EXTI interrupts are + * also configured for the pin. + */ + + stm32_configgpio(GPIO_BTN_USER); + return NUM_BUTTONS; +} + +/**************************************************************************** + * Name: board_buttons + * + * Description: + * After board_button_initialize() has been called, board_buttons() may be + * called to collect the state of all buttons. board_buttons() returns an + * 32-bit unsigned integer with each bit associated with a button. See the + * BUTTON_*_BIT definitions in board.h for the meaning of each bit. + * + ****************************************************************************/ + +uint32_t board_buttons(void) +{ + /* Check the state of the USER button. A LOW value means that the key is + * pressed. + */ + + return stm32_gpioread(GPIO_BTN_USER) ? 0 : BUTTON_USER_BIT; +} + +/**************************************************************************** + * Name: board_button_irq + * + * Description: + * board_button_irq() may be called to register an interrupt handler that + * will be called when a button is depressed or released. The ID value is + * a button enumeration value that uniquely identifies a button resource. + * See the BUTTON_* definitions in board.h for the meaning of the + * enumeration value. + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_IRQBUTTONS +int board_button_irq(int id, xcpt_t irqhandler, void *arg) +{ + int ret = -EINVAL; + + if (id == BUTTON_USER) + { + ret = stm32_gpiosetevent(GPIO_BTN_USER, true, true, true, irqhandler, + arg); + } + + return ret; +} +#endif + +#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/stm32f1/nucleo-f103rb/src/stm32_foc_ihm07m1.c b/boards/arm/stm32f1/nucleo-f103rb/src/stm32_foc_ihm07m1.c new file mode 100644 index 0000000000000..632f8770ef304 --- /dev/null +++ b/boards/arm/stm32f1/nucleo-f103rb/src/stm32_foc_ihm07m1.c @@ -0,0 +1,185 @@ +/**************************************************************************** + * boards/arm/stm32f1/nucleo-f103rb/src/stm32_foc_ihm07m1.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "stm32_ihm07m1.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define CURRENT_SAMPLE_TIME ADC_SMPR_28p5 +#define VBUS_SAMPLE_TIME ADC_SMPR_239p5 +#define POT_SAMPLE_TIME ADC_SMPR_239p5 + +/* ADC1 channels used in this example */ + +#define ADC1_INJECTED (CONFIG_MOTOR_FOC_SHUNTS) + +#ifdef CONFIG_BOARD_STM32_IHM07M1_VBUS +# define IHM07M1_VBUS 1 +#else +# define IHM07M1_VBUS 0 +#endif + +#ifdef CONFIG_BOARD_STM32_IHM07M1_POT +# define IHM07M1_POT 1 +#else +# define IHM07M1_POT 0 +#endif + +#define ADC1_REGULAR (IHM07M1_VBUS + IHM07M1_POT) +#define ADC1_NCHANNELS (ADC1_INJECTED + ADC1_REGULAR) + +/* Check ADC1 configuration */ + +#if ADC1_INJECTED != CONFIG_STM32_ADC1_INJECTED_CHAN +# error +#endif + +/* TIM1 configuration */ + +#ifndef CONFIG_STM32_TIM1_PARTIAL_REMAP +# error +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* FOC ADC configuration: + * - Current Phase V -> ADC1 INJ1 -> ADC1_IN0 (PA0) + * - Current Phase U -> ADC1 INJ2 -> ADC1_IN11 (PC1) + * - Current Phase W -> ADC1 INJ3 -> ADC1_I10 (PC0) + * optional: + * - VBUS -> ADC1 REG -> ADC1_IN1 (PA1) + * - POT -> ADC1 REG -> ADC1_IN9 (PB1) + * + * TIM1 PWM configuration: + * - Phase U high -> TIM1_CH1 (PA8) + * - Phase V high -> TIM1_CH2 (PA9) + * - Phase W high -> TIM1_CH3 (PA10) + * + */ + +static uint8_t g_adc1_chan[] = +{ +#ifdef CONFIG_BOARD_STM32_IHM07M1_VBUS + 1, /* ADC1 REG - VBUS */ +#endif +#ifdef CONFIG_BOARD_STM32_IHM07M1_POT + 9, /* ADC1 REG - POT */ +#endif + 0, /* ADC1 INJ1 - PHASE 1 */ +#if CONFIG_MOTOR_FOC_SHUNTS == 3 + 11, /* ADC1 INJ2 - PHASE 2 */ + 10, /* ADC1 INJ3 - PHASE 3 */ +#endif +}; + +static uint32_t g_adc1_pins[] = +{ +#ifdef CONFIG_BOARD_STM32_IHM07M1_VBUS + GPIO_ADC123_IN1_0, +#endif +#ifdef CONFIG_BOARD_STM32_IHM07M1_POT + GPIO_ADC12_IN9_0, +#endif + GPIO_ADC123_IN0_0, +#if CONFIG_MOTOR_FOC_SHUNTS > 1 + GPIO_ADC123_IN11_0, +#endif +#if CONFIG_MOTOR_FOC_SHUNTS > 2 + GPIO_ADC123_IN10_0, +#endif +}; + +/* ADC1 sample time configuration */ + +static adc_channel_t g_adc1_stime[] = +{ +#ifdef CONFIG_BOARD_STM32_IHM07M1_VBUS + { + .channel = 2, + .sample_time = VBUS_SAMPLE_TIME + }, +#endif +#ifdef CONFIG_BOARD_STM32_IHM07M1_POT + { + .channel = 12, + .sample_time = POT_SAMPLE_TIME + }, +#endif + { + .channel = 1, + .sample_time = CURRENT_SAMPLE_TIME + }, +#if CONFIG_MOTOR_FOC_SHUNTS > 1 + { + .channel = 7, + .sample_time = CURRENT_SAMPLE_TIME + }, +#endif +#if CONFIG_MOTOR_FOC_SHUNTS > 2 + { + .channel = 6, + .sample_time = CURRENT_SAMPLE_TIME + }, +#endif +}; + +/* Board specific ADC configuration for FOC */ + +static struct stm32_foc_adc_s g_adc_cfg = +{ + .chan = g_adc1_chan, + .pins = g_adc1_pins, + .stime = g_adc1_stime, + .nchan = ADC1_NCHANNELS, + .regch = ADC1_REGULAR, + .intf = 1 +}; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_foc_setup + * + * Description: + * Initialize FOC driver. + * + * Returned Value: + * 0 on success, a negated errno value on failure + * + ****************************************************************************/ + +int stm32_foc_setup(void) +{ + return board_ihm07m1_initialize(&g_adc_cfg); +} diff --git a/boards/arm/stm32f1/nucleo-f103rb/src/stm32_pwm.c b/boards/arm/stm32f1/nucleo-f103rb/src/stm32_pwm.c new file mode 100644 index 0000000000000..e4942fddead1e --- /dev/null +++ b/boards/arm/stm32f1/nucleo-f103rb/src/stm32_pwm.c @@ -0,0 +1,110 @@ +/**************************************************************************** + * boards/arm/stm32f1/nucleo-f103rb/src/stm32_pwm.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32_pwm.h" +#include "nucleo-f103rb.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +#define HAVE_PWM 1 + +#ifndef CONFIG_PWM +# undef HAVE_PWM +#endif + +#ifndef CONFIG_STM32_TIM1 +# undef HAVE_PWM +#endif + +#ifndef CONFIG_STM32_TIM1_PWM +# undef HAVE_PWM +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_pwm_setup + * + * Description: + * Initialize PWM and register the PWM device. + * + ****************************************************************************/ + +int stm32_pwm_setup(void) +{ +#ifdef HAVE_PWM + static bool initialized = false; + struct pwm_lowerhalf_s *pwm; + int ret; + + /* Have we already initialized? */ + + if (!initialized) + { + /* Call stm32_pwminitialize() to get an instance of the PWM interface */ + + pwm = stm32_pwminitialize(NUCLEOF103RB_PWMTIMER); + if (!pwm) + { + tmrerr("ERROR: Failed to get the STM32 PWM lower half\n"); + return -ENODEV; + } + + /* Register the PWM driver at "/dev/pwm0" */ + + ret = pwm_register("/dev/pwm0", pwm); + if (ret < 0) + { + tmrerr("ERROR: pwm_register failed: %d\n", ret); + return ret; + } + + /* Now we are initialized */ + + initialized = true; + } + + return OK; +#else + return -ENODEV; +#endif +} diff --git a/boards/arm/stm32f1/nucleo-f103rb/src/stm32_userleds.c b/boards/arm/stm32f1/nucleo-f103rb/src/stm32_userleds.c new file mode 100644 index 0000000000000..3e9985bd99864 --- /dev/null +++ b/boards/arm/stm32f1/nucleo-f103rb/src/stm32_userleds.c @@ -0,0 +1,77 @@ +/**************************************************************************** + * boards/arm/stm32f1/nucleo-f103rb/src/stm32_userleds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include + +#include "stm32.h" +#include "nucleo-f103rb.h" + +#ifndef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_userled_initialize + ****************************************************************************/ + +uint32_t board_userled_initialize(void) +{ + /* Configure LED1 GPIO for output */ + + stm32_configgpio(GPIO_LED1); + return BOARD_NLEDS; +} + +/**************************************************************************** + * Name: board_userled + ****************************************************************************/ + +void board_userled(int led, bool ledon) +{ + if (led == BOARD_LED1) + { + stm32_gpiowrite(GPIO_LED1, ledon); + } +} + +/**************************************************************************** + * Name: board_userled_all + ****************************************************************************/ + +void board_userled_all(uint32_t ledset) +{ + stm32_gpiowrite(GPIO_LED1, (ledset & BOARD_LED1_BIT) != 0); +} + +#endif /* !CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32f1/olimex-stm32-p107/CMakeLists.txt b/boards/arm/stm32f1/olimex-stm32-p107/CMakeLists.txt new file mode 100644 index 0000000000000..0a2eaea0a5fa6 --- /dev/null +++ b/boards/arm/stm32f1/olimex-stm32-p107/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32f1/olimex-stm32-p107/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/arm/stm32/olimex-stm32-p107/Kconfig b/boards/arm/stm32f1/olimex-stm32-p107/Kconfig similarity index 100% rename from boards/arm/stm32/olimex-stm32-p107/Kconfig rename to boards/arm/stm32f1/olimex-stm32-p107/Kconfig diff --git a/boards/arm/stm32f1/olimex-stm32-p107/configs/nsh/defconfig b/boards/arm/stm32f1/olimex-stm32-p107/configs/nsh/defconfig new file mode 100644 index 0000000000000..8b360b4955289 --- /dev/null +++ b/boards/arm/stm32f1/olimex-stm32-p107/configs/nsh/defconfig @@ -0,0 +1,67 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_MMCSD_HAVE_CARDDETECT is not set +# CONFIG_MMCSD_MMCSUPPORT is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="olimex-stm32-p107" +CONFIG_ARCH_BOARD_OLIMEX_STM32P107=y +CONFIG_ARCH_CHIP="stm32f1" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F107VC=y +CONFIG_ARCH_CHIP_STM32F1=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=5483 +CONFIG_BUILTIN=y +CONFIG_CAN=y +CONFIG_ETH0_PHY_KS8721=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_MMCSD=y +CONFIG_MTD=y +CONFIG_NET=y +CONFIG_NETDB_DNSCLIENT=y +CONFIG_NETINIT_DRIPADDR=0xc0a80201 +CONFIG_NETINIT_IPADDR=0xc0a80232 +CONFIG_NETINIT_NOMAC=y +CONFIG_NETUTILS_TFTPC=y +CONFIG_NETUTILS_WEBCLIENT=y +CONFIG_NET_ETH_PKTSIZE=650 +CONFIG_NET_ICMP_SOCKET=y +CONFIG_NET_MAX_LISTENPORTS=40 +CONFIG_NET_TCP=y +CONFIG_NET_TCP_PREALLOC_CONNS=40 +CONFIG_NET_UDP=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=65536 +CONFIG_RAM_START=0x20000000 +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=192 +CONFIG_SCHED_HPWORKSTACKSIZE=1024 +CONFIG_START_DAY=21 +CONFIG_START_MONTH=9 +CONFIG_START_YEAR=2009 +CONFIG_STM32_ETHMAC=y +CONFIG_STM32_JTAG_FULL_ENABLE=y +CONFIG_STM32_PHYSR=16 +CONFIG_STM32_PHYSR_100MBPS=0x0000 +CONFIG_STM32_PHYSR_FULLDUPLEX=0x0004 +CONFIG_STM32_PHYSR_MODE=0x0004 +CONFIG_STM32_PHYSR_SPEED=0x0002 +CONFIG_STM32_PWR=y +CONFIG_STM32_USART2=y +CONFIG_STM32_USART2_REMAP=y +CONFIG_SYSTEM_NSH=y +CONFIG_SYSTEM_PING=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f1/olimex-stm32-p107/include/board.h b/boards/arm/stm32f1/olimex-stm32-p107/include/board.h new file mode 100644 index 0000000000000..612ecb223fdcf --- /dev/null +++ b/boards/arm/stm32f1/olimex-stm32-p107/include/board.h @@ -0,0 +1,145 @@ +/**************************************************************************** + * boards/arm/stm32f1/olimex-stm32-p107/include/board.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_STM32_OLIMEX_STM32_P107_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32_OLIMEX_STM32_P107_INCLUDE_BOARD_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#ifndef __ASSEMBLY__ +# include +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Clocking *****************************************************************/ + +/* HSI - 8 MHz RC factory-trimmed + * LSI - 40 KHz RC (30-60KHz, uncalibrated) + * HSE - On-board crystal frequency is 25MHz + * LSE - 32.768 kHz + */ + +#define STM32_BOARD_XTAL 25000000ul + +#define STM32_HSI_FREQUENCY 8000000ul +#define STM32_LSI_FREQUENCY 40000 +#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL +#define STM32_LSE_FREQUENCY 32768 + +/* PLL output is 72MHz */ + +#define STM32_PLL_PREDIV2 RCC_CFGR2_PREDIV2d5 /* 25MHz / 5 => 5MHz */ +#define STM32_PLL_PLL2MUL RCC_CFGR2_PLL2MULx8 /* 5MHz * 8 => 40MHz */ +#define STM32_PLL_PREDIV1 RCC_CFGR2_PREDIV1d5 /* 40MHz / 5 => 8MHz */ +#define STM32_PLL_PLLMUL RCC_CFGR_PLLMUL_CLKx9 /* 8MHz * 9 => 72Mhz */ +#define STM32_PLL_FREQUENCY (72000000) + +/* SYCLLK and HCLK are the PLL frequency */ + +#define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY +#define STM32_HCLK_FREQUENCY STM32_PLL_FREQUENCY + +/* APB2 clock (PCLK2) is HCLK (72MHz) */ + +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK +#define STM32_PCLK2_FREQUENCY STM32_HCLK_FREQUENCY +#define STM32_APB2_CLKIN (STM32_PCLK2_FREQUENCY) /* Timers 2-7, 12-14 */ + +/* APB2 timers 1 and 8 will receive PCLK2. */ + +#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) + +/* APB1 clock (PCLK1) is HCLK/2 (36MHz) */ + +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd2 +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/2) + +/* APB1 timers 2-7 will be twice PCLK1 */ + +#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) + +/* MCO output driven by PLL3. From above, we already have PLL3 input + * frequency as: + * + * STM32_PLL_PREDIV2 = 5, 25MHz / 5 => 5MHz + */ + +#if defined(CONFIG_STM32_MII_MCO) || defined(CONFIG_STM32_RMII_MCO) +# define BOARD_CFGR_MCO_SOURCE RCC_CFGR_PLL3CLK /* Source: PLL3 */ +# define STM32_PLL_PLL3MUL RCC_CFGR2_PLL3MULx10 /* MCO 5MHz * 10 = 50MHz */ +#endif + +/* Alternate function pin selections (auto-aliased for new pinmap) */ + +/* USART2 */ + +#define GPIO_USART2_TX GPIO_ADJUST_MODE(GPIO_USART2_TX_0, GPIO_MODE_50MHz) +#define GPIO_USART2_RX GPIO_USART2_RX_0 +#define GPIO_USART2_CTS GPIO_USART2_CTS_0 +#define GPIO_USART2_RTS GPIO_ADJUST_MODE(GPIO_USART2_RTS_0, GPIO_MODE_50MHz) +#define GPIO_USART2_CK GPIO_ADJUST_MODE(GPIO_USART2_CK_0, GPIO_MODE_50MHz) + +/* MCO */ + +#define GPIO_MCO GPIO_ADJUST_MODE(GPIO_MCO_0, GPIO_MODE_50MHz) + +/* Ethernet (MII/RMII) */ + +#define GPIO_ETH_MDC GPIO_ADJUST_MODE(GPIO_ETH_MDC_0, GPIO_MODE_50MHz) +#define GPIO_ETH_MDIO GPIO_ADJUST_MODE(GPIO_ETH_MDIO_0, GPIO_MODE_50MHz) +#define GPIO_ETH_MII_COL GPIO_ETH_MII_COL_0 +#define GPIO_ETH_MII_CRS GPIO_ETH_MII_CRS_0 +#define GPIO_ETH_MII_RX_CLK GPIO_ETH_MII_RX_CLK_0 +#define GPIO_ETH_MII_RXD0 GPIO_ETH_MII_RXD0_0 +#define GPIO_ETH_MII_RXD1 GPIO_ETH_MII_RXD1_0 +#define GPIO_ETH_MII_RXD2 GPIO_ETH_MII_RXD2_0 +#define GPIO_ETH_MII_RXD3 GPIO_ETH_MII_RXD3_0 +#define GPIO_ETH_MII_RX_DV GPIO_ETH_MII_RX_DV_0 +#define GPIO_ETH_MII_RX_ER GPIO_ETH_MII_RX_ER_0 +#define GPIO_ETH_MII_TX_CLK GPIO_ETH_MII_TX_CLK_0 +#define GPIO_ETH_MII_TXD0 GPIO_ADJUST_MODE(GPIO_ETH_MII_TXD0_0, GPIO_MODE_50MHz) +#define GPIO_ETH_MII_TXD1 GPIO_ADJUST_MODE(GPIO_ETH_MII_TXD1_0, GPIO_MODE_50MHz) +#define GPIO_ETH_MII_TXD2 GPIO_ADJUST_MODE(GPIO_ETH_MII_TXD2_0, GPIO_MODE_50MHz) +#define GPIO_ETH_MII_TXD3 GPIO_ADJUST_MODE(GPIO_ETH_MII_TXD3_0, GPIO_MODE_50MHz) +#define GPIO_ETH_MII_TX_EN GPIO_ADJUST_MODE(GPIO_ETH_MII_TX_EN_0, GPIO_MODE_50MHz) +#define GPIO_ETH_RMII_CRS_DV GPIO_ETH_RMII_CRS_DV_0 +#define GPIO_ETH_RMII_REF_CLK GPIO_ETH_RMII_REF_CLK_0 +#define GPIO_ETH_RMII_RXD0 GPIO_ETH_RMII_RXD0_0 +#define GPIO_ETH_RMII_RXD1 GPIO_ETH_RMII_RXD1_0 +#define GPIO_ETH_RMII_TXD0 GPIO_ADJUST_MODE(GPIO_ETH_RMII_TXD0_0, GPIO_MODE_50MHz) +#define GPIO_ETH_RMII_TXD1 GPIO_ADJUST_MODE(GPIO_ETH_RMII_TXD1_0, GPIO_MODE_50MHz) +#define GPIO_ETH_RMII_TX_EN GPIO_ADJUST_MODE(GPIO_ETH_RMII_TX_EN_0, GPIO_MODE_50MHz) + +#endif /* __BOARDS_ARM_STM32_OLIMEX_STM32_P107_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32f1/olimex-stm32-p107/scripts/Make.defs b/boards/arm/stm32f1/olimex-stm32-p107/scripts/Make.defs new file mode 100644 index 0000000000000..dda83d8898358 --- /dev/null +++ b/boards/arm/stm32f1/olimex-stm32-p107/scripts/Make.defs @@ -0,0 +1,46 @@ +############################################################################ +# boards/arm/stm32f1/olimex-stm32-p107/scripts/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/.config +include $(TOPDIR)/tools/Config.mk +include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs + +ifeq ($(CONFIG_STM32_DFU),y) + LDSCRIPT = ld.script.dfu +else + LDSCRIPT = ld.script +endif + +ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) + +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-gotoff.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32f1/olimex-stm32-p107/scripts/ld.script b/boards/arm/stm32f1/olimex-stm32-p107/scripts/ld.script new file mode 100644 index 0000000000000..7a37a617e0702 --- /dev/null +++ b/boards/arm/stm32f1/olimex-stm32-p107/scripts/ld.script @@ -0,0 +1,115 @@ +/**************************************************************************** + * boards/arm/stm32f1/olimex-stm32-p107/scripts/ld.script + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +MEMORY +{ + flash (rx) : ORIGIN = 0x08000000, LENGTH = 256K + sram (rwx) : ORIGIN = 0x20000000, LENGTH = 64K +} + +OUTPUT_ARCH(arm) +EXTERN(_vectors) +ENTRY(_stext) +SECTIONS +{ + .text : { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > flash + + .init_section : ALIGN(4) { + _sinit = ABSOLUTE(.); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) + _einit = ABSOLUTE(.); + } > flash + + .ARM.extab : ALIGN(4) { + *(.ARM.extab*) + } > flash + + .ARM.exidx : ALIGN(4) { + __exidx_start = ABSOLUTE(.); + *(.ARM.exidx*) + __exidx_end = ABSOLUTE(.); + } > flash + + .tdata : { + _stdata = ABSOLUTE(.); + *(.tdata .tdata.* .gnu.linkonce.td.*); + _etdata = ABSOLUTE(.); + } > flash + + .tbss : { + _stbss = ABSOLUTE(.); + *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); + _etbss = ABSOLUTE(.); + } > flash + + _eronly = ABSOLUTE(.); + + /* The STM32F107VC has 64Kb of SRAM beginning at the following address */ + + .data : ALIGN(4) { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > sram AT > flash + + .bss : ALIGN(4) { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + _ebss = ABSOLUTE(.); + } > sram + + /* Stabs debugging sections. */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/stm32f1/olimex-stm32-p107/scripts/ld.script.dfu b/boards/arm/stm32f1/olimex-stm32-p107/scripts/ld.script.dfu new file mode 100644 index 0000000000000..410230772b174 --- /dev/null +++ b/boards/arm/stm32f1/olimex-stm32-p107/scripts/ld.script.dfu @@ -0,0 +1,101 @@ +/**************************************************************************** + * boards/arm/stm32f1/olimex-stm32-p107/scripts/ld.script.dfu + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* Don't know if this is correct. Just 256K-48K (not testet) */ +MEMORY +{ + flash (rx) : ORIGIN = 0x08003000, LENGTH = 208K + sram (rwx) : ORIGIN = 0x20000000, LENGTH = 64K +} + +OUTPUT_ARCH(arm) +EXTERN(_vectors) +ENTRY(_stext) +SECTIONS +{ + .text : { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > flash + + .init_section : ALIGN(4) { + _sinit = ABSOLUTE(.); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) + _einit = ABSOLUTE(.); + } > flash + + .ARM.extab : ALIGN(4) { + *(.ARM.extab*) + } > flash + + .ARM.exidx : ALIGN(4) { + __exidx_start = ABSOLUTE(.); + *(.ARM.exidx*) + __exidx_end = ABSOLUTE(.); + } > flash + + _eronly = ABSOLUTE(.); + + /* The STM32F103Z has 64Kb of SRAM beginning at the following address */ + + .data : ALIGN(4) { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + _edata = ABSOLUTE(.); + } > sram AT > flash + + .bss : ALIGN(4) { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + _ebss = ABSOLUTE(.); + } > sram + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/stm32f1/olimex-stm32-p107/src/CMakeLists.txt b/boards/arm/stm32f1/olimex-stm32-p107/src/CMakeLists.txt new file mode 100644 index 0000000000000..36500b34205ae --- /dev/null +++ b/boards/arm/stm32f1/olimex-stm32-p107/src/CMakeLists.txt @@ -0,0 +1,35 @@ +# ############################################################################## +# boards/arm/stm32f1/olimex-stm32-p107/src/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(SRCS stm32_boot.c stm32_spi.c) + +if(CONFIG_STM32_CAN_CHARDRIVER) + list(APPEND SRCS stm32_can.c) +endif() + +if(CONFIG_ENCX24J600) + list(APPEND SRCS stm32_encx24j600.c) +endif() + +target_sources(board PRIVATE ${SRCS}) + +set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/ld.script") diff --git a/boards/arm/stm32f1/olimex-stm32-p107/src/Make.defs b/boards/arm/stm32f1/olimex-stm32-p107/src/Make.defs new file mode 100644 index 0000000000000..c50f59af776f6 --- /dev/null +++ b/boards/arm/stm32f1/olimex-stm32-p107/src/Make.defs @@ -0,0 +1,37 @@ +############################################################################ +# boards/arm/stm32f1/olimex-stm32-p107/src/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +CSRCS = stm32_boot.c stm32_spi.c + +ifeq ($(CONFIG_STM32_CAN_CHARDRIVER),y) +CSRCS += stm32_can.c +endif + +ifeq ($(CONFIG_ENCX24J600),y) +CSRCS += stm32_encx24j600.c +endif + +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/olimex-stm32-p107/src/olimex-stm32-p107.h b/boards/arm/stm32f1/olimex-stm32-p107/src/olimex-stm32-p107.h similarity index 98% rename from boards/arm/stm32/olimex-stm32-p107/src/olimex-stm32-p107.h rename to boards/arm/stm32f1/olimex-stm32-p107/src/olimex-stm32-p107.h index 4ce6a7ce0f9cb..97366814f1fe6 100644 --- a/boards/arm/stm32/olimex-stm32-p107/src/olimex-stm32-p107.h +++ b/boards/arm/stm32f1/olimex-stm32-p107/src/olimex-stm32-p107.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/olimex-stm32-p107/src/olimex-stm32-p107.h + * boards/arm/stm32f1/olimex-stm32-p107/src/olimex-stm32-p107.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f1/olimex-stm32-p107/src/stm32_boot.c b/boards/arm/stm32f1/olimex-stm32-p107/src/stm32_boot.c new file mode 100644 index 0000000000000..63c23905de96e --- /dev/null +++ b/boards/arm/stm32f1/olimex-stm32-p107/src/stm32_boot.c @@ -0,0 +1,99 @@ +/**************************************************************************** + * boards/arm/stm32f1/olimex-stm32-p107/src/stm32_boot.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include + +#include +#include +#include + +#include "stm32.h" +#include "arm_internal.h" +#include "olimex-stm32-p107.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_boardinitialize + * + * Description: + * All STM32 architectures must provide the following entry point. + * This entry point is called early in the initialization -- after all + * memory has been configured and mapped but before any devices have been + * initialized. + * + ****************************************************************************/ + +void stm32_boardinitialize(void) +{ + /* Configure SPI chip selects if 1) SPI is not disabled, and 2) the weak + * function stm32_spidev_initialize() has been brought into the link. + */ + +#if defined(CONFIG_STM32_SPI3) + if (stm32_spidev_initialize) + { + stm32_spidev_initialize(); + } +#endif +} + +/**************************************************************************** + * Name: board_late_initialize + * + * Description: + * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_late_initialize(). board_late_initialize() will + * be called immediately after up_initialize() is called and just before + * the initial application is started. + * This additional initialization phase may be used, for example, to + * initialize board-specific device drivers. + * + ****************************************************************************/ + +#ifdef CONFIG_BOARD_LATE_INITIALIZE +void board_late_initialize(void) +{ + int ret; + +#ifdef CONFIG_STM32_CAN_CHARDRIVER + /* Initialize CAN and register the CAN driver. */ + + ret = stm32_can_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_can_setup failed: %d\n", ret); + } +#endif + + UNUSED(ret); +} +#endif diff --git a/boards/arm/stm32f1/olimex-stm32-p107/src/stm32_can.c b/boards/arm/stm32f1/olimex-stm32-p107/src/stm32_can.c new file mode 100644 index 0000000000000..e6381bb949c36 --- /dev/null +++ b/boards/arm/stm32f1/olimex-stm32-p107/src/stm32_can.c @@ -0,0 +1,103 @@ +/**************************************************************************** + * boards/arm/stm32f1/olimex-stm32-p107/src/stm32_can.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32.h" +#include "stm32_can.h" + +#ifdef CONFIG_CAN + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* The STM32F107VC supports CAN1 and CAN2 */ + +#if defined(CONFIG_STM32_CAN1) && defined(CONFIG_STM32_CAN2) +# warning "Both CAN1 and CAN2 are enabled. Only CAN1 is used." +# undef CONFIG_STM32_CAN2 +#endif + +#ifdef CONFIG_STM32_CAN1 +# define CAN_PORT 1 +#else +# define CAN_PORT 2 +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_can_setup + * + * Description: + * Initialize CAN and register the CAN device + * + ****************************************************************************/ + +int stm32_can_setup(void) +{ +#if defined(CONFIG_STM32_CAN1) || defined(CONFIG_STM32_CAN2) + struct can_dev_s *can; + int ret; + + /* Call stm32_caninitialize() to get an instance of the CAN interface */ + + can = stm32_caninitialize(CAN_PORT); + if (can == NULL) + { + canerr("ERROR: Failed to get CAN interface\n"); + return -ENODEV; + } + + /* Register the CAN driver at "/dev/can0" */ + + ret = can_register("/dev/can0", can); + if (ret < 0) + { + canerr("ERROR: can_register failed: %d\n", ret); + return ret; + } + + return OK; +#else + return -ENODEV; +#endif +} + +#endif /* CONFIG_CAN */ diff --git a/boards/arm/stm32/olimex-stm32-p107/src/stm32_encx24j600.c b/boards/arm/stm32f1/olimex-stm32-p107/src/stm32_encx24j600.c similarity index 99% rename from boards/arm/stm32/olimex-stm32-p107/src/stm32_encx24j600.c rename to boards/arm/stm32f1/olimex-stm32-p107/src/stm32_encx24j600.c index c689ee908232f..a3b484f5a1667 100644 --- a/boards/arm/stm32/olimex-stm32-p107/src/stm32_encx24j600.c +++ b/boards/arm/stm32f1/olimex-stm32-p107/src/stm32_encx24j600.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/olimex-stm32-p107/src/stm32_encx24j600.c + * boards/arm/stm32f1/olimex-stm32-p107/src/stm32_encx24j600.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f1/olimex-stm32-p107/src/stm32_spi.c b/boards/arm/stm32f1/olimex-stm32-p107/src/stm32_spi.c new file mode 100644 index 0000000000000..19f74116c0cb2 --- /dev/null +++ b/boards/arm/stm32f1/olimex-stm32-p107/src/stm32_spi.c @@ -0,0 +1,121 @@ +/**************************************************************************** + * boards/arm/stm32f1/olimex-stm32-p107/src/stm32_spi.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "arm_internal.h" +#include "chip.h" +#include "stm32.h" + +#include "olimex-stm32-p107.h" + +#if defined(CONFIG_STM32_SPI3) + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_spidev_initialize + * + * Description: + * Called to configure SPI chip select GPIO pins for the Olimex stm32-p107 + * board. + * + ****************************************************************************/ + +void weak_function stm32_spidev_initialize(void) +{ + /* NOTE: Clocking for SPI3 was already provided in stm32_rcc.c. + * Configurations of SPI pins is performed in stm32_spi.c. + * Here, we only initialize chip select pins unique to the board + * architecture. + */ + + /* Configure ENCX24J600 SPI1 CS (also RESET and interrupt pins) */ + +#if defined(CONFIG_ENCX24J600) && defined(CONFIG_STM32_SPI3) + stm32_configgpio(GPIO_ENCX24J600_CS); + stm32_configgpio(GPIO_ENCX24J600_INTR); +#endif +} + +/**************************************************************************** + * Name: stm32_spi1/2/3select and stm32_spi1/2/3status + * + * Description: + * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status + * must be provided by board-specific logic. They are implementations of + * the select and status methods of the SPI interface defined by struct + * spi_ops_s (see include/nuttx/spi/spi.h). All other methods + * (including stm32_spibus_initialize()) are provided by common STM32 + * logic. To use this common SPI logic on your board: + * + * 1. Provide logic in stm32_boardinitialize() to configure SPI chip select + * pins. + * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() functions + * in your board-specific logic. These functions will perform chip + * selection and status operations using GPIOs in the way your board is + * configured. + * 3. Add a calls to stm32_spibus_initialize() in your low level + * application initialization logic + * 4. The handle returned by stm32_spibus_initialize() may then be used to + * bind the SPI driver to higher level logic (e.g., calling + * mmcsd_spislotinitialize(), for example, will bind the SPI driver to + * the SPI MMC/SD driver). + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_SPI3 +void stm32_spi3select(struct spi_dev_s *dev, + uint32_t devid, + bool selected) +{ + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); + + if (devid == SPIDEV_ETHERNET(0)) + { + /* Set the GPIO low to select and high to de-select */ + + stm32_gpiowrite(GPIO_ENCX24J600_CS, !selected); + } +} + +uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid) +{ + return SPI_STATUS_PRESENT; +} +#endif + +#endif /* CONFIG_STM32_SPI3 */ diff --git a/boards/arm/stm32f1/olimexino-stm32/CMakeLists.txt b/boards/arm/stm32f1/olimexino-stm32/CMakeLists.txt new file mode 100644 index 0000000000000..79a8aa20d7491 --- /dev/null +++ b/boards/arm/stm32f1/olimexino-stm32/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32f1/olimexino-stm32/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/arm/stm32/olimexino-stm32/Kconfig b/boards/arm/stm32f1/olimexino-stm32/Kconfig similarity index 100% rename from boards/arm/stm32/olimexino-stm32/Kconfig rename to boards/arm/stm32f1/olimexino-stm32/Kconfig diff --git a/boards/arm/stm32f1/olimexino-stm32/configs/can/defconfig b/boards/arm/stm32f1/olimexino-stm32/configs/can/defconfig new file mode 100644 index 0000000000000..250c12385ea57 --- /dev/null +++ b/boards/arm/stm32f1/olimexino-stm32/configs/can/defconfig @@ -0,0 +1,99 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_DISABLE_OS_API is not set +# CONFIG_DISABLE_PSEUDOFS_OPERATIONS is not set +# CONFIG_NSH_DISABLE_CMP is not set +# CONFIG_NSH_DISABLE_DF is not set +# CONFIG_NSH_DISABLE_EXEC is not set +# CONFIG_NSH_DISABLE_GET is not set +# CONFIG_NSH_DISABLE_HEXDUMP is not set +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_NSH_DISABLE_PUT is not set +# CONFIG_NSH_DISABLE_XD is not set +CONFIG_ANALOG=y +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="olimexino-stm32" +CONFIG_ARCH_BOARD_OLIMEXINO_STM32=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f1" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F103RB=y +CONFIG_ARCH_CHIP_STM32F1=y +CONFIG_ARCH_HIPRI_INTERRUPT=y +CONFIG_ARCH_INTERRUPTSTACK=340 +CONFIG_ARCH_IRQBUTTONS=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=5483 +CONFIG_BUILTIN=y +CONFIG_CAN_EXTID=y +CONFIG_CAN_LOOPBACK=y +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_DEFAULT_SMALL=y +CONFIG_EXAMPLES_CAN=y +CONFIG_EXAMPLES_HELLOXX=y +CONFIG_FAT_LCNAMES=y +CONFIG_FAT_LFN=y +CONFIG_FAT_MAXFNAME=12 +CONFIG_FILE_STREAM=y +CONFIG_FS_FAT=y +CONFIG_FS_FATTIME=y +CONFIG_FS_NAMED_SEMAPHORES=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_I2C=y +CONFIG_I2C_RESET=y +CONFIG_IDLETHREAD_STACKSIZE=300 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=880 +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=40 +CONFIG_MM_SMALL=y +CONFIG_NAME_MAX=8 +CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=5 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_CODECS_BUFSIZE=0 +CONFIG_NSH_FILEIOSIZE=128 +CONFIG_NSH_NESTDEPTH=0 +CONFIG_POSIX_SPAWN_DEFAULT_STACKSIZE=768 +CONFIG_PREALLOC_TIMERS=2 +CONFIG_PRIORITY_INHERITANCE=y +CONFIG_PTHREAD_STACK_DEFAULT=464 +CONFIG_RAM_SIZE=20480 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SERIAL_TERMIOS=y +CONFIG_STACK_COLORATION=y +CONFIG_START_YEAR=2014 +CONFIG_STM32_ADC1=y +CONFIG_STM32_CAN1=y +CONFIG_STM32_CAN1_REMAP1=y +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_FLOWCONTROL_BROKEN=y +CONFIG_STM32_FORCEPOWER=y +CONFIG_STM32_I2C2=y +CONFIG_STM32_I2C_DUTY16_9=y +CONFIG_STM32_I2C_DYNTIMEO=y +CONFIG_STM32_I2C_DYNTIMEO_STARTSTOP=10 +CONFIG_STM32_I2C_DYNTIMEO_USECPERBYTE=40 +CONFIG_STM32_JTAG_FULL_ENABLE=y +CONFIG_STM32_PWR=y +CONFIG_STM32_SERIAL_DISABLE_REORDERING=y +CONFIG_STM32_SPI2=y +CONFIG_STM32_TIM1=y +CONFIG_STM32_TIM1_PARTIAL_REMAP=y +CONFIG_STM32_TIM3=y +CONFIG_STM32_TIM3_PARTIAL_REMAP=y +CONFIG_STM32_USART1=y +CONFIG_SYMTAB_ORDEREDBYNAME=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=12 +CONFIG_USART1_RXBUFSIZE=32 +CONFIG_USART1_SERIAL_CONSOLE=y +CONFIG_USART1_TXBUFSIZE=32 diff --git a/boards/arm/stm32f1/olimexino-stm32/configs/composite/defconfig b/boards/arm/stm32f1/olimexino-stm32/configs/composite/defconfig new file mode 100644 index 0000000000000..15da06b5596df --- /dev/null +++ b/boards/arm/stm32f1/olimexino-stm32/configs/composite/defconfig @@ -0,0 +1,133 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_DISABLE_OS_API is not set +# CONFIG_DISABLE_PSEUDOFS_OPERATIONS is not set +# CONFIG_MMCSD_HAVE_CARDDETECT is not set +# CONFIG_NSH_DISABLEBG is not set +# CONFIG_NSH_DISABLESCRIPT is not set +# CONFIG_NSH_DISABLE_CMP is not set +# CONFIG_NSH_DISABLE_DF is not set +# CONFIG_NSH_DISABLE_EXEC is not set +# CONFIG_NSH_DISABLE_EXIT is not set +# CONFIG_NSH_DISABLE_GET is not set +# CONFIG_NSH_DISABLE_HEXDUMP is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_ITEF is not set +# CONFIG_NSH_DISABLE_LOOPS is not set +# CONFIG_NSH_DISABLE_LOSETUP is not set +# CONFIG_NSH_DISABLE_MKRD is not set +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_NSH_DISABLE_PUT is not set +# CONFIG_NSH_DISABLE_SEMICOLON is not set +# CONFIG_NSH_DISABLE_WGET is not set +# CONFIG_NSH_DISABLE_XD is not set +# CONFIG_SPI_CALLBACK is not set +CONFIG_ANALOG=y +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="olimexino-stm32" +CONFIG_ARCH_BOARD_OLIMEXINO_STM32=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f1" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F103RB=y +CONFIG_ARCH_CHIP_STM32F1=y +CONFIG_ARCH_HIPRI_INTERRUPT=y +CONFIG_ARCH_INTERRUPTSTACK=340 +CONFIG_ARCH_IRQBUTTONS=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=5483 +CONFIG_BUILTIN=y +CONFIG_CDCACM=y +CONFIG_CDCACM_COMPOSITE=y +CONFIG_CDCACM_NRDREQS=2 +CONFIG_CDCACM_NWRREQS=2 +CONFIG_CDCACM_RXBUFSIZE=96 +CONFIG_CDCACM_TXBUFSIZE=96 +CONFIG_COMPOSITE_IAD=y +CONFIG_COMPOSITE_PRODUCTID=0x2022 +CONFIG_COMPOSITE_PRODUCTSTR="Composite Device" +CONFIG_COMPOSITE_VENDORID=0x03eb +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_DEFAULT_SMALL=y +CONFIG_EXAMPLES_HELLOXX=y +CONFIG_FAT_LCNAMES=y +CONFIG_FAT_LFN=y +CONFIG_FAT_MAXFNAME=12 +CONFIG_FILE_STREAM=y +CONFIG_FS_FAT=y +CONFIG_FS_FATTIME=y +CONFIG_FS_NAMED_SEMAPHORES=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_IDLETHREAD_STACKSIZE=300 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=880 +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=40 +CONFIG_MMCSD=y +CONFIG_MM_SMALL=y +CONFIG_NAME_MAX=8 +CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=5 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_CODECS_BUFSIZE=0 +CONFIG_NSH_FILEIOSIZE=128 +CONFIG_POSIX_SPAWN_DEFAULT_STACKSIZE=768 +CONFIG_PREALLOC_TIMERS=2 +CONFIG_PRIORITY_INHERITANCE=y +CONFIG_PTHREAD_STACK_DEFAULT=464 +CONFIG_RAM_SIZE=20480 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SERIAL_TERMIOS=y +CONFIG_STACK_COLORATION=y +CONFIG_STM32_ADC1=y +CONFIG_STM32_BKP=y +CONFIG_STM32_CRC=y +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_DMA1=y +CONFIG_STM32_DMA2=y +CONFIG_STM32_DMACAPABLE=y +CONFIG_STM32_FLOWCONTROL_BROKEN=y +CONFIG_STM32_FORCEPOWER=y +CONFIG_STM32_I2C2=y +CONFIG_STM32_I2C_DUTY16_9=y +CONFIG_STM32_I2C_DYNTIMEO=y +CONFIG_STM32_I2C_DYNTIMEO_STARTSTOP=10 +CONFIG_STM32_I2C_DYNTIMEO_USECPERBYTE=40 +CONFIG_STM32_JTAG_FULL_ENABLE=y +CONFIG_STM32_PWR=y +CONFIG_STM32_RTC=y +CONFIG_STM32_SERIAL_DISABLE_REORDERING=y +CONFIG_STM32_SPI1=y +CONFIG_STM32_SPI2=y +CONFIG_STM32_TIM1=y +CONFIG_STM32_TIM1_PARTIAL_REMAP=y +CONFIG_STM32_TIM3=y +CONFIG_STM32_TIM3_PARTIAL_REMAP=y +CONFIG_STM32_USART1=y +CONFIG_STM32_USART2=y +CONFIG_STM32_USB=y +CONFIG_SYMTAB_ORDEREDBYNAME=y +CONFIG_SYSTEM_COMPOSITE=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=12 +CONFIG_USART1_RXBUFSIZE=32 +CONFIG_USART1_SERIAL_CONSOLE=y +CONFIG_USART1_TXBUFSIZE=32 +CONFIG_USART2_RXBUFSIZE=32 +CONFIG_USART2_TXBUFSIZE=32 +CONFIG_USBDEV_COMPOSITE=y +CONFIG_USBMSC=y +CONFIG_USBMSC_COMPOSITE=y +CONFIG_USBMSC_NRDREQS=2 +CONFIG_USBMSC_NWRREQS=2 +CONFIG_USBMSC_REMOVABLE=y +CONFIG_USBMSC_SCSI_STACKSIZE=340 +CONFIG_WATCHDOG=y diff --git a/boards/arm/stm32f1/olimexino-stm32/configs/nsh/defconfig b/boards/arm/stm32f1/olimexino-stm32/configs/nsh/defconfig new file mode 100644 index 0000000000000..d5366a2e5fcc6 --- /dev/null +++ b/boards/arm/stm32f1/olimexino-stm32/configs/nsh/defconfig @@ -0,0 +1,114 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_DISABLE_OS_API is not set +# CONFIG_DISABLE_PSEUDOFS_OPERATIONS is not set +# CONFIG_MMCSD_HAVE_CARDDETECT is not set +# CONFIG_NSH_DISABLEBG is not set +# CONFIG_NSH_DISABLESCRIPT is not set +# CONFIG_NSH_DISABLE_CMP is not set +# CONFIG_NSH_DISABLE_DF is not set +# CONFIG_NSH_DISABLE_EXEC is not set +# CONFIG_NSH_DISABLE_EXIT is not set +# CONFIG_NSH_DISABLE_GET is not set +# CONFIG_NSH_DISABLE_HEXDUMP is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_ITEF is not set +# CONFIG_NSH_DISABLE_LOOPS is not set +# CONFIG_NSH_DISABLE_LOSETUP is not set +# CONFIG_NSH_DISABLE_MKRD is not set +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_NSH_DISABLE_PUT is not set +# CONFIG_NSH_DISABLE_SEMICOLON is not set +# CONFIG_NSH_DISABLE_WGET is not set +# CONFIG_NSH_DISABLE_XD is not set +# CONFIG_SPI_CALLBACK is not set +CONFIG_ANALOG=y +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="olimexino-stm32" +CONFIG_ARCH_BOARD_OLIMEXINO_STM32=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f1" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F103RB=y +CONFIG_ARCH_CHIP_STM32F1=y +CONFIG_ARCH_HIPRI_INTERRUPT=y +CONFIG_ARCH_INTERRUPTSTACK=340 +CONFIG_ARCH_IRQBUTTONS=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=5483 +CONFIG_BUILTIN=y +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_DEFAULT_SMALL=y +CONFIG_EXAMPLES_HELLOXX=y +CONFIG_FAT_LCNAMES=y +CONFIG_FAT_LFN=y +CONFIG_FAT_MAXFNAME=12 +CONFIG_FILE_STREAM=y +CONFIG_FS_FAT=y +CONFIG_FS_FATTIME=y +CONFIG_FS_NAMED_SEMAPHORES=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_IDLETHREAD_STACKSIZE=300 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=880 +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=40 +CONFIG_MMCSD=y +CONFIG_MM_SMALL=y +CONFIG_NAME_MAX=8 +CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=5 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_CODECS_BUFSIZE=0 +CONFIG_NSH_FILEIOSIZE=128 +CONFIG_POSIX_SPAWN_DEFAULT_STACKSIZE=768 +CONFIG_PREALLOC_TIMERS=2 +CONFIG_PRIORITY_INHERITANCE=y +CONFIG_PTHREAD_STACK_DEFAULT=464 +CONFIG_RAM_SIZE=20480 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SERIAL_TERMIOS=y +CONFIG_STACK_COLORATION=y +CONFIG_STM32_ADC1=y +CONFIG_STM32_BKP=y +CONFIG_STM32_CRC=y +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_DMA1=y +CONFIG_STM32_DMA2=y +CONFIG_STM32_DMACAPABLE=y +CONFIG_STM32_FLOWCONTROL_BROKEN=y +CONFIG_STM32_FORCEPOWER=y +CONFIG_STM32_I2C2=y +CONFIG_STM32_I2C_DUTY16_9=y +CONFIG_STM32_I2C_DYNTIMEO=y +CONFIG_STM32_I2C_DYNTIMEO_STARTSTOP=10 +CONFIG_STM32_I2C_DYNTIMEO_USECPERBYTE=40 +CONFIG_STM32_JTAG_FULL_ENABLE=y +CONFIG_STM32_PWR=y +CONFIG_STM32_RTC=y +CONFIG_STM32_SERIAL_DISABLE_REORDERING=y +CONFIG_STM32_SPI1=y +CONFIG_STM32_SPI2=y +CONFIG_STM32_TIM1=y +CONFIG_STM32_TIM1_PARTIAL_REMAP=y +CONFIG_STM32_TIM3=y +CONFIG_STM32_TIM3_PARTIAL_REMAP=y +CONFIG_STM32_USART1=y +CONFIG_STM32_USART2=y +CONFIG_SYMTAB_ORDEREDBYNAME=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=12 +CONFIG_USART1_RXBUFSIZE=32 +CONFIG_USART1_SERIAL_CONSOLE=y +CONFIG_USART1_TXBUFSIZE=32 +CONFIG_USART2_RXBUFSIZE=32 +CONFIG_USART2_TXBUFSIZE=32 +CONFIG_WATCHDOG=y diff --git a/boards/arm/stm32f1/olimexino-stm32/configs/smallnsh/defconfig b/boards/arm/stm32f1/olimexino-stm32/configs/smallnsh/defconfig new file mode 100644 index 0000000000000..d21cfa15a197c --- /dev/null +++ b/boards/arm/stm32f1/olimexino-stm32/configs/smallnsh/defconfig @@ -0,0 +1,76 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_DISABLE_OS_API is not set +# CONFIG_DISABLE_PSEUDOFS_OPERATIONS is not set +# CONFIG_NSH_DISABLE_HEXDUMP is not set +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_NSH_DISABLE_XD is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="olimexino-stm32" +CONFIG_ARCH_BOARD_OLIMEXINO_STM32=y +CONFIG_ARCH_CHIP="stm32f1" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F103RB=y +CONFIG_ARCH_CHIP_STM32F1=y +CONFIG_ARCH_HIPRI_INTERRUPT=y +CONFIG_ARCH_INTERRUPTSTACK=340 +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=5483 +CONFIG_BUILTIN=y +CONFIG_CAN_EXTID=y +CONFIG_CAN_LOOPBACK=y +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_DEFAULT_SMALL=y +CONFIG_EXAMPLES_CAN=y +CONFIG_FDCLONE_STDIO=y +CONFIG_FILE_STREAM=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_IDLETHREAD_STACKSIZE=300 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=880 +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=40 +CONFIG_MM_SMALL=y +CONFIG_NAME_MAX=8 +CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=5 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_CODECS_BUFSIZE=0 +CONFIG_NSH_FILEIOSIZE=128 +CONFIG_NSH_NESTDEPTH=0 +CONFIG_POSIX_SPAWN_DEFAULT_STACKSIZE=768 +CONFIG_PREALLOC_TIMERS=2 +CONFIG_PRIORITY_INHERITANCE=y +CONFIG_PTHREAD_STACK_DEFAULT=464 +CONFIG_RAM_SIZE=20480 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKSTACKSIZE=758 +CONFIG_STACK_COLORATION=y +CONFIG_START_YEAR=2014 +CONFIG_STM32_CAN1=y +CONFIG_STM32_CAN1_REMAP1=y +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_FORCEPOWER=y +CONFIG_STM32_JTAG_FULL_ENABLE=y +CONFIG_STM32_PWR=y +CONFIG_STM32_SERIAL_DISABLE_REORDERING=y +CONFIG_STM32_SPI2=y +CONFIG_STM32_TIM1=y +CONFIG_STM32_TIM1_PARTIAL_REMAP=y +CONFIG_STM32_TIM3=y +CONFIG_STM32_TIM3_PARTIAL_REMAP=y +CONFIG_STM32_USART1=y +CONFIG_SYMTAB_ORDEREDBYNAME=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=12 +CONFIG_USART1_RXBUFSIZE=32 +CONFIG_USART1_SERIAL_CONSOLE=y +CONFIG_USART1_TXBUFSIZE=32 diff --git a/boards/arm/stm32f1/olimexino-stm32/configs/tiny/defconfig b/boards/arm/stm32f1/olimexino-stm32/configs/tiny/defconfig new file mode 100644 index 0000000000000..14bbaffe7b963 --- /dev/null +++ b/boards/arm/stm32f1/olimexino-stm32/configs/tiny/defconfig @@ -0,0 +1,75 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_LEDS is not set +# CONFIG_DISABLE_OS_API is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="olimexino-stm32" +CONFIG_ARCH_BOARD_OLIMEXINO_STM32=y +CONFIG_ARCH_CHIP="stm32f1" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F103RB=y +CONFIG_ARCH_CHIP_STM32F1=y +CONFIG_ARCH_HIPRI_INTERRUPT=y +CONFIG_ARCH_INTERRUPTSTACK=340 +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL=y +CONFIG_BOARD_LOOPSPERMSEC=5483 +CONFIG_BUILTIN=y +CONFIG_CAN_EXTID=y +CONFIG_CAN_LOOPBACK=y +CONFIG_CONSOLE_SYSLOG=y +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_DEFAULT_SMALL=y +CONFIG_DISABLE_MOUNTPOINT=y +CONFIG_EXAMPLES_CAN=y +CONFIG_FDCLONE_DISABLE=y +CONFIG_FDCLONE_STDIO=y +CONFIG_FILE_STREAM=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_IDLETHREAD_STACKSIZE=300 +CONFIG_INIT_ENTRYPOINT="can_main" +CONFIG_INIT_STACKSIZE=880 +CONFIG_INTELHEX_BINARY=y +CONFIG_MM_SMALL=y +CONFIG_NAME_MAX=8 +CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=5 +CONFIG_POSIX_SPAWN_DEFAULT_STACKSIZE=768 +CONFIG_PREALLOC_TIMERS=2 +CONFIG_PRIORITY_INHERITANCE=y +CONFIG_PTHREAD_STACK_DEFAULT=464 +CONFIG_RAM_SIZE=20480 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKSTACKSIZE=758 +CONFIG_SCHED_LPWORK=y +CONFIG_SCHED_LPWORKSTACKSIZE=768 +CONFIG_STACK_COLORATION=y +CONFIG_START_YEAR=2014 +CONFIG_STM32_CAN1=y +CONFIG_STM32_CAN1_REMAP1=y +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_FLOWCONTROL_BROKEN=y +CONFIG_STM32_FORCEPOWER=y +CONFIG_STM32_JTAG_FULL_ENABLE=y +CONFIG_STM32_PWR=y +CONFIG_STM32_SERIAL_DISABLE_REORDERING=y +CONFIG_STM32_SPI2=y +CONFIG_STM32_TIM1=y +CONFIG_STM32_TIM1_PARTIAL_REMAP=y +CONFIG_STM32_TIM3=y +CONFIG_STM32_TIM3_PARTIAL_REMAP=y +CONFIG_STM32_USART1=y +CONFIG_SYMTAB_ORDEREDBYNAME=y +CONFIG_SYSTEM_READLINE=y +CONFIG_TASK_NAME_SIZE=12 +CONFIG_USART1_RXBUFSIZE=32 +CONFIG_USART1_SERIAL_CONSOLE=y +CONFIG_USART1_TXBUFSIZE=32 diff --git a/boards/arm/stm32f1/olimexino-stm32/include/board.h b/boards/arm/stm32f1/olimexino-stm32/include/board.h new file mode 100644 index 0000000000000..43d1b956c90f3 --- /dev/null +++ b/boards/arm/stm32f1/olimexino-stm32/include/board.h @@ -0,0 +1,252 @@ +/**************************************************************************** + * boards/arm/stm32f1/olimexino-stm32/include/board.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_STM32_OLIMEXINO_STM32_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32_OLIMEXINO_STM32_INCLUDE_BOARD_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#ifndef __ASSEMBLY__ +# include +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Clocking *****************************************************************/ + +/* HSI - 8 MHz RC factory-trimmed + * LSI - 40 KHz RC (30-60KHz, uncalibrated) + * HSE - On-board crystal frequency is 8MHz + * LSE - 32.768 kHz + */ + +#define STM32_BOARD_XTAL 8000000ul + +#define STM32_HSI_FREQUENCY 8000000ul +#define STM32_LSI_FREQUENCY 40000 +#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL +#define STM32_LSE_FREQUENCY 32768 + +/* PLL source is HSE/1, + * PLL multiplier is 9: + * PLL frequency is 8MHz (XTAL) x 9 = 72MHz + */ + +#define STM32_CFGR_PLLSRC RCC_CFGR_PLLSRC +#define STM32_CFGR_PLLXTPRE 0 +#define STM32_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx9 +#define STM32_PLL_FREQUENCY (9*STM32_BOARD_XTAL) + +/* Use the PLL and set the SYSCLK source to be the PLL */ + +#define STM32_SYSCLK_SW RCC_CFGR_SW_PLL +#define STM32_SYSCLK_SWS RCC_CFGR_SWS_PLL +#define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY + +/* AHB clock (HCLK) is SYSCLK (72MHz) */ + +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK +#define STM32_HCLK_FREQUENCY STM32_PLL_FREQUENCY + +/* APB2 clock (PCLK2) is HCLK (72MHz) */ + +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK +#define STM32_PCLK2_FREQUENCY STM32_HCLK_FREQUENCY + +/* APB2 timers 1 and 8 will receive PCLK2. */ + +#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) + +/* APB1 clock (PCLK1) is HCLK/2 (36MHz) */ + +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd2 +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/2) + +/* APB1 timers 2-7 will be twice PCLK1 */ + +#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) + +/* USB divider -- Divide PLL clock by 1.5 */ + +#define STM32_CFGR_USBPRE 0 + +/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx + * otherwise frequency is 2xAPBx. + * Note: TIM1,8 are on APB2, others on APB1 + */ + +#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM2_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM3_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM4_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM5_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM6_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM7_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY + +/* Buttons ******************************************************************/ + +#define BUTTON_BOOT0_BIT (0) +#define BUTTON_BOOT0_MASK (1< flash + + .init_section : ALIGN(4) { + _sinit = ABSOLUTE(.); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) + _einit = ABSOLUTE(.); + } > flash + + .ARM.extab : ALIGN(4) { + *(.ARM.extab*) + } > flash + + .ARM.exidx : ALIGN(4) { + __exidx_start = ABSOLUTE(.); + *(.ARM.exidx*) + __exidx_end = ABSOLUTE(.); + } > flash + + .tdata : { + _stdata = ABSOLUTE(.); + *(.tdata .tdata.* .gnu.linkonce.td.*); + _etdata = ABSOLUTE(.); + } > flash + + .tbss : { + _stbss = ABSOLUTE(.); + *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); + _etbss = ABSOLUTE(.); + } > flash + + _eronly = ABSOLUTE(.); + + .data : ALIGN(4) { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > sram AT > flash + + .bss : ALIGN(4) { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + _ebss = ABSOLUTE(.); + } > sram + + /* Stabs debugging sections. */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/stm32f1/olimexino-stm32/scripts/ld.script.dfu b/boards/arm/stm32f1/olimexino-stm32/scripts/ld.script.dfu new file mode 100644 index 0000000000000..5e711e9bf4496 --- /dev/null +++ b/boards/arm/stm32f1/olimexino-stm32/scripts/ld.script.dfu @@ -0,0 +1,113 @@ +/**************************************************************************** + * boards/arm/stm32f1/olimexino-stm32/scripts/ld.script.dfu + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* Don't know if this is correct. Just 256K-48K (not tested) */ +MEMORY +{ + flash (rx) : ORIGIN = 0x08003000, LENGTH = 208K + sram (rwx) : ORIGIN = 0x20000000, LENGTH = 64K +} + +OUTPUT_ARCH(arm) +EXTERN(_vectors) +ENTRY(_stext) +SECTIONS +{ + .text : { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > flash + + .init_section : ALIGN(4) { + _sinit = ABSOLUTE(.); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) + _einit = ABSOLUTE(.); + } > flash + + .ARM.extab : ALIGN(4) { + *(.ARM.extab*) + } > flash + + .ARM.exidx : ALIGN(4) { + __exidx_start = ABSOLUTE(.); + *(.ARM.exidx*) + __exidx_end = ABSOLUTE(.); + } > flash + + .tdata : { + _stdata = ABSOLUTE(.); + *(.tdata .tdata.* .gnu.linkonce.td.*); + _etdata = ABSOLUTE(.); + } > flash + + .tbss : { + _stbss = ABSOLUTE(.); + *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); + _etbss = ABSOLUTE(.); + } > flash + + _eronly = ABSOLUTE(.); + + /* The STM32F103Z has 64Kb of SRAM beginning at the following address */ + + .data : ALIGN(4) { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + _edata = ABSOLUTE(.); + } > sram AT > flash + + .bss : ALIGN(4) { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + _ebss = ABSOLUTE(.); + } > sram + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/stm32f1/olimexino-stm32/src/CMakeLists.txt b/boards/arm/stm32f1/olimexino-stm32/src/CMakeLists.txt new file mode 100644 index 0000000000000..92c20f5852f57 --- /dev/null +++ b/boards/arm/stm32f1/olimexino-stm32/src/CMakeLists.txt @@ -0,0 +1,47 @@ +# ############################################################################## +# boards/arm/stm32f1/olimexino-stm32/src/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(SRCS stm32_boot.c stm32_spi.c stm32_leds.c) + +if(CONFIG_STM32_CAN_CHARDRIVER) + list(APPEND SRCS stm32_can.c) +endif() + +if(CONFIG_USBMSC) + list(APPEND SRCS stm32_usbmsc.c) +endif() + +if(CONFIG_USBDEV_COMPOSITE) + list(APPEND SRCS stm32_composite.c) +endif() + +if(CONFIG_USBDEV) + list(APPEND SRCS stm32_usbdev.c) +endif() + +if(CONFIG_ARCH_BUTTONS) + list(APPEND SRCS stm32_buttons.c) +endif() + +target_sources(board PRIVATE ${SRCS}) + +set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/ld.script") diff --git a/boards/arm/stm32f1/olimexino-stm32/src/Make.defs b/boards/arm/stm32f1/olimexino-stm32/src/Make.defs new file mode 100644 index 0000000000000..3e70dc2362c6e --- /dev/null +++ b/boards/arm/stm32f1/olimexino-stm32/src/Make.defs @@ -0,0 +1,49 @@ +############################################################################ +# boards/arm/stm32f1/olimexino-stm32/src/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +CSRCS = stm32_boot.c stm32_spi.c stm32_leds.c + +ifeq ($(CONFIG_STM32_CAN_CHARDRIVER),y) +CSRCS += stm32_can.c +endif + +ifeq ($(CONFIG_USBMSC),y) +CSRCS += stm32_usbmsc.c +endif + +ifeq ($(CONFIG_USBDEV_COMPOSITE),y) +CSRCS += stm32_composite.c +endif + +ifeq ($(CONFIG_USBDEV),y) +CSRCS += stm32_usbdev.c +endif + +ifeq ($(CONFIG_ARCH_BUTTONS),y) +CSRCS += stm32_buttons.c +endif + +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/olimexino-stm32/src/olimexino-stm32.h b/boards/arm/stm32f1/olimexino-stm32/src/olimexino-stm32.h similarity index 99% rename from boards/arm/stm32/olimexino-stm32/src/olimexino-stm32.h rename to boards/arm/stm32f1/olimexino-stm32/src/olimexino-stm32.h index 09d5de74303ea..e0f4f7c67c1b2 100644 --- a/boards/arm/stm32/olimexino-stm32/src/olimexino-stm32.h +++ b/boards/arm/stm32f1/olimexino-stm32/src/olimexino-stm32.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/olimexino-stm32/src/olimexino-stm32.h + * boards/arm/stm32f1/olimexino-stm32/src/olimexino-stm32.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f1/olimexino-stm32/src/stm32_boot.c b/boards/arm/stm32f1/olimexino-stm32/src/stm32_boot.c new file mode 100644 index 0000000000000..3e0ea392f3aec --- /dev/null +++ b/boards/arm/stm32f1/olimexino-stm32/src/stm32_boot.c @@ -0,0 +1,166 @@ +/**************************************************************************** + * boards/arm/stm32f1/olimexino-stm32/src/stm32_boot.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include +#include +#include +#include + +#include +#include +#include +#include + +#ifdef CONFIG_USBMONITOR +# include +#endif + +#ifdef CONFIG_USBDEV +# include "stm32_usbdev.h" +#endif + +#include "stm32.h" +#include "olimexino-stm32.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: vbus_handler + ****************************************************************************/ + +#if defined(CONFIG_USBDEV) +static int vbus_handler(int irq, void *context, void *arg) +{ + return OK; +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_boardinitialize + * + * Description: + * All STM32 architectures must provide the following entry point. + * This entry point is called early in the initialization -- after all + * memory has been configured and mapped but before any devices have been + * initialized. + * + ****************************************************************************/ + +void stm32_boardinitialize(void) +{ +#ifdef CONFIG_ARCH_LEDS + /* Configure on-board LEDs if LED support has been selected. */ + + stm32_led_initialize(); +#endif + +#ifdef CONFIG_ARCH_BUTTONS + /* Configure on-board buttons. */ + + board_button_initialize(); +#endif + +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || \ + defined(CONFIG_STM32_SPI3) + /* Configure SPI chip selects if 1) SP2 is not disabled, and 2) the weak + * function stm32_spidev_initialize() has been brought into the link. + */ + + if (stm32_spidev_initialize) + { + stm32_spidev_initialize(); + } +#endif + +#if defined(CONFIG_USBDEV) && defined(CONFIG_STM32_USB) + /* Initialize USB is 1) USBDEV is selected, 2) the USB controller is not + * disabled, and 3) the weak function stm32_usbinitialize() has been + * brought into the build. + */ + + stm32_usbinitialize(); +#endif +} + +/**************************************************************************** + * Name: board_late_initialize + * + * Description: + * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_late_initialize(). board_late_initialize() will be + * called immediately after up_initialize() is called and just before the + * initial application is started. This additional initialization phase + * may be used, for example, to initialize board-specific device drivers. + * + ****************************************************************************/ + +#ifdef CONFIG_BOARD_LATE_INITIALIZE +void board_late_initialize(void) +{ + int ret = OK; + +#ifdef CONFIG_USBMSC +#if !defined(CONFIG_NSH_BUILTIN_APPS) && !defined(CONFIG_SYSTEM_USBMSC) + ret = board_usbmsc_initialize(0); +#endif +#endif + +#if !defined(CONFIG_NSH_BUILTIN_APPS) && defined(CONFIG_USBDEV_COMPOSITE) + ret = board_composite_initialize(0); +#endif + +#ifdef CONFIG_STM32_CAN_CHARDRIVER + /* Initialize CAN and register the CAN driver. */ + + ret = stm32_can_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_can_setup failed: %d\n", ret); + } +#endif + + UNUSED(ret); + +#if defined(CONFIG_USBDEV) + stm32_usb_set_pwr_callback(vbus_handler); +#endif +} +#endif diff --git a/boards/arm/stm32f1/olimexino-stm32/src/stm32_buttons.c b/boards/arm/stm32f1/olimexino-stm32/src/stm32_buttons.c new file mode 100644 index 0000000000000..341e220517ec8 --- /dev/null +++ b/boards/arm/stm32f1/olimexino-stm32/src/stm32_buttons.c @@ -0,0 +1,126 @@ +/**************************************************************************** + * boards/arm/stm32f1/olimexino-stm32/src/stm32_buttons.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include +#include + +#include "olimexino-stm32.h" + +#ifdef CONFIG_ARCH_BUTTONS + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Button support. + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * + * After board_button_initialize() has been called, board_buttons() may be + * called to collect the state of all buttons. board_buttons() returns an + * 32-bit bit set with each bit associated with a button. + * See the BUTTON_*_BIT definitions in board.h for the meaning of each bit. + * + * board_button_irq() may be called to register an interrupt handler that + * will be called when a button is depressed or released. The ID value is + * a button enumeration value that uniquely identifies a button resource. + * See the BUTTON_* definitions in board.h for the meaning of enumeration + * value. + * + ****************************************************************************/ + +/**************************************************************************** + * Name: board_button_initialize + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. + * + ****************************************************************************/ + +uint32_t board_button_initialize(void) +{ + stm32_configgpio(BUTTON_BOOT0N); + return 1; +} + +/**************************************************************************** + * Name: board_buttons + * + * Description: + * + * After board_button_initialize() has been called, board_buttons() may be + * called to collect the state of all buttons. board_buttons() returns an + * 32-bit bit set with each bit associated with a button. + * See the BUTTON_*_BIT definitions in board.h for the meaning of each bit. + * + ****************************************************************************/ + +uint32_t board_buttons(void) +{ + return stm32_gpioread(BUTTON_BOOT0N) ? 0 : BUTTON_BOOT0_MASK; +} + +/**************************************************************************** + * Name: board_button_irq + * + * Description: + * + * board_button_irq() may be called to register an interrupt handler that + * will be called when a button is depressed or released. The ID value is + * a button enumeration value that uniquely identifies a button resource. + * See the BUTTON_* definitions in board.h for the meaning of enumeration + * value. + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_IRQBUTTONS +int board_button_irq(int id, xcpt_t irqhandler, void *arg) +{ + int ret = -EINVAL; + + /* The following should be atomic */ + + if (id == IRQBUTTON) + { + ret = stm32_gpiosetevent(BUTTON_BOOT0N, true, true, true, + irqhandler, arg); + } + + return ret; +} +#endif +#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/stm32f1/olimexino-stm32/src/stm32_can.c b/boards/arm/stm32f1/olimexino-stm32/src/stm32_can.c new file mode 100644 index 0000000000000..06c03bd103f98 --- /dev/null +++ b/boards/arm/stm32f1/olimexino-stm32/src/stm32_can.c @@ -0,0 +1,105 @@ +/**************************************************************************** + * boards/arm/stm32f1/olimexino-stm32/src/stm32_can.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32.h" +#include "stm32_can.h" + +#include "olimexino-stm32.h" + +#ifdef CONFIG_CAN + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* The STM32F107VC supports CAN1 and CAN2 */ + +#if defined(CONFIG_STM32_CAN1) && defined(CONFIG_STM32_CAN2) +# warning "Both CAN1 and CAN2 are enabled. Only CAN1 is connected." +# undef CONFIG_STM32_CAN2 +#endif + +#ifdef CONFIG_STM32_CAN1 +# define CAN_PORT 1 +#else +# define CAN_PORT 2 +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_can_setup + * + * Description: + * Initialize CAN and register the CAN device + * + ****************************************************************************/ + +int stm32_can_setup(void) +{ +#if defined(CONFIG_STM32_CAN1) || defined(CONFIG_STM32_CAN2) + struct can_dev_s *can; + int ret; + + /* Call stm32_caninitialize() to get an instance of the CAN interface */ + + can = stm32_caninitialize(CAN_PORT); + if (can == NULL) + { + canerr("ERROR: Failed to get CAN interface\n"); + return -ENODEV; + } + + /* Register the CAN driver at "/dev/can0" */ + + ret = can_register("/dev/can0", can); + if (ret < 0) + { + canerr("ERROR: can_register failed: %d\n", ret); + return ret; + } + + return OK; +#else + return -ENODEV; +#endif +} + +#endif /* CONFIG_CAN */ diff --git a/boards/arm/stm32f1/olimexino-stm32/src/stm32_composite.c b/boards/arm/stm32f1/olimexino-stm32/src/stm32_composite.c new file mode 100644 index 0000000000000..79a7efdc01ead --- /dev/null +++ b/boards/arm/stm32f1/olimexino-stm32/src/stm32_composite.c @@ -0,0 +1,448 @@ +/**************************************************************************** + * boards/arm/stm32f1/olimexino-stm32/src/stm32_composite.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#include "stm32.h" +#include "olimexino-stm32.h" + +/* There is nothing to do here if SPI support is not selected. */ + +#if defined(CONFIG_BOARDCTL_USBDEVCTRL) && defined(CONFIG_USBDEV_COMPOSITE) + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* No SPI? Then no USB MSC device in composite */ + +#ifndef CONFIG_STM32_SPI +# undef CONFIG_USBMSC_COMPOSITE +#endif + +/* SLOT number(s) could depend on the board configuration */ + +#ifdef CONFIG_ARCH_BOARD_OLIMEXINO_STM32 +# undef OLIMEXINO_STM32_MMCSDSLOTNO +# define OLIMEXINO_STM32_MMCSDSLOTNO 0 +# undef OLIMEXINO_STM32_MMCSDSPIPORTNO +# define OLIMEXINO_STM32_MMCSDSPIPORTNO 2 +#else +/* Add configuration for new STM32 boards here */ + +# error "Unrecognized STM32 board" +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#ifdef CONFIG_USBMSC_COMPOSITE +static void *g_mschandle; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_mscclassobject + * + * Description: + * If the mass storage class driver is part of composite device, then + * its instantiation and configuration is a multi-step, board-specific, + * process (See comments for usbmsc_configure below). In this case, + * board-specific logic must provide board_mscclassobject(). + * + * board_mscclassobject() is called from the composite driver. It must + * encapsulate the instantiation and configuration of the mass storage + * class and the return the mass storage device's class driver instance + * to the composite driver. + * + * Input Parameters: + * classdev - The location to return the mass storage class' device + * instance. + * + * Returned Value: + * 0 on success; a negated errno on failure + * + ****************************************************************************/ + +#ifdef CONFIG_USBMSC_COMPOSITE +static int board_mscclassobject(int minor, + struct usbdev_devinfo_s *devinfo, + struct usbdevclass_driver_s **classdev) +{ + int ret; + + DEBUGASSERT(g_mschandle == NULL); + + /* Configure the mass storage device */ + + uinfo("Configuring with NLUNS=1\n"); + ret = usbmsc_configure(1, &g_mschandle); + if (ret < 0) + { + uerr("ERROR: usbmsc_configure failed: %d\n", -ret); + return ret; + } + + uinfo("MSC handle=%p\n", g_mschandle); + + /* Bind the LUN(s) */ + + uinfo("Bind LUN=0 to /dev/mmcsd0\n"); + ret = usbmsc_bindlun(g_mschandle, "/dev/mmcsd0", 0, 0, 0, false); + if (ret < 0) + { + uerr("ERROR: usbmsc_bindlun failed for LUN 1 at /dev/mmcsd0: %d\n", + ret); + usbmsc_uninitialize(g_mschandle); + g_mschandle = NULL; + return ret; + } + + /* Get the mass storage device's class object */ + + ret = usbmsc_classobject(g_mschandle, devinfo, classdev); + if (ret < 0) + { + uerr("ERROR: usbmsc_classobject failed: %d\n", -ret); + usbmsc_uninitialize(g_mschandle); + g_mschandle = NULL; + } + + return ret; +} +#endif + +/**************************************************************************** + * Name: board_mscuninitialize + * + * Description: + * Un-initialize the USB storage class driver. This is just an + * application specific wrapper aboutn usbmsc_unitialize() that is called + * form the composite device logic. + * + * Input Parameters: + * classdev - The class driver instance previously given to the composite + * driver by board_mscclassobject(). + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_USBMSC_COMPOSITE +static void board_mscuninitialize(struct usbdevclass_driver_s *classdev) +{ + DEBUGASSERT(g_mschandle != NULL); + usbmsc_uninitialize(g_mschandle); + g_mschandle = NULL; +} +#endif + +/**************************************************************************** + * Name: board_composite0_connect + * + * Description: + * Connect the USB composite device on the specified USB device port for + * configuration 0. + * + * Input Parameters: + * port - The USB device port. + * + * Returned Value: + * A non-NULL handle value is returned on success. NULL is returned on + * any failure. + * + ****************************************************************************/ + +#ifdef CONFIG_USBMSC_COMPOSITE +static void *board_composite0_connect(int port) +{ + /* Here we are composing the configuration of the usb composite device. + * + * The standard is to use one CDC/ACM and one USB mass storage device. + */ + + struct composite_devdesc_s dev[2]; + int ifnobase = 0; + int strbase = COMPOSITE_NSTRIDS; + + /* Configure the CDC/ACM device */ + + /* Ask the cdcacm driver to fill in the constants we didn't + * know here. + */ + + cdcacm_get_composite_devdesc(&dev[0]); + + /* Overwrite and correct some values... */ + + /* The callback functions for the CDC/ACM class */ + + dev[0].classobject = cdcacm_classobject; + dev[0].uninitialize = cdcacm_uninitialize; + + /* Interfaces */ + + dev[0].devinfo.ifnobase = ifnobase; /* Offset to Interface-IDs */ + dev[0].minor = 0; /* The minor interface number */ + + /* Strings */ + + dev[0].devinfo.strbase = strbase; /* Offset to String Numbers */ + + /* Endpoints */ + + dev[0].devinfo.epno[CDCACM_EP_INTIN_IDX] = 1; + dev[0].devinfo.epno[CDCACM_EP_BULKIN_IDX] = 2; + dev[0].devinfo.epno[CDCACM_EP_BULKOUT_IDX] = 3; + + /* Count up the base numbers */ + + ifnobase += dev[0].devinfo.ninterfaces; + strbase += dev[0].devinfo.nstrings; + + /* Configure the mass storage device device */ + + /* Ask the usbmsc driver to fill in the constants we didn't + * know here. + */ + + usbmsc_get_composite_devdesc(&dev[1]); + + /* Overwrite and correct some values... */ + + /* The callback functions for the USBMSC class */ + + dev[1].classobject = board_mscclassobject; + dev[1].uninitialize = board_mscuninitialize; + + /* Interfaces */ + + dev[1].devinfo.ifnobase = ifnobase; /* Offset to Interface-IDs */ + dev[1].minor = 0; /* The minor interface number */ + + /* Strings */ + + dev[1].devinfo.strbase = strbase; /* Offset to String Numbers */ + + /* Endpoints */ + + dev[1].devinfo.epno[USBMSC_EP_BULKIN_IDX] = 5; + dev[1].devinfo.epno[USBMSC_EP_BULKOUT_IDX] = 4; + + /* Count up the base numbers */ + + ifnobase += dev[1].devinfo.ninterfaces; + strbase += dev[1].devinfo.nstrings; + + return composite_initialize(composite_getdevdescs(), dev, 2); +} +#endif + +/**************************************************************************** + * Name: board_composite1_connect + * + * Description: + * Connect the USB composite device on the specified USB device port for + * configuration 1. + * + * Input Parameters: + * port - The USB device port. + * + * Returned Value: + * A non-NULL handle value is returned on success. NULL is returned on + * any failure. + * + ****************************************************************************/ + +static void *board_composite1_connect(int port) +{ + /* REVISIT: This configuration currently fails. stm32_epallocpma() fails + * allocate a buffer for the 6th endpoint. Currently it supports 7x64 byte + * buffers, two required for EP0, leaving only buffers for 5 additional + * endpoints. + */ + +#if 0 + struct composite_devdesc_s dev[2]; + int strbase = COMPOSITE_NSTRIDS; + int ifnobase = 0; + int epno; + int i; + + for (i = 0, epno = 1; i < 2; i++) + { + /* Ask the cdcacm driver to fill in the constants we didn't know here */ + + cdcacm_get_composite_devdesc(&dev[i]); + + /* Overwrite and correct some values... */ + + /* The callback functions for the CDC/ACM class */ + + dev[i].classobject = cdcacm_classobject; + dev[i].uninitialize = cdcacm_uninitialize; + + dev[i].minor = i; /* The minor interface number */ + + /* Interfaces */ + + dev[i].devinfo.ifnobase = ifnobase; /* Offset to Interface-IDs */ + + /* Strings */ + + dev[i].devinfo.strbase = strbase; /* Offset to String Numbers */ + + /* Endpoints */ + + dev[i].devinfo.epno[CDCACM_EP_INTIN_IDX] = epno++; + dev[i].devinfo.epno[CDCACM_EP_BULKIN_IDX] = epno++; + dev[i].devinfo.epno[CDCACM_EP_BULKOUT_IDX] = epno++; + + ifnobase += dev[i].devinfo.ninterfaces; + strbase += dev[i].devinfo.nstrings; + } + + return composite_initialize(composite_getdevdescs(), dev, 2); +#else + return NULL; +#endif +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_composite_initialize + * + * Description: + * Perform architecture specific initialization of a composite USB device. + * + ****************************************************************************/ + +int board_composite_initialize(int port) +{ + /* If system/composite is built as an NSH command, then SD slot should + * already have been initialized. + * In this case, there is nothing further to be done here. + */ + + struct spi_dev_s *spi; + int ret; + + /* First, get an instance of the SPI interface */ + + syslog(LOG_INFO, "Initializing SPI port %d\n", + OLIMEXINO_STM32_MMCSDSPIPORTNO); + + spi = stm32_spibus_initialize(OLIMEXINO_STM32_MMCSDSPIPORTNO); + if (!spi) + { + syslog(LOG_ERR, "ERROR: Failed to initialize SPI port %d\n", + OLIMEXINO_STM32_MMCSDSPIPORTNO); + return -ENODEV; + } + + syslog(LOG_INFO, "Successfully initialized SPI port %d\n", + OLIMEXINO_STM32_MMCSDSPIPORTNO); + + /* Now bind the SPI interface to the MMC/SD driver */ + + syslog(LOG_INFO, "Bind SPI to the MMC/SD driver, minor=0 slot=%d\n", + OLIMEXINO_STM32_MMCSDSLOTNO); + + ret = mmcsd_spislotinitialize(0, OLIMEXINO_STM32_MMCSDSLOTNO, spi); + if (ret != OK) + { + syslog(LOG_ERR, + "ERROR: Failed to bind SPI port %d to MMC/SD minor=0 slot=%d %d\n", + OLIMEXINO_STM32_MMCSDSPIPORTNO, OLIMEXINO_STM32_MMCSDSLOTNO, + ret); + return ret; + } + + syslog(LOG_INFO, "Successfully bound SPI to the MMC/SD driver\n"); + + return OK; +} + +/**************************************************************************** + * Name: board_composite_connect + * + * Description: + * Connect the USB composite device on the specified USB device port using + * the specified configuration. The interpretation of the configid is + * board specific. + * + * Input Parameters: + * port - The USB device port. + * configid - The USB composite configuration + * + * Returned Value: + * A non-NULL handle value is returned on success. NULL is returned on + * any failure. + * + ****************************************************************************/ + +void *board_composite_connect(int port, int configid) +{ + if (configid == 0) + { +#ifdef CONFIG_USBMSC_COMPOSITE + return board_composite0_connect(port); +#else + return NULL; +#endif + } + else if (configid == 1) + { + return board_composite1_connect(port); + } + else + { + return NULL; + } +} + +#endif /* CONFIG_BOARDCTL_USBDEVCTRL && CONFIG_USBDEV_COMPOSITE */ diff --git a/boards/arm/stm32f1/olimexino-stm32/src/stm32_leds.c b/boards/arm/stm32f1/olimexino-stm32/src/stm32_leds.c new file mode 100644 index 0000000000000..49fc941fc4581 --- /dev/null +++ b/boards/arm/stm32f1/olimexino-stm32/src/stm32_leds.c @@ -0,0 +1,183 @@ +/**************************************************************************** + * boards/arm/stm32f1/olimexino-stm32/src/stm32_leds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "stm32.h" +#include "olimexino-stm32.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Dump GPIO registers */ + +#ifdef CONFIG_DEBUG_LEDS_INFO +# define led_dumpgpio(m) stm32_dumpgpio(GPIO_LED_GREEN, m) +#else +# define led_dumpgpio(m) +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#ifdef CONFIG_ARCH_LEDS +static bool g_initialized = false; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_led_initialize/board_userled_initialize + ****************************************************************************/ + +#ifdef CONFIG_ARCH_LEDS +uint32_t stm32_led_initialize(void) +#else +uint32_t board_userled_initialize(void) +#endif +{ + /* Configure all LED GPIO lines */ + + led_dumpgpio("board_*led_initialize() Entry)"); + + stm32_configgpio(GPIO_LED_YELLOW); + stm32_configgpio(GPIO_LED_GREEN); + + led_dumpgpio("board_*led_initialize() Exit"); + return BOARD_NLEDS; +} + +/**************************************************************************** + * Name: board_userled + ****************************************************************************/ + +#ifndef CONFIG_ARCH_LEDS +void board_userled(int led, bool ledon) +{ + if (led == BOARD_LED_GREEN) + { + stm32_gpiowrite(GPIO_LED_GREEN, !ledon); + } + else if (led == BOARD_LED_YELLOW) + { + stm32_gpiowrite(GPIO_LED_YELLOW, !ledon); + } +} +#endif + +/**************************************************************************** + * Name: board_userled_all + ****************************************************************************/ + +#ifndef CONFIG_ARCH_LEDS +void board_userled_all(uint32_t ledset) +{ + stm32_gpiowrite(GPIO_LED_GREEN, (ledset & BOARD_LED_YELLOW_BIT) == 0); + stm32_gpiowrite(GPIO_LED_YELLOW, (ledset & BOARD_LED_YELLOW_BIT) == 0); +} +#endif + +/**************************************************************************** + * Name: board_autoled_on + ****************************************************************************/ + +#ifdef CONFIG_ARCH_LEDS +void board_autoled_on(int led) +{ + switch (led) + { + default: + case LED_STARTED: + case LED_HEAPALLOCATE: + case LED_IRQSENABLED: + stm32_gpiowrite(GPIO_LED_GREEN, false); + stm32_gpiowrite(GPIO_LED_YELLOW, false); + break; + + case LED_STACKCREATED: + stm32_gpiowrite(GPIO_LED_GREEN, true); + stm32_gpiowrite(GPIO_LED_YELLOW, false); + g_initialized = true; + break; + + case LED_INIRQ: + case LED_SIGNAL: + case LED_ASSERTION: + case LED_PANIC: + stm32_gpiowrite(GPIO_LED_YELLOW, true); + break; + + case LED_IDLE : /* IDLE */ + stm32_gpiowrite(GPIO_LED_GREEN, false); + break; + } +} +#endif + +/**************************************************************************** + * Name: board_autoled_off + ****************************************************************************/ + +#ifdef CONFIG_ARCH_LEDS +void board_autoled_off(int led) +{ + switch (led) + { + default: + case LED_STARTED: + case LED_HEAPALLOCATE: + case LED_IRQSENABLED: + case LED_STACKCREATED: + stm32_gpiowrite(GPIO_LED_GREEN, false); + + case LED_INIRQ: + case LED_SIGNAL: + case LED_ASSERTION: + case LED_PANIC: + stm32_gpiowrite(GPIO_LED_YELLOW, false); + break; + + case LED_IDLE: /* IDLE */ + stm32_gpiowrite(GPIO_LED_GREEN, g_initialized); + break; + } +} +#endif diff --git a/boards/arm/stm32f1/olimexino-stm32/src/stm32_spi.c b/boards/arm/stm32f1/olimexino-stm32/src/stm32_spi.c new file mode 100644 index 0000000000000..50e199d75dca3 --- /dev/null +++ b/boards/arm/stm32f1/olimexino-stm32/src/stm32_spi.c @@ -0,0 +1,195 @@ +/**************************************************************************** + * boards/arm/stm32f1/olimexino-stm32/src/stm32_spi.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include + +#include +#include "chip.h" +#include "stm32.h" +#include "olimexino-stm32.h" + +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || defined(CONFIG_STM32_SPI3) + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_spidev_initialize + * + * Description: + * Called to configure SPI chip select GPIO pins for the board. + * + ****************************************************************************/ + +void weak_function stm32_spidev_initialize(void) +{ + /* Setup CS */ + +#ifdef CONFIG_STM32_SPI1 + stm32_configgpio(USER_CSN); +#endif + +#ifdef CONFIG_STM32_SPI2 + stm32_configgpio(MMCSD_CSN); +#endif +} + +/**************************************************************************** + * Name: stm32_spi1/2/3select and stm32_spi1/2/3status + * + * Description: + * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status + * must be provided by board-specific logic. They are implementations of + * the select and status methods of the SPI interface defined by struct + * spi_ops_s (see include/nuttx/spi/spi.h). All other methods (including + * stm32_spibus_initialize()) are provided by common STM32 logic. + * To use this common SPI logic on your board: + * + * 1. Provide logic in stm32_boardinitialize() to configure SPI chip + * select pins. + * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() + * functions in your board-specific logic. These functions will perform + * chip selection and status operations using GPIOs in the way your + * board is configured. + * 3. Add a calls to stm32_spibus_initialize() in your low level + * application initialization logic + * 4. The handle returned by stm32_spibus_initialize() may then be used + * to bind the SPI driver to higher level logic (e.g., calling + * mmcsd_spislotinitialize(), for example, will bind the SPI driver + * to the SPI MMC/SD driver). + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_SPI1 +void stm32_spi1select(struct spi_dev_s *dev, + uint32_t devid, bool selected) +{ + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); + if (devid == SPIDEV_USER(0)) + { + stm32_gpiowrite(USER_CSN, !selected); + } +} + +uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} +#endif + +#ifdef CONFIG_STM32_SPI2 +void stm32_spi2select(struct spi_dev_s *dev, + uint32_t devid, bool selected) +{ + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); +#if defined(CONFIG_MMCSD) + if (devid == SPIDEV_MMCSD(0)) + { + stm32_gpiowrite(MMCSD_CSN, !selected); + } +#endif +} + +uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) +{ + /* No switch on SD card socket so assume it is here */ + + return SPI_STATUS_PRESENT; +} +#endif + +#ifdef CONFIG_STM32_SPI3 +void stm32_spi3select(struct spi_dev_s *dev, + uint32_t devid, bool selected) +{ + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); +} + +uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} +#endif + +/**************************************************************************** + * Name: stm32_spi1cmddata + * + * Description: + * Set or clear the SH1101A A0 or SD1306 D/C n bit to select data (true) + * or command (false). This function must be provided by platform-specific + * logic. This is an implementation of the cmddata method of the SPI + * interface defined by struct spi_ops_s (see include/nuttx/spi/spi.h). + * + * Input Parameters: + * + * spi - SPI device that controls the bus the device that requires the CMD/ + * DATA selection. + * devid - If there are multiple devices on the bus, this selects which one + * to select cmd or data. NOTE: This design restricts, for example, + * one one SPI display per SPI bus. + * cmd - true: select command; false: select data + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_SPI_CMDDATA +#ifdef CONFIG_STM32_SPI1 +int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) +{ + return OK; +} +#endif + +#ifdef CONFIG_STM32_SPI2 +int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) +{ + return OK; +} +#endif + +#ifdef CONFIG_STM32_SPI3 +int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) +{ + return -ENODEV; +} +#endif +#endif /* CONFIG_SPI_CMDDATA */ + +#endif /* CONFIG_STM32_SPI1 || CONFIG_STM32_SPI2 */ diff --git a/boards/arm/stm32f1/olimexino-stm32/src/stm32_usbdev.c b/boards/arm/stm32f1/olimexino-stm32/src/stm32_usbdev.c new file mode 100644 index 0000000000000..fbbca672512e5 --- /dev/null +++ b/boards/arm/stm32f1/olimexino-stm32/src/stm32_usbdev.c @@ -0,0 +1,121 @@ +/**************************************************************************** + * boards/arm/stm32f1/olimexino-stm32/src/stm32_usbdev.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include + +#include + +#include "stm32.h" +#include "olimexino-stm32.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_usb_set_pwr_callback() + * + * Description: + * Input Parameters: + * pwr_changed_handler: An interrupt handler that will be called on VBUS + * power state changes. + * + ****************************************************************************/ + +void stm32_usb_set_pwr_callback(xcpt_t pwr_changed_handler) +{ + stm32_gpiosetevent(GPIO_USB_VBUS, true, true, true, + pwr_changed_handler, NULL); +} + +/**************************************************************************** + * Name: stm32_usbinitialize + * + * Description: + * Called to setup USB-related GPIO pins. + * + ****************************************************************************/ + +void stm32_usbinitialize(void) +{ + uinfo("called\n"); + + /* USB Soft Connect Pullup */ + + stm32_configgpio(GPIO_USB_PULLUPN); +} + +/**************************************************************************** + * Name: stm32_usbpullup + * + * Description: + * If USB is supported and the board supports a pullup via GPIO (for USB + * software connect and disconnect), then the board software must provide + * stm32_pullup. + * See include/nuttx/usb/usbdev.h for additional description of this + * method. Alternatively, if no pull-up GPIO the following EXTERN can + * be redefined to be NULL. + * + ****************************************************************************/ + +int stm32_usbpullup(struct usbdev_s *dev, bool enable) +{ + usbtrace(TRACE_DEVPULLUP, (uint16_t)enable); + stm32_gpiowrite(GPIO_USB_PULLUPN, !enable); + return OK; +} + +/**************************************************************************** + * Name: stm32_usbsuspend + * + * Description: + * Board logic must provide the stm32_usbsuspend logic if the USBDEV + * driver is used. This function is called whenever the USB enters or + * leaves suspend mode. This is an opportunity for the board logic to + * shutdown clocks, power, etc. while the USB is suspended. + * + ****************************************************************************/ + +void stm32_usbsuspend(struct usbdev_s *dev, bool resume) +{ + uinfo("resume: %d\n", resume); +} diff --git a/boards/arm/stm32f1/olimexino-stm32/src/stm32_usbmsc.c b/boards/arm/stm32f1/olimexino-stm32/src/stm32_usbmsc.c new file mode 100644 index 0000000000000..9a9a44a028fef --- /dev/null +++ b/boards/arm/stm32f1/olimexino-stm32/src/stm32_usbmsc.c @@ -0,0 +1,126 @@ +/**************************************************************************** + * boards/arm/stm32f1/olimexino-stm32/src/stm32_usbmsc.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include +#include + +#include "stm32.h" +#include "olimexino-stm32.h" + +/* There is nothing to do here if SPI support is not selected. */ + +#ifdef CONFIG_STM32_SPI + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +#ifndef CONFIG_SYSTEM_USBMSC_DEVMINOR1 +# define CONFIG_SYSTEM_USBMSC_DEVMINOR1 0 +#endif + +/* SLOT number(s) could depend on the board configuration */ + +#ifdef CONFIG_ARCH_BOARD_OLIMEXINO_STM32 +# undef OLIMEXINO_STM32_MMCSDSLOTNO +# define OLIMEXINO_STM32_MMCSDSLOTNO 0 +# undef OLIMEXINO_STM32_MMCSDSPIPORTNO +# define OLIMEXINO_STM32_MMCSDSPIPORTNO 2 +#else +/* Add configuration for new STM32 boards here */ + +# error "Unrecognized STM32 board" +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_usbmsc_initialize + * + * Description: + * Perform architecture specific initialization of the USB MSC device. + * + ****************************************************************************/ + +int board_usbmsc_initialize(int port) +{ + /* If system/usbmsc is built as an NSH command, then SD slot should + * already have been initialized. + * In this case, there is nothing further to be done here. + */ + + struct spi_dev_s *spi; + int ret; + + /* First, get an instance of the SPI interface */ + + syslog(LOG_INFO, "Initializing SPI port %d\n", + OLIMEXINO_STM32_MMCSDSPIPORTNO); + + spi = stm32_spibus_initialize(OLIMEXINO_STM32_MMCSDSPIPORTNO); + if (!spi) + { + syslog(LOG_ERR, "ERROR: Failed to initialize SPI port %d\n", + OLIMEXINO_STM32_MMCSDSPIPORTNO); + return -ENODEV; + } + + syslog(LOG_INFO, "Successfully initialized SPI port %d\n", + OLIMEXINO_STM32_MMCSDSPIPORTNO); + + /* Now bind the SPI interface to the MMC/SD driver */ + + syslog(LOG_INFO, "Bind SPI to the MMC/SD driver, minor=%d slot=%d\n", + CONFIG_SYSTEM_USBMSC_DEVMINOR1, OLIMEXINO_STM32_MMCSDSLOTNO); + + ret = mmcsd_spislotinitialize(CONFIG_SYSTEM_USBMSC_DEVMINOR1, + OLIMEXINO_STM32_MMCSDSLOTNO, spi); + if (ret < 0) + { + syslog(LOG_ERR, + "ERROR: Failed to bind SPI port %d to MMC/SD minor=%d slot=%d %d\n", + OLIMEXINO_STM32_MMCSDSPIPORTNO, CONFIG_SYSTEM_USBMSC_DEVMINOR1, + OLIMEXINO_STM32_MMCSDSLOTNO, ret); + return ret; + } + + syslog(LOG_INFO, "Successfully bound SPI to the MMC/SD driver\n"); + + return OK; +} + +#endif /* CONFIG_STM32_SPI */ diff --git a/boards/arm/stm32f1/shenzhou/CMakeLists.txt b/boards/arm/stm32f1/shenzhou/CMakeLists.txt new file mode 100644 index 0000000000000..23fa95383dd8e --- /dev/null +++ b/boards/arm/stm32f1/shenzhou/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32f1/shenzhou/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/arm/stm32/shenzhou/Kconfig b/boards/arm/stm32f1/shenzhou/Kconfig similarity index 100% rename from boards/arm/stm32/shenzhou/Kconfig rename to boards/arm/stm32f1/shenzhou/Kconfig diff --git a/boards/arm/stm32f1/shenzhou/configs/nsh/defconfig b/boards/arm/stm32f1/shenzhou/configs/nsh/defconfig new file mode 100644 index 0000000000000..cc6a676e941f6 --- /dev/null +++ b/boards/arm/stm32f1/shenzhou/configs/nsh/defconfig @@ -0,0 +1,77 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_SPI_CALLBACK is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="shenzhou" +CONFIG_ARCH_BOARD_SHENZHOU=y +CONFIG_ARCH_CHIP="stm32f1" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F107VC=y +CONFIG_ARCH_CHIP_STM32F1=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=5483 +CONFIG_BUILTIN=y +CONFIG_ETH0_PHY_DM9161=y +CONFIG_FAT_LCNAMES=y +CONFIG_FAT_LFN=y +CONFIG_FS_FAT=y +CONFIG_HAVE_CXX=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_MMCSD=y +CONFIG_MMCSD_SPICLOCK=12500000 +CONFIG_NET=y +CONFIG_NETDB_DNSCLIENT=y +CONFIG_NETDB_DNSSERVER_NOADDR=y +CONFIG_NETINIT_NOMAC=y +CONFIG_NETUTILS_TELNETD=y +CONFIG_NETUTILS_TFTPC=y +CONFIG_NETUTILS_WEBCLIENT=y +CONFIG_NET_ICMP_SOCKET=y +CONFIG_NET_MAX_LISTENPORTS=40 +CONFIG_NET_STATISTICS=y +CONFIG_NET_TCP=y +CONFIG_NET_TCP_PREALLOC_CONNS=40 +CONFIG_NET_UDP=y +CONFIG_NET_UDP_CHECKSUMS=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_MMCSDSPIPORTNO=1 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=65536 +CONFIG_RAM_START=0x20000000 +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_WAITPID=y +CONFIG_STM32_BKP=y +CONFIG_STM32_ETHMAC=y +CONFIG_STM32_ETH_REMAP=y +CONFIG_STM32_JTAG_FULL_ENABLE=y +CONFIG_STM32_PHYADDR=0 +CONFIG_STM32_PHYSR=17 +CONFIG_STM32_PHYSR_100FD=0x8000 +CONFIG_STM32_PHYSR_100HD=0x4000 +CONFIG_STM32_PHYSR_10FD=0x2000 +CONFIG_STM32_PHYSR_10HD=0x1000 +CONFIG_STM32_PHYSR_ALTCONFIG=y +CONFIG_STM32_PHYSR_ALTMODE=0xf000 +CONFIG_STM32_PWR=y +CONFIG_STM32_RTC=y +CONFIG_STM32_SPI1=y +CONFIG_STM32_USART2=y +CONFIG_STM32_USART2_REMAP=y +CONFIG_SYSTEM_NSH=y +CONFIG_SYSTEM_PING=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART2_RXBUFSIZE=128 +CONFIG_USART2_SERIAL_CONSOLE=y +CONFIG_USART2_TXBUFSIZE=128 diff --git a/boards/arm/stm32f1/shenzhou/configs/nxwm/defconfig b/boards/arm/stm32f1/shenzhou/configs/nxwm/defconfig new file mode 100644 index 0000000000000..39fd4cf05d07b --- /dev/null +++ b/boards/arm/stm32f1/shenzhou/configs/nxwm/defconfig @@ -0,0 +1,126 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_NXFONTS_DISABLE_16BPP is not set +# CONFIG_NXTK_DEFAULT_BORDERCOLORS is not set +# CONFIG_NX_DISABLE_16BPP is not set +# CONFIG_NX_PACKEDMSFIRST is not set +CONFIG_ADS7843E_SPIDEV=3 +CONFIG_ADS7843E_SWAPXY=y +CONFIG_ADS7843E_THRESHX=39 +CONFIG_ADS7843E_THRESHY=51 +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="shenzhou" +CONFIG_ARCH_BOARD_SHENZHOU=y +CONFIG_ARCH_CHIP="stm32f1" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F107VC=y +CONFIG_ARCH_CHIP_STM32F1=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=5483 +CONFIG_ETH0_PHY_DM9161=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_HOST_WINDOWS=y +CONFIG_INIT_ENTRYPOINT="nxwm_main" +CONFIG_INIT_STACKSIZE=1024 +CONFIG_INPUT=y +CONFIG_INPUT_ADS7843E=y +CONFIG_INTELHEX_BINARY=y +CONFIG_LCD=y +CONFIG_LCD_MAXCONTRAST=1 +CONFIG_LCD_NOGETRUN=y +CONFIG_LCD_SSD1289=y +CONFIG_LIBC_MAX_EXITFUNS=1 +CONFIG_LINE_MAX=64 +CONFIG_MQ_MAXMSGSIZE=64 +CONFIG_NET=y +CONFIG_NETDB_DNSCLIENT=y +CONFIG_NETDB_DNSCLIENT_ENTRIES=4 +CONFIG_NETDB_DNSSERVER_NOADDR=y +CONFIG_NETINIT_NOMAC=y +CONFIG_NETUTILS_TELNETD=y +CONFIG_NETUTILS_TFTPC=y +CONFIG_NETUTILS_WEBCLIENT=y +CONFIG_NET_ICMP_SOCKET=y +CONFIG_NET_MAX_LISTENPORTS=16 +CONFIG_NET_STATISTICS=y +CONFIG_NET_TCP=y +CONFIG_NET_TCP_PREALLOC_CONNS=16 +CONFIG_NET_UDP=y +CONFIG_NET_UDP_CHECKSUMS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_LIBRARY=y +CONFIG_NSH_READLINE=y +CONFIG_NX=y +CONFIG_NXFONT_SANS22X29B=y +CONFIG_NXFONT_SANS23X27=y +CONFIG_NXTERM=y +CONFIG_NXTERM_CACHESIZE=32 +CONFIG_NXTERM_CURSORCHAR=95 +CONFIG_NXTERM_MXCHARS=325 +CONFIG_NXTERM_NXKBDIN=y +CONFIG_NXTK_BORDERCOLOR1=0x5cb7 +CONFIG_NXTK_BORDERCOLOR2=0x21c9 +CONFIG_NXTK_BORDERCOLOR3=0xffdf +CONFIG_NXWIDGETS=y +CONFIG_NXWIDGETS_BPP=16 +CONFIG_NXWIDGETS_LISTENERSTACK=1596 +CONFIG_NXWIDGETS_SIZEOFCHAR=1 +CONFIG_NXWM=y +CONFIG_NXWM_BACKGROUND_IMAGE="" +CONFIG_NXWM_CALIBRATION_LISTENERSTACK=1024 +CONFIG_NXWM_HEXCALCULATOR_CUSTOM_FONTID=y +CONFIG_NXWM_HEXCALCULATOR_FONTID=5 +CONFIG_NXWM_KEYBOARD=y +CONFIG_NXWM_KEYBOARD_LISTENERPRIO=100 +CONFIG_NXWM_KEYBOARD_LISTENERSTACK=1024 +CONFIG_NXWM_NXTERM_STACKSIZE=1596 +CONFIG_NXWM_STARTWINDOW_STACKSIZE=1596 +CONFIG_NXWM_TASKBAR_LEFT=y +CONFIG_NXWM_TASKBAR_VSPACING=4 +CONFIG_NXWM_TOUCHSCREEN_LISTENERPRIO=101 +CONFIG_NXWM_TOUCHSCREEN_LISTENERSTACK=1596 +CONFIG_NX_BLOCKING=y +CONFIG_NX_KBD=y +CONFIG_NX_XYINPUT_TOUCHSCREEN=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_PTHREAD_STACK_DEFAULT=1024 +CONFIG_RAM_SIZE=65536 +CONFIG_RAM_START=0x20000000 +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=192 +CONFIG_SCHED_HPWORKSTACKSIZE=1024 +CONFIG_START_DAY=26 +CONFIG_START_MONTH=9 +CONFIG_START_YEAR=2012 +CONFIG_STM32_ETHMAC=y +CONFIG_STM32_ETH_REMAP=y +CONFIG_STM32_JTAG_FULL_ENABLE=y +CONFIG_STM32_PHYADDR=0 +CONFIG_STM32_PHYSR=17 +CONFIG_STM32_PHYSR_100FD=0x8000 +CONFIG_STM32_PHYSR_100HD=0x4000 +CONFIG_STM32_PHYSR_10FD=0x2000 +CONFIG_STM32_PHYSR_10HD=0x1000 +CONFIG_STM32_PHYSR_ALTCONFIG=y +CONFIG_STM32_PHYSR_ALTMODE=0xf000 +CONFIG_STM32_SPI3=y +CONFIG_STM32_SPI3_REMAP=y +CONFIG_STM32_USART2=y +CONFIG_STM32_USART2_REMAP=y +CONFIG_SYSTEM_PING=y +CONFIG_SYSTEM_TELNETD_SESSION_STACKSIZE=1596 +CONFIG_SYSTEM_TELNETD_STACKSIZE=1596 +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART2_RXBUFSIZE=128 +CONFIG_USART2_SERIAL_CONSOLE=y +CONFIG_USART2_TXBUFSIZE=128 diff --git a/boards/arm/stm32f1/shenzhou/configs/thttpd/defconfig b/boards/arm/stm32f1/shenzhou/configs/thttpd/defconfig new file mode 100644 index 0000000000000..9d4170bfa9e3d --- /dev/null +++ b/boards/arm/stm32f1/shenzhou/configs/thttpd/defconfig @@ -0,0 +1,90 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="shenzhou" +CONFIG_ARCH_BOARD_SHENZHOU=y +CONFIG_ARCH_CHIP="stm32f1" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F107VC=y +CONFIG_ARCH_CHIP_STM32F1=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_ARM_TOOLCHAIN_BUILDROOT=y +CONFIG_BOARD_LOOPSPERMSEC=5483 +CONFIG_BUILTIN=y +CONFIG_ETH0_PHY_DM9161=y +CONFIG_EXAMPLES_THTTPD=y +CONFIG_EXAMPLES_THTTPD_DRIPADDR=0xc0a80001 +CONFIG_EXAMPLES_THTTPD_NOMAC=y +CONFIG_FS_NXFFS=y +CONFIG_FS_ROMFS=y +CONFIG_HAVE_CXX=y +CONFIG_INIT_ENTRYPOINT="thttp_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_MTD=y +CONFIG_MTD_W25=y +CONFIG_NET=y +CONFIG_NETDB_DNSCLIENT=y +CONFIG_NETDB_DNSSERVER_NOADDR=y +CONFIG_NETINIT_DRIPADDR=0xc0a80001 +CONFIG_NETINIT_IPADDR=0xc0a80032 +CONFIG_NETINIT_NOMAC=y +CONFIG_NETUTILS_TELNETD=y +CONFIG_NETUTILS_TFTPC=y +CONFIG_NETUTILS_THTTPD=y +CONFIG_NETUTILS_WEBCLIENT=y +CONFIG_NET_BROADCAST=y +CONFIG_NET_ETH_PKTSIZE=768 +CONFIG_NET_ICMP_SOCKET=y +CONFIG_NET_MAX_LISTENPORTS=40 +CONFIG_NET_STATISTICS=y +CONFIG_NET_TCP=y +CONFIG_NET_TCP_PREALLOC_CONNS=40 +CONFIG_NET_UDP=y +CONFIG_NET_UDP_CHECKSUMS=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_NXFLAT=y +CONFIG_PIPES=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=65536 +CONFIG_RAM_START=0x20000000 +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_WAITPID=y +CONFIG_STM32_BKP=y +CONFIG_STM32_ETHMAC=y +CONFIG_STM32_ETH_REMAP=y +CONFIG_STM32_JTAG_FULL_ENABLE=y +CONFIG_STM32_PHYSR=17 +CONFIG_STM32_PHYSR_100FD=0x8000 +CONFIG_STM32_PHYSR_100HD=0x4000 +CONFIG_STM32_PHYSR_10FD=0x2000 +CONFIG_STM32_PHYSR_10HD=0x1000 +CONFIG_STM32_PHYSR_ALTCONFIG=y +CONFIG_STM32_PHYSR_ALTMODE=0xf000 +CONFIG_STM32_PWR=y +CONFIG_STM32_RTC=y +CONFIG_STM32_SPI1=y +CONFIG_STM32_USART2=y +CONFIG_STM32_USART2_REMAP=y +CONFIG_SYMTAB_ORDEREDBYNAME=y +CONFIG_SYSTEM_NSH=y +CONFIG_SYSTEM_PING=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_THTTPD_CGI_BYTECOUNT=20000 +CONFIG_THTTPD_CGI_PRIORITY=50 +CONFIG_THTTPD_CGI_STACKSIZE=1024 +CONFIG_THTTPD_IOBUFFERSIZE=1024 +CONFIG_THTTPD_IPADDR=0xc0a80032 +CONFIG_USART2_RXBUFSIZE=128 +CONFIG_USART2_SERIAL_CONSOLE=y +CONFIG_USART2_TXBUFSIZE=128 diff --git a/boards/arm/stm32f1/shenzhou/include/board.h b/boards/arm/stm32f1/shenzhou/include/board.h new file mode 100644 index 0000000000000..858074f77dfe5 --- /dev/null +++ b/boards/arm/stm32f1/shenzhou/include/board.h @@ -0,0 +1,463 @@ +/**************************************************************************** + * boards/arm/stm32f1/shenzhou/include/board.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_STM32_SHENZHOU_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32_SHENZHOU_INCLUDE_BOARD_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#ifndef __ASSEMBLY__ +# include +#endif + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Clocking *****************************************************************/ + +/* HSI - 8 MHz RC factory-trimmed + * LSI - 40 KHz RC (30-60KHz, uncalibrated) + * HSE - On-board crystal frequency is 25MHz + * LSE - 32.768 kHz + */ + +#define STM32_BOARD_XTAL 25000000ul + +#define STM32_HSI_FREQUENCY 8000000ul +#define STM32_LSI_FREQUENCY 40000 +#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL +#define STM32_LSE_FREQUENCY 32768 + +/* PLL output is 72MHz */ + +#define STM32_PLL_PREDIV2 RCC_CFGR2_PREDIV2d5 /* 25MHz / 5 => 5MHz */ +#define STM32_PLL_PLL2MUL RCC_CFGR2_PLL2MULx8 /* 5MHz * 8 => 40MHz */ +#define STM32_PLL_PREDIV1 RCC_CFGR2_PREDIV1d5 /* 40MHz / 5 => 8MHz */ +#define STM32_PLL_PLLMUL RCC_CFGR_PLLMUL_CLKx9 /* 8MHz * 9 => 72Mhz */ +#define STM32_PLL_FREQUENCY (72000000) + +/* SYCLLK and HCLK are the PLL frequency */ + +#define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY +#define STM32_HCLK_FREQUENCY STM32_PLL_FREQUENCY + +/* APB2 clock (PCLK2) is HCLK (72MHz) */ + +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK +#define STM32_PCLK2_FREQUENCY STM32_HCLK_FREQUENCY +#define STM32_APB2_CLKIN (STM32_PCLK2_FREQUENCY) /* Timers 2-7, 12-14 */ + +/* APB2 timers 1 and 8 will receive PCLK2. */ + +#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) + +/* APB1 clock (PCLK1) is HCLK/2 (36MHz) */ + +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd2 +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/2) + +/* APB1 timers 2-7 will be twice PCLK1 */ + +#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) + +/* MCO output driven by PLL3. + * From above, we already have PLL3 input frequency as: + * + * STM32_PLL_PREDIV2 = 5, 25MHz / 5 => 5MHz + */ + +#if defined(CONFIG_STM32_MII_MCO) || defined(CONFIG_STM32_RMII_MCO) +# define BOARD_CFGR_MCO_SOURCE RCC_CFGR_PLL3CLK /* Source: PLL3 */ +# define STM32_PLL_PLL3MUL RCC_CFGR2_PLL3MULx10 /* MCO 5MHz * 10 = 50MHz */ +#endif + +/* LED definitions **********************************************************/ + +/* If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs in + * any way. The following definitions are used to access individual LEDs. + */ + +/* LED index values for use with board_userled() */ + +#define BOARD_LED1 0 +#define BOARD_LED2 1 +#define BOARD_LED3 2 +#define BOARD_LED4 3 +#define BOARD_NLEDS 4 + +/* LED bits for use with board_userled_all() */ + +#define BOARD_LED1_BIT (1 << BOARD_LED1) +#define BOARD_LED2_BIT (1 << BOARD_LED2) +#define BOARD_LED3_BIT (1 << BOARD_LED3) +#define BOARD_LED4_BIT (1 << BOARD_LED4) + +/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the 4 LEDs on + * board the STM3240G-EVAL. + * The following definitions describe how NuttX controls the LEDs: + */ + +#define LED_STARTED 0 /* LED1 */ +#define LED_HEAPALLOCATE 1 /* LED2 */ +#define LED_IRQSENABLED 2 /* LED1 + LED2 */ +#define LED_STACKCREATED 3 /* LED3 */ +#define LED_INIRQ 4 /* LED1 + LED3 */ +#define LED_SIGNAL 5 /* LED2 + LED3 */ +#define LED_ASSERTION 6 /* LED1 + LED2 + LED3 */ +#define LED_PANIC 7 /* N/C + N/C + N/C + LED4 */ + +/* Button definitions *******************************************************/ + +/* The STM3240G-EVAL supports three buttons: */ + +#define BUTTON_KEY1 0 /* Name printed on board */ +#define BUTTON_KEY2 1 +#define BUTTON_KEY3 2 +#define BUTTON_KEY4 3 +#define NUM_BUTTONS 4 + +#define BUTTON_USERKEY2 BUTTON_KEY1 /* Names in schematic */ +#define BUTTON_USERKEY BUTTON_KEY2 +#define BUTTON_TAMPER BUTTON_KEY3 +#define BUTTON_WAKEUP BUTTON_KEY4 + +#define BUTTON_KEY1_BIT (1 << BUTTON_KEY1) +#define BUTTON_KEY2_BIT (1 << BUTTON_KEY2) +#define BUTTON_KEY3_BIT (1 << BUTTON_KEY3) +#define BUTTON_KEY4_BIT (1 << BUTTON_KEY4) + +#define BUTTON_USERKEY2_BIT BUTTON_KEY1_BIT +#define BUTTON_USERKEY_BIT BUTTON_KEY2_BIT +#define BUTTON_TAMPER_BIT BUTTON_KEY3_BIT +#define BUTTON_WAKEUP_BIT BUTTON_KEY4_BIT + +/* Relays */ + +#define NUM_RELAYS 2 + +/* Pin selections ***********************************************************/ + +/* Ethernet + * + * -- ---- -------------- --------------------------------------------------- + * PN NAME SIGNAL NOTES + * -- ---- -------------- --------------------------------------------------- + * 24 PA1 MII_RX_CLK Ethernet PHY NOTE: Despite the MII labeling of + * RMII_REF_CLK Ethernet PHY these signals, the DM916AEP is + * 25 PA2 MII_MDIO Ethernet PHY actually configured to work in RMII + * 48 PB11 MII_TX_EN Ethernet PHY mode. + * 51 PB12 MII_TXD0 Ethernet PHY + * 52 PB13 MII_TXD1 Ethernet PHY + * 16 PC1 MII_MDC Ethernet PHY + * 34 PC5 MII_INT Ethernet PHY + * 55 PD8 MII_RX_DV Ethernet PHY. Requires CONFIG_STM32_ETH_REMAP + * 55 PD8 RMII_CRSDV Ethernet PHY. Requires CONFIG_STM32_ETH_REMAP + * 56 PD9 MII_RXD0 Ethernet PHY. Requires CONFIG_STM32_ETH_REMAP + * 57 PD10 MII_RXD1 Ethernet PHY. Requires CONFIG_STM32_ETH_REMAP + * + * The board desdign can support a 50MHz external clock to drive the PHY + * (U9). However, on my board, U9 is not present. + * + * 67 PA8 MCO DM9161AEP + */ + +#ifdef CONFIG_STM32_ETHMAC +# ifndef CONFIG_STM32_ETH_REMAP +# error "STM32 Ethernet requires CONFIG_STM32_ETH_REMAP" +# endif +# ifndef CONFIG_STM32_RMII +# error "STM32 Ethernet requires CONFIG_STM32_RMII" +# endif +# ifndef CONFIG_STM32_RMII_MCO +# error "STM32 Ethernet requires CONFIG_STM32_RMII_MCO" +# endif +#endif + +/* USB + * + * -- ---- -------------- --------------------------------------------------- + * PN NAME SIGNAL NOTES + * -- ---- -------------- --------------------------------------------------- + * 68 PA9 USB_VBUS MINI-USB-AB. JP3 + * 69 PA10 USB_ID MINI-USB-AB. JP5 + * 70 PA11 USB_DM MINI-USB-AB + * 71 PA12 USB_DP MINI-USB-AB + * 95 PB8 USB_PWR Drives USB VBUS + */ + +/* UARTS/USARTS + * + * -- ---- -------------- --------------------------------------------------- + * PN NAME SIGNAL NOTES + * -- ---- -------------- --------------------------------------------------- + * 68 PA9 USART1_TX MAX3232 to CN5. Requires CONFIG_STM32_USART1_REMAP + * 69 PA10 USART1_RX MAX3232 to CN5. Requires CONFIG_STM32_USART1_REMAP + * 86 PD5 USART2_TX MAX3232 to CN6. Requires CONFIG_STM32_USART2_REMAP + * 87 PD6 USART2_RX MAX3232 to CN6. Requires CONFIG_STM32_USART2_REMAP + * 86 PD5 485_TX Same as USART2_TX but goes to SP3485 + * 87 PD6 485_RX Save as USART2_RX but goes to SP3485 (see JP4) + */ + +#if defined(CONFIG_STM32_USART1) && !defined(CONFIG_STM32_USART1_REMAP) +# error "CONFIG_STM32_USART1 requires CONFIG_STM32_USART1_REMAP" +#endif + +#if defined(CONFIG_STM32_USART2) && !defined(CONFIG_STM32_USART2_REMAP) +# error "CONFIG_STM32_USART2 requires CONFIG_STM32_USART2_REMAP" +#endif + +/* SPI + * + * -- ---- -------------- --------------------------------------------------- + * PN NAME SIGNAL NOTES + * -- ---- -------------- --------------------------------------------------- + * 30 PA5 SPI1_SCK To the SD card, SPI FLASH. + * Requires !CONFIG_STM32_SPI1_REMAP + * 31 PA6 SPI1_MISO To the SD card, SPI FLASH. + * Requires !CONFIG_STM32_SPI1_REMAP + * 32 PA7 SPI1_MOSI To the SD card, SPI FLASH. + * Requires !CONFIG_STM32_SPI1_REMAP + * 78 PC10 SPI3_SCK To TFT LCD (CN13), + * the NRF24L01 2.4G wireless module. + * Requires CONFIG_STM32_SPI3_REMAP. + * 79 PC11 SPI3_MISO To TFT LCD (CN13), + * the NRF24L01 2.4G wireless module. + * Requires CONFIG_STM32_SPI3_REMAP. + * 80 PC12 SPI3_MOSI To TFT LCD (CN13), + * the NRF24L01 2.4G wireless module. + * Requires CONFIG_STM32_SPI3_REMAP. + */ + +#if defined(CONFIG_STM32_SPI1) && defined(CONFIG_STM32_SPI1_REMAP) +# error "CONFIG_STM32_SPI1 must not have CONFIG_STM32_SPI1_REMAP" +#endif + +#if defined(CONFIG_STM32_SPI3) && !defined(CONFIG_STM32_SPI3_REMAP) +# error "CONFIG_STM32_SPI3 requires CONFIG_STM32_SPI3_REMAP" +#endif + +/* DAC + * + * -- ---- -------------- --------------------------------------------------- + * PN NAME SIGNAL NOTES + * -- ---- -------------- --------------------------------------------------- + * 29 PA4 DAC_OUT1 To CON5(CN14) + * 30 PA5 DAC_OUT2 To CON5(CN14). JP10 + */ + +/* ADC + * + * -- ---- -------------- --------------------------------------------------- + * PN NAME SIGNAL NOTES + * -- ---- -------------- --------------------------------------------------- + * 35 PB0 ADC_IN1 GPIO_ADC12_IN8. To CON5(CN14) + * 36 PB1 ADC_IN2 GPIO_ADC12_IN9. To CON5(CN14) + * 15 PC0 POTENTIO_METER GPIO_ADC12_IN10 + */ + +/* CAN + * + * -- ---- -------------- --------------------------------------------------- + * PN NAME SIGNAL NOTES + * -- ---- -------------- --------------------------------------------------- + * 91 PB5 CAN2_RX Requires CONFIG_STM32_CAN2_REMAP. + * 92 PB6 CAN2_TX Requires CONFIG_STM32_CAN2_REMAP. See also JP11 + * 81 PD0 CAN1_RX Requires CONFIG_STM32_CAN1_REMAP2. + * 82 PD1 CAN1_TX Requires CONFIG_STM32_CAN1_REMAP2. + */ + +#if defined(CONFIG_STM32_CAN1) && !defined(CONFIG_STM32_CAN1_REMAP2) +# error "CONFIG_STM32_CAN1 requires CONFIG_STM32_CAN1_REMAP2" +#endif + +#if defined(CONFIG_STM32_CAN2) && !defined(CONFIG_STM32_CAN2_REMAP) +# error "CONFIG_STM32_CAN2 requires CONFIG_STM32_CAN2_REMAP" +#endif + +/* I2C + * + * -- ---- -------------- --------------------------------------------------- + * PN NAME SIGNAL NOTES + * -- ---- -------------- --------------------------------------------------- + * 92 PB6 I2C1_SCL Requires !CONFIG_STM32_I2C1_REMAP + * 93 PB7 I2C1_SDA + */ + +#if defined(CONFIG_STM32_I2C1) && defined(CONFIG_STM32_I2C1_REMAP) +# error "CONFIG_STM32_I2C1 must not have CONFIG_STM32_I2C1_REMAP" +#endif + +/* I2S + * + * -- ---- -------------- --------------------------------------------------- + * PN NAME SIGNAL NOTES + * -- ---- -------------- --------------------------------------------------- + * 51 PB12 I2S_WS GPIO_I2S2_WS. Audio DAC + * 52 PB13 I2S_CK GPIO_I2S2_CK. Audio DAC + * 54 PB15 I2S_DIN ??? Audio DAC data in. + * 63 PC6 I2S_MCK GPIO_I2S2_MCK. Audio DAC. Active low: Pulled high + */ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_lcdclear + * + * Description: + * This is a non-standard LCD interface just for the Shenzhou board. + * Because of the various rotations, clearing the display in the normal way + * by writing a sequences of runs that covers the entire display can be + * very slow. Here the display is cleared by simply setting all GRAM + * memory to the specified color. + * + ****************************************************************************/ + +void stm32_lcdclear(uint16_t color); + +/**************************************************************************** + * Relay control functions + * + * Description: + * Non-standard functions for relay control from the Shenzhou board. + * + * NOTE: These must match the prototypes in include/nuttx/arch.h + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_RELAYS +void up_relaysinit(void); +void relays_setstat(int relays, bool stat); +bool relays_getstat(int relays); +void relays_setstats(uint32_t relays_stat); +uint32_t relays_getstats(void); +void relays_onoff(int relays, uint32_t mdelay); +void relays_onoffs(uint32_t relays_stat, uint32_t mdelay); +void relays_resetmode(int relays); +void relays_powermode(int relays); +void relays_resetmodes(uint32_t relays_stat); +void relays_powermodes(uint32_t relays_stat); +#endif + +/**************************************************************************** + * Chip ID functions + * + * Description: + * Non-standard functions to obtain chip ID information. + * + ****************************************************************************/ + +const char *stm32_getchipid(void); +const char *stm32_getchipid_string(void); + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ + +/* Alternate function pin selections (auto-aliased for new pinmap) */ + +/* USART2 */ + +#define GPIO_USART2_TX GPIO_ADJUST_MODE(GPIO_USART2_TX_0, GPIO_MODE_50MHz) +#define GPIO_USART2_RX GPIO_USART2_RX_0 +#define GPIO_USART2_CTS GPIO_USART2_CTS_0 +#define GPIO_USART2_RTS GPIO_ADJUST_MODE(GPIO_USART2_RTS_0, GPIO_MODE_50MHz) +#define GPIO_USART2_CK GPIO_ADJUST_MODE(GPIO_USART2_CK_0, GPIO_MODE_50MHz) + +/* SPI1 */ + +#define GPIO_SPI1_NSS GPIO_ADJUST_MODE(GPIO_SPI1_NSS_0, GPIO_MODE_50MHz) +#define GPIO_SPI1_SCK GPIO_ADJUST_MODE(GPIO_SPI1_SCK_0, GPIO_MODE_50MHz) +#define GPIO_SPI1_MISO GPIO_ADJUST_MODE(GPIO_SPI1_MISO_0, GPIO_MODE_50MHz) +#define GPIO_SPI1_MOSI GPIO_ADJUST_MODE(GPIO_SPI1_MOSI_0, GPIO_MODE_50MHz) + +/* SPI3 */ + +#define GPIO_SPI3_NSS GPIO_ADJUST_MODE(GPIO_SPI3_NSS_0, GPIO_MODE_50MHz) +#define GPIO_SPI3_SCK GPIO_ADJUST_MODE(GPIO_SPI3_SCK_0, GPIO_MODE_50MHz) +#define GPIO_SPI3_MISO GPIO_ADJUST_MODE(GPIO_SPI3_MISO_0, GPIO_MODE_50MHz) +#define GPIO_SPI3_MOSI GPIO_ADJUST_MODE(GPIO_SPI3_MOSI_0, GPIO_MODE_50MHz) + +/* MCO */ + +#define GPIO_MCO GPIO_ADJUST_MODE(GPIO_MCO_0, GPIO_MODE_50MHz) + +/* Ethernet (MII/RMII) */ + +#define GPIO_ETH_MDC GPIO_ADJUST_MODE(GPIO_ETH_MDC_0, GPIO_MODE_50MHz) +#define GPIO_ETH_MDIO GPIO_ADJUST_MODE(GPIO_ETH_MDIO_0, GPIO_MODE_50MHz) +#define GPIO_ETH_MII_COL GPIO_ETH_MII_COL_0 +#define GPIO_ETH_MII_CRS GPIO_ETH_MII_CRS_0 +#define GPIO_ETH_MII_RX_CLK GPIO_ETH_MII_RX_CLK_0 +#define GPIO_ETH_MII_RXD0 GPIO_ETH_MII_RXD0_0 +#define GPIO_ETH_MII_RXD1 GPIO_ETH_MII_RXD1_0 +#define GPIO_ETH_MII_RXD2 GPIO_ETH_MII_RXD2_0 +#define GPIO_ETH_MII_RXD3 GPIO_ETH_MII_RXD3_0 +#define GPIO_ETH_MII_RX_DV GPIO_ETH_MII_RX_DV_0 +#define GPIO_ETH_MII_RX_ER GPIO_ETH_MII_RX_ER_0 +#define GPIO_ETH_MII_TX_CLK GPIO_ETH_MII_TX_CLK_0 +#define GPIO_ETH_MII_TXD0 GPIO_ADJUST_MODE(GPIO_ETH_MII_TXD0_0, GPIO_MODE_50MHz) +#define GPIO_ETH_MII_TXD1 GPIO_ADJUST_MODE(GPIO_ETH_MII_TXD1_0, GPIO_MODE_50MHz) +#define GPIO_ETH_MII_TXD2 GPIO_ADJUST_MODE(GPIO_ETH_MII_TXD2_0, GPIO_MODE_50MHz) +#define GPIO_ETH_MII_TXD3 GPIO_ADJUST_MODE(GPIO_ETH_MII_TXD3_0, GPIO_MODE_50MHz) +#define GPIO_ETH_MII_TX_EN GPIO_ADJUST_MODE(GPIO_ETH_MII_TX_EN_0, GPIO_MODE_50MHz) +#define GPIO_ETH_RMII_CRS_DV GPIO_ETH_RMII_CRS_DV_0 +#define GPIO_ETH_RMII_REF_CLK GPIO_ETH_RMII_REF_CLK_0 +#define GPIO_ETH_RMII_RXD0 GPIO_ETH_RMII_RXD0_0 +#define GPIO_ETH_RMII_RXD1 GPIO_ETH_RMII_RXD1_0 +#define GPIO_ETH_RMII_TXD0 GPIO_ADJUST_MODE(GPIO_ETH_RMII_TXD0_0, GPIO_MODE_50MHz) +#define GPIO_ETH_RMII_TXD1 GPIO_ADJUST_MODE(GPIO_ETH_RMII_TXD1_0, GPIO_MODE_50MHz) +#define GPIO_ETH_RMII_TX_EN GPIO_ADJUST_MODE(GPIO_ETH_RMII_TX_EN_0, GPIO_MODE_50MHz) + +#endif /* __BOARDS_ARM_STM32_SHENZHOU_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32f1/shenzhou/scripts/Make.defs b/boards/arm/stm32f1/shenzhou/scripts/Make.defs new file mode 100644 index 0000000000000..d43905ce21972 --- /dev/null +++ b/boards/arm/stm32f1/shenzhou/scripts/Make.defs @@ -0,0 +1,53 @@ +############################################################################ +# boards/arm/stm32f1/shenzhou/scripts/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/.config +include $(TOPDIR)/tools/Config.mk +include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs + +# Pick the linker script + +ifeq ($(CONFIG_STM32_DFU),y) + LDSCRIPT = ld.script.dfu +else + LDSCRIPT = ld.script +endif + +ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) + +MKNXFLAT = mknxflat +LDNXFLAT = ldnxflat + +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-gotoff.ld -no-check-sections +#NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections + +LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32f1/shenzhou/scripts/ld.script b/boards/arm/stm32f1/shenzhou/scripts/ld.script new file mode 100644 index 0000000000000..8487eb9e18295 --- /dev/null +++ b/boards/arm/stm32f1/shenzhou/scripts/ld.script @@ -0,0 +1,119 @@ +/**************************************************************************** + * boards/arm/stm32f1/shenzhou/scripts/ld.script + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* The STM32F107VC has 256K of FLASH beginning at address 0x0800:0000 and + * 64K of SRAM beginning at address 0x2000:0000. + */ + +MEMORY +{ + flash (rx) : ORIGIN = 0x08000000, LENGTH = 256K + sram (rwx) : ORIGIN = 0x20000000, LENGTH = 64K +} + +OUTPUT_ARCH(arm) +EXTERN(_vectors) +ENTRY(_stext) +SECTIONS +{ + .text : { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > flash + + .init_section : ALIGN(4) { + _sinit = ABSOLUTE(.); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) + _einit = ABSOLUTE(.); + } > flash + + .ARM.extab : ALIGN(4) { + *(.ARM.extab*) + } > flash + + .ARM.exidx : ALIGN(4) { + __exidx_start = ABSOLUTE(.); + *(.ARM.exidx*) + __exidx_end = ABSOLUTE(.); + } > flash + + .tdata : { + _stdata = ABSOLUTE(.); + *(.tdata .tdata.* .gnu.linkonce.td.*); + _etdata = ABSOLUTE(.); + } > flash + + .tbss : { + _stbss = ABSOLUTE(.); + *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); + _etbss = ABSOLUTE(.); + } > flash + + _eronly = ABSOLUTE(.); + + /* The STM32F107VC has 64Kb of SRAM beginning at the following address */ + + .data : ALIGN(4) { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > sram AT > flash + + .bss : ALIGN(4) { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + _ebss = ABSOLUTE(.); + } > sram + + /* Stabs debugging sections. */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/stm32f1/shenzhou/scripts/ld.script.dfu b/boards/arm/stm32f1/shenzhou/scripts/ld.script.dfu new file mode 100644 index 0000000000000..02c796db472e9 --- /dev/null +++ b/boards/arm/stm32f1/shenzhou/scripts/ld.script.dfu @@ -0,0 +1,118 @@ +/**************************************************************************** + * boards/arm/stm32f1/shenzhou/scripts/ld.script.dfu + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* The STM32F107VC has 256K of FLASH beginning at address 0x0800:0000 and + * 64K of SRAM beginning at address 0x2000:0000. Here we assume that the + * STMicro DFU bootloader is being used. In that case, the correct load .text + * load address is 0x08003000 (leaving 208K). + */ + +MEMORY +{ + flash (rx) : ORIGIN = 0x08003000, LENGTH = 208K + sram (rwx) : ORIGIN = 0x20000000, LENGTH = 64K +} + +OUTPUT_ARCH(arm) +EXTERN(_vectors) +ENTRY(_stext) +SECTIONS +{ + .text : { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > flash + + .init_section : ALIGN(4) { + _sinit = ABSOLUTE(.); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) + _einit = ABSOLUTE(.); + } > flash + + .ARM.extab : ALIGN(4) { + *(.ARM.extab*) + } > flash + + .ARM.exidx : ALIGN(4) { + __exidx_start = ABSOLUTE(.); + *(.ARM.exidx*) + __exidx_end = ABSOLUTE(.); + } > flash + + .tdata : { + _stdata = ABSOLUTE(.); + *(.tdata .tdata.* .gnu.linkonce.td.*); + _etdata = ABSOLUTE(.); + } > flash + + .tbss : { + _stbss = ABSOLUTE(.); + *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); + _etbss = ABSOLUTE(.); + } > flash + + _eronly = ABSOLUTE(.); + + /* The STM32F107VC has 64Kb of SRAM beginning at the following address */ + + .data : ALIGN(4) { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + _edata = ABSOLUTE(.); + } > sram AT > flash + + .bss : ALIGN(4) { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + _ebss = ABSOLUTE(.); + } > sram + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/stm32f1/shenzhou/src/CMakeLists.txt b/boards/arm/stm32f1/shenzhou/src/CMakeLists.txt new file mode 100644 index 0000000000000..162ec56a04e9e --- /dev/null +++ b/boards/arm/stm32f1/shenzhou/src/CMakeLists.txt @@ -0,0 +1,73 @@ +# ############################################################################## +# boards/arm/stm32f1/shenzhou/src/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(SRCS stm32_boot.c stm32_spi.c stm32_mmcsd.c stm32_chipid.c) + +if(CONFIG_ARCH_LEDS) + list(APPEND SRCS stm32_autoleds.c) +else() + list(APPEND SRCS stm32_userleds.c) +endif() + +if(CONFIG_ARCH_BUTTONS) + list(APPEND SRCS stm32_buttons.c) +endif() + +if(CONFIG_ARCH_RELAYS) + list(APPEND SRCS stm32_relays.c) +endif() + +if(CONFIG_STM32_OTGFS) + list(APPEND SRCS stm32_usb.c) +endif() + +if(CONFIG_MTD_W25) + list(APPEND SRCS stm32_w25.c) +endif() + +if(CONFIG_USBMSC) + list(APPEND SRCS stm32_usbmsc.c) +endif() + +if(CONFIG_STM32_CAN_CHARDRIVER) + list(APPEND SRCS stm32_can.c) +endif() + +if(CONFIG_ADC) + list(APPEND SRCS stm32_adc.c) +endif() + +# NOTE: SSD1289 is not supported on the board + +if(CONFIG_LCD_SSD1289) + list(APPEND SRCS stm32_ssd1289.c) +else() + list(APPEND SRCS stm32_ili93xx.c) +endif() + +if(CONFIG_INPUT_ADS7843E) + list(APPEND SRCS stm32_touchscreen.c) +endif() + +target_sources(board PRIVATE ${SRCS}) + +set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/ld.script") diff --git a/boards/arm/stm32f1/shenzhou/src/Make.defs b/boards/arm/stm32f1/shenzhou/src/Make.defs new file mode 100644 index 0000000000000..262f74241035f --- /dev/null +++ b/boards/arm/stm32f1/shenzhou/src/Make.defs @@ -0,0 +1,75 @@ +############################################################################ +# boards/arm/stm32f1/shenzhou/src/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +CSRCS = stm32_boot.c stm32_spi.c stm32_mmcsd.c stm32_chipid.c + +ifeq ($(CONFIG_ARCH_LEDS),y) +CSRCS += stm32_autoleds.c +else +CSRCS += stm32_userleds.c +endif + +ifeq ($(CONFIG_ARCH_BUTTONS),y) +CSRCS += stm32_buttons.c +endif + +ifeq ($(CONFIG_ARCH_RELAYS),y) +CSRCS += stm32_relays.c +endif + +ifeq ($(CONFIG_STM32_OTGFS),y) +CSRCS += stm32_usb.c +endif + +ifeq ($(CONFIG_MTD_W25),y) +CSRCS += stm32_w25.c +endif + +ifeq ($(CONFIG_USBMSC),y) +CSRCS += stm32_usbmsc.c +endif + +ifeq ($(CONFIG_STM32_CAN_CHARDRIVER),y) +CSRCS += stm32_can.c +endif + +ifeq ($(CONFIG_ADC),y) +CSRCS += stm32_adc.c +endif + +# NOTE: SSD1289 is not supported on the board + +ifeq ($(CONFIG_LCD_SSD1289),y) +CSRCS += stm32_ssd1289.c +else +CSRCS += stm32_ili93xx.c +endif + +ifeq ($(CONFIG_INPUT_ADS7843E),y) +CSRCS += stm32_touchscreen.c +endif + +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/shenzhou/src/shenzhou.h b/boards/arm/stm32f1/shenzhou/src/shenzhou.h similarity index 99% rename from boards/arm/stm32/shenzhou/src/shenzhou.h rename to boards/arm/stm32f1/shenzhou/src/shenzhou.h index 9bf3f825b80ea..089c07fd6f15d 100644 --- a/boards/arm/stm32/shenzhou/src/shenzhou.h +++ b/boards/arm/stm32f1/shenzhou/src/shenzhou.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/shenzhou/src/shenzhou.h + * boards/arm/stm32f1/shenzhou/src/shenzhou.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f1/shenzhou/src/stm32_adc.c b/boards/arm/stm32f1/shenzhou/src/stm32_adc.c new file mode 100644 index 0000000000000..922698d8e7400 --- /dev/null +++ b/boards/arm/stm32f1/shenzhou/src/stm32_adc.c @@ -0,0 +1,166 @@ +/**************************************************************************** + * boards/arm/stm32f1/shenzhou/src/stm32_adc.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32_pwm.h" +#include "shenzhou.h" + +#ifdef CONFIG_ADC + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* Up to 3 ADC interfaces are supported */ + +#if STM32_NADC < 3 +# undef CONFIG_STM32_ADC3 +#endif + +#if STM32_NADC < 2 +# undef CONFIG_STM32_ADC2 +#endif + +#if STM32_NADC < 1 +# undef CONFIG_STM32_ADC1 +#endif + +#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) || defined(CONFIG_STM32_ADC3) +#ifndef CONFIG_STM32_ADC1 +# warning "Channel information only available for ADC1" +#endif + +/* The number of ADC channels in the conversion list */ + +#define ADC1_NCHANNELS 1 + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* Identifying number of each ADC channel. + * The only internal signal for ADC testing is the potentiometer input: + * + * ADC1_IN10(PC0) Potentiometer + * + * External signals are also available on CON5 CN14: + * + * ADC_IN8 (PB0) CON5 CN14 Pin2 + * ADC_IN9 (PB1) CON5 CN14 Pin1 + */ + +#ifdef CONFIG_STM32_ADC1 +static const uint8_t g_chanlist[ADC1_NCHANNELS] = +{ + 10 +}; + +/* {10, 8, 9}; */ + +/* Configurations of pins used by each ADC channel */ + +static const uint32_t g_pinlist[ADC1_NCHANNELS] = +{ + GPIO_ADC12_IN10 +}; + +/* {GPIO_ADC12_IN10, GPIO_ADC12_IN8, GPIO_ADC12_IN9}; */ +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_adc_setup + * + * Description: + * Initialize ADC and register the ADC driver. + * + ****************************************************************************/ + +int stm32_adc_setup(void) +{ +#ifdef CONFIG_STM32_ADC1 + static bool initialized = false; + struct adc_dev_s *adc; + int ret; + int i; + + /* Check if we have already initialized */ + + if (!initialized) + { + /* Configure the pins as analog inputs for the selected channels */ + + for (i = 0; i < ADC1_NCHANNELS; i++) + { + stm32_configgpio(g_pinlist[i]); + } + + /* Call stm32_adcinitialize() to get an instance of the ADC interface */ + + adc = stm32_adcinitialize(1, g_chanlist, ADC1_NCHANNELS); + if (adc == NULL) + { + aerr("ERROR: Failed to get ADC interface\n"); + return -ENODEV; + } + + /* Register the ADC driver at "/dev/adc0" */ + + ret = adc_register("/dev/adc0", adc); + if (ret < 0) + { + aerr("ERROR: adc_register failed: %d\n", ret); + return ret; + } + + /* Now we are initialized */ + + initialized = true; + } + + return OK; +#else + return -ENOSYS; +#endif +} + +#endif /* CONFIG_STM32_ADC1 || CONFIG_STM32_ADC2 || CONFIG_STM32_ADC3 */ +#endif /* CONFIG_ADC */ diff --git a/boards/arm/stm32f1/shenzhou/src/stm32_autoleds.c b/boards/arm/stm32f1/shenzhou/src/stm32_autoleds.c new file mode 100644 index 0000000000000..4ea472253b4dd --- /dev/null +++ b/boards/arm/stm32f1/shenzhou/src/stm32_autoleds.c @@ -0,0 +1,376 @@ +/**************************************************************************** + * boards/arm/stm32f1/shenzhou/src/stm32_autoleds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32.h" +#include "shenzhou.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* The following definitions map the encoded LED setting to GPIO settings */ + +#define SHENZHOU_LED1 (1 << 0) +#define SHENZHOU_LED2 (1 << 1) +#define SHENZHOU_LED3 (1 << 2) +#define SHENZHOU_LED4 (1 << 3) + +#define ON_SETBITS_SHIFT (0) +#define ON_CLRBITS_SHIFT (4) +#define OFF_SETBITS_SHIFT (8) +#define OFF_CLRBITS_SHIFT (12) + +#define ON_BITS(v) ((v) & 0xff) +#define OFF_BITS(v) (((v) >> 8) & 0x0ff) +#define SETBITS(b) ((b) & 0x0f) +#define CLRBITS(b) (((b) >> 4) & 0x0f) + +#define ON_SETBITS(v) (SETBITS(ON_BITS(v)) +#define ON_CLRBITS(v) (CLRBITS(ON_BITS(v)) +#define OFF_SETBITS(v) (SETBITS(OFF_BITS(v)) +#define OFF_CLRBITS(v) (CLRBITS(OFF_BITS(v)) + +#define LED_STARTED_ON_SETBITS ((SHENZHOU_LED1) << ON_SETBITS_SHIFT) +#define LED_STARTED_ON_CLRBITS ((SHENZHOU_LED2|SHENZHOU_LED3|SHENZHOU_LED4) << ON_CLRBITS_SHIFT) +#define LED_STARTED_OFF_SETBITS (0 << OFF_SETBITS_SHIFT) +#define LED_STARTED_OFF_CLRBITS ((SHENZHOU_LED1|SHENZHOU_LED2|SHENZHOU_LED3|SHENZHOU_LED4) << OFF_CLRBITS_SHIFT) + +#define LED_HEAPALLOCATE_ON_SETBITS ((SHENZHOU_LED2) << ON_SETBITS_SHIFT) +#define LED_HEAPALLOCATE_ON_CLRBITS ((SHENZHOU_LED1|SHENZHOU_LED3|SHENZHOU_LED4) << ON_CLRBITS_SHIFT) +#define LED_HEAPALLOCATE_OFF_SETBITS ((SHENZHOU_LED1) << OFF_SETBITS_SHIFT) +#define LED_HEAPALLOCATE_OFF_CLRBITS ((SHENZHOU_LED2|SHENZHOU_LED3|SHENZHOU_LED4) << OFF_CLRBITS_SHIFT) + +#define LED_IRQSENABLED_ON_SETBITS ((SHENZHOU_LED1|SHENZHOU_LED2) << ON_SETBITS_SHIFT) +#define LED_IRQSENABLED_ON_CLRBITS ((SHENZHOU_LED3|SHENZHOU_LED4) << ON_CLRBITS_SHIFT) +#define LED_IRQSENABLED_OFF_SETBITS ((SHENZHOU_LED2) << OFF_SETBITS_SHIFT) +#define LED_IRQSENABLED_OFF_CLRBITS ((SHENZHOU_LED1|SHENZHOU_LED3|SHENZHOU_LED4) << OFF_CLRBITS_SHIFT) + +#define LED_STACKCREATED_ON_SETBITS ((SHENZHOU_LED3) << ON_SETBITS_SHIFT) +#define LED_STACKCREATED_ON_CLRBITS ((SHENZHOU_LED1|SHENZHOU_LED2|SHENZHOU_LED4) << ON_CLRBITS_SHIFT) +#define LED_STACKCREATED_OFF_SETBITS ((SHENZHOU_LED1|SHENZHOU_LED2) << OFF_SETBITS_SHIFT) +#define LED_STACKCREATED_OFF_CLRBITS ((SHENZHOU_LED3|SHENZHOU_LED4) << OFF_CLRBITS_SHIFT) + +#define LED_INIRQ_ON_SETBITS ((SHENZHOU_LED1) << ON_SETBITS_SHIFT) +#define LED_INIRQ_ON_CLRBITS ((0) << ON_CLRBITS_SHIFT) +#define LED_INIRQ_OFF_SETBITS ((0) << OFF_SETBITS_SHIFT) +#define LED_INIRQ_OFF_CLRBITS ((SHENZHOU_LED1) << OFF_CLRBITS_SHIFT) + +#define LED_SIGNAL_ON_SETBITS ((SHENZHOU_LED2) << ON_SETBITS_SHIFT) +#define LED_SIGNAL_ON_CLRBITS ((0) << ON_CLRBITS_SHIFT) +#define LED_SIGNAL_OFF_SETBITS ((0) << OFF_SETBITS_SHIFT) +#define LED_SIGNAL_OFF_CLRBITS ((SHENZHOU_LED2) << OFF_CLRBITS_SHIFT) + +#define LED_ASSERTION_ON_SETBITS ((SHENZHOU_LED4) << ON_SETBITS_SHIFT) +#define LED_ASSERTION_ON_CLRBITS ((0) << ON_CLRBITS_SHIFT) +#define LED_ASSERTION_OFF_SETBITS ((0) << OFF_SETBITS_SHIFT) +#define LED_ASSERTION_OFF_CLRBITS ((SHENZHOU_LED4) << OFF_CLRBITS_SHIFT) + +#define LED_PANIC_ON_SETBITS ((SHENZHOU_LED4) << ON_SETBITS_SHIFT) +#define LED_PANIC_ON_CLRBITS ((0) << ON_CLRBITS_SHIFT) +#define LED_PANIC_OFF_SETBITS ((0) << OFF_SETBITS_SHIFT) +#define LED_PANIC_OFF_CLRBITS ((SHENZHOU_LED4) << OFF_CLRBITS_SHIFT) + +/**************************************************************************** + * Private Function Protototypes + ****************************************************************************/ + +/* LED State Controls */ + +static inline void led_clrbits(unsigned int clrbits); +static inline void led_setbits(unsigned int setbits); +static void led_setonoff(unsigned int bits); + +/* LED Power Management */ + +#ifdef CONFIG_PM +static void led_pm_notify(struct pm_callback_s *cb, int domain, + enum pm_state_e pmstate); +static int led_pm_prepare(struct pm_callback_s *cb, int domain, + enum pm_state_e pmstate); +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static const uint16_t g_ledbits[8] = +{ + (LED_STARTED_ON_SETBITS | LED_STARTED_ON_CLRBITS | + LED_STARTED_OFF_SETBITS | LED_STARTED_OFF_CLRBITS), + + (LED_HEAPALLOCATE_ON_SETBITS | LED_HEAPALLOCATE_ON_CLRBITS | + LED_HEAPALLOCATE_OFF_SETBITS | LED_HEAPALLOCATE_OFF_CLRBITS), + + (LED_IRQSENABLED_ON_SETBITS | LED_IRQSENABLED_ON_CLRBITS | + LED_IRQSENABLED_OFF_SETBITS | LED_IRQSENABLED_OFF_CLRBITS), + + (LED_STACKCREATED_ON_SETBITS | LED_STACKCREATED_ON_CLRBITS | + LED_STACKCREATED_OFF_SETBITS | LED_STACKCREATED_OFF_CLRBITS), + + (LED_INIRQ_ON_SETBITS | LED_INIRQ_ON_CLRBITS | + LED_INIRQ_OFF_SETBITS | LED_INIRQ_OFF_CLRBITS), + + (LED_SIGNAL_ON_SETBITS | LED_SIGNAL_ON_CLRBITS | + LED_SIGNAL_OFF_SETBITS | LED_SIGNAL_OFF_CLRBITS), + + (LED_ASSERTION_ON_SETBITS | LED_ASSERTION_ON_CLRBITS | + LED_ASSERTION_OFF_SETBITS | LED_ASSERTION_OFF_CLRBITS), + + (LED_PANIC_ON_SETBITS | LED_PANIC_ON_CLRBITS | + LED_PANIC_OFF_SETBITS | LED_PANIC_OFF_CLRBITS) +}; + +#ifdef CONFIG_PM +static struct pm_callback_s g_ledscb = +{ + .notify = led_pm_notify, + .prepare = led_pm_prepare, +}; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: led_clrbits + * + * Description: + * Clear all LEDs to the bit encoded state + * + ****************************************************************************/ + +static inline void led_clrbits(unsigned int clrbits) +{ + /* All LEDs are pulled up and, hence, active low */ + + if ((clrbits & SHENZHOU_LED1) != 0) + { + stm32_gpiowrite(GPIO_LED1, true); + } + + if ((clrbits & SHENZHOU_LED2) != 0) + { + stm32_gpiowrite(GPIO_LED2, true); + } + + if ((clrbits & SHENZHOU_LED3) != 0) + { + stm32_gpiowrite(GPIO_LED3, true); + } + + if ((clrbits & SHENZHOU_LED4) != 0) + { + stm32_gpiowrite(GPIO_LED4, true); + } +} + +/**************************************************************************** + * Name: led_setbits + * + * Description: + * Set all LEDs to the bit encoded state + * + ****************************************************************************/ + +static inline void led_setbits(unsigned int setbits) +{ + /* All LEDs are pulled up and, hence, active low */ + + if ((setbits & SHENZHOU_LED1) != 0) + { + stm32_gpiowrite(GPIO_LED1, false); + } + + if ((setbits & SHENZHOU_LED2) != 0) + { + stm32_gpiowrite(GPIO_LED2, false); + } + + if ((setbits & SHENZHOU_LED3) != 0) + { + stm32_gpiowrite(GPIO_LED3, false); + } + + if ((setbits & SHENZHOU_LED4) != 0) + { + stm32_gpiowrite(GPIO_LED4, false); + } +} + +/**************************************************************************** + * Name: led_setonoff + * + * Description: + * Set/clear all LEDs to the bit encoded state + * + ****************************************************************************/ + +static void led_setonoff(unsigned int bits) +{ + led_clrbits(CLRBITS(bits)); + led_setbits(SETBITS(bits)); +} + +/**************************************************************************** + * Name: led_pm_notify + * + * Description: + * Notify the driver of new power state. This callback is called after + * all drivers have had the opportunity to prepare for the new power state. + * + ****************************************************************************/ + +#ifdef CONFIG_PM +static void led_pm_notify(struct pm_callback_s *cb, int domain, + enum pm_state_e pmstate) +{ + switch (pmstate) + { + case PM_NORMAL: + { + /* Restore normal LEDs operation */ + } + break; + + case PM_IDLE: + { + /* Entering IDLE mode - Turn leds off */ + } + break; + + case PM_STANDBY: + { + /* Entering STANDBY mode - Logic for PM_STANDBY goes here */ + } + break; + + case PM_SLEEP: + { + /* Entering SLEEP mode - Logic for PM_SLEEP goes here */ + } + break; + + default: + { + /* Should not get here */ + } + break; + } +} +#endif + +/**************************************************************************** + * Name: led_pm_prepare + * + * Description: + * Request the driver to prepare for a new power state. This is a warning + * that the system is about to enter into a new power state. The driver + * should begin whatever operations that may be required to enter power + * state. The driver may abort the state change mode by returning a + * non-zero value from the callback function. + * + ****************************************************************************/ + +#ifdef CONFIG_PM +static int led_pm_prepare(struct pm_callback_s *cb, int domain, + enum pm_state_e pmstate) +{ + /* No preparation to change power modes is required by the LEDs driver. + * We always accept the state change by returning OK. + */ + + return OK; +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_autoled_initialize + ****************************************************************************/ + +#ifdef CONFIG_ARCH_LEDS +void board_autoled_initialize(void) +{ + /* Configure LED1-4 GPIOs for output */ + + stm32_configgpio(GPIO_LED1); + stm32_configgpio(GPIO_LED2); + stm32_configgpio(GPIO_LED3); + stm32_configgpio(GPIO_LED4); +} + +/**************************************************************************** + * Name: board_autoled_on + ****************************************************************************/ + +void board_autoled_on(int led) +{ + led_setonoff(ON_BITS(g_ledbits[led])); +} + +/**************************************************************************** + * Name: board_autoled_off + ****************************************************************************/ + +void board_autoled_off(int led) +{ + led_setonoff(OFF_BITS(g_ledbits[led])); +} + +/**************************************************************************** + * Name: up_ledpminitialize + ****************************************************************************/ + +#ifdef CONFIG_PM +void up_ledpminitialize(void) +{ + /* Register to receive power management callbacks */ + + int ret = pm_register(&g_ledscb); + if (ret != OK) + { + board_autoled_on(LED_ASSERTION); + } +} +#endif /* CONFIG_PM */ + +#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32f1/shenzhou/src/stm32_boot.c b/boards/arm/stm32f1/shenzhou/src/stm32_boot.c new file mode 100644 index 0000000000000..c2e3492aaa343 --- /dev/null +++ b/boards/arm/stm32f1/shenzhou/src/stm32_boot.c @@ -0,0 +1,270 @@ +/**************************************************************************** + * boards/arm/stm32f1/shenzhou/src/stm32_boot.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include +#include +#include +#include + +#include +#include + +#include "arm_internal.h" +#include "stm32.h" +#include "shenzhou.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* Assume that we support everything until convinced otherwise */ + +#define HAVE_MMCSD 1 +#define HAVE_USBDEV 1 +#define HAVE_USBHOST 1 +#define HAVE_W25 1 + +/* Configuration ************************************************************/ + +/* SPI1 connects to the SD CARD (and to the SPI FLASH) */ + +#define STM32_MMCSDSPIPORTNO 1 /* SPI1 */ +#define STM32_MMCSDSLOTNO 0 /* Only one slot */ + +#ifndef CONFIG_STM32_SPI1 +# undef HAVE_MMCSD +#endif + +/* Can't support MMC/SD features if mountpoints are disabled */ + +#ifdef CONFIG_DISABLE_MOUNTPOINT +# undef HAVE_MMCSD +#endif + +/* Default MMC/SD minor number */ + +#ifdef HAVE_MMCSD +# ifndef CONFIG_NSH_MMCSDMINOR +# define CONFIG_NSH_MMCSDMINOR 0 +# endif + +/* Default MMC/SD SLOT number */ + +# if defined(CONFIG_NSH_MMCSDSLOTNO) && CONFIG_NSH_MMCSDSLOTNO != STM32_MMCSDSLOTNO +# error "Only one MMC/SD slot: Slot 0" +# endif + +/* Verify configured SPI port number */ + +# if defined(CONFIG_NSH_MMCSDSPIPORTNO) && CONFIG_NSH_MMCSDSPIPORTNO != STM32_MMCSDSPIPORTNO +# error "Only one MMC/SD port: SPI1" +# endif +#endif + +/* Can't support the W25 device if it SPI1 or W25 support is not enabled */ + +#if !defined(CONFIG_STM32_SPI1) || !defined(CONFIG_MTD_W25) +# undef HAVE_W25 +#endif + +/* Can't support W25 features if mountpoints are disabled */ + +#ifdef CONFIG_DISABLE_MOUNTPOINT +# undef HAVE_W25 +#endif + +/* Default W25 minor number */ + +#if defined(HAVE_W25) && !defined(CONFIG_NSH_W25MINOR) +# define CONFIG_NSH_W25MINOR 0 +#endif + +/* Can't support USB host or device features if USB OTG FS is not enabled */ + +#ifndef CONFIG_STM32_OTGFS +# undef HAVE_USBDEV +# undef HAVE_USBHOST +#endif + +/* Can't support USB device is USB device is not enabled */ + +#ifndef CONFIG_USBDEV +# undef HAVE_USBDEV +#endif + +/* Can't support USB host is USB host is not enabled */ + +#ifndef CONFIG_USBHOST +# undef HAVE_USBHOST +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_boardinitialize + * + * Description: + * All STM32 architectures must provide the following entry point. + * This entry point is called early in the initialization -- after all + * memory has been configured and mapped but before any devices have been + * initialized. + * + ****************************************************************************/ + +void stm32_boardinitialize(void) +{ + /* Configure SPI chip selects if 1) SPI is not disabled, and 2) the weak + * function stm32_spidev_initialize() has been brought into the link. + */ + +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI3) + if (stm32_spidev_initialize) + { + stm32_spidev_initialize(); + } +#endif + + /* Initialize USB is 1) USBDEV is selected, 2) the USB controller is not + * disabled, and 3) the weak function stm32_usbinitialize() has been + * brought into the build. + */ + +#if defined(CONFIG_USBDEV) && defined(CONFIG_STM32_USB) + if (stm32_usbinitialize) + { + stm32_usbinitialize(); + } +#endif + + /* Configure on-board LEDs if LED support has been selected. */ + +#ifdef CONFIG_ARCH_LEDS + board_autoled_initialize(); +#endif +} + +/**************************************************************************** + * Name: board_late_initialize + * + * Description: + * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_late_initialize(). board_late_initialize() will + * be called immediately after up_initialize() is called and just before + * the initial application is started. This additional initialization + * phase may be used, for example, to initialize board-specific device + * drivers. + * + ****************************************************************************/ + +#ifdef CONFIG_BOARD_LATE_INITIALIZE +void board_late_initialize(void) +{ + int ret; + +#ifdef HAVE_W25 + /* Initialize and register the W25 FLASH file system. */ + + ret = stm32_w25initialize(CONFIG_NSH_W25MINOR); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to initialize W25 minor %d: %d\n", + CONFIG_NSH_W25MINOR, ret); + return; + } +#endif + +#ifdef HAVE_MMCSD + /* Initialize the SPI-based MMC/SD slot */ + + ret = stm32_sdinitialize(CONFIG_NSH_MMCSDMINOR); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to initialize MMC/SD slot %d: %d\n", + STM32_MMCSDSLOTNO, ret); + return; + } +#endif + +#ifdef HAVE_USBHOST + /* Initialize USB host operation. + * stm32_usbhost_initialize() starts a thread will monitor + * for USB connection and disconnection events. + */ + + ret = stm32_usbhost_initialize(); + if (ret != OK) + { + syslog(LOG_ERR, "ERROR: Failed to initialize USB host: %d\n", ret); + return; + } +#endif + +#ifdef CONFIG_INPUT_ADS7843E + /* Initialize the touchscreen */ + + ret = stm32_tsc_setup(0); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_tsc_setup failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_ADC + /* Initialize ADC and register the ADC driver. */ + + ret = stm32_adc_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_adc_setup failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_STM32_CAN_CHARDRIVER + /* Initialize CAN and register the CAN driver. */ + + ret = stm32_can_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_can_setup failed: %d\n", ret); + } +#endif + + UNUSED(ret); +} +#endif diff --git a/boards/arm/stm32f1/shenzhou/src/stm32_buttons.c b/boards/arm/stm32f1/shenzhou/src/stm32_buttons.c new file mode 100644 index 0000000000000..15dcb93fae35f --- /dev/null +++ b/boards/arm/stm32f1/shenzhou/src/stm32_buttons.c @@ -0,0 +1,157 @@ +/**************************************************************************** + * boards/arm/stm32f1/shenzhou/src/stm32_buttons.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include +#include + +#include "shenzhou.h" + +#ifdef CONFIG_ARCH_BUTTONS + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* Pin configuration for each Shenzhou button. This array is indexed by + * the BUTTON_* definitions in board.h + */ + +static const uint32_t g_buttons[NUM_BUTTONS] = +{ + GPIO_BTN_USERKEY2, GPIO_BTN_USERKEY, GPIO_BTN_TAMPER, GPIO_BTN_WAKEUP +}; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_button_initialize + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. + * + ****************************************************************************/ + +uint32_t board_button_initialize(void) +{ + int i; + + /* Configure the GPIO pins as inputs. NOTE that EXTI interrupts are + * configured for some pins but NOT used in this file + */ + + for (i = 0; i < NUM_BUTTONS; i++) + { + stm32_configgpio(g_buttons[i]); + } + + return NUM_BUTTONS; +} + +/**************************************************************************** + * Name: board_buttons + ****************************************************************************/ + +uint32_t board_buttons(void) +{ + uint32_t ret = 0; + int i; + + /* Check that state of each key */ + + for (i = 0; i < NUM_BUTTONS; i++) + { + /* A LOW value means that the key is pressed for most keys. + * The exception is the WAKEUP button. + */ + + bool released = stm32_gpioread(g_buttons[i]); + if (i == BUTTON_WAKEUP) + { + released = !released; + } + + /* Accumulate the set of depressed (not released) keys */ + + if (!released) + { + ret |= (1 << i); + } + } + + return ret; +} + +/**************************************************************************** + * Button support. + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. + * + * After board_button_initialize() has been called, board_buttons() may be + * called to collect the state of all buttons. board_buttons() returns an + * 32-bit bit set with each bit associated with a button. See the + * BUTTON_*_BIT and JOYSTICK_*_BIT definitions in board.h for the meaning + * of each bit. + * + * board_button_irq() may be called to register an interrupt handler that + * will be called when a button is depressed or released. The ID value is a + * button enumeration value that uniquely identifies a button resource. See + * the BUTTON_* and JOYSTICK_* definitions in board.h for the meaning of + * enumeration value. + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_IRQBUTTONS +int board_button_irq(int id, xcpt_t irqhandler, void *arg) +{ + int ret = -EINVAL; + + /* The following should be atomic */ + + if (id >= MIN_IRQBUTTON && id <= MAX_IRQBUTTON) + { + ret = stm32_gpiosetevent(g_buttons[id], true, true, true, + irqhandler, arg); + } + + return ret; +} +#endif +#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/stm32f1/shenzhou/src/stm32_can.c b/boards/arm/stm32f1/shenzhou/src/stm32_can.c new file mode 100644 index 0000000000000..5a8f603b946e7 --- /dev/null +++ b/boards/arm/stm32f1/shenzhou/src/stm32_can.c @@ -0,0 +1,104 @@ +/**************************************************************************** + * boards/arm/stm32f1/shenzhou/src/stm32_can.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32.h" +#include "stm32_can.h" +#include "shenzhou.h" + +#ifdef CONFIG_CAN + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* The STM32F107VC supports CAN1 and CAN2 */ + +#if defined(CONFIG_STM32_CAN1) && defined(CONFIG_STM32_CAN2) +# warning "Both CAN1 and CAN2 are enabled. Only CAN1 is connected." +# undef CONFIG_STM32_CAN2 +#endif + +#ifdef CONFIG_STM32_CAN1 +# define CAN_PORT 1 +#else +# define CAN_PORT 2 +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_can_setup + * + * Description: + * Initialize CAN and register the CAN device + * + ****************************************************************************/ + +int stm32_can_setup(void) +{ +#if defined(CONFIG_STM32_CAN1) || defined(CONFIG_STM32_CAN2) + struct can_dev_s *can; + int ret; + + /* Call stm32_caninitialize() to get an instance of the CAN interface */ + + can = stm32_caninitialize(CAN_PORT); + if (can == NULL) + { + canerr("ERROR: Failed to get CAN interface\n"); + return -ENODEV; + } + + /* Register the CAN driver at "/dev/can0" */ + + ret = can_register("/dev/can0", can); + if (ret < 0) + { + canerr("ERROR: can_register failed: %d\n", ret); + return ret; + } + + return OK; +#else + return -ENODEV; +#endif +} + +#endif /* CONFIG_CAN */ diff --git a/boards/arm/stm32f1/shenzhou/src/stm32_chipid.c b/boards/arm/stm32f1/shenzhou/src/stm32_chipid.c new file mode 100644 index 0000000000000..8ae5a0fd1813d --- /dev/null +++ b/boards/arm/stm32f1/shenzhou/src/stm32_chipid.c @@ -0,0 +1,79 @@ +/**************************************************************************** + * boards/arm/stm32f1/shenzhou/src/stm32_chipid.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include + +#include "arm_internal.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +const char *stm32_getchipid(void) +{ + static char cpuid[12]; + int i; + + for (i = 0; i < 12; i++) + { + cpuid[i] = getreg8(0x1ffff7e8 + i); + } + + return cpuid; +} + +const char *stm32_getchipid_string(void) +{ + static char cpuid[27]; + int c; + int i; + + for (i = 0, c = 0; i < 12; i++) + { + snprintf(&cpuid[c], sizeof(cpuid) - c, + "%02X", getreg8(0x1ffff7e8 + 11 - i)); + c += 2; + if (i % 4 == 3) + { + cpuid[c++] = '-'; + } + } + + cpuid[26] = '\0'; + return cpuid; +} diff --git a/boards/arm/stm32/shenzhou/src/stm32_ili93xx.c b/boards/arm/stm32f1/shenzhou/src/stm32_ili93xx.c similarity index 99% rename from boards/arm/stm32/shenzhou/src/stm32_ili93xx.c rename to boards/arm/stm32f1/shenzhou/src/stm32_ili93xx.c index eb190ae7884a3..5610e1946a196 100644 --- a/boards/arm/stm32/shenzhou/src/stm32_ili93xx.c +++ b/boards/arm/stm32f1/shenzhou/src/stm32_ili93xx.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/shenzhou/src/stm32_ili93xx.c + * boards/arm/stm32f1/shenzhou/src/stm32_ili93xx.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f1/shenzhou/src/stm32_mmcsd.c b/boards/arm/stm32f1/shenzhou/src/stm32_mmcsd.c new file mode 100644 index 0000000000000..d9e7cbfa97dac --- /dev/null +++ b/boards/arm/stm32f1/shenzhou/src/stm32_mmcsd.c @@ -0,0 +1,116 @@ +/**************************************************************************** + * boards/arm/stm32f1/shenzhou/src/stm32_mmcsd.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "stm32_spi.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* SPI1 connects to the SD CARD (and to the SPI FLASH) */ + +#define HAVE_MMCSD 1 /* Assume that we have SD support */ +#define STM32_MMCSDSPIPORTNO 1 /* Port is SPI1 */ +#define STM32_MMCSDSLOTNO 0 /* There is only one slot */ + +#ifndef CONFIG_STM32_SPI1 +# undef HAVE_MMCSD +#endif + +/* Can't support MMC/SD features if MMC/SD driver support is not selected */ + +#ifndef CONFIG_MMCSD +# undef HAVE_MMCSD +#endif + +/* Can't support MMC/SD features if mountpoints are disabled */ + +#ifdef CONFIG_DISABLE_MOUNTPOINT +# undef HAVE_MMCSD +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_sdinitialize + * + * Description: + * Initialize the SPI-based SD card. Requires CONFIG_DISABLE_MOUNTPOINT=n + * and CONFIG_STM32_SPI1=y + * + ****************************************************************************/ + +int stm32_sdinitialize(int minor) +{ +#ifdef HAVE_MMCSD + struct spi_dev_s *spi; + int ret; + + /* Get the SPI port */ + + finfo("Initializing SPI port %d\n", STM32_MMCSDSPIPORTNO); + + spi = stm32_spibus_initialize(STM32_MMCSDSPIPORTNO); + if (!spi) + { + ferr("ERROR: Failed to initialize SPI port %d\n", + STM32_MMCSDSPIPORTNO); + return -ENODEV; + } + + finfo("Successfully initialized SPI port %d\n", STM32_MMCSDSPIPORTNO); + + /* Bind the SPI port to the slot */ + + finfo("Binding SPI port %d to MMC/SD slot %d\n", + STM32_MMCSDSPIPORTNO, STM32_MMCSDSLOTNO); + + ret = mmcsd_spislotinitialize(minor, STM32_MMCSDSLOTNO, spi); + if (ret < 0) + { + ferr("ERROR: Failed to bind SPI port %d to MMC/SD slot %d: %d\n", + STM32_MMCSDSPIPORTNO, STM32_MMCSDSLOTNO, ret); + return ret; + } + + finfo("Successfully bound SPI port %d to MMC/SD slot %d\n", + STM32_MMCSDSPIPORTNO, STM32_MMCSDSLOTNO); +#endif + return OK; +} diff --git a/boards/arm/stm32f1/shenzhou/src/stm32_relays.c b/boards/arm/stm32f1/shenzhou/src/stm32_relays.c new file mode 100644 index 0000000000000..6c7fd95eeaa09 --- /dev/null +++ b/boards/arm/stm32f1/shenzhou/src/stm32_relays.c @@ -0,0 +1,274 @@ +/**************************************************************************** + * boards/arm/stm32f1/shenzhou/src/stm32_relays.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include +#include + +#include "shenzhou.h" + +#ifdef CONFIG_ARCH_RELAYS + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define RELAYS_MIN_RESET_TIME 5 +#define RELAYS_RESET_MTIME 5 +#define RELAYS_POWER_MTIME 50 + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static uint32_t g_relays_stat = 0; +static bool g_relays_init = false; + +static const uint16_t g_relays[NUM_RELAYS] = +{ + GPIO_RELAYS_R00 +#ifdef GPIO_RELAYS_R01 + , GPIO_RELAYS_R01 +#endif +#ifdef GPIO_RELAYS_R02 + , GPIO_RELAYS_R02 +#endif +#ifdef GPIO_RELAYS_R03 + , GPIO_RELAYS_R03 +#endif +#ifdef GPIO_RELAYS_R04 + , GPIO_RELAYS_R04 +#endif +#ifdef GPIO_RELAYS_R05 + , GPIO_RELAYS_R05 +#endif +#ifdef GPIO_RELAYS_R06 + , GPIO_RELAYS_R06 +#endif +#ifdef GPIO_RELAYS_R07 + , GPIO_RELAYS_R07 +#endif +#ifdef GPIO_RELAYS_R08 + , GPIO_RELAYS_R08 +#endif +#ifdef GPIO_RELAYS_R09 + , GPIO_RELAYS_R09 +#endif +#ifdef GPIO_RELAYS_R10 + , GPIO_RELAYS_R10 +#endif +#ifdef GPIO_RELAYS_R11 + , GPIO_RELAYS_R11 +#endif +#ifdef GPIO_RELAYS_R12 + , GPIO_RELAYS_R12 +#endif +#ifdef GPIO_RELAYS_R13 + , GPIO_RELAYS_R13 +#endif +#ifdef GPIO_RELAYS_R14 + , GPIO_RELAYS_R14 +#endif +#ifdef GPIO_RELAYS_R15 + , GPIO_RELAYS_R15 +#endif +#ifdef GPIO_RELAYS_R16 + , GPIO_RELAYS_R16 +#endif +#ifdef GPIO_RELAYS_R17 + , GPIO_RELAYS_R17 +#endif +#ifdef GPIO_RELAYS_R18 + , GPIO_RELAYS_R18 +#endif +#ifdef GPIO_RELAYS_R19 + , GPIO_RELAYS_R19 +#endif +#ifdef GPIO_RELAYS_R20 + , GPIO_RELAYS_R20 +#endif +#ifdef GPIO_RELAYS_R21 + , GPIO_RELAYS_R21 +#endif +#ifdef GPIO_RELAYS_R22 + , GPIO_RELAYS_R22 +#endif +#ifdef GPIO_RELAYS_R23 + , GPIO_RELAYS_R23 +#endif +#ifdef GPIO_RELAYS_R24 + , GPIO_RELAYS_R24 +#endif +#ifdef GPIO_RELAYS_R25 + , GPIO_RELAYS_R25 +#endif +#ifdef GPIO_RELAYS_R26 + , GPIO_RELAYS_R26 +#endif +#ifdef GPIO_RELAYS_R27 + , GPIO_RELAYS_R27 +#endif +#ifdef GPIO_RELAYS_R28 + , GPIO_RELAYS_R28 +#endif +#ifdef GPIO_RELAYS_R29 + , GPIO_RELAYS_R29 +#endif +#ifdef GPIO_RELAYS_R30 + , GPIO_RELAYS_R30 +#endif +#ifdef GPIO_RELAYS_R31 + , GPIO_RELAYS_R31 +#endif +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +void up_relaysinit(void) +{ + int i; + + if (g_relays_init) + { + return; + } + + /* Configure the GPIO pins as inputs. NOTE that EXTI interrupts are + * configured for some pins but NOT used in this file + */ + + for (i = 0; i < NUM_RELAYS; i++) + { + stm32_configgpio(g_relays[i]); + stm32_gpiowrite(g_relays[i], false); + } + + g_relays_init = true; +} + +void relays_setstat(int relays, bool stat) +{ + if ((unsigned)relays < NUM_RELAYS) + { + stm32_gpiowrite(g_relays[relays], stat); + if (!stat) + { + g_relays_stat &= ~(1 << relays); + } + else + { + g_relays_stat |= (1 << relays); + } + } +} + +bool relays_getstat(int relays) +{ + if ((unsigned)relays < NUM_RELAYS) + { + return (g_relays_stat & (1 << relays)) != 0; + } + + return false; +} + +void relays_setstats(uint32_t relays_stat) +{ + int i; + + for (i = 0; i < NUM_RELAYS; i++) + { + relays_setstat(i, (relays_stat & (1 << i)) != 0); + } +} + +uint32_t relays_getstats(void) +{ + return (uint32_t)g_relays_stat; +} + +void relays_onoff(int relays, uint32_t mdelay) +{ + if ((unsigned)relays < NUM_RELAYS) + { + if (mdelay > 0) + { + if (relays_getstat(relays)) + { + relays_setstat(relays, false); + nxsched_usleep(RELAYS_MIN_RESET_TIME * 1000 * 1000); + } + + relays_setstat(relays, true); + nxsched_usleep(mdelay * 100 * 1000); + relays_setstat(relays, false); + } + } +} + +void relays_onoffs(uint32_t relays_stat, uint32_t mdelay) +{ + int i; + + for (i = 0; i < NUM_RELAYS; i++) + { + relays_onoff(i, mdelay); + } +} + +void relays_resetmode(int relays) +{ + relays_onoff(relays, RELAYS_RESET_MTIME); +} + +void relays_powermode(int relays) +{ + relays_onoff(relays, RELAYS_POWER_MTIME); +} + +void relays_resetmodes(uint32_t relays_stat) +{ + relays_onoffs(relays_stat, RELAYS_RESET_MTIME); +} + +void relays_powermodes(uint32_t relays_stat) +{ + relays_onoffs(relays_stat, RELAYS_POWER_MTIME); +} + +#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/stm32f1/shenzhou/src/stm32_spi.c b/boards/arm/stm32f1/shenzhou/src/stm32_spi.c new file mode 100644 index 0000000000000..d77612c7eb6f1 --- /dev/null +++ b/boards/arm/stm32f1/shenzhou/src/stm32_spi.c @@ -0,0 +1,189 @@ +/**************************************************************************** + * boards/arm/stm32f1/shenzhou/src/stm32_spi.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "arm_internal.h" +#include "chip.h" +#include "stm32.h" +#include "shenzhou.h" + +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI3) + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_spidev_initialize + * + * Description: + * Called to configure SPI chip select GPIO pins for the Shenzhou board. + * + ****************************************************************************/ + +void weak_function stm32_spidev_initialize(void) +{ + /* NOTE: Clocking for SPI1 and/or SPI3 was already provided in stm32_rcc.c. + * Configurations of SPI pins is performed in stm32_spi.c. + * Here, we only initialize chip select pins unique to the board + * architecture. + */ + + /* SPI1 connects to the SD CARD and to the SPI FLASH */ + +#ifdef CONFIG_STM32_SPI1 + stm32_configgpio(GPIO_SD_CS); /* SD card chip select */ + stm32_configgpio(GPIO_SD_CD); /* SD card detect */ + stm32_configgpio(GPIO_FLASH_CS); /* FLASH chip select */ +#endif + + /* SPI3 connects to TFT LCD module and the RF24L01 2.4G wireless module */ + +#ifdef CONFIG_STM32_SPI3 + stm32_configgpio(GPIO_TP_CS); /* Touchscreen chip select */ + stm32_configgpio(GPIO_LCDDF_CS); /* Data flash chip select (on the LCD module) */ + stm32_configgpio(GPIO_LCDSD_CS); /* SD chip select (on the LCD module) */ + stm32_configgpio(GPIO_WIRELESS_CS); /* Wireless chip select */ +#endif +} + +/**************************************************************************** + * Name: stm32_spi1/2/3select and stm32_spi1/2/3status + * + * Description: + * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status + * must be provided by board-specific logic. They are implementations of + * the select and status methods of the SPI interface defined by struct + * spi_ops_s (see include/nuttx/spi/spi.h). + * All other methods (including stm32_spibus_initialize()) are provided by + * common STM32 logic. + * To use this common SPI logic on your board: + * + * 1. Provide logic in stm32_boardinitialize() to configure SPI chip select + * pins. + * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() functions + * in your board-specific logic. These functions will perform chip + * selection and status operations using GPIOs in the way your board is + * configured. + * 3. Add a calls to stm32_spibus_initialize() in your low level + * application initialization logic + * 4. The handle returned by stm32_spibus_initialize() may then be used to + * bind the SPI driver to higher level logic (e.g., calling + * mmcsd_spislotinitialize(), for example, will bind the SPI driver to + * the SPI MMC/SD driver). + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_SPI1 +void stm32_spi1select(struct spi_dev_s *dev, + uint32_t devid, bool selected) +{ + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); + + /* SPI1 connects to the SD CARD and to the SPI FLASH */ + + if (devid == SPIDEV_MMCSD(0)) + { + /* Set the GPIO low to select and high to de-select */ + + stm32_gpiowrite(GPIO_SD_CS, !selected); + } + else if (devid == SPIDEV_FLASH(0)) + { + /* Set the GPIO low to select and high to de-select */ + + stm32_gpiowrite(GPIO_FLASH_CS, !selected); + } +} + +uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) +{ + /* The card detect pin is pulled up so that we detect the presence of a + * card by see a low value on the input pin. + */ + + if (stm32_gpioread(GPIO_SD_CD)) + { + return 0; + } + + return SPI_STATUS_PRESENT; +} +#endif + +#ifdef CONFIG_STM32_SPI3 +void stm32_spi3select(struct spi_dev_s *dev, + uint32_t devid, bool selected) +{ + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); + + /* SPI3 connects to TFT LCD (for touchscreen and SD) and the RF24L01 2.4G + * wireless module. + */ + + if (devid == SPIDEV_TOUCHSCREEN(0)) + { + /* Set the GPIO low to select and high to de-select */ + + stm32_gpiowrite(GPIO_TP_CS, !selected); + } + else if (devid == SPIDEV_MMCSD(0)) + { + /* Set the GPIO low to select and high to de-select */ + + stm32_gpiowrite(GPIO_LCDDF_CS, !selected); + } + else if (devid == SPIDEV_FLASH(0)) + { + /* Set the GPIO low to select and high to de-select */ + + stm32_gpiowrite(GPIO_LCDSD_CS, !selected); + } + else if (devid == SPIDEV_WIRELESS(0)) + { + /* Set the GPIO low to select and high to de-select */ + + stm32_gpiowrite(GPIO_WIRELESS_CS, !selected); + } +} + +uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} +#endif + +#endif /* CONFIG_STM32_SPI1 || CONFIG_STM32_SPI3 */ diff --git a/boards/arm/stm32f1/shenzhou/src/stm32_ssd1289.c b/boards/arm/stm32f1/shenzhou/src/stm32_ssd1289.c new file mode 100644 index 0000000000000..d4bbe679b1b94 --- /dev/null +++ b/boards/arm/stm32f1/shenzhou/src/stm32_ssd1289.c @@ -0,0 +1,597 @@ +/**************************************************************************** + * boards/arm/stm32f1/shenzhou/src/stm32_ssd1289.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include + +#include "arm_internal.h" +#include "stm32.h" +#include "shenzhou.h" + +#ifdef CONFIG_LCD_SSD1289 + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +#undef CONFIG_LCD_FASTCONFIG +#define CONFIG_LCD_FASTCONFIG 1 + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/* This structure describes the state of this driver */ + +struct stm32_lower_s +{ + struct ssd1289_lcd_s dev; /* This is externally visible the driver state */ + struct lcd_dev_s *drvr; /* The saved instance of the LCD driver */ + bool output; /* True: Configured for output */ +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/* Helpers */ + +#ifdef CONFIG_LCD_REGDEBUG +static void stm32_lcdshow(struct stm32_lower_s *priv, + const char *msg); +#else +# define stm32_lcdshow(p,m) +#endif + +static void stm32_wrdata(struct stm32_lower_s *priv, uint16_t data); +#ifndef CONFIG_LCD_NOGETRUN +static inline uint16_t stm32_rddata(struct stm32_lower_s *priv); +#endif + +/* Low Level LCD access */ + +static void stm32_select(struct ssd1289_lcd_s *dev); +static void stm32_deselect(struct ssd1289_lcd_s *dev); +static void stm32_index(struct ssd1289_lcd_s *dev, uint8_t index); +#ifndef CONFIG_LCD_NOGETRUN +static uint16_t stm32_read(struct ssd1289_lcd_s *dev); +#endif +static void stm32_write(struct ssd1289_lcd_s *dev, uint16_t data); +static void stm32_backlight(struct ssd1289_lcd_s *dev, int power); + +/* Initialization */ + +#ifndef CONFIG_LCD_NOGETRUN +static void stm32_lcdinput(struct stm32_lower_s *priv); +#endif +static void stm32_lcdoutput(struct stm32_lower_s *priv); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* TFT LCD + * + * -- ---- -------------- --------------------------------------------------- + * PN NAME SIGNAL NOTES + * -- ---- -------------- --------------------------------------------------- + * 37 PB2 DATA_LE To TFT LCD (CN13, ping 28) + * 96 PB9 F_CS To both the TFT LCD (CN13, pin 30) and + * to the W25X16 SPI FLASH + * 34 PC5 TP_INT JP6. To TFT LCD (CN13) module (CN13, pin 26) + * 65 PC8 LCD_CS Active low: Pulled high (CN13, pin 19) + * 66 PC9 TP_CS Active low: Pulled high (CN13, pin 31) + * 78 PC10 SPI3_SCK To TFT LCD (CN13, pin 29) + * 79 PC11 SPI3_MISO To TFT LCD (CN13, pin 25) + * 80 PC12 SPI3_MOSI To TFT LCD (CN13, pin 27) + * 58 PD11 SD_CS Active low: Pulled high + * (See also TFT LCD CN13, pin 32) + * 60 PD13 LCD_RS To TFT LCD (CN13, pin 20) + * 61 PD14 LCD_WR To TFT LCD (CN13, pin 21). + * Schematic is wrong LCD_WR is PB14. + * 62 PD15 LCD_RD To TFT LCD (CN13, pin 22) + * 97 PE0 DB00 To TFT LCD (CN13, pin 3) + * 98 PE1 DB01 To TFT LCD (CN13, pin 4) + * 1 PE2 DB02 To TFT LCD (CN13, pin 5) + * 2 PE3 DB03 To TFT LCD (CN13, pin 6) + * 3 PE4 DB04 To TFT LCD (CN13, pin 7) + * 4 PE5 DB05 To TFT LCD (CN13, pin 8) + * 5 PE6 DB06 To TFT LCD (CN13, pin 9) + * 38 PE7 DB07 To TFT LCD (CN13, pin 10) + * 39 PE8 DB08 To TFT LCD (CN13, pin 11) + * 40 PE9 DB09 To TFT LCD (CN13, pin 12) + * 41 PE10 DB10 To TFT LCD (CN13, pin 13) + * 42 PE11 DB11 To TFT LCD (CN13, pin 16) + * 43 PE12 DB12 To TFT LCD (CN13, pin 15) + * 44 PE13 DB13 To TFT LCD (CN13, pin 16) + * 45 PE14 DB14 To TFT LCD (CN13, pin 17) + * 46 PE15 DB15 To TFT LCD (CN13, pin 18) + * + * NOTE: + * The backlight signl NC_BL (CN13, pin 24) is pulled high and not under + * software control + * + * On LCD module: + * -- -------------- -------------------------------------------------------- + * PN SIGNAL NOTES + * -- -------------- -------------------------------------------------------- + * 3 DB01 To LCD DB1 + * 4 DB00 To LCD DB0 + * 5 DB03 To LCD DB3 + * 6 DB02 To LCD DB2 + * 7 DB05 To LCD DB5 + * 8 DB04 To LCD DB4 + * 9 DB07 To LCD DB7 + * 10 DB06 To LCD DB6 + * 11 DB09 To LCD DB9 + * 12 DB08 To LCD DB8 + * 13 DB11 To LCD DB11 + * 14 DB10 To LCD DB10 + * 15 DB13 To LCD DB13 + * 16 DB12 To LCD DB12 + * 17 DB15 To LCD DB15 + * 18 DB14 To LCD DB14 + * 19 RS To LCD RS + * 20 /LCD_CS To LCD CS + * 21 /RD To LCD RD + * 22 /WR To LCD WR + * 23 BL_EN (Not referenced) + * 24 /RESET + * 25 /INT To Touch IC /INT + * 26 MISO To Touch IC DOUT; To AT45DB161B SO; To SD card DAT0 + * 27 LE To 74HC573 that controls LCD 8-bit/16-bit mode + * 28 MOSI To Touch IC DIN; To AT45DB161B SI; To SD card CMD + * 29 /DF_CS To AT45DB161B Data Flash /CS + * 30 SCLK To Touch IC DCLK; To AT45DB161B SCK; To SD card CLK + * 31 /SD_CS To SD card /CS + * 31 /TP_CS To Touch IC CS + */ + +/* LCD GPIO configurations */ + +#ifndef CONFIG_LCD_FASTCONFIG +static const uint32_t g_lcdout[16] = +{ + GPIO_LCD_D0OUT, GPIO_LCD_D1OUT, + GPIO_LCD_D2OUT, GPIO_LCD_D3OUT, + GPIO_LCD_D4OUT, GPIO_LCD_D5OUT, + GPIO_LCD_D6OUT, GPIO_LCD_D7OUT, + GPIO_LCD_D8OUT, GPIO_LCD_D9OUT, + GPIO_LCD_D10OUT, GPIO_LCD_D11OUT, + GPIO_LCD_D12OUT, GPIO_LCD_D13OUT, + GPIO_LCD_D14OUT, GPIO_LCD_D15OUT +}; + +static const uint32_t g_lcdin[16] = +{ + GPIO_LCD_D0IN, GPIO_LCD_D1IN, + GPIO_LCD_D2IN, GPIO_LCD_D3IN, + GPIO_LCD_D4IN, GPIO_LCD_D5IN, + GPIO_LCD_D6IN, GPIO_LCD_D7IN, + GPIO_LCD_D8IN, GPIO_LCD_D9IN, + GPIO_LCD_D10IN, GPIO_LCD_D11IN, + GPIO_LCD_D12IN, GPIO_LCD_D13IN, + GPIO_LCD_D14IN, GPIO_LCD_D15IN +}; +#endif + +static const uint32_t g_lcdconfig[] = +{ + GPIO_LCD_RS, GPIO_LCD_CS, + GPIO_LCD_RD, GPIO_LCD_WR, + GPIO_LCD_LE, +}; +#define NLCD_CONFIG (sizeof(g_lcdconfig)/sizeof(uint32_t)) + +/* Driver state structure (only supports one LCD) */ + +static struct stm32_lower_s g_lcdlower = +{ + { + .select = stm32_select, + .deselect = stm32_deselect, + .index = stm32_index, +#ifndef CONFIG_LCD_NOGETRUN + .read = stm32_read, +#endif + .write = stm32_write, + .backlight = stm32_backlight + }, + .drvr = NULL, + .output = false +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_lcdshow + * + * Description: + * Show the state of the interface + * + ****************************************************************************/ + +#ifdef CONFIG_LCD_REGDEBUG +static void stm32_lcdshow(struct stm32_lower_s *priv, + const char *msg) +{ + _info("%s:\n", msg); + _info(" CRTL RS: %d CS: %d RD: %d WR: %d LE: %d\n", + getreg32(LCD_RS_READ), getreg32(LCD_CS_READ), getreg32(LCD_RD_READ), + getreg32(LCD_WR_READ), getreg32(LCD_LE_READ)); + _info(" DATA CR: %08x %08x\n", getreg32(LCD_CRL), getreg32(LCD_CRH)); + if (priv->output) + { + _info(" OUTPUT: %08x\n", getreg32(LCD_ODR)); + } + else + { + _info(" INPUT: %08x\n", getreg32(LCD_IDR)); + } +} +#endif + +/**************************************************************************** + * Name: stm32_wrdata + * + * Description: + * Latch data on D0-D15 and toggle the WR line. + * + ****************************************************************************/ + +static void stm32_wrdata(struct stm32_lower_s *priv, uint16_t data) +{ + /* Make sure D0-D15 are configured as outputs */ + + stm32_lcdoutput(priv); + + /* Latch the 16-bit LCD data and toggle the WR line */ + + putreg32(1, LCD_WR_CLEAR); + putreg32((uint32_t)data, LCD_ODR); + + /* Total WR pulse with should be 50ns wide. */ + + putreg32(1, LCD_WR_SET); +} + +/**************************************************************************** + * Name: stm32_rddata + * + * Description: + * Latch data on D0-D15 and toggle the WR line. + * + ****************************************************************************/ + +#ifndef CONFIG_LCD_NOGETRUN +static inline uint16_t stm32_rddata(struct stm32_lower_s *priv) +{ + uint16_t regval; + + /* Make sure D0-D15 are configured as inputs */ + + stm32_lcdinput(priv); + + /* Toggle the RD line to latch the 16-bit LCD data */ + + putreg32(1, LCD_RD_CLEAR); + + /* Data should appear 250ns after RD. + * Total RD pulse width should be 500nS + */ + + __asm__ __volatile__(" nop\n nop\n nop\n nop\n"); + regval = (uint16_t)getreg32(LCD_IDR); + putreg32(1, LCD_RD_SET); + return regval; +} +#endif + +/**************************************************************************** + * Name: stm32_select + * + * Description: + * Select the LCD device + * + ****************************************************************************/ + +static void stm32_select(struct ssd1289_lcd_s *dev) +{ + /* Select the LCD by setting the LCD_CS low */ + + putreg32(1, LCD_CS_CLEAR); +} + +/**************************************************************************** + * Name: stm32_deselect + * + * Description: + * De-select the LCD device + * + ****************************************************************************/ + +static void stm32_deselect(struct ssd1289_lcd_s *dev) +{ + /* De-select the LCD by setting the LCD_CS high */ + + putreg32(1, LCD_CS_SET); +} + +/**************************************************************************** + * Name: stm32_index + * + * Description: + * Set the index register + * + ****************************************************************************/ + +static void stm32_index(struct ssd1289_lcd_s *dev, uint8_t index) +{ + struct stm32_lower_s *priv = (struct stm32_lower_s *)dev; + + /* Clear the RS signal to select the index address */ + + putreg32(1, LCD_RS_CLEAR); + + /* And write the index */ + + stm32_wrdata(priv, (uint16_t)index); +} + +/**************************************************************************** + * Name: stm32_read + * + * Description: + * Read LCD data (GRAM data or register contents) + * + ****************************************************************************/ + +#ifndef CONFIG_LCD_NOGETRUN +static uint16_t stm32_read(struct ssd1289_lcd_s *dev) +{ + struct stm32_lower_s *priv = (struct stm32_lower_s *)dev; + + /* Set the RS signal to select the data address */ + + putreg32(1, LCD_RS_SET); + + /* Read and return the data */ + + return stm32_rddata(priv); +} +#endif + +/**************************************************************************** + * Name: stm32_write + * + * Description: + * Write LCD data (GRAM data or register contents) + * + ****************************************************************************/ + +static void stm32_write(struct ssd1289_lcd_s *dev, uint16_t data) +{ + struct stm32_lower_s *priv = (struct stm32_lower_s *)dev; + + /* Set the RS signal to select the data address */ + + putreg32(1, LCD_RS_SET); + + /* And write the data */ + + stm32_wrdata(priv, data); +} + +/**************************************************************************** + * Name: stm32_backlight + * + * Description: + * Write LCD data (GRAM data or register contents) + * + ****************************************************************************/ + +static void stm32_backlight(struct ssd1289_lcd_s *dev, int power) +{ + /* There is no software control over the backlight */ +} + +/**************************************************************************** + * Name: stm32_lcdinput + * + * Description: + * Config data lines for input operations. + * + ****************************************************************************/ + +#ifndef CONFIG_LCD_NOGETRUN +static void stm32_lcdinput(struct stm32_lower_s *priv) +{ +#ifndef CONFIG_LCD_FASTCONFIG + int i; +#endif + + /* Check if we are already configured for input */ + + if (priv->output) + { + /* Configure GPIO data lines as inputs */ + +#ifdef CONFIG_LCD_FASTCONFIG + putreg32(LCD_INPUT, LCD_CRL); + putreg32(LCD_INPUT, LCD_CRH); +#else + for (i = 0; i < 16; i++) + { + stm32_configgpio(g_lcdin[i]); + } +#endif + + /* No longer configured for output */ + + priv->output = false; + } +} +#endif + +/**************************************************************************** + * Name: stm32_lcdoutput + * + * Description: + * Config data lines for output operations. + * + ****************************************************************************/ + +static void stm32_lcdoutput(struct stm32_lower_s *priv) +{ +#ifndef CONFIG_LCD_FASTCONFIG + int i; +#endif + + /* Check if we are already configured for output */ + + if (!priv->output) + { + /* Configure GPIO data lines as outputs */ + +#ifdef CONFIG_LCD_FASTCONFIG + putreg32(LCD_OUTPUT, LCD_CRL); + putreg32(LCD_OUTPUT, LCD_CRH); +#else + for (i = 0; i < 16; i++) + { + stm32_configgpio(g_lcdout[i]); + } +#endif + + /* Now we are configured for output */ + + priv->output = true; + } +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_lcd_initialize + * + * Description: + * Initialize the LCD video hardware. + * The initial state of the LCD is fully initialized, display memory + * cleared, and the LCD ready to use, but with the power setting at 0 + * (full off). + * + ****************************************************************************/ + +int board_lcd_initialize(void) +{ + struct stm32_lower_s *priv = &g_lcdlower; + int i; + + /* Only initialize the driver once */ + + if (!priv->drvr) + { + lcdinfo("Initializing\n"); + + /* Configure GPIO pins */ + + stm32_lcdoutput(priv); + for (i = 0; i < NLCD_CONFIG; i++) + { + stm32_configgpio(g_lcdconfig[i]); + } + + /* Configure and enable the LCD */ + + priv->drvr = ssd1289_lcdinitialize(&priv->dev); + if (!priv->drvr) + { + lcderr("ERROR: ssd1289_lcdinitialize failed\n"); + return -ENODEV; + } + } + + /* Turn the display off */ + + priv->drvr->setpower(priv->drvr, 0); + return OK; +} + +/**************************************************************************** + * Name: board_lcd_getdev + * + * Description: + * Return a a reference to the LCD object for the specified LCD. + * This allows support for multiple LCD devices. + * + ****************************************************************************/ + +struct lcd_dev_s *board_lcd_getdev(int lcddev) +{ + struct stm32_lower_s *priv = &g_lcdlower; + DEBUGASSERT(lcddev == 0); + return priv->drvr; +} + +/**************************************************************************** + * Name: board_lcd_uninitialize + * + * Description: + * Uninitialize the LCD support + * + ****************************************************************************/ + +void board_lcd_uninitialize(void) +{ + struct stm32_lower_s *priv = &g_lcdlower; + + /* Turn the display off */ + + priv->drvr->setpower(priv->drvr, 0); +} + +#endif /* CONFIG_LCD_SSD1289 */ diff --git a/boards/arm/stm32f1/shenzhou/src/stm32_touchscreen.c b/boards/arm/stm32f1/shenzhou/src/stm32_touchscreen.c new file mode 100644 index 0000000000000..c7733ba51f97d --- /dev/null +++ b/boards/arm/stm32f1/shenzhou/src/stm32_touchscreen.c @@ -0,0 +1,276 @@ +/**************************************************************************** + * boards/arm/stm32f1/shenzhou/src/stm32_touchscreen.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include "stm32.h" +#include "shenzhou.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +#ifdef CONFIG_INPUT_ADS7843E +#ifndef CONFIG_INPUT +# error "Touchscreen support requires CONFIG_INPUT" +#endif + +#ifndef CONFIG_STM32_SPI3 +# error "Touchscreen support requires CONFIG_STM32_SPI3" +#endif + +#ifndef CONFIG_ADS7843E_FREQUENCY +# define CONFIG_ADS7843E_FREQUENCY 500000 +#endif + +#ifndef CONFIG_ADS7843E_SPIDEV +# define CONFIG_ADS7843E_SPIDEV 3 +#endif + +#if CONFIG_ADS7843E_SPIDEV != 3 +# error "CONFIG_ADS7843E_SPIDEV must be three" +#endif + +#ifndef CONFIG_ADS7843E_DEVMINOR +# define CONFIG_ADS7843E_DEVMINOR 0 +#endif + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +struct stm32_config_s +{ + struct ads7843e_config_s dev; + xcpt_t handler; +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/* IRQ/GPIO access callbacks. These operations all hidden behind + * callbacks to isolate the ADS7843E driver from differences in GPIO + * interrupt handling by varying boards and MCUs. If possible, + * interrupts should be configured on both rising and falling edges + * so that contact and loss-of-contact events can be detected. + * + * attach - Attach the ADS7843E interrupt handler to the GPIO interrupt + * enable - Enable or disable the GPIO interrupt + * clear - Acknowledge/clear any pending GPIO interrupt + * pendown - Return the state of the pen down GPIO input + */ + +static int tsc_attach(struct ads7843e_config_s *state, xcpt_t isr); +static void tsc_enable(struct ads7843e_config_s *state, bool enable); +static void tsc_clear(struct ads7843e_config_s *state); +static bool tsc_busy(struct ads7843e_config_s *state); +static bool tsc_pendown(struct ads7843e_config_s *state); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* A reference to a structure of this type must be passed to the ADS7843E + * driver. This structure provides information about the configuration + * of the ADS7843E and provides some board-specific hooks. + * + * Memory for this structure is provided by the caller. It is not copied + * by the driver and is presumed to persist while the driver is active. The + * memory must be writable because, under certain circumstances, the driver + * may modify frequency or X plate resistance values. + */ + +static struct stm32_config_s g_tscinfo = +{ + { + .frequency = CONFIG_ADS7843E_FREQUENCY, + .attach = tsc_attach, + .enable = tsc_enable, + .clear = tsc_clear, + .busy = tsc_busy, + .pendown = tsc_pendown, + }, + .handler = NULL, +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/* IRQ/GPIO access callbacks. These operations all hidden behind + * callbacks to isolate the ADS7843E driver from differences in GPIO + * interrupt handling by varying boards and MCUs. If possible, + * interrupts should be configured on both rising and falling edges + * so that contact and loss-of-contact events can be detected. + * + * attach - Attach the ADS7843E interrupt handler to the GPIO interrupt + * enable - Enable or disable the GPIO interrupt + * clear - Acknowledge/clear any pending GPIO interrupt + * pendown - Return the state of the pen down GPIO input + */ + +static int tsc_attach(struct ads7843e_config_s *state, xcpt_t handler) +{ + struct stm32_config_s *priv = (struct stm32_config_s *)state; + + /* Just save the handler for use when the interrupt is enabled */ + + priv->handler = handler; + return OK; +} + +static void tsc_enable(struct ads7843e_config_s *state, bool enable) +{ + struct stm32_config_s *priv = (struct stm32_config_s *)state; + + /* The caller should not attempt to enable interrupts if the handler + * has not yet been 'attached' + */ + + DEBUGASSERT(priv->handler || !enable); + + /* Attach and enable, or detach and disable */ + + iinfo("enable:%d\n", enable); + if (enable) + { + stm32_gpiosetevent(GPIO_TP_INT, true, true, false, + priv->handler, NULL); + } + else + { + stm32_gpiosetevent(GPIO_TP_INT, false, false, false, + NULL, NULL); + } +} + +static void tsc_clear(struct ads7843e_config_s *state) +{ + /* Does nothing */ +} + +static bool tsc_busy(struct ads7843e_config_s *state) +{ + /* Hmmm... The ADS7843E BUSY pin is not brought out on the Shenzhou board. + * We will most certainly have to revisit this. There is this cryptic + * statement in the XPT2046 spec: "No DCLK delay required with dedicated + * serial port." + * + * The busy state is used by the ADS7843E driver to control the delay + * between sending the command, then reading the returned data. + */ + + return false; +} + +static bool tsc_pendown(struct ads7843e_config_s *state) +{ + /* XPT2046 uses an an internal pullup resistor. The PENIRQ output goes low + * due to the current path through the touch screen to ground, which + * initiates an interrupt to the processor via TP_INT. + */ + + bool pendown = !stm32_gpioread(GPIO_TP_INT); + iinfo("pendown:%d\n", pendown); + return pendown; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_tsc_setup + * + * Description: + * This function is called by board-bringup logic to configure the + * touchscreen device. This function will register the driver as + * /dev/inputN where N is the minor device number. + * + * Input Parameters: + * minor - The input device minor number + * + * Returned Value: + * Zero is returned on success. Otherwise, a negated errno value is + * returned to indicate the nature of the failure. + * + ****************************************************************************/ + +int stm32_tsc_setup(int minor) +{ + struct spi_dev_s *dev; + int ret; + + iinfo("minor %d\n", minor); + DEBUGASSERT(minor == 0); + + /* Configure and enable the ADS7843E interrupt pin as an input. */ + + stm32_configgpio(GPIO_TP_INT); + + /* Get an instance of the SPI interface */ + + dev = stm32_spibus_initialize(CONFIG_ADS7843E_SPIDEV); + if (!dev) + { + ierr("ERROR: Failed to initialize SPI bus %d\n", + CONFIG_ADS7843E_SPIDEV); + return -ENODEV; + } + + /* Initialize and register the SPI touschscreen device */ + + ret = ads7843e_register(dev, &g_tscinfo.dev, + CONFIG_ADS7843E_DEVMINOR); + if (ret < 0) + { + ierr("ERROR: Failed to initialize SPI bus %d\n", + CONFIG_ADS7843E_SPIDEV); + + /* up_spiuninitialize(dev); */ + + return -ENODEV; + } + + return OK; +} + +#endif /* CONFIG_INPUT_ADS7843E */ diff --git a/boards/arm/stm32f1/shenzhou/src/stm32_usb.c b/boards/arm/stm32f1/shenzhou/src/stm32_usb.c new file mode 100644 index 0000000000000..bbc47272d2334 --- /dev/null +++ b/boards/arm/stm32f1/shenzhou/src/stm32_usb.c @@ -0,0 +1,304 @@ +/**************************************************************************** + * boards/arm/stm32f1/shenzhou/src/stm32_usb.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include "arm_internal.h" +#include "stm32.h" +#include "stm32_otgfs.h" +#include "shenzhou.h" + +#ifdef CONFIG_STM32_OTGFS + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#if defined(CONFIG_USBDEV) || defined(CONFIG_USBHOST) +# define HAVE_USB 1 +#else +# warning "CONFIG_STM32_OTGFS is enabled but neither CONFIG_USBDEV nor CONFIG_USBHOST" +# undef HAVE_USB +#endif + +#ifndef CONFIG_USBHOST_DEFPRIO +# define CONFIG_USBHOST_DEFPRIO 50 +#endif + +#ifndef CONFIG_USBHOST_STACKSIZE +# ifdef CONFIG_USBHOST_HUB +# define CONFIG_USBHOST_STACKSIZE 1536 +# else +# define CONFIG_USBHOST_STACKSIZE 1024 +# endif +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +static struct usbhost_connection_s *g_usbconn; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: usbhost_waiter + * + * Description: + * Wait for USB devices to be connected. + * + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +static int usbhost_waiter(int argc, char *argv[]) +{ + struct usbhost_hubport_s *hport; + + uinfo("Running\n"); + for (; ; ) + { + /* Wait for the device to change state */ + + DEBUGVERIFY(CONN_WAIT(g_usbconn, &hport)); + uinfo("%s\n", hport->connected ? "connected" : "disconnected"); + + /* Did we just become connected? */ + + if (hport->connected) + { + /* Yes.. enumerate the newly connected device */ + + CONN_ENUMERATE(g_usbconn, hport); + } + } + + /* Keep the compiler from complaining */ + + return 0; +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_usbinitialize + * + * Description: + * Called from stm32_usbinitialize very early in initialization to setup + * USB-related GPIO pins for the STM3240G-EVAL board. + * + ****************************************************************************/ + +void stm32_usbinitialize(void) +{ + /* The OTG FS has an internal soft pull-up. + * No GPIO configuration is required + */ + + /* Configure the OTG FS VBUS sensing GPIO, + * Power On, and Overcurrent GPIOs + */ + +#ifdef CONFIG_STM32_OTGFS + stm32_configgpio(GPIO_OTGFS_VBUS); + stm32_configgpio(GPIO_OTGFS_PWRON); + stm32_configgpio(GPIO_OTGFS_OVER); +#endif +} + +/**************************************************************************** + * Name: stm32_usbhost_initialize + * + * Description: + * Called at application startup time to initialize the USB host + * functionality. + * This function will start a thread that will monitor for device + * connection/disconnection events. + * + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +int stm32_usbhost_initialize(void) +{ + int ret; + + /* First, register all of the class drivers needed to support the drivers + * that we care about: + */ + + uinfo("Register class drivers\n"); + +#ifdef CONFIG_USBHOST_MSC + /* Register the USB mass storage class class */ + + ret = usbhost_msc_initialize(); + if (ret != OK) + { + uerr("ERROR: Failed to register the mass storage class: %d\n", ret); + } +#endif + +#ifdef CONFIG_USBHOST_CDCACM + /* Register the CDC/ACM serial class */ + + ret = usbhost_cdcacm_initialize(); + if (ret != OK) + { + uerr("ERROR: Failed to register the CDC/ACM serial class: %d\n", ret); + } +#endif + + /* Then get an instance of the USB host interface */ + + uinfo("Initialize USB host\n"); + g_usbconn = stm32_otgfshost_initialize(0); + if (g_usbconn) + { + /* Start a thread to handle device connection. */ + + uinfo("Start usbhost_waiter\n"); + + ret = kthread_create("usbhost", CONFIG_USBHOST_DEFPRIO, + CONFIG_USBHOST_STACKSIZE, + usbhost_waiter, NULL); + return ret < 0 ? -ENOEXEC : OK; + } + + return -ENODEV; +} +#endif + +/**************************************************************************** + * Name: stm32_usbhost_vbusdrive + * + * Description: + * Enable/disable driving of VBUS 5V output. This function must be + * provided be each platform that implements the STM32 OTG FS host + * interface + * + * "On-chip 5 V VBUS generation is not supported. For this reason, a + * charge pump or, if 5 V are available on the application board, a + * basic power switch, must be added externally to drive the 5 V VBUS + * line. The external charge pump can be driven by any GPIO output. + * When the application decides to power on VBUS using the chosen GPIO, + * it must also set the port power bit in the host port control and + * status register (PPWR bit in OTG_FS_HPRT). + * + * "The application uses this field to control power to this port, + * and the core clears this bit on an overcurrent condition." + * + * Input Parameters: + * iface - For future growth to handle multiple USB host interface. + * Should be zero. + * enable - true: enable VBUS power; false: disable VBUS power + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +void stm32_usbhost_vbusdrive(int iface, bool enable) +{ + DEBUGASSERT(iface == 0); + + if (enable) + { + /* Enable the Power Switch by driving the enable pin low */ + + stm32_gpiowrite(GPIO_OTGFS_PWRON, false); + } + else + { + /* Disable the Power Switch by driving the enable pin high */ + + stm32_gpiowrite(GPIO_OTGFS_PWRON, true); + } +} +#endif + +/**************************************************************************** + * Name: stm32_setup_overcurrent + * + * Description: + * Setup to receive an interrupt-level callback if an overcurrent + * condition is detected. + * + * Input Parameters: + * handler - New overcurrent interrupt handler + * arg - The argument provided for the interrupt handler + * + * Returned Value: + * Zero (OK) is returned on success. Otherwise, a negated errno value + * is returned to indicate the nature of the failure. + * + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +int stm32_setup_overcurrent(xcpt_t handler, void *arg) +{ + return -ENOSYS; +} +#endif + +/**************************************************************************** + * Name: stm32_usbsuspend + * + * Description: + * Board logic must provide the stm32_usbsuspend logic if the USBDEV + * driver is used. This function is called whenever the USB enters or + * leaves suspend mode. This is an opportunity for the board logic to + * shutdown clocks, power, etc. while the USB is suspended. + * + ****************************************************************************/ + +#ifdef CONFIG_USBDEV +void stm32_usbsuspend(struct usbdev_s *dev, bool resume) +{ + uinfo("resume: %d\n", resume); +} +#endif + +#endif /* CONFIG_STM32_OTGFS */ diff --git a/boards/arm/stm32f1/shenzhou/src/stm32_usbmsc.c b/boards/arm/stm32f1/shenzhou/src/stm32_usbmsc.c new file mode 100644 index 0000000000000..bce9cfc30f6b0 --- /dev/null +++ b/boards/arm/stm32f1/shenzhou/src/stm32_usbmsc.c @@ -0,0 +1,72 @@ +/**************************************************************************** + * boards/arm/stm32f1/shenzhou/src/stm32_usbmsc.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include + +#include "stm32.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +#ifndef CONFIG_SYSTEM_USBMSC_DEVMINOR1 +# define CONFIG_SYSTEM_USBMSC_DEVMINOR1 0 +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_usbmsc_initialize + * + * Description: + * Perform architecture specific initialization as needed to establish + * the mass storage device that will be exported by the USB MSC device. + * + ****************************************************************************/ + +int board_usbmsc_initialize(int port) +{ + /* If system/usbmsc is built as an NSH command, then SD slot should + * already have been initialized. + * In this case, there is nothing further to be done here. + */ + +#ifndef CONFIG_NSH_BUILTIN_APPS + return stm32_sdinitialize(CONFIG_SYSTEM_USBMSC_DEVMINOR1); +#else + return OK; +#endif +} diff --git a/boards/arm/stm32f1/shenzhou/src/stm32_userleds.c b/boards/arm/stm32f1/shenzhou/src/stm32_userleds.c new file mode 100644 index 0000000000000..9b18917f728a0 --- /dev/null +++ b/boards/arm/stm32f1/shenzhou/src/stm32_userleds.c @@ -0,0 +1,96 @@ +/**************************************************************************** + * boards/arm/stm32f1/shenzhou/src/stm32_userleds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32.h" +#include "shenzhou.h" + +#ifndef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* This array maps an LED number to GPIO pin configuration */ + +static uint32_t g_ledcfg[BOARD_NLEDS] = +{ + GPIO_LED1, GPIO_LED2, GPIO_LED3, GPIO_LED4 +}; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_userled_initialize + ****************************************************************************/ + +uint32_t board_userled_initialize(void) +{ + /* Configure LED1-4 GPIOs for output */ + + stm32_configgpio(GPIO_LED1); + stm32_configgpio(GPIO_LED2); + stm32_configgpio(GPIO_LED3); + stm32_configgpio(GPIO_LED4); + return BOARD_NLEDS; +} + +/**************************************************************************** + * Name: board_userled + ****************************************************************************/ + +void board_userled(int led, bool ledon) +{ + if ((unsigned)led < BOARD_NLEDS) + { + stm32_gpiowrite(g_ledcfg[led], ledon); + } +} + +/**************************************************************************** + * Name: board_userled_all + ****************************************************************************/ + +void board_userled_all(uint32_t ledset) +{ + stm32_gpiowrite(GPIO_LED1, (ledset & BOARD_LED1_BIT) == 0); + stm32_gpiowrite(GPIO_LED2, (ledset & BOARD_LED2_BIT) == 0); + stm32_gpiowrite(GPIO_LED3, (ledset & BOARD_LED3_BIT) == 0); + stm32_gpiowrite(GPIO_LED4, (ledset & BOARD_LED4_BIT) == 0); +} + +#endif /* !CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32f1/shenzhou/src/stm32_w25.c b/boards/arm/stm32f1/shenzhou/src/stm32_w25.c new file mode 100644 index 0000000000000..1658b957ca3ab --- /dev/null +++ b/boards/arm/stm32f1/shenzhou/src/stm32_w25.c @@ -0,0 +1,145 @@ +/**************************************************************************** + * boards/arm/stm32f1/shenzhou/src/stm32_w25.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#ifdef CONFIG_STM32_SPI1 +# include +# include +# include +# include + +# include "stm32_spi.h" +#endif + +#include "shenzhou.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* Can't support the W25 device if it SPI1 or W25 support is not enabled */ + +#define HAVE_W25 1 +#if !defined(CONFIG_STM32_SPI1) || !defined(CONFIG_MTD_W25) +# undef HAVE_W25 +#endif + +/* Can't support W25 features if mountpoints are disabled */ + +#if defined(CONFIG_DISABLE_MOUNTPOINT) +# undef HAVE_W25 +#endif + +/* Can't support both FAT and NXFFS */ + +#if defined(CONFIG_FS_FAT) && defined(CONFIG_FS_NXFFS) +# warning "Can't support both FAT and NXFFS -- using FAT" +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_w25initialize + * + * Description: + * Initialize and register the W25 FLASH file system. + * + ****************************************************************************/ + +int stm32_w25initialize(int minor) +{ +#ifdef HAVE_W25 + struct spi_dev_s *spi; + struct mtd_dev_s *mtd; +#ifdef CONFIG_FS_NXFFS + char devname[12]; +#endif + int ret; + + /* Get the SPI port */ + + spi = stm32_spibus_initialize(1); + if (!spi) + { + ferr("ERROR: Failed to initialize SPI port 2\n"); + return -ENODEV; + } + + /* Now bind the SPI interface to the W25 SPI FLASH driver */ + + mtd = w25_initialize(spi); + if (!mtd) + { + ferr("ERROR: Failed to bind SPI port 2 to the SST 25 FLASH driver\n"); + return -ENODEV; + } + +#ifndef CONFIG_FS_NXFFS + /* Register the MTD driver */ + + char path[32]; + snprintf(path, sizeof(path), "/dev/mtdblock%d", minor); + ret = register_mtddriver(path, mtd, 0755, NULL); + if (ret < 0) + { + ferr("ERROR: Failed to register the MTD driver %s, ret %d\n", + path, ret); + return ret; + } +#else + /* Initialize to provide NXFFS on the MTD interface */ + + ret = nxffs_initialize(mtd); + if (ret < 0) + { + ferr("ERROR: NXFFS initialization failed: %d\n", -ret); + return ret; + } + + /* Mount the file system at /mnt/w25 */ + + snprintf(devname, sizeof(devname), "/mnt/w25%c", 'a' + minor); + ret = nx_mount(NULL, devname, "nxffs", 0, NULL); + if (ret < 0) + { + ferr("ERROR: Failed to mount the NXFFS volume: %d\n", ret); + return ret; + } +#endif +#endif + + return OK; +} diff --git a/boards/arm/stm32/shenzhou/tools/olimex-arm-usb-ocd.cfg b/boards/arm/stm32f1/shenzhou/tools/olimex-arm-usb-ocd.cfg similarity index 100% rename from boards/arm/stm32/shenzhou/tools/olimex-arm-usb-ocd.cfg rename to boards/arm/stm32f1/shenzhou/tools/olimex-arm-usb-ocd.cfg diff --git a/boards/arm/stm32f1/shenzhou/tools/oocd.sh b/boards/arm/stm32f1/shenzhou/tools/oocd.sh new file mode 100755 index 0000000000000..e965ac36e90cc --- /dev/null +++ b/boards/arm/stm32f1/shenzhou/tools/oocd.sh @@ -0,0 +1,90 @@ +#!/usr/bin/env bash + +# Get command line parameters + +USAGE="USAGE: $0 [-dh] " +ADVICE="Try '$0 -h' for more information" + +unset DEBUG + +while [ ! -z "$1" ]; do + case $1 in + -d ) + set -x + DEBUG=-d3 + ;; + -h ) + echo "$0 is a tool for generation of proper version files for the NuttX build" + echo "" + echo $USAGE + echo "" + echo "Where:" + echo " -d" + echo " Enable script debug" + echo " -h" + echo " show this help message and exit" + echo " Use the OpenOCD 0.4.0" + echo " " + echo " The full path to the top-level NuttX directory" + exit 0 + ;; + * ) + break; + ;; + esac + shift +done + +TOPDIR=$1 +if [ -z "${TOPDIR}" ]; then + echo "Missing argument" + echo $USAGE + echo $ADVICE + exit 1 +fi + +# This script *probably* only works with the following versions of OpenOCD: + +# Local search directory and configurations + +OPENOCD_SEARCHDIR="${TOPDIR}/boards/arm/stm32f1/shenzhou/tools" +OPENOCD_WSEARCHDIR="`cygpath -w ${OPENOCD_SEARCHDIR}`" + +OPENOCD_PATH="/cygdrive/c/Program Files (x86)/OpenOCD/0.4.0/bin" +OPENOCD_EXE=openocd.exe +OPENOCD_INTERFACE="olimex-arm-usb-ocd.cfg" + +OPENOCD_TARGET="stm32.cfg" +OPENOCD_ARGS="${DEBUG} -s ${OPENOCD_WSEARCHDIR} -f ${OPENOCD_INTERFACE} -f ${OPENOCD_TARGET}" + +echo "Trying OpenOCD 0.4.0 path: ${OPENOCD_PATH}/${OPENOCD_EXE}" + +# Verify that everything is what it claims it is and is located where it claims it is. + +if [ ! -x "${OPENOCD_PATH}/${OPENOCD_EXE}" ]; then + echo "OpenOCD executable does not exist: ${OPENOCD_PATH}/${OPENOCD_EXE}" + exit 1 +fi +if [ ! -f "${OPENOCD_SEARCHDIR}/${OPENOCD_TARGET}" ]; then + echo "OpenOCD target config file does not exist: ${OPENOCD_SEARCHDIR}/${OPENOCD_TARGET}" + exit 1 +fi +if [ ! -f "${OPENOCD_SEARCHDIR}/${OPENOCD_INTERFACE}" ]; then + echo "OpenOCD interface config file does not exist: ${OPENOCD_SEARCHDIR}/${OPENOCD_INTERFACE}" + exit 1 +fi + +# Enable debug if so requested + +if [ "X$2" = "X-d" ]; then + OPENOCD_ARGS=$OPENOCD_ARGS" -d3" + set -x +fi + +# Okay... do it! + +echo "Starting OpenOCD" +"${OPENOCD_PATH}/${OPENOCD_EXE}" ${OPENOCD_ARGS} & +echo "OpenOCD daemon started" +ps -ef | grep openocd +echo "In GDB: target remote localhost:3333" diff --git a/boards/arm/stm32/shenzhou/tools/stm32.cfg b/boards/arm/stm32f1/shenzhou/tools/stm32.cfg similarity index 100% rename from boards/arm/stm32/shenzhou/tools/stm32.cfg rename to boards/arm/stm32f1/shenzhou/tools/stm32.cfg diff --git a/boards/arm/stm32/shenzhou/tools/usb-driver.txt b/boards/arm/stm32f1/shenzhou/tools/usb-driver.txt similarity index 100% rename from boards/arm/stm32/shenzhou/tools/usb-driver.txt rename to boards/arm/stm32f1/shenzhou/tools/usb-driver.txt diff --git a/boards/arm/stm32f1/stm3210e-eval/CMakeLists.txt b/boards/arm/stm32f1/stm3210e-eval/CMakeLists.txt new file mode 100644 index 0000000000000..c8d5f73a4984d --- /dev/null +++ b/boards/arm/stm32f1/stm3210e-eval/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32f1/stm3210e-eval/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/arm/stm32/stm3210e-eval/Kconfig b/boards/arm/stm32f1/stm3210e-eval/Kconfig similarity index 100% rename from boards/arm/stm32/stm3210e-eval/Kconfig rename to boards/arm/stm32f1/stm3210e-eval/Kconfig diff --git a/boards/arm/stm32f1/stm3210e-eval/configs/composite/defconfig b/boards/arm/stm32f1/stm3210e-eval/configs/composite/defconfig new file mode 100644 index 0000000000000..ceb671630bab5 --- /dev/null +++ b/boards/arm/stm32f1/stm3210e-eval/configs/composite/defconfig @@ -0,0 +1,66 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_MMCSD_HAVE_CARDDETECT is not set +# CONFIG_MMCSD_MMCSUPPORT is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm3210e-eval" +CONFIG_ARCH_BOARD_STM3210E_EVAL=y +CONFIG_ARCH_CHIP="stm32f1" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F103ZE=y +CONFIG_ARCH_CHIP_STM32F1=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL=y +CONFIG_BOARD_LOOPSPERMSEC=5483 +CONFIG_CDCACM=y +CONFIG_CDCACM_COMPOSITE=y +CONFIG_CDCACM_RXBUFSIZE=256 +CONFIG_CDCACM_TXBUFSIZE=256 +CONFIG_COMPOSITE_CONFIGSTR="system/composite" +CONFIG_COMPOSITE_IAD=y +CONFIG_COMPOSITE_PRODUCTID=0x2022 +CONFIG_COMPOSITE_PRODUCTSTR="Composite Device" +CONFIG_COMPOSITE_SERIALSTR="12345" +CONFIG_COMPOSITE_VENDORID=0x03eb +CONFIG_HOST_WINDOWS=y +CONFIG_INIT_ENTRYPOINT="conn_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_MMCSD=y +CONFIG_MMCSD_SDIO=y +CONFIG_MTD=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=65536 +CONFIG_RAM_START=0x20000000 +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=192 +CONFIG_SCHED_HPWORKSTACKSIZE=1024 +CONFIG_START_DAY=30 +CONFIG_START_MONTH=11 +CONFIG_START_YEAR=2009 +CONFIG_STM32_DFU=y +CONFIG_STM32_DMA2=y +CONFIG_STM32_FSMC=y +CONFIG_STM32_JTAG_FULL_ENABLE=y +CONFIG_STM32_SDIO=y +CONFIG_STM32_USART1=y +CONFIG_STM32_USART2=y +CONFIG_STM32_USB=y +CONFIG_SYMTAB_ORDEREDBYNAME=y +CONFIG_SYSTEM_COMPOSITE=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART1_SERIAL_CONSOLE=y +CONFIG_USBDEV_COMPOSITE=y +CONFIG_USBMSC=y +CONFIG_USBMSC_BULKINREQLEN=256 +CONFIG_USBMSC_BULKOUTREQLEN=256 +CONFIG_USBMSC_COMPOSITE=y +CONFIG_USBMSC_NRDREQS=2 +CONFIG_USBMSC_NWRREQS=2 +CONFIG_USBMSC_REMOVABLE=y +CONFIG_USBMSC_VERSIONNO=0x0399 diff --git a/boards/arm/stm32f1/stm3210e-eval/configs/nsh/defconfig b/boards/arm/stm32f1/stm3210e-eval/configs/nsh/defconfig new file mode 100644 index 0000000000000..7b6a0aa141087 --- /dev/null +++ b/boards/arm/stm32f1/stm3210e-eval/configs/nsh/defconfig @@ -0,0 +1,53 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_MMCSD_HAVE_CARDDETECT is not set +# CONFIG_MMCSD_MMCSUPPORT is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm3210e-eval" +CONFIG_ARCH_BOARD_STM3210E_EVAL=y +CONFIG_ARCH_CHIP="stm32f1" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F103ZE=y +CONFIG_ARCH_CHIP_STM32F1=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_ARM_TOOLCHAIN_BUILDROOT=y +CONFIG_BOARD_LOOPSPERMSEC=5483 +CONFIG_FAT_LCNAMES=y +CONFIG_FS_FAT=y +CONFIG_HOST_WINDOWS=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_MMCSD=y +CONFIG_MMCSD_SDIO=y +CONFIG_MTD=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=65536 +CONFIG_RAM_START=0x20000000 +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=192 +CONFIG_SCHED_HPWORKSTACKSIZE=1024 +CONFIG_START_DAY=21 +CONFIG_START_MONTH=9 +CONFIG_START_YEAR=2009 +CONFIG_STM32_DFU=y +CONFIG_STM32_DMA2=y +CONFIG_STM32_FSMC=y +CONFIG_STM32_JTAG_FULL_ENABLE=y +CONFIG_STM32_SDIO=y +CONFIG_STM32_USART1=y +CONFIG_STM32_USART2=y +CONFIG_STM32_USB=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f1/stm3210e-eval/configs/nsh2/defconfig b/boards/arm/stm32f1/stm3210e-eval/configs/nsh2/defconfig new file mode 100644 index 0000000000000..9fab1ef45c748 --- /dev/null +++ b/boards/arm/stm32f1/stm3210e-eval/configs/nsh2/defconfig @@ -0,0 +1,110 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_EXAMPLES_NXHELLO_DEFAULT_COLORS is not set +# CONFIG_EXAMPLES_NXHELLO_DEFAULT_FONT is not set +# CONFIG_EXAMPLES_NX_DEFAULT_COLORS is not set +# CONFIG_EXAMPLES_NX_DEFAULT_FONT is not set +# CONFIG_MMCSD_HAVE_CARDDETECT is not set +# CONFIG_MMCSD_MMCSUPPORT is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_NXFONTS_DISABLE_16BPP is not set +# CONFIG_NXTK_DEFAULT_BORDERCOLORS is not set +# CONFIG_NX_DISABLE_16BPP is not set +# CONFIG_NX_PACKEDMSFIRST is not set +# CONFIG_NX_WRITEONLY is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm3210e-eval" +CONFIG_ARCH_BOARD_STM3210E_EVAL=y +CONFIG_ARCH_CHIP="stm32f1" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F103ZE=y +CONFIG_ARCH_CHIP_STM32F1=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=5483 +CONFIG_BUILTIN=y +CONFIG_EXAMPLES_NX=y +CONFIG_EXAMPLES_NXHELLO=y +CONFIG_EXAMPLES_NXHELLO_BGCOLOR=0x0011 +CONFIG_EXAMPLES_NXHELLO_BPP=16 +CONFIG_EXAMPLES_NXHELLO_FONTCOLOR=0xffdf +CONFIG_EXAMPLES_NXHELLO_FONTID=6 +CONFIG_EXAMPLES_NX_BGCOLOR=0x0011 +CONFIG_EXAMPLES_NX_BPP=16 +CONFIG_EXAMPLES_NX_COLOR1=0xaedc +CONFIG_EXAMPLES_NX_COLOR2=0xe7ff +CONFIG_EXAMPLES_NX_FONTCOLOR=0x0000 +CONFIG_EXAMPLES_NX_FONTID=0 +CONFIG_EXAMPLES_NX_TBCOLOR=0xd69a +CONFIG_FAT_LCNAMES=y +CONFIG_FAT_LFN=y +CONFIG_FS_FAT=y +CONFIG_HOST_WINDOWS=y +CONFIG_I2C=y +CONFIG_I2CTOOL_DEFFREQ=100000 +CONFIG_I2CTOOL_MAXBUS=2 +CONFIG_I2CTOOL_MINBUS=1 +CONFIG_I2C_POLLED=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LCD_MAXCONTRAST=1 +CONFIG_LCD_NOGETRUN=y +CONFIG_LCD_RPORTRAIT=y +CONFIG_LINE_MAX=64 +CONFIG_MMCSD=y +CONFIG_MMCSD_SDIO=y +CONFIG_MQ_MAXMSGSIZE=64 +CONFIG_MTD=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_NX=y +CONFIG_NXFONT_SANS23X27=y +CONFIG_NXFONT_SANS28X37B=y +CONFIG_NXTK_BORDERCOLOR1=0xd69a +CONFIG_NXTK_BORDERCOLOR2=0xad55 +CONFIG_NX_BLOCKING=y +CONFIG_NX_KBD=y +CONFIG_NX_XYINPUT_MOUSE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=65536 +CONFIG_RAM_START=0x20000000 +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=192 +CONFIG_SCHED_HPWORKSTACKSIZE=1024 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=5 +CONFIG_START_MONTH=7 +CONFIG_START_YEAR=2011 +CONFIG_STM3210E_LCD=y +CONFIG_STM3210E_R61580_DISABLE=y +CONFIG_STM32_DFU=y +CONFIG_STM32_DMA2=y +CONFIG_STM32_FSMC=y +CONFIG_STM32_I2C1=y +CONFIG_STM32_JTAG_FULL_ENABLE=y +CONFIG_STM32_SDIO=y +CONFIG_STM32_USART1=y +CONFIG_STM32_USART2=y +CONFIG_STM32_USB=y +CONFIG_SYSTEM_I2CTOOL=y +CONFIG_SYSTEM_NSH=y +CONFIG_SYSTEM_USBMSC=y +CONFIG_SYSTEM_USBMSC_DEVMINOR1=0 +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART1_SERIAL_CONSOLE=y +CONFIG_USBMSC=y +CONFIG_USBMSC_BULKINREQLEN=256 +CONFIG_USBMSC_BULKOUTREQLEN=256 +CONFIG_USBMSC_EPBULKIN=5 +CONFIG_USBMSC_NRDREQS=2 +CONFIG_USBMSC_NWRREQS=2 +CONFIG_USBMSC_PRODUCTSTR="USBdev Storage" +CONFIG_USBMSC_REMOVABLE=y +CONFIG_USBMSC_VERSIONNO=0x0399 diff --git a/boards/arm/stm32f1/stm3210e-eval/configs/nx/defconfig b/boards/arm/stm32f1/stm3210e-eval/configs/nx/defconfig new file mode 100644 index 0000000000000..280f178d64d4b --- /dev/null +++ b/boards/arm/stm32f1/stm3210e-eval/configs/nx/defconfig @@ -0,0 +1,72 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_EXAMPLES_NX_DEFAULT_COLORS is not set +# CONFIG_EXAMPLES_NX_DEFAULT_FONT is not set +# CONFIG_NXFONTS_DISABLE_16BPP is not set +# CONFIG_NXTK_DEFAULT_BORDERCOLORS is not set +# CONFIG_NX_DISABLE_16BPP is not set +# CONFIG_NX_PACKEDMSFIRST is not set +# CONFIG_NX_WRITEONLY is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm3210e-eval" +CONFIG_ARCH_BOARD_STM3210E_EVAL=y +CONFIG_ARCH_CHIP="stm32f1" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F103ZE=y +CONFIG_ARCH_CHIP_STM32F1=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=5483 +CONFIG_CONSOLE_SYSLOG=y +CONFIG_DISABLE_ENVIRON=y +CONFIG_DISABLE_MOUNTPOINT=y +CONFIG_DISABLE_POSIX_TIMERS=y +CONFIG_EXAMPLES_NX=y +CONFIG_EXAMPLES_NX_BGCOLOR=0x0011 +CONFIG_EXAMPLES_NX_BPP=16 +CONFIG_EXAMPLES_NX_COLOR1=0xaedc +CONFIG_EXAMPLES_NX_COLOR2=0xe7ff +CONFIG_EXAMPLES_NX_FONTCOLOR=0x0000 +CONFIG_EXAMPLES_NX_FONTID=0 +CONFIG_EXAMPLES_NX_TBCOLOR=0xd69a +CONFIG_HOST_WINDOWS=y +CONFIG_INIT_ENTRYPOINT="nx_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LCD_MAXCONTRAST=1 +CONFIG_LCD_NOGETRUN=y +CONFIG_LCD_RPORTRAIT=y +CONFIG_MQ_MAXMSGSIZE=64 +CONFIG_NX=y +CONFIG_NXFONT_SANS23X27=y +CONFIG_NXTK_BORDERCOLOR1=0xad55 +CONFIG_NXTK_BORDERCOLOR2=0x6b4d +CONFIG_NXTK_BORDERCOLOR3=0xdedb +CONFIG_NX_BLOCKING=y +CONFIG_NX_KBD=y +CONFIG_NX_XYINPUT_MOUSE=y +CONFIG_RAM_SIZE=65536 +CONFIG_RAM_START=0x20000000 +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=192 +CONFIG_SCHED_HPWORKSTACKSIZE=1024 +CONFIG_START_DAY=5 +CONFIG_START_MONTH=7 +CONFIG_START_YEAR=2011 +CONFIG_STM3210E_LCD=y +CONFIG_STM3210E_R61580_DISABLE=y +CONFIG_STM32_DFU=y +CONFIG_STM32_DMA2=y +CONFIG_STM32_FSMC=y +CONFIG_STM32_I2C1=y +CONFIG_STM32_JTAG_FULL_ENABLE=y +CONFIG_STM32_USART1=y +CONFIG_STM32_USART2=y +CONFIG_STM32_USB=y +CONFIG_SYMTAB_ORDEREDBYNAME=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f1/stm3210e-eval/configs/nxterm/defconfig b/boards/arm/stm32f1/stm3210e-eval/configs/nxterm/defconfig new file mode 100644 index 0000000000000..aeaf6de160c35 --- /dev/null +++ b/boards/arm/stm32f1/stm3210e-eval/configs/nxterm/defconfig @@ -0,0 +1,68 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_NXFONTS_DISABLE_16BPP is not set +# CONFIG_NXTK_DEFAULT_BORDERCOLORS is not set +# CONFIG_NX_DISABLE_16BPP is not set +# CONFIG_NX_PACKEDMSFIRST is not set +# CONFIG_NX_WRITEONLY is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm3210e-eval" +CONFIG_ARCH_BOARD_STM3210E_EVAL=y +CONFIG_ARCH_CHIP="stm32f1" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F103ZE=y +CONFIG_ARCH_CHIP_STM32F1=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=5483 +CONFIG_BUILTIN=y +CONFIG_EXAMPLES_NXTERM=y +CONFIG_HOST_WINDOWS=y +CONFIG_INIT_ENTRYPOINT="nxterm_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LCD_MAXCONTRAST=1 +CONFIG_LCD_NOGETRUN=y +CONFIG_LINE_MAX=64 +CONFIG_MQ_MAXMSGSIZE=64 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_LIBRARY=y +CONFIG_NSH_READLINE=y +CONFIG_NX=y +CONFIG_NXFONT_SANS23X27=y +CONFIG_NXTERM=y +CONFIG_NXTERM_CACHESIZE=32 +CONFIG_NXTERM_CURSORCHAR=95 +CONFIG_NXTERM_MXCHARS=256 +CONFIG_NXTK_BORDERCOLOR1=0xad55 +CONFIG_NXTK_BORDERCOLOR2=0x6b4d +CONFIG_NXTK_BORDERCOLOR3=0xdedb +CONFIG_NX_BLOCKING=y +CONFIG_NX_KBD=y +CONFIG_NX_XYINPUT_MOUSE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=65536 +CONFIG_RAM_START=0x20000000 +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=192 +CONFIG_SCHED_HPWORKSTACKSIZE=1024 +CONFIG_START_DAY=29 +CONFIG_START_MONTH=3 +CONFIG_START_YEAR=2012 +CONFIG_STM3210E_LCD=y +CONFIG_STM3210E_R61580_DISABLE=y +CONFIG_STM32_DFU=y +CONFIG_STM32_DMA2=y +CONFIG_STM32_FSMC=y +CONFIG_STM32_JTAG_FULL_ENABLE=y +CONFIG_STM32_USART1=y +CONFIG_STM32_USART2=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f1/stm3210e-eval/configs/pm/defconfig b/boards/arm/stm32f1/stm3210e-eval/configs/pm/defconfig new file mode 100644 index 0000000000000..bf5f62f52ccec --- /dev/null +++ b/boards/arm/stm32f1/stm3210e-eval/configs/pm/defconfig @@ -0,0 +1,95 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_EXAMPLES_NXHELLO_DEFAULT_COLORS is not set +# CONFIG_EXAMPLES_NXHELLO_DEFAULT_FONT is not set +# CONFIG_EXAMPLES_NX_DEFAULT_COLORS is not set +# CONFIG_EXAMPLES_NX_DEFAULT_FONT is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_NXFONTS_DISABLE_16BPP is not set +# CONFIG_NXTK_DEFAULT_BORDERCOLORS is not set +# CONFIG_NX_DISABLE_16BPP is not set +# CONFIG_NX_PACKEDMSFIRST is not set +# CONFIG_NX_WRITEONLY is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm3210e-eval" +CONFIG_ARCH_BOARD_STM3210E_EVAL=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f1" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F103ZE=y +CONFIG_ARCH_CHIP_STM32F1=y +CONFIG_ARCH_CUSTOM_PMINIT=y +CONFIG_ARCH_IDLE_CUSTOM=y +CONFIG_ARCH_IRQBUTTONS=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=5483 +CONFIG_BUILTIN=y +CONFIG_EXAMPLES_NX=y +CONFIG_EXAMPLES_NXHELLO=y +CONFIG_EXAMPLES_NXHELLO_BGCOLOR=0x0011 +CONFIG_EXAMPLES_NXHELLO_BPP=16 +CONFIG_EXAMPLES_NXHELLO_FONTCOLOR=0xffdf +CONFIG_EXAMPLES_NXHELLO_FONTID=6 +CONFIG_EXAMPLES_NX_BGCOLOR=0x0011 +CONFIG_EXAMPLES_NX_BPP=16 +CONFIG_EXAMPLES_NX_COLOR1=0xaedc +CONFIG_EXAMPLES_NX_COLOR2=0xe7ff +CONFIG_EXAMPLES_NX_FONTCOLOR=0x0000 +CONFIG_EXAMPLES_NX_FONTID=0 +CONFIG_EXAMPLES_NX_TBCOLOR=0xd69a +CONFIG_HOST_WINDOWS=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LCD_MAXCONTRAST=100 +CONFIG_LCD_MAXPOWER=100 +CONFIG_LCD_NOGETRUN=y +CONFIG_LCD_RPORTRAIT=y +CONFIG_LINE_MAX=64 +CONFIG_MQ_MAXMSGSIZE=64 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_NX=y +CONFIG_NXFONT_SANS23X27=y +CONFIG_NXFONT_SANS28X37B=y +CONFIG_NXTK_BORDERCOLOR1=0xad55 +CONFIG_NXTK_BORDERCOLOR2=0x6b4d +CONFIG_NXTK_BORDERCOLOR3=0xdedb +CONFIG_NX_BLOCKING=y +CONFIG_NX_KBD=y +CONFIG_NX_XYINPUT_TOUCHSCREEN=y +CONFIG_PM=y +CONFIG_PM_BUTTONS=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=65536 +CONFIG_RAM_START=0x20000000 +CONFIG_RR_INTERVAL=200 +CONFIG_RTC_ALARM=y +CONFIG_RTC_FREQUENCY=16384 +CONFIG_RTC_HIRES=y +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=192 +CONFIG_SCHED_HPWORKSTACKSIZE=1024 +CONFIG_SCHED_WAITPID=y +CONFIG_STM3210E_LCD=y +CONFIG_STM3210E_LCD_BACKLIGHT=y +CONFIG_STM3210E_LCD_PWM=y +CONFIG_STM3210E_R61580_DISABLE=y +CONFIG_STM32_BKP=y +CONFIG_STM32_DFU=y +CONFIG_STM32_FSMC=y +CONFIG_STM32_JTAG_FULL_ENABLE=y +CONFIG_STM32_PWR=y +CONFIG_STM32_RTC=y +CONFIG_STM32_TIM1=y +CONFIG_STM32_USART1=y +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f1/stm3210e-eval/configs/usbmsc/defconfig b/boards/arm/stm32f1/stm3210e-eval/configs/usbmsc/defconfig new file mode 100644 index 0000000000000..862ffdecb9ea9 --- /dev/null +++ b/boards/arm/stm32f1/stm3210e-eval/configs/usbmsc/defconfig @@ -0,0 +1,55 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_MMCSD_HAVE_CARDDETECT is not set +# CONFIG_MMCSD_MMCSUPPORT is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm3210e-eval" +CONFIG_ARCH_BOARD_STM3210E_EVAL=y +CONFIG_ARCH_CHIP="stm32f1" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F103ZE=y +CONFIG_ARCH_CHIP_STM32F1=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_ARM_TOOLCHAIN_BUILDROOT=y +CONFIG_BOARDCTL=y +CONFIG_BOARD_LOOPSPERMSEC=5483 +CONFIG_INIT_ENTRYPOINT="msconn_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_MMCSD=y +CONFIG_MMCSD_SDIO=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=65536 +CONFIG_RAM_START=0x20000000 +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=192 +CONFIG_SCHED_HPWORKSTACKSIZE=1024 +CONFIG_START_DAY=30 +CONFIG_START_MONTH=11 +CONFIG_START_YEAR=2009 +CONFIG_STM32_DFU=y +CONFIG_STM32_DMA2=y +CONFIG_STM32_FSMC=y +CONFIG_STM32_JTAG_FULL_ENABLE=y +CONFIG_STM32_SDIO=y +CONFIG_STM32_USART1=y +CONFIG_STM32_USART2=y +CONFIG_STM32_USB=y +CONFIG_SYSTEM_USBMSC=y +CONFIG_SYSTEM_USBMSC_DEVMINOR1=0 +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART1_SERIAL_CONSOLE=y +CONFIG_USBMSC=y +CONFIG_USBMSC_BULKINREQLEN=256 +CONFIG_USBMSC_BULKOUTREQLEN=256 +CONFIG_USBMSC_EPBULKIN=5 +CONFIG_USBMSC_NRDREQS=2 +CONFIG_USBMSC_NWRREQS=2 +CONFIG_USBMSC_PRODUCTSTR="USBdev Storage" +CONFIG_USBMSC_REMOVABLE=y +CONFIG_USBMSC_VERSIONNO=0x0399 diff --git a/boards/arm/stm32f1/stm3210e-eval/configs/usbserial/defconfig b/boards/arm/stm32f1/stm3210e-eval/configs/usbserial/defconfig new file mode 100644 index 0000000000000..0fda54afcae8a --- /dev/null +++ b/boards/arm/stm32f1/stm3210e-eval/configs/usbserial/defconfig @@ -0,0 +1,41 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm3210e-eval" +CONFIG_ARCH_BOARD_STM3210E_EVAL=y +CONFIG_ARCH_CHIP="stm32f1" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F103ZE=y +CONFIG_ARCH_CHIP_STM32F1=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_ARM_TOOLCHAIN_BUILDROOT_OABI=y +CONFIG_BOARDCTL=y +CONFIG_BOARD_LOOPSPERMSEC=5483 +CONFIG_DISABLE_MOUNTPOINT=y +CONFIG_EXAMPLES_USBSERIAL=y +CONFIG_INIT_ENTRYPOINT="usbserial_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_PL2303=y +CONFIG_PL2303_PRODUCTSTR="USBdev Serial" +CONFIG_PL2303_RXBUFSIZE=512 +CONFIG_PL2303_TXBUFSIZE=512 +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=65536 +CONFIG_RAM_START=0x20000000 +CONFIG_RR_INTERVAL=200 +CONFIG_START_DAY=23 +CONFIG_START_MONTH=10 +CONFIG_START_YEAR=2009 +CONFIG_STM32_DFU=y +CONFIG_STM32_FSMC=y +CONFIG_STM32_JTAG_FULL_ENABLE=y +CONFIG_STM32_USART1=y +CONFIG_STM32_USART2=y +CONFIG_STM32_USB=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f1/stm3210e-eval/include/board.h b/boards/arm/stm32f1/stm3210e-eval/include/board.h new file mode 100644 index 0000000000000..ad0c8628d22e4 --- /dev/null +++ b/boards/arm/stm32f1/stm3210e-eval/include/board.h @@ -0,0 +1,402 @@ +/**************************************************************************** + * boards/arm/stm32f1/stm3210e-eval/include/board.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_STM32_STM3210E_EVAL_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32_STM3210E_EVAL_INCLUDE_BOARD_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#ifndef __ASSEMBLY__ +# include +#endif + +/* Logic in arch/arm/src and boards/ may need to include these file prior to + * including board.h: stm32_rcc.h, stm32_sdio.h, stm32.h. They cannot be + * included here because board.h is used in other contexts where the STM32 + * internal header files are not available. + */ + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Clocking *****************************************************************/ + +/* On-board crystal frequency is 8MHz (HSE) */ + +#define STM32_BOARD_XTAL 8000000ul + +/* PLL source is HSE/1, PLL multiplier is 9: + * PLL frequency is 8MHz (XTAL) x 9 = 72MHz + */ + +#define STM32_CFGR_PLLSRC RCC_CFGR_PLLSRC +#define STM32_CFGR_PLLXTPRE 0 +#define STM32_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx9 +#define STM32_PLL_FREQUENCY (9*STM32_BOARD_XTAL) + +/* Use the PLL and set the SYSCLK source to be the PLL */ + +#define STM32_SYSCLK_SW RCC_CFGR_SW_PLL +#define STM32_SYSCLK_SWS RCC_CFGR_SWS_PLL +#define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY + +/* AHB clock (HCLK) is SYSCLK (72MHz) */ + +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK +#define STM32_HCLK_FREQUENCY STM32_PLL_FREQUENCY + +/* APB2 clock (PCLK2) is HCLK (72MHz) */ + +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK +#define STM32_PCLK2_FREQUENCY STM32_HCLK_FREQUENCY +#define STM32_APB2_CLKIN (STM32_PCLK2_FREQUENCY) /* Timers 2-7, 12-14 */ + +/* APB2 timers 1 and 8 will receive PCLK2. */ + +#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) + +/* APB1 clock (PCLK1) is HCLK/2 (36MHz) */ + +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd2 +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/2) + +/* APB1 timers 2-7 will be twice PCLK1 */ + +#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) + +/* USB divider -- Divide PLL clock by 1.5 */ + +#define STM32_CFGR_USBPRE 0 + +/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx + * otherwise frequency is 2xAPBx. + * Note: TIM1,8 are on APB2, others on APB1 + */ + +#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM2_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM3_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM4_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM5_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM6_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM7_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY + +/* SDIO dividers. Note that slower clocking is required when DMA is disabled + * in order to avoid RX overrun/TX underrun errors due to delayed responses + * to service FIFOs in interrupt driven mode. These values have not been + * tuned!!! + * + * HCLK=72MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(178+2)=400 KHz + */ + +#define SDIO_INIT_CLKDIV (178 << SDIO_CLKCR_CLKDIV_SHIFT) + +/* DMA ON: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(2+2)=18 MHz + * DMA OFF: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(3+2)=14.4 MHz + */ + +#ifdef CONFIG_SDIO_DMA +# define SDIO_MMCXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT) +#else +# define SDIO_MMCXFR_CLKDIV (3 << SDIO_CLKCR_CLKDIV_SHIFT) +#endif + +/* DMA ON: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(1+2)=24 MHz + * DMA OFF: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(3+2)=14.4 MHz + */ + +#ifdef CONFIG_SDIO_DMA +# define SDIO_SDXFR_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT) +#else +# define SDIO_SDXFR_CLKDIV (3 << SDIO_CLKCR_CLKDIV_SHIFT) +#endif + +/* SRAM definitions *********************************************************/ + +/* The 8 Mbit SRAM is provided on the PT3 board using the FSMC_NE3 chip + * select. + */ + +/* This is the Bank1 SRAM3 address: */ + +#define BOARD_SRAM_BASE 0x68000000 /* Bank2 SRAM3 base address */ +#define BOARD_SRAM_SIZE (1*1024*1024) /* 8-Mbit = 1-Mbyte */ + +/* LED definitions **********************************************************/ + +/* The STM3210E-EVAL board has 4 LEDs that we will encode as: */ + +#define LED_STARTED 0 /* LED1 */ +#define LED_HEAPALLOCATE 1 /* LED2 */ +#define LED_IRQSENABLED 2 /* LED1 + LED2 */ +#define LED_STACKCREATED 3 /* LED3 */ +#define LED_INIRQ 4 /* LED1 + LED3 */ +#define LED_SIGNAL 5 /* LED2 + LED3 */ +#define LED_ASSERTION 6 /* LED1 + LED2 + LED3 */ +#define LED_PANIC 7 /* N/C + N/C + N/C + LED4 */ + +/* The STM3210E-EVAL supports several buttons + * + * Reset -- Connected to NRST + * Wakeup -- Connected to PA.0 + * Tamper -- Connected to PC.13 + * Key -- Connected to PG.8 + * + * And a Joystick + * + * Joystick center -- Connected to PG.7 + * Joystick down -- Connected to PD.3 + * Joystick left -- Connected to PG.14 + * Joystick right -- Connected to PG.13 + * Joystick up -- Connected to PG.15 + * + * The Joystick is treated like the other buttons unless + * CONFIG_INPUT_DJOYSTICK is defined, then it is assumed that they should be + * used by the discrete joystick driver. + */ + +#define BUTTON_WAKEUP 0 +#define BUTTON_TAMPER 1 +#define BUTTON_KEY 2 + +#ifdef CONFIG_INPUT_DJOYSTICK +# define NUM_BUTTONS 3 +#else +# define JOYSTICK_SEL 3 +# define JOYSTICK_DOWN 4 +# define JOYSTICK_LEFT 5 +# define JOYSTICK_RIGHT 6 +# define JOYSTICK_UP 7 + +# define NUM_BUTTONS 8 +#endif + +#define BUTTON_WAKEUP_BIT (1 << BUTTON_WAKEUP) +#define BUTTON_TAMPER_BIT (1 << BUTTON_TAMPER) +#define BUTTON_KEY_BIT (1 << BUTTON_KEY) + +#ifndef CONFIG_INPUT_DJOYSTICK +# define JOYSTICK_SEL_BIT (1 << JOYSTICK_SEL) +# define JOYSTICK_DOWN_BIT (1 << JOYSTICK_DOWN) +# define JOYSTICK_LEFT_BIT (1 << JOYSTICK_LEFT) +# define JOYSTICK_RIGHT_BIT (1 << JOYSTICK_RIGHT) +# define JOYSTICK_UP_BIT (1 << JOYSTICK_UP) +#endif + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: stm3210e_lcdclear + * + * Description: + * This is a non-standard LCD interface just for the STM3210E-EVAL board. + * Because of the various rotations, clearing the display in the normal + * way by writing a sequences of runs that covers the entire display can + * be very slow. Here the display is cleared by simply setting all GRAM + * memory to the specified color. + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_FSMC +void stm3210e_lcdclear(uint16_t color); +#endif + +/**************************************************************************** + * Name: stm32_lm75initialize + * + * Description: + * Initialize and register the LM-75 Temperature Sensor driver. + * + * Input Parameters: + * devpath - The full path to the driver to register. E.g., "/dev/temp0" + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +#if defined(CONFIG_I2C) && defined(CONFIG_LM75_I2C) && defined(CONFIG_STM32_I2C1) +int stm32_lm75initialize(const char *devpath); +#endif + +/**************************************************************************** + * Name: stm32_lm75attach + * + * Description: + * Attach the LM-75 interrupt handler + * + * Input Parameters: + * irqhandler - the LM-75 interrupt handler + * arg - The argument that will accompany the interrupt + * + * Returned Value: + * Zero (OK) returned on success; a negated errno value is returned on + * failure. + * + ****************************************************************************/ + +#if defined(CONFIG_I2C) && defined(CONFIG_LM75_I2C) && defined(CONFIG_STM32_I2C1) +int stm32_lm75attach(xcpt_t irqhandler, void *arg); +#endif + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ + +/* Alternate function pin selections (auto-aliased for new pinmap) */ + +/* USART1 */ + +#define GPIO_USART1_TX GPIO_ADJUST_MODE(GPIO_USART1_TX_0, GPIO_MODE_50MHz) +#define GPIO_USART1_RX GPIO_USART1_RX_0 + +/* USART2 */ + +#define GPIO_USART2_TX GPIO_ADJUST_MODE(GPIO_USART2_TX_0, GPIO_MODE_50MHz) +#define GPIO_USART2_RX GPIO_USART2_RX_0 +#define GPIO_USART2_CTS GPIO_USART2_CTS_0 +#define GPIO_USART2_RTS GPIO_ADJUST_MODE(GPIO_USART2_RTS_0, GPIO_MODE_50MHz) +#define GPIO_USART2_CK GPIO_ADJUST_MODE(GPIO_USART2_CK_0, GPIO_MODE_50MHz) + +/* I2C1 */ + +#define GPIO_I2C1_SCL GPIO_ADJUST_MODE(GPIO_I2C1_SCL_0, GPIO_MODE_50MHz) +#define GPIO_I2C1_SDA GPIO_ADJUST_MODE(GPIO_I2C1_SDA_0, GPIO_MODE_50MHz) + +/* SPI1 */ + +#define GPIO_SPI1_NSS GPIO_ADJUST_MODE(GPIO_SPI1_NSS_0, GPIO_MODE_50MHz) +#define GPIO_SPI1_SCK GPIO_ADJUST_MODE(GPIO_SPI1_SCK_0, GPIO_MODE_50MHz) +#define GPIO_SPI1_MISO GPIO_ADJUST_MODE(GPIO_SPI1_MISO_0, GPIO_MODE_50MHz) +#define GPIO_SPI1_MOSI GPIO_ADJUST_MODE(GPIO_SPI1_MOSI_0, GPIO_MODE_50MHz) + +/* USB */ + +#define GPIO_USB_DM GPIO_USB_DM_0 +#define GPIO_USB_DP GPIO_USB_DP_0 + +/* SDIO */ + +#define GPIO_SDIO_CK GPIO_ADJUST_MODE(GPIO_SDIO_CK_0, GPIO_MODE_50MHz) +#define GPIO_SDIO_CMD GPIO_ADJUST_MODE(GPIO_SDIO_CMD_0, GPIO_MODE_50MHz) +#define GPIO_SDIO_D0 GPIO_ADJUST_MODE(GPIO_SDIO_D0_0, GPIO_MODE_50MHz) +#define GPIO_SDIO_D1 GPIO_ADJUST_MODE(GPIO_SDIO_D1_0, GPIO_MODE_50MHz) +#define GPIO_SDIO_D2 GPIO_ADJUST_MODE(GPIO_SDIO_D2_0, GPIO_MODE_50MHz) +#define GPIO_SDIO_D3 GPIO_ADJUST_MODE(GPIO_SDIO_D3_0, GPIO_MODE_50MHz) + +/* TIM1 */ + +#define GPIO_TIM1_CH1IN GPIO_TIM1_CH1IN_0 +#define GPIO_TIM1_CH1OUT GPIO_ADJUST_MODE(GPIO_TIM1_CH1OUT_0, GPIO_MODE_50MHz) +#define GPIO_TIM1_CH2IN GPIO_TIM1_CH2IN_0 +#define GPIO_TIM1_CH2OUT GPIO_ADJUST_MODE(GPIO_TIM1_CH2OUT_0, GPIO_MODE_50MHz) +#define GPIO_TIM1_CH3IN GPIO_TIM1_CH3IN_0 +#define GPIO_TIM1_CH3OUT GPIO_ADJUST_MODE(GPIO_TIM1_CH3OUT_0, GPIO_MODE_50MHz) +#define GPIO_TIM1_CH4IN GPIO_TIM1_CH4IN_0 +#define GPIO_TIM1_CH4OUT GPIO_ADJUST_MODE(GPIO_TIM1_CH4OUT_0, GPIO_MODE_50MHz) +#define GPIO_TIM1_BKIN GPIO_TIM1_BKIN_0 +#define GPIO_TIM1_ETR GPIO_TIM1_ETR_0 +#define GPIO_TIM1_CH1NOUT GPIO_ADJUST_MODE(GPIO_TIM1_CH1NOUT_0, GPIO_MODE_50MHz) +#define GPIO_TIM1_CH2NOUT GPIO_ADJUST_MODE(GPIO_TIM1_CH2NOUT_0, GPIO_MODE_50MHz) +#define GPIO_TIM1_CH3NOUT GPIO_ADJUST_MODE(GPIO_TIM1_CH3NOUT_0, GPIO_MODE_50MHz) + +/* FSMC NPS pins (used by board srcs) */ + +#define GPIO_NPS_A0 GPIO_ADJUST_MODE(GPIO_NPS_A0_0, GPIO_MODE_50MHz) +#define GPIO_NPS_A1 GPIO_ADJUST_MODE(GPIO_NPS_A1_0, GPIO_MODE_50MHz) +#define GPIO_NPS_A10 GPIO_ADJUST_MODE(GPIO_NPS_A10_0, GPIO_MODE_50MHz) +#define GPIO_NPS_A11 GPIO_ADJUST_MODE(GPIO_NPS_A11_0, GPIO_MODE_50MHz) +#define GPIO_NPS_A12 GPIO_ADJUST_MODE(GPIO_NPS_A12_0, GPIO_MODE_50MHz) +#define GPIO_NPS_A13 GPIO_ADJUST_MODE(GPIO_NPS_A13_0, GPIO_MODE_50MHz) +#define GPIO_NPS_A14 GPIO_ADJUST_MODE(GPIO_NPS_A14_0, GPIO_MODE_50MHz) +#define GPIO_NPS_A15 GPIO_ADJUST_MODE(GPIO_NPS_A15_0, GPIO_MODE_50MHz) +#define GPIO_NPS_A16 GPIO_ADJUST_MODE(GPIO_NPS_A16_0, GPIO_MODE_50MHz) +#define GPIO_NPS_A17 GPIO_ADJUST_MODE(GPIO_NPS_A17_0, GPIO_MODE_50MHz) +#define GPIO_NPS_A18 GPIO_ADJUST_MODE(GPIO_NPS_A18_0, GPIO_MODE_50MHz) +#define GPIO_NPS_A19 GPIO_ADJUST_MODE(GPIO_NPS_A19_0, GPIO_MODE_50MHz) +#define GPIO_NPS_A2 GPIO_ADJUST_MODE(GPIO_NPS_A2_0, GPIO_MODE_50MHz) +#define GPIO_NPS_A20 GPIO_ADJUST_MODE(GPIO_NPS_A20_0, GPIO_MODE_50MHz) +#define GPIO_NPS_A21 GPIO_ADJUST_MODE(GPIO_NPS_A21_0, GPIO_MODE_50MHz) +#define GPIO_NPS_A22 GPIO_ADJUST_MODE(GPIO_NPS_A22_0, GPIO_MODE_50MHz) +#define GPIO_NPS_A3 GPIO_ADJUST_MODE(GPIO_NPS_A3_0, GPIO_MODE_50MHz) +#define GPIO_NPS_A4 GPIO_ADJUST_MODE(GPIO_NPS_A4_0, GPIO_MODE_50MHz) +#define GPIO_NPS_A5 GPIO_ADJUST_MODE(GPIO_NPS_A5_0, GPIO_MODE_50MHz) +#define GPIO_NPS_A6 GPIO_ADJUST_MODE(GPIO_NPS_A6_0, GPIO_MODE_50MHz) +#define GPIO_NPS_A7 GPIO_ADJUST_MODE(GPIO_NPS_A7_0, GPIO_MODE_50MHz) +#define GPIO_NPS_A8 GPIO_ADJUST_MODE(GPIO_NPS_A8_0, GPIO_MODE_50MHz) +#define GPIO_NPS_A9 GPIO_ADJUST_MODE(GPIO_NPS_A9_0, GPIO_MODE_50MHz) +#define GPIO_NPS_D0 GPIO_ADJUST_MODE(GPIO_NPS_D0_0, GPIO_MODE_50MHz) +#define GPIO_NPS_D1 GPIO_ADJUST_MODE(GPIO_NPS_D1_0, GPIO_MODE_50MHz) +#define GPIO_NPS_D10 GPIO_ADJUST_MODE(GPIO_NPS_D10_0, GPIO_MODE_50MHz) +#define GPIO_NPS_D11 GPIO_ADJUST_MODE(GPIO_NPS_D11_0, GPIO_MODE_50MHz) +#define GPIO_NPS_D12 GPIO_ADJUST_MODE(GPIO_NPS_D12_0, GPIO_MODE_50MHz) +#define GPIO_NPS_D13 GPIO_ADJUST_MODE(GPIO_NPS_D13_0, GPIO_MODE_50MHz) +#define GPIO_NPS_D14 GPIO_ADJUST_MODE(GPIO_NPS_D14_0, GPIO_MODE_50MHz) +#define GPIO_NPS_D15 GPIO_ADJUST_MODE(GPIO_NPS_D15_0, GPIO_MODE_50MHz) +#define GPIO_NPS_D2 GPIO_ADJUST_MODE(GPIO_NPS_D2_0, GPIO_MODE_50MHz) +#define GPIO_NPS_D3 GPIO_ADJUST_MODE(GPIO_NPS_D3_0, GPIO_MODE_50MHz) +#define GPIO_NPS_D4 GPIO_ADJUST_MODE(GPIO_NPS_D4_0, GPIO_MODE_50MHz) +#define GPIO_NPS_D5 GPIO_ADJUST_MODE(GPIO_NPS_D5_0, GPIO_MODE_50MHz) +#define GPIO_NPS_D6 GPIO_ADJUST_MODE(GPIO_NPS_D6_0, GPIO_MODE_50MHz) +#define GPIO_NPS_D7 GPIO_ADJUST_MODE(GPIO_NPS_D7_0, GPIO_MODE_50MHz) +#define GPIO_NPS_D8 GPIO_ADJUST_MODE(GPIO_NPS_D8_0, GPIO_MODE_50MHz) +#define GPIO_NPS_D9 GPIO_ADJUST_MODE(GPIO_NPS_D9_0, GPIO_MODE_50MHz) +#define GPIO_NPS_NBL0 GPIO_ADJUST_MODE(GPIO_NPS_NBL0_0, GPIO_MODE_50MHz) +#define GPIO_NPS_NBL1 GPIO_ADJUST_MODE(GPIO_NPS_NBL1_0, GPIO_MODE_50MHz) +#define GPIO_NPS_NE2 GPIO_ADJUST_MODE(GPIO_NPS_NE2_0, GPIO_MODE_50MHz) +#define GPIO_NPS_NE3 GPIO_ADJUST_MODE(GPIO_NPS_NE3_0, GPIO_MODE_50MHz) +#define GPIO_NPS_NE4 GPIO_ADJUST_MODE(GPIO_NPS_NE4_0, GPIO_MODE_50MHz) +#define GPIO_NPS_NOE GPIO_ADJUST_MODE(GPIO_NPS_NOE_0, GPIO_MODE_50MHz) +#define GPIO_NPS_NWE GPIO_ADJUST_MODE(GPIO_NPS_NWE_0, GPIO_MODE_50MHz) + +#endif /* __BOARDS_ARM_STM32_STM3210E_EVAL_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32f1/stm3210e-eval/scripts/Make.defs b/boards/arm/stm32f1/stm3210e-eval/scripts/Make.defs new file mode 100644 index 0000000000000..42002bd0d2967 --- /dev/null +++ b/boards/arm/stm32f1/stm3210e-eval/scripts/Make.defs @@ -0,0 +1,46 @@ +############################################################################ +# boards/arm/stm32f1/stm3210e-eval/scripts/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/.config +include $(TOPDIR)/tools/Config.mk +include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs + +ifeq ($(CONFIG_STM32_DFU),y) + LDSCRIPT = ld.script.dfu +else + LDSCRIPT = ld.script +endif + +ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) + +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32f1/stm3210e-eval/scripts/ld.script b/boards/arm/stm32f1/stm3210e-eval/scripts/ld.script new file mode 100644 index 0000000000000..0f14faebace94 --- /dev/null +++ b/boards/arm/stm32f1/stm3210e-eval/scripts/ld.script @@ -0,0 +1,122 @@ +/**************************************************************************** + * boards/arm/stm32f1/stm3210e-eval/scripts/ld.script + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* The STM32F103ZET6 has 512Kb of FLASH beginning at address 0x0800:0000 and + * 64Kb of SRAM beginning at address 0x2000:0000. When booting from FLASH, + * FLASH memory is aliased to address 0x0000:0000 where the code expects to + * begin execution by jumping to the entry point in the 0x0800:0000 address + * range. + */ + +MEMORY +{ + flash (rx) : ORIGIN = 0x08000000, LENGTH = 512K + sram (rwx) : ORIGIN = 0x20000000, LENGTH = 64K +} + +OUTPUT_ARCH(arm) +EXTERN(_vectors) +ENTRY(_stext) +SECTIONS +{ + .text : { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > flash + + .init_section : ALIGN(4) { + _sinit = ABSOLUTE(.); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) + _einit = ABSOLUTE(.); + } > flash + + .ARM.extab : ALIGN(4) { + *(.ARM.extab*) + } > flash + + .ARM.exidx : ALIGN(4) { + __exidx_start = ABSOLUTE(.); + *(.ARM.exidx*) + __exidx_end = ABSOLUTE(.); + } > flash + + .tdata : { + _stdata = ABSOLUTE(.); + *(.tdata .tdata.* .gnu.linkonce.td.*); + _etdata = ABSOLUTE(.); + } > flash + + .tbss : { + _stbss = ABSOLUTE(.); + *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); + _etbss = ABSOLUTE(.); + } > flash + + _eronly = ABSOLUTE(.); + + /* The STM32F103Z has 64Kb of SRAM beginning at the following address */ + + .data : ALIGN(4) { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > sram AT > flash + + .bss : ALIGN(4) { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + _ebss = ABSOLUTE(.); + } > sram + + /* Stabs debugging sections. */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/stm32f1/stm3210e-eval/scripts/ld.script.dfu b/boards/arm/stm32f1/stm3210e-eval/scripts/ld.script.dfu new file mode 100644 index 0000000000000..1a8c3f20a865e --- /dev/null +++ b/boards/arm/stm32f1/stm3210e-eval/scripts/ld.script.dfu @@ -0,0 +1,118 @@ +/**************************************************************************** + * boards/arm/stm32f1/stm3210e-eval/scripts/ld.script.dfu + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* The STM32F103ZET6 has 512Kb of FLASH beginning at address 0x0800:0000 and + * 64Kb of SRAM beginning at address 0x2000:0000. Here we assume that the + * STM3210E-EVAL's DFU bootloader is being used. In that case, the correct + * load .text load address is 0x08003000 (leaving 464Kb). + */ + +MEMORY +{ + flash (rx) : ORIGIN = 0x08003000, LENGTH = 464K + sram (rwx) : ORIGIN = 0x20000000, LENGTH = 64K +} + +OUTPUT_ARCH(arm) +EXTERN(_vectors) +ENTRY(_stext) +SECTIONS +{ + .text : { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > flash + + .init_section : ALIGN(4) { + _sinit = ABSOLUTE(.); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) + _einit = ABSOLUTE(.); + } > flash + + .ARM.extab : ALIGN(4) { + *(.ARM.extab*) + } > flash + + .ARM.exidx : ALIGN(4) { + __exidx_start = ABSOLUTE(.); + *(.ARM.exidx*) + __exidx_end = ABSOLUTE(.); + } > flash + + .tdata : { + _stdata = ABSOLUTE(.); + *(.tdata .tdata.* .gnu.linkonce.td.*); + _etdata = ABSOLUTE(.); + } > flash + + .tbss : { + _stbss = ABSOLUTE(.); + *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); + _etbss = ABSOLUTE(.); + } > flash + + _eronly = ABSOLUTE(.); + + /* The STM32F103Z has 64Kb of SRAM beginning at the following address */ + + .data : ALIGN(4) { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + _edata = ABSOLUTE(.); + } > sram AT > flash + + .bss : ALIGN(4) { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + _ebss = ABSOLUTE(.); + } > sram + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/stm32f1/stm3210e-eval/src/CMakeLists.txt b/boards/arm/stm32f1/stm3210e-eval/src/CMakeLists.txt new file mode 100644 index 0000000000000..34dd5c8b2858b --- /dev/null +++ b/boards/arm/stm32f1/stm3210e-eval/src/CMakeLists.txt @@ -0,0 +1,70 @@ +# ############################################################################## +# boards/arm/stm32f1/stm3210e-eval/src/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(SRCS stm32_boot.c stm32_bringup.c stm32_leds.c stm32_spi.c stm32_usbdev.c) + +if(CONFIG_STM32_FSMC) + list(APPEND SRCS stm32_lcd.c stm32_extcontext.c stm32_extmem.c + stm32_selectnor.c) + list(APPEND SRCS stm32_deselectnor.c stm32_selectsram.c stm32_deselectsram.c) + list(APPEND SRCS stm32_selectlcd.c stm32_deselectlcd.c) +endif() + +if(CONFIG_ADC) + list(APPEND SRCS stm32_adc.c) +endif() + +if(CONFIG_USBMSC) + list(APPEND SRCS stm32_usbmsc.c) +endif() + +if(CONFIG_USBDEV_COMPOSITE) + list(APPEND SRCS stm32_composite.c) +endif() + +if(CONFIG_STM32_CAN_CHARDRIVER) + list(APPEND SRCS stm32_can.c) +endif() + +if(CONFIG_ARCH_CUSTOM_PMINIT) + list(APPEND SRCS stm32_pm.c) +endif() + +if(CONFIG_ARCH_BUTTONS) + list(APPEND SRCS stm32_buttons.c) + + if(CONFIG_PM_BUTTONS) + list(APPEND SRCS stm32_pmbuttons.c) + endif() +endif() + +if(CONFIG_INPUT_DJOYSTICK) + list(APPEND SRCS stm32_djoystick.c) +endif() + +if(CONFIG_ARCH_IDLE_CUSTOM) + list(APPEND SRCS stm32_idle.c) +endif() + +target_sources(board PRIVATE ${SRCS}) + +set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/ld.script") diff --git a/boards/arm/stm32f1/stm3210e-eval/src/Make.defs b/boards/arm/stm32f1/stm3210e-eval/src/Make.defs new file mode 100644 index 0000000000000..06d9de85d5af2 --- /dev/null +++ b/boards/arm/stm32f1/stm3210e-eval/src/Make.defs @@ -0,0 +1,71 @@ +############################################################################ +# boards/arm/stm32f1/stm3210e-eval/src/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +CSRCS = stm32_boot.c stm32_bringup.c stm32_leds.c stm32_spi.c stm32_usbdev.c + +ifeq ($(CONFIG_STM32_FSMC),y) +CSRCS += stm32_lcd.c stm32_extcontext.c stm32_extmem.c stm32_selectnor.c +CSRCS += stm32_deselectnor.c stm32_selectsram.c stm32_deselectsram.c +CSRCS += stm32_selectlcd.c stm32_deselectlcd.c +endif + +ifeq ($(CONFIG_ADC),y) +CSRCS += stm32_adc.c +endif + +ifeq ($(CONFIG_USBMSC),y) +CSRCS += stm32_usbmsc.c +endif + +ifeq ($(CONFIG_USBDEV_COMPOSITE),y) +CSRCS += stm32_composite.c +endif + +ifeq ($(CONFIG_STM32_CAN_CHARDRIVER),y) +CSRCS += stm32_can.c +endif + +ifeq ($(CONFIG_ARCH_CUSTOM_PMINIT),y) +CSRCS += stm32_pm.c +endif + +ifeq ($(CONFIG_ARCH_BUTTONS),y) +CSRCS += stm32_buttons.c + +ifeq ($(CONFIG_PM_BUTTONS),y) +CSRCS += stm32_pmbuttons.c +endif +endif + +ifeq ($(CONFIG_INPUT_DJOYSTICK),y) +CSRCS += stm32_djoystick.c +endif + +ifeq ($(CONFIG_ARCH_IDLE_CUSTOM),y) +CSRCS += stm32_idle.c +endif + +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/stm3210e-eval/src/stm3210e-eval.h b/boards/arm/stm32f1/stm3210e-eval/src/stm3210e-eval.h similarity index 99% rename from boards/arm/stm32/stm3210e-eval/src/stm3210e-eval.h rename to boards/arm/stm32f1/stm3210e-eval/src/stm3210e-eval.h index 0f56d7a932858..f97c09d7bf257 100644 --- a/boards/arm/stm32/stm3210e-eval/src/stm3210e-eval.h +++ b/boards/arm/stm32f1/stm3210e-eval/src/stm3210e-eval.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm3210e-eval/src/stm3210e-eval.h + * boards/arm/stm32f1/stm3210e-eval/src/stm3210e-eval.h * * SPDX-License-Identifier: Apache-2.0 * @@ -32,7 +32,7 @@ #include -#include +#include #include "stm32_gpio.h" diff --git a/boards/arm/stm32f1/stm3210e-eval/src/stm32_adc.c b/boards/arm/stm32f1/stm3210e-eval/src/stm32_adc.c new file mode 100644 index 0000000000000..dca12d9b1b80f --- /dev/null +++ b/boards/arm/stm32f1/stm3210e-eval/src/stm32_adc.c @@ -0,0 +1,153 @@ +/**************************************************************************** + * boards/arm/stm32f1/stm3210e-eval/src/stm32_adc.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32_pwm.h" +#include "stm3210e-eval.h" + +#ifdef CONFIG_ADC + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* Up to 3 ADC interfaces are supported */ + +#if STM32_NADC < 3 +# undef CONFIG_STM32_ADC3 +#endif + +#if STM32_NADC < 2 +# undef CONFIG_STM32_ADC2 +#endif + +#if STM32_NADC < 1 +# undef CONFIG_STM32_ADC1 +#endif + +#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) || defined(CONFIG_STM32_ADC3) +#ifndef CONFIG_STM32_ADC1 +# warning "Channel information only available for ADC1" +#endif + +/* The number of ADC channels in the conversion list */ + +#define ADC1_NCHANNELS 1 + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* Identifying number of each ADC channel: Variable Resistor */ + +#ifdef CONFIG_STM32_ADC1 +static const uint8_t g_chanlist[ADC1_NCHANNELS] = +{ + 14 +}; + +/* Configurations of pins used byte each ADC channels */ + +static const uint32_t g_pinlist[ADC1_NCHANNELS] = +{ + GPIO_ADC1_IN14 +}; +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_adc_setup + * + * Description: + * Initialize ADC and register the ADC driver. + * + ****************************************************************************/ + +int stm32_adc_setup(void) +{ +#ifdef CONFIG_STM32_ADC1 + static bool initialized = false; + struct adc_dev_s *adc; + int ret; + int i; + + /* Check if we have already initialized */ + + if (!initialized) + { + /* Configure the pins as analog inputs for the selected channels */ + + for (i = 0; i < ADC1_NCHANNELS; i++) + { + stm32_configgpio(g_pinlist[i]); + } + + /* Call stm32_adcinitialize() to get an instance of the ADC interface */ + + adc = stm32_adcinitialize(1, g_chanlist, ADC1_NCHANNELS); + if (adc == NULL) + { + aerr("ERROR: Failed to get ADC interface\n"); + return -ENODEV; + } + + /* Register the ADC driver at "/dev/adc0" */ + + ret = adc_register("/dev/adc0", adc); + if (ret < 0) + { + aerr("ERROR: adc_register failed: %d\n", ret); + return ret; + } + + /* Now we are initialized */ + + initialized = true; + } + + return OK; +#else + return -ENOSYS; +#endif +} + +#endif /* CONFIG_STM32_ADC1 || CONFIG_STM32_ADC2 || CONFIG_STM32_ADC3 */ +#endif /* CONFIG_ADC */ diff --git a/boards/arm/stm32f1/stm3210e-eval/src/stm32_boot.c b/boards/arm/stm32f1/stm3210e-eval/src/stm32_boot.c new file mode 100644 index 0000000000000..cb9730521db75 --- /dev/null +++ b/boards/arm/stm32f1/stm3210e-eval/src/stm32_boot.c @@ -0,0 +1,118 @@ +/**************************************************************************** + * boards/arm/stm32f1/stm3210e-eval/src/stm32_boot.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include +#include + +#include "arm_internal.h" +#include "stm3210e-eval.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_boardinitialize + * + * Description: + * All STM32 architectures must provide the following entry point. + * This entry point is called early in the initialization -- after all + * memory has been configured and mapped but before any devices have been + * initialized. + * + ****************************************************************************/ + +void stm32_boardinitialize(void) +{ + /* If the FSMC and external RAM are selected, then enable SRAM access */ + +#if defined(CONFIG_STM32_FSMC) && defined(CONFIG_STM32_EXTERNAL_RAM) + stm32_selectsram(); +#endif + + /* Configure SPI chip selects if 1) SPI is not disabled, and 2) the weak + * function stm32_spidev_initialize() has been brought into the link. + */ + +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) + if (stm32_spidev_initialize) + { + stm32_spidev_initialize(); + } +#endif + + /* Initialize USB is 1) USBDEV is selected, 2) the USB controller is not + * disabled, and 3) the weak function stm32_usbinitialize() has been + * brought into the build. + */ + +#if defined(CONFIG_USBDEV) && defined(CONFIG_STM32_USB) + if (stm32_usbinitialize) + { + stm32_usbinitialize(); + } +#endif + + /* Configure on-board LEDs if LED support has been selected. */ + +#ifdef CONFIG_ARCH_LEDS + board_autoled_initialize(); +#endif +} + +/**************************************************************************** + * Name: board_late_initialize + * + * Description: + * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_late_initialize(). board_late_initialize() will be + * called immediately after up_initialize() is called and just before the + * initial application is started. This additional initialization phase + * may be used, for example, to initialize board-specific device drivers. + * + ****************************************************************************/ + +#ifdef CONFIG_BOARD_LATE_INITIALIZE +void board_late_initialize(void) +{ + /* Perform board-specific initialization */ + + stm32_bringup(); +} +#endif diff --git a/boards/arm/stm32f1/stm3210e-eval/src/stm32_bringup.c b/boards/arm/stm32f1/stm3210e-eval/src/stm32_bringup.c new file mode 100644 index 0000000000000..45beb076a2658 --- /dev/null +++ b/boards/arm/stm32f1/stm3210e-eval/src/stm32_bringup.c @@ -0,0 +1,317 @@ +/**************************************************************************** + * boards/arm/stm32f1/stm3210e-eval/src/stm32_bringup.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include + +#ifdef CONFIG_STM32_SPI1 +# include +# include +#endif + +#ifdef CONFIG_STM32_SDIO +# include +# include +#endif + +#ifdef CONFIG_VIDEO_FB +# include +#endif + +#include "stm32.h" +#include "stm32_i2c.h" +#include "stm3210e-eval.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* For now, don't build in any SPI1 support -- NSH is not using it */ + +#undef CONFIG_STM32_SPI1 + +/* PORT and SLOT number probably depend on the board configuration */ + +#ifdef CONFIG_ARCH_BOARD_STM3210E_EVAL +# define NSH_HAVEUSBDEV 1 +# define NSH_HAVEMMCSD 1 +# if defined(CONFIG_NSH_MMCSDSLOTNO) && CONFIG_NSH_MMCSDSLOTNO != 0 +# error "Only one MMC/SD slot" +# undef CONFIG_NSH_MMCSDSLOTNO +# endif +# ifndef CONFIG_NSH_MMCSDSLOTNO +# define CONFIG_NSH_MMCSDSLOTNO 0 +# endif +#else + +/* Add configuration for new STM32 boards here */ + +# error "Unrecognized STM32 board" +# undef NSH_HAVEUSBDEV +# undef NSH_HAVEMMCSD +#endif + +/* Can't support USB features if USB is not enabled */ + +#ifndef CONFIG_USBDEV +# undef NSH_HAVEUSBDEV +#endif + +/* Can't support MMC/SD features if mountpoints are disabled or if SDIO + * support is not enabled. + */ + +#if defined(CONFIG_DISABLE_MOUNTPOINT) || !defined(CONFIG_STM32_SDIO) +# undef NSH_HAVEMMCSD +#endif + +#ifndef CONFIG_NSH_MMCSDMINOR +# define CONFIG_NSH_MMCSDMINOR 0 +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_i2c_register + * + * Description: + * Register one I2C drivers for the I2C tool. + * + ****************************************************************************/ + +#ifdef HAVE_I2CTOOL +static void stm32_i2c_register(int bus) +{ + struct i2c_master_s *i2c; + int ret; + + i2c = stm32_i2cbus_initialize(bus); + if (i2c == NULL) + { + _err("ERROR: Failed to get I2C%d interface\n", bus); + } + else + { + ret = i2c_register(i2c, bus); + if (ret < 0) + { + _err("ERROR: Failed to register I2C%d driver: %d\n", bus, ret); + stm32_i2cbus_uninitialize(i2c); + } + } +} +#endif + +/**************************************************************************** + * Name: stm32_i2ctool + * + * Description: + * Register I2C drivers for the I2C tool. + * + ****************************************************************************/ + +#ifdef HAVE_I2CTOOL +static void stm32_i2ctool(void) +{ +#ifdef CONFIG_STM32_I2C1 + stm32_i2c_register(1); +#endif +#ifdef CONFIG_STM32_I2C2 + stm32_i2c_register(2); +#endif +#ifdef CONFIG_STM32_I2C3 + stm32_i2c_register(3); +#endif +} +#else +# define stm32_i2ctool() +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_bringup + * + * Description: + * Perform architecture-specific initialization + * + * CONFIG_BOARD_LATE_INITIALIZE=y : + * Called from board_late_initialize(). + * + ****************************************************************************/ + +int stm32_bringup(void) +{ +#ifdef CONFIG_STM32_SPI1 + struct spi_dev_s *spi; + struct mtd_dev_s *mtd; +#endif +#ifdef NSH_HAVEMMCSD + struct sdio_dev_s *sdio; +#endif + int ret; + + /* Register I2C drivers on behalf of the I2C tool */ + + stm32_i2ctool(); + + /* Configure SPI-based devices */ + +#ifdef CONFIG_STM32_SPI1 + /* Get the SPI port */ + + syslog(LOG_INFO, "Initializing SPI port 1\n"); + spi = stm32_spibus_initialize(1); + if (!spi) + { + syslog(LOG_ERR, "ERROR: Failed to initialize SPI port 1\n"); + return -ENODEV; + } + + syslog(LOG_INFO, "Successfully initialized SPI port 1\n"); + + /* Now bind the SPI interface to the M25P64/128 SPI FLASH driver */ + + syslog(LOG_INFO, "Bind SPI to the SPI flash driver\n"); + + mtd = m25p_initialize(spi); + if (!mtd) + { + syslog(LOG_ERR, + "ERROR: Failed to bind SPI port 0 to the SPI FLASH driver\n"); + return -ENODEV; + } + + syslog(LOG_INFO, + "Successfully bound SPI port 0 to the SPI FLASH driver\n"); +#warning "Now what are we going to do with this SPI FLASH driver?" +#endif + + /* Create the SPI FLASH MTD instance */ + + /* The M25Pxx is not a give media to implement a file system.. + * its block sizes are too large + */ + + /* Mount the SDIO-based MMC/SD block driver */ + +#ifdef NSH_HAVEMMCSD + /* First, get an instance of the SDIO interface */ + + syslog(LOG_INFO, "Initializing SDIO slot %d\n", + CONFIG_NSH_MMCSDSLOTNO); + + sdio = sdio_initialize(CONFIG_NSH_MMCSDSLOTNO); + if (!sdio) + { + syslog(LOG_ERR, "ERROR: Failed to initialize SDIO slot %d\n", + CONFIG_NSH_MMCSDSLOTNO); + return -ENODEV; + } + + /* Now bind the SDIO interface to the MMC/SD driver */ + + syslog(LOG_INFO, "Bind SDIO to the MMC/SD driver, minor=%d\n", + CONFIG_NSH_MMCSDMINOR); + + ret = mmcsd_slotinitialize(CONFIG_NSH_MMCSDMINOR, sdio); + if (ret != OK) + { + syslog(LOG_ERR, + "ERROR: Failed to bind SDIO to the MMC/SD driver: %d\n", ret); + return ret; + } + + syslog(LOG_INFO, "Successfully bound SDIO to the MMC/SD driver\n"); + + /* Then let's guess and say that there is a card in the slot. + * I need to check to see if the STM3210E-EVAL board supports a GPIO + * to detect if there is a card in the slot. + */ + + sdio_mediachange(sdio, true); +#endif + +#ifdef CONFIG_ADC + /* Initialize ADC and register the ADC driver. */ + + ret = stm32_adc_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_adc_setup failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_STM32_CAN_CHARDRIVER + /* Initialize CAN and register the CAN driver. */ + + ret = stm32_can_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_can_setup failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_VIDEO_FB + /* Initialize and register the simulated framebuffer driver */ + + ret = fb_register(0, 0); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: fb_register() failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_INPUT_DJOYSTICK + /* Initialize and register the joystick driver */ + + ret = stm32_djoy_initialization(); + if (ret != OK) + { + syslog(LOG_ERR, + "ERROR: Failed to register the joystick driver: %d\n", ret); + return ret; + } + + syslog(LOG_INFO, "Successfully registered the joystick driver\n"); +#endif + + UNUSED(ret); + return OK; +} diff --git a/boards/arm/stm32f1/stm3210e-eval/src/stm32_buttons.c b/boards/arm/stm32f1/stm3210e-eval/src/stm32_buttons.c new file mode 100644 index 0000000000000..9833133076a16 --- /dev/null +++ b/boards/arm/stm32f1/stm3210e-eval/src/stm32_buttons.c @@ -0,0 +1,171 @@ +/**************************************************************************** + * boards/arm/stm32f1/stm3210e-eval/src/stm32_buttons.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include +#include + +#include "stm32_gpio.h" +#include "stm3210e-eval.h" + +#ifdef CONFIG_ARCH_BUTTONS + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* Pin configuration for each STM3210E-EVAL button. This array is indexed by + * the BUTTON_* and JOYSTICK_* definitions in board.h + */ + +static const uint32_t g_buttons[NUM_BUTTONS] = +{ + GPIO_BTN_WAKEUP, GPIO_BTN_TAMPER, GPIO_BTN_KEY, + + /* The Joystick is treated like the other buttons unless + * CONFIG_INPUT_DJOYSTICK is defined, then it is assumed that they should + * be used by the discrete joystick driver. + */ + +#ifndef CONFIG_INPUT_DJOYSTICK + GPIO_JOY_SEL, GPIO_JOY_DOWN, GPIO_JOY_LEFT, GPIO_JOY_RIGHT, GPIO_JOY_UP +#endif +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_button_initialize + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. + * + ****************************************************************************/ + +uint32_t board_button_initialize(void) +{ + int i; + + /* Configure the GPIO pins as inputs. NOTE that EXTI interrupts are + * configured for some pins but NOT used in this file + */ + + for (i = 0; i < NUM_BUTTONS; i++) + { + stm32_configgpio(g_buttons[i]); + } + + return NUM_BUTTONS; +} + +/**************************************************************************** + * Name: board_buttons + ****************************************************************************/ + +uint32_t board_buttons(void) +{ + uint32_t ret = 0; + int i; + + /* Check that state of each key */ + + for (i = 0; i < NUM_BUTTONS; i++) + { + /* A LOW value means that the key is pressed for most keys. + * The exception is the WAKEUP button. + */ + + bool released = stm32_gpioread(g_buttons[i]); + if (i == BUTTON_WAKEUP) + { + released = !released; + } + + /* Accumulate the set of depressed (not released) keys */ + + if (!released) + { + ret |= (1 << i); + } + } + + return ret; +} + +/**************************************************************************** + * Button support. + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. + * + * After board_button_initialize() has been called, board_buttons() may be + * called to collect the state of all buttons. board_buttons() returns an + * 32-bit bit set with each bit associated with a button. See the + * BUTTON_*_BIT and JOYSTICK_*_BIT definitions in board.h for the meaning + * of each bit. + * + * board_button_irq() may be called to register an interrupt handler that + * will be called when a button is depressed or released. The ID value is a + * button enumeration value that uniquely identifies a button resource. See + * the BUTTON_* and JOYSTICK_* definitions in board.h for the meaning of + * enumeration value. + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_IRQBUTTONS +int board_button_irq(int id, xcpt_t irqhandler, void *arg) +{ + int ret = -EINVAL; + + /* The following should be atomic */ + + if (id >= MIN_IRQBUTTON && id <= MAX_IRQBUTTON) + { + ret = stm32_gpiosetevent(g_buttons[id], true, true, true, + irqhandler, arg); + } + + return ret; +} +#endif +#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/stm32f1/stm3210e-eval/src/stm32_can.c b/boards/arm/stm32f1/stm3210e-eval/src/stm32_can.c new file mode 100644 index 0000000000000..4bd62db364e7a --- /dev/null +++ b/boards/arm/stm32f1/stm3210e-eval/src/stm32_can.c @@ -0,0 +1,95 @@ +/**************************************************************************** + * boards/arm/stm32f1/stm3210e-eval/src/stm32_can.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32.h" +#include "stm32_can.h" +#include "stm3210e-eval.h" + +#ifdef CONFIG_CAN + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* The STM32F103ZE supports only CAN1 */ + +#define CAN_PORT 1 + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_can_setup + * + * Description: + * Initialize CAN and register the CAN device + * + ****************************************************************************/ + +int stm32_can_setup(void) +{ +#ifdef CONFIG_STM32_CAN1 + struct can_dev_s *can; + int ret; + + /* Call stm32_caninitialize() to get an instance of the CAN interface */ + + can = stm32_caninitialize(CAN_PORT); + if (can == NULL) + { + canerr("ERROR: Failed to get CAN interface\n"); + return -ENODEV; + } + + /* Register the CAN driver at "/dev/can0" */ + + ret = can_register("/dev/can0", can); + if (ret < 0) + { + canerr("ERROR: can_register failed: %d\n", ret); + return ret; + } + + return OK; +#else + return -ENODEV; +#endif +} + +#endif /* CONFIG_CAN */ diff --git a/boards/arm/stm32f1/stm3210e-eval/src/stm32_composite.c b/boards/arm/stm32f1/stm3210e-eval/src/stm32_composite.c new file mode 100644 index 0000000000000..7eaeac511209a --- /dev/null +++ b/boards/arm/stm32f1/stm3210e-eval/src/stm32_composite.c @@ -0,0 +1,450 @@ +/**************************************************************************** + * boards/arm/stm32f1/stm3210e-eval/src/stm32_composite.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#include "stm32.h" + +#if defined(CONFIG_BOARDCTL_USBDEVCTRL) && defined(CONFIG_USBDEV_COMPOSITE) + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* No SDIO? Then no USB MSC device in composite */ + +#ifndef CONFIG_STM32_SDIO +# undef CONFIG_USBMSC_COMPOSITE +#endif + +/* SLOT number(s) could depend on the board configuration */ + +#ifdef CONFIG_ARCH_BOARD_STM3210E_EVAL +# undef STM32_MMCSDSLOTNO +# define STM32_MMCSDSLOTNO 0 +#else +/* Add configuration for new STM32 boards here */ + +# error "Unrecognized STM32 board" +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#ifdef CONFIG_USBMSC_COMPOSITE +static void *g_mschandle; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_mscclassobject + * + * Description: + * If the mass storage class driver is part of composite device, then + * its instantiation and configuration is a multi-step, board-specific, + * process (See comments for usbmsc_configure below). In this case, + * board-specific logic must provide board_mscclassobject(). + * + * board_mscclassobject() is called from the composite driver. It must + * encapsulate the instantiation and configuration of the mass storage + * class and the return the mass storage device's class driver instance + * to the composite driver. + * + * Input Parameters: + * classdev - The location to return the mass storage class' device + * instance. + * + * Returned Value: + * 0 on success; a negated errno on failure + * + ****************************************************************************/ + +#ifdef CONFIG_USBMSC_COMPOSITE +static int board_mscclassobject(int minor, + struct usbdev_devinfo_s *devinfo, + struct usbdevclass_driver_s **classdev) +{ + int ret; + + DEBUGASSERT(g_mschandle == NULL); + + /* Configure the mass storage device */ + + uinfo("Configuring with NLUNS=1\n"); + ret = usbmsc_configure(1, &g_mschandle); + if (ret < 0) + { + uerr("ERROR: usbmsc_configure failed: %d\n", -ret); + return ret; + } + + uinfo("MSC handle=%p\n", g_mschandle); + + /* Bind the LUN(s) */ + + uinfo("Bind LUN=0 to /dev/mmcsd0\n"); + ret = usbmsc_bindlun(g_mschandle, "/dev/mmcsd0", 0, 0, 0, false); + if (ret < 0) + { + uerr("ERROR: usbmsc_bindlun failed for LUN 1 at /dev/mmcsd0: %d\n", + ret); + usbmsc_uninitialize(g_mschandle); + g_mschandle = NULL; + return ret; + } + + /* Get the mass storage device's class object */ + + ret = usbmsc_classobject(g_mschandle, devinfo, classdev); + if (ret < 0) + { + uerr("ERROR: usbmsc_classobject failed: %d\n", -ret); + usbmsc_uninitialize(g_mschandle); + g_mschandle = NULL; + } + + return ret; +} +#endif + +/**************************************************************************** + * Name: board_mscuninitialize + * + * Description: + * Un-initialize the USB storage class driver. + * This is just an application- specific wrapper about usbmsc_unitialize() + * that is called form the composite device logic. + * + * Input Parameters: + * classdev - The class driver instance previously given to the composite + * driver by board_mscclassobject(). + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_USBMSC_COMPOSITE +static void board_mscuninitialize(struct usbdevclass_driver_s *classdev) +{ + DEBUGASSERT(g_mschandle != NULL); + usbmsc_uninitialize(g_mschandle); + g_mschandle = NULL; +} +#endif + +/**************************************************************************** + * Name: board_composite0_connect + * + * Description: + * Connect the USB composite device on the specified USB device port for + * configuration 0. + * + * Input Parameters: + * port - The USB device port. + * + * Returned Value: + * A non-NULL handle value is returned on success. NULL is returned on + * any failure. + * + ****************************************************************************/ + +#ifdef CONFIG_USBMSC_COMPOSITE +static void *board_composite0_connect(int port) +{ + /* Here we are composing the configuration of the usb composite device. + * + * The standard is to use one CDC/ACM and one USB mass storage device. + */ + + struct composite_devdesc_s dev[2]; + int ifnobase = 0; + int strbase = COMPOSITE_NSTRIDS; + + /* Configure the CDC/ACM device */ + + /* Ask the cdcacm driver to fill in the constants we didn't + * know here. + */ + + cdcacm_get_composite_devdesc(&dev[0]); + + /* Overwrite and correct some values... */ + + /* The callback functions for the CDC/ACM class */ + + dev[0].classobject = cdcacm_classobject; + dev[0].uninitialize = cdcacm_uninitialize; + + /* Interfaces */ + + dev[0].devinfo.ifnobase = ifnobase; /* Offset to Interface-IDs */ + dev[0].minor = 0; /* The minor interface number */ + + /* Strings */ + + dev[0].devinfo.strbase = strbase; /* Offset to String Numbers */ + + /* Endpoints */ + + dev[0].devinfo.epno[CDCACM_EP_INTIN_IDX] = 1; + dev[0].devinfo.epno[CDCACM_EP_BULKIN_IDX] = 2; + dev[0].devinfo.epno[CDCACM_EP_BULKOUT_IDX] = 3; + + /* Count up the base numbers */ + + ifnobase += dev[0].devinfo.ninterfaces; + strbase += dev[0].devinfo.nstrings; + + /* Configure the mass storage device device */ + + /* Ask the usbmsc driver to fill in the constants we didn't + * know here. + */ + + usbmsc_get_composite_devdesc(&dev[1]); + + /* Overwrite and correct some values... */ + + /* The callback functions for the USBMSC class */ + + dev[1].classobject = board_mscclassobject; + dev[1].uninitialize = board_mscuninitialize; + + /* Interfaces */ + + dev[1].devinfo.ifnobase = ifnobase; /* Offset to Interface-IDs */ + dev[1].minor = 0; /* The minor interface number */ + + /* Strings */ + + dev[1].devinfo.strbase = strbase; /* Offset to String Numbers */ + + /* Endpoints */ + + dev[1].devinfo.epno[USBMSC_EP_BULKIN_IDX] = 5; + dev[1].devinfo.epno[USBMSC_EP_BULKOUT_IDX] = 4; + + /* Count up the base numbers */ + + ifnobase += dev[1].devinfo.ninterfaces; + strbase += dev[1].devinfo.nstrings; + + return composite_initialize(composite_getdevdescs(), dev, 2); +} +#endif + +/**************************************************************************** + * Name: board_composite1_connect + * + * Description: + * Connect the USB composite device on the specified USB device port for + * configuration 1. + * + * Input Parameters: + * port - The USB device port. + * + * Returned Value: + * A non-NULL handle value is returned on success. NULL is returned on + * any failure. + * + ****************************************************************************/ + +static void *board_composite1_connect(int port) +{ + /* REVISIT: This configuration currently fails. stm32_epallocpma() fails + * allocate a buffer for the 6th endpoint. Currently it supports 7x64 byte + * buffers, two required for EP0, leaving only buffers for 5 additional + * endpoints. + */ + +#if 0 + struct composite_devdesc_s dev[2]; + int strbase = COMPOSITE_NSTRIDS; + int ifnobase = 0; + int epno; + int i; + + for (i = 0, epno = 1; i < 2; i++) + { + /* Ask the cdcacm driver to fill in the constants we didn't know here */ + + cdcacm_get_composite_devdesc(&dev[i]); + + /* Overwrite and correct some values... */ + + /* The callback functions for the CDC/ACM class */ + + dev[i].classobject = cdcacm_classobject; + dev[i].uninitialize = cdcacm_uninitialize; + + dev[i].minor = i; /* The minor interface number */ + + /* Interfaces */ + + dev[i].devinfo.ifnobase = ifnobase; /* Offset to Interface-IDs */ + + /* Strings */ + + dev[i].devinfo.strbase = strbase; /* Offset to String Numbers */ + + /* Endpoints */ + + dev[i].devinfo.epno[CDCACM_EP_INTIN_IDX] = epno++; + dev[i].devinfo.epno[CDCACM_EP_BULKIN_IDX] = epno++; + dev[i].devinfo.epno[CDCACM_EP_BULKOUT_IDX] = epno++; + + ifnobase += dev[i].devinfo.ninterfaces; + strbase += dev[i].devinfo.nstrings; + } + + return composite_initialize(composite_getdevdescs(), dev, 2); +#else + return NULL; +#endif +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_composite_initialize + * + * Description: + * Perform architecture specific initialization of a composite USB device. + * + ****************************************************************************/ + +int board_composite_initialize(int port) +{ + /* If system/composite is built as an NSH command, then SD slot should + * already have been initialized. + * In this case, there is nothing further to be done here. + * + * NOTE: CONFIG_NSH_BUILTIN_APPS is not a fool-proof indication that NSH + * was built. + */ + +#ifndef CONFIG_NSH_BUILTIN_APPS + struct sdio_dev_s *sdio; + int ret; + + /* First, get an instance of the SDIO interface */ + + syslog(LOG_INFO, "Initializing SDIO slot %d\n", STM32_MMCSDSLOTNO); + + sdio = sdio_initialize(STM32_MMCSDSLOTNO); + if (!sdio) + { + syslog(LOG_ERR, "ERROR: Failed to initialize SDIO slot %d\n", + STM32_MMCSDSLOTNO); + return -ENODEV; + } + + /* Now bind the SDIO interface to the MMC/SD driver */ + + syslog(LOG_INFO, "Bind SDIO to the MMC/SD driver, minor=0\n"); + + ret = mmcsd_slotinitialize(0, sdio); + if (ret != OK) + { + syslog(LOG_ERR, + "ERROR: Failed to bind SDIO to the MMC/SD driver: %d\n", + ret); + return ret; + } + + syslog(LOG_INFO, "Successfully bound SDIO to the MMC/SD driver\n"); + + /* Then let's guess and say that there is a card in the slot. I need to + * check to see if the STM3210E-EVAL board supports a GPIO to detect if + * there is a card in the slot. + */ + + sdio_mediachange(sdio, true); + +#endif /* CONFIG_NSH_BUILTIN_APPS */ + + return OK; +} + +/**************************************************************************** + * Name: board_composite_connect + * + * Description: + * Connect the USB composite device on the specified USB device port using + * the specified configuration. The interpretation of the configid is + * board specific. + * + * Input Parameters: + * port - The USB device port. + * configid - The USB composite configuration + * + * Returned Value: + * A non-NULL handle value is returned on success. NULL is returned on + * any failure. + * + ****************************************************************************/ + +void *board_composite_connect(int port, int configid) +{ + if (configid == 0) + { +#ifdef CONFIG_USBMSC_COMPOSITE + return board_composite0_connect(port); +#else + return NULL; +#endif + } + else if (configid == 1) + { + return board_composite1_connect(port); + } + else + { + return NULL; + } +} + +#endif /* CONFIG_BOARDCTL_USBDEVCTRL && CONFIG_USBDEV_COMPOSITE */ diff --git a/boards/arm/stm32f1/stm3210e-eval/src/stm32_deselectlcd.c b/boards/arm/stm32f1/stm3210e-eval/src/stm32_deselectlcd.c new file mode 100644 index 0000000000000..e36b381ba7c79 --- /dev/null +++ b/boards/arm/stm32f1/stm3210e-eval/src/stm32_deselectlcd.c @@ -0,0 +1,80 @@ +/**************************************************************************** + * boards/arm/stm32f1/stm3210e-eval/src/stm32_deselectlcd.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include "arm_internal.h" +#include "stm32.h" +#include "stm3210e-eval.h" + +#ifdef CONFIG_STM32_FSMC + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_deselectlcd + * + * Description: + * Disable the LCD + * + ****************************************************************************/ + +void stm32_deselectlcd(void) +{ + /* Restore registers to their power up settings */ + + putreg32(0xffffffff, STM32_FSMC_BCR4); + + /* Bank1 NOR/SRAM timing register configuration */ + + putreg32(0x0fffffff, STM32_FSMC_BTR4); + + /* Disable AHB clocking to the FSMC */ + + stm32_fsmc_disable(); +} + +#endif /* CONFIG_STM32_FSMC */ diff --git a/boards/arm/stm32/stm3210e-eval/src/stm32_deselectnor.c b/boards/arm/stm32f1/stm3210e-eval/src/stm32_deselectnor.c similarity index 97% rename from boards/arm/stm32/stm3210e-eval/src/stm32_deselectnor.c rename to boards/arm/stm32f1/stm3210e-eval/src/stm32_deselectnor.c index 64260e9803876..1798b2b4c943f 100644 --- a/boards/arm/stm32/stm3210e-eval/src/stm32_deselectnor.c +++ b/boards/arm/stm32f1/stm3210e-eval/src/stm32_deselectnor.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm3210e-eval/src/stm32_deselectnor.c + * boards/arm/stm32f1/stm3210e-eval/src/stm32_deselectnor.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f1/stm3210e-eval/src/stm32_deselectsram.c b/boards/arm/stm32f1/stm3210e-eval/src/stm32_deselectsram.c new file mode 100644 index 0000000000000..2a23173f2a441 --- /dev/null +++ b/boards/arm/stm32f1/stm3210e-eval/src/stm32_deselectsram.c @@ -0,0 +1,80 @@ +/**************************************************************************** + * boards/arm/stm32f1/stm3210e-eval/src/stm32_deselectsram.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include "arm_internal.h" +#include "stm32.h" +#include "stm3210e-eval.h" + +#ifdef CONFIG_STM32_FSMC + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_deselectsram + * + * Description: + * Disable NOR FLASH + * + ****************************************************************************/ + +void stm32_deselectsram(void) +{ + /* Restore registers to their power up settings */ + + putreg32(0x000030d2, STM32_FSMC_BCR3); + + /* Bank1 NOR/SRAM timing register configuration */ + + putreg32(0x0fffffff, STM32_FSMC_BTR3); + + /* Disable AHB clocking to the FSMC */ + + stm32_fsmc_disable(); +} + +#endif /* CONFIG_STM32_FSMC */ diff --git a/boards/arm/stm32f1/stm3210e-eval/src/stm32_djoystick.c b/boards/arm/stm32f1/stm3210e-eval/src/stm32_djoystick.c new file mode 100644 index 0000000000000..4b3b7868e3316 --- /dev/null +++ b/boards/arm/stm32f1/stm3210e-eval/src/stm32_djoystick.c @@ -0,0 +1,299 @@ +/**************************************************************************** + * boards/arm/stm32f1/stm3210e-eval/src/stm32_djoystick.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include +#include +#include + +#include "stm32_gpio.h" +#include "stm3210e-eval.h" + +#ifdef CONFIG_INPUT_DJOYSTICK + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Number of Joystick discretes */ + +#define DJOY_NGPIOS 5 + +/* Bitset of supported Joystick discretes */ + +#define DJOY_SUPPORTED (DJOY_UP_BIT | DJOY_DOWN_BIT | DJOY_LEFT_BIT | \ + DJOY_RIGHT_BIT | DJOY_BUTTON_SELECT_BIT) + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +static djoy_buttonset_t +djoy_supported(const struct djoy_lowerhalf_s *lower); +static djoy_buttonset_t +djoy_sample(const struct djoy_lowerhalf_s *lower); +static void djoy_enable(const struct djoy_lowerhalf_s *lower, + djoy_buttonset_t press, djoy_buttonset_t release, + djoy_interrupt_t handler, void *arg); + +static void djoy_disable(void); +static int djoy_interrupt(int irq, void *context, void *arg); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* Pin configuration for each STM3210E-EVAL joystick "button." Index using + * DJOY_* definitions in include/nuttx/input/djoystick.h. + */ + +static const uint16_t g_joygpio[DJOY_NGPIOS] = +{ + GPIO_JOY_UP, GPIO_JOY_DOWN, GPIO_JOY_LEFT, GPIO_JOY_RIGHT, GPIO_JOY_SEL +}; + +/* Current interrupt handler and argument */ + +static djoy_interrupt_t g_djoyhandler; +static void *g_djoyarg; + +/* This is the discrete joystick lower half driver interface */ + +static const struct djoy_lowerhalf_s g_djoylower = +{ + .dl_supported = djoy_supported, + .dl_sample = djoy_sample, + .dl_enable = djoy_enable, +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: djoy_supported + * + * Description: + * Return the set of buttons supported on the discrete joystick device + * + ****************************************************************************/ + +static djoy_buttonset_t +djoy_supported(const struct djoy_lowerhalf_s *lower) +{ + iinfo("Supported: %02x\n", DJOY_SUPPORTED); + return (djoy_buttonset_t)DJOY_SUPPORTED; +} + +/**************************************************************************** + * Name: djoy_sample + * + * Description: + * Return the current state of all discrete joystick buttons + * + ****************************************************************************/ + +static djoy_buttonset_t djoy_sample(const struct djoy_lowerhalf_s *lower) +{ + djoy_buttonset_t ret = 0; + int i; + + /* Read each joystick GPIO value */ + + for (i = 0; i < DJOY_NGPIOS; i++) + { + bool released = stm32_gpioread(g_joygpio[i]); + if (!released) + { + ret |= (1 << i); + } + } + + iinfo("Retuning: %02x\n", DJOY_SUPPORTED); + return ret; +} + +/**************************************************************************** + * Name: djoy_enable + * + * Description: + * Enable interrupts on the selected set of joystick buttons. And empty + * set will disable all interrupts. + * + ****************************************************************************/ + +static void djoy_enable(const struct djoy_lowerhalf_s *lower, + djoy_buttonset_t press, djoy_buttonset_t release, + djoy_interrupt_t handler, void *arg) +{ + irqstate_t flags; + djoy_buttonset_t either = press | release; + djoy_buttonset_t bit; + bool rising; + bool falling; + int i; + + /* Start with all interrupts disabled */ + + flags = enter_critical_section(); + djoy_disable(); + + iinfo("press: %02x release: %02x handler: %p arg: %p\n", + press, release, handler, arg); + + /* If no events are indicated or if no handler is provided, then this + * must really be a request to disable interrupts. + */ + + if (either && handler) + { + /* Save the new the handler and argument */ + + g_djoyhandler = handler; + g_djoyarg = arg; + + /* Check each GPIO. */ + + for (i = 0; i < DJOY_NGPIOS; i++) + { + /* Enable interrupts on each pin that has either a press or + * release event associated with it. + */ + + bit = (1 << i); + if ((either & bit) != 0) + { + /* Active low so a press corresponds to a falling edge and + * a release corresponds to a rising edge. + */ + + falling = ((press & bit) != 0); + rising = ((release & bit) != 0); + + iinfo("GPIO %d: rising: %d falling: %d\n", + i, rising, falling); + + stm32_gpiosetevent(g_joygpio[i], rising, falling, + true, djoy_interrupt, NULL); + } + } + } + + leave_critical_section(flags); +} + +/**************************************************************************** + * Name: djoy_disable + * + * Description: + * Disable all joystick interrupts + * + ****************************************************************************/ + +static void djoy_disable(void) +{ + irqstate_t flags; + int i; + + /* Disable each joystick interrupt */ + + flags = enter_critical_section(); + for (i = 0; i < DJOY_NGPIOS; i++) + { + stm32_gpiosetevent(g_joygpio[i], false, false, false, NULL, NULL); + } + + leave_critical_section(flags); + + /* Nullify the handler and argument */ + + g_djoyhandler = NULL; + g_djoyarg = NULL; +} + +/**************************************************************************** + * Name: djoy_interrupt + * + * Description: + * Discrete joystick interrupt handler + * + ****************************************************************************/ + +static int djoy_interrupt(int irq, void *context, void *arg) +{ + DEBUGASSERT(g_djoyhandler); + if (g_djoyhandler) + { + g_djoyhandler(&g_djoylower, g_djoyarg); + } + + return OK; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_djoy_initialization + * + * Description: + * Initialize and register the discrete joystick driver + * + ****************************************************************************/ + +int stm32_djoy_initialization(void) +{ + int i; + + /* Configure the GPIO pins as inputs. NOTE: This is unnecessary for + * interrupting pins since it will also be done by stm32_gpiosetevent(). + */ + + for (i = 0; i < DJOY_NGPIOS; i++) + { + stm32_configgpio(g_joygpio[i]); + } + + /* Make sure that all interrupts are disabled */ + + djoy_disable(); + + /* Register the joystick device as /dev/djoy0 */ + + return djoy_register("/dev/djoy0", &g_djoylower); +} + +#endif /* CONFIG_INPUT_DJOYSTICK */ diff --git a/boards/arm/stm32/stm3210e-eval/src/stm32_extcontext.c b/boards/arm/stm32f1/stm3210e-eval/src/stm32_extcontext.c similarity index 98% rename from boards/arm/stm32/stm3210e-eval/src/stm32_extcontext.c rename to boards/arm/stm32f1/stm3210e-eval/src/stm32_extcontext.c index c6b2b4afc386e..64f822a232fe8 100644 --- a/boards/arm/stm32/stm3210e-eval/src/stm32_extcontext.c +++ b/boards/arm/stm32f1/stm3210e-eval/src/stm32_extcontext.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm3210e-eval/src/stm32_extcontext.c + * boards/arm/stm32f1/stm3210e-eval/src/stm32_extcontext.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f1/stm3210e-eval/src/stm32_extmem.c b/boards/arm/stm32f1/stm3210e-eval/src/stm32_extmem.c new file mode 100644 index 0000000000000..3b2779e4ffb27 --- /dev/null +++ b/boards/arm/stm32f1/stm3210e-eval/src/stm32_extmem.c @@ -0,0 +1,137 @@ +/**************************************************************************** + * boards/arm/stm32f1/stm3210e-eval/src/stm32_extmem.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32_gpio.h" +#include "stm32.h" +#include "stm3210e-eval.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifndef CONFIG_STM32_FSMC +# warning "FSMC is not enabled" +#endif + +#if STM32_NGPIO_PORTS < 6 +# error "Required GPIO ports not enabled" +#endif + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/* 512Kx16 SRAM is connected to bank2 of the FSMC interface and both 8- and + * 16-bit accesses are allowed by BLN0 and BLN1 connected to BLE and BHE of + * SRAM, respectively. + * + * Pin Usage (per schematic) + * + * FLASH SRAM NAND LCD + * D[0..15] [0..15] [0..15] [0..7] [0..15] + * A[0..23] [0..22] [0..18] [16,17] [0] + * FSMC_NBL0 PE0 OUT ~BLE --- --- --- + * FSMC_NBL1 PE1 OUT ~BHE --- --- --- + * FSMC_NE2 PG9 OUT --- ~E --- --- + * FSMC_NE3 PG10 OUT ~CE --- --- --- + * FSMC_NE4 PG12 OUT --- --- --- ~CS + * FSMC_NWE PD5 OUT ~WE ~W ~W ~WR/SCL + * FSMC_NOE PD4 OUT ~OE ~G ~R ~RD + * FSMC_NWAIT PD6 IN --- R~B --- --- + * FSMC_INT2 PG6* IN --- --- R~B --- + * + * *JP7 will switch to PD6 + */ + +/* It would be much more efficient to brute force these all into the + * the appropriate registers. Just a little tricky. + */ + +/* GPIO configurations common to SRAM and NOR Flash */ + +const uint16_t g_commonconfig[NCOMMON_CONFIG] = +{ + /* A0... A18 */ + + GPIO_NPS_A0, GPIO_NPS_A1, GPIO_NPS_A2, GPIO_NPS_A3, + GPIO_NPS_A4, GPIO_NPS_A5, GPIO_NPS_A6, GPIO_NPS_A7, + GPIO_NPS_A8, GPIO_NPS_A9, GPIO_NPS_A10, GPIO_NPS_A11, + GPIO_NPS_A12, GPIO_NPS_A13, GPIO_NPS_A14, GPIO_NPS_A15, + GPIO_NPS_A16, GPIO_NPS_A17, GPIO_NPS_A18, + + /* D0... D15 */ + + GPIO_NPS_D0, GPIO_NPS_D1, GPIO_NPS_D2, GPIO_NPS_D3, + GPIO_NPS_D4, GPIO_NPS_D5, GPIO_NPS_D6, GPIO_NPS_D7, + GPIO_NPS_D8, GPIO_NPS_D9, GPIO_NPS_D10, GPIO_NPS_D11, + GPIO_NPS_D12, GPIO_NPS_D13, GPIO_NPS_D14, GPIO_NPS_D15, + + /* NOE, NWE */ + + GPIO_NPS_NOE, GPIO_NPS_NWE +}; + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_extmemgpios + * + * Description: + * Initialize GPIOs for NOR or SRAM + * + ****************************************************************************/ + +void stm32_extmemgpios(const uint16_t *gpios, int ngpios) +{ + int i; + + /* Configure GPIOs */ + + for (i = 0; i < ngpios; i++) + { + stm32_configgpio(gpios[i]); + } +} diff --git a/boards/arm/stm32f1/stm3210e-eval/src/stm32_idle.c b/boards/arm/stm32f1/stm3210e-eval/src/stm32_idle.c new file mode 100644 index 0000000000000..1c4cb71b0df62 --- /dev/null +++ b/boards/arm/stm32f1/stm3210e-eval/src/stm32_idle.c @@ -0,0 +1,437 @@ +/**************************************************************************** + * boards/arm/stm32f1/stm3210e-eval/src/stm32_idle.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include +#include +#include + +#include + +#include +#include + +#include "arm_internal.h" +#include "stm32_pm.h" +#include "stm32_rcc.h" +#include "stm32_exti.h" +#include "stm32_rtc.h" + +#include "stm3210e-eval.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* Does the board support an IDLE LED to indicate that the board is in the + * IDLE state? + */ + +#if defined(CONFIG_ARCH_LEDS) && defined(LED_IDLE) +# define BEGIN_IDLE() board_autoled_on(LED_IDLE) +# define END_IDLE() board_autoled_off(LED_IDLE) +#else +# define BEGIN_IDLE() +# define END_IDLE() +#endif + +/* Values for the RTC Alarm to wake up from the PM_STANDBY mode + * (which corresponds to STM32 stop mode). If this alarm expires, + * the logic in this file will wakeup from PM_STANDBY mode and + * transition to PM_SLEEP mode (STM32 standby mode). + */ + +#ifndef CONFIG_PM_ALARM_SEC +# define CONFIG_PM_ALARM_SEC 15 +#endif + +#ifndef CONFIG_PM_ALARM_NSEC +# define CONFIG_PM_ALARM_NSEC 0 +#endif + +/* Values for the RTC Alarm to reset from the PM_SLEEP mode (STM32 + * standby mode). If CONFIG_PM_SLEEP_WAKEUP is defined in the + * configuration, then the logic in this file will program the RTC + * alarm to wakeup the processor after an a delay. + * + * This feature might be useful, for example, in a system that needs to + * use minimal power but awake up to perform some task at periodic + * intervals. + */ + +#ifdef CONFIG_PM_SLEEP_WAKEUP + +# ifndef CONFIG_RTC_ALARM +# error "CONFIG_RTC_ALARM should be enabled to use CONFIG_PM_SLEEP_WAKEUP" +# endif + +/* If CONFIG_PM_SLEEP_WAKEUP is defined, then CONFIG_PM_SLEEP_WAKEUP_SEC + * and CONFIG_PM_SLEEP_WAKEUP_NSEC define the delay until the STM32 + * awakens from PM_SLEEP mode. + */ + +# ifndef CONFIG_PM_SLEEP_WAKEUP_SEC +# define CONFIG_PM_SLEEP_WAKEUP_SEC 10 +# endif + +# ifndef CONFIG_PM_SLEEP_WAKEUP_NSEC +# define CONFIG_PM_SLEEP_WAKEUP_NSEC 0 +# endif +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#if defined(CONFIG_PM) && defined(CONFIG_RTC_ALARM) +static volatile bool g_alarmwakeup; /* Wakeup Alarm indicator */ +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_alarmcb + * + * Description: + * RTC alarm callback + * + ****************************************************************************/ + +#if defined(CONFIG_PM) && defined(CONFIG_RTC_ALARM) +static void stm32_alarmcb(void) +{ + /* Note that we were awaken by an alarm */ + + g_alarmwakeup = true; +} +#endif + +/**************************************************************************** + * Name: stm32_alarm_exti + * + * Description: + * RTC alarm EXTI interrupt service routine + * + ****************************************************************************/ + +#if defined(CONFIG_PM) && defined(CONFIG_RTC_ALARM) +static int stm32_alarm_exti(int irq, void *context, void *arg) +{ + stm32_alarmcb(); + return OK; +} +#endif + +/**************************************************************************** + * Name: stm32_exti_cancel + * + * Description: + * Disable the ALARM EXTI interrupt + * + ****************************************************************************/ + +#if defined(CONFIG_PM) && defined(CONFIG_RTC_ALARM) +static void stm32_exti_cancel(void) +{ + stm32_exti_alarm(false, false, false, NULL, NULL); +} +#endif + +/**************************************************************************** + * Name: stm32_rtc_alarm + * + * Description: + * Set the alarm + * + ****************************************************************************/ + +#if defined(CONFIG_PM) && defined(CONFIG_RTC_ALARM) +static int stm32_rtc_alarm(time_t tv_sec, time_t tv_nsec, bool exti) +{ + struct timespec alarmtime; + int ret; + + /* Configure to receive RTC Alarm EXTI interrupt */ + + if (exti) + { + /* TODO: Make sure that that is no pending EXTI interrupt */ + + stm32_exti_alarm(true, true, true, stm32_alarm_exti, NULL); + } + + /* Configure the RTC alarm to Auto Wake the system */ + + up_rtc_gettime(&alarmtime); + + alarmtime.tv_sec += tv_sec; + alarmtime.tv_nsec += tv_nsec; + + /* The tv_nsec value must not exceed 1,000,000,000. That + * would be an invalid time. + */ + + if (alarmtime.tv_nsec >= NSEC_PER_SEC) + { + /* Carry to the seconds */ + + alarmtime.tv_sec++; + alarmtime.tv_nsec -= NSEC_PER_SEC; + } + + /* Set the alarm */ + + g_alarmwakeup = false; + ret = stm32_rtc_setalarm(&alarmtime, stm32_alarmcb); + if (ret < 0) + { + serr("ERROR: Warning: The alarm is already set\n"); + } + + return ret; +} +#endif + +/**************************************************************************** + * Name: stm32_idlepm + * + * Description: + * Perform IDLE state power management. + * + ****************************************************************************/ + +#ifdef CONFIG_PM +static void stm32_idlepm(void) +{ + static enum pm_state_e oldstate = PM_NORMAL; + enum pm_state_e newstate; + int ret; + + /* The following is logic that is done after the wake-up from PM_STANDBY + * state. It decides whether to go back to the PM_NORMAL or to the deeper + * power-saving mode PM_SLEEP: If the alarm expired with no "normal" + * wake-up event, then PM_SLEEP is entered. + * + * Logically, this code belongs at the end of the PM_STANDBY case below, + * does not work in the position for some unknown reason. + */ + + if (oldstate == PM_STANDBY) + { + /* Were we awakened by the alarm? */ + +#ifdef CONFIG_RTC_ALARM + if (g_alarmwakeup) + { + /* Yes.. Go to SLEEP mode */ + + newstate = PM_SLEEP; + } + else +#endif + { + /* Resume normal operation */ + + newstate = PM_NORMAL; + } + } + else + { + /* Let the PM system decide, which power saving level can be obtained */ + + newstate = pm_checkstate(PM_IDLE_DOMAIN); + } + + /* Check for state changes */ + + if (newstate != oldstate) + { + _info("newstate= %d oldstate=%d\n", newstate, oldstate); + + sched_lock(); + + /* Force the global state change */ + + ret = pm_changestate(PM_IDLE_DOMAIN, newstate); + if (ret < 0) + { + /* The new state change failed, revert to the preceding state */ + + pm_changestate(PM_IDLE_DOMAIN, oldstate); + + /* No state change... */ + + goto errout; + } + + /* Then perform board-specific, state-dependent logic here */ + + switch (newstate) + { + case PM_NORMAL: + { + /* If we just awakened from PM_STANDBY mode, then reconfigure + * clocking. + */ + + if (oldstate == PM_STANDBY) + { + /* Re-enable clocking */ + + stm32_clockenable(); + + /* The system timer was disabled while in PM_STANDBY or + * PM_SLEEP modes. But the RTC has still be running: Reset + * the system time the current RTC time. + */ + +#ifdef CONFIG_RTC + clock_synchronize(NULL); +#endif + } + } + break; + + case PM_IDLE: + { + } + break; + + case PM_STANDBY: + { + /* Set the alarm as an EXTI Line */ + +#ifdef CONFIG_RTC_ALARM + stm32_rtc_alarm(CONFIG_PM_ALARM_SEC, CONFIG_PM_ALARM_NSEC, true); +#endif + /* Wait 10ms */ + + up_mdelay(10); + + /* Enter the STM32 stop mode */ + + stm32_pmstop(false); + + /* We have been re-awakened by some even: A button press? + * An alarm? Cancel any pending alarm and resume the normal + * operation. + */ + +#ifdef CONFIG_RTC_ALARM + stm32_exti_cancel(); + ret = stm32_rtc_cancelalarm(); + if (ret < 0) + { + swarn("WARNING: Cancel alarm failed\n"); + } +#endif + + /* Note: See the additional PM_STANDBY related logic at the + * beginning of this function. That logic is executed after + * this point. + */ + } + break; + + case PM_SLEEP: + { + /* We should not return from standby mode. The only way out + * of standby is via the reset path. + */ + + /* Configure the RTC alarm to Auto Reset the system */ + +#ifdef CONFIG_PM_SLEEP_WAKEUP + stm32_rtc_alarm(CONFIG_PM_SLEEP_WAKEUP_SEC, + CONFIG_PM_SLEEP_WAKEUP_NSEC, false); +#endif + /* Wait 10ms */ + + up_mdelay(10); + + /* Enter the STM32 standby mode */ + + stm32_pmstandby(); + } + break; + + default: + break; + } + + /* Save the new state */ + + oldstate = newstate; + +errout: + sched_unlock(); + } +} +#else +# define stm32_idlepm() +#endif /* CONFIG_PM */ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_idle + * + * Description: + * up_idle() is the logic that will be executed when their is no other + * ready-to-run task. This is processor idle time and will continue until + * some interrupt occurs to cause a context switch from the idle task. + * + * Processing in this state may be processor-specific. e.g., this is where + * power management operations might be performed. + * + ****************************************************************************/ + +void up_idle(void) +{ +#if defined(CONFIG_SUPPRESS_INTERRUPTS) || defined(CONFIG_SUPPRESS_TIMER_INTS) + /* If the system is idle and there are no timer interrupts, then process + * "fake" timer interrupts. Hopefully, something will wake up. + */ + + nxsched_process_timer(); +#else + + /* Perform IDLE mode power management */ + + BEGIN_IDLE(); + stm32_idlepm(); + END_IDLE(); +#endif +} diff --git a/boards/arm/stm32f1/stm3210e-eval/src/stm32_lcd.c b/boards/arm/stm32f1/stm3210e-eval/src/stm32_lcd.c new file mode 100644 index 0000000000000..f0b29a830d7b0 --- /dev/null +++ b/boards/arm/stm32f1/stm3210e-eval/src/stm32_lcd.c @@ -0,0 +1,1841 @@ +/**************************************************************************** + * boards/arm/stm32f1/stm3210e-eval/src/stm32_lcd.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* This driver supports the following LCDs: + * + * 1. Ampire AM-240320LTNQW00H + * 2. Orise Tech SPFD5408B + * 3. RenesasSP R61580 + * + * The driver dynamically selects the LCD based on the reported LCD ID value. + * However, code size can be reduced by suppressing support for individual + * LCDs using: + * + * CONFIG_STM3210E_AM240320_DISABLE + * CONFIG_STM3210E_SPFD5408B_DISABLE + * CONFIG_STM3210E_R61580_DISABLE + * + * Omitting the above (or setting them to "n") enables support for the LCD. + * Setting any of the above to "y" will disable support for the + * corresponding LCD. + */ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include +#include + +#include "arm_internal.h" +#include "stm32.h" +#include "stm3210e-eval.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* Check contrast selection */ + +#if !defined(CONFIG_LCD_MAXCONTRAST) +# define CONFIG_LCD_MAXCONTRAST 1 +#endif + +/* Backlight */ + +#ifndef CONFIG_STM3210E_LCD_BACKLIGHT +# undef CONFIG_STM3210E_LCD_PWM +#endif + +#if defined(CONFIG_STM3210E_LCD_BACKLIGHT) && defined(CONFIG_STM3210E_LCD_PWM) +# if !defined(CONFIG_STM32_TIM1) +# warning "CONFIG_STM3210E_LCD_PWM requires CONFIG_STM32_TIM1" +# undef CONFIG_STM3210E_LCD_PWM +# endif +# if defined(CONFIG_STM32_TIM1_FULL_REMAP) +# warning "PA8 cannot be configured as TIM1 CH1 with full remap" +# undef CONFIG_STM3210E_LCD_PWM +# endif +#endif + +#if defined(CONFIG_STM3210E_LCD_BACKLIGHT) && defined(CONFIG_STM3210E_LCD_PWM) +# if CONFIG_LCD_MAXPOWER < 2 +# warning "A larger value of CONFIG_LCD_MAXPOWER is recommended" +# endif +#endif + +/* Check power setting */ + +#if !defined(CONFIG_LCD_MAXPOWER) || CONFIG_LCD_MAXPOWER < 1 +# undef CONFIG_LCD_MAXPOWER +# if defined(CONFIG_STM3210E_LCD_BACKLIGHT) && defined(CONFIG_STM3210E_LCD_PWM) +# define CONFIG_LCD_MAXPOWER 100 +# else +# define CONFIG_LCD_MAXPOWER 1 +# endif +#endif + +#if CONFIG_LCD_MAXPOWER > 255 +# error "CONFIG_LCD_MAXPOWER must be less than 256 to fit in uint8_t" +#endif + +/* PWM Frequency */ + +#ifndef CONFIG_STM3210E_LCD_PWMFREQUENCY +# define CONFIG_STM3210E_LCD_PWMFREQUENCY 100 +#endif + +/* Check orientation */ + +#if defined(CONFIG_LCD_PORTRAIT) +# if defined(CONFIG_LCD_LANDSCAPE) || defined(CONFIG_LCD_RPORTRAIT) +# error "Cannot define both portrait and any other orientations" +# endif +#elif defined(CONFIG_LCD_RPORTRAIT) +# if defined(CONFIG_LCD_LANDSCAPE) || defined(CONFIG_LCD_PORTRAIT) +# error "Cannot define both rportrait and any other orientations" +# endif +#elif !defined(CONFIG_LCD_LANDSCAPE) +# define CONFIG_LCD_LANDSCAPE 1 +#endif + +/* When reading 16-bit gram data, there may some shifts in the returned data + * and/or there may be some colors in the incorrect posisions: + * + * - SPFD5408B: There appears to be a 5-bit shift in the returned data. + * Red and green appear to be swapped on read-back as well + * - R61580: There is a 16-bit (1 pixel) shift in the returned data. + * - AM240320: Unknown -- assume colors are correct for now. + */ + +#define SPFD5408B_RDSHIFT 5 + +/* Display/Color Properties *************************************************/ + +/* Display Resolution */ + +#ifdef CONFIG_LCD_LANDSCAPE +# define STM3210E_XRES 320 +# define STM3210E_YRES 240 +#else +# define STM3210E_XRES 240 +# define STM3210E_YRES 320 +#endif + +/* Color depth and format */ + +#define STM3210E_BPP 16 +#define STM3210E_COLORFMT FB_FMT_RGB16_565 + +/* STM3210E-EVAL LCD Hardware Definitions ***********************************/ + +/* LCD /CS is CE4, Bank 4 of NOR/SRAM Bank 1~4 */ + +#define STM3210E_LCDBASE ((uint32_t)(0x60000000 | 0x0c000000)) +#define LCD ((struct lcd_regs_s *) STM3210E_LCDBASE) + +#define LCD_REG_0 0x00 +#define LCD_REG_1 0x01 +#define LCD_REG_2 0x02 +#define LCD_REG_3 0x03 +#define LCD_REG_4 0x04 +#define LCD_REG_5 0x05 +#define LCD_REG_6 0x06 +#define LCD_REG_7 0x07 +#define LCD_REG_8 0x08 +#define LCD_REG_9 0x09 +#define LCD_REG_10 0x0a +#define LCD_REG_12 0x0c +#define LCD_REG_13 0x0d +#define LCD_REG_14 0x0e +#define LCD_REG_15 0x0f +#define LCD_REG_16 0x10 +#define LCD_REG_17 0x11 +#define LCD_REG_18 0x12 +#define LCD_REG_19 0x13 +#define LCD_REG_20 0x14 +#define LCD_REG_21 0x15 +#define LCD_REG_22 0x16 +#define LCD_REG_23 0x17 +#define LCD_REG_24 0x18 +#define LCD_REG_25 0x19 +#define LCD_REG_26 0x1a +#define LCD_REG_27 0x1b +#define LCD_REG_28 0x1c +#define LCD_REG_29 0x1d +#define LCD_REG_30 0x1e +#define LCD_REG_31 0x1f +#define LCD_REG_32 0x20 +#define LCD_REG_33 0x21 +#define LCD_REG_34 0x22 +#define LCD_REG_36 0x24 +#define LCD_REG_37 0x25 +#define LCD_REG_40 0x28 +#define LCD_REG_41 0x29 +#define LCD_REG_43 0x2b +#define LCD_REG_45 0x2d +#define LCD_REG_48 0x30 +#define LCD_REG_49 0x31 +#define LCD_REG_50 0x32 +#define LCD_REG_51 0x33 +#define LCD_REG_52 0x34 +#define LCD_REG_53 0x35 +#define LCD_REG_54 0x36 +#define LCD_REG_55 0x37 +#define LCD_REG_56 0x38 +#define LCD_REG_57 0x39 +#define LCD_REG_58 0x3a +#define LCD_REG_59 0x3b +#define LCD_REG_60 0x3c +#define LCD_REG_61 0x3d +#define LCD_REG_62 0x3e +#define LCD_REG_63 0x3f +#define LCD_REG_64 0x40 +#define LCD_REG_65 0x41 +#define LCD_REG_66 0x42 +#define LCD_REG_67 0x43 +#define LCD_REG_68 0x44 +#define LCD_REG_69 0x45 +#define LCD_REG_70 0x46 +#define LCD_REG_71 0x47 +#define LCD_REG_72 0x48 +#define LCD_REG_73 0x49 +#define LCD_REG_74 0x4a +#define LCD_REG_75 0x4b +#define LCD_REG_76 0x4c +#define LCD_REG_77 0x4d +#define LCD_REG_78 0x4e +#define LCD_REG_79 0x4f +#define LCD_REG_80 0x50 +#define LCD_REG_81 0x51 +#define LCD_REG_82 0x52 +#define LCD_REG_83 0x53 +#define LCD_REG_96 0x60 +#define LCD_REG_97 0x61 +#define LCD_REG_106 0x6a +#define LCD_REG_118 0x76 +#define LCD_REG_128 0x80 +#define LCD_REG_129 0x81 +#define LCD_REG_130 0x82 +#define LCD_REG_131 0x83 +#define LCD_REG_132 0x84 +#define LCD_REG_133 0x85 +#define LCD_REG_134 0x86 +#define LCD_REG_135 0x87 +#define LCD_REG_136 0x88 +#define LCD_REG_137 0x89 +#define LCD_REG_139 0x8b +#define LCD_REG_140 0x8c +#define LCD_REG_141 0x8d +#define LCD_REG_143 0x8f +#define LCD_REG_144 0x90 +#define LCD_REG_145 0x91 +#define LCD_REG_146 0x92 +#define LCD_REG_147 0x93 +#define LCD_REG_148 0x94 +#define LCD_REG_149 0x95 +#define LCD_REG_150 0x96 +#define LCD_REG_151 0x97 +#define LCD_REG_152 0x98 +#define LCD_REG_153 0x99 +#define LCD_REG_154 0x9a +#define LCD_REG_157 0x9d +#define LCD_REG_164 0xa4 +#define LCD_REG_192 0xc0 +#define LCD_REG_193 0xc1 +#define LCD_REG_229 0xe5 + +/* LCD IDs */ + +#define SPFD5408B_ID 0x5408 +#define R61580_ID 0x1580 + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/* LCD type */ + +enum lcd_type_e +{ + LCD_TYPE_UNKNOWN = 0, + LCD_TYPE_SPFD5408B, + LCD_TYPE_R61580, + LCD_TYPE_AM240320 +}; + +/* This structure describes the LCD registers */ + +struct lcd_regs_s +{ + volatile uint16_t address; + volatile uint16_t value; +}; + +/* This structure describes the state of this driver */ + +struct stm3210e_dev_s +{ + /* Publicly visible device structure */ + + struct lcd_dev_s dev; + +#if defined(CONFIG_STM3210E_LCD_BACKLIGHT) && defined(CONFIG_STM3210E_LCD_PWM) + uint32_t reload; +#endif + + /* Private LCD-specific information follows */ + + uint8_t type; /* LCD type. See enum lcd_type_e */ + uint8_t power; /* Current power setting */ +}; + +/**************************************************************************** + * Private Function Protototypes + ****************************************************************************/ + +/* Low Level LCD access */ + +static void stm3210e_writereg(uint8_t regaddr, uint16_t regval); +static uint16_t stm3210e_readreg(uint8_t regaddr); +static inline void stm3210e_gramselect(void); +static inline void stm3210e_writegram(uint16_t rgbval); +static void stm3210e_readsetup(uint16_t *accum); +#ifndef CONFIG_STM3210E_AM240320_DISABLE +static void stm3210e_readnosetup(uint16_t *accum); +#endif +static uint16_t stm3210e_readshift(uint16_t *accum); +static uint16_t stm3210e_readnoshift(uint16_t *accum); +static void stm3210e_setcursor(uint16_t col, uint16_t row); + +/* LCD Data Transfer Methods */ + +static int stm3210e_putrun(struct lcd_dev_s *dev, + fb_coord_t row, fb_coord_t col, + const uint8_t *buffer, + size_t npixels); +static int stm3210e_getrun(struct lcd_dev_s *dev, + fb_coord_t row, fb_coord_t col, + uint8_t *buffer, + size_t npixels); + +/* LCD Configuration */ + +static int stm3210e_getvideoinfo(struct lcd_dev_s *dev, + struct fb_videoinfo_s *vinfo); +static int stm3210e_getplaneinfo(struct lcd_dev_s *dev, + unsigned int planeno, + struct lcd_planeinfo_s *pinfo); + +/* LCD RGB Mapping */ + +#ifdef CONFIG_FB_CMAP +# error "RGB color mapping not supported by this driver" +#endif + +/* Cursor Controls */ + +#ifdef CONFIG_FB_HWCURSOR +# error "Cursor control not supported by this driver" +#endif + +/* LCD Specific Controls */ + +static int stm3210e_getpower(struct lcd_dev_s *dev); +static int stm3210e_setpower(struct lcd_dev_s *dev, int power); +static int stm3210e_getcontrast(struct lcd_dev_s *dev); +static int stm3210e_setcontrast(struct lcd_dev_s *dev, + unsigned int contrast); + +/* LCD Power Management */ + +#ifdef CONFIG_PM +static void stm3210e_pm_notify(struct pm_callback_s *cb, int domain, + enum pm_state_e pmstate); +static int stm3210e_pm_prepare(struct pm_callback_s *cb, int domain, + enum pm_state_e pmstate); +#endif + +/* Initialization */ + +static inline void stm3210e_lcdinitialize(void); +#ifdef CONFIG_STM3210E_LCD_BACKLIGHT +static void stm3210e_backlight(void); +#else +# define stm3210e_backlight() +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* This is working memory allocated by the LCD driver for each LCD device + * and for each color plane. This memory will hold one raster line of data. + * The size of the allocated run buffer must therefore be at least + * (bpp * xres / 8). Actual alignment of the buffer must conform to the + * bitwidth of the underlying pixel type. + * + * If there are multiple planes, they may share the same working buffer + * because different planes will not be operate on concurrently. However, + * if there are multiple LCD devices, they must each have unique run buffers. + */ + +static uint16_t g_runbuffer[STM3210E_XRES]; + +/* This structure describes the overall LCD video controller */ + +static const struct fb_videoinfo_s g_videoinfo = +{ + .fmt = STM3210E_COLORFMT, /* Color format: RGB16-565: RRRR RGGG GGGB BBBB */ + .xres = STM3210E_XRES, /* Horizontal resolution in pixel columns */ + .yres = STM3210E_YRES, /* Vertical resolution in pixel rows */ + .nplanes = 1, /* Number of color planes supported */ +}; + +/* This is the standard, NuttX Plane information object */ + +static const struct lcd_planeinfo_s g_planeinfo = +{ + .putrun = stm3210e_putrun, /* Put a run into LCD memory */ + .getrun = stm3210e_getrun, /* Get a run from LCD memory */ + .buffer = (uint8_t *)g_runbuffer, /* Run scratch buffer */ + .bpp = STM3210E_BPP, /* Bits-per-pixel */ +}; + +/* This is the standard, NuttX LCD driver object */ + +static struct stm3210e_dev_s g_lcddev = +{ + .dev = + { + /* LCD Configuration */ + + .getvideoinfo = stm3210e_getvideoinfo, + .getplaneinfo = stm3210e_getplaneinfo, + + /* LCD RGB Mapping -- Not supported */ + + /* Cursor Controls -- Not supported */ + + /* LCD Specific Controls */ + + .getpower = stm3210e_getpower, + .setpower = stm3210e_setpower, + .getcontrast = stm3210e_getcontrast, + .setcontrast = stm3210e_setcontrast, + }, +}; + +#ifdef CONFIG_PM +static struct pm_callback_s g_lcdcb = +{ + .notify = stm3210e_pm_notify, + .prepare = stm3210e_pm_prepare, +}; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm3210e_writereg + * + * Description: + * Write to an LCD register + * + ****************************************************************************/ + +static void stm3210e_writereg(uint8_t regaddr, uint16_t regval) +{ + /* Write the register address then write the register value */ + + LCD->address = regaddr; + LCD->value = regval; +} + +/**************************************************************************** + * Name: stm3210e_readreg + * + * Description: + * Read from an LCD register + * + ****************************************************************************/ + +static uint16_t stm3210e_readreg(uint8_t regaddr) +{ + /* Write the register address then read the register value */ + + LCD->address = regaddr; + return LCD->value; +} + +/**************************************************************************** + * Name: stm3210e_gramselect + * + * Description: + * Setup to read or write multiple pixels to the GRAM memory + * + ****************************************************************************/ + +static inline void stm3210e_gramselect(void) +{ + LCD->address = LCD_REG_34; +} + +/**************************************************************************** + * Name: stm3210e_writegram + * + * Description: + * Write one pixel to the GRAM memory + * + ****************************************************************************/ + +static inline void stm3210e_writegram(uint16_t rgbval) +{ + /* Write the value (GRAM register already selected) */ + + LCD->value = rgbval; +} + +/**************************************************************************** + * Name: stm3210e_readsetup / stm3210e_readnosetup + * + * Description: + * Prime the operation by reading one pixel from the GRAM memory if + * necessary for this LCD type. When reading 16-bit gram data, there may + * be some shifts in the returned data: + * + * - SPFD5408B: There appears to be a 5-bit shift in the returned data. + * - R61580: There is a 16-bit (1 pixel) shift in the returned data. + * - AM240320: Unknown -- assuming no shift in the return data + * + ****************************************************************************/ + +/* Used for SPFD5408B and R61580 */ + +#if !defined(CONFIG_STM3210E_SPFD5408B_DISABLE) || !defined(CONFIG_STM3210E_R61580_DISABLE) +static void stm3210e_readsetup(uint16_t *accum) +{ + /* Read-ahead one pixel */ + + *accum = LCD->value; +} +#endif + +/* Used only for AM240320 */ + +#ifndef CONFIG_STM3210E_AM240320_DISABLE +static void stm3210e_readnosetup(uint16_t *accum) +{ +} +#endif + +/**************************************************************************** + * Name: stm3210e_readshift / stm3210e_readnoshift + * + * Description: + * Read one correctly aligned pixel from the GRAM memory. Possibly + * shifting the data and possibly swapping red and green components. + * + * - SPFD5408B: There appears to be a 5-bit shift in the returned data. + * Red and green appear to be swapped on read-back as well + * - R61580: There is a 16-bit (1 pixel) shift in the returned data. + * All colors in the normal order + * - AM240320: Unknown -- assuming colors are in the color order + * + ****************************************************************************/ + +/* This version is used only for the SPFD5408B. It shifts the data by + * 5-bits and swaps red and green + */ + +#ifndef CONFIG_STM3210E_SPFD5408B_DISABLE +static uint16_t stm3210e_readshift(uint16_t *accum) +{ + uint16_t red; + uint16_t green; + uint16_t blue; + + /* Read the value (GRAM register already selected) */ + + uint16_t next = LCD->value; + + /* Return previous bits 0-10 as bits 6-15 and next data bits 11-15 as + * bits 0-5 + * + * xxxx xPPP PPPP PPPP + * NNNN Nxxx xxxx xxxx + * + * Assuming that SPFD5408B_RDSHIFT == 5 + */ + + uint16_t value = *accum << SPFD5408B_RDSHIFT | + next >> (16 - SPFD5408B_RDSHIFT); + + /* Save the value for the next time we are called */ + + *accum = next; + + /* Tear the RGB655 apart. Swap read and green */ + + red = (value << (11 - 5)) & 0xf800; /* Move bits 5-9 to 11-15 */ + green = (value >> (10 - 5)) & 0x07e0; /* Move bits 10-15 to bits 5-10 */ + blue = value & 0x001f; /* Blue is in the right place */ + + /* And put the RGB565 back together */ + + value = red | green | blue; + + /* This is weird... If blue is zero, then red+green values are off by 0x20. + * Except that both 0x0000 and 0x0020 can map to 0x0000. Need to revisit + * this!!!!!!!!!!! I might be misinterpreting some of the data that I + * have. + */ + +#if 0 /* REVISIT */ + if (value != 0 && blue == 0) + { + value += 0x20; + } +#endif + + return value; +} +#endif + +/* This version is used for the R61580 and for the AM240320. It neither + * shifts nor swaps colors. + */ + +#if !defined(CONFIG_STM3210E_R61580_DISABLE) || !defined(CONFIG_STM3210E_AM240320_DISABLE) +static uint16_t stm3210e_readnoshift(uint16_t *accum) +{ + /* Read the value (GRAM register already selected) */ + + return LCD->value; +} +#endif + +/**************************************************************************** + * Name: stm3210e_setcursor + * + * Description: + * Set the cursor position. In landscape mode, the "column" is actually + * the physical Y position and the "row" is the physical X position. + * + ****************************************************************************/ + +static void stm3210e_setcursor(uint16_t col, uint16_t row) +{ + stm3210e_writereg(LCD_REG_32, row); /* GRAM horizontal address */ + stm3210e_writereg(LCD_REG_33, col); /* GRAM vertical address */ +} + +/**************************************************************************** + * Name: stm3210e_putrun + * + * Description: + * This method can be used to write a partial raster line to the LCD: + * + * dev - The lcd device + * row - Starting row to write to (range: 0 <= row < yres) + * col - Starting column to write to (range: 0 <= col <= xres-npixels) + * buffer - The buffer containing the run to be written to the LCD + * npixels - The number of pixels to write to the LCD + * (range: 0 < npixels <= xres-col) + * + ****************************************************************************/ + +static int stm3210e_putrun(struct lcd_dev_s *dev, + fb_coord_t row, fb_coord_t col, + const uint8_t *buffer, + size_t npixels) +{ + const uint16_t *src = (const uint16_t *)buffer; + int i; + + /* Buffer must be provided and aligned to a 16-bit address boundary */ + + lcdinfo("row: %d col: %d npixels: %d\n", row, col, npixels); + DEBUGASSERT(buffer && ((uintptr_t)buffer & 1) == 0); + + /* Write the run to GRAM. */ + +#ifdef CONFIG_LCD_LANDSCAPE + /* Convert coordinates -- Which edge of the display is the "top?" Here the + * edge with the simplest conversion is used. + */ + + col = (STM3210E_XRES - 1) - col; + + /* Set the cursor position */ + + stm3210e_setcursor(col, row); + + /* Then write the GRAM data, auto-decrementing X */ + + stm3210e_gramselect(); + for (i = 0; i < npixels; i++) + { + /* Write the next pixel to this position (auto-decrements to the next + * column) + */ + + stm3210e_writegram(*src++); + } +#elif defined(CONFIG_LCD_PORTRAIT) + /* Convert coordinates. (Swap row and column. This is done implicitly). */ + + /* Then write the GRAM data, manually incrementing Y (which is col) */ + + for (i = 0; i < npixels; i++) + { + /* Write the next pixel to this position */ + + stm3210e_setcursor(row, col); + stm3210e_gramselect(); + stm3210e_writegram(*src++); + + /* Increment to next column */ + + col++; + } +#else /* CONFIG_LCD_RPORTRAIT */ + /* Convert coordinates. (Swap row and column. This is done implicitly). + * Which edge of the display is the "top"? + */ + + col = (STM3210E_XRES - 1) - col; + row = (STM3210E_YRES - 1) - row; + + /* Then write the GRAM data, manually incrementing Y (which is col) */ + + for (i = 0; i < npixels; i++) + { + /* Write the next pixel to this position */ + + stm3210e_setcursor(row, col); + stm3210e_gramselect(); + stm3210e_writegram(*src++); + + /* Decrement to next column */ + + col--; + } +#endif + + return OK; +} + +/**************************************************************************** + * Name: stm3210e_getrun + * + * Description: + * This method can be used to read a partial raster line from the LCD: + * + * dev - The lcd device + * row - Starting row to read from (range: 0 <= row < yres) + * col - Starting column to read read (range: 0 <= col <= xres-npixels) + * buffer - The buffer in which to return the run read from the LCD + * npixels - The number of pixels to read from the LCD + * (range: 0 < npixels <= xres-col) + * + ****************************************************************************/ + +static int stm3210e_getrun(struct lcd_dev_s *dev, + fb_coord_t row, fb_coord_t col, + uint8_t *buffer, + size_t npixels) +{ + uint16_t *dest = (uint16_t *)buffer; + void (*readsetup)(uint16_t *accum); + uint16_t (*readgram)(uint16_t *accum); + uint16_t accum; + int i; + + /* Buffer must be provided and aligned to a 16-bit address boundary */ + + lcdinfo("row: %d col: %d npixels: %d\n", row, col, npixels); + DEBUGASSERT(buffer && ((uintptr_t)buffer & 1) == 0); + + /* Configure according to the LCD type */ + + switch (g_lcddev.type) + { +#ifndef CONFIG_STM3210E_SPFD5408B_DISABLE + case LCD_TYPE_SPFD5408B: + readsetup = stm3210e_readsetup; + readgram = stm3210e_readshift; + break; +#endif + +#ifndef CONFIG_STM3210E_R61580_DISABLE + case LCD_TYPE_R61580: + readsetup = stm3210e_readsetup; + readgram = stm3210e_readnoshift; + break; +#endif + +#ifndef CONFIG_STM3210E_AM240320_DISABLE + case LCD_TYPE_AM240320: + readsetup = stm3210e_readnosetup; + readgram = stm3210e_readnoshift; + break; +#endif + + default: /* Shouldn't happen */ + return -ENOSYS; + } + + /* Read the run from GRAM. */ + +#ifdef CONFIG_LCD_LANDSCAPE + /* Convert coordinates -- Which edge of the display is the "top?" Here the + * edge with the simplest conversion is used. + */ + + col = (STM3210E_XRES - 1) - col; + + /* Set the cursor position */ + + stm3210e_setcursor(col, row); + + /* Then read the GRAM data, auto-decrementing Y */ + + stm3210e_gramselect(); + + /* Prime the pump for unaligned read data */ + + readsetup(&accum); + + for (i = 0; i < npixels; i++) + { + /* Read the next pixel from this position (autoincrements to the next + * row) + */ + + *dest++ = readgram(&accum); + } +#elif defined(CONFIG_LCD_PORTRAIT) + /* Convert coordinates (Swap row and column. This is done implicitly). */ + + /* Then read the GRAM data, manually incrementing Y (which is col) */ + + for (i = 0; i < npixels; i++) + { + /* Read the next pixel from this position */ + + stm3210e_setcursor(row, col); + stm3210e_gramselect(); + readsetup(&accum); + *dest++ = readgram(&accum); + + /* Increment to next column */ + + col++; + } +#else /* CONFIG_LCD_RPORTRAIT */ + /* Convert coordinates. (Swap row and column. This is done implicitly). + * Which edge of the display is the "top"? + */ + + col = (STM3210E_XRES - 1) - col; + row = (STM3210E_YRES - 1) - row; + + /* Then write the GRAM data, manually incrementing Y (which is col) */ + + for (i = 0; i < npixels; i++) + { + /* Write the next pixel to this position */ + + stm3210e_setcursor(row, col); + stm3210e_gramselect(); + readsetup(&accum); + *dest++ = readgram(&accum); + + /* Decrement to next column */ + + col--; + } +#endif + + return OK; +} + +/**************************************************************************** + * Name: stm3210e_getvideoinfo + * + * Description: + * Get information about the LCD video controller configuration. + * + ****************************************************************************/ + +static int stm3210e_getvideoinfo(struct lcd_dev_s *dev, + struct fb_videoinfo_s *vinfo) +{ + DEBUGASSERT(dev && vinfo); + ginfo("fmt: %d xres: %d yres: %d nplanes: %d\n", + g_videoinfo.fmt, g_videoinfo.xres, + g_videoinfo.yres, g_videoinfo.nplanes); + memcpy(vinfo, &g_videoinfo, sizeof(struct fb_videoinfo_s)); + return OK; +} + +/**************************************************************************** + * Name: stm3210e_getplaneinfo + * + * Description: + * Get information about the configuration of each LCD color plane. + * + ****************************************************************************/ + +static int stm3210e_getplaneinfo(struct lcd_dev_s *dev, + unsigned int planeno, + struct lcd_planeinfo_s *pinfo) +{ + DEBUGASSERT(dev && pinfo && planeno == 0); + ginfo("planeno: %d bpp: %d\n", planeno, g_planeinfo.bpp); + memcpy(pinfo, &g_planeinfo, sizeof(struct lcd_planeinfo_s)); + pinfo->dev = dev; + return OK; +} + +/**************************************************************************** + * Name: stm3210e_getpower + * + * Description: + * Get the LCD panel power status (0: full off - CONFIG_LCD_MAXPOWER: + * full on). On backlit LCDs, this setting may correspond to the backlight + * setting. + * + ****************************************************************************/ + +static int stm3210e_getpower(struct lcd_dev_s *dev) +{ + ginfo("power: %d\n", 0); + return g_lcddev.power; +} + +/**************************************************************************** + * Name: stm3210e_poweroff + * + * Description: + * Enable/disable LCD panel power (0: full off - CONFIG_LCD_MAXPOWER: + * full on). On backlit LCDs, this setting may correspond to the backlight + * setting. + * + ****************************************************************************/ + +static int stm3210e_poweroff(void) +{ + /* Turn the display off */ + + stm3210e_writereg(LCD_REG_7, 0); + + /* Disable timer 1 clocking */ + +#if defined(CONFIG_STM3210E_LCD_BACKLIGHT) +# if defined(CONFIG_STM3210E_LCD_PWM) + modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM1EN, 0); +# endif + + /* Configure the PA8 pin as an output */ + + stm32_configgpio(GPIO_LCD_BACKLIGHT); + + /* Turn the backlight off */ + + stm32_gpiowrite(GPIO_LCD_BACKLIGHT, false); +#endif + + /* Remember the power off state */ + + g_lcddev.power = 0; + return OK; +} + +/**************************************************************************** + * Name: stm3210e_setpower + * + * Description: + * Enable/disable LCD panel power (0: full off - CONFIG_LCD_MAXPOWER: + * full on). On backlit LCDs, this setting may correspond to the backlight + * setting. + * + ****************************************************************************/ + +static int stm3210e_setpower(struct lcd_dev_s *dev, int power) +{ + ginfo("power: %d\n", power); + DEBUGASSERT((unsigned)power <= CONFIG_LCD_MAXPOWER); + + /* Set new power level */ + + if (power > 0) + { +#if defined(CONFIG_STM3210E_LCD_BACKLIGHT) && defined(CONFIG_STM3210E_LCD_PWM) + uint32_t frac; + uint32_t duty; + + /* If we are coming up from the power off state, then re-configure + * the timer + */ + + if (g_lcddev.power == 0) + { + stm3210e_backlight(); + } + + /* Make sure that the power value is within range */ + + if (power > CONFIG_LCD_MAXPOWER) + { + power = CONFIG_LCD_MAXPOWER; + } + + /* Calculate the new backlight duty. It is a faction of the timer1 + * period based on the ration of the current power setting to the + * maximum power setting. + */ + + frac = (power << 16) / CONFIG_LCD_MAXPOWER; + duty = (g_lcddev.reload * frac) >> 16; + if (duty > 0) + { + duty--; + } + + putreg16((uint16_t)duty, STM32_TIM1_CCR1); +#else + /* Turn the backlight on */ + + stm32_gpiowrite(GPIO_LCD_BACKLIGHT, true); +#endif + /* Then turn the display on */ + +#ifndef CONFIG_STM3210E_AM240320_DISABLE +# if !defined (CONFIG_STM3210E_SPFD5408B_DISABLE) || !defined(CONFIG_STM3210E_R61580_DISABLE) + stm3210e_writereg(LCD_REG_7, + g_lcddev.type == LCD_TYPE_AM240320 ? + 0x0173 : 0x0112); +# else + stm3210e_writereg(LCD_REG_7, 0x0173); +# endif +#else + stm3210e_writereg(LCD_REG_7, 0x0112); +#endif + g_lcddev.power = power; + } + else + { + /* Turn the display off */ + + stm3210e_poweroff(); + } + + return OK; +} + +/**************************************************************************** + * Name: stm3210e_getcontrast + * + * Description: + * Get the current contrast setting (0-CONFIG_LCD_MAXCONTRAST). + * + ****************************************************************************/ + +static int stm3210e_getcontrast(struct lcd_dev_s *dev) +{ + ginfo("Not implemented\n"); + return -ENOSYS; +} + +/**************************************************************************** + * Name: stm3210e_setcontrast + * + * Description: + * Set LCD panel contrast (0-CONFIG_LCD_MAXCONTRAST). + * + ****************************************************************************/ + +static int stm3210e_setcontrast(struct lcd_dev_s *dev, unsigned int contrast) +{ + ginfo("contrast: %d\n", contrast); + return -ENOSYS; +} + +/**************************************************************************** + * Name: stm3210e_pm_notify + * + * Description: + * Notify the driver of new power state. This callback is called after + * all drivers have had the opportunity to prepare for the new power state. + * + * Input Parameters: + * + * cb - Returned to the driver. The driver version of the callback + * structure may include additional, driver-specific state data at + * the end of the structure. + * + * pmstate - Identifies the new PM state + * + * Returned Value: + * None - The driver already agreed to transition to the low power + * consumption state when when it returned OK to the prepare() call. + * + * + ****************************************************************************/ + +#ifdef CONFIG_PM +static void stm3210e_pm_notify(struct pm_callback_s *cb, int domain, + enum pm_state_e pmstate) +{ +#ifdef CONFIG_STM3210E_LCD_PWM + uint32_t frac; + uint32_t duty; +#endif + + switch (pmstate) + { + case PM_NORMAL: + { + /* Restore normal LCD operation */ + +#ifdef CONFIG_STM3210E_LCD_PWM + frac = (g_lcddev.power << 16) / CONFIG_LCD_MAXPOWER; + duty = (g_lcddev.reload * frac) >> 16; + if (duty > 0) + { + duty--; + } + + putreg16((uint16_t)duty, STM32_TIM1_CCR1); +#endif + } + break; + + case PM_IDLE: + { + /* Entering IDLE mode - Reduce LCD light */ + +#ifdef CONFIG_STM3210E_LCD_PWM + frac = (g_lcddev.power << 16) / CONFIG_LCD_MAXPOWER; + duty = (g_lcddev.reload * frac) >> 16; + if (duty > 0) + { + duty--; + } + + /* Reduce the LCD backlight to 50% of the MAXPOWER */ + + duty >>= 1; + putreg16((uint16_t)duty, STM32_TIM1_CCR1); +#endif + } + break; + + case PM_STANDBY: + { + /* Entering STANDBY mode - Turn display backlight off */ + +#ifdef CONFIG_STM3210E_LCD_PWM + putreg16(0, STM32_TIM1_CCR1); +#endif + } + break; + + case PM_SLEEP: + { + /* Entering SLEEP mode - Turn off LCD */ + + if (g_lcddev.type == LCD_TYPE_AM240320) + { + /* Display off sequence */ + + stm3210e_writereg(LCD_REG_0, 0xa0); /* White display mode setting */ + up_mdelay(10); /* Wait for 2 frame scan */ + stm3210e_writereg(LCD_REG_59, 0x00); /* Gate scan stop */ + + /* Power off sequence */ + + stm3210e_writereg(LCD_REG_30, 0x09); /* VCOM stop */ + stm3210e_writereg(LCD_REG_27, 0x0e); /* VS/VDH turn off */ + stm3210e_writereg(LCD_REG_24, 0xc0); /* CP1, CP2, CP3 turn off */ + up_mdelay(10); /* wait 10 ms */ + + stm3210e_writereg(LCD_REG_24, 0x00); /* VR1 / VR2 off */ + stm3210e_writereg(LCD_REG_28, 0x30); /* Step up circuit operating current stop */ + up_mdelay(10); + + stm3210e_poweroff(); + stm3210e_writereg(LCD_REG_0, 0xa0); /* White display mode setting */ + up_mdelay(10); /* Wait for 2 frame scan */ + + stm3210e_writereg(LCD_REG_59, 0x00); /* Gate scan stop */ + } + else + { + stm3210e_poweroff(); + } + } + break; + + default: + { + /* Should not get here */ + } + break; + } +} +#endif + +/**************************************************************************** + * Name: stm3210e_pm_prepare + * + * Description: + * Request the driver to prepare for a new power state. This is a warning + * that the system is about to enter into a new power state. The driver + * should begin whatever operations that may be required to enter power + * state. The driver may abort the state change mode by returning a + * non-zero value from the callback function. + * + * Input Parameters: + * + * cb - Returned to the driver. The driver version of the callback + * structure may include additional, driver-specific state data at + * the end of the structure. + * + * pmstate - Identifies the new PM state + * + * Returned Value: + * Zero - (OK) means the event was successfully processed and that the + * driver is prepared for the PM state change. + * + * Non-zero - means that the driver is not prepared to perform the tasks + * needed achieve this power setting and will cause the state + * change to be aborted. NOTE: The prepare() method will also + * be called when reverting from lower back to higher power + * consumption modes (say because another driver refused a + * lower power state change). Drivers are not permitted to + * return non-zero values when reverting back to higher power + * consumption modes! + * + * + ****************************************************************************/ + +#ifdef CONFIG_PM +static int stm3210e_pm_prepare(struct pm_callback_s *cb, int domain, + enum pm_state_e pmstate) +{ + /* No preparation to change power modes is required by the LCD driver. + * We always accept the state change by returning OK. + */ + + return OK; +} +#endif + +/**************************************************************************** + * Name: stm3210e_lcdinitialize + * + * Description: + * Set LCD panel contrast (0-CONFIG_LCD_MAXCONTRAST). + * + ****************************************************************************/ + +static inline void stm3210e_lcdinitialize(void) +{ + uint16_t id; + + /* Check if the LCD is Orise Tech SPFD5408B Controller (or the compatible + * RenesasSP R61580). + */ + + id = stm3210e_readreg(LCD_REG_0); + lcdinfo("LCD ID: %04x\n", id); + + /* Check if the ID is for the SPFD5408B */ + +#if !defined(CONFIG_STM3210E_SPFD5408B_DISABLE) + if (id == SPFD5408B_ID) + { + /* Set the LCD type for the SPFD5408B */ + + g_lcddev.type = LCD_TYPE_SPFD5408B; + lcdinfo("LCD type: %d\n", g_lcddev.type); + + /* Start Initial Sequence */ + + stm3210e_writereg(LCD_REG_1, 0x0100); /* Set SS bit */ + stm3210e_writereg(LCD_REG_2, 0x0700); /* Set 1 line inversion */ + stm3210e_writereg(LCD_REG_3, 0x1030); /* Set GRAM write direction and BGR=1. */ + stm3210e_writereg(LCD_REG_4, 0x0000); /* Resize register */ + stm3210e_writereg(LCD_REG_8, 0x0202); /* Set the back porch and front porch */ + stm3210e_writereg(LCD_REG_9, 0x0000); /* Set non-display area refresh cycle ISC[3:0] */ + stm3210e_writereg(LCD_REG_10, 0x0000); /* FMARK function */ + stm3210e_writereg(LCD_REG_12, 0x0000); /* RGB 18-bit System interface setting */ + stm3210e_writereg(LCD_REG_13, 0x0000); /* Frame marker Position */ + stm3210e_writereg(LCD_REG_15, 0x0000); /* RGB interface polarity, no impact */ + + /* Power On sequence */ + + stm3210e_writereg(LCD_REG_16, 0x0000); /* SAP, BT[3:0], AP, DSTB, SLP, STB */ + stm3210e_writereg(LCD_REG_17, 0x0000); /* DC1[2:0], DC0[2:0], VC[2:0] */ + stm3210e_writereg(LCD_REG_18, 0x0000); /* VREG1OUT voltage */ + stm3210e_writereg(LCD_REG_19, 0x0000); /* VDV[4:0] for VCOM amplitude */ + up_mdelay(200); /* Dis-charge capacitor power voltage (200ms) */ + + stm3210e_writereg(LCD_REG_17, 0x0007); /* DC1[2:0], DC0[2:0], VC[2:0] */ + up_mdelay(50); + + stm3210e_writereg(LCD_REG_16, 0x12b0); /* SAP, BT[3:0], AP, DSTB, SLP, STB */ + up_mdelay(50); + + stm3210e_writereg(LCD_REG_18, 0x01bd); /* External reference voltage= Vci */ + up_mdelay(50); + + stm3210e_writereg(LCD_REG_19, 0x1400); /* VDV[4:0] for VCOM amplitude */ + stm3210e_writereg(LCD_REG_41, 0x000e); /* VCM[4:0] for VCOMH */ + up_mdelay(50); + + stm3210e_writereg(LCD_REG_32, 0x0000); /* GRAM horizontal Address */ + stm3210e_writereg(LCD_REG_33, 0x013f); /* GRAM Vertical Address */ + + /* Adjust the Gamma Curve (SPFD5408B) */ + + stm3210e_writereg(LCD_REG_48, 0x0b0d); + stm3210e_writereg(LCD_REG_49, 0x1923); + stm3210e_writereg(LCD_REG_50, 0x1c26); + stm3210e_writereg(LCD_REG_51, 0x261c); + stm3210e_writereg(LCD_REG_52, 0x2419); + stm3210e_writereg(LCD_REG_53, 0x0d0b); + stm3210e_writereg(LCD_REG_54, 0x1006); + stm3210e_writereg(LCD_REG_55, 0x0610); + stm3210e_writereg(LCD_REG_56, 0x0706); + stm3210e_writereg(LCD_REG_57, 0x0304); + stm3210e_writereg(LCD_REG_58, 0x0e05); + stm3210e_writereg(LCD_REG_59, 0x0e01); + stm3210e_writereg(LCD_REG_60, 0x010e); + stm3210e_writereg(LCD_REG_61, 0x050e); + stm3210e_writereg(LCD_REG_62, 0x0403); + stm3210e_writereg(LCD_REG_63, 0x0607); + + /* Set GRAM area */ + + stm3210e_writereg(LCD_REG_80, 0x0000); /* Horizontal GRAM Start Address */ + stm3210e_writereg(LCD_REG_81, 0x00ef); /* Horizontal GRAM End Address */ + stm3210e_writereg(LCD_REG_82, 0x0000); /* Vertical GRAM Start Address */ + stm3210e_writereg(LCD_REG_83, 0x013f); /* Vertical GRAM End Address */ + stm3210e_writereg(LCD_REG_96, 0xa700); /* Gate Scan Line */ + stm3210e_writereg(LCD_REG_97, 0x0001); /* NDL, VLE, REV */ + stm3210e_writereg(LCD_REG_106, 0x0000); /* set scrolling line */ + + /* Partial Display Control */ + + stm3210e_writereg(LCD_REG_128, 0x0000); + stm3210e_writereg(LCD_REG_129, 0x0000); + stm3210e_writereg(LCD_REG_130, 0x0000); + stm3210e_writereg(LCD_REG_131, 0x0000); + stm3210e_writereg(LCD_REG_132, 0x0000); + stm3210e_writereg(LCD_REG_133, 0x0000); + + /* Panel Control */ + + stm3210e_writereg(LCD_REG_144, 0x0010); + stm3210e_writereg(LCD_REG_146, 0x0000); + stm3210e_writereg(LCD_REG_147, 0x0003); + stm3210e_writereg(LCD_REG_149, 0x0110); + stm3210e_writereg(LCD_REG_151, 0x0000); + stm3210e_writereg(LCD_REG_152, 0x0000); + + /* Set GRAM write direction and BGR=1 + * I/D=01 (Horizontal : increment, Vertical : decrement) + * AM=1 (address is updated in vertical writing direction) + */ + + stm3210e_writereg(LCD_REG_3, 0x1018); + stm3210e_writereg(LCD_REG_7, 0); /* Display OFF */ + } + else +#endif + + /* Check if the ID is for the almost compatible R61580 */ + +#if !defined(CONFIG_STM3210E_R61580_DISABLE) + if (id == R61580_ID) + { + /* Set the LCD type for the R61580 */ + + g_lcddev.type = LCD_TYPE_R61580; + lcdinfo("LCD type: %d\n", g_lcddev.type); + + /* Start Initial Sequence */ + + stm3210e_writereg(LCD_REG_0, 0x0000); + stm3210e_writereg(LCD_REG_0, 0x0000); + up_mdelay(100); + stm3210e_writereg(LCD_REG_0, 0x0000); + stm3210e_writereg(LCD_REG_0, 0x0000); + stm3210e_writereg(LCD_REG_0, 0x0000); + stm3210e_writereg(LCD_REG_0, 0x0000); + stm3210e_writereg(LCD_REG_164, 0x0001); + up_mdelay(100); + stm3210e_writereg(LCD_REG_96, 0xa700); + stm3210e_writereg(LCD_REG_8, 0x0808); + + /* Gamma Setting */ + + stm3210e_writereg(LCD_REG_48, 0x0203); + stm3210e_writereg(LCD_REG_49, 0x080f); + stm3210e_writereg(LCD_REG_50, 0x0401); + stm3210e_writereg(LCD_REG_51, 0x050b); + stm3210e_writereg(LCD_REG_52, 0x3330); + stm3210e_writereg(LCD_REG_53, 0x0b05); + stm3210e_writereg(LCD_REG_54, 0x0005); + stm3210e_writereg(LCD_REG_55, 0x0f08); + stm3210e_writereg(LCD_REG_56, 0x0302); + stm3210e_writereg(LCD_REG_57, 0x3033); + + /* Power Setting */ + + stm3210e_writereg(LCD_REG_144, 0x0018); /* 80Hz */ + stm3210e_writereg(LCD_REG_16, 0x0530); /* BT, AP */ + stm3210e_writereg(LCD_REG_17, 0x0237); /* DC1,DC0,VC */ + stm3210e_writereg(LCD_REG_18, 0x01bf); + stm3210e_writereg(LCD_REG_19, 0x1000); /* VCOM */ + up_mdelay(200); + + stm3210e_writereg(LCD_REG_1, 0x0100); /* Set SS bit */ + stm3210e_writereg(LCD_REG_2, 0x0200); + stm3210e_writereg(LCD_REG_3, 0x1030); /* Set GRAM write direction and BGR=1. */ + stm3210e_writereg(LCD_REG_9, 0x0001); + stm3210e_writereg(LCD_REG_10, 0x0008); + stm3210e_writereg(LCD_REG_12, 0x0000); /* RGB 18-bit System interface setting */ + stm3210e_writereg(LCD_REG_13, 0xd000); + stm3210e_writereg(LCD_REG_14, 0x0030); + stm3210e_writereg(LCD_REG_15, 0x0000); /* RGB interface polarity, no impact */ + stm3210e_writereg(LCD_REG_32, 0x0000); /* H Start */ + stm3210e_writereg(LCD_REG_33, 0x0000); /* V Start */ + stm3210e_writereg(LCD_REG_41, 0x002e); + stm3210e_writereg(LCD_REG_80, 0x0000); /* Horizontal GRAM Start Address */ + stm3210e_writereg(LCD_REG_81, 0x00ef); /* Horizontal GRAM End Address */ + stm3210e_writereg(LCD_REG_82, 0x0000); /* Vertical GRAM Start Address */ + stm3210e_writereg(LCD_REG_83, 0x013f); /* Vertical GRAM End Address */ + stm3210e_writereg(LCD_REG_97, 0x0001); /* NDL, VLE, REV */ + stm3210e_writereg(LCD_REG_106, 0x0000); /* set scrolling line */ + stm3210e_writereg(LCD_REG_128, 0x0000); + stm3210e_writereg(LCD_REG_129, 0x0000); + stm3210e_writereg(LCD_REG_130, 0x005f); + stm3210e_writereg(LCD_REG_147, 0x0701); + + stm3210e_writereg(LCD_REG_7, 0x0000); /* Display OFF */ + } + else +#endif + { +#ifndef CONFIG_STM3210E_AM240320_DISABLE + /* Set the LCD type for the AM240320 */ + + g_lcddev.type = LCD_TYPE_AM240320; + lcdinfo("LCD type: %d\n", g_lcddev.type); + + /* Start Initial Sequence */ + + stm3210e_writereg(LCD_REG_229, 0x8000); /* Set the internal vcore voltage */ + stm3210e_writereg(LCD_REG_0, 0x0001); /* Start internal OSC. */ + stm3210e_writereg(LCD_REG_1, 0x0100); /* Set SS and SM bit */ + stm3210e_writereg(LCD_REG_2, 0x0700); /* Set 1 line inversion */ + stm3210e_writereg(LCD_REG_3, 0x1030); /* Set GRAM write direction and BGR=1. */ + stm3210e_writereg(LCD_REG_4, 0x0000); /* Resize register */ + stm3210e_writereg(LCD_REG_8, 0x0202); /* Set the back porch and front porch */ + stm3210e_writereg(LCD_REG_9, 0x0000); /* Set non-display area refresh cycle ISC[3:0] */ + stm3210e_writereg(LCD_REG_10, 0x0000); /* FMARK function */ + stm3210e_writereg(LCD_REG_12, 0x0000); /* RGB interface setting */ + stm3210e_writereg(LCD_REG_13, 0x0000); /* Frame marker Position */ + stm3210e_writereg(LCD_REG_15, 0x0000); /* RGB interface polarity */ + + /* Power On sequence */ + + stm3210e_writereg(LCD_REG_16, 0x0000); /* SAP, BT[3:0], AP, DSTB, SLP, STB */ + stm3210e_writereg(LCD_REG_17, 0x0000); /* DC1[2:0], DC0[2:0], VC[2:0] */ + stm3210e_writereg(LCD_REG_18, 0x0000); /* VREG1OUT voltage */ + stm3210e_writereg(LCD_REG_19, 0x0000); /* VDV[4:0] for VCOM amplitude */ + up_mdelay(200); /* Dis-charge capacitor power voltage (200ms) */ + + stm3210e_writereg(LCD_REG_16, 0x17b0); /* SAP, BT[3:0], AP, DSTB, SLP, STB */ + stm3210e_writereg(LCD_REG_17, 0x0137); /* DC1[2:0], DC0[2:0], VC[2:0] */ + up_mdelay(50); + + stm3210e_writereg(LCD_REG_18, 0x0139); /* VREG1OUT voltage */ + up_mdelay(50); + + stm3210e_writereg(LCD_REG_19, 0x1d00); /* VDV[4:0] for VCOM amplitude */ + stm3210e_writereg(LCD_REG_41, 0x0013); /* VCM[4:0] for VCOMH */ + up_mdelay(50); + + stm3210e_writereg(LCD_REG_32, 0x0000); /* GRAM horizontal Address */ + stm3210e_writereg(LCD_REG_33, 0x0000); /* GRAM Vertical Address */ + + /* Adjust the Gamma Curve */ + + stm3210e_writereg(LCD_REG_48, 0x0006); + stm3210e_writereg(LCD_REG_49, 0x0101); + stm3210e_writereg(LCD_REG_50, 0x0003); + stm3210e_writereg(LCD_REG_53, 0x0106); + stm3210e_writereg(LCD_REG_54, 0x0b02); + stm3210e_writereg(LCD_REG_55, 0x0302); + stm3210e_writereg(LCD_REG_56, 0x0707); + stm3210e_writereg(LCD_REG_57, 0x0007); + stm3210e_writereg(LCD_REG_60, 0x0600); + stm3210e_writereg(LCD_REG_61, 0x020b); + + /* Set GRAM area */ + + stm3210e_writereg(LCD_REG_80, 0x0000); /* Horizontal GRAM Start Address */ + stm3210e_writereg(LCD_REG_81, 0x00ef); /* Horizontal GRAM End Address */ + stm3210e_writereg(LCD_REG_82, 0x0000); /* Vertical GRAM Start Address */ + stm3210e_writereg(LCD_REG_83, 0x013f); /* Vertical GRAM End Address */ + stm3210e_writereg(LCD_REG_96, 0x2700); /* Gate Scan Line */ + stm3210e_writereg(LCD_REG_97, 0x0001); /* NDL,VLE, REV */ + stm3210e_writereg(LCD_REG_106, 0x0000); /* Set scrolling line */ + + /* Partial Display Control */ + + stm3210e_writereg(LCD_REG_128, 0x0000); + stm3210e_writereg(LCD_REG_129, 0x0000); + stm3210e_writereg(LCD_REG_130, 0x0000); + stm3210e_writereg(LCD_REG_131, 0x0000); + stm3210e_writereg(LCD_REG_132, 0x0000); + stm3210e_writereg(LCD_REG_133, 0x0000); + + /* Panel Control */ + + stm3210e_writereg(LCD_REG_144, 0x0010); + stm3210e_writereg(LCD_REG_146, 0x0000); + stm3210e_writereg(LCD_REG_147, 0x0003); + stm3210e_writereg(LCD_REG_149, 0x0110); + stm3210e_writereg(LCD_REG_151, 0x0000); + stm3210e_writereg(LCD_REG_152, 0x0000); + + /* Set GRAM write direction and BGR = 1 + * + * I/D=01 (Horizontal : increment, Vertical : decrement) + * AM=1 (address is updated in vertical writing direction) + */ + + stm3210e_writereg(LCD_REG_3, 0x1018); + stm3210e_writereg(LCD_REG_7, 0); /* Display off */ +#else + lcderr("ERROR: Unsupported LCD type\n"); +#endif + } +} + +/**************************************************************************** + * Name: stm3210e_backlight + * + * Description: + * The LCD backlight is driven from PA8 which must be configured as TIM1 + * CH1. TIM1 must then be configured to output a clock on PA8; the duty + * of the clock determineds the backlight level. + * + ****************************************************************************/ + +#ifdef CONFIG_STM3210E_LCD_BACKLIGHT +static void stm3210e_backlight(void) +{ +#ifdef CONFIG_STM3210E_LCD_PWM + uint32_t prescaler; + uint32_t reload; + uint32_t timclk; + uint16_t bdtr; + uint16_t ccmr; + uint16_t ccer; + uint16_t cr2; + + /* Calculate the TIM1 prescaler value */ + + prescaler = (STM32_PCLK2_FREQUENCY / CONFIG_STM3210E_LCD_PWMFREQUENCY + + 65534) / 65535; + if (prescaler < 1) + { + prescaler = 1; + } + else if (prescaler > 65536) + { + prescaler = 65536; + } + + /* Calculate the TIM1 reload value */ + + timclk = STM32_PCLK2_FREQUENCY / prescaler; + reload = timclk / CONFIG_STM3210E_LCD_PWMFREQUENCY; + + if (reload < 1) + { + reload = 1; + } + else if (reload > 65535) + { + reload = 65535; + } + + g_lcddev.reload = reload; + + /* Configure PA8 as TIM1 CH1 output */ + + stm32_configgpio(GPIO_TIM1_CH1OUT); + + /* Enabled timer 1 clocking */ + + modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM1EN); + + /* Reset timer 1 */ + + modifyreg32(STM32_RCC_APB2RSTR, 0, RCC_APB2RSTR_TIM1RST); + modifyreg32(STM32_RCC_APB2RSTR, RCC_APB2RSTR_TIM1RST, 0); + + /* Reset the Counter Mode and set the clock division */ + + putreg16(0, STM32_TIM1_CR1); + + /* Set the Autoreload value */ + + putreg16(reload - 1, STM32_TIM1_ARR); + + /* Set the Prescaler value */ + + putreg16(prescaler - 1, STM32_TIM1_PSC); + + /* Generate an update event to reload the Prescaler value immediately */ + + putreg16(ATIM_EGR_UG, STM32_TIM1_EGR); + + /* Reset the Repetition Counter value */ + + putreg16(0, STM32_TIM1_RCR); + + /* Set the main output enable (MOE) bit and clear the OSSI and OSSR + * bits in the BDTR register. + */ + + bdtr = getreg16(STM32_TIM1_BDTR); + bdtr &= ~(ATIM_BDTR_OSSI | ATIM_BDTR_OSSR); + bdtr |= ATIM_BDTR_MOE; + putreg16(bdtr, STM32_TIM1_BDTR); + + /* Disable the Channel 1 */ + + ccer = getreg16(STM32_TIM1_CCER); + ccer &= ~ATIM_CCER_CC1E; + putreg16(ccer, STM32_TIM1_CCER); + + /* Get the TIM1 CR2 register value */ + + cr2 = getreg16(STM32_TIM1_CR2); + + /* Select the Output Compare Mode Bits */ + + ccmr = getreg16(STM32_TIM1_CCMR1); + ccmr &= ATIM_CCMR1_OC1M_MASK; + ccmr |= (ATIM_CCMR_MODE_PWM1 << ATIM_CCMR1_OC1M_SHIFT); + ccmr |= (ATIM_CCMR_CCS_CCOUT << ATIM_CCMR1_CC1S_SHIFT); + + /* Set the power to the minimum value */ + + g_lcddev.power = 0; + putreg16(0, STM32_TIM1_CCR1); + + /* Select the output polarity level == LOW and enable */ + + ccer |= (ATIM_CCER_CC1E); + + /* Reset the Output N Polarity level */ + + ccer &= ~(ATIM_CCER_CC1NP | ATIM_CCER_CC1NE); + + /* Reset the Output Compare and Output Compare N IDLE State */ + + cr2 &= ~(ATIM_CR2_OIS1 | ATIM_CR2_OIS1N); + + /* Write the timer configuration */ + + putreg16(cr2, STM32_TIM1_CR2); + putreg16(ccmr, STM32_TIM1_CCMR1); + putreg16(ccer, STM32_TIM1_CCER); + + /* Set the auto preload enable bit */ + + modifyreg16(STM32_TIM1_CR1, 0, ATIM_CR1_ARPE); + + /* Enable Backlight Timer */ + + ccer |= ATIM_CR1_CEN; + putreg16(ccer, STM32_TIM1_CR1); + + /* Dump timer1 registers */ + + lcdinfo("APB2ENR: %08" PRIx32 "\n", getreg32(STM32_RCC_APB2ENR)); + lcdinfo("CR1: %04" PRIx32 "\n", getreg32(STM32_TIM1_CR1)); + lcdinfo("CR2: %04" PRIx32 "\n", getreg32(STM32_TIM1_CR2)); + lcdinfo("SMCR: %04" PRIx32 "\n", getreg32(STM32_TIM1_SMCR)); + lcdinfo("DIER: %04" PRIx32 "\n", getreg32(STM32_TIM1_DIER)); + lcdinfo("SR: %04" PRIx32 "\n", getreg32(STM32_TIM1_SR)); + lcdinfo("BDTR: %04" PRIx32 "\n", getreg32(STM32_TIM1_BDTR)); + lcdinfo("CCMR1: %04" PRIx32 "\n", getreg32(STM32_TIM1_CCMR1)); + lcdinfo("CCMR2: %04" PRIx32 "\n", getreg32(STM32_TIM1_CCMR2)); + lcdinfo("CCER: %04" PRIx32 "\n", getreg32(STM32_TIM1_CCER)); + lcdinfo("CNT: %04" PRIx32 "\n", getreg32(STM32_TIM1_CNT)); + lcdinfo("PSC: %04" PRIx32 "\n", getreg32(STM32_TIM1_PSC)); + lcdinfo("ARR: %04" PRIx32 "\n", getreg32(STM32_TIM1_ARR)); + lcdinfo("RCR: %04" PRIx32 "\n", getreg32(STM32_TIM1_RCR)); + lcdinfo("CCR1: %04" PRIx32 "\n", getreg32(STM32_TIM1_CCR1)); + lcdinfo("CCR2: %04" PRIx32 "\n", getreg32(STM32_TIM1_CCR2)); + lcdinfo("CCR3: %04" PRIx32 "\n", getreg32(STM32_TIM1_CCR3)); + lcdinfo("CCR4: %04" PRIx32 "\n", getreg32(STM32_TIM1_CCR4)); + lcdinfo("DMAR: %04" PRIx32 "\n", getreg32(STM32_TIM1_DMAR)); +#endif +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_lcd_initialize + * + * Description: + * Initialize the LCD video hardware. The initial state of the LCD is + * fully initialized, display memory cleared, and the LCD ready to use, + * but with the power setting at 0 (full off). + * + ****************************************************************************/ + +int board_lcd_initialize(void) +{ +#ifdef CONFIG_PM + int ret; +#endif + + ginfo("Initializing\n"); + + /* Register to receive power management callbacks */ + +#ifdef CONFIG_PM + ret = pm_register(&g_lcdcb); + if (ret != OK) + { + lcderr("ERROR: pm_register failed: %d\n", ret); + } +#endif + + /* Configure GPIO pins and configure the FSMC to support the LCD */ + + stm32_selectlcd(); + + /* Configure and enable LCD */ + + up_mdelay(50); + stm3210e_lcdinitialize(); + + /* Clear the display (setting it to the color 0=black) */ + + stm3210e_lcdclear(0); + + /* Turn the backlight off */ + + stm3210e_poweroff(); + return OK; +} + +/**************************************************************************** + * Name: board_lcd_getdev + * + * Description: + * Return a a reference to the LCD object for the specified LCD. This + * allows support for multiple LCD devices. + * + ****************************************************************************/ + +struct lcd_dev_s *board_lcd_getdev(int lcddev) +{ + DEBUGASSERT(lcddev == 0); + return &g_lcddev.dev; +} + +/**************************************************************************** + * Name: board_lcd_uninitialize + * + * Description: + * Uninitialize the LCD support + * + ****************************************************************************/ + +void board_lcd_uninitialize(void) +{ + stm3210e_poweroff(); + stm32_deselectlcd(); +} + +/**************************************************************************** + * Name: stm3210e_lcdclear + * + * Description: + * This is a non-standard LCD interface just for the STM3210E-EVAL board. + * Because of the various rotations, clearing the display in the normal + * way by writing a sequences of runs that covers the entire display can + * be very slow. Here the display is cleared by simply setting all GRAM + * memory to the specified color. + * + ****************************************************************************/ + +void stm3210e_lcdclear(uint16_t color) +{ + uint32_t i = 0; + + stm3210e_setcursor(0, STM3210E_XRES - 1); + stm3210e_gramselect(); + for (i = 0; i < STM3210E_XRES * STM3210E_YRES; i++) + { + LCD->value = color; + } +} diff --git a/boards/arm/stm32f1/stm3210e-eval/src/stm32_leds.c b/boards/arm/stm32f1/stm3210e-eval/src/stm32_leds.c new file mode 100644 index 0000000000000..d2b6e2f5f57df --- /dev/null +++ b/boards/arm/stm32f1/stm3210e-eval/src/stm32_leds.c @@ -0,0 +1,372 @@ +/**************************************************************************** + * boards/arm/stm32f1/stm3210e-eval/src/stm32_leds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32.h" +#include "stm3210e-eval.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* The following definitions map the encoded LED setting to GPIO settings */ + +#define STM3210E_LED1 (1 << 0) +#define STM3210E_LED2 (1 << 1) +#define STM3210E_LED3 (1 << 2) +#define STM3210E_LED4 (1 << 3) + +#define ON_SETBITS_SHIFT (0) +#define ON_CLRBITS_SHIFT (4) +#define OFF_SETBITS_SHIFT (8) +#define OFF_CLRBITS_SHIFT (12) + +#define ON_BITS(v) ((v) & 0xff) +#define OFF_BITS(v) (((v) >> 8) & 0x0ff) +#define SETBITS(b) ((b) & 0x0f) +#define CLRBITS(b) (((b) >> 4) & 0x0f) + +#define ON_SETBITS(v) (SETBITS(ON_BITS(v)) +#define ON_CLRBITS(v) (CLRBITS(ON_BITS(v)) +#define OFF_SETBITS(v) (SETBITS(OFF_BITS(v)) +#define OFF_CLRBITS(v) (CLRBITS(OFF_BITS(v)) + +#define LED_STARTED_ON_SETBITS ((STM3210E_LED1) << ON_SETBITS_SHIFT) +#define LED_STARTED_ON_CLRBITS ((STM3210E_LED2|STM3210E_LED3|STM3210E_LED4) << ON_CLRBITS_SHIFT) +#define LED_STARTED_OFF_SETBITS (0 << OFF_SETBITS_SHIFT) +#define LED_STARTED_OFF_CLRBITS ((STM3210E_LED1|STM3210E_LED2|STM3210E_LED3|STM3210E_LED4) << OFF_CLRBITS_SHIFT) + +#define LED_HEAPALLOCATE_ON_SETBITS ((STM3210E_LED2) << ON_SETBITS_SHIFT) +#define LED_HEAPALLOCATE_ON_CLRBITS ((STM3210E_LED1|STM3210E_LED3|STM3210E_LED4) << ON_CLRBITS_SHIFT) +#define LED_HEAPALLOCATE_OFF_SETBITS ((STM3210E_LED1) << OFF_SETBITS_SHIFT) +#define LED_HEAPALLOCATE_OFF_CLRBITS ((STM3210E_LED2|STM3210E_LED3|STM3210E_LED4) << OFF_CLRBITS_SHIFT) + +#define LED_IRQSENABLED_ON_SETBITS ((STM3210E_LED1|STM3210E_LED2) << ON_SETBITS_SHIFT) +#define LED_IRQSENABLED_ON_CLRBITS ((STM3210E_LED3|STM3210E_LED4) << ON_CLRBITS_SHIFT) +#define LED_IRQSENABLED_OFF_SETBITS ((STM3210E_LED2) << OFF_SETBITS_SHIFT) +#define LED_IRQSENABLED_OFF_CLRBITS ((STM3210E_LED1|STM3210E_LED3|STM3210E_LED4) << OFF_CLRBITS_SHIFT) + +#define LED_STACKCREATED_ON_SETBITS ((STM3210E_LED3) << ON_SETBITS_SHIFT) +#define LED_STACKCREATED_ON_CLRBITS ((STM3210E_LED1|STM3210E_LED2|STM3210E_LED4) << ON_CLRBITS_SHIFT) +#define LED_STACKCREATED_OFF_SETBITS ((STM3210E_LED1|STM3210E_LED2) << OFF_SETBITS_SHIFT) +#define LED_STACKCREATED_OFF_CLRBITS ((STM3210E_LED3|STM3210E_LED4) << OFF_CLRBITS_SHIFT) + +#define LED_INIRQ_ON_SETBITS ((STM3210E_LED1) << ON_SETBITS_SHIFT) +#define LED_INIRQ_ON_CLRBITS ((0) << ON_CLRBITS_SHIFT) +#define LED_INIRQ_OFF_SETBITS ((0) << OFF_SETBITS_SHIFT) +#define LED_INIRQ_OFF_CLRBITS ((STM3210E_LED1) << OFF_CLRBITS_SHIFT) + +#define LED_SIGNAL_ON_SETBITS ((STM3210E_LED2) << ON_SETBITS_SHIFT) +#define LED_SIGNAL_ON_CLRBITS ((0) << ON_CLRBITS_SHIFT) +#define LED_SIGNAL_OFF_SETBITS ((0) << OFF_SETBITS_SHIFT) +#define LED_SIGNAL_OFF_CLRBITS ((STM3210E_LED2) << OFF_CLRBITS_SHIFT) + +#define LED_ASSERTION_ON_SETBITS ((STM3210E_LED4) << ON_SETBITS_SHIFT) +#define LED_ASSERTION_ON_CLRBITS ((0) << ON_CLRBITS_SHIFT) +#define LED_ASSERTION_OFF_SETBITS ((0) << OFF_SETBITS_SHIFT) +#define LED_ASSERTION_OFF_CLRBITS ((STM3210E_LED4) << OFF_CLRBITS_SHIFT) + +#define LED_PANIC_ON_SETBITS ((STM3210E_LED4) << ON_SETBITS_SHIFT) +#define LED_PANIC_ON_CLRBITS ((0) << ON_CLRBITS_SHIFT) +#define LED_PANIC_OFF_SETBITS ((0) << OFF_SETBITS_SHIFT) +#define LED_PANIC_OFF_CLRBITS ((STM3210E_LED4) << OFF_CLRBITS_SHIFT) + +/**************************************************************************** + * Private Function Protototypes + ****************************************************************************/ + +/* LED State Controls */ + +static inline void led_clrbits(unsigned int clrbits); +static inline void led_setbits(unsigned int setbits); +static void led_setonoff(unsigned int bits); + +/* LED Power Management */ + +#ifdef CONFIG_PM +static void led_pm_notify(struct pm_callback_s *cb, int domain, + enum pm_state_e pmstate); +static int led_pm_prepare(struct pm_callback_s *cb, int domain, + enum pm_state_e pmstate); +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static const uint16_t g_ledbits[8] = +{ + (LED_STARTED_ON_SETBITS | LED_STARTED_ON_CLRBITS | + LED_STARTED_OFF_SETBITS | LED_STARTED_OFF_CLRBITS), + + (LED_HEAPALLOCATE_ON_SETBITS | LED_HEAPALLOCATE_ON_CLRBITS | + LED_HEAPALLOCATE_OFF_SETBITS | LED_HEAPALLOCATE_OFF_CLRBITS), + + (LED_IRQSENABLED_ON_SETBITS | LED_IRQSENABLED_ON_CLRBITS | + LED_IRQSENABLED_OFF_SETBITS | LED_IRQSENABLED_OFF_CLRBITS), + + (LED_STACKCREATED_ON_SETBITS | LED_STACKCREATED_ON_CLRBITS | + LED_STACKCREATED_OFF_SETBITS | LED_STACKCREATED_OFF_CLRBITS), + + (LED_INIRQ_ON_SETBITS | LED_INIRQ_ON_CLRBITS | + LED_INIRQ_OFF_SETBITS | LED_INIRQ_OFF_CLRBITS), + + (LED_SIGNAL_ON_SETBITS | LED_SIGNAL_ON_CLRBITS | + LED_SIGNAL_OFF_SETBITS | LED_SIGNAL_OFF_CLRBITS), + + (LED_ASSERTION_ON_SETBITS | LED_ASSERTION_ON_CLRBITS | + LED_ASSERTION_OFF_SETBITS | LED_ASSERTION_OFF_CLRBITS), + + (LED_PANIC_ON_SETBITS | LED_PANIC_ON_CLRBITS | + LED_PANIC_OFF_SETBITS | LED_PANIC_OFF_CLRBITS) +}; + +#ifdef CONFIG_PM +static struct pm_callback_s g_ledscb = +{ + .notify = led_pm_notify, + .prepare = led_pm_prepare, +}; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: led_clrbits + * + * Description: + * Clear all LEDs to the bit encoded state + * + ****************************************************************************/ + +static inline void led_clrbits(unsigned int clrbits) +{ + if ((clrbits & STM3210E_LED1) != 0) + { + stm32_gpiowrite(GPIO_LED1, false); + } + + if ((clrbits & STM3210E_LED2) != 0) + { + stm32_gpiowrite(GPIO_LED2, false); + } + + if ((clrbits & STM3210E_LED3) != 0) + { + stm32_gpiowrite(GPIO_LED3, false); + } + + if ((clrbits & STM3210E_LED4) != 0) + { + stm32_gpiowrite(GPIO_LED4, false); + } +} + +/**************************************************************************** + * Name: led_setbits + * + * Description: + * Set all LEDs to the bit encoded state + * + ****************************************************************************/ + +static inline void led_setbits(unsigned int setbits) +{ + if ((setbits & STM3210E_LED1) != 0) + { + stm32_gpiowrite(GPIO_LED1, true); + } + + if ((setbits & STM3210E_LED2) != 0) + { + stm32_gpiowrite(GPIO_LED2, true); + } + + if ((setbits & STM3210E_LED3) != 0) + { + stm32_gpiowrite(GPIO_LED3, true); + } + + if ((setbits & STM3210E_LED4) != 0) + { + stm32_gpiowrite(GPIO_LED4, true); + } +} + +/**************************************************************************** + * Name: led_setonoff + * + * Description: + * Set/clear all LEDs to the bit encoded state + * + ****************************************************************************/ + +static void led_setonoff(unsigned int bits) +{ + led_clrbits(CLRBITS(bits)); + led_setbits(SETBITS(bits)); +} + +/**************************************************************************** + * Name: led_pm_notify + * + * Description: + * Notify the driver of new power state. This callback is called after + * all drivers have had the opportunity to prepare for the new power state. + * + ****************************************************************************/ + +#ifdef CONFIG_PM +static void led_pm_notify(struct pm_callback_s *cb, int domain, + enum pm_state_e pmstate) +{ + switch (pmstate) + { + case PM_NORMAL: + { + /* Restore normal LEDs operation */ + } + break; + + case PM_IDLE: + { + /* Entering IDLE mode - Turn leds off */ + } + break; + + case PM_STANDBY: + { + /* Entering STANDBY mode - Logic for PM_STANDBY goes here */ + } + break; + + case PM_SLEEP: + { + /* Entering SLEEP mode - Logic for PM_SLEEP goes here */ + } + break; + + default: + { + /* Should not get here */ + } + break; + } +} +#endif + +/**************************************************************************** + * Name: led_pm_prepare + * + * Description: + * Request the driver to prepare for a new power state. This is a warning + * that the system is about to enter into a new power state. The driver + * should begin whatever operations that may be required to enter power + * state. The driver may abort the state change mode by returning a + * non-zero value from the callback function. + * + ****************************************************************************/ + +#ifdef CONFIG_PM +static int led_pm_prepare(struct pm_callback_s *cb, int domain, + enum pm_state_e pmstate) +{ + /* No preparation to change power modes is required by the LEDs driver. + * We always accept the state change by returning OK. + */ + + return OK; +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_autoled_initialize + ****************************************************************************/ + +#ifdef CONFIG_ARCH_LEDS +void board_autoled_initialize(void) +{ + /* Configure LED1-4 GPIOs for output */ + + stm32_configgpio(GPIO_LED1); + stm32_configgpio(GPIO_LED2); + stm32_configgpio(GPIO_LED3); + stm32_configgpio(GPIO_LED4); +} + +/**************************************************************************** + * Name: board_autoled_on + ****************************************************************************/ + +void board_autoled_on(int led) +{ + led_setonoff(ON_BITS(g_ledbits[led])); +} + +/**************************************************************************** + * Name: board_autoled_off + ****************************************************************************/ + +void board_autoled_off(int led) +{ + led_setonoff(OFF_BITS(g_ledbits[led])); +} + +/**************************************************************************** + * Name: stm32_ledpminitialize + ****************************************************************************/ + +#ifdef CONFIG_PM +void stm32_ledpminitialize(void) +{ + /* Register to receive power management callbacks */ + + int ret = pm_register(&g_ledscb); + if (ret != OK) + { + board_autoled_on(LED_ASSERTION); + } +} +#endif /* CONFIG_PM */ + +#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32f1/stm3210e-eval/src/stm32_pm.c b/boards/arm/stm32f1/stm3210e-eval/src/stm32_pm.c new file mode 100644 index 0000000000000..0f4aa4ac80baa --- /dev/null +++ b/boards/arm/stm32f1/stm3210e-eval/src/stm32_pm.c @@ -0,0 +1,75 @@ +/**************************************************************************** + * boards/arm/stm32f1/stm3210e-eval/src/stm32_pm.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include "arm_internal.h" +#include "stm32_pm.h" +#include "stm3210e-eval.h" + +#ifdef CONFIG_PM + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: arm_pminitialize + * + * Description: + * This function is called by MCU-specific logic at power-on reset in + * order to provide one-time initialization the power management subsystem. + * This function must be called *very* early in the initialization sequence + * *before* any other device drivers are initialized (since they may + * attempt to register with the power management subsystem). + * + * Input Parameters: + * None. + * + * Returned Value: + * None. + * + ****************************************************************************/ + +void arm_pminitialize(void) +{ + /* Initialize the NuttX power management subsystem proper */ + + pm_initialize(); + +#if defined(CONFIG_ARCH_IDLE_CUSTOM) && defined(CONFIG_PM_BUTTONS) + /* Initialize the buttons to wake up the system from low power modes */ + + stm32_pmbuttons(); +#endif + + /* Initialize the LED PM */ + + stm32_ledpminitialize(); +} + +#endif /* CONFIG_PM */ diff --git a/boards/arm/stm32f1/stm3210e-eval/src/stm32_pmbuttons.c b/boards/arm/stm32f1/stm3210e-eval/src/stm32_pmbuttons.c new file mode 100644 index 0000000000000..bc9823007cdad --- /dev/null +++ b/boards/arm/stm32f1/stm3210e-eval/src/stm32_pmbuttons.c @@ -0,0 +1,181 @@ +/**************************************************************************** + * boards/arm/stm32f1/stm3210e-eval/src/stm32_pmbuttons.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include +#include +#include + +#include +#include +#include + +#include "arm_internal.h" +#include "nvic.h" +#include "stm32_pwr.h" +#include "stm32_pm.h" +#include "stm3210e-eval.h" + +#if defined(CONFIG_PM) && defined(CONFIG_ARCH_IDLE_CUSTOM) && defined(CONFIG_PM_BUTTONS) + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +#ifndef CONFIG_ARCH_BUTTONS +# error "CONFIG_ARCH_BUTTONS is not defined in the configuration" +#endif + +#define BUTTON_MIN 0 +#ifdef CONFIG_INPUT_DJOYSTICK +# define BUTTON_MAX 2 +#else +# define BUTTON_MAX 7 +#endif + +#ifndef CONFIG_PM_BUTTONS_MIN +# define CONFIG_PM_BUTTONS_MIN BUTTON_MIN +#endif +#ifndef CONFIG_PM_BUTTONS_MAX +# define CONFIG_PM_BUTTONS_MAX BUTTON_MAX +#endif + +#if CONFIG_PM_BUTTONS_MIN > CONFIG_PM_BUTTONS_MAX +# error "CONFIG_PM_BUTTONS_MIN > CONFIG_PM_BUTTONS_MAX" +#endif + +#if CONFIG_PM_BUTTONS_MAX > BUTTON_MAX +# error "CONFIG_PM_BUTTONS_MAX > BUTTON_MAX" +#endif + +#ifndef CONFIG_ARCH_IRQBUTTONS +# warning "CONFIG_ARCH_IRQBUTTONS is not defined in the configuration" +#endif + +#ifndef CONFIG_PM_IRQBUTTONS_MIN +# define CONFIG_PM_IRQBUTTONS_MIN CONFIG_PM_BUTTONS_MIN +#endif + +#ifndef CONFIG_PM_IRQBUTTONS_MAX +# define CONFIG_PM_IRQBUTTONS_MAX CONFIG_PM_BUTTONS_MAX +#endif + +#if CONFIG_PM_IRQBUTTONS_MIN > CONFIG_PM_IRQBUTTONS_MAX +# error "CONFIG_PM_IRQBUTTONS_MIN > CONFIG_PM_IRQBUTTONS_MAX" +#endif + +#if CONFIG_PM_IRQBUTTONS_MAX > 7 +# error "CONFIG_PM_IRQBUTTONS_MAX > 7" +#endif + +#ifndef CONFIG_PM_BUTTON_ACTIVITY +# define CONFIG_PM_BUTTON_ACTIVITY 10 +#endif + +/* Miscellaneous Definitions ************************************************/ + +#define MIN_BUTTON MIN(CONFIG_PM_BUTTONS_MIN, CONFIG_PM_IRQBUTTONS_MIN) +#define MAX_BUTTON MAX(CONFIG_PM_BUTTONS_MAX, CONFIG_PM_IRQBUTTONS_MAX) + +#define NUM_PMBUTTONS (MAX_BUTTON - MIN_BUTTON + 1) +#define BUTTON_INDEX(b) ((b)-MIN_BUTTON) + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +#ifdef CONFIG_ARCH_IRQBUTTONS +/**************************************************************************** + * Name: button_handler + * + * Description: + * Handle a button wake-up interrupt + * + ****************************************************************************/ + +static int button_handler(int irq, void *context, void *arg) +{ + /* At this point the MCU should have already awakened. The state + * change will be handled in the IDLE loop when the system is re-awakened + * The button interrupt handler should be totally ignorant of the PM + * activities and should report button activity as if nothing + * special happened. + */ + + pm_activity(PM_IDLE_DOMAIN, CONFIG_PM_BUTTON_ACTIVITY); + return 0; +} +#endif /* CONFIG_ARCH_IRQBUTTONS */ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_pmbuttons + * + * Description: + * Configure all the buttons of the STM3210e-eval board as EXTI, + * so any button is able to wakeup the MCU from the PM_STANDBY mode + * + ****************************************************************************/ + +void stm32_pmbuttons(void) +{ +#ifdef CONFIG_ARCH_IRQBUTTONS + int ret; + int i; +#endif + + /* Initialize the button GPIOs */ + + board_button_initialize(); + +#ifdef CONFIG_ARCH_IRQBUTTONS + for (i = CONFIG_PM_IRQBUTTONS_MIN; i <= CONFIG_PM_IRQBUTTONS_MAX; i++) + { + ret = board_button_irq(i, button_handler, (void *)i); + if (ret < 0) + { + serr("ERROR: board_button_irq failed: %d\n", ret); + } + } +#endif +} + +#endif /* defined(CONFIG_PM) && defined(CONFIG_ARCH_IDLE_CUSTOM) && defined(CONFIG_PM_BUTTONS) */ diff --git a/boards/arm/stm32f1/stm3210e-eval/src/stm32_selectlcd.c b/boards/arm/stm32f1/stm3210e-eval/src/stm32_selectlcd.c new file mode 100644 index 0000000000000..f506a43e45957 --- /dev/null +++ b/boards/arm/stm32f1/stm3210e-eval/src/stm32_selectlcd.c @@ -0,0 +1,134 @@ +/**************************************************************************** + * boards/arm/stm32f1/stm3210e-eval/src/stm32_selectlcd.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32.h" +#include +#include "stm3210e-eval.h" + +#ifdef CONFIG_STM32_FSMC + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#if STM32_NGPIO_PORTS < 6 +# error "Required GPIO ports not enabled" +#endif + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* 512Kx16 SRAM is connected to bank2 of the FSMC interface and both 8- and + * 16-bit accesses are allowed by BLN0 and BLN1 connected to BLE and BHE of + * SRAM, respectively. + * + * Pin Usage (per schematic) + * FLASH SRAM NAND LCD + * D[0..15] [0..15] [0..15] [0..7] [0..15] + * A[0..23] [0..22] [0..18] [16,17] [0] + * FSMC_NBL0 PE0 OUT ~BLE --- --- --- + * FSMC_NBL1 PE1 OUT ~BHE --- --- --- + * FSMC_NE2 PG9 OUT --- ~E --- --- + * FSMC_NE3 PG10 OUT ~CE --- --- --- + * FSMC_NE4 PG12 OUT --- --- --- ~CS + * FSMC_NWE PD5 OUT ~WE ~W ~W ~WR/SCL + * FSMC_NOE PD4 OUT ~OE ~G ~R ~RD + * FSMC_NWAIT PD6 IN --- R~B --- --- + * FSMC_INT2 PG6* IN --- --- R~B --- + * + * *JP7 will switch to PD6 + */ + +/* GPIO configurations unique to the LCD */ + +static const uint16_t g_lcdconfig[] = +{ + /* NE4 */ + + GPIO_NPS_NE4 +}; +#define NLCD_CONFIG (sizeof(g_lcdconfig)/sizeof(uint16_t)) + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_selectlcd + * + * Description: + * Initialize to the LCD + * + ****************************************************************************/ + +void stm32_selectlcd(void) +{ + /* Configure new GPIO state */ + + stm32_extmemgpios(g_commonconfig, NCOMMON_CONFIG); + stm32_extmemgpios(g_lcdconfig, NLCD_CONFIG); + + /* Enable AHB clocking to the FSMC */ + + stm32_fsmc_enable(); + + /* Bank4 NOR/SRAM control register configuration */ + + putreg32(FSMC_BCR_SRAM | FSMC_BCR_MWID16 | + FSMC_BCR_WREN, STM32_FSMC_BCR4); + + /* Bank4 NOR/SRAM timing register configuration */ + + putreg32(FSMC_BTR_ADDSET(1) | FSMC_BTR_ADDHLD(1) | + FSMC_BTR_DATAST(2) | FSMC_BTR_BUSTURN(1) | + FSMC_BTR_CLKDIV(1) | FSMC_BTR_DATLAT(2) | + FSMC_BTR_ACCMODA, STM32_FSMC_BTR4); + + putreg32(0xffffffff, STM32_FSMC_BWTR4); + + /* Enable the bank by setting the MBKEN bit */ + + putreg32(FSMC_BCR_MBKEN | FSMC_BCR_SRAM | + FSMC_BCR_MWID16 | FSMC_BCR_WREN, STM32_FSMC_BCR4); +} + +#endif /* CONFIG_STM32_FSMC */ diff --git a/boards/arm/stm32/stm3210e-eval/src/stm32_selectnor.c b/boards/arm/stm32f1/stm3210e-eval/src/stm32_selectnor.c similarity index 98% rename from boards/arm/stm32/stm3210e-eval/src/stm32_selectnor.c rename to boards/arm/stm32f1/stm3210e-eval/src/stm32_selectnor.c index ce5039b0501d4..f5823c781e2a4 100644 --- a/boards/arm/stm32/stm3210e-eval/src/stm32_selectnor.c +++ b/boards/arm/stm32f1/stm3210e-eval/src/stm32_selectnor.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm3210e-eval/src/stm32_selectnor.c + * boards/arm/stm32f1/stm3210e-eval/src/stm32_selectnor.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f1/stm3210e-eval/src/stm32_selectsram.c b/boards/arm/stm32f1/stm3210e-eval/src/stm32_selectsram.c new file mode 100644 index 0000000000000..6d46f6c872e4c --- /dev/null +++ b/boards/arm/stm32f1/stm3210e-eval/src/stm32_selectsram.c @@ -0,0 +1,133 @@ +/**************************************************************************** + * boards/arm/stm32f1/stm3210e-eval/src/stm32_selectsram.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32.h" +#include +#include "stm3210e-eval.h" + +#ifdef CONFIG_STM32_FSMC + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#if STM32_NGPIO_PORTS < 6 +# error "Required GPIO ports not enabled" +#endif + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* 512Kx16 SRAM is connected to bank2 of the FSMC interface and both 8- and + * 16-bit accesses are allowed by BLN0 and BLN1 connected to BLE and BHE of + * SRAM, respectively. + * + * Pin Usage (per schematic) + * FLASH SRAM NAND LCD + * D[0..15] [0..15] [0..15] [0..7] [0..15] + * A[0..23] [0..22] [0..18] [16,17] [0] + * FSMC_NBL0 PE0 OUT ~BLE --- --- --- + * FSMC_NBL1 PE1 OUT ~BHE --- --- --- + * FSMC_NE2 PG9 OUT --- ~E --- --- + * FSMC_NE3 PG10 OUT ~CE --- --- --- + * FSMC_NE4 PG12 OUT --- --- --- ~CS + * FSMC_NWE PD5 OUT ~WE ~W ~W ~WR/SCL + * FSMC_NOE PD4 OUT ~OE ~G ~R ~RD + * FSMC_NWAIT PD6 IN --- R~B --- --- + * FSMC_INT2 PG6* IN --- --- R~B --- + * + * *JP7 will switch to PD6 + */ + +/* GPIO configurations unique to SRAM */ + +static const uint16_t g_sramconfig[] = +{ + /* NE3, NBL0, NBL1, */ + + GPIO_NPS_NE3, GPIO_NPS_NBL0, GPIO_NPS_NBL1 +}; +#define NSRAM_CONFIG (sizeof(g_sramconfig)/sizeof(uint16_t)) + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_selectsram + * + * Description: + * Initialize to access external SRAM + * + ****************************************************************************/ + +void stm32_selectsram(void) +{ + /* Configure new GPIO state */ + + stm32_extmemgpios(g_commonconfig, NCOMMON_CONFIG); + stm32_extmemgpios(g_sramconfig, NSRAM_CONFIG); + + /* Enable AHB clocking to the FSMC */ + + stm32_fsmc_enable(); + + /* Bank1 NOR/SRAM control register configuration */ + + putreg32(FSMC_BCR_MWID16 | FSMC_BCR_WREN, STM32_FSMC_BCR3); + + /* Bank1 NOR/SRAM timing register configuration */ + + putreg32(FSMC_BTR_ADDSET(1) | FSMC_BTR_ADDHLD(1) | + FSMC_BTR_DATAST(3) | FSMC_BTR_BUSTURN(1) | + FSMC_BTR_CLKDIV(1) | FSMC_BTR_DATLAT(2) | + FSMC_BTR_ACCMODA, STM32_FSMC_BTR3); + + putreg32(0xffffffff, STM32_FSMC_BWTR3); + + /* Enable the bank */ + + putreg32(FSMC_BCR_MBKEN | FSMC_BCR_MWID16 | + FSMC_BCR_WREN, STM32_FSMC_BCR3); +} + +#endif /* CONFIG_STM32_FSMC */ diff --git a/boards/arm/stm32f1/stm3210e-eval/src/stm32_spi.c b/boards/arm/stm32f1/stm3210e-eval/src/stm32_spi.c new file mode 100644 index 0000000000000..69641713aa004 --- /dev/null +++ b/boards/arm/stm32f1/stm3210e-eval/src/stm32_spi.c @@ -0,0 +1,146 @@ +/**************************************************************************** + * boards/arm/stm32f1/stm3210e-eval/src/stm32_spi.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "arm_internal.h" +#include "chip.h" +#include "stm32.h" +#include "stm3210e-eval.h" + +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_spidev_initialize + * + * Description: + * Called to configure SPI chip select GPIO pins for the STM3210E-EVAL + * board. + * + ****************************************************************************/ + +void weak_function stm32_spidev_initialize(void) +{ + /* NOTE: Clocking for SPI1 and/or SPI2 was already provided in stm32_rcc.c. + * Configurations of SPI pins is performed in stm32_spi.c. + * Here, we only initialize chip select pins unique to the board + * architecture. + */ + +#ifdef CONFIG_STM32_SPI1 + /* Configure the SPI-based FLASH CS GPIO */ + + stm32_configgpio(GPIO_FLASH_CS); +#endif +} + +/**************************************************************************** + * Name: stm32_spi1/2/3select and stm32_spi1/2/3status + * + * Description: + * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status + * must be provided by board-specific logic. They are implementations of + * the select and status methods of the SPI interface defined by struct + * spi_ops_s (see include/nuttx/spi/spi.h). All other methods + * (including stm32_spibus_initialize()) are provided by common STM32 logic. + * To use this common SPI logic on your board: + * + * 1. Provide logic in stm32_boardinitialize() to configure SPI chip select + * pins. + * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() functions + * in your board-specific logic. These functions will perform chip + * selection and status operations using GPIOs in the way your board is + * configured. + * 3. Add a calls to stm32_spibus_initialize() in your low level + * application initialization logic + * 4. The handle returned by stm32_spibus_initialize() may then be used to + * bind the SPI driver to higher level logic (e.g., calling + * mmcsd_spislotinitialize(), for example, will bind the SPI driver to + * the SPI MMC/SD driver). + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_SPI1 +void stm32_spi1select(struct spi_dev_s *dev, + uint32_t devid, bool selected) +{ + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); + + if (devid == SPIDEV_FLASH(0)) + { + /* Set the GPIO low to select and high to de-select */ + + stm32_gpiowrite(GPIO_FLASH_CS, !selected); + } +} + +uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) +{ + return SPI_STATUS_PRESENT; +} +#endif + +#ifdef CONFIG_STM32_SPI2 +void stm32_spi2select(struct spi_dev_s *dev, + uint32_t devid, bool selected) +{ + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); +} + +uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) +{ + return SPI_STATUS_PRESENT; +} +#endif + +#ifdef CONFIG_STM32_SPI3 +void stm32_spi3select(struct spi_dev_s *dev, + uint32_t devid, bool selected) +{ + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); +} + +uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid) +{ + return SPI_STATUS_PRESENT; +} +#endif + +#endif /* CONFIG_STM32_SPI1 || CONFIG_STM32_SPI2 */ diff --git a/boards/arm/stm32f1/stm3210e-eval/src/stm32_usbdev.c b/boards/arm/stm32f1/stm3210e-eval/src/stm32_usbdev.c new file mode 100644 index 0000000000000..ac892b7e8af7b --- /dev/null +++ b/boards/arm/stm32f1/stm3210e-eval/src/stm32_usbdev.c @@ -0,0 +1,102 @@ +/**************************************************************************** + * boards/arm/stm32f1/stm3210e-eval/src/stm32_usbdev.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include + +#include "arm_internal.h" +#include "stm32.h" +#include "stm3210e-eval.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_usbinitialize + * + * Description: + * Called to setup USB-related GPIO pins for the STM3210E-EVAL board. + * + ****************************************************************************/ + +void stm32_usbinitialize(void) +{ + /* USB Soft Connect Pullup: PB.14 */ + + stm32_configgpio(GPIO_USB_PULLUP); +} + +/**************************************************************************** + * Name: stm32_usbpullup + * + * Description: + * If USB is supported and the board supports a pullup via GPIO (for USB + * software connect and disconnect), then the board software must provide + * stm32_pullup. + * See include/nuttx/usb/usbdev.h for additional description of this + * method. Alternatively, if no pull-up GPIO the following EXTERN can be + * redefined to be NULL. + * + ****************************************************************************/ + +int stm32_usbpullup(struct usbdev_s *dev, bool enable) +{ + usbtrace(TRACE_DEVPULLUP, (uint16_t)enable); + stm32_gpiowrite(GPIO_USB_PULLUP, !enable); + return OK; +} + +/**************************************************************************** + * Name: stm32_usbsuspend + * + * Description: + * Board logic must provide the stm32_usbsuspend logic if the USBDEV driver + * is used. This function is called whenever the USB enters or leaves + * suspend mode. This is an opportunity for the board logic to shutdown + * clocks, power, etc. while the USB is suspended. + * + ****************************************************************************/ + +void stm32_usbsuspend(struct usbdev_s *dev, bool resume) +{ + uinfo("resume: %d\n", resume); +} diff --git a/boards/arm/stm32f1/stm3210e-eval/src/stm32_usbmsc.c b/boards/arm/stm32f1/stm3210e-eval/src/stm32_usbmsc.c new file mode 100644 index 0000000000000..ecb66a7f25d82 --- /dev/null +++ b/boards/arm/stm32f1/stm3210e-eval/src/stm32_usbmsc.c @@ -0,0 +1,141 @@ +/**************************************************************************** + * boards/arm/stm32f1/stm3210e-eval/src/stm32_usbmsc.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include +#include + +#include "stm32.h" + +/* There is nothing to do here if SDIO support is not selected. */ + +#ifdef CONFIG_STM32_SDIO + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +#ifndef CONFIG_SYSTEM_USBMSC_DEVMINOR1 +# define CONFIG_SYSTEM_USBMSC_DEVMINOR1 0 +#endif + +/* SLOT number(s) could depend on the board configuration */ + +#ifdef CONFIG_ARCH_BOARD_STM3210E_EVAL +# undef STM32_MMCSDSLOTNO +# define STM32_MMCSDSLOTNO 0 +#else +/* Add configuration for new STM32 boards here */ + +# error "Unrecognized STM32 board" +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_bringup + * + * Description: + * Perform architecture-specific initialization + * + * CONFIG_BOARD_LATE_INITIALIZE=y : + * Called from board_late_initialize(). + * + ****************************************************************************/ + +int stm32_bringup(void); + +/**************************************************************************** + * Name: board_usbmsc_initialize + * + * Description: + * Perform architecture specific initialization as needed to establish + * the mass storage device that will be exported by the USB MSC device. + * + ****************************************************************************/ + +int board_usbmsc_initialize(int port) +{ + /* If system/usbmsc is built as an NSH command, then SD slot should + * already have been initialized. + * In this case, there is nothing further to be done here. + */ + +#ifndef CONFIG_NSH_BUILTIN_APPS + struct sdio_dev_s *sdio; + int ret; + + /* First, get an instance of the SDIO interface */ + + syslog(LOG_INFO, "Initializing SDIO slot %d\n", STM32_MMCSDSLOTNO); + + sdio = sdio_initialize(STM32_MMCSDSLOTNO); + if (!sdio) + { + syslog(LOG_ERR, "ERROR: Failed to initialize SDIO slot %d\n", + STM32_MMCSDSLOTNO); + return -ENODEV; + } + + /* Now bind the SDIO interface to the MMC/SD driver */ + + syslog(LOG_INFO, "Bind SDIO to the MMC/SD driver, minor=%d\n", + CONFIG_SYSTEM_USBMSC_DEVMINOR1); + + ret = mmcsd_slotinitialize(CONFIG_SYSTEM_USBMSC_DEVMINOR1, sdio); + if (ret != OK) + { + syslog(LOG_ERR, + "ERROR: Failed to bind SDIO to the MMC/SD driver: %d\n", + ret); + return ret; + } + + syslog(LOG_INFO, "Successfully bound SDIO to the MMC/SD driver\n"); + + /* Then let's guess and say that there is a card in the slot. + * I need to check to see if the STM3210E-EVAL board supports a GPIO to + * detect if there is a card in the slot. + */ + + sdio_mediachange(sdio, true); + +#endif /* CONFIG_NSH_BUILTIN_APPS */ + + return OK; +} + +#endif /* CONFIG_STM32_SDIO */ diff --git a/boards/arm/stm32/stm3210e-eval/tools/olimex-arm-usb-ocd.cfg b/boards/arm/stm32f1/stm3210e-eval/tools/olimex-arm-usb-ocd.cfg similarity index 100% rename from boards/arm/stm32/stm3210e-eval/tools/olimex-arm-usb-ocd.cfg rename to boards/arm/stm32f1/stm3210e-eval/tools/olimex-arm-usb-ocd.cfg diff --git a/boards/arm/stm32f1/stm3210e-eval/tools/oocd.sh b/boards/arm/stm32f1/stm3210e-eval/tools/oocd.sh new file mode 100755 index 0000000000000..04c7a7606c2a1 --- /dev/null +++ b/boards/arm/stm32f1/stm3210e-eval/tools/oocd.sh @@ -0,0 +1,87 @@ +#!/usr/bin/env bash + +# Get command line parameters + +USAGE="USAGE: $0 [-dh] " +ADVICE="Try '$0 -h' for more information" + +while [ ! -z "$1" ]; do + case $1 in + -d ) + set -x + ;; + -h ) + echo "$0 is a tool for generation of proper version files for the NuttX build" + echo "" + echo $USAGE + echo "" + echo "Where:" + echo " -d" + echo " Enable script debug" + echo " -h" + echo " show this help message and exit" + echo " Use the OpenOCD 0.4.0" + echo " " + echo " The full path to the top-level NuttX directory" + exit 0 + ;; + * ) + break; + ;; + esac + shift +done + +TOPDIR=$1 +if [ -z "${TOPDIR}" ]; then + echo "Missing argument" + echo $USAGE + echo $ADVICE + exit 1 +fi + +# This script *probably* only works with the following versions of OpenOCD: + +# Local search directory and configurations + +OPENOCD_SEARCHDIR="${TOPDIR}/boards/arm/stm32f1/stm3210e-eval/tools" +OPENOCD_WSEARCHDIR="`cygpath -w ${OPENOCD_SEARCHDIR}`" + +OPENOCD_PATH="/cygdrive/c/Program Files (x86)/OpenOCD/0.4.0/bin" +OPENOCD_EXE=openocd.exe +OPENOCD_INTERFACE="olimex-arm-usb-ocd.cfg" + +OPENOCD_TARGET="stm32.cfg" +OPENOCD_ARGS="-s ${OPENOCD_WSEARCHDIR} -f ${OPENOCD_INTERFACE} -f ${OPENOCD_TARGET}" + +echo "Trying OpenOCD 0.4.0 path: ${OPENOCD_PATH}/${OPENOCD_EXE}" + +# Verify that everything is what it claims it is and is located where it claims it is. + +if [ ! -x "${OPENOCD_PATH}/${OPENOCD_EXE}" ]; then + echo "OpenOCD executable does not exist: ${OPENOCD_PATH}/${OPENOCD_EXE}" + exit 1 +fi +if [ ! -f "${OPENOCD_SEARCHDIR}/${OPENOCD_TARGET}" ]; then + echo "OpenOCD target config file does not exist: ${OPENOCD_SEARCHDIR}/${OPENOCD_TARGET}" + exit 1 +fi +if [ ! -f "${OPENOCD_SEARCHDIR}/${OPENOCD_INTERFACE}" ]; then + echo "OpenOCD interface config file does not exist: ${OPENOCD_SEARCHDIR}/${OPENOCD_INTERFACE}" + exit 1 +fi + +# Enable debug if so requested + +if [ "X$2" = "X-d" ]; then + OPENOCD_ARGS=$OPENOCD_ARGS" -d3" + set -x +fi + +# Okay... do it! + +echo "Starting OpenOCD" +"${OPENOCD_PATH}/${OPENOCD_EXE}" ${OPENOCD_ARGS} & +echo "OpenOCD daemon started" +ps -ef | grep openocd +echo "In GDB: target remote localhost:3333" diff --git a/boards/arm/stm32/stm3210e-eval/tools/stm32.cfg b/boards/arm/stm32f1/stm3210e-eval/tools/stm32.cfg similarity index 100% rename from boards/arm/stm32/stm3210e-eval/tools/stm32.cfg rename to boards/arm/stm32f1/stm3210e-eval/tools/stm32.cfg diff --git a/boards/arm/stm32/stm3210e-eval/tools/usb-driver.txt b/boards/arm/stm32f1/stm3210e-eval/tools/usb-driver.txt similarity index 100% rename from boards/arm/stm32/stm3210e-eval/tools/usb-driver.txt rename to boards/arm/stm32f1/stm3210e-eval/tools/usb-driver.txt diff --git a/boards/arm/stm32f1/stm32_tiny/CMakeLists.txt b/boards/arm/stm32f1/stm32_tiny/CMakeLists.txt new file mode 100644 index 0000000000000..a22235736fc87 --- /dev/null +++ b/boards/arm/stm32f1/stm32_tiny/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32f1/stm32_tiny/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/arm/stm32/stm32_tiny/Kconfig b/boards/arm/stm32f1/stm32_tiny/Kconfig similarity index 100% rename from boards/arm/stm32/stm32_tiny/Kconfig rename to boards/arm/stm32f1/stm32_tiny/Kconfig diff --git a/boards/arm/stm32f1/stm32_tiny/configs/nsh/defconfig b/boards/arm/stm32f1/stm32_tiny/configs/nsh/defconfig new file mode 100644 index 0000000000000..b6dfc1579c239 --- /dev/null +++ b/boards/arm/stm32f1/stm32_tiny/configs/nsh/defconfig @@ -0,0 +1,58 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_DISABLE_OS_API is not set +# CONFIG_NSH_DISABLESCRIPT is not set +# CONFIG_NSH_DISABLE_EXEC is not set +# CONFIG_NSH_DISABLE_EXIT is not set +# CONFIG_NSH_DISABLE_GET is not set +# CONFIG_NSH_DISABLE_HEXDUMP is not set +# CONFIG_NSH_DISABLE_MKRD is not set +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_NSH_DISABLE_PUT is not set +# CONFIG_NSH_DISABLE_WGET is not set +# CONFIG_NSH_DISABLE_XD is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32_tiny" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_STM32_TINY=y +CONFIG_ARCH_CHIP="stm32f1" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F103C8=y +CONFIG_ARCH_CHIP_STM32F1=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_ARM_TOOLCHAIN_BUILDROOT=y +CONFIG_BOARD_LOOPSPERMSEC=5483 +CONFIG_BUILTIN=y +CONFIG_DEFAULT_SMALL=y +CONFIG_DRIVERS_WIRELESS=y +CONFIG_EXAMPLES_NRF24L01TERM=y +CONFIG_FILE_STREAM=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_LINE_MAX=80 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=1024 +CONFIG_RAM_SIZE=20480 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=192 +CONFIG_SCHED_WAITPID=y +CONFIG_SERIAL_TERMIOS=y +CONFIG_START_DAY=5 +CONFIG_START_MONTH=7 +CONFIG_START_YEAR=2011 +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_JTAG_FULL_ENABLE=y +CONFIG_STM32_SPI2=y +CONFIG_STM32_USART1=y +CONFIG_SYMTAB_ORDEREDBYNAME=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART1_SERIAL_CONSOLE=y +CONFIG_WL_NRF24L01=y diff --git a/boards/arm/stm32f1/stm32_tiny/configs/usbnsh/defconfig b/boards/arm/stm32f1/stm32_tiny/configs/usbnsh/defconfig new file mode 100644 index 0000000000000..0b88bf691343d --- /dev/null +++ b/boards/arm/stm32f1/stm32_tiny/configs/usbnsh/defconfig @@ -0,0 +1,56 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_DEV_CONSOLE is not set +# CONFIG_DISABLE_OS_API is not set +# CONFIG_NSH_DISABLEBG is not set +# CONFIG_NSH_DISABLESCRIPT is not set +# CONFIG_NSH_DISABLE_EXEC is not set +# CONFIG_NSH_DISABLE_EXIT is not set +# CONFIG_NSH_DISABLE_GET is not set +# CONFIG_NSH_DISABLE_HEXDUMP is not set +# CONFIG_NSH_DISABLE_MKRD is not set +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_NSH_DISABLE_PUT is not set +# CONFIG_NSH_DISABLE_WGET is not set +# CONFIG_NSH_DISABLE_XD is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32_tiny" +CONFIG_ARCH_BOARD_STM32_TINY=y +CONFIG_ARCH_CHIP="stm32f1" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F103C8=y +CONFIG_ARCH_CHIP_STM32F1=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL_USBDEVCTRL=y +CONFIG_BOARD_LOOPSPERMSEC=5483 +CONFIG_BUILTIN=y +CONFIG_CDCACM=y +CONFIG_CDCACM_CONSOLE=y +CONFIG_CDCACM_RXBUFSIZE=256 +CONFIG_CDCACM_TXBUFSIZE=256 +CONFIG_DEFAULT_SMALL=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_LINE_MAX=80 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=1024 +CONFIG_RAM_SIZE=20480 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=5 +CONFIG_START_MONTH=7 +CONFIG_START_YEAR=2011 +CONFIG_STM32_JTAG_FULL_ENABLE=y +CONFIG_STM32_USART1=y +CONFIG_STM32_USB=y +CONFIG_SYMTAB_ORDEREDBYNAME=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USBDEV_TRACE=y +CONFIG_USBDEV_TRACE_NRECORDS=32 diff --git a/boards/arm/stm32f1/stm32_tiny/include/board.h b/boards/arm/stm32f1/stm32_tiny/include/board.h new file mode 100644 index 0000000000000..2a9a1ac8c9218 --- /dev/null +++ b/boards/arm/stm32f1/stm32_tiny/include/board.h @@ -0,0 +1,182 @@ +/**************************************************************************** + * boards/arm/stm32f1/stm32_tiny/include/board.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARD_ARM_STM32_STM32_TINY_INCLUDE_BOARD_H +#define __BOARD_ARM_STM32_STM32_TINY_INCLUDE_BOARD_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#ifndef __ASSEMBLY__ +# include +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Clocking *****************************************************************/ + +/* On-board crystal frequency is 8MHz (HSE) */ + +#define STM32_BOARD_XTAL 8000000ul + +/* PLL source is HSE/1, PLL multiplier is 9: PLL frequency is + * 8MHz (XTAL) x 9 = 72MHz + */ + +#define STM32_CFGR_PLLSRC RCC_CFGR_PLLSRC +#define STM32_CFGR_PLLXTPRE 0 +#define STM32_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx9 +#define STM32_PLL_FREQUENCY (9*STM32_BOARD_XTAL) + +/* Use the PLL and set the SYSCLK source to be the PLL */ + +#define STM32_SYSCLK_SW RCC_CFGR_SW_PLL +#define STM32_SYSCLK_SWS RCC_CFGR_SWS_PLL +#define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY + +/* AHB clock (HCLK) is SYSCLK (72MHz) */ + +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK +#define STM32_HCLK_FREQUENCY STM32_PLL_FREQUENCY + +/* APB2 clock (PCLK2) is HCLK (72MHz) */ + +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK +#define STM32_PCLK2_FREQUENCY STM32_HCLK_FREQUENCY + +/* APB2 timers 1 and 8 will receive PCLK2. */ + +#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) + +/* APB1 clock (PCLK1) is HCLK/2 (36MHz) */ + +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd2 +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/2) + +/* APB1 timers 2-7 will be twice PCLK1 */ + +#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) + +/* USB divider -- Divide PLL clock by 1.5 */ + +#define STM32_CFGR_USBPRE 0 + +/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx + * otherwise frequency is 2xAPBx. + * Note: TIM1,8 are on APB2, others on APB1 + */ + +#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM2_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM3_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM4_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM5_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM6_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM7_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY + +/* SDIO dividers. Note that slower clocking is required when DMA is disabled + * in order to avoid RX overrun/TX underrun errors due to delayed responses + * to service FIFOs in interrupt driven mode. These values have not been + * tuned!!! + * + * HCLK=72MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(178+2)=400 KHz + */ + +#define SDIO_INIT_CLKDIV (178 << SDIO_CLKCR_CLKDIV_SHIFT) + +/* DMA ON: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(2+2)=18 MHz + * DMA OFF: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(3+2)=14.4 MHz + */ + +#ifdef CONFIG_SDIO_DMA +# define SDIO_MMCXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT) +#else +# define SDIO_MMCXFR_CLKDIV (3 << SDIO_CLKCR_CLKDIV_SHIFT) +#endif + +/* DMA ON: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(1+2)=24 MHz + * DMA OFF: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(3+2)=14.4 MHz + */ + +#ifdef CONFIG_SDIO_DMA +# define SDIO_SDXFR_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT) +#else +# define SDIO_SDXFR_CLKDIV (3 << SDIO_CLKCR_CLKDIV_SHIFT) +#endif + +/* LED definitions **********************************************************/ + +/* The board has only one controllable LED */ +#define LED_STARTED 0 /* No LEDs */ +#define LED_HEAPALLOCATE 1 /* LED1 on */ +#define LED_IRQSENABLED 2 /* LED2 on */ +#define LED_STACKCREATED 3 /* LED1 on */ +#define LED_INIRQ 4 /* LED1 off */ +#define LED_SIGNAL 5 /* LED2 on */ +#define LED_ASSERTION 6 /* LED1 + LED2 */ +#define LED_PANIC 7 /* LED1 / LED2 blinking */ + +/* NRF24L01 Driver **********************************************************/ + +/* NRF24L01 chip enable: PB.1 */ + +#define GPIO_NRF24L01_CE (GPIO_OUTPUT|GPIO_CNF_OUTPP|GPIO_MODE_50MHz|\ + GPIO_OUTPUT_CLEAR|GPIO_PORTB|GPIO_PIN1) + +/* NRF24L01 IRQ line: PA.0 */ + +#define GPIO_NRF24L01_IRQ (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_PORTA|GPIO_PIN0) + +#define BOARD_NRF24L01_GPIO_CE GPIO_NRF24L01_CE +#define BOARD_NRF24L01_GPIO_IRQ GPIO_NRF24L01_IRQ + +/* Alternate function pin selections (auto-aliased for new pinmap) */ + +/* USART1 */ + +#define GPIO_USART1_TX GPIO_ADJUST_MODE(GPIO_USART1_TX_0, GPIO_MODE_50MHz) +#define GPIO_USART1_RX GPIO_USART1_RX_0 + +/* SPI2 */ + +#define GPIO_SPI2_NSS GPIO_ADJUST_MODE(GPIO_SPI2_NSS_0, GPIO_MODE_50MHz) +#define GPIO_SPI2_SCK GPIO_ADJUST_MODE(GPIO_SPI2_SCK_0, GPIO_MODE_50MHz) +#define GPIO_SPI2_MISO GPIO_ADJUST_MODE(GPIO_SPI2_MISO_0, GPIO_MODE_50MHz) +#define GPIO_SPI2_MOSI GPIO_ADJUST_MODE(GPIO_SPI2_MOSI_0, GPIO_MODE_50MHz) + +/* USB */ + +#define GPIO_USB_DM GPIO_USB_DM_0 +#define GPIO_USB_DP GPIO_USB_DP_0 + +#endif /* __ARCH_ARM_STM32_STM32_TINY_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32f1/stm32_tiny/scripts/Make.defs b/boards/arm/stm32f1/stm32_tiny/scripts/Make.defs new file mode 100644 index 0000000000000..fd9ee583e0705 --- /dev/null +++ b/boards/arm/stm32f1/stm32_tiny/scripts/Make.defs @@ -0,0 +1,41 @@ +############################################################################ +# boards/arm/stm32f1/stm32_tiny/scripts/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/.config +include $(TOPDIR)/tools/Config.mk +include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs + +LDSCRIPT = ld.script +ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) + +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32f1/stm32_tiny/scripts/ld.script b/boards/arm/stm32f1/stm32_tiny/scripts/ld.script new file mode 100644 index 0000000000000..d8c2424728fae --- /dev/null +++ b/boards/arm/stm32f1/stm32_tiny/scripts/ld.script @@ -0,0 +1,122 @@ +/**************************************************************************** + * boards/arm/stm32f1/stm32_tiny/scripts/ld.script + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* The STM32F103C8T6 has 64Kb of FLASH beginning at address 0x0800:0000 and + * 20Kb of SRAM beginning at address 0x2000:0000. When booting from FLASH, + * FLASH memory is aliased to address 0x0000:0000 where the code expects to + * begin execution by jumping to the entry point in the 0x0800:0000 address + * range. + */ + +MEMORY +{ + flash (rx) : ORIGIN = 0x08000000, LENGTH = 64K + sram (rwx) : ORIGIN = 0x20000000, LENGTH = 20K +} + +OUTPUT_ARCH(arm) +EXTERN(_vectors) +ENTRY(_stext) +SECTIONS +{ + .text : { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > flash + + .init_section : ALIGN(4) { + _sinit = ABSOLUTE(.); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) + _einit = ABSOLUTE(.); + } > flash + + .ARM.extab : ALIGN(4) { + *(.ARM.extab*) + } > flash + + .ARM.exidx : ALIGN(4) { + __exidx_start = ABSOLUTE(.); + *(.ARM.exidx*) + __exidx_end = ABSOLUTE(.); + } > flash + + .tdata : { + _stdata = ABSOLUTE(.); + *(.tdata .tdata.* .gnu.linkonce.td.*); + _etdata = ABSOLUTE(.); + } > flash + + .tbss : { + _stbss = ABSOLUTE(.); + *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); + _etbss = ABSOLUTE(.); + } > flash + + _eronly = ABSOLUTE(.); + + /* The STM32F103C8T6 has 20Kb of SRAM beginning at the following address */ + + .data : ALIGN(4) { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > sram AT > flash + + .bss : ALIGN(4) { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + _ebss = ABSOLUTE(.); + } > sram + + /* Stabs debugging sections. */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/stm32f1/stm32_tiny/src/CMakeLists.txt b/boards/arm/stm32f1/stm32_tiny/src/CMakeLists.txt new file mode 100644 index 0000000000000..b09d5da50b72c --- /dev/null +++ b/boards/arm/stm32f1/stm32_tiny/src/CMakeLists.txt @@ -0,0 +1,31 @@ +# ############################################################################## +# boards/arm/stm32f1/stm32_tiny/src/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(SRCS stm32_boot.c stm32_leds.c stm32_spi.c stm32_usbdev.c) + +if(CONFIG_PWM) + list(APPEND SRCS stm32_pwm.c) +endif() + +target_sources(board PRIVATE ${SRCS}) + +set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/ld.script") diff --git a/boards/arm/stm32f1/stm32_tiny/src/Make.defs b/boards/arm/stm32f1/stm32_tiny/src/Make.defs new file mode 100644 index 0000000000000..3e58ff4b7fee3 --- /dev/null +++ b/boards/arm/stm32f1/stm32_tiny/src/Make.defs @@ -0,0 +1,33 @@ +############################################################################ +# boards/arm/stm32f1/stm32_tiny/src/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +CSRCS = stm32_boot.c stm32_leds.c stm32_spi.c stm32_usbdev.c + +ifeq ($(CONFIG_PWM),y) +CSRCS += stm32_pwm.c +endif + +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32f1/stm32_tiny/src/stm32_boot.c b/boards/arm/stm32f1/stm32_tiny/src/stm32_boot.c new file mode 100644 index 0000000000000..3150b338e9261 --- /dev/null +++ b/boards/arm/stm32f1/stm32_tiny/src/stm32_boot.c @@ -0,0 +1,131 @@ +/**************************************************************************** + * boards/arm/stm32f1/stm32_tiny/src/stm32_boot.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include + +#include +#include + +#include "arm_internal.h" +#include "stm32_tiny.h" + +#ifdef CONFIG_WL_NRF24L01 +#include "stm32_nrf24l01.h" +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_boardinitialize + * + * Description: + * All STM32 architectures must provide the following entry point. This + * entry point is called early in the initialization -- after all memory + * has been configured and mapped but before any devices have been + * initialized. + * + ****************************************************************************/ + +void stm32_boardinitialize(void) +{ + /* Configure on-board LEDs if LED support has been selected. */ + +#ifdef CONFIG_ARCH_LEDS + board_autoled_initialize(); +#endif + + /* Configure SPI chip selects if 1) SPI is not disabled, and 2) the weak + * function stm32_spidev_initialize() has been brought into the link. + */ + +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) + stm32_spidev_initialize(); +#endif + + /* Initialize USB is 1) USBDEV is selected, 2) the USB controller is not + * disabled, and 3) the weak function stm32_usbinitialize() has been + * brought into the build. + */ + +#if defined(CONFIG_USBDEV) && defined(CONFIG_STM32_USB) + stm32_usbinitialize(); +#endif +} + +/**************************************************************************** + * Name: board_late_initialize + * + * Description: + * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_late_initialize(). board_late_initialize() will + * be called immediately after up_initialize() is called and just before + * the initial application is started. This additional initialization + * phase may be used, for example, to initialize board-specific device + * drivers. + * + ****************************************************************************/ + +#ifdef CONFIG_BOARD_LATE_INITIALIZE +void board_late_initialize(void) +{ + int ret = OK; + + UNUSED(ret); + +#ifdef CONFIG_PWM + /* Initialize PWM and register the PWM device. */ + + ret = stm32_pwm_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_pwm_setup() failed: %d\n", ret); + } +#endif + +#if defined(CONFIG_WL_NRF24L01) + /* Initialize the NRF24L01 wireless module */ + + ret = board_nrf24l01_initialize(2); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: board_nrf24l01_initialize failed: %d\n", ret); + } +#endif +} +#endif diff --git a/boards/arm/stm32f1/stm32_tiny/src/stm32_leds.c b/boards/arm/stm32f1/stm32_tiny/src/stm32_leds.c new file mode 100644 index 0000000000000..79b15918460de --- /dev/null +++ b/boards/arm/stm32f1/stm32_tiny/src/stm32_leds.c @@ -0,0 +1,110 @@ +/**************************************************************************** + * boards/arm/stm32f1/stm32_tiny/src/stm32_leds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32.h" +#include "stm32_tiny.h" + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +static inline void set_led(bool v) +{ + ledinfo("Turn LED %s\n", v? "on":"off"); + stm32_gpiowrite(GPIO_LED, v); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_autoled_initialize + ****************************************************************************/ + +#ifdef CONFIG_ARCH_LEDS +void board_autoled_initialize(void) +{ + /* Configure LED GPIO for output */ + + stm32_configgpio(GPIO_LED); +} + +/**************************************************************************** + * Name: board_autoled_on + ****************************************************************************/ + +void board_autoled_on(int led) +{ + ledinfo("board_autoled_on(%d)\n", led); + switch (led) + { + case LED_STARTED: + case LED_HEAPALLOCATE: + /* As the board provides only one soft controllable LED, + * we simply turn it on when the board boots + */ + + set_led(true); + break; + case LED_PANIC: + + /* For panic state, the LED is blinking */ + + set_led(true); + break; + } +} + +/**************************************************************************** + * Name: board_autoled_off + ****************************************************************************/ + +void board_autoled_off(int led) +{ + switch (led) + { + case LED_PANIC: + + /* For panic state, the LED is blinking */ + + set_led(false); + break; + } +} + +#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32f1/stm32_tiny/src/stm32_pwm.c b/boards/arm/stm32f1/stm32_tiny/src/stm32_pwm.c new file mode 100644 index 0000000000000..332755c7b21c0 --- /dev/null +++ b/boards/arm/stm32f1/stm32_tiny/src/stm32_pwm.c @@ -0,0 +1,103 @@ +/**************************************************************************** + * boards/arm/stm32f1/stm32_tiny/src/stm32_pwm.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include + +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32_pwm.h" +#include "stm32_tiny.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* PWM + * + * The STM32 Tiny board provides a LED on GPIO line B5. + */ + +#ifdef CONFIG_PWM + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_pwm_setup + * + * Description: + * Initialize PWM and register the PWM device. + * + ****************************************************************************/ + +int stm32_pwm_setup(void) +{ + static bool initialized = false; + struct pwm_lowerhalf_s *pwm; + int ret; + + /* Have we already initialized? */ + + if (!initialized) + { + /* Call stm32_pwminitialize() to get an instance of the PWM interface */ + + pwm = stm32_pwminitialize(STM32TINY_PWMTIMER); + if (!pwm) + { + aerr("ERROR: Failed to get the STM32 PWM lower half\n"); + return -ENODEV; + } + + /* Register the PWM driver at "/dev/pwm0" */ + + ret = pwm_register("/dev/pwm0", pwm); + if (ret < 0) + { + aerr("ERROR: pwm_register failed: %d\n", ret); + return ret; + } + + /* Now we are initialized */ + + initialized = true; + } + + return OK; +} + +#endif /* CONFIG_PWM */ diff --git a/boards/arm/stm32f1/stm32_tiny/src/stm32_spi.c b/boards/arm/stm32f1/stm32_tiny/src/stm32_spi.c new file mode 100644 index 0000000000000..0b27f331ef712 --- /dev/null +++ b/boards/arm/stm32f1/stm32_tiny/src/stm32_spi.c @@ -0,0 +1,151 @@ +/**************************************************************************** + * boards/arm/stm32f1/stm32_tiny/src/stm32_spi.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "arm_internal.h" +#include "chip.h" +#include "stm32.h" +#include "stm32_tiny.h" + +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_spidev_initialize + * + * Description: + * Called to configure SPI chip select GPIO pins for the HY-MiniSTM32 + * board. + * + ****************************************************************************/ + +void stm32_spidev_initialize(void) +{ + /* NOTE: Clocking for SPI1 and/or SPI2 was already provided in stm32_rcc.c. + * Configurations of SPI pins is performed in stm32_spi.c. + * Here, we only initialize chip select pins unique to the board + * architecture. + */ + +#ifdef CONFIG_STM32_SPI2 +# ifdef CONFIG_WL_NRF24L01 + /* Configure the SPI-based NRF24L01 chip select GPIO */ + + spiinfo("Configure GPIO for SPI2/CS\n"); + stm32_configgpio(GPIO_NRF24L01_CS); +# endif +#endif +} + +/**************************************************************************** + * Name: stm32_spi1/2select and stm32_spi1/2status + * + * Description: + * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status + * must be provided by board-specific logic. They are implementations of + * the select and status methods of the SPI interface defined by struct + * spi_ops_s (see include/nuttx/spi/spi.h). All other methods (including + * stm32_spibus_initialize()) are provided by common STM32 logic. + * To use this common SPI logic on your board: + * + * 1. Provide logic in stm32_boardinitialize() to configure SPI chip + * select pins. + * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() functions + * in your board-specific logic. These functions will perform chip + * selection and status operations using GPIOs in the way your board is + * configured. + * 3. Add a calls to stm32_spibus_initialize() in your low level + * application initialization logic + * 4. The handle returned by stm32_spibus_initialize() may then be used to + * bind the SPI driver to higher level logic (e.g., calling + * mmcsd_spislotinitialize(), for example, will bind the SPI driver to + * the SPI MMC/SD driver). + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_SPI1 +void stm32_spi1select(struct spi_dev_s *dev, + uint32_t devid, bool selected) +{ +} + +uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} +#endif + +#ifdef CONFIG_STM32_SPI2 +void stm32_spi2select(struct spi_dev_s *dev, + uint32_t devid, bool selected) +{ + switch (devid) + { +#ifdef CONFIG_WL_NRF24L01 + case SPIDEV_WIRELESS(0): + spiinfo("nRF24L01 device %s\n", selected ? "asserted" : "de-asserted"); + + /* Set the GPIO low to select and high to de-select */ + + stm32_gpiowrite(GPIO_NRF24L01_CS, !selected); + break; +#endif + default: + break; + } +} + +uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) +{ + uint8_t status = 0; + switch (devid) + { +#ifdef CONFIG_WL_NRF24L01 + case SPIDEV_WIRELESS(0): + status |= SPI_STATUS_PRESENT; + break; +#endif + default: + break; + } + + return status; +} + +#endif + +#endif /* CONFIG_STM32_SPI1 || CONFIG_STM32_SPI2 */ diff --git a/boards/arm/stm32/stm32_tiny/src/stm32_tiny.h b/boards/arm/stm32f1/stm32_tiny/src/stm32_tiny.h similarity index 98% rename from boards/arm/stm32/stm32_tiny/src/stm32_tiny.h rename to boards/arm/stm32f1/stm32_tiny/src/stm32_tiny.h index 1d113843ecf3a..300fdd01bb155 100644 --- a/boards/arm/stm32/stm32_tiny/src/stm32_tiny.h +++ b/boards/arm/stm32f1/stm32_tiny/src/stm32_tiny.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32_tiny/src/stm32_tiny.h + * boards/arm/stm32f1/stm32_tiny/src/stm32_tiny.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f1/stm32_tiny/src/stm32_usbdev.c b/boards/arm/stm32f1/stm32_tiny/src/stm32_usbdev.c new file mode 100644 index 0000000000000..b183b6827ef9c --- /dev/null +++ b/boards/arm/stm32f1/stm32_tiny/src/stm32_usbdev.c @@ -0,0 +1,106 @@ +/**************************************************************************** + * boards/arm/stm32f1/stm32_tiny/src/stm32_usbdev.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include + +#include "arm_internal.h" +#include "stm32.h" +#include "stm32_tiny.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_usbinitialize + * + * Description: + * Called to setup USB-related GPIO pins for the Hy-Mini STM32v board. + * + ****************************************************************************/ + +void stm32_usbinitialize(void) +{ + uinfo("called\n"); + + /* USB Soft Connect Pullup */ + + stm32_configgpio(GPIO_USB_PULLUP); +} + +/**************************************************************************** + * Name: stm32_usbpullup + * + * Description: + * If USB is supported and the board supports a pullup via GPIO (for USB + * software connect and disconnect), then the board software must provide + * stm32_pullup. + * See include/nuttx/usb/usbdev.h for additional description of this + * method. + * Alternatively, if no pull-up GPIO the following EXTERN can be redefined + * to be NULL. + * + ****************************************************************************/ + +int stm32_usbpullup(struct usbdev_s *dev, bool enable) +{ + usbtrace(TRACE_DEVPULLUP, (uint16_t)enable); + stm32_gpiowrite(GPIO_USB_PULLUP, !enable); + return OK; +} + +/**************************************************************************** + * Name: stm32_usbsuspend + * + * Description: + * Board logic must provide the stm32_usbsuspend logic if the USBDEV + * driver is used. This function is called whenever the USB enters or + * leaves suspend mode. + * This is an opportunity for the board logic to shutdown clocks, power, + * etc. while the USB is suspended. + * + ****************************************************************************/ + +void stm32_usbsuspend(struct usbdev_s *dev, bool resume) +{ + uinfo("resume: %d\n", resume); +} diff --git a/boards/arm/stm32f1/stm32butterfly2/CMakeLists.txt b/boards/arm/stm32f1/stm32butterfly2/CMakeLists.txt new file mode 100644 index 0000000000000..7c8a40cb663a6 --- /dev/null +++ b/boards/arm/stm32f1/stm32butterfly2/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32f1/stm32butterfly2/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/arm/stm32/stm32butterfly2/Kconfig b/boards/arm/stm32f1/stm32butterfly2/Kconfig similarity index 100% rename from boards/arm/stm32/stm32butterfly2/Kconfig rename to boards/arm/stm32f1/stm32butterfly2/Kconfig diff --git a/boards/arm/stm32f1/stm32butterfly2/configs/nsh/defconfig b/boards/arm/stm32f1/stm32butterfly2/configs/nsh/defconfig new file mode 100644 index 0000000000000..151be594518f0 --- /dev/null +++ b/boards/arm/stm32f1/stm32butterfly2/configs/nsh/defconfig @@ -0,0 +1,72 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_DISABLE_OS_API is not set +# CONFIG_MMCSD_MMCSUPPORT is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_DISABLE_LOSMART is not set +CONFIG_ADC=y +CONFIG_ANALOG=y +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32butterfly2" +CONFIG_ARCH_BOARD_STM32_BUTTERFLY2=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f1" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F107VC=y +CONFIG_ARCH_CHIP_STM32F1=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_ARM_TOOLCHAIN_BUILDROOT=y +CONFIG_BOARD_LOOPSPERMSEC=5483 +CONFIG_BUILTIN=y +CONFIG_EXAMPLES_ADC=y +CONFIG_EXAMPLES_ADC_SWTRIG=y +CONFIG_EXAMPLES_HIDKBD=y +CONFIG_EXAMPLES_HIDKBD_DEFPRIO=50 +CONFIG_EXAMPLES_HIDKBD_STACKSIZE=1024 +CONFIG_EXAMPLES_MOUNT=y +CONFIG_FAT_LCNAMES=y +CONFIG_FAT_LFN=y +CONFIG_FS_FAT=y +CONFIG_FS_PROCFS=y +CONFIG_FS_PROCFS_REGISTER=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_STRERROR=y +CONFIG_LIBC_STRERROR_SHORT=y +CONFIG_MMCSD=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_MOTD=y +CONFIG_NSH_MOTD_STRING="stm32butterfly2 welcoms you" +CONFIG_NSH_READLINE=y +CONFIG_NSH_STRERROR=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=65536 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_READLINE_TABCOMPLETION=y +CONFIG_RR_INTERVAL=100 +CONFIG_SCHED_CPULOAD_SYSCLK=y +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=192 +CONFIG_SCHED_HPWORKSTACKSIZE=1024 +CONFIG_START_YEAR=1970 +CONFIG_STM32_ADC1=y +CONFIG_STM32_JTAG_FULL_ENABLE=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PWR=y +CONFIG_STM32_SPI1=y +CONFIG_STM32_USART2=y +CONFIG_STM32_USART2_REMAP=y +CONFIG_STM32_USBHOST=y +CONFIG_SYSLOG_TIMESTAMP=y +CONFIG_SYSTEM_NSH=y +CONFIG_SYSTEM_VI=y +CONFIG_TESTING_RAMTEST=y +CONFIG_USART2_SERIAL_CONSOLE=y +CONFIG_USBHOST_HIDKBD=y +CONFIG_USBHOST_MSC=y diff --git a/boards/arm/stm32f1/stm32butterfly2/configs/nshnet/defconfig b/boards/arm/stm32f1/stm32butterfly2/configs/nshnet/defconfig new file mode 100644 index 0000000000000..4ffa586a44c71 --- /dev/null +++ b/boards/arm/stm32f1/stm32butterfly2/configs/nshnet/defconfig @@ -0,0 +1,91 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_DISABLE_OS_API is not set +# CONFIG_MMCSD_MMCSUPPORT is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_DISABLE_LOSMART is not set +# CONFIG_STM32_AUTONEG is not set +CONFIG_ADC=y +CONFIG_ANALOG=y +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32butterfly2" +CONFIG_ARCH_BOARD_STM32_BUTTERFLY2=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f1" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F107VC=y +CONFIG_ARCH_CHIP_STM32F1=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_ARM_TOOLCHAIN_BUILDROOT=y +CONFIG_BOARD_LOOPSPERMSEC=5483 +CONFIG_BUILTIN=y +CONFIG_ETH0_PHY_DP83848C=y +CONFIG_EXAMPLES_ADC=y +CONFIG_EXAMPLES_ADC_SWTRIG=y +CONFIG_EXAMPLES_MOUNT=y +CONFIG_EXAMPLES_USBSERIAL=y +CONFIG_FAT_LCNAMES=y +CONFIG_FAT_LFN=y +CONFIG_FS_FAT=y +CONFIG_FS_PROCFS=y +CONFIG_FS_PROCFS_REGISTER=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_HOSTNAME="butterfly2" +CONFIG_LIBC_STRERROR=y +CONFIG_LIBC_STRERROR_SHORT=y +CONFIG_MMCSD=y +CONFIG_NET=y +CONFIG_NETINIT_DRIPADDR=0x0a010101 +CONFIG_NETINIT_IPADDR=0x0a010163 +CONFIG_NETINIT_NOMAC=y +CONFIG_NET_ARP_IPIN=y +CONFIG_NET_ETH_PKTSIZE=1500 +CONFIG_NET_ICMP_SOCKET=y +CONFIG_NET_LOCAL=y +CONFIG_NET_TCP=y +CONFIG_NET_UDP=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_MOTD=y +CONFIG_NSH_MOTD_STRING="stm32butterfly2 welcoms you" +CONFIG_NSH_READLINE=y +CONFIG_NSH_STRERROR=y +CONFIG_PL2303=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=65536 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_READLINE_TABCOMPLETION=y +CONFIG_RR_INTERVAL=100 +CONFIG_SCHED_CPULOAD_SYSCLK=y +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=192 +CONFIG_SCHED_HPWORKSTACKSIZE=1024 +CONFIG_START_YEAR=1970 +CONFIG_STM32_ADC1=y +CONFIG_STM32_ETH100MBPS=y +CONFIG_STM32_ETHFD=y +CONFIG_STM32_ETHMAC=y +CONFIG_STM32_ETH_REMAP=y +CONFIG_STM32_JTAG_FULL_ENABLE=y +CONFIG_STM32_MII=y +CONFIG_STM32_MII_EXTCLK=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PWR=y +CONFIG_STM32_SPI1=y +CONFIG_STM32_USART2=y +CONFIG_STM32_USART2_REMAP=y +CONFIG_SYSLOG_TIMESTAMP=y +CONFIG_SYSTEM_NSH=y +CONFIG_SYSTEM_PING=y +CONFIG_SYSTEM_VI=y +CONFIG_TESTING_RAMTEST=y +CONFIG_USART2_SERIAL_CONSOLE=y +CONFIG_USBDEV=y +CONFIG_USBDEV_BUSPOWERED=y +CONFIG_USBDEV_MAXPOWER=500 diff --git a/boards/arm/stm32f1/stm32butterfly2/configs/nshusbdev/defconfig b/boards/arm/stm32f1/stm32butterfly2/configs/nshusbdev/defconfig new file mode 100644 index 0000000000000..a2793fec93239 --- /dev/null +++ b/boards/arm/stm32f1/stm32butterfly2/configs/nshusbdev/defconfig @@ -0,0 +1,71 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_DISABLE_OS_API is not set +# CONFIG_MMCSD_MMCSUPPORT is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_DISABLE_LOSMART is not set +CONFIG_ADC=y +CONFIG_ANALOG=y +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32butterfly2" +CONFIG_ARCH_BOARD_STM32_BUTTERFLY2=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f1" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F107VC=y +CONFIG_ARCH_CHIP_STM32F1=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_ARM_TOOLCHAIN_BUILDROOT=y +CONFIG_BOARD_LOOPSPERMSEC=5483 +CONFIG_BUILTIN=y +CONFIG_EXAMPLES_ADC=y +CONFIG_EXAMPLES_ADC_SWTRIG=y +CONFIG_EXAMPLES_MOUNT=y +CONFIG_EXAMPLES_USBSERIAL=y +CONFIG_FAT_LCNAMES=y +CONFIG_FAT_LFN=y +CONFIG_FS_FAT=y +CONFIG_FS_PROCFS=y +CONFIG_FS_PROCFS_REGISTER=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_STRERROR=y +CONFIG_LIBC_STRERROR_SHORT=y +CONFIG_MMCSD=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_MOTD=y +CONFIG_NSH_MOTD_STRING="stm32butterfly2 welcoms you" +CONFIG_NSH_READLINE=y +CONFIG_NSH_STRERROR=y +CONFIG_PL2303=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=65536 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_READLINE_TABCOMPLETION=y +CONFIG_RR_INTERVAL=100 +CONFIG_SCHED_CPULOAD_SYSCLK=y +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=192 +CONFIG_SCHED_HPWORKSTACKSIZE=1024 +CONFIG_START_YEAR=1970 +CONFIG_STM32_ADC1=y +CONFIG_STM32_JTAG_FULL_ENABLE=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PWR=y +CONFIG_STM32_SPI1=y +CONFIG_STM32_USART2=y +CONFIG_STM32_USART2_REMAP=y +CONFIG_SYSLOG_TIMESTAMP=y +CONFIG_SYSTEM_NSH=y +CONFIG_SYSTEM_VI=y +CONFIG_TESTING_RAMTEST=y +CONFIG_USART2_SERIAL_CONSOLE=y +CONFIG_USBDEV=y +CONFIG_USBDEV_BUSPOWERED=y +CONFIG_USBDEV_MAXPOWER=500 diff --git a/boards/arm/stm32f1/stm32butterfly2/configs/nshusbhost/defconfig b/boards/arm/stm32f1/stm32butterfly2/configs/nshusbhost/defconfig new file mode 100644 index 0000000000000..151be594518f0 --- /dev/null +++ b/boards/arm/stm32f1/stm32butterfly2/configs/nshusbhost/defconfig @@ -0,0 +1,72 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_DISABLE_OS_API is not set +# CONFIG_MMCSD_MMCSUPPORT is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_DISABLE_LOSMART is not set +CONFIG_ADC=y +CONFIG_ANALOG=y +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32butterfly2" +CONFIG_ARCH_BOARD_STM32_BUTTERFLY2=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f1" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F107VC=y +CONFIG_ARCH_CHIP_STM32F1=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_ARM_TOOLCHAIN_BUILDROOT=y +CONFIG_BOARD_LOOPSPERMSEC=5483 +CONFIG_BUILTIN=y +CONFIG_EXAMPLES_ADC=y +CONFIG_EXAMPLES_ADC_SWTRIG=y +CONFIG_EXAMPLES_HIDKBD=y +CONFIG_EXAMPLES_HIDKBD_DEFPRIO=50 +CONFIG_EXAMPLES_HIDKBD_STACKSIZE=1024 +CONFIG_EXAMPLES_MOUNT=y +CONFIG_FAT_LCNAMES=y +CONFIG_FAT_LFN=y +CONFIG_FS_FAT=y +CONFIG_FS_PROCFS=y +CONFIG_FS_PROCFS_REGISTER=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_STRERROR=y +CONFIG_LIBC_STRERROR_SHORT=y +CONFIG_MMCSD=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_MOTD=y +CONFIG_NSH_MOTD_STRING="stm32butterfly2 welcoms you" +CONFIG_NSH_READLINE=y +CONFIG_NSH_STRERROR=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=65536 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_READLINE_TABCOMPLETION=y +CONFIG_RR_INTERVAL=100 +CONFIG_SCHED_CPULOAD_SYSCLK=y +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=192 +CONFIG_SCHED_HPWORKSTACKSIZE=1024 +CONFIG_START_YEAR=1970 +CONFIG_STM32_ADC1=y +CONFIG_STM32_JTAG_FULL_ENABLE=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PWR=y +CONFIG_STM32_SPI1=y +CONFIG_STM32_USART2=y +CONFIG_STM32_USART2_REMAP=y +CONFIG_STM32_USBHOST=y +CONFIG_SYSLOG_TIMESTAMP=y +CONFIG_SYSTEM_NSH=y +CONFIG_SYSTEM_VI=y +CONFIG_TESTING_RAMTEST=y +CONFIG_USART2_SERIAL_CONSOLE=y +CONFIG_USBHOST_HIDKBD=y +CONFIG_USBHOST_MSC=y diff --git a/boards/arm/stm32f1/stm32butterfly2/include/board.h b/boards/arm/stm32f1/stm32butterfly2/include/board.h new file mode 100644 index 0000000000000..cef38c97de014 --- /dev/null +++ b/boards/arm/stm32f1/stm32butterfly2/include/board.h @@ -0,0 +1,219 @@ +/**************************************************************************** + * boards/arm/stm32f1/stm32butterfly2/include/board.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_STM32_STM32_BUTTERFLY2_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32_STM32_BUTTERFLY2_INCLUDE_BOARD_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#ifndef __ASSEMBLY__ +# include +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Clocking *****************************************************************/ + +/* HSI - 8 MHz RC factory-trimmed + * LSI - 40 KHz RC (30-60KHz, uncalibrated) + * HSE - On-board crystal frequency is 14.7456MHz + * LSE - LSE is not connected + */ + +#define STM32_BOARD_XTAL 14745600ul + +#define STM32_HSI_FREQUENCY 8000000ul +#define STM32_LSI_FREQUENCY 40000u +#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL +#define STM32_LSE_FREQUENCY 0 + +/* PLL output is 71.8848MHz */ + +#define STM32_PLL_PREDIV2 RCC_CFGR2_PREDIV2d4 +#define STM32_PLL_PLL2MUL RCC_CFGR2_PLL2MULx12 +#define STM32_PLL_PREDIV1 RCC_CFGR2_PREDIV1d4 +#define STM32_PLL_PLLMUL RCC_CFGR_PLLMUL_CLKx65 +#define STM32_PLL_FREQUENCY 71884800ul + +/* SYSCLK and HCLK adre the PLL frequency */ + +#define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY +#define STM32_HCLK_FREQUENCY STM32_PLL_FREQUENCY + +/* USB clock output is 47.9232MHz */ + +#define STM32_CFGR_OTGFSPRE RCC_CFGR_OTGFSPREd3 + +/* APB2 clock (PCLK2) is HCLK */ + +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK +#define STM32_PCLK2_FREQUENCY STM32_HCLK_FREQUENCY +#define STM32_APB2_CLKIN STM32_PCLK2_FREQUENCY + +#define STM32APB_TIM1_CLKIN STM32_PCLK2_FREQUENCY + +/* APB1 clock (PCLK1) is HCLK/2 (35.9424MHz) */ + +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd2 +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/2) + +#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) + +/* LED definitions **********************************************************/ + +/* There are four LEDs on stm32butterfly2 board that can be controlled by + * software. + * All pulled high and van be illuminated by driving the output low. + * + * LED1 PB0 + * LED2 PB1 + * LED3 PC4 + * LED4 PC5 + */ + +/* LED index values for use with board_userled() */ + +#define BOARD_LED1 0 +#define BOARD_LED2 1 +#define BOARD_LED3 2 +#define BOARD_LED4 3 +#define BOARD_NLEDS 4 + +/* LED bits for use with board_userled_all() */ + +#define BOARD_LED1_BIT (1 << BOARD_LED1) +#define BOARD_LED2_BIT (1 << BOARD_LED2) +#define BOARD_LED3_BIT (1 << BOARD_LED3) +#define BOARD_LED4_BIT (1 << BOARD_LED4) + +/* These LEDs are not used by the board port unless CONFIG_ARCH_LEDS is + * defined. In thath case, the usage by the board port is defined in + * include/board.h and src/stm32_leds.c. The LEDs are used to encode + * OS-related events as follows: + * + * SYMBOL Val Meaning LED state + * LED1 LED2 LED3 LED4 + * ----------------- --- ----------------------- ---- ---- ---- ---- + */ + +#define LED_STARTED 0 /* NuttX has been started ON OFF OFF OFF */ +#define LED_HEAPALLOCATE 1 /* Heap has been allocated OFF ON OFF OFF */ +#define LED_IRQSENABLED 2 /* Interrupts enabled OFF OFF ON OFF */ +#define LED_STACKCREATED 3 /* Idle stack created OFF OFF OFF ON */ +#define LED_INIRQ 5 /* In an interrupt N/C N/C N/C GLOW */ +#define LED_SIGNAL 6 /* In a signal handler N/C N/C N/C GLOW */ +#define LED_ASSERTION 7 /* An assertion failed N/C N/C N/C GLOW */ +#define LED_PANIC 8 /* The system has crashed N/C N/C N/C FLASH */ +#undef LED_IDLE /* MCU is in sleep mode Not used */ + +/* After booting, LED1-3 are not longer used by the system and can be used + * for other purposes by the application (Of course, all LEDs are available + * to the application if CONFIG_ARCH_LEDS is not defined. + */ + +/* ADC configuration. Right now only ADC12_IN10 is supported + * (potentiometer) + */ + +#ifdef CONFIG_STM32_ADC2 +# error "CONFIG_STM32_ADC2 is not supported" +#endif + +/* SPI configuration. Only SPI1 is supported */ + +#ifdef CONFIG_STM32_SPI2 +# error "CONFIG_STM32_SPI2 is not supported" +#endif + +/* Alternate function pin selections (auto-aliased for new pinmap) */ + +/* USART2 */ + +#define GPIO_USART2_TX GPIO_ADJUST_MODE(GPIO_USART2_TX_0, GPIO_MODE_50MHz) +#define GPIO_USART2_RX GPIO_USART2_RX_0 +#define GPIO_USART2_CTS GPIO_USART2_CTS_0 +#define GPIO_USART2_RTS GPIO_ADJUST_MODE(GPIO_USART2_RTS_0, GPIO_MODE_50MHz) +#define GPIO_USART2_CK GPIO_ADJUST_MODE(GPIO_USART2_CK_0, GPIO_MODE_50MHz) + +/* SPI1 */ + +#define GPIO_SPI1_NSS GPIO_ADJUST_MODE(GPIO_SPI1_NSS_0, GPIO_MODE_50MHz) +#define GPIO_SPI1_SCK GPIO_ADJUST_MODE(GPIO_SPI1_SCK_0, GPIO_MODE_50MHz) +#define GPIO_SPI1_MISO GPIO_ADJUST_MODE(GPIO_SPI1_MISO_0, GPIO_MODE_50MHz) +#define GPIO_SPI1_MOSI GPIO_ADJUST_MODE(GPIO_SPI1_MOSI_0, GPIO_MODE_50MHz) + +/* USB */ + +#define GPIO_USB_DM GPIO_USB_DM_0 +#define GPIO_USB_DP GPIO_USB_DP_0 + +/* MCO */ + +#define GPIO_MCO GPIO_ADJUST_MODE(GPIO_MCO_0, GPIO_MODE_50MHz) + +/* Ethernet (MII/RMII) */ + +#define GPIO_ETH_MDC GPIO_ADJUST_MODE(GPIO_ETH_MDC_0, GPIO_MODE_50MHz) +#define GPIO_ETH_MDIO GPIO_ADJUST_MODE(GPIO_ETH_MDIO_0, GPIO_MODE_50MHz) +#define GPIO_ETH_MII_COL GPIO_ETH_MII_COL_0 +#define GPIO_ETH_MII_CRS GPIO_ETH_MII_CRS_0 +#define GPIO_ETH_MII_RX_CLK GPIO_ETH_MII_RX_CLK_0 +#define GPIO_ETH_MII_RXD0 GPIO_ETH_MII_RXD0_0 +#define GPIO_ETH_MII_RXD1 GPIO_ETH_MII_RXD1_0 +#define GPIO_ETH_MII_RXD2 GPIO_ETH_MII_RXD2_0 +#define GPIO_ETH_MII_RXD3 GPIO_ETH_MII_RXD3_0 +#define GPIO_ETH_MII_RX_DV GPIO_ETH_MII_RX_DV_0 +#define GPIO_ETH_MII_RX_ER GPIO_ETH_MII_RX_ER_0 +#define GPIO_ETH_MII_TX_CLK GPIO_ETH_MII_TX_CLK_0 +#define GPIO_ETH_MII_TXD0 GPIO_ADJUST_MODE(GPIO_ETH_MII_TXD0_0, GPIO_MODE_50MHz) +#define GPIO_ETH_MII_TXD1 GPIO_ADJUST_MODE(GPIO_ETH_MII_TXD1_0, GPIO_MODE_50MHz) +#define GPIO_ETH_MII_TXD2 GPIO_ADJUST_MODE(GPIO_ETH_MII_TXD2_0, GPIO_MODE_50MHz) +#define GPIO_ETH_MII_TXD3 GPIO_ADJUST_MODE(GPIO_ETH_MII_TXD3_0, GPIO_MODE_50MHz) +#define GPIO_ETH_MII_TX_EN GPIO_ADJUST_MODE(GPIO_ETH_MII_TX_EN_0, GPIO_MODE_50MHz) +#define GPIO_ETH_RMII_CRS_DV GPIO_ETH_RMII_CRS_DV_0 +#define GPIO_ETH_RMII_REF_CLK GPIO_ETH_RMII_REF_CLK_0 +#define GPIO_ETH_RMII_RXD0 GPIO_ETH_RMII_RXD0_0 +#define GPIO_ETH_RMII_RXD1 GPIO_ETH_RMII_RXD1_0 +#define GPIO_ETH_RMII_TXD0 GPIO_ADJUST_MODE(GPIO_ETH_RMII_TXD0_0, GPIO_MODE_50MHz) +#define GPIO_ETH_RMII_TXD1 GPIO_ADJUST_MODE(GPIO_ETH_RMII_TXD1_0, GPIO_MODE_50MHz) +#define GPIO_ETH_RMII_TX_EN GPIO_ADJUST_MODE(GPIO_ETH_RMII_TX_EN_0, GPIO_MODE_50MHz) + +/* USB OTG FS */ + +#define GPIO_OTGFS_DM GPIO_ADJUST_MODE(GPIO_OTGFS_DM_0, GPIO_MODE_50MHz) +#define GPIO_OTGFS_DP GPIO_ADJUST_MODE(GPIO_OTGFS_DP_0, GPIO_MODE_50MHz) +#define GPIO_OTGFS_ID GPIO_ADJUST_MODE(GPIO_OTGFS_ID_0, GPIO_MODE_50MHz) +#define GPIO_OTGFS_SOF GPIO_ADJUST_MODE(GPIO_OTGFS_SOF_0, GPIO_MODE_50MHz) +#define GPIO_OTGFS_VBUS GPIO_OTGFS_VBUS_0 + +#endif /* __BOARDS_ARM_STM32_STM32_BUTTERFLY2_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32f1/stm32butterfly2/scripts/Make.defs b/boards/arm/stm32f1/stm32butterfly2/scripts/Make.defs new file mode 100644 index 0000000000000..42d7ff815b502 --- /dev/null +++ b/boards/arm/stm32f1/stm32butterfly2/scripts/Make.defs @@ -0,0 +1,46 @@ +############################################################################ +# boards/arm/stm32f1/stm32butterfly2/scripts/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/.config +include $(TOPDIR)/tools/Config.mk +include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs + +ifeq ($(CONFIG_STM32_DFU),y) + LDSCRIPT = dfu.ld +else + LDSCRIPT = flash.ld +endif + +ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) + +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-gotoff.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32f1/stm32butterfly2/scripts/dfu.ld b/boards/arm/stm32f1/stm32butterfly2/scripts/dfu.ld new file mode 100644 index 0000000000000..dcdeb43f940d6 --- /dev/null +++ b/boards/arm/stm32f1/stm32butterfly2/scripts/dfu.ld @@ -0,0 +1,118 @@ +/**************************************************************************** + * boards/arm/stm32f1/stm32butterfly2/scripts/dfu.ld + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +MEMORY +{ + flash (rx) : ORIGIN = 0x08003000, LENGTH = 208K + sram (rwx) : ORIGIN = 0x20000000, LENGTH = 64K +} + +OUTPUT_ARCH(arm) +EXTERN(_vectors) +ENTRY(_stext) +SECTIONS +{ + .text : { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > flash + + .init_section : { + _sinit = ABSOLUTE(.); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) + _einit = ABSOLUTE(.); + } > flash + + .ARM.extab : { + *(.ARM.extab*) + } > flash + + __exidx_start = ABSOLUTE(.); + .ARM.exidx : { + *(.ARM.exidx*) + } > flash + __exidx_end = ABSOLUTE(.); + + .tdata : { + _stdata = ABSOLUTE(.); + *(.tdata .tdata.* .gnu.linkonce.td.*); + _etdata = ABSOLUTE(.); + } > flash + + .tbss : { + _stbss = ABSOLUTE(.); + *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); + _etbss = ABSOLUTE(.); + } > flash + + _eronly = ABSOLUTE(.); + + /* The RAM vector table (if present) should lie at the beginning of SRAM */ + + .ram_vectors : { + *(.ram_vectors) + } > sram + + .data : { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > sram AT > flash + + .bss : { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(8); + _ebss = ABSOLUTE(.); + } > sram + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/stm32f1/stm32butterfly2/scripts/flash.ld b/boards/arm/stm32f1/stm32butterfly2/scripts/flash.ld new file mode 100644 index 0000000000000..3fc5750bbfc16 --- /dev/null +++ b/boards/arm/stm32f1/stm32butterfly2/scripts/flash.ld @@ -0,0 +1,118 @@ +/**************************************************************************** + * boards/arm/stm32f1/stm32butterfly2/scripts/flash.ld + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +MEMORY +{ + flash (rx) : ORIGIN = 0x08000000, LENGTH = 256K + sram (rwx) : ORIGIN = 0x20000000, LENGTH = 64K +} + +OUTPUT_ARCH(arm) +EXTERN(_vectors) +ENTRY(_stext) +SECTIONS +{ + .text : { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > flash + + .init_section : { + _sinit = ABSOLUTE(.); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) + _einit = ABSOLUTE(.); + } > flash + + .ARM.extab : { + *(.ARM.extab*) + } > flash + + __exidx_start = ABSOLUTE(.); + .ARM.exidx : { + *(.ARM.exidx*) + } > flash + __exidx_end = ABSOLUTE(.); + + .tdata : { + _stdata = ABSOLUTE(.); + *(.tdata .tdata.* .gnu.linkonce.td.*); + _etdata = ABSOLUTE(.); + } > flash + + .tbss : { + _stbss = ABSOLUTE(.); + *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); + _etbss = ABSOLUTE(.); + } > flash + + _eronly = ABSOLUTE(.); + + /* The RAM vector table (if present) should lie at the beginning of SRAM */ + + .ram_vectors : { + *(.ram_vectors) + } > sram + + .data : { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > sram AT > flash + + .bss : { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(8); + _ebss = ABSOLUTE(.); + } > sram + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/stm32f1/stm32butterfly2/src/CMakeLists.txt b/boards/arm/stm32f1/stm32butterfly2/src/CMakeLists.txt new file mode 100644 index 0000000000000..6005e74d05fb6 --- /dev/null +++ b/boards/arm/stm32f1/stm32butterfly2/src/CMakeLists.txt @@ -0,0 +1,55 @@ +# ############################################################################## +# boards/arm/stm32f1/stm32butterfly2/src/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(SRCS stm32_boot.c stm32_leds.c) + +if(CONFIG_STM32_ADC) + list(APPEND SRCS stm32_adc.c) +endif() + +if(CONFIG_STM32_SPI1) + list(APPEND SRCS stm32_spi.c) +endif() + +if(CONFIG_STM32_OTGFS) + list(APPEND SRCS stm32_usb.c) +endif() + +if(CONFIG_STM32_USBHOST) + list(APPEND SRCS stm32_usbhost.c) +endif() + +if(CONFIG_USBDEV) + list(APPEND SRCS stm32_usbdev.c) +endif() + +if(CONFIG_MMCSD) + list(APPEND SRCS stm32_mmcsd.c) +endif() + +if(CONFIG_ARCH_BUTTONS) + list(APPEND SRCS stm32_buttons.c) +endif() + +target_sources(board PRIVATE ${SRCS}) + +set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/flash.ld") diff --git a/boards/arm/stm32f1/stm32butterfly2/src/Make.defs b/boards/arm/stm32f1/stm32butterfly2/src/Make.defs new file mode 100644 index 0000000000000..f6e1bc4b4f599 --- /dev/null +++ b/boards/arm/stm32f1/stm32butterfly2/src/Make.defs @@ -0,0 +1,57 @@ +############################################################################ +# boards/arm/stm32f1/stm32butterfly2/src/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +CSRCS = stm32_boot.c stm32_leds.c + +ifeq ($(CONFIG_STM32_ADC),y) +CSRCS += stm32_adc.c +endif + +ifeq ($(CONFIG_STM32_SPI1),y) +CSRCS += stm32_spi.c +endif + +ifeq ($(CONFIG_STM32_OTGFS),y) +CSRCS += stm32_usb.c +endif + +ifeq ($(CONFIG_STM32_USBHOST),y) +CSRCS += stm32_usbhost.c +endif + +ifeq ($(CONFIG_USBDEV),y) +CSRCS += stm32_usbdev.c +endif + +ifeq ($(CONFIG_MMCSD),y) +CSRCS += stm32_mmcsd.c +endif + +ifeq ($(CONFIG_ARCH_BUTTONS),y) +CSRCS += stm32_buttons.c +endif + +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32f1/stm32butterfly2/src/stm32_adc.c b/boards/arm/stm32f1/stm32butterfly2/src/stm32_adc.c new file mode 100644 index 0000000000000..e38387e607b72 --- /dev/null +++ b/boards/arm/stm32f1/stm32butterfly2/src/stm32_adc.c @@ -0,0 +1,78 @@ +/**************************************************************************** + * boards/arm/stm32f1/stm32butterfly2/src/stm32_adc.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include "chip.h" +#include "stm32_adc.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_adc_setup + * + * Description: + * Initialize ADC and register the ADC driver. + * + ****************************************************************************/ + +int stm32_adc_setup(void) +{ + static bool initialized = false; + uint8_t channel[1] = + { + 10 + }; + + struct adc_dev_s *adc; + int rv; + + if (initialized) + { + return OK; + } + + ainfo("INFO: Initializing ADC12_IN10\n"); + stm32_configgpio(GPIO_ADC12_IN10_0); + if ((adc = stm32_adcinitialize(1, channel, 1)) == NULL) + { + aerr("ERROR: Failed to get adc interface\n"); + return -ENODEV; + } + + if ((rv = adc_register("/dev/adc0", adc)) < 0) + { + aerr("ERROR: adc_register failed: %d\n", rv); + return rv; + } + + initialized = true; + ainfo("INFO: ADC12_IN10 initialized successfully\n"); + return OK; +} diff --git a/boards/arm/stm32f1/stm32butterfly2/src/stm32_boot.c b/boards/arm/stm32f1/stm32butterfly2/src/stm32_boot.c new file mode 100644 index 0000000000000..b3391b7eb5699 --- /dev/null +++ b/boards/arm/stm32f1/stm32butterfly2/src/stm32_boot.c @@ -0,0 +1,100 @@ +/**************************************************************************** + * boards/arm/stm32f1/stm32butterfly2/src/stm32_boot.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include + +#include "stm32_butterfly2.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_boardinitialize + * + * Description: + * Initializes low level pins for the drivers. + ****************************************************************************/ + +void stm32_boardinitialize(void) +{ + stm32_led_initialize(); + stm32_spidev_initialize(); + stm32_usb_initialize(); +} + +/**************************************************************************** + * Name: board_late_initialize + * + * Description: + * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_late_initialize(). board_late_initialize() will + * be called immediately after up_initialize() is called and just before + * the initial application is started. This additional initialization + * phase may be used, for example, to initialize board-specific device + * drivers. + * + ****************************************************************************/ + +#ifdef CONFIG_BOARD_LATE_INITIALIZE +void board_late_initialize(void) +{ + int ret = 0; + +#ifdef CONFIG_MMCSD + ret = stm32_mmcsd_initialize(CONFIG_NSH_MMCSDMINOR); + if (ret < 0) + { + syslog(LOG_ERR, "Failed to initialize SD slot: %d\n", ret); + return; + } +#endif + +#ifdef CONFIG_USBHOST + ret = stm32_usbhost_initialize(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to initialize USB host: %d\n", ret); + return; + } +#endif + +#ifdef CONFIG_ADC + /* Initialize ADC and register the ADC driver. */ + + ret = stm32_adc_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_adc_setup failed: %d\n", ret); + } +#endif + + UNUSED(ret); +} +#endif diff --git a/boards/arm/stm32/stm32butterfly2/src/stm32_butterfly2.h b/boards/arm/stm32f1/stm32butterfly2/src/stm32_butterfly2.h similarity index 98% rename from boards/arm/stm32/stm32butterfly2/src/stm32_butterfly2.h rename to boards/arm/stm32f1/stm32butterfly2/src/stm32_butterfly2.h index f034a407985b3..1f7def6679975 100644 --- a/boards/arm/stm32/stm32butterfly2/src/stm32_butterfly2.h +++ b/boards/arm/stm32f1/stm32butterfly2/src/stm32_butterfly2.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32butterfly2/src/stm32_butterfly2.h + * boards/arm/stm32f1/stm32butterfly2/src/stm32_butterfly2.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f1/stm32butterfly2/src/stm32_buttons.c b/boards/arm/stm32f1/stm32butterfly2/src/stm32_buttons.c new file mode 100644 index 0000000000000..8f5f81e84e817 --- /dev/null +++ b/boards/arm/stm32f1/stm32butterfly2/src/stm32_buttons.c @@ -0,0 +1,99 @@ +/**************************************************************************** + * boards/arm/stm32f1/stm32butterfly2/src/stm32_buttons.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "stm32_gpio.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define NUM_BUTTONS 5 + +#define GPIO_JOY_O (GPIO_INPUT | GPIO_CNF_INFLOAT | GPIO_MODE_INPUT |\ + GPIO_PORTC | GPIO_PIN7) +#define GPIO_JOY_U (GPIO_INPUT | GPIO_CNF_INFLOAT | GPIO_MODE_INPUT |\ + GPIO_PORTC | GPIO_PIN8) +#define GPIO_JOY_D (GPIO_INPUT | GPIO_CNF_INFLOAT | GPIO_MODE_INPUT |\ + GPIO_PORTC | GPIO_PIN9) +#define GPIO_JOY_R (GPIO_INPUT | GPIO_CNF_INFLOAT | GPIO_MODE_INPUT |\ + GPIO_PORTC | GPIO_PIN10) +#define GPIO_JOY_L (GPIO_INPUT | GPIO_CNF_INFLOAT | GPIO_MODE_INPUT |\ + GPIO_PORTC | GPIO_PIN11) + +/**************************************************************************** + * Private Declarations + ****************************************************************************/ + +static const uint32_t buttons[NUM_BUTTONS] = +{ + GPIO_JOY_O, GPIO_JOY_U, GPIO_JOY_D, GPIO_JOY_R, GPIO_JOY_L +}; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_button_initialize + * + * Description: + * Initializes gpio pins for joystick buttons + ****************************************************************************/ + +uint32_t board_button_initialize(void) +{ + int i; + + for (i = 0; i != NUM_BUTTONS; ++i) + { + stm32_configgpio(buttons[i]); + } + + return NUM_BUTTONS; +} + +/**************************************************************************** + * Name: board_buttons + * + * Description: + * Reads keys + ****************************************************************************/ + +uint32_t board_buttons(void) +{ + uint32_t rv = 0; + int i; + + for (i = 0; i != NUM_BUTTONS; ++i) + { + if (stm32_gpioread(buttons[i]) == 0) + { + rv |= 1 << i; + } + } + + return rv; +} diff --git a/boards/arm/stm32f1/stm32butterfly2/src/stm32_leds.c b/boards/arm/stm32f1/stm32butterfly2/src/stm32_leds.c new file mode 100644 index 0000000000000..08723b683580f --- /dev/null +++ b/boards/arm/stm32f1/stm32butterfly2/src/stm32_leds.c @@ -0,0 +1,257 @@ +/**************************************************************************** + * boards/arm/stm32f1/stm32butterfly2/src/stm32_leds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include +#include +#include + +#include "stm32_gpio.h" + +/**************************************************************************** + * Pre-processor definitions + ****************************************************************************/ + +#define GPIO_LED1 (GPIO_OUTPUT | GPIO_CNF_OUTPP | GPIO_MODE_50MHz |\ + GPIO_OUTPUT_SET | GPIO_PORTB | GPIO_PIN0) +#define GPIO_LED2 (GPIO_OUTPUT | GPIO_CNF_OUTPP | GPIO_MODE_50MHz |\ + GPIO_OUTPUT_SET | GPIO_PORTB | GPIO_PIN1) +#define GPIO_LED3 (GPIO_OUTPUT | GPIO_CNF_OUTPP | GPIO_MODE_50MHz |\ + GPIO_OUTPUT_SET | GPIO_PORTC | GPIO_PIN4) +#define GPIO_LED4 (GPIO_OUTPUT | GPIO_CNF_OUTPP | GPIO_MODE_50MHz |\ + GPIO_OUTPUT_SET | GPIO_PORTC | GPIO_PIN5) + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/* Identifies led state */ + +enum led_state +{ + LED_ON = false, + LED_OFF = true +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: led_state + * + * Description: + * Sets pack of leds to given state + ****************************************************************************/ + +static void led_state(enum led_state state, unsigned int leds) +{ + if (leds & BOARD_LED1_BIT) + { + stm32_gpiowrite(GPIO_LED1, state); + } + + if (leds & BOARD_LED2_BIT) + { + stm32_gpiowrite(GPIO_LED2, state); + } + + if (leds & BOARD_LED3_BIT) + { + stm32_gpiowrite(GPIO_LED3, state); + } + + if (leds & BOARD_LED4_BIT) + { + stm32_gpiowrite(GPIO_LED4, state); + } +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_led_initialize + * + * Description: + * Initializes low level gpio pins for board LEDS + ****************************************************************************/ + +void stm32_led_initialize(void) +{ + stm32_configgpio(GPIO_LED1); + stm32_configgpio(GPIO_LED2); + stm32_configgpio(GPIO_LED3); + stm32_configgpio(GPIO_LED4); +} + +#ifdef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Name: board_autoled_on + * + * Description: + * Drives board leds when specific RTOS state led occurs. + * + * Input Parameters: + * led - This is actually RTOS state not led number of anything like that + ****************************************************************************/ + +void board_autoled_on(int led) +{ + switch (led) + { + case LED_STARTED: + led_state(LED_OFF, BOARD_LED2_BIT | BOARD_LED3_BIT | BOARD_LED4_BIT); + led_state(LED_ON, BOARD_LED1_BIT); + break; + + case LED_HEAPALLOCATE: + led_state(LED_OFF, BOARD_LED1_BIT | BOARD_LED3_BIT | BOARD_LED4_BIT); + led_state(LED_ON, BOARD_LED2_BIT); + break; + + case LED_IRQSENABLED: + led_state(LED_OFF, BOARD_LED1_BIT | BOARD_LED2_BIT | BOARD_LED4_BIT); + led_state(LED_ON, BOARD_LED3_BIT); + break; + + case LED_STACKCREATED: + led_state(LED_OFF, BOARD_LED1_BIT | BOARD_LED2_BIT | BOARD_LED3_BIT); + led_state(LED_ON, BOARD_LED4_BIT); + break; + + case LED_INIRQ: + case LED_SIGNAL: + case LED_ASSERTION: + case LED_PANIC: + led_state(LED_ON, BOARD_LED4_BIT); + break; + } +} + +/**************************************************************************** + * Name: board_autoled_off + * + * Description: + * Drives board leds when specific RTOS state led ends + * + * Input Parameters: + * led - This is actually RTOS state not led number of anything like that + ****************************************************************************/ + +void board_autoled_off(int led) +{ + switch (led) + { + case LED_STARTED: + led_state(LED_OFF, BOARD_LED1_BIT); + break; + + case LED_HEAPALLOCATE: + led_state(LED_OFF, BOARD_LED2_BIT); + break; + + case LED_IRQSENABLED: + led_state(LED_OFF, BOARD_LED3_BIT); + break; + + case LED_STACKCREATED: + case LED_INIRQ: + case LED_SIGNAL: + case LED_ASSERTION: + case LED_PANIC: + led_state(LED_OFF, BOARD_LED4_BIT); + break; + } +} +#endif + +/**************************************************************************** + * Name: board_userled_initialize + * + * Description: + * This function should initialize leds for user use, but on RTOS start we + * initialize every led for use by RTOS and at end, when RTOS is fully + * booted up, we give control of these specific leds for user. So that's + * why this function is empty. + ****************************************************************************/ + +uint32_t board_userled_initialize(void) +{ + /* Already initialized by stm32_led_initialize. */ + + return BOARD_NLEDS; +} + +/**************************************************************************** + * Name: board_userled + * + * Description: + * Sets led to ledon state. + * + * Input Parameters: + * led - Led to be set, indexed from 0 + * ledon - new state for the led. + ****************************************************************************/ + +void board_userled(int led, bool ledon) +{ + unsigned int ledbit; + +#ifndef CONFIG_ARCH_LEDS + if (led == BOARD_LED4) + { + return; + } +#endif + + ledbit = 1 << led; + led_state(ledon, ledbit); +} + +/**************************************************************************** + * Name: board_userled_all + * + * Description: + * Sets whole ledset to given state. + * + * Input Parameters: + * ledset - Led bits to be set on or off + ****************************************************************************/ + +void board_userled_all(uint32_t ledset) +{ +#ifdef CONFIG_ARCH_LEDS + led_state(LED_ON, ledset & ~BOARD_LED4_BIT); + led_state(LED_OFF, ~(ledset | BOARD_LED4_BIT)); +#else + led_state(LED_ON, ledset); + led_state(LED_OFF, ~ledset); +#endif +} diff --git a/boards/arm/stm32f1/stm32butterfly2/src/stm32_mmcsd.c b/boards/arm/stm32f1/stm32butterfly2/src/stm32_mmcsd.c new file mode 100644 index 0000000000000..b471480af3487 --- /dev/null +++ b/boards/arm/stm32f1/stm32butterfly2/src/stm32_mmcsd.c @@ -0,0 +1,203 @@ +/**************************************************************************** + * boards/arm/stm32f1/stm32butterfly2/src/stm32_mmcsd.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include "stm32.h" +#include "stm32_butterfly2.h" +#include "stm32_spi.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifndef CONFIG_STM32_SPI1 +# error "SD driver requires CONFIG_STM32_SPI1 to be enabled" +#endif + +#ifdef CONFIG_DISABLE_MOUNTPOINT +# error "SD driver requires CONFIG_DISABLE_MOUNTPOINT to be disabled" +#endif + +/**************************************************************************** + * Private Definitions + ****************************************************************************/ + +static const int SD_SPI_PORT = 1; /* SD is connected to SPI1 port */ +static const int SD_SLOT_NO = 0; /* There is only one SD slot */ + +/* Media changed callback */ + +static spi_mediachange_t g_chmediaclbk; + +/* Argument for media changed callback */ + +static void *g_chmediaarg; + +/* Semafor to inform stm32_cd_thread that card was inserted or pulled out */ + +static sem_t g_cdsem = SEM_INITIALIZER(0); + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_cd_thread + * + * Description: + * Working thread to call mediachanged function when card is inserted or + * pulled out. + ****************************************************************************/ + +static void *stm32_cd_thread(void *arg) +{ + spiinfo("INFO: Running card detect thread\n"); + while (1) + { + nxsem_wait(&g_cdsem); + spiinfo("INFO: Card has been inserted, initializing\n"); + + if (g_chmediaclbk) + { + /* Card doesn't seem to initialize properly without letting it to + * rest for a millisecond or so. + */ + + nxsched_usleep(1 * 1000); + g_chmediaclbk(g_chmediaarg); + } + } + + return NULL; +} + +/**************************************************************************** + * Name: stm32_cd + * + * Description: + * Card detect interrupt handler. + ****************************************************************************/ + +static int stm32_cd(int irq, void *context, void *arg) +{ + static const int debounce_time = 100; /* [ms] */ + static uint32_t now = 0; + static uint32_t prev = 0; + struct timespec tp; + + clock_systime_timespec(&tp); + now = tp.tv_sec * 1000 + tp.tv_nsec / 1000000; + + /* When inserting card, card detect plate might bounce causing this + * interrupt to be called many time on single card insert/deinsert. Thus + * we are allowing only one interrupt every 100ms. + */ + + if (now - debounce_time > prev) + { + prev = now; + nxsem_post(&g_cdsem); + } + + return OK; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_spi1register + * + * Description: + * Registers media change callback + ****************************************************************************/ + +int stm32_spi1register(struct spi_dev_s *dev, spi_mediachange_t callback, + void *arg) +{ + spiinfo("INFO: Registering spi1 device\n"); + g_chmediaclbk = callback; + g_chmediaarg = arg; + return OK; +} + +/**************************************************************************** + * Name: stm32_mmcsd_initialize + * + * Description: + * Initialize SPI-based SD card and card detect thread. + ****************************************************************************/ + +int stm32_mmcsd_initialize(int minor) +{ + struct spi_dev_s *spi; + struct sched_param schparam; + pthread_attr_t pattr; + int rv; + + spiinfo("INFO: Initializing mmcsd card\n"); + if ((spi = stm32_spibus_initialize(SD_SPI_PORT)) == NULL) + { + ferr("failed to initialize SPI port %d\n", SD_SPI_PORT); + return -ENODEV; + } + + if ((rv = mmcsd_spislotinitialize(minor, SD_SLOT_NO, spi)) < 0) + { + ferr("failed to bind SPI port %d to SD slot %d\n", SD_SPI_PORT, + SD_SLOT_NO); + return rv; + } + + stm32_gpiosetevent(GPIO_SD_CD, true, true, true, stm32_cd, NULL); + + pthread_attr_init(&pattr); +#ifdef CONFIG_DEBUG_FS + pthread_attr_setstacksize(&pattr, 1024); +#else + pthread_attr_setstacksize(&pattr, 256); +#endif + + schparam.sched_priority = 50; + pthread_attr_setschedparam(&pattr, &schparam); + pthread_create(NULL, &pattr, stm32_cd_thread, NULL); + + spiinfo("INFO: mmcsd card has been initialized successfully\n"); + return OK; +} diff --git a/boards/arm/stm32f1/stm32butterfly2/src/stm32_spi.c b/boards/arm/stm32f1/stm32butterfly2/src/stm32_spi.c new file mode 100644 index 0000000000000..0d6e77b58db94 --- /dev/null +++ b/boards/arm/stm32f1/stm32butterfly2/src/stm32_spi.c @@ -0,0 +1,98 @@ +/**************************************************************************** + * boards/arm/stm32f1/stm32butterfly2/src/stm32_spi.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include "stm32_butterfly2.h" +#include "stm32_gpio.h" +#include "stm32_spi.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_spidev_initialize + * + * Description: + * Called to configure SPI chip select GPIO pins. + * + * Note: + * Here only CS pins are configured as SPI pins are configured by driver + * itself. + ****************************************************************************/ + +void stm32_spidev_initialize(void) +{ + spiinfo("INFO: Initializing spi gpio pins\n"); + + stm32_configgpio(GPIO_SD_CS); + stm32_configgpio(GPIO_SD_CD); +} + +/**************************************************************************** + * Name: stm32_spi1select + * + * Description: + * Function asserts given devid based on select + ****************************************************************************/ + +void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, + bool select) +{ + spiinfo("INFO: Selecting spi dev: %" PRId32 ", state: %d\n", + devid, select); + + if (devid == SPIDEV_MMCSD(0)) + { + stm32_gpiowrite(GPIO_SD_CS, !select); + } +} + +/**************************************************************************** + * Name: stm32_spi1status + * + * Description: + * Return status of devid + ****************************************************************************/ + +uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) +{ + spiinfo("INFO: Requesting info from spi dev: %" PRId32 "\n", devid); + + if (devid == SPIDEV_MMCSD(0)) + { + if (stm32_gpioread(GPIO_SD_CD) == 0) + { + return SPI_STATUS_PRESENT; + } + } + + return 0; +} diff --git a/boards/arm/stm32f1/stm32butterfly2/src/stm32_usb.c b/boards/arm/stm32f1/stm32butterfly2/src/stm32_usb.c new file mode 100644 index 0000000000000..53cdb720cf874 --- /dev/null +++ b/boards/arm/stm32f1/stm32butterfly2/src/stm32_usb.c @@ -0,0 +1,51 @@ +/**************************************************************************** + * boards/arm/stm32f1/stm32butterfly2/src/stm32_usb.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "stm32_gpio.h" + +#include +#include "stm32_butterfly2.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_usb_initialize + * + * Description: + * Initializes USB pins + ****************************************************************************/ + +void stm32_usb_initialize(void) +{ + uinfo("INFO: Initializing usb otgfs gpio pins\n"); + + stm32_configgpio(GPIO_OTGFS_VBUS); + stm32_configgpio(GPIO_OTGFS_PWRON); +} diff --git a/boards/arm/stm32f1/stm32butterfly2/src/stm32_usbdev.c b/boards/arm/stm32f1/stm32butterfly2/src/stm32_usbdev.c new file mode 100644 index 0000000000000..b7414d0669f3f --- /dev/null +++ b/boards/arm/stm32f1/stm32butterfly2/src/stm32_usbdev.c @@ -0,0 +1,65 @@ +/**************************************************************************** + * boards/arm/stm32f1/stm32butterfly2/src/stm32_usbdev.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include + +#include "stm32_otgfs.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifndef CONFIG_STM32_OTGFS +# error "CONFIG_USBDEV requires CONFIG_STM32_OTGFS to be enabled" +#endif + +#ifdef CONFIG_USBHOST +# error "CONFIG_USBDEV cannot be set alongside CONFIG_USBHOST" +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_usbsuspend + * + * Description: + * Board logic must provide the stm32_usbsuspend logic if the USBDEV driver + * is used. This function is called whenever the USB enters or leaves + * suspend mode. This is an opportunity for the board logic to shutdown + * clocks, power, etc. while the USB is suspended. + * + * TODO: + * - Well... implement those features like clock shutdown. + ****************************************************************************/ + +void stm32_usbsuspend(struct usbdev_s *dev, bool resume) +{ + uinfo("INFO: usb %s", resume ? "resumed" : "suspended"); +} diff --git a/boards/arm/stm32f1/stm32butterfly2/src/stm32_usbhost.c b/boards/arm/stm32f1/stm32butterfly2/src/stm32_usbhost.c new file mode 100644 index 0000000000000..6510e703c9b53 --- /dev/null +++ b/boards/arm/stm32f1/stm32butterfly2/src/stm32_usbhost.c @@ -0,0 +1,187 @@ +/**************************************************************************** + * boards/arm/stm32f1/stm32butterfly2/src/stm32_usbhost.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "stm32.h" +#include "stm32_butterfly2.h" +#include "stm32_otgfs.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifndef CONFIG_STM32_OTGFS +# error "CONFIG_USBHOST requires CONFIG_STM32_OTGFS to be enabled" +#endif + +#ifdef CONFIG_USBDEV +# error "CONFIG_USBHOST cannot be set alongside CONFIG_USBDEV" +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static struct usbhost_connection_s *g_usbconn; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: usbhost_detect + * + * Description: + * Wait for USB devices to be connected. + ****************************************************************************/ + +static void *usbhost_detect(void *arg) +{ + struct usbhost_hubport_s *hport; + + uinfo("INFO: Starting usb detect thread\n"); + + for (; ; ) + { + CONN_WAIT(g_usbconn, &hport); + + if (hport->connected) + { + CONN_ENUMERATE(g_usbconn, hport); + } + } + + return 0; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_usbhost_initialize + * + * Description: + * Initializes USB host functionality. + ****************************************************************************/ + +int stm32_usbhost_initialize(void) +{ + int rv; + +#ifdef CONFIG_USBHOST_MSC + uinfo("INFO: Initializing USB MSC class\n"); + + if ((rv = usbhost_msc_initialize()) < 0) + { + uerr("ERROR: Failed to register mass storage class: %d\n", rv); + } +#endif + +#ifdef CONFIG_USBHOST_CDACM + uinfo("INFO: Initializing CDCACM usb class\n"); + + if ((rv = usbhost_cdacm_initialize()) < 0) + { + uerr("ERROR: Failed to register CDC/ACM serial class: %d\n", rv); + } +#endif + +#ifdef CONFIG_USBHOST_HIDKBD + uinfo("INFO: Initializing HID Keyboard usb class\n"); + + if ((rv = usbhost_kbdinit()) < 0) + { + uerr("ERROR: Failed to register the KBD class: %d\n", rv); + } +#endif + +#ifdef CONFIG_USBHOST_HIDMOUSE + uinfo("INFO: Initializing HID Mouse usb class\n"); + + if ((rv = usbhost_mouse_init()) < 0) + { + uerr("ERROR: Failed to register the mouse class: %d\n", rv); + } +#endif + +#ifdef CONFIG_USBHOST_HUB + uinfo("INFO: Initializing USB HUB class\n"); + + if ((rv = usbhost_hub_initialize()) < 0) + { + uerr("ERROR: Failed to register hub class: %d\n", rv); + } +#endif + + if ((g_usbconn = stm32_otgfshost_initialize(0))) + { + pthread_attr_t pattr; + struct sched_param schparam; + + pthread_attr_init(&pattr); + pthread_attr_setstacksize(&pattr, 2048); + + schparam.sched_priority = 50; + pthread_attr_setschedparam(&pattr, &schparam); + + return pthread_create(NULL, &pattr, usbhost_detect, NULL); + } + + return -ENODEV; +} + +/**************************************************************************** + * Name: stm32_usbhost_vbusdrive + * + * Description: + * Enable/disable driving of VBUS 5V output. + * + * The application uses this field to control power to this port, and the + * core clears this bit on an overcurrent condition. + * + * Input Parameters: + * iface - For future growth to handle multiple USB host interface. + * Should be zero. + * enable - true: enable VBUS power; false: disable VBUS power + * + * Returned Value: + * None + ****************************************************************************/ + +void stm32_usbhost_vbusdrive(int iface, bool enable) +{ + stm32_gpiowrite(GPIO_OTGFS_PWRON, enable); +} diff --git a/boards/arm/stm32f1/stm32f103-minimum/CMakeLists.txt b/boards/arm/stm32f1/stm32f103-minimum/CMakeLists.txt new file mode 100644 index 0000000000000..617cc91dd8803 --- /dev/null +++ b/boards/arm/stm32f1/stm32f103-minimum/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32f1/stm32f103-minimum/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/arm/stm32/stm32f103-minimum/Kconfig b/boards/arm/stm32f1/stm32f103-minimum/Kconfig similarity index 100% rename from boards/arm/stm32/stm32f103-minimum/Kconfig rename to boards/arm/stm32f1/stm32f103-minimum/Kconfig diff --git a/boards/arm/stm32f1/stm32f103-minimum/configs/adb/defconfig b/boards/arm/stm32f1/stm32f103-minimum/configs/adb/defconfig new file mode 100644 index 0000000000000..36fb231b5a9fa --- /dev/null +++ b/boards/arm/stm32f1/stm32f103-minimum/configs/adb/defconfig @@ -0,0 +1,79 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_BINFMT_DISABLE is not set +# CONFIG_DISABLE_OS_API is not set +# CONFIG_FS_PROCFS_EXCLUDE_BLOCKS is not set +# CONFIG_FS_PROCFS_EXCLUDE_ENVIRON is not set +# CONFIG_FS_PROCFS_EXCLUDE_MEMDUMP is not set +# CONFIG_FS_PROCFS_EXCLUDE_MEMINFO is not set +# CONFIG_FS_PROCFS_EXCLUDE_MOUNT is not set +# CONFIG_FS_PROCFS_EXCLUDE_PROCESS is not set +# CONFIG_FS_PROCFS_EXCLUDE_UPTIME is not set +# CONFIG_FS_PROCFS_EXCLUDE_USAGE is not set +# CONFIG_FS_PROCFS_EXCLUDE_VERSION is not set +# CONFIG_FS_PROCFS_INCLUDE_PROGMEM is not set +# CONFIG_NSH_DISABLESCRIPT is not set +# CONFIG_NSH_DISABLE_EXEC is not set +# CONFIG_NSH_DISABLE_EXIT is not set +# CONFIG_NSH_DISABLE_GET is not set +# CONFIG_NSH_DISABLE_HEXDUMP is not set +# CONFIG_NSH_DISABLE_PUT is not set +# CONFIG_NSH_DISABLE_WGET is not set +# CONFIG_NSH_DISABLE_XD is not set +CONFIG_ADBD_DEVICE_ID="test" +CONFIG_ADBD_FILE_SERVICE=y +CONFIG_ADBD_SHELL_SERVICE=y +CONFIG_ADBD_USB_SERVER=y +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f103-minimum" +CONFIG_ARCH_BOARD_STM32F103_MINIMUM=y +CONFIG_ARCH_CHIP="stm32f1" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F103C8=y +CONFIG_ARCH_CHIP_STM32F1=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=5483 +CONFIG_BUILTIN=y +CONFIG_DEFAULT_SMALL=y +CONFIG_ENABLE_ALL_SIGNALS=y +CONFIG_EXAMPLES_HELLO=y +CONFIG_FILE_STREAM=y +CONFIG_FS_PROCFS=y +CONFIG_INIT_ENTRYPOINT="adbd_main" +CONFIG_INIT_STACKSIZE=1024 +CONFIG_LIBC_EXECFUNCS=y +CONFIG_LIBUV=y +CONFIG_LINE_MAX=80 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=1024 +CONFIG_PSEUDOTERM=y +CONFIG_RAM_SIZE=20480 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_CHILD_STATUS=y +CONFIG_SCHED_HAVE_PARENT=y +CONFIG_SCHED_WAITPID=y +CONFIG_SERIAL_TERMIOS=y +CONFIG_STACK_COLORATION=y +CONFIG_START_DAY=5 +CONFIG_START_MONTH=7 +CONFIG_START_YEAR=2011 +CONFIG_STM32_DFU=y +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_JTAG_FULL_ENABLE=y +CONFIG_STM32_USART1=y +CONFIG_STM32_USB=y +CONFIG_SYMTAB_ORDEREDBYNAME=y +CONFIG_SYSTEM_ADBD=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=8 +CONFIG_TLS_TASK_NELEM=4 +CONFIG_USART1_SERIAL_CONSOLE=y +CONFIG_USBADB=y +CONFIG_USBDEV_BUSPOWERED=y diff --git a/boards/arm/stm32f1/stm32f103-minimum/configs/apds9960/defconfig b/boards/arm/stm32f1/stm32f103-minimum/configs/apds9960/defconfig new file mode 100644 index 0000000000000..cbb116b3a5311 --- /dev/null +++ b/boards/arm/stm32f1/stm32f103-minimum/configs/apds9960/defconfig @@ -0,0 +1,61 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_DISABLE_OS_API is not set +# CONFIG_NSH_DISABLESCRIPT is not set +# CONFIG_NSH_DISABLE_EXEC is not set +# CONFIG_NSH_DISABLE_EXIT is not set +# CONFIG_NSH_DISABLE_GET is not set +# CONFIG_NSH_DISABLE_HEXDUMP is not set +# CONFIG_NSH_DISABLE_MKRD is not set +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_NSH_DISABLE_PUT is not set +# CONFIG_NSH_DISABLE_WGET is not set +# CONFIG_NSH_DISABLE_XD is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f103-minimum" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_STM32F103_MINIMUM=y +CONFIG_ARCH_CHIP="stm32f1" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F103C8=y +CONFIG_ARCH_CHIP_STM32F1=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=5483 +CONFIG_BUILTIN=y +CONFIG_DEFAULT_SMALL=y +CONFIG_EXAMPLES_APDS9960=y +CONFIG_FILE_STREAM=y +CONFIG_I2C_DRIVER=y +CONFIG_IDLETHREAD_STACKSIZE=512 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_LINE_MAX=80 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=1024 +CONFIG_PTHREAD_STACK_MIN=512 +CONFIG_RAM_SIZE=20480 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=192 +CONFIG_SCHED_HPWORKSTACKSIZE=3072 +CONFIG_SCHED_WAITPID=y +CONFIG_SENSORS=y +CONFIG_SENSORS_APDS9960=y +CONFIG_SERIAL_TERMIOS=y +CONFIG_START_DAY=5 +CONFIG_START_MONTH=7 +CONFIG_START_YEAR=2011 +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_I2C1=y +CONFIG_STM32_JTAG_FULL_ENABLE=y +CONFIG_STM32_USART1=y +CONFIG_SYMTAB_ORDEREDBYNAME=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f1/stm32f103-minimum/configs/audio_tone/defconfig b/boards/arm/stm32f1/stm32f103-minimum/configs/audio_tone/defconfig new file mode 100644 index 0000000000000..002da5d5dbb8a --- /dev/null +++ b/boards/arm/stm32f1/stm32f103-minimum/configs/audio_tone/defconfig @@ -0,0 +1,62 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_DISABLE_OS_API is not set +# CONFIG_NSH_DISABLESCRIPT is not set +# CONFIG_NSH_DISABLE_EXEC is not set +# CONFIG_NSH_DISABLE_EXIT is not set +# CONFIG_NSH_DISABLE_GET is not set +# CONFIG_NSH_DISABLE_HEXDUMP is not set +# CONFIG_NSH_DISABLE_MKRD is not set +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_NSH_DISABLE_PUT is not set +# CONFIG_NSH_DISABLE_WGET is not set +# CONFIG_NSH_DISABLE_XD is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f103-minimum" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_STM32F103_MINIMUM=y +CONFIG_ARCH_CHIP="stm32f1" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F103C8=y +CONFIG_ARCH_CHIP_STM32F1=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_AUDIO=y +CONFIG_AUDIO_TONE=y +CONFIG_BOARD_LOOPSPERMSEC=5483 +CONFIG_BUILTIN=y +CONFIG_DEFAULT_SMALL=y +CONFIG_DRIVERS_AUDIO=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_LINE_MAX=80 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=1024 +CONFIG_PWM=y +CONFIG_RAM_SIZE=20480 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=192 +CONFIG_SCHED_WAITPID=y +CONFIG_SERIAL_TERMIOS=y +CONFIG_START_DAY=5 +CONFIG_START_MONTH=7 +CONFIG_START_YEAR=2011 +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_JTAG_FULL_ENABLE=y +CONFIG_STM32_ONESHOT=y +CONFIG_STM32_TIM2=y +CONFIG_STM32_TIM2_CH2OUT=y +CONFIG_STM32_TIM2_CHANNEL=2 +CONFIG_STM32_TIM2_PWM=y +CONFIG_STM32_TIM3=y +CONFIG_STM32_USART1=y +CONFIG_SYMTAB_ORDEREDBYNAME=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f1/stm32f103-minimum/configs/buttons/defconfig b/boards/arm/stm32f1/stm32f103-minimum/configs/buttons/defconfig new file mode 100644 index 0000000000000..1909d11c9d45a --- /dev/null +++ b/boards/arm/stm32f1/stm32f103-minimum/configs/buttons/defconfig @@ -0,0 +1,59 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_LEDS is not set +# CONFIG_DISABLE_OS_API is not set +# CONFIG_NSH_DISABLESCRIPT is not set +# CONFIG_NSH_DISABLE_EXEC is not set +# CONFIG_NSH_DISABLE_EXIT is not set +# CONFIG_NSH_DISABLE_GET is not set +# CONFIG_NSH_DISABLE_HEXDUMP is not set +# CONFIG_NSH_DISABLE_MKRD is not set +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_NSH_DISABLE_PUT is not set +# CONFIG_NSH_DISABLE_WGET is not set +# CONFIG_NSH_DISABLE_XD is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f103-minimum" +CONFIG_ARCH_BOARD_STM32F103_MINIMUM=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f1" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F103C8=y +CONFIG_ARCH_CHIP_STM32F1=y +CONFIG_ARCH_IRQBUTTONS=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=5483 +CONFIG_BUILTIN=y +CONFIG_DEFAULT_SMALL=y +CONFIG_EXAMPLES_BUTTONS=y +CONFIG_FILE_STREAM=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INPUT=y +CONFIG_INPUT_BUTTONS=y +CONFIG_INPUT_BUTTONS_LOWER=y +CONFIG_LINE_MAX=80 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=1024 +CONFIG_RAM_SIZE=20480 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=192 +CONFIG_SCHED_WAITPID=y +CONFIG_SERIAL_TERMIOS=y +CONFIG_START_DAY=5 +CONFIG_START_MONTH=7 +CONFIG_START_YEAR=2011 +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_USART1=y +CONFIG_SYMTAB_ORDEREDBYNAME=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f1/stm32f103-minimum/configs/can/defconfig b/boards/arm/stm32f1/stm32f103-minimum/configs/can/defconfig new file mode 100644 index 0000000000000..1ef7b1dec1d77 --- /dev/null +++ b/boards/arm/stm32f1/stm32f103-minimum/configs/can/defconfig @@ -0,0 +1,74 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_DISABLE_OS_API is not set +# CONFIG_NSH_DISABLESCRIPT is not set +# CONFIG_NSH_DISABLE_CAT is not set +# CONFIG_NSH_DISABLE_CD is not set +# CONFIG_NSH_DISABLE_CP is not set +# CONFIG_NSH_DISABLE_ECHO is not set +# CONFIG_NSH_DISABLE_EXEC is not set +# CONFIG_NSH_DISABLE_EXIT is not set +# CONFIG_NSH_DISABLE_FREE is not set +# CONFIG_NSH_DISABLE_GET is not set +# CONFIG_NSH_DISABLE_HEXDUMP is not set +# CONFIG_NSH_DISABLE_LS is not set +# CONFIG_NSH_DISABLE_MKDIR is not set +# CONFIG_NSH_DISABLE_MOUNT is not set +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_NSH_DISABLE_PUT is not set +# CONFIG_NSH_DISABLE_PWD is not set +# CONFIG_NSH_DISABLE_RM is not set +# CONFIG_NSH_DISABLE_SLEEP is not set +# CONFIG_NSH_DISABLE_TEST is not set +# CONFIG_NSH_DISABLE_UMOUNT is not set +# CONFIG_NSH_DISABLE_UNAME is not set +# CONFIG_NSH_DISABLE_WGET is not set +# CONFIG_NSH_DISABLE_XD is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f103-minimum" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_STM32F103_MINIMUM=y +CONFIG_ARCH_CHIP="stm32f1" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F103C8=y +CONFIG_ARCH_CHIP_STM32F1=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=5483 +CONFIG_BUILTIN=y +CONFIG_CAN_ERRORS=y +CONFIG_CAN_EXTID=y +CONFIG_DEFAULT_SMALL=y +CONFIG_EXAMPLES_CAN=y +CONFIG_EXAMPLES_CAN_NMSGS=4 +CONFIG_EXAMPLES_CAN_WRITE=y +CONFIG_HOST_MACOS=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_LINE_MAX=80 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=1024 +CONFIG_RAM_SIZE=20480 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=192 +CONFIG_SCHED_WAITPID=y +CONFIG_SERIAL_TERMIOS=y +CONFIG_START_DAY=5 +CONFIG_START_MONTH=7 +CONFIG_START_YEAR=2011 +CONFIG_STM32_CAN1=y +CONFIG_STM32_CAN_TSEG1=13 +CONFIG_STM32_CAN_TSEG2=2 +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_JTAG_FULL_ENABLE=y +CONFIG_STM32_USART1=y +CONFIG_SYMTAB_ORDEREDBYNAME=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f1/stm32f103-minimum/configs/hello/defconfig b/boards/arm/stm32f1/stm32f103-minimum/configs/hello/defconfig new file mode 100644 index 0000000000000..175e2d56fbca7 --- /dev/null +++ b/boards/arm/stm32f1/stm32f103-minimum/configs/hello/defconfig @@ -0,0 +1,51 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_LEDS is not set +# CONFIG_NSH_DISABLEBG is not set +# CONFIG_NSH_DISABLE_DF is not set +# CONFIG_NSH_DISABLE_EXEC is not set +# CONFIG_NSH_DISABLE_EXIT is not set +# CONFIG_NSH_DISABLE_GET is not set +# CONFIG_NSH_DISABLE_HEXDUMP is not set +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_NSH_DISABLE_XD is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f103-minimum" +CONFIG_ARCH_BOARD_STM32F103_MINIMUM=y +CONFIG_ARCH_CHIP="stm32f1" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F103C8=y +CONFIG_ARCH_CHIP_STM32F1=y +CONFIG_BOARD_LOOPSPERMSEC=5483 +CONFIG_DEFAULT_SMALL=y +CONFIG_DISABLE_MOUNTPOINT=y +CONFIG_EXAMPLES_HELLO=y +CONFIG_FDCLONE_STDIO=y +CONFIG_INIT_ENTRYPOINT="hello_main" +CONFIG_INIT_STACKSIZE=1536 +CONFIG_LINE_MAX=80 +CONFIG_MM_SMALL=y +CONFIG_NSH_FILEIOSIZE=64 +CONFIG_NUNGET_CHARS=0 +CONFIG_POSIX_SPAWN_DEFAULT_STACKSIZE=1536 +CONFIG_PTHREAD_STACK_DEFAULT=1536 +CONFIG_RAM_SIZE=20480 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SERIAL_TERMIOS=y +CONFIG_START_DAY=5 +CONFIG_START_MONTH=7 +CONFIG_START_YEAR=2011 +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_JTAG_FULL_ENABLE=y +CONFIG_STM32_NOEXT_VECTORS=y +CONFIG_STM32_USART1=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f1/stm32f103-minimum/configs/jlx12864g/defconfig b/boards/arm/stm32f1/stm32f103-minimum/configs/jlx12864g/defconfig new file mode 100644 index 0000000000000..abeabb55778c9 --- /dev/null +++ b/boards/arm/stm32f1/stm32f103-minimum/configs/jlx12864g/defconfig @@ -0,0 +1,66 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_DISABLE_OS_API is not set +# CONFIG_NSH_DISABLESCRIPT is not set +# CONFIG_NSH_DISABLE_EXEC is not set +# CONFIG_NSH_DISABLE_EXIT is not set +# CONFIG_NSH_DISABLE_GET is not set +# CONFIG_NSH_DISABLE_HEXDUMP is not set +# CONFIG_NSH_DISABLE_MKRD is not set +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_NSH_DISABLE_PUT is not set +# CONFIG_NSH_DISABLE_WGET is not set +# CONFIG_NSH_DISABLE_XD is not set +# CONFIG_NX_DISABLE_1BPP is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f103-minimum" +CONFIG_ARCH_BOARD_STM32F103_MINIMUM=y +CONFIG_ARCH_CHIP="stm32f1" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F103C8=y +CONFIG_ARCH_CHIP_STM32F1=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=5483 +CONFIG_BUILTIN=y +CONFIG_DEFAULT_SMALL=y +CONFIG_EXAMPLES_NXHELLO=y +CONFIG_EXAMPLES_NXHELLO_BPP=1 +CONFIG_EXAMPLES_NXHELLO_LISTENER_STACKSIZE=1536 +CONFIG_EXAMPLES_NXHELLO_STACKSIZE=1536 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_LCD=y +CONFIG_LCD_ST7567=y +CONFIG_LINE_MAX=80 +CONFIG_MQ_MAXMSGSIZE=64 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=1024 +CONFIG_NX=y +CONFIG_NXFONT_MONO5X8=y +CONFIG_NXTK_BORDERWIDTH=1 +CONFIG_NX_BLOCKING=y +CONFIG_NX_WRITEONLY=y +CONFIG_RAM_SIZE=20480 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=192 +CONFIG_SCHED_WAITPID=y +CONFIG_SERIAL_TERMIOS=y +CONFIG_SPI_CMDDATA=y +CONFIG_START_DAY=5 +CONFIG_START_MONTH=7 +CONFIG_START_YEAR=2011 +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_JTAG_FULL_ENABLE=y +CONFIG_STM32_SPI1=y +CONFIG_STM32_USART1=y +CONFIG_SYMTAB_ORDEREDBYNAME=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f1/stm32f103-minimum/configs/lcd1602/defconfig b/boards/arm/stm32f1/stm32f103-minimum/configs/lcd1602/defconfig new file mode 100644 index 0000000000000..d9b48e9bb91a7 --- /dev/null +++ b/boards/arm/stm32f1/stm32f103-minimum/configs/lcd1602/defconfig @@ -0,0 +1,63 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_DISABLE_OS_API is not set +# CONFIG_NSH_DISABLESCRIPT is not set +# CONFIG_NSH_DISABLE_EXEC is not set +# CONFIG_NSH_DISABLE_EXIT is not set +# CONFIG_NSH_DISABLE_GET is not set +# CONFIG_NSH_DISABLE_HEXDUMP is not set +# CONFIG_NSH_DISABLE_MKRD is not set +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_NSH_DISABLE_PUT is not set +# CONFIG_NSH_DISABLE_WGET is not set +# CONFIG_NSH_DISABLE_XD is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f103-minimum" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_STM32F103_MINIMUM=y +CONFIG_ARCH_CHIP="stm32f1" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F103C8=y +CONFIG_ARCH_CHIP_STM32F1=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=5483 +CONFIG_BUILTIN=y +CONFIG_DEFAULT_SMALL=y +CONFIG_EXAMPLES_SLCD=y +CONFIG_FILE_STREAM=y +CONFIG_I2C=y +CONFIG_I2CTOOL_DEFFREQ=100000 +CONFIG_I2CTOOL_MAXBUS=1 +CONFIG_I2CTOOL_MINBUS=1 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_LCD_BACKPACK=y +CONFIG_LCD_LCD1602=y +CONFIG_LINE_MAX=80 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=1024 +CONFIG_RAM_SIZE=20480 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=192 +CONFIG_SCHED_WAITPID=y +CONFIG_SERIAL_TERMIOS=y +CONFIG_SLCD=y +CONFIG_START_DAY=5 +CONFIG_START_MONTH=7 +CONFIG_START_YEAR=2011 +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_I2C1=y +CONFIG_STM32_JTAG_FULL_ENABLE=y +CONFIG_STM32_USART1=y +CONFIG_SYMTAB_ORDEREDBYNAME=y +CONFIG_SYSTEM_I2CTOOL=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f1/stm32f103-minimum/configs/mcp2515/defconfig b/boards/arm/stm32f1/stm32f103-minimum/configs/mcp2515/defconfig new file mode 100644 index 0000000000000..f86c33c470acb --- /dev/null +++ b/boards/arm/stm32f1/stm32f103-minimum/configs/mcp2515/defconfig @@ -0,0 +1,60 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_DISABLE_OS_API is not set +# CONFIG_NSH_DISABLESCRIPT is not set +# CONFIG_NSH_DISABLE_EXEC is not set +# CONFIG_NSH_DISABLE_EXIT is not set +# CONFIG_NSH_DISABLE_GET is not set +# CONFIG_NSH_DISABLE_HEXDUMP is not set +# CONFIG_NSH_DISABLE_MKRD is not set +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_NSH_DISABLE_PUT is not set +# CONFIG_NSH_DISABLE_WGET is not set +# CONFIG_NSH_DISABLE_XD is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f103-minimum" +CONFIG_ARCH_BOARD_STM32F103_MINIMUM=y +CONFIG_ARCH_CHIP="stm32f1" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F103C8=y +CONFIG_ARCH_CHIP_STM32F1=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=5483 +CONFIG_BUILTIN=y +CONFIG_CAN=y +CONFIG_CANUTILS_CANLIB=y +CONFIG_CAN_MCP2515=y +CONFIG_CAN_TXREADY=y +CONFIG_DEFAULT_SMALL=y +CONFIG_EXAMPLES_CAN=y +CONFIG_EXAMPLES_CAN_READ=y +CONFIG_FILE_STREAM=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_LINE_MAX=80 +CONFIG_MCP2515_PHASESEG1=3 +CONFIG_MCP2515_PROPSEG=1 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=1024 +CONFIG_RAM_SIZE=20480 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORKPRIORITY=192 +CONFIG_SCHED_WAITPID=y +CONFIG_SERIAL_TERMIOS=y +CONFIG_START_DAY=5 +CONFIG_START_MONTH=7 +CONFIG_START_YEAR=2011 +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_JTAG_FULL_ENABLE=y +CONFIG_STM32_SPI1=y +CONFIG_STM32_USART1=y +CONFIG_SYMTAB_ORDEREDBYNAME=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f1/stm32f103-minimum/configs/nrf24/defconfig b/boards/arm/stm32f1/stm32f103-minimum/configs/nrf24/defconfig new file mode 100644 index 0000000000000..9c543b8150d49 --- /dev/null +++ b/boards/arm/stm32f1/stm32f103-minimum/configs/nrf24/defconfig @@ -0,0 +1,57 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_DISABLE_OS_API is not set +# CONFIG_NSH_DISABLESCRIPT is not set +# CONFIG_NSH_DISABLE_EXEC is not set +# CONFIG_NSH_DISABLE_EXIT is not set +# CONFIG_NSH_DISABLE_GET is not set +# CONFIG_NSH_DISABLE_HEXDUMP is not set +# CONFIG_NSH_DISABLE_MKRD is not set +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_NSH_DISABLE_PUT is not set +# CONFIG_NSH_DISABLE_WGET is not set +# CONFIG_NSH_DISABLE_XD is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f103-minimum" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_STM32F103_MINIMUM=y +CONFIG_ARCH_CHIP="stm32f1" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F103C8=y +CONFIG_ARCH_CHIP_STM32F1=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=5483 +CONFIG_BUILTIN=y +CONFIG_DEFAULT_SMALL=y +CONFIG_DRIVERS_WIRELESS=y +CONFIG_EXAMPLES_NRF24L01TERM=y +CONFIG_FILE_STREAM=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_LINE_MAX=80 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=1024 +CONFIG_RAM_SIZE=20480 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=192 +CONFIG_SCHED_WAITPID=y +CONFIG_SERIAL_TERMIOS=y +CONFIG_START_DAY=5 +CONFIG_START_MONTH=7 +CONFIG_START_YEAR=2011 +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_JTAG_FULL_ENABLE=y +CONFIG_STM32_SPI1=y +CONFIG_STM32_USART1=y +CONFIG_SYMTAB_ORDEREDBYNAME=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART1_SERIAL_CONSOLE=y +CONFIG_WL_NRF24L01=y diff --git a/boards/arm/stm32f1/stm32f103-minimum/configs/nsh/defconfig b/boards/arm/stm32f1/stm32f103-minimum/configs/nsh/defconfig new file mode 100644 index 0000000000000..17c41e7e90488 --- /dev/null +++ b/boards/arm/stm32f1/stm32f103-minimum/configs/nsh/defconfig @@ -0,0 +1,65 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_DISABLE_OS_API is not set +# CONFIG_NSH_DISABLESCRIPT is not set +# CONFIG_NSH_DISABLE_CAT is not set +# CONFIG_NSH_DISABLE_CD is not set +# CONFIG_NSH_DISABLE_CP is not set +# CONFIG_NSH_DISABLE_ECHO is not set +# CONFIG_NSH_DISABLE_EXEC is not set +# CONFIG_NSH_DISABLE_EXIT is not set +# CONFIG_NSH_DISABLE_FREE is not set +# CONFIG_NSH_DISABLE_GET is not set +# CONFIG_NSH_DISABLE_HEXDUMP is not set +# CONFIG_NSH_DISABLE_LS is not set +# CONFIG_NSH_DISABLE_MKDIR is not set +# CONFIG_NSH_DISABLE_MOUNT is not set +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_NSH_DISABLE_PUT is not set +# CONFIG_NSH_DISABLE_PWD is not set +# CONFIG_NSH_DISABLE_RM is not set +# CONFIG_NSH_DISABLE_SLEEP is not set +# CONFIG_NSH_DISABLE_TEST is not set +# CONFIG_NSH_DISABLE_UMOUNT is not set +# CONFIG_NSH_DISABLE_UNAME is not set +# CONFIG_NSH_DISABLE_WGET is not set +# CONFIG_NSH_DISABLE_XD is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f103-minimum" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_STM32F103_MINIMUM=y +CONFIG_ARCH_CHIP="stm32f1" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F103C8=y +CONFIG_ARCH_CHIP_STM32F1=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=5483 +CONFIG_BUILTIN=y +CONFIG_DEFAULT_SMALL=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_LINE_MAX=80 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=1024 +CONFIG_RAM_SIZE=20480 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=192 +CONFIG_SCHED_WAITPID=y +CONFIG_SERIAL_TERMIOS=y +CONFIG_START_DAY=5 +CONFIG_START_MONTH=7 +CONFIG_START_YEAR=2011 +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_JTAG_FULL_ENABLE=y +CONFIG_STM32_USART1=y +CONFIG_SYMTAB_ORDEREDBYNAME=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f1/stm32f103-minimum/configs/pwm/defconfig b/boards/arm/stm32f1/stm32f103-minimum/configs/pwm/defconfig new file mode 100644 index 0000000000000..36708cff5947c --- /dev/null +++ b/boards/arm/stm32f1/stm32f103-minimum/configs/pwm/defconfig @@ -0,0 +1,58 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_DISABLE_OS_API is not set +# CONFIG_NSH_DISABLESCRIPT is not set +# CONFIG_NSH_DISABLE_EXEC is not set +# CONFIG_NSH_DISABLE_EXIT is not set +# CONFIG_NSH_DISABLE_GET is not set +# CONFIG_NSH_DISABLE_HEXDUMP is not set +# CONFIG_NSH_DISABLE_MKRD is not set +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_NSH_DISABLE_PUT is not set +# CONFIG_NSH_DISABLE_WGET is not set +# CONFIG_NSH_DISABLE_XD is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f103-minimum" +CONFIG_ARCH_BOARD_STM32F103_MINIMUM=y +CONFIG_ARCH_CHIP="stm32f1" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F103C8=y +CONFIG_ARCH_CHIP_STM32F1=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=5483 +CONFIG_BUILTIN=y +CONFIG_DEFAULT_SMALL=y +CONFIG_EXAMPLES_PWM=y +CONFIG_FILE_STREAM=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_LINE_MAX=80 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=1024 +CONFIG_PWM=y +CONFIG_RAM_SIZE=20480 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=192 +CONFIG_SCHED_WAITPID=y +CONFIG_SERIAL_TERMIOS=y +CONFIG_START_DAY=5 +CONFIG_START_MONTH=7 +CONFIG_START_YEAR=2011 +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_JTAG_FULL_ENABLE=y +CONFIG_STM32_TIM3=y +CONFIG_STM32_TIM3_CH3OUT=y +CONFIG_STM32_TIM3_CHANNEL=3 +CONFIG_STM32_TIM3_PWM=y +CONFIG_STM32_USART1=y +CONFIG_SYMTAB_ORDEREDBYNAME=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f1/stm32f103-minimum/configs/rfid-rc522/defconfig b/boards/arm/stm32f1/stm32f103-minimum/configs/rfid-rc522/defconfig new file mode 100644 index 0000000000000..8a19f92058947 --- /dev/null +++ b/boards/arm/stm32f1/stm32f103-minimum/configs/rfid-rc522/defconfig @@ -0,0 +1,56 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_DISABLE_OS_API is not set +# CONFIG_NSH_DISABLESCRIPT is not set +# CONFIG_NSH_DISABLE_EXEC is not set +# CONFIG_NSH_DISABLE_EXIT is not set +# CONFIG_NSH_DISABLE_GET is not set +# CONFIG_NSH_DISABLE_HEXDUMP is not set +# CONFIG_NSH_DISABLE_MKRD is not set +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_NSH_DISABLE_PUT is not set +# CONFIG_NSH_DISABLE_WGET is not set +# CONFIG_NSH_DISABLE_XD is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f103-minimum" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_STM32F103_MINIMUM=y +CONFIG_ARCH_CHIP="stm32f1" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F103C8=y +CONFIG_ARCH_CHIP_STM32F1=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=5483 +CONFIG_BUILTIN=y +CONFIG_CL_MFRC522=y +CONFIG_DEFAULT_SMALL=y +CONFIG_DRIVERS_CONTACTLESS=y +CONFIG_EXAMPLES_RFID_READUID=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_LINE_MAX=80 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=1024 +CONFIG_RAM_SIZE=20480 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=192 +CONFIG_SCHED_WAITPID=y +CONFIG_SERIAL_TERMIOS=y +CONFIG_START_DAY=5 +CONFIG_START_MONTH=7 +CONFIG_START_YEAR=2011 +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_JTAG_FULL_ENABLE=y +CONFIG_STM32_SPI1=y +CONFIG_STM32_USART1=y +CONFIG_SYMTAB_ORDEREDBYNAME=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f1/stm32f103-minimum/configs/rgbled/defconfig b/boards/arm/stm32f1/stm32f103-minimum/configs/rgbled/defconfig new file mode 100644 index 0000000000000..f13a149685258 --- /dev/null +++ b/boards/arm/stm32f1/stm32f103-minimum/configs/rgbled/defconfig @@ -0,0 +1,70 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_DISABLE_OS_API is not set +# CONFIG_NSH_DISABLESCRIPT is not set +# CONFIG_NSH_DISABLE_EXEC is not set +# CONFIG_NSH_DISABLE_EXIT is not set +# CONFIG_NSH_DISABLE_GET is not set +# CONFIG_NSH_DISABLE_HEXDUMP is not set +# CONFIG_NSH_DISABLE_MKRD is not set +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_NSH_DISABLE_PUT is not set +# CONFIG_NSH_DISABLE_WGET is not set +# CONFIG_NSH_DISABLE_XD is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f103-minimum" +CONFIG_ARCH_BOARD_STM32F103_MINIMUM=y +CONFIG_ARCH_CHIP="stm32f1" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F103C8=y +CONFIG_ARCH_CHIP_STM32F1=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=5483 +CONFIG_BUILTIN=y +CONFIG_DEFAULT_SMALL=y +CONFIG_EXAMPLES_RGBLED=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_LINE_MAX=80 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=1024 +CONFIG_PWM=y +CONFIG_PWM_NCHANNELS=3 +CONFIG_RAM_SIZE=20480 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RGBLED=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=192 +CONFIG_SCHED_WAITPID=y +CONFIG_SERIAL_TERMIOS=y +CONFIG_START_DAY=5 +CONFIG_START_MONTH=7 +CONFIG_START_YEAR=2011 +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_JTAG_FULL_ENABLE=y +CONFIG_STM32_TIM1=y +CONFIG_STM32_TIM1_CH1OUT=y +CONFIG_STM32_TIM1_PWM=y +CONFIG_STM32_TIM2=y +CONFIG_STM32_TIM2_CH2OUT=y +CONFIG_STM32_TIM2_CHANNEL=2 +CONFIG_STM32_TIM2_PWM=y +CONFIG_STM32_TIM3=y +CONFIG_STM32_TIM3_CH3OUT=y +CONFIG_STM32_TIM3_CHANNEL=3 +CONFIG_STM32_TIM3_PWM=y +CONFIG_STM32_TIM4=y +CONFIG_STM32_TIM4_CH4OUT=y +CONFIG_STM32_TIM4_CHANNEL=4 +CONFIG_STM32_TIM4_PWM=y +CONFIG_STM32_USART1=y +CONFIG_SYMTAB_ORDEREDBYNAME=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f1/stm32f103-minimum/configs/sensors/defconfig b/boards/arm/stm32f1/stm32f103-minimum/configs/sensors/defconfig new file mode 100644 index 0000000000000..ded90e2212abe --- /dev/null +++ b/boards/arm/stm32f1/stm32f103-minimum/configs/sensors/defconfig @@ -0,0 +1,70 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_DEV_CONSOLE is not set +# CONFIG_DISABLE_OS_API is not set +# CONFIG_NSH_DISABLEBG is not set +# CONFIG_NSH_DISABLESCRIPT is not set +# CONFIG_NSH_DISABLE_EXEC is not set +# CONFIG_NSH_DISABLE_EXIT is not set +# CONFIG_NSH_DISABLE_MB is not set +# CONFIG_NSH_DISABLE_MH is not set +# CONFIG_NSH_DISABLE_MW is not set +# CONFIG_NSH_DISABLE_PS is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f103-minimum" +CONFIG_ARCH_BOARD_STM32F103_MINIMUM=y +CONFIG_ARCH_CHIP="stm32f1" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F103C8=y +CONFIG_ARCH_CHIP_STM32F1=y +CONFIG_BOARDCTL=y +CONFIG_BOARDCTL_USBDEVCTRL=y +CONFIG_BOARD_LOOPSPERMSEC=5483 +CONFIG_BUILTIN=y +CONFIG_CDCACM=y +CONFIG_CDCACM_CONSOLE=y +CONFIG_CDCACM_RXBUFSIZE=256 +CONFIG_CDCACM_TXBUFSIZE=256 +CONFIG_DEFAULT_SMALL=y +CONFIG_ENABLE_ALL_SIGNALS=y +CONFIG_I2C=y +CONFIG_I2C_DRIVER=y +CONFIG_I2C_RESET=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_LIBC_FLOATINGPOINT=y +CONFIG_LIBM_TOOLCHAIN=y +CONFIG_LINE_MAX=80 +CONFIG_LTO_FULL=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=1024 +CONFIG_RAM_SIZE=20480 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_SENSORS=y +CONFIG_SENSORS_DS18B20=y +CONFIG_SENSORS_DS18B20_POLL=y +CONFIG_SENSORS_HYT271=y +CONFIG_SENSORS_HYT271_POLL=y +CONFIG_SERIAL_TERMIOS=y +CONFIG_START_DAY=5 +CONFIG_START_MONTH=7 +CONFIG_START_YEAR=2011 +CONFIG_STM32_I2C2=y +CONFIG_STM32_JTAG_FULL_ENABLE=y +CONFIG_STM32_TIM1=y +CONFIG_STM32_TIM2=y +CONFIG_STM32_USART1=y +CONFIG_STM32_USART2=y +CONFIG_STM32_USART2_1WIREDRIVER=y +CONFIG_STM32_USART_SINGLEWIRE=y +CONFIG_STM32_USB=y +CONFIG_SYSTEM_NSH=y +CONFIG_SYSTEM_SENSORTEST=y +CONFIG_TASK_NAME_SIZE=0 diff --git a/boards/arm/stm32f1/stm32f103-minimum/configs/ssd1306/defconfig b/boards/arm/stm32f1/stm32f103-minimum/configs/ssd1306/defconfig new file mode 100644 index 0000000000000..88c42001647ae --- /dev/null +++ b/boards/arm/stm32f1/stm32f103-minimum/configs/ssd1306/defconfig @@ -0,0 +1,74 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_DISABLE_OS_API is not set +# CONFIG_NSH_DISABLESCRIPT is not set +# CONFIG_NSH_DISABLE_CAT is not set +# CONFIG_NSH_DISABLE_CD is not set +# CONFIG_NSH_DISABLE_CP is not set +# CONFIG_NSH_DISABLE_ECHO is not set +# CONFIG_NSH_DISABLE_EXEC is not set +# CONFIG_NSH_DISABLE_EXIT is not set +# CONFIG_NSH_DISABLE_FREE is not set +# CONFIG_NSH_DISABLE_GET is not set +# CONFIG_NSH_DISABLE_HEXDUMP is not set +# CONFIG_NSH_DISABLE_LS is not set +# CONFIG_NSH_DISABLE_MKDIR is not set +# CONFIG_NSH_DISABLE_MOUNT is not set +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_NSH_DISABLE_PUT is not set +# CONFIG_NSH_DISABLE_PWD is not set +# CONFIG_NSH_DISABLE_RM is not set +# CONFIG_NSH_DISABLE_SLEEP is not set +# CONFIG_NSH_DISABLE_TEST is not set +# CONFIG_NSH_DISABLE_UMOUNT is not set +# CONFIG_NSH_DISABLE_UNAME is not set +# CONFIG_NSH_DISABLE_WGET is not set +# CONFIG_NSH_DISABLE_XD is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f103-minimum" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_STM32F103_MINIMUM=y +CONFIG_ARCH_CHIP="stm32f1" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F103C8=y +CONFIG_ARCH_CHIP_STM32F1=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=5483 +CONFIG_BUILTIN=y +CONFIG_DEFAULT_SMALL=y +CONFIG_DRIVERS_VIDEO=y +CONFIG_EXAMPLES_FB=y +CONFIG_FILE_STREAM=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_LCD=y +CONFIG_LCD_FRAMEBUFFER=y +CONFIG_LCD_SSD1306_I2C=y +CONFIG_LCD_UG2864HSWEG01=y +CONFIG_LINE_MAX=80 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=1024 +CONFIG_RAM_SIZE=20480 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=192 +CONFIG_SCHED_WAITPID=y +CONFIG_SERIAL_TERMIOS=y +CONFIG_START_DAY=5 +CONFIG_START_MONTH=7 +CONFIG_START_YEAR=2011 +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_I2C1=y +CONFIG_STM32_JTAG_FULL_ENABLE=y +CONFIG_STM32_USART1=y +CONFIG_SYMTAB_ORDEREDBYNAME=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART1_SERIAL_CONSOLE=y +CONFIG_VIDEO_FB=y diff --git a/boards/arm/stm32f1/stm32f103-minimum/configs/usbnsh/defconfig b/boards/arm/stm32f1/stm32f103-minimum/configs/usbnsh/defconfig new file mode 100644 index 0000000000000..0f71cd1624691 --- /dev/null +++ b/boards/arm/stm32f1/stm32f103-minimum/configs/usbnsh/defconfig @@ -0,0 +1,56 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_DEV_CONSOLE is not set +# CONFIG_DISABLE_OS_API is not set +# CONFIG_NSH_DISABLEBG is not set +# CONFIG_NSH_DISABLESCRIPT is not set +# CONFIG_NSH_DISABLE_EXEC is not set +# CONFIG_NSH_DISABLE_EXIT is not set +# CONFIG_NSH_DISABLE_GET is not set +# CONFIG_NSH_DISABLE_HEXDUMP is not set +# CONFIG_NSH_DISABLE_MKRD is not set +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_NSH_DISABLE_PUT is not set +# CONFIG_NSH_DISABLE_WGET is not set +# CONFIG_NSH_DISABLE_XD is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f103-minimum" +CONFIG_ARCH_BOARD_STM32F103_MINIMUM=y +CONFIG_ARCH_CHIP="stm32f1" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F103C8=y +CONFIG_ARCH_CHIP_STM32F1=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL_USBDEVCTRL=y +CONFIG_BOARD_LOOPSPERMSEC=5483 +CONFIG_BUILTIN=y +CONFIG_CDCACM=y +CONFIG_CDCACM_CONSOLE=y +CONFIG_CDCACM_RXBUFSIZE=256 +CONFIG_CDCACM_TXBUFSIZE=256 +CONFIG_DEFAULT_SMALL=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_LINE_MAX=80 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=1024 +CONFIG_RAM_SIZE=20480 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=5 +CONFIG_START_MONTH=7 +CONFIG_START_YEAR=2011 +CONFIG_STM32_JTAG_FULL_ENABLE=y +CONFIG_STM32_USART1=y +CONFIG_STM32_USB=y +CONFIG_SYMTAB_ORDEREDBYNAME=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USBDEV_TRACE=y +CONFIG_USBDEV_TRACE_NRECORDS=32 diff --git a/boards/arm/stm32f1/stm32f103-minimum/configs/userled/defconfig b/boards/arm/stm32f1/stm32f103-minimum/configs/userled/defconfig new file mode 100644 index 0000000000000..a1bd26f706dff --- /dev/null +++ b/boards/arm/stm32f1/stm32f103-minimum/configs/userled/defconfig @@ -0,0 +1,57 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_LEDS is not set +# CONFIG_DISABLE_OS_API is not set +# CONFIG_NSH_DISABLESCRIPT is not set +# CONFIG_NSH_DISABLE_EXEC is not set +# CONFIG_NSH_DISABLE_EXIT is not set +# CONFIG_NSH_DISABLE_GET is not set +# CONFIG_NSH_DISABLE_HEXDUMP is not set +# CONFIG_NSH_DISABLE_MKRD is not set +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_NSH_DISABLE_PUT is not set +# CONFIG_NSH_DISABLE_WGET is not set +# CONFIG_NSH_DISABLE_XD is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f103-minimum" +CONFIG_ARCH_BOARD_STM32F103_MINIMUM=y +CONFIG_ARCH_CHIP="stm32f1" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F103C8=y +CONFIG_ARCH_CHIP_STM32F1=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=5483 +CONFIG_BUILTIN=y +CONFIG_DEFAULT_SMALL=y +CONFIG_ENABLE_ALL_SIGNALS=y +CONFIG_EXAMPLES_LEDS=y +CONFIG_FILE_STREAM=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_LINE_MAX=80 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=1024 +CONFIG_RAM_SIZE=20480 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=192 +CONFIG_SCHED_WAITPID=y +CONFIG_SERIAL_TERMIOS=y +CONFIG_START_DAY=5 +CONFIG_START_MONTH=7 +CONFIG_START_YEAR=2011 +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_USART1=y +CONFIG_SYMTAB_ORDEREDBYNAME=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART1_SERIAL_CONSOLE=y +CONFIG_USERLED=y +CONFIG_USERLED_LOWER=y diff --git a/boards/arm/stm32f1/stm32f103-minimum/configs/veml6070/defconfig b/boards/arm/stm32f1/stm32f103-minimum/configs/veml6070/defconfig new file mode 100644 index 0000000000000..79db5a7a98fe7 --- /dev/null +++ b/boards/arm/stm32f1/stm32f103-minimum/configs/veml6070/defconfig @@ -0,0 +1,55 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_DISABLE_OS_API is not set +# CONFIG_NSH_DISABLESCRIPT is not set +# CONFIG_NSH_DISABLE_EXEC is not set +# CONFIG_NSH_DISABLE_EXIT is not set +# CONFIG_NSH_DISABLE_GET is not set +# CONFIG_NSH_DISABLE_HEXDUMP is not set +# CONFIG_NSH_DISABLE_MKRD is not set +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_NSH_DISABLE_PUT is not set +# CONFIG_NSH_DISABLE_WGET is not set +# CONFIG_NSH_DISABLE_XD is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f103-minimum" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_STM32F103_MINIMUM=y +CONFIG_ARCH_CHIP="stm32f1" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F103C8=y +CONFIG_ARCH_CHIP_STM32F1=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=5483 +CONFIG_BUILTIN=y +CONFIG_DEFAULT_SMALL=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_LINE_MAX=80 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=1024 +CONFIG_RAM_SIZE=20480 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=192 +CONFIG_SCHED_WAITPID=y +CONFIG_SENSORS=y +CONFIG_SENSORS_VEML6070=y +CONFIG_SERIAL_TERMIOS=y +CONFIG_START_DAY=5 +CONFIG_START_MONTH=7 +CONFIG_START_YEAR=2011 +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_I2C1=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_USART1=y +CONFIG_SYMTAB_ORDEREDBYNAME=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f1/stm32f103-minimum/include/board.h b/boards/arm/stm32f1/stm32f103-minimum/include/board.h new file mode 100644 index 0000000000000..52c125f7cc8c1 --- /dev/null +++ b/boards/arm/stm32f1/stm32f103-minimum/include/board.h @@ -0,0 +1,321 @@ +/**************************************************************************** + * boards/arm/stm32f1/stm32f103-minimum/include/board.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_STM32_STM32F103_MINIMUM_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32_STM32F103_MINIMUM_INCLUDE_BOARD_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#ifndef __ASSEMBLY__ +# include +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Clocking *****************************************************************/ + +/* On-board crystal frequency is 8MHz (HSE) */ + +#define STM32_BOARD_XTAL 8000000ul + +/* PLL source is HSE/1, PLL multiplier is 9: PLL frequency is + * 8MHz (XTAL) x 9 = 72MHz + */ + +#define STM32_CFGR_PLLSRC RCC_CFGR_PLLSRC +#define STM32_CFGR_PLLXTPRE 0 +#define STM32_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx9 +#define STM32_PLL_FREQUENCY (9*STM32_BOARD_XTAL) + +/* Use the PLL and set the SYSCLK source to be the PLL */ + +#define STM32_SYSCLK_SW RCC_CFGR_SW_PLL +#define STM32_SYSCLK_SWS RCC_CFGR_SWS_PLL +#define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY + +/* AHB clock (HCLK) is SYSCLK (72MHz) */ + +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK +#define STM32_HCLK_FREQUENCY STM32_PLL_FREQUENCY + +/* APB2 clock (PCLK2) is HCLK (72MHz) */ + +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK +#define STM32_PCLK2_FREQUENCY STM32_HCLK_FREQUENCY + +/* APB2 timers 1 and 8 will receive PCLK2. */ + +#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) + +/* APB1 clock (PCLK1) is HCLK/2 (36MHz) */ + +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd2 +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/2) + +/* APB1 timers 2-7 will be twice PCLK1 */ + +#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) + +/* USB divider -- Divide PLL clock by 1.5 */ + +#define STM32_CFGR_USBPRE 0 + +/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx + * otherwise frequency is 2xAPBx. + * Note: TIM1,8 are on APB2, others on APB1 + */ + +#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM2_FREQUENCY STM32_PCLK1_FREQUENCY +#define BOARD_TIM3_FREQUENCY STM32_PCLK1_FREQUENCY +#define BOARD_TIM4_FREQUENCY STM32_PCLK1_FREQUENCY +#define BOARD_TIM5_FREQUENCY STM32_PCLK1_FREQUENCY +#define BOARD_TIM6_FREQUENCY STM32_PCLK1_FREQUENCY +#define BOARD_TIM7_FREQUENCY STM32_PCLK1_FREQUENCY +#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY + +/* SDIO dividers. Note that slower clocking is required when DMA is disabled + * in order to avoid RX overrun/TX underrun errors due to delayed responses + * to service FIFOs in interrupt driven mode. These values have not been + * tuned!!! + * + * HCLK=72MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(178+2)=400 KHz + */ + +#define SDIO_INIT_CLKDIV (178 << SDIO_CLKCR_CLKDIV_SHIFT) + +/* DMA ON: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(2+2)=18 MHz + * DMA OFF: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(3+2)=14.4 MHz + */ + +#ifdef CONFIG_SDIO_DMA +# define SDIO_MMCXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT) +#else +# define SDIO_MMCXFR_CLKDIV (3 << SDIO_CLKCR_CLKDIV_SHIFT) +#endif + +/* DMA ON: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(1+2)=24 MHz + * DMA OFF: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(3+2)=14.4 MHz + */ + +#ifdef CONFIG_SDIO_DMA +# define SDIO_SDXFR_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT) +#else +# define SDIO_SDXFR_CLKDIV (3 << SDIO_CLKCR_CLKDIV_SHIFT) +#endif + +/* BUTTON definitions *******************************************************/ + +#define NUM_BUTTONS 2 + +#define BUTTON_USER1 0 +#define BUTTON_USER2 1 +#define BUTTON_USER1_BIT (1 << BUTTON_USER1) +#define BUTTON_USER2_BIT (1 << BUTTON_USER2) + +/* LED definitions **********************************************************/ + +/* Define how many LEDs this board has (needed by userleds) */ + +#define BOARD_NLEDS 1 + +/* The board has only one controllable LED */ + +#define LED_STARTED 0 /* No LEDs */ +#define LED_HEAPALLOCATE 1 /* LED1 on */ +#define LED_IRQSENABLED 2 /* LED2 on */ +#define LED_STACKCREATED 3 /* LED1 on */ +#define LED_INIRQ 4 /* LED1 off */ +#define LED_SIGNAL 5 /* LED2 on */ +#define LED_ASSERTION 6 /* LED1 + LED2 */ +#define LED_PANIC 7 /* LED1 / LED2 blinking */ + +/* PWM + * + * The STM32F103-Minimum has no real on-board PWM devices, but the board can + * be configured to output a pulse train using TIM3 CH3 on PB0. + * + * Note: we don't need redefine GPIO_TIM3_CH3OUT because PB0 is not + * remap pin. + */ + +/* RGB LED + * + * R = TIM1 CH1 on PA8 | G = TIM2 CH2 on PA1 | B = TIM4 CH4 on PB9 + * + * Note: Pin boards: GPIO_TIM1_CH1OUT ; GPIO_TIM2_CH2OUT ; GPIO_TIM4_CH4OUT + */ + +#define RGBLED_RPWMTIMER 1 +#define RGBLED_RPWMCHANNEL 1 +#define RGBLED_GPWMTIMER 2 +#define RGBLED_GPWMCHANNEL 2 +#define RGBLED_BPWMTIMER 4 +#define RGBLED_BPWMCHANNEL 4 + +/* Tone Driver **************************************************************/ + +#define BOARD_TONE_PWM_TIM 2 /* PWM timer for tone generation */ +#define BOARD_TONE_PWM_CHANNEL 2 /* PWM channel for tone generation */ +#define BOARD_TONE_ONESHOT_TIM 3 /* Oneshot timer for note timings */ +#define BOARD_TONE_ONESHOT_TIM_RES 10 /* Oneshot timer resolution (us) */ + +/* NRF24L01 Driver **********************************************************/ + +/* Chip enable: PB.1 */ + +#define GPIO_NRF24L01_CE (GPIO_OUTPUT|GPIO_CNF_OUTPP|GPIO_MODE_50MHz|\ + GPIO_OUTPUT_CLEAR|GPIO_PORTB|GPIO_PIN1) + +/* IRQ line: PA.0 */ + +#define GPIO_NRF24L01_IRQ (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_PORTA|GPIO_PIN0) + +#define BOARD_NRF24L01_GPIO_CE GPIO_NRF24L01_CE +#define BOARD_NRF24L01_GPIO_IRQ GPIO_NRF24L01_IRQ + +/* HCSR04 driver */ + +/* Pins config to use with HC-SR04 sensor */ + +#define GPIO_HCSR04_INT (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_PORTA|GPIO_PIN0) +#define GPIO_HCSR04_TRIG (GPIO_OUTPUT|GPIO_CNF_OUTPP|GPIO_MODE_50MHz|\ + GPIO_OUTPUT_CLEAR|GPIO_PORTA|GPIO_PIN1) + +#define BOARD_HCSR04_GPIO_INT GPIO_HCSR04_INT +#define BOARD_HCSR04_GPIO_TRIG GPIO_HCSR04_TRIG +#define BOARD_HCSR04_FRTIMER 1 /* TIM1 as free running timer */ + +/* Pin for APDS-9960 sensor */ + +#define GPIO_APDS9960_INT (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_PORTA|GPIO_PIN0) + +#define BOARD_APDS9960_GPIO_INT GPIO_APDS9960_INT + +/* ZERO CROSS pin definition */ + +#define BOARD_ZEROCROSS_GPIO \ + (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_PORTA|GPIO_PIN0) + +/* Alternate function pin selections (auto-aliased for new pinmap) */ + +/* USART1 */ + +#define GPIO_USART1_TX GPIO_ADJUST_MODE(GPIO_USART1_TX_0, GPIO_MODE_50MHz) +#define GPIO_USART1_RX GPIO_USART1_RX_0 + +/* USART2 */ + +#define GPIO_USART2_TX GPIO_ADJUST_MODE(GPIO_USART2_TX_0, GPIO_MODE_50MHz) +#define GPIO_USART2_RX GPIO_USART2_RX_0 +#define GPIO_USART2_CTS GPIO_USART2_CTS_0 +#define GPIO_USART2_RTS GPIO_ADJUST_MODE(GPIO_USART2_RTS_0, GPIO_MODE_50MHz) +#define GPIO_USART2_CK GPIO_ADJUST_MODE(GPIO_USART2_CK_0, GPIO_MODE_50MHz) + +/* SPI1 */ + +#define GPIO_SPI1_NSS GPIO_ADJUST_MODE(GPIO_SPI1_NSS_0, GPIO_MODE_50MHz) +#define GPIO_SPI1_SCK GPIO_ADJUST_MODE(GPIO_SPI1_SCK_0, GPIO_MODE_50MHz) +#define GPIO_SPI1_MISO GPIO_ADJUST_MODE(GPIO_SPI1_MISO_0, GPIO_MODE_50MHz) +#define GPIO_SPI1_MOSI GPIO_ADJUST_MODE(GPIO_SPI1_MOSI_0, GPIO_MODE_50MHz) + +/* I2C1 */ + +#define GPIO_I2C1_SCL GPIO_ADJUST_MODE(GPIO_I2C1_SCL_0, GPIO_MODE_50MHz) +#define GPIO_I2C1_SDA GPIO_ADJUST_MODE(GPIO_I2C1_SDA_0, GPIO_MODE_50MHz) + +/* I2C2 */ + +#define GPIO_I2C2_SCL GPIO_ADJUST_MODE(GPIO_I2C2_SCL_0, GPIO_MODE_50MHz) +#define GPIO_I2C2_SDA GPIO_ADJUST_MODE(GPIO_I2C2_SDA_0, GPIO_MODE_50MHz) + +/* CAN1 */ + +#define GPIO_CAN1_RX GPIO_CAN1_RX_0 +#define GPIO_CAN1_TX GPIO_ADJUST_MODE(GPIO_CAN1_TX_0, GPIO_MODE_50MHz) + +/* USB */ + +#define GPIO_USB_DM GPIO_USB_DM_0 +#define GPIO_USB_DP GPIO_USB_DP_0 + +/* TIM1 */ + +#define GPIO_TIM1_CH1IN GPIO_TIM1_CH1IN_0 +#define GPIO_TIM1_CH1OUT GPIO_ADJUST_MODE(GPIO_TIM1_CH1OUT_0, GPIO_MODE_50MHz) +#define GPIO_TIM1_CH2IN GPIO_TIM1_CH2IN_0 +#define GPIO_TIM1_CH2OUT GPIO_ADJUST_MODE(GPIO_TIM1_CH2OUT_0, GPIO_MODE_50MHz) +#define GPIO_TIM1_CH3IN GPIO_TIM1_CH3IN_0 +#define GPIO_TIM1_CH3OUT GPIO_ADJUST_MODE(GPIO_TIM1_CH3OUT_0, GPIO_MODE_50MHz) +#define GPIO_TIM1_CH4IN GPIO_TIM1_CH4IN_0 +#define GPIO_TIM1_CH4OUT GPIO_ADJUST_MODE(GPIO_TIM1_CH4OUT_0, GPIO_MODE_50MHz) +#define GPIO_TIM1_BKIN GPIO_TIM1_BKIN_0 +#define GPIO_TIM1_ETR GPIO_TIM1_ETR_0 +#define GPIO_TIM1_CH1NOUT GPIO_ADJUST_MODE(GPIO_TIM1_CH1NOUT_0, GPIO_MODE_50MHz) +#define GPIO_TIM1_CH2NOUT GPIO_ADJUST_MODE(GPIO_TIM1_CH2NOUT_0, GPIO_MODE_50MHz) +#define GPIO_TIM1_CH3NOUT GPIO_ADJUST_MODE(GPIO_TIM1_CH3NOUT_0, GPIO_MODE_50MHz) + +/* TIM2 */ + +#define GPIO_TIM2_CH1IN GPIO_TIM2_CH1IN_0 +#define GPIO_TIM2_CH1OUT GPIO_ADJUST_MODE(GPIO_TIM2_CH1OUT_0, GPIO_MODE_50MHz) +#define GPIO_TIM2_CH2IN GPIO_TIM2_CH2IN_0 +#define GPIO_TIM2_CH2OUT GPIO_ADJUST_MODE(GPIO_TIM2_CH2OUT_0, GPIO_MODE_50MHz) +#define GPIO_TIM2_CH3IN GPIO_TIM2_CH3IN_0 +#define GPIO_TIM2_CH3OUT GPIO_ADJUST_MODE(GPIO_TIM2_CH3OUT_0, GPIO_MODE_50MHz) +#define GPIO_TIM2_CH4IN GPIO_TIM2_CH4IN_0 +#define GPIO_TIM2_CH4OUT GPIO_ADJUST_MODE(GPIO_TIM2_CH4OUT_0, GPIO_MODE_50MHz) + +/* TIM3 */ + +#define GPIO_TIM3_CH1IN GPIO_TIM3_CH1IN_0 +#define GPIO_TIM3_CH1OUT GPIO_ADJUST_MODE(GPIO_TIM3_CH1OUT_0, GPIO_MODE_50MHz) +#define GPIO_TIM3_CH2IN GPIO_TIM3_CH2IN_0 +#define GPIO_TIM3_CH2OUT GPIO_ADJUST_MODE(GPIO_TIM3_CH2OUT_0, GPIO_MODE_50MHz) +#define GPIO_TIM3_CH3IN GPIO_TIM3_CH3IN_0 +#define GPIO_TIM3_CH3OUT GPIO_ADJUST_MODE(GPIO_TIM3_CH3OUT_0, GPIO_MODE_50MHz) +#define GPIO_TIM3_CH4IN GPIO_TIM3_CH4IN_0 +#define GPIO_TIM3_CH4OUT GPIO_ADJUST_MODE(GPIO_TIM3_CH4OUT_0, GPIO_MODE_50MHz) + +/* TIM4 */ + +#define GPIO_TIM4_CH1IN GPIO_TIM4_CH1IN_0 +#define GPIO_TIM4_CH1OUT GPIO_ADJUST_MODE(GPIO_TIM4_CH1OUT_0, GPIO_MODE_50MHz) +#define GPIO_TIM4_CH2IN GPIO_TIM4_CH2IN_0 +#define GPIO_TIM4_CH2OUT GPIO_ADJUST_MODE(GPIO_TIM4_CH2OUT_0, GPIO_MODE_50MHz) +#define GPIO_TIM4_CH3IN GPIO_TIM4_CH3IN_0 +#define GPIO_TIM4_CH3OUT GPIO_ADJUST_MODE(GPIO_TIM4_CH3OUT_0, GPIO_MODE_50MHz) +#define GPIO_TIM4_CH4IN GPIO_TIM4_CH4IN_0 +#define GPIO_TIM4_CH4OUT GPIO_ADJUST_MODE(GPIO_TIM4_CH4OUT_0, GPIO_MODE_50MHz) + +#endif /* __BOARDS_ARM_STM32_STM32F103_MINIMUM_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32f1/stm32f103-minimum/scripts/Make.defs b/boards/arm/stm32f1/stm32f103-minimum/scripts/Make.defs new file mode 100644 index 0000000000000..2fc72d54d7f9f --- /dev/null +++ b/boards/arm/stm32f1/stm32f103-minimum/scripts/Make.defs @@ -0,0 +1,46 @@ +############################################################################ +# boards/arm/stm32f1/stm32f103-minimum/scripts/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/.config +include $(TOPDIR)/tools/Config.mk +include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs + +ifeq ($(CONFIG_STM32_DFU),y) + LDSCRIPT = ld.script.dfu +else + LDSCRIPT = ld.script +endif + +ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) + +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32f1/stm32f103-minimum/scripts/ld.script b/boards/arm/stm32f1/stm32f103-minimum/scripts/ld.script new file mode 100644 index 0000000000000..2b4373a395604 --- /dev/null +++ b/boards/arm/stm32f1/stm32f103-minimum/scripts/ld.script @@ -0,0 +1,127 @@ +/**************************************************************************** + * boards/arm/stm32f1/stm32f103-minimum/scripts/ld.script + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* The STM32F103C8T6 has 64Kb of FLASH beginning at address 0x0800:0000 and + * 20Kb of SRAM beginning at address 0x2000:0000. When booting from FLASH, + * FLASH memory is aliased to address 0x0000:0000 where the code expects to + * begin execution by jumping to the entry point in the 0x0800:0000 address + * range. + * + * NOTE: While the STM32F103C8T6 states that the part has 64Kb of FLASH, + * all parts that I have seen do, in fact, have 128Kb of FLASH. That + * additional 64Kb of FLASH can be utilized by simply change the LENGTH + * of the flash region from 64K to 128K. + */ + +MEMORY +{ + flash (rx) : ORIGIN = 0x08000000, LENGTH = 128K + sram (rwx) : ORIGIN = 0x20000000, LENGTH = 20K +} + +OUTPUT_ARCH(arm) +EXTERN(_vectors) +ENTRY(_stext) +SECTIONS +{ + .text : { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > flash + + .init_section : ALIGN(4) { + _sinit = ABSOLUTE(.); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) + _einit = ABSOLUTE(.); + } > flash + + .ARM.extab : ALIGN(4) { + *(.ARM.extab*) + } > flash + + .ARM.exidx : ALIGN(4) { + __exidx_start = ABSOLUTE(.); + *(.ARM.exidx*) + __exidx_end = ABSOLUTE(.); + } > flash + + .tdata : { + _stdata = ABSOLUTE(.); + *(.tdata .tdata.* .gnu.linkonce.td.*); + _etdata = ABSOLUTE(.); + } > flash + + .tbss : { + _stbss = ABSOLUTE(.); + *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); + _etbss = ABSOLUTE(.); + } > flash + + _eronly = LOADADDR(.data); + + /* The STM32F103C8T6 has 20Kb of SRAM beginning at the following address */ + + .data : ALIGN(4) { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > sram AT > flash + + .bss : ALIGN(4) { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + _ebss = ABSOLUTE(.); + } > sram + + /* Stabs debugging sections. */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/stm32f1/stm32f103-minimum/scripts/ld.script.dfu b/boards/arm/stm32f1/stm32f103-minimum/scripts/ld.script.dfu new file mode 100644 index 0000000000000..28a18a1d04ad3 --- /dev/null +++ b/boards/arm/stm32f1/stm32f103-minimum/scripts/ld.script.dfu @@ -0,0 +1,118 @@ +/**************************************************************************** + * boards/arm/stm32f1/stm32f103-minimum/scripts/ld.script.dfu + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* The STM32F103C8T6 has 64Kb of FLASH beginning at address 0x0800:0000 and + * 20Kb of SRAM beginning at address 0x2000:0000. Here we assume that the + * STM32duino bootloader is being used. In that case, the correct load .text + * address is 0x0800:2000 (leaving 56Kb). + */ + +MEMORY +{ + flash (rx) : ORIGIN = 0x08002000, LENGTH = 120K + sram (rwx) : ORIGIN = 0x20000000, LENGTH = 20K +} + +OUTPUT_ARCH(arm) +EXTERN(_vectors) +ENTRY(_stext) +SECTIONS +{ + .text : { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > flash + + .init_section : ALIGN(4) { + _sinit = ABSOLUTE(.); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) + _einit = ABSOLUTE(.); + } > flash + + .ARM.extab : ALIGN(4) { + *(.ARM.extab*) + } > flash + + .ARM.exidx : ALIGN(4) { + __exidx_start = ABSOLUTE(.); + *(.ARM.exidx*) + __exidx_end = ABSOLUTE(.); + } > flash + + .tdata : { + _stdata = ABSOLUTE(.); + *(.tdata .tdata.* .gnu.linkonce.td.*); + _etdata = ABSOLUTE(.); + } > flash + + .tbss : { + _stbss = ABSOLUTE(.); + *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); + _etbss = ABSOLUTE(.); + } > flash + + _eronly = ABSOLUTE(.); + + /* The STM32F103C8T6 has 20Kb of SRAM beginning at the following address */ + + .data : ALIGN(4) { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + _edata = ABSOLUTE(.); + } > sram AT > flash + + .bss : ALIGN(4) { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + _ebss = ABSOLUTE(.); + } > sram + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/stm32f1/stm32f103-minimum/src/CMakeLists.txt b/boards/arm/stm32f1/stm32f103-minimum/src/CMakeLists.txt new file mode 100644 index 0000000000000..98249b1b9fcb3 --- /dev/null +++ b/boards/arm/stm32f1/stm32f103-minimum/src/CMakeLists.txt @@ -0,0 +1,116 @@ +# ############################################################################## +# boards/arm/stm32f1/stm32f103-minimum/src/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(SRCS stm32_boot.c stm32_bringup.c stm32_spi.c) + +if(CONFIG_ARCH_BUTTONS) + list(APPEND SRCS stm32_buttons.c) +endif() + +if(CONFIG_ARCH_LEDS) + list(APPEND SRCS stm32_autoleds.c) +else() + list(APPEND SRCS stm32_userleds.c) +endif() + +if(CONFIG_ADC) + list(APPEND SRCS stm32_adc.c) +endif() + +if(CONFIG_DEV_GPIO) + list(APPEND SRCS stm32_gpio.c) +endif() + +if(CONFIG_PWM) + list(APPEND SRCS stm32_pwm.c) +endif() + +if(CONFIG_SENSORS_HYT271) + list(APPEND SRCS stm32_hyt271.c) +endif() + +if(CONFIG_SENSORS_DS18B20) + list(APPEND SRCS stm32_ds18b20.c) +endif() + +if(CONFIG_RGBLED) + list(APPEND SRCS stm32_rgbled.c) +endif() + +if(CONFIG_MMCSD) + list(APPEND SRCS stm32_mmcsd.c) +endif() + +if(CONFIG_MTD_W25) + list(APPEND SRCS stm32_w25.c) +endif() + +if(CONFIG_MTD_AT24XX) + if(CONFIG_STM32_I2C1) + list(APPEND SRCS stm32_at24.c) + endif() +endif() + +if(CONFIG_CAN_MCP2515) + list(APPEND SRCS stm32_mcp2515.c) +endif() + +if(CONFIG_LCD_MAX7219) + list(APPEND SRCS stm32_max7219.c) +endif() + +if(CONFIG_INPUT_NUNCHUCK) + list(APPEND SRCS stm32_nunchuck.c) +endif() + +if(CONFIG_LCD_SSD1306_I2C) + list(APPEND SRCS stm32_lcd_ssd1306.c) +endif() + +if(CONFIG_LCD_ST7567) + list(APPEND SRCS stm32_lcd_st7567.c) +endif() + +if(CONFIG_LCD_PCD8544) + list(APPEND SRCS stm32_pcd8544.c) +endif() + +if(CONFIG_USBDEV) + list(APPEND SRCS stm32_usbdev.c) +endif() + +if(CONFIG_USBMSC) + list(APPEND SRCS stm32_usbmsc.c) +endif() + +if(CONFIG_STM32_CAN) + if(CONFIG_STM32_CAN_CHARDRIVER) + list(APPEND SRCS stm32_can.c) + endif() + if(CONFIG_STM32_CAN_SOCKET) + list(APPEND SRCS stm32_cansock.c) + endif() +endif() + +target_sources(board PRIVATE ${SRCS}) + +set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/ld.script") diff --git a/boards/arm/stm32f1/stm32f103-minimum/src/Make.defs b/boards/arm/stm32f1/stm32f103-minimum/src/Make.defs new file mode 100644 index 0000000000000..b65b48862a135 --- /dev/null +++ b/boards/arm/stm32f1/stm32f103-minimum/src/Make.defs @@ -0,0 +1,118 @@ +############################################################################ +# boards/arm/stm32f1/stm32f103-minimum/src/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +CSRCS = stm32_boot.c stm32_bringup.c stm32_spi.c + +ifeq ($(CONFIG_ARCH_BUTTONS),y) + CSRCS += stm32_buttons.c +endif + +ifeq ($(CONFIG_ARCH_LEDS),y) + CSRCS += stm32_autoleds.c +else + CSRCS += stm32_userleds.c +endif + +ifeq ($(CONFIG_ADC),y) +CSRCS += stm32_adc.c +endif + +ifeq ($(CONFIG_DEV_GPIO),y) + CSRCS += stm32_gpio.c +endif + +ifeq ($(CONFIG_PWM),y) + CSRCS += stm32_pwm.c +endif + +ifeq ($(CONFIG_SENSORS_HYT271),y) + CSRCS += stm32_hyt271.c +endif + +ifeq ($(CONFIG_SENSORS_DS18B20),y) + CSRCS += stm32_ds18b20.c +endif + +ifeq ($(CONFIG_RGBLED),y) + CSRCS += stm32_rgbled.c +endif + +ifeq ($(CONFIG_MMCSD),y) + CSRCS += stm32_mmcsd.c +endif + +ifeq ($(CONFIG_MTD_W25),y) + CSRCS += stm32_w25.c +endif + +ifeq ($(CONFIG_MTD_AT24XX),y) +ifeq ($(CONFIG_STM32_I2C1),y) +CSRCS += stm32_at24.c +endif +endif + +ifeq ($(CONFIG_CAN_MCP2515),y) + CSRCS += stm32_mcp2515.c +endif + +ifeq ($(CONFIG_LCD_MAX7219),y) + CSRCS += stm32_max7219.c +endif + +ifeq ($(CONFIG_INPUT_NUNCHUCK),y) + CSRCS += stm32_nunchuck.c +endif + +ifeq ($(CONFIG_LCD_SSD1306_I2C),y) +CSRCS += stm32_lcd_ssd1306.c +endif + +ifeq ($(CONFIG_LCD_ST7567),y) + CSRCS += stm32_lcd_st7567.c +endif + +ifeq ($(CONFIG_LCD_PCD8544),y) + CSRCS += stm32_pcd8544.c +endif + +ifeq ($(CONFIG_USBDEV),y) + CSRCS += stm32_usbdev.c +endif + +ifeq ($(CONFIG_USBMSC),y) +CSRCS += stm32_usbmsc.c +endif + +ifeq ($(CONFIG_STM32_CAN),y) +ifeq ($(CONFIG_STM32_CAN_CHARDRIVER),y) +CSRCS += stm32_can.c +endif +ifeq ($(CONFIG_STM32_CAN_SOCKET),y) +CSRCS += stm32_cansock.c +endif +endif + +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32f1/stm32f103-minimum/src/stm32_adc.c b/boards/arm/stm32f1/stm32f103-minimum/src/stm32_adc.c new file mode 100644 index 0000000000000..ab527d7429ea5 --- /dev/null +++ b/boards/arm/stm32f1/stm32f103-minimum/src/stm32_adc.c @@ -0,0 +1,150 @@ +/**************************************************************************** + * boards/arm/stm32f1/stm32f103-minimum/src/stm32_adc.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include +#include + +#include "chip.h" +#include "stm32_adc.h" +#include "stm32f103_minimum.h" + +#ifdef CONFIG_ADC + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* Up to 2 ADC interfaces are supported */ + +#if STM32_NADC < 2 +# undef CONFIG_STM32_ADC2 +#endif + +#if STM32_NADC < 1 +# undef CONFIG_STM32_ADC1 +#endif + +#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) +#ifndef CONFIG_STM32_ADC1 +# warning "Channel information only available for ADC1" +#endif + +/* The number of ADC channels in the conversion list */ + +#define ADC1_NCHANNELS 1 + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* Identifying number of each ADC channel to be used with Variable Resistor + * (Pontentiometer) + */ + +#ifdef CONFIG_STM32_ADC1 +static const uint8_t g_chanlist[ADC1_NCHANNELS] = +{ + 0 +}; /* ADC12_IN0 */ + +/* Configurations of pins used byte each ADC channels */ + +static const uint32_t g_pinlist[ADC1_NCHANNELS] = +{ + GPIO_ADC12_IN0 +}; +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_adc_setup + * + * Description: + * Initialize ADC and register the ADC driver. + * + ****************************************************************************/ + +int stm32_adc_setup(void) +{ +#ifdef CONFIG_STM32_ADC1 + static bool initialized = false; + struct adc_dev_s *adc; + int ret; + int i; + + /* Check if we have already initialized */ + + if (!initialized) + { + /* Configure the pins as analog inputs for the selected channels */ + + for (i = 0; i < ADC1_NCHANNELS; i++) + { + stm32_configgpio(g_pinlist[i]); + } + + /* Call stm32_adcinitialize() to get an instance of the ADC interface */ + + adc = stm32_adcinitialize(1, g_chanlist, ADC1_NCHANNELS); + if (adc == NULL) + { + aerr("ERROR: Failed to get ADC interface\n"); + return -ENODEV; + } + + /* Register the ADC driver at "/dev/adc0" */ + + ret = adc_register("/dev/adc0", adc); + if (ret < 0) + { + aerr("ERROR: adc_register failed: %d\n", ret); + return ret; + } + + /* Now we are initialized */ + + initialized = true; + } + + return OK; +#else + return -ENOSYS; +#endif +} + +#endif /* CONFIG_STM32_ADC1 || CONFIG_STM32_ADC2 || CONFIG_STM32_ADC3 */ +#endif /* CONFIG_ADC */ diff --git a/boards/arm/stm32f1/stm32f103-minimum/src/stm32_at24.c b/boards/arm/stm32f1/stm32f103-minimum/src/stm32_at24.c new file mode 100644 index 0000000000000..f4ac9eccdcc15 --- /dev/null +++ b/boards/arm/stm32f1/stm32f103-minimum/src/stm32_at24.c @@ -0,0 +1,135 @@ +/**************************************************************************** + * boards/arm/stm32f1/stm32f103-minimum/src/stm32_at24.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include +#include +#include + +#include "stm32_i2c.h" +#include "stm32f103_minimum.h" + +#ifdef HAVE_AT24 + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_at24_automount + * + * Description: + * Initialize and configure the AT24 serial EEPROM + * + ****************************************************************************/ + +int stm32_at24_automount(int minor) +{ + struct i2c_master_s *i2c; + struct mtd_dev_s *mtd; + static bool initialized = false; + int ret; + + /* Have we already initialized? */ + + if (!initialized) + { + /* No.. Get the I2C bus driver */ + + finfo("Initialize I2C%d\n", AT24_I2C_BUS); + i2c = stm32_i2cbus_initialize(AT24_I2C_BUS); + if (!i2c) + { + ferr("ERROR: Failed to initialize I2C%d\n", AT24_I2C_BUS); + return -ENODEV; + } + + /* Now bind the I2C interface to the AT24 I2C EEPROM driver */ + + finfo("Bind the AT24 EEPROM driver to I2C%d\n", AT24_I2C_BUS); + mtd = at24c_initialize(i2c); + if (!mtd) + { + ferr("ERROR: Failed to bind TWI%d to the AT24 EEPROM driver\n", + AT24_I2C_BUS); + return -ENODEV; + } + +#if defined(CONFIG_STM32F103MINIMUM_AT24_FTL) + /* Register the MTD driver */ + + char path[32]; + snprintf(path, sizeof(path), "/dev/mtdblock%d", AT24_MINOR); + ret = register_mtddriver(path, mtd, 0755, NULL); + if (ret < 0) + { + ferr("ERROR: Failed to register the MTD driver %s, ret %d\n", + path, ret); + return ret; + } + +#elif defined(CONFIG_STM32F103MINIMUM_AT24_NXFFS) + /* Initialize to provide NXFFS on the MTD interface */ + + finfo("Initialize the NXFFS file system\n"); + ret = nxffs_initialize(mtd); + if (ret < 0) + { + ferr("ERROR: NXFFS initialization failed: %d\n", ret); + return ret; + } + + /* Mount the file system at /mnt/at24 */ + + finfo("Mount the NXFFS file system at /dev/at24\n"); + ret = nx_mount(NULL, "/mnt/at24", "nxffs", 0, NULL); + if (ret < 0) + { + ferr("ERROR: Failed to mount the NXFFS volume: %d\n", ret); + return ret; + } +#endif + + /* Now we are initialized */ + + initialized = true; + } + + return OK; +} + +#endif /* HAVE_AT24 */ diff --git a/boards/arm/stm32f1/stm32f103-minimum/src/stm32_autoleds.c b/boards/arm/stm32f1/stm32f103-minimum/src/stm32_autoleds.c new file mode 100644 index 0000000000000..341981c8dd2d4 --- /dev/null +++ b/boards/arm/stm32f1/stm32f103-minimum/src/stm32_autoleds.c @@ -0,0 +1,113 @@ +/**************************************************************************** + * boards/arm/stm32f1/stm32f103-minimum/src/stm32_autoleds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32.h" +#include "stm32f103_minimum.h" + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +static inline void set_led(bool v) +{ + ledinfo("Turn LED %s\n", v? "on":"off"); + stm32_gpiowrite(GPIO_LED1, !v); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_autoled_initialize + ****************************************************************************/ + +#ifdef CONFIG_ARCH_LEDS +void board_autoled_initialize(void) +{ + /* Configure LED GPIO for output */ + + stm32_configgpio(GPIO_LED1); +} + +/**************************************************************************** + * Name: board_autoled_on + ****************************************************************************/ + +void board_autoled_on(int led) +{ + ledinfo("board_autoled_on(%d)\n", led); + + switch (led) + { + case LED_STARTED: + case LED_HEAPALLOCATE: + + /* As the board provides only one soft controllable LED, we simply + * turn it on when the board boots. + */ + + set_led(true); + break; + + case LED_PANIC: + + /* For panic state, the LED is blinking */ + + set_led(true); + break; + } +} + +/**************************************************************************** + * Name: board_autoled_off + ****************************************************************************/ + +void board_autoled_off(int led) +{ + switch (led) + { + case LED_PANIC: + + /* For panic state, the LED is blinking */ + + set_led(false); + break; + } +} + +#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32f1/stm32f103-minimum/src/stm32_boot.c b/boards/arm/stm32f1/stm32f103-minimum/src/stm32_boot.c new file mode 100644 index 0000000000000..029f62453edd4 --- /dev/null +++ b/boards/arm/stm32f1/stm32f103-minimum/src/stm32_boot.c @@ -0,0 +1,101 @@ +/**************************************************************************** + * boards/arm/stm32f1/stm32f103-minimum/src/stm32_boot.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include + +#include +#include + +#include "arm_internal.h" +#include "stm32f103_minimum.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_boardinitialize + * + * Description: + * All STM32 architectures must provide the following entry point. This + * entry point is called early in the initialization -- after all memory + * has been configured and mapped but before any devices have been + * initialized. + * + ****************************************************************************/ + +void stm32_boardinitialize(void) +{ + /* Configure on-board LEDs if LED support has been selected. */ + +#ifdef CONFIG_ARCH_LEDS + board_autoled_initialize(); +#endif + + /* Configure SPI chip selects if + * 1) SPI is not disabled, and + * 2) the weak function stm32_spidev_initialize() has been brought into + * the link. + */ + +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) + stm32_spidev_initialize(); +#endif + + /* Initialize USB is + * 1) USBDEV is selected, + * 2) the USB controller is not disabled, and + * 3) the weak function stm32_usbinitialize() has been brought + * into the build. + */ + +#if defined(CONFIG_USBDEV) && defined(CONFIG_STM32_USB) + stm32_usbinitialize(); +#endif +} + +/**************************************************************************** + * Name: board_late_initialize + * + * Description: + * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_late_initialize(). board_late_initialize() + * will be called immediately after up_initialize() is called and just + * before the initial application is started. This additional + * initialization phase may be used, for example, to initialize + * board-specific device drivers. + * + ****************************************************************************/ + +#ifdef CONFIG_BOARD_LATE_INITIALIZE +void board_late_initialize(void) +{ + stm32_bringup(); +} +#endif diff --git a/boards/arm/stm32f1/stm32f103-minimum/src/stm32_bringup.c b/boards/arm/stm32f1/stm32f103-minimum/src/stm32_bringup.c new file mode 100644 index 0000000000000..90273d107320b --- /dev/null +++ b/boards/arm/stm32f1/stm32f103-minimum/src/stm32_bringup.c @@ -0,0 +1,603 @@ +/**************************************************************************** + * boards/arm/stm32f1/stm32f103-minimum/src/stm32_bringup.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include + +#include +#include +#include + +#ifdef CONFIG_USBMONITOR +# include +#endif + +#include "stm32.h" + +#ifdef CONFIG_STM32_OTGFS +# include "stm32_usbhost.h" +#endif + +#ifdef CONFIG_INPUT_BUTTONS +# include +#endif + +#ifdef CONFIG_USERLED +# include +#endif + +#ifdef CONFIG_VIDEO_FB +# include +#endif + +#ifdef CONFIG_CL_MFRC522 +#include "stm32_mfrc522.h" +#endif + +#include "stm32f103_minimum.h" + +/* Conditional logic in stm32f103_minimum.h will determine if certain + * features are supported. Tests for these features need to be made after + * including stm32f103_minimum.h. + */ + +#ifdef HAVE_RTC_DRIVER +# include +# include "stm32_rtc.h" +#endif + +/* The following are includes from board-common logic */ + +#ifdef CONFIG_SENSORS_BMP180 +#include "stm32_bmp180.h" +#endif + +#ifdef CONFIG_LEDS_APA102 +#include "stm32_apa102.h" +#endif + +#ifdef CONFIG_WS2812 +#include "stm32_ws2812.h" +#endif + +#ifdef CONFIG_SENSORS_MAX6675 +#include "stm32_max6675.h" +#endif + +#ifdef CONFIG_SENSORS_VEML6070 +#include "stm32_veml6070.h" +#endif + +#ifdef CONFIG_INPUT_NUNCHUCK +#include "stm32_nunchuck.h" +#endif + +#ifdef CONFIG_AUDIO_TONE +#include "stm32_tone.h" +#endif + +#ifdef CONFIG_SENSORS_LM75 +#include "stm32_lm75.h" +#endif + +#ifdef CONFIG_WL_NRF24L01 +#include "stm32_nrf24l01.h" +#endif + +#ifdef CONFIG_SENSORS_HCSR04 +#include "stm32_hcsr04.h" +#endif + +#ifdef CONFIG_SENSORS_APDS9960 +#include "stm32_apds9960.h" +#endif + +#ifdef CONFIG_SENSORS_ZEROCROSS +#include "stm32_zerocross.h" +#endif + +#ifdef CONFIG_SENSORS_QENCODER +#include "board_qencoder.h" +#endif + +#ifdef CONFIG_SENSORS_HYT271 +# define HAVE_SENSORS_DEVICE +#endif + +#ifdef CONFIG_SENSORS_DS18B20 +# define HAVE_SENSORS_DEVICE +#endif + +#ifdef CONFIG_LCD_BACKPACK +#include "stm32_lcd_backpack.h" +#endif + +#ifdef CONFIG_USBADB +#include +#endif + +#ifdef CONFIG_I2C_DRIVER +#include +#include "stm32_i2c.h" +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Checking needed by W25 Flash */ + +#define HAVE_W25 1 + +/* Can't support the W25 device if it SPI1 or W25 support is not enabled */ + +#if !defined(CONFIG_STM32_SPI1) || !defined(CONFIG_MTD_W25) +# undef HAVE_W25 +#endif + +/* Can't support W25 features if mountpoints are disabled */ + +#ifdef CONFIG_DISABLE_MOUNTPOINT +# undef HAVE_W25 +#endif + +/* Default W25 minor number */ + +#if defined(HAVE_W25) && !defined(CONFIG_NSH_W25MINOR) +# define CONFIG_NSH_W25MINOR 0 +#endif + +/* Checking needed by MMC/SDCard */ + +#ifdef CONFIG_NSH_MMCSDMINOR +# define MMCSD_MINOR CONFIG_NSH_MMCSDMINOR +#else +# define MMCSD_MINOR 0 +#endif + +/**************************************************************************** + * Name: stm32_i2c_register + * + * Description: + * Register one I2C drivers for the I2C tool. + * + ****************************************************************************/ +#ifdef CONFIG_I2C_DRIVER +static void stm32_i2c_register(int bus) +{ + struct i2c_master_s *i2c; + int ret; + + i2c = stm32_i2cbus_initialize(bus); + if (i2c == NULL) + { + syslog(LOG_ERR, "ERROR: Failed to get I2C%d interface\n", bus); + } + else + { + ret = i2c_register(i2c, bus); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to register I2C%d driver: %d\n", + bus, ret); + stm32_i2cbus_uninitialize(i2c); + } + } +} +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#ifdef HAVE_SENSORS_DEVICE +static int g_sensor_devno; +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_bringup + * + * Description: + * Perform architecture-specific initialization + * + * CONFIG_BOARD_LATE_INITIALIZE=y : + * Called from board_late_initialize(). + * + ****************************************************************************/ + +int stm32_bringup(void) +{ +#ifdef CONFIG_ONESHOT + struct oneshot_lowerhalf_s *os = NULL; +#endif + int ret = OK; + +#ifdef CONFIG_DEV_GPIO + ret = stm32_gpio_initialize(); + if (ret < 0) + { + syslog(LOG_ERR, "Failed to initialize GPIO Driver: %d\n", ret); + return ret; + } +#endif + +#ifdef CONFIG_VIDEO_FB + /* Initialize and register the framebuffer driver */ + + ret = fb_register(0, 0); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: fb_register() failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_I2C_DRIVER + /* Register I2C drivers on behalf of the I2C tool */ + #ifdef CONFIG_STM32_I2C1 + stm32_i2c_register(1); + #endif + #ifdef CONFIG_STM32_I2C2 + stm32_i2c_register(2); + #endif + #ifdef CONFIG_STM32_I2C3 + stm32_i2c_register(3); + #endif +#endif + +#ifdef CONFIG_LCD_BACKPACK + /* slcd:0, i2c:1, rows=2, cols=16 */ + + ret = board_lcd_backpack_init(0, 1, 2, 16); + if (ret < 0) + { + syslog(LOG_ERR, "Failed to initialize PCF8574 LCD, error %d\n", ret); + return ret; + } +#endif + +#ifdef CONFIG_SENSORS_ZEROCROSS + /* Configure the zero-crossing driver */ + + ret = board_zerocross_initialize(0); + if (ret < 0) + { + syslog(LOG_ERR, "Failed to initialize Zero-Cross, error %d\n", ret); + return ret; + } +#endif + +#ifdef CONFIG_MMCSD + ret = stm32_mmcsd_initialize(MMCSD_MINOR); + if (ret < 0) + { + syslog(LOG_ERR, "Failed to initialize SD slot %d: %d\n", ret); + return ret; + } +#endif + +#ifdef CONFIG_SENSORS_BMP180 + /* Initialize the BMP180 pressure sensor. */ + + ret = board_bmp180_initialize(0, 1); + if (ret < 0) + { + syslog(LOG_ERR, "Failed to initialize BMP180, error %d\n", ret); + return ret; + } +#endif + +#ifdef HAVE_W25 + /* Initialize and register the W25 FLASH file system. */ + + ret = stm32_w25initialize(CONFIG_NSH_W25MINOR); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to initialize W25 minor %d: %d\n", + CONFIG_NSH_W25MINOR, ret); + return ret; + } +#endif + +#ifdef CONFIG_FS_PROCFS + /* Mount the procfs file system */ + + ret = nx_mount(NULL, STM32_PROCFS_MOUNTPOINT, "procfs", 0, NULL); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to mount procfs at %s: %d\n", + STM32_PROCFS_MOUNTPOINT, ret); + } +#endif + +#ifdef HAVE_AT24 + /* Initialize the AT24 driver */ + + ret = stm32_at24_automount(AT24_MINOR); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_at24_automount() failed: %d\n", ret); + return ret; + } +#endif /* HAVE_AT24 */ + +#ifdef CONFIG_PWM + /* Initialize PWM and register the PWM device. */ + + ret = stm32_pwm_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_pwm_setup() failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_AUDIO_TONE + /* Configure and initialize the tone generator. */ + + ret = board_tone_initialize(0); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: board_tone_initialize() failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_LEDS_APA102 + /* Configure and initialize the APA102 LED Strip. */ + + ret = board_apa102_initialize(0, 1); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: board_apa102_initialize() failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_WS2812 + /* Configure and initialize the WS2812 LEDs. */ + + ret = board_ws2812_initialize(0, WS2812_SPI, WS2812_NLEDS); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: board_ws2812_initialize() failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_SENSORS_HYT271 + /* Configure and initialize the HYT271 sensors */ + + ret = stm32_hyt271initialize(g_sensor_devno); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_hyt271initialize() failed: %d\n", ret); + } + else + { + g_sensor_devno += ret; + } +#endif + +#ifdef CONFIG_SENSORS_DS18B20 + /* Configure and initialize the DS18B20 sensors */ + + ret = stm32_ds18b20initialize(g_sensor_devno); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_ds18b20initialize() failed: %d\n", ret); + } + else + { + g_sensor_devno += ret; + } +#endif + +#ifdef CONFIG_LM75_I2C + /* Configure and initialize the LM75 sensor */ + + ret = board_lm75_initialize(0, 1); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: board_lm75_initialize() failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_RGBLED + /* Configure and initialize the RGB LED. */ + + ret = stm32_rgbled_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_rgbled_setup() failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_SENSORS_HCSR04 + /* Configure and initialize the HC-SR04 distance sensor */ + + ret = board_hcsr04_initialize(0); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: board_hcsr04_initialize() failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_SENSORS_MAX6675 + ret = board_max6675_initialize(0, 1); + if (ret < 0) + { + serr("ERROR: board_max6675_initialize() failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_CAN_MCP2515 + /* Configure and initialize the MCP2515 CAN device */ + + ret = stm32_mcp2515initialize("/dev/can0"); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_mcp2515initialize() failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_CL_MFRC522 + ret = stm32_mfrc522initialize("/dev/rfid0"); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_mfrc522initialize() failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_ONESHOT + os = oneshot_initialize(1, 10); + if (os) + { + ret = oneshot_register("/dev/oneshot", os); + } +#endif + +#ifdef CONFIG_INPUT_BUTTONS + /* Register the BUTTON driver */ + + ret = btn_lower_initialize("/dev/buttons"); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: btn_lower_initialize() failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_INPUT_NUNCHUCK + /* Register the Nunchuck driver */ + + ret = board_nunchuck_initialize(0, 1); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: board_nunchuck_initialize() failed: %d\n", + ret); + } +#endif + +#ifdef CONFIG_SENSORS_QENCODER + /* Initialize and register the qencoder driver */ + + ret = board_qencoder_initialize(0, + CONFIG_STM32F103MINIMUM_QETIMER); + if (ret != OK) + { + syslog(LOG_ERR, + "ERROR: Failed to register the qencoder: %d\n", + ret); + } +#endif + +#ifdef CONFIG_USERLED + /* Register the LED driver */ + + ret = userled_lower_initialize("/dev/userleds"); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: userled_lower_initialize() failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_SENSORS_APDS9960 + /* Register the APDS-9960 gesture sensor */ + + ret = board_apds9960_initialize(0, 1); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: board_apds9960_initialize() failed: %d\n", + ret); + } +#endif + +#ifdef CONFIG_SENSORS_VEML6070 + /* Register the UV-A light sensor */ + + ret = board_veml6070_initialize(0, 1); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: board_veml6070_initialize() failed: %d\n", + ret); + } +#endif + +#ifdef CONFIG_ADC + /* Initialize ADC and register the ADC driver. */ + + ret = stm32_adc_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_adc_setup() failed: %d\n", ret); + } +#endif + +#if defined(CONFIG_WL_NRF24L01) + /* Initialize the NRF24L01 wireless module */ + + ret = board_nrf24l01_initialize(1); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: board_nrf24l01_initialize() failed: %d\n", + ret); + } +#endif + +#ifdef CONFIG_USBADB + usbdev_adb_initialize(); +#endif + +#ifdef CONFIG_STM32_CAN_CHARDRIVER + /* Initialize CAN and register the CAN driver. */ + + ret = stm32_can_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_can_setup failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_STM32_CAN_SOCKET + /* Initialize CAN socket interface */ + + /* STM32F103C8 may not have enough Flash for SocketCAN; use a part with + * more Flash (e.g. STM32F103CB). + */ + + ret = stm32_cansock_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_cansock_setup failed: %d\n", ret); + } +#endif + + return ret; +} diff --git a/boards/arm/stm32f1/stm32f103-minimum/src/stm32_buttons.c b/boards/arm/stm32f1/stm32f103-minimum/src/stm32_buttons.c new file mode 100644 index 0000000000000..55775a26fd983 --- /dev/null +++ b/boards/arm/stm32f1/stm32f103-minimum/src/stm32_buttons.c @@ -0,0 +1,160 @@ +/**************************************************************************** + * boards/arm/stm32f1/stm32f103-minimum/src/stm32_buttons.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include +#include + +#include "stm32_gpio.h" +#include "stm32f103_minimum.h" + +#if defined(CONFIG_ARCH_BUTTONS) + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#if defined(CONFIG_INPUT_BUTTONS) && !defined(CONFIG_ARCH_IRQBUTTONS) +# error "The NuttX Buttons Driver depends on IRQ support to work!\n" +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/* Pin configuration for each STM32F3Discovery button. This array is indexed + * by the BUTTON_* definitions in board.h + */ + +static const uint32_t g_buttons[NUM_BUTTONS] = +{ + GPIO_BTN_USER1, GPIO_BTN_USER2 +}; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_button_initialize + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. + * + ****************************************************************************/ + +uint32_t board_button_initialize(void) +{ + int i; + + /* Configure the GPIO pins as inputs. NOTE that EXTI interrupts are + * configured for all pins. + */ + + for (i = 0; i < NUM_BUTTONS; i++) + { + stm32_configgpio(g_buttons[i]); + } + + return NUM_BUTTONS; +} + +/**************************************************************************** + * Name: board_buttons + ****************************************************************************/ + +uint32_t board_buttons(void) +{ + uint32_t ret = 0; + int i; + + /* Check that state of each key */ + + for (i = 0; i < NUM_BUTTONS; i++) + { + /* A LOW value means that the key is pressed. */ + + bool released = stm32_gpioread(g_buttons[i]); + + /* Accumulate the set of depressed (not released) keys */ + + if (!released) + { + ret |= (1 << i); + } + } + + return ret; +} + +/**************************************************************************** + * Button support. + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. + * + * After board_button_initialize() has been called, board_buttons() may be + * called to collect the state of all buttons. board_buttons() returns + * an 32-bit bit set with each bit associated with a button. See the + * BUTTON_*_BIT definitions in board.h for the meaning of each bit. + * + * board_button_irq() may be called to register an interrupt handler that + * will be called when a button is depressed or released. The ID value is + * a button enumeration value that uniquely identifies a button resource. + * See the BUTTON_* definitions in board.h for the meaning of enumeration + * value. + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_IRQBUTTONS +int board_button_irq(int id, xcpt_t irqhandler, void *arg) +{ + int ret = -EINVAL; + + /* The following should be atomic */ + + if (id >= MIN_IRQBUTTON && id <= MAX_IRQBUTTON) + { + ret = stm32_gpiosetevent(g_buttons[id], true, true, true, irqhandler, + arg); + } + + return ret; +} +#endif + +#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/stm32f1/stm32f103-minimum/src/stm32_can.c b/boards/arm/stm32f1/stm32f103-minimum/src/stm32_can.c new file mode 100644 index 0000000000000..3b80bc794fd9a --- /dev/null +++ b/boards/arm/stm32f1/stm32f103-minimum/src/stm32_can.c @@ -0,0 +1,69 @@ +/**************************************************************************** + * boards/arm/stm32f1/stm32f103-minimum/src/stm32_can.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include + +#include "stm32.h" +#include "stm32_can.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_can_setup + * + * Description: + * Initialize CAN and register the CAN device + * + ****************************************************************************/ + +int stm32_can_setup(void) +{ + struct can_dev_s *can; + int ret; + + can = stm32_caninitialize(1); + if (can == NULL) + { + canerr("ERROR: Failed to get CAN interface\n"); + return -ENODEV; + } + + ret = can_register("/dev/can0", can); + if (ret < 0) + { + canerr("ERROR: can_register failed: %d\n", ret); + return ret; + } + + return OK; +} diff --git a/boards/arm/stm32f1/stm32f103-minimum/src/stm32_cansock.c b/boards/arm/stm32f1/stm32f103-minimum/src/stm32_cansock.c new file mode 100644 index 0000000000000..db15840d4b867 --- /dev/null +++ b/boards/arm/stm32f1/stm32f103-minimum/src/stm32_cansock.c @@ -0,0 +1,59 @@ +/**************************************************************************** + * boards/arm/stm32f1/stm32f103-minimum/src/stm32_cansock.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include "stm32_can.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_cansock_setup + * + * Description: + * Initialize CAN socket interface + * + ****************************************************************************/ + +int stm32_cansock_setup(void) +{ + int ret; + + /* Call stm32_cansockinitialize() to register the CAN network device */ + + ret = stm32_cansockinitialize(1); + if (ret < 0) + { + canerr("ERROR: Failed to get CAN interface %d\n", ret); + return ret; + } + + return OK; +} diff --git a/boards/arm/stm32/stm32f103-minimum/src/stm32_ds18b20.c b/boards/arm/stm32f1/stm32f103-minimum/src/stm32_ds18b20.c similarity index 98% rename from boards/arm/stm32/stm32f103-minimum/src/stm32_ds18b20.c rename to boards/arm/stm32f1/stm32f103-minimum/src/stm32_ds18b20.c index 91b7c4e8da079..3749f5d14c063 100644 --- a/boards/arm/stm32/stm32f103-minimum/src/stm32_ds18b20.c +++ b/boards/arm/stm32f1/stm32f103-minimum/src/stm32_ds18b20.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f103-minimum/src/stm32_ds18b20.c + * boards/arm/stm32f1/stm32f103-minimum/src/stm32_ds18b20.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f1/stm32f103-minimum/src/stm32_gpio.c b/boards/arm/stm32f1/stm32f103-minimum/src/stm32_gpio.c new file mode 100644 index 0000000000000..aa0cf6dc13b77 --- /dev/null +++ b/boards/arm/stm32f1/stm32f103-minimum/src/stm32_gpio.c @@ -0,0 +1,343 @@ +/**************************************************************************** + * boards/arm/stm32f1/stm32f103-minimum/src/stm32_gpio.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include +#include + +#include + +#include "chip.h" +#include "stm32.h" +#include "stm32f103_minimum.h" + +#if defined(CONFIG_DEV_GPIO) && !defined(CONFIG_GPIO_LOWER_HALF) + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +struct stm32gpio_dev_s +{ + struct gpio_dev_s gpio; + uint8_t id; +}; + +struct stm32gpint_dev_s +{ + struct stm32gpio_dev_s stm32gpio; + pin_interrupt_t callback; +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +#if BOARD_NGPIOIN > 0 +static int gpin_read(struct gpio_dev_s *dev, bool *value); +#endif /* BOARD_NGPIOIN > 0 */ +#if BOARD_NGPIOOUT > 0 +static int gpout_read(struct gpio_dev_s *dev, bool *value); +static int gpout_write(struct gpio_dev_s *dev, bool value); +#endif /* BOARD_NGPIOOUT > 0 */ +#if BOARD_NGPIOINT > 0 +static int gpint_read(struct gpio_dev_s *dev, bool *value); +static int gpint_attach(struct gpio_dev_s *dev, + pin_interrupt_t callback); +static int gpint_enable(struct gpio_dev_s *dev, bool enable); +#endif /* BOARD_NGPIOINT > 0 */ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#if BOARD_NGPIOIN > 0 +static const struct gpio_operations_s gpin_ops = +{ + .go_read = gpin_read, + .go_write = NULL, + .go_attach = NULL, + .go_enable = NULL, +}; +#endif /* BOARD_NGPIOIN > 0 */ + +#if BOARD_NGPIOOUT > 0 +static const struct gpio_operations_s gpout_ops = +{ + .go_read = gpout_read, + .go_write = gpout_write, + .go_attach = NULL, + .go_enable = NULL, +}; +#endif /* BOARD_NGPIOOUT > 0 */ + +#if BOARD_NGPIOINT > 0 +static const struct gpio_operations_s gpint_ops = +{ + .go_read = gpint_read, + .go_write = NULL, + .go_attach = gpint_attach, + .go_enable = gpint_enable, +}; +#endif /* BOARD_NGPIOINT > 0 */ + +#if BOARD_NGPIOIN > 0 +/* This array maps the GPIO pins used as INPUT */ + +static const uint32_t g_gpioinputs[BOARD_NGPIOIN] = +{ + GPIO_IN1, +}; + +static struct stm32gpio_dev_s g_gpin[BOARD_NGPIOIN]; +#endif + +#if BOARD_NGPIOOUT > 0 +/* This array maps the GPIO pins used as OUTPUT */ + +static const uint32_t g_gpiooutputs[BOARD_NGPIOOUT] = +{ + GPIO_OUT1, +}; + +static struct stm32gpio_dev_s g_gpout[BOARD_NGPIOOUT]; +#endif + +#if BOARD_NGPIOINT > 0 +/* This array maps the GPIO pins used as INTERRUPT INPUTS */ + +static const uint32_t g_gpiointinputs[BOARD_NGPIOINT] = +{ + GPIO_INT1, +}; + +static struct stm32gpint_dev_s g_gpint[BOARD_NGPIOINT]; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + + #if BOARD_NGPIOINT > 0 +static int stm32gpio_interrupt(int irq, void *context, void *arg) +{ + struct stm32gpint_dev_s *stm32gpint = + (struct stm32gpint_dev_s *)arg; + + DEBUGASSERT(stm32gpint != NULL && stm32gpint->callback != NULL); + gpioinfo("Interrupt! callback=%p\n", stm32gpint->callback); + + stm32gpint->callback(&stm32gpint->stm32gpio.gpio, + stm32gpint->stm32gpio.id); + return OK; +} +#endif /* BOARD_NGPIOINT > 0 */ + +#if BOARD_NGPIOIN > 0 +static int gpin_read(struct gpio_dev_s *dev, bool *value) +{ + struct stm32gpio_dev_s *stm32gpio = + (struct stm32gpio_dev_s *)dev; + + DEBUGASSERT(stm32gpio != NULL && value != NULL); + DEBUGASSERT(stm32gpio->id < BOARD_NGPIOIN); + gpioinfo("Reading...\n"); + + *value = stm32_gpioread(g_gpioinputs[stm32gpio->id]); + return OK; +} +#endif /* BOARD_NGPIOIN > 0*/ + +#if BOARD_NGPIOOUT > 0 +static int gpout_read(struct gpio_dev_s *dev, bool *value) +{ + struct stm32gpio_dev_s *stm32gpio = + (struct stm32gpio_dev_s *)dev; + + DEBUGASSERT(stm32gpio != NULL && value != NULL); + DEBUGASSERT(stm32gpio->id < BOARD_NGPIOOUT); + gpioinfo("Reading...\n"); + + *value = stm32_gpioread(g_gpiooutputs[stm32gpio->id]); + return OK; +} + +static int gpout_write(struct gpio_dev_s *dev, bool value) +{ + struct stm32gpio_dev_s *stm32gpio = + (struct stm32gpio_dev_s *)dev; + + DEBUGASSERT(stm32gpio != NULL); + DEBUGASSERT(stm32gpio->id < BOARD_NGPIOOUT); + gpioinfo("Writing %d\n", (int)value); + + stm32_gpiowrite(g_gpiooutputs[stm32gpio->id], value); + return OK; +} +#endif /* BOARD_NGPIOOUT > 0 */ + +#if BOARD_NGPIOINT > 0 +static int gpint_read(struct gpio_dev_s *dev, bool *value) +{ + struct stm32gpint_dev_s *stm32gpint = + (struct stm32gpint_dev_s *)dev; + + DEBUGASSERT(stm32gpint != NULL && value != NULL); + DEBUGASSERT(stm32gpint->stm32gpio.id < BOARD_NGPIOINT); + gpioinfo("Reading int pin...\n"); + + *value = stm32_gpioread(g_gpiointinputs[stm32gpint->stm32gpio.id]); + return OK; +} + +static int gpint_attach(struct gpio_dev_s *dev, + pin_interrupt_t callback) +{ + struct stm32gpint_dev_s *stm32gpint = + (struct stm32gpint_dev_s *)dev; + + gpioinfo("Attaching the callback\n"); + + /* Make sure the interrupt is disabled */ + + stm32_gpiosetevent(g_gpiointinputs[stm32gpint->stm32gpio.id], false, + false, false, NULL, NULL); + + gpioinfo("Attach %p\n", callback); + stm32gpint->callback = callback; + return OK; +} + +static int gpint_enable(struct gpio_dev_s *dev, bool enable) +{ + struct stm32gpint_dev_s *stm32gpint = + (struct stm32gpint_dev_s *)dev; + + if (enable) + { + if (stm32gpint->callback != NULL) + { + gpioinfo("Enabling the interrupt\n"); + + /* Configure the interrupt for rising edge */ + + stm32_gpiosetevent(g_gpiointinputs[stm32gpint->stm32gpio.id], + true, false, false, stm32gpio_interrupt, + &g_gpint[stm32gpint->stm32gpio.id]); + } + } + else + { + gpioinfo("Disable the interrupt\n"); + stm32_gpiosetevent(g_gpiointinputs[stm32gpint->stm32gpio.id], + false, false, false, NULL, NULL); + } + + return OK; +} +#endif /* BOARD_NGPIOINT > 0 */ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_gpio_initialize + * + * Description: + * Initialize GPIO drivers for use with /apps/examples/gpio + * + ****************************************************************************/ + +int stm32_gpio_initialize(void) +{ + int i; + int pincount = 0; + +#if BOARD_NGPIOIN > 0 + for (i = 0; i < BOARD_NGPIOIN; i++) + { + /* Setup and register the GPIO pin */ + + g_gpin[i].gpio.gp_pintype = GPIO_INPUT_PIN; + g_gpin[i].gpio.gp_ops = &gpin_ops; + g_gpin[i].id = i; + gpio_pin_register(&g_gpin[i].gpio, pincount); + + /* Configure the pin that will be used as input */ + + stm32_configgpio(g_gpioinputs[i]); + + pincount++; + } +#endif + +#if BOARD_NGPIOOUT > 0 + for (i = 0; i < BOARD_NGPIOOUT; i++) + { + /* Setup and register the GPIO pin */ + + g_gpout[i].gpio.gp_pintype = GPIO_OUTPUT_PIN; + g_gpout[i].gpio.gp_ops = &gpout_ops; + g_gpout[i].id = i; + gpio_pin_register(&g_gpout[i].gpio, pincount); + + /* Configure the pin that will be used as output */ + + stm32_gpiowrite(g_gpiooutputs[i], 0); + stm32_configgpio(g_gpiooutputs[i]); + + pincount++; + } +#endif + +#if BOARD_NGPIOINT > 0 + for (i = 0; i < BOARD_NGPIOINT; i++) + { + /* Setup and register the GPIO pin */ + + g_gpint[i].stm32gpio.gpio.gp_pintype = GPIO_INTERRUPT_PIN; + g_gpint[i].stm32gpio.gpio.gp_ops = &gpint_ops; + g_gpint[i].stm32gpio.id = i; + gpio_pin_register(&g_gpint[i].stm32gpio.gpio, pincount); + + /* Configure the pin that will be used as interrupt input */ + + stm32_configgpio(g_gpiointinputs[i]); + + pincount++; + } +#endif + + return 0; +} +#endif /* CONFIG_DEV_GPIO && !CONFIG_GPIO_LOWER_HALF */ diff --git a/boards/arm/stm32/stm32f103-minimum/src/stm32_hyt271.c b/boards/arm/stm32f1/stm32f103-minimum/src/stm32_hyt271.c similarity index 98% rename from boards/arm/stm32/stm32f103-minimum/src/stm32_hyt271.c rename to boards/arm/stm32f1/stm32f103-minimum/src/stm32_hyt271.c index e054a450031e4..7ebd76dd08a59 100644 --- a/boards/arm/stm32/stm32f103-minimum/src/stm32_hyt271.c +++ b/boards/arm/stm32f1/stm32f103-minimum/src/stm32_hyt271.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f103-minimum/src/stm32_hyt271.c + * boards/arm/stm32f1/stm32f103-minimum/src/stm32_hyt271.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f1/stm32f103-minimum/src/stm32_lcd_ssd1306.c b/boards/arm/stm32f1/stm32f103-minimum/src/stm32_lcd_ssd1306.c new file mode 100644 index 0000000000000..206ed62e678c8 --- /dev/null +++ b/boards/arm/stm32f1/stm32f103-minimum/src/stm32_lcd_ssd1306.c @@ -0,0 +1,88 @@ +/**************************************************************************** + * boards/arm/stm32f1/stm32f103-minimum/src/stm32_lcd_ssd1306.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include +#include +#include + +#include "stm32.h" +#include "stm32f103_minimum.h" + +#include "stm32_ssd1306.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define OLED_I2C_PORT 1 /* OLED display connected to I2C1 */ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_lcd_initialize + ****************************************************************************/ + +int board_lcd_initialize(void) +{ + int ret; + + ret = board_ssd1306_initialize(OLED_I2C_PORT); + if (ret < 0) + { + lcderr("ERROR: Failed to initialize SSD1306\n"); + return ret; + } + + return OK; +} + +/**************************************************************************** + * Name: board_lcd_getdev + ****************************************************************************/ + +struct lcd_dev_s *board_lcd_getdev(int devno) +{ + return board_ssd1306_getdev(); +} + +/**************************************************************************** + * Name: board_lcd_uninitialize + ****************************************************************************/ + +void board_lcd_uninitialize(void) +{ + /* TO-FIX */ +} diff --git a/boards/arm/stm32/stm32f103-minimum/src/stm32_lcd_st7567.c b/boards/arm/stm32f1/stm32f103-minimum/src/stm32_lcd_st7567.c similarity index 98% rename from boards/arm/stm32/stm32f103-minimum/src/stm32_lcd_st7567.c rename to boards/arm/stm32f1/stm32f103-minimum/src/stm32_lcd_st7567.c index 97381277ed099..e0337214ebf25 100644 --- a/boards/arm/stm32/stm32f103-minimum/src/stm32_lcd_st7567.c +++ b/boards/arm/stm32f1/stm32f103-minimum/src/stm32_lcd_st7567.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f103-minimum/src/stm32_lcd_st7567.c + * boards/arm/stm32f1/stm32f103-minimum/src/stm32_lcd_st7567.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f1/stm32f103-minimum/src/stm32_max7219.c b/boards/arm/stm32f1/stm32f103-minimum/src/stm32_max7219.c new file mode 100644 index 0000000000000..d4205a9f0e534 --- /dev/null +++ b/boards/arm/stm32f1/stm32f103-minimum/src/stm32_max7219.c @@ -0,0 +1,114 @@ +/**************************************************************************** + * boards/arm/stm32f1/stm32f103-minimum/src/stm32_max7219.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include "stm32_gpio.h" +#include "stm32_spi.h" +#include "stm32f103_minimum.h" + +#ifdef CONFIG_NX_LCDDRIVER + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define LCD_SPI_PORTNO 1 /* On SPI1 */ + +#ifndef CONFIG_LCD_CONTRAST +# define CONFIG_LCD_CONTRAST 60 +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +struct spi_dev_s *g_spidev; +struct lcd_dev_s *g_lcddev; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_lcd_initialize + ****************************************************************************/ + +int board_lcd_initialize(void) +{ + g_spidev = stm32_spibus_initialize(LCD_SPI_PORTNO); + + if (!g_spidev) + { + lcderr("ERROR: Failed to initialize SPI port %d\n", LCD_SPI_PORTNO); + return -ENODEV; + } + + return OK; +} + +/**************************************************************************** + * Name: board_lcd_getdev + ****************************************************************************/ + +struct lcd_dev_s *board_lcd_getdev(int lcddev) +{ + g_lcddev = max7219_initialize(g_spidev, lcddev); + if (!g_lcddev) + { + lcderr("ERROR: Failed to bind SPI port 1 to LCD %d\n", lcddev); + } + else + { + lcdinfo("SPI port 1 bound to LCD %d\n", lcddev); + + return g_lcddev; + } + + return NULL; +} + +/**************************************************************************** + * Name: board_lcd_uninitialize + ****************************************************************************/ + +void board_lcd_uninitialize(void) +{ + /* TO-FIX */ +} + +#endif /* CONFIG_NX_LCDDRIVER */ diff --git a/boards/arm/stm32f1/stm32f103-minimum/src/stm32_mcp2515.c b/boards/arm/stm32f1/stm32f103-minimum/src/stm32_mcp2515.c new file mode 100644 index 0000000000000..ed9b317847f85 --- /dev/null +++ b/boards/arm/stm32f1/stm32f103-minimum/src/stm32_mcp2515.c @@ -0,0 +1,241 @@ +/**************************************************************************** + * boards/arm/stm32f1/stm32f103-minimum/src/stm32_mcp2515.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "stm32.h" +#include "stm32_spi.h" +#include "stm32f103_minimum.h" + +#if defined(CONFIG_SPI) && defined(CONFIG_STM32_SPI1) && \ + defined(CONFIG_CAN_MCP2515) + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define MCP2515_SPI_PORTNO 1 /* On SPI1 */ + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +struct stm32_mcp2515config_s +{ + /* Configuration structure as seen by the MCP2515 driver */ + + struct mcp2515_config_s config; + + /* Additional private definitions only known to this driver */ + + struct mcp2515_can_s *handle; /* The MCP2515 driver handle */ + mcp2515_handler_t handler; /* The MCP2515 interrupt handler */ + void *arg; /* Argument to pass to the interrupt handler */ +}; + +/**************************************************************************** + * Static Function Prototypes + ****************************************************************************/ + +/* IRQ/GPIO access callbacks. These operations all hidden behind callbacks + * to isolate the MCP2515 driver from differences in GPIO interrupt handling + * by varying boards and MCUs. + * + * attach - Attach the MCP2515 interrupt handler to the GPIO interrupt + */ + +static int mcp2515_attach(struct mcp2515_config_s *state, + mcp2515_handler_t handler, void *arg); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* A reference to a structure of this type must be passed to the MCP2515 + * driver. This structure provides information about the configuration + * of the MCP2515 and provides some board-specific hooks. + * + * Memory for this structure is provided by the caller. It is not copied + * by the driver and is presumed to persist while the driver is active. The + * memory must be writable because, under certain circumstances, the driver + * may modify frequency or X plate resistance values. + */ + +static struct stm32_mcp2515config_s g_mcp2515config = +{ + .config = + { + .spi = NULL, + .baud = 0, /* REVISIT. Probably broken by commit eb7373cedfa */ + .btp = 0, /* REVISIT. Probably broken by commit eb7373cedfa */ + .devid = 0, + .mode = 0, /* REVISIT. Probably broken by commit eb7373cedfa */ + .nfilters = 6, +#ifdef MCP2515_LOOPBACK + .loopback = false; +#endif + .attach = mcp2515_attach, + }, +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/* This is the MCP2515 Interrupt handler */ + +int mcp2515_interrupt(int irq, void *context, void *arg) +{ + struct stm32_mcp2515config_s *priv = + (struct stm32_mcp2515config_s *)arg; + + DEBUGASSERT(priv != NULL); + + /* Verify that we have a handler attached */ + + if (priv->handler) + { + /* Yes.. forward with interrupt along with its argument */ + + priv->handler(&priv->config, priv->arg); + } + + return OK; +} + +static int mcp2515_attach(struct mcp2515_config_s *state, + mcp2515_handler_t handler, void *arg) +{ + struct stm32_mcp2515config_s *priv = + (struct stm32_mcp2515config_s *)state; + irqstate_t flags; + + caninfo("Saving handler %p\n", handler); + + flags = enter_critical_section(); + + priv->handler = handler; + priv->arg = arg; + + /* Configure the interrupt for falling edge */ + + stm32_gpiosetevent(GPIO_MCP2515_IRQ, false, true, false, + mcp2515_interrupt, priv); + + leave_critical_section(flags); + + return OK; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_mcp2515initialize + * + * Description: + * Initialize and register the MCP2515 RFID driver. + * + * Input Parameters: + * devpath - The full path to the driver to register. E.g., "/dev/rfid0" + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +int stm32_mcp2515initialize(const char *devpath) +{ + struct spi_dev_s *spi; + struct can_dev_s *can; + struct mcp2515_can_s *mcp2515; + int ret; + + /* Check if we are already initialized */ + + if (!g_mcp2515config.handle) + { + sninfo("Initializing\n"); + + /* Configure the MCP2515 interrupt pin as an input */ + + stm32_configgpio(GPIO_MCP2515_IRQ); + + spi = stm32_spibus_initialize(MCP2515_SPI_PORTNO); + + if (!spi) + { + return -ENODEV; + } + + /* Save the SPI instance in the mcp2515_config_s structure */ + + g_mcp2515config.config.spi = spi; + + /* Instantiate the MCP2515 CAN Driver */ + + mcp2515 = mcp2515_instantiate(&g_mcp2515config.config); + if (mcp2515 == NULL) + { + canerr("ERROR: Failed to get MCP2515 Driver Loaded\n"); + return -ENODEV; + } + + /* Save the opaque structure */ + + g_mcp2515config.handle = mcp2515; + + /* Initialize the CAN Device with the MCP2515 operations */ + + can = mcp2515_initialize(mcp2515); + if (can == NULL) + { + canerr("ERROR: Failed to get CAN interface\n"); + return -ENODEV; + } + + /* Register the CAN driver at "/dev/can0" */ + + ret = can_register(devpath, can); + if (ret < 0) + { + canerr("ERROR: can_register failed: %d\n", ret); + return ret; + } + } + + return OK; +} + +#endif /* CONFIG_SPI && CONFIG_CAN_MCP2515 */ diff --git a/boards/arm/stm32f1/stm32f103-minimum/src/stm32_mmcsd.c b/boards/arm/stm32f1/stm32f103-minimum/src/stm32_mmcsd.c new file mode 100644 index 0000000000000..a8aa3c854896b --- /dev/null +++ b/boards/arm/stm32f1/stm32f103-minimum/src/stm32_mmcsd.c @@ -0,0 +1,116 @@ +/**************************************************************************** + * boards/arm/stm32f1/stm32f103-minimum/src/stm32_mmcsd.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "stm32.h" +#include "stm32f103_minimum.h" +#include "stm32_spi.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifndef CONFIG_STM32_SPI1 +# error "SD driver requires CONFIG_STM32_SPI1 to be enabled" +#endif + +#ifdef CONFIG_DISABLE_MOUNTPOINT +# error "SD driver requires CONFIG_DISABLE_MOUNTPOINT to be disabled" +#endif + +/**************************************************************************** + * Private Definitions + ****************************************************************************/ + +static const int SD_SPI_PORT = 1; /* SD is connected to SPI1 port */ +static const int SD_SLOT_NO = 0; /* There is only one SD slot */ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/* NOTE: We are using a SDCard adapter/module without Card Detect pin! + * Then we don't need to Card Detect callback here. + */ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_spi1register + * + * Description: + * Registers media change callback + ****************************************************************************/ + +int stm32_spi1register(struct spi_dev_s *dev, spi_mediachange_t callback, + void *arg) +{ + spiinfo("INFO: Registering spi1 device\n"); + return OK; +} + +/**************************************************************************** + * Name: stm32_mmcsd_initialize + * + * Description: + * Initialize SPI-based SD card and card detect thread. + ****************************************************************************/ + +int stm32_mmcsd_initialize(int minor) +{ + struct spi_dev_s *spi; + int rv; + + mcinfo("INFO: Initializing mmcsd card\n"); + + spi = stm32_spibus_initialize(SD_SPI_PORT); + if (spi == NULL) + { + mcerr("ERROR: Failed to initialize SPI port %d\n", SD_SPI_PORT); + return -ENODEV; + } + + rv = mmcsd_spislotinitialize(minor, SD_SLOT_NO, spi); + if (rv < 0) + { + mcerr("ERROR: Failed to bind SPI port %d to SD slot %d\n", + SD_SPI_PORT, SD_SLOT_NO); + return rv; + } + + spiinfo("INFO: mmcsd card has been initialized successfully\n"); + return OK; +} diff --git a/boards/arm/stm32/stm32f103-minimum/src/stm32_pcd8544.c b/boards/arm/stm32f1/stm32f103-minimum/src/stm32_pcd8544.c similarity index 98% rename from boards/arm/stm32/stm32f103-minimum/src/stm32_pcd8544.c rename to boards/arm/stm32f1/stm32f103-minimum/src/stm32_pcd8544.c index 1bff3d3426aa5..da8ff4b7a2230 100644 --- a/boards/arm/stm32/stm32f103-minimum/src/stm32_pcd8544.c +++ b/boards/arm/stm32f1/stm32f103-minimum/src/stm32_pcd8544.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f103-minimum/src/stm32_pcd8544.c + * boards/arm/stm32f1/stm32f103-minimum/src/stm32_pcd8544.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f1/stm32f103-minimum/src/stm32_pwm.c b/boards/arm/stm32f1/stm32f103-minimum/src/stm32_pwm.c new file mode 100644 index 0000000000000..8cdb0e0fe6eb0 --- /dev/null +++ b/boards/arm/stm32f1/stm32f103-minimum/src/stm32_pwm.c @@ -0,0 +1,127 @@ +/**************************************************************************** + * boards/arm/stm32f1/stm32f103-minimum/src/stm32_pwm.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32_pwm.h" +#include "stm32f103_minimum.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* PWM + * + * The stm32f103-minimum has no real on-board PWM devices, but the board can + * be configured to output a pulse train using TIM4 CH2. + * This pin is used by FSMC is connect to CN5 just for this purpose: + * + * PB0 ADC12_IN8/TIM3_CH3 + * + */ + +#define HAVE_PWM 1 + +#ifndef CONFIG_PWM +# undef HAVE_PWM +#endif + +#ifndef CONFIG_STM32_TIM3 +# undef HAVE_PWM +#endif + +#ifndef CONFIG_STM32_TIM3_PWM +# undef HAVE_PWM +#endif + +#if !defined(CONFIG_STM32_TIM3_CHANNEL) || CONFIG_STM32_TIM3_CHANNEL != STM32F103MINIMUM_PWMCHANNEL +# undef HAVE_PWM +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_pwm_setup + * + * Description: + * Initialize PWM and register the PWM device. + * + ****************************************************************************/ + +int stm32_pwm_setup(void) +{ +#ifdef HAVE_PWM + static bool initialized = false; + struct pwm_lowerhalf_s *pwm; + int ret; + + /* Have we already initialized? */ + + if (!initialized) + { + /* Call stm32_pwminitialize() to get an instance of the PWM interface */ + + pwm = stm32_pwminitialize(STM32F103MINIMUM_PWMTIMER); + if (!pwm) + { + aerr("ERROR: Failed to get the STM32 PWM lower half\n"); + return -ENODEV; + } + + /* Register the PWM driver at "/dev/pwm0" */ + + ret = pwm_register("/dev/pwm0", pwm); + if (ret < 0) + { + aerr("ERROR: pwm_register failed: %d\n", ret); + return ret; + } + + /* Now we are initialized */ + + initialized = true; + } + + return OK; +#else + return -ENODEV; +#endif +} diff --git a/boards/arm/stm32f1/stm32f103-minimum/src/stm32_rgbled.c b/boards/arm/stm32f1/stm32f103-minimum/src/stm32_rgbled.c new file mode 100644 index 0000000000000..5363f128f711e --- /dev/null +++ b/boards/arm/stm32f1/stm32f103-minimum/src/stm32_rgbled.c @@ -0,0 +1,185 @@ +/**************************************************************************** + * boards/arm/stm32f1/stm32f103-minimum/src/stm32_rgbled.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32_pwm.h" +#include "stm32f103_minimum.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +#define HAVE_RGBLED 1 + +#ifndef CONFIG_PWM +# undef HAVE_RGBLED +#endif + +#ifndef CONFIG_STM32_TIM1 +# undef HAVE_RGBLED +#endif + +#ifndef CONFIG_STM32_TIM2 +# undef HAVE_RGBLED +#endif + +#ifndef CONFIG_STM32_TIM4 +# undef HAVE_RGBLED +#endif + +#ifndef CONFIG_STM32_TIM1_PWM +# undef HAVE_RGBLED +#endif + +#ifndef CONFIG_STM32_TIM2_PWM +# undef HAVE_RGBLED +#endif + +#ifndef CONFIG_STM32_TIM4_PWM +# undef HAVE_RGBLED +#endif + +#if CONFIG_STM32_TIM1_CHANNEL != RGBLED_RPWMCHANNEL +# undef HAVE_PWM +#endif + +#if CONFIG_STM32_TIM2_CHANNEL != RGBLED_GPWMCHANNEL +# undef HAVE_PWM +#endif + +#if CONFIG_STM32_TIM4_CHANNEL != RGBLED_BPWMCHANNEL +# undef HAVE_PWM +#endif + +#ifdef HAVE_RGBLED + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_rgbled_setup + * + * Description: + * Initial for support of a connected RGB LED using PWM. + * + ****************************************************************************/ + +int stm32_rgbled_setup(void) +{ + static bool initialized = false; + struct pwm_lowerhalf_s *ledr; + struct pwm_lowerhalf_s *ledg; + struct pwm_lowerhalf_s *ledb; + struct pwm_info_s info; + int ret; + + /* Have we already initialized? */ + + if (!initialized) + { + /* Call stm32_pwminitialize() to get an instance of the PWM interface */ + + ledr = stm32_pwminitialize(RGBLED_RPWMTIMER); + if (!ledr) + { + lederr("ERROR: Failed to get the STM32 PWM lower half to LEDR\n"); + return -ENODEV; + } + + /* Define frequency and duty cycle */ + + info.frequency = 100; + info.channels[0].duty = 0; + + /* Initialize LED R */ + + ledr->ops->setup(ledr); + ledr->ops->start(ledr, &info); + + /* Call stm32_pwminitialize() to get an instance of the PWM interface */ + + ledg = stm32_pwminitialize(RGBLED_GPWMTIMER); + if (!ledg) + { + lederr("ERROR: Failed to get the STM32 PWM lower half to LEDG\n"); + return -ENODEV; + } + + /* Initialize LED G */ + + ledg->ops->setup(ledg); + ledg->ops->start(ledg, &info); + + /* Call stm32_pwminitialize() to get an instance of the PWM interface */ + + ledb = stm32_pwminitialize(RGBLED_BPWMTIMER); + if (!ledb) + { + lederr("ERROR: Failed to get the STM32 PWM lower half to LEDB\n"); + return -ENODEV; + } + + /* Initialize LED B */ + + ledb->ops->setup(ledb); + ledb->ops->start(ledb, &info); + + /* Register the RGB LED diver at "/dev/rgbled0" */ + + ret = rgbled_register("/dev/rgbled0", ledr, ledg, ledb, + RGBLED_RPWMCHANNEL, RGBLED_GPWMCHANNEL, + RGBLED_BPWMCHANNEL); + if (ret < 0) + { + lederr("ERROR: rgbled_register failed: %d\n", ret); + return ret; + } + + /* Now we are initialized */ + + initialized = true; + } + + return OK; +} + +#else +# error "HAVE_RGBLED is undefined" +#endif /* HAVE_RGBLED */ diff --git a/boards/arm/stm32f1/stm32f103-minimum/src/stm32_spi.c b/boards/arm/stm32f1/stm32f103-minimum/src/stm32_spi.c new file mode 100644 index 0000000000000..46f22b8038bda --- /dev/null +++ b/boards/arm/stm32f1/stm32f103-minimum/src/stm32_spi.c @@ -0,0 +1,285 @@ +/**************************************************************************** + * boards/arm/stm32f1/stm32f103-minimum/src/stm32_spi.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "arm_internal.h" +#include "chip.h" +#include "stm32.h" +#include "stm32f103_minimum.h" + +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_spidev_initialize + * + * Description: + * Called to configure SPI chip select GPIO pins for the HY-MiniSTM32 + * board. + * + ****************************************************************************/ + +void stm32_spidev_initialize(void) +{ + /* NOTE: Clocking for SPI1 and/or SPI2 was already provided in stm32_rcc.c. + * Configurations of SPI pins is performed in stm32_spi.c. + * Here, we only initialize chip select pins unique to the board + * architecture. + */ + +#ifdef CONFIG_MTD_W25 + stm32_configgpio(FLASH_SPI1_CS); /* FLASH chip select */ +#endif + +#ifdef CONFIG_CAN_MCP2515 + stm32_configgpio(GPIO_MCP2515_CS); /* MCP2515 chip select */ +#endif + +#ifdef CONFIG_CL_MFRC522 + stm32_configgpio(GPIO_CS_MFRC522); /* MFRC522 chip select */ +#endif + +#if defined(CONFIG_SENSORS_MAX6675) + stm32_configgpio(GPIO_MAX6675_CS); /* MAX6675 chip select */ +#endif + +#ifdef CONFIG_LCD_MAX7219 + stm32_configgpio(STM32_LCD_CS); /* MAX7219 chip select */ +#endif + +#ifdef CONFIG_LCD_ST7567 + stm32_configgpio(STM32_LCD_CS); /* ST7567 chip select */ +#endif + +#ifdef CONFIG_LCD_PCD8544 + stm32_configgpio(STM32_LCD_CS); /* ST7567 chip select */ +#endif + +#ifdef CONFIG_WL_NRF24L01 + stm32_configgpio(GPIO_NRF24L01_CS); /* nRF24L01 chip select */ +#endif + +#ifdef CONFIG_MMCSD_SPI + stm32_configgpio(GPIO_SDCARD_CS); /* SD/MMC Card chip select */ +#endif +} + +/**************************************************************************** + * Name: stm32_spi1/2select and stm32_spi1/2status + * + * Description: + * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status + * must be provided by board-specific logic. They are implementations of + * the select and status methods of the SPI interface defined by struct + * spi_ops_s (see include/nuttx/spi/spi.h). All other methods (including + * stm32_spibus_initialize()) are provided by common STM32 logic. + * To use this common SPI logic on your board: + * + * 1. Provide logic in stm32_boardinitialize() to configure SPI chip select + * pins. + * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() functions + * in your board-specific logic. These functions will perform chip + * selection and status operations using GPIOs in the way your board is + * configured. + * 3. Add a calls to stm32_spibus_initialize() in your low level + * application initialization logic + * 4. The handle returned by stm32_spibus_initialize() may then be used to + * bind the SPI driver to higher level logic (e.g., calling + * mmcsd_spislotinitialize(), for example, will bind the SPI driver to + * the SPI MMC/SD driver). + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_SPI1 +void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, + bool selected) +{ +#if defined(CONFIG_CAN_MCP2515) + if (devid == SPIDEV_CANBUS(0)) + { + stm32_gpiowrite(GPIO_MCP2515_CS, !selected); + } +#endif + +#if defined(CONFIG_CL_MFRC522) + if (devid == SPIDEV_CONTACTLESS(0)) + { + stm32_gpiowrite(GPIO_CS_MFRC522, !selected); + } +#endif + +#if defined(CONFIG_SENSORS_MAX6675) + if (devid == SPIDEV_TEMPERATURE(0)) + { + stm32_gpiowrite(GPIO_MAX6675_CS, !selected); + } +#endif + +#ifdef CONFIG_LCD_MAX7219 + if (devid == SPIDEV_DISPLAY(0)) + { + stm32_gpiowrite(STM32_LCD_CS, !selected); + } +#endif + +#ifdef CONFIG_LCD_PCD8544 + if (devid == SPIDEV_DISPLAY(0)) + { + stm32_gpiowrite(STM32_LCD_CS, !selected); + } +#endif + +#ifdef CONFIG_LCD_ST7567 + if (devid == SPIDEV_DISPLAY(0)) + { + stm32_gpiowrite(STM32_LCD_CS, !selected); + } +#endif + +#ifdef CONFIG_WL_NRF24L01 + if (devid == SPIDEV_WIRELESS(0)) + { + stm32_gpiowrite(GPIO_NRF24L01_CS, !selected); + } +#endif + +#ifdef CONFIG_MMCSD_SPI + if (devid == SPIDEV_MMCSD(0)) + { + stm32_gpiowrite(GPIO_SDCARD_CS, !selected); + } +#endif + +#ifdef CONFIG_MTD_W25 + stm32_gpiowrite(FLASH_SPI1_CS, !selected); +#endif +} + +uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) +{ + uint8_t status = 0; + +#ifdef CONFIG_WL_NRF24L01 + if (devid == SPIDEV_WIRELESS(0)) + { + status |= SPI_STATUS_PRESENT; + } +#endif + +#ifdef CONFIG_MMCSD_SPI + if (devid == SPIDEV_MMCSD(0)) + { + status |= SPI_STATUS_PRESENT; + } +#endif + + return status; +} +#endif + +#ifdef CONFIG_STM32_SPI2 +void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid, + bool selected) +{ +} + +uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} +#endif + +/**************************************************************************** + * Name: stm32_spi1cmddata + * + * Description: + * Set or clear the SH1101A A0 or SD1306 D/C n bit to select data (true) + * or command (false). This function must be provided by platform-specific + * logic. This is an implementation of the cmddata method of the SPI + * interface defined by struct spi_ops_s (see include/nuttx/spi/spi.h). + * + * Input Parameters: + * + * spi - SPI device that controls the bus the device that requires the CMD/ + * DATA selection. + * devid - If there are multiple devices on the bus, this selects which one + * to select cmd or data. NOTE: This design restricts, for example, + * one one SPI display per SPI bus. + * cmd - true: select command; false: select data + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_SPI_CMDDATA +#ifdef CONFIG_STM32_SPI1 +int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, + bool cmd) +{ +#ifdef CONFIG_LCD_ST7567 + if (devid == SPIDEV_DISPLAY(0)) + { + /* This is the Data/Command control pad which determines whether the + * data bits are data or a command. + */ + + stm32_gpiowrite(STM32_LCD_RS, !cmd); + + return OK; + } +#endif + +#ifdef CONFIG_LCD_PCD8544 + if (devid == SPIDEV_DISPLAY(0)) + { + /* This is the Data/Command control pad which determines whether the + * data bits are data or a command. + */ + + stm32_gpiowrite(STM32_LCD_CD, !cmd); + + return OK; + } +#endif + + return -ENODEV; +} +#endif +#endif + +#endif /* CONFIG_STM32_SPI1 || CONFIG_STM32_SPI2 */ diff --git a/boards/arm/stm32f1/stm32f103-minimum/src/stm32_usbdev.c b/boards/arm/stm32f1/stm32f103-minimum/src/stm32_usbdev.c new file mode 100644 index 0000000000000..812481439f930 --- /dev/null +++ b/boards/arm/stm32f1/stm32f103-minimum/src/stm32_usbdev.c @@ -0,0 +1,93 @@ +/**************************************************************************** + * boards/arm/stm32f1/stm32f103-minimum/src/stm32_usbdev.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include + +#include "arm_internal.h" +#include "stm32.h" +#include "stm32f103_minimum.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_usbinitialize + * + * Description: + * Called to setup USB-related GPIO pins for the STM32F103 Minimum board. + * + ****************************************************************************/ + +void stm32_usbinitialize(void) +{ + /* USB Soft Connect Pullup */ + + stm32_configgpio(GPIO_USB_PULLUP); +} + +/**************************************************************************** + * Name: stm32_usbpullup + * + * Description: + * If USB is supported and the board supports a pullup via GPIO (for USB + * software connect and disconnect), then the board software must provide + * stm32_pullup. See include/nuttx/usb/usbdev.h for additional description + * of this method. Alternatively, if no pull-up GPIO the following EXTERN + * can be redefined to be NULL. + * + ****************************************************************************/ + +int stm32_usbpullup(struct usbdev_s *dev, bool enable) +{ + usbtrace(TRACE_DEVPULLUP, (uint16_t)enable); + stm32_gpiowrite(GPIO_USB_PULLUP, enable); + return OK; +} + +/**************************************************************************** + * Name: stm32_usbsuspend + * + * Description: + * Board logic must provide the stm32_usbsuspend logic if the USBDEV driver + * is used. This function is called whenever the USB enters or leaves + * suspend mode. This is an opportunity for the board logic to shutdown + * clocks, power, etc. while the USB is suspended. + * + ****************************************************************************/ + +void stm32_usbsuspend(struct usbdev_s *dev, bool resume) +{ + uinfo("resume: %d\n", resume); +} diff --git a/boards/arm/stm32f1/stm32f103-minimum/src/stm32_usbmsc.c b/boards/arm/stm32f1/stm32f103-minimum/src/stm32_usbmsc.c new file mode 100644 index 0000000000000..d7e83b0581e7a --- /dev/null +++ b/boards/arm/stm32f1/stm32f103-minimum/src/stm32_usbmsc.c @@ -0,0 +1,71 @@ +/**************************************************************************** + * boards/arm/stm32f1/stm32f103-minimum/src/stm32_usbmsc.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include + +#include "stm32.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +#ifndef CONFIG_SYSTEM_USBMSC_DEVMINOR1 +# define CONFIG_SYSTEM_USBMSC_DEVMINOR1 0 +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_usbmsc_initialize + * + * Description: + * Perform architecture specific initialization of the USB MSC device. + * + ****************************************************************************/ + +int board_usbmsc_initialize(int port) +{ + /* If system/usbmsc is built as an NSH command, then SD slot should + * already have been initialized. + * In this case, there is nothing further to be done here. + */ + +#ifndef CONFIG_NSH_BUILTIN_APPS + return stm32_sdinitialize(CONFIG_SYSTEM_USBMSC_DEVMINOR1); +#else + return OK; +#endif +} diff --git a/boards/arm/stm32f1/stm32f103-minimum/src/stm32_userleds.c b/boards/arm/stm32f1/stm32f103-minimum/src/stm32_userleds.c new file mode 100644 index 0000000000000..96c7b06056852 --- /dev/null +++ b/boards/arm/stm32f1/stm32f103-minimum/src/stm32_userleds.c @@ -0,0 +1,102 @@ +/**************************************************************************** + * boards/arm/stm32f1/stm32f103-minimum/src/stm32_userleds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include + +#include "chip.h" +#include "stm32.h" +#include "stm32f103_minimum.h" + +#ifndef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* This array maps an LED number to GPIO pin configuration */ + +static const uint32_t g_ledcfg[BOARD_NLEDS] = +{ + GPIO_LED1, +}; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_userled_initialize + ****************************************************************************/ + +uint32_t board_userled_initialize(void) +{ + int i; + + /* Configure LED GPIOs for output */ + + for (i = 0; i < BOARD_NLEDS; i++) + { + stm32_configgpio(g_ledcfg[i]); + } + + return BOARD_NLEDS; +} + +/**************************************************************************** + * Name: board_userled + ****************************************************************************/ + +void board_userled(int led, bool ledon) +{ + if ((unsigned)led < BOARD_NLEDS) + { + stm32_gpiowrite(g_ledcfg[led], ledon); + } +} + +/**************************************************************************** + * Name: board_userled_all + ****************************************************************************/ + +void board_userled_all(uint32_t ledset) +{ + int i; + + /* Configure LED GPIOs for output */ + + for (i = 0; i < BOARD_NLEDS; i++) + { + stm32_gpiowrite(g_ledcfg[i], (ledset & (1 << i)) != 0); + } +} + +#endif /* !CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32f1/stm32f103-minimum/src/stm32_w25.c b/boards/arm/stm32f1/stm32f103-minimum/src/stm32_w25.c new file mode 100644 index 0000000000000..96b95da27caff --- /dev/null +++ b/boards/arm/stm32f1/stm32f103-minimum/src/stm32_w25.c @@ -0,0 +1,279 @@ +/**************************************************************************** + * boards/arm/stm32f1/stm32f103-minimum/src/stm32_w25.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include + +#ifdef CONFIG_STM32_SPI1 +# include +# include +# include +# include +#endif + +#include "stm32_spi.h" + +#include "stm32f103_minimum.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Debug ********************************************************************/ + +/* Non-standard debug that may be enabled just for testing the watchdog + * timer + */ + +#define W25_SPI_PORT 1 + +/* Configuration ************************************************************/ + +/* Can't support the W25 device if it SPI1 or W25 support is not enabled */ + +#define HAVE_W25 1 +#if !defined(CONFIG_STM32_SPI1) || !defined(CONFIG_MTD_W25) +# undef HAVE_W25 +#endif + +/* Can't support W25 features if mountpoints are disabled */ + +#if defined(CONFIG_DISABLE_MOUNTPOINT) +# undef HAVE_W25 +#endif + +/* Can't support both FAT and SMARTFS */ + +#if defined(CONFIG_FS_FAT) && defined(CONFIG_FS_SMARTFS) +# warning "Can't support both FAT and SMARTFS -- using FAT" +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_w25initialize + * + * Description: + * Initialize and register the W25 FLASH file system. + * + ****************************************************************************/ + +int stm32_w25initialize(int minor) +{ + int ret; +#ifdef HAVE_W25 + struct spi_dev_s *spi; + struct mtd_dev_s *mtd; + struct mtd_geometry_s geo; +#if defined(CONFIG_MTD_PARTITION_NAMES) + const char *partname = CONFIG_STM32F103MINIMUM_FLASH_PART_NAMES; +#endif + + /* Get the SPI port */ + + spi = stm32_spibus_initialize(W25_SPI_PORT); + if (!spi) + { + syslog(LOG_ERR, "ERROR: Failed to initialize SPI port %d\n", + W25_SPI_PORT); + return -ENODEV; + } + + /* Now bind the SPI interface to the W25 SPI FLASH driver */ + + mtd = w25_initialize(spi); + if (!mtd) + { + syslog(LOG_ERR, "ERROR: Failed to bind SPI port %d to the Winbond" + "W25 FLASH driver\n", W25_SPI_PORT); + return -ENODEV; + } + +#ifndef CONFIG_FS_SMARTFS + /* Register the MTD driver */ + + char path[32]; + snprintf(path, sizeof(path), "/dev/mtdblock%d", minor); + ret = register_mtddriver(path, mtd, 0755, NULL); + if (ret < 0) + { + syslog(LOG_ERR, + "ERROR: Failed to register the MTD driver %s, ret %d\n", + path, ret); + return ret; + } +#else + /* Initialize to provide SMARTFS on the MTD interface */ + + /* Get the geometry of the FLASH device */ + + ret = mtd->ioctl(mtd, MTDIOC_GEOMETRY, (unsigned long)((uintptr_t)&geo)); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: mtd->ioctl failed: %d\n", ret); + return ret; + } + +#ifdef CONFIG_STM32F103MINIMUM_FLASH_PART + { + int partno; + int partsize; + int partoffset; + int partszbytes; + int erasesize; + const char *partstring = CONFIG_STM32F103MINIMUM_FLASH_PART_LIST; + const char *ptr; + struct mtd_dev_s *mtd_part; + char partref[16]; + + /* Now create a partition on the FLASH device */ + + partno = 0; + ptr = partstring; + partoffset = 0; + + /* Get the Flash erase size */ + + erasesize = geo.erasesize; + + while (*ptr != '\0') + { + /* Get the partition size */ + + partsize = atoi(ptr); + partszbytes = (partsize << 10); /* partsize is defined in KB */ + + /* Check if partition size is bigger then erase block */ + + if (partszbytes < erasesize) + { + syslog(LOG_ERR, + "ERROR: Partition size is lesser than erasesize!\n"); + return -1; + } + + /* Check if partition size is multiple of erase block */ + + if ((partszbytes % erasesize) != 0) + { + syslog(LOG_ERR, + "ERROR: Partition size isn't multiple of erasesize!\n"); + return -1; + } + + mtd_part = mtd_partition(mtd, partoffset, partszbytes / erasesize); + partoffset += partszbytes / erasesize; + +#ifdef CONFIG_STM32F103MINIMUM_FLASH_CONFIG_PART + /* Test if this is the config partition */ + + if (CONFIG_STM32F103MINIMUM_FLASH_CONFIG_PART_NUMBER == partno) + { + /* Register the partition as the config device */ + + mtdconfig_register(mtd_part); + } + else +#endif + { + /* Now initialize a SMART Flash block device and bind it + * to the MTD device. + */ + +#if defined(CONFIG_MTD_SMART) && defined(CONFIG_FS_SMARTFS) + snprintf(partref, sizeof(partref), "p%d", partno); + smart_initialize(CONFIG_STM32F103MINIMUM_FLASH_MINOR, + mtd_part, partref); +#endif + } + + /* Set the partition name */ + +#if defined(CONFIG_MTD_PARTITION_NAMES) + if (!mtd_part) + { + syslog(LOG_ERR, "Error: failed to create partition %s\n", + partname); + return -1; + } + + mtd_setpartitionname(mtd_part, partname); + + /* Now skip to next name. We don't need to split the string here + * because the MTD partition logic will only display names up to + * the comma, thus allowing us to use a single static name + * in the code. + */ + + while (*partname != ',' && *partname != '\0') + { + /* Skip to next ',' */ + + partname++; + } + + if (*partname == ',') + { + partname++; + } +#endif + + /* Update the pointer to point to the next size in the list */ + + while ((*ptr >= '0') && (*ptr <= '9')) + { + ptr++; + } + + if (*ptr == ',') + { + ptr++; + } + + /* Increment the part number */ + + partno++; + } + } +#else /* CONFIG_STM32F103MINIMUM_FLASH_PART */ + + /* Configure the device with no partition support */ + + smart_initialize(CONFIG_STM32F103MINIMUM_FLASH_MINOR, mtd, NULL); + +#endif /* CONFIG_STM32F103MINIMUM_FLASH_PART */ +#endif /* CONFIG_FS_SMARTFS */ +#endif /* HAVE_W25 */ + + return OK; +} diff --git a/boards/arm/stm32/stm32f103-minimum/src/stm32f103_minimum.h b/boards/arm/stm32f1/stm32f103-minimum/src/stm32f103_minimum.h similarity index 99% rename from boards/arm/stm32/stm32f103-minimum/src/stm32f103_minimum.h rename to boards/arm/stm32f1/stm32f103-minimum/src/stm32f103_minimum.h index a3cac399ded8f..5270b996e1c83 100644 --- a/boards/arm/stm32/stm32f103-minimum/src/stm32f103_minimum.h +++ b/boards/arm/stm32f1/stm32f103-minimum/src/stm32f103_minimum.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f103-minimum/src/stm32f103_minimum.h + * boards/arm/stm32f1/stm32f103-minimum/src/stm32f103_minimum.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f1/stm32vldiscovery/CMakeLists.txt b/boards/arm/stm32f1/stm32vldiscovery/CMakeLists.txt new file mode 100644 index 0000000000000..82b0be5e77cee --- /dev/null +++ b/boards/arm/stm32f1/stm32vldiscovery/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32f1/stm32vldiscovery/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/arm/stm32/stm32vldiscovery/Kconfig b/boards/arm/stm32f1/stm32vldiscovery/Kconfig similarity index 100% rename from boards/arm/stm32/stm32vldiscovery/Kconfig rename to boards/arm/stm32f1/stm32vldiscovery/Kconfig diff --git a/boards/arm/stm32f1/stm32vldiscovery/configs/nsh/defconfig b/boards/arm/stm32f1/stm32vldiscovery/configs/nsh/defconfig new file mode 100644 index 0000000000000..dc5b5c596e92c --- /dev/null +++ b/boards/arm/stm32f1/stm32vldiscovery/configs/nsh/defconfig @@ -0,0 +1,59 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_DISABLE_ENVIRON is not set +# CONFIG_DISABLE_POSIX_TIMERS is not set +# CONFIG_NSH_DISABLEBG is not set +# CONFIG_NSH_DISABLESCRIPT is not set +# CONFIG_NSH_DISABLE_EXEC is not set +# CONFIG_NSH_DISABLE_EXIT is not set +# CONFIG_NSH_DISABLE_GET is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_LOSETUP is not set +# CONFIG_NSH_DISABLE_MKRD is not set +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_NSH_DISABLE_PUT is not set +# CONFIG_NSH_DISABLE_WGET is not set +# CONFIG_NSH_DISABLE_XD is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32vldiscovery" +CONFIG_ARCH_BOARD_STM32VL_DISCOVERY=y +CONFIG_ARCH_CHIP="stm32f1" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F100RB=y +CONFIG_ARCH_CHIP_STM32F1=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=2398 +CONFIG_BUILTIN=y +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_DEFAULT_SMALL=y +CONFIG_IDLETHREAD_STACKSIZE=128 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=768 +CONFIG_INTELHEX_BINARY=y +CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=4 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_PTHREAD_STACK_DEFAULT=128 +CONFIG_PTHREAD_STACK_MIN=128 +CONFIG_RAM_SIZE=8192 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_STDIO_BUFFER_SIZE=0 +CONFIG_STM32_BKP=y +CONFIG_STM32_JTAG_FULL_ENABLE=y +CONFIG_STM32_PWR=y +CONFIG_STM32_RTC=y +CONFIG_STM32_USART1=y +CONFIG_SYMTAB_ORDEREDBYNAME=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART1_RXBUFSIZE=128 +CONFIG_USART1_SERIAL_CONSOLE=y +CONFIG_USART1_TXBUFSIZE=128 diff --git a/boards/arm/stm32f1/stm32vldiscovery/include/board.h b/boards/arm/stm32f1/stm32vldiscovery/include/board.h new file mode 100644 index 0000000000000..cde0a062e8e30 --- /dev/null +++ b/boards/arm/stm32f1/stm32vldiscovery/include/board.h @@ -0,0 +1,142 @@ +/**************************************************************************** + * boards/arm/stm32f1/stm32vldiscovery/include/board.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_STM32_STM32VLDISCOVERY_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32_STM32VLDISCOVERY_INCLUDE_BOARD_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#ifndef __ASSEMBLY__ +# include +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Clocking *****************************************************************/ + +/* On-board crystal frequency is 8MHz (HSE) */ + +#define STM32_BOARD_XTAL 8000000ul + +/* PLL source is HSE / 1, + * PLL multiplier is 3: PLL output frequency is 8MHz (XTAL) x 3 = 24MHz + */ + +#define STM32_CFGR2_PREDIV1 RCC_CFGR2_PREDIV1d1 +#define STM32_CFGR_PLLSRC RCC_CFGR_PLLSRC +#define STM32_CFGR_PLLXTPRE 0 +#define STM32_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx3 +#define STM32_PLL_FREQUENCY (3 * STM32_BOARD_XTAL) + +/* Use the PLL and set the SYSCLK source to be the PLL */ + +#define STM32_SYSCLK_SW RCC_CFGR_SW_PLL +#define STM32_SYSCLK_SWS RCC_CFGR_SWS_PLL +#define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY + +/* AHB clock (HCLK) is SYSCLK (24MHz) */ + +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK +#define STM32_HCLK_FREQUENCY STM32_PLL_FREQUENCY + +/* APB2 clock (PCLK2) is HCLK (24MHz) */ + +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK +#define STM32_PCLK2_FREQUENCY STM32_HCLK_FREQUENCY + +/* APB2 timers (1, 15-17) will receive PCLK2. */ + +#define STM32_APB2_TIM1_CLKIN STM32_PCLK2_FREQUENCY +#define STM32_APB2_TIM15_CLKIN STM32_PCLK2_FREQUENCY +#define STM32_APB2_TIM16_CLKIN STM32_PCLK2_FREQUENCY +#define STM32_APB2_TIM17_CLKIN STM32_PCLK2_FREQUENCY + +/* APB1 clock (PCLK1) is HCLK (24MHz) */ + +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK +#define STM32_PCLK1_FREQUENCY STM32_HCLK_FREQUENCY + +/* APB1 timers (2-7, 12-14) will receive PCLK1. */ + +#define STM32_APB1_TIM2_CLKIN STM32_PCLK1_FREQUENCY +#define STM32_APB1_TIM3_CLKIN STM32_PCLK1_FREQUENCY +#define STM32_APB1_TIM4_CLKIN STM32_PCLK1_FREQUENCY +#define STM32_APB1_TIM5_CLKIN STM32_PCLK1_FREQUENCY +#define STM32_APB1_TIM6_CLKIN STM32_PCLK1_FREQUENCY +#define STM32_APB1_TIM7_CLKIN STM32_PCLK1_FREQUENCY +#define STM32_APB1_TIM12_CLKIN STM32_PCLK1_FREQUENCY +#define STM32_APB1_TIM13_CLKIN STM32_PCLK1_FREQUENCY +#define STM32_APB1_TIM14_CLKIN STM32_PCLK1_FREQUENCY + +/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx + * otherwise frequency is 2xAPBx. + * Note: TIM1,15-17 are on APB2, others on APB1 + */ + +#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM2_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM3_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM4_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM5_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM6_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM7_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY + +/* LED definitions **********************************************************/ + +/* It is assumed that a generic board has 1 LED. Thus only two different + * states can be shown. Statuses defined as "1" will light the LED, the + * ones defined as "0" will turn the LED off. + */ + +#define LED_STARTED 1 +#define LED_HEAPALLOCATE 1 +#define LED_IRQSENABLED 1 +#define LED_STACKCREATED 1 +#define LED_INIRQ 1 +#define LED_SIGNAL 1 +#define LED_ASSERTION 0 +#define LED_PANIC 0 + +/* Button definitions *******************************************************/ + +/* It is assumed that a generic board has 1 button. */ + +#define BUTTON_0 0 + +#define NUM_BUTTONS 1 + +#define BUTTON_0_BIT (1 << BUTTON_0) + +/* Alternate function pin selections ****************************************/ + +/* USART1 */ + +#define GPIO_USART1_TX GPIO_ADJUST_MODE(GPIO_USART1_TX_0, GPIO_MODE_50MHz) +#define GPIO_USART1_RX GPIO_USART1_RX_0 + +#endif /* __BOARDS_ARM_STM32_STM32VLDISCOVERY_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32f1/stm32vldiscovery/scripts/Make.defs b/boards/arm/stm32f1/stm32vldiscovery/scripts/Make.defs new file mode 100644 index 0000000000000..ae0bf8f97a444 --- /dev/null +++ b/boards/arm/stm32f1/stm32vldiscovery/scripts/Make.defs @@ -0,0 +1,41 @@ +############################################################################ +# boards/arm/stm32f1/stm32vldiscovery/scripts/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/.config +include $(TOPDIR)/tools/Config.mk +include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs + +LDSCRIPT = stm32vldiscovery.ld +ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) + +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32/stm32vldiscovery/scripts/stm32vldiscovery.ld b/boards/arm/stm32f1/stm32vldiscovery/scripts/stm32vldiscovery.ld similarity index 98% rename from boards/arm/stm32/stm32vldiscovery/scripts/stm32vldiscovery.ld rename to boards/arm/stm32f1/stm32vldiscovery/scripts/stm32vldiscovery.ld index d0ce202ebf6d0..0decb5ac94d45 100644 --- a/boards/arm/stm32/stm32vldiscovery/scripts/stm32vldiscovery.ld +++ b/boards/arm/stm32f1/stm32vldiscovery/scripts/stm32vldiscovery.ld @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32vldiscovery/scripts/stm32vldiscovery.ld + * boards/arm/stm32f1/stm32vldiscovery/scripts/stm32vldiscovery.ld * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f1/stm32vldiscovery/src/CMakeLists.txt b/boards/arm/stm32f1/stm32vldiscovery/src/CMakeLists.txt new file mode 100644 index 0000000000000..d28696c419692 --- /dev/null +++ b/boards/arm/stm32f1/stm32vldiscovery/src/CMakeLists.txt @@ -0,0 +1,28 @@ +# ############################################################################## +# boards/arm/stm32f1/stm32vldiscovery/src/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(SRCS stm32_boot.c stm32_bringup.c stm32_leds.c stm32_buttons.c) + +target_sources(board PRIVATE ${SRCS}) + +set_property(GLOBAL PROPERTY LD_SCRIPT + "${NUTTX_BOARD_DIR}/scripts/stm32vldiscovery.ld") diff --git a/boards/arm/stm32f1/stm32vldiscovery/src/Make.defs b/boards/arm/stm32f1/stm32vldiscovery/src/Make.defs new file mode 100644 index 0000000000000..2cac864f9dcd7 --- /dev/null +++ b/boards/arm/stm32f1/stm32vldiscovery/src/Make.defs @@ -0,0 +1,29 @@ +############################################################################ +# boards/arm/stm32f1/stm32vldiscovery/src/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +CSRCS = stm32_boot.c stm32_bringup.c stm32_leds.c stm32_buttons.c + +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32f1/stm32vldiscovery/src/stm32_boot.c b/boards/arm/stm32f1/stm32vldiscovery/src/stm32_boot.c new file mode 100644 index 0000000000000..dcf8e4960a11b --- /dev/null +++ b/boards/arm/stm32f1/stm32vldiscovery/src/stm32_boot.c @@ -0,0 +1,82 @@ +/**************************************************************************** + * boards/arm/stm32f1/stm32vldiscovery/src/stm32_boot.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include +#include + +#include "arm_internal.h" +#include "stm32vldiscovery.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_boardinitialize + * + * Description: + * All STM32 architectures must provide the following entry point. + * This entry point is called early in the initialization -- after all + * memory has been configured and mapped but before any devices have been + * initialized. + * + ****************************************************************************/ + +void stm32_boardinitialize(void) +{ + /* Configure on-board LEDs if LED support has been selected. */ + +#ifdef CONFIG_ARCH_LEDS + stm32_led_initialize(); +#endif +} + +/**************************************************************************** + * Name: board_late_initialize + * + * Description: + * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_late_initialize(). board_late_initialize() will + * be called immediately after up_initialize() is called and just before + * the initial application is started. This additional initialization + * phase may be used, for example, to initialize board-specific device + * drivers. + * + ****************************************************************************/ + +#ifdef CONFIG_BOARD_LATE_INITIALIZE +void board_late_initialize(void) +{ + /* Perform board-specific initialization */ + + stm32_bringup(); +} +#endif diff --git a/boards/arm/stm32f1/stm32vldiscovery/src/stm32_bringup.c b/boards/arm/stm32f1/stm32vldiscovery/src/stm32_bringup.c new file mode 100644 index 0000000000000..fa7c252e32629 --- /dev/null +++ b/boards/arm/stm32f1/stm32vldiscovery/src/stm32_bringup.c @@ -0,0 +1,96 @@ +/**************************************************************************** + * boards/arm/stm32f1/stm32vldiscovery/src/stm32_bringup.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#ifdef CONFIG_FS_PROCFS +# include +#endif + +#ifdef CONFIG_INPUT_BUTTONS +# include +#endif + +#ifdef CONFIG_USERLED +# include +#endif + +#include "stm32.h" +#include "stm32vldiscovery.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_bringup + * + * Description: + * Perform architecture-specific initialization + * + * CONFIG_BOARD_LATE_INITIALIZE=y : + * Called from board_late_initialize(). + * + ****************************************************************************/ + +int stm32_bringup(void) +{ + int ret = OK; + +#ifdef CONFIG_INPUT_BUTTONS + /* Register the BUTTON driver */ + + ret = btn_lower_initialize("/dev/buttons"); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: btn_lower_initialize() failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_USERLED + /* Register the LED driver */ + + ret = userled_lower_initialize("/dev/userleds"); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: userled_lower_initialize() failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_FS_PROCFS + /* Mount the procfs file system */ + + ret = nx_mount(NULL, "/proc", "procfs", 0, NULL); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to mount procfs at /proc: %d\n", ret); + } +#endif + + return ret; +} diff --git a/boards/arm/stm32f1/stm32vldiscovery/src/stm32_buttons.c b/boards/arm/stm32f1/stm32vldiscovery/src/stm32_buttons.c new file mode 100644 index 0000000000000..fe0a79c175428 --- /dev/null +++ b/boards/arm/stm32f1/stm32vldiscovery/src/stm32_buttons.c @@ -0,0 +1,111 @@ +/**************************************************************************** + * boards/arm/stm32f1/stm32vldiscovery/src/stm32_buttons.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include +#include + +#include "stm32vldiscovery.h" + +#ifdef CONFIG_ARCH_BUTTONS + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_button_initialize + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. + * + ****************************************************************************/ + +uint32_t board_button_initialize(void) +{ + stm32_configgpio(GPIO_BTN_0); /* Configure the GPIO pins as inputs. */ + return NUM_BUTTONS; +} + +/**************************************************************************** + * Name: board_buttons + ****************************************************************************/ + +uint32_t board_buttons(void) +{ + uint32_t ret = 0; + + ret = (stm32_gpioread(GPIO_BTN_0) == false ? 1 : 0); + + return ret; +} + +/**************************************************************************** + * Button support. + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. + * + * After board_button_initialize() has been called, board_buttons() may be + * called to collect the state of all buttons. board_buttons() returns an + * 32-bit bit set with each bit associated with a button. See the + * BUTTON_*_BIT and JOYSTICK_*_BIT definitions in board.h for the meaning + * of each bit. + * + * board_button_irq() may be called to register an interrupt handler that + * will be called when a button is depressed or released. The ID value is a + * button enumeration value that uniquely identifies a button resource. See + * the BUTTON_* and JOYSTICK_* definitions in board.h for the meaning of + * enumeration value. + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_IRQBUTTONS +int board_button_irq(int id, xcpt_t irqhandler, void *arg) +{ + int ret = -EINVAL; + + if (id == 0) + { + ret = stm32_gpiosetevent(GPIO_BTN_0, true, true, true, + irqhandler, arg); + } + + return ret; +} +#endif +#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/stm32f1/stm32vldiscovery/src/stm32_leds.c b/boards/arm/stm32f1/stm32vldiscovery/src/stm32_leds.c new file mode 100644 index 0000000000000..084e383263370 --- /dev/null +++ b/boards/arm/stm32f1/stm32vldiscovery/src/stm32_leds.c @@ -0,0 +1,79 @@ +/**************************************************************************** + * boards/arm/stm32f1/stm32vldiscovery/src/stm32_leds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32.h" +#include "stm32vldiscovery.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_led_initialize + ****************************************************************************/ + +#ifdef CONFIG_ARCH_LEDS +void stm32_led_initialize(void) +{ + stm32_configgpio(GPIO_LED1); /* Configure LED1 GPIO for output */ +} + +/**************************************************************************** + * Name: board_autoled_on + ****************************************************************************/ + +void board_autoled_on(int led) +{ + if (led == 1) + { + stm32_gpiowrite(GPIO_LED1, true); + } +} + +/**************************************************************************** + * Name: board_autoled_off + ****************************************************************************/ + +void board_autoled_off(int led) +{ + if (led == 0) + { + stm32_gpiowrite(GPIO_LED1, false); + } +} + +#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/stm32vldiscovery/src/stm32vldiscovery.h b/boards/arm/stm32f1/stm32vldiscovery/src/stm32vldiscovery.h similarity index 97% rename from boards/arm/stm32/stm32vldiscovery/src/stm32vldiscovery.h rename to boards/arm/stm32f1/stm32vldiscovery/src/stm32vldiscovery.h index 23898505690f0..d3b3191071251 100644 --- a/boards/arm/stm32/stm32vldiscovery/src/stm32vldiscovery.h +++ b/boards/arm/stm32f1/stm32vldiscovery/src/stm32vldiscovery.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32vldiscovery/src/stm32vldiscovery.h + * boards/arm/stm32f1/stm32vldiscovery/src/stm32vldiscovery.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f1/viewtool-stm32f107/CMakeLists.txt b/boards/arm/stm32f1/viewtool-stm32f107/CMakeLists.txt new file mode 100644 index 0000000000000..23add80a6ace8 --- /dev/null +++ b/boards/arm/stm32f1/viewtool-stm32f107/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32f1/viewtool-stm32f107/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/arm/stm32/viewtool-stm32f107/Kconfig b/boards/arm/stm32f1/viewtool-stm32f107/Kconfig similarity index 100% rename from boards/arm/stm32/viewtool-stm32f107/Kconfig rename to boards/arm/stm32f1/viewtool-stm32f107/Kconfig diff --git a/boards/arm/stm32f1/viewtool-stm32f107/configs/ft80x/defconfig b/boards/arm/stm32f1/viewtool-stm32f107/configs/ft80x/defconfig new file mode 100644 index 0000000000000..5cfee10bef73b --- /dev/null +++ b/boards/arm/stm32f1/viewtool-stm32f107/configs/ft80x/defconfig @@ -0,0 +1,44 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="viewtool-stm32f107" +CONFIG_ARCH_BOARD_VIEWTOOL_STM32F107=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f1" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F107VC=y +CONFIG_ARCH_CHIP_STM32F1=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=5483 +CONFIG_BUILTIN=y +CONFIG_EXAMPLES_FT80X=y +CONFIG_FS_PROCFS=y +CONFIG_HOST_WINDOWS=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LCD=y +CONFIG_LCD_FT80X=y +CONFIG_LCD_FT80X_AUDIO_GPIOSHUTDOWN=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=65536 +CONFIG_RAM_START=0x20000000 +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORKPRIORITY=192 +CONFIG_SCHED_HPWORKSTACKSIZE=1024 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=24 +CONFIG_START_MONTH=2 +CONFIG_STM32_JTAG_FULL_ENABLE=y +CONFIG_STM32_PWR=y +CONFIG_STM32_SPI1=y +CONFIG_STM32_USART1=y +CONFIG_SYSTEM_NSH=y +CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f1/viewtool-stm32f107/configs/highpri/defconfig b/boards/arm/stm32f1/viewtool-stm32f107/configs/highpri/defconfig new file mode 100644 index 0000000000000..40363260dd68a --- /dev/null +++ b/boards/arm/stm32f1/viewtool-stm32f107/configs/highpri/defconfig @@ -0,0 +1,39 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="viewtool-stm32f107" +CONFIG_ARCH_BOARD_VIEWTOOL_STM32F107=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f1" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F103VC=y +CONFIG_ARCH_CHIP_STM32F1=y +CONFIG_ARCH_HIPRI_INTERRUPT=y +CONFIG_ARCH_RAMVECTORS=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=5483 +CONFIG_HOST_WINDOWS=y +CONFIG_INIT_ENTRYPOINT="highpri_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=65536 +CONFIG_RAM_START=0x20000000 +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=192 +CONFIG_SCHED_HPWORKSTACKSIZE=1024 +CONFIG_START_DAY=22 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2013 +CONFIG_STM32_JTAG_FULL_ENABLE=y +CONFIG_STM32_PWR=y +CONFIG_STM32_TIM6=y +CONFIG_STM32_USART1=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART1_SERIAL_CONSOLE=y +CONFIG_VIEWTOOL_HIGHPRI=y diff --git a/boards/arm/stm32f1/viewtool-stm32f107/configs/netnsh/defconfig b/boards/arm/stm32f1/viewtool-stm32f107/configs/netnsh/defconfig new file mode 100644 index 0000000000000..ff5671048b632 --- /dev/null +++ b/boards/arm/stm32f1/viewtool-stm32f107/configs/netnsh/defconfig @@ -0,0 +1,72 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="viewtool-stm32f107" +CONFIG_ARCH_BOARD_VIEWTOOL_STM32F107=y +CONFIG_ARCH_CHIP="stm32f1" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F107VC=y +CONFIG_ARCH_CHIP_STM32F1=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=5483 +CONFIG_BUILTIN=y +CONFIG_ETH0_PHY_DP83848C=y +CONFIG_FS_PROCFS=y +CONFIG_HOST_WINDOWS=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_IOB_NBUFFERS=24 +CONFIG_LIBC_HOSTNAME="Viewtool-STM32F107" +CONFIG_NET=y +CONFIG_NETDB_DNSCLIENT=y +CONFIG_NETDB_DNSSERVER_NOADDR=y +CONFIG_NETINIT_NOMAC=y +CONFIG_NETINIT_THREAD=y +CONFIG_NETUTILS_DHCPC=y +CONFIG_NETUTILS_TELNETD=y +CONFIG_NETUTILS_TFTPC=y +CONFIG_NETUTILS_WEBCLIENT=y +CONFIG_NET_BROADCAST=y +CONFIG_NET_ICMP_SOCKET=y +CONFIG_NET_ICMPv6=y +CONFIG_NET_ICMPv6_NEIGHBOR=y +CONFIG_NET_ICMPv6_SOCKET=y +CONFIG_NET_IPv6=y +CONFIG_NET_MAX_LISTENPORTS=40 +CONFIG_NET_ROUTE=y +CONFIG_NET_TCP=y +CONFIG_NET_TCP_PREALLOC_CONNS=40 +CONFIG_NET_TCP_WRITE_BUFFERS=y +CONFIG_NET_UDP=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=65536 +CONFIG_RAM_START=0x20000000 +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=192 +CONFIG_SCHED_HPWORKSTACKSIZE=1024 +CONFIG_START_DAY=23 +CONFIG_STM32_ETHMAC=y +CONFIG_STM32_JTAG_FULL_ENABLE=y +CONFIG_STM32_PHYSR=16 +CONFIG_STM32_PHYSR_100MBPS=0x0000 +CONFIG_STM32_PHYSR_FULLDUPLEX=0x0004 +CONFIG_STM32_PHYSR_MODE=0x0004 +CONFIG_STM32_PHYSR_SPEED=0x0002 +CONFIG_STM32_PWR=y +CONFIG_STM32_RMII_EXTCLK=y +CONFIG_STM32_USART1=y +CONFIG_SYSTEM_NSH=y +CONFIG_SYSTEM_PING6=y +CONFIG_SYSTEM_PING=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f1/viewtool-stm32f107/configs/nsh/defconfig b/boards/arm/stm32f1/viewtool-stm32f107/configs/nsh/defconfig new file mode 100644 index 0000000000000..04627a445fcce --- /dev/null +++ b/boards/arm/stm32f1/viewtool-stm32f107/configs/nsh/defconfig @@ -0,0 +1,41 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="viewtool-stm32f107" +CONFIG_ARCH_BOARD_VIEWTOOL_STM32F107=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f1" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F107VC=y +CONFIG_ARCH_CHIP_STM32F1=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=5483 +CONFIG_BUILTIN=y +CONFIG_FS_PROCFS=y +CONFIG_HOST_WINDOWS=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=65536 +CONFIG_RAM_START=0x20000000 +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=192 +CONFIG_SCHED_HPWORKSTACKSIZE=1024 +CONFIG_START_DAY=21 +CONFIG_START_MONTH=9 +CONFIG_START_YEAR=2009 +CONFIG_STM32_JTAG_FULL_ENABLE=y +CONFIG_STM32_PWR=y +CONFIG_STM32_USART1=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f1/viewtool-stm32f107/configs/tcpblaster/defconfig b/boards/arm/stm32f1/viewtool-stm32f107/configs/tcpblaster/defconfig new file mode 100644 index 0000000000000..0feae7117d368 --- /dev/null +++ b/boards/arm/stm32f1/viewtool-stm32f107/configs/tcpblaster/defconfig @@ -0,0 +1,63 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="viewtool-stm32f107" +CONFIG_ARCH_BOARD_VIEWTOOL_STM32F107=y +CONFIG_ARCH_CHIP="stm32f1" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F107VC=y +CONFIG_ARCH_CHIP_STM32F1=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=5483 +CONFIG_BUILTIN=y +CONFIG_ETH0_PHY_DP83848C=y +CONFIG_EXAMPLES_TCPBLASTER=y +CONFIG_FS_PROCFS=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_IOB_NBUFFERS=50 +CONFIG_IOB_NCHAINS=12 +CONFIG_LIBC_HOSTNAME="Viewtool-STM32F107" +CONFIG_LIBM=y +CONFIG_NET=y +CONFIG_NETINIT_NOMAC=y +CONFIG_NETINIT_THREAD=y +CONFIG_NETUTILS_TELNETD=y +CONFIG_NET_ETH_PKTSIZE=1514 +CONFIG_NET_ICMP_SOCKET=y +CONFIG_NET_MAX_LISTENPORTS=40 +CONFIG_NET_ROUTE=y +CONFIG_NET_SOCKOPTS=y +CONFIG_NET_STATISTICS=y +CONFIG_NET_TCP=y +CONFIG_NET_TCP_PREALLOC_CONNS=40 +CONFIG_NET_TCP_WRITE_BUFFERS=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=65536 +CONFIG_RAM_START=0x20000000 +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_LPWORK=y +CONFIG_SCHED_LPWORKPRIORITY=120 +CONFIG_START_DAY=23 +CONFIG_STM32_ETHMAC=y +CONFIG_STM32_JTAG_FULL_ENABLE=y +CONFIG_STM32_PHYSR=16 +CONFIG_STM32_PHYSR_100MBPS=0x0000 +CONFIG_STM32_PHYSR_FULLDUPLEX=0x0004 +CONFIG_STM32_PHYSR_MODE=0x0004 +CONFIG_STM32_PHYSR_SPEED=0x0002 +CONFIG_STM32_PWR=y +CONFIG_STM32_RMII_EXTCLK=y +CONFIG_STM32_USART1=y +CONFIG_SYSTEM_NSH=y +CONFIG_SYSTEM_PING=y +CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/viewtool-stm32f107/include/board-stm32f103vct6.h b/boards/arm/stm32f1/viewtool-stm32f107/include/board-stm32f103vct6.h similarity index 98% rename from boards/arm/stm32/viewtool-stm32f107/include/board-stm32f103vct6.h rename to boards/arm/stm32f1/viewtool-stm32f107/include/board-stm32f103vct6.h index 3fa04fc724078..75e96c764593d 100644 --- a/boards/arm/stm32/viewtool-stm32f107/include/board-stm32f103vct6.h +++ b/boards/arm/stm32f1/viewtool-stm32f107/include/board-stm32f103vct6.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/viewtool-stm32f107/include/board-stm32f103vct6.h + * boards/arm/stm32f1/viewtool-stm32f107/include/board-stm32f103vct6.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/viewtool-stm32f107/include/board-stm32f107vct6.h b/boards/arm/stm32f1/viewtool-stm32f107/include/board-stm32f107vct6.h similarity index 98% rename from boards/arm/stm32/viewtool-stm32f107/include/board-stm32f107vct6.h rename to boards/arm/stm32f1/viewtool-stm32f107/include/board-stm32f107vct6.h index 4f88851d81dc5..ac40282bdcc68 100644 --- a/boards/arm/stm32/viewtool-stm32f107/include/board-stm32f107vct6.h +++ b/boards/arm/stm32f1/viewtool-stm32f107/include/board-stm32f107vct6.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/viewtool-stm32f107/include/board-stm32f107vct6.h + * boards/arm/stm32f1/viewtool-stm32f107/include/board-stm32f107vct6.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f1/viewtool-stm32f107/include/board.h b/boards/arm/stm32f1/viewtool-stm32f107/include/board.h new file mode 100644 index 0000000000000..dc37787be0cb0 --- /dev/null +++ b/boards/arm/stm32f1/viewtool-stm32f107/include/board.h @@ -0,0 +1,166 @@ +/**************************************************************************** + * boards/arm/stm32f1/viewtool-stm32f107/include/board.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_STM32_VIEWTOOL_STM32F107_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32_VIEWTOOL_STM32F107_INCLUDE_BOARD_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#ifndef __ASSEMBLY__ +# include +#endif + +/* Clocking *****************************************************************/ + +#if defined(CONFIG_ARCH_CHIP_STM32F107VC) +# include +#elif defined(CONFIG_ARCH_CHIP_STM32F103VC) +# include +#else +# error Unrecognized STM32 chip +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* LED definitions **********************************************************/ + +/* There are four LEDs on the ViewTool STM32F103/F107 board that can be + * controlled by software: LED1 through LED4. All pulled high and can be + * illuminated by driving the output to low + * + * LED1 PA6 + * LED2 PA7 + * LED3 PB12 + * LED4 PB13 + */ + +/* LED index values for use with board_userled() */ + +#define BOARD_LED1 0 +#define BOARD_LED2 1 +#define BOARD_LED3 2 +#define BOARD_LED4 3 +#define BOARD_NLEDS 4 + +/* LED bits for use with board_userled_all() */ + +#define BOARD_LED1_BIT (1 << BOARD_LED1) +#define BOARD_LED2_BIT (1 << BOARD_LED2) +#define BOARD_LED3_BIT (1 << BOARD_LED3) +#define BOARD_LED4_BIT (1 << BOARD_LED4) + +/* These LEDs are not used by the board port unless CONFIG_ARCH_LEDS is + * defined. In that case, the usage by the board port is defined in + * include/board.h and src/stm32_leds.c. The LEDs are used to encode + * OS-related events as follows: + * + * SYMBOL Val Meaning LED state + * LED1 LED2 LED3 LED4 + * ----------------- --- ----------------------- ---- ---- ---- ---- + */ +#define LED_STARTED 0 /* NuttX has been started ON OFF OFF OFF */ +#define LED_HEAPALLOCATE 1 /* Heap has been allocated OFF ON OFF OFF */ +#define LED_IRQSENABLED 2 /* Interrupts enabled ON ON OFF OFF */ +#define LED_STACKCREATED 3 /* Idle stack created OFF OFF ON OFF */ +#define LED_INIRQ 4 /* In an interrupt N/C N/C N/C GLOW */ +#define LED_SIGNAL 4 /* In a signal handler N/C N/C N/C GLOW */ +#define LED_ASSERTION 4 /* An assertion failed N/C N/C N/C GLOW */ +#define LED_PANIC 4 /* The system has crashed N/C N/C N/C FLASH */ +#undef LED_IDLE /* MCU is in sleep mode Not used */ + +/* After booting, LED1-3 are not longer used by the system and can be used + * for other purposes by the application (Of course, all LEDs are available + * to the application if CONFIG_ARCH_LEDS is not defined. + */ + +/* Buttons ******************************************************************/ + +/* All pulled high and will be sensed low when depressed. + * + * SW2 PC11 Needs J42 closed + * SW3 PC12 Needs J43 closed + * SW4 PA0 Needs J44 closed + */ + +#define BUTTON_SW2 0 +#define BUTTON_SW3 1 +#define BUTTON_SW4 2 +#define NUM_BUTTONS 3 + +#define BUTTON_SW2_BIT (1 << BUTTON_SW2) +#define BUTTON_SW3_BIT (1 << BUTTON_SW3) +#define BUTTON_SW4_BIT (1 << BUTTON_SW4) + +/* Alternate function pin selections (auto-aliased for new pinmap) */ + +/* USART1 */ + +#define GPIO_USART1_TX GPIO_ADJUST_MODE(GPIO_USART1_TX_0, GPIO_MODE_50MHz) +#define GPIO_USART1_RX GPIO_USART1_RX_0 + +/* SPI1 */ + +#define GPIO_SPI1_NSS GPIO_ADJUST_MODE(GPIO_SPI1_NSS_0, GPIO_MODE_50MHz) +#define GPIO_SPI1_SCK GPIO_ADJUST_MODE(GPIO_SPI1_SCK_0, GPIO_MODE_50MHz) +#define GPIO_SPI1_MISO GPIO_ADJUST_MODE(GPIO_SPI1_MISO_0, GPIO_MODE_50MHz) +#define GPIO_SPI1_MOSI GPIO_ADJUST_MODE(GPIO_SPI1_MOSI_0, GPIO_MODE_50MHz) + +/* MCO */ + +#define GPIO_MCO GPIO_ADJUST_MODE(GPIO_MCO_0, GPIO_MODE_50MHz) + +/* Ethernet (MII/RMII) */ + +#define GPIO_ETH_MDC GPIO_ADJUST_MODE(GPIO_ETH_MDC_0, GPIO_MODE_50MHz) +#define GPIO_ETH_MDIO GPIO_ADJUST_MODE(GPIO_ETH_MDIO_0, GPIO_MODE_50MHz) +#define GPIO_ETH_MII_COL GPIO_ETH_MII_COL_0 +#define GPIO_ETH_MII_CRS GPIO_ETH_MII_CRS_0 +#define GPIO_ETH_MII_RX_CLK GPIO_ETH_MII_RX_CLK_0 +#define GPIO_ETH_MII_RXD0 GPIO_ETH_MII_RXD0_0 +#define GPIO_ETH_MII_RXD1 GPIO_ETH_MII_RXD1_0 +#define GPIO_ETH_MII_RXD2 GPIO_ETH_MII_RXD2_0 +#define GPIO_ETH_MII_RXD3 GPIO_ETH_MII_RXD3_0 +#define GPIO_ETH_MII_RX_DV GPIO_ETH_MII_RX_DV_0 +#define GPIO_ETH_MII_RX_ER GPIO_ETH_MII_RX_ER_0 +#define GPIO_ETH_MII_TX_CLK GPIO_ETH_MII_TX_CLK_0 +#define GPIO_ETH_MII_TXD0 GPIO_ADJUST_MODE(GPIO_ETH_MII_TXD0_0, GPIO_MODE_50MHz) +#define GPIO_ETH_MII_TXD1 GPIO_ADJUST_MODE(GPIO_ETH_MII_TXD1_0, GPIO_MODE_50MHz) +#define GPIO_ETH_MII_TXD2 GPIO_ADJUST_MODE(GPIO_ETH_MII_TXD2_0, GPIO_MODE_50MHz) +#define GPIO_ETH_MII_TXD3 GPIO_ADJUST_MODE(GPIO_ETH_MII_TXD3_0, GPIO_MODE_50MHz) +#define GPIO_ETH_MII_TX_EN GPIO_ADJUST_MODE(GPIO_ETH_MII_TX_EN_0, GPIO_MODE_50MHz) +#define GPIO_ETH_RMII_CRS_DV GPIO_ETH_RMII_CRS_DV_0 +#define GPIO_ETH_RMII_REF_CLK GPIO_ETH_RMII_REF_CLK_0 +#define GPIO_ETH_RMII_RXD0 GPIO_ETH_RMII_RXD0_0 +#define GPIO_ETH_RMII_RXD1 GPIO_ETH_RMII_RXD1_0 +#define GPIO_ETH_RMII_TXD0 GPIO_ADJUST_MODE(GPIO_ETH_RMII_TXD0_0, GPIO_MODE_50MHz) +#define GPIO_ETH_RMII_TXD1 GPIO_ADJUST_MODE(GPIO_ETH_RMII_TXD1_0, GPIO_MODE_50MHz) +#define GPIO_ETH_RMII_TX_EN GPIO_ADJUST_MODE(GPIO_ETH_RMII_TX_EN_0, GPIO_MODE_50MHz) + +/* TIM6 has no GPIO pins (basic timer) */ + +#endif /* __BOARDS_ARM_STM32_VIEWTOOL_STM32F107_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32f1/viewtool-stm32f107/scripts/Make.defs b/boards/arm/stm32f1/viewtool-stm32f107/scripts/Make.defs new file mode 100644 index 0000000000000..6789123bb8cc6 --- /dev/null +++ b/boards/arm/stm32f1/viewtool-stm32f107/scripts/Make.defs @@ -0,0 +1,46 @@ +############################################################################ +# boards/arm/stm32f1/viewtool-stm32f107/scripts/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/.config +include $(TOPDIR)/tools/Config.mk +include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs + +ifeq ($(CONFIG_STM32_DFU),y) + LDSCRIPT = dfu.ld +else + LDSCRIPT = flash.ld +endif + +ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) + +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-gotoff.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32f1/viewtool-stm32f107/scripts/dfu.ld b/boards/arm/stm32f1/viewtool-stm32f107/scripts/dfu.ld new file mode 100644 index 0000000000000..a83768dd0966d --- /dev/null +++ b/boards/arm/stm32f1/viewtool-stm32f107/scripts/dfu.ld @@ -0,0 +1,118 @@ +/**************************************************************************** + * boards/arm/stm32f1/viewtool-stm32f107/scripts/dfu.ld + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +MEMORY +{ + flash (rx) : ORIGIN = 0x08003000, LENGTH = 208K + sram (rwx) : ORIGIN = 0x20000000, LENGTH = 64K +} + +OUTPUT_ARCH(arm) +EXTERN(_vectors) +ENTRY(_stext) +SECTIONS +{ + .text : { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > flash + + .init_section : { + _sinit = ABSOLUTE(.); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) + _einit = ABSOLUTE(.); + } > flash + + .ARM.extab : { + *(.ARM.extab*) + } > flash + + __exidx_start = ABSOLUTE(.); + .ARM.exidx : { + *(.ARM.exidx*) + } > flash + __exidx_end = ABSOLUTE(.); + + .tdata : { + _stdata = ABSOLUTE(.); + *(.tdata .tdata.* .gnu.linkonce.td.*); + _etdata = ABSOLUTE(.); + } > flash + + .tbss : { + _stbss = ABSOLUTE(.); + *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); + _etbss = ABSOLUTE(.); + } > flash + + _eronly = ABSOLUTE(.); + + /* The RAM vector table (if present) should lie at the beginning of SRAM */ + + .ram_vectors : { + *(.ram_vectors) + } > sram + + .data : { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > sram AT > flash + + .bss : { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(8); + _ebss = ABSOLUTE(.); + } > sram + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/stm32f1/viewtool-stm32f107/scripts/flash.ld b/boards/arm/stm32f1/viewtool-stm32f107/scripts/flash.ld new file mode 100644 index 0000000000000..904f9b611a6de --- /dev/null +++ b/boards/arm/stm32f1/viewtool-stm32f107/scripts/flash.ld @@ -0,0 +1,118 @@ +/**************************************************************************** + * boards/arm/stm32f1/viewtool-stm32f107/scripts/flash.ld + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +MEMORY +{ + flash (rx) : ORIGIN = 0x08000000, LENGTH = 256K + sram (rwx) : ORIGIN = 0x20000000, LENGTH = 64K +} + +OUTPUT_ARCH(arm) +EXTERN(_vectors) +ENTRY(_stext) +SECTIONS +{ + .text : { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > flash + + .init_section : { + _sinit = ABSOLUTE(.); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) + _einit = ABSOLUTE(.); + } > flash + + .ARM.extab : { + *(.ARM.extab*) + } > flash + + __exidx_start = ABSOLUTE(.); + .ARM.exidx : { + *(.ARM.exidx*) + } > flash + __exidx_end = ABSOLUTE(.); + + .tdata : { + _stdata = ABSOLUTE(.); + *(.tdata .tdata.* .gnu.linkonce.td.*); + _etdata = ABSOLUTE(.); + } > flash + + .tbss : { + _stbss = ABSOLUTE(.); + *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); + _etbss = ABSOLUTE(.); + } > flash + + _eronly = ABSOLUTE(.); + + /* The RAM vector table (if present) should lie at the beginning of SRAM */ + + .ram_vectors : { + *(.ram_vectors) + } > sram + + .data : { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > sram AT > flash + + .bss : { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(8); + _ebss = ABSOLUTE(.); + } > sram + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/stm32f1/viewtool-stm32f107/src/CMakeLists.txt b/boards/arm/stm32f1/viewtool-stm32f107/src/CMakeLists.txt new file mode 100644 index 0000000000000..c801fe9de8713 --- /dev/null +++ b/boards/arm/stm32f1/viewtool-stm32f107/src/CMakeLists.txt @@ -0,0 +1,79 @@ +# ############################################################################## +# boards/arm/stm32f1/viewtool-stm32f107/src/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(SRCS stm32_boot.c stm32_bringup.c stm32_leds.c stm32_spi.c) + +if(CONFIG_STM32_CAN_CHARDRIVER) + list(APPEND SRCS stm32_can.c) +endif() + +if(CONFIG_MMCSD) + list(APPEND SRCS stm32_mmcsd.c) +endif() + +if(CONFIG_STM32_OTGFS) + list(APPEND SRCS stm32_usbdev.c) +else() + if(CONFIG_STM32_USB) + list(APPEND SRCS stm32_usbdev.c) + endif() +endif() + +if(CONFIG_INPUT_ADS7843E) + list(APPEND SRCS stm32_ads7843e.c) +endif() + +if(CONFIG_LCD_SSD1289) + list(APPEND SRCS stm32_ssd1289.c) +endif() + +if(CONFIG_USBMSC) + list(APPEND SRCS stm32_usbmsc.c) +endif() + +if(CONFIG_ARCH_BUTTONS) + list(APPEND SRCS stm32_buttons.c) +endif() + +if(CONFIG_VIEWTOOL_HIGHPRI) + list(APPEND SRCS stm32_highpri.c) +endif() + +if(CONFIG_VIEWTOOL_FT80X_SPI1) + list(APPEND SRCS stm32_ft80x.c) +elseif(CONFIG_VIEWTOOL_FT80X_SPI2) + list(APPEND SRCS stm32_ft80x.c) +endif() + +if(CONFIG_VIEWTOOL_MAX3421E_SPI1) + list(APPEND SRCS stm32_max3421e.c) +elseif(CONFIG_VIEWTOOL_MAX3421E_SPI2) + list(APPEND SRCS stm32_max3421e.c) +endif() + +target_sources(board PRIVATE ${SRCS}) + +if(CONFIG_STM32_DFU) + set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/dfu.ld") +else() + set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/flash.ld") +endif() diff --git a/boards/arm/stm32f1/viewtool-stm32f107/src/Make.defs b/boards/arm/stm32f1/viewtool-stm32f107/src/Make.defs new file mode 100644 index 0000000000000..00ba8c4b620c6 --- /dev/null +++ b/boards/arm/stm32f1/viewtool-stm32f107/src/Make.defs @@ -0,0 +1,77 @@ +############################################################################ +# boards/arm/stm32f1/viewtool-stm32f107/src/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +CSRCS = stm32_boot.c stm32_bringup.c stm32_leds.c stm32_spi.c + +ifeq ($(CONFIG_STM32_CAN_CHARDRIVER),y) +CSRCS += stm32_can.c +endif + +ifeq ($(CONFIG_MMCSD),y) +CSRCS += stm32_mmcsd.c +endif + +ifeq ($(CONFIG_STM32_OTGFS),y) # F107 +CSRCS += stm32_usbdev.c +else +ifeq ($(CONFIG_STM32_USB),y) # F103 +CSRCS += stm32_usbdev.c +endif +endif + +ifeq ($(CONFIG_INPUT_ADS7843E),y) # F103 +CSRCS += stm32_ads7843e.c +endif + +ifeq ($(CONFIG_LCD_SSD1289),y) # F103 +CSRCS += stm32_ssd1289.c +endif + +ifeq ($(CONFIG_USBMSC),y) +CSRCS += stm32_usbmsc.c +endif + +ifeq ($(CONFIG_ARCH_BUTTONS),y) +CSRCS += stm32_buttons.c +endif + +ifeq ($(CONFIG_VIEWTOOL_HIGHPRI),y) +CSRCS += stm32_highpri.c +endif + +ifeq ($(CONFIG_VIEWTOOL_FT80X_SPI1),y) +CSRCS += stm32_ft80x.c +else ifeq ($(CONFIG_VIEWTOOL_FT80X_SPI2),y) +CSRCS += stm32_ft80x.c +endif + +ifeq ($(CONFIG_VIEWTOOL_MAX3421E_SPI1),y) +CSRCS += stm32_max3421e.c +else ifeq ($(CONFIG_VIEWTOOL_MAX3421E_SPI2),y) +CSRCS += stm32_max3421e.c +endif + +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/viewtool-stm32f107/src/stm32_ads7843e.c b/boards/arm/stm32f1/viewtool-stm32f107/src/stm32_ads7843e.c similarity index 99% rename from boards/arm/stm32/viewtool-stm32f107/src/stm32_ads7843e.c rename to boards/arm/stm32f1/viewtool-stm32f107/src/stm32_ads7843e.c index 99c2c0315eb79..9982aca8aa2bc 100644 --- a/boards/arm/stm32/viewtool-stm32f107/src/stm32_ads7843e.c +++ b/boards/arm/stm32f1/viewtool-stm32f107/src/stm32_ads7843e.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/viewtool-stm32f107/src/stm32_ads7843e.c + * boards/arm/stm32f1/viewtool-stm32f107/src/stm32_ads7843e.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f1/viewtool-stm32f107/src/stm32_boot.c b/boards/arm/stm32f1/viewtool-stm32f107/src/stm32_boot.c new file mode 100644 index 0000000000000..a5b6fbb767c25 --- /dev/null +++ b/boards/arm/stm32f1/viewtool-stm32f107/src/stm32_boot.c @@ -0,0 +1,99 @@ +/**************************************************************************** + * boards/arm/stm32f1/viewtool-stm32f107/src/stm32_boot.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include + +#include "arm_internal.h" +#include "viewtool_stm32f107.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_boardinitialize + * + * Description: + * All STM32 architectures must provide the following entry point. This + * entry point is called early in the initialization -- after all memory + * has been configured and mapped but before any devices have been + * initialized. + * + ****************************************************************************/ + +void stm32_boardinitialize(void) +{ + /* Configure SPI chip selects if 1) SPI is not disabled, and 2) the weak + * function stm32_spidev_initialize() has been brought into the link. + */ + +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || defined(CONFIG_STM32_SPI3) + if (stm32_spidev_initialize) + { + stm32_spidev_initialize(); + } +#endif + + /* Initialize USB is 1) USBDEV is selected, 2) the USB controller is not + * disabled, and 3) the weak function stm32_usbdev_initialize() has been + * brought into the build. + */ + +#if defined(CONFIG_STM32_OTGFS) && defined(CONFIG_USBDEV) + if (stm32_usbdev_initialize) + { + stm32_usbdev_initialize(); + } +#endif + + /* Configure on-board LEDs (unconditionally). */ + + stm32_led_initialize(); +} + +/**************************************************************************** + * Name: board_late_initialize + * + * Description: + * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_late_initialize(). board_late_initialize() will be + * called immediately after up_initialize() is called and just before the + * initial application is started. This additional initialization phase + * may be used, for example, to initialize board-specific device drivers. + * + ****************************************************************************/ + +#ifdef CONFIG_BOARD_LATE_INITIALIZE +void board_late_initialize(void) +{ + /* Perform board-specific initialization */ + + stm32_bringup(); +} +#endif diff --git a/boards/arm/stm32f1/viewtool-stm32f107/src/stm32_bringup.c b/boards/arm/stm32f1/viewtool-stm32f107/src/stm32_bringup.c new file mode 100644 index 0000000000000..a8ea0f1113525 --- /dev/null +++ b/boards/arm/stm32f1/viewtool-stm32f107/src/stm32_bringup.c @@ -0,0 +1,202 @@ +/**************************************************************************** + * boards/arm/stm32f1/viewtool-stm32f107/src/stm32_bringup.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#ifdef CONFIG_RTC_DRIVER +# include +# include "stm32_rtc.h" +#endif + +#include "viewtool_stm32f107.h" + +#ifdef CONFIG_SENSORS_MPL115A +#include "stm32_mpl115a.h" +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* Default MMC/SD SLOT number */ + +#ifdef HAVE_MMCSD +# if defined(CONFIG_NSH_MMCSDSLOTNO) && CONFIG_NSH_MMCSDSLOTNO != VIEWTOOL_MMCSD_SLOTNO +# error "Only one MMC/SD slot: VIEWTOOL_MMCSD_SLOTNO" +# undef CONFIG_NSH_MMCSDSLOTNO +# define CONFIG_NSH_MMCSDSLOTNO VIEWTOOL_MMCSD_SLOTNO +# endif + +# ifndef CONFIG_NSH_MMCSDSLOTNO +# define CONFIG_NSH_MMCSDSLOTNO VIEWTOOL_MMCSD_SLOTNO +# endif +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: rtc_driver_initialize + * + * Description: + * Initialize and register the RTC driver. + * + ****************************************************************************/ + +#ifdef HAVE_RTC_DRIVER +static int rtc_driver_initialize(void) +{ + struct rtc_lowerhalf_s *lower; + int ret; + + /* Instantiate the STM32 lower-half RTC driver */ + + lower = stm32_rtc_lowerhalf(); + if (lower == NULL) + { + serr("ERROR: Failed to instantiate the RTC lower-half driver\n"); + ret = -ENOMEM; + } + else + { + /* Bind the lower half driver and register the combined RTC driver + * as /dev/rtc0 + */ + + ret = rtc_initialize(0, lower); + if (ret < 0) + { + serr("ERROR: Failed to bind/register the RTC driver: %d\n", ret); + } + } + + return ret; +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_bringup + * + * Description: + * Perform architecture-specific initialization + * + * CONFIG_BOARD_LATE_INITIALIZE=y : + * Called from board_late_initialize(). + * + ****************************************************************************/ + +int stm32_bringup(void) +{ + int ret; + +#ifdef HAVE_RTC_DRIVER + ret = rtc_driver_initialize(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: rtc_driver_initialize failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_FS_PROCFS + /* Mount the procfs file system */ + + ret = nx_mount(NULL, STM32_PROCFS_MOUNTPOINT, "procfs", 0, NULL); + if (ret < 0) + { + serr("ERROR: Failed to mount procfs at %s: %d\n", + STM32_PROCFS_MOUNTPOINT, ret); + } +#endif + +#ifdef HAVE_MMCSD + ret = stm32_sdinitialize(CONFIG_NSH_MMCSDSLOTNO); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_sdinitialize failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_INPUT_ADS7843E + /* Initialize the touchscreen */ + + ret = stm32_tsc_setup(0); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_tsc_setup failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_STM32_CAN_CHARDRIVER + /* Initialize CAN and register the CAN driver. */ + + ret = stm32_can_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_can_setup failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_SENSORS_MPL115A + ret = board_mpl115a_initialize(0, 5); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_mpl115ainitialize failed: %d\n", ret); + } +#endif + +#if defined(CONFIG_VIEWTOOL_FT80X_SPI1) || defined(CONFIG_VIEWTOOL_FT80X_SPI2) + ret = stm32_ft80x_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_ft80x_setup failed: %d\n", ret); + } +#endif + +#if defined(CONFIG_VIEWTOOL_MAX3421E_SPI1) || defined(CONFIG_VIEWTOOL_MAX3421E_SPI2) + ret = stm32_max3421e_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_ft80x_setup failed: %d\n", ret); + } +#endif + + UNUSED(ret); + return OK; +} diff --git a/boards/arm/stm32f1/viewtool-stm32f107/src/stm32_buttons.c b/boards/arm/stm32f1/viewtool-stm32f107/src/stm32_buttons.c new file mode 100644 index 0000000000000..427e07f6c76d9 --- /dev/null +++ b/boards/arm/stm32f1/viewtool-stm32f107/src/stm32_buttons.c @@ -0,0 +1,153 @@ +/**************************************************************************** + * boards/arm/stm32f1/viewtool-stm32f107/src/stm32_buttons.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include +#include + +#include "viewtool_stm32f107.h" + +#ifdef CONFIG_ARCH_BUTTONS + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* Pin configuration for each STM3210E-EVAL button. This array is indexed by + * the BUTTON_* and JOYSTICK_* definitions in board.h + */ + +static const uint32_t g_buttons[NUM_BUTTONS] = +{ + GPIO_SW2, GPIO_SW3, GPIO_SW4 +}; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_button_initialize + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. + * + ****************************************************************************/ + +uint32_t board_button_initialize(void) +{ + int i; + + /* Configure the GPIO pins as inputs. NOTE that EXTI interrupts are + * configured for some pins but NOT used in this file + */ + + for (i = 0; i < NUM_BUTTONS; i++) + { + stm32_configgpio(g_buttons[i]); + } + + return NUM_BUTTONS; +} + +/**************************************************************************** + * Name: board_buttons + ****************************************************************************/ + +uint32_t board_buttons(void) +{ + uint32_t ret = 0; + int i; + + /* Check that state of each key */ + + for (i = 0; i < NUM_BUTTONS; i++) + { + /* A LOW value means that the key is pressed for most keys. The + * exception is the WAKEUP button. + */ + + bool released = stm32_gpioread(g_buttons[i]); + + /* Accumulate the set of depressed (not released) keys */ + + if (!released) + { + ret |= (1 << i); + } + } + + return ret; +} + +/**************************************************************************** + * Button support. + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. + * + * After board_button_initialize() has been called, board_buttons() may be + * called to collect the state of all buttons. board_buttons() returns an + * 32-bit bit set with each bit associated with a button. See the + * BUTTON_*_BIT and JOYSTICK_*_BIT definitions in board.h for the meaning + * of each bit. + * + * board_button_irq() may be called to register an interrupt handler that + * will be called when a button is depressed or released. The ID value is a + * button enumeration value that uniquely identifies a button resource. See + * the BUTTON_* and JOYSTICK_* definitions in board.h for the meaning of + * enumeration value. + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_IRQBUTTONS +int board_button_irq(int id, xcpt_t irqhandler, void *arg) +{ + int ret = -EINVAL; + + /* The following should be atomic */ + + if (id >= MIN_IRQBUTTON && id <= MAX_IRQBUTTON) + { + ret = stm32_gpiosetevent(g_buttons[id], true, true, true, + irqhandler, arg); + } + + return ret; +} +#endif +#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/stm32f1/viewtool-stm32f107/src/stm32_can.c b/boards/arm/stm32f1/viewtool-stm32f107/src/stm32_can.c new file mode 100644 index 0000000000000..672a1294a2b8d --- /dev/null +++ b/boards/arm/stm32f1/viewtool-stm32f107/src/stm32_can.c @@ -0,0 +1,103 @@ +/**************************************************************************** + * boards/arm/stm32f1/viewtool-stm32f107/src/stm32_can.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32.h" +#include "stm32_can.h" + +#ifdef CONFIG_CAN + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* The STM32F107VC supports CAN1 and CAN2 */ + +#if defined(CONFIG_STM32_CAN1) && defined(CONFIG_STM32_CAN2) +# warning "Both CAN1 and CAN2 are enabled. Assuming only CAN1." +# undef CONFIG_STM32_CAN2 +#endif + +#ifdef CONFIG_STM32_CAN1 +# define CAN_PORT 1 +#else +# define CAN_PORT 2 +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_can_setup + * + * Description: + * Initialize CAN and register the CAN device + * + ****************************************************************************/ + +int stm32_can_setup(void) +{ +#if defined(CONFIG_STM32_CAN1) || defined(CONFIG_STM32_CAN2) + struct can_dev_s *can; + int ret; + + /* Call stm32_caninitialize() to get an instance of the CAN interface */ + + can = stm32_caninitialize(CAN_PORT); + if (can == NULL) + { + canerr("ERROR: Failed to get CAN interface\n"); + return -ENODEV; + } + + /* Register the CAN driver at "/dev/can0" */ + + ret = can_register("/dev/can0", can); + if (ret < 0) + { + canerr("ERROR: can_register failed: %d\n", ret); + return ret; + } + + return OK; +#else + return -ENODEV; +#endif +} + +#endif /* CONFIG_CAN */ diff --git a/boards/arm/stm32/viewtool-stm32f107/src/stm32_ft80x.c b/boards/arm/stm32f1/viewtool-stm32f107/src/stm32_ft80x.c similarity index 99% rename from boards/arm/stm32/viewtool-stm32f107/src/stm32_ft80x.c rename to boards/arm/stm32f1/viewtool-stm32f107/src/stm32_ft80x.c index 59620fcab0fd9..cba254d55703d 100644 --- a/boards/arm/stm32/viewtool-stm32f107/src/stm32_ft80x.c +++ b/boards/arm/stm32f1/viewtool-stm32f107/src/stm32_ft80x.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/viewtool-stm32f107/src/stm32_ft80x.c + * boards/arm/stm32f1/viewtool-stm32f107/src/stm32_ft80x.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f1/viewtool-stm32f107/src/stm32_highpri.c b/boards/arm/stm32f1/viewtool-stm32f107/src/stm32_highpri.c new file mode 100644 index 0000000000000..d7a113d035b63 --- /dev/null +++ b/boards/arm/stm32f1/viewtool-stm32f107/src/stm32_highpri.c @@ -0,0 +1,277 @@ +/**************************************************************************** + * boards/arm/stm32f1/viewtool-stm32f107/src/stm32_highpri.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include + +#include +#include + +#include "arm_internal.h" +#include "ram_vectors.h" +#include "stm32_tim.h" + +#include "viewtool_stm32f107.h" + +#include + +#ifdef CONFIG_VIEWTOOL_HIGHPRI + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +#ifndef CONFIG_ARCH_CHIP_STM32F103VC +# warning This only only been verified with CONFIG_ARCH_CHIP_STM32F103VC +#endif + +#ifndef CONFIG_ARCH_HIPRI_INTERRUPT +# error CONFIG_ARCH_HIPRI_INTERRUPT is required +#endif + +#ifndef CONFIG_ARCH_RAMVECTORS +# error CONFIG_ARCH_RAMVECTORS is required +#endif + +#ifndef CONFIG_STM32_TIM6 +# error CONFIG_STM32_TIM6 is required +#endif + +#ifndef CONFIG_VIEWTOOL_TIM6_FREQUENCY +# warning CONFIG_VIEWTOOL_TIM6_FREQUENCY defaulting to STM32_APB1_TIM6_CLKIN +# define CONFIG_VIEWTOOL_TIM6_FREQUENCY STM32_APB1_TIM6_CLKIN +#endif + +#ifndef CONFIG_VIEWTOOL_TIM6_PERIOD +# warning CONFIG_VIEWTOOL_TIM6_PERIOD defaulting to 1MS +# define CONFIG_VIEWTOOL_TIM6_PERIOD (CONFIG_VIEWTOOL_TIM6_FREQUENCY / 1000) +#endif + +#ifndef CONFIG_ARCH_IRQPRIO +# error CONFIG_ARCH_IRQPRIO is required +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +struct highpri_s +{ + struct stm32_tim_dev_s *dev; /* TIM6 driver instance */ + volatile uint64_t basepri[16]; + volatile uint64_t handler; + volatile uint64_t thread; +}; + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static struct highpri_s g_highpri; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +static inline_function bool is_nesting_interrupt(void) +{ + return up_interrupt_context(); +} + +/**************************************************************************** + * Name: tim6_handler + * + * Description: + * This is the handler for the high speed TIM6 interrupt. + * + ****************************************************************************/ + +void tim6_handler(void) +{ + uint8_t basepri; + int index; + + /* Acknowledge the timer interrupt */ + + STM32_TIM_ACKINT(g_highpri.dev, ATIM_SR_UIF); + + /* Increment the count associated with the current basepri */ + + basepri = getbasepri(); + index = ((basepri >> 4) & 15); + g_highpri.basepri[index]++; + + /* Check if we are in an interrupt handle */ + + if (is_nesting_interrupt()) + { + g_highpri.handler++; + } + else + { + g_highpri.thread++; + } +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: highpri_main + * + * Description: + * Main entry point in into the high priority interrupt test. + * + ****************************************************************************/ + +int highpri_main(int argc, char *argv[]) +{ + struct stm32_tim_dev_s *dev; + uint64_t basepri[16]; + uint64_t handler; + uint64_t thread; + uint64_t total; + uint32_t seconds; + int prescaler; + int ret; + int i; + + printf("highpri_main: Started\n"); + + /* Configure basic timer TIM6 and enable interrupts */ + + dev = stm32_tim_init(6); + if (!dev) + { + fprintf(stderr, "highpri_main: ERROR: stm32_tim_init(6) failed\n"); + return EXIT_FAILURE; + } + + g_highpri.dev = dev; + + prescaler = STM32_TIM_SETCLOCK(dev, CONFIG_VIEWTOOL_TIM6_FREQUENCY); + printf("TIM6 CLKIN=%jd Hz, Frequency=%d Hz, prescaler=%d\n", + (uintmax_t)STM32_APB1_TIM6_CLKIN, CONFIG_VIEWTOOL_TIM6_FREQUENCY, + prescaler); + + STM32_TIM_SETPERIOD(dev, CONFIG_VIEWTOOL_TIM6_PERIOD); + printf("TIM6 period=%d cycles; interrupt rate=%d Hz\n", + CONFIG_VIEWTOOL_TIM6_PERIOD, + CONFIG_VIEWTOOL_TIM6_FREQUENCY / CONFIG_VIEWTOOL_TIM6_PERIOD); + + /* Attach TIM6 ram vector */ + + ret = arm_ramvec_attach(STM32_IRQ_TIM6, tim6_handler); + if (ret < 0) + { + fprintf(stderr, "highpri_main: ERROR: arm_ramvec_attach failed: %d\n", + ret); + return EXIT_FAILURE; + } + + /* Set the priority of the TIM6 interrupt vector */ + + ret = up_prioritize_irq(STM32_IRQ_TIM6, NVIC_SYSH_HIGH_PRIORITY); + if (ret < 0) + { + fprintf(stderr, "highpri_main: ERROR: up_prioritize_irq failed: %d\n", + ret); + return EXIT_FAILURE; + } + + /* Enable the timer interrupt at the NVIC and at TIM6 */ + + up_enable_irq(STM32_IRQ_TIM6); + STM32_TIM_ENABLEINT(dev, ATIM_DIER_UIE); + + /* Monitor interrupts */ + + seconds = 0; + for (; ; ) + { + /* Flush stdout and wait a bit */ + + fflush(stdout); + nxsched_sleep(1); + seconds++; + + /* Sample counts so that they are not volatile. Missing a count now + * and then is a normal consequence of this design. + */ + + for (i = 0; i < 16; i++) + { + basepri[i] = g_highpri.basepri[i]; + } + + handler = g_highpri.handler; + thread = g_highpri.thread; + + /* Then print out what is happening */ + + printf("Elapsed time: %" PRId32 " seconds\n\n", seconds); + for (i = 0, total = 0; i < 16; i++) + { + total += basepri[i]; + } + + if (total > 0) + { + for (i = 0; i < 16; i++) + { + if (basepri[i] > 0) + { + printf(" basepri[%02x]: %lld (%d%%)\n", + i << 4, basepri[i], + (int)((100 * basepri[i] + (total / 2)) / total)); + } + } + } + + total = handler + thread; + if (total > 0) + { + printf(" Handler: %lld (%d%%)\n", + handler, (int)((100*handler + (total / 2)) / total)); + printf(" Thread: %lld (%d%%)\n\n", + thread, (int)((100*thread + (total / 2)) / total)); + } + } + + return EXIT_SUCCESS; +} + +#endif /* CONFIG_VIEWTOOL_HIGHPRI */ diff --git a/boards/arm/stm32f1/viewtool-stm32f107/src/stm32_leds.c b/boards/arm/stm32f1/viewtool-stm32f107/src/stm32_leds.c new file mode 100644 index 0000000000000..51573cbff7560 --- /dev/null +++ b/boards/arm/stm32f1/viewtool-stm32f107/src/stm32_leds.c @@ -0,0 +1,280 @@ +/**************************************************************************** + * boards/arm/stm32f1/viewtool-stm32f107/src/stm32_leds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "stm32_gpio.h" +#include "viewtool_stm32f107.h" + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: led_onbits + * + * Description: + * Clear all LEDs to the bit encoded state + * + ****************************************************************************/ + +static void led_onbits(unsigned int clrbits) +{ + if ((clrbits & BOARD_LED1_BIT) != 0) + { + stm32_gpiowrite(GPIO_LED1, false); + } + + if ((clrbits & BOARD_LED2_BIT) != 0) + { + stm32_gpiowrite(GPIO_LED2, false); + } + + if ((clrbits & BOARD_LED3_BIT) != 0) + { + stm32_gpiowrite(GPIO_LED3, false); + } + + if ((clrbits & BOARD_LED4_BIT) != 0) + { + stm32_gpiowrite(GPIO_LED4, false); + } +} + +/**************************************************************************** + * Name: led_offbits + * + * Description: + * Clear all LEDs to the bit encoded state + * + ****************************************************************************/ + +static void led_offbits(unsigned int clrbits) +{ + if ((clrbits & BOARD_LED1_BIT) != 0) + { + stm32_gpiowrite(GPIO_LED1, true); + } + + if ((clrbits & BOARD_LED2_BIT) != 0) + { + stm32_gpiowrite(GPIO_LED2, true); + } + + if ((clrbits & BOARD_LED3_BIT) != 0) + { + stm32_gpiowrite(GPIO_LED3, true); + } + + if ((clrbits & BOARD_LED4_BIT) != 0) + { + stm32_gpiowrite(GPIO_LED4, true); + } +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_led_initialize + * + * Description: + * Configure LEDs. LEDs are left in the OFF state. + * + ****************************************************************************/ + +void stm32_led_initialize(void) +{ + /* Configure LED1-4 GPIOs for output. Initial state is OFF */ + + stm32_configgpio(GPIO_LED1); + stm32_configgpio(GPIO_LED2); + stm32_configgpio(GPIO_LED3); + stm32_configgpio(GPIO_LED4); +} + +/**************************************************************************** + * Name: board_autoled_on + * + * Description: + * Select the "logical" ON state: + * + * SYMBOL Val Meaning LED state + * LED1 LED2 LED3 LED4 + * ----------------- --- ----------------------- ---- ---- ---- ---- + * LED_STARTED 0 NuttX has been started ON OFF OFF OFF + * LED_HEAPALLOCATE 1 Heap has been allocated OFF ON OFF OFF + * LED_IRQSENABLED 2 Interrupts enabled ON ON OFF OFF + * LED_STACKCREATED 3 Idle stack created OFF OFF ON OFF + * LED_INIRQ 4 In an interrupt N/C N/C N/C GLOW + * LED_SIGNAL 4 In a signal handler N/C N/C N/C GLOW + * LED_ASSERTION 4 An assertion failed N/C N/C N/C GLOW + * LED_PANIC 4 The system has crashed N/C N/C N/C FLASH + * ED_IDLE MCU is in sleep mode Not used + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_LEDS +void board_autoled_on(int led) +{ + switch (led) + { + case 0: + led_offbits(BOARD_LED2_BIT | BOARD_LED3_BIT | BOARD_LED4_BIT); + led_onbits(BOARD_LED1_BIT); + break; + + case 1: + led_offbits(BOARD_LED1_BIT | BOARD_LED3_BIT | BOARD_LED4_BIT); + led_onbits(BOARD_LED2_BIT); + break; + + case 2: + led_offbits(BOARD_LED3_BIT | BOARD_LED4_BIT); + led_onbits(BOARD_LED1_BIT | BOARD_LED2_BIT); + break; + + case 3: + led_offbits(BOARD_LED1_BIT | BOARD_LED2_BIT | BOARD_LED4_BIT); + led_onbits(BOARD_LED3_BIT); + break; + + case 4: + stm32_gpiowrite(GPIO_LED4, false); + break; + } +} +#endif + +/**************************************************************************** + * Name: board_autoled_off + * + * Description: + * Select the "logical" OFF state: + * + * SYMBOL Val Meaning LED state + * LED1 LED2 LED3 LED4 + * ----------------- --- ----------------------- ---- ---- ---- ---- + * LED_STARTED 0 NuttX has been started ON OFF OFF OFF + * LED_HEAPALLOCATE 1 Heap has been allocated OFF ON OFF OFF + * LED_IRQSENABLED 2 Interrupts enabled ON ON OFF OFF + * LED_STACKCREATED 3 Idle stack created OFF OFF ON OFF + * LED_INIRQ 4 In an interrupt N/C N/C N/C GLOW + * LED_SIGNAL 4 In a signal handler N/C N/C N/C GLOW + * LED_ASSERTION 4 An assertion failed N/C N/C N/C GLOW + * LED_PANIC 4 The system has crashed N/C N/C N/C FLASH + * ED_IDLE MCU is in sleep mode Not used + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_LEDS +void board_autoled_off(int led) +{ + switch (led) + { + case 0: + case 1: + case 2: + case 3: + break; + + case 4: + stm32_gpiowrite(GPIO_LED4, true); + break; + } +} +#endif + +/**************************************************************************** + * Name: board_userled_initialize, board_userled, and board_userled_all + * + * Description: + * These interfaces allow user control of the board LEDs. + * + * If CONFIG_ARCH_LEDS is defined, then NuttX will control both on-board + * LEDs up until the completion of boot. The it will continue to control + * LED2; LED1 is available for application use. + * + * If CONFIG_ARCH_LEDS is not defined, then both LEDs are available for + * application use. + * + ****************************************************************************/ + +uint32_t board_userled_initialize(void) +{ + /* Already initialized by stm32_led_initialize */ + + return BOARD_NLEDS; +} + +void board_userled(int led, bool ledon) +{ + uint32_t pinset; + + switch (led) + { + case BOARD_LED1: + pinset = GPIO_LED1; + break; + + case BOARD_LED2: + pinset = GPIO_LED2; + break; + + case BOARD_LED3: + pinset = GPIO_LED3; + break; + + case BOARD_LED4: +#ifndef CONFIG_ARCH_LEDS + pinset = GPIO_LED4; + break; +#endif + default: + return; + } + + stm32_gpiowrite(pinset, !ledon); +} + +void board_userled_all(uint32_t ledset) +{ +#ifdef CONFIG_ARCH_LEDS + led_onbits(ledset & ~BOARD_LED4_BIT); + led_offbits(~(ledset | BOARD_LED4_BIT)); +#else + led_onbits(ledset); + led_offbits(~ledset); +#endif +} diff --git a/boards/arm/stm32/viewtool-stm32f107/src/stm32_max3421e.c b/boards/arm/stm32f1/viewtool-stm32f107/src/stm32_max3421e.c similarity index 99% rename from boards/arm/stm32/viewtool-stm32f107/src/stm32_max3421e.c rename to boards/arm/stm32f1/viewtool-stm32f107/src/stm32_max3421e.c index b7b6d1053be83..f397f0925237b 100644 --- a/boards/arm/stm32/viewtool-stm32f107/src/stm32_max3421e.c +++ b/boards/arm/stm32f1/viewtool-stm32f107/src/stm32_max3421e.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/viewtool-stm32f107/src/stm32_max3421e.c + * boards/arm/stm32f1/viewtool-stm32f107/src/stm32_max3421e.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f1/viewtool-stm32f107/src/stm32_mmcsd.c b/boards/arm/stm32f1/viewtool-stm32f107/src/stm32_mmcsd.c new file mode 100644 index 0000000000000..318d2badb5409 --- /dev/null +++ b/boards/arm/stm32f1/viewtool-stm32f107/src/stm32_mmcsd.c @@ -0,0 +1,121 @@ +/**************************************************************************** + * boards/arm/stm32f1/viewtool-stm32f107/src/stm32_mmcsd.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "stm32_sdio.h" +#include "viewtool_stm32f107.h" + +/* Only the STM32F103 supports the SDIO interface */ + +#ifdef CONFIG_ARCH_CHIP_STM32F103VC + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +#define HAVE_MMCSD 1 /* Assume that we have SD support */ +#define STM32_MMCSDSLOTNO 0 /* There is only one slot */ + +/* Can't support MMC/SD features if the SDIO peripheral is disabled */ + +#ifndef CONFIG_STM32_SDIO +# undef HAVE_MMCSD +#endif + +/* Can't support MMC/SD features if mountpoints are disabled */ + +#ifdef CONFIG_DISABLE_MOUNTPOINT +# undef HAVE_MMCSD +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_sdinitialize + * + * Description: + * Initialize the SPI-based SD card. Requires CONFIG_DISABLE_MOUNTPOINT=n + * and CONFIG_STM32_SDIO=y + * + ****************************************************************************/ + +int stm32_sdinitialize(int minor) +{ +#ifdef HAVE_MMCSD + struct sdio_dev_s *sdio; + int ret; + + /* Configure the card-detect GPIO */ +#warning REVISIT: Missing logic + + /* First, get an instance of the SDIO interface */ + + sdio = sdio_initialize(STM32_MMCSDSLOTNO); + if (!sdio) + { + ferr("ERROR: Failed to initialize SDIO slot %d\n", STM32_MMCSDSLOTNO); + return -ENODEV; + } + + finfo("Initialized SDIO slot %d\n", STM32_MMCSDSLOTNO); + + /* Now bind the SDIO interface to the MMC/SD driver */ + + ret = mmcsd_slotinitialize(minor, sdio); + if (ret != OK) + { + ferr("ERROR:"); + ferr("Failed to bind SDIO slot %d to the MMC/SD driver, minor=%d\n", + STM32_MMCSDSLOTNO, minor); + } + + finfo("Bound SDIO slot %d to the MMC/SD driver, minor=%d\n", + STM32_MMCSDSLOTNO, minor); + + /* Then let's guess and say that there is a card in the slot. I need to + * check to see if the M3 Wildfire board supports a GPIO to detect if there + * is a card in the slot. + */ +#warning REVISIT: Need to read the current state of the card-detect pin +#warning REVISIT: Need to support interrupts from the card-detect pin + sdio_mediachange(sdio, true); +#endif + return OK; +} + +#endif /* CONFIG_ARCH_CHIP_STM32F103VC */ diff --git a/boards/arm/stm32f1/viewtool-stm32f107/src/stm32_spi.c b/boards/arm/stm32f1/viewtool-stm32f107/src/stm32_spi.c new file mode 100644 index 0000000000000..04ec48f81d2d8 --- /dev/null +++ b/boards/arm/stm32f1/viewtool-stm32f107/src/stm32_spi.c @@ -0,0 +1,210 @@ +/**************************************************************************** + * boards/arm/stm32f1/viewtool-stm32f107/src/stm32_spi.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "arm_internal.h" +#include "chip.h" +#include "stm32.h" +#include "viewtool_stm32f107.h" + +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || defined(CONFIG_STM32_SPI3) + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_spidev_initialize + * + * Description: + * Called to configure SPI chip select GPIO pins for the Viewtool + * stm32f103/107 board. + * + ****************************************************************************/ + +void weak_function stm32_spidev_initialize(void) +{ + /* NOTE: Clocking for SPIx was already provided in stm32_rcc.c. + * Configurations of SPI pins is performed in stm32_spi.c. + * Here, we only initialize chip select pins unique to the board + * architecture. + */ + +#if defined(CONFIG_STM32_SPI2) && defined(CONFIG_INPUT_ADS7843E) + /* Configure the XPT2046 SPI2 CS pin as an output */ + + stm32_configgpio(GPIO_LCDTP_CS); +#endif + +#if defined(CONFIG_STM32_SPI3) && defined(CONFIG_SENSORS_MPL115A) + /* Configure the MPL115A SPI3 CS pin as an output */ + + stm32_configgpio(GPIO_MPL115A_CS); +#endif + +#if defined(CONFIG_VIEWTOOL_FT80X_SPI1) || defined(CONFIG_VIEWTOOL_FT80X_SPI2) + /* Configure the FT80x CS pin as an input */ + + stm32_configgpio(GPIO_FT80X_CS); +#endif + +#if defined(CONFIG_VIEWTOOL_MAX3421E_SPI1) || defined(CONFIG_VIEWTOOL_MAX3421E_SPI2) + /* Configure the MAX3421E CS pin as an input */ + + stm32_configgpio(GPIO_MAX3421E_CS); +#endif +} + +/**************************************************************************** + * Name: stm32_spi1/2/3select and stm32_spi1/2/3status + * + * Description: + * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status + * must be provided by board-specific logic. They are implementations of + * the select and status methods of the SPI interface defined by struct + * spi_ops_s (see include/nuttx/spi/spi.h). All other methods + * (including stm32_spibus_initialize()) are provided by common STM32 logic. + * To use this common SPI logic on your board: + * + * 1. Provide logic in stm32_boardinitialize() to configure SPI chip + * select pins. + * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() functions + * in your board-specific logic. These functions will perform chip + * selection and status operations using GPIOs in the way your board is + * configured. + * 3. Add a calls to stm32_spibus_initialize() in your low level + * application initialization logic + * 4. The handle returned by stm32_spibus_initialize() may then be used to + * bind the SPI driver to higher level logic (e.g., calling + * mmcsd_spislotinitialize(), for example, will bind the SPI driver to + * the SPI MMC/SD driver). + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_SPI1 +void stm32_spi1select(struct spi_dev_s *dev, + uint32_t devid, bool selected) +{ + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); + +#ifdef CONFIG_VIEWTOOL_FT80X_SPI1 + /* Select/de-select the FT80x */ + + if (devid == SPIDEV_DISPLAY(0)) + { + stm32_gpiowrite(GPIO_FT80X_CS, !selected); + } + else +#endif +#ifdef CONFIG_VIEWTOOL_MAX3421E_SPI1 + /* Select/de-select the MAX3421E */ + + if (devid == SPIDEV_USBHOST(0)) + { + stm32_gpiowrite(GPIO_MAX3421E_CS, !selected); + } + else +#endif + { + spierr("ERROR: Unrecognized devid: %08lx\n", (unsigned long)devid); + } +} + +uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} +#endif + +#ifdef CONFIG_STM32_SPI2 +void stm32_spi2select(struct spi_dev_s *dev, + uint32_t devid, bool selected) +{ + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); + +#ifdef CONFIG_INPUT_ADS7843E + /* Select/de-select the touchscreen */ + + if (devid == SPIDEV_TOUCHSCREEN(0)) + { + stm32_gpiowrite(GPIO_LCDTP_CS, !selected); + } + else +#endif +#ifdef CONFIG_VIEWTOOL_FT80X_SPI2 + /* Select/de-select the FT80x */ + + if (devid == SPIDEV_DISPLAY(0)) + { + stm32_gpiowrite(GPIO_FT80X_CS, !selected); + } + else +#endif +#ifdef CONFIG_VIEWTOOL_MAX3421E_SPI2 + /* Select/de-select the MAX3421E */ + + if (devid == SPIDEV_USBHOST(0)) + { + stm32_gpiowrite(GPIO_MAX3421E_CS, !selected); + } + else +#endif + { + spierr("ERROR: Unrecognized devid: %08lx\n", (unsigned long)devid); + } +} + +uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} +#endif + +#ifdef CONFIG_STM32_SPI3 +void stm32_spi3select(struct spi_dev_s *dev, + uint32_t devid, bool selected) +{ + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); +} + +uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} +#endif + +#endif /* CONFIG_STM32_SPI1 || CONFIG_STM32_SPI2 || CONFIG_STM32_SPI3*/ diff --git a/boards/arm/stm32f1/viewtool-stm32f107/src/stm32_ssd1289.c b/boards/arm/stm32f1/viewtool-stm32f107/src/stm32_ssd1289.c new file mode 100644 index 0000000000000..4d80b05f9d86f --- /dev/null +++ b/boards/arm/stm32f1/viewtool-stm32f107/src/stm32_ssd1289.c @@ -0,0 +1,568 @@ +/**************************************************************************** + * boards/arm/stm32f1/viewtool-stm32f107/src/stm32_ssd1289.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include + +#include "arm_internal.h" +#include "stm32.h" +#include "viewtool_stm32f107.h" + +#ifdef CONFIG_LCD_SSD1289 + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +#ifndef CONFIG_STM32_FSMC +# error "CONFIG_STM32_FSMC is required to use the LCD" +#endif + +/* Color depth and format */ + +#define LCD_BPP 16 +#define LCD_COLORFMT FB_FMT_RGB16_565 + +/* Display Resolution */ + +#if defined(CONFIG_LCD_LANDSCAPE) +# define LCD_XRES 320 +# define LCD_YRES 240 +#else +# define LCD_XRES 240 +# define LCD_YRES 320 +#endif + +#define LCD_BL_TIMER_PERIOD 8999 + +/* LCD is connected to the FSMC_Bank1_NOR/SRAM1 and NE1 is used as chip + * select signal + */ + +/* RS <==> A16 */ + +#define LCD_INDEX 0x60000000 /* RS = 0 */ +#define LCD_DATA 0x60020000 /* RS = 1 */ + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/* Low Level LCD access */ + +static void stm32_select(struct ssd1289_lcd_s *dev); +static void stm32_deselect(struct ssd1289_lcd_s *dev); +static void stm32_index(struct ssd1289_lcd_s *dev, uint8_t index); +#ifndef CONFIG_SSD1289_WRONLY +static uint16_t stm32_read(struct ssd1289_lcd_s *dev); +#endif +static void stm32_write(struct ssd1289_lcd_s *dev, uint16_t data); +static void stm32_backlight(struct ssd1289_lcd_s *dev, int power); + +static void stm32_extmemgpios(const uint16_t *gpios, int ngpios); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* LCD + * + * An LCD may be connected via J11. Only the STM32F103 supports the FSMC + * signals needed to drive the LCD. + * + * The LCD features an (1) HY32D module with built-in SSD1289 LCD controller, + * and (a) a XPT2046 touch screen controller. + * + * LCD Connector + * ------------- + * + * ------------------------- --------------------- --------------- + * Connector J11 GPIO CONFIGURATION(s) + * PIN SIGNAL LEGEND (F103 only) LCD Module + * --- --------- ----------- --------------------- --------------- + * 1 VDD_5 NC N/A 5V --- + * 2 GND GND N/A GND --- + * 3 PD14 DATA0 GPIO_NPS_D0 D0 HY32D + * 4 PD15 DATA1 GPIO_NPS_D1 D1 HY32D + * 5 PD0 DATA2 GPIO_NPS_D2 D2 HY32D + * 6 PD1 DATA3 GPIO_NPS_D3 D3 HY32D + * 7 PE7 DATA4 GPIO_NPS_D4 D4 HY32D + * 8 PE8 DATA5 GPIO_NPS_D5 D5 HY32D + * 9 PE9 DATA6 GPIO_NPS_D6 D6 HY32D + * 10 PE10 DATA7 GPIO_NPS_D7 D7 HY32D + * 11 PE11 DATA8 GPIO_NPS_D8 D8 HY32D + * 12 PE12 DATA9 GPIO_NPS_D9 D9 HY32D + * 13 PE13 DATA10 GPIO_NPS_D10 D10 HY32D + * 14 PE14 DATA11 GPIO_NPS_D11 D11 HY32D + * 15 PE15 DATA12 GPIO_NPS_D12 D12 HY32D + * 16 PD8 DATA13 GPIO_NPS_D13 D13 HY32D + * 17 PD9 DATA14 GPIO_NPS_D14 D14 HY32D + * 18 PD10 DATA15 GPIO_NPS_D15 D15 HY32D + * 19 (3) LCD_CS GPIO_NPS_NE1 CS HY32D + * 20 PD11 LCD_RS GPIO_NPS_A16 RS HY32D + * 21 PD5 LCD_R/W GPIO_NPS_NWE WR HY32D + * 22 PD4 LCD_RD GPIO_NPS_NOE RD HY32D + * 23 PB1 LCD_RESET (GPIO) RESET HY32D + * 24 N/C NC N/A TE (unused?) + * 25 VDD_3.3 BL_VCC N/A BLVDD CA6219 + * (Drives LCD backlight) + * 26 GND BL_GND N/A BLGND CA6219 + * 27 PB0 BL_PWM GPIO_TIM3_CH3OUT(2) BL_CNT CA6219 + * 28 PC5 LCDTP_IRQ (GPIO) TP_IRQ XPT2046 + * 29 PC4 LCDTP_CS (GPIO) TP_CS XPT2046 + * 30 PB13 LCDTP_CLK GPIO_SPI2_SCK TP_SCK XPT2046 + * 31 PB15 LCDTP_DIN GPIO_SPI2_MOSI TP_SI XPT2046 + * 32 PB14 LCDTP_DOUT GPIO_SPI2_MISO TP_SO XPT2046 + * 33 VDD_3.3 VDD_3.3 N/A 3.3V --- + * 34 GND GND N/A GND --- + * --- --------- ----------- --------------------- --------------- + * + * NOTES: + * 1) Only the F103 version of the board supports the FSMC + * 2) No remap + * 3) LCD_CS is controlled by J13 JUMPER4 (under the LCD unfortunately): + * + * 1->2 : PD7 (GPIO_NPS_NE1) enables the multiplexor : 1E\ enable input + * (active LOW) + * 3->4 : PD13 provides 1A0 input (1A1 is grounded). : 1A0 address input + * So will chip enable to either LCD_CS or + * Flash_CS. + * 5->6 : 1Y0 output to LCD_CS : 1Y0 address output + * 7->8 : 1Y1 output to Flash_CE : 1Y1 address output + * + * Truth Table: + * 1E\ 1A0 1A1 1Y0 1Y1 + * --- --- --- --- --- + * HI N/A N/A HI HI + * LO LO LO LO HI + * LO HI LO HI LO + */ + +const uint16_t fsmc_gpios[] = +{ + /* A16... A23. REVISIT: only A16 is used by the LCD */ + + GPIO_NPS_A16, GPIO_NPS_A17, GPIO_NPS_A18, GPIO_NPS_A19, GPIO_NPS_A20, + GPIO_NPS_A21, GPIO_NPS_A22, GPIO_NPS_A23, + + /* D0... D15 */ + + GPIO_NPS_D0, GPIO_NPS_D1, GPIO_NPS_D2, GPIO_NPS_D3, GPIO_NPS_D4, + GPIO_NPS_D5, GPIO_NPS_D6, GPIO_NPS_D7, GPIO_NPS_D8, GPIO_NPS_D9, + GPIO_NPS_D10, GPIO_NPS_D11, GPIO_NPS_D12, GPIO_NPS_D13, GPIO_NPS_D14, + GPIO_NPS_D15, + + /* NOE, NWE, and NE1 */ + + GPIO_NPS_NOE, GPIO_NPS_NWE, GPIO_NPS_NE1 +}; + +#define NGPIOS (sizeof(fsmc_gpios)/sizeof(uint16_t)) + +/* This is the driver state structure */ + +static struct ssd1289_lcd_s g_ssd1289 = +{ + .select = stm32_select, + .deselect = stm32_deselect, + .index = stm32_index, +#ifndef CONFIG_SSD1289_WRONLY + .read = stm32_read, +#endif + .write = stm32_write, + .backlight = stm32_backlight +}; + +/* The saved instance of the LCD driver */ + +static struct lcd_dev_s *g_ssd1289drvr; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_select + * + * Description: + * Select the LCD device + * + ****************************************************************************/ + +static void stm32_select(struct ssd1289_lcd_s *dev) +{ + /* Does not apply to this hardware */ +} + +/**************************************************************************** + * Name: stm32_deselect + * + * Description: + * De-select the LCD device + * + ****************************************************************************/ + +static void stm32_deselect(struct ssd1289_lcd_s *dev) +{ + /* Does not apply to this hardware */ +} + +/**************************************************************************** + * Name: stm32_index + * + * Description: + * Set the index register + * + ****************************************************************************/ + +static void stm32_index(struct ssd1289_lcd_s *dev, uint8_t index) +{ + putreg16((uint16_t)index, LCD_INDEX); +} + +/**************************************************************************** + * Name: stm32_read + * + * Description: + * Read LCD data (GRAM data or register contents) + * + ****************************************************************************/ + +#ifndef CONFIG_SSD1289_WRONLY +static uint16_t stm32_read(struct ssd1289_lcd_s *dev) +{ + return getreg16(LCD_DATA); +} +#endif + +/**************************************************************************** + * Name: stm32_write + * + * Description: + * Write LCD data (GRAM data or register contents) + * + ****************************************************************************/ + +static void stm32_write(struct ssd1289_lcd_s *dev, uint16_t data) +{ + putreg16((uint16_t)data, LCD_DATA); +} + +/**************************************************************************** + * Name: stm32_backlight + * + * Description: + * Enable/disable LCD panel power + * (0: full off - CONFIG_LCD_MAXPOWER: full on). + * Used here to set pwm duty on timer used for backlight. + * + ****************************************************************************/ + +static void stm32_backlight(struct ssd1289_lcd_s *dev, int power) +{ + DEBUGASSERT(power <= CONFIG_LCD_MAXPOWER); + + /* Set new power level */ + + if (power > 0) + { + uint32_t duty; + + /* Calculate the new backlight duty. It is a fraction of the timer + * period based on the ration of the current power setting to the + * maximum power setting. + */ + + duty = ((uint32_t)LCD_BL_TIMER_PERIOD * + (uint32_t)power) / CONFIG_LCD_MAXPOWER; + if (duty >= LCD_BL_TIMER_PERIOD) + { + duty = LCD_BL_TIMER_PERIOD - 1; + } + + putreg16((uint16_t)duty, STM32_TIM3_CCR2); + } + else + { + putreg16((uint16_t)0, STM32_TIM3_CCR2); + } +} + +static void init_lcd_backlight(void) +{ + uint16_t ccmr; + uint16_t ccer; + + /* Configure PB5 as TIM3 CH2 output */ + + stm32_configgpio(GPIO_TIM3_CH2OUT); + + /* Enable timer 3 clocking */ + + modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM3EN); + + /* Reset timer 3 */ + + modifyreg32(STM32_RCC_APB1RSTR, 0, RCC_APB1RSTR_TIM3RST); + modifyreg32(STM32_RCC_APB1RSTR, RCC_APB1RSTR_TIM3RST, 0); + + /* Reset the Counter Mode and set the clock division */ + + putreg16(0, STM32_TIM3_CR1); + + /* Set the Autoreload value */ + + putreg16(LCD_BL_TIMER_PERIOD, STM32_TIM3_ARR); + + /* Set the Prescaler value */ + + putreg16(0, STM32_TIM3_PSC); + + /* Generate an update event to reload the Prescaler value immediately */ + + putreg16(ATIM_EGR_UG, STM32_TIM3_EGR); + + /* Disable the Channel 2 */ + + ccer = getreg16(STM32_TIM3_CCER); + ccer &= ~ATIM_CCER_CC2E; + putreg16(ccer, STM32_TIM3_CCER); + + /* Select the Output Compare Mode Bits */ + + ccmr = getreg16(STM32_TIM3_CCMR1); + ccmr &= ATIM_CCMR1_OC2M_MASK; + ccmr |= (ATIM_CCMR_MODE_PWM1 << ATIM_CCMR1_OC2M_SHIFT); + + putreg16(0, STM32_TIM3_CCR2); + + /* Select the output polarity level == HIGH */ + + ccer &= ~ATIM_CCER_CC2P; + + /* Enable channel 2 */ + + ccer |= ATIM_CCER_CC2E; + + /* Write the timer configuration */ + + putreg16(ccmr, STM32_TIM3_CCMR1); + putreg16(ccer, STM32_TIM3_CCER); + + /* Set the auto preload enable bit */ + + modifyreg16(STM32_TIM3_CR1, 0, ATIM_CR1_ARPE); + + /* Enable Backlight Timer !!!! */ + + modifyreg16(STM32_TIM3_CR1, 0, ATIM_CR1_CEN); + + /* Dump timer3 registers */ + + lcdinfo("APB1ENR: %08x\n", getreg32(STM32_RCC_APB1ENR)); + lcdinfo("CR1: %04x\n", getreg32(STM32_TIM3_CR1)); + lcdinfo("CR2: %04x\n", getreg32(STM32_TIM3_CR2)); + lcdinfo("SMCR: %04x\n", getreg32(STM32_TIM3_SMCR)); + lcdinfo("DIER: %04x\n", getreg32(STM32_TIM3_DIER)); + lcdinfo("SR: %04x\n", getreg32(STM32_TIM3_SR)); + lcdinfo("EGR: %04x\n", getreg32(STM32_TIM3_EGR)); + lcdinfo("CCMR1: %04x\n", getreg32(STM32_TIM3_CCMR1)); + lcdinfo("CCMR2: %04x\n", getreg32(STM32_TIM3_CCMR2)); + lcdinfo("CCER: %04x\n", getreg32(STM32_TIM3_CCER)); + lcdinfo("CNT: %04x\n", getreg32(STM32_TIM3_CNT)); + lcdinfo("PSC: %04x\n", getreg32(STM32_TIM3_PSC)); + lcdinfo("ARR: %04x\n", getreg32(STM32_TIM3_ARR)); + lcdinfo("CCR1: %04x\n", getreg32(STM32_TIM3_CCR1)); + lcdinfo("CCR2: %04x\n", getreg32(STM32_TIM3_CCR2)); + lcdinfo("CCR3: %04x\n", getreg32(STM32_TIM3_CCR3)); + lcdinfo("CCR4: %04x\n", getreg32(STM32_TIM3_CCR4)); + lcdinfo("CCR4: %04x\n", getreg32(STM32_TIM3_CCR4)); + lcdinfo("CCR4: %04x\n", getreg32(STM32_TIM3_CCR4)); + lcdinfo("DMAR: %04x\n", getreg32(STM32_TIM3_DMAR)); +} + +/**************************************************************************** + * Name: stm32_selectlcd + * + * Description: + * Initialize the memory controller (FSMC) + * + ****************************************************************************/ + +static void stm32_selectlcd(void) +{ + /* Configure new GPIO state */ + + stm32_extmemgpios(fsmc_gpios, NGPIOS); + + /* Enable AHB clocking to the FSMC */ + + stm32_fsmc_enable(); + + /* Bank1 NOR/SRAM control register configuration */ + + putreg32(FSMC_BCR_SRAM | FSMC_BCR_MWID16 | FSMC_BCR_WREN, STM32_FSMC_BCR1); + + /* Bank1 NOR/SRAM timing register configuration */ + + putreg32( + FSMC_BTR_ADDSET(1) | FSMC_BTR_ADDHLD(1) | + FSMC_BTR_DATAST(2) | FSMC_BTR_BUSTURN(1) | + FSMC_BTR_CLKDIV(1) | FSMC_BTR_DATLAT(2) | + FSMC_BTR_ACCMODA, + STM32_FSMC_BTR1); + + /* As ext mode is not active the write timing is ignored!! */ + + putreg32(0xffffffff, STM32_FSMC_BWTR1); + + /* Enable the bank by setting the MBKEN bit */ + + putreg32(FSMC_BCR_MBKEN | FSMC_BCR_SRAM | FSMC_BCR_MWID16 | FSMC_BCR_WREN, + STM32_FSMC_BCR1); + + /* Configure the LCD RESET pin. + * Initial value will take the LCD out of reset + */ + + stm32_configgpio(GPIO_LCD_RESET); +} + +/**************************************************************************** + * Name: stm32_extmemgpios + * + * Description: + * Initialize GPIOs for NOR or SRAM + * + ****************************************************************************/ + +static void stm32_extmemgpios(const uint16_t *gpios, int ngpios) +{ + int i; + + /* Configure GPIOs */ + + for (i = 0; i < ngpios; i++) + { + stm32_configgpio(gpios[i]); + } +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_lcd_initialize + * + * Description: + * Initialize the LCD video hardware. + * The initial state of the LCD is fully initialized, display memory + * cleared, and the LCD ready to use, but with the power setting at 0 + * (full off). + * + ****************************************************************************/ + +int board_lcd_initialize(void) +{ + /* Only initialize the driver once */ + + if (!g_ssd1289drvr) + { + lcdinfo("Initializing\n"); + + /* Initialize the backlight */ + + init_lcd_backlight(); + + /* Configure GPIO pins and configure the FSMC to support the LCD */ + + stm32_selectlcd(); + + /* Configure and enable the LCD */ + + up_mdelay(50); + g_ssd1289drvr = ssd1289_lcdinitialize(&g_ssd1289); + if (!g_ssd1289drvr) + { + lcderr("ERROR: ssd1289_lcdinitialize failed\n"); + return -ENODEV; + } + } + + /* Turn the display off */ + + g_ssd1289drvr->setpower(g_ssd1289drvr, 0); + return OK; +} + +/**************************************************************************** + * Name: board_lcd_getdev + * + * Description: + * Return a a reference to the LCD object for the specified LCD. + * This allows support for multiple LCD devices. + * + ****************************************************************************/ + +struct lcd_dev_s *board_lcd_getdev(int lcddev) +{ + DEBUGASSERT(lcddev == 0); + return g_ssd1289drvr; +} + +/**************************************************************************** + * Name: board_lcd_uninitialize + * + * Description: + * Uninitialize the LCD support + * + ****************************************************************************/ + +void board_lcd_uninitialize(void) +{ + /* Turn the display off */ + + g_ssd1289drvr->setpower(g_ssd1289drvr, 0); +} + +#endif /* CONFIG_LCD_SSD1289 */ diff --git a/boards/arm/stm32f1/viewtool-stm32f107/src/stm32_usbdev.c b/boards/arm/stm32f1/viewtool-stm32f107/src/stm32_usbdev.c new file mode 100644 index 0000000000000..c94e99e18cdaa --- /dev/null +++ b/boards/arm/stm32f1/viewtool-stm32f107/src/stm32_usbdev.c @@ -0,0 +1,113 @@ +/**************************************************************************** + * boards/arm/stm32f1/viewtool-stm32f107/src/stm32_usbdev.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include + +#include "stm32_otgfs.h" +#include "viewtool_stm32f107.h" + +#if defined(CONFIG_STM32_OTGFS) || defined(CONFIG_STM32_USB) + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_usbdev_initialize + * + * Description: + * Called from stm32_boardinitialize very early in initialization to setup + * USB related GPIO pins for the Viewtool STM32F107 board. + * + ****************************************************************************/ + +void stm32_usbdev_initialize(void) +{ + /* The OTG FS has an internal soft pull-up. + * No GPIO configuration is required + */ + +#ifdef CONFIG_ARCH_CHIP_STM32F103VC + stm32_configgpio(GPIO_USB_PULLUP); +#endif +} + +/**************************************************************************** + * Name: stm32_usbpullup + * + * Description: + * If USB is supported and the board supports a pullup via GPIO (for USB + * software connect and disconnect), then the board software must provide + * stm32_pullup. See include/nuttx/usb/usbdev.h for additional + * description of this method. Alternatively, if no pull-up GPIO the + * following EXTERN can be redefined to be NULL. + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_CHIP_STM32F103VC +int stm32_usbpullup(struct usbdev_s *dev, bool enable) +{ + usbtrace(TRACE_DEVPULLUP, (uint16_t)enable); + stm32_gpiowrite(GPIO_USB_PULLUP, !enable); + return OK; +} +#endif + +/**************************************************************************** + * Name: stm32_usbsuspend + * + * Description: + * Board logic must provide the stm32_usbsuspend logic if the USBDEV driver + * is used. This function is called whenever the USB enters or leaves + * suspend mode. This is an opportunity for the board logic to shutdown + * clocks, power, etc. while the USB is suspended. + * + ****************************************************************************/ + +void stm32_usbsuspend(struct usbdev_s *dev, bool resume) +{ + uinfo("resume: %d\n", resume); +} + +#endif /* CONFIG_STM32_OTGFS || CONFIG_STM32_USB*/ diff --git a/boards/arm/stm32f1/viewtool-stm32f107/src/stm32_usbmsc.c b/boards/arm/stm32f1/viewtool-stm32f107/src/stm32_usbmsc.c new file mode 100644 index 0000000000000..2a2d8f2984798 --- /dev/null +++ b/boards/arm/stm32f1/viewtool-stm32f107/src/stm32_usbmsc.c @@ -0,0 +1,73 @@ +/**************************************************************************** + * boards/arm/stm32f1/viewtool-stm32f107/src/stm32_usbmsc.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include + +#include "stm32.h" +#include "viewtool_stm32f107.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +#ifndef CONFIG_SYSTEM_USBMSC_DEVMINOR1 +# define CONFIG_SYSTEM_USBMSC_DEVMINOR1 VIEWTOOL_MMCSD_SLOTNO +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_usbmsc_initialize + * + * Description: + * Perform architecture specific initialization as needed to establish + * the mass storage device that will be exported by the USB MSC device. + * + ****************************************************************************/ + +int board_usbmsc_initialize(int port) +{ + /* If system/usbmsc is built as an NSH command, then SD slot should + * already have been initialized. + * In this case, there is nothing further to be done here. + */ + +#if defined(HAVE_MMCSD) && !defined(CONFIG_NSH_BUILTIN_APPS) + return stm32_sdinitialize(CONFIG_SYSTEM_USBMSC_DEVMINOR1); +#else + return OK; +#endif +} diff --git a/boards/arm/stm32/viewtool-stm32f107/src/viewtool_stm32f107.h b/boards/arm/stm32f1/viewtool-stm32f107/src/viewtool_stm32f107.h similarity index 99% rename from boards/arm/stm32/viewtool-stm32f107/src/viewtool_stm32f107.h rename to boards/arm/stm32f1/viewtool-stm32f107/src/viewtool_stm32f107.h index be6c8199aff3c..35c858e0a753a 100644 --- a/boards/arm/stm32/viewtool-stm32f107/src/viewtool_stm32f107.h +++ b/boards/arm/stm32f1/viewtool-stm32f107/src/viewtool_stm32f107.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/viewtool-stm32f107/src/viewtool_stm32f107.h + * boards/arm/stm32f1/viewtool-stm32f107/src/viewtool_stm32f107.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f2/common/CMakeLists.txt b/boards/arm/stm32f2/common/CMakeLists.txt new file mode 100644 index 0000000000000..ada7f1b5fc03f --- /dev/null +++ b/boards/arm/stm32f2/common/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32f2/common/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(${NUTTX_DIR}/boards/arm/common/stm32 stm32_common) diff --git a/boards/arm/stm32f2/common/Kconfig b/boards/arm/stm32f2/common/Kconfig new file mode 100644 index 0000000000000..5c48f62a0258b --- /dev/null +++ b/boards/arm/stm32f2/common/Kconfig @@ -0,0 +1,6 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# + +source "boards/arm/common/stm32/Kconfig" diff --git a/boards/arm/stm32f2/common/Makefile b/boards/arm/stm32f2/common/Makefile new file mode 100644 index 0000000000000..2b5f1ae16b15d --- /dev/null +++ b/boards/arm/stm32f2/common/Makefile @@ -0,0 +1,39 @@ +############################################################################# +# boards/arm/stm32f2/common/Makefile +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################# + +include $(TOPDIR)/Make.defs + +STM32_BOARD_COMMON_DIR := $(TOPDIR)$(DELIM)boards$(DELIM)arm$(DELIM)common$(DELIM)stm32 +STM32_COMMON_SRCDIR := $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)common$(DELIM)stm32 + +include board/Make.defs +include $(STM32_BOARD_COMMON_DIR)$(DELIM)src$(DELIM)Make.defs + +DEPPATH += --dep-path board + +include $(TOPDIR)/boards/Board.mk + +ARCHSRCDIR = $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src +BOARDDIR = $(ARCHSRCDIR)$(DELIM)board +CFLAGS += ${INCDIR_PREFIX}$(BOARDDIR)$(DELIM)include +CFLAGS += ${INCDIR_PREFIX}$(STM32_COMMON_SRCDIR) +CXXFLAGS += ${INCDIR_PREFIX}$(STM32_COMMON_SRCDIR) diff --git a/boards/arm/stm32f2/emw3162/CMakeLists.txt b/boards/arm/stm32f2/emw3162/CMakeLists.txt new file mode 100644 index 0000000000000..3ae13f51fc402 --- /dev/null +++ b/boards/arm/stm32f2/emw3162/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32f2/emw3162/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/arm/stm32/emw3162/Kconfig b/boards/arm/stm32f2/emw3162/Kconfig similarity index 100% rename from boards/arm/stm32/emw3162/Kconfig rename to boards/arm/stm32f2/emw3162/Kconfig diff --git a/boards/arm/stm32f2/emw3162/configs/nsh/defconfig b/boards/arm/stm32f2/emw3162/configs/nsh/defconfig new file mode 100644 index 0000000000000..ba23a8e0b0ec9 --- /dev/null +++ b/boards/arm/stm32f2/emw3162/configs/nsh/defconfig @@ -0,0 +1,42 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="emw3162" +CONFIG_ARCH_BOARD_EMW3162=y +CONFIG_ARCH_CHIP="stm32f2" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F205RG=y +CONFIG_ARCH_CHIP_STM32F2=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_MM_REGIONS=2 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_USART1=y +CONFIG_SYSTEM_NSH=y +CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f2/emw3162/configs/wlan/defconfig b/boards/arm/stm32f2/emw3162/configs/wlan/defconfig new file mode 100644 index 0000000000000..a623c00de3555 --- /dev/null +++ b/boards/arm/stm32f2/emw3162/configs/wlan/defconfig @@ -0,0 +1,83 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_IEEE80211_BROADCOM_FWFILES is not set +# CONFIG_MMCSD_HAVE_CARDDETECT is not set +# CONFIG_MMCSD_MMCSUPPORT is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="emw3162" +CONFIG_ARCH_BOARD_EMW3162=y +CONFIG_ARCH_CHIP="stm32f2" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F205RG=y +CONFIG_ARCH_CHIP_STM32F2=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_DRIVERS_IEEE80211=y +CONFIG_DRIVERS_WIRELESS=y +CONFIG_EMW3162_WLAN=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_IEEE80211_BROADCOM_BCM43362=y +CONFIG_IEEE80211_BROADCOM_DMABUF_ALIGNMENT=16 +CONFIG_IEEE80211_BROADCOM_FULLMAC_SDIO=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBM=y +CONFIG_LINE_MAX=64 +CONFIG_MMCSD=y +CONFIG_MMCSD_SDIO=y +CONFIG_MM_REGIONS=2 +CONFIG_NET=y +CONFIG_NETDB_DNSCLIENT=y +CONFIG_NETDEV_LATEINIT=y +CONFIG_NETDEV_WIRELESS_IOCTL=y +CONFIG_NETINIT_DHCPC=y +CONFIG_NETINIT_DRIPADDR=0xc0a80001 +CONFIG_NETUTILS_DHCPC=y +CONFIG_NETUTILS_TELNETD=y +CONFIG_NET_BROADCAST=y +CONFIG_NET_ETH_PKTSIZE=800 +CONFIG_NET_GUARDSIZE=32 +CONFIG_NET_ICMP_SOCKET=y +CONFIG_NET_PKT=y +CONFIG_NET_TCP=y +CONFIG_NET_UDP=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_RTC_DATETIME=y +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_WAITPID=y +CONFIG_SDIO_BLOCKSETUP=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_STM32_DMA2=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_PWR=y +CONFIG_STM32_RTC=y +CONFIG_STM32_SDIO=y +CONFIG_STM32_SDIO_CARD=y +CONFIG_STM32_SDIO_PULLUP=y +CONFIG_STM32_USART1=y +CONFIG_SYSLOG_CHAR=y +CONFIG_SYSLOG_DEVPATH="/dev/ttyS0" +CONFIG_SYSTEM_NSH=y +CONFIG_SYSTEM_PING=y +CONFIG_USART1_SERIAL_CONSOLE=y +CONFIG_WIRELESS_WAPI=y +CONFIG_WIRELESS_WAPI_CMDTOOL=y diff --git a/boards/arm/stm32f2/emw3162/include/board.h b/boards/arm/stm32f2/emw3162/include/board.h new file mode 100644 index 0000000000000..04fe380ce64ce --- /dev/null +++ b/boards/arm/stm32f2/emw3162/include/board.h @@ -0,0 +1,218 @@ +/**************************************************************************** + * boards/arm/stm32f2/emw3162/include/board.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_STM32_EMW3162_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32_EMW3162_INCLUDE_BOARD_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#ifndef __ASSEMBLY__ +# include +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Clocking *****************************************************************/ + +/* The EMW3162 board features a single 26MHz crystal. + * + * This is the canonical configuration: + * System Clock source : PLL (HSE) + * SYSCLK(Hz) : 120000000 Determined by PLL + * configuration + * HCLK(Hz) : 120000000 (STM32_RCC_CFGR_HPRE) + * AHB Prescaler : 1 (STM32_RCC_CFGR_HPRE) + * APB1 Prescaler : 4 (STM32_RCC_CFGR_PPRE1) + * APB2 Prescaler : 2 (STM32_RCC_CFGR_PPRE2) + * HSE Frequency(Hz) : 26000000 (STM32_BOARD_XTAL) + * PLLM : 26 (STM32_PLLCFG_PLLM) + * PLLN : 240 (STM32_PLLCFG_PLLN) + * PLLP : 2 (STM32_PLLCFG_PLLP) + * PLLQ : 5 (STM32_PLLCFG_PLLQ) + * Main regulator output voltage : Scale1 mode Needed for high speed + * SYSCLK + * Flash Latency(WS) : 3 + * Prefetch Buffer : OFF + * Instruction cache : ON + * Data cache : ON + * Require 48MHz for USB OTG HS : Enabled + * SDIO and RNG clock + */ + +/* HSI - 16 MHz RC factory-trimmed + * LSI - 32 KHz RC + * HSE - On-board crystal frequency is 26MHz + * LSE - 32.768 kHz + */ + +#define STM32_BOARD_XTAL 26000000ul + +#define STM32_HSI_FREQUENCY 16000000ul +#define STM32_LSI_FREQUENCY 32000 +#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL +#define STM32_LSE_FREQUENCY 32768 + +/* Main PLL Configuration. + * + * PLL source is HSE + * PLL_VCO = (STM32_HSE_FREQUENCY / PLLM) * PLLN + * = (26,000,000 / 26) * 240 + * = 240,000,000 + * SYSCLK = PLL_VCO / PLLP + * = 240,000,000 / 2 = 120,000,000 + * USB OTG FS, SDIO and RNG Clock + * = PLL_VCO / PLLQ + * = 48,000,000 + */ + +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(26) +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(240) +#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_2 +#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(5) + +#define STM32_SYSCLK_FREQUENCY 120000000ul + +/* AHB clock (HCLK) is SYSCLK (120MHz) */ + +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY + +/* APB1 clock (PCLK1) is HCLK/4 (30MHz) */ + +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd4 /* PCLK1 = HCLK / 4 */ +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/4) + +/* APB2 clock (PCLK2) is HCLK/2 (60MHz) */ + +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLKd2 /* PCLK2 = HCLK / 2 */ +#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/2) + +/* LED definitions **********************************************************/ + +/* LED index values for use with board_userled() */ + +#define BOARD_LED1 0 +#define BOARD_NLEDS 1 + +/* LED bits for use with board_userled_all() */ + +#define BOARD_LED1_BIT (1 << BOARD_LED1) + +/* These LEDs are not used by the board port unless CONFIG_ARCH_LEDS is + * defined. In that case, the usage by the board port is defined in + * include/board.h and src/sam_autoleds.c. The LEDs are used to encode + * OS-related events as follows: + * + * ------------------- ---------------------------- ------ + * SYMBOL Meaning LED + * ------------------- ---------------------------- ------ + */ + +#define LED_STARTED 0 /* NuttX has been started OFF */ +#define LED_HEAPALLOCATE 0 /* Heap has been allocated OFF */ +#define LED_IRQSENABLED 0 /* Interrupts enabled OFF */ +#define LED_STACKCREATED 1 /* Idle stack created ON */ +#define LED_INIRQ 2 /* In an interrupt N/C */ +#define LED_SIGNAL 2 /* In a signal handler N/C */ +#define LED_ASSERTION 2 /* An assertion failed N/C */ +#define LED_PANIC 3 /* The system has crashed FLASH */ +#undef LED_IDLE /* MCU is in sleep mode Not used */ + +/* Thus if LED is statically on, NuttX has successfully booted and is, + * apparently, running normally. If LED is flashing at approximately + * 2Hz, then a fatal error has been detected and the system has halted. + */ + +/* Alternate function pin selections ****************************************/ + +/* UART1 */ + +#ifdef CONFIG_STM32_USART1 +# define GPIO_USART1_RX (GPIO_USART1_RX_1|GPIO_SPEED_100MHz) +# define GPIO_USART1_TX (GPIO_USART1_TX_1|GPIO_SPEED_100MHz) +#endif + +/* MCO1 */ + +#define GPIO_MCO1 (GPIO_MCO1_0|GPIO_SPEED_100MHz) + +/* SDIO */ + +#define GPIO_SDIO_CK (GPIO_SDIO_CK_0|GPIO_SPEED_50MHz) +#define GPIO_SDIO_CMD (GPIO_SDIO_CMD_0|GPIO_SPEED_50MHz) +#define GPIO_SDIO_D0 (GPIO_SDIO_D0_0|GPIO_SPEED_50MHz) +#define GPIO_SDIO_D1 (GPIO_SDIO_D1_0|GPIO_SPEED_50MHz) +#define GPIO_SDIO_D2 (GPIO_SDIO_D2_0|GPIO_SPEED_50MHz) +#define GPIO_SDIO_D3 (GPIO_SDIO_D3_0|GPIO_SPEED_50MHz) + +/* SDIO definitions *********************************************************/ + +/* Note that slower clocking is required when DMA is disabled in order + * to avoid RX overrun/TX underrun errors due to delayed responses + * to service FIFOs in interrupt driven mode. + * + * These values have not been tuned!!! + * + * SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(118+2)=400 KHz + */ + +#define SDIO_INIT_CLKDIV (118 << SDIO_CLKCR_CLKDIV_SHIFT) + +/* DMA ON: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(1+2)=16 MHz + * DMA OFF: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(2+2)=12 MHz + */ + +#ifdef CONFIG_SDIO_DMA +# define SDIO_MMCXFR_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT) +#else +# define SDIO_MMCXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT) +#endif + +/* DMA ON: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(1+2)=16 MHz + * DMA OFF: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(2+2)=12 MHz + */ + +#ifdef CONFIG_SDIO_DMA +# define SDIO_SDXFR_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT) +#else +# define SDIO_SDXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT) +#endif + +/* DMA Channel/Stream Selections ********************************************/ + +/* Stream selections are arbitrary for now but might become important in the + * future if we set aside more DMA channels/streams. + * + * SDIO DMA + * DMAMAP_SDIO_1 = Channel 4, Stream 3 + * DMAMAP_SDIO_2 = Channel 4, Stream 6 + */ + +#define DMAMAP_SDIO DMAMAP_SDIO_1 + +#endif /* __BOARDS_ARM_STM32_EMW3162_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32f2/emw3162/scripts/Make.defs b/boards/arm/stm32f2/emw3162/scripts/Make.defs new file mode 100644 index 0000000000000..0f1c1fb18ddc2 --- /dev/null +++ b/boards/arm/stm32f2/emw3162/scripts/Make.defs @@ -0,0 +1,41 @@ +############################################################################ +# boards/arm/stm32f2/emw3162/scripts/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/.config +include $(TOPDIR)/tools/Config.mk +include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs + +LDSCRIPT = ld.script +ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) + +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -Wl,-no-check-sections +LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32f2/emw3162/scripts/ld.script b/boards/arm/stm32f2/emw3162/scripts/ld.script new file mode 100644 index 0000000000000..6728bf250c633 --- /dev/null +++ b/boards/arm/stm32f2/emw3162/scripts/ld.script @@ -0,0 +1,130 @@ +/**************************************************************************** + * boards/arm/stm32f2/emw3162/scripts/ld.script + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* The STM32F205RG has 1024Kb of FLASH beginning at address 0x0800:0000 and + * 112Kb of SRAM in main SRAM1 and 16 Kb in auxiliary SRAM2. + * + * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 + * where the code expects to begin execution by jumping to the entry point in + * the 0x0800:0000 address + * range. + */ + +MEMORY +{ + flash (rx) : ORIGIN = 0x08000000, LENGTH = 1024K + sram (rwx) : ORIGIN = 0x20000000, LENGTH = 112K +} + +OUTPUT_ARCH(arm) +EXTERN(_vectors) +ENTRY(_stext) +SECTIONS +{ + .text : { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + + wlan_firmware_image_location = .; + *(.wlan_firmware_image .wlan_firmware_image.*) + wlan_firmware_image_end = .; + + wlan_nvram_image_location = .; + *(.wlan_nvram_image .wlan_nvram_image.*) + wlan_nvram_image_end = .; + + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > flash + + .init_section : { + _sinit = ABSOLUTE(.); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) + _einit = ABSOLUTE(.); + } > flash + + .ARM.extab : { + *(.ARM.extab*) + } > flash + + __exidx_start = ABSOLUTE(.); + .ARM.exidx : { + *(.ARM.exidx*) + } > flash + __exidx_end = ABSOLUTE(.); + + .tdata : { + _stdata = ABSOLUTE(.); + *(.tdata .tdata.* .gnu.linkonce.td.*); + _etdata = ABSOLUTE(.); + } > flash + + .tbss : { + _stbss = ABSOLUTE(.); + *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); + _etbss = ABSOLUTE(.); + } > flash + + _eronly = ABSOLUTE(.); + + .data : { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > sram AT > flash + + .bss : { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + _ebss = ABSOLUTE(.); + } > sram + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/stm32f2/emw3162/src/CMakeLists.txt b/boards/arm/stm32f2/emw3162/src/CMakeLists.txt new file mode 100644 index 0000000000000..74410fcc34ea8 --- /dev/null +++ b/boards/arm/stm32f2/emw3162/src/CMakeLists.txt @@ -0,0 +1,38 @@ +# ############################################################################## +# boards/arm/stm32f2/emw3162/src/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(SRCS stm32_boot.c stm32_bringup.c) + +if(CONFIG_ARCH_LEDS) + list(APPEND SRCS stm32_autoleds.c) +else() + list(APPEND SRCS stm32_userleds.c) +endif() + +if(CONFIG_EMW3162_WLAN) + list(APPEND SRCS stm32_wlan.c) + list(APPEND SRCS stm32_wlan_firmware.c) +endif() + +target_sources(board PRIVATE ${SRCS}) + +set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/ld.script") diff --git a/boards/arm/stm32f2/emw3162/src/Make.defs b/boards/arm/stm32f2/emw3162/src/Make.defs new file mode 100644 index 0000000000000..1cd6ec0b13d29 --- /dev/null +++ b/boards/arm/stm32f2/emw3162/src/Make.defs @@ -0,0 +1,40 @@ +############################################################################ +# boards/arm/stm32f2/emw3162/src/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +CSRCS = stm32_boot.c stm32_bringup.c + +ifeq ($(CONFIG_ARCH_LEDS),y) +CSRCS += stm32_autoleds.c +else +CSRCS += stm32_userleds.c +endif + +ifeq ($(CONFIG_EMW3162_WLAN),y) +CSRCS += stm32_wlan.c +CSRCS += stm32_wlan_firmware.c +endif + +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/emw3162/src/emw3162.h b/boards/arm/stm32f2/emw3162/src/emw3162.h similarity index 98% rename from boards/arm/stm32/emw3162/src/emw3162.h rename to boards/arm/stm32f2/emw3162/src/emw3162.h index 6142ab2310eed..2930b3292652f 100644 --- a/boards/arm/stm32/emw3162/src/emw3162.h +++ b/boards/arm/stm32f2/emw3162/src/emw3162.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/emw3162/src/emw3162.h + * boards/arm/stm32f2/emw3162/src/emw3162.h * * SPDX-License-Identifier: Apache-2.0 * @@ -29,7 +29,7 @@ #include #include -#include +#include /**************************************************************************** * Pre-processor Definitions diff --git a/boards/arm/stm32f2/emw3162/src/stm32_autoleds.c b/boards/arm/stm32f2/emw3162/src/stm32_autoleds.c new file mode 100644 index 0000000000000..e385fbbbd863b --- /dev/null +++ b/boards/arm/stm32f2/emw3162/src/stm32_autoleds.c @@ -0,0 +1,101 @@ +/**************************************************************************** + * boards/arm/stm32f2/emw3162/src/stm32_autoleds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* LEDs + * + * These LEDs are not used by the board port unless CONFIG_ARCH_LEDS is + * defined. In that case, the usage by the board port is defined in + * include/board.h and src/sam_autoleds.c. The LEDs are used to encode + * OS-related events as follows: + * + * ------------------- ----------------------- ------ + * SYMBOL Meaning LED + * ------------------- ----------------------- ------ + * LED_STARTED NuttX has been started OFF + * LED_HEAPALLOCATE Heap has been allocated OFF + * LED_IRQSENABLED Interrupts enabled OFF + * LED_STACKCREATED Idle stack created ON + * LED_INIRQ In an interrupt N/C + * LED_SIGNAL In a signal handler N/C + * LED_ASSERTION An assertion failed N/C + * LED_PANIC The system has crashed FLASH + * + * Thus is LED is statically on, NuttX has successfully booted and is, + * apparently, running normally. If LED is flashing at approximately + * 2Hz, then a fatal error has been detected and the system has halted. + */ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include +#include + +#include "stm32_gpio.h" +#include "emw3162.h" + +#ifdef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_autoled_initialize + ****************************************************************************/ + +void board_autoled_initialize(void) +{ + /* Configure EMW3162 LED gpio as output */ + + stm32_configgpio(GPIO_LED1); +} + +/**************************************************************************** + * Name: board_autoled_on + ****************************************************************************/ + +void board_autoled_on(int led) +{ + if (led == 1 || led == 3) + { + stm32_gpiowrite(GPIO_LED1, true); + } +} + +/**************************************************************************** + * Name: board_autoled_off + ****************************************************************************/ + +void board_autoled_off(int led) +{ + if (led == 3) + { + stm32_gpiowrite(GPIO_LED1, false); + } +} + +#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32f2/emw3162/src/stm32_boot.c b/boards/arm/stm32f2/emw3162/src/stm32_boot.c new file mode 100644 index 0000000000000..afed8722823e4 --- /dev/null +++ b/boards/arm/stm32f2/emw3162/src/stm32_boot.c @@ -0,0 +1,80 @@ +/**************************************************************************** + * boards/arm/stm32f2/emw3162/src/stm32_boot.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include "arm_internal.h" +#include "emw3162.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_boardinitialize + * + * Description: + * All STM32 architectures must provide the following entry point. This + * entry point is called early in the initialization -- after all memory + * has been configured and mapped but before any devices have been + * initialized. + * + ****************************************************************************/ + +void stm32_boardinitialize(void) +{ +#ifdef CONFIG_ARCH_LEDS + /* Configure on-board LEDs if LED support has been selected. */ + + board_autoled_initialize(); +#endif +} + +/**************************************************************************** + * Name: board_late_initialize + * + * Description: + * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_late_initialize(). board_late_initialize() will + * be called immediately after up_intitialize() is called and just before + * the initial application is started. This additional initialization + * phase may be used, for example, to initialize board-specific device + * drivers. + * + ****************************************************************************/ + +#ifdef CONFIG_BOARD_LATE_INITIALIZE +void board_late_initialize(void) +{ + /* Perform board initialization */ + + stm32_bringup(); +} +#endif /* CONFIG_BOARD_LATE_INITIALIZE */ diff --git a/boards/arm/stm32f2/emw3162/src/stm32_bringup.c b/boards/arm/stm32f2/emw3162/src/stm32_bringup.c new file mode 100644 index 0000000000000..f78b630f1385d --- /dev/null +++ b/boards/arm/stm32f2/emw3162/src/stm32_bringup.c @@ -0,0 +1,96 @@ +/**************************************************************************** + * boards/arm/stm32f2/emw3162/src/stm32_bringup.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include +#include + +#include + +#include "emw3162.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_bringup + * + * Description: + * This function initializes and configures all on-board features + * appropriate for the selected configuration. + * + ****************************************************************************/ + +int stm32_bringup(void) +{ + int ret = OK; + +#ifdef CONFIG_FS_PROCFS + /* Mount the procfs file system */ + + ret = nx_mount(NULL, "/proc", "procfs", 0, NULL); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to mount procfs at /proc: %d\n", ret); + } +#endif + +#if defined(CONFIG_USERLED) && !defined(CONFIG_ARCH_LEDS) +#ifdef CONFIG_USERLED_LOWER + /* Register the LED driver */ + + ret = userled_lower_initialize("/dev/userleds"); + if (ret != OK) + { + syslog(LOG_ERR, "ERROR: userled_lower_initialize() failed: %d\n", ret); + return ret; + } +#else + /* Enable USER LED support for some other purpose */ + + board_userled_initialize(); +#endif /* CONFIG_USERLED_LOWER */ +#endif /* CONFIG_USERLED && !CONFIG_ARCH_LEDS */ + +#ifdef CONFIG_EMW3162_WLAN + /* Initialize wlan driver and hardware */ + + ret = emw3162_wlan_initialize(); + if (ret != OK) + { + syslog(LOG_ERR, "Failed to initialize wlan: %d\n", ret); + return ret; + } +#endif + + return ret; +} diff --git a/boards/arm/stm32f2/emw3162/src/stm32_userleds.c b/boards/arm/stm32f2/emw3162/src/stm32_userleds.c new file mode 100644 index 0000000000000..51cadf4321bb9 --- /dev/null +++ b/boards/arm/stm32f2/emw3162/src/stm32_userleds.c @@ -0,0 +1,74 @@ +/**************************************************************************** + * boards/arm/stm32f2/emw3162/src/stm32_userleds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include +#include "emw3162.h" + +#include "stm32_gpio.h" + +#ifndef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_userled_initialize + ****************************************************************************/ + +uint32_t board_userled_initialize(void) +{ + /* Configure EMW3162 LED gpio as output */ + + stm32_configgpio(GPIO_LED1); + return BOARD_NLEDS; +} + +/**************************************************************************** + * Name: board_userled + ****************************************************************************/ + +void board_userled(int led, bool ledon) +{ + if (led == BOARD_LED1) + { + stm32_gpiowrite(GPIO_LED1, ledon); + } +} + +/**************************************************************************** + * Name: board_userled_all + ****************************************************************************/ + +void board_userled_all(uint32_t ledset) +{ + stm32_gpiowrite(GPIO_LED1, !!(ledset & BOARD_LED1_BIT)); +} + +#endif /* !CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32f2/emw3162/src/stm32_wlan.c b/boards/arm/stm32f2/emw3162/src/stm32_wlan.c new file mode 100644 index 0000000000000..4396b94401a04 --- /dev/null +++ b/boards/arm/stm32f2/emw3162/src/stm32_wlan.c @@ -0,0 +1,176 @@ +/**************************************************************************** + * boards/arm/stm32f2/emw3162/src/stm32_wlan.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include +#include + +#include + +#include "stm32.h" +#include "stm32_gpio.h" +#include "stm32_sdio.h" + +#include "emw3162.h" + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static struct sdio_dev_s *g_sdio_dev; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: bcmf_board_reset + ****************************************************************************/ + +void bcmf_board_reset(int minor, bool reset) +{ + if (minor != SDIO_WLAN0_MINOR) + { + return; + } + + stm32_gpiowrite(GPIO_WLAN0_RESET, !reset); +} + +/**************************************************************************** + * Name: bcmf_board_power + ****************************************************************************/ + +void bcmf_board_power(int minor, bool power) +{ + if (minor != SDIO_WLAN0_MINOR) + { + return; + } + + stm32_gpiowrite(GPIO_WLAN0_PWRDN, !power); +} + +/**************************************************************************** + * Name: bcmf_board_initialize + ****************************************************************************/ + +void bcmf_board_initialize(int minor) +{ + if (minor != SDIO_WLAN0_MINOR) + { + return; + } + + /* Configure MCO1 output to drive EXT_SLEEP_CLK input pin of BCM43362 */ + + stm32_configgpio(GPIO_MCO1); + stm32_mco1config(RCC_CFGR_MCO1_LSE, RCC_CFGR_MCO1PRE_NONE); + + /* Configure PowerDown pin */ + + stm32_configgpio(GPIO_WLAN0_PWRDN); + + /* Shutdown wlan chip */ + + bcmf_board_power(minor, false); + + /* Configure reset pin */ + + stm32_configgpio(GPIO_WLAN0_RESET); + + /* Put wlan chip in reset state */ + + bcmf_board_reset(minor, true); +} + +/**************************************************************************** + * Name: bcmf_board_setup_oob_irq + ****************************************************************************/ + +void bcmf_board_setup_oob_irq(int minor, int (*func)(void *), void *arg) +{ + if (minor != SDIO_WLAN0_MINOR) + { + return; + } + + /* Configure SDIO card in-band interrupt callback */ + + if (g_sdio_dev != NULL) + { + sdio_set_sdio_card_isr(g_sdio_dev, func, arg); + } +} + +/**************************************************************************** + * Name: bcmf_board_etheraddr + ****************************************************************************/ + +bool bcmf_board_etheraddr(struct ether_addr *ethaddr) +{ + return false; +} + +/**************************************************************************** + * Name: emw3162_wlan_initialize + ****************************************************************************/ + +int emw3162_wlan_initialize(void) +{ + int ret; + + /* Initialize sdio interface */ + + wlinfo("Initializing SDIO slot %d\n", SDIO_WLAN0_SLOTNO); + + g_sdio_dev = sdio_initialize(SDIO_WLAN0_SLOTNO); + + if (!g_sdio_dev) + { + wlerr("ERROR: Failed to initialize SDIO with slot %d\n", + SDIO_WLAN0_SLOTNO); + return ERROR; + } + + /* Bind the SDIO interface to the bcmf driver */ + + ret = bcmf_sdio_initialize(SDIO_WLAN0_MINOR, g_sdio_dev); + + if (ret != OK) + { + wlerr("ERROR: Failed to bind SDIO to bcmf driver\n"); + + /* FIXME deinitialize sdio device */ + + return ERROR; + } + + return OK; +} diff --git a/boards/arm/stm32/emw3162/src/stm32_wlan_firmware.c b/boards/arm/stm32f2/emw3162/src/stm32_wlan_firmware.c similarity index 100% rename from boards/arm/stm32/emw3162/src/stm32_wlan_firmware.c rename to boards/arm/stm32f2/emw3162/src/stm32_wlan_firmware.c diff --git a/boards/arm/stm32f2/nucleo-f207zg/CMakeLists.txt b/boards/arm/stm32f2/nucleo-f207zg/CMakeLists.txt new file mode 100644 index 0000000000000..4f4af60fbffd3 --- /dev/null +++ b/boards/arm/stm32f2/nucleo-f207zg/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32f2/nucleo-f207zg/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/arm/stm32/nucleo-f207zg/Kconfig b/boards/arm/stm32f2/nucleo-f207zg/Kconfig similarity index 100% rename from boards/arm/stm32/nucleo-f207zg/Kconfig rename to boards/arm/stm32f2/nucleo-f207zg/Kconfig diff --git a/boards/arm/stm32f2/nucleo-f207zg/configs/adc/defconfig b/boards/arm/stm32f2/nucleo-f207zg/configs/adc/defconfig new file mode 100644 index 0000000000000..53b10cb1c268e --- /dev/null +++ b/boards/arm/stm32f2/nucleo-f207zg/configs/adc/defconfig @@ -0,0 +1,48 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +CONFIG_ADC=y +CONFIG_ADC_FIFOSIZE=4 +CONFIG_ANALOG=y +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nucleo-f207zg" +CONFIG_ARCH_BOARD_NUCLEO_F207ZG=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f2" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F207ZG=y +CONFIG_ARCH_CHIP_STM32F2=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=6522 +CONFIG_BUILTIN=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_EXAMPLES_ADC=y +CONFIG_EXAMPLES_ADC_GROUPSIZE=3 +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_MM_REGIONS=2 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=27 +CONFIG_START_YEAR=2013 +CONFIG_STM32_ADC1=y +CONFIG_STM32_ADC1_DMA=y +CONFIG_STM32_ADC3=y +CONFIG_STM32_DMA2=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_TIM1=y +CONFIG_STM32_TIM1_ADC=y +CONFIG_STM32_USART3=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART3_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f2/nucleo-f207zg/configs/nsh/defconfig b/boards/arm/stm32f2/nucleo-f207zg/configs/nsh/defconfig new file mode 100644 index 0000000000000..2679b5c5e8b9f --- /dev/null +++ b/boards/arm/stm32f2/nucleo-f207zg/configs/nsh/defconfig @@ -0,0 +1,38 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nucleo-f207zg" +CONFIG_ARCH_BOARD_NUCLEO_F207ZG=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f2" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F207ZG=y +CONFIG_ARCH_CHIP_STM32F2=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=6522 +CONFIG_BUILTIN=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_EXAMPLES_HELLO=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_MM_REGIONS=2 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=27 +CONFIG_START_YEAR=2013 +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_USART3=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART3_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f2/nucleo-f207zg/configs/pwm/defconfig b/boards/arm/stm32f2/nucleo-f207zg/configs/pwm/defconfig new file mode 100644 index 0000000000000..04c5b15c5027e --- /dev/null +++ b/boards/arm/stm32f2/nucleo-f207zg/configs/pwm/defconfig @@ -0,0 +1,42 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nucleo-f207zg" +CONFIG_ARCH_BOARD_NUCLEO_F207ZG=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f2" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F207ZG=y +CONFIG_ARCH_CHIP_STM32F2=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=6522 +CONFIG_BUILTIN=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_EXAMPLES_PWM=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_MM_REGIONS=2 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_PWM=y +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=27 +CONFIG_START_YEAR=2013 +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_TIM1=y +CONFIG_STM32_TIM1_CH1OUT=y +CONFIG_STM32_TIM1_PWM=y +CONFIG_STM32_USART3=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART3_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f2/nucleo-f207zg/include/board.h b/boards/arm/stm32f2/nucleo-f207zg/include/board.h new file mode 100644 index 0000000000000..62f9ed1e30ef6 --- /dev/null +++ b/boards/arm/stm32f2/nucleo-f207zg/include/board.h @@ -0,0 +1,209 @@ +/**************************************************************************** + * boards/arm/stm32f2/nucleo-f207zg/include/board.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_STM32_NUCLEO_F207ZG_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32_NUCLEO_F207ZG_INCLUDE_BOARD_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#ifndef __ASSEMBLY__ +# include +# include +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Clocking *****************************************************************/ + +/* HSI - 16 MHz RC factory-trimmed + * LSI - 32 KHz RC + * HSE - 8 MHz from MCO output of ST-LINK + * LSE - 32.768 kHz + */ + +#define STM32_BOARD_XTAL 8000000ul + +#define STM32_HSI_FREQUENCY 16000000ul +#define STM32_LSI_FREQUENCY 32000 +#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL +#define STM32_LSE_FREQUENCY 32768 /* X2 on board */ + +/* Main PLL Configuration. + * + * Formulae: + * + * VCO input frequency = + * PLL input clock frequency / PLLM, 2 <= PLLM <= 63 + * VCO output frequency = + * VCO input frequency × PLLN, 50 <= PLLN <= 432 + * PLL output clock frequency = + * VCO frequency / PLLP, PLLP = 2, 4, 6, or 8 + * USB OTG FS clock frequency = + * VCO frequency / PLLQ, 2 <= PLLQ <= 15 + * + * We will configure like this + * + * PLL source is HSE + * PLL_VCO = (STM32_HSE_FREQUENCY / PLLM) * PLLN + * = (8,000,000 / 2) * 100 + * = 400,000,000 + * SYSCLK = PLL_VCO / PLLP + * = 400,000,000 / 4 = 100,000,000 + * RNG Clock + * = PLL_VCO / PLLQ + * = 400,000,000 / 8 = 50,000,000 + * + */ + +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(2) +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(100) +#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_4 +#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(8) + +#define STM32_SYSCLK_FREQUENCY 100000000ul + +/* AHB clock (HCLK) is SYSCLK (100MHz) */ + +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY + +/* APB1 clock (PCLK1) is HCLK/2 (25MHz) */ + +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd4 /* PCLK1 = HCLK / 4 */ +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/4) + +/* APB2 clock (PCLK2) is HCLK/2 (50MHz) */ + +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 2 */ +#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/2) + +/* Timers driven from APB2 will be twice PCLK2 (100Mhz) */ + +#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM9_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM10_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM11_CLKIN (2*STM32_PCLK2_FREQUENCY) + +/* Timers driven from APB1 will be twice PCLK1 (50MHz) */ + +#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) + +/* LED definitions **********************************************************/ + +/* The Nucleo-144 board has numerous LEDs but only three, LD1 a Green LED, + * LD2 a Blue LED and LD3 a Red LED, that can be controlled by software. + * The following definitions assume the default Solder Bridges are installed. + * + * If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs + * in any way. + * The following definitions are used to access individual LEDs. + */ + +/* LED index values for use with board_userled() */ + +#define BOARD_LED1 0 +#define BOARD_LED2 1 +#define BOARD_LED3 2 +#define BOARD_NLEDS 3 + +#define BOARD_LED_GREEN BOARD_LED1 +#define BOARD_LED_BLUE BOARD_LED2 +#define BOARD_LED_RED BOARD_LED3 + +/* LED bits for use with board_userled_all() */ + +#define BOARD_LED1_BIT (1 << BOARD_LED1) +#define BOARD_LED2_BIT (1 << BOARD_LED2) +#define BOARD_LED3_BIT (1 << BOARD_LED3) + +/* If CONFIG_ARCH_LEDS is defined, the usage by the board port is defined in + * include/board.h and src/stm32_leds.c. The LEDs are used to encode + * OS-related events as follows: + * + * + * SYMBOL Meaning LED state + * Red Green Blue + * ---------------------- -------------------------- ------ ------ ---- + */ + +#define LED_STARTED 0 /* NuttX has been started OFF OFF OFF */ +#define LED_HEAPALLOCATE 1 /* Heap has been allocated OFF OFF ON */ +#define LED_IRQSENABLED 2 /* Interrupts enabled OFF ON OFF */ +#define LED_STACKCREATED 3 /* Idle stack created OFF ON ON */ +#define LED_INIRQ 4 /* In an interrupt N/C N/C GLOW */ +#define LED_SIGNAL 5 /* In a signal handler N/C GLOW N/C */ +#define LED_ASSERTION 6 /* An assertion failed GLOW N/C GLOW */ +#define LED_PANIC 7 /* The system has crashed Blink OFF N/C */ +#define LED_IDLE 8 /* MCU is in sleep mode ON OFF OFF */ + +/* Button definitions *******************************************************/ + +/* The NUCLEO board supports one button: Pushbutton B1, labeled "User", is + * connected to GPIO PC13. A high value will be sensed when the button is + * depressed. + */ + +#define BUTTON_USER 0 +#define NUM_BUTTONS 1 + +#define BUTTON_USER_BIT (1 << BUTTON_USER) + +/* Alternate function pin selections ****************************************/ + +/* USART3 (Nucleo Virtual Console) */ + +#define GPIO_USART3_RX (GPIO_USART3_RX_3|GPIO_SPEED_100MHz) /* PD9 */ +#define GPIO_USART3_TX (GPIO_USART3_TX_3|GPIO_SPEED_100MHz) /* PD8 */ + +/* PWM configuration ********************************************************/ + +/* TIM1 PWM */ + +#define GPIO_TIM1_CH1OUT (GPIO_TIM1_CH1OUT_2|GPIO_SPEED_50MHz) /* PE9 */ +#define GPIO_TIM1_CH1NOUT GPIO_TIM1_CH1N_3 /* PE8 */ +#define GPIO_TIM1_CH2OUT (GPIO_TIM1_CH2OUT_2|GPIO_SPEED_50MHz) /* PE11 */ +#define GPIO_TIM1_CH2NOUT GPIO_TIM1_CH2N_3 /* PE10 */ +#define GPIO_TIM1_CH3OUT (GPIO_TIM1_CH3OUT_2|GPIO_SPEED_50MHz) /* PE13 */ +#define GPIO_TIM1_CH3NOUT GPIO_TIM1_CH3N_3 /* PE12 */ + +/* DMA channels *************************************************************/ + +/* ADC */ + +#define ADC1_DMA_CHAN DMAMAP_ADC1_1 + +#endif /* __BOARDS_ARM_STM32_NUCLEO_F207ZG_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32f2/nucleo-f207zg/scripts/Make.defs b/boards/arm/stm32f2/nucleo-f207zg/scripts/Make.defs new file mode 100644 index 0000000000000..63f3a3eb5cedf --- /dev/null +++ b/boards/arm/stm32f2/nucleo-f207zg/scripts/Make.defs @@ -0,0 +1,41 @@ +############################################################################ +# boards/arm/stm32f2/nucleo-f207zg/scripts/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/.config +include $(TOPDIR)/tools/Config.mk +include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs + +LDSCRIPT = ld.script +ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) + +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32f2/nucleo-f207zg/scripts/ld.script b/boards/arm/stm32f2/nucleo-f207zg/scripts/ld.script new file mode 100644 index 0000000000000..5ea1a69efb101 --- /dev/null +++ b/boards/arm/stm32f2/nucleo-f207zg/scripts/ld.script @@ -0,0 +1,124 @@ +/**************************************************************************** + * boards/arm/stm32f2/nucleo-f207zg/scripts/ld.script + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* The STM32F207ZG has 1Mb of FLASH beginning at address 0x0800:0000, + * 128Kb of SRAM. SRAM is split up into two blocks: + * + * 1) 112Kb of SRAM beginning at address 0x2000:0000 + * 2) 16Kb of SRAM beginning at address 0x2001:c000 + * + * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 + * where the code expects to begin execution by jumping to the entry point in + * the 0x0800:0000 address range. + */ + +MEMORY +{ + flash (rx) : ORIGIN = 0x08000000, LENGTH = 1M + sram (rwx) : ORIGIN = 0x20000000, LENGTH = 112K +} + +OUTPUT_ARCH(arm) +EXTERN(_vectors) +ENTRY(_stext) +SECTIONS +{ + .text : { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > flash + + .init_section : ALIGN(4) { + _sinit = ABSOLUTE(.); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) + _einit = ABSOLUTE(.); + } > flash + + .ARM.extab : ALIGN(4) { + *(.ARM.extab*) + } > flash + + .ARM.exidx : ALIGN(4) { + __exidx_start = ABSOLUTE(.); + *(.ARM.exidx*) + __exidx_end = ABSOLUTE(.); + } > flash + + .tdata : { + _stdata = ABSOLUTE(.); + *(.tdata .tdata.* .gnu.linkonce.td.*); + _etdata = ABSOLUTE(.); + } > flash + + .tbss : { + _stbss = ABSOLUTE(.); + *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); + _etbss = ABSOLUTE(.); + } > flash + + _eronly = ABSOLUTE(.); + + .data : ALIGN(4) { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > sram AT > flash + + .bss : ALIGN(4) { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + _ebss = ABSOLUTE(.); + } > sram + + /* Stabs debugging sections. */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/stm32f2/nucleo-f207zg/src/CMakeLists.txt b/boards/arm/stm32f2/nucleo-f207zg/src/CMakeLists.txt new file mode 100644 index 0000000000000..06e696f957093 --- /dev/null +++ b/boards/arm/stm32f2/nucleo-f207zg/src/CMakeLists.txt @@ -0,0 +1,49 @@ +# ############################################################################## +# boards/arm/stm32f2/nucleo-f207zg/src/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(SRCS stm32_boot.c stm32_bringup.c) + +if(CONFIG_ARCH_LEDS) + list(APPEND SRCS stm32_autoleds.c) +else() + list(APPEND SRCS stm32_userleds.c) +endif() + +if(CONFIG_ARCH_BUTTONS) + list(APPEND SRCS stm32_buttons.c) +endif() + +if(CONFIG_STM32_OTGFS) + list(APPEND SRCS stm32_usb.c) +endif() + +if(CONFIG_ADC) + list(APPEND SRCS stm32_adc.c) +endif() + +if(CONFIG_PWM) + list(APPEND SRCS stm32_pwm.c) +endif() + +target_sources(board PRIVATE ${SRCS}) + +set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/ld.script") diff --git a/boards/arm/stm32f2/nucleo-f207zg/src/Make.defs b/boards/arm/stm32f2/nucleo-f207zg/src/Make.defs new file mode 100644 index 0000000000000..71bb086e05788 --- /dev/null +++ b/boards/arm/stm32f2/nucleo-f207zg/src/Make.defs @@ -0,0 +1,51 @@ +############################################################################ +# boards/arm/stm32f2/nucleo-f207zg/src/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +CSRCS = stm32_boot.c stm32_bringup.c + +ifeq ($(CONFIG_ARCH_LEDS),y) +CSRCS += stm32_autoleds.c +else +CSRCS += stm32_userleds.c +endif + +ifeq ($(CONFIG_ARCH_BUTTONS),y) +CSRCS += stm32_buttons.c +endif + +ifeq ($(CONFIG_STM32_OTGFS),y) +CSRCS += stm32_usb.c +endif + +ifeq ($(CONFIG_ADC),y) +CSRCS += stm32_adc.c +endif + +ifeq ($(CONFIG_PWM),y) +CSRCS += stm32_pwm.c +endif + +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/nucleo-f207zg/src/nucleo-f207zg.h b/boards/arm/stm32f2/nucleo-f207zg/src/nucleo-f207zg.h similarity index 98% rename from boards/arm/stm32/nucleo-f207zg/src/nucleo-f207zg.h rename to boards/arm/stm32f2/nucleo-f207zg/src/nucleo-f207zg.h index c6d2497a86498..26ec0f5cb0903 100644 --- a/boards/arm/stm32/nucleo-f207zg/src/nucleo-f207zg.h +++ b/boards/arm/stm32f2/nucleo-f207zg/src/nucleo-f207zg.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f207zg/src/nucleo-f207zg.h + * boards/arm/stm32f2/nucleo-f207zg/src/nucleo-f207zg.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f2/nucleo-f207zg/src/stm32_adc.c b/boards/arm/stm32f2/nucleo-f207zg/src/stm32_adc.c new file mode 100644 index 0000000000000..3e2a2c19e32aa --- /dev/null +++ b/boards/arm/stm32f2/nucleo-f207zg/src/stm32_adc.c @@ -0,0 +1,243 @@ +/**************************************************************************** + * boards/arm/stm32f2/nucleo-f207zg/src/stm32_adc.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "stm32.h" + +#if defined(CONFIG_ADC) && (defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC3)) + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* 1 or 2 ADC devices (DEV1, DEV2). + * ADC1 and ADC3 supported for now. + */ + +#if defined(CONFIG_STM32_ADC1) +# define DEV1_PORT 1 +#endif + +#if defined(CONFIG_STM32_ADC3) +# if defined(DEV1_PORT) +# define DEV2_PORT 3 +# else +# define DEV1_PORT 3 +# endif +#endif + +/* The number of ADC channels in the conversion list */ + +/* TODO DMA */ + +#define ADC1_NCHANNELS 3 +#define ADC3_NCHANNELS 3 + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* DEV 1 */ + +#if DEV1_PORT == 1 + +#define DEV1_NCHANNELS ADC1_NCHANNELS + +/* Identifying number of each ADC channel (even if NCHANNELS is less ) */ + +static const uint8_t g_chanlist1[3] = +{ + 3, + 10, + 13 +}; + +/* Configurations of pins used by each ADC channel */ + +static const uint32_t g_pinlist1[3] = +{ + GPIO_ADC1_IN3_0, /* PA3/A0 */ + GPIO_ADC1_IN10_0, /* PC0/A1 */ + GPIO_ADC1_IN13_0, /* PC3/A2 */ +}; + +#elif DEV1_PORT == 3 + +#define DEV1_NCHANNELS ADC3_NCHANNELS + +/* Identifying number of each ADC channel */ + +static const uint8_t g_chanlist1[3] = +{ + 9, + 15, + 8 +}; + +/* Configurations of pins used by each ADC channel */ + +static const uint32_t g_pinlist1[3] = +{ + GPIO_ADC3_IN9_0, /* PF3/A3 */ + GPIO_ADC3_IN15_0, /* PF5/A4 */ + GPIO_ADC3_IN8_0, /* PF10/A5 */ +}; + +#endif /* DEV1_PORT == 1 */ + +#ifdef DEV2_PORT + +/* DEV 2 */ + +#if DEV2_PORT == 3 + +#define DEV2_NCHANNELS ADC3_NCHANNELS + +/* Identifying number of each ADC channel */ + +static const uint8_t g_chanlist2[3] = +{ + 9, + 15, + 8 +}; + +/* Configurations of pins used by each ADC channel */ + +static const uint32_t g_pinlist2[3] = +{ + GPIO_ADC3_IN9_0, /* PF3/A3 */ + GPIO_ADC3_IN15_0, /* PF5/A4 */ + GPIO_ADC3_IN8_0, /* PF10/A5 */ +}; + +#endif /* DEV2_PORT == 3 */ +#endif /* DEV2_PORT */ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_adc_setup + * + * Description: + * Initialize ADC and register the ADC driver. + * + ****************************************************************************/ + +int stm32_adc_setup(void) +{ + static bool initialized = false; + struct adc_dev_s *adc; + int ret; + int i; + + /* Check if we have already initialized */ + + if (!initialized) + { + /* DEV1 */ + + /* Configure the pins as analog inputs for the selected channels */ + + for (i = 0; i < DEV1_NCHANNELS; i++) + { + stm32_configgpio(g_pinlist1[i]); + } + + /* Call stm32_adcinitialize() to get an instance of the ADC interface */ + + adc = stm32_adcinitialize(DEV1_PORT, g_chanlist1, DEV1_NCHANNELS); + if (adc == NULL) + { + aerr("ERROR: Failed to get ADC interface 1\n"); + return -ENODEV; + } + + /* Register the ADC driver at "/dev/adc0" */ + + ret = adc_register("/dev/adc0", adc); + if (ret < 0) + { + aerr("ERROR: adc_register /dev/adc0 failed: %d\n", ret); + return ret; + } + +#ifdef DEV2_PORT + /* DEV2 */ + + /* Configure the pins as analog inputs for the selected channels */ + + for (i = 0; i < DEV2_NCHANNELS; i++) + { + stm32_configgpio(g_pinlist2[i]); + } + + /* Call stm32_adcinitialize() to get an instance of the ADC interface */ + + adc = stm32_adcinitialize(DEV2_PORT, g_chanlist2, DEV2_NCHANNELS); + if (adc == NULL) + { + aerr("ERROR: Failed to get ADC interface 2\n"); + return -ENODEV; + } + + /* Register the ADC driver at "/dev/adc1" */ + + ret = adc_register("/dev/adc1", adc); + if (ret < 0) + { + aerr("ERROR: adc_register /dev/adc1 failed: %d\n", ret); + return ret; + } +#endif + + initialized = true; + } + + return OK; +} + +#endif /* CONFIG_ADC && (CONFIG_STM32_ADC1 || CONFIG_STM32_ADC3) */ diff --git a/boards/arm/stm32f2/nucleo-f207zg/src/stm32_autoleds.c b/boards/arm/stm32f2/nucleo-f207zg/src/stm32_autoleds.c new file mode 100644 index 0000000000000..10db82a159ec9 --- /dev/null +++ b/boards/arm/stm32f2/nucleo-f207zg/src/stm32_autoleds.c @@ -0,0 +1,171 @@ +/**************************************************************************** + * boards/arm/stm32f2/nucleo-f207zg/src/stm32_autoleds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include + +#include +#include + +#include "stm32_gpio.h" +#include "nucleo-f207zg.h" + +#ifdef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* Indexed by BOARD_LED_ */ + +static const uint32_t g_ledmap[BOARD_NLEDS] = +{ + GPIO_LED_GREEN, + GPIO_LED_BLUE, + GPIO_LED_RED, +}; + +static bool g_initialized; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +static void phy_set_led(int led, bool state) +{ + /* Active High */ + + stm32_gpiowrite(g_ledmap[led], state); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_autoled_initialize + ****************************************************************************/ + +void board_autoled_initialize(void) +{ + int i; + + /* Configure the LD1 GPIO for output. Initial state is OFF */ + + for (i = 0; i < nitems(g_ledmap); i++) + { + stm32_configgpio(g_ledmap[i]); + } +} + +/**************************************************************************** + * Name: board_autoled_on + ****************************************************************************/ + +void board_autoled_on(int led) +{ + switch (led) + { + default: + break; + + case LED_HEAPALLOCATE: + phy_set_led(BOARD_LED_BLUE, true); + break; + + case LED_IRQSENABLED: + phy_set_led(BOARD_LED_BLUE, false); + phy_set_led(BOARD_LED_GREEN, true); + break; + + case LED_STACKCREATED: + phy_set_led(BOARD_LED_GREEN, true); + phy_set_led(BOARD_LED_BLUE, true); + g_initialized = true; + break; + + case LED_INIRQ: + phy_set_led(BOARD_LED_BLUE, true); + break; + + case LED_SIGNAL: + phy_set_led(BOARD_LED_GREEN, true); + break; + + case LED_ASSERTION: + phy_set_led(BOARD_LED_RED, true); + phy_set_led(BOARD_LED_BLUE, true); + break; + + case LED_PANIC: + phy_set_led(BOARD_LED_RED, true); + break; + + case LED_IDLE : /* IDLE */ + phy_set_led(BOARD_LED_RED, true); + break; + } +} + +/**************************************************************************** + * Name: board_autoled_off + ****************************************************************************/ + +void board_autoled_off(int led) +{ + switch (led) + { + default: + break; + + case LED_SIGNAL: + phy_set_led(BOARD_LED_GREEN, false); + break; + + case LED_INIRQ: + phy_set_led(BOARD_LED_BLUE, false); + break; + + case LED_ASSERTION: + phy_set_led(BOARD_LED_RED, false); + phy_set_led(BOARD_LED_BLUE, false); + break; + + case LED_PANIC: + phy_set_led(BOARD_LED_RED, false); + break; + + case LED_IDLE : /* IDLE */ + phy_set_led(BOARD_LED_RED, false); + break; + } +} + +#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32f2/nucleo-f207zg/src/stm32_boot.c b/boards/arm/stm32f2/nucleo-f207zg/src/stm32_boot.c new file mode 100644 index 0000000000000..5828a05c690c6 --- /dev/null +++ b/boards/arm/stm32f2/nucleo-f207zg/src/stm32_boot.c @@ -0,0 +1,87 @@ +/**************************************************************************** + * boards/arm/stm32f2/nucleo-f207zg/src/stm32_boot.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include +#include + +#include "arm_internal.h" +#include "stm32_start.h" +#include "nucleo-f207zg.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_boardinitialize + * + * Description: + * All STM32 architectures must provide the following entry point. + * This entry point is called early in the initialization -- after all + * memory has been configured and mapped but before any devices have been + * initialized. + * + ****************************************************************************/ + +void stm32_boardinitialize(void) +{ +#ifdef CONFIG_ARCH_LEDS + /* Configure on-board LEDs if LED support has been selected. */ + + board_autoled_initialize(); +#endif + +#if defined(CONFIG_STM32_OTGFS) || defined(CONFIG_STM32_HOST) + /* Initialize USB */ + + stm32_usbinitialize(); +#endif +} + +/**************************************************************************** + * Name: board_late_initialize + * + * Description: + * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_late_initialize(). board_late_initialize() + * will be called immediately after up_initialize() is called and just + * before the initial application is started. + * This additional initialization phase may be used, for example, to + * initialize board-specific device drivers. + * + ****************************************************************************/ + +#ifdef CONFIG_BOARD_LATE_INITIALIZE +void board_late_initialize(void) +{ + stm32_bringup(); +} +#endif diff --git a/boards/arm/stm32f2/nucleo-f207zg/src/stm32_bringup.c b/boards/arm/stm32f2/nucleo-f207zg/src/stm32_bringup.c new file mode 100644 index 0000000000000..1927f3bca09be --- /dev/null +++ b/boards/arm/stm32f2/nucleo-f207zg/src/stm32_bringup.c @@ -0,0 +1,92 @@ +/**************************************************************************** + * boards/arm/stm32f2/nucleo-f207zg/src/stm32_bringup.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include "nucleo-f207zg.h" + +#ifdef CONFIG_INPUT_BUTTONS +# include +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_bringup + * + * Description: + * Perform architecture-specific initialization + * + * CONFIG_BOARD_LATE_INITIALIZE=y : + * Called from board_late_initialize(). + * + ****************************************************************************/ + +int stm32_bringup(void) +{ + int ret = OK; + +#ifdef CONFIG_ADC + /* Initialize ADC and register the ADC driver. */ + + ret = stm32_adc_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_adc_setup failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_PWM + /* Initialize PWM and register the PWM driver. */ + + ret = stm32_pwm_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_pwm_setup failed: %d\n", ret); + } +#endif + +#if defined(CONFIG_CDCACM) && !defined(CONFIG_CDCACM_CONSOLE) + /* Initialize CDCACM */ + + syslog(LOG_INFO, "Initialize CDCACM device\n"); + + ret = cdcacm_initialize(0, NULL); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: cdcacm_initialize failed: %d\n", ret); + } +#endif + + UNUSED(ret); + return OK; +} diff --git a/boards/arm/stm32f2/nucleo-f207zg/src/stm32_buttons.c b/boards/arm/stm32f2/nucleo-f207zg/src/stm32_buttons.c new file mode 100644 index 0000000000000..8638a37a4b613 --- /dev/null +++ b/boards/arm/stm32f2/nucleo-f207zg/src/stm32_buttons.c @@ -0,0 +1,107 @@ +/**************************************************************************** + * boards/arm/stm32f2/nucleo-f207zg/src/stm32_buttons.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include + +#include "stm32_gpio.h" +#include "nucleo-f207zg.h" +#include + +#ifdef CONFIG_ARCH_BUTTONS + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_button_initialize + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. + * + ****************************************************************************/ + +uint32_t board_button_initialize(void) +{ + stm32_configgpio(GPIO_BTN_USER); + return NUM_BUTTONS; +} + +/**************************************************************************** + * Name: board_buttons + ****************************************************************************/ + +uint32_t board_buttons(void) +{ + return stm32_gpioread(GPIO_BTN_USER) ? 1 : 0; +} + +/**************************************************************************** + * Button support. + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. + * + * After board_button_initialize() has been called, board_buttons() may be + * called to collect the state of all buttons. board_buttons() returns a + * 32-bit bit set with each bit associated with a button. See the + * BUTTON_*_BIT definitions in board.h for the meaning of each bit. + * + * board_button_irq() may be called to register an interrupt handler that + * will be called when a button is depressed or released. The ID value is + * a button enumeration value that uniquely identifies a button resource. + * See the BUTTON_* definitions in board.h for the meaning of enumeration + * value. + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_IRQBUTTONS +int board_button_irq(int id, xcpt_t irqhandler, void *arg) +{ + int ret = -EINVAL; + + if (id == BUTTON_USER) + { + ret = stm32_gpiosetevent(GPIO_BTN_USER, true, true, true, + irqhandler, arg); + } + + return ret; +} +#endif +#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/stm32f2/nucleo-f207zg/src/stm32_pwm.c b/boards/arm/stm32f2/nucleo-f207zg/src/stm32_pwm.c new file mode 100644 index 0000000000000..a43f95dc57e24 --- /dev/null +++ b/boards/arm/stm32f2/nucleo-f207zg/src/stm32_pwm.c @@ -0,0 +1,110 @@ +/**************************************************************************** + * boards/arm/stm32f2/nucleo-f207zg/src/stm32_pwm.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32_pwm.h" +#include "nucleo-f207zg.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +#define HAVE_PWM 1 + +#ifndef CONFIG_PWM +# undef HAVE_PWM +#endif + +#ifndef CONFIG_STM32_TIM1 +# undef HAVE_PWM +#endif + +#ifndef CONFIG_STM32_TIM1_PWM +# undef HAVE_PWM +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_pwm_setup + * + * Description: + * Initialize PWM and register the PWM device. + * + ****************************************************************************/ + +int stm32_pwm_setup(void) +{ +#ifdef HAVE_PWM + static bool initialized = false; + struct pwm_lowerhalf_s *pwm; + int ret; + + /* Have we already initialized? */ + + if (!initialized) + { + /* Call stm32_pwminitialize() to get an instance of the PWM interface */ + + pwm = stm32_pwminitialize(NUCLEOF207ZG_PWMTIMER); + if (!pwm) + { + tmrerr("ERROR: Failed to get the STM32 PWM lower half\n"); + return -ENODEV; + } + + /* Register the PWM driver at "/dev/pwm0" */ + + ret = pwm_register("/dev/pwm0", pwm); + if (ret < 0) + { + tmrerr("ERROR: pwm_register failed: %d\n", ret); + return ret; + } + + /* Now we are initialized */ + + initialized = true; + } + + return OK; +#else + return -ENODEV; +#endif +} diff --git a/boards/arm/stm32f2/nucleo-f207zg/src/stm32_usb.c b/boards/arm/stm32f2/nucleo-f207zg/src/stm32_usb.c new file mode 100644 index 0000000000000..6d3390be492aa --- /dev/null +++ b/boards/arm/stm32f2/nucleo-f207zg/src/stm32_usb.c @@ -0,0 +1,322 @@ +/**************************************************************************** + * boards/arm/stm32f2/nucleo-f207zg/src/stm32_usb.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include "arm_internal.h" +#include "chip.h" +#include "stm32_gpio.h" +#include "stm32_otgfs.h" +#include "nucleo-f207zg.h" + +#ifdef CONFIG_STM32_OTGFS + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#if defined(CONFIG_USBDEV) || defined(CONFIG_USBHOST) +# define HAVE_USB 1 +#else +# warning "CONFIG_STM32_OTGFS is enabled but neither CONFIG_USBDEV nor CONFIG_USBHOST" +# undef HAVE_USB +#endif + +#ifndef CONFIG_NUCLEOF207ZG_USBHOST_PRIO +# define CONFIG_NUCLEOF207ZG_USBHOST_PRIO 100 +#endif + +#ifndef CONFIG_NUCLEOF207ZG_USBHOST_STACKSIZE +# define CONFIG_NUCLEOF207ZG_USBHOST_STACKSIZE 1024 +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +static struct usbhost_connection_s *g_usbconn; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: usbhost_waiter + * + * Description: + * Wait for USB devices to be connected. + * + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +static int usbhost_waiter(int argc, char *argv[]) +{ + struct usbhost_hubport_s *hport; + + uinfo("Running\n"); + for (; ; ) + { + /* Wait for the device to change state */ + + DEBUGVERIFY(CONN_WAIT(g_usbconn, &hport)); + uinfo("%s\n", hport->connected ? "connected" : "disconnected"); + + /* Did we just become connected? */ + + if (hport->connected) + { + /* Yes.. enumerate the newly connected device */ + + CONN_ENUMERATE(g_usbconn, hport); + } + } + + /* Keep the compiler from complaining */ + + return 0; +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_usbinitialize + * + * Description: + * Called from stm32_usbinitialize very early in initialization to setup + * USB-related GPIO pins for the nucleo-144 board. + * + ****************************************************************************/ + +void stm32_usbinitialize(void) +{ + /* The OTG FS has an internal soft pull-up. + * No GPIO configuration is required + */ + + /* Configure the OTG FS VBUS sensing GPIO, + * Power On, and Overcurrent GPIOs + */ + +#ifdef CONFIG_STM32_OTGFS + stm32_configgpio(GPIO_OTGFS_VBUS); + stm32_configgpio(GPIO_OTGFS_PWRON); + stm32_configgpio(GPIO_OTGFS_OVER); +#endif +} + +/**************************************************************************** + * Name: stm32_usbhost_initialize + * + * Description: + * Called at application startup time to initialize the USB host + * functionality. + * This function will start a thread that will monitor for device + * connection/disconnection events. + * + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +int stm32_usbhost_initialize(void) +{ + int ret; + + /* First, register all of the class drivers needed to support the drivers + * that we care about: + */ + + uinfo("Register class drivers\n"); + +#ifdef CONFIG_USBHOST_HUB + /* Initialize USB hub class support */ + + ret = usbhost_hub_initialize(); + if (ret < 0) + { + uerr("ERROR: usbhost_hub_initialize failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_USBHOST_MSC + /* Register the USB mass storage class class */ + + ret = usbhost_msc_initialize(); + if (ret != OK) + { + uerr("ERROR: Failed to register the mass storage class: %d\n", ret); + } +#endif + +#ifdef CONFIG_USBHOST_CDCACM + /* Register the CDC/ACM serial class */ + + ret = usbhost_cdcacm_initialize(); + if (ret != OK) + { + uerr("ERROR: Failed to register the CDC/ACM serial class: %d\n", ret); + } +#endif + +#ifdef CONFIG_USBHOST_HIDKBD + /* Initialize the HID keyboard class */ + + ret = usbhost_kbdinit(); + if (ret != OK) + { + uerr("ERROR: Failed to register the HID keyboard class\n"); + } +#endif + +#ifdef CONFIG_USBHOST_HIDMOUSE + /* Initialize the HID mouse class */ + + ret = usbhost_mouse_init(); + if (ret != OK) + { + uerr("ERROR: Failed to register the HID mouse class\n"); + } +#endif + + /* Then get an instance of the USB host interface */ + + uinfo("Initialize USB host\n"); + g_usbconn = stm32_otgfshost_initialize(0); + if (g_usbconn) + { + /* Start a thread to handle device connection. */ + + uinfo("Start usbhost_waiter\n"); + + ret = kthread_create("usbhost", CONFIG_NUCLEOF207ZG_USBHOST_PRIO, + CONFIG_NUCLEOF207ZG_USBHOST_STACKSIZE, + usbhost_waiter, NULL); + return ret < 0 ? -ENOEXEC : OK; + } + + return -ENODEV; +} +#endif + +/**************************************************************************** + * Name: stm32_usbhost_vbusdrive + * + * Description: + * Enable/disable driving of VBUS 5V output. This function must be + * provided be each platform that implements the STM32 OTG FS host + * interface + * + * "On-chip 5 V VBUS generation is not supported. For this reason, a + * charge pump or, if 5 V are available on the application board, a + * basic power switch, must be added externally to drive the 5 V VBUS + * line. The external charge pump can be driven by any GPIO output. + * When the application decides to power on VBUS using the chosen GPIO, + * it must also set the port power bit in the host port control and + * status register (PPWR bit in OTG_FS_HPRT). + * + * "The application uses this field to control power to this port, + * and the core clears this bit on an overcurrent condition." + * + * Input Parameters: + * iface - For future growth to handle multiple USB host interface. + * Should be zero. + * enable - true: enable VBUS power; false: disable VBUS power + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +void stm32_usbhost_vbusdrive(int iface, bool enable) +{ + DEBUGASSERT(iface == 0); + + /* Set the Power Switch by driving the active low enable pin */ + + stm32_gpiowrite(GPIO_OTGFS_PWRON, !enable); +} +#endif + +/**************************************************************************** + * Name: stm32_setup_overcurrent + * + * Description: + * Setup to receive an interrupt-level callback if an overcurrent + * condition is detected. + * + * Input Parameters: + * handler - New overcurrent interrupt handler + * arg - The argument provided for the interrupt handler + * + * Returned Value: + * Zero (OK) is returned on success. Otherwise, a negated errno value + * is returned to indicate the nature of the failure. + * + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +int stm32_setup_overcurrent(xcpt_t handler, void *arg) +{ + return stm32_gpiosetevent(GPIO_OTGFS_OVER, true, true, true, handler, arg); +} +#endif + +/**************************************************************************** + * Name: stm32_usbsuspend + * + * Description: + * Board logic must provide the stm32_usbsuspend logic if the USBDEV + * driver is used. This function is called whenever the USB enters or + * leaves suspend mode. This is an opportunity for the board logic to + * shutdown clocks, power, etc. while the USB is suspended. + * + ****************************************************************************/ + +#ifdef CONFIG_USBDEV +void stm32_usbsuspend(struct usbdev_s *dev, bool resume) +{ + uinfo("resume: %d\n", resume); +} +#endif + +#endif /* CONFIG_STM32_OTGFS */ diff --git a/boards/arm/stm32f2/nucleo-f207zg/src/stm32_userleds.c b/boards/arm/stm32f2/nucleo-f207zg/src/stm32_userleds.c new file mode 100644 index 0000000000000..7ee325e6000c9 --- /dev/null +++ b/boards/arm/stm32f2/nucleo-f207zg/src/stm32_userleds.c @@ -0,0 +1,127 @@ +/**************************************************************************** + * boards/arm/stm32f2/nucleo-f207zg/src/stm32_userleds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include + +#include +#include + +#include "stm32_gpio.h" +#include "nucleo-f207zg.h" + +#ifndef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* This array maps an LED number to GPIO pin configuration and is indexed by + * BOARD_LED_ + */ + +static const uint32_t g_ledcfg[BOARD_NLEDS] = +{ + GPIO_LED_GREEN, + GPIO_LED_BLUE, + GPIO_LED_RED, +}; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_userled_initialize + * + * Description: + * If CONFIG_ARCH_LEDS is defined, then NuttX will control the on-board + * LEDs. If CONFIG_ARCH_LEDS is not defined, then the + * board_userled_initialize() is available to initialize the LED from user + * application logic. + * + ****************************************************************************/ + +uint32_t board_userled_initialize(void) +{ + int i; + + /* Configure LED1-3 GPIOs for output */ + + for (i = 0; i < nitems(g_ledcfg); i++) + { + stm32_configgpio(g_ledcfg[i]); + } + + return BOARD_NLEDS; +} + +/**************************************************************************** + * Name: board_userled + * + * Description: + * If CONFIG_ARCH_LEDS is defined, then NuttX will control the on-board + * LEDs. If CONFIG_ARCH_LEDS is not defined, then the board_userled() is + * available to control the LED from user application logic. + * + ****************************************************************************/ + +void board_userled(int led, bool ledon) +{ + if ((unsigned)led < nitems(g_ledcfg)) + { + stm32_gpiowrite(g_ledcfg[led], ledon); + } +} + +/**************************************************************************** + * Name: board_userled_all + * + * Description: + * If CONFIG_ARCH_LEDS is defined, then NuttX will control the on-board + * LEDs. If CONFIG_ARCH_LEDS is not defined, then the board_userled_all() + * is available to control the LED from user application logic. NOTE: since + * there is only a single LED on-board, this is function is not very useful. + * + ****************************************************************************/ + +void board_userled_all(uint32_t ledset) +{ + int i; + + /* Configure LED1-3 GPIOs for output */ + + for (i = 0; i < nitems(g_ledcfg); i++) + { + stm32_gpiowrite(g_ledcfg[i], (ledset & (1 << i)) != 0); + } +} + +#endif /* !CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32f2/olimex-stm32-p207/CMakeLists.txt b/boards/arm/stm32f2/olimex-stm32-p207/CMakeLists.txt new file mode 100644 index 0000000000000..f2381912c114f --- /dev/null +++ b/boards/arm/stm32f2/olimex-stm32-p207/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32f2/olimex-stm32-p207/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/arm/stm32/olimex-stm32-p207/Kconfig b/boards/arm/stm32f2/olimex-stm32-p207/Kconfig similarity index 100% rename from boards/arm/stm32/olimex-stm32-p207/Kconfig rename to boards/arm/stm32f2/olimex-stm32-p207/Kconfig diff --git a/boards/arm/stm32f2/olimex-stm32-p207/configs/nsh/defconfig b/boards/arm/stm32f2/olimex-stm32-p207/configs/nsh/defconfig new file mode 100644 index 0000000000000..d74bd22eb862f --- /dev/null +++ b/boards/arm/stm32f2/olimex-stm32-p207/configs/nsh/defconfig @@ -0,0 +1,82 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +CONFIG_ADC=y +CONFIG_ANALOG=y +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="olimex-stm32-p207" +CONFIG_ARCH_BOARD_OLIMEX_STM32P207=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f2" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F207ZE=y +CONFIG_ARCH_CHIP_STM32F2=y +CONFIG_ARCH_IRQBUTTONS=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_ARM_TOOLCHAIN_BUILDROOT=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_ETH0_PHY_KS8721=y +CONFIG_EXAMPLES_ADC=y +CONFIG_EXAMPLES_ADC_GROUPSIZE=1 +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_MM_REGIONS=2 +CONFIG_NET=y +CONFIG_NETDB_DNSCLIENT=y +CONFIG_NETINIT_DRIPADDR=0xa0000001 +CONFIG_NETINIT_IPADDR=0xa0000002 +CONFIG_NETINIT_NOMAC=y +CONFIG_NET_ICMP_SOCKET=y +CONFIG_NET_STATISTICS=y +CONFIG_NET_TCP=y +CONFIG_NET_UDP=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_DISABLE_GET=y +CONFIG_NSH_DISABLE_PUT=y +CONFIG_NSH_DISABLE_WGET=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=192 +CONFIG_SCHED_WAITPID=y +CONFIG_START_YEAR=2013 +CONFIG_STM32_ADC1=y +CONFIG_STM32_CAN1=y +CONFIG_STM32_CAN_TSEG2=8 +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_ETHMAC=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PHYSR=31 +CONFIG_STM32_PHYSR_100FD=0x18 +CONFIG_STM32_PHYSR_100HD=0x8 +CONFIG_STM32_PHYSR_10FD=0x14 +CONFIG_STM32_PHYSR_10HD=0x4 +CONFIG_STM32_PHYSR_ALTCONFIG=y +CONFIG_STM32_PHYSR_ALTMODE=0x1c +CONFIG_STM32_PWR=y +CONFIG_STM32_RMII_EXTCLK=y +CONFIG_STM32_TIM1=y +CONFIG_STM32_TIM1_ADC=y +CONFIG_STM32_USART3=y +CONFIG_SYSTEM_NSH=y +CONFIG_SYSTEM_PING=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART3_SERIAL_CONSOLE=y +CONFIG_USBHOST=y diff --git a/boards/arm/stm32f2/olimex-stm32-p207/include/board.h b/boards/arm/stm32f2/olimex-stm32-p207/include/board.h new file mode 100644 index 0000000000000..7ad51256922fb --- /dev/null +++ b/boards/arm/stm32f2/olimex-stm32-p207/include/board.h @@ -0,0 +1,241 @@ +/**************************************************************************** + * boards/arm/stm32f2/olimex-stm32-p207/include/board.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_STM32_OLIMEX_STM32_P207_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32_OLIMEX_STM32_P207_INCLUDE_BOARD_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#ifndef __ASSEMBLY__ +# include +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Clocking *****************************************************************/ + +/* HSI - 16 MHz RC factory-trimmed + * LSI - 32 KHz RC (30-60KHz, uncalibrated) + * HSE - On-board crystal frequency is 25MHz + * LSE - 32.768 kHz + */ + +#define STM32_BOARD_XTAL 25000000ul + +#define STM32_HSI_FREQUENCY 16000000ul +#define STM32_LSI_FREQUENCY 32000 +#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL +#define STM32_LSE_FREQUENCY 32768 + +/* Main PLL Configuration. + * + * PLL source is HSE + * PLL_VCO = (STM32_HSE_FREQUENCY / PLLM) * PLLN + * = (25,000,000 / 25) * 240 + * = 240,000,000 + * SYSCLK = PLL_VCO / PLLP + * = 240,000,000 / 2 = 120,000,000 + * USB OTG FS, SDIO and RNG Clock + * = PLL_VCO / PLLQ + * = 240,000,000 / 5 = 48,000,000 + * = 48,000,000 + */ + +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(25) +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(240) +#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_2 +#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(5) + +#define STM32_SYSCLK_FREQUENCY 120000000ul + +/* AHB clock (HCLK) is SYSCLK (120MHz) */ + +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY + +/* APB1 clock (PCLK1) is HCLK/4 (30MHz) */ + +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd4 /* PCLK1 = HCLK / 4 */ +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/4) + +/* Timers driven from APB1 will be twice PCLK1 (60Mhz) */ + +#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) + +/* APB2 clock (PCLK2) is HCLK/2 (60MHz) */ + +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLKd2 /* PCLK2 = HCLK / 2 */ +#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/2) + +/* Timers driven from APB2 will be twice PCLK2 (120Mhz) */ + +#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM9_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM10_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM11_CLKIN (2*STM32_PCLK2_FREQUENCY) + +/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx + * otherwise frequency is 2xAPBx. + * Note: TIM1,8 are on APB2, others on APB1 + */ + +#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM2_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM3_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM4_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM5_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM6_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM7_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY + +/* LED definitions **********************************************************/ + +/* If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs in + * any way. The following definitions are used to access individual LEDs. + */ + +/* LED index values for use with board_userled() */ + +#define BOARD_LED1 0 +#define BOARD_LED2 1 +#define BOARD_LED3 2 +#define BOARD_LED4 3 +#define BOARD_NLEDS 4 + +#define BOARD_LED_GREEN1 BOARD_LED1 +#define BOARD_LED_YELLOW BOARD_LED2 +#define BOARD_LED_RED BOARD_LED3 +#define BOARD_LED_GREEN2 BOARD_LED4 + +/* LED bits for use with board_userled_all() */ + +#define BOARD_LED1_BIT (1 << BOARD_LED1) +#define BOARD_LED2_BIT (1 << BOARD_LED2) +#define BOARD_LED3_BIT (1 << BOARD_LED3) +#define BOARD_LED4_BIT (1 << BOARD_LED4) + +/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the 4 LEDs on + * board the Olimex STM32-P207. + * The following definitions describe how NuttX controls the LEDs: + */ + +#define LED_STARTED 0 /* LED1 */ +#define LED_HEAPALLOCATE 1 /* LED2 */ +#define LED_IRQSENABLED 2 /* LED1 + LED2 */ +#define LED_STACKCREATED 3 /* LED3 */ +#define LED_INIRQ 4 /* LED1 + LED3 */ +#define LED_SIGNAL 5 /* LED2 + LED3 */ +#define LED_ASSERTION 6 /* LED1 + LED2 + LED3 */ +#define LED_PANIC 7 /* N/C + N/C + N/C + LED4 */ + +/* Button definitions *******************************************************/ + +/* The Olimex STM32-P207 supports seven buttons: */ + +#define BUTTON_TAMPER 0 +#define BUTTON_WKUP 1 +#define BUTTON_RIGHT 2 +#define BUTTON_UP 3 +#define BUTTON_LEFT 4 +#define BUTTON_DOWN 5 +#define BUTTON_CENTER 6 + +#define NUM_BUTTONS 7 + +#define BUTTON_TAMPER_BIT (1 << BUTTON_TAMPER) +#define BUTTON_WKUP_BIT (1 << BUTTON_WKUP) +#define BUTTON_RIGHT_BIT (1 << BUTTON_RIGHT) +#define BUTTON_UP_BIT (1 << BUTTON_UP) +#define BUTTON_LEFT_BIT (1 << BUTTON_LEFT) +#define BUTTON_DOWN_BIT (1 << BUTTON_DOWN) +#define BUTTON_CENTER_BIT (1 << BUTTON_CENTER) + +/* Alternate function pin selections ****************************************/ + +/* USART3: */ +#define GPIO_USART3_RX (GPIO_USART3_RX_3|GPIO_SPEED_100MHz) /* PD9 */ +#define GPIO_USART3_TX (GPIO_USART3_TX_3|GPIO_SPEED_100MHz) /* PD8 */ +#define GPIO_USART3_CTS GPIO_USART3_CTS_2 /* PD11 */ +#define GPIO_USART3_RTS GPIO_USART3_RTS_2 /* PD12 */ + +/* CAN: */ +#define GPIO_CAN1_RX (GPIO_CAN1_RX_2|GPIO_SPEED_50MHz) /* PB8 */ +#define GPIO_CAN1_TX (GPIO_CAN1_TX_2|GPIO_SPEED_50MHz) /* PB9 */ + +/* Ethernet: */ + +/* - PA2 is ETH_MDIO + * - PC1 is ETH_MDC + * - PB5 is ETH_PPS_OUT - NC (not connected) + * - PA0 is ETH_MII_CRS - NC + * - PA3 is ETH_MII_COL - NC + * - PB10 is ETH_MII_RX_ER - NC + * - PB0 is ETH_MII_RXD2 - NC + * - PH7 is ETH_MII_RXD3 - NC + * - PC3 is ETH_MII_TX_CLK - NC + * - PC2 is ETH_MII_TXD2 - NC + * - PB8 is ETH_MII_TXD3 - NC + * - PA1 is ETH_MII_RX_CLK/ETH_RMII_REF_CLK + * - PA7 is ETH_MII_RX_DV/ETH_RMII_CRS_DV + * - PC4 is ETH_MII_RXD0/ETH_RMII_RXD0 + * - PC5 is ETH_MII_RXD1/ETH_RMII_RXD1 + * - PB11 is ETH_MII_TX_EN/ETH_RMII_TX_EN + * - PG13 is ETH_MII_TXD0/ETH_RMII_TXD0 + * - PG14 is ETH_MII_TXD1/ETH_RMII_TXD1 + */ + +#define GPIO_ETH_MDC (GPIO_ETH_MDC_0|GPIO_SPEED_100MHz) +#define GPIO_ETH_MDIO (GPIO_ETH_MDIO_0|GPIO_SPEED_100MHz) +#define GPIO_ETH_RMII_CRS_DV (GPIO_ETH_RMII_CRS_DV_0|GPIO_SPEED_100MHz) +#define GPIO_ETH_RMII_REF_CLK (GPIO_ETH_RMII_REF_CLK_0|GPIO_SPEED_100MHz) +#define GPIO_ETH_RMII_RXD0 (GPIO_ETH_RMII_RXD0_0|GPIO_SPEED_100MHz) +#define GPIO_ETH_RMII_RXD1 (GPIO_ETH_RMII_RXD1_0|GPIO_SPEED_100MHz) +#define GPIO_ETH_PPS_OUT (GPIO_ETH_PPS_OUT_1|GPIO_SPEED_100MHz) +#define GPIO_ETH_MII_CRS (GPIO_ETH_MII_CRS_1|GPIO_SPEED_100MHz) +#define GPIO_ETH_MII_COL (GPIO_ETH_MII_COL_1|GPIO_SPEED_100MHz) +#define GPIO_ETH_MII_RX_ER (GPIO_ETH_MII_RX_ER_1|GPIO_SPEED_100MHz) +#define GPIO_ETH_MII_RXD2 (GPIO_ETH_MII_RXD2_1|GPIO_SPEED_100MHz) +#define GPIO_ETH_MII_RXD3 (GPIO_ETH_MII_RXD3_1|GPIO_SPEED_100MHz) +#define GPIO_ETH_MII_TXD3 (GPIO_ETH_MII_TXD3_1|GPIO_SPEED_100MHz) +#define GPIO_ETH_MII_TX_EN (GPIO_ETH_MII_TX_EN_2|GPIO_SPEED_100MHz) +#define GPIO_ETH_MII_TXD0 (GPIO_ETH_MII_TXD0_2|GPIO_SPEED_100MHz) +#define GPIO_ETH_MII_TXD1 (GPIO_ETH_MII_TXD1_2|GPIO_SPEED_100MHz) +#define GPIO_ETH_RMII_TX_EN (GPIO_ETH_RMII_TX_EN_1|GPIO_SPEED_100MHz) +#define GPIO_ETH_RMII_TXD0 (GPIO_ETH_RMII_TXD0_2|GPIO_SPEED_100MHz) +#define GPIO_ETH_RMII_TXD1 (GPIO_ETH_RMII_TXD1_2|GPIO_SPEED_100MHz) + +#endif /* __BOARDS_ARM_STM32_OLIMEX_STM32_P207_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32f2/olimex-stm32-p207/scripts/Make.defs b/boards/arm/stm32f2/olimex-stm32-p207/scripts/Make.defs new file mode 100644 index 0000000000000..d8143a48feef7 --- /dev/null +++ b/boards/arm/stm32f2/olimex-stm32-p207/scripts/Make.defs @@ -0,0 +1,41 @@ +############################################################################ +# boards/arm/stm32f2/olimex-stm32-p207/scripts/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/.config +include $(TOPDIR)/tools/Config.mk +include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs + +LDSCRIPT = ld.script +ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) + +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-gotoff.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32f2/olimex-stm32-p207/scripts/ld.script b/boards/arm/stm32f2/olimex-stm32-p207/scripts/ld.script new file mode 100644 index 0000000000000..b658404f87cdc --- /dev/null +++ b/boards/arm/stm32f2/olimex-stm32-p207/scripts/ld.script @@ -0,0 +1,125 @@ +/**************************************************************************** + * boards/arm/stm32f2/olimex-stm32-p207/scripts/ld.script + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* The STM32F207ZET6 has 512Kb of FLASH beginning at address 0x0800:0000 and + * 128Kb of SRAM. SRAM is split up into two blocks: + * + * 1) 112Kb of SRAM beginning at address 0x2000:0000 + * 2) 16Kb of SRAM beginning at address 0x2001:c000 + * + * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 + * where the code expects to begin execution by jumping to the entry point in + * the 0x0800:0000 address + * range. + */ + +MEMORY +{ + flash (rx) : ORIGIN = 0x08000000, LENGTH = 512K + sram (rwx) : ORIGIN = 0x20000000, LENGTH = 112K +} + +OUTPUT_ARCH(arm) +EXTERN(_vectors) +ENTRY(_stext) +SECTIONS +{ + .text : { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > flash + + .init_section : ALIGN(4) { + _sinit = ABSOLUTE(.); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) + _einit = ABSOLUTE(.); + } > flash + + .ARM.extab : ALIGN(4) { + *(.ARM.extab*) + } > flash + + .ARM.exidx : ALIGN(4) { + __exidx_start = ABSOLUTE(.); + *(.ARM.exidx*) + __exidx_end = ABSOLUTE(.); + } > flash + + .tdata : { + _stdata = ABSOLUTE(.); + *(.tdata .tdata.* .gnu.linkonce.td.*); + _etdata = ABSOLUTE(.); + } > flash + + .tbss : { + _stbss = ABSOLUTE(.); + *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); + _etbss = ABSOLUTE(.); + } > flash + + _eronly = ABSOLUTE(.); + + .data : ALIGN(4) { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > sram AT > flash + + .bss : ALIGN(4) { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + _ebss = ABSOLUTE(.); + } > sram + + /* Stabs debugging sections. */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/stm32f2/olimex-stm32-p207/src/CMakeLists.txt b/boards/arm/stm32f2/olimex-stm32-p207/src/CMakeLists.txt new file mode 100644 index 0000000000000..1f6060c53a7c4 --- /dev/null +++ b/boards/arm/stm32f2/olimex-stm32-p207/src/CMakeLists.txt @@ -0,0 +1,49 @@ +# ############################################################################## +# boards/arm/stm32f2/olimex-stm32-p207/src/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(SRCS stm32_boot.c) + +if(CONFIG_ARCH_LEDS) + list(APPEND SRCS stm32_autoleds.c) +else() + list(APPEND SRCS stm32_userleds.c) +endif() + +if(CONFIG_ARCH_BUTTONS) + list(APPEND SRCS stm32_buttons.c) +endif() + +if(CONFIG_STM32_OTGFS) + list(APPEND SRCS stm32_usb.c) +endif() + +if(CONFIG_ADC) + list(APPEND SRCS stm32_adc.c) +endif() + +if(CONFIG_STM32_CAN_CHARDRIVER) + list(APPEND SRCS stm32_can.c) +endif() + +target_sources(board PRIVATE ${SRCS}) + +set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/ld.script") diff --git a/boards/arm/stm32f2/olimex-stm32-p207/src/Make.defs b/boards/arm/stm32f2/olimex-stm32-p207/src/Make.defs new file mode 100644 index 0000000000000..f506294680bc3 --- /dev/null +++ b/boards/arm/stm32f2/olimex-stm32-p207/src/Make.defs @@ -0,0 +1,51 @@ +############################################################################ +# boards/arm/stm32f2/olimex-stm32-p207/src/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +CSRCS = stm32_boot.c + +ifeq ($(CONFIG_ARCH_LEDS),y) +CSRCS += stm32_autoleds.c +else +CSRCS += stm32_userleds.c +endif + +ifeq ($(CONFIG_ARCH_BUTTONS),y) +CSRCS += stm32_buttons.c +endif + +ifeq ($(CONFIG_STM32_OTGFS),y) +CSRCS += stm32_usb.c +endif + +ifeq ($(CONFIG_ADC),y) +CSRCS += stm32_adc.c +endif + +ifeq ($(CONFIG_STM32_CAN_CHARDRIVER),y) +CSRCS += stm32_can.c +endif + +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/olimex-stm32-p207/src/olimex-stm32-p207.h b/boards/arm/stm32f2/olimex-stm32-p207/src/olimex-stm32-p207.h similarity index 98% rename from boards/arm/stm32/olimex-stm32-p207/src/olimex-stm32-p207.h rename to boards/arm/stm32f2/olimex-stm32-p207/src/olimex-stm32-p207.h index 5f69d7f4934bd..30f8489f63342 100644 --- a/boards/arm/stm32/olimex-stm32-p207/src/olimex-stm32-p207.h +++ b/boards/arm/stm32f2/olimex-stm32-p207/src/olimex-stm32-p207.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/olimex-stm32-p207/src/olimex-stm32-p207.h + * boards/arm/stm32f2/olimex-stm32-p207/src/olimex-stm32-p207.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f2/olimex-stm32-p207/src/stm32_adc.c b/boards/arm/stm32f2/olimex-stm32-p207/src/stm32_adc.c new file mode 100644 index 0000000000000..4c75b624f493e --- /dev/null +++ b/boards/arm/stm32f2/olimex-stm32-p207/src/stm32_adc.c @@ -0,0 +1,156 @@ +/**************************************************************************** + * boards/arm/stm32f2/olimex-stm32-p207/src/stm32_adc.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include +#include + +#include "chip.h" +#include "stm32_adc.h" +#include "olimex-stm32-p207.h" + +#ifdef CONFIG_ADC + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* Up to 3 ADC interfaces are supported */ + +#if STM32_NADC < 3 +# undef CONFIG_STM32_ADC3 +#endif + +#if STM32_NADC < 2 +# undef CONFIG_STM32_ADC2 +#endif + +#if STM32_NADC < 1 +# undef CONFIG_STM32_ADC1 +#endif + +#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) || defined(CONFIG_STM32_ADC3) +#ifndef CONFIG_STM32_ADC1 +# warning "Channel information only available for ADC1" +#endif + +/* The number of ADC channels in the conversion list */ + +#define ADC1_NCHANNELS 1 + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* The Olimex STM32-P207 has a 10 Kohm potentiometer AN_TR connected to PC0 + * ADC123_IN10 + */ + +/* Identifying number of each ADC channel: Variable Resistor. */ + +#ifdef CONFIG_STM32_ADC1 +static const uint8_t g_chanlist[ADC1_NCHANNELS] = +{ + 10 +}; + +/* Configurations of pins used byte each ADC channels */ + +static const uint32_t g_pinlist[ADC1_NCHANNELS] = +{ + GPIO_ADC1_IN10_0 +}; +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_adc_setup + * + * Description: + * Initialize ADC and register the ADC driver. + * + ****************************************************************************/ + +int stm32_adc_setup(void) +{ +#ifdef CONFIG_STM32_ADC1 + static bool initialized = false; + struct adc_dev_s *adc; + int ret; + int i; + + /* Check if we have already initialized */ + + if (!initialized) + { + /* Configure the pins as analog inputs for the selected channels */ + + for (i = 0; i < ADC1_NCHANNELS; i++) + { + stm32_configgpio(g_pinlist[i]); + } + + /* Call stm32_adcinitialize() to get an instance of the ADC interface */ + + adc = stm32_adcinitialize(1, g_chanlist, ADC1_NCHANNELS); + if (adc == NULL) + { + aerr("ERROR: Failed to get ADC interface\n"); + return -ENODEV; + } + + /* Register the ADC driver at "/dev/adc0" */ + + ret = adc_register("/dev/adc0", adc); + if (ret < 0) + { + aerr("ERROR: adc_register failed: %d\n", ret); + return ret; + } + + /* Now we are initialized */ + + initialized = true; + } + + return OK; +#else + return -ENOSYS; +#endif +} + +#endif /* CONFIG_STM32_ADC1 || CONFIG_STM32_ADC2 || CONFIG_STM32_ADC3 */ +#endif /* CONFIG_ADC */ diff --git a/boards/arm/stm32f2/olimex-stm32-p207/src/stm32_autoleds.c b/boards/arm/stm32f2/olimex-stm32-p207/src/stm32_autoleds.c new file mode 100644 index 0000000000000..a748ff57c4c23 --- /dev/null +++ b/boards/arm/stm32f2/olimex-stm32-p207/src/stm32_autoleds.c @@ -0,0 +1,160 @@ +/**************************************************************************** + * boards/arm/stm32f2/olimex-stm32-p207/src/stm32_autoleds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "stm32.h" +#include "olimex-stm32-p207.h" + +#ifdef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* The following definitions map the encoded LED setting to GPIO settings */ + +#define LED_STARTED_BITS (BOARD_LED1_BIT) +#define LED_HEAPALLOCATE_BITS (BOARD_LED2_BIT) +#define LED_IRQSENABLED_BITS (BOARD_LED1_BIT | BOARD_LED2_BIT) +#define LED_STACKCREATED_BITS (BOARD_LED3_BIT) +#define LED_INIRQ_BITS (BOARD_LED1_BIT | BOARD_LED3_BIT) +#define LED_SIGNAL_BITS (BOARD_LED2_BIT | BOARD_LED3_BIT) +#define LED_ASSERTION_BITS (BOARD_LED1_BIT | BOARD_LED2_BIT | BOARD_LED3_BIT) +#define LED_PANIC_BITS (BOARD_LED4_BIT) + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static const unsigned int g_ledbits[8] = +{ + LED_STARTED_BITS, + LED_HEAPALLOCATE_BITS, + LED_IRQSENABLED_BITS, + LED_STACKCREATED_BITS, + LED_INIRQ_BITS, + LED_SIGNAL_BITS, + LED_ASSERTION_BITS, + LED_PANIC_BITS +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +static inline void led_clrbits(unsigned int clrbits) +{ + if ((clrbits & BOARD_LED1_BIT) != 0) + { + stm32_gpiowrite(GPIO_LED1, false); + } + + if ((clrbits & BOARD_LED2_BIT) != 0) + { + stm32_gpiowrite(GPIO_LED2, false); + } + + if ((clrbits & BOARD_LED3_BIT) != 0) + { + stm32_gpiowrite(GPIO_LED3, false); + } + + if ((clrbits & BOARD_LED4_BIT) != 0) + { + stm32_gpiowrite(GPIO_LED4, false); + } +} + +static inline void led_setbits(unsigned int setbits) +{ + if ((setbits & BOARD_LED1_BIT) != 0) + { + stm32_gpiowrite(GPIO_LED1, true); + } + + if ((setbits & BOARD_LED2_BIT) != 0) + { + stm32_gpiowrite(GPIO_LED2, true); + } + + if ((setbits & BOARD_LED3_BIT) != 0) + { + stm32_gpiowrite(GPIO_LED3, true); + } + + if ((setbits & BOARD_LED4_BIT) != 0) + { + stm32_gpiowrite(GPIO_LED4, true); + } +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_autoled_initialize + ****************************************************************************/ + +void board_autoled_initialize(void) +{ + /* Configure LED1-4 GPIOs for output */ + + stm32_configgpio(GPIO_LED1); + stm32_configgpio(GPIO_LED2); + stm32_configgpio(GPIO_LED3); + stm32_configgpio(GPIO_LED4); +} + +/**************************************************************************** + * Name: board_autoled_on + ****************************************************************************/ + +void board_autoled_on(int led) +{ + led_clrbits(BOARD_LED1_BIT | BOARD_LED2_BIT | + BOARD_LED3_BIT | BOARD_LED4_BIT); + led_setbits(g_ledbits[led]); +} + +/**************************************************************************** + * Name: board_autoled_off + ****************************************************************************/ + +void board_autoled_off(int led) +{ + led_clrbits(g_ledbits[led]); +} + +#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32f2/olimex-stm32-p207/src/stm32_boot.c b/boards/arm/stm32f2/olimex-stm32-p207/src/stm32_boot.c new file mode 100644 index 0000000000000..1fee37320cfcf --- /dev/null +++ b/boards/arm/stm32f2/olimex-stm32-p207/src/stm32_boot.c @@ -0,0 +1,205 @@ +/**************************************************************************** + * boards/arm/stm32f2/olimex-stm32-p207/src/stm32_boot.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include +#include +#include +#include + +#include +#include +#include + +#ifdef CONFIG_USBMONITOR +# include +#endif + +#ifdef CONFIG_STM32_OTGFS +# include "stm32_usbhost.h" +#endif + +#include "stm32.h" +#include "olimex-stm32-p207.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +#define HAVE_USBDEV 1 +#define HAVE_USBHOST 1 +#define HAVE_USBMONITOR 1 + +/* Can't support USB host or device features if USB OTG FS is not enabled */ + +#ifndef CONFIG_STM32_OTGFS +# undef HAVE_USBDEV +# undef HAVE_USBHOST +#endif + +/* Can't support USB device if USB device is not enabled */ + +#ifndef CONFIG_USBDEV +# undef HAVE_USBDEV +#endif + +/* Can't support USB host is USB host is not enabled */ + +#ifndef CONFIG_STM32_USBHOST +# undef CONFIG_USBHOST +# undef HAVE_USBHOST +#endif + +/* Check if we should enable the USB monitor before starting NSH */ + +#ifndef CONFIG_USBMONITOR +# undef HAVE_USBMONITOR +#endif + +#ifndef HAVE_USBDEV +# undef CONFIG_USBDEV_TRACE +#endif + +#ifndef HAVE_USBHOST +# undef CONFIG_USBHOST_TRACE +#endif + +#if !defined(CONFIG_USBDEV_TRACE) && !defined(CONFIG_USBHOST_TRACE) +# undef HAVE_USBMONITOR +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_boardinitialize + * + * Description: + * All STM32 architectures must provide the following entry point. + * This entry point is called early in the initialization -- after all + * memory has been configured and mapped but before any devices have been + * initialized. + * + ****************************************************************************/ + +void stm32_boardinitialize(void) +{ + /* Initialize USB if the 1) OTG FS controller is in the configuration and + * 2) disabled, and 3) the weak function stm32_usbinitialize() has been + * brought into the build. + * Presumably either CONFIG_USBDEV or CONFIG_USBHOST is also selected. + */ + +#ifdef CONFIG_STM32_OTGFS + if (stm32_usbinitialize) + { + stm32_usbinitialize(); + } +#endif + + /* Configure on-board LEDs if LED support has been selected. */ + +#ifdef CONFIG_ARCH_LEDS + board_autoled_initialize(); +#endif + + /* Configure on-board BUTTONs if BUTTON support has been selected. */ + +#ifdef CONFIG_ARCH_BUTTONS + board_button_initialize(); +#endif +} + +/**************************************************************************** + * Name: board_late_initialize + * + * Description: + * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_late_initialize(). board_late_initialize() will be + * called immediately after up_initialize() is called and just before the + * initial application is started. This additional initialization phase + * may be used, for example, to initialize board-specific device drivers. + * + ****************************************************************************/ + +#ifdef CONFIG_BOARD_LATE_INITIALIZE +void board_late_initialize(void) +{ + int ret; + +#ifdef CONFIG_STM32_CAN_CHARDRIVER + /* Initialize CAN and register the CAN driver. */ + + ret = stm32_can_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_can_setup failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_ADC + /* Initialize ADC and register the ADC driver. */ + + ret = stm32_adc_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_adc_setup failed: %d\n", ret); + } +#endif + +#ifdef HAVE_USBHOST + /* Initialize USB host operation. stm32_usbhost_initialize() starts a + * thread will monitor for USB connection and disconnection events. + */ + + ret = stm32_usbhost_initialize(); + if (ret != OK) + { + syslog(LOG_ERR, "ERROR: Failed to initialize USB host: %d\n", ret); + return; + } +#endif + +#ifdef HAVE_USBMONITOR + /* Start the USB Monitor */ + + ret = usbmonitor_start(); + if (ret != OK) + { + syslog(LOG_ERR, "ERROR: Failed to start USB monitor: %d\n", ret); + } +#endif + + UNUSED(ret); +} +#endif diff --git a/boards/arm/stm32f2/olimex-stm32-p207/src/stm32_buttons.c b/boards/arm/stm32f2/olimex-stm32-p207/src/stm32_buttons.c new file mode 100644 index 0000000000000..20089fe607e81 --- /dev/null +++ b/boards/arm/stm32f2/olimex-stm32-p207/src/stm32_buttons.c @@ -0,0 +1,176 @@ +/**************************************************************************** + * boards/arm/stm32f2/olimex-stm32-p207/src/stm32_buttons.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include +#include + +#include "olimex-stm32-p207.h" + +#ifdef CONFIG_ARCH_BUTTONS + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* Pin configuration for each STM32F4 Discovery button. This array is indexed + * by the BUTTON_* definitions in board.h + */ + +static const uint32_t g_buttons[NUM_BUTTONS] = +{ + GPIO_BTN_TAMPER, + GPIO_BTN_WKUP, + GPIO_BTN_RIGHT, + GPIO_BTN_UP, + GPIO_BTN_LEFT, + GPIO_BTN_DOWN, + GPIO_BTN_CENTER +}; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_button_initialize + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. + * + ****************************************************************************/ + +uint32_t board_button_initialize(void) +{ + int i; + + /* Configure the GPIO pins as inputs. NOTE that EXTI interrupts are + * configured for all pins. + */ + + for (i = 0; i < NUM_BUTTONS; i++) + { + stm32_configgpio(g_buttons[i]); + } + + return NUM_BUTTONS; +} + +/**************************************************************************** + * Name: board_buttons + ****************************************************************************/ + +uint32_t board_buttons(void) +{ + uint32_t ret = 0; + + /* Check that state of each key */ + + if (!stm32_gpioread(g_buttons[BUTTON_TAMPER])) + { + ret |= BUTTON_TAMPER_BIT; + } + + if (stm32_gpioread(g_buttons[BUTTON_WKUP])) + { + ret |= BUTTON_WKUP_BIT; + } + + if (stm32_gpioread(g_buttons[BUTTON_RIGHT])) + { + ret |= BUTTON_RIGHT_BIT; + } + + if (stm32_gpioread(g_buttons[BUTTON_UP])) + { + ret |= BUTTON_UP_BIT; + } + + if (stm32_gpioread(g_buttons[BUTTON_LEFT])) + { + ret |= BUTTON_LEFT_BIT; + } + + if (stm32_gpioread(g_buttons[BUTTON_DOWN])) + { + ret |= BUTTON_DOWN_BIT; + } + + if (stm32_gpioread(g_buttons[BUTTON_CENTER])) + { + ret |= BUTTON_CENTER_BIT; + } + + return ret; +} + +/**************************************************************************** + * Button support. + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. + * + * After board_button_initialize() has been called, board_buttons() may be + * called to collect the state of all buttons. board_buttons() returns an + * 32-bit bit set with each bit associated with a button. See the + * BUTTON_*_BIT definitions in board.h for the meaning of each bit. + * + * board_button_irq() may be called to register an interrupt handler that + * will be called when a button is depressed or released. The ID value is a + * button enumeration value that uniquely identifies a button resource. See + * the BUTTON_* definitions in board.h for the meaning of enumeration + * value. + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_IRQBUTTONS +int board_button_irq(int id, xcpt_t irqhandler, void *arg) +{ + int ret = -EINVAL; + + /* The following should be atomic */ + + if (id >= MIN_IRQBUTTON && id <= MAX_IRQBUTTON) + { + ret = stm32_gpiosetevent(g_buttons[id], true, true, true, + irqhandler, arg); + } + + return ret; +} +#endif +#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/stm32f2/olimex-stm32-p207/src/stm32_can.c b/boards/arm/stm32f2/olimex-stm32-p207/src/stm32_can.c new file mode 100644 index 0000000000000..f64cb2f25b3e6 --- /dev/null +++ b/boards/arm/stm32f2/olimex-stm32-p207/src/stm32_can.c @@ -0,0 +1,100 @@ +/**************************************************************************** + * boards/arm/stm32f2/olimex-stm32-p207/src/stm32_can.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include + +#include "stm32.h" +#include "stm32_can.h" +#include "olimex-stm32-p207.h" + +#ifdef CONFIG_CAN + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +#if defined(CONFIG_STM32_CAN1) && defined(CONFIG_STM32_CAN2) +# warning "Both CAN1 and CAN2 are enabled. Only CAN1 is connected." +# undef CONFIG_STM32_CAN2 +#endif + +#ifdef CONFIG_STM32_CAN1 +# define CAN_PORT 1 +#else +# define CAN_PORT 2 +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_can_setup + * + * Description: + * Initialize CAN and register the CAN device + * + ****************************************************************************/ + +int stm32_can_setup(void) +{ +#if defined(CONFIG_STM32_CAN1) || defined(CONFIG_STM32_CAN2) + struct can_dev_s *can; + int ret; + + /* Call stm32_caninitialize() to get an instance of the CAN interface */ + + can = stm32_caninitialize(CAN_PORT); + if (can == NULL) + { + canerr("ERROR: Failed to get CAN interface\n"); + return -ENODEV; + } + + /* Register the CAN driver at "/dev/can0" */ + + ret = can_register("/dev/can0", can); + if (ret < 0) + { + canerr("ERROR: can_register failed: %d\n", ret); + return ret; + } + + return OK; +#else + return -ENODEV; +#endif +} + +#endif /* CONFIG_CAN */ diff --git a/boards/arm/stm32f2/olimex-stm32-p207/src/stm32_usb.c b/boards/arm/stm32f2/olimex-stm32-p207/src/stm32_usb.c new file mode 100644 index 0000000000000..3931c992d829b --- /dev/null +++ b/boards/arm/stm32f2/olimex-stm32-p207/src/stm32_usb.c @@ -0,0 +1,313 @@ +/**************************************************************************** + * boards/arm/stm32f2/olimex-stm32-p207/src/stm32_usb.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include "stm32.h" +#include "stm32_otgfs.h" +#include "olimex-stm32-p207.h" + +#ifdef CONFIG_STM32_OTGFS + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#if defined(CONFIG_USBDEV) || defined(CONFIG_USBHOST) +# define HAVE_USB 1 +#else +# warning "CONFIG_STM32_OTGFS is enabled but neither CONFIG_USBDEV nor CONFIG_USBHOST" +# undef HAVE_USB +#endif + +#ifndef CONFIG_USBHOST_DEFPRIO +# define CONFIG_USBHOST_DEFPRIO 50 +#endif + +#ifndef CONFIG_USBHOST_STACKSIZE +# ifdef CONFIG_USBHOST_HUB +# define CONFIG_USBHOST_STACKSIZE 1536 +# else +# define CONFIG_USBHOST_STACKSIZE 1024 +# endif +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#ifdef CONFIG_STM32_USBHOST +static struct usbhost_connection_s *g_usbconn; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: usbhost_waiter + * + * Description: + * Wait for USB devices to be connected. + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_USBHOST +static int usbhost_waiter(int argc, char *argv[]) +{ + struct usbhost_hubport_s *hport; + + uinfo("Running\n"); + for (; ; ) + { + /* Wait for the device to change state */ + + DEBUGVERIFY(CONN_WAIT(g_usbconn, &hport)); + uinfo("%s\n", hport->connected ? "connected" : "disconnected"); + + /* Did we just become connected? */ + + if (hport->connected) + { + /* Yes.. enumerate the newly connected device */ + + CONN_ENUMERATE(g_usbconn, hport); + } + } + + /* Keep the compiler from complaining */ + + return 0; +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_usbinitialize + * + * Description: + * Called from stm32_usbinitialize very early in initialization to setup + * USB-related GPIO pins for the STM32F4Discovery board. + * + ****************************************************************************/ + +void stm32_usbinitialize(void) +{ + /* The OTG FS has an internal soft pull-up. + * No GPIO configuration is required + */ + + /* Configure the OTG FS VBUS sensing GPIO, + * Power On, and Overcurrent GPIOs + */ + +#ifdef CONFIG_STM32_OTGFS + stm32_configgpio(GPIO_OTGFS_VBUS); + stm32_configgpio(GPIO_OTGFS_PWRON); + stm32_configgpio(GPIO_OTGFS_OVER); +#endif +} + +/**************************************************************************** + * Name: stm32_usbhost_initialize + * + * Description: + * Called at application startup time to initialize the USB host + * functionality. + * This function will start a thread that will monitor for device + * connection/disconnection events. + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_USBHOST +int stm32_usbhost_initialize(void) +{ + int ret; + + /* First, register all of the class drivers needed to support the drivers + * that we care about: + */ + + uinfo("Register class drivers\n"); + +#ifdef CONFIG_USBHOST_HUB + /* Initialize USB hub class support */ + + ret = usbhost_hub_initialize(); + if (ret < 0) + { + uerr("ERROR: usbhost_hub_initialize failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_USBHOST_MSC + /* Register the USB host Mass Storage Class */ + + ret = usbhost_msc_initialize(); + if (ret != OK) + { + uerr("ERROR: Failed to register the mass storage class: %d\n", ret); + } +#endif + +#ifdef CONFIG_USBHOST_CDCACM + /* Register the CDC/ACM serial class */ + + ret = usbhost_cdcacm_initialize(); + if (ret != OK) + { + uerr("ERROR: Failed to register the CDC/ACM serial class: %d\n", ret); + } +#endif + + /* Then get an instance of the USB host interface */ + + uinfo("Initialize USB host\n"); + g_usbconn = stm32_otgfshost_initialize(0); + if (g_usbconn) + { + /* Start a thread to handle device connection. */ + + uinfo("Start usbhost_waiter\n"); + + ret = kthread_create("usbhost", CONFIG_USBHOST_DEFPRIO, + CONFIG_USBHOST_STACKSIZE, + usbhost_waiter, NULL); + return ret < 0 ? -ENOEXEC : OK; + } + + return -ENODEV; +} +#endif + +/**************************************************************************** + * Name: stm32_setup_overcurrent + * + * Description: + * Setup to receive an interrupt-level callback if an overcurrent + * condition is detected. + * + * Input Parameters: + * handler - New overcurrent interrupt handler + * arg - The argument provided for the interrupt handler + * + * Returned Value: + * Zero (OK) is returned on success. Otherwise, a negated errno value + * is returned to indicate the nature of the failure. + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_USBHOST +int stm32_setup_overcurrent(xcpt_t handler, void *arg) +{ + return stm32_gpiosetevent(GPIO_OTGFS_OVER, true, true, true, handler, arg); +} +#endif + +/**************************************************************************** + * Name: stm32_usbhost_vbusdrive + * + * Description: + * Enable/disable driving of VBUS 5V output. This function must be + * provided be each platform that implements the STM32 OTG FS host + * interface + * + * "On-chip 5 V VBUS generation is not supported. For this reason, a + * charge pump or, if 5 V are available on the application board, a + * basic power switch, must be added externally to drive the 5 V VBUS + * line. The external charge pump can be driven by any GPIO output. + * When the application decides to power on VBUS using the chosen GPIO, + * it must also set the port power bit in the host port control and + * status register (PPWR bit in OTG_FS_HPRT). + * + * "The application uses this field to control power to this port, + * and the core clears this bit on an overcurrent condition." + * + * Input Parameters: + * iface - For future growth to handle multiple USB host interface. + * Should be zero. + * enable - true: enable VBUS power; false: disable VBUS power + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_USBHOST +void stm32_usbhost_vbusdrive(int iface, bool enable) +{ + DEBUGASSERT(iface == 0); + + if (enable) + { + /* Enable the Power Switch by driving the enable pin low */ + + stm32_gpiowrite(GPIO_OTGFS_PWRON, false); + } + else + { + /* Disable the Power Switch by driving the enable pin high */ + + stm32_gpiowrite(GPIO_OTGFS_PWRON, true); + } +} +#endif + +/**************************************************************************** + * Name: stm32_usbsuspend + * + * Description: + * Board logic must provide the stm32_usbsuspend logic if the USBDEV + * driver is used. This function is called whenever the USB enters or + * leaves suspend mode. This is an opportunity for the board logic to + * shutdown clocks, power, etc. while the USB is suspended. + * + ****************************************************************************/ + +#ifdef CONFIG_USBDEV +void stm32_usbsuspend(struct usbdev_s *dev, bool resume) +{ + uinfo("resume: %d\n", resume); +} +#endif + +#endif /* CONFIG_STM32_OTGFS */ diff --git a/boards/arm/stm32f2/olimex-stm32-p207/src/stm32_userleds.c b/boards/arm/stm32f2/olimex-stm32-p207/src/stm32_userleds.c new file mode 100644 index 0000000000000..b552c74f23790 --- /dev/null +++ b/boards/arm/stm32f2/olimex-stm32-p207/src/stm32_userleds.c @@ -0,0 +1,104 @@ +/**************************************************************************** + * boards/arm/stm32f2/olimex-stm32-p207/src/stm32_userleds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include "stm32.h" +#include "olimex-stm32-p207.h" + +#ifndef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* This array maps an LED number to GPIO pin configuration */ + +static uint32_t g_ledcfg[BOARD_NLEDS] = +{ + GPIO_LED1, GPIO_LED2, GPIO_LED3, GPIO_LED4 +}; + +/**************************************************************************** + * Private Function Protototypes + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_userled_initialize + ****************************************************************************/ + +uint32_t board_userled_initialize(void) +{ + /* Configure LED1-4 GPIOs for output */ + + stm32_configgpio(GPIO_LED1); + stm32_configgpio(GPIO_LED2); + stm32_configgpio(GPIO_LED3); + stm32_configgpio(GPIO_LED4); + return BOARD_NLEDS; +} + +/**************************************************************************** + * Name: board_userled + ****************************************************************************/ + +void board_userled(int led, bool ledon) +{ + if ((unsigned)led < BOARD_NLEDS) + { + stm32_gpiowrite(g_ledcfg[led], ledon); + } +} + +/**************************************************************************** + * Name: board_userled_all + ****************************************************************************/ + +void board_userled_all(uint32_t ledset) +{ + stm32_gpiowrite(GPIO_LED1, (ledset & BOARD_LED1_BIT) != 0); + stm32_gpiowrite(GPIO_LED2, (ledset & BOARD_LED2_BIT) != 0); + stm32_gpiowrite(GPIO_LED3, (ledset & BOARD_LED3_BIT) != 0); + stm32_gpiowrite(GPIO_LED4, (ledset & BOARD_LED4_BIT) != 0); +} + +#endif /* !CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32f2/photon/CMakeLists.txt b/boards/arm/stm32f2/photon/CMakeLists.txt new file mode 100644 index 0000000000000..425a22bcb9f1e --- /dev/null +++ b/boards/arm/stm32f2/photon/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32f2/photon/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/arm/stm32/photon/Kconfig b/boards/arm/stm32f2/photon/Kconfig similarity index 100% rename from boards/arm/stm32/photon/Kconfig rename to boards/arm/stm32f2/photon/Kconfig diff --git a/boards/arm/stm32f2/photon/configs/adb/defconfig b/boards/arm/stm32f2/photon/configs/adb/defconfig new file mode 100644 index 0000000000000..08ea7b3596958 --- /dev/null +++ b/boards/arm/stm32f2/photon/configs/adb/defconfig @@ -0,0 +1,71 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_LEDS is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ADBD_AUTHENTICATION=y +CONFIG_ADBD_AUTH_PUBKEY=y +CONFIG_ADBD_DEVICE_ID="serialno" +CONFIG_ADBD_FILE_SERVICE=y +CONFIG_ADBD_LOGCAT_SERVICE=y +CONFIG_ADBD_SHELL_SERVICE=y +CONFIG_ADBD_USB_SERVER=y +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="photon" +CONFIG_ARCH_BOARD_PHOTON=y +CONFIG_ARCH_CHIP="stm32f2" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F205RG=y +CONFIG_ARCH_CHIP_STM32F2=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_DEBUG_FEATURES=y +CONFIG_DEV_URANDOM=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INIT_ENTRYPOINT="adbd_main" +CONFIG_INIT_STACKSIZE=3072 +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_EXECFUNCS=y +CONFIG_LIBUV=y +CONFIG_LINE_MAX=64 +CONFIG_MM_REGIONS=2 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PHOTON_DFU_BOOTLOADER=y +CONFIG_PHOTON_IWDG=y +CONFIG_PHOTON_WDG_THREAD=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_PSEUDOTERM=y +CONFIG_RAMLOG=y +CONFIG_RAMLOG_BUFSIZE=2048 +CONFIG_RAMLOG_SYSLOG=y +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_CHILD_STATUS=y +CONFIG_SCHED_HAVE_PARENT=y +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_STM32_IWDG=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_OTGHS=y +CONFIG_STM32_USART1=y +CONFIG_SYSTEM_ADBD=y +CONFIG_SYSTEM_NSH=y +CONFIG_TLS_TASK_NELEM=4 +CONFIG_USART1_SERIAL_CONSOLE=y +CONFIG_USBADB=y +CONFIG_USBDEV=y +CONFIG_USBDEV_BUSPOWERED=y diff --git a/boards/arm/stm32f2/photon/configs/nsh/defconfig b/boards/arm/stm32f2/photon/configs/nsh/defconfig new file mode 100644 index 0000000000000..e5d1d5b3b9c33 --- /dev/null +++ b/boards/arm/stm32f2/photon/configs/nsh/defconfig @@ -0,0 +1,47 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_LEDS is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="photon" +CONFIG_ARCH_BOARD_PHOTON=y +CONFIG_ARCH_CHIP="stm32f2" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F205RG=y +CONFIG_ARCH_CHIP_STM32F2=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_MM_REGIONS=2 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PHOTON_DFU_BOOTLOADER=y +CONFIG_PHOTON_IWDG=y +CONFIG_PHOTON_WDG_THREAD=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_STM32_IWDG=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_USART1=y +CONFIG_SYSTEM_NSH=y +CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f2/photon/configs/rgbled/defconfig b/boards/arm/stm32f2/photon/configs/rgbled/defconfig new file mode 100644 index 0000000000000..dc5e7d9718c03 --- /dev/null +++ b/boards/arm/stm32f2/photon/configs/rgbled/defconfig @@ -0,0 +1,69 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_LEDS is not set +# CONFIG_DEV_CONSOLE is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="photon" +CONFIG_ARCH_BOARD_PHOTON=y +CONFIG_ARCH_CHIP="stm32f2" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F205RG=y +CONFIG_ARCH_CHIP_STM32F2=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL_USBDEVCTRL=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_CDCACM=y +CONFIG_CDCACM_CONSOLE=y +CONFIG_EXAMPLES_RGBLED=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_MM_REGIONS=2 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PHOTON_DFU_BOOTLOADER=y +CONFIG_PHOTON_IWDG=y +CONFIG_PHOTON_WDG_THREAD=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_PWM=y +CONFIG_PWM_NCHANNELS=4 +CONFIG_RAMLOG=y +CONFIG_RAMLOG_BUFSIZE=8192 +CONFIG_RAMLOG_SYSLOG=y +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RGBLED=y +CONFIG_RGBLED_INVERT=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_STM32_IWDG=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_OTGHS=y +CONFIG_STM32_PWM_MULTICHAN=y +CONFIG_STM32_TIM2=y +CONFIG_STM32_TIM2_CH2OUT=y +CONFIG_STM32_TIM2_CH3OUT=y +CONFIG_STM32_TIM2_CH4OUT=y +CONFIG_STM32_TIM2_CHANNEL2=y +CONFIG_STM32_TIM2_CHANNEL3=y +CONFIG_STM32_TIM2_CHANNEL4=y +CONFIG_STM32_TIM2_PWM=y +CONFIG_STM32_USART1=y +CONFIG_SYSTEM_NSH=y +CONFIG_USBDEV=y diff --git a/boards/arm/stm32f2/photon/configs/usbnsh/defconfig b/boards/arm/stm32f2/photon/configs/usbnsh/defconfig new file mode 100644 index 0000000000000..d364c6b0c33fd --- /dev/null +++ b/boards/arm/stm32f2/photon/configs/usbnsh/defconfig @@ -0,0 +1,53 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_DEV_CONSOLE is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="photon" +CONFIG_ARCH_BOARD_PHOTON=y +CONFIG_ARCH_CHIP="stm32f2" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F205RG=y +CONFIG_ARCH_CHIP_STM32F2=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL_USBDEVCTRL=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_CDCACM=y +CONFIG_CDCACM_CONSOLE=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_MM_REGIONS=2 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PHOTON_DFU_BOOTLOADER=y +CONFIG_PHOTON_IWDG=y +CONFIG_PHOTON_WDG_THREAD=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_STM32_IWDG=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_OTGHS=y +CONFIG_STM32_USART1=y +CONFIG_SYSLOG_CHAR=y +CONFIG_SYSLOG_DEVPATH="/dev/ttyS0" +CONFIG_SYSTEM_NSH=y +CONFIG_USBDEV=y diff --git a/boards/arm/stm32f2/photon/configs/wlan-perf/defconfig b/boards/arm/stm32f2/photon/configs/wlan-perf/defconfig new file mode 100644 index 0000000000000..d763e1d77aac2 --- /dev/null +++ b/boards/arm/stm32f2/photon/configs/wlan-perf/defconfig @@ -0,0 +1,89 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_LEDS is not set +# CONFIG_IEEE80211_BROADCOM_FWFILES is not set +# CONFIG_MMCSD_HAVE_CARDDETECT is not set +# CONFIG_MMCSD_MMCSUPPORT is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="photon" +CONFIG_ARCH_BOARD_PHOTON=y +CONFIG_ARCH_CHIP="stm32f2" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F205RG=y +CONFIG_ARCH_CHIP_STM32F2=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_DFU_BASE=0x8020000 +CONFIG_DFU_BINARY=y +CONFIG_DFU_PID=0xd006 +CONFIG_DFU_VID=0x2b04 +CONFIG_DRIVERS_IEEE80211=y +CONFIG_DRIVERS_WIRELESS=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_IEEE80211_BROADCOM_BCM43362=y +CONFIG_IEEE80211_BROADCOM_DMABUF_ALIGNMENT=16 +CONFIG_IEEE80211_BROADCOM_FRAME_POOL_SIZE=32 +CONFIG_IEEE80211_BROADCOM_FULLMAC_SDIO=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBM=y +CONFIG_LINE_MAX=64 +CONFIG_MMCSD=y +CONFIG_MMCSD_SDIO=y +CONFIG_MM_REGIONS=2 +CONFIG_NET=y +CONFIG_NETDB_DNSCLIENT=y +CONFIG_NETDEV_LATEINIT=y +CONFIG_NETDEV_WIRELESS_IOCTL=y +CONFIG_NETINIT_DHCPC=y +CONFIG_NETINIT_DRIPADDR=0xc0a80001 +CONFIG_NETUTILS_DHCPC=y +CONFIG_NETUTILS_IPERF=y +CONFIG_NETUTILS_TELNETD=y +CONFIG_NET_BROADCAST=y +CONFIG_NET_ETH_PKTSIZE=1514 +CONFIG_NET_ICMP_SOCKET=y +CONFIG_NET_PKT=y +CONFIG_NET_TCP=y +CONFIG_NET_UDP=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PHOTON_DFU_BOOTLOADER=y +CONFIG_PHOTON_IWDG=y +CONFIG_PHOTON_WDG_THREAD=y +CONFIG_PHOTON_WLAN=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_WAITPID=y +CONFIG_SDIO_BLOCKSETUP=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_STM32_DMA2=y +CONFIG_STM32_IWDG=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_SDIO=y +CONFIG_STM32_SDIO_CARD=y +CONFIG_STM32_USART1=y +CONFIG_SYSLOG_CHAR=y +CONFIG_SYSLOG_DEVPATH="/dev/ttyS0" +CONFIG_SYSTEM_NSH=y +CONFIG_SYSTEM_PING=y +CONFIG_USART1_SERIAL_CONSOLE=y +CONFIG_USERLED=y +CONFIG_WIRELESS_WAPI=y +CONFIG_WIRELESS_WAPI_CMDTOOL=y diff --git a/boards/arm/stm32f2/photon/configs/wlan/defconfig b/boards/arm/stm32f2/photon/configs/wlan/defconfig new file mode 100644 index 0000000000000..98f29fac9ed95 --- /dev/null +++ b/boards/arm/stm32f2/photon/configs/wlan/defconfig @@ -0,0 +1,101 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_LEDS is not set +# CONFIG_IEEE80211_BROADCOM_FWFILES is not set +# CONFIG_MMCSD_HAVE_CARDDETECT is not set +# CONFIG_MMCSD_MMCSUPPORT is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="photon" +CONFIG_ARCH_BOARD_PHOTON=y +CONFIG_ARCH_CHIP="stm32f2" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F205RG=y +CONFIG_ARCH_CHIP_STM32F2=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_DEBUG_ASSERTIONS=y +CONFIG_DEBUG_FEATURES=y +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_DFU_BASE=0x8020000 +CONFIG_DFU_BINARY=y +CONFIG_DFU_PID=0xd006 +CONFIG_DFU_VID=0x2b04 +CONFIG_DRIVERS_IEEE80211=y +CONFIG_DRIVERS_WIRELESS=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_IEEE80211_BROADCOM_BCM43362=y +CONFIG_IEEE80211_BROADCOM_DMABUF_ALIGNMENT=16 +CONFIG_IEEE80211_BROADCOM_FRAME_POOL_SIZE=16 +CONFIG_IEEE80211_BROADCOM_FULLMAC_SDIO=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBM=y +CONFIG_LINE_MAX=64 +CONFIG_MMCSD=y +CONFIG_MMCSD_SDIO=y +CONFIG_MMCSD_SDIOWAIT_WRCOMPLETE=y +CONFIG_MM_REGIONS=2 +CONFIG_NDEBUG=y +CONFIG_NET=y +CONFIG_NETDB_DNSCLIENT=y +CONFIG_NETDEV_LATEINIT=y +CONFIG_NETDEV_WIRELESS_IOCTL=y +CONFIG_NETINIT_DHCPC=y +CONFIG_NETINIT_DRIPADDR=0xc0a80001 +CONFIG_NETUTILS_IPERF=y +CONFIG_NETUTILS_TELNETD=y +CONFIG_NET_BROADCAST=y +CONFIG_NET_ETH_PKTSIZE=1518 +CONFIG_NET_GUARDSIZE=32 +CONFIG_NET_ICMP_SOCKET=y +CONFIG_NET_PKT=y +CONFIG_NET_TCP=y +CONFIG_NET_UDP=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PHOTON_DFU_BOOTLOADER=y +CONFIG_PHOTON_IWDG=y +CONFIG_PHOTON_WDG_THREAD=y +CONFIG_PHOTON_WLAN=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_WAITPID=y +CONFIG_SDIO_BLOCKSETUP=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_STM32_DMA2=y +CONFIG_STM32_IWDG=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_SDIO=y +CONFIG_STM32_SDIO_CARD=y +CONFIG_STM32_USART1=y +CONFIG_SYSLOG_BUFFER=y +CONFIG_SYSLOG_CHAR=y +CONFIG_SYSLOG_CONSOLE=y +CONFIG_SYSLOG_DEVPATH="/dev/ttyS0" +CONFIG_SYSLOG_INTBUFFER=y +CONFIG_SYSLOG_PROCESSID=y +CONFIG_SYSLOG_TIMESTAMP=y +CONFIG_SYSTEM_DHCPC_RENEW=y +CONFIG_SYSTEM_NSH=y +CONFIG_SYSTEM_PING=y +CONFIG_USART1_SERIAL_CONSOLE=y +CONFIG_USERLED=y +CONFIG_WIRELESS_WAPI=y +CONFIG_WIRELESS_WAPI_CMDTOOL=y diff --git a/boards/arm/stm32f2/photon/include/board.h b/boards/arm/stm32f2/photon/include/board.h new file mode 100644 index 0000000000000..a26b8826bffae --- /dev/null +++ b/boards/arm/stm32f2/photon/include/board.h @@ -0,0 +1,311 @@ +/**************************************************************************** + * boards/arm/stm32f2/photon/include/board.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_STM32_PHOTON_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32_PHOTON_INCLUDE_BOARD_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#ifndef __ASSEMBLY__ +# include +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Clocking *****************************************************************/ + +/* The Particle photon board features a single 26MHz crystal. + * + * This is the canonical configuration: + * System Clock source : PLL (HSE) + * SYSCLK(Hz) : 120000000 Determined by PLL + * configuration + * HCLK(Hz) : 120000000 (STM32_RCC_CFGR_HPRE) + * AHB Prescaler : 1 (STM32_RCC_CFGR_HPRE) + * APB1 Prescaler : 4 (STM32_RCC_CFGR_PPRE1) + * APB2 Prescaler : 2 (STM32_RCC_CFGR_PPRE2) + * HSE Frequency(Hz) : 26000000 (STM32_BOARD_XTAL) + * PLLM : 26 (STM32_PLLCFG_PLLM) + * PLLN : 240 (STM32_PLLCFG_PLLN) + * PLLP : 2 (STM32_PLLCFG_PLLP) + * PLLQ : 5 (STM32_PLLCFG_PLLQ) + * Main regulator output voltage : Scale1 mode Needed for high speed + * SYSCLK + * Flash Latency(WS) : 3 + * Prefetch Buffer : OFF + * Instruction cache : ON + * Data cache : ON + * Require 48MHz for USB OTG HS : Enabled + * SDIO and RNG clock + */ + +/* HSI - 16 MHz RC factory-trimmed + * LSI - 32 KHz RC + * HSE - On-board crystal frequency is 26MHz + * LSE - 32.768 kHz + */ + +#define STM32_BOARD_XTAL 26000000ul + +#define STM32_HSI_FREQUENCY 16000000ul +#define STM32_LSI_FREQUENCY 32000 +#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL +#define STM32_LSE_FREQUENCY 32768 + +/* Main PLL Configuration. + * + * PLL source is HSE + * PLL_VCO = (STM32_HSE_FREQUENCY / PLLM) * PLLN + * = (26,000,000 / 26) * 240 + * = 240,000,000 + * SYSCLK = PLL_VCO / PLLP + * = 240,000,000 / 2 = 120,000,000 + * USB OTG FS, SDIO and RNG Clock + * = PLL_VCO / PLLQ + * = 48,000,000 + */ + +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(26) +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(240) +#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_2 +#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(5) + +#define STM32_SYSCLK_FREQUENCY 120000000ul + +/* AHB clock (HCLK) is SYSCLK (120MHz) */ + +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY + +/* APB1 clock (PCLK1) is HCLK/4 (30MHz) */ + +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd4 /* PCLK1 = HCLK / 4 */ +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/4) + +/* Timers driven from APB1 will be twice PCLK1 */ + +#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) + +/* APB2 clock (PCLK2) is HCLK/2 (60MHz) */ + +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLKd2 /* PCLK2 = HCLK / 2 */ +#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/2) + +/* Timers driven from APB2 will be twice PCLK2 */ + +#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM9_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM10_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM11_CLKIN (2*STM32_PCLK2_FREQUENCY) + +/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx + * otherwise frequency is 2xAPBx. + * Note: TIM1,8 are on APB2, others on APB1 + */ + +#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM2_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM3_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM4_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM5_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM6_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM7_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY + +/* USB OTG HS definitions ***************************************************/ + +/* Do not enable external PHY clock or OTG_HS module will not work */ + +#undef BOARD_ENABLE_USBOTG_HSULPI + +/* LED definitions **********************************************************/ + +/* LEDs + * + * A single LED is available driven by PA13. + */ + +/* LED index values for use with board_userled() */ + +#define BOARD_LED1 0 +#define BOARD_NLEDS 1 + +/* LED bits for use with board_userled_all() */ + +#define BOARD_LED1_BIT (1 << BOARD_LED1) + +/* These LEDs are not used by the board port unless CONFIG_ARCH_LEDS is + * defined. In that case, the usage by the board port is defined in + * include/board.h and src/sam_autoleds.c. The LEDs are used to encode + * OS-related events as follows: + * + * ------------------- ---------------------------- ------ + * SYMBOL Meaning LED + * ------------------- ---------------------------- ------ + */ + +#define LED_STARTED 0 /* NuttX has been started OFF */ +#define LED_HEAPALLOCATE 0 /* Heap has been allocated OFF */ +#define LED_IRQSENABLED 0 /* Interrupts enabled OFF */ +#define LED_STACKCREATED 1 /* Idle stack created ON */ +#define LED_INIRQ 2 /* In an interrupt N/C */ +#define LED_SIGNAL 2 /* In a signal handler N/C */ +#define LED_ASSERTION 2 /* An assertion failed N/C */ +#define LED_PANIC 3 /* The system has crashed FLASH */ +#undef LED_IDLE /* MCU is in sleep mode Not used */ + +/* Thus if LED is statically on, NuttX has successfully booted and is, + * apparently, running normally. If LED is flashing at approximately + * 2Hz, then a fatal error has been detected and the system has halted. + */ + +/* TIM */ + +#define GPIO_TIM2_CH2OUT (GPIO_TIM2_CH2OUT_1|GPIO_SPEED_50MHz) +#define GPIO_TIM2_CH3OUT (GPIO_TIM2_CH3OUT_1|GPIO_SPEED_50MHz) +#define GPIO_TIM2_CH4OUT (GPIO_TIM2_CH4OUT_1|GPIO_SPEED_50MHz) + +/* RGB LED + * + * R = TIM2 CH2 on PA1 | G = TIM2 CH3 on PA2 | B = TIM4 CH4 on PA3 + * + * Note: Pin boards: GPIO_TIM2_CH2OUT ; GPIO_TIM2_CH3OUT ; GPIO_TIM2_CH4OUT + */ + +#define RGBLED_RPWMTIMER 2 +#define RGBLED_RPWMCHANNEL 2 +#define RGBLED_GPWMTIMER 2 +#define RGBLED_GPWMCHANNEL 3 +#define RGBLED_BPWMTIMER 2 +#define RGBLED_BPWMCHANNEL 4 + +/* Button definitions *******************************************************/ + +#define BOARD_BUTTON1 0 +#define NUM_BUTTONS 1 +#define BOARD_BUTTON1_BIT (1 << BOARD_BUTTON1) + +/* Alternate function pin selections ****************************************/ + +/* UART1 */ + +#ifdef CONFIG_STM32_USART1 +# define GPIO_USART1_RX (GPIO_USART1_RX_1|GPIO_SPEED_100MHz) +# define GPIO_USART1_TX (GPIO_USART1_TX_1|GPIO_SPEED_100MHz) +#endif + +/* SPI1 */ + +#define GPIO_SPI1_MISO (GPIO_SPI1_MISO_1|GPIO_SPEED_50MHz) /* PA6 */ +#define GPIO_SPI1_MOSI (GPIO_SPI1_MOSI_1|GPIO_SPEED_50MHz) /* PA7 */ +#define GPIO_SPI1_SCK (GPIO_SPI1_SCK_1|GPIO_SPEED_50MHz) /* PA5 */ + +/* SPI3 */ + +#define GPIO_SPI3_MISO (GPIO_SPI3_MISO_1|GPIO_SPEED_50MHz) /* PB4 */ +#define GPIO_SPI3_MOSI (GPIO_SPI3_MOSI_1|GPIO_SPEED_50MHz) /* PB5 */ +#define GPIO_SPI3_SCK (GPIO_SPI3_SCK_1|GPIO_SPEED_50MHz) /* PB3 */ + +/* SDIO */ + +#define GPIO_SDIO_CK (GPIO_SDIO_CK_0|GPIO_SPEED_50MHz) +#define GPIO_SDIO_CMD (GPIO_SDIO_CMD_0|GPIO_SPEED_50MHz) +#define GPIO_SDIO_D0 (GPIO_SDIO_D0_0|GPIO_SPEED_50MHz) +#define GPIO_SDIO_D1 (GPIO_SDIO_D1_0|GPIO_SPEED_50MHz) +#define GPIO_SDIO_D2 (GPIO_SDIO_D2_0|GPIO_SPEED_50MHz) +#define GPIO_SDIO_D3 (GPIO_SDIO_D3_0|GPIO_SPEED_50MHz) + +/* OTG FS */ + +#define GPIO_OTGFS_DM (GPIO_OTGFS_DM_0|GPIO_SPEED_100MHz) +#define GPIO_OTGFS_DP (GPIO_OTGFS_DP_0|GPIO_SPEED_100MHz) +#define GPIO_OTGFS_ID (GPIO_OTGFS_ID_0|GPIO_SPEED_100MHz) +#define GPIO_OTGFS_SOF (GPIO_OTGFS_SOF_0|GPIO_SPEED_100MHz) + +/* OTG HS */ + +#define GPIO_OTGHS_DM (GPIO_OTGHS_DM_0|GPIO_SPEED_100MHz) +#define GPIO_OTGHS_DP (GPIO_OTGHS_DP_0|GPIO_SPEED_100MHz) +#define GPIO_OTGHS_ID GPIO_OTGHS_ID_0 +#define GPIO_OTGHS_SOF GPIO_OTGHS_SOF_0 + +/* SDIO definitions *********************************************************/ + +/* Note that slower clocking is required when DMA is disabled in order + * to avoid RX overrun/TX underrun errors due to delayed responses + * to service FIFOs in interrupt driven mode. + * + * These values have not been tuned!!! + * + * SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(118+2)=400 KHz + */ + +#define SDIO_INIT_CLKDIV (118 << SDIO_CLKCR_CLKDIV_SHIFT) + +/* DMA ON: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(1+2)=16 MHz + * DMA OFF: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(2+2)=12 MHz + */ + +#ifdef CONFIG_SDIO_DMA +# define SDIO_MMCXFR_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT) +#else +# define SDIO_MMCXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT) +#endif + +/* DMA ON: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(1+2)=16 MHz + * DMA OFF: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(2+2)=12 MHz + */ + +#ifdef CONFIG_SDIO_DMA +# define SDIO_SDXFR_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT) +#else +# define SDIO_SDXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT) +#endif + +/* DMA Channel/Stream Selections ********************************************/ + +/* Stream selections are arbitrary for now but might become important in the + * future if we set aside more DMA channels/streams. + * + * SDIO DMA + * DMAMAP_SDIO_1 = Channel 4, Stream 3 + * DMAMAP_SDIO_2 = Channel 4, Stream 6 + */ + +#define DMAMAP_SDIO DMAMAP_SDIO_1 + +#endif /* __BOARDS_ARM_STM32_PHOTON_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32f2/photon/scripts/Make.defs b/boards/arm/stm32f2/photon/scripts/Make.defs new file mode 100644 index 0000000000000..930772652d6ab --- /dev/null +++ b/boards/arm/stm32f2/photon/scripts/Make.defs @@ -0,0 +1,68 @@ +############################################################################ +# boards/arm/stm32f2/photon/scripts/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/.config +include $(TOPDIR)/tools/Config.mk +include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs + +ifeq ($(CONFIG_PHOTON_DFU_BOOTLOADER),y) +LDSCRIPT = photon_dfu.ld +else +LDSCRIPT = photon_jtag.ld +endif + +ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) + +# See http://dfu-util.sourceforge.net/ + +DFUSUFFIX = dfu-suffix +DFUUTIL = dfu-util + +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 + +ifeq ($(CONFIG_DFU_BINARY),y) + +define FLASH + $(Q) echo "DFUSUFFIX: $(1).dfu" + $(Q) $(OBJCOPY) $(OBJCOPYARGS) -O binary $(1) $(1).dfu + $(Q) $(DFUSUFFIX) -v $(subst 0x,,$(CONFIG_DFU_VID)) -p $(subst 0x,,$(CONFIG_DFU_PID)) -a $(1).dfu + $(Q) $(DFUUTIL) -d $(CONFIG_DFU_VID):$(CONFIG_DFU_PID) -a 0 -s $(CONFIG_DFU_BASE) -D $(1).dfu +endef + +else + +define FLASH + $(Q) $(ECHO) "Photon firmware upload through JTAG is not supported" +endef + +endif diff --git a/boards/arm/stm32/photon/scripts/photon_dfu.ld b/boards/arm/stm32f2/photon/scripts/photon_dfu.ld similarity index 98% rename from boards/arm/stm32/photon/scripts/photon_dfu.ld rename to boards/arm/stm32f2/photon/scripts/photon_dfu.ld index 0272b8a715797..d5fdad6367dfa 100644 --- a/boards/arm/stm32/photon/scripts/photon_dfu.ld +++ b/boards/arm/stm32f2/photon/scripts/photon_dfu.ld @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/photon/scripts/photon_dfu.ld + * boards/arm/stm32f2/photon/scripts/photon_dfu.ld * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/photon/scripts/photon_jtag.ld b/boards/arm/stm32f2/photon/scripts/photon_jtag.ld similarity index 98% rename from boards/arm/stm32/photon/scripts/photon_jtag.ld rename to boards/arm/stm32f2/photon/scripts/photon_jtag.ld index ca944b41a41b3..ad1ecad2b09af 100644 --- a/boards/arm/stm32/photon/scripts/photon_jtag.ld +++ b/boards/arm/stm32f2/photon/scripts/photon_jtag.ld @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/photon/scripts/photon_jtag.ld + * boards/arm/stm32f2/photon/scripts/photon_jtag.ld * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f2/photon/src/CMakeLists.txt b/boards/arm/stm32f2/photon/src/CMakeLists.txt new file mode 100644 index 0000000000000..e9248b8107f1b --- /dev/null +++ b/boards/arm/stm32f2/photon/src/CMakeLists.txt @@ -0,0 +1,68 @@ +# ############################################################################## +# boards/arm/stm32f2/photon/src/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(SRCS stm32_boot.c stm32_bringup.c stm32_spi.c) + +if(CONFIG_PHOTON_DFU_BOOTLOADER) + list(APPEND SRCS dfu_signature.c) +endif() + +if(CONFIG_INPUT_BUTTONS) + list(APPEND SRCS stm32_buttons.c) +endif() + +if(CONFIG_ARCH_LEDS) + list(APPEND SRCS stm32_autoleds.c) +else() + list(APPEND SRCS stm32_userleds.c) +endif() + +if(CONFIG_PHOTON_WDG) + list(APPEND SRCS stm32_wdt.c) +endif() + +if(CONFIG_PHOTON_WLAN) + list(APPEND SRCS stm32_wlan.c) + list(APPEND SRCS stm32_wlan_firmware.c) +endif() + +if(CONFIG_STM32_OTGHS) + list(APPEND SRCS stm32_usb.c) +endif() + +if(CONFIG_RGBLED) + list(APPEND SRCS stm32_rgbled.c) +endif() + +if(CONFIG_USBDEV_COMPOSITE) + list(APPEND SRCS stm32_composite.c) +endif() + +target_sources(board PRIVATE ${SRCS}) + +if(CONFIG_PHOTON_DFU_BOOTLOADER) + set_property(GLOBAL PROPERTY LD_SCRIPT + "${NUTTX_BOARD_DIR}/scripts/photon_dfu.ld") +else() + set_property(GLOBAL PROPERTY LD_SCRIPT + "${NUTTX_BOARD_DIR}/scripts/photon_jtag.ld") +endif() diff --git a/boards/arm/stm32f2/photon/src/Make.defs b/boards/arm/stm32f2/photon/src/Make.defs new file mode 100644 index 0000000000000..36c65e38e42d1 --- /dev/null +++ b/boards/arm/stm32f2/photon/src/Make.defs @@ -0,0 +1,64 @@ +############################################################################ +# boards/arm/stm32f2/photon/src/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +CSRCS = stm32_boot.c stm32_bringup.c stm32_spi.c + +ifeq ($(CONFIG_PHOTON_DFU_BOOTLOADER),y) +CSRCS += dfu_signature.c +endif + +ifeq ($(CONFIG_INPUT_BUTTONS),y) +CSRCS += stm32_buttons.c +endif + +ifeq ($(CONFIG_ARCH_LEDS),y) +CSRCS += stm32_autoleds.c +else +CSRCS += stm32_userleds.c +endif + +ifeq ($(CONFIG_PHOTON_WDG),y) +CSRCS += stm32_wdt.c +endif + +ifeq ($(CONFIG_PHOTON_WLAN),y) +CSRCS += stm32_wlan.c +CSRCS += stm32_wlan_firmware.c +endif + +ifeq ($(CONFIG_STM32_OTGHS),y) +CSRCS += stm32_usb.c +endif + +ifeq ($(CONFIG_RGBLED),y) + CSRCS += stm32_rgbled.c +endif + +ifeq ($(CONFIG_USBDEV_COMPOSITE),y) +CSRCS += stm32_composite.c +endif + +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/photon/src/dfu_signature.c b/boards/arm/stm32f2/photon/src/dfu_signature.c similarity index 98% rename from boards/arm/stm32/photon/src/dfu_signature.c rename to boards/arm/stm32f2/photon/src/dfu_signature.c index 0ac237a385281..3738ed93a4208 100644 --- a/boards/arm/stm32/photon/src/dfu_signature.c +++ b/boards/arm/stm32f2/photon/src/dfu_signature.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/photon/src/dfu_signature.c + * boards/arm/stm32f2/photon/src/dfu_signature.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/photon/src/photon.h b/boards/arm/stm32f2/photon/src/photon.h similarity index 98% rename from boards/arm/stm32/photon/src/photon.h rename to boards/arm/stm32f2/photon/src/photon.h index 299fe0294ecd0..30f904847d118 100644 --- a/boards/arm/stm32/photon/src/photon.h +++ b/boards/arm/stm32f2/photon/src/photon.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/photon/src/photon.h + * boards/arm/stm32f2/photon/src/photon.h * * SPDX-License-Identifier: Apache-2.0 * @@ -29,7 +29,7 @@ #include #include -#include +#include /**************************************************************************** * Pre-processor Definitions diff --git a/boards/arm/stm32f2/photon/src/stm32_autoleds.c b/boards/arm/stm32f2/photon/src/stm32_autoleds.c new file mode 100644 index 0000000000000..fe1a324f455d5 --- /dev/null +++ b/boards/arm/stm32f2/photon/src/stm32_autoleds.c @@ -0,0 +1,103 @@ +/**************************************************************************** + * boards/arm/stm32f2/photon/src/stm32_autoleds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* LEDs + * + * A single LED is available driven by PA13. + * + * These LEDs are not used by the board port unless CONFIG_ARCH_LEDS is + * defined. In that case, the usage by the board port is defined in + * include/board.h and src/sam_autoleds.c. The LEDs are used to encode + * OS-related events as follows: + * + * ------------------- ----------------------- ------ + * SYMBOL Meaning LED + * ------------------- ----------------------- ------ + * LED_STARTED NuttX has been started OFF + * LED_HEAPALLOCATE Heap has been allocated OFF + * LED_IRQSENABLED Interrupts enabled OFF + * LED_STACKCREATED Idle stack created ON + * LED_INIRQ In an interrupt N/C + * LED_SIGNAL In a signal handler N/C + * LED_ASSERTION An assertion failed N/C + * LED_PANIC The system has crashed FLASH + * + * Thus is LED is statically on, NuttX has successfully booted and is, + * apparently, running normally. If LED is flashing at approximately + * 2Hz, then a fatal error has been detected and the system has halted. + */ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include +#include + +#include "stm32_gpio.h" +#include "photon.h" + +#ifdef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_autoled_initialize + ****************************************************************************/ + +void board_autoled_initialize(void) +{ + /* Configure Photon LED gpio as output */ + + stm32_configgpio(GPIO_LED1); +} + +/**************************************************************************** + * Name: board_autoled_on + ****************************************************************************/ + +void board_autoled_on(int led) +{ + if (led == 1 || led == 3) + { + stm32_gpiowrite(GPIO_LED1, true); + } +} + +/**************************************************************************** + * Name: board_autoled_off + ****************************************************************************/ + +void board_autoled_off(int led) +{ + if (led == 3) + { + stm32_gpiowrite(GPIO_LED1, false); + } +} + +#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32f2/photon/src/stm32_boot.c b/boards/arm/stm32f2/photon/src/stm32_boot.c new file mode 100644 index 0000000000000..8acf417ab0f0c --- /dev/null +++ b/boards/arm/stm32f2/photon/src/stm32_boot.c @@ -0,0 +1,106 @@ +/**************************************************************************** + * boards/arm/stm32f2/photon/src/stm32_boot.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include "arm_internal.h" +#include "photon.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_boardinitialize + * + * Description: + * All STM32 architectures must provide the following entry point. This + * entry point is called early in the initialization -- after all memory + * has been configured and mapped but before any devices have been + * initialized. + * + ****************************************************************************/ + +void stm32_boardinitialize(void) +{ +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || defined(CONFIG_STM32_SPI3) + /* Configure SPI chip selects if 1) SPI is not disabled, and 2) the weak + * function stm32_spidev_initialize() has been brought into the link. + */ + + if (stm32_spidev_initialize) + { + stm32_spidev_initialize(); + } +#endif + +#ifdef CONFIG_STM32_OTGHS + /* Initialize USB if the + * 1) OTG HS controller is in the configuration and + * 2) disabled, and + * 3) the weak function stm32_usbinitialize() has been brought into + * the build. Presumably either CONFIG_USBDEV or CONFIG_USBHOST is also + * selected. + */ + + if (stm32_usbinitialize) + { + stm32_usbinitialize(); + } +#endif + +#ifdef CONFIG_ARCH_LEDS + /* Configure on-board LEDs if LED support has been selected. */ + + board_autoled_initialize(); +#endif +} + +/**************************************************************************** + * Name: board_late_initialize + * + * Description: + * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_late_initialize(). board_late_initialize() will + * be called immediately after up_initialize() is called and just before + * the initial application is started. This additional initialization + * phase may be used, for example, to initialize board-specific device + * drivers. + * + ****************************************************************************/ + +#ifdef CONFIG_BOARD_LATE_INITIALIZE +void board_late_initialize(void) +{ + /* Perform board initialization */ + + stm32_bringup(); +} +#endif /* CONFIG_BOARD_LATE_INITIALIZE */ diff --git a/boards/arm/stm32f2/photon/src/stm32_bringup.c b/boards/arm/stm32f2/photon/src/stm32_bringup.c new file mode 100644 index 0000000000000..7bcb3c0afa0e3 --- /dev/null +++ b/boards/arm/stm32f2/photon/src/stm32_bringup.c @@ -0,0 +1,167 @@ +/**************************************************************************** + * boards/arm/stm32f2/photon/src/stm32_bringup.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include +#include +#include + +#include + +#include "photon.h" +#include "stm32_wdg.h" + +#ifdef CONFIG_USBADB +# include +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_bringup + * + * Description: + * This function initializes and configures all on-board features + * appropriate for the selected configuration. + * + ****************************************************************************/ + +int stm32_bringup(void) +{ + int ret = OK; + +#ifdef CONFIG_FS_PROCFS + /* Mount the procfs file system */ + + ret = nx_mount(NULL, "/proc", "procfs", 0, NULL); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to mount procfs at /proc: %d\n", ret); + } +#endif + +#if defined(CONFIG_USERLED) && !defined(CONFIG_ARCH_LEDS) +#ifdef CONFIG_USERLED_LOWER + /* Register the LED driver */ + + ret = userled_lower_initialize("/dev/userleds"); + if (ret != OK) + { + syslog(LOG_ERR, "ERROR: userled_lower_initialize() failed: %d\n", ret); + return ret; + } +#else + /* Enable USER LED support for some other purpose */ + + board_userled_initialize(); +#endif /* CONFIG_USERLED_LOWER */ +#endif /* CONFIG_USERLED && !CONFIG_ARCH_LEDS */ + +#ifdef CONFIG_INPUT_BUTTONS +#ifdef CONFIG_INPUT_BUTTONS_LOWER + /* Register the BUTTON driver */ + + ret = btn_lower_initialize("/dev/buttons"); + if (ret != OK) + { + syslog(LOG_ERR, "ERROR: btn_lower_initialize() failed: %d\n", ret); + return ret; + } +#else + /* Enable BUTTON support for some other purpose */ + + board_button_initialize(); +#endif /* CONFIG_INPUT_BUTTONS_LOWER */ +#endif /* CONFIG_INPUT_BUTTONS */ + +#ifdef CONFIG_STM32_IWDG + /* Initialize the watchdog timer */ + + stm32_iwdginitialize("/dev/watchdog0", STM32_LSI_FREQUENCY); +#endif + +#ifdef CONFIG_PHOTON_WDG + /* Start WDG kicker thread */ + + ret = photon_watchdog_initialize(); + if (ret != OK) + { + syslog(LOG_ERR, "Failed to start watchdog thread: %d\n", ret); + return ret; + } +#endif + +#ifdef CONFIG_RGBLED + /* Configure and initialize the RGB LED. */ + + ret = stm32_rgbled_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_rgbled_setup() failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_PHOTON_WLAN + /* Initialize wlan driver and hardware */ + + ret = photon_wlan_initialize(); + if (ret != OK) + { + syslog(LOG_ERR, "Failed to initialize wlan: %d\n", ret); + return ret; + } +#endif + +#ifdef CONFIG_USBDEV_COMPOSITE + +#ifndef CONFIG_BOARDCTL_USBDEVCTRL + ret = board_composite_initialize(0); + if (ret != OK) + { + syslog(LOG_ERR, "Failed to initialize composite: %d\n", ret); + return ret; + } + + if (board_composite_connect(0, 0) == NULL) + { + syslog(LOG_ERR, "Failed to connect composite: %d\n", ret); + return ret; + } +#endif /* !CONFIG_BOARDCTL_USBDEVCTRL */ +#else +#ifdef CONFIG_USBADB + usbdev_adb_initialize(); +#endif +#endif /* CONFIG_USBDEV_COMPOSITE */ + return ret; +} diff --git a/boards/arm/stm32f2/photon/src/stm32_buttons.c b/boards/arm/stm32f2/photon/src/stm32_buttons.c new file mode 100644 index 0000000000000..c4f6bd29b3a08 --- /dev/null +++ b/boards/arm/stm32f2/photon/src/stm32_buttons.c @@ -0,0 +1,88 @@ +/**************************************************************************** + * boards/arm/stm32f2/photon/src/stm32_buttons.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include "photon.h" + +#include "stm32_gpio.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_button_initialize + ****************************************************************************/ + +uint32_t board_button_initialize(void) +{ + /* Configure Photon button gpio as input */ + + stm32_configgpio(GPIO_BUTTON1); + return NUM_BUTTONS; +} + +/**************************************************************************** + * Name: board_buttons + ****************************************************************************/ + +uint32_t board_buttons(void) +{ + /* Check the state of the only button */ + + if (stm32_gpioread(GPIO_BUTTON1)) + { + return BOARD_BUTTON1_BIT; + } + + return 0; +} + +/**************************************************************************** + * Name: board_button_irq + ****************************************************************************/ + +#ifdef CONFIG_ARCH_IRQBUTTONS +int board_button_irq(int id, xcpt_t irqhandler, void *arg) +{ + if (id != BOARD_BUTTON1) + { + /* Invalid button id */ + + return -EINVAL; + } + + /* Configure interrupt on falling edge only */ + + return stm32_gpiosetevent(GPIO_BUTTON1, false, true, false, + irqhandler, arg); +} +#endif /* CONFIG_ARCH_IRQBUTTONS */ diff --git a/boards/arm/stm32f2/photon/src/stm32_composite.c b/boards/arm/stm32f2/photon/src/stm32_composite.c new file mode 100644 index 0000000000000..49f82ed1d23ef --- /dev/null +++ b/boards/arm/stm32f2/photon/src/stm32_composite.c @@ -0,0 +1,166 @@ +/**************************************************************************** + * boards/arm/stm32f2/photon/src/stm32_composite.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include +#include +#include + +#include "stm32.h" + +#if defined(CONFIG_BOARDCTL_USBDEVCTRL) && defined(CONFIG_USBDEV_COMPOSITE) + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_composite0_connect + * + * Description: + * Connect the USB composite device on the specified USB device port for + * configuration 0. + * + * Input Parameters: + * port - The USB device port. + * + * Returned Value: + * A non-NULL handle value is returned on success. NULL is returned on + * any failure. + * + ****************************************************************************/ + +static void *board_composite0_connect(int port) +{ + /* Here we are composing the configuration of the usb composite device. + * + * The standard is to use one CDC/ACM and one USB mass storage device. + */ + + /* Change "dev" array size to add more composite devs */ + + struct composite_devdesc_s dev[1]; + int ifnobase = 0; + int strbase = (COMPOSITE_NSTRIDS) - 1; + + int dev_idx = 0; + +#ifdef CONFIG_USBADB + /* Configure the ADB USB device */ + + /* Ask the adb driver to fill in the constants we didn't + * know here. + */ + + usbdev_adb_get_composite_devdesc(&dev[dev_idx]); + + /* Interfaces */ + + dev[dev_idx].devinfo.ifnobase = ifnobase; /* Offset to Interface-IDs */ + dev[dev_idx].minor = 0; /* The minor interface number */ + + /* Strings */ + + dev[dev_idx].devinfo.strbase = strbase; /* Offset to String Numbers */ + + /* Endpoints */ + + dev[dev_idx].devinfo.epno[USBADB_EP_BULKIN_IDX] = 1; + dev[dev_idx].devinfo.epno[USBADB_EP_BULKOUT_IDX] = 2; + + /* Count up the base numbers */ + + ifnobase += dev[dev_idx].devinfo.ninterfaces; + strbase += dev[dev_idx].devinfo.nstrings; + + dev_idx += 1; +#endif + + /* Add other composite devices here */ + + return composite_initialize(composite_getdevdescs(), dev, dev_idx); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_composite_initialize + * + * Description: + * Perform architecture specific initialization of a composite USB device. + * + ****************************************************************************/ + +int board_composite_initialize(int port) +{ + return OK; +} + +/**************************************************************************** + * Name: board_composite_connect + * + * Description: + * Connect the USB composite device on the specified USB device port using + * the specified configuration. The interpretation of the configid is + * board specific. + * + * Input Parameters: + * port - The USB device port. + * configid - The USB composite configuration + * + * Returned Value: + * A non-NULL handle value is returned on success. NULL is returned on + * any failure. + * + ****************************************************************************/ + +void *board_composite_connect(int port, int configid) +{ + if (configid == 0) + { + return board_composite0_connect(port); + } + + return NULL; +} + +#endif /* CONFIG_BOARDCTL_USBDEVCTRL && CONFIG_USBDEV_COMPOSITE */ diff --git a/boards/arm/stm32f2/photon/src/stm32_rgbled.c b/boards/arm/stm32f2/photon/src/stm32_rgbled.c new file mode 100644 index 0000000000000..3b56149af249c --- /dev/null +++ b/boards/arm/stm32f2/photon/src/stm32_rgbled.c @@ -0,0 +1,169 @@ +/**************************************************************************** + * boards/arm/stm32f2/photon/src/stm32_rgbled.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include +#include +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32_pwm.h" +#include "photon.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +#define HAVE_RGBLED 1 + +#ifndef CONFIG_PWM +# undef HAVE_RGBLED +#endif + +#ifndef CONFIG_STM32_TIM2 +# undef HAVE_RGBLED +#endif + +#ifndef CONFIG_STM32_TIM2_PWM +# undef HAVE_RGBLED +#endif + +#ifndef CONFIG_STM32_TIM2_CHANNEL2 +# undef HAVE_PWM +#endif + +#ifndef CONFIG_STM32_TIM2_CHANNEL3 +# undef HAVE_PWM +#endif + +#ifndef CONFIG_STM32_TIM2_CHANNEL4 +# undef HAVE_PWM +#endif + +#ifdef HAVE_RGBLED + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_rgbled_setup + * + * Description: + * Initial for support of a connected RGB LED using PWM. + * + ****************************************************************************/ + +int stm32_rgbled_setup(void) +{ + static bool initialized = false; + struct pwm_lowerhalf_s *ledr; + struct pwm_lowerhalf_s *ledg; + struct pwm_lowerhalf_s *ledb; + struct file file; + int ret; + + /* Have we already initialized? */ + + if (!initialized) + { + /* Call stm32_pwminitialize() to get an instance of the PWM interface */ + + ledr = stm32_pwminitialize(RGBLED_RPWMTIMER); + if (!ledr) + { + lederr("ERROR: Failed to get the STM32 PWM lower half to LEDR\n"); + return -ENODEV; + } + + ledr->ops->setup(ledr); + + /* Call stm32_pwminitialize() to get an instance of the PWM interface */ + + ledg = stm32_pwminitialize(RGBLED_GPWMTIMER); + if (!ledg) + { + lederr("ERROR: Failed to get the STM32 PWM lower half to LEDG\n"); + return -ENODEV; + } + + ledg->ops->setup(ledg); + + /* Call stm32_pwminitialize() to get an instance of the PWM interface */ + + ledb = stm32_pwminitialize(RGBLED_BPWMTIMER); + if (!ledb) + { + lederr("ERROR: Failed to get the STM32 PWM lower half to LEDB\n"); + return -ENODEV; + } + + ledb->ops->setup(ledb); + + /* Register the RGB LED diver at "/dev/rgbled0" */ + + ret = rgbled_register("/dev/rgbled0", ledr, ledg, ledb, + RGBLED_RPWMCHANNEL, RGBLED_GPWMCHANNEL, + RGBLED_BPWMCHANNEL); + if (ret < 0) + { + lederr("ERROR: rgbled_register failed: %d\n", ret); + return ret; + } + + ret = file_open(&file, "/dev/rgbled0", O_WRONLY); + if (ret < 0) + { + lederr("ERROR: open failed: %d\n", ret); + return ret; + } + + /* Initialize led off */ + + file_write(&file, "#000000", 8); + file_close(&file); + + /* Now we are initialized */ + + initialized = true; + } + + return OK; +} + +#else +# error "HAVE_RGBLED is undefined" +#endif /* HAVE_RGBLED */ diff --git a/boards/arm/stm32f2/photon/src/stm32_spi.c b/boards/arm/stm32f2/photon/src/stm32_spi.c new file mode 100644 index 0000000000000..775b45ed32d14 --- /dev/null +++ b/boards/arm/stm32f2/photon/src/stm32_spi.c @@ -0,0 +1,186 @@ +/**************************************************************************** + * boards/arm/stm32f2/photon/src/stm32_spi.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include + +#include "arm_internal.h" +#include "chip.h" +#include "stm32.h" + +#include "photon.h" + +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || defined(CONFIG_STM32_SPI3) + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_spidev_initialize + * + * Description: + * Called to configure SPI chip select GPIO pins for the Mikroe Clicker2 + * STM32 board. + * + ****************************************************************************/ + +void weak_function stm32_spidev_initialize(void) +{ +} + +/**************************************************************************** + * Name: stm32_spi1/2/3select and stm32_spi1/2/3status + * + * Description: + * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status + * must be provided by board-specific logic. They are implementations of + * the select and status methods of the SPI interface defined by struct + * spi_ops_s (see include/nuttx/spi/spi.h). All other methods (including + * stm32_spibus_initialize()) are provided by common STM32 logic. + * To use this common SPI logic on your board: + * + * 1. Provide logic in stm32_boardinitialize() to configure SPI chip select + * pins. + * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() functions + * in your board-specific logic. These functions will perform chip + * selection and status operations using GPIOs in the way your board is + * configured. + * 3. Add a calls to stm32_spibus_initialize() in your low level + * application initialization logic + * 4. The handle returned by stm32_spibus_initialize() may then be used to + * bind the SPI driver to higher level logic (e.g., calling + * mmcsd_spislotinitialize(), for example, will bind the SPI driver to + * the SPI MMC/SD driver). + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_SPI1 +void stm32_spi1select(struct spi_dev_s *dev, + uint32_t devid, bool selected) +{ + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); +} + +uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} +#endif + +#ifdef CONFIG_STM32_SPI2 +void stm32_spi2select(struct spi_dev_s *dev, + uint32_t devid, bool selected) +{ + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); +} + +uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} +#endif + +#ifdef CONFIG_STM32_SPI3 +void stm32_spi3select(struct spi_dev_s *dev, + uint32_t devid, bool selected) +{ + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); +} + +uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid) +{ + switch (devid) + { + default: + break; + } + + return 0; +} +#endif + +/**************************************************************************** + * Name: stm32_spi1cmddata + * + * Description: + * Set or clear the SH1101A A0 or SD1306 D/C n bit to select data (true) + * or command (false). This function must be provided by platform-specific + * logic. This is an implementation of the cmddata method of the SPI + * interface defined by struct spi_ops_s (see include/nuttx/spi/spi.h). + * + * Input Parameters: + * + * spi - SPI device that controls the bus the device that requires the CMD/ + * DATA selection. + * devid - If there are multiple devices on the bus, this selects which one + * to select cmd or data. NOTE: This design restricts, for example, + * one one SPI display per SPI bus. + * cmd - true: select command; false: select data + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_SPI_CMDDATA +#ifdef CONFIG_STM32_SPI1 +int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) +{ + return -ENODEV; +} +#endif + +#ifdef CONFIG_STM32_SPI2 +int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) +{ + /* To be provided */ + + return -ENODEV; +} +#endif + +#ifdef CONFIG_STM32_SPI3 +int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) +{ + /* To be provided */ + + return -ENODEV; +} +#endif +#endif /* CONFIG_SPI_CMDDATA */ + +#endif /* CONFIG_STM32_SPI1 || CONFIG_STM32_SPI2 */ diff --git a/boards/arm/stm32f2/photon/src/stm32_usb.c b/boards/arm/stm32f2/photon/src/stm32_usb.c new file mode 100644 index 0000000000000..3bb76c85e31a8 --- /dev/null +++ b/boards/arm/stm32f2/photon/src/stm32_usb.c @@ -0,0 +1,68 @@ +/**************************************************************************** + * boards/arm/stm32f2/photon/src/stm32_usb.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include "photon.h" +#include + +#include +#include + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_usbinitialize + * + * Description: + * Called from stm32_usbinitialize very early in initialization to setup + * USB-related GPIO pins for the Photon board. + * + ****************************************************************************/ + +void stm32_usbinitialize(void) +{ +} + +/**************************************************************************** + * Name: stm32_usbsuspend + * + * Description: + * Board logic must provide the stm32_usbsuspend logic if the USBDEV driver + * is used. + * This function is called whenever the USB enters or leaves suspend mode. + * This is an opportunity for the board logic to shutdown clocks, power, + * etc. while the USB is suspended. + * + ****************************************************************************/ + +#ifdef CONFIG_USBDEV +void stm32_usbsuspend(struct usbdev_s *dev, bool resume) +{ + uinfo("resume: %d\n", resume); +} +#endif diff --git a/boards/arm/stm32f2/photon/src/stm32_userleds.c b/boards/arm/stm32f2/photon/src/stm32_userleds.c new file mode 100644 index 0000000000000..30b2933307b43 --- /dev/null +++ b/boards/arm/stm32f2/photon/src/stm32_userleds.c @@ -0,0 +1,74 @@ +/**************************************************************************** + * boards/arm/stm32f2/photon/src/stm32_userleds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include +#include "photon.h" + +#include "stm32_gpio.h" + +#ifndef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_userled_initialize + ****************************************************************************/ + +uint32_t board_userled_initialize(void) +{ + /* Configure Photon LED gpio as output */ + + stm32_configgpio(GPIO_LED1); + return BOARD_NLEDS; +} + +/**************************************************************************** + * Name: board_userled + ****************************************************************************/ + +void board_userled(int led, bool ledon) +{ + if (led == BOARD_LED1) + { + stm32_gpiowrite(GPIO_LED1, ledon); + } +} + +/**************************************************************************** + * Name: board_userled_all + ****************************************************************************/ + +void board_userled_all(uint32_t ledset) +{ + stm32_gpiowrite(GPIO_LED1, !!(ledset & BOARD_LED1_BIT)); +} + +#endif /* !CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/photon/src/stm32_wdt.c b/boards/arm/stm32f2/photon/src/stm32_wdt.c similarity index 98% rename from boards/arm/stm32/photon/src/stm32_wdt.c rename to boards/arm/stm32f2/photon/src/stm32_wdt.c index 738312db16eb9..09db859e1df03 100644 --- a/boards/arm/stm32/photon/src/stm32_wdt.c +++ b/boards/arm/stm32f2/photon/src/stm32_wdt.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/photon/src/stm32_wdt.c + * boards/arm/stm32f2/photon/src/stm32_wdt.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f2/photon/src/stm32_wlan.c b/boards/arm/stm32f2/photon/src/stm32_wlan.c new file mode 100644 index 0000000000000..f1548ca8a858f --- /dev/null +++ b/boards/arm/stm32f2/photon/src/stm32_wlan.c @@ -0,0 +1,157 @@ +/**************************************************************************** + * boards/arm/stm32f2/photon/src/stm32_wlan.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include +#include + +#include + +#include "stm32_gpio.h" +#include "stm32_sdio.h" + +#include "photon.h" + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static struct sdio_dev_s *g_sdio_dev; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: bcmf_board_reset + ****************************************************************************/ + +void bcmf_board_reset(int minor, bool reset) +{ + if (minor != SDIO_WLAN0_MINOR) + { + return; + } + + stm32_gpiowrite(GPIO_WLAN0_RESET, !reset); +} + +/**************************************************************************** + * Name: bcmf_board_power + ****************************************************************************/ + +void bcmf_board_power(int minor, bool power) +{ + /* Power signal is not used on Photon board */ +} + +/**************************************************************************** + * Name: bcmf_board_initialize + ****************************************************************************/ + +void bcmf_board_initialize(int minor) +{ + if (minor != SDIO_WLAN0_MINOR) + { + return; + } + + /* Configure reset pin */ + + stm32_configgpio(GPIO_WLAN0_RESET); + + /* Put wlan chip in reset state */ + + bcmf_board_reset(minor, true); +} + +/**************************************************************************** + * Name: bcmf_board_setup_oob_irq + ****************************************************************************/ + +void bcmf_board_setup_oob_irq(int minor, int (*func)(void *), void *arg) +{ + if (minor != SDIO_WLAN0_MINOR) + { + return; + } + + /* Configure SDIO card in-band interrupt callback */ + + if (g_sdio_dev != NULL) + { + sdio_set_sdio_card_isr(g_sdio_dev, func, arg); + } +} + +/**************************************************************************** + * Name: bcmf_board_etheraddr + ****************************************************************************/ + +bool bcmf_board_etheraddr(struct ether_addr *ethaddr) +{ + return false; +} + +/**************************************************************************** + * Name: photon_wlan_initialize + ****************************************************************************/ + +int photon_wlan_initialize(void) +{ + int ret; + + /* Initialize sdio interface */ + + wlinfo("Initializing SDIO slot %d\n", SDIO_WLAN0_SLOTNO); + + g_sdio_dev = sdio_initialize(SDIO_WLAN0_SLOTNO); + + if (!g_sdio_dev) + { + wlerr("ERROR: Failed to initialize SDIO with slot %d\n", + SDIO_WLAN0_SLOTNO); + return ERROR; + } + + /* Bind the SDIO interface to the bcmf driver */ + + ret = bcmf_sdio_initialize(SDIO_WLAN0_MINOR, g_sdio_dev); + + if (ret != OK) + { + wlerr("ERROR: Failed to bind SDIO to bcmf driver\n"); + + /* FIXME deinitialize sdio device */ + + return ERROR; + } + + return OK; +} diff --git a/boards/arm/stm32/photon/src/stm32_wlan_firmware.c b/boards/arm/stm32f2/photon/src/stm32_wlan_firmware.c similarity index 99% rename from boards/arm/stm32/photon/src/stm32_wlan_firmware.c rename to boards/arm/stm32f2/photon/src/stm32_wlan_firmware.c index 2374ae038c923..ace87343d4e79 100644 --- a/boards/arm/stm32/photon/src/stm32_wlan_firmware.c +++ b/boards/arm/stm32f2/photon/src/stm32_wlan_firmware.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/photon/src/stm32_wlan_firmware.c + * boards/arm/stm32f2/photon/src/stm32_wlan_firmware.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f2/stm3220g-eval/CMakeLists.txt b/boards/arm/stm32f2/stm3220g-eval/CMakeLists.txt new file mode 100644 index 0000000000000..9107f3bbd27ee --- /dev/null +++ b/boards/arm/stm32f2/stm3220g-eval/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32f2/stm3220g-eval/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/arm/stm32/stm3220g-eval/Kconfig b/boards/arm/stm32f2/stm3220g-eval/Kconfig similarity index 100% rename from boards/arm/stm32/stm3220g-eval/Kconfig rename to boards/arm/stm32f2/stm3220g-eval/Kconfig diff --git a/boards/arm/stm32f2/stm3220g-eval/configs/dhcpd/defconfig b/boards/arm/stm32f2/stm3220g-eval/configs/dhcpd/defconfig new file mode 100644 index 0000000000000..4e83650fdf40e --- /dev/null +++ b/boards/arm/stm32f2/stm3220g-eval/configs/dhcpd/defconfig @@ -0,0 +1,61 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NETUTILS_DHCPD_IGNOREBROADCAST is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm3220g-eval" +CONFIG_ARCH_BOARD_STM3220G_EVAL=y +CONFIG_ARCH_CHIP="stm32f2" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F207IG=y +CONFIG_ARCH_CHIP_STM32F2=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=10926 +CONFIG_DISABLE_ENVIRON=y +CONFIG_DISABLE_MOUNTPOINT=y +CONFIG_DISABLE_MQUEUE=y +CONFIG_DISABLE_PTHREAD=y +CONFIG_ETH0_PHY_DP83848C=y +CONFIG_EXAMPLES_DHCPD=y +CONFIG_EXAMPLES_DHCPD_NOMAC=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_HOST_WINDOWS=y +CONFIG_INIT_ENTRYPOINT="dhcpd_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_MM_REGIONS=2 +CONFIG_NET=y +CONFIG_NETUTILS_DHCPD=y +CONFIG_NETUTILS_NETLIB=y +CONFIG_NET_BROADCAST=y +CONFIG_NET_SOCKOPTS=y +CONFIG_NET_UDP=y +CONFIG_NET_UDP_CHECKSUMS=y +CONFIG_NUNGET_CHARS=0 +CONFIG_RAM_SIZE=196608 +CONFIG_RAM_START=0x20000000 +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=13 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2012 +CONFIG_STDIO_DISABLE_BUFFERING=y +CONFIG_STM32_DFU=y +CONFIG_STM32_ETHMAC=y +CONFIG_STM32_JTAG_FULL_ENABLE=y +CONFIG_STM32_MII=y +CONFIG_STM32_PHYSR=16 +CONFIG_STM32_PHYSR_100MBPS=0x0000 +CONFIG_STM32_PHYSR_FULLDUPLEX=0x0004 +CONFIG_STM32_PHYSR_MODE=0x0004 +CONFIG_STM32_PHYSR_SPEED=0x0002 +CONFIG_STM32_USART3=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART3_RXBUFSIZE=128 +CONFIG_USART3_SERIAL_CONSOLE=y +CONFIG_USART3_TXBUFSIZE=128 diff --git a/boards/arm/stm32f2/stm3220g-eval/configs/nettest/defconfig b/boards/arm/stm32f2/stm3220g-eval/configs/nettest/defconfig new file mode 100644 index 0000000000000..431b3151a62e2 --- /dev/null +++ b/boards/arm/stm32f2/stm3220g-eval/configs/nettest/defconfig @@ -0,0 +1,60 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm3220g-eval" +CONFIG_ARCH_BOARD_STM3220G_EVAL=y +CONFIG_ARCH_CHIP="stm32f2" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F207IG=y +CONFIG_ARCH_CHIP_STM32F2=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=10926 +CONFIG_CONSOLE_SYSLOG=y +CONFIG_DISABLE_ENVIRON=y +CONFIG_DISABLE_MOUNTPOINT=y +CONFIG_DISABLE_MQUEUE=y +CONFIG_DISABLE_PTHREAD=y +CONFIG_ETH0_PHY_DP83848C=y +CONFIG_EXAMPLES_NETTEST=y +CONFIG_EXAMPLES_NETTEST_NOMAC=y +CONFIG_EXAMPLES_NETTEST_PERFORMANCE=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_HOST_WINDOWS=y +CONFIG_INIT_ENTRYPOINT="nettest_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_NET=y +CONFIG_NETUTILS_NETLIB=y +CONFIG_NET_MAX_LISTENPORTS=40 +CONFIG_NET_SOCKOPTS=y +CONFIG_NET_TCP=y +CONFIG_NET_TCP_PREALLOC_CONNS=40 +CONFIG_NUNGET_CHARS=0 +CONFIG_RAM_SIZE=196608 +CONFIG_RAM_START=0x20000000 +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2012 +CONFIG_STDIO_DISABLE_BUFFERING=y +CONFIG_STM32_DFU=y +CONFIG_STM32_ETHMAC=y +CONFIG_STM32_JTAG_FULL_ENABLE=y +CONFIG_STM32_MII=y +CONFIG_STM32_PHYSR=16 +CONFIG_STM32_PHYSR_100MBPS=0x0000 +CONFIG_STM32_PHYSR_FULLDUPLEX=0x0004 +CONFIG_STM32_PHYSR_MODE=0x0004 +CONFIG_STM32_PHYSR_SPEED=0x0002 +CONFIG_STM32_USART3=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART3_RXBUFSIZE=128 +CONFIG_USART3_SERIAL_CONSOLE=y +CONFIG_USART3_TXBUFSIZE=128 diff --git a/boards/arm/stm32f2/stm3220g-eval/configs/nsh/defconfig b/boards/arm/stm32f2/stm3220g-eval/configs/nsh/defconfig new file mode 100644 index 0000000000000..26a63e10c0781 --- /dev/null +++ b/boards/arm/stm32f2/stm3220g-eval/configs/nsh/defconfig @@ -0,0 +1,75 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_MMCSD_HAVE_CARDDETECT is not set +# CONFIG_MMCSD_MMCSUPPORT is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm3220g-eval" +CONFIG_ARCH_BOARD_STM3220G_EVAL=y +CONFIG_ARCH_CHIP="stm32f2" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F207IG=y +CONFIG_ARCH_CHIP_STM32F2=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=10926 +CONFIG_BUILTIN=y +CONFIG_ETH0_PHY_DP83848C=y +CONFIG_FAT_LCNAMES=y +CONFIG_FAT_LFN=y +CONFIG_FS_FAT=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_I2C=y +CONFIG_I2C_POLLED=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_MMCSD=y +CONFIG_MMCSD_MULTIBLOCK_LIMIT=1 +CONFIG_MTD=y +CONFIG_NET=y +CONFIG_NETDB_DNSCLIENT=y +CONFIG_NETUTILS_TFTPC=y +CONFIG_NETUTILS_WEBCLIENT=y +CONFIG_NET_BROADCAST=y +CONFIG_NET_ICMP_SOCKET=y +CONFIG_NET_MAX_LISTENPORTS=40 +CONFIG_NET_STATISTICS=y +CONFIG_NET_TCP=y +CONFIG_NET_TCP_PREALLOC_CONNS=40 +CONFIG_NET_UDP=y +CONFIG_NET_UDP_CHECKSUMS=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=196608 +CONFIG_RAM_START=0x20000000 +CONFIG_RR_INTERVAL=200 +CONFIG_RTC_DATETIME=y +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_WAITPID=y +CONFIG_STM32_DFU=y +CONFIG_STM32_ETHMAC=y +CONFIG_STM32_I2C1=y +CONFIG_STM32_JTAG_FULL_ENABLE=y +CONFIG_STM32_MII=y +CONFIG_STM32_PHYSR=16 +CONFIG_STM32_PHYSR_100MBPS=0x0000 +CONFIG_STM32_PHYSR_FULLDUPLEX=0x0004 +CONFIG_STM32_PHYSR_MODE=0x0004 +CONFIG_STM32_PHYSR_SPEED=0x0002 +CONFIG_STM32_PWR=y +CONFIG_STM32_RTC=y +CONFIG_STM32_USART3=y +CONFIG_SYMTAB_ORDEREDBYNAME=y +CONFIG_SYSTEM_NSH=y +CONFIG_SYSTEM_PING=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART3_RXBUFSIZE=128 +CONFIG_USART3_SERIAL_CONSOLE=y +CONFIG_USART3_TXBUFSIZE=128 diff --git a/boards/arm/stm32f2/stm3220g-eval/configs/nsh2/defconfig b/boards/arm/stm32f2/stm3220g-eval/configs/nsh2/defconfig new file mode 100644 index 0000000000000..5dff42667f25d --- /dev/null +++ b/boards/arm/stm32f2/stm3220g-eval/configs/nsh2/defconfig @@ -0,0 +1,89 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_DEV_CONSOLE is not set +# CONFIG_MMCSD_HAVE_CARDDETECT is not set +# CONFIG_MMCSD_MMCSUPPORT is not set +# CONFIG_NSH_CONSOLE is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm3220g-eval" +CONFIG_ARCH_BOARD_STM3220G_EVAL=y +CONFIG_ARCH_CHIP="stm32f2" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F207IG=y +CONFIG_ARCH_CHIP_STM32F2=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=10926 +CONFIG_BUILTIN=y +CONFIG_ETH0_PHY_DP83848C=y +CONFIG_FAT_LCNAMES=y +CONFIG_FAT_LFN=y +CONFIG_FS_FAT=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_HOST_WINDOWS=y +CONFIG_I2C=y +CONFIG_I2CTOOL_DEFFREQ=100000 +CONFIG_I2CTOOL_MINBUS=1 +CONFIG_I2C_POLLED=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_MMCSD=y +CONFIG_MMCSD_MULTIBLOCK_LIMIT=1 +CONFIG_MMCSD_SDIO=y +CONFIG_MTD=y +CONFIG_NET=y +CONFIG_NETDB_DNSCLIENT=y +CONFIG_NETDB_DNSCLIENT_ENTRIES=4 +CONFIG_NETDB_DNSSERVER_NOADDR=y +CONFIG_NETINIT_NOMAC=y +CONFIG_NETUTILS_TELNETD=y +CONFIG_NETUTILS_TFTPC=y +CONFIG_NETUTILS_WEBCLIENT=y +CONFIG_NET_BROADCAST=y +CONFIG_NET_ICMP_SOCKET=y +CONFIG_NET_MAX_LISTENPORTS=40 +CONFIG_NET_STATISTICS=y +CONFIG_NET_TCP=y +CONFIG_NET_TCP_PREALLOC_CONNS=40 +CONFIG_NET_UDP=y +CONFIG_NET_UDP_CHECKSUMS=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAMLOG=y +CONFIG_RAMLOG_SYSLOG=y +CONFIG_RAM_SIZE=196608 +CONFIG_RAM_START=0x20000000 +CONFIG_RR_INTERVAL=200 +CONFIG_RTC_DATETIME=y +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=192 +CONFIG_SCHED_WAITPID=y +CONFIG_STM32_DFU=y +CONFIG_STM32_DMA2=y +CONFIG_STM32_ETHMAC=y +CONFIG_STM32_I2C1=y +CONFIG_STM32_JTAG_FULL_ENABLE=y +CONFIG_STM32_MII=y +CONFIG_STM32_PHYSR=16 +CONFIG_STM32_PHYSR_100MBPS=0x0000 +CONFIG_STM32_PHYSR_FULLDUPLEX=0x0004 +CONFIG_STM32_PHYSR_MODE=0x0004 +CONFIG_STM32_PHYSR_SPEED=0x0002 +CONFIG_STM32_PWR=y +CONFIG_STM32_RTC=y +CONFIG_STM32_SDIO=y +CONFIG_SYMTAB_ORDEREDBYNAME=y +CONFIG_SYSTEM_I2CTOOL=y +CONFIG_SYSTEM_NSH=y +CONFIG_SYSTEM_PING=y +CONFIG_TASK_NAME_SIZE=0 diff --git a/boards/arm/stm32f2/stm3220g-eval/configs/nxwm/defconfig b/boards/arm/stm32f2/stm3220g-eval/configs/nxwm/defconfig new file mode 100644 index 0000000000000..8a2c4444608fc --- /dev/null +++ b/boards/arm/stm32f2/stm3220g-eval/configs/nxwm/defconfig @@ -0,0 +1,126 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_MMCSD_HAVE_CARDDETECT is not set +# CONFIG_MMCSD_MMCSUPPORT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_NXFONTS_DISABLE_16BPP is not set +# CONFIG_NXTK_DEFAULT_BORDERCOLORS is not set +# CONFIG_NX_DISABLE_16BPP is not set +# CONFIG_NX_PACKEDMSFIRST is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm3220g-eval" +CONFIG_ARCH_BOARD_STM3220G_EVAL=y +CONFIG_ARCH_CHIP="stm32f2" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F207IG=y +CONFIG_ARCH_CHIP_STM32F2=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=10926 +CONFIG_ETH0_PHY_DP83848C=y +CONFIG_FAT_LCNAMES=y +CONFIG_FAT_LFN=y +CONFIG_FS_FAT=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_HOST_WINDOWS=y +CONFIG_I2C_POLLED=y +CONFIG_INIT_ENTRYPOINT="nxwm_main" +CONFIG_INPUT=y +CONFIG_INPUT_STMPE811=y +CONFIG_INTELHEX_BINARY=y +CONFIG_LCD=y +CONFIG_LCD_MAXCONTRAST=1 +CONFIG_LCD_NOGETRUN=y +CONFIG_LIBC_MAX_EXITFUNS=1 +CONFIG_LINE_MAX=64 +CONFIG_MMCSD=y +CONFIG_MMCSD_MULTIBLOCK_LIMIT=1 +CONFIG_MQ_MAXMSGSIZE=64 +CONFIG_NET=y +CONFIG_NETINIT_NOMAC=y +CONFIG_NETUTILS_TELNETD=y +CONFIG_NETUTILS_TFTPC=y +CONFIG_NETUTILS_WEBCLIENT=y +CONFIG_NET_ICMP_SOCKET=y +CONFIG_NET_MAX_LISTENPORTS=40 +CONFIG_NET_STATISTICS=y +CONFIG_NET_TCP=y +CONFIG_NET_TCP_PREALLOC_CONNS=40 +CONFIG_NET_UDP=y +CONFIG_NET_UDP_CHECKSUMS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_LIBRARY=y +CONFIG_NSH_READLINE=y +CONFIG_NX=y +CONFIG_NXFONT_SANS22X29B=y +CONFIG_NXFONT_SANS23X27=y +CONFIG_NXTERM=y +CONFIG_NXTERM_CACHESIZE=32 +CONFIG_NXTERM_CURSORCHAR=95 +CONFIG_NXTERM_MXCHARS=325 +CONFIG_NXTERM_NXKBDIN=y +CONFIG_NXTK_BORDERCOLOR1=0x5cb7 +CONFIG_NXTK_BORDERCOLOR2=0x21c9 +CONFIG_NXTK_BORDERCOLOR3=0xffdf +CONFIG_NXWIDGETS=y +CONFIG_NXWIDGETS_BPP=16 +CONFIG_NXWIDGETS_CUSTOM_EDGECOLORS=y +CONFIG_NXWIDGETS_CUSTOM_FILLCOLORS=y +CONFIG_NXWIDGETS_DEFAULT_BACKGROUNDCOLOR=0x9dfb +CONFIG_NXWIDGETS_DEFAULT_HIGHLIGHTCOLOR=0xc618 +CONFIG_NXWIDGETS_DEFAULT_SELECTEDBACKGROUNDCOLOR=0xd73e +CONFIG_NXWIDGETS_DEFAULT_SHADOWEDGECOLOR=0x21e9 +CONFIG_NXWIDGETS_DEFAULT_SHINEEDGECOLOR=0xffdf +CONFIG_NXWIDGETS_SIZEOFCHAR=1 +CONFIG_NXWM=y +CONFIG_NXWM_BACKGROUND_IMAGE="" +CONFIG_NXWM_HEXCALCULATOR_CUSTOM_FONTID=y +CONFIG_NXWM_HEXCALCULATOR_FONTID=5 +CONFIG_NXWM_KEYBOARD=y +CONFIG_NXWM_KEYBOARD_LISTENERPRIO=100 +CONFIG_NXWM_TASKBAR_LEFT=y +CONFIG_NXWM_TASKBAR_VSPACING=4 +CONFIG_NXWM_TOUCHSCREEN_LISTENERPRIO=100 +CONFIG_NX_BLOCKING=y +CONFIG_NX_KBD=y +CONFIG_NX_XYINPUT_TOUCHSCREEN=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=196608 +CONFIG_RAM_START=0x20000000 +CONFIG_RR_INTERVAL=200 +CONFIG_RTC_DATETIME=y +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=192 +CONFIG_SCHED_WAITPID=y +CONFIG_STM32_DFU=y +CONFIG_STM32_ETHMAC=y +CONFIG_STM32_FSMC=y +CONFIG_STM32_I2C1=y +CONFIG_STM32_JTAG_FULL_ENABLE=y +CONFIG_STM32_MII=y +CONFIG_STM32_PHYSR=16 +CONFIG_STM32_PHYSR_100MBPS=0x0000 +CONFIG_STM32_PHYSR_FULLDUPLEX=0x0004 +CONFIG_STM32_PHYSR_MODE=0x0004 +CONFIG_STM32_PHYSR_SPEED=0x0002 +CONFIG_STM32_PWR=y +CONFIG_STM32_RTC=y +CONFIG_STM32_USART3=y +CONFIG_STMPE811_ACTIVELOW=y +CONFIG_STMPE811_EDGE=y +CONFIG_STMPE811_MULTIPLE=y +CONFIG_STMPE811_THRESHX=39 +CONFIG_STMPE811_THRESHY=51 +CONFIG_SYMTAB_ORDEREDBYNAME=y +CONFIG_SYSTEM_PING=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART3_RXBUFSIZE=128 +CONFIG_USART3_SERIAL_CONSOLE=y +CONFIG_USART3_TXBUFSIZE=128 diff --git a/boards/arm/stm32f2/stm3220g-eval/configs/telnetd/defconfig b/boards/arm/stm32f2/stm3220g-eval/configs/telnetd/defconfig new file mode 100644 index 0000000000000..5d80ddff92c0a --- /dev/null +++ b/boards/arm/stm32f2/stm3220g-eval/configs/telnetd/defconfig @@ -0,0 +1,62 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm3220g-eval" +CONFIG_ARCH_BOARD_STM3220G_EVAL=y +CONFIG_ARCH_CHIP="stm32f2" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F207IG=y +CONFIG_ARCH_CHIP_STM32F2=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=10926 +CONFIG_CONSOLE_SYSLOG=y +CONFIG_DISABLE_ENVIRON=y +CONFIG_DISABLE_MOUNTPOINT=y +CONFIG_DISABLE_MQUEUE=y +CONFIG_DISABLE_PTHREAD=y +CONFIG_ETH0_PHY_DP83848C=y +CONFIG_EXAMPLES_TELNETD=y +CONFIG_EXAMPLES_TELNETD_CLIENTPRIO=128 +CONFIG_EXAMPLES_TELNETD_DAEMONPRIO=128 +CONFIG_EXAMPLES_TELNETD_NOMAC=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INIT_ENTRYPOINT="telnetd_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_MM_REGIONS=2 +CONFIG_NET=y +CONFIG_NETUTILS_TELNETD=y +CONFIG_NET_MAX_LISTENPORTS=40 +CONFIG_NET_SOCKOPTS=y +CONFIG_NET_TCP=y +CONFIG_NET_TCP_PREALLOC_CONNS=40 +CONFIG_NSH_LIBRARY=y +CONFIG_NUNGET_CHARS=0 +CONFIG_RAM_SIZE=196608 +CONFIG_RAM_START=0x20000000 +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2012 +CONFIG_STM32_DFU=y +CONFIG_STM32_ETHMAC=y +CONFIG_STM32_JTAG_FULL_ENABLE=y +CONFIG_STM32_MII=y +CONFIG_STM32_PHYSR=16 +CONFIG_STM32_PHYSR_100MBPS=0x0000 +CONFIG_STM32_PHYSR_FULLDUPLEX=0x0004 +CONFIG_STM32_PHYSR_MODE=0x0004 +CONFIG_STM32_PHYSR_SPEED=0x0002 +CONFIG_STM32_USART3=y +CONFIG_SYSTEM_READLINE=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART3_RXBUFSIZE=128 +CONFIG_USART3_SERIAL_CONSOLE=y +CONFIG_USART3_TXBUFSIZE=128 diff --git a/boards/arm/stm32f2/stm3220g-eval/include/board.h b/boards/arm/stm32f2/stm3220g-eval/include/board.h new file mode 100644 index 0000000000000..fb3043eada22d --- /dev/null +++ b/boards/arm/stm32f2/stm3220g-eval/include/board.h @@ -0,0 +1,552 @@ +/**************************************************************************** + * boards/arm/stm32f2/stm3220g-eval/include/board.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_STM32_STM3220G_EVAL_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32_STM3220G_EVAL_INCLUDE_BOARD_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#ifndef __ASSEMBLY__ +# include +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Clocking *****************************************************************/ + +/* Four clock sources are available on STM3220G-EVAL evaluation board for + * STM32F207IGH6 and RTC embedded: + * + * X1, 25 MHz crystal for ethernet PHY with socket. + * It can be removed when clock is provided by MCO pin of the MCU + * X2, 26 MHz crystal for USB OTG HS PHY + * X3, 32 kHz crystal for embedded RTC + * X4, 25 MHz crystal with socket for STM32F207IGH6 microcontroller + * (It can be removed from socket when internal RC clock is used.) + * + * This is the "standard" configuration as set up by + * arch/arm/src/stm32f40xx_rcc.c: + * System Clock source : PLL (HSE) + * SYSCLK(Hz) : 120000000 Determined by PLL + * configuration + * HCLK(Hz) : 120000000 (STM32_RCC_CFGR_HPRE) + * AHB Prescaler : 1 (STM32_RCC_CFGR_HPRE) + * APB1 Prescaler : 4 (STM32_RCC_CFGR_PPRE1) + * APB2 Prescaler : 2 (STM32_RCC_CFGR_PPRE2) + * HSE Frequency(Hz) : 25000000 (STM32_BOARD_XTAL) + * PLLM : 25 (STM32_PLLCFG_PLLM) + * PLLN : 240 (STM32_PLLCFG_PLLN) + * PLLP : 2 (STM32_PLLCFG_PLLP) + * PLLQ : 5 (STM32_PLLCFG_PLLQ) + * Main regulator output voltage : Scale1 mode Needed for high speed + * SYSCLK + * Flash Latency(WS) : 5 + * Prefetch Buffer : OFF + * Instruction cache : ON + * Data cache : ON + * Require 48MHz for USB OTG FS, : Enabled + * SDIO and RNG clock + */ + +/* HSI - 16 MHz RC factory-trimmed + * LSI - 32 KHz RC + * HSE - On-board crystal frequency is 25MHz + * LSE - 32.768 kHz + */ + +#define STM32_BOARD_XTAL 25000000ul + +#define STM32_HSI_FREQUENCY 16000000ul +#define STM32_LSI_FREQUENCY 32000 +#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL +#define STM32_LSE_FREQUENCY 32768 + +/* Main PLL Configuration. + * + * PLL source is HSE + * PLL_VCO = (STM32_HSE_FREQUENCY / PLLM) * PLLN + * = (25,000,000 / 25) * 240 + * = 240,000,000 + * SYSCLK = PLL_VCO / PLLP + * = 240,000,000 / 2 = 120,000,000 + * USB OTG FS, SDIO and RNG Clock + * = PLL_VCO / PLLQ + * = 240,000,000 / 5 = 48,000,000 + * = 48,000,000 + */ + +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(25) +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(240) +#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_2 +#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(5) + +#define STM32_SYSCLK_FREQUENCY 120000000ul + +/* AHB clock (HCLK) is SYSCLK (120MHz) */ + +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY + +/* APB1 clock (PCLK1) is HCLK/4 (30MHz) */ + +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd4 /* PCLK1 = HCLK / 4 */ +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/4) + +/* Timers driven from APB1 will be twice PCLK1 (60Mhz) */ + +#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) + +/* APB2 clock (PCLK2) is HCLK/2 (60MHz) */ + +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLKd2 /* PCLK2 = HCLK / 2 */ +#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/2) + +/* Timers driven from APB2 will be twice PCLK2 (120Mhz) */ + +#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM9_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM10_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM11_CLKIN (2*STM32_PCLK2_FREQUENCY) + +/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx + * otherwise frequency is 2xAPBx. + * Note: TIM1,8 are on APB2, others on APB1 + */ + +#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM2_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM3_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM4_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM5_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM6_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM7_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY + +/* SDIO dividers. Note that slower clocking is required when DMA is disabled + * in order to avoid RX overrun/TX underrun errors due to delayed responses + * to service FIFOs in interrupt driven mode. These values have not been + * tuned!!! + * + * SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(118+2)=400 KHz + */ + +#define SDIO_INIT_CLKDIV (118 << SDIO_CLKCR_CLKDIV_SHIFT) + +/* DMA ON: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(1+2)=16 MHz + * DMA OFF: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(2+2)=12 MHz + */ + +#ifdef CONFIG_SDIO_DMA +# define SDIO_MMCXFR_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT) +#else +# define SDIO_MMCXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT) +#endif + +/* DMA ON: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(1+2)= 16 MHz + * DMA OFF: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(2+2)= 12 MHz + */ + +#ifdef CONFIG_SDIO_DMA +# define SDIO_SDXFR_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT) +#else +# define SDIO_SDXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT) +#endif + +/* Ethernet *****************************************************************/ + +/* We need to provide clocking to the MII PHY via MCO1 (PA8) */ + +#if defined(CONFIG_NET) && defined(CONFIG_STM32_ETHMAC) + +# if !defined(CONFIG_STM32_MII) +# warning "CONFIG_STM32_MII required for Ethernet" +# elif !defined(CONFIG_STM32_MII_MCO1) +# warning "CONFIG_STM32_MII_MCO1 required for Ethernet MII" +# else + + /* Output HSE clock (25MHz) on MCO1 pin (PA8) to clock the PHY */ + +# define BOARD_CFGR_MC01_SOURCE RCC_CFGR_MCO1_HSE +# define BOARD_CFGR_MC01_DIVIDER RCC_CFGR_MCO1PRE_NONE + +# endif +#endif + +/* LED definitions **********************************************************/ + +/* If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs in + * any way. The following definitions are used to access individual LEDs. + */ + +/* LED index values for use with board_userled() */ + +#define BOARD_LED1 0 +#define BOARD_LED2 1 +#define BOARD_LED3 2 +#define BOARD_LED4 3 +#define BOARD_NLEDS 4 + +/* LED bits for use with board_userled_all() */ + +#define BOARD_LED1_BIT (1 << BOARD_LED1) +#define BOARD_LED2_BIT (1 << BOARD_LED2) +#define BOARD_LED3_BIT (1 << BOARD_LED3) +#define BOARD_LED4_BIT (1 << BOARD_LED4) + +/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the 4 LEDs on + * board the STM3220G-EVAL. + * The following definitions describe how NuttX controls the LEDs: + */ + +#define LED_STARTED 0 /* LED1 */ +#define LED_HEAPALLOCATE 1 /* LED2 */ +#define LED_IRQSENABLED 2 /* LED1 + LED2 */ +#define LED_STACKCREATED 3 /* LED3 */ +#define LED_INIRQ 4 /* LED1 + LED3 */ +#define LED_SIGNAL 5 /* LED2 + LED3 */ +#define LED_ASSERTION 6 /* LED1 + LED2 + LED3 */ +#define LED_PANIC 7 /* N/C + N/C + N/C + LED4 */ + +/* Button definitions *******************************************************/ + +/* The STM3220G-EVAL supports three buttons: */ + +#define BUTTON_WAKEUP 0 +#define BUTTON_TAMPER 1 +#define BUTTON_USER 2 + +#define NUM_BUTTONS 3 + +#define BUTTON_WAKEUP_BIT (1 << BUTTON_WAKEUP) +#define BUTTON_TAMPER_BIT (1 << BUTTON_TAMPER) +#define BUTTON_USER_BIT (1 << BUTTON_USER) + +/* Alternate function pin selections ****************************************/ + +/* UART3: + * + * - PC11 is MicroSDCard_D3 & RS232/IrDA_RX (JP22 open) + * - PC10 is MicroSDCard_D2 & RSS232/IrDA_TX + */ + +#ifdef CONFIG_STM32_USART3 +# define GPIO_USART3_RX (GPIO_USART3_RX_2|GPIO_SPEED_100MHz) +# define GPIO_USART3_TX (GPIO_USART3_TX_2|GPIO_SPEED_100MHz) +#endif + +/* Ethernet: + * + * - PA2 is ETH_MDIO + * - PC1 is ETH_MDC + * - PB5 is ETH_PPS_OUT + * - PH2 is ETH_MII_CRS + * - PH3 is ETH_MII_COL + * - PI10 is ETH_MII_RX_ER + * - PH6 is ETH_MII_RXD2 + * - PH7 is ETH_MII_RXD3 + * - PC3 is ETH_MII_TX_CLK + * - PC2 is ETH_MII_TXD2 + * - PB8 is ETH_MII_TXD3 + * - PA1 is ETH_MII_RX_CLK/ETH_RMII_REF_CLK + * - PA7 is ETH_MII_RX_DV/ETH_RMII_CRS_DV + * - PC4 is ETH_MII_RXD0/ETH_RMII_RXD0 + * - PC5 is ETH_MII_RXD1/ETH_RMII_RXD1 + * - PG11 is ETH_MII_TX_EN/ETH_RMII_TX_EN + * - PG13 is ETH_MII_TXD0/ETH_RMII_TXD0 + * - PG14 is ETH_MII_TXD1/ETH_RMII_TXD1 + */ + +#define GPIO_MCO1 (GPIO_MCO1_0|GPIO_SPEED_100MHz) +#define GPIO_ETH_MDC (GPIO_ETH_MDC_0|GPIO_SPEED_100MHz) +#define GPIO_ETH_MDIO (GPIO_ETH_MDIO_0|GPIO_SPEED_100MHz) +#define GPIO_ETH_MII_RX_CLK (GPIO_ETH_MII_RX_CLK_0|GPIO_SPEED_100MHz) +#define GPIO_ETH_MII_RX_DV (GPIO_ETH_MII_RX_DV_0|GPIO_SPEED_100MHz) +#define GPIO_ETH_MII_RXD0 (GPIO_ETH_MII_RXD0_0|GPIO_SPEED_100MHz) +#define GPIO_ETH_MII_RXD1 (GPIO_ETH_MII_RXD1_0|GPIO_SPEED_100MHz) +#define GPIO_ETH_MII_TX_CLK (GPIO_ETH_MII_TX_CLK_0|GPIO_SPEED_100MHz) +#define GPIO_ETH_MII_TXD2 (GPIO_ETH_MII_TXD2_0|GPIO_SPEED_100MHz) +#define GPIO_ETH_RMII_CRS_DV (GPIO_ETH_RMII_CRS_DV_0|GPIO_SPEED_100MHz) +#define GPIO_ETH_RMII_REF_CLK (GPIO_ETH_RMII_REF_CLK_0|GPIO_SPEED_100MHz) +#define GPIO_ETH_RMII_RXD0 (GPIO_ETH_RMII_RXD0_0|GPIO_SPEED_100MHz) +#define GPIO_ETH_RMII_RXD1 (GPIO_ETH_RMII_RXD1_0|GPIO_SPEED_100MHz) +#define GPIO_ETH_PPS_OUT (GPIO_ETH_PPS_OUT_1|GPIO_SPEED_100MHz) +#define GPIO_ETH_MII_CRS (GPIO_ETH_MII_CRS_2|GPIO_SPEED_100MHz) +#define GPIO_ETH_MII_COL (GPIO_ETH_MII_COL_2|GPIO_SPEED_100MHz) +#define GPIO_ETH_MII_RX_ER (GPIO_ETH_MII_RX_ER_2|GPIO_SPEED_100MHz) +#define GPIO_ETH_MII_RXD2 (GPIO_ETH_MII_RXD2_2|GPIO_SPEED_100MHz) +#define GPIO_ETH_MII_RXD3 (GPIO_ETH_MII_RXD3_2|GPIO_SPEED_100MHz) +#define GPIO_ETH_MII_TXD3 (GPIO_ETH_MII_TXD3_1|GPIO_SPEED_100MHz) +#define GPIO_ETH_MII_TX_EN (GPIO_ETH_MII_TX_EN_2|GPIO_SPEED_100MHz) +#define GPIO_ETH_MII_TXD0 (GPIO_ETH_MII_TXD0_2|GPIO_SPEED_100MHz) +#define GPIO_ETH_MII_TXD1 (GPIO_ETH_MII_TXD1_2|GPIO_SPEED_100MHz) +#define GPIO_ETH_RMII_TX_EN (GPIO_ETH_RMII_TX_EN_2|GPIO_SPEED_100MHz) +#define GPIO_ETH_RMII_TXD0 (GPIO_ETH_RMII_TXD0_2|GPIO_SPEED_100MHz) +#define GPIO_ETH_RMII_TXD1 (GPIO_ETH_RMII_TXD1_2|GPIO_SPEED_100MHz) + +/* PWM + * + * The STM3220G-Eval has no real on-board PWM devices, but the board can be + * configured to output a pulse train using the following: + * + * If FSMC is not used: + * TIM4 CH2OUT: PD13 FSMC_A18 / MC_TIM4_CH2OUT + * Daughterboard Extension Connector, CN3, pin 32 + * Motor Control Connector CN15, + * pin 33 -- not available unless you bridge SB14. + * + * TIM1 CH1OUT: PE9 FSMC_D6 + * Daughterboard Extension Connector, CN2, pin 24 + * + * TIM1_CH2OUT: PE11 FSMC_D8 + * Daughterboard Extension Connector, CN2, pin 26 + * + * TIM1_CH3OUT: PE13 FSMC_D10 + * Daughterboard Extension Connector, CN2, pin 28 + * + * TIM1_CH4OUT: PE14 FSMC_D11 + * Daughterboard Extension Connector, CN2, pin 29 + * + * If OTG FS is not used + * + * TIM1_CH3OUT: PA10 OTG_FS_ID + * Daughterboard Extension Connector, CN3, pin 14 + * + * TIM1_CH4OUT: PA11 OTG_FS_DM + * Daughterboard Extension Connector, CN3, pin 11 + * + * If DMCI is not used + * + * TIM8 CH1OUT: PI5 DCMI_VSYNC & MC + * Daughterboard Extension Connector, CN4, pin 4 + * + * TIM8_CH2OUT: PI6 DCMI_D6 & MC + * Daughterboard Extension Connector, CN4, pin 3 + * + * TIM8_CH3OUT: PI7 DCMI_D7 & MC + * Daughterboard Extension Connector, CN4, pin 2 + * + * If SDIO is not used + * + * TIM8_CH3OUT: PC8 MicroSDCard_D0 & MC + * Daughterboard Extension Connector, CN3, pin 18 + * + * TIM8_CH4OUT: PC9 MicroSDCard_D1 & I2S_CKIN (Need JP16 open) + * Daughterboard Extension Connector, CN3, pin 17 + * + * Others + * + * TIM8 CH1OUT: PC6 I2S_MCK & Smartcard_IO (JP21 open) + */ + +#if !defined(CONFIG_STM32_FSMC) +# define GPIO_TIM4_CH2OUT (GPIO_TIM4_CH2OUT_2|GPIO_SPEED_50MHz) +# define GPIO_TIM1_CH1OUT (GPIO_TIM1_CH1OUT_2|GPIO_SPEED_50MHz) +# define GPIO_TIM1_CH2OUT (GPIO_TIM1_CH2OUT_2|GPIO_SPEED_50MHz) +# define GPIO_TIM1_CH3OUT (GPIO_TIM1_CH3OUT_2|GPIO_SPEED_50MHz) +# define GPIO_TIM1_CH4OUT (GPIO_TIM1_CH4OUT_2|GPIO_SPEED_50MHz) +#elif !defined(CONFIG_STM32_OTGFS) +# define GPIO_TIM1_CH3OUT (GPIO_TIM1_CH3OUT_1|GPIO_SPEED_50MHz) +# define GPIO_TIM1_CH4OUT (GPIO_TIM1_CH4OUT_1|GPIO_SPEED_50MHz) +#endif + +#if !defined(CONFIG_STM32_DCMI) +# define GPIO_TIM8_CH1OUT (GPIO_TIM8_CH1OUT_2|GPIO_SPEED_50MHz) +# define GPIO_TIM8_CH2OUT (GPIO_TIM8_CH2OUT_2|GPIO_SPEED_50MHz) +# define GPIO_TIM8_CH3OUT (GPIO_TIM8_CH3OUT_2|GPIO_SPEED_50MHz) +#else +# define GPIO_TIM8_CH1OUT (GPIO_TIM8_CH1OUT_1|GPIO_SPEED_50MHz) +# if !defined(CONFIG_STM32_SDIO) +# define GPIO_TIM8_CH3OUT (GPIO_TIM8_CH3OUT_1|GPIO_SPEED_50MHz) +# endif +#endif + +#if !defined(CONFIG_STM32_SDIO) +# define GPIO_TIM8_CH4OUT (GPIO_TIM8_CH4OUT_1|GPIO_SPEED_50MHz) +#endif + +/* CAN + * + * Connector 10 (CN10) + * is DB-9 male connector that can be used with CAN1 or CAN2. + * + * JP10 connects CAN1_RX or CAN2_RX to the CAN transceiver + * JP3 connects CAN1_TX or CAN2_TX to the CAN transceiver + * + * CAN signals are then available on CN10 pins: + * + * CN10 Pin 7 = CANH + * CN10 Pin 2 = CANL + * + * Mapping to STM32 GPIO pins: + * + * PD0 = FSMC_D2 & CAN1_RX + * PD1 = FSMC_D3 & CAN1_TX + * PB13 = ULPI_D6 & CAN2_TX + * PB5 = ULPI_D7 & CAN2_RX + */ + +#define GPIO_CAN1_RX (GPIO_CAN1_RX_3|GPIO_SPEED_50MHz) +#define GPIO_CAN1_TX (GPIO_CAN1_TX_3|GPIO_SPEED_50MHz) + +#define GPIO_CAN2_RX (GPIO_CAN2_RX_2|GPIO_SPEED_50MHz) +#define GPIO_CAN2_TX (GPIO_CAN2_TX_1|GPIO_SPEED_50MHz) + +/* I2C. + * Only I2C1 is available on the STM3220G-EVAL. I2C1_SCL and I2C1_SDA are + * available on the following pins: + * + * - PB6 is I2C1_SCL + * - PB9 is I2C1_SDA + */ + +#define GPIO_I2C1_SCL (GPIO_I2C1_SCL_1|GPIO_SPEED_50MHz) +#define GPIO_I2C1_SDA (GPIO_I2C1_SDA_2|GPIO_SPEED_50MHz) + +/* SDIO */ + +#define GPIO_SDIO_CK (GPIO_SDIO_CK_0|GPIO_SPEED_50MHz) +#define GPIO_SDIO_CMD (GPIO_SDIO_CMD_0|GPIO_SPEED_50MHz) +#define GPIO_SDIO_D0 (GPIO_SDIO_D0_0|GPIO_SPEED_50MHz) +#define GPIO_SDIO_D1 (GPIO_SDIO_D1_0|GPIO_SPEED_50MHz) +#define GPIO_SDIO_D2 (GPIO_SDIO_D2_0|GPIO_SPEED_50MHz) +#define GPIO_SDIO_D3 (GPIO_SDIO_D3_0|GPIO_SPEED_50MHz) + +/* FSMC (LCD/SRAM) */ + +#define GPIO_FSMC_NOE (GPIO_FSMC_NOE_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_NWE (GPIO_FSMC_NWE_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_NE2 (GPIO_FSMC_NE2_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_NE3 (GPIO_FSMC_NE3_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_NBL0 (GPIO_FSMC_NBL0_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_NBL1 (GPIO_FSMC_NBL1_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A0 (GPIO_FSMC_A0_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A1 (GPIO_FSMC_A1_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A2 (GPIO_FSMC_A2_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A3 (GPIO_FSMC_A3_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A4 (GPIO_FSMC_A4_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A5 (GPIO_FSMC_A5_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A6 (GPIO_FSMC_A6_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A7 (GPIO_FSMC_A7_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A8 (GPIO_FSMC_A8_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A9 (GPIO_FSMC_A9_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A10 (GPIO_FSMC_A10_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A11 (GPIO_FSMC_A11_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A12 (GPIO_FSMC_A12_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A13 (GPIO_FSMC_A13_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A14 (GPIO_FSMC_A14_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A15 (GPIO_FSMC_A15_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A16 (GPIO_FSMC_A16_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A17 (GPIO_FSMC_A17_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A18 (GPIO_FSMC_A18_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A19 (GPIO_FSMC_A19_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A20 (GPIO_FSMC_A20_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A21 (GPIO_FSMC_A21_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A22 (GPIO_FSMC_A22_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A23 (GPIO_FSMC_A23_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A24 (GPIO_FSMC_A24_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A25 (GPIO_FSMC_A25_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_D0 (GPIO_FSMC_D0_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_D1 (GPIO_FSMC_D1_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_D2 (GPIO_FSMC_D2_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_D3 (GPIO_FSMC_D3_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_D4 (GPIO_FSMC_D4_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_D5 (GPIO_FSMC_D5_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_D6 (GPIO_FSMC_D6_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_D7 (GPIO_FSMC_D7_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_D8 (GPIO_FSMC_D8_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_D9 (GPIO_FSMC_D9_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_D10 (GPIO_FSMC_D10_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_D11 (GPIO_FSMC_D11_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_D12 (GPIO_FSMC_D12_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_D13 (GPIO_FSMC_D13_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_D14 (GPIO_FSMC_D14_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_D15 (GPIO_FSMC_D15_0|GPIO_SPEED_100MHz) + +/* DMA Channel/Stream Selections ********************************************/ + +/* Stream selections are arbitrary for now but might become important in the + * future is we set aside more DMA channels/streams. + * + * SDIO DMA + * DMAMAP_SDIO_1 = Channel 4, Stream 3 + * DMAMAP_SDIO_2 = Channel 4, Stream 6 + */ + +#define DMAMAP_SDIO DMAMAP_SDIO_1 + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: stm3220g_lcdclear + * + * Description: + * This is a non-standard LCD interface just for the STM3210E-EVAL board. + * Because of the various rotations, clearing the display in the normal + * way by writing a sequences of runs that covers the entire display can be + * very slow. Here the display is cleared by simply setting all GRAM + * memory to the specified color. + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_FSMC +void stm3220g_lcdclear(uint16_t color); +#endif + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __BOARDS_ARM_STM32_STM3220G_EVAL_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32f2/stm3220g-eval/scripts/Make.defs b/boards/arm/stm32f2/stm3220g-eval/scripts/Make.defs new file mode 100644 index 0000000000000..3b902ef1830a2 --- /dev/null +++ b/boards/arm/stm32f2/stm3220g-eval/scripts/Make.defs @@ -0,0 +1,41 @@ +############################################################################ +# boards/arm/stm32f2/stm3220g-eval/scripts/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/.config +include $(TOPDIR)/tools/Config.mk +include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs + +LDSCRIPT = ld.script +ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) + +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32f2/stm3220g-eval/scripts/ld.script b/boards/arm/stm32f2/stm3220g-eval/scripts/ld.script new file mode 100644 index 0000000000000..bb2f5e12f4c53 --- /dev/null +++ b/boards/arm/stm32f2/stm3220g-eval/scripts/ld.script @@ -0,0 +1,125 @@ +/**************************************************************************** + * boards/arm/stm32f2/stm3220g-eval/scripts/ld.script + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* The STM32F207IGH6U has 1024Kb of FLASH beginning at address 0x0800:0000 and + * 128Kb of SRAM. SRAM is split up into two blocks: + * + * 1) 112Kb of SRAM beginning at address 0x2000:0000 + * 2) 16Kb of SRAM beginning at address 0x2001:c000 + * + * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 + * where the code expects to begin execution by jumping to the entry point in + * the 0x0800:0000 address + * range. + */ + +MEMORY +{ + flash (rx) : ORIGIN = 0x08000000, LENGTH = 1024K + sram (rwx) : ORIGIN = 0x20000000, LENGTH = 112K +} + +OUTPUT_ARCH(arm) +EXTERN(_vectors) +ENTRY(_stext) +SECTIONS +{ + .text : { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > flash + + .init_section : ALIGN(4) { + _sinit = ABSOLUTE(.); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) + _einit = ABSOLUTE(.); + } > flash + + .ARM.extab : ALIGN(4) { + *(.ARM.extab*) + } > flash + + .ARM.exidx : ALIGN(4) { + __exidx_start = ABSOLUTE(.); + *(.ARM.exidx*) + __exidx_end = ABSOLUTE(.); + } > flash + + .tdata : { + _stdata = ABSOLUTE(.); + *(.tdata .tdata.* .gnu.linkonce.td.*); + _etdata = ABSOLUTE(.); + } > flash + + .tbss : { + _stbss = ABSOLUTE(.); + *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); + _etbss = ABSOLUTE(.); + } > flash + + _eronly = ABSOLUTE(.); + + .data : ALIGN(4) { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > sram AT > flash + + .bss : ALIGN(4) { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + _ebss = ABSOLUTE(.); + } > sram + + /* Stabs debugging sections. */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/stm32f2/stm3220g-eval/src/CMakeLists.txt b/boards/arm/stm32f2/stm3220g-eval/src/CMakeLists.txt new file mode 100644 index 0000000000000..c198e622bed54 --- /dev/null +++ b/boards/arm/stm32f2/stm3220g-eval/src/CMakeLists.txt @@ -0,0 +1,69 @@ +# ############################################################################## +# boards/arm/stm32f2/stm3220g-eval/src/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(SRCS stm32_boot.c stm32_spi.c) + +if(CONFIG_ARCH_LEDS) + list(APPEND SRCS stm32_autoleds.c) +else() + list(APPEND SRCS stm32_userleds.c) +endif() + +if(CONFIG_ARCH_BUTTONS) + list(APPEND SRCS stm32_buttons.c) +endif() + +if(CONFIG_STM32_OTGFS) + list(APPEND SRCS stm32_usb.c) +endif() + +if(CONFIG_STM32_FSMC) + list( + APPEND + SRCS + stm32_lcd.c + stm32_selectlcd.c + stm32_deselectlcd.c + stm32_selectsram.c + stm32_deselectsram.c + stm32_extmem.c) +endif() + +if(CONFIG_ADC) + list(APPEND SRCS stm32_adc.c) +endif() + +if(CONFIG_PWM) + list(APPEND SRCS stm32_pwm.c) +endif() + +if(CONFIG_STM32_CAN_CHARDRIVER) + list(APPEND SRCS stm32_can.c) +endif() + +if(CONFIG_INPUT_STMPE811) + list(APPEND SRCS stm32_stmpe811.c) +endif() + +target_sources(board PRIVATE ${SRCS}) + +set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/ld.script") diff --git a/boards/arm/stm32f2/stm3220g-eval/src/Make.defs b/boards/arm/stm32f2/stm3220g-eval/src/Make.defs new file mode 100644 index 0000000000000..3c938b3299867 --- /dev/null +++ b/boards/arm/stm32f2/stm3220g-eval/src/Make.defs @@ -0,0 +1,63 @@ +############################################################################ +# boards/arm/stm32f2/stm3220g-eval/src/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +CSRCS = stm32_boot.c stm32_spi.c + +ifeq ($(CONFIG_ARCH_LEDS),y) +CSRCS += stm32_autoleds.c +else +CSRCS += stm32_userleds.c +endif + +ifeq ($(CONFIG_ARCH_BUTTONS),y) +CSRCS += stm32_buttons.c +endif + +ifeq ($(CONFIG_STM32_OTGFS),y) +CSRCS += stm32_usb.c +endif + +ifeq ($(CONFIG_STM32_FSMC),y) +CSRCS += stm32_lcd.c stm32_selectlcd.c stm32_deselectlcd.c stm32_selectsram.c stm32_deselectsram.c stm32_extmem.c +endif + +ifeq ($(CONFIG_ADC),y) +CSRCS += stm32_adc.c +endif + +ifeq ($(CONFIG_PWM),y) +CSRCS += stm32_pwm.c +endif + +ifeq ($(CONFIG_STM32_CAN_CHARDRIVER),y) +CSRCS += stm32_can.c +endif + +ifeq ($(CONFIG_INPUT_STMPE811),y) +CSRCS += stm32_stmpe811.c +endif + +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/stm3220g-eval/src/stm3220g-eval.h b/boards/arm/stm32f2/stm3220g-eval/src/stm3220g-eval.h similarity index 99% rename from boards/arm/stm32/stm3220g-eval/src/stm3220g-eval.h rename to boards/arm/stm32f2/stm3220g-eval/src/stm3220g-eval.h index 7908e0a422c30..775b69a377d8b 100644 --- a/boards/arm/stm32/stm3220g-eval/src/stm3220g-eval.h +++ b/boards/arm/stm32f2/stm3220g-eval/src/stm3220g-eval.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm3220g-eval/src/stm3220g-eval.h + * boards/arm/stm32f2/stm3220g-eval/src/stm3220g-eval.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f2/stm3220g-eval/src/stm32_adc.c b/boards/arm/stm32f2/stm3220g-eval/src/stm32_adc.c new file mode 100644 index 0000000000000..347835c5d36a1 --- /dev/null +++ b/boards/arm/stm32f2/stm3220g-eval/src/stm32_adc.c @@ -0,0 +1,157 @@ +/**************************************************************************** + * boards/arm/stm32f2/stm3220g-eval/src/stm32_adc.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32_pwm.h" +#include "stm3220g-eval.h" + +#ifdef CONFIG_ADC + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* Up to 3 ADC interfaces are supported */ + +#if STM32_NADC < 3 +# undef CONFIG_STM32_ADC3 +#endif + +#if STM32_NADC < 2 +# undef CONFIG_STM32_ADC2 +#endif + +#if STM32_NADC < 1 +# undef CONFIG_STM32_ADC1 +#endif + +#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) || defined(CONFIG_STM32_ADC3) +#ifndef CONFIG_STM32_ADC3 +# warning "Channel information only available for ADC3" +#endif + +/* The number of ADC channels in the conversion list */ + +#define ADC3_NCHANNELS 1 + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* The STM3220G-EVAL has a 10 Kohm potentiometer RV1 connected to PF9 of + * STM32F207IGH6 on the board: TIM14_CH1/FSMC_CD/ADC3_IN7 + */ + +/* Identifying number of each ADC channel: Variable Resistor. */ + +#ifdef CONFIG_STM32_ADC3 +static const uint8_t g_chanlist[ADC3_NCHANNELS] = +{ + 7 +}; + +/* Configurations of pins used byte each ADC channels */ + +static const uint32_t g_pinlist[ADC3_NCHANNELS] = +{ + GPIO_ADC3_IN7 +}; +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_adc_setup + * + * Description: + * Initialize ADC and register the ADC driver. + * + ****************************************************************************/ + +int stm32_adc_setup(void) +{ +#ifdef CONFIG_STM32_ADC3 + static bool initialized = false; + struct adc_dev_s *adc; + int ret; + int i; + + /* Check if we have already initialized */ + + if (!initialized) + { + /* Configure the pins as analog inputs for the selected channels */ + + for (i = 0; i < ADC3_NCHANNELS; i++) + { + stm32_configgpio(g_pinlist[i]); + } + + /* Call stm32_adcinitialize() to get an instance of the ADC interface */ + + adc = stm32_adcinitialize(3, g_chanlist, ADC3_NCHANNELS); + if (adc == NULL) + { + aerr("ERROR: Failed to get ADC interface\n"); + return -ENODEV; + } + + /* Register the ADC driver at "/dev/adc0" */ + + ret = adc_register("/dev/adc0", adc); + if (ret < 0) + { + aerr("ERROR: adc_register failed: %d\n", ret); + return ret; + } + + /* Now we are initialized */ + + initialized = true; + } + + return OK; +#else + return -ENOSYS; +#endif +} + +#endif /* CONFIG_STM32_ADC1 || CONFIG_STM32_ADC2 || CONFIG_STM32_ADC3 */ +#endif /* CONFIG_ADC */ diff --git a/boards/arm/stm32f2/stm3220g-eval/src/stm32_autoleds.c b/boards/arm/stm32f2/stm3220g-eval/src/stm32_autoleds.c new file mode 100644 index 0000000000000..58d3ebc7653ac --- /dev/null +++ b/boards/arm/stm32f2/stm3220g-eval/src/stm32_autoleds.c @@ -0,0 +1,232 @@ +/**************************************************************************** + * boards/arm/stm32f2/stm3220g-eval/src/stm32_autoleds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32.h" +#include "stm3220g-eval.h" + +#ifdef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* The following definitions map the encoded LED setting to GPIO settings */ + +#define STM3210E_LED1 (1 << 0) +#define STM3210E_LED2 (1 << 1) +#define STM3210E_LED3 (1 << 2) +#define STM3210E_LED4 (1 << 3) + +#define ON_SETBITS_SHIFT (0) +#define ON_CLRBITS_SHIFT (4) +#define OFF_SETBITS_SHIFT (8) +#define OFF_CLRBITS_SHIFT (12) + +#define ON_BITS(v) ((v) & 0xff) +#define OFF_BITS(v) (((v) >> 8) & 0x0ff) +#define SETBITS(b) ((b) & 0x0f) +#define CLRBITS(b) (((b) >> 4) & 0x0f) + +#define ON_SETBITS(v) (SETBITS(ON_BITS(v)) +#define ON_CLRBITS(v) (CLRBITS(ON_BITS(v)) +#define OFF_SETBITS(v) (SETBITS(OFF_BITS(v)) +#define OFF_CLRBITS(v) (CLRBITS(OFF_BITS(v)) + +#define LED_STARTED_ON_SETBITS ((STM3210E_LED1) << ON_SETBITS_SHIFT) +#define LED_STARTED_ON_CLRBITS ((STM3210E_LED2|STM3210E_LED3|STM3210E_LED4) << ON_CLRBITS_SHIFT) +#define LED_STARTED_OFF_SETBITS (0 << OFF_SETBITS_SHIFT) +#define LED_STARTED_OFF_CLRBITS ((STM3210E_LED1|STM3210E_LED2|STM3210E_LED3|STM3210E_LED4) << OFF_CLRBITS_SHIFT) + +#define LED_HEAPALLOCATE_ON_SETBITS ((STM3210E_LED2) << ON_SETBITS_SHIFT) +#define LED_HEAPALLOCATE_ON_CLRBITS ((STM3210E_LED1|STM3210E_LED3|STM3210E_LED4) << ON_CLRBITS_SHIFT) +#define LED_HEAPALLOCATE_OFF_SETBITS ((STM3210E_LED1) << OFF_SETBITS_SHIFT) +#define LED_HEAPALLOCATE_OFF_CLRBITS ((STM3210E_LED2|STM3210E_LED3|STM3210E_LED4) << OFF_CLRBITS_SHIFT) + +#define LED_IRQSENABLED_ON_SETBITS ((STM3210E_LED1|STM3210E_LED2) << ON_SETBITS_SHIFT) +#define LED_IRQSENABLED_ON_CLRBITS ((STM3210E_LED3|STM3210E_LED4) << ON_CLRBITS_SHIFT) +#define LED_IRQSENABLED_OFF_SETBITS ((STM3210E_LED2) << OFF_SETBITS_SHIFT) +#define LED_IRQSENABLED_OFF_CLRBITS ((STM3210E_LED1|STM3210E_LED3|STM3210E_LED4) << OFF_CLRBITS_SHIFT) + +#define LED_STACKCREATED_ON_SETBITS ((STM3210E_LED3) << ON_SETBITS_SHIFT) +#define LED_STACKCREATED_ON_CLRBITS ((STM3210E_LED1|STM3210E_LED2|STM3210E_LED4) << ON_CLRBITS_SHIFT) +#define LED_STACKCREATED_OFF_SETBITS ((STM3210E_LED1|STM3210E_LED2) << OFF_SETBITS_SHIFT) +#define LED_STACKCREATED_OFF_CLRBITS ((STM3210E_LED3|STM3210E_LED4) << OFF_CLRBITS_SHIFT) + +#define LED_INIRQ_ON_SETBITS ((STM3210E_LED1) << ON_SETBITS_SHIFT) +#define LED_INIRQ_ON_CLRBITS ((0) << ON_CLRBITS_SHIFT) +#define LED_INIRQ_OFF_SETBITS ((0) << OFF_SETBITS_SHIFT) +#define LED_INIRQ_OFF_CLRBITS ((STM3210E_LED1) << OFF_CLRBITS_SHIFT) + +#define LED_SIGNAL_ON_SETBITS ((STM3210E_LED2) << ON_SETBITS_SHIFT) +#define LED_SIGNAL_ON_CLRBITS ((0) << ON_CLRBITS_SHIFT) +#define LED_SIGNAL_OFF_SETBITS ((0) << OFF_SETBITS_SHIFT) +#define LED_SIGNAL_OFF_CLRBITS ((STM3210E_LED2) << OFF_CLRBITS_SHIFT) + +#define LED_ASSERTION_ON_SETBITS ((STM3210E_LED4) << ON_SETBITS_SHIFT) +#define LED_ASSERTION_ON_CLRBITS ((0) << ON_CLRBITS_SHIFT) +#define LED_ASSERTION_OFF_SETBITS ((0) << OFF_SETBITS_SHIFT) +#define LED_ASSERTION_OFF_CLRBITS ((STM3210E_LED4) << OFF_CLRBITS_SHIFT) + +#define LED_PANIC_ON_SETBITS ((STM3210E_LED4) << ON_SETBITS_SHIFT) +#define LED_PANIC_ON_CLRBITS ((0) << ON_CLRBITS_SHIFT) +#define LED_PANIC_OFF_SETBITS ((0) << OFF_SETBITS_SHIFT) +#define LED_PANIC_OFF_CLRBITS ((STM3210E_LED4) << OFF_CLRBITS_SHIFT) + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static const uint16_t g_ledbits[8] = +{ + (LED_STARTED_ON_SETBITS | LED_STARTED_ON_CLRBITS | + LED_STARTED_OFF_SETBITS | LED_STARTED_OFF_CLRBITS), + + (LED_HEAPALLOCATE_ON_SETBITS | LED_HEAPALLOCATE_ON_CLRBITS | + LED_HEAPALLOCATE_OFF_SETBITS | LED_HEAPALLOCATE_OFF_CLRBITS), + + (LED_IRQSENABLED_ON_SETBITS | LED_IRQSENABLED_ON_CLRBITS | + LED_IRQSENABLED_OFF_SETBITS | LED_IRQSENABLED_OFF_CLRBITS), + + (LED_STACKCREATED_ON_SETBITS | LED_STACKCREATED_ON_CLRBITS | + LED_STACKCREATED_OFF_SETBITS | LED_STACKCREATED_OFF_CLRBITS), + + (LED_INIRQ_ON_SETBITS | LED_INIRQ_ON_CLRBITS | + LED_INIRQ_OFF_SETBITS | LED_INIRQ_OFF_CLRBITS), + + (LED_SIGNAL_ON_SETBITS | LED_SIGNAL_ON_CLRBITS | + LED_SIGNAL_OFF_SETBITS | LED_SIGNAL_OFF_CLRBITS), + + (LED_ASSERTION_ON_SETBITS | LED_ASSERTION_ON_CLRBITS | + LED_ASSERTION_OFF_SETBITS | LED_ASSERTION_OFF_CLRBITS), + + (LED_PANIC_ON_SETBITS | LED_PANIC_ON_CLRBITS | + LED_PANIC_OFF_SETBITS | LED_PANIC_OFF_CLRBITS) +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +static inline void led_clrbits(unsigned int clrbits) +{ + if ((clrbits & STM3210E_LED1) != 0) + { + stm32_gpiowrite(GPIO_LED1, false); + } + + if ((clrbits & STM3210E_LED2) != 0) + { + stm32_gpiowrite(GPIO_LED2, false); + } + + if ((clrbits & STM3210E_LED3) != 0) + { + stm32_gpiowrite(GPIO_LED3, false); + } + + if ((clrbits & STM3210E_LED4) != 0) + { + stm32_gpiowrite(GPIO_LED4, false); + } +} + +static inline void led_setbits(unsigned int setbits) +{ + if ((setbits & STM3210E_LED1) != 0) + { + stm32_gpiowrite(GPIO_LED1, true); + } + + if ((setbits & STM3210E_LED2) != 0) + { + stm32_gpiowrite(GPIO_LED2, true); + } + + if ((setbits & STM3210E_LED3) != 0) + { + stm32_gpiowrite(GPIO_LED3, true); + } + + if ((setbits & STM3210E_LED4) != 0) + { + stm32_gpiowrite(GPIO_LED4, true); + } +} + +static void led_setonoff(unsigned int bits) +{ + led_clrbits(CLRBITS(bits)); + led_setbits(SETBITS(bits)); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_autoled_initialize + ****************************************************************************/ + +void board_autoled_initialize(void) +{ + /* Configure LED1-4 GPIOs for output */ + + stm32_configgpio(GPIO_LED1); + stm32_configgpio(GPIO_LED2); + stm32_configgpio(GPIO_LED3); + stm32_configgpio(GPIO_LED4); +} + +/**************************************************************************** + * Name: board_autoled_on + ****************************************************************************/ + +void board_autoled_on(int led) +{ + led_setonoff(ON_BITS(g_ledbits[led])); +} + +/**************************************************************************** + * Name: board_autoled_off + ****************************************************************************/ + +void board_autoled_off(int led) +{ + led_setonoff(OFF_BITS(g_ledbits[led])); +} + +#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32f2/stm3220g-eval/src/stm32_boot.c b/boards/arm/stm32f2/stm3220g-eval/src/stm32_boot.c new file mode 100644 index 0000000000000..f73fd6ed35a54 --- /dev/null +++ b/boards/arm/stm32f2/stm3220g-eval/src/stm32_boot.c @@ -0,0 +1,368 @@ +/**************************************************************************** + * boards/arm/stm32f2/stm3220g-eval/src/stm32_boot.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include +#include +#include + +#include +#include +#include + +#ifdef CONFIG_STM32_SPI1 +# include +# include +#endif + +#ifdef CONFIG_STM32_SDIO +# include +# include +#endif + +#ifdef CONFIG_STM32_OTGFS +# include "stm32_usbhost.h" +#endif + +#include "arm_internal.h" +#include "stm32.h" +#include "stm32_i2c.h" +#include "stm3220g-eval.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* For now, don't build in any SPI1 support -- NSH is not using it */ + +#undef CONFIG_STM32_SPI1 + +/* MMCSD PORT and SLOT number probably depend on the board configuration */ + +#define HAVE_USBDEV 1 +#define HAVE_MMCSD 1 +#define HAVE_USBHOST 1 + +#if defined(CONFIG_NSH_MMCSDSLOTNO) && CONFIG_NSH_MMCSDSLOTNO != 0 +# error "Only one MMC/SD slot" +# undef CONFIG_NSH_MMCSDSLOTNO +#endif + +#ifndef CONFIG_NSH_MMCSDSLOTNO +# define CONFIG_NSH_MMCSDSLOTNO 0 +#endif + +/* Can't support MMC/SD features if mountpoints are disabled or if SDIO + * support is not enabled. + */ + +#if defined(CONFIG_DISABLE_MOUNTPOINT) || !defined(CONFIG_STM32_SDIO) +# undef HAVE_MMCSD +#endif + +#ifndef CONFIG_NSH_MMCSDMINOR +# define CONFIG_NSH_MMCSDMINOR 0 +#endif + +/* Can't support USB host or device features if USB OTG FS is not enabled */ + +#ifndef CONFIG_STM32_OTGFS +# undef HAVE_USBDEV +# undef HAVE_USBHOST +#endif + +/* Can't support USB device is USB device is not enabled */ + +#ifndef CONFIG_USBDEV +# undef HAVE_USBDEV +#endif + +/* Can't support USB host is USB host is not enabled */ + +#ifndef CONFIG_USBHOST +# undef HAVE_USBHOST +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_i2c_register + * + * Description: + * Register one I2C drivers for the I2C tool. + * + ****************************************************************************/ + +#ifdef HAVE_I2CTOOL +static void stm32_i2c_register(int bus) +{ + struct i2c_master_s *i2c; + int ret; + + i2c = stm32_i2cbus_initialize(bus); + if (i2c == NULL) + { + _err("ERROR: Failed to get I2C%d interface\n", bus); + } + else + { + ret = i2c_register(i2c, bus); + if (ret < 0) + { + _err("ERROR: Failed to register I2C%d driver: %d\n", bus, ret); + stm32_i2cbus_uninitialize(i2c); + } + } +} +#endif + +/**************************************************************************** + * Name: stm32_i2ctool + * + * Description: + * Register I2C drivers for the I2C tool. + * + ****************************************************************************/ + +#ifdef HAVE_I2CTOOL +static void stm32_i2ctool(void) +{ +#ifdef CONFIG_STM32_I2C1 + stm32_i2c_register(1); +#endif +#ifdef CONFIG_STM32_I2C2 + stm32_i2c_register(2); +#endif +#ifdef CONFIG_STM32_I2C3 + stm32_i2c_register(3); +#endif +} +#else +# define stm32_i2ctool() +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_boardinitialize + * + * Description: + * All STM32 architectures must provide the following entry point. + * This entry point is called early in the initialization -- after all + * memory has been configured and mapped but before any devices have been + * initialized. + * + ****************************************************************************/ + +void stm32_boardinitialize(void) +{ + /* Configure SPI chip selects if 1) SPI is not disabled, and 2) the weak + * function stm32_spidev_initialize() has been brought into the link. + */ + +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || defined(CONFIG_STM32_SPI3) + if (stm32_spidev_initialize) + { + stm32_spidev_initialize(); + } +#endif + + /* If the FSMC is enabled, then enable SRAM access */ + +#ifdef CONFIG_STM32_FSMC + stm32_selectsram(); +#endif + + /* Initialize USB if the 1) OTG FS controller is in the configuration and + * 2) the weak function stm32_usbinitialize() has been brought into the + * build. + * Presumably either CONFIG_USBDEV or CONFIG_USBHOST is also selected. + */ + +#ifdef CONFIG_STM32_OTGFS + if (stm32_usbinitialize) + { + stm32_usbinitialize(); + } +#endif + + /* Configure on-board LEDs if LED support has been selected. */ + +#ifdef CONFIG_ARCH_LEDS + board_autoled_initialize(); +#endif +} + +/**************************************************************************** + * Name: board_late_initialize + * + * Description: + * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_late_initialize(). board_late_initialize() will be + * called immediately after up_initialize() is called and just before the + * initial application is started. This additional initialization phase + * may be used, for example, to initialize board-specific device drivers. + * + ****************************************************************************/ + +#ifdef CONFIG_BOARD_LATE_INITIALIZE +void board_late_initialize(void) +{ +#ifdef CONFIG_STM32_SPI1 + struct spi_dev_s *spi; + struct mtd_dev_s *mtd; +#endif +#ifdef HAVE_MMCSD + struct sdio_dev_s *sdio; +#endif + int ret; + + /* Register I2C drivers on behalf of the I2C tool */ + + stm32_i2ctool(); + + /* Configure SPI-based devices */ + +#ifdef CONFIG_STM32_SPI1 + /* Get the SPI port */ + + spi = stm32_spibus_initialize(1); + if (!spi) + { + syslog(LOG_ERR, "ERROR: Failed to initialize SPI port 0\n"); + return; + } + + /* Now bind the SPI interface to the M25P64/128 SPI FLASH driver */ + + mtd = m25p_initialize(spi); + if (!mtd) + { + syslog(LOG_ERR, + "ERROR: Failed to bind SPI port 0 to the SPI FLASH driver\n"); + return; + } + +#warning "Now what are we going to do with this SPI FLASH driver?" +#endif + + /* Mount the SDIO-based MMC/SD block driver */ + +#ifdef HAVE_MMCSD + /* First, get an instance of the SDIO interface */ + + sdio = sdio_initialize(CONFIG_NSH_MMCSDSLOTNO); + if (!sdio) + { + syslog(LOG_ERR, "ERROR: Failed to initialize SDIO slot %d\n", + CONFIG_NSH_MMCSDSLOTNO); + return; + } + + /* Now bind the SDIO interface to the MMC/SD driver */ + + ret = mmcsd_slotinitialize(CONFIG_NSH_MMCSDMINOR, sdio); + if (ret != OK) + { + syslog(LOG_ERR, + "ERROR: Failed to bind SDIO to the MMC/SD driver: %d\n", ret); + return; + } + + /* Then let's guess and say that there is a card in the slot. I need to + * check to see if the STM3220G-EVAL board supports a GPIO to detect if + * there is a card in the slot. + */ + + sdio_mediachange(sdio, true); +#endif + + /* Initialize USB host operation. stm32_usbhost_initialize() starts a + * thread will monitor for USB connection and disconnection events. + */ + +#ifdef HAVE_USBHOST + ret = stm32_usbhost_initialize(); + if (ret != OK) + { + syslog(LOG_ERR, "ERROR: Failed to initialize USB host: %d\n", ret); + return; + } +#endif + +#ifdef CONFIG_INPUT_STMPE811 + /* Initialize the touchscreen */ + + ret = stm32_tsc_setup(0); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_tsc_setup failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_PWM + /* Initialize PWM and register the PWM device. */ + + ret = stm32_pwm_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_pwm_setup() failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_ADC + /* Initialize ADC and register the ADC driver. */ + + ret = stm32_adc_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_adc_setup failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_STM32_CAN_CHARDRIVER + /* Initialize CAN and register the CAN driver. */ + + ret = stm32_can_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_can_setup failed: %d\n", ret); + } +#endif + + UNUSED(ret); +} +#endif diff --git a/boards/arm/stm32f2/stm3220g-eval/src/stm32_buttons.c b/boards/arm/stm32f2/stm3220g-eval/src/stm32_buttons.c new file mode 100644 index 0000000000000..f054a70494d16 --- /dev/null +++ b/boards/arm/stm32f2/stm3220g-eval/src/stm32_buttons.c @@ -0,0 +1,156 @@ +/**************************************************************************** + * boards/arm/stm32f2/stm3220g-eval/src/stm32_buttons.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include +#include + +#include "stm3220g-eval.h" + +#ifdef CONFIG_ARCH_BUTTONS + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* Pin configuration for each STM3210E-EVAL button. This array is indexed by + * the BUTTON_* and JOYSTICK_* definitions in board.h + */ + +static const uint32_t g_buttons[NUM_BUTTONS] = +{ + GPIO_BTN_WAKEUP, GPIO_BTN_TAMPER, GPIO_BTN_USER +}; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_button_initialize + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. + * + ****************************************************************************/ + +uint32_t board_button_initialize(void) +{ + int i; + + /* Configure the GPIO pins as inputs. NOTE that EXTI interrupts are + * configured for all pins. + */ + + for (i = 0; i < NUM_BUTTONS; i++) + { + stm32_configgpio(g_buttons[i]); + } + + return NUM_BUTTONS; +} + +/**************************************************************************** + * Name: board_buttons + ****************************************************************************/ + +uint32_t board_buttons(void) +{ + uint32_t ret = 0; + int i; + + /* Check that state of each key */ + + for (i = 0; i < NUM_BUTTONS; i++) + { + /* A LOW value means that the key is pressed for most keys. + * The exception is the WAKEUP button. + */ + + bool released = stm32_gpioread(g_buttons[i]); + if (i == BUTTON_WAKEUP) + { + released = !released; + } + + /* Accumulate the set of depressed (not released) keys */ + + if (!released) + { + ret |= (1 << i); + } + } + + return ret; +} + +/**************************************************************************** + * Button support. + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. + * + * After board_button_initialize() has been called, board_buttons() may be + * called to collect the state of all buttons. board_buttons() returns an + * 32-bit bit set with each bit associated with a button. See the + * BUTTON_*_BIT definitions in board.h for the meaning of each bit. + * + * board_button_irq() may be called to register an interrupt handler that + * will be called when a button is depressed or released. The ID value is a + * button enumeration value that uniquely identifies a button resource. See + * the BUTTON_* definitions in board.h for the meaning of enumeration + * value. + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_IRQBUTTONS +int board_button_irq(int id, xcpt_t irqhandler, void *arg) +{ + int ret = -EINVAL; + + /* The following should be atomic */ + + if (id >= MIN_IRQBUTTON && id <= MAX_IRQBUTTON) + { + ret = stm32_gpiosetevent(g_buttons[id], true, true, true, + irqhandler, arg); + } + + return ret; +} +#endif +#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/stm32f2/stm3220g-eval/src/stm32_can.c b/boards/arm/stm32f2/stm3220g-eval/src/stm32_can.c new file mode 100644 index 0000000000000..5a2826f4674ff --- /dev/null +++ b/boards/arm/stm32f2/stm3220g-eval/src/stm32_can.c @@ -0,0 +1,102 @@ +/**************************************************************************** + * boards/arm/stm32f2/stm3220g-eval/src/stm32_can.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32.h" +#include "stm32_can.h" +#include "stm3220g-eval.h" + +#ifdef CONFIG_CAN + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +#if defined(CONFIG_STM32_CAN1) && defined(CONFIG_STM32_CAN2) +# warning "Both CAN1 and CAN2 are enabled. Assuming only CAN1." +# undef CONFIG_STM32_CAN2 +#endif + +#ifdef CONFIG_STM32_CAN1 +# define CAN_PORT 1 +#else +# define CAN_PORT 2 +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_can_setup + * + * Description: + * Initialize CAN and register the CAN device + * + ****************************************************************************/ + +int stm32_can_setup(void) +{ +#if defined(CONFIG_STM32_CAN1) || defined(CONFIG_STM32_CAN2) + struct can_dev_s *can; + int ret; + + /* Call stm32_caninitialize() to get an instance of the CAN interface */ + + can = stm32_caninitialize(CAN_PORT); + if (can == NULL) + { + canerr("ERROR: Failed to get CAN interface\n"); + return -ENODEV; + } + + /* Register the CAN driver at "/dev/can0" */ + + ret = can_register("/dev/can0", can); + if (ret < 0) + { + canerr("ERROR: can_register failed: %d\n", ret); + return ret; + } + + return OK; +#else + return -ENODEV; +#endif +} + +#endif /* CONFIG_CAN */ diff --git a/boards/arm/stm32f2/stm3220g-eval/src/stm32_deselectlcd.c b/boards/arm/stm32f2/stm3220g-eval/src/stm32_deselectlcd.c new file mode 100644 index 0000000000000..3ef672f986de7 --- /dev/null +++ b/boards/arm/stm32f2/stm3220g-eval/src/stm32_deselectlcd.c @@ -0,0 +1,80 @@ +/**************************************************************************** + * boards/arm/stm32f2/stm3220g-eval/src/stm32_deselectlcd.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include "arm_internal.h" +#include "stm32.h" +#include "stm3220g-eval.h" + +#ifdef CONFIG_STM32_FSMC + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_deselectlcd + * + * Description: + * Disable the LCD + * + ****************************************************************************/ + +void stm32_deselectlcd(void) +{ + /* Restore registers to their power up settings */ + + putreg32(0xffffffff, STM32_FSMC_BCR4); + + /* Bank1 NOR/SRAM timing register configuration */ + + putreg32(0x0fffffff, STM32_FSMC_BTR4); + + /* Disable AHB clocking to the FSMC */ + + stm32_fsmc_disable(); +} + +#endif /* CONFIG_STM32_FSMC */ diff --git a/boards/arm/stm32f2/stm3220g-eval/src/stm32_deselectsram.c b/boards/arm/stm32f2/stm3220g-eval/src/stm32_deselectsram.c new file mode 100644 index 0000000000000..e1fe12d86a533 --- /dev/null +++ b/boards/arm/stm32f2/stm3220g-eval/src/stm32_deselectsram.c @@ -0,0 +1,80 @@ +/**************************************************************************** + * boards/arm/stm32f2/stm3220g-eval/src/stm32_deselectsram.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include "arm_internal.h" +#include "stm32.h" +#include "stm3220g-eval.h" + +#ifdef CONFIG_STM32_FSMC + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_deselectsram + * + * Description: + * Disable SRAM + * + ****************************************************************************/ + +void stm32_deselectsram(void) +{ + /* Restore registers to their power up settings */ + + putreg32(FSMC_BCR_RSTVALUE, STM32_FSMC_BCR2); + + /* Bank1 NOR/SRAM timing register configuration */ + + putreg32(FSMC_BTR_RSTVALUE, STM32_FSMC_BTR2); + + /* Disable AHB clocking to the FSMC */ + + stm32_fsmc_disable(); +} + +#endif /* CONFIG_STM32_FSMC */ diff --git a/boards/arm/stm32f2/stm3220g-eval/src/stm32_extmem.c b/boards/arm/stm32f2/stm3220g-eval/src/stm32_extmem.c new file mode 100644 index 0000000000000..7a0344fcc7e5e --- /dev/null +++ b/boards/arm/stm32f2/stm3220g-eval/src/stm32_extmem.c @@ -0,0 +1,141 @@ +/**************************************************************************** + * boards/arm/stm32f2/stm3220g-eval/src/stm32_extmem.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32_gpio.h" +#include "stm32.h" +#include "stm3220g-eval.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifndef CONFIG_STM32_FSMC +# warning "FSMC is not enabled" +#endif + +#if STM32_NGPIO_PORTS < 6 +# error "Required GPIO ports not enabled" +#endif + +#define STM32_FSMC_NADDRCONFIGS 26 +#define STM32_FSMC_NDATACONFIGS 16 + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/* GPIO configurations common to most external memories */ + +static const uint32_t g_addressconfig[STM32_FSMC_NADDRCONFIGS] = +{ + GPIO_FSMC_A0, GPIO_FSMC_A1, GPIO_FSMC_A2, + GPIO_FSMC_A3, GPIO_FSMC_A4, GPIO_FSMC_A5, + GPIO_FSMC_A6, GPIO_FSMC_A7, GPIO_FSMC_A8, + GPIO_FSMC_A9, GPIO_FSMC_A10, GPIO_FSMC_A11, + GPIO_FSMC_A12, GPIO_FSMC_A13, GPIO_FSMC_A14, + GPIO_FSMC_A15, GPIO_FSMC_A16, GPIO_FSMC_A17, + GPIO_FSMC_A18, GPIO_FSMC_A19, GPIO_FSMC_A20, + GPIO_FSMC_A21, GPIO_FSMC_A22, GPIO_FSMC_A23, + GPIO_FSMC_A24, GPIO_FSMC_A25 +}; + +static const uint32_t g_dataconfig[STM32_FSMC_NDATACONFIGS] = +{ + GPIO_FSMC_D0, GPIO_FSMC_D1, GPIO_FSMC_D2, + GPIO_FSMC_D3, GPIO_FSMC_D4, GPIO_FSMC_D5, + GPIO_FSMC_D6, GPIO_FSMC_D7, GPIO_FSMC_D8, + GPIO_FSMC_D9, GPIO_FSMC_D10, GPIO_FSMC_D11, + GPIO_FSMC_D12, GPIO_FSMC_D13, GPIO_FSMC_D14, + GPIO_FSMC_D15 +}; + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_extmemgpios + * + * Description: + * Initialize GPIOs for external memory usage + * + ****************************************************************************/ + +void stm32_extmemgpios(const uint32_t *gpios, int ngpios) +{ + int i; + + /* Configure GPIOs */ + + for (i = 0; i < ngpios; i++) + { + stm32_configgpio(gpios[i]); + } +} + +/**************************************************************************** + * Name: stm32_extmemaddr + * + * Description: + * Initialize address line GPIOs for external memory access + * + ****************************************************************************/ + +void stm32_extmemaddr(int naddrs) +{ + stm32_extmemgpios(g_addressconfig, naddrs); +} + +/**************************************************************************** + * Name: stm32_extmemdata + * + * Description: + * Initialize data line GPIOs for external memory access + * + ****************************************************************************/ + +void stm32_extmemdata(int ndata) +{ + stm32_extmemgpios(g_dataconfig, ndata); +} diff --git a/boards/arm/stm32f2/stm3220g-eval/src/stm32_lcd.c b/boards/arm/stm32f2/stm3220g-eval/src/stm32_lcd.c new file mode 100644 index 0000000000000..d8c10b4639535 --- /dev/null +++ b/boards/arm/stm32f2/stm3220g-eval/src/stm32_lcd.c @@ -0,0 +1,1186 @@ +/**************************************************************************** + * boards/arm/stm32f2/stm3220g-eval/src/stm32_lcd.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* This driver supports the following LCDs on the STM324xG_EVAL board: + * + * AM-240320L8TNQW00H (LCD_ILI9320 or LCD_ILI9321) OR + * AM-240320D5TOQW01H (LCD_ILI9325) + */ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include + +#include "arm_internal.h" +#include "stm32.h" +#include "stm3220g-eval.h" + +#if !defined(CONFIG_STM32_ILI9320_DISABLE) || !defined(CONFIG_STM32_ILI9325_DISABLE) + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* CONFIG_STM32_ILI9320_DISABLE may be defined to disabled the + * AM-240320L8TNQW00H (LCD_ILI9320 or LCD_ILI9321) + * CONFIG_STM32_ILI9325_DISABLE may be defined to disabled the + * AM-240320D5TOQW01H (LCD_ILI9325) + */ + +/* Check contrast selection */ + +#if !defined(CONFIG_LCD_MAXCONTRAST) +# define CONFIG_LCD_MAXCONTRAST 1 +#endif + +/* Check power setting */ + +#if !defined(CONFIG_LCD_MAXPOWER) || CONFIG_LCD_MAXPOWER < 1 +# define CONFIG_LCD_MAXPOWER 1 +#endif + +#if CONFIG_LCD_MAXPOWER > 255 +# error "CONFIG_LCD_MAXPOWER must be less than 256 to fit in uint8_t" +#endif + +/* Check orientation */ + +#if defined(CONFIG_LCD_PORTRAIT) +# if defined(CONFIG_LCD_LANDSCAPE) || defined(CONFIG_LCD_RLANDSCAPE) || defined(CONFIG_LCD_RPORTRAIT) +# error "Cannot define both portrait and any other orientations" +# endif +#elif defined(CONFIG_LCD_RPORTRAIT) +# if defined(CONFIG_LCD_LANDSCAPE) || defined(CONFIG_LCD_RLANDSCAPE) +# error "Cannot define both rportrait and any other orientations" +# endif +#elif defined(CONFIG_LCD_LANDSCAPE) +# ifdef CONFIG_LCD_RLANDSCAPE +# error "Cannot define both landscape and any other orientations" +# endif +#elif !defined(CONFIG_LCD_RLANDSCAPE) +# define CONFIG_LCD_LANDSCAPE 1 +#endif + +/* Display/Color Properties *************************************************/ + +/* Display Resolution */ + +#if defined(CONFIG_LCD_LANDSCAPE) || defined(CONFIG_LCD_RLANDSCAPE) +# define STM3220G_XRES 320 +# define STM3220G_YRES 240 +#else +# define STM3220G_XRES 240 +# define STM3220G_YRES 320 +#endif + +/* Color depth and format */ + +#define STM3220G_BPP 16 +#define STM3220G_COLORFMT FB_FMT_RGB16_565 + +/* STM3220G-EVAL LCD Hardware Definitions ***********************************/ + +/* LCD /CS is CE4, Bank 3 of NOR/SRAM Bank 1~4 */ + +#define STM3220G_LCDBASE ((uintptr_t)(0x60000000 | 0x08000000)) +#define LCD ((struct lcd_regs_s *)STM3220G_LCDBASE) + +#define LCD_REG_0 0x00 +#define LCD_REG_1 0x01 +#define LCD_REG_2 0x02 +#define LCD_REG_3 0x03 +#define LCD_REG_4 0x04 +#define LCD_REG_5 0x05 +#define LCD_REG_6 0x06 +#define LCD_REG_7 0x07 +#define LCD_REG_8 0x08 +#define LCD_REG_9 0x09 +#define LCD_REG_10 0x0a +#define LCD_REG_12 0x0c +#define LCD_REG_13 0x0d +#define LCD_REG_14 0x0e +#define LCD_REG_15 0x0f +#define LCD_REG_16 0x10 +#define LCD_REG_17 0x11 +#define LCD_REG_18 0x12 +#define LCD_REG_19 0x13 +#define LCD_REG_20 0x14 +#define LCD_REG_21 0x15 +#define LCD_REG_22 0x16 +#define LCD_REG_23 0x17 +#define LCD_REG_24 0x18 +#define LCD_REG_25 0x19 +#define LCD_REG_26 0x1a +#define LCD_REG_27 0x1b +#define LCD_REG_28 0x1c +#define LCD_REG_29 0x1d +#define LCD_REG_30 0x1e +#define LCD_REG_31 0x1f +#define LCD_REG_32 0x20 +#define LCD_REG_33 0x21 +#define LCD_REG_34 0x22 +#define LCD_REG_36 0x24 +#define LCD_REG_37 0x25 +#define LCD_REG_40 0x28 +#define LCD_REG_41 0x29 +#define LCD_REG_43 0x2b +#define LCD_REG_45 0x2d +#define LCD_REG_48 0x30 +#define LCD_REG_49 0x31 +#define LCD_REG_50 0x32 +#define LCD_REG_51 0x33 +#define LCD_REG_52 0x34 +#define LCD_REG_53 0x35 +#define LCD_REG_54 0x36 +#define LCD_REG_55 0x37 +#define LCD_REG_56 0x38 +#define LCD_REG_57 0x39 +#define LCD_REG_58 0x3a +#define LCD_REG_59 0x3b +#define LCD_REG_60 0x3c +#define LCD_REG_61 0x3d +#define LCD_REG_62 0x3e +#define LCD_REG_63 0x3f +#define LCD_REG_64 0x40 +#define LCD_REG_65 0x41 +#define LCD_REG_66 0x42 +#define LCD_REG_67 0x43 +#define LCD_REG_68 0x44 +#define LCD_REG_69 0x45 +#define LCD_REG_70 0x46 +#define LCD_REG_71 0x47 +#define LCD_REG_72 0x48 +#define LCD_REG_73 0x49 +#define LCD_REG_74 0x4a +#define LCD_REG_75 0x4b +#define LCD_REG_76 0x4c +#define LCD_REG_77 0x4d +#define LCD_REG_78 0x4e +#define LCD_REG_79 0x4f +#define LCD_REG_80 0x50 +#define LCD_REG_81 0x51 +#define LCD_REG_82 0x52 +#define LCD_REG_83 0x53 +#define LCD_REG_96 0x60 +#define LCD_REG_97 0x61 +#define LCD_REG_106 0x6a +#define LCD_REG_118 0x76 +#define LCD_REG_128 0x80 +#define LCD_REG_129 0x81 +#define LCD_REG_130 0x82 +#define LCD_REG_131 0x83 +#define LCD_REG_132 0x84 +#define LCD_REG_133 0x85 +#define LCD_REG_134 0x86 +#define LCD_REG_135 0x87 +#define LCD_REG_136 0x88 +#define LCD_REG_137 0x89 +#define LCD_REG_139 0x8b +#define LCD_REG_140 0x8c +#define LCD_REG_141 0x8d +#define LCD_REG_143 0x8f +#define LCD_REG_144 0x90 +#define LCD_REG_145 0x91 +#define LCD_REG_146 0x92 +#define LCD_REG_147 0x93 +#define LCD_REG_148 0x94 +#define LCD_REG_149 0x95 +#define LCD_REG_150 0x96 +#define LCD_REG_151 0x97 +#define LCD_REG_152 0x98 +#define LCD_REG_153 0x99 +#define LCD_REG_154 0x9a +#define LCD_REG_157 0x9d +#define LCD_REG_164 0xa4 +#define LCD_REG_192 0xc0 +#define LCD_REG_193 0xc1 +#define LCD_REG_229 0xe5 + +/* LCD IDs */ + +#define ILI9320_ID 0x9320 +#define ILI9321_ID 0x9321 +#define ILI9325_ID 0x9325 + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/* LCD type */ + +enum lcd_type_e +{ + LCD_TYPE_UNKNOWN = 0, + LCD_TYPE_ILI9320, + LCD_TYPE_ILI9325 +}; + +/* This structure describes the LCD registers */ + +struct lcd_regs_s +{ + volatile uint16_t address; + volatile uint16_t value; +}; + +/* This structure describes the state of this driver */ + +struct stm3220g_dev_s +{ + /* Publicly visible device structure */ + + struct lcd_dev_s dev; + + /* Private LCD-specific information follows */ + + uint8_t type; /* LCD type. See enum lcd_type_e */ + uint8_t power; /* Current power setting */ +}; + +/**************************************************************************** + * Private Function Protototypes + ****************************************************************************/ + +/* Low Level LCD access */ + +static void stm3220g_writereg(uint8_t regaddr, uint16_t regval); +static uint16_t stm3220g_readreg(uint8_t regaddr); +static inline void stm3220g_gramselect(void); +static inline void stm3220g_writegram(uint16_t rgbval); +static void stm3220g_readnosetup(uint16_t *accum); +static uint16_t stm3220g_readnoshift(uint16_t *accum); +static void stm3220g_setcursor(uint16_t col, uint16_t row); + +/* LCD Data Transfer Methods */ + +static int stm3220g_putrun(struct lcd_dev_s *dev, + fb_coord_t row, fb_coord_t col, + const uint8_t *buffer, size_t npixels); +static int stm3220g_getrun(struct lcd_dev_s *dev, + fb_coord_t row, fb_coord_t col, + uint8_t *buffer, size_t npixels); + +/* LCD Configuration */ + +static int stm3220g_getvideoinfo(struct lcd_dev_s *dev, + struct fb_videoinfo_s *vinfo); +static int stm3220g_getplaneinfo(struct lcd_dev_s *dev, + unsigned int planeno, + struct lcd_planeinfo_s *pinfo); + +/* LCD RGB Mapping */ + +#ifdef CONFIG_FB_CMAP +# error "RGB color mapping not supported by this driver" +#endif + +/* Cursor Controls */ + +#ifdef CONFIG_FB_HWCURSOR +# error "Cursor control not supported by this driver" +#endif + +/* LCD Specific Controls */ + +static int stm3220g_getpower(struct lcd_dev_s *dev); +static int stm3220g_setpower(struct lcd_dev_s *dev, int power); +static int stm3220g_getcontrast(struct lcd_dev_s *dev); +static int stm3220g_setcontrast(struct lcd_dev_s *dev, + unsigned int contrast); + +/* Initialization */ + +static inline void stm3220g_lcdinitialize(void); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* This is working memory allocated by the LCD driver for each LCD device + * and for each color plane. This memory will hold one raster line of data. + * The size of the allocated run buffer must therefore be at least + * (bpp * xres / 8). Actual alignment of the buffer must conform to the + * bitwidth of the underlying pixel type. + * + * If there are multiple planes, they may share the same working buffer + * because different planes will not be operate on concurrently. However, + * if there are multiple LCD devices, they must each have unique run buffers. + */ + +static uint16_t g_runbuffer[STM3220G_XRES]; + +/* This structure describes the overall LCD video controller */ + +static const struct fb_videoinfo_s g_videoinfo = +{ + .fmt = STM3220G_COLORFMT, /* Color format: RGB16-565: RRRR RGGG GGGB BBBB */ + .xres = STM3220G_XRES, /* Horizontal resolution in pixel columns */ + .yres = STM3220G_YRES, /* Vertical resolution in pixel rows */ + .nplanes = 1, /* Number of color planes supported */ +}; + +/* This is the standard, NuttX Plane information object */ + +static const struct lcd_planeinfo_s g_planeinfo = +{ + .putrun = stm3220g_putrun, /* Put a run into LCD memory */ + .getrun = stm3220g_getrun, /* Get a run from LCD memory */ + .buffer = (uint8_t *)g_runbuffer, /* Run scratch buffer */ + .bpp = STM3220G_BPP, /* Bits-per-pixel */ +}; + +/* This is the standard, NuttX LCD driver object */ + +static struct stm3220g_dev_s g_lcddev = +{ + .dev = + { + /* LCD Configuration */ + + .getvideoinfo = stm3220g_getvideoinfo, + .getplaneinfo = stm3220g_getplaneinfo, + + /* LCD RGB Mapping -- Not supported */ + + /* Cursor Controls -- Not supported */ + + /* LCD Specific Controls */ + + .getpower = stm3220g_getpower, + .setpower = stm3220g_setpower, + .getcontrast = stm3220g_getcontrast, + .setcontrast = stm3220g_setcontrast, + }, +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm3220g_writereg + * + * Description: + * Write to an LCD register + * + ****************************************************************************/ + +static void stm3220g_writereg(uint8_t regaddr, uint16_t regval) +{ + /* Write the register address then write the register value */ + + LCD->address = regaddr; + LCD->value = regval; +} + +/**************************************************************************** + * Name: stm3220g_readreg + * + * Description: + * Read from an LCD register + * + ****************************************************************************/ + +static uint16_t stm3220g_readreg(uint8_t regaddr) +{ + /* Write the register address then read the register value */ + + LCD->address = regaddr; + return LCD->value; +} + +/**************************************************************************** + * Name: stm3220g_gramselect + * + * Description: + * Setup to read or write multiple pixels to the GRAM memory + * + ****************************************************************************/ + +static inline void stm3220g_gramselect(void) +{ + LCD->address = LCD_REG_34; +} + +/**************************************************************************** + * Name: stm3220g_writegram + * + * Description: + * Write one pixel to the GRAM memory + * + ****************************************************************************/ + +static inline void stm3220g_writegram(uint16_t rgbval) +{ + /* Write the value (GRAM register already selected) */ + + LCD->value = rgbval; +} + +/**************************************************************************** + * Name: stm3220g_readnosetup + * + * Description: + * Prime the operation by reading one pixel from the GRAM memory if + * necessary for this LCD type. When reading 16-bit gram data, there may + * be some shifts in the returned data: + * + * - ILI932x: Discard first dummy read; no shift in the return data + * + ****************************************************************************/ + +static void stm3220g_readnosetup(uint16_t *accum) +{ + /* Read-ahead one pixel */ + + *accum = LCD->value; +} + +/**************************************************************************** + * Name: stm3220g_readnoshift + * + * Description: + * Read one correctly aligned pixel from the GRAM memory. + * Possibly shifting the data and possibly swapping red and green + * components. + * + * - ILI932x: Unknown -- assuming colors are in the color order + * + ****************************************************************************/ + +static uint16_t stm3220g_readnoshift(uint16_t *accum) +{ + /* Read the value (GRAM register already selected) */ + + return LCD->value; +} + +/**************************************************************************** + * Name: stm3220g_setcursor + * + * Description: + * Set the cursor position. In landscape mode, the "column" is actually + * the physical Y position and the "row" is the physical X position. + * + ****************************************************************************/ + +static void stm3220g_setcursor(uint16_t col, uint16_t row) +{ + stm3220g_writereg(LCD_REG_32, row); /* GRAM horizontal address */ + stm3220g_writereg(LCD_REG_33, col); /* GRAM vertical address */ +} + +/**************************************************************************** + * Name: stm3220g_putrun + * + * Description: + * This method can be used to write a partial raster line to the LCD: + * + * dev - The LCD device + * row - Starting row to write to (range: 0 <= row < yres) + * col - Starting column to write to (range: 0 <= col <= xres-npixels) + * buffer - The buffer containing the run to be written to the LCD + * npixels - The number of pixels to write to the LCD + * (range: 0 < npixels <= xres-col) + * + ****************************************************************************/ + +static int stm3220g_putrun(struct lcd_dev_s *dev, + fb_coord_t row, fb_coord_t col, + const uint8_t *buffer, size_t npixels) +{ + const uint16_t *src = (const uint16_t *)buffer; + int i; + + /* Buffer must be provided and aligned to a 16-bit address boundary */ + + lcdinfo("row: %d col: %d npixels: %d\n", row, col, npixels); + DEBUGASSERT(buffer && ((uintptr_t)buffer & 1) == 0); + + /* Write the run to GRAM. */ + +#ifdef CONFIG_LCD_LANDSCAPE + /* Convert coordinates -- Here the edge away from the row of buttons on + * the STM3220G-EVAL is used as the top. + */ + + /* Write the GRAM data, manually incrementing X */ + + for (i = 0; i < npixels; i++) + { + /* Write the next pixel to this position */ + + stm3220g_setcursor(col, row); + stm3220g_gramselect(); + stm3220g_writegram(*src++); + + /* Increment to next column */ + + col++; + } +#elif defined(CONFIG_LCD_RLANDSCAPE) + /* Convert coordinates -- Here the edge next to the row of buttons on + * the STM3220G-EVAL is used as the top. + */ + + col = (STM3220G_XRES - 1) - col; + row = (STM3220G_YRES - 1) - row; + + /* Set the cursor position */ + + stm3220g_setcursor(col, row); + + /* Then write the GRAM data, auto-decrementing X */ + + stm3220g_gramselect(); + for (i = 0; i < npixels; i++) + { + /* Write the next pixel to this position + * (auto-decrements to the next column) + */ + + stm3220g_writegram(*src++); + } +#elif defined(CONFIG_LCD_PORTRAIT) + /* Convert coordinates. + * In this configuration, the top of the display is to the left + * of the buttons (if the board is held so that the buttons are at the + * bottom of the board). + */ + + col = (STM3220G_XRES - 1) - col; + + /* Then write the GRAM data, manually incrementing Y (which is col) */ + + for (i = 0; i < npixels; i++) + { + /* Write the next pixel to this position */ + + stm3220g_setcursor(row, col); + stm3220g_gramselect(); + stm3220g_writegram(*src++); + + /* Increment to next column */ + + col--; + } +#else /* CONFIG_LCD_RPORTRAIT */ + /* Convert coordinates. + * In this configuration, the top of the display is to the right of the + * buttons (if the board is held so that the buttons are at the bottom of + * the board). + */ + + row = (STM3220G_YRES - 1) - row; + + /* Then write the GRAM data, manually incrementing Y (which is col) */ + + for (i = 0; i < npixels; i++) + { + /* Write the next pixel to this position */ + + stm3220g_setcursor(row, col); + stm3220g_gramselect(); + stm3220g_writegram(*src++); + + /* Decrement to next column */ + + col++; + } +#endif + + return OK; +} + +/**************************************************************************** + * Name: stm3220g_getrun + * + * Description: + * This method can be used to read a partial raster line from the LCD: + * + * dev - The LCD device + * row - Starting row to read from (range: 0 <= row < yres) + * col - Starting column to read read (range: 0 <= col <= xres-npixels) + * buffer - The buffer in which to return the run read from the LCD + * npixels - The number of pixels to read from the LCD + * (range: 0 < npixels <= xres-col) + * + ****************************************************************************/ + +static int stm3220g_getrun(struct lcd_dev_s *dev, + fb_coord_t row, fb_coord_t col, + uint8_t *buffer, size_t npixels) +{ + uint16_t *dest = (uint16_t *)buffer; + void (*readsetup)(uint16_t *accum); + uint16_t (*readgram)(uint16_t *accum); + uint16_t accum; + int i; + + /* Buffer must be provided and aligned to a 16-bit address boundary */ + + lcdinfo("row: %d col: %d npixels: %d\n", row, col, npixels); + DEBUGASSERT(buffer && ((uintptr_t)buffer & 1) == 0); + + /* Configure according to the LCD type. + * Kind of silly with only one LCD type. + */ + + switch (g_lcddev.type) + { + case LCD_TYPE_ILI9320: + case LCD_TYPE_ILI9325: + readsetup = stm3220g_readnosetup; + readgram = stm3220g_readnoshift; + break; + + default: /* Shouldn't happen */ + return -ENOSYS; + } + + /* Read the run from GRAM. */ + +#ifdef CONFIG_LCD_LANDSCAPE + /* Convert coordinates -- Here the edge away from the row of buttons on + * the STM3220G-EVAL is used as the top. + */ + + for (i = 0; i < npixels; i++) + { + /* Read the next pixel from this position */ + + stm3220g_setcursor(row, col); + stm3220g_gramselect(); + readsetup(&accum); + *dest++ = readgram(&accum); + + /* Increment to next column */ + + col++; + } +#elif defined(CONFIG_LCD_RLANDSCAPE) + /* Convert coordinates -- Here the edge next to the row of buttons on + * the STM3220G-EVAL is used as the top. + */ + + col = (STM3220G_XRES - 1) - col; + row = (STM3220G_YRES - 1) - row; + + /* Set the cursor position */ + + stm3220g_setcursor(col, row); + + /* Then read the GRAM data, auto-decrementing Y */ + + stm3220g_gramselect(); + + /* Prime the pump for unaligned read data */ + + readsetup(&accum); + + for (i = 0; i < npixels; i++) + { + /* Read the next pixel from this position + * (autoincrements to the next row) + */ + + *dest++ = readgram(&accum); + } +#elif defined(CONFIG_LCD_PORTRAIT) + /* Convert coordinates. + * In this configuration, the top of the display is to the left + * of the buttons (if the board is held so that the buttons are + * at the bottom of the board). + */ + + col = (STM3220G_XRES - 1) - col; + + /* Then read the GRAM data, manually incrementing Y (which is col) */ + + for (i = 0; i < npixels; i++) + { + /* Read the next pixel from this position */ + + stm3220g_setcursor(row, col); + stm3220g_gramselect(); + readsetup(&accum); + *dest++ = readgram(&accum); + + /* Increment to next column */ + + col--; + } +#else /* CONFIG_LCD_RPORTRAIT */ + /* Convert coordinates. + * In this configuration, the top of the display is to the right + * of the buttons (if the board is held so that the buttons are + * at the bottom of the board). + */ + + row = (STM3220G_YRES - 1) - row; + + /* Then write the GRAM data, manually incrementing Y (which is col) */ + + for (i = 0; i < npixels; i++) + { + /* Write the next pixel to this position */ + + stm3220g_setcursor(row, col); + stm3220g_gramselect(); + readsetup(&accum); + *dest++ = readgram(&accum); + + /* Decrement to next column */ + + col++; + } +#endif + + return OK; +} + +/**************************************************************************** + * Name: stm3220g_getvideoinfo + * + * Description: + * Get information about the LCD video controller configuration. + * + ****************************************************************************/ + +static int stm3220g_getvideoinfo(struct lcd_dev_s *dev, + struct fb_videoinfo_s *vinfo) +{ + DEBUGASSERT(dev && vinfo); + lcdinfo("fmt: %d xres: %d yres: %d nplanes: %d\n", + g_videoinfo.fmt, g_videoinfo.xres, + g_videoinfo.yres, g_videoinfo.nplanes); + memcpy(vinfo, &g_videoinfo, sizeof(struct fb_videoinfo_s)); + return OK; +} + +/**************************************************************************** + * Name: stm3220g_getplaneinfo + * + * Description: + * Get information about the configuration of each LCD color plane. + * + ****************************************************************************/ + +static int stm3220g_getplaneinfo(struct lcd_dev_s *dev, + unsigned int planeno, + struct lcd_planeinfo_s *pinfo) +{ + DEBUGASSERT(dev && pinfo && planeno == 0); + lcdinfo("planeno: %d bpp: %d\n", planeno, g_planeinfo.bpp); + memcpy(pinfo, &g_planeinfo, sizeof(struct lcd_planeinfo_s)); + pinfo->dev = dev; + return OK; +} + +/**************************************************************************** + * Name: stm3220g_getpower + * + * Description: + * Get the LCD panel power status + * (0: full off - CONFIG_LCD_MAXPOWER: full on). On backlit LCDs, + * this setting may correspond to the backlight setting. + * + ****************************************************************************/ + +static int stm3220g_getpower(struct lcd_dev_s *dev) +{ + lcdinfo("power: %d\n", 0); + return g_lcddev.power; +} + +/**************************************************************************** + * Name: stm3220g_poweroff + * + * Description: + * Enable/disable LCD panel power + * (0: full off - CONFIG_LCD_MAXPOWER: full on). On backlit LCDs, + * this setting may correspond to the backlight setting. + * + ****************************************************************************/ + +static int stm3220g_poweroff(void) +{ + /* Turn the display off */ + + stm3220g_writereg(LCD_REG_7, 0); + + /* Remember the power off state */ + + g_lcddev.power = 0; + return OK; +} + +/**************************************************************************** + * Name: stm3220g_setpower + * + * Description: + * Enable/disable LCD panel power + * (0: full off - CONFIG_LCD_MAXPOWER: full on). On backlit LCDs, + * this setting may correspond to the backlight setting. + * + ****************************************************************************/ + +static int stm3220g_setpower(struct lcd_dev_s *dev, int power) +{ + lcdinfo("power: %d\n", power); + DEBUGASSERT((unsigned)power <= CONFIG_LCD_MAXPOWER); + + /* Set new power level */ + + if (power > 0) + { + /* Then turn the display on */ + +#if !defined(CONFIG_STM32_ILI9320_DISABLE) || !defined(CONFIG_STM32_ILI9325_DISABLE) + stm3220g_writereg(LCD_REG_7, 0x0173); +#endif + g_lcddev.power = power; + } + else + { + /* Turn the display off */ + + stm3220g_poweroff(); + } + + return OK; +} + +/**************************************************************************** + * Name: stm3220g_getcontrast + * + * Description: + * Get the current contrast setting (0-CONFIG_LCD_MAXCONTRAST). + * + ****************************************************************************/ + +static int stm3220g_getcontrast(struct lcd_dev_s *dev) +{ + lcdinfo("Not implemented\n"); + return -ENOSYS; +} + +/**************************************************************************** + * Name: stm3220g_setcontrast + * + * Description: + * Set LCD panel contrast (0-CONFIG_LCD_MAXCONTRAST). + * + ****************************************************************************/ + +static int stm3220g_setcontrast(struct lcd_dev_s *dev, unsigned int contrast) +{ + lcdinfo("contrast: %d\n", contrast); + return -ENOSYS; +} + +/**************************************************************************** + * Name: stm3220g_lcdinitialize + * + * Description: + * Set LCD panel contrast (0-CONFIG_LCD_MAXCONTRAST). + * + ****************************************************************************/ + +static inline void stm3220g_lcdinitialize(void) +{ + uint16_t id; + + /* Check LCD ID */ + + id = stm3220g_readreg(LCD_REG_0); + lcdinfo("LCD ID: %04x\n", id); + + /* Check if the ID is for the STM32_ILI9320 (or ILI9321) or STM32_ILI9325 */ + +#if !defined(CONFIG_STM32_ILI9320_DISABLE) && !defined(CONFIG_STM32_ILI9325_DISABLE) + if (id == ILI9320_ID || id == ILI9321_ID || id == ILI9325_ID) +#elif !defined(CONFIG_STM32_ILI9320_DISABLE) && defined(CONFIG_STM32_ILI9325_DISABLE) + if (id == ILI9320_ID || id == ILI9321_ID) +#else /* if defined(CONFIG_STM32_ILI9320_DISABLE) && !defined(CONFIG_STM32_ILI9325_DISABLE)) */ + if (id == ILI9325_ID) +#endif + { + /* Save the LCD type (not actually used at for anything important) */ + +#if !defined(CONFIG_STM32_ILI9320_DISABLE) +# if !defined(CONFIG_STM32_ILI9325_DISABLE) + if (id == ILI9325_ID) + { + g_lcddev.type = LCD_TYPE_ILI9325; + } + else +# endif + { + g_lcddev.type = LCD_TYPE_ILI9320; + stm3220g_writereg(LCD_REG_229, 0x8000); /* Set the internal vcore voltage */ + } +#else /* if !defined(CONFIG_STM32_ILI9325_DISABLE) */ + g_lcddev.type = LCD_TYPE_ILI9325; +#endif + lcdinfo("LCD type: %d\n", g_lcddev.type); + + /* Start Initial Sequence */ + + stm3220g_writereg(LCD_REG_0, 0x0001); /* Start internal OSC. */ + stm3220g_writereg(LCD_REG_1, 0x0100); /* Set SS and SM bit */ + stm3220g_writereg(LCD_REG_2, 0x0700); /* Set 1 line inversion */ + stm3220g_writereg(LCD_REG_3, 0x1030); /* Set GRAM write direction and BGR=1. */ + + /* stm3220g_writereg(LCD_REG_3, 0x1018); + * Set GRAM write direction and BGR=1. + */ + + stm3220g_writereg(LCD_REG_4, 0x0000); /* Resize register */ + stm3220g_writereg(LCD_REG_8, 0x0202); /* Set the back porch and front porch */ + stm3220g_writereg(LCD_REG_9, 0x0000); /* Set non-display area refresh cycle ISC[3:0] */ + stm3220g_writereg(LCD_REG_10, 0x0000); /* FMARK function */ + stm3220g_writereg(LCD_REG_12, 0x0000); /* RGB interface setting */ + stm3220g_writereg(LCD_REG_13, 0x0000); /* Frame marker Position */ + stm3220g_writereg(LCD_REG_15, 0x0000); /* RGB interface polarity */ + + /* Power On sequence */ + + stm3220g_writereg(LCD_REG_16, 0x0000); /* SAP, BT[3:0], AP, DSTB, SLP, STB */ + stm3220g_writereg(LCD_REG_17, 0x0000); /* DC1[2:0], DC0[2:0], VC[2:0] */ + stm3220g_writereg(LCD_REG_18, 0x0000); /* VREG1OUT voltage */ + stm3220g_writereg(LCD_REG_19, 0x0000); /* VDV[4:0] for VCOM amplitude */ + up_mdelay(200); /* Dis-charge capacitor power voltage (200ms) */ + + stm3220g_writereg(LCD_REG_16, 0x17b0); /* SAP, BT[3:0], AP, DSTB, SLP, STB */ + stm3220g_writereg(LCD_REG_17, 0x0137); /* DC1[2:0], DC0[2:0], VC[2:0] */ + up_mdelay(50); + + stm3220g_writereg(LCD_REG_18, 0x0139); /* VREG1OUT voltage */ + up_mdelay(50); + + stm3220g_writereg(LCD_REG_19, 0x1d00); /* VDV[4:0] for VCOM amplitude */ + stm3220g_writereg(LCD_REG_41, 0x0013); /* VCM[4:0] for VCOMH */ + up_mdelay(50); + + stm3220g_writereg(LCD_REG_32, 0x0000); /* GRAM horizontal Address */ + stm3220g_writereg(LCD_REG_33, 0x0000); /* GRAM Vertical Address */ + + /* Adjust the Gamma Curve (ILI9320/1) */ + +#if !defined(CONFIG_STM32_ILI9320_DISABLE) +# if !defined(CONFIG_STM32_ILI9325_DISABLE) + if (g_lcddev.type == LCD_TYPE_ILI9320) +# endif + { + stm3220g_writereg(LCD_REG_48, 0x0006); + stm3220g_writereg(LCD_REG_49, 0x0101); + stm3220g_writereg(LCD_REG_50, 0x0003); + stm3220g_writereg(LCD_REG_53, 0x0106); + stm3220g_writereg(LCD_REG_54, 0x0b02); + stm3220g_writereg(LCD_REG_55, 0x0302); + stm3220g_writereg(LCD_REG_56, 0x0707); + stm3220g_writereg(LCD_REG_57, 0x0007); + stm3220g_writereg(LCD_REG_60, 0x0600); + stm3220g_writereg(LCD_REG_61, 0x020b); + } +#endif + + /* Adjust the Gamma Curve (ILI9325) */ + +#if !defined(CONFIG_STM32_ILI9325_DISABLE) +# if !defined(CONFIG_STM32_ILI9320_DISABLE) + else +# endif + { + stm3220g_writereg(LCD_REG_48, 0x0007); + stm3220g_writereg(LCD_REG_49, 0x0302); + stm3220g_writereg(LCD_REG_50, 0x0105); + stm3220g_writereg(LCD_REG_53, 0x0206); + stm3220g_writereg(LCD_REG_54, 0x0808); + stm3220g_writereg(LCD_REG_55, 0x0206); + stm3220g_writereg(LCD_REG_56, 0x0504); + stm3220g_writereg(LCD_REG_57, 0x0007); + stm3220g_writereg(LCD_REG_60, 0x0105); + stm3220g_writereg(LCD_REG_61, 0x0808); + } +#endif + + /* Set GRAM area */ + + stm3220g_writereg(LCD_REG_80, 0x0000); /* Horizontal GRAM Start Address */ + stm3220g_writereg(LCD_REG_81, 0x00ef); /* Horizontal GRAM End Address */ + stm3220g_writereg(LCD_REG_82, 0x0000); /* Vertical GRAM Start Address */ + stm3220g_writereg(LCD_REG_83, 0x013f); /* Vertical GRAM End Address */ + stm3220g_writereg(LCD_REG_96, 0x2700); /* Gate Scan Line */ + + /* stm3220g_writereg(LCD_REG_96, 0xa700); + * Gate Scan Line(GS=1, scan direction is G320~G1) + */ + + stm3220g_writereg(LCD_REG_97, 0x0001); /* NDL,VLE, REV */ + stm3220g_writereg(LCD_REG_106, 0x0000); /* Set scrolling line */ + + /* Partial Display Control */ + + stm3220g_writereg(LCD_REG_128, 0x0000); + stm3220g_writereg(LCD_REG_129, 0x0000); + stm3220g_writereg(LCD_REG_130, 0x0000); + stm3220g_writereg(LCD_REG_131, 0x0000); + stm3220g_writereg(LCD_REG_132, 0x0000); + stm3220g_writereg(LCD_REG_133, 0x0000); + + /* Panel Control */ + + stm3220g_writereg(LCD_REG_144, 0x0010); + stm3220g_writereg(LCD_REG_146, 0x0000); + stm3220g_writereg(LCD_REG_147, 0x0003); + stm3220g_writereg(LCD_REG_149, 0x0110); + stm3220g_writereg(LCD_REG_151, 0x0000); + stm3220g_writereg(LCD_REG_152, 0x0000); + + /* Set GRAM write direction and BGR = 1 + * + * I/D=01 (Horizontal : increment, Vertical : decrement) + * AM=1 (address is updated in vertical writing direction) + */ + + stm3220g_writereg(LCD_REG_3, 0x1018); + stm3220g_writereg(LCD_REG_7, 0); /* Display off */ + } + else + { + lcderr("ERROR: Unsupported LCD type\n"); + } +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_lcd_initialize + * + * Description: + * Initialize the LCD video hardware. + * The initial state of the LCD is fully initialized, display memory + * cleared, and the LCD ready to use, but with the power setting at 0 + * (full off). + * + ****************************************************************************/ + +int board_lcd_initialize(void) +{ + lcdinfo("Initializing\n"); + + /* Configure GPIO pins and configure the FSMC to support the LCD */ + + stm32_selectlcd(); + + /* Configure and enable LCD */ + + up_mdelay(50); + stm3220g_lcdinitialize(); + + /* Clear the display (setting it to the color 0=black) */ + + stm3220g_lcdclear(0); + + /* Turn the display off */ + + stm3220g_poweroff(); + return OK; +} + +/**************************************************************************** + * Name: board_lcd_getdev + * + * Description: + * Return a a reference to the LCD object for the specified LCD. + * This allows support for multiple LCD devices. + * + ****************************************************************************/ + +struct lcd_dev_s *board_lcd_getdev(int lcddev) +{ + DEBUGASSERT(lcddev == 0); + return &g_lcddev.dev; +} + +/**************************************************************************** + * Name: board_lcd_uninitialize + * + * Description: + * Uninitialize the LCD support + * + ****************************************************************************/ + +void board_lcd_uninitialize(void) +{ + stm3220g_poweroff(); + stm32_deselectlcd(); +} + +/**************************************************************************** + * Name: stm3220g_lcdclear + * + * Description: + * This is a non-standard LCD interface just for the stm3220g-EVAL board. + * Because of the various rotations, clearing the display in the normal + * way by writing a sequences of runs that covers the entire display can + * be very slow. Here the display is cleared by simply setting all GRAM + * memory to the specified color. + * + ****************************************************************************/ + +void stm3220g_lcdclear(uint16_t color) +{ + uint32_t i = 0; + + stm3220g_setcursor(0, STM3220G_XRES - 1); + stm3220g_gramselect(); + for (i = 0; i < STM3220G_XRES * STM3220G_YRES; i++) + { + LCD->value = color; + } +} + +#endif /* !CONFIG_STM32_ILI9320_DISABLE || !CONFIG_STM32_ILI9325_DISABLE */ diff --git a/boards/arm/stm32f2/stm3220g-eval/src/stm32_pwm.c b/boards/arm/stm32f2/stm3220g-eval/src/stm32_pwm.c new file mode 100644 index 0000000000000..55325a9f41d31 --- /dev/null +++ b/boards/arm/stm32f2/stm3220g-eval/src/stm32_pwm.c @@ -0,0 +1,105 @@ +/**************************************************************************** + * boards/arm/stm32f2/stm3220g-eval/src/stm32_pwm.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include + +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32_pwm.h" +#include "stm3220g-eval.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* PWM + * + * The STM3220G-Eval has no real on-board PWM devices, but the board can be + * configured to output a pulse train using variously unused pins on the + * board for PWM output (see board.h for details of pins). + */ + +#ifdef CONFIG_PWM + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_pwm_setup + * + * Description: + * Initialize PWM and register the PWM device. + * + ****************************************************************************/ + +int stm32_pwm_setup(void) +{ + static bool initialized = false; + struct pwm_lowerhalf_s *pwm; + int ret; + + /* Have we already initialized? */ + + if (!initialized) + { + /* Call stm32_pwminitialize() to get an instance of the PWM interface */ + + pwm = stm32_pwminitialize(STM3220G_EVAL_PWMTIMER); + if (!pwm) + { + aerr("ERROR: Failed to get the STM32 PWM lower half\n"); + return -ENODEV; + } + + /* Register the PWM driver at "/dev/pwm0" */ + + ret = pwm_register("/dev/pwm0", pwm); + if (ret < 0) + { + aerr("ERROR: pwm_register failed: %d\n", ret); + return ret; + } + + /* Now we are initialized */ + + initialized = true; + } + + return OK; +} + +#endif /* CONFIG_PWM */ diff --git a/boards/arm/stm32f2/stm3220g-eval/src/stm32_selectlcd.c b/boards/arm/stm32f2/stm3220g-eval/src/stm32_selectlcd.c new file mode 100644 index 0000000000000..9931766925263 --- /dev/null +++ b/boards/arm/stm32f2/stm3220g-eval/src/stm32_selectlcd.c @@ -0,0 +1,155 @@ +/**************************************************************************** + * boards/arm/stm32f2/stm3220g-eval/src/stm32_selectlcd.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32.h" +#include +#include "stm3220g-eval.h" + +#ifdef CONFIG_STM32_FSMC + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#if STM32_NGPIO_PORTS < 6 +# error "Required GPIO ports not enabled" +#endif + +/* SRAM pin definitions */ + +#define LCD_NADDRLINES 1 +#define LCD_NDATALINES 16 + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* Pin Usage (per schematic) + * SRAM LCD + * D[0..15] [0..15] [0..15] + * A[0..25] [0..22] [0] RS + * FSMC_NBL0 PE0 OUT --- --- + * FSMC_NBL1 PE1 OUT --- --- + * FSMC_NE2 PG9 OUT --- --- + * FSMC_NE3 PG10 OUT --- ~CS + * FSMC_NE4 PG12 OUT --- --- + * FSMC_NWE PD5 OUT --- ~WR/SCL + * FSMC_NOE PD4 OUT --- ~RD + * FSMC_NWAIT PD6 IN --- --- + * FSMC_INT2 PG6* IN --- --- + * FSMC_INT3 + * FSMC_INTR + * FSMC_CD + * FSMC_CLK + * FSMC_NCE2 + * FSMC_NCE3 + * FSMC_NCE4_1 + * FSMC_NCE4_2 + * FSMC_NIORD + * FSMC_NIOWR + * FSMC_NL + * FSMC_NREG + */ + +/* GPIO configurations unique to the LCD */ + +static const uint32_t g_lcdconfig[] = +{ + /* NOE, NWE, and NE3 */ + + GPIO_FSMC_NOE, GPIO_FSMC_NWE, GPIO_FSMC_NE3 +}; +#define NLCD_CONFIG (sizeof(g_lcdconfig)/sizeof(uint32_t)) + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_selectlcd + * + * Description: + * Initialize to the LCD + * + ****************************************************************************/ + +void stm32_selectlcd(void) +{ + /* Configure new GPIO pins */ + + stm32_extmemaddr(LCD_NADDRLINES); /* Common address lines: A0 */ + stm32_extmemdata(LCD_NDATALINES); /* Common data lines: D0-D15 */ + stm32_extmemgpios(g_lcdconfig, NLCD_CONFIG); /* LCD-specific control lines */ + + /* Enable AHB clocking to the FSMC */ + + stm32_fsmc_enable(); + + /* Color LCD configuration (LCD configured as follow): + * + * - Data/Address MUX = Disable "FSMC_BCR_MUXEN" just not enable it. + * - Extended Mode = Disable "FSMC_BCR_EXTMOD" + * - Memory Type = SRAM "FSMC_BCR_SRAM" + * - Data Width = 16bit "FSMC_BCR_MWID16" + * - Write Operation = Enable "FSMC_BCR_WREN" + * - Asynchronous Wait = Disable + */ + + /* Bank3 NOR/SRAM control register configuration */ + + putreg32(FSMC_BCR_SRAM | FSMC_BCR_MWID16 | FSMC_BCR_WREN, STM32_FSMC_BCR3); + + /* Bank3 NOR/SRAM timing register configuration */ + + putreg32(FSMC_BTR_ADDSET(5) | FSMC_BTR_ADDHLD(1) | + FSMC_BTR_DATAST(9) | FSMC_BTR_BUSTURN(1) | + FSMC_BTR_CLKDIV(1) | FSMC_BTR_DATLAT(2) | + FSMC_BTR_ACCMODA, STM32_FSMC_BTR3); + + putreg32(0xffffffff, STM32_FSMC_BWTR3); + + /* Enable the bank by setting the MBKEN bit */ + + putreg32(FSMC_BCR_MBKEN | FSMC_BCR_SRAM | + FSMC_BCR_MWID16 | FSMC_BCR_WREN, STM32_FSMC_BCR3); +} + +#endif /* CONFIG_STM32_FSMC */ diff --git a/boards/arm/stm32f2/stm3220g-eval/src/stm32_selectsram.c b/boards/arm/stm32f2/stm3220g-eval/src/stm32_selectsram.c new file mode 100644 index 0000000000000..3a0016a1a4947 --- /dev/null +++ b/boards/arm/stm32f2/stm3220g-eval/src/stm32_selectsram.c @@ -0,0 +1,186 @@ +/**************************************************************************** + * boards/arm/stm32f2/stm3220g-eval/src/stm32_selectsram.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32.h" +#include +#include "stm3220g-eval.h" + +#ifdef CONFIG_STM32_FSMC + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#if STM32_NGPIO_PORTS < 6 +# error "Required GPIO ports not enabled" +#endif + +/* SRAM Timing */ + +#define SRAM_ADDRESS_SETUP_TIME 3 +#define SRAM_ADDRESS_HOLD_TIME 1 +#define SRAM_DATA_SETUP_TIME 6 +#define SRAM_BUS_TURNAROUND_DURATION 1 +#define SRAM_CLK_DIVISION 1 +#define SRAM_DATA_LATENCY 2 + +/* SRAM pin definitions */ + +#define SRAM_NADDRLINES 21 +#define SRAM_NDATALINES 16 + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* GPIOs Configuration ****************************************************** + * PD0 <-> FSMC_D2 PE0 <-> FSMC_NBL0 PF0 <-> FSMC_A0 PG0 <-> FSMC_A10 + * PD1 <-> FSMC_D3 PE1 <-> FSMC_NBL1 PF1 <-> FSMC_A1 PG1 <-> FSMC_A11 + * PD4 <-> FSMC_NOE PE3 <-> FSMC_A19 PF2 <-> FSMC_A2 PG2 <-> FSMC_A12 + * PD5 <-> FSMC_NWE PE4 <-> FSMC_A20 PF3 <-> FSMC_A3 PG3 <-> FSMC_A13 + * PD8 <-> FSMC_D13 PE7 <-> FSMC_D4 PF4 <-> FSMC_A4 PG4 <-> FSMC_A14 + * PD9 <-> FSMC_D14 PE8 <-> FSMC_D5 PF5 <-> FSMC_A5 PG5 <-> FSMC_A15 + * PD10 <-> FSMC_D15 PE9 <-> FSMC_D6 PF12 <-> FSMC_A6 PG9 <-> FSMC_NE2 + * PD11 <-> FSMC_A16 PE10 <-> FSMC_D7 PF13 <-> FSMC_A7 + * PD12 <-> FSMC_A17 PE11 <-> FSMC_D8 PF14 <-> FSMC_A8 + * PD13 <-> FSMC_A18 PE12 <-> FSMC_D9 PF15 <-> FSMC_A9 + * PD14 <-> FSMC_D0 PE13 <-> FSMC_D10 + * PD15 <-> FSMC_D1 PE14 <-> FSMC_D11 + * PE15 <-> FSMC_D12 + */ + +/* GPIO configurations unique to SRAM */ + +static const uint32_t g_sramconfig[] = +{ + /* NE3, NBL0, NBL1, */ + + GPIO_FSMC_NOE, GPIO_FSMC_NWE, GPIO_FSMC_NBL0, GPIO_FSMC_NBL1, GPIO_FSMC_NE2 +}; +#define NSRAM_CONFIG (sizeof(g_sramconfig)/sizeof(uint32_t)) + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_selectsram + * + * Description: + * Initialize to access external SRAM. SRAM will be visible at the FSMC + * Bank NOR/SRAM2 base address (0x64000000) + * + * General transaction rules. The requested AHB transaction data size can + * be 8-, 16- or 32-bit wide whereas the SRAM has a fixed 16-bit data + * width. Some simple transaction rules must be followed: + * + * Case 1: AHB transaction width and SRAM data width are equal + * There is no issue in this case. + * Case 2: AHB transaction size is greater than the memory size + * In this case, the FSMC splits the AHB transaction into smaller + * consecutive memory accesses in order to meet the external data width. + * Case 3: AHB transaction size is smaller than the memory size. + * SRAM supports the byte select feature. + * a) FSMC allows write transactions accessing the right data through its + * byte lanes (NBL[1:0]) + * b) Read transactions are allowed (the controller reads the entire + * memory word and uses the needed byte only). The NBL[1:0] are always + * kept low during read transactions. + * + ****************************************************************************/ + +void stm32_selectsram(void) +{ + /* Configure new GPIO pins */ + + stm32_extmemaddr(SRAM_NADDRLINES); /* Common address lines: A0-A20 */ + stm32_extmemdata(SRAM_NDATALINES); /* Common data lines: D0-D15 */ + stm32_extmemgpios(g_sramconfig, NSRAM_CONFIG); /* SRAM-specific control lines */ + + /* Enable AHB clocking to the FSMC */ + + stm32_fsmc_enable(); + + /* Bank1 NOR/SRAM control register configuration + * + * Bank enable : Not yet + * Data address mux : Disabled + * Memory Type : PSRAM + * Data bus width : 16-bits + * Flash access : Disabled + * Burst access mode : Disabled + * Polarity : Low + * Wrapped burst mode : Disabled + * Write timing : Before state + * Write enable : Yes + * Wait signal : Disabled + * Extended mode : Disabled + * Asynchronous wait : Disabled + * Write burst : Disabled + */ + + putreg32((FSMC_BCR_PSRAM | FSMC_BCR_MWID16 | + FSMC_BCR_WREN), STM32_FSMC_BCR2); + + /* Bank1 NOR/SRAM timing register configuration */ + + putreg32((FSMC_BTR_ADDSET(SRAM_ADDRESS_SETUP_TIME) | + FSMC_BTR_ADDHLD(SRAM_ADDRESS_HOLD_TIME) | + FSMC_BTR_DATAST(SRAM_DATA_SETUP_TIME) | + FSMC_BTR_BUSTURN(SRAM_BUS_TURNAROUND_DURATION) | + FSMC_BTR_CLKDIV(SRAM_CLK_DIVISION) | + FSMC_BTR_DATLAT(SRAM_DATA_LATENCY) | + FSMC_BTR_ACCMODA), + STM32_FSMC_BTR2); + + /* Bank1 NOR/SRAM timing register for write configuration, + * if extended mode is used + */ + + putreg32(0xffffffff, STM32_FSMC_BWTR2); /* Extended mode not used */ + + /* Enable the bank */ + + putreg32((FSMC_BCR_MBKEN | FSMC_BCR_PSRAM | + FSMC_BCR_MWID16 | FSMC_BCR_WREN), STM32_FSMC_BCR2); +} + +#endif /* CONFIG_STM32_FSMC */ diff --git a/boards/arm/stm32f2/stm3220g-eval/src/stm32_spi.c b/boards/arm/stm32f2/stm3220g-eval/src/stm32_spi.c new file mode 100644 index 0000000000000..c766ed8ca4424 --- /dev/null +++ b/boards/arm/stm32f2/stm3220g-eval/src/stm32_spi.c @@ -0,0 +1,130 @@ +/**************************************************************************** + * boards/arm/stm32f2/stm3220g-eval/src/stm32_spi.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "arm_internal.h" +#include "chip.h" +#include "stm32.h" +#include "stm3220g-eval.h" + +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || defined(CONFIG_STM32_SPI3) + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_spidev_initialize + * + * Description: + * Called to configure SPI chip select GPIO pins for the STM3220G-EVAL + * board. + * + ****************************************************************************/ + +void weak_function stm32_spidev_initialize(void) +{ +#warning "Missing logic" +} + +/**************************************************************************** + * Name: stm32_spi1/2/3select and stm32_spi1/2/3status + * + * Description: + * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status + * must be provided by board-specific logic. They are implementations of + * the select and status methods of the SPI interface defined by struct + * spi_ops_s (see include/nuttx/spi/spi.h). All other methods + * (including stm32_spibus_initialize()) are provided by common STM32 + * logic. + * To use this common SPI logic on your board: + * + * 1. Provide logic in stm32_boardinitialize() to configure SPI chip select + * pins. + * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() functions + * in your board-specific logic. These functions will perform chip + * selection and status operations using GPIOs in the way your board is + * configured. + * 3. Add a calls to stm32_spibus_initialize() in your low level + * application initialization logic + * 4. The handle returned by stm32_spibus_initialize() may then be used to + * bind the SPI driver to higher level logic (e.g., calling + * mmcsd_spislotinitialize(), for example, will bind the SPI driver to + * the SPI MMC/SD driver). + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_SPI1 +void stm32_spi1select(struct spi_dev_s *dev, + uint32_t devid, bool selected) +{ + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); +} + +uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) +{ + return SPI_STATUS_PRESENT; +} +#endif + +#ifdef CONFIG_STM32_SPI2 +void stm32_spi2select(struct spi_dev_s *dev, + uint32_t devid, bool selected) +{ + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); +} + +uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) +{ + return SPI_STATUS_PRESENT; +} +#endif + +#ifdef CONFIG_STM32_SPI3 +void stm32_spi3select(struct spi_dev_s *dev, + uint32_t devid, bool selected) +{ + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); +} + +uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid) +{ + return SPI_STATUS_PRESENT; +} +#endif + +#endif /* CONFIG_STM32_SPI1 || CONFIG_STM32_SPI2 */ diff --git a/boards/arm/stm32f2/stm3220g-eval/src/stm32_stmpe811.c b/boards/arm/stm32f2/stm3220g-eval/src/stm32_stmpe811.c new file mode 100644 index 0000000000000..4b37d489a8eab --- /dev/null +++ b/boards/arm/stm32f2/stm3220g-eval/src/stm32_stmpe811.c @@ -0,0 +1,337 @@ +/**************************************************************************** + * boards/arm/stm32f2/stm3220g-eval/src/stm32_stmpe811.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include + +#include "stm32.h" +#include "stm3220g-eval.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +#ifdef CONFIG_INPUT_STMPE811 +#ifndef CONFIG_INPUT +# error "STMPE811 support requires CONFIG_INPUT" +#endif + +#ifndef CONFIG_STM32_I2C1 +# error "STMPE811 support requires CONFIG_STM32_I2C1" +#endif + +#ifndef CONFIG_STMPE811_I2C +# error "Only the STMPE811 I2C interface is supported" +#endif + +#ifdef CONFIG_STMPE811_SPI +# error "Only the STMPE811 SPI interface is supported" +#endif + +#ifndef CONFIG_STMPE811_FREQUENCY +# define CONFIG_STMPE811_FREQUENCY 100000 +#endif + +#ifndef CONFIG_STMPE811_I2CDEV +# define CONFIG_STMPE811_I2CDEV 1 +#endif + +#if CONFIG_STMPE811_I2CDEV != 1 +# error "CONFIG_STMPE811_I2CDEV must be one" +#endif + +#ifndef CONFIG_STMPE811_DEVMINOR +# define CONFIG_STMPE811_DEVMINOR 0 +#endif + +/* Board definitions ********************************************************/ + +/* The STM3220G-EVAL has two STMPE811QTR I/O expanders on board both + * connected to the STM32 via I2C1. They share a common interrupt line: PI2. + * + * STMPE811 U24, I2C address 0x41 (7-bit) + * ------ ---- ---------------- -------------------------------------------- + * STPE11 PIN BOARD SIGNAL BOARD CONNECTION + * ------ ---- ---------------- -------------------------------------------- + * Y- TouchScreen_Y- LCD Connector XL + * X- TouchScreen_X- LCD Connector XR + * Y+ TouchScreen_Y+ LCD Connector XD + * X+ TouchScreen_X+ LCD Connector XU + * IN3 EXP_IO9 + * IN2 EXP_IO10 + * IN1 EXP_IO11 + * IN0 EXP_IO12 + * + * STMPE811 U29, I2C address 0x44 (7-bit) + * ------ ---- ---------------- -------------------------------------------- + * STPE11 PIN BOARD SIGNAL BOARD CONNECTION + * ------ ---- ---------------- -------------------------------------------- + * Y- EXP_IO1 + * X- EXP_IO2 + * Y+ EXP_IO3 + * X+ EXP_IO4 + * IN3 EXP_IO5 + * IN2 EXP_IO6 + * IN1 EXP_IO7 + * IN0 EXP_IO8 + */ + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +struct stm32_stmpe811config_s +{ + /* Configuration structure as seen by the STMPE811 driver */ + + struct stmpe811_config_s config; + + /* Additional private definitions only known to this driver */ + + STMPE811_HANDLE handle; /* The STMPE811 driver handle */ + xcpt_t handler; /* The STMPE811 interrupt handler */ + void *arg; /* Interrupt handler argument */ +}; + +/**************************************************************************** + * Static Function Prototypes + ****************************************************************************/ + +/* IRQ/GPIO access callbacks. These operations all hidden behind callbacks + * to isolate the STMPE811 driver from differences in GPIO + * interrupt handling by varying boards and MCUs.* so that contact and loss- + * of-contact events can be detected. + * + * attach - Attach the STMPE811 interrupt handler to the GPIO interrupt + * enable - Enable or disable the GPIO interrupt + * clear - Acknowledge/clear any pending GPIO interrupt + */ + +static int stmpe811_attach(struct stmpe811_config_s *state, xcpt_t isr, + void *arg); +static void stmpe811_enable(struct stmpe811_config_s *state, + bool enable); +static void stmpe811_clear(struct stmpe811_config_s *state); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* A reference to a structure of this type must be passed to the STMPE811 + * driver. This structure provides information about the configuration + * of the STMPE811 and provides some board-specific hooks. + * + * Memory for this structure is provided by the caller. It is not copied + * by the driver and is presumed to persist while the driver is active. The + * memory must be writable because, under certain circumstances, the driver + * may modify frequency or X plate resistance values. + */ + +#ifndef CONFIG_STMPE811_TSC_DISABLE +static struct stm32_stmpe811config_s g_stmpe811config = +{ + .config = + { +#ifdef CONFIG_STMPE811_I2C + .address = STMPE811_ADDR1, +#endif + .frequency = CONFIG_STMPE811_FREQUENCY, + +#ifdef CONFIG_STMPE811_MULTIPLE + .irq = STM32_IRQ_EXTI2, +#endif + .ctrl1 = (ADC_CTRL1_SAMPLE_TIME_80 | ADC_CTRL1_MOD_12B), + .ctrl2 = ADC_CTRL2_ADC_FREQ_3p25, + + .attach = stmpe811_attach, + .enable = stmpe811_enable, + .clear = stmpe811_clear, + }, + .handler = NULL, + .arg = NULL, +}; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/* IRQ/GPIO access callbacks. These operations all hidden behind + * callbacks to isolate the STMPE811 driver from differences in GPIO + * interrupt handling by varying boards and MCUs. + * + * attach - Attach the STMPE811 interrupt handler to the GPIO interrupt + * enable - Enable or disable the GPIO interrupt + * clear - Acknowledge/clear any pending GPIO interrupt + */ + +static int stmpe811_attach(struct stmpe811_config_s *state, xcpt_t isr, + void *arg) +{ + struct stm32_stmpe811config_s *priv = + (struct stm32_stmpe811config_s *)state; + + iinfo("Saving handler %p\n", isr); + DEBUGASSERT(priv); + + /* Just save the handler. We will use it when EXTI interruptsare enabled */ + + priv->handler = isr; + priv->arg = arg; + return OK; +} + +static void stmpe811_enable(struct stmpe811_config_s *state, bool enable) +{ + struct stm32_stmpe811config_s *priv = + (struct stm32_stmpe811config_s *)state; + irqstate_t flags; + + /* Attach and enable, or detach and disable. Enabling and disabling GPIO + * interrupts is a multi-step process so the safest thing is to keep + * interrupts disabled during the reconfiguration. + */ + + flags = enter_critical_section(); + if (enable) + { + /* Configure the EXTI interrupt using the SAVED handler */ + + stm32_gpiosetevent(GPIO_IO_EXPANDER, true, true, true, + priv->handler, priv->arg); + } + else + { + /* Configure the EXTI interrupt with a NULL handler to disable it */ + + stm32_gpiosetevent(GPIO_IO_EXPANDER, false, false, false, + NULL, NULL); + } + + leave_critical_section(flags); +} + +static void stmpe811_clear(struct stmpe811_config_s *state) +{ + /* Does nothing */ +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_tsc_setup + * + * Description: + * This function is called by board-bringup logic to configure the + * touchscreen device. This function will register the driver as + * /dev/inputN where N is the minor device number. + * + * Input Parameters: + * minor - The input device minor number + * + * Returned Value: + * Zero is returned on success. Otherwise, a negated errno value is + * returned to indicate the nature of the failure. + * + ****************************************************************************/ + +int stm32_tsc_setup(int minor) +{ +#ifndef CONFIG_STMPE811_TSC_DISABLE + struct i2c_master_s *dev; + int ret; + + iinfo("minor %d\n", minor); + DEBUGASSERT(minor == 0); + + /* Check if we are already initialized */ + + if (!g_stmpe811config.handle) + { + iinfo("Initializing\n"); + + /* Configure the STMPE811 interrupt pin as an input */ + + stm32_configgpio(GPIO_IO_EXPANDER); + + /* Get an instance of the I2C interface */ + + dev = stm32_i2cbus_initialize(CONFIG_STMPE811_I2CDEV); + if (!dev) + { + ierr("ERROR: Failed to initialize I2C bus %d\n", + CONFIG_STMPE811_I2CDEV); + return -ENODEV; + } + + /* Instantiate the STMPE811 driver */ + + g_stmpe811config.handle = + stmpe811_instantiate(dev, + (struct stmpe811_config_s *)&g_stmpe811config); + if (!g_stmpe811config.handle) + { + ierr("ERROR: Failed to instantiate the STMPE811 driver\n"); + return -ENODEV; + } + + /* Initialize and register the I2C touchscreen device */ + + ret = stmpe811_register(g_stmpe811config.handle, + CONFIG_STMPE811_DEVMINOR); + if (ret < 0) + { + ierr("ERROR: Failed to register STMPE driver: %d\n", ret); + + /* stm32_i2cbus_uninitialize(dev); */ + + return -ENODEV; + } + } + + return OK; +#else + return -ENOSYS; +#endif +} + +#endif /* CONFIG_INPUT_STMPE811 */ diff --git a/boards/arm/stm32f2/stm3220g-eval/src/stm32_usb.c b/boards/arm/stm32f2/stm3220g-eval/src/stm32_usb.c new file mode 100644 index 0000000000000..18abe851b1637 --- /dev/null +++ b/boards/arm/stm32f2/stm3220g-eval/src/stm32_usb.c @@ -0,0 +1,304 @@ +/**************************************************************************** + * boards/arm/stm32f2/stm3220g-eval/src/stm32_usb.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include "arm_internal.h" +#include "stm32.h" +#include "stm32_otgfs.h" +#include "stm3220g-eval.h" + +#ifdef CONFIG_STM32_OTGFS + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#if defined(CONFIG_USBDEV) || defined(CONFIG_USBHOST) +# define HAVE_USB 1 +#else +# warning "CONFIG_STM32_OTGFS is enabled but neither CONFIG_USBDEV nor CONFIG_USBHOST" +# undef HAVE_USB +#endif + +#ifndef CONFIG_USBHOST_DEFPRIO +# define CONFIG_USBHOST_DEFPRIO 50 +#endif + +#ifndef CONFIG_USBHOST_STACKSIZE +# ifdef CONFIG_USBHOST_HUB +# define CONFIG_USBHOST_STACKSIZE 1536 +# else +# define CONFIG_USBHOST_STACKSIZE 1024 +# endif +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +static struct usbhost_connection_s *g_usbconn; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: usbhost_waiter + * + * Description: + * Wait for USB devices to be connected. + * + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +static int usbhost_waiter(int argc, char *argv[]) +{ + struct usbhost_hubport_s *hport; + + uinfo("Running\n"); + for (; ; ) + { + /* Wait for the device to change state */ + + DEBUGVERIFY(CONN_WAIT(g_usbconn, &hport)); + uinfo("%s\n", hport->connected ? "connected" : "disconnected"); + + /* Did we just become connected? */ + + if (hport->connected) + { + /* Yes.. enumerate the newly connected device */ + + CONN_ENUMERATE(g_usbconn, hport); + } + } + + /* Keep the compiler from complaining */ + + return 0; +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_usbinitialize + * + * Description: + * Called from stm32_usbinitialize very early in initialization to setup + * USB-related GPIO pins for the STM3220G-EVAL board. + * + ****************************************************************************/ + +void stm32_usbinitialize(void) +{ +#ifdef HAVE_USB + /* The OTG FS has an internal soft pull-up. + * No GPIO configuration is required + */ + + /* Configure the OTG FS VBUS sensing GPIO, + * Power On, and Overcurrent GPIOs + */ + + stm32_configgpio(GPIO_OTGFS_VBUS); + stm32_configgpio(GPIO_OTGFS_PWRON); + stm32_configgpio(GPIO_OTGFS_OVER); +#endif +} + +/**************************************************************************** + * Name: stm32_usbhost_initialize + * + * Description: + * Called at application startup time to initialize the USB host + * functionality. + * This function will start a thread that will monitor for device + * connection/disconnection events. + * + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +int stm32_usbhost_initialize(void) +{ + int ret; + + /* First, register all of the class drivers needed to support the drivers + * that we care about: + */ + + uinfo("Register class drivers\n"); + +#ifdef CONFIG_USBHOST_MSC + /* Register the USB mass storage class class */ + + ret = usbhost_msc_initialize(); + if (ret != OK) + { + uerr("ERROR: Failed to register the mass storage class: %d\n", ret); + } +#endif + +#ifdef CONFIG_USBHOST_CDCACM + /* Register the CDC/ACM serial class */ + + ret = usbhost_cdcacm_initialize(); + if (ret != OK) + { + uerr("ERROR: Failed to register the CDC/ACM serial class: %d\n", ret); + } +#endif + + /* Then get an instance of the USB host interface */ + + uinfo("Initialize USB host\n"); + g_usbconn = stm32_otgfshost_initialize(0); + if (g_usbconn) + { + /* Start a thread to handle device connection. */ + + uinfo("Start usbhost_waiter\n"); + + ret = kthread_create("usbhost", CONFIG_USBHOST_DEFPRIO, + CONFIG_USBHOST_STACKSIZE, + usbhost_waiter, NULL); + return ret < 0 ? -ENOEXEC : OK; + } + + return -ENODEV; +} +#endif + +/**************************************************************************** + * Name: stm32_usbhost_vbusdrive + * + * Description: + * Enable/disable driving of VBUS 5V output. This function must be + * provided be each platform that implements the STM32 OTG FS host + * interface + * + * "On-chip 5 V VBUS generation is not supported. For this reason, a + * charge pump or, if 5 V are available on the application board, a + * basic power switch, must be added externally to drive the 5 V VBUS + * line. The external charge pump can be driven by any GPIO output. + * When the application decides to power on VBUS using the chosen GPIO, + * it must also set the port power bit in the host port control and + * status register (PPWR bit in OTG_FS_HPRT). + * + * "The application uses this field to control power to this port, + * and the core clears this bit on an overcurrent condition." + * + * Input Parameters: + * iface - For future growth to handle multiple USB host interface. + * Should be zero. + * enable - true: enable VBUS power; false: disable VBUS power + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +void stm32_usbhost_vbusdrive(int iface, bool enable) +{ + DEBUGASSERT(iface == 0); + + if (enable) + { + /* Enable the Power Switch by driving the enable pin low */ + + stm32_gpiowrite(GPIO_OTGFS_PWRON, false); + } + else + { + /* Disable the Power Switch by driving the enable pin high */ + + stm32_gpiowrite(GPIO_OTGFS_PWRON, true); + } +} +#endif + +/**************************************************************************** + * Name: stm32_setup_overcurrent + * + * Description: + * Setup to receive an interrupt-level callback if an overcurrent + * condition is detected. + * + * Input Parameters: + * handler - New overcurrent interrupt handler + * arg - The argument provided for the interrupt handler + * + * Returned Value: + * Zero (OK) is returned on success. Otherwise, a negated errno value + * is returned to indicate the nature of the failure. + * + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +int stm32_setup_overcurrent(xcpt_t handler, void *arg) +{ + return stm32_gpiosetevent(GPIO_OTGFS_OVER, true, true, true, handler, arg); +} +#endif + +/**************************************************************************** + * Name: stm32_usbsuspend + * + * Description: + * Board logic must provide the stm32_usbsuspend logic if the USBDEV + * driver is used. This function is called whenever the USB enters or + * leaves suspend mode. This is an opportunity for the board logic to + * shutdown clocks, power, etc. while the USB is suspended. + * + ****************************************************************************/ + +#ifdef CONFIG_USBDEV +void stm32_usbsuspend(struct usbdev_s *dev, bool resume) +{ + uinfo("resume: %d\n", resume); +} +#endif + +#endif /* CONFIG_STM32_OTGFS */ diff --git a/boards/arm/stm32f2/stm3220g-eval/src/stm32_userleds.c b/boards/arm/stm32f2/stm3220g-eval/src/stm32_userleds.c new file mode 100644 index 0000000000000..c7c5a9f1c708d --- /dev/null +++ b/boards/arm/stm32f2/stm3220g-eval/src/stm32_userleds.c @@ -0,0 +1,96 @@ +/**************************************************************************** + * boards/arm/stm32f2/stm3220g-eval/src/stm32_userleds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32.h" +#include "stm3220g-eval.h" + +#ifndef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* This array maps an LED number to GPIO pin configuration */ + +static uint32_t g_ledcfg[BOARD_NLEDS] = +{ + GPIO_LED1, GPIO_LED2, GPIO_LED3, GPIO_LED4 +}; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_userled_initialize + ****************************************************************************/ + +uint32_t board_userled_initialize(void) +{ + /* Configure LED1-4 GPIOs for output */ + + stm32_configgpio(GPIO_LED1); + stm32_configgpio(GPIO_LED2); + stm32_configgpio(GPIO_LED3); + stm32_configgpio(GPIO_LED4); + return BOARD_NLEDS; +} + +/**************************************************************************** + * Name: board_userled + ****************************************************************************/ + +void board_userled(int led, bool ledon) +{ + if ((unsigned)led < BOARD_NLEDS) + { + stm32_gpiowrite(g_ledcfg[led], ledon); + } +} + +/**************************************************************************** + * Name: board_userled_all + ****************************************************************************/ + +void board_userled_all(uint32_t ledset) +{ + stm32_gpiowrite(GPIO_LED1, (ledset & BOARD_LED1_BIT) == 0); + stm32_gpiowrite(GPIO_LED2, (ledset & BOARD_LED2_BIT) == 0); + stm32_gpiowrite(GPIO_LED3, (ledset & BOARD_LED3_BIT) == 0); + stm32_gpiowrite(GPIO_LED4, (ledset & BOARD_LED4_BIT) == 0); +} + +#endif /* !CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/stm3220g-eval/tools/olimex-arm-usb-ocd.cfg b/boards/arm/stm32f2/stm3220g-eval/tools/olimex-arm-usb-ocd.cfg similarity index 100% rename from boards/arm/stm32/stm3220g-eval/tools/olimex-arm-usb-ocd.cfg rename to boards/arm/stm32f2/stm3220g-eval/tools/olimex-arm-usb-ocd.cfg diff --git a/boards/arm/stm32f2/stm3220g-eval/tools/oocd.sh b/boards/arm/stm32f2/stm3220g-eval/tools/oocd.sh new file mode 100755 index 0000000000000..9d01a7c87563c --- /dev/null +++ b/boards/arm/stm32f2/stm3220g-eval/tools/oocd.sh @@ -0,0 +1,87 @@ +#!/usr/bin/env bash + +# Get command line parameters + +USAGE="USAGE: $0 [-dh] " +ADVICE="Try '$0 -h' for more information" + +while [ ! -z "$1" ]; do + case $1 in + -d ) + set -x + ;; + -h ) + echo "$0 is a tool for generation of proper version files for the NuttX build" + echo "" + echo $USAGE + echo "" + echo "Where:" + echo " -d" + echo " Enable script debug" + echo " -h" + echo " show this help message and exit" + echo " Use the OpenOCD 0.4.0" + echo " " + echo " The full path to the top-level NuttX directory" + exit 0 + ;; + * ) + break; + ;; + esac + shift +done + +TOPDIR=$1 +if [ -z "${TOPDIR}" ]; then + echo "Missing argument" + echo $USAGE + echo $ADVICE + exit 1 +fi + +# This script *probably* only works with the following versions of OpenOCD: + +# Local search directory and configurations + +OPENOCD_SEARCHDIR="${TOPDIR}/boards/arm/stm32f2/stm3220g-eval/tools" +OPENOCD_WSEARCHDIR="`cygpath -w ${OPENOCD_SEARCHDIR}`" + +OPENOCD_PATH="/cygdrive/c/Program Files (x86)/OpenOCD/0.4.0/bin" +OPENOCD_EXE=openocd.exe +OPENOCD_INTERFACE="olimex-arm-usb-ocd.cfg" + +OPENOCD_TARGET="stm32.cfg" +OPENOCD_ARGS="-s ${OPENOCD_WSEARCHDIR} -f ${OPENOCD_INTERFACE} -f ${OPENOCD_TARGET}" + +echo "Trying OpenOCD 0.4.0 path: ${OPENOCD_PATH}/${OPENOCD_EXE}" + +# Verify that everything is what it claims it is and is located where it claims it is. + +if [ ! -x "${OPENOCD_PATH}/${OPENOCD_EXE}" ]; then + echo "OpenOCD executable does not exist: ${OPENOCD_PATH}/${OPENOCD_EXE}" + exit 1 +fi +if [ ! -f "${OPENOCD_SEARCHDIR}/${OPENOCD_TARGET}" ]; then + echo "OpenOCD target config file does not exist: ${OPENOCD_SEARCHDIR}/${OPENOCD_TARGET}" + exit 1 +fi +if [ ! -f "${OPENOCD_SEARCHDIR}/${OPENOCD_INTERFACE}" ]; then + echo "OpenOCD interface config file does not exist: ${OPENOCD_SEARCHDIR}/${OPENOCD_INTERFACE}" + exit 1 +fi + +# Enable debug if so requested + +if [ "X$2" = "X-d" ]; then + OPENOCD_ARGS=$OPENOCD_ARGS" -d3" + set -x +fi + +# Okay... do it! + +echo "Starting OpenOCD" +"${OPENOCD_PATH}/${OPENOCD_EXE}" ${OPENOCD_ARGS} & +echo "OpenOCD daemon started" +ps -ef | grep openocd +echo "In GDB: target remote localhost:3333" diff --git a/boards/arm/stm32/stm3220g-eval/tools/stm32.cfg b/boards/arm/stm32f2/stm3220g-eval/tools/stm32.cfg similarity index 100% rename from boards/arm/stm32/stm3220g-eval/tools/stm32.cfg rename to boards/arm/stm32f2/stm3220g-eval/tools/stm32.cfg diff --git a/boards/arm/stm32/stm3220g-eval/tools/usb-driver.txt b/boards/arm/stm32f2/stm3220g-eval/tools/usb-driver.txt similarity index 100% rename from boards/arm/stm32/stm3220g-eval/tools/usb-driver.txt rename to boards/arm/stm32f2/stm3220g-eval/tools/usb-driver.txt diff --git a/boards/arm/stm32f3/common/CMakeLists.txt b/boards/arm/stm32f3/common/CMakeLists.txt new file mode 100644 index 0000000000000..6d2b8c896bd73 --- /dev/null +++ b/boards/arm/stm32f3/common/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32f3/common/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(${NUTTX_DIR}/boards/arm/common/stm32 stm32_common) diff --git a/boards/arm/stm32f3/common/Kconfig b/boards/arm/stm32f3/common/Kconfig new file mode 100644 index 0000000000000..5c48f62a0258b --- /dev/null +++ b/boards/arm/stm32f3/common/Kconfig @@ -0,0 +1,6 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# + +source "boards/arm/common/stm32/Kconfig" diff --git a/boards/arm/stm32f3/common/Makefile b/boards/arm/stm32f3/common/Makefile new file mode 100644 index 0000000000000..e7a1eed83cc33 --- /dev/null +++ b/boards/arm/stm32f3/common/Makefile @@ -0,0 +1,39 @@ +############################################################################# +# boards/arm/stm32f3/common/Makefile +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################# + +include $(TOPDIR)/Make.defs + +STM32_BOARD_COMMON_DIR := $(TOPDIR)$(DELIM)boards$(DELIM)arm$(DELIM)common$(DELIM)stm32 +STM32_COMMON_SRCDIR := $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)common$(DELIM)stm32 + +include board/Make.defs +include $(STM32_BOARD_COMMON_DIR)$(DELIM)src$(DELIM)Make.defs + +DEPPATH += --dep-path board + +include $(TOPDIR)/boards/Board.mk + +ARCHSRCDIR = $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src +BOARDDIR = $(ARCHSRCDIR)$(DELIM)board +CFLAGS += ${INCDIR_PREFIX}$(BOARDDIR)$(DELIM)include +CFLAGS += ${INCDIR_PREFIX}$(STM32_COMMON_SRCDIR) +CXXFLAGS += ${INCDIR_PREFIX}$(STM32_COMMON_SRCDIR) diff --git a/boards/arm/stm32f3/nucleo-f302r8/CMakeLists.txt b/boards/arm/stm32f3/nucleo-f302r8/CMakeLists.txt new file mode 100644 index 0000000000000..d777a964b1855 --- /dev/null +++ b/boards/arm/stm32f3/nucleo-f302r8/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32f3/nucleo-f302r8/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/arm/stm32/nucleo-f302r8/Kconfig b/boards/arm/stm32f3/nucleo-f302r8/Kconfig similarity index 100% rename from boards/arm/stm32/nucleo-f302r8/Kconfig rename to boards/arm/stm32f3/nucleo-f302r8/Kconfig diff --git a/boards/arm/stm32f3/nucleo-f302r8/configs/can/defconfig b/boards/arm/stm32f3/nucleo-f302r8/configs/can/defconfig new file mode 100644 index 0000000000000..5e2a50cea1ad3 --- /dev/null +++ b/boards/arm/stm32f3/nucleo-f302r8/configs/can/defconfig @@ -0,0 +1,55 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nucleo-f302r8" +CONFIG_ARCH_BOARD_NUCLEO_F302R8=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f3" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F302R8=y +CONFIG_ARCH_CHIP_STM32F3=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_CAN_ERRORS=y +CONFIG_CAN_EXTID=y +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_DEFAULT_SMALL=y +CONFIG_EXAMPLES_CAN=y +CONFIG_EXAMPLES_CAN_WRITE=y +CONFIG_FDCLONE_STDIO=y +CONFIG_FILE_STREAM=y +CONFIG_FS_LARGEFILE=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=1024 +CONFIG_INTELHEX_BINARY=y +CONFIG_NAME_MAX=16 +CONFIG_NSH_ARGCAT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=256 +CONFIG_NSH_QUOTE=y +CONFIG_POSIX_SPAWN_DEFAULT_STACKSIZE=512 +CONFIG_RAM_SIZE=16386 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_STDIO_BUFFER_SIZE=255 +CONFIG_STM32_CAN1=y +CONFIG_STM32_CAN_TSEG1=15 +CONFIG_STM32_CAN_TSEG2=2 +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_PWR=y +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f3/nucleo-f302r8/configs/cansock/defconfig b/boards/arm/stm32f3/nucleo-f302r8/configs/cansock/defconfig new file mode 100644 index 0000000000000..de7101c186d01 --- /dev/null +++ b/boards/arm/stm32f3/nucleo-f302r8/configs/cansock/defconfig @@ -0,0 +1,68 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_NET_ETHERNET is not set +# CONFIG_NET_IPv4 is not set +CONFIG_ALLOW_BSD_COMPONENTS=y +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nucleo-f302r8" +CONFIG_ARCH_BOARD_NUCLEO_F302R8=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f3" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F302R8=y +CONFIG_ARCH_CHIP_STM32F3=y +CONFIG_ARCH_INTERRUPTSTACK=1024 +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_INITTHREAD_STACKSIZE=1024 +CONFIG_BOARD_LOOPSPERMSEC=8499 +CONFIG_BUILTIN=y +CONFIG_CANUTILS_CANDUMP=y +CONFIG_CANUTILS_CANSEND=y +CONFIG_CANUTILS_LIBCANUTILS=y +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_DEFAULT_SMALL=y +CONFIG_ENABLE_ALL_SIGNALS=y +CONFIG_FILE_STREAM=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_IOB_BUFSIZE=64 +CONFIG_IOB_NBUFFERS=5 +CONFIG_IRQ_WORK_STACKSIZE=1024 +CONFIG_LTO_FULL=y +CONFIG_NAME_MAX=0 +CONFIG_NET=y +CONFIG_NETDEV_IFINDEX=y +CONFIG_NETDEV_LATEINIT=y +CONFIG_NET_CAN=y +CONFIG_NET_CAN_ERRORS=y +CONFIG_NET_PREALLOC_DEVIF_CALLBACKS=2 +CONFIG_NET_SOCKOPTS=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_PROMPT_MAX=8 +CONFIG_RAM_SIZE=16386 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_LPWORK=y +CONFIG_SCHED_LPWORKSTACKSIZE=1024 +CONFIG_SCHED_WAITPID=y +CONFIG_SIG_PREALLOC_IRQ_ACTIONS=0 +CONFIG_START_DAY=14 +CONFIG_START_MONTH=10 +CONFIG_START_YEAR=2014 +CONFIG_STM32_CAN1=y +CONFIG_STM32_CAN_SOCKET=y +CONFIG_STM32_CAN_TSEG1=15 +CONFIG_STM32_CAN_TSEG2=2 +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f3/nucleo-f302r8/configs/highpri/defconfig b/boards/arm/stm32f3/nucleo-f302r8/configs/highpri/defconfig new file mode 100644 index 0000000000000..f415d6e0fc5c4 --- /dev/null +++ b/boards/arm/stm32f3/nucleo-f302r8/configs/highpri/defconfig @@ -0,0 +1,59 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nucleo-f302r8" +CONFIG_ARCH_BOARD_NUCLEO_F302R8=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f3" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F302R8=y +CONFIG_ARCH_CHIP_STM32F3=y +CONFIG_ARCH_HIPRI_INTERRUPT=y +CONFIG_ARCH_RAMVECTORS=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_DISABLE_ENVIRON=y +CONFIG_DISABLE_MQUEUE=y +CONFIG_DISABLE_POSIX_TIMERS=y +CONFIG_FDCLONE_STDIO=y +CONFIG_INIT_ENTRYPOINT="highpri_main" +CONFIG_INIT_STACKSIZE=1024 +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBM=y +CONFIG_NAME_MAX=16 +CONFIG_NUCLEOF302R8_HIGHPRI=y +CONFIG_POSIX_SPAWN_DEFAULT_STACKSIZE=512 +CONFIG_PTHREAD_STACK_DEFAULT=1024 +CONFIG_PTHREAD_STACK_MIN=1024 +CONFIG_PWM=y +CONFIG_RAM_SIZE=12288 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_STM32_ADC1=y +CONFIG_STM32_ADC1_DMA=y +CONFIG_STM32_ADC1_DMA_CFG=1 +CONFIG_STM32_ADC1_EXTSEL=y +CONFIG_STM32_ADC_LL_OPS=y +CONFIG_STM32_ADC_NOIRQ=y +CONFIG_STM32_DMA1=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_PWM_LL_OPS=y +CONFIG_STM32_PWR=y +CONFIG_STM32_TIM1=y +CONFIG_STM32_TIM1_PWM=y +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_READLINE=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f3/nucleo-f302r8/configs/ihm07m1_b16/defconfig b/boards/arm/stm32f3/nucleo-f302r8/configs/ihm07m1_b16/defconfig new file mode 100644 index 0000000000000..b0a78520cab60 --- /dev/null +++ b/boards/arm/stm32f3/nucleo-f302r8/configs/ihm07m1_b16/defconfig @@ -0,0 +1,88 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_DISABLE_MQUEUE is not set +# CONFIG_DISABLE_PTHREAD is not set +CONFIG_ADC=y +CONFIG_ADC_FIFOSIZE=3 +CONFIG_ANALOG=y +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nucleo-f302r8" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_NUCLEO_F302R8=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f3" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F302R8=y +CONFIG_ARCH_CHIP_STM32F3=y +CONFIG_ARCH_INTERRUPTSTACK=1024 +CONFIG_ARCH_IRQBUTTONS=y +CONFIG_ARMV7M_LIBM=y +CONFIG_BOARDCTL=y +CONFIG_BOARD_LOOPSPERMSEC=8499 +CONFIG_BOARD_STM32_IHM07M1=y +CONFIG_BOARD_STM32_IHM07M1_POT=y +CONFIG_BOARD_STM32_IHM07M1_VBUS=y +CONFIG_BUILTIN=y +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_DEFAULT_SMALL=y +CONFIG_DEFAULT_TASK_STACKSIZE=1024 +CONFIG_EXAMPLES_FOC=y +CONFIG_EXAMPLES_FOC_ADC_MAX=4095 +CONFIG_EXAMPLES_FOC_ADC_VREF=3300 +CONFIG_EXAMPLES_FOC_CONTROL_STACKSIZE=2048 +CONFIG_EXAMPLES_FOC_FIXED16_INST=1 +CONFIG_EXAMPLES_FOC_HAVE_BUTTON=y +CONFIG_EXAMPLES_FOC_NOTIFIER_FREQ=5000 +CONFIG_EXAMPLES_FOC_PWM_FREQ=20000 +CONFIG_EXAMPLES_FOC_RAMP_ACC=1000000 +CONFIG_EXAMPLES_FOC_RAMP_DEC=1000000 +CONFIG_EXAMPLES_FOC_RAMP_THR=10000 +CONFIG_EXAMPLES_FOC_SETPOINT_ADC=y +CONFIG_EXAMPLES_FOC_VBUS_ADC=y +CONFIG_EXAMPLES_FOC_VBUS_SCALE=19152 +CONFIG_INDUSTRY_FOC=y +CONFIG_INDUSTRY_FOC_FIXED16=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INPUT=y +CONFIG_INPUT_BUTTONS=y +CONFIG_INPUT_BUTTONS_LOWER=y +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBM=y +CONFIG_MOTOR=y +CONFIG_MOTOR_FOC=y +CONFIG_MOTOR_FOC_TRACE=y +CONFIG_MQ_MAXMSGSIZE=5 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_DISABLE_HELP=y +CONFIG_RAM_SIZE=16386 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=14 +CONFIG_START_MONTH=10 +CONFIG_START_YEAR=2014 +CONFIG_STM32_ADC1_ANIOC_TRIGGER=1 +CONFIG_STM32_ADC1_DMA=y +CONFIG_STM32_ADC1_DMA_CFG=1 +CONFIG_STM32_ADC1_INJECTED_CHAN=3 +CONFIG_STM32_DMA1=y +CONFIG_STM32_DMA2=y +CONFIG_STM32_FOC=y +CONFIG_STM32_FOC_FOC0=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_TIM1_CH1MODE=0 +CONFIG_STM32_TIM1_CH2MODE=0 +CONFIG_STM32_TIM1_CH3MODE=0 +CONFIG_STM32_TIM1_MODE=2 +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART2_SERIAL_CONSOLE=y +CONFIG_USART2_TXDMA=y diff --git a/boards/arm/stm32f3/nucleo-f302r8/configs/ihm07m1_f32/defconfig b/boards/arm/stm32f3/nucleo-f302r8/configs/ihm07m1_f32/defconfig new file mode 100644 index 0000000000000..95222d7a3e89f --- /dev/null +++ b/boards/arm/stm32f3/nucleo-f302r8/configs/ihm07m1_f32/defconfig @@ -0,0 +1,87 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_DISABLE_MQUEUE is not set +# CONFIG_DISABLE_PTHREAD is not set +CONFIG_ADC=y +CONFIG_ADC_FIFOSIZE=3 +CONFIG_ANALOG=y +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nucleo-f302r8" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_NUCLEO_F302R8=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f3" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F302R8=y +CONFIG_ARCH_CHIP_STM32F3=y +CONFIG_ARCH_INTERRUPTSTACK=1024 +CONFIG_ARCH_IRQBUTTONS=y +CONFIG_ARMV7M_LIBM=y +CONFIG_BOARDCTL=y +CONFIG_BOARD_LOOPSPERMSEC=8499 +CONFIG_BOARD_STM32_IHM07M1=y +CONFIG_BOARD_STM32_IHM07M1_POT=y +CONFIG_BOARD_STM32_IHM07M1_VBUS=y +CONFIG_BUILTIN=y +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_DEFAULT_SMALL=y +CONFIG_DEFAULT_TASK_STACKSIZE=1024 +CONFIG_EXAMPLES_FOC=y +CONFIG_EXAMPLES_FOC_ADC_MAX=4095 +CONFIG_EXAMPLES_FOC_ADC_VREF=3300 +CONFIG_EXAMPLES_FOC_CONTROL_STACKSIZE=2048 +CONFIG_EXAMPLES_FOC_FLOAT_INST=1 +CONFIG_EXAMPLES_FOC_HAVE_BUTTON=y +CONFIG_EXAMPLES_FOC_NOTIFIER_FREQ=5000 +CONFIG_EXAMPLES_FOC_PWM_FREQ=20000 +CONFIG_EXAMPLES_FOC_RAMP_ACC=1000000 +CONFIG_EXAMPLES_FOC_RAMP_DEC=1000000 +CONFIG_EXAMPLES_FOC_RAMP_THR=10000 +CONFIG_EXAMPLES_FOC_SETPOINT_ADC=y +CONFIG_EXAMPLES_FOC_VBUS_ADC=y +CONFIG_EXAMPLES_FOC_VBUS_SCALE=19152 +CONFIG_INDUSTRY_FOC=y +CONFIG_INDUSTRY_FOC_FLOAT=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INPUT=y +CONFIG_INPUT_BUTTONS=y +CONFIG_INPUT_BUTTONS_LOWER=y +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBM=y +CONFIG_MOTOR=y +CONFIG_MOTOR_FOC=y +CONFIG_MOTOR_FOC_TRACE=y +CONFIG_MQ_MAXMSGSIZE=5 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_RAM_SIZE=16386 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=14 +CONFIG_START_MONTH=10 +CONFIG_START_YEAR=2014 +CONFIG_STM32_ADC1_ANIOC_TRIGGER=1 +CONFIG_STM32_ADC1_DMA=y +CONFIG_STM32_ADC1_DMA_CFG=1 +CONFIG_STM32_ADC1_INJECTED_CHAN=3 +CONFIG_STM32_DMA1=y +CONFIG_STM32_DMA2=y +CONFIG_STM32_FOC=y +CONFIG_STM32_FOC_FOC0=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_TIM1_CH1MODE=0 +CONFIG_STM32_TIM1_CH2MODE=0 +CONFIG_STM32_TIM1_CH3MODE=0 +CONFIG_STM32_TIM1_MODE=2 +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART2_SERIAL_CONSOLE=y +CONFIG_USART2_TXDMA=y diff --git a/boards/arm/stm32f3/nucleo-f302r8/configs/nsh/defconfig b/boards/arm/stm32f3/nucleo-f302r8/configs/nsh/defconfig new file mode 100644 index 0000000000000..7363a11f42d78 --- /dev/null +++ b/boards/arm/stm32f3/nucleo-f302r8/configs/nsh/defconfig @@ -0,0 +1,86 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_SYSTEM_DD is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nucleo-f302r8" +CONFIG_ARCH_BOARD_NUCLEO_F302R8=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f3" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F302R8=y +CONFIG_ARCH_CHIP_STM32F3=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_DISABLE_ENVIRON=y +CONFIG_DISABLE_MQUEUE=y +CONFIG_DISABLE_POSIX_TIMERS=y +CONFIG_DISABLE_PTHREAD=y +CONFIG_EXAMPLES_HELLO=y +CONFIG_FDCLONE_STDIO=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=1024 +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_NAME_MAX=16 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_DISABLE_BASENAME=y +CONFIG_NSH_DISABLE_CAT=y +CONFIG_NSH_DISABLE_CD=y +CONFIG_NSH_DISABLE_CMP=y +CONFIG_NSH_DISABLE_CP=y +CONFIG_NSH_DISABLE_DF=y +CONFIG_NSH_DISABLE_DIRNAME=y +CONFIG_NSH_DISABLE_EXEC=y +CONFIG_NSH_DISABLE_EXIT=y +CONFIG_NSH_DISABLE_GET=y +CONFIG_NSH_DISABLE_HEXDUMP=y +CONFIG_NSH_DISABLE_KILL=y +CONFIG_NSH_DISABLE_LOSETUP=y +CONFIG_NSH_DISABLE_LS=y +CONFIG_NSH_DISABLE_MKDIR=y +CONFIG_NSH_DISABLE_MKRD=y +CONFIG_NSH_DISABLE_MOUNT=y +CONFIG_NSH_DISABLE_MV=y +CONFIG_NSH_DISABLE_PUT=y +CONFIG_NSH_DISABLE_PWD=y +CONFIG_NSH_DISABLE_RM=y +CONFIG_NSH_DISABLE_RMDIR=y +CONFIG_NSH_DISABLE_SET=y +CONFIG_NSH_DISABLE_SLEEP=y +CONFIG_NSH_DISABLE_SOURCE=y +CONFIG_NSH_DISABLE_TEST=y +CONFIG_NSH_DISABLE_TIME=y +CONFIG_NSH_DISABLE_UMOUNT=y +CONFIG_NSH_DISABLE_UNAME=y +CONFIG_NSH_DISABLE_UNSET=y +CONFIG_NSH_DISABLE_USLEEP=y +CONFIG_NSH_DISABLE_WGET=y +CONFIG_NSH_DISABLE_XD=y +CONFIG_NSH_FILEIOSIZE=256 +CONFIG_NSH_READLINE=y +CONFIG_POSIX_SPAWN_DEFAULT_STACKSIZE=512 +CONFIG_PTHREAD_STACK_DEFAULT=1024 +CONFIG_PTHREAD_STACK_MIN=1024 +CONFIG_RAM_SIZE=16386 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_PWR=y +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f3/nucleo-f302r8/configs/qenco/defconfig b/boards/arm/stm32f3/nucleo-f302r8/configs/qenco/defconfig new file mode 100644 index 0000000000000..f8824d5845013 --- /dev/null +++ b/boards/arm/stm32f3/nucleo-f302r8/configs/qenco/defconfig @@ -0,0 +1,112 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_DISABLE_ENVIRON is not set +# CONFIG_DISABLE_MQUEUE is not set +# CONFIG_DISABLE_MQUEUE_NOTIFICATION is not set +# CONFIG_DISABLE_POSIX_TIMERS is not set +# CONFIG_DISABLE_PSEUDOFS_OPERATIONS is not set +# CONFIG_DISABLE_PTHREAD is not set +# CONFIG_NSH_DISABLEBG is not set +# CONFIG_NSH_DISABLESCRIPT is not set +# CONFIG_NSH_DISABLE_BASENAME is not set +# CONFIG_NSH_DISABLE_CAT is not set +# CONFIG_NSH_DISABLE_CD is not set +# CONFIG_NSH_DISABLE_CMP is not set +# CONFIG_NSH_DISABLE_CP is not set +# CONFIG_NSH_DISABLE_DF is not set +# CONFIG_NSH_DISABLE_DIRNAME is not set +# CONFIG_NSH_DISABLE_DMESG is not set +# CONFIG_NSH_DISABLE_ECHO is not set +# CONFIG_NSH_DISABLE_ENV is not set +# CONFIG_NSH_DISABLE_EXEC is not set +# CONFIG_NSH_DISABLE_EXIT is not set +# CONFIG_NSH_DISABLE_EXPORT is not set +# CONFIG_NSH_DISABLE_FREE is not set +# CONFIG_NSH_DISABLE_GET is not set +# CONFIG_NSH_DISABLE_HEXDUMP is not set +# CONFIG_NSH_DISABLE_ITEF is not set +# CONFIG_NSH_DISABLE_KILL is not set +# CONFIG_NSH_DISABLE_LOOPS is not set +# CONFIG_NSH_DISABLE_LOSETUP is not set +# CONFIG_NSH_DISABLE_LS is not set +# CONFIG_NSH_DISABLE_MKDIR is not set +# CONFIG_NSH_DISABLE_MKRD is not set +# CONFIG_NSH_DISABLE_MOUNT is not set +# CONFIG_NSH_DISABLE_MV is not set +# CONFIG_NSH_DISABLE_PRINTF is not set +# CONFIG_NSH_DISABLE_PUT is not set +# CONFIG_NSH_DISABLE_PWD is not set +# CONFIG_NSH_DISABLE_RM is not set +# CONFIG_NSH_DISABLE_RMDIR is not set +# CONFIG_NSH_DISABLE_SEMICOLON is not set +# CONFIG_NSH_DISABLE_SET is not set +# CONFIG_NSH_DISABLE_SLEEP is not set +# CONFIG_NSH_DISABLE_SOURCE is not set +# CONFIG_NSH_DISABLE_TEST is not set +# CONFIG_NSH_DISABLE_TIME is not set +# CONFIG_NSH_DISABLE_TRUNCATE is not set +# CONFIG_NSH_DISABLE_UMOUNT is not set +# CONFIG_NSH_DISABLE_UNAME is not set +# CONFIG_NSH_DISABLE_UNSET is not set +# CONFIG_NSH_DISABLE_UPTIME is not set +# CONFIG_NSH_DISABLE_USLEEP is not set +# CONFIG_NSH_DISABLE_WGET is not set +# CONFIG_NSH_DISABLE_XD is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nucleo-f302r8" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_NUCLEO_F302R8=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f3" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F302R8=y +CONFIG_ARCH_CHIP_STM32F3=y +CONFIG_ARCH_INTERRUPTSTACK=1024 +CONFIG_ARCH_IRQPRIO=y +CONFIG_BOARD_LOOPSPERMSEC=8499 +CONFIG_BUILTIN=y +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_DEFAULT_SMALL=y +CONFIG_EXAMPLES_QENCODER=y +CONFIG_EXAMPLES_QENCODER_HAVE_MAXPOS=y +CONFIG_EXAMPLES_QENCODER_MAXPOS=8192 +CONFIG_FILE_STREAM=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBM_TOOLCHAIN=y +CONFIG_LINE_MAX=80 +CONFIG_MQ_MAXMSGSIZE=5 +CONFIG_NSH_ARGCAT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_CLE=y +CONFIG_NSH_FILEIOSIZE=1024 +CONFIG_PREALLOC_MQ_IRQ_MSGS=8 +CONFIG_PREALLOC_MQ_MSGS=8 +CONFIG_PTHREAD_MUTEX_ROBUST=y +CONFIG_RAM_SIZE=16386 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_SENSORS=y +CONFIG_SENSORS_QENCODER=y +CONFIG_SIG_PREALLOC_IRQ_ACTIONS=8 +CONFIG_START_DAY=14 +CONFIG_START_MONTH=10 +CONFIG_START_YEAR=2014 +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_QENCODER_DISABLE_EXTEND16BTIMERS=y +CONFIG_STM32_QENCODER_SAMPLE_FDTS_2=y +CONFIG_STM32_TIM2=y +CONFIG_STM32_TIM2_QE=y +CONFIG_STM32_TIM2_QEPSC=0 +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f3/nucleo-f302r8/include/board.h b/boards/arm/stm32f3/nucleo-f302r8/include/board.h new file mode 100644 index 0000000000000..14529925ce35c --- /dev/null +++ b/boards/arm/stm32f3/nucleo-f302r8/include/board.h @@ -0,0 +1,308 @@ +/**************************************************************************** + * boards/arm/stm32f3/nucleo-f302r8/include/board.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_STM32_NUCLEO_F302R8_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32_NUCLEO_F302R8_INCLUDE_BOARD_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#ifndef __ASSEMBLY__ +# include +# include +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Clocking *****************************************************************/ + +/* HSI - Internal 8 MHz RC Oscillator + * LSI - 32 KHz RC + * HSE - On-board crystal frequency is 8MHz + * LSE - 32.768 kHz + */ + +#define STM32_BOARD_XTAL 8000000ul /* X1 on board */ + +#define STM32_HSI_FREQUENCY 8000000ul +#define STM32_LSI_FREQUENCY 40000 /* Between 30kHz and 60kHz */ +#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL +#define STM32_LSE_FREQUENCY 32768 /* X2 on board */ + +/* PLL source is HSE/1, PLL multiplier is 9: PLL frequency is + * 8MHz (XTAL) x 9 = 72MHz + */ + +#define STM32_CFGR_PLLSRC RCC_CFGR_PLLSRC +#define STM32_CFGR_PLLXTPRE 0 +#define STM32_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx9 +#define STM32_PLL_FREQUENCY (9*STM32_BOARD_XTAL) + +/* Use the PLL and set the SYSCLK source to be the PLL */ + +#define STM32_SYSCLK_SW RCC_CFGR_SW_PLL +#define STM32_SYSCLK_SWS RCC_CFGR_SWS_PLL +#define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY + +/* AHB clock (HCLK) is SYSCLK (72MHz) */ + +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY + +/* APB2 clock (PCLK2) is HCLK (72MHz) */ + +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK +#define STM32_PCLK2_FREQUENCY STM32_HCLK_FREQUENCY +#define STM32_APB2_CLKIN (STM32_PCLK2_FREQUENCY) /* Timers 1 and 8, 15-17 */ + +/* APB2 timers 1 and 8, 15-17 will receive PCLK2. */ + +/* Timers driven from APB2 will be PCLK2 */ + +#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB1_TIM15_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB1_TIM16_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB1_TIM17_CLKIN (STM32_PCLK2_FREQUENCY) + +/* APB1 clock (PCLK1) is HCLK/2 (36MHz) */ + +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd2 +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/2) + +/* APB1 timers 2-7 will be twice PCLK1 */ + +#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) + +/* USB divider -- Divide PLL clock by 1.5 */ + +#define STM32_CFGR_USBPRE 0 + +/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx + * otherwise frequency is 2xAPBx. + * Note: TIM1,8 are on APB2, others on APB1 + */ + +#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM2_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM3_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM4_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM5_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM6_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM7_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY + +/* LED definitions **********************************************************/ + +/* The Nucleo F302R8 board has three LEDs. Two of these are controlled by + * logic on the board and are not available for software control: + * + * LD1 COM: LD1 default status is red. LD1 turns to green to indicate that + * communications are in progress between the PC and the + * ST-LINK/V2-1. + * LD3 PWR: red LED indicates that the board is powered. + * + * And one can be controlled by software: + * + * User LD2: green LED is a user LED connected to the I/O PB13 of the + * STM32F302R8T6. + * + * If CONFIG_ARCH_LEDS is not defined, then the user can control the LED in + * any way. The following definition is used to access the LED. + */ + +/* LED index values for use with board_userled() */ + +#define BOARD_LED1 0 /* User LD2 */ +#define BOARD_NLEDS 1 + +/* LED bits for use with board_userled_all() */ + +#define BOARD_LED1_BIT (1 << BOARD_LED1) + +/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the LED on board + * the Nucleo F302R8. The following definitions describe how NuttX controls + * the LED: + * + * SYMBOL Meaning LED1 state + * ------------------ ----------------------- ---------- + * LED_STARTED NuttX has been started OFF + * LED_HEAPALLOCATE Heap has been allocated OFF + * LED_IRQSENABLED Interrupts enabled OFF + * LED_STACKCREATED Idle stack created ON + * LED_INIRQ In an interrupt No change + * LED_SIGNAL In a signal handler No change + * LED_ASSERTION An assertion failed No change + * LED_PANIC The system has crashed Blinking + * LED_IDLE STM32 is in sleep mode Not used + */ + +#define LED_STARTED 0 +#define LED_HEAPALLOCATE 0 +#define LED_IRQSENABLED 0 +#define LED_STACKCREATED 1 +#define LED_INIRQ 2 +#define LED_SIGNAL 2 +#define LED_ASSERTION 2 +#define LED_PANIC 1 + +/* Button definitions *******************************************************/ + +/* The Nucleo F302R8 supports two buttons; only one button is controllable + * by software: + * + * B1 USER: user button connected to the I/O PC13 of the STM32F302R8T6. + * B2 RESET: push button connected to NRST is used to RESET the + * STM32F302R8T6. + */ + +#define BUTTON_USER 0 +#define NUM_BUTTONS 1 + +#define BUTTON_USER_BIT (1 << BUTTON_USER) + +/* Alternate function pin selections ****************************************/ + +/* TIM2 input ***************************************************************/ + +#define GPIO_TIM2_CH1IN (GPIO_TIM2_CH1IN_2 | GPIO_PULLUP | GPIO_SPEED_50MHz) /* PA15 */ +#define GPIO_TIM2_CH2IN (GPIO_TIM2_CH2IN_2 | GPIO_PULLUP | GPIO_SPEED_50MHz) /* PB3 */ + +/* USART */ + +/* By default the USART2 is connected to STLINK Virtual COM Port: + * USART2_RX - PA3 + * USART2_TX - PA2 + */ + +#define GPIO_USART2_RX (GPIO_USART2_RX_2|GPIO_SPEED_50MHz) /* PA3 */ +#define GPIO_USART2_TX (GPIO_USART2_TX_2|GPIO_SPEED_50MHz) /* PA2 */ + +/* USART1 + * + * At default use: + * USART1_RX - PB7 + * USART1_TX - PB6 + * + * If CONFIG_NUCLEOF302R8_RS485_WAVESHARE=y use configuration to match RS485 + * shield from Waveshare: + * + * USART1_RX - PA10 + * USART1_TX - PA9 + * RS485_DIR - PA8 (arduino D7) + * + */ + +#ifdef CONFIG_NUCLEOF302R8_RS485_WAVESHARE +# define GPIO_USART1_RX (GPIO_USART1_RX_1|GPIO_SPEED_50MHz) /* PA10 */ +# define GPIO_USART1_TX (GPIO_USART1_TX_1|GPIO_SPEED_50MHz) /* PA9 */ +# define GPIO_USART1_RS485_DIR (GPIO_OUTPUT | GPIO_PUSHPULL | \ + GPIO_SPEED_50MHz | GPIO_OUTPUT_CLEAR | \ + GPIO_PORTA | GPIO_PIN8) +#else +# define GPIO_USART1_RX (GPIO_USART1_RX_2|GPIO_SPEED_50MHz) /* PB7 */ +# define GPIO_USART1_TX (GPIO_USART1_TX_2|GPIO_SPEED_50MHz) /* PB6 */ +#endif + +/* CAN */ + +#define GPIO_CAN1_RX (GPIO_CAN_RX_3|GPIO_SPEED_50MHz) /* PB8 */ +#define GPIO_CAN1_TX (GPIO_CAN_TX_3|GPIO_SPEED_50MHz) /* PB9 */ + +/* PWM configuration ********************************************************/ + +/* TIM1 PWM */ + +#define STM32_TIM1_TRGO 0 + +#define GPIO_TIM1_CH1OUT (GPIO_TIM1_CH1OUT_2|GPIO_SPEED_50MHz) /* PA8 */ +#define GPIO_TIM1_CH1NOUT (GPIO_TIM1_CH1N_3|GPIO_SPEED_50MHz) /* PA11 */ +#define GPIO_TIM1_CH2OUT (GPIO_TIM1_CH2OUT_2|GPIO_SPEED_50MHz) /* PA9 */ +#define GPIO_TIM1_CH2NOUT (GPIO_TIM1_CH2N_2|GPIO_SPEED_50MHz) /* PA12 */ +#define GPIO_TIM1_CH3OUT (GPIO_TIM1_CH3OUT_2|GPIO_SPEED_50MHz) /* PA10 */ +#define GPIO_TIM1_CH3NOUT (GPIO_TIM1_CH3N_3|GPIO_SPEED_50MHz) /* PB1 */ + +/* TIM2 PWM */ + +#define GPIO_TIM2_CH1OUT (GPIO_TIM2_CH1_ETR_1|GPIO_SPEED_50MHz) /* PA0 */ +#define GPIO_TIM2_CH2OUT (GPIO_TIM2_CH2OUT_1|GPIO_SPEED_50MHz) /* PA1 */ +#define GPIO_TIM2_CH3OUT (GPIO_TIM2_CH3OUT_1|GPIO_SPEED_50MHz) /* PA9 */ + +/* DMA channels *************************************************************/ + +/* ADC */ + +#define ADC1_DMA_CHAN DMACHAN_ADC1 /* DMA1_CH1 */ + +#ifdef CONFIG_BOARD_STM32_IHM07M1 + +/* Configuration specific for the X-NUCLEO-IHM07M1 expansion board with + * the L6230 gate drivers. + */ + +/* TIM1 configuration *******************************************************/ + +# define GPIO_TIM1_CH1OUT (GPIO_TIM1_CH1OUT_2|GPIO_SPEED_50MHz) /* TIM1 CH1 - PA8 - U high */ +# define GPIO_TIM1_CH2OUT (GPIO_TIM1_CH2OUT_2|GPIO_SPEED_50MHz) /* TIM1 CH2 - PA9 - V high */ +# define GPIO_TIM1_CH3OUT (GPIO_TIM1_CH3OUT_2|GPIO_SPEED_50MHz) /* TIM1 CH3 - PA10 - W high */ +# define GPIO_TIM1_CH4OUT 0 /* not used as output */ + +/* UVW ENABLE */ + +# define GPIO_FOC_EN_U (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz| \ + GPIO_OUTPUT_CLEAR|GPIO_PORTC|GPIO_PIN10) +# define GPIO_FOC_EN_V (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz| \ + GPIO_OUTPUT_CLEAR|GPIO_PORTC|GPIO_PIN11) +# define GPIO_FOC_EN_W (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz| \ + GPIO_OUTPUT_CLEAR|GPIO_PORTC|GPIO_PIN12) + +/* DIAG/ENABLE */ + +# define GPIO_FOC_DIAGEN (GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz| \ + GPIO_OUTPUT_CLEAR|GPIO_PORTA|GPIO_PIN11) + +# define GPIO_FOC_LED2 (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz| \ + GPIO_OUTPUT_CLEAR|GPIO_PORTB|GPIO_PIN2) + +/* Debug pins */ + +# define GPIO_FOC_DEBUG0 (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz| \ + GPIO_OUTPUT_CLEAR|GPIO_PORTB|GPIO_PIN8) +# define GPIO_FOC_DEBUG1 (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz| \ + GPIO_OUTPUT_CLEAR|GPIO_PORTB|GPIO_PIN9) +# define GPIO_FOC_DEBUG2 (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz| \ + GPIO_OUTPUT_CLEAR|GPIO_PORTC|GPIO_PIN6) +# define GPIO_FOC_DEBUG3 (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz| \ + GPIO_OUTPUT_CLEAR|GPIO_PORTC|GPIO_PIN5) + +#endif /* CONFIG_BOARD_STM32_IHM07M1 */ + +#endif /* __BOARDS_ARM_STM32_NUCLEO_F302R8_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32f3/nucleo-f302r8/scripts/Make.defs b/boards/arm/stm32f3/nucleo-f302r8/scripts/Make.defs new file mode 100644 index 0000000000000..32cfbf2717852 --- /dev/null +++ b/boards/arm/stm32f3/nucleo-f302r8/scripts/Make.defs @@ -0,0 +1,41 @@ +############################################################################ +# boards/arm/stm32f3/nucleo-f302r8/scripts/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/.config +include $(TOPDIR)/tools/Config.mk +include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs + +LDSCRIPT = ld.script +ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) + +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32f3/nucleo-f302r8/scripts/ld.script b/boards/arm/stm32f3/nucleo-f302r8/scripts/ld.script new file mode 100644 index 0000000000000..a5bad8b6daca6 --- /dev/null +++ b/boards/arm/stm32f3/nucleo-f302r8/scripts/ld.script @@ -0,0 +1,127 @@ +/**************************************************************************** + * boards/arm/stm32f3/nucleo-f302r8/scripts/ld.script + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* The STM32F302R8T6 has 64Kb of FLASH beginning at address 0x0800:0000 and + * 16Kb of SRAM. + * + * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 + * where the code expects to begin execution by jumping to the entry point in + * the 0x0800:0000 address range. + */ + +MEMORY +{ + flash (rx) : ORIGIN = 0x08000000, LENGTH = 64K + sram (rwx) : ORIGIN = 0x20000000, LENGTH = 16K +} + +OUTPUT_ARCH(arm) +EXTERN(_vectors) +ENTRY(_stext) +SECTIONS +{ + .text : { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > flash + + .init_section : ALIGN(4) { + _sinit = ABSOLUTE(.); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) + _einit = ABSOLUTE(.); + } > flash + + .ARM.extab : ALIGN(4) { + *(.ARM.extab*) + } > flash + + .ARM.exidx : ALIGN(4) { + __exidx_start = ABSOLUTE(.); + *(.ARM.exidx*) + __exidx_end = ABSOLUTE(.); + } > flash + + .tdata : { + _stdata = ABSOLUTE(.); + *(.tdata .tdata.* .gnu.linkonce.td.*); + _etdata = ABSOLUTE(.); + } > flash + + .tbss : { + _stbss = ABSOLUTE(.); + *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); + _etbss = ABSOLUTE(.); + } > flash + + _eronly = ABSOLUTE(.); + + /* The RAM vector table (if present) should lie at the beginning of SRAM */ + + .ram_vectors : { + *(.ram_vectors) + } > sram + + .data : ALIGN(4) { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > sram AT > flash + + .bss : ALIGN(4) { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + _ebss = ABSOLUTE(.); + } > sram + + /* Stabs debugging sections. */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/stm32f3/nucleo-f302r8/src/CMakeLists.txt b/boards/arm/stm32f3/nucleo-f302r8/src/CMakeLists.txt new file mode 100644 index 0000000000000..d2e1166c77e9c --- /dev/null +++ b/boards/arm/stm32f3/nucleo-f302r8/src/CMakeLists.txt @@ -0,0 +1,62 @@ +# ############################################################################## +# boards/arm/stm32f3/nucleo-f302r8/src/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(SRCS stm32_boot.c stm32_bringup.c) + +if(CONFIG_ARCH_LEDS) + list(APPEND SRCS stm32_autoleds.c) +else() + list(APPEND SRCS stm32_userleds.c) +endif() + +if(CONFIG_ARCH_BUTTONS) + list(APPEND SRCS stm32_buttons.c) +endif() + +if(CONFIG_PWM) + list(APPEND SRCS stm32_pwm.c) +endif() + +if(CONFIG_NUCLEOF302R8_HIGHPRI) + list(APPEND SRCS stm32_highpri.c) +endif() + +if(CONFIG_BOARD_STM32_IHM07M1) + list(APPEND SRCS stm32_foc_ihm07m1.c) +else() + if(CONFIG_ADC) + list(APPEND SRCS stm32_adc.c) + endif() +endif() + +if(CONFIG_STM32_CAN) + if(CONFIG_STM32_CAN_CHARDRIVER) + list(APPEND SRCS stm32_can.c) + endif() + if(CONFIG_STM32_CAN_SOCKET) + list(APPEND SRCS stm32_cansock.c) + endif() +endif() + +target_sources(board PRIVATE ${SRCS}) + +set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/ld.script") diff --git a/boards/arm/stm32f3/nucleo-f302r8/src/Make.defs b/boards/arm/stm32f3/nucleo-f302r8/src/Make.defs new file mode 100644 index 0000000000000..4b4fc883e987f --- /dev/null +++ b/boards/arm/stm32f3/nucleo-f302r8/src/Make.defs @@ -0,0 +1,64 @@ +############################################################################ +# boards/arm/stm32f3/nucleo-f302r8/src/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +CSRCS = stm32_boot.c stm32_bringup.c + +ifeq ($(CONFIG_ARCH_LEDS),y) +CSRCS += stm32_autoleds.c +else +CSRCS += stm32_userleds.c +endif + +ifeq ($(CONFIG_ARCH_BUTTONS),y) +CSRCS += stm32_buttons.c +endif + +ifeq ($(CONFIG_PWM),y) +CSRCS += stm32_pwm.c +endif + +ifeq ($(CONFIG_NUCLEOF302R8_HIGHPRI),y) +CSRCS += stm32_highpri.c +endif + +ifeq ($(CONFIG_BOARD_STM32_IHM07M1),y) +CSRCS += stm32_foc_ihm07m1.c +else +ifeq ($(CONFIG_ADC),y) +CSRCS += stm32_adc.c +endif +endif + +ifeq ($(CONFIG_STM32_CAN),y) +ifeq ($(CONFIG_STM32_CAN_CHARDRIVER),y) +CSRCS += stm32_can.c +endif +ifeq ($(CONFIG_STM32_CAN_SOCKET),y) +CSRCS += stm32_cansock.c +endif +endif + +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/nucleo-f302r8/src/nucleo-f302r8.h b/boards/arm/stm32f3/nucleo-f302r8/src/nucleo-f302r8.h similarity index 99% rename from boards/arm/stm32/nucleo-f302r8/src/nucleo-f302r8.h rename to boards/arm/stm32f3/nucleo-f302r8/src/nucleo-f302r8.h index 6c3c83d04a00a..f38dbe2ed2873 100644 --- a/boards/arm/stm32/nucleo-f302r8/src/nucleo-f302r8.h +++ b/boards/arm/stm32f3/nucleo-f302r8/src/nucleo-f302r8.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f302r8/src/nucleo-f302r8.h + * boards/arm/stm32f3/nucleo-f302r8/src/nucleo-f302r8.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f3/nucleo-f302r8/src/stm32_adc.c b/boards/arm/stm32f3/nucleo-f302r8/src/stm32_adc.c new file mode 100644 index 0000000000000..b4aed937ec96b --- /dev/null +++ b/boards/arm/stm32f3/nucleo-f302r8/src/stm32_adc.c @@ -0,0 +1,112 @@ +/**************************************************************************** + * boards/arm/stm32f3/nucleo-f302r8/src/stm32_adc.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include + +#include "stm32.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifndef CONFIG_STM32_ADC1 +# error ADC1 support must be enabled +#endif + +#ifndef CONFIG_STM32_ADC1_DMA +# error ADC1 DMA support must be enabled +#endif + +#define ADC1_NCHANNELS 4 + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* Use CN8 pins 35, 36, 37 and 38 */ + +static const uint8_t g_adc1_chanlist[ADC1_NCHANNELS] = +{ + 6, 7, 8, 9 +}; + +static const uint32_t g_adc1_pinlist[ADC1_NCHANNELS] = +{ + GPIO_ADC1_IN6_0, /* PC0 */ + GPIO_ADC1_IN7_0, /* PC1 */ + GPIO_ADC1_IN8_0, /* PC2 */ + GPIO_ADC1_IN9_0, /* PC3 */ +}; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_adc_setup + * + * Description: + * Initialize ADC and register the ADC driver. + * + ****************************************************************************/ + +int stm32_adc_setup(void) +{ + struct adc_dev_s *adc; + int ret; + int i; + + /* Configure the pins as analog inputs for the selected channels */ + + for (i = 0; i < ADC1_NCHANNELS; i++) + { + stm32_configgpio(g_adc1_pinlist[i]); + } + + /* Call stm32_adcinitialize() to get an instance of the ADC interface */ + + adc = stm32_adcinitialize(1, g_adc1_chanlist, ADC1_NCHANNELS); + if (adc == NULL) + { + aerr("ERROR: Failed to get ADC interface\n"); + return -ENODEV; + } + + /* Register the ADC driver at "/dev/adc0" */ + + ret = adc_register("/dev/adc0", adc); + if (ret < 0) + { + aerr("ERROR: adc_register failed: %d\n", ret); + return ret; + } + + return OK; +} diff --git a/boards/arm/stm32f3/nucleo-f302r8/src/stm32_autoleds.c b/boards/arm/stm32f3/nucleo-f302r8/src/stm32_autoleds.c new file mode 100644 index 0000000000000..16b52f1961fb9 --- /dev/null +++ b/boards/arm/stm32f3/nucleo-f302r8/src/stm32_autoleds.c @@ -0,0 +1,80 @@ +/**************************************************************************** + * boards/arm/stm32f3/nucleo-f302r8/src/stm32_autoleds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "stm32.h" +#include "nucleo-f302r8.h" + +#ifdef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_autoled_initialize + ****************************************************************************/ + +void board_autoled_initialize(void) +{ + /* Configure LED1 GPIO for output */ + + stm32_configgpio(GPIO_LED1); +} + +/**************************************************************************** + * Name: board_autoled_on + ****************************************************************************/ + +void board_autoled_on(int led) +{ + if (led == BOARD_LED1) + { + stm32_gpiowrite(GPIO_LED1, true); + } +} + +/**************************************************************************** + * Name: board_autoled_off + ****************************************************************************/ + +void board_autoled_off(int led) +{ + if (led == BOARD_LED1) + { + stm32_gpiowrite(GPIO_LED1, false); + } +} + +#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32f3/nucleo-f302r8/src/stm32_boot.c b/boards/arm/stm32f3/nucleo-f302r8/src/stm32_boot.c new file mode 100644 index 0000000000000..58c14e3183616 --- /dev/null +++ b/boards/arm/stm32f3/nucleo-f302r8/src/stm32_boot.c @@ -0,0 +1,95 @@ +/**************************************************************************** + * boards/arm/stm32f3/nucleo-f302r8/src/stm32_boot.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include "nucleo-f302r8.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_boardinitialize + * + * Description: + * All STM32 architectures must provide the following entry point. This + * entry point is called early in the initialization -- after all memory + * has been configured and mapped but before any devices have been + * initialized. + * + ****************************************************************************/ + +void stm32_boardinitialize(void) +{ + /* Configure on-board LEDs if LED support has been selected. */ + +#ifdef CONFIG_ARCH_LEDS + board_autoled_initialize(); +#endif +} + +/**************************************************************************** + * Name: board_late_initialize + * + * Description: + * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_late_initialize(). board_late_initialize() will + * be called immediately after up_initialize() is called and just before + * the initial application is started. This additional initialization + * phase may be used, for example, to initialize board-specific device + * drivers. + * + ****************************************************************************/ + +#ifdef CONFIG_BOARD_LATE_INITIALIZE +void board_late_initialize(void) +{ + /* Perform board-specific initialization */ + + stm32_bringup(); +} +#endif diff --git a/boards/arm/stm32f3/nucleo-f302r8/src/stm32_bringup.c b/boards/arm/stm32f3/nucleo-f302r8/src/stm32_bringup.c new file mode 100644 index 0000000000000..ddf259cacf795 --- /dev/null +++ b/boards/arm/stm32f3/nucleo-f302r8/src/stm32_bringup.c @@ -0,0 +1,188 @@ +/**************************************************************************** + * boards/arm/stm32f3/nucleo-f302r8/src/stm32_bringup.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include + +#include + +#ifdef CONFIG_USERLED +# include +#endif + +#ifdef CONFIG_INPUT_BUTTONS +# include +#endif + +#ifdef CONFIG_SENSORS_QENCODER +# include "board_qencoder.h" +#endif + +#ifdef CONFIG_SENSORS_HALL3PHASE +# include "board_hall3ph.h" +#endif + +#include "nucleo-f302r8.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#undef HAVE_LEDS +#undef HAVE_DAC + +#if !defined(CONFIG_ARCH_LEDS) && defined(CONFIG_USERLED_LOWER) +# define HAVE_LEDS 1 +#endif + +#if defined(CONFIG_DAC) +# define HAVE_DAC 1 +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_bringup + * + * Description: + * Perform architecture-specific initialization + * + * CONFIG_BOARD_LATE_INITIALIZE=y : + * Called from board_late_initialize(). + * + ****************************************************************************/ + +int stm32_bringup(void) +{ + int ret; + +#ifdef CONFIG_INPUT_BUTTONS + /* Register the BUTTON driver */ + + ret = btn_lower_initialize("/dev/buttons"); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: btn_lower_initialize() failed: %d\n", ret); + } +#endif + +#ifdef HAVE_LEDS + /* Register the LED driver */ + + ret = userled_lower_initialize(LED_DRIVER_PATH); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: userled_lower_initialize() failed: %d\n", ret); + return ret; + } +#endif + +#ifdef CONFIG_PWM + /* Initialize PWM and register the PWM device. */ + + ret = stm32_pwm_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_pwm_setup() failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_STM32_FOC + /* Initialize and register the FOC device */ + + ret = stm32_foc_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_foc_setup failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_ADC + /* Initialize ADC and register the ADC driver. */ + + ret = stm32_adc_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_adc_setup failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_SENSORS_QENCODER + /* Initialize and register the qencoder driver */ + + ret = board_qencoder_initialize(0, CONFIG_NUCLEO_F302R8_QETIMER); + if (ret != OK) + { + syslog(LOG_ERR, + "ERROR: Failed to register the qencoder: %d\n", + ret); + return ret; + } +#endif + +#ifdef CONFIG_SENSORS_HALL3PHASE + /* Initialize and register the 3-phase Hall effect sensor driver */ + + ret = board_hall3ph_initialize(0, GPIO_HALL_PHA, GPIO_HALL_PHB, + GPIO_HALL_PHC); + if (ret != OK) + { + syslog(LOG_ERR, + "ERROR: Failed to register the hall : %d\n", + ret); + return ret; + } +#endif + +#ifdef CONFIG_STM32_CAN_CHARDRIVER + /* Initialize CAN and register the CAN driver. */ + + ret = stm32_can_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_can_setup failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_STM32_CAN_SOCKET + /* Initialize CAN socket interface */ + + ret = stm32_cansock_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_cansock_setup failed: %d\n", ret); + } +#endif + + UNUSED(ret); + return OK; +} diff --git a/boards/arm/stm32f3/nucleo-f302r8/src/stm32_buttons.c b/boards/arm/stm32f3/nucleo-f302r8/src/stm32_buttons.c new file mode 100644 index 0000000000000..718b549d346af --- /dev/null +++ b/boards/arm/stm32f3/nucleo-f302r8/src/stm32_buttons.c @@ -0,0 +1,113 @@ +/**************************************************************************** + * boards/arm/stm32f3/nucleo-f302r8/src/stm32_buttons.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "stm32.h" +#include "nucleo-f302r8.h" + +#ifdef CONFIG_ARCH_BUTTONS + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_button_initialize + * + * Description: + * board_button_initialize() must be called to initialize button + * resources. After that, board_buttons() may be called to collect the + * current state of all buttons or board_button_irq() may be called to + * register button interrupt handlers. + * + ****************************************************************************/ + +uint32_t board_button_initialize(void) +{ + /* Configure the single button as an input. NOTE that EXTI interrupts are + * also configured for the pin. + */ + + stm32_configgpio(GPIO_BTN_USER); + return NUM_BUTTONS; +} + +/**************************************************************************** + * Name: board_buttons + * + * Description: + * After board_button_initialize() has been called, board_buttons() may be + * called to collect the state of all buttons. board_buttons() returns an + * 32-bit unsigned integer with each bit associated with a button. See the + * BUTTON_*_BIT definitions in board.h for the meaning of each bit. + * + ****************************************************************************/ + +uint32_t board_buttons(void) +{ + /* Check the state of the USER button. A LOW value means that the key is + * pressed. + */ + + return stm32_gpioread(GPIO_BTN_USER) ? 0 : BUTTON_USER_BIT; +} + +/**************************************************************************** + * Name: board_button_irq + * + * Description: + * board_button_irq() may be called to register an interrupt handler that + * will be called when a button is depressed or released. The ID value is + * a button enumeration value that uniquely identifies a button resource. + * See the BUTTON_* definitions in board.h for the meaning of the + * enumeration value. + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_IRQBUTTONS +int board_button_irq(int id, xcpt_t irqhandler, void *arg) +{ + int ret = -EINVAL; + + if (id == BUTTON_USER) + { + ret = stm32_gpiosetevent(GPIO_BTN_USER, true, true, true, irqhandler, + arg); + } + + return ret; +} +#endif + +#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/stm32f3/nucleo-f302r8/src/stm32_can.c b/boards/arm/stm32f3/nucleo-f302r8/src/stm32_can.c new file mode 100644 index 0000000000000..c75d14627c29d --- /dev/null +++ b/boards/arm/stm32f3/nucleo-f302r8/src/stm32_can.c @@ -0,0 +1,73 @@ +/**************************************************************************** + * boards/arm/stm32f3/nucleo-f302r8/src/stm32_can.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include + +#include "stm32.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_can_setup + * + * Description: + * Initialize CAN and register the CAN device + * + ****************************************************************************/ + +int stm32_can_setup(void) +{ + struct can_dev_s *can; + int ret; + + /* Call stm32_caninitialize() to get an instance of the CAN interface */ + + can = stm32_caninitialize(1); + if (can == NULL) + { + canerr("ERROR: Failed to get CAN interface\n"); + return -ENODEV; + } + + /* Register the CAN driver at "/dev/can0" */ + + ret = can_register("/dev/can0", can); + if (ret < 0) + { + canerr("ERROR: can_register failed: %d\n", ret); + return ret; + } + + return OK; +} diff --git a/boards/arm/stm32f3/nucleo-f302r8/src/stm32_cansock.c b/boards/arm/stm32f3/nucleo-f302r8/src/stm32_cansock.c new file mode 100644 index 0000000000000..6a7ed672f30bb --- /dev/null +++ b/boards/arm/stm32f3/nucleo-f302r8/src/stm32_cansock.c @@ -0,0 +1,59 @@ +/**************************************************************************** + * boards/arm/stm32f3/nucleo-f302r8/src/stm32_cansock.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include "stm32_can.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_cansock_setup + * + * Description: + * Initialize CAN socket interface + * + ****************************************************************************/ + +int stm32_cansock_setup(void) +{ + int ret; + + /* Call stm32_caninitialize() to get an instance of the CAN interface */ + + ret = stm32_cansockinitialize(1); + if (ret < 0) + { + canerr("ERROR: Failed to get CAN interface %d\n", ret); + return ret; + } + + return OK; +} diff --git a/boards/arm/stm32f3/nucleo-f302r8/src/stm32_foc_ihm07m1.c b/boards/arm/stm32f3/nucleo-f302r8/src/stm32_foc_ihm07m1.c new file mode 100644 index 0000000000000..b06c6378f9dab --- /dev/null +++ b/boards/arm/stm32f3/nucleo-f302r8/src/stm32_foc_ihm07m1.c @@ -0,0 +1,183 @@ +/**************************************************************************** + * boards/arm/stm32f3/nucleo-f302r8/src/stm32_foc_ihm07m1.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "stm32_ihm07m1.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define CURRENT_SAMPLE_TIME ADC_SMPR_19p5 +#define VBUS_SAMPLE_TIME ADC_SMPR_601p5 +#define POT_SAMPLE_TIME ADC_SMPR_601p5 + +/* ADC1 channels used in this example */ + +#define ADC1_INJECTED (CONFIG_MOTOR_FOC_SHUNTS) + +#ifdef CONFIG_BOARD_STM32_IHM07M1_VBUS +# define IHM07M1_VBUS 1 +#else +# define IHM07M1_VBUS 0 +#endif + +#ifdef CONFIG_BOARD_STM32_IHM07M1_POT +# define IHM07M1_POT 1 +#else +# define IHM07M1_POT 0 +#endif + +#define ADC1_REGULAR (IHM07M1_VBUS + IHM07M1_POT) +#define ADC1_NCHANNELS (ADC1_INJECTED + ADC1_REGULAR) + +/* Check ADC1 configuration */ + +#if ADC1_INJECTED != CONFIG_STM32_ADC1_INJECTED_CHAN +# error +#endif + +#if CONFIG_STM32_ADC1_RESOLUTION != 0 +# error +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* FOC ADC configuration: + * - Current Phase V -> ADC1 INJ1 -> ADC1_IN1 (PA0) + * - Current Phase U -> ADC1 INJ2 -> ADC1_IN7 (PC1) + * - Current Phase W -> ADC1 INJ3 -> ADC1_IN6 (PC0) + * optional: + * - VBUS -> ADC1 REG -> ADC1_IN2 (PA1) + * - POT -> ADC1 REG -> ADC1_IN12 (PB1) + * + * TIM1 PWM configuration: + * - Phase U high -> TIM1_CH1 (PA8) + * - Phase V high -> TIM1_CH2 (PA9) + * - Phase W high -> TIM1_CH3 (PA10) + * + */ + +static uint8_t g_adc1_chan[] = +{ +#ifdef CONFIG_BOARD_STM32_IHM07M1_VBUS + 2, /* ADC1 REG - VBUS */ +#endif +#ifdef CONFIG_BOARD_STM32_IHM07M1_POT + 12, /* ADC1 REG - POT */ +#endif + 1, /* ADC1 INJ1 - PHASE 1 */ +#if CONFIG_MOTOR_FOC_SHUNTS == 3 + 7, /* ADC1 INJ2 - PHASE 2 */ + 6, /* ADC1 INJ3 - PHASE 3 */ +#endif +}; + +static uint32_t g_adc1_pins[] = +{ +#ifdef CONFIG_BOARD_STM32_IHM07M1_VBUS + GPIO_ADC1_IN2_0, +#endif +#ifdef CONFIG_BOARD_STM32_IHM07M1_POT + GPIO_ADC1_IN12_0, +#endif + GPIO_ADC1_IN1_0, +#if CONFIG_MOTOR_FOC_SHUNTS > 1 + GPIO_ADC1_IN7_0, +#endif +#if CONFIG_MOTOR_FOC_SHUNTS > 2 + GPIO_ADC1_IN6_0, +#endif +}; + +/* ADC1 sample time configuration */ + +static adc_channel_t g_adc1_stime[] = +{ +#ifdef CONFIG_BOARD_STM32_IHM07M1_VBUS + { + .channel = 2, + .sample_time = VBUS_SAMPLE_TIME + }, +#endif +#ifdef CONFIG_BOARD_STM32_IHM07M1_POT + { + .channel = 12, + .sample_time = POT_SAMPLE_TIME + }, +#endif + { + .channel = 1, + .sample_time = CURRENT_SAMPLE_TIME + }, +#if CONFIG_MOTOR_FOC_SHUNTS > 1 + { + .channel = 7, + .sample_time = CURRENT_SAMPLE_TIME + }, +#endif +#if CONFIG_MOTOR_FOC_SHUNTS > 2 + { + .channel = 6, + .sample_time = CURRENT_SAMPLE_TIME + }, +#endif +}; + +/* Board specific ADC configuration for FOC */ + +static struct stm32_foc_adc_s g_adc_cfg = +{ + .chan = g_adc1_chan, + .pins = g_adc1_pins, + .stime = g_adc1_stime, + .nchan = ADC1_NCHANNELS, + .regch = ADC1_REGULAR, + .intf = 1 +}; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_foc_setup + * + * Description: + * Initialize FOC driver. + * + * Returned Value: + * 0 on success, a negated errno value on failure + * + ****************************************************************************/ + +int stm32_foc_setup(void) +{ + return board_ihm07m1_initialize(&g_adc_cfg); +} diff --git a/boards/arm/stm32f3/nucleo-f302r8/src/stm32_highpri.c b/boards/arm/stm32f3/nucleo-f302r8/src/stm32_highpri.c new file mode 100644 index 0000000000000..2882d646db15d --- /dev/null +++ b/boards/arm/stm32f3/nucleo-f302r8/src/stm32_highpri.c @@ -0,0 +1,544 @@ +/**************************************************************************** + * boards/arm/stm32f3/nucleo-f302r8/src/stm32_highpri.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include +#include + +#include "arm_internal.h" +#include "ram_vectors.h" + +#include "stm32_pwm.h" +#include "stm32_adc.h" +#include "stm32_dma.h" + +#include + +#ifdef CONFIG_NUCLEOF302R8_HIGHPRI + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +#ifndef CONFIG_ARCH_HIPRI_INTERRUPT +# error CONFIG_ARCH_HIPRI_INTERRUPT is required +#endif + +#ifndef CONFIG_ARCH_RAMVECTORS +# error CONFIG_ARCH_RAMVECTORS is required +#endif + +#ifndef CONFIG_ARCH_IRQPRIO +# error CONFIG_ARCH_IRQPRIO is required +#endif + +#ifndef CONFIG_ARCH_FPU +# warning Set CONFIG_ARCH_FPU for hardware FPU support +#endif + +#ifdef CONFIG_STM32_ADC1_DMA +# if defined(CONFIG_STM32_TIM1_PWM) +# define HIGHPRI_HAVE_TIM1 +# endif +# if (CONFIG_STM32_ADC1_DMA_CFG != 1) +# error ADC1 DMA must be configured in Circular Mode +# endif +# if !defined(HIGHPRI_HAVE_TIM1) +# error "Needs TIM1 to trigger ADC DMA" +# endif +#endif + +#if (CONFIG_STM32_ADC1_INJECTED_CHAN > 0) +# if (CONFIG_STM32_ADC1_INJECTED_CHAN > 2) +# error Max 2 injected channels supported for now +# else +# define HIGHPRI_HAVE_INJECTED +# endif +#endif + +#ifdef HIGHPRI_HAVE_INJECTED +# define INJ_NCHANNELS CONFIG_STM32_ADC1_INJECTED_CHAN +#else +# define INJ_NCHANNELS (0) +#endif + +#ifndef CONFIG_STM32_ADC1_DMA +# define REG_NCHANNELS (1) +#else +# define REG_NCHANNELS (3) +#endif + +#define ADC1_NCHANNELS (REG_NCHANNELS + INJ_NCHANNELS) + +#define DEV1_PORT (1) +#define DEV1_NCHANNELS ADC1_NCHANNELS +#define ADC_REF_VOLTAGE (3.3f) +#define ADC_VAL_MAX (4095) + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/* High priority example private data */ + +struct highpri_s +{ + struct stm32_adc_dev_s *adc1; +#ifdef HIGHPRI_HAVE_TIM1 + struct stm32_pwm_dev_s *pwm; +#endif + volatile uint32_t cntr1; + volatile uint32_t cntr2; + volatile uint8_t current; + uint16_t r_val[REG_NCHANNELS]; + float r_volt[REG_NCHANNELS]; +#ifdef HIGHPRI_HAVE_INJECTED + uint16_t j_val[INJ_NCHANNELS]; + float j_volt[INJ_NCHANNELS]; +#endif + bool lock; +}; + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* ADC channel list */ + +static const uint8_t g_chanlist1[DEV1_NCHANNELS] = +{ + 1, +#ifdef CONFIG_STM32_ADC1_DMA + 2, + 11, +#endif +#if INJ_NCHANNELS > 0 + 7, +#endif +#if INJ_NCHANNELS > 1 + 6 +#endif +}; + +/* Configurations of pins used by ADC channel */ + +static const uint32_t g_pinlist1[DEV1_NCHANNELS] = +{ + GPIO_ADC1_IN1_0, /* PA0/A0 */ +#ifdef CONFIG_STM32_ADC1_DMA + GPIO_ADC1_IN2_0, /* PA1/A1 */ + GPIO_ADC1_IN11_0, /* PB0/A3 */ +#endif +#if INJ_NCHANNELS > 0 + GPIO_ADC1_IN7_0, /* PC1/A4 */ +#endif +#if INJ_NCHANNELS > 1 + GPIO_ADC1_IN6_0 /* PC0/A5 */ +#endif +}; + +static struct highpri_s g_highpri; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: adc12_handler + * + * Description: + * This is the handler for the high speed ADC interrupt. + * + ****************************************************************************/ + +#if !defined(CONFIG_STM32_ADC1_DMA) || defined(HIGHPRI_HAVE_INJECTED) +void adc12_handler(void) +{ + struct stm32_adc_dev_s *adc = g_highpri.adc1; + float ref = ADC_REF_VOLTAGE; + float bit = ADC_VAL_MAX; + uint32_t pending; +#ifdef HIGHPRI_HAVE_INJECTED + int i = 0; +#endif + + /* Get pending ADC interrupts */ + + pending = STM32_ADC_INT_GET(adc); + + if (g_highpri.lock == true) + { + goto irq_out; + } + +#ifndef CONFIG_STM32_ADC1_DMA + /* Regular channel end of conversion */ + + if (pending & ADC_ISR_EOC) + { + /* Increase regular sequence counter */ + + g_highpri.cntr1 += 1; + + /* Get regular data */ + + g_highpri.r_val[g_highpri.current] = STM32_ADC_REGDATA_GET(adc); + + /* Do some floating point operations */ + + g_highpri.r_volt[g_highpri.current] = + (float)g_highpri.r_val[g_highpri.current] * ref / bit; + + if (g_highpri.current >= REG_NCHANNELS - 1) + { + g_highpri.current = 0; + } + else + { + g_highpri.current += 1; + } + } +#endif + +#ifdef HIGHPRI_HAVE_INJECTED + /* Injected channel end of sequence */ + + if (pending & ADC_ISR_JEOS) + { + /* Increase injected sequence counter */ + + g_highpri.cntr2 += 1; + + /* Get injected channels */ + + for (i = 0; i < INJ_NCHANNELS; i += 1) + { + g_highpri.j_val[i] = STM32_ADC_INJDATA_GET(adc, i); + } + + /* Do some floating point operations */ + + for (i = 0; i < INJ_NCHANNELS; i += 1) + { + g_highpri.j_volt[i] = (float)g_highpri.j_val[i] * ref / bit; + } + } +#endif + +irq_out: + + /* Clear ADC pending interrupts */ + + STM32_ADC_INT_ACK(adc, pending); +} +#endif + +/**************************************************************************** + * Name: dmach1_handler + * + * Description: + * This is the handler for the high speed ADC interrupt using DMA transfer. + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_ADC1_DMA +void dma1ch1_handler(void) +{ + float ref = ADC_REF_VOLTAGE; + float bit = ADC_VAL_MAX; + uint32_t pending; + int i; + + pending = stm32_dma_intget(STM32_DMA1_CHAN1); + + if (g_highpri.lock == true) + { + goto irq_out; + } + + /* Increase regular sequence counter */ + + g_highpri.cntr1 += 1; + + for (i = 0; i < REG_NCHANNELS; i += 1) + { + /* Do some floating point operations */ + + g_highpri.r_volt[i] = (float)g_highpri.r_val[i] * ref / bit; + } + +irq_out: + + /* Clear DMA pending interrupts */ + + stm32_dma_intack(STM32_DMA1_CHAN1, pending); +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: highpri_main + * + * Description: + * Main entry point in into the high priority interrupt test. + * + ****************************************************************************/ + +int highpri_main(int argc, char *argv[]) +{ +#ifdef HIGHPRI_HAVE_TIM1 + struct stm32_pwm_dev_s *pwm1; +#endif + struct adc_dev_s *adc1; + struct highpri_s *highpri; + int ret; + int i; + + highpri = &g_highpri; + + /* Initialize highpri structure */ + + memset(highpri, 0, sizeof(struct highpri_s)); + + printf("\nhighpri_main: Started\n"); + + /* Configure the pins as analog inputs for the selected channels */ + + for (i = 0; i < DEV1_NCHANNELS; i++) + { + stm32_configgpio(g_pinlist1[i]); + } + + /* Initialize ADC driver */ + + adc1 = stm32_adcinitialize(DEV1_PORT, g_chanlist1, DEV1_NCHANNELS); + if (adc1 == NULL) + { + aerr("ERROR: Failed to get ADC interface 1\n"); + ret = EXIT_FAILURE; + goto errout; + } + + highpri->adc1 = (struct stm32_adc_dev_s *)adc1->ad_priv; + +#ifdef HIGHPRI_HAVE_TIM1 + /* Initialize TIM1 */ + + pwm1 = (struct stm32_pwm_dev_s *) stm32_pwminitialize(1); + if (pwm1 == NULL) + { + printf("ERROR: Failed to get PWM1 interface\n"); + ret = EXIT_FAILURE; + goto errout; + } + + highpri->pwm = pwm1; + + /* Setup PWM device */ + + PWM_SETUP(pwm1); + + /* Set timer frequency */ + + PWM_FREQ_UPDATE(pwm1, 1000); + + /* Set CCR1 */ + + PWM_CCR_UPDATE(pwm1, 1, 0x0f00); + + /* Enable TIM1 OUT1 */ + + PWM_OUTPUTS_ENABLE(pwm1, STM32_PWM_OUT1, true); + +#ifdef CONFIG_DEBUG_PWM_INFO + /* Print debug */ + + PWM_DUMP_REGS(pwm1); +#endif + +#endif /* HIGHPRI_HAVE_TIM1 */ + +#if !defined(CONFIG_STM32_ADC1_DMA) || defined(HIGHPRI_HAVE_INJECTED) + /* Attach ADC12 ram vector if no DMA or injected channels support */ + + ret = arm_ramvec_attach(STM32_IRQ_ADC12, adc12_handler); + if (ret < 0) + { + fprintf(stderr, "highpri_main: ERROR: arm_ramvec_attach failed: %d\n", + ret); + ret = EXIT_FAILURE; + goto errout; + } + + /* Set the priority of the ADC12 interrupt vector */ + + ret = up_prioritize_irq(STM32_IRQ_ADC12, NVIC_SYSH_HIGH_PRIORITY); + if (ret < 0) + { + fprintf(stderr, "highpri_main: ERROR: up_prioritize_irq failed: %d\n", + ret); + ret = EXIT_FAILURE; + goto errout; + } + + up_enable_irq(STM32_IRQ_ADC12); +#endif + +#ifdef CONFIG_STM32_ADC1_DMA + /* Attach DMA1 CH1 ram vector if DMA */ + + ret = arm_ramvec_attach(STM32_IRQ_DMA1CH1, dma1ch1_handler); + if (ret < 0) + { + fprintf(stderr, "highpri_main: ERROR: arm_ramvec_attach failed: %d\n", + ret); + ret = EXIT_FAILURE; + goto errout; + } + + /* Set the priority of the DMA1CH1 interrupt vector */ + + ret = up_prioritize_irq(STM32_IRQ_DMA1CH1, NVIC_SYSH_HIGH_PRIORITY); + if (ret < 0) + { + fprintf(stderr, "highpri_main: ERROR: up_prioritize_irq failed: %d\n", + ret); + ret = EXIT_FAILURE; + goto errout; + } + + up_enable_irq(STM32_IRQ_DMA1CH1); +#endif + + /* Setup ADC hardware */ + + adc1->ad_ops->ao_setup(adc1); + + /* Configure regular channels trigger to T1CC1 */ + + STM32_ADC_EXTCFG_SET(highpri->adc1, + ADC1_EXTSEL_T1CC1 | ADC_EXTREG_EXTEN_DEFAULT); + +#ifndef CONFIG_STM32_ADC1_DMA + /* Enable ADC regular conversion interrupts if no DMA */ + + STM32_ADC_INT_ENABLE(highpri->adc1, ADC_IER_EOC); +#else + /* Register ADC buffer for DMA transfer */ + + STM32_ADC_REGBUF_REGISTER(highpri->adc1, g_highpri.r_val, REG_NCHANNELS); +#endif + +#ifdef HIGHPRI_HAVE_INJECTED + /* Enable ADC injected sequence end interrupts */ + + STM32_ADC_INT_ENABLE(highpri->adc1, ADC_IER_JEOS); +#endif + +#ifdef HIGHPRI_HAVE_TIM1 + /* Enable timer counter after ADC configuration */ + + PWM_TIM_ENABLE(pwm1, true); +#endif + + while (1) + { +#ifndef CONFIG_STM32_ADC1_DMA + /* Software trigger for regular sequence */ + + adc1->ad_ops->ao_ioctl(adc1, IO_TRIGGER_REG, 0); + + nxsched_usleep(100); +#endif + +#ifdef HIGHPRI_HAVE_INJECTED + /* Software trigger for injected sequence */ + + adc1->ad_ops->ao_ioctl(adc1, IO_TRIGGER_INJ, 0); + + nxsched_usleep(100); +#endif + /* Lock global data */ + + g_highpri.lock = true; + +#ifndef CONFIG_STM32_ADC1_DMA + printf("%" PRId32 " [%d] %0.3fV\n", g_highpri.cntr1, g_highpri.current, + g_highpri.r_volt[g_highpri.current]); +#else + printf("%" PRId32 " ", g_highpri.cntr1); + + for (i = 0; i < REG_NCHANNELS; i += 1) + { + printf("r:[%d] %0.3fV, ", i, g_highpri.r_volt[i]); + } + + printf("\n"); +#endif + +#ifdef HIGHPRI_HAVE_INJECTED + /* Print data from injected channels */ + + printf("%" PRId32 " ", g_highpri.cntr2); + + for (i = 0; i < INJ_NCHANNELS; i += 1) + { + printf("j:[%d] %0.3fV, ", i, g_highpri.j_volt[i]); + } + + printf("\n"); +#endif + /* Unlock global data */ + + g_highpri.lock = false; + + nxsched_sleep(1); + } + +errout: + return ret; +} + +#endif /* CONFIG_NUCLEOF302R8_HIGHPRI */ diff --git a/boards/arm/stm32f3/nucleo-f302r8/src/stm32_pwm.c b/boards/arm/stm32f3/nucleo-f302r8/src/stm32_pwm.c new file mode 100644 index 0000000000000..3270dce669b6c --- /dev/null +++ b/boards/arm/stm32f3/nucleo-f302r8/src/stm32_pwm.c @@ -0,0 +1,110 @@ +/**************************************************************************** + * boards/arm/stm32f3/nucleo-f302r8/src/stm32_pwm.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32_pwm.h" +#include "nucleo-f302r8.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +#define HAVE_PWM 1 + +#ifndef CONFIG_PWM +# undef HAVE_PWM +#endif + +#ifndef CONFIG_STM32_TIM1 +# undef HAVE_PWM +#endif + +#ifndef CONFIG_STM32_TIM1_PWM +# undef HAVE_PWM +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_pwm_setup + * + * Description: + * Initialize PWM and register the PWM device. + * + ****************************************************************************/ + +int stm32_pwm_setup(void) +{ +#ifdef HAVE_PWM + static bool initialized = false; + struct pwm_lowerhalf_s *pwm; + int ret; + + /* Have we already initialized? */ + + if (!initialized) + { + /* Call stm32_pwminitialize() to get an instance of the PWM interface */ + + pwm = stm32_pwminitialize(NUCLEOF302R8_PWMTIMER); + if (!pwm) + { + tmrerr("ERROR: Failed to get the STM32 PWM lower half\n"); + return -ENODEV; + } + + /* Register the PWM driver at "/dev/pwm0" */ + + ret = pwm_register("/dev/pwm0", pwm); + if (ret < 0) + { + tmrerr("ERROR: pwm_register failed: %d\n", ret); + return ret; + } + + /* Now we are initialized */ + + initialized = true; + } + + return OK; +#else + return -ENODEV; +#endif +} diff --git a/boards/arm/stm32f3/nucleo-f302r8/src/stm32_userleds.c b/boards/arm/stm32f3/nucleo-f302r8/src/stm32_userleds.c new file mode 100644 index 0000000000000..5b5c35cf20d09 --- /dev/null +++ b/boards/arm/stm32f3/nucleo-f302r8/src/stm32_userleds.c @@ -0,0 +1,77 @@ +/**************************************************************************** + * boards/arm/stm32f3/nucleo-f302r8/src/stm32_userleds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include + +#include "stm32.h" +#include "nucleo-f302r8.h" + +#ifndef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_userled_initialize + ****************************************************************************/ + +uint32_t board_userled_initialize(void) +{ + /* Configure LED1 GPIO for output */ + + stm32_configgpio(GPIO_LED1); + return BOARD_NLEDS; +} + +/**************************************************************************** + * Name: board_userled + ****************************************************************************/ + +void board_userled(int led, bool ledon) +{ + if (led == BOARD_LED1) + { + stm32_gpiowrite(GPIO_LED1, ledon); + } +} + +/**************************************************************************** + * Name: board_userled_all + ****************************************************************************/ + +void board_userled_all(uint32_t ledset) +{ + stm32_gpiowrite(GPIO_LED1, (ledset & BOARD_LED1_BIT) != 0); +} + +#endif /* !CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32f3/nucleo-f303re/CMakeLists.txt b/boards/arm/stm32f3/nucleo-f303re/CMakeLists.txt new file mode 100644 index 0000000000000..98d4d6771d75e --- /dev/null +++ b/boards/arm/stm32f3/nucleo-f303re/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32f3/nucleo-f303re/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/arm/stm32/nucleo-f303re/Kconfig b/boards/arm/stm32f3/nucleo-f303re/Kconfig similarity index 100% rename from boards/arm/stm32/nucleo-f303re/Kconfig rename to boards/arm/stm32f3/nucleo-f303re/Kconfig diff --git a/boards/arm/stm32f3/nucleo-f303re/configs/adc/defconfig b/boards/arm/stm32f3/nucleo-f303re/configs/adc/defconfig new file mode 100644 index 0000000000000..800369214a2b5 --- /dev/null +++ b/boards/arm/stm32f3/nucleo-f303re/configs/adc/defconfig @@ -0,0 +1,48 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +CONFIG_ADC=y +CONFIG_ANALOG=y +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nucleo-f303re" +CONFIG_ARCH_BOARD_NUCLEO_F303RE=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f3" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F303RE=y +CONFIG_ARCH_CHIP_STM32F3=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=6522 +CONFIG_BUILTIN=y +CONFIG_EXAMPLES_ADC=y +CONFIG_EXAMPLES_ADC_GROUPSIZE=3 +CONFIG_EXAMPLES_ADC_SWTRIG=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=65536 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=27 +CONFIG_START_YEAR=2013 +CONFIG_STM32_ADC1=y +CONFIG_STM32_ADC1_DMA=y +CONFIG_STM32_ADC3=y +CONFIG_STM32_DMA1=y +CONFIG_STM32_FORCEPOWER=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_TIM1=y +CONFIG_STM32_TIM1_ADC=y +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f3/nucleo-f303re/configs/can/defconfig b/boards/arm/stm32f3/nucleo-f303re/configs/can/defconfig new file mode 100644 index 0000000000000..464b73deff777 --- /dev/null +++ b/boards/arm/stm32f3/nucleo-f303re/configs/can/defconfig @@ -0,0 +1,40 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_DEV_CONSOLE is not set +# CONFIG_SERIAL is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nucleo-f303re" +CONFIG_ARCH_BOARD_NUCLEO_F303RE=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f3" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F303RE=y +CONFIG_ARCH_CHIP_STM32F3=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL=y +CONFIG_BOARD_LOOPSPERMSEC=6522 +CONFIG_EXAMPLES_CAN=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_INIT_ENTRYPOINT="can_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_MM_REGIONS=2 +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=65536 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=27 +CONFIG_START_YEAR=2013 +CONFIG_STM32_CAN1=y +CONFIG_STM32_CAN_TSEG1=15 +CONFIG_STM32_CAN_TSEG2=2 +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_SYSLOG_NONE=y +CONFIG_TASK_NAME_SIZE=0 diff --git a/boards/arm/stm32f3/nucleo-f303re/configs/hello/defconfig b/boards/arm/stm32f3/nucleo-f303re/configs/hello/defconfig new file mode 100644 index 0000000000000..e8470d5fdbdcb --- /dev/null +++ b/boards/arm/stm32f3/nucleo-f303re/configs/hello/defconfig @@ -0,0 +1,36 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nucleo-f303re" +CONFIG_ARCH_BOARD_NUCLEO_F303RE=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f3" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F303RE=y +CONFIG_ARCH_CHIP_STM32F3=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=6522 +CONFIG_DEBUG_SYMBOLS=y +CONFIG_EXAMPLES_HELLO=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_INIT_ENTRYPOINT="hello_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_MM_REGIONS=2 +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=65536 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=27 +CONFIG_START_YEAR=2013 +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_USART2=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f3/nucleo-f303re/configs/nsh/defconfig b/boards/arm/stm32f3/nucleo-f303re/configs/nsh/defconfig new file mode 100644 index 0000000000000..4b5ead9b89fa8 --- /dev/null +++ b/boards/arm/stm32f3/nucleo-f303re/configs/nsh/defconfig @@ -0,0 +1,36 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nucleo-f303re" +CONFIG_ARCH_BOARD_NUCLEO_F303RE=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f3" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F303RE=y +CONFIG_ARCH_CHIP_STM32F3=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=6522 +CONFIG_DEBUG_SYMBOLS=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_MM_REGIONS=2 +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=65536 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=27 +CONFIG_START_YEAR=2013 +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f3/nucleo-f303re/configs/nxlines/defconfig b/boards/arm/stm32f3/nucleo-f303re/configs/nxlines/defconfig new file mode 100644 index 0000000000000..6c5fbbe4e1c31 --- /dev/null +++ b/boards/arm/stm32f3/nucleo-f303re/configs/nxlines/defconfig @@ -0,0 +1,48 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_DEV_CONSOLE is not set +# CONFIG_NXFONTS_DISABLE_16BPP is not set +# CONFIG_NX_DISABLE_16BPP is not set +# CONFIG_SERIAL is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nucleo-f303re" +CONFIG_ARCH_BOARD_NUCLEO_F303RE=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f3" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F303RE=y +CONFIG_ARCH_CHIP_STM32F3=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=6522 +CONFIG_CAN=y +CONFIG_EXAMPLES_NXLINES=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_INIT_ENTRYPOINT="nxlines_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LCD=y +CONFIG_LCD_SSD1351=y +CONFIG_MM_REGIONS=2 +CONFIG_MQ_MAXMSGSIZE=64 +CONFIG_NX=y +CONFIG_NXFONT_MONO5X8=y +CONFIG_NXSTART_EXTERNINIT=y +CONFIG_NX_BLOCKING=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAMLOG=y +CONFIG_RAMLOG_SYSLOG=y +CONFIG_RAM_SIZE=65536 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=27 +CONFIG_START_YEAR=2013 +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_SPI1=y +CONFIG_TASK_NAME_SIZE=0 diff --git a/boards/arm/stm32f3/nucleo-f303re/configs/pwm/defconfig b/boards/arm/stm32f3/nucleo-f303re/configs/pwm/defconfig new file mode 100644 index 0000000000000..e6ef3644349bf --- /dev/null +++ b/boards/arm/stm32f3/nucleo-f303re/configs/pwm/defconfig @@ -0,0 +1,47 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nucleo-f303re" +CONFIG_ARCH_BOARD_NUCLEO_F303RE=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f3" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F303RE=y +CONFIG_ARCH_CHIP_STM32F3=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=6522 +CONFIG_BUILTIN=y +CONFIG_EXAMPLES_PWM=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_MM_REGIONS=2 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_PWM=y +CONFIG_PWM_NCHANNELS=2 +CONFIG_RAM_SIZE=65536 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=27 +CONFIG_START_YEAR=2013 +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_PWM_MULTICHAN=y +CONFIG_STM32_TIM3=y +CONFIG_STM32_TIM3_CH1OUT=y +CONFIG_STM32_TIM3_CH2OUT=y +CONFIG_STM32_TIM3_CHANNEL1=y +CONFIG_STM32_TIM3_CHANNEL2=y +CONFIG_STM32_TIM3_PWM=y +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f3/nucleo-f303re/configs/serialrx/defconfig b/boards/arm/stm32f3/nucleo-f303re/configs/serialrx/defconfig new file mode 100644 index 0000000000000..cdfbb2e02b01b --- /dev/null +++ b/boards/arm/stm32f3/nucleo-f303re/configs/serialrx/defconfig @@ -0,0 +1,39 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_DEV_CONSOLE is not set +CONFIG_ANALOG=y +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nucleo-f303re" +CONFIG_ARCH_BOARD_NUCLEO_F303RE=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f3" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F303RE=y +CONFIG_ARCH_CHIP_STM32F3=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL=y +CONFIG_BOARD_LOOPSPERMSEC=6522 +CONFIG_EXAMPLES_SERIALRX=y +CONFIG_EXAMPLES_SERIALRX_PRINTSTR=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_INIT_ENTRYPOINT="serialrx_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_MM_REGIONS=2 +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=65536 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=27 +CONFIG_START_YEAR=2013 +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_UART4=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_UART4_BAUD=9600 diff --git a/boards/arm/stm32f3/nucleo-f303re/include/board.h b/boards/arm/stm32f3/nucleo-f303re/include/board.h new file mode 100644 index 0000000000000..a27906b0a72a9 --- /dev/null +++ b/boards/arm/stm32f3/nucleo-f303re/include/board.h @@ -0,0 +1,241 @@ +/**************************************************************************** + * boards/arm/stm32f3/nucleo-f303re/include/board.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_STM32_NUCLEO_F303RE_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32_NUCLEO_F303RE_INCLUDE_BOARD_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#ifndef __ASSEMBLY__ +# include +# include +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Clocking *****************************************************************/ + +/* HSI - Internal 8 MHz RC Oscillator + * LSI - 32 KHz RC + * HSE - 8 MHz from MCO output of ST-LINK + * LSE - 32.768 kHz + */ + +#define STM32_BOARD_XTAL 8000000ul /* X1 on board */ + +#define STM32_HSEBYP_ENABLE +#define STM32_HSI_FREQUENCY 8000000ul +#define STM32_LSI_FREQUENCY 40000 /* Between 30kHz and 60kHz */ +#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL +#define STM32_LSE_FREQUENCY 32768 /* X2 on board */ + +/* PLL source is HSE/1, + * PLL multiplier is 9: + * PLL frequency is 8MHz (XTAL) x 9 = 72MHz + */ + +#define STM32_CFGR_PLLSRC RCC_CFGR_PLLSRC +#define STM32_CFGR_PLLXTPRE 0 +#define STM32_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx9 +#define STM32_PLL_FREQUENCY (9*STM32_BOARD_XTAL) + +/* Use the PLL and set the SYSCLK source to be the PLL */ + +#define STM32_SYSCLK_SW RCC_CFGR_SW_PLL +#define STM32_SYSCLK_SWS RCC_CFGR_SWS_PLL +#define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY + +/* AHB clock (HCLK) is SYSCLK (72MHz) */ + +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY + +/* APB2 clock (PCLK2) is HCLK (72MHz) */ + +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK +#define STM32_PCLK2_FREQUENCY STM32_HCLK_FREQUENCY +#define STM32_APB2_CLKIN (STM32_PCLK2_FREQUENCY) /* Timers 1 and 8, 15-17 */ + +/* APB2 timers 1 and 8, 15-17 will receive PCLK2. */ + +/* Timers driven from APB2 will be PCLK2 */ + +#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB1_TIM15_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB1_TIM16_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB1_TIM17_CLKIN (STM32_PCLK2_FREQUENCY) + +/* APB1 clock (PCLK1) is HCLK/2 (36MHz) */ + +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd2 +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/2) + +/* APB1 timers 2-7 will be twice PCLK1 */ + +#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) + +/* USB divider -- Divide PLL clock by 1.5 */ + +#define STM32_CFGR_USBPRE 0 + +/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx + * otherwise frequency is 2xAPBx. + * Note: TIM1,8 are on APB2, others on APB1 + */ + +#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM2_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM3_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM4_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM5_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM6_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM7_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY + +/* LED definitions **********************************************************/ + +/* The Nucleo F303RE board has three LEDs. Two of these are controlled by + * logic on the board and are not available for software control: + * + * LD1 COM: LD1 default status is red. LD1 turns to green to indicate that + * communications are in progress between the PC and the + * ST-LINK/V2-1. + * LD3 PWR: red LED indicates that the board is powered. + * + * And one can be controlled by software: + * + * User LD2: green LED is a user LED connected to the I/O PA5 of the + * STM32F303RET6. + * + * If CONFIG_ARCH_LEDS is not defined, then the user can control the LED in + * any way. The following definition is used to access the LED. + */ + +/* LED index values for use with board_userled() */ + +#define BOARD_LED1 0 /* User LD2 */ +#define BOARD_NLEDS 1 + +/* LED bits for use with board_userled_all() */ + +#define BOARD_LED1_BIT (1 << BOARD_LED1) + +/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the LED on board + * the Nucleo F303RE. The following definitions describe how NuttX controls + * the LED: + * + * SYMBOL Meaning LED1 state + * ------------------ ----------------------- ---------- + * LED_STARTED NuttX has been started OFF + * LED_HEAPALLOCATE Heap has been allocated OFF + * LED_IRQSENABLED Interrupts enabled OFF + * LED_STACKCREATED Idle stack created ON + * LED_INIRQ In an interrupt No change + * LED_SIGNAL In a signal handler No change + * LED_ASSERTION An assertion failed No change + * LED_PANIC The system has crashed Blinking + * LED_IDLE STM32 is in sleep mode Not used + */ + +#define LED_STARTED 0 +#define LED_HEAPALLOCATE 0 +#define LED_IRQSENABLED 0 +#define LED_STACKCREATED 1 +#define LED_INIRQ 2 +#define LED_SIGNAL 2 +#define LED_ASSERTION 2 +#define LED_PANIC 1 + +/* Button definitions *******************************************************/ + +/* The Nucleo F303RE supports two buttons; only one button is controllable + * by software: + * + * B1 USER: user button connected to the I/O PC13 of the STM32F303RET6. + * B2 RESET: push button connected to NRST is used to RESET the + * STM32F303RET6. + */ + +#define BUTTON_USER 0 +#define NUM_BUTTONS 1 + +#define BUTTON_USER_BIT (1 << BUTTON_USER) + +/* Alternate function pin selections ****************************************/ + +/* CAN */ + +#define GPIO_CAN1_RX (GPIO_CAN_RX_2|GPIO_SPEED_25MHz) +#define GPIO_CAN1_TX (GPIO_CAN_TX_2|GPIO_SPEED_25MHz) + +/* I2C */ + +#define GPIO_I2C1_SCL (GPIO_I2C1_SCL_3|GPIO_SPEED_50MHz) +#define GPIO_I2C1_SDA (GPIO_I2C1_SDA_3|GPIO_SPEED_50MHz) + +/* SPI */ + +#define GPIO_SPI1_MISO GPIO_SPI1_MISO_1 +#define GPIO_SPI1_MOSI GPIO_SPI1_MOSI_1 +#define GPIO_SPI1_SCK GPIO_SPI1_SCK_1 + +/* TIM */ + +#define GPIO_TIM2_CH2OUT (GPIO_TIM2_CH2OUT_2|GPIO_SPEED_50MHz) +#define GPIO_TIM2_CH3OUT (GPIO_TIM2_CH3OUT_3|GPIO_SPEED_50MHz) + +#define GPIO_TIM3_CH1OUT (GPIO_TIM3_CH1OUT_2|GPIO_SPEED_50MHz) +#define GPIO_TIM3_CH2OUT (GPIO_TIM3_CH2OUT_4|GPIO_SPEED_50MHz) + +#define GPIO_TIM4_CH1OUT (GPIO_TIM4_CH1OUT_2|GPIO_SPEED_50MHz) + +/* USART */ + +#define GPIO_USART2_RX (GPIO_USART2_RX_2|GPIO_SPEED_50MHz) +#define GPIO_USART2_TX (GPIO_USART2_TX_2|GPIO_SPEED_50MHz) + +/* UART4 */ + +#define GPIO_UART4_RX (GPIO_UART4_RX_0|GPIO_SPEED_50MHz) +#define GPIO_UART4_TX (GPIO_UART4_TX_0|GPIO_SPEED_50MHz) + +/* DMA channels *************************************************************/ + +/* ADC */ + +#define ADC1_DMA_CHAN DMACHAN_ADC1 +#define ADC2_DMA_CHAN DMACHAN_ADC2_1 +#define ADC3_DMA_CHAN DMACHAN_ADC3 +#define ADC4_DMA_CHAN DMACHAN_ADC4_1 + +#endif /* __BOARDS_ARM_STM32_NUCLEO_F303RE_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32f3/nucleo-f303re/scripts/Make.defs b/boards/arm/stm32f3/nucleo-f303re/scripts/Make.defs new file mode 100644 index 0000000000000..8d2299c83d6d5 --- /dev/null +++ b/boards/arm/stm32f3/nucleo-f303re/scripts/Make.defs @@ -0,0 +1,41 @@ +############################################################################ +# boards/arm/stm32f3/nucleo-f303re/scripts/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/.config +include $(TOPDIR)/tools/Config.mk +include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs + +LDSCRIPT = ld.script +ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) + +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32f3/nucleo-f303re/scripts/ld.script b/boards/arm/stm32f3/nucleo-f303re/scripts/ld.script new file mode 100644 index 0000000000000..49e73ee56d140 --- /dev/null +++ b/boards/arm/stm32f3/nucleo-f303re/scripts/ld.script @@ -0,0 +1,121 @@ +/**************************************************************************** + * boards/arm/stm32f3/nucleo-f303re/scripts/ld.script + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* The STM32F303RET6 has 512Kb of FLASH beginning at address 0x0800:0000 and + * 64Kb of SRAM. + * + * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 + * where the code expects to begin execution by jumping to the entry point in + * the 0x0800:0000 address range. + */ + +MEMORY +{ + flash (rx) : ORIGIN = 0x08000000, LENGTH = 512K + sram (rwx) : ORIGIN = 0x20000000, LENGTH = 64K +} + +OUTPUT_ARCH(arm) +EXTERN(_vectors) +ENTRY(_stext) +SECTIONS +{ + .text : { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > flash + + .init_section : ALIGN(4) { + _sinit = ABSOLUTE(.); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) + _einit = ABSOLUTE(.); + } > flash + + .ARM.extab : ALIGN(4) { + *(.ARM.extab*) + } > flash + + .ARM.exidx : ALIGN(4) { + __exidx_start = ABSOLUTE(.); + *(.ARM.exidx*) + __exidx_end = ABSOLUTE(.); + } > flash + + .tdata : { + _stdata = ABSOLUTE(.); + *(.tdata .tdata.* .gnu.linkonce.td.*); + _etdata = ABSOLUTE(.); + } > flash + + .tbss : { + _stbss = ABSOLUTE(.); + *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); + _etbss = ABSOLUTE(.); + } > flash + + _eronly = ABSOLUTE(.); + + .data : ALIGN(4) { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > sram AT > flash + + .bss : ALIGN(4) { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + _ebss = ABSOLUTE(.); + } > sram + + /* Stabs debugging sections. */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/stm32f3/nucleo-f303re/src/CMakeLists.txt b/boards/arm/stm32f3/nucleo-f303re/src/CMakeLists.txt new file mode 100644 index 0000000000000..1388c1f7d1eda --- /dev/null +++ b/boards/arm/stm32f3/nucleo-f303re/src/CMakeLists.txt @@ -0,0 +1,69 @@ +# ############################################################################## +# boards/arm/stm32f3/nucleo-f303re/src/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(SRCS stm32_boot.c) + +if(CONFIG_ARCH_LEDS) + list(APPEND SRCS stm32_autoleds.c) +else() + list(APPEND SRCS stm32_userleds.c) +endif() + +if(CONFIG_ARCH_BUTTONS) + list(APPEND SRCS stm32_buttons.c) +endif() + +if(CONFIG_ADC) + list(APPEND SRCS stm32_adc.c) +endif() + +if(CONFIG_STM32_CAN_CHARDRIVER) + list(APPEND SRCS stm32_can.c) +endif() + +if(CONFIG_DAC) + list(APPEND SRCS stm32_dac.c) +endif() + +if(CONFIG_PWM) + list(APPEND SRCS stm32_pwm.c) +endif() + +if(CONFIG_SPI) + list(APPEND SRCS stm32_spi.c) +endif() + +if(CONFIG_LCD_SSD1351) + list(APPEND SRCS stm32_ssd1351.c) +endif() + +if(CONFIG_TIMER) + list(APPEND SRCS stm32_timer.c) +endif() + +if(CONFIG_BOARDCTL_UNIQUEID) + list(APPEND SRCS stm32_uid.c) +endif() + +target_sources(board PRIVATE ${SRCS}) + +set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/ld.script") diff --git a/boards/arm/stm32f3/nucleo-f303re/src/Make.defs b/boards/arm/stm32f3/nucleo-f303re/src/Make.defs new file mode 100644 index 0000000000000..d65a5d39ac5b2 --- /dev/null +++ b/boards/arm/stm32f3/nucleo-f303re/src/Make.defs @@ -0,0 +1,71 @@ +############################################################################ +# boards/arm/stm32f3/nucleo-f303re/src/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +CSRCS = stm32_boot.c + +ifeq ($(CONFIG_ARCH_LEDS),y) +CSRCS += stm32_autoleds.c +else +CSRCS += stm32_userleds.c +endif + +ifeq ($(CONFIG_ARCH_BUTTONS),y) +CSRCS += stm32_buttons.c +endif + +ifeq ($(CONFIG_ADC),y) +CSRCS += stm32_adc.c +endif + +ifeq ($(CONFIG_STM32_CAN_CHARDRIVER),y) +CSRCS += stm32_can.c +endif + +ifeq ($(CONFIG_DAC),y) +CSRCS += stm32_dac.c +endif + +ifeq ($(CONFIG_PWM),y) +CSRCS += stm32_pwm.c +endif + +ifeq ($(CONFIG_SPI),y) +CSRCS += stm32_spi.c +endif + +ifeq ($(CONFIG_LCD_SSD1351),y) +CSRCS += stm32_ssd1351.c +endif + +ifeq ($(CONFIG_TIMER),y) +CSRCS += stm32_timer.c +endif + +ifeq ($(CONFIG_BOARDCTL_UNIQUEID),y) +CSRCS += stm32_uid.c +endif + +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/nucleo-f303re/src/nucleo-f303re.h b/boards/arm/stm32f3/nucleo-f303re/src/nucleo-f303re.h similarity index 99% rename from boards/arm/stm32/nucleo-f303re/src/nucleo-f303re.h rename to boards/arm/stm32f3/nucleo-f303re/src/nucleo-f303re.h index bcd7bb841769a..01ce746a80522 100644 --- a/boards/arm/stm32/nucleo-f303re/src/nucleo-f303re.h +++ b/boards/arm/stm32f3/nucleo-f303re/src/nucleo-f303re.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f303re/src/nucleo-f303re.h + * boards/arm/stm32f3/nucleo-f303re/src/nucleo-f303re.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f3/nucleo-f303re/src/stm32_adc.c b/boards/arm/stm32f3/nucleo-f303re/src/stm32_adc.c new file mode 100644 index 0000000000000..8031cccfaeeaa --- /dev/null +++ b/boards/arm/stm32f3/nucleo-f303re/src/stm32_adc.c @@ -0,0 +1,374 @@ +/**************************************************************************** + * boards/arm/stm32f3/nucleo-f303re/src/stm32_adc.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "stm32.h" + +#if defined(CONFIG_ADC) && \ + (defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) || \ + defined(CONFIG_STM32_ADC3) || defined(CONFIG_STM32_ADC4)) + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +#if (defined(CONFIG_STM32_ADC1) && defined(CONFIG_STM32_ADC2)) || \ + (defined(CONFIG_STM32_ADC3) && defined(CONFIG_STM32_ADC4)) +# error "will not work with this combination of ADCs" +#endif + +/* 1 or 2 ADC devices (DEV1, DEV2) */ + +#if defined(CONFIG_STM32_ADC1) +# define DEV1_PORT 1 +#endif + +#if defined(CONFIG_STM32_ADC2) +# if defined(DEV1_PORT) +# define DEV2_PORT 2 +# else +# define DEV1_PORT 2 +# endif +#endif + +#if defined(CONFIG_STM32_ADC3) +# if defined(DEV2_PORT) +# error "Choose maximum two of ADC1, ADC2, ADC3, ADC4" +# else +# if defined(DEV1_PORT) +# define DEV2_PORT 3 +# else +# define DEV1_PORT 3 +# endif +# endif +#endif + +#if defined(CONFIG_STM32_ADC4) +# if defined(DEV2_PORT) +# error "Choose maximum two of ADC1, ADC2, ADC3, ADC4" +# else +# if defined(DEV1_PORT) +# define DEV2_PORT 4 +# else +# define DEV1_PORT 4 +# endif +# endif +#endif + +/* The number of ADC channels in the conversion list */ + +/* TODO DMA */ + +#define ADC1_NCHANNELS 4 +#define ADC2_NCHANNELS 3 +#define ADC3_NCHANNELS 3 +#define ADC4_NCHANNELS 1 + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* DEV 1 */ + +#if DEV1_PORT == 1 + +#define DEV1_NCHANNELS ADC1_NCHANNELS + +/* Identifying number of each ADC channel (even if NCHANNELS is less ) */ + +static const uint8_t g_chanlist1[4] = +{ + 1, + 2, + 6, + 7, +}; + +/* Configurations of pins used by each ADC channel */ + +static const uint32_t g_pinlist1[4] = +{ + GPIO_ADC1_IN1_0, + GPIO_ADC1_IN2_0, + GPIO_ADC1_IN6_0, + GPIO_ADC1_IN7_0 +}; + +#elif DEV1_PORT == 2 + +#define DEV1_NCHANNELS ADC2_NCHANNELS + +/* Identifying number of each ADC channel */ + +static const uint8_t g_chanlist1[3] = +{ + 1, + 3, + 4 +}; + +/* Configurations of pins used by each ADC channel */ + +static const uint32_t g_pinlist1[3] = +{ + GPIO_ADC2_IN1_0, + GPIO_ADC2_IN3_0, + GPIO_ADC2_IN4_0 +}; + +#elif DEV1_PORT == 3 + +#define DEV1_NCHANNELS ADC3_NCHANNELS + +/* Identifying number of each ADC channel */ + +static const uint8_t g_chanlist1[3] = +{ + 1, + 5, + 12 +}; + +/* Configurations of pins used by each ADC channel */ + +static const uint32_t g_pinlist1[3] = +{ + GPIO_ADC3_IN1_0, + GPIO_ADC3_IN5_0, + GPIO_ADC3_IN12_0 +}; + +#elif DEV1_PORT == 4 + +#define DEV1_NCHANNELS ADC4_NCHANNELS + +/* Identifying number of each ADC channel */ + +static const uint8_t g_chanlist1[1] = +{ + 3 +}; + +/* Configurations of pins used by each ADC channel */ + +static const uint32_t g_pinlist1[1] = +{ + GPIO_ADC4_IN3_0 +}; + +#endif + +#ifdef DEV2_PORT + +/* DEV 2 */ + +#if DEV2_PORT == 1 + +#define DEV2_NCHANNELS ADC1_NCHANNELS + +/* Identifying number of each ADC channel (even if NCHANNELS is less ) */ + +static const uint8_t g_chanlist2[4] = +{ + 1, + 2, + 6, + 7 +}; + +/* Configurations of pins used by each ADC channel */ + +static const uint32_t g_pinlist2[4] = +{ + GPIO_ADC1_IN1_0, + GPIO_ADC1_IN2_0, + GPIO_ADC1_IN6_0, + GPIO_ADC1_IN7_0 +}; + +#elif DEV2_PORT == 2 + +#define DEV2_NCHANNELS ADC2_NCHANNELS + +/* Identifying number of each ADC channel */ + +static const uint8_t g_chanlist2[3] = +{ + 1, + 3, + 4 +}; + +/* Configurations of pins used by each ADC channel */ + +static const uint32_t g_pinlist2[3] = +{ + GPIO_ADC2_IN1_0, + GPIO_ADC2_IN3_0, + GPIO_ADC2_IN4_0 +}; + +#elif DEV2_PORT == 3 + +#define DEV2_NCHANNELS ADC3_NCHANNELS + +/* Identifying number of each ADC channel */ + +static const uint8_t g_chanlist2[3] = +{ + 1, + 5, + 12 +}; + +/* Configurations of pins used by each ADC channel */ + +static const uint32_t g_pinlist2[3] = +{ + GPIO_ADC3_IN1_0, + GPIO_ADC3_IN5_0, + GPIO_ADC3_IN12_0 +}; + +#elif DEV2_PORT == 4 + +#define DEV2_NCHANNELS ADC4_NCHANNELS + +/* Identifying number of each ADC channel */ + +static const uint8_t g_chanlist2[1] = +{ + 3 +}; + +/* Configurations of pins used by each ADC channel */ + +static const uint32_t g_pinlist2[1] = +{ + GPIO_ADC4_IN3_0 +}; + +#endif +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_adc_setup + * + * Description: + * Initialize ADC and register the ADC driver. + * + ****************************************************************************/ + +int stm32_adc_setup(void) +{ + struct adc_dev_s *adc; + int ret; + int i; + + /* DEV1 */ + + /* Configure the pins as analog inputs for the selected channels */ + + for (i = 0; i < DEV1_NCHANNELS; i++) + { + stm32_configgpio(g_pinlist1[i]); + } + + /* Call stm32_adcinitialize() to get an instance of the ADC interface */ + + adc = stm32_adcinitialize(DEV1_PORT, g_chanlist1, DEV1_NCHANNELS); + if (adc == NULL) + { + aerr("ERROR: Failed to get ADC interface 1\n"); + return -ENODEV; + } + + /* Register the ADC driver at "/dev/adc0" */ + + ret = adc_register("/dev/adc0", adc); + if (ret < 0) + { + aerr("ERROR: adc_register /dev/adc0 failed: %d\n", ret); + return ret; + } + +#ifdef DEV2_PORT + + /* DEV2 */ + + /* Configure the pins as analog inputs for the selected channels */ + + for (i = 0; i < DEV2_NCHANNELS; i++) + { + stm32_configgpio(g_pinlist2[i]); + } + + /* Call stm32_adcinitialize() to get an instance of the ADC interface */ + + adc = stm32_adcinitialize(DEV2_PORT, g_chanlist2, DEV2_NCHANNELS); + if (adc == NULL) + { + aerr("ERROR: Failed to get ADC interface 2\n"); + return -ENODEV; + } + + /* Register the ADC driver at "/dev/adc1" */ + + ret = adc_register("/dev/adc1", adc); + if (ret < 0) + { + aerr("ERROR: adc_register /dev/adc1 failed: %d\n", ret); + return ret; + } +#endif + + return OK; +} + +#endif /* CONFIG_ADC && (CONFIG_STM32_ADC1 || CONFIG_STM32_ADC2 || + * CONFIG_STM32_ADC3 || CONFIG_STM32_ADC4) */ diff --git a/boards/arm/stm32f3/nucleo-f303re/src/stm32_autoleds.c b/boards/arm/stm32f3/nucleo-f303re/src/stm32_autoleds.c new file mode 100644 index 0000000000000..b8bd4ec3c7f06 --- /dev/null +++ b/boards/arm/stm32f3/nucleo-f303re/src/stm32_autoleds.c @@ -0,0 +1,80 @@ +/**************************************************************************** + * boards/arm/stm32f3/nucleo-f303re/src/stm32_autoleds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "stm32.h" +#include "nucleo-f303re.h" + +#ifdef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_autoled_initialize + ****************************************************************************/ + +void board_autoled_initialize(void) +{ + /* Configure LED1 GPIO for output */ + + stm32_configgpio(GPIO_LED1); +} + +/**************************************************************************** + * Name: board_autoled_on + ****************************************************************************/ + +void board_autoled_on(int led) +{ + if (led == BOARD_LED1) + { + stm32_gpiowrite(GPIO_LED1, true); + } +} + +/**************************************************************************** + * Name: board_autoled_off + ****************************************************************************/ + +void board_autoled_off(int led) +{ + if (led == BOARD_LED1) + { + stm32_gpiowrite(GPIO_LED1, false); + } +} + +#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32f3/nucleo-f303re/src/stm32_boot.c b/boards/arm/stm32f3/nucleo-f303re/src/stm32_boot.c new file mode 100644 index 0000000000000..8ff26cda3c57b --- /dev/null +++ b/boards/arm/stm32f3/nucleo-f303re/src/stm32_boot.c @@ -0,0 +1,171 @@ +/**************************************************************************** + * boards/arm/stm32f3/nucleo-f303re/src/stm32_boot.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include +#include + +#include "nucleo-f303re.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#undef HAVE_LEDS +#undef HAVE_DAC + +#if !defined(CONFIG_ARCH_LEDS) && defined(CONFIG_USERLED_LOWER) +# define HAVE_LEDS 1 +#endif + +#if defined(CONFIG_DAC) +# define HAVE_DAC 1 +#endif + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_boardinitialize + * + * Description: + * All STM32 architectures must provide the following entry point. This + * entry point is called early in the initialization -- after all memory + * has been configured and mapped but before any devices have been + * initialized. + * + ****************************************************************************/ + +void stm32_boardinitialize(void) +{ +#ifdef CONFIG_SPI + if (stm32_spidev_initialize != NULL) + { + stm32_spidev_initialize(); + } +#endif + + /* Configure on-board LEDs if LED support has been selected. */ + +#ifdef CONFIG_ARCH_LEDS + board_autoled_initialize(); +#endif +} + +/**************************************************************************** + * Name: board_late_initialize + * + * Description: + * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_late_initialize(). board_late_initialize() will + * be called immediately after up_intitialize() is called and just before + * the initial application is started. This additional initialization + * phase may be used, for example, to initialize board-specific device + * drivers. + * + ****************************************************************************/ + +#ifdef CONFIG_BOARD_LATE_INITIALIZE +void board_late_initialize(void) +{ + int ret; + +#ifdef HAVE_LEDS + /* Register the LED driver */ + + ret = userled_lower_initialize(LED_DRIVER_PATH); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: userled_lower_initialize() failed: %d\n", ret); + return ret; + } +#endif + +#ifdef CONFIG_PWM + /* Initialize PWM and register the PWM device. */ + + ret = stm32_pwm_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_pwm_setup() failed: %d\n", ret); + } +#endif + + /* Contrairement à l'ADC, il n'y a pas de BOARDIOC_DAC_SETUP spécifique. + * Il faut le faire ici + */ + +#ifdef HAVE_DAC + ret = board_dac_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: board_dac_setup() failed: %d\n", ret); + return; + } +#endif + +#ifdef CONFIG_ADC + /* Initialize ADC and register the ADC driver. */ + + ret = stm32_adc_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_adc_setup failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_STM32_CAN_CHARDRIVER + /* Initialize CAN and register the CAN driver. */ + + ret = stm32_can_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_can_setup failed: %d\n", ret); + } +#endif + + UNUSED(ret); +} +#endif /* CONFIG_BOARD_LATE_INITIALIZE */ diff --git a/boards/arm/stm32f3/nucleo-f303re/src/stm32_buttons.c b/boards/arm/stm32f3/nucleo-f303re/src/stm32_buttons.c new file mode 100644 index 0000000000000..0dbfc2add9f6b --- /dev/null +++ b/boards/arm/stm32f3/nucleo-f303re/src/stm32_buttons.c @@ -0,0 +1,113 @@ +/**************************************************************************** + * boards/arm/stm32f3/nucleo-f303re/src/stm32_buttons.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "stm32.h" +#include "nucleo-f303re.h" + +#ifdef CONFIG_ARCH_BUTTONS + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_button_initialize + * + * Description: + * board_button_initialize() must be called to initialize button + * resources. After that, board_buttons() may be called to collect the + * current state of all buttons or board_button_irq() may be called to + * register button interrupt handlers. + * + ****************************************************************************/ + +uint32_t board_button_initialize(void) +{ + /* Configure the single button as an input. NOTE that EXTI interrupts are + * also configured for the pin. + */ + + stm32_configgpio(GPIO_BTN_USER); + return NUM_BUTTONS; +} + +/**************************************************************************** + * Name: board_buttons + * + * Description: + * After board_button_initialize() has been called, board_buttons() may be + * called to collect the state of all buttons. board_buttons() returns an + * 32-bit unsigned integer with each bit associated with a button. See the + * BUTTON_*_BIT definitions in board.h for the meaning of each bit. + * + ****************************************************************************/ + +uint32_t board_buttons(void) +{ + /* Check the state of the USER button. A LOW value means that the key is + * pressed. + */ + + return stm32_gpioread(GPIO_BTN_USER) ? 0 : BUTTON_USER_BIT; +} + +/**************************************************************************** + * Name: board_button_irq + * + * Description: + * board_button_irq() may be called to register an interrupt handler that + * will be called when a button is depressed or released. The ID value is + * a button enumeration value that uniquely identifies a button resource. + * See the BUTTON_* definitions in board.h for the meaning of the + * enumeration value. + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_IRQBUTTONS +int board_button_irq(int id, xcpt_t irqhandler, void *arg) +{ + int ret = -EINVAL; + + if (id == BUTTON_USER) + { + ret = stm32_gpiosetevent(GPIO_BTN_USER, true, true, true, irqhandler, + arg); + } + + return ret; +} +#endif + +#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/stm32f3/nucleo-f303re/src/stm32_can.c b/boards/arm/stm32f3/nucleo-f303re/src/stm32_can.c new file mode 100644 index 0000000000000..5aad29928486f --- /dev/null +++ b/boards/arm/stm32f3/nucleo-f303re/src/stm32_can.c @@ -0,0 +1,81 @@ +/**************************************************************************** + * boards/arm/stm32f3/nucleo-f303re/src/stm32_can.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include + +#include "stm32.h" + +#ifdef CONFIG_CAN + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_can_setup + * + * Description: + * Initialize CAN and register the CAN device + * + ****************************************************************************/ + +int stm32_can_setup(void) +{ +#ifdef CONFIG_STM32_CAN1 + struct can_dev_s *can; + int ret; + + /* Call stm32_caninitialize() to get an instance of the CAN interface */ + + can = stm32_caninitialize(1); + if (can == NULL) + { + canerr("ERROR: Failed to get CAN interface\n"); + return -ENODEV; + } + + /* Register the CAN driver at "/dev/can0" */ + + ret = can_register("/dev/can0", can); + if (ret < 0) + { + canerr("ERROR: can_register failed: %d\n", ret); + return ret; + } + + return OK; +#else + return -ENODEV; +#endif +} + +#endif /* CONFIG_CAN */ diff --git a/boards/arm/stm32f3/nucleo-f303re/src/stm32_pwm.c b/boards/arm/stm32f3/nucleo-f303re/src/stm32_pwm.c new file mode 100644 index 0000000000000..c9910bee3d00a --- /dev/null +++ b/boards/arm/stm32f3/nucleo-f303re/src/stm32_pwm.c @@ -0,0 +1,89 @@ +/**************************************************************************** + * boards/arm/stm32f3/nucleo-f303re/src/stm32_pwm.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "stm32_pwm.h" +#include "nucleo-f303re.h" + +#ifdef CONFIG_PWM + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_pwm_setup + * + * Description: + * Initialize PWM and register the PWM device. + * + ****************************************************************************/ + +int stm32_pwm_setup(void) +{ + static bool initialized = false; + struct pwm_lowerhalf_s *pwm; + int ret; + + /* Have we already initialized? */ + + if (!initialized) + { + /* Call stm32_pwminitialize() to get an instance of the PWM interface */ + + pwm = stm32_pwminitialize(NUCLEO_F303RE_PWMTIMER); + if (pwm == NULL) + { + pwmerr("ERROR: Failed to get the STM32 PWM lower half\n"); + return -ENODEV; + } + + /* Register the PWM driver at "/dev/pwm0" */ + + ret = pwm_register("/dev/pwm0", pwm); + if (ret < 0) + { + pwmerr("ERROR: pwm_register failed: %d\n", ret); + return ret; + } + + /* Now we are initialized */ + + initialized = true; + } + + return OK; +} + +#endif /* CONFIG_PWM */ diff --git a/boards/arm/stm32f3/nucleo-f303re/src/stm32_spi.c b/boards/arm/stm32f3/nucleo-f303re/src/stm32_spi.c new file mode 100644 index 0000000000000..70e8e235c6efc --- /dev/null +++ b/boards/arm/stm32f3/nucleo-f303re/src/stm32_spi.c @@ -0,0 +1,195 @@ +/**************************************************************************** + * boards/arm/stm32f3/nucleo-f303re/src/stm32_spi.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include + +#include "arm_internal.h" +#include "chip.h" +#include "stm32.h" +#include "nucleo-f303re.h" + +#ifdef CONFIG_SPI + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_spidev_initialize + * + * Description: + * Called to configure SPI chip select GPIO pins for the board. + * + ****************************************************************************/ + +void weak_function stm32_spidev_initialize(void) +{ +#if defined(CONFIG_LCD_SSD1351) + stm32_configgpio(GPIO_OLED_CS); /* OLED chip select */ + stm32_configgpio(GPIO_OLED_DC); /* OLED Command/Data */ +#endif +} + +/**************************************************************************** + * Name: stm32_spi1/2/3select and stm32_spi1/2/3status + * + * Description: + * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status + * must be provided by board-specific logic. They are implementations of + * the select and status methods of the SPI interface defined by struct + * spi_ops_s (see include/nuttx/spi/spi.h). All other methods (including + * stm32_spibus_initialize()) are provided by common STM32 logic. + * To use this common SPI logic on your board: + * + * 1. Provide logic in stm32_boardinitialize() to configure SPI chip select + * pins. + * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() functions + * in your board-specific logic. These functions will perform chip + * selection and status operations using GPIOs in the way your board is + * configured. + * 3. Add a calls to stm32_spibus_initialize() in your low level + * application initialization logic + * 4. The handle returned by stm32_spibus_initialize() may then be used to + * bind the SPI driver to higher level logic (e.g., calling + * mmcsd_spislotinitialize(), for example, will bind the SPI driver to + * the SPI MMC/SD driver). + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_SPI1 +void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, + bool selected) +{ + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); + +#if defined(CONFIG_LCD_SSD1351) + if (devid == SPIDEV_DISPLAY(0)) + { + stm32_gpiowrite(GPIO_OLED_CS, !selected); + } +#endif +} + +uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} +#endif + +#ifdef CONFIG_STM32_SPI2 +void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid, + bool selected) +{ + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); +} + +uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} +#endif + +#ifdef CONFIG_STM32_SPI3 +void stm32_spi3select(struct spi_dev_s *dev, uint32_t devid, + bool selected) +{ + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); +} + +uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} +#endif + +/**************************************************************************** + * Name: stm32_spi1cmddata + * + * Description: + * Set or clear the SSD1351 D/C n bit to select data (true) or command + * (false). This function must be provided by platform-specific logic. + * This is an implementation of the cmddata method of the SPI interface + * defined by struct spi_ops_s (see include/nuttx/spi/spi.h). + * + * Input Parameters: + * spi - SPI device that controls the bus the device that requires the + * CMD/DATA selection. + * devid - If there are multiple devices on the bus, this selects which one + * to select cmd or data. NOTE: This design restricts, for + * example, one SPI display per SPI bus. + * cmd - true: select command; false: select data + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_SPI_CMDDATA +#ifdef CONFIG_STM32_SPI1 +int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, + bool cmd) +{ +#ifdef CONFIG_LCD_SSD1351 + if (devid == SPIDEV_DISPLAY(0)) + { + stm32_gpiowrite(GPIO_OLED_DC, !cmd); + return OK; + } +#endif + + return -ENODEV; +} +#endif + +#ifdef CONFIG_STM32_SPI2 +int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, + bool cmd) +{ + return -ENODEV; +} +#endif + +#ifdef CONFIG_STM32_SPI3 +int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, + bool cmd) +{ + return -ENODEV; +} +#endif +#endif /* CONFIG_SPI_CMDDATA */ + +#endif /* CONFIG_SPI */ diff --git a/boards/arm/stm32f3/nucleo-f303re/src/stm32_ssd1351.c b/boards/arm/stm32f3/nucleo-f303re/src/stm32_ssd1351.c new file mode 100644 index 0000000000000..35e09d621e525 --- /dev/null +++ b/boards/arm/stm32f3/nucleo-f303re/src/stm32_ssd1351.c @@ -0,0 +1,118 @@ +/**************************************************************************** + * boards/arm/stm32f3/nucleo-f303re/src/stm32_ssd1351.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include +#include +#include +#include +#include + +#include "stm32_gpio.h" +#include "stm32_spi.h" + +#include "nucleo-f303re.h" + +#ifdef CONFIG_LCD_SSD1351 + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* The pin configurations here require that SPI1 is selected */ + +#ifndef CONFIG_STM32_SPI1 +# error "The OLED driver requires CONFIG_STM32_SPI1 in the configuration" +#endif + +#ifndef CONFIG_SSD1351_SPI4WIRE +# error "The configuration requires the SPI 4-wire interface" +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_graphics_setup + * + * Description: + * Called by NX initialization logic to configure the OLED. + * + ****************************************************************************/ + +struct lcd_dev_s *board_graphics_setup(unsigned int devno) +{ + struct spi_dev_s *spi; + struct lcd_dev_s *dev; + + /* Configure the OLED GPIOs. This initial configuration is RESET low, + * putting the OLED into reset state. + */ + + stm32_configgpio(GPIO_OLED_RESET); + + /* Wait a bit then release the OLED from the reset state */ + + up_mdelay(20); + stm32_gpiowrite(GPIO_OLED_RESET, true); + + /* Get the SPI1 port interface */ + + spi = stm32_spibus_initialize(1); + if (spi == NULL) + { + lcderr("ERROR: Failed to initialize SPI port 1\n"); + } + else + { + /* Bind the SPI port to the OLED */ + + dev = ssd1351_initialize(spi, devno); + if (dev == NULL) + { + lcderr("ERROR: Failed to bind SPI port 1 to OLED %d\n", devno); + } + else + { + lcdinfo("Bound SPI port 1 to OLED %d\n", devno); + + /* And turn the OLED on */ + + dev->setpower(dev, LCD_FULL_ON); + return dev; + } + } + + return NULL; +} + +#endif /* CONFIG_LCD_SSD1351 */ diff --git a/boards/arm/stm32f3/nucleo-f303re/src/stm32_timer.c b/boards/arm/stm32f3/nucleo-f303re/src/stm32_timer.c new file mode 100644 index 0000000000000..61e2ff9d063a1 --- /dev/null +++ b/boards/arm/stm32f3/nucleo-f303re/src/stm32_timer.c @@ -0,0 +1,67 @@ +/**************************************************************************** + * boards/arm/stm32f3/nucleo-f303re/src/stm32_timer.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include + +#include "stm32_tim.h" +#include "nucleo-f303re.h" + +#ifdef CONFIG_TIMER + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_timer_driver_setup + * + * Description: + * Configure the timer driver. + * + * Input Parameters: + * devpath - The full path to the timer device. This should be of the + * form /dev/timer0 + * timer - The timer's number. + * + * Returned Value: + * Zero (OK) is returned on success; A negated errno value is returned + * to indicate the nature of any failure. + * + ****************************************************************************/ + +int stm32_timer_driver_setup(const char *devpath, int timer) +{ + return stm32_timer_initialize(devpath, timer); +} + +#endif diff --git a/boards/arm/stm32f3/nucleo-f303re/src/stm32_uid.c b/boards/arm/stm32f3/nucleo-f303re/src/stm32_uid.c new file mode 100644 index 0000000000000..54e03ff99d1e7 --- /dev/null +++ b/boards/arm/stm32f3/nucleo-f303re/src/stm32_uid.c @@ -0,0 +1,68 @@ +/**************************************************************************** + * boards/arm/stm32f3/nucleo-f303re/src/stm32_uid.c + * + * SPDX-License-Identifier: BSD-3-Clause + * SPDX-FileCopyrightText: 2015 Marawan Ragab. All rights reserved. + * SPDX-FileContributor: Marawan Ragab + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include "stm32_uid.h" + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +#if defined(CONFIG_BOARDCTL_UNIQUEID) +int board_uniqueid(uint8_t *uniqueid) +{ + if (uniqueid == NULL) + { + return -EINVAL; + } + + stm32_get_uniqueid(uniqueid); + return OK; +} +#endif diff --git a/boards/arm/stm32f3/nucleo-f303re/src/stm32_userleds.c b/boards/arm/stm32f3/nucleo-f303re/src/stm32_userleds.c new file mode 100644 index 0000000000000..fdcf173464039 --- /dev/null +++ b/boards/arm/stm32f3/nucleo-f303re/src/stm32_userleds.c @@ -0,0 +1,77 @@ +/**************************************************************************** + * boards/arm/stm32f3/nucleo-f303re/src/stm32_userleds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include + +#include "stm32.h" +#include "nucleo-f303re.h" + +#ifndef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_userled_initialize + ****************************************************************************/ + +uint32_t board_userled_initialize(void) +{ + /* Configure LED1 GPIO for output */ + + stm32_configgpio(GPIO_LED1); + return BOARD_NLEDS; +} + +/**************************************************************************** + * Name: board_userled + ****************************************************************************/ + +void board_userled(int led, bool ledon) +{ + if (led == BOARD_LED1) + { + stm32_gpiowrite(GPIO_LED1, ledon); + } +} + +/**************************************************************************** + * Name: board_userled_all + ****************************************************************************/ + +void board_userled_all(uint32_t ledset) +{ + stm32_gpiowrite(GPIO_LED1, (ledset & BOARD_LED1_BIT) != 0); +} + +#endif /* !CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32f3/nucleo-f303ze/CMakeLists.txt b/boards/arm/stm32f3/nucleo-f303ze/CMakeLists.txt new file mode 100644 index 0000000000000..236a1e371d10e --- /dev/null +++ b/boards/arm/stm32f3/nucleo-f303ze/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32f3/nucleo-f303ze/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/arm/stm32/nucleo-f303ze/Kconfig b/boards/arm/stm32f3/nucleo-f303ze/Kconfig similarity index 100% rename from boards/arm/stm32/nucleo-f303ze/Kconfig rename to boards/arm/stm32f3/nucleo-f303ze/Kconfig diff --git a/boards/arm/stm32f3/nucleo-f303ze/configs/adc/defconfig b/boards/arm/stm32f3/nucleo-f303ze/configs/adc/defconfig new file mode 100644 index 0000000000000..f9450ed1b9f70 --- /dev/null +++ b/boards/arm/stm32f3/nucleo-f303ze/configs/adc/defconfig @@ -0,0 +1,53 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_STM32_CCMEXCLUDE is not set +CONFIG_ADC=y +CONFIG_ANALOG=y +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nucleo-f303ze" +CONFIG_ARCH_BOARD_NUCLEO_F303ZE=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f3" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F303ZE=y +CONFIG_ARCH_CHIP_STM32F3=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=6522 +CONFIG_BUILTIN=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_EXAMPLES_ADC=y +CONFIG_EXAMPLES_ADC_GROUPSIZE=3 +CONFIG_EXAMPLES_ADC_SWTRIG=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_MM_REGIONS=2 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=65536 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=27 +CONFIG_START_YEAR=2013 +CONFIG_STM32_ADC1=y +CONFIG_STM32_ADC1_DMA=y +CONFIG_STM32_ADC3=y +CONFIG_STM32_ADC3_RESOLUTION=3 +CONFIG_STM32_DMA1=y +CONFIG_STM32_DMA2=y +CONFIG_STM32_FORCEPOWER=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_TIM1=y +CONFIG_STM32_TIM1_ADC=y +CONFIG_STM32_USART3=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART3_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f3/nucleo-f303ze/configs/nsh/defconfig b/boards/arm/stm32f3/nucleo-f303ze/configs/nsh/defconfig new file mode 100644 index 0000000000000..c6f9fe743d03a --- /dev/null +++ b/boards/arm/stm32f3/nucleo-f303ze/configs/nsh/defconfig @@ -0,0 +1,39 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nucleo-f303ze" +CONFIG_ARCH_BOARD_NUCLEO_F303ZE=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f3" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F303ZE=y +CONFIG_ARCH_CHIP_STM32F3=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=6522 +CONFIG_BUILTIN=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_EXAMPLES_HELLO=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_MM_REGIONS=2 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=65536 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=27 +CONFIG_START_YEAR=2013 +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_USART3=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART3_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f3/nucleo-f303ze/configs/nxlines_oled/defconfig b/boards/arm/stm32f3/nucleo-f303ze/configs/nxlines_oled/defconfig new file mode 100644 index 0000000000000..028b18ca152f2 --- /dev/null +++ b/boards/arm/stm32f3/nucleo-f303ze/configs/nxlines_oled/defconfig @@ -0,0 +1,54 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_EXAMPLES_NXLINES_DEFAULT_COLORS is not set +# CONFIG_NX_DISABLE_1BPP is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nucleo-f303ze" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_NUCLEO_F303ZE=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f3" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F303ZE=y +CONFIG_ARCH_CHIP_STM32F3=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=6522 +CONFIG_BUILTIN=y +CONFIG_EXAMPLES_NXLINES=y +CONFIG_EXAMPLES_NXLINES_BORDERWIDTH=1 +CONFIG_EXAMPLES_NXLINES_BPP=1 +CONFIG_EXAMPLES_NXLINES_LINECOLOR=0xff +CONFIG_EXAMPLES_NXLINES_LINEWIDTH=1 +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LCD=y +CONFIG_LCD_MAXCONTRAST=255 +CONFIG_LCD_SH1106_OLED_132=y +CONFIG_LCD_SSD1306_I2C=y +CONFIG_MM_REGIONS=2 +CONFIG_MQ_MAXMSGSIZE=64 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NX=y +CONFIG_NXFONT_MONO5X8=y +CONFIG_NX_BLOCKING=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=65536 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=27 +CONFIG_START_YEAR=2013 +CONFIG_STM32_I2C1=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_USART3=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART3_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f3/nucleo-f303ze/include/board.h b/boards/arm/stm32f3/nucleo-f303ze/include/board.h new file mode 100644 index 0000000000000..2f7b5950dd010 --- /dev/null +++ b/boards/arm/stm32f3/nucleo-f303ze/include/board.h @@ -0,0 +1,207 @@ +/**************************************************************************** + * boards/arm/stm32f3/nucleo-f303ze/include/board.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_STM32_NUCLEO_F303ZE_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32_NUCLEO_F303ZE_INCLUDE_BOARD_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#ifndef __ASSEMBLY__ +# include +# include +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Clocking *****************************************************************/ + +/* HSI - Internal 8 MHz RC Oscillator + * LSI - 32 KHz RC + * HSE - 8 MHz from MCO output of ST-LINK + * LSE - 32.768 kHz + */ + +#define STM32_BOARD_XTAL 8000000ul /* X1 on board */ + +#define STM32_HSEBYP_ENABLE +#define STM32_HSI_FREQUENCY 8000000ul +#define STM32_LSI_FREQUENCY 40000 /* Between 30kHz and 60kHz */ +#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL +#define STM32_LSE_FREQUENCY 32768 /* X2 on board */ + +/* PLL source is HSE/1, PLL multiplier is 9: + * PLL frequency is 8MHz (XTAL) x 9 = 72MHz + */ + +#define STM32_CFGR_PLLSRC RCC_CFGR_PLLSRC +#define STM32_CFGR_PLLXTPRE 0 +#define STM32_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx9 +#define STM32_PLL_FREQUENCY (9*STM32_BOARD_XTAL) + +/* Use the PLL and set the SYSCLK source to be the PLL */ + +#define STM32_SYSCLK_SW RCC_CFGR_SW_PLL +#define STM32_SYSCLK_SWS RCC_CFGR_SWS_PLL +#define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY + +/* AHB clock (HCLK) is SYSCLK (72MHz) */ + +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY + +/* APB2 clock (PCLK2) is HCLK (72MHz) */ + +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK +#define STM32_PCLK2_FREQUENCY STM32_HCLK_FREQUENCY +#define STM32_APB2_CLKIN (STM32_PCLK2_FREQUENCY) /* Timers 1 and 8, 15-17 */ + +/* APB2 timers 1 and 8, 15-17 will receive PCLK2. */ + +/* Timers driven from APB2 will be PCLK2 */ + +#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB1_TIM15_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB1_TIM16_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB1_TIM17_CLKIN (STM32_PCLK2_FREQUENCY) + +/* APB1 clock (PCLK1) is HCLK/2 (36MHz) */ + +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd2 +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/2) + +/* APB1 timers 2-7 will be twice PCLK1 */ + +#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) + +/* USB divider -- Divide PLL clock by 1.5 */ + +#define STM32_CFGR_USBPRE 0 + +/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx + * otherwise frequency is 2xAPBx. + * Note: TIM1,8 are on APB2, others on APB1 + */ + +#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM2_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM3_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM4_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM5_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM6_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM7_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY + +/* LED definitions **********************************************************/ + +/* The Nucleo-144 board has numerous LEDs but only three, LD1 a Green LED, + * LD2 a Blue LED and LD3 a Red LED, that can be controlled by software. + * The following definitions assume the default Solder Bridges are installed. + * + * If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs + * in any way. + * The following definitions are used to access individual LEDs. + */ + +/* LED index values for use with board_userled() */ + +#define BOARD_LED1 0 +#define BOARD_LED2 1 +#define BOARD_LED3 2 +#define BOARD_NLEDS 3 + +#define BOARD_LED_GREEN BOARD_LED1 +#define BOARD_LED_BLUE BOARD_LED2 +#define BOARD_LED_RED BOARD_LED3 + +/* LED bits for use with board_userled_all() */ + +#define BOARD_LED1_BIT (1 << BOARD_LED1) +#define BOARD_LED2_BIT (1 << BOARD_LED2) +#define BOARD_LED3_BIT (1 << BOARD_LED3) + +/* If CONFIG_ARCH_LEDS is defined, the usage by the board port is defined in + * include/board.h and src/stm32_leds.c. The LEDs are used to encode + * OS-related events as follows: + * + * + * SYMBOL Meaning LED state + * Red Green Blue + * ---------------------- -------------------------- ------ ------ ---- + */ + +#define LED_STARTED 0 /* NuttX has been started OFF OFF OFF */ +#define LED_HEAPALLOCATE 1 /* Heap has been allocated OFF OFF ON */ +#define LED_IRQSENABLED 2 /* Interrupts enabled OFF ON OFF */ +#define LED_STACKCREATED 3 /* Idle stack created OFF ON ON */ +#define LED_INIRQ 4 /* In an interrupt N/C N/C GLOW */ +#define LED_SIGNAL 5 /* In a signal handler N/C GLOW N/C */ +#define LED_ASSERTION 6 /* An assertion failed GLOW N/C GLOW */ +#define LED_PANIC 7 /* The system has crashed Blink OFF N/C */ +#define LED_IDLE 8 /* MCU is in sleep mode ON OFF OFF */ + +/* Button definitions *******************************************************/ + +/* The NUCLEO board supports one button: Pushbutton B1, labeled "User", is + * connected to GPIO PC13. A high value will be sensed when the button is + * depressed. + */ + +#define BUTTON_USER 0 +#define NUM_BUTTONS 1 + +#define BUTTON_USER_BIT (1 << BUTTON_USER) + +/* Alternate function pin selections ****************************************/ + +/* USART3 (Nucleo Virtual Console) */ + +#define GPIO_USART3_RX (GPIO_USART3_RX_3|GPIO_SPEED_50MHz) /* PD9 */ +#define GPIO_USART3_TX (GPIO_USART3_TX_3|GPIO_SPEED_50MHz) /* PD8 */ + +/* I2C1 Use Nucleo I2C1 pins */ + +#define GPIO_I2C1_SCL (GPIO_I2C1_SCL_3|GPIO_SPEED_50MHz) /* PB8 - D15 */ +#define GPIO_I2C1_SDA (GPIO_I2C1_SDA_3|GPIO_SPEED_50MHz) /* PB9 - D14 */ + +/* I2C2 Use Nucleo I2C2 pins */ + +#define GPIO_I2C2_SCL (GPIO_I2C2_SCL_2|GPIO_SPEED_50MHz) /* PF1 - D69 */ +#define GPIO_I2C2_SDA (GPIO_I2C2_SDA_2|GPIO_SPEED_50MHz) /* PF0 - D68 */ +#define GPIO_I2C2_SMBA (GPIO_I2C2_SMBA_2|GPIO_SPEED_50MHz) /* PF2 - D70 */ + +/* DMA **********************************************************************/ + +#define ADC1_DMA_CHAN DMACHAN_ADC1 +#define ADC3_DMA_CHAN DMACHAN_ADC3 + +#endif /* __BOARDS_ARM_STM32_NUCLEO_F303ZE_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32f3/nucleo-f303ze/scripts/Make.defs b/boards/arm/stm32f3/nucleo-f303ze/scripts/Make.defs new file mode 100644 index 0000000000000..1a1821fb246ab --- /dev/null +++ b/boards/arm/stm32f3/nucleo-f303ze/scripts/Make.defs @@ -0,0 +1,41 @@ +############################################################################ +# boards/arm/stm32f3/nucleo-f303ze/scripts/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/.config +include $(TOPDIR)/tools/Config.mk +include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs + +LDSCRIPT = ld.script +ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) + +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32f3/nucleo-f303ze/scripts/ld.script b/boards/arm/stm32f3/nucleo-f303ze/scripts/ld.script new file mode 100644 index 0000000000000..055c0bbe01f36 --- /dev/null +++ b/boards/arm/stm32f3/nucleo-f303ze/scripts/ld.script @@ -0,0 +1,121 @@ +/**************************************************************************** + * boards/arm/stm32f3/nucleo-f303ze/scripts/ld.script + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* The STM32F303ZET6 has 512Kb of FLASH beginning at address 0x0800:0000, + * 64Kb of SRAM and 16kb CCM RAM. + * + * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 + * where the code expects to begin execution by jumping to the entry point in + * the 0x0800:0000 address range. + */ + +MEMORY +{ + flash (rx) : ORIGIN = 0x08000000, LENGTH = 512K + sram (rwx) : ORIGIN = 0x20000000, LENGTH = 64K +} + +OUTPUT_ARCH(arm) +EXTERN(_vectors) +ENTRY(_stext) +SECTIONS +{ + .text : { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > flash + + .init_section : ALIGN(4) { + _sinit = ABSOLUTE(.); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) + _einit = ABSOLUTE(.); + } > flash + + .ARM.extab : ALIGN(4) { + *(.ARM.extab*) + } > flash + + .ARM.exidx : ALIGN(4) { + __exidx_start = ABSOLUTE(.); + *(.ARM.exidx*) + __exidx_end = ABSOLUTE(.); + } > flash + + .tdata : { + _stdata = ABSOLUTE(.); + *(.tdata .tdata.* .gnu.linkonce.td.*); + _etdata = ABSOLUTE(.); + } > flash + + .tbss : { + _stbss = ABSOLUTE(.); + *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); + _etbss = ABSOLUTE(.); + } > flash + + _eronly = ABSOLUTE(.); + + .data : ALIGN(4) { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > sram AT > flash + + .bss : ALIGN(4) { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + _ebss = ABSOLUTE(.); + } > sram + + /* Stabs debugging sections. */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/stm32f3/nucleo-f303ze/src/CMakeLists.txt b/boards/arm/stm32f3/nucleo-f303ze/src/CMakeLists.txt new file mode 100644 index 0000000000000..1ad333906e15e --- /dev/null +++ b/boards/arm/stm32f3/nucleo-f303ze/src/CMakeLists.txt @@ -0,0 +1,45 @@ +# ############################################################################## +# boards/arm/stm32f3/nucleo-f303ze/src/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(SRCS stm32_boot.c stm32_bringup.c) + +if(CONFIG_ARCH_LEDS) + list(APPEND SRCS stm32_autoleds.c) +else() + list(APPEND SRCS stm32_userleds.c) +endif() + +if(CONFIG_ARCH_BUTTONS) + list(APPEND SRCS stm32_buttons.c) +endif() + +if(CONFIG_ADC) + list(APPEND SRCS stm32_adc.c) +endif() + +if(CONFIG_LCD_SSD1306) + list(APPEND SRCS stm32_lcd.c) +endif() + +target_sources(board PRIVATE ${SRCS}) + +set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/ld.script") diff --git a/boards/arm/stm32f3/nucleo-f303ze/src/Make.defs b/boards/arm/stm32f3/nucleo-f303ze/src/Make.defs new file mode 100644 index 0000000000000..57baf0dc88aab --- /dev/null +++ b/boards/arm/stm32f3/nucleo-f303ze/src/Make.defs @@ -0,0 +1,47 @@ +############################################################################ +# boards/arm/stm32f3/nucleo-f303ze/src/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +CSRCS = stm32_boot.c stm32_bringup.c + +ifeq ($(CONFIG_ARCH_LEDS),y) +CSRCS += stm32_autoleds.c +else +CSRCS += stm32_userleds.c +endif + +ifeq ($(CONFIG_ARCH_BUTTONS),y) +CSRCS += stm32_buttons.c +endif + +ifeq ($(CONFIG_ADC),y) +CSRCS += stm32_adc.c +endif + +ifeq ($(CONFIG_LCD_SSD1306),y) +CSRCS += stm32_lcd.c +endif + +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/nucleo-f303ze/src/nucleo-f303ze.h b/boards/arm/stm32f3/nucleo-f303ze/src/nucleo-f303ze.h similarity index 98% rename from boards/arm/stm32/nucleo-f303ze/src/nucleo-f303ze.h rename to boards/arm/stm32f3/nucleo-f303ze/src/nucleo-f303ze.h index 7f302796b5f3e..35d4d81fa9abc 100644 --- a/boards/arm/stm32/nucleo-f303ze/src/nucleo-f303ze.h +++ b/boards/arm/stm32f3/nucleo-f303ze/src/nucleo-f303ze.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f303ze/src/nucleo-f303ze.h + * boards/arm/stm32f3/nucleo-f303ze/src/nucleo-f303ze.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f3/nucleo-f303ze/src/stm32_adc.c b/boards/arm/stm32f3/nucleo-f303ze/src/stm32_adc.c new file mode 100644 index 0000000000000..e137704a98a88 --- /dev/null +++ b/boards/arm/stm32f3/nucleo-f303ze/src/stm32_adc.c @@ -0,0 +1,243 @@ +/**************************************************************************** + * boards/arm/stm32f3/nucleo-f303ze/src/stm32_adc.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "stm32.h" + +#if defined(CONFIG_ADC) && (defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC3)) + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* 1 or 2 ADC devices (DEV1, DEV2). + * ADC1 and ADC3 supported for now. + */ + +#if defined(CONFIG_STM32_ADC1) +# define DEV1_PORT 1 +#endif + +#if defined(CONFIG_STM32_ADC3) +# if defined(DEV1_PORT) +# define DEV2_PORT 3 +# else +# define DEV1_PORT 3 +# endif +#endif + +/* The number of ADC channels in the conversion list */ + +/* TODO DMA */ + +#define ADC1_NCHANNELS 3 +#define ADC3_NCHANNELS 3 + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* DEV 1 */ + +#if DEV1_PORT == 1 + +#define DEV1_NCHANNELS ADC1_NCHANNELS + +/* Identifying number of each ADC channel (even if NCHANNELS is less ) */ + +static const uint8_t g_chanlist1[3] = +{ + 4, + 6, + 9 +}; + +/* Configurations of pins used by each ADC channel */ + +static const uint32_t g_pinlist1[3] = +{ + GPIO_ADC1_IN4_0, /* PA3/A0 */ + GPIO_ADC1_IN6_0, /* PC0/A1 */ + GPIO_ADC1_IN9_0, /* PC3/A2 */ +}; + +#elif DEV1_PORT == 3 + +#define DEV1_NCHANNELS ADC3_NCHANNELS + +/* Identifying number of each ADC channel */ + +static const uint8_t g_chanlist1[3] = +{ + 8, + 9, + 10 +}; + +/* Configurations of pins used by each ADC channel */ + +static const uint32_t g_pinlist1[3] = +{ + GPIO_ADC3_IN8_0, /* PD11/A3 */ + GPIO_ADC3_IN9_0, /* PD12/A4 */ + GPIO_ADC3_IN10_0, /* PD13/A5 */ +}; + +#endif /* DEV1_PORT == 1 */ + +#ifdef DEV2_PORT + +/* DEV 2 */ + +#if DEV2_PORT == 3 + +#define DEV2_NCHANNELS ADC3_NCHANNELS + +/* Identifying number of each ADC channel */ + +static const uint8_t g_chanlist2[3] = +{ + 8, + 9, + 10 +}; + +/* Configurations of pins used by each ADC channel */ + +static const uint32_t g_pinlist2[3] = +{ + GPIO_ADC3_IN8_0, /* PD11/A3 */ + GPIO_ADC3_IN9_0, /* PD12/A4 */ + GPIO_ADC3_IN10_0, /* PD13/A5 */ +}; + +#endif /* DEV2_PORT == 3 */ +#endif /* DEV2_PORT */ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_adc_setup + * + * Description: + * Initialize ADC and register the ADC driver. + * + ****************************************************************************/ + +int stm32_adc_setup(void) +{ + static bool initialized = false; + struct adc_dev_s *adc; + int ret; + int i; + + /* Check if we have already initialized */ + + if (!initialized) + { + /* DEV1 */ + + /* Configure the pins as analog inputs for the selected channels */ + + for (i = 0; i < DEV1_NCHANNELS; i++) + { + stm32_configgpio(g_pinlist1[i]); + } + + /* Call stm32_adcinitialize() to get an instance of the ADC interface */ + + adc = stm32_adcinitialize(DEV1_PORT, g_chanlist1, DEV1_NCHANNELS); + if (adc == NULL) + { + aerr("ERROR: Failed to get ADC interface 1\n"); + return -ENODEV; + } + + /* Register the ADC driver at "/dev/adc0" */ + + ret = adc_register("/dev/adc0", adc); + if (ret < 0) + { + aerr("ERROR: adc_register /dev/adc0 failed: %d\n", ret); + return ret; + } + +#ifdef DEV2_PORT + /* DEV2 */ + + /* Configure the pins as analog inputs for the selected channels */ + + for (i = 0; i < DEV2_NCHANNELS; i++) + { + stm32_configgpio(g_pinlist2[i]); + } + + /* Call stm32_adcinitialize() to get an instance of the ADC interface */ + + adc = stm32_adcinitialize(DEV2_PORT, g_chanlist2, DEV2_NCHANNELS); + if (adc == NULL) + { + aerr("ERROR: Failed to get ADC interface 2\n"); + return -ENODEV; + } + + /* Register the ADC driver at "/dev/adc1" */ + + ret = adc_register("/dev/adc1", adc); + if (ret < 0) + { + aerr("ERROR: adc_register /dev/adc1 failed: %d\n", ret); + return ret; + } +#endif + + initialized = true; + } + + return OK; +} + +#endif /* CONFIG_ADC && (CONFIG_STM32_ADC1 || CONFIG_STM32_ADC3) */ diff --git a/boards/arm/stm32f3/nucleo-f303ze/src/stm32_autoleds.c b/boards/arm/stm32f3/nucleo-f303ze/src/stm32_autoleds.c new file mode 100644 index 0000000000000..1861cae6b24e3 --- /dev/null +++ b/boards/arm/stm32f3/nucleo-f303ze/src/stm32_autoleds.c @@ -0,0 +1,171 @@ +/**************************************************************************** + * boards/arm/stm32f3/nucleo-f303ze/src/stm32_autoleds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include + +#include +#include + +#include "stm32_gpio.h" +#include "nucleo-f303ze.h" + +#ifdef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* Indexed by BOARD_LED_ */ + +static const uint32_t g_ledmap[BOARD_NLEDS] = +{ + GPIO_LED_GREEN, + GPIO_LED_BLUE, + GPIO_LED_RED, +}; + +static bool g_initialized; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +static void phy_set_led(int led, bool state) +{ + /* Active High */ + + stm32_gpiowrite(g_ledmap[led], state); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_autoled_initialize + ****************************************************************************/ + +void board_autoled_initialize(void) +{ + int i; + + /* Configure the LD1 GPIO for output. Initial state is OFF */ + + for (i = 0; i < nitems(g_ledmap); i++) + { + stm32_configgpio(g_ledmap[i]); + } +} + +/**************************************************************************** + * Name: board_autoled_on + ****************************************************************************/ + +void board_autoled_on(int led) +{ + switch (led) + { + default: + break; + + case LED_HEAPALLOCATE: + phy_set_led(BOARD_LED_BLUE, true); + break; + + case LED_IRQSENABLED: + phy_set_led(BOARD_LED_BLUE, false); + phy_set_led(BOARD_LED_GREEN, true); + break; + + case LED_STACKCREATED: + phy_set_led(BOARD_LED_GREEN, true); + phy_set_led(BOARD_LED_BLUE, true); + g_initialized = true; + break; + + case LED_INIRQ: + phy_set_led(BOARD_LED_BLUE, true); + break; + + case LED_SIGNAL: + phy_set_led(BOARD_LED_GREEN, true); + break; + + case LED_ASSERTION: + phy_set_led(BOARD_LED_RED, true); + phy_set_led(BOARD_LED_BLUE, true); + break; + + case LED_PANIC: + phy_set_led(BOARD_LED_RED, true); + break; + + case LED_IDLE : /* IDLE */ + phy_set_led(BOARD_LED_RED, true); + break; + } +} + +/**************************************************************************** + * Name: board_autoled_off + ****************************************************************************/ + +void board_autoled_off(int led) +{ + switch (led) + { + default: + break; + + case LED_SIGNAL: + phy_set_led(BOARD_LED_GREEN, false); + break; + + case LED_INIRQ: + phy_set_led(BOARD_LED_BLUE, false); + break; + + case LED_ASSERTION: + phy_set_led(BOARD_LED_RED, false); + phy_set_led(BOARD_LED_BLUE, false); + break; + + case LED_PANIC: + phy_set_led(BOARD_LED_RED, false); + break; + + case LED_IDLE : /* IDLE */ + phy_set_led(BOARD_LED_RED, false); + break; + } +} + +#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32f3/nucleo-f303ze/src/stm32_boot.c b/boards/arm/stm32f3/nucleo-f303ze/src/stm32_boot.c new file mode 100644 index 0000000000000..8984995d203f7 --- /dev/null +++ b/boards/arm/stm32f3/nucleo-f303ze/src/stm32_boot.c @@ -0,0 +1,81 @@ +/**************************************************************************** + * boards/arm/stm32f3/nucleo-f303ze/src/stm32_boot.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include +#include + +#include "arm_internal.h" +#include "stm32_start.h" +#include "nucleo-f303ze.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_boardinitialize + * + * Description: + * All STM32 architectures must provide the following entry point. + * This entry point is called early in the initialization -- after all + * memory has been configured and mapped but before any devices have been + * initialized. + * + ****************************************************************************/ + +void stm32_boardinitialize(void) +{ +#ifdef CONFIG_ARCH_LEDS + /* Configure on-board LEDs if LED support has been selected. */ + + board_autoled_initialize(); +#endif +} + +/**************************************************************************** + * Name: board_late_initialize + * + * Description: + * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_late_initialize(). board_late_initialize() will + * be called immediately after up_initialize() is called and just before + * the initial application is started. + * This additional initialization phase may be used, for example, to + * initialize board-specific device drivers. + * + ****************************************************************************/ + +#ifdef CONFIG_BOARD_LATE_INITIALIZE +void board_late_initialize(void) +{ + stm32_bringup(); +} +#endif diff --git a/boards/arm/stm32f3/nucleo-f303ze/src/stm32_bringup.c b/boards/arm/stm32f3/nucleo-f303ze/src/stm32_bringup.c new file mode 100644 index 0000000000000..3daad9db6c2be --- /dev/null +++ b/boards/arm/stm32f3/nucleo-f303ze/src/stm32_bringup.c @@ -0,0 +1,71 @@ +/**************************************************************************** + * boards/arm/stm32f3/nucleo-f303ze/src/stm32_bringup.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include "nucleo-f303ze.h" + +#ifdef CONFIG_INPUT_BUTTONS +# include +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_bringup + * + * Description: + * Perform architecture-specific initialization + * + * CONFIG_BOARD_LATE_INITIALIZE=y : + * Called from board_late_initialize(). + * + ****************************************************************************/ + +int stm32_bringup(void) +{ + int ret = OK; + + UNUSED(ret); + +#ifdef CONFIG_ADC + /* Initialize ADC and register the ADC driver. */ + + ret = stm32_adc_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_adc_setup failed: %d\n", ret); + } +#endif + + return OK; +} diff --git a/boards/arm/stm32f3/nucleo-f303ze/src/stm32_buttons.c b/boards/arm/stm32f3/nucleo-f303ze/src/stm32_buttons.c new file mode 100644 index 0000000000000..ff143d50418ac --- /dev/null +++ b/boards/arm/stm32f3/nucleo-f303ze/src/stm32_buttons.c @@ -0,0 +1,107 @@ +/**************************************************************************** + * boards/arm/stm32f3/nucleo-f303ze/src/stm32_buttons.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include + +#include "stm32_gpio.h" +#include "nucleo-f303ze.h" +#include + +#ifdef CONFIG_ARCH_BUTTONS + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_button_initialize + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. + * + ****************************************************************************/ + +uint32_t board_button_initialize(void) +{ + stm32_configgpio(GPIO_BTN_USER); + return NUM_BUTTONS; +} + +/**************************************************************************** + * Name: board_buttons + ****************************************************************************/ + +uint32_t board_buttons(void) +{ + return stm32_gpioread(GPIO_BTN_USER) ? 1 : 0; +} + +/**************************************************************************** + * Button support. + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. + * + * After board_button_initialize() has been called, board_buttons() may be + * called to collect the state of all buttons. board_buttons() returns a + * 32-bit bit set with each bit associated with a button. See the + * BUTTON_*_BIT definitions in board.h for the meaning of each bit. + * + * board_button_irq() may be called to register an interrupt handler that + * will be called when a button is depressed or released. The ID value is + * a button enumeration value that uniquely identifies a button resource. + * See the BUTTON_* definitions in board.h for the meaning of enumeration + * value. + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_IRQBUTTONS +int board_button_irq(int id, xcpt_t irqhandler, void *arg) +{ + int ret = -EINVAL; + + if (id == BUTTON_USER) + { + ret = stm32_gpiosetevent(GPIO_BTN_USER, true, true, true, + irqhandler, arg); + } + + return ret; +} +#endif +#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/stm32f3/nucleo-f303ze/src/stm32_lcd.c b/boards/arm/stm32f3/nucleo-f303ze/src/stm32_lcd.c new file mode 100644 index 0000000000000..2499bfdbb64ba --- /dev/null +++ b/boards/arm/stm32f3/nucleo-f303ze/src/stm32_lcd.c @@ -0,0 +1,89 @@ +/**************************************************************************** + * boards/arm/stm32f3/nucleo-f303ze/src/stm32_lcd.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include +#include +#include +#include + +#include "stm32.h" +#include "nucleo-f303ze.h" + +#include "stm32_ssd1306.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define OLED_I2C_PORT 1 /* OLED display connected to I2C1 */ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_lcd_initialize + ****************************************************************************/ + +int board_lcd_initialize(void) +{ + int ret; + + ret = board_ssd1306_initialize(OLED_I2C_PORT); + if (ret < 0) + { + lcderr("ERROR: Failed to initialize SSD1306\n"); + return ret; + } + + return OK; +} + +/**************************************************************************** + * Name: board_lcd_getdev + ****************************************************************************/ + +struct lcd_dev_s *board_lcd_getdev(int devno) +{ + return board_ssd1306_getdev(); +} + +/**************************************************************************** + * Name: board_lcd_uninitialize + ****************************************************************************/ + +void board_lcd_uninitialize(void) +{ + /* TO-FIX */ +} diff --git a/boards/arm/stm32f3/nucleo-f303ze/src/stm32_userleds.c b/boards/arm/stm32f3/nucleo-f303ze/src/stm32_userleds.c new file mode 100644 index 0000000000000..770c74720d13d --- /dev/null +++ b/boards/arm/stm32f3/nucleo-f303ze/src/stm32_userleds.c @@ -0,0 +1,127 @@ +/**************************************************************************** + * boards/arm/stm32f3/nucleo-f303ze/src/stm32_userleds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include + +#include +#include + +#include "stm32_gpio.h" +#include "nucleo-f303ze.h" + +#ifndef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* This array maps an LED number to GPIO pin configuration and is indexed by + * BOARD_LED_ + */ + +static const uint32_t g_ledcfg[BOARD_NLEDS] = +{ + GPIO_LED_GREEN, + GPIO_LED_BLUE, + GPIO_LED_RED, +}; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_userled_initialize + * + * Description: + * If CONFIG_ARCH_LEDS is defined, then NuttX will control the on-board + * LEDs. If CONFIG_ARCH_LEDS is not defined, then the + * board_userled_initialize() is available to initialize the LED from user + * application logic. + * + ****************************************************************************/ + +uint32_t board_userled_initialize(void) +{ + int i; + + /* Configure LED1-3 GPIOs for output */ + + for (i = 0; i < nitems(g_ledcfg); i++) + { + stm32_configgpio(g_ledcfg[i]); + } + + return BOARD_NLEDS; +} + +/**************************************************************************** + * Name: board_userled + * + * Description: + * If CONFIG_ARCH_LEDS is defined, then NuttX will control the on-board + * LEDs. If CONFIG_ARCH_LEDS is not defined, then the board_userled() is + * available to control the LED from user application logic. + * + ****************************************************************************/ + +void board_userled(int led, bool ledon) +{ + if ((unsigned)led < nitems(g_ledcfg)) + { + stm32_gpiowrite(g_ledcfg[led], ledon); + } +} + +/**************************************************************************** + * Name: board_userled_all + * + * Description: + * If CONFIG_ARCH_LEDS is defined, then NuttX will control the on-board + * LEDs. If CONFIG_ARCH_LEDS is not defined, then the board_userled_all() + * is available to control the LED from user application logic. NOTE: since + * there is only a single LED on-board, this is function is not very useful. + * + ****************************************************************************/ + +void board_userled_all(uint32_t ledset) +{ + int i; + + /* Configure LED1-3 GPIOs for output */ + + for (i = 0; i < nitems(g_ledcfg); i++) + { + stm32_gpiowrite(g_ledcfg[i], (ledset & (1 << i)) != 0); + } +} + +#endif /* !CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32f3/nucleo-f334r8/CMakeLists.txt b/boards/arm/stm32f3/nucleo-f334r8/CMakeLists.txt new file mode 100644 index 0000000000000..6822d936f9563 --- /dev/null +++ b/boards/arm/stm32f3/nucleo-f334r8/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32f3/nucleo-f334r8/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/arm/stm32/nucleo-f334r8/Kconfig b/boards/arm/stm32f3/nucleo-f334r8/Kconfig similarity index 100% rename from boards/arm/stm32/nucleo-f334r8/Kconfig rename to boards/arm/stm32f3/nucleo-f334r8/Kconfig diff --git a/boards/arm/stm32f3/nucleo-f334r8/configs/adc/defconfig b/boards/arm/stm32f3/nucleo-f334r8/configs/adc/defconfig new file mode 100644 index 0000000000000..c5b882ea44497 --- /dev/null +++ b/boards/arm/stm32f3/nucleo-f334r8/configs/adc/defconfig @@ -0,0 +1,96 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_SYSTEM_DD is not set +CONFIG_ADC=y +CONFIG_ANALOG=y +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nucleo-f334r8" +CONFIG_ARCH_BOARD_NUCLEO_F334R8=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f3" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F334R8=y +CONFIG_ARCH_CHIP_STM32F3=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_DISABLE_ENVIRON=y +CONFIG_DISABLE_MQUEUE=y +CONFIG_DISABLE_POSIX_TIMERS=y +CONFIG_DISABLE_PTHREAD=y +CONFIG_EXAMPLES_ADC=y +CONFIG_EXAMPLES_ADC_GROUPSIZE=3 +CONFIG_EXAMPLES_ADC_SWTRIG=y +CONFIG_FDCLONE_STDIO=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=1024 +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_NAME_MAX=16 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_DISABLE_BASENAME=y +CONFIG_NSH_DISABLE_CAT=y +CONFIG_NSH_DISABLE_CD=y +CONFIG_NSH_DISABLE_CMP=y +CONFIG_NSH_DISABLE_CP=y +CONFIG_NSH_DISABLE_DF=y +CONFIG_NSH_DISABLE_DIRNAME=y +CONFIG_NSH_DISABLE_EXEC=y +CONFIG_NSH_DISABLE_EXIT=y +CONFIG_NSH_DISABLE_GET=y +CONFIG_NSH_DISABLE_HEXDUMP=y +CONFIG_NSH_DISABLE_KILL=y +CONFIG_NSH_DISABLE_LOSETUP=y +CONFIG_NSH_DISABLE_LS=y +CONFIG_NSH_DISABLE_MKDIR=y +CONFIG_NSH_DISABLE_MKRD=y +CONFIG_NSH_DISABLE_MOUNT=y +CONFIG_NSH_DISABLE_MV=y +CONFIG_NSH_DISABLE_PUT=y +CONFIG_NSH_DISABLE_PWD=y +CONFIG_NSH_DISABLE_RM=y +CONFIG_NSH_DISABLE_RMDIR=y +CONFIG_NSH_DISABLE_SET=y +CONFIG_NSH_DISABLE_SLEEP=y +CONFIG_NSH_DISABLE_SOURCE=y +CONFIG_NSH_DISABLE_TEST=y +CONFIG_NSH_DISABLE_TIME=y +CONFIG_NSH_DISABLE_UMOUNT=y +CONFIG_NSH_DISABLE_UNAME=y +CONFIG_NSH_DISABLE_UNSET=y +CONFIG_NSH_DISABLE_USLEEP=y +CONFIG_NSH_DISABLE_WGET=y +CONFIG_NSH_DISABLE_XD=y +CONFIG_NSH_FILEIOSIZE=256 +CONFIG_NSH_READLINE=y +CONFIG_POSIX_SPAWN_DEFAULT_STACKSIZE=512 +CONFIG_PTHREAD_STACK_DEFAULT=1024 +CONFIG_PTHREAD_STACK_MIN=1024 +CONFIG_RAM_SIZE=12288 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_STM32_ADC1=y +CONFIG_STM32_ADC1_DMA=y +CONFIG_STM32_ADC2=y +CONFIG_STM32_DMA1=y +CONFIG_STM32_FORCEPOWER=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_PWR=y +CONFIG_STM32_TIM1=y +CONFIG_STM32_TIM1_ADC=y +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f3/nucleo-f334r8/configs/highpri/defconfig b/boards/arm/stm32f3/nucleo-f334r8/configs/highpri/defconfig new file mode 100644 index 0000000000000..1c1da0ff5ee24 --- /dev/null +++ b/boards/arm/stm32f3/nucleo-f334r8/configs/highpri/defconfig @@ -0,0 +1,63 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nucleo-f334r8" +CONFIG_ARCH_BOARD_NUCLEO_F334R8=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f3" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F334R8=y +CONFIG_ARCH_CHIP_STM32F3=y +CONFIG_ARCH_HIPRI_INTERRUPT=y +CONFIG_ARCH_RAMVECTORS=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_DISABLE_ENVIRON=y +CONFIG_DISABLE_MQUEUE=y +CONFIG_DISABLE_POSIX_TIMERS=y +CONFIG_FDCLONE_STDIO=y +CONFIG_INIT_ENTRYPOINT="highpri_main" +CONFIG_INIT_STACKSIZE=1024 +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBM=y +CONFIG_NAME_MAX=16 +CONFIG_NUCLEOF334R8_HIGHPRI=y +CONFIG_POSIX_SPAWN_DEFAULT_STACKSIZE=512 +CONFIG_PTHREAD_STACK_DEFAULT=1024 +CONFIG_PTHREAD_STACK_MIN=1024 +CONFIG_RAM_SIZE=12288 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_STM32_ADC1=y +CONFIG_STM32_ADC1_DMA=y +CONFIG_STM32_ADC1_DMA_CFG=1 +CONFIG_STM32_ADC1_EXTSEL=y +CONFIG_STM32_ADC1_INJECTED_CHAN=1 +CONFIG_STM32_ADC_LL_OPS=y +CONFIG_STM32_ADC_NOIRQ=y +CONFIG_STM32_DMA1=y +CONFIG_STM32_HRTIM1=y +CONFIG_STM32_HRTIM_ADC1_TRG1=y +CONFIG_STM32_HRTIM_ADC=y +CONFIG_STM32_HRTIM_CLK_FROM_PLL=y +CONFIG_STM32_HRTIM_DISABLE_CHARDRV=y +CONFIG_STM32_HRTIM_NO_ENABLE_TIMERS=y +CONFIG_STM32_HRTIM_TIMA=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_PWR=y +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_READLINE=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f3/nucleo-f334r8/configs/nsh/defconfig b/boards/arm/stm32f3/nucleo-f334r8/configs/nsh/defconfig new file mode 100644 index 0000000000000..7a8a8baf3f1a4 --- /dev/null +++ b/boards/arm/stm32f3/nucleo-f334r8/configs/nsh/defconfig @@ -0,0 +1,87 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_SYSTEM_DD is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nucleo-f334r8" +CONFIG_ARCH_BOARD_NUCLEO_F334R8=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f3" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F334R8=y +CONFIG_ARCH_CHIP_STM32F3=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_DISABLE_ENVIRON=y +CONFIG_DISABLE_MQUEUE=y +CONFIG_DISABLE_POSIX_TIMERS=y +CONFIG_DISABLE_PTHREAD=y +CONFIG_EXAMPLES_HELLO=y +CONFIG_FDCLONE_STDIO=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=1024 +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_NAME_MAX=16 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_DISABLE_BASENAME=y +CONFIG_NSH_DISABLE_CAT=y +CONFIG_NSH_DISABLE_CD=y +CONFIG_NSH_DISABLE_CMP=y +CONFIG_NSH_DISABLE_CP=y +CONFIG_NSH_DISABLE_DF=y +CONFIG_NSH_DISABLE_DIRNAME=y +CONFIG_NSH_DISABLE_EXEC=y +CONFIG_NSH_DISABLE_EXIT=y +CONFIG_NSH_DISABLE_GET=y +CONFIG_NSH_DISABLE_HEXDUMP=y +CONFIG_NSH_DISABLE_KILL=y +CONFIG_NSH_DISABLE_LOSETUP=y +CONFIG_NSH_DISABLE_LS=y +CONFIG_NSH_DISABLE_MKDIR=y +CONFIG_NSH_DISABLE_MKRD=y +CONFIG_NSH_DISABLE_MOUNT=y +CONFIG_NSH_DISABLE_MV=y +CONFIG_NSH_DISABLE_PUT=y +CONFIG_NSH_DISABLE_PWD=y +CONFIG_NSH_DISABLE_RM=y +CONFIG_NSH_DISABLE_RMDIR=y +CONFIG_NSH_DISABLE_SET=y +CONFIG_NSH_DISABLE_SLEEP=y +CONFIG_NSH_DISABLE_SOURCE=y +CONFIG_NSH_DISABLE_TEST=y +CONFIG_NSH_DISABLE_TIME=y +CONFIG_NSH_DISABLE_UMOUNT=y +CONFIG_NSH_DISABLE_UNAME=y +CONFIG_NSH_DISABLE_UNSET=y +CONFIG_NSH_DISABLE_USLEEP=y +CONFIG_NSH_DISABLE_WGET=y +CONFIG_NSH_DISABLE_XD=y +CONFIG_NSH_FILEIOSIZE=256 +CONFIG_NSH_READLINE=y +CONFIG_POSIX_SPAWN_DEFAULT_STACKSIZE=512 +CONFIG_PTHREAD_STACK_DEFAULT=1024 +CONFIG_PTHREAD_STACK_MIN=1024 +CONFIG_RAM_SIZE=12288 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_STM32_CCMEXCLUDE=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_PWR=y +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f3/nucleo-f334r8/configs/spwm1/defconfig b/boards/arm/stm32f3/nucleo-f334r8/configs/spwm1/defconfig new file mode 100644 index 0000000000000..351e8d90ad43e --- /dev/null +++ b/boards/arm/stm32f3/nucleo-f334r8/configs/spwm1/defconfig @@ -0,0 +1,74 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nucleo-f334r8" +CONFIG_ARCH_BOARD_NUCLEO_F334R8=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f3" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F334R8=y +CONFIG_ARCH_CHIP_STM32F3=y +CONFIG_ARCH_HIPRI_INTERRUPT=y +CONFIG_ARCH_RAMVECTORS=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_DISABLE_ENVIRON=y +CONFIG_DISABLE_MQUEUE=y +CONFIG_DISABLE_POSIX_TIMERS=y +CONFIG_FDCLONE_STDIO=y +CONFIG_INIT_ENTRYPOINT="spwm_main" +CONFIG_INIT_STACKSIZE=1024 +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBM=y +CONFIG_NAME_MAX=16 +CONFIG_NUCLEOF334R8_SPWM=y +CONFIG_NUCLEOF334R8_SPWM_PHASE_NUM=3 +CONFIG_NUCLEOF334R8_SPWM_USE_HRTIM1=y +CONFIG_POSIX_SPAWN_DEFAULT_STACKSIZE=512 +CONFIG_PTHREAD_STACK_DEFAULT=1024 +CONFIG_PTHREAD_STACK_MIN=1024 +CONFIG_RAM_SIZE=12288 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_STM32_CCMEXCLUDE=y +CONFIG_STM32_HRTIM1=y +CONFIG_STM32_HRTIM_CLK_FROM_PLL=y +CONFIG_STM32_HRTIM_DISABLE_CHARDRV=y +CONFIG_STM32_HRTIM_INTERRUPTS=y +CONFIG_STM32_HRTIM_MASTER=y +CONFIG_STM32_HRTIM_MASTER_IRQ=y +CONFIG_STM32_HRTIM_NO_ENABLE_TIMERS=y +CONFIG_STM32_HRTIM_PWM=y +CONFIG_STM32_HRTIM_TIMA=y +CONFIG_STM32_HRTIM_TIMA_PWM=y +CONFIG_STM32_HRTIM_TIMA_PWM_CH1=y +CONFIG_STM32_HRTIM_TIMB=y +CONFIG_STM32_HRTIM_TIMB_PWM=y +CONFIG_STM32_HRTIM_TIMB_PWM_CH1=y +CONFIG_STM32_HRTIM_TIMC=y +CONFIG_STM32_HRTIM_TIMC_PWM=y +CONFIG_STM32_HRTIM_TIMC_PWM_CH1=y +CONFIG_STM32_HRTIM_TIMD=y +CONFIG_STM32_HRTIM_TIMD_PWM=y +CONFIG_STM32_HRTIM_TIMD_PWM_CH1=y +CONFIG_STM32_HRTIM_TIME=y +CONFIG_STM32_HRTIM_TIME_PWM=y +CONFIG_STM32_HRTIM_TIME_PWM_CH1=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_PWR=y +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_READLINE=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f3/nucleo-f334r8/configs/spwm2/defconfig b/boards/arm/stm32f3/nucleo-f334r8/configs/spwm2/defconfig new file mode 100644 index 0000000000000..2427abbae0bcc --- /dev/null +++ b/boards/arm/stm32f3/nucleo-f334r8/configs/spwm2/defconfig @@ -0,0 +1,65 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nucleo-f334r8" +CONFIG_ARCH_BOARD_NUCLEO_F334R8=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f3" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F334R8=y +CONFIG_ARCH_CHIP_STM32F3=y +CONFIG_ARCH_HIPRI_INTERRUPT=y +CONFIG_ARCH_RAMVECTORS=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_DISABLE_ENVIRON=y +CONFIG_DISABLE_MQUEUE=y +CONFIG_DISABLE_POSIX_TIMERS=y +CONFIG_FDCLONE_STDIO=y +CONFIG_INIT_ENTRYPOINT="spwm_main" +CONFIG_INIT_STACKSIZE=1024 +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBM=y +CONFIG_NAME_MAX=16 +CONFIG_NUCLEOF334R8_SPWM=y +CONFIG_NUCLEOF334R8_SPWM_PHASE_NUM=4 +CONFIG_POSIX_SPAWN_DEFAULT_STACKSIZE=512 +CONFIG_PTHREAD_STACK_DEFAULT=1024 +CONFIG_PTHREAD_STACK_MIN=1024 +CONFIG_RAM_SIZE=12288 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_STM32_CCMEXCLUDE=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_PWM_LL_OPS=y +CONFIG_STM32_PWM_MULTICHAN=y +CONFIG_STM32_PWR=y +CONFIG_STM32_TIM1=y +CONFIG_STM32_TIM1_CH1OUT=y +CONFIG_STM32_TIM1_CH2OUT=y +CONFIG_STM32_TIM1_CH3OUT=y +CONFIG_STM32_TIM1_CH4OUT=y +CONFIG_STM32_TIM1_CHANNEL1=y +CONFIG_STM32_TIM1_CHANNEL2=y +CONFIG_STM32_TIM1_CHANNEL3=y +CONFIG_STM32_TIM1_CHANNEL4=y +CONFIG_STM32_TIM1_PWM=y +CONFIG_STM32_TIM6=y +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_READLINE=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f3/nucleo-f334r8/include/board.h b/boards/arm/stm32f3/nucleo-f334r8/include/board.h new file mode 100644 index 0000000000000..52d5fbd8889cf --- /dev/null +++ b/boards/arm/stm32f3/nucleo-f334r8/include/board.h @@ -0,0 +1,344 @@ +/**************************************************************************** + * boards/arm/stm32f3/nucleo-f334r8/include/board.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_STM32_NUCLEO_F334R8_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32_NUCLEO_F334R8_INCLUDE_BOARD_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#ifndef __ASSEMBLY__ +# include +# include +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Clocking *****************************************************************/ + +/* HSI - Internal 8 MHz RC Oscillator + * LSI - 32 KHz RC + * HSE - 8 MHz from MCO output of ST-LINK + * LSE - 32.768 kHz + */ + +#define STM32_BOARD_XTAL 8000000ul + +#define STM32_HSI_FREQUENCY 8000000ul +#define STM32_LSI_FREQUENCY 32000 /* Between 30kHz and 60kHz */ +#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL +#define STM32_LSE_FREQUENCY 32768 /* X2 on board */ + +/* PLL source is HSE/1, PLL multiplier is 9: PLL frequency is + * 8MHz (XTAL) x 9 = 72MHz + */ + +#define STM32_CFGR_PLLSRC RCC_CFGR_PLLSRC +#define STM32_CFGR_PLLXTPRE 0 +#define STM32_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx9 +#define STM32_PLL_FREQUENCY (9*STM32_BOARD_XTAL) + +/* Use the PLL and set the SYSCLK source to be the PLL */ + +#define STM32_SYSCLK_SW RCC_CFGR_SW_PLL +#define STM32_SYSCLK_SWS RCC_CFGR_SWS_PLL +#define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY + +/* AHB clock (HCLK) is SYSCLK (72MHz) */ + +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY + +/* APB2 clock (PCLK2) is HCLK (72MHz) */ + +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK +#define STM32_PCLK2_FREQUENCY STM32_HCLK_FREQUENCY +#define STM32_APB2_CLKIN (STM32_PCLK2_FREQUENCY) + +/* APB2 timers 1, 8, 15-17 and HRTIM1 will receive PCLK2. */ + +/* Timers driven from APB2 will be PCLK2 */ + +#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB1_TIM15_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB1_TIM16_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB1_TIM17_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB1_THRTIM1_CLKIN (STM32_PCLK2_FREQUENCY) + +/* APB1 clock (PCLK1) is HCLK/2 (36MHz) */ + +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd2 +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/2) + +/* APB1 timers 2-7 will be twice PCLK1 */ + +#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) + +/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx + * otherwise frequency is 2xAPBx. + * Note: TIM1,8 are on APB2, others on APB1 + */ + +#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM15_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM16_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM17_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM2_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM3_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM5_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM6_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM7_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_HRTIM1_FREQUENCY STM32_HCLK_FREQUENCY + +/* LED definitions **********************************************************/ + +/* The Nucleo F334R8 board has three LEDs. Two of these are controlled by + * logic on the board and are not available for software control: + * + * LD1 COM: LD1 default status is red. LD1 turns to green to indicate that + * communications are in progress between the PC and the + * ST-LINK/V2-1. + * LD3 PWR: red LED indicates that the board is powered. + * + * And one can be controlled by software: + * + * User LD2: green LED is a user LED connected to the I/O PA5 of the + * STM32F334R8. + * + * If CONFIG_ARCH_LEDS is not defined, then the user can control the LED in + * any way. The following definition is used to access the LED. + */ + +/* LED index values for use with board_userled() */ + +#define BOARD_LED1 0 /* User LD2 */ +#define BOARD_NLEDS 1 + +/* LED bits for use with board_userled_all() */ + +#define BOARD_LED1_BIT (1 << BOARD_LED1) + +/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the LED on board + * the Nucleo F334R8. The following definitions describe how NuttX controls + * the LED: + * + * SYMBOL Meaning LED1 state + * ------------------ ----------------------- ---------- + * LED_STARTED NuttX has been started OFF + * LED_HEAPALLOCATE Heap has been allocated OFF + * LED_IRQSENABLED Interrupts enabled OFF + * LED_STACKCREATED Idle stack created ON + * LED_INIRQ In an interrupt No change + * LED_SIGNAL In a signal handler No change + * LED_ASSERTION An assertion failed No change + * LED_PANIC The system has crashed Blinking + * LED_IDLE STM32 is in sleep mode Not used + */ + +#define LED_STARTED 0 +#define LED_HEAPALLOCATE 0 +#define LED_IRQSENABLED 0 +#define LED_STACKCREATED 1 +#define LED_INIRQ 2 +#define LED_SIGNAL 2 +#define LED_ASSERTION 2 +#define LED_PANIC 1 + +/* Button definitions *******************************************************/ + +/* The Nucleo F334R8 supports two buttons; only one button is controllable + * by software: + * + * B1 USER: user button connected to the I/O PC13 of the STM32F334R8. + * B2 RESET: push button connected to NRST is used to RESET the + * STM32F334R8. + */ + +#define BUTTON_USER 0 +#define NUM_BUTTONS 1 + +#define BUTTON_USER_BIT (1 << BUTTON_USER) + +/* Alternate function pin selections ****************************************/ + +/* CAN */ + +#define GPIO_CAN1_RX (GPIO_CAN_RX_2|GPIO_SPEED_50MHz) +#define GPIO_CAN1_TX (GPIO_CAN_TX_2|GPIO_SPEED_50MHz) + +/* I2C */ + +#define GPIO_I2C1_SCL (GPIO_I2C1_SCL_3|GPIO_SPEED_50MHz) +#define GPIO_I2C1_SDA (GPIO_I2C1_SDA_3|GPIO_SPEED_50MHz) + +/* SPI */ + +#define GPIO_SPI1_MISO (GPIO_SPI1_MISO_1|GPIO_SPEED_50MHz) +#define GPIO_SPI1_MOSI (GPIO_SPI1_MOSI_1|GPIO_SPEED_50MHz) +#define GPIO_SPI1_SCK (GPIO_SPI1_SCK_1|GPIO_SPEED_50MHz) + +/* TIM */ + +#define GPIO_TIM2_CH2OUT (GPIO_TIM2_CH2OUT_2|GPIO_SPEED_50MHz) +#define GPIO_TIM2_CH3OUT (GPIO_TIM2_CH3OUT_3|GPIO_SPEED_50MHz) + +#define GPIO_TIM3_CH1OUT (GPIO_TIM3_CH1OUT_2|GPIO_SPEED_50MHz) +#define GPIO_TIM3_CH2OUT (GPIO_TIM3_CH2OUT_4|GPIO_SPEED_50MHz) + +#define GPIO_TIM4_CH1OUT (GPIO_TIM4_CH1OUT_2|GPIO_SPEED_50MHz) + +/* USART */ + +/* By default the USART2 is connected to STLINK Virtual COM Port: + * USART2_RX - PA3 + * USART2_TX - PA2 + */ + +#define GPIO_USART2_RX (GPIO_USART2_RX_1|GPIO_SPEED_50MHz) /* PA3 */ +#define GPIO_USART2_TX (GPIO_USART2_TX_1|GPIO_SPEED_50MHz) /* PA2 */ + +#define GPIO_USART1_RX (GPIO_USART1_RX_1|GPIO_SPEED_50MHz) /* PA10 */ +#define GPIO_USART1_TX (GPIO_USART1_TX_1|GPIO_SPEED_50MHz) /* PA9 */ + +/* COMP */ + +/* OPAMP */ + +#define OPAMP2_VMSEL OPAMP2_VMSEL_PC5 +#define OPAMP2_VPSEL OPAMP2_VPSEL_PB14 + +/* Configuration specific to high priority interrupts example: + * - HRTIM Timer A trigger for ADC if DMA transfer and HRTIM + * - TIM1 CC1 trigger for ADC if DMA transfer and TIM1 PWM + * - ADC DMA transfer on DMA1_CH1 + */ + +#ifdef CONFIG_NUCLEOF334R8_HIGHPRI + +#if defined(CONFIG_STM32_HRTIM1) && defined(CONFIG_STM32_ADC1_DMA) + +/* HRTIM - ADC trigger */ + +#define HRTIM_TIMA_PRESCALER HRTIM_PRESCALER_128 +#define HRTIM_TIMA_MODE HRTIM_MODE_CONT +#define HRTIM_TIMA_UPDATE 0 +#define HRTIM_TIMA_RESET 0 + +#define HRTIM_ADC_TRG1 HRTIM_ADCTRG13_APER + +#endif /* CONFIG_STM32_HRTIM1 && CONFIG_STM32_ADC1_DMA*/ +#endif /* CONFIG_NUCLEOF334R8_HIGHPRI */ + +#ifdef CONFIG_NUCLEOF334R8_SPWM +# ifdef CONFIG_NUCLEOF334R8_SPWM_USE_TIM1 + +/* TIM1 PWM configuration ***************************************************/ + +# define GPIO_TIM1_CH1OUT (GPIO_TIM1_CH1OUT_1|GPIO_SPEED_50MHz) /* TIM1 CH1 - PA8 */ +# define GPIO_TIM1_CH1NOUT (GPIO_TIM1_CH1N_3|GPIO_SPEED_50MHz) /* TIM1 CH1N - PA7 */ + /* TIM1 CH2 - PA9 */ +# define GPIO_TIM1_CH2NOUT (GPIO_TIM1_CH2N_2|GPIO_SPEED_50MHz) /* TIM1 CH2N - PB0 */ +# define GPIO_TIM1_CH3OUT (GPIO_TIM1_CH3OUT_1|GPIO_SPEED_50MHz) /* TIM1 CH3 - PA10 */ +# define GPIO_TIM1_CH3NOUT (GPIO_TIM1_CH3N_2|GPIO_SPEED_50MHz) /* TIM1 CH3N - PB1 */ +# define GPIO_TIM1_CH4OUT (GPIO_TIM1_CH4OUT_1|GPIO_SPEED_50MHz) /* TIM1 CH4 - PA11 */ +# endif + +# ifdef CONFIG_NUCLEOF334R8_SPWM_USE_HRTIM1 + +/* HRTIM configuration ******************************************************/ + +# define HRTIM_MASTER_PRESCALER HRTIM_PRESCALER_128 +# define HRTIM_MASTER_MODE HRTIM_MODE_CONT + +# define HRTIM_TIMA_PRESCALER HRTIM_PRESCALER_128 +# define HRTIM_TIMA_MODE (HRTIM_MODE_CONT | HRTIM_MODE_PRELOAD) +# define HRTIM_TIMA_CH1_SET HRTIM_OUT_SET_PER +# define HRTIM_TIMA_CH1_RST HRTIM_OUT_RST_CMP1 +# define HRTIM_TIMA_UPDATE HRTIM_UPDATE_MSTU +# define HRTIM_TIMA_RESET 0 + +# define HRTIM_TIMB_PRESCALER HRTIM_PRESCALER_128 +# define HRTIM_TIMB_MODE (HRTIM_MODE_CONT | HRTIM_MODE_PRELOAD) +# define HRTIM_TIMB_CH1_SET HRTIM_OUT_SET_PER +# define HRTIM_TIMB_CH1_RST HRTIM_OUT_RST_CMP1 +# define HRTIM_TIMB_UPDATE HRTIM_UPDATE_MSTU +# define HRTIM_TIMB_RESET 0 + +# define HRTIM_TIMC_PRESCALER HRTIM_PRESCALER_128 +# define HRTIM_TIMC_MODE (HRTIM_MODE_CONT | HRTIM_MODE_PRELOAD) +# define HRTIM_TIMC_CH1_SET HRTIM_OUT_SET_PER +# define HRTIM_TIMC_CH1_RST HRTIM_OUT_RST_CMP1 +# define HRTIM_TIMC_UPDATE HRTIM_UPDATE_MSTU +# define HRTIM_TIMC_RESET 0 + +# define HRTIM_TIMD_PRESCALER HRTIM_PRESCALER_128 +# define HRTIM_TIMD_MODE (HRTIM_MODE_CONT | HRTIM_MODE_PRELOAD) +# define HRTIM_TIMD_CH1_SET HRTIM_OUT_SET_PER +# define HRTIM_TIMD_CH1_RST HRTIM_OUT_RST_CMP1 +# define HRTIM_TIMD_UPDATE HRTIM_UPDATE_MSTU +# define HRTIM_TIMD_RESET 0 + +# define HRTIM_TIME_PRESCALER HRTIM_PRESCALER_128 +# define HRTIM_TIME_MODE (HRTIM_MODE_CONT | HRTIM_MODE_PRELOAD) +# define HRTIM_TIME_CH1_SET HRTIM_OUT_SET_PER +# define HRTIM_TIME_CH1_RST HRTIM_OUT_RST_CMP1 +# define HRTIM_TIME_UPDATE HRTIM_UPDATE_MSTU +# define HRTIM_TIME_RESET 0 + +# define HRTIM_MASTER_IRQ HRTIM_IRQ_MCMP1 +# endif + +#endif /* CONFIG_NUCLEOF334R8_SPWM */ + +/* DMA channels *************************************************************/ + +/* ADC */ + +#define ADC1_DMA_CHAN DMACHAN_ADC1 /* DMA1_CH1 */ + +/* TIM1 CH2 alias (used by spwm2 config) */ + +#define GPIO_TIM1_CH2OUT (GPIO_TIM1_CH2OUT_0|GPIO_SPEED_50MHz) + +/* HRTIM1 */ + +#define GPIO_HRTIM1_CHA1 GPIO_HRTIM1_CHA1_0 +#define GPIO_HRTIM1_CHA2 GPIO_HRTIM1_CHA2_0 +#define GPIO_HRTIM1_CHB1 GPIO_HRTIM1_CHB1_0 +#define GPIO_HRTIM1_CHB2 GPIO_HRTIM1_CHB2_0 +#define GPIO_HRTIM1_CHC1 GPIO_HRTIM1_CHC1_0 +#define GPIO_HRTIM1_CHC2 GPIO_HRTIM1_CHC2_0 +#define GPIO_HRTIM1_CHD1 GPIO_HRTIM1_CHD1_0 +#define GPIO_HRTIM1_CHD2 GPIO_HRTIM1_CHD2_0 +#define GPIO_HRTIM1_CHE1 GPIO_HRTIM1_CHE1_0 +#define GPIO_HRTIM1_CHE2 GPIO_HRTIM1_CHE2_0 + +#endif /* __BOARDS_ARM_STM32_NUCLEO_F334R8_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32f3/nucleo-f334r8/scripts/Make.defs b/boards/arm/stm32f3/nucleo-f334r8/scripts/Make.defs new file mode 100644 index 0000000000000..26228f81667ec --- /dev/null +++ b/boards/arm/stm32f3/nucleo-f334r8/scripts/Make.defs @@ -0,0 +1,41 @@ +############################################################################ +# boards/arm/stm32f3/nucleo-f334r8/scripts/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/.config +include $(TOPDIR)/tools/Config.mk +include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs + +LDSCRIPT = ld.script +ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) + +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32f3/nucleo-f334r8/scripts/ld.script b/boards/arm/stm32f3/nucleo-f334r8/scripts/ld.script new file mode 100644 index 0000000000000..83850802f0114 --- /dev/null +++ b/boards/arm/stm32f3/nucleo-f334r8/scripts/ld.script @@ -0,0 +1,127 @@ +/**************************************************************************** + * boards/arm/stm32f3/nucleo-f334r8/scripts/ld.script + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* The STM32F334R8 has 64Kb of FLASH beginning at address 0x0800:0000, + * 12Kb of SRAM and 4Kb of CCM SRAM. + * + * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 + * where the code expects to begin execution by jumping to the entry point in + * the 0x0800:0000 address range. + */ + +MEMORY +{ + flash (rx) : ORIGIN = 0x08000000, LENGTH = 64K + sram (rwx) : ORIGIN = 0x20000000, LENGTH = 12K +} + +OUTPUT_ARCH(arm) +EXTERN(_vectors) +ENTRY(_stext) +SECTIONS +{ + .text : { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > flash + + .init_section : ALIGN(4) { + _sinit = ABSOLUTE(.); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) + _einit = ABSOLUTE(.); + } > flash + + .ARM.extab : ALIGN(4) { + *(.ARM.extab*) + } > flash + + .ARM.exidx : ALIGN(4) { + __exidx_start = ABSOLUTE(.); + *(.ARM.exidx*) + __exidx_end = ABSOLUTE(.); + } > flash + + .tdata : { + _stdata = ABSOLUTE(.); + *(.tdata .tdata.* .gnu.linkonce.td.*); + _etdata = ABSOLUTE(.); + } > flash + + .tbss : { + _stbss = ABSOLUTE(.); + *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); + _etbss = ABSOLUTE(.); + } > flash + + _eronly = ABSOLUTE(.); + + /* The RAM vector table (if present) should lie at the beginning of SRAM */ + + .ram_vectors : { + *(.ram_vectors) + } > sram + + .data : ALIGN(4) { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > sram AT > flash + + .bss : ALIGN(4) { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + _ebss = ABSOLUTE(.); + } > sram + + /* Stabs debugging sections. */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/stm32f3/nucleo-f334r8/src/CMakeLists.txt b/boards/arm/stm32f3/nucleo-f334r8/src/CMakeLists.txt new file mode 100644 index 0000000000000..e56987f9cbacb --- /dev/null +++ b/boards/arm/stm32f3/nucleo-f334r8/src/CMakeLists.txt @@ -0,0 +1,59 @@ +# ############################################################################## +# boards/arm/stm32f3/nucleo-f334r8/src/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(SRCS stm32_boot.c) + +if(CONFIG_ARCH_LEDS) + list(APPEND SRCS stm32_autoleds.c) +endif() + +if(CONFIG_ADC) + list(APPEND SRCS stm32_adc.c) +endif() + +if(CONFIG_DAC) + list(APPEND SRCS stm32_dac.c) +endif() + +if(CONFIG_STM32_HRTIM) + list(APPEND SRCS stm32_hrtim.c) +endif() + +if(CONFIG_COMP) + list(APPEND SRCS stm32_comp.c) +endif() + +if(CONFIG_OPAMP) + list(APPEND SRCS stm32_opamp.c) +endif() + +if(CONFIG_NUCLEOF334R8_HIGHPRI) + list(APPEND SRCS stm32_highpri.c) +endif() + +if(CONFIG_NUCLEOF334R8_SPWM) + list(APPEND SRCS stm32_spwm.c) +endif() + +target_sources(board PRIVATE ${SRCS}) + +set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/ld.script") diff --git a/boards/arm/stm32f3/nucleo-f334r8/src/Make.defs b/boards/arm/stm32f3/nucleo-f334r8/src/Make.defs new file mode 100644 index 0000000000000..a3a09d9253c52 --- /dev/null +++ b/boards/arm/stm32f3/nucleo-f334r8/src/Make.defs @@ -0,0 +1,61 @@ +############################################################################ +# boards/arm/stm32f3/nucleo-f334r8/src/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +CSRCS = stm32_boot.c + +ifeq ($(CONFIG_ARCH_LEDS),y) +CSRCS += stm32_autoleds.c +endif + +ifeq ($(CONFIG_ADC),y) +CSRCS += stm32_adc.c +endif + +ifeq ($(CONFIG_DAC),y) +CSRCS += stm32_dac.c +endif + +ifeq ($(CONFIG_STM32_HRTIM),y) +CSRCS += stm32_hrtim.c +endif + +ifeq ($(CONFIG_COMP),y) +CSRCS += stm32_comp.c +endif + +ifeq ($(CONFIG_OPAMP),y) +CSRCS += stm32_opamp.c +endif + +ifeq ($(CONFIG_NUCLEOF334R8_HIGHPRI),y) +CSRCS += stm32_highpri.c +endif + +ifeq ($(CONFIG_NUCLEOF334R8_SPWM),y) +CSRCS += stm32_spwm.c +endif + +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/nucleo-f334r8/src/nucleo-f334r8.h b/boards/arm/stm32f3/nucleo-f334r8/src/nucleo-f334r8.h similarity index 99% rename from boards/arm/stm32/nucleo-f334r8/src/nucleo-f334r8.h rename to boards/arm/stm32f3/nucleo-f334r8/src/nucleo-f334r8.h index ddcab273b090b..b2a0f7c72f4dd 100644 --- a/boards/arm/stm32/nucleo-f334r8/src/nucleo-f334r8.h +++ b/boards/arm/stm32f3/nucleo-f334r8/src/nucleo-f334r8.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f334r8/src/nucleo-f334r8.h + * boards/arm/stm32f3/nucleo-f334r8/src/nucleo-f334r8.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f3/nucleo-f334r8/src/stm32_adc.c b/boards/arm/stm32f3/nucleo-f334r8/src/stm32_adc.c new file mode 100644 index 0000000000000..d6530730994c9 --- /dev/null +++ b/boards/arm/stm32f3/nucleo-f334r8/src/stm32_adc.c @@ -0,0 +1,242 @@ +/**************************************************************************** + * boards/arm/stm32f3/nucleo-f334r8/src/stm32_adc.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "stm32.h" + +#if defined(CONFIG_ADC) && (defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2)) + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* 1 or 2 ADC devices (DEV1, DEV2) */ + +#if defined(CONFIG_STM32_ADC1) +# define DEV1_PORT 1 +#endif + +#if defined(CONFIG_STM32_ADC2) +# if defined(DEV1_PORT) +# define DEV2_PORT 2 +# else +# define DEV1_PORT 2 +# endif +#endif + +/* The number of ADC channels in the conversion list */ + +/* TODO DMA */ + +#define ADC1_NCHANNELS 3 +#define ADC2_NCHANNELS 3 + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* DEV 1 */ + +#if DEV1_PORT == 1 + +#define DEV1_NCHANNELS ADC1_NCHANNELS + +/* Identifying number of each ADC channel (even if NCHANNELS is less ) */ + +static const uint8_t g_chanlist1[3] = +{ + 1, + 2, + 11 +}; + +/* Configurations of pins used by each ADC channel */ + +static const uint32_t g_pinlist1[3] = +{ + GPIO_ADC1_IN1_0, /* PA0/A0 */ + GPIO_ADC1_IN2_0, /* PA1/A1 */ + GPIO_ADC1_IN11_0, /* PB0/A3 */ +}; + +#elif DEV1_PORT == 2 + +#define DEV1_NCHANNELS ADC2_NCHANNELS + +/* Identifying number of each ADC channel */ + +static const uint8_t g_chanlist1[3] = +{ + 1, + 6, + 7 +}; + +/* Configurations of pins used by each ADC channel */ + +static const uint32_t g_pinlist1[3] = +{ + GPIO_ADC2_IN1_0, /* PA4/A2 */ + GPIO_ADC2_IN7_0, /* PC1/A4 */ + GPIO_ADC2_IN6_0, /* PC0/A5 */ +}; + +#endif /* DEV1_PORT == 1 */ + +#ifdef DEV2_PORT + +/* DEV 2 */ + +#if DEV2_PORT == 2 + +#define DEV2_NCHANNELS ADC2_NCHANNELS + +/* Identifying number of each ADC channel */ + +static const uint8_t g_chanlist2[3] = +{ + 1, + 6, + 7 +}; + +/* Configurations of pins used by each ADC channel */ + +static const uint32_t g_pinlist2[3] = +{ + GPIO_ADC2_IN1_0, /* PA4/A2 */ + GPIO_ADC2_IN7_0, /* PC1/A4 */ + GPIO_ADC2_IN6_0, /* PC0/A5 */ +}; + +#endif /* DEV2_PORT == 2 */ +#endif /* DEV2_PORT */ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_adc_setup + * + * Description: + * Initialize ADC and register the ADC driver. + * + ****************************************************************************/ + +int stm32_adc_setup(void) +{ + static bool initialized = false; + struct adc_dev_s *adc; + int ret; + int i; + + /* Check if we have already initialized */ + + if (!initialized) + { + /* DEV1 */ + + /* Configure the pins as analog inputs for the selected channels */ + + for (i = 0; i < DEV1_NCHANNELS; i++) + { + stm32_configgpio(g_pinlist1[i]); + } + + /* Call stm32_adcinitialize() to get an instance of the ADC interface */ + + adc = stm32_adcinitialize(DEV1_PORT, g_chanlist1, DEV1_NCHANNELS); + if (adc == NULL) + { + aerr("ERROR: Failed to get ADC interface 1\n"); + return -ENODEV; + } + + /* Register the ADC driver at "/dev/adc0" */ + + ret = adc_register("/dev/adc0", adc); + if (ret < 0) + { + aerr("ERROR: adc_register /dev/adc0 failed: %d\n", ret); + return ret; + } + +#ifdef DEV2_PORT + + /* DEV2 */ + + /* Configure the pins as analog inputs for the selected channels */ + + for (i = 0; i < DEV2_NCHANNELS; i++) + { + stm32_configgpio(g_pinlist2[i]); + } + + /* Call stm32_adcinitialize() to get an instance of the ADC interface */ + + adc = stm32_adcinitialize(DEV2_PORT, g_chanlist2, DEV2_NCHANNELS); + if (adc == NULL) + { + aerr("ERROR: Failed to get ADC interface 2\n"); + return -ENODEV; + } + + /* Register the ADC driver at "/dev/adc1" */ + + ret = adc_register("/dev/adc1", adc); + if (ret < 0) + { + aerr("ERROR: adc_register /dev/adc1 failed: %d\n", ret); + return ret; + } +#endif + + initialized = true; + } + + return OK; +} + +#endif /* CONFIG_ADC && (CONFIG_STM32_ADC1 || CONFIG_STM32_ADC2) */ diff --git a/boards/arm/stm32f3/nucleo-f334r8/src/stm32_autoleds.c b/boards/arm/stm32f3/nucleo-f334r8/src/stm32_autoleds.c new file mode 100644 index 0000000000000..a108db4e5e303 --- /dev/null +++ b/boards/arm/stm32f3/nucleo-f334r8/src/stm32_autoleds.c @@ -0,0 +1,80 @@ +/**************************************************************************** + * boards/arm/stm32f3/nucleo-f334r8/src/stm32_autoleds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "stm32.h" +#include "nucleo-f334r8.h" + +#ifdef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_autoled_initialize + ****************************************************************************/ + +void board_autoled_initialize(void) +{ + /* Configure LED1 GPIO for output */ + + stm32_configgpio(GPIO_LED1); +} + +/**************************************************************************** + * Name: board_autoled_on + ****************************************************************************/ + +void board_autoled_on(int led) +{ + if (led == BOARD_LED1) + { + stm32_gpiowrite(GPIO_LED1, true); + } +} + +/**************************************************************************** + * Name: board_autoled_off + ****************************************************************************/ + +void board_autoled_off(int led) +{ + if (led == BOARD_LED1) + { + stm32_gpiowrite(GPIO_LED1, false); + } +} + +#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32f3/nucleo-f334r8/src/stm32_boot.c b/boards/arm/stm32f3/nucleo-f334r8/src/stm32_boot.c new file mode 100644 index 0000000000000..69051c8f1b3e0 --- /dev/null +++ b/boards/arm/stm32f3/nucleo-f334r8/src/stm32_boot.c @@ -0,0 +1,162 @@ +/**************************************************************************** + * boards/arm/stm32f3/nucleo-f334r8/src/stm32_boot.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include +#include + +#include "nucleo-f334r8.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#undef HAVE_LEDS +#undef HAVE_DAC + +#if !defined(CONFIG_ARCH_LEDS) && defined(CONFIG_USERLED_LOWER) +# define HAVE_LEDS 1 +#endif + +#if defined(CONFIG_DAC) +# define HAVE_DAC1 1 +# define HAVE_DAC2 1 +#endif + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_boardinitialize + * + * Description: + * All STM32 architectures must provide the following entry point. This + * entry point is called early in the initialization -- after all memory + * has been configured and mapped but before any devices have been + * initialized. + * + ****************************************************************************/ + +void stm32_boardinitialize(void) +{ +#ifdef CONFIG_ARCH_LEDS + /* Configure on-board LEDs if LED support has been selected. */ + + board_autoled_initialize(); +#endif +} + +/**************************************************************************** + * Name: board_late_initialize + * + * Description: + * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_late_initialize(). board_late_initialize() will + * be called immediately after up_initialize() is called and just before + * the initial application is started. This additional initialization + * phase may be used, for example, to initialize board-specific device + * drivers. + * + ****************************************************************************/ + +#ifdef CONFIG_BOARD_LATE_INITIALIZE +void board_late_initialize(void) +{ + int ret; + +#ifdef HAVE_LEDS + /* Register the LED driver */ + + ret = userled_lower_initialize(LED_DRIVER_PATH); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: userled_lower_initialize() failed: %d\n", ret); + return; + } +#endif + +#ifdef CONFIG_ADC + /* Initialize ADC and register the ADC driver. */ + + ret = stm32_adc_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_adc_setup failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_DAC + /* Initialize DAC and register the DAC driver. */ + + ret = stm32_dac_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_dac_setup failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_COMP + /* Initialize COMP and register the COMP driver. */ + + ret = stm32_comp_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_comp_setup failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_OPAMP + /* Initialize OPAMP and register the OPAMP driver. */ + + ret = stm32_opamp_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_opamp_setup failed: %d\n", ret); + } +#endif + + UNUSED(ret); +} +#endif diff --git a/boards/arm/stm32f3/nucleo-f334r8/src/stm32_comp.c b/boards/arm/stm32f3/nucleo-f334r8/src/stm32_comp.c new file mode 100644 index 0000000000000..cc95203cb1e4e --- /dev/null +++ b/boards/arm/stm32f3/nucleo-f334r8/src/stm32_comp.c @@ -0,0 +1,122 @@ +/**************************************************************************** + * boards/arm/stm32f3/nucleo-f334r8/src/stm32_comp.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "stm32.h" + +#if defined(CONFIG_COMP) && (defined(CONFIG_STM32_COMP2) || \ + defined(CONFIG_STM32_COMP4) || \ + defined(CONFIG_STM32_COMP6)) + +#ifdef CONFIG_STM32_COMP2 +# if defined(CONFIG_STM32_COMP4) || defined(CONFIG_STM32_COMP6) +# error "Currently only one COMP device supported" +# endif +#elif CONFIG_STM32_COMP4 +# if defined(CONFIG_STM32_COMP2) || defined(CONFIG_STM32_COMP6) +# error "Currently only one COMP device supported" +# endif +#elif CONFIG_STM32_COMP6 +# if defined(CONFIG_STM32_COMP2) || defined(CONFIG_STM32_COMP4) +# error "Currently only one COMP device supported" +# endif +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_comp_setup + * + * Description: + * Initialize COMP + * + ****************************************************************************/ + +int stm32_comp_setup(void) +{ + static bool initialized = false; + struct comp_dev_s *comp = NULL; + int ret; + + if (!initialized) + { + /* Get the comparator interface */ + +#ifdef CONFIG_STM32_COMP2 + comp = stm32_compinitialize(2); + if (comp == NULL) + { + aerr("ERROR: Failed to get COMP%d interface\n", 2); + return -ENODEV; + } +#endif + +#ifdef CONFIG_STM32_COMP4 + comp = stm32_compinitialize(4); + if (comp == NULL) + { + aerr("ERROR: Failed to get COMP%d interface\n", 4); + return -ENODEV; + } +#endif + +#ifdef CONFIG_STM32_COMP6 + comp = stm32_compinitialize(6); + if (comp == NULL) + { + aerr("ERROR: Failed to get COMP%d interface\n", 6); + return -ENODEV; + } +#endif + + /* Register the comparator character driver at /dev/comp0 */ + + ret = comp_register("/dev/comp0", comp); + if (ret < 0) + { + aerr("ERROR: comp_register failed: %d\n", ret); + return ret; + } + + initialized = true; + } + + return OK; +} + +#endif /* CONFIG_COMP && (CONFIG_STM32_COMP1 || + * CONFIG_STM32_COMP2 + * CONFIG_STM32_COMP6) */ diff --git a/boards/arm/stm32f3/nucleo-f334r8/src/stm32_highpri.c b/boards/arm/stm32f3/nucleo-f334r8/src/stm32_highpri.c new file mode 100644 index 0000000000000..961fcdd3a3f00 --- /dev/null +++ b/boards/arm/stm32f3/nucleo-f334r8/src/stm32_highpri.c @@ -0,0 +1,586 @@ +/**************************************************************************** + * boards/arm/stm32f3/nucleo-f334r8/src/stm32_highpri.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include +#include + +#include "arm_internal.h" +#include "ram_vectors.h" + +#include "stm32_hrtim.h" +#include "stm32_pwm.h" +#include "stm32_adc.h" +#include "stm32_dma.h" + +#include + +#ifdef CONFIG_NUCLEOF334R8_HIGHPRI + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +#ifndef CONFIG_ARCH_HIPRI_INTERRUPT +# error CONFIG_ARCH_HIPRI_INTERRUPT is required +#endif + +#ifndef CONFIG_ARCH_RAMVECTORS +# error CONFIG_ARCH_RAMVECTORS is required +#endif + +#ifndef CONFIG_ARCH_IRQPRIO +# error CONFIG_ARCH_IRQPRIO is required +#endif + +#ifndef CONFIG_ARCH_FPU +# warning Set CONFIG_ARCH_FPU for hardware FPU support +#endif + +#ifdef CONFIG_STM32_ADC1_DMA +# if defined(CONFIG_STM32_HRTIM1) && defined(CONFIG_STM32_HRTIM_TIMA) +# define HIGHPRI_HAVE_HRTIM +# endif +# if defined(CONFIG_STM32_TIM1_PWM) +# define HIGHPRI_HAVE_TIM1 +# endif +# if (CONFIG_STM32_ADC1_DMA_CFG != 1) +# error ADC1 DMA must be configured in Circular Mode +# endif +# if defined(HIGHPRI_HAVE_HRTIM) && defined(HIGHPRI_HAVE_TIM1) +# error HRTIM TIM A or TIM1 ! +# elif !defined(HIGHPRI_HAVE_HRTIM) && !defined(HIGHPRI_HAVE_TIM1) +# error "Needs HRTIM TIMA or TIM1 to trigger ADC DMA" +# endif +#endif + +#ifdef HIGHPRI_HAVE_HRTIM +# if !defined(CONFIG_STM32_HRTIM_ADC1_TRG1) || !defined(CONFIG_STM32_HRTIM_ADC) +# error +# endif +#endif + +#if (CONFIG_STM32_ADC1_INJECTED_CHAN > 0) +# if (CONFIG_STM32_ADC1_INJECTED_CHAN > 2) +# error Max 2 injected channels supported for now +# else +# define HIGHPRI_HAVE_INJECTED +# endif +#endif + +#ifdef HIGHPRI_HAVE_INJECTED +# define INJ_NCHANNELS CONFIG_STM32_ADC1_INJECTED_CHAN +#else +# define INJ_NCHANNELS (0) +#endif + +#ifndef CONFIG_STM32_ADC1_DMA +# define REG_NCHANNELS (1) +#else +# define REG_NCHANNELS (3) +#endif + +#define ADC1_NCHANNELS (REG_NCHANNELS + INJ_NCHANNELS) + +#define DEV1_PORT (1) +#define DEV1_NCHANNELS ADC1_NCHANNELS +#define ADC_REF_VOLTAGE (3.3f) +#define ADC_VAL_MAX (4095) + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/* High priority example private data */ + +struct highpri_s +{ + struct stm32_adc_dev_s *adc1; +#ifdef HIGHPRI_HAVE_HRTIM + struct hrtim_dev_s *hrtim; +#endif +#ifdef HIGHPRI_HAVE_TIM1 + struct stm32_pwm_dev_s *pwm; +#endif + volatile uint32_t cntr1; + volatile uint32_t cntr2; + volatile uint8_t current; + uint16_t r_val[REG_NCHANNELS]; + float r_volt[REG_NCHANNELS]; +#ifdef HIGHPRI_HAVE_INJECTED + uint16_t j_val[INJ_NCHANNELS]; + float j_volt[INJ_NCHANNELS]; +#endif + bool lock; +}; + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* ADC channel list */ + +static const uint8_t g_chanlist1[DEV1_NCHANNELS] = +{ + 1, +#ifdef CONFIG_STM32_ADC1_DMA + 2, + 11, +#endif +#if INJ_NCHANNELS > 0 + 7, +#endif +#if INJ_NCHANNELS > 1 + 6 +#endif +}; + +/* Configurations of pins used by ADC channel */ + +static const uint32_t g_pinlist1[DEV1_NCHANNELS] = +{ + GPIO_ADC1_IN1_0, /* PA0/A0 */ +#ifdef CONFIG_STM32_ADC1_DMA + GPIO_ADC1_IN2_0, /* PA1/A1 */ + GPIO_ADC1_IN11_0, /* PB0/A3 */ +#endif +#if INJ_NCHANNELS > 0 + GPIO_ADC1_IN7_0, /* PC1/A4 */ +#endif +#if INJ_NCHANNELS > 1 + GPIO_ADC1_IN6_0 /* PC0/A5 */ +#endif +}; + +static struct highpri_s g_highpri; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: adc12_handler + * + * Description: + * This is the handler for the high speed ADC interrupt. + * + ****************************************************************************/ + +#if !defined(CONFIG_STM32_ADC1_DMA) || defined(HIGHPRI_HAVE_INJECTED) +void adc12_handler(void) +{ + struct stm32_adc_dev_s *adc = g_highpri.adc1; + float ref = ADC_REF_VOLTAGE; + float bit = ADC_VAL_MAX; + uint32_t pending; +#ifdef HIGHPRI_HAVE_INJECTED + int i = 0; +#endif + + /* Get pending ADC interrupts */ + + pending = STM32_ADC_INT_GET(adc); + + if (g_highpri.lock == true) + { + goto irq_out; + } + +#ifndef CONFIG_STM32_ADC1_DMA + /* Regular channel end of conversion */ + + if (pending & ADC_ISR_EOC) + { + /* Increase regular sequence counter */ + + g_highpri.cntr1 += 1; + + /* Get regular data */ + + g_highpri.r_val[g_highpri.current] = STM32_ADC_REGDATA_GET(adc); + + /* Do some floating point operations */ + + g_highpri.r_volt[g_highpri.current] = + (float)g_highpri.r_val[g_highpri.current] * ref / bit; + + if (g_highpri.current >= REG_NCHANNELS - 1) + { + g_highpri.current = 0; + } + else + { + g_highpri.current += 1; + } + } +#endif + +#ifdef HIGHPRI_HAVE_INJECTED + /* Injected channel end of sequence */ + + if (pending & ADC_ISR_JEOS) + { + /* Increase injected sequence counter */ + + g_highpri.cntr2 += 1; + + /* Get injected channels */ + + for (i = 0; i < INJ_NCHANNELS; i += 1) + { + g_highpri.j_val[i] = STM32_ADC_INJDATA_GET(adc, i); + } + + /* Do some floating point operations */ + + for (i = 0; i < INJ_NCHANNELS; i += 1) + { + g_highpri.j_volt[i] = (float)g_highpri.j_val[i] * ref / bit; + } + } +#endif + +irq_out: + + /* Clear ADC pending interrupts */ + + STM32_ADC_INT_ACK(adc, pending); +} +#endif + +/**************************************************************************** + * Name: dmach1_handler + * + * Description: + * This is the handler for the high speed ADC interrupt using DMA transfer. + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_ADC1_DMA +void dma1ch1_handler(void) +{ + float ref = ADC_REF_VOLTAGE; + float bit = ADC_VAL_MAX; + uint32_t pending; + int i; + + pending = stm32_dma_intget(STM32_DMA1_CHAN1); + + if (g_highpri.lock == true) + { + goto irq_out; + } + + /* Increase regular sequence counter */ + + g_highpri.cntr1 += 1; + + for (i = 0; i < REG_NCHANNELS; i += 1) + { + /* Do some floating point operations */ + + g_highpri.r_volt[i] = (float)g_highpri.r_val[i] * ref / bit; + } + +irq_out: + + /* Clear DMA pending interrupts */ + + stm32_dma_intack(STM32_DMA1_CHAN1, pending); +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: highpri_main + * + * Description: + * Main entry point in into the high priority interrupt test. + * + ****************************************************************************/ + +int highpri_main(int argc, char *argv[]) +{ +#ifdef HIGHPRI_HAVE_HRTIM + struct hrtim_dev_s *hrtim; +#endif +#ifdef HIGHPRI_HAVE_TIM1 + struct stm32_pwm_dev_s *pwm1; +#endif + struct adc_dev_s *adc1; + struct highpri_s *highpri; + int ret; + int i; + + highpri = &g_highpri; + + /* Initialize highpri structure */ + + memset(highpri, 0, sizeof(struct highpri_s)); + + printf("\nhighpri_main: Started\n"); + + /* Configure the pins as analog inputs for the selected channels */ + + for (i = 0; i < DEV1_NCHANNELS; i++) + { + stm32_configgpio(g_pinlist1[i]); + } + + /* Initialize ADC driver */ + + adc1 = stm32_adcinitialize(DEV1_PORT, g_chanlist1, DEV1_NCHANNELS); + if (adc1 == NULL) + { + aerr("ERROR: Failed to get ADC interface 1\n"); + ret = EXIT_FAILURE; + goto errout; + } + + highpri->adc1 = (struct stm32_adc_dev_s *)adc1->ad_priv; + +#ifdef HIGHPRI_HAVE_HRTIM + /* Configure HRTIM */ + + hrtim = stm32_hrtiminitialize(); + if (hrtim == NULL) + { + printf("ERROR: Failed to get HRTIM1 interface\n"); + ret = EXIT_FAILURE; + goto errout; + } + + highpri->hrtim = hrtim; + + /* Set Timer A Period */ + + HRTIM_PER_SET(hrtim, HRTIM_TIMER_TIMA, 0xffd0); +#endif /* HIGHPRI_HAVE_HRTIM */ + +#ifdef HIGHPRI_HAVE_TIM1 + /* Initialize TIM1 */ + + pwm1 = (struct stm32_pwm_dev_s *) stm32_pwminitialize(1); + if (pwm1 == NULL) + { + printf("ERROR: Failed to get PWM1 interface\n"); + ret = EXIT_FAILURE; + goto errout; + } + + highpri->pwm = pwm1; + + /* Setup PWM device */ + + PWM_SETUP(pwm1); + + /* Set timer frequency */ + + PWM_FREQ_UPDATE(pwm1, 1000); + + /* Set CCR1 */ + + PWM_CCR_UPDATE(pwm1, 1, 0x0f00); + + /* Enable TIM1 OUT1 */ + + PWM_OUTPUTS_ENABLE(pwm1, STM32_PWM_OUT1, true); + +#ifdef CONFIG_DEBUG_PWM_INFO + /* Print debug */ + + PWM_DUMP_REGS(pwm1); +#endif + +#endif /* HIGHPRI_HAVE_TIM1 */ + +#if !defined(CONFIG_STM32_ADC1_DMA) || defined(HIGHPRI_HAVE_INJECTED) + /* Attach ADC12 ram vector if no DMA or injected channels support */ + + ret = arm_ramvec_attach(STM32_IRQ_ADC12, adc12_handler); + if (ret < 0) + { + fprintf(stderr, "highpri_main: ERROR: arm_ramvec_attach failed: %d\n", + ret); + ret = EXIT_FAILURE; + goto errout; + } + + /* Set the priority of the ADC12 interrupt vector */ + + ret = up_prioritize_irq(STM32_IRQ_ADC12, NVIC_SYSH_HIGH_PRIORITY); + if (ret < 0) + { + fprintf(stderr, "highpri_main: ERROR: up_prioritize_irq failed: %d\n", + ret); + ret = EXIT_FAILURE; + goto errout; + } + + up_enable_irq(STM32_IRQ_ADC12); +#endif + +#ifdef CONFIG_STM32_ADC1_DMA + /* Attach DMA1 CH1 ram vector if DMA */ + + ret = arm_ramvec_attach(STM32_IRQ_DMA1CH1, dma1ch1_handler); + if (ret < 0) + { + fprintf(stderr, "highpri_main: ERROR: arm_ramvec_attach failed: %d\n", + ret); + ret = EXIT_FAILURE; + goto errout; + } + + /* Set the priority of the DMA1CH1 interrupt vector */ + + ret = up_prioritize_irq(STM32_IRQ_DMA1CH1, NVIC_SYSH_HIGH_PRIORITY); + if (ret < 0) + { + fprintf(stderr, "highpri_main: ERROR: up_prioritize_irq failed: %d\n", + ret); + ret = EXIT_FAILURE; + goto errout; + } + + up_enable_irq(STM32_IRQ_DMA1CH1); +#endif + + /* Setup ADC hardware */ + + adc1->ad_ops->ao_setup(adc1); + + /* Configure regular channels trigger to T1CC1 */ + + STM32_ADC_EXTCFG_SET(highpri->adc1, + ADC1_EXTSEL_T1CC1 | ADC_EXTREG_EXTEN_DEFAULT); + +#ifndef CONFIG_STM32_ADC1_DMA + /* Enable ADC regular conversion interrupts if no DMA */ + + STM32_ADC_INT_ENABLE(highpri->adc1, ADC_IER_EOC); +#else + /* Register ADC buffer for DMA transfer */ + + STM32_ADC_REGBUF_REGISTER(highpri->adc1, g_highpri.r_val, REG_NCHANNELS); +#endif + +#ifdef HIGHPRI_HAVE_INJECTED + /* Enable ADC injected sequence end interrupts */ + + STM32_ADC_INT_ENABLE(highpri->adc1, ADC_IER_JEOS); +#endif + +#ifdef HIGHPRI_HAVE_HRTIM + /* Enable HRTIM TIMA after ADC configuration */ + + HRTIM_TIM_ENABLE(highpri->hrtim, HRTIM_TIMER_TIMA, true); +#endif + +#ifdef HIGHPRI_HAVE_TIM1 + /* Enable timer counter after ADC configuration */ + + PWM_TIM_ENABLE(pwm1, true); +#endif + + while (1) + { +#ifndef CONFIG_STM32_ADC1_DMA + /* Software trigger for regular sequence */ + + adc1->ad_ops->ao_ioctl(adc1, IO_TRIGGER_REG, 0); + + nxsched_usleep(100); +#endif + +#ifdef HIGHPRI_HAVE_INJECTED + /* Software trigger for injected sequence */ + + adc1->ad_ops->ao_ioctl(adc1, IO_TRIGGER_INJ, 0); + + nxsched_usleep(100); +#endif + /* Lock global data */ + + g_highpri.lock = true; + +#ifndef CONFIG_STM32_ADC1_DMA + printf("%" PRId32 " [%d] %0.3fV\n", g_highpri.cntr1, g_highpri.current, + g_highpri.r_volt[g_highpri.current]); +#else + printf("%" PRId32 " ", g_highpri.cntr1); + + for (i = 0; i < REG_NCHANNELS; i += 1) + { + printf("r:[%d] %0.3fV, ", i, g_highpri.r_volt[i]); + } + + printf("\n"); +#endif + +#ifdef HIGHPRI_HAVE_INJECTED + /* Print data from injected channels */ + + printf("%" PRId32 " ", g_highpri.cntr2); + + for (i = 0; i < INJ_NCHANNELS; i += 1) + { + printf("j:[%d] %0.3fV, ", i, g_highpri.j_volt[i]); + } + + printf("\n"); +#endif + /* Unlock global data */ + + g_highpri.lock = false; + + nxsched_sleep(1); + } + +errout: + return ret; +} + +#endif /* CONFIG_NUCLEOF334R8_HIGHPRI */ diff --git a/boards/arm/stm32f3/nucleo-f334r8/src/stm32_hrtim.c b/boards/arm/stm32f3/nucleo-f334r8/src/stm32_hrtim.c new file mode 100644 index 0000000000000..6e33327441494 --- /dev/null +++ b/boards/arm/stm32f3/nucleo-f334r8/src/stm32_hrtim.c @@ -0,0 +1,86 @@ +/**************************************************************************** + * boards/arm/stm32f3/nucleo-f334r8/src/stm32_hrtim.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include + +#include "stm32_hrtim.h" + +#ifndef CONFIG_STM32_HRTIM_DISABLE_CHARDRV + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_hrtim_setup + * + * Description: + * Initialize HRTIM driver + * + * Returned Value: + * 0 on success, a negated errno value on failure + * + ****************************************************************************/ + +int stm32_hrtim_setup(void) +{ + static bool initialized = false; + struct hrtim_dev_s *hrtim = NULL; + int ret; + + if (!initialized) + { + /* Get the HRTIM interface */ + + hrtim = stm32_hrtiminitialize(); + if (hrtim == NULL) + { + tmrerr("ERROR: Failed to get HRTIM1 interface\n"); + return -ENODEV; + } + + /* Register the HRTIM character driver at /dev/hrtim0 */ + + ret = hrtim_register("/dev/hrtim0", hrtim); + if (ret < 0) + { + tmrerr("ERROR: hrtim_register failed: %d\n", ret); + return ret; + } + + initialized = true; + } + + return OK; +} + +#endif /* CONFIG_STM32_HRTIM && CONFIG_STM32_HRTIM1 */ diff --git a/boards/arm/stm32f3/nucleo-f334r8/src/stm32_opamp.c b/boards/arm/stm32f3/nucleo-f334r8/src/stm32_opamp.c new file mode 100644 index 0000000000000..33a3febc2ab3e --- /dev/null +++ b/boards/arm/stm32f3/nucleo-f334r8/src/stm32_opamp.c @@ -0,0 +1,86 @@ +/**************************************************************************** + * boards/arm/stm32f3/nucleo-f334r8/src/stm32_opamp.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "stm32.h" + +#if defined(CONFIG_OPAMP) && defined(CONFIG_STM32_OPAMP2) + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_opamp_setup + * + * Description: + * Initialize OPAMP + * + ****************************************************************************/ + +int stm32_opamp_setup(void) +{ + static bool initialized = false; + struct opamp_dev_s *opamp = NULL; + int ret; + + if (!initialized) + { + /* Get the OPAMP interface */ + +#ifdef CONFIG_STM32_OPAMP2 + opamp = stm32_opampinitialize(2); + if (opamp == NULL) + { + aerr("ERROR: Failed to get OPAMP%d interface\n", 2); + return -ENODEV; + } +#endif + + /* Register the OPAMP character driver at /dev/opamp0 */ + + ret = opamp_register("/dev/opamp0", opamp); + if (ret < 0) + { + aerr("ERROR: opamp_register failed: %d\n", ret); + return ret; + } + + initialized = true; + } + + return OK; +} + +#endif /* CONFIG_OPAMP && CONFIG_STM32_OPAMP2 */ diff --git a/boards/arm/stm32/nucleo-f334r8/src/stm32_spwm.c b/boards/arm/stm32f3/nucleo-f334r8/src/stm32_spwm.c similarity index 99% rename from boards/arm/stm32/nucleo-f334r8/src/stm32_spwm.c rename to boards/arm/stm32f3/nucleo-f334r8/src/stm32_spwm.c index 1bb93258e20ab..3fd7576b0120c 100644 --- a/boards/arm/stm32/nucleo-f334r8/src/stm32_spwm.c +++ b/boards/arm/stm32f3/nucleo-f334r8/src/stm32_spwm.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f334r8/src/stm32_spwm.c + * boards/arm/stm32f3/nucleo-f334r8/src/stm32_spwm.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f3/stm32f334-disco/CMakeLists.txt b/boards/arm/stm32f3/stm32f334-disco/CMakeLists.txt new file mode 100644 index 0000000000000..25937ad493c21 --- /dev/null +++ b/boards/arm/stm32f3/stm32f334-disco/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32f3/stm32f334-disco/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/arm/stm32/stm32f334-disco/Kconfig b/boards/arm/stm32f3/stm32f334-disco/Kconfig similarity index 100% rename from boards/arm/stm32/stm32f334-disco/Kconfig rename to boards/arm/stm32f3/stm32f334-disco/Kconfig diff --git a/boards/arm/stm32f3/stm32f334-disco/configs/buckboost/defconfig b/boards/arm/stm32f3/stm32f334-disco/configs/buckboost/defconfig new file mode 100644 index 0000000000000..2736b34ef80b1 --- /dev/null +++ b/boards/arm/stm32f3/stm32f334-disco/configs/buckboost/defconfig @@ -0,0 +1,129 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_SYSTEM_DD is not set +CONFIG_ADC=y +CONFIG_ANALOG=y +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f334-disco" +CONFIG_ARCH_BOARD_STM32F334_DISCO=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f3" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F334C8=y +CONFIG_ARCH_CHIP_STM32F3=y +CONFIG_ARCH_HIPRI_INTERRUPT=y +CONFIG_ARCH_RAMVECTORS=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_DISABLE_ENVIRON=y +CONFIG_DISABLE_MQUEUE=y +CONFIG_DISABLE_POSIX_TIMERS=y +CONFIG_DISABLE_PTHREAD=y +CONFIG_DRIVERS_SMPS=y +CONFIG_EXAMPLES_SMPS=y +CONFIG_EXAMPLES_SMPS_DEVPATH="/dev/smps0" +CONFIG_EXAMPLES_SMPS_IN_VOLTAGE_LIMIT=10000 +CONFIG_EXAMPLES_SMPS_OUT_CURRENT_LIMIT=100 +CONFIG_EXAMPLES_SMPS_OUT_POWER_LIMIT=100 +CONFIG_EXAMPLES_SMPS_OUT_VOLTAGE_DEFAULT=5000 +CONFIG_EXAMPLES_SMPS_OUT_VOLTAGE_LIMIT=10000 +CONFIG_EXAMPLES_SMPS_TIME_DEFAULT=10 +CONFIG_FDCLONE_STDIO=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=1024 +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBDSP=y +CONFIG_LIBM=y +CONFIG_LINE_MAX=64 +CONFIG_NAME_MAX=16 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_DISABLE_BASENAME=y +CONFIG_NSH_DISABLE_CAT=y +CONFIG_NSH_DISABLE_CD=y +CONFIG_NSH_DISABLE_CMP=y +CONFIG_NSH_DISABLE_CP=y +CONFIG_NSH_DISABLE_DF=y +CONFIG_NSH_DISABLE_DIRNAME=y +CONFIG_NSH_DISABLE_ECHO=y +CONFIG_NSH_DISABLE_EXEC=y +CONFIG_NSH_DISABLE_EXIT=y +CONFIG_NSH_DISABLE_FREE=y +CONFIG_NSH_DISABLE_GET=y +CONFIG_NSH_DISABLE_HELP=y +CONFIG_NSH_DISABLE_HEXDUMP=y +CONFIG_NSH_DISABLE_KILL=y +CONFIG_NSH_DISABLE_LOSETUP=y +CONFIG_NSH_DISABLE_LS=y +CONFIG_NSH_DISABLE_MKDIR=y +CONFIG_NSH_DISABLE_MKRD=y +CONFIG_NSH_DISABLE_MOUNT=y +CONFIG_NSH_DISABLE_MV=y +CONFIG_NSH_DISABLE_PUT=y +CONFIG_NSH_DISABLE_PWD=y +CONFIG_NSH_DISABLE_RM=y +CONFIG_NSH_DISABLE_RMDIR=y +CONFIG_NSH_DISABLE_SET=y +CONFIG_NSH_DISABLE_SLEEP=y +CONFIG_NSH_DISABLE_SOURCE=y +CONFIG_NSH_DISABLE_TEST=y +CONFIG_NSH_DISABLE_TIME=y +CONFIG_NSH_DISABLE_UMOUNT=y +CONFIG_NSH_DISABLE_UNAME=y +CONFIG_NSH_DISABLE_UNSET=y +CONFIG_NSH_DISABLE_USLEEP=y +CONFIG_NSH_DISABLE_WGET=y +CONFIG_NSH_DISABLE_XD=y +CONFIG_NSH_FILEIOSIZE=256 +CONFIG_NSH_READLINE=y +CONFIG_POSIX_SPAWN_DEFAULT_STACKSIZE=512 +CONFIG_PTHREAD_STACK_DEFAULT=1024 +CONFIG_PTHREAD_STACK_MIN=1024 +CONFIG_RAM_SIZE=12288 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_SMPS_HAVE_INPUT_VOLTAGE=y +CONFIG_SMPS_HAVE_OUTPUT_VOLTAGE=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_STDIO_BUFFER_SIZE=128 +CONFIG_STM32_ADC1=y +CONFIG_STM32_ADC1_INJECTED_CHAN=2 +CONFIG_STM32_ADC_CHANGE_SAMPLETIME=y +CONFIG_STM32_ADC_LL_OPS=y +CONFIG_STM32_ADC_NOIRQ=y +CONFIG_STM32_CCMEXCLUDE=y +CONFIG_STM32_HRTIM1=y +CONFIG_STM32_HRTIM_ADC1_TRG2=y +CONFIG_STM32_HRTIM_ADC=y +CONFIG_STM32_HRTIM_CLK_FROM_PLL=y +CONFIG_STM32_HRTIM_DEADTIME=y +CONFIG_STM32_HRTIM_DISABLE_CHARDRV=y +CONFIG_STM32_HRTIM_PWM=y +CONFIG_STM32_HRTIM_TIMA=y +CONFIG_STM32_HRTIM_TIMA_DT=y +CONFIG_STM32_HRTIM_TIMA_PWM=y +CONFIG_STM32_HRTIM_TIMA_PWM_CH1=y +CONFIG_STM32_HRTIM_TIMA_PWM_CH2=y +CONFIG_STM32_HRTIM_TIMB=y +CONFIG_STM32_HRTIM_TIMB_DT=y +CONFIG_STM32_HRTIM_TIMB_PWM=y +CONFIG_STM32_HRTIM_TIMB_PWM_CH1=y +CONFIG_STM32_HRTIM_TIMB_PWM_CH2=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_PWR=y +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f3/stm32f334-disco/configs/nsh/defconfig b/boards/arm/stm32f3/stm32f334-disco/configs/nsh/defconfig new file mode 100644 index 0000000000000..7bdc5a61d0faf --- /dev/null +++ b/boards/arm/stm32f3/stm32f334-disco/configs/nsh/defconfig @@ -0,0 +1,89 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_SYSTEM_DD is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f334-disco" +CONFIG_ARCH_BOARD_STM32F334_DISCO=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f3" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F334C8=y +CONFIG_ARCH_CHIP_STM32F3=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_ARM_TOOLCHAIN_BUILDROOT=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_DEBUG_FEATURES=y +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_DISABLE_ENVIRON=y +CONFIG_DISABLE_MQUEUE=y +CONFIG_DISABLE_POSIX_TIMERS=y +CONFIG_DISABLE_PTHREAD=y +CONFIG_EXAMPLES_HELLO=y +CONFIG_FDCLONE_STDIO=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=1024 +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_NAME_MAX=16 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_DISABLE_BASENAME=y +CONFIG_NSH_DISABLE_CAT=y +CONFIG_NSH_DISABLE_CD=y +CONFIG_NSH_DISABLE_CMP=y +CONFIG_NSH_DISABLE_CP=y +CONFIG_NSH_DISABLE_DF=y +CONFIG_NSH_DISABLE_DIRNAME=y +CONFIG_NSH_DISABLE_EXEC=y +CONFIG_NSH_DISABLE_EXIT=y +CONFIG_NSH_DISABLE_GET=y +CONFIG_NSH_DISABLE_HEXDUMP=y +CONFIG_NSH_DISABLE_KILL=y +CONFIG_NSH_DISABLE_LOSETUP=y +CONFIG_NSH_DISABLE_LS=y +CONFIG_NSH_DISABLE_MKDIR=y +CONFIG_NSH_DISABLE_MKRD=y +CONFIG_NSH_DISABLE_MOUNT=y +CONFIG_NSH_DISABLE_MV=y +CONFIG_NSH_DISABLE_PUT=y +CONFIG_NSH_DISABLE_PWD=y +CONFIG_NSH_DISABLE_RM=y +CONFIG_NSH_DISABLE_RMDIR=y +CONFIG_NSH_DISABLE_SET=y +CONFIG_NSH_DISABLE_SLEEP=y +CONFIG_NSH_DISABLE_SOURCE=y +CONFIG_NSH_DISABLE_TEST=y +CONFIG_NSH_DISABLE_TIME=y +CONFIG_NSH_DISABLE_UMOUNT=y +CONFIG_NSH_DISABLE_UNAME=y +CONFIG_NSH_DISABLE_UNSET=y +CONFIG_NSH_DISABLE_USLEEP=y +CONFIG_NSH_DISABLE_WGET=y +CONFIG_NSH_DISABLE_XD=y +CONFIG_NSH_FILEIOSIZE=256 +CONFIG_NSH_READLINE=y +CONFIG_POSIX_SPAWN_DEFAULT_STACKSIZE=512 +CONFIG_PTHREAD_STACK_DEFAULT=1024 +CONFIG_PTHREAD_STACK_MIN=1024 +CONFIG_RAM_SIZE=12288 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_STM32_CCMEXCLUDE=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_PWR=y +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f3/stm32f334-disco/configs/powerled/defconfig b/boards/arm/stm32f3/stm32f334-disco/configs/powerled/defconfig new file mode 100644 index 0000000000000..a6bccf5b39779 --- /dev/null +++ b/boards/arm/stm32f3/stm32f334-disco/configs/powerled/defconfig @@ -0,0 +1,99 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_DISABLE_POSIX_TIMERS is not set +# CONFIG_DISABLE_PSEUDOFS_OPERATIONS is not set +# CONFIG_NSH_DISABLEBG is not set +# CONFIG_NSH_DISABLESCRIPT is not set +# CONFIG_NSH_DISABLE_DMESG is not set +# CONFIG_NSH_DISABLE_ECHO is not set +# CONFIG_NSH_DISABLE_ENV is not set +# CONFIG_NSH_DISABLE_EXPORT is not set +# CONFIG_NSH_DISABLE_FREE is not set +# CONFIG_NSH_DISABLE_ITEF is not set +# CONFIG_NSH_DISABLE_LOOPS is not set +# CONFIG_NSH_DISABLE_LS is not set +# CONFIG_NSH_DISABLE_PRINTF is not set +# CONFIG_NSH_DISABLE_SEMICOLON is not set +# CONFIG_NSH_DISABLE_TRUNCATE is not set +# CONFIG_NSH_DISABLE_UPTIME is not set +CONFIG_ANALOG=y +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f334-disco" +CONFIG_ARCH_BOARD_STM32F334_DISCO=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f3" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F334C8=y +CONFIG_ARCH_CHIP_STM32F3=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_ARM_TOOLCHAIN_BUILDROOT=y +CONFIG_BOARDCTL=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_COMP=y +CONFIG_DAC=y +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_DEFAULT_SMALL=y +CONFIG_DRIVERS_POWERLED=y +CONFIG_EXAMPLES_POWERLED=y +CONFIG_EXAMPLES_POWERLED_CURRENT_LIMIT=100 +CONFIG_EXAMPLES_POWERLED_DEVPATH="/dev/powerled0" +CONFIG_FDCLONE_STDIO=y +CONFIG_FILE_STREAM=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=1024 +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_FLOATINGPOINT=y +CONFIG_LIBM=y +CONFIG_NAME_MAX=16 +CONFIG_NSH_ARGCAT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=256 +CONFIG_NSH_MAXARGUMENTS=16 +CONFIG_POSIX_SPAWN_DEFAULT_STACKSIZE=512 +CONFIG_PREALLOC_TIMERS=2 +CONFIG_PTHREAD_STACK_DEFAULT=1024 +CONFIG_PTHREAD_STACK_MIN=1024 +CONFIG_RAM_SIZE=12288 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_SIG_PREALLOC_IRQ_ACTIONS=8 +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_STM32_COMP4=y +CONFIG_STM32_DAC1=y +CONFIG_STM32_DAC1CH1=y +CONFIG_STM32_DAC1CH1_DMA=y +CONFIG_STM32_DAC1CH1_DMA_BUFFER_SIZE=5 +CONFIG_STM32_DAC1CH1_DMA_EXTERNAL=y +CONFIG_STM32_DMA1=y +CONFIG_STM32_HRTIM1=y +CONFIG_STM32_HRTIM_BURST=y +CONFIG_STM32_HRTIM_CLK_FROM_PLL=y +CONFIG_STM32_HRTIM_DISABLE_CHARDRV=y +CONFIG_STM32_HRTIM_DMA=y +CONFIG_STM32_HRTIM_EEV2=y +CONFIG_STM32_HRTIM_EVENTS=y +CONFIG_STM32_HRTIM_PWM=y +CONFIG_STM32_HRTIM_TIMC=y +CONFIG_STM32_HRTIM_TIMC_BURST=y +CONFIG_STM32_HRTIM_TIMC_BURST_CH1=y +CONFIG_STM32_HRTIM_TIMC_DMA=y +CONFIG_STM32_HRTIM_TIMC_PWM=y +CONFIG_STM32_HRTIM_TIMC_PWM_CH1=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_PWR=y +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f3/stm32f334-disco/include/board.h b/boards/arm/stm32f3/stm32f334-disco/include/board.h new file mode 100644 index 0000000000000..b4c5ffeca08aa --- /dev/null +++ b/boards/arm/stm32f3/stm32f334-disco/include/board.h @@ -0,0 +1,337 @@ +/**************************************************************************** + * boards/arm/stm32f3/stm32f334-disco/include/board.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_STM32_STM32F334_DISCO_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32_STM32F334_DISCO_INCLUDE_BOARD_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#ifndef __ASSEMBLY__ +# include +# include +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Clocking *****************************************************************/ + +/* HSI - Internal 8 MHz RC Oscillator + * LSI - 32 KHz RC + * HSE - 8 MHz from MCO output of ST-LINK + * LSE - 32.768 kHz + */ + +#define STM32_BOARD_XTAL 8000000ul + +#define STM32_HSI_FREQUENCY 8000000ul +#define STM32_LSI_FREQUENCY 32000 /* Between 30kHz and 60kHz */ +#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL +#define STM32_LSE_FREQUENCY 32768 /* X2 on board */ + +/* PLL source is HSE/1, PLL multiplier is 9: + * PLL frequency is 8MHz (XTAL) x 9 = 72MHz + */ + +#define STM32_CFGR_PLLSRC RCC_CFGR_PLLSRC +#define STM32_CFGR_PLLXTPRE 0 +#define STM32_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx9 +#define STM32_PLL_FREQUENCY (9*STM32_BOARD_XTAL) + +/* Use the PLL and set the SYSCLK source to be the PLL */ + +#define STM32_SYSCLK_SW RCC_CFGR_SW_PLL +#define STM32_SYSCLK_SWS RCC_CFGR_SWS_PLL +#define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY + +/* AHB clock (HCLK) is SYSCLK (72MHz) */ + +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK +#define STM32_HCLK_FREQUENCY STM32_PLL_FREQUENCY + +/* APB2 clock (PCLK2) is HCLK (72MHz) */ + +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK +#define STM32_PCLK2_FREQUENCY STM32_HCLK_FREQUENCY +#define STM32_APB2_CLKIN (STM32_PCLK2_FREQUENCY) + +/* APB2 timers 1, 8, 15-17 and HRTIM1 will receive PCLK2. */ + +/* Timers driven from APB2 will be PCLK2 */ + +#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB1_TIM15_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB1_TIM16_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB1_TIM17_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB1_THRTIM1_CLKIN (STM32_PCLK2_FREQUENCY) + +/* APB1 clock (PCLK1) is HCLK/2 (36MHz) */ + +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd2 +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/2) + +/* APB1 timers 2-7 will be twice PCLK1 */ + +#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) + +/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx + * otherwise frequency is 2xAPBx. + * Note: TIM1,8 are on APB2, others on APB1 + */ + +#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM15_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM16_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM17_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM2_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM3_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM5_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM6_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM7_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_HRTIM1_FREQUENCY STM32_HCLK_FREQUENCY + +/* LED definitions **********************************************************/ + +/* LED index values for use with board_userled() */ + +#define BOARD_LED1 0 +#define BOARD_LED2 1 +#define BOARD_LED3 2 +#define BOARD_LED4 3 +#define BOARD_NLEDS 4 + +/* LED bits for use with board_userled_all() */ + +#define BOARD_LED1_BIT (1 << BOARD_LED1) +#define BOARD_LED2_BIT (1 << BOARD_LED2) +#define BOARD_LED3_BIT (1 << BOARD_LED3) +#define BOARD_LED4_BIT (1 << BOARD_LED4) + +/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the 4 LEDs on + * board the stm32f334-disco. The following definitions describe how NuttX + * controls the LEDs: + */ + +#define LED_STARTED 0 /* LED1 */ +#define LED_HEAPALLOCATE 1 /* LED2 */ +#define LED_IRQSENABLED 2 /* LED1 + LED2 */ +#define LED_STACKCREATED 3 /* LED3 */ +#define LED_INIRQ 4 /* LED1 + LED3 */ +#define LED_SIGNAL 5 /* LED2 + LED3 */ +#define LED_ASSERTION 6 /* LED1 + LED2 + LED3 */ +#define LED_PANIC 7 /* N/C + N/C + N/C + LED4 */ + +/* Button definitions *******************************************************/ + +/* The STM32F334-DISCO supports two buttons; only one button is controllable + * by software: + * + * B1 USER: user button connected to the I/O PA0 of the STM32F334R8. + * B2 RESET: push button connected to NRST is used to RESET the + * STM32F334R8. + */ + +#define BUTTON_USER 0 +#define NUM_BUTTONS 1 + +#define BUTTON_USER_BIT (1 << BUTTON_USER) + +/* Alternate function pin selections ****************************************/ + +/* CAN */ + +#define GPIO_CAN1_RX (GPIO_CAN_RX_2|GPIO_SPEED_50MHz) +#define GPIO_CAN1_TX (GPIO_CAN_TX_2|GPIO_SPEED_50MHz) + +/* I2C */ + +#define GPIO_I2C1_SCL (GPIO_I2C1_SCL_3|GPIO_SPEED_50MHz) +#define GPIO_I2C1_SDA (GPIO_I2C1_SDA_3|GPIO_SPEED_50MHz) + +/* SPI */ + +#define GPIO_SPI1_MISO (GPIO_SPI1_MISO_1|GPIO_SPEED_50MHz) +#define GPIO_SPI1_MOSI (GPIO_SPI1_MOSI_1|GPIO_SPEED_50MHz) +#define GPIO_SPI1_SCK (GPIO_SPI1_SCK_1|GPIO_SPEED_50MHz) + +/* TIM */ + +#define GPIO_TIM2_CH2OUT (GPIO_TIM2_CH2OUT_2|GPIO_SPEED_50MHz) +#define GPIO_TIM2_CH3OUT (GPIO_TIM2_CH3OUT_3|GPIO_SPEED_50MHz) + +#define GPIO_TIM3_CH1OUT (GPIO_TIM3_CH1OUT_2|GPIO_SPEED_50MHz) +#define GPIO_TIM3_CH2OUT (GPIO_TIM3_CH2OUT_4|GPIO_SPEED_50MHz) + +#define GPIO_TIM4_CH1OUT (GPIO_TIM4_CH1OUT_2|GPIO_SPEED_50MHz) + +/* USART */ + +#define GPIO_USART2_RX (GPIO_USART2_RX_3|GPIO_SPEED_50MHz) /* PB4 */ +#define GPIO_USART2_TX (GPIO_USART2_TX_3|GPIO_SPEED_50MHz) /* PB3 */ + +/* Board configuration for powerled example: + * - Set HRTIM TIMC output 1 (PB12) on PERIOD. + * - Reset HRTIM TIMC output 1 on HRTIM EEV2. + * - HRTIM EEV2 is connected to COMP4 output which works as current limit. + * - COMP4 inverting input is connected to DAC1CH1 output. + * - COMP4 non-inverting input (PB1) is connected to current sense + * resistor (1 Ohm). + * - DAC1CH1 DMA transfer is triggered by HRTIM TIMC events, which is used + * to provide slope compensation. + */ + +#if defined(CONFIG_EXAMPLES_POWERLED) + +/* Comparators configuration ************************************************/ + +#define COMP4_INM COMP_INMSEL_DAC1CH1 + +/* HRTIM configuration ******************************************************/ + +#define HRTIM_TIMC_PRESCALER HRTIM_PRESCALER_1 +#define HRTIM_TIMC_MODE HRTIM_MODE_CONT +#define HRTIM_TIMC_DMA (HRTIM_DMA_REP|HRTIM_DMA_CMP1|HRTIM_DMA_CMP2| \ + HRTIM_DMA_CMP3|HRTIM_DMA_CMP4) +#define HRTIM_TIMC_CH1_SET HRTIM_OUT_SET_PER +#define HRTIM_TIMC_CH1_RST HRTIM_OUT_RST_EXTEVNT2 +#define HRTIM_TIMC_CH1_IDLE_STATE HRTIM_IDLE_INACTIVE + +#define HRTIM_EEV_SAMPLING HRTIM_EEV_SAMPLING_d1 +#define HRTIM_EEV2_SRC HRTIM_EEV_SRC_ANALOG +#define HRTIM_EEV2_FILTER HRTIM_EEV_DISABLE +#define HRTIM_EEV2_POL HRTIM_EEV_POL_HIGH +#define HRTIM_EEV2_SEN HRTIM_EEV_SEN_LEVEL +#define HRTIM_EEV2_MODE HRTIM_EEV_MODE_FAST + +#define HRTIM_BURST_CLOCK HRTIM_BURST_CLOCK_HRTIM +#define HRTIM_BURST_PRESCALER HRTIM_BURST_PRESCALER_1 +#define HRTIM_BURST_TRIGGERS 0 + +/* DMA channels *************************************************************/ + +/* DAC */ + +#define DAC1CH1_DMA_CHAN DMACHAN_HRTIM1_C + +#endif /* CONFIG_EXAMPLES_POWERLED */ + +/* Board configuration for SMPS example: + * PA8 - HRTIM_CHA1 + * PA9 - HRTIM_CHA2 + * PA10 - HRTIM_CHB1 + * PA11 - HRTIM_CHB2 + * VIN - ADC Channel 2 (PA1) + * VOUT - ADC Channel 4 (PA3) + */ + +#if defined(CONFIG_EXAMPLES_SMPS) + +/* HRTIM configuration ******************************************************/ + +/* Timer A configuration - Buck operations */ + +#define HRTIM_TIMA_PRESCALER HRTIM_PRESCALER_1 +#define HRTIM_TIMA_MODE HRTIM_MODE_CONT +#define HRTIM_TIMA_UPDATE 0 +#define HRTIM_TIMA_RESET 0 + +#define HRTIM_TIMA_CH1_SET HRTIM_OUT_SET_NONE +#define HRTIM_TIMA_CH1_RST HRTIM_OUT_RST_NONE +#define HRTIM_TIMA_CH2_SET HRTIM_OUT_SET_NONE +#define HRTIM_TIMA_CH2_RST HRTIM_OUT_RST_NONE + +#define HRTIM_TIMA_DT_FSLOCK HRTIM_DT_LOCK +#define HRTIM_TIMA_DT_RSLOCK HRTIM_DT_LOCK +#define HRTIM_TIMA_DT_FVLOCK HRTIM_DT_RW +#define HRTIM_TIMA_DT_RVLOCK HRTIM_DT_RW +#define HRTIM_TIMA_DT_FSIGN HRTIM_DT_SIGN_POSITIVE +#define HRTIM_TIMA_DT_RSIGN HRTIM_DT_SIGN_POSITIVE +#define HRTIM_TIMA_DT_PRESCALER HRTIM_DEADTIME_PRESCALER_1 + +/* Timer B configuration - Boost operations */ + +#define HRTIM_TIMB_PRESCALER HRTIM_PRESCALER_1 +#define HRTIM_TIMB_MODE HRTIM_MODE_CONT +#define HRTIM_TIMB_UPDATE 0 +#define HRTIM_TIMB_RESET 0 + +#define HRTIM_TIMB_CH1_SET HRTIM_OUT_SET_NONE +#define HRTIM_TIMB_CH1_RST HRTIM_OUT_RST_NONE +#define HRTIM_TIMB_CH2_SET HRTIM_OUT_SET_NONE +#define HRTIM_TIMB_CH2_RST HRTIM_OUT_RST_NONE + +#define HRTIM_TIMB_DT_FSLOCK HRTIM_DT_LOCK +#define HRTIM_TIMB_DT_RSLOCK HRTIM_DT_LOCK +#define HRTIM_TIMB_DT_FVLOCK HRTIM_DT_RW +#define HRTIM_TIMB_DT_RVLOCK HRTIM_DT_RW +#define HRTIM_TIMB_DT_FSIGN HRTIM_DT_SIGN_POSITIVE +#define HRTIM_TIMB_DT_RSIGN HRTIM_DT_SIGN_POSITIVE +#define HRTIM_TIMB_DT_PRESCALER HRTIM_DEADTIME_PRESCALER_1 + +#define HRTIM_ADC_TRG2 HRTIM_ADCTRG24_AC4 + +/* DMA channels *************************************************************/ + +#endif /* CONFIG_EXAMPLES_SMPS */ + +/* HRTIM1 */ + +#define GPIO_HRTIM1_CHA1 GPIO_HRTIM1_CHA1_0 +#define GPIO_HRTIM1_CHA2 GPIO_HRTIM1_CHA2_0 +#define GPIO_HRTIM1_CHB1 GPIO_HRTIM1_CHB1_0 +#define GPIO_HRTIM1_CHB2 GPIO_HRTIM1_CHB2_0 +#define GPIO_HRTIM1_CHC1 GPIO_HRTIM1_CHC1_0 +#define GPIO_HRTIM1_CHC2 GPIO_HRTIM1_CHC2_0 +#define GPIO_HRTIM1_CHD1 GPIO_HRTIM1_CHD1_0 +#define GPIO_HRTIM1_CHD2 GPIO_HRTIM1_CHD2_0 +#define GPIO_HRTIM1_CHE1 GPIO_HRTIM1_CHE1_0 +#define GPIO_HRTIM1_CHE2 GPIO_HRTIM1_CHE2_0 +#define GPIO_HRTIM1_EEV1 GPIO_HRTIM1_EEV1_0 +#define GPIO_HRTIM1_EEV2 GPIO_HRTIM1_EEV2_0 +#define GPIO_HRTIM1_EEV3 GPIO_HRTIM1_EEV3_0 +#define GPIO_HRTIM1_FLT1 GPIO_HRTIM1_FLT1_0 +#define GPIO_HRTIM1_FLT2 GPIO_HRTIM1_FLT2_0 +#define GPIO_HRTIM1_FLT3 GPIO_HRTIM1_FLT3_0 +#define GPIO_HRTIM1_FLT4 GPIO_HRTIM1_FLT4_0 +#define GPIO_HRTIM1_FLT5 GPIO_HRTIM1_FLT5_0 + +/* COMP */ + +#define GPIO_COMP2_INP GPIO_COMP2_INP_0 +#define GPIO_COMP4_INP GPIO_COMP4_INP_0 +#define GPIO_COMP6_INP GPIO_COMP6_INP_0 + +/* DAC */ + +#define GPIO_DAC1_OUT1 GPIO_DAC1_OUT1_0 +#define GPIO_DAC1_OUT2 GPIO_DAC1_OUT2_0 + +#endif /* __BOARDS_ARM_STM32_STM32F334_DISCO_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32f3/stm32f334-disco/scripts/Make.defs b/boards/arm/stm32f3/stm32f334-disco/scripts/Make.defs new file mode 100644 index 0000000000000..808988ed8e20d --- /dev/null +++ b/boards/arm/stm32f3/stm32f334-disco/scripts/Make.defs @@ -0,0 +1,41 @@ +############################################################################ +# boards/arm/stm32f3/stm32f334-disco/scripts/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/.config +include $(TOPDIR)/tools/Config.mk +include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs + +LDSCRIPT = ld.script +ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) + +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32f3/stm32f334-disco/scripts/ld.script b/boards/arm/stm32f3/stm32f334-disco/scripts/ld.script new file mode 100644 index 0000000000000..f5f4236470b70 --- /dev/null +++ b/boards/arm/stm32f3/stm32f334-disco/scripts/ld.script @@ -0,0 +1,127 @@ +/**************************************************************************** + * boards/arm/stm32f3/stm32f334-disco/scripts/ld.script + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* The STM32F334C8 has 64Kb of FLASH beginning at address 0x0800:0000, + * 12Kb of SRAM and 4Kb of CCM SRAM. + * + * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 + * where the code expects to begin execution by jumping to the entry point in + * the 0x0800:0000 address range. + */ + +MEMORY +{ + flash (rx) : ORIGIN = 0x08000000, LENGTH = 64K + sram (rwx) : ORIGIN = 0x20000000, LENGTH = 12K +} + +OUTPUT_ARCH(arm) +EXTERN(_vectors) +ENTRY(_stext) +SECTIONS +{ + .text : { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > flash + + .init_section : ALIGN(4) { + _sinit = ABSOLUTE(.); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) + _einit = ABSOLUTE(.); + } > flash + + .ARM.extab : ALIGN(4) { + *(.ARM.extab*) + } > flash + + .ARM.exidx : ALIGN(4) { + __exidx_start = ABSOLUTE(.); + *(.ARM.exidx*) + __exidx_end = ABSOLUTE(.); + } > flash + + .tdata : { + _stdata = ABSOLUTE(.); + *(.tdata .tdata.* .gnu.linkonce.td.*); + _etdata = ABSOLUTE(.); + } > flash + + .tbss : { + _stbss = ABSOLUTE(.); + *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); + _etbss = ABSOLUTE(.); + } > flash + + _eronly = ABSOLUTE(.); + + /* The RAM vector table (if present) should lie at the beginning of SRAM */ + + .ram_vectors : { + *(.ram_vectors) + } > sram + + .data : ALIGN(4) { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > sram AT > flash + + .bss : ALIGN(4) { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + _ebss = ABSOLUTE(.); + } > sram + + /* Stabs debugging sections. */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/stm32f3/stm32f334-disco/src/CMakeLists.txt b/boards/arm/stm32f3/stm32f334-disco/src/CMakeLists.txt new file mode 100644 index 0000000000000..0f8f031ecba1b --- /dev/null +++ b/boards/arm/stm32f3/stm32f334-disco/src/CMakeLists.txt @@ -0,0 +1,55 @@ +# ############################################################################## +# boards/arm/stm32f3/stm32f334-disco/src/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(SRCS stm32_boot.c) + +if(CONFIG_ARCH_LEDS) + list(APPEND SRCS stm32_autoleds.c) +endif() + +if(CONFIG_STM32_CAN_CHARDRIVER) + list(APPEND SRCS stm32_can.c) +endif() + +if(CONFIG_PWM) + list(APPEND SRCS stm32_pwm.c) +endif() + +if(CONFIG_SPI) + list(APPEND SRCS stm32_spi.c) +endif() + +if(CONFIG_TIMER) + list(APPEND SRCS stm32_timer.c) +endif() + +if(CONFIG_DRIVERS_POWERLED) + list(APPEND SRCS stm32_powerled.c) +endif() + +if(CONFIG_DRIVERS_SMPS) + list(APPEND SRCS stm32_smps.c) +endif() + +target_sources(board PRIVATE ${SRCS}) + +set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/ld.script") diff --git a/boards/arm/stm32f3/stm32f334-disco/src/Make.defs b/boards/arm/stm32f3/stm32f334-disco/src/Make.defs new file mode 100644 index 0000000000000..fc16406ada6f5 --- /dev/null +++ b/boards/arm/stm32f3/stm32f334-disco/src/Make.defs @@ -0,0 +1,57 @@ +############################################################################ +# boards/arm/stm32f3/stm32f334-disco/src/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +CSRCS = stm32_boot.c + +ifeq ($(CONFIG_ARCH_LEDS),y) +CSRCS += stm32_autoleds.c +endif + +ifeq ($(CONFIG_STM32_CAN_CHARDRIVER),y) +CSRCS += stm32_can.c +endif + +ifeq ($(CONFIG_PWM),y) +CSRCS += stm32_pwm.c +endif + +ifeq ($(CONFIG_SPI),y) +CSRCS += stm32_spi.c +endif + +ifeq ($(CONFIG_TIMER),y) +CSRCS += stm32_timer.c +endif + +ifeq ($(CONFIG_DRIVERS_POWERLED),y) +CSRCS += stm32_powerled.c +endif + +ifeq ($(CONFIG_DRIVERS_SMPS),y) +CSRCS += stm32_smps.c +endif + +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32f3/stm32f334-disco/src/stm32_adc.c b/boards/arm/stm32f3/stm32f334-disco/src/stm32_adc.c new file mode 100644 index 0000000000000..82267bb3d83f0 --- /dev/null +++ b/boards/arm/stm32f3/stm32f334-disco/src/stm32_adc.c @@ -0,0 +1,241 @@ +/**************************************************************************** + * boards/arm/stm32f3/stm32f334-disco/src/stm32_adc.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "stm32.h" + +#if defined(CONFIG_ADC) && (defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2)) + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* 1 or 2 ADC devices (DEV1, DEV2) */ + +#if defined(CONFIG_STM32_ADC1) +# define DEV1_PORT 1 +#endif + +#if defined(CONFIG_STM32_ADC2) +# if defined(DEV1_PORT) +# define DEV2_PORT 2 +# else +# define DEV1_PORT 2 +# endif +#endif + +/* The number of ADC channels in the conversion list */ + +/* TODO DMA */ + +#define ADC1_NCHANNELS 3 +#define ADC2_NCHANNELS 3 + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* DEV 1 */ + +#if DEV1_PORT == 1 + +#define DEV1_NCHANNELS ADC1_NCHANNELS + +/* Identifying number of each ADC channel (even if NCHANNELS is less ) */ + +static const uint8_t g_chanlist1[3] = +{ + 1, + 2, + 11 +}; + +/* Configurations of pins used by each ADC channel */ + +static const uint32_t g_pinlist1[3] = +{ + GPIO_ADC1_IN1_0, /* PA0/A0 */ + GPIO_ADC1_IN2_0, /* PA1/A1 */ + GPIO_ADC1_IN11_0, /* PB0/A3 */ +}; + +#elif DEV1_PORT == 2 + +#define DEV1_NCHANNELS ADC2_NCHANNELS + +/* Identifying number of each ADC channel */ + +static const uint8_t g_chanlist1[3] = +{ + 1, + 6, + 7 +}; + +/* Configurations of pins used by each ADC channel */ + +static const uint32_t g_pinlist1[3] = +{ + GPIO_ADC2_IN1_0, /* PA4/A2 */ + GPIO_ADC2_IN7_0, /* PC1/A4 */ + GPIO_ADC2_IN6_0, /* PC0/A5 */ +}; + +#endif /* DEV1_PORT == 1 */ + +#ifdef DEV2_PORT + +/* DEV 2 */ + +#if DEV2_PORT == 2 + +#define DEV2_NCHANNELS ADC2_NCHANNELS + +/* Identifying number of each ADC channel */ + +static const uint8_t g_chanlist2[1] = +{ + 1, + 6, + 7 +}; + +/* Configurations of pins used by each ADC channel */ + +static const uint32_t g_pinlist2[3] = +{ + GPIO_ADC2_IN1_0, /* PA4/A2 */ + GPIO_ADC2_IN7_0, /* PC1/A4 */ + GPIO_ADC2_IN6_0, /* PC0/A5 */ +}; + +#endif /* DEV2_PORT == 2 */ +#endif /* DEV2_PORT */ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_adc_setup + * + * Description: + * Initialize ADC and register the ADC driver. + * + ****************************************************************************/ + +int stm32_adc_setup(void) +{ + static bool initialized = false; + struct adc_dev_s *adc; + int ret; + int i; + + /* Check if we have already initialized */ + + if (!initialized) + { + /* DEV1 */ + + /* Configure the pins as analog inputs for the selected channels */ + + for (i = 0; i < DEV1_NCHANNELS; i++) + { + stm32_configgpio(g_pinlist1[i]); + } + + /* Call stm32_adcinitialize() to get an instance of the ADC interface */ + + adc = stm32_adcinitialize(DEV1_PORT, g_chanlist1, DEV1_NCHANNELS); + if (adc == NULL) + { + aerr("ERROR: Failed to get ADC interface 1\n"); + return -ENODEV; + } + + /* Register the ADC driver at "/dev/adc0" */ + + ret = adc_register("/dev/adc0", adc); + if (ret < 0) + { + aerr("ERROR: adc_register /dev/adc0 failed: %d\n", ret); + return ret; + } + +#ifdef DEV2_PORT + /* DEV2 */ + + /* Configure the pins as analog inputs for the selected channels */ + + for (i = 0; i < DEV2_NCHANNELS; i++) + { + stm32_configgpio(g_pinlist2[i]); + } + + /* Call stm32_adcinitialize() to get an instance of the ADC interface */ + + adc = stm32_adcinitialize(DEV2_PORT, g_chanlist2, DEV2_NCHANNELS); + if (adc == NULL) + { + aerr("ERROR: Failed to get ADC interface 2\n"); + return -ENODEV; + } + + /* Register the ADC driver at "/dev/adc1" */ + + ret = adc_register("/dev/adc1", adc); + if (ret < 0) + { + aerr("ERROR: adc_register /dev/adc1 failed: %d\n", ret); + return ret; + } +#endif + + initialized = true; + } + + return OK; +} + +#endif /* CONFIG_ADC && (CONFIG_STM32_ADC1 || CONFIG_STM32_ADC2) */ diff --git a/boards/arm/stm32f3/stm32f334-disco/src/stm32_autoleds.c b/boards/arm/stm32f3/stm32f334-disco/src/stm32_autoleds.c new file mode 100644 index 0000000000000..2adf161687a1d --- /dev/null +++ b/boards/arm/stm32f3/stm32f334-disco/src/stm32_autoleds.c @@ -0,0 +1,80 @@ +/**************************************************************************** + * boards/arm/stm32f3/stm32f334-disco/src/stm32_autoleds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "stm32.h" +#include "stm32f334-disco.h" + +#ifdef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_autoled_initialize + ****************************************************************************/ + +void board_autoled_initialize(void) +{ + /* Configure LED1 GPIO for output */ + + stm32_configgpio(GPIO_LED1); +} + +/**************************************************************************** + * Name: board_autoled_on + ****************************************************************************/ + +void board_autoled_on(int led) +{ + if (led == BOARD_LED1) + { + stm32_gpiowrite(GPIO_LED1, true); + } +} + +/**************************************************************************** + * Name: board_autoled_off + ****************************************************************************/ + +void board_autoled_off(int led) +{ + if (led == BOARD_LED1) + { + stm32_gpiowrite(GPIO_LED1, false); + } +} + +#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32f3/stm32f334-disco/src/stm32_boot.c b/boards/arm/stm32f3/stm32f334-disco/src/stm32_boot.c new file mode 100644 index 0000000000000..0dce4b87b7d74 --- /dev/null +++ b/boards/arm/stm32f3/stm32f334-disco/src/stm32_boot.c @@ -0,0 +1,194 @@ +/**************************************************************************** + * boards/arm/stm32f3/stm32f334-disco/src/stm32_boot.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include +#include + +#include "stm32f334-disco.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#undef HAVE_LEDS +#undef HAVE_DAC + +#if !defined(CONFIG_ARCH_LEDS) && defined(CONFIG_USERLED_LOWER) +# define HAVE_LEDS 1 +#endif + +#if defined(CONFIG_DAC) +# define HAVE_DAC1 1 +# define HAVE_DAC2 1 +#endif + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_boardinitialize + * + * Description: + * All STM32 architectures must provide the following entry point. This + * entry point is called early in the initialization -- after all memory + * has been configured and mapped but before any devices have been + * initialized. + * + ****************************************************************************/ + +void stm32_boardinitialize(void) +{ +#ifdef CONFIG_ARCH_LEDS + /* Configure on-board LEDs if LED support has been selected. */ + + board_autoled_initialize(); +#endif +} + +/**************************************************************************** + * Name: board_late_initialize + * + * Description: + * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_late_initialize(). board_late_initialize() will + * be called immediately after up_initialize() is called and just before + * the initial application is started. This additional initialization + * phase may be used, for example, to initialize board-specific device + * drivers. + * + ****************************************************************************/ + +#ifdef CONFIG_BOARD_LATE_INITIALIZE +void board_late_initialize(void) +{ + int ret; + +#if !defined(CONFIG_DRIVERS_POWERLED) && !defined(CONFIG_DRIVERS_SMPS) +#ifdef HAVE_LEDS + /* Register the LED driver */ + + ret = userled_lower_initialize(LED_DRIVER_PATH); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: userled_lower_initialize() failed: %d\n", ret); + return; + } +#endif + +#ifdef CONFIG_ADC + /* Initialize ADC and register the ADC driver. */ + + ret = stm32_adc_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_adc_setup failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_DAC + /* Initialize DAC and register the DAC driver. */ + + ret = stm32_dac_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_dac_setup failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_COMP + /* Initialize COMP and register the COMP driver. */ + + ret = stm32_comp_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_comp_setup failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_OPAMP + /* Initialize OPAMP and register the OPAMP driver. */ + + ret = stm32_opamp_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_opamp_setup failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_STM32_HRTIM + /* Initialize HRTIM and register the HRTIM driver. */ + + ret = stm32_hrtim_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_hrtim_setup failed: %d\n", ret); + } +#endif +#endif + +#ifdef CONFIG_DRIVERS_POWERLED + /* Initialize powerled and register the powerled driver */ + + ret = stm32_powerled_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_powerled_setup failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_DRIVERS_SMPS + /* Initialize smps and register the smps driver */ + + ret = stm32_smps_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_smps_setup failed: %d\n", ret); + } +#endif + + UNUSED(ret); +} +#endif diff --git a/boards/arm/stm32f3/stm32f334-disco/src/stm32_comp.c b/boards/arm/stm32f3/stm32f334-disco/src/stm32_comp.c new file mode 100644 index 0000000000000..9f0c52f925b54 --- /dev/null +++ b/boards/arm/stm32f3/stm32f334-disco/src/stm32_comp.c @@ -0,0 +1,122 @@ +/**************************************************************************** + * boards/arm/stm32f3/stm32f334-disco/src/stm32_comp.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "stm32.h" + +#if defined(CONFIG_COMP) && (defined(CONFIG_STM32_COMP2) || \ + defined(CONFIG_STM32_COMP4) || \ + defined(CONFIG_STM32_COMP6)) + +#ifdef CONFIG_STM32_COMP2 +# if defined(CONFIG_STM32_COMP4) || defined(CONFIG_STM32_COMP6) +# error "Currently only one COMP device supported" +# endif +#elif CONFIG_STM32_COMP4 +# if defined(CONFIG_STM32_COMP2) || defined(CONFIG_STM32_COMP6) +# error "Currently only one COMP device supported" +# endif +#elif CONFIG_STM32_COMP6 +# if defined(CONFIG_STM32_COMP2) || defined(CONFIG_STM32_COMP4) +# error "Currently only one COMP device supported" +# endif +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_comp_setup + * + * Description: + * Initialize COMP + * + ****************************************************************************/ + +int stm32_comp_setup(void) +{ + static bool initialized = false; + struct comp_dev_s *comp = NULL; + int ret; + + if (!initialized) + { + /* Get the comparator interface */ + +#ifdef CONFIG_STM32_COMP2 + comp = stm32_compinitialize(2); + if (comp == NULL) + { + aerr("ERROR: Failed to get COMP%d interface\n", 2); + return -ENODEV; + } +#endif + +#ifdef CONFIG_STM32_COMP4 + comp = stm32_compinitialize(4); + if (comp == NULL) + { + aerr("ERROR: Failed to get COMP%d interface\n", 4); + return -ENODEV; + } +#endif + +#ifdef CONFIG_STM32_COMP6 + comp = stm32_compinitialize(6); + if (comp == NULL) + { + aerr("ERROR: Failed to get COMP%d interface\n", 6); + return -ENODEV; + } +#endif + + /* Register the comparator character driver at /dev/comp0 */ + + ret = comp_register("/dev/comp0", comp); + if (ret < 0) + { + aerr("ERROR: comp_register failed: %d\n", ret); + return ret; + } + + initialized = true; + } + + return OK; +} + +#endif /* CONFIG_COMP && (CONFIG_STM32_COMP1 || + * CONFIG_STM32_COMP2 + * CONFIG_STM32_COMP6) */ diff --git a/boards/arm/stm32f3/stm32f334-disco/src/stm32_hrtim.c b/boards/arm/stm32f3/stm32f334-disco/src/stm32_hrtim.c new file mode 100644 index 0000000000000..38885ff50b9f9 --- /dev/null +++ b/boards/arm/stm32f3/stm32f334-disco/src/stm32_hrtim.c @@ -0,0 +1,86 @@ +/**************************************************************************** + * boards/arm/stm32f3/stm32f334-disco/src/stm32_hrtim.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include + +#include "stm32_hrtim.h" + +#if defined(CONFIG_STM32_HRTIM) && defined(CONFIG_STM32_HRTIM1) + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_hrtim_setup + * + * Description: + * Initialize HRTIM driver + * + * Returned Value: + * 0 on success, a negated errno value on failure + * + ****************************************************************************/ + +int stm32_hrtim_setup(void) +{ + static bool initialized = false; + struct hrtim_dev_s *hrtim = NULL; + int ret; + + if (!initialized) + { + /* Get the HRTIM interface */ + + hrtim = stm32_hrtiminitialize(); + if (hrtim == NULL) + { + tmrerr("ERROR: Failed to get HRTIM1 interface\n"); + return -ENODEV; + } + + /* Register the HRTIM character driver at /dev/hrtim0 */ + + ret = hrtim_register("/dev/hrtim0", hrtim); + if (ret < 0) + { + tmrerr("ERROR: hrtim_register failed: %d\n", ret); + return ret; + } + + initialized = true; + } + + return OK; +} + +#endif /* CONFIG_STM32_HRTIM && CONFIG_STM32_HRTIM1 */ diff --git a/boards/arm/stm32f3/stm32f334-disco/src/stm32_opamp.c b/boards/arm/stm32f3/stm32f334-disco/src/stm32_opamp.c new file mode 100644 index 0000000000000..03f9557d1e14a --- /dev/null +++ b/boards/arm/stm32f3/stm32f334-disco/src/stm32_opamp.c @@ -0,0 +1,86 @@ +/**************************************************************************** + * boards/arm/stm32f3/stm32f334-disco/src/stm32_opamp.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "stm32.h" + +#if defined(CONFIG_OPAMP) && defined(CONFIG_STM32_OPAMP2) + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_opamp_setup + * + * Description: + * Initialize OPAMP + * + ****************************************************************************/ + +int stm32_opamp_setup(void) +{ + static bool initialized = false; + struct opamp_dev_s *opamp = NULL; + int ret; + + if (!initialized) + { + /* Get the OPAMP interface */ + +#ifdef CONFIG_STM32_OPAMP2 + opamp = stm32_opampinitialize(2); + if (opamp == NULL) + { + aerr("ERROR: Failed to get OPAMP%d interface\n", 2); + return -ENODEV; + } +#endif + + /* Register the OPAMP character driver at /dev/opamp0 */ + + ret = opamp_register("/dev/opamp0", opamp); + if (ret < 0) + { + aerr("ERROR: opamp_register failed: %d\n", ret); + return ret; + } + + initialized = true; + } + + return OK; +} + +#endif /* CONFIG_OPAMP && CONFIG_STM32_OPAMP2 */ diff --git a/boards/arm/stm32/stm32f334-disco/src/stm32_powerled.c b/boards/arm/stm32f3/stm32f334-disco/src/stm32_powerled.c similarity index 99% rename from boards/arm/stm32/stm32f334-disco/src/stm32_powerled.c rename to boards/arm/stm32f3/stm32f334-disco/src/stm32_powerled.c index 0f7890bd25fd6..81430e490d8d7 100644 --- a/boards/arm/stm32/stm32f334-disco/src/stm32_powerled.c +++ b/boards/arm/stm32f3/stm32f334-disco/src/stm32_powerled.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f334-disco/src/stm32_powerled.c + * boards/arm/stm32f3/stm32f334-disco/src/stm32_powerled.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f3/stm32f334-disco/src/stm32_smps.c b/boards/arm/stm32f3/stm32f334-disco/src/stm32_smps.c new file mode 100644 index 0000000000000..9253f274ce9d0 --- /dev/null +++ b/boards/arm/stm32f3/stm32f334-disco/src/stm32_smps.c @@ -0,0 +1,1143 @@ +/**************************************************************************** + * boards/arm/stm32f3/stm32f334-disco/src/stm32_smps.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#include + +#include "arm_internal.h" +#include "ram_vectors.h" + +#include "stm32_hrtim.h" +#include "stm32_adc.h" + +#include + +#if defined(CONFIG_EXAMPLES_SMPS) && defined(CONFIG_DRIVERS_SMPS) + +#ifndef CONFIG_LIBDSP +# error CONFIG_LIBDSP is required +#endif + +#ifndef CONFIG_ARCH_HIPRI_INTERRUPT +# error CONFIG_ARCH_HIPRI_INTERRUPT is required +#endif + +#ifndef CONFIG_ARCH_RAMVECTORS +# error CONFIG_ARCH_RAMVECTORS is required +#endif + +#ifndef CONFIG_ARCH_IRQPRIO +# error CONFIG_ARCH_IRQPRIO is required +#endif + +#ifndef CONFIG_ARCH_FPU +# warning Set CONFIG_ARCH_FPU for hardware FPU support +#endif + +#if !defined(CONFIG_STM32_HRTIM1) || !defined(CONFIG_STM32_HRTIM) +# error "SMPS example requires HRTIM1 support" +#endif + +#if !defined(CONFIG_STM32_ADC1) || !defined(CONFIG_ADC) +# error "SMPS example requires ADC1 support" +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* ADC1 channels used in this example */ + +#define ADC1_NCHANNELS 2 + +/* ADC1 injected channels numeration */ + +#define V_IN_ADC_INJ_CHANNEL 0 +#define V_OUT_ADC_INJ_CHANNEL 1 + +/* Voltage reference for ADC */ + +#define ADC_REF_VOLTAGE ((float)3.3) + +/* ADC resolution */ + +#define ADC_VAL_MAX 4095 + +/* Input voltage conversion ratio - 6.8k/(6.8k + 27k) */ + +#define V_IN_RATIO (float)((float)(6800+27000)/(float)6800) + +/* Output voltage conversion ratio - 3.3k/(3.3k + 13.3k) */ + +#define V_OUT_RATIO (float)((float)(3300+13300)/(float)3300) + +/* Some absolute limits */ + +#define SMPS_ABSOLUTE_OUT_CURRENT_LIMIT_mA 250 +#define SMPS_ABSOLUTE_OUT_VOLTAGE_LIMIT_mV 15000 +#define SMPS_ABSOLUTE_IN_VOLTAGE_LIMIT_mV 15000 + +#if CONFIG_EXAMPLES_SMPS_OUT_CURRENT_LIMIT > SMPS_ABSOLUTE_OUT_CURRENT_LIMIT_mA +# error "Output current limit great than absolute limit!" +#endif +#if CONFIG_EXAMPLES_SMPS_OUT_VOLTAGE_LIMIT > SMPS_ABSOLUTE_OUT_VOLTAGE_LIMIT_mV +# error "Output voltage limit greater than absolute limit!" +#endif +#if CONFIG_EXAMPLES_SMPS_IN_VOLTAGE_LIMIT > SMPS_ABSOLUTE_IN_VOLTAGE_LIMIT_mV +# error "Input voltage limit greater than absolute limit!" +#endif + +/* Maximum output voltage for boost converter in float */ + +#define BOOST_VOLT_MAX ((float)CONFIG_EXAMPLES_SMPS_OUT_VOLTAGE_LIMIT/1000.0) + +/* Current limit table dimension */ + +#define SMPS_CURRENT_LIMIT_TAB_DIM 15 + +/* At this time only PID controller implemented */ + +#define SMPS_CONTROLLER_PID 1 + +/* Converter's finite accuracy */ + +#define SMPS_VOLTAGE_ACCURACY ((float)0.01) + +/* Buck-boost mode threshold */ + +#define SMPS_BUCKBOOST_RANGE ((float)0.5) + +/* PID controller configuration */ + +#define PID_KP ((float)1.0) +#define PID_KI ((float)0.1) +#define PID_KD ((float)0.0) + +/* Converter frequencies: + * - TIMA_PWM_FREQ - buck converter 250kHz + * - TIMB_PWM_FREQ - boost converter 250kHz + */ + +#define TIMA_PWM_FREQ 250000 +#define TIMB_PWM_FREQ 250000 + +/* Deadtime configuration */ + +#define DT_RISING 0x0A0 +#define DT_FALLING 0x0A0 + +/* Helper macros */ + +#define HRTIM_ALL_OUTPUTS_ENABLE(hrtim, state) \ + HRTIM_OUTPUTS_ENABLE(hrtim, HRTIM_OUT_TIMA_CH1|HRTIM_OUT_TIMA_CH2| \ + HRTIM_OUT_TIMB_CH1|HRTIM_OUT_TIMB_CH2, state); + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/* Current converter mode */ + +enum converter_mode_e +{ + CONVERTER_MODE_INIT, /* Initial mode */ + CONVERTER_MODE_BUCK, /* Buck mode operations (V_in > V_out) */ + CONVERTER_MODE_BOOST, /* Boost mode operations (V_in < V_out) */ + CONVERTER_MODE_BUCKBOOST, /* Buck-boost operations (V_in near V_out) */ +}; + +/* SMPS lower drivers structure */ + +struct smps_lower_dev_s +{ + struct hrtim_dev_s *hrtim; /* PWM generation */ + struct stm32_adc_dev_s *adc; /* input and output voltage sense */ + struct comp_dev_s *comp; /* not used in this demo - only as reference */ + struct dac_dev_s *dac; /* not used in this demo - only as reference */ + struct opamp_dev_s *opamp; /* not used in this demo - only as reference */ +}; + +/* Private data for smps */ + +struct smps_priv_s +{ + uint8_t conv_mode; /* Converter mode */ + uint16_t v_in_raw; /* Voltage input RAW value */ + uint16_t v_out_raw; /* Voltage output RAW value */ + float v_in; /* Voltage input real value in V */ + float v_out; /* Voltage output real value in V */ + bool running; /* Running flag */ + pid_controller_f32_t pid; /* PID controller */ + float *c_limit_tab; /* Current limit tab */ +}; + +/**************************************************************************** + * Private Function Protototypes + ****************************************************************************/ + +static int smps_setup(struct smps_dev_s *dev); +static int smps_shutdown(struct smps_dev_s *dev); +static int smps_start(struct smps_dev_s *dev); +static int smps_stop(struct smps_dev_s *dev); +static int smps_params_set(struct smps_dev_s *dev, + struct smps_params_s *param); +static int smps_mode_set(struct smps_dev_s *dev, uint8_t mode); +static int smps_limits_set(struct smps_dev_s *dev, + struct smps_limits_s *limits); +static int smps_state_get(struct smps_dev_s *dev, + struct smps_state_s *state); +static int smps_fault_set(struct smps_dev_s *dev, uint8_t fault); +static int smps_fault_get(struct smps_dev_s *dev, + uint8_t *fault); +static int smps_fault_clean(struct smps_dev_s *dev, + uint8_t fault); +static int smps_ioctl(struct smps_dev_s *dev, int cmd, + unsigned long arg); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +struct smps_lower_dev_s g_smps_lower; +struct smps_priv_s g_smps_priv; +struct smps_s g_smps; + +struct smps_ops_s g_smps_ops = +{ + .setup = smps_setup, + .shutdown = smps_shutdown, + .start = smps_start, + .stop = smps_stop, + .params_set = smps_params_set, + .mode_set = smps_mode_set, + .limits_set = smps_limits_set, + .fault_set = smps_fault_set, + .state_get = smps_state_get, + .fault_get = smps_fault_get, + .fault_clean = smps_fault_clean, + .ioctl = smps_ioctl +}; + +struct smps_dev_s g_smps_dev = +{ + .ops = &g_smps_ops, + .priv = &g_smps, + .lower = NULL +}; + +/* ADC configuration: + * - Input voltage (V_IN) - ADC1 Channel 2 (PA1) + * - Output voltage (V_OUT) - ADC1 Channel 4 (PA3) + * + * ADC channels configured in injected mode. + * + * Transistors configuration in buck mode: + * - T5 - ON + * - T12 - OFF + * - T4 and T11 - buck operation + * Transistors configuration in boost mode: + * - T4 - ON + * - T11 - OFF + * - T5 and T12 - boost operation + * Transistors configuration in buck-boost mode: + * - T4, T11 - buck operation + * - T5 and T12 - boost operation + * + * HRTIM outputs configuration: + * - T4 -> PA8 -> HRTIM_CHA1 + * - T5 -> PA11 -> HRTIM_CHB2 + * - T11 -> PA9 -> HRTIM_CHA2 + * - T12 -> PA10 -> HRTIM_CHB1 + * + */ + +/* ADC channel list */ + +static const uint8_t g_adc1chan[ADC1_NCHANNELS] = +{ + 2, + 4 +}; + +/* Configurations of pins used by ADC channel */ + +static const uint32_t g_adc1pins[ADC1_NCHANNELS] = +{ + GPIO_ADC1_IN2_0, /* PA1 - V_IN */ + GPIO_ADC1_IN4_0, /* PA3 - V_OUT */ +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +static int smps_shutdown(struct smps_dev_s *dev) +{ + struct smps_s *smps = (struct smps_s *)dev->priv; + struct smps_priv_s *priv = (struct smps_priv_s *)smps->priv; + + /* Stop smps if running */ + + if (priv->running == true) + { + smps_stop(dev); + } + + /* Reset smps structure */ + + memset(smps, 0, sizeof(struct smps_s)); + + return OK; +} + +/**************************************************************************** + * Name: smps_setup + * + * Description: + * + * Returned Value: + * 0 on success, a negated errno value on failure + * + ****************************************************************************/ + +static int smps_setup(struct smps_dev_s *dev) +{ + struct smps_lower_dev_s *lower = dev->lower; + struct smps_s *smps = (struct smps_s *)dev->priv; + struct hrtim_dev_s *hrtim = NULL; + struct stm32_adc_dev_s *adc = NULL; + struct smps_priv_s *priv; + struct adc_channel_s channels[ADC1_NCHANNELS]; + struct adc_sample_time_s stime; + int ret = OK; + int i = 0; + + /* Initialize smps structure */ + + smps->opmode = SMPS_OPMODE_INIT; + smps->state.state = SMPS_STATE_INIT; + smps->priv = &g_smps_priv; + + /* Check lower half drivers */ + + hrtim = lower->hrtim; + if (hrtim == NULL) + { + pwrerr("ERROR: Failed to get hrtim "); + ret = ERROR; + goto errout; + } + + adc = lower->adc; + if (adc == NULL) + { + pwrerr("ERROR: Failed to get ADC lower level interface"); + ret = ERROR; + goto errout; + } + + /* Update ADC sample time */ + + for (i = 0; i < ADC1_NCHANNELS; i += 1) + { + channels[i].sample_time = ADC_SMPR_61p5; + channels[i].channel = g_adc1chan[i]; + } + + memset(&stime, 0, sizeof(struct adc_sample_time_s)); + + stime.channels_nbr = ADC1_NCHANNELS; + stime.channel = channels; + + STM32_ADC_SAMPLETIME_SET(adc, &stime); + STM32_ADC_SAMPLETIME_WRITE(adc); + + /* TODO: create current limit table */ + + UNUSED(priv); + +errout: + return ret; +} + +static int smps_start(struct smps_dev_s *dev) +{ + struct smps_lower_dev_s *lower = dev->lower; + struct smps_s *smps = (struct smps_s *)dev->priv; + struct smps_priv_s *priv = (struct smps_priv_s *)smps->priv; + struct hrtim_dev_s *hrtim = lower->hrtim; + struct stm32_adc_dev_s *adc = lower->adc; + volatile uint64_t per = 0; + uint64_t fclk = 0; + int ret = OK; + + /* Disable HRTIM outputs */ + + HRTIM_ALL_OUTPUTS_ENABLE(hrtim, false); + + /* Reset SMPS private structure */ + + memset(priv, 0, sizeof(struct smps_priv_s)); + +#ifdef SMPS_CONTROLLER_PID + /* Initialize PID controller */ + + pid_controller_init(&priv->pid, PID_KP, PID_KI, PID_KD); + + /* Set PID controller saturation */ + + pid_saturation_set(&priv->pid, 0.0, BOOST_VOLT_MAX); + + /* Reset PI integral if saturated */ + + pi_ireset_enable(&priv->pid, true); +#endif + + /* Get TIMA period value for given frequency */ + + fclk = HRTIM_FCLK_GET(hrtim, HRTIM_TIMER_TIMA); + per = fclk / TIMA_PWM_FREQ; + if (per > HRTIM_PER_MAX) + { + pwrerr("ERROR: Can not achieve tima pwm " + "freq=%" PRIu32 " if fclk=%" PRIu64 "\n", + (uint32_t)TIMA_PWM_FREQ, fclk); + ret = -EINVAL; + goto errout; + } + + /* Set TIMA period value */ + + HRTIM_PER_SET(hrtim, HRTIM_TIMER_TIMA, (uint16_t)per); + + /* Get TIMB period value for given frequency */ + + fclk = HRTIM_FCLK_GET(hrtim, HRTIM_TIMER_TIMB); + per = fclk / TIMB_PWM_FREQ; + if (per > HRTIM_PER_MAX) + { + pwrerr("ERROR: Can not achieve timb pwm " + "freq=%" PRIu32 " if fclk=%" PRIu64 "\n", + (uint32_t)TIMB_PWM_FREQ, fclk); + ret = -EINVAL; + goto errout; + } + + /* Set TIMB period value */ + + HRTIM_PER_SET(hrtim, HRTIM_TIMER_TIMB, (uint16_t)per); + + /* ADC trigger on TIMA CMP4 */ + + HRTIM_CMP_SET(hrtim, HRTIM_TIMER_TIMA, HRTIM_CMP4, 10000); + + /* Configure TIMER A and TIMER B deadtime mode + * + * NOTE: In deadtime mode we have to configure output 1 only + * (SETx1, RSTx1), output 2 configuration is not significant. + */ + + HRTIM_DEADTIME_UPDATE(hrtim, HRTIM_TIMER_TIMA, HRTIM_DT_EDGE_RISING, + DT_RISING); + HRTIM_DEADTIME_UPDATE(hrtim, HRTIM_TIMER_TIMA, HRTIM_DT_EDGE_FALLING, + DT_FALLING); + HRTIM_DEADTIME_UPDATE(hrtim, HRTIM_TIMER_TIMB, HRTIM_DT_EDGE_RISING, + DT_RISING); + HRTIM_DEADTIME_UPDATE(hrtim, HRTIM_TIMER_TIMB, HRTIM_DT_EDGE_FALLING, + DT_FALLING); + + /* Set T4 and T12 to a low state. + * Deadtime mode force T11 and T5 to a high state. + */ + + HRTIM_OUTPUT_SET_SET(hrtim, HRTIM_OUT_TIMA_CH1, HRTIM_OUT_SET_NONE); + HRTIM_OUTPUT_RST_SET(hrtim, HRTIM_OUT_TIMA_CH1, HRTIM_OUT_RST_PER); + + HRTIM_OUTPUT_SET_SET(hrtim, HRTIM_OUT_TIMB_CH1, HRTIM_OUT_SET_NONE); + HRTIM_OUTPUT_RST_SET(hrtim, HRTIM_OUT_TIMB_CH1, HRTIM_OUT_RST_PER); + + /* Set running flag */ + + priv->running = true; + + HRTIM_ALL_OUTPUTS_ENABLE(hrtim, true); + + /* Enable ADC JEOS interrupts */ + + STM32_ADC_INT_ENABLE(adc, ADC_INT_JEOS); + + /* Enable ADC12 interrupts */ + + up_enable_irq(STM32_IRQ_ADC12); + + /* Start injected conversion */ + + STM32_ADC_INJ_STARTCONV(adc, true); + +errout: + return ret; +} + +static int smps_stop(struct smps_dev_s *dev) +{ + struct smps_lower_dev_s *lower = dev->lower; + struct smps_s *smps = (struct smps_s *)dev->priv; + struct smps_priv_s *priv = (struct smps_priv_s *)smps->priv; + struct hrtim_dev_s *hrtim = lower->hrtim; + struct stm32_adc_dev_s *adc = lower->adc; + + /* Disable HRTIM outputs */ + + HRTIM_ALL_OUTPUTS_ENABLE(hrtim, false); + + /* Stop injected conversion */ + + STM32_ADC_INJ_STARTCONV(adc, false); + + /* Disable ADC JEOS interrupts */ + + STM32_ADC_INT_DISABLE(adc, ADC_INT_JEOS); + + /* Disable ADC12 interrupts */ + + up_disable_irq(STM32_IRQ_ADC12); + + /* Reset running flag */ + + priv->running = false; + + return OK; +} + +static int smps_params_set(struct smps_dev_s *dev, + struct smps_params_s *param) +{ + struct smps_s *smps = (struct smps_s *)dev->priv; + int ret = OK; + + /* Only output voltage */ + + smps->param.v_out = param->v_out; + + /* REVISIT: use current and power parameters ? */ + + if (param->i_out > 0) + { + pwrwarn("WARNING: Output current parameters not used in this demo\n"); + } + + if (param->p_out > 0) + { + pwrwarn("WARNING: Output power parameters not used in this demo\n"); + } + + return ret; +} + +static int smps_mode_set(struct smps_dev_s *dev, uint8_t mode) +{ + struct smps_s *smps = (struct smps_s *)dev->priv; + int ret = OK; + + /* Only constant voltage mode supported */ + + if (mode == SMPS_OPMODE_CV) + { + smps->opmode = mode; + } + else + { + pwrerr("ERROR: Unsupported SMPS mode %d!\n", mode); + ret = ERROR; + goto errout; + } + +errout: + return ret; +} + +static int smps_limits_set(struct smps_dev_s *dev, + struct smps_limits_s *limits) +{ + struct smps_s *smps = (struct smps_s *)dev->priv; + int ret = OK; + + /* Some assertions */ + + if (limits->v_out <= 0) + { + pwrerr("ERROR: Output voltage limit must be set!\n"); + ret = ERROR; + goto errout; + } + + if (limits->v_in <= 0) + { + pwrerr("ERROR: Input voltage limit must be set!\n"); + ret = ERROR; + goto errout; + } + + if (limits->i_out <= 0) + { + pwrerr("ERROR: Output current limit must be set!\n"); + ret = ERROR; + goto errout; + } + + if (limits->v_out * 1000 > CONFIG_EXAMPLES_SMPS_OUT_VOLTAGE_LIMIT) + { + limits->v_out = (float)CONFIG_EXAMPLES_SMPS_OUT_VOLTAGE_LIMIT / 1000.0; + pwrwarn("WARNING: " + "SMPS output voltage limiit > SMPS absolute output voltage " + "limit. Set output voltage limit to %.2f.\n", + limits->v_out); + } + + if (limits->v_in * 1000 > CONFIG_EXAMPLES_SMPS_IN_VOLTAGE_LIMIT) + { + limits->v_in = (float)CONFIG_EXAMPLES_SMPS_IN_VOLTAGE_LIMIT / 1000.0; + pwrwarn("WARNING: " + "SMPS input voltage limiit > SMPS absolute input voltage " + "limit. Set input voltage limit to %.2f.\n", + limits->v_in); + } + + if (limits->i_out * 1000 > CONFIG_EXAMPLES_SMPS_OUT_CURRENT_LIMIT) + { + limits->i_out = (float)CONFIG_EXAMPLES_SMPS_OUT_CURRENT_LIMIT / 1000.0; + pwrwarn("WARNING: " + "SMPS output current limiit > SMPS absolute output current " + "limit. Set output current limit to %.2f.\n", + limits->i_out); + } + + /* Set output voltage limit */ + + smps->limits.v_out = limits->v_out; + + /* Set input voltage limit */ + + smps->limits.v_in = limits->v_in; + + /* Set current limit */ + + smps->limits.i_out = limits->i_out; + + /* Lock limits */ + + smps->limits.lock = true; + +errout: + return ret; +} + +static int smps_state_get(struct smps_dev_s *dev, + struct smps_state_s *state) +{ + struct smps_s *smps = (struct smps_s *)dev->priv; + + /* Copy locally stored feedbacks data to status structure */ + + smps->state.fb.v_in = g_smps_priv.v_in; + smps->state.fb.v_out = g_smps_priv.v_out; + + /* Return state structure to caller */ + + memcpy(state, &smps->state, sizeof(struct smps_state_s)); + + return OK; +} + +static int smps_fault_set(struct smps_dev_s *dev, uint8_t fault) +{ + return OK; +} + +static int smps_fault_get(struct smps_dev_s *dev, uint8_t *fault) +{ + return OK; +} + +static int smps_fault_clean(struct smps_dev_s *dev, uint8_t fault) +{ + return OK; +} + +static int smps_ioctl(struct smps_dev_s *dev, int cmd, unsigned long arg) +{ + return OK; +} + +/**************************************************************************** + * Name: smps_controller + ****************************************************************************/ + +static float smps_controller(struct smps_priv_s *priv, float err) +{ + float out = 0.0; + +#ifdef SMPS_CONTROLLER_PID + out = pid_controller(&priv->pid, err); +#else +# error "At this time only PID controller implemented" +#endif + + return out; +} + +/**************************************************************************** + * Name: smps_duty_set + ****************************************************************************/ + +static void smps_duty_set(struct smps_priv_s *priv, + struct smps_lower_dev_s *lower, + float out) +{ + struct hrtim_dev_s *hrtim = lower->hrtim; + uint8_t mode = priv->conv_mode; + uint16_t cmp = 0; + float duty = 0.0; + uint16_t per = 0; + + switch (mode) + { + case CONVERTER_MODE_INIT: + { + /* Do nothing */ + + break; + } + + case CONVERTER_MODE_BUCK: + { + if (out >= priv->v_in) out = priv->v_in; + if (out < 0.0) out = 0.0; + + duty = out / priv->v_in; + +#warning TODO: current limit in buck mode + + per = HRTIM_PER_GET(hrtim, HRTIM_TIMER_TIMA); + + cmp = (uint16_t)(per * duty); + + if (cmp > per - 30) cmp = per - 30; + + /* Set T4 duty cycle. T11 is complementary to T4 */ + + HRTIM_CMP_SET(hrtim, HRTIM_TIMER_TIMA, HRTIM_CMP1, cmp); + + break; + } + + case CONVERTER_MODE_BOOST: + { + per = HRTIM_PER_GET(hrtim, HRTIM_TIMER_TIMA); + + if (out < priv->v_in) out = priv->v_in; + if (out >= BOOST_VOLT_MAX) out = BOOST_VOLT_MAX; + + duty = 1.0 - priv->v_in / out; + +#warning TODO: current limit in boost mode + + cmp = (uint16_t)(per * duty); + + /* Set T12 duty cycle. T5 is complementary to T12 */ + + HRTIM_CMP_SET(hrtim, HRTIM_TIMER_TIMB, HRTIM_CMP1, cmp); + + break; + } + + case CONVERTER_MODE_BUCKBOOST: + { + /* Buck converter is set to fixed duty cycle (80%). + * Now we need set boost converter + */ + + per = HRTIM_PER_GET(hrtim, HRTIM_TIMER_TIMA); + + if (out < priv->v_in) out = priv->v_in; + if (out >= BOOST_VOLT_MAX) out = BOOST_VOLT_MAX; + + duty = 1.0 - priv->v_in / out; + +#warning TODO: current limit in buck boost mode + + cmp = (uint16_t)(per * duty); + + /* Set T12 duty cycle. T5 is complementary to T12 */ + + HRTIM_CMP_SET(hrtim, HRTIM_TIMER_TIMB, HRTIM_CMP1, cmp); + + break; + } + + default: + { + pwrerr("ERROR: Unknown converter mode %d!\n", mode); + break; + } + } +} + +/**************************************************************************** + * Name: smps_conv_mode_set + * + * Description: + * Change converter mode (buck/boost/buck-boost). + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void smps_conv_mode_set(struct smps_priv_s *priv, + struct smps_lower_dev_s *lower, + uint8_t mode) +{ + struct hrtim_dev_s *hrtim = lower->hrtim; + + /* Disable all outputs */ + + HRTIM_ALL_OUTPUTS_ENABLE(hrtim, false); + + switch (mode) + { + case CONVERTER_MODE_INIT: + { + break; + } + + case CONVERTER_MODE_BUCK: + { + /* Set T12 low (T5 high) on the next PER */ + + HRTIM_OUTPUT_SET_SET(hrtim, HRTIM_OUT_TIMB_CH1, + HRTIM_OUT_SET_NONE); + HRTIM_OUTPUT_RST_SET(hrtim, HRTIM_OUT_TIMB_CH1, + HRTIM_OUT_RST_PER); + + /* Set T4 to a high state on PER and reset on CMP1. + * T11 is complementary to T4. + */ + + HRTIM_OUTPUT_SET_SET(hrtim, HRTIM_OUT_TIMA_CH1, + HRTIM_OUT_SET_PER); + HRTIM_OUTPUT_RST_SET(hrtim, HRTIM_OUT_TIMA_CH1, + HRTIM_OUT_RST_CMP1); + + break; + } + + case CONVERTER_MODE_BOOST: + { + /* Set T4 high (T11 low) on the next PER */ + + HRTIM_OUTPUT_SET_SET(hrtim, HRTIM_OUT_TIMA_CH1, + HRTIM_OUT_SET_PER); + HRTIM_OUTPUT_RST_SET(hrtim, HRTIM_OUT_TIMA_CH1, + HRTIM_OUT_RST_NONE); + + /* Set T12 to a high state on PER and reset on CMP1. + * T5 is complementary to T12. + */ + + HRTIM_OUTPUT_SET_SET(hrtim, HRTIM_OUT_TIMB_CH1, + HRTIM_OUT_SET_PER); + HRTIM_OUTPUT_RST_SET(hrtim, HRTIM_OUT_TIMB_CH1, + HRTIM_OUT_RST_CMP1); + + break; + } + + case CONVERTER_MODE_BUCKBOOST: + { + /* Set T4 to a high state on PER and reset on CMP1. + * T11 is complementary to T4. + */ + + HRTIM_OUTPUT_SET_SET(hrtim, HRTIM_OUT_TIMA_CH1, + HRTIM_OUT_SET_PER); + HRTIM_OUTPUT_RST_SET(hrtim, HRTIM_OUT_TIMA_CH1, + HRTIM_OUT_RST_CMP1); + + /* Set T12 to a high state on PER and reset on CMP1. + * T5 is complementary to T12. + */ + + HRTIM_OUTPUT_SET_SET(hrtim, HRTIM_OUT_TIMB_CH1, + HRTIM_OUT_SET_PER); + HRTIM_OUTPUT_RST_SET(hrtim, HRTIM_OUT_TIMB_CH1, + HRTIM_OUT_RST_CMP1); + + /* Set fixed duty cycle (80%) on buck converter (T4 and T11) */ + + HRTIM_CMP_SET(hrtim, HRTIM_TIMER_TIMA, HRTIM_CMP1, + 0.8 * ((uint16_t)HRTIM_PER_GET(hrtim, + HRTIM_TIMER_TIMA))); + + break; + } + + default: + { + pwrerr("ERROR: Unknown converter mode %d!\n", mode); + break; + } + } + + /* Set mode in private data */ + + priv->conv_mode = mode; + + /* Enable outputs */ + + HRTIM_ALL_OUTPUTS_ENABLE(hrtim, true); +} + +/**************************************************************************** + * Name: adc12_handler + ****************************************************************************/ + +static void adc12_handler(void) +{ + struct smps_dev_s *dev = &g_smps_dev; + struct smps_s *smps = (struct smps_s *)dev->priv; + struct smps_priv_s *priv = (struct smps_priv_s *)smps->priv; + struct smps_lower_dev_s *lower = dev->lower; + struct stm32_adc_dev_s *adc = lower->adc; + uint32_t pending; + float ref = ADC_REF_VOLTAGE; + float bit = ADC_VAL_MAX; + float err; + float out; + uint8_t mode; + + pending = STM32_ADC_INT_GET(adc); + + if (pending & ADC_INT_JEOC && priv->running == true) + { + /* Get raw ADC values */ + + priv->v_out_raw = STM32_ADC_INJDATA_GET(adc, V_OUT_ADC_INJ_CHANNEL); + priv->v_in_raw = STM32_ADC_INJDATA_GET(adc, V_IN_ADC_INJ_CHANNEL); + + /* Convert raw values to real values */ + + priv->v_out = (priv->v_out_raw * ref / bit) * V_OUT_RATIO; + priv->v_in = (priv->v_in_raw * ref / bit) * V_IN_RATIO; + + /* According to measured voltages we set converter + * in appropriate mode + */ + + if (smps->param.v_out > (priv->v_in + SMPS_BUCKBOOST_RANGE)) + { + /* Desired output voltage greater than input voltage - set + * boost converter + */ + + mode = CONVERTER_MODE_BOOST; + } + + else if (smps->param.v_out < (priv->v_in - SMPS_BUCKBOOST_RANGE)) + { + /* Desired output voltage lower than input voltage - set + * buck converter + */ + + mode = CONVERTER_MODE_BUCK; + } + + else + { + /* Desired output voltage close to input voltage - set + * buck-boost converter + */ + + mode = CONVERTER_MODE_BUCKBOOST; + } + + /* Configure converter to the new mode if needed */ + + if (priv->conv_mode != mode) + { + smps_conv_mode_set(priv, lower, mode); + } + + /* Get regulator error */ + + err = smps->param.v_out - priv->v_out; + + if (err >= SMPS_VOLTAGE_ACCURACY || err <= (-SMPS_VOLTAGE_ACCURACY)) + { + /* PID controller */ + + out = smps_controller(priv, err); + + /* Update duty cycle */ + + smps_duty_set(priv, lower, out); + } + } + + /* Clear pending */ + + STM32_ADC_INT_ACK(adc, pending); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_smps_setup + * + * Description: + * Initialize SMPS driver. + * + * Returned Value: + * 0 on success, a negated errno value on failure + * + ****************************************************************************/ + +int stm32_smps_setup(void) +{ + struct smps_lower_dev_s *lower = &g_smps_lower; + struct smps_dev_s *smps = &g_smps_dev; + struct hrtim_dev_s *hrtim = NULL; + struct adc_dev_s *adc = NULL; + static bool initialized = false; + int ret = OK; + int i; + + /* Initialize only once */ + + if (!initialized) + { + /* Get the HRTIM interface */ + + hrtim = stm32_hrtiminitialize(); + if (hrtim == NULL) + { + pwrerr("ERROR: Failed to get HRTIM1 interface\n"); + return -ENODEV; + } + + /* Configure the pins as analog inputs for the selected channels */ + + for (i = 0; i < ADC1_NCHANNELS; i++) + { + stm32_configgpio(g_adc1pins[i]); + } + + /* Get the ADC interface */ + + adc = stm32_adcinitialize(1, g_adc1chan, ADC1_NCHANNELS); + if (adc == NULL) + { + pwrerr("ERROR: Failed to get ADC %d interface\n", 1); + return -ENODEV; + } + + /* Initialize SMPS lower driver interfaces */ + + lower->hrtim = hrtim; + lower->adc = adc->ad_priv; + lower->comp = NULL; + lower->dac = NULL; + lower->opamp = NULL; + + /* Attach ADC12 ram vector */ + + ret = arm_ramvec_attach(STM32_IRQ_ADC12, adc12_handler); + if (ret < 0) + { + pwrerr("ERROR: arm_ramvec_attach failed: %d\n", ret); + ret = EXIT_FAILURE; + goto errout; + } + + /* Set the priority of the ADC12 interrupt vector */ + + ret = up_prioritize_irq(STM32_IRQ_ADC12, NVIC_SYSH_HIGH_PRIORITY); + if (ret < 0) + { + pwrerr("ERROR: up_prioritize_irq failed: %d\n", ret); + ret = EXIT_FAILURE; + goto errout; + } + + /* Setup ADC hardware */ + + adc->ad_ops->ao_setup(adc); + + /* We do not need register character drivers for SMPS lower + * peripherals. All control should be done via SMPS character + * driver. + */ + + ret = smps_register(CONFIG_EXAMPLES_SMPS_DEVPATH, smps, (void *)lower); + if (ret < 0) + { + pwrerr("ERROR: smps_register failed: %d\n", ret); + return ret; + } + + initialized = true; + } + +errout: + return ret; +} + +#endif /* CONFIG_EXAMPLE_SMPS && CONFIG_DRIVERS_SMPS*/ diff --git a/boards/arm/stm32/stm32f334-disco/src/stm32f334-disco.h b/boards/arm/stm32f3/stm32f334-disco/src/stm32f334-disco.h similarity index 99% rename from boards/arm/stm32/stm32f334-disco/src/stm32f334-disco.h rename to boards/arm/stm32f3/stm32f334-disco/src/stm32f334-disco.h index 213f549b42778..0aac0ea8e6c43 100644 --- a/boards/arm/stm32/stm32f334-disco/src/stm32f334-disco.h +++ b/boards/arm/stm32f3/stm32f334-disco/src/stm32f334-disco.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f334-disco/src/stm32f334-disco.h + * boards/arm/stm32f3/stm32f334-disco/src/stm32f334-disco.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f3/stm32f3discovery/CMakeLists.txt b/boards/arm/stm32f3/stm32f3discovery/CMakeLists.txt new file mode 100644 index 0000000000000..898b9836865dd --- /dev/null +++ b/boards/arm/stm32f3/stm32f3discovery/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32f3/stm32f3discovery/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/arm/stm32/stm32f3discovery/Kconfig b/boards/arm/stm32f3/stm32f3discovery/Kconfig similarity index 100% rename from boards/arm/stm32/stm32f3discovery/Kconfig rename to boards/arm/stm32f3/stm32f3discovery/Kconfig diff --git a/boards/arm/stm32f3/stm32f3discovery/configs/nsh/defconfig b/boards/arm/stm32f3/stm32f3discovery/configs/nsh/defconfig new file mode 100644 index 0000000000000..e05647d329bb3 --- /dev/null +++ b/boards/arm/stm32f3/stm32f3discovery/configs/nsh/defconfig @@ -0,0 +1,53 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f3discovery" +CONFIG_ARCH_BOARD_STM32F3_DISCOVERY=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f3" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F303VC=y +CONFIG_ARCH_CHIP_STM32F3=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=6522 +CONFIG_BUILTIN=y +CONFIG_CDCACM=y +CONFIG_CDCACM_RXBUFSIZE=256 +CONFIG_CDCACM_TXBUFSIZE=256 +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_HOST_WINDOWS=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_MM_REGIONS=2 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=40960 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_PWR=y +CONFIG_STM32_USART2=y +CONFIG_STM32_USB=y +CONFIG_SYSTEM_CDCACM=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART2_RXBUFSIZE=128 +CONFIG_USART2_SERIAL_CONSOLE=y +CONFIG_USART2_TXBUFSIZE=128 diff --git a/boards/arm/stm32f3/stm32f3discovery/configs/usbnsh/defconfig b/boards/arm/stm32f3/stm32f3discovery/configs/usbnsh/defconfig new file mode 100644 index 0000000000000..ca4b9b582409e --- /dev/null +++ b/boards/arm/stm32f3/stm32f3discovery/configs/usbnsh/defconfig @@ -0,0 +1,55 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_DEV_CONSOLE is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f3discovery" +CONFIG_ARCH_BOARD_STM32F3_DISCOVERY=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f3" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F303VC=y +CONFIG_ARCH_CHIP_STM32F3=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL_USBDEVCTRL=y +CONFIG_BOARD_LOOPSPERMSEC=6522 +CONFIG_BUILTIN=y +CONFIG_CDCACM=y +CONFIG_CDCACM_CONSOLE=y +CONFIG_CDCACM_RXBUFSIZE=256 +CONFIG_CDCACM_TXBUFSIZE=256 +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_HOST_WINDOWS=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_MM_REGIONS=2 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=40960 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=27 +CONFIG_START_YEAR=2013 +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_PWR=y +CONFIG_STM32_SPI1=y +CONFIG_STM32_USART2=y +CONFIG_STM32_USB=y +CONFIG_SYSLOG_CHAR=y +CONFIG_SYSLOG_DEVPATH="/dev/ttyS0" +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 diff --git a/boards/arm/stm32f3/stm32f3discovery/include/board.h b/boards/arm/stm32f3/stm32f3discovery/include/board.h new file mode 100644 index 0000000000000..0e989224f4505 --- /dev/null +++ b/boards/arm/stm32f3/stm32f3discovery/include/board.h @@ -0,0 +1,275 @@ +/**************************************************************************** + * boards/arm/stm32f3/stm32f3discovery/include/board.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_STM32_STM32F3DISCOVERY_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32_STM32F3DISCOVERY_INCLUDE_BOARD_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#ifndef __ASSEMBLY__ +# include +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Clocking *****************************************************************/ + +/* HSI - Internal 8 MHz RC Oscillator + * LSI - 32 KHz RC + * HSE - On-board crystal frequency is 8MHz + * LSE - 32.768 kHz + */ + +#define STM32_BOARD_XTAL 8000000ul /* X1 on board */ + +#define STM32_HSI_FREQUENCY 8000000ul +#define STM32_LSI_FREQUENCY 40000 /* Between 30kHz and 60kHz */ +#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL +#define STM32_LSE_FREQUENCY 32768 /* X2 on board */ + +/* PLL source is HSE/1, + * PLL multiplier is 9: + * PLL frequency is 8MHz (XTAL) x 9 = 72MHz + */ + +#define STM32_CFGR_PLLSRC RCC_CFGR_PLLSRC +#define STM32_CFGR_PLLXTPRE 0 +#define STM32_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx9 +#define STM32_PLL_FREQUENCY (9*STM32_BOARD_XTAL) + +/* Use the PLL and set the SYSCLK source to be the PLL */ + +#define STM32_SYSCLK_SW RCC_CFGR_SW_PLL +#define STM32_SYSCLK_SWS RCC_CFGR_SWS_PLL +#define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY + +/* AHB clock (HCLK) is SYSCLK (72MHz) */ + +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK +#define STM32_HCLK_FREQUENCY STM32_PLL_FREQUENCY + +/* APB2 clock (PCLK2) is HCLK (72MHz) */ + +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK +#define STM32_PCLK2_FREQUENCY STM32_HCLK_FREQUENCY +#define STM32_APB2_CLKIN (STM32_PCLK2_FREQUENCY) /* Timers 1 and 8, 15-17 */ + +/* APB2 timers 1 and 8, 15-17 will receive PCLK2. */ + +/* Timers driven from APB2 will be PCLK2 */ + +#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB1_TIM15_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB1_TIM16_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB1_TIM17_CLKIN (STM32_PCLK2_FREQUENCY) + +/* APB1 clock (PCLK1) is HCLK/2 (36MHz) */ + +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd2 +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/2) + +/* APB1 timers 2-7 will be twice PCLK1 */ + +#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) + +/* USB divider -- Divide PLL clock by 1.5 */ + +#define STM32_CFGR_USBPRE 0 + +/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx + * otherwise frequency is 2xAPBx. + * Note: TIM1,8 are on APB2, others on APB1 + */ + +#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM2_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM3_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM4_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM5_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM6_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM7_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY + +/* LED definitions **********************************************************/ + +/* The STM32F3Discovery board has ten LEDs. Two of these are controlled by + * logic on the board and are not available for software control: + * + * LD1 PWR: red LED indicates that the board is powered. + * LD2 COM: LD2 default status is red. LD2 turns to green to indicate that + * communications are in progress between the PC and the + * ST-LINK/V2. + * + * And eight can be controlled by software: + * + * User LEDs connected to the I/O of the STM32F303VCT6. + * User LD3: red LED is a user LED connected to the PE9 I/O. + * User LD4: blue LED is a user LED connected to the PE8 I/O. + * User LD5: orange LED is a user LED connected to the PE10 I/O. + * User LD6: green LED is a user LED connected to the PE15 I/O. + * User LD7: green LED is a user LED connected to the PE11 I/O. + * User LD8: orange LED is a user LED connected to the PE14 I/O. + * User LD9: blue LED is a user LED connected to the PE12 I/O. + * User LD10: red LED is a user LED connected to the PE13 I/O. + * + * If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs in + * any way. The following definitions are used to access individual LEDs. + */ + +/* LED index values for use with board_userled() */ + +#define BOARD_LED1 0 /* User LD3 */ +#define BOARD_LED2 1 /* User LD4 */ +#define BOARD_LED3 2 /* User LD5 */ +#define BOARD_LED4 3 /* User LD6 */ +#define BOARD_LED5 4 /* User LD7 */ +#define BOARD_LED6 5 /* User LD8 */ +#define BOARD_LED7 6 /* User LD9 */ +#define BOARD_LED8 7 /* User LD10 */ +#define BOARD_NLEDS 8 + +/* LED bits for use with board_userled_all() */ + +#define BOARD_LED1_BIT (1 << BOARD_LED1) +#define BOARD_LED2_BIT (1 << BOARD_LED2) +#define BOARD_LED3_BIT (1 << BOARD_LED3) +#define BOARD_LED4_BIT (1 << BOARD_LED4) +#define BOARD_LED5_BIT (1 << BOARD_LED5) +#define BOARD_LED6_BIT (1 << BOARD_LED6) +#define BOARD_LED7_BIT (1 << BOARD_LED7) +#define BOARD_LED8_BIT (1 << BOARD_LED8) + +/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the 8 LEDs on + * board the stm32f3discovery. + * The following definitions describe how NuttX controls the LEDs: + * + * SYMBOL Meaning LED state + * Initially all LEDs are OFF + * ------------------- ----------------------- ------------- ------------ + * LED_STARTED NuttX has been started LD3 ON + * LED_HEAPALLOCATE Heap has been allocated LD4 ON + * LED_IRQSENABLED Interrupts enabled LD4 ON + * LED_STACKCREATED Idle stack created LD6 ON + * LED_INIRQ In an interrupt LD7 should glow + * LED_SIGNAL In a signal handler LD8 might glow + * LED_ASSERTION An assertion failed LD9 ON while handling + * the assertion + * LED_PANIC The system has crashed LD10 Blinking at 2Hz + * LED_IDLE STM32 is in sleep mode (Optional, not used) + */ + +#define LED_STARTED 0 +#define LED_HEAPALLOCATE 1 +#define LED_IRQSENABLED 2 +#define LED_STACKCREATED 3 +#define LED_INIRQ 4 +#define LED_SIGNAL 5 +#define LED_ASSERTION 6 +#define LED_PANIC 7 + +/* Button definitions *******************************************************/ + +/* The STM32F3Discovery supports two buttons; only one button is controllable + * by software: + * + * B1 USER: + * user and wake-up button connected to the I/O PA0 of the + * STM32F303VCT6. + * B2 RESET: + * pushbutton connected to NRST is used to RESET the STM32F303VCT6. + */ + +#define BUTTON_USER 0 + +#define NUM_BUTTONS 1 + +#define BUTTON_USER_BIT (1 << BUTTON_USER) + +/* Alternate function pin selections ****************************************/ + +/* USART + * + * USART1: Hardwired to embedded STLinkV2 hardware debugger + * RX (PC5) + * TX (PC4) + * + * USART2: + * Connect to an external UART<->RS232 transceiver for use as console. + * RX (PA3) + * TX (PA2) + */ + +#define GPIO_USART2_RX (GPIO_USART2_RX_2|GPIO_SPEED_50MHz) +#define GPIO_USART2_TX (GPIO_USART2_TX_2|GPIO_SPEED_50MHz) + +/* SPI + * + * SPI1: Hardwired to ST L3GD20 MEMS device + * MISO (PA6) + * MSOI (PA7) + * SCK (PA5) + */ + +#define GPIO_SPI1_MISO GPIO_SPI1_MISO_1 +#define GPIO_SPI1_MOSI GPIO_SPI1_MOSI_1 +#define GPIO_SPI1_SCK GPIO_SPI1_SCK_1 + +/* I2C + * + * I2C1: Accessible via expansion headers + * SCL (PA15) + * SDA (PA14) + * SMBA (PB5) + * + * I2C2: Accessible via expansion headers + * SCL (PA9) + * SDA (PA10) + * SMBA (PB12) + */ + +#ifdef CONFIG_STM32_I2C1 +#define GPIO_I2C1_SCL (GPIO_I2C1_SCL_1|GPIO_SPEED_50MHz) +#define GPIO_I2C1_SDA (GPIO_I2C1_SDA_1|GPIO_SPEED_50MHz) +#endif + +#ifdef CONFIG_STM32_I2C2 +#define GPIO_I2C2_SCL (GPIO_I2C2_SCL_1|GPIO_SPEED_50MHz) +#define GPIO_I2C2_SDA (GPIO_I2C2_SDA_1|GPIO_SPEED_50MHz) +#endif + +/* USB */ + +#define GPIO_USB_DM (GPIO_USB_DM_0|GPIO_SPEED_50MHz) +#define GPIO_USB_DP (GPIO_USB_DP_0|GPIO_SPEED_50MHz) + +#endif /* __BOARDS_ARM_STM32_STM32F3DISCOVERY_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32f3/stm32f3discovery/scripts/Make.defs b/boards/arm/stm32f3/stm32f3discovery/scripts/Make.defs new file mode 100644 index 0000000000000..be421233cda68 --- /dev/null +++ b/boards/arm/stm32f3/stm32f3discovery/scripts/Make.defs @@ -0,0 +1,41 @@ +############################################################################ +# boards/arm/stm32f3/stm32f3discovery/scripts/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/.config +include $(TOPDIR)/tools/Config.mk +include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs + +LDSCRIPT = ld.script +ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) + +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32f3/stm32f3discovery/scripts/ld.script b/boards/arm/stm32f3/stm32f3discovery/scripts/ld.script new file mode 100644 index 0000000000000..a54ec9fcb66f1 --- /dev/null +++ b/boards/arm/stm32f3/stm32f3discovery/scripts/ld.script @@ -0,0 +1,121 @@ +/**************************************************************************** + * boards/arm/stm32f3/stm32f3discovery/scripts/ld.script + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* The STM32F303VCT has 256Kb of FLASH beginning at address 0x0800:0000 and + * 40Kb of SRAM. + * + * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 + * where the code expects to begin execution by jumping to the entry point in + * the 0x0800:0000 address range. + */ + +MEMORY +{ + flash (rx) : ORIGIN = 0x08000000, LENGTH = 256K + sram (rwx) : ORIGIN = 0x20000000, LENGTH = 40K +} + +OUTPUT_ARCH(arm) +EXTERN(_vectors) +ENTRY(_stext) +SECTIONS +{ + .text : { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > flash + + .init_section : ALIGN(4) { + _sinit = ABSOLUTE(.); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) + _einit = ABSOLUTE(.); + } > flash + + .ARM.extab : ALIGN(4) { + *(.ARM.extab*) + } > flash + + .ARM.exidx : ALIGN(4) { + __exidx_start = ABSOLUTE(.); + *(.ARM.exidx*) + __exidx_end = ABSOLUTE(.); + } > flash + + .tdata : { + _stdata = ABSOLUTE(.); + *(.tdata .tdata.* .gnu.linkonce.td.*); + _etdata = ABSOLUTE(.); + } > flash + + .tbss : { + _stbss = ABSOLUTE(.); + *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); + _etbss = ABSOLUTE(.); + } > flash + + _eronly = ABSOLUTE(.); + + .data : ALIGN(4) { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > sram AT > flash + + .bss : ALIGN(4) { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + _ebss = ABSOLUTE(.); + } > sram + + /* Stabs debugging sections. */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/stm32f3/stm32f3discovery/src/CMakeLists.txt b/boards/arm/stm32f3/stm32f3discovery/src/CMakeLists.txt new file mode 100644 index 0000000000000..b630617db143d --- /dev/null +++ b/boards/arm/stm32f3/stm32f3discovery/src/CMakeLists.txt @@ -0,0 +1,45 @@ +# ############################################################################## +# boards/arm/stm32f3/stm32f3discovery/src/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(SRCS stm32_boot.c stm32_bringup.c stm32_spi.c) + +if(CONFIG_ARCH_LEDS) + list(APPEND SRCS stm32_autoleds.c) +else() + list(APPEND SRCS stm32_userleds.c) +endif() + +if(CONFIG_ARCH_BUTTONS) + list(APPEND SRCS stm32_buttons.c) +endif() + +if(CONFIG_STM32_USB) + list(APPEND SRCS stm32_usb.c) +endif() + +if(CONFIG_PWM) + list(APPEND SRCS stm32_pwm.c) +endif() + +target_sources(board PRIVATE ${SRCS}) + +set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/ld.script") diff --git a/boards/arm/stm32f3/stm32f3discovery/src/Make.defs b/boards/arm/stm32f3/stm32f3discovery/src/Make.defs new file mode 100644 index 0000000000000..726b069c0ef0d --- /dev/null +++ b/boards/arm/stm32f3/stm32f3discovery/src/Make.defs @@ -0,0 +1,47 @@ +############################################################################ +# boards/arm/stm32f3/stm32f3discovery/src/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +CSRCS = stm32_boot.c stm32_bringup.c stm32_spi.c + +ifeq ($(CONFIG_ARCH_LEDS),y) +CSRCS += stm32_autoleds.c +else +CSRCS += stm32_userleds.c +endif + +ifeq ($(CONFIG_ARCH_BUTTONS),y) +CSRCS += stm32_buttons.c +endif + +ifeq ($(CONFIG_STM32_USB),y) +CSRCS += stm32_usb.c +endif + +ifeq ($(CONFIG_PWM),y) +CSRCS += stm32_pwm.c +endif + +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32f3/stm32f3discovery/src/stm32_autoleds.c b/boards/arm/stm32f3/stm32f3discovery/src/stm32_autoleds.c new file mode 100644 index 0000000000000..a88f93396fb4a --- /dev/null +++ b/boards/arm/stm32f3/stm32f3discovery/src/stm32_autoleds.c @@ -0,0 +1,108 @@ +/**************************************************************************** + * boards/arm/stm32f3/stm32f3discovery/src/stm32_autoleds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "chip.h" +#include "stm32.h" +#include "stm32f3discovery.h" + +#ifdef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* This array maps an LED number to GPIO pin configuration */ + +static const uint32_t g_ledcfg[BOARD_NLEDS] = +{ + GPIO_LED1, GPIO_LED2, GPIO_LED3, GPIO_LED4, + GPIO_LED5, GPIO_LED6, GPIO_LED7, GPIO_LED8 +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_autoled_onoff + ****************************************************************************/ + +void board_autoled_onoff(int led, bool state) +{ + if ((unsigned)led < BOARD_NLEDS) + { + stm32_gpiowrite(g_ledcfg[led], state); + } +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_autoled_initialize + ****************************************************************************/ + +void board_autoled_initialize(void) +{ + int i; + + /* Configure LED1-8 GPIOs for output */ + + for (i = 0; i < BOARD_NLEDS; i++) + { + stm32_configgpio(g_ledcfg[i]); + } +} + +/**************************************************************************** + * Name: board_autoled_on + ****************************************************************************/ + +void board_autoled_on(int led) +{ + board_autoled_onoff(led, true); +} + +/**************************************************************************** + * Name: board_autoled_off + ****************************************************************************/ + +void board_autoled_off(int led) +{ + board_autoled_onoff(led, false); +} + +#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32f3/stm32f3discovery/src/stm32_boot.c b/boards/arm/stm32f3/stm32f3discovery/src/stm32_boot.c new file mode 100644 index 0000000000000..88ceb8fb8611d --- /dev/null +++ b/boards/arm/stm32f3/stm32f3discovery/src/stm32_boot.c @@ -0,0 +1,105 @@ +/**************************************************************************** + * boards/arm/stm32f3/stm32f3discovery/src/stm32_boot.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include +#include + +#include "arm_internal.h" +#include "stm32f3discovery.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_boardinitialize + * + * Description: + * All STM32 architectures must provide the following entry point. + * This entry point is called early in the initialization -- after all + * memory has been configured and mapped but before any devices have been + * initialized. + * + ****************************************************************************/ + +void stm32_boardinitialize(void) +{ + /* Configure SPI chip selects if 1) SPI is not disabled, and 2) the weak + * function stm32_spidev_initialize() has been brought into the link. + */ + +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || defined(CONFIG_STM32_SPI3) + if (stm32_spidev_initialize) + { + stm32_spidev_initialize(); + } +#endif + + /* Initialize USB if the 1) USB device controller is in the configuration + * and 2) disabled, and 3) the weak function stm32_usbinitialize() has + * been brought into the build. Presumably either CONFIG_USBDEV is also + * selected. + */ + +#ifdef CONFIG_STM32_USB + if (stm32_usbinitialize) + { + stm32_usbinitialize(); + } +#endif + + /* Configure on-board LEDs if LED support has been selected. */ + +#ifdef CONFIG_ARCH_LEDS + board_autoled_initialize(); +#endif +} + +/**************************************************************************** + * Name: board_late_initialize + * + * Description: + * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_late_initialize(). board_late_initialize() will be + * called immediately after up_initialize() is called and just before the + * initial application is started. This additional initialization phase + * may be used, for example, to initialize board-specific device drivers. + * + ****************************************************************************/ + +#ifdef CONFIG_BOARD_LATE_INITIALIZE +void board_late_initialize(void) +{ + /* Perform board-specific initialization */ + + stm32_bringup(); +} +#endif diff --git a/boards/arm/stm32f3/stm32f3discovery/src/stm32_bringup.c b/boards/arm/stm32f3/stm32f3discovery/src/stm32_bringup.c new file mode 100644 index 0000000000000..4b4f5a63b7323 --- /dev/null +++ b/boards/arm/stm32f3/stm32f3discovery/src/stm32_bringup.c @@ -0,0 +1,141 @@ +/**************************************************************************** + * boards/arm/stm32f3/stm32f3discovery/src/stm32_bringup.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include + +#ifdef CONFIG_USBMONITOR +# include +#endif + +#include "stm32.h" +#include "stm32f3discovery.h" + +#ifdef CONFIG_SENSORS_QENCODER +#include "board_qencoder.h" +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +#define HAVE_USBDEV 1 +#define HAVE_USBMONITOR 1 + +/* Can't support USB device features if the STM32 USB peripheral is not + * enabled. + */ + +#ifndef CONFIG_STM32_USB +# undef HAVE_USBDEV +#endif + +/* Can't support USB device is USB device is not enabled */ + +#ifndef CONFIG_USBDEV +# undef HAVE_USBDEV +#endif + +/* Check if we should enable the USB monitor before starting NSH */ + +#ifndef CONFIG_USBMONITOR +# undef HAVE_USBMONITOR +#endif + +#ifndef HAVE_USBDEV +# undef CONFIG_USBDEV_TRACE +#endif + +#ifndef HAVE_USBHOST +# undef CONFIG_USBHOST_TRACE +#endif + +#if !defined(CONFIG_USBDEV_TRACE) && !defined(CONFIG_USBHOST_TRACE) +# undef HAVE_USBMONITOR +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_bringup + * + * Description: + * Perform architecture-specific initialization + * + * CONFIG_BOARD_LATE_INITIALIZE=y : + * Called from board_late_initialize(). + * + ****************************************************************************/ + +int stm32_bringup(void) +{ + int ret = OK; + +#ifdef HAVE_USBMONITOR + /* Start the USB Monitor */ + + ret = usbmonitor_start(); + if (ret != OK) + { + syslog(LOG_ERR, "ERROR: Failed to start USB monitor: %d\n", ret); + } +#endif + +#ifdef CONFIG_PWM + /* Initialize PWM and register the PWM device. */ + + ret = stm32_pwm_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_pwm_setup() failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_SENSORS_QENCODER + /* Initialize and register the qencoder driver */ + + ret = board_qencoder_initialize(0, CONFIG_STM32F3DISCO_QETIMER); + if (ret != OK) + { + syslog(LOG_ERR, + "ERROR: Failed to register the qencoder: %d\n", + ret); + return ret; + } +#endif + + return ret; +} diff --git a/boards/arm/stm32f3/stm32f3discovery/src/stm32_buttons.c b/boards/arm/stm32f3/stm32f3discovery/src/stm32_buttons.c new file mode 100644 index 0000000000000..b95f1899118dc --- /dev/null +++ b/boards/arm/stm32f3/stm32f3discovery/src/stm32_buttons.c @@ -0,0 +1,150 @@ +/**************************************************************************** + * boards/arm/stm32f3/stm32f3discovery/src/stm32_buttons.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include +#include + +#include "stm32f3discovery.h" + +#ifdef CONFIG_ARCH_BUTTONS + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* Pin configuration for each STM32F3Discovery button. This array is indexed + * by the BUTTON_* definitions in board.h + */ + +static const uint32_t g_buttons[NUM_BUTTONS] = +{ + GPIO_BTN_USER +}; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_button_initialize + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. + * + ****************************************************************************/ + +uint32_t board_button_initialize(void) +{ + int i; + + /* Configure the GPIO pins as inputs. NOTE that EXTI interrupts are + * configured for all pins. + */ + + for (i = 0; i < NUM_BUTTONS; i++) + { + stm32_configgpio(g_buttons[i]); + } + + return NUM_BUTTONS; +} + +/**************************************************************************** + * Name: board_buttons + ****************************************************************************/ + +uint32_t board_buttons(void) +{ + uint32_t ret = 0; + int i; + + /* Check that state of each key */ + + for (i = 0; i < NUM_BUTTONS; i++) + { + /* A LOW value means that the key is pressed. */ + + bool released = stm32_gpioread(g_buttons[i]); + + /* Accumulate the set of depressed (not released) keys */ + + if (!released) + { + ret |= (1 << i); + } + } + + return ret; +} + +/**************************************************************************** + * Button support. + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. + * + * After board_button_initialize() has been called, board_buttons() may be + * called to collect the state of all buttons. board_buttons() returns an + * 32-bit bit set with each bit associated with a button. See the + * BUTTON_*_BIT definitions in board.h for the meaning of each bit. + * + * board_button_irq() may be called to register an interrupt handler that + * will be called when a button is depressed or released. The ID value is a + * button enumeration value that uniquely identifies a button resource. See + * the BUTTON_* definitions in board.h for the meaning of enumeration + * value. + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_IRQBUTTONS +int board_button_irq(int id, xcpt_t irqhandler, void *arg) +{ + int ret = -EINVAL; + + /* The following should be atomic */ + + if (id >= MIN_IRQBUTTON && id <= MAX_IRQBUTTON) + { + ret = stm32_gpiosetevent(g_buttons[id], true, true, true, + irqhandler, arg); + } + + return ret; +} +#endif +#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/stm32f3/stm32f3discovery/src/stm32_pwm.c b/boards/arm/stm32f3/stm32f3discovery/src/stm32_pwm.c new file mode 100644 index 0000000000000..132b6bbdf5630 --- /dev/null +++ b/boards/arm/stm32f3/stm32f3discovery/src/stm32_pwm.c @@ -0,0 +1,127 @@ +/**************************************************************************** + * boards/arm/stm32f3/stm32f3discovery/src/stm32_pwm.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include + +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32_pwm.h" +#include "stm32f3discovery.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* PWM + * + * The stm32f3discovery has no real on-board PWM devices, but the board can + * be configured to output a pulse train using TIM4 CH2. This pin is used + * by FSMC is connected to CN5 just for this purpose: + * + * PD13 FSMC_A18 / MC_TIM4_CH2OUT pin 33 (EnB) + * + * FSMC must be disabled in this case! + */ + +#define HAVE_PWM 1 + +#ifndef CONFIG_PWM +# undef HAVE_PWM +#endif + +#ifndef CONFIG_STM32_TIM4 +# undef HAVE_PWM +#endif + +#ifndef CONFIG_STM32_TIM4_PWM +# undef HAVE_PWM +#endif + +#if CONFIG_STM32_TIM4_CHANNEL != STM32F3DISCOVERY_PWMCHANNEL +# undef HAVE_PWM +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_pwm_setup + * + * Description: + * Initialize PWM and register the PWM device. + * + ****************************************************************************/ + +int stm32_pwm_setup(void) +{ +#ifdef HAVE_PWM + static bool initialized = false; + struct pwm_lowerhalf_s *pwm; + int ret; + + /* Have we already initialized? */ + + if (!initialized) + { + /* Call stm32_pwminitialize() to get an instance of the PWM interface */ + + pwm = stm32_pwminitialize(STM32F3DISCOVERY_PWMTIMER); + if (!pwm) + { + aerr("ERROR: Failed to get the STM32 PWM lower half\n"); + return -ENODEV; + } + + /* Register the PWM driver at "/dev/pwm0" */ + + ret = pwm_register("/dev/pwm0", pwm); + if (ret < 0) + { + aerr("ERROR: pwm_register failed: %d\n", ret); + return ret; + } + + /* Now we are initialized */ + + initialized = true; + } + + return OK; +#else + return -ENODEV; +#endif +} diff --git a/boards/arm/stm32f3/stm32f3discovery/src/stm32_spi.c b/boards/arm/stm32f3/stm32f3discovery/src/stm32_spi.c new file mode 100644 index 0000000000000..9b9e324250dd4 --- /dev/null +++ b/boards/arm/stm32f3/stm32f3discovery/src/stm32_spi.c @@ -0,0 +1,182 @@ +/**************************************************************************** + * boards/arm/stm32f3/stm32f3discovery/src/stm32_spi.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include + +#include "arm_internal.h" +#include "chip.h" +#include "stm32.h" +#include "stm32f3discovery.h" + +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || defined(CONFIG_STM32_SPI3) + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_spidev_initialize + * + * Description: + * Called to configure SPI chip select GPIO pins for the stm32f3discovery + * board. + * + ****************************************************************************/ + +void weak_function stm32_spidev_initialize(void) +{ +#ifdef CONFIG_STM32_SPI1 + stm32_configgpio(GPIO_MEMS_CS); /* MEMS chip select */ + stm32_configgpio(GPIO_MEMS_INT1); /* MEMS interrupts */ + stm32_configgpio(GPIO_MEMS_INT2); +#endif +} + +/**************************************************************************** + * Name: stm32_spi1/2/3select and stm32_spi1/2/3status + * + * Description: + * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status + * must be provided by board-specific logic. They are implementations of + * the select and status methods of the SPI interface defined by struct + * spi_ops_s (see include/nuttx/spi/spi.h). All other methods + * (including stm32_spibus_initialize()) are provided by common STM32 logic. + * To use this common SPI logic on your board: + * + * 1. Provide logic in stm32_boardinitialize() to configure SPI chip select + * pins. + * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() functions + * in your board-specific logic. These functions will perform chip + * selection and status operations using GPIOs in the way your board is + * configured. + * 3. Add a calls to stm32_spibus_initialize() in your low level + * application initialization logic + * 4. The handle returned by stm32_spibus_initialize() may then be used to + * bind the SPI driver to higher level logic (e.g., calling + * mmcsd_spislotinitialize(), for example, will bind the SPI driver to + * the SPI MMC/SD driver). + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_SPI1 +void stm32_spi1select(struct spi_dev_s *dev, + uint32_t devid, bool selected) +{ + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); + + stm32_gpiowrite(GPIO_MEMS_CS, !selected); +} + +uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} +#endif + +#ifdef CONFIG_STM32_SPI2 +void stm32_spi2select(struct spi_dev_s *dev, + uint32_t devid, bool selected) +{ + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); +} + +uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} +#endif + +#ifdef CONFIG_STM32_SPI3 +void stm32_spi3select(struct spi_dev_s *dev, + uint32_t devid, bool selected) +{ + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); +} + +uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} +#endif + +/**************************************************************************** + * Name: stm32_spi1cmddata + * + * Description: + * Set or clear the SH1101A A0 or SD1306 D/C n bit to select data (true) + * or command (false). This function must be provided by platform-specific + * logic. This is an implementation of the cmddata method of the SPI + * interface defined by struct spi_ops_s (see include/nuttx/spi/spi.h). + * + * Input Parameters: + * + * spi - SPI device that controls the bus the device that requires the CMD/ + * DATA selection. + * devid - If there are multiple devices on the bus, this selects which one + * to select cmd or data. NOTE: This design restricts, for example, + * one one SPI display per SPI bus. + * cmd - true: select command; false: select data + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_SPI_CMDDATA +#ifdef CONFIG_STM32_SPI1 +int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) +{ + return -ENODEV; +} +#endif + +#ifdef CONFIG_STM32_SPI2 +int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) +{ + return -ENODEV; +} +#endif + +#ifdef CONFIG_STM32_SPI3 +int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) +{ + return -ENODEV; +} +#endif +#endif /* CONFIG_SPI_CMDDATA */ + +#endif /* CONFIG_STM32_SPI1 || CONFIG_STM32_SPI2 */ diff --git a/boards/arm/stm32f3/stm32f3discovery/src/stm32_usb.c b/boards/arm/stm32f3/stm32f3discovery/src/stm32_usb.c new file mode 100644 index 0000000000000..7084ab7babdea --- /dev/null +++ b/boards/arm/stm32f3/stm32f3discovery/src/stm32_usb.c @@ -0,0 +1,116 @@ +/**************************************************************************** + * boards/arm/stm32f3/stm32f3discovery/src/stm32_usb.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include + +#include +#include + +#include "arm_internal.h" +#include "stm32.h" +#include "stm32f3discovery.h" + +#ifdef CONFIG_STM32_USB + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifdef CONFIG_USBDEV +# define HAVE_USB 1 +#else +# warning "CONFIG_STM32_USB is enabled but CONFIG_USBDEV is not" +# undef HAVE_USB +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_usbinitialize + * + * Description: + * Called from stm32_usbinitialize very early in initialization to setup + * USB-related GPIO pins for the STM32F3Discovery board. + * + ****************************************************************************/ + +void stm32_usbinitialize(void) +{ + /* Does the STM32 F3 have an external soft pull-up? */ +} + +/**************************************************************************** + * Name: stm32_usbpullup + * + * Description: + * If USB is supported and the board supports a pullup via GPIO (for USB + * software connect and disconnect), then the board software must provide + * stm32_pullup. + * See include/nuttx/usb/usbdev.h for additional description of this + * method. + * + ****************************************************************************/ + +int stm32_usbpullup(struct usbdev_s *dev, bool enable) +{ + usbtrace(TRACE_DEVPULLUP, (uint16_t)enable); + return OK; +} + +/**************************************************************************** + * Name: stm32_usbsuspend + * + * Description: + * Board logic must provide the stm32_usbsuspend logic if the USBDEV driver + * is used. This function is called whenever the USB enters or leaves + * suspend mode. This is an opportunity for the board logic to shutdown + * clocks, power, etc. while the USB is suspended. + * + ****************************************************************************/ + +void stm32_usbsuspend(struct usbdev_s *dev, bool resume) +{ + uinfo("Resume: %d\n", resume); +} + +#endif /* CONFIG_STM32_USB */ diff --git a/boards/arm/stm32f3/stm32f3discovery/src/stm32_userleds.c b/boards/arm/stm32f3/stm32f3discovery/src/stm32_userleds.c new file mode 100644 index 0000000000000..f38041a78a167 --- /dev/null +++ b/boards/arm/stm32f3/stm32f3discovery/src/stm32_userleds.c @@ -0,0 +1,103 @@ +/**************************************************************************** + * boards/arm/stm32f3/stm32f3discovery/src/stm32_userleds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include + +#include "chip.h" +#include "stm32.h" +#include "stm32f3discovery.h" + +#ifndef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* This array maps an LED number to GPIO pin configuration */ + +static const uint32_t g_ledcfg[BOARD_NLEDS] = +{ + GPIO_LED1, GPIO_LED2, GPIO_LED3, GPIO_LED4, + GPIO_LED5, GPIO_LED6, GPIO_LED7, GPIO_LED8 +}; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_userled_initialize + ****************************************************************************/ + +uint32_t board_userled_initialize(void) +{ + int i; + + /* Configure LED1-8 GPIOs for output */ + + for (i = 0; i < BOARD_NLEDS; i++) + { + stm32_configgpio(g_ledcfg[i]); + } + + return BOARD_NLEDS; +} + +/**************************************************************************** + * Name: board_userled + ****************************************************************************/ + +void board_userled(int led, bool ledon) +{ + if ((unsigned)led < BOARD_NLEDS) + { + stm32_gpiowrite(g_ledcfg[led], ledon); + } +} + +/**************************************************************************** + * Name: board_userled_all + ****************************************************************************/ + +void board_userled_all(uint32_t ledset) +{ + int i; + + /* Configure LED1-8 GPIOs for output */ + + for (i = 0; i < BOARD_NLEDS; i++) + { + stm32_gpiowrite(g_ledcfg[i], (ledset & (1 << i)) != 0); + } +} + +#endif /* !CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/stm32f3discovery/src/stm32f3discovery.h b/boards/arm/stm32f3/stm32f3discovery/src/stm32f3discovery.h similarity index 98% rename from boards/arm/stm32/stm32f3discovery/src/stm32f3discovery.h rename to boards/arm/stm32f3/stm32f3discovery/src/stm32f3discovery.h index 44464bcf3a854..79b1062803433 100644 --- a/boards/arm/stm32/stm32f3discovery/src/stm32f3discovery.h +++ b/boards/arm/stm32f3/stm32f3discovery/src/stm32f3discovery.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f3discovery/src/stm32f3discovery.h + * boards/arm/stm32f3/stm32f3discovery/src/stm32f3discovery.h * * SPDX-License-Identifier: Apache-2.0 * @@ -33,7 +33,7 @@ #include -#include +#include #include "stm32.h" diff --git a/boards/arm/stm32f4/axoloti/CMakeLists.txt b/boards/arm/stm32f4/axoloti/CMakeLists.txt new file mode 100644 index 0000000000000..83d2d132d5d67 --- /dev/null +++ b/boards/arm/stm32f4/axoloti/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32f4/axoloti/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/arm/stm32/axoloti/Kconfig b/boards/arm/stm32f4/axoloti/Kconfig similarity index 100% rename from boards/arm/stm32/axoloti/Kconfig rename to boards/arm/stm32f4/axoloti/Kconfig diff --git a/boards/arm/stm32f4/axoloti/configs/nsh/defconfig b/boards/arm/stm32f4/axoloti/configs/nsh/defconfig new file mode 100644 index 0000000000000..00ea1126c4189 --- /dev/null +++ b/boards/arm/stm32f4/axoloti/configs/nsh/defconfig @@ -0,0 +1,40 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_ARCH_LEDS is not set +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_STANDARD_SERIAL is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="axoloti" +CONFIG_ARCH_BOARD_AXOLOTI=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F427I=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_IRQBUTTONS=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INPUT=y +CONFIG_INPUT_BUTTONS=y +CONFIG_INPUT_BUTTONS_LOWER=y +CONFIG_LIBC_FLOATINGPOINT=y +CONFIG_MM_REGIONS=2 +CONFIG_RAW_BINARY=y +CONFIG_STM32_CCMEXCLUDE=y +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_JTAG_FULL_ENABLE=y +CONFIG_STM32_USART1=y +CONFIG_STM32_USART6=y +CONFIG_SYSTEM_NSH=y +CONFIG_USART1_SERIAL_CONSOLE=y +CONFIG_USART6_BAUD=31250 +CONFIG_USART6_RXBUFSIZE=128 +CONFIG_USART6_TXBUFSIZE=32 +CONFIG_USERLED=y +CONFIG_USERLED_LOWER=y diff --git a/boards/arm/stm32f4/axoloti/include/board.h b/boards/arm/stm32f4/axoloti/include/board.h new file mode 100644 index 0000000000000..07a076bda5aa6 --- /dev/null +++ b/boards/arm/stm32f4/axoloti/include/board.h @@ -0,0 +1,263 @@ +/**************************************************************************** + * boards/arm/stm32f4/axoloti/include/board.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_STM32_AXOLOTI_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32_AXOLOTI_INCLUDE_BOARD_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#ifndef __ASSEMBLY__ +# include +# include +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Clocking + * The Axoloti board has an external 8MHz crystal. + * The SoC can run at 180MHz, but the required USB clock of 48MHz cannot be + * configured at that system clock rate, so the core clock is 168MHz. + * + * This is the canonical configuration: + * System Clock source : PLL (HSE) + * SYSCLK(Hz) : 168000000 Determined by PLL configuration + * HCLK(Hz) : 168000000 (STM32_RCC_CFGR_HPRE) + * AHB Prescaler : 1 (STM32_RCC_CFGR_HPRE) + * APB1 Prescaler : 4 (STM32_RCC_CFGR_PPRE1) + * APB2 Prescaler : 2 (STM32_RCC_CFGR_PPRE2) + * HSE Frequency(Hz) : 8000000 (STM32_BOARD_XTAL) + * PLLM : 8 (STM32_PLLCFG_PLLM) + * PLLN : 336 (STM32_PLLCFG_PLLN) + * PLLP : 2 (STM32_PLLCFG_PLLP) + * PLLQ : 7 (STM32_PLLCFG_PLLQ) + * Main regulator + * output voltage : Scale1 mode Needed for high speed SYSCLK + * Flash Latency(WS) : 5 + * Prefetch Buffer : OFF + * Instruction cache : ON + * Data cache : ON + * Require 48MHz for + * USB OTG FS, + * SDIO and RNG clock : Enabled + */ + +/* HSI - 16 MHz RC factory-trimmed + * LSI - 32 KHz RC + * HSE - On-board crystal frequency is 8MHz + * LSE - 32.768 kHz + */ + +#define STM32_BOARD_XTAL 8000000ul + +#define STM32_HSI_FREQUENCY 16000000ul +#define STM32_LSI_FREQUENCY 32000 +#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL +#define STM32_LSE_FREQUENCY 32768 + +/* Main PLL Configuration. + * + * PLL source is HSE + * PLL_VCO = (STM32_HSE_FREQUENCY / PLLM) * PLLN + * = (8,000,000 / 8) * 336 + * = 336,000,000 + * SYSCLK = PLL_VCO / PLLP + * = 336,000,000 / 2 = 168,000,000 + * USB OTG FS, SDIO and RNG Clock + * = PLL_VCO / PLLQ + * = 48,000,000 + */ + +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(8) +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(336) +#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_2 +#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(7) + +#define STM32_SYSCLK_FREQUENCY 168000000ul + +/* AHB clock (HCLK) is SYSCLK (168MHz) */ + +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY + +/* APB1 clock (PCLK1) is HCLK/4 (42MHz) */ + +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd4 /* PCLK1 = HCLK / 4 */ +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/4) + +/* APB2 clock (PCLK2) is HCLK/2 (84MHz) */ + +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLKd2 /* PCLK2 = HCLK / 2 */ +#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/2) + +/**************************************************************************** + * LED Definitions + * If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs in + * any way. The following definitions are used to access individual LEDs. + */ + +/* LED index values for use with board_userled() */ + +#define BOARD_LED1 0 +#define BOARD_LED2 1 +#define BOARD_NLEDS 2 +#define BOARD_LED_GREEN BOARD_LED1 +#define BOARD_LED_RED BOARD_LED2 + +/* LED bits for use with board_userled_all() */ + +#define BOARD_LED1_BIT (1 << BOARD_LED1) +#define BOARD_LED2_BIT (1 << BOARD_LED2) + +/**************************************************************************** + * Button Definitions + * There are two buttons on the axoloti, one of them is GPIO connected. The + * other is a reset button and is not under software control. + */ + +#define BUTTON_USER 0 +#define NUM_BUTTONS 1 +#define BUTTON_USER_BIT (1 << BUTTON_USER) + +/**************************************************************************** + * UARTs + * The MIDI in/out ports of the axoloti are connected on USART6. + * It maybe convenient to run a serial port connected to the header pins, + * so we can optionally use USART1 for that. + */ + +/* USART1 - console on header pins */ + +#define GPIO_USART1_RX (GPIO_USART1_RX_2|GPIO_SPEED_100MHz) /* AF7, PB7 */ +#define GPIO_USART1_TX (GPIO_USART1_TX_2|GPIO_SPEED_100MHz) /* AF7, PB6 */ + +/* USART6 - midi in/out */ + +#define GPIO_USART6_RX (GPIO_ALT|GPIO_AF8|GPIO_PORTG|GPIO_PIN9| \ + GPIO_PULLUP|GPIO_SPEED_2MHz|GPIO_PUSHPULL) + +#define GPIO_USART6_TX (GPIO_ALT|GPIO_AF8|GPIO_PORTG|GPIO_PIN14| \ + GPIO_FLOAT|GPIO_SPEED_2MHz|GPIO_OPENDRAIN) + +/**************************************************************************** + * I2C Bus + * Turn on the internal pullups since there are no external pullups. + */ + +/* I2C1 - for external devices */ + +#define GPIO_I2C1_SCL (GPIO_ALT|GPIO_AF4|GPIO_PORTB|GPIO_PIN8| \ + GPIO_SPEED_2MHz|GPIO_OPENDRAIN|GPIO_PULLUP) + +#define GPIO_I2C1_SDA (GPIO_ALT|GPIO_AF4|GPIO_PORTB|GPIO_PIN9| \ + GPIO_SPEED_2MHz|GPIO_OPENDRAIN|GPIO_PULLUP) + +/* I2C3 - for the ADAU1961 codec */ + +#define GPIO_I2C3_SCL (GPIO_ALT|GPIO_AF4|GPIO_PORTH|GPIO_PIN7| \ + GPIO_SPEED_2MHz|GPIO_OPENDRAIN|GPIO_PULLUP) + +#define GPIO_I2C3_SDA (GPIO_ALT|GPIO_AF4|GPIO_PORTH|GPIO_PIN8| \ + GPIO_SPEED_2MHz|GPIO_OPENDRAIN|GPIO_PULLUP) + +/**************************************************************************** + * SAI Bus + * Used with the ADAU1961 CODEC + * PE3_SAI1_SD_B (GPIO_SAI1_SD_B_1) + * PE4_SAI1_FS_A (GPIO_SAI1_FS_A) + * PE5_SAI1_SCK_A (GPIO_SAI1_SCK_A) + * PE6_SAI1_SD_A (GPIO_SAI1_SD_A_2) + * PA8_MCO1 + */ + +#define GPIO_SAI1_SD_B GPIO_SAI1_SD_B_1 /* AF6, PE3 */ +#define GPIO_SAI1_SD_A GPIO_SAI1_SD_A_2 /* AF6, PE6 */ + +#define STM32_SAI1_FREQUENCY (48000 * 2 * 256) /* TODO ?? */ + +/* DAC DMA to Codec + * dma 2, stream 1, channel 0 + * memory to peripheral + * 32 bits + */ +#define DMACHAN_SAI1_A DMAMAP_SAI1_A_1 + +/* ADC DMA from Codec + * dma 2, stream 4, channel 1, + * peripheral to memory + * 32 bits + */ +#define DMACHAN_SAI1_B DMAMAP_SAI1_B_2 + +/**************************************************************************** + * SDIO + * Used for the SD card interface. + * d0 (AF12, PC8) + * d1 (AF12, PC9) + * d2 (AF12, PC10) + * d3 (AF12, PC11) + * clk (AF12, PC12) + * cmd (AF12, PD2) + * cd1 PD13 + */ + +/* SDIO dividers. Note that slower clocking is required when DMA is disabled + * in order to avoid RX overrun/TX underrun errors due to delayed responses + * to service FIFOs in interrupt driven mode. These values have not been + * tuned!!! + * + * SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(118+2)=400 KHz + */ + +#define SDIO_INIT_CLKDIV (118 << SDIO_CLKCR_CLKDIV_SHIFT) + +/* DMA ON: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(1+2)=16 MHz + * DMA OFF: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(2+2)=12 MHz + */ + +#ifdef CONFIG_SDIO_DMA +# define SDIO_MMCXFR_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT) +#else +# define SDIO_MMCXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT) +#endif + +/* DMA ON: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(1+2)=16 MHz + * DMA OFF: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(2+2)=12 MHz + */ + +#ifdef CONFIG_SDIO_DMA +# define SDIO_SDXFR_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT) +#else +# define SDIO_SDXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT) +#endif + +/* dma 2, stream 6, channel 4 */ + +#define DMAMAP_SDIO DMAMAP_SDIO_2 + +#endif /* __BOARDS_ARM_STM32_AXOLOTI_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32f4/axoloti/scripts/Make.defs b/boards/arm/stm32f4/axoloti/scripts/Make.defs new file mode 100644 index 0000000000000..9f486f1452db0 --- /dev/null +++ b/boards/arm/stm32f4/axoloti/scripts/Make.defs @@ -0,0 +1,41 @@ +############################################################################ +# boards/arm/stm32f4/axoloti/scripts/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/.config +include $(TOPDIR)/tools/Config.mk +include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs + +LDSCRIPT = ld.script +ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) + +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32f4/axoloti/scripts/kernel-space.ld b/boards/arm/stm32f4/axoloti/scripts/kernel-space.ld new file mode 100644 index 0000000000000..f87d33f4f4417 --- /dev/null +++ b/boards/arm/stm32f4/axoloti/scripts/kernel-space.ld @@ -0,0 +1,100 @@ +/**************************************************************************** + * boards/arm/stm32f4/axoloti/scripts/kernel-space.ld + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* NOTE: This depends on the memory.ld script having been included prior to + * this script. + */ + +OUTPUT_ARCH(arm) +EXTERN(_vectors) +ENTRY(_stext) +SECTIONS +{ + .text : { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > kflash + + .init_section : { + _sinit = ABSOLUTE(.); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) + _einit = ABSOLUTE(.); + } > kflash + + .ARM.extab : { + *(.ARM.extab*) + } > kflash + + __exidx_start = ABSOLUTE(.); + .ARM.exidx : { + *(.ARM.exidx*) + } > kflash + + __exidx_end = ABSOLUTE(.); + + _eronly = ABSOLUTE(.); + + .data : { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > ksram AT > kflash + + .bss : { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(8); + _ebss = ABSOLUTE(.); + } > ksram + + /* Stabs debugging sections */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/stm32f4/axoloti/scripts/ld.script b/boards/arm/stm32f4/axoloti/scripts/ld.script new file mode 100644 index 0000000000000..72142ae7d5a12 --- /dev/null +++ b/boards/arm/stm32f4/axoloti/scripts/ld.script @@ -0,0 +1,132 @@ +/**************************************************************************** + * boards/arm/stm32f4/axoloti/scripts/ld.script + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* The STM32F427IGH6 has 1024KiB of FLASH beginning at address 0x0800:0000 and + * 256KiB of SRAM. SRAM is split up into four blocks: + * + * 1) 112KiB of SRAM beginning at address 0x2000:0000 + * 2) 16KiB of SRAM beginning at address 0x2001:c000 + * 3) 64KiB of SRAM beginning at address 0x2002:0000 + * 4) 64KiB of CCM SRAM beginning at address 0x1000:0000 + * + * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 + * where the code expects to begin execution by jumping to the entry point in + * the 0x0800:0000 address + * range. + */ + +MEMORY +{ + flash (rx) : ORIGIN = 0x08000000, LENGTH = 1024K + sram (rwx) : ORIGIN = 0x20000000, LENGTH = 112K +} + +OUTPUT_ARCH(arm) +EXTERN(_vectors) +ENTRY(_stext) +SECTIONS +{ + .text : { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > flash + + .init_section : { + _sinit = ABSOLUTE(.); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) + _einit = ABSOLUTE(.); + } > flash + + .ARM.extab : { + *(.ARM.extab*) + } > flash + + __exidx_start = ABSOLUTE(.); + .ARM.exidx : { + *(.ARM.exidx*) + } > flash + __exidx_end = ABSOLUTE(.); + + .tdata : { + _stdata = ABSOLUTE(.); + *(.tdata .tdata.* .gnu.linkonce.td.*); + _etdata = ABSOLUTE(.); + } > flash + + .tbss : { + _stbss = ABSOLUTE(.); + *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); + _etbss = ABSOLUTE(.); + } > flash + + _eronly = ABSOLUTE(.); + + /* The RAM vector table (if present) should lie at the beginning of SRAM */ + + .ram_vectors : { + *(.ram_vectors) + } > sram + + .data : { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > sram AT > flash + + .bss : { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + _ebss = ABSOLUTE(.); + } > sram + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/stm32f4/axoloti/scripts/memory.ld b/boards/arm/stm32f4/axoloti/scripts/memory.ld new file mode 100644 index 0000000000000..a168b907bc879 --- /dev/null +++ b/boards/arm/stm32f4/axoloti/scripts/memory.ld @@ -0,0 +1,88 @@ +/**************************************************************************** + * boards/arm/stm32f4/axoloti/scripts/memory.ld + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* The STM32F427IGH6 has 1024KiB of FLASH beginning at address 0x0800:0000 and + * 256KiB of SRAM. SRAM is split up into four blocks: + * + * 1) 112KiB of SRAM beginning at address 0x2000:0000 + * 2) 16KiB of SRAM beginning at address 0x2001:c000 + * 3) 64KiB of SRAM beginning at address 0x2002:0000 + * 4) 64KiB of CCM SRAM beginning at address 0x1000:0000 + * + * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 + * where the code expects to begin execution by jumping to the entry point in + * the 0x0800:0000 address range. + * + * For MPU support, the kernel-mode NuttX section is assumed to be 128Kb of + * FLASH and 4Kb of SRAM. That is an excessive amount for the kernel which + * should fit into 64KB and, of course, can be optimized as needed (See + * also boards/arm/stm32f4/axoloti/scripts/kernel-space.ld). Allowing the + * additional does permit addition debug instrumentation to be added to the + * kernel space without overflowing the partition. + * + * Alignment of the user space FLASH partition is also a critical factor: + * The user space FLASH partition will be spanned with a single region of + * size 2**n bytes. The alignment of the user-space region must be the same. + * As a consequence, as the user-space increases in size, the alignment + * requirement also increases. + * + * This alignment requirement means that the largest user space FLASH region + * you can have will be 512KB at it would have to be positioned at + * 0x08800000. If you change this address, don't forget to change the + * CONFIG_NUTTX_USERSPACE configuration setting to match and to modify + * the check in kernel/userspace.c. + * + * For the same reasons, the maximum size of the SRAM mapping is limited to + * 4KB. Both of these alignment limitations could be reduced by using + * multiple regions to map the FLASH/SDRAM range or perhaps with some + * clever use of subregions. + * + * A detailed memory map for the 112KB SRAM region is as follows: + * + * 0x20000 0000: Kernel .data region. Typical size: 0.1KB + * ------- ---- Kernel .bss region. Typical size: 1.8KB + * 0x20000 0800: Kernel IDLE thread stack (approximate). Size is + * determined by CONFIG_IDLETHREAD_STACKSIZE and + * adjustments for alignment. Typical is 1KB. + * ------- ---- Padded to 4KB + * 0x20000 1000: User .data region. Size is variable. + * ------- ---- User .bss region Size is variable. + * 0x20000 2000: Beginning of kernel heap. Size determined by + * CONFIG_MM_KERNEL_HEAPSIZE. + * ------- ---- Beginning of user heap. Can vary with other settings. + * 0x20001 c000: End+1 of CPU RAM + */ + +MEMORY +{ + /* 1024Kb FLASH */ + + kflash (rx) : ORIGIN = 0x08000000, LENGTH = 128K + uflash (rx) : ORIGIN = 0x08020000, LENGTH = 128K + xflash (rx) : ORIGIN = 0x08040000, LENGTH = 768K + + /* 112Kb of contiguous SRAM */ + + ksram (rwx) : ORIGIN = 0x20000000, LENGTH = 4K + usram (rwx) : ORIGIN = 0x20001000, LENGTH = 4K + xsram (rwx) : ORIGIN = 0x20002000, LENGTH = 104K +} diff --git a/boards/arm/stm32f4/axoloti/scripts/user-space.ld b/boards/arm/stm32f4/axoloti/scripts/user-space.ld new file mode 100644 index 0000000000000..c5b08c5f8471b --- /dev/null +++ b/boards/arm/stm32f4/axoloti/scripts/user-space.ld @@ -0,0 +1,114 @@ +/**************************************************************************** + * boards/arm/stm32f4/axoloti/scripts/user-space.ld + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* NOTE: This depends on the memory.ld script having been included prior to + * this script. + */ + +/* Make sure that the critical memory management functions are in user-space. + * the user heap memory manager will reside in user-space but be usable both + * by kernel- and user-space code + */ + +EXTERN(umm_initialize) +EXTERN(umm_addregion) + +EXTERN(malloc) +EXTERN(realloc) +EXTERN(zalloc) +EXTERN(free) + +OUTPUT_ARCH(arm) +SECTIONS +{ + .userspace : { + *(.userspace) + } > uflash + + .text : { + _stext = ABSOLUTE(.); + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > uflash + + .init_section : { + _sinit = ABSOLUTE(.); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) + _einit = ABSOLUTE(.); + } > uflash + + .ARM.extab : { + *(.ARM.extab*) + } > uflash + + __exidx_start = ABSOLUTE(.); + .ARM.exidx : { + *(.ARM.exidx*) + } > uflash + + __exidx_end = ABSOLUTE(.); + + _eronly = ABSOLUTE(.); + + .data : { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > usram AT > uflash + + .bss : { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(8); + _ebss = ABSOLUTE(.); + } > usram + + /* Stabs debugging sections */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/stm32f4/axoloti/src/CMakeLists.txt b/boards/arm/stm32f4/axoloti/src/CMakeLists.txt new file mode 100644 index 0000000000000..e1eb12177d57a --- /dev/null +++ b/boards/arm/stm32f4/axoloti/src/CMakeLists.txt @@ -0,0 +1,53 @@ +# ############################################################################## +# boards/arm/stm32f4/axoloti/src/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(SRCS stm32_boot.c stm32_bringup.c) + +if(CONFIG_STM32_FMC) + list(APPEND SRCS stm32_extmem.c) +endif() + +if(CONFIG_ARCH_LEDS) + list(APPEND SRCS stm32_autoleds.c) +else() + list(APPEND SRCS stm32_userleds.c) +endif() + +if(CONFIG_AUDIO_ADAU1961) + list(APPEND SRCS stm32_adau1961.c) +endif() + +if(CONFIG_ARCH_BUTTONS) + list(APPEND SRCS stm32_buttons.c) +endif() + +if(CONFIG_STM32_SDIO) + list(APPEND SRCS stm32_sdio.c) +endif() + +if(CONFIG_USBHOST) + list(APPEND SRCS stm32_usbhost.c) +endif() + +target_sources(board PRIVATE ${SRCS}) + +set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/ld.script") diff --git a/boards/arm/stm32f4/axoloti/src/Make.defs b/boards/arm/stm32f4/axoloti/src/Make.defs new file mode 100644 index 0000000000000..69fd26fb33db0 --- /dev/null +++ b/boards/arm/stm32f4/axoloti/src/Make.defs @@ -0,0 +1,55 @@ +############################################################################ +# boards/arm/stm32f4/axoloti/src/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +CSRCS = stm32_boot.c stm32_bringup.c + +ifeq ($(CONFIG_STM32_FMC),y) +CSRCS += stm32_extmem.c +endif + +ifeq ($(CONFIG_ARCH_LEDS),y) +CSRCS += stm32_autoleds.c +else +CSRCS += stm32_userleds.c +endif + +ifeq ($(CONFIG_AUDIO_ADAU1961),y) +CSRCS += stm32_adau1961.c +endif + +ifeq ($(CONFIG_ARCH_BUTTONS),y) +CSRCS += stm32_buttons.c +endif + +ifeq ($(CONFIG_STM32_SDIO),y) +CSRCS += stm32_sdio.c +endif + +ifeq ($(CONFIG_USBHOST),y) +CSRCS += stm32_usbhost.c +endif + +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/axoloti/src/axoloti.h b/boards/arm/stm32f4/axoloti/src/axoloti.h similarity index 99% rename from boards/arm/stm32/axoloti/src/axoloti.h rename to boards/arm/stm32f4/axoloti/src/axoloti.h index d6a2c7ac57707..2554ef11df13c 100644 --- a/boards/arm/stm32/axoloti/src/axoloti.h +++ b/boards/arm/stm32f4/axoloti/src/axoloti.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/axoloti/src/axoloti.h + * boards/arm/stm32f4/axoloti/src/axoloti.h * * SPDX-License-Identifier: Apache-2.0 * @@ -30,7 +30,7 @@ #include #include #include -#include +#include /**************************************************************************** * Pre-processor Definitions diff --git a/boards/arm/stm32/axoloti/src/stm32_adau1961.c b/boards/arm/stm32f4/axoloti/src/stm32_adau1961.c similarity index 99% rename from boards/arm/stm32/axoloti/src/stm32_adau1961.c rename to boards/arm/stm32f4/axoloti/src/stm32_adau1961.c index 1d3851ba296a4..30fbef9abdd3f 100644 --- a/boards/arm/stm32/axoloti/src/stm32_adau1961.c +++ b/boards/arm/stm32f4/axoloti/src/stm32_adau1961.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/axoloti/src/stm32_adau1961.c + * boards/arm/stm32f4/axoloti/src/stm32_adau1961.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f4/axoloti/src/stm32_boot.c b/boards/arm/stm32f4/axoloti/src/stm32_boot.c new file mode 100644 index 0000000000000..2eb3a1596fb26 --- /dev/null +++ b/boards/arm/stm32f4/axoloti/src/stm32_boot.c @@ -0,0 +1,89 @@ +/**************************************************************************** + * boards/arm/stm32f4/axoloti/src/stm32_boot.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include +#include + +#include "arm_internal.h" +#include "nvic.h" +#include "itm.h" + +#include "stm32.h" +#include "axoloti.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_boardinitialize + * + * Description: + * All STM32 architectures must provide the following entry point. This + * entry point is called early in the initialization -- after all memory + * has been configured and mapped but before any devices have been + * initialized. + * + ****************************************************************************/ + +void stm32_boardinitialize(void) +{ +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || \ + defined(CONFIG_STM32_SPI3) + stm32_spidev_initialize(); +#endif + +#if defined(CONFIG_STM32_OTGHS) || defined(CONFIG_STM32_OTGFS) + stm32_usbinitialize(); +#endif +} + +/**************************************************************************** + * Name: board_late_initialize + * + * Description: + * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_late_initialize(). board_late_initialize() will + * be called immediately after up_initialize() is called and just before + * the initial application is started. This additional initialization + * phase may be used, for example, to initialize board-specific device + * drivers. + * + ****************************************************************************/ + +#ifdef CONFIG_BOARD_LATE_INITIALIZE +void board_late_initialize(void) +{ + /* Perform board-specific initialization */ + + stm32_bringup(); +} +#endif diff --git a/boards/arm/stm32f4/axoloti/src/stm32_bringup.c b/boards/arm/stm32f4/axoloti/src/stm32_bringup.c new file mode 100644 index 0000000000000..f110e09055822 --- /dev/null +++ b/boards/arm/stm32f4/axoloti/src/stm32_bringup.c @@ -0,0 +1,176 @@ +/**************************************************************************** + * boards/arm/stm32f4/axoloti/src/stm32_bringup.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include + +#ifdef CONFIG_USBMONITOR +# include +#endif + +#include "stm32.h" + +#ifdef CONFIG_STM32_OTGHS +# include "stm32_usbhost.h" +#endif + +#ifdef CONFIG_INPUT_BUTTONS +# include +#endif + +#ifdef CONFIG_USERLED +# include +#endif + +#include "axoloti.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_bringup + * + * Description: + * Perform architecture-specific initialization + * + * CONFIG_BOARD_LATE_INITIALIZE=y : + * Called from board_late_initialize(). + * + ****************************************************************************/ + +int stm32_bringup(void) +{ +#ifdef HAVE_RTC_DRIVER + struct rtc_lowerhalf_s *lower; +#endif + int ret = OK; + +#ifdef HAVE_SDRAM + /* Initialize access to the SDRAM device */ + + ret = stm32_sdram_initialize(); + if (ret != OK) + { + syslog(LOG_ERR, "stm32_sdram_initialize failed %d\n", ret); + return ret; + } +#endif + +#ifdef HAVE_SDIO + /* Initialize the SDIO block driver */ + + ret = stm32_sdio_initialize(); + if (ret != OK) + { + syslog(LOG_ERR, "stm32_sdio_initialize failed %d\n", ret); + return ret; + } +#endif + +#ifdef HAVE_USBHOST + /* Initialize USB host operation. stm32_usbhost_initialize() starts a + * thread will monitor for USB connection and disconnection events. + */ + + ret = stm32_usbhost_initialize(); + if (ret != OK) + { + syslog(LOG_ERR, "stm32_usbhost_initialize failed %d\n", ret); + return ret; + } +#endif + +#ifdef HAVE_USBMONITOR + /* Start the USB Monitor */ + + ret = usbmonitor_start(); + if (ret != OK) + { + syslog(LOG_ERR, "usbmonitor_start failed %d\n", ret); + return ret; + } +#endif + +#ifdef CONFIG_INPUT_BUTTONS + /* Register the BUTTON driver */ + + ret = btn_lower_initialize("/dev/buttons"); + if (ret < 0) + { + syslog(LOG_ERR, "btn_lower_initialize failed %d\n", ret); + } +#endif + +#ifdef CONFIG_INPUT_REI2C + /* Register the rei2c driver */ + + ret = rei2c_initialize("/dev/re0"); + if (ret < 0) + { + syslog(LOG_ERR, "rei2c_initialize failed %d\n", ret); + } +#endif + +#ifdef CONFIG_USERLED + /* Register the LED driver */ + + ret = userled_lower_initialize("/dev/userleds"); + if (ret < 0) + { + syslog(LOG_ERR, "userled_lower_initialize failed %d\n", ret); + } +#endif + +#ifdef HAVE_ADAU1961 + /* Configure ADAU1961 audio */ + + ret = stm32_adau1961_initialize(1); + if (ret != OK) + { + syslog(LOG_ERR, "stm32_adau1961_initialize failed %d\n", ret); + } +#endif + +#ifdef CONFIG_FS_PROCFS + /* Mount the procfs file system */ + + ret = nx_mount(NULL, STM32_PROCFS_MOUNTPOINT, "procfs", 0, NULL); + if (ret < 0) + { + syslog(LOG_ERR, "failed to mount procfs at %s %d\n", + STM32_PROCFS_MOUNTPOINT, ret); + } +#endif + + return ret; +} diff --git a/boards/arm/stm32f4/axoloti/src/stm32_buttons.c b/boards/arm/stm32f4/axoloti/src/stm32_buttons.c new file mode 100644 index 0000000000000..5ec7863e74cdf --- /dev/null +++ b/boards/arm/stm32f4/axoloti/src/stm32_buttons.c @@ -0,0 +1,151 @@ +/**************************************************************************** + * boards/arm/stm32f4/axoloti/src/stm32_buttons.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include +#include + +#include "stm32.h" +#include "axoloti.h" + +#ifdef CONFIG_ARCH_BUTTONS + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* Pin configuration for each axoloti button. This array is indexed by + * the BUTTON_* definitions in board.h + */ + +static const uint32_t g_buttons[NUM_BUTTONS] = +{ + GPIO_BTN_USER, +}; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_button_initialize + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. + * + ****************************************************************************/ + +uint32_t board_button_initialize(void) +{ + int i; + + /* Configure the GPIO pins as inputs. + * EXTI interrupts are configured for all pins. + */ + + for (i = 0; i < NUM_BUTTONS; i++) + { + stm32_configgpio(g_buttons[i]); + } + + return NUM_BUTTONS; +} + +/**************************************************************************** + * Name: board_buttons + ****************************************************************************/ + +uint32_t board_buttons(void) +{ + uint32_t ret = 0; + int i; + + /* Check that state of each key */ + + for (i = 0; i < NUM_BUTTONS; i++) + { + /* A HI value means that the key is pressed. */ + + bool pressed = stm32_gpioread(g_buttons[i]); + + /* Accumulate the set of depressed (not released) keys */ + + if (pressed) + { + ret |= (1 << i); + } + } + + return ret; +} + +/**************************************************************************** + * Button support. + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. + * + * After board_button_initialize() has been called, board_buttons() may be + * called to collect the state of all buttons. board_buttons() returns an + * 32-bit bit set with each bit associated with a button. See the + * BUTTON_*_BIT definitions in board.h for the meaning of each bit. + * + * board_button_irq() may be called to register an interrupt handler that + * will be called when a button is depressed or released. The ID value is + * a button enumeration value that uniquely identifies a button resource. + * See the BUTTON_* definitions in board.h for the meaning of enumeration + * value. + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_IRQBUTTONS +int board_button_irq(int id, xcpt_t irqhandler, void *arg) +{ + int ret = -EINVAL; + + /* The following should be atomic */ + + if (id >= MIN_IRQBUTTON && id <= MAX_IRQBUTTON) + { + ret = + stm32_gpiosetevent(g_buttons[id], true, true, true, irqhandler, arg); + } + + return ret; +} +#endif +#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/stm32f4/axoloti/src/stm32_extmem.c b/boards/arm/stm32f4/axoloti/src/stm32_extmem.c new file mode 100644 index 0000000000000..496b14c757d89 --- /dev/null +++ b/boards/arm/stm32f4/axoloti/src/stm32_extmem.c @@ -0,0 +1,310 @@ +/**************************************************************************** + * boards/arm/stm32f4/axoloti/src/stm32_extmem.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32.h" +#include "axoloti.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifndef CONFIG_STM32_FMC +#warning "FMC is not enabled" +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* Axoloti SDRAM GPIO configuration */ + +static const uint32_t g_sdram_config[] = +{ + /* Data lines */ + + GPIO_FMC_D0, GPIO_FMC_D1, GPIO_FMC_D2, GPIO_FMC_D3, + GPIO_FMC_D4, GPIO_FMC_D5, GPIO_FMC_D6, GPIO_FMC_D7, + GPIO_FMC_D8, GPIO_FMC_D9, GPIO_FMC_D10, GPIO_FMC_D11, + GPIO_FMC_D12, GPIO_FMC_D13, GPIO_FMC_D14, GPIO_FMC_D15, + + /* Address lines */ + + GPIO_FMC_A0, GPIO_FMC_A1, GPIO_FMC_A2, GPIO_FMC_A3, + GPIO_FMC_A4, GPIO_FMC_A5, GPIO_FMC_A6, GPIO_FMC_A7, + GPIO_FMC_A8, GPIO_FMC_A9, GPIO_FMC_A10, GPIO_FMC_A11, + GPIO_FMC_A12, + + /* Control lines */ + + GPIO_FMC_BA0, /* ba0 */ + GPIO_FMC_BA1, /* ba1 */ + GPIO_FMC_NBL0, /* ldqm */ + GPIO_FMC_NBL1, /* udqm */ + GPIO_FMC_SDCLK, /* clk */ + GPIO_FMC_SDCKE0_1, /* cke */ + GPIO_FMC_SDNWE_2, /* we */ + GPIO_FMC_SDNCAS, /* cas */ + GPIO_FMC_SDNRAS, /* ras */ + GPIO_FMC_SDNE0_1, /* cs0 */ + GPIO_FMC_SDNE1_2, /* cs1 */ +}; + +#define NUM_SDRAM_GPIOS (sizeof(g_sdram_config) / sizeof(uint32_t)) + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_sdram_memtest + * + * Description: + * Test the SDRAM. + * + ****************************************************************************/ + +#define RAND_A 22695477 +#define RAND_C 1 +#define TEST_ITERATIONS 16 + +int stm32_sdram_memtest(void *base, uint32_t size) +{ + volatile int iter; + volatile int i; + + /* Linear write with linear congruential generator values */ + + for (iter = 0; iter < TEST_ITERATIONS; iter++) + { + uint32_t x = iter; + + /* Write */ + + for (i = 0; i < size / 4; i++) + { + x = (RAND_A * x) + RAND_C; + ((volatile uint32_t *)base)[i] = x; + } + + /* Read/verify */ + + x = iter; + for (i = 0; i < size / 4; i++) + { + x = (RAND_A * x) + RAND_C; + if (((volatile uint32_t *)base)[i] != x) + { + return -1; + } + } + } + + /* Scattered byte write at linear congruential generator addresses */ + + for (iter = 0; iter < TEST_ITERATIONS; iter++) + { + uint32_t x = iter; + + /* Write */ + + for (i = 0; i < 1024 * 1024; i++) + { + x = (RAND_A * x) + RAND_C; + ((volatile uint8_t *)base)[x & (size - 1)] = (uint8_t) i; + } + + /* Read/verify */ + + x = iter; + for (i = 0; i < 1024 * 1024; i++) + { + x = (RAND_A * x) + RAND_C; + if (((volatile uint8_t *)base)[x & (size - 1)] != (uint8_t) i) + { + return -1; + } + } + } + + return OK; +} + +/**************************************************************************** + * Name: stm32_sdram_initialize + * + * Description: + * Called from stm32_bringup to initialize external SDRAM access. + * The Axoloti uses an Alliance Memory AS4C4M16SA SDRAM. + * + ****************************************************************************/ + +int stm32_sdram_initialize(void) +{ + uint32_t val; + int i; + + /* Configure SDRAM GPIOs */ + + for (i = 0; i < NUM_SDRAM_GPIOS; i++) + { + stm32_configgpio(g_sdram_config[i]); + } + + /* Enable the FMC */ + + stm32_fmc_enable(); + + /* Go through the SDRAM initialization steps per the reference manual. + * The sdclk period is set to 2 x hclk. That is: 168 /2 = 84 MHz + * This gives a clock period of about 11.9 ns + */ + + /* Step 1: + * Program the memory device features into the FMC_SDCRx register. The + * SDRAM clock frequency, RBURST and RPIPE must be programmed in the + * FMC_SDCR1 register. + */ + + val = FMC_SDCR_RPIPE_1 | /* rpipe = 1 hclk */ + FMC_SDCR_READBURST | /* read burst enabled */ + FMC_SDCR_SDCLK_2X | /* sdclk = 2 hclk */ + FMC_SDCR_CAS_LATENCY_2 | /* cas latency = 2 cycles */ + FMC_SDCR_NBANKS_4 | /* 4 internal banks */ + FMC_SDCR_WIDTH_16 | /* width = 16 bits */ + FMC_SDCR_ROWS_12 | /* numrows = 12 */ + FMC_SDCR_COLS_8; /* numcols = 8 bits */ + stm32_fmc_sdram_set_control(1, val); + + /* Step 2: + * Program the memory device timing into the FMC_SDTRx register. The + * TRP and TRC timings must be programmed in the FMC_SDTR1 register. + */ + + val = FMC_SDTR_TRCD(2) | /* ras to cas delay 21ns => 2x11.90ns */ + FMC_SDTR_TRP(2) | /* row precharge 21ns => 2x11.90ns */ + FMC_SDTR_TRC(6) | /* row cycle time 63ns => 6x11.9ns */ + FMC_SDTR_TRAS(4) | /* row active time 42ns = >4x11.9ns */ + FMC_SDTR_TWR(4) | /* write to precharge 42ns => 4x11.9ns */ + FMC_SDTR_TXSR(6) | /* exit self refresh 65ns => 6x11.9ns */ + FMC_SDTR_TMRD(2); /* load mode register to active 2 clks */ + stm32_fmc_sdram_set_timing(1, val); + + /* Step 3: + * Set MODE bits to ‘001’ and configure the Target Bank bits (CTB1 + * and/or CTB2) in the FMC_SDCMR register to start delivering the clock + * to the memory (SDCKE is driven high). + */ + + val = FMC_SDCMR_BANK_1 | FMC_SDCMR_CMD_CLK_ENABLE; + stm32_fmc_sdram_command(val); + + /* Step 4: + * Wait during the prescribed delay period. Typical delay is around 100 + * μs (refer to the SDRAM datasheet for the required delay after + * power-up). + */ + + nxsched_usleep(1000); + + /* Step 5: + * Set MODE bits to ‘010’ and configure the Target Bank bits (CTB1 + * and/or CTB2) in the FMC_SDCMR register to issue a “Precharge All” + * command. + */ + + val = FMC_SDCMR_BANK_1 | FMC_SDCMR_CMD_PALL; + stm32_fmc_sdram_command(val); + + /* Step 6: + * Set MODE bits to ‘011’, and configure the Target Bank bits (CTB1 + * and/or CTB2) as well as the number of consecutive Auto-refresh + * commands (NRFS) in the FMC_SDCMR register. Refer to the SDRAM + * datasheet for the number of Auto-refresh commands that should be + * issued. Typical number is 8. + */ + + val = FMC_SDCMR_NRFS(5) | FMC_SDCMR_BANK_1 | FMC_SDCMR_CMD_AUTO_REFRESH; + stm32_fmc_sdram_command(val); + + /* Step 7: + * Configure the MRD field according to your SDRAM device, set the MODE + * bits to '100', and configure the Target Bank bits (CTB1 and/or CTB2) + * in the FMC_SDCMR register to issue a "Load Mode Register" command in + * order to program the SDRAM. In particular: + * a) The CAS latency must be selected following configured value in + * FMC_SDCR1/2 registers + * b) The Burst Length (BL) of 1 must be selected by configuring the + * M[2:0] bits to 000 in the mode register (refer to the SDRAM + * datasheet). If the Mode Register is not the same for both SDRAM + * banks, this step has to be repeated twice, once for each bank, + * and the Target Bank bits set accordingly. + */ + + val = FMC_SDCMR_MDR_BURST_LENGTH_2 | + FMC_SDCMR_MDR_BURST_TYPE_SEQUENTIAL | + FMC_SDCMR_MDR_CAS_LATENCY_2 | + FMC_SDCMR_MDR_MODE_NORMAL | + FMC_SDCMR_MDR_WBL_SINGLE | FMC_SDCMR_BANK_1 | FMC_SDCMR_CMD_LOAD_MODE; + stm32_fmc_sdram_command(val); + + /* Step 8: + * Program the refresh rate in the FMC_SDRTR register + * The refresh rate corresponds to the delay between refresh cycles. Its + * value must be adapted to SDRAM devices. + */ + + stm32_fmc_sdram_set_refresh_rate(1292); /* (64ms/4096rows) x 84MHz) - 20 */ + + /* Step 9: + * For mobile SDRAM devices, to program the extended mode register it + * should be done once the SDRAM device is initialized: First, a dummy + * read access should be performed while BA1=1 and BA=0 (refer to SDRAM + * address mapping section for BA[1:0] address mapping) in order to select + * the extended mode register instead of Load mode register and then + * program the needed value. + */ + + /* Setting EMRS is optional and we're not bothering ... */ + + /* Enable memory writes for bank 1 */ + + stm32_fmc_sdram_write_protect(1, false); + + /* Wait for the controller to be ready */ + + stm32_fmc_sdram_wait(); + return OK; +} diff --git a/boards/arm/stm32f4/axoloti/src/stm32_sdio.c b/boards/arm/stm32f4/axoloti/src/stm32_sdio.c new file mode 100644 index 0000000000000..35236a2039c14 --- /dev/null +++ b/boards/arm/stm32f4/axoloti/src/stm32_sdio.c @@ -0,0 +1,156 @@ +/**************************************************************************** + * boards/arm/stm32f4/axoloti/src/stm32_sdio.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include + +#include "stm32.h" +#include "axoloti.h" + +#ifdef HAVE_SDIO + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Card detections requires card support and a card detection GPIO */ + +#define HAVE_NCD 1 +#if !defined(HAVE_SDIO) || !defined(GPIO_SDIO_NCD) +#undef HAVE_NCD +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static struct sdio_dev_s *g_sdio_dev; +#ifdef HAVE_NCD +static bool g_sd_inserted; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_ncd_interrupt + * + * Description: + * Card detect interrupt handler. + * + ****************************************************************************/ + +#ifdef HAVE_NCD +static int stm32_ncd_interrupt(int irq, void *context, void *arg) +{ + bool present; + + present = !stm32_gpioread(GPIO_SDIO_NCD); + if (present != g_sd_inserted) + { + sdio_mediachange(g_sdio_dev, present); + g_sd_inserted = present; + } + + return OK; +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_sdio_initialize + * + * Description: + * Initialize SDIO-based MMC/SD card support + * + ****************************************************************************/ + +int stm32_sdio_initialize(void) +{ + int ret; + +#ifdef HAVE_NCD + /* Configure the card detect GPIO */ + + stm32_configgpio(GPIO_SDIO_NCD); + + /* Register an interrupt handler for the card detect pin */ + + stm32_gpiosetevent(GPIO_SDIO_NCD, true, true, true, + stm32_ncd_interrupt, NULL); +#endif + + /* Mount the SDIO-based MMC/SD block driver. + * First, get an instance of the SDIO interface + */ + + finfo("Initializing SDIO slot %d\n", SDIO_SLOTNO); + g_sdio_dev = sdio_initialize(SDIO_SLOTNO); + if (!g_sdio_dev) + { + ferr("ERROR: Failed to initialize SDIO slot %d\n", SDIO_SLOTNO); + return -ENODEV; + } + + /* Now bind the SDIO interface to the MMC/SD driver */ + + finfo("Bind SDIO to the MMC/SD driver, minor=%d\n", SDIO_MINOR); + ret = mmcsd_slotinitialize(SDIO_MINOR, g_sdio_dev); + if (ret != OK) + { + ferr("ERROR: Failed to bind SDIO to the MMC/SD driver: %d\n", ret); + return ret; + } + + finfo("Successfully bound SDIO to the MMC/SD driver\n"); + +#ifdef HAVE_NCD + /* Use SD card detect pin to check if a card is g_sd_inserted */ + + g_sd_inserted = !stm32_gpioread(GPIO_SDIO_NCD); + finfo("Card detect : %d\n", g_sd_inserted); + sdio_mediachange(g_sdio_dev, g_sd_inserted); +#else + /* Assume that the SD card is inserted. What choice do we have? */ + + sdio_mediachange(g_sdio_dev, true); +#endif + + return OK; +} + +#endif /* HAVE_SDIO */ diff --git a/boards/arm/stm32f4/axoloti/src/stm32_usbhost.c b/boards/arm/stm32f4/axoloti/src/stm32_usbhost.c new file mode 100644 index 0000000000000..94aed1ef76b3b --- /dev/null +++ b/boards/arm/stm32f4/axoloti/src/stm32_usbhost.c @@ -0,0 +1,265 @@ +/**************************************************************************** + * boards/arm/stm32f4/axoloti/src/stm32_usbhost.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include "arm_internal.h" +#include "stm32.h" +#include "stm32_otghs.h" +#include "axoloti.h" + +#ifdef CONFIG_STM32_OTGHS + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#if defined(CONFIG_USBDEV) || defined(CONFIG_USBHOST) +#define HAVE_USB 1 +#else +#warning "CONFIG_STM32_OTGHS is enabled but neither CONFIG_USBDEV nor CONFIG_USBHOST" +#undef HAVE_USB +#endif + +#ifndef CONFIG_AXOLOTI_USBHOST_PRIO +#define CONFIG_AXOLOTI_USBHOST_PRIO 100 +#endif + +#ifndef CONFIG_AXOLOTI_USBHOST_STACKSIZE +#define CONFIG_AXOLOTI_USBHOST_STACKSIZE 1024 +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +static struct usbhost_connection_s *g_usbconn; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: usbhost_waiter + * + * Description: + * Wait for USB devices to be connected. + * + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +static int usbhost_waiter(int argc, char *argv[]) +{ + struct usbhost_hubport_s *hport; + uinfo("Running\n"); + + for (; ; ) + { + /* Wait for the device to change state */ + + DEBUGVERIFY(CONN_WAIT(g_usbconn, &hport)); + uinfo("%s\n", hport->connected ? "connected" : "disconnected"); + + /* Did we just become connected? */ + + if (hport->connected) + { + /* Yes.. enumerate the newly connected device */ + + CONN_ENUMERATE(g_usbconn, hport); + } + } + + /* Keep the compiler from complaining */ + + return 0; +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_usbinitialize + * + * Description: + * Called from stm32_usbinitialize very early in initialization to setup + * USB-related GPIO pins for the Axoloti board. + * + ****************************************************************************/ + +void stm32_usbinitialize(void) +{ +#ifdef CONFIG_STM32_OTGHS + stm32_configgpio(GPIO_OTGHS_PWRON); + stm32_configgpio(GPIO_OTGHS_OVER); +#endif +} + +/**************************************************************************** + * Name: stm32_usbhost_vbusdrive + * + * Description: + * Enable/disable driving of VBUS 5V output. This function must be provided + * be each platform that implements the STM32 OTG HS host interface + * + * Input Parameters: + * iface - For future growth to handle multiple USB host interface. Should + * be zero. + * enable - true: enable VBUS power; false: disable VBUS power + * + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +void stm32_usbhost_vbusdrive(int iface, bool enable) +{ + DEBUGASSERT(iface == 0); + if (enable) + { + /* Enable the Power Switch by driving the enable pin low */ + + stm32_gpiowrite(GPIO_OTGHS_PWRON, false); + } + else + { + /* Disable the Power Switch by driving the enable pin high */ + + stm32_gpiowrite(GPIO_OTGHS_PWRON, true); + } +} +#endif + +/**************************************************************************** + * Name: stm32_setup_overcurrent + * + * Description: + * Setup to receive an interrupt-level callback if an overcurrent condition + * is detected. + * + * Input Parameters: + * handler - New overcurrent interrupt handler + * arg - The argument provided for the interrupt handler + * + * Returned Value: + * Zero (OK) is returned on success. Otherwise, a negated errno value is + * returned to indicate the nature of the failure. + * + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +int stm32_setup_overcurrent(xcpt_t handler, void *arg) +{ + return stm32_gpiosetevent(GPIO_OTGHS_OVER, true, true, true, handler, arg); +} +#endif + +/**************************************************************************** + * Name: stm32_usbhost_initialize + * + * Description: + * Called at application startup time to initialize the USB host + * functionality. This function will start a thread that will monitor for + * device connection/disconnection events. + * + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +int stm32_usbhost_initialize(void) +{ + int ret; + + /* First, register all of the class drivers needed to support the drivers + * that we care about: + */ + + uinfo("Register class drivers\n"); + +#ifdef CONFIG_USBHOST_MSC + /* Register the USB mass storage class class */ + + ret = usbhost_msc_initialize(); + if (ret != OK) + { + uerr("ERROR: Failed to register the mass storage class: %d\n", ret); + } +#endif + +#ifdef CONFIG_USBHOST_HIDKBD + /* Initialize the HID keyboard class */ + + ret = usbhost_kbdinit(); + if (ret != OK) + { + uerr("ERROR: Failed to register the HID keyboard class\n"); + } +#endif + +#ifdef CONFIG_USBHOST_HIDMOUSE + /* Initialize the HID mouse class */ + + ret = usbhost_mouse_init(); + if (ret != OK) + { + uerr("ERROR: Failed to register the HID mouse class\n"); + } +#endif + + /* Then get an instance of the USB host interface */ + + uinfo("Initialize USB host\n"); + g_usbconn = stm32_otghshost_initialize(0); + if (g_usbconn) + { + /* Start a thread to handle device connection. */ + + uinfo("Start usbhost_waiter\n"); + ret = kthread_create("usbhost", CONFIG_AXOLOTI_USBHOST_PRIO, + CONFIG_AXOLOTI_USBHOST_STACKSIZE, + usbhost_waiter, NULL); + return ret < 0 ? -ENOEXEC : OK; + } + + return -ENODEV; +} +#endif + +#endif /* CONFIG_STM32_OTGHS */ diff --git a/boards/arm/stm32f4/axoloti/src/stm32_userleds.c b/boards/arm/stm32f4/axoloti/src/stm32_userleds.c new file mode 100644 index 0000000000000..b6825a8b06b2a --- /dev/null +++ b/boards/arm/stm32f4/axoloti/src/stm32_userleds.c @@ -0,0 +1,93 @@ +/**************************************************************************** + * boards/arm/stm32f4/axoloti/src/stm32_userleds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32.h" +#include "axoloti.h" + +#ifndef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* This array maps an LED number to GPIO pin configuration */ + +static uint32_t g_ledcfg[BOARD_NLEDS] = +{ + GPIO_LED1, GPIO_LED2, +}; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_userled_initialize + ****************************************************************************/ + +uint32_t board_userled_initialize(void) +{ + /* Configure LED1-2 GPIOs for output */ + + stm32_configgpio(GPIO_LED1); + stm32_configgpio(GPIO_LED2); + return BOARD_NLEDS; +} + +/**************************************************************************** + * Name: board_userled + ****************************************************************************/ + +void board_userled(int led, bool ledon) +{ + if ((unsigned)led < BOARD_NLEDS) + { + stm32_gpiowrite(g_ledcfg[led], ledon); + } +} + +/**************************************************************************** + * Name: board_userled_all + ****************************************************************************/ + +void board_userled_all(uint32_t ledset) +{ + stm32_gpiowrite(GPIO_LED1, (ledset & BOARD_LED1_BIT) == 0); + stm32_gpiowrite(GPIO_LED2, (ledset & BOARD_LED2_BIT) == 0); +} + +#endif /* !CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32f4/clicker2-stm32/CMakeLists.txt b/boards/arm/stm32f4/clicker2-stm32/CMakeLists.txt new file mode 100644 index 0000000000000..c6fa956e228ba --- /dev/null +++ b/boards/arm/stm32f4/clicker2-stm32/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32f4/clicker2-stm32/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/arm/stm32/clicker2-stm32/Kconfig b/boards/arm/stm32f4/clicker2-stm32/Kconfig similarity index 100% rename from boards/arm/stm32/clicker2-stm32/Kconfig rename to boards/arm/stm32f4/clicker2-stm32/Kconfig diff --git a/boards/arm/stm32f4/clicker2-stm32/configs/knsh/defconfig b/boards/arm/stm32f4/clicker2-stm32/configs/knsh/defconfig new file mode 100644 index 0000000000000..3f73f847e27d5 --- /dev/null +++ b/boards/arm/stm32f4/clicker2-stm32/configs/knsh/defconfig @@ -0,0 +1,55 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_SYSTEM_DD is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="clicker2-stm32" +CONFIG_ARCH_BOARD_CLICKER2_STM32=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F407VG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_IRQBUTTONS=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_ARM_MPU=y +CONFIG_BOARDCTL=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILD_PROTECTED=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_NSH_DISABLE_GET=y +CONFIG_NSH_DISABLE_IFUPDOWN=y +CONFIG_NSH_DISABLE_MKRD=y +CONFIG_NSH_DISABLE_PUT=y +CONFIG_NSH_DISABLE_WGET=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_NUTTX_USERSPACE=0x08020000 +CONFIG_PASS1_BUILDIR="boards/arm/stm32f4/clicker2-stm32/kernel" +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=131072 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=192 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=25 +CONFIG_START_MONTH=3 +CONFIG_STM32_CCMEXCLUDE=y +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_PWR=y +CONFIG_STM32_USART3=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=32 +CONFIG_USART3_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f4/clicker2-stm32/configs/mrf24j40-6lowpan/defconfig b/boards/arm/stm32f4/clicker2-stm32/configs/mrf24j40-6lowpan/defconfig new file mode 100644 index 0000000000000..d468e8c135bef --- /dev/null +++ b/boards/arm/stm32f4/clicker2-stm32/configs/mrf24j40-6lowpan/defconfig @@ -0,0 +1,109 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_DEV_CONSOLE is not set +# CONFIG_NET_ETHERNET is not set +# CONFIG_NET_IPv4 is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="clicker2-stm32" +CONFIG_ARCH_BOARD_CLICKER2_STM32=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F407VG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_IRQBUTTONS=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL_USBDEVCTRL=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_CDCACM=y +CONFIG_CDCACM_CONSOLE=y +CONFIG_CDCACM_RXBUFSIZE=256 +CONFIG_CDCACM_TXBUFSIZE=256 +CONFIG_DRIVERS_IEEE802154=y +CONFIG_DRIVERS_WIRELESS=y +CONFIG_EXAMPLES_NETTEST=y +CONFIG_EXAMPLES_NETTEST_DEVNAME="wpan0" +CONFIG_EXAMPLES_NETTEST_SERVERIPv6ADDR_1=0xfe80 +CONFIG_EXAMPLES_NETTEST_SERVERIPv6ADDR_6=0x00ff +CONFIG_EXAMPLES_NETTEST_SERVERIPv6ADDR_7=0xfe00 +CONFIG_EXAMPLES_NETTEST_SERVERIPv6ADDR_8=0x0800 +CONFIG_EXAMPLES_NETTEST_SERVER_PORTNO=61616 +CONFIG_EXAMPLES_NETTEST_TARGET2=y +CONFIG_EXAMPLES_UDP=y +CONFIG_EXAMPLES_UDP_CLIENT_PORTNO=61617 +CONFIG_EXAMPLES_UDP_DEVNAME="wpan0" +CONFIG_EXAMPLES_UDP_SERVERIPv6ADDR_1=0xfe80 +CONFIG_EXAMPLES_UDP_SERVERIPv6ADDR_6=0x00ff +CONFIG_EXAMPLES_UDP_SERVERIPv6ADDR_7=0xfe00 +CONFIG_EXAMPLES_UDP_SERVERIPv6ADDR_8=0x0d00 +CONFIG_EXAMPLES_UDP_SERVER_PORTNO=61616 +CONFIG_EXAMPLES_UDP_TARGET2=y +CONFIG_FAT_LCNAMES=y +CONFIG_FAT_LFN=y +CONFIG_FS_FAT=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_IEEE802154_I8SAK=y +CONFIG_IEEE802154_MAC=y +CONFIG_IEEE802154_MACDEV=y +CONFIG_IEEE802154_MRF24J40=y +CONFIG_IEEE802154_NETDEV=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_IOB_BUFSIZE=128 +CONFIG_IOB_NBUFFERS=32 +CONFIG_IOB_NCHAINS=16 +CONFIG_LIBC_HOSTNAME="MRF24J40" +CONFIG_LINE_MAX=64 +CONFIG_MAC802154_NTXDESC=32 +CONFIG_NET=y +CONFIG_NETDEV_LATEINIT=y +CONFIG_NETDEV_STATISTICS=y +CONFIG_NETDEV_WIRELESS_IOCTL=y +CONFIG_NETINIT_NETLOCAL=y +CONFIG_NETINIT_NOMAC=y +CONFIG_NETUTILS_TELNETD=y +CONFIG_NET_6LOWPAN=y +CONFIG_NET_BROADCAST=y +CONFIG_NET_IPv6=y +CONFIG_NET_SOCKOPTS=y +CONFIG_NET_STATISTICS=y +CONFIG_NET_TCP=y +CONFIG_NET_TCP_WRITE_BUFFERS=y +CONFIG_NET_UDP=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_DISABLE_GET=y +CONFIG_NSH_DISABLE_PUT=y +CONFIG_NSH_DISABLE_WGET=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=131072 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=192 +CONFIG_SCHED_LPWORK=y +CONFIG_SCHED_LPWORKPRIORITY=160 +CONFIG_SCHED_WAITPID=y +CONFIG_START_YEAR=2013 +CONFIG_STM32_CCMEXCLUDE=y +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PWR=y +CONFIG_STM32_USART3=y +CONFIG_SYSTEM_NSH=y +CONFIG_SYSTEM_TELNET_CLIENT=y +CONFIG_TASK_NAME_SIZE=32 +CONFIG_USBDEV=y +CONFIG_WIRELESS=y +CONFIG_WIRELESS_IEEE802154=y diff --git a/boards/arm/stm32f4/clicker2-stm32/configs/mrf24j40-mac/defconfig b/boards/arm/stm32f4/clicker2-stm32/configs/mrf24j40-mac/defconfig new file mode 100644 index 0000000000000..37c9d51ec17c5 --- /dev/null +++ b/boards/arm/stm32f4/clicker2-stm32/configs/mrf24j40-mac/defconfig @@ -0,0 +1,61 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="clicker2-stm32" +CONFIG_ARCH_BOARD_CLICKER2_STM32=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F407VG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_IRQBUTTONS=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_DRIVERS_IEEE802154=y +CONFIG_DRIVERS_WIRELESS=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_IEEE802154_I8SAK=y +CONFIG_IEEE802154_MAC=y +CONFIG_IEEE802154_MACDEV=y +CONFIG_IEEE802154_MRF24J40=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_DISABLE_GET=y +CONFIG_NSH_DISABLE_IFUPDOWN=y +CONFIG_NSH_DISABLE_PUT=y +CONFIG_NSH_DISABLE_WGET=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAMLOG=y +CONFIG_RAMLOG_SYSLOG=y +CONFIG_RAM_SIZE=131072 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=192 +CONFIG_SCHED_LPWORK=y +CONFIG_SCHED_WAITPID=y +CONFIG_START_YEAR=2013 +CONFIG_STM32_CCMEXCLUDE=y +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_PWR=y +CONFIG_STM32_USART3=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=32 +CONFIG_USART3_SERIAL_CONSOLE=y +CONFIG_WIRELESS=y +CONFIG_WIRELESS_IEEE802154=y diff --git a/boards/arm/stm32f4/clicker2-stm32/configs/mrf24j40-starhub/defconfig b/boards/arm/stm32f4/clicker2-stm32/configs/mrf24j40-starhub/defconfig new file mode 100644 index 0000000000000..9906db1241ab4 --- /dev/null +++ b/boards/arm/stm32f4/clicker2-stm32/configs/mrf24j40-starhub/defconfig @@ -0,0 +1,94 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_DEV_CONSOLE is not set +# CONFIG_NET_ETHERNET is not set +# CONFIG_NET_IPv4 is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="clicker2-stm32" +CONFIG_ARCH_BOARD_CLICKER2_STM32=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F407VG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_IRQBUTTONS=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL_USBDEVCTRL=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_CDCACM=y +CONFIG_CDCACM_CONSOLE=y +CONFIG_CDCACM_RXBUFSIZE=256 +CONFIG_CDCACM_TXBUFSIZE=256 +CONFIG_DRIVERS_IEEE802154=y +CONFIG_DRIVERS_WIRELESS=y +CONFIG_FAT_LCNAMES=y +CONFIG_FAT_LFN=y +CONFIG_FS_FAT=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_IEEE802154_I8SAK=y +CONFIG_IEEE802154_MAC=y +CONFIG_IEEE802154_MACDEV=y +CONFIG_IEEE802154_MRF24J40=y +CONFIG_IEEE802154_NETDEV=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_IOB_BUFSIZE=128 +CONFIG_IOB_NBUFFERS=32 +CONFIG_IOB_NCHAINS=16 +CONFIG_LIBC_HOSTNAME="MRF24J40" +CONFIG_LINE_MAX=64 +CONFIG_MAC802154_NTXDESC=32 +CONFIG_NET=y +CONFIG_NETDEV_LATEINIT=y +CONFIG_NETDEV_STATISTICS=y +CONFIG_NETDEV_TELNET=y +CONFIG_NETDEV_WIRELESS_IOCTL=y +CONFIG_NETINIT_NETLOCAL=y +CONFIG_NETINIT_NOMAC=y +CONFIG_NET_6LOWPAN=y +CONFIG_NET_BROADCAST=y +CONFIG_NET_IPv6=y +CONFIG_NET_SOCKOPTS=y +CONFIG_NET_STAR=y +CONFIG_NET_STARHUB=y +CONFIG_NET_STATISTICS=y +CONFIG_NET_TCP=y +CONFIG_NET_TCP_WRITE_BUFFERS=y +CONFIG_NET_UDP=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_DISABLE_GET=y +CONFIG_NSH_DISABLE_PUT=y +CONFIG_NSH_DISABLE_WGET=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=131072 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=192 +CONFIG_SCHED_LPWORK=y +CONFIG_SCHED_LPWORKPRIORITY=160 +CONFIG_SCHED_WAITPID=y +CONFIG_START_YEAR=2013 +CONFIG_STM32_CCMEXCLUDE=y +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PWR=y +CONFIG_STM32_USART3=y +CONFIG_SYSTEM_NSH=y +CONFIG_SYSTEM_TELNET_CLIENT=y +CONFIG_TASK_NAME_SIZE=32 +CONFIG_USBDEV=y +CONFIG_WIRELESS=y +CONFIG_WIRELESS_IEEE802154=y diff --git a/boards/arm/stm32f4/clicker2-stm32/configs/mrf24j40-starpoint/defconfig b/boards/arm/stm32f4/clicker2-stm32/configs/mrf24j40-starpoint/defconfig new file mode 100644 index 0000000000000..6f66c0144f9b1 --- /dev/null +++ b/boards/arm/stm32f4/clicker2-stm32/configs/mrf24j40-starpoint/defconfig @@ -0,0 +1,110 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_DEV_CONSOLE is not set +# CONFIG_NET_ETHERNET is not set +# CONFIG_NET_IPv4 is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="clicker2-stm32" +CONFIG_ARCH_BOARD_CLICKER2_STM32=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F407VG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_IRQBUTTONS=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL_USBDEVCTRL=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_CDCACM=y +CONFIG_CDCACM_CONSOLE=y +CONFIG_CDCACM_RXBUFSIZE=256 +CONFIG_CDCACM_TXBUFSIZE=256 +CONFIG_DRIVERS_IEEE802154=y +CONFIG_DRIVERS_WIRELESS=y +CONFIG_EXAMPLES_NETTEST=y +CONFIG_EXAMPLES_NETTEST_DEVNAME="wpan0" +CONFIG_EXAMPLES_NETTEST_SERVERIPv6ADDR_1=0xfe80 +CONFIG_EXAMPLES_NETTEST_SERVERIPv6ADDR_6=0x00ff +CONFIG_EXAMPLES_NETTEST_SERVERIPv6ADDR_7=0xfe00 +CONFIG_EXAMPLES_NETTEST_SERVERIPv6ADDR_8=0x0800 +CONFIG_EXAMPLES_NETTEST_SERVER_PORTNO=61616 +CONFIG_EXAMPLES_NETTEST_TARGET2=y +CONFIG_EXAMPLES_UDP=y +CONFIG_EXAMPLES_UDP_CLIENT_PORTNO=61617 +CONFIG_EXAMPLES_UDP_DEVNAME="wpan0" +CONFIG_EXAMPLES_UDP_SERVERIPv6ADDR_1=0xfe80 +CONFIG_EXAMPLES_UDP_SERVERIPv6ADDR_6=0x00ff +CONFIG_EXAMPLES_UDP_SERVERIPv6ADDR_7=0xfe00 +CONFIG_EXAMPLES_UDP_SERVERIPv6ADDR_8=0x0d00 +CONFIG_EXAMPLES_UDP_SERVER_PORTNO=61616 +CONFIG_EXAMPLES_UDP_TARGET2=y +CONFIG_FAT_LCNAMES=y +CONFIG_FAT_LFN=y +CONFIG_FS_FAT=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_IEEE802154_I8SAK=y +CONFIG_IEEE802154_MAC=y +CONFIG_IEEE802154_MACDEV=y +CONFIG_IEEE802154_MRF24J40=y +CONFIG_IEEE802154_NETDEV=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_IOB_BUFSIZE=128 +CONFIG_IOB_NBUFFERS=32 +CONFIG_IOB_NCHAINS=16 +CONFIG_LIBC_HOSTNAME="MRF24J40" +CONFIG_LINE_MAX=64 +CONFIG_MAC802154_NTXDESC=32 +CONFIG_NET=y +CONFIG_NETDEV_LATEINIT=y +CONFIG_NETDEV_STATISTICS=y +CONFIG_NETDEV_WIRELESS_IOCTL=y +CONFIG_NETINIT_NETLOCAL=y +CONFIG_NETINIT_NOMAC=y +CONFIG_NETUTILS_TELNETC=y +CONFIG_NETUTILS_TELNETD=y +CONFIG_NET_6LOWPAN=y +CONFIG_NET_BROADCAST=y +CONFIG_NET_IPv6=y +CONFIG_NET_SOCKOPTS=y +CONFIG_NET_STAR=y +CONFIG_NET_STATISTICS=y +CONFIG_NET_TCP=y +CONFIG_NET_TCP_WRITE_BUFFERS=y +CONFIG_NET_UDP=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_DISABLE_GET=y +CONFIG_NSH_DISABLE_PUT=y +CONFIG_NSH_DISABLE_WGET=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=131072 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=192 +CONFIG_SCHED_LPWORK=y +CONFIG_SCHED_LPWORKPRIORITY=160 +CONFIG_SCHED_WAITPID=y +CONFIG_START_YEAR=2013 +CONFIG_STM32_CCMEXCLUDE=y +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PWR=y +CONFIG_STM32_USART3=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=32 +CONFIG_USBDEV=y +CONFIG_WIRELESS=y +CONFIG_WIRELESS_IEEE802154=y diff --git a/boards/arm/stm32f4/clicker2-stm32/configs/nsh/defconfig b/boards/arm/stm32f4/clicker2-stm32/configs/nsh/defconfig new file mode 100644 index 0000000000000..50e12a7f9e480 --- /dev/null +++ b/boards/arm/stm32f4/clicker2-stm32/configs/nsh/defconfig @@ -0,0 +1,50 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="clicker2-stm32" +CONFIG_ARCH_BOARD_CLICKER2_STM32=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F407VG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_IRQBUTTONS=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_DISABLE_GET=y +CONFIG_NSH_DISABLE_IFUPDOWN=y +CONFIG_NSH_DISABLE_PUT=y +CONFIG_NSH_DISABLE_WGET=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=131072 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=192 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=25 +CONFIG_START_MONTH=3 +CONFIG_STM32_CCMEXCLUDE=y +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_PWR=y +CONFIG_STM32_USART3=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=32 +CONFIG_USART3_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f4/clicker2-stm32/configs/usbnsh/defconfig b/boards/arm/stm32f4/clicker2-stm32/configs/usbnsh/defconfig new file mode 100644 index 0000000000000..33748ef3ecab5 --- /dev/null +++ b/boards/arm/stm32f4/clicker2-stm32/configs/usbnsh/defconfig @@ -0,0 +1,64 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_DEV_CONSOLE is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="clicker2-stm32" +CONFIG_ARCH_BOARD_CLICKER2_STM32=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F407VG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_IRQBUTTONS=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL_USBDEVCTRL=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_CDCACM=y +CONFIG_CDCACM_CONSOLE=y +CONFIG_CDCACM_RXBUFSIZE=256 +CONFIG_CDCACM_TXBUFSIZE=256 +CONFIG_FAT_LCNAMES=y +CONFIG_FAT_LFN=y +CONFIG_FS_FAT=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_DISABLE_GET=y +CONFIG_NSH_DISABLE_IFUPDOWN=y +CONFIG_NSH_DISABLE_PUT=y +CONFIG_NSH_DISABLE_WGET=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=131072 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=192 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=25 +CONFIG_START_MONTH=3 +CONFIG_STM32_CCMEXCLUDE=y +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PWR=y +CONFIG_STM32_USART3=y +CONFIG_SYSLOG_CHAR=y +CONFIG_SYSLOG_DEVPATH="/dev/ttyS0" +CONFIG_SYSLOG_INTBUFFER=y +CONFIG_SYSLOG_INTBUFSIZE=396 +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=32 +CONFIG_USBDEV=y diff --git a/boards/arm/stm32f4/clicker2-stm32/configs/xbee-6lowpan/defconfig b/boards/arm/stm32f4/clicker2-stm32/configs/xbee-6lowpan/defconfig new file mode 100644 index 0000000000000..853fec364b7df --- /dev/null +++ b/boards/arm/stm32f4/clicker2-stm32/configs/xbee-6lowpan/defconfig @@ -0,0 +1,105 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_DEV_CONSOLE is not set +# CONFIG_NET_ETHERNET is not set +# CONFIG_NET_IPv4 is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="clicker2-stm32" +CONFIG_ARCH_BOARD_CLICKER2_STM32=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F407VG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_IRQBUTTONS=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL_USBDEVCTRL=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_CDCACM=y +CONFIG_CDCACM_CONSOLE=y +CONFIG_CDCACM_RXBUFSIZE=256 +CONFIG_CDCACM_TXBUFSIZE=256 +CONFIG_CLICKER2_STM32_MB1_XBEE=y +CONFIG_DRIVERS_IEEE802154=y +CONFIG_DRIVERS_WIRELESS=y +CONFIG_EXAMPLES_NETTEST=y +CONFIG_EXAMPLES_NETTEST_DEVNAME="wpan0" +CONFIG_EXAMPLES_NETTEST_SERVERIPv6ADDR_1=0xfe80 +CONFIG_EXAMPLES_NETTEST_SERVERIPv6ADDR_6=0x00ff +CONFIG_EXAMPLES_NETTEST_SERVERIPv6ADDR_7=0xfe00 +CONFIG_EXAMPLES_NETTEST_SERVERIPv6ADDR_8=0x0800 +CONFIG_EXAMPLES_NETTEST_SERVER_PORTNO=61616 +CONFIG_EXAMPLES_NETTEST_TARGET2=y +CONFIG_EXAMPLES_UDP=y +CONFIG_EXAMPLES_UDP_CLIENT_PORTNO=61617 +CONFIG_EXAMPLES_UDP_DEVNAME="wpan0" +CONFIG_EXAMPLES_UDP_SERVERIPv6ADDR_1=0xfe80 +CONFIG_EXAMPLES_UDP_SERVERIPv6ADDR_6=0x00ff +CONFIG_EXAMPLES_UDP_SERVERIPv6ADDR_7=0xfe00 +CONFIG_EXAMPLES_UDP_SERVERIPv6ADDR_8=0x0d00 +CONFIG_EXAMPLES_UDP_SERVER_PORTNO=61616 +CONFIG_EXAMPLES_UDP_TARGET2=y +CONFIG_FAT_LCNAMES=y +CONFIG_FAT_LFN=y +CONFIG_FS_FAT=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_IEEE802154_I8SAK=y +CONFIG_IEEE802154_XBEE=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_IOB_BUFSIZE=128 +CONFIG_IOB_NBUFFERS=32 +CONFIG_IOB_NCHAINS=16 +CONFIG_LIBC_HOSTNAME="XBee" +CONFIG_LINE_MAX=64 +CONFIG_NET=y +CONFIG_NETDEV_LATEINIT=y +CONFIG_NETDEV_WIRELESS_IOCTL=y +CONFIG_NETINIT_NETLOCAL=y +CONFIG_NETINIT_NOMAC=y +CONFIG_NETUTILS_TELNETD=y +CONFIG_NET_6LOWPAN=y +CONFIG_NET_BROADCAST=y +CONFIG_NET_IPv6=y +CONFIG_NET_SOCKOPTS=y +CONFIG_NET_STATISTICS=y +CONFIG_NET_TCP=y +CONFIG_NET_TCP_WRITE_BUFFERS=y +CONFIG_NET_UDP=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_DISABLE_GET=y +CONFIG_NSH_DISABLE_PUT=y +CONFIG_NSH_DISABLE_WGET=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=131072 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=192 +CONFIG_SCHED_LPWORK=y +CONFIG_SCHED_LPWORKPRIORITY=160 +CONFIG_SCHED_WAITPID=y +CONFIG_START_YEAR=2013 +CONFIG_STM32_CCMEXCLUDE=y +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PWR=y +CONFIG_STM32_USART3=y +CONFIG_SYSTEM_NSH=y +CONFIG_SYSTEM_TELNET_CLIENT=y +CONFIG_TASK_NAME_SIZE=32 +CONFIG_USBDEV=y +CONFIG_WIRELESS=y +CONFIG_WIRELESS_IEEE802154=y diff --git a/boards/arm/stm32f4/clicker2-stm32/include/board.h b/boards/arm/stm32f4/clicker2-stm32/include/board.h new file mode 100644 index 0000000000000..5234be7f4f8b6 --- /dev/null +++ b/boards/arm/stm32f4/clicker2-stm32/include/board.h @@ -0,0 +1,321 @@ +/**************************************************************************** + * boards/arm/stm32f4/clicker2-stm32/include/board.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_STM32_CLICKER2_STM32_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32_CLICKER2_STM32_INCLUDE_BOARD_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#ifndef __ASSEMBLY__ +# include +# include +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Clocking *****************************************************************/ + +/* The Clicker 2 for STM32 board features a 25Hz crystal and 32.768kHz RTC + * crystal. + * + * This is the canonical configuration: + * System Clock source : PLL (HSE) + * SYSCLK(Hz) : 168000000 Determined by PLL configuration + * HCLK(Hz) : 168000000 (STM32_RCC_CFGR_HPRE) + * AHB Prescaler : 1 (STM32_RCC_CFGR_HPRE) + * APB1 Prescaler : 4 (STM32_RCC_CFGR_PPRE1) + * APB2 Prescaler : 2 (STM32_RCC_CFGR_PPRE2) + * HSE Frequency(Hz) : 25000000 (STM32_BOARD_XTAL) + * PLLM : 25 (STM32_PLLCFG_PLLM) + * PLLN : 336 (STM32_PLLCFG_PLLN) + * PLLP : 2 (STM32_PLLCFG_PLLP) + * PLLQ : 7 (STM32_PLLCFG_PLLQ) + * Main regulator + * output voltage : Scale1 mode Needed for high speed SYSCLK + * Flash Latency(WS) : 5 + * Prefetch Buffer : OFF + * Instruction cache : ON + * Data cache : ON + * Require 48MHz for + * USB OTG FS, : Enabled + * SDIO and RNG clock + */ + +/* HSI - 16 MHz RC factory-trimmed + * LSI - 32 KHz RC + * HSE - On-board crystal frequency is 25MHz + * LSE - 32.768 kHz + */ + +#define STM32_BOARD_XTAL 25000000ul + +#define STM32_HSI_FREQUENCY 16000000ul +#define STM32_LSI_FREQUENCY 32000 +#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL +#define STM32_LSE_FREQUENCY 32768 + +/* Main PLL Configuration. + * + * PLL source is HSE + * PLL_VCO = (STM32_HSE_FREQUENCY / PLLM) * PLLN + * = (25,000,000 / 25) * 336 + * = 336,000,000 + * SYSCLK = PLL_VCO / PLLP + * = 336,000,000 / 2 = 168,000,000 + * USB OTG FS, SDIO and RNG Clock + * = PLL_VCO / PLLQ + * = 48,000,000 + */ + +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(25) +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(336) +#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_2 +#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(7) + +#define STM32_SYSCLK_FREQUENCY 168000000ul + +/* AHB clock (HCLK) is SYSCLK (168MHz) */ + +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY + +/* APB1 clock (PCLK1) is HCLK/4 (42MHz) */ + +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd4 /* PCLK1 = HCLK / 4 */ +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/4) + +/* Timers driven from APB1 will be twice PCLK1 */ + +#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) + +/* APB2 clock (PCLK2) is HCLK/2 (84MHz) */ + +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLKd2 /* PCLK2 = HCLK / 2 */ +#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/2) + +/* Timers driven from APB2 will be twice PCLK2 */ + +#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM9_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM10_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM11_CLKIN (2*STM32_PCLK2_FREQUENCY) + +/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx + * otherwise frequency is 2xAPBx. + * Note: TIM1,8 are on APB2, others on APB1 + */ + +#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM2_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM3_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM4_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM5_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM6_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM7_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY + +/* SDIO dividers. Note that slower clocking is required when DMA is disabled + * in order to avoid RX overrun/TX underrun errors due to delayed responses + * to service FIFOs in interrupt driven mode. These values have not been + * tuned!!! + * + * SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(118+2)=400 KHz + */ + +#define SDIO_INIT_CLKDIV (118 << SDIO_CLKCR_CLKDIV_SHIFT) + +/* DMA ON: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(1+2)=16 MHz + * DMA OFF: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(2+2)=12 MHz + */ + +#ifdef CONFIG_SDIO_DMA +# define SDIO_MMCXFR_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT) +#else +# define SDIO_MMCXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT) +#endif + +/* DMA ON: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(1+2)=16 MHz + * DMA OFF: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(2+2)=12 MHz + */ + +#ifdef CONFIG_SDIO_DMA +# define SDIO_SDXFR_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT) +#else +# define SDIO_SDXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT) +#endif + +/* LED definitions **********************************************************/ + +/* The Mikroe Clicker2 STM32 has two user controllable LEDs: + * + * LD1 - PE12, Active high output illuminates + * LD2 - PE15, Active high output illuminates + * + * If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs in + * any way. The following definitions are used to access individual LEDs. + */ + +/* LED index values for use with board_userled() */ + +#define BOARD_LED1 0 +#define BOARD_LED2 1 +#define BOARD_NLEDS 2 + +/* LED bits for use with board_userled_all() */ + +#define BOARD_LED1_BIT (1 << BOARD_LED1) +#define BOARD_LED2_BIT (1 << BOARD_LED2) + +/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the 2 LEDs on + * board the Clicker2 for STM32. + * The following definitions describe how NuttX controls the LEDs: + * + * SYMBOL Meaning LED state + * LED1 LED2 + * ------------------- ----------------------- -------- -------- + * LED_STARTED NuttX has been started OFF OFF + * LED_HEAPALLOCATE Heap has been allocated OFF OFF + * LED_IRQSENABLED Interrupts enabled OFF OFF + * LED_STACKCREATED Idle stack created ON OFF + * LED_INIRQ In an interrupt N/C ON + * LED_SIGNAL In a signal handler No change + * LED_ASSERTION An assertion failed No change + * LED_PANIC The system has crashed OFF Blinking + * LED_IDLE STM32 is in sleep mode Not used + */ + +#define LED_STARTED 0 +#define LED_HEAPALLOCATE 0 +#define LED_IRQSENABLED 0 +#define LED_STACKCREATED 1 +#define LED_INIRQ 2 +#define LED_SIGNAL 3 +#define LED_ASSERTION 3 +#define LED_PANIC 4 + +/* Button definitions *******************************************************/ + +/* The Mikroe Clicker2 STM32 has two buttons available to software: + * + * T2 - PE0, Low sensed when pressed + * T3 - PA10, Low sensed when pressed + */ + +#define BUTTON_T2 0 +#define BUTTON_T3 1 +#define NUM_BUTTONS 2 + +#define BUTTON_T2_BIT (1 << BUTTON_T2) +#define BUTTON_T3_BIT (1 << BUTTON_T3) + +/* Alternate function pin selections ****************************************/ + +/* U[S]ARTs + * + * USART2 - mikroBUS1 + * USART3 - mikroBUS2 + * + * Assuming RS-232 connverted connected on mikroMB1/12 + */ + +#define GPIO_USART2_RX (GPIO_USART2_RX_2|GPIO_SPEED_100MHz) /* PD6 */ +#define GPIO_USART2_TX (GPIO_USART2_TX_2|GPIO_SPEED_100MHz) /* PD5 */ + +#define GPIO_USART3_RX (GPIO_USART3_RX_3|GPIO_SPEED_100MHz) /* PD9 */ +#define GPIO_USART3_TX (GPIO_USART3_TX_3|GPIO_SPEED_100MHz) /* PD8 */ + +/* SPI + * + * SPI2 - mikroBUS2 + * SPI3 - mikroBUS1 + */ + +#define GPIO_SPI2_MISO (GPIO_SPI2_MISO_1|GPIO_SPEED_50MHz) /* PC12 */ +#define GPIO_SPI2_MOSI (GPIO_SPI2_MOSI_1|GPIO_SPEED_50MHz) /* PC11 */ +#define GPIO_SPI2_SCK (GPIO_SPI2_SCK_2|GPIO_SPEED_50MHz) /* PC10 */ + +#define GPIO_SPI3_MISO (GPIO_SPI3_MISO_2|GPIO_SPEED_50MHz) /* PB15 */ +#define GPIO_SPI3_MOSI (GPIO_SPI3_MOSI_2|GPIO_SPEED_50MHz) /* PB14 */ +#define GPIO_SPI3_SCK (GPIO_SPI3_SCK_2|GPIO_SPEED_50MHz) /* PB13 */ + +/* I2C + * + * I2C2 - mikroBUS2 + * I2C3 - mikroBUS1 + */ + +#define GPIO_I2C2_SCL (GPIO_I2C2_SCL_1|GPIO_SPEED_50MHz) /* PB10 */ +#define GPIO_I2C2_SDA (GPIO_I2C2_SDA_1|GPIO_SPEED_50MHz) /* PB11 */ + +#define GPIO_I2C3_SCL (GPIO_I2C3_SCL_1|GPIO_SPEED_50MHz) /* PA8 */ +#define GPIO_I2C3_SDA (GPIO_I2C3_SDA_1|GPIO_SPEED_50MHz) /* PC9 */ + +/* Analog + * + * mikroBUS1 ADC: PA2-MB1_AN + * mikroBUS1 ADC: PA3-MB2_AN + */ + +/* PWM + * + * mikroBUS1 ADC: PE9-MB1-PWM (TIM1, channel 1) + * mikroBUS1 ADC: PD12-MB2-PWM (TIM4, channel 1) + */ + +#define GPIO_TIM1_CH1OUT (GPIO_TIM1_CH1OUT_2|GPIO_SPEED_50MHz) /* PE9 */ +#define GPIO_TIM4_CH1OUT (GPIO_TIM4_CH1OUT_2|GPIO_SPEED_50MHz) /* PD12 */ + +/* DMA Channel/Stream Selections ********************************************/ + +/* Stream selections are arbitrary for now but might become important in the + * future if we set aside more DMA channels/streams. + * + * SDIO DMA + * DMAMAP_SDIO_1 = Channel 4, Stream 3 + * DMAMAP_SDIO_2 = Channel 4, Stream 6 + */ + +#define DMAMAP_SDIO DMAMAP_SDIO_1 + +/* USB OTG FS */ + +#define GPIO_OTGFS_DM (GPIO_OTGFS_DM_0|GPIO_SPEED_100MHz) +#define GPIO_OTGFS_DP (GPIO_OTGFS_DP_0|GPIO_SPEED_100MHz) +#define GPIO_OTGFS_ID (GPIO_OTGFS_ID_0|GPIO_SPEED_100MHz) +#define GPIO_OTGFS_SOF (GPIO_OTGFS_SOF_0|GPIO_SPEED_100MHz) + +#endif /* __BOARDS_ARM_STM32_CLICKER2_STM32_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32f4/clicker2-stm32/kernel/Makefile b/boards/arm/stm32f4/clicker2-stm32/kernel/Makefile new file mode 100644 index 0000000000000..2f5b6553e7264 --- /dev/null +++ b/boards/arm/stm32f4/clicker2-stm32/kernel/Makefile @@ -0,0 +1,94 @@ +############################################################################ +# boards/arm/stm32f4/clicker2-stm32/kernel/Makefile +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +# The entry point name (if none is provided in the .config file) + +CONFIG_INIT_ENTRYPOINT ?= user_start +ENTRYPT = $(patsubst "%",%,$(CONFIG_INIT_ENTRYPOINT)) + +# Get the paths to the libraries and the links script path in format that +# is appropriate for the host OS + +USER_LIBPATHS = $(addprefix -L,$(call CONVERT_PATH,$(addprefix $(TOPDIR)$(DELIM),$(dir $(USERLIBS))))) +USER_LDSCRIPT = -T $(call CONVERT_PATH,$(BOARD_DIR)$(DELIM)scripts$(DELIM)memory.ld) +USER_LDSCRIPT += -T $(call CONVERT_PATH,$(BOARD_DIR)$(DELIM)scripts$(DELIM)user-space.ld) +USER_HEXFILE += $(call CONVERT_PATH,$(TOPDIR)$(DELIM)nuttx_user.hex) +USER_SRECFILE += $(call CONVERT_PATH,$(TOPDIR)$(DELIM)nuttx_user.srec) +USER_BINFILE += $(call CONVERT_PATH,$(TOPDIR)$(DELIM)nuttx_user.bin) + +USER_LDFLAGS = --undefined=$(ENTRYPT) --entry=$(ENTRYPT) $(USER_LDSCRIPT) +USER_LDLIBS = $(patsubst lib%,-l%,$(basename $(notdir $(USERLIBS)))) +USER_LIBGCC = "${shell "$(CC)" $(ARCHCPUFLAGS) -print-libgcc-file-name}" + +# Source files + +CSRCS = stm32_userspace.c +COBJS = $(CSRCS:.c=$(OBJEXT)) +OBJS = $(COBJS) + +# Targets: + +all: $(TOPDIR)$(DELIM)nuttx_user.elf $(TOPDIR)$(DELIM)User.map +.PHONY: nuttx_user.elf depend clean distclean + +$(COBJS): %$(OBJEXT): %.c + $(call COMPILE, $<, $@) + +# Create the nuttx_user.elf file containing all of the user-mode code + +nuttx_user.elf: $(OBJS) + $(Q) $(LD) -o $@ $(USER_LDFLAGS) $(USER_LIBPATHS) $(OBJS) --start-group $(USER_LDLIBS) --end-group $(USER_LIBGCC) + +$(TOPDIR)$(DELIM)nuttx_user.elf: nuttx_user.elf + @echo "LD: nuttx_user.elf" + $(Q) cp -a nuttx_user.elf $(TOPDIR)$(DELIM)nuttx_user.elf +ifeq ($(CONFIG_INTELHEX_BINARY),y) + @echo "CP: nuttx_user.hex" + $(Q) $(OBJCOPY) $(OBJCOPYARGS) -O ihex nuttx_user.elf $(USER_HEXFILE) +endif +ifeq ($(CONFIG_MOTOROLA_SREC),y) + @echo "CP: nuttx_user.srec" + $(Q) $(OBJCOPY) $(OBJCOPYARGS) -O srec nuttx_user.elf $(USER_SRECFILE) +endif +ifeq ($(CONFIG_RAW_BINARY),y) + @echo "CP: nuttx_user.bin" + $(Q) $(OBJCOPY) $(OBJCOPYARGS) -O binary nuttx_user.elf $(USER_BINFILE) +endif + +$(TOPDIR)$(DELIM)User.map: nuttx_user.elf + @echo "MK: User.map" + $(Q) $(NM) nuttx_user.elf >$(TOPDIR)$(DELIM)User.map + $(Q) $(CROSSDEV)size nuttx_user.elf + +.depend: + +depend: .depend + +clean: + $(call DELFILE, nuttx_user.elf) + $(call DELFILE, "$(TOPDIR)$(DELIM)nuttx_user.*") + $(call DELFILE, "$(TOPDIR)$(DELIM)User.map") + $(call CLEAN) + +distclean: clean diff --git a/boards/arm/stm32f4/clicker2-stm32/kernel/stm32_userspace.c b/boards/arm/stm32f4/clicker2-stm32/kernel/stm32_userspace.c new file mode 100644 index 0000000000000..fcaa153b6704d --- /dev/null +++ b/boards/arm/stm32f4/clicker2-stm32/kernel/stm32_userspace.c @@ -0,0 +1,113 @@ +/**************************************************************************** + * boards/arm/stm32f4/clicker2-stm32/kernel/stm32_userspace.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include +#include +#include +#include + +#if defined(CONFIG_BUILD_PROTECTED) && !defined(__KERNEL__) + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +#ifndef CONFIG_NUTTX_USERSPACE +# error "CONFIG_NUTTX_USERSPACE not defined" +#endif + +#if CONFIG_NUTTX_USERSPACE != 0x08020000 +# error "CONFIG_NUTTX_USERSPACE must be 0x08020000 to match memory.ld" +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static struct userspace_data_s g_userspace_data = +{ + .us_heap = &g_mmheap, +}; + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/* These 'addresses' of these values are setup by + * the linker script. + */ + +extern uint8_t _stext[]; /* Start of .text */ +extern uint8_t _etext[]; /* End_1 of .text + .rodata */ +extern const uint8_t _eronly[]; /* End+1 of read only section (.text + .rodata) */ +extern uint8_t _sdata[]; /* Start of .data */ +extern uint8_t _edata[]; /* End+1 of .data */ +extern uint8_t _sbss[]; /* Start of .bss */ +extern uint8_t _ebss[]; /* End+1 of .bss */ + +const struct userspace_s userspace locate_data(".userspace") = +{ + /* General memory map */ + + .us_entrypoint = CONFIG_INIT_ENTRYPOINT, + .us_textstart = (uintptr_t)_stext, + .us_textend = (uintptr_t)_etext, + .us_datasource = (uintptr_t)_eronly, + .us_datastart = (uintptr_t)_sdata, + .us_dataend = (uintptr_t)_edata, + .us_bssstart = (uintptr_t)_sbss, + .us_bssend = (uintptr_t)_ebss, + + /* User data memory structure */ + + .us_data = &g_userspace_data, + + /* Task/thread startup routines */ + + .task_startup = nxtask_startup, + + /* Signal handler trampoline */ + + .signal_handler = up_signal_handler, + + /* User-space work queue support (declared in include/nuttx/wqueue.h) */ + +#ifdef CONFIG_LIBC_USRWORK + .work_usrstart = work_usrstart, +#endif +}; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +#endif /* CONFIG_BUILD_PROTECTED && !__KERNEL__ */ diff --git a/boards/arm/stm32f4/clicker2-stm32/scripts/Make.defs b/boards/arm/stm32f4/clicker2-stm32/scripts/Make.defs new file mode 100644 index 0000000000000..a90d88a34ec92 --- /dev/null +++ b/boards/arm/stm32f4/clicker2-stm32/scripts/Make.defs @@ -0,0 +1,41 @@ +############################################################################ +# boards/arm/stm32f4/clicker2-stm32/scripts/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/.config +include $(TOPDIR)/tools/Config.mk +include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs + +LDSCRIPT = flash.ld +ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) + +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-gotoff.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32f4/clicker2-stm32/scripts/flash.ld b/boards/arm/stm32f4/clicker2-stm32/scripts/flash.ld new file mode 100644 index 0000000000000..4615162c950c8 --- /dev/null +++ b/boards/arm/stm32f4/clicker2-stm32/scripts/flash.ld @@ -0,0 +1,131 @@ +/**************************************************************************** + * boards/arm/stm32f4/clicker2-stm32/scripts/flash.ld + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* The STM32F407VG has 1024Kb of FLASH beginning at address 0x0800:0000 and + * 192Kb of SRAM. SRAM is split up into three blocks: + * + * 1) 112Kb of SRAM beginning at address 0x2000:0000 + * 2) 16Kb of SRAM beginning at address 0x2001:c000 + * 3) 64Kb of CCM SRAM beginning at address 0x1000:0000 + * + * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 + * where the code expects to begin execution by jumping to the entry point in + * the 0x0800:0000 address range. + */ + +MEMORY +{ + flash (rx) : ORIGIN = 0x08000000, LENGTH = 1024K + sram (rwx) : ORIGIN = 0x20000000, LENGTH = 112K +} + +OUTPUT_ARCH(arm) +EXTERN(_vectors) +ENTRY(_stext) +SECTIONS +{ + .text : + { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > flash + + .init_section : + { + _sinit = ABSOLUTE(.); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) + _einit = ABSOLUTE(.); + } > flash + + .ARM.extab : + { + *(.ARM.extab*) + } > flash + + __exidx_start = ABSOLUTE(.); + .ARM.exidx : + { + *(.ARM.exidx*) + } > flash + __exidx_end = ABSOLUTE(.); + + .tdata : { + _stdata = ABSOLUTE(.); + *(.tdata .tdata.* .gnu.linkonce.td.*); + _etdata = ABSOLUTE(.); + } > flash + + .tbss : { + _stbss = ABSOLUTE(.); + *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); + _etbss = ABSOLUTE(.); + } > flash + + _eronly = ABSOLUTE(.); + + .data : + { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > sram AT > flash + + .bss : + { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(8); + _ebss = ABSOLUTE(.); + } > sram + + /* Stabs debugging sections. */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/stm32f4/clicker2-stm32/scripts/kernel-space.ld b/boards/arm/stm32f4/clicker2-stm32/scripts/kernel-space.ld new file mode 100644 index 0000000000000..4ab5390cf829c --- /dev/null +++ b/boards/arm/stm32f4/clicker2-stm32/scripts/kernel-space.ld @@ -0,0 +1,106 @@ +/**************************************************************************** + * boards/arm/stm32f4/clicker2-stm32/scripts/kernel-space.ld + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* NOTE: This depends on the memory.ld script having been included prior to + * this script. + */ + +OUTPUT_ARCH(arm) +EXTERN(_vectors) +ENTRY(_stext) +SECTIONS +{ + .text : + { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > kflash + + .init_section : + { + _sinit = ABSOLUTE(.); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) + _einit = ABSOLUTE(.); + } > kflash + + .ARM.extab : + { + *(.ARM.extab*) + } > kflash + + __exidx_start = ABSOLUTE(.); + .ARM.exidx : + { + *(.ARM.exidx*) + } > kflash + + __exidx_end = ABSOLUTE(.); + + _eronly = ABSOLUTE(.); + + .data : + { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > ksram AT > kflash + + .bss : + { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(8); + _ebss = ABSOLUTE(.); + } > ksram + + /* Stabs debugging sections */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/stm32f4/clicker2-stm32/scripts/memory.ld b/boards/arm/stm32f4/clicker2-stm32/scripts/memory.ld new file mode 100644 index 0000000000000..c19be9593b5db --- /dev/null +++ b/boards/arm/stm32f4/clicker2-stm32/scripts/memory.ld @@ -0,0 +1,87 @@ +/**************************************************************************** + * boards/arm/stm32f4/clicker2-stm32/scripts/memory.ld + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* The STM32F407VG has 1024Kb of FLASH beginning at address 0x0800:0000 and + * 192Kb of SRAM. SRAM is split up into three blocks: + * + * 1) 112KB of SRAM beginning at address 0x2000:0000 + * 2) 16KB of SRAM beginning at address 0x2001:c000 + * 3) 64KB of CCM SRAM beginning at address 0x1000:0000 + * + * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 + * where the code expects to begin execution by jumping to the entry point in + * the 0x0800:0000 address range. + * + * For MPU support, the kernel-mode NuttX section is assumed to be 128Kb of + * FLASH and 4Kb of SRAM. That is an excessive amount for the kernel which + * should fit into 64KB and, of course, can be optimized as needed (See + * also boards/arm/stm32f4/clicker2-stm32/scripts/kernel-space.ld). Allowing the + * additional does permit addition debug instrumentation to be added to the + * kernel space without overflowing the partition. + * + * Alignment of the user space FLASH partition is also a critical factor: + * The user space FLASH partition will be spanned with a single region of + * size 2**n bytes. The alignment of the user-space region must be the same. + * As a consequence, as the user-space increases in size, the alignment + * requirement also increases. + * + * This alignment requirement means that the largest user space FLASH region + * you can have will be 512KB at it would have to be positioned at + * 0x08800000. If you change this address, don't forget to change the + * CONFIG_NUTTX_USERSPACE configuration setting to match and to modify + * the check in kernel/userspace.c. + * + * For the same reasons, the maximum size of the SRAM mapping is limited to + * 4KB. Both of these alignment limitations could be reduced by using + * multiple regions to map the FLASH/SDRAM range or perhaps with some + * clever use of subregions. + * + * A detailed memory map for the 112KB SRAM region is as follows: + * + * 0x20000 0000: Kernel .data region. Typical size: 0.1KB + * ------- ---- Kernel .bss region. Typical size: 1.8KB + * 0x20000 0800: Kernel IDLE thread stack (approximate). Size is + * determined by CONFIG_IDLETHREAD_STACKSIZE and + * adjustments for alignment. Typical is 1KB. + * ------- ---- Padded to 4KB + * 0x20000 1000: User .data region. Size is variable. + * ------- ---- User .bss region Size is variable. + * 0x20000 2000: Beginning of kernel heap. Size determined by + * CONFIG_MM_KERNEL_HEAPSIZE. + * ------- ---- Beginning of user heap. Can vary with other settings. + * 0x20001 c000: End+1 of CPU RAM + */ + +MEMORY +{ + /* 1024Kb FLASH */ + + kflash (rx) : ORIGIN = 0x08000000, LENGTH = 128K + uflash (rx) : ORIGIN = 0x08020000, LENGTH = 128K + xflash (rx) : ORIGIN = 0x08040000, LENGTH = 768K + + /* 112Kb of contiguous SRAM */ + + ksram (rwx) : ORIGIN = 0x20000000, LENGTH = 4K + usram (rwx) : ORIGIN = 0x20001000, LENGTH = 4K + xsram (rwx) : ORIGIN = 0x20002000, LENGTH = 104K +} diff --git a/boards/arm/stm32f4/clicker2-stm32/scripts/user-space.ld b/boards/arm/stm32f4/clicker2-stm32/scripts/user-space.ld new file mode 100644 index 0000000000000..a7fa7ca7f5626 --- /dev/null +++ b/boards/arm/stm32f4/clicker2-stm32/scripts/user-space.ld @@ -0,0 +1,108 @@ +/**************************************************************************** + * boards/arm/stm32f4/clicker2-stm32/scripts/user-space.ld + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* NOTE: This depends on the memory.ld script having been included prior to + * this script. + */ + +OUTPUT_ARCH(arm) +SECTIONS +{ + .userspace : + { + *(.userspace) + } > uflash + + .text : + { + _stext = ABSOLUTE(.); + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > uflash + + .init_section : + { + _sinit = ABSOLUTE(.); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) + _einit = ABSOLUTE(.); + } > uflash + + .ARM.extab : + { + *(.ARM.extab*) + } > uflash + + __exidx_start = ABSOLUTE(.); + .ARM.exidx : + { + *(.ARM.exidx*) + } > uflash + + __exidx_end = ABSOLUTE(.); + + _eronly = ABSOLUTE(.); + + .data : + { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > usram AT > uflash + + .bss : + { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(8); + _ebss = ABSOLUTE(.); + } > usram + + /* Stabs debugging sections */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/stm32f4/clicker2-stm32/src/CMakeLists.txt b/boards/arm/stm32f4/clicker2-stm32/src/CMakeLists.txt new file mode 100644 index 0000000000000..ae754f915ab1c --- /dev/null +++ b/boards/arm/stm32f4/clicker2-stm32/src/CMakeLists.txt @@ -0,0 +1,65 @@ +# ############################################################################## +# boards/arm/stm32f4/clicker2-stm32/src/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(SRCS stm32_boot.c stm32_bringup.c stm32_spi.c) + +if(CONFIG_ARCH_LEDS) + list(APPEND SRCS stm32_autoleds.c) +else() + list(APPEND SRCS stm32_userleds.c) +endif() + +if(CONFIG_ARCH_BUTTONS) + list(APPEND SRCS stm32_buttons.c) +endif() + +if(CONFIG_STM32_OTGFS) + list(APPEND SRCS stm32_usb.c) +endif() + +if(CONFIG_IEEE802154_MRF24J40) + list(APPEND SRCS stm32_mrf24j40.c) +endif() + +if(CONFIG_IEEE802154_XBEE) + list(APPEND SRCS stm32_xbee.c) +endif() + +if(CONFIG_MMCSD_SPI) + list(APPEND SRCS stm32_mmcsd.c) +endif() + +if(CONFIG_FS_AUTOMOUNTER) + list(APPEND SRCS stm32_automount.c) +endif() + +if(CONFIG_ADC) + list(APPEND SRCS stm32_adc.c) +endif() + +if(CONFIG_STM32_CAN_CHARDRIVER) + list(APPEND SRCS stm32_can.c) +endif() + +target_sources(board PRIVATE ${SRCS}) + +set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/flash.ld") diff --git a/boards/arm/stm32f4/clicker2-stm32/src/Make.defs b/boards/arm/stm32f4/clicker2-stm32/src/Make.defs new file mode 100644 index 0000000000000..8aa9073a43a93 --- /dev/null +++ b/boards/arm/stm32f4/clicker2-stm32/src/Make.defs @@ -0,0 +1,67 @@ +############################################################################ +# boards/arm/stm32f4/clicker2-stm32/src/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +CSRCS = stm32_boot.c stm32_bringup.c stm32_spi.c + +ifeq ($(CONFIG_ARCH_LEDS),y) +CSRCS += stm32_autoleds.c +else +CSRCS += stm32_userleds.c +endif + +ifeq ($(CONFIG_ARCH_BUTTONS),y) +CSRCS += stm32_buttons.c +endif + +ifeq ($(CONFIG_STM32_OTGFS),y) +CSRCS += stm32_usb.c +endif + +ifeq ($(CONFIG_IEEE802154_MRF24J40),y) +CSRCS += stm32_mrf24j40.c +endif + +ifeq ($(CONFIG_IEEE802154_XBEE),y) +CSRCS += stm32_xbee.c +endif + +ifeq ($(CONFIG_MMCSD_SPI),y) +CSRCS += stm32_mmcsd.c +endif + +ifeq ($(CONFIG_FS_AUTOMOUNTER),y) +CSRCS += stm32_automount.c +endif + +ifeq ($(CONFIG_ADC),y) +CSRCS += stm32_adc.c +endif + +ifeq ($(CONFIG_STM32_CAN_CHARDRIVER),y) +CSRCS += stm32_can.c +endif + +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/clicker2-stm32/src/clicker2-stm32.h b/boards/arm/stm32f4/clicker2-stm32/src/clicker2-stm32.h similarity index 99% rename from boards/arm/stm32/clicker2-stm32/src/clicker2-stm32.h rename to boards/arm/stm32f4/clicker2-stm32/src/clicker2-stm32.h index 206efc3a8ba01..021d8c0ceac95 100644 --- a/boards/arm/stm32/clicker2-stm32/src/clicker2-stm32.h +++ b/boards/arm/stm32f4/clicker2-stm32/src/clicker2-stm32.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/clicker2-stm32/src/clicker2-stm32.h + * boards/arm/stm32f4/clicker2-stm32/src/clicker2-stm32.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f4/clicker2-stm32/src/stm32_adc.c b/boards/arm/stm32f4/clicker2-stm32/src/stm32_adc.c new file mode 100644 index 0000000000000..2da98b9f340d4 --- /dev/null +++ b/boards/arm/stm32f4/clicker2-stm32/src/stm32_adc.c @@ -0,0 +1,156 @@ +/**************************************************************************** + * boards/arm/stm32f4/clicker2-stm32/src/stm32_adc.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include +#include + +#include "chip.h" +#include "stm32_adc.h" +#include "clicker2-stm32.h" + +#ifdef CONFIG_ADC + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* Up to 3 ADC interfaces are supported */ + +#if STM32_NADC < 3 +# undef CONFIG_STM32_ADC3 +#endif + +#if STM32_NADC < 2 +# undef CONFIG_STM32_ADC2 +#endif + +#if STM32_NADC < 1 +# undef CONFIG_STM32_ADC1 +#endif + +#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) || defined(CONFIG_STM32_ADC3) +#ifndef CONFIG_STM32_ADC1 +# warning "Channel information only available for ADC1" +#endif + +/* The number of ADC channels in the conversion list */ + +#define ADC1_NCHANNELS 1 + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* The Olimex STM32-P407 has a 10 Kohm potentiometer AN_TR connected to PC0 + * ADC123_IN10 + */ + +/* Identifying number of each ADC channel: Variable Resistor. */ + +#ifdef CONFIG_STM32_ADC1 +static const uint8_t g_chanlist[ADC1_NCHANNELS] = +{ + 10 +}; + +/* Configurations of pins used byte each ADC channels */ + +static const uint32_t g_pinlist[ADC1_NCHANNELS] = +{ + GPIO_ADC1_IN10 +}; +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_adc_setup + * + * Description: + * Initialize ADC and register the ADC driver. + * + ****************************************************************************/ + +int stm32_adc_setup(void) +{ +#ifdef CONFIG_STM32_ADC1 + static bool initialized = false; + struct adc_dev_s *adc; + int ret; + int i; + + /* Check if we have already initialized */ + + if (!initialized) + { + /* Configure the pins as analog inputs for the selected channels */ + + for (i = 0; i < ADC1_NCHANNELS; i++) + { + stm32_configgpio(g_pinlist[i]); + } + + /* Call stm32_adcinitialize() to get an instance of the ADC interface */ + + adc = stm32_adcinitialize(1, g_chanlist, ADC1_NCHANNELS); + if (adc == NULL) + { + aerr("ERROR: Failed to get ADC interface\n"); + return -ENODEV; + } + + /* Register the ADC driver at "/dev/adc0" */ + + ret = adc_register("/dev/adc0", adc); + if (ret < 0) + { + aerr("ERROR: adc_register failed: %d\n", ret); + return ret; + } + + /* Now we are initialized */ + + initialized = true; + } + + return OK; +#else + return -ENOSYS; +#endif +} + +#endif /* CONFIG_STM32_ADC1 || CONFIG_STM32_ADC2 || CONFIG_STM32_ADC3 */ +#endif /* CONFIG_ADC */ diff --git a/boards/arm/stm32f4/clicker2-stm32/src/stm32_autoleds.c b/boards/arm/stm32f4/clicker2-stm32/src/stm32_autoleds.c new file mode 100644 index 0000000000000..c05d2d69f3a0e --- /dev/null +++ b/boards/arm/stm32f4/clicker2-stm32/src/stm32_autoleds.c @@ -0,0 +1,189 @@ +/**************************************************************************** + * boards/arm/stm32f4/clicker2-stm32/src/stm32_autoleds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the 2 LEDs on + * board the Clicker2 for STM32. The following definitions describe how + * NuttX controls the LEDs: + * + * SYMBOL Meaning LED state + * LED1 LED2 + * ------------------- ----------------------- -------- -------- + * LED_STARTED NuttX has been started OFF OFF + * LED_HEAPALLOCATE Heap has been allocated OFF OFF + * LED_IRQSENABLED Interrupts enabled OFF OFF + * LED_STACKCREATED Idle stack created ON OFF + * LED_INIRQ In an interrupt N/C ON + * LED_SIGNAL In a signal handler No change + * LED_ASSERTION An assertion failed No change + * LED_PANIC The system has crashed OFF Blinking + * LED_IDLE STM32 is in sleep mode Not used + * + * VALUE + * -------------------------------------------- -------- -------- + * 0 OFF OFF + * 1 ON OFF + * 2 N/C ON + * 3 N/C N/C + * 4 OFF ON + */ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "stm32.h" +#include "clicker2-stm32.h" + +#ifdef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +static void board_led1_on(int led) +{ + bool ledon = false; + + switch (led) + { + case 0: /* LED1=OFF */ + case 4: /* LED1=OFF */ + break; + + case 1: /* LED1=ON */ + ledon = true; + break; + + case 2: /* LED1=N/C */ + case 3: /* LED1=N/C */ + default: + return; + } + + stm32_gpiowrite(GPIO_LED1, ledon); +} + +static void board_led2_on(int led) +{ + bool ledon = false; + + switch (led) + { + case 0: /* LED2=OFF */ + case 1: /* LED2=OFF */ + break; + + case 2: /* LED2=ON */ + case 4: /* LED2=ON */ + ledon = true; + break; + + case 3: /* LED2=N/C */ + default: + return; + } + + stm32_gpiowrite(GPIO_LED2, ledon); +} + +static void board_led1_off(int led) +{ + switch (led) + { + case 0: /* LED1=OFF */ + case 1: /* LED1=OFF */ + case 4: /* LED1=OFF */ + break; + + case 2: /* LED1=N/C */ + case 3: /* LED1=N/C */ + default: + return; + } + + stm32_gpiowrite(GPIO_LED1, false); +} + +static void board_led2_off(int led) +{ + switch (led) + { + case 0: /* LED2=OFF */ + case 1: /* LED2=OFF */ + case 2: /* LED2=OFF */ + case 4: /* LED2=OFF */ + break; + + case 3: /* LED2=N/C */ + default: + return; + } + + stm32_gpiowrite(GPIO_LED2, false); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_autoled_initialize + ****************************************************************************/ + +void board_autoled_initialize(void) +{ + /* Configure LED1-2 GPIOs for output */ + + stm32_configgpio(GPIO_LED1); + stm32_configgpio(GPIO_LED2); +} + +/**************************************************************************** + * Name: board_autoled_on + ****************************************************************************/ + +void board_autoled_on(int led) +{ + board_led1_on(led); + board_led2_on(led); +} + +/**************************************************************************** + * Name: board_autoled_off + ****************************************************************************/ + +void board_autoled_off(int led) +{ + board_led1_off(led); + board_led2_off(led); +} + +#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/clicker2-stm32/src/stm32_automount.c b/boards/arm/stm32f4/clicker2-stm32/src/stm32_automount.c similarity index 99% rename from boards/arm/stm32/clicker2-stm32/src/stm32_automount.c rename to boards/arm/stm32f4/clicker2-stm32/src/stm32_automount.c index 6b2927ae6b590..7b3b777ceebb0 100644 --- a/boards/arm/stm32/clicker2-stm32/src/stm32_automount.c +++ b/boards/arm/stm32f4/clicker2-stm32/src/stm32_automount.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/clicker2-stm32/src/stm32_automount.c + * boards/arm/stm32f4/clicker2-stm32/src/stm32_automount.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f4/clicker2-stm32/src/stm32_boot.c b/boards/arm/stm32f4/clicker2-stm32/src/stm32_boot.c new file mode 100644 index 0000000000000..89ef2589b8e43 --- /dev/null +++ b/boards/arm/stm32f4/clicker2-stm32/src/stm32_boot.c @@ -0,0 +1,139 @@ +/**************************************************************************** + * boards/arm/stm32f4/clicker2-stm32/src/stm32_boot.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include "clicker2-stm32.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_boardinitialize + * + * Description: + * All STM32 architectures must provide the following entry point. + * This entry point is called early in the initialization -- after all + * memory has been configured and mapped but before any devices have been + * initialized. + * + ****************************************************************************/ + +void stm32_boardinitialize(void) +{ +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || defined(CONFIG_STM32_SPI3) + /* Configure SPI chip selects if 1) SPI is not disabled, and 2) the weak + * function stm32_spidev_initialize() has been brought into the link. + */ + + if (stm32_spidev_initialize) + { + stm32_spidev_initialize(); + } +#endif + +#ifdef CONFIG_STM32_OTGFS + /* Initialize USB if the 1) OTG FS controller is in the configuration and + * 2) disabled, and 3) the weak function stm32_usb_configure() has been + * brought into the build. Presumably either CONFIG_USBDEV or + * CONFIG_USBHOST is also selected. + */ + + stm32_usb_configure(); +#endif + +#ifdef CONFIG_ARCH_LEDS + /* Configure on-board LEDs if LED support has been selected. */ + + board_autoled_initialize(); +#endif + +#ifdef CONFIG_ARCH_BUTTONS + /* Configure on-board BUTTONs if BUTTON support has been selected. */ + + board_button_initialize(); +#endif +} + +/**************************************************************************** + * Name: board_late_initialize + * + * Description: + * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_late_initialize(). board_late_initialize() will be + * called immediately after up_initialize() is called and just before the + * initial application is started. This additional initialization phase + * may be used, for example, to initialize board-specific device drivers. + * + ****************************************************************************/ + +#ifdef CONFIG_BOARD_LATE_INITIALIZE +void board_late_initialize(void) +{ + int ret; + + ret = stm32_bringup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_bringup() failed: %d\n", ret); + return; + } + +#ifdef CONFIG_CLICKER2_STM32_SYSLOG_FILE + + /* Delay some time for the automounter to finish mounting before + * bringing up file syslog. + */ + + nxsched_usleep(CONFIG_CLICKER2_STM32_SYSLOG_FILE_DELAY * 1000); + + syslog_channel_t *channel; + channel = syslog_file_channel(CONFIG_CLICKER2_STM32_SYSLOG_FILE_PATH); + if (channel == NULL) + { + syslog(LOG_ERR, "ERROR: syslog_file_channel() failed\n"); + return; + } +#endif + + UNUSED(ret); +} +#endif diff --git a/boards/arm/stm32f4/clicker2-stm32/src/stm32_bringup.c b/boards/arm/stm32f4/clicker2-stm32/src/stm32_bringup.c new file mode 100644 index 0000000000000..385e36e540a8f --- /dev/null +++ b/boards/arm/stm32f4/clicker2-stm32/src/stm32_bringup.c @@ -0,0 +1,193 @@ +/**************************************************************************** + * boards/arm/stm32f4/clicker2-stm32/src/stm32_bringup.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include +#include + +#ifdef CONFIG_USBMONITOR +# include +#endif + +#ifdef CONFIG_RNDIS +# include +# include +#endif + +#include "stm32.h" +#include "clicker2-stm32.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifdef CONFIG_RNDIS +# ifndef CONFIG_CLICKER2_STM32_RNDIS_MACADDR +# define CONFIG_CLICKER2_STM32_RNDIS_MACADDR 0xfadedeadbeef +# endif +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_bringup + * + * Description: + * Perform architecture-specific initialization + * + * CONFIG_BOARD_LATE_INITIALIZE=y : + * Called from board_late_initialize(). + * + ****************************************************************************/ + +int stm32_bringup(void) +{ + int ret; + +#ifdef CONFIG_FS_PROCFS + /* Mount the procfs file system */ + + ret = nx_mount(NULL, "/proc", "procfs", 0, NULL); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to mount procfs at /proc: %d\n", ret); + } +#endif + +#ifdef CONFIG_STM32_CAN_CHARDRIVER + /* Initialize CAN and register the CAN driver. */ + + ret = stm32_can_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_can_setup failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_ADC + /* Initialize ADC and register the ADC driver. */ + + ret = stm32_adc_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_adc_setup failed: %d\n", ret); + } +#endif + +#ifdef HAVE_USBMONITOR + /* Start the USB Monitor */ + + ret = usbmonitor_start(); + if (ret != OK) + { + syslog(LOG_ERR, "ERROR: Failed to start USB monitor: %d\n", ret); + } +#endif + +#if defined(CONFIG_CLICKER2_STM32_MB1_BEE) || defined(CONFIG_CLICKER2_STM32_MB2_BEE) + /* Configure MRF24J40 wireless */ + + ret = stm32_mrf24j40_initialize(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_mrf24j40_initialize() failed: %d\n", + ret); + } +#endif + +#if defined(CONFIG_CLICKER2_STM32_MB1_XBEE) || defined(CONFIG_CLICKER2_STM32_MB2_XBEE) + /* Configure XBee wireless */ + + ret = stm32_xbee_initialize(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_xbee_initialize() failed: %d\n", ret); + } +#endif + +#if defined(CONFIG_CLICKER2_STM32_MB1_MMCSD_AUTOMOUNT) || \ + defined(CONFIG_CLICKER2_STM32_MB2_MMCSD_AUTOMOUNT) + /* Configure uSD automounter */ + + ret = stm32_automount_initialize(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_automount_initialize() failed: %d\n", + ret); + } +#endif + +#if defined(CONFIG_CLICKER2_STM32_MB1_MMCSD) || defined(CONFIG_CLICKER2_STM32_MB2_MMCSD) + /* Configure uSD card slot */ + + ret = stm32_mmcsd_initialize(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_mmcsd_initialize() failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_INPUT_BUTTONS + /* Register the BUTTON driver */ + + ret = btn_lower_initialize("/dev/buttons"); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: btn_lower_initialize() failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_RNDIS + uint8_t mac[IFHWADDRLEN]; + + mac[0] = (CONFIG_CLICKER2_STM32_RNDIS_MACADDR >> (8 * 5)) & 0xff; + mac[1] = (CONFIG_CLICKER2_STM32_RNDIS_MACADDR >> (8 * 4)) & 0xff; + mac[2] = (CONFIG_CLICKER2_STM32_RNDIS_MACADDR >> (8 * 3)) & 0xff; + mac[3] = (CONFIG_CLICKER2_STM32_RNDIS_MACADDR >> (8 * 2)) & 0xff; + mac[4] = (CONFIG_CLICKER2_STM32_RNDIS_MACADDR >> (8 * 1)) & 0xff; + mac[5] = (CONFIG_CLICKER2_STM32_RNDIS_MACADDR >> (8 * 0)) & 0xff; + + /* Register USB RNDIS Driver */ + + ret = usbdev_rndis_initialize(mac); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: usbdev_rndis_initialize() failed %d\n", ret); + } +#endif + + UNUSED(ret); + return OK; +} diff --git a/boards/arm/stm32f4/clicker2-stm32/src/stm32_buttons.c b/boards/arm/stm32f4/clicker2-stm32/src/stm32_buttons.c new file mode 100644 index 0000000000000..357926885bde3 --- /dev/null +++ b/boards/arm/stm32f4/clicker2-stm32/src/stm32_buttons.c @@ -0,0 +1,123 @@ +/**************************************************************************** + * boards/arm/stm32f4/clicker2-stm32/src/stm32_buttons.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include +#include + +#include "stm32_gpio.h" +#include "stm32_exti.h" + +#include "clicker2-stm32.h" + +#ifdef CONFIG_ARCH_BUTTONS + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_button_initialize + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. + * + ****************************************************************************/ + +uint32_t board_button_initialize(void) +{ + /* Configure BUTTONS T2-T3 GPIOs for input */ + + stm32_configgpio(GPIO_BTN_T2); + stm32_configgpio(GPIO_BTN_T3); + return NUM_BUTTONS; +} + +/**************************************************************************** + * Name: board_buttons + ****************************************************************************/ + +uint32_t board_buttons(void) +{ + uint32_t ret = 0; + + /* Check that state of each key. A low value will be sensed when the + * button is pressed. + */ + + if (!stm32_gpioread(GPIO_BTN_T2)) + { + ret |= BUTTON_T2_BIT; + } + + if (!stm32_gpioread(GPIO_BTN_T3)) + { + ret |= BUTTON_T3_BIT; + } + + return ret; +} + +/**************************************************************************** + * Button support. + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. + * + * After board_button_initialize() has been called, board_buttons() may be + * called to collect the state of all buttons. board_buttons() returns an + * 32-bit bit set with each bit associated with a button. See the + * BUTTON_*_BIT definitions in board.h for the meaning of each bit. + * + * board_button_irq() may be called to register an interrupt handler that + * will be called when a button is depressed or released. The ID value is a + * button enumeration value that uniquely identifies a button resource. See + * the BUTTON_* definitions in board.h for the meaning of enumeration + * value. + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_IRQBUTTONS +int board_button_irq(int id, xcpt_t irqhandler, void *arg) +{ + uint32_t btncfg; + + btncfg = (id == BUTTON_T2) ? GPIO_BTN_T2 : GPIO_BTN_T3; + return stm32_gpiosetevent(btncfg, true, true, true, irqhandler, arg); +} +#endif +#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/stm32f4/clicker2-stm32/src/stm32_can.c b/boards/arm/stm32f4/clicker2-stm32/src/stm32_can.c new file mode 100644 index 0000000000000..c5487024a4751 --- /dev/null +++ b/boards/arm/stm32f4/clicker2-stm32/src/stm32_can.c @@ -0,0 +1,100 @@ +/**************************************************************************** + * boards/arm/stm32f4/clicker2-stm32/src/stm32_can.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include + +#include "stm32.h" +#include "stm32_can.h" +#include "clicker2-stm32.h" + +#ifdef CONFIG_CAN + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +#if defined(CONFIG_STM32_CAN1) && defined(CONFIG_STM32_CAN2) +# warning "Both CAN1 and CAN2 are enabled. Only CAN1 is connected." +# undef CONFIG_STM32_CAN2 +#endif + +#ifdef CONFIG_STM32_CAN1 +# define CAN_PORT 1 +#else +# define CAN_PORT 2 +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_can_setup + * + * Description: + * Initialize CAN and register the CAN device + * + ****************************************************************************/ + +int stm32_can_setup(void) +{ +#if defined(CONFIG_STM32_CAN1) || defined(CONFIG_STM32_CAN2) + struct can_dev_s *can; + int ret; + + /* Call stm32_caninitialize() to get an instance of the CAN interface */ + + can = stm32_caninitialize(CAN_PORT); + if (can == NULL) + { + canerr("ERROR: Failed to get CAN interface\n"); + return -ENODEV; + } + + /* Register the CAN driver at "/dev/can0" */ + + ret = can_register("/dev/can0", can); + if (ret < 0) + { + canerr("ERROR: can_register failed: %d\n", ret); + return ret; + } + + return OK; +#else + return -ENODEV; +#endif +} + +#endif /* CONFIG_CAN */ diff --git a/boards/arm/stm32f4/clicker2-stm32/src/stm32_mmcsd.c b/boards/arm/stm32f4/clicker2-stm32/src/stm32_mmcsd.c new file mode 100644 index 0000000000000..6d34e4bb2150a --- /dev/null +++ b/boards/arm/stm32f4/clicker2-stm32/src/stm32_mmcsd.c @@ -0,0 +1,423 @@ +/**************************************************************************** + * boards/arm/stm32f4/clicker2-stm32/src/stm32_mmcsd.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include "stm32_spi.h" + +#include "clicker2-stm32.h" + +#ifdef CONFIG_MMCSD_SPI + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#if !defined(CONFIG_CLICKER2_STM32_MB1_MMCSD) && \ + !defined(CONFIG_CLICKER2_STM32_MB2_MMCSD) +# error Only the Mikroe uSD click boards are supported +#endif + +/* Can't support MMC/SD features if mountpoints are disabled or if SDIO + * support is not enabled. + */ + +#if defined(CONFIG_DISABLE_MOUNTPOINT) +# error Mountpoints are required for MMCSD support +#endif + +#ifdef CONFIG_CLICKER2_STM32_MB1_MMCSD +# ifndef CONFIG_STM32_SPI3 +# error MMCSD on mikroBUS1 requires CONFIG_STM32_SPI3 +# endif +#endif + +#ifdef CONFIG_CLICKER2_STM32_MB2_MMCSD +# ifndef CONFIG_STM32_SPI2 +# error MMCSD on mikroBUS1 requires CONFIG_STM32_SPI2 +# endif +#endif + +#ifdef CONFIG_SCHED_LPWORK +# define MMCSDWORK LPWORK +#elif defined (CONFIG_SCHED_HPWORK) +# define MMCSDWORK HPWORK +#else +# error High or low priority work queue required for MMCSD support +#endif + +/* Card Detect + * + * mikroBUS1 Card Detect (AN pin): PE10-MB1_INT + * mikroBUS2 Card Detect (AN pin: PE14-MB2_INT + * + * There is a pull-up on the uSD click board` + */ + +#define GPIO_MB1_CD (GPIO_INPUT|GPIO_FLOAT|GPIO_EXTI|GPIO_PORTA|GPIO_PIN2) +#define GPIO_MB2_CD (GPIO_INPUT|GPIO_FLOAT|GPIO_EXTI|GPIO_PORTA|GPIO_PIN3) + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/* This structure holds static information unique to one MMCSD slot */ + +struct stm32_mmcsd_state_s +{ + uint8_t spidev; /* SPI bus used for MMCSD */ + uint8_t slotno; /* Slot number */ + int minor; /* The MMC/SD minor device number */ + uint32_t cdcfg; /* Card detect PIO pin configuration */ + xcpt_t handler; /* Interrupt handler */ + bool cd; /* TRUE: card is inserted */ + spi_mediachange_t callback; /* SPI media change callback */ + void *cbarg; /* Argument to pass to media change callback */ + struct work_s work; /* For deferring card detect interrupt work */ +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +static bool stm32_cardinserted_internal(struct stm32_mmcsd_state_s *state); +static void stm32_mmcsd_carddetect(void *arg); +static int stm32_mmcsd_setup(struct stm32_mmcsd_state_s *); + +#ifdef CONFIG_CLICKER2_STM32_MB1_MMCSD +static int stm32_mb1_mmcsd_carddetect(int irq, + void *regs, + void *arg); +#endif + +#ifdef CONFIG_CLICKER2_STM32_MB2_MMCSD +static int stm32_mb2_mmcsd_carddetect(int irq, + void *regs, + void *arg); +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* MMCSD device state */ + +#ifdef CONFIG_CLICKER2_STM32_MB1_MMCSD +static int stm32_mb1_mmcsd_carddetect(int irq, void *regs, void *arg); + +static struct stm32_mmcsd_state_s g_mb1_mmcsd = +{ + .spidev = 3, + .slotno = MB1_MMCSD_SLOTNO, + .minor = MB1_MMCSD_MINOR, + .cdcfg = GPIO_MB1_CD, + .handler = stm32_mb1_mmcsd_carddetect, + .callback = NULL, + .cbarg = NULL, +}; +#endif + +#ifdef CONFIG_CLICKER2_STM32_MB2_MMCSD +static int stm32_mb2_mmcsd_carddetect(int irq, void *regs, void *arg); + +static struct stm32_mmcsd_state_s g_mb2_mmcsd = +{ + .spidev = 2, + .slotno = MB2_MMCSD_SLOTNO, + .minor = MB2_MMCSD_MINOR, + .cdcfg = GPIO_MB2_CD, + .handler = stm32_mb2_mmcsd_carddetect, + .callback = NULL, + .cbarg = NULL, +}; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_cardinserted_internal + * + * Description: + * Check if a card is inserted into the selected MMCSD slot + * + ****************************************************************************/ + +static bool stm32_cardinserted_internal(struct stm32_mmcsd_state_s *state) +{ + bool inserted; + + /* Get the state of the PIO pin */ + + inserted = stm32_gpioread(state->cdcfg); + finfo("Slot %d inserted: %s\n", state->slotno, inserted ? "NO" : "YES"); + return !inserted; +} + +/**************************************************************************** + * Name: stm32_mmcsd_carddetect, stm32_mb1_mmcsd_carddetect, and + * stm32_mb2_mmcsd_carddetect + * + * Description: + * Card detect interrupt handlers + * + ****************************************************************************/ + +static void stm32_mmcsd_carddetect(void *arg) +{ + bool cd; + struct stm32_mmcsd_state_s *state = + (struct stm32_mmcsd_state_s *)arg; + + /* Get the current card insertion state */ + + cd = stm32_cardinserted_internal(state); + + /* Has the card detect state changed? */ + + if (cd != state->cd) + { + /* Yes... remember that new state and inform the HSMCI driver */ + + state->cd = cd; + + /* Report the new state to the SPI driver */ + + if (state->callback) + { + state->callback(state->cbarg); + } + } + +#ifdef HAVE_AUTOMOUNTER + /* Let the automounter know about the insertion event */ + + stm32_automount_event(state->slotno, stm32_cardinserted(state->slotno)); +#endif +} + +#ifdef CONFIG_CLICKER2_STM32_MB1_MMCSD +static int stm32_mb1_mmcsd_carddetect(int irq, void *regs, void *arg) +{ + if (work_available(&g_mb1_mmcsd.work)) + { + return work_queue(MMCSDWORK, &g_mb1_mmcsd.work, stm32_mmcsd_carddetect, + &g_mb1_mmcsd, 0); + } + + return OK; +} +#endif + +#ifdef CONFIG_CLICKER2_STM32_MB2_MMCSD +static int stm32_mb2_mmcsd_carddetect(int irq, void *regs, void *arg) +{ + if (work_available(&g_mb2_mmcsd.work)) + { + return work_queue(MMCSDWORK, &g_mb2_mmcsd.work, stm32_mmcsd_carddetect, + &g_mb2_mmcsd, 0); + } + + return OK; +} +#endif + +static int stm32_mmcsd_setup(struct stm32_mmcsd_state_s *state) +{ + struct spi_dev_s *spi; + int ret; + + /* Initialize the SPI bus and get an instance of the SPI interface */ + + spi = stm32_spibus_initialize(state->spidev); + if (spi == NULL) + { + spierr("ERROR: Failed to initialize SPI bus %d\n", state->spidev); + return -ENODEV; + } + + ret = mmcsd_spislotinitialize(state->minor, state->slotno, spi); + if (ret < 0) + { + mcerr("ERROR: Failed to bind SPI port %d to SD slot %d\n", + state->spidev, state->slotno); + return ret; + } + + /* Initialize Card Detect pin and enable interrupt on edges */ + + stm32_configgpio(state->cdcfg); + stm32_gpiosetevent(state->cdcfg, true, true, true, state->handler, NULL); + + state->cd = stm32_cardinserted_internal(state); + if (state->callback) + { + state->callback(state->cbarg); + } + +#ifdef HAVE_AUTOMOUNTER + /* Let the automounter know about the insertion event */ + + stm32_automount_event(state->slotno, stm32_cardinserted(state->slotno)); +#endif + + mcinfo("INFO: mmcsd%d card has been initialized successfully\n", + state->minor); + return OK; +} + +/**************************************************************************** + * Public Function + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_mmcsd_initialize + * + * Description: + * Initialize the MMCSD device. + * + * Returned Value: + * Zero is returned on success. Otherwise, a negated errno value is + * returned to indicate the nature of the failure. + * + ****************************************************************************/ + +int stm32_mmcsd_initialize(void) +{ + int ret; + +#ifdef CONFIG_CLICKER2_STM32_MB1_MMCSD + finfo("Configuring MMCSD on mikroBUS1\n"); + + ret = stm32_mmcsd_setup(&g_mb1_mmcsd); + if (ret < 0) + { + mcerr("ERROR: Failed to initialize MMCSD on mikroBus1: %d\n", ret); + } +#endif + +#ifdef CONFIG_CLICKER2_STM32_MB2_MMCSD + finfo("Configuring MMCSD on mikroBUS2\n"); + ret = stm32_mmcsd_setup(&g_mb2_mmcsd); + if (ret < 0) + { + mcerr("ERROR: Failed to initialize MMCSD on mikroBus2: %d\n", ret); + } +#endif + + UNUSED(ret); + return OK; +} + +/**************************************************************************** + * Name: stm32_cardinserted + * + * Description: + * Check if a card is inserted into the selected MMCSD slot + * + ****************************************************************************/ + +bool stm32_cardinserted(int slotno) +{ + struct stm32_mmcsd_state_s *state; + + /* Get the MMCSD description */ + +#ifdef CONFIG_CLICKER2_STM32_MB1_MMCSD + if (slotno == g_mb1_mmcsd.slotno) + { + state = &g_mb1_mmcsd; + } +#endif +#ifdef CONFIG_CLICKER2_STM32_MB2_MMCSD + + if (slotno == g_mb2_mmcsd.slotno) + { + state = &g_mb2_mmcsd; + } +#endif + + if (!state) + { + ferr("ERROR: No state for slotno %d\n", slotno); + return false; + } + + /* Return the state of the CD pin */ + + return stm32_cardinserted_internal(state); +} + +/**************************************************************************** + * Name: stm32_spi2register + * + * Description: + * Registers media change callback + ****************************************************************************/ + +int stm32_spi2register(struct spi_dev_s *dev, spi_mediachange_t callback, + void *arg) +{ + spiinfo("INFO: Registering spi2 device\n"); +#ifdef CONFIG_CLICKER2_STM32_MB2_MMCSD + g_mb2_mmcsd.callback = callback; + g_mb2_mmcsd.cbarg = arg; +#endif + return OK; +} + +/**************************************************************************** + * Name: stm32_spi3register + * + * Description: + * Registers media change callback + ****************************************************************************/ + +int stm32_spi3register(struct spi_dev_s *dev, spi_mediachange_t callback, + void *arg) +{ + spiinfo("INFO: Registering spi3 device\n"); +#ifdef CONFIG_CLICKER2_STM32_MB1_MMCSD + g_mb1_mmcsd.callback = callback; + g_mb1_mmcsd.cbarg = arg; +#endif + return OK; +} + +#endif /* CONFIG_MMCSD_SPI */ diff --git a/boards/arm/stm32f4/clicker2-stm32/src/stm32_mrf24j40.c b/boards/arm/stm32f4/clicker2-stm32/src/stm32_mrf24j40.c new file mode 100644 index 0000000000000..ecd813fb9a5fc --- /dev/null +++ b/boards/arm/stm32f4/clicker2-stm32/src/stm32_mrf24j40.c @@ -0,0 +1,328 @@ +/**************************************************************************** + * boards/arm/stm32f4/clicker2-stm32/src/stm32_mrf24j40.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include "stm32_gpio.h" +#include "stm32_exti.h" +#include "stm32_spi.h" + +#include "clicker2-stm32.h" + +#ifdef CONFIG_IEEE802154_MRF24J40 + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifndef CONFIG_DRIVERS_WIRELESS +# error Wireless support requires CONFIG_DRIVERS_WIRELESS +#endif + +#if !defined(CONFIG_CLICKER2_STM32_MB1_BEE) && \ + !defined(CONFIG_CLICKER2_STM32_MB2_BEE) +# error Only the Mikroe BEE board is supported +#endif + +#ifdef CONFIG_CLICKER2_STM32_MB1_BEE +# ifndef CONFIG_STM32_SPI3 +# error Mikroe BEE on mikroBUS1 requires CONFIG_STM32_SPI3 +# endif +#endif + +#ifdef CONFIG_CLICKER2_STM32_MB2_BEE +# ifndef CONFIG_STM32_SPI2 +# error Mikroe BEE on mikroBUS1 requires CONFIG_STM32_SPI2 +# endif +#endif + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +struct stm32_priv_s +{ + struct mrf24j40_lower_s dev; + xcpt_t handler; + void *arg; + uint32_t intcfg; + uint8_t spidev; +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/* IRQ/GPIO access callbacks. These operations all hidden behind callbacks + * to isolate the MRF24J40 driver from differences in GPIO interrupt handling + * varying boards and MCUs. + * + * irq_attach - Attach the MRF24J40 interrupt handler to the GPIO + * interrupt + * irq_enable - Enable or disable the GPIO interrupt + */ + +static int stm32_attach_irq(const struct mrf24j40_lower_s *lower, + xcpt_t handler, void *arg); +static void stm32_enable_irq(const struct mrf24j40_lower_s *lower, + bool state); +static int stm32_mrf24j40_devsetup(struct stm32_priv_s *priv); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* A reference to a structure of this type must be passed to the MRF24J40 + * driver. This structure provides information about the configuration + * of the MRF24J40 and provides some board-specific hooks. + * + * Memory for this structure is provided by the caller. It is not copied + * by the driver and is presumed to persist while the driver is active. The + * memory must be writable because, under certain circumstances, the driver + * may modify frequency or X plate resistance values. + */ + +#ifdef CONFIG_CLICKER2_STM32_MB1_BEE +static struct stm32_priv_s g_mrf24j40_mb1_priv = +{ + .dev.attach = stm32_attach_irq, + .dev.enable = stm32_enable_irq, + .handler = NULL, + .arg = NULL, + .intcfg = GPIO_MB1_INT, + .spidev = 3, +}; +#endif + +#ifdef CONFIG_CLICKER2_STM32_MB2_BEE +static struct stm32_priv_s g_mrf24j40_mb2_priv = +{ + .dev.attach = stm32_attach_irq, + .dev.enable = stm32_enable_irq, + .handler = NULL, + .arg = NULL, + .intcfg = GPIO_MB2_INT, + .spidev = 2, +}; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/* IRQ/GPIO access callbacks. These operations all hidden behind + * callbacks to isolate the MRF24J40 driver from differences in GPIO + * interrupt handling by varying boards and MCUs. If possible, + * interrupts should be configured on both rising and falling edges + * so that contact and loss-of-contact events can be detected. + * + * irq_attach - Attach the MRF24J40 interrupt handler to the GPIO + * interrupt + * irq_enable - Enable or disable the GPIO interrupt + */ + +static int stm32_attach_irq(const struct mrf24j40_lower_s *lower, + xcpt_t handler, void *arg) +{ + struct stm32_priv_s *priv = (struct stm32_priv_s *)lower; + + DEBUGASSERT(priv != NULL); + + /* Just save the handler for use when the interrupt is enabled */ + + priv->handler = handler; + priv->arg = arg; + return OK; +} + +static void stm32_enable_irq(const struct mrf24j40_lower_s *lower, + bool state) +{ + struct stm32_priv_s *priv = (struct stm32_priv_s *)lower; + + /* The caller should not attempt to enable interrupts if the handler + * has not yet been 'attached' + */ + + DEBUGASSERT(priv != NULL && (priv->handler != NULL || !state)); + +#ifdef CONFIG_CLICKER2_STM32_MRF24J40LH_VERBOSE + wlinfo("state:%d\n", (int)state); +#endif + + /* Attach and enable, or detach and disable */ + + if (state) + { + stm32_gpiosetevent(priv->intcfg, false, true, true, + priv->handler, priv->arg); + } + else + { + stm32_gpiosetevent(priv->intcfg, false, false, false, + NULL, NULL); + } +} + +/**************************************************************************** + * Name: stm32_mrf24j40_devsetup + * + * Description: + * Initialize one the MRF24J40 device in one mikroBUS slot + * + * Returned Value: + * Zero is returned on success. Otherwise, a negated errno value is + * returned to indicate the nature of the failure. + * + ****************************************************************************/ + +static int stm32_mrf24j40_devsetup(struct stm32_priv_s *priv) +{ + struct ieee802154_radio_s *radio; + MACHANDLE mac; + struct spi_dev_s *spi; + int ret; + + /* Configure the interrupt pin */ + + stm32_configgpio(priv->intcfg); + + /* Initialize the SPI bus and get an instance of the SPI interface */ + + spi = stm32_spibus_initialize(priv->spidev); + if (spi == NULL) + { + wlerr("ERROR: Failed to initialize SPI bus %d\n", priv->spidev); + return -ENODEV; + } + + /* Initialize and register the SPI MRF24J40 device */ + + radio = mrf24j40_init(spi, &priv->dev); + if (radio == NULL) + { + wlerr("ERROR: Failed to initialize SPI bus %d\n", priv->spidev); + return -ENODEV; + } + + /* Create a 802.15.4 MAC device from a 802.15.4 compatible radio device. */ + + mac = mac802154_create(radio); + if (mac == NULL) + { + wlerr("ERROR: Failed to initialize IEEE802.15.4 MAC\n"); + return -ENODEV; + } + +#ifdef CONFIG_IEEE802154_NETDEV + /* Use the IEEE802.15.4 MAC interface instance to create a 6LoWPAN + * network interface by wrapping the MAC interface instance in a + * network device driver via mac802154dev_register(). + */ + + ret = mac802154netdev_register(mac); + if (ret < 0) + { + wlerr("ERROR: Failed to register the MAC network driver wpan%d: %d\n", + 0, ret); + return ret; + } +#endif + +#ifdef CONFIG_IEEE802154_MACDEV + /* If want to call these APIs from userspace, you have to wrap the MAC + * interface in a character device viamac802154dev_register(). + */ + + ret = mac802154dev_register(mac, 0); + if (ret < 0) + { + wlerr("ERROR:"); + wlerr(" Failed to register the MAC character driver /dev/ieee%d: %d\n", + 0, ret); + return ret; + } +#endif + + UNUSED(ret); + return OK; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_mrf24j40_initialize + * + * Description: + * Initialize the MRF24J40 device. + * + * Returned Value: + * Zero is returned on success. Otherwise, a negated errno value is + * returned to indicate the nature of the failure. + * + ****************************************************************************/ + +int stm32_mrf24j40_initialize(void) +{ + int ret; + +#ifdef CONFIG_CLICKER2_STM32_MB1_BEE + wlinfo("Configuring BEE in mikroBUS1\n"); + + ret = stm32_mrf24j40_devsetup(&g_mrf24j40_mb1_priv); + if (ret < 0) + { + wlerr("ERROR: Failed to initialize BD in mikroBUS1: %d\n", ret); + } +#endif + +#ifdef CONFIG_CLICKER2_STM32_MB2_BEE + wlinfo("Configuring BEE in mikroBUS2\n"); + + ret = stm32_mrf24j40_devsetup(&g_mrf24j40_mb2_priv); + if (ret < 0) + { + wlerr("ERROR: Failed to initialize BD in mikroBUS2: %d\n", ret); + } +#endif + + UNUSED(ret); + return OK; +} +#endif /* CONFIG_IEEE802154_MRF24J40 */ diff --git a/boards/arm/stm32f4/clicker2-stm32/src/stm32_spi.c b/boards/arm/stm32f4/clicker2-stm32/src/stm32_spi.c new file mode 100644 index 0000000000000..3e631a3b6a33c --- /dev/null +++ b/boards/arm/stm32f4/clicker2-stm32/src/stm32_spi.c @@ -0,0 +1,268 @@ +/**************************************************************************** + * boards/arm/stm32f4/clicker2-stm32/src/stm32_spi.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include + +#include "arm_internal.h" +#include "chip.h" +#include "stm32.h" + +#include "clicker2-stm32.h" + +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || defined(CONFIG_STM32_SPI3) + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_spidev_initialize + * + * Description: + * Called to configure SPI chip select GPIO pins for the Mikroe Clicker2 + * STM32 board. + * + ****************************************************************************/ + +void weak_function stm32_spidev_initialize(void) +{ +#if defined(CONFIG_STM32_SPI3) && defined(CONFIG_CLICKER2_STM32_MB1_SPI) + /* Enable chip select for mikroBUS1 */ + + stm32_configgpio(GPIO_MB1_CS); +#endif +#if defined(CONFIG_STM32_SPI2) && defined(CONFIG_CLICKER2_STM32_MB2_SPI) + /* Enable chip select for mikroBUS2 */ + + stm32_configgpio(GPIO_MB2_CS); +#endif +} + +/**************************************************************************** + * Name: stm32_spi1/2/3select and stm32_spi1/2/3status + * + * Description: + * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status + * must be provided by board-specific logic. They are implementations of + * the select and status methods of the SPI interface defined by struct + * spi_ops_s (see include/nuttx/spi/spi.h). All other methods + * (including stm32_spibus_initialize()) are provided by common STM32 + * logic. To use this common SPI logic on your board: + * + * 1. Provide logic in stm32_boardinitialize() to configure SPI chip select + * pins. + * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() functions + * in your board-specific logic. These functions will perform chip + * selection and status operations using GPIOs in the way your board is + * configured. + * 3. Add a calls to stm32_spibus_initialize() in your low level + * application initialization logic + * 4. The handle returned by stm32_spibus_initialize() may then be used to + * bind the SPI driver to higher level logic (e.g., calling + * mmcsd_spislotinitialize(), for example, will bind the SPI driver to + * the SPI MMC/SD driver). + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_SPI1 +void stm32_spi1select(struct spi_dev_s *dev, + uint32_t devid, bool selected) +{ + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); +} + +uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} +#endif + +#ifdef CONFIG_STM32_SPI2 +void stm32_spi2select(struct spi_dev_s *dev, + uint32_t devid, bool selected) +{ + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); + + switch (devid) + { +#ifdef CONFIG_IEEE802154_MRF24J40 + case SPIDEV_IEEE802154(0): + + /* Set the GPIO low to select and high to de-select */ + + stm32_gpiowrite(GPIO_MB2_CS, !selected); + break; +#endif +#ifdef CONFIG_IEEE802154_XBEE + case SPIDEV_IEEE802154(0): + + /* Set the GPIO low to select and high to de-select */ + + stm32_gpiowrite(GPIO_MB2_CS, !selected); + break; +#endif +#ifdef CONFIG_MMCSD_SPI + case SPIDEV_MMCSD(0): + + /* Set the GPIO low to select and high to de-select */ + + stm32_gpiowrite(GPIO_MB2_CS, !selected); + break; +#endif + default: + break; + } +} + +uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) +{ + uint8_t status = 0; + +#ifdef CONFIG_CLICKER2_STM32_MB2_MMCSD + if (devid == SPIDEV_MMCSD(0)) + { + status = stm32_cardinserted(MB2_MMCSD_SLOTNO); + } +#endif + + return status; +} +#endif + +#ifdef CONFIG_STM32_SPI3 +void stm32_spi3select(struct spi_dev_s *dev, + uint32_t devid, bool selected) +{ + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); + + switch (devid) + { +#ifdef CONFIG_IEEE802154_MRF24J40 + case SPIDEV_IEEE802154(0): + + /* Set the GPIO low to select and high to de-select */ + + stm32_gpiowrite(GPIO_MB1_CS, !selected); + break; +#endif +#ifdef CONFIG_IEEE802154_XBEE + case SPIDEV_IEEE802154(0): + + /* Set the GPIO low to select and high to de-select */ + + stm32_gpiowrite(GPIO_MB1_CS, !selected); + break; +#endif +#ifdef CONFIG_MMCSD_SPI + case SPIDEV_MMCSD(0): + + /* Set the GPIO low to select and high to de-select */ + + stm32_gpiowrite(GPIO_MB1_CS, !selected); + break; +#endif + default: + break; + } +} + +uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid) +{ + uint8_t status = 0; + +#ifdef CONFIG_CLICKER2_STM32_MB1_MMCSD + if (devid == SPIDEV_MMCSD(0)) + { + status |= stm32_cardinserted(MB1_MMCSD_SLOTNO); + } +#endif + + return status; +} +#endif + +/**************************************************************************** + * Name: stm32_spi1cmddata + * + * Description: + * Set or clear the SH1101A A0 or SD1306 D/C n bit to select data (true) + * or command (false). This function must be provided by platform-specific + * logic. This is an implementation of the cmddata method of the SPI + * interface defined by struct spi_ops_s (see include/nuttx/spi/spi.h). + * + * Input Parameters: + * + * spi - SPI device that controls the bus the device that requires the CMD/ + * DATA selection. + * devid - If there are multiple devices on the bus, this selects which one + * to select cmd or data. NOTE: This design restricts, for example, + * one one SPI display per SPI bus. + * cmd - true: select command; false: select data + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_SPI_CMDDATA +#ifdef CONFIG_STM32_SPI1 +int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) +{ + return -ENODEV; +} +#endif + +#ifdef CONFIG_STM32_SPI2 +int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) +{ + /* To be provided */ + + return -ENODEV; +} +#endif + +#ifdef CONFIG_STM32_SPI3 +int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) +{ + /* To be provided */ + + return -ENODEV; +} +#endif +#endif /* CONFIG_SPI_CMDDATA */ + +#endif /* CONFIG_STM32_SPI1 || CONFIG_STM32_SPI2 */ diff --git a/boards/arm/stm32f4/clicker2-stm32/src/stm32_usb.c b/boards/arm/stm32f4/clicker2-stm32/src/stm32_usb.c new file mode 100644 index 0000000000000..6c32c09880b88 --- /dev/null +++ b/boards/arm/stm32f4/clicker2-stm32/src/stm32_usb.c @@ -0,0 +1,96 @@ +/**************************************************************************** + * boards/arm/stm32f4/clicker2-stm32/src/stm32_usb.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include "stm32_otgfs.h" +#include "stm32_gpio.h" +#include "clicker2-stm32.h" + +#ifdef CONFIG_STM32_OTGFS + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifdef CONFIG_USBDEV +# define HAVE_USB 1 +#else +# warning "CONFIG_STM32_OTGFS is enabled but CONFIG_USBDEV is not" +# undef HAVE_USB +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_usb_configure + * + * Description: + * Called from stm32_boardinitialize very early in initialization to setup + * USB-related GPIO pins for the Olimex STM32 P407 board. + * + ****************************************************************************/ + +void stm32_usb_configure(void) +{ +#ifdef CONFIG_STM32_OTGFS + /* The OTG FS has an internal soft pull-up. + * No GPIO configuration is required + */ + + /* Configure the OTG FS VBUS sensing GPIO */ + + stm32_configgpio(GPIO_OTGFS_VBUS); +#endif +} + +/**************************************************************************** + * Name: stm32_usbsuspend + * + * Description: + * Board logic must provide the stm32_usbsuspend logic if the USBDEV + * driver is used. This function is called whenever the USB enters or + * leaves suspend mode. + * This is an opportunity for the board logic to shutdown clocks, power, + * etc. while the USB is suspended. + * + ****************************************************************************/ + +#ifdef CONFIG_USBDEV +void stm32_usbsuspend(struct usbdev_s *dev, bool resume) +{ + uinfo("resume: %d\n", resume); +} +#endif + +#endif /* CONFIG_STM32_OTGFS */ diff --git a/boards/arm/stm32f4/clicker2-stm32/src/stm32_userleds.c b/boards/arm/stm32f4/clicker2-stm32/src/stm32_userleds.c new file mode 100644 index 0000000000000..4d9f9190137d9 --- /dev/null +++ b/boards/arm/stm32f4/clicker2-stm32/src/stm32_userleds.c @@ -0,0 +1,89 @@ +/**************************************************************************** + * boards/arm/stm32f4/clicker2-stm32/src/stm32_userleds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include "stm32.h" +#include "clicker2-stm32.h" + +#ifndef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_userled_initialize + ****************************************************************************/ + +uint32_t board_userled_initialize(void) +{ + /* Configure LED1-2 GPIOs for output */ + + stm32_configgpio(GPIO_LED1); + stm32_configgpio(GPIO_LED2); + return BOARD_NLEDS; +} + +/**************************************************************************** + * Name: board_userled + ****************************************************************************/ + +void board_userled(int led, bool ledon) +{ + gpioconfig_t ledcfg; + + if (led == BOARD_LED1) + { + ledcfg = GPIO_LED1; + } + else if (led == BOARD_LED2) + { + ledcfg = GPIO_LED2; + } + else + { + return; + } + + stm32_gpiowrite(ledcfg, true); +} + +/**************************************************************************** + * Name: board_userled_all + ****************************************************************************/ + +void board_userled_all(uint32_t ledset) +{ + stm32_gpiowrite(GPIO_LED1, (ledset & BOARD_LED1_BIT) != 0); + stm32_gpiowrite(GPIO_LED2, (ledset & BOARD_LED2_BIT) != 0); +} + +#endif /* !CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/clicker2-stm32/src/stm32_xbee.c b/boards/arm/stm32f4/clicker2-stm32/src/stm32_xbee.c similarity index 99% rename from boards/arm/stm32/clicker2-stm32/src/stm32_xbee.c rename to boards/arm/stm32f4/clicker2-stm32/src/stm32_xbee.c index c5bd9cafb82cb..8aef55384ca8d 100644 --- a/boards/arm/stm32/clicker2-stm32/src/stm32_xbee.c +++ b/boards/arm/stm32f4/clicker2-stm32/src/stm32_xbee.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/clicker2-stm32/src/stm32_xbee.c + * boards/arm/stm32f4/clicker2-stm32/src/stm32_xbee.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f4/common/CMakeLists.txt b/boards/arm/stm32f4/common/CMakeLists.txt new file mode 100644 index 0000000000000..c0b10dbf603f3 --- /dev/null +++ b/boards/arm/stm32f4/common/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32f4/common/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(${NUTTX_DIR}/boards/arm/common/stm32 stm32_common) diff --git a/boards/arm/stm32f4/common/Kconfig b/boards/arm/stm32f4/common/Kconfig new file mode 100644 index 0000000000000..5c48f62a0258b --- /dev/null +++ b/boards/arm/stm32f4/common/Kconfig @@ -0,0 +1,6 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# + +source "boards/arm/common/stm32/Kconfig" diff --git a/boards/arm/stm32f4/common/Makefile b/boards/arm/stm32f4/common/Makefile new file mode 100644 index 0000000000000..cb4984cccea4d --- /dev/null +++ b/boards/arm/stm32f4/common/Makefile @@ -0,0 +1,39 @@ +############################################################################# +# boards/arm/stm32f4/common/Makefile +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################# + +include $(TOPDIR)/Make.defs + +STM32_BOARD_COMMON_DIR := $(TOPDIR)$(DELIM)boards$(DELIM)arm$(DELIM)common$(DELIM)stm32 +STM32_COMMON_SRCDIR := $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)common$(DELIM)stm32 + +include board/Make.defs +include $(STM32_BOARD_COMMON_DIR)$(DELIM)src$(DELIM)Make.defs + +DEPPATH += --dep-path board + +include $(TOPDIR)/boards/Board.mk + +ARCHSRCDIR = $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src +BOARDDIR = $(ARCHSRCDIR)$(DELIM)board +CFLAGS += ${INCDIR_PREFIX}$(BOARDDIR)$(DELIM)include +CFLAGS += ${INCDIR_PREFIX}$(STM32_COMMON_SRCDIR) +CXXFLAGS += ${INCDIR_PREFIX}$(STM32_COMMON_SRCDIR) diff --git a/boards/arm/stm32f4/mikroe-stm32f4/CMakeLists.txt b/boards/arm/stm32f4/mikroe-stm32f4/CMakeLists.txt new file mode 100644 index 0000000000000..ea2ce2c8f04c7 --- /dev/null +++ b/boards/arm/stm32f4/mikroe-stm32f4/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32f4/mikroe-stm32f4/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/arm/stm32/mikroe-stm32f4/Kconfig b/boards/arm/stm32f4/mikroe-stm32f4/Kconfig similarity index 100% rename from boards/arm/stm32/mikroe-stm32f4/Kconfig rename to boards/arm/stm32f4/mikroe-stm32f4/Kconfig diff --git a/boards/arm/stm32f4/mikroe-stm32f4/configs/fulldemo/defconfig b/boards/arm/stm32f4/mikroe-stm32f4/configs/fulldemo/defconfig new file mode 100644 index 0000000000000..b72204cedca5f --- /dev/null +++ b/boards/arm/stm32f4/mikroe-stm32f4/configs/fulldemo/defconfig @@ -0,0 +1,137 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_DEV_CONSOLE is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_NXFONTS_DISABLE_16BPP is not set +# CONFIG_NXPLAYER_INCLUDE_PREFERRED_DEVICE is not set +# CONFIG_NXTK_DEFAULT_BORDERCOLORS is not set +# CONFIG_NX_DISABLE_16BPP is not set +# CONFIG_SPI_CALLBACK is not set +# CONFIG_STM32_CCMEXCLUDE is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="mikroe-stm32f4" +CONFIG_ARCH_BOARD_MIKROE_STM32F4=y +CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F407VG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_AUDIO=y +CONFIG_AUDIO_FORMAT_MIDI=y +CONFIG_AUDIO_VS1053=y +CONFIG_BOARDCTL_USBDEVCTRL=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_CDCACM=y +CONFIG_CDCACM_CONSOLE=y +CONFIG_CDCACM_RXBUFSIZE=256 +CONFIG_CDCACM_TXBUFSIZE=256 +CONFIG_DEBUG_SYMBOLS=y +CONFIG_DEV_LOOP=y +CONFIG_DRIVERS_AUDIO=y +CONFIG_ETC_FATDEVNO=0 +CONFIG_ETC_ROMFS=y +CONFIG_EXAMPLES_NX=y +CONFIG_EXAMPLES_NX_BPP=16 +CONFIG_EXAMPLES_TOUCHSCREEN=y +CONFIG_FS_BINFS=y +CONFIG_FS_FAT=y +CONFIG_FS_ROMFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_INIT_ENTRYPOINT="nxwm_main" +CONFIG_INPUT=y +CONFIG_INTELHEX_BINARY=y +CONFIG_LCD=y +CONFIG_LCD_MIO283QT2=y +CONFIG_LIBC_MAX_EXITFUNS=4 +CONFIG_LIBC_PERROR_STDOUT=y +CONFIG_LIBC_STRERROR=y +CONFIG_LINE_MAX=64 +CONFIG_M25P_MANUFACTURER=0x1C +CONFIG_M25P_MEMORY_TYPE=0x31 +CONFIG_M25P_SUBSECTOR_ERASE=y +CONFIG_MIKROE_FLASH=y +CONFIG_MIKROE_FLASH_PART=y +CONFIG_MMCSD=y +CONFIG_MMCSD_SPICLOCK=30000000 +CONFIG_MM_REGIONS=2 +CONFIG_MQ_MAXMSGSIZE=64 +CONFIG_MTD_CONFIG=y +CONFIG_MTD_PARTITION=y +CONFIG_MTD_SMART_SECTOR_SIZE=512 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_NSH_STRERROR=y +CONFIG_NX=y +CONFIG_NXFONT_SANS17X23B=y +CONFIG_NXFONT_SANS20X27B=y +CONFIG_NXFONT_SANS22X29B=y +CONFIG_NXFONT_SANS28X37B=y +CONFIG_NXFONT_SERIF22X28B=y +CONFIG_NXPLAYER_DEFAULT_MEDIADIR="/usr/sounds" +CONFIG_NXPLAYER_INCLUDE_SYSTEM_RESET=y +CONFIG_NXTERM=y +CONFIG_NXTERM_CURSORCHAR=95 +CONFIG_NXTK_BORDERCOLOR1=0x8410 +CONFIG_NXTK_BORDERCOLOR2=0x4208 +CONFIG_NXTK_BORDERCOLOR3=0xc618 +CONFIG_NXTK_BORDERWIDTH=3 +CONFIG_NXWIDGETS=y +CONFIG_NXWIDGETS_BPP=16 +CONFIG_NXWIDGETS_SIZEOFCHAR=1 +CONFIG_NXWM=y +CONFIG_NXWM_BACKGROUND_IMAGE="" +CONFIG_NXWM_HEXCALCULATOR_BACKGROUNDCOLOR=0x39C7 +CONFIG_NXWM_HEXCALCULATOR_CUSTOM_COLORS=y +CONFIG_NXWM_KEYBOARD=y +CONFIG_NXWM_KEYBOARD_DEVPATH="/dev/ttyS0" +CONFIG_NXWM_KEYBOARD_LISTENERPRIO=100 +CONFIG_NXWM_MEDIAPLAYER=y +CONFIG_NXWM_TASKBAR_LEFT=y +CONFIG_NXWM_TOUCHSCREEN_CONFIGDATA=y +CONFIG_NXWM_TOUCHSCREEN_LISTENERPRIO=100 +CONFIG_NX_BLOCKING=y +CONFIG_NX_KBD=y +CONFIG_NX_XYINPUT_TOUCHSCREEN=y +CONFIG_PLATFORM_CONFIGDATA=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAMMTD=y +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_RTC_ALARM=y +CONFIG_RTC_DATETIME=y +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=192 +CONFIG_SCHED_WAITPID=y +CONFIG_STM32_ADC2=y +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_DMA1=y +CONFIG_STM32_FLASH_PREFETCH=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PWR=y +CONFIG_STM32_RNG=y +CONFIG_STM32_RTC=y +CONFIG_STM32_SPI2=y +CONFIG_STM32_TIM1=y +CONFIG_STM32_USART2=y +CONFIG_SYSLOG_CHAR=y +CONFIG_SYSLOG_DEVPATH="/dev/ttyS0" +CONFIG_SYSTEM_FLASH_ERASEALL=y +CONFIG_SYSTEM_NSH=y +CONFIG_SYSTEM_NXPLAYER=y +CONFIG_TASK_NAME_SIZE=11 +CONFIG_USBDEV=y diff --git a/boards/arm/stm32f4/mikroe-stm32f4/configs/kostest/defconfig b/boards/arm/stm32f4/mikroe-stm32f4/configs/kostest/defconfig new file mode 100644 index 0000000000000..1c3eb8c59df96 --- /dev/null +++ b/boards/arm/stm32f4/mikroe-stm32f4/configs/kostest/defconfig @@ -0,0 +1,84 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_DEV_CONSOLE is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_SPI_CALLBACK is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="mikroe-stm32f4" +CONFIG_ARCH_BOARD_MIKROE_STM32F4=y +CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F407VG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_ARM_MPU=y +CONFIG_BOARDCTL_USBDEVCTRL=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILD_PROTECTED=y +CONFIG_CDCACM=y +CONFIG_CDCACM_CONSOLE=y +CONFIG_CDCACM_RXBUFSIZE=256 +CONFIG_CDCACM_TXBUFSIZE=256 +CONFIG_DEBUG_SYMBOLS=y +CONFIG_DEV_LOOP=y +CONFIG_FS_FAT=y +CONFIG_FS_ROMFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_INIT_ENTRYPOINT="ostest_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_MAX_EXITFUNS=4 +CONFIG_LIBC_PERROR_STDOUT=y +CONFIG_LIBC_STRERROR=y +CONFIG_LINE_MAX=64 +CONFIG_M25P_MANUFACTURER=0x1C +CONFIG_M25P_MEMORY_TYPE=0x31 +CONFIG_M25P_SUBSECTOR_ERASE=y +CONFIG_MIKROE_FLASH=y +CONFIG_MIKROE_FLASH_PART=y +CONFIG_MIKROE_FLASH_PART_LIST="256,768" +CONFIG_MMCSD=y +CONFIG_MM_REGIONS=2 +CONFIG_MTD_PARTITION=y +CONFIG_MTD_SMART_SECTOR_SIZE=512 +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_NSH_STRERROR=y +CONFIG_NUTTX_USERSPACE=0x08020000 +CONFIG_PASS1_BUILDIR="boards/arm/stm32f4/mikroe-stm32f4/kernel" +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAMMTD=y +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_RTC_ALARM=y +CONFIG_RTC_DATETIME=y +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=192 +CONFIG_SCHED_WAITPID=y +CONFIG_STM32_ADC2=y +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_FLASH_PREFETCH=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PWR=y +CONFIG_STM32_RNG=y +CONFIG_STM32_RTC=y +CONFIG_STM32_SPI2=y +CONFIG_STM32_TIM1=y +CONFIG_STM32_USART2=y +CONFIG_SYSLOG_CHAR=y +CONFIG_SYSLOG_DEVPATH="/dev/ttyS0" +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=11 +CONFIG_TESTING_OSTEST=y +CONFIG_USBDEV=y diff --git a/boards/arm/stm32f4/mikroe-stm32f4/configs/nsh/defconfig b/boards/arm/stm32f4/mikroe-stm32f4/configs/nsh/defconfig new file mode 100644 index 0000000000000..b1dfc76caa8f1 --- /dev/null +++ b/boards/arm/stm32f4/mikroe-stm32f4/configs/nsh/defconfig @@ -0,0 +1,70 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_DEV_CONSOLE is not set +# CONFIG_DISABLE_OS_API is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_SPI_CALLBACK is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="mikroe-stm32f4" +CONFIG_ARCH_BOARD_MIKROE_STM32F4=y +CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F407VG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_DEV_LOOP=y +CONFIG_FS_FAT=y +CONFIG_FS_ROMFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_PERROR_STDOUT=y +CONFIG_LIBC_STRERROR=y +CONFIG_LINE_MAX=64 +CONFIG_M25P_MANUFACTURER=0x1C +CONFIG_M25P_MEMORY_TYPE=0x31 +CONFIG_M25P_SUBSECTOR_ERASE=y +CONFIG_MIKROE_FLASH=y +CONFIG_MIKROE_FLASH_PART=y +CONFIG_MIKROE_FLASH_PART_LIST="256,768" +CONFIG_MMCSD=y +CONFIG_MM_REGIONS=2 +CONFIG_MTD_PARTITION=y +CONFIG_MTD_SMART_SECTOR_SIZE=512 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_NSH_STRERROR=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAMMTD=y +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=27 +CONFIG_START_YEAR=2013 +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_PWR=y +CONFIG_STM32_RNG=y +CONFIG_STM32_SPI2=y +CONFIG_STM32_USART2=y +CONFIG_SYSLOG_CHAR=y +CONFIG_SYSLOG_DEVPATH="/dev/ttyS0" +CONFIG_SYSTEM_FLASH_ERASEALL=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f4/mikroe-stm32f4/configs/nx/defconfig b/boards/arm/stm32f4/mikroe-stm32f4/configs/nx/defconfig new file mode 100644 index 0000000000000..000e9a61f2990 --- /dev/null +++ b/boards/arm/stm32f4/mikroe-stm32f4/configs/nx/defconfig @@ -0,0 +1,66 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_DEV_CONSOLE is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_NXFONTS_DISABLE_16BPP is not set +# CONFIG_NXTK_DEFAULT_BORDERCOLORS is not set +# CONFIG_NX_DISABLE_16BPP is not set +# CONFIG_SERIAL is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="mikroe-stm32f4" +CONFIG_ARCH_BOARD_MIKROE_STM32F4=y +CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F407VG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_EXAMPLES_NX=y +CONFIG_EXAMPLES_NX_BPP=16 +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_INIT_ENTRYPOINT="nx_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LCD=y +CONFIG_LCD_MIO283QT2=y +CONFIG_LIBC_PERROR_STDOUT=y +CONFIG_LIBC_STRERROR=y +CONFIG_LINE_MAX=64 +CONFIG_MM_REGIONS=2 +CONFIG_MQ_MAXMSGSIZE=64 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_LIBRARY=y +CONFIG_NSH_READLINE=y +CONFIG_NSH_STRERROR=y +CONFIG_NX=y +CONFIG_NXFONT_SERIF22X28B=y +CONFIG_NXTK_BORDERCOLOR1=0x8410 +CONFIG_NXTK_BORDERCOLOR2=0x4208 +CONFIG_NXTK_BORDERCOLOR3=0xc618 +CONFIG_NXTK_BORDERWIDTH=3 +CONFIG_NX_BLOCKING=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=27 +CONFIG_START_YEAR=2013 +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_PWR=y +CONFIG_SYSLOG_CHAR=y +CONFIG_SYSLOG_DEVPATH="/dev/ttyS0" +CONFIG_TASK_NAME_SIZE=0 diff --git a/boards/arm/stm32f4/mikroe-stm32f4/configs/nxlines/defconfig b/boards/arm/stm32f4/mikroe-stm32f4/configs/nxlines/defconfig new file mode 100644 index 0000000000000..c67e2e80f97fc --- /dev/null +++ b/boards/arm/stm32f4/mikroe-stm32f4/configs/nxlines/defconfig @@ -0,0 +1,70 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_DEV_CONSOLE is not set +# CONFIG_EXAMPLES_NXLINES_DEFAULT_COLORS is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_NXFONTS_DISABLE_16BPP is not set +# CONFIG_NXTK_DEFAULT_BORDERCOLORS is not set +# CONFIG_NX_DISABLE_16BPP is not set +# CONFIG_NX_WRITEONLY is not set +# CONFIG_SERIAL is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="mikroe-stm32f4" +CONFIG_ARCH_BOARD_MIKROE_STM32F4=y +CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F407VG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_EXAMPLES_NXLINES=y +CONFIG_EXAMPLES_NXLINES_BGCOLOR=0x0 +CONFIG_EXAMPLES_NXLINES_BORDERCOLOR=0xFFE0 +CONFIG_EXAMPLES_NXLINES_BPP=16 +CONFIG_EXAMPLES_NXLINES_CIRCLECOLOR=0x87F0 +CONFIG_EXAMPLES_NXLINES_LINECOLOR=0x861F +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_INIT_ENTRYPOINT="nxlines_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LCD=y +CONFIG_LCD_MIO283QT2=y +CONFIG_LCD_NOGETRUN=y +CONFIG_LINE_MAX=64 +CONFIG_MM_REGIONS=2 +CONFIG_MQ_MAXMSGSIZE=64 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_LIBRARY=y +CONFIG_NSH_READLINE=y +CONFIG_NX=y +CONFIG_NXFONT_SERIF22X28B=y +CONFIG_NXTK_BORDERCOLOR1=0x8410 +CONFIG_NXTK_BORDERCOLOR2=0x4208 +CONFIG_NXTK_BORDERCOLOR3=0xc618 +CONFIG_NXTK_BORDERWIDTH=3 +CONFIG_NX_BLOCKING=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=27 +CONFIG_START_YEAR=2013 +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_PWR=y +CONFIG_SYSLOG_CHAR=y +CONFIG_SYSLOG_DEVPATH="/dev/ttyS0" +CONFIG_TASK_NAME_SIZE=0 diff --git a/boards/arm/stm32f4/mikroe-stm32f4/configs/nxtext/defconfig b/boards/arm/stm32f4/mikroe-stm32f4/configs/nxtext/defconfig new file mode 100644 index 0000000000000..30d89a2cdffdb --- /dev/null +++ b/boards/arm/stm32f4/mikroe-stm32f4/configs/nxtext/defconfig @@ -0,0 +1,64 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_DEV_CONSOLE is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_NXFONTS_DISABLE_16BPP is not set +# CONFIG_NXTK_DEFAULT_BORDERCOLORS is not set +# CONFIG_NX_DISABLE_16BPP is not set +# CONFIG_SERIAL is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="mikroe-stm32f4" +CONFIG_ARCH_BOARD_MIKROE_STM32F4=y +CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F407VG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_EXAMPLES_NXTEXT=y +CONFIG_EXAMPLES_NXTEXT_BPP=16 +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_INIT_ENTRYPOINT="nxtext_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LCD=y +CONFIG_LCD_MIO283QT2=y +CONFIG_LINE_MAX=64 +CONFIG_MM_REGIONS=2 +CONFIG_MQ_MAXMSGSIZE=64 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_LIBRARY=y +CONFIG_NSH_READLINE=y +CONFIG_NX=y +CONFIG_NXFONT_SERIF22X28B=y +CONFIG_NXTK_BORDERCOLOR1=0x8410 +CONFIG_NXTK_BORDERCOLOR2=0x4208 +CONFIG_NXTK_BORDERCOLOR3=0xc618 +CONFIG_NXTK_BORDERWIDTH=3 +CONFIG_NX_BLOCKING=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=27 +CONFIG_START_YEAR=2013 +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_PWR=y +CONFIG_SYSLOG_CHAR=y +CONFIG_SYSLOG_DEVPATH="/dev/ttyS0" +CONFIG_TASK_NAME_SIZE=0 diff --git a/boards/arm/stm32f4/mikroe-stm32f4/configs/usbnsh/defconfig b/boards/arm/stm32f4/mikroe-stm32f4/configs/usbnsh/defconfig new file mode 100644 index 0000000000000..598b990801356 --- /dev/null +++ b/boards/arm/stm32f4/mikroe-stm32f4/configs/usbnsh/defconfig @@ -0,0 +1,75 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_DEV_CONSOLE is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_SPI_CALLBACK is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="mikroe-stm32f4" +CONFIG_ARCH_BOARD_MIKROE_STM32F4=y +CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F407VG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL_USBDEVCTRL=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_CDCACM=y +CONFIG_CDCACM_CONSOLE=y +CONFIG_CDCACM_RXBUFSIZE=256 +CONFIG_CDCACM_TXBUFSIZE=256 +CONFIG_DEV_LOOP=y +CONFIG_FS_FAT=y +CONFIG_FS_ROMFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_PERROR_STDOUT=y +CONFIG_LIBC_STRERROR=y +CONFIG_LINE_MAX=64 +CONFIG_M25P_MANUFACTURER=0x1C +CONFIG_M25P_MEMORY_TYPE=0x31 +CONFIG_M25P_SUBSECTOR_ERASE=y +CONFIG_MIKROE_FLASH=y +CONFIG_MIKROE_FLASH_PART=y +CONFIG_MIKROE_FLASH_PART_LIST="256,768" +CONFIG_MIKROE_RAMMTD=y +CONFIG_MMCSD=y +CONFIG_MM_REGIONS=2 +CONFIG_MTD_PARTITION=y +CONFIG_MTD_SMART_SECTOR_SIZE=512 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_NSH_STRERROR=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=27 +CONFIG_START_YEAR=2013 +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PWR=y +CONFIG_STM32_RNG=y +CONFIG_STM32_SPI2=y +CONFIG_STM32_USART2=y +CONFIG_SYSLOG_CHAR=y +CONFIG_SYSLOG_DEVPATH="/dev/ttyS0" +CONFIG_SYSTEM_FLASH_ERASEALL=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USBDEV=y diff --git a/boards/arm/stm32f4/mikroe-stm32f4/include/board.h b/boards/arm/stm32f4/mikroe-stm32f4/include/board.h new file mode 100644 index 0000000000000..8c6d5b2833ef7 --- /dev/null +++ b/boards/arm/stm32f4/mikroe-stm32f4/include/board.h @@ -0,0 +1,251 @@ +/**************************************************************************** + * boards/arm/stm32f4/mikroe-stm32f4/include/board.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_STM32_MIKROE_STM32F4_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32_MIKROE_STM32F4_INCLUDE_BOARD_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#ifndef __ASSEMBLY__ +# include +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Clocking *****************************************************************/ + +/* The Mikroe STM32F4 Mikromedia board features a single 32kHz crystal. + * The main clock uses the internal 16Mhz RC oscillator. + * + * This is the canonical configuration: + * System Clock source :PLL (HSE) + * SYSCLK(Hz) :168000000 Determined by PLL configuration + * HCLK(Hz) :168000000 (STM32_RCC_CFGR_HPRE) + * AHB Prescaler :1 (STM32_RCC_CFGR_HPRE) + * APB1 Prescaler :4 (STM32_RCC_CFGR_PPRE1) + * APB2 Prescaler :2 (STM32_RCC_CFGR_PPRE2) + * HSI Frequency(Hz) :16000000 (STM32_HSI_FREQUENCY) + * PLLM :16 (STM32_PLLCFG_PLLM) + * PLLN :36 (STM32_PLLCFG_PLLN) + * PLLP :2 (STM32_PLLCFG_PLLP) + * PLLQ :7 (STM32_PLLCFG_PLLQ) + * Main regulator output voltage :Scale1 mode Needed for high speed SYSCLK + * Flash Latency(WS) :5 + * Prefetch Buffer :OFF + * Instruction cache :ON + * Data cache :ON + * Require 48MHz for USB OTG FS, :Enabled + * SDIO and RNG clock + */ + +/* HSI - 16 MHz RC factory-trimmed + * LSI - 32 KHz RC + * HSE - On-board crystal frequency is 8MHz + * LSE - 32.768 kHz + */ + +#define STM32_BOARD_XTAL 8000000ul + +#define STM32_HSI_FREQUENCY 16000000ul +#define STM32_LSI_FREQUENCY 32000 +#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL +#define STM32_LSE_FREQUENCY 32768 + +/* Main PLL Configuration. + * + * PLL source is HSI + * PLL_VCO = (STM32_HSI_FREQUENCY / PLLM) * PLLN + * = (16,000,000 / 16) * 336 + * = 336,000,000 + * SYSCLK = PLL_VCO / PLLP + * = 336,000,000 / 2 = 168,000,000 + * USB OTG FS, SDIO and RNG Clock + * = PLL_VCO / PLLQ + * = 48,000,000 + */ + +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(16) +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(336) +#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_2 +#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(7) + +#define STM32_SYSCLK_FREQUENCY 168000000ul + +/* AHB clock (HCLK) is SYSCLK (168MHz) */ + +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY + +/* APB1 clock (PCLK1) is HCLK/4 (42MHz) */ + +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd4 /* PCLK1 = HCLK / 4 */ +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/4) + +/* Timers driven from APB1 will be twice PCLK1 */ + +#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) + +/* APB2 clock (PCLK2) is HCLK/2 (84MHz) */ + +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLKd2 /* PCLK2 = HCLK / 2 */ +#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/2) + +/* Timers driven from APB2 will be twice PCLK2 */ + +#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM9_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM10_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM11_CLKIN (2*STM32_PCLK2_FREQUENCY) + +/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx + * otherwise frequency is 2xAPBx. + * Note: TIM1,8 are on APB2, others on APB1 + */ + +#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM2_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM3_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM4_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM5_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM6_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM7_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY + +/* LED definitions **********************************************************/ + +/* If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs in + * any way. The following definitions are used to access individual LEDs. + */ + +/* LED index values for use with board_userled() */ + +#if 0 +#define BOARD_LED1 0 +#define BOARD_LED2 1 +#define BOARD_LED3 2 +#define BOARD_LED4 3 +#endif +#define BOARD_NLEDS 0 + +#if 0 +#define BOARD_LED_GREEN BOARD_LED1 +#define BOARD_LED_ORANGE BOARD_LED2 +#define BOARD_LED_RED BOARD_LED3 +#define BOARD_LED_BLUE BOARD_LED4 + +/* LED bits for use with board_userled_all() */ + +#define BOARD_LED1_BIT (1 << BOARD_LED1) +#define BOARD_LED2_BIT (1 << BOARD_LED2) +#define BOARD_LED3_BIT (1 << BOARD_LED3) +#define BOARD_LED4_BIT (1 << BOARD_LED4) + +/* If CONFIG_ARCH_LEDs is defined, + * then NuttX will control the 4 LEDs on board the stm32f4discovery. + * The following definitions describe how NuttX controls the LEDs: + */ + +#define LED_STARTED 0 /* LED1 */ +#define LED_HEAPALLOCATE 1 /* LED2 */ +#define LED_IRQSENABLED 2 /* LED1 + LED2 */ +#define LED_STACKCREATED 3 /* LED3 */ +#define LED_INIRQ 4 /* LED1 + LED3 */ +#define LED_SIGNAL 5 /* LED2 + LED3 */ +#define LED_ASSERTION 6 /* LED1 + LED2 + LED3 */ +#define LED_PANIC 7 /* N/C + N/C + N/C + LED4 */ + +/* Button definitions *******************************************************/ + +/* The STM32F4 Discovery supports one button: */ + +#define BUTTON_USER 0 + +#define NUM_BUTTONS 0 + +#define BUTTON_USER_BIT (1 << BUTTON_USER) + +#endif /* 0 */ + +/* Alternate function pin selections ****************************************/ + +/* UART2: + * + * The Mikroe-STM32F4 board has no on-board serial devices, but it brings out + * UART2 to the expansion header. + */ + +#define GPIO_USART2_RX (GPIO_USART2_RX_2|GPIO_SPEED_100MHz) +#define GPIO_USART2_TX (GPIO_USART2_TX_2|GPIO_SPEED_100MHz) + +/* PWM + * + * The STM32F4 Discovery has no real on-board PWM devices, but the board can + * be configured to output a pulse train using TIM4 CH2 on PD13. + */ + +#define GPIO_TIM4_CH2OUT (GPIO_TIM4_CH2OUT_2|GPIO_SPEED_50MHz) + +/* SPI - Onboard devices use SPI3, plus SPI2 routes to the I/O header */ + +#define GPIO_SPI2_MISO (GPIO_SPI2_MISO_1|GPIO_SPEED_50MHz) +#define GPIO_SPI2_MOSI (GPIO_SPI2_MOSI_1|GPIO_SPEED_50MHz) +#define GPIO_SPI2_SCK (GPIO_SPI2_SCK_2|GPIO_SPEED_50MHz) +#define DMACHAN_SPI2_RX DMAMAP_SPI2_RX +#define DMACHAN_SPI2_TX DMAMAP_SPI2_TX + +#define GPIO_SPI3_MISO (GPIO_SPI3_MISO_2|GPIO_SPEED_50MHz) +#define GPIO_SPI3_MOSI (GPIO_SPI3_MOSI_2|GPIO_SPEED_50MHz) +#define GPIO_SPI3_SCK (GPIO_SPI3_SCK_2|GPIO_SPEED_50MHz) +#define DMACHAN_SPI3_RX DMAMAP_SPI3_RX_2 +#define DMACHAN_SPI3_TX DMAMAP_SPI3_TX_2 + +/* Timer Inputs/Outputs */ + +#define GPIO_TIM2_CH1IN (GPIO_TIM2_CH1IN_2|GPIO_SPEED_50MHz) +#define GPIO_TIM2_CH2IN (GPIO_TIM2_CH2IN_1|GPIO_SPEED_50MHz) + +#define GPIO_TIM8_CH1IN (GPIO_TIM8_CH1IN_1|GPIO_SPEED_50MHz) +#define GPIO_TIM8_CH2IN (GPIO_TIM8_CH2IN_1|GPIO_SPEED_50MHz) + +/* USB OTG FS */ + +#define GPIO_OTGFS_DM (GPIO_OTGFS_DM_0|GPIO_SPEED_100MHz) +#define GPIO_OTGFS_DP (GPIO_OTGFS_DP_0|GPIO_SPEED_100MHz) +#define GPIO_OTGFS_ID (GPIO_OTGFS_ID_0|GPIO_SPEED_100MHz) +#define GPIO_OTGFS_SOF (GPIO_OTGFS_SOF_0|GPIO_SPEED_100MHz) + +#endif /* __BOARDS_ARM_STM32_MIKROE_STM32F4_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32f4/mikroe-stm32f4/kernel/Makefile b/boards/arm/stm32f4/mikroe-stm32f4/kernel/Makefile new file mode 100644 index 0000000000000..085f09c0d79a0 --- /dev/null +++ b/boards/arm/stm32f4/mikroe-stm32f4/kernel/Makefile @@ -0,0 +1,94 @@ +############################################################################ +# boards/arm/stm32f4/mikroe-stm32f4/kernel/Makefile +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +# The entry point name (if none is provided in the .config file) + +CONFIG_INIT_ENTRYPOINT ?= user_start +ENTRYPT = $(patsubst "%",%,$(CONFIG_INIT_ENTRYPOINT)) + +# Get the paths to the libraries and the links script path in format that +# is appropriate for the host OS + +USER_LIBPATHS = $(addprefix -L,$(call CONVERT_PATH,$(addprefix $(TOPDIR)$(DELIM),$(dir $(USERLIBS))))) +USER_LDSCRIPT = -T $(call CONVERT_PATH,$(BOARD_DIR)$(DELIM)scripts$(DELIM)memory.ld) +USER_LDSCRIPT += -T $(call CONVERT_PATH,$(BOARD_DIR)$(DELIM)scripts$(DELIM)user-space.ld) +USER_HEXFILE += $(call CONVERT_PATH,$(TOPDIR)$(DELIM)nuttx_user.hex) +USER_SRECFILE += $(call CONVERT_PATH,$(TOPDIR)$(DELIM)nuttx_user.srec) +USER_BINFILE += $(call CONVERT_PATH,$(TOPDIR)$(DELIM)nuttx_user.bin) + +USER_LDFLAGS = --undefined=$(ENTRYPT) --entry=$(ENTRYPT) $(USER_LDSCRIPT) +USER_LDLIBS = $(patsubst lib%,-l%,$(basename $(notdir $(USERLIBS)))) +USER_LIBGCC = "${shell "$(CC)" $(ARCHCPUFLAGS) -print-libgcc-file-name}" + +# Source files + +CSRCS = stm32_userspace.c +COBJS = $(CSRCS:.c=$(OBJEXT)) +OBJS = $(COBJS) + +# Targets: + +all: $(TOPDIR)$(DELIM)nuttx_user.elf $(TOPDIR)$(DELIM)User.map +.PHONY: nuttx_user.elf depend clean distclean + +$(COBJS): %$(OBJEXT): %.c + $(call COMPILE, $<, $@) + +# Create the nuttx_user.elf file containing all of the user-mode code + +nuttx_user.elf: $(OBJS) + $(Q) $(LD) -o $@ $(USER_LDFLAGS) $(USER_LIBPATHS) $(OBJS) --start-group $(USER_LDLIBS) --end-group $(USER_LIBGCC) + +$(TOPDIR)$(DELIM)nuttx_user.elf: nuttx_user.elf + @echo "LD: nuttx_user.elf" + $(Q) cp -a nuttx_user.elf $(TOPDIR)$(DELIM)nuttx_user.elf +ifeq ($(CONFIG_INTELHEX_BINARY),y) + @echo "CP: nuttx_user.hex" + $(Q) $(OBJCOPY) $(OBJCOPYARGS) -O ihex nuttx_user.elf $(USER_HEXFILE) +endif +ifeq ($(CONFIG_MOTOROLA_SREC),y) + @echo "CP: nuttx_user.srec" + $(Q) $(OBJCOPY) $(OBJCOPYARGS) -O srec nuttx_user.elf $(USER_SRECFILE) +endif +ifeq ($(CONFIG_RAW_BINARY),y) + @echo "CP: nuttx_user.bin" + $(Q) $(OBJCOPY) $(OBJCOPYARGS) -O binary nuttx_user.elf $(USER_BINFILE) +endif + +$(TOPDIR)$(DELIM)User.map: nuttx_user.elf + @echo "MK: User.map" + $(Q) $(NM) nuttx_user.elf >$(TOPDIR)$(DELIM)User.map + $(Q) $(CROSSDEV)size nuttx_user.elf + +.depend: + +depend: .depend + +clean: + $(call DELFILE, nuttx_user.elf) + $(call DELFILE, "$(TOPDIR)$(DELIM)nuttx_user.*") + $(call DELFILE, "$(TOPDIR)$(DELIM)User.map") + $(call CLEAN) + +distclean: clean diff --git a/boards/arm/stm32f4/mikroe-stm32f4/kernel/stm32_userspace.c b/boards/arm/stm32f4/mikroe-stm32f4/kernel/stm32_userspace.c new file mode 100644 index 0000000000000..75c04f0ea07e9 --- /dev/null +++ b/boards/arm/stm32f4/mikroe-stm32f4/kernel/stm32_userspace.c @@ -0,0 +1,110 @@ +/**************************************************************************** + * boards/arm/stm32f4/mikroe-stm32f4/kernel/stm32_userspace.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include +#include +#include + +#if defined(CONFIG_BUILD_PROTECTED) && !defined(__KERNEL__) + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +#ifndef CONFIG_NUTTX_USERSPACE +# error "CONFIG_NUTTX_USERSPACE not defined" +#endif + +#if CONFIG_NUTTX_USERSPACE != 0x08020000 +# error "CONFIG_NUTTX_USERSPACE must be 0x08020000 to match memory.ld" +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static struct userspace_data_s g_userspace_data = +{ + .us_heap = &g_mmheap, +}; + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/* These 'addresses' of these values are setup by the linker script. */ + +extern uint8_t _stext[]; /* Start of .text */ +extern uint8_t _etext[]; /* End_1 of .text + .rodata */ +extern const uint8_t _eronly[]; /* End+1 of read only section (.text + .rodata) */ +extern uint8_t _sdata[]; /* Start of .data */ +extern uint8_t _edata[]; /* End+1 of .data */ +extern uint8_t _sbss[]; /* Start of .bss */ +extern uint8_t _ebss[]; /* End+1 of .bss */ + +const struct userspace_s userspace locate_data(".userspace") = +{ + /* General memory map */ + + .us_entrypoint = CONFIG_INIT_ENTRYPOINT, + .us_textstart = (uintptr_t)_stext, + .us_textend = (uintptr_t)_etext, + .us_datasource = (uintptr_t)_eronly, + .us_datastart = (uintptr_t)_sdata, + .us_dataend = (uintptr_t)_edata, + .us_bssstart = (uintptr_t)_sbss, + .us_bssend = (uintptr_t)_ebss, + + /* User data memory structure */ + + .us_data = &g_userspace_data, + + /* Task/thread startup routines */ + + .task_startup = nxtask_startup, + + /* Signal handler trampoline */ + + .signal_handler = up_signal_handler, + + /* User-space work queue support (declared in include/nuttx/wqueue.h) */ + +#ifdef CONFIG_LIBC_USRWORK + .work_usrstart = work_usrstart, +#endif +}; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +#endif /* CONFIG_BUILD_PROTECTED && !__KERNEL__ */ diff --git a/boards/arm/stm32f4/mikroe-stm32f4/scripts/Make.defs b/boards/arm/stm32f4/mikroe-stm32f4/scripts/Make.defs new file mode 100644 index 0000000000000..c97f06d478ed3 --- /dev/null +++ b/boards/arm/stm32f4/mikroe-stm32f4/scripts/Make.defs @@ -0,0 +1,41 @@ +############################################################################ +# boards/arm/stm32f4/mikroe-stm32f4/scripts/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/.config +include $(TOPDIR)/tools/Config.mk +include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs + +LDSCRIPT = ld.script +ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) + +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32f4/mikroe-stm32f4/scripts/kernel-space.ld b/boards/arm/stm32f4/mikroe-stm32f4/scripts/kernel-space.ld new file mode 100644 index 0000000000000..153de5546bda5 --- /dev/null +++ b/boards/arm/stm32f4/mikroe-stm32f4/scripts/kernel-space.ld @@ -0,0 +1,100 @@ +/**************************************************************************** + * boards/arm/stm32f4/mikroe-stm32f4/scripts/kernel-space.ld + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* NOTE: This depends on the memory.ld script having been included prior to + * this script. + */ + +OUTPUT_ARCH(arm) +EXTERN(_vectors) +ENTRY(_stext) +SECTIONS +{ + .text : { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > kflash + + .init_section : { + _sinit = ABSOLUTE(.); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) + _einit = ABSOLUTE(.); + } > kflash + + .ARM.extab : { + *(.ARM.extab*) + } > kflash + + __exidx_start = ABSOLUTE(.); + .ARM.exidx : { + *(.ARM.exidx*) + } > kflash + + __exidx_end = ABSOLUTE(.); + + _eronly = ABSOLUTE(.); + + .data : { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > ksram AT > kflash + + .bss : { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(8); + _ebss = ABSOLUTE(.); + } > ksram + + /* Stabs debugging sections */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/stm32f4/mikroe-stm32f4/scripts/ld.script b/boards/arm/stm32f4/mikroe-stm32f4/scripts/ld.script new file mode 100644 index 0000000000000..b0a85f1be26e6 --- /dev/null +++ b/boards/arm/stm32f4/mikroe-stm32f4/scripts/ld.script @@ -0,0 +1,126 @@ +/**************************************************************************** + * boards/arm/stm32f4/mikroe-stm32f4/scripts/ld.script + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* The STM32F407VG has 1024Kb of FLASH beginning at address 0x0800:0000 and + * 192Kb of SRAM. SRAM is split up into three blocks: + * + * 1) 112Kb of SRAM beginning at address 0x2000:0000 + * 2) 16Kb of SRAM beginning at address 0x2001:c000 + * 3) 64Kb of CCM SRAM beginning at address 0x1000:0000 + * + * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 + * where the code expects to begin execution by jumping to the entry point in + * the 0x0800:0000 address + * range. + */ + +MEMORY +{ + flash (rx) : ORIGIN = 0x08000000, LENGTH = 1024K + sram (rwx) : ORIGIN = 0x20000000, LENGTH = 112K +} + +OUTPUT_ARCH(arm) +EXTERN(_vectors) +ENTRY(_stext) +SECTIONS +{ + .text : { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > flash + + .init_section : ALIGN(4) { + _sinit = ABSOLUTE(.); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) + _einit = ABSOLUTE(.); + } > flash + + .ARM.extab : ALIGN(4) { + *(.ARM.extab*) + } > flash + + .ARM.exidx : ALIGN(4) { + __exidx_start = ABSOLUTE(.); + *(.ARM.exidx*) + __exidx_end = ABSOLUTE(.); + } > flash + + .tdata : { + _stdata = ABSOLUTE(.); + *(.tdata .tdata.* .gnu.linkonce.td.*); + _etdata = ABSOLUTE(.); + } > flash + + .tbss : { + _stbss = ABSOLUTE(.); + *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); + _etbss = ABSOLUTE(.); + } > flash + + _eronly = ABSOLUTE(.); + + .data : ALIGN(4) { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > sram AT > flash + + .bss : ALIGN(4) { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + _ebss = ABSOLUTE(.); + } > sram + + /* Stabs debugging sections. */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/stm32f4/mikroe-stm32f4/scripts/memory.ld b/boards/arm/stm32f4/mikroe-stm32f4/scripts/memory.ld new file mode 100644 index 0000000000000..9d0a6f39cf69d --- /dev/null +++ b/boards/arm/stm32f4/mikroe-stm32f4/scripts/memory.ld @@ -0,0 +1,87 @@ +/**************************************************************************** + * boards/arm/stm32f4/mikroe-stm32f4/scripts/memory.ld + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* The STM32F407VG has 1024Kb of FLASH beginning at address 0x0800:0000 and + * 192Kb of SRAM. SRAM is split up into three blocks: + * + * 1) 112KB of SRAM beginning at address 0x2000:0000 + * 2) 16KB of SRAM beginning at address 0x2001:c000 + * 3) 64KB of CCM SRAM beginning at address 0x1000:0000 + * + * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 + * where the code expects to begin execution by jumping to the entry point in + * the 0x0800:0000 address range. + * + * For MPU support, the kernel-mode NuttX section is assumed to be 128Kb of + * FLASH and 4Kb of SRAM. That is an excessive amount for the kernel which + * should fit into 64KB and, of course, can be optimized as needed (See + * also boards/stm32f4discovery/scripts/kernel-space.ld). Allowing the + * additional does permit addition debug instrumentation to be added to the + * kernel space without overflowing the partition. + * + * Alignment of the user space FLASH partition is also a critical factor: + * The user space FLASH partition will be spanned with a single region of + * size 2**n bytes. The alignment of the user-space region must be the same. + * As a consequence, as the user-space increases in size, the alignment + * requirement also increases. + * + * This alignment requirement means that the largest user space FLASH region + * you can have will be 512KB at it would have to be positioned at + * 0x08800000. If you change this address, don't forget to change the + * CONFIG_NUTTX_USERSPACE configuration setting to match and to modify + * the check in kernel/userspace.c. + * + * For the same reasons, the maximum size of the SRAM mapping is limited to + * 4KB. Both of these alignment limitations could be reduced by using + * multiple regions to map the FLASH/SDRAM range or perhaps with some + * clever use of subregions. + * + * A detailed memory map for the 112KB SRAM region is as follows: + * + * 0x20000 0000: Kernel .data region. Typical size: 0.1KB + * ------- ---- Kernel .bss region. Typical size: 1.8KB + * 0x20000 0800: Kernel IDLE thread stack (approximate). Size is + * determined by CONFIG_IDLETHREAD_STACKSIZE and + * adjustments for alignment. Typical is 1KB. + * ------- ---- Padded to 4KB + * 0x20000 1000: User .data region. Size is variable. + * ------- ---- User .bss region Size is variable. + * 0x20000 2000: Beginning of kernel heap. Size determined by + * CONFIG_MM_KERNEL_HEAPSIZE. + * ------- ---- Beginning of user heap. Can vary with other settings. + * 0x20001 c000: End+1 of CPU RAM + */ + +MEMORY +{ + /* 1024Kb FLASH */ + + kflash (rx) : ORIGIN = 0x08000000, LENGTH = 128K + uflash (rx) : ORIGIN = 0x08020000, LENGTH = 128K + xflash (rx) : ORIGIN = 0x08040000, LENGTH = 768K + + /* 112Kb of contiguous SRAM */ + + ksram (rwx) : ORIGIN = 0x20000000, LENGTH = 4K + usram (rwx) : ORIGIN = 0x20001000, LENGTH = 4K + xsram (rwx) : ORIGIN = 0x20002000, LENGTH = 104K +} diff --git a/boards/arm/stm32f4/mikroe-stm32f4/scripts/user-space.ld b/boards/arm/stm32f4/mikroe-stm32f4/scripts/user-space.ld new file mode 100644 index 0000000000000..56cf83bb0fac8 --- /dev/null +++ b/boards/arm/stm32f4/mikroe-stm32f4/scripts/user-space.ld @@ -0,0 +1,101 @@ +/**************************************************************************** + * boards/arm/stm32f4/mikroe-stm32f4/scripts/user-space.ld + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* NOTE: This depends on the memory.ld script having been included prior to + * this script. + */ + +OUTPUT_ARCH(arm) +SECTIONS +{ + .userspace : { + *(.userspace) + } > uflash + + .text : { + _stext = ABSOLUTE(.); + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > uflash + + .init_section : { + _sinit = ABSOLUTE(.); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) + _einit = ABSOLUTE(.); + } > uflash + + .ARM.extab : { + *(.ARM.extab*) + } > uflash + + __exidx_start = ABSOLUTE(.); + .ARM.exidx : { + *(.ARM.exidx*) + } > uflash + + __exidx_end = ABSOLUTE(.); + + _eronly = ABSOLUTE(.); + + .data : { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > usram AT > uflash + + .bss : { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(8); + _ebss = ABSOLUTE(.); + } > usram + + /* Stabs debugging sections */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/stm32f4/mikroe-stm32f4/src/CMakeLists.txt b/boards/arm/stm32f4/mikroe-stm32f4/src/CMakeLists.txt new file mode 100644 index 0000000000000..1f0c3d19eed73 --- /dev/null +++ b/boards/arm/stm32f4/mikroe-stm32f4/src/CMakeLists.txt @@ -0,0 +1,67 @@ +# ############################################################################## +# boards/arm/stm32f4/mikroe-stm32f4/src/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(SRCS stm32_boot.c stm32_spi.c) + +if(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) + list(APPEND SRCS stm32_clockconfig.c) +endif() + +if(CONFIG_STM32_OTGFS) + list(APPEND SRCS stm32_usb.c) +endif() + +if(CONFIG_PWM) + list(APPEND SRCS stm32_pwm.c) +endif() + +if(CONFIG_ARCH_CUSTOM_PMINIT) + list(APPEND SRCS stm32_pm.c) +endif() + +if(CONFIG_ARCH_IDLE_CUSTOM) + list(APPEND SRCS stm32_idle.c) +endif() + +if(CONFIG_STM32_FSMC) + list(APPEND SRCS stm32_extmem.c) +endif() + +if(CONFIG_INPUT) + list(APPEND SRCS stm32_touchscreen.c) +endif() + +if(CONFIG_LCD_MIO283QT2) + list(APPEND SRCS stm32_mio283qt2.c) +endif() + +if(CONFIG_LCD_MIO283QT9A) + list(APPEND SRCS stm32_mio283qt9a.c) +endif() + +if(CONFIG_AUDIO_VS1053) + list(APPEND SRCS stm32_vs1053.c) +endif() + +target_sources(board PRIVATE ${SRCS}) + +set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/ld.script") diff --git a/boards/arm/stm32f4/mikroe-stm32f4/src/Make.defs b/boards/arm/stm32f4/mikroe-stm32f4/src/Make.defs new file mode 100644 index 0000000000000..aea83e0fe0551 --- /dev/null +++ b/boards/arm/stm32f4/mikroe-stm32f4/src/Make.defs @@ -0,0 +1,73 @@ +############################################################################ +# boards/arm/stm32f4/mikroe-stm32f4/src/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +CSRCS = stm32_boot.c stm32_spi.c + +ifeq ($(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG),y) +CSRCS += stm32_clockconfig.c +endif + +ifeq ($(CONFIG_STM32_OTGFS),y) +CSRCS += stm32_usb.c +endif + +ifeq ($(CONFIG_PWM),y) +CSRCS += stm32_pwm.c +endif + +ifeq ($(CONFIG_ARCH_CUSTOM_PMINIT),y) +CSRCS += stm32_pm.c +endif + +ifeq ($(CONFIG_ARCH_IDLE_CUSTOM),y) +CSRCS += stm32_idle.c +endif + +ifeq ($(CONFIG_STM32_FSMC),y) +CSRCS += stm32_extmem.c +endif + +ifeq ($(CONFIG_INPUT),y) +CSRCS += stm32_touchscreen.c +endif + +ifeq ($(CONFIG_LCD_MIO283QT2),y) +CSRCS += stm32_mio283qt2.c +endif + +ifeq ($(CONFIG_LCD_MIO283QT9A),y) +CSRCS += stm32_mio283qt9a.c +endif + +ifeq ($(CONFIG_AUDIO_VS1053),y) +CSRCS += stm32_vs1053.c +endif + +ifeq ($(CONFIG_ETC_ROMFS),y) +CSRCS += etc_romfs.c +endif + +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/mikroe-stm32f4/src/etc_romfs.c b/boards/arm/stm32f4/mikroe-stm32f4/src/etc_romfs.c similarity index 99% rename from boards/arm/stm32/mikroe-stm32f4/src/etc_romfs.c rename to boards/arm/stm32f4/mikroe-stm32f4/src/etc_romfs.c index 158b6f532564a..8e4bde5a9f646 100644 --- a/boards/arm/stm32/mikroe-stm32f4/src/etc_romfs.c +++ b/boards/arm/stm32f4/mikroe-stm32f4/src/etc_romfs.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/mikroe-stm32f4/src/etc_romfs.c + * boards/arm/stm32f4/mikroe-stm32f4/src/etc_romfs.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/mikroe-stm32f4/src/mikroe-stm32f4.h b/boards/arm/stm32f4/mikroe-stm32f4/src/mikroe-stm32f4.h similarity index 99% rename from boards/arm/stm32/mikroe-stm32f4/src/mikroe-stm32f4.h rename to boards/arm/stm32f4/mikroe-stm32f4/src/mikroe-stm32f4.h index beeb62fda1f6b..ab13436ea2165 100644 --- a/boards/arm/stm32/mikroe-stm32f4/src/mikroe-stm32f4.h +++ b/boards/arm/stm32f4/mikroe-stm32f4/src/mikroe-stm32f4.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/mikroe-stm32f4/src/mikroe-stm32f4.h + * boards/arm/stm32f4/mikroe-stm32f4/src/mikroe-stm32f4.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f4/mikroe-stm32f4/src/stm32_boot.c b/boards/arm/stm32f4/mikroe-stm32f4/src/stm32_boot.c new file mode 100644 index 0000000000000..548e44dd179ef --- /dev/null +++ b/boards/arm/stm32f4/mikroe-stm32f4/src/stm32_boot.c @@ -0,0 +1,467 @@ +/**************************************************************************** + * boards/arm/stm32f4/mikroe-stm32f4/src/stm32_boot.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include +#include +#include +#include + +#include +#include +#include + +#ifdef CONFIG_STM32_SPI3 +# include +#endif + +#ifdef CONFIG_MTD_M25P +# include +#endif + +#ifdef CONFIG_USBMONITOR +# include +#endif + +#ifdef CONFIG_MIKROE_FLASH_CONFIG_PART +#ifdef CONFIG_PLATFORM_CONFIGDATA +# include +#endif +#endif + +#ifdef CONFIG_AUDIO +# include +#endif + +#ifdef CONFIG_STM32_OTGFS +# include "stm32_usbhost.h" +#endif + +#include "stm32.h" +#include "arm_internal.h" +#include "mikroe-stm32f4.h" + +#ifdef CONFIG_SENSORS_QENCODER +#include "board_qencoder.h" +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +#define HAVE_USBDEV 1 +#define HAVE_USBHOST 1 +#define HAVE_USBMONITOR 1 +#define NSH_HAVEMMCSD 1 + +/* Can't support USB host or device features if USB OTG FS is not enabled */ + +#ifndef CONFIG_STM32_OTGFS +# undef HAVE_USBDEV +# undef HAVE_USBHOST +#endif + +/* Can't support USB device is USB device is not enabled */ + +#ifndef CONFIG_USBDEV +# undef HAVE_USBDEV +#endif + +/* Can't support USB host is USB host is not enabled */ + +#ifndef CONFIG_USBHOST +# undef HAVE_USBHOST +#endif + +/* Check if we should enable the USB monitor before starting NSH */ + +#ifndef CONFIG_USBMONITOR +# undef HAVE_USBMONITOR +#endif + +#ifndef HAVE_USBDEV +# undef CONFIG_USBDEV_TRACE +#endif + +#ifndef HAVE_USBHOST +# undef CONFIG_USBHOST_TRACE +#endif + +#if !defined(CONFIG_USBDEV_TRACE) && !defined(CONFIG_USBHOST_TRACE) +# undef HAVE_USBMONITOR +#endif + +/* Can't support MMC/SD features if mountpoints are disabled or if SDIO + * support is not enabled. + */ + +#if defined(CONFIG_DISABLE_MOUNTPOINT) || !defined(CONFIG_STM32_SPI3) +# undef NSH_HAVEMMCSD +#endif + +#ifndef CONFIG_NSH_MMCSDMINOR +# define CONFIG_NSH_MMCSDMINOR 0 +#endif + +# ifndef CONFIG_RAMMTD_BLOCKSIZE +# define CONFIG_RAMMTD_BLOCKSIZE 512 +# endif + +# ifndef CONFIG_RAMMTD_ERASESIZE +# define CONFIG_RAMMTD_ERASESIZE 4096 +# endif + +# ifndef CONFIG_TESTING_SMART_NEBLOCKS +# define CONFIG_TESTING_SMART_NEBLOCKS (22) +# endif + +#ifdef CONFIG_MIKROE_RAMMTD +# ifndef CONFIG_MIKROE_RAMMTD_MINOR +# define CONFIG_MIKROE_RAMMTD_MINOR 1 +# endif +# ifndef CONFIG_MIKROE_RAMMTD_SIZE +# define CONFIG_MIKROE_RAMMTD_SIZE 32 +# endif +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_boardinitialize + * + * Description: + * All STM32 architectures must provide the following entry point. + * This entry point is called early in the initialization -- after all + * memory has been configured and mapped but before any devices have been + * initialized. + * + ****************************************************************************/ + +void stm32_boardinitialize(void) +{ + /* First reset the VS1053 since it tends to produce noise out of power on + * reset + */ + +#ifdef CONFIG_AUDIO_VS1053 + stm32_configgpio(GPIO_VS1053_RST); +#endif + + /* Configure GPIOs for controlling the LCD */ + +#if defined(CONFIG_LCD_MIO283QT2) || defined(CONFIG_LCD_MIO283QT9A) + stm32_lcdinitialize(); +#endif + + /* Configure SPI chip selects if 1) SPI is not disabled, and 2) the weak + * function stm32_spidev_initialize() has been brought into the link. + */ + +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || defined(CONFIG_STM32_SPI3) + if (stm32_spidev_initialize) + { + stm32_spidev_initialize(); + } +#endif + + /* Initialize USB if the 1) OTG FS controller is in the configuration and + * 2) disabled, and 3) the weak function stm32_usbinitialize() has been + * brought into the build. Presumably either CONFIG_USBDEV or + * CONFIG_USBHOST is also selected. + */ + +#ifdef CONFIG_STM32_OTGFS + if (stm32_usbinitialize) + { + stm32_usbinitialize(); + } +#endif +} + +/**************************************************************************** + * Name: board_late_initialize + * + * Description: + * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_late_initialize(). board_late_initialize() will + * be called immediately after up_initialize() is called and just before + * the initial application is started. This additional initialization + * phase may be used, for example, to initialize board-specific device + * drivers. + * + ****************************************************************************/ + +#ifdef CONFIG_BOARD_LATE_INITIALIZE +void board_late_initialize(void) +{ +#ifdef CONFIG_STM32_SPI3 + struct spi_dev_s *spi; + struct mtd_dev_s *mtd; +#endif + int ret = OK; + + /* Configure SPI-based devices */ + +#ifdef CONFIG_STM32_SPI3 + /* Get the SPI port */ + + syslog(LOG_INFO, "Initializing SPI port 3\n"); + spi = stm32_spibus_initialize(3); + if (!spi) + { + syslog(LOG_ERR, "ERROR: Failed to initialize SPI port 3\n"); + return; + } + + syslog(LOG_INFO, "Successfully initialized SPI port 3\n"); + + /* Now bind the SPI interface to the M25P8 SPI FLASH driver */ + +#if defined(CONFIG_MTD) && defined(CONFIG_MIKROE_FLASH) + syslog(LOG_INFO, "Bind SPI to the SPI flash driver\n"); + + mtd = m25p_initialize(spi); + if (!mtd) + { + syslog(LOG_ERR, "ERROR: Failed to bind SPI port 3 to the SPI" + " FLASH driver\n"); + } + else + { + syslog(LOG_INFO, "Successfully bound SPI port 3 to the SPI" + " FLASH driver\n"); + +#ifdef CONFIG_MIKROE_FLASH_PART + { + int partno; + int partsize; + int partoffset; + const char *partstring = CONFIG_MIKROE_FLASH_PART_LIST; + const char *ptr; + struct mtd_dev_s *mtd_part; + char partname[16]; + + /* Now create a partition on the FLASH device */ + + partno = 0; + ptr = partstring; + partoffset = 0; + + while (*ptr != '\0') + { + /* Get the partition size */ + + partsize = atoi(ptr); + mtd_part = mtd_partition(mtd, partoffset, + (partsize >> 2) * 16); + partoffset += (partsize >> 2) * 16; + +#ifdef CONFIG_MIKROE_FLASH_CONFIG_PART + /* Test if this is the config partition */ + + if (CONFIG_MIKROE_FLASH_CONFIG_PART_NUMBER == partno) + { + /* Register the partition as the config device */ + + mtdconfig_register(mtd_part); + } + else +#endif + { + /* Now initialize a SMART Flash block device and bind it + * to the MTD device. + */ + + #if defined(CONFIG_MTD_SMART) && defined(CONFIG_FS_SMARTFS) + snprintf(partname, sizeof(partname), "p%d", partno); + smart_initialize(CONFIG_MIKROE_FLASH_MINOR, mtd_part, + partname); +#endif + } + + /* Update the pointer to point to the next size in the list */ + + while ((*ptr >= '0') && (*ptr <= '9')) + { + ptr++; + } + + if (*ptr == ',') + { + ptr++; + } + + /* Increment the part number */ + + partno++; + } + } +#else /* CONFIG_MIKROE_FLASH_PART */ + + /* Configure the device with no partition support */ + + smart_initialize(CONFIG_MIKROE_FLASH_MINOR, mtd, NULL); + +#endif /* CONFIG_MIKROE_FLASH_PART */ + } + + /* Create a RAM MTD device if configured */ + +#if defined(CONFIG_RAMMTD) && defined(CONFIG_MIKROE_RAMMTD) + { + uint8_t *start = + kmm_malloc(CONFIG_MIKROE_RAMMTD_SIZE * 1024); + mtd = rammtd_initialize(start, CONFIG_MIKROE_RAMMTD_SIZE * 1024); + mtd->ioctl(mtd, MTDIOC_BULKERASE, 0); + + /* Now initialize a SMART Flash block device and bind it to the + * MTD device + */ + +#if defined(CONFIG_MTD_SMART) && defined(CONFIG_FS_SMARTFS) + smart_initialize(CONFIG_MIKROE_RAMMTD_MINOR, mtd, NULL); +#endif + } + +#endif /* CONFIG_RAMMTD && CONFIG_MIKROE_RAMMTD */ + +#endif /* CONFIG_MTD */ +#endif /* CONFIG_STM32_SPI3 */ + + /* Create the SPI FLASH MTD instance */ + + /* The M25Pxx is not a good media to implement a file system.. + * its block sizes are too large + */ + + /* Mount the SDIO-based MMC/SD block driver */ + +#ifdef NSH_HAVEMMCSD + /* Bind the spi interface to the MMC/SD driver */ + + syslog(LOG_INFO, "Bind SDIO to the MMC/SD driver, minor=%d\n", + CONFIG_NSH_MMCSDMINOR); + + ret = mmcsd_spislotinitialize(CONFIG_NSH_MMCSDMINOR, + CONFIG_NSH_MMCSDSLOTNO, spi); + if (ret != OK) + { + syslog(LOG_ERR, "ERROR: Failed to bind SPI to the MMC/SD driver:" + " %d\n", ret); + } + else + { + syslog(LOG_INFO, "Successfully bound SPI to the MMC/SD driver\n"); + } +#endif + +#ifdef HAVE_USBHOST + /* Initialize USB host operation. stm32_usbhost_initialize() starts a + * thread will monitor for USB connection and disconnection events. + */ + + ret = stm32_usbhost_initialize(); + if (ret != OK) + { + syslog(LOG_ERR, "ERROR: Failed to initialize USB host: %d\n", ret); + return; + } +#endif + +#ifdef HAVE_USBMONITOR + /* Start the USB Monitor */ + + ret = usbmonitor_start(); + if (ret != OK) + { + syslog(LOG_ERR, "ERROR: Failed to start USB monitor: %d\n", ret); + } +#endif + +#ifdef CONFIG_INPUT + /* Initialize the touchscreen */ + + ret = stm32_tsc_setup(0); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_tsc_setup failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_PWM + /* Initialize PWM and register the PWM device. */ + + ret = stm32_pwm_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_pwm_setup() failed: %d\n", ret); + } +#endif + +#if defined(CONFIG_LCD_MIO283QT2) || defined(CONFIG_LCD_MIO283QT9A) + /* Configure the TFT LCD module */ + + syslog(LOG_INFO, "Initializing TFT LCD module\n"); + + ret = board_lcd_initialize(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to initialize TFT LCD module\n"); + } +#endif + +#ifdef CONFIG_SENSORS_QENCODER + /* Initialize and register the qencoder driver */ + + ret = board_qencoder_initialize(0, CONFIG_MIKROE_QETIMER); + if (ret != OK) + { + syslog(LOG_ERR, + "ERROR: Failed to register the qencoder: %d\n", + ret); + return; + } +#endif + +#ifdef CONFIG_AUDIO + /* Configure the Audio sub-system if enabled and bind it to SPI 3 */ + + up_vs1053initialize(spi); +#endif +} +#endif diff --git a/boards/arm/stm32/mikroe-stm32f4/src/stm32_clockconfig.c b/boards/arm/stm32f4/mikroe-stm32f4/src/stm32_clockconfig.c similarity index 98% rename from boards/arm/stm32/mikroe-stm32f4/src/stm32_clockconfig.c rename to boards/arm/stm32f4/mikroe-stm32f4/src/stm32_clockconfig.c index 75b6870101ab3..2bf857538d281 100644 --- a/boards/arm/stm32/mikroe-stm32f4/src/stm32_clockconfig.c +++ b/boards/arm/stm32f4/mikroe-stm32f4/src/stm32_clockconfig.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/mikroe-stm32f4/src/stm32_clockconfig.c + * boards/arm/stm32f4/mikroe-stm32f4/src/stm32_clockconfig.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f4/mikroe-stm32f4/src/stm32_extmem.c b/boards/arm/stm32f4/mikroe-stm32f4/src/stm32_extmem.c new file mode 100644 index 0000000000000..3f04746a7eca8 --- /dev/null +++ b/boards/arm/stm32f4/mikroe-stm32f4/src/stm32_extmem.c @@ -0,0 +1,141 @@ +/**************************************************************************** + * boards/arm/stm32f4/mikroe-stm32f4/src/stm32_extmem.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32_gpio.h" +#include "stm32.h" +#include "mikroe-stm32f4.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifndef CONFIG_STM32_FSMC +# warning "FSMC is not enabled" +#endif + +#if STM32_NGPIO_PORTS < 6 +# error "Required GPIO ports not enabled" +#endif + +#define STM32_FSMC_NADDRCONFIGS 26 +#define STM32_FSMC_NDATACONFIGS 16 + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/* GPIO configurations common to most external memories */ + +static const uint32_t g_addressconfig[STM32_FSMC_NADDRCONFIGS] = +{ + GPIO_FSMC_A0, GPIO_FSMC_A1 , GPIO_FSMC_A2, + GPIO_FSMC_A3, GPIO_FSMC_A4 , GPIO_FSMC_A5, + GPIO_FSMC_A6, GPIO_FSMC_A7, GPIO_FSMC_A8, + GPIO_FSMC_A9, GPIO_FSMC_A10, GPIO_FSMC_A11, + GPIO_FSMC_A12, GPIO_FSMC_A13, GPIO_FSMC_A14, + GPIO_FSMC_A15, GPIO_FSMC_A16, GPIO_FSMC_A17, + GPIO_FSMC_A18, GPIO_FSMC_A19, GPIO_FSMC_A20, + GPIO_FSMC_A21, GPIO_FSMC_A22, GPIO_FSMC_A23, + GPIO_FSMC_A24, GPIO_FSMC_A25 +}; + +static const uint32_t g_dataconfig[STM32_FSMC_NDATACONFIGS] = +{ + GPIO_FSMC_D0, GPIO_FSMC_D1 , GPIO_FSMC_D2, + GPIO_FSMC_D3, GPIO_FSMC_D4 , GPIO_FSMC_D5, + GPIO_FSMC_D6, GPIO_FSMC_D7, GPIO_FSMC_D8, + GPIO_FSMC_D9, GPIO_FSMC_D10, GPIO_FSMC_D11, + GPIO_FSMC_D12, GPIO_FSMC_D13, GPIO_FSMC_D14, + GPIO_FSMC_D15 +}; + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_extmemgpios + * + * Description: + * Initialize GPIOs for external memory usage + * + ****************************************************************************/ + +void stm32_extmemgpios(const uint32_t *gpios, int ngpios) +{ + int i; + + /* Configure GPIOs */ + + for (i = 0; i < ngpios; i++) + { + stm32_configgpio(gpios[i]); + } +} + +/**************************************************************************** + * Name: stm32_extmemaddr + * + * Description: + * Initialize address line GPIOs for external memory access + * + ****************************************************************************/ + +void stm32_extmemaddr(int naddrs) +{ + stm32_extmemgpios(g_addressconfig, naddrs); +} + +/**************************************************************************** + * Name: stm32_extmemdata + * + * Description: + * Initialize data line GPIOs for external memory access + * + ****************************************************************************/ + +void stm32_extmemdata(int ndata) +{ + stm32_extmemgpios(g_dataconfig, ndata); +} diff --git a/boards/arm/stm32f4/mikroe-stm32f4/src/stm32_idle.c b/boards/arm/stm32f4/mikroe-stm32f4/src/stm32_idle.c new file mode 100644 index 0000000000000..f9cef25fff2b8 --- /dev/null +++ b/boards/arm/stm32f4/mikroe-stm32f4/src/stm32_idle.c @@ -0,0 +1,263 @@ +/**************************************************************************** + * boards/arm/stm32f4/mikroe-stm32f4/src/stm32_idle.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include + +#include +#include +#include +#include + +#include + +#include "arm_internal.h" +#include "stm32_pm.h" +#include "stm32_rcc.h" +#include "stm32_exti.h" + +#include "mikroe-stm32f4.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* Does the board support an IDLE LED to indicate that the board is in the + * IDLE state? + */ + +#if defined(CONFIG_ARCH_LEDS) && defined(LED_IDLE) +# define BEGIN_IDLE() board_autoled_on(LED_IDLE) +# define END_IDLE() board_autoled_off(LED_IDLE) +#else +# define BEGIN_IDLE() +# define END_IDLE() +#endif + +/* Values for the RTC Alarm to wake up from the PM_STANDBY mode */ + +#ifndef CONFIG_PM_ALARM_SEC +# define CONFIG_PM_ALARM_SEC 3 +#endif + +#ifndef CONFIG_PM_ALARM_NSEC +# define CONFIG_PM_ALARM_NSEC 0 +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#if defined(CONFIG_PM) && defined(CONFIG_RTC_ALARM) +static void up_alarmcb(void); +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_idlepm + * + * Description: + * Perform IDLE state power management. + * + ****************************************************************************/ + +#ifdef CONFIG_PM +static void up_idlepm(void) +{ +#ifdef CONFIG_RTC_ALARM + struct timespec alarmtime; +#endif + static enum pm_state_e oldstate = PM_NORMAL; + enum pm_state_e newstate; + irqstate_t flags; + int ret; + + /* Decide, which power saving level can be obtained */ + + newstate = pm_checkstate(PM_IDLE_DOMAIN); + + /* Check for state changes */ + + if (newstate != oldstate) + { + _info("newstate= %d oldstate=%d\n", newstate, oldstate); + + flags = enter_critical_section(); + + /* Force the global state change */ + + ret = pm_changestate(PM_IDLE_DOMAIN, newstate); + if (ret < 0) + { + /* The new state change failed, revert to the preceding state */ + + pm_changestate(PM_IDLE_DOMAIN, oldstate); + + /* No state change... */ + + goto errout; + } + + /* Then perform board-specific, state-dependent logic here */ + + switch (newstate) + { + case PM_NORMAL: + { + } + break; + + case PM_IDLE: + { + } + break; + + case PM_STANDBY: + { +#ifdef CONFIG_RTC_ALARM + /* Disable RTC Alarm interrupt */ + +#warning "missing logic" + + /* Configure the RTC alarm to Auto Wake the system */ + +#warning "missing logic" + + /* The tv_nsec value must not exceed 1,000,000,000. That + * would be an invalid time. + */ + +#warning "missing logic" + + /* Set the alarm */ + +#warning "missing logic" +#endif + /* Call the STM32 stop mode */ + + stm32_pmstop(true); + + /* We have been re-awakened by some even: A button press? + * An alarm? Cancel any pending alarm and resume the normal + * operation. + */ + +#ifdef CONFIG_RTC_ALARM +#warning "missing logic" +#endif + /* Resume normal operation */ + + pm_changestate(PM_IDLE_DOMAIN, PM_NORMAL); + newstate = PM_NORMAL; + } + break; + + case PM_SLEEP: + { + /* We should not return from standby mode. The only way out + * of standby is via the reset path. + */ + + stm32_pmstandby(); + } + break; + + default: + break; + } + + /* Save the new state */ + + oldstate = newstate; + +errout: + leave_critical_section(flags); + } +} +#else +# define up_idlepm() +#endif + +/**************************************************************************** + * Name: up_alarmcb + * + * Description: + * RTC alarm service routine + * + ****************************************************************************/ + +#if defined(CONFIG_PM) && defined(CONFIG_RTC_ALARM) +static void up_alarmcb(void) +{ + /* This alarm occurs because there wasn't any EXTI interrupt during the + * PM_STANDBY period. So just go to sleep. + */ + + pm_changestate(PM_IDLE_DOMAIN, PM_SLEEP); +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_idle + * + * Description: + * up_idle() is the logic that will be executed when their is no other + * ready-to-run task. This is processor idle time and will continue until + * some interrupt occurs to cause a context switch from the idle task. + * + * Processing in this state may be processor-specific. e.g., this is where + * power management operations might be performed. + * + ****************************************************************************/ + +void up_idle(void) +{ +#if defined(CONFIG_SUPPRESS_INTERRUPTS) || defined(CONFIG_SUPPRESS_TIMER_INTS) + /* If the system is idle and there are no timer interrupts, then process + * "fake" timer interrupts. Hopefully, something will wake up. + */ + + nxsched_process_timer(); +#else + + /* Perform IDLE mode power management */ + + BEGIN_IDLE(); + up_idlepm(); + END_IDLE(); +#endif +} diff --git a/boards/arm/stm32/mikroe-stm32f4/src/stm32_mio283qt2.c b/boards/arm/stm32f4/mikroe-stm32f4/src/stm32_mio283qt2.c similarity index 99% rename from boards/arm/stm32/mikroe-stm32f4/src/stm32_mio283qt2.c rename to boards/arm/stm32f4/mikroe-stm32f4/src/stm32_mio283qt2.c index c56b43eed1a16..259eaf710b705 100644 --- a/boards/arm/stm32/mikroe-stm32f4/src/stm32_mio283qt2.c +++ b/boards/arm/stm32f4/mikroe-stm32f4/src/stm32_mio283qt2.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/mikroe-stm32f4/src/stm32_mio283qt2.c + * boards/arm/stm32f4/mikroe-stm32f4/src/stm32_mio283qt2.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/mikroe-stm32f4/src/stm32_mio283qt9a.c b/boards/arm/stm32f4/mikroe-stm32f4/src/stm32_mio283qt9a.c similarity index 99% rename from boards/arm/stm32/mikroe-stm32f4/src/stm32_mio283qt9a.c rename to boards/arm/stm32f4/mikroe-stm32f4/src/stm32_mio283qt9a.c index b40aff992d589..aab48c5e5e561 100644 --- a/boards/arm/stm32/mikroe-stm32f4/src/stm32_mio283qt9a.c +++ b/boards/arm/stm32f4/mikroe-stm32f4/src/stm32_mio283qt9a.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/mikroe-stm32f4/src/stm32_mio283qt9a.c + * boards/arm/stm32f4/mikroe-stm32f4/src/stm32_mio283qt9a.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f4/mikroe-stm32f4/src/stm32_pm.c b/boards/arm/stm32f4/mikroe-stm32f4/src/stm32_pm.c new file mode 100644 index 0000000000000..1905d67954d5e --- /dev/null +++ b/boards/arm/stm32f4/mikroe-stm32f4/src/stm32_pm.c @@ -0,0 +1,75 @@ +/**************************************************************************** + * boards/arm/stm32f4/mikroe-stm32f4/src/stm32_pm.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include "arm_internal.h" +#include "stm32_pm.h" +#include "mikroe-stm32f4.h" + +#ifdef CONFIG_PM + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: arm_pminitialize + * + * Description: + * This function is called by MCU-specific logic at power-on reset in + * order to provide one-time initialization the power management subsystem. + * This function must be called *very* early in the initialization sequence + * *before* any other device drivers are initialized (since they may + * attempt to register with the power management subsystem). + * + * Input Parameters: + * None. + * + * Returned Value: + * None. + * + ****************************************************************************/ + +void arm_pminitialize(void) +{ + /* Initialize the NuttX power management subsystem proper */ + + pm_initialize(); + +#if defined(CONFIG_ARCH_IDLE_CUSTOM) && defined(CONFIG_PM_BUTTONS) + /* Initialize the buttons to wake up the system from low power modes */ + + up_pmbuttons(); +#endif + + /* Initialize the LED PM */ + + up_ledpminitialize(); +} + +#endif /* CONFIG_PM */ diff --git a/boards/arm/stm32f4/mikroe-stm32f4/src/stm32_pwm.c b/boards/arm/stm32f4/mikroe-stm32f4/src/stm32_pwm.c new file mode 100644 index 0000000000000..0e96a7fd9a247 --- /dev/null +++ b/boards/arm/stm32f4/mikroe-stm32f4/src/stm32_pwm.c @@ -0,0 +1,127 @@ +/**************************************************************************** + * boards/arm/stm32f4/mikroe-stm32f4/src/stm32_pwm.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include + +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32_pwm.h" +#include "mikroe-stm32f4.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* PWM + * + * The mikroe_stm32f4 has no real on-board PWM devices, but the board can be + * configured to output a pulse train using TIM4 CH2. + * This pin is used by FSMC is connected to CN5 just for this purpose: + * + * PD13 FSMC_A18 / MC_TIM4_CH2OUT pin 33 (EnB) + * + * FSMC must be disabled in this case! + */ + +#define HAVE_PWM 1 + +#ifndef CONFIG_PWM +# undef HAVE_PWM +#endif + +#ifndef CONFIG_STM32_TIM4 +# undef HAVE_PWM +#endif + +#ifndef CONFIG_STM32_TIM4_PWM +# undef HAVE_PWM +#endif + +#if CONFIG_STM32_TIM4_CHANNEL != STM32F4DISCOVERY_PWMCHANNEL +# undef HAVE_PWM +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_pwm_setup + * + * Description: + * Initialize PWM and register the PWM device. + * + ****************************************************************************/ + +int stm32_pwm_setup(void) +{ +#ifdef HAVE_PWM + static bool initialized = false; + struct pwm_lowerhalf_s *pwm; + int ret; + + /* Have we already initialized? */ + + if (!initialized) + { + /* Call stm32_pwminitialize() to get an instance of the PWM interface */ + + pwm = stm32_pwminitialize(STM32F4DISCOVERY_PWMTIMER); + if (!pwm) + { + _err("ERROR: Failed to get the STM32 PWM lower half\n"); + return -ENODEV; + } + + /* Register the PWM driver at "/dev/pwm0" */ + + ret = pwm_register("/dev/pwm0", pwm); + if (ret < 0) + { + aerr("ERROR: pwm_register failed: %d\n", ret); + return ret; + } + + /* Now we are initialized */ + + initialized = true; + } + + return OK; +#else + return -ENODEV; +#endif +} diff --git a/boards/arm/stm32f4/mikroe-stm32f4/src/stm32_spi.c b/boards/arm/stm32f4/mikroe-stm32f4/src/stm32_spi.c new file mode 100644 index 0000000000000..35f55d130af89 --- /dev/null +++ b/boards/arm/stm32f4/mikroe-stm32f4/src/stm32_spi.c @@ -0,0 +1,246 @@ +/**************************************************************************** + * boards/arm/stm32f4/mikroe-stm32f4/src/stm32_spi.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include + +#include +#include + +#include "arm_internal.h" +#include "chip.h" +#include "stm32.h" +#include "mikroe-stm32f4.h" + +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || defined(CONFIG_STM32_SPI3) + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_spidev_initialize + * + * Description: + * Called to configure SPI chip select GPIO pins for the mikroe_stm32f4 + * board. + * + ****************************************************************************/ + +void weak_function stm32_spidev_initialize(void) +{ +#ifdef CONFIG_STM32_SPI3 + +#ifdef CONFIG_MTD_M25P + stm32_configgpio(GPIO_CS_FLASH); /* FLASH chip select */ +#endif + +#if defined(CONFIG_MMCSD) + stm32_configgpio(GPIO_CS_MMCSD); /* MMC/SD chip select */ + stm32_configgpio(GPIO_SD_CD); /* MMC/SD card detect */ +#endif + +#ifdef CONFIG_AUDIO_VS1053 + stm32_configgpio(GPIO_CS_MP3_DATA); /* MP3 codec chip select for DATA */ + stm32_configgpio(GPIO_CS_MP3_CMD); /* MP3 codec chip select for CMD */ +#endif + + /* Configure the EXP I/O cs for SPI3 */ + + stm32_configgpio(GPIO_CS_EXP_SPI3); /* Expander chip select */ + +#endif +} + +/**************************************************************************** + * Name: stm32_spi1/2/3select and stm32_spi1/2/3status + * + * Description: + * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status + * must be provided by board-specific logic. They are implementations of + * the select and status methods of the SPI interface defined by struct + * spi_ops_s (see include/nuttx/spi/spi.h). All other methods (including + * stm32_spibus_initialize()) are provided by common STM32 logic. + * To use this common SPI logic on your board: + * + * 1. Provide logic in stm32_boardinitialize() to configure SPI chip + * select pins. + * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() functions + * in your board-specific logic. These functions will perform chip + * selection and status operations using GPIOs in the way your board is + * configured. + * 3. Add a calls to stm32_spibus_initialize() in your low level + * application initialization logic + * 4. The handle returned by stm32_spibus_initialize() may then be used to + * bind the SPI driver to higher level logic (e.g., calling + * mmcsd_spislotinitialize(), for example, will bind the SPI driver to + * the SPI MMC/SD driver). + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_SPI3 +void stm32_spi3select(struct spi_dev_s *dev, + uint32_t devid, bool selected) +{ + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); + +#if defined(CONFIG_AUDIO_VS1053) + if (devid == SPIDEV_AUDIO_DATA(0)) + { + stm32_gpiowrite(GPIO_CS_MP3_DATA, !selected); + } + else if (devid == SPIDEV_AUDIO_CTRL(0)) + { + stm32_gpiowrite(GPIO_CS_MP3_CMD, !selected); + } + else +#endif + +#if defined(CONFIG_MMCSD) + if (devid == SPIDEV_MMCSD(0)) + { + stm32_gpiowrite(GPIO_CS_MMCSD, !selected); + } + else +#endif + +#if defined(CONFIG_MTD_M25P) + if (devid == SPIDEV_FLASH(0)) + { + stm32_gpiowrite(GPIO_CS_FLASH, !selected); + } + else +#endif + + /* Must be the expansion header device */ + + if (devid == SPIDEV_EXPANDER(0)) + { + stm32_gpiowrite(GPIO_CS_EXP_SPI3, !selected); + } +} + +uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid) +{ + uint8_t ret = 0; + +#if defined(CONFIG_MMCSD) + if (devid == SPIDEV_MMCSD(0)) + { + /* A low value indicates the card is present */ + + if (!stm32_gpioread(GPIO_SD_CD)) + { + ret = SPI_STATUS_PRESENT; + } + } +#endif + + return ret; +} +#endif + +#ifdef CONFIG_STM32_SPI2 +void stm32_spi2select(struct spi_dev_s *dev, + uint32_t devid, bool selected) +{ + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); +} + +uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} +#endif + +#ifdef CONFIG_STM32_SPI1 +void stm32_spi1select(struct spi_dev_s *dev, + uint32_t devid, bool selected) +{ + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); +} + +uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} +#endif + +/**************************************************************************** + * Name: stm32_spi1cmddata + * + * Description: + * Set or clear the SH1101A A0 or SD1306 D/C n bit to select data (true) + * or command (false). This function must be provided by platform-specific + * logic. This is an implementation of the cmddata method of the SPI + * interface defined by struct spi_ops_s (see include/nuttx/spi/spi.h). + * + * Input Parameters: + * + * spi - SPI device that controls the bus the device that requires the CMD/ + * DATA selection. + * devid - If there are multiple devices on the bus, this selects which one + * to select cmd or data. NOTE: This design restricts, for example, + * one one SPI display per SPI bus. + * cmd - true: select command; false: select data + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_SPI_CMDDATA +#ifdef CONFIG_STM32_SPI1 +int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) +{ + return -ENODEV; +} +#endif + +#ifdef CONFIG_STM32_SPI2 +int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) +{ + return OK; +} +#endif + +#ifdef CONFIG_STM32_SPI3 +int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) +{ + return OK; +} +#endif +#endif /* CONFIG_SPI_CMDDATA */ + +#endif /* CONFIG_STM32_SPI1 || CONFIG_STM32_SPI2 */ diff --git a/boards/arm/stm32f4/mikroe-stm32f4/src/stm32_touchscreen.c b/boards/arm/stm32f4/mikroe-stm32f4/src/stm32_touchscreen.c new file mode 100644 index 0000000000000..c1ca271395472 --- /dev/null +++ b/boards/arm/stm32f4/mikroe-stm32f4/src/stm32_touchscreen.c @@ -0,0 +1,1547 @@ +/**************************************************************************** + * boards/arm/stm32f4/mikroe-stm32f4/src/stm32_touchscreen.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include "arm_internal.h" +#include "stm32_adc.h" +#include "stm32_gpio.h" +#include "mikroe-stm32f4.h" + +#ifdef CONFIG_INPUT + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* Reference counting is partially implemented, but not needed in the current + * design. + */ + +#define CONFIG_TOUCHSCREEN_REFCNT +/* Should we try again on bad samples? */ + +#undef CONFIG_TOUCHSCREEN_RESAMPLE + +/* TP uses ADC Channel #2 in a dedicated mode. Ensure ADC2 not selected for + * general use via the menuconfig + */ + +#ifndef CONFIG_STM32_ADC2 +# error Touchpanel Input (CONFIG_INPUT=y) requires enablinga ADC2 (CONFIG_STM32_ADC2=y) +#endif + +/* Work queue support is required */ + +#ifndef CONFIG_SCHED_WORKQUEUE +# warning Work queue support is required (CONFIG_SCHED_WORKQUEUE=y) +#endif + +/* CONFIG_TOUCHSCREEN_THRESHX and CONFIG_TOUCHSCREEN_THRESHY + * Touchscreen data comes in a a very high rate. New touch positions + * will only be reported when the X or Y data changes by these thresholds. + * This trades reduces data rate for some loss in dragging accuracy. The + * touchscreen is configure for 12-bit values so the raw ranges are 0-4096. + * So for example, if your display is 320x240, then THRESHX=3 and THRESHY=4 + * would correspond to one pixel. Default: 4 + */ + +#ifndef CONFIG_TOUCHSCREEN_THRESHX +# define CONFIG_TOUCHSCREEN_THRESHX 12 +#endif + +#ifndef CONFIG_TOUCHSCREEN_THRESHY +# define CONFIG_TOUCHSCREEN_THRESHY 12 +#endif + +#ifndef CONFIG_TOUCHSCREEN_AVG_SAMPLES +# define CONFIG_TOUCHSCREEN_AVG_SAMPLES 2 +#endif + +#ifndef CONFIG_TOUCHSCREEN_NPOLLWAITERS +# define CONFIG_TOUCHSCREEN_NPOLLWAITERS 2 +#endif + +/* Driver support ***********************************************************/ + +/* This format is used to construct the /dev/input[n] device driver path. It + * is defined here so that it will be used consistently in all places. + */ + +#define DEV_FORMAT "/dev/input%d" +#define DEV_NAMELEN 16 + +/* Mikroe-STM32M4 Touchscreen Hardware Definitions ************************** + * PIN CONFIGURATIONS SIGNAL NAME ON-BOARD CONNECTIONS + * --- ---------------------------------- -------------------- -------------- + * 35 PB0 LCD-YD YD Analog input + * 36 PB1 LCD-XL XL Analog input + * 95 PB8 DRIVEA Drives XR, XL and YU + * 96 PB9 DRIVEB Drives YD + */ + +#define LCD_YD_PIN (0) +#define LCD_XL_PIN (1) +#define LCD_YD_CHANNEL (8) +#define LCD_XL_CHANNEL (9) +#define LCD_DRIVEA_PIN (8) +#define LCD_DRIVEB_PIN (9) + +#define LCD_DRIVEA_BIT (1 << LCD_DRIVEA_PIN) +#define LCD_DRIVEB_BIT (1 << LCD_DRIVEB_PIN) +#define LCD_SAMPX_BITS (LCD_DRIVEA_BIT | (LCD_DRIVEB_BIT << 16)) +#define LCD_SAMPY_BITS (LCD_DRIVEB_BIT | (LCD_DRIVEA_BIT << 16)) +#define LCD_TP_PORT_SETRESET STM32_GPIOB_BSRR + +#define TC_ADC_BASE STM32_ADC2_BASE /* ADC Channel base for TP */ +#define ADC_CR1_ALLINTS (ADC_CR1_AWDIE | ADC_CR1_EOCIE | ADC_CR1_JEOCIE) + +/* Conversions are performed as 10-bit samples represented as 16-bit */ + +#define MAX_ADC (4096) + +/* A measured value has to be within this range to be considered */ + +#define UPPER_THRESHOLD (MAX_ADC-1) +#define LOWER_THRESHOLD (362) + +/* Delays *******************************************************************/ + +/* All values will be increased by one system timer tick (probably 10MS). */ + +#define TC_PENUP_POLL_TICKS MSEC2TICK(70) /* IDLE polling rate: 70 MSec */ +#define TC_PENDOWN_POLL_TICKS MSEC2TICK(40) /* Active polling rate: 40 MSec */ +#define TC_DEBOUNCE_TICKS MSEC2TICK(16) /* Delay before re-sampling: 16 MSec */ +#define TC_SAMPLE_TICKS MSEC2TICK(4) /* Delay for A/D sampling: 4 MSec */ +#define TC_SETTLE_TICKS MSEC2TICK(10) /* Delay for A/D settling: 10 MSec */ +#define TC_RESAMPLE_TICKS TC_SAMPLE_TICKS + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/* This enumeration describes the state of touchscreen state machine */ + +enum tc_state_e +{ + TC_READY = 0, /* Ready to begin next sample */ + TC_READY_SETTLE, /* Allowing time for Y DRIVE to settle */ + TC_YPENDOWN, /* Allowing time for the Y pen down sampling */ + TC_DEBOUNCE, /* Allowing a debounce time for the first sample */ + TC_RESAMPLE, /* Restart sampling on a bad measurement */ + TC_YSAMPLE, /* Allowing time for the Y sampling */ + TC_XSETTLE, /* Allowing time for the X to settle after changing DRIVE */ + TC_XSAMPLE, /* Allowing time for the X sampling */ + TC_XRESAMPLE, /* Allow time to resample X */ + TC_PENDOWN, /* Conversion is complete -- pen down */ + TC_PENUP /* Conversion is complete -- pen up */ +}; + +/* This describes the state of one contact */ + +enum tc_contact_e +{ + CONTACT_NONE = 0, /* No contact */ + CONTACT_DOWN, /* First contact */ + CONTACT_MOVE, /* Same contact, possibly different position */ + CONTACT_UP, /* Contact lost */ +}; + +/* This structure describes the results of one touchscreen sample */ + +struct tc_sample_s +{ + uint8_t id; /* Sampled touch point ID */ + uint8_t contact; /* Contact state (see enum tc_contact_e) */ + bool valid; /* True: x,y contain valid, sampled data */ + uint16_t x; /* Thresholded X position */ + uint16_t y; /* Thresholded Y position */ +}; + +/* This structure describes the state of one touchscreen driver instance */ + +struct tc_dev_s +{ +#ifdef CONFIG_TOUCHSCREEN_REFCNT + uint8_t crefs; /* Number of times the device has been opened */ +#endif + uint8_t state; /* See enum tc_state_e */ + uint8_t nwaiters; /* Number of threads waiting for touchscreen data */ + uint8_t id; /* Current touch point ID */ + volatile bool penchange; /* An unreported event is buffered */ + uint16_t value; /* Partial sample value (Y+ or X-) */ + uint16_t newy; /* New, un-thresholded Y value */ + uint8_t sampcount; /* Count of samples for average so far */ + uint8_t resamplecount; /* Countdown to PENUP */ + mutex_t devlock; /* Manages exclusive access to this structure */ + sem_t waitsem; /* Used to wait for the availability of data */ + struct tc_sample_s sample; /* Last sampled touch point data */ + struct work_s work; /* Supports the state machine delayed processing */ + + /* The following is a list if poll structures of threads waiting for + * driver events. The 'struct pollfd' reference for each open is also + * retained in the f_priv field of the 'struct file'. + */ + + struct pollfd *fds[CONFIG_TOUCHSCREEN_NPOLLWAITERS]; +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +static void tc_adc_init(void); +static void tc_adc_start_sample(int pin); +static uint16_t tc_adc_read_sample(void); +static void tc_y_sample(void); +static void tc_x_sample(void); +static inline bool tc_valid_sample(uint16_t sample); + +static void tc_notify(struct tc_dev_s *priv); +static int tc_sample(struct tc_dev_s *priv, + struct tc_sample_s *sample); +static int tc_waitsample(struct tc_dev_s *priv, + struct tc_sample_s *sample); +static void tc_worker(void *arg); + +/* Character driver methods */ + +static int tc_open(struct file *filep); +static int tc_close(struct file *filep); +static ssize_t tc_read(struct file *filep, char *buffer, size_t len); +static int tc_ioctl(struct file *filep, int cmd, unsigned long arg); +static int tc_poll(struct file *filep, struct pollfd *fds, bool setup); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* This the vtable that supports the character driver interface */ + +static const struct file_operations g_tc_fops = +{ + tc_open, /* open */ + tc_close, /* close */ + tc_read, /* read */ + NULL, /* write */ + NULL, /* seek */ + tc_ioctl, /* ioctl */ + NULL, /* mmap */ + NULL, /* truncate */ + tc_poll /* poll */ +}; + +/* If only a single touchscreen device is supported, then the driver state + * structure may as well be pre-allocated. + */ + +#ifndef CONFIG_TOUCHSCREEN_MULTIPLE +static struct tc_dev_s g_touchscreen; +static bool g_touchinitdone = false; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: tc_adc_getreg + * + * Description: + * Read the value of an TC ADC channel (#2) register. + * + * Input Parameters: + * offset - The offset to the register to read + * value + * + * Returned Value: + * + ****************************************************************************/ + +static inline uint32_t tc_adc_getreg(int offset) +{ + return getreg32(TC_ADC_BASE + offset); +} + +/**************************************************************************** + * Name: tc_adc_putreg + * + * Description: + * Set the value of an ADC register. + * + * Input Parameters: + * offset - The offset to the register to read + * + * Returned Value: + * + ****************************************************************************/ + +static inline void tc_adc_putreg(int offset, uint32_t value) +{ + putreg32(value, TC_ADC_BASE + offset); +} + +/**************************************************************************** + * Name: tc_adc_init + * + * Description: + * Initialize ADC Channel #2 for use with the touch panel. The touch panel + * uses Channels 8 and 9 (PB0 and PB1) to read the X and Y axis touch + * positions. + * + ****************************************************************************/ + +static void tc_adc_init(void) +{ + irqstate_t flags; + uint32_t regval; + + /* Do an rcc reset to reset the ADC peripheral */ + + /* Disable interrupts. This is necessary because the APB2RTSR register + * is used by several different drivers. + */ + + flags = enter_critical_section(); + + /* Enable ADC reset state */ + + regval = getreg32(STM32_RCC_APB2RSTR); + regval |= RCC_APB2RSTR_ADCRST; + putreg32(regval, STM32_RCC_APB2RSTR); + + /* Release ADC from reset state */ + + regval &= ~RCC_APB2RSTR_ADCRST; + putreg32(regval, STM32_RCC_APB2RSTR); + + /* Initialize the watchdog high threshold register */ + + tc_adc_putreg(STM32_ADC_HTR_OFFSET, 0x00000fff); + + /* Initialize the watchdog low threshold register */ + + tc_adc_putreg(STM32_ADC_LTR_OFFSET, 0x00000000); + + /* Initialize the same sample time for each ADC 55.5 cycles + * + * During sample cycles channel selection bits must remain unchanged. + * + * 000: 1.5 cycles + * 001: 7.5 cycles + * 010: 13.5 cycles + * 011: 28.5 cycles + * 100: 41.5 cycles + * 101: 55.5 cycles + * 110: 71.5 cycles + * 111: 239.5 cycles + */ + + tc_adc_putreg(STM32_ADC_SMPR1_OFFSET, 0x00b6db6d); + tc_adc_putreg(STM32_ADC_SMPR2_OFFSET, 0x00b6db6d); + + /* ADC CR1 Configuration */ + + regval = tc_adc_getreg(STM32_ADC_CR1_OFFSET); + + /* Initialize the Analog watchdog enable */ + + regval &= ~ADC_CR1_AWDEN; + regval |= (LCD_YD_CHANNEL << ADC_CR1_AWDCH_SHIFT); + + /* Enable interrupt flags */ + + /* regval |= ADC_CR1_ALLINTS; */ + + /* Disable Overrun interrupt */ + + regval &= ~ADC_CR1_OVRIE; + + /* Set the resolution of the conversion. We only need 10 bits. */ + + regval |= ADC_CR1_RES_12BIT; + + tc_adc_putreg(STM32_ADC_CR1_OFFSET, regval); + + /* ADC CR2 Configuration */ + + regval = tc_adc_getreg(STM32_ADC_CR2_OFFSET); + + /* Clear CONT, continuous mode disable. We will perform single + * sampling on one channel at a time. + */ + + regval &= ~ADC_CR2_CONT; + + /* Set ALIGN (Right = 0) */ + + regval &= ~ADC_CR2_ALIGN; + + /* External trigger disable. We will do SW triggering */ + + regval &= ~ADC_CR2_EXTEN_MASK; + + tc_adc_putreg(STM32_ADC_CR2_OFFSET, regval); + + /* Configuration of the channel conversion - start with Y sampling */ + + regval = tc_adc_getreg(STM32_ADC_SQR3_OFFSET) & ADC_SQR3_RESERVED; + regval |= LCD_YD_CHANNEL; + tc_adc_putreg(STM32_ADC_SQR3_OFFSET, regval); + + /* Set the number of conversions = 1 */ + + regval = tc_adc_getreg(STM32_ADC_SQR1_OFFSET) & ADC_SQR1_RESERVED; + regval |= 0 << ADC_SQR1_L_SHIFT; + tc_adc_putreg(STM32_ADC_SQR1_OFFSET, regval); + + /* ADC CCR configuration */ + + regval = getreg32(STM32_ADC_CCR); + regval &= ~(ADC_CCR_MULTI_MASK | ADC_CCR_DELAY_MASK | ADC_CCR_DDS | + ADC_CCR_DMA_MASK | ADC_CCR_ADCPRE_MASK | ADC_CCR_VBATEN | + ADC_CCR_TSVREFE); + regval |= (ADC_CCR_MULTI_NONE | ADC_CCR_DMA_DISABLED | + ADC_CCR_ADCPRE_DIV2); + putreg32(regval, STM32_ADC_CCR); + + /* Set ADON to wake up the ADC from Power Down state. */ + + regval = tc_adc_getreg(STM32_ADC_CR2_OFFSET); + regval |= ADC_CR2_ADON; + tc_adc_putreg(STM32_ADC_CR2_OFFSET, regval); + + /* Restore the IRQ state */ + + leave_critical_section(flags); +} + +/**************************************************************************** + * Name: tc_adc_start_sample + * + * Description: + * Perform A/D sampling. Time must be allowed between the start of + * sampling and conversion (approx. 100Ms). + * + ****************************************************************************/ + +static void tc_adc_start_sample(int channel) +{ + uint32_t regval; + + /* Configure the specified channel for ADC conversion. */ + + regval = tc_adc_getreg(STM32_ADC_SQR3_OFFSET) & ADC_SQR3_RESERVED; + regval |= channel; + tc_adc_putreg(STM32_ADC_SQR3_OFFSET, regval); + + /* Configure the Watchdog for this channel */ + + regval = tc_adc_getreg(STM32_ADC_CR1_OFFSET) & ADC_CR1_AWDCH_MASK; + regval |= (channel << ADC_CR1_AWDCH_SHIFT); + tc_adc_putreg(STM32_ADC_CR1_OFFSET, regval); + + /* Start the conversion */ + + regval = tc_adc_getreg(STM32_ADC_CR2_OFFSET); + regval |= ADC_CR2_SWSTART; + tc_adc_putreg(STM32_ADC_CR2_OFFSET, regval); +} + +/**************************************************************************** + * Name: tc_adc_read_sample + * + * Description: + * Begin A/D conversion. Time must be allowed between the start of + * sampling and conversion (approx. 100Ms). + * + * Assumptions: + * 1) All output pins configured as outputs: + * 2) Appropriate pins are driven high and low + * + ****************************************************************************/ + +static uint16_t tc_adc_read_sample(void) +{ + uint16_t retval; + uint32_t adcsr; + uint16_t count = 0; + + /* Validate the conversion is complete */ + + adcsr = tc_adc_getreg(STM32_ADC_SR_OFFSET); + while ((adcsr & ADC_SR_EOC) == 0) + { + adcsr = tc_adc_getreg(STM32_ADC_SR_OFFSET); + count++; + } + + /* Read the sample */ + + retval = tc_adc_getreg(STM32_ADC_DR_OFFSET); + retval &= ADC_DR_RDATA_MASK; + + if (count > 0) + { + iinfo("Count = %d\n", count); + } + + return retval; +} + +/**************************************************************************** + * Name: tc_y_sample + * + * Description: + * Initiate sampling on Y + * + ****************************************************************************/ + +static void tc_y_sample(void) +{ + /* Start the Y axis sampling */ + + tc_adc_start_sample(LCD_XL_CHANNEL); +} + +/**************************************************************************** + * Name: tc_x_sample + * + * Description: + * Initiate sampling on X + * + ****************************************************************************/ + +static void tc_x_sample(void) +{ + /* Start the X axis sampling */ + + tc_adc_start_sample(LCD_YD_CHANNEL); +} + +/**************************************************************************** + * Name: tc_valid_sample + ****************************************************************************/ + +static inline bool tc_valid_sample(uint16_t sample) +{ + return (sample > LOWER_THRESHOLD); +} + +/**************************************************************************** + * Name: tc_notify + ****************************************************************************/ + +static void tc_notify(struct tc_dev_s *priv) +{ + /* If no threads have the driver open, then just dump the state */ + +#ifdef CONFIG_TOUCHSCREEN_REFCNT + if ((priv->crefs == 0) && priv->sample.contact == CONTACT_UP) + { + priv->sample.contact = CONTACT_NONE; + priv->sample.valid = false; + priv->id++; + return; + } +#endif + + /* If there are threads waiting on poll() for touchscreen data to become + * available, then wake them up now. NOTE: we wake up all waiting threads + * because we do not know that they are going to do. If they all try to + * read the data, then some make end up blocking after all. + */ + + poll_notify(priv->fds, CONFIG_TOUCHSCREEN_NPOLLWAITERS, POLLIN); + + /* If there are threads waiting for read data, then signal one of them + * that the read data is available. + */ + + if (priv->nwaiters > 0) + { + /* After posting this semaphore, we need to exit because the + * touchscreen is no longer available. + */ + + nxsem_post(&priv->waitsem); + } +} + +/**************************************************************************** + * Name: tc_sample + * + * Assumptions: pre-emption is disabled + * + ****************************************************************************/ + +static int tc_sample(struct tc_dev_s *priv, + struct tc_sample_s *sample) +{ + int ret = -EAGAIN; + + /* Is there new touchscreen sample data available? */ + + if (priv->penchange) + { + /* Yes.. the state has changed in some way. Return a copy of the + * sampled data. + */ + + memcpy(sample, &priv->sample, sizeof(struct tc_sample_s)); + + /* Now manage state transitions */ + + if (sample->contact == CONTACT_UP) + { + /* Next.. no contact. Increment the ID so that next contact ID + * will be unique. X/Y positions are no longer valid. + */ + + priv->sample.contact = CONTACT_NONE; + priv->sample.valid = false; + priv->id++; + } + else if (sample->contact == CONTACT_DOWN) + { + /* First report -- next report will be a movement */ + + priv->sample.contact = CONTACT_MOVE; + } + + priv->penchange = false; + ret = OK; + } + + return ret; +} + +/**************************************************************************** + * Name: tc_waitsample + ****************************************************************************/ + +static int tc_waitsample(struct tc_dev_s *priv, + struct tc_sample_s *sample) +{ + int ret; + irqstate_t flags; + + /* Interrupts must be disabled when this is called to (1) prevent posting + * of semaphores from interrupt handlers, and (2) to prevent sampled data + * from changing until it has been reported. + */ + + flags = enter_critical_section(); + + /* Now release the mutex that manages mutually exclusive access to + * the device structure. This may cause other tasks to become ready to + * run, but they cannot run yet because pre-emption is disabled. + */ + + nxmutex_unlock(&priv->devlock); + + /* Try to get the a sample... if we cannot, then wait on the semaphore + * that is posted when new sample data is available. + */ + + while (tc_sample(priv, sample) < 0) + { + /* Wait for a change in the touchscreen state */ + + priv->nwaiters++; + ret = nxsem_wait(&priv->waitsem); + priv->nwaiters--; + + if (ret < 0) + { + goto errout; + } + } + + /* Re-acquire the semaphore that manages mutually exclusive access to + * the device structure. We may have to wait here. But we have our + * sample. Interrupts and pre-emption will be re-enabled while we wait. + */ + + ret = nxmutex_lock(&priv->devlock); + +errout: + /* Then re-enable interrupts. We might get interrupt here and there + * could be a new sample. But no new threads will run because we still + * have pre-emption disabled. + */ + + leave_critical_section(flags); + return ret; +} + +/**************************************************************************** + * Name: tc_worker + ****************************************************************************/ + +static void tc_worker(void *arg) +{ + struct tc_dev_s *priv = (struct tc_dev_s *)arg; + uint32_t delay = TC_PENUP_POLL_TICKS; + uint16_t value; + uint16_t newx = 0; + int16_t xdiff; + int16_t ydiff; + + DEBUGASSERT(priv != NULL); + + /* Perform the next action based on the state of the conversions */ + + switch (priv->state) + { + /* The touchscreen is IDLE and we are ready to begin the next sample */ + + case TC_READY: + { + /* Select DRIVE for Y sampling */ + + /* Configure XL, XR with drive voltages and disable YU drive. Note + * that this is configuring the DRIVEA and DRIVEB outputs to enable + * the on-board transistor drive logic to energize the touch panel. + */ + + *((uint32_t *)LCD_TP_PORT_SETRESET) = LCD_SAMPY_BITS; + + /* Allow time for the Y DRIVE to settle */ + + priv->resamplecount = 0; + priv->sampcount = 0; + priv->value = 0; + priv->state = TC_READY_SETTLE; + delay = TC_SETTLE_TICKS; + } + break; + + case TC_READY_SETTLE: + { + /* Start Y sampling */ + + tc_y_sample(); + + /* Allow time for the Y pend down sampling */ + + priv->state = TC_YPENDOWN; + delay = TC_SAMPLE_TICKS; + } + break; + + /* The Y sampling time has elapsed and the Y value should be ready + * for conversion + */ + + case TC_YPENDOWN: + { + /* Convert the Y sample value */ + + value = tc_adc_read_sample(); + + /* A converted value at the minimum would mean that there is no touch + * and that the sampling period is complete. + */ + + if (!tc_valid_sample(value)) + { + priv->state = TC_PENUP; + } + else + { + /* Allow time for touch inputs to stabilize */ + + priv->state = TC_DEBOUNCE; + delay = TC_DEBOUNCE_TICKS; + } + } + break; + + /* The debounce time period has elapsed and we are ready to re-sample + * the touchscreen. + */ + + case TC_RESAMPLE: + { + /* Select DRIVE for Y sampling */ + + /* Configure XL, XR with drive voltages and disable YU drive. Note + * that this is configuring the DRIVEA and DRIVEB outputs to enable + * the on-board transistor drive logic to energize the touch panel. + */ + + *((uint32_t *)LCD_TP_PORT_SETRESET) = LCD_SAMPY_BITS; + + /* Allow time for the Y DRIVE to settle */ + + priv->state = TC_DEBOUNCE; + delay = TC_SETTLE_TICKS; + } + break; + + case TC_DEBOUNCE: + { + /* (Re-)start Y sampling */ + + tc_y_sample(); + + /* Allow time for the Y sampling */ + + priv->state = TC_YSAMPLE; + delay = TC_SAMPLE_TICKS; + } + break; + + /* The Y sampling period has elapsed and we are ready to perform the + * conversion. + */ + + case TC_YSAMPLE: /* Allowing time for the Y sampling */ + { + /* Read the Y axis position */ + + value = tc_adc_read_sample(); + + /* A converted value at the minimum would mean that we lost the + * contact before all of the conversions were completed. At + * converted value at the maximum value is probably bad too. + */ + + if (!tc_valid_sample(value)) + { +#ifdef CONFIG_TOUCHSCREEN_RESAMPLE + priv->state = TC_RESAMPLE; + delay = TC_RESAMPLE_TICKS; +#else + priv->state = TC_PENUP; +#endif + } + else + { + value = MAX_ADC - value; + priv->value += value; + if (++priv->sampcount < CONFIG_TOUCHSCREEN_AVG_SAMPLES) + { + priv->state = TC_READY_SETTLE; + delay = 1; + break; + } + + priv->newy = value / CONFIG_TOUCHSCREEN_AVG_SAMPLES; + priv->value = 0; + priv->sampcount = 0; + iinfo("Y=%d\n", priv->newy); + + /* Configure YU and YD with drive voltages and disable XR drive. + * Note that this is configuring the DRIVEA and DRIVEB outputs + * to enable the on-board transistor drive logic to energize the + * touch panel. + */ + + *((uint32_t *)LCD_TP_PORT_SETRESET) = LCD_SAMPX_BITS; + + /* Allow time for the X sampling */ + + priv->state = TC_XSETTLE; + delay = TC_SETTLE_TICKS; + } + } + break; + + case TC_XRESAMPLE: /* Perform X resampling */ + { + if (priv->resamplecount-- == 0) + { + priv->state = TC_PENUP; + break; + } + } + + case TC_XSETTLE: /* Allowing time X to settle after changing DRIVE */ + { + /* The X Drive settling time has elaspsed and it's time to start + * the conversion + */ + + /* Start X sampling */ + + tc_x_sample(); + + /* Allow time for the X sampling */ + + priv->state = TC_XSAMPLE; + delay = TC_SAMPLE_TICKS; + } + break; + + case TC_XSAMPLE: /* Allowing time for the X sampling */ + { + /* Read the converted X axis position */ + + value = tc_adc_read_sample(); + + /* A converted value at the minimum would mean that we lost the + * contact before all of the conversions were completed. At + * converted value at the maximum value is probably bad too. + */ + + if (!tc_valid_sample(value)) + { +#ifdef CONFIG_TOUCHSCREEN_RESAMPLE + priv->state = TC_XRESAMPLE; + if (priv->resamplecount == 0) + priv->resamplecount = 1; + delay = TC_RESAMPLE_TICKS; +#else + priv->state = TC_PENUP; +#endif + } + else + { + /* Calculate the X axis position */ + + priv->value += value; + if (++priv->sampcount < CONFIG_TOUCHSCREEN_AVG_SAMPLES) + { + priv->state = TC_XSETTLE; + delay = 1; + break; + } + + newx = value / CONFIG_TOUCHSCREEN_AVG_SAMPLES; + iinfo("X=%d\n", newx); + + /* Samples are available */ + + priv->state = TC_PENDOWN; + } + } + break; + } + + /* Check for terminal conditions.. */ + + /* Check if the sampling resulted in a pen up decision. If so, we need to + * handle the change from pen down to pen up. + */ + + if (priv->state == TC_PENUP) + { + /* Ignore if the pen was already down (CONTACT_NONE == pen up and + * already reported. CONTACT_UP == pen up, but not reported) + */ + + if (priv->sample.contact != CONTACT_NONE && + priv->sample.contact != CONTACT_UP) + { + /* The pen is up. We know from the above test, that this is a + * loss of contact condition. This will be changed to CONTACT_NONE + * after the loss of contact is sampled. + */ + + priv->sample.contact = CONTACT_UP; + + /* Indicate the availability of new sample data for this ID */ + + priv->sample.id = priv->id; + priv->penchange = true; + + /* Notify any waiters that new touchscreen data is available */ + + iinfo("1:X=%d, Y=%d\n", priv->sample.x, priv->sample.y); + + tc_notify(priv); + } + + /* Set up for the next poll */ + + priv->sample.valid = false; + priv->state = TC_READY; + delay = TC_PENUP_POLL_TICKS; + } + + /* Check if the sampling resulted in a pen down decision. */ + + else if (priv->state == TC_PENDOWN) + { + /* It is a pen down event. If the last loss-of-contact event has not + * been processed yet, then we have to ignore the pen down event (or + * else it will look like a drag event) + */ + + if (priv->sample.contact != CONTACT_UP) + { + /* Perform a thresholding operation so that the results will be + * more stable. If the difference from the last sample is small, + * then ignore the event. + */ + + xdiff = (int16_t)priv->sample.x - (int16_t)newx; + if (xdiff < 0) + { + xdiff = -xdiff; + } + + ydiff = (int16_t)priv->sample.y - (int16_t)priv->newy; + if (ydiff < 0) + { + ydiff = -ydiff; + } + + if (xdiff >= CONFIG_TOUCHSCREEN_THRESHX || + ydiff >= CONFIG_TOUCHSCREEN_THRESHY) + { + /* There is some change above the threshold... + * Report the change. + */ + +#ifdef CONFIG_LCD_LANDSCAPE + priv->sample.x = MAX_ADC - priv->newy; + priv->sample.y = newx; +#else + priv->sample.x = newx; + priv->sample.y = priv->newy; +#endif + priv->sample.valid = true; + + /* If this is the first (acknowledged) penddown report, then + * report this as the 1st contact. If contact == CONTACT_DOWN, + * it will be set to set to CONTACT_MOVE after the contact is + * first sampled. + */ + + if (priv->sample.contact != CONTACT_MOVE) + { + /* First contact */ + + priv->sample.contact = CONTACT_DOWN; + } + + /* Indicate the availability of new sample data for this ID */ + + priv->sample.id = priv->id; + priv->penchange = true; + + /* Notify any waiters that nes touchscreen data is available */ + + iinfo("2:X=%d, Y=%d\n", priv->sample.x, priv->sample.y); + + tc_notify(priv); + } + } + + /* Set up for the next poll */ + + priv->state = TC_READY; + delay = TC_PENDOWN_POLL_TICKS; + } + + /* Set up the next sample event */ + + work_queue(HPWORK, &priv->work, tc_worker, priv, delay); +} + +/**************************************************************************** + * Name: tc_open + ****************************************************************************/ + +static int tc_open(struct file *filep) +{ +#ifdef CONFIG_TOUCHSCREEN_REFCNT + struct inode *inode; + struct tc_dev_s *priv; + uint8_t tmp; + int ret; + + inode = filep->f_inode; + + DEBUGASSERT(inode->i_private); + priv = inode->i_private; + + /* Get exclusive access to the driver data structure */ + + ret = nxmutex_lock(&priv->devlock); + if (ret < 0) + { + return ret; + } + + /* Increment the reference count */ + + tmp = priv->crefs + 1; + if (tmp == 0) + { + /* More than 255 opens; uint8_t overflows to zero */ + + ret = -EMFILE; + goto errout_with_lock; + } + + /* When the reference increments to 1, this is the first open event + * on the driver.. and an opportunity to do any one-time initialization. + */ + + /* Save the new open count on success */ + + priv->crefs = tmp; + +errout_with_lock: + nxmutex_unlock(&priv->devlock); + return ret; +#else + return OK; +#endif +} + +/**************************************************************************** + * Name: tc_close + ****************************************************************************/ + +static int tc_close(struct file *filep) +{ +#ifdef CONFIG_TOUCHSCREEN_REFCNT + struct inode *inode; + struct tc_dev_s *priv; + int ret; + + inode = filep->f_inode; + + DEBUGASSERT(inode->i_private); + priv = inode->i_private; + + /* Get exclusive access to the driver data structure */ + + ret = nxmutex_lock(&priv->devlock); + if (ret < 0) + { + return ret; + } + + /* Decrement the reference count unless it would decrement a negative + * value. When the count decrements to zero, there are no further + * open references to the driver. + */ + + if (priv->crefs >= 1) + { + priv->crefs--; + } + + nxmutex_unlock(&priv->devlock); +#endif + return OK; +} + +/**************************************************************************** + * Name: tc_read + ****************************************************************************/ + +static ssize_t tc_read(struct file *filep, char *buffer, size_t len) +{ + struct inode *inode; + struct tc_dev_s *priv; + struct touch_sample_s *report; + struct tc_sample_s sample; + int ret; + + inode = filep->f_inode; + + DEBUGASSERT(inode->i_private); + priv = inode->i_private; + + /* Verify that the caller has provided a buffer large enough to receive + * the touch data. + */ + + if (len < SIZEOF_TOUCH_SAMPLE_S(1)) + { + /* We could provide logic to break up a touch report into segments and + * handle smaller reads... but why? + */ + + return -ENOSYS; + } + + /* Get exclusive access to the driver data structure */ + + ret = nxmutex_lock(&priv->devlock); + if (ret < 0) + { + return ret; + } + + /* Try to read sample data. */ + + ret = tc_sample(priv, &sample); + if (ret < 0) + { + /* Sample data is not available now. We would ave to wait to get + * receive sample data. If the user has specified the O_NONBLOCK + * option, then just return an error. + */ + + if (filep->f_oflags & O_NONBLOCK) + { + ret = -EAGAIN; + goto errout; + } + + /* Wait for sample data */ + + ret = tc_waitsample(priv, &sample); + if (ret < 0) + { + /* We might have been awakened by a signal */ + + goto errout; + } + } + + /* In any event, we now have sampled touchscreen data that we can report + * to the caller. + */ + + report = (struct touch_sample_s *)buffer; + memset(report, 0, SIZEOF_TOUCH_SAMPLE_S(1)); + report->npoints = 1; + report->point[0].id = sample.id; + report->point[0].x = sample.x; + report->point[0].y = sample.y; + + /* Report the appropriate flags */ + + if (sample.contact == CONTACT_UP) + { + /* Pen is now up. Is the positional data valid? This is important to + * know because the release will be sent to the window based on its + * last positional data. + */ + + if (sample.valid) + { + report->point[0].flags = TOUCH_UP | TOUCH_ID_VALID | + TOUCH_POS_VALID | TOUCH_PRESSURE_VALID; + } + else + { + report->point[0].flags = TOUCH_UP | TOUCH_ID_VALID; + } + } + else + { + if (sample.contact == CONTACT_DOWN) + { + /* First contact */ + + report->point[0].flags = TOUCH_DOWN | TOUCH_ID_VALID | + TOUCH_POS_VALID; + } + else /* if (sample->contact == CONTACT_MOVE) */ + { + /* Movement of the same contact */ + + report->point[0].flags = TOUCH_MOVE | TOUCH_ID_VALID | + TOUCH_POS_VALID; + } + } + + ret = SIZEOF_TOUCH_SAMPLE_S(1); + +errout: + nxmutex_unlock(&priv->devlock); + return ret; +} + +/**************************************************************************** + * Name: tc_ioctl + ****************************************************************************/ + +static int tc_ioctl(struct file *filep, int cmd, unsigned long arg) +{ +#if 1 + iinfo("cmd: %d arg: %ld\n", cmd, arg); + return -ENOTTY; /* None yet supported */ +#else + struct inode *inode; + struct tc_dev_s *priv; + int ret; + + iinfo("cmd: %d arg: %ld\n", cmd, arg); + inode = filep->f_inode; + + DEBUGASSERT(inode->i_private); + priv = inode->i_private; + + /* Get exclusive access to the driver data structure */ + + ret = nxmutex_lock(&priv->devlock); + if (ret < 0) + { + return ret; + } + + /* Process the IOCTL by command */ + + switch (cmd) + { + /* ADD IOCTL COMMAND CASES HERE */ + + default: + ret = -ENOTTY; + break; + } + + nxmutex_unlock(&priv->devlock); + return ret; +#endif +} + +/**************************************************************************** + * Name: tc_poll + ****************************************************************************/ + +static int tc_poll(struct file *filep, struct pollfd *fds, bool setup) +{ + struct inode *inode; + struct tc_dev_s *priv; + int ret; + int i; + + iinfo("setup: %d\n", (int)setup); + DEBUGASSERT(fds); + inode = filep->f_inode; + + DEBUGASSERT(inode->i_private); + priv = inode->i_private; + + /* Are we setting up the poll? Or tearing it down? */ + + ret = nxmutex_lock(&priv->devlock); + if (ret < 0) + { + return ret; + } + + if (setup) + { + /* Ignore waits that do not include POLLIN */ + + if ((fds->events & POLLIN) == 0) + { + ierr("ERROR: Missing POLLIN: revents: %08" PRIx32 "\n", + fds->revents); + ret = -EDEADLK; + goto errout; + } + + /* This is a request to set up the poll. Find an available + * slot for the poll structure reference + */ + + for (i = 0; i < CONFIG_TOUCHSCREEN_NPOLLWAITERS; i++) + { + /* Find an available slot */ + + if (!priv->fds[i]) + { + /* Bind the poll structure and this slot */ + + priv->fds[i] = fds; + fds->priv = &priv->fds[i]; + break; + } + } + + if (i >= CONFIG_TOUCHSCREEN_NPOLLWAITERS) + { + ierr("ERROR: No available slot found: %d\n", i); + fds->priv = NULL; + ret = -EBUSY; + goto errout; + } + + /* Should we immediately notify on any of the requested events? */ + + if (priv->penchange) + { + poll_notify(&fds, 1, POLLIN); + } + } + else if (fds->priv) + { + /* This is a request to tear down the poll. */ + + struct pollfd **slot = (struct pollfd **)fds->priv; + DEBUGASSERT(slot != NULL); + + /* Remove all memory of the poll setup */ + + *slot = NULL; + fds->priv = NULL; + } + +errout: + nxmutex_unlock(&priv->devlock); + return ret; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_tsc_setup + * + * Description: + * This function is called by board-bringup logic to configure the + * touchscreen device. This function will register the driver as + * /dev/inputN where N is the minor device number. + * + * Input Parameters: + * minor - The input device minor number + * + * Returned Value: + * Zero is returned on success. Otherwise, a negated errno value is + * returned to indicate the nature of the failure. + * + ****************************************************************************/ + +int stm32_tsc_setup(int minor) +{ + struct tc_dev_s *priv; + char devname[DEV_NAMELEN]; +#ifdef CONFIG_TOUCHSCREEN_MULTIPLE + irqstate_t flags; +#endif + int ret; + + iinfo("minor: %d\n", minor); + DEBUGASSERT(minor >= 0 && minor < 100); + + /* If we only have one touchscreen, check if we already did init */ + +#ifndef CONFIG_TOUCHSCREEN_MULTIPLE + if (g_touchinitdone) + { + return OK; + } +#endif + + /* Configure the touchscreen DRIVEA and DRIVEB pins for output */ + + stm32_configgpio(GPIO_TP_DRIVEA); + stm32_configgpio(GPIO_TP_DRIVEB); + + /* Configure Analog inputs for sampling X and Y coordinates */ + + stm32_configgpio(GPIO_TP_XL); + stm32_configgpio(GPIO_TP_YD); + + tc_adc_init(); + + /* Create and initialize a touchscreen device driver instance */ + +#ifndef CONFIG_TOUCHSCREEN_MULTIPLE + priv = &g_touchscreen; +#else + priv = kmm_malloc(sizeof(struct tc_dev_s)); + if (!priv) + { + ierr("ERROR: kmm_malloc(%d) failed\n", sizeof(struct tc_dev_s)); + return -ENOMEM; + } +#endif + + /* Initialize the touchscreen device driver instance */ + + memset(priv, 0, sizeof(struct tc_dev_s)); + nxmutex_init(&priv->devlock); /* Initialize device structure mutex */ + nxsem_init(&priv->waitsem, 0, 0); /* Initialize pen event wait semaphore */ + + /* Register the device as an input device */ + + snprintf(devname, sizeof(devname), DEV_FORMAT, minor); + iinfo("Registering %s\n", devname); + + ret = register_driver(devname, &g_tc_fops, 0666, priv); + if (ret < 0) + { + ierr("ERROR: register_driver() failed: %d\n", ret); + goto errout_with_priv; + } + + /* Schedule work to perform the initial sampling and to set the data + * availability conditions. + */ + + priv->state = TC_READY; + ret = work_queue(HPWORK, &priv->work, tc_worker, priv, 0); + if (ret != 0) + { + ierr("ERROR: Failed to queue work: %d\n", ret); + goto errout_with_priv; + } + + /* And return success (?) */ + +#ifndef CONFIG_TOUCHSCREEN_MULTIPLE + g_touchinitdone = true; +#endif + + return OK; + +errout_with_priv: + nxmutex_destroy(&priv->devlock); + nxsem_destroy(&priv->waitsem); +#ifdef CONFIG_TOUCHSCREEN_MULTIPLE + kmm_free(priv); +#endif + return ret; +} + +#endif /* CONFIG_INPUT */ diff --git a/boards/arm/stm32f4/mikroe-stm32f4/src/stm32_usb.c b/boards/arm/stm32f4/mikroe-stm32f4/src/stm32_usb.c new file mode 100644 index 0000000000000..fc2c9b7af8f0c --- /dev/null +++ b/boards/arm/stm32f4/mikroe-stm32f4/src/stm32_usb.c @@ -0,0 +1,304 @@ +/**************************************************************************** + * boards/arm/stm32f4/mikroe-stm32f4/src/stm32_usb.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include "arm_internal.h" +#include "stm32.h" +#include "stm32_otgfs.h" +#include "mikroe-stm32f4.h" + +#ifdef CONFIG_STM32_OTGFS + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#if defined(CONFIG_USBDEV) || defined(CONFIG_USBHOST) +# define HAVE_USB 1 +#else +# warning "CONFIG_STM32_OTGFS is enabled but neither CONFIG_USBDEV nor CONFIG_USBHOST" +# undef HAVE_USB +#endif + +#ifndef CONFIG_USBHOST_DEFPRIO +# define CONFIG_USBHOST_DEFPRIO 50 +#endif + +#ifndef CONFIG_USBHOST_STACKSIZE +# ifdef CONFIG_USBHOST_HUB +# define CONFIG_USBHOST_STACKSIZE 1536 +# else +# define CONFIG_USBHOST_STACKSIZE 1024 +# endif +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +static struct usbhost_connection_s *g_usbconn; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: usbhost_waiter + * + * Description: + * Wait for USB devices to be connected. + * + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +static int usbhost_waiter(int argc, char *argv[]) +{ + struct usbhost_hubport_s *hport; + + uinfo("Running\n"); + for (; ; ) + { + /* Wait for the device to change state */ + + DEBUGVERIFY(CONN_WAIT(g_usbconn, &hport)); + uinfo("%s\n", hport->connected ? "connected" : "disconnected"); + + /* Did we just become connected? */ + + if (hport->connected) + { + /* Yes.. enumerate the newly connected device */ + + CONN_ENUMERATE(g_usbconn, hport); + } + } + + /* Keep the compiler from complaining */ + + return 0; +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_usbinitialize + * + * Description: + * Called from stm32_usbinitialize very early in initialization to setup + * USB-related GPIO pins for the STM32F4Discovery board. + * + ****************************************************************************/ + +void stm32_usbinitialize(void) +{ + /* The OTG FS has an internal soft pull-up. + * No GPIO configuration is required + */ + + /* Configure the OTG FS VBUS sensing GPIO, + * Power On, and Overcurrent GPIOs + */ + +#ifdef CONFIG_STM32_OTGFS + stm32_configgpio(GPIO_OTGFS_VBUS); + stm32_configgpio(GPIO_OTGFS_PWRON); + stm32_configgpio(GPIO_OTGFS_OVER); +#endif +} + +/**************************************************************************** + * Name: stm32_usbhost_initialize + * + * Description: + * Called at application startup time to initialize the USB host + * functionality. + * This function will start a thread that will monitor for device + * connection/disconnection events. + * + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +int stm32_usbhost_initialize(void) +{ + int ret; + + /* First, register all of the class drivers needed to support the drivers + * that we care about: + */ + + uinfo("Register class drivers\n"); + +#ifdef CONFIG_USBHOST_MSC + /* Register the USB host Mass Storage Class */ + + ret = usbhost_msc_initialize(); + if (ret != OK) + { + uerr("ERROR: Failed to register the mass storage class: %d\n", ret); + } +#endif + +#ifdef CONFIG_USBHOST_CDCACM + /* Register the CDC/ACM serial class */ + + ret = usbhost_cdcacm_initialize(); + if (ret != OK) + { + uerr("ERROR: Failed to register the CDC/ACM serial class: %d\n", ret); + } +#endif + + /* Then get an instance of the USB host interface */ + + uinfo("Initialize USB host\n"); + g_usbconn = stm32_otgfshost_initialize(0); + if (g_usbconn) + { + /* Start a thread to handle device connection. */ + + uinfo("Start usbhost_waiter\n"); + + ret = kthread_create("usbhost", CONFIG_USBHOST_DEFPRIO, + CONFIG_USBHOST_STACKSIZE, + usbhost_waiter, NULL); + return ret < 0 ? -ENOEXEC : OK; + } + + return -ENODEV; +} +#endif + +/**************************************************************************** + * Name: stm32_usbhost_vbusdrive + * + * Description: + * Enable/disable driving of VBUS 5V output. This function must be + * provided be each platform that implements the STM32 OTG FS host + * interface + * + * "On-chip 5 V VBUS generation is not supported. For this reason, a + * charge pump or, if 5 V are available on the application board, a + * basic power switch, must be added externally to drive the 5 V VBUS + * line. The external charge pump can be driven by any GPIO output. + * When the application decides to power on VBUS using the chosen GPIO, + * it must also set the port power bit in the host port control and + * status register (PPWR bit in OTG_FS_HPRT). + * + * "The application uses this field to control power to this port, + * and the core clears this bit on an overcurrent condition." + * + * Input Parameters: + * iface - For future growth to handle multiple USB host interface. + * Should be zero. + * enable - true: enable VBUS power; false: disable VBUS power + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +void stm32_usbhost_vbusdrive(int iface, bool enable) +{ + DEBUGASSERT(iface == 0); + + if (enable) + { + /* Enable the Power Switch by driving the enable pin low */ + + stm32_gpiowrite(GPIO_OTGFS_PWRON, false); + } + else + { + /* Disable the Power Switch by driving the enable pin high */ + + stm32_gpiowrite(GPIO_OTGFS_PWRON, true); + } +} +#endif + +/**************************************************************************** + * Name: stm32_setup_overcurrent + * + * Description: + * Setup to receive an interrupt-level callback if an overcurrent + * condition is detected. + * + * Input Parameters: + * handler - New overcurrent interrupt handler + * arg - The argument provided for the interrupt handler + * + * Returned Value: + * Zero (OK) is returned on success. Otherwise, a negated errno value + * is returned to indicate the nature of the failure. + * + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +int stm32_setup_overcurrent(xcpt_t handler, void *arg) +{ + return stm32_gpiosetevent(GPIO_OTGFS_OVER, true, true, true, handler, arg); +} +#endif + +/**************************************************************************** + * Name: stm32_usbsuspend + * + * Description: + * Board logic must provide the stm32_usbsuspend logic if the USBDEV + * driver is used. This function is called whenever the USB enters or + * leaves suspend mode. This is an opportunity for the board logic to + * shutdown clocks, power, etc. while the USB is suspended. + * + ****************************************************************************/ + +#ifdef CONFIG_USBDEV +void stm32_usbsuspend(struct usbdev_s *dev, bool resume) +{ + uinfo("resume: %d\n", resume); +} +#endif + +#endif /* CONFIG_STM32_OTGFS */ diff --git a/boards/arm/stm32/mikroe-stm32f4/src/stm32_vs1053.c b/boards/arm/stm32f4/mikroe-stm32f4/src/stm32_vs1053.c similarity index 99% rename from boards/arm/stm32/mikroe-stm32f4/src/stm32_vs1053.c rename to boards/arm/stm32f4/mikroe-stm32f4/src/stm32_vs1053.c index 00f3c919e2e8c..938fa1764412d 100644 --- a/boards/arm/stm32/mikroe-stm32f4/src/stm32_vs1053.c +++ b/boards/arm/stm32f4/mikroe-stm32f4/src/stm32_vs1053.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/mikroe-stm32f4/src/stm32_vs1053.c + * boards/arm/stm32f4/mikroe-stm32f4/src/stm32_vs1053.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f4/nucleo-f401re/CMakeLists.txt b/boards/arm/stm32f4/nucleo-f401re/CMakeLists.txt new file mode 100644 index 0000000000000..a8b1f68f8e169 --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f401re/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32f4/nucleo-f401re/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/arm/stm32/nucleo-f401re/Kconfig b/boards/arm/stm32f4/nucleo-f401re/Kconfig similarity index 100% rename from boards/arm/stm32/nucleo-f401re/Kconfig rename to boards/arm/stm32f4/nucleo-f401re/Kconfig diff --git a/boards/arm/stm32f4/nucleo-f401re/configs/fb/defconfig b/boards/arm/stm32f4/nucleo-f401re/configs/fb/defconfig new file mode 100644 index 0000000000000..7e41a42500837 --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f401re/configs/fb/defconfig @@ -0,0 +1,63 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_ARCH_LEDS is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nucleo-f401re" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_NUCLEO_F401RE=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F401RE=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=8499 +CONFIG_BUILTIN=y +CONFIG_DRIVERS_VIDEO=y +CONFIG_EXAMPLES_FB=y +CONFIG_FB_MODULEINFO=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LCD=y +CONFIG_LCD_DEV=y +CONFIG_LCD_FRAMEBUFFER=y +CONFIG_LCD_UG2864HSWEG01=y +CONFIG_LINE_MAX=64 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=98304 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_SPI_CMDDATA=y +CONFIG_SPI_DRIVER=y +CONFIG_SSD1306_FREQUENCY=1000000 +CONFIG_START_DAY=5 +CONFIG_START_MONTH=5 +CONFIG_START_YEAR=2014 +CONFIG_STM32_I2C1=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PWR=y +CONFIG_STM32_SPI1=y +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART2_SERIAL_CONSOLE=y +CONFIG_VIDEO_FB=y diff --git a/boards/arm/stm32f4/nucleo-f401re/configs/nsh/defconfig b/boards/arm/stm32f4/nucleo-f401re/configs/nsh/defconfig new file mode 100644 index 0000000000000..691067a8b3ab0 --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f401re/configs/nsh/defconfig @@ -0,0 +1,49 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nucleo-f401re" +CONFIG_ARCH_BOARD_NUCLEO_F401RE=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F401RE=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=8499 +CONFIG_BUILTIN=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=98304 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_SPI=y +CONFIG_START_DAY=5 +CONFIG_START_MONTH=5 +CONFIG_START_YEAR=2014 +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PWR=y +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f4/nucleo-f401re/include/board.h b/boards/arm/stm32f4/nucleo-f401re/include/board.h new file mode 100644 index 0000000000000..f8cff6a2383a6 --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f401re/include/board.h @@ -0,0 +1,380 @@ +/**************************************************************************** + * boards/arm/stm32f4/nucleo-f401re/include/board.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_STM32_NUCLEO_F401RE_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32_NUCLEO_F401RE_INCLUDE_BOARD_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#ifndef __ASSEMBLY__ +# include +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Clocking *****************************************************************/ + +/* The NUCLEO401RE supports both HSE and LSE crystals (X2 and X3). + * However, as shipped, the X2 and X3 crystals are not populated. + * Therefore the Nucleo-F401RE will need to run off the 16MHz HSI clock. + * + * System Clock source : PLL (HSI) + * SYSCLK(Hz) : 84000000 Determined by PLL + * configuration + * HCLK(Hz) : 84000000 (STM32_RCC_CFGR_HPRE) + * AHB Prescaler : 1 (STM32_RCC_CFGR_HPRE) + * APB1 Prescaler : 2 (STM32_RCC_CFGR_PPRE1) + * APB2 Prescaler : 1 (STM32_RCC_CFGR_PPRE2) + * HSI Frequency(Hz) : 16000000 (nominal) + * PLLM : 16 (STM32_PLLCFG_PLLM) + * PLLN : 336 (STM32_PLLCFG_PLLN) + * PLLP : 4 (STM32_PLLCFG_PLLP) + * PLLQ : 7 (STM32_PLLCFG_PPQ) + * Flash Latency(WS) : 5 + * Prefetch Buffer : OFF + * Instruction cache : ON + * Data cache : ON + * Require 48MHz for USB OTG FS, : Enabled + * SDIO and RNG clock + */ + +/* HSI - 16 MHz RC factory-trimmed + * LSI - 32 KHz RC + * HSE - not installed + * LSE - not installed + */ + +#define STM32_HSI_FREQUENCY 16000000ul +#define STM32_LSI_FREQUENCY 32000 +#define STM32_BOARD_USEHSI 1 + +/* Main PLL Configuration. + * + * Formulae: + * + * VCO input frequency = PLL input clock frequency / PLLM, + * 2 <= PLLM <= 63 + * VCO output frequency = VCO input frequency × PLLN, + * 192 <= PLLN <= 432 + * PLL output clock frequency = VCO frequency / PLLP, + * PLLP = 2, 4, 6, or 8 + * USB OTG FS clock frequency = VCO frequency / PLLQ, + * 2 <= PLLQ <= 15 + * + * We would like to have SYSYCLK=84MHz and we must have the USB clock= 48MHz. + * Some possible solutions include: + * + * PLLN=210 PLLM=5 PLLP=8 PLLQ=14 SYSCLK=84000000 OTGFS=48000000 + * PLLN=210 PLLM=10 PLLP=4 PLLQ=7 SYSCLK=84000000 OTGFS=48000000 + * PLLN=336 PLLM=8 PLLP=8 PLLQ=14 SYSCLK=84000000 OTGFS=48000000 + * PLLN=336 PLLM=16 PLLP=4 PLLQ=7 SYSCLK=84000000 OTGFS=48000000 + * PLLN=420 PLLM=10 PLLP=8 PLLQ=14 SYSCLK=84000000 OTGFS=48000000 + * PLLN=420 PLLM=20 PLLP=4 PLLQ=7 SYSCLK=84000000 OTGFS=48000000 + * + * We will configure like this + * + * PLL source is HSI + * PLL_VCO = (STM32_HSI_FREQUENCY / PLLM) * PLLN + * = (16,000,000 / 16) * 336 + * = 336,000,000 + * SYSCLK = PLL_VCO / PLLP + * = 336,000,000 / 4 = 84,000,000 + * USB OTG FS and SDIO Clock + * = PLL_VCO / PLLQ + * = 336,000,000 / 7 = 48,000,000 + * + * REVISIT: Trimming of the HSI is not yet supported. + */ + +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(16) +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(336) +#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_4 +#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(7) + +#define STM32_SYSCLK_FREQUENCY 84000000ul + +/* AHB clock (HCLK) is SYSCLK (84MHz) */ + +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY + +/* APB1 clock (PCLK1) is HCLK/2 (42MHz) */ + +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd2 /* PCLK1 = HCLK / 2 */ +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/2) + +/* Timers driven from APB1 will be twice PCLK1 */ + +/* REVISIT */ + +#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) + +/* APB2 clock (PCLK2) is HCLK (84MHz) */ + +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ +#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/1) + +/* Timers driven from APB2 will be twice PCLK2 */ + +/* REVISIT */ + +#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM9_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB2_TIM10_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB2_TIM11_CLKIN (2*STM32_PCLK1_FREQUENCY) + +/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx + * otherwise frequency is 2xAPBx. + * Note: TIM1,8 are on APB2, others on APB1 + */ + +/* REVISIT */ + +#define BOARD_TIM1_FREQUENCY (2*STM32_PCLK2_FREQUENCY) +#define BOARD_TIM2_FREQUENCY (2*STM32_PCLK1_FREQUENCY) +#define BOARD_TIM3_FREQUENCY (2*STM32_PCLK1_FREQUENCY) +#define BOARD_TIM4_FREQUENCY (2*STM32_PCLK1_FREQUENCY) +#define BOARD_TIM5_FREQUENCY (2*STM32_PCLK1_FREQUENCY) +#define BOARD_TIM6_FREQUENCY (2*STM32_PCLK1_FREQUENCY) +#define BOARD_TIM7_FREQUENCY (2*STM32_PCLK1_FREQUENCY) +#define BOARD_TIM8_FREQUENCY (2*STM32_PCLK2_FREQUENCY) + +/* SDIO dividers. Note that slower clocking is required when DMA is disabled + * in order to avoid RX overrun/TX underrun errors due to delayed responses + * to service FIFOs in interrupt driven mode. These values have not been + * tuned!!! + * + * HCLK=72MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(178+2)=400 KHz + */ + +/* REVISIT */ + +#define SDIO_INIT_CLKDIV (178 << SDIO_CLKCR_CLKDIV_SHIFT) + +/* DMA ON: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(2+2)=18 MHz + * DMA OFF: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(3+2)=14.4 MHz + */ + +/* REVISIT */ + +#ifdef CONFIG_SDIO_DMA +# define SDIO_MMCXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT) +#else +# define SDIO_MMCXFR_CLKDIV (3 << SDIO_CLKCR_CLKDIV_SHIFT) +#endif + +/* DMA ON: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(1+2)=24 MHz + * DMA OFF: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(3+2)=14.4 MHz + */ + +/* REVISIT */ + +#ifdef CONFIG_SDIO_DMA +# define SDIO_SDXFR_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT) +#else +# define SDIO_SDXFR_CLKDIV (3 << SDIO_CLKCR_CLKDIV_SHIFT) +#endif + +/* DMA Channel/Stream Selections ********************************************/ + +/* Stream selections are arbitrary for now but might become important in + * the future is we set aside more DMA channels/streams. + * + * SDIO DMA + *   DMAMAP_SDIO_1 = Channel 4, Stream 3 <- may later be used by SPI DMA + *   DMAMAP_SDIO_2 = Channel 4, Stream 6 + */ + +#define DMAMAP_SDIO DMAMAP_SDIO_1 + +/* Need to VERIFY fwb */ + +#define DMACHAN_SPI1_RX DMAMAP_SPI1_RX_1 +#define DMACHAN_SPI1_TX DMAMAP_SPI1_TX_1 +#define DMACHAN_SPI2_RX DMAMAP_SPI2_RX +#define DMACHAN_SPI2_TX DMAMAP_SPI2_TX + +/* Alternate function pin selections ****************************************/ + +/* USART1: + * RXD: PA10 CN9 pin 3, CN10 pin 33 + * PB7 CN7 pin 21 + * TXD: PA9 CN5 pin 1, CN10 pin 21 + * PB6 CN5 pin 3, CN10 pin 17 + */ + +#if 1 +# define GPIO_USART1_RX (GPIO_USART1_RX_1|GPIO_SPEED_100MHz) /* PA10 */ +# define GPIO_USART1_TX (GPIO_USART1_TX_1|GPIO_SPEED_100MHz) /* PA9 */ +#else +# define GPIO_USART1_RX (GPIO_USART1_RX_2|GPIO_SPEED_100MHz) /* PB7 */ +# define GPIO_USART1_TX (GPIO_USART1_TX_2|GPIO_SPEED_100MHz) /* PB6 */ +#endif + +/* USART2: + * RXD: PA3 CN9 pin 1 (See SB13, 14, 62, 63). CN10 pin 37 + * PD6 + * TXD: PA2 CN9 pin 2(See SB13, 14, 62, 63). CN10 pin 35 + * PD5 + */ + +#define GPIO_USART2_RX (GPIO_USART2_RX_1|GPIO_SPEED_100MHz) /* PA3 */ +#define GPIO_USART2_TX (GPIO_USART2_TX_1|GPIO_SPEED_100MHz) /* PA2 */ +#define GPIO_USART2_RTS GPIO_USART2_RTS_2 +#define GPIO_USART2_CTS GPIO_USART2_CTS_2 + +/* USART6: + * RXD: PC7 CN5 pin2, CN10 pin 19 + * PA12 CN10, pin 12 + * TXD: PC6 CN10, pin 4 + * PA11 CN10, pin 14 + */ + +#define GPIO_USART6_RX (GPIO_USART6_RX_1|GPIO_SPEED_100MHz) /* PC7 */ +#define GPIO_USART6_TX (GPIO_USART6_TX_1|GPIO_SPEED_100MHz) /* PC6 */ + +/* UART RX DMA configurations */ + +#define DMAMAP_USART1_RX DMAMAP_USART1_RX_2 +#define DMAMAP_USART6_RX DMAMAP_USART6_RX_2 + +/* I2C + * + * The optional _GPIO configurations allow the I2C driver to manually + * reset the bus to clear stuck slaves. They match the pin configuration, + * but are normally-high GPIOs. + */ + +#define GPIO_I2C1_SCL (GPIO_I2C1_SCL_2|GPIO_SPEED_50MHz) +#define GPIO_I2C1_SDA (GPIO_I2C1_SDA_2|GPIO_SPEED_50MHz) +#define GPIO_I2C1_SCL_GPIO \ + (GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTB|GPIO_PIN8) +#define GPIO_I2C1_SDA_GPIO \ + (GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTB|GPIO_PIN9) + +#define GPIO_I2C2_SCL (GPIO_I2C2_SCL_1|GPIO_SPEED_50MHz) +#define GPIO_I2C2_SDA (GPIO_I2C2_SDA_1|GPIO_SPEED_50MHz) +#define GPIO_I2C2_SCL_GPIO \ + (GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTB|GPIO_PIN10) +#define GPIO_I2C2_SDA_GPIO \ + (GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTB|GPIO_PIN11) + +/* SPI + * + * There are sensors on SPI1, and SPI2 is connected to the FRAM. + */ + +#define GPIO_SPI1_MISO (GPIO_SPI1_MISO_1|GPIO_SPEED_50MHz) +#define GPIO_SPI1_MOSI (GPIO_SPI1_MOSI_1|GPIO_SPEED_50MHz) +#define GPIO_SPI1_SCK (GPIO_SPI1_SCK_1|GPIO_SPEED_50MHz) + +#define GPIO_SPI2_MISO (GPIO_SPI2_MISO_1|GPIO_SPEED_50MHz) +#define GPIO_SPI2_MOSI (GPIO_SPI2_MOSI_1|GPIO_SPEED_50MHz) +#define GPIO_SPI2_SCK (GPIO_SPI2_SCK_2|GPIO_SPEED_50MHz) + +/* LEDs + * + * The Nucleo F401RE board provide a single user LED, LD2. LD2 + * is the green LED connected to Arduino signal D13 corresponding to MCU I/O + * PA5 (pin 21) or PB13 (pin 34) depending on the STM32 target. + * + * - When the I/O is HIGH value, the LED is on. + * - When the I/O is LOW, the LED is off. + */ + +/* LED index values for use with board_userled() */ + +#define BOARD_LD2 0 +#define BOARD_NLEDS 1 + +/* LED bits for use with board_userled_all() */ + +#define BOARD_LD2_BIT (1 << BOARD_LD2) + +/* These LEDs are not used by the board port unless CONFIG_ARCH_LEDS is + * defined. In that case, the usage by the board port is defined in + * include/board.h and src/sam_leds.c. The LEDs are used to encode OS-related + * events as follows when the red LED (PE24) is available: + * + * SYMBOL Meaning LD2 + * ------------------- ----------------------- ----------- + * LED_STARTED NuttX has been started OFF + * LED_HEAPALLOCATE Heap has been allocated OFF + * LED_IRQSENABLED Interrupts enabled OFF + * LED_STACKCREATED Idle stack created ON + * LED_INIRQ In an interrupt No change + * LED_SIGNAL In a signal handler No change + * LED_ASSERTION An assertion failed No change + * LED_PANIC The system has crashed Blinking + * LED_IDLE MCU is in sleep mode Not used + * + * Thus if LD2, NuttX has successfully booted and is, apparently, running + * normally. If LD2 is flashing at approximately 2Hz, then a fatal error + * has been detected and the system has halted. + */ + +#define LED_STARTED 0 +#define LED_HEAPALLOCATE 0 +#define LED_IRQSENABLED 0 +#define LED_STACKCREATED 1 +#define LED_INIRQ 2 +#define LED_SIGNAL 2 +#define LED_ASSERTION 2 +#define LED_PANIC 1 + +/* Buttons + * + * B1 USER: + * the user button is connected to the I/O PC13 (pin 2) of the STM32 + * microcontroller. + */ + +#define BUTTON_USER 0 +#define NUM_BUTTONS 1 + +#define BUTTON_USER_BIT (1 << BUTTON_USER) + +#define GPIO_TIM2_CH1IN (GPIO_TIM2_CH1IN_1 | GPIO_PULLUP | GPIO_SPEED_50MHz) +#define GPIO_TIM2_CH2IN (GPIO_TIM2_CH2IN_1 | GPIO_PULLUP | GPIO_SPEED_50MHz) + +/* USB OTG FS */ + +#define GPIO_OTGFS_DM (GPIO_OTGFS_DM_0|GPIO_SPEED_100MHz) +#define GPIO_OTGFS_DP (GPIO_OTGFS_DP_0|GPIO_SPEED_100MHz) +#define GPIO_OTGFS_ID (GPIO_OTGFS_ID_0|GPIO_SPEED_100MHz) +#define GPIO_OTGFS_SOF (GPIO_OTGFS_SOF_0|GPIO_SPEED_100MHz) + +#endif /* __BOARDS_ARM_STM32_NUCLEO_F401RE_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32f4/nucleo-f401re/scripts/Make.defs b/boards/arm/stm32f4/nucleo-f401re/scripts/Make.defs new file mode 100644 index 0000000000000..35c3c0c4e272d --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f401re/scripts/Make.defs @@ -0,0 +1,43 @@ +############################################################################ +# boards/arm/stm32f4/nucleo-f401re/scripts/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/.config +include $(TOPDIR)/tools/Config.mk +include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs + +LDSCRIPT = flash.ld + +ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) + +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 + diff --git a/boards/arm/stm32f4/nucleo-f401re/scripts/flash.ld b/boards/arm/stm32f4/nucleo-f401re/scripts/flash.ld new file mode 100644 index 0000000000000..66d8d456dc6d1 --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f401re/scripts/flash.ld @@ -0,0 +1,109 @@ +/**************************************************************************** + * boards/arm/stm32f4/nucleo-f401re/scripts/flash.ld + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* The STM32F401RE has 512Kb of FLASH beginning at address 0x0800:0000 and + * 96Kb of SRAM beginning at address 0x2000:0000. When booting from FLASH, + * FLASH memory is aliased to address 0x0000:0000 where the code expects to + * begin execution by jumping to the entry point in the 0x0800:0000 address + * range. + */ + +MEMORY +{ + flash (rx) : ORIGIN = 0x08000000, LENGTH = 512K + sram (rwx) : ORIGIN = 0x20000000, LENGTH = 96K +} + +OUTPUT_ARCH(arm) +EXTERN(_vectors) +ENTRY(_stext) +SECTIONS +{ + .text : { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > flash + + .init_section : { + _sinit = ABSOLUTE(.); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) + _einit = ABSOLUTE(.); + } > flash + + .ARM.extab : { + *(.ARM.extab*) + } > flash + + __exidx_start = ABSOLUTE(.); + .ARM.exidx : { + *(.ARM.exidx*) + } > flash + __exidx_end = ABSOLUTE(.); + + _eronly = ABSOLUTE(.); + + /* The STM32F103VCT6 has 48Kb of SRAM beginning at the following address */ + + .data : { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > sram AT > flash + + .bss : { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(8); + _ebss = ABSOLUTE(.); + } > sram + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/stm32f4/nucleo-f401re/src/CMakeLists.txt b/boards/arm/stm32f4/nucleo-f401re/src/CMakeLists.txt new file mode 100644 index 0000000000000..b0ff5784c01e8 --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f401re/src/CMakeLists.txt @@ -0,0 +1,54 @@ +# ############################################################################## +# boards/arm/stm32f4/nucleo-f401re/src/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(SRCS stm32_boot.c stm32_spi.c stm32_bringup.c) + +if(CONFIG_VIDEO_FB) + if(CONFIG_LCD_SSD1306) + list(APPEND SRCS stm32_lcd_ssd1306.c) + endif() +endif() + +if(CONFIG_ARCH_LEDS) + list(APPEND SRCS stm32_autoleds.c) +else() + list(APPEND SRCS stm32_userleds.c) +endif() + +if(CONFIG_ARCH_BUTTONS) + list(APPEND SRCS stm32_buttons.c) +endif() + +if(CONFIG_ADC) + list(APPEND SRCS stm32_adc.c) + if(CONFIG_INPUT_AJOYSTICK) + list(APPEND SRCS stm32_ajoystick.c) + endif() +endif() + +if(CONFIG_CAN_MCP2515) + list(APPEND SRCS stm32_mcp2515.c) +endif() + +target_sources(board PRIVATE ${SRCS}) + +set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/flash.ld") diff --git a/boards/arm/stm32f4/nucleo-f401re/src/Make.defs b/boards/arm/stm32f4/nucleo-f401re/src/Make.defs new file mode 100644 index 0000000000000..369d8455de3ec --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f401re/src/Make.defs @@ -0,0 +1,56 @@ +############################################################################ +# boards/arm/stm32f4/nucleo-f401re/src/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +CSRCS = stm32_boot.c stm32_spi.c stm32_bringup.c + +ifeq ($(CONFIG_VIDEO_FB),y) +ifeq ($(CONFIG_LCD_SSD1306),y) + CSRCS += stm32_lcd_ssd1306.c +endif +endif + +ifeq ($(CONFIG_ARCH_LEDS),y) +CSRCS += stm32_autoleds.c +else +CSRCS += stm32_userleds.c +endif + +ifeq ($(CONFIG_ARCH_BUTTONS),y) +CSRCS += stm32_buttons.c +endif + +ifeq ($(CONFIG_ADC),y) +CSRCS += stm32_adc.c +ifeq ($(CONFIG_INPUT_AJOYSTICK),y) +CSRCS += stm32_ajoystick.c +endif +endif + +ifeq ($(CONFIG_CAN_MCP2515),y) + CSRCS += stm32_mcp2515.c +endif + +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/nucleo-f401re/src/nucleo-f401re.h b/boards/arm/stm32f4/nucleo-f401re/src/nucleo-f401re.h similarity index 99% rename from boards/arm/stm32/nucleo-f401re/src/nucleo-f401re.h rename to boards/arm/stm32f4/nucleo-f401re/src/nucleo-f401re.h index 09a0d7af69a92..3e3010ad53b70 100644 --- a/boards/arm/stm32/nucleo-f401re/src/nucleo-f401re.h +++ b/boards/arm/stm32f4/nucleo-f401re/src/nucleo-f401re.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f401re/src/nucleo-f401re.h + * boards/arm/stm32f4/nucleo-f401re/src/nucleo-f401re.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f4/nucleo-f401re/src/stm32_adc.c b/boards/arm/stm32f4/nucleo-f401re/src/stm32_adc.c new file mode 100644 index 0000000000000..71b9e0974ec49 --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f401re/src/stm32_adc.c @@ -0,0 +1,142 @@ +/**************************************************************************** + * boards/arm/stm32f4/nucleo-f401re/src/stm32_adc.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32_adc.h" +#include "nucleo-f401re.h" + +#include + +#ifdef CONFIG_STM32_ADC1 + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* The number of ADC channels in the conversion list */ + +#ifdef CONFIG_ADC_DMA +# define ADC1_NCHANNELS 2 +#else +# define ADC1_NCHANNELS 1 +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* Identifying number of each ADC channel. */ + +#ifdef CONFIG_ADC_DMA +/* Configure ADC inputs on ADC_IN0 and ADC_IN1 */ + +static const uint8_t g_adc1_chanlist[ADC1_NCHANNELS] = +{ + 0, 1 +}; + +/* Configurations of pins used byte each ADC channels */ + +static const uint32_t g_adc1_pinlist[ADC1_NCHANNELS] = +{ + GPIO_ADC1_IN0, GPIO_ADC1_IN0 +}; + +#else +/* Without DMA, only a single channel can be supported */ + +/* Configura ADC input on ADC_IN0 */ + +static const uint8_t g_adc1_chanlist[ADC1_NCHANNELS] = +{ + 0 +}; + +/* Configurations of pins used byte each ADC channels */ + +static const uint32_t g_adc1_pinlist[ADC1_NCHANNELS] = +{ + GPIO_ADC1_IN0 +}; + +#endif /* CONFIG_ADC_DMA */ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_adc_setup + * + * Description: + * Initialize ADC and register the ADC driver. + * + ****************************************************************************/ + +int stm32_adc_setup(void) +{ + struct adc_dev_s *adc; + int ret; + int i; + + /* Configure the pins as analog inputs for the selected channels */ + + for (i = 0; i < ADC1_NCHANNELS; i++) + { + stm32_configgpio(g_adc1_pinlist[i]); + } + + /* Call stm32_adcinitialize() to get an instance of the ADC interface */ + + adc = stm32_adcinitialize(1, g_adc1_chanlist, ADC1_NCHANNELS); + if (adc == NULL) + { + aerr("ERROR: Failed to get ADC interface\n"); + return -ENODEV; + } + + /* Register the ADC driver at "/dev/adc0" */ + + ret = adc_register("/dev/adc0", adc); + if (ret < 0) + { + aerr("ERROR: adc_register failed: %d\n", ret); + return ret; + } + + return OK; +} + +#endif /* CONFIG_STM32_ADC1 */ diff --git a/boards/arm/stm32f4/nucleo-f401re/src/stm32_ajoystick.c b/boards/arm/stm32f4/nucleo-f401re/src/stm32_ajoystick.c new file mode 100644 index 0000000000000..7aa585817726b --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f401re/src/stm32_ajoystick.c @@ -0,0 +1,490 @@ +/**************************************************************************** + * boards/arm/stm32f4/nucleo-f401re/src/stm32_ajoystick.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include "stm32_gpio.h" +#include "stm32_adc.h" +#include "hardware/stm32_adc.h" +#include "nucleo-f401re.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Check for pre-requisites and pin conflicts */ + +#ifdef CONFIG_INPUT_AJOYSTICK +# if !defined(CONFIG_ADC) +# error CONFIG_ADC is required for the Itead joystick +# undef CONFIG_INPUT_AJOYSTICK +# elif !defined(CONFIG_STM32_ADC1) +# error CONFIG_STM32_ADC1 is required for Itead joystick +# undef CONFIG_INPUT_AJOYSTICK +# endif +#endif /* CONFIG_INPUT_AJOYSTICK */ + +#ifdef CONFIG_INPUT_AJOYSTICK + +/* A no-ADC, buttons only version can be built for testing */ + +#undef NO_JOYSTICK_ADC + +/* Maximum number of ADC channels */ + +#define MAX_ADC_CHANNELS 8 + +/* Dual channel ADC support requires DMA */ + +#ifdef CONFIG_ADC_DMA +# define NJOYSTICK_CHANNELS 2 +#else +# define NJOYSTICK_CHANNELS 1 +#endif + +#ifdef CONFIG_NUCLEO_F401RE_AJOY_MINBUTTONS +/* Number of Joystick buttons */ + +# define AJOY_NGPIOS 3 + +/* Bitset of supported Joystick buttons */ + +# define AJOY_SUPPORTED (AJOY_BUTTON_1_BIT | AJOY_BUTTON_2_BIT | \ + AJOY_BUTTON_3_BIT) +#else +/* Number of Joystick buttons */ + +# define AJOY_NGPIOS 7 + +/* Bitset of supported Joystick buttons */ + +# define AJOY_SUPPORTED (AJOY_BUTTON_1_BIT | AJOY_BUTTON_2_BIT | \ + AJOY_BUTTON_3_BIT | AJOY_BUTTON_4_BIT | \ + AJOY_BUTTON_5_BIT | AJOY_BUTTON_6_BIT | \ + AJOY_BUTTON_7_BIT ) +#endif + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +static ajoy_buttonset_t +ajoy_supported(const struct ajoy_lowerhalf_s *lower); +static int ajoy_sample(const struct ajoy_lowerhalf_s *lower, + struct ajoy_sample_s *sample); +static ajoy_buttonset_t +ajoy_buttons(const struct ajoy_lowerhalf_s *lower); +static void ajoy_enable(const struct ajoy_lowerhalf_s *lower, + ajoy_buttonset_t press, ajoy_buttonset_t release, + ajoy_handler_t handler, void *arg); + +static void ajoy_disable(void); +static int ajoy_interrupt(int irq, void *context, void *arg); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* Pin configuration for each Itead joystick button. Index using AJOY_* + * button definitions in include/nuttx/input/ajoystick.h. + */ + +#ifdef CONFIG_NUCLEO_F401RE_AJOY_MINBUTTONS +static const uint32_t g_joygpio[AJOY_NGPIOS] = +{ + GPIO_BUTTON_1, GPIO_BUTTON_2, GPIO_BUTTON_3 +}; +#else +static const uint32_t g_joygpio[AJOY_NGPIOS] = +{ + GPIO_BUTTON_1, GPIO_BUTTON_2, GPIO_BUTTON_3, GPIO_BUTTON_4, + GPIO_BUTTON_5, GPIO_BUTTON_6, GPIO_BUTTON_7 +}; +#endif + +/* This is the button joystick lower half driver interface */ + +static const struct ajoy_lowerhalf_s g_ajoylower = +{ + .al_supported = ajoy_supported, + .al_sample = ajoy_sample, + .al_buttons = ajoy_buttons, + .al_enable = ajoy_enable, +}; + +#ifndef NO_JOYSTICK_ADC +/* Thread-independent file structure for the open ADC driver */ + +static struct file g_adcfile; +#endif + +/* Current interrupt handler and argument */ + +static ajoy_handler_t g_ajoyhandler; +static void *g_ajoyarg; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: ajoy_supported + * + * Description: + * Return the set of buttons supported on the button joystick device + * + ****************************************************************************/ + +static ajoy_buttonset_t +ajoy_supported(const struct ajoy_lowerhalf_s *lower) +{ + iinfo("Supported: %02x\n", AJOY_SUPPORTED); + return (ajoy_buttonset_t)AJOY_SUPPORTED; +} + +/**************************************************************************** + * Name: ajoy_sample + * + * Description: + * Return the current state of all button joystick buttons + * + ****************************************************************************/ + +static int ajoy_sample(const struct ajoy_lowerhalf_s *lower, + struct ajoy_sample_s *sample) +{ +#ifndef NO_JOYSTICK_ADC + struct adc_msg_s adcmsg[MAX_ADC_CHANNELS]; + struct adc_msg_s *ptr; + ssize_t nread; + ssize_t offset; + int have; + int i; + + /* Read all of the available samples (handling the case where additional + * channels are enabled). + */ + + nread = file_read(&g_adcfile, adcmsg, + MAX_ADC_CHANNELS * sizeof(struct adc_msg_s)); + if (nread < 0) + { + if (nread != -EINTR) + { + ierr("ERROR: read failed: %d\n", (int)nread); + } + + return nread; + } + else if (nread < NJOYSTICK_CHANNELS * sizeof(struct adc_msg_s)) + { + ierr("ERROR: read too small: %ld\n", (long)nread); + return -EIO; + } + + /* Sample and the raw analog inputs */ + +#ifdef CONFIG_ADC_DMA + have = 0; + +#else + /* If DMA is not supported, then we will have only a single ADC channel */ + + have = 2; + sample->as_y = 0; +#endif + + for (i = 0, offset = 0; + i < MAX_ADC_CHANNELS && offset < nread && have != 3; + i++, offset += sizeof(struct adc_msg_s)) + { + ptr = &adcmsg[i]; + + /* Is this one of the channels that we need? */ + + if ((have & 1) == 0 && ptr->am_channel == 0) + { + int32_t tmp = ptr->am_data; + sample->as_x = (int16_t)tmp; + have |= 1; + + iinfo("X sample: %ld -> %d\n", (long)tmp, (int)sample->as_x); + } + +#ifdef CONFIG_ADC_DMA + if ((have & 2) == 0 && ptr->am_channel == 1) + { + int32_t tmp = ptr->am_data; + sample->as_y = (int16_t)tmp; + have |= 2; + + iinfo("Y sample: %ld -> %d\n", (long)tmp, (int)sample->as_y); + } +#endif + } + + if (have != 3) + { + ierr("ERROR: Could not find joystick channels\n"); + return -EIO; + } + +#else + /* ADC support is disabled */ + + sample->as_x = 0; + sample->as_y = 0; +#endif + + /* Sample the discrete button inputs */ + + sample->as_buttons = ajoy_buttons(lower); + iinfo("Returning: %02x\n", sample->as_buttons); + return OK; +} + +/**************************************************************************** + * Name: ajoy_buttons + * + * Description: + * Return the current state of button data (only) + * + ****************************************************************************/ + +static ajoy_buttonset_t +ajoy_buttons(const struct ajoy_lowerhalf_s *lower) +{ + ajoy_buttonset_t ret = 0; + int i; + + /* Read each joystick GPIO value */ + + for (i = 0; i < AJOY_NGPIOS; i++) + { + /* Button outputs are pulled high. So a sensed low level means that the + * button is pressed. + */ + + if (!stm32_gpioread(g_joygpio[i])) + { + ret |= (1 << i); + } + } + + iinfo("Returning: %02x\n", ret); + return ret; +} + +/**************************************************************************** + * Name: ajoy_enable + * + * Description: + * Enable interrupts on the selected set of joystick buttons. And empty + * set will disable all interrupts. + * + ****************************************************************************/ + +static void ajoy_enable(const struct ajoy_lowerhalf_s *lower, + ajoy_buttonset_t press, ajoy_buttonset_t release, + ajoy_handler_t handler, void *arg) +{ + irqstate_t flags; + ajoy_buttonset_t either = press | release; + ajoy_buttonset_t bit; + bool rising; + bool falling; + int i; + + /* Start with all interrupts disabled */ + + flags = enter_critical_section(); + ajoy_disable(); + + iinfo("press: %02x release: %02x handler: %p arg: %p\n", + press, release, handler, arg); + + /* If no events are indicated or if no handler is provided, then this + * must really be a request to disable interrupts. + */ + + if (either && handler) + { + /* Save the new the handler and argument */ + + g_ajoyhandler = handler; + g_ajoyarg = arg; + + /* Check each GPIO. */ + + for (i = 0; i < AJOY_NGPIOS; i++) + { + /* Enable interrupts on each pin that has either a press or + * release event associated with it. + */ + + bit = (1 << i); + if ((either & bit) != 0) + { + /* Active low so a press corresponds to a falling edge and + * a release corresponds to a rising edge. + */ + + falling = ((press & bit) != 0); + rising = ((release & bit) != 0); + + iinfo("GPIO %d: rising: %d falling: %d\n", + i, rising, falling); + + stm32_gpiosetevent(g_joygpio[i], rising, falling, + true, ajoy_interrupt, NULL); + } + } + } + + leave_critical_section(flags); +} + +/**************************************************************************** + * Name: ajoy_disable + * + * Description: + * Disable all joystick interrupts + * + ****************************************************************************/ + +static void ajoy_disable(void) +{ + irqstate_t flags; + int i; + + /* Disable each joystick interrupt */ + + flags = enter_critical_section(); + for (i = 0; i < AJOY_NGPIOS; i++) + { + stm32_gpiosetevent(g_joygpio[i], false, false, false, NULL, NULL); + } + + leave_critical_section(flags); + + /* Nullify the handler and argument */ + + g_ajoyhandler = NULL; + g_ajoyarg = NULL; +} + +/**************************************************************************** + * Name: ajoy_interrupt + * + * Description: + * Discrete joystick interrupt handler + * + ****************************************************************************/ + +static int ajoy_interrupt(int irq, void *context, void *arg) +{ + DEBUGASSERT(g_ajoyhandler); + + if (g_ajoyhandler) + { + g_ajoyhandler(&g_ajoylower, g_ajoyarg); + } + + return OK; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_ajoy_initialize + * + * Description: + * Initialize and register the button joystick driver + * + ****************************************************************************/ + +int board_ajoy_initialize(void) +{ + int ret; + int i; + +#ifndef NO_JOYSTICK_ADC + iinfo("Initialize ADC driver: /dev/adc0\n"); + + /* NOTE: The ADC driver was initialized earlier in the bring-up sequence. */ + + /* Open the ADC driver for reading. */ + + ret = file_open(&g_adcfile, "/dev/adc0", O_RDONLY); + if (ret < 0) + { + ierr("ERROR: Failed to open /dev/adc0: %d\n", ret); + return ret; + } +#endif + + /* Configure the GPIO pins as interrupting inputs. NOTE: This is + * unnecessary for interrupting pins since it will also be done by + * stm32_gpiosetevent(). + */ + + for (i = 0; i < AJOY_NGPIOS; i++) + { + /* Configure the PIO as an input */ + + stm32_configgpio(g_joygpio[i]); + } + + /* Register the joystick device as /dev/ajoy0 */ + + iinfo("Initialize joystick driver: /dev/ajoy0\n"); + + ret = ajoy_register("/dev/ajoy0", &g_ajoylower); + if (ret < 0) + { + ierr("ERROR: ajoy_register failed: %d\n", ret); +#ifndef NO_JOYSTICK_ADC + file_close(&g_adcfile); +#endif + } + + return ret; +} + +#endif /* CONFIG_INPUT_AJOYSTICK */ diff --git a/boards/arm/stm32f4/nucleo-f401re/src/stm32_autoleds.c b/boards/arm/stm32f4/nucleo-f401re/src/stm32_autoleds.c new file mode 100644 index 0000000000000..7ccc090918848 --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f401re/src/stm32_autoleds.c @@ -0,0 +1,83 @@ +/**************************************************************************** + * boards/arm/stm32f4/nucleo-f401re/src/stm32_autoleds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32.h" +#include "nucleo-f401re.h" + +#include + +#ifdef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_autoled_initialize + ****************************************************************************/ + +void board_autoled_initialize(void) +{ + /* Configure LD2 GPIO for output */ + + stm32_configgpio(GPIO_LD2); +} + +/**************************************************************************** + * Name: board_autoled_on + ****************************************************************************/ + +void board_autoled_on(int led) +{ + if (led == 1) + { + stm32_gpiowrite(GPIO_LD2, true); + } +} + +/**************************************************************************** + * Name: board_autoled_off + ****************************************************************************/ + +void board_autoled_off(int led) +{ + if (led == 1) + { + stm32_gpiowrite(GPIO_LD2, false); + } +} + +#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32f4/nucleo-f401re/src/stm32_boot.c b/boards/arm/stm32f4/nucleo-f401re/src/stm32_boot.c new file mode 100644 index 0000000000000..c37cf6b9febc7 --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f401re/src/stm32_boot.c @@ -0,0 +1,101 @@ +/**************************************************************************** + * boards/arm/stm32f4/nucleo-f401re/src/stm32_boot.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include +#include + +#include + +#include "arm_internal.h" +#include "nucleo-f401re.h" + +#include + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_boardinitialize + * + * Description: + * All STM32 architectures must provide the following entry point. + * This entry point is called early in the initialization -- after all + * memory has been configured and mapped but before any devices have been + * initialized. + * + ****************************************************************************/ + +void stm32_boardinitialize(void) +{ + /* Configure on-board LEDs if LED support has been selected. */ + +#ifdef CONFIG_ARCH_LEDS + board_autoled_initialize(); +#endif + + /* Configure SPI chip selects if 1) SP2 is not disabled, and 2) the weak + * function stm32_spidev_initialize() has been brought into the link. + */ + +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || defined(CONFIG_STM32_SPI3) + stm32_spidev_initialize(); +#endif + + /* Initialize USB is 1) USBDEV is selected, 2) the USB controller is not + * disabled, and 3) the weak function stm32_usbinitialize() has been + * brought into the build. + */ + +#if defined(CONFIG_USBDEV) && defined(CONFIG_STM32_USB) + stm32_usbinitialize(); +#endif +} + +/**************************************************************************** + * Name: board_late_initialize + * + * Description: + * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_late_initialize(). board_late_initialize() will + * be called immediately after up_initialize() is called and just before + * the initial application is started. This additional initialization + * phase may be used, for example, to initialize board-specific device + * drivers. + * + ****************************************************************************/ + +#ifdef CONFIG_BOARD_LATE_INITIALIZE +void board_late_initialize(void) +{ + stm32_bringup(); +} +#endif diff --git a/boards/arm/stm32f4/nucleo-f401re/src/stm32_bringup.c b/boards/arm/stm32f4/nucleo-f401re/src/stm32_bringup.c new file mode 100644 index 0000000000000..224f1ead6d9e8 --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f401re/src/stm32_bringup.c @@ -0,0 +1,213 @@ +/**************************************************************************** + * boards/arm/stm32f4/nucleo-f401re/src/stm32_bringup.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include +#include +#include + +#include +#include + +#include + +#ifdef CONFIG_USERLED +# include +#endif + +#ifdef CONFIG_INPUT_BUTTONS +# include +#endif + +#include "nucleo-f401re.h" + +#include + +#ifdef CONFIG_SENSORS_QENCODER +#include "board_qencoder.h" +#endif + +#undef HAVE_LEDS +#if !defined(CONFIG_ARCH_LEDS) && defined(CONFIG_USERLED_LOWER) +# define HAVE_LEDS 1 +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_bringup + * + * Description: + * Perform architecture-specific initialization + * + * CONFIG_BOARD_LATE_INITIALIZE=y : + * Called from board_late_initialize(). + * + ****************************************************************************/ + +int stm32_bringup(void) +{ + int ret = OK; + +#ifdef HAVE_LEDS + /* Register the LED driver */ + + ret = userled_lower_initialize("/dev/userleds"); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: userled_lower_initialize() failed: %d\n", ret); + return ret; + } +#endif + +#ifdef CONFIG_INPUT_BUTTONS + /* Register the BUTTON driver */ + + ret = btn_lower_initialize("/dev/buttons"); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: btn_lower_initialize() failed: %d\n", ret); + } +#endif + + /* Configure SPI-based devices */ + +#ifdef CONFIG_STM32_SPI1 + /* Get the SPI port */ + + struct spi_dev_s *spi; + + spi = stm32_spibus_initialize(1); + if (!spi) + { + syslog(LOG_ERR, "ERROR: Failed to initialize SPI port 1\n"); + return -ENODEV; + } + +#if defined(CONFIG_LCD_SSD1306_SPI) && !defined(CONFIG_VIDEO_FB) + board_lcd_initialize(); +#endif + +#ifdef CONFIG_VIDEO_FB + ret = fb_register(0, 0); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: fb_register() failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_CAN_MCP2515 +#ifdef CONFIG_STM32_SPI1 + stm32_configgpio(GPIO_MCP2515_CS); /* MEMS chip select */ +#endif + + /* Configure and initialize the MCP2515 CAN device */ + + ret = stm32_mcp2515initialize("/dev/can0"); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_mcp2515initialize() failed: %d\n", ret); + } +#endif +#endif + +#ifdef HAVE_MMCSD + /* First, get an instance of the SDIO interface */ + + g_sdio = sdio_initialize(CONFIG_NSH_MMCSDSLOTNO); + if (!g_sdio) + { + syslog(LOG_ERR, "ERROR: Failed to initialize SDIO slot %d\n", + CONFIG_NSH_MMCSDSLOTNO); + return -ENODEV; + } + + /* Now bind the SDIO interface to the MMC/SD driver */ + + ret = mmcsd_slotinitialize(CONFIG_NSH_MMCSDMINOR, g_sdio); + if (ret != OK) + { + syslog(LOG_ERR, + "ERROR: Failed to bind SDIO to the MMC/SD driver: %d\n", + ret); + return ret; + } + + /* Then let's guess and say that there is a card in the slot. There is no + * card detect GPIO. + */ + + sdio_mediachange(g_sdio, true); + + syslog(LOG_INFO, "[boot] Initialized SDIO\n"); +#endif + +#ifdef CONFIG_ADC + /* Initialize ADC and register the ADC driver. */ + + ret = stm32_adc_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_adc_setup failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_SENSORS_QENCODER + /* Initialize and register the qencoder driver */ + + ret = board_qencoder_initialize(0, CONFIG_NUCLEO_F401RE_QETIMER); + if (ret != OK) + { + syslog(LOG_ERR, + "ERROR: Failed to register the qencoder: %d\n", + ret); + return ret; + } +#endif + +#ifdef CONFIG_INPUT_AJOYSTICK + /* Initialize and register the joystick driver */ + + ret = board_ajoy_initialize(); + if (ret != OK) + { + syslog(LOG_ERR, + "ERROR: Failed to register the joystick driver: %d\n", + ret); + return ret; + } +#endif + + return ret; +} diff --git a/boards/arm/stm32f4/nucleo-f401re/src/stm32_buttons.c b/boards/arm/stm32f4/nucleo-f401re/src/stm32_buttons.c new file mode 100644 index 0000000000000..da3e2fb0ee6cd --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f401re/src/stm32_buttons.c @@ -0,0 +1,117 @@ +/**************************************************************************** + * boards/arm/stm32f4/nucleo-f401re/src/stm32_buttons.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include + +#include "stm32_gpio.h" +#include "nucleo-f401re.h" + +#include + +#ifdef CONFIG_ARCH_BUTTONS + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_button_initialize + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. + * + ****************************************************************************/ + +uint32_t board_button_initialize(void) +{ + /* Configure the single button as an input. NOTE that EXTI interrupts are + * also configured for the pin. + */ + + stm32_configgpio(GPIO_BTN_USER); + return NUM_BUTTONS; +} + +/**************************************************************************** + * Name: board_buttons + ****************************************************************************/ + +uint32_t board_buttons(void) +{ + /* Check that state of each USER button. A LOW value means that the key is + * pressed. + */ + + bool released = stm32_gpioread(GPIO_BTN_USER); + return !released; +} + +/**************************************************************************** + * Button support. + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. + * + * After board_button_initialize() has been called, board_buttons() may be + * called to collect the state of all buttons. board_buttons() returns an + * 32-bit bit set with each bit associated with a button. See the + * BUTTON_*_BIT definitions in board.h for the meaning of each bit. + * + * board_button_irq() may be called to register an interrupt handler that + * will be called when a button is depressed or released. The ID value is a + * button enumeration value that uniquely identifies a button resource. See + * the BUTTON_* definitions in board.h for the meaning of enumeration + * value. + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_IRQBUTTONS +int board_button_irq(int id, xcpt_t irqhandler, void *arg) +{ + int ret = -EINVAL; + + if (id == BUTTON_USER) + { + ret = stm32_gpiosetevent(GPIO_BTN_USER, true, true, true, + irqhandler, arg); + } + + return ret; +} +#endif +#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/stm32f4/nucleo-f401re/src/stm32_lcd_ssd1306.c b/boards/arm/stm32f4/nucleo-f401re/src/stm32_lcd_ssd1306.c new file mode 100644 index 0000000000000..4865b4d69b089 --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f401re/src/stm32_lcd_ssd1306.c @@ -0,0 +1,88 @@ +/**************************************************************************** + * boards/arm/stm32f4/nucleo-f401re/src/stm32_lcd_ssd1306.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include +#include +#include + +#include "stm32.h" +#include "nucleo-f401re.h" + +#include "stm32_ssd1306.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define OLED_SPI_PORT 1 /* OLED display connected to SPI1 */ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_lcd_initialize + ****************************************************************************/ + +int board_lcd_initialize(void) +{ + int ret; + + ret = board_ssd1306_initialize(OLED_SPI_PORT); + if (ret < 0) + { + lcderr("ERROR: Failed to initialize SSD1306\n"); + return ret; + } + + return OK; +} + +/**************************************************************************** + * Name: board_lcd_getdev + ****************************************************************************/ + +struct lcd_dev_s *board_lcd_getdev(int devno) +{ + return board_ssd1306_getdev(); +} + +/**************************************************************************** + * Name: board_lcd_uninitialize + ****************************************************************************/ + +void board_lcd_uninitialize(void) +{ + /* TO-FIX */ +} diff --git a/boards/arm/stm32f4/nucleo-f401re/src/stm32_mcp2515.c b/boards/arm/stm32f4/nucleo-f401re/src/stm32_mcp2515.c new file mode 100644 index 0000000000000..3a87e3e7af2d6 --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f401re/src/stm32_mcp2515.c @@ -0,0 +1,241 @@ +/**************************************************************************** + * boards/arm/stm32f4/nucleo-f401re/src/stm32_mcp2515.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "stm32.h" +#include "stm32_spi.h" +#include "nucleo-f401re.h" + +#if defined(CONFIG_SPI) && defined(CONFIG_STM32_SPI1) && \ + defined(CONFIG_CAN_MCP2515) + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define MCP2515_SPI_PORTNO 1 /* On SPI1 */ + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +struct stm32_mcp2515config_s +{ + /* Configuration structure as seen by the MCP2515 driver */ + + struct mcp2515_config_s config; + + /* Additional private definitions only known to this driver */ + + struct mcp2515_can_s *handle; /* The MCP2515 driver handle */ + mcp2515_handler_t handler; /* The MCP2515 interrupt handler */ + void *arg; /* Argument to pass to the interrupt handler */ +}; + +/**************************************************************************** + * Static Function Prototypes + ****************************************************************************/ + +/* IRQ/GPIO access callbacks. These operations all hidden behind callbacks + * to isolate the MCP2515 driver from differences in GPIO interrupt handling + * by varying boards and MCUs. + * + * attach - Attach the MCP2515 interrupt handler to the GPIO interrupt + */ + +static int mcp2515_attach(struct mcp2515_config_s *state, + mcp2515_handler_t handler, void *arg); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* A reference to a structure of this type must be passed to the MCP2515 + * driver. This structure provides information about the configuration + * of the MCP2515 and provides some board-specific hooks. + * + * Memory for this structure is provided by the caller. It is not copied + * by the driver and is presumed to persist while the driver is active. The + * memory must be writable because, under certain circumstances, the driver + * may modify frequency or X plate resistance values. + */ + +static struct stm32_mcp2515config_s g_mcp2515config = +{ + .config = + { + .spi = NULL, + .baud = 0, /* REVISIT. Probably broken by commit eb7373cedfa */ + .btp = 0, /* REVISIT. Probably broken by commit eb7373cedfa */ + .devid = 0, + .mode = 0, /* REVISIT. Probably broken by commit eb7373cedfa */ + .nfilters = 6, +#ifdef MCP2515_LOOPBACK + .loopback = false; +#endif + .attach = mcp2515_attach, + }, +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/* This is the MCP2515 Interrupt handler */ + +int mcp2515_interrupt(int irq, void *context, void *arg) +{ + struct stm32_mcp2515config_s *priv = + (struct stm32_mcp2515config_s *)arg; + + DEBUGASSERT(priv != NULL); + + /* Verify that we have a handler attached */ + + if (priv->handler) + { + /* Yes.. forward with interrupt along with its argument */ + + priv->handler(&priv->config, priv->arg); + } + + return OK; +} + +static int mcp2515_attach(struct mcp2515_config_s *state, + mcp2515_handler_t handler, void *arg) +{ + struct stm32_mcp2515config_s *priv = + (struct stm32_mcp2515config_s *)state; + irqstate_t flags; + + caninfo("Saving handler %p\n", handler); + + flags = enter_critical_section(); + + priv->handler = handler; + priv->arg = arg; + + /* Configure the interrupt for falling edge */ + + stm32_gpiosetevent(GPIO_MCP2515_IRQ, false, true, false, + mcp2515_interrupt, priv); + + leave_critical_section(flags); + + return OK; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_mcp2515initialize + * + * Description: + * Initialize and register the MCP2515 RFID driver. + * + * Input Parameters: + * devpath - The full path to the driver to register. E.g., "/dev/rfid0" + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +int stm32_mcp2515initialize(const char *devpath) +{ + struct spi_dev_s *spi; + struct can_dev_s *can; + struct mcp2515_can_s *mcp2515; + int ret; + + /* Check if we are already initialized */ + + if (!g_mcp2515config.handle) + { + sninfo("Initializing\n"); + + /* Configure the MCP2515 interrupt pin as an input */ + + stm32_configgpio(GPIO_MCP2515_IRQ); + + spi = stm32_spibus_initialize(MCP2515_SPI_PORTNO); + + if (!spi) + { + return -ENODEV; + } + + /* Save the SPI instance in the mcp2515_config_s structure */ + + g_mcp2515config.config.spi = spi; + + /* Instantiate the MCP2515 CAN Driver */ + + mcp2515 = mcp2515_instantiate(&g_mcp2515config.config); + if (mcp2515 == NULL) + { + canerr("ERROR: Failed to get MCP2515 Driver Loaded\n"); + return -ENODEV; + } + + /* Save the opaque structure */ + + g_mcp2515config.handle = mcp2515; + + /* Initialize the CAN Device with the MCP2515 operations */ + + can = mcp2515_initialize(mcp2515); + if (can == NULL) + { + canerr("ERROR: Failed to get CAN interface\n"); + return -ENODEV; + } + + /* Register the CAN driver at "/dev/can0" */ + + ret = can_register(devpath, can); + if (ret < 0) + { + canerr("ERROR: can_register failed: %d\n", ret); + return ret; + } + } + + return OK; +} + +#endif /* CONFIG_SPI && CONFIG_CAN_MCP2515 */ diff --git a/boards/arm/stm32f4/nucleo-f401re/src/stm32_spi.c b/boards/arm/stm32f4/nucleo-f401re/src/stm32_spi.c new file mode 100644 index 0000000000000..721b001a01463 --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f401re/src/stm32_spi.c @@ -0,0 +1,246 @@ +/**************************************************************************** + * boards/arm/stm32f4/nucleo-f401re/src/stm32_spi.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include + +#include "arm_internal.h" +#include "chip.h" +#include "stm32.h" + +#include "nucleo-f401re.h" + +#include + +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || \ + defined(CONFIG_STM32_SPI3) + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/* Global driver instances */ + +#ifdef CONFIG_STM32_SPI1 +struct spi_dev_s *g_spi1; +#endif +#ifdef CONFIG_STM32_SPI2 +struct spi_dev_s *g_spi2; +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_spidev_initialize + * + * Description: + * Called to configure SPI chip select GPIO pins for the Nucleo-F401RE + * + ****************************************************************************/ + +void weak_function stm32_spidev_initialize(void) +{ +#ifdef CONFIG_STM32_SPI1 + /* Configure SPI-based devices */ + + g_spi1 = stm32_spibus_initialize(1); + if (!g_spi1) + { + spierr("ERROR: FAILED to initialize SPI port 1\n"); + } + +#ifdef CONFIG_LCD_SSD1306_SPI + stm32_configgpio(GPIO_SSD1306_CS); /* SSD1306 chip select */ + stm32_configgpio(GPIO_SSD1306_CMD); /* SSD1306 data/!command */ +#endif + +#ifdef CONFIG_CAN_MCP2515 + stm32_configgpio(GPIO_MCP2515_CS); /* MCP2515 chip select */ +#endif + +#ifdef HAVE_MMCSD + stm32_configgpio(GPIO_SPI_CS_SD_CARD); +#endif +#endif + +#ifdef CONFIG_STM32_SPI2 + /* Configure SPI-based devices */ + + g_spi2 = stm32_spibus_initialize(2); +#endif +} + +/**************************************************************************** + * Name: stm32_spi1/2/3select and stm32_spi1/2/3status + * + * Description: + * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status + * must be provided by board-specific logic. They are implementations of + * the select and status methods of the SPI interface defined by struct + * spi_ops_s (see include/nuttx/spi/spi.h). All other methods (including + * stm32_spibus_initialize()) are provided by common STM32 logic. To use + * this common SPI logic on your board: + * + * 1. Provide logic in stm32_boardinitialize() to configure SPI chip select + * pins. + * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() functions + * in your board-specific logic. These functions will perform chip + * selection and status operations using GPIOs in the way your board is + * configured. + * 3. Add a calls to stm32_spibus_initialize() in your low level + * application initialization logic + * 4. The handle returned by stm32_spibus_initialize() may then be used to + * bind the SPI driver to higher level logic (e.g., calling + * mmcsd_spislotinitialize(), for example, will bind the SPI driver to + * the SPI MMC/SD driver). + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_SPI1 +void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, + bool selected) +{ + spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : + "de-assert"); + +#if defined(CONFIG_LCD_SSD1306_SPI) + if (devid == SPIDEV_DISPLAY(0)) + { + stm32_gpiowrite(GPIO_SSD1306_CS, !selected); + } +#endif + +#if defined(CONFIG_CAN_MCP2515) + if (devid == SPIDEV_CANBUS(0)) + { + stm32_gpiowrite(GPIO_MCP2515_CS, !selected); + } +#endif + +#ifdef HAVE_MMCSD + if (devid == SPIDEV_MMCSD(0)) + { + stm32_gpiowrite(GPIO_SPI_CS_SD_CARD, !selected); + } +#endif +} + +uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} +#endif + +#ifdef CONFIG_STM32_SPI2 +void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid, + bool selected) +{ + spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : + "de-assert"); +} + +uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} +#endif + +#ifdef CONFIG_STM32_SPI3 +void stm32_spi3select(struct spi_dev_s *dev, uint32_t devid, + bool selected) +{ + spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : + "de-assert"); +} + +uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} +#endif + +/**************************************************************************** + * Name: stm32_spi1cmddata + * + * Description: + * Set or clear the SH1101A A0 or SD1306 D/C n bit to select data (true) + * or command (false). This function must be provided by platform-specific + * logic. This is an implementation of the cmddata method of the SPI + * interface defined by struct spi_ops_s (see include/nuttx/spi/spi.h). + * + * Input Parameters: + * + * spi - SPI device that controls the bus the device that requires the CMD/ + * DATA selection. + * devid - If there are multiple devices on the bus, this selects which one + * to select cmd or data. NOTE: This design restricts, for example, + * one one SPI display per SPI bus. + * cmd - true: select command; false: select data + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_SPI_CMDDATA +#ifdef CONFIG_STM32_SPI1 +int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) +{ +#if defined(CONFIG_LCD_SSD1306_SPI) + if (devid == SPIDEV_DISPLAY(0)) + { + stm32_gpiowrite(GPIO_SSD1306_CMD, !cmd); + } +#endif + + return OK; +} +#endif + +#ifdef CONFIG_STM32_SPI2 +int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) +{ + return OK; +} +#endif + +#ifdef CONFIG_STM32_SPI3 +int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) +{ + return OK; +} +#endif +#endif /* CONFIG_SPI_CMDDATA */ + +#endif /* CONFIG_STM32_SPI1 || CONFIG_STM32_SPI2 || CONFIG_STM32_SPI3 */ diff --git a/boards/arm/stm32f4/nucleo-f401re/src/stm32_userleds.c b/boards/arm/stm32f4/nucleo-f401re/src/stm32_userleds.c new file mode 100644 index 0000000000000..c7737d5e3e0ec --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f401re/src/stm32_userleds.c @@ -0,0 +1,218 @@ +/**************************************************************************** + * boards/arm/stm32f4/nucleo-f401re/src/stm32_userleds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32.h" +#include "nucleo-f401re.h" + +#include + +#ifndef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/* LED Power Management */ + +#ifdef CONFIG_PM +static void led_pm_notify(struct pm_callback_s *cb, int domain, + enum pm_state_e pmstate); +static int led_pm_prepare(struct pm_callback_s *cb, int domain, + enum pm_state_e pmstate); +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#ifdef CONFIG_PM +static struct pm_callback_s g_ledscb = +{ + .notify = led_pm_notify, + .prepare = led_pm_prepare, +}; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: led_pm_notify + * + * Description: + * Notify the driver of new power state. This callback is called after + * all drivers have had the opportunity to prepare for the new power state. + * + ****************************************************************************/ + +#ifdef CONFIG_PM +static void led_pm_notify(struct pm_callback_s *cb, int domain, + enum pm_state_e pmstate) +{ + switch (pmstate) + { + case PM_NORMAL: + { + /* Restore normal LEDs operation */ + } + break; + + case PM_IDLE: + { + /* Entering IDLE mode - Turn leds off */ + } + break; + + case PM_STANDBY: + { + /* Entering STANDBY mode - Logic for PM_STANDBY goes here */ + } + break; + + case PM_SLEEP: + { + /* Entering SLEEP mode - Logic for PM_SLEEP goes here */ + } + break; + + default: + { + /* Should not get here */ + } + break; + } +} +#endif + +/**************************************************************************** + * Name: led_pm_prepare + * + * Description: + * Request the driver to prepare for a new power state. This is a warning + * that the system is about to enter into a new power state. The driver + * should begin whatever operations that may be required to enter power + * state. The driver may abort the state change mode by returning a + * non-zero value from the callback function. + * + ****************************************************************************/ + +#ifdef CONFIG_PM +static int led_pm_prepare(struct pm_callback_s *cb, int domain, + enum pm_state_e pmstate) +{ + /* No preparation to change power modes is required by the LEDs driver. + * We always accept the state change by returning OK. + */ + + return OK; +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_userled_initialize + ****************************************************************************/ + +uint32_t board_userled_initialize(void) +{ + /* Configure LD2 GPIO for output */ + + stm32_configgpio(GPIO_LD2); + return BOARD_NLEDS; +} + +/**************************************************************************** + * Name: board_userled + ****************************************************************************/ + +void board_userled(int led, bool ledon) +{ + if (BOARD_LD2_BIT == (1 << led)) + { + stm32_gpiowrite(GPIO_LD2, ledon); + } +} + +/**************************************************************************** + * Name: board_userled_all + ****************************************************************************/ + +void board_userled_all(uint32_t ledset) +{ + /* An output of '1' illuminates the LED */ + + stm32_gpiowrite(GPIO_LD2, (ledset & BOARD_LD2_BIT) != 0); +} + +#ifdef CONFIG_USERLED_LOWER_READSTATE +/**************************************************************************** + * Name: board_userled_getall + ****************************************************************************/ + +void board_userled_getall(uint32_t *ledset) +{ + /* Clear the LED bits */ + + *ledset = 0; + + /* Get LED state. An output of '1' illuminates the LED. */ + + *ledset |= ((stm32_gpioread(GPIO_LD2) & 1) << BOARD_LD2); +} + +#endif /* CONFIG_USERLED_LOWER_READSTATE */ + +/**************************************************************************** + * Name: stm32_led_pminitialize + ****************************************************************************/ + +#ifdef CONFIG_PM +void stm32_led_pminitialize(void) +{ + /* Register to receive power management callbacks */ + + int ret = pm_register(&g_ledscb); + DEBUGASSERT(ret == OK); + UNUSED(ret); +} +#endif /* CONFIG_PM */ + +#endif /* !CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32f4/nucleo-f410rb/CMakeLists.txt b/boards/arm/stm32f4/nucleo-f410rb/CMakeLists.txt new file mode 100644 index 0000000000000..bbf909582a5b7 --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f410rb/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32f4/nucleo-f410rb/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/arm/stm32/nucleo-f410rb/Kconfig b/boards/arm/stm32f4/nucleo-f410rb/Kconfig similarity index 100% rename from boards/arm/stm32/nucleo-f410rb/Kconfig rename to boards/arm/stm32f4/nucleo-f410rb/Kconfig diff --git a/boards/arm/stm32f4/nucleo-f410rb/configs/nsh/defconfig b/boards/arm/stm32f4/nucleo-f410rb/configs/nsh/defconfig new file mode 100644 index 0000000000000..2f7c904678df6 --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f410rb/configs/nsh/defconfig @@ -0,0 +1,58 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +CONFIG_ADC=y +CONFIG_ANALOG=y +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nucleo-f410rb" +CONFIG_ARCH_BOARD_NUCLEO_F410RB=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F410RB=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=8499 +CONFIG_BUILTIN=y +CONFIG_EXAMPLES_HELLO=y +CONFIG_HAVE_CXX=y +CONFIG_HEAP_COLORATION=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=32768 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_SERIAL_TERMIOS=y +CONFIG_STACK_COLORATION=y +CONFIG_START_DAY=25 +CONFIG_START_MONTH=9 +CONFIG_START_YEAR=2017 +CONFIG_STM32_ADC1=y +CONFIG_STM32_ADC1_DMA=y +CONFIG_STM32_DMA2=y +CONFIG_STM32_FLASH_CONFIG_B=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_PWR=y +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_CLE=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART2_SERIAL_CONSOLE=y +CONFIG_USERLED=y +CONFIG_USERLED_LOWER=y diff --git a/boards/arm/stm32f4/nucleo-f410rb/include/board.h b/boards/arm/stm32f4/nucleo-f410rb/include/board.h new file mode 100644 index 0000000000000..4a264975b6f73 --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f410rb/include/board.h @@ -0,0 +1,303 @@ +/**************************************************************************** + * boards/arm/stm32f4/nucleo-f410rb/include/board.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_STM32_NUCLEO_F410RB_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32_NUCLEO_F410RB_INCLUDE_BOARD_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#ifndef __ASSEMBLY__ +# include +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Clocking *****************************************************************/ + +/* The NUCLEO410RB supports both HSE and LSE crystals (X2 and X3). + * However, as shipped, the X3 crystals is not populated. + * Therefore the Nucleo-F410RB will need to run off the 16MHz HSI clock. + * + * System Clock source : PLL (HSI) + * SYSCLK(Hz) : 100000000 Determined by PLL configuration + * HCLK(Hz) : 100000000 (STM32_RCC_CFGR_HPRE) + * AHB Prescaler : 1 (STM32_RCC_CFGR_HPRE) + * APB1 Prescaler : 2 (STM32_RCC_CFGR_PPRE1) + * APB2 Prescaler : 1 (STM32_RCC_CFGR_PPRE2) + * HSI Frequency(Hz) : 16000000 (nominal) + * PLLM : 2 (STM32_PLLCFG_PLLM) + * PLLN : 50 (STM32_PLLCFG_PLLN) + * PLLP : 4 (STM32_PLLCFG_PLLP) + * PLLQ : 8 (STM32_PLLCFG_PPQ) + * Flash Latency(WS) : 5 + * Prefetch Buffer : OFF + * Instruction cache : ON + * Data cache : ON + */ + +/* HSI - 16 MHz RC factory-trimmed + * LSI - 32 KHz RC + * HSE - not installed + * LSE - not installed + */ + +#define STM32_HSI_FREQUENCY 16000000ul +#define STM32_LSI_FREQUENCY 32000 +#define STM32_BOARD_USEHSI 1 + +/* Main PLL Configuration. + * + * Formulae: + * + * VCO input frequency = PLL input clock frequency / PLLM, + * 2 <= PLLM <= 63 + * VCO output frequency = VCO input frequency � PLLN, + * 50 <= PLLN <= 432 + * PLL output clock frequency = VCO frequency / PLLP, + * PLLP = 2, 4, 6, or 8 + * USB OTG FS clock frequency = VCO frequency / PLLQ, + * 2 <= PLLQ <= 15 + * + * We will configure like this + * + * PLL source is HSI + * PLL_VCO = (STM32_HSI_FREQUENCY / PLLM) * PLLN + * = (16,000,000 / 2) * 50 + * = 400,000,000 + * SYSCLK = PLL_VCO / PLLP + * = 400,000,000 / 4 = 100,000,000 + * RNG Clock + * = PLL_VCO / PLLQ + * = 400,000,000 / 8 = 50,000,000 + * + * REVISIT: Trimming of the HSI is not yet supported. + */ + +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(2) +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(50) +#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_4 +#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(8) + +#define STM32_SYSCLK_FREQUENCY 100000000ul + +/* AHB clock (HCLK) is SYSCLK (100MHz) */ + +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY + +/* APB1 clock (PCLK1) is HCLK/2 (50MHz) */ + +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd2 /* PCLK1 = HCLK / 2 */ +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/2) + +/* Timers driven from APB1 will be twice PCLK1 */ + +/* REVISIT */ + +#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) + +/* APB2 clock (PCLK2) is HCLK (100MHz) */ + +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK */ +#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY) + +/* Timers driven from APB2 will be PCLK2 */ + +/* REVISIT */ + +#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM9_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM11_CLKIN (STM32_PCLK2_FREQUENCY) + +/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx + * otherwise frequency is 2xAPBx. + * Note: TIM1,9,11 are on APB2, others on APB1 + */ + +/* REVISIT */ + +#define BOARD_TIM1_FREQUENCY STM32_APB2_TIM1_CLKIN +#define BOARD_TIM5_FREQUENCY STM32_APB1_TIM5_CLKIN +#define BOARD_TIM6_FREQUENCY STM32_APB1_TIM6_CLKIN +#define BOARD_TIM9_FREQUENCY STM32_APB2_TIM9_CLKIN +#define BOARD_TIM11_FREQUENCY STM32_APB2_TIM11_CLKIN + +/* DMA Channel/Stream Selections ********************************************/ + +/* Stream selections are arbitrary for now but might become important in the + * future is we set aside more DMA channels/streams. + */ + +#define ADC1_DMA_CHAN DMAMAP_ADC1_1 +#define GPIO_TIM1_CH1OUT (GPIO_TIM1_CH1OUT_1|GPIO_SPEED_50MHz) + +#define DMACHAN_SPI1_RX DMAMAP_SPI1_RX_1 +#define DMACHAN_SPI1_TX DMAMAP_SPI1_TX_1 +#define DMACHAN_SPI2_RX DMAMAP_SPI2_RX +#define DMACHAN_SPI2_TX DMAMAP_SPI2_TX + +/* Alternate function pin selections ****************************************/ + +/* USART1: + * RXD: PA10 CN9 pin 3, CN10 pin 33 + * PB7 CN7 pin 21 + * TXD: PA9 CN5 pin 1, CN10 pin 21 + * PB6 CN5 pin 3, CN10 pin 17 + */ + +#if 1 +# define GPIO_USART1_RX (GPIO_USART1_RX_1|GPIO_SPEED_100MHz) /* PA10 */ +# define GPIO_USART1_TX (GPIO_USART1_TX_1|GPIO_SPEED_100MHz) /* PA9 */ +#else +# define GPIO_USART1_RX (GPIO_USART1_RX_2|GPIO_SPEED_100MHz) /* PB7 */ +# define GPIO_USART1_TX (GPIO_USART1_TX_2|GPIO_SPEED_100MHz) /* PB6 */ +#endif + +/* USART2: + * RXD: PA3 CN9 pin 1 (See SB13, 14, 62, 63). CN10 pin 37 + * PD6 + * TXD: PA2 CN9 pin 2(See SB13, 14, 62, 63). CN10 pin 35 + * PD5 + */ + +#define GPIO_USART2_RX (GPIO_USART2_RX_1|GPIO_SPEED_100MHz) /* PA3 */ +#define GPIO_USART2_TX (GPIO_USART2_TX_1|GPIO_SPEED_100MHz) /* PA2 */ +#define GPIO_USART2_RTS GPIO_USART2_RTS_2 +#define GPIO_USART2_CTS GPIO_USART2_CTS_2 + +/* USART6: + * RXD: PC7 CN5 pin2, CN10 pin 19 + * PA12 CN10, pin 12 + * TXD: PC6 CN10, pin 4 + * PA11 CN10, pin 14 + */ + +#define GPIO_USART6_RX (GPIO_USART6_RX_1|GPIO_SPEED_100MHz) /* PC7 */ +#define GPIO_USART6_TX (GPIO_USART6_TX_1|GPIO_SPEED_100MHz) /* PC6 */ + +/* UART RX DMA configurations */ + +#define DMAMAP_USART1_RX DMAMAP_USART1_RX_2 +#define DMAMAP_USART6_RX DMAMAP_USART6_RX_2 + +/* I2C + * + * The optional _GPIO configurations allow the I2C driver to manually + * reset the bus to clear stuck slaves. They match the pin configuration, + * but are normally-high GPIOs. + */ + +#define GPIO_I2C1_SCL (GPIO_I2C1_SCL_2|GPIO_SPEED_50MHz) +#define GPIO_I2C1_SDA (GPIO_I2C1_SDA_2|GPIO_SPEED_50MHz) +#define GPIO_I2C1_SCL_GPIO \ + (GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTB|GPIO_PIN8) +#define GPIO_I2C1_SDA_GPIO \ + (GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTB|GPIO_PIN9) + +#define GPIO_I2C2_SCL (GPIO_I2C2_SCL_1|GPIO_SPEED_50MHz) +#define GPIO_I2C2_SDA (GPIO_I2C2_SDA_1|GPIO_SPEED_50MHz) +#define GPIO_I2C2_SCL_GPIO \ + (GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTB|GPIO_PIN10) +#define GPIO_I2C2_SDA_GPIO \ + (GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTB|GPIO_PIN11) + +/* SPI + * + */ + +#define GPIO_SPI1_MISO (GPIO_SPI1_MISO_1|GPIO_SPEED_50MHz) +#define GPIO_SPI1_MOSI (GPIO_SPI1_MOSI_1|GPIO_SPEED_50MHz) +#define GPIO_SPI1_SCK (GPIO_SPI1_SCK_1|GPIO_SPEED_50MHz) + +#define GPIO_SPI2_MISO (GPIO_SPI2_MISO_1|GPIO_SPEED_50MHz) +#define GPIO_SPI2_MOSI (GPIO_SPI2_MOSI_1|GPIO_SPEED_50MHz) +#define GPIO_SPI2_SCK (GPIO_SPI2_SCK_2|GPIO_SPEED_50MHz) + +/* LEDs + * + * The Nucleo F410RB board provide a single user LED, LD2. LD2 + * is the green LED connected to Arduino signal D13 corresponding to MCU I/O + * PA5 (pin 21) or PB13 (pin 34) depending on the STM32 target. + * + * - When the I/O is HIGH value, the LED is on. + * - When the I/O is LOW, the LED is off. + */ + +/* LED index values for use with board_userled() */ + +#define BOARD_LD2 0 +#define BOARD_NLEDS 1 + +/* LED bits for use with board_userled_all() */ + +#define BOARD_LD2_BIT (1 << BOARD_LD2) + +/* These LEDs are not used by the board port unless CONFIG_ARCH_LEDS is + * defined. In that case, the usage by the board port is defined in + * include/board.h and src/sam_leds.c. The LEDs are used to encode OS-related + * events as follows when the red LED (PE24) is available: + * + * SYMBOL Meaning LD2 + * ------------------- ----------------------- ----------- + * LED_STARTED NuttX has been started OFF + * LED_HEAPALLOCATE Heap has been allocated OFF + * LED_IRQSENABLED Interrupts enabled OFF + * LED_STACKCREATED Idle stack created ON + * LED_INIRQ In an interrupt No change + * LED_SIGNAL In a signal handler No change + * LED_ASSERTION An assertion failed No change + * LED_PANIC The system has crashed Blinking + * LED_IDLE MCU is in sleep mode Not used + * + * Thus if LD2, NuttX has successfully booted and is, apparently, running + * normally. If LD2 is flashing at approximately 2Hz, then a fatal error + * has been detected and the system has halted. + */ + +#define LED_STARTED 0 +#define LED_HEAPALLOCATE 0 +#define LED_IRQSENABLED 0 +#define LED_STACKCREATED 1 +#define LED_INIRQ 2 +#define LED_SIGNAL 2 +#define LED_ASSERTION 2 +#define LED_PANIC 1 + +/* Buttons + * + * B1 USER: + * the user button is connected to the I/O PC13 (pin 2) of the STM32 + * microcontroller. + */ + +#define BUTTON_USER 0 +#define NUM_BUTTONS 1 + +#define BUTTON_USER_BIT (1 << BUTTON_USER) + +#endif /* __BOARDS_ARM_STM32_NUCLEO_F410RB_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32f4/nucleo-f410rb/scripts/Make.defs b/boards/arm/stm32f4/nucleo-f410rb/scripts/Make.defs new file mode 100644 index 0000000000000..02cb165c1f3af --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f410rb/scripts/Make.defs @@ -0,0 +1,41 @@ +############################################################################ +# boards/arm/stm32f4/nucleo-f410rb/scripts/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/.config +include $(TOPDIR)/tools/Config.mk +include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs + +LDSCRIPT = f410rb.ld +ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) + +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32/nucleo-f410rb/scripts/f410rb.ld b/boards/arm/stm32f4/nucleo-f410rb/scripts/f410rb.ld similarity index 98% rename from boards/arm/stm32/nucleo-f410rb/scripts/f410rb.ld rename to boards/arm/stm32f4/nucleo-f410rb/scripts/f410rb.ld index ec48fa2500b75..3cabdd87366e0 100644 --- a/boards/arm/stm32/nucleo-f410rb/scripts/f410rb.ld +++ b/boards/arm/stm32f4/nucleo-f410rb/scripts/f410rb.ld @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f410rb/scripts/f410rb.ld + * boards/arm/stm32f4/nucleo-f410rb/scripts/f410rb.ld * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f4/nucleo-f410rb/src/CMakeLists.txt b/boards/arm/stm32f4/nucleo-f410rb/src/CMakeLists.txt new file mode 100644 index 0000000000000..99f2c446b2035 --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f410rb/src/CMakeLists.txt @@ -0,0 +1,41 @@ +# ############################################################################## +# boards/arm/stm32f4/nucleo-f410rb/src/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(SRCS stm32_boot.c stm32_bringup.c) + +if(CONFIG_ARCH_LEDS) + list(APPEND SRCS stm32_autoleds.c) +else() + list(APPEND SRCS stm32_userleds.c) +endif() + +if(CONFIG_ARCH_BUTTONS) + list(APPEND SRCS stm32_buttons.c) +endif() + +if(CONFIG_ADC) + list(APPEND SRCS stm32_adc.c) +endif() + +target_sources(board PRIVATE ${SRCS}) + +set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/f410rb.ld") diff --git a/boards/arm/stm32f4/nucleo-f410rb/src/Make.defs b/boards/arm/stm32f4/nucleo-f410rb/src/Make.defs new file mode 100644 index 0000000000000..dce7ead7aff34 --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f410rb/src/Make.defs @@ -0,0 +1,43 @@ +############################################################################ +# boards/arm/stm32f4/nucleo-f410rb/src/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +CSRCS = stm32_boot.c stm32_bringup.c + +ifeq ($(CONFIG_ARCH_LEDS),y) +CSRCS += stm32_autoleds.c +else +CSRCS += stm32_userleds.c +endif + +ifeq ($(CONFIG_ARCH_BUTTONS),y) +CSRCS += stm32_buttons.c +endif + +ifeq ($(CONFIG_ADC),y) +CSRCS += stm32_adc.c +endif + +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/nucleo-f410rb/src/nucleo-f410rb.h b/boards/arm/stm32f4/nucleo-f410rb/src/nucleo-f410rb.h similarity index 98% rename from boards/arm/stm32/nucleo-f410rb/src/nucleo-f410rb.h rename to boards/arm/stm32f4/nucleo-f410rb/src/nucleo-f410rb.h index 1ff343716d0e6..a6f43ec0118de 100644 --- a/boards/arm/stm32/nucleo-f410rb/src/nucleo-f410rb.h +++ b/boards/arm/stm32f4/nucleo-f410rb/src/nucleo-f410rb.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f410rb/src/nucleo-f410rb.h + * boards/arm/stm32f4/nucleo-f410rb/src/nucleo-f410rb.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f4/nucleo-f410rb/src/stm32_adc.c b/boards/arm/stm32f4/nucleo-f410rb/src/stm32_adc.c new file mode 100644 index 0000000000000..db05549543825 --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f410rb/src/stm32_adc.c @@ -0,0 +1,142 @@ +/**************************************************************************** + * boards/arm/stm32f4/nucleo-f410rb/src/stm32_adc.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include +#include + +#include "chip.h" +#include "arm_internal.h" +#include "nucleo-f410rb.h" + +#ifdef CONFIG_STM32_ADC1 + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* The number of ADC channels in the conversion list */ + +#ifdef CONFIG_STM32_ADC1_DMA +# define ADC1_NCHANNELS 2 +#else +# define ADC1_NCHANNELS 1 +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* Identifying number of each ADC channel. */ + +#ifdef CONFIG_STM32_ADC1_DMA +/* ADC_IN0 and ADC_IN1 */ + +static const uint8_t g_adc1_chanlist[ADC1_NCHANNELS] = +{ + 9, 8 +}; + +/* Configurations of pins used byte each ADC channels */ + +static const uint32_t g_adc1_pinlist[ADC1_NCHANNELS] = +{ + GPIO_ADC1_IN9_0, GPIO_ADC1_IN8_0 +}; + +#else +/* Without DMA, only a single channel can be supported */ + +/* ADC_IN0 */ + +static const uint8_t g_adc1_chanlist[ADC1_NCHANNELS] = +{ + 9 +}; + +/* Configurations of pins used byte each ADC channels */ + +static const uint32_t g_adc1_pinlist[ADC1_NCHANNELS] = +{ + GPIO_ADC1_IN9_0 +}; + +#endif /* CONFIG_STM32_ADC1_DMA */ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_adc_setup + * + * Description: + * Initialize ADC and register the ADC driver. + * + ****************************************************************************/ + +int stm32_adc_setup(void) +{ + struct adc_dev_s *adc; + int ret; + int i; + + /* Configure the pins as analog inputs for the selected channels */ + + syslog(LOG_ERR, "stm32_adc_setup configuration: %d\n", ADC1_NCHANNELS); + + for (i = 0; i < ADC1_NCHANNELS; i++) + { + stm32_configgpio(g_adc1_pinlist[i]); + } + + /* Call stm32_adcinitialize() to get an instance of the ADC interface */ + + adc = stm32_adcinitialize(1, g_adc1_chanlist, ADC1_NCHANNELS); + if (adc == NULL) + { + aerr("ERROR: Failed to get ADC interface\n"); + return -ENODEV; + } + + /* Register the ADC driver at "/dev/adc0" */ + + ret = adc_register("/dev/adc0", adc); + if (ret < 0) + { + aerr("ERROR: adc_register failed: %d\n", ret); + return ret; + } + + return OK; +} + +#endif /* CONFIG_STM32_ADC1 */ diff --git a/boards/arm/stm32f4/nucleo-f410rb/src/stm32_autoleds.c b/boards/arm/stm32f4/nucleo-f410rb/src/stm32_autoleds.c new file mode 100644 index 0000000000000..f182bd93aedbe --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f410rb/src/stm32_autoleds.c @@ -0,0 +1,82 @@ +/**************************************************************************** + * boards/arm/stm32f4/nucleo-f410rb/src/stm32_autoleds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32.h" +#include "nucleo-f410rb.h" + +#ifdef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_autoled_initialize + ****************************************************************************/ + +void board_autoled_initialize(void) +{ + /* Configure LD2 GPIO for output */ + + stm32_configgpio(GPIO_LD2); +} + +/**************************************************************************** + * Name: board_autoled_on + ****************************************************************************/ + +void board_autoled_on(int led) +{ + if (led == 1) + { + stm32_gpiowrite(GPIO_LD2, true); + } +} + +/**************************************************************************** + * Name: board_autoled_off + ****************************************************************************/ + +void board_autoled_off(int led) +{ + if (led == 1) + { + stm32_gpiowrite(GPIO_LD2, false); + } +} + +#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32f4/nucleo-f410rb/src/stm32_boot.c b/boards/arm/stm32f4/nucleo-f410rb/src/stm32_boot.c new file mode 100644 index 0000000000000..41ead6f349cfd --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f410rb/src/stm32_boot.c @@ -0,0 +1,95 @@ +/**************************************************************************** + * boards/arm/stm32f4/nucleo-f410rb/src/stm32_boot.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include +#include +#include + +#include "arm_internal.h" +#include "nucleo-f410rb.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_boardinitialize + * + * Description: + * All STM32 architectures must provide the following entry point. This + * entry point is called early in the initialization -- after all memory + * has been configured and mapped but before any devices have been + * initialized. + * + ****************************************************************************/ + +void stm32_boardinitialize(void) +{ +#ifdef CONFIG_ARCH_LEDS + /* Configure on-board LEDs if LED support has been selected. */ + + board_autoled_initialize(); +#endif + +#ifdef CONFIG_ARCH_BUTTONS + /* Configure on-board BUTTONs if BUTTON support has been selected. */ + + board_button_initialize(); +#endif +} + +/**************************************************************************** + * Name: board_late_initialize + * + * Description: + * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_late_initialize(). board_late_initialize() will + * be called immediately after up_initialize() is called and just before + * the initial application is started. This additional initialization + * phase may be used, for example, to initialize board-specific device + * drivers. + * + ****************************************************************************/ + +#ifdef CONFIG_BOARD_LATE_INITIALIZE +void board_late_initialize(void) +{ + stm32_bringup(); +} +#endif diff --git a/boards/arm/stm32f4/nucleo-f410rb/src/stm32_bringup.c b/boards/arm/stm32f4/nucleo-f410rb/src/stm32_bringup.c new file mode 100644 index 0000000000000..53c3ee92501d1 --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f410rb/src/stm32_bringup.c @@ -0,0 +1,70 @@ +/**************************************************************************** + * boards/arm/stm32f4/nucleo-f410rb/src/stm32_bringup.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include + +#include + +#include "nucleo-f410rb.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_bringup + * + * Description: + * Perform architecture-specific initialization + * + * CONFIG_BOARD_LATE_INITIALIZE=y : + * Called from board_late_initialize(). + * + ****************************************************************************/ + +int stm32_bringup(void) +{ + int ret; + +#ifdef CONFIG_ADC + /* Initialize ADC and register the ADC driver. */ + + ret = stm32_adc_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_adc_setup failed: %d\n", ret); + } +#endif + + UNUSED(ret); + return OK; +} diff --git a/boards/arm/stm32f4/nucleo-f410rb/src/stm32_buttons.c b/boards/arm/stm32f4/nucleo-f410rb/src/stm32_buttons.c new file mode 100644 index 0000000000000..a400a0692c98e --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f410rb/src/stm32_buttons.c @@ -0,0 +1,115 @@ +/**************************************************************************** + * boards/arm/stm32f4/nucleo-f410rb/src/stm32_buttons.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include +#include + +#include "nucleo-f410rb.h" + +#ifdef CONFIG_ARCH_BUTTONS + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_button_initialize + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. + * + ****************************************************************************/ + +uint32_t board_button_initialize(void) +{ + /* Configure the single button as an input. NOTE that EXTI interrupts are + * also configured for the pin. + */ + + stm32_configgpio(GPIO_BTN_USER); + return NUM_BUTTONS; +} + +/**************************************************************************** + * Name: board_buttons + ****************************************************************************/ + +uint32_t board_buttons(void) +{ + /* Check that state of each USER button. A LOW value means that the key is + * pressed. + */ + + bool released = stm32_gpioread(GPIO_BTN_USER); + return !released; +} + +/**************************************************************************** + * Button support. + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. + * + * After board_button_initialize() has been called, board_buttons() may be + * called to collect the state of all buttons. board_buttons() returns an + * 32-bit bit set with each bit associated with a button. See the + * BUTTON_*_BIT definitions in board.h for the meaning of each bit. + * + * board_button_irq() may be called to register an interrupt handler that + * will be called when a button is depressed or released. The ID value is a + * button enumeration value that uniquely identifies a button resource. See + * the BUTTON_* definitions in board.h for the meaning of enumeration + * value. + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_IRQBUTTONS +int board_button_irq(int id, xcpt_t irqhandler, void *arg) +{ + int ret = -EINVAL; + + if (id == BUTTON_USER) + { + ret = stm32_gpiosetevent(GPIO_BTN_USER, true, true, true, + irqhandler, arg); + } + + return ret; +} +#endif +#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/stm32f4/nucleo-f410rb/src/stm32_userleds.c b/boards/arm/stm32f4/nucleo-f410rb/src/stm32_userleds.c new file mode 100644 index 0000000000000..80c619214d63b --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f410rb/src/stm32_userleds.c @@ -0,0 +1,197 @@ +/**************************************************************************** + * boards/arm/stm32f4/nucleo-f410rb/src/stm32_userleds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32.h" +#include "nucleo-f410rb.h" + +#ifndef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/* LED Power Management */ + +#ifdef CONFIG_PM +static void led_pm_notify(struct pm_callback_s *cb, int domain, + enum pm_state_e pmstate); +static int led_pm_prepare(struct pm_callback_s *cb, int domain, + enum pm_state_e pmstate); +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#ifdef CONFIG_PM +static struct pm_callback_s g_ledscb = +{ + .notify = led_pm_notify, + .prepare = led_pm_prepare, +}; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: led_pm_notify + * + * Description: + * Notify the driver of new power state. This callback is called after + * all drivers have had the opportunity to prepare for the new power state. + * + ****************************************************************************/ + +#ifdef CONFIG_PM +static void led_pm_notify(struct pm_callback_s *cb, int domain, + enum pm_state_e pmstate) +{ + switch (pmstate) + { + case PM_NORMAL: + { + /* Restore normal LEDs operation */ + } + break; + + case PM_IDLE: + { + /* Entering IDLE mode - Turn leds off */ + } + break; + + case PM_STANDBY: + { + /* Entering STANDBY mode - Logic for PM_STANDBY goes here */ + } + break; + + case PM_SLEEP: + { + /* Entering SLEEP mode - Logic for PM_SLEEP goes here */ + } + break; + + default: + { + /* Should not get here */ + } + break; + } +} +#endif + +/**************************************************************************** + * Name: led_pm_prepare + * + * Description: + * Request the driver to prepare for a new power state. This is a warning + * that the system is about to enter into a new power state. The driver + * should begin whatever operations that may be required to enter power + * state. The driver may abort the state change mode by returning a + * non-zero value from the callback function. + * + ****************************************************************************/ + +#ifdef CONFIG_PM +static int led_pm_prepare(struct pm_callback_s *cb, int domain, + enum pm_state_e pmstate) +{ + /* No preparation to change power modes is required by the LEDs driver. + * We always accept the state change by returning OK. + */ + + return OK; +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_userled_initialize + ****************************************************************************/ + +uint32_t board_userled_initialize(void) +{ + /* Configure LD2 GPIO for output */ + + stm32_configgpio(GPIO_LD2); + return BOARD_NLEDS; +} + +/**************************************************************************** + * Name: board_userled + ****************************************************************************/ + +void board_userled(int led, bool ledon) +{ + if (led == BOARD_LD2) + { + stm32_gpiowrite(GPIO_LD2, ledon); + } +} + +/**************************************************************************** + * Name: board_userled_all + ****************************************************************************/ + +void board_userled_all(uint32_t ledset) +{ + stm32_gpiowrite(GPIO_LD2, (ledset & BOARD_LD2_BIT) != 0); +} + +/**************************************************************************** + * Name: stm32_led_pminitialize + ****************************************************************************/ + +#ifdef CONFIG_PM +void stm32_led_pminitialize(void) +{ + /* Register to receive power management callbacks */ + + int ret = pm_register(&g_ledscb); + DEBUGASSERT(ret == OK); + UNUSED(ret); +} +#endif /* CONFIG_PM */ + +#endif /* !CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32f4/nucleo-f411re/CMakeLists.txt b/boards/arm/stm32f4/nucleo-f411re/CMakeLists.txt new file mode 100644 index 0000000000000..cbf8d25eb2d0e --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f411re/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32f4/nucleo-f411re/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/arm/stm32/nucleo-f411re/Kconfig b/boards/arm/stm32f4/nucleo-f411re/Kconfig similarity index 100% rename from boards/arm/stm32/nucleo-f411re/Kconfig rename to boards/arm/stm32f4/nucleo-f411re/Kconfig diff --git a/boards/arm/stm32f4/nucleo-f411re/configs/mcp2515-extid/defconfig b/boards/arm/stm32f4/nucleo-f411re/configs/mcp2515-extid/defconfig new file mode 100644 index 0000000000000..a15efeda08509 --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f411re/configs/mcp2515-extid/defconfig @@ -0,0 +1,59 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nucleo-f411re" +CONFIG_ARCH_BOARD_NUCLEO_F411RE=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F411RE=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=8499 +CONFIG_BUILTIN=y +CONFIG_CAN=y +CONFIG_CANUTILS_CANLIB=y +CONFIG_CAN_EXTID=y +CONFIG_CAN_MCP2515=y +CONFIG_EXAMPLES_CAN=y +CONFIG_EXAMPLES_CAN_NMSGS=1 +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_MCP2515_PHASESEG1=3 +CONFIG_MCP2515_PROPSEG=1 +CONFIG_MCP2515_SPI_SCK_FREQUENCY=500000 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=131072 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=14 +CONFIG_START_MONTH=10 +CONFIG_START_YEAR=2014 +CONFIG_STM32_CRC=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PWR=y +CONFIG_STM32_SPI1=y +CONFIG_STM32_USART1=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f4/nucleo-f411re/configs/nsh/defconfig b/boards/arm/stm32f4/nucleo-f411re/configs/nsh/defconfig new file mode 100644 index 0000000000000..97a7772143003 --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f411re/configs/nsh/defconfig @@ -0,0 +1,50 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nucleo-f411re" +CONFIG_ARCH_BOARD_NUCLEO_F411RE=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F411RE=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=8499 +CONFIG_BUILTIN=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=131072 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_SPI=y +CONFIG_START_DAY=14 +CONFIG_START_MONTH=10 +CONFIG_START_YEAR=2014 +CONFIG_STM32_CRC=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PWR=y +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f4/nucleo-f411re/include/board.h b/boards/arm/stm32f4/nucleo-f411re/include/board.h new file mode 100644 index 0000000000000..6613554b8c486 --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f411re/include/board.h @@ -0,0 +1,377 @@ +/**************************************************************************** + * boards/arm/stm32f4/nucleo-f411re/include/board.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_STM32_NUCLEO_F411RE_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32_NUCLEO_F411RE_INCLUDE_BOARD_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#ifndef __ASSEMBLY__ +# include +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Clocking *****************************************************************/ + +/* The NUCLEOF411RE supports both HSE and LSE crystals (X2 and X3). + * However, as shipped, the X2 and X3 crystals are not populated. + * Therefore the Nucleo-FF411RE will need to run off the 16MHz HSI clock. + * + * System Clock source : PLL (HSI) + * SYSCLK(Hz) : 104000000 Determined by PLL + * configuration + * HCLK(Hz) : 104000000 (STM32_RCC_CFGR_HPRE) + * AHB Prescaler : 1 (STM32_RCC_CFGR_HPRE) + * APB1 Prescaler : 2 (STM32_RCC_CFGR_PPRE1) + * APB2 Prescaler : 1 (STM32_RCC_CFGR_PPRE2) + * HSI Frequency(Hz) : 16000000 (nominal) + * PLLM : 8 (STM32_PLLCFG_PLLM) + * PLLN : 216 (STM32_PLLCFG_PLLN) + * PLLP : 4 (STM32_PLLCFG_PLLP) + * PLLQ : 9 (STM32_PLLCFG_PPQ) + * Flash Latency(WS) : 4 + * Prefetch Buffer : OFF + * Instruction cache : ON + * Data cache : ON + * Require 48MHz for USB OTG FS, : Enabled + * SDIO and RNG clock + */ + +/* HSI - 16 MHz RC factory-trimmed + * LSI - 32 KHz RC + * HSE - not installed + * LSE - not installed + */ + +#define STM32_HSI_FREQUENCY 16000000ul +#define STM32_LSI_FREQUENCY 32000 +#define STM32_BOARD_USEHSI 1 + +/* Main PLL Configuration. + * + * Formulae: + * + * VCO input frequency = PLL input clock frequency / PLLM, + * 2 <= PLLM <= 63 + * VCO output frequency = VCO input frequency × PLLN, + * 192 <= PLLN <= 432 + * PLL output clock frequency = VCO frequency / PLLP, + * PLLP = 2, 4, 6, or 8 + * USB OTG FS clock frequency = VCO frequency / PLLQ, + * 2 <= PLLQ <= 15 + * + + * There is no config for 100 MHz and 48 MHz for usb, + * so we would like to have SYSYCLK=104MHz and we must have + * the USB clock= 48MHz. + * + * PLLQ = 13 PLLP = 6 PLLN=390 PLLM=10 + * + * We will configure like this + * + * PLL source is HSI + * PLL_VCO = (STM32_HSI_FREQUENCY / PLLM) * PLLN + * = (16,000,000 / 10) * 390 + * = 624,000,000 + * SYSCLK = PLL_VCO / PLLP + * = 624,000,000 / 6 = 104,000,000 + * USB OTG FS and SDIO Clock + * = PLL_VCO / PLLQ + * = 624,000,000 / 13 = 48,000,000 + * + * REVISIT: Trimming of the HSI is not yet supported. + */ + +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(10) +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(390) +#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_6 +#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(13) + +#define STM32_SYSCLK_FREQUENCY 104000000ul + +/* AHB clock (HCLK) is SYSCLK (104MHz) */ + +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY + +/* APB1 clock (PCLK1) is HCLK/2 (52MHz) */ + +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd2 /* PCLK1 = HCLK / 2 */ +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/2) + +/* Timers driven from APB1 will be twice PCLK1 */ + +/* REVISIT */ + +#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) + +/* APB2 clock (PCLK2) is HCLK (104MHz) */ + +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ +#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/1) + +/* Timers driven from APB2 will be twice PCLK2 */ + +/* REVISIT */ + +#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM9_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB2_TIM10_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB2_TIM11_CLKIN (2*STM32_PCLK1_FREQUENCY) + +/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx + * otherwise frequency is 2xAPBx. + * Note: TIM1,8 are on APB2, others on APB1 + */ + +/* REVISIT */ + +#define BOARD_TIM1_FREQUENCY (2*STM32_PCLK2_FREQUENCY) +#define BOARD_TIM2_FREQUENCY (2*STM32_PCLK1_FREQUENCY) +#define BOARD_TIM3_FREQUENCY (2*STM32_PCLK1_FREQUENCY) +#define BOARD_TIM4_FREQUENCY (2*STM32_PCLK1_FREQUENCY) +#define BOARD_TIM5_FREQUENCY (2*STM32_PCLK1_FREQUENCY) +#define BOARD_TIM6_FREQUENCY (2*STM32_PCLK1_FREQUENCY) +#define BOARD_TIM7_FREQUENCY (2*STM32_PCLK1_FREQUENCY) +#define BOARD_TIM8_FREQUENCY (2*STM32_PCLK2_FREQUENCY) + +/* SDIO dividers. Note that slower clocking is required when DMA is disabled + * in order to avoid RX overrun/TX underrun errors due to delayed responses + * to service FIFOs in interrupt driven mode. These values have not been + * tuned!!! + * + * HCLK=72MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(178+2)=400 KHz + */ + +/* REVISIT */ + +#define SDIO_INIT_CLKDIV (178 << SDIO_CLKCR_CLKDIV_SHIFT) + +/* DMA ON: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(2+2)=18 MHz + * DMA OFF: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(3+2)=14.4 MHz + */ + +/* REVISIT */ + +#ifdef CONFIG_SDIO_DMA +# define SDIO_MMCXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT) +#else +# define SDIO_MMCXFR_CLKDIV (3 << SDIO_CLKCR_CLKDIV_SHIFT) +#endif + +/* DMA ON: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(1+2)=24 MHz + * DMA OFF: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(3+2)=14.4 MHz + */ + +/* REVISIT */ + +#ifdef CONFIG_SDIO_DMA +# define SDIO_SDXFR_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT) +#else +# define SDIO_SDXFR_CLKDIV (3 << SDIO_CLKCR_CLKDIV_SHIFT) +#endif + +/* DMA Channel/Stream Selections ********************************************/ + +/* Stream selections are arbitrary for now but might become important in + * the future is we set aside more DMA channels/streams. + * + * SDIO DMA + *   DMAMAP_SDIO_1 = Channel 4, Stream 3 <- may later be used by SPI DMA + *   DMAMAP_SDIO_2 = Channel 4, Stream 6 + */ + +#define DMAMAP_SDIO DMAMAP_SDIO_1 + +/* Need to VERIFY fwb */ + +#define DMACHAN_SPI1_RX DMAMAP_SPI1_RX_1 +#define DMACHAN_SPI1_TX DMAMAP_SPI1_TX_1 +#define DMACHAN_SPI2_RX DMAMAP_SPI2_RX +#define DMACHAN_SPI2_TX DMAMAP_SPI2_TX + +/* Alternate function pin selections ****************************************/ + +/* USART1: + * RXD: PA10 CN9 pin 3, CN10 pin 33 + * PB7 CN7 pin 21 + * TXD: PA9 CN5 pin 1, CN10 pin 21 + * PB6 CN5 pin 3, CN10 pin 17 + */ + +#if 1 +# define GPIO_USART1_RX (GPIO_USART1_RX_1|GPIO_SPEED_100MHz) /* PA10 */ +# define GPIO_USART1_TX (GPIO_USART1_TX_1|GPIO_SPEED_100MHz) /* PA9 */ +#else +# define GPIO_USART1_RX (GPIO_USART1_RX_2|GPIO_SPEED_100MHz) /* PB7 */ +# define GPIO_USART1_TX (GPIO_USART1_TX_2|GPIO_SPEED_100MHz) /* PB6 */ +#endif + +/* USART2: + * RXD: PA3 CN9 pin 1 (See SB13, 14, 62, 63). CN10 pin 37 + * PD6 + * TXD: PA2 CN9 pin 2(See SB13, 14, 62, 63). CN10 pin 35 + * PD5 + */ + +#define GPIO_USART2_RX (GPIO_USART2_RX_1|GPIO_SPEED_100MHz) /* PA3 */ +#define GPIO_USART2_TX (GPIO_USART2_TX_1|GPIO_SPEED_100MHz) /* PA2 */ +#define GPIO_USART2_RTS GPIO_USART2_RTS_2 +#define GPIO_USART2_CTS GPIO_USART2_CTS_2 + +/* USART6: + * RXD: PC7 CN5 pin2, CN10 pin 19 + * PA12 CN10, pin 12 + * TXD: PC6 CN10, pin 4 + * PA11 CN10, pin 14 + */ + +#define GPIO_USART6_RX (GPIO_USART6_RX_1|GPIO_SPEED_100MHz) /* PC7 */ +#define GPIO_USART6_TX (GPIO_USART6_TX_1|GPIO_SPEED_100MHz) /* PC6 */ + +/* UART RX DMA configurations */ + +#define DMAMAP_USART1_RX DMAMAP_USART1_RX_2 +#define DMAMAP_USART6_RX DMAMAP_USART6_RX_2 + +/* I2C + * + * The optional _GPIO configurations allow the I2C driver to manually + * reset the bus to clear stuck slaves. They match the pin configuration, + * but are normally-high GPIOs. + */ + +#define GPIO_I2C1_SCL (GPIO_I2C1_SCL_2|GPIO_SPEED_50MHz) +#define GPIO_I2C1_SDA (GPIO_I2C1_SDA_2|GPIO_SPEED_50MHz) +#define GPIO_I2C1_SCL_GPIO \ + (GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTB|GPIO_PIN8) +#define GPIO_I2C1_SDA_GPIO \ + (GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTB|GPIO_PIN9) + +#define GPIO_I2C2_SCL (GPIO_I2C2_SCL_1|GPIO_SPEED_50MHz) +#define GPIO_I2C2_SDA (GPIO_I2C2_SDA_1|GPIO_SPEED_50MHz) +#define GPIO_I2C2_SCL_GPIO \ + (GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTB|GPIO_PIN10) +#define GPIO_I2C2_SDA_GPIO \ + (GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTB|GPIO_PIN11) + +/* SPI + * + * There are sensors on SPI1, and SPI2 is connected to the FRAM. + */ + +#define GPIO_SPI1_MISO (GPIO_SPI1_MISO_1|GPIO_SPEED_50MHz) +#define GPIO_SPI1_MOSI (GPIO_SPI1_MOSI_1|GPIO_SPEED_50MHz) +#define GPIO_SPI1_SCK (GPIO_SPI1_SCK_1|GPIO_SPEED_50MHz) + +#define GPIO_SPI2_MISO (GPIO_SPI2_MISO_1|GPIO_SPEED_50MHz) +#define GPIO_SPI2_MOSI (GPIO_SPI2_MOSI_1|GPIO_SPEED_50MHz) +#define GPIO_SPI2_SCK (GPIO_SPI2_SCK_2|GPIO_SPEED_50MHz) + +/* LEDs + * + * The Nucleo F411RE board provide a single user LED, LD2. LD2 + * is the green LED connected to Arduino signal D13 corresponding to MCU I/O + * PA5 (pin 21) or PB13 (pin 34) depending on the STM32 target. + * + * - When the I/O is HIGH value, the LED is on. + * - When the I/O is LOW, the LED is off. + */ + +/* LED index values for use with board_userled() */ + +#define BOARD_LD2 0 +#define BOARD_NLEDS 1 + +/* LED bits for use with board_userled_all() */ + +#define BOARD_LD2_BIT (1 << BOARD_LD2) + +/* These LEDs are not used by the board port unless CONFIG_ARCH_LEDS is + * defined. In that case, the usage by the board port is defined in + * include/board.h and src/sam_leds.c. The LEDs are used to encode OS-related + * events as follows when the red LED (PE24) is available: + * + * SYMBOL Meaning LD2 + * ------------------- ----------------------- ----------- + * LED_STARTED NuttX has been started OFF + * LED_HEAPALLOCATE Heap has been allocated OFF + * LED_IRQSENABLED Interrupts enabled OFF + * LED_STACKCREATED Idle stack created ON + * LED_INIRQ In an interrupt No change + * LED_SIGNAL In a signal handler No change + * LED_ASSERTION An assertion failed No change + * LED_PANIC The system has crashed Blinking + * LED_IDLE MCU is in sleep mode Not used + * + * Thus if LD2, NuttX has successfully booted and is, apparently, running + * normally. If LD2 is flashing at approximately 2Hz, then a fatal error + * has been detected and the system has halted. + */ + +#define LED_STARTED 0 +#define LED_HEAPALLOCATE 0 +#define LED_IRQSENABLED 0 +#define LED_STACKCREATED 1 +#define LED_INIRQ 2 +#define LED_SIGNAL 2 +#define LED_ASSERTION 2 +#define LED_PANIC 1 + +/* Buttons + * + * B1 USER: + * the user button is connected to the I/O PC13 (pin 2) of the STM32 + * microcontroller. + */ + +#define BUTTON_USER 0 +#define NUM_BUTTONS 1 + +#define BUTTON_USER_BIT (1 << BUTTON_USER) + +#define GPIO_TIM2_CH1IN (GPIO_TIM2_CH1IN_1 | GPIO_PULLUP | GPIO_SPEED_50MHz) +#define GPIO_TIM2_CH2IN (GPIO_TIM2_CH2IN_1 | GPIO_PULLUP | GPIO_SPEED_50MHz) + +/* USB OTG FS */ + +#define GPIO_OTGFS_DM (GPIO_OTGFS_DM_0|GPIO_SPEED_100MHz) +#define GPIO_OTGFS_DP (GPIO_OTGFS_DP_0|GPIO_SPEED_100MHz) +#define GPIO_OTGFS_ID (GPIO_OTGFS_ID_0|GPIO_SPEED_100MHz) +#define GPIO_OTGFS_SOF (GPIO_OTGFS_SOF_0|GPIO_SPEED_100MHz) + +#endif /* __BOARDS_ARM_STM32_NUCLEO_F411RE_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32f4/nucleo-f411re/scripts/Make.defs b/boards/arm/stm32f4/nucleo-f411re/scripts/Make.defs new file mode 100644 index 0000000000000..15d0e61e1e998 --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f411re/scripts/Make.defs @@ -0,0 +1,43 @@ +############################################################################ +# boards/arm/stm32f4/nucleo-f411re/scripts/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/.config +include $(TOPDIR)/tools/Config.mk +include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs + +LDSCRIPT = flash.ld + +ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) + +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 + diff --git a/boards/arm/stm32f4/nucleo-f411re/scripts/flash.ld b/boards/arm/stm32f4/nucleo-f411re/scripts/flash.ld new file mode 100644 index 0000000000000..2a160e7bbfca3 --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f411re/scripts/flash.ld @@ -0,0 +1,121 @@ +/**************************************************************************** + * boards/arm/stm32f4/nucleo-f411re/scripts/flash.ld + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* The STM32F411RE has 512Kb of FLASH beginning at address 0x0800:0000 and + * 128Kb of SRAM beginning at address 0x2000:0000. When booting from FLASH, + * FLASH memory is aliased to address 0x0000:0000 where the code expects to + * begin execution by jumping to the entry point in the 0x0800:0000 address + * range. + */ + +MEMORY +{ + flash (rx) : ORIGIN = 0x08000000, LENGTH = 512K + sram (rwx) : ORIGIN = 0x20000000, LENGTH = 128K +} + +OUTPUT_ARCH(arm) +EXTERN(_vectors) +ENTRY(_stext) +SECTIONS +{ + .text : { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > flash + + .init_section : { + _sinit = ABSOLUTE(.); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) + _einit = ABSOLUTE(.); + } > flash + + .tdata : { + _stdata = ABSOLUTE(.); + *(.tdata .tdata.* .gnu.linkonce.td.*); + _etdata = ABSOLUTE(.); + } > flash + + .tbss : { + _stbss = ABSOLUTE(.); + *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); + _etbss = ABSOLUTE(.); + } > flash + + .ARM.extab : { + *(.ARM.extab*) + } > flash + + __exidx_start = ABSOLUTE(.); + .ARM.exidx : { + *(.ARM.exidx*) + } > flash + __exidx_end = ABSOLUTE(.); + + _eronly = ABSOLUTE(.); + + /* The STM32F103VCT6 has 48Kb of SRAM beginning at the following address */ + + .data : { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > sram AT > flash + + .bss : { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(8); + _ebss = ABSOLUTE(.); + } > sram + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/stm32f4/nucleo-f411re/src/CMakeLists.txt b/boards/arm/stm32f4/nucleo-f411re/src/CMakeLists.txt new file mode 100644 index 0000000000000..951b203a531f1 --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f411re/src/CMakeLists.txt @@ -0,0 +1,54 @@ +# ############################################################################## +# boards/arm/stm32f4/nucleo-f411re/src/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(SRCS stm32_boot.c stm32_spi.c stm32_bringup.c) + +if(CONFIG_VIDEO_FB) + if(CONFIG_LCD_SSD1306) + list(APPEND SRCS stm32_lcd_ssd1306.c) + endif() +endif() + +if(CONFIG_ARCH_LEDS) + list(APPEND SRCS stm32_autoleds.c) +else() + list(APPEND SRCS stm32_userleds.c) +endif() + +if(CONFIG_ARCH_BUTTONS) + list(APPEND SRCS stm32_buttons.c) +endif() + +if(CONFIG_ADC) + list(APPEND SRCS stm32_adc.c) + if(CONFIG_INPUT_AJOYSTICK) + list(APPEND SRCS stm32_ajoystick.c) + endif() +endif() + +if(CONFIG_CAN_MCP2515) + list(APPEND SRCS stm32_mcp2515.c) +endif() + +target_sources(board PRIVATE ${SRCS}) + +set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/flash.ld") diff --git a/boards/arm/stm32f4/nucleo-f411re/src/Make.defs b/boards/arm/stm32f4/nucleo-f411re/src/Make.defs new file mode 100644 index 0000000000000..9f0e1dfa8db92 --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f411re/src/Make.defs @@ -0,0 +1,56 @@ +############################################################################ +# boards/arm/stm32f4/nucleo-f411re/src/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +CSRCS = stm32_boot.c stm32_spi.c stm32_bringup.c + +ifeq ($(CONFIG_VIDEO_FB),y) +ifeq ($(CONFIG_LCD_SSD1306),y) + CSRCS += stm32_lcd_ssd1306.c +endif +endif + +ifeq ($(CONFIG_ARCH_LEDS),y) +CSRCS += stm32_autoleds.c +else +CSRCS += stm32_userleds.c +endif + +ifeq ($(CONFIG_ARCH_BUTTONS),y) +CSRCS += stm32_buttons.c +endif + +ifeq ($(CONFIG_ADC),y) +CSRCS += stm32_adc.c +ifeq ($(CONFIG_INPUT_AJOYSTICK),y) +CSRCS += stm32_ajoystick.c +endif +endif + +ifeq ($(CONFIG_CAN_MCP2515),y) + CSRCS += stm32_mcp2515.c +endif + +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/nucleo-f411re/src/nucleo-f411re.h b/boards/arm/stm32f4/nucleo-f411re/src/nucleo-f411re.h similarity index 99% rename from boards/arm/stm32/nucleo-f411re/src/nucleo-f411re.h rename to boards/arm/stm32f4/nucleo-f411re/src/nucleo-f411re.h index 036d7b73c37de..2f052ef44dc34 100644 --- a/boards/arm/stm32/nucleo-f411re/src/nucleo-f411re.h +++ b/boards/arm/stm32f4/nucleo-f411re/src/nucleo-f411re.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f411re/src/nucleo-f411re.h + * boards/arm/stm32f4/nucleo-f411re/src/nucleo-f411re.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f4/nucleo-f411re/src/stm32_adc.c b/boards/arm/stm32f4/nucleo-f411re/src/stm32_adc.c new file mode 100644 index 0000000000000..d07d2edbc6aae --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f411re/src/stm32_adc.c @@ -0,0 +1,142 @@ +/**************************************************************************** + * boards/arm/stm32f4/nucleo-f411re/src/stm32_adc.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32_adc.h" +#include "nucleo-f411re.h" + +#include + +#ifdef CONFIG_STM32_ADC1 + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* The number of ADC channels in the conversion list */ + +#ifdef CONFIG_ADC_DMA +# define ADC1_NCHANNELS 2 +#else +# define ADC1_NCHANNELS 1 +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* Identifying number of each ADC channel. */ + +#ifdef CONFIG_ADC_DMA +/* Configure ADC inputs on ADC_IN0 and ADC_IN1 */ + +static const uint8_t g_adc1_chanlist[ADC1_NCHANNELS] = +{ + 0, 1 +}; + +/* Configurations of pins used byte each ADC channels */ + +static const uint32_t g_adc1_pinlist[ADC1_NCHANNELS] = +{ + GPIO_ADC1_IN0, GPIO_ADC1_IN0 +}; + +#else +/* Without DMA, only a single channel can be supported */ + +/* Configura ADC input on ADC_IN0 */ + +static const uint8_t g_adc1_chanlist[ADC1_NCHANNELS] = +{ + 0 +}; + +/* Configurations of pins used byte each ADC channels */ + +static const uint32_t g_adc1_pinlist[ADC1_NCHANNELS] = +{ + GPIO_ADC1_IN0 +}; + +#endif /* CONFIG_ADC_DMA */ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_adc_setup + * + * Description: + * Initialize ADC and register the ADC driver. + * + ****************************************************************************/ + +int stm32_adc_setup(void) +{ + struct adc_dev_s *adc; + int ret; + int i; + + /* Configure the pins as analog inputs for the selected channels */ + + for (i = 0; i < ADC1_NCHANNELS; i++) + { + stm32_configgpio(g_adc1_pinlist[i]); + } + + /* Call stm32_adcinitialize() to get an instance of the ADC interface */ + + adc = stm32_adcinitialize(1, g_adc1_chanlist, ADC1_NCHANNELS); + if (adc == NULL) + { + aerr("ERROR: Failed to get ADC interface\n"); + return -ENODEV; + } + + /* Register the ADC driver at "/dev/adc0" */ + + ret = adc_register("/dev/adc0", adc); + if (ret < 0) + { + aerr("ERROR: adc_register failed: %d\n", ret); + return ret; + } + + return OK; +} + +#endif /* CONFIG_STM32_ADC1 */ diff --git a/boards/arm/stm32f4/nucleo-f411re/src/stm32_ajoystick.c b/boards/arm/stm32f4/nucleo-f411re/src/stm32_ajoystick.c new file mode 100644 index 0000000000000..9ba5d9f69aa94 --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f411re/src/stm32_ajoystick.c @@ -0,0 +1,490 @@ +/**************************************************************************** + * boards/arm/stm32f4/nucleo-f411re/src/stm32_ajoystick.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include "stm32_gpio.h" +#include "stm32_adc.h" +#include "hardware/stm32_adc.h" +#include "nucleo-f411re.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Check for pre-requisites and pin conflicts */ + +#ifdef CONFIG_INPUT_AJOYSTICK +# if !defined(CONFIG_ADC) +# error CONFIG_ADC is required for the Itead joystick +# undef CONFIG_INPUT_AJOYSTICK +# elif !defined(CONFIG_STM32_ADC1) +# error CONFIG_STM32_ADC1 is required for Itead joystick +# undef CONFIG_INPUT_AJOYSTICK +# endif +#endif /* CONFIG_INPUT_AJOYSTICK */ + +#ifdef CONFIG_INPUT_AJOYSTICK + +/* A no-ADC, buttons only version can be built for testing */ + +#undef NO_JOYSTICK_ADC + +/* Maximum number of ADC channels */ + +#define MAX_ADC_CHANNELS 8 + +/* Dual channel ADC support requires DMA */ + +#ifdef CONFIG_ADC_DMA +# define NJOYSTICK_CHANNELS 2 +#else +# define NJOYSTICK_CHANNELS 1 +#endif + +#ifdef CONFIG_NUCLEO_F411RE_AJOY_MINBUTTONS +/* Number of Joystick buttons */ + +# define AJOY_NGPIOS 3 + +/* Bitset of supported Joystick buttons */ + +# define AJOY_SUPPORTED (AJOY_BUTTON_1_BIT | AJOY_BUTTON_2_BIT | \ + AJOY_BUTTON_3_BIT) +#else +/* Number of Joystick buttons */ + +# define AJOY_NGPIOS 7 + +/* Bitset of supported Joystick buttons */ + +# define AJOY_SUPPORTED (AJOY_BUTTON_1_BIT | AJOY_BUTTON_2_BIT | \ + AJOY_BUTTON_3_BIT | AJOY_BUTTON_4_BIT | \ + AJOY_BUTTON_5_BIT | AJOY_BUTTON_6_BIT | \ + AJOY_BUTTON_7_BIT ) +#endif + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +static ajoy_buttonset_t +ajoy_supported(const struct ajoy_lowerhalf_s *lower); +static int ajoy_sample(const struct ajoy_lowerhalf_s *lower, + struct ajoy_sample_s *sample); +static ajoy_buttonset_t +ajoy_buttons(const struct ajoy_lowerhalf_s *lower); +static void ajoy_enable(const struct ajoy_lowerhalf_s *lower, + ajoy_buttonset_t press, ajoy_buttonset_t release, + ajoy_handler_t handler, void *arg); + +static void ajoy_disable(void); +static int ajoy_interrupt(int irq, void *context, void *arg); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* Pin configuration for each Itead joystick button. Index using AJOY_* + * button definitions in include/nuttx/input/ajoystick.h. + */ + +#ifdef CONFIG_NUCLEO_F411RE_AJOY_MINBUTTONS +static const uint32_t g_joygpio[AJOY_NGPIOS] = +{ + GPIO_BUTTON_1, GPIO_BUTTON_2, GPIO_BUTTON_3 +}; +#else +static const uint32_t g_joygpio[AJOY_NGPIOS] = +{ + GPIO_BUTTON_1, GPIO_BUTTON_2, GPIO_BUTTON_3, GPIO_BUTTON_4, + GPIO_BUTTON_5, GPIO_BUTTON_6, GPIO_BUTTON_7 +}; +#endif + +/* This is the button joystick lower half driver interface */ + +static const struct ajoy_lowerhalf_s g_ajoylower = +{ + .al_supported = ajoy_supported, + .al_sample = ajoy_sample, + .al_buttons = ajoy_buttons, + .al_enable = ajoy_enable, +}; + +#ifndef NO_JOYSTICK_ADC +/* Thread-independent file structure for the open ADC driver */ + +static struct file g_adcfile; +#endif + +/* Current interrupt handler and argument */ + +static ajoy_handler_t g_ajoyhandler; +static void *g_ajoyarg; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: ajoy_supported + * + * Description: + * Return the set of buttons supported on the button joystick device + * + ****************************************************************************/ + +static ajoy_buttonset_t +ajoy_supported(const struct ajoy_lowerhalf_s *lower) +{ + iinfo("Supported: %02x\n", AJOY_SUPPORTED); + return (ajoy_buttonset_t)AJOY_SUPPORTED; +} + +/**************************************************************************** + * Name: ajoy_sample + * + * Description: + * Return the current state of all button joystick buttons + * + ****************************************************************************/ + +static int ajoy_sample(const struct ajoy_lowerhalf_s *lower, + struct ajoy_sample_s *sample) +{ +#ifndef NO_JOYSTICK_ADC + struct adc_msg_s adcmsg[MAX_ADC_CHANNELS]; + struct adc_msg_s *ptr; + ssize_t nread; + ssize_t offset; + int have; + int i; + + /* Read all of the available samples (handling the case where additional + * channels are enabled). + */ + + nread = file_read(&g_adcfile, adcmsg, + MAX_ADC_CHANNELS * sizeof(struct adc_msg_s)); + if (nread < 0) + { + if (nread != -EINTR) + { + ierr("ERROR: read failed: %d\n", (int)nread); + } + + return nread; + } + else if (nread < NJOYSTICK_CHANNELS * sizeof(struct adc_msg_s)) + { + ierr("ERROR: read too small: %ld\n", (long)nread); + return -EIO; + } + + /* Sample and the raw analog inputs */ + +#ifdef CONFIG_ADC_DMA + have = 0; + +#else + /* If DMA is not supported, then we will have only a single ADC channel */ + + have = 2; + sample->as_y = 0; +#endif + + for (i = 0, offset = 0; + i < MAX_ADC_CHANNELS && offset < nread && have != 3; + i++, offset += sizeof(struct adc_msg_s)) + { + ptr = &adcmsg[i]; + + /* Is this one of the channels that we need? */ + + if ((have & 1) == 0 && ptr->am_channel == 0) + { + int32_t tmp = ptr->am_data; + sample->as_x = (int16_t)tmp; + have |= 1; + + iinfo("X sample: %ld -> %d\n", (long)tmp, (int)sample->as_x); + } + +#ifdef CONFIG_ADC_DMA + if ((have & 2) == 0 && ptr->am_channel == 1) + { + int32_t tmp = ptr->am_data; + sample->as_y = (int16_t)tmp; + have |= 2; + + iinfo("Y sample: %ld -> %d\n", (long)tmp, (int)sample->as_y); + } +#endif + } + + if (have != 3) + { + ierr("ERROR: Could not find joystick channels\n"); + return -EIO; + } + +#else + /* ADC support is disabled */ + + sample->as_x = 0; + sample->as_y = 0; +#endif + + /* Sample the discrete button inputs */ + + sample->as_buttons = ajoy_buttons(lower); + iinfo("Returning: %02x\n", sample->as_buttons); + return OK; +} + +/**************************************************************************** + * Name: ajoy_buttons + * + * Description: + * Return the current state of button data (only) + * + ****************************************************************************/ + +static ajoy_buttonset_t +ajoy_buttons(const struct ajoy_lowerhalf_s *lower) +{ + ajoy_buttonset_t ret = 0; + int i; + + /* Read each joystick GPIO value */ + + for (i = 0; i < AJOY_NGPIOS; i++) + { + /* Button outputs are pulled high. So a sensed low level means that the + * button is pressed. + */ + + if (!stm32_gpioread(g_joygpio[i])) + { + ret |= (1 << i); + } + } + + iinfo("Returning: %02x\n", ret); + return ret; +} + +/**************************************************************************** + * Name: ajoy_enable + * + * Description: + * Enable interrupts on the selected set of joystick buttons. And empty + * set will disable all interrupts. + * + ****************************************************************************/ + +static void ajoy_enable(const struct ajoy_lowerhalf_s *lower, + ajoy_buttonset_t press, ajoy_buttonset_t release, + ajoy_handler_t handler, void *arg) +{ + irqstate_t flags; + ajoy_buttonset_t either = press | release; + ajoy_buttonset_t bit; + bool rising; + bool falling; + int i; + + /* Start with all interrupts disabled */ + + flags = enter_critical_section(); + ajoy_disable(); + + iinfo("press: %02x release: %02x handler: %p arg: %p\n", + press, release, handler, arg); + + /* If no events are indicated or if no handler is provided, then this + * must really be a request to disable interrupts. + */ + + if (either && handler) + { + /* Save the new the handler and argument */ + + g_ajoyhandler = handler; + g_ajoyarg = arg; + + /* Check each GPIO. */ + + for (i = 0; i < AJOY_NGPIOS; i++) + { + /* Enable interrupts on each pin that has either a press or + * release event associated with it. + */ + + bit = (1 << i); + if ((either & bit) != 0) + { + /* Active low so a press corresponds to a falling edge and + * a release corresponds to a rising edge. + */ + + falling = ((press & bit) != 0); + rising = ((release & bit) != 0); + + iinfo("GPIO %d: rising: %d falling: %d\n", + i, rising, falling); + + stm32_gpiosetevent(g_joygpio[i], rising, falling, + true, ajoy_interrupt, NULL); + } + } + } + + leave_critical_section(flags); +} + +/**************************************************************************** + * Name: ajoy_disable + * + * Description: + * Disable all joystick interrupts + * + ****************************************************************************/ + +static void ajoy_disable(void) +{ + irqstate_t flags; + int i; + + /* Disable each joystick interrupt */ + + flags = enter_critical_section(); + for (i = 0; i < AJOY_NGPIOS; i++) + { + stm32_gpiosetevent(g_joygpio[i], false, false, false, NULL, NULL); + } + + leave_critical_section(flags); + + /* Nullify the handler and argument */ + + g_ajoyhandler = NULL; + g_ajoyarg = NULL; +} + +/**************************************************************************** + * Name: ajoy_interrupt + * + * Description: + * Discrete joystick interrupt handler + * + ****************************************************************************/ + +static int ajoy_interrupt(int irq, void *context, void *arg) +{ + DEBUGASSERT(g_ajoyhandler); + + if (g_ajoyhandler) + { + g_ajoyhandler(&g_ajoylower, g_ajoyarg); + } + + return OK; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_ajoy_initialize + * + * Description: + * Initialize and register the button joystick driver + * + ****************************************************************************/ + +int board_ajoy_initialize(void) +{ + int ret; + int i; + +#ifndef NO_JOYSTICK_ADC + iinfo("Initialize ADC driver: /dev/adc0\n"); + + /* NOTE: The ADC driver was initialized earlier in the bring-up sequence. */ + + /* Open the ADC driver for reading. */ + + ret = file_open(&g_adcfile, "/dev/adc0", O_RDONLY); + if (ret < 0) + { + ierr("ERROR: Failed to open /dev/adc0: %d\n", ret); + return ret; + } +#endif + + /* Configure the GPIO pins as interrupting inputs. NOTE: This is + * unnecessary for interrupting pins since it will also be done by + * stm32_gpiosetevent(). + */ + + for (i = 0; i < AJOY_NGPIOS; i++) + { + /* Configure the PIO as an input */ + + stm32_configgpio(g_joygpio[i]); + } + + /* Register the joystick device as /dev/ajoy0 */ + + iinfo("Initialize joystick driver: /dev/ajoy0\n"); + + ret = ajoy_register("/dev/ajoy0", &g_ajoylower); + if (ret < 0) + { + ierr("ERROR: ajoy_register failed: %d\n", ret); +#ifndef NO_JOYSTICK_ADC + file_close(&g_adcfile); +#endif + } + + return ret; +} + +#endif /* CONFIG_INPUT_AJOYSTICK */ diff --git a/boards/arm/stm32f4/nucleo-f411re/src/stm32_autoleds.c b/boards/arm/stm32f4/nucleo-f411re/src/stm32_autoleds.c new file mode 100644 index 0000000000000..16655c5a13e3d --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f411re/src/stm32_autoleds.c @@ -0,0 +1,83 @@ +/**************************************************************************** + * boards/arm/stm32f4/nucleo-f411re/src/stm32_autoleds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32.h" +#include "nucleo-f411re.h" + +#include + +#ifdef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_autoled_initialize + ****************************************************************************/ + +void board_autoled_initialize(void) +{ + /* Configure LD2 GPIO for output */ + + stm32_configgpio(GPIO_LD2); +} + +/**************************************************************************** + * Name: board_autoled_on + ****************************************************************************/ + +void board_autoled_on(int led) +{ + if (led == 1) + { + stm32_gpiowrite(GPIO_LD2, true); + } +} + +/**************************************************************************** + * Name: board_autoled_off + ****************************************************************************/ + +void board_autoled_off(int led) +{ + if (led == 1) + { + stm32_gpiowrite(GPIO_LD2, false); + } +} + +#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32f4/nucleo-f411re/src/stm32_boot.c b/boards/arm/stm32f4/nucleo-f411re/src/stm32_boot.c new file mode 100644 index 0000000000000..aabbaf87e948d --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f411re/src/stm32_boot.c @@ -0,0 +1,101 @@ +/**************************************************************************** + * boards/arm/stm32f4/nucleo-f411re/src/stm32_boot.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include +#include + +#include + +#include "arm_internal.h" +#include "nucleo-f411re.h" + +#include + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_boardinitialize + * + * Description: + * All STM32 architectures must provide the following entry point. + * This entry point is called early in the initialization -- after all + * memory has been configured and mapped but before any devices have been + * initialized. + * + ****************************************************************************/ + +void stm32_boardinitialize(void) +{ + /* Configure on-board LEDs if LED support has been selected. */ + +#ifdef CONFIG_ARCH_LEDS + board_autoled_initialize(); +#endif + + /* Configure SPI chip selects if 1) SP2 is not disabled, and 2) the weak + * function stm32_spidev_initialize() has been brought into the link. + */ + +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || defined(CONFIG_STM32_SPI3) + stm32_spidev_initialize(); +#endif + + /* Initialize USB is 1) USBDEV is selected, 2) the USB controller is not + * disabled, and 3) the weak function stm32_usbinitialize() has been + * brought into the build. + */ + +#if defined(CONFIG_USBDEV) && defined(CONFIG_STM32_USB) + stm32_usbinitialize(); +#endif +} + +/**************************************************************************** + * Name: board_late_initialize + * + * Description: + * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_late_initialize(). board_late_initialize() will + * be called immediately after up_initialize() is called and just before + * the initial application is started. This additional initialization + * phase may be used, for example, to initialize board-specific device + * drivers. + * + ****************************************************************************/ + +#ifdef CONFIG_BOARD_LATE_INITIALIZE +void board_late_initialize(void) +{ + stm32_bringup(); +} +#endif diff --git a/boards/arm/stm32f4/nucleo-f411re/src/stm32_bringup.c b/boards/arm/stm32f4/nucleo-f411re/src/stm32_bringup.c new file mode 100644 index 0000000000000..5d0025fdac224 --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f411re/src/stm32_bringup.c @@ -0,0 +1,213 @@ +/**************************************************************************** + * boards/arm/stm32f4/nucleo-f411re/src/stm32_bringup.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include +#include +#include + +#include +#include + +#include + +#ifdef CONFIG_USERLED +# include +#endif + +#ifdef CONFIG_INPUT_BUTTONS +# include +#endif + +#include "nucleo-f411re.h" + +#include + +#ifdef CONFIG_SENSORS_QENCODER +#include "board_qencoder.h" +#endif + +#undef HAVE_LEDS +#if !defined(CONFIG_ARCH_LEDS) && defined(CONFIG_USERLED_LOWER) +# define HAVE_LEDS 1 +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_bringup + * + * Description: + * Perform architecture-specific initialization + * + * CONFIG_BOARD_LATE_INITIALIZE=y : + * Called from board_late_initialize(). + * + ****************************************************************************/ + +int stm32_bringup(void) +{ + int ret = OK; + +#ifdef HAVE_LEDS + /* Register the LED driver */ + + ret = userled_lower_initialize("/dev/userleds"); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: userled_lower_initialize() failed: %d\n", ret); + return ret; + } +#endif + +#ifdef CONFIG_INPUT_BUTTONS + /* Register the BUTTON driver */ + + ret = btn_lower_initialize("/dev/buttons"); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: btn_lower_initialize() failed: %d\n", ret); + } +#endif + + /* Configure SPI-based devices */ + +#ifdef CONFIG_STM32_SPI1 + /* Get the SPI port */ + + struct spi_dev_s *spi; + + spi = stm32_spibus_initialize(1); + if (!spi) + { + syslog(LOG_ERR, "ERROR: Failed to initialize SPI port 1\n"); + return -ENODEV; + } + +#if defined(CONFIG_LCD_SSD1306_SPI) && !defined(CONFIG_VIDEO_FB) + board_lcd_initialize(); +#endif + +#ifdef CONFIG_VIDEO_FB + ret = fb_register(0, 0); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: fb_register() failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_CAN_MCP2515 +#ifdef CONFIG_STM32_SPI1 + stm32_configgpio(GPIO_MCP2515_CS); /* MEMS chip select */ +#endif + + /* Configure and initialize the MCP2515 CAN device */ + + ret = stm32_mcp2515initialize("/dev/can0"); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_mcp2515initialize() failed: %d\n", ret); + } +#endif +#endif + +#ifdef HAVE_MMCSD + /* First, get an instance of the SDIO interface */ + + g_sdio = sdio_initialize(CONFIG_NSH_MMCSDSLOTNO); + if (!g_sdio) + { + syslog(LOG_ERR, "ERROR: Failed to initialize SDIO slot %d\n", + CONFIG_NSH_MMCSDSLOTNO); + return -ENODEV; + } + + /* Now bind the SDIO interface to the MMC/SD driver */ + + ret = mmcsd_slotinitialize(CONFIG_NSH_MMCSDMINOR, g_sdio); + if (ret != OK) + { + syslog(LOG_ERR, + "ERROR: Failed to bind SDIO to the MMC/SD driver: %d\n", + ret); + return ret; + } + + /* Then let's guess and say that there is a card in the slot. There is no + * card detect GPIO. + */ + + sdio_mediachange(g_sdio, true); + + syslog(LOG_INFO, "[boot] Initialized SDIO\n"); +#endif + +#ifdef CONFIG_ADC + /* Initialize ADC and register the ADC driver. */ + + ret = stm32_adc_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_adc_setup failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_SENSORS_QENCODER + /* Initialize and register the qencoder driver */ + + ret = board_qencoder_initialize(0, CONFIG_NUCLEO_F411RE_QETIMER); + if (ret != OK) + { + syslog(LOG_ERR, + "ERROR: Failed to register the qencoder: %d\n", + ret); + return ret; + } +#endif + +#ifdef CONFIG_INPUT_AJOYSTICK + /* Initialize and register the joystick driver */ + + ret = board_ajoy_initialize(); + if (ret != OK) + { + syslog(LOG_ERR, + "ERROR: Failed to register the joystick driver: %d\n", + ret); + return ret; + } +#endif + + return ret; +} diff --git a/boards/arm/stm32f4/nucleo-f411re/src/stm32_buttons.c b/boards/arm/stm32f4/nucleo-f411re/src/stm32_buttons.c new file mode 100644 index 0000000000000..25f46f0715463 --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f411re/src/stm32_buttons.c @@ -0,0 +1,117 @@ +/**************************************************************************** + * boards/arm/stm32f4/nucleo-f411re/src/stm32_buttons.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include + +#include "stm32_gpio.h" +#include "nucleo-f411re.h" + +#include + +#ifdef CONFIG_ARCH_BUTTONS + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_button_initialize + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. + * + ****************************************************************************/ + +uint32_t board_button_initialize(void) +{ + /* Configure the single button as an input. NOTE that EXTI interrupts are + * also configured for the pin. + */ + + stm32_configgpio(GPIO_BTN_USER); + return NUM_BUTTONS; +} + +/**************************************************************************** + * Name: board_buttons + ****************************************************************************/ + +uint32_t board_buttons(void) +{ + /* Check that state of each USER button. A LOW value means that the key is + * pressed. + */ + + bool released = stm32_gpioread(GPIO_BTN_USER); + return !released; +} + +/**************************************************************************** + * Button support. + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. + * + * After board_button_initialize() has been called, board_buttons() may be + * called to collect the state of all buttons. board_buttons() returns an + * 32-bit bit set with each bit associated with a button. See the + * BUTTON_*_BIT definitions in board.h for the meaning of each bit. + * + * board_button_irq() may be called to register an interrupt handler that + * will be called when a button is depressed or released. The ID value is a + * button enumeration value that uniquely identifies a button resource. See + * the BUTTON_* definitions in board.h for the meaning of enumeration + * value. + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_IRQBUTTONS +int board_button_irq(int id, xcpt_t irqhandler, void *arg) +{ + int ret = -EINVAL; + + if (id == BUTTON_USER) + { + ret = stm32_gpiosetevent(GPIO_BTN_USER, true, true, true, + irqhandler, arg); + } + + return ret; +} +#endif +#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/stm32f4/nucleo-f411re/src/stm32_lcd_ssd1306.c b/boards/arm/stm32f4/nucleo-f411re/src/stm32_lcd_ssd1306.c new file mode 100644 index 0000000000000..1fda9fe85e2dc --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f411re/src/stm32_lcd_ssd1306.c @@ -0,0 +1,88 @@ +/**************************************************************************** + * boards/arm/stm32f4/nucleo-f411re/src/stm32_lcd_ssd1306.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include +#include +#include + +#include "stm32.h" +#include "nucleo-f411re.h" + +#include "stm32_ssd1306.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define OLED_SPI_PORT 1 /* OLED display connected to SPI1 */ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_lcd_initialize + ****************************************************************************/ + +int board_lcd_initialize(void) +{ + int ret; + + ret = board_ssd1306_initialize(OLED_SPI_PORT); + if (ret < 0) + { + lcderr("ERROR: Failed to initialize SSD1306\n"); + return ret; + } + + return OK; +} + +/**************************************************************************** + * Name: board_lcd_getdev + ****************************************************************************/ + +struct lcd_dev_s *board_lcd_getdev(int devno) +{ + return board_ssd1306_getdev(); +} + +/**************************************************************************** + * Name: board_lcd_uninitialize + ****************************************************************************/ + +void board_lcd_uninitialize(void) +{ + /* TO-FIX */ +} diff --git a/boards/arm/stm32f4/nucleo-f411re/src/stm32_mcp2515.c b/boards/arm/stm32f4/nucleo-f411re/src/stm32_mcp2515.c new file mode 100644 index 0000000000000..3b5cf927c8d3e --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f411re/src/stm32_mcp2515.c @@ -0,0 +1,241 @@ +/**************************************************************************** + * boards/arm/stm32f4/nucleo-f411re/src/stm32_mcp2515.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "stm32.h" +#include "stm32_spi.h" +#include "nucleo-f411re.h" + +#if defined(CONFIG_SPI) && defined(CONFIG_STM32_SPI1) && \ + defined(CONFIG_CAN_MCP2515) + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define MCP2515_SPI_PORTNO 1 /* On SPI1 */ + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +struct stm32_mcp2515config_s +{ + /* Configuration structure as seen by the MCP2515 driver */ + + struct mcp2515_config_s config; + + /* Additional private definitions only known to this driver */ + + struct mcp2515_can_s *handle; /* The MCP2515 driver handle */ + mcp2515_handler_t handler; /* The MCP2515 interrupt handler */ + void *arg; /* Argument to pass to the interrupt handler */ +}; + +/**************************************************************************** + * Static Function Prototypes + ****************************************************************************/ + +/* IRQ/GPIO access callbacks. These operations all hidden behind callbacks + * to isolate the MCP2515 driver from differences in GPIO interrupt handling + * by varying boards and MCUs. + * + * attach - Attach the MCP2515 interrupt handler to the GPIO interrupt + */ + +static int mcp2515_attach(struct mcp2515_config_s *state, + mcp2515_handler_t handler, void *arg); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* A reference to a structure of this type must be passed to the MCP2515 + * driver. This structure provides information about the configuration + * of the MCP2515 and provides some board-specific hooks. + * + * Memory for this structure is provided by the caller. It is not copied + * by the driver and is presumed to persist while the driver is active. The + * memory must be writable because, under certain circumstances, the driver + * may modify frequency or X plate resistance values. + */ + +static struct stm32_mcp2515config_s g_mcp2515config = +{ + .config = + { + .spi = NULL, + .baud = 0, /* REVISIT. Probably broken by commit eb7373cedfa */ + .btp = 0, /* REVISIT. Probably broken by commit eb7373cedfa */ + .devid = 0, + .mode = 0, /* REVISIT. Probably broken by commit eb7373cedfa */ + .nfilters = 6, +#ifdef MCP2515_LOOPBACK + .loopback = false; +#endif + .attach = mcp2515_attach, + }, +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/* This is the MCP2515 Interrupt handler */ + +int mcp2515_interrupt(int irq, void *context, void *arg) +{ + struct stm32_mcp2515config_s *priv = + (struct stm32_mcp2515config_s *)arg; + + DEBUGASSERT(priv != NULL); + + /* Verify that we have a handler attached */ + + if (priv->handler) + { + /* Yes.. forward with interrupt along with its argument */ + + priv->handler(&priv->config, priv->arg); + } + + return OK; +} + +static int mcp2515_attach(struct mcp2515_config_s *state, + mcp2515_handler_t handler, void *arg) +{ + struct stm32_mcp2515config_s *priv = + (struct stm32_mcp2515config_s *)state; + irqstate_t flags; + + caninfo("Saving handler %p\n", handler); + + flags = enter_critical_section(); + + priv->handler = handler; + priv->arg = arg; + + /* Configure the interrupt for falling edge */ + + stm32_gpiosetevent(GPIO_MCP2515_IRQ, false, true, false, + mcp2515_interrupt, priv); + + leave_critical_section(flags); + + return OK; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_mcp2515initialize + * + * Description: + * Initialize and register the MCP2515 RFID driver. + * + * Input Parameters: + * devpath - The full path to the driver to register. E.g., "/dev/rfid0" + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +int stm32_mcp2515initialize(const char *devpath) +{ + struct spi_dev_s *spi; + struct can_dev_s *can; + struct mcp2515_can_s *mcp2515; + int ret; + + /* Check if we are already initialized */ + + if (!g_mcp2515config.handle) + { + sninfo("Initializing\n"); + + /* Configure the MCP2515 interrupt pin as an input */ + + stm32_configgpio(GPIO_MCP2515_IRQ); + + spi = stm32_spibus_initialize(MCP2515_SPI_PORTNO); + + if (!spi) + { + return -ENODEV; + } + + /* Save the SPI instance in the mcp2515_config_s structure */ + + g_mcp2515config.config.spi = spi; + + /* Instantiate the MCP2515 CAN Driver */ + + mcp2515 = mcp2515_instantiate(&g_mcp2515config.config); + if (mcp2515 == NULL) + { + canerr("ERROR: Failed to get MCP2515 Driver Loaded\n"); + return -ENODEV; + } + + /* Save the opaque structure */ + + g_mcp2515config.handle = mcp2515; + + /* Initialize the CAN Device with the MCP2515 operations */ + + can = mcp2515_initialize(mcp2515); + if (can == NULL) + { + canerr("ERROR: Failed to get CAN interface\n"); + return -ENODEV; + } + + /* Register the CAN driver at "/dev/can0" */ + + ret = can_register(devpath, can); + if (ret < 0) + { + canerr("ERROR: can_register failed: %d\n", ret); + return ret; + } + } + + return OK; +} + +#endif /* CONFIG_SPI && CONFIG_CAN_MCP2515 */ diff --git a/boards/arm/stm32f4/nucleo-f411re/src/stm32_spi.c b/boards/arm/stm32f4/nucleo-f411re/src/stm32_spi.c new file mode 100644 index 0000000000000..69a16d88c7f37 --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f411re/src/stm32_spi.c @@ -0,0 +1,246 @@ +/**************************************************************************** + * boards/arm/stm32f4/nucleo-f411re/src/stm32_spi.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include + +#include "arm_internal.h" +#include "chip.h" +#include "stm32.h" + +#include "nucleo-f411re.h" + +#include + +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || \ + defined(CONFIG_STM32_SPI3) + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/* Global driver instances */ + +#ifdef CONFIG_STM32_SPI1 +struct spi_dev_s *g_spi1; +#endif +#ifdef CONFIG_STM32_SPI2 +struct spi_dev_s *g_spi2; +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_spidev_initialize + * + * Description: + * Called to configure SPI chip select GPIO pins for the Nucleo-F411RE + * + ****************************************************************************/ + +void weak_function stm32_spidev_initialize(void) +{ +#ifdef CONFIG_STM32_SPI1 + /* Configure SPI-based devices */ + + g_spi1 = stm32_spibus_initialize(1); + if (!g_spi1) + { + spierr("ERROR: FAILED to initialize SPI port 1\n"); + } + +#ifdef CONFIG_LCD_SSD1306_SPI + stm32_configgpio(GPIO_SSD1306_CS); /* SSD1306 chip select */ + stm32_configgpio(GPIO_SSD1306_CMD); /* SSD1306 data/!command */ +#endif + +#ifdef CONFIG_CAN_MCP2515 + stm32_configgpio(GPIO_MCP2515_CS); /* MCP2515 chip select */ +#endif + +#ifdef HAVE_MMCSD + stm32_configgpio(GPIO_SPI_CS_SD_CARD); +#endif +#endif + +#ifdef CONFIG_STM32_SPI2 + /* Configure SPI-based devices */ + + g_spi2 = stm32_spibus_initialize(2); +#endif +} + +/**************************************************************************** + * Name: stm32_spi1/2/3select and stm32_spi1/2/3status + * + * Description: + * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status + * must be provided by board-specific logic. They are implementations of + * the select and status methods of the SPI interface defined by struct + * spi_ops_s (see include/nuttx/spi/spi.h). All other methods (including + * stm32_spibus_initialize()) are provided by common STM32 logic. To use + * this common SPI logic on your board: + * + * 1. Provide logic in stm32_boardinitialize() to configure SPI chip select + * pins. + * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() functions + * in your board-specific logic. These functions will perform chip + * selection and status operations using GPIOs in the way your board is + * configured. + * 3. Add a calls to stm32_spibus_initialize() in your low level + * application initialization logic + * 4. The handle returned by stm32_spibus_initialize() may then be used to + * bind the SPI driver to higher level logic (e.g., calling + * mmcsd_spislotinitialize(), for example, will bind the SPI driver to + * the SPI MMC/SD driver). + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_SPI1 +void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, + bool selected) +{ + spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : + "de-assert"); + +#if defined(CONFIG_LCD_SSD1306_SPI) + if (devid == SPIDEV_DISPLAY(0)) + { + stm32_gpiowrite(GPIO_SSD1306_CS, !selected); + } +#endif + +#if defined(CONFIG_CAN_MCP2515) + if (devid == SPIDEV_CANBUS(0)) + { + stm32_gpiowrite(GPIO_MCP2515_CS, !selected); + } +#endif + +#ifdef HAVE_MMCSD + if (devid == SPIDEV_MMCSD(0)) + { + stm32_gpiowrite(GPIO_SPI_CS_SD_CARD, !selected); + } +#endif +} + +uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} +#endif + +#ifdef CONFIG_STM32_SPI2 +void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid, + bool selected) +{ + spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : + "de-assert"); +} + +uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} +#endif + +#ifdef CONFIG_STM32_SPI3 +void stm32_spi3select(struct spi_dev_s *dev, uint32_t devid, + bool selected) +{ + spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : + "de-assert"); +} + +uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} +#endif + +/**************************************************************************** + * Name: stm32_spi1cmddata + * + * Description: + * Set or clear the SH1101A A0 or SD1306 D/C n bit to select data (true) + * or command (false). This function must be provided by platform-specific + * logic. This is an implementation of the cmddata method of the SPI + * interface defined by struct spi_ops_s (see include/nuttx/spi/spi.h). + * + * Input Parameters: + * + * spi - SPI device that controls the bus the device that requires the CMD/ + * DATA selection. + * devid - If there are multiple devices on the bus, this selects which one + * to select cmd or data. NOTE: This design restricts, for example, + * one one SPI display per SPI bus. + * cmd - true: select command; false: select data + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_SPI_CMDDATA +#ifdef CONFIG_STM32_SPI1 +int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) +{ +#if defined(CONFIG_LCD_SSD1306_SPI) + if (devid == SPIDEV_DISPLAY(0)) + { + stm32_gpiowrite(GPIO_SSD1306_CMD, !cmd); + } +#endif + + return OK; +} +#endif + +#ifdef CONFIG_STM32_SPI2 +int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) +{ + return OK; +} +#endif + +#ifdef CONFIG_STM32_SPI3 +int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) +{ + return OK; +} +#endif +#endif /* CONFIG_SPI_CMDDATA */ + +#endif /* CONFIG_STM32_SPI1 || CONFIG_STM32_SPI2 || CONFIG_STM32_SPI3 */ diff --git a/boards/arm/stm32f4/nucleo-f411re/src/stm32_userleds.c b/boards/arm/stm32f4/nucleo-f411re/src/stm32_userleds.c new file mode 100644 index 0000000000000..0cb15012e4ed0 --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f411re/src/stm32_userleds.c @@ -0,0 +1,218 @@ +/**************************************************************************** + * boards/arm/stm32f4/nucleo-f411re/src/stm32_userleds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32.h" +#include "nucleo-f411re.h" + +#include + +#ifndef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/* LED Power Management */ + +#ifdef CONFIG_PM +static void led_pm_notify(struct pm_callback_s *cb, int domain, + enum pm_state_e pmstate); +static int led_pm_prepare(struct pm_callback_s *cb, int domain, + enum pm_state_e pmstate); +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#ifdef CONFIG_PM +static struct pm_callback_s g_ledscb = +{ + .notify = led_pm_notify, + .prepare = led_pm_prepare, +}; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: led_pm_notify + * + * Description: + * Notify the driver of new power state. This callback is called after + * all drivers have had the opportunity to prepare for the new power state. + * + ****************************************************************************/ + +#ifdef CONFIG_PM +static void led_pm_notify(struct pm_callback_s *cb, int domain, + enum pm_state_e pmstate) +{ + switch (pmstate) + { + case PM_NORMAL: + { + /* Restore normal LEDs operation */ + } + break; + + case PM_IDLE: + { + /* Entering IDLE mode - Turn leds off */ + } + break; + + case PM_STANDBY: + { + /* Entering STANDBY mode - Logic for PM_STANDBY goes here */ + } + break; + + case PM_SLEEP: + { + /* Entering SLEEP mode - Logic for PM_SLEEP goes here */ + } + break; + + default: + { + /* Should not get here */ + } + break; + } +} +#endif + +/**************************************************************************** + * Name: led_pm_prepare + * + * Description: + * Request the driver to prepare for a new power state. This is a warning + * that the system is about to enter into a new power state. The driver + * should begin whatever operations that may be required to enter power + * state. The driver may abort the state change mode by returning a + * non-zero value from the callback function. + * + ****************************************************************************/ + +#ifdef CONFIG_PM +static int led_pm_prepare(struct pm_callback_s *cb, int domain, + enum pm_state_e pmstate) +{ + /* No preparation to change power modes is required by the LEDs driver. + * We always accept the state change by returning OK. + */ + + return OK; +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_userled_initialize + ****************************************************************************/ + +uint32_t board_userled_initialize(void) +{ + /* Configure LD2 GPIO for output */ + + stm32_configgpio(GPIO_LD2); + return BOARD_NLEDS; +} + +/**************************************************************************** + * Name: board_userled + ****************************************************************************/ + +void board_userled(int led, bool ledon) +{ + if (BOARD_LD2_BIT == (1 << led)) + { + stm32_gpiowrite(GPIO_LD2, ledon); + } +} + +/**************************************************************************** + * Name: board_userled_all + ****************************************************************************/ + +void board_userled_all(uint32_t ledset) +{ + /* An output of '1' illuminates the LED */ + + stm32_gpiowrite(GPIO_LD2, (ledset & BOARD_LD2_BIT) != 0); +} + +#ifdef CONFIG_USERLED_LOWER_READSTATE +/**************************************************************************** + * Name: board_userled_getall + ****************************************************************************/ + +void board_userled_getall(uint32_t *ledset) +{ + /* Clear the LED bits */ + + *ledset = 0; + + /* Get LED state. An output of '1' illuminates the LED. */ + + *ledset |= ((stm32_gpioread(GPIO_LD2) & 1) << BOARD_LD2); +} + +#endif /* CONFIG_USERLED_LOWER_READSTATE */ + +/**************************************************************************** + * Name: stm32_led_pminitialize + ****************************************************************************/ + +#ifdef CONFIG_PM +void stm32_led_pminitialize(void) +{ + /* Register to receive power management callbacks */ + + int ret = pm_register(&g_ledscb); + DEBUGASSERT(ret == OK); + UNUSED(ret); +} +#endif /* CONFIG_PM */ + +#endif /* !CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32f4/nucleo-f412zg/CMakeLists.txt b/boards/arm/stm32f4/nucleo-f412zg/CMakeLists.txt new file mode 100644 index 0000000000000..78c8c99ff2578 --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f412zg/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32f4/nucleo-f412zg/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/arm/stm32/nucleo-f412zg/Kconfig b/boards/arm/stm32f4/nucleo-f412zg/Kconfig similarity index 100% rename from boards/arm/stm32/nucleo-f412zg/Kconfig rename to boards/arm/stm32f4/nucleo-f412zg/Kconfig diff --git a/boards/arm/stm32f4/nucleo-f412zg/configs/coremark/defconfig b/boards/arm/stm32f4/nucleo-f412zg/configs/coremark/defconfig new file mode 100644 index 0000000000000..4f4f921618ca3 --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f412zg/configs/coremark/defconfig @@ -0,0 +1,52 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_DISABLE_OS_API is not set +# CONFIG_STM32_SYSCFG is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nucleo-f412zg" +CONFIG_ARCH_BOARD_NUCLEO_F412ZG=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F412ZG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_SIZET_LONG=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BENCHMARK_COREMARK=y +CONFIG_BOARDCTL=y +CONFIG_BOARDCTL_MKRD=y +CONFIG_BOARD_LOOPSPERMSEC=8499 +CONFIG_BUILTIN=y +CONFIG_DEBUG_CUSTOMOPT=y +CONFIG_DEBUG_HARDFAULT_ALERT=y +CONFIG_DEBUG_OPTLEVEL="-O3" +CONFIG_INIT_ENTRYPOINT="coremark_main" +CONFIG_INIT_STACKSIZE=4096 +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_PREALLOC_CHILDSTATUS=2 +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=262144 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_SCHED_CHILD_STATUS=y +CONFIG_SCHED_HAVE_PARENT=y +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=30 +CONFIG_START_MONTH=11 +CONFIG_START_YEAR=2019 +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_FLASH_PREFETCH=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_SERIAL_DISABLE_REORDERING=y +CONFIG_STM32_USART3=y +CONFIG_SYSTEM_READLINE=y +CONFIG_TASK_NAME_SIZE=32 +CONFIG_USART3_SERIAL_CONSOLE=y +CONFIG_USEC_PER_TICK=1000 diff --git a/boards/arm/stm32f4/nucleo-f412zg/configs/nsh/defconfig b/boards/arm/stm32f4/nucleo-f412zg/configs/nsh/defconfig new file mode 100644 index 0000000000000..ece24fb0b1a7d --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f412zg/configs/nsh/defconfig @@ -0,0 +1,60 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_DISABLE_OS_API is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_STM32_SYSCFG is not set +CONFIG_ADC=y +CONFIG_ANALOG=y +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nucleo-f412zg" +CONFIG_ARCH_BOARD_NUCLEO_F412ZG=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F412ZG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_SIZET_LONG=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=8499 +CONFIG_BUILTIN=y +CONFIG_CAN=y +CONFIG_DEBUG_HARDFAULT_ALERT=y +CONFIG_HAVE_CXX=y +CONFIG_I2C=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_CHILDSTATUS=2 +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=262144 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_SCHED_CHILD_STATUS=y +CONFIG_SCHED_HAVE_PARENT=y +CONFIG_SCHED_WAITPID=y +CONFIG_SPI=y +CONFIG_START_DAY=30 +CONFIG_START_MONTH=11 +CONFIG_START_YEAR=2019 +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_FLASH_PREFETCH=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_SERIAL_DISABLE_REORDERING=y +CONFIG_STM32_USART3=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=32 +CONFIG_TIMER=y +CONFIG_USART3_SERIAL_CONSOLE=y +CONFIG_USEC_PER_TICK=1000 diff --git a/boards/arm/stm32f4/nucleo-f412zg/configs/ostest/defconfig b/boards/arm/stm32f4/nucleo-f412zg/configs/ostest/defconfig new file mode 100644 index 0000000000000..e6c03ecfce8b5 --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f412zg/configs/ostest/defconfig @@ -0,0 +1,61 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_DISABLE_OS_API is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_STM32_SYSCFG is not set +CONFIG_ADC=y +CONFIG_ANALOG=y +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nucleo-f412zg" +CONFIG_ARCH_BOARD_NUCLEO_F412ZG=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F412ZG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_SIZET_LONG=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=8499 +CONFIG_BUILTIN=y +CONFIG_CAN=y +CONFIG_DEBUG_HARDFAULT_ALERT=y +CONFIG_HAVE_CXX=y +CONFIG_I2C=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_CHILDSTATUS=2 +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=262144 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_SCHED_CHILD_STATUS=y +CONFIG_SCHED_HAVE_PARENT=y +CONFIG_SCHED_WAITPID=y +CONFIG_SPI=y +CONFIG_START_DAY=30 +CONFIG_START_MONTH=11 +CONFIG_START_YEAR=2019 +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_FLASH_PREFETCH=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_SERIAL_DISABLE_REORDERING=y +CONFIG_STM32_USART3=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=32 +CONFIG_TESTING_OSTEST=y +CONFIG_TIMER=y +CONFIG_USART3_SERIAL_CONSOLE=y +CONFIG_USEC_PER_TICK=1000 diff --git a/boards/arm/stm32f4/nucleo-f412zg/include/board.h b/boards/arm/stm32f4/nucleo-f412zg/include/board.h new file mode 100644 index 0000000000000..35a7fa13dd5b1 --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f412zg/include/board.h @@ -0,0 +1,228 @@ +/**************************************************************************** + * boards/arm/stm32f4/nucleo-f412zg/include/board.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_STM32_NUCLEO_F412ZG_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32_NUCLEO_F412ZG_INCLUDE_BOARD_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#ifndef __ASSEMBLY__ +# include +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* HSI - 16 MHz RC factory-trimmed + * LSI - 32 KHz RC + * HSE - 8 MHz Crystal + * LSE - not installed + */ + +#define STM32_BOARD_USEHSE 1 +#define STM32_BOARD_XTAL 8000000 +#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL + +#define STM32_HSI_FREQUENCY 16000000ul +#define STM32_LSI_FREQUENCY 32000 + +/* Main PLL Configuration */ + +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(8) +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(384) +#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_4 +#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(8) +#define STM32_PLLCFG_PLLR RCC_PLLCFG_PLLR(2) + +#define STM32_RCC_PLLI2SCFGR_PLLI2SM RCC_PLLI2SCFGR_PLLI2SM(16) +#define STM32_RCC_PLLI2SCFGR_PLLI2SN RCC_PLLI2SCFGR_PLLI2SN(192) +#define STM32_RCC_PLLI2SCFGR_PLLI2SQ RCC_PLLI2SCFGR_PLLI2SQ(2) +#define STM32_RCC_PLLI2SCFGR_PLLI2SR RCC_PLLI2SCFGR_PLLI2SR(2) +#define STM32_RCC_PLLI2SCFGR_PLLI2SSRC RCC_PLLI2SCFGR_PLLI2SSRC(0) /* HSE or HSI depending on PLLSRC of PLLCFGR*/ + +#define STM32_RCC_DCKCFGR2_CK48MSEL RCC_DCKCFGR2_CK48MSEL_PLL +#define STM32_RCC_DCKCFGR2_FMPI2C1SEL RCC_DCKCFGR2_FMPI2C1SEL_APB +#define STM32_RCC_DCKCFGR2_SDIOSEL RCC_DCKCFGR2_SDIOSEL_48MHZ + +#define STM32_SYSCLK_FREQUENCY 96000000ul + +/* AHB clock (HCLK) is SYSCLK (96MHz) */ + +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY + +/* APB1 clock (PCLK1) is HCLK/2 (48MHz) */ + +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd2 /* PCLK1 = HCLK / 2 */ +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/2) + +/* Timers driven from APB1 will be twice PCLK1 */ + +#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) + +/* APB2 clock (PCLK2) is HCLK (96MHz) */ + +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK */ +#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY) + +/* Timers driven from APB2 will be PCLK2 since no prescale division */ + +#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM9_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM10_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM11_CLKIN (STM32_PCLK2_FREQUENCY) + +/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx + * otherwise frequency is 2xAPBx. + * Note: TIM1,8 are on APB2, others on APB1 + */ + +#define BOARD_TIM2_FREQUENCY (2 * STM32_PCLK1_FREQUENCY) +#define BOARD_TIM3_FREQUENCY (2 * STM32_PCLK1_FREQUENCY) +#define BOARD_TIM4_FREQUENCY (2 * STM32_PCLK1_FREQUENCY) +#define BOARD_TIM5_FREQUENCY (2 * STM32_PCLK1_FREQUENCY) +#define BOARD_TIM6_FREQUENCY (2 * STM32_PCLK1_FREQUENCY) +#define BOARD_TIM7_FREQUENCY (2 * STM32_PCLK1_FREQUENCY) +#define BOARD_TIM8_FREQUENCY (2 * STM32_PCLK2_FREQUENCY) + +/* Alternate function pin selections ****************************************/ + +/* USART2: + * RXD: PD6 CN9 pin 4 + * TXD: PD5 CN9 pin 6 + */ + +# define GPIO_USART2_RX (GPIO_USART2_RX_2|GPIO_SPEED_100MHz) +# define GPIO_USART2_TX (GPIO_USART2_TX_2|GPIO_SPEED_100MHz) + +/* USART3 (ST-LINK Virtual COM Port): + * RXD: PD9 + * TXD: PD8 + */ + +# define GPIO_USART3_RX (GPIO_USART3_RX_3|GPIO_SPEED_100MHz) +# define GPIO_USART3_TX (GPIO_USART3_TX_3|GPIO_SPEED_100MHz) + +/* USART6: + * RXD: PG9 CN10 pin 16 + * TXD: PG14 CN10 pin 14 + */ + +#define GPIO_USART6_RX (GPIO_USART6_RX_2|GPIO_SPEED_100MHz) +#define GPIO_USART6_TX (GPIO_USART6_TX_2|GPIO_SPEED_100MHz) + +/* I2C1: + * SCL: PB8 CN7 pin2 + * SDA: PB9 CN7 pin4 + */ + +#define GPIO_I2C1_SCL (GPIO_I2C1_SCL_2|GPIO_SPEED_50MHz) +#define GPIO_I2C1_SDA (GPIO_I2C1_SDA_2|GPIO_SPEED_50MHz) + +#define GPIO_I2C1_SCL_GPIO \ + (GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTB|GPIO_PIN8) +#define GPIO_I2C1_SDA_GPIO \ + (GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTB|GPIO_PIN9) + +/* SPI1: + * MISO: PA6 CN7 pin 12 + * MOSI: PA7 CN7 pin 14 + * SCK: PA5 CN7 pin 10 + */ + +#define GPIO_SPI1_MISO (GPIO_SPI1_MISO_1|GPIO_SPEED_50MHz) +#define GPIO_SPI1_MOSI (GPIO_SPI1_MOSI_1|GPIO_SPEED_50MHz) +#define GPIO_SPI1_SCK (GPIO_SPI1_SCK_1|GPIO_SPEED_50MHz) + +/* CAN1: + * RX: PD0 CN9 pin 25 + * TX: PD1 CN9 pin 27 + */ + +#define GPIO_CAN1_RX (GPIO_CAN1_RX_3|GPIO_SPEED_50MHz) +#define GPIO_CAN1_TX (GPIO_CAN1_TX_3|GPIO_SPEED_50MHz) + +/* LEDs + * + * The NUCLEO-F412ZG board has 3 user leds. + * LD1: PB0 GREEN + * LD2: PB7 BLUE + * LD3: PB14 RED + */ + +#define BOARD_NLEDS 3 + +#define GPIO_LD1 \ +(GPIO_PORTB | GPIO_PIN0 | GPIO_OUTPUT_CLEAR | GPIO_OUTPUT | GPIO_PULLUP | \ +GPIO_SPEED_50MHz) + +#define GPIO_LD2 \ +(GPIO_PORTB | GPIO_PIN7 | GPIO_OUTPUT_CLEAR | GPIO_OUTPUT | GPIO_PULLUP | \ +GPIO_SPEED_50MHz) + +#define GPIO_LD3 \ +(GPIO_PORTB | GPIO_PIN14 | GPIO_OUTPUT_CLEAR | GPIO_OUTPUT | GPIO_PULLUP | \ +GPIO_SPEED_50MHz) + +/* These LEDs are not used by the board port unless CONFIG_ARCH_LEDS is + * defined. In that case, the usage by the board port is defined in + * include/board.h and src/sam_leds.c. The LEDs are used to encode OS-related + * events as follows when the red LED (PE24) is available: + * + * SYMBOL Meaning + * ------------------- ----------------------- + * LED_STARTED NuttX has been started + * LED_HEAPALLOCATE Heap has been allocated + * LED_IRQSENABLED Interrupts enabled + * LED_STACKCREATED Idle stack created + * LED_INIRQ In an interrupt + * LED_SIGNAL In a signal handler + * LED_ASSERTION An assertion failed + * LED_PANIC The system has crashed + * LED_IDLE MCU is in sleep mode + * + * Thus if LD2, NuttX has successfully booted and is, apparently, running + * normally. If LD2 is flashing at approximately 2Hz, then a fatal error + * has been detected and the system has halted. + */ + +#define LED_STARTED 1 +#define LED_HEAPALLOCATE 0 +#define LED_IRQSENABLED 0 +#define LED_STACKCREATED 3 +#define LED_INIRQ 0 +#define LED_SIGNAL 0 +#define LED_ASSERTION 1 +#define LED_PANIC 1 + +#endif /* __BOARDS_ARM_STM32_NUCLEO_F412ZG_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32f4/nucleo-f412zg/scripts/Make.defs b/boards/arm/stm32f4/nucleo-f412zg/scripts/Make.defs new file mode 100644 index 0000000000000..7bd8f7113fd08 --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f412zg/scripts/Make.defs @@ -0,0 +1,42 @@ +############################################################################ +# boards/arm/stm32f4/nucleo-f412zg/scripts/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include ${TOPDIR}/.config +include ${TOPDIR}/tools/Config.mk +include ${TOPDIR}/arch/arm/src/armv7-m/Toolchain.defs + +LDSCRIPT = f412zg.ld +ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) + +ARCHDEFINES = +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32/nucleo-f412zg/scripts/f412zg.ld b/boards/arm/stm32f4/nucleo-f412zg/scripts/f412zg.ld similarity index 98% rename from boards/arm/stm32/nucleo-f412zg/scripts/f412zg.ld rename to boards/arm/stm32f4/nucleo-f412zg/scripts/f412zg.ld index 0c66b0979e5a4..d89c019092523 100644 --- a/boards/arm/stm32/nucleo-f412zg/scripts/f412zg.ld +++ b/boards/arm/stm32f4/nucleo-f412zg/scripts/f412zg.ld @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f412zg/scripts/f412zg.ld + * boards/arm/stm32f4/nucleo-f412zg/scripts/f412zg.ld * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f4/nucleo-f412zg/src/CMakeLists.txt b/boards/arm/stm32f4/nucleo-f412zg/src/CMakeLists.txt new file mode 100644 index 0000000000000..48cd9e8753692 --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f412zg/src/CMakeLists.txt @@ -0,0 +1,35 @@ +# ############################################################################## +# boards/arm/stm32f4/nucleo-f412zg/src/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(SRCS stm32_boot.c stm32_bringup.c) + +if(CONFIG_ARCH_LEDS) + list(APPEND SRCS stm32_autoleds.c) +endif() + +if(CONFIG_STM32_OTGFS) + list(APPEND SRCS stm32_usb.c) +endif() + +target_sources(board PRIVATE ${SRCS}) + +set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/f412zg.ld") diff --git a/boards/arm/stm32f4/nucleo-f412zg/src/Make.defs b/boards/arm/stm32f4/nucleo-f412zg/src/Make.defs new file mode 100644 index 0000000000000..9c28d010d9304 --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f412zg/src/Make.defs @@ -0,0 +1,38 @@ +############################################################################ +# boards/arm/stm32f4/nucleo-f412zg/src/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +-include $(TOPDIR)/Make.defs + +ASRCS = +CSRCS = stm32_boot.c stm32_bringup.c + +ifeq ($(CONFIG_ARCH_LEDS),y) +CSRCS += stm32_autoleds.c +endif + +ifeq ($(CONFIG_STM32_OTGFS),y) +CSRCS += stm32_usb.c +endif + +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/nucleo-f412zg/src/nucleo-f412zg.h b/boards/arm/stm32f4/nucleo-f412zg/src/nucleo-f412zg.h similarity index 98% rename from boards/arm/stm32/nucleo-f412zg/src/nucleo-f412zg.h rename to boards/arm/stm32f4/nucleo-f412zg/src/nucleo-f412zg.h index e0a4726994c8d..203f5ce92737b 100644 --- a/boards/arm/stm32/nucleo-f412zg/src/nucleo-f412zg.h +++ b/boards/arm/stm32f4/nucleo-f412zg/src/nucleo-f412zg.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f412zg/src/nucleo-f412zg.h + * boards/arm/stm32f4/nucleo-f412zg/src/nucleo-f412zg.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f4/nucleo-f412zg/src/stm32_autoleds.c b/boards/arm/stm32f4/nucleo-f412zg/src/stm32_autoleds.c new file mode 100644 index 0000000000000..c9e7efe0a2481 --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f412zg/src/stm32_autoleds.c @@ -0,0 +1,104 @@ +/**************************************************************************** + * boards/arm/stm32f4/nucleo-f412zg/src/stm32_autoleds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32.h" +#include "nucleo-f412zg.h" + +#ifdef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_autoled_initialize + ****************************************************************************/ + +void board_autoled_initialize(void) +{ + stm32_configgpio(GPIO_LD1); + stm32_configgpio(GPIO_LD2); + stm32_configgpio(GPIO_LD3); +} + +/**************************************************************************** + * Name: board_autoled_on + ****************************************************************************/ + +void board_autoled_on(int led) +{ + switch (led) + { + case 1: + stm32_gpiowrite(GPIO_LD1, true); + break; + case 2: + stm32_gpiowrite(GPIO_LD1, true); + stm32_gpiowrite(GPIO_LD2, true); + break; + case 3: + stm32_gpiowrite(GPIO_LD1, true); + stm32_gpiowrite(GPIO_LD2, true); + stm32_gpiowrite(GPIO_LD3, true); + break; + } +} + +/**************************************************************************** + * Name: board_autoled_off + ****************************************************************************/ + +void board_autoled_off(int led) +{ + switch (led) + { + case 1: + stm32_gpiowrite(GPIO_LD1, false); + break; + case 2: + stm32_gpiowrite(GPIO_LD1, false); + stm32_gpiowrite(GPIO_LD2, false); + break; + case 3: + stm32_gpiowrite(GPIO_LD1, false); + stm32_gpiowrite(GPIO_LD2, false); + stm32_gpiowrite(GPIO_LD3, false); + break; + } +} + +#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32f4/nucleo-f412zg/src/stm32_boot.c b/boards/arm/stm32f4/nucleo-f412zg/src/stm32_boot.c new file mode 100644 index 0000000000000..407e508cc35d5 --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f412zg/src/stm32_boot.c @@ -0,0 +1,100 @@ +/**************************************************************************** + * boards/arm/stm32f4/nucleo-f412zg/src/stm32_boot.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include +#include + +#include + +#include "arm_internal.h" +#include "nucleo-f412zg.h" +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_boardinitialize + * + * Description: + * All STM32 architectures must provide the following entry point. This + * entry point is called early in the initialization -- after all memory + * has been configured and mapped but before any devices have been + * initialized. + * + ****************************************************************************/ + +void stm32_boardinitialize(void) +{ +#ifdef CONFIG_ARCH_LEDS + /* Configure on-board LEDs if LED support has been selected. */ + + board_autoled_initialize(); +#endif + +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || \ + defined(CONFIG_STM32_SPI3) + /* Configure SPI chip selects if 1) SP2 is not disabled, and 2) the + * weak function stm32_spidev_initialize() has been brought into the link. + */ + + stm32_spidev_initialize(); +#endif + +#ifdef CONFIG_STM32_OTGFS + /* Initialize USB if the OTG FS controller is in the configuration. + * Presumably either CONFIG_USBDEV or CONFIG_USBHOST is also selected. + */ + + stm32_usbinitialize(); +#endif +} + +/**************************************************************************** + * Name: board_late_initialize + * + * Description: + * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_late_initialize(). board_late_initialize() will + * be called immediately after up_initialize() is called and just before + * the initial application is started. This additional initialization + * phase may be used, for example, to initialize board-specific device + * drivers. + * + ****************************************************************************/ + +#ifdef CONFIG_BOARD_LATE_INITIALIZE +void board_late_initialize(void) +{ + /* Perform board-specific initialization */ + + stm32_bringup(); +} +#endif diff --git a/boards/arm/stm32f4/nucleo-f412zg/src/stm32_bringup.c b/boards/arm/stm32f4/nucleo-f412zg/src/stm32_bringup.c new file mode 100644 index 0000000000000..695de2977b5d4 --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f412zg/src/stm32_bringup.c @@ -0,0 +1,84 @@ +/**************************************************************************** + * boards/arm/stm32f4/nucleo-f412zg/src/stm32_bringup.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include + +#include "stm32.h" +#include "nucleo-f412zg.h" + +#ifdef CONFIG_STM32_OTGFS +# include "stm32_usbhost.h" +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_bringup + * + * Description: + * Perform architecture-specific initialization + * + * CONFIG_BOARD_LATE_INITIALIZE=y : + * Called from board_late_initialize(). + * + ****************************************************************************/ + +int stm32_bringup(void) +{ + int ret = OK; + +#if defined(CONFIG_STM32_OTGFS) && defined(CONFIG_USBHOST) + /* Initialize USB host operation. stm32_usbhost_initialize() starts a + * thread will monitor for USB connection and disconnection events. + */ + + ret = stm32_usbhost_initialize(); + if (ret != OK) + { + uerr("ERROR: Failed to initialize USB host: %d\n", ret); + return ret; + } +#endif + +#ifdef CONFIG_FS_PROCFS + /* Mount the procfs file system */ + + ret = nx_mount(NULL, STM32_PROCFS_MOUNTPOINT, "procfs", 0, NULL); + if (ret < 0) + { + ferr("ERROR: Failed to mount procfs at %s: %d\n", + STM32_PROCFS_MOUNTPOINT, ret); + } +#endif + + return ret; +} diff --git a/boards/arm/stm32f4/nucleo-f412zg/src/stm32_usb.c b/boards/arm/stm32f4/nucleo-f412zg/src/stm32_usb.c new file mode 100644 index 0000000000000..5359021bc9597 --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f412zg/src/stm32_usb.c @@ -0,0 +1,352 @@ +/**************************************************************************** + * boards/arm/stm32f4/nucleo-f412zg/src/stm32_usb.c + * + * SPDX-License-Identifier: BSD-3-Clause + * SPDX-FileCopyrightText: 2017 Gregory Nutt. All rights reserved. + * SPDX-FileCopyrightText: 2017 Brian Webb. All rights reserved. + * SPDX-FileContributor: Gregory Nutt + * SPDX-FileContributor: Brian Webb + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include "up_internal.h" +#include "stm32.h" +#include "stm32_otgfs.h" +#include "nucleo-f412zg.h" + +#ifdef CONFIG_STM32_OTGFS + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#if !defined(CONFIG_USBDEV) && !defined(CONFIG_USBHOST) +# warning "CONFIG_STM32_OTGFS is enabled but neither CONFIG_USBDEV nor CONFIG_USBHOST" +#endif + +#ifndef CONFIG_STM32F411DISCO_USBHOST_PRIO +# define CONFIG_STM32F411DISCO_USBHOST_PRIO 100 +#endif + +#ifndef CONFIG_STM32F411DISCO_USBHOST_STACKSIZE +# define CONFIG_STM32F411DISCO_USBHOST_STACKSIZE 1024 +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +static struct usbhost_connection_s *g_usbconn; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: usbhost_waiter + * + * Description: + * Wait for USB devices to be connected. + * + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +static int usbhost_waiter(int argc, char *argv[]) +{ + struct usbhost_hubport_s *hport; + + uinfo("Running\n"); + for (; ; ) + { + /* Wait for the device to change state */ + + DEBUGVERIFY(CONN_WAIT(g_usbconn, &hport)); + uinfo("%s\n", hport->connected ? "connected" : "disconnected"); + + /* Did we just become connected? */ + + if (hport->connected) + { + /* Yes.. enumerate the newly connected device */ + + CONN_ENUMERATE(g_usbconn, hport); + } + } + + /* Keep the compiler from complaining */ + + return 0; +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_usbinitialize + * + * Description: + * Called from stm32_usbinitialize very early in initialization to setup + * USB-related GPIO pins for the STM32F411 Discovery board. + * + ****************************************************************************/ + +void stm32_usbinitialize(void) +{ + /* The OTG FS has an internal soft pull-up. + * No GPIO configuration is required. + */ + + /* Configure the OTG FS VBUS sensing GPIO, + * Power On, and Overcurrent GPIOs. + */ + +#ifdef CONFIG_STM32_OTGFS + stm32_configgpio(GPIO_OTGFS_VBUS); + stm32_configgpio(GPIO_OTGFS_PWRON); + stm32_configgpio(GPIO_OTGFS_OVER); +#endif +} + +/**************************************************************************** + * Name: stm32_usbhost_initialize + * + * Description: + * Called at application startup time to initialize the USB host + * functionality. This function will start a thread that will monitor + * for device connection/disconnection events. + * + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +int stm32_usbhost_initialize(void) +{ + int ret; + + /* First, register all of the class drivers needed to support the drivers + * that we care about: + */ + + uinfo("Register class drivers\n"); + +#ifdef CONFIG_USBHOST_HUB + /* Initialize USB hub class support */ + + ret = usbhost_hub_initialize(); + if (ret < 0) + { + uerr("ERROR: usbhost_hub_initialize failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_USBHOST_MSC + /* Register the USB mass storage class class */ + + ret = usbhost_msc_initialize(); + if (ret != OK) + { + uerr("ERROR: Failed to register the mass storage class: %d\n", ret); + } +#endif + +#ifdef CONFIG_USBHOST_CDCACM + /* Register the CDC/ACM serial class */ + + ret = usbhost_cdcacm_initialize(); + if (ret != OK) + { + uerr("ERROR: Failed to register the CDC/ACM serial class: %d\n", ret); + } +#endif + +#ifdef CONFIG_USBHOST_HIDKBD + /* Initialize the HID keyboard class */ + + ret = usbhost_kbdinit(); + if (ret != OK) + { + uerr("ERROR: Failed to register the HID keyboard class\n"); + } +#endif + +#ifdef CONFIG_USBHOST_HIDMOUSE + /* Initialize the HID mouse class */ + + ret = usbhost_mouse_init(); + if (ret != OK) + { + uerr("ERROR: Failed to register the HID mouse class\n"); + } +#endif + +#ifdef CONFIG_USBHOST_XBOXCONTROLLER + /* Initialize the HID mouse class */ + + ret = usbhost_xboxcontroller_init(); + if (ret != OK) + { + uerr("ERROR: Failed to register the XBox Controller class\n"); + } +#endif + + /* Then get an instance of the USB host interface */ + + uinfo("Initialize USB host\n"); + g_usbconn = stm32_otgfshost_initialize(0); + if (g_usbconn) + { + /* Start a thread to handle device connection. */ + + uinfo("Start usbhost_waiter\n"); + + ret = kthread_create("usbhost", CONFIG_STM32F411DISCO_USBHOST_PRIO, + CONFIG_STM32F411DISCO_USBHOST_STACKSIZE, + usbhost_waiter, NULL); + return ret < 0 ? -ENOEXEC : OK; + } + + return -ENODEV; +} +#endif + +/**************************************************************************** + * Name: stm32_usbhost_vbusdrive + * + * Description: + * Enable/disable driving of VBUS 5V output. This function must be + * provided be each platform that implements the STM32 OTG FS host + * interface. + * + * "On-chip 5 V VBUS generation is not supported. For this reason, a charge + * pump or, if 5 V are available on the application board, a basic power + * switch, must be added externally to drive the 5 V VBUS line. The + * external charge pump can be driven by any GPIO output. When the + * application decides to power on VBUS using the chosen GPIO, it must + * also set the port power bit in the host port control and status + * register (PPWR bit in OTG_FS_HPRT). + * + * "The application uses this field to control power to this port, and + * the core clears this bit on an overcurrent condition." + * + * Input Parameters: + * iface - For future growth to handle multiple USB host interface. + * Should be zero. + * enable - true: enable VBUS power; false: disable VBUS power + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +void stm32_usbhost_vbusdrive(int iface, bool enable) +{ + DEBUGASSERT(iface == 0); + + if (enable) + { + /* Enable the Power Switch by driving the enable pin low */ + + stm32_gpiowrite(GPIO_OTGFS_PWRON, false); + } + else + { + /* Disable the Power Switch by driving the enable pin high */ + + stm32_gpiowrite(GPIO_OTGFS_PWRON, true); + } +} +#endif + +/**************************************************************************** + * Name: stm32_setup_overcurrent + * + * Description: + * Setup to receive an interrupt-level callback if an overcurrent condition + * is detected. + * + * Input Parameters: + * handler - New overcurrent interrupt handler + * arg - The argument provided for the interrupt handler + * + * Returned Value: + * Zero (OK) is returned on success. Otherwise, a negated errno value is + * returned to indicate the nature of the failure. + * + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +int stm32_setup_overcurrent(xcpt_t handler, void *arg) +{ + return stm32_gpiosetevent(GPIO_OTGFS_OVER, true, true, true, handler, arg); +} +#endif + +/**************************************************************************** + * Name: stm32_usbsuspend + * + * Description: + * Board logic must provide the stm32_usbsuspend logic if the USBDEV driver + * is used. This function is called whenever the USB enters or leaves + * suspend mode. This is an opportunity for the board logic to shutdown + * clocks, power, etc. while the USB is suspended. + * + ****************************************************************************/ + +#ifdef CONFIG_USBDEV +void stm32_usbsuspend(struct usbdev_s *dev, bool resume) +{ + uinfo("resume: %d\n", resume); +} +#endif + +#endif /* CONFIG_STM32_OTGFS */ diff --git a/boards/arm/stm32f4/nucleo-f429zi/CMakeLists.txt b/boards/arm/stm32f4/nucleo-f429zi/CMakeLists.txt new file mode 100644 index 0000000000000..cefebbf5e5096 --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f429zi/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32f4/nucleo-f429zi/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/arm/stm32/nucleo-f429zi/Kconfig b/boards/arm/stm32f4/nucleo-f429zi/Kconfig similarity index 100% rename from boards/arm/stm32/nucleo-f429zi/Kconfig rename to boards/arm/stm32f4/nucleo-f429zi/Kconfig diff --git a/boards/arm/stm32f4/nucleo-f429zi/configs/netnsh/defconfig b/boards/arm/stm32f4/nucleo-f429zi/configs/netnsh/defconfig new file mode 100644 index 0000000000000..d6a052fbd2a7f --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f429zi/configs/netnsh/defconfig @@ -0,0 +1,82 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_STM32_FLASH_PREFETCH is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nucleo-f429zi" +CONFIG_ARCH_BOARD_NUCLEO_F429ZI=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F429Z=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_ETH0_PHY_LAN8742A=y +CONFIG_FS_PROCFS=y +CONFIG_FS_PROCFS_REGISTER=y +CONFIG_FS_TMPFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_MM_REGIONS=2 +CONFIG_NET=y +CONFIG_NETDB_DNSCLIENT=y +CONFIG_NETINIT_DHCPC=y +CONFIG_NETINIT_NOMAC=y +CONFIG_NETUTILS_DISCOVER=y +CONFIG_NETUTILS_TELNETD=y +CONFIG_NETUTILS_WEBCLIENT=y +CONFIG_NET_ARP_IPIN=y +CONFIG_NET_BROADCAST=y +CONFIG_NET_ETH_PKTSIZE=1500 +CONFIG_NET_ICMP_SOCKET=y +CONFIG_NET_IGMP=y +CONFIG_NET_LOOPBACK=y +CONFIG_NET_ROUTE=y +CONFIG_NET_STATISTICS=y +CONFIG_NET_TCP=y +CONFIG_NET_UDP=y +CONFIG_NET_UDP_CHECKSUMS=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_NUCLEO_F429ZI_CONSOLE_VIRTUAL=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_LPWORK=y +CONFIG_SCHED_WAITPID=y +CONFIG_SPI=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_ETHMAC=y +CONFIG_STM32_FLASH_CONFIG_I=y +CONFIG_STM32_PHYADDR=0 +CONFIG_STM32_PHYSR=31 +CONFIG_STM32_PHYSR_100FD=0x0018 +CONFIG_STM32_PHYSR_100HD=0x0008 +CONFIG_STM32_PHYSR_10FD=0x0014 +CONFIG_STM32_PHYSR_10HD=0x0004 +CONFIG_STM32_PHYSR_ALTCONFIG=y +CONFIG_STM32_PHYSR_ALTMODE=0x001c +CONFIG_STM32_RMII_EXTCLK=y +CONFIG_SYSTEM_DHCPC_RENEW=y +CONFIG_SYSTEM_NSH=y +CONFIG_SYSTEM_PING=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART3_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f4/nucleo-f429zi/configs/nsh/defconfig b/boards/arm/stm32f4/nucleo-f429zi/configs/nsh/defconfig new file mode 100644 index 0000000000000..262b4becc718f --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f429zi/configs/nsh/defconfig @@ -0,0 +1,49 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_STM32_FLASH_PREFETCH is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nucleo-f429zi" +CONFIG_ARCH_BOARD_NUCLEO_F429ZI=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F429Z=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_MM_REGIONS=2 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_NUCLEO_F429ZI_CONSOLE_VIRTUAL=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_SPI=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_FLASH_CONFIG_I=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_PWR=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART3_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f4/nucleo-f429zi/configs/trace/defconfig b/boards/arm/stm32f4/nucleo-f429zi/configs/trace/defconfig new file mode 100644 index 0000000000000..a03f1d5e458d9 --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f429zi/configs/trace/defconfig @@ -0,0 +1,90 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_STM32_FLASH_PREFETCH is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nucleo-f429zi" +CONFIG_ARCH_BOARD_NUCLEO_F429ZI=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F429Z=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_DRIVERS_NOTE=y +CONFIG_DRIVERS_NOTECTL=y +CONFIG_ETH0_PHY_LAN8742A=y +CONFIG_FS_PROCFS=y +CONFIG_FS_PROCFS_REGISTER=y +CONFIG_FS_TMPFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_MM_REGIONS=2 +CONFIG_NET=y +CONFIG_NETDB_DNSCLIENT=y +CONFIG_NETINIT_DHCPC=y +CONFIG_NETINIT_NOMAC=y +CONFIG_NETUTILS_DISCOVER=y +CONFIG_NETUTILS_TELNETD=y +CONFIG_NETUTILS_WEBCLIENT=y +CONFIG_NET_ARP_IPIN=y +CONFIG_NET_BROADCAST=y +CONFIG_NET_ETH_PKTSIZE=1500 +CONFIG_NET_ICMP_SOCKET=y +CONFIG_NET_IGMP=y +CONFIG_NET_LOOPBACK=y +CONFIG_NET_ROUTE=y +CONFIG_NET_STATISTICS=y +CONFIG_NET_TCP=y +CONFIG_NET_UDP=y +CONFIG_NET_UDP_CHECKSUMS=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_NUCLEO_F429ZI_CONSOLE_VIRTUAL=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_INSTRUMENTATION=y +CONFIG_SCHED_INSTRUMENTATION_DUMP=y +CONFIG_SCHED_INSTRUMENTATION_FILTER=y +CONFIG_SCHED_LPWORK=y +CONFIG_SCHED_WAITPID=y +CONFIG_SPI=y +CONFIG_STACK_USAGE=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_ETHMAC=y +CONFIG_STM32_FLASH_CONFIG_I=y +CONFIG_STM32_PHYADDR=0 +CONFIG_STM32_PHYSR=31 +CONFIG_STM32_PHYSR_100FD=0x0018 +CONFIG_STM32_PHYSR_100HD=0x0008 +CONFIG_STM32_PHYSR_10FD=0x0014 +CONFIG_STM32_PHYSR_10HD=0x0004 +CONFIG_STM32_PHYSR_ALTCONFIG=y +CONFIG_STM32_PHYSR_ALTMODE=0x001c +CONFIG_STM32_RMII_EXTCLK=y +CONFIG_SYSTEM_DHCPC_RENEW=y +CONFIG_SYSTEM_NSH=y +CONFIG_SYSTEM_PING=y +CONFIG_SYSTEM_TRACE=y +CONFIG_SYSTEM_TRACE_STACKSIZE=8192 +CONFIG_TASK_NAME_SIZE=32 +CONFIG_USART3_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f4/nucleo-f429zi/include/board.h b/boards/arm/stm32f4/nucleo-f429zi/include/board.h new file mode 100644 index 0000000000000..4e259c13a929c --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f429zi/include/board.h @@ -0,0 +1,376 @@ +/**************************************************************************** + * boards/arm/stm32f4/nucleo-f429zi/include/board.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_STM32F4_NUCLEO_F429ZI_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32F4_NUCLEO_F429ZI_INCLUDE_BOARD_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#ifndef __ASSEMBLY__ +# include +#endif + +/* Do not include STM32 F4 header files here */ + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Clocking *****************************************************************/ + +/* The STM32F4 Discovery board features a single 8MHz crystal. Space is + * provided for a 32kHz RTC backup crystal, but it is not stuffed. + * + * This is the canonical configuration: + * System Clock source : PLL (HSE) + * SYSCLK(Hz) : 180000000 Determined by PLL config + * HCLK(Hz) : 180000000 (STM32_RCC_CFGR_HPRE) + * AHB Prescaler : 1 (STM32_RCC_CFGR_HPRE) + * APB1 Prescaler : 4 (STM32_RCC_CFGR_PPRE1) + * APB2 Prescaler : 2 (STM32_RCC_CFGR_PPRE2) + * HSE Frequency(Hz) : 8000000 (STM32_BOARD_XTAL) + * PLLM : 8 (STM32_PLLCFG_PLLM) + * PLLN : 336 (STM32_PLLCFG_PLLN) + * PLLP : 2 (STM32_PLLCFG_PLLP) + * PLLQ : 7 (STM32_PLLCFG_PLLQ) + * Main regulator output voltage : Scale1 mode Needed for highspeed SYSCLK + * Flash Latency(WS) : 5 + * Prefetch Buffer : OFF + * Instruction cache : ON + * Data cache : ON + * Require 48MHz for USB OTG FS, : Enabled + * SDIO and RNG clock + */ + +/* HSI - 16 MHz RC factory-trimmed + * LSI - 32 KHz RC + * HSE - On-board crystal frequency is 8MHz + * LSE - 32.768 kHz + */ + +#define STM32_BOARD_XTAL 8000000ul + +#define STM32_HSI_FREQUENCY 16000000ul +#define STM32_LSI_FREQUENCY 32000 +#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL +#define STM32_LSE_FREQUENCY 32768 + +/* Main PLL Configuration. + * + * PLL source is HSE + * PLL_VCO = (STM32_HSE_FREQUENCY / PLLM) * PLLN + * = (8,000,000 / 8) * 336 + * = 336,000,000 + * SYSCLK = PLL_VCO / PLLP + * = 336,000,000 / 2 = 168,000,000 + * USB OTG FS, SDIO and RNG Clock + * = PLL_VCO / PLLQ + * = 48,000,000 + */ + +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(8) +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(336) +#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_2 +#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(7) + +#define STM32_SYSCLK_FREQUENCY 168000000ul + +/* AHB clock (HCLK) is SYSCLK (168MHz) */ + +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY + +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd4 /* PCLK1 = HCLK / 4 */ +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/4) + +/* Timers driven from APB1 will be twice PCLK1 */ + +#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) + +/* APB2 clock (PCLK2) is HCLK/2 (84MHz) */ + +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLKd2 /* PCLK2 = HCLK / 2 */ +#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/2) + +/* Timers driven from APB2 will be twice PCLK2 */ + +#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM9_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM10_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM11_CLKIN (2*STM32_PCLK2_FREQUENCY) + +/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx + * otherwise frequency is 2xAPBx. + * Note: TIM1,8 are on APB2, others on APB1 + */ + +#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM2_FREQUENCY (STM32_HCLK_FREQUENCY/2) +#define BOARD_TIM3_FREQUENCY (STM32_HCLK_FREQUENCY/2) +#define BOARD_TIM4_FREQUENCY (STM32_HCLK_FREQUENCY/2) +#define BOARD_TIM5_FREQUENCY (STM32_HCLK_FREQUENCY/2) +#define BOARD_TIM6_FREQUENCY (STM32_HCLK_FREQUENCY/2) +#define BOARD_TIM7_FREQUENCY (STM32_HCLK_FREQUENCY/2) +#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY + +/* DMA Channel/Stream Selections ********************************************/ + +/* Stream selections are arbitrary for now but might become important in the + * future if we set aside more DMA channels/streams. + * + * SDMMC DMA is on DMA2 + * + * SDMMC1 DMA + * DMAMAP_SDMMC1_1 = Channel 4, Stream 3 + * DMAMAP_SDMMC1_2 = Channel 4, Stream 6 + * + * SDMMC2 DMA + * DMAMAP_SDMMC2_1 = Channel 11, Stream 0 + * DMAMAP_SDMMC3_2 = Channel 11, Stream 5 + */ + +#define DMAMAP_SDMMC1 DMAMAP_SDMMC1_1 +#define DMAMAP_SDMMC2 DMAMAP_SDMMC2_1 + +/* FLASH wait states + * + * --------- ---------- ----------- + * VDD MAX SYSCLK WAIT STATES + * --------- ---------- ----------- + * 1.7-2.1 V 180 MHz 8 + * 2.1-2.4 V 216 MHz 9 + * 2.4-2.7 V 216 MHz 8 + * 2.7-3.6 V 216 MHz 7 + * --------- ---------- ----------- + */ + +#define BOARD_FLASH_WAITSTATES 7 + +/* LED definitions **********************************************************/ + +/* The Nucleo-144 board has numerous LEDs but only three, LD1 a Green LED, + * LD2 a Blue LED and LD3 a Red LED, that can be controlled by software. + * The following definitions assume the default Solder Bridges are installed. + * + * If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs + * in any way. + * The following definitions are used to access individual LEDs. + */ + +/* LED index values for use with board_userled() */ + +#define BOARD_LED1 0 +#define BOARD_LED2 1 +#define BOARD_LED3 2 +#define BOARD_NLEDS 3 + +#define BOARD_LED_GREEN BOARD_LED1 +#define BOARD_LED_BLUE BOARD_LED2 +#define BOARD_LED_RED BOARD_LED3 + +/* LED bits for use with board_userled_all() */ + +#define BOARD_LED1_BIT (1 << BOARD_LED1) +#define BOARD_LED2_BIT (1 << BOARD_LED2) +#define BOARD_LED3_BIT (1 << BOARD_LED3) + +/* If CONFIG_ARCH_LEDS is defined, the usage by the board port is defined in + * include/board.h and src/stm32_leds.c. The LEDs are used to encode + * OS-related events as follows: + * + * + * SYMBOL Meaning LED state + * Red Green Blue + * ---------------------- -------------------------- ------ ------ --- + */ + +#define LED_STARTED 0 /* NuttX has been started OFF OFF OFF */ +#define LED_HEAPALLOCATE 1 /* Heap has been allocated OFF OFF ON */ +#define LED_IRQSENABLED 2 /* Interrupts enabled OFF ON OFF */ +#define LED_STACKCREATED 3 /* Idle stack created OFF ON ON */ +#define LED_INIRQ 4 /* In an interrupt N/C N/C GLOW */ +#define LED_SIGNAL 5 /* In a signal handler N/C GLOW N/C */ +#define LED_ASSERTION 6 /* An assertion failed GLOW N/C GLOW */ +#define LED_PANIC 7 /* The system has crashed Blink OFF N/C */ +#define LED_IDLE 8 /* MCU is in sleep mode ON OFF OFF */ + +/* Thus if the Green LED is statically on, NuttX has successfully booted and + * is, apparently, running normally. If the Red LED is flashing at + * approximately 2Hz, then a fatal error has been detected and the system + * has halted. + */ + +/* Button definitions *******************************************************/ + +/* The STM32F4 Discovery supports one button: Pushbutton B1, labeled "User", + * is connected to GPIO PI11. + * A high value will be sensed when the button is depressed. + */ + +#define BUTTON_USER 0 +#define NUM_BUTTONS 1 +#define BUTTON_USER_BIT (1 << BUTTON_USER) + +/* Alternate function pin selections ****************************************/ + +/* TIM */ + +#define GPIO_TIM1_CH1OUT (GPIO_TIM1_CH1OUT_1|GPIO_SPEED_50MHz) +#define GPIO_TIM2_CH1OUT (GPIO_TIM2_CH1OUT_1|GPIO_SPEED_50MHz) +#define GPIO_TIM3_CH1OUT (GPIO_TIM3_CH1OUT_1|GPIO_SPEED_50MHz) +#define GPIO_TIM4_CH1OUT (GPIO_TIM4_CH1OUT_1|GPIO_SPEED_50MHz) + +#if defined(CONFIG_NUCLEO_F429ZI_CONSOLE_ARDUINO) + +/* USART6: + * + * These configurations assume that you are using a standard Arduio RS-232 + * shield with the serial interface with RX on pin D0 and TX on pin D1: + * + * -------- --------------- + * STM32F4 + * ARDUIONO FUNCTION GPIO + * -- ----- --------- ----- + * DO RX USART6_RX PG9 + * D1 TX USART6_TX PG14 + * -- ----- --------- ----- + */ + + # define GPIO_USART6_RX (GPIO_USART6_RX_2|GPIO_SPEED_100MHz) + # define GPIO_USART6_TX (GPIO_USART6_TX_2|GPIO_SPEED_100MHz) +#endif + +/* USART3: + * Use USART3 and the USB virtual COM port + */ + +#if defined(CONFIG_NUCLEO_F429ZI_CONSOLE_VIRTUAL) + # define GPIO_USART3_RX (GPIO_USART3_RX_3|GPIO_SPEED_100MHz) + # define GPIO_USART3_TX (GPIO_USART3_TX_3|GPIO_SPEED_100MHz) +#endif + +/* DMA channels *************************************************************/ + +/* ADC */ + +#define ADC1_DMA_CHAN DMAMAP_ADC1_1 +#define ADC2_DMA_CHAN DMAMAP_ADC2_1 +#define ADC3_DMA_CHAN DMAMAP_ADC3_1 + +/* SPI + * + * + * PA6 SPI1_MISO CN12-13 + * PA7 SPI1_MOSI CN12-15 + * PA5 SPI1_SCK CN12-11 + * + * PB14 SPI2_MISO CN12-28 + * PB15 SPI2_MOSI CN12-26 + * PB13 SPI2_SCK CN12-30 + * + * PB4 SPI3_MISO CN12-27 + * PB5 SPI3_MOSI CN12-29 + * PB3 SPI3_SCK CN12-31 + */ + +#define GPIO_SPI1_MISO (GPIO_SPI1_MISO_1|GPIO_SPEED_50MHz) +#define GPIO_SPI1_MOSI (GPIO_SPI1_MOSI_1|GPIO_SPEED_50MHz) +#define GPIO_SPI1_SCK (GPIO_SPI1_SCK_1|GPIO_SPEED_50MHz) + +#define GPIO_SPI2_MISO (GPIO_SPI2_MISO_1|GPIO_SPEED_50MHz) +#define GPIO_SPI2_MOSI (GPIO_SPI2_MOSI_1|GPIO_SPEED_50MHz) +#define GPIO_SPI2_SCK (GPIO_SPI2_SCK_3|GPIO_SPEED_50MHz) + +#define GPIO_SPI3_MISO (GPIO_SPI3_MISO_1|GPIO_SPEED_50MHz) +#define GPIO_SPI3_MOSI (GPIO_SPI3_MOSI_2|GPIO_SPEED_50MHz) +#define GPIO_SPI3_SCK (GPIO_SPI3_SCK_1|GPIO_SPEED_50MHz) + +/* I2C + * + * + * PB8 I2C1_SCL CN12-3 + * PB9 I2C1_SDA CN12-5 + + * PB10 I2C2_SCL CN11-51 + * PB11 I2C2_SDA CN12-18 + * + * PA8 I2C3_SCL CN12-23 + * PC9 I2C3_SDA CN12-1 + * + */ + +#define GPIO_I2C1_SCL (GPIO_I2C1_SCL_2|GPIO_SPEED_50MHz) +#define GPIO_I2C1_SDA (GPIO_I2C1_SDA_2|GPIO_SPEED_50MHz) + +#define GPIO_I2C2_SCL (GPIO_I2C2_SCL_1|GPIO_SPEED_50MHz) +#define GPIO_I2C2_SDA (GPIO_I2C2_SDA_1|GPIO_SPEED_50MHz) + +#define GPIO_I2C3_SCL (GPIO_I2C3_SCL_1|GPIO_SPEED_50MHz) +#define GPIO_I2C3_SDA (GPIO_I2C3_SDA_1|GPIO_SPEED_50MHz) + +/* The STM32 F4 connects to a SMSC LAN8742A PHY using these pins: + * + * STM32 F4 BOARD LAN8742A + * GPIO SIGNAL PIN NAME + * -------- ------------ ------------- + * PG11 RMII_TX_EN TXEN + * PG13 RMII_TXD0 TXD0 + * PB13 RMII_TXD1 TXD1 + * PC4 RMII_RXD0 RXD0/MODE0 + * PC5 RMII_RXD1 RXD1/MODE1 + * PG2 RMII_RXER RXER/PHYAD0 -- Not used + * PA7 RMII_CRS_DV CRS_DV/MODE2 + * PC1 RMII_MDC MDC + * PA2 RMII_MDIO MDIO + * N/A NRST nRST + * PA1 RMII_REF_CLK nINT/REFCLK0 + * N/A OSC_25M XTAL1/CLKIN + * + * The PHY address is either 0 or 1, depending on the state of PG2 on reset. + * PG2 is not controlled but appears to result in a PHY address of 0. + */ + +#define GPIO_ETH_RMII_TX_EN (GPIO_ETH_RMII_TX_EN_2|GPIO_SPEED_100MHz) +#define GPIO_ETH_RMII_TXD0 (GPIO_ETH_RMII_TXD0_2|GPIO_SPEED_100MHz) +#define GPIO_ETH_RMII_TXD1 (GPIO_ETH_RMII_TXD1_1|GPIO_SPEED_100MHz) + +#define GPIO_ETH_MDC (GPIO_ETH_MDC_0|GPIO_SPEED_100MHz) +#define GPIO_ETH_MDIO (GPIO_ETH_MDIO_0|GPIO_SPEED_100MHz) +#define GPIO_ETH_RMII_CRS_DV (GPIO_ETH_RMII_CRS_DV_0|GPIO_SPEED_100MHz) +#define GPIO_ETH_RMII_REF_CLK (GPIO_ETH_RMII_REF_CLK_0|GPIO_SPEED_100MHz) +#define GPIO_ETH_RMII_RXD0 (GPIO_ETH_RMII_RXD0_0|GPIO_SPEED_100MHz) +#define GPIO_ETH_RMII_RXD1 (GPIO_ETH_RMII_RXD1_0|GPIO_SPEED_100MHz) + +#endif /* __BOARDS_ARM_STM32F4_NUCLEO_F429ZI_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32f4/nucleo-f429zi/scripts/Make.defs b/boards/arm/stm32f4/nucleo-f429zi/scripts/Make.defs new file mode 100644 index 0000000000000..b60be2ea2217a --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f429zi/scripts/Make.defs @@ -0,0 +1,41 @@ +############################################################################ +# boards/arm/stm32f4/nucleo-f429zi/scripts/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/.config +include $(TOPDIR)/tools/Config.mk +include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs + +LDSCRIPT = ld.script +ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) + +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32f4/nucleo-f429zi/scripts/kernel-space.ld b/boards/arm/stm32f4/nucleo-f429zi/scripts/kernel-space.ld new file mode 100644 index 0000000000000..c1decce24f5f9 --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f429zi/scripts/kernel-space.ld @@ -0,0 +1,100 @@ +/**************************************************************************** + * boards/arm/stm32f4/nucleo-f429zi/scripts/kernel-space.ld + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* NOTE: This depends on the memory.ld script having been included prior to + * this script. + */ + +OUTPUT_ARCH(arm) +EXTERN(_vectors) +ENTRY(_stext) +SECTIONS +{ + .text : { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > kflash + + .init_section : { + _sinit = ABSOLUTE(.); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) + _einit = ABSOLUTE(.); + } > kflash + + .ARM.extab : { + *(.ARM.extab*) + } > kflash + + __exidx_start = ABSOLUTE(.); + .ARM.exidx : { + *(.ARM.exidx*) + } > kflash + + __exidx_end = ABSOLUTE(.); + + _eronly = ABSOLUTE(.); + + .data : { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > ksram AT > kflash + + .bss : { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(8); + _ebss = ABSOLUTE(.); + } > ksram + + /* Stabs debugging sections */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/stm32f4/nucleo-f429zi/scripts/ld.script b/boards/arm/stm32f4/nucleo-f429zi/scripts/ld.script new file mode 100644 index 0000000000000..9a1d4001a9959 --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f429zi/scripts/ld.script @@ -0,0 +1,133 @@ +/**************************************************************************** + * boards/arm/stm32f4/nucleo-f429zi/scripts/ld.script + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* The STM32F429ZIT6 has 2048Kb of FLASH beginning at address 0x0800:0000 and + * 256Kb of SRAM. SRAM is split up into four blocks: + * + * 1) 112Kb of SRAM beginning at address 0x2000:0000 + * 2) 16Kb of SRAM beginning at address 0x2001:c000 + * 3) 64Kb of SRAM beginning at address 0x2002:0000 + * 4) 64Kb of CCM SRAM beginning at address 0x1000:0000 + * + * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 + * where the code expects to begin execution by jumping to the entry point in + * the 0x0800:0000 address + * range. + */ + +MEMORY +{ + flash (rx) : ORIGIN = 0x08000000, LENGTH = 2048K + sram (rwx) : ORIGIN = 0x20000000, LENGTH = 112K +} + +OUTPUT_ARCH(arm) +EXTERN(_vectors) +ENTRY(_stext) +SECTIONS +{ + .text : { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > flash + + .init_section : ALIGN(4) { + _sinit = ABSOLUTE(.); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) + _einit = ABSOLUTE(.); + } > flash + + .ARM.extab : ALIGN(4) { + *(.ARM.extab*) + } > flash + + .ARM.exidx : ALIGN(4) { + __exidx_start = ABSOLUTE(.); + *(.ARM.exidx*) + __exidx_end = ABSOLUTE(.); + } > flash + + .tdata : { + _stdata = ABSOLUTE(.); + *(.tdata .tdata.* .gnu.linkonce.td.*); + _etdata = ABSOLUTE(.); + } > flash + + .tbss : { + _stbss = ABSOLUTE(.); + *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); + _etbss = ABSOLUTE(.); + } > flash + + _eronly = ABSOLUTE(.); + + /* The RAM vector table (if present) should lie at the beginning of SRAM */ + + .ram_vectors : { + *(.ram_vectors) + } > sram + + .data : ALIGN(4) { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > sram AT > flash + + .bss : ALIGN(4) { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + _ebss = ABSOLUTE(.); + } > sram + + /* Stabs debugging sections. */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/stm32f4/nucleo-f429zi/scripts/memory.ld b/boards/arm/stm32f4/nucleo-f429zi/scripts/memory.ld new file mode 100644 index 0000000000000..ec8a5798e4ac2 --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f429zi/scripts/memory.ld @@ -0,0 +1,88 @@ +/**************************************************************************** + * boards/arm/stm32f4/nucleo-f429zi/scripts/memory.ld + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* The STM32F429ZIT has 2048Kb of FLASH beginning at address 0x0800:0000 and + * 256Kb of SRAM. SRAM is split up into four blocks: + * + * 1) 112KB of SRAM beginning at address 0x2000:0000 + * 2) 16KB of SRAM beginning at address 0x2001:c000 + * 3) 64KB of SRAM beginning at address 0x2002:0000 + * 4) 64KB of CCM SRAM beginning at address 0x1000:0000 + * + * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 + * where the code expects to begin execution by jumping to the entry point in + * the 0x0800:0000 address range. + * + * For MPU support, the kernel-mode NuttX section is assumed to be 128Kb of + * FLASH and 4Kb of SRAM. That is an excessive amount for the kernel which + * should fit into 64KB and, of course, can be optimized as needed (See + * also boards/arm/stm32f4/stm32f429i-disco/scripts/kernel-space.ld). Allowing the + * additional does permit addition debug instrumentation to be added to the + * kernel space without overflowing the partition. + * + * Alignment of the user space FLASH partition is also a critical factor: + * The user space FLASH partition will be spanned with a single region of + * size 2**n bytes. The alignment of the user-space region must be the same. + * As a consequence, as the user-space increases in size, the alignment + * requirement also increases. + * + * This alignment requirement means that the largest user space FLASH region + * you can have will be 512KB at it would have to be positioned at + * 0x08800000. If you change this address, don't forget to change the + * CONFIG_NUTTX_USERSPACE configuration setting to match and to modify + * the check in kernel/userspace.c. + * + * For the same reasons, the maximum size of the SRAM mapping is limited to + * 4KB. Both of these alignment limitations could be reduced by using + * multiple regions to map the FLASH/SDRAM range or perhaps with some + * clever use of subregions. + * + * A detailed memory map for the 112KB SRAM region is as follows: + * + * 0x20000 0000: Kernel .data region. Typical size: 0.1KB + * ------- ---- Kernel .bss region. Typical size: 1.8KB + * 0x20000 0800: Kernel IDLE thread stack (approximate). Size is + * determined by CONFIG_IDLETHREAD_STACKSIZE and + * adjustments for alignment. Typical is 1KB. + * ------- ---- Padded to 4KB + * 0x20000 1000: User .data region. Size is variable. + * ------- ---- User .bss region Size is variable. + * 0x20000 2000: Beginning of kernel heap. Size determined by + * CONFIG_MM_KERNEL_HEAPSIZE. + * ------- ---- Beginning of user heap. Can vary with other settings. + * 0x20001 c000: End+1 of CPU RAM + */ + +MEMORY +{ + /* 1024Kb FLASH */ + + kflash (rx) : ORIGIN = 0x08000000, LENGTH = 128K + uflash (rx) : ORIGIN = 0x08020000, LENGTH = 128K + xflash (rx) : ORIGIN = 0x08040000, LENGTH = 768K + + /* 112Kb of contiguous SRAM */ + + ksram (rwx) : ORIGIN = 0x20000000, LENGTH = 4K + usram (rwx) : ORIGIN = 0x20001000, LENGTH = 4K + xsram (rwx) : ORIGIN = 0x20002000, LENGTH = 104K +} diff --git a/boards/arm/stm32f4/nucleo-f429zi/scripts/user-space.ld b/boards/arm/stm32f4/nucleo-f429zi/scripts/user-space.ld new file mode 100644 index 0000000000000..2a9866a6758cf --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f429zi/scripts/user-space.ld @@ -0,0 +1,114 @@ +/**************************************************************************** + * boards/arm/stm32f4/nucleo-f429zi/scripts/user-space.ld + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* NOTE: This depends on the memory.ld script having been included prior to + * this script. + */ + +/* Make sure that the critical memory management functions are in user-space. + * the user heap memory manager will reside in user-space but be usable both + * by kernel- and user-space code + */ + +EXTERN(umm_initialize) +EXTERN(umm_addregion) + +EXTERN(malloc) +EXTERN(realloc) +EXTERN(zalloc) +EXTERN(free) + +OUTPUT_ARCH(arm) +SECTIONS +{ + .userspace : { + *(.userspace) + } > uflash + + .text : { + _stext = ABSOLUTE(.); + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > uflash + + .init_section : { + _sinit = ABSOLUTE(.); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) + _einit = ABSOLUTE(.); + } > uflash + + .ARM.extab : { + *(.ARM.extab*) + } > uflash + + __exidx_start = ABSOLUTE(.); + .ARM.exidx : { + *(.ARM.exidx*) + } > uflash + + __exidx_end = ABSOLUTE(.); + + _eronly = ABSOLUTE(.); + + .data : { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > usram AT > uflash + + .bss : { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(8); + _ebss = ABSOLUTE(.); + } > usram + + /* Stabs debugging sections */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/stm32f4/nucleo-f429zi/src/CMakeLists.txt b/boards/arm/stm32f4/nucleo-f429zi/src/CMakeLists.txt new file mode 100644 index 0000000000000..3977def05e600 --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f429zi/src/CMakeLists.txt @@ -0,0 +1,65 @@ +# ############################################################################## +# boards/arm/stm32f4/nucleo-f429zi/src/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(SRCS stm32_boot.c) + +if(CONFIG_ARCH_LEDS) + list(APPEND SRCS stm32_autoleds.c) +else() + list(APPEND SRCS stm32_userleds.c) +endif() + +if(CONFIG_ARCH_BUTTONS) + list(APPEND SRCS stm32_buttons.c) +endif() + +if(CONFIG_DEV_GPIO) + list(APPEND SRCS stm32_gpio.c) +endif() + +if(CONFIG_SPI) + list(APPEND SRCS stm32_spi.c) +endif() + +if(CONFIG_ADC) + list(APPEND SRCS stm32_adc.c) +endif() + +if(CONFIG_PWM) + list(APPEND SRCS stm32_pwm.c) +endif() + +if(CONFIG_MMCSD) + list(APPEND SRCS stm32_sdio.c) +endif() + +if(CONFIG_STM32_OTGFS) + list(APPEND SRCS stm32_usb.c) +endif() + +if(CONFIG_STM32_BBSRAM) + list(APPEND SRCS stm32_bbsram.c) +endif() + +target_sources(board PRIVATE ${SRCS}) + +set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/ld.script") diff --git a/boards/arm/stm32f4/nucleo-f429zi/src/Make.defs b/boards/arm/stm32f4/nucleo-f429zi/src/Make.defs new file mode 100644 index 0000000000000..b5de1a7ff7ee6 --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f429zi/src/Make.defs @@ -0,0 +1,67 @@ +############################################################################ +# boards/arm/stm32f4/nucleo-f429zi/src/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +CSRCS = stm32_boot.c + +ifeq ($(CONFIG_ARCH_LEDS),y) +CSRCS += stm32_autoleds.c +else +CSRCS += stm32_userleds.c +endif + +ifeq ($(CONFIG_ARCH_BUTTONS),y) +CSRCS += stm32_buttons.c +endif + +ifeq ($(CONFIG_DEV_GPIO),y) +CSRCS += stm32_gpio.c +endif + +ifeq ($(CONFIG_SPI),y) +CSRCS += stm32_spi.c +endif + +ifeq ($(CONFIG_ADC),y) +CSRCS += stm32_adc.c +endif + +ifeq ($(CONFIG_PWM),y) +CSRCS += stm32_pwm.c +endif + +ifeq ($(CONFIG_MMCSD),y) +CSRCS += stm32_sdio.c +endif + +ifeq ($(CONFIG_STM32_OTGFS),y) +CSRCS += stm32_usb.c +endif + +ifeq ($(CONFIG_STM32_BBSRAM),y) +CSRCS += stm32_bbsram.c +endif + +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/nucleo-f429zi/src/nucleo-144.h b/boards/arm/stm32f4/nucleo-f429zi/src/nucleo-144.h similarity index 99% rename from boards/arm/stm32/nucleo-f429zi/src/nucleo-144.h rename to boards/arm/stm32f4/nucleo-f429zi/src/nucleo-144.h index c66f463faa4fc..60e0078b43c8a 100644 --- a/boards/arm/stm32/nucleo-f429zi/src/nucleo-144.h +++ b/boards/arm/stm32f4/nucleo-f429zi/src/nucleo-144.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f429zi/src/nucleo-144.h + * boards/arm/stm32f4/nucleo-f429zi/src/nucleo-144.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f4/nucleo-f429zi/src/stm32_adc.c b/boards/arm/stm32f4/nucleo-f429zi/src/stm32_adc.c new file mode 100644 index 0000000000000..1c8b4361bdf3a --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f429zi/src/stm32_adc.c @@ -0,0 +1,169 @@ +/**************************************************************************** + * boards/arm/stm32f4/nucleo-f429zi/src/stm32_adc.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include +#include + +#include "chip.h" +#include "stm32_gpio.h" +#include "stm32_adc.h" +#include "nucleo-144.h" + +#ifdef CONFIG_ADC + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* Up to 3 ADC interfaces are supported */ + +#if STM32F4_NADC < 3 +# undef CONFIG_STM32_ADC3 +#endif + +#if STM32F4_NADC < 2 +# undef CONFIG_STM32_ADC2 +#endif + +#if STM32F4_NADC < 1 +# undef CONFIG_STM32_ADC1 +#endif + +#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) || defined(CONFIG_STM32_ADC3) +#ifndef CONFIG_STM32_ADC1 +# warning "Channel information only available for ADC1" +#endif + +/* The number of ADC channels in the conversion list */ + +#define ADC1_NCHANNELS 1 + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* Identifying number of each ADC channel: Variable Resistor. + * + * {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 15}; + */ + +#ifdef CONFIG_STM32_ADC1 +static const uint8_t g_chanlist[ADC1_NCHANNELS] = + { + 3 + }; + +/* Configurations of pins used byte each ADC channels + * + * {GPIO_ADC1_IN1, GPIO_ADC1_IN2, GPIO_ADC1_IN3, GPIO_ADC1_IN4, + * GPIO_ADC1_IN5, GPIO_ADC1_IN6, GPIO_ADC1_IN7, GPIO_ADC1_IN8, + * GPIO_ADC1_IN9, GPIO_ADC1_IN10, GPIO_ADC1_IN11, GPIO_ADC1_IN12, + * GPIO_ADC1_IN13, GPIO_ADC1_IN15}; + */ + +static const uint32_t g_pinlist[ADC1_NCHANNELS] = + { + GPIO_ADC1_IN3 + }; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_adc_setup + * + * Description: + * Initialize ADC and register the ADC driver. + * + ****************************************************************************/ + +int stm32_adc_setup(void) +{ +#ifdef CONFIG_STM32_ADC1 + static bool initialized = false; + struct adc_dev_s *adc; + int ret; + int i; + + /* Check if we have already initialized */ + + if (!initialized) + { + /* Configure the pins as analog inputs for the selected channels */ + + for (i = 0; i < ADC1_NCHANNELS; i++) + { + if (g_pinlist[i] != 0) + { + stm32_configgpio(g_pinlist[i]); + } + } + + /* Call stm32_adcinitialize() to get an instance of the ADC interface */ + + adc = stm32_adc_initialize(1, g_chanlist, ADC1_NCHANNELS); + if (adc == NULL) + { + aerr("ERROR: Failed to get ADC interface\n"); + return -ENODEV; + } + + /* Register the ADC driver at "/dev/adc0" */ + + ret = adc_register("/dev/adc0", adc); + if (ret < 0) + { + aerr("ERROR: adc_register failed: %d\n", ret); + return ret; + } + + /* Now we are initialized */ + + initialized = true; + } + + return OK; +#else + return -ENOSYS; +#endif +} + +#endif /* CONFIG_STM32_ADC1 || CONFIG_STM32_ADC2 || CONFIG_STM32_ADC3 */ +#endif /* CONFIG_ADC */ diff --git a/boards/arm/stm32f4/nucleo-f429zi/src/stm32_autoleds.c b/boards/arm/stm32f4/nucleo-f429zi/src/stm32_autoleds.c new file mode 100644 index 0000000000000..54359c2a1741f --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f429zi/src/stm32_autoleds.c @@ -0,0 +1,170 @@ +/**************************************************************************** + * boards/arm/stm32f4/nucleo-f429zi/src/stm32_autoleds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include + +#include +#include + +#include "stm32_gpio.h" +#include "nucleo-144.h" +#ifdef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* Indexed by BOARD_LED_ */ + +static const uint32_t g_ledmap[BOARD_NLEDS] = +{ + GPIO_LED_GREEN, + GPIO_LED_BLUE, + GPIO_LED_RED, +}; + +static bool g_initialized; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +static void phy_set_led(int led, bool state) +{ + /* Active High */ + + stm32_gpiowrite(g_ledmap[led], state); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_autoled_initialize + ****************************************************************************/ + +void board_autoled_initialize(void) +{ + int i; + + /* Configure the LD1 GPIO for output. Initial state is OFF */ + + for (i = 0; i < nitems(g_ledmap); i++) + { + stm32_configgpio(g_ledmap[i]); + } +} + +/**************************************************************************** + * Name: board_autoled_on + ****************************************************************************/ + +void board_autoled_on(int led) +{ + switch (led) + { + default: + break; + + case LED_HEAPALLOCATE: + phy_set_led(BOARD_LED_BLUE, true); + break; + + case LED_IRQSENABLED: + phy_set_led(BOARD_LED_BLUE, false); + phy_set_led(BOARD_LED_GREEN, true); + break; + + case LED_STACKCREATED: + phy_set_led(BOARD_LED_GREEN, true); + phy_set_led(BOARD_LED_BLUE, true); + g_initialized = true; + break; + + case LED_INIRQ: + phy_set_led(BOARD_LED_BLUE, true); + break; + + case LED_SIGNAL: + phy_set_led(BOARD_LED_GREEN, true); + break; + + case LED_ASSERTION: + phy_set_led(BOARD_LED_RED, true); + phy_set_led(BOARD_LED_BLUE, true); + break; + + case LED_PANIC: + phy_set_led(BOARD_LED_RED, true); + break; + + case LED_IDLE : /* IDLE */ + phy_set_led(BOARD_LED_RED, true); + break; + } +} + +/**************************************************************************** + * Name: board_autoled_off + ****************************************************************************/ + +void board_autoled_off(int led) +{ + switch (led) + { + default: + break; + + case LED_SIGNAL: + phy_set_led(BOARD_LED_GREEN, false); + break; + + case LED_INIRQ: + phy_set_led(BOARD_LED_BLUE, false); + break; + + case LED_ASSERTION: + phy_set_led(BOARD_LED_RED, false); + phy_set_led(BOARD_LED_BLUE, false); + break; + + case LED_PANIC: + phy_set_led(BOARD_LED_RED, false); + break; + + case LED_IDLE : /* IDLE */ + phy_set_led(BOARD_LED_RED, false); + break; + } +} + +#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32f4/nucleo-f429zi/src/stm32_bbsram.c b/boards/arm/stm32f4/nucleo-f429zi/src/stm32_bbsram.c new file mode 100644 index 0000000000000..fa40d5c420128 --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f429zi/src/stm32_bbsram.c @@ -0,0 +1,519 @@ +/**************************************************************************** + * boards/arm/stm32f4/nucleo-f429zi/src/stm32_bbsram.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include + +#include "arm_internal.h" +#include "stm32_bbsram.h" + +#include "nucleo-144.h" + +#ifdef CONFIG_STM32_BBSRAM + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +#define FREEZE_STR(s) #s +#define STRINGIFY(s) FREEZE_STR(s) +#define HARDFAULT_FILENO 3 +#define HARDFAULT_PATH BBSRAM_PATH""STRINGIFY(HARDFAULT_FILENO) +#define HARDFAULT_REBOOT_ FILENO 0 +#define HARDFAULT_REBOOT_PATH BBSRAM_PATH""STRINGIFY(HARDFAULT_REBOOT_FILENO) + +#define BBSRAM_SIZE_FN0 (sizeof(int)) +#define BBSRAM_SIZE_FN1 384 +#define BBSRAM_SIZE_FN2 384 +#define BBSRAM_SIZE_FN3 - 1 + +/* The following guides in the amount of the user and interrupt stack + * data we can save. The amount of storage left will dictate the actual + * number of entries of the user stack data saved. If it is too big + * It will be truncated by the call to stm32_bbsram_savepanic + */ +#define BBSRAM_HEADER_SIZE 20 /* This is an assumption */ +#define BBSRAM_USED ((4*BBSRAM_HEADER_SIZE)+ \ + (BBSRAM_SIZE_FN0+BBSRAM_SIZE_FN1+ \ + BBSRAM_SIZE_FN2)) +#define BBSRAM_REAMINING (STM32_BBSRAM_SIZE-BBSRAM_USED) +#if CONFIG_ARCH_INTERRUPTSTACK <= 3 +# define BBSRAM_NUMBER_STACKS 1 +#else +# define BBSRAM_NUMBER_STACKS 2 +#endif +#define BBSRAM_FIXED_ELEMENTS_SIZE (sizeof(info_t)) +#define BBSRAM_LEFTOVER (BBSRAM_REAMINING-\ + BBSRAM_FIXED_ELEMENTS_SIZE) + +#define CONFIG_ISTACK_SIZE (BBSRAM_LEFTOVER/BBSRAM_NUMBER_STACKS/ \ + sizeof(stack_word_t)) +#define CONFIG_USTACK_SIZE (BBSRAM_LEFTOVER/BBSRAM_NUMBER_STACKS/ \ + sizeof(stack_word_t)) + +/* The path to the Battery Backed up SRAM */ + +#define BBSRAM_PATH "/fs/bbr" + +/* The sizes of the files to create (-1) use rest of BBSRAM memory */ + +#define BSRAM_FILE_SIZES \ +{ \ + BBSRAM_SIZE_FN0, \ + BBSRAM_SIZE_FN1, \ + BBSRAM_SIZE_FN2, \ + BBSRAM_SIZE_FN3, \ + 0 \ +} + +/* For Assert keep this much of the file name */ + +#define MAX_FILE_PATH_LENGTH 40 + +#define HEADER_TIME_FMT "%Y-%m-%d-%H:%M:%S" +#define HEADER_TIME_FMT_NUM (2+ 0+ 0+ 0+ 0+ 0) +#define HEADER_TIME_FMT_LEN (((nitems(HEADER_TIME_FMT)-1) + \ + HEADER_TIME_FMT_NUM)) + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* Used for stack frame storage */ + +typedef uint32_t stack_word_t; + +/* Stack related data */ + +typedef struct +{ + uint32_t sp; + uint32_t top; + uint32_t size; +} _stack_t; + +typedef struct +{ + _stack_t user; +#if CONFIG_ARCH_INTERRUPTSTACK > 3 + _stack_t interrupt; +#endif +} stacks_t; + +/* Not Used for reference only */ + +typedef struct +{ + uint32_t r0; + uint32_t r1; + uint32_t r2; + uint32_t r3; + uint32_t r4; + uint32_t r5; + uint32_t r6; + uint32_t r7; + uint32_t r8; + uint32_t r9; + uint32_t r10; + uint32_t r11; + uint32_t r12; + uint32_t sp; + uint32_t lr; + uint32_t pc; + uint32_t xpsr; + uint32_t d0; + uint32_t d1; + uint32_t d2; + uint32_t d3; + uint32_t d4; + uint32_t d5; + uint32_t d6; + uint32_t d7; + uint32_t d8; + uint32_t d9; + uint32_t d10; + uint32_t d11; + uint32_t d12; + uint32_t d13; + uint32_t d14; + uint32_t d15; + uint32_t fpscr; + uint32_t sp_main; + uint32_t sp_process; + uint32_t apsr; + uint32_t ipsr; + uint32_t epsr; + uint32_t primask; + uint32_t basepri; + uint32_t faultmask; + uint32_t control; + uint32_t s0; + uint32_t s1; + uint32_t s2; + uint32_t s3; + uint32_t s4; + uint32_t s5; + uint32_t s6; + uint32_t s7; + uint32_t s8; + uint32_t s9; + uint32_t s10; + uint32_t s11; + uint32_t s12; + uint32_t s13; + uint32_t s14; + uint32_t s15; + uint32_t s16; + uint32_t s17; + uint32_t s18; + uint32_t s19; + uint32_t s20; + uint32_t s21; + uint32_t s22; + uint32_t s23; + uint32_t s24; + uint32_t s25; + uint32_t s26; + uint32_t s27; + uint32_t s28; + uint32_t s29; + uint32_t s30; + uint32_t s31; +} proc_regs_t; + +/* Flags to identify what is in the dump */ + +typedef enum +{ + REGS_PRESENT = 0x01, + USERSTACK_PRESENT = 0x02, + INTSTACK_PRESENT = 0x04, + INVALID_USERSTACK_PTR = 0x20, + INVALID_INTSTACK_PTR = 0x40, +} fault_flags_t; + +typedef struct +{ + fault_flags_t flags; /* What is in the dump */ + uintptr_t current_regs; /* Used to validate the dump */ + int lineno; /* __LINE__ to up_assert */ + pid_t pid; /* Process ID */ + uint32_t regs[XCPTCONTEXT_REGS]; /* Interrupt register save area */ + stack_t stacks; /* Stack info */ + char name[CONFIG_TASK_NAME_SIZE + 1]; /* Task name (with NULL + * terminator) */ + char filename[MAX_FILE_PATH_LENGTH]; /* the Last of chars in + * __FILE__ to up_assert */ +} info_t; + +typedef struct +{ + info_t info; /* The info */ +#if CONFIG_ARCH_INTERRUPTSTACK > 3 + /* The amount of stack data is compile time + * sized backed on what is left after the + * other BBSRAM files are defined + * The order is such that only the + * ustack should be truncated + */ + stack_word_t istack[CONFIG_USTACK_SIZE]; +#endif + stack_word_t ustack[CONFIG_ISTACK_SIZE]; +} fullcontext_t; + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static uint8_t g_sdata[STM32_BBSRAM_SIZE]; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: hardfault_get_desc + ****************************************************************************/ + +static int hardfault_get_desc(struct bbsramd_s *desc) +{ + struct file filestruct; + int ret; + + ret = file_open(&filestruct, HARDFAULT_PATH, O_RDONLY); + if (ret < 0) + { + syslog(LOG_INFO, "stm32 bbsram: Failed to open Fault Log file [%s] " + "(%d)\n", HARDFAULT_PATH, ret); + } + else + { + ret = file_ioctl(&filestruct, STM32_BBSRAM_GETDESC_IOCTL, + (unsigned long)((uintptr_t)desc)); + file_close(&filestruct); + + if (ret < 0) + { + syslog(LOG_INFO, "stm32 bbsram:" + "Failed to get Fault Log descriptor" "(%d)\n", ret); + } + } + + return ret; +} + +/**************************************************************************** + * Name: copy_reverse + ****************************************************************************/ + +#if defined(CONFIG_STM32_SAVE_CRASHDUMP) +static void copy_reverse(stack_word_t *dest, stack_word_t *src, int size) +{ + while (size--) + { + *dest++ = *src--; + } +} +#endif /* CONFIG_STM32_SAVE_CRASHDUMP */ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_bbsram_int + ****************************************************************************/ + +int stm32_bbsram_int(void) +{ + int filesizes[CONFIG_STM32_BBSRAM_FILES + 1] = BSRAM_FILE_SIZES; + char buf[HEADER_TIME_FMT_LEN + 1]; + struct bbsramd_s desc; + int rv; + int state; + struct tm tt; + time_t time_sec; + + /* Using Battery Backed Up SRAM */ + + stm32_bbsraminitialize(BBSRAM_PATH, filesizes); + +#if defined(CONFIG_STM32_SAVE_CRASHDUMP) + /* Panic Logging in Battery Backed Up Files + * Do we have an hard fault in BBSRAM? + */ + + rv = hardfault_get_desc(&desc); + if (rv >= OK) + { + syslog(LOG_EMERG, "There is a hard fault logged.\n"); + state = (desc.lastwrite.tv_sec || desc.lastwrite.tv_nsec) ? OK : 1; + + syslog(LOG_INFO, "Fault Log info File No %d Length %d flags:0x%02x " + "state:%d\n", (unsigned int)desc.fileno, (unsigned int) desc.len, + (unsigned int)desc.flags, state); + + if (state == OK) + { + time_sec = desc.lastwrite.tv_sec + (desc.lastwrite.tv_nsec / 1e9); + gmtime_r(&time_sec, &tt); + strftime(buf, HEADER_TIME_FMT_LEN , HEADER_TIME_FMT , &tt); + + syslog(LOG_INFO, "Fault Logged on %s - Valid\n", buf); + } + + rv = nx_unlink(HARDFAULT_PATH); + if (rv < 0) + { + syslog(LOG_INFO, "stm32 bbsram: Failed to unlink Fault Log file" + "[%s] (%d)\n", HARDFAULT_PATH, rv); + } + } +#endif /* CONFIG_STM32_SAVE_CRASHDUMP */ + + return rv; +} + +/**************************************************************************** + * Name: board_crashdump + ****************************************************************************/ + +#if defined(CONFIG_STM32_SAVE_CRASHDUMP) +void board_crashdump(uintptr_t sp, struct tcb_s *tcb, + const char *filename, int lineno, + const char *msg, void *regs) +{ + fullcontext_t *pdump = (fullcontext_t *)&g_sdata; + int rv; + + enter_critical_section(); + + /* Zero out everything */ + + memset(pdump, 0, sizeof(fullcontext_t)); + + /* Save Info */ + + pdump->info.lineno = lineno; + + if (filename) + { + int offset = 0; + unsigned int len = strlen((char *)filename) + 1; + + if (len > sizeof(pdump->info.filename)) + { + offset = len - sizeof(pdump->info.filename); + } + + strlcpy(pdump->info.filename, (char *)&filename[offset], + sizeof(pdump->info.filename)); + } + + /* Save the value of the pointer for current_regs as debugging info. + * It should be NULL in case of an ASSERT and will aid in cross + * checking the validity of system memory at the time of the + * fault. + */ + + pdump->info.current_regs = (uintptr_t)running_regs(); + + /* Save Context */ + + strlcpy(pdump->info.name, get_task_name(tcb), sizeof(pdump->info.name)); + + pdump->info.pid = tcb->pid; + + if (up_interrupt_context()) + { + pdump->info.stacks.interrupt.sp = sp; + pdump->info.flags |= (REGS_PRESENT | USERSTACK_PRESENT | + INTSTACK_PRESENT); + memcpy(pdump->info.regs, running_regs(), + sizeof(pdump->info.regs)); + pdump->info.stacks.user.sp = pdump->info.regs[REG_R13]; + } + else + { + /* users context */ + + pdump->info.flags |= USERSTACK_PRESENT; + pdump->info.stacks.user.sp = sp; + } + + pdump->info.stacks.user.top = (uint32_t)tcb->stack_base_ptr + + tcb->adj_stack_size; + pdump->info.stacks.user.size = (uint32_t)tcb->adj_stack_size; + +#if CONFIG_ARCH_INTERRUPTSTACK > 3 + /* Get the limits on the interrupt stack memory */ + + pdump->info.stacks.interrupt.top = (uint32_t)g_intstacktop; + pdump->info.stacks.interrupt.size = (CONFIG_ARCH_INTERRUPTSTACK & ~3); + + /* If In interrupt Context save the interrupt stack data centered + * about the interrupt stack pointer + */ + + if ((pdump->info.flags & INTSTACK_PRESENT) != 0) + { + stack_word_t *ps = (stack_word_t *) pdump->info.stacks.interrupt.sp; + copy_reverse(pdump->istack, &ps[nitems(pdump->istack) / 2], + nitems(pdump->istack)); + } + + /* Is it Invalid? */ + + if (!(pdump->info.stacks.interrupt.sp + <= pdump->info.stacks.interrupt.top && + pdump->info.stacks.interrupt.sp > pdump->info.stacks.interrupt.top - + pdump->info.stacks.interrupt.size)) + { + pdump->info.flags |= INVALID_INTSTACK_PTR; + } + +#endif + /* If In interrupt context or User save the user stack data centered + * about the user stack pointer + */ + + if ((pdump->info.flags & USERSTACK_PRESENT) != 0) + { + stack_word_t *ps = (stack_word_t *) pdump->info.stacks.user.sp; + copy_reverse(pdump->ustack, &ps[nitems(pdump->ustack) / 2], + nitems(pdump->ustack)); + } + + /* Is it Invalid? */ + + if (!(pdump->info.stacks.user.sp <= pdump->info.stacks.user.top && + pdump->info.stacks.user.sp > pdump->info.stacks.user.top - + pdump->info.stacks.user.size)) + { + pdump->info.flags |= INVALID_USERSTACK_PTR; + } + + rv = stm32_bbsram_savepanic(HARDFAULT_FILENO, (uint8_t *)pdump, + sizeof(fullcontext_t)); + + /* Test if memory got wiped because of using _sdata */ + + if (rv == -ENXIO) + { + char *dead = "Memory wiped - dump not saved!"; + + while (*dead) + { + arm_lowputc(*dead++); + } + } + else if (rv == -ENOSPC) + { + /* hard fault again */ + + arm_lowputc('!'); + } +} +#endif /* CONFIG_STM32_SAVE_CRASHDUMP */ + +#endif /* CONFIG_STM32_BBSRAM */ diff --git a/boards/arm/stm32f4/nucleo-f429zi/src/stm32_boot.c b/boards/arm/stm32f4/nucleo-f429zi/src/stm32_boot.c new file mode 100644 index 0000000000000..656da24f96794 --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f429zi/src/stm32_boot.c @@ -0,0 +1,252 @@ +/**************************************************************************** + * boards/arm/stm32f4/nucleo-f429zi/src/stm32_boot.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include +#include + +#include +#include +#include +#include + +#include "arm_internal.h" +#include "nucleo-144.h" + +#ifdef CONFIG_STM32_ROMFS +#include "stm32_romfs.h" +#endif + +#ifdef CONFIG_SENSORS_AMG88XX +#include "stm32_amg88xx.h" +#endif + +#if defined(CONFIG_I2C) && defined(CONFIG_SYSTEM_I2CTOOL) +# include "stm32_i2c.h" +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_i2c_register + * + * Description: + * Register one I2C drivers for the I2C tool. + * + ****************************************************************************/ + +#if defined(CONFIG_I2C) && defined(CONFIG_SYSTEM_I2CTOOL) +static void stm32_i2c_register(int bus) +{ + struct i2c_master_s *i2c; + int ret; + + i2c = stm32_i2cbus_initialize(bus); + if (i2c == NULL) + { + syslog(LOG_ERR, "ERROR: Failed to get I2C%d interface\n", bus); + } + else + { + ret = i2c_register(i2c, bus); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to register I2C%d driver: %d\n", + bus, ret); + stm32_i2cbus_uninitialize(i2c); + } + } +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_boardinitialize + * + * Description: + * All STM32 architectures must provide the following entry point. + * This entry point is called early in the initialization + * after all memory has been configured and mapped but + * before any devices have been initialized. + * + ****************************************************************************/ + +void stm32_boardinitialize(void) +{ +#ifdef CONFIG_ARCH_LEDS + /* Configure on-board LEDs if LED support has been selected. */ + + board_autoled_initialize(); +#endif + +#if defined(CONFIG_STM32_OTGFS) || defined(CONFIG_STM32_HOST) + stm32_usbinitialize(); +#endif + +#if defined(CONFIG_SPI) + /* Configure SPI chip selects */ + + stm32_spidev_initialize(); +#endif +} + +/**************************************************************************** + * Name: board_late_initialize + * + * Description: + * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_late_initialize(). board_late_initialize() + * will be called immediately after up_initialize() is called and + * just before the initial application is started. This additional + * initialization phase may be used, for example, to initialize + * board-specific device drivers. + * + ****************************************************************************/ + +#ifdef CONFIG_BOARD_LATE_INITIALIZE +void board_late_initialize(void) +{ + int ret; + +#ifdef CONFIG_FS_PROCFS + /* Mount the procfs file system */ + + ret = nx_mount(NULL, STM32_PROCFS_MOUNTPOINT, "procfs", 0, NULL); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to mount procfs at %s: %d\n", + STM32_PROCFS_MOUNTPOINT, ret); + } +#endif + +#ifdef CONFIG_STM32_ROMFS + /* Mount the romfs partition */ + + ret = stm32_romfs_initialize(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to mount romfs at %s: %d\n", + CONFIG_STM32_ROMFS_MOUNTPOINT, ret); + } +#endif + +#ifdef CONFIG_DEV_GPIO + /* Register the GPIO driver */ + + ret = stm32_gpio_initialize(); + if (ret < 0) + { + syslog(LOG_ERR, "Failed to initialize GPIO Driver: %d\n", ret); + return; + } +#endif + +#if !defined(CONFIG_ARCH_LEDS) && defined(CONFIG_USERLED_LOWER) + /* Register the LED driver */ + + ret = userled_lower_initialize(LED_DRIVER_PATH); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: userled_lower_initialize() failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_ADC + /* Initialize ADC and register the ADC driver. */ + + ret = stm32_adc_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_adc_setup failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_STM32_BBSRAM + /* Initialize battery-backed RAM */ + + stm32_bbsram_int(); +#endif + +#if defined(CONFIG_FAT_DMAMEMORY) + if (stm32_dma_alloc_init() < 0) + { + syslog(LOG_ERR, "DMA alloc FAILED"); + } +#endif + +#if defined(CONFIG_NUCLEO_SPI_TEST) + /* Create SPI interfaces */ + + ret = stm32_spidev_bus_test(); + if (ret != OK) + { + syslog(LOG_ERR, "ERROR: Failed to initialize SPI interfaces: %d\n", + ret); + return; + } +#endif + +#if defined(CONFIG_MMCSD) + /* Initialize the SDIO block driver */ + + ret = stm32_sdio_initialize(); + if (ret != OK) + { + ferr("ERROR: Failed to initialize MMC/SD driver: %d\n", ret); + return; + } +#endif + +#if defined(CONFIG_PWM) + /* Initialize PWM and register the PWM device */ + + ret = stm32_pwm_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_pwm_setup() failed: %d\n", ret); + } +#endif + +#if defined(CONFIG_I2C) && defined(CONFIG_SYSTEM_I2CTOOL) + stm32_i2c_register(1); +#endif + +#ifdef CONFIG_SENSORS_AMG88XX + board_amg88xx_initialize(1); +#endif + + UNUSED(ret); +} +#endif diff --git a/boards/arm/stm32f4/nucleo-f429zi/src/stm32_buttons.c b/boards/arm/stm32f4/nucleo-f429zi/src/stm32_buttons.c new file mode 100644 index 0000000000000..26101a63eb997 --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f429zi/src/stm32_buttons.c @@ -0,0 +1,110 @@ +/**************************************************************************** + * boards/arm/stm32f4/nucleo-f429zi/src/stm32_buttons.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include + +#include + +#include "stm32_gpio.h" +#include "nucleo-144.h" + +#ifdef CONFIG_ARCH_BUTTONS + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_button_initialize + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. + * + ****************************************************************************/ + +uint32_t board_button_initialize(void) +{ + stm32_configgpio(GPIO_BTN_USER); + return NUM_BUTTONS; +} + +/**************************************************************************** + * Name: board_buttons + ****************************************************************************/ + +uint32_t board_buttons(void) +{ + return stm32_gpioread(GPIO_BTN_USER) ? 1 : 0; +} + +/**************************************************************************** + * Button support. + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current + * state of all buttons or board_button_irq() may be called to register + * button interrupt handlers. + * + * After board_button_initialize() has been called, board_buttons() + * may be called to collect the state of all buttons. board_buttons() + * returns an 32-bit bit set with each bit associated with a button. + * See the BUTTON_*_BIT definitions in board.h for the meaning of each + * bit. + * + * board_button_irq() may be called to register an interrupt handler that + * will be called when a button is depressed or released. The ID value + * is a button enumeration value that uniquely identifies a button + * resource. See the BUTTON_* definitions in board.h for the meaning of + * enumeration value. + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_IRQBUTTONS +int board_button_irq(int id, xcpt_t irqhandler, void *arg) +{ + int ret = -EINVAL; + + if (id == BUTTON_USER) + { + ret = stm32_gpiosetevent(GPIO_BTN_USER, + true, true, true, + irqhandler, arg); + } + + return ret; +} +#endif +#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/stm32/nucleo-f429zi/src/stm32_dma_alloc.c b/boards/arm/stm32f4/nucleo-f429zi/src/stm32_dma_alloc.c similarity index 98% rename from boards/arm/stm32/nucleo-f429zi/src/stm32_dma_alloc.c rename to boards/arm/stm32f4/nucleo-f429zi/src/stm32_dma_alloc.c index c11a26e3adb8c..0cc0979f5780e 100644 --- a/boards/arm/stm32/nucleo-f429zi/src/stm32_dma_alloc.c +++ b/boards/arm/stm32f4/nucleo-f429zi/src/stm32_dma_alloc.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f429zi/src/stm32_dma_alloc.c + * boards/arm/stm32f4/nucleo-f429zi/src/stm32_dma_alloc.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f4/nucleo-f429zi/src/stm32_gpio.c b/boards/arm/stm32f4/nucleo-f429zi/src/stm32_gpio.c new file mode 100644 index 0000000000000..b58bf7c7a5c1f --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f429zi/src/stm32_gpio.c @@ -0,0 +1,323 @@ +/**************************************************************************** + * boards/arm/stm32f4/nucleo-f429zi/src/stm32_gpio.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include +#include + +#include + +#include "chip.h" +#include "stm32_gpio.h" +#include "nucleo-144.h" + +#if defined(CONFIG_DEV_GPIO) && !defined(CONFIG_GPIO_LOWER_HALF) + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +struct stm32gpio_dev_s +{ + struct gpio_dev_s gpio; + uint8_t id; +}; + +struct stm32gpint_dev_s +{ + struct stm32gpio_dev_s stm32gpio; + pin_interrupt_t callback; +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +static int gpin_read(struct gpio_dev_s *dev, bool *value); +static int gpout_read(struct gpio_dev_s *dev, bool *value); +static int gpout_write(struct gpio_dev_s *dev, bool value); +static int gpint_read(struct gpio_dev_s *dev, bool *value); +static int gpint_attach(struct gpio_dev_s *dev, + pin_interrupt_t callback); +static int gpint_enable(struct gpio_dev_s *dev, bool enable); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static const struct gpio_operations_s gpin_ops = +{ + .go_read = gpin_read, + .go_write = NULL, + .go_attach = NULL, + .go_enable = NULL, +}; + +static const struct gpio_operations_s gpout_ops = +{ + .go_read = gpout_read, + .go_write = gpout_write, + .go_attach = NULL, + .go_enable = NULL, +}; + +static const struct gpio_operations_s gpint_ops = +{ + .go_read = gpint_read, + .go_write = NULL, + .go_attach = gpint_attach, + .go_enable = gpint_enable, +}; + +#if BOARD_NGPIOIN > 0 +/* This array maps the GPIO pins used as INPUT */ + +static const uint32_t g_gpioinputs[BOARD_NGPIOIN] = +{ + GPIO_IN1, +}; + +static struct stm32gpio_dev_s g_gpin[BOARD_NGPIOIN]; +#endif + +#if BOARD_NGPIOOUT +/* This array maps the GPIO pins used as OUTPUT */ + +static const uint32_t g_gpiooutputs[BOARD_NGPIOOUT] = +{ + GPIO_OUT1, +}; + +static struct stm32gpio_dev_s g_gpout[BOARD_NGPIOOUT]; +#endif + +#if BOARD_NGPIOINT > 0 +/* This array maps the GPIO pins used as INTERRUPT INPUTS */ + +static const uint32_t g_gpiointinputs[BOARD_NGPIOINT] = +{ + GPIO_INT1, +}; + +static struct stm32gpint_dev_s g_gpint[BOARD_NGPIOINT]; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +static int stm32gpio_interrupt(int irq, void *context, void *arg) +{ + struct stm32gpint_dev_s *stm32gpint = + (struct stm32gpint_dev_s *)arg; + + DEBUGASSERT(stm32gpint != NULL && stm32gpint->callback != NULL); + gpioinfo("Interrupt! callback=%p\n", stm32gpint->callback); + + stm32gpint->callback(&stm32gpint->stm32gpio.gpio, + stm32gpint->stm32gpio.id); + return OK; +} + +static int gpin_read(struct gpio_dev_s *dev, bool *value) +{ + struct stm32gpio_dev_s *stm32gpio = + (struct stm32gpio_dev_s *)dev; + + DEBUGASSERT(stm32gpio != NULL && value != NULL); + DEBUGASSERT(stm32gpio->id < BOARD_NGPIOIN); + gpioinfo("Reading...\n"); + + *value = stm32_gpioread(g_gpioinputs[stm32gpio->id]); + return OK; +} + +static int gpout_read(struct gpio_dev_s *dev, bool *value) +{ + struct stm32gpio_dev_s *stm32gpio = + (struct stm32gpio_dev_s *)dev; + + DEBUGASSERT(stm32gpio != NULL && value != NULL); + DEBUGASSERT(stm32gpio->id < BOARD_NGPIOOUT); + gpioinfo("Reading...\n"); + + *value = stm32_gpioread(g_gpiooutputs[stm32gpio->id]); + return OK; +} + +static int gpout_write(struct gpio_dev_s *dev, bool value) +{ + struct stm32gpio_dev_s *stm32gpio = + (struct stm32gpio_dev_s *)dev; + + DEBUGASSERT(stm32gpio != NULL); + DEBUGASSERT(stm32gpio->id < BOARD_NGPIOOUT); + gpioinfo("Writing %d\n", (int)value); + + stm32_gpiowrite(g_gpiooutputs[stm32gpio->id], value); + return OK; +} + +static int gpint_read(struct gpio_dev_s *dev, bool *value) +{ + struct stm32gpint_dev_s *stm32gpint = + (struct stm32gpint_dev_s *)dev; + + DEBUGASSERT(stm32gpint != NULL && value != NULL); + DEBUGASSERT(stm32gpint->stm32gpio.id < BOARD_NGPIOINT); + gpioinfo("Reading int pin...\n"); + + *value = stm32_gpioread(g_gpiointinputs[stm32gpint->stm32gpio.id]); + return OK; +} + +static int gpint_attach(struct gpio_dev_s *dev, + pin_interrupt_t callback) +{ + struct stm32gpint_dev_s *stm32gpint = + (struct stm32gpint_dev_s *)dev; + + gpioinfo("Attaching the callback\n"); + + /* Make sure the interrupt is disabled */ + + stm32_gpiosetevent(g_gpiointinputs[stm32gpint->stm32gpio.id], false, + false, false, NULL, NULL); + + gpioinfo("Attach %p\n", callback); + stm32gpint->callback = callback; + return OK; +} + +static int gpint_enable(struct gpio_dev_s *dev, bool enable) +{ + struct stm32gpint_dev_s *stm32gpint = + (struct stm32gpint_dev_s *)dev; + + if (enable) + { + if (stm32gpint->callback != NULL) + { + gpioinfo("Enabling the interrupt\n"); + + /* Configure the interrupt for rising edge */ + + stm32_gpiosetevent(g_gpiointinputs[stm32gpint->stm32gpio.id], + true, false, false, stm32gpio_interrupt, + &g_gpint[stm32gpint->stm32gpio.id]); + } + } + else + { + gpioinfo("Disable the interrupt\n"); + stm32_gpiosetevent(g_gpiointinputs[stm32gpint->stm32gpio.id], + false, false, false, NULL, NULL); + } + + return OK; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_gpio_initialize + * + * Description: + * Initialize GPIO drivers for use with /apps/examples/gpio + * + ****************************************************************************/ + +int stm32_gpio_initialize(void) +{ + int i; + int pincount = 0; + +#if BOARD_NGPIOIN > 0 + for (i = 0; i < BOARD_NGPIOIN; i++) + { + /* Setup and register the GPIO pin */ + + g_gpin[i].gpio.gp_pintype = GPIO_INPUT_PIN; + g_gpin[i].gpio.gp_ops = &gpin_ops; + g_gpin[i].id = i; + gpio_pin_register(&g_gpin[i].gpio, pincount); + + /* Configure the pin that will be used as input */ + + stm32_configgpio(g_gpioinputs[i]); + + pincount++; + } +#endif + +#if BOARD_NGPIOOUT > 0 + for (i = 0; i < BOARD_NGPIOOUT; i++) + { + /* Setup and register the GPIO pin */ + + g_gpout[i].gpio.gp_pintype = GPIO_OUTPUT_PIN; + g_gpout[i].gpio.gp_ops = &gpout_ops; + g_gpout[i].id = i; + gpio_pin_register(&g_gpout[i].gpio, pincount); + + /* Configure the pin that will be used as output */ + + stm32_gpiowrite(g_gpiooutputs[i], 0); + stm32_configgpio(g_gpiooutputs[i]); + + pincount++; + } +#endif + +#if BOARD_NGPIOINT > 0 + for (i = 0; i < BOARD_NGPIOINT; i++) + { + /* Setup and register the GPIO pin */ + + g_gpint[i].stm32gpio.gpio.gp_pintype = GPIO_INTERRUPT_PIN; + g_gpint[i].stm32gpio.gpio.gp_ops = &gpint_ops; + g_gpint[i].stm32gpio.id = i; + gpio_pin_register(&g_gpint[i].stm32gpio.gpio, pincount); + + /* Configure the pin that will be used as interrupt input */ + + stm32_configgpio(g_gpiointinputs[i]); + + pincount++; + } +#endif + + return 0; +} +#endif /* CONFIG_DEV_GPIO && !CONFIG_GPIO_LOWER_HALF */ diff --git a/boards/arm/stm32f4/nucleo-f429zi/src/stm32_pwm.c b/boards/arm/stm32f4/nucleo-f429zi/src/stm32_pwm.c new file mode 100644 index 0000000000000..a7186ebdb7c6e --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f429zi/src/stm32_pwm.c @@ -0,0 +1,149 @@ +/**************************************************************************** + * boards/arm/stm32f4/nucleo-f429zi/src/stm32_pwm.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32_pwm.h" +#include "nucleo-144.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define HAVE_PWM 1 +#ifndef CONFIG_PWM +# undef HAVE_PWM +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_pwm_setup + * + * Description: + * Initialize PWM and register the PWM device. + * + ****************************************************************************/ + +int stm32_pwm_setup(void) +{ +#ifdef HAVE_PWM + static bool initialized = false; + struct pwm_lowerhalf_s *pwm; + int ret; + + /* Have we already initialized? */ + + if (!initialized) + { + /* Call stm32_pwminitialize() to get an instance of the PWM interface */ + +#if defined(CONFIG_STM32_TIM1_PWM) + pwm = stm32_pwminitialize(1); + if (!pwm) + { + aerr("ERROR: Failed to get the STM32F4 PWM lower half\n"); + return -ENODEV; + } + + ret = pwm_register("/dev/pwm0", pwm); + if (ret < 0) + { + aerr("ERROR: pwm_register failed: %d\n", ret); + return ret; + } +#endif + +#if defined(CONFIG_STM32_TIM2_PWM) + pwm = stm32_pwminitialize(2); + if (!pwm) + { + aerr("ERROR: Failed to get the STM32F4 PWM lower half\n"); + return -ENODEV; + } + + ret = pwm_register("/dev/pwm1", pwm); + if (ret < 0) + { + aerr("ERROR: pwm_register failed: %d\n", ret); + return ret; + } +#endif + +#if defined(CONFIG_STM32_TIM3_PWM) + pwm = stm32_pwminitialize(3); + if (!pwm) + { + aerr("ERROR: Failed to get the STM32F4 PWM lower half\n"); + return -ENODEV; + } + + ret = pwm_register("/dev/pwm2", pwm); + if (ret < 0) + { + aerr("ERROR: pwm_register failed: %d\n", ret); + return ret; + } +#endif + +#if defined(CONFIG_STM32_TIM4_PWM) + pwm = stm32_pwminitialize(4); + if (!pwm) + { + aerr("ERROR: Failed to get the STM32F4 PWM lower half\n"); + return -ENODEV; + } + + ret = pwm_register("/dev/pwm3", pwm); + if (ret < 0) + { + aerr("ERROR: pwm_register failed: %d\n", ret); + return ret; + } + +#endif + /* Now we are initialized */ + + initialized = true; + } + + return OK; +#else + return -ENODEV; +#endif +} diff --git a/boards/arm/stm32f4/nucleo-f429zi/src/stm32_romfs.h b/boards/arm/stm32f4/nucleo-f429zi/src/stm32_romfs.h new file mode 100644 index 0000000000000..2e8f7f643cb82 --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f429zi/src/stm32_romfs.h @@ -0,0 +1,63 @@ +/**************************************************************************** + * boards/arm/stm32f4/nucleo-f429zi/src/stm32_romfs.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_STM32F4_NUCLEOF429ZI_SRC_STM32_ROMFS_H +#define __BOARDS_ARM_STM32F4_NUCLEOF429ZI_SRC_STM32_ROMFS_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#ifdef CONFIG_STM32_ROMFS + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define ROMFS_SECTOR_SIZE 64 + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_romfs_initialize + * + * Description: + * Registers built-in ROMFS image as block device and mounts it. + * + * Returned Value: + * Zero (OK) on success, a negated errno value on error. + * + * Assumptions/Limitations: + * Memory addresses [romfs_data_begin .. romfs_data_end) should contain + * ROMFS volume data, as included in the assembly snippet above (l. 84). + * + ****************************************************************************/ + +int stm32_romfs_initialize(void); + +#endif /* CONFIG_STM32_ROMFS */ + +#endif /* __BOARDS_ARM_STM32F4_NUCLEOF429ZI_SRC_STM32_ROMFS_H */ diff --git a/boards/arm/stm32f4/nucleo-f429zi/src/stm32_sdio.c b/boards/arm/stm32f4/nucleo-f429zi/src/stm32_sdio.c new file mode 100644 index 0000000000000..fd8a1dca33e1b --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f429zi/src/stm32_sdio.c @@ -0,0 +1,163 @@ +/**************************************************************************** + * boards/arm/stm32f4/nucleo-f429zi/src/stm32_sdio.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include + +#include "chip.h" +#include "nucleo-144.h" +#include "stm32_gpio.h" +#include "stm32_sdmmc.h" + +#ifdef CONFIG_MMCSD + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* Card detections requires card support and a card detection GPIO */ + +#define HAVE_NCD 1 +#if !defined(GPIO_SDMMC1_NCD) +# undef HAVE_NCD +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static struct sdio_dev_s *g_sdio_dev; +#ifdef HAVE_NCD +static bool g_sd_inserted; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_ncd_interrupt + * + * Description: + * Card detect interrupt handler. + * + ****************************************************************************/ + +#ifdef HAVE_NCD +static int stm32_ncd_interrupt(int irq, void *context) +{ + bool present; + + present = !stm32_gpioread(GPIO_SDMMC1_NCD); + if (g_sdio_dev && present != g_sd_inserted) + { + sdio_mediachange(g_sdio_dev, present); + g_sd_inserted = present; + } + + return OK; +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_sdio_initialize + * + * Description: + * Initialize SDIO-based MMC/SD card support + * + ****************************************************************************/ + +int stm32_sdio_initialize(void) +{ + int ret; + +#ifdef HAVE_NCD + /* Configure the card detect GPIO */ + + stm32_configgpio(GPIO_SDMMC1_NCD); + + /* Register an interrupt handler for the card detect pin */ + + stm32_gpiosetevent(GPIO_SDMMC1_NCD, true, true, true, + stm32_ncd_interrupt, NULL); +#endif + + /* Mount the SDIO-based MMC/SD block driver + * First, get an instance of the SDIO interface + */ + + finfo("Initializing SDIO slot %d\n", SDIO_SLOTNO); + + g_sdio_dev = sdio_initialize(SDIO_SLOTNO); + if (!g_sdio_dev) + { + ferr("ERROR: Failed to initialize SDIO slot %d\n", SDIO_SLOTNO); + return -ENODEV; + } + + /* Now bind the SDIO interface to the MMC/SD driver */ + + finfo("Bind SDIO to the MMC/SD driver, minor=%d\n", SDIO_MINOR); + + ret = mmcsd_slotinitialize(SDIO_MINOR, g_sdio_dev); + if (ret != OK) + { + ferr("ERROR: Failed to bind SDIO to the MMC/SD driver: %d\n", ret); + return ret; + } + + finfo("Successfully bound SDIO to the MMC/SD driver\n"); + +#ifdef HAVE_NCD + /* Use SD card detect pin to check if a card is g_sd_inserted */ + + g_sd_inserted = !stm32_gpioread(GPIO_SDMMC1_NCD); + finfo("Card detect : %d\n", g_sd_inserted); + + sdio_mediachange(g_sdio_dev, g_sd_inserted); +#else + /* Assume that the SD card is inserted. What choice do we have? */ + + sdio_mediachange(g_sdio_dev, true); +#endif + + return OK; +} + +#endif /* HAVE_SDIO */ diff --git a/boards/arm/stm32f4/nucleo-f429zi/src/stm32_spi.c b/boards/arm/stm32f4/nucleo-f429zi/src/stm32_spi.c new file mode 100644 index 0000000000000..fa7a2cc7519f8 --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f429zi/src/stm32_spi.c @@ -0,0 +1,496 @@ +/**************************************************************************** + * boards/arm/stm32f4/nucleo-f429zi/src/stm32_spi.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include + +#include +#include + +#include "arm_internal.h" +#include "chip.h" +#include "stm32_gpio.h" +#include "stm32_spi.h" + +#include "nucleo-144.h" + +#if defined(CONFIG_SPI) + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#if defined(CONFIG_NUCLEO_SPI1_TEST) +# if defined(CONFIG_NUCLEO_SPI1_TEST_MODE0) +# define CONFIG_NUCLEO_SPI1_TEST_MODE SPIDEV_MODE0 +# elif defined(CONFIG_NUCLEO_SPI1_TEST_MODE1) +# define CONFIG_NUCLEO_SPI1_TEST_MODE SPIDEV_MODE1 +# elif defined(CONFIG_NUCLEO_SPI1_TEST_MODE2) +# define CONFIG_NUCLEO_SPI1_TEST_MODE SPIDEV_MODE2 +# elif defined(CONFIG_NUCLEO_SPI1_TEST_MODE3) +# define CONFIG_NUCLEO_SPI1_TEST_MODE SPIDEV_MODE3 +# else +# error "No CONFIG_NUCLEO_SPI1_TEST_MODEx defined" +# endif +#endif + +#if defined(CONFIG_NUCLEO_SPI2_TEST) +# if defined(CONFIG_NUCLEO_SPI2_TEST_MODE0) +# define CONFIG_NUCLEO_SPI2_TEST_MODE SPIDEV_MODE0 +# elif defined(CONFIG_NUCLEO_SPI2_TEST_MODE1) +# define CONFIG_NUCLEO_SPI2_TEST_MODE SPIDEV_MODE1 +# elif defined(CONFIG_NUCLEO_SPI2_TEST_MODE2) +# define CONFIG_NUCLEO_SPI2_TEST_MODE SPIDEV_MODE2 +# elif defined(CONFIG_NUCLEO_SPI2_TEST_MODE3) +# define CONFIG_NUCLEO_SPI2_TEST_MODE SPIDEV_MODE3 +# else +# error "No CONFIG_NUCLEO_SPI2_TEST_MODEx defined" +# endif +#endif + +#if defined(CONFIG_NUCLEO_SPI3_TEST) +# if defined(CONFIG_NUCLEO_SPI3_TEST_MODE0) +# define CONFIG_NUCLEO_SPI3_TEST_MODE SPIDEV_MODE0 +# elif defined(CONFIG_NUCLEO_SPI3_TEST_MODE1) +# define CONFIG_NUCLEO_SPI3_TEST_MODE SPIDEV_MODE1 +# elif defined(CONFIG_NUCLEO_SPI3_TEST_MODE2) +# define CONFIG_NUCLEO_SPI3_TEST_MODE SPIDEV_MODE2 +# elif defined(CONFIG_NUCLEO_SPI3_TEST_MODE3) +# define CONFIG_NUCLEO_SPI3_TEST_MODE SPIDEV_MODE3 +# else +# error "No CONFIG_NUCLEO_SPI3_TEST_MODEx defined" +# endif +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#if defined(CONFIG_STM32_SPI1) +static const uint32_t g_spi1gpio[] = +{ +# if defined(GPIO_SPI1_CS0) + GPIO_SPI1_CS0, +# else + 0, +# endif +# if defined(GPIO_SPI1_CS1) + GPIO_SPI1_CS1, +# else + 0, +# endif +# if defined(GPIO_SPI1_CS2) + GPIO_SPI1_CS2, +# else + 0, +# endif +# if defined(GPIO_SPI1_CS3) + GPIO_SPI1_CS3 +# else + 0 +# endif +}; +#endif + +#if defined(CONFIG_STM32_SPI2) +static const uint32_t g_spi2gpio[] = +{ +# if defined(GPIO_SPI2_CS0) + GPIO_SPI2_CS0, +# else + 0, +# endif +# if defined(GPIO_SPI2_CS1) + GPIO_SPI2_CS1, +# else + 0, +# endif +# if defined(GPIO_SPI2_CS2) + GPIO_SPI2_CS2, +# else + 0, +# endif +# if defined(GPIO_SPI2_CS3) + GPIO_SPI2_CS3 +# else + 0 +# endif +}; +#endif + +#if defined(CONFIG_STM32_SPI3) +static const uint32_t g_spi3gpio[] = +{ +# if defined(GPIO_SPI3_CS0) + GPIO_SPI3_CS0, +# else + 0, +# endif +# if defined(GPIO_SPI3_CS1) + GPIO_SPI3_CS1, +# else + 0, +# endif +# if defined(GPIO_SPI3_CS2) + GPIO_SPI3_CS2, +# else + 0, +# endif +# if defined(GPIO_SPI3_CS3) + GPIO_SPI3_CS3 +# else + 0 +# endif +}; +#endif + +#if defined(CONFIG_NUCLEO_SPI_TEST) +# if defined(CONFIG_STM32_SPI1) +struct spi_dev_s *spi1; +# endif +# if defined(CONFIG_STM32_SPI2) +struct spi_dev_s *spi2; +# endif +# if defined(CONFIG_STM32_SPI3) +struct spi_dev_s *spi3; +# endif +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_spidev_initialize + * + * Description: + * Called to configure SPI chip select GPIO pins for the Nucleo-144 board. + * + ****************************************************************************/ + +void weak_function stm32_spidev_initialize(void) +{ + /* Configure SPI CS GPIO for output */ + +#if defined(CONFIG_STM32_SPI1) + for (int i = 0; i < nitems(g_spi1gpio); i++) + { + if (g_spi1gpio[i] != 0) + { + stm32_configgpio(g_spi1gpio[i]); + } + } +#endif + +#if defined(CONFIG_STM32_SPI2) + for (int i = 0; i < nitems(g_spi2gpio); i++) + { + if (g_spi2gpio[i] != 0) + { + stm32_configgpio(g_spi2gpio[i]); + } + } +#endif + +#if defined(CONFIG_STM32_SPI3) + for (int i = 0; i < nitems(g_spi3gpio); i++) + { + if (g_spi3gpio[i] != 0) + { + stm32_configgpio(g_spi3gpio[i]); + } + } +#endif +} + +/**************************************************************************** + * Name: stm32_spi1/2/3/4/5/6select and stm32_spi1/2/3/4/5/6status + * + * Description: + * The external functions, stm32_spi1/2/3/4/5/6select and + * stm32_spi1/2/3/4/5/6status must be provided by board-specific logic. + * They are implementations of the select and status methods of + * the SPI interface defined by struct spi_ops_s + * (see include/nuttx/spi/spi.h). All other methods + * (including stm32_spibus_initialize()) are provided by common + * STM32 logic. To use this common SPI logic on your board: + * + * 1. Provide logic in stm32_boardinitialize() to configure SPI chip select + * pins. + * 2. Provide stm32_spi1/2/3/4/5/6select() and stm32_spi1/2/3/4/5/6status() + * functions in your board-specific logic. These functions will + * perform chip selection and status operations using GPIOs in + * the way your board is configured. + * 3. Add a calls to stm32_spibus_initialize() in your low level + * application initialization logic + * 4. The handle returned by stm32_spibus_initialize() may then be + * used to bind the SPI driver to higher level logic (e.g., calling + * mmcsd_spislotinitialize(), for example, will bind the SPI + * driver to the SPI MMC/SD driver). + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_SPI1 +void stm32_spi1select(struct spi_dev_s *dev, + uint32_t devid, bool selected) +{ + uint32_t index = SPIDEVID_INDEX(devid); + + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); + + if (g_spi1gpio[index] != 0) + { + stm32_gpiowrite(g_spi1gpio[index], !selected); + } +} + +uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} +#endif + +#ifdef CONFIG_STM32_SPI2 +void stm32_spi2select(struct spi_dev_s *dev, + uint32_t devid, bool selected) +{ + uint32_t index = SPIDEVID_INDEX(devid); + + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); + + if (g_spi2gpio[index] != 0) + { + stm32_gpiowrite(g_spi2gpio[index], !selected); + } +} + +uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} +#endif + +#ifdef CONFIG_STM32_SPI3 +void stm32_spi3select(struct spi_dev_s *dev, + uint32_t devid, bool selected) +{ + uint32_t index = SPIDEVID_INDEX(devid); + + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); + + if (g_spi3gpio[index] != 0) + { + stm32_gpiowrite(g_spi3gpio[index], !selected); + } +} + +uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} +#endif + +#ifdef CONFIG_STM32_SPI4 +void stm32_spi4select(struct spi_dev_s *dev, + uint32_t devid, bool selected) +{ + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); +} + +uint8_t stm32_spi4status(struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} +#endif + +#ifdef CONFIG_STM32_SPI5 +void stm32_spi5select(struct spi_dev_s *dev, + uint32_t devid, bool selected) +{ + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); +} + +uint8_t stm32_spi5status(struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} +#endif + +#ifdef CONFIG_STM32_SPI6 +void stm32_spi6select(struct spi_dev_s *dev, + uint32_t devid, bool selected) +{ + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); +} + +uint8_t stm32_spi6status(struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} +#endif + +/**************************************************************************** + * Name: stm32_spi1/2/3/4/5/6cmddata + * + * Description: + * Set or clear the SH1101A A0 or SD1306 D/C n bit to select data (true) + * or command (false). This function must be provided by platform-specific + * logic. This is an implementation of the cmddata method of the SPI + * interface defined by struct spi_ops_s (see include/nuttx/spi/spi.h). + * + * Input Parameters: + * + * spi - SPI device that controls the bus the device that requires the CMD/ + * DATA selection. + * devid - If there are multiple devices on the bus, this selects which one + * to select cmd or data. NOTE: This design restricts, for example, + * one one SPI display per SPI bus. + * cmd - true: select command; false: select data + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_SPI_CMDDATA +#ifdef CONFIG_STM32_SPI1 +int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) +{ + return -ENODEV; +} +#endif + +#ifdef CONFIG_STM32_SPI2 +int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) +{ + return -ENODEV; +} +#endif + +#ifdef CONFIG_STM32_SPI3 +int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) +{ + return -ENODEV; +} +#endif + +#ifdef CONFIG_STM32_SPI4 +int stm32_spi4cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) +{ + return -ENODEV; +} +#endif + +#ifdef CONFIG_STM32_SPI5 +int stm32_spi5cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) +{ + return -ENODEV; +} +#endif + +#ifdef CONFIG_STM32_SPI6 +int stm32_spi6cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) +{ + return -ENODEV; +} +#endif + +#endif /* CONFIG_SPI_CMDDATA */ + +#if defined(CONFIG_NUCLEO_SPI_TEST) +int stm32_spidev_bus_test(void) +{ + /* Configure and test SPI */ + + uint8_t *tx = (uint8_t *)CONFIG_NUCLEO_SPI_TEST_MESSAGE; + +#if defined(CONFIG_NUCLEO_SPI1_TEST) + spi1 = stm32_spibus_initialize(1); + + if (!spi1) + { + syslog(LOG_ERR, "ERROR Failed to initialize SPI port 1\n"); + return -ENODEV; + } + + /* Default SPI1 to NUCLEO_SPI1_FREQ and mode */ + + SPI_SETFREQUENCY(spi1, CONFIG_NUCLEO_SPI1_TEST_FREQ); + SPI_SETBITS(spi1, CONFIG_NUCLEO_SPI1_TEST_BITS); + SPI_SETMODE(spi1, CONFIG_NUCLEO_SPI1_TEST_MODE); + SPI_EXCHANGE(spi1, tx, NULL, nitems(CONFIG_NUCLEO_SPI_TEST_MESSAGE)); +#endif + +#if defined(CONFIG_NUCLEO_SPI2_TEST) + spi2 = stm32_spibus_initialize(2); + + if (!spi2) + { + syslog(LOG_ERR, "ERROR Failed to initialize SPI port 2\n"); + return -ENODEV; + } + + /* Default SPI2 to NUCLEO_SPI2_FREQ and mode */ + + SPI_SETFREQUENCY(spi2, CONFIG_NUCLEO_SPI2_TEST_FREQ); + SPI_SETBITS(spi2, CONFIG_NUCLEO_SPI2_TEST_BITS); + SPI_SETMODE(spi2, CONFIG_NUCLEO_SPI2_TEST_MODE); + SPI_EXCHANGE(spi2, tx, NULL, nitems(CONFIG_NUCLEO_SPI_TEST_MESSAGE)); +#endif + +#if defined(CONFIG_NUCLEO_SPI3_TEST) + spi3 = stm32_spibus_initialize(3); + + if (!spi3) + { + syslog(LOG_ERR, "ERROR Failed to initialize SPI port 2\n"); + return -ENODEV; + } + + /* Default SPI3 to NUCLEO_SPI3_FREQ and mode */ + + SPI_SETFREQUENCY(spi3, CONFIG_NUCLEO_SPI3_TEST_FREQ); + SPI_SETBITS(spi3, CONFIG_NUCLEO_SPI3_TEST_BITS); + SPI_SETMODE(spi3, CONFIG_NUCLEO_SPI3_TEST_MODE); + SPI_EXCHANGE(spi3, tx, NULL, nitems(CONFIG_NUCLEO_SPI_TEST_MESSAGE)); +#endif + + return OK; +} +#endif /* NUCLEO_SPI_TEST */ +#endif /* defined(CONFIG_SPI) */ diff --git a/boards/arm/stm32f4/nucleo-f429zi/src/stm32_usb.c b/boards/arm/stm32f4/nucleo-f429zi/src/stm32_usb.c new file mode 100644 index 0000000000000..47d002de4cc52 --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f429zi/src/stm32_usb.c @@ -0,0 +1,322 @@ +/**************************************************************************** + * boards/arm/stm32f4/nucleo-f429zi/src/stm32_usb.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include "arm_internal.h" +#include "chip.h" +#include "stm32_gpio.h" +#include "stm32_otg.h" +#include "nucleo-144.h" + +#ifdef CONFIG_STM32_OTGFS + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#if defined(CONFIG_USBDEV) || defined(CONFIG_USBHOST) +# define HAVE_USB 1 +#else +# warning "CONFIG_STM32_OTGFS is enabled but neither CONFIG_USBDEV nor CONFIG_USBHOST" +# undef HAVE_USB +#endif + +#ifndef CONFIG_NUCLEO144_USBHOST_PRIO +# define CONFIG_NUCLEO144_USBHOST_PRIO 100 +#endif + +#ifndef CONFIG_NUCLEO_USBHOST_STACKSIZE +# define CONFIG_NUCLEO_USBHOST_STACKSIZE 1024 +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +static struct usbhost_connection_s *g_usbconn; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: usbhost_waiter + * + * Description: + * Wait for USB devices to be connected. + * + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +static int usbhost_waiter(int argc, char *argv[]) +{ + struct usbhost_hubport_s *hport; + + uinfo("Running\n"); + for (; ; ) + { + /* Wait for the device to change state */ + + DEBUGVERIFY(CONN_WAIT(g_usbconn, &hport)); + uinfo("%s\n", hport->connected ? "connected" : "disconnected"); + + /* Did we just become connected? */ + + if (hport->connected) + { + /* Yes.. enumerate the newly connected device */ + + CONN_ENUMERATE(g_usbconn, hport); + } + } + + /* Keep the compiler from complaining */ + + return 0; +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_usbinitialize + * + * Description: + * Called from stm32_usbinitialize very early in initialization + * to setup USB-related GPIO pins for the nucleo-144 board. + * + ****************************************************************************/ + +void stm32_usbinitialize(void) +{ + /* The OTG FS has an internal soft pull-up. + * No GPIO configuration is required + */ + + /* Configure the OTG FS VBUS sensing GPIO, + * Power On, and Overcurrent GPIOs + */ + +#ifdef CONFIG_STM32_OTGFS + stm32_configgpio(GPIO_OTGFS_VBUS); + stm32_configgpio(GPIO_OTGFS_PWRON); + stm32_configgpio(GPIO_OTGFS_OVER); +#endif +} + +/**************************************************************************** + * Name: stm32_usbhost_initialize + * + * Description: + * Called at application startup time to initialize the + * USB host functionality. This function will start a thread + * that will monitor for device connection/disconnection events. + * + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +int stm32_usbhost_initialize(void) +{ + int ret; + + /* First, register all of the class drivers needed to support the drivers + * that we care about: + */ + + uinfo("Register class drivers\n"); + +#ifdef CONFIG_USBHOST_HUB + /* Initialize USB hub class support */ + + ret = usbhost_hub_initialize(); + if (ret < 0) + { + uerr("ERROR: usbhost_hub_initialize failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_USBHOST_MSC + /* Register the USB mass storage class class */ + + ret = usbhost_msc_initialize(); + if (ret != OK) + { + uerr("ERROR: Failed to register the mass storage class: %d\n", ret); + } +#endif + +#ifdef CONFIG_USBHOST_CDCACM + /* Register the CDC/ACM serial class */ + + ret = usbhost_cdcacm_initialize(); + if (ret != OK) + { + uerr("ERROR: Failed to register the CDC/ACM serial class: %d\n", ret); + } +#endif + +#ifdef CONFIG_USBHOST_HIDKBD + /* Initialize the HID keyboard class */ + + ret = usbhost_kbdinit(); + if (ret != OK) + { + uerr("ERROR: Failed to register the HID keyboard class\n"); + } +#endif + +#ifdef CONFIG_USBHOST_HIDMOUSE + /* Initialize the HID mouse class */ + + ret = usbhost_mouse_init(); + if (ret != OK) + { + uerr("ERROR: Failed to register the HID mouse class\n"); + } +#endif + + /* Then get an instance of the USB host interface */ + + uinfo("Initialize USB host\n"); + g_usbconn = stm32_otgfshost_initialize(0); + if (g_usbconn) + { + /* Start a thread to handle device connection. */ + + uinfo("Start usbhost_waiter\n"); + + ret = kthread_create("usbhost", CONFIG_STM32F4DISCO_USBHOST_PRIO, + CONFIG_STM32F4DISCO_USBHOST_STACKSIZE, + usbhost_waiter, NULL); + return ret < 0 ? -ENOEXEC : OK; + } + + return -ENODEV; +} +#endif + +/**************************************************************************** + * Name: stm32_usbhost_vbusdrive + * + * Description: + * Enable/disable driving of VBUS 5V output. This function + * must be provided be each platform that implements the + * STM32 OTG FS host interface + * + * "On-chip 5 V VBUS generation is not supported. For this reason, + * a charge pump or, if 5 V are available on the application board, + * a basic power switch, must be added externally to drive the 5 V + * VBUS line. The external charge pump can be driven by any GPIO + * output. When the application decides to power on VBUS using + * the chosen GPIO, it must also set the port power bit in the host port + * control and status register (PPWR bit in OTG_FS_HPRT). + * + * "The application uses this field to control power to this port, + * and the core clears this bit on an overcurrent condition." + * + * Input Parameters: + * iface - For future growth to handle multiple USB host interface. + * Should be zero. + * enable - true: enable VBUS power; false: disable VBUS power + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +void stm32_usbhost_vbusdrive(int iface, bool enable) +{ + DEBUGASSERT(iface == 0); + + /* Set the Power Switch by driving the active low enable pin */ + + stm32_gpiowrite(GPIO_OTGFS_PWRON, !enable); +} +#endif + +/**************************************************************************** + * Name: stm32_setup_overcurrent + * + * Description: + * Setup to receive an interrupt-level callback if an + * overcurrent condition is detected. + * + * Input Parameters: + * handler - New overcurrent interrupt handler + * arg - The argument provided for the interrupt handler + * + * Returned Value: + * Zero (OK) is returned on success. Otherwise, a negated errno + * value is returned to indicate the nature of the failure. + * + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +int stm32_setup_overcurrent(xcpt_t handler, void *arg) +{ + return stm32_gpiosetevent(GPIO_OTGFS_OVER, true, true, true, handler, arg); +} +#endif + +/**************************************************************************** + * Name: stm32_usbsuspend + * + * Description: + * Board logic must provide the stm32_usbsuspend logic if the + * USBDEV driver is used. This function is called whenever the + * USB enters or leaves suspend mode. This is an opportunity + * for the board logic to shutdown clocks, power, etc. while the + * USB is suspended. + * + ****************************************************************************/ + +#ifdef CONFIG_USBDEV +void stm32_usbsuspend(struct usbdev_s *dev, bool resume) +{ + uinfo("resume: %d\n", resume); +} +#endif + +#endif /* CONFIG_STM32_OTGFS */ diff --git a/boards/arm/stm32f4/nucleo-f429zi/src/stm32_userleds.c b/boards/arm/stm32f4/nucleo-f429zi/src/stm32_userleds.c new file mode 100644 index 0000000000000..7677d7ba65c61 --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f429zi/src/stm32_userleds.c @@ -0,0 +1,128 @@ +/**************************************************************************** + * boards/arm/stm32f4/nucleo-f429zi/src/stm32_userleds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include + +#include +#include + +#include "stm32_gpio.h" +#include "nucleo-144.h" + +#ifndef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* This array maps an LED number to GPIO pin configuration and is indexed by + * BOARD_LED_ + */ + +static const uint32_t g_ledcfg[BOARD_NLEDS] = +{ + GPIO_LED_GREEN, + GPIO_LED_BLUE, + GPIO_LED_RED, +}; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_userled_initialize + * + * Description: + * If CONFIG_ARCH_LEDS is defined, then NuttX will control the on-board + * LEDs. If CONFIG_ARCH_LEDS is not defined, then the + * board_userled_initialize() is available to initialize the LED from user + * application logic. + * + ****************************************************************************/ + +uint32_t board_userled_initialize(void) +{ + int i; + + /* Configure LED1-3 GPIOs for output */ + + for (i = 0; i < nitems(g_ledcfg); i++) + { + stm32_configgpio(g_ledcfg[i]); + } + + return BOARD_NLEDS; +} + +/**************************************************************************** + * Name: board_userled + * + * Description: + * If CONFIG_ARCH_LEDS is defined, then NuttX will control the on-board + * LEDs. If CONFIG_ARCH_LEDS is not defined, then the board_userled() is + * available to control the LED from user application logic. + * + ****************************************************************************/ + +void board_userled(int led, bool ledon) +{ + if ((unsigned)led < nitems(g_ledcfg)) + { + stm32_gpiowrite(g_ledcfg[led], ledon); + } +} + +/**************************************************************************** + * Name: board_userled_all + * + * Description: + * If CONFIG_ARCH_LEDS is defined, then NuttX will control the on-board + * LEDs. If CONFIG_ARCH_LEDS is not defined, then the board_userled_all() + * is available to control the LED from user application logic. + * NOTE: since there is only a single LED on-board, this is function + * is not very useful. + * + ****************************************************************************/ + +void board_userled_all(uint32_t ledset) +{ + int i; + + /* Configure LED1-3 GPIOs for output */ + + for (i = 0; i < nitems(g_ledcfg); i++) + { + stm32_gpiowrite(g_ledcfg[i], (ledset & (1 << i)) != 0); + } +} + +#endif /* !CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32f4/nucleo-f446re/CMakeLists.txt b/boards/arm/stm32f4/nucleo-f446re/CMakeLists.txt new file mode 100644 index 0000000000000..4371e311a7bf9 --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f446re/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32f4/nucleo-f446re/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/arm/stm32f4/nucleo-f446re/Kconfig b/boards/arm/stm32f4/nucleo-f446re/Kconfig new file mode 100644 index 0000000000000..1007c8b531564 --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f446re/Kconfig @@ -0,0 +1,33 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# + +if ARCH_BOARD_NUCLEO_F446RE + +if SENSORS_QENCODER + +config NUCLEO_F446RE_QETIMER + int "Timer to use with QE encoder" + default 3 + +config NUCLEO_F446RE_QETIMER_TIM2_IHM08M1_MAP + bool "Use TIM2 QE pins to match IHM08M1 board pins" + default n + depends on STM32_TIM2_QE + +endif # SENSORS_QENCODER + +config NUCLEO_F446RE_AJOY_MINBUTTONS + bool "Minimal Joystick Buttons" + default STM32_USART1 + depends on INPUT_AJOYSTICK + ---help--- + The Itead Joystick shield supports analog X/Y position and up to 5 + buttons. Some of these buttons may conflict with other resources + (Button F, for example, conflicts with the default USART1 pin usage). + Selecting this option will return the number of buttons to the + minimal set: SELECT (joystick down), FIRE (BUTTON B), and JUMP + (BUTTON A). + +endif # ARCH_BOARD_NUCLEO_F446RE diff --git a/boards/arm/stm32f4/nucleo-f446re/configs/adc/defconfig b/boards/arm/stm32f4/nucleo-f446re/configs/adc/defconfig new file mode 100644 index 0000000000000..5b5f4de0bc0a4 --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f446re/configs/adc/defconfig @@ -0,0 +1,57 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_STM32_FLASH_PREFETCH is not set +CONFIG_ADC=y +CONFIG_ANALOG=y +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nucleo-f446re" +CONFIG_ARCH_BOARD_NUCLEO_F446RE=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F446R=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=8499 +CONFIG_BUILTIN=y +CONFIG_EXAMPLES_ADC=y +CONFIG_EXAMPLES_ADC_GROUPSIZE=2 +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=131072 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=14 +CONFIG_START_MONTH=10 +CONFIG_START_YEAR=2014 +CONFIG_STM32_ADC1=y +CONFIG_STM32_ADC1_DMA=y +CONFIG_STM32_ADC1_SAMPLE_FREQUENCY=1 +CONFIG_STM32_DMA2=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_TIM1=y +CONFIG_STM32_TIM1_ADC=y +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f4/nucleo-f446re/configs/can/defconfig b/boards/arm/stm32f4/nucleo-f446re/configs/can/defconfig new file mode 100644 index 0000000000000..bf16478bf0f30 --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f446re/configs/can/defconfig @@ -0,0 +1,58 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_STM32_FLASH_PREFETCH is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nucleo-f446re" +CONFIG_ARCH_BOARD_NUCLEO_F446RE=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F446R=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=8499 +CONFIG_BUILTIN=y +CONFIG_EXAMPLES_CAN=y +CONFIG_EXAMPLES_CAN_NMSGS=100 +CONFIG_EXAMPLES_CAN_WRITE=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=131072 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_SPI=y +CONFIG_START_DAY=14 +CONFIG_START_MONTH=10 +CONFIG_START_YEAR=2014 +CONFIG_STM32_CAN1=y +CONFIG_STM32_CAN2=y +CONFIG_STM32_CAN_TSEG1=13 +CONFIG_STM32_CAN_TSEG2=2 +CONFIG_STM32_CRC=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PWR=y +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f4/nucleo-f446re/configs/cansock/defconfig b/boards/arm/stm32f4/nucleo-f446re/configs/cansock/defconfig new file mode 100644 index 0000000000000..e549ee92ce967 --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f446re/configs/cansock/defconfig @@ -0,0 +1,72 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_NET_ETHERNET is not set +# CONFIG_NET_IPv4 is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_STM32_FLASH_PREFETCH is not set +CONFIG_ALLOW_BSD_COMPONENTS=y +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nucleo-f446re" +CONFIG_ARCH_BOARD_NUCLEO_F446RE=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F446R=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=8499 +CONFIG_BUILTIN=y +CONFIG_CANUTILS_CANDUMP=y +CONFIG_CANUTILS_CANSEND=y +CONFIG_CANUTILS_LIBCANUTILS=y +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_FS_PROCFS=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_IOB_BUFSIZE=16 +CONFIG_IOB_NBUFFERS=1024 +CONFIG_LINE_MAX=64 +CONFIG_NET=y +CONFIG_NETDEV_IFINDEX=y +CONFIG_NETDEV_LATEINIT=y +CONFIG_NET_CAN=y +CONFIG_NET_CAN_EXTID=y +CONFIG_NET_SOCKOPTS=y +CONFIG_NET_STATISTICS=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_DISABLE_IFUPDOWN=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=131072 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_LPWORK=y +CONFIG_SCHED_LPWORKPRIORITY=176 +CONFIG_SCHED_WAITPID=y +CONFIG_SPI=y +CONFIG_START_DAY=14 +CONFIG_START_MONTH=10 +CONFIG_START_YEAR=2014 +CONFIG_STM32_CAN1=y +CONFIG_STM32_CAN_SOCKET=y +CONFIG_STM32_CAN_TSEG1=13 +CONFIG_STM32_CAN_TSEG2=2 +CONFIG_STM32_CRC=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PWR=y +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f4/nucleo-f446re/configs/dac/defconfig b/boards/arm/stm32f4/nucleo-f446re/configs/dac/defconfig new file mode 100644 index 0000000000000..12275ba08bfb9 --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f446re/configs/dac/defconfig @@ -0,0 +1,56 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_STM32_FLASH_PREFETCH is not set +CONFIG_ANALOG=y +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nucleo-f446re" +CONFIG_ARCH_BOARD_NUCLEO_F446RE=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F446R=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=8499 +CONFIG_BUILTIN=y +CONFIG_DAC=y +CONFIG_EXAMPLES_DAC=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=131072 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_SPI=y +CONFIG_START_DAY=14 +CONFIG_START_MONTH=10 +CONFIG_START_YEAR=2014 +CONFIG_STM32_CRC=y +CONFIG_STM32_DAC1=y +CONFIG_STM32_DAC1CH1=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PWR=y +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f4/nucleo-f446re/configs/gpio/defconfig b/boards/arm/stm32f4/nucleo-f446re/configs/gpio/defconfig new file mode 100644 index 0000000000000..9367b5a74c27f --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f446re/configs/gpio/defconfig @@ -0,0 +1,52 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_STM32_FLASH_PREFETCH is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nucleo-f446re" +CONFIG_ARCH_BOARD_NUCLEO_F446RE=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F446R=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=8499 +CONFIG_BUILTIN=y +CONFIG_DEV_GPIO=y +CONFIG_EXAMPLES_GPIO=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=131072 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=14 +CONFIG_START_MONTH=10 +CONFIG_START_YEAR=2014 +CONFIG_STM32_CRC=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PWR=y +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f4/nucleo-f446re/configs/ihm08m1_b16/defconfig b/boards/arm/stm32f4/nucleo-f446re/configs/ihm08m1_b16/defconfig new file mode 100644 index 0000000000000..243dbde9820d1 --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f446re/configs/ihm08m1_b16/defconfig @@ -0,0 +1,91 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_DISABLE_MQUEUE is not set +# CONFIG_DISABLE_PTHREAD is not set +CONFIG_ADC=y +CONFIG_ADC_FIFOSIZE=3 +CONFIG_ANALOG=y +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nucleo-f446re" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_NUCLEO_F446RE=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F446R=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_INTERRUPTSTACK=1024 +CONFIG_ARCH_IRQBUTTONS=y +CONFIG_ARMV7M_LIBM=y +CONFIG_BOARDCTL=y +CONFIG_BOARD_LOOPSPERMSEC=8499 +CONFIG_BOARD_STM32_IHM08M1=y +CONFIG_BOARD_STM32_IHM08M1_POT=y +CONFIG_BOARD_STM32_IHM08M1_VBUS=y +CONFIG_BUILTIN=y +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_DEFAULT_SMALL=y +CONFIG_DEFAULT_TASK_STACKSIZE=1024 +CONFIG_EXAMPLES_FOC=y +CONFIG_EXAMPLES_FOC_ADC_MAX=4095 +CONFIG_EXAMPLES_FOC_ADC_VREF=3300 +CONFIG_EXAMPLES_FOC_CONTROL_STACKSIZE=2048 +CONFIG_EXAMPLES_FOC_FIXED16_INST=1 +CONFIG_EXAMPLES_FOC_HAVE_BUTTON=y +CONFIG_EXAMPLES_FOC_RAMP_ACC=200000 +CONFIG_EXAMPLES_FOC_RAMP_DEC=200000 +CONFIG_EXAMPLES_FOC_RAMP_THR=10000 +CONFIG_EXAMPLES_FOC_SETPOINT_ADC=y +CONFIG_EXAMPLES_FOC_VBUS_ADC=y +CONFIG_EXAMPLES_FOC_VBUS_SCALE=19152 +CONFIG_INDUSTRY_FOC=y +CONFIG_INDUSTRY_FOC_FIXED16=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INPUT=y +CONFIG_INPUT_BUTTONS=y +CONFIG_INPUT_BUTTONS_LOWER=y +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_FLOATINGPOINT=y +CONFIG_LIBM=y +CONFIG_MOTOR=y +CONFIG_MOTOR_FOC=y +CONFIG_MOTOR_FOC_TRACE=y +CONFIG_MQ_MAXMSGSIZE=5 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_RAM_SIZE=16386 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=14 +CONFIG_START_MONTH=10 +CONFIG_START_YEAR=2014 +CONFIG_STM32_ADC1_ANIOC_TRIGGER=1 +CONFIG_STM32_ADC1_DMA=y +CONFIG_STM32_ADC1_DMA_CFG=1 +CONFIG_STM32_ADC1_INJECTED_CHAN=3 +CONFIG_STM32_DMA1=y +CONFIG_STM32_DMA2=y +CONFIG_STM32_FOC=y +CONFIG_STM32_FOC_FOC0=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_TIM1_CH1MODE=0 +CONFIG_STM32_TIM1_CH1NPOL=1 +CONFIG_STM32_TIM1_CH2MODE=0 +CONFIG_STM32_TIM1_CH2NPOL=1 +CONFIG_STM32_TIM1_CH3MODE=0 +CONFIG_STM32_TIM1_CH3NPOL=1 +CONFIG_STM32_TIM1_MODE=2 +CONFIG_STM32_TIM2=y +CONFIG_STM32_USART1=y +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART2_SERIAL_CONSOLE=y +CONFIG_USART2_TXDMA=y diff --git a/boards/arm/stm32f4/nucleo-f446re/configs/ihm08m1_f32/defconfig b/boards/arm/stm32f4/nucleo-f446re/configs/ihm08m1_f32/defconfig new file mode 100644 index 0000000000000..ce02324a89ad6 --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f446re/configs/ihm08m1_f32/defconfig @@ -0,0 +1,91 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_DISABLE_MQUEUE is not set +# CONFIG_DISABLE_PTHREAD is not set +CONFIG_ADC=y +CONFIG_ADC_FIFOSIZE=3 +CONFIG_ANALOG=y +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nucleo-f446re" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_NUCLEO_F446RE=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F446R=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_INTERRUPTSTACK=1024 +CONFIG_ARCH_IRQBUTTONS=y +CONFIG_ARMV7M_LIBM=y +CONFIG_BOARDCTL=y +CONFIG_BOARD_LOOPSPERMSEC=8499 +CONFIG_BOARD_STM32_IHM08M1=y +CONFIG_BOARD_STM32_IHM08M1_POT=y +CONFIG_BOARD_STM32_IHM08M1_VBUS=y +CONFIG_BUILTIN=y +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_DEFAULT_SMALL=y +CONFIG_DEFAULT_TASK_STACKSIZE=1024 +CONFIG_EXAMPLES_FOC=y +CONFIG_EXAMPLES_FOC_ADC_MAX=4095 +CONFIG_EXAMPLES_FOC_ADC_VREF=3300 +CONFIG_EXAMPLES_FOC_CONTROL_STACKSIZE=2048 +CONFIG_EXAMPLES_FOC_FLOAT_INST=1 +CONFIG_EXAMPLES_FOC_HAVE_BUTTON=y +CONFIG_EXAMPLES_FOC_RAMP_ACC=200000 +CONFIG_EXAMPLES_FOC_RAMP_DEC=200000 +CONFIG_EXAMPLES_FOC_RAMP_THR=10000 +CONFIG_EXAMPLES_FOC_SETPOINT_ADC=y +CONFIG_EXAMPLES_FOC_VBUS_ADC=y +CONFIG_EXAMPLES_FOC_VBUS_SCALE=19152 +CONFIG_INDUSTRY_FOC=y +CONFIG_INDUSTRY_FOC_FLOAT=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INPUT=y +CONFIG_INPUT_BUTTONS=y +CONFIG_INPUT_BUTTONS_LOWER=y +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_FLOATINGPOINT=y +CONFIG_LIBM=y +CONFIG_MOTOR=y +CONFIG_MOTOR_FOC=y +CONFIG_MOTOR_FOC_TRACE=y +CONFIG_MQ_MAXMSGSIZE=5 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_RAM_SIZE=16386 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=14 +CONFIG_START_MONTH=10 +CONFIG_START_YEAR=2014 +CONFIG_STM32_ADC1_ANIOC_TRIGGER=1 +CONFIG_STM32_ADC1_DMA=y +CONFIG_STM32_ADC1_DMA_CFG=1 +CONFIG_STM32_ADC1_INJECTED_CHAN=3 +CONFIG_STM32_DMA1=y +CONFIG_STM32_DMA2=y +CONFIG_STM32_FOC=y +CONFIG_STM32_FOC_FOC0=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_TIM1_CH1MODE=0 +CONFIG_STM32_TIM1_CH1NPOL=1 +CONFIG_STM32_TIM1_CH2MODE=0 +CONFIG_STM32_TIM1_CH2NPOL=1 +CONFIG_STM32_TIM1_CH3MODE=0 +CONFIG_STM32_TIM1_CH3NPOL=1 +CONFIG_STM32_TIM1_MODE=2 +CONFIG_STM32_TIM2=y +CONFIG_STM32_USART1=y +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART2_SERIAL_CONSOLE=y +CONFIG_USART2_TXDMA=y diff --git a/boards/arm/stm32f4/nucleo-f446re/configs/jumbo/defconfig b/boards/arm/stm32f4/nucleo-f446re/configs/jumbo/defconfig new file mode 100644 index 0000000000000..aa93ca052f811 --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f446re/configs/jumbo/defconfig @@ -0,0 +1,55 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_STM32_FLASH_PREFETCH is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nucleo-f446re" +CONFIG_ARCH_BOARD_NUCLEO_F446RE=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F446R=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=8499 +CONFIG_BUILTIN=y +CONFIG_EXAMPLES_PULSECOUNT=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=131072 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_SPI=y +CONFIG_START_DAY=14 +CONFIG_START_MONTH=10 +CONFIG_START_YEAR=2014 +CONFIG_STM32_CRC=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PWR=y +CONFIG_STM32_TIM8=y +CONFIG_STM32_TIM8_PULSECOUNT=y +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_TESTING_OSTEST=y +CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f4/nucleo-f446re/configs/lcd/defconfig b/boards/arm/stm32f4/nucleo-f446re/configs/lcd/defconfig new file mode 100644 index 0000000000000..db27a7127b80b --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f446re/configs/lcd/defconfig @@ -0,0 +1,59 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_STM32_FLASH_PREFETCH is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nucleo-f446re" +CONFIG_ARCH_BOARD_NUCLEO_F446RE=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F446R=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=8499 +CONFIG_BUILTIN=y +CONFIG_DRIVERS_VIDEO=y +CONFIG_EXAMPLES_FB=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LCD=y +CONFIG_LCD_FRAMEBUFFER=y +CONFIG_LCD_ILI9225=y +CONFIG_LCD_PORTRAIT=y +CONFIG_LINE_MAX=64 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=131072 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_SPI_CMDDATA=y +CONFIG_START_DAY=14 +CONFIG_START_MONTH=10 +CONFIG_START_YEAR=2014 +CONFIG_STM32_CRC=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PWR=y +CONFIG_STM32_SPI3=y +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART2_SERIAL_CONSOLE=y +CONFIG_VIDEO_FB=y diff --git a/boards/arm/stm32f4/nucleo-f446re/configs/nsh/defconfig b/boards/arm/stm32f4/nucleo-f446re/configs/nsh/defconfig new file mode 100644 index 0000000000000..a4266c978ab70 --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f446re/configs/nsh/defconfig @@ -0,0 +1,52 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_STM32_FLASH_PREFETCH is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nucleo-f446re" +CONFIG_ARCH_BOARD_NUCLEO_F446RE=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F446R=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=8499 +CONFIG_BUILTIN=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=131072 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_SPI=y +CONFIG_START_DAY=14 +CONFIG_START_MONTH=10 +CONFIG_START_YEAR=2014 +CONFIG_STM32_CRC=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PWR=y +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_TESTING_OSTEST=y +CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f4/nucleo-f446re/configs/pwm/defconfig b/boards/arm/stm32f4/nucleo-f446re/configs/pwm/defconfig new file mode 100644 index 0000000000000..d56c5382c30a6 --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f446re/configs/pwm/defconfig @@ -0,0 +1,56 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_STM32_FLASH_PREFETCH is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nucleo-f446re" +CONFIG_ARCH_BOARD_NUCLEO_F446RE=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F446R=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=8499 +CONFIG_BUILTIN=y +CONFIG_EXAMPLES_PWM=y +CONFIG_EXAMPLES_PWM_DEVPATH="/dev/pwm2" +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_PWM=y +CONFIG_RAM_SIZE=131072 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=14 +CONFIG_START_MONTH=10 +CONFIG_START_YEAR=2014 +CONFIG_STM32_CRC=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PWR=y +CONFIG_STM32_TIM3=y +CONFIG_STM32_TIM3_CH1OUT=y +CONFIG_STM32_TIM3_PWM=y +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f4/nucleo-f446re/configs/qenco/defconfig b/boards/arm/stm32f4/nucleo-f446re/configs/qenco/defconfig new file mode 100644 index 0000000000000..9227f770c5526 --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f446re/configs/qenco/defconfig @@ -0,0 +1,51 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nucleo-f446re" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_NUCLEO_F446RE=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F446R=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_INTERRUPTSTACK=1024 +CONFIG_ARCH_IRQPRIO=y +CONFIG_BOARD_LOOPSPERMSEC=8499 +CONFIG_BUILTIN=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_EXAMPLES_QENCODER=y +CONFIG_EXAMPLES_QENCODER_HAVE_MAXPOS=y +CONFIG_EXAMPLES_QENCODER_MAXPOS=8192 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_MQ_MAXMSGSIZE=5 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NUCLEO_F446RE_QETIMER=2 +CONFIG_NUCLEO_F446RE_QETIMER_TIM2_IHM08M1_MAP=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=16386 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_SENSORS=y +CONFIG_SENSORS_QENCODER=y +CONFIG_START_DAY=14 +CONFIG_START_MONTH=10 +CONFIG_START_YEAR=2014 +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_QENCODER_DISABLE_EXTEND16BTIMERS=y +CONFIG_STM32_QENCODER_SAMPLE_FDTS_2=y +CONFIG_STM32_TIM2=y +CONFIG_STM32_TIM2_QE=y +CONFIG_STM32_TIM2_QEPSC=0 +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f4/nucleo-f446re/configs/systemview/defconfig b/boards/arm/stm32f4/nucleo-f446re/configs/systemview/defconfig new file mode 100644 index 0000000000000..891ed15e1505c --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f446re/configs/systemview/defconfig @@ -0,0 +1,52 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_DRIVERS_NOTERAM is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_STM32_FLASH_PREFETCH is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nucleo-f446re" +CONFIG_ARCH_BOARD_NUCLEO_F446RE=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F446R=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=8499 +CONFIG_BUILTIN=y +CONFIG_DRIVERS_NOTE=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=131072 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_INSTRUMENTATION=y +CONFIG_SCHED_INSTRUMENTATION_IRQHANDLER=y +CONFIG_SCHED_WAITPID=y +CONFIG_SEGGER_SYSVIEW=y +CONFIG_START_DAY=14 +CONFIG_START_MONTH=10 +CONFIG_START_YEAR=2014 +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=32 +CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f4/nucleo-f446re/include/board.h b/boards/arm/stm32f4/nucleo-f446re/include/board.h new file mode 100644 index 0000000000000..dc46e111057ad --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f446re/include/board.h @@ -0,0 +1,444 @@ +/**************************************************************************** + * boards/arm/stm32f4/nucleo-f446re/include/board.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_STM32_NUCLEO_F446RE_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32_NUCLEO_F446RE_INCLUDE_BOARD_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#ifndef __ASSEMBLY__ +# include +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Clocking *****************************************************************/ + +/* The NUCLEOF446RE supports both HSE and LSE crystals (X2 and X3). + * However, as shipped, the X2 and X3 crystals are not populated. + * Therefore the Nucleo-FF446RE will need to run off the 16MHz HSI clock. + * + * System Clock source : PLL (HSI) + * SYSCLK(Hz) : 180000000 Determined by PLL config + * HCLK(Hz) : 180000000 (STM32_RCC_CFGR_HPRE) + * AHB Prescaler : 1 (STM32_RCC_CFGR_HPRE) + * APB1 Prescaler : 2 (STM32_RCC_CFGR_PPRE1) + * APB2 Prescaler : 1 (STM32_RCC_CFGR_PPRE2) + * HSI Frequency(Hz) : 16000000 (nominal) + * PLLM : 8 (STM32_PLLCFG_PLLM) + * PLLN : 216 (STM32_PLLCFG_PLLN) + * PLLP : 4 (STM32_PLLCFG_PLLP) + * PLLQ : 9 (STM32_PLLCFG_PPQ) + * Flash Latency(WS) : 4 + * Prefetch Buffer : OFF + * Instruction cache : ON + * Data cache : ON + * Require 48MHz for USB OTG FS, : Enabled + * SDIO and RNG clock + */ + +/* HSI - 16 MHz RC factory-trimmed + * LSI - 32 KHz RC + * HSE - not installed + * LSE - not installed + */ + +#define STM32_HSI_FREQUENCY 16000000ul +#define STM32_LSI_FREQUENCY 32000 +#define STM32_BOARD_USEHSI 1 + +/* Main PLL Configuration. + * + * Formulae: + * + * target 180 MHz, source 16 MHz -> ratio = 11.25 = 22.5 x 2 = 45 x 4 + * so we can select a divider of 4 and a multiplier of 45 + * However multiplier must be between 50 and 432 + * so we double again to choose a multiplier of 90, and a divider of 8 + * VCO output frequency must be in range 100...432 MHz + * + * VCO input frequency = PLL input clock frequency / PLLM, + * 2 <= PLLM <= 63 + * VCO output frequency = VCO input frequency × PLLN, + * 50 <= PLLN <= 432 (50-99 only if VCO input > 1 MHz) + * PLL output clock frequency = VCO frequency / PLLP, + * PLLP = 2, 4, 6, or 8 + * USB OTG FS clock frequency = VCO frequency / PLLQ, + * 2 <= PLLQ <= 15 + * + + * PLLQ = 7.5 PLLP = 2 PLLN=90 PLLM=4 + * + * We will configure like this + * + * PLL source is HSI + * PLL_VCO = (STM32_HSI_FREQUENCY / PLLM) * PLLN + * = (16,000,000 / 4) * 90 + * = 360 MHz + * SYSCLK = PLL_VCO / PLLP + * = 360,000,000 / 2 = 180,000,000 + * USB OTG FS and SDIO Clock + * = TODO 7.5 is not possible + * + * REVISIT: Trimming of the HSI is not yet supported. + */ + +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(4) +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(90) +#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_2 +#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(15) + +#define STM32_SYSCLK_FREQUENCY 180000000ul + +/* AHB clock (HCLK) is SYSCLK (104MHz) */ + +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY + +/* APB1 clock (PCLK1) is HCLK/2 (52MHz) */ + +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd2 /* PCLK1 = HCLK / 2 */ +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/2) + +/* Timers driven from APB1 will be twice PCLK1 (REVISIT) */ + +#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) + +/* APB2 clock (PCLK2) is HCLK (104MHz) */ + +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ +#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/1) + +/* Timers driven from APB1 will be twice PCLK1 */ + +#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM9_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM10_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM11_CLKIN (STM32_PCLK2_FREQUENCY) + +/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx + * otherwise frequency is 2xAPBx. + * Note: TIM1,8 are on APB2, others on APB1 + */ + +#define BOARD_TIM1_FREQUENCY (STM32_PCLK2_FREQUENCY) +#define BOARD_TIM2_FREQUENCY (2*STM32_PCLK1_FREQUENCY) +#define BOARD_TIM3_FREQUENCY (2*STM32_PCLK1_FREQUENCY) +#define BOARD_TIM4_FREQUENCY (2*STM32_PCLK1_FREQUENCY) +#define BOARD_TIM5_FREQUENCY (2*STM32_PCLK1_FREQUENCY) +#define BOARD_TIM6_FREQUENCY (2*STM32_PCLK1_FREQUENCY) +#define BOARD_TIM7_FREQUENCY (2*STM32_PCLK1_FREQUENCY) +#define BOARD_TIM8_FREQUENCY (STM32_PCLK2_FREQUENCY) + +/* SDIO dividers. Note that slower clocking is required when DMA is disabled + * in order to avoid RX overrun/TX underrun errors due to delayed responses + * to service FIFOs in interrupt driven mode. These values have not been + * tuned!!! + * + * HCLK=72MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(178+2)=400 KHz + * + * REVISIT + */ + +#define SDIO_INIT_CLKDIV (178 << SDIO_CLKCR_CLKDIV_SHIFT) + +/* DMA ON: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(2+2)=18 MHz + * DMA OFF: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(3+2)=14.4 MHz + * + * REVISIT + */ + +#ifdef CONFIG_SDIO_DMA +# define SDIO_MMCXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT) +#else +# define SDIO_MMCXFR_CLKDIV (3 << SDIO_CLKCR_CLKDIV_SHIFT) +#endif + +/* DMA ON: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(1+2)=24 MHz + * DMA OFF: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(3+2)=14.4 MHz + * + * REVISIT + */ + +#ifdef CONFIG_SDIO_DMA +# define SDIO_SDXFR_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT) +#else +# define SDIO_SDXFR_CLKDIV (3 << SDIO_CLKCR_CLKDIV_SHIFT) +#endif + +/* DMA Channel/Stream Selections ********************************************/ + +/* Stream selections are arbitrary for now but might become important in the + * future is we set aside more DMA channels/streams. + * + * SDIO DMA + *   DMAMAP_SDIO_1 = Channel 4, Stream 3 <- may later be used by SPI DMA + *   DMAMAP_SDIO_2 = Channel 4, Stream 6 + */ + +#define DMAMAP_SDIO DMAMAP_SDIO_1 + +/* Need to VERIFY fwb */ + +#define DMACHAN_SPI1_RX DMAMAP_SPI1_RX_1 +#define DMACHAN_SPI1_TX DMAMAP_SPI1_TX_1 +#define DMACHAN_SPI2_RX DMAMAP_SPI2_RX +#define DMACHAN_SPI2_TX DMAMAP_SPI2_TX + +/* ADC 1 */ + +#define ADC1_DMA_CHAN DMAMAP_ADC1_1 + +/* Alternate function pin selections ****************************************/ + +/* USART1: + * RXD: PA10 CN9 pin 3, CN10 pin 33 + * PB7 CN7 pin 21 + * TXD: PA9 CN5 pin 1, CN10 pin 21 + * PB6 CN5 pin 3, CN10 pin 17 + */ + +#if !defined(CONFIG_BOARD_STM32_IHM08M1) +# define GPIO_USART1_RX (GPIO_USART1_RX_1|GPIO_SPEED_100MHz) /* PA10 */ +# define GPIO_USART1_TX (GPIO_USART1_TX_1|GPIO_SPEED_100MHz) /* PA9 */ +#else +# define GPIO_USART1_RX (GPIO_USART1_RX_2|GPIO_SPEED_100MHz) /* PB7 */ +# define GPIO_USART1_TX (GPIO_USART1_TX_2|GPIO_SPEED_100MHz) /* PB6 */ +#endif + +/* USART2: + * RXD: PA3 CN9 pin 1 (See SB13, 14, 62, 63). CN10 pin 37 + * PD6 + * TXD: PA2 CN9 pin 2(See SB13, 14, 62, 63). CN10 pin 35 + * PD5 + */ + +#define GPIO_USART2_RX (GPIO_USART2_RX_1|GPIO_SPEED_100MHz) /* PA3 */ +#define GPIO_USART2_TX (GPIO_USART2_TX_1|GPIO_SPEED_100MHz) /* PA2 */ +#define GPIO_USART2_RTS GPIO_USART2_RTS_2 +#define GPIO_USART2_CTS GPIO_USART2_CTS_2 + +/* USART6: + * RXD: PC7 CN5 pin2, CN10 pin 19 + * PA12 CN10, pin 12 + * TXD: PC6 CN10, pin 4 + * PA11 CN10, pin 14 + */ + +#define GPIO_USART6_RX (GPIO_USART6_RX_1|GPIO_SPEED_100MHz) /* PC7 */ +#define GPIO_USART6_TX (GPIO_USART6_TX_1|GPIO_SPEED_100MHz) /* PC6 */ + +/* UART RX DMA configurations */ + +#define DMAMAP_USART1_RX DMAMAP_USART1_RX_2 +#define DMAMAP_USART6_RX DMAMAP_USART6_RX_2 + +/* I2C + * + * The optional _GPIO configurations allow the I2C driver to manually + * reset the bus to clear stuck slaves. They match the pin configuration, + * but are normally-high GPIOs. + */ + +#define GPIO_I2C1_SCL (GPIO_I2C1_SCL_2|GPIO_SPEED_50MHz) +#define GPIO_I2C1_SDA (GPIO_I2C1_SDA_2|GPIO_SPEED_50MHz) +#define GPIO_I2C1_SCL_GPIO \ + (GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET| \ + GPIO_PORTB|GPIO_PIN8) +#define GPIO_I2C1_SDA_GPIO \ + (GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET| \ + GPIO_PORTB|GPIO_PIN9) + +#define GPIO_I2C2_SCL (GPIO_I2C2_SCL_1|GPIO_SPEED_50MHz) +#define GPIO_I2C2_SDA (GPIO_I2C2_SDA_1|GPIO_SPEED_50MHz) +#define GPIO_I2C2_SCL_GPIO \ + (GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET| \ + GPIO_PORTB|GPIO_PIN10) +#define GPIO_I2C2_SDA_GPIO \ + (GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET| \ + GPIO_PORTB|GPIO_PIN11) + +/* SPI + * + * There are sensors on SPI1, and SPI2 is connected to the FRAM. + */ + +#define GPIO_SPI1_MISO (GPIO_SPI1_MISO_1|GPIO_SPEED_50MHz) +#define GPIO_SPI1_MOSI (GPIO_SPI1_MOSI_1|GPIO_SPEED_50MHz) +#define GPIO_SPI1_SCK (GPIO_SPI1_SCK_1|GPIO_SPEED_50MHz) + +#define GPIO_SPI2_MISO (GPIO_SPI2_MISO_1|GPIO_SPEED_50MHz) +#define GPIO_SPI2_MOSI (GPIO_SPI2_MOSI_1|GPIO_SPEED_50MHz) +#define GPIO_SPI2_SCK (GPIO_SPI2_SCK_2|GPIO_SPEED_50MHz) + +#define GPIO_SPI3_MISO (GPIO_SPI3_MISO_1|GPIO_SPEED_50MHz) +#define GPIO_SPI3_MOSI (GPIO_SPI3_MOSI_1|GPIO_SPEED_50MHz) +#define GPIO_SPI3_SCK (GPIO_SPI3_SCK_1|GPIO_SPEED_50MHz) + +/* CAN */ + +#define GPIO_CAN1_RX (GPIO_CAN1_RX_2|GPIO_SPEED_50MHz) +#define GPIO_CAN1_TX (GPIO_CAN1_TX_2|GPIO_SPEED_50MHz) + +#define GPIO_CAN2_RX (GPIO_CAN2_RX_2|GPIO_SPEED_50MHz) +#define GPIO_CAN2_TX (GPIO_CAN2_TX_2|GPIO_SPEED_50MHz) + +/* LEDs + * + * The Nucleo F446RE and F411RE boards provide a single user LED, LD2. LD2 + * is the green LED connected to Arduino signal D13 corresponding to MCU I/O + * PA5 (pin 21) or PB13 (pin 34) depending on the STM32 target. + * + * - When the I/O is HIGH value, the LED is on. + * - When the I/O is LOW, the LED is off. + */ + +/* LED index values for use with board_userled() */ + +#define BOARD_LD2 0 +#define BOARD_NLEDS 1 + +/* LED bits for use with board_userled_all() */ + +#define BOARD_LD2_BIT (1 << BOARD_LD2) + +/* These LEDs are not used by the board port unless CONFIG_ARCH_LEDS is + * defined. In that case, the usage by the board port is defined in + * include/board.h and src/sam_leds.c. The LEDs are used to encode OS-related + * events as follows when the red LED (PE24) is available: + * + * SYMBOL Meaning LD2 + * ------------------- ----------------------- ----------- + * LED_STARTED NuttX has been started OFF + * LED_HEAPALLOCATE Heap has been allocated OFF + * LED_IRQSENABLED Interrupts enabled OFF + * LED_STACKCREATED Idle stack created ON + * LED_INIRQ In an interrupt No change + * LED_SIGNAL In a signal handler No change + * LED_ASSERTION An assertion failed No change + * LED_PANIC The system has crashed Blinking + * LED_IDLE MCU is in sleep mode Not used + * + * Thus if LD2, NuttX has successfully booted and is, apparently, running + * normally. If LD2 is flashing at approximately 2Hz, then a fatal error + * has been detected and the system has halted. + */ + +#define LED_STARTED 0 +#define LED_HEAPALLOCATE 0 +#define LED_IRQSENABLED 0 +#define LED_STACKCREATED 1 +#define LED_INIRQ 2 +#define LED_SIGNAL 2 +#define LED_ASSERTION 2 +#define LED_PANIC 1 + +/* Buttons + * + * B1 USER: the user button is connected to the I/O PC13 (pin 2) of + * the STM32 microcontroller. + */ + +#define BUTTON_USER 0 +#define NUM_BUTTONS 1 + +#define BUTTON_USER_BIT (1 << BUTTON_USER) + +/* TIM2 input ***************************************************************/ + +#ifndef CONFIG_NUCLEO_F446RE_QETIMER_TIM2_IHM08M1_MAP +# define GPIO_TIM2_CH1IN (GPIO_TIM2_CH1IN_1 | GPIO_PULLUP | GPIO_SPEED_50MHz) /* PA8 */ +# define GPIO_TIM2_CH2IN (GPIO_TIM2_CH2IN_1 | GPIO_PULLUP | GPIO_SPEED_50MHz) /* PB0 */ +#else +# define GPIO_TIM2_CH1IN (GPIO_TIM2_CH1IN_2 | GPIO_PULLUP | GPIO_SPEED_50MHz) /* PA15 */ +# define GPIO_TIM2_CH2IN (GPIO_TIM2_CH2IN_2 | GPIO_PULLUP | GPIO_SPEED_50MHz) /* PB3 */ +#endif + +/* TIM3 configuration *******************************************************/ + +#define GPIO_TIM3_CH1OUT (GPIO_TIM3_CH1OUT_1|GPIO_SPEED_50MHz) + +/* TIM8 configuration *******************************************************/ + +#define GPIO_TIM8_CH1OUT (GPIO_TIM8_CH1OUT_1|GPIO_SPEED_50MHz) /* PC6 */ + +#ifdef CONFIG_BOARD_STM32_IHM08M1 + +/* Configuration specific to the X-NUCLEO-IHM08M1 expansion board with + * the L6398 gate drivers. + */ + +/* TIM1 configuration *******************************************************/ + +#define GPIO_TIM1_CH1OUT (GPIO_TIM1_CH1OUT_1|GPIO_SPEED_50MHz) /* TIM1 CH1 - PA8 - U high */ +#define GPIO_TIM1_CH1NOUT GPIO_TIM1_CH1N_1 /* TIM1 CH1N - PA7 - U low */ +#define GPIO_TIM1_CH2OUT (GPIO_TIM1_CH2OUT_1|GPIO_SPEED_50MHz) /* TIM1 CH2 - PA9 - V high */ +#define GPIO_TIM1_CH2NOUT GPIO_TIM1_CH2N_1 /* TIM1 CH2N - PB0 - V low */ +#define GPIO_TIM1_CH3OUT (GPIO_TIM1_CH3OUT_1|GPIO_SPEED_50MHz) /* TIM1 CH3 - PA10 - W high */ +#define GPIO_TIM1_CH3NOUT GPIO_TIM1_CH3N_1 /* TIM1 CH3N - PB1 - W low */ +#define GPIO_TIM1_CH4OUT 0 /* not used as output */ + +/* Board LED */ + +# define GPIO_FOC_LED2 (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz| \ + GPIO_OUTPUT_CLEAR|GPIO_PORTB|GPIO_PIN2) + +/* Debug pin */ + +# define GPIO_FOC_DEBUG0 (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz| \ + GPIO_OUTPUT_CLEAR|GPIO_PORTB|GPIO_PIN12) +# define GPIO_FOC_DEBUG1 (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz| \ + GPIO_OUTPUT_CLEAR|GPIO_PORTB|GPIO_PIN9) +# define GPIO_FOC_DEBUG2 (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz| \ + GPIO_OUTPUT_CLEAR|GPIO_PORTC|GPIO_PIN6) +# define GPIO_FOC_DEBUG3 (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz| \ + GPIO_OUTPUT_CLEAR|GPIO_PORTB|GPIO_PIN5) + +#endif /* CONFIG_BOARD_STM32_IHM08M1 */ + +/* DAC */ + +#define GPIO_DAC1_OUT1 GPIO_DAC1_OUT1_0 +#define GPIO_DAC1_OUT2 GPIO_DAC1_OUT2_0 + +/* USB OTG FS */ + +#define GPIO_OTGFS_DM (GPIO_OTGFS_DM_0|GPIO_SPEED_100MHz) +#define GPIO_OTGFS_DP (GPIO_OTGFS_DP_0|GPIO_SPEED_100MHz) +#define GPIO_OTGFS_ID (GPIO_OTGFS_ID_0|GPIO_SPEED_100MHz) +#define GPIO_OTGFS_SOF (GPIO_OTGFS_SOF_0|GPIO_SPEED_100MHz) + +#endif /* __BOARDS_ARM_STM32_NUCLEO_F446RE_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32f4/nucleo-f446re/scripts/Make.defs b/boards/arm/stm32f4/nucleo-f446re/scripts/Make.defs new file mode 100644 index 0000000000000..e2c1dea47e06f --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f446re/scripts/Make.defs @@ -0,0 +1,42 @@ +############################################################################ +# boards/arm/stm32f4/nucleo-f446re/scripts/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/.config +include $(TOPDIR)/tools/Config.mk +include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs + +LDSCRIPT = f446re.ld +ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) + +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 + diff --git a/boards/arm/stm32/nucleo-f446re/scripts/f446re.ld b/boards/arm/stm32f4/nucleo-f446re/scripts/f446re.ld similarity index 98% rename from boards/arm/stm32/nucleo-f446re/scripts/f446re.ld rename to boards/arm/stm32f4/nucleo-f446re/scripts/f446re.ld index bdb91d982c9dc..cc81e91e33f55 100644 --- a/boards/arm/stm32/nucleo-f446re/scripts/f446re.ld +++ b/boards/arm/stm32f4/nucleo-f446re/scripts/f446re.ld @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f446re/scripts/f446re.ld + * boards/arm/stm32f4/nucleo-f446re/scripts/f446re.ld * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f4/nucleo-f446re/src/CMakeLists.txt b/boards/arm/stm32f4/nucleo-f446re/src/CMakeLists.txt new file mode 100644 index 0000000000000..610cad1a6c0d2 --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f446re/src/CMakeLists.txt @@ -0,0 +1,75 @@ +# ############################################################################## +# boards/arm/stm32f4/nucleo-f446re/src/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(SRCS stm32_boot.c stm32_bringup.c stm32_spi.c) + +if(CONFIG_ARCH_LEDS) + list(APPEND SRCS stm32_autoleds.c) +else() + list(APPEND SRCS stm32_userleds.c) +endif() + +if(CONFIG_ARCH_BUTTONS) + list(APPEND SRCS stm32_buttons.c) +endif() + +if(CONFIG_LCD_ILI9225) + list(APPEND SRCS stm32_ili9225.c) +endif() + +if(NOT CONFIG_STM32_FOC) + if(CONFIG_ADC) + list(APPEND SRCS stm32_adc.c) + if(CONFIG_INPUT_AJOYSTICK) + list(APPEND SRCS stm32_ajoystick.c) + endif() + endif() +endif() + +if(CONFIG_STM32_CAN) + if(CONFIG_STM32_CAN_CHARDRIVER) + list(APPEND SRCS stm32_can.c) + endif() + if(CONFIG_STM32_CAN_SOCKET) + list(APPEND SRCS stm32_cansock.c) + endif() +endif() + +if(CONFIG_STM32_PWM) + list(APPEND SRCS stm32_pwm.c) +endif() + +if(CONFIG_DEV_GPIO) + list(APPEND SRCS stm32_gpio.c) +endif() + +if(CONFIG_DAC) + list(APPEND SRCS stm32_dac.c) +endif() + +if(CONFIG_BOARD_STM32_IHM08M1) + list(APPEND SRCS stm32_foc_ihm08m1.c) +endif() + +target_sources(board PRIVATE ${SRCS}) + +set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/f446re.ld") diff --git a/boards/arm/stm32f4/nucleo-f446re/src/Make.defs b/boards/arm/stm32f4/nucleo-f446re/src/Make.defs new file mode 100644 index 0000000000000..f4f9c4ec5ce29 --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f446re/src/Make.defs @@ -0,0 +1,77 @@ +############################################################################ +# boards/arm/stm32f4/nucleo-f446re/src/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +CSRCS = stm32_boot.c stm32_bringup.c stm32_spi.c + +ifeq ($(CONFIG_ARCH_LEDS),y) +CSRCS += stm32_autoleds.c +else +CSRCS += stm32_userleds.c +endif + +ifeq ($(CONFIG_ARCH_BUTTONS),y) +CSRCS += stm32_buttons.c +endif + +ifeq ($(CONFIG_LCD_ILI9225),y) +CSRCS += stm32_ili9225.c +endif + +ifneq ($(CONFIG_STM32_FOC),y) +ifeq ($(CONFIG_ADC),y) +CSRCS += stm32_adc.c +ifeq ($(CONFIG_INPUT_AJOYSTICK),y) +CSRCS += stm32_ajoystick.c +endif +endif +endif + +ifeq ($(CONFIG_STM32_CAN),y) +ifeq ($(CONFIG_STM32_CAN_CHARDRIVER),y) +CSRCS += stm32_can.c +endif +ifeq ($(CONFIG_STM32_CAN_SOCKET),y) +CSRCS += stm32_cansock.c +endif +endif + +ifeq ($(CONFIG_STM32_PWM),y) +CSRCS += stm32_pwm.c +endif + +ifeq ($(CONFIG_DEV_GPIO),y) +CSRCS += stm32_gpio.c +endif + +ifeq ($(CONFIG_DAC),y) +CSRCS += stm32_dac.c +endif + +ifeq ($(CONFIG_BOARD_STM32_IHM08M1),y) +CSRCS += stm32_foc_ihm08m1.c +endif + +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/nucleo-f446re/src/nucleo-f446re.h b/boards/arm/stm32f4/nucleo-f446re/src/nucleo-f446re.h similarity index 99% rename from boards/arm/stm32/nucleo-f446re/src/nucleo-f446re.h rename to boards/arm/stm32f4/nucleo-f446re/src/nucleo-f446re.h index 9510bade876e0..d3e51ce12cccd 100644 --- a/boards/arm/stm32/nucleo-f446re/src/nucleo-f446re.h +++ b/boards/arm/stm32f4/nucleo-f446re/src/nucleo-f446re.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f446re/src/nucleo-f446re.h + * boards/arm/stm32f4/nucleo-f446re/src/nucleo-f446re.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f4/nucleo-f446re/src/stm32_adc.c b/boards/arm/stm32f4/nucleo-f446re/src/stm32_adc.c new file mode 100644 index 0000000000000..a39c53c93c552 --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f446re/src/stm32_adc.c @@ -0,0 +1,142 @@ +/**************************************************************************** + * boards/arm/stm32f4/nucleo-f446re/src/stm32_adc.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32_pwm.h" +#include "nucleo-f446re.h" + +#ifdef CONFIG_STM32_ADC1 + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* The number of ADC channels in the conversion list */ + +#ifdef CONFIG_STM32_ADC1_DMA +# define ADC1_NCHANNELS 2 +#else +# define ADC1_NCHANNELS 1 +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* Identifying number of each ADC channel. */ + +#ifdef CONFIG_STM32_ADC1_DMA +/* The Itead analog joystick gets inputs on ADC_IN0 and ADC_IN1 */ + +static const uint8_t g_adc1_chanlist[ADC1_NCHANNELS] = +{ + 0, 1 +}; + +/* Configurations of pins used byte each ADC channels */ + +static const uint32_t g_adc1_pinlist[ADC1_NCHANNELS] = +{ + GPIO_ADC1_IN0_0, + GPIO_ADC1_IN1_0 +}; + +#else +/* Without DMA, only a single channel can be supported */ + +/* The Itead analog joystick gets input on ADC_IN0 */ + +static const uint8_t g_adc1_chanlist[ADC1_NCHANNELS] = +{ + 0 +}; + +/* Configurations of pins used byte each ADC channels */ + +static const uint32_t g_adc1_pinlist[ADC1_NCHANNELS] = +{ + GPIO_ADC1_IN0_0 +}; + +#endif /* CONFIG_STM32_ADC1_DMA */ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_adc_setup + * + * Description: + * Initialize ADC and register the ADC driver. + * + ****************************************************************************/ + +int stm32_adc_setup(void) +{ + struct adc_dev_s *adc; + int ret; + int i; + + /* Configure the pins as analog inputs for the selected channels */ + + for (i = 0; i < ADC1_NCHANNELS; i++) + { + stm32_configgpio(g_adc1_pinlist[i]); + } + + /* Call stm32_adcinitialize() to get an instance of the ADC interface */ + + adc = stm32_adcinitialize(1, g_adc1_chanlist, ADC1_NCHANNELS); + if (adc == NULL) + { + aerr("ERROR: Failed to get ADC interface\n"); + return -ENODEV; + } + + /* Register the ADC driver at "/dev/adc0" */ + + ret = adc_register("/dev/adc0", adc); + if (ret < 0) + { + aerr("ERROR: adc_register failed: %d\n", ret); + return ret; + } + + return OK; +} + +#endif /* CONFIG_STM32_ADC1 */ diff --git a/boards/arm/stm32f4/nucleo-f446re/src/stm32_ajoystick.c b/boards/arm/stm32f4/nucleo-f446re/src/stm32_ajoystick.c new file mode 100644 index 0000000000000..4027f6b925860 --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f446re/src/stm32_ajoystick.c @@ -0,0 +1,491 @@ +/**************************************************************************** + * boards/arm/stm32f4/nucleo-f446re/src/stm32_ajoystick.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include "stm32_gpio.h" +#include "stm32_adc.h" +#include "hardware/stm32_adc.h" +#include "nucleo-f446re.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Check for pre-requisites and pin conflicts */ + +#ifdef CONFIG_INPUT_AJOYSTICK +# if !defined(CONFIG_ADC) +# error CONFIG_ADC is required for the Itead joystick +# undef CONFIG_INPUT_AJOYSTICK +# elif !defined(CONFIG_STM32_ADC1) +# error CONFIG_STM32_ADC1 is required for Itead joystick +# undef CONFIG_INPUT_AJOYSTICK +# endif +#endif /* CONFIG_INPUT_AJOYSTICK */ + +#ifdef CONFIG_INPUT_AJOYSTICK + +/* A no-ADC, buttons only version can be built for testing */ + +#undef NO_JOYSTICK_ADC + +/* Maximum number of ADC channels */ + +#define MAX_ADC_CHANNELS 8 + +/* Dual channel ADC support requires DMA */ + +#ifdef CONFIG_ADC_DMA +# define NJOYSTICK_CHANNELS 2 +#else +# define NJOYSTICK_CHANNELS 1 +#endif + +#ifdef CONFIG_NUCLEO_F401RE_AJOY_MINBUTTONS +/* Number of Joystick buttons */ + +# define AJOY_NGPIOS 3 + +/* Bitset of supported Joystick buttons */ + +# define AJOY_SUPPORTED (AJOY_BUTTON_1_BIT | AJOY_BUTTON_2_BIT | \ + AJOY_BUTTON_3_BIT) +#else +/* Number of Joystick buttons */ + +# define AJOY_NGPIOS 7 + +/* Bitset of supported Joystick buttons */ + +# define AJOY_SUPPORTED (AJOY_BUTTON_1_BIT | AJOY_BUTTON_2_BIT | \ + AJOY_BUTTON_3_BIT | AJOY_BUTTON_4_BIT | \ + AJOY_BUTTON_5_BIT | AJOY_BUTTON_6_BIT | \ + AJOY_BUTTON_7_BIT ) +#endif + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +static ajoy_buttonset_t +ajoy_supported(const struct ajoy_lowerhalf_s *lower); +static int ajoy_sample(const struct ajoy_lowerhalf_s *lower, + struct ajoy_sample_s *sample); +static ajoy_buttonset_t +ajoy_buttons(const struct ajoy_lowerhalf_s *lower); +static void +ajoy_enable(const struct ajoy_lowerhalf_s *lower, + ajoy_buttonset_t press, ajoy_buttonset_t release, + ajoy_handler_t handler, void *arg); + +static void ajoy_disable(void); +static int ajoy_interrupt(int irq, void *context, void *arg); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* Pin configuration for each Itead joystick button. Index using AJOY_* + * button definitions in include/nuttx/input/ajoystick.h. + */ + +#ifdef CONFIG_NUCLEO_F401RE_AJOY_MINBUTTONS +static const uint32_t g_joygpio[AJOY_NGPIOS] = +{ + GPIO_BUTTON_1, GPIO_BUTTON_2, GPIO_BUTTON_3 +}; +#else +static const uint32_t g_joygpio[AJOY_NGPIOS] = +{ + GPIO_BUTTON_1, GPIO_BUTTON_2, GPIO_BUTTON_3, GPIO_BUTTON_4, + GPIO_BUTTON_5, GPIO_BUTTON_6, GPIO_BUTTON_7 +}; +#endif + +/* This is the button joystick lower half driver interface */ + +static const struct ajoy_lowerhalf_s g_ajoylower = +{ + .al_supported = ajoy_supported, + .al_sample = ajoy_sample, + .al_buttons = ajoy_buttons, + .al_enable = ajoy_enable, +}; + +#ifndef NO_JOYSTICK_ADC +/* Thread-independent file structure for the open ADC driver */ + +static struct file g_adcfile; +#endif + +/* Current interrupt handler and argument */ + +static ajoy_handler_t g_ajoyhandler; +static void *g_ajoyarg; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: ajoy_supported + * + * Description: + * Return the set of buttons supported on the button joystick device + * + ****************************************************************************/ + +static ajoy_buttonset_t +ajoy_supported(const struct ajoy_lowerhalf_s *lower) +{ + iinfo("Supported: %02x\n", AJOY_SUPPORTED); + return (ajoy_buttonset_t)AJOY_SUPPORTED; +} + +/**************************************************************************** + * Name: ajoy_sample + * + * Description: + * Return the current state of all button joystick buttons + * + ****************************************************************************/ + +static int ajoy_sample(const struct ajoy_lowerhalf_s *lower, + struct ajoy_sample_s *sample) +{ +#ifndef NO_JOYSTICK_ADC + struct adc_msg_s adcmsg[MAX_ADC_CHANNELS]; + struct adc_msg_s *ptr; + ssize_t nread; + ssize_t offset; + int have; + int i; + + /* Read all of the available samples (handling the case where additional + * channels are enabled). + */ + + nread = file_read(&g_adcfile, adcmsg, + MAX_ADC_CHANNELS * sizeof(struct adc_msg_s)); + if (nread < 0) + { + if (nread != -EINTR) + { + ierr("ERROR: read failed: %d\n", (int)nread); + } + + return nread; + } + else if (nread < NJOYSTICK_CHANNELS * sizeof(struct adc_msg_s)) + { + ierr("ERROR: read too small: %ld\n", (long)nread); + return -EIO; + } + + /* Sample and the raw analog inputs */ + +#ifdef CONFIG_ADC_DMA + have = 0; + +#else + /* If DMA is not supported, then we will have only a single ADC channel */ + + have = 2; + sample->as_y = 0; +#endif + + for (i = 0, offset = 0; + i < MAX_ADC_CHANNELS && offset < nread && have != 3; + i++, offset += sizeof(struct adc_msg_s)) + { + ptr = &adcmsg[i]; + + /* Is this one of the channels that we need? */ + + if ((have & 1) == 0 && ptr->am_channel == 0) + { + int32_t tmp = ptr->am_data; + sample->as_x = (int16_t)tmp; + have |= 1; + + iinfo("X sample: %ld -> %d\n", (long)tmp, (int)sample->as_x); + } + +#ifdef CONFIG_ADC_DMA + if ((have & 2) == 0 && ptr->am_channel == 1) + { + int32_t tmp = ptr->am_data; + sample->as_y = (int16_t)tmp; + have |= 2; + + iinfo("Y sample: %ld -> %d\n", (long)tmp, (int)sample->as_y); + } +#endif + } + + if (have != 3) + { + ierr("ERROR: Could not find joystick channels\n"); + return -EIO; + } + +#else + /* ADC support is disabled */ + + sample->as_x = 0; + sample->as_y = 0; +#endif + + /* Sample the discrete button inputs */ + + sample->as_buttons = ajoy_buttons(lower); + iinfo("Returning: %02x\n", sample->as_buttons); + return OK; +} + +/**************************************************************************** + * Name: ajoy_buttons + * + * Description: + * Return the current state of button data (only) + * + ****************************************************************************/ + +static ajoy_buttonset_t +ajoy_buttons(const struct ajoy_lowerhalf_s *lower) +{ + ajoy_buttonset_t ret = 0; + int i; + + /* Read each joystick GPIO value */ + + for (i = 0; i < AJOY_NGPIOS; i++) + { + /* Button outputs are pulled high. So a sensed low level means that the + * button is pressed. + */ + + if (!stm32_gpioread(g_joygpio[i])) + { + ret |= (1 << i); + } + } + + iinfo("Returning: %02x\n", ret); + return ret; +} + +/**************************************************************************** + * Name: ajoy_enable + * + * Description: + * Enable interrupts on the selected set of joystick buttons. And empty + * set will disable all interrupts. + * + ****************************************************************************/ + +static void ajoy_enable(const struct ajoy_lowerhalf_s *lower, + ajoy_buttonset_t press, ajoy_buttonset_t release, + ajoy_handler_t handler, void *arg) +{ + irqstate_t flags; + ajoy_buttonset_t either = press | release; + ajoy_buttonset_t bit; + bool rising; + bool falling; + int i; + + /* Start with all interrupts disabled */ + + flags = enter_critical_section(); + ajoy_disable(); + + iinfo("press: %02x release: %02x handler: %p arg: %p\n", + press, release, handler, arg); + + /* If no events are indicated or if no handler is provided, then this + * must really be a request to disable interrupts. + */ + + if (either && handler) + { + /* Save the new the handler and argument */ + + g_ajoyhandler = handler; + g_ajoyarg = arg; + + /* Check each GPIO. */ + + for (i = 0; i < AJOY_NGPIOS; i++) + { + /* Enable interrupts on each pin that has either a press or + * release event associated with it. + */ + + bit = (1 << i); + if ((either & bit) != 0) + { + /* Active low so a press corresponds to a falling edge and + * a release corresponds to a rising edge. + */ + + falling = ((press & bit) != 0); + rising = ((release & bit) != 0); + + iinfo("GPIO %d: rising: %d falling: %d\n", + i, rising, falling); + + stm32_gpiosetevent(g_joygpio[i], rising, falling, + true, ajoy_interrupt, NULL); + } + } + } + + leave_critical_section(flags); +} + +/**************************************************************************** + * Name: ajoy_disable + * + * Description: + * Disable all joystick interrupts + * + ****************************************************************************/ + +static void ajoy_disable(void) +{ + irqstate_t flags; + int i; + + /* Disable each joystick interrupt */ + + flags = enter_critical_section(); + for (i = 0; i < AJOY_NGPIOS; i++) + { + stm32_gpiosetevent(g_joygpio[i], false, false, false, NULL, NULL); + } + + leave_critical_section(flags); + + /* Nullify the handler and argument */ + + g_ajoyhandler = NULL; + g_ajoyarg = NULL; +} + +/**************************************************************************** + * Name: ajoy_interrupt + * + * Description: + * Discrete joystick interrupt handler + * + ****************************************************************************/ + +static int ajoy_interrupt(int irq, void *context, void *arg) +{ + DEBUGASSERT(g_ajoyhandler); + + if (g_ajoyhandler) + { + g_ajoyhandler(&g_ajoylower, g_ajoyarg); + } + + return OK; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_ajoy_initialize + * + * Description: + * Initialize and register the button joystick driver + * + ****************************************************************************/ + +int board_ajoy_initialize(void) +{ + int ret; + int i; + +#ifndef NO_JOYSTICK_ADC + iinfo("Initialize ADC driver: /dev/adc0\n"); + + /* Open the ADC driver for reading. + * NOTE: The ADC driver was initialized earlier in the bring-up sequence. + */ + + ret = file_open(&g_adcfile, "/dev/adc0", O_RDONLY); + if (ret < 0) + { + ierr("ERROR: Failed to open /dev/adc0: %d\n", ret); + return ret; + } +#endif + + /* Configure the GPIO pins as interrupting inputs. NOTE: This is + * unnecessary for interrupting pins since it will also be done by + * stm32_gpiosetevent(). + */ + + for (i = 0; i < AJOY_NGPIOS; i++) + { + /* Configure the PIO as an input */ + + stm32_configgpio(g_joygpio[i]); + } + + /* Register the joystick device as /dev/ajoy0 */ + + iinfo("Initialize joystick driver: /dev/ajoy0\n"); + + ret = ajoy_register("/dev/ajoy0", &g_ajoylower); + if (ret < 0) + { + ierr("ERROR: ajoy_register failed: %d\n", ret); +#ifndef NO_JOYSTICK_ADC + file_close(&g_adcfile); +#endif + } + + return ret; +} + +#endif /* CONFIG_INPUT_AJOYSTICK */ diff --git a/boards/arm/stm32f4/nucleo-f446re/src/stm32_autoleds.c b/boards/arm/stm32f4/nucleo-f446re/src/stm32_autoleds.c new file mode 100644 index 0000000000000..ab223ac8a5284 --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f446re/src/stm32_autoleds.c @@ -0,0 +1,82 @@ +/**************************************************************************** + * boards/arm/stm32f4/nucleo-f446re/src/stm32_autoleds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32.h" +#include "nucleo-f446re.h" + +#ifdef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_autoled_initialize + ****************************************************************************/ + +void board_autoled_initialize(void) +{ + /* Configure LD2 GPIO for output */ + + stm32_configgpio(GPIO_LD2); +} + +/**************************************************************************** + * Name: board_autoled_on + ****************************************************************************/ + +void board_autoled_on(int led) +{ + if (led == 1) + { + stm32_gpiowrite(GPIO_LD2, true); + } +} + +/**************************************************************************** + * Name: board_autoled_off + ****************************************************************************/ + +void board_autoled_off(int led) +{ + if (led == 1) + { + stm32_gpiowrite(GPIO_LD2, false); + } +} + +#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32f4/nucleo-f446re/src/stm32_boot.c b/boards/arm/stm32f4/nucleo-f446re/src/stm32_boot.c new file mode 100644 index 0000000000000..9ac3db6e971d8 --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f446re/src/stm32_boot.c @@ -0,0 +1,103 @@ +/**************************************************************************** + * boards/arm/stm32f4/nucleo-f446re/src/stm32_boot.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include +#include +#include + +#include + +#include "arm_internal.h" +#include "nucleo-f446re.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_boardinitialize + * + * Description: + * All STM32 architectures must provide the following entry point. This + * entry point is called early in the initialization -- after all memory + * has been configured and mapped but before any devices have been + * initialized. + * + ****************************************************************************/ + +void stm32_boardinitialize(void) +{ +#ifdef CONFIG_ARCH_LEDS + /* Configure on-board LEDs if LED support has been selected. */ + + board_autoled_initialize(); +#endif + +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || \ + defined(CONFIG_STM32_SPI3) + /* Configure SPI chip selects if 1) SP2 is not disabled, and 2) the weak + * function stm32_spidev_initialize() has been brought into the link. + */ + + stm32_spidev_initialize(); +#endif + +#if defined(CONFIG_USBDEV) && defined(CONFIG_STM32_USB) + /* Initialize USB is 1) USBDEV is selected, 2) the USB controller is not + * disabled, and 3) the weak function stm32_usbinitialize() has been + * broughtvinto the build. + */ + + stm32_usbinitialize(); +#endif +} + +/**************************************************************************** + * Name: board_late_initialize + * + * Description: + * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_late_initialize(). board_late_initialize() will + * be called immediately after up_initialize() is called and just before + * the initial application is started. This additional initialization + * phase may be used, for example, to initialize board-specific device + * drivers. + * + ****************************************************************************/ + +#ifdef CONFIG_BOARD_LATE_INITIALIZE +void board_late_initialize(void) +{ + /* Perform board-specific initialization */ + + stm32_bringup(); +} +#endif diff --git a/boards/arm/stm32f4/nucleo-f446re/src/stm32_bringup.c b/boards/arm/stm32f4/nucleo-f446re/src/stm32_bringup.c new file mode 100644 index 0000000000000..13cf8656c7ca4 --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f446re/src/stm32_bringup.c @@ -0,0 +1,304 @@ +/**************************************************************************** + * boards/arm/stm32f4/nucleo-f446re/src/stm32_bringup.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include +#include +#include + +#include + +#include + +#ifdef CONFIG_PULSECOUNT +# include "stm32_pulsecount.h" +#endif + +#ifdef CONFIG_INPUT_BUTTONS +# include +#endif + +#ifdef CONFIG_SENSORS_QENCODER +# include "board_qencoder.h" +#endif + +#ifdef CONFIG_SENSORS_HALL3PHASE +# include "board_hall3ph.h" +#endif + +#ifdef CONFIG_VIDEO_FB +# include +#endif + +#ifdef CONFIG_USERLED +# include +#endif + +#ifdef CONFIG_STM32_ROMFS +# include "stm32_romfs.h" +#endif +#include "nucleo-f446re.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_bringup + * + * Description: + * Perform architecture-specific initialization + * + * CONFIG_BOARD_LATE_INITIALIZE=y : + * Called from board_late_initialize(). + * + ****************************************************************************/ + +int stm32_bringup(void) +{ +#ifdef CONFIG_PULSECOUNT + struct pulsecount_lowerhalf_s *pulsecount; +#endif + int ret = OK; + +#ifdef CONFIG_FS_PROCFS + /* Mount the procfs file system */ + + ret = nx_mount(NULL, STM32_PROCFS_MOUNTPOINT, "procfs", 0, NULL); + if (ret < 0) + { + syslog(LOG_ERR, + "ERROR: Failed to mount the PROC filesystem: %d\n", ret); + } +#endif /* CONFIG_FS_PROCFS */ + +#ifdef CONFIG_STM32_ROMFS + ret = stm32_romfs_initialize(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to mount romfs at %s: %d\n", + CONFIG_STM32_ROMFS_MOUNTPOINT, ret); + } +#endif + +#ifdef CONFIG_INPUT_BUTTONS + /* Register the BUTTON driver */ + + ret = btn_lower_initialize("/dev/buttons"); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: btn_lower_initialize() failed: %d\n", ret); + } +#endif + +#ifdef HAVE_MMCSD + /* First, get an instance of the SDIO interface */ + + g_sdio = sdio_initialize(CONFIG_NSH_MMCSDSLOTNO); + if (!g_sdio) + { + syslog(LOG_ERR, "ERROR: Failed to initialize SDIO slot %d\n", + CONFIG_NSH_MMCSDSLOTNO); + return -ENODEV; + } + + /* Now bind the SDIO interface to the MMC/SD driver */ + + ret = mmcsd_slotinitialize(CONFIG_NSH_MMCSDMINOR, g_sdio); + if (ret != OK) + { + syslog(LOG_ERR, + "ERROR: Failed to bind SDIO to the MMC/SD driver: %d\n", + ret); + return ret; + } + + /* Then let's guess and say that there is a card in the slot. There is no + * card detect GPIO. + */ + + sdio_mediachange(g_sdio, true); + + syslog(LOG_INFO, "[boot] Initialized SDIO\n"); +#endif + +#ifdef CONFIG_STM32_FOC + /* Initialize and register the FOC device */ + + ret = stm32_foc_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_foc_setup failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_ADC + /* Initialize ADC and register the ADC driver. */ + + ret = stm32_adc_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_adc_setup failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_PULSECOUNT + /* Initialize and register the pulse count driver. */ + + pulsecount = stm32_pulsecountinitialize(8); + if (pulsecount == NULL) + { + syslog(LOG_ERR, "ERROR: stm32_pulsecountinitialize failed\n"); + return -ENODEV; + } + + ret = pulsecount_register("/dev/pulsecount0", pulsecount); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: pulsecount_register failed: %d\n", ret); + return ret; + } +#endif + +#ifdef CONFIG_STM32_CAN_CHARDRIVER + /* Initialize CAN and register the CAN driver. */ + + ret = stm32_can_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_can_setup failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_STM32_CAN_SOCKET + /* Initialize CAN socket interface */ + + ret = stm32_cansock_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_cansock_setup failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_VIDEO_FB + /* Initialize and register the framebuffer driver */ + + ret = fb_register(0, 0); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: fb_register() failed %d\n", ret); + } +#endif + +#ifdef CONFIG_SENSORS_QENCODER + /* Initialize and register the qencoder driver */ + + ret = board_qencoder_initialize(0, CONFIG_NUCLEO_F446RE_QETIMER); + if (ret != OK) + { + syslog(LOG_ERR, + "ERROR: Failed to register the qencoder: %d\n", + ret); + return ret; + } +#endif + +#ifdef CONFIG_SENSORS_HALL3PHASE + /* Initialize and register the 3-phase Hall effect sensor driver */ + + ret = board_hall3ph_initialize(0, GPIO_HALL_PHA, GPIO_HALL_PHB, + GPIO_HALL_PHC); + if (ret != OK) + { + syslog(LOG_ERR, + "ERROR: Failed to register the hall : %d\n", + ret); + return ret; + } +#endif + +#ifdef CONFIG_INPUT_AJOYSTICK + /* Initialize and register the joystick driver */ + + ret = board_ajoy_initialize(); + if (ret != OK) + { + syslog(LOG_ERR, + "ERROR: Failed to register the joystick driver: %d\n", + ret); + return ret; + } +#endif + +#ifdef CONFIG_PWM + /* Initialize PWM and register the PWM device */ + + ret = stm32_pwm_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_pwm_setup() failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_DEV_GPIO + /* Initialize GPIO driver */ + + ret = stm32_gpio_initialize(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_gpio_initialize() failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_USERLED + /* Register the LED driver */ + + ret = userled_lower_initialize("/dev/userleds"); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: userled_lower_initialize() failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_DAC + /* Initialize DAC and register the DAC driver. */ + + ret = stm32_dac_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to start ADC1: %d\n", ret); + } +#endif + + return ret; +} diff --git a/boards/arm/stm32f4/nucleo-f446re/src/stm32_buttons.c b/boards/arm/stm32f4/nucleo-f446re/src/stm32_buttons.c new file mode 100644 index 0000000000000..9b267ab7ae7ce --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f446re/src/stm32_buttons.c @@ -0,0 +1,115 @@ +/**************************************************************************** + * boards/arm/stm32f4/nucleo-f446re/src/stm32_buttons.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include +#include + +#include "nucleo-f446re.h" + +#ifdef CONFIG_ARCH_BUTTONS + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_button_initialize + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. + * + ****************************************************************************/ + +uint32_t board_button_initialize(void) +{ + /* Configure the single button as an input. NOTE that EXTI interrupts are + * also configured for the pin. + */ + + stm32_configgpio(GPIO_BTN_USER); + return NUM_BUTTONS; +} + +/**************************************************************************** + * Name: board_buttons + ****************************************************************************/ + +uint32_t board_buttons(void) +{ + /* Check that state of each USER button. A LOW value means that the key is + * pressed. + */ + + bool released = stm32_gpioread(GPIO_BTN_USER); + return !released; +} + +/**************************************************************************** + * Button support. + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. + * + * After board_button_initialize() has been called, board_buttons() may be + * called to collect the state of all buttons. board_buttons() returns an + * 32-bit bit set with each bit associated with a button. See the + * BUTTON_*_BIT definitions in board.h for the meaning of each bit. + * + * board_button_irq() may be called to register an interrupt handler that + * will be called when a button is depressed or released. The ID value is + * a button enumeration value that uniquely identifies a button resource. + * See the BUTTON_* definitions in board.h for the meaning of enumeration + * value. + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_IRQBUTTONS +int board_button_irq(int id, xcpt_t irqhandler, void *arg) +{ + int ret = -EINVAL; + + if (id == BUTTON_USER) + { + ret = stm32_gpiosetevent(GPIO_BTN_USER, true, true, true, irqhandler, + arg); + } + + return ret; +} +#endif +#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/stm32f4/nucleo-f446re/src/stm32_can.c b/boards/arm/stm32f4/nucleo-f446re/src/stm32_can.c new file mode 100644 index 0000000000000..bb052a7c12464 --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f446re/src/stm32_can.c @@ -0,0 +1,117 @@ +/**************************************************************************** + * boards/arm/stm32f4/nucleo-f446re/src/stm32_can.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32.h" +#include "stm32_can.h" +#include "nucleo-f446re.h" + +#ifdef CONFIG_CAN + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +#if !defined(CONFIG_STM32_CAN1) && !defined(CONFIG_STM32_CAN2) +# error "No CAN is enable. Please enable at least one CAN device" +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_can_setup + * + * Description: + * Initialize CAN and register the CAN device + * + ****************************************************************************/ + +int stm32_can_setup(void) +{ + struct can_dev_s *can; + int ret; + +#ifdef CONFIG_STM32_CAN1 + + /* Call stm32_caninitialize() to get an instance of the CAN interface */ + + can = stm32_caninitialize(1); + if (can == NULL) + { + canerr("ERROR: Failed to get CAN interface\n"); + return -ENODEV; + } + + /* Register the CAN driver at "/dev/can0" */ + + ret = can_register("/dev/can0", can); + if (ret < 0) + { + canerr("ERROR: can_register failed: %d\n", ret); + return ret; + } + +#endif +#ifdef CONFIG_STM32_CAN2 + + /* Call stm32_caninitialize() to get an instance of the CAN interface */ + + can = stm32_caninitialize(2); + if (can == NULL) + { + canerr("ERROR: Failed to get CAN interface\n"); + return -ENODEV; + } + + /* Register the CAN driver at "/dev/can1" */ + + ret = can_register("/dev/can1", can); + if (ret < 0) + { + canerr("ERROR: can_register failed: %d\n", ret); + return ret; + } + +#endif + UNUSED(ret); + UNUSED(can); + return OK; +} + +#endif /* CONFIG_CAN */ diff --git a/boards/arm/stm32f4/nucleo-f446re/src/stm32_cansock.c b/boards/arm/stm32f4/nucleo-f446re/src/stm32_cansock.c new file mode 100644 index 0000000000000..a41b61f230761 --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f446re/src/stm32_cansock.c @@ -0,0 +1,85 @@ +/**************************************************************************** + * boards/arm/stm32f4/nucleo-f446re/src/stm32_cansock.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include "stm32_can.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +#if !defined(CONFIG_STM32_CAN1) && !defined(CONFIG_STM32_CAN2) +# error "No CAN is enable. Please enable at least one CAN device" +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_cansock_setup + * + * Description: + * Initialize CAN socket interface + * + ****************************************************************************/ + +int stm32_cansock_setup(void) +{ + int ret = OK; + + UNUSED(ret); + +#ifdef CONFIG_STM32_CAN1 + /* Call stm32_caninitialize() to get an instance of the CAN interface */ + + ret = stm32_cansockinitialize(1); + if (ret < 0) + { + canerr("ERROR: Failed to get CAN interface %d\n", ret); + goto errout; + } +#endif + +#ifdef CONFIG_STM32_CAN2 + /* Call stm32_caninitialize() to get an instance of the CAN interface */ + + ret = stm32_cansockinitialize(2); + if (ret < 0) + { + canerr("ERROR: Failed to get CAN interface %d\n", ret); + goto errout; + } +#endif + +errout: + return ret; +} diff --git a/boards/arm/stm32f4/nucleo-f446re/src/stm32_dac.c b/boards/arm/stm32f4/nucleo-f446re/src/stm32_dac.c new file mode 100644 index 0000000000000..bb835a90f0423 --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f446re/src/stm32_dac.c @@ -0,0 +1,112 @@ +/**************************************************************************** + * boards/arm/stm32f4/nucleo-f446re/src/stm32_dac.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include + +#include +#include + +#include "stm32_dac.h" +#include "nucleo-f446re.h" + +#ifdef CONFIG_DAC + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#ifdef CONFIG_STM32_DAC1CH1 +static struct dac_dev_s *g_dac1; +#endif + +#ifdef CONFIG_STM32_DAC1CH2 +static struct dac_dev_s *g_dac2; +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_dac_setup + * + * Description: + * Initialize and register the DAC driver. + * + * Input parameters: + * devpath - The full path to the driver to register. E.g., "/dev/dac0" + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +int stm32_dac_setup(void) +{ + int ret; +#ifdef CONFIG_STM32_DAC1CH1 + g_dac1 = stm32_dacinitialize(1); + if (g_dac1 == NULL) + { + aerr("ERROR: Failed to get DAC interface\n"); + return -ENODEV; + } + + /* Register the DAC driver at "/dev/dac0" */ + + ret = dac_register("/dev/dac0", g_dac1); + if (ret < 0) + { + aerr("ERROR: dac_register() failed: %d\n", ret); + return ret; + } + +#endif +#ifdef CONFIG_STM32_DAC1CH2 + g_dac2 = stm32_dacinitialize(2); + if (g_dac2 == NULL) + { + aerr("ERROR: Failed to get DAC interface\n"); + return -ENODEV; + } + + /* Register the DAC driver at "/dev/dac1" */ + + ret = dac_register("/dev/dac1", g_dac2); + if (ret < 0) + { + aerr("ERROR: dac_register() failed: %d\n", ret); + return ret; + } +#endif + + UNUSED(ret); + return OK; +} + +#endif /* CONFIG_DAC */ diff --git a/boards/arm/stm32/nucleo-f446re/src/stm32_foc_ihm08m1.c b/boards/arm/stm32f4/nucleo-f446re/src/stm32_foc_ihm08m1.c similarity index 98% rename from boards/arm/stm32/nucleo-f446re/src/stm32_foc_ihm08m1.c rename to boards/arm/stm32f4/nucleo-f446re/src/stm32_foc_ihm08m1.c index 99857b6aa012a..047dca4ffa0a5 100644 --- a/boards/arm/stm32/nucleo-f446re/src/stm32_foc_ihm08m1.c +++ b/boards/arm/stm32f4/nucleo-f446re/src/stm32_foc_ihm08m1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f446re/src/stm32_foc_ihm08m1.c + * boards/arm/stm32f4/nucleo-f446re/src/stm32_foc_ihm08m1.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f4/nucleo-f446re/src/stm32_gpio.c b/boards/arm/stm32f4/nucleo-f446re/src/stm32_gpio.c new file mode 100644 index 0000000000000..46fba657f50cd --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f446re/src/stm32_gpio.c @@ -0,0 +1,343 @@ +/**************************************************************************** + * boards/arm/stm32f4/nucleo-f446re/src/stm32_gpio.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include +#include + +#include + +#include "chip.h" +#include "stm32.h" +#include "nucleo-f446re.h" + +#if defined(CONFIG_DEV_GPIO) && !defined(CONFIG_GPIO_LOWER_HALF) + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +struct stm32gpio_dev_s +{ + struct gpio_dev_s gpio; + uint8_t id; +}; + +struct stm32gpint_dev_s +{ + struct stm32gpio_dev_s stm32gpio; + pin_interrupt_t callback; +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +#if BOARD_NGPIOIN > 0 +static int gpin_read(struct gpio_dev_s *dev, bool *value); +#endif +#if BOARD_NGPIOOUT > 0 +static int gpout_read(struct gpio_dev_s *dev, bool *value); +static int gpout_write(struct gpio_dev_s *dev, bool value); +#endif +#if BOARD_NGPIOINT > 0 +static int gpint_read(struct gpio_dev_s *dev, bool *value); +static int gpint_attach(struct gpio_dev_s *dev, + pin_interrupt_t callback); +static int gpint_enable(struct gpio_dev_s *dev, bool enable); +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#if BOARD_NGPIOIN > 0 +static const struct gpio_operations_s gpin_ops = +{ + .go_read = gpin_read, + .go_write = NULL, + .go_attach = NULL, + .go_enable = NULL, +}; +#endif + +#if BOARD_NGPIOOUT > 0 +static const struct gpio_operations_s gpout_ops = +{ + .go_read = gpout_read, + .go_write = gpout_write, + .go_attach = NULL, + .go_enable = NULL, +}; +#endif + +#if BOARD_NGPIOINT > 0 +static const struct gpio_operations_s gpint_ops = +{ + .go_read = gpint_read, + .go_write = NULL, + .go_attach = gpint_attach, + .go_enable = gpint_enable, +}; +#endif + +#if BOARD_NGPIOIN > 0 +/* This array maps the GPIO pins used as INPUT */ + +static const uint32_t g_gpioinputs[BOARD_NGPIOIN] = +{ + GPIO_IN1, +}; + +static struct stm32gpio_dev_s g_gpin[BOARD_NGPIOIN]; +#endif + +#if BOARD_NGPIOOUT +/* This array maps the GPIO pins used as OUTPUT */ + +static const uint32_t g_gpiooutputs[BOARD_NGPIOOUT] = +{ + GPIO_OUT1, +}; + +static struct stm32gpio_dev_s g_gpout[BOARD_NGPIOOUT]; +#endif + +#if BOARD_NGPIOINT > 0 +/* This array maps the GPIO pins used as INTERRUPT INPUTS */ + +static const uint32_t g_gpiointinputs[BOARD_NGPIOINT] = +{ + GPIO_INT1, +}; + +static struct stm32gpint_dev_s g_gpint[BOARD_NGPIOINT]; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +#if BOARD_NGPIOINT > 0 +static int stm32gpio_interrupt(int irq, void *context, void *arg) +{ + struct stm32gpint_dev_s *stm32gpint = + (struct stm32gpint_dev_s *)arg; + + DEBUGASSERT(stm32gpint != NULL && stm32gpint->callback != NULL); + gpioinfo("Interrupt! callback=%p\n", stm32gpint->callback); + + stm32gpint->callback(&stm32gpint->stm32gpio.gpio, + stm32gpint->stm32gpio.id); + return OK; +} +#endif + +#if BOARD_NGPIOIN > 0 +static int gpin_read(struct gpio_dev_s *dev, bool *value) +{ + struct stm32gpio_dev_s *stm32gpio = + (struct stm32gpio_dev_s *)dev; + + DEBUGASSERT(stm32gpio != NULL && value != NULL); + DEBUGASSERT(stm32gpio->id < BOARD_NGPIOIN); + gpioinfo("Reading...\n"); + + *value = stm32_gpioread(g_gpioinputs[stm32gpio->id]); + return OK; +} +#endif + +#if BOARD_NGPIOOUT > 0 +static int gpout_read(struct gpio_dev_s *dev, bool *value) +{ + struct stm32gpio_dev_s *stm32gpio = + (struct stm32gpio_dev_s *)dev; + + DEBUGASSERT(stm32gpio != NULL && value != NULL); + DEBUGASSERT(stm32gpio->id < BOARD_NGPIOOUT); + gpioinfo("Reading...\n"); + + *value = stm32_gpioread(g_gpiooutputs[stm32gpio->id]); + return OK; +} + +static int gpout_write(struct gpio_dev_s *dev, bool value) +{ + struct stm32gpio_dev_s *stm32gpio = + (struct stm32gpio_dev_s *)dev; + + DEBUGASSERT(stm32gpio != NULL); + DEBUGASSERT(stm32gpio->id < BOARD_NGPIOOUT); + gpioinfo("Writing %d\n", (int)value); + + stm32_gpiowrite(g_gpiooutputs[stm32gpio->id], value); + return OK; +} +#endif + +#if BOARD_NGPIOINT > 0 +static int gpint_read(struct gpio_dev_s *dev, bool *value) +{ + struct stm32gpint_dev_s *stm32gpint = + (struct stm32gpint_dev_s *)dev; + + DEBUGASSERT(stm32gpint != NULL && value != NULL); + DEBUGASSERT(stm32gpint->stm32gpio.id < BOARD_NGPIOINT); + gpioinfo("Reading int pin...\n"); + + *value = stm32_gpioread(g_gpiointinputs[stm32gpint->stm32gpio.id]); + return OK; +} + +static int gpint_attach(struct gpio_dev_s *dev, + pin_interrupt_t callback) +{ + struct stm32gpint_dev_s *stm32gpint = + (struct stm32gpint_dev_s *)dev; + + gpioinfo("Attaching the callback\n"); + + /* Make sure the interrupt is disabled */ + + stm32_gpiosetevent(g_gpiointinputs[stm32gpint->stm32gpio.id], false, + false, false, NULL, NULL); + + gpioinfo("Attach %p\n", callback); + stm32gpint->callback = callback; + return OK; +} + +static int gpint_enable(struct gpio_dev_s *dev, bool enable) +{ + struct stm32gpint_dev_s *stm32gpint = + (struct stm32gpint_dev_s *)dev; + + if (enable) + { + if (stm32gpint->callback != NULL) + { + gpioinfo("Enabling the interrupt\n"); + + /* Configure the interrupt for rising edge */ + + stm32_gpiosetevent(g_gpiointinputs[stm32gpint->stm32gpio.id], + true, false, false, stm32gpio_interrupt, + &g_gpint[stm32gpint->stm32gpio.id]); + } + } + else + { + gpioinfo("Disable the interrupt\n"); + stm32_gpiosetevent(g_gpiointinputs[stm32gpint->stm32gpio.id], + false, false, false, NULL, NULL); + } + + return OK; +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_gpio_initialize + * + * Description: + * Initialize GPIO drivers for use with /apps/examples/gpio + * + ****************************************************************************/ + +int stm32_gpio_initialize(void) +{ + int i; + int pincount = 0; + +#if BOARD_NGPIOIN > 0 + for (i = 0; i < BOARD_NGPIOIN; i++) + { + /* Setup and register the GPIO pin */ + + g_gpin[i].gpio.gp_pintype = GPIO_INPUT_PIN; + g_gpin[i].gpio.gp_ops = &gpin_ops; + g_gpin[i].id = i; + gpio_pin_register(&g_gpin[i].gpio, pincount); + + /* Configure the pin that will be used as input */ + + stm32_configgpio(g_gpioinputs[i]); + + pincount++; + } +#endif + +#if BOARD_NGPIOOUT > 0 + for (i = 0; i < BOARD_NGPIOOUT; i++) + { + /* Setup and register the GPIO pin */ + + g_gpout[i].gpio.gp_pintype = GPIO_OUTPUT_PIN; + g_gpout[i].gpio.gp_ops = &gpout_ops; + g_gpout[i].id = i; + gpio_pin_register(&g_gpout[i].gpio, pincount); + + /* Configure the pin that will be used as output */ + + stm32_gpiowrite(g_gpiooutputs[i], 0); + stm32_configgpio(g_gpiooutputs[i]); + + pincount++; + } +#endif + +#if BOARD_NGPIOINT > 0 + for (i = 0; i < BOARD_NGPIOINT; i++) + { + /* Setup and register the GPIO pin */ + + g_gpint[i].stm32gpio.gpio.gp_pintype = GPIO_INTERRUPT_PIN; + g_gpint[i].stm32gpio.gpio.gp_ops = &gpint_ops; + g_gpint[i].stm32gpio.id = i; + gpio_pin_register(&g_gpint[i].stm32gpio.gpio, pincount); + + /* Configure the pin that will be used as interrupt input */ + + stm32_configgpio(g_gpiointinputs[i]); + + pincount++; + } +#endif + + return 0; +} +#endif /* CONFIG_DEV_GPIO && !CONFIG_GPIO_LOWER_HALF */ diff --git a/boards/arm/stm32/nucleo-f446re/src/stm32_ili9225.c b/boards/arm/stm32f4/nucleo-f446re/src/stm32_ili9225.c similarity index 98% rename from boards/arm/stm32/nucleo-f446re/src/stm32_ili9225.c rename to boards/arm/stm32f4/nucleo-f446re/src/stm32_ili9225.c index 435ba03a61295..5966852282063 100644 --- a/boards/arm/stm32/nucleo-f446re/src/stm32_ili9225.c +++ b/boards/arm/stm32f4/nucleo-f446re/src/stm32_ili9225.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f446re/src/stm32_ili9225.c + * boards/arm/stm32f4/nucleo-f446re/src/stm32_ili9225.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f4/nucleo-f446re/src/stm32_pwm.c b/boards/arm/stm32f4/nucleo-f446re/src/stm32_pwm.c new file mode 100644 index 0000000000000..e091f026a7124 --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f446re/src/stm32_pwm.c @@ -0,0 +1,134 @@ +/**************************************************************************** + * boards/arm/stm32f4/nucleo-f446re/src/stm32_pwm.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32_pwm.h" +#include "nucleo-f446re.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_pwm_setup + * + * Description: + * Initialize PWM and register the PWM device. + * + * Return Value: + * OK on success; a negated errno value on failure. + * + ****************************************************************************/ + +int stm32_pwm_setup(void) +{ +#ifdef CONFIG_PWM + struct pwm_lowerhalf_s *pwm; + int ret; + + /* Call stm32_pwminitialize() to get an instance of the PWM interface */ + +#if defined(CONFIG_STM32_TIM1_PWM) + pwm = stm32_pwminitialize(1); + if (!pwm) + { + pwmerr("ERROR: Failed to get the STM32 PWM lower half\n"); + return -ENODEV; + } + + ret = pwm_register("/dev/pwm0", pwm); + if (ret < 0) + { + pwmerr("ERROR: pwm_register failed: %d\n", ret); + return ret; + } +#endif + +#if defined(CONFIG_STM32_TIM2_PWM) + pwm = stm32_pwminitialize(2); + if (!pwm) + { + pwmerr("ERROR: Failed to get the STM32 PWM lower half\n"); + return -ENODEV; + } + + ret = pwm_register("/dev/pwm1", pwm); + if (ret < 0) + { + pwmerr("ERROR: pwm_register failed: %d\n", ret); + return ret; + } +#endif + +#if defined(CONFIG_STM32_TIM3_PWM) + pwm = stm32_pwminitialize(3); + if (!pwm) + { + pwmerr("ERROR: Failed to get the STM32 PWM lower half\n"); + return -ENODEV; + } + + ret = pwm_register("/dev/pwm2", pwm); + if (ret < 0) + { + pwmerr("ERROR: pwm_register failed: %d\n", ret); + return ret; + } +#endif + +#if defined(CONFIG_STM32_TIM4_PWM) + pwm = stm32_pwminitialize(4); + if (!pwm) + { + pwmerr("ERROR: Failed to get the STM32 PWM lower half\n"); + return -ENODEV; + } + + ret = pwm_register("/dev/pwm3", pwm); + if (ret < 0) + { + pwmerr("ERROR: pwm_register failed: %d\n", ret); + return ret; + } + +#endif + + return OK; +#else + return -ENODEV; +#endif +} diff --git a/boards/arm/stm32f4/nucleo-f446re/src/stm32_spi.c b/boards/arm/stm32f4/nucleo-f446re/src/stm32_spi.c new file mode 100644 index 0000000000000..65b9768161fff --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f446re/src/stm32_spi.c @@ -0,0 +1,236 @@ +/**************************************************************************** + * boards/arm/stm32f4/nucleo-f446re/src/stm32_spi.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include + +#include "arm_internal.h" +#include "chip.h" +#include "stm32.h" + +#include "nucleo-f446re.h" + +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || \ + defined(CONFIG_STM32_SPI3) + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/* Global driver instances */ + +#ifdef CONFIG_STM32_SPI1 +struct spi_dev_s *g_spi1; +#endif +#ifdef CONFIG_STM32_SPI2 +struct spi_dev_s *g_spi2; +#endif +#ifdef CONFIG_STM32_SPI3 +struct spi_dev_s *g_spi3; +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_spidev_initialize + * + * Description: + * Called to configure SPI chip select GPIO pins for the Nucleo-F401RE and + * Nucleo-F411RE boards. + * + ****************************************************************************/ + +void weak_function stm32_spidev_initialize(void) +{ +#ifdef CONFIG_STM32_SPI1 + /* Configure SPI-based devices */ + + g_spi1 = stm32_spibus_initialize(1); + if (!g_spi1) + { + spierr("ERROR: FAILED to initialize SPI port 1\n"); + } + +#ifdef HAVE_MMCSD + stm32_configgpio(GPIO_SPI_CS_SD_CARD); +#endif +#endif + +#ifdef CONFIG_STM32_SPI2 + /* Configure SPI-based devices */ + + g_spi2 = stm32_spibus_initialize(2); +#endif + +#ifdef CONFIG_STM32_SPI3 + /* Configure SPI-based devices */ + + g_spi3 = stm32_spibus_initialize(3); + +#ifdef HAVE_LCD + stm32_configgpio(GPIO_LCD_CS); + stm32_configgpio(GPIO_LCD_RS); +#endif + +#endif +} + +/**************************************************************************** + * Name: stm32_spi1/2/3select and stm32_spi1/2/3status + * + * Description: + * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status + * must be provided by board-specific logic. They are implementations of + * the select and status methods of the SPI interface defined by struct + * spi_ops_s (see include/nuttx/spi/spi.h). All other methods (including + * stm32_spibus_initialize()) are provided by common STM32 logic. To use + * this common SPI logic on your board: + * + * 1. Provide logic in stm32_boardinitialize() to configure SPI chip + * select pins. + * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() functions + * in your board-specific logic. These functions will perform chip + * selection and status operations using GPIOs in the way your board is + * configured. + * 3. Add a calls to stm32_spibus_initialize() in your low level + * application initialization logic + * 4. The handle returned by stm32_spibus_initialize() may then be used to + * bind the SPI driver to higher level logic (e.g., calling + * mmcsd_spislotinitialize(), for example, will bind the SPI driver to + * the SPI MMC/SD driver). + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_SPI1 +void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, + bool selected) +{ + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); + +#ifdef HAVE_MMCSD + if (devid == SPIDEV_MMCSD(0)) + { + stm32_gpiowrite(GPIO_SPI_CS_SD_CARD, !selected); + } +#endif +} + +uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} +#endif + +#ifdef CONFIG_STM32_SPI2 +void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid, + bool selected) +{ + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); +} + +uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} +#endif + +#ifdef CONFIG_STM32_SPI3 +void stm32_spi3select(struct spi_dev_s *dev, uint32_t devid, + bool selected) +{ + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); + +#ifdef HAVE_LCD + stm32_gpiowrite(GPIO_LCD_CS, !selected); +#endif +} + +uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} +#endif + +/**************************************************************************** + * Name: stm32_spi1cmddata + * + * Description: + * Set or clear the SH1101A A0 or SD1306 D/C n bit to select data (true) + * or command (false). This function must be provided by platform-specific + * logic. This is an implementation of the cmddata method of the SPI + * interface defined by struct spi_ops_s (see include/nuttx/spi/spi.h). + * + * Input Parameters: + * + * spi - SPI device that controls the bus the device that requires the CMD/ + * DATA selection. + * devid - If there are multiple devices on the bus, this selects which one + * to select cmd or data. NOTE: This design restricts, for example, + * one one SPI display per SPI bus. + * cmd - true: select command; false: select data + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_SPI_CMDDATA +#ifdef CONFIG_STM32_SPI1 +int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) +{ + return OK; +} +#endif + +#ifdef CONFIG_STM32_SPI2 +int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) +{ + return OK; +} +#endif + +#ifdef CONFIG_STM32_SPI3 +int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) +{ + stm32_gpiowrite(GPIO_LCD_RS, !cmd); + return OK; +} +#endif +#endif /* CONFIG_SPI_CMDDATA */ + +#endif /* CONFIG_STM32_SPI1 || CONFIG_STM32_SPI2 || CONFIG_STM32_SPI3 */ diff --git a/boards/arm/stm32f4/nucleo-f446re/src/stm32_userleds.c b/boards/arm/stm32f4/nucleo-f446re/src/stm32_userleds.c new file mode 100644 index 0000000000000..8a2c4d80797cd --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f446re/src/stm32_userleds.c @@ -0,0 +1,105 @@ +/**************************************************************************** + * boards/arm/stm32f4/nucleo-f446re/src/stm32_userleds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32.h" +#include "nucleo-f446re.h" + +#ifndef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* This array maps an LED number to GPIO pin configuration */ + +static const uint32_t g_ledcfg[BOARD_NLEDS] = +{ + GPIO_LD2, +}; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_userled_initialize + ****************************************************************************/ + +uint32_t board_userled_initialize(void) +{ + int i; + + /* Configure LED GPIOs for output */ + + for (i = 0; i < BOARD_NLEDS; i++) + { + stm32_configgpio(g_ledcfg[i]); + } + + return BOARD_NLEDS; +} + +/**************************************************************************** + * Name: board_userled + ****************************************************************************/ + +void board_userled(int led, bool ledon) +{ + if ((unsigned)led < BOARD_NLEDS) + { + stm32_gpiowrite(g_ledcfg[led], ledon); + } +} + +/**************************************************************************** + * Name: board_userled_all + ****************************************************************************/ + +void board_userled_all(uint32_t ledset) +{ + int i; + + /* Configure LED GPIOs for output */ + + for (i = 0; i < BOARD_NLEDS; i++) + { + stm32_gpiowrite(g_ledcfg[i], (ledset & (1 << i)) != 0); + } +} + +#endif /* !CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32f4/odrive36/CMakeLists.txt b/boards/arm/stm32f4/odrive36/CMakeLists.txt new file mode 100644 index 0000000000000..61c57407acdf8 --- /dev/null +++ b/boards/arm/stm32f4/odrive36/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32f4/odrive36/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/arm/stm32/odrive36/Kconfig b/boards/arm/stm32f4/odrive36/Kconfig similarity index 100% rename from boards/arm/stm32/odrive36/Kconfig rename to boards/arm/stm32f4/odrive36/Kconfig diff --git a/boards/arm/stm32f4/odrive36/configs/nsh/defconfig b/boards/arm/stm32f4/odrive36/configs/nsh/defconfig new file mode 100644 index 0000000000000..fd7a87f012fc6 --- /dev/null +++ b/boards/arm/stm32f4/odrive36/configs/nsh/defconfig @@ -0,0 +1,43 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="odrive36" +CONFIG_ARCH_BOARD_ODRIVE36=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F405RG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=15272 +CONFIG_BUILTIN=y +CONFIG_EXAMPLES_HELLO=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_MM_REGIONS=2 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_NSH=y +CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f4/odrive36/configs/usbnsh/defconfig b/boards/arm/stm32f4/odrive36/configs/usbnsh/defconfig new file mode 100644 index 0000000000000..0ce1ca15d65e4 --- /dev/null +++ b/boards/arm/stm32f4/odrive36/configs/usbnsh/defconfig @@ -0,0 +1,55 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_DEV_CONSOLE is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="odrive36" +CONFIG_ARCH_BOARD_ODRIVE36=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F405RG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL_USBDEVCTRL=y +CONFIG_BOARD_LOOPSPERMSEC=15272 +CONFIG_BUILTIN=y +CONFIG_CDCACM=y +CONFIG_CDCACM_CONSOLE=y +CONFIG_CDCACM_RXBUFSIZE=256 +CONFIG_CDCACM_TXBUFSIZE=256 +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_EXAMPLES_HELLO=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_MM_REGIONS=2 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAMLOG=y +CONFIG_RAMLOG_BUFSIZE=4096 +CONFIG_RAMLOG_SYSLOG=y +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_STACK_COLORATION=y +CONFIG_START_DAY=27 +CONFIG_START_YEAR=2013 +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PWR=y +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_NSH=y +CONFIG_USBDEV=y diff --git a/boards/arm/stm32f4/odrive36/include/board.h b/boards/arm/stm32f4/odrive36/include/board.h new file mode 100644 index 0000000000000..88d42164eaf24 --- /dev/null +++ b/boards/arm/stm32f4/odrive36/include/board.h @@ -0,0 +1,212 @@ +/**************************************************************************** + * boards/arm/stm32f4/odrive36/include/board.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_STM32_ODRIVE36_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32_ODRIVE36_INCLUDE_BOARD_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#ifndef __ASSEMBLY__ +# include +#endif +#include "stm32_rcc.h" +#include "stm32.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Clocking *****************************************************************/ + +/* HSI - 16 MHz RC factory-trimmed + * LSI - 32 KHz RC (30-60KHz, uncalibrated) + * HSE - On-board crystal frequency is 8MHz + * LSE - 32.768 kHz + */ + +#define STM32_BOARD_XTAL 8000000ul + +#define STM32_HSI_FREQUENCY 16000000ul +#define STM32_LSI_FREQUENCY 32000 +#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL +#define STM32_LSE_FREQUENCY 32768 + +/* Main PLL Configuration. + * + * PLL source is HSE + * PLL_VCO = (STM32_HSE_FREQUENCY / PLLM) * PLLN + * = (8,000,000 / 8) * 336 + * = 336,000,000 + * SYSCLK = PLL_VCO / PLLP + * = 336,000,000 / 2 = 168,000,000 + * USB OTG FS, SDIO and RNG Clock + * = PLL_VCO / PLLQ + * = 48,000,000 + */ + +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(8) +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(336) +#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_2 +#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(7) + +#define STM32_SYSCLK_FREQUENCY 168000000ul + +/* AHB clock (HCLK) is SYSCLK (168MHz) */ + +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY + +/* APB1 clock (PCLK1) is HCLK/4 (42MHz) */ + +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd4 /* PCLK1 = HCLK / 4 */ +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/4) + +/* Timers driven from APB1 will be twice PCLK1 */ + +#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) + +/* APB2 clock (PCLK2) is HCLK/2 (84MHz) */ + +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLKd2 /* PCLK2 = HCLK / 2 */ +#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/2) + +/* Timers driven from APB2 will be twice PCLK2 */ + +#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM9_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM10_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM11_CLKIN (2*STM32_PCLK2_FREQUENCY) + +/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx + * otherwise frequency is 2xAPBx. + * Note: TIM1,8 are on APB2, others on APB1 + */ + +#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM2_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM3_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM4_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM5_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM6_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM7_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY + +/* DMA Channel/Stream Selections ********************************************/ + +/* ADC 1 */ + +#define ADC1_DMA_CHAN DMAMAP_ADC1_1 + +/* Alternate function pin selections ****************************************/ + +/* ADC */ + +#define GPIO_ADC1_IN4 GPIO_ADC1_IN4_0 +#define GPIO_ADC1_IN5 GPIO_ADC1_IN5_0 +#define GPIO_ADC1_IN6 GPIO_ADC1_IN6_0 +#define GPIO_ADC1_IN15 GPIO_ADC1_IN15_0 + +#define GPIO_ADC2_IN10 GPIO_ADC2_IN10_0 +#define GPIO_ADC2_IN11 GPIO_ADC2_IN11_0 +#define GPIO_ADC2_IN12 GPIO_ADC2_IN13_0 + +#define GPIO_ADC3_IN12 GPIO_ADC3_IN12_0 +#define GPIO_ADC3_IN13 GPIO_ADC3_IN13_0 + +/* USART2: + * USART2_TX - PA2 - GPIO_3 + * USART2_RX - PA3 - GPIO_4 + */ + +#define GPIO_USART2_RX (GPIO_USART2_RX_1|GPIO_SPEED_100MHz) +#define GPIO_USART2_TX (GPIO_USART2_TX_1|GPIO_SPEED_100MHz) + +/* CAN: + * CAN_R - PB8 + * CAN_T - PB9 + */ + +#define GPIO_CAN1_RX (GPIO_CAN1_RX_2|GPIO_SPEED_50MHz) +#define GPIO_CAN1_TX (GPIO_CAN1_TX_2|GPIO_SPEED_50MHz) + +/* SPI3 - connected to DRV8301 + * SPI3_SCK - PC10 + * SPI3_MISO - PC11 + * SPI3_MOSI - PC12 + */ + +#define GPIO_SPI3_SCK (GPIO_SPI3_SCK_2|GPIO_SPEED_50MHz) +#define GPIO_SPI3_MISO (GPIO_SPI3_MISO_2|GPIO_SPEED_50MHz) +#define GPIO_SPI3_MOSI (GPIO_SPI3_MOSI_2|GPIO_SPEED_50MHz) + +/* USBDEV */ + +#define GPIO_OTGFS_DM (GPIO_OTGFS_DM_0|GPIO_SPEED_100MHz) +#define GPIO_OTGFS_DP (GPIO_OTGFS_DP_0|GPIO_SPEED_100MHz) +#define GPIO_OTGFS_ID (GPIO_OTGFS_ID_0|GPIO_SPEED_100MHz) + +/* Dual FOC configuration */ + +/* TIM1 configuration *******************************************************/ + +#define GPIO_TIM1_CH1OUT (GPIO_TIM1_CH1OUT_1|GPIO_SPEED_100MHz) /* TIM1 CH1 - PA8 - U high */ +#define GPIO_TIM1_CH1NOUT (GPIO_TIM1_CH1N_2|GPIO_SPEED_100MHz) /* TIM1 CH1N - PB13 - U low */ +#define GPIO_TIM1_CH2OUT (GPIO_TIM1_CH2OUT_1|GPIO_SPEED_100MHz) /* TIM1 CH2 - PA9 - V high */ +#define GPIO_TIM1_CH2NOUT (GPIO_TIM1_CH2N_2|GPIO_SPEED_100MHz) /* TIM1 CH2N - PB14 - V low */ +#define GPIO_TIM1_CH3OUT (GPIO_TIM1_CH3OUT_1|GPIO_SPEED_100MHz) /* TIM1 CH3 - PA10 - W high */ +#define GPIO_TIM1_CH3NOUT (GPIO_TIM1_CH3N_2|GPIO_SPEED_100MHz) /* TIM1 CH3N - PB15 - W low */ +#define GPIO_TIM1_CH4OUT 0 /* not used as output */ + +/* TIM8 configuration *******************************************************/ + +#define GPIO_TIM8_CH1OUT (GPIO_TIM8_CH1OUT_1|GPIO_SPEED_100MHz) /* TIM8 CH1 - PC6 - U high */ +#define GPIO_TIM8_CH1NOUT (GPIO_TIM8_CH1N_2|GPIO_SPEED_100MHz) /* TIM8 CH1N - PA7 - U low */ +#define GPIO_TIM8_CH2OUT (GPIO_TIM8_CH2OUT_1|GPIO_SPEED_100MHz) /* TIM8 CH2 - PC7 - V high */ +#define GPIO_TIM8_CH2NOUT (GPIO_TIM8_CH2N_1|GPIO_SPEED_100MHz) /* TIM8 CH2N - PB0 - V low */ +#define GPIO_TIM8_CH3OUT (GPIO_TIM8_CH3OUT_1|GPIO_SPEED_100MHz) /* TIM8 CH3 - PC8 - W high */ +#define GPIO_TIM8_CH3NOUT (GPIO_TIM8_CH3N_1|GPIO_SPEED_100MHz) /* TIM8 CH3N - PB1 - W low */ +#define GPIO_TIM8_CH4OUT 0 /* not used as output */ + +/* QEN3 configuration *******************************************************/ + +#define GPIO_TIM3_CH1IN (GPIO_TIM3_CH1IN_2|GPIO_SPEED_50MHz) /* TIM3 CH1IN - PB4 */ +#define GPIO_TIM3_CH2IN (GPIO_TIM3_CH2IN_2|GPIO_SPEED_50MHz) /* TIM3 CH2IN - PB5 */ + +/* QEN4 configuration *******************************************************/ + +#define GPIO_TIM4_CH1IN (GPIO_TIM4_CH1IN_1|GPIO_SPEED_50MHz) /* TIM4 CH1IN - PB6 */ +#define GPIO_TIM4_CH2IN (GPIO_TIM4_CH2IN_1|GPIO_SPEED_50MHz) /* TIM4 CH2IN - PB7 */ + +#endif /* __BOARDS_ARM_STM32_ODRIVE36_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32f4/odrive36/scripts/Make.defs b/boards/arm/stm32f4/odrive36/scripts/Make.defs new file mode 100644 index 0000000000000..afe5816161125 --- /dev/null +++ b/boards/arm/stm32f4/odrive36/scripts/Make.defs @@ -0,0 +1,42 @@ +############################################################################ +# boards/arm/stm32f4/odrive36/scripts/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/.config +include $(TOPDIR)/tools/Config.mk +include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs + +LDSCRIPT = ld.script + +ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) + +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32f4/odrive36/scripts/ld.script b/boards/arm/stm32f4/odrive36/scripts/ld.script new file mode 100644 index 0000000000000..e96bd2dde2af2 --- /dev/null +++ b/boards/arm/stm32f4/odrive36/scripts/ld.script @@ -0,0 +1,125 @@ +/**************************************************************************** + * boards/arm/stm32f4/odrive36/scripts/ld.script + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* The STM32F405RGT6 has 1024Kb of FLASH beginning at address 0x0800:0000 and + * 192Kb of SRAM. SRAM is split up into two blocks: + * + * 1) 112Kb of SRAM beginning at address 0x2000:0000 + * 2) 16Kb of SRAM beginning at address 0x2001:c000 + * 3) 64Kb of SRAM beginning at address 0x2002:0000 + * + * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 + * where the code expects to begin execution by jumping to the entry point in + * the 0x0800:0000 address + * range. + */ + +MEMORY +{ + flash (rx) : ORIGIN = 0x08000000, LENGTH = 1024K + sram (rwx) : ORIGIN = 0x20000000, LENGTH = 112K +} + +OUTPUT_ARCH(arm) +EXTERN(_vectors) +ENTRY(_stext) +SECTIONS +{ + .text : { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > flash + + .init_section : ALIGN(4) { + _sinit = ABSOLUTE(.); + KEEP(*(.init_array .init_array.*)) + _einit = ABSOLUTE(.); + } > flash + + .ARM.extab : ALIGN(4) { + *(.ARM.extab*) + } > flash + + .ARM.exidx : ALIGN(4) { + __exidx_start = ABSOLUTE(.); + *(.ARM.exidx*) + __exidx_end = ABSOLUTE(.); + } > flash + + .tdata : { + _stdata = ABSOLUTE(.); + *(.tdata .tdata.* .gnu.linkonce.td.*); + _etdata = ABSOLUTE(.); + } > flash + + .tbss : { + _stbss = ABSOLUTE(.); + *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); + _etbss = ABSOLUTE(.); + } > flash + + _eronly = ABSOLUTE(.); + + .data : ALIGN(4) { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > sram AT > flash + + .bss : ALIGN(4) { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + _ebss = ABSOLUTE(.); + } > sram + + /* Stabs debugging sections. */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/stm32f4/odrive36/src/CMakeLists.txt b/boards/arm/stm32f4/odrive36/src/CMakeLists.txt new file mode 100644 index 0000000000000..3cb279a2f7221 --- /dev/null +++ b/boards/arm/stm32f4/odrive36/src/CMakeLists.txt @@ -0,0 +1,39 @@ +# ############################################################################## +# boards/arm/stm32f4/odrive36/src/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(SRCS stm32_boot.c stm32_bringup.c) + +if(CONFIG_STM32_SPI) + list(APPEND SRCS stm32_spi.c) +endif() + +if(CONFIG_STM32_FOC) + list(APPEND SRCS stm32_foc.c) +endif() + +if(CONFIG_STM32_OTGFS) + list(APPEND SRCS stm32_usb.c) +endif() + +target_sources(board PRIVATE ${SRCS}) + +set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/ld.script") diff --git a/boards/arm/stm32f4/odrive36/src/Make.defs b/boards/arm/stm32f4/odrive36/src/Make.defs new file mode 100644 index 0000000000000..1b8f5678a4648 --- /dev/null +++ b/boards/arm/stm32f4/odrive36/src/Make.defs @@ -0,0 +1,41 @@ +############################################################################ +# boards/arm/stm32f4/odrive36/src/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +CSRCS = stm32_boot.c stm32_bringup.c + +ifeq ($(CONFIG_STM32_SPI),y) +CSRCS += stm32_spi.c +endif + +ifeq ($(CONFIG_STM32_FOC),y) +CSRCS += stm32_foc.c +endif + +ifeq ($(CONFIG_STM32_OTGFS),y) +CSRCS += stm32_usb.c +endif + +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += $(shell $(INCDIR) "$(CC)" $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board) diff --git a/boards/arm/stm32/odrive36/src/odrive.h b/boards/arm/stm32f4/odrive36/src/odrive.h similarity index 99% rename from boards/arm/stm32/odrive36/src/odrive.h rename to boards/arm/stm32f4/odrive36/src/odrive.h index c8de89d3b2a99..22d37671a3d2b 100644 --- a/boards/arm/stm32/odrive36/src/odrive.h +++ b/boards/arm/stm32f4/odrive36/src/odrive.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/odrive36/src/odrive.h + * boards/arm/stm32f4/odrive36/src/odrive.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f4/odrive36/src/stm32_boot.c b/boards/arm/stm32f4/odrive36/src/stm32_boot.c new file mode 100644 index 0000000000000..8d0b01456725b --- /dev/null +++ b/boards/arm/stm32f4/odrive36/src/stm32_boot.c @@ -0,0 +1,107 @@ +/**************************************************************************** + * boards/arm/stm32f4/odrive36/src/stm32_boot.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include +#include +#include + +#include + +#include "arm_internal.h" +#include "odrive.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_boardinitialize + * + * Description: + * All STM32 architectures must provide the following entry point. This + * entry point is called early in the initialization -- after all memory + * has been configured and mapped but before any devices have been + * initialized. + * + ****************************************************************************/ + +void stm32_boardinitialize(void) +{ +#ifdef CONFIG_SEGGER_SYSVIEW + up_perf_init((void *)STM32_SYSCLK_FREQUENCY); +#endif + +#ifdef CONFIG_ARCH_LEDS + /* Configure on-board LEDs if LED support has been selected. */ + + board_autoled_initialize(); +#endif + +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || \ + defined(CONFIG_STM32_SPI3) + /* Configure SPI chip selects if 1) SP2 is not disabled, and 2) the weak + * function stm32_spidev_initialize() has been brought into the link. + */ + + stm32_spidev_initialize(); +#endif + +#ifdef CONFIG_STM32_OTGFS + /* Initialize USB is 1) USBDEV is selected, 2) the USB controller is not + * disabled, and 3) the weak function stm32_usbinitialize() has been + * brought into the build. + */ + + stm32_usbinitialize(); +#endif +} + +/**************************************************************************** + * Name: board_late_initialize + * + * Description: + * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_late_initialize(). board_late_initialize() will + * be called immediately after up_initialize() is called and just before + * the initial application is started. This additional initialization + * phase may be used, for example, to initialize board-specific device + * drivers. + * + ****************************************************************************/ + +#ifdef CONFIG_BOARD_LATE_INITIALIZE +void board_late_initialize(void) +{ + /* Perform board-specific initialization */ + + stm32_bringup(); +} +#endif diff --git a/boards/arm/stm32f4/odrive36/src/stm32_bringup.c b/boards/arm/stm32f4/odrive36/src/stm32_bringup.c new file mode 100644 index 0000000000000..23a07ac524b8d --- /dev/null +++ b/boards/arm/stm32f4/odrive36/src/stm32_bringup.c @@ -0,0 +1,140 @@ +/**************************************************************************** + * boards/arm/stm32f4/odrive36/src/stm32_bringup.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include + +#include +#include + +#ifdef CONFIG_SENSORS_QENCODER +# include "board_qencoder.h" +# include "stm32_qencoder.h" +#endif + +#include "odrive.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_bringup + * + * Description: + * Perform architecture-specific initialization + * + * CONFIG_BOARD_LATE_INITIALIZE=y : + * Called from board_late_initialize(). + * + ****************************************************************************/ + +int stm32_bringup(void) +{ + int ret = OK; + +#ifdef CONFIG_FS_PROCFS + /* Mount the procfs file system */ + + ret = nx_mount(NULL, STM32_PROCFS_MOUNTPOINT, "procfs", 0, NULL); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to mount the PROC filesystem: %d\n", + ret); + } +#endif /* CONFIG_FS_PROCFS */ + +#if defined(CONFIG_CDCACM) && !defined(CONFIG_CDCACM_CONSOLE) + /* Initialize CDCACM */ + + ret = cdcacm_initialize(0, NULL); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: cdcacm_initialize failed: %d\n", ret); + } +#endif /* CONFIG_CDCACM & !CONFIG_CDCACM_CONSOLE */ + +#if defined(CONFIG_STM32_TIM3_QE) && defined(CONFIG_SENSORS_QENCODER) + /* Initialize and register the qencoder driver - TIM3 */ + + ret = board_qencoder_initialize(0, 3); + if (ret != OK) + { + syslog(LOG_ERR, "ERROR: Failed to register the qencoder: %d\n", ret); + } + + /* Connect QE index pin */ + + ret = stm32_qe_index_init(3, GPIO_QE3_INDEX); + if (ret != OK) + { + syslog(LOG_ERR, "ERROR: Failed to register qe index pin: %d\n", ret); + } +#endif + +#if defined(CONFIG_STM32_TIM4_QE) && defined(CONFIG_SENSORS_QENCODER) + /* Initialize and register the qencoder driver - TIM4 */ + + ret = board_qencoder_initialize(1, 4); + if (ret != OK) + { + syslog(LOG_ERR, "ERROR: Failed to register the qencoder: %d\n", ret); + } + + /* Connect QE index pin */ + + ret = stm32_qe_index_init(4, GPIO_QE4_INDEX); + if (ret != OK) + { + syslog(LOG_ERR, "ERROR: Failed to register qe index pin: %d\n", ret); + } +#endif + +#ifdef CONFIG_ADC + /* Initialize ADC and register the ADC driver. */ + + ret = stm32_adc_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_adc_setup failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_STM32_FOC + /* Initialize and register FOC devices */ + + ret = stm32_foc_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_foc_setup failed: %d\n", ret); + } +#endif + + return ret; +} diff --git a/boards/arm/stm32f4/odrive36/src/stm32_foc.c b/boards/arm/stm32f4/odrive36/src/stm32_foc.c new file mode 100644 index 0000000000000..8e3ee20001356 --- /dev/null +++ b/boards/arm/stm32f4/odrive36/src/stm32_foc.c @@ -0,0 +1,962 @@ +/**************************************************************************** + * boards/arm/stm32f4/odrive36/src/stm32_foc.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include + +#include +#include +#include + +#include +#include + +#include "stm32_foc.h" +#include "stm32_gpio.h" +#ifdef CONFIG_ADC +# include "stm32_adc.h" +#endif + +#include "odrive.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifndef CONFIG_ODRIVE_HW_VOLTAGE_56 +# error Tested only for ODrive 56V version +#endif + +/* Supported FOC instances */ + +#ifdef CONFIG_ODRIVE_FOC_FOC0 +# define ODRIVE_FOC_FOC0 1 +#else +# define ODRIVE_FOC_FOC0 0 +#endif + +#ifdef CONFIG_ODRIVE_FOC_FOC1 +# define ODRIVE_FOC_FOC1 1 +#else +# define ODRIVE_FOC_FOC1 0 +#endif + +#define ODRIVE_FOC_INST (ODRIVE_FOC_FOC0 + ODRIVE_FOC_FOC1) + +#ifdef CONFIG_ODRIVE_FOC_FOC0 +# define ODRIVE32_FOC0_DEVPATH "/dev/foc0" +# define ODRIVE32_FOC0_INST (0) +#endif + +#ifdef CONFIG_ODRIVE_FOC_FOC1 +# define ODRIVE32_FOC1_DEVPATH "/dev/foc1" +# define ODRIVE32_FOC1_INST (1) +#endif + +/* Must match upper-half configuration */ + +#if ODRIVE_FOC_INST != CONFIG_MOTOR_FOC_INST +# error Invalid configuration +#endif + +/* Only 2-shunt configuration supported by board */ + +#if CONFIG_MOTOR_FOC_SHUNTS != 2 +# error For now only 2-shunts configuration is supported +#endif + +/* Configuration specific for DRV8301: + * 1. PWM channels must have positive polarity + * 2. PWM complementary channels must have positive polarity + */ + +#ifndef CONFIG_STM32_FOC_HAS_PWM_COMPLEMENTARY +# error +#endif + +#ifdef CONFIG_ODRIVE_FOC_FOC0 + +# if CONFIG_STM32_TIM1_CH1POL != 0 +# error +# endif +# if CONFIG_STM32_TIM1_CH2POL != 0 +# error +# endif +# if CONFIG_STM32_TIM1_CH3POL != 0 +# error +# endif +# if CONFIG_STM32_TIM1_CH1NPOL != 0 +# error +# endif +# if CONFIG_STM32_TIM1_CH2NPOL != 0 +# error +# endif +# if CONFIG_STM32_TIM1_CH3NPOL != 0 +# error +# endif + +/* FOC0 uses ADC2 */ + +# ifndef CONFIG_STM32_FOC_FOC0_ADC2 +# error +# endif + +# if CONFIG_STM32_ADC2_RESOLUTION != 0 +# error +# endif + +#endif /* CONFIG_ODRIVE_FOC_FOC0 */ + +#ifdef CONFIG_ODRIVE_FOC_FOC1 + +# if CONFIG_STM32_TIM8_CH1POL != 0 +# error +# endif +# if CONFIG_STM32_TIM8_CH2POL != 0 +# error +# endif +# if CONFIG_STM32_TIM8_CH3POL != 0 +# error +# endif +# if CONFIG_STM32_TIM8_CH1NPOL != 0 +# error +# endif +# if CONFIG_STM32_TIM8_CH2NPOL != 0 +# error +# endif +# if CONFIG_STM32_TIM8_CH3NPOL != 0 +# error +# endif + +/* FOC1 uses ADC3 */ + +# ifndef CONFIG_STM32_FOC_FOC1_ADC3 +# error +# endif + +# if CONFIG_STM32_ADC3_RESOLUTION != 0 +# error +# endif + +#endif /* CONFIG_ODRIVE_FOC_FOC1 */ + +/* Aux ADC needs DMA enabled */ + +#ifdef CONFIG_ADC +# ifndef CONFIG_STM32_ADC1_DMA +# error +# endif +# ifndef CONFIG_STM32_ADC1_SCAN +# error +# endif +#endif + +/* TODO: */ + +#define PWM_DEADTIME (50) +#define PWM_DEADTIME_NS (320) + +/* Board parameters: + * Current shunt resistance = 0.0005 + * Current sense gain = (10/20/40/80) + * Vbus min = 12V + * Vbus max = 24V or 56V + * Iout max = 40A (no cooling for + * MOSFETs) + * IPHASE_RATIO = 1/(R_shunt*gain) + * ADC_REF_VOLTAGE = 3.3 + * ADC_VAL_MAX = 4095 + * ADC_TO_VOLT = ADC_REF_VOLTAGE / ADC_VAL_MAX + * IPHASE_ADC = IPHASE_RATIO * ADC_TO_VOLT = 0.02014 (gain=80) + * VBUS_RATIO = 1/VBUS_gain = 11 or 19 + */ + +#define ADC_VOLT_REF 3300000 /* micro volt */ +#define ADC_VAL_MAX 4095 +#define R_SHUNT 500 /* micro ohm */ + +/* Center-aligned PWM duty cycle limits */ + +#define MAX_DUTY_B16 ftob16(0.95f) + +/* ADC configuration */ + +#define CURRENT_SAMPLE_TIME ADC_SMPR_3 +#define VBUS_SAMPLE_TIME ADC_SMPR_15 +#define TEMP_SAMPLE_TIME ADC_SMPR_15 + +#define ODRIVE_ADC_AUX (1) +#define ODRIVE_ADC_FOC0 (2) +#define ODRIVE_ADC_FOC1 (3) + +#ifdef CONFIG_ODRIVE_FOC_VBUS +# define ODRIVE_FOC_VBUS 1 +#else +# define ODRIVE_FOC_VBUS 0 +#endif +#ifdef CONFIG_ODRIVE_FOC_TEMP +# define ODRIVE_FOC_TEMP 3 +#else +# define ODRIVE_FOC_TEMP 0 +#endif + +#ifdef CONFIG_ADC +# define ODRIVE_ADC_AUX_DEVPATH "/dev/adc0" +# define ODRIVE_ADC_AUX_NCHAN (ODRIVE_FOC_VBUS + ODRIVE_FOC_TEMP) +#endif + +#define ADC1_INJECTED (0) +#define ADC1_REGULAR (0) +#define ADC1_NCHANNELS (ADC1_INJECTED + ADC1_REGULAR) + +#define ADC2_INJECTED (CONFIG_MOTOR_FOC_SHUNTS) +#define ADC2_REGULAR (0) +#define ADC2_NCHANNELS (ADC2_INJECTED + ADC2_REGULAR) + +#define ADC3_INJECTED (CONFIG_MOTOR_FOC_SHUNTS) +#define ADC3_REGULAR (0) +#define ADC3_NCHANNELS (ADC3_INJECTED + ADC3_REGULAR) + +#if ADC1_INJECTED != CONFIG_STM32_ADC1_INJECTED_CHAN +# error +#endif + +#if ADC2_INJECTED != CONFIG_STM32_ADC2_INJECTED_CHAN +# error +#endif + +#if ADC3_INJECTED != CONFIG_STM32_ADC3_INJECTED_CHAN +# error +#endif + +/* DRV8301 configuration */ + +#ifndef CONFIG_STM32_SPI3 +# error +#endif + +#define DRV8301_0_SPI (3) +#define DRV8301_1_SPI (3) + +#define DRV8301_FREQUENCY (500000) + +/* Qenco configuration */ + +#ifdef CONFIG_SENSORS_QENCODER +# ifndef CONFIG_STM32_QENCODER_DISABLE_EXTEND16BTIMERS +# error Invalid configuration +# endif +# ifndef CONFIG_STM32_QENCODER_INDEX_PIN +# error Invalid configuration +# endif +# ifdef CONFIG_STM32_TIM3_QE +# if CONFIG_STM32_TIM3_QEPSC != 0 +# error Invalid TIM3 QEPSC value +# endif +# endif +# ifdef CONFIG_STM32_TIM4_QE +# if CONFIG_STM32_TIM4_QEPSC != 0 +# error Invalid TIM4 QEPSC value +# endif +# endif +#endif + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/**************************************************************************** + * Private Function Protototypes + ****************************************************************************/ + +static int board_foc_setup(struct foc_dev_s *dev); +static int board_foc_shutdown(struct foc_dev_s *dev); +static int board_foc_calibration(struct foc_dev_s *dev, bool state); +static int board_foc_fault_clear(struct foc_dev_s *dev); +static int board_foc_pwm_start(struct foc_dev_s *dev, bool state); +static int board_foc_current_get(struct foc_dev_s *dev, int16_t *curr_raw, + foc_current_t *curr); +static int board_foc_info_get(struct foc_dev_s *dev, + struct foc_info_s *info); +static int board_foc_ioctl(struct foc_dev_s *dev, int cmd, + unsigned long arg); +#ifdef CONFIG_MOTOR_FOC_TRACE +static int board_foc_trace_init(struct foc_dev_s *dev); +static void board_foc_trace(struct foc_dev_s *dev, int type, bool state); +#endif + +static int stm32_foc_drv8301_fault_attach(struct focpwr_dev_s *dev, + xcpt_t isr, void *arg); +static int stm32_foc_drv8301_gate_enable(struct focpwr_dev_s *dev, + bool enable); +static void stm32_foc_drv8301_fault_handle(struct focpwr_dev_s *dev); + +static int stm32_focdev_setup(int devno, int spino, + struct stm32_foc_board_s *board); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* Board specific ops */ + +static struct stm32_foc_board_ops_s g_stm32_foc_board_ops = +{ + .setup = board_foc_setup, + .shutdown = board_foc_shutdown, + .calibration = board_foc_calibration, + .fault_clear = board_foc_fault_clear, + .pwm_start = board_foc_pwm_start, + .current_get = board_foc_current_get, + .info_get = board_foc_info_get, + .ioctl = board_foc_ioctl, +#ifdef CONFIG_MOTOR_FOC_TRACE + .trace_init = board_foc_trace_init, + .trace = board_foc_trace +#endif +}; + +/* Board specific ADC configuration + * + * AUX (only VBUS used): + * VBUS - ADC1 - ADC1_IN6 (PA6) + * M0_TEMP - ADC1 - ADC1_IN15 (PC5) + * M1_TEMP - ADC1 - ADC1_IN4 (PA4) + * AUX_TEMP - ADC1 - ADC1_IN5 (PA5) + * + * FOC device 0: + * Phase 1 - ADC2 - ADC2_IN10 (PC0) + * Phase 2 - ADC2 - ADC2_IN11 (PC1) + * + * FOC device 1: + * Phase 1 - ADC3 - ADC3_IN13 (PC3) + * Phase 2 - ADC3 - ADC3_IN12 (PC2) + * + */ + +#ifdef CONFIG_ADC + +/* AUX ADC configuration */ + +static uint8_t g_adc_aux_chan[] = +{ +#ifdef CONFIG_ODRIVE_FOC_VBUS + 6, +#endif +#ifdef ODRIVE_ADC_TEMP + 15, + 4, + 5 +#endif +}; + +static uint32_t g_adc_aux_pins[] = +{ +#ifdef CONFIG_ODRIVE_FOC_VBUS + GPIO_ADC1_IN6, +#endif +#ifdef ODRIVE_ADC_TEMP + GPIO_ADC1_IN15, + GPIO_ADC1_IN4, + GPIO_ADC1_IN5 +#endif +}; + +static adc_channel_t g_adc_aux_stime[] = +{ +#ifdef CONFIG_ODRIVE_FOC_VBUS + { + .channel = 6, + .sample_time = VBUS_SAMPLE_TIME + }, +#endif +#ifdef ODRIVE_ADC_TEMP + { + .channel = 15, + .sample_time = TEMP_SAMPLE_TIME + }, + { + .channel = 4, + .sample_time = TEMP_SAMPLE_TIME + }, + { + .channel = 5, + .sample_time = TEMP_SAMPLE_TIME + } +#endif +}; +#endif + +#ifdef CONFIG_ODRIVE_FOC_FOC0 +/* Board specific ADC configuration for FOC device 0 */ + +static uint8_t g_adc_foc0_chan[] = +{ + 10, + 11 +}; + +static uint32_t g_adc_foc0_pins[] = +{ + GPIO_ADC2_IN10, + GPIO_ADC2_IN11, +}; + +static adc_channel_t g_adc_foc0_stime[] = +{ + { + .channel = 10, + .sample_time = CURRENT_SAMPLE_TIME + }, + { + .channel = 11, + .sample_time = CURRENT_SAMPLE_TIME + } +}; + +static struct stm32_foc_adc_s g_adc_foc0_cfg = +{ + .chan = g_adc_foc0_chan, + .pins = g_adc_foc0_pins, + .stime = g_adc_foc0_stime, + .nchan = ADC2_NCHANNELS, + .regch = ADC2_REGULAR, + .intf = ODRIVE_ADC_FOC0 +}; +#endif + +#ifdef CONFIG_ODRIVE_FOC_FOC1 +/* Board specific ADC configuration for FOC device 1 */ + +static uint8_t g_adc_foc1_chan[] = +{ + 13, + 12 +}; + +static uint32_t g_adc_foc1_pins[] = +{ + GPIO_ADC3_IN13, + GPIO_ADC3_IN12, +}; + +static adc_channel_t g_adc_foc1_stime[] = +{ + { + .channel = 13, + .sample_time = CURRENT_SAMPLE_TIME + }, + { + .channel = 12, + .sample_time = CURRENT_SAMPLE_TIME + } +}; + +static struct stm32_foc_adc_s g_adc_foc1_cfg = +{ + .chan = g_adc_foc1_chan, + .pins = g_adc_foc1_pins, + .stime = g_adc_foc1_stime, + .nchan = ADC3_NCHANNELS, + .regch = ADC3_REGULAR, + .intf = ODRIVE_ADC_FOC1 +}; +#endif + +#ifdef CONFIG_ODRIVE_FOC_FOC0 +/* Board specific data - FOC 0 */ + +static struct stm32_foc_board_data_s g_stm32_foc0_board_data = +{ + .adc_cfg = &g_adc_foc0_cfg, + .pwm_dt = (PWM_DEADTIME), +}; + +/* Board specific configuration */ + +static struct stm32_foc_board_s g_stm32_foc0_board = +{ + .data = &g_stm32_foc0_board_data, + .ops = &g_stm32_foc_board_ops, +}; +#endif + +#ifdef CONFIG_ODRIVE_FOC_FOC1 +/* Board specific data - FOC 1 */ + +static struct stm32_foc_board_data_s g_stm32_foc1_board_data = +{ + .adc_cfg = &g_adc_foc1_cfg, + .pwm_dt = (PWM_DEADTIME), +}; + +/* Board specific configuration */ + +static struct stm32_foc_board_s g_stm32_foc1_board = +{ + .data = &g_stm32_foc1_board_data, + .ops = &g_stm32_foc_board_ops, +}; +#endif + +/* DRV8301 board ops */ + +static struct drv8301_ops_s g_drv8301_board_ops = +{ + .fault_attach = stm32_foc_drv8301_fault_attach, + .gate_enable = stm32_foc_drv8301_gate_enable, + .fault_handle = stm32_foc_drv8301_fault_handle +}; + +/* Global data */ + +static mutex_t g_common_lock = NXMUTEX_INITIALIZER; +static bool g_fault_attached = false; +static bool g_gate_enabled = false; + +static struct foc_dev_s *g_foc_dev[2] = +{ + NULL, + NULL +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_foc_setup + ****************************************************************************/ + +static int board_foc_setup(struct foc_dev_s *dev) +{ + DEBUGASSERT(dev); + DEBUGASSERT(dev->pwr); + + return dev->pwr->ops->setup(dev->pwr); +} + +/**************************************************************************** + * Name: board_foc_shutdown + ****************************************************************************/ + +static int board_foc_shutdown(struct foc_dev_s *dev) +{ + DEBUGASSERT(dev); + DEBUGASSERT(dev->pwr); + + return dev->pwr->ops->shutdown(dev->pwr); +} + +/**************************************************************************** + * Name: board_foc_calibration + ****************************************************************************/ + +static int board_foc_calibration(struct foc_dev_s *dev, bool state) +{ + DEBUGASSERT(dev); + DEBUGASSERT(dev->pwr); + + return dev->pwr->ops->calibration(dev->pwr, state); +} + +/**************************************************************************** + * Name: board_foc_fault_clear + ****************************************************************************/ + +static int board_foc_fault_clear(struct foc_dev_s *dev) +{ + DEBUGASSERT(dev); + + UNUSED(dev); + + /* TODO: clear DRV8301 faults */ + + return OK; +} + +/**************************************************************************** + * Name: board_foc_pwm_start + ****************************************************************************/ + +static int board_foc_pwm_start(struct foc_dev_s *dev, bool state) +{ + DEBUGASSERT(dev); + + return OK; +} + +/**************************************************************************** + * Name: board_foc_current_get + ****************************************************************************/ + +static int board_foc_current_get(struct foc_dev_s *dev, int16_t *curr_raw, + foc_current_t *curr) +{ + DEBUGASSERT(dev); + DEBUGASSERT(curr_raw); + DEBUGASSERT(curr); + + /* Get currents */ + + curr[1] = curr_raw[0]; + curr[2] = curr_raw[1]; + + /* From Kirchhoff's current law: ia = -(ib + ic) */ + + curr[0] = -(curr[1] + curr[2]); + + return OK; +} + +/**************************************************************************** + * Name: board_foc_info_get + ****************************************************************************/ + +static int board_foc_info_get(struct foc_dev_s *dev, + struct foc_info_s *info) +{ + struct foc_get_boardcfg_s cfg; + + DEBUGASSERT(dev); + DEBUGASSERT(info); + + UNUSED(dev); + + /* PWM */ + + info->hw_cfg.pwm_dt_ns = PWM_DEADTIME_NS; + info->hw_cfg.pwm_max = MAX_DUTY_B16; + + /* Get power stage configuration */ + + board_foc_ioctl(dev, MTRIOC_GET_BOARDCFG, (unsigned long)&cfg); + + /* ADC Current */ + + info->hw_cfg.iphase_max = 40000; + + info->hw_cfg.iphase_scale = ((100000ul * (ADC_VOLT_REF / ADC_VAL_MAX)) / + (cfg.gain * R_SHUNT)); + + return OK; +} + +/**************************************************************************** + * Name: board_foc_ioctl + ****************************************************************************/ + +static int board_foc_ioctl(struct foc_dev_s *dev, int cmd, unsigned long arg) +{ + DEBUGASSERT(dev); + DEBUGASSERT(dev->pwr); + + return dev->pwr->ops->ioctl(dev->pwr, cmd, arg); +} + +#ifdef CONFIG_MOTOR_FOC_TRACE +/**************************************************************************** + * Name: board_foc_trace_init + ****************************************************************************/ + +static int board_foc_trace_init(struct foc_dev_s *dev) +{ + DEBUGASSERT(dev); + + UNUSED(dev); + + /* Not supported */ + + return -1; +} + +/**************************************************************************** + * Name: board_foc_trace + ****************************************************************************/ + +static void board_foc_trace(struct foc_dev_s *dev, int type, bool state) +{ + DEBUGASSERT(dev); + + UNUSED(dev); +} +#endif + +/**************************************************************************** + * Name: stm32_foc_drv8301_fault_attach + ****************************************************************************/ + +static int stm32_foc_drv8301_fault_attach(struct focpwr_dev_s *dev, + xcpt_t isr, void *arg) +{ + int ret = OK; + + nxmutex_lock(&g_common_lock); + + /* nFAULT is common for both FOC instances */ + + if (g_fault_attached != (bool) isr) + { + ret = stm32_gpiosetevent(GPIO_DRV8301_NFAULT, false, true, false, + isr, arg); + + g_fault_attached = (bool) isr; + } + + nxmutex_unlock(&g_common_lock); + + return ret; +} + +/**************************************************************************** + * Name: stm32_foc_drv8301_gate_enable + ****************************************************************************/ + +static int stm32_foc_drv8301_gate_enable(struct focpwr_dev_s *dev, + bool enable) +{ + /* ENGATE is common for both FOC instances */ + + nxmutex_lock(&g_common_lock); + + if (enable != g_gate_enabled) + { + stm32_gpiowrite(GPIO_DRV8301_ENGATE, enable); + + g_gate_enabled = enable; + } + + nxmutex_unlock(&g_common_lock); + + return OK; +} + +/**************************************************************************** + * Name: stm32_foc_drv8301_fault_handle + ****************************************************************************/ + +static void stm32_foc_drv8301_fault_handle(struct focpwr_dev_s *dev) +{ + UNUSED(dev); + + /* Set fault state for both instances */ + +#ifdef CONFIG_ODRIVE_FOC_FOC0 + g_foc_dev[0]->state.fault |= FOC_FAULT_BOARD; +#endif + +#ifdef CONFIG_ODRIVE_FOC_FOC1 + g_foc_dev[1]->state.fault |= FOC_FAULT_BOARD; +#endif + + /* Disable gates for both instances */ + + stm32_gpiowrite(GPIO_DRV8301_ENGATE, false); +} + +/**************************************************************************** + * Name: stm32_focdev_setup + ****************************************************************************/ + +static int stm32_focdev_setup(int devno, int spino, + struct stm32_foc_board_s *board) +{ + struct drv8301_cfg_s drv8301_cfg; + struct drv8301_board_s drv8301_board; + struct spi_dev_s *spi = NULL; + struct foc_dev_s *foc = NULL; + int ret = OK; + char devpath[20]; + + /* Initialize arch specific FOC 0 lower-half */ + + foc = stm32_foc_initialize(devno, board); + if (foc == NULL) + { + ret = -errno; + mtrerr("Failed to initialize STM32 FOC: %d\n", ret); + goto errout; + } + + DEBUGASSERT(foc->lower); + + /* Get devpath */ + + snprintf(devpath, sizeof(devpath), "/dev/foc%d", devno); + + /* Get SPI device */ + + spi = stm32_spibus_initialize(spino); + if (spi == NULL) + { + ret = -errno; + goto errout; + } + + /* DRV8301 configuration */ + + drv8301_cfg.freq = DRV8301_FREQUENCY; + drv8301_cfg.gate_curr = DRV8301_GATECURR_1p7; + drv8301_cfg.gain = DRV8301_GAIN_80; + drv8301_cfg.pwm_mode = DRV8301_PWM_6IN; + drv8301_cfg.oc_adj = DRV8301_OCADJ_DEFAULT; + + /* DRV8301 board data */ + + drv8301_board.spi = spi; + drv8301_board.ops = &g_drv8301_board_ops; + drv8301_board.cfg = &drv8301_cfg; + drv8301_board.devno = devno; + + /* Register DRV8301 device */ + + ret = drv8301_register(devpath, foc, &drv8301_board); + if (ret < 0) + { + mtrerr("Failed to register drv8301 device: %d\n", ret); + goto errout; + } + +errout: + return ret; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_foc_setup + * + * Description: + * Setup FOC devices + * + * Returned Value: + * 0 on success, a negated errno value on failure + * + ****************************************************************************/ + +int stm32_foc_setup(void) +{ + int ret = OK; + + /* Configure common EN_GATE */ + + stm32_configgpio(GPIO_DRV8301_ENGATE); + +#ifdef CONFIG_ODRIVE_FOC_FOC0 + ret = stm32_focdev_setup(0, DRV8301_0_SPI, &g_stm32_foc0_board); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_focdev_setup 0 failed: %d\n", ret); + goto errout; + } +#endif + +#ifdef CONFIG_ODRIVE_FOC_FOC1 + ret = stm32_focdev_setup(1, DRV8301_1_SPI, &g_stm32_foc1_board); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_focdev_setup 1 failed: %d\n", ret); + goto errout; + } +#endif + +errout: + return ret; +} + +#ifdef CONFIG_ADC +/**************************************************************************** + * Name: stm32_adc_setup + * + * Description: + * Initialize ADC and register the ADC driver. + * + ****************************************************************************/ + +int stm32_adc_setup(void) +{ + struct adc_dev_s *adc = NULL; + struct stm32_adc_dev_s *stm32_adc = NULL; + struct adc_sample_time_s stime; + int i = 0; + int ret = OK; + + /* Configure pins */ + + for (i = 0; i < ODRIVE_ADC_AUX_NCHAN; i += 1) + { + stm32_configgpio(g_adc_aux_pins[i]); + } + + /* Initialize ADC */ + + adc = stm32_adcinitialize(ODRIVE_ADC_AUX, g_adc_aux_chan, + ODRIVE_ADC_AUX_NCHAN); + if (adc == NULL) + { + aerr("ERROR: Failed to get ADC interface %d\n", ODRIVE_ADC_AUX); + ret = -ENODEV; + goto errout; + } + + /* Register ADC */ + + ret = adc_register(ODRIVE_ADC_AUX_DEVPATH, adc); + if (ret < 0) + { + aerr("ERROR: adc_register %s failed: %d\n", + ODRIVE_ADC_AUX_DEVPATH, ret); + goto errout; + } + + /* Get lower-half ADC */ + + stm32_adc = (struct stm32_adc_dev_s *)adc->ad_priv; + DEBUGASSERT(stm32_adc); + + /* Configure ADC sample time */ + + memset(&stime, 0, sizeof(struct adc_sample_time_s)); + + stime.channels_nbr = ODRIVE_ADC_AUX_NCHAN; + stime.channel = g_adc_aux_stime; + + STM32_ADC_SAMPLETIME_SET(stm32_adc, &stime); + STM32_ADC_SAMPLETIME_WRITE(stm32_adc); + + ret = OK; + +errout: + return ret; +} +#endif diff --git a/boards/arm/stm32f4/odrive36/src/stm32_spi.c b/boards/arm/stm32f4/odrive36/src/stm32_spi.c new file mode 100644 index 0000000000000..1e462af7a338b --- /dev/null +++ b/boards/arm/stm32f4/odrive36/src/stm32_spi.c @@ -0,0 +1,198 @@ +/**************************************************************************** + * boards/arm/stm32f4/odrive36/src/stm32_spi.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include + +#include "arm_internal.h" +#include "chip.h" +#include "stm32.h" + +#include "odrive.h" + +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || defined(CONFIG_STM32_SPI3) + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_spidev_initialize + * + * Description: + * Called to configure SPI chip select GPIO pins for the stm32f4discovery + * board. + * + ****************************************************************************/ + +void weak_function stm32_spidev_initialize(void) +{ +#ifdef CONFIG_MOTOR_FOC +# ifdef CONFIG_ODRIVE_FOC_FOC0 + stm32_configgpio(GPIO_GATEDRV0_CS); +# endif +# ifdef CONFIG_ODRIVE_FOC_FOC1 + stm32_configgpio(GPIO_GATEDRV1_CS); +# endif +#endif /* CONFIG_MOTOR_FOC */ +} + +/**************************************************************************** + * Name: stm32_spi1/2/3select and stm32_spi1/2/3status + * + * Description: + * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status + * must be provided by board-specific logic. They are implementations of + * the select and status methods of the SPI interface defined by struct + * spi_ops_s (see include/nuttx/spi/spi.h). All other methods (including + * stm32_spibus_initialize()) are provided by common STM32 logic. To use + * this common SPI logic on your board: + * + * 1. Provide logic in stm32_boardinitialize() to configure SPI chip select + * pins. + * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() functions + * in your board-specific logic. These functions will perform chip + * selection and status operations using GPIOs in the way your board + * is configured. + * 3. Add a calls to stm32_spibus_initialize() in your low level + * application initialization logic + * 4. The handle returned by stm32_spibus_initialize() may then be used to + * bind the SPI driver to higher level logic (e.g., calling + * mmcsd_spislotinitialize(), for example, will bind the SPI driver to + * the SPI MMC/SD driver). + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_SPI1 +void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, bool selected) +{ + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); +} + +uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} +#endif + +#ifdef CONFIG_STM32_SPI2 +void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid, + bool selected) +{ + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); +} + +uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} +#endif + +#ifdef CONFIG_STM32_SPI3 +void stm32_spi3select(struct spi_dev_s *dev, uint32_t devid, bool selected) +{ + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); + +#ifdef CONFIG_MOTOR_FOC +# ifdef CONFIG_ODRIVE_FOC_FOC0 + if (devid == SPIDEV_MOTOR(0)) + { + stm32_gpiowrite(GPIO_GATEDRV0_CS, !selected); + } +# endif + +# ifdef CONFIG_ODRIVE_FOC_FOC1 + if (devid == SPIDEV_MOTOR(1)) + { + stm32_gpiowrite(GPIO_GATEDRV1_CS, !selected); + } +# endif +#endif /* CONFIG_MOTOR_FOC */ +} + +uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} +#endif + +/**************************************************************************** + * Name: stm32_spi1cmddata + * + * Description: + * Set or clear the SH1101A A0 or SD1306 D/C n bit to select data (true) + * or command (false). This function must be provided by platform-specific + * logic. This is an implementation of the cmddata method of the SPI + * interface defined by struct spi_ops_s (see include/nuttx/spi/spi.h). + * + * Input Parameters: + * + * spi - SPI device that controls the bus the device that requires the CMD/ + * DATA selection. + * devid - If there are multiple devices on the bus, this selects which one + * to select cmd or data. NOTE: This design restricts, for example, + * one one SPI display per SPI bus. + * cmd - true: select command; false: select data + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_SPI_CMDDATA +#ifdef CONFIG_STM32_SPI1 +int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) +{ + return -ENODEV; +} +#endif + +#ifdef CONFIG_STM32_SPI2 +int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) +{ + return -ENODEV; +} +#endif + +#ifdef CONFIG_STM32_SPI3 +int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) +{ + return -ENODEV; +} +#endif +#endif /* CONFIG_SPI_CMDDATA */ + +#endif /* CONFIG_STM32_SPI1 || CONFIG_STM32_SPI2 || CONFIG_STM32_SPI3 */ diff --git a/boards/arm/stm32f4/odrive36/src/stm32_usb.c b/boards/arm/stm32f4/odrive36/src/stm32_usb.c new file mode 100644 index 0000000000000..d3f53924d0c3e --- /dev/null +++ b/boards/arm/stm32f4/odrive36/src/stm32_usb.c @@ -0,0 +1,105 @@ +/**************************************************************************** + * boards/arm/stm32f4/odrive36/src/stm32_usb.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include "arm_internal.h" +#include "stm32.h" +#include "stm32_otgfs.h" +#include "odrive.h" + +#ifdef CONFIG_STM32_OTGFS + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#if defined(CONFIG_USBDEV) +# define HAVE_USB 1 +#else +# warning "CONFIG_STM32_OTGFS is enabled but neither CONFIG_USBDEV" +# undef HAVE_USB +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_usbinitialize + * + * Description: + * Called from stm32_usbinitialize very early in initialization to setup + * USB-related GPIO pins for the STM32F4Discovery board. + * + ****************************************************************************/ + +void stm32_usbinitialize(void) +{ + /* The OTG FS has an internal soft pull-up. + * No GPIO configuration is required + */ +} + +/**************************************************************************** + * Name: stm32_usbsuspend + * + * Description: + * Board logic must provide the stm32_usbsuspend logic if the USBDEV + * driver is used. This function is called whenever the USB enters or + * leaves suspend mode. This is an opportunity for the board logic to + * shutdown clocks, power, etc. while the USB is suspended. + * + ****************************************************************************/ + +#ifdef CONFIG_USBDEV +void stm32_usbsuspend(struct usbdev_s *dev, bool resume) +{ + uinfo("resume: %d\n", resume); +} +#endif + +#endif /* CONFIG_STM32_OTGFS */ diff --git a/boards/arm/stm32f4/olimex-stm32-e407/CMakeLists.txt b/boards/arm/stm32f4/olimex-stm32-e407/CMakeLists.txt new file mode 100644 index 0000000000000..389002b8fac05 --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-e407/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32f4/olimex-stm32-e407/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/arm/stm32/olimex-stm32-e407/Kconfig b/boards/arm/stm32f4/olimex-stm32-e407/Kconfig similarity index 100% rename from boards/arm/stm32/olimex-stm32-e407/Kconfig rename to boards/arm/stm32f4/olimex-stm32-e407/Kconfig diff --git a/boards/arm/stm32f4/olimex-stm32-e407/configs/bmp180/defconfig b/boards/arm/stm32f4/olimex-stm32-e407/configs/bmp180/defconfig new file mode 100644 index 0000000000000..0234ae05eba53 --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-e407/configs/bmp180/defconfig @@ -0,0 +1,57 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="olimex-stm32-e407" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_OLIMEX_STM32E407=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F407ZG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL_USBDEVCTRL=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_CDCACM=y +CONFIG_CDCACM_CONSOLE=y +CONFIG_EXAMPLES_BMP180=y +CONFIG_EXAMPLES_HELLO=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_MM_REGIONS=2 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_SENSORS=y +CONFIG_SENSORS_BMP180=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_STM32_I2C1=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PWR=y +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_NSH=y +CONFIG_USART2_RXBUFSIZE=128 +CONFIG_USART2_TXBUFSIZE=128 +CONFIG_USBDEV=y diff --git a/boards/arm/stm32f4/olimex-stm32-e407/configs/dac/defconfig b/boards/arm/stm32f4/olimex-stm32-e407/configs/dac/defconfig new file mode 100644 index 0000000000000..7c870afe0d1f1 --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-e407/configs/dac/defconfig @@ -0,0 +1,58 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ANALOG=y +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="olimex-stm32-e407" +CONFIG_ARCH_BOARD_OLIMEX_STM32E407=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F407ZG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL_USBDEVCTRL=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_CDCACM=y +CONFIG_CDCACM_CONSOLE=y +CONFIG_DAC=y +CONFIG_EXAMPLES_DAC=y +CONFIG_EXAMPLES_HELLO=y +CONFIG_EXAMPLES_HELLOXX=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_MM_REGIONS=2 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_STM32_DAC1=y +CONFIG_STM32_DAC1CH1=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PWR=y +CONFIG_STM32_USART3=y +CONFIG_SYSTEM_NSH=y +CONFIG_USART3_RXBUFSIZE=128 +CONFIG_USART3_TXBUFSIZE=128 +CONFIG_USBDEV=y diff --git a/boards/arm/stm32f4/olimex-stm32-e407/configs/discover/defconfig b/boards/arm/stm32f4/olimex-stm32-e407/configs/discover/defconfig new file mode 100644 index 0000000000000..67d4415b193ee --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-e407/configs/discover/defconfig @@ -0,0 +1,71 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="olimex-stm32-e407" +CONFIG_ARCH_BOARD_OLIMEX_STM32E407=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F407ZG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_ARM_TOOLCHAIN_BUILDROOT=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_ETH0_PHY_LAN8720=y +CONFIG_EXAMPLES_DISCOVER=y +CONFIG_EXAMPLES_DISCOVER_DHCPC=y +CONFIG_EXAMPLES_DISCOVER_DRIPADDR=0xc0a80101 +CONFIG_EXAMPLES_DISCOVER_NOMAC=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INIT_ENTRYPOINT="discover_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_MM_REGIONS=2 +CONFIG_NET=y +CONFIG_NET_ARP_IPIN=y +CONFIG_NET_BROADCAST=y +CONFIG_NET_ICMP_SOCKET=y +CONFIG_NET_MAX_LISTENPORTS=40 +CONFIG_NET_STATISTICS=y +CONFIG_NET_TCP=y +CONFIG_NET_TCP_PREALLOC_CONNS=40 +CONFIG_NET_UDP=y +CONFIG_NET_UDP_CHECKSUMS=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_WAITPID=y +CONFIG_SPI=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_ETHMAC=y +CONFIG_STM32_JTAG_FULL_ENABLE=y +CONFIG_STM32_PHYADDR=0 +CONFIG_STM32_PHYSR=31 +CONFIG_STM32_PHYSR_100FD=0x0018 +CONFIG_STM32_PHYSR_100HD=0x0008 +CONFIG_STM32_PHYSR_10FD=0x0014 +CONFIG_STM32_PHYSR_10HD=0x0004 +CONFIG_STM32_PHYSR_ALTCONFIG=y +CONFIG_STM32_PHYSR_ALTMODE=0x001c +CONFIG_STM32_PWR=y +CONFIG_STM32_RMII_EXTCLK=y +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_PING=y +CONFIG_USART2_RXBUFSIZE=128 +CONFIG_USART2_SERIAL_CONSOLE=y +CONFIG_USART2_TXBUFSIZE=128 diff --git a/boards/arm/stm32f4/olimex-stm32-e407/configs/ina219/defconfig b/boards/arm/stm32f4/olimex-stm32-e407/configs/ina219/defconfig new file mode 100644 index 0000000000000..c945c4e776bc8 --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-e407/configs/ina219/defconfig @@ -0,0 +1,58 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_DEV_CONSOLE is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="olimex-stm32-e407" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_OLIMEX_STM32E407=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F407ZG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL_USBDEVCTRL=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_CDCACM=y +CONFIG_CDCACM_CONSOLE=y +CONFIG_CDCACM_RXBUFSIZE=256 +CONFIG_CDCACM_TXBUFSIZE=256 +CONFIG_EXAMPLES_HELLO=y +CONFIG_EXAMPLES_INA219=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_MM_REGIONS=2 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_SENSORS=y +CONFIG_SENSORS_INA219=y +CONFIG_START_DAY=27 +CONFIG_START_YEAR=2013 +CONFIG_STM32_I2C1=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PWR=y +CONFIG_STM32_USART2=y +CONFIG_SYSLOG_CHAR=y +CONFIG_SYSLOG_DEVPATH="/dev/ttyS0" +CONFIG_SYSTEM_NSH=y +CONFIG_USBDEV=y diff --git a/boards/arm/stm32f4/olimex-stm32-e407/configs/mrf24j40-6lowpan/defconfig b/boards/arm/stm32f4/olimex-stm32-e407/configs/mrf24j40-6lowpan/defconfig new file mode 100644 index 0000000000000..44eab998857a8 --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-e407/configs/mrf24j40-6lowpan/defconfig @@ -0,0 +1,104 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_NET_ETHERNET is not set +# CONFIG_NET_IPv4 is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="olimex-stm32-e407" +CONFIG_ARCH_BOARD_OLIMEX_STM32E407=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F407ZG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL_USBDEVCTRL=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_CDCACM=y +CONFIG_CDCACM_CONSOLE=y +CONFIG_DEBUG_FEATURES=y +CONFIG_DEBUG_NET=y +CONFIG_DEBUG_NET_ERROR=y +CONFIG_DEBUG_NET_INFO=y +CONFIG_DEBUG_NET_WARN=y +CONFIG_DEBUG_WIRELESS=y +CONFIG_DEBUG_WIRELESS_ERROR=y +CONFIG_DEBUG_WIRELESS_INFO=y +CONFIG_DEBUG_WIRELESS_WARN=y +CONFIG_DRIVERS_IEEE802154=y +CONFIG_DRIVERS_WIRELESS=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_IEEE802154_I8SAK=y +CONFIG_IEEE802154_MAC=y +CONFIG_IEEE802154_MACDEV=y +CONFIG_IEEE802154_MRF24J40=y +CONFIG_IEEE802154_NETDEV=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_IOB_BUFSIZE=128 +CONFIG_IOB_NBUFFERS=32 +CONFIG_IOB_NCHAINS=16 +CONFIG_LINE_MAX=64 +CONFIG_MAC802154_NTXDESC=32 +CONFIG_MM_REGIONS=2 +CONFIG_NET=y +CONFIG_NETDEV_IFINDEX=y +CONFIG_NETDEV_LATEINIT=y +CONFIG_NETDEV_PHY_IOCTL=y +CONFIG_NETDEV_STATISTICS=y +CONFIG_NETDEV_WIRELESS_IOCTL=y +CONFIG_NETUTILS_TELNETD=y +CONFIG_NET_6LOWPAN=y +CONFIG_NET_6LOWPAN_COMPRESSION_THRESHOLD=500 +CONFIG_NET_6LOWPAN_EXTENDEDADDR=y +CONFIG_NET_BROADCAST=y +CONFIG_NET_ICMPv6=y +CONFIG_NET_ICMPv6_AUTOCONF=y +CONFIG_NET_ICMPv6_NEIGHBOR=y +CONFIG_NET_ICMPv6_ROUTER=y +CONFIG_NET_ICMPv6_SOCKET=y +CONFIG_NET_IPv6=y +CONFIG_NET_PROMISCUOUS=y +CONFIG_NET_ROUTE=y +CONFIG_NET_SOCKOPTS=y +CONFIG_NET_STATISTICS=y +CONFIG_NET_TCP=y +CONFIG_NET_TCP_WRITE_BUFFERS=y +CONFIG_NET_UDP=y +CONFIG_NET_UDP_WRITE_BUFFERS=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_LPWORK=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PWR=y +CONFIG_STM32_SPI1=y +CONFIG_STM32_USART3=y +CONFIG_SYSTEM_NSH=y +CONFIG_SYSTEM_PING6=y +CONFIG_SYSTEM_SYSTEM=y +CONFIG_USART3_RXBUFSIZE=128 +CONFIG_USART3_TXBUFSIZE=128 +CONFIG_USBDEV=y +CONFIG_WIRELESS=y +CONFIG_WIRELESS_IEEE802154=y diff --git a/boards/arm/stm32f4/olimex-stm32-e407/configs/mrf24j40-mac/defconfig b/boards/arm/stm32f4/olimex-stm32-e407/configs/mrf24j40-mac/defconfig new file mode 100644 index 0000000000000..1f65505de8fef --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-e407/configs/mrf24j40-mac/defconfig @@ -0,0 +1,63 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="olimex-stm32-e407" +CONFIG_ARCH_BOARD_OLIMEX_STM32E407=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F407ZG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_DEBUG_FEATURES=y +CONFIG_DEBUG_WIRELESS=y +CONFIG_DEBUG_WIRELESS_ERROR=y +CONFIG_DEBUG_WIRELESS_INFO=y +CONFIG_DEBUG_WIRELESS_WARN=y +CONFIG_DRIVERS_IEEE802154=y +CONFIG_DRIVERS_WIRELESS=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_IEEE802154_I8SAK=y +CONFIG_IEEE802154_MAC=y +CONFIG_IEEE802154_MACDEV=y +CONFIG_IEEE802154_MRF24J40=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_MM_REGIONS=2 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_LPWORK=y +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_PWR=y +CONFIG_STM32_SPI1=y +CONFIG_STM32_USART3=y +CONFIG_SYSTEM_NSH=y +CONFIG_USART3_RXBUFSIZE=128 +CONFIG_USART3_SERIAL_CONSOLE=y +CONFIG_USART3_TXBUFSIZE=128 +CONFIG_WIRELESS=y +CONFIG_WIRELESS_IEEE802154=y diff --git a/boards/arm/stm32f4/olimex-stm32-e407/configs/netnsh/defconfig b/boards/arm/stm32f4/olimex-stm32-e407/configs/netnsh/defconfig new file mode 100644 index 0000000000000..40f0c41a88e7d --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-e407/configs/netnsh/defconfig @@ -0,0 +1,76 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="olimex-stm32-e407" +CONFIG_ARCH_BOARD_OLIMEX_STM32E407=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F407ZG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_ARM_TOOLCHAIN_BUILDROOT=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_ETH0_PHY_LAN8720=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_MM_REGIONS=2 +CONFIG_NET=y +CONFIG_NETDB_DNSCLIENT=y +CONFIG_NETINIT_DHCPC=y +CONFIG_NETINIT_DRIPADDR=0xc0a80101 +CONFIG_NETINIT_NOMAC=y +CONFIG_NETUTILS_DHCPC=y +CONFIG_NETUTILS_DISCOVER=y +CONFIG_NETUTILS_TELNETD=y +CONFIG_NET_ARP_IPIN=y +CONFIG_NET_BROADCAST=y +CONFIG_NET_ICMP_SOCKET=y +CONFIG_NET_MAX_LISTENPORTS=40 +CONFIG_NET_STATISTICS=y +CONFIG_NET_TCP=y +CONFIG_NET_TCP_PREALLOC_CONNS=40 +CONFIG_NET_UDP=y +CONFIG_NET_UDP_CHECKSUMS=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_WAITPID=y +CONFIG_SPI=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_ETHMAC=y +CONFIG_STM32_JTAG_FULL_ENABLE=y +CONFIG_STM32_PHYADDR=0 +CONFIG_STM32_PHYSR=31 +CONFIG_STM32_PHYSR_100FD=0x0018 +CONFIG_STM32_PHYSR_100HD=0x0008 +CONFIG_STM32_PHYSR_10FD=0x0014 +CONFIG_STM32_PHYSR_10HD=0x0004 +CONFIG_STM32_PHYSR_ALTCONFIG=y +CONFIG_STM32_PHYSR_ALTMODE=0x001c +CONFIG_STM32_PWR=y +CONFIG_STM32_RMII_EXTCLK=y +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_NSH=y +CONFIG_SYSTEM_PING=y +CONFIG_USART2_RXBUFSIZE=128 +CONFIG_USART2_SERIAL_CONSOLE=y +CONFIG_USART2_TXBUFSIZE=128 diff --git a/boards/arm/stm32f4/olimex-stm32-e407/configs/nsh/defconfig b/boards/arm/stm32f4/olimex-stm32-e407/configs/nsh/defconfig new file mode 100644 index 0000000000000..0dd7bf92b27cb --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-e407/configs/nsh/defconfig @@ -0,0 +1,49 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="olimex-stm32-e407" +CONFIG_ARCH_BOARD_OLIMEX_STM32E407=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F407ZG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_EXAMPLES_HELLO=y +CONFIG_EXAMPLES_HELLOXX=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_MM_REGIONS=2 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_PWR=y +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_NSH=y +CONFIG_USART2_RXBUFSIZE=128 +CONFIG_USART2_SERIAL_CONSOLE=y +CONFIG_USART2_TXBUFSIZE=128 diff --git a/boards/arm/stm32f4/olimex-stm32-e407/configs/telnetd/defconfig b/boards/arm/stm32f4/olimex-stm32-e407/configs/telnetd/defconfig new file mode 100644 index 0000000000000..bd9d1caa9a893 --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-e407/configs/telnetd/defconfig @@ -0,0 +1,79 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="olimex-stm32-e407" +CONFIG_ARCH_BOARD_OLIMEX_STM32E407=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F407ZG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_ARM_TOOLCHAIN_BUILDROOT=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_ETH0_PHY_LAN8720=y +CONFIG_EXAMPLES_TELNETD=y +CONFIG_EXAMPLES_TELNETD_CLIENTPRIO=128 +CONFIG_EXAMPLES_TELNETD_DAEMONPRIO=128 +CONFIG_EXAMPLES_TELNETD_DRIPADDR=0xc0a80101 +CONFIG_EXAMPLES_TELNETD_IPADDR=0xc0a80185 +CONFIG_EXAMPLES_TELNETD_NOMAC=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INIT_ENTRYPOINT="telnetd_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_MM_REGIONS=2 +CONFIG_NET=y +CONFIG_NETDB_DNSCLIENT=y +CONFIG_NETUTILS_DHCPC=y +CONFIG_NETUTILS_DISCOVER=y +CONFIG_NETUTILS_TELNETD=y +CONFIG_NET_ARP_IPIN=y +CONFIG_NET_BROADCAST=y +CONFIG_NET_ICMP_SOCKET=y +CONFIG_NET_MAX_LISTENPORTS=40 +CONFIG_NET_STATISTICS=y +CONFIG_NET_TCP=y +CONFIG_NET_TCP_PREALLOC_CONNS=40 +CONFIG_NET_UDP=y +CONFIG_NET_UDP_CHECKSUMS=y +CONFIG_NSH_LIBRARY=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_WAITPID=y +CONFIG_SPI=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_ETHMAC=y +CONFIG_STM32_JTAG_FULL_ENABLE=y +CONFIG_STM32_PHYADDR=0 +CONFIG_STM32_PHYSR=31 +CONFIG_STM32_PHYSR_100FD=0x0018 +CONFIG_STM32_PHYSR_100HD=0x0008 +CONFIG_STM32_PHYSR_10FD=0x0014 +CONFIG_STM32_PHYSR_10HD=0x0004 +CONFIG_STM32_PHYSR_ALTCONFIG=y +CONFIG_STM32_PHYSR_ALTMODE=0x001c +CONFIG_STM32_PWR=y +CONFIG_STM32_RMII_EXTCLK=y +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_PING=y +CONFIG_SYSTEM_READLINE=y +CONFIG_USART2_RXBUFSIZE=128 +CONFIG_USART2_SERIAL_CONSOLE=y +CONFIG_USART2_TXBUFSIZE=128 diff --git a/boards/arm/stm32f4/olimex-stm32-e407/configs/timer/defconfig b/boards/arm/stm32f4/olimex-stm32-e407/configs/timer/defconfig new file mode 100644 index 0000000000000..578b077e1bad4 --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-e407/configs/timer/defconfig @@ -0,0 +1,54 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="olimex-stm32-e407" +CONFIG_ARCH_BOARD_OLIMEX_STM32E407=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F407ZG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL_USBDEVCTRL=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_CDCACM=y +CONFIG_CDCACM_CONSOLE=y +CONFIG_EXAMPLES_HELLO=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_MM_REGIONS=2 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PWR=y +CONFIG_STM32_TIM1=y +CONFIG_STM32_USART3=y +CONFIG_SYSTEM_NSH=y +CONFIG_TIMER=y +CONFIG_USART3_RXBUFSIZE=128 +CONFIG_USART3_TXBUFSIZE=128 +CONFIG_USBDEV=y diff --git a/boards/arm/stm32f4/olimex-stm32-e407/configs/usbnsh/defconfig b/boards/arm/stm32f4/olimex-stm32-e407/configs/usbnsh/defconfig new file mode 100644 index 0000000000000..9cfbc79057571 --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-e407/configs/usbnsh/defconfig @@ -0,0 +1,55 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_DEV_CONSOLE is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="olimex-stm32-e407" +CONFIG_ARCH_BOARD_OLIMEX_STM32E407=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F407ZG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL_USBDEVCTRL=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_CDCACM=y +CONFIG_CDCACM_CONSOLE=y +CONFIG_CDCACM_RXBUFSIZE=256 +CONFIG_CDCACM_TXBUFSIZE=256 +CONFIG_EXAMPLES_HELLO=y +CONFIG_EXAMPLES_HELLOXX=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_MM_REGIONS=2 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_SPI=y +CONFIG_START_DAY=27 +CONFIG_START_YEAR=2013 +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PWR=y +CONFIG_STM32_USART2=y +CONFIG_SYSLOG_CHAR=y +CONFIG_SYSLOG_DEVPATH="/dev/ttyS0" +CONFIG_SYSTEM_NSH=y +CONFIG_USBDEV=y diff --git a/boards/arm/stm32f4/olimex-stm32-e407/configs/webserver/defconfig b/boards/arm/stm32f4/olimex-stm32-e407/configs/webserver/defconfig new file mode 100644 index 0000000000000..05748b1f5ee17 --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-e407/configs/webserver/defconfig @@ -0,0 +1,73 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="olimex-stm32-e407" +CONFIG_ARCH_BOARD_OLIMEX_STM32E407=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F407ZG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_ARM_TOOLCHAIN_BUILDROOT=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_ETH0_PHY_LAN8720=y +CONFIG_EXAMPLES_WEBSERVER=y +CONFIG_EXAMPLES_WEBSERVER_DRIPADDR=0xc0a80101 +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INIT_ENTRYPOINT="webserver_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_MM_REGIONS=2 +CONFIG_NET=y +CONFIG_NETDB_DNSCLIENT=y +CONFIG_NETUTILS_DHCPC=y +CONFIG_NETUTILS_DISCOVER=y +CONFIG_NETUTILS_WEBSERVER=y +CONFIG_NET_ARP_IPIN=y +CONFIG_NET_BROADCAST=y +CONFIG_NET_ICMP_SOCKET=y +CONFIG_NET_MAX_LISTENPORTS=40 +CONFIG_NET_STATISTICS=y +CONFIG_NET_TCP=y +CONFIG_NET_TCP_PREALLOC_CONNS=40 +CONFIG_NET_UDP=y +CONFIG_NET_UDP_CHECKSUMS=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_WAITPID=y +CONFIG_SPI=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_ETHMAC=y +CONFIG_STM32_JTAG_FULL_ENABLE=y +CONFIG_STM32_PHYADDR=0 +CONFIG_STM32_PHYSR=31 +CONFIG_STM32_PHYSR_100FD=0x0018 +CONFIG_STM32_PHYSR_100HD=0x0008 +CONFIG_STM32_PHYSR_10FD=0x0014 +CONFIG_STM32_PHYSR_10HD=0x0004 +CONFIG_STM32_PHYSR_ALTCONFIG=y +CONFIG_STM32_PHYSR_ALTMODE=0x001c +CONFIG_STM32_PWR=y +CONFIG_STM32_RMII_EXTCLK=y +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_PING=y +CONFIG_USART2_RXBUFSIZE=128 +CONFIG_USART2_SERIAL_CONSOLE=y +CONFIG_USART2_TXBUFSIZE=128 diff --git a/boards/arm/stm32f4/olimex-stm32-e407/include/board.h b/boards/arm/stm32f4/olimex-stm32-e407/include/board.h new file mode 100644 index 0000000000000..a12b129b4ddcc --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-e407/include/board.h @@ -0,0 +1,280 @@ +/**************************************************************************** + * boards/arm/stm32f4/olimex-stm32-e407/include/board.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_STM32_OLIMEX_STM32_E407_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32_OLIMEX_STM32_E407_INCLUDE_BOARD_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#ifndef __ASSEMBLY__ +# include +# include +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Clocking *****************************************************************/ + +/* The Olimex-STM32-E407 board features a 12MHz crystal and + * a 32kHz RTC backup crystal. + * + * This is the canonical configuration: + * System Clock source : PLL (HSE) + * SYSCLK(Hz) : 168000000 Determined by PLL configuration + * HCLK(Hz) : 168000000 (STM32_RCC_CFGR_HPRE) + * AHB Prescaler : 1 (STM32_RCC_CFGR_HPRE) + * APB1 Prescaler : 4 (STM32_RCC_CFGR_PPRE1) + * APB2 Prescaler : 2 (STM32_RCC_CFGR_PPRE2) + * HSE Frequency(Hz) : 8000000 (STM32_BOARD_XTAL) + * PLLM : 8 (STM32_PLLCFG_PLLM) + * PLLN : 336 (STM32_PLLCFG_PLLN) + * PLLP : 2 (STM32_PLLCFG_PLLP) + * PLLQ : 7 (STM32_PLLCFG_PLLQ) + * Main regulator output + * voltage : Scale1 mode Needed for high speed SYSCLK + * Flash Latency(WS) : 5 + * Prefetch Buffer : OFF + * Instruction cache : ON + * Data cache : ON + * Require 48MHz for : Enabled + * USB OTG FS, + * SDIO and RNG clock + */ + +/* HSI - 16 MHz RC factory-trimmed + * LSI - 32 KHz RC (30-60KHz, uncalibrated) + * HSE - On-board crystal frequency is 12MHz + * LSE - 32.768 kHz + * STM32F407ZGT6 - too 168Mhz + */ + +#define STM32_BOARD_XTAL 12000000ul + +#define STM32_HSI_FREQUENCY 16000000ul +#define STM32_LSI_FREQUENCY 32000 +#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL +#define STM32_LSE_FREQUENCY 32768 + +/* Main PLL Configuration. + * + * PLL source is HSE + * PLL_VCO = (STM32_HSE_FREQUENCY / PLLM) * PLLN + * = (25,000,000 / 12) * 360 + * = 240,000,000 + * SYSCLK = PLL_VCO / PLLP + * = 240,000,000 / 2 = 120,000,000 + * USB OTG FS, SDIO and RNG Clock + * = PLL_VCO / PLLQ + * = 240,000,000 / 5 = 48,000,000 + * = 48,000,000 + * + * Xtal /M *n /P SysClk AHB HCLK APB1 PCLK1 + * 12Mhz HSE /12 336 /2 PLLCLK 168Mhz /1 168 /4 42Mhz + * 12Mhz HSE /6 168 /2 PLLCLK 168Mhz /1 168 /4 42Mhz + */ + +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(3) +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(84) +#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_2 +#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(5) +#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(7) + +#define STM32_SYSCLK_FREQUENCY 168000000ul + +/* AHB clock (HCLK) is SYSCLK (168MHz) */ + +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY + +/* APB1 clock (PCLK1) is HCLK/4 (42MHz) */ + +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd4 /* PCLK1 = HCLK / 4 */ +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/4) + +/* Timers driven from APB1 will be twice PCLK1 */ + +#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) + +/* APB2 clock (PCLK2) is HCLK/2 */ + +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLKd2 /* PCLK2 = HCLK / 2 */ +#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/2) + +/* Timers driven from APB2 will be twice PCLK2 */ + +#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM9_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM10_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM11_CLKIN (2*STM32_PCLK2_FREQUENCY) + +/* Timer Frequencies, if APBx is set to 1, frequency is same as APBx + * otherwise frequency is 2xAPBx. + * Note: TIM1,8 are on APB2, others on APB1 + */ + +#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM2_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM3_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM4_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM5_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM6_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM7_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY + +/* LED definitions **********************************************************/ + +/* If CONFIG_ARCH_LEDS is not defined, then the user can control the status + * LED in any way. + * The following definitions are used to access individual LEDs. + */ + +/* LED index values for use with board_userled() */ + +#define BOARD_LED_STATUS 0 +#define BOARD_NLEDS 1 + +/* LED bits for use with board_userled_all() */ + +#define BOARD_LED_STATUS_BIT (1 << BOARD_LED1) + +/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the status LED of + * the Olimex STM32-E405. + * The following definitions describe how NuttX controls the LEDs: + */ + +#define LED_STARTED 0 /* LED_STATUS on */ +#define LED_HEAPALLOCATE 1 /* no change */ +#define LED_IRQSENABLED 2 /* no change */ +#define LED_STACKCREATED 3 /* no change */ +#define LED_INIRQ 4 /* no change */ +#define LED_SIGNAL 5 /* no change */ +#define LED_ASSERTION 6 /* LED_STATUS off */ +#define LED_PANIC 7 /* LED_STATUS blinking */ + +/* Button definitions *******************************************************/ + +/* The Olimex STM32-E405 supports one buttons: */ + +#define BUTTON_BUT 0 +#define NUM_BUTTONS 1 + +#define BUTTON_BUT_BIT (1 << BUTTON_BUT) + +/* Alternate function pin selections ****************************************/ + +/* USART1 */ + +#define GPIO_USART1_RX (GPIO_USART1_RX_2|GPIO_SPEED_100MHz) /* PB7 */ +#define GPIO_USART1_TX (GPIO_USART1_TX_2|GPIO_SPEED_100MHz) /* PB6 */ + +/* USART2 */ + +#define GPIO_USART2_RX (GPIO_USART2_RX_2|GPIO_SPEED_100MHz) /* PD6 */ +#define GPIO_USART2_TX (GPIO_USART2_TX_2|GPIO_SPEED_100MHz) /* PD5 */ + +/* USART3 */ + +#define GPIO_USART3_RX (GPIO_USART3_RX_1|GPIO_SPEED_100MHz) /* PB11 */ +#define GPIO_USART3_TX (GPIO_USART3_TX_1|GPIO_SPEED_100MHz) /* PB10 */ + +/* CAN */ + +#define GPIO_CAN1_RX (GPIO_CAN1_RX_2|GPIO_SPEED_50MHz) /* PB8 */ +#define GPIO_CAN1_TX (GPIO_CAN1_TX_2|GPIO_SPEED_50MHz) /* PB9 */ + +/* I2C */ + +#define GPIO_I2C1_SCL (GPIO_I2C1_SCL_1|GPIO_SPEED_50MHz) /* PB6 */ +#define GPIO_I2C1_SDA (GPIO_I2C1_SDA_1|GPIO_SPEED_50MHz) /* PB7 */ + +/* SPI1 */ + +#define GPIO_SPI1_SCK (GPIO_SPI1_SCK_1|GPIO_SPEED_50MHz) /* PA5 */ +#define GPIO_SPI1_MOSI (GPIO_SPI1_MOSI_2|GPIO_SPEED_50MHz) /* PB5 */ +#define GPIO_SPI1_MISO (GPIO_SPI1_MISO_1|GPIO_SPEED_50MHz) /* PA6 */ + +/* Ethernet *****************************************************************/ + +#if defined(CONFIG_STM32_ETHMAC) +/* RMII interface to the LAN8710 PHY (works with LAN8720 driver) */ + +# ifndef CONFIG_STM32_RMII +# error CONFIG_STM32_RMII must be defined +# endif + +/* Clocking is provided by an external 50Mhz XTAL */ + +# ifndef CONFIG_STM32_RMII_EXTCLK +# error CONFIG_STM32_RMII_EXTCLK must be defined +# endif + +/* Pin disambiguation */ + +# define GPIO_ETH_MII_COL (GPIO_ETH_MII_COL_1|GPIO_SPEED_100MHz) /* PA3 */ +# define GPIO_ETH_RMII_TXD0 (GPIO_ETH_RMII_TXD0_2|GPIO_SPEED_100MHz) /* PG13 */ +# define GPIO_ETH_RMII_TXD1 (GPIO_ETH_RMII_TXD1_2|GPIO_SPEED_100MHz) /* PG14 */ +# define GPIO_ETH_RMII_TX_EN (GPIO_ETH_RMII_TX_EN_2|GPIO_SPEED_100MHz) /* PG11 */ + +#endif + +/* ETH MII/RMII inputs and MDC/MDIO (referenced by arch driver) */ + +#define GPIO_ETH_MDC (GPIO_ETH_MDC_0|GPIO_SPEED_100MHz) +#define GPIO_ETH_MDIO (GPIO_ETH_MDIO_0|GPIO_SPEED_100MHz) +#define GPIO_ETH_MII_RX_CLK (GPIO_ETH_MII_RX_CLK_0|GPIO_SPEED_100MHz) +#define GPIO_ETH_MII_RX_DV (GPIO_ETH_MII_RX_DV_0|GPIO_SPEED_100MHz) +#define GPIO_ETH_MII_RXD0 (GPIO_ETH_MII_RXD0_0|GPIO_SPEED_100MHz) +#define GPIO_ETH_MII_RXD1 (GPIO_ETH_MII_RXD1_0|GPIO_SPEED_100MHz) +#define GPIO_ETH_RMII_CRS_DV (GPIO_ETH_RMII_CRS_DV_0|GPIO_SPEED_100MHz) +#define GPIO_ETH_RMII_REF_CLK (GPIO_ETH_RMII_REF_CLK_0|GPIO_SPEED_100MHz) +#define GPIO_ETH_RMII_RXD0 (GPIO_ETH_RMII_RXD0_0|GPIO_SPEED_100MHz) +#define GPIO_ETH_RMII_RXD1 (GPIO_ETH_RMII_RXD1_0|GPIO_SPEED_100MHz) +#define GPIO_MCO1 (GPIO_MCO1_0|GPIO_SPEED_100MHz) + +/* DAC */ + +#define GPIO_DAC1_OUT1 GPIO_DAC1_OUT1_0 +#define GPIO_DAC1_OUT2 GPIO_DAC1_OUT2_0 + +/* USB OTG FS */ + +#define GPIO_OTGFS_DM (GPIO_OTGFS_DM_0|GPIO_SPEED_100MHz) +#define GPIO_OTGFS_DP (GPIO_OTGFS_DP_0|GPIO_SPEED_100MHz) +#define GPIO_OTGFS_ID (GPIO_OTGFS_ID_0|GPIO_SPEED_100MHz) +#define GPIO_OTGFS_SOF (GPIO_OTGFS_SOF_0|GPIO_SPEED_100MHz) + +#endif /* __BOARDS_ARM_STM32_OLIMEX_STM32_E407_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32f4/olimex-stm32-e407/scripts/Make.defs b/boards/arm/stm32f4/olimex-stm32-e407/scripts/Make.defs new file mode 100644 index 0000000000000..884d70b69442b --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-e407/scripts/Make.defs @@ -0,0 +1,46 @@ +############################################################################ +# boards/arm/stm32f4/olimex-stm32-e407/scripts/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/.config +include $(TOPDIR)/tools/Config.mk +include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs + +ifeq ($(CONFIG_ARCH_CHIP_STM32F407ZE),y) +LDSCRIPT = f407ze.ld +else ifeq ($(CONFIG_ARCH_CHIP_STM32F407ZG),y) +LDSCRIPT = f407zg.ld +endif + +ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) + +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32/olimex-stm32-e407/scripts/f407ze.ld b/boards/arm/stm32f4/olimex-stm32-e407/scripts/f407ze.ld similarity index 98% rename from boards/arm/stm32/olimex-stm32-e407/scripts/f407ze.ld rename to boards/arm/stm32f4/olimex-stm32-e407/scripts/f407ze.ld index 654c8e73ab517..283be36be0f54 100644 --- a/boards/arm/stm32/olimex-stm32-e407/scripts/f407ze.ld +++ b/boards/arm/stm32f4/olimex-stm32-e407/scripts/f407ze.ld @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/olimex-stm32-e407/scripts/f407ze.ld + * boards/arm/stm32f4/olimex-stm32-e407/scripts/f407ze.ld * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/olimex-stm32-e407/scripts/f407zg.ld b/boards/arm/stm32f4/olimex-stm32-e407/scripts/f407zg.ld similarity index 98% rename from boards/arm/stm32/olimex-stm32-e407/scripts/f407zg.ld rename to boards/arm/stm32f4/olimex-stm32-e407/scripts/f407zg.ld index 3760d7df2012c..f0bd2b2277403 100644 --- a/boards/arm/stm32/olimex-stm32-e407/scripts/f407zg.ld +++ b/boards/arm/stm32f4/olimex-stm32-e407/scripts/f407zg.ld @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/olimex-stm32-e407/scripts/f407zg.ld + * boards/arm/stm32f4/olimex-stm32-e407/scripts/f407zg.ld * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f4/olimex-stm32-e407/src/CMakeLists.txt b/boards/arm/stm32f4/olimex-stm32-e407/src/CMakeLists.txt new file mode 100644 index 0000000000000..c3ee8a36e6686 --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-e407/src/CMakeLists.txt @@ -0,0 +1,77 @@ +# ############################################################################## +# boards/arm/stm32f4/olimex-stm32-e407/src/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(SRCS stm32_boot.c stm32_bringup.c stm32_spi.c) + +if(CONFIG_ARCH_LEDS) + list(APPEND SRCS stm32_autoleds.c) +else() + list(APPEND SRCS stm32_userleds.c) +endif() + +if(CONFIG_ARCH_BUTTONS) + list(APPEND SRCS stm32_buttons.c) +endif() + +if(CONFIG_ARCH_IDLE_CUSTOM) + list(APPEND SRCS stm32_idle.c) +endif() + +if(CONFIG_STM32_FSMC) + list(APPEND SRCS stm32_extmem.c) +endif() + +if(CONFIG_STM32_OTGFS) + list(APPEND SRCS stm32_usb.c) +endif() + +if(CONFIG_STM32_OTGHS) + list(APPEND SRCS stm32_usb.c) +endif() + +if(CONFIG_ADC) + list(APPEND SRCS stm32_adc.c) +endif() + +if(CONFIG_CAN) + list(APPEND SRCS stm32_can.c) +endif() + +if(CONFIG_DAC) + list(APPEND SRCS stm32_dac.c) +endif() + +if(CONFIG_TIMER) + list(APPEND SRCS stm32_timer.c) +endif() + +if(CONFIG_IEEE802154_MRF24J40) + list(APPEND SRCS stm32_mrf24j40.c) +endif() + +target_sources(board PRIVATE ${SRCS}) + +if(CONFIG_ARCH_CHIP_STM32F407ZE) + set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/f407ze.ld") +else() + set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/f407zg.ld") +endif() diff --git a/boards/arm/stm32f4/olimex-stm32-e407/src/Make.defs b/boards/arm/stm32f4/olimex-stm32-e407/src/Make.defs new file mode 100644 index 0000000000000..84b3dce9a7828 --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-e407/src/Make.defs @@ -0,0 +1,75 @@ +############################################################################ +# boards/arm/stm32f4/olimex-stm32-e407/src/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +CSRCS = stm32_boot.c stm32_bringup.c stm32_spi.c + +ifeq ($(CONFIG_ARCH_LEDS),y) +CSRCS += stm32_autoleds.c +else +CSRCS += stm32_userleds.c +endif + +ifeq ($(CONFIG_ARCH_BUTTONS),y) +CSRCS += stm32_buttons.c +endif + +ifeq ($(CONFIG_ARCH_IDLE_CUSTOM),y) +CSRCS += stm32_idle.c +endif + +ifeq ($(CONFIG_STM32_FSMC),y) +CSRCS += stm32_extmem.c +endif + +ifeq ($(CONFIG_STM32_OTGFS),y) +CSRCS += stm32_usb.c +endif + +ifeq ($(CONFIG_STM32_OTGHS),y) +CSRCS += stm32_usb.c +endif + +ifeq ($(CONFIG_ADC),y) +CSRCS += stm32_adc.c +endif + +ifeq ($(CONFIG_CAN),y) +CSRCS += stm32_can.c +endif + +ifeq ($(CONFIG_DAC),y) +CSRCS += stm32_dac.c +endif + +ifeq ($(CONFIG_TIMER),y) +CSRCS += stm32_timer.c +endif + +ifeq ($(CONFIG_IEEE802154_MRF24J40),y) +CSRCS += stm32_mrf24j40.c +endif + +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/olimex-stm32-e407/src/olimex-stm32-e407.h b/boards/arm/stm32f4/olimex-stm32-e407/src/olimex-stm32-e407.h similarity index 99% rename from boards/arm/stm32/olimex-stm32-e407/src/olimex-stm32-e407.h rename to boards/arm/stm32f4/olimex-stm32-e407/src/olimex-stm32-e407.h index 7d1d5064417ca..ee640dbc99df9 100644 --- a/boards/arm/stm32/olimex-stm32-e407/src/olimex-stm32-e407.h +++ b/boards/arm/stm32f4/olimex-stm32-e407/src/olimex-stm32-e407.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/olimex-stm32-e407/src/olimex-stm32-e407.h + * boards/arm/stm32f4/olimex-stm32-e407/src/olimex-stm32-e407.h * * SPDX-License-Identifier: Apache-2.0 * @@ -30,7 +30,7 @@ #include #include #include -#include +#include #include "stm32.h" diff --git a/boards/arm/stm32f4/olimex-stm32-e407/src/stm32_adc.c b/boards/arm/stm32f4/olimex-stm32-e407/src/stm32_adc.c new file mode 100644 index 0000000000000..7796617d96b7a --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-e407/src/stm32_adc.c @@ -0,0 +1,166 @@ +/**************************************************************************** + * boards/arm/stm32f4/olimex-stm32-e407/src/stm32_adc.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include +#include + +#include "chip.h" +#include "stm32_adc.h" +#include "olimex-stm32-e407.h" + +#ifdef CONFIG_ADC + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* Up to 3 ADC interfaces are supported */ + +#if STM32_NADC < 3 +# undef CONFIG_STM32_ADC3 +#endif + +#if STM32_NADC < 2 +# undef CONFIG_STM32_ADC2 +#endif + +#if STM32_NADC < 1 +# undef CONFIG_STM32_ADC1 +#endif + +#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) || defined(CONFIG_STM32_ADC3) +#ifndef CONFIG_STM32_ADC1 +# warning "Channel information only available for ADC1" +#endif + +/* The number of ADC channels in the conversion list */ + +#define ADC1_NCHANNELS 1//14 + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* The Olimex STM32-P405 has a 10 Kohm potentiometer AN_TR connected to PC0 + * ADC123_IN10 + */ + +/* Identifying number of each ADC channel: Variable Resistor. + * + * {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 15}; + */ + +#ifdef CONFIG_STM32_ADC1 +static const uint8_t g_chanlist[ADC1_NCHANNELS] = +{ + 1 +}; + +/* Configurations of pins used byte each ADC channels + * + * {GPIO_ADC1_IN1, GPIO_ADC1_IN2, GPIO_ADC1_IN3, + * GPIO_ADC1_IN4, GPIO_ADC1_IN5, GPIO_ADC1_IN6, + * GPIO_ADC1_IN7, GPIO_ADC1_IN8, GPIO_ADC1_IN9, + * GPIO_ADC1_IN10, GPIO_ADC1_IN11, GPIO_ADC1_IN12, + * GPIO_ADC1_IN13, GPIO_ADC1_IN15}; + */ + +static const uint32_t g_pinlist[ADC1_NCHANNELS] = +{ + GPIO_ADC1_IN1 +}; +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_adc_setup + * + * Description: + * Initialize ADC and register the ADC driver. + * + ****************************************************************************/ + +int stm32_adc_setup(void) +{ +#ifdef CONFIG_STM32_ADC1 + static bool initialized = false; + struct adc_dev_s *adc; + int ret; + int i; + + /* Check if we have already initialized */ + + if (!initialized) + { + /* Configure the pins as analog inputs for the selected channels */ + + for (i = 0; i < ADC1_NCHANNELS; i++) + { + stm32_configgpio(g_pinlist[i]); + } + + /* Call stm32_adcinitialize() to get an instance of the ADC interface */ + + adc = stm32_adcinitialize(1, g_chanlist, ADC1_NCHANNELS); + if (adc == NULL) + { + adbg("ERROR: Failed to get ADC interface\n"); + return -ENODEV; + } + + /* Register the ADC driver at "/dev/adc0" */ + + ret = adc_register("/dev/adc0", adc); + if (ret < 0) + { + adbg("adc_register failed: %d\n", ret); + return ret; + } + + /* Now we are initialized */ + + initialized = true; + } + + return OK; +#else + return -ENOSYS; +#endif +} + +#endif /* CONFIG_STM32_ADC1 || CONFIG_STM32_ADC2 || CONFIG_STM32_ADC3 */ +#endif /* CONFIG_ADC */ diff --git a/boards/arm/stm32f4/olimex-stm32-e407/src/stm32_autoleds.c b/boards/arm/stm32f4/olimex-stm32-e407/src/stm32_autoleds.c new file mode 100644 index 0000000000000..d58f96ed9e944 --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-e407/src/stm32_autoleds.c @@ -0,0 +1,92 @@ +/**************************************************************************** + * boards/arm/stm32f4/olimex-stm32-e407/src/stm32_autoleds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32.h" +#include "olimex-stm32-e407.h" + +#ifdef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_autoled_initialize + ****************************************************************************/ + +void board_autoled_initialize(void) +{ + /* Configure LED_STATUS GPIO for output */ + + stm32_configgpio(GPIO_LED_STATUS); +} + +/**************************************************************************** + * Name: board_autoled_on + ****************************************************************************/ + +void board_autoled_on(int led) +{ + if (led == LED_STARTED) + { + stm32_gpiowrite(GPIO_LED_STATUS, true); + } + + if (led == LED_ASSERTION || led == LED_PANIC) + { + stm32_gpiowrite(GPIO_LED_STATUS, false); + } +} + +/**************************************************************************** + * Name: board_autoled_off + ****************************************************************************/ + +void board_autoled_off(int led) +{ + if (led == LED_STARTED) + { + stm32_gpiowrite(GPIO_LED_STATUS, false); + } + + if (led == LED_ASSERTION || led == LED_PANIC) + { + stm32_gpiowrite(GPIO_LED_STATUS, true); + } +} + +#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32f4/olimex-stm32-e407/src/stm32_boot.c b/boards/arm/stm32f4/olimex-stm32-e407/src/stm32_boot.c new file mode 100644 index 0000000000000..b9bc201270e0e --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-e407/src/stm32_boot.c @@ -0,0 +1,105 @@ +/**************************************************************************** + * boards/arm/stm32f4/olimex-stm32-e407/src/stm32_boot.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include +#include +#include + +#include "arm_internal.h" +#include "stm32_ccm.h" +#include "stm32.h" +#include "stm32_i2c.h" + +#include "olimex-stm32-e407.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_boardinitialize + * + * Description: + * All STM32 architectures must provide the following entry point. This + * entry point is called early in the initialization -- after all memory + * has been configured and mapped but before any devices have been + * initialized. + * + ****************************************************************************/ + +void stm32_boardinitialize(void) +{ +#if defined(CONFIG_STM32_OTGFS) || defined(CONFIG_STM32_OTGHS) + /* Initialize USB if the 1) OTG FS controller is in the configuration and + * 2) disabled, and 3) the weak function stm32_usbinitialize() has been + * brought into the build. Presumably either CONFIG_USBDEV is also + * selected. + */ + + if (stm32_usbinitialize) + { + stm32_usbinitialize(); + } +#endif + +#ifdef CONFIG_ARCH_LEDS + /* Configure on-board LEDs if LED support has been selected. */ + + board_autoled_initialize(); +#endif + +#ifdef CONFIG_ARCH_BUTTONS + /* Configure on-board BUTTONs if BUTTON support has been selected. */ + + board_button_initialize(); +#endif +} + +/**************************************************************************** + * Name: board_late_initialize + * + * Description: + * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_late_initialize(). board_late_initialize() will be + * called immediately after up_initialize() is called and just before the + * initial application is started. This additional initialization phase + * may be used, for example, to initialize board-specific device drivers. + * + ****************************************************************************/ + +#ifdef CONFIG_BOARD_LATE_INITIALIZE +void board_late_initialize(void) +{ + /* Perform board-specific initialization */ + + stm32_bringup(); +} +#endif diff --git a/boards/arm/stm32f4/olimex-stm32-e407/src/stm32_bringup.c b/boards/arm/stm32f4/olimex-stm32-e407/src/stm32_bringup.c new file mode 100644 index 0000000000000..6dab2b6595451 --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-e407/src/stm32_bringup.c @@ -0,0 +1,283 @@ +/**************************************************************************** + * boards/arm/stm32f4/olimex-stm32-e407/src/stm32_bringup.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include + +#ifdef CONFIG_USBMONITOR +# include +#endif + +#ifdef CONFIG_STM32_OTGFS +# include "stm32_usbhost.h" +#endif + +#include "stm32.h" +#include "olimex-stm32-e407.h" + +/* The following are includes from board-common logic */ + +#ifdef CONFIG_SENSORS_BMP180 +#include "stm32_bmp180.h" +#endif + +#ifdef CONFIG_SENSORS_INA219 +#include "stm32_ina219.h" +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +#define HAVE_USBDEV 1 +#define HAVE_USBHOST 1 +#define HAVE_USBMONITOR 1 +/* #define HAVE_I2CTOOL 1 */ + +/* Can't support USB host or device features if USB OTG HS is not enabled */ + +#ifndef CONFIG_STM32_OTGHS +# undef HAVE_USBDEV +# undef HAVE_USBHOST +#endif + +/* Can't support USB device USB device is not enabled */ + +#ifndef CONFIG_USBDEV +# undef HAVE_USBDEV +#endif + +/* Can't support USB host is USB host is not enabled */ + +#ifndef CONFIG_USBHOST +# undef HAVE_USBHOST +#endif + +/* Check if we should enable the USB monitor before starting NSH */ + +#ifndef CONFIG_USBMONITOR +# undef HAVE_USBMONITOR +#endif + +#ifndef HAVE_USBDEV +# undef CONFIG_USBDEV_TRACE +#endif + +#ifndef HAVE_USBHOST +# undef CONFIG_USBHOST_TRACE +#endif + +#if !defined(CONFIG_USBDEV_TRACE) && !defined(CONFIG_USBHOST_TRACE) +# undef HAVE_USBMONITOR +#endif + +#if !defined(CONFIG_STM32_CAN1) && !defined(CONFIG_STM32_CAN2) +# undef CONFIG_CAN +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_i2c_register + * + * Description: + * Register one I2C drivers for the I2C tool. + * + ****************************************************************************/ + +#ifdef HAVE_I2CTOOL +static void stm32_i2c_register(int bus) +{ + struct i2c_master_s *i2c; + int ret; + + i2c = stm32_i2cbus_initialize(bus); + if (i2c == NULL) + { + _err("ERROR: Failed to get I2C%d interface\n", bus); + } + else + { + ret = i2c_register(i2c, bus); + if (ret < 0) + { + _err("ERROR: Failed to register I2C%d driver: %d\n", bus, ret); + stm32_i2cbus_uninitialize(i2c); + } + } +} +#endif + +/**************************************************************************** + * Name: stm32_i2ctool + * + * Description: + * Register I2C drivers for the I2C tool. + * + ****************************************************************************/ + +#ifdef HAVE_I2CTOOL +static void stm32_i2ctool(void) +{ +#ifdef CONFIG_STM32_I2C1 + stm32_i2c_register(1); +#endif +#ifdef CONFIG_STM32_I2C2 + stm32_i2c_register(2); +#endif +#ifdef CONFIG_STM32_I2C3 + stm32_i2c_register(3); +#endif +} +#else +# define stm32_i2ctool() +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_bringup + * + * Description: + * Perform architecture-specific initialization + * + * CONFIG_BOARD_LATE_INITIALIZE=y : + * Called from board_late_initialize(). + * + ****************************************************************************/ + +int stm32_bringup(void) +{ + int ret; + + /* Register I2C drivers on behalf of the I2C tool */ + + stm32_i2ctool(); + +#ifdef CONFIG_CAN + /* Initialize CAN and register the CAN driver. */ + + ret = stm32_can_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_can_setup failed: %d\n", ret); + } +#endif + +#ifdef HAVE_USBHOST + /* Initialize USB host operation. stm32_usbhost_initialize() starts a + * thread will monitor for USB connection and disconnection events. + */ + + ret = stm32_usbhost_initialize(); + if (ret != OK) + { + syslog(LOG_ERR, "ERROR: Failed to initialize USB host: %d\n", ret); + return ret; + } +#endif + +#ifdef HAVE_USBMONITOR + /* Start the USB Monitor */ + + ret = usbmonitor_start(); + if (ret != OK) + { + syslog(LOG_ERR, "ERROR: Failed to start USB monitor: %d\n", ret); + } +#endif + +#ifdef CONFIG_SENSORS_BMP180 + /* Initialize the BMP180 pressure sensor. */ + + ret = board_bmp180_initialize(0, 1); + if (ret < 0) + { + syslog(LOG_ERR, "Failed to initialize BMP180, error %d\n", ret); + return ret; + } +#endif + +#ifdef CONFIG_DAC + /* Initialize DAC and register the DAC driver. */ + + ret = stm32_dac_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to start ADC1: %d\n", ret); + } +#endif + +#ifdef CONFIG_SENSORS_INA219 + /* Configure and initialize the INA219 sensor */ + + ret = board_ina219_initialize(0, 1); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_ina219initialize() failed: %d\n", ret); + } +#endif + +#if defined(CONFIG_TIMER) + /* Initialize the timer, at this moment it's only Timer 1,2,3 */ + + #if defined(CONFIG_STM32_TIM1) + stm32_timer_driver_setup("/dev/timer1", 1); + #endif + #if defined(CONFIG_STM32_TIM2) + stm32_timer_driver_setup("/dev/timer2", 2); + #endif + #if defined(CONFIG_STM32_TIM3) + stm32_timer_driver_setup("/dev/timer3", 3); + #endif +#endif + +#ifdef CONFIG_IEEE802154_MRF24J40 + /* Configure MRF24J40 wireless */ + + ret = stm32_mrf24j40_initialize(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_mrf24j40_initialize() failed:" + " %d\n", ret); + } +#endif + + UNUSED(ret); + return OK; +} diff --git a/boards/arm/stm32f4/olimex-stm32-e407/src/stm32_buttons.c b/boards/arm/stm32f4/olimex-stm32-e407/src/stm32_buttons.c new file mode 100644 index 0000000000000..09c257fd4079e --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-e407/src/stm32_buttons.c @@ -0,0 +1,140 @@ +/**************************************************************************** + * boards/arm/stm32f4/olimex-stm32-e407/src/stm32_buttons.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include +#include + +#include "olimex-stm32-e407.h" + +#ifdef CONFIG_ARCH_BUTTONS + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* Pin configuration for each Olimex-STM32-H405 button. This array is + * indexed by the BUTTON_* definitions in board.h + */ + +static const uint32_t g_buttons[NUM_BUTTONS] = +{ + GPIO_BTN_BUT +}; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_button_initialize + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. + * + ****************************************************************************/ + +uint32_t board_button_initialize(void) +{ + int i; + + /* Configure the GPIO pins as inputs. NOTE that EXTI interrupts are + * configured for all pins. + */ + + for (i = 0; i < NUM_BUTTONS; i++) + { + stm32_configgpio(g_buttons[i]); + } + + return NUM_BUTTONS; +} + +/**************************************************************************** + * Name: board_buttons + ****************************************************************************/ + +uint32_t board_buttons(void) +{ + uint32_t ret = 0; + + /* Check that state of each key */ + + if (!stm32_gpioread(g_buttons[BUTTON_BUT])) + { + ret |= BUTTON_BUT_BIT; + } + + return ret; +} + +/**************************************************************************** + * Button support. + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. + * + * After board_button_initialize() has been called, board_buttons() may be + * called to collect the state of all buttons. board_buttons() returns an + * 32-bit bit set with each bit associated with a button. See the + * BUTTON_*_BIT definitions in board.h for the meaning of each bit. + * + * board_button_irq() may be called to register an interrupt handler that + * will be called when a button is depressed or released. The ID value is + * a button enumeration value that uniquely identifies a button resource. + * See the BUTTON_* definitions in board.h for the meaning of enumeration + * value. + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_IRQBUTTONS +int board_button_irq(int id, xcpt_t irqhandler, void *arg) +{ + int ret = -EINVAL; + + /* The following should be atomic */ + + if (id >= MIN_IRQBUTTON && id <= MAX_IRQBUTTON) + { + ret = stm32_gpiosetevent(g_buttons[id], true, true, true, irqhandler, + arg); + } + + return ret; +} +#endif +#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/stm32f4/olimex-stm32-e407/src/stm32_can.c b/boards/arm/stm32f4/olimex-stm32-e407/src/stm32_can.c new file mode 100644 index 0000000000000..2550c1b3f140b --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-e407/src/stm32_can.c @@ -0,0 +1,100 @@ +/**************************************************************************** + * boards/arm/stm32f4/olimex-stm32-e407/src/stm32_can.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include + +#include "stm32.h" +#include "stm32_can.h" +#include "olimex-stm32-e407.h" + +#ifdef CONFIG_CAN + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +#if defined(CONFIG_STM32_CAN1) && defined(CONFIG_STM32_CAN2) +# warning "Both CAN1 and CAN2 are enabled. Only CAN1 is used." +# undef CONFIG_STM32_CAN2 +#endif + +#ifdef CONFIG_STM32_CAN1 +# define CAN_PORT 1 +#else +# define CAN_PORT 2 +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_can_setup + * + * Description: + * Initialize CAN and register the CAN device + * + ****************************************************************************/ + +int stm32_can_setup(void) +{ +#if defined(CONFIG_STM32_CAN1) || defined(CONFIG_STM32_CAN2) + struct can_dev_s *can; + int ret; + + /* Call stm32_caninitialize() to get an instance of the CAN interface */ + + can = stm32_caninitialize(CAN_PORT); + if (can == NULL) + { + candbg("ERROR: Failed to get CAN interface\n"); + return -ENODEV; + } + + /* Register the CAN driver at "/dev/can0" */ + + ret = can_register("/dev/can0", can); + if (ret < 0) + { + candbg("ERROR: can_register failed: %d\n", ret); + return ret; + } + + return OK; +#else + return -ENODEV; +#endif +} + +#endif /* CONFIG_CAN */ diff --git a/boards/arm/stm32f4/olimex-stm32-e407/src/stm32_dac.c b/boards/arm/stm32f4/olimex-stm32-e407/src/stm32_dac.c new file mode 100644 index 0000000000000..f553f6d94b4ef --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-e407/src/stm32_dac.c @@ -0,0 +1,110 @@ +/**************************************************************************** + * boards/arm/stm32f4/olimex-stm32-e407/src/stm32_dac.c + * + * SPDX-License-Identifier: BSD-3-Clause + * SPDX-FileCopyrightText: 2019 Acutronics Robotics All rights reserved. + * SPDX-FileContributor: Juan Flores + * SPDX-FileContributor: Juha Niskanen + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include + +#include +#include + +#include "stm32_dac.h" +#include "olimex-stm32-e407.h" + +#include + +#if defined(CONFIG_DAC) + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static struct dac_dev_s *g_dac; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_dac_setup + * + * Description: + * Initialize and register the DAC0 of the microcontroller. + * + * Input parameters: + * devpath - The full path to the driver to register. E.g., "/dev/dac0" + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +int stm32_dac_setup(void) +{ + static bool initialized = false; + + if (!initialized) + { + int ret; + + g_dac = stm32_dacinitialize(1); + if (g_dac == NULL) + { + aerr("ERROR: Failed to get DAC interface\n"); + return -ENODEV; + } + + /* Register the DAC driver at "/dev/dac0" */ + + ret = dac_register("/dev/dac0", g_dac); + if (ret < 0) + { + aerr("ERROR: dac_register failed: %d\n", ret); + return ret; + } + + initialized = true; + } + + return OK; +} + +#endif diff --git a/boards/arm/stm32f4/olimex-stm32-e407/src/stm32_mrf24j40.c b/boards/arm/stm32f4/olimex-stm32-e407/src/stm32_mrf24j40.c new file mode 100644 index 0000000000000..3baadf6977c6a --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-e407/src/stm32_mrf24j40.c @@ -0,0 +1,279 @@ +/**************************************************************************** + * boards/arm/stm32f4/olimex-stm32-e407/src/stm32_mrf24j40.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include "stm32_gpio.h" +#include "stm32_exti.h" +#include "stm32_spi.h" + +#include "olimex-stm32-e407.h" + +#ifdef CONFIG_IEEE802154_MRF24J40 + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +struct stm32_priv_s +{ + struct mrf24j40_lower_s dev; + xcpt_t handler; + void *arg; + uint32_t intcfg; + uint8_t spidev; +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/* IRQ/GPIO access callbacks. These operations all hidden behind callbacks + * to isolate the MRF24J40 driver from differences in GPIO interrupt handling + * varying boards and MCUs. + * + * irq_attach - Attach the MRF24J40 interrupt handler to the GPIO + * interrupt + * irq_enable - Enable or disable the GPIO interrupt + */ + +static int stm32_attach_irq(const struct mrf24j40_lower_s *lower, + xcpt_t handler, void *arg); +static void stm32_enable_irq(const struct mrf24j40_lower_s *lower, + bool state); +static int stm32_mrf24j40_devsetup(struct stm32_priv_s *priv); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* A reference to a structure of this type must be passed to the MRF24J40 + * driver. This structure provides information about the configuration + * of the MRF24J40 and provides some board-specific hooks. + * + * Memory for this structure is provided by the caller. It is not copied + * by the driver and is presumed to persist while the driver is active. The + * memory must be writable because, under certain circumstances, the driver + * may modify frequency or X plate resistance values. + */ + +static struct stm32_priv_s g_mrf24j40_mb1_priv = +{ + .dev.attach = stm32_attach_irq, + .dev.enable = stm32_enable_irq, + .handler = NULL, + .arg = NULL, + .intcfg = GPIO_MRF24J40_INT, + .spidev = 1, +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/* IRQ/GPIO access callbacks. These operations all hidden behind + * callbacks to isolate the MRF24J40 driver from differences in GPIO + * interrupt handling by varying boards and MCUs. If possible, + * interrupts should be configured on both rising and falling edges + * so that contact and loss-of-contact events can be detected. + * + * irq_attach - Attach the MRF24J40 interrupt handler to the GPIO + * interrupt + * irq_enable - Enable or disable the GPIO interrupt + */ + +static int stm32_attach_irq(const struct mrf24j40_lower_s *lower, + xcpt_t handler, void *arg) +{ + struct stm32_priv_s *priv = (struct stm32_priv_s *)lower; + + DEBUGASSERT(priv != NULL); + + /* Just save the handler for use when the interrupt is enabled */ + + priv->handler = handler; + priv->arg = arg; + return OK; +} + +static void stm32_enable_irq(const struct mrf24j40_lower_s *lower, + bool state) +{ + struct stm32_priv_s *priv = (struct stm32_priv_s *)lower; + + /* The caller should not attempt to enable interrupts if the handler + * has not yet been 'attached' + */ + + DEBUGASSERT(priv != NULL && (priv->handler != NULL || !state)); + + wlinfo("state:%d\n", (int)state); + + /* Attach and enable, or detach and disable */ + + if (state) + { + stm32_gpiosetevent(priv->intcfg, false, true, true, + priv->handler, priv->arg); + } + else + { + stm32_gpiosetevent(priv->intcfg, false, false, false, + NULL, NULL); + } +} + +/**************************************************************************** + * Name: stm32_mrf24j40_devsetup + * + * Description: + * Initialize one the MRF24J40 device in one mikroBUS slot + * + * Returned Value: + * Zero is returned on success. Otherwise, a negated errno value is + * returned to indicate the nature of the failure. + * + ****************************************************************************/ + +static int stm32_mrf24j40_devsetup(struct stm32_priv_s *priv) +{ + struct ieee802154_radio_s *radio; + MACHANDLE mac; + struct spi_dev_s *spi; + int ret; + + /* Configure the interrupt pin */ + + stm32_configgpio(priv->intcfg); + + /* Initialize the SPI bus and get an instance of the SPI interface */ + + spi = stm32_spibus_initialize(priv->spidev); + if (spi == NULL) + { + wlerr("ERROR: Failed to initialize SPI bus %d\n", priv->spidev); + return -ENODEV; + } + + /* Initialize and register the SPI MRF24J40 device */ + + radio = mrf24j40_init(spi, &priv->dev); + if (radio == NULL) + { + wlerr("ERROR: Failed to initialize SPI bus %d\n", priv->spidev); + return -ENODEV; + } + + /* Create a 802.15.4 MAC device from a 802.15.4 compatible radio device. */ + + mac = mac802154_create(radio); + if (mac == NULL) + { + wlerr("ERROR: Failed to initialize IEEE802.15.4 MAC\n"); + return -ENODEV; + } + +#ifdef CONFIG_IEEE802154_NETDEV + /* Use the IEEE802.15.4 MAC interface instance to create a 6LoWPAN + * network interface by wrapping the MAC interface instance in a + * network device driver via mac802154dev_register(). + */ + + ret = mac802154netdev_register(mac); + if (ret < 0) + { + wlerr("ERROR: Failed to register the MAC network driver wpan%d: %d\n", + 0, ret); + return ret; + } +#endif + +#ifdef CONFIG_IEEE802154_MACDEV + /* If want to call these APIs from userspace, you have to wrap the MAC + * interface in a character device viamac802154dev_register(). + */ + + ret = mac802154dev_register(mac, 0); + if (ret < 0) + { + wlerr("ERROR: " + "Failed to register the MAC character driver /dev/ieee%d: %d\n", + 0, ret); + return ret; + } +#endif + + UNUSED(ret); + return OK; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_mrf24j40_initialize + * + * Description: + * Initialize the MRF24J40 device. + * + * Returned Value: + * Zero is returned on success. Otherwise, a negated errno value is + * returned to indicate the nature of the failure. + * + ****************************************************************************/ + +int stm32_mrf24j40_initialize(void) +{ + int ret; + + wlinfo("Configuring MRF24J40\n"); + + ret = stm32_mrf24j40_devsetup(&g_mrf24j40_mb1_priv); + if (ret < 0) + { + wlerr("ERROR: Failed to initialize BD in mikroBUS1: %d\n", ret); + } + + UNUSED(ret); + return OK; +} +#endif /* CONFIG_IEEE802154_MRF24J40 */ diff --git a/boards/arm/stm32f4/olimex-stm32-e407/src/stm32_spi.c b/boards/arm/stm32f4/olimex-stm32-e407/src/stm32_spi.c new file mode 100644 index 0000000000000..c188a6abe7e3d --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-e407/src/stm32_spi.c @@ -0,0 +1,303 @@ +/**************************************************************************** + * boards/arm/stm32f4/olimex-stm32-e407/src/stm32_spi.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "arm_internal.h" +#include "chip.h" +#include "stm32.h" +#include "olimex-stm32-e407.h" + +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_spidev_initialize + * + * Description: + * Called to configure SPI chip select GPIO pins for the Olimex-STM32-E407 + * board. + * + ****************************************************************************/ + +void stm32_spidev_initialize(void) +{ + /* NOTE: Clocking for SPI1 and/or SPI2 was already provided in stm32_rcc.c. + * Configurations of SPI pins is performed in stm32_spi.c. + * Here, we only initialize chip select pins unique to the board + * architecture. + */ + +#ifdef CONFIG_MTD_W25 + stm32_configgpio(FLASH_SPI1_CS); /* FLASH chip select */ +#endif + +#ifdef CONFIG_CAN_MCP2515 + stm32_configgpio(GPIO_MCP2515_CS); /* MCP2515 chip select */ +#endif + +#ifdef CONFIG_CL_MFRC522 + stm32_configgpio(GPIO_CS_MFRC522); /* MFRC522 chip select */ +#endif + +#if defined(CONFIG_SENSORS_MAX6675) + stm32_configgpio(GPIO_MAX6675_CS); /* MAX6675 chip select */ +#endif + +#ifdef CONFIG_LCD_MAX7219 + stm32_configgpio(STM32_LCD_CS); /* MAX7219 chip select */ +#endif + +#ifdef CONFIG_LCD_ST7567 + stm32_configgpio(STM32_LCD_CS); /* ST7567 chip select */ +#endif + +#ifdef CONFIG_LCD_PCD8544 + stm32_configgpio(STM32_LCD_CS); /* ST7567 chip select */ +#endif + +#ifdef CONFIG_WL_NRF24L01 + stm32_configgpio(GPIO_NRF24L01_CS); /* nRF24L01 chip select */ +#endif + +#ifdef CONFIG_MMCSD_SPI + stm32_configgpio(GPIO_SDCARD_CS); /* SD/MMC Card chip select */ +#endif + +#ifdef CONFIG_IEEE802154_MRF24J40 + stm32_configgpio(GPIO_MRF24J40_CS); /* MRF24J40 chip select */ +#endif +} + +/**************************************************************************** + * Name: stm32_spi1/2select and stm32_spi1/2status + * + * Description: + * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status + * must be provided by board-specific logic. They are implementations of + * the select and status methods of the SPI interface defined by struct + * spi_ops_s (see include/nuttx/spi/spi.h). All other methods (including + * stm32_spibus_initialize()) are provided by common STM32 logic. To use + * this common SPI logic on your board: + * + * 1. Provide logic in stm32_boardinitialize() to configure SPI chip select + * pins. + * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() functions + * in your board-specific logic. These functions will perform chip + * selection and status operations using GPIOs in the way your board is + * configured. + * 3. Add a calls to stm32_spibus_initialize() in your low level + * application initialization logic + * 4. The handle returned by stm32_spibus_initialize() may then be used to + * bind the SPI driver to higher level logic (e.g., calling + * mmcsd_spislotinitialize(), for example, will bind the SPI driver to + * the SPI MMC/SD driver). + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_SPI1 +void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, + bool selected) +{ +#if defined(CONFIG_CAN_MCP2515) + if (devid == SPIDEV_CANBUS(0)) + { + stm32_gpiowrite(GPIO_MCP2515_CS, !selected); + } +#endif + +#if defined(CONFIG_CL_MFRC522) + if (devid == SPIDEV_CONTACTLESS(0)) + { + stm32_gpiowrite(GPIO_CS_MFRC522, !selected); + } +#endif + +#ifdef CONFIG_IEEE802154_MRF24J40 + if (devid == SPIDEV_IEEE802154(0)) + { + stm32_gpiowrite(GPIO_MRF24J40_CS, !selected); + } +#endif + +#if defined(CONFIG_IEEE802154_XBEE) + if (devid == SPIDEV_IEEE802154(0)) + { + stm32_gpiowrite(GPIO_XBEE_CS, !selected); + } +#endif + +#if defined(CONFIG_SENSORS_MAX6675) + if (devid == SPIDEV_TEMPERATURE(0)) + { + stm32_gpiowrite(GPIO_MAX6675_CS, !selected); + } +#endif + +#ifdef CONFIG_LCD_MAX7219 + if (devid == SPIDEV_DISPLAY(0)) + { + stm32_gpiowrite(STM32_LCD_CS, !selected); + } +#endif + +#ifdef CONFIG_LCD_PCD8544 + if (devid == SPIDEV_DISPLAY(0)) + { + stm32_gpiowrite(STM32_LCD_CS, !selected); + } +#endif + +#ifdef CONFIG_LCD_ST7567 + if (devid == SPIDEV_DISPLAY(0)) + { + stm32_gpiowrite(STM32_LCD_CS, !selected); + } +#endif + +#ifdef CONFIG_WL_NRF24L01 + if (devid == SPIDEV_WIRELESS(0)) + { + stm32_gpiowrite(GPIO_NRF24L01_CS, !selected); + } +#endif + +#ifdef CONFIG_MMCSD_SPI + if (devid == SPIDEV_MMCSD(0)) + { + stm32_gpiowrite(GPIO_SDCARD_CS, !selected); + } +#endif + +#ifdef CONFIG_MTD_W25 + stm32_gpiowrite(FLASH_SPI1_CS, !selected); +#endif +} + +uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) +{ + uint8_t status = 0; + +#ifdef CONFIG_WL_NRF24L01 + if (devid == SPIDEV_WIRELESS(0)) + { + status |= SPI_STATUS_PRESENT; + } +#endif + +#ifdef CONFIG_MMCSD_SPI + if (devid == SPIDEV_MMCSD(0)) + { + status |= SPI_STATUS_PRESENT; + } +#endif + + return status; +} +#endif + +#ifdef CONFIG_STM32_SPI2 +void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid, + bool selected) +{ +} + +uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} +#endif + +/**************************************************************************** + * Name: stm32_spi1cmddata + * + * Description: + * Set or clear the SH1101A A0 or SD1306 D/C n bit to select data (true) + * or command (false). This function must be provided by platform-specific + * logic. This is an implementation of the cmddata method of the SPI + * interface defined by struct spi_ops_s (see include/nuttx/spi/spi.h). + * + * Input Parameters: + * + * spi - SPI device that controls the bus the device that requires the CMD/ + * DATA selection. + * devid - If there are multiple devices on the bus, this selects which one + * to select cmd or data. NOTE: This design restricts, for example, + * one one SPI display per SPI bus. + * cmd - true: select command; false: select data + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_SPI_CMDDATA +#ifdef CONFIG_STM32_SPI1 +int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, + bool cmd) +{ +#ifdef CONFIG_LCD_ST7567 + if (devid == SPIDEV_DISPLAY(0)) + { + /* This is the Data/Command control pad which determines whether the + * data bits are data or a command. + */ + + stm32_gpiowrite(STM32_LCD_RS, !cmd); + + return OK; + } +#endif + +#ifdef CONFIG_LCD_PCD8544 + if (devid == SPIDEV_DISPLAY(0)) + { + /* This is the Data/Command control pad which determines whether the + * data bits are data or a command. + */ + + stm32_gpiowrite(STM32_LCD_CD, !cmd); + + return OK; + } +#endif + + return -ENODEV; +} +#endif +#endif + +#endif /* CONFIG_STM32_SPI1 || CONFIG_STM32_SPI2 */ diff --git a/boards/arm/stm32f4/olimex-stm32-e407/src/stm32_timer.c b/boards/arm/stm32f4/olimex-stm32-e407/src/stm32_timer.c new file mode 100644 index 0000000000000..8d696f1f725d8 --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-e407/src/stm32_timer.c @@ -0,0 +1,63 @@ +/**************************************************************************** + * boards/arm/stm32f4/olimex-stm32-e407/src/stm32_timer.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include + +#include "stm32_tim.h" +#include "olimex-stm32-e407.h" + +#ifdef CONFIG_TIMER + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_timer_driver_setup + * + * Description: + * Configure the timer driver. + * + * Input Parameters: + * devpath - The full path to the timer device. This should be of the + * form /dev/timer0 + * timer - The timer's number. + * + * Returned Values: + * Zero (OK) is returned on success; A negated errno value is returned + * to indicate the nature of any failure. + * + ****************************************************************************/ + +int stm32_timer_driver_setup(const char *devpath, int timer) +{ + return stm32_timer_initialize(devpath, timer); +} + +#endif diff --git a/boards/arm/stm32f4/olimex-stm32-e407/src/stm32_usb.c b/boards/arm/stm32f4/olimex-stm32-e407/src/stm32_usb.c new file mode 100644 index 0000000000000..29725ddce93ce --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-e407/src/stm32_usb.c @@ -0,0 +1,329 @@ +/**************************************************************************** + * boards/arm/stm32f4/olimex-stm32-e407/src/stm32_usb.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include "arm_internal.h" +#include "stm32.h" +#include "stm32_otgfs.h" +#include "olimex-stm32-e407.h" + +#ifdef CONFIG_STM32_OTGFS + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#if defined(CONFIG_USBDEV) || defined(CONFIG_USBHOST) +# define HAVE_USB 1 +#else +# warning "CONFIG_STM32_OTGFS is enabled but neither CONFIG_USBDEV nor CONFIG_USBHOST" +# undef HAVE_USB +#endif + +#ifndef CONFIG_STM32F4DISCO_USBHOST_PRIO +# define CONFIG_STM32F4DISCO_USBHOST_PRIO 100 +#endif + +#ifndef CONFIG_STM32F4DISCO_USBHOST_STACKSIZE +# define CONFIG_STM32F4DISCO_USBHOST_STACKSIZE 1024 +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +static struct usbhost_connection_s *g_usbconn; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: usbhost_waiter + * + * Description: + * Wait for USB devices to be connected. + * + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +static int usbhost_waiter(int argc, char *argv[]) +{ + struct usbhost_hubport_s *hport; + + uinfo("Running\n"); + for (; ; ) + { + /* Wait for the device to change state */ + + DEBUGVERIFY(CONN_WAIT(g_usbconn, &hport)); + uinfo("%s\n", hport->connected ? "connected" : "disconnected"); + + /* Did we just become connected? */ + + if (hport->connected) + { + /* Yes.. enumerate the newly connected device */ + + CONN_ENUMERATE(g_usbconn, hport); + } + } + + /* Keep the compiler from complaining */ + + return 0; +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_usbinitialize + * + * Description: + * Called from stm32_usbinitialize very early in initialization to setup + * USB-related GPIO pins for the STM32F4Discovery board. + * + ****************************************************************************/ + +void stm32_usbinitialize(void) +{ + /* The OTG FS has an internal soft pull-up. + * No GPIO configuration is required + */ + + /* Configure the OTG FS VBUS sensing GPIO, + * Power On, and Overcurrent GPIOs + */ + +#ifdef CONFIG_STM32_OTGFS + stm32_configgpio(GPIO_OTGFS_VBUS); + stm32_configgpio(GPIO_OTGFS_PWRON); + stm32_configgpio(GPIO_OTGFS_OVER); +#endif +} + +/**************************************************************************** + * Name: stm32_usbhost_initialize + * + * Description: + * Called at application startup time to initialize the USB host + * functionality. This function will start a thread that will monitor + * for device connection/disconnection events. + * + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +int stm32_usbhost_initialize(void) +{ + int ret; + + /* First, register all of the class drivers needed to support the drivers + * that we care about: + */ + + uvdbg("Register class drivers\n"); + +#ifdef CONFIG_USBHOST_HUB + /* Initialize USB hub class support */ + + ret = usbhost_hub_initialize(); + if (ret < 0) + { + uerr("ERROR: usbhost_hub_initialize failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_USBHOST_MSC + /* Register the USB mass storage class class */ + + ret = usbhost_msc_initialize(); + if (ret != OK) + { + uerr("ERROR: Failed to register the mass storage class: %d\n", ret); + } +#endif + +#ifdef CONFIG_USBHOST_CDCACM + /* Register the CDC/ACM serial class */ + + ret = usbhost_cdcacm_initialize(); + if (ret != OK) + { + uerr("ERROR: Failed to register the CDC/ACM serial class: %d\n", ret); + } +#endif + +#ifdef CONFIG_USBHOST_HIDKBD + /* Initialize the HID keyboard class */ + + ret = usbhost_kbdinit(); + if (ret != OK) + { + uerr("Failed to register the HID keyboard class\n"); + } +#endif + +#ifdef CONFIG_USBHOST_HIDMOUSE + /* Initialize the HID mouse class */ + + ret = usbhost_mouse_init(); + if (ret != OK) + { + uerr("Failed to register the HID mouse class\n"); + } +#endif + + /* Then get an instance of the USB host interface */ + + uinfo("Initialize USB host\n"); + g_usbconn = stm32_otgfshost_initialize(0); + if (g_usbconn) + { + /* Start a thread to handle device connection. */ + + uinfo("Start usbhost_waiter\n"); + + ret = kthread_create("usbhost", CONFIG_STM32F4DISCO_USBHOST_PRIO, + CONFIG_STM32F4DISCO_USBHOST_STACKSIZE, + usbhost_waiter, NULL); + return ret < 0 ? -ENOEXEC : OK; + } + + return -ENODEV; +} +#endif + +/**************************************************************************** + * Name: stm32_usbhost_vbusdrive + * + * Description: + * Enable/disable driving of VBUS 5V output. This function must be + * provided be each platform that implements the STM32 OTG FS host + * interface + * + * "On-chip 5 V VBUS generation is not supported. For this reason, a + * charge pump or, if 5 V are available on the application board, a + * basic power switch, must be added externally to drive the 5 V VBUS + * line. The external charge pump can be driven by any GPIO output. + * When the application decides to power on VBUS using the chosen GPIO, + * it must also set the port power bit in the host port control and + * status register (PPWR bit in OTG_FS_HPRT). + * + * "The application uses this field to control power to this port, andi + * the core clears this bit on an overcurrent condition." + * + * Input Parameters: + * iface - For future growth to handle multiple USB host interface. + * Should be zero. + * enable - true: enable VBUS power; false: disable VBUS power + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +void stm32_usbhost_vbusdrive(int iface, bool enable) +{ + DEBUGASSERT(iface == 0); + + if (enable) + { + /* Enable the Power Switch by driving the enable pin low */ + + stm32_gpiowrite(GPIO_OTGFS_PWRON, false); + } + else + { + /* Disable the Power Switch by driving the enable pin high */ + + stm32_gpiowrite(GPIO_OTGFS_PWRON, true); + } +} +#endif + +/**************************************************************************** + * Name: stm32_setup_overcurrent + * + * Description: + * Setup to receive an interrupt-level callback if an overcurrent + * condition is detected. + * + * Input Parameters: + * handler - New overcurrent interrupt handler + * arg - The argument provided for the interrupt handler + * + * Returned Value: + * Zero (OK) is returned on success. Otherwise, a negated errno value is + * returned to indicate the nature of the failure. + * + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +int stm32_setup_overcurrent(xcpt_t handler, void *arg) +{ + return stm32_gpiosetevent(GPIO_OTGFS_OVER, true, true, true, handler, arg); +} +#endif + +/**************************************************************************** + * Name: stm32_usbsuspend + * + * Description: + * Board logic must provide the stm32_usbsuspend logic if the USBDEV + * driver is used. This function is called whenever the USB enters or + * leaves suspend mode. This is an opportunity for the board logic to + * shutdown clocks, power, etc. while the USB is suspended. + * + ****************************************************************************/ + +#ifdef CONFIG_USBDEV +void stm32_usbsuspend(struct usbdev_s *dev, bool resume) +{ + uinfo("resume: %d\n", resume); +} +#endif + +#endif /* CONFIG_STM32_OTGFS */ diff --git a/boards/arm/stm32f4/olimex-stm32-e407/src/stm32_userleds.c b/boards/arm/stm32f4/olimex-stm32-e407/src/stm32_userleds.c new file mode 100644 index 0000000000000..b45090679214f --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-e407/src/stm32_userleds.c @@ -0,0 +1,95 @@ +/**************************************************************************** + * boards/arm/stm32f4/olimex-stm32-e407/src/stm32_userleds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32.h" +#include "olimex-stm32-e407.h" + +#ifndef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* This array maps an LED number to GPIO pin configuration */ + +static uint32_t g_ledcfg[BOARD_NLEDS] = +{ + GPIO_LED_STATUS +}; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_userled_initialize + ****************************************************************************/ + +uint32_t board_userled_initialize(void) +{ + /* Configure LED1-4 GPIOs for output */ + + stm32_configgpio(GPIO_LED_STATUS); + return BOARD_NLEDS; +} + +/**************************************************************************** + * Name: board_userled + ****************************************************************************/ + +void board_userled(int led, bool ledon) +{ + if ((unsigned)led < BOARD_NLEDS) + { + stm32_gpiowrite(g_ledcfg[led], ledon); + } +} + +/**************************************************************************** + * Name: board_userled_all + ****************************************************************************/ + +void board_userled_all(uint32_t ledset) +{ + stm32_gpiowrite(GPIO_LED_STATUS, (ledset & BOARD_LED1_BIT) != 0); +} + +#endif /* !CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32f4/olimex-stm32-h405/CMakeLists.txt b/boards/arm/stm32f4/olimex-stm32-h405/CMakeLists.txt new file mode 100644 index 0000000000000..8f277b475ed80 --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-h405/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32f4/olimex-stm32-h405/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/arm/stm32/olimex-stm32-h405/Kconfig b/boards/arm/stm32f4/olimex-stm32-h405/Kconfig similarity index 100% rename from boards/arm/stm32/olimex-stm32-h405/Kconfig rename to boards/arm/stm32f4/olimex-stm32-h405/Kconfig diff --git a/boards/arm/stm32f4/olimex-stm32-h405/configs/usbnsh/defconfig b/boards/arm/stm32f4/olimex-stm32-h405/configs/usbnsh/defconfig new file mode 100644 index 0000000000000..04484f5b989c8 --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-h405/configs/usbnsh/defconfig @@ -0,0 +1,68 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_DEV_CONSOLE is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +CONFIG_ADC=y +CONFIG_ANALOG=y +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="olimex-stm32-h405" +CONFIG_ARCH_BOARD_OLIMEX_STM32H405=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F405RG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_IRQBUTTONS=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_ARM_TOOLCHAIN_BUILDROOT=y +CONFIG_BOARDCTL_USBDEVCTRL=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_CDCACM=y +CONFIG_CDCACM_CONSOLE=y +CONFIG_CDCACM_RXBUFSIZE=256 +CONFIG_CDCACM_TXBUFSIZE=256 +CONFIG_DEBUG_SYMBOLS=y +CONFIG_EXAMPLES_ADC=y +CONFIG_EXAMPLES_CAN=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_MM_REGIONS=2 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_DISABLE_GET=y +CONFIG_NSH_DISABLE_PUT=y +CONFIG_NSH_DISABLE_WGET=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=192 +CONFIG_SCHED_WAITPID=y +CONFIG_START_YEAR=2013 +CONFIG_STM32_ADC1=y +CONFIG_STM32_CAN1=y +CONFIG_STM32_CAN_TSEG2=8 +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PWR=y +CONFIG_STM32_TIM1=y +CONFIG_STM32_TIM1_ADC=y +CONFIG_STM32_USART3=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USBDEV=y diff --git a/boards/arm/stm32f4/olimex-stm32-h405/include/board.h b/boards/arm/stm32f4/olimex-stm32-h405/include/board.h new file mode 100644 index 0000000000000..139fac64fa5c8 --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-h405/include/board.h @@ -0,0 +1,187 @@ +/**************************************************************************** + * boards/arm/stm32f4/olimex-stm32-h405/include/board.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_STM32_OLIMEX_STM32_H405_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32_OLIMEX_STM32_H405_INCLUDE_BOARD_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#ifndef __ASSEMBLY__ +# include +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Clocking *****************************************************************/ + +/* HSI - 16 MHz RC factory-trimmed + * LSI - 32 KHz RC (30-60KHz, uncalibrated) + * HSE - On-board crystal frequency is 8MHz + * LSE - 32.768 kHz + */ + +#define STM32_BOARD_XTAL 8000000ul + +#define STM32_HSI_FREQUENCY 16000000ul +#define STM32_LSI_FREQUENCY 32000 +#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL +#define STM32_LSE_FREQUENCY 32768 + +/* Main PLL Configuration. + * + * PLL source is HSE + * PLL_VCO = (STM32_HSE_FREQUENCY / PLLM) * PLLN + * = (25,000,000 / 12) * 360 + * = 240,000,000 + * SYSCLK = PLL_VCO / PLLP + * = 240,000,000 / 2 = 120,000,000 + * USB OTG FS, SDIO and RNG Clock + * = PLL_VCO / PLLQ + * = 240,000,000 / 5 = 48,000,000 + * = 48,000,000 + */ + +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(12) +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(360) +#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_2 +#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(5) + +#define STM32_SYSCLK_FREQUENCY 120000000ul + +/* AHB clock (HCLK) is SYSCLK (120MHz) */ + +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY + +/* APB1 clock (PCLK1) is HCLK/4 (30MHz) */ + +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd4 /* PCLK1 = HCLK / 4 */ +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/4) + +/* Timers driven from APB1 will be twice PCLK1 (60Mhz) */ + +#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) + +/* APB2 clock (PCLK2) is HCLK/2 (60MHz) */ + +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLKd2 /* PCLK2 = HCLK / 2 */ +#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/2) + +/* Timers driven from APB2 will be twice PCLK2 (120Mhz) */ + +#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM9_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM10_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM11_CLKIN (2*STM32_PCLK2_FREQUENCY) + +/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx + * otherwise frequency is 2xAPBx. + * Note: TIM1,8 are on APB2, others on APB1 + */ + +#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM2_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM3_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM4_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM5_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM6_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM7_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY + +/* LED definitions **********************************************************/ + +/* If CONFIG_ARCH_LEDS is not defined, then the user can control the status + * LED in any way. + * The following definitions are used to access individual LEDs. + */ + +/* LED index values for use with board_userled() */ + +#define BOARD_LED_STATUS 0 +#define BOARD_NLEDS 1 + +/* LED bits for use with board_userled_all() */ + +#define BOARD_LED_STATUS_BIT (1 << BOARD_LED1) + +/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the status LED of + * the Olimex STM32-H405. + * The following definitions describe how NuttX controls the LEDs: + */ + +#define LED_STARTED 0 /* LED_STATUS on */ +#define LED_HEAPALLOCATE 1 /* no change */ +#define LED_IRQSENABLED 2 /* no change */ +#define LED_STACKCREATED 3 /* no change */ +#define LED_INIRQ 4 /* no change */ +#define LED_SIGNAL 5 /* no change */ +#define LED_ASSERTION 6 /* LED_STATUS off */ +#define LED_PANIC 7 /* LED_STATUS blinking */ + +/* Button definitions *******************************************************/ + +/* The Olimex STM32-H405 supports one buttons: */ + +#define BUTTON_BUT 0 +#define NUM_BUTTONS 1 + +#define BUTTON_BUT_BIT (1 << BUTTON_BUT) + +/* Alternate function pin selections ****************************************/ + +/* USART3: */ + +#define GPIO_USART3_RX (GPIO_USART3_RX_1|GPIO_SPEED_100MHz) /* PB11 */ +#define GPIO_USART3_TX (GPIO_USART3_TX_1|GPIO_SPEED_100MHz) /* PB10 */ +#define GPIO_USART3_CTS GPIO_USART3_CTS_1 /* PB13 */ +#define GPIO_USART3_RTS GPIO_USART3_RTS_1 /* PB14 */ + +/* CAN: */ + +#define GPIO_CAN1_RX (GPIO_CAN1_RX_2|GPIO_SPEED_50MHz) /* PB8 */ +#define GPIO_CAN1_TX (GPIO_CAN1_TX_2|GPIO_SPEED_50MHz) /* PB9 */ +#define GPIO_CAN2_RX (GPIO_CAN1_RX_2|GPIO_SPEED_50MHz) /* PB5 */ +#define GPIO_CAN2_TX (GPIO_CAN1_TX_2|GPIO_SPEED_50MHz) /* PB6 */ + +/* USB OTG FS */ + +#define GPIO_OTGFS_DM (GPIO_OTGFS_DM_0|GPIO_SPEED_100MHz) +#define GPIO_OTGFS_DP (GPIO_OTGFS_DP_0|GPIO_SPEED_100MHz) +#define GPIO_OTGFS_ID (GPIO_OTGFS_ID_0|GPIO_SPEED_100MHz) +#define GPIO_OTGFS_SOF (GPIO_OTGFS_SOF_0|GPIO_SPEED_100MHz) + +#endif /* __BOARDS_ARM_STM32_OLIMEX_STM32_H405_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32f4/olimex-stm32-h405/scripts/Make.defs b/boards/arm/stm32f4/olimex-stm32-h405/scripts/Make.defs new file mode 100644 index 0000000000000..f9d445c42f7d8 --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-h405/scripts/Make.defs @@ -0,0 +1,41 @@ +############################################################################ +# boards/arm/stm32f4/olimex-stm32-h405/scripts/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/.config +include $(TOPDIR)/tools/Config.mk +include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs + +LDSCRIPT = ld.script +ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) + +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-gotoff.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32f4/olimex-stm32-h405/scripts/ld.script b/boards/arm/stm32f4/olimex-stm32-h405/scripts/ld.script new file mode 100644 index 0000000000000..3bf301337f5b9 --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-h405/scripts/ld.script @@ -0,0 +1,126 @@ +/**************************************************************************** + * boards/arm/stm32f4/olimex-stm32-h405/scripts/ld.script + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* The STM32F405RGT6 has 1024Kb of FLASH beginning at address 0x0800:0000 and + * 192Kb of SRAM. SRAM is split up into two blocks: + * + * 1) 112Kb of SRAM beginning at address 0x2000:0000 + * 2) 16Kb of SRAM beginning at address 0x2001:c000 + * 3) 64Kb of SRAM beginning at address 0x2002:0000 + * + * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 + * where the code expects to begin execution by jumping to the entry point in + * the 0x0800:0000 address + * range. + */ + +MEMORY +{ + flash (rx) : ORIGIN = 0x08000000, LENGTH = 1024K + sram (rwx) : ORIGIN = 0x20000000, LENGTH = 112K +} + +OUTPUT_ARCH(arm) +EXTERN(_vectors) +ENTRY(_stext) +SECTIONS +{ + .text : { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > flash + + .init_section : ALIGN(4) { + _sinit = ABSOLUTE(.); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) + _einit = ABSOLUTE(.); + } > flash + + .ARM.extab : ALIGN(4) { + *(.ARM.extab*) + } > flash + + .ARM.exidx : ALIGN(4) { + __exidx_start = ABSOLUTE(.); + *(.ARM.exidx*) + __exidx_end = ABSOLUTE(.); + } > flash + + .tdata : { + _stdata = ABSOLUTE(.); + *(.tdata .tdata.* .gnu.linkonce.td.*); + _etdata = ABSOLUTE(.); + } > flash + + .tbss : { + _stbss = ABSOLUTE(.); + *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); + _etbss = ABSOLUTE(.); + } > flash + + _eronly = ABSOLUTE(.); + + .data : ALIGN(4) { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > sram AT > flash + + .bss : ALIGN(4) { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + _ebss = ABSOLUTE(.); + } > sram + + /* Stabs debugging sections. */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/stm32f4/olimex-stm32-h405/src/CMakeLists.txt b/boards/arm/stm32f4/olimex-stm32-h405/src/CMakeLists.txt new file mode 100644 index 0000000000000..5c6283a1d120b --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-h405/src/CMakeLists.txt @@ -0,0 +1,49 @@ +# ############################################################################## +# boards/arm/stm32f4/olimex-stm32-h405/src/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(SRCS stm32_boot.c) + +if(CONFIG_ARCH_LEDS) + list(APPEND SRCS stm32_autoleds.c) +else() + list(APPEND SRCS stm32_userleds.c) +endif() + +if(CONFIG_ARCH_BUTTONS) + list(APPEND SRCS stm32_buttons.c) +endif() + +if(CONFIG_STM32_OTGFS) + list(APPEND SRCS stm32_usb.c) +endif() + +if(CONFIG_ADC) + list(APPEND SRCS stm32_adc.c) +endif() + +if(CONFIG_STM32_CAN_CHARDRIVER) + list(APPEND SRCS stm32_can.c) +endif() + +target_sources(board PRIVATE ${SRCS}) + +set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/ld.script") diff --git a/boards/arm/stm32f4/olimex-stm32-h405/src/Make.defs b/boards/arm/stm32f4/olimex-stm32-h405/src/Make.defs new file mode 100644 index 0000000000000..edf6087d9fd98 --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-h405/src/Make.defs @@ -0,0 +1,51 @@ +############################################################################ +# boards/arm/stm32f4/olimex-stm32-h405/src/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +CSRCS = stm32_boot.c + +ifeq ($(CONFIG_ARCH_LEDS),y) +CSRCS += stm32_autoleds.c +else +CSRCS += stm32_userleds.c +endif + +ifeq ($(CONFIG_ARCH_BUTTONS),y) +CSRCS += stm32_buttons.c +endif + +ifeq ($(CONFIG_STM32_OTGFS),y) +CSRCS += stm32_usb.c +endif + +ifeq ($(CONFIG_ADC),y) +CSRCS += stm32_adc.c +endif + +ifeq ($(CONFIG_STM32_CAN_CHARDRIVER),y) +CSRCS += stm32_can.c +endif + +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/olimex-stm32-h405/src/olimex-stm32-h405.h b/boards/arm/stm32f4/olimex-stm32-h405/src/olimex-stm32-h405.h similarity index 98% rename from boards/arm/stm32/olimex-stm32-h405/src/olimex-stm32-h405.h rename to boards/arm/stm32f4/olimex-stm32-h405/src/olimex-stm32-h405.h index 06359cc80bd93..610c2384d5cd5 100644 --- a/boards/arm/stm32/olimex-stm32-h405/src/olimex-stm32-h405.h +++ b/boards/arm/stm32f4/olimex-stm32-h405/src/olimex-stm32-h405.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/olimex-stm32-h405/src/olimex-stm32-h405.h + * boards/arm/stm32f4/olimex-stm32-h405/src/olimex-stm32-h405.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f4/olimex-stm32-h405/src/stm32_adc.c b/boards/arm/stm32f4/olimex-stm32-h405/src/stm32_adc.c new file mode 100644 index 0000000000000..6415a54736bc5 --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-h405/src/stm32_adc.c @@ -0,0 +1,170 @@ +/**************************************************************************** + * boards/arm/stm32f4/olimex-stm32-h405/src/stm32_adc.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include +#include + +#include "chip.h" +#include "stm32_adc.h" +#include "olimex-stm32-h405.h" + +#ifdef CONFIG_ADC + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* Up to 3 ADC interfaces are supported */ + +#if STM32_NADC < 3 +# undef CONFIG_STM32_ADC3 +#endif + +#if STM32_NADC < 2 +# undef CONFIG_STM32_ADC2 +#endif + +#if STM32_NADC < 1 +# undef CONFIG_STM32_ADC1 +#endif + +#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) || defined(CONFIG_STM32_ADC3) +#ifndef CONFIG_STM32_ADC1 +# warning "Channel information only available for ADC1" +#endif + +/* The number of ADC channels in the conversion list */ + +#define ADC1_NCHANNELS 1//14 + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* The Olimex STM32-P405 has a 10 Kohm potentiometer AN_TR connected to PC0 + * ADC123_IN10 + */ + +/* Identifying number of each ADC channel: Variable Resistor. */ + +#ifdef CONFIG_STM32_ADC1 +static const uint8_t g_chanlist[ADC1_NCHANNELS] = +{ + 1 +}; +/* , 2, 3, + * 4, 5, 6, + * 7, 8, 9, + * 10, 11, 12, + * 13, 15 + * }; + */ + +/* Configurations of pins used byte each ADC channels */ + +static const uint32_t g_pinlist[ADC1_NCHANNELS] = +{ + GPIO_ADC1_IN1_0 +}; +/* , GPIO_ADC1_IN2_0, GPIO_ADC1_IN3_0, + * GPIO_ADC1_IN4_0, GPIO_ADC1_IN5_0, GPIO_ADC1_IN6_0, + * GPIO_ADC1_IN7_0, GPIO_ADC1_IN8_0, GPIO_ADC1_IN9_0, + * GPIO_ADC1_IN10_0, GPIO_ADC1_IN11_0, GPIO_ADC1_IN12_0, + * GPIO_ADC1_IN13_0, GPIO_ADC1_IN15_0 + * }; + */ +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_adc_setup + * + * Description: + * Initialize ADC and register the ADC driver. + * + ****************************************************************************/ + +int stm32_adc_setup(void) +{ +#ifdef CONFIG_STM32_ADC1 + static bool initialized = false; + struct adc_dev_s *adc; + int ret; + int i; + + /* Check if we have already initialized */ + + if (!initialized) + { + /* Configure the pins as analog inputs for the selected channels */ + + for (i = 0; i < ADC1_NCHANNELS; i++) + { + stm32_configgpio(g_pinlist[i]); + } + + /* Call stm32_adcinitialize() to get an instance of the ADC interface */ + + adc = stm32_adcinitialize(1, g_chanlist, ADC1_NCHANNELS); + if (adc == NULL) + { + aerr("ERROR: Failed to get ADC interface\n"); + return -ENODEV; + } + + /* Register the ADC driver at "/dev/adc0" */ + + ret = adc_register("/dev/adc0", adc); + if (ret < 0) + { + aerr("ERROR: adc_register failed: %d\n", ret); + return ret; + } + + /* Now we are initialized */ + + initialized = true; + } + + return OK; +#else + return -ENOSYS; +#endif +} + +#endif /* CONFIG_STM32_ADC1 || CONFIG_STM32_ADC2 || CONFIG_STM32_ADC3 */ +#endif /* CONFIG_ADC */ diff --git a/boards/arm/stm32f4/olimex-stm32-h405/src/stm32_autoleds.c b/boards/arm/stm32f4/olimex-stm32-h405/src/stm32_autoleds.c new file mode 100644 index 0000000000000..2c131bdac98c6 --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-h405/src/stm32_autoleds.c @@ -0,0 +1,90 @@ +/**************************************************************************** + * boards/arm/stm32f4/olimex-stm32-h405/src/stm32_autoleds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "stm32.h" +#include "olimex-stm32-h405.h" + +#ifdef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_autoled_initialize + ****************************************************************************/ + +void board_autoled_initialize(void) +{ + /* Configure LED_STATUS GPIO for output */ + + stm32_configgpio(GPIO_LED_STATUS); +} + +/**************************************************************************** + * Name: board_autoled_on + ****************************************************************************/ + +void board_autoled_on(int led) +{ + if (led == LED_STARTED) + { + stm32_gpiowrite(GPIO_LED_STATUS, true); + } + + if (led == LED_ASSERTION || led == LED_PANIC) + { + stm32_gpiowrite(GPIO_LED_STATUS, false); + } +} + +/**************************************************************************** + * Name: board_autoled_off + ****************************************************************************/ + +void board_autoled_off(int led) +{ + if (led == LED_STARTED) + { + stm32_gpiowrite(GPIO_LED_STATUS, false); + } + + if (led == LED_ASSERTION || led == LED_PANIC) + { + stm32_gpiowrite(GPIO_LED_STATUS, true); + } +} + +#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32f4/olimex-stm32-h405/src/stm32_boot.c b/boards/arm/stm32f4/olimex-stm32-h405/src/stm32_boot.c new file mode 100644 index 0000000000000..c030d22076a64 --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-h405/src/stm32_boot.c @@ -0,0 +1,142 @@ +/**************************************************************************** + * boards/arm/stm32f4/olimex-stm32-h405/src/stm32_boot.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include +#include +#include +#include + +#include +#include +#include + +#ifdef CONFIG_USBMONITOR +# include +#endif + +#ifdef CONFIG_STM32_OTGFS +# include "stm32_usbhost.h" +#endif + +#include "stm32.h" +#include "olimex-stm32-h405.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#if !defined(CONFIG_STM32_CAN1) && !defined(CONFIG_STM32_CAN2) +# undef CONFIG_CAN +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_boardinitialize + * + * Description: + * All STM32 architectures must provide the following entry point. + * This entry point is called early in the initialization -- after all + * memory has been configured and mapped but before any devices have been + * initialized. + * + ****************************************************************************/ + +void stm32_boardinitialize(void) +{ + /* Initialize USB if the 1) OTG FS controller is in the configuration and + * 2) disabled, and 3) the weak function stm32_usbinitialize() has been + * brought into the build. Presumably either CONFIG_USBDEV is also + * selected. + */ + +#ifdef CONFIG_STM32_OTGFS + if (stm32_usbinitialize) + { + stm32_usbinitialize(); + } +#endif + + /* Configure on-board LEDs if LED support has been selected. */ + +#ifdef CONFIG_ARCH_LEDS + board_autoled_initialize(); +#endif + + /* Configure on-board BUTTONs if BUTTON support has been selected. */ + +#ifdef CONFIG_ARCH_BUTTONS + board_button_initialize(); +#endif +} + +/**************************************************************************** + * Name: board_late_initialize + * + * Description: + * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_late_initialize(). board_late_initialize() will be + * called immediately after up_intitialize() is called and just before the + * initial application is started. This additional initialization phase + * may be used, for example, to initialize board-specific device drivers. + * + ****************************************************************************/ + +#ifdef CONFIG_BOARD_LATE_INITIALIZE +void board_late_initialize(void) +{ + int ret; + +#ifdef CONFIG_ADC + /* Initialize ADC and register the ADC driver. */ + + ret = stm32_adc_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_adc_setup failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_STM32_CAN_CHARDRIVER + /* Initialize CAN and register the CAN driver. */ + + ret = stm32_can_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_can_setup failed: %d\n", ret); + } +#endif + + UNUSED(ret); +} +#endif diff --git a/boards/arm/stm32f4/olimex-stm32-h405/src/stm32_buttons.c b/boards/arm/stm32f4/olimex-stm32-h405/src/stm32_buttons.c new file mode 100644 index 0000000000000..8f180773eb7a6 --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-h405/src/stm32_buttons.c @@ -0,0 +1,140 @@ +/**************************************************************************** + * boards/arm/stm32f4/olimex-stm32-h405/src/stm32_buttons.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include +#include + +#include "olimex-stm32-h405.h" + +#ifdef CONFIG_ARCH_BUTTONS + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* Pin configuration for each Olimex-STM32-H405 button. This array is indexed + * by the BUTTON_* definitions in board.h + */ + +static const uint32_t g_buttons[NUM_BUTTONS] = +{ + GPIO_BTN_BUT +}; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_button_initialize + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. + * + ****************************************************************************/ + +uint32_t board_button_initialize(void) +{ + int i; + + /* Configure the GPIO pins as inputs. NOTE that EXTI interrupts are + * configured for all pins. + */ + + for (i = 0; i < NUM_BUTTONS; i++) + { + stm32_configgpio(g_buttons[i]); + } + + return NUM_BUTTONS; +} + +/**************************************************************************** + * Name: board_buttons + ****************************************************************************/ + +uint32_t board_buttons(void) +{ + uint32_t ret = 0; + + /* Check that state of each key */ + + if (!stm32_gpioread(g_buttons[BUTTON_BUT])) + { + ret |= BUTTON_BUT_BIT; + } + + return ret; +} + +/**************************************************************************** + * Button support. + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. + * + * After board_button_initialize() has been called, board_buttons() may be + * called to collect the state of all buttons. board_buttons() returns an + * 32-bit bit set with each bit associated with a button. See the + * BUTTON_*_BIT definitions in board.h for the meaning of each bit. + * + * board_button_irq() may be called to register an interrupt handler that + * will be called when a button is depressed or released. The ID value is a + * button enumeration value that uniquely identifies a button resource. See + * the BUTTON_* definitions in board.h for the meaning of enumeration + * value. + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_IRQBUTTONS +int board_button_irq(int id, xcpt_t irqhandler, void *arg) +{ + int ret = -EINVAL; + + /* The following should be atomic */ + + if (id >= MIN_IRQBUTTON && id <= MAX_IRQBUTTON) + { + ret = stm32_gpiosetevent(g_buttons[id], true, true, true, + irqhandler, arg); + } + + return ret; +} +#endif +#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/stm32f4/olimex-stm32-h405/src/stm32_can.c b/boards/arm/stm32f4/olimex-stm32-h405/src/stm32_can.c new file mode 100644 index 0000000000000..44529b9f1ef12 --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-h405/src/stm32_can.c @@ -0,0 +1,101 @@ +/**************************************************************************** + * boards/arm/stm32f4/olimex-stm32-h405/src/stm32_can.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include + +#include + +#include "stm32.h" +#include "stm32_can.h" +#include "olimex-stm32-h405.h" + +#ifdef CONFIG_CAN + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +#if defined(CONFIG_STM32_CAN1) && defined(CONFIG_STM32_CAN2) +# warning "Both CAN1 and CAN2 are enabled. Only CAN1 is used." +# undef CONFIG_STM32_CAN2 +#endif + +#ifdef CONFIG_STM32_CAN1 +# define CAN_PORT 1 +#else +# define CAN_PORT 2 +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_can_setup + * + * Description: + * Initialize CAN and register the CAN device + * + ****************************************************************************/ + +int stm32_can_setup(void) +{ +#if defined(CONFIG_STM32_CAN1) || defined(CONFIG_STM32_CAN2) + struct can_dev_s *can; + int ret; + + /* Call stm32_caninitialize() to get an instance of the CAN interface */ + + can = stm32_caninitialize(CAN_PORT); + if (can == NULL) + { + canerr("ERROR: Failed to get CAN interface\n"); + return -ENODEV; + } + + /* Register the CAN driver at "/dev/can0" */ + + ret = can_register("/dev/can0", can); + if (ret < 0) + { + canerr("ERROR: can_register failed: %d\n", ret); + return ret; + } + + return OK; +#else + return -ENODEV; +#endif +} + +#endif /* CONFIG_CAN */ diff --git a/boards/arm/stm32f4/olimex-stm32-h405/src/stm32_usb.c b/boards/arm/stm32f4/olimex-stm32-h405/src/stm32_usb.c new file mode 100644 index 0000000000000..c64185910443d --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-h405/src/stm32_usb.c @@ -0,0 +1,108 @@ +/**************************************************************************** + * boards/arm/stm32f4/olimex-stm32-h405/src/stm32_usb.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include + +#include +#include +#include +#include "stm32.h" +#include "stm32_otgfs.h" +#include "olimex-stm32-h405.h" + +#ifdef CONFIG_STM32_OTGFS + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#if defined(CONFIG_USBDEV) +# define HAVE_USB 1 +#else +# warning "CONFIG_STM32_OTGFS is enabled but not CONFIG_USBDEV" +# undef HAVE_USB +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_usbinitialize + * + * Description: + * Called from stm32_usbinitialize very early in initialization to setup + * USB-related GPIO pins for the STM32F4Discovery board. + * + ****************************************************************************/ + +void stm32_usbinitialize(void) +{ + /* The OTG FS has an internal soft pull-up. + * No GPIO configuration is required + */ + + /* Configure the OTG FS VBUS sensing GPIO */ + +#ifdef CONFIG_STM32_OTGFS + stm32_configgpio(GPIO_OTGFS_VBUS); +#endif +} + +/**************************************************************************** + * Name: stm32_usbsuspend + * + * Description: + * Board logic must provide the stm32_usbsuspend logic if the USBDEV + * driver is used. This function is called whenever the USB enters or + * leaves suspend mode. + * This is an opportunity for the board logic to shutdown clocks, power, + * etc. while the USB is suspended. + * + ****************************************************************************/ + +#ifdef CONFIG_USBDEV +void stm32_usbsuspend(struct usbdev_s *dev, bool resume) +{ + uinfo("resume: %d\n", resume); +} +#endif + +#endif /* CONFIG_STM32_OTGFS */ diff --git a/boards/arm/stm32f4/olimex-stm32-h405/src/stm32_userleds.c b/boards/arm/stm32f4/olimex-stm32-h405/src/stm32_userleds.c new file mode 100644 index 0000000000000..1662368f1a3c7 --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-h405/src/stm32_userleds.c @@ -0,0 +1,86 @@ +/**************************************************************************** + * boards/arm/stm32f4/olimex-stm32-h405/src/stm32_userleds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include "stm32.h" +#include "olimex-stm32-h405.h" + +#ifndef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* This array maps an LED number to GPIO pin configuration */ + +static uint32_t g_ledcfg[BOARD_NLEDS] = +{ + GPIO_LED_STATUS +}; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_userled_initialize + ****************************************************************************/ + +uint32_t board_userled_initialize(void) +{ + /* Configure LED1-4 GPIOs for output */ + + stm32_configgpio(GPIO_LED_STATUS); + return BOARD_NLEDS; +} + +/**************************************************************************** + * Name: board_userled + ****************************************************************************/ + +void board_userled(int led, bool ledon) +{ + if ((unsigned)led < BOARD_NLEDS) + { + stm32_gpiowrite(g_ledcfg[led], ledon); + } +} + +/**************************************************************************** + * Name: board_userled_all + ****************************************************************************/ + +void board_userled_all(uint32_t ledset) +{ + stm32_gpiowrite(GPIO_LED_STATUS, (ledset & BOARD_LED1_BIT) != 0); +} + +#endif /* !CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32f4/olimex-stm32-h407/CMakeLists.txt b/boards/arm/stm32f4/olimex-stm32-h407/CMakeLists.txt new file mode 100644 index 0000000000000..8bbac202e6fdf --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-h407/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32f4/olimex-stm32-h407/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/arm/stm32/olimex-stm32-h407/Kconfig b/boards/arm/stm32f4/olimex-stm32-h407/Kconfig similarity index 100% rename from boards/arm/stm32/olimex-stm32-h407/Kconfig rename to boards/arm/stm32f4/olimex-stm32-h407/Kconfig diff --git a/boards/arm/stm32f4/olimex-stm32-h407/configs/nsh/defconfig b/boards/arm/stm32f4/olimex-stm32-h407/configs/nsh/defconfig new file mode 100644 index 0000000000000..d1ceb8ccdc762 --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-h407/configs/nsh/defconfig @@ -0,0 +1,50 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_SPI_EXCHANGE is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="olimex-stm32-h407" +CONFIG_ARCH_BOARD_OLIMEX_STM32H407=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F407ZG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_MM_REGIONS=2 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_SPI=y +CONFIG_START_YEAR=2016 +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PWR=y +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_NSH=y +CONFIG_USART2_RXBUFSIZE=128 +CONFIG_USART2_SERIAL_CONSOLE=y +CONFIG_USART2_TXBUFSIZE=128 diff --git a/boards/arm/stm32f4/olimex-stm32-h407/configs/nsh_uext/defconfig b/boards/arm/stm32f4/olimex-stm32-h407/configs/nsh_uext/defconfig new file mode 100644 index 0000000000000..1c67edfa136a3 --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-h407/configs/nsh_uext/defconfig @@ -0,0 +1,49 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_SPI_EXCHANGE is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="olimex-stm32-h407" +CONFIG_ARCH_BOARD_OLIMEX_STM32H407=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F407ZG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_FS_PROCFS=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_MM_REGIONS=2 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_SPI=y +CONFIG_START_YEAR=2016 +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PWR=y +CONFIG_STM32_USART2=y +CONFIG_STM32_USART6=y +CONFIG_SYSTEM_NSH=y +CONFIG_USART2_RXBUFSIZE=128 +CONFIG_USART2_TXBUFSIZE=128 +CONFIG_USART6_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f4/olimex-stm32-h407/include/board.h b/boards/arm/stm32f4/olimex-stm32-h407/include/board.h new file mode 100644 index 0000000000000..231db8e186534 --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-h407/include/board.h @@ -0,0 +1,287 @@ +/**************************************************************************** + * boards/arm/stm32f4/olimex-stm32-h407/include/board.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_STM32_OLIMEX_STM32_H407_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32_OLIMEX_STM32_H407_INCLUDE_BOARD_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#ifndef __ASSEMBLY__ +# include +# include +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Clocking *****************************************************************/ + +/* The Olimex-STM32-H407 board features a 12MHz crystal and + * a 32kHz RTC backup crystal. + * + * This is the canonical configuration: + * System Clock source : PLL (HSE) + * SYSCLK(Hz) : 168000000 Determined by PLL configuration + * HCLK(Hz) : 168000000 (STM32_RCC_CFGR_HPRE) + * AHB Prescaler : 1 (STM32_RCC_CFGR_HPRE) + * APB1 Prescaler : 4 (STM32_RCC_CFGR_PPRE1) + * APB2 Prescaler : 2 (STM32_RCC_CFGR_PPRE2) + * HSE Frequency(Hz) : 8000000 (STM32_BOARD_XTAL) + * PLLM : 8 (STM32_PLLCFG_PLLM) + * PLLN : 336 (STM32_PLLCFG_PLLN) + * PLLP : 2 (STM32_PLLCFG_PLLP) + * PLLQ : 7 (STM32_PLLCFG_PLLQ) + * Main regulator output + * voltage : Scale1 mode Needed for high speed SYSCLK + * Flash Latency(WS) : 5 + * Prefetch Buffer : OFF + * Instruction cache : ON + * Data cache : ON + * Require 48MHz for + * USB OTG FS, + * SDIO and RNG clock : Enabled + */ + +/* HSI - 16 MHz RC factory-trimmed + * LSI - 32 KHz RC (30-60KHz, uncalibrated) + * HSE - On-board crystal frequency is 12MHz + * LSE - 32.768 kHz + * STM32F407ZGT6 - too 168Mhz + */ + +#define STM32_BOARD_XTAL 12000000ul + +#define STM32_HSI_FREQUENCY 16000000ul +#define STM32_LSI_FREQUENCY 32000 +#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL +#define STM32_LSE_FREQUENCY 32768 + +/* Main PLL Configuration. + * + * PLL source is HSE + * PLL_VCO = (STM32_HSE_FREQUENCY / PLLM) * PLLN + * = (25,000,000 / 12) * 360 + * = 240,000,000 + * SYSCLK = PLL_VCO / PLLP + * = 240,000,000 / 2 = 120,000,000 + * USB OTG FS, SDIO and RNG Clock + * = PLL_VCO / PLLQ + * = 240,000,000 / 5 = 48,000,000 + * = 48,000,000 + * + * Xtal /M *n /P SysClk AHB HCLK APB1 PCLK1 + * 12Mhz HSE /12 336 /2 PLLCLK 168Mhz /1 168 /4 42Mhz + * 12Mhz HSE /6 168 /2 PLLCLK 168Mhz /1 168 /4 42Mhz + */ + +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(3) +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(84) +#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_2 +#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(5) +#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(7) + +#define STM32_SYSCLK_FREQUENCY 168000000ul + +/* AHB clock (HCLK) is SYSCLK (168MHz) */ + +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY + +/* APB1 clock (PCLK1) is HCLK/4 (42MHz) */ + +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd4 /* PCLK1 = HCLK / 4 */ +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/4) + +/* Timers driven from APB1 will be twice PCLK1 */ + +#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) + +/* APB2 clock (PCLK2) is HCLK/2 */ + +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLKd2 /* PCLK2 = HCLK / 2 */ +#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/2) + +/* Timers driven from APB2 will be twice PCLK2 */ + +#define STM32_APB2_TIM1_CLKIN (2 * STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM8_CLKIN (2 * STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM9_CLKIN (2 * STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM10_CLKIN (2 * STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM11_CLKIN (2 * STM32_PCLK2_FREQUENCY) + +/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx + * otherwise frequency is 2xAPBx. + * Note: TIM1,8 are on APB2, others on APB1 + */ + +#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM2_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM3_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM4_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM5_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM6_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM7_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY + +/* SDIO dividers. Note that slower clocking is required when DMA is disabled + * in order to avoid RX overrun/TX underrun errors due to delayed responses + * to service FIFOs in interrupt driven mode. These values have not been + * tuned!!! + * + * SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(118+2)=400 KHz + */ + +#define SDIO_INIT_CLKDIV (118 << SDIO_CLKCR_CLKDIV_SHIFT) + +/* DMA ON: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(1+2)=16 MHz + * DMA OFF: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(2+2)=12 MHz + */ + +#ifdef CONFIG_SDIO_DMA +# define SDIO_MMCXFR_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT) +#else +# define SDIO_MMCXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT) +#endif + +/* DMA ON: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(1+2)=16 MHz + * DMA OFF: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(2+2)=12 MHz + */ + +#ifdef CONFIG_SDIO_DMA +# define SDIO_SDXFR_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT) +#else +# define SDIO_SDXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT) +#endif + +/* LED definitions **********************************************************/ + +/* If CONFIG_ARCH_LEDS is not defined, then the user can control the status + * LED in any way. + * The following definitions are used to access individual LEDs. + */ + +/* LED index values for use with board_userled() */ + +#define BOARD_LED_STATUS 0 +#define BOARD_NLEDS 1 + +/* LED bits for use with board_userled_all() */ + +#define BOARD_LED_STATUS_BIT (1 << BOARD_LED_STATUS) + +/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the status LED of + * the Olimex STM32-H405. + * The following definitions describe how NuttX controls the LEDs: + */ + +#define LED_STARTED 0 /* LED_STATUS on */ +#define LED_HEAPALLOCATE 1 /* no change */ +#define LED_IRQSENABLED 2 /* no change */ +#define LED_STACKCREATED 3 /* no change */ +#define LED_INIRQ 4 /* no change */ +#define LED_SIGNAL 5 /* no change */ +#define LED_ASSERTION 6 /* LED_STATUS off */ +#define LED_PANIC 7 /* LED_STATUS blinking */ + +/* Button definitions *******************************************************/ + +/* The Olimex STM32-H405 supports one buttons: */ + +#define BUTTON_BUT 0 +#define NUM_BUTTONS 1 + +#define BUTTON_BUT_BIT (1 << BUTTON_BUT) + +/* Alternate function pin selections ****************************************/ + +/* USART3: */ + +#if 0 +#define GPIO_USART3_RX (GPIO_USART3_RX_1|GPIO_SPEED_100MHz) /* PB11 */ +#define GPIO_USART3_TX (GPIO_USART3_TX_1|GPIO_SPEED_100MHz) /* PB10 */ +#define GPIO_USART3_CTS GPIO_USART3_CTS_1 /* PB13 */ +#define GPIO_USART3_RTS GPIO_USART3_RTS_1 /* PB14 */ +#endif + +/* USART2: */ + +#define GPIO_USART2_RX (GPIO_USART2_RX_1|GPIO_SPEED_100MHz) +#define GPIO_USART2_TX (GPIO_USART2_TX_1|GPIO_SPEED_100MHz) +#define GPIO_USART2_CTS GPIO_USART2_CTS_1 +#define GPIO_USART2_RTS GPIO_USART2_RTS_1 + +/* USART6: (UEXT connector) */ + +#define GPIO_USART6_RX (GPIO_USART6_RX_1|GPIO_SPEED_100MHz) +#define GPIO_USART6_TX (GPIO_USART6_TX_1|GPIO_SPEED_100MHz) + +/* GPIO_USART6_CTS and GPIO_USART6_RTS aren't used for UEXT */ + +/* CAN: */ + +#define GPIO_CAN1_RX (GPIO_CAN1_RX_2|GPIO_SPEED_50MHz) /* PB8 */ +#define GPIO_CAN1_TX (GPIO_CAN1_TX_2|GPIO_SPEED_50MHz) /* PB9 */ +#define GPIO_CAN2_RX (GPIO_CAN1_RX_2|GPIO_SPEED_50MHz) /* PB5 */ +#define GPIO_CAN2_TX (GPIO_CAN1_TX_2|GPIO_SPEED_50MHz) /* PB6 */ + +/* SDIO */ + +#define GPIO_SDIO_CK (GPIO_SDIO_CK_0|GPIO_SPEED_50MHz) +#define GPIO_SDIO_CMD (GPIO_SDIO_CMD_0|GPIO_SPEED_50MHz) +#define GPIO_SDIO_D0 (GPIO_SDIO_D0_0|GPIO_SPEED_50MHz) +#define GPIO_SDIO_D1 (GPIO_SDIO_D1_0|GPIO_SPEED_50MHz) +#define GPIO_SDIO_D2 (GPIO_SDIO_D2_0|GPIO_SPEED_50MHz) +#define GPIO_SDIO_D3 (GPIO_SDIO_D3_0|GPIO_SPEED_50MHz) + +/* USB OTG FS */ + +#define GPIO_OTGFS_DM (GPIO_OTGFS_DM_0|GPIO_SPEED_100MHz) +#define GPIO_OTGFS_DP (GPIO_OTGFS_DP_0|GPIO_SPEED_100MHz) +#define GPIO_OTGFS_ID (GPIO_OTGFS_ID_0|GPIO_SPEED_100MHz) +#define GPIO_OTGFS_SOF (GPIO_OTGFS_SOF_0|GPIO_SPEED_100MHz) + +/* DMA Channel/Stream Selections ********************************************/ + +/* Stream selections are arbitrary for now but might become important in the + * future if we set aside more DMA channels/streams. + * + * SDIO DMA + * DMAMAP_SDIO_1 = Channel 4, Stream 3 + * DMAMAP_SDIO_2 = Channel 4, Stream 6 + */ + +#define DMAMAP_SDIO DMAMAP_SDIO_1 + +#endif /* __BOARDS_ARM_STM32_OLIMEX_STM32_H407_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32f4/olimex-stm32-h407/scripts/Make.defs b/boards/arm/stm32f4/olimex-stm32-h407/scripts/Make.defs new file mode 100644 index 0000000000000..e158e90e0f33c --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-h407/scripts/Make.defs @@ -0,0 +1,41 @@ +############################################################################ +# boards/arm/stm32f4/olimex-stm32-h407/scripts/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/.config +include $(TOPDIR)/tools/Config.mk +include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs + +LDSCRIPT = ld.script +ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) + +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32f4/olimex-stm32-h407/scripts/ld.script b/boards/arm/stm32f4/olimex-stm32-h407/scripts/ld.script new file mode 100644 index 0000000000000..5fc191cd18ccf --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-h407/scripts/ld.script @@ -0,0 +1,125 @@ +/**************************************************************************** + * boards/arm/stm32f4/olimex-stm32-h407/scripts/ld.script + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* The STM32F407ZGT6 has 1024Kb of FLASH beginning at address 0x0800:0000 and + * 192Kb of SRAM. SRAM is split up into two blocks: + * + * 1) 112Kb of SRAM beginning at address 0x2000:0000 + * 2) 16Kb of SRAM beginning at address 0x2001:c000 + * 3) 64Kb of SRAM beginning at address 0x2002:0000 + * + * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 + * where the code expects to begin execution by jumping to the entry point in + * the 0x0800:0000 address + * range. + */ + +MEMORY +{ + flash (rx) : ORIGIN = 0x08000000, LENGTH = 1024K + sram (rwx) : ORIGIN = 0x20000000, LENGTH = 112K +} + +OUTPUT_ARCH(arm) +ENTRY(_stext) +SECTIONS +{ + .text : { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > flash + + .init_section : ALIGN(4) { + _sinit = ABSOLUTE(.); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) + _einit = ABSOLUTE(.); + } > flash + + .ARM.extab : ALIGN(4) { + *(.ARM.extab*) + } > flash + + .ARM.exidx : ALIGN(4) { + __exidx_start = ABSOLUTE(.); + *(.ARM.exidx*) + __exidx_end = ABSOLUTE(.); + } > flash + + .tdata : { + _stdata = ABSOLUTE(.); + *(.tdata .tdata.* .gnu.linkonce.td.*); + _etdata = ABSOLUTE(.); + } > flash + + .tbss : { + _stbss = ABSOLUTE(.); + *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); + _etbss = ABSOLUTE(.); + } > flash + + _eronly = ABSOLUTE(.); + + .data : ALIGN(4) { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > sram AT > flash + + .bss : ALIGN(4) { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + _ebss = ABSOLUTE(.); + } > sram + + /* Stabs debugging sections. */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/stm32f4/olimex-stm32-h407/src/CMakeLists.txt b/boards/arm/stm32f4/olimex-stm32-h407/src/CMakeLists.txt new file mode 100644 index 0000000000000..51a4ddbada411 --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-h407/src/CMakeLists.txt @@ -0,0 +1,65 @@ +# ############################################################################## +# boards/arm/stm32f4/olimex-stm32-h407/src/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(SRCS stm32_boot.c stm32_bringup.c) + +if(CONFIG_ARCH_LEDS) + list(APPEND SRCS stm32_autoleds.c) +else() + list(APPEND SRCS stm32_userleds.c) +endif() + +if(CONFIG_ARCH_BUTTONS) + list(APPEND SRCS stm32_buttons.c) +endif() + +if(CONFIG_ARCH_IDLE_CUSTOM) + list(APPEND SRCS stm32_idle.c) +endif() + +if(CONFIG_STM32_FSMC) + list(APPEND SRCS stm32_extmem.c) +endif() + +if(CONFIG_STM32_OTGFS) + list(APPEND SRCS stm32_usb.c) +endif() + +if(CONFIG_STM32_OTGHS) + list(APPEND SRCS stm32_usb.c) +endif() + +if(CONFIG_ADC) + list(APPEND SRCS stm32_adc.c) +endif() + +if(CONFIG_STM32_CAN_CHARDRIVER) + list(APPEND SRCS stm32_can.c) +endif() + +if(CONFIG_STM32_SDIO) + list(APPEND SRCS stm32_sdio.c) +endif() + +target_sources(board PRIVATE ${SRCS}) + +set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/ld.script") diff --git a/boards/arm/stm32f4/olimex-stm32-h407/src/Make.defs b/boards/arm/stm32f4/olimex-stm32-h407/src/Make.defs new file mode 100644 index 0000000000000..7fd882bf3aa8d --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-h407/src/Make.defs @@ -0,0 +1,67 @@ +############################################################################ +# boards/arm/stm32f4/olimex-stm32-h407/src/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +CSRCS = stm32_boot.c stm32_bringup.c + +ifeq ($(CONFIG_ARCH_LEDS),y) +CSRCS += stm32_autoleds.c +else +CSRCS += stm32_userleds.c +endif + +ifeq ($(CONFIG_ARCH_BUTTONS),y) +CSRCS += stm32_buttons.c +endif + +ifeq ($(CONFIG_ARCH_IDLE_CUSTOM),y) +CSRCS += stm32_idle.c +endif + +ifeq ($(CONFIG_STM32_FSMC),y) +CSRCS += stm32_extmem.c +endif + +ifeq ($(CONFIG_STM32_OTGFS),y) +CSRCS += stm32_usb.c +endif + +ifeq ($(CONFIG_STM32_OTGHS),y) +CSRCS += stm32_usb.c +endif + +ifeq ($(CONFIG_ADC),y) +CSRCS += stm32_adc.c +endif + +ifeq ($(CONFIG_STM32_CAN_CHARDRIVER),y) +CSRCS += stm32_can.c +endif + +ifeq ($(CONFIG_STM32_SDIO),y) +CSRCS += stm32_sdio.c +endif + +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/olimex-stm32-h407/src/olimex-stm32-h407.h b/boards/arm/stm32f4/olimex-stm32-h407/src/olimex-stm32-h407.h similarity index 99% rename from boards/arm/stm32/olimex-stm32-h407/src/olimex-stm32-h407.h rename to boards/arm/stm32f4/olimex-stm32-h407/src/olimex-stm32-h407.h index 5fe28b34fab4a..bb73d19691f6f 100644 --- a/boards/arm/stm32/olimex-stm32-h407/src/olimex-stm32-h407.h +++ b/boards/arm/stm32f4/olimex-stm32-h407/src/olimex-stm32-h407.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/olimex-stm32-h407/src/olimex-stm32-h407.h + * boards/arm/stm32f4/olimex-stm32-h407/src/olimex-stm32-h407.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f4/olimex-stm32-h407/src/stm32_adc.c b/boards/arm/stm32f4/olimex-stm32-h407/src/stm32_adc.c new file mode 100644 index 0000000000000..1e6c8c43807df --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-h407/src/stm32_adc.c @@ -0,0 +1,165 @@ +/**************************************************************************** + * boards/arm/stm32f4/olimex-stm32-h407/src/stm32_adc.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include +#include + +#include "chip.h" +#include "stm32_adc.h" +#include "olimex-stm32-h407.h" + +#ifdef CONFIG_ADC + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* Up to 3 ADC interfaces are supported */ + +#if STM32_NADC < 3 +# undef CONFIG_STM32_ADC3 +#endif + +#if STM32_NADC < 2 +# undef CONFIG_STM32_ADC2 +#endif + +#if STM32_NADC < 1 +# undef CONFIG_STM32_ADC1 +#endif + +#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) || defined(CONFIG_STM32_ADC3) +#ifndef CONFIG_STM32_ADC1 +# warning "Channel information only available for ADC1" +#endif + +/* The number of ADC channels in the conversion list */ + +#define ADC1_NCHANNELS 1//14 + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* The Olimex STM32-P405 has a 10 Kohm potentiometer AN_TR connected to PC0 + * ADC123_IN10 + */ + +/* Identifying number of each ADC channel: Variable Resistor. + * + * {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 15}; + */ + +#ifdef CONFIG_STM32_ADC1 +static const uint8_t g_chanlist[ADC1_NCHANNELS] = +{ + 1 +}; + +/* Configurations of pins used byte each ADC channels + * + * {GPIO_ADC1_IN1, GPIO_ADC1_IN2, GPIO_ADC1_IN3, GPIO_ADC1_IN4, + * GPIO_ADC1_IN5, GPIO_ADC1_IN6, GPIO_ADC1_IN7, GPIO_ADC1_IN8, + * GPIO_ADC1_IN9, GPIO_ADC1_IN10, GPIO_ADC1_IN11, GPIO_ADC1_IN12, + * GPIO_ADC1_IN13, GPIO_ADC1_IN15}; + */ + +static const uint32_t g_pinlist[ADC1_NCHANNELS] = +{ + GPIO_ADC1_IN1 +}; +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_adc_setup + * + * Description: + * Initialize ADC and register the ADC driver. + * + ****************************************************************************/ + +int stm32_adc_setup(void) +{ +#ifdef CONFIG_STM32_ADC1 + static bool initialized = false; + struct adc_dev_s *adc; + int ret; + int i; + + /* Check if we have already initialized */ + + if (!initialized) + { + /* Configure the pins as analog inputs for the selected channels */ + + for (i = 0; i < ADC1_NCHANNELS; i++) + { + stm32_configgpio(g_pinlist[i]); + } + + /* Call stm32_adcinitialize() to get an instance of the ADC interface */ + + adc = stm32_adcinitialize(1, g_chanlist, ADC1_NCHANNELS); + if (adc == NULL) + { + aerr("ERROR: Failed to get ADC interface\n"); + return -ENODEV; + } + + /* Register the ADC driver at "/dev/adc0" */ + + ret = adc_register("/dev/adc0", adc); + if (ret < 0) + { + aerr("ERROR: adc_register failed: %d\n", ret); + return ret; + } + + /* Now we are initialized */ + + initialized = true; + } + + return OK; +#else + return -ENOSYS; +#endif +} + +#endif /* CONFIG_STM32_ADC1 || CONFIG_STM32_ADC2 || CONFIG_STM32_ADC3 */ +#endif /* CONFIG_ADC */ diff --git a/boards/arm/stm32f4/olimex-stm32-h407/src/stm32_autoleds.c b/boards/arm/stm32f4/olimex-stm32-h407/src/stm32_autoleds.c new file mode 100644 index 0000000000000..6c9fa1b273fba --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-h407/src/stm32_autoleds.c @@ -0,0 +1,92 @@ +/**************************************************************************** + * boards/arm/stm32f4/olimex-stm32-h407/src/stm32_autoleds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32.h" +#include "olimex-stm32-h407.h" + +#ifdef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_autoled_initialize + ****************************************************************************/ + +void board_autoled_initialize(void) +{ + /* Configure LED_STATUS GPIO for output */ + + stm32_configgpio(GPIO_LED_STATUS); +} + +/**************************************************************************** + * Name: board_autoled_on + ****************************************************************************/ + +void board_autoled_on(int led) +{ + if (led == LED_STARTED) + { + stm32_gpiowrite(GPIO_LED_STATUS, true); + } + + if (led == LED_ASSERTION || led == LED_PANIC) + { + stm32_gpiowrite(GPIO_LED_STATUS, false); + } +} + +/**************************************************************************** + * Name: board_autoled_off + ****************************************************************************/ + +void board_autoled_off(int led) +{ + if (led == LED_STARTED) + { + stm32_gpiowrite(GPIO_LED_STATUS, false); + } + + if (led == LED_ASSERTION || led == LED_PANIC) + { + stm32_gpiowrite(GPIO_LED_STATUS, true); + } +} + +#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32f4/olimex-stm32-h407/src/stm32_boot.c b/boards/arm/stm32f4/olimex-stm32-h407/src/stm32_boot.c new file mode 100644 index 0000000000000..63eb2232eb3e5 --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-h407/src/stm32_boot.c @@ -0,0 +1,100 @@ +/**************************************************************************** + * boards/arm/stm32f4/olimex-stm32-h407/src/stm32_boot.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include +#include +#include + +#include "arm_internal.h" +#include "olimex-stm32-h407.h" +#include "stm32_ccm.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_boardinitialize + * + * Description: + * All STM32 architectures must provide the following entry point. + * This entry point is called early in the initialization -- after all + * memory has been configured and mapped but before any devices have been + * initialized. + * + ****************************************************************************/ + +void stm32_boardinitialize(void) +{ +#if defined(CONFIG_STM32_OTGFS) || defined(CONFIG_STM32_OTGHS) + /* Initialize USB if the 1) OTG FS controller is in the configuration and + * 2) disabled, and 3) the weak function stm32_usbinitialize() has been + * brought into the build. + * Presumably either CONFIG_USBDEV is also selected. + */ + + if (stm32_usbinitialize) + { + stm32_usbinitialize(); + } +#endif + +#ifdef CONFIG_ARCH_LEDS + /* Configure on-board LEDs if LED support has been selected. */ + + board_autoled_initialize(); +#endif + +#ifdef CONFIG_ARCH_BUTTONS + /* Configure on-board BUTTONs if BUTTON support has been selected. */ + + board_button_initialize(); +#endif +} + +/**************************************************************************** + * Name: board_late_initialize + * + * Description: + * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_late_initialize(). board_late_initialize() will be + * called immediately after up_intitialize() is called and just before the + * initial application is started. This additional initialization phase + * may be used, for example, to initialize board-specific device drivers. + * + ****************************************************************************/ + +#ifdef CONFIG_BOARD_LATE_INITIALIZE +void board_late_initialize(void) +{ + stm32_bringup(); +} +#endif diff --git a/boards/arm/stm32f4/olimex-stm32-h407/src/stm32_bringup.c b/boards/arm/stm32f4/olimex-stm32-h407/src/stm32_bringup.c new file mode 100644 index 0000000000000..83932835b4b7a --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-h407/src/stm32_bringup.c @@ -0,0 +1,168 @@ +/**************************************************************************** + * boards/arm/stm32f4/olimex-stm32-h407/src/stm32_bringup.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include + +#ifdef CONFIG_USBMONITOR +# include +#endif + +#ifdef CONFIG_STM32_OTGFS +# include "stm32_usbhost.h" +#endif + +#include "stm32.h" +#include "olimex-stm32-h407.h" + +/* Conditional logic in olimex-stm32-h407.h will determine if certain + * features are supported. + * Tests for these features need to be made after including + * olimex-stm32-h407.h. + */ + +#ifdef HAVE_RTC_DRIVER +# include +# include "stm32_rtc.h" +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_bringup + * + * Description: + * Perform architecture specific initialization + * + * CONFIG_BOARD_LATE_INITIALIZE=y: + * Called from board_late_initialize(). + * + * Otherwise, bad news: Never called + * + ****************************************************************************/ + +int stm32_bringup(void) +{ +#ifdef HAVE_RTC_DRIVER + struct rtc_lowerhalf_s *lower; +#endif + int ret; + +#ifdef CONFIG_STM32_CAN_CHARDRIVER + /* Initialize CAN and register the CAN driver. */ + + ret = stm32_can_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_can_setup failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_ADC + /* Initialize ADC and register the ADC driver. */ + + ret = stm32_adc_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_adc_setup failed: %d\n", ret); + } +#endif + +#ifdef HAVE_SDIO + /* Initialize the SDIO block driver */ + + ret = stm32_sdio_initialize(); + if (ret != OK) + { + syslog(LOG_ERR, + "ERROR: Failed to initialize MMC/SD driver: %d\n", + ret); + } +#endif + +#ifdef HAVE_USBHOST + /* Initialize USB host operation. + * stm32_usbhost_initialize() starts a thread will monitor for USB + * connection and disconnection events. + */ + + ret = stm32_usbhost_initialize(); + if (ret != OK) + { + syslog(LOG_ERR, + "ERROR: Failed to initialize USB host: %d\n", + ret); + } +#endif + +#ifdef HAVE_USBMONITOR + /* Start the USB Monitor */ + + ret = usbmonitor_start(); + if (ret != OK) + { + syslog(LOG_ERR, + "ERROR: Failed to start USB monitor: %d\n", + ret); + } +#endif + +#ifdef HAVE_RTC_DRIVER + /* Instantiate the STM32 lower-half RTC driver */ + + lower = stm32_rtc_lowerhalf(); + if (!lower) + { + syslog(LOG_ERR, + "ERROR: Failed to instantiate the RTC lower-half driver\n"); + } + else + { + /* Bind the lower half driver and register the combined RTC driver + * as /dev/rtc0 + */ + + ret = rtc_initialize(0, lower); + if (ret < 0) + { + syslog(LOG_ERR, + "ERROR: Failed to bind/register the RTC driver: %d\n", + ret); + } + } +#endif + + UNUSED(ret); + return OK; +} diff --git a/boards/arm/stm32f4/olimex-stm32-h407/src/stm32_buttons.c b/boards/arm/stm32f4/olimex-stm32-h407/src/stm32_buttons.c new file mode 100644 index 0000000000000..2c8c1b3b4904a --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-h407/src/stm32_buttons.c @@ -0,0 +1,140 @@ +/**************************************************************************** + * boards/arm/stm32f4/olimex-stm32-h407/src/stm32_buttons.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include +#include + +#include "olimex-stm32-h407.h" + +#ifdef CONFIG_ARCH_BUTTONS + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* Pin configuration for each Olimex-STM32-H405 button. This array is indexed + * by the BUTTON_* definitions in board.h + */ + +static const uint32_t g_buttons[NUM_BUTTONS] = +{ + GPIO_BTN_BUT +}; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_button_initialize + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. + * + ****************************************************************************/ + +uint32_t board_button_initialize(void) +{ + int i; + + /* Configure the GPIO pins as inputs. NOTE that EXTI interrupts are + * configured for all pins. + */ + + for (i = 0; i < NUM_BUTTONS; i++) + { + stm32_configgpio(g_buttons[i]); + } + + return NUM_BUTTONS; +} + +/**************************************************************************** + * Name: board_buttons + ****************************************************************************/ + +uint32_t board_buttons(void) +{ + uint32_t ret = 0; + + /* Check that state of each key */ + + if (!stm32_gpioread(g_buttons[BUTTON_BUT])) + { + ret |= BUTTON_BUT_BIT; + } + + return ret; +} + +/**************************************************************************** + * Button support. + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. + * + * After board_button_initialize() has been called, board_buttons() may be + * called to collect the state of all buttons. board_buttons() returns an + * 32-bit bit set with each bit associated with a button. See the + * BUTTON_*_BIT definitions in board.h for the meaning of each bit. + * + * board_button_irq() may be called to register an interrupt handler that + * will be called when a button is depressed or released. The ID value is + * a button enumeration value that uniquely identifies a button resource. + * See the BUTTON_* definitions in board.h for the meaning of enumeration + * value. + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_IRQBUTTONS +int board_button_irq(int id, xcpt_t irqhandler, void *arg) +{ + int ret = -EINVAL; + + /* The following should be atomic */ + + if (id >= MIN_IRQBUTTON && id <= MAX_IRQBUTTON) + { + ret = stm32_gpiosetevent(g_buttons[id], true, true, true, irqhandler, + arg); + } + + return ret; +} +#endif +#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/stm32f4/olimex-stm32-h407/src/stm32_can.c b/boards/arm/stm32f4/olimex-stm32-h407/src/stm32_can.c new file mode 100644 index 0000000000000..3953ecafb566a --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-h407/src/stm32_can.c @@ -0,0 +1,100 @@ +/**************************************************************************** + * boards/arm/stm32f4/olimex-stm32-h407/src/stm32_can.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include + +#include "stm32.h" +#include "stm32_can.h" +#include "olimex-stm32-h407.h" + +#ifdef CONFIG_CAN + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +#if defined(CONFIG_STM32_CAN1) && defined(CONFIG_STM32_CAN2) +# warning "Both CAN1 and CAN2 are enabled. Only CAN1 is used." +# undef CONFIG_STM32_CAN2 +#endif + +#ifdef CONFIG_STM32_CAN1 +# define CAN_PORT 1 +#else +# define CAN_PORT 2 +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_can_setup + * + * Description: + * Initialize CAN and register the CAN device + * + ****************************************************************************/ + +int stm32_can_setup(void) +{ +#if defined(CONFIG_STM32_CAN1) || defined(CONFIG_STM32_CAN2) + struct can_dev_s *can; + int ret; + + /* Call stm32_caninitialize() to get an instance of the CAN interface */ + + can = stm32_caninitialize(CAN_PORT); + if (can == NULL) + { + canerr("ERROR: Failed to get CAN interface\n"); + return -ENODEV; + } + + /* Register the CAN driver at "/dev/can0" */ + + ret = can_register("/dev/can0", can); + if (ret < 0) + { + canerr("ERROR: can_register failed: %d\n", ret); + return ret; + } + + return OK; +#else + return -ENODEV; +#endif +} + +#endif /* CONFIG_CAN */ diff --git a/boards/arm/stm32f4/olimex-stm32-h407/src/stm32_sdio.c b/boards/arm/stm32f4/olimex-stm32-h407/src/stm32_sdio.c new file mode 100644 index 0000000000000..e8c8fda4baad7 --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-h407/src/stm32_sdio.c @@ -0,0 +1,161 @@ +/**************************************************************************** + * boards/arm/stm32f4/olimex-stm32-h407/src/stm32_sdio.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include + +#include "stm32.h" +#include "olimex-stm32-h407.h" + +#ifdef HAVE_SDIO + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* Card detections requires card support and a card detection GPIO */ + +#define HAVE_NCD 1 +#if !defined(HAVE_SDIO) || !defined(GPIO_SDIO_NCD) +# undef HAVE_NCD +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static struct sdio_dev_s *g_sdio_dev; +#ifdef HAVE_NCD +static bool g_sd_inserted; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_ncd_interrupt + * + * Description: + * Card detect interrupt handler. + * + ****************************************************************************/ + +#ifdef HAVE_NCD +static int stm32_ncd_interrupt(int irq, void *context) +{ + bool present; + + present = !stm32_gpioread(GPIO_SDIO_NCD); + if (present != g_sd_inserted) + { + sdio_mediachange(g_sdio_dev, present); + g_sd_inserted = present; + } + + return OK; +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_sdio_initialize + * + * Description: + * Initialize SDIO-based MMC/SD card support + * + ****************************************************************************/ + +int stm32_sdio_initialize(void) +{ + int ret; + +#ifdef HAVE_NCD + /* Configure the card detect GPIO */ + + stm32_configgpio(GPIO_SDIO_NCD); + + /* Register an interrupt handler for the card detect pin */ + + stm32_gpiosetevent(GPIO_SDIO_NCD, true, true, true, + stm32_ncd_interrupt, NULL); +#endif + + /* Mount the SDIO-based MMC/SD block driver */ + + /* First, get an instance of the SDIO interface */ + + finfo("Initializing SDIO slot %d\n", SDIO_SLOTNO); + + g_sdio_dev = sdio_initialize(SDIO_SLOTNO); + if (!g_sdio_dev) + { + ferr("ERROR: Failed to initialize SDIO slot %d\n", SDIO_SLOTNO); + return -ENODEV; + } + + /* Now bind the SDIO interface to the MMC/SD driver */ + + finfo("Bind SDIO to the MMC/SD driver, minor=%d\n", SDIO_MINOR); + + ret = mmcsd_slotinitialize(SDIO_MINOR, g_sdio_dev); + if (ret != OK) + { + ferr("ERROR: Failed to bind SDIO to the MMC/SD driver: %d\n", ret); + return ret; + } + + finfo("Successfully bound SDIO to the MMC/SD driver\n"); + +#ifdef HAVE_NCD + /* Use SD card detect pin to check if a card is g_sd_inserted */ + + g_sd_inserted = !stm32_gpioread(GPIO_SDIO_NCD); + finfo("Card detect : %d\n", g_sd_inserted); + + sdio_mediachange(g_sdio_dev, g_sd_inserted); +#else + /* Assume that the SD card is inserted. What choice do we have? */ + + sdio_mediachange(g_sdio_dev, true); +#endif + + return OK; +} + +#endif /* HAVE_SDIO */ diff --git a/boards/arm/stm32f4/olimex-stm32-h407/src/stm32_usb.c b/boards/arm/stm32f4/olimex-stm32-h407/src/stm32_usb.c new file mode 100644 index 0000000000000..fefb1776b45ff --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-h407/src/stm32_usb.c @@ -0,0 +1,311 @@ +/**************************************************************************** + * boards/arm/stm32f4/olimex-stm32-h407/src/stm32_usb.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include "arm_internal.h" +#include "stm32.h" +#include "stm32_otgfs.h" +#include "stm32_otghs.h" +#include "olimex-stm32-h407.h" + +#ifdef CONFIG_STM32_OTGHS + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#if defined(CONFIG_USBDEV) || defined(CONFIG_USBHOST) +# define HAVE_USB 1 +#else +# warning "CONFIG_STM32_OTGHS is enabled but neither CONFIG_USBDEV nor CONFIG_USBHOST" +# undef HAVE_USB +#endif + +#ifndef CONFIG_STM32F407_USBHOST_PRIO +# define CONFIG_STM32F407_USBHOST_PRIO 100 +#endif + +#ifndef CONFIG_STM32F407_USBHOST_STACKSIZE +# define CONFIG_STM32F407_USBHOST_STACKSIZE 1024 +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +static struct usbhost_connection_s *g_usbconn; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: usbhost_waiter + * + * Description: + * Wait for USB devices to be connected. + * + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +static int usbhost_waiter(int argc, char *argv[]) +{ + struct usbhost_hubport_s *hport; + + uinfo("Running\n"); + for (; ; ) + { + /* Wait for the device to change state */ + + DEBUGVERIFY(CONN_WAIT(g_usbconn, &hport)); + uinfo("%s\n", hport->connected ? "connected" : "disconnected"); + + /* Did we just become connected? */ + + if (hport->connected) + { + /* Yes.. enumerate the newly connected device */ + + CONN_ENUMERATE(g_usbconn, hport); + } + } + + /* Keep the compiler from complaining */ + + return 0; +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_usbinitialize + * + * Description: + * Called from stm32_usbinitialize very early in initialization to setup + * USB-related GPIO pins for the STM32F4Discovery board. + * + ****************************************************************************/ + +void stm32_usbinitialize(void) +{ + /* The OTG FS has an internal soft pull-up. + * No GPIO configuration is required + */ + + /* Configure the OTG FS VBUS sensing GPIO, + * Power On, and Overcurrent GPIOs + */ + +#ifdef CONFIG_STM32_OTGHS + stm32_configgpio(GPIO_OTGHS_VBUS); + stm32_configgpio(GPIO_OTGHS_PWRON); + stm32_configgpio(GPIO_OTGHS_OVER); +#endif +} + +/**************************************************************************** + * Name: stm32_usbhost_initialize + * + * Description: + * Called at application startup time to initialize the USB host + * functionality. + * This function will start a thread that will monitor for device + * connection/disconnection events. + * + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +int stm32_usbhost_initialize(void) +{ + int ret; + + /* First, register all of the class drivers needed to support the drivers + * that we care about: + */ + + uinfo("Register class drivers\n"); + +#ifdef CONFIG_USBHOST_HUB + /* Initialize USB hub class support */ + + ret = usbhost_hub_initialize(); + if (ret < 0) + { + uerr("ERROR: usbhost_hub_initialize failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_USBHOST_MSC + /* Register the USB mass storage class class */ + + ret = usbhost_msc_initialize(); + if (ret != OK) + { + uerr("ERROR: Failed to register the mass storage class: %d\n", ret); + } +#endif + +#ifdef CONFIG_USBHOST_CDCACM + /* Register the CDC/ACM serial class */ + + ret = usbhost_cdcacm_initialize(); + if (ret != OK) + { + uerr("ERROR: Failed to register the CDC/ACM serial class: %d\n", ret); + } +#endif + + /* Then get an instance of the USB host interface */ + + uinfo("Initialize USB host\n"); + g_usbconn = stm32_otghshost_initialize(0); + if (g_usbconn) + { + /* Start a thread to handle device connection. */ + + uinfo("Start usbhost_waiter\n"); + + ret = kthread_create("usbhost", CONFIG_STM32H407_USBHOST_PRIO, + CONFIG_STM32H407_USBHOST_STACKSIZE, + usbhost_waiter, NULL); + return ret < 0 ? -ENOEXEC : OK; + } + + return -ENODEV; +} +#endif + +/**************************************************************************** + * Name: stm32_usbhost_vbusdrive + * + * Description: + * Enable/disable driving of VBUS 5V output. This function must be + * provided be each platform that implements the STM32 OTG FS host + * interface + * + * "On-chip 5 V VBUS generation is not supported. For this reason, a + * charge pump or, if 5 V are available on the application board, a + * basic power switch, must be added externally to drive the 5 V VBUS + * line. The external charge pump can be driven by any GPIO output. + * When the application decides to power on VBUS using the chosen GPIO, + * it must also set the port power bit in the host port control and + * status register (PPWR bit in OTG_FS_HPRT). + * + * "The application uses this field to control power to this port, + * and the core clears this bit on an overcurrent condition." + * + * Input Parameters: + * iface - For future growth to handle multiple USB host interface. + * Should be zero. + * enable - true: enable VBUS power; false: disable VBUS power + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +void stm32_usbhost_vbusdrive(int iface, bool enable) +{ + DEBUGASSERT(iface == 0); + + if (enable) + { + /* Enable the Power Switch by driving the enable pin low */ + + stm32_gpiowrite(GPIO_OTGHS_PWRON, false); + } + else + { + /* Disable the Power Switch by driving the enable pin high */ + + stm32_gpiowrite(GPIO_OTGHS_PWRON, true); + } +} +#endif + +/**************************************************************************** + * Name: stm32_setup_overcurrent + * + * Description: + * Setup to receive an interrupt-level callback if an overcurrent + * condition is detected. + * + * Input Parameters: + * handler - New overcurrent interrupt handler + * arg - The argument provided for the interrupt handler + * + * Returned Value: + * Zero (OK) is returned on success. Otherwise, a negated errno value + * is returned to indicate the nature of the failure. + * + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +int stm32_setup_overcurrent(xcpt_t handler, void *arg) +{ + return stm32_gpiosetevent(GPIO_OTGHS_OVER, true, true, true, handler, arg); +} +#endif + +/**************************************************************************** + * Name: stm32_usbsuspend + * + * Description: + * Board logic must provide the stm32_usbsuspend logic if the USBDEV + * driver is used. This function is called whenever the USB enters or + * leaves suspend mode. This is an opportunity for the board logic to + * shutdown clocks, power, etc. while the USB is suspended. + * + ****************************************************************************/ + +#ifdef CONFIG_USBDEV +void stm32_usbsuspend(struct usbdev_s *dev, bool resume) +{ + uinfo("resume: %d\n", resume); +} +#endif + +#endif /* CONFIG_STM32_OTGHS */ diff --git a/boards/arm/stm32f4/olimex-stm32-h407/src/stm32_userleds.c b/boards/arm/stm32f4/olimex-stm32-h407/src/stm32_userleds.c new file mode 100644 index 0000000000000..807ad57522dc5 --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-h407/src/stm32_userleds.c @@ -0,0 +1,91 @@ +/**************************************************************************** + * boards/arm/stm32f4/olimex-stm32-h407/src/stm32_userleds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32.h" +#include "olimex-stm32-h407.h" + +#ifndef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* This array maps an LED number to GPIO pin configuration */ + +static uint32_t g_ledcfg[BOARD_NLEDS] = +{ + GPIO_LED_STATUS +}; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_userled_initialize + ****************************************************************************/ + +uint32_t board_userled_initialize(void) +{ + /* Configure LED1-4 GPIOs for output */ + + stm32_configgpio(GPIO_LED_STATUS); + return BOARD_NLEDS; +} + +/**************************************************************************** + * Name: board_userled + ****************************************************************************/ + +void board_userled(int led, bool ledon) +{ + if ((unsigned)led < BOARD_NLEDS) + { + stm32_gpiowrite(g_ledcfg[led], ledon); + } +} + +/**************************************************************************** + * Name: board_userled_all + ****************************************************************************/ + +void board_userled_all(uint32_t ledset) +{ + stm32_gpiowrite(GPIO_LED_STATUS, (ledset & BOARD_LED1_BIT) != 0); +} + +#endif /* !CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32f4/olimex-stm32-p407/CMakeLists.txt b/boards/arm/stm32f4/olimex-stm32-p407/CMakeLists.txt new file mode 100644 index 0000000000000..03081b159c48f --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-p407/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32f4/olimex-stm32-p407/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/arm/stm32/olimex-stm32-p407/Kconfig b/boards/arm/stm32f4/olimex-stm32-p407/Kconfig similarity index 100% rename from boards/arm/stm32/olimex-stm32-p407/Kconfig rename to boards/arm/stm32f4/olimex-stm32-p407/Kconfig diff --git a/boards/arm/stm32f4/olimex-stm32-p407/configs/audio/defconfig b/boards/arm/stm32f4/olimex-stm32-p407/configs/audio/defconfig new file mode 100644 index 0000000000000..c4aa5630fee81 --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-p407/configs/audio/defconfig @@ -0,0 +1,68 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="olimex-stm32-p407" +CONFIG_ARCH_BOARD_OLIMEX_STM32P407=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F407ZG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_IRQBUTTONS=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_AUDIO=y +CONFIG_AUDIO_CS4344=y +CONFIG_AUDIO_EXCLUDE_TONE=y +CONFIG_AUDIO_EXCLUDE_VOLUME=y +CONFIG_AUDIO_I2S=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_DRIVERS_AUDIO=y +CONFIG_FAT_LCNAMES=y +CONFIG_FAT_LFN=y +CONFIG_FS_FAT=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_DISABLE_GET=y +CONFIG_NSH_DISABLE_IFUPDOWN=y +CONFIG_NSH_DISABLE_PUT=y +CONFIG_NSH_DISABLE_WGET=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_NXPLAYER_DEFAULT_MEDIADIR="/mnt/music" +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=131072 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=192 +CONFIG_SCHED_WAITPID=y +CONFIG_START_YEAR=2013 +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_DMA1=y +CONFIG_STM32_I2S3=y +CONFIG_STM32_I2S3_TX=y +CONFIG_STM32_I2S_MCK=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PWR=y +CONFIG_STM32_SPI3=y +CONFIG_STM32_SPI3_DMA=y +CONFIG_STM32_USART3=y +CONFIG_STM32_USBHOST=y +CONFIG_SYSTEM_NSH=y +CONFIG_SYSTEM_NXPLAYER=y +CONFIG_TASK_NAME_SIZE=32 +CONFIG_USART3_SERIAL_CONSOLE=y +CONFIG_USBHOST_MSC=y diff --git a/boards/arm/stm32f4/olimex-stm32-p407/configs/dhtxx/defconfig b/boards/arm/stm32f4/olimex-stm32-p407/configs/dhtxx/defconfig new file mode 100644 index 0000000000000..c2568a49d5a41 --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-p407/configs/dhtxx/defconfig @@ -0,0 +1,62 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="olimex-stm32-p407" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_OLIMEX_STM32P407=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F407ZG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_IRQBUTTONS=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL_USBDEVCTRL=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_CDCACM=y +CONFIG_CDCACM_CONSOLE=y +CONFIG_EXAMPLES_DHTXX=y +CONFIG_FAT_LCNAMES=y +CONFIG_FAT_LFN=y +CONFIG_FS_FAT=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_DISABLE_GET=y +CONFIG_NSH_DISABLE_IFUPDOWN=y +CONFIG_NSH_DISABLE_PUT=y +CONFIG_NSH_DISABLE_WGET=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=131072 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=192 +CONFIG_SCHED_WAITPID=y +CONFIG_SENSORS=y +CONFIG_SENSORS_DHTXX=y +CONFIG_START_YEAR=2013 +CONFIG_STM32_CCMEXCLUDE=y +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_FREERUN=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PWR=y +CONFIG_STM32_TIM1=y +CONFIG_STM32_USART3=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=32 +CONFIG_USBDEV=y diff --git a/boards/arm/stm32f4/olimex-stm32-p407/configs/hidkbd/defconfig b/boards/arm/stm32f4/olimex-stm32-p407/configs/hidkbd/defconfig new file mode 100644 index 0000000000000..1474e1bd56540 --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-p407/configs/hidkbd/defconfig @@ -0,0 +1,56 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="olimex-stm32-p407" +CONFIG_ARCH_BOARD_OLIMEX_STM32P407=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F407ZG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_IRQBUTTONS=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_EXAMPLES_HIDKBD=y +CONFIG_FAT_LCNAMES=y +CONFIG_FAT_LFN=y +CONFIG_FS_FAT=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_DISABLE_GET=y +CONFIG_NSH_DISABLE_IFUPDOWN=y +CONFIG_NSH_DISABLE_PUT=y +CONFIG_NSH_DISABLE_WGET=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=131072 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=192 +CONFIG_SCHED_WAITPID=y +CONFIG_START_YEAR=2013 +CONFIG_STM32_CCMEXCLUDE=y +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PWR=y +CONFIG_STM32_USART3=y +CONFIG_STM32_USBHOST=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=32 +CONFIG_USART3_SERIAL_CONSOLE=y +CONFIG_USBHOST_HIDKBD=y diff --git a/boards/arm/stm32f4/olimex-stm32-p407/configs/kelf/Make.defs b/boards/arm/stm32f4/olimex-stm32-p407/configs/kelf/Make.defs new file mode 100644 index 0000000000000..9c06da91d4e6e --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-p407/configs/kelf/Make.defs @@ -0,0 +1,41 @@ +############################################################################ +# boards/arm/stm32f4/olimex-stm32-p407/configs/kelf/Make.defs +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/.config +include $(TOPDIR)/tools/Config.mk +include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs + +ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)memory.ld +ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)kernel-space.ld + +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ + +# NXFLAT module definitions + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)$(DELIM)binfmt$(DELIM)libnxflat$(DELIM)gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32f4/olimex-stm32-p407/configs/kelf/defconfig b/boards/arm/stm32f4/olimex-stm32-p407/configs/kelf/defconfig new file mode 100644 index 0000000000000..15ba73092b067 --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-p407/configs/kelf/defconfig @@ -0,0 +1,59 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="olimex-stm32-p407" +CONFIG_ARCH_BOARD_OLIMEX_STM32P407=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F407ZG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_ARM_MPU=y +CONFIG_BINFMT_CONSTRUCTORS=y +CONFIG_BOARDCTL=y +CONFIG_BOARDCTL_ROMDISK=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILD_PROTECTED=y +CONFIG_CONSOLE_SYSLOG=y +CONFIG_ELF=y +CONFIG_ELF_STACKSIZE=4096 +CONFIG_EXAMPLES_ELF=y +CONFIG_EXAMPLES_ELF_DEVPATH="/dev/sda" +CONFIG_EXAMPLES_ELF_FSREMOVEABLE=y +CONFIG_FAT_LCNAMES=y +CONFIG_FAT_LFN=y +CONFIG_FS_FAT=y +CONFIG_HAVE_CXX=y +CONFIG_INIT_ENTRYPOINT="elf_main" +CONFIG_INIT_STACKSIZE=4096 +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_ENVPATH=y +CONFIG_MM_KERNEL_HEAPSIZE=16384 +CONFIG_MM_REGIONS=2 +CONFIG_NUTTX_USERSPACE=0x08020000 +CONFIG_PASS1_BUILDIR="boards/arm/stm32f4/olimex-stm32-p407/kernel" +CONFIG_PATH_INITIAL="/mnt/vfat" +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=4 +CONFIG_START_MONTH=8 +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_RNG=y +CONFIG_STM32_SDIO=y +CONFIG_STM32_USART3=y +CONFIG_STM32_USBHOST=y +CONFIG_SYMTAB_ORDEREDBYNAME=y +CONFIG_USART3_SERIAL_CONSOLE=y +CONFIG_USBHOST_ISOC_DISABLE=y +CONFIG_USBHOST_MSC=y diff --git a/boards/arm/stm32f4/olimex-stm32-p407/configs/kmodule/Make.defs b/boards/arm/stm32f4/olimex-stm32-p407/configs/kmodule/Make.defs new file mode 100644 index 0000000000000..22979d8184d48 --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-p407/configs/kmodule/Make.defs @@ -0,0 +1,41 @@ +############################################################################ +# boards/arm/stm32f4/olimex-stm32-p407/configs/kmodule/Make.defs +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/.config +include $(TOPDIR)/tools/Config.mk +include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs + +ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)memory.ld +ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)kernel-space.ld + +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ + +# NXFLAT module definitions + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)$(DELIM)binfmt$(DELIM)libnxflat$(DELIM)gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32f4/olimex-stm32-p407/configs/kmodule/defconfig b/boards/arm/stm32f4/olimex-stm32-p407/configs/kmodule/defconfig new file mode 100644 index 0000000000000..1026bb269dd02 --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-p407/configs/kmodule/defconfig @@ -0,0 +1,55 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="olimex-stm32-p407" +CONFIG_ARCH_BOARD_OLIMEX_STM32P407=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F407ZG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQBUTTONS=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_ARM_MPU=y +CONFIG_BOARDCTL=y +CONFIG_BOARDCTL_ROMDISK=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILD_PROTECTED=y +CONFIG_EXAMPLES_MODULE=y +CONFIG_EXAMPLES_MODULE_DEVPATH="/dev/sda" +CONFIG_EXAMPLES_MODULE_FSREMOVEABLE=y +CONFIG_FAT_LCNAMES=y +CONFIG_FAT_LFN=y +CONFIG_FS_FAT=y +CONFIG_FS_PROCFS=y +CONFIG_INIT_ENTRYPOINT="module_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_MM_KERNEL_HEAPSIZE=16384 +CONFIG_MM_REGIONS=2 +CONFIG_MODULE=y +CONFIG_NUTTX_USERSPACE=0x08020000 +CONFIG_PASS1_BUILDIR="boards/arm/stm32f4/olimex-stm32-p407/kernel" +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=5 +CONFIG_START_MONTH=8 +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PWR=y +CONFIG_STM32_USART3=y +CONFIG_STM32_USBHOST=y +CONFIG_SYMTAB_ORDEREDBYNAME=y +CONFIG_USART3_SERIAL_CONSOLE=y +CONFIG_USBHOST_ISOC_DISABLE=y +CONFIG_USBHOST_MSC=y diff --git a/boards/arm/stm32f4/olimex-stm32-p407/configs/knsh/Make.defs b/boards/arm/stm32f4/olimex-stm32-p407/configs/knsh/Make.defs new file mode 100644 index 0000000000000..f9a6444eca014 --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-p407/configs/knsh/Make.defs @@ -0,0 +1,42 @@ +############################################################################ +# boards/arm/stm32f4/olimex-stm32-p407/configs/knsh/Make.defs +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/.config +include $(TOPDIR)/tools/Config.mk +include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs + +LDSCRIPT1 = memory.ld +LDSCRIPT2 = kernel-space.ld + +ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT1) +ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT2) + +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-gotoff.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32f4/olimex-stm32-p407/configs/knsh/defconfig b/boards/arm/stm32f4/olimex-stm32-p407/configs/knsh/defconfig new file mode 100644 index 0000000000000..40beb1054dc67 --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-p407/configs/knsh/defconfig @@ -0,0 +1,55 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_SYSTEM_DD is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="olimex-stm32-p407" +CONFIG_ARCH_BOARD_OLIMEX_STM32P407=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F407ZG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_IRQBUTTONS=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_ARM_MPU=y +CONFIG_BOARDCTL=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILD_PROTECTED=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_MM_KERNEL_HEAPSIZE=16384 +CONFIG_NSH_DISABLE_GET=y +CONFIG_NSH_DISABLE_IFUPDOWN=y +CONFIG_NSH_DISABLE_MKRD=y +CONFIG_NSH_DISABLE_PUT=y +CONFIG_NSH_DISABLE_WGET=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_NUTTX_USERSPACE=0x08020000 +CONFIG_PASS1_BUILDIR="boards/arm/stm32f4/olimex-stm32-p407/kernel" +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=131072 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=192 +CONFIG_SCHED_WAITPID=y +CONFIG_START_YEAR=2013 +CONFIG_STM32_CCMEXCLUDE=y +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_PWR=y +CONFIG_STM32_USART3=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=32 +CONFIG_USART3_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f4/olimex-stm32-p407/configs/module/defconfig b/boards/arm/stm32f4/olimex-stm32-p407/configs/module/defconfig new file mode 100644 index 0000000000000..a9a50a224efb3 --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-p407/configs/module/defconfig @@ -0,0 +1,49 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="olimex-stm32-p407" +CONFIG_ARCH_BOARD_OLIMEX_STM32P407=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F407ZG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQBUTTONS=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL_ROMDISK=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_EXAMPLES_MODULE=y +CONFIG_FAT_LCNAMES=y +CONFIG_FAT_LFN=y +CONFIG_FS_FAT=y +CONFIG_FS_PROCFS=y +CONFIG_FS_ROMFS=y +CONFIG_HOST_WINDOWS=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_LINE_MAX=64 +CONFIG_MODULE=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_DISABLE_IFUPDOWN=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=393216 +CONFIG_RAM_START=0x20400000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_WAITPID=y +CONFIG_START_MONTH=6 +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_PWR=y +CONFIG_STM32_USART3=y +CONFIG_SYSTEM_NSH=y +CONFIG_USART3_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f4/olimex-stm32-p407/configs/mqttc/defconfig b/boards/arm/stm32f4/olimex-stm32-p407/configs/mqttc/defconfig new file mode 100644 index 0000000000000..6dc5ccbb18bb5 --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-p407/configs/mqttc/defconfig @@ -0,0 +1,83 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_STM32_AUTONEG is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="olimex-stm32-p407" +CONFIG_ARCH_BOARD_OLIMEX_STM32P407=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F407ZG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_IRQBUTTONS=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_ETH0_PHY_KS8721=y +CONFIG_EXAMPLES_MQTTC=y +CONFIG_FAT_LCNAMES=y +CONFIG_FAT_LFN=y +CONFIG_FS_FAT=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_HTS221_DEBUG=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBM=y +CONFIG_LINE_MAX=64 +CONFIG_NET=y +CONFIG_NETDB_DNSCLIENT=y +CONFIG_NETDB_DNSSERVER_IPv4ADDR=0xc0a80101 +CONFIG_NETINIT_DRIPADDR=0xc0a80101 +CONFIG_NETINIT_IPADDR=0xc0a801e1 +CONFIG_NETINIT_NOMAC=y +CONFIG_NETUTILS_MQTTC=y +CONFIG_NETUTILS_TELNETD=y +CONFIG_NET_ICMP_SOCKET=y +CONFIG_NET_STATISTICS=y +CONFIG_NET_TCP=y +CONFIG_NET_TCP_NOTIFIER=y +CONFIG_NET_TCP_WRITE_BUFFERS=y +CONFIG_NET_UDP=y +CONFIG_NET_UDP_WRITE_BUFFERS=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_DISABLE_GET=y +CONFIG_NSH_DISABLE_IFUPDOWN=y +CONFIG_NSH_DISABLE_PUT=y +CONFIG_NSH_DISABLE_WGET=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=131072 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_READLINE_CMD_HISTORY=y +CONFIG_READLINE_TABCOMPLETION=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=192 +CONFIG_SCHED_WAITPID=y +CONFIG_SENSORS=y +CONFIG_SENSORS_HTS221=y +CONFIG_START_YEAR=2013 +CONFIG_STM32_CCMEXCLUDE=y +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_ETH100MBPS=y +CONFIG_STM32_ETHFD=y +CONFIG_STM32_ETHMAC=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_PWR=y +CONFIG_STM32_RMII_EXTCLK=y +CONFIG_STM32_USART6=y +CONFIG_SYSTEM_NETDB=y +CONFIG_SYSTEM_NSH=y +CONFIG_SYSTEM_PING=y +CONFIG_SYSTEM_TELNET_CLIENT=y +CONFIG_TASK_NAME_SIZE=32 +CONFIG_USART6_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f4/olimex-stm32-p407/configs/nsh/defconfig b/boards/arm/stm32f4/olimex-stm32-p407/configs/nsh/defconfig new file mode 100644 index 0000000000000..20dfd48105d7f --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-p407/configs/nsh/defconfig @@ -0,0 +1,55 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="olimex-stm32-p407" +CONFIG_ARCH_BOARD_OLIMEX_STM32P407=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F407ZG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_IRQBUTTONS=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_FAT_LCNAMES=y +CONFIG_FAT_LFN=y +CONFIG_FS_FAT=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_DISABLE_GET=y +CONFIG_NSH_DISABLE_IFUPDOWN=y +CONFIG_NSH_DISABLE_PUT=y +CONFIG_NSH_DISABLE_WGET=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=131072 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=192 +CONFIG_SCHED_WAITPID=y +CONFIG_START_YEAR=2013 +CONFIG_STM32_CCMEXCLUDE=y +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PWR=y +CONFIG_STM32_USART3=y +CONFIG_STM32_USBHOST=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=32 +CONFIG_USART3_SERIAL_CONSOLE=y +CONFIG_USBHOST_MSC=y diff --git a/boards/arm/stm32f4/olimex-stm32-p407/configs/zmodem/defconfig b/boards/arm/stm32f4/olimex-stm32-p407/configs/zmodem/defconfig new file mode 100644 index 0000000000000..d14e46b5dd711 --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-p407/configs/zmodem/defconfig @@ -0,0 +1,73 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="olimex-stm32-p407" +CONFIG_ARCH_BOARD_OLIMEX_STM32P407=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F407ZG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_FAT_LCNAMES=y +CONFIG_FAT_LFN=y +CONFIG_FS_FAT=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_I2C=y +CONFIG_I2C_POLLED=y +CONFIG_I2C_RESET=y +CONFIG_I2S=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_MM_REGIONS=2 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_WAITPID=y +CONFIG_SERIAL_IFLOWCONTROL_LOWER_WATERMARK=25 +CONFIG_SERIAL_IFLOWCONTROL_UPPER_WATERMARK=75 +CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS=y +CONFIG_SERIAL_TERMIOS=y +CONFIG_SPI=y +CONFIG_START_DAY=26 +CONFIG_START_MONTH=5 +CONFIG_STM32_CCMEXCLUDE=y +CONFIG_STM32_FLOWCONTROL_BROKEN=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PWR=y +CONFIG_STM32_USART3=y +CONFIG_STM32_USART6=y +CONFIG_STM32_USBHOST=y +CONFIG_SYSTEM_NSH=y +CONFIG_SYSTEM_ZMODEM=y +CONFIG_SYSTEM_ZMODEM_DEVNAME="/dev/ttyS1" +CONFIG_SYSTEM_ZMODEM_IFLOW=y +CONFIG_SYSTEM_ZMODEM_MOUNTPOINT="/mnt" +CONFIG_SYSTEM_ZMODEM_OFLOW=y +CONFIG_SYSTEM_ZMODEM_PKTBUFSIZE=1024 +CONFIG_USART3_BAUD=9600 +CONFIG_USART3_IFLOWCONTROL=y +CONFIG_USART3_OFLOWCONTROL=y +CONFIG_USART3_RXBUFSIZE=512 +CONFIG_USART6_SERIAL_CONSOLE=y +CONFIG_USBHOST_ISOC_DISABLE=y +CONFIG_USBHOST_MSC=y diff --git a/boards/arm/stm32f4/olimex-stm32-p407/include/board.h b/boards/arm/stm32f4/olimex-stm32-p407/include/board.h new file mode 100644 index 0000000000000..e1d157fa0dd95 --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-p407/include/board.h @@ -0,0 +1,453 @@ +/**************************************************************************** + * boards/arm/stm32f4/olimex-stm32-p407/include/board.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_STM32_OLIMEX_STM32_P407_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32_OLIMEX_STM32_P407_INCLUDE_BOARD_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#ifndef __ASSEMBLY__ +# include +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Clocking *****************************************************************/ + +/* HSI - 16 MHz RC factory-trimmed + * LSI - 32 KHz RC (30-60KHz, uncalibrated) + * HSE - On-board crystal frequency is 25MHz + * LSE - 32.768 kHz + */ + +#define STM32_BOARD_XTAL 25000000ul + +#define STM32_HSI_FREQUENCY 16000000ul +#define STM32_LSI_FREQUENCY 32000 +#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL +#define STM32_LSE_FREQUENCY 32768 + +/* Main PLL Configuration. + * + * PLL source is HSE + * PLL_VCO = (STM32_HSE_FREQUENCY / PLLM) * PLLN + * = (25,000,000 / 25) * 336 + * = 336,000,000 + * SYSCLK = PLL_VCO / PLLP + * = 336,000,000 / 2 = 168,000,000 + * USB OTG FS, SDIO and RNG Clock + * = PLL_VCO / PLLQ + * = 48,000,000 + */ + +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(25) +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(336) +#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_2 +#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(7) + +#define STM32_SYSCLK_FREQUENCY 168000000ul + +/* AHB clock (HCLK) is SYSCLK (168MHz) */ + +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY + +/* APB1 clock (PCLK1) is HCLK/4 (42MHz) */ + +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd4 /* PCLK1 = HCLK / 4 */ +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/4) + +/* Timers driven from APB1 will be twice PCLK1 */ + +#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) + +/* APB2 clock (PCLK2) is HCLK/2 (84MHz) */ + +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLKd2 /* PCLK2 = HCLK / 2 */ +#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/2) + +/* Timers driven from APB2 will be twice PCLK2 */ + +#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM9_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM10_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM11_CLKIN (2*STM32_PCLK2_FREQUENCY) + +/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx + * otherwise frequency is 2xAPBx. + * Note: TIM1,8 are on APB2, others on APB1 + */ + +#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM2_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM3_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM4_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM5_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM6_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM7_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY + +/* SDIO dividers. Note that slower clocking is required when DMA is disabled + * in order to avoid RX overrun/TX underrun errors due to delayed responses + * to service FIFOs in interrupt driven mode. These values have not been + * tuned!!! + * + * SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(118+2)=400 KHz + */ + +#define SDIO_INIT_CLKDIV (118 << SDIO_CLKCR_CLKDIV_SHIFT) + +/* DMA ON: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(1+2)=16 MHz + * DMA OFF: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(2+2)=12 MHz + */ + +#ifdef CONFIG_SDIO_DMA +# define SDIO_MMCXFR_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT) +#else +# define SDIO_MMCXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT) +#endif + +/* DMA ON: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(1+2)=16 MHz + * DMA OFF: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(2+2)=12 MHz + */ + +#ifdef CONFIG_SDIO_DMA +# define SDIO_SDXFR_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT) +#else +# define SDIO_SDXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT) +#endif + +/* LED definitions **********************************************************/ + +/* If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs + * in any way. The following definitions are used to access individual LEDs. + */ + +/* LED index values for use with board_userled() */ + +#define BOARD_LED1 0 +#define BOARD_LED2 1 +#define BOARD_LED3 2 +#define BOARD_LED4 3 +#define BOARD_NLEDS 4 + +#define BOARD_LED_GREEN1 BOARD_LED1 +#define BOARD_LED_YELLOW BOARD_LED2 +#define BOARD_LED_RED BOARD_LED3 +#define BOARD_LED_GREEN2 BOARD_LED4 + +/* LED bits for use with board_userled_all() */ + +#define BOARD_LED1_BIT (1 << BOARD_LED1) +#define BOARD_LED2_BIT (1 << BOARD_LED2) +#define BOARD_LED3_BIT (1 << BOARD_LED3) +#define BOARD_LED4_BIT (1 << BOARD_LED4) + +/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the 4 LEDs on + * board the Olimex STM32-P407. The following definitions describe how + * NuttX controls the LEDs: + */ + +#define LED_STARTED 0 /* LED1 */ +#define LED_HEAPALLOCATE 1 /* LED2 */ +#define LED_IRQSENABLED 2 /* LED1 + LED2 */ +#define LED_STACKCREATED 3 /* LED3 */ +#define LED_INIRQ 4 /* LED1 + LED3 */ +#define LED_SIGNAL 5 /* LED2 + LED3 */ +#define LED_ASSERTION 6 /* LED1 + LED2 + LED3 */ +#define LED_PANIC 7 /* N/C + N/C + N/C + LED4 */ + +/* Button definitions *******************************************************/ + +/* The Olimex STM32-P407 supports seven buttons: */ + +#define BUTTON_TAMPER 0 +#define BUTTON_WKUP 1 + +#ifdef CONFIG_INPUT_DJOYSTICK +# define NUM_BUTTONS 2 +#else +# define JOYSTICK_RIGHT 2 +# define JOYSTICK_UP 3 +# define JOYSTICK_LEFT 4 +# define JOYSTICK_DOWN 5 +# define JOYSTICK_CENTER 6 + +# define NUM_BUTTONS 7 +#endif + +#define BUTTON_TAMPER_BIT (1 << BUTTON_TAMPER) +#define BUTTON_WKUP_BIT (1 << BUTTON_WKUP) + +#ifndef CONFIG_INPUT_DJOYSTICK +# define JOYSTICK_RIGHT_BIT (1 << JOYSTICK_RIGHT) +# define JOYSTICK_UP_BIT (1 << JOYSTICK_UP) +# define JOYSTICK_LEFT_BIT (1 << JOYSTICK_LEFT) +# define JOYSTICK_DOWN_BIT (1 << JOYSTICK_DOWN) +# define JOYSTICK_CENTER_BIT (1 << JOYSTICK_CENTER) +#endif + +/* Alternate function pin selections ****************************************/ + +/* USART3: */ + +#define GPIO_USART3_RX (GPIO_USART3_RX_3|GPIO_SPEED_100MHz) /* PD9 */ +#define GPIO_USART3_TX (GPIO_USART3_TX_3|GPIO_SPEED_100MHz) /* PD8 */ +#define GPIO_USART3_CTS GPIO_USART3_CTS_2 /* PD11 */ +#define GPIO_USART3_RTS GPIO_USART3_RTS_2 /* PD12 */ + +/* UEXT USART3: This will redefine the above macros if enabled. */ + +#ifdef CONFIG_STM32_OLIMEXP407_UEXT_USART3 +# undef GPIO_USART3_RX (GPIO_USART3_RX_3|GPIO_SPEED_100MHz) +# undef GPIO_USART3_TX (GPIO_USART3_TX_3|GPIO_SPEED_100MHz) +# undef GPIO_USART3_CTS GPIO_USART3_CTS_2 +# undef GPIO_USART3_RTS GPIO_USART3_RTS_2 + +# define GPIO_USART3_RX (GPIO_USART3_RX_2|GPIO_SPEED_100MHz) /* PC11 */ +# define GPIO_USART3_TX (GPIO_USART3_TX_2|GPIO_SPEED_100MHz) /* PC10 */ +#endif + +/* USART6: */ + +#define GPIO_USART6_RX (GPIO_USART6_RX_2|GPIO_SPEED_100MHz) /* PG9 */ +#define GPIO_USART6_TX (GPIO_USART6_TX_1|GPIO_SPEED_100MHz) /* PC6 */ + +/* CAN: */ + +#define GPIO_CAN1_RX (GPIO_CAN1_RX_2|GPIO_SPEED_50MHz) /* PB8 */ +#define GPIO_CAN1_TX (GPIO_CAN1_TX_2|GPIO_SPEED_50MHz) /* PB9 */ + +/* microSD Connector: + * + * ----------------- ----------------- ------------------------ + * SD/MMC CONNECTOR BOARD GPIO CONFIGURATION(s + * PIN SIGNAL SIGNAL (no remapping) + * --- ------------- ----------------- ------------------------- + * 1 DAT2/RES SD_D2/USART3_TX/ PC10 GPIO_SDIO_D2 + * SPI3_SCK + * 2 CD/DAT3/CS SD_D3/USART3_RX/ PC11 GPIO_SDIO_D3 + * SPI3_MISO + * 3 CMD/DI SD_CMD PD2 GPIO_SDIO_CMD + * 4 VDD N/A N/A + * 5 CLK/SCLK SD_CLK/SPI3_MOSI PC12 GPIO_SDIO_CK + * 6 VSS N/A N/A + * 7 DAT0/D0 SD_D0/DCMI_D2 PC8 GPIO_SDIO_D0 + * 8 DAT1/RES SD_D1/DCMI_D3 PC9 GPIO_SDIO_D1 + * --- ------------- ----------------- ------------------------- + * + * NOTES: + * 1. DAT4, DAT4, DAT6, and DAT7 not connected. + * 2. There are no alternative pin selections. + * 3. There is no card detect (CD) GPIO input so we will not + * sense if there is a card in the SD slot or not. This will + * make usage very awkward. + */ + +/* Ethernet: + * + * - PA2 is ETH_MDIO + * - PC1 is ETH_MDC + * - PB5 is ETH_PPS_OUT - NC (not connected) + * - PA0 is ETH_MII_CRS - NC + * - PA3 is ETH_MII_COL - NC + * - PB10 is ETH_MII_RX_ER - NC + * - PB0 is ETH_MII_RXD2 - NC + * - PH7 is ETH_MII_RXD3 - NC + * - PC3 is ETH_MII_TX_CLK - NC + * - PC2 is ETH_MII_TXD2 - NC + * - PB8 is ETH_MII_TXD3 - NC + * - PA1 is ETH_MII_RX_CLK/ETH_RMII_REF_CLK + * - PA7 is ETH_MII_RX_DV/ETH_RMII_CRS_DV + * - PC4 is ETH_MII_RXD0/ETH_RMII_RXD0 + * - PC5 is ETH_MII_RXD1/ETH_RMII_RXD1 + * - PB11 is ETH_MII_TX_EN/ETH_RMII_TX_EN + * - PG13 is ETH_MII_TXD0/ETH_RMII_TXD0 + * - PG14 is ETH_MII_TXD1/ETH_RMII_TXD1 + */ + +#define GPIO_ETH_PPS_OUT (GPIO_ETH_PPS_OUT_1|GPIO_SPEED_100MHz) +#define GPIO_ETH_MII_CRS (GPIO_ETH_MII_CRS_1|GPIO_SPEED_100MHz) +#define GPIO_ETH_MII_COL (GPIO_ETH_MII_COL_1|GPIO_SPEED_100MHz) +#define GPIO_ETH_MII_RX_ER (GPIO_ETH_MII_RX_ER_1|GPIO_SPEED_100MHz) +#define GPIO_ETH_MII_RXD2 (GPIO_ETH_MII_RXD2_1|GPIO_SPEED_100MHz) +#define GPIO_ETH_MII_RXD3 (GPIO_ETH_MII_RXD3_1|GPIO_SPEED_100MHz) +#define GPIO_ETH_MII_TXD3 (GPIO_ETH_MII_TXD3_1|GPIO_SPEED_100MHz) +#define GPIO_ETH_MII_TX_EN (GPIO_ETH_MII_TX_EN_2|GPIO_SPEED_100MHz) +#define GPIO_ETH_MII_TXD0 (GPIO_ETH_MII_TXD0_2|GPIO_SPEED_100MHz) +#define GPIO_ETH_MII_TXD1 (GPIO_ETH_MII_TXD1_2|GPIO_SPEED_100MHz) +#define GPIO_ETH_RMII_TX_EN (GPIO_ETH_RMII_TX_EN_1|GPIO_SPEED_100MHz) +#define GPIO_ETH_RMII_TXD0 (GPIO_ETH_RMII_TXD0_2|GPIO_SPEED_100MHz) +#define GPIO_ETH_RMII_TXD1 (GPIO_ETH_RMII_TXD1_2|GPIO_SPEED_100MHz) + +/* DMA Channel/Stream Selections ********************************************/ + +/* Stream selections are arbitrary for now but might become important in + * the future if we set aside more DMA channels/streams. + * + * SDIO DMA + * DMAMAP_SDIO_1 = Channel 4, Stream 3 + * DMAMAP_SDIO_2 = Channel 4, Stream 6 + */ + +#define DMAMAP_SDIO DMAMAP_SDIO_1 + +/* USART6 + * + * DMAMAP_USART6_RX_1 = Channel 5, Stream1 + * DMAMAP_USART6_RX_2 = Channel 5, Stream2 + * DMAMAP_USART6_TX_1 = Channel 5, Stream6 + * DMAMAP_USART6_TX_2 = Channel 5, Stream7 + */ + +#define DMAMAP_USART6_RX DMAMAP_USART6_RX_1 +#define DMAMAP_USART6_TX DMAMAP_USART6_TX_1 + +/* DHTxx pin configuration */ + +#define GPIO_DHTXX_PIN (GPIO_PORTG|GPIO_PIN9) +#define GPIO_DHTXX_PIN_OUTPUT (GPIO_OUTPUT|GPIO_FLOAT|GPIO_SPEED_100MHz|GPIO_DHTXX_PIN) +#define GPIO_DHTXX_PIN_INPUT (GPIO_INPUT|GPIO_FLOAT|GPIO_DHTXX_PIN) + +#define BOARD_DHTXX_GPIO_INPUT GPIO_DHTXX_PIN_INPUT +#define BOARD_DHTXX_GPIO_OUTPUT GPIO_DHTXX_PIN_OUTPUT +#define BOARD_DHTXX_FRTIMER 1 /* Free-run timer 1 */ + +/* SPI3 - As present in the UEXT header */ + +#define GPIO_SPI3_MISO (GPIO_SPI3_MISO_2|GPIO_SPEED_50MHz) +#define GPIO_SPI3_MOSI (GPIO_SPI3_MOSI_2|GPIO_SPEED_50MHz) +#define GPIO_SPI3_SCK (GPIO_SPI3_SCK_2|GPIO_SPEED_50MHz) + +#define DMACHAN_SPI3_RX DMAMAP_SPI3_RX_1 +#define DMACHAN_SPI3_TX DMAMAP_SPI3_TX_1 + +/* I2S3 - CS4344 configuration uses I2S3 */ + +#define GPIO_I2S3_SD GPIO_I2S3_SD_1 +#define GPIO_I2S3_CK GPIO_I2S3_CK_1 +#define GPIO_I2S3_WS GPIO_I2S3_WS_2 +#define GPIO_I2S3_MCK GPIO_I2S3_MCK_0 + +#define DMACHAN_I2S3_RX DMAMAP_SPI3_RX_2 +#define DMACHAN_I2S3_TX DMAMAP_SPI3_TX_2 + +/* ETH MII/RMII inputs and MDC/MDIO (referenced by arch driver) */ + +#define GPIO_ETH_MDC (GPIO_ETH_MDC_0|GPIO_SPEED_100MHz) +#define GPIO_ETH_MDIO (GPIO_ETH_MDIO_0|GPIO_SPEED_100MHz) +#define GPIO_ETH_MII_RX_CLK (GPIO_ETH_MII_RX_CLK_0|GPIO_SPEED_100MHz) +#define GPIO_ETH_MII_RX_DV (GPIO_ETH_MII_RX_DV_0|GPIO_SPEED_100MHz) +#define GPIO_ETH_MII_RXD0 (GPIO_ETH_MII_RXD0_0|GPIO_SPEED_100MHz) +#define GPIO_ETH_MII_RXD1 (GPIO_ETH_MII_RXD1_0|GPIO_SPEED_100MHz) +#define GPIO_ETH_MII_TX_CLK (GPIO_ETH_MII_TX_CLK_0|GPIO_SPEED_100MHz) +#define GPIO_ETH_MII_TXD2 (GPIO_ETH_MII_TXD2_0|GPIO_SPEED_100MHz) +#define GPIO_ETH_RMII_CRS_DV (GPIO_ETH_RMII_CRS_DV_0|GPIO_SPEED_100MHz) +#define GPIO_ETH_RMII_REF_CLK (GPIO_ETH_RMII_REF_CLK_0|GPIO_SPEED_100MHz) +#define GPIO_ETH_RMII_RXD0 (GPIO_ETH_RMII_RXD0_0|GPIO_SPEED_100MHz) +#define GPIO_ETH_RMII_RXD1 (GPIO_ETH_RMII_RXD1_0|GPIO_SPEED_100MHz) +#define GPIO_MCO1 (GPIO_MCO1_0|GPIO_SPEED_100MHz) + +/* SDIO */ + +#define GPIO_SDIO_CK (GPIO_SDIO_CK_0|GPIO_SPEED_50MHz) +#define GPIO_SDIO_CMD (GPIO_SDIO_CMD_0|GPIO_SPEED_50MHz) +#define GPIO_SDIO_D0 (GPIO_SDIO_D0_0|GPIO_SPEED_50MHz) +#define GPIO_SDIO_D1 (GPIO_SDIO_D1_0|GPIO_SPEED_50MHz) +#define GPIO_SDIO_D2 (GPIO_SDIO_D2_0|GPIO_SPEED_50MHz) +#define GPIO_SDIO_D3 (GPIO_SDIO_D3_0|GPIO_SPEED_50MHz) + +/* USB OTG FS */ + +#define GPIO_OTGFS_DM (GPIO_OTGFS_DM_0|GPIO_SPEED_100MHz) +#define GPIO_OTGFS_DP (GPIO_OTGFS_DP_0|GPIO_SPEED_100MHz) +#define GPIO_OTGFS_ID (GPIO_OTGFS_ID_0|GPIO_SPEED_100MHz) +#define GPIO_OTGFS_SOF (GPIO_OTGFS_SOF_0|GPIO_SPEED_100MHz) + +/* FSMC SRAM */ + +#define GPIO_FSMC_A0 (GPIO_FSMC_A0_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A1 (GPIO_FSMC_A1_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A2 (GPIO_FSMC_A2_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A3 (GPIO_FSMC_A3_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A4 (GPIO_FSMC_A4_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A5 (GPIO_FSMC_A5_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A6 (GPIO_FSMC_A6_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A7 (GPIO_FSMC_A7_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A8 (GPIO_FSMC_A8_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A9 (GPIO_FSMC_A9_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A10 (GPIO_FSMC_A10_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A11 (GPIO_FSMC_A11_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A12 (GPIO_FSMC_A12_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A13 (GPIO_FSMC_A13_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A14 (GPIO_FSMC_A14_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A15 (GPIO_FSMC_A15_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A16 (GPIO_FSMC_A16_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A17 (GPIO_FSMC_A17_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A18 (GPIO_FSMC_A18_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A19 (GPIO_FSMC_A19_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A20 (GPIO_FSMC_A20_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A21 (GPIO_FSMC_A21_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A22 (GPIO_FSMC_A22_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A23 (GPIO_FSMC_A23_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A24 (GPIO_FSMC_A24_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A25 (GPIO_FSMC_A25_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_D0 (GPIO_FSMC_D0_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_D1 (GPIO_FSMC_D1_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_D2 (GPIO_FSMC_D2_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_D3 (GPIO_FSMC_D3_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_D4 (GPIO_FSMC_D4_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_D5 (GPIO_FSMC_D5_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_D6 (GPIO_FSMC_D6_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_D7 (GPIO_FSMC_D7_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_D8 (GPIO_FSMC_D8_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_D9 (GPIO_FSMC_D9_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_D10 (GPIO_FSMC_D10_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_D11 (GPIO_FSMC_D11_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_D12 (GPIO_FSMC_D12_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_D13 (GPIO_FSMC_D13_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_D14 (GPIO_FSMC_D14_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_D15 (GPIO_FSMC_D15_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_NOE (GPIO_FSMC_NOE_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_NWE (GPIO_FSMC_NWE_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_NE1 (GPIO_FSMC_NE1_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_NE2 (GPIO_FSMC_NE2_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_NE3 (GPIO_FSMC_NE3_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_NBL0 (GPIO_FSMC_NBL0_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_NBL1 (GPIO_FSMC_NBL1_0|GPIO_SPEED_100MHz) + +#endif /* __BOARDS_ARM_STM32_OLIMEX_STM32_P407_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32f4/olimex-stm32-p407/kernel/Makefile b/boards/arm/stm32f4/olimex-stm32-p407/kernel/Makefile new file mode 100644 index 0000000000000..e056219e025ae --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-p407/kernel/Makefile @@ -0,0 +1,94 @@ +############################################################################ +# boards/arm/stm32f4/olimex-stm32-p407/kernel/Makefile +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +# The entry point name (if none is provided in the .config file) + +CONFIG_INIT_ENTRYPOINT ?= user_start +ENTRYPT = $(patsubst "%",%,$(CONFIG_INIT_ENTRYPOINT)) + +# Get the paths to the libraries and the links script path in format that +# is appropriate for the host OS + +USER_LIBPATHS = $(addprefix -L,$(call CONVERT_PATH,$(addprefix $(TOPDIR)$(DELIM),$(dir $(USERLIBS))))) +USER_LDSCRIPT = -T $(call CONVERT_PATH,$(BOARD_DIR)$(DELIM)scripts$(DELIM)memory.ld) +USER_LDSCRIPT += -T $(call CONVERT_PATH,$(BOARD_DIR)$(DELIM)scripts$(DELIM)user-space.ld) +USER_HEXFILE += $(call CONVERT_PATH,$(TOPDIR)$(DELIM)nuttx_user.hex) +USER_SRECFILE += $(call CONVERT_PATH,$(TOPDIR)$(DELIM)nuttx_user.srec) +USER_BINFILE += $(call CONVERT_PATH,$(TOPDIR)$(DELIM)nuttx_user.bin) + +USER_LDFLAGS = --undefined=$(ENTRYPT) --entry=$(ENTRYPT) $(USER_LDSCRIPT) +USER_LDLIBS = $(patsubst lib%,-l%,$(basename $(notdir $(USERLIBS)))) +USER_LIBGCC = "${shell "$(CC)" $(ARCHCPUFLAGS) -print-libgcc-file-name}" + +# Source files + +CSRCS = stm32_userspace.c +COBJS = $(CSRCS:.c=$(OBJEXT)) +OBJS = $(COBJS) + +# Targets: + +all: $(TOPDIR)$(DELIM)nuttx_user.elf $(TOPDIR)$(DELIM)User.map +.PHONY: nuttx_user.elf depend clean distclean + +$(COBJS): %$(OBJEXT): %.c + $(call COMPILE, $<, $@) + +# Create the nuttx_user.elf file containing all of the user-mode code + +nuttx_user.elf: $(OBJS) + $(Q) $(LD) -o $@ $(USER_LDFLAGS) $(USER_LIBPATHS) $(OBJS) --start-group $(USER_LDLIBS) --end-group $(USER_LIBGCC) + +$(TOPDIR)$(DELIM)nuttx_user.elf: nuttx_user.elf + @echo "LD: nuttx_user.elf" + $(Q) cp -a nuttx_user.elf $(TOPDIR)$(DELIM)nuttx_user.elf +ifeq ($(CONFIG_INTELHEX_BINARY),y) + @echo "CP: nuttx_user.hex" + $(Q) $(OBJCOPY) $(OBJCOPYARGS) -O ihex nuttx_user.elf $(USER_HEXFILE) +endif +ifeq ($(CONFIG_MOTOROLA_SREC),y) + @echo "CP: nuttx_user.srec" + $(Q) $(OBJCOPY) $(OBJCOPYARGS) -O srec nuttx_user.elf $(USER_SRECFILE) +endif +ifeq ($(CONFIG_RAW_BINARY),y) + @echo "CP: nuttx_user.bin" + $(Q) $(OBJCOPY) $(OBJCOPYARGS) -O binary nuttx_user.elf $(USER_BINFILE) +endif + +$(TOPDIR)$(DELIM)User.map: nuttx_user.elf + @echo "MK: User.map" + $(Q) $(NM) nuttx_user.elf >$(TOPDIR)$(DELIM)User.map + $(Q) $(CROSSDEV)size nuttx_user.elf + +.depend: + +depend: .depend + +clean: + $(call DELFILE, nuttx_user.elf) + $(call DELFILE, "$(TOPDIR)$(DELIM)nuttx_user.*") + $(call DELFILE, "$(TOPDIR)$(DELIM)User.map") + $(call CLEAN) + +distclean: clean diff --git a/boards/arm/stm32f4/olimex-stm32-p407/kernel/stm32_userspace.c b/boards/arm/stm32f4/olimex-stm32-p407/kernel/stm32_userspace.c new file mode 100644 index 0000000000000..db4079eff62b9 --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-p407/kernel/stm32_userspace.c @@ -0,0 +1,111 @@ +/**************************************************************************** + * boards/arm/stm32f4/olimex-stm32-p407/kernel/stm32_userspace.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include +#include +#include +#include + +#if defined(CONFIG_BUILD_PROTECTED) && !defined(__KERNEL__) + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +#ifndef CONFIG_NUTTX_USERSPACE +# error "CONFIG_NUTTX_USERSPACE not defined" +#endif + +#if CONFIG_NUTTX_USERSPACE != 0x08020000 +# error "CONFIG_NUTTX_USERSPACE must be 0x08020000 to match memory.ld" +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static struct userspace_data_s g_userspace_data = +{ + .us_heap = &g_mmheap, +}; + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/* These 'addresses' of these values are setup by the linker script. */ + +extern uint8_t _stext[]; /* Start of .text */ +extern uint8_t _etext[]; /* End_1 of .text + .rodata */ +extern const uint8_t _eronly[]; /* End+1 of read only section (.text + .rodata) */ +extern uint8_t _sdata[]; /* Start of .data */ +extern uint8_t _edata[]; /* End+1 of .data */ +extern uint8_t _sbss[]; /* Start of .bss */ +extern uint8_t _ebss[]; /* End+1 of .bss */ + +const struct userspace_s userspace locate_data(".userspace") = +{ + /* General memory map */ + + .us_entrypoint = CONFIG_INIT_ENTRYPOINT, + .us_textstart = (uintptr_t)_stext, + .us_textend = (uintptr_t)_etext, + .us_datasource = (uintptr_t)_eronly, + .us_datastart = (uintptr_t)_sdata, + .us_dataend = (uintptr_t)_edata, + .us_bssstart = (uintptr_t)_sbss, + .us_bssend = (uintptr_t)_ebss, + + /* User data memory structure */ + + .us_data = &g_userspace_data, + + /* Task/thread startup routines */ + + .task_startup = nxtask_startup, + + /* Signal handler trampoline */ + + .signal_handler = up_signal_handler, + + /* User-space work queue support (declared in include/nuttx/wqueue.h) */ + +#ifdef CONFIG_LIBC_USRWORK + .work_usrstart = work_usrstart, +#endif +}; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +#endif /* CONFIG_BUILD_PROTECTED && !__KERNEL__ */ diff --git a/boards/arm/stm32f4/olimex-stm32-p407/scripts/Make.defs b/boards/arm/stm32f4/olimex-stm32-p407/scripts/Make.defs new file mode 100644 index 0000000000000..086726dad0f23 --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-p407/scripts/Make.defs @@ -0,0 +1,41 @@ +############################################################################ +# boards/arm/stm32f4/olimex-stm32-p407/scripts/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/.config +include $(TOPDIR)/tools/Config.mk +include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs + +LDSCRIPT = flash.ld +ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) + +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-gotoff.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32f4/olimex-stm32-p407/scripts/flash.ld b/boards/arm/stm32f4/olimex-stm32-p407/scripts/flash.ld new file mode 100644 index 0000000000000..577a9d8f2df75 --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-p407/scripts/flash.ld @@ -0,0 +1,124 @@ +/**************************************************************************** + * boards/arm/stm32f4/olimex-stm32-p407/scripts/flash.ld + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* The STM32F407VG has 1024Kb of FLASH beginning at address 0x0800:0000 and + * 192Kb of SRAM. SRAM is split up into three blocks: + * + * 1) 112Kb of SRAM beginning at address 0x2000:0000 + * 2) 16Kb of SRAM beginning at address 0x2001:c000 + * 3) 64Kb of CCM SRAM beginning at address 0x1000:0000 + * + * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 + * where the code expects to begin execution by jumping to the entry point in + * the 0x0800:0000 address range. + */ + +MEMORY +{ + flash (rx) : ORIGIN = 0x08000000, LENGTH = 1024K + sram (rwx) : ORIGIN = 0x20000000, LENGTH = 112K +} + +OUTPUT_ARCH(arm) +EXTERN(_vectors) +ENTRY(_stext) +SECTIONS +{ + .text : { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > flash + + .init_section : { + _sinit = ABSOLUTE(.); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) + _einit = ABSOLUTE(.); + } > flash + + .ARM.extab : { + *(.ARM.extab*) + } > flash + + __exidx_start = ABSOLUTE(.); + .ARM.exidx : { + *(.ARM.exidx*) + } > flash + __exidx_end = ABSOLUTE(.); + + .tdata : { + _stdata = ABSOLUTE(.); + *(.tdata .tdata.* .gnu.linkonce.td.*); + _etdata = ABSOLUTE(.); + } > flash + + .tbss : { + _stbss = ABSOLUTE(.); + *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); + _etbss = ABSOLUTE(.); + } > flash + + _eronly = ABSOLUTE(.); + + .data : { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > sram AT > flash + + .bss : { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(8); + _ebss = ABSOLUTE(.); + } > sram + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/stm32f4/olimex-stm32-p407/scripts/kernel-space.ld b/boards/arm/stm32f4/olimex-stm32-p407/scripts/kernel-space.ld new file mode 100644 index 0000000000000..8eab527b056ae --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-p407/scripts/kernel-space.ld @@ -0,0 +1,101 @@ +/**************************************************************************** + * boards/arm/stm32f4/olimex-stm32-p407/scripts/kernel-space.ld + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* NOTE: This depends on the memory.ld script having been included prior to + * this script. + */ + +OUTPUT_ARCH(arm) +EXTERN(_vectors) +ENTRY(_stext) + +SECTIONS +{ + .text : { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > kflash + + .init_section : { + _sinit = ABSOLUTE(.); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) + _einit = ABSOLUTE(.); + } > kflash + + .ARM.extab : { + *(.ARM.extab*) + } > kflash + + __exidx_start = ABSOLUTE(.); + .ARM.exidx : { + *(.ARM.exidx*) + } > kflash + + __exidx_end = ABSOLUTE(.); + + _eronly = ABSOLUTE(.); + + .data : { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > ksram AT > kflash + + .bss : { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(8); + _ebss = ABSOLUTE(.); + } > ksram + + /* Stabs debugging sections */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/stm32f4/olimex-stm32-p407/scripts/memory.ld b/boards/arm/stm32f4/olimex-stm32-p407/scripts/memory.ld new file mode 100644 index 0000000000000..a636ac8e99f0d --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-p407/scripts/memory.ld @@ -0,0 +1,100 @@ +/**************************************************************************** + * boards/arm/stm32f4/olimex-stm32-p407/scripts/memory.ld + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* The STM32F407VG has 1024Kb of FLASH beginning at address 0x0800:0000 and + * 192Kb of SRAM. SRAM is split up into three blocks: + * + * 1) 112KB of SRAM beginning at address 0x2000:0000 + * 2) 16KB of SRAM beginning at address 0x2001:c000 + * 3) 64KB of CCM SRAM beginning at address 0x1000:0000 + * + * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 + * where the code expects to begin execution by jumping to the entry point in + * the 0x0800:0000 address range. + * + * For MPU support, the kernel-mode NuttX section is assumed to be 128Kb of + * FLASH and 8Kb of SRAM. (See boards/stm32f4discovery/scripts/kernel-space.ld). + * Allowing additional memory permitis configuring debug instrumentation to + * be added to the kernel space without overflowing the partition. This could + * just as easily be set to 256Kb or even 512Kb. + * + * Alignment of the user space FLASH partition is also a critical factor: + * The user space FLASH partition will be spanned with a single region of + * size 2**n bytes. The alignment of the user-space region must be the same. + * As a consequence, as the user-space increases in size, the alignment + * requirement also increases. + * + * This alignment requirement means that the largest user space FLASH region + * you can have will be 512KB at it would have to be positioned at + * 0x08800000 (it cannot be positioned at 0x0800000 because vectors power-up + * reset vectors are places at the beginning of that range). If you change + * this address, don't forget to change the CONFIG_NUTTX_USERSPACE + * configuration setting to match and to modify the check in kernel/userspace.c. + * + * With 112Kb of SRAM a 64Kb user heap would seem possible but it is not in + * the current organization of SRAM memory (that could be changed with a + * little effort). The current ordering of SRAM is: (1) kernel .bss/.data, + * (2) user .bss/.data, (3) kernel heap (determined by CONFIG_MM_KERNEL_HEAPSIZE), + * and (4) the user heap. The maximum size of the user space heap is then + * limited to 32Kb beginning at address 0x20008000. + * + * Both of these alignment limitations could be reduced by using multiple + * regions to map the FLASH/SDRAM range or perhaps with some clever use of + * subregions or with multiple MPU regions per memory region. + * + * NOTE: The MPU is used in a mode where mappings are not required for + * kernel addresses and, hence, there are not alignment issues for those + * case. Only the user address spaces suffer from alignment requirements. + * However, in order to exploit this fact, we would still need to change + * the ordering of memory regions in SRAM. + * + * A detailed memory map for the 112KB SRAM region is as follows: + * + * 0x2000 0000: Kernel .data region. Typical size: 0.1KB + * ------ ---- Kernel .bss region. Typical size: 1.8KB + * 0x2000 0800: Kernel IDLE thread stack (approximate). Size is + * determined by CONFIG_IDLETHREAD_STACKSIZE and + * adjustments for alignment. Typical is 1KB. + * ------ ---- Padded to 8KB + * 0x2000 2000: User .data region. Size is variable. + * ------ ---- User .bss region Size is variable. + * 0x2000 4000: Beginning of kernel heap. Size determined by + * CONFIG_MM_KERNEL_HEAPSIZE which must be set to 16Kb. + * 0x2000 8000: Beginning of 32Kb user heap. + * 0x2001 0000: The remainder of SRAM is, unfortunately, wasted. + * 0x2001 c000: End+1 of CPU RAM + */ + +MEMORY +{ + /* 1024Kb FLASH */ + + kflash (rx) : ORIGIN = 0x08000000, LENGTH = 128K + uflash (rx) : ORIGIN = 0x08020000, LENGTH = 128K + xflash (rx) : ORIGIN = 0x08040000, LENGTH = 768K + + /* 112Kb of contiguous SRAM */ + + ksram (rwx) : ORIGIN = 0x20000000, LENGTH = 16K + usram (rwx) : ORIGIN = 0x20004000, LENGTH = 16K + xsram (rwx) : ORIGIN = 0x2000a000, LENGTH = 80K +} diff --git a/boards/arm/stm32f4/olimex-stm32-p407/scripts/user-space.ld b/boards/arm/stm32f4/olimex-stm32-p407/scripts/user-space.ld new file mode 100644 index 0000000000000..97ddb090ed1ac --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-p407/scripts/user-space.ld @@ -0,0 +1,114 @@ +/**************************************************************************** + * boards/arm/stm32f4/olimex-stm32-p407/scripts/user-space.ld + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* NOTE: This depends on the memory.ld script having been included prior to + * this script. + */ + +/* Make sure that the critical memory management functions are in user-space. + * the user heap memory manager will reside in user-space but be usable both + * by kernel- and user-space code + */ + +EXTERN(umm_initialize) +EXTERN(umm_addregion) + +EXTERN(malloc) +EXTERN(realloc) +EXTERN(zalloc) +EXTERN(free) + +OUTPUT_ARCH(arm) +SECTIONS +{ + .userspace : { + *(.userspace) + } > uflash + + .text : { + _stext = ABSOLUTE(.); + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > uflash + + .init_section : { + _sinit = ABSOLUTE(.); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) + _einit = ABSOLUTE(.); + } > uflash + + .ARM.extab : { + *(.ARM.extab*) + } > uflash + + __exidx_start = ABSOLUTE(.); + .ARM.exidx : { + *(.ARM.exidx*) + } > uflash + + __exidx_end = ABSOLUTE(.); + + _eronly = ABSOLUTE(.); + + .data : { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > usram AT > uflash + + .bss : { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(8); + _ebss = ABSOLUTE(.); + } > usram + + /* Stabs debugging sections */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/stm32f4/olimex-stm32-p407/src/CMakeLists.txt b/boards/arm/stm32f4/olimex-stm32-p407/src/CMakeLists.txt new file mode 100644 index 0000000000000..1ba829e0eeee5 --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-p407/src/CMakeLists.txt @@ -0,0 +1,61 @@ +# ############################################################################## +# boards/arm/stm32f4/olimex-stm32-p407/src/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(SRCS stm32_boot.c stm32_bringup.c stm32_spi.c stm32_st7735.c) + +if(CONFIG_ARCH_LEDS) + list(APPEND SRCS stm32_autoleds.c) +else() + list(APPEND SRCS stm32_userleds.c) +endif() + +if(CONFIG_ARCH_BUTTONS) + list(APPEND SRCS stm32_buttons.c) +endif() + +if(CONFIG_STM32_FSMC) + list(APPEND SRCS stm32_sram.c) +endif() + +if(CONFIG_STM32_OTGFS) + list(APPEND SRCS stm32_usb.c) +endif() + +if(CONFIG_ADC) + list(APPEND SRCS stm32_adc.c) +endif() + +if(CONFIG_STM32_CAN_CHARDRIVER) + list(APPEND SRCS stm32_can.c) +endif() + +if(CONFIG_AUDIO_CS4344) + list(APPEND SRCS stm32_cs4344.c) +endif() + +if(CONFIG_INPUT_DJOYSTICK) + list(APPEND SRCS stm32_djoystick.c) +endif() + +target_sources(board PRIVATE ${SRCS}) + +set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/flash.ld") diff --git a/boards/arm/stm32f4/olimex-stm32-p407/src/Make.defs b/boards/arm/stm32f4/olimex-stm32-p407/src/Make.defs new file mode 100644 index 0000000000000..490a60598470e --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-p407/src/Make.defs @@ -0,0 +1,63 @@ +############################################################################ +# boards/arm/stm32f4/olimex-stm32-p407/src/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +CSRCS = stm32_boot.c stm32_bringup.c stm32_spi.c stm32_st7735.c + +ifeq ($(CONFIG_ARCH_LEDS),y) + CSRCS += stm32_autoleds.c +else + CSRCS += stm32_userleds.c +endif + +ifeq ($(CONFIG_ARCH_BUTTONS),y) + CSRCS += stm32_buttons.c +endif + +ifeq ($(CONFIG_STM32_FSMC),y) + CSRCS += stm32_sram.c +endif + +ifeq ($(CONFIG_STM32_OTGFS),y) + CSRCS += stm32_usb.c +endif + +ifeq ($(CONFIG_ADC),y) + CSRCS += stm32_adc.c +endif + +ifeq ($(CONFIG_STM32_CAN_CHARDRIVER),y) + CSRCS += stm32_can.c +endif + +ifeq ($(CONFIG_AUDIO_CS4344),y) + CSRCS += stm32_cs4344.c +endif + +ifeq ($(CONFIG_INPUT_DJOYSTICK),y) + CSRCS += stm32_djoystick.c +endif + +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/olimex-stm32-p407/src/olimex-stm32-p407.h b/boards/arm/stm32f4/olimex-stm32-p407/src/olimex-stm32-p407.h similarity index 99% rename from boards/arm/stm32/olimex-stm32-p407/src/olimex-stm32-p407.h rename to boards/arm/stm32f4/olimex-stm32-p407/src/olimex-stm32-p407.h index 8847489d52044..a158aaf9af686 100644 --- a/boards/arm/stm32/olimex-stm32-p407/src/olimex-stm32-p407.h +++ b/boards/arm/stm32f4/olimex-stm32-p407/src/olimex-stm32-p407.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/olimex-stm32-p407/src/olimex-stm32-p407.h + * boards/arm/stm32f4/olimex-stm32-p407/src/olimex-stm32-p407.h * * SPDX-License-Identifier: Apache-2.0 * @@ -31,7 +31,7 @@ #include #include #include -#include +#include /**************************************************************************** * Pre-processor Definitions diff --git a/boards/arm/stm32f4/olimex-stm32-p407/src/stm32_adc.c b/boards/arm/stm32f4/olimex-stm32-p407/src/stm32_adc.c new file mode 100644 index 0000000000000..0278cefdd267c --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-p407/src/stm32_adc.c @@ -0,0 +1,156 @@ +/**************************************************************************** + * boards/arm/stm32f4/olimex-stm32-p407/src/stm32_adc.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include +#include + +#include "chip.h" +#include "stm32_adc.h" +#include "olimex-stm32-p407.h" + +#ifdef CONFIG_ADC + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* Up to 3 ADC interfaces are supported */ + +#if STM32_NADC < 3 +# undef CONFIG_STM32_ADC3 +#endif + +#if STM32_NADC < 2 +# undef CONFIG_STM32_ADC2 +#endif + +#if STM32_NADC < 1 +# undef CONFIG_STM32_ADC1 +#endif + +#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) || defined(CONFIG_STM32_ADC3) +#ifndef CONFIG_STM32_ADC1 +# warning "Channel information only available for ADC1" +#endif + +/* The number of ADC channels in the conversion list */ + +#define ADC1_NCHANNELS 1 + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* The Olimex STM32-P407 has a 10 Kohm potentiometer AN_TR connected to PC0 + * ADC123_IN10 + */ + +/* Identifying number of each ADC channel: Variable Resistor. */ + +#ifdef CONFIG_STM32_ADC1 +static const uint8_t g_chanlist[ADC1_NCHANNELS] = +{ + 10 +}; + +/* Configurations of pins used byte each ADC channels */ + +static const uint32_t g_pinlist[ADC1_NCHANNELS] = +{ + GPIO_ADC1_IN10 +}; +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_adc_setup + * + * Description: + * Initialize ADC and register the ADC driver. + * + ****************************************************************************/ + +int stm32_adc_setup(void) +{ +#ifdef CONFIG_STM32_ADC1 + static bool initialized = false; + struct adc_dev_s *adc; + int ret; + int i; + + /* Check if we have already initialized */ + + if (!initialized) + { + /* Configure the pins as analog inputs for the selected channels */ + + for (i = 0; i < ADC1_NCHANNELS; i++) + { + stm32_configgpio(g_pinlist[i]); + } + + /* Call stm32_adcinitialize() to get an instance of the ADC interface */ + + adc = stm32_adcinitialize(1, g_chanlist, ADC1_NCHANNELS); + if (adc == NULL) + { + aerr("ERROR: Failed to get ADC interface\n"); + return -ENODEV; + } + + /* Register the ADC driver at "/dev/adc0" */ + + ret = adc_register("/dev/adc0", adc); + if (ret < 0) + { + aerr("ERROR: adc_register failed: %d\n", ret); + return ret; + } + + /* Now we are initialized */ + + initialized = true; + } + + return OK; +#else + return -ENOSYS; +#endif +} + +#endif /* CONFIG_STM32_ADC1 || CONFIG_STM32_ADC2 || CONFIG_STM32_ADC3 */ +#endif /* CONFIG_ADC */ diff --git a/boards/arm/stm32f4/olimex-stm32-p407/src/stm32_autoleds.c b/boards/arm/stm32f4/olimex-stm32-p407/src/stm32_autoleds.c new file mode 100644 index 0000000000000..8ac94043160c2 --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-p407/src/stm32_autoleds.c @@ -0,0 +1,160 @@ +/**************************************************************************** + * boards/arm/stm32f4/olimex-stm32-p407/src/stm32_autoleds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "stm32.h" +#include "olimex-stm32-p407.h" + +#ifdef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* The following definitions map the encoded LED setting to GPIO settings */ + +#define LED_STARTED_BITS (BOARD_LED1_BIT) +#define LED_HEAPALLOCATE_BITS (BOARD_LED2_BIT) +#define LED_IRQSENABLED_BITS (BOARD_LED1_BIT | BOARD_LED2_BIT) +#define LED_STACKCREATED_BITS (BOARD_LED3_BIT) +#define LED_INIRQ_BITS (BOARD_LED1_BIT | BOARD_LED3_BIT) +#define LED_SIGNAL_BITS (BOARD_LED2_BIT | BOARD_LED3_BIT) +#define LED_ASSERTION_BITS (BOARD_LED1_BIT | BOARD_LED2_BIT | BOARD_LED3_BIT) +#define LED_PANIC_BITS (BOARD_LED4_BIT) + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static const unsigned int g_ledbits[8] = +{ + LED_STARTED_BITS, + LED_HEAPALLOCATE_BITS, + LED_IRQSENABLED_BITS, + LED_STACKCREATED_BITS, + LED_INIRQ_BITS, + LED_SIGNAL_BITS, + LED_ASSERTION_BITS, + LED_PANIC_BITS +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +static inline void led_clrbits(unsigned int clrbits) +{ + if ((clrbits & BOARD_LED1_BIT) != 0) + { + stm32_gpiowrite(GPIO_LED1, false); + } + + if ((clrbits & BOARD_LED2_BIT) != 0) + { + stm32_gpiowrite(GPIO_LED2, false); + } + + if ((clrbits & BOARD_LED3_BIT) != 0) + { + stm32_gpiowrite(GPIO_LED3, false); + } + + if ((clrbits & BOARD_LED4_BIT) != 0) + { + stm32_gpiowrite(GPIO_LED4, false); + } +} + +static inline void led_setbits(unsigned int setbits) +{ + if ((setbits & BOARD_LED1_BIT) != 0) + { + stm32_gpiowrite(GPIO_LED1, true); + } + + if ((setbits & BOARD_LED2_BIT) != 0) + { + stm32_gpiowrite(GPIO_LED2, true); + } + + if ((setbits & BOARD_LED3_BIT) != 0) + { + stm32_gpiowrite(GPIO_LED3, true); + } + + if ((setbits & BOARD_LED4_BIT) != 0) + { + stm32_gpiowrite(GPIO_LED4, true); + } +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_autoled_initialize + ****************************************************************************/ + +void board_autoled_initialize(void) +{ + /* Configure LED1-4 GPIOs for output */ + + stm32_configgpio(GPIO_LED1); + stm32_configgpio(GPIO_LED2); + stm32_configgpio(GPIO_LED3); + stm32_configgpio(GPIO_LED4); +} + +/**************************************************************************** + * Name: board_autoled_on + ****************************************************************************/ + +void board_autoled_on(int led) +{ + led_clrbits(BOARD_LED1_BIT | BOARD_LED2_BIT | + BOARD_LED3_BIT | BOARD_LED4_BIT); + led_setbits(g_ledbits[led]); +} + +/**************************************************************************** + * Name: board_autoled_off + ****************************************************************************/ + +void board_autoled_off(int led) +{ + led_clrbits(g_ledbits[led]); +} + +#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32f4/olimex-stm32-p407/src/stm32_boot.c b/boards/arm/stm32f4/olimex-stm32-p407/src/stm32_boot.c new file mode 100644 index 0000000000000..96f423fd65d3a --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-p407/src/stm32_boot.c @@ -0,0 +1,116 @@ +/**************************************************************************** + * boards/arm/stm32f4/olimex-stm32-p407/src/stm32_boot.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include +#include +#include + +#include "olimex-stm32-p407.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_boardinitialize + * + * Description: + * All STM32 architectures must provide the following entry point. + * This entry point is called early in the initialization -- after all + * memory has been configured and mapped but before any devices have been + * initialized. + * + ****************************************************************************/ + +void stm32_boardinitialize(void) +{ +#ifdef CONFIG_STM32_FSMC + /* If the FSMC is enabled, then enable SRAM access */ + + stm32_stram_configure(); +#endif + +#ifdef CONFIG_STM32_OTGFS + /* Initialize USB if the 1) OTG FS controller is in the configuration + * and 2) disabled, and 3) the weak function stm32_usb_configure() has been + * brought into the build. Presumably either CONFIG_USBDEV or + * CONFIG_USBHOST is also selected. + */ + + stm32_usb_configure(); +#endif + + /* Configure on-board LEDs if LED support has been selected. */ + +#ifdef CONFIG_ARCH_LEDS + board_autoled_initialize(); +#endif + + /* Configure on-board BUTTONs if BUTTON support has been selected. */ + +#ifdef CONFIG_ARCH_BUTTONS + board_button_initialize(); +#endif + + /* Configure SPI chip selects if 1) SPI is not disabled, and 2) the weak + * function stm32_spidev_initialize() has been brought into the link. + */ + +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) ||\ + defined(CONFIG_STM32_SPI3) + if (stm32_spidev_initialize) + { + stm32_spidev_initialize(); + } +#endif +} + +/**************************************************************************** + * Name: board_late_initialize + * + * Description: + * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_late_initialize(). board_late_initialize() will + * be called immediately after up_initialize() is called and just before + * the initial application is started. This additional initialization + * phase may be used, for example, to initialize board-specific device + * drivers. + * + ****************************************************************************/ + +#ifdef CONFIG_BOARD_LATE_INITIALIZE +void board_late_initialize(void) +{ + /* Perform board-specific initialization here if so configured */ + + stm32_bringup(); +} +#endif diff --git a/boards/arm/stm32f4/olimex-stm32-p407/src/stm32_bringup.c b/boards/arm/stm32f4/olimex-stm32-p407/src/stm32_bringup.c new file mode 100644 index 0000000000000..23aef9764d545 --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-p407/src/stm32_bringup.c @@ -0,0 +1,219 @@ +/**************************************************************************** + * boards/arm/stm32f4/olimex-stm32-p407/src/stm32_bringup.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include +#include +#include + +#ifdef CONFIG_USBMONITOR +# include +#endif + +#ifdef CONFIG_MODULE +# include +#endif + +#ifdef CONFIG_STM32_OTGFS +# include "stm32_usbhost.h" +#endif + +#include "stm32.h" +#include "olimex-stm32-p407.h" + +#ifdef CONFIG_SENSORS_DHTXX +#include "stm32_dhtxx.h" +#endif + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#ifdef HAVE_MODSYMS +extern const struct symtab_s MODSYMS_SYMTAB_ARRAY[]; +extern const int MODSYMS_NSYMBOLS_VAR; +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_bringup + * + * Description: + * Perform architecture-specific initialization + * + * CONFIG_BOARD_LATE_INITIALIZE=y : + * Called from board_late_initialize(). + * + ****************************************************************************/ + +int stm32_bringup(void) +{ +#ifdef HAVE_MMCSD + struct sdio_dev_s *sdio; +#endif + int ret; + +#ifdef CONFIG_FS_PROCFS + /* Mount the procfs file system */ + + ret = nx_mount(NULL, "/proc", "procfs", 0, NULL); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to mount procfs at /proc: %d\n", ret); + } +#endif + +#ifdef HAVE_MODSYMS + /* Install the module symbol table */ + + libelf_setsymtab(MODSYMS_SYMTAB_ARRAY, MODSYMS_NSYMBOLS_VAR); +#endif + +#ifdef HAVE_MMCSD + /* Mount the SDIO-based MMC/SD block driver */ + + /* First, get an instance of the SDIO interface */ + + sdio = sdio_initialize(MMCSD_SLOTNO); + if (!sdio) + { + syslog(LOG_ERR, + "ERROR: Failed to initialize SDIO slot %d\n", + MMCSD_SLOTNO); + return -ENODEV; + } + + /* Now bind the SDIO interface to the MMC/SD driver */ + + ret = mmcsd_slotinitialize(MMCSD_MINOR, sdio); + if (ret != OK) + { + syslog(LOG_ERR, + "ERROR: Failed to bind SDIO to the MMC/SD driver: %d\n", + ret); + return ret; + } + + /* Then let's guess and say that there is a card in the slot. The Olimex + * STM32 P407 does not support a GPIO to detect if there is a card in + * the slot so we are reduced to guessing. + */ + + sdio_mediachange(sdio, true); +#endif + +#ifdef CONFIG_STM32_CAN_CHARDRIVER + /* Initialize CAN and register the CAN driver. */ + + ret = stm32_can_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_can_setup failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_ADC + /* Initialize ADC and register the ADC driver. */ + + ret = stm32_adc_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_adc_setup failed: %d\n", ret); + } +#endif + +#ifdef HAVE_USBHOST + /* Initialize USB host operation. stm32_usbhost_setup() starts a thread + * will monitor for USB connection and disconnection events. + */ + + ret = stm32_usbhost_setup(); + if (ret != OK) + { + syslog(LOG_ERR, "ERROR: Failed to initialize USB host: %d\n", ret); + return ret; + } +#endif + +#ifdef HAVE_USBMONITOR + /* Start the USB Monitor */ + + ret = usbmonitor_start(); + if (ret != OK) + { + syslog(LOG_ERR, "ERROR: Failed to start USB monitor: %d\n", ret); + } +#endif + +#ifdef CONFIG_INPUT_BUTTONS + /* Register the BUTTON driver */ + + ret = btn_lower_initialize("/dev/buttons"); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: btn_lower_initialize() failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_SENSORS_DHTXX + ret = board_dhtxx_initialize(0); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_dhtxx_initialize() failed: %d\n", ret); + } +#endif + +#ifdef HAVE_CS4344 + /* Configure CS4344 audio */ + + ret = stm32_cs4344_initialize(1); + if (ret != OK) + { + syslog(LOG_ERR, "Failed to initialize CS4344 audio: %d\n", ret); + } +#endif + +#ifdef CONFIG_INPUT_DJOYSTICK + ret = stm32_djoy_initialize(); + if (ret != OK) + { + syslog(LOG_ERR, "Failed to register djoystick driver: %d\n", ret); + } +#endif + + UNUSED(ret); + return OK; +} diff --git a/boards/arm/stm32f4/olimex-stm32-p407/src/stm32_buttons.c b/boards/arm/stm32f4/olimex-stm32-p407/src/stm32_buttons.c new file mode 100644 index 0000000000000..7e53c997deead --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-p407/src/stm32_buttons.c @@ -0,0 +1,188 @@ +/**************************************************************************** + * boards/arm/stm32f4/olimex-stm32-p407/src/stm32_buttons.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include +#include + +#include "stm32_gpio.h" + +#include "olimex-stm32-p407.h" + +#ifdef CONFIG_ARCH_BUTTONS + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* Pin configuration for each STM32F4 Discovery button. This array is indexed + * by the BUTTON_* definitions in board.h + */ + +static const uint32_t g_buttons[NUM_BUTTONS] = +{ + GPIO_BTN_TAMPER, + GPIO_BTN_WKUP, + + /* The Joystick is treated like the other buttons unless + * CONFIG_INPUT_DJOYSTICK is defined, then it is assumed that they should + * be used by the discrete joystick driver. + */ + +#ifndef CONFIG_INPUT_DJOYSTICK + GPIO_JOY_RIGHT, + GPIO_JOY_UP, + GPIO_JOY_LEFT, + GPIO_JOY_DOWN, + GPIO_JOY_CENTER +#endif +}; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_button_initialize + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. + * + ****************************************************************************/ + +uint32_t board_button_initialize(void) +{ + int i; + + /* Configure the GPIO pins as inputs. NOTE that EXTI interrupts are + * configured for all pins. + */ + + for (i = 0; i < NUM_BUTTONS; i++) + { + stm32_configgpio(g_buttons[i]); + } + + return NUM_BUTTONS; +} + +/**************************************************************************** + * Name: board_buttons + ****************************************************************************/ + +uint32_t board_buttons(void) +{ + uint32_t ret = 0; + + /* Check that state of each key */ + + if (!stm32_gpioread(g_buttons[BUTTON_TAMPER])) + { + ret |= BUTTON_TAMPER_BIT; + } + + if (stm32_gpioread(g_buttons[BUTTON_WKUP])) + { + ret |= BUTTON_WKUP_BIT; + } + +#ifndef CONFIG_INPUT_DJOYSTICK + if (stm32_gpioread(g_buttons[JOYSTICK_RIGHT])) + { + ret |= JOYSTICK_RIGHT_BIT; + } + + if (stm32_gpioread(g_buttons[JOYSTICK_UP])) + { + ret |= JOYSTICK_UP_BIT; + } + + if (stm32_gpioread(g_buttons[JOYSTICK_LEFT])) + { + ret |= JOYSTICK_LEFT_BIT; + } + + if (stm32_gpioread(g_buttons[JOYSTICK_DOWN])) + { + ret |= JOYSTICK_DOWN_BIT; + } + + if (stm32_gpioread(g_buttons[JOYSTICK_CENTER])) + { + ret |= JOYSTICK_CENTER_BIT; + } +#endif + + return ret; +} + +/**************************************************************************** + * Button support. + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. + * + * After board_button_initialize() has been called, board_buttons() may be + * called to collect the state of all buttons. board_buttons() returns an + * 32-bit bit set with each bit associated with a button. See the + * BUTTON_*_BIT definitions in board.h for the meaning of each bit. + * + * board_button_irq() may be called to register an interrupt handler that + * will be called when a button is depressed or released. The ID value is a + * button enumeration value that uniquely identifies a button resource. See + * the BUTTON_* definitions in board.h for the meaning of enumeration + * value. + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_IRQBUTTONS +int board_button_irq(int id, xcpt_t irqhandler, void *arg) +{ + int ret = -EINVAL; + + /* The following should be atomic */ + + if (id >= MIN_IRQBUTTON && id <= MAX_IRQBUTTON) + { + ret = stm32_gpiosetevent(g_buttons[id], true, true, true, + irqhandler, arg); + } + + return ret; +} +#endif +#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/stm32f4/olimex-stm32-p407/src/stm32_can.c b/boards/arm/stm32f4/olimex-stm32-p407/src/stm32_can.c new file mode 100644 index 0000000000000..abb3d539c7289 --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-p407/src/stm32_can.c @@ -0,0 +1,100 @@ +/**************************************************************************** + * boards/arm/stm32f4/olimex-stm32-p407/src/stm32_can.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include + +#include "stm32.h" +#include "stm32_can.h" +#include "olimex-stm32-p407.h" + +#ifdef CONFIG_CAN + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +#if defined(CONFIG_STM32_CAN1) && defined(CONFIG_STM32_CAN2) +# warning "Both CAN1 and CAN2 are enabled. Only CAN1 is connected." +# undef CONFIG_STM32_CAN2 +#endif + +#ifdef CONFIG_STM32_CAN1 +# define CAN_PORT 1 +#else +# define CAN_PORT 2 +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_can_setup + * + * Description: + * Initialize CAN and register the CAN device + * + ****************************************************************************/ + +int stm32_can_setup(void) +{ +#if defined(CONFIG_STM32_CAN1) || defined(CONFIG_STM32_CAN2) + struct can_dev_s *can; + int ret; + + /* Call stm32_caninitialize() to get an instance of the CAN interface */ + + can = stm32_caninitialize(CAN_PORT); + if (can == NULL) + { + canerr("ERROR: Failed to get CAN interface\n"); + return -ENODEV; + } + + /* Register the CAN driver at "/dev/can0" */ + + ret = can_register("/dev/can0", can); + if (ret < 0) + { + canerr("ERROR: can_register failed: %d\n", ret); + return ret; + } + + return OK; +#else + return -ENODEV; +#endif +} + +#endif /* CONFIG_CAN */ diff --git a/boards/arm/stm32f4/olimex-stm32-p407/src/stm32_cs4344.c b/boards/arm/stm32f4/olimex-stm32-p407/src/stm32_cs4344.c new file mode 100644 index 0000000000000..caebdff338f3b --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-p407/src/stm32_cs4344.c @@ -0,0 +1,172 @@ +/**************************************************************************** + * boards/arm/stm32f4/olimex-stm32-p407/src/stm32_cs4344.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include + +#include "stm32.h" +#include "olimex-stm32-p407.h" + +#ifdef HAVE_CS4344 + +/**************************************************************************** + * Pre-Processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_cs4344_initialize + * + * Description: + * This function is called by platform-specific, setup logic to configure + * and register the CS4344 device. This function will register the driver + * as /dev/audio/pcm[x] where x is determined by the minor device number. + * + * Input Parameters: + * minor - The input device minor number + * + * Returned Value: + * Zero is returned on success. Otherwise, a negated errno value is + * returned to indicate the nature of the failure. + * + ****************************************************************************/ + +int stm32_cs4344_initialize(int minor) +{ + struct audio_lowerhalf_s *cs4344; + struct audio_lowerhalf_s *pcm; + struct i2s_dev_s *i2s; + static bool initialized = false; + char devname[12]; + int ret; + + audinfo("minor %d\n", minor); + DEBUGASSERT(minor >= 0 && minor <= 25); + + /* Have we already initialized? Since we never uninitialize we must + * prevent multiple initializations. This is necessary, for example, + * when the touchscreen example is used as a built-in application in + * NSH and can be called numerous time. It will attempt to initialize + * each time. + */ + + if (!initialized) + { + /* Get an instance of the I2S interface for the CS4344 data channel */ + + i2s = stm32_i2sbus_initialize(CS4344_I2S_BUS); + if (!i2s) + { + auderr("ERROR: Failed to initialize I2S%d\n", CS4344_I2S_BUS); + ret = -ENODEV; + goto errout; + } + + /* Now we can use this I2S interface to initialize the CS4344 which + * will return an audio interface. + */ + + cs4344 = cs4344_initialize(i2s); + if (!cs4344) + { + auderr("ERROR: Failed to initialize the CS4344\n"); + ret = -ENODEV; + goto errout; + } + + /* No we can embed the CS4344/I2S conglomerate into a PCM decoder + * instance so that we will have a PCM front end for the CS4344 + * driver. + */ + + pcm = pcm_decode_initialize(cs4344); + if (!pcm) + { + auderr("ERROR: Failed create the PCM decoder\n"); + ret = -ENODEV; + goto errout; + } + + /* Create a device name */ + + snprintf(devname, sizeof(devname), "pcm%d", minor); + + /* Finally, we can register the PCM/CS4344/I2S audio device. + * + * Is anyone young enough to remember Rube Goldberg? + */ + + ret = audio_register(devname, pcm); + if (ret < 0) + { + auderr("ERROR: Failed to register /dev/%s device: %d\n", + devname, ret); + goto errout; + } + + /* Now we are initialized */ + + initialized = true; + } + + return OK; + +errout: + return ret; +} + +#endif /* HAVE_CS4344 */ diff --git a/boards/arm/stm32f4/olimex-stm32-p407/src/stm32_djoystick.c b/boards/arm/stm32f4/olimex-stm32-p407/src/stm32_djoystick.c new file mode 100644 index 0000000000000..191399950d24f --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-p407/src/stm32_djoystick.c @@ -0,0 +1,299 @@ +/**************************************************************************** + * boards/arm/stm32f4/olimex-stm32-p407/src/stm32_djoystick.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include +#include +#include + +#include "stm32_gpio.h" +#include "olimex-stm32-p407.h" + +#ifdef CONFIG_INPUT_DJOYSTICK + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Number of Joystick discretes */ + +#define DJOY_NGPIOS 5 + +/* Bitset of supported Joystick discretes */ + +#define DJOY_SUPPORTED (DJOY_UP_BIT | DJOY_DOWN_BIT | DJOY_LEFT_BIT | \ + DJOY_RIGHT_BIT | DJOY_BUTTON_SELECT_BIT) + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +static djoy_buttonset_t + djoy_supported(const struct djoy_lowerhalf_s *lower); +static djoy_buttonset_t + djoy_sample(const struct djoy_lowerhalf_s *lower); +static void djoy_enable(const struct djoy_lowerhalf_s *lower, + djoy_buttonset_t press, djoy_buttonset_t release, + djoy_interrupt_t handler, void *arg); + +static void djoy_disable(void); +static int djoy_interrupt(int irq, void *context, void *arg); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* Pin configuration for each Olimex-P407 joystick "button." Index using + * DJOY_* definitions in include/nuttx/input/djoystick.h. + */ + +static const uint16_t g_joygpio[DJOY_NGPIOS] = +{ + GPIO_JOY_UP, GPIO_JOY_DOWN, GPIO_JOY_LEFT, GPIO_JOY_RIGHT, GPIO_JOY_CENTER +}; + +/* Current interrupt handler and argument */ + +static djoy_interrupt_t g_djoyhandler; +static void *g_djoyarg; + +/* This is the discrete joystick lower half driver interface */ + +static const struct djoy_lowerhalf_s g_djoylower = +{ + .dl_supported = djoy_supported, + .dl_sample = djoy_sample, + .dl_enable = djoy_enable, +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: djoy_supported + * + * Description: + * Return the set of buttons supported on the discrete joystick device + * + ****************************************************************************/ + +static djoy_buttonset_t + djoy_supported(const struct djoy_lowerhalf_s *lower) +{ + iinfo("Supported: %02x\n", DJOY_SUPPORTED); + return (djoy_buttonset_t)DJOY_SUPPORTED; +} + +/**************************************************************************** + * Name: djoy_sample + * + * Description: + * Return the current state of all discrete joystick buttons + * + ****************************************************************************/ + +static djoy_buttonset_t djoy_sample(const struct djoy_lowerhalf_s *lower) +{ + djoy_buttonset_t ret = 0; + int i; + + /* Read each joystick GPIO value */ + + for (i = 0; i < DJOY_NGPIOS; i++) + { + bool released = stm32_gpioread(g_joygpio[i]); + if (!released) + { + ret |= (1 << i); + } + } + + iinfo("Retuning: %02x\n", DJOY_SUPPORTED); + return ret; +} + +/**************************************************************************** + * Name: djoy_enable + * + * Description: + * Enable interrupts on the selected set of joystick buttons. And empty + * set will disable all interrupts. + * + ****************************************************************************/ + +static void djoy_enable(const struct djoy_lowerhalf_s *lower, + djoy_buttonset_t press, djoy_buttonset_t release, + djoy_interrupt_t handler, void *arg) +{ + irqstate_t flags; + djoy_buttonset_t either = press | release; + djoy_buttonset_t bit; + bool rising; + bool falling; + int i; + + /* Start with all interrupts disabled */ + + flags = enter_critical_section(); + djoy_disable(); + + iinfo("press: %02x release: %02x handler: %p arg: %p\n", + press, release, handler, arg); + + /* If no events are indicated or if no handler is provided, then this + * must really be a request to disable interrupts. + */ + + if (either && handler) + { + /* Save the new the handler and argument */ + + g_djoyhandler = handler; + g_djoyarg = arg; + + /* Check each GPIO. */ + + for (i = 0; i < DJOY_NGPIOS; i++) + { + /* Enable interrupts on each pin that has either a press or + * release event associated with it. + */ + + bit = (1 << i); + if ((either & bit) != 0) + { + /* Active low so a press corresponds to a falling edge and + * a release corresponds to a rising edge. + */ + + falling = ((press & bit) != 0); + rising = ((release & bit) != 0); + + iinfo("GPIO %d: rising: %d falling: %d\n", + i, rising, falling); + + stm32_gpiosetevent(g_joygpio[i], rising, falling, + true, djoy_interrupt, NULL); + } + } + } + + leave_critical_section(flags); +} + +/**************************************************************************** + * Name: djoy_disable + * + * Description: + * Disable all joystick interrupts + * + ****************************************************************************/ + +static void djoy_disable(void) +{ + irqstate_t flags; + int i; + + /* Disable each joystick interrupt */ + + flags = enter_critical_section(); + for (i = 0; i < DJOY_NGPIOS; i++) + { + stm32_gpiosetevent(g_joygpio[i], false, false, false, NULL, NULL); + } + + leave_critical_section(flags); + + /* Nullify the handler and argument */ + + g_djoyhandler = NULL; + g_djoyarg = NULL; +} + +/**************************************************************************** + * Name: djoy_interrupt + * + * Description: + * Discrete joystick interrupt handler + * + ****************************************************************************/ + +static int djoy_interrupt(int irq, void *context, void *arg) +{ + DEBUGASSERT(g_djoyhandler); + if (g_djoyhandler) + { + g_djoyhandler(&g_djoylower, g_djoyarg); + } + + return OK; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_djoy_initialize + * + * Description: + * Initialize and register the discrete joystick driver + * + ****************************************************************************/ + +int stm32_djoy_initialize(void) +{ + int i; + + /* Configure the GPIO pins as inputs. NOTE: This is unnecessary for + * interrupting pins since it will also be done by stm32_gpiosetevent(). + */ + + for (i = 0; i < DJOY_NGPIOS; i++) + { + stm32_configgpio(g_joygpio[i]); + } + + /* Make sure that all interrupts are disabled */ + + djoy_disable(); + + /* Register the joystick device as /dev/djoy0 */ + + return djoy_register("/dev/djoy0", &g_djoylower); +} + +#endif /* CONFIG_INPUT_DJOYSTICK */ diff --git a/boards/arm/stm32f4/olimex-stm32-p407/src/stm32_spi.c b/boards/arm/stm32f4/olimex-stm32-p407/src/stm32_spi.c new file mode 100644 index 0000000000000..d7777549c85b6 --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-p407/src/stm32_spi.c @@ -0,0 +1,197 @@ +/**************************************************************************** + * boards/arm/stm32f4/olimex-stm32-p407/src/stm32_spi.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include + +#include "arm_internal.h" +#include "chip.h" +#include "stm32.h" + +#include "olimex-stm32-p407.h" + +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) ||\ + defined(CONFIG_STM32_SPI3) + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_spidev_initialize + * + * Description: + * Called to configure SPI chip select GPIO pins for the olimex + * board. + * + ****************************************************************************/ + +void weak_function stm32_spidev_initialize(void) +{ + stm32_configgpio(GPIO_ST7735_CS); +} + +/**************************************************************************** + * Name: stm32_spi1/2/3select and stm32_spi1/2/3status + * + * Description: + * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status + * must be provided by board-specific logic. They are implementations of + * the select and status methods of the SPI interface defined by struct + * spi_ops_s (see include/nuttx/spi/spi.h). All other methods (including + * stm32_spibus_initialize()) are provided by common STM32 logic. To use + * this common SPI logic on your board: + * + * 1. Provide logic in stm32_boardinitialize() to configure SPI chip select + * pins. + * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() functions + * in your board-specific logic. These functions will perform chip + * selection and status operations using GPIOs in the way your board + * is configured. + * 3. Add a call to stm32_spibus_initialize() in your low level application + * initialization logic + * 4. The handle returned by stm32_spibus_initialize() may then be used to + * bind the SPI driver to higher level logic (e.g., calling + * mmcsd_spislotinitialize(), for example, will bind the SPI driver to + * the SPI MMC/SD driver). + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_SPI1 +void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, + bool selected) +{ + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); +} + +uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} +#endif + +#ifdef CONFIG_STM32_SPI2 +void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid, + bool selected) +{ + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); +} + +uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} +#endif + +#ifdef CONFIG_STM32_SPI3 +void stm32_spi3select(struct spi_dev_s *dev, uint32_t devid, + bool selected) +{ + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); + +#ifdef CONFIG_LCD_ST7735 + if (devid == SPIDEV_DISPLAY(0)) + { + stm32_gpiowrite(GPIO_ST7735_CS, !selected); + } +#endif +} + +uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} +#endif + +/**************************************************************************** + * Name: stm32_spi1cmddata + * + * Description: + * Set or clear the SH1101A A0 or SD1306 D/C n bit to select data (true) + * or command (false). This function must be provided by platform-specific + * logic. This is an implementation of the cmddata method of the SPI + * interface defined by struct spi_ops_s (see include/nuttx/spi/spi.h). + * + * Input Parameters: + * + * spi - SPI device that controls the bus the device that requires the CMD/ + * DATA selection. + * devid - If there are multiple devices on the bus, this selects which one + * to select cmd or data. NOTE: This design restricts, for example, + * one one SPI display per SPI bus. + * cmd - true: select command; false: select data + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_SPI_CMDDATA +#ifdef CONFIG_STM32_SPI1 +int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) +{ + return -ENODEV; +} +#endif + +#ifdef CONFIG_STM32_SPI2 +int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) +{ + return -ENODEV; +} +#endif + +#ifdef CONFIG_STM32_SPI3 +int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) +{ + /* This is the Data/Command control pad which determines whether the + * data bits are data or a command. + */ + +#ifdef CONFIG_LCD_ST7735 + if (devid == SPIDEV_DISPLAY(0)) + { + stm32_gpiowrite(GPIO_ST7735_AO, !cmd); + return OK; + } +#endif + + return -ENODEV; +} +#endif +#endif /* CONFIG_SPI_CMDDATA */ + +#endif /* CONFIG_STM32_SPI1 || CONFIG_STM32_SPI2 */ diff --git a/boards/arm/stm32/olimex-stm32-p407/src/stm32_sram.c b/boards/arm/stm32f4/olimex-stm32-p407/src/stm32_sram.c similarity index 99% rename from boards/arm/stm32/olimex-stm32-p407/src/stm32_sram.c rename to boards/arm/stm32f4/olimex-stm32-p407/src/stm32_sram.c index d2d7a1c260822..0e3a7159be359 100644 --- a/boards/arm/stm32/olimex-stm32-p407/src/stm32_sram.c +++ b/boards/arm/stm32f4/olimex-stm32-p407/src/stm32_sram.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/olimex-stm32-p407/src/stm32_sram.c + * boards/arm/stm32f4/olimex-stm32-p407/src/stm32_sram.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/olimex-stm32-p407/src/stm32_st7735.c b/boards/arm/stm32f4/olimex-stm32-p407/src/stm32_st7735.c similarity index 98% rename from boards/arm/stm32/olimex-stm32-p407/src/stm32_st7735.c rename to boards/arm/stm32f4/olimex-stm32-p407/src/stm32_st7735.c index 9e74c73f2780f..3ee27f56b0ac6 100644 --- a/boards/arm/stm32/olimex-stm32-p407/src/stm32_st7735.c +++ b/boards/arm/stm32f4/olimex-stm32-p407/src/stm32_st7735.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/olimex-stm32-p407/src/stm32_st7735.c + * boards/arm/stm32f4/olimex-stm32-p407/src/stm32_st7735.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f4/olimex-stm32-p407/src/stm32_usb.c b/boards/arm/stm32f4/olimex-stm32-p407/src/stm32_usb.c new file mode 100644 index 0000000000000..63700d43db542 --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-p407/src/stm32_usb.c @@ -0,0 +1,330 @@ +/**************************************************************************** + * boards/arm/stm32f4/olimex-stm32-p407/src/stm32_usb.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include "arm_internal.h" +#include "stm32.h" +#include "stm32_otgfs.h" +#include "olimex-stm32-p407.h" + +#ifdef CONFIG_STM32_OTGFS + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#if defined(CONFIG_USBDEV) || defined(CONFIG_USBHOST) +# define HAVE_USB 1 +#else +# warning "CONFIG_STM32_OTGFS is enabled but neither CONFIG_USBDEV nor CONFIG_USBHOST" +# undef HAVE_USB +#endif + +#ifndef CONFIG_OLIMEXP407_USBHOST_PRIO +# define CONFIG_OLIMEXP407_USBHOST_PRIO 100 +#endif + +#ifndef CONFIG_OLIMEXP407_USBHOST_STACKSIZE +# define CONFIG_OLIMEXP407_USBHOST_STACKSIZE 1024 +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +static struct usbhost_connection_s *g_usbconn; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: usbhost_waiter + * + * Description: + * Wait for USB devices to be connected. + * + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +static int usbhost_waiter(int argc, char *argv[]) +{ + struct usbhost_hubport_s *hport; + + uinfo("Running\n"); + for (; ; ) + { + /* Wait for the device to change state */ + + DEBUGVERIFY(CONN_WAIT(g_usbconn, &hport)); + uinfo("%s\n", hport->connected ? "connected" : "disconnected"); + + /* Did we just become connected? */ + + if (hport->connected) + { + /* Yes.. enumerate the newly connected device */ + + CONN_ENUMERATE(g_usbconn, hport); + } + } + + /* Keep the compiler from complaining */ + + return 0; +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_usb_configure + * + * Description: + * Called from stm32_usb_configure very early in initialization to setup + * USB-related GPIO pins for the Olimex STM32 P407 board. + * + ****************************************************************************/ + +void stm32_usb_configure(void) +{ +#ifdef CONFIG_STM32_OTGFS + /* The OTG FS has an internal soft pull-up. + * No GPIO configuration is required + */ + + /* Configure the OTG FS VBUS sensing GPIO, + * Power On, and Overcurrent GPIOs + */ + + stm32_configgpio(GPIO_OTGFS_VBUS); + stm32_configgpio(GPIO_OTGFS_PWRON); + stm32_configgpio(GPIO_OTGFS_OVER); +#endif +} + +/**************************************************************************** + * Name: stm32_usbhost_setup + * + * Description: + * Called at application startup time to initialize the USB host + * functionality. + * This function will start a thread that will monitor for device + * connection/disconnection events. + * + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +int stm32_usbhost_setup(void) +{ + int ret; + + /* First, register all of the class drivers needed to support the drivers + * that we care about: + */ + + uinfo("Register class drivers\n"); + +#ifdef CONFIG_USBHOST_HUB + /* Initialize USB hub class support */ + + ret = usbhost_hub_initialize(); + if (ret < 0) + { + uerr("ERROR: usbhost_hub_initialize failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_USBHOST_MSC + /* Register the USB mass storage class class */ + + ret = usbhost_msc_initialize(); + if (ret != OK) + { + uerr("ERROR: Failed to register the mass storage class: %d\n", ret); + } +#endif + +#ifdef CONFIG_USBHOST_CDCACM + /* Register the CDC/ACM serial class */ + + ret = usbhost_cdcacm_initialize(); + if (ret != OK) + { + uerr("ERROR: Failed to register the CDC/ACM serial class: %d\n", ret); + } +#endif + +#ifdef CONFIG_USBHOST_HIDKBD + /* Initialize the HID keyboard class */ + + ret = usbhost_kbdinit(); + if (ret != OK) + { + uerr("ERROR: Failed to register the HID keyboard class\n"); + } +#endif + +#ifdef CONFIG_USBHOST_HIDMOUSE + /* Initialize the HID mouse class */ + + ret = usbhost_mouse_init(); + if (ret != OK) + { + uerr("ERROR: Failed to register the HID mouse class\n"); + } +#endif + + /* Then get an instance of the USB host interface */ + + uinfo("Initialize USB host\n"); + g_usbconn = stm32_otgfshost_initialize(0); + if (g_usbconn) + { + /* Start a thread to handle device connection. */ + + uinfo("Start usbhost_waiter\n"); + + ret = kthread_create("usbhost", CONFIG_OLIMEXP407_USBHOST_PRIO, + CONFIG_OLIMEXP407_USBHOST_STACKSIZE, + usbhost_waiter, NULL); + return ret < 0 ? -ENOEXEC : OK; + } + + return -ENODEV; +} +#endif + +/**************************************************************************** + * Name: stm32_usbhost_vbusdrive + * + * Description: + * Enable/disable driving of VBUS 5V output. This function must be + * provided be each platform that implements the STM32 OTG FS host + * interface + * + * "On-chip 5 V VBUS generation is not supported. For this reason, a + * charge pump or, if 5 V are available on the application board, a + * basic power switch, must be added externally to drive the 5 V VBUS + * line. The external charge pump can be driven by any GPIO output. + * When the application decides to power on VBUS using the chosen GPIO, + * it must also set the port power bit in the host port control and + * status register (PPWR bit in OTG_FS_HPRT). + * + * "The application uses this field to control power to this port, + * and the core clears this bit on an overcurrent condition." + * + * Input Parameters: + * iface - For future growth to handle multiple USB host interface. + * Should be zero. + * enable - true: enable VBUS power; false: disable VBUS power + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +void stm32_usbhost_vbusdrive(int iface, bool enable) +{ + DEBUGASSERT(iface == 0); + + if (enable) + { + /* Enable the Power Switch by driving the enable pin low */ + + stm32_gpiowrite(GPIO_OTGFS_PWRON, false); + } + else + { + /* Disable the Power Switch by driving the enable pin high */ + + stm32_gpiowrite(GPIO_OTGFS_PWRON, true); + } +} +#endif + +/**************************************************************************** + * Name: stm32_setup_overcurrent + * + * Description: + * Setup to receive an interrupt-level callback if an overcurrent + * condition is detected. + * + * Input Parameters: + * handler - New overcurrent interrupt handler + * arg - The argument provided for the interrupt handler + * + * Returned Value: + * Zero (OK) is returned on success. Otherwise, a negated errno value + * is returned to indicate the nature of the failure. + * + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +int stm32_setup_overcurrent(xcpt_t handler, void *arg) +{ + return stm32_gpiosetevent(GPIO_OTGFS_OVER, true, true, true, handler, arg); +} +#endif + +/**************************************************************************** + * Name: stm32_usbsuspend + * + * Description: + * Board logic must provide the stm32_usbsuspend logic if the USBDEV + * driver is used. This function is called whenever the USB enters or + * leaves suspend mode. This is an opportunity for the board logic to + * shutdown clocks, power, etc. while the USB is suspended. + * + ****************************************************************************/ + +#ifdef CONFIG_USBDEV +void stm32_usbsuspend(struct usbdev_s *dev, bool resume) +{ + uinfo("resume: %d\n", resume); +} +#endif + +#endif /* CONFIG_STM32_OTGFS */ diff --git a/boards/arm/stm32f4/olimex-stm32-p407/src/stm32_userleds.c b/boards/arm/stm32f4/olimex-stm32-p407/src/stm32_userleds.c new file mode 100644 index 0000000000000..01b7c08ceade3 --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-p407/src/stm32_userleds.c @@ -0,0 +1,104 @@ +/**************************************************************************** + * boards/arm/stm32f4/olimex-stm32-p407/src/stm32_userleds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include "stm32.h" +#include "olimex-stm32-p407.h" + +#ifndef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* This array maps an LED number to GPIO pin configuration */ + +static uint32_t g_ledcfg[BOARD_NLEDS] = +{ + GPIO_LED1, GPIO_LED2, GPIO_LED3, GPIO_LED4 +}; + +/**************************************************************************** + * Private Function Protototypes + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_userled_initialize + ****************************************************************************/ + +uint32_t board_userled_initialize(void) +{ + /* Configure LED1-4 GPIOs for output */ + + stm32_configgpio(GPIO_LED1); + stm32_configgpio(GPIO_LED2); + stm32_configgpio(GPIO_LED3); + stm32_configgpio(GPIO_LED4); + return BOARD_NLEDS; +} + +/**************************************************************************** + * Name: board_userled + ****************************************************************************/ + +void board_userled(int led, bool ledon) +{ + if ((unsigned)led < BOARD_NLEDS) + { + stm32_gpiowrite(g_ledcfg[led], ledon); + } +} + +/**************************************************************************** + * Name: board_userled_all + ****************************************************************************/ + +void board_userled_all(uint32_t ledset) +{ + stm32_gpiowrite(GPIO_LED1, (ledset & BOARD_LED1_BIT) != 0); + stm32_gpiowrite(GPIO_LED2, (ledset & BOARD_LED2_BIT) != 0); + stm32_gpiowrite(GPIO_LED3, (ledset & BOARD_LED3_BIT) != 0); + stm32_gpiowrite(GPIO_LED4, (ledset & BOARD_LED4_BIT) != 0); +} + +#endif /* !CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32f4/omnibusf4/CMakeLists.txt b/boards/arm/stm32f4/omnibusf4/CMakeLists.txt new file mode 100644 index 0000000000000..b1118af49bb66 --- /dev/null +++ b/boards/arm/stm32f4/omnibusf4/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32f4/omnibusf4/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/arm/stm32f4/omnibusf4/Kconfig b/boards/arm/stm32f4/omnibusf4/Kconfig new file mode 100644 index 0000000000000..bb0e7ff53b936 --- /dev/null +++ b/boards/arm/stm32f4/omnibusf4/Kconfig @@ -0,0 +1,8 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# + +if ARCH_BOARD_OMNIBUSF4 + +endif diff --git a/boards/arm/stm32f4/omnibusf4/configs/nsh/defconfig b/boards/arm/stm32f4/omnibusf4/configs/nsh/defconfig new file mode 100644 index 0000000000000..848febabe21a9 --- /dev/null +++ b/boards/arm/stm32f4/omnibusf4/configs/nsh/defconfig @@ -0,0 +1,124 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_LEDS is not set +# CONFIG_MMCSD_HAVE_CARDDETECT is not set +# CONFIG_MMCSD_HAVE_WRITEPROTECT is not set +# CONFIG_MMCSD_MMCSUPPORT is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_SPI_CALLBACK is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="omnibusf4" +CONFIG_ARCH_BOARD_OMNIBUSF4=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F405RG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL_IOCTL=y +CONFIG_BOARDCTL_RESET=y +CONFIG_BOARDCTL_USBDEVCTRL=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_DEBUG_FEATURES=y +CONFIG_DEV_GPIO=y +CONFIG_DEV_URANDOM=y +CONFIG_DRIVERS_VIDEO=y +CONFIG_EXAMPLES_HELLO=y +CONFIG_EXAMPLES_HELLOXX=y +CONFIG_EXAMPLES_LEDS=y +CONFIG_EXAMPLES_LEDS_LEDSET=0x1 +CONFIG_EXAMPLES_LEDS_STACKSIZE=512 +CONFIG_EXAMPLES_PWM=y +CONFIG_EXAMPLES_SERIALRX=y +CONFIG_EXAMPLES_SERIALRX_PRINTHEX=y +CONFIG_FAT_LCNAMES=y +CONFIG_FAT_LFN=y +CONFIG_FS_FAT=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_IOB_NBUFFERS=24 +CONFIG_IOB_NCHAINS=8 +CONFIG_LIBC_HOSTNAME="omnibusf4" +CONFIG_LIBM=y +CONFIG_LINE_MAX=64 +CONFIG_M25P_SPIFREQUENCY=75000000 +CONFIG_MMCSD=y +CONFIG_MM_IOB=y +CONFIG_MM_REGIONS=2 +CONFIG_MPU60X0_EXTI=y +CONFIG_MTD=y +CONFIG_MTD_M25P=y +CONFIG_MTD_SECT512=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_MMCSDSPIPORTNO=2 +CONFIG_NSH_PROMPT_STRING="omnibusf4> " +CONFIG_NSH_READLINE=y +CONFIG_PIPES=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_PWM=y +CONFIG_PWM_NCHANNELS=4 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_LPWORK=y +CONFIG_SCHED_WAITPID=y +CONFIG_SENSORS=y +CONFIG_SENSORS_MPU60X0=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_STM32_CCMDATARAM=y +CONFIG_STM32_CCMEXCLUDE=y +CONFIG_STM32_DFU=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PWM_MULTICHAN=y +CONFIG_STM32_PWR=y +CONFIG_STM32_SPI1=y +CONFIG_STM32_SPI2=y +CONFIG_STM32_SPI3=y +CONFIG_STM32_TIM10=y +CONFIG_STM32_TIM12=y +CONFIG_STM32_TIM1=y +CONFIG_STM32_TIM2=y +CONFIG_STM32_TIM2_CH3OUT=y +CONFIG_STM32_TIM2_CH4OUT=y +CONFIG_STM32_TIM2_CHANNEL3=y +CONFIG_STM32_TIM2_CHANNEL4=y +CONFIG_STM32_TIM2_PWM=y +CONFIG_STM32_TIM3=y +CONFIG_STM32_TIM3_CH3OUT=y +CONFIG_STM32_TIM3_CH4OUT=y +CONFIG_STM32_TIM3_CHANNEL3=y +CONFIG_STM32_TIM3_CHANNEL4=y +CONFIG_STM32_TIM3_PWM=y +CONFIG_STM32_TIM4=y +CONFIG_STM32_TIM5=y +CONFIG_STM32_TIM8=y +CONFIG_STM32_TIM9=y +CONFIG_STM32_USART1=y +CONFIG_STM32_USART3=y +CONFIG_STM32_USART6=y +CONFIG_SYSTEM_NSH=y +CONFIG_SYSTEM_ZMODEM=y +CONFIG_USART3_SERIAL_CONSOLE=y +CONFIG_USBDEV=y +CONFIG_USBDEV_BUSPOWERED=y +CONFIG_USBDEV_DMA=y +CONFIG_USBDEV_DUALSPEED=y +CONFIG_USBDEV_MAXPOWER=500 +CONFIG_USERLED=y +CONFIG_USERLED_LOWER=y +CONFIG_VIDEO_MAX7456=y +CONFIG_WQUEUE_NOTIFIER=y diff --git a/boards/arm/stm32f4/omnibusf4/include/board.h b/boards/arm/stm32f4/omnibusf4/include/board.h new file mode 100644 index 0000000000000..3fd9a21b8f2a6 --- /dev/null +++ b/boards/arm/stm32f4/omnibusf4/include/board.h @@ -0,0 +1,262 @@ +/**************************************************************************** + * boards/arm/stm32f4/omnibusf4/include/board.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_STM32_OMNIBUSF4_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32_OMNIBUSF4_INCLUDE_BOARD_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#ifndef __ASSEMBLY__ +# include +# include +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Clocking *****************************************************************/ + +/* The OMNIBUSF4 board uses a single 8MHz crystal. + * + * This is the canonical configuration: + * System Clock source : PLL (HSE) + * SYSCLK(Hz) : 168000000 Determined by PLL configuration + * HCLK(Hz) : 168000000 (STM32_RCC_CFGR_HPRE) + * AHB Prescaler : 1 (STM32_RCC_CFGR_HPRE) + * APB1 Prescaler : 4 (STM32_RCC_CFGR_PPRE1) + * APB2 Prescaler : 2 (STM32_RCC_CFGR_PPRE2) + * HSE Frequency(Hz) : 8000000 (STM32_BOARD_XTAL) + * PLLM : 8 (STM32_PLLCFG_PLLM) + * PLLN : 336 (STM32_PLLCFG_PLLN) + * PLLP : 2 (STM32_PLLCFG_PLLP) + * PLLQ : 7 (STM32_PLLCFG_PLLQ) + * Main regulator + * output voltage : Scale1 mode Needed for high speed SYSCLK + * Flash Latency(WS) : 5 + * Prefetch Buffer : OFF + * Instruction cache : ON + * Data cache : ON + * Require 48MHz for + * USB OTG FS, : Enabled + * SDIO and RNG clock + */ + +/* HSI - 16 MHz RC factory-trimmed + * LSI - 32 KHz RC + * HSE - On-board crystal frequency is 8MHz + * LSE - 32.768 kHz + */ + +#define STM32_BOARD_XTAL 8000000ul + +#define STM32_HSI_FREQUENCY 16000000ul +#define STM32_LSI_FREQUENCY 32000 +#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL +#define STM32_LSE_FREQUENCY 32768 + +/* Main PLL Configuration. + * + * PLL source is HSE + * PLL_VCO = (STM32_HSE_FREQUENCY / PLLM) * PLLN + * = (8,000,000 / 8) * 336 + * = 336,000,000 + * SYSCLK = PLL_VCO / PLLP + * = 336,000,000 / 2 = 168,000,000 + * USB OTG FS, SDIO and RNG Clock + * = PLL_VCO / PLLQ + * = 48,000,000 + */ + +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(8) +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(336) +#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_2 +#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(7) + +#define STM32_SYSCLK_FREQUENCY 168000000ul + +/* AHB clock (HCLK) is SYSCLK (168MHz) */ + +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY + +/* APB1 clock (PCLK1) is HCLK/4 (42MHz) */ + +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd4 /* PCLK1 = HCLK / 4 */ +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/4) + +/* Timers driven from APB1 will be twice PCLK1 */ + +#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) + +/* APB2 clock (PCLK2) is HCLK/2 (84MHz) */ + +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLKd2 /* PCLK2 = HCLK / 2 */ +#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/2) + +/* Timers driven from APB2 will be twice PCLK2 */ + +#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM9_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM10_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM11_CLKIN (2*STM32_PCLK2_FREQUENCY) + +/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx + * otherwise frequency is 2xAPBx. + * Note: TIM1,8 are on APB2, others on APB1 + */ + +#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM2_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM3_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM4_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM5_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM6_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM7_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY + +/* Pin configurations *******************************************************/ + +#define BOARD_NLEDS 2 /* One literal LED, one beeper */ +#define GPIO_LED1 (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_50MHz |\ + GPIO_OUTPUT_CLEAR | GPIO_PORTB | GPIO_PIN5) +#define GPIO_BEEPER1 (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_50MHz |\ + GPIO_OUTPUT_CLEAR | GPIO_PORTB|GPIO_PIN4) + +/* USART1: */ + +#if 0 +#define INVERTER_PIN_USART1 PC0 /* DYS F4 Pro, Omnibus F4 AIO 1st Gen only */ +#endif +#define GPIO_USART1_RX (GPIO_USART1_RX_1|GPIO_SPEED_100MHz) /* PA10 */ +#define GPIO_USART1_TX (GPIO_USART1_TX_1|GPIO_SPEED_100MHz) /* PA9 */ + +/* USART2: + * + * TODO: Do OMNIBUSF4 targets use USART2? + */ + +/* USART3: */ + +#define GPIO_USART3_TX (GPIO_USART3_TX_1|GPIO_SPEED_100MHz) /* PB10 */ +#define GPIO_USART3_RX (GPIO_USART3_RX_1|GPIO_SPEED_100MHz) /* PB11 */ + +/* USART4: */ + +/* USART6: */ + +#if 0 +#define INVERTER_PIN_UART6 PC8 /* Omnibus F4 V3 and later, EXUAVF4PRO */ +#endif +#define GPIO_USART6_RX (GPIO_USART6_RX_1|GPIO_SPEED_100MHz) /* PC7 */ +#define GPIO_USART6_TX (GPIO_USART6_TX_1|GPIO_SPEED_100MHz) /* PC6 */ + +/* PWM - motor outputs, etc. are on these pins: */ + +#define GPIO_TIM3_CH3OUT (GPIO_TIM3_CH3OUT_1|GPIO_SPEED_50MHz) /* S1_OUT PB0 */ +#define GPIO_TIM3_CH4OUT (GPIO_TIM3_CH4OUT_1|GPIO_SPEED_50MHz) /* S2_OUT PB1 */ +#define GPIO_TIM2_CH4OUT (GPIO_TIM2_CH4OUT_1|GPIO_SPEED_50MHz) /* S3_OUT PA3 */ +#define GPIO_TIM2_CH3OUT (GPIO_TIM3_CH3OUT_1|GPIO_SPEED_50MHz) /* S4_OUT PA2 */ + +/* SPI1 : + * + * MPU6000 6-axis motion sensor (accelerometer + gyroscope), or + * MPU6500 6-Axis MEMS MotionTracking Device with DMP + * + * MPU6000 interrupts + * #define USE_GYRO_EXTI + * #define GYRO_1_EXTI_PIN PC4 + * #define USE_MPU_DATA_READY_SIGNAL + * + * #define GYRO_1_ALIGN CW270_DEG + * #define ACC_1_ALIGN CW270_DEG + */ + +#define GPIO_SPI1_MISO (GPIO_SPI1_MISO_1|GPIO_SPEED_50MHz) /* PA6 */ +#define GPIO_SPI1_MOSI (GPIO_SPI1_MOSI_1|GPIO_SPEED_50MHz) /* PA7 */ +#define GPIO_SPI1_SCK (GPIO_SPI1_SCK_1|GPIO_SPEED_50MHz) /* PA5 */ +#if 0 +#define GPIO_SPI1_NSS (GPIO_SPI1_NSS_2|GPIO_SPEED_50MHz) /* PA4 */ +#endif +#define DMACHAN_SPI1_RX DMAMAP_SPI1_RX_1 /* 2:0:3 */ +#define DMACHAN_SPI1_TX DMAMAP_SPI1_TX_1 /* 2:3:3 */ + +/* SPI2 : + * + * Used for MMC/SD on OMNIBUSF4SD. + */ + +#define GPIO_SPI2_MISO (GPIO_SPI2_MISO_1|GPIO_SPEED_50MHz) /* PB14 */ +#define GPIO_SPI2_MOSI (GPIO_SPI2_MOSI_1|GPIO_SPEED_50MHz) /* PB15 */ +#define GPIO_SPI2_NSS (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_50MHz | \ + GPIO_OUTPUT_SET | GPIO_PORTB | GPIO_PIN12) +#define GPIO_SPI2_SCK (GPIO_SPI2_SCK_2|GPIO_SPEED_50MHz) /* PB13 */ +#define DMACHAN_SPI2_RX DMAMAP_SPI2_RX /* 1:3:0 */ +#define DMACHAN_SPI2_TX DMAMAP_SPI2_TX /* 1:4:0 */ + +#define GPIO_MMCSD_NSS GPIO_SPI2_NSS +#define GPIO_MMCSD_NCD (GPIO_INPUT | GPIO_FLOAT | GPIO_EXTI | \ + GPIO_PORTB | GPIO_PIN7) /* PB7 SD_DET */ + +/* SPI3 : + * + * OMNIBUSF4SD targets use PA15 for NSS; others use PB4 + * (? BF code says "PB3"). + * define GPIO_SPI3_NSS GPIO_SPI3_NSS_2 PB4 + * + * Barometer and/or MAX7456, depending on the target. + * (OMNIBUSF4BASE targets appear to have a cyrf6936 device.) + */ + +#define GPIO_SPI3_MISO (GPIO_SPI3_MISO_2|GPIO_SPEED_50MHz) /* PC11 */ +#define GPIO_SPI3_MOSI (GPIO_SPI3_MOSI_2|GPIO_SPEED_50MHz) /* PC12 */ +#define GPIO_SPI3_NSS (GPIO_SPI3_NSS_1|GPIO_SPEED_50MHz) /* PA15 */ /* TODO: doesn't work like a chip select */ +#define GPIO_SPI3_SCK (GPIO_SPI3_SCK_2|GPIO_SPEED_50MHz) /* PC10 */ + +#if 0 +/* I2C : */ + +#define GPIO_I2C1_SCL (GPIO_I2C1_SCL_1|GPIO_SPEED_50MHz) +#define GPIO_I2C1_SDA (GPIO_I2C1_SDA_2|GPIO_SPEED_50MHz) +#endif + +/* USB OTG FS */ + +#define GPIO_OTGFS_DM (GPIO_OTGFS_DM_0|GPIO_SPEED_100MHz) +#define GPIO_OTGFS_DP (GPIO_OTGFS_DP_0|GPIO_SPEED_100MHz) +#define GPIO_OTGFS_ID (GPIO_OTGFS_ID_0|GPIO_SPEED_100MHz) +#define GPIO_OTGFS_SOF (GPIO_OTGFS_SOF_0|GPIO_SPEED_100MHz) + +#endif /* __BOARDS_ARM_STM32_OMNIBUSF4_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32f4/omnibusf4/kernel/Makefile b/boards/arm/stm32f4/omnibusf4/kernel/Makefile new file mode 100644 index 0000000000000..9ccee530286fc --- /dev/null +++ b/boards/arm/stm32f4/omnibusf4/kernel/Makefile @@ -0,0 +1,94 @@ +############################################################################ +# boards/arm/stm32f4/omnibusf4/kernel/Makefile +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +# The entry point name (if none is provided in the .config file) + +CONFIG_INIT_ENTRYPOINT ?= user_start +ENTRYPT = $(patsubst "%",%,$(CONFIG_INIT_ENTRYPOINT)) + +# Get the paths to the libraries and the links script path in format that +# is appropriate for the host OS + +USER_LIBPATHS = $(addprefix -L,$(call CONVERT_PATH,$(addprefix $(TOPDIR)$(DELIM),$(dir $(USERLIBS))))) +USER_LDSCRIPT = -T $(call CONVERT_PATH,$(BOARD_DIR)$(DELIM)scripts$(DELIM)memory.ld) +USER_LDSCRIPT += -T $(call CONVERT_PATH,$(BOARD_DIR)$(DELIM)scripts$(DELIM)user-space.ld) +USER_HEXFILE += $(call CONVERT_PATH,$(TOPDIR)$(DELIM)nuttx_user.hex) +USER_SRECFILE += $(call CONVERT_PATH,$(TOPDIR)$(DELIM)nuttx_user.srec) +USER_BINFILE += $(call CONVERT_PATH,$(TOPDIR)$(DELIM)nuttx_user.bin) + +USER_LDFLAGS = --undefined=$(ENTRYPT) --entry=$(ENTRYPT) $(USER_LDSCRIPT) +USER_LDLIBS = $(patsubst lib%,-l%,$(basename $(notdir $(USERLIBS)))) +USER_LIBGCC = "${shell "$(CC)" $(ARCHCPUFLAGS) -print-libgcc-file-name}" + +# Source files + +CSRCS = stm32_userspace.c +COBJS = $(CSRCS:.c=$(OBJEXT)) +OBJS = $(COBJS) + +# Targets: + +all: $(TOPDIR)$(DELIM)nuttx_user.elf $(TOPDIR)$(DELIM)User.map +.PHONY: nuttx_user.elf depend clean distclean + +$(COBJS): %$(OBJEXT): %.c + $(call COMPILE, $<, $@) + +# Create the nuttx_user.elf file containing all of the user-mode code + +nuttx_user.elf: $(OBJS) + $(Q) $(LD) -o $@ $(USER_LDFLAGS) $(USER_LIBPATHS) $(OBJS) --start-group $(USER_LDLIBS) --end-group $(USER_LIBGCC) + +$(TOPDIR)$(DELIM)nuttx_user.elf: nuttx_user.elf + @echo "LD: nuttx_user.elf" + $(Q) cp -a nuttx_user.elf $(TOPDIR)$(DELIM)nuttx_user.elf +ifeq ($(CONFIG_INTELHEX_BINARY),y) + @echo "CP: nuttx_user.hex" + $(Q) $(OBJCOPY) $(OBJCOPYARGS) -O ihex nuttx_user.elf $(USER_HEXFILE) +endif +ifeq ($(CONFIG_MOTOROLA_SREC),y) + @echo "CP: nuttx_user.srec" + $(Q) $(OBJCOPY) $(OBJCOPYARGS) -O srec nuttx_user.elf $(USER_SRECFILE) +endif +ifeq ($(CONFIG_RAW_BINARY),y) + @echo "CP: nuttx_user.bin" + $(Q) $(OBJCOPY) $(OBJCOPYARGS) -O binary nuttx_user.elf $(USER_BINFILE) +endif + +$(TOPDIR)$(DELIM)User.map: nuttx_user.elf + @echo "MK: User.map" + $(Q) $(NM) nuttx_user.elf >$(TOPDIR)$(DELIM)User.map + $(Q) $(CROSSDEV)size nuttx_user.elf + +.depend: + +depend: .depend + +clean: + $(call DELFILE, nuttx_user.elf) + $(call DELFILE, "$(TOPDIR)$(DELIM)nuttx_user.*") + $(call DELFILE, "$(TOPDIR)$(DELIM)User.map") + $(call CLEAN) + +distclean: clean diff --git a/boards/arm/stm32f4/omnibusf4/kernel/stm32_userspace.c b/boards/arm/stm32f4/omnibusf4/kernel/stm32_userspace.c new file mode 100644 index 0000000000000..77bf45552f209 --- /dev/null +++ b/boards/arm/stm32f4/omnibusf4/kernel/stm32_userspace.c @@ -0,0 +1,111 @@ +/**************************************************************************** + * boards/arm/stm32f4/omnibusf4/kernel/stm32_userspace.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include +#include +#include +#include + +#if defined(CONFIG_BUILD_PROTECTED) && !defined(__KERNEL__) + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +#ifndef CONFIG_NUTTX_USERSPACE +# error "CONFIG_NUTTX_USERSPACE not defined" +#endif + +#if CONFIG_NUTTX_USERSPACE != 0x08020000 +# error "CONFIG_NUTTX_USERSPACE must be 0x08020000 to match memory.ld" +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static struct userspace_data_s g_userspace_data = +{ + .us_heap = &g_mmheap, +}; + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/* These 'addresses' of these values are setup by the linker script. */ + +extern uint8_t _stext[]; /* Start of .text */ +extern uint8_t _etext[]; /* End_1 of .text + .rodata */ +extern const uint8_t _eronly[]; /* End+1 of read only section (.text + .rodata) */ +extern uint8_t _sdata[]; /* Start of .data */ +extern uint8_t _edata[]; /* End+1 of .data */ +extern uint8_t _sbss[]; /* Start of .bss */ +extern uint8_t _ebss[]; /* End+1 of .bss */ + +const struct userspace_s userspace locate_data(".userspace") = +{ + /* General memory map */ + + .us_entrypoint = CONFIG_INIT_ENTRYPOINT, + .us_textstart = (uintptr_t)_stext, + .us_textend = (uintptr_t)_etext, + .us_datasource = (uintptr_t)_eronly, + .us_datastart = (uintptr_t)_sdata, + .us_dataend = (uintptr_t)_edata, + .us_bssstart = (uintptr_t)_sbss, + .us_bssend = (uintptr_t)_ebss, + + /* User data memory structure */ + + .us_data = &g_userspace_data, + + /* Task/thread startup routines */ + + .task_startup = nxtask_startup, + + /* Signal handler trampoline */ + + .signal_handler = up_signal_handler, + + /* User-space work queue support (declared in include/nuttx/wqueue.h) */ + +#ifdef CONFIG_LIBC_USRWORK + .work_usrstart = work_usrstart, +#endif +}; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +#endif /* CONFIG_BUILD_PROTECTED && !__KERNEL__ */ diff --git a/boards/arm/stm32f4/omnibusf4/scripts/Make.defs b/boards/arm/stm32f4/omnibusf4/scripts/Make.defs new file mode 100644 index 0000000000000..f5c23b2b86ca9 --- /dev/null +++ b/boards/arm/stm32f4/omnibusf4/scripts/Make.defs @@ -0,0 +1,41 @@ +############################################################################ +# boards/arm/stm32f4/omnibusf4/scripts/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/.config +include $(TOPDIR)/tools/Config.mk +include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs + +LDSCRIPT = ld.script +ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) + +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32f4/omnibusf4/scripts/kernel-space.ld b/boards/arm/stm32f4/omnibusf4/scripts/kernel-space.ld new file mode 100644 index 0000000000000..6c45eaa4e84e0 --- /dev/null +++ b/boards/arm/stm32f4/omnibusf4/scripts/kernel-space.ld @@ -0,0 +1,99 @@ +/**************************************************************************** + * boards/arm/stm32f4/omnibusf4/scripts/kernel-space.ld + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* NOTE: This depends on the memory.ld script having been included prior to + * this script. + */ + +OUTPUT_ARCH(arm) +ENTRY(_stext) +SECTIONS +{ + .text : { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > kflash + + .init_section : { + _sinit = ABSOLUTE(.); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) + _einit = ABSOLUTE(.); + } > kflash + + .ARM.extab : { + *(.ARM.extab*) + } > kflash + + __exidx_start = ABSOLUTE(.); + .ARM.exidx : { + *(.ARM.exidx*) + } > kflash + + __exidx_end = ABSOLUTE(.); + + _eronly = ABSOLUTE(.); + + .data : { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > ksram AT > kflash + + .bss : { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(8); + _ebss = ABSOLUTE(.); + } > ksram + + /* Stabs debugging sections */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/stm32f4/omnibusf4/scripts/ld.script b/boards/arm/stm32f4/omnibusf4/scripts/ld.script new file mode 100644 index 0000000000000..947c33103d258 --- /dev/null +++ b/boards/arm/stm32f4/omnibusf4/scripts/ld.script @@ -0,0 +1,126 @@ +/**************************************************************************** + * boards/arm/stm32f4/omnibusf4/scripts/ld.script + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* The STM32F407VG has 1024Kb of FLASH beginning at address 0x0800:0000 and + * 192Kb of SRAM. SRAM is split up into three blocks: + * + * 1) 112Kb of SRAM beginning at address 0x2000:0000 + * 2) 16Kb of SRAM beginning at address 0x2001:c000 + * 3) 64Kb of CCM SRAM beginning at address 0x1000:0000 + * + * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 + * where the code expects to begin execution by jumping to the entry point in + * the 0x0800:0000 address + * range. + */ + +MEMORY +{ + flash (rx) : ORIGIN = 0x08000000, LENGTH = 1024K + sram (rwx) : ORIGIN = 0x20000000, LENGTH = 112K +} + +OUTPUT_ARCH(arm) +ENTRY(_stext) +EXTERN(_vectors) +SECTIONS +{ + .text : { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > flash + + .init_section : ALIGN(4) { + _sinit = ABSOLUTE(.); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) + _einit = ABSOLUTE(.); + } > flash + + .ARM.extab : ALIGN(4) { + *(.ARM.extab*) + } > flash + + .ARM.exidx : ALIGN(4) { + __exidx_start = ABSOLUTE(.); + *(.ARM.exidx*) + __exidx_end = ABSOLUTE(.); + } > flash + + .tdata : { + _stdata = ABSOLUTE(.); + *(.tdata .tdata.* .gnu.linkonce.td.*); + _etdata = ABSOLUTE(.); + } > flash + + .tbss : { + _stbss = ABSOLUTE(.); + *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); + _etbss = ABSOLUTE(.); + } > flash + + _eronly = ABSOLUTE(.); + + .data : ALIGN(4) { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > sram AT > flash + + .bss : ALIGN(4) { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + _ebss = ABSOLUTE(.); + } > sram + + /* Stabs debugging sections. */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/stm32f4/omnibusf4/scripts/memory.ld b/boards/arm/stm32f4/omnibusf4/scripts/memory.ld new file mode 100644 index 0000000000000..196d3591fffc7 --- /dev/null +++ b/boards/arm/stm32f4/omnibusf4/scripts/memory.ld @@ -0,0 +1,87 @@ +/**************************************************************************** + * boards/arm/stm32f4/omnibusf4/scripts/memory.ld + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* The STM32F407VG has 1024Kb of FLASH beginning at address 0x0800:0000 and + * 192Kb of SRAM. SRAM is split up into three blocks: + * + * 1) 112KB of SRAM beginning at address 0x2000:0000 + * 2) 16KB of SRAM beginning at address 0x2001:c000 + * 3) 64KB of CCM SRAM beginning at address 0x1000:0000 + * + * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 + * where the code expects to begin execution by jumping to the entry point in + * the 0x0800:0000 address range. + * + * For MPU support, the kernel-mode NuttX section is assumed to be 128Kb of + * FLASH and 4Kb of SRAM. That is an excessive amount for the kernel which + * should fit into 64KB and, of course, can be optimized as needed (See + * also boards/arm/stm32f4/omnibusf4/scripts/kernel-space.ld). Allowing the + * additional does permit addition debug instrumentation to be added to the + * kernel space without overflowing the partition. + * + * Alignment of the user space FLASH partition is also a critical factor: + * The user space FLASH partition will be spanned with a single region of + * size 2**n bytes. The alignment of the user-space region must be the same. + * As a consequence, as the user-space increases in size, the alignment + * requirement also increases. + * + * This alignment requirement means that the largest user space FLASH region + * you can have will be 512KB at it would have to be positioned at + * 0x08800000. If you change this address, don't forget to change the + * CONFIG_NUTTX_USERSPACE configuration setting to match and to modify + * the check in kernel/userspace.c. + * + * For the same reasons, the maximum size of the SRAM mapping is limited to + * 4KB. Both of these alignment limitations could be reduced by using + * multiple regions to map the FLASH/SDRAM range or perhaps with some + * clever use of subregions. + * + * A detailed memory map for the 112KB SRAM region is as follows: + * + * 0x20000 0000: Kernel .data region. Typical size: 0.1KB + * ------- ---- Kernel .bss region. Typical size: 1.8KB + * 0x20000 0800: Kernel IDLE thread stack (approximate). Size is + * determined by CONFIG_IDLETHREAD_STACKSIZE and + * adjustments for alignment. Typical is 1KB. + * ------- ---- Padded to 4KB + * 0x20000 1000: User .data region. Size is variable. + * ------- ---- User .bss region Size is variable. + * 0x20000 2000: Beginning of kernel heap. Size determined by + * CONFIG_MM_KERNEL_HEAPSIZE. + * ------- ---- Beginning of user heap. Can vary with other settings. + * 0x20001 c000: End+1 of CPU RAM + */ + +MEMORY +{ + /* 1024Kb FLASH */ + + kflash (rx) : ORIGIN = 0x08000000, LENGTH = 128K + uflash (rx) : ORIGIN = 0x08020000, LENGTH = 128K + xflash (rx) : ORIGIN = 0x08040000, LENGTH = 768K + + /* 112Kb of contiguous SRAM */ + + ksram (rwx) : ORIGIN = 0x20000000, LENGTH = 4K + usram (rwx) : ORIGIN = 0x20001000, LENGTH = 4K + xsram (rwx) : ORIGIN = 0x20002000, LENGTH = 104K +} diff --git a/boards/arm/stm32f4/omnibusf4/scripts/user-space.ld b/boards/arm/stm32f4/omnibusf4/scripts/user-space.ld new file mode 100644 index 0000000000000..b50708ae317ee --- /dev/null +++ b/boards/arm/stm32f4/omnibusf4/scripts/user-space.ld @@ -0,0 +1,101 @@ +/**************************************************************************** + * boards/arm/stm32f4/omnibusf4/scripts/user-space.ld + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* NOTE: This depends on the memory.ld script having been included prior to + * this script. + */ + +OUTPUT_ARCH(arm) +SECTIONS +{ + .userspace : { + *(.userspace) + } > uflash + + .text : { + _stext = ABSOLUTE(.); + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > uflash + + .init_section : { + _sinit = ABSOLUTE(.); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) + _einit = ABSOLUTE(.); + } > uflash + + .ARM.extab : { + *(.ARM.extab*) + } > uflash + + __exidx_start = ABSOLUTE(.); + .ARM.exidx : { + *(.ARM.exidx*) + } > uflash + + __exidx_end = ABSOLUTE(.); + + _eronly = ABSOLUTE(.); + + .data : { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > usram AT > uflash + + .bss : { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(8); + _ebss = ABSOLUTE(.); + } > usram + + /* Stabs debugging sections */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/stm32f4/omnibusf4/src/CMakeLists.txt b/boards/arm/stm32f4/omnibusf4/src/CMakeLists.txt new file mode 100644 index 0000000000000..e7c271fa8e38b --- /dev/null +++ b/boards/arm/stm32f4/omnibusf4/src/CMakeLists.txt @@ -0,0 +1,79 @@ +# ############################################################################## +# boards/arm/stm32f4/omnibusf4/src/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(SRCS stm32_boot.c stm32_bringup.c stm32_spi.c stm32_userleds.c) + +if(CONFIG_SENSORS_MPU60X0) + list(APPEND SRCS stm32_mpu6000.c) +endif() + +if(CONFIG_VIDEO_MAX7456) + list(APPEND SRCS stm32_max7456.c) +endif() + +if(CONFIG_STM32_OTGFS) + list(APPEND SRCS stm32_usb.c) +endif() + +if(CONFIG_NETDEVICES) + list(APPEND SRCS stm32_netinit.c) +endif() + +if(CONFIG_PWM) + list(APPEND SRCS stm32_pwm.c) +endif() + +if(CONFIG_BOARDCTL_RESET) + list(APPEND SRCS stm32_reset.c) +endif() + +if(CONFIG_BOARDCTL_IOCTL) + list(APPEND SRCS stm32_ioctl.c) +endif() + +if(CONFIG_ARCH_CUSTOM_PMINIT) + list(APPEND SRCS stm32_pm.c) +endif() + +if(CONFIG_ARCH_IDLE_CUSTOM) + list(APPEND SRCS stm32_idle.c) +endif() + +if(CONFIG_TIMER) + list(APPEND SRCS stm32_timer.c) +endif() + +if(CONFIG_BOARDCTL_UNIQUEID) + list(APPEND SRCS stm32_uid.c) +endif() + +if(CONFIG_USBMSC) + list(APPEND SRCS stm32_usbmsc.c) +endif() + +if(CONFIG_MMCSD) + list(APPEND SRCS stm32_mmcsd.c) +endif() + +target_sources(board PRIVATE ${SRCS}) + +set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/ld.script") diff --git a/boards/arm/stm32f4/omnibusf4/src/Make.defs b/boards/arm/stm32f4/omnibusf4/src/Make.defs new file mode 100644 index 0000000000000..8cea316c75d79 --- /dev/null +++ b/boards/arm/stm32f4/omnibusf4/src/Make.defs @@ -0,0 +1,80 @@ +############################################################################ +# boards/arm/stm32f4/omnibusf4/src/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +CSRCS = stm32_boot.c stm32_bringup.c stm32_spi.c stm32_userleds.c + +ifeq ($(CONFIG_SENSORS_MPU60X0),y) +CSRCS += stm32_mpu6000.c +endif + +ifeq ($(CONFIG_VIDEO_MAX7456),y) +CSRCS += stm32_max7456.c +endif + +ifeq ($(CONFIG_STM32_OTGFS),y) +CSRCS += stm32_usb.c +endif + +ifeq ($(CONFIG_NETDEVICES),y) +CSRCS += stm32_netinit.c +endif + +ifeq ($(CONFIG_PWM),y) +CSRCS += stm32_pwm.c +endif + +ifeq ($(CONFIG_BOARDCTL_RESET),y) +CSRCS += stm32_reset.c +endif +ifeq ($(CONFIG_BOARDCTL_IOCTL),y) +CSRCS += stm32_ioctl.c +endif + +ifeq ($(CONFIG_ARCH_CUSTOM_PMINIT),y) +CSRCS += stm32_pm.c +endif + +ifeq ($(CONFIG_ARCH_IDLE_CUSTOM),y) +CSRCS += stm32_idle.c +endif + +ifeq ($(CONFIG_TIMER),y) +CSRCS += stm32_timer.c +endif + +ifeq ($(CONFIG_BOARDCTL_UNIQUEID),y) +CSRCS += stm32_uid.c +endif + +ifeq ($(CONFIG_USBMSC),y) +CSRCS += stm32_usbmsc.c +endif + +ifeq ($(CONFIG_MMCSD),y) +CSRCS += stm32_mmcsd.c +endif + +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/omnibusf4/src/omnibusf4.h b/boards/arm/stm32f4/omnibusf4/src/omnibusf4.h similarity index 98% rename from boards/arm/stm32/omnibusf4/src/omnibusf4.h rename to boards/arm/stm32f4/omnibusf4/src/omnibusf4.h index d401a52253d24..1eb7d9667cb9e 100644 --- a/boards/arm/stm32/omnibusf4/src/omnibusf4.h +++ b/boards/arm/stm32f4/omnibusf4/src/omnibusf4.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/omnibusf4/src/omnibusf4.h + * boards/arm/stm32f4/omnibusf4/src/omnibusf4.h * * SPDX-License-Identifier: Apache-2.0 * @@ -30,7 +30,7 @@ #include #include #include -#include +#include /**************************************************************************** * Pre-processor Definitions diff --git a/boards/arm/stm32f4/omnibusf4/src/stm32_boot.c b/boards/arm/stm32f4/omnibusf4/src/stm32_boot.c new file mode 100644 index 0000000000000..1eb7e82d4bae0 --- /dev/null +++ b/boards/arm/stm32f4/omnibusf4/src/stm32_boot.c @@ -0,0 +1,127 @@ +/**************************************************************************** + * boards/arm/stm32f4/omnibusf4/src/stm32_boot.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include +#include + +#include "arm_internal.h" +#include "nvic.h" +#include "itm.h" + +#include "stm32.h" +#include "omnibusf4.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_boardinitialize + * + * Description: + * All STM32 architectures must provide the following entry point. This + * entry point is called early in the initialization -- after all memory + * has been configured and mapped but before any devices have been + * initialized. + * + ****************************************************************************/ + +void stm32_boardinitialize(void) +{ +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || defined(CONFIG_STM32_SPI3) + /* Configure SPI chip selects if 1) SPI is not disabled, and 2) the weak + * function stm32_spidev_initialize() has been brought into the link. + */ + + if (stm32_spidev_initialize) + { + stm32_spidev_initialize(); + } +#endif + +#ifdef CONFIG_STM32_OTGFS + /* Initialize USB if the + * 1) OTG FS controller is in the configuration and + * 2) disabled, and + * 3) the weak function stm32_usbinitialize() has been brought into the + * build. Presumably either CONFIG_USBDEV or CONFIG_USBHOST is also + * selected. + */ + + if (stm32_usbinitialize) + { + stm32_usbinitialize(); + } +#endif + +#ifdef HAVE_NETMONITOR + /* Configure board resources to support networking. */ + + if (stm32_netinitialize) + { + stm32_netinitialize(); + } +#endif + +#ifdef CONFIG_ARCH_LEDS + /* Configure on-board LEDs if LED support has been selected. */ + + board_autoled_initialize(); +#endif + +#ifdef HAVE_CCM_HEAP + /* Initialize CCM allocator */ + + ccm_initialize(); +#endif +} + +/**************************************************************************** + * Name: board_late_initialize + * + * Description: + * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_late_initialize(). board_late_initialize() will + * be called immediately after up_initialize() is called and just before + * the initial application is started. This additional initialization + * phase may be used, for example, to initialize board-specific device + * drivers. + * + ****************************************************************************/ + +#ifdef CONFIG_BOARD_LATE_INITIALIZE +void board_late_initialize(void) +{ + /* Perform board-specific initialization */ + + stm32_bringup(); +} +#endif diff --git a/boards/arm/stm32f4/omnibusf4/src/stm32_bringup.c b/boards/arm/stm32f4/omnibusf4/src/stm32_bringup.c new file mode 100644 index 0000000000000..a8d3e5d7a4a8e --- /dev/null +++ b/boards/arm/stm32f4/omnibusf4/src/stm32_bringup.c @@ -0,0 +1,294 @@ +/**************************************************************************** + * boards/arm/stm32f4/omnibusf4/src/stm32_bringup.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include + +#ifdef CONFIG_USBMONITOR +# include +#endif + +#include "stm32.h" +#ifdef CONFIG_STM32_ROMFS +# include "stm32_romfs.h" +#endif + +#ifdef CONFIG_STM32_OTGFS +# include "stm32_usbhost.h" +#endif + +#ifdef CONFIG_USERLED +# include +#endif + +#ifdef CONFIG_RNDIS +# include +#endif + +#include "omnibusf4.h" + +/* Conditional logic in omnibusf4.h will determine if certain features + * are supported. Tests for these features need to be made after including + * omnibusf4.h. + */ + +#ifdef HAVE_RTC_DRIVER +# include +# include "stm32_rtc.h" +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_i2c_register + * + * Description: + * Register one I2C drivers for the I2C tool. + * + ****************************************************************************/ + +#if defined(CONFIG_I2C) && defined(CONFIG_SYSTEM_I2CTOOL) +static void stm32_i2c_register(int bus) +{ + struct i2c_master_s *i2c; + int ret; + + i2c = stm32_i2cbus_initialize(bus); + if (i2c == NULL) + { + syslog(LOG_ERR, "ERROR: Failed to get I2C%d interface\n", bus); + } + else + { + ret = i2c_register(i2c, bus); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to register I2C%d driver: %d\n", + bus, ret); + stm32_i2cbus_uninitialize(i2c); + } + } +} +#endif + +/**************************************************************************** + * Name: stm32_i2ctool + * + * Description: + * Register I2C drivers for the I2C tool. + * + ****************************************************************************/ + +#if defined(CONFIG_I2C) && defined(CONFIG_SYSTEM_I2CTOOL) +static void stm32_i2ctool(void) +{ + stm32_i2c_register(1); +#if 0 + stm32_i2c_register(1); + stm32_i2c_register(2); +#endif +} +#else +# define stm32_i2ctool() +#endif + +/**************************************************************************** + * Name: stm32_bringup + * + * Description: + * Perform architecture-specific initialization + * + * CONFIG_BOARD_INITIALIZE=y : + * Called from board_initialize(). + * + * CONFIG_BOARD_INITIALIZE=n && CONFIG_BOARDCTL=y : + * Called from the NSH library + * + ****************************************************************************/ + +int stm32_bringup(void) +{ +#ifdef HAVE_RTC_DRIVER + struct rtc_lowerhalf_s *lower; +#endif + int ret = OK; + +#if defined(CONFIG_I2C) && defined(CONFIG_SYSTEM_I2CTOOL) + stm32_i2ctool(); +#endif + +#ifdef HAVE_USBHOST + /* Initialize USB host operation. stm32_usbhost_initialize() starts a + * thread will monitor for USB connection and disconnection events. + */ + + ret = stm32_usbhost_initialize(); + if (ret != OK) + { + uerr("ERROR: Failed to initialize USB host: %d\n", ret); + return ret; + } +#endif + +#ifdef HAVE_USBMONITOR + /* Start the USB Monitor */ + + ret = usbmonitor_start(); + if (ret != OK) + { + uerr("ERROR: Failed to start USB monitor: %d\n", ret); + return ret; + } +#endif + +#ifdef CONFIG_MMCSD_SPI + /* Our MMC/SD port is on SPI2. */ + + ret = stm32_mmcsd_initialize(2, CONFIG_NSH_MMCSDMINOR); + if (ret < 0) + { + syslog(LOG_ERR, "Failed to initialize SD slot %d: %d\n", + CONFIG_NSH_MMCSDMINOR, ret); + } +#endif + +#ifdef CONFIG_PWM + ret = stm32_pwm_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_pwm_setup() failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_STM32_CAN_CHARDRIVER + /* Initialize CAN and register the CAN driver. */ + + ret = stm32_can_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_can_setup failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_SENSORS_MPU60X0 + /* Initialize the MPU6000 device. */ + + ret = stm32_mpu6000_initialize(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_mpu6000_initialize() failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_VIDEO_MAX7456 + /* Initialize the MAX7456 OSD device. */ + + ret = stm32_max7456_initialize(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_max7456_initialize() failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_USERLED + /* Register the LED driver */ + + ret = userled_lower_initialize("/dev/userleds"); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: userled_lower_initialize() failed: %d\n", ret); + } +#endif + +#ifdef HAVE_RTC_DRIVER + /* Instantiate the STM32 lower-half RTC driver */ + + lower = stm32_rtc_lowerhalf(); + if (!lower) + { + serr("ERROR: Failed to instantiate the RTC lower-half driver\n"); + return -ENOMEM; + } + else + { + /* Bind the lower half driver and register the combined RTC driver + * as /dev/rtc0 + */ + + ret = rtc_initialize(0, lower); + if (ret < 0) + { + serr("ERROR: Failed to bind/register the RTC driver: %d\n", ret); + return ret; + } + } +#endif + +#ifdef CONFIG_FS_PROCFS + /* Mount the procfs file system */ + + ret = nx_mount(NULL, STM32_PROCFS_MOUNTPOINT, "procfs", 0, NULL); + if (ret < 0) + { + serr("ERROR: Failed to mount procfs at %s: %d\n", + STM32_PROCFS_MOUNTPOINT, ret); + } +#endif + +#ifdef CONFIG_STM32_ROMFS + /* Initialize and mount ROMFS. */ + + ret = stm32_romfs_initialize(); + if (ret < 0) + { + serr("ERROR: Failed to mount romfs at %s: %d\n", + CONFIG_STM32_ROMFS_MOUNTPOINT, ret); + } +#endif + +#if defined(CONFIG_RNDIS) + /* Set up a MAC address for the RNDIS device. */ + + uint8_t mac[6]; + mac[0] = 0xa0; /* TODO */ + mac[1] = (CONFIG_NETINIT_MACADDR_2 >> (8 * 0)) & 0xff; + mac[2] = (CONFIG_NETINIT_MACADDR_1 >> (8 * 3)) & 0xff; + mac[3] = (CONFIG_NETINIT_MACADDR_1 >> (8 * 2)) & 0xff; + mac[4] = (CONFIG_NETINIT_MACADDR_1 >> (8 * 1)) & 0xff; + mac[5] = (CONFIG_NETINIT_MACADDR_1 >> (8 * 0)) & 0xff; + usbdev_rndis_initialize(mac); +#endif + + return ret; +} diff --git a/boards/arm/stm32f4/omnibusf4/src/stm32_idle.c b/boards/arm/stm32f4/omnibusf4/src/stm32_idle.c new file mode 100644 index 0000000000000..ae1ed8241462b --- /dev/null +++ b/boards/arm/stm32f4/omnibusf4/src/stm32_idle.c @@ -0,0 +1,260 @@ +/**************************************************************************** + * boards/arm/stm32f4/omnibusf4/src/stm32_idle.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include + +#include +#include +#include +#include + +#include + +#include "arm_internal.h" +#include "stm32_pm.h" +#include "stm32_rcc.h" +#include "stm32_exti.h" + +#include "omnibusf4.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* Does the board support an IDLE LED to indicate that the board is in the + * IDLE state? + */ + +#if defined(CONFIG_ARCH_LEDS) && defined(LED_IDLE) +# define BEGIN_IDLE() board_autoled_on(LED_IDLE) +# define END_IDLE() board_autoled_off(LED_IDLE) +#else +# define BEGIN_IDLE() +# define END_IDLE() +#endif + +/* Values for the RTC Alarm to wake up from the PM_STANDBY mode */ + +#ifndef CONFIG_PM_ALARM_SEC +# define CONFIG_PM_ALARM_SEC 3 +#endif + +#ifndef CONFIG_PM_ALARM_NSEC +# define CONFIG_PM_ALARM_NSEC 0 +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#if 0 /* Not used */ +static void up_alarmcb(void); +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_idlepm + * + * Description: + * Perform IDLE state power management. + * + ****************************************************************************/ + +#ifdef CONFIG_PM +static void stm32_idlepm(void) +{ + static enum pm_state_e oldstate = PM_NORMAL; + enum pm_state_e newstate; + irqstate_t flags; + int ret; + + /* Decide, which power saving level can be obtained */ + + newstate = pm_checkstate(PM_IDLE_DOMAIN); + + /* Check for state changes */ + + if (newstate != oldstate) + { + sinfo("newstate= %d oldstate=%d\n", newstate, oldstate); + + flags = enter_critical_section(); + + /* Force the global state change */ + + ret = pm_changestate(PM_IDLE_DOMAIN, newstate); + if (ret < 0) + { + /* The new state change failed, revert to the preceding state */ + + pm_changestate(PM_IDLE_DOMAIN, oldstate); + + /* No state change... */ + + goto errout; + } + + /* Then perform board-specific, state-dependent logic here */ + + switch (newstate) + { + case PM_NORMAL: + { + } + break; + + case PM_IDLE: + { + } + break; + + case PM_STANDBY: + { +#ifdef CONFIG_RTC_ALARM + /* Disable RTC Alarm interrupt */ + +#warning "missing logic" + + /* Configure the RTC alarm to Auto Wake the system */ + +#warning "missing logic" + + /* The tv_nsec value must not exceed 1,000,000,000. That + * would be an invalid time. + */ + +#warning "missing logic" + + /* Set the alarm */ + +#warning "missing logic" +#endif + /* Call the STM32 stop mode */ + + stm32_pmstop(true); + + /* We have been re-awakened by some even: A button press? + * An alarm? Cancel any pending alarm and resume the normal + * operation. + */ + +#ifdef CONFIG_RTC_ALARM +#warning "missing logic" +#endif + /* Resume normal operation */ + + pm_changestate(PM_IDLE_DOMAIN, PM_NORMAL); + newstate = PM_NORMAL; + } + break; + + case PM_SLEEP: + { + /* We should not return from standby mode. The only way out + * of standby is via the reset path. + */ + + stm32_pmstandby(); + } + break; + + default: + break; + } + + /* Save the new state */ + + oldstate = newstate; + +errout: + leave_critical_section(flags); + } +} +#else +# define stm32_idlepm() +#endif + +/**************************************************************************** + * Name: up_alarmcb + * + * Description: + * RTC alarm service routine + * + ****************************************************************************/ + +#if 0 /* Not used */ +static void up_alarmcb(void) +{ + /* This alarm occurs because there wasn't any EXTI interrupt during the + * PM_STANDBY period. So just go to sleep. + */ + + pm_changestate(PM_IDLE_DOMAIN, PM_SLEEP); +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_idle + * + * Description: + * up_idle() is the logic that will be executed when their is no other + * ready-to-run task. This is processor idle time and will continue until + * some interrupt occurs to cause a context switch from the idle task. + * + * Processing in this state may be processor-specific. e.g., this is where + * power management operations might be performed. + * + ****************************************************************************/ + +void up_idle(void) +{ +#if defined(CONFIG_SUPPRESS_INTERRUPTS) || defined(CONFIG_SUPPRESS_TIMER_INTS) + /* If the system is idle and there are no timer interrupts, then process + * "fake" timer interrupts. Hopefully, something will wake up. + */ + + nxsched_process_timer(); +#else + + /* Perform IDLE mode power management */ + + BEGIN_IDLE(); + stm32_idlepm(); + END_IDLE(); +#endif +} diff --git a/boards/arm/stm32/omnibusf4/src/stm32_ioctl.c b/boards/arm/stm32f4/omnibusf4/src/stm32_ioctl.c similarity index 98% rename from boards/arm/stm32/omnibusf4/src/stm32_ioctl.c rename to boards/arm/stm32f4/omnibusf4/src/stm32_ioctl.c index c7d7674e3bf64..c744806de825a 100644 --- a/boards/arm/stm32/omnibusf4/src/stm32_ioctl.c +++ b/boards/arm/stm32f4/omnibusf4/src/stm32_ioctl.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/omnibusf4/src/stm32_ioctl.c + * boards/arm/stm32f4/omnibusf4/src/stm32_ioctl.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/omnibusf4/src/stm32_max7456.c b/boards/arm/stm32f4/omnibusf4/src/stm32_max7456.c similarity index 98% rename from boards/arm/stm32/omnibusf4/src/stm32_max7456.c rename to boards/arm/stm32f4/omnibusf4/src/stm32_max7456.c index 58413d89ee70f..05c90434478ff 100644 --- a/boards/arm/stm32/omnibusf4/src/stm32_max7456.c +++ b/boards/arm/stm32f4/omnibusf4/src/stm32_max7456.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/omnibusf4/src/stm32_max7456.c + * boards/arm/stm32f4/omnibusf4/src/stm32_max7456.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f4/omnibusf4/src/stm32_mmcsd.c b/boards/arm/stm32f4/omnibusf4/src/stm32_mmcsd.c new file mode 100644 index 0000000000000..2459813e68b58 --- /dev/null +++ b/boards/arm/stm32f4/omnibusf4/src/stm32_mmcsd.c @@ -0,0 +1,105 @@ +/**************************************************************************** + * boards/arm/stm32f4/omnibusf4/src/stm32_mmcsd.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "arm_internal.h" +#include "chip.h" +#include "stm32.h" + +#include +#include "omnibusf4.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifdef CONFIG_DISABLE_MOUNTPOINT +# error "SD driver requires CONFIG_DISABLE_MOUNTPOINT to be disabled" +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_spi1register + * + * Description: + * Registers media change callback + ****************************************************************************/ + +int stm32_spi2register(struct spi_dev_s *dev, spi_mediachange_t callback, + void *arg) +{ + /* TODO: media change callback */ + + return OK; +} + +/**************************************************************************** + * Name: stm32_mmcsd_initialize + * + * Description: + * Initialize SPI-based SD card and card detect thread. + ****************************************************************************/ + +int stm32_mmcsd_initialize(int port, int minor) +{ + struct spi_dev_s *spi; + int rv; + + stm32_configgpio(GPIO_MMCSD_NCD); /* SD_DET */ + stm32_configgpio(GPIO_MMCSD_NSS); /* CS */ + + mcinfo("INFO: Initializing mmcsd port %d minor %d SD_DET %x\n", + port, minor, stm32_gpioread(GPIO_MMCSD_NCD)); + + spi = stm32_spibus_initialize(port); + if (spi == NULL) + { + mcerr("ERROR: Failed to initialize SPI port %d\n", port); + return -ENODEV; + } + + rv = mmcsd_spislotinitialize(minor, minor, spi); + if (rv < 0) + { + mcerr("ERROR: Failed to bind SPI port %d to SD slot %d\n", + port, minor); + return rv; + } + + spiinfo("INFO: mmcsd card has been initialized successfully\n"); + return OK; +} diff --git a/boards/arm/stm32/omnibusf4/src/stm32_mpu6000.c b/boards/arm/stm32f4/omnibusf4/src/stm32_mpu6000.c similarity index 98% rename from boards/arm/stm32/omnibusf4/src/stm32_mpu6000.c rename to boards/arm/stm32f4/omnibusf4/src/stm32_mpu6000.c index 9d79cf9790e83..c2957c2a7e1de 100644 --- a/boards/arm/stm32/omnibusf4/src/stm32_mpu6000.c +++ b/boards/arm/stm32f4/omnibusf4/src/stm32_mpu6000.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/omnibusf4/src/stm32_mpu6000.c + * boards/arm/stm32f4/omnibusf4/src/stm32_mpu6000.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f4/omnibusf4/src/stm32_netinit.c b/boards/arm/stm32f4/omnibusf4/src/stm32_netinit.c new file mode 100644 index 0000000000000..3360c835506fe --- /dev/null +++ b/boards/arm/stm32f4/omnibusf4/src/stm32_netinit.c @@ -0,0 +1,41 @@ +/**************************************************************************** + * boards/arm/stm32f4/omnibusf4/src/stm32_netinit.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: arm_netinitialize + ****************************************************************************/ + +#if defined(CONFIG_NET) && !defined(CONFIG_NETDEV_LATEINIT) +void arm_netinitialize(void) +{ +} +#endif diff --git a/boards/arm/stm32f4/omnibusf4/src/stm32_pm.c b/boards/arm/stm32f4/omnibusf4/src/stm32_pm.c new file mode 100644 index 0000000000000..dfe132e9f78dd --- /dev/null +++ b/boards/arm/stm32f4/omnibusf4/src/stm32_pm.c @@ -0,0 +1,75 @@ +/**************************************************************************** + * boards/arm/stm32f4/omnibusf4/src/stm32_pm.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include "arm_internal.h" +#include "stm32_pm.h" +#include "omnibusf4.h" + +#ifdef CONFIG_PM + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_pminitialize + * + * Description: + * This function is called by MCU-specific logic at power-on reset in + * order to provide one-time initialization the power management subsystem. + * This function must be called *very* early in the initialization sequence + * *before* any other device drivers are initialized (since they may + * attempt to register with the power management subsystem). + * + * Input Parameters: + * None. + * + * Returned Value: + * None. + * + ****************************************************************************/ + +void arm_pminitialize(void) +{ + /* Initialize the NuttX power management subsystem proper */ + + pm_initialize(); + +#if defined(CONFIG_ARCH_IDLE_CUSTOM) && defined(CONFIG_PM_BUTTONS) + /* Initialize the buttons to wake up the system from low power modes */ + + stm32_pm_buttons(); +#endif + + /* Initialize the LED PM */ + + stm32_led_pminitialize(); +} + +#endif /* CONFIG_PM */ diff --git a/boards/arm/stm32f4/omnibusf4/src/stm32_pwm.c b/boards/arm/stm32f4/omnibusf4/src/stm32_pwm.c new file mode 100644 index 0000000000000..41770c035b60d --- /dev/null +++ b/boards/arm/stm32f4/omnibusf4/src/stm32_pwm.c @@ -0,0 +1,113 @@ +/**************************************************************************** + * boards/arm/stm32f4/omnibusf4/src/stm32_pwm.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32_pwm.h" +#include "omnibusf4.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_pwm_setup + * + * Description: + * + * Initialize PWM and register Omnibus F4's TIM2 and TIM3 PWM devices: + * + * TIM3 CH3 PB0 S1_OUT + * TIM3 CH4 PB1 S2_OUT + * TIM2 CH4 PA3 S3_OUT + * TIM2 CH3 PA2 S4_OUT + * + ****************************************************************************/ + +int stm32_pwm_setup(void) +{ + int npwm = 0; /* hardware device enumerator */ + const char *ppwm = NULL; /* pointer to PWM device name */ + struct pwm_lowerhalf_s *pwm = NULL; /* lower-half driver handle */ + + /* Initialize TIM2 and TIM3. + * + * Ihe underlying STM32 driver "knows" there are up to four channels + * available for each timer device, so we don't have to do anything + * special here to export the two channels each that we're + * interested in. The user will want to avoid the channels that + * aren't connected to anything, however, or risk death by boredom + * from resulting non-response. + */ + + for (npwm = 2; npwm <= 3; npwm++) + { + pwm = stm32_pwminitialize(npwm); + + /* If we can't get the lower-half handle, skip and keep going. */ + + if (!pwm) + { + continue; + } + + /* Translate the peripheral number to a device name. */ + + switch (npwm) + { + case 2: + ppwm = "/dev/pwm2"; + break; + + case 3: + ppwm = "/dev/pwm3"; + break; + + /* Skip missing names. */ + + default: + continue; + } + + pwm_register(ppwm, pwm); + } + + return 0; +} diff --git a/boards/arm/stm32f4/omnibusf4/src/stm32_reset.c b/boards/arm/stm32f4/omnibusf4/src/stm32_reset.c new file mode 100644 index 0000000000000..4d6ec55831d9d --- /dev/null +++ b/boards/arm/stm32f4/omnibusf4/src/stm32_reset.c @@ -0,0 +1,56 @@ +/**************************************************************************** + * boards/arm/stm32f4/omnibusf4/src/stm32_reset.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include "stm32_dfumode.h" + +#ifdef CONFIG_BOARDCTL_RESET + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +int board_reset(int mode) +{ + if (mode == 0) + { + /* Normal reset */ + + up_systemreset(); + } + else + { + /* DFU reset */ + + stm32_dfumode(); + } +} + +#endif /* CONFIG_BOARDCTL_RESET */ diff --git a/boards/arm/stm32f4/omnibusf4/src/stm32_spi.c b/boards/arm/stm32f4/omnibusf4/src/stm32_spi.c new file mode 100644 index 0000000000000..91a4916ca6f77 --- /dev/null +++ b/boards/arm/stm32f4/omnibusf4/src/stm32_spi.c @@ -0,0 +1,155 @@ +/**************************************************************************** + * boards/arm/stm32f4/omnibusf4/src/stm32_spi.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include + +#include "arm_internal.h" +#include "chip.h" +#include "stm32.h" + +#include "omnibusf4.h" + +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || \ + defined(CONFIG_STM32_SPI3) + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_spidev_initialize + * + * Description: + * Called to configure SPI chip select GPIO pins for the omnibusf4 board. + * + ****************************************************************************/ + +void weak_function stm32_spidev_initialize(void) +{ +#ifdef CONFIG_STM32_SPI1 + stm32_configgpio(GPIO_CS_MPU6000); + stm32_configgpio(GPIO_EXTI_MPU6000); +#endif +#ifdef CONFIG_STM32_SPI3 + stm32_configgpio(GPIO_CS_MAX7456); +#endif +#if defined(CONFIG_MMCSD_SPI) + stm32_configgpio(GPIO_MMCSD_NCD); /* SD_DET */ + stm32_configgpio(GPIO_MMCSD_NSS); /* CS */ +#endif +} + +/**************************************************************************** + * Name: stm32_spi1/2/3select and stm32_spi1/2/3status + * + * Description: + * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status + * must be provided by board-specific logic. They are implementations of + * the select and status methods of the SPI interface defined by struct + * spi_ops_s (see include/nuttx/spi/spi.h). All other methods (including + * stm32_spibus_initialize()) are provided by common STM32 logic. To use + * this common SPI logic on your board: + * + * 1. Provide logic in stm32_boardinitialize() to configure SPI chip select + * pins. + * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() functions + * in your board-specific logic. These functions will perform chip + * selection and + * status operations using GPIOs in the way your board is configured. + * 3. Add a calls to stm32_spibus_initialize() in your low level + * application initialization logic + * 4. The handle returned by stm32_spibus_initialize() may then be used to + * bind the SPI driver to higher level logic (e.g., calling + * mmcsd_spislotinitialize(), for example, will bind the SPI driver to + * the SPI MMC/SD driver). + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_SPI1 +void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, + bool selected) +{ + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); + + /* Note: CS is active-low. */ + + stm32_gpiowrite(GPIO_CS_MPU6000, !selected); +} + +uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} +#endif + +#ifdef CONFIG_STM32_SPI2 +void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid, + bool selected) +{ + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); + + /* Note: NSS is active-low. */ + + stm32_gpiowrite(GPIO_MMCSD_NSS, selected ? 0 : 1); +} + +uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) +{ + /* Note: SD_DET is pulled high when there's no SD card present. */ + + return stm32_gpioread(GPIO_MMCSD_NCD) ? 0 : 1; +} +#endif + +#ifdef CONFIG_STM32_SPI3 +void stm32_spi3select(struct spi_dev_s *dev, uint32_t devid, + bool selected) +{ + spiinfo("devid: %d %s\n", + (int)devid, selected ? "assert" : "de-assert"); + + /* Note: MAX7456 CS is active-low. */ + + stm32_gpiowrite(GPIO_CS_MAX7456, selected ? 0 : 1); +} + +uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} +#endif + +#endif /* CONFIG_STM32_SPI1 || CONFIG_STM32_SPI2 || CONFIG_STM32_SPI3 */ diff --git a/boards/arm/stm32f4/omnibusf4/src/stm32_timer.c b/boards/arm/stm32f4/omnibusf4/src/stm32_timer.c new file mode 100644 index 0000000000000..c0b13b8a0a26d --- /dev/null +++ b/boards/arm/stm32f4/omnibusf4/src/stm32_timer.c @@ -0,0 +1,63 @@ +/**************************************************************************** + * boards/arm/stm32f4/omnibusf4/src/stm32_timer.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include + +#include "stm32_tim.h" +#include "omnibusf4.h" + +#ifdef CONFIG_TIMER + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_timer_driver_setup + * + * Description: + * Configure the timer driver. + * + * Input Parameters: + * devpath - The full path to the timer device. This should be of the + * form /dev/timer0 + * timer - The timer's number. + * + * Returned Value: + * Zero (OK) is returned on success; A negated errno value is returned + * to indicate the nature of any failure. + * + ****************************************************************************/ + +int stm32_timer_driver_setup(const char *devpath, int timer) +{ + return stm32_timer_initialize(devpath, timer); +} + +#endif diff --git a/boards/arm/stm32f4/omnibusf4/src/stm32_uid.c b/boards/arm/stm32f4/omnibusf4/src/stm32_uid.c new file mode 100644 index 0000000000000..5ea001248f0cd --- /dev/null +++ b/boards/arm/stm32f4/omnibusf4/src/stm32_uid.c @@ -0,0 +1,68 @@ +/**************************************************************************** + * boards/arm/stm32f4/omnibusf4/src/stm32_uid.c + * + * SPDX-License-Identifier: BSD-3-Clause + * SPDX-FileCopyrightText: 2015 Marawan Ragab. All rights reserved. + * SPDX-FileContributor: Marawan Ragab + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include "stm32_uid.h" + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +#if defined(CONFIG_BOARDCTL_UNIQUEID) +int board_uniqueid(uint8_t *uniqueid) +{ + if (uniqueid == NULL) + { + return -EINVAL; + } + + stm32_get_uniqueid(uniqueid); + return OK; +} +#endif diff --git a/boards/arm/stm32f4/omnibusf4/src/stm32_usb.c b/boards/arm/stm32f4/omnibusf4/src/stm32_usb.c new file mode 100644 index 0000000000000..d229c176ce9ed --- /dev/null +++ b/boards/arm/stm32f4/omnibusf4/src/stm32_usb.c @@ -0,0 +1,338 @@ +/**************************************************************************** + * boards/arm/stm32f4/omnibusf4/src/stm32_usb.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include "arm_internal.h" +#include "stm32.h" +#include "stm32_otgfs.h" +#include "omnibusf4.h" + +#ifdef CONFIG_STM32_OTGFS + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#if defined(CONFIG_USBDEV) || defined(CONFIG_USBHOST) +# define HAVE_USB 1 +#else +# warning "CONFIG_STM32_OTGFS is enabled but neither CONFIG_USBDEV nor CONFIG_USBHOST" +# undef HAVE_USB +#endif + +#ifndef CONFIG_OMNIBUSF4_USBHOST_PRIO +# define CONFIG_OMNIBUSF4_USBHOST_PRIO 100 +#endif + +#ifndef CONFIG_OMNIBUSF4_USBHOST_STACKSIZE +# define CONFIG_OMNIBUSF4_USBHOST_STACKSIZE 1024 +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +static struct usbhost_connection_s *g_usbconn; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: usbhost_waiter + * + * Description: + * Wait for USB devices to be connected. + * + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +static int usbhost_waiter(int argc, char *argv[]) +{ + struct usbhost_hubport_s *hport; + + uinfo("Running\n"); + for (; ; ) + { + /* Wait for the device to change state */ + + DEBUGVERIFY(CONN_WAIT(g_usbconn, &hport)); + uinfo("%s\n", hport->connected ? "connected" : "disconnected"); + + /* Did we just become connected? */ + + if (hport->connected) + { + /* Yes.. enumerate the newly connected device */ + + CONN_ENUMERATE(g_usbconn, hport); + } + } + + /* Keep the compiler from complaining */ + + return 0; +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_usbinitialize + * + * Description: + * Called from stm32_usbinitialize very early in initialization to setup + * USB-related GPIO pins for the Omnibusf4 board. + * + ****************************************************************************/ + +void stm32_usbinitialize(void) +{ + /* The OTG FS has an internal soft pull-up. + * No GPIO configuration is required + */ + + /* Configure the OTG FS VBUS sensing GPIO, + * Power On, and Overcurrent GPIOs + */ + +#ifdef CONFIG_STM32_OTGFS + stm32_configgpio(GPIO_OTGFS_VBUS); +#endif +} + +/**************************************************************************** + * Name: stm32_usbhost_initialize + * + * Description: + * Called at application startup time to initialize the USB host + * functionality. + * This function will start a thread that will monitor for device + * connection/disconnection events. + * + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +int stm32_usbhost_initialize(void) +{ + int ret; + + /* First, register all of the class drivers needed to support the drivers + * that we care about: + */ + + uinfo("Register class drivers\n"); + +#ifdef CONFIG_USBHOST_HUB + /* Initialize USB hub class support */ + + ret = usbhost_hub_initialize(); + if (ret < 0) + { + uerr("ERROR: usbhost_hub_initialize failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_USBHOST_MSC + /* Register the USB mass storage class class */ + + ret = usbhost_msc_initialize(); + if (ret != OK) + { + uerr("ERROR: Failed to register the mass storage class: %d\n", ret); + } +#endif + +#ifdef CONFIG_USBHOST_CDCACM + /* Register the CDC/ACM serial class */ + + ret = usbhost_cdcacm_initialize(); + if (ret != OK) + { + uerr("ERROR: Failed to register the CDC/ACM serial class: %d\n", ret); + } +#endif + +#ifdef CONFIG_USBHOST_HIDKBD + /* Initialize the HID keyboard class */ + + ret = usbhost_kbdinit(); + if (ret != OK) + { + uerr("ERROR: Failed to register the HID keyboard class\n"); + } +#endif + +#ifdef CONFIG_USBHOST_HIDMOUSE + /* Initialize the HID mouse class */ + + ret = usbhost_mouse_init(); + if (ret != OK) + { + uerr("ERROR: Failed to register the HID mouse class\n"); + } +#endif + +#ifdef CONFIG_USBHOST_XBOXCONTROLLER + /* Initialize the HID mouse class */ + + ret = usbhost_xboxcontroller_init(); + if (ret != OK) + { + uerr("ERROR: Failed to register the XBox Controller class\n"); + } +#endif + + /* Then get an instance of the USB host interface */ + + uinfo("Initialize USB host\n"); + g_usbconn = stm32_otgfshost_initialize(0); + if (g_usbconn) + { + /* Start a thread to handle device connection. */ + + uinfo("Start usbhost_waiter\n"); + + ret = kthread_create("usbhost", CONFIG_OMNIBUSF4_USBHOST_PRIO, + CONFIG_OMNIBUSF4_USBHOST_STACKSIZE, + usbhost_waiter, NULL); + return ret < 0 ? -ENOEXEC : OK; + } + + return -ENODEV; +} +#endif + +/**************************************************************************** + * Name: stm32_usbhost_vbusdrive + * + * Description: + * Enable/disable driving of VBUS 5V output. This function must be + * provided be each platform that implements the STM32 OTG FS host + * interface + * + * "On-chip 5 V VBUS generation is not supported. For this reason, a + * charge pump or, if 5 V are available on the application board, a + * basic power switch, must be added externally to drive the 5 V VBUS + * line. The external charge pump can be driven by any GPIO output. + * When the application decides to power on VBUS using the chosen GPIO, + * it must also set the port power bit in the host port control and + * status register (PPWR bit in OTG_FS_HPRT). + * + * "The application uses this field to control power to this port, + * and the core clears this bit on an overcurrent condition." + * + * Input Parameters: + * iface - For future growth to handle multiple USB host interface. + * Should be zero. + * enable - true: enable VBUS power; false: disable VBUS power + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +void stm32_usbhost_vbusdrive(int iface, bool enable) +{ + DEBUGASSERT(iface == 0); + + if (enable) + { + /* Enable the Power Switch by driving the enable pin low */ + + stm32_gpiowrite(GPIO_OTGFS_PWRON, false); + } + else + { + /* Disable the Power Switch by driving the enable pin high */ + + stm32_gpiowrite(GPIO_OTGFS_PWRON, true); + } +} +#endif + +/**************************************************************************** + * Name: stm32_setup_overcurrent + * + * Description: + * Setup to receive an interrupt-level callback if an overcurrent + * condition is detected. + * + * Input Parameters: + * handler - New overcurrent interrupt handler + * arg - The argument provided for the interrupt handler + * + * Returned Value: + * Zero (OK) is returned on success. Otherwise, a negated errno value + * is returned to indicate the nature of the failure. + * + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +int stm32_setup_overcurrent(xcpt_t handler, void *arg) +{ + return stm32_gpiosetevent(GPIO_OTGFS_OVER, true, true, true, handler, arg); +} +#endif + +/**************************************************************************** + * Name: stm32_usbsuspend + * + * Description: + * Board logic must provide the stm32_usbsuspend logic if the USBDEV + * driver is used. This function is called whenever the USB enters or + * leaves suspend mode. This is an opportunity for the board logic to + * shutdown clocks, power, etc. while the USB is suspended. + * + ****************************************************************************/ + +#ifdef CONFIG_USBDEV +void stm32_usbsuspend(struct usbdev_s *dev, bool resume) +{ + uinfo("resume: %d\n", resume); +} +#endif + +#endif /* CONFIG_STM32_OTGFS */ diff --git a/boards/arm/stm32f4/omnibusf4/src/stm32_usbmsc.c b/boards/arm/stm32f4/omnibusf4/src/stm32_usbmsc.c new file mode 100644 index 0000000000000..5fb5e1124971d --- /dev/null +++ b/boards/arm/stm32f4/omnibusf4/src/stm32_usbmsc.c @@ -0,0 +1,71 @@ +/**************************************************************************** + * boards/arm/stm32f4/omnibusf4/src/stm32_usbmsc.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include + +#include "stm32.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +#ifndef CONFIG_SYSTEM_USBMSC_DEVMINOR1 +# define CONFIG_SYSTEM_USBMSC_DEVMINOR1 0 +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_usbmsc_initialize + * + * Description: + * Perform architecture specific initialization of the USB MSC device. + * + ****************************************************************************/ + +int board_usbmsc_initialize(int port) +{ + /* If system/usbmsc is built as an NSH command, then SD slot should + * already have been initialized. + * In this case, there is nothing further to be done here. + */ + +#ifndef CONFIG_NSH_BUILTIN_APPS + return stm32_sdinitialize(CONFIG_SYSTEM_USBMSC_DEVMINOR1); +#else + return OK; +#endif +} diff --git a/boards/arm/stm32f4/omnibusf4/src/stm32_userleds.c b/boards/arm/stm32f4/omnibusf4/src/stm32_userleds.c new file mode 100644 index 0000000000000..ecfafda5b1fac --- /dev/null +++ b/boards/arm/stm32f4/omnibusf4/src/stm32_userleds.c @@ -0,0 +1,217 @@ +/**************************************************************************** + * boards/arm/stm32f4/omnibusf4/src/stm32_userleds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32.h" +#include "omnibusf4.h" + +#ifndef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* This array maps an LED number to GPIO pin configuration */ + +static uint32_t g_ledcfg[BOARD_NLEDS] = +{ + GPIO_LED1, + GPIO_BEEPER1 +}; + +/**************************************************************************** + * Private Function Protototypes + ****************************************************************************/ + +/* LED Power Management */ + +#ifdef CONFIG_PM +static void led_pm_notify(struct pm_callback_s *cb, int domain, + enum pm_state_e pmstate); +static int led_pm_prepare(struct pm_callback_s *cb, int domain, + enum pm_state_e pmstate); +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#ifdef CONFIG_PM +static struct pm_callback_s g_ledscb = +{ + .notify = led_pm_notify, + .prepare = led_pm_prepare, +}; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: led_pm_notify + * + * Description: + * Notify the driver of new power state. This callback is called after + * all drivers have had the opportunity to prepare for the new power state. + * + ****************************************************************************/ + +#ifdef CONFIG_PM +static void led_pm_notify(struct pm_callback_s *cb, int domain, + enum pm_state_e pmstate) +{ + switch (pmstate) + { + case PM_NORMAL: + { + /* Restore normal LEDs operation */ + } + break; + + case PM_IDLE: + { + /* Entering IDLE mode - Turn leds off */ + } + break; + + case PM_STANDBY: + { + /* Entering STANDBY mode - Logic for PM_STANDBY goes here */ + } + break; + + case PM_SLEEP: + { + /* Entering SLEEP mode - Logic for PM_SLEEP goes here */ + } + break; + + default: + { + /* Should not get here */ + } + break; + } +} +#endif + +/**************************************************************************** + * Name: led_pm_prepare + * + * Description: + * Request the driver to prepare for a new power state. This is a warning + * that the system is about to enter into a new power state. The driver + * should begin whatever operations that may be required to enter power + * state. The driver may abort the state change mode by returning a + * non-zero value from the callback function. + * + ****************************************************************************/ + +#ifdef CONFIG_PM +static int led_pm_prepare(struct pm_callback_s *cb, int domain, + enum pm_state_e pmstate) +{ + /* No preparation to change power modes is required by the LEDs driver. + * We always accept the state change by returning OK. + */ + + return OK; +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_userled_initialize + ****************************************************************************/ + +uint32_t board_userled_initialize(void) +{ + for (unsigned wled = 0; wled < BOARD_NLEDS; wled++) + { + stm32_configgpio(g_ledcfg[wled]); + } + + return BOARD_NLEDS; +} + +/**************************************************************************** + * Name: board_userled + ****************************************************************************/ + +void board_userled(int led, bool ledon) +{ + if ((unsigned)led < BOARD_NLEDS) + { + stm32_gpiowrite(g_ledcfg[led], ledon); + } +} + +/**************************************************************************** + * Name: board_userled_all + ****************************************************************************/ + +void board_userled_all(uint32_t ledset) +{ + for (unsigned wled = 0; wled < BOARD_NLEDS; wled++) + { + stm32_gpiowrite(g_ledcfg[wled], + (ledset & (1 << wled)) == 0 ? 1 : 0); + } +} + +/**************************************************************************** + * Name: stm32_led_pminitialize + ****************************************************************************/ + +#ifdef CONFIG_PM +void stm32_led_pminitialize(void) +{ + /* Register to receive power management callbacks */ + + int ret = pm_register(&g_ledscb); + if (ret != OK) + { + board_autoled_on(LED_ASSERTION); + } +} +#endif /* CONFIG_PM */ + +#endif /* !CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32f4/stm3240g-eval/CMakeLists.txt b/boards/arm/stm32f4/stm3240g-eval/CMakeLists.txt new file mode 100644 index 0000000000000..efa9246cf956b --- /dev/null +++ b/boards/arm/stm32f4/stm3240g-eval/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32f4/stm3240g-eval/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/arm/stm32/stm3240g-eval/Kconfig b/boards/arm/stm32f4/stm3240g-eval/Kconfig similarity index 100% rename from boards/arm/stm32/stm3240g-eval/Kconfig rename to boards/arm/stm32f4/stm3240g-eval/Kconfig diff --git a/boards/arm/stm32f4/stm3240g-eval/configs/dhcpd/defconfig b/boards/arm/stm32f4/stm3240g-eval/configs/dhcpd/defconfig new file mode 100644 index 0000000000000..f6c6f56690768 --- /dev/null +++ b/boards/arm/stm32f4/stm3240g-eval/configs/dhcpd/defconfig @@ -0,0 +1,62 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_NETUTILS_DHCPD_IGNOREBROADCAST is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm3240g-eval" +CONFIG_ARCH_BOARD_STM3240G_EVAL=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F407IG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_DISABLE_ENVIRON=y +CONFIG_DISABLE_MOUNTPOINT=y +CONFIG_DISABLE_MQUEUE=y +CONFIG_DISABLE_PTHREAD=y +CONFIG_ETH0_PHY_DP83848C=y +CONFIG_EXAMPLES_DHCPD=y +CONFIG_EXAMPLES_DHCPD_NOMAC=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_HOST_WINDOWS=y +CONFIG_INIT_ENTRYPOINT="dhcpd_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_MM_REGIONS=2 +CONFIG_NET=y +CONFIG_NETUTILS_DHCPD=y +CONFIG_NETUTILS_NETLIB=y +CONFIG_NET_BROADCAST=y +CONFIG_NET_SOCKOPTS=y +CONFIG_NET_UDP=y +CONFIG_NET_UDP_CHECKSUMS=y +CONFIG_NUNGET_CHARS=0 +CONFIG_RAM_SIZE=196608 +CONFIG_RAM_START=0x20000000 +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=13 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_STDIO_DISABLE_BUFFERING=y +CONFIG_STM32_DFU=y +CONFIG_STM32_ETHMAC=y +CONFIG_STM32_JTAG_FULL_ENABLE=y +CONFIG_STM32_MII=y +CONFIG_STM32_PHYSR=16 +CONFIG_STM32_PHYSR_100MBPS=0x0000 +CONFIG_STM32_PHYSR_FULLDUPLEX=0x0004 +CONFIG_STM32_PHYSR_MODE=0x0004 +CONFIG_STM32_PHYSR_SPEED=0x0002 +CONFIG_STM32_USART3=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART3_RXBUFSIZE=128 +CONFIG_USART3_SERIAL_CONSOLE=y +CONFIG_USART3_TXBUFSIZE=128 diff --git a/boards/arm/stm32f4/stm3240g-eval/configs/discover/defconfig b/boards/arm/stm32f4/stm3240g-eval/configs/discover/defconfig new file mode 100644 index 0000000000000..616c7e441cb72 --- /dev/null +++ b/boards/arm/stm32f4/stm3240g-eval/configs/discover/defconfig @@ -0,0 +1,70 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm3240g-eval" +CONFIG_ARCH_BOARD_STM3240G_EVAL=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F407IG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_DISCOVER_DESCR="STM3240G-EVAL" +CONFIG_ETH0_PHY_DP83848C=y +CONFIG_EXAMPLES_DISCOVER=y +CONFIG_EXAMPLES_DISCOVER_DHCPC=y +CONFIG_EXAMPLES_DISCOVER_DRIPADDR=0xc0a80201 +CONFIG_EXAMPLES_DISCOVER_NOMAC=y +CONFIG_FAT_LCNAMES=y +CONFIG_FAT_LFN=y +CONFIG_FS_FAT=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_I2C=y +CONFIG_I2C_POLLED=y +CONFIG_INIT_ENTRYPOINT="discover_main" +CONFIG_MM_REGIONS=2 +CONFIG_NET=y +CONFIG_NETDB_DNSCLIENT_ENTRIES=4 +CONFIG_NET_ARP_IPIN=y +CONFIG_NET_BROADCAST=y +CONFIG_NET_ETH_PKTSIZE=650 +CONFIG_NET_ICMP_SOCKET=y +CONFIG_NET_MAX_LISTENPORTS=40 +CONFIG_NET_STATISTICS=y +CONFIG_NET_TCP=y +CONFIG_NET_TCP_PREALLOC_CONNS=40 +CONFIG_NET_UDP=y +CONFIG_NET_UDP_CHECKSUMS=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=196608 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_STM32_ETHMAC=y +CONFIG_STM32_I2C1=y +CONFIG_STM32_JTAG_FULL_ENABLE=y +CONFIG_STM32_MII=y +CONFIG_STM32_PHYSR=16 +CONFIG_STM32_PHYSR_100MBPS=0x0000 +CONFIG_STM32_PHYSR_FULLDUPLEX=0x0004 +CONFIG_STM32_PHYSR_MODE=0x0004 +CONFIG_STM32_PHYSR_SPEED=0x0002 +CONFIG_STM32_PWR=y +CONFIG_STM32_USART3=y +CONFIG_SYSTEM_PING=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART3_RXBUFSIZE=128 +CONFIG_USART3_SERIAL_CONSOLE=y +CONFIG_USART3_TXBUFSIZE=128 diff --git a/boards/arm/stm32f4/stm3240g-eval/configs/fb/defconfig b/boards/arm/stm32f4/stm3240g-eval/configs/fb/defconfig new file mode 100644 index 0000000000000..7658129cd2b0b --- /dev/null +++ b/boards/arm/stm32f4/stm3240g-eval/configs/fb/defconfig @@ -0,0 +1,72 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm3240g-eval" +CONFIG_ARCH_BOARD_STM3240G_EVAL=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F407IG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_DRIVERS_VIDEO=y +CONFIG_EXAMPLES_FB=y +CONFIG_EXAMPLES_PDCURSES=y +CONFIG_FS_PROCFS=y +CONFIG_GRAPHICS_PDCURSES=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_HEAP2_BASE=0x64000000 +CONFIG_HEAP2_SIZE=2097152 +CONFIG_HOST_WINDOWS=y +CONFIG_I2C=y +CONFIG_I2C_POLLED=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LCD=y +CONFIG_LCD_FRAMEBUFFER=y +CONFIG_LCD_MAXCONTRAST=1 +CONFIG_LCD_NOGETRUN=y +CONFIG_LINE_MAX=64 +CONFIG_MM_REGIONS=3 +CONFIG_MQ_MAXMSGSIZE=64 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_DISABLE_IFUPDOWN=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_NXFONTS_DISABLE_1BPP=y +CONFIG_NXFONTS_DISABLE_24BPP=y +CONFIG_NXFONTS_DISABLE_2BPP=y +CONFIG_NXFONTS_DISABLE_32BPP=y +CONFIG_NXFONTS_DISABLE_4BPP=y +CONFIG_NXFONTS_DISABLE_8BPP=y +CONFIG_PDCURSES_FONT_6X9=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=196608 +CONFIG_RAM_START=0x20000000 +CONFIG_RR_INTERVAL=200 +CONFIG_RTC_DATETIME=y +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=17 +CONFIG_START_MONTH=9 +CONFIG_STM32_EXTERNAL_RAM=y +CONFIG_STM32_FSMC=y +CONFIG_STM32_I2C1=y +CONFIG_STM32_JTAG_FULL_ENABLE=y +CONFIG_STM32_PWR=y +CONFIG_STM32_RTC=y +CONFIG_STM32_USART3=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART3_RXBUFSIZE=128 +CONFIG_USART3_SERIAL_CONSOLE=y +CONFIG_USART3_TXBUFSIZE=128 +CONFIG_VIDEO_FB=y diff --git a/boards/arm/stm32f4/stm3240g-eval/configs/knxwm/Make.defs b/boards/arm/stm32f4/stm3240g-eval/configs/knxwm/Make.defs new file mode 100644 index 0000000000000..bdadecf86030b --- /dev/null +++ b/boards/arm/stm32f4/stm3240g-eval/configs/knxwm/Make.defs @@ -0,0 +1,40 @@ +############################################################################ +# boards/arm/stm32f4/stm3240g-eval/configs/knxwm/Make.defs +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/.config +include $(TOPDIR)/tools/Config.mk +include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs + +ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)memory.ld +ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)kernel-space.ld + +ARCHCXXFLAGS += -fpermissive +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32f4/stm3240g-eval/configs/knxwm/defconfig b/boards/arm/stm32f4/stm3240g-eval/configs/knxwm/defconfig new file mode 100644 index 0000000000000..8e78252589727 --- /dev/null +++ b/boards/arm/stm32f4/stm3240g-eval/configs/knxwm/defconfig @@ -0,0 +1,99 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_NXFONTS_DISABLE_16BPP is not set +# CONFIG_NXTK_DEFAULT_BORDERCOLORS is not set +# CONFIG_NXWM_NXTERM is not set +# CONFIG_NX_DISABLE_16BPP is not set +# CONFIG_NX_PACKEDMSFIRST is not set +# CONFIG_NX_WRITEONLY is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm3240g-eval" +CONFIG_ARCH_BOARD_STM3240G_EVAL=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F407IG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_ARM_MPU=y +CONFIG_ARM_TOOLCHAIN_BUILDROOT=y +CONFIG_BOARDCTL=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILD_PROTECTED=y +CONFIG_FAT_LCNAMES=y +CONFIG_FAT_LFN=y +CONFIG_FS_FAT=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_HOST_WINDOWS=y +CONFIG_I2C_POLLED=y +CONFIG_INIT_ENTRYPOINT="nxwm_main" +CONFIG_INPUT=y +CONFIG_INPUT_STMPE811=y +CONFIG_INTELHEX_BINARY=y +CONFIG_LCD=y +CONFIG_LCD_MAXCONTRAST=1 +CONFIG_LCD_NOGETRUN=y +CONFIG_LIBC_MAX_EXITFUNS=1 +CONFIG_LIBC_USRWORK=y +CONFIG_MM_REGIONS=2 +CONFIG_MQ_MAXMSGSIZE=64 +CONFIG_NUTTX_USERSPACE=0x08040000 +CONFIG_NX=y +CONFIG_NXFONT_SANS22X29B=y +CONFIG_NXFONT_SANS23X27=y +CONFIG_NXSTART_SERVERSTACK=1596 +CONFIG_NXTK_BORDERCOLOR1=0x5cb7 +CONFIG_NXTK_BORDERCOLOR2=0x21c9 +CONFIG_NXTK_BORDERCOLOR3=0xffdf +CONFIG_NXWIDGETS=y +CONFIG_NXWIDGETS_BPP=16 +CONFIG_NXWIDGETS_CUSTOM_EDGECOLORS=y +CONFIG_NXWIDGETS_CUSTOM_FILLCOLORS=y +CONFIG_NXWIDGETS_DEFAULT_BACKGROUNDCOLOR=0x9dfb +CONFIG_NXWIDGETS_DEFAULT_HIGHLIGHTCOLOR=0xc618 +CONFIG_NXWIDGETS_DEFAULT_SELECTEDBACKGROUNDCOLOR=0xd73e +CONFIG_NXWIDGETS_DEFAULT_SHADOWEDGECOLOR=0x21e9 +CONFIG_NXWIDGETS_DEFAULT_SHINEEDGECOLOR=0xffdf +CONFIG_NXWIDGETS_SIZEOFCHAR=1 +CONFIG_NXWM=y +CONFIG_NXWM_HEXCALCULATOR_CUSTOM_FONTID=y +CONFIG_NXWM_HEXCALCULATOR_FONTID=5 +CONFIG_NXWM_KEYBOARD=y +CONFIG_NXWM_TASKBAR_LEFT=y +CONFIG_NXWM_TASKBAR_VSPACING=4 +CONFIG_NX_BLOCKING=y +CONFIG_NX_KBD=y +CONFIG_NX_XYINPUT_TOUCHSCREEN=y +CONFIG_PASS1_BUILDIR="boards/arm/stm32f4/stm3240g-eval/kernel" +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=196608 +CONFIG_RAM_START=0x20000000 +CONFIG_RR_INTERVAL=200 +CONFIG_RTC_DATETIME=y +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=192 +CONFIG_SCHED_WAITPID=y +CONFIG_STM32_DFU=y +CONFIG_STM32_FSMC=y +CONFIG_STM32_I2C1=y +CONFIG_STM32_JTAG_FULL_ENABLE=y +CONFIG_STM32_PWR=y +CONFIG_STM32_RTC=y +CONFIG_STM32_USART3=y +CONFIG_STMPE811_ACTIVELOW=y +CONFIG_STMPE811_EDGE=y +CONFIG_STMPE811_MULTIPLE=y +CONFIG_STMPE811_THRESHX=39 +CONFIG_STMPE811_THRESHY=51 +CONFIG_SYMTAB_ORDEREDBYNAME=y +CONFIG_SYSTEM_READLINE=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART3_RXBUFSIZE=128 +CONFIG_USART3_SERIAL_CONSOLE=y +CONFIG_USART3_TXBUFSIZE=128 diff --git a/boards/arm/stm32f4/stm3240g-eval/configs/nettest/defconfig b/boards/arm/stm32f4/stm3240g-eval/configs/nettest/defconfig new file mode 100644 index 0000000000000..1f3385947f2d1 --- /dev/null +++ b/boards/arm/stm32f4/stm3240g-eval/configs/nettest/defconfig @@ -0,0 +1,62 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm3240g-eval" +CONFIG_ARCH_BOARD_STM3240G_EVAL=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F407IG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_CONSOLE_SYSLOG=y +CONFIG_DISABLE_ENVIRON=y +CONFIG_DISABLE_MOUNTPOINT=y +CONFIG_DISABLE_MQUEUE=y +CONFIG_DISABLE_PTHREAD=y +CONFIG_ETH0_PHY_DP83848C=y +CONFIG_EXAMPLES_NETTEST=y +CONFIG_EXAMPLES_NETTEST_NOMAC=y +CONFIG_EXAMPLES_NETTEST_PERFORMANCE=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_HOST_WINDOWS=y +CONFIG_INIT_ENTRYPOINT="nettest_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_MM_REGIONS=2 +CONFIG_NET=y +CONFIG_NETUTILS_NETLIB=y +CONFIG_NET_MAX_LISTENPORTS=40 +CONFIG_NET_SOCKOPTS=y +CONFIG_NET_TCP=y +CONFIG_NET_TCP_PREALLOC_CONNS=40 +CONFIG_NUNGET_CHARS=0 +CONFIG_RAM_SIZE=196608 +CONFIG_RAM_START=0x20000000 +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_STDIO_DISABLE_BUFFERING=y +CONFIG_STM32_DFU=y +CONFIG_STM32_ETHMAC=y +CONFIG_STM32_JTAG_FULL_ENABLE=y +CONFIG_STM32_MII=y +CONFIG_STM32_PHYSR=16 +CONFIG_STM32_PHYSR_100MBPS=0x0000 +CONFIG_STM32_PHYSR_FULLDUPLEX=0x0004 +CONFIG_STM32_PHYSR_MODE=0x0004 +CONFIG_STM32_PHYSR_SPEED=0x0002 +CONFIG_STM32_USART3=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART3_RXBUFSIZE=128 +CONFIG_USART3_SERIAL_CONSOLE=y +CONFIG_USART3_TXBUFSIZE=128 diff --git a/boards/arm/stm32f4/stm3240g-eval/configs/nsh/defconfig b/boards/arm/stm32f4/stm3240g-eval/configs/nsh/defconfig new file mode 100644 index 0000000000000..80a98d96abb30 --- /dev/null +++ b/boards/arm/stm32f4/stm3240g-eval/configs/nsh/defconfig @@ -0,0 +1,82 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm3240g-eval" +CONFIG_ARCH_BOARD_STM3240G_EVAL=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F407IG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_ETH0_PHY_DP83848C=y +CONFIG_FAT_LCNAMES=y +CONFIG_FAT_LFN=y +CONFIG_FS_FAT=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_HOST_WINDOWS=y +CONFIG_I2C=y +CONFIG_I2CTOOL_DEFFREQ=100000 +CONFIG_I2CTOOL_MINBUS=1 +CONFIG_I2C_POLLED=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_MM_REGIONS=2 +CONFIG_NET=y +CONFIG_NETDB_DNSCLIENT=y +CONFIG_NETDB_DNSCLIENT_ENTRIES=4 +CONFIG_NETDB_DNSSERVER_NOADDR=y +CONFIG_NETINIT_NOMAC=y +CONFIG_NETUTILS_TELNETD=y +CONFIG_NETUTILS_TFTPC=y +CONFIG_NETUTILS_WEBCLIENT=y +CONFIG_NET_BROADCAST=y +CONFIG_NET_ICMP_SOCKET=y +CONFIG_NET_MAX_LISTENPORTS=40 +CONFIG_NET_STATISTICS=y +CONFIG_NET_TCP=y +CONFIG_NET_TCP_PREALLOC_CONNS=40 +CONFIG_NET_UDP=y +CONFIG_NET_UDP_CHECKSUMS=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=196608 +CONFIG_RAM_START=0x20000000 +CONFIG_RR_INTERVAL=200 +CONFIG_RTC_DATETIME=y +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_WAITPID=y +CONFIG_STM32_ETHMAC=y +CONFIG_STM32_I2C1=y +CONFIG_STM32_JTAG_FULL_ENABLE=y +CONFIG_STM32_MII=y +CONFIG_STM32_PHYSR=16 +CONFIG_STM32_PHYSR_100MBPS=0x0000 +CONFIG_STM32_PHYSR_FULLDUPLEX=0x0004 +CONFIG_STM32_PHYSR_MODE=0x0004 +CONFIG_STM32_PHYSR_SPEED=0x0002 +CONFIG_STM32_PWR=y +CONFIG_STM32_RNG=y +CONFIG_STM32_RTC=y +CONFIG_STM32_USART3=y +CONFIG_SYMTAB_ORDEREDBYNAME=y +CONFIG_SYSTEM_I2CTOOL=y +CONFIG_SYSTEM_NSH=y +CONFIG_SYSTEM_PING=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART3_RXBUFSIZE=128 +CONFIG_USART3_SERIAL_CONSOLE=y +CONFIG_USART3_TXBUFSIZE=128 diff --git a/boards/arm/stm32f4/stm3240g-eval/configs/nsh2/defconfig b/boards/arm/stm32f4/stm3240g-eval/configs/nsh2/defconfig new file mode 100644 index 0000000000000..005e9e04a08fe --- /dev/null +++ b/boards/arm/stm32f4/stm3240g-eval/configs/nsh2/defconfig @@ -0,0 +1,91 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_DEV_CONSOLE is not set +# CONFIG_MMCSD_HAVE_CARDDETECT is not set +# CONFIG_MMCSD_MMCSUPPORT is not set +# CONFIG_NSH_CONSOLE is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm3240g-eval" +CONFIG_ARCH_BOARD_STM3240G_EVAL=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F407IG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_ETH0_PHY_DP83848C=y +CONFIG_FAT_LCNAMES=y +CONFIG_FAT_LFN=y +CONFIG_FS_FAT=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_HOST_WINDOWS=y +CONFIG_I2C=y +CONFIG_I2CTOOL_DEFFREQ=100000 +CONFIG_I2CTOOL_MINBUS=1 +CONFIG_I2C_POLLED=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_MMCSD=y +CONFIG_MMCSD_MULTIBLOCK_LIMIT=1 +CONFIG_MMCSD_SDIO=y +CONFIG_MTD=y +CONFIG_NET=y +CONFIG_NETDB_DNSCLIENT=y +CONFIG_NETDB_DNSCLIENT_ENTRIES=4 +CONFIG_NETDB_DNSSERVER_NOADDR=y +CONFIG_NETINIT_NOMAC=y +CONFIG_NETUTILS_TELNETD=y +CONFIG_NETUTILS_TFTPC=y +CONFIG_NETUTILS_WEBCLIENT=y +CONFIG_NET_BROADCAST=y +CONFIG_NET_ICMP_SOCKET=y +CONFIG_NET_MAX_LISTENPORTS=40 +CONFIG_NET_STATISTICS=y +CONFIG_NET_TCP=y +CONFIG_NET_TCP_PREALLOC_CONNS=40 +CONFIG_NET_UDP=y +CONFIG_NET_UDP_CHECKSUMS=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAMLOG=y +CONFIG_RAMLOG_SYSLOG=y +CONFIG_RAM_SIZE=196608 +CONFIG_RAM_START=0x20000000 +CONFIG_RR_INTERVAL=200 +CONFIG_RTC_DATETIME=y +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=192 +CONFIG_SCHED_HPWORKSTACKSIZE=1024 +CONFIG_SCHED_WAITPID=y +CONFIG_STM32_DFU=y +CONFIG_STM32_DMA2=y +CONFIG_STM32_ETHMAC=y +CONFIG_STM32_I2C1=y +CONFIG_STM32_JTAG_FULL_ENABLE=y +CONFIG_STM32_MII=y +CONFIG_STM32_PHYSR=16 +CONFIG_STM32_PHYSR_100MBPS=0x0000 +CONFIG_STM32_PHYSR_FULLDUPLEX=0x0004 +CONFIG_STM32_PHYSR_MODE=0x0004 +CONFIG_STM32_PHYSR_SPEED=0x0002 +CONFIG_STM32_PWR=y +CONFIG_STM32_RTC=y +CONFIG_STM32_SDIO=y +CONFIG_SYMTAB_ORDEREDBYNAME=y +CONFIG_SYSTEM_I2CTOOL=y +CONFIG_SYSTEM_NSH=y +CONFIG_SYSTEM_PING=y +CONFIG_TASK_NAME_SIZE=0 diff --git a/boards/arm/stm32f4/stm3240g-eval/configs/nxterm/defconfig b/boards/arm/stm32f4/stm3240g-eval/configs/nxterm/defconfig new file mode 100644 index 0000000000000..25740c07a6c71 --- /dev/null +++ b/boards/arm/stm32f4/stm3240g-eval/configs/nxterm/defconfig @@ -0,0 +1,104 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_NXFONTS_DISABLE_16BPP is not set +# CONFIG_NXTK_DEFAULT_BORDERCOLORS is not set +# CONFIG_NX_DISABLE_16BPP is not set +# CONFIG_NX_PACKEDMSFIRST is not set +# CONFIG_NX_WRITEONLY is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm3240g-eval" +CONFIG_ARCH_BOARD_STM3240G_EVAL=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F407IG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_ETH0_PHY_DP83848C=y +CONFIG_EXAMPLES_NXTERM=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_HEAP2_BASE=0x64000000 +CONFIG_HEAP2_SIZE=2097152 +CONFIG_HOST_WINDOWS=y +CONFIG_I2C=y +CONFIG_I2CTOOL_DEFFREQ=100000 +CONFIG_I2CTOOL_MINBUS=1 +CONFIG_I2C_POLLED=y +CONFIG_INIT_ENTRYPOINT="nxterm_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LCD=y +CONFIG_LCD_MAXCONTRAST=1 +CONFIG_LCD_NOGETRUN=y +CONFIG_LINE_MAX=64 +CONFIG_MM_REGIONS=3 +CONFIG_MQ_MAXMSGSIZE=64 +CONFIG_NET=y +CONFIG_NETDB_DNSCLIENT=y +CONFIG_NETDB_DNSCLIENT_ENTRIES=4 +CONFIG_NETDB_DNSSERVER_NOADDR=y +CONFIG_NETINIT_NOMAC=y +CONFIG_NETUTILS_TELNETD=y +CONFIG_NETUTILS_TFTPC=y +CONFIG_NETUTILS_WEBCLIENT=y +CONFIG_NET_BROADCAST=y +CONFIG_NET_ICMP_SOCKET=y +CONFIG_NET_MAX_LISTENPORTS=40 +CONFIG_NET_STATISTICS=y +CONFIG_NET_TCP=y +CONFIG_NET_TCP_PREALLOC_CONNS=40 +CONFIG_NET_UDP=y +CONFIG_NET_UDP_CHECKSUMS=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_LIBRARY=y +CONFIG_NSH_READLINE=y +CONFIG_NX=y +CONFIG_NXFONT_SANS23X27=y +CONFIG_NXTERM=y +CONFIG_NXTERM_CACHESIZE=32 +CONFIG_NXTERM_CURSORCHAR=95 +CONFIG_NXTERM_MXCHARS=256 +CONFIG_NXTK_BORDERCOLOR1=0xad55 +CONFIG_NXTK_BORDERCOLOR2=0x6b4d +CONFIG_NXTK_BORDERCOLOR3=0xdedb +CONFIG_NX_BLOCKING=y +CONFIG_NX_KBD=y +CONFIG_NX_XYINPUT_MOUSE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=196608 +CONFIG_RAM_START=0x20000000 +CONFIG_RR_INTERVAL=200 +CONFIG_RTC_DATETIME=y +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_WAITPID=y +CONFIG_STM32_DFU=y +CONFIG_STM32_ETHMAC=y +CONFIG_STM32_EXTERNAL_RAM=y +CONFIG_STM32_FSMC=y +CONFIG_STM32_I2C1=y +CONFIG_STM32_JTAG_FULL_ENABLE=y +CONFIG_STM32_MII=y +CONFIG_STM32_PHYSR=16 +CONFIG_STM32_PHYSR_100MBPS=0x0000 +CONFIG_STM32_PHYSR_FULLDUPLEX=0x0004 +CONFIG_STM32_PHYSR_MODE=0x0004 +CONFIG_STM32_PHYSR_SPEED=0x0002 +CONFIG_STM32_PWR=y +CONFIG_STM32_RTC=y +CONFIG_STM32_USART3=y +CONFIG_SYSTEM_I2CTOOL=y +CONFIG_SYSTEM_PING=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART3_RXBUFSIZE=128 +CONFIG_USART3_SERIAL_CONSOLE=y +CONFIG_USART3_TXBUFSIZE=128 diff --git a/boards/arm/stm32f4/stm3240g-eval/configs/nxwm/defconfig b/boards/arm/stm32f4/stm3240g-eval/configs/nxwm/defconfig new file mode 100644 index 0000000000000..9104b7cd84a13 --- /dev/null +++ b/boards/arm/stm32f4/stm3240g-eval/configs/nxwm/defconfig @@ -0,0 +1,123 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_NXFONTS_DISABLE_16BPP is not set +# CONFIG_NXTK_DEFAULT_BORDERCOLORS is not set +# CONFIG_NX_DISABLE_16BPP is not set +# CONFIG_NX_PACKEDMSFIRST is not set +# CONFIG_NX_WRITEONLY is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm3240g-eval" +CONFIG_ARCH_BOARD_STM3240G_EVAL=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F407IG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_FAT_LCNAMES=y +CONFIG_FAT_LFN=y +CONFIG_FS_FAT=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_HOST_WINDOWS=y +CONFIG_I2C_POLLED=y +CONFIG_INIT_ENTRYPOINT="nxwm_main" +CONFIG_INPUT=y +CONFIG_INPUT_STMPE811=y +CONFIG_INTELHEX_BINARY=y +CONFIG_LCD=y +CONFIG_LCD_MAXCONTRAST=1 +CONFIG_LCD_NOGETRUN=y +CONFIG_LIBC_MAX_EXITFUNS=1 +CONFIG_LINE_MAX=64 +CONFIG_MM_REGIONS=2 +CONFIG_MQ_MAXMSGSIZE=64 +CONFIG_NET=y +CONFIG_NETDB_DNSCLIENT=y +CONFIG_NETDB_DNSSERVER_NOADDR=y +CONFIG_NETINIT_NOMAC=y +CONFIG_NETUTILS_TELNETD=y +CONFIG_NETUTILS_TFTPC=y +CONFIG_NETUTILS_WEBCLIENT=y +CONFIG_NET_ICMP_SOCKET=y +CONFIG_NET_MAX_LISTENPORTS=40 +CONFIG_NET_STATISTICS=y +CONFIG_NET_TCP=y +CONFIG_NET_TCP_PREALLOC_CONNS=40 +CONFIG_NET_UDP=y +CONFIG_NET_UDP_CHECKSUMS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_LIBRARY=y +CONFIG_NSH_READLINE=y +CONFIG_NX=y +CONFIG_NXFONT_SANS22X29B=y +CONFIG_NXFONT_SANS23X27=y +CONFIG_NXTERM=y +CONFIG_NXTERM_CACHESIZE=32 +CONFIG_NXTERM_CURSORCHAR=95 +CONFIG_NXTERM_MXCHARS=325 +CONFIG_NXTERM_NXKBDIN=y +CONFIG_NXTK_BORDERCOLOR1=0x5cb7 +CONFIG_NXTK_BORDERCOLOR2=0x21c9 +CONFIG_NXTK_BORDERCOLOR3=0xffdf +CONFIG_NXWIDGETS=y +CONFIG_NXWIDGETS_BPP=16 +CONFIG_NXWIDGETS_CUSTOM_EDGECOLORS=y +CONFIG_NXWIDGETS_CUSTOM_FILLCOLORS=y +CONFIG_NXWIDGETS_DEFAULT_BACKGROUNDCOLOR=0x9dfb +CONFIG_NXWIDGETS_DEFAULT_HIGHLIGHTCOLOR=0xc618 +CONFIG_NXWIDGETS_DEFAULT_SELECTEDBACKGROUNDCOLOR=0xd73e +CONFIG_NXWIDGETS_DEFAULT_SHADOWEDGECOLOR=0x21e9 +CONFIG_NXWIDGETS_DEFAULT_SHINEEDGECOLOR=0xffdf +CONFIG_NXWIDGETS_SIZEOFCHAR=1 +CONFIG_NXWM=y +CONFIG_NXWM_HEXCALCULATOR_CUSTOM_FONTID=y +CONFIG_NXWM_HEXCALCULATOR_FONTID=5 +CONFIG_NXWM_KEYBOARD=y +CONFIG_NXWM_TASKBAR_LEFT=y +CONFIG_NXWM_TASKBAR_VSPACING=4 +CONFIG_NX_BLOCKING=y +CONFIG_NX_KBD=y +CONFIG_NX_XYINPUT_TOUCHSCREEN=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=196608 +CONFIG_RAM_START=0x20000000 +CONFIG_RR_INTERVAL=200 +CONFIG_RTC_DATETIME=y +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=192 +CONFIG_SCHED_WAITPID=y +CONFIG_STM32_DFU=y +CONFIG_STM32_ETHMAC=y +CONFIG_STM32_FSMC=y +CONFIG_STM32_I2C1=y +CONFIG_STM32_JTAG_FULL_ENABLE=y +CONFIG_STM32_MII=y +CONFIG_STM32_PHYSR=16 +CONFIG_STM32_PHYSR_100MBPS=0x0000 +CONFIG_STM32_PHYSR_FULLDUPLEX=0x0004 +CONFIG_STM32_PHYSR_MODE=0x0004 +CONFIG_STM32_PHYSR_SPEED=0x0002 +CONFIG_STM32_PWR=y +CONFIG_STM32_RTC=y +CONFIG_STM32_USART3=y +CONFIG_STMPE811_ACTIVELOW=y +CONFIG_STMPE811_EDGE=y +CONFIG_STMPE811_MULTIPLE=y +CONFIG_STMPE811_THRESHX=39 +CONFIG_STMPE811_THRESHY=51 +CONFIG_SYMTAB_ORDEREDBYNAME=y +CONFIG_SYSTEM_PING=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART3_RXBUFSIZE=128 +CONFIG_USART3_SERIAL_CONSOLE=y +CONFIG_USART3_TXBUFSIZE=128 diff --git a/boards/arm/stm32f4/stm3240g-eval/configs/telnetd/defconfig b/boards/arm/stm32f4/stm3240g-eval/configs/telnetd/defconfig new file mode 100644 index 0000000000000..fbe59922f17a5 --- /dev/null +++ b/boards/arm/stm32f4/stm3240g-eval/configs/telnetd/defconfig @@ -0,0 +1,63 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm3240g-eval" +CONFIG_ARCH_BOARD_STM3240G_EVAL=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F407IG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_CONSOLE_SYSLOG=y +CONFIG_DISABLE_ENVIRON=y +CONFIG_DISABLE_MOUNTPOINT=y +CONFIG_DISABLE_MQUEUE=y +CONFIG_DISABLE_PTHREAD=y +CONFIG_ETH0_PHY_DP83848C=y +CONFIG_EXAMPLES_TELNETD=y +CONFIG_EXAMPLES_TELNETD_CLIENTPRIO=128 +CONFIG_EXAMPLES_TELNETD_DAEMONPRIO=128 +CONFIG_EXAMPLES_TELNETD_NOMAC=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INIT_ENTRYPOINT="telnetd_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_MM_REGIONS=2 +CONFIG_NET=y +CONFIG_NETUTILS_TELNETD=y +CONFIG_NET_MAX_LISTENPORTS=40 +CONFIG_NET_SOCKOPTS=y +CONFIG_NET_TCP=y +CONFIG_NET_TCP_PREALLOC_CONNS=40 +CONFIG_NSH_LIBRARY=y +CONFIG_NUNGET_CHARS=0 +CONFIG_RAM_SIZE=196608 +CONFIG_RAM_START=0x20000000 +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_STM32_DFU=y +CONFIG_STM32_ETHMAC=y +CONFIG_STM32_JTAG_FULL_ENABLE=y +CONFIG_STM32_MII=y +CONFIG_STM32_PHYSR=16 +CONFIG_STM32_PHYSR_100MBPS=0x0000 +CONFIG_STM32_PHYSR_FULLDUPLEX=0x0004 +CONFIG_STM32_PHYSR_MODE=0x0004 +CONFIG_STM32_PHYSR_SPEED=0x0002 +CONFIG_STM32_USART3=y +CONFIG_SYSTEM_READLINE=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART3_RXBUFSIZE=128 +CONFIG_USART3_SERIAL_CONSOLE=y +CONFIG_USART3_TXBUFSIZE=128 diff --git a/boards/arm/stm32f4/stm3240g-eval/configs/webserver/defconfig b/boards/arm/stm32f4/stm3240g-eval/configs/webserver/defconfig new file mode 100644 index 0000000000000..28c7c0ac95600 --- /dev/null +++ b/boards/arm/stm32f4/stm3240g-eval/configs/webserver/defconfig @@ -0,0 +1,76 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm3240g-eval" +CONFIG_ARCH_BOARD_STM3240G_EVAL=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F407IG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_EXAMPLES_NETTEST=y +CONFIG_EXAMPLES_WEBSERVER=y +CONFIG_FAT_LCNAMES=y +CONFIG_FAT_LFN=y +CONFIG_FS_FAT=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_I2C=y +CONFIG_I2C_POLLED=y +CONFIG_INIT_ENTRYPOINT="webserver_main" +CONFIG_LINE_MAX=64 +CONFIG_MM_REGIONS=2 +CONFIG_MTD=y +CONFIG_NET=y +CONFIG_NETINIT_NOMAC=y +CONFIG_NETUTILS_TELNETD=y +CONFIG_NETUTILS_WEBSERVER=y +CONFIG_NET_ICMP_SOCKET=y +CONFIG_NET_MAX_LISTENPORTS=40 +CONFIG_NET_SOCKOPTS=y +CONFIG_NET_STATISTICS=y +CONFIG_NET_TCP=y +CONFIG_NET_TCP_PREALLOC_CONNS=40 +CONFIG_NET_UDP=y +CONFIG_NET_UDP_CHECKSUMS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_LIBRARY=y +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=196608 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_RTC_DATETIME=y +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_WAITPID=y +CONFIG_STM32_CCMEXCLUDE=y +CONFIG_STM32_ETHMAC=y +CONFIG_STM32_I2C1=y +CONFIG_STM32_JTAG_FULL_ENABLE=y +CONFIG_STM32_MII=y +CONFIG_STM32_PHYSR=16 +CONFIG_STM32_PHYSR_100MBPS=0x0000 +CONFIG_STM32_PHYSR_FULLDUPLEX=0x0004 +CONFIG_STM32_PHYSR_MODE=0x0004 +CONFIG_STM32_PHYSR_SPEED=0x0002 +CONFIG_STM32_PWR=y +CONFIG_STM32_RTC=y +CONFIG_STM32_USART3=y +CONFIG_SYMTAB_ORDEREDBYNAME=y +CONFIG_SYSTEM_PING=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART3_RXBUFSIZE=128 +CONFIG_USART3_SERIAL_CONSOLE=y +CONFIG_USART3_TXBUFSIZE=128 diff --git a/boards/arm/stm32f4/stm3240g-eval/configs/xmlrpc/defconfig b/boards/arm/stm32f4/stm3240g-eval/configs/xmlrpc/defconfig new file mode 100644 index 0000000000000..530c00545a4e2 --- /dev/null +++ b/boards/arm/stm32f4/stm3240g-eval/configs/xmlrpc/defconfig @@ -0,0 +1,70 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_DISABLE_OS_API is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm3240g-eval" +CONFIG_ARCH_BOARD_STM3240G_EVAL=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F407IG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_ETH0_PHY_DP83848C=y +CONFIG_EXAMPLES_XMLRPC=y +CONFIG_EXAMPLES_XMLRPC_DHCPC=y +CONFIG_EXAMPLES_XMLRPC_NOMAC=y +CONFIG_FAT_LCNAMES=y +CONFIG_FAT_LFN=y +CONFIG_FS_FAT=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_I2C=y +CONFIG_I2C_POLLED=y +CONFIG_INIT_ENTRYPOINT="xmlrpc_main" +CONFIG_INIT_STACKSIZE=4096 +CONFIG_MM_REGIONS=2 +CONFIG_NET=y +CONFIG_NETDB_DNSCLIENT_ENTRIES=4 +CONFIG_NET_ARP_IPIN=y +CONFIG_NET_BROADCAST=y +CONFIG_NET_ETH_PKTSIZE=650 +CONFIG_NET_ICMP_SOCKET=y +CONFIG_NET_MAX_LISTENPORTS=40 +CONFIG_NET_STATISTICS=y +CONFIG_NET_TCP=y +CONFIG_NET_TCP_PREALLOC_CONNS=40 +CONFIG_NET_UDP=y +CONFIG_NET_UDP_CHECKSUMS=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=196608 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_STM32_ETHMAC=y +CONFIG_STM32_I2C1=y +CONFIG_STM32_JTAG_FULL_ENABLE=y +CONFIG_STM32_MII=y +CONFIG_STM32_PHYSR=16 +CONFIG_STM32_PHYSR_100MBPS=0x0000 +CONFIG_STM32_PHYSR_FULLDUPLEX=0x0004 +CONFIG_STM32_PHYSR_MODE=0x0004 +CONFIG_STM32_PHYSR_SPEED=0x0002 +CONFIG_STM32_PWR=y +CONFIG_STM32_USART3=y +CONFIG_SYSTEM_PING=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART3_RXBUFSIZE=128 +CONFIG_USART3_SERIAL_CONSOLE=y +CONFIG_USART3_TXBUFSIZE=128 diff --git a/boards/arm/stm32f4/stm3240g-eval/include/board.h b/boards/arm/stm32f4/stm3240g-eval/include/board.h new file mode 100644 index 0000000000000..702e2d93d9084 --- /dev/null +++ b/boards/arm/stm32f4/stm3240g-eval/include/board.h @@ -0,0 +1,603 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm3240g-eval/include/board.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARD_ARM_STM32_STM3240G_EVAL_INCLUDE_BOARD_H +#define __BOARD_ARM_STM32_STM3240G_EVAL_INCLUDE_BOARD_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#ifndef __ASSEMBLY__ +# include +#endif + +/* Logic in arch/arm/src and boards/ may need to include these file prior to + * including board.h: stm32_rcc.h, stm32_sdio.h, stm32.h. They cannot be + * included here because board.h is used in other contexts where the STM32 + * internal header files are not available. + */ + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Clocking *****************************************************************/ + +/* Four clock sources are available on STM3240G-EVAL evaluation board for + * STM32F407IGH6 and RTC embedded: + * + * X1, 25 MHz crystal for Ethernet PHY with socket. + * It can be removed when clock is provided by MCO pin of the MCU + * X2, 26 MHz crystal for USB OTG HS PHY + * X3, 32 kHz crystal for embedded RTC + * X4, 25 MHz crystal with socket for STM32F407IGH6 microcontroller + * (It can be removed from socket when internal RC clock is used.) + * + * This is the "standard" configuration as set up by + * arch/arm/src/stm32f40xx_rcc.c: + * System Clock source : PLL (HSE) + * SYSCLK(Hz) : 168000000 Determined by PLL + * configuration + * HCLK(Hz) : 168000000 (STM32_RCC_CFGR_HPRE) + * AHB Prescaler : 1 (STM32_RCC_CFGR_HPRE) + * APB1 Prescaler : 4 (STM32_RCC_CFGR_PPRE1) + * APB2 Prescaler : 2 (STM32_RCC_CFGR_PPRE2) + * HSE Frequency(Hz) : 25000000 (STM32_BOARD_XTAL) + * PLLM : 25 (STM32_PLLCFG_PLLM) + * PLLN : 336 (STM32_PLLCFG_PLLN) + * PLLP : 2 (STM32_PLLCFG_PLLP) + * PLLQ : 7 (STM32_PLLCFG_PLLQ) + * Main regulator output voltage : Scale1 mode Needed for high speed + * SYSCLK + * Flash Latency(WS) : 5 + * Prefetch Buffer : OFF + * Instruction cache : ON + * Data cache : ON + * Require 48MHz for USB OTG FS, : Enabled + * SDIO and RNG clock + */ + +/* HSI - 16 MHz RC factory-trimmed + * LSI - 32 KHz RC + * HSE - On-board crystal frequency is 25MHz + * LSE - 32.768 kHz + */ + +#define STM32_BOARD_XTAL 25000000ul + +#define STM32_HSI_FREQUENCY 16000000ul +#define STM32_LSI_FREQUENCY 32000 +#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL +#define STM32_LSE_FREQUENCY 32768 + +/* Main PLL Configuration. + * + * PLL source is HSE + * PLL_VCO = (STM32_HSE_FREQUENCY / PLLM) * PLLN + * = (25,000,000 / 25) * 336 + * = 336,000,000 + * SYSCLK = PLL_VCO / PLLP + * = 336,000,000 / 2 = 168,000,000 + * USB OTG FS, SDIO and RNG Clock + * = PLL_VCO / PLLQ + * = 48,000,000 + */ + +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(25) +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(336) +#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_2 +#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(7) + +#define STM32_SYSCLK_FREQUENCY 168000000ul + +/* AHB clock (HCLK) is SYSCLK (168MHz) */ + +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY + +/* APB1 clock (PCLK1) is HCLK/4 (42MHz) */ + +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd4 /* PCLK1 = HCLK / 4 */ +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/4) + +/* Timers driven from APB1 will be twice PCLK1 */ + +#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) + +/* APB2 clock (PCLK2) is HCLK/2 (84MHz) */ + +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLKd2 /* PCLK2 = HCLK / 2 */ +#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/2) + +/* Timers driven from APB2 will be twice PCLK2 */ + +#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM9_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM10_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM11_CLKIN (2*STM32_PCLK2_FREQUENCY) + +/* Timer Frequencies, if APBx is set to 1, frequency is same as APBx + * otherwise frequency is 2xAPBx. + * Note: TIM1,8-11 are on APB2, others on APB1 + */ + +#define BOARD_TIM2_FREQUENCY    STM32_APB1_TIM2_CLKIN +#define BOARD_TIM3_FREQUENCY    STM32_APB1_TIM3_CLKIN +#define BOARD_TIM4_FREQUENCY    STM32_APB1_TIM4_CLKIN +#define BOARD_TIM5_FREQUENCY    STM32_APB1_TIM5_CLKIN +#define BOARD_TIM6_FREQUENCY    STM32_APB1_TIM6_CLKIN +#define BOARD_TIM7_FREQUENCY    STM32_APB1_TIM7_CLKIN +#define BOARD_TIM12_FREQUENCY   STM32_APB1_TIM12_CLKIN +#define BOARD_TIM13_FREQUENCY   STM32_APB1_TIM13_CLKIN +#define BOARD_TIM14_FREQUENCY   STM32_APB1_TIM14_CLKIN + +#define BOARD_TIM1_FREQUENCY    STM32_APB2_TIM1_CLKIN +#define BOARD_TIM8_FREQUENCY    STM32_APB2_TIM8_CLKIN +#define BOARD_TIM9_FREQUENCY    STM32_APB2_TIM9_CLKIN +#define BOARD_TIM10_FREQUENCY   STM32_APB2_TIM10_CLKIN +#define BOARD_TIM11_FREQUENCY   STM32_APB2_TIM11_CLKIN + +/* SDIO dividers. Note that slower clocking is required when DMA is disabled + * in order to avoid RX overrun/TX underrun errors due to delayed responses + * to service FIFOs in interrupt driven mode. These values have not been + * tuned!!! + * + * SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(118+2)=400 KHz + */ + +#define SDIO_INIT_CLKDIV (118 << SDIO_CLKCR_CLKDIV_SHIFT) + +/* DMA ON: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(1+2)=16 MHz + * DMA OFF: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(2+2)=12 MHz + */ + +#ifdef CONFIG_SDIO_DMA +# define SDIO_MMCXFR_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT) +#else +# define SDIO_MMCXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT) +#endif + +/* DMA ON: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(1+2)=16 MHz + * DMA OFF: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(2+2)=12 MHz + */ + +#ifdef CONFIG_SDIO_DMA +# define SDIO_SDXFR_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT) +#else +# define SDIO_SDXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT) +#endif + +/* Ethernet *****************************************************************/ + +/* We need to provide clocking to the MII PHY via MCO1 (PA8) */ + +#if defined(CONFIG_NET) && defined(CONFIG_STM32_ETHMAC) + +# if !defined(CONFIG_STM32_MII) +# warning "CONFIG_STM32_MII required for Ethernet" +# elif !defined(CONFIG_STM32_MII_MCO1) +# warning "CONFIG_STM32_MII_MCO1 required for Ethernet MII" +# else + + /* Output HSE clock (25MHz) on MCO1 pin (PA8) to clock the PHY */ + +# define BOARD_CFGR_MC01_SOURCE RCC_CFGR_MCO1_HSE +# define BOARD_CFGR_MC01_DIVIDER RCC_CFGR_MCO1PRE_NONE + +# endif +#endif + +/* LED definitions **********************************************************/ + +/* If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs in + * any way. The following definitions are used to access individual LEDs. + */ + +/* LED index values for use with board_userled() */ + +#define BOARD_LED1 0 +#define BOARD_LED2 1 +#define BOARD_LED3 2 +#define BOARD_LED4 3 +#define BOARD_NLEDS 4 + +/* LED bits for use with board_userled_all() */ + +#define BOARD_LED1_BIT (1 << BOARD_LED1) +#define BOARD_LED2_BIT (1 << BOARD_LED2) +#define BOARD_LED3_BIT (1 << BOARD_LED3) +#define BOARD_LED4_BIT (1 << BOARD_LED4) + +/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the 4 LEDs on + * board the STM3240G-EVAL. + * The following definitions describe how NuttX controls the LEDs: + */ + +#define LED_STARTED 0 /* LED1 */ +#define LED_HEAPALLOCATE 1 /* LED2 */ +#define LED_IRQSENABLED 2 /* LED1 + LED2 */ +#define LED_STACKCREATED 3 /* LED3 */ +#define LED_INIRQ 4 /* LED1 + LED3 */ +#define LED_SIGNAL 5 /* LED2 + LED3 */ +#define LED_ASSERTION 6 /* LED1 + LED2 + LED3 */ +#define LED_PANIC 7 /* N/C + N/C + N/C + LED4 */ + +/* Button definitions *******************************************************/ + +/* The STM3240G-EVAL supports three buttons: */ + +#define BUTTON_WAKEUP 0 +#define BUTTON_TAMPER 1 +#define BUTTON_USER 2 + +#define NUM_BUTTONS 3 + +#define BUTTON_WAKEUP_BIT (1 << BUTTON_WAKEUP) +#define BUTTON_TAMPER_BIT (1 << BUTTON_TAMPER) +#define BUTTON_USER_BIT (1 << BUTTON_USER) + +/* SRAM definitions *********************************************************/ + +/* The 16 Mbit SRAM is connected to the STM32F407IGH6 FSMC bus which shares + * the same I/Os with the CAN1 bus. Jumper settings: + * + * JP1: Connect PE4 to SRAM as A20 + * JP2: onnect PE3 to SRAM as A19 + * + * JP3 and JP10 must not be fitted for SRAM and LCD application. + * JP3 and JP10 select CAN1 or CAN2 if fitted; neither if not fitted. + */ + +#if defined(CONFIG_STM32_FSMC) && defined(CONFIG_STM32_EXTERNAL_RAM) +# if defined(CONFIG_STM32_CAN1) || defined(CONFIG_STM32_CAN2) +# error "The STM3240G-EVAL cannot support both CAN and FSMC SRAM" +# endif +#endif + +/* This is the Bank1 SRAM2 address: */ + +#define BOARD_SRAM_BASE 0x64000000 +#define BOARD_SRAM_SIZE (2*1024*1024) + +/* Alternate function pin selections ****************************************/ + +/* UART3: + * + * - PC11 is MicroSDCard_D3 & RS232/IrDA_RX (JP22 open) + * - PC10 is MicroSDCard_D2 & RSS232/IrDA_TX + */ + +#define GPIO_USART3_RX (GPIO_USART3_RX_2|GPIO_SPEED_100MHz) +#define GPIO_USART3_TX (GPIO_USART3_TX_2|GPIO_SPEED_100MHz) + +/* Ethernet: + * + * - PA2 is ETH_MDIO + * - PC1 is ETH_MDC + * - PB5 is ETH_PPS_OUT + * - PH2 is ETH_MII_CRS + * - PH3 is ETH_MII_COL + * - PI10 is ETH_MII_RX_ER + * - PH6 is ETH_MII_RXD2 + * - PH7 is ETH_MII_RXD3 + * - PC3 is ETH_MII_TX_CLK + * - PC2 is ETH_MII_TXD2 + * - PB8 is ETH_MII_TXD3 + * - PA1 is ETH_MII_RX_CLK/ETH_RMII_REF_CLK + * - PA7 is ETH_MII_RX_DV/ETH_RMII_CRS_DV + * - PC4 is ETH_MII_RXD0/ETH_RMII_RXD0 + * - PC5 is ETH_MII_RXD1/ETH_RMII_RXD1 + * - PG11 is ETH_MII_TX_EN/ETH_RMII_TX_EN + * - PG13 is ETH_MII_TXD0/ETH_RMII_TXD0 + * - PG14 is ETH_MII_TXD1/ETH_RMII_TXD1 + */ + +#define GPIO_ETH_PPS_OUT (GPIO_ETH_PPS_OUT_1|GPIO_SPEED_100MHz) +#define GPIO_ETH_MII_CRS (GPIO_ETH_MII_CRS_2|GPIO_SPEED_100MHz) +#define GPIO_ETH_MII_COL (GPIO_ETH_MII_COL_2|GPIO_SPEED_100MHz) +#define GPIO_ETH_MII_RX_ER (GPIO_ETH_MII_RX_ER_2|GPIO_SPEED_100MHz) +#define GPIO_ETH_MII_RXD2 (GPIO_ETH_MII_RXD2_2|GPIO_SPEED_100MHz) +#define GPIO_ETH_MII_RXD3 (GPIO_ETH_MII_RXD3_2|GPIO_SPEED_100MHz) +#define GPIO_ETH_MII_TXD3 (GPIO_ETH_MII_TXD3_1|GPIO_SPEED_100MHz) +#define GPIO_ETH_MII_TX_EN (GPIO_ETH_MII_TX_EN_2|GPIO_SPEED_100MHz) +#define GPIO_ETH_MII_TXD0 (GPIO_ETH_MII_TXD0_2|GPIO_SPEED_100MHz) +#define GPIO_ETH_MII_TXD1 (GPIO_ETH_MII_TXD1_2|GPIO_SPEED_100MHz) +#define GPIO_ETH_RMII_TX_EN (GPIO_ETH_RMII_TX_EN_2|GPIO_SPEED_100MHz) +#define GPIO_ETH_RMII_TXD0 (GPIO_ETH_RMII_TXD0_2|GPIO_SPEED_100MHz) +#define GPIO_ETH_RMII_TXD1 (GPIO_ETH_RMII_TXD1_2|GPIO_SPEED_100MHz) + +/* PWM + * + * The STM3240G-Eval has no real on-board PWM devices, but the board can be + * configured to output a pulse train using the following: + * + * If FSMC is not used: + * TIM4 CH2OUT: PD13 FSMC_A18 / MC_TIM4_CH2OUT + * Daughterboard Extension Connector, CN3, pin 32 + * Motor Control Connector CN15, + * pin 33 -- not available unless you bridge SB14. + * + * TIM1 CH1OUT: PE9 FSMC_D6 + * Daughterboard Extension Connector, CN2, pin 24 + * + * TIM1_CH2OUT: PE11 FSMC_D8 + * Daughterboard Extension Connector, CN2, pin 26 + * + * TIM1_CH3OUT: PE13 FSMC_D10 + * Daughterboard Extension Connector, CN2, pin 28 + * + * TIM1_CH4OUT: PE14 FSMC_D11 + * Daughterboard Extension Connector, CN2, pin 29 + * + * If OTG FS is not used + * + * TIM1_CH3OUT: PA10 OTG_FS_ID + * Daughterboard Extension Connector, CN3, pin 14 + * + * TIM1_CH4OUT: PA11 OTG_FS_DM + * Daughterboard Extension Connector, CN3, pin 11 + * + * If DMCI is not used + * + * TIM8 CH1OUT: PI5 DCMI_VSYNC & MC + * Daughterboard Extension Connector, CN4, pin 4 + * + * TIM8_CH2OUT: PI6 DCMI_D6 & MC + * Daughterboard Extension Connector, CN4, pin 3 + * + * TIM8_CH3OUT: PI7 DCMI_D7 & MC + * Daughterboard Extension Connector, CN4, pin 2 + * + * If SDIO is not used + * + * TIM8_CH3OUT: PC8 MicroSDCard_D0 & MC + * Daughterboard Extension Connector, CN3, pin 18 + * + * TIM8_CH4OUT: PC9 MicroSDCard_D1 & I2S_CKIN (Need JP16 open) + * Daughterboard Extension Connector, CN3, pin 17 + * + * Others + * + * TIM8 CH1OUT: PC6 I2S_MCK & Smartcard_IO (JP21 open) + */ + +#if !defined(CONFIG_STM32_FSMC) +# define GPIO_TIM4_CH2OUT (GPIO_TIM4_CH2OUT_2|GPIO_SPEED_50MHz) +# define GPIO_TIM1_CH1OUT (GPIO_TIM1_CH1OUT_2|GPIO_SPEED_50MHz) +# define GPIO_TIM1_CH2OUT (GPIO_TIM1_CH2OUT_2|GPIO_SPEED_50MHz) +# define GPIO_TIM1_CH3OUT (GPIO_TIM1_CH3OUT_2|GPIO_SPEED_50MHz) +# define GPIO_TIM1_CH4OUT (GPIO_TIM1_CH4OUT_2|GPIO_SPEED_50MHz) +#elif !defined(CONFIG_STM32_OTGFS) +# define GPIO_TIM1_CH3OUT (GPIO_TIM1_CH3OUT_1|GPIO_SPEED_50MHz) +# define GPIO_TIM1_CH4OUT (GPIO_TIM1_CH4OUT_1|GPIO_SPEED_50MHz) +#endif + +#if !defined(CONFIG_STM32_DCMI) +# define GPIO_TIM8_CH1OUT (GPIO_TIM8_CH1OUT_2|GPIO_SPEED_50MHz) +# define GPIO_TIM8_CH2OUT (GPIO_TIM8_CH2OUT_2|GPIO_SPEED_50MHz) +# define GPIO_TIM8_CH3OUT (GPIO_TIM8_CH3OUT_2|GPIO_SPEED_50MHz) +#else +# define GPIO_TIM8_CH1OUT (GPIO_TIM8_CH1OUT_1|GPIO_SPEED_50MHz) +# if !defined(CONFIG_STM32_SDIO) +# define GPIO_TIM8_CH3OUT (GPIO_TIM8_CH3OUT_1|GPIO_SPEED_50MHz) +# endif +#endif + +#if !defined(CONFIG_STM32_SDIO) +# define GPIO_TIM8_CH4OUT (GPIO_TIM8_CH4OUT_1|GPIO_SPEED_50MHz) +#endif + +/* CAN + * + * Connector 10 (CN10) + * is DB-9 male connector that can be used with CAN1 or CAN2. + * + * JP10 connects CAN1_RX or CAN2_RX to the CAN transceiver + * JP3 connects CAN1_TX or CAN2_TX to the CAN transceiver + * + * CAN signals are then available on CN10 pins: + * + * CN10 Pin 7 = CANH + * CN10 Pin 2 = CANL + * + * Mapping to STM32 GPIO pins: + * + * PD0 = FSMC_D2 & CAN1_RX + * PD1 = FSMC_D3 & CAN1_TX + * PB13 = ULPI_D6 & CAN2_TX + * PB5 = ULPI_D7 & CAN2_RX + */ + +#define GPIO_CAN1_RX (GPIO_CAN1_RX_3|GPIO_SPEED_50MHz) +#define GPIO_CAN1_TX (GPIO_CAN1_TX_3|GPIO_SPEED_50MHz) + +#define GPIO_CAN2_RX (GPIO_CAN2_RX_2|GPIO_SPEED_50MHz) +#define GPIO_CAN2_TX (GPIO_CAN2_TX_1|GPIO_SPEED_50MHz) + +/* I2C. + * Only I2C1 is available on the STM3240G-EVAL. I2C1_SCL and I2C1_SDA are + * available on the following pins: + * + * - PB6 is I2C1_SCL + * - PB9 is I2C1_SDA + */ + +#define GPIO_I2C1_SCL (GPIO_I2C1_SCL_1|GPIO_SPEED_50MHz) +#define GPIO_I2C1_SDA (GPIO_I2C1_SDA_2|GPIO_SPEED_50MHz) + +/* DMA Channel/Stream Selections ********************************************/ + +/* Stream selections are arbitrary for now but might become important in the + * future if we set aside more DMA channels/streams. + * + * SDIO DMA + * DMAMAP_SDIO_1 = Channel 4, Stream 3 + * DMAMAP_SDIO_2 = Channel 4, Stream 6 + */ + +#define DMAMAP_SDIO DMAMAP_SDIO_1 + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: stm3240g_lcdclear + * + * Description: + * This is a non-standard LCD interface just for the STM3210E-EVAL board. + * Because of the various rotations, clearing the display in the normal + * way by writing a sequences of runs that covers the entire display can be + * very slow. Here the display is cleared by simply setting all GRAM + * memory to the specified color. + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_FSMC +void stm3240g_lcdclear(uint16_t color); +#endif + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ + +/* ETH MII/RMII inputs and MDC/MDIO + MCO1 */ + +#define GPIO_MCO1 (GPIO_MCO1_0|GPIO_SPEED_100MHz) +#define GPIO_ETH_MDC (GPIO_ETH_MDC_0|GPIO_SPEED_100MHz) +#define GPIO_ETH_MDIO (GPIO_ETH_MDIO_0|GPIO_SPEED_100MHz) +#define GPIO_ETH_MII_RX_CLK (GPIO_ETH_MII_RX_CLK_0|GPIO_SPEED_100MHz) +#define GPIO_ETH_MII_RX_DV (GPIO_ETH_MII_RX_DV_0|GPIO_SPEED_100MHz) +#define GPIO_ETH_MII_RXD0 (GPIO_ETH_MII_RXD0_0|GPIO_SPEED_100MHz) +#define GPIO_ETH_MII_RXD1 (GPIO_ETH_MII_RXD1_0|GPIO_SPEED_100MHz) +#define GPIO_ETH_MII_TX_CLK (GPIO_ETH_MII_TX_CLK_0|GPIO_SPEED_100MHz) +#define GPIO_ETH_MII_TXD2 (GPIO_ETH_MII_TXD2_0|GPIO_SPEED_100MHz) +#define GPIO_ETH_RMII_CRS_DV (GPIO_ETH_RMII_CRS_DV_0|GPIO_SPEED_100MHz) +#define GPIO_ETH_RMII_REF_CLK (GPIO_ETH_RMII_REF_CLK_0|GPIO_SPEED_100MHz) +#define GPIO_ETH_RMII_RXD0 (GPIO_ETH_RMII_RXD0_0|GPIO_SPEED_100MHz) +#define GPIO_ETH_RMII_RXD1 (GPIO_ETH_RMII_RXD1_0|GPIO_SPEED_100MHz) + +/* SDIO */ + +#define GPIO_SDIO_CK (GPIO_SDIO_CK_0|GPIO_SPEED_50MHz) +#define GPIO_SDIO_CMD (GPIO_SDIO_CMD_0|GPIO_SPEED_50MHz) +#define GPIO_SDIO_D0 (GPIO_SDIO_D0_0|GPIO_SPEED_50MHz) +#define GPIO_SDIO_D1 (GPIO_SDIO_D1_0|GPIO_SPEED_50MHz) +#define GPIO_SDIO_D2 (GPIO_SDIO_D2_0|GPIO_SPEED_50MHz) +#define GPIO_SDIO_D3 (GPIO_SDIO_D3_0|GPIO_SPEED_50MHz) + +/* USB OTG FS */ + +#define GPIO_OTGFS_DM (GPIO_OTGFS_DM_0|GPIO_SPEED_100MHz) +#define GPIO_OTGFS_DP (GPIO_OTGFS_DP_0|GPIO_SPEED_100MHz) +#define GPIO_OTGFS_ID (GPIO_OTGFS_ID_0|GPIO_SPEED_100MHz) +#define GPIO_OTGFS_SOF (GPIO_OTGFS_SOF_0|GPIO_SPEED_100MHz) + +/* DAC */ + +#define GPIO_DAC1_OUT1 GPIO_DAC1_OUT1_0 +#define GPIO_DAC1_OUT2 GPIO_DAC1_OUT2_0 + +/* FSMC SRAM/LCD */ + +#define GPIO_FSMC_A0 (GPIO_FSMC_A0_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A1 (GPIO_FSMC_A1_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A2 (GPIO_FSMC_A2_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A3 (GPIO_FSMC_A3_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A4 (GPIO_FSMC_A4_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A5 (GPIO_FSMC_A5_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A6 (GPIO_FSMC_A6_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A7 (GPIO_FSMC_A7_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A8 (GPIO_FSMC_A8_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A9 (GPIO_FSMC_A9_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A10 (GPIO_FSMC_A10_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A11 (GPIO_FSMC_A11_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A12 (GPIO_FSMC_A12_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A13 (GPIO_FSMC_A13_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A14 (GPIO_FSMC_A14_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A15 (GPIO_FSMC_A15_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A16 (GPIO_FSMC_A16_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A17 (GPIO_FSMC_A17_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A18 (GPIO_FSMC_A18_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A19 (GPIO_FSMC_A19_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A20 (GPIO_FSMC_A20_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A21 (GPIO_FSMC_A21_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A22 (GPIO_FSMC_A22_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A23 (GPIO_FSMC_A23_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A24 (GPIO_FSMC_A24_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A25 (GPIO_FSMC_A25_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_D0 (GPIO_FSMC_D0_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_D1 (GPIO_FSMC_D1_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_D2 (GPIO_FSMC_D2_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_D3 (GPIO_FSMC_D3_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_D4 (GPIO_FSMC_D4_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_D5 (GPIO_FSMC_D5_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_D6 (GPIO_FSMC_D6_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_D7 (GPIO_FSMC_D7_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_D8 (GPIO_FSMC_D8_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_D9 (GPIO_FSMC_D9_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_D10 (GPIO_FSMC_D10_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_D11 (GPIO_FSMC_D11_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_D12 (GPIO_FSMC_D12_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_D13 (GPIO_FSMC_D13_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_D14 (GPIO_FSMC_D14_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_D15 (GPIO_FSMC_D15_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_NOE (GPIO_FSMC_NOE_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_NWE (GPIO_FSMC_NWE_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_NE1 (GPIO_FSMC_NE1_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_NE2 (GPIO_FSMC_NE2_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_NE3 (GPIO_FSMC_NE3_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_NE4 (GPIO_FSMC_NE4_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_NBL0 (GPIO_FSMC_NBL0_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_NBL1 (GPIO_FSMC_NBL1_0|GPIO_SPEED_100MHz) + +#endif /* __BOARD_ARM_STM32_STM3240G_EVAL_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32f4/stm3240g-eval/kernel/Makefile b/boards/arm/stm32f4/stm3240g-eval/kernel/Makefile new file mode 100644 index 0000000000000..f89e2210f73fe --- /dev/null +++ b/boards/arm/stm32f4/stm3240g-eval/kernel/Makefile @@ -0,0 +1,94 @@ +############################################################################ +# boards/arm/stm32f4/stm3240g-eval/kernel/Makefile +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +# The entry point name (if none is provided in the .config file) + +CONFIG_INIT_ENTRYPOINT ?= user_start +ENTRYPT = $(patsubst "%",%,$(CONFIG_INIT_ENTRYPOINT)) + +# Get the paths to the libraries and the links script path in format that +# is appropriate for the host OS + +USER_LIBPATHS = $(addprefix -L,$(call CONVERT_PATH,$(addprefix $(TOPDIR)$(DELIM),$(dir $(USERLIBS))))) +USER_LDSCRIPT = -T $(call CONVERT_PATH,$(BOARD_DIR)$(DELIM)scripts$(DELIM)memory.ld) +USER_LDSCRIPT += -T $(call CONVERT_PATH,$(BOARD_DIR)$(DELIM)scripts$(DELIM)user-space.ld) +USER_HEXFILE += $(call CONVERT_PATH,$(TOPDIR)$(DELIM)nuttx_user.hex) +USER_SRECFILE += $(call CONVERT_PATH,$(TOPDIR)$(DELIM)nuttx_user.srec) +USER_BINFILE += $(call CONVERT_PATH,$(TOPDIR)$(DELIM)nuttx_user.bin) + +USER_LDFLAGS = --undefined=$(ENTRYPT) --entry=$(ENTRYPT) $(USER_LDSCRIPT) +USER_LDLIBS = $(patsubst lib%,-l%,$(basename $(notdir $(USERLIBS)))) +USER_LIBGCC = "${shell "$(CC)" $(ARCHCPUFLAGS) -print-libgcc-file-name}" + +# Source files + +CSRCS = stm32_userspace.c +COBJS = $(CSRCS:.c=$(OBJEXT)) +OBJS = $(COBJS) + +# Targets: + +all: $(TOPDIR)$(DELIM)nuttx_user.elf $(TOPDIR)$(DELIM)User.map +.PHONY: nuttx_user.elf depend clean distclean + +$(COBJS): %$(OBJEXT): %.c + $(call COMPILE, $<, $@) + +# Create the nuttx_user.elf file containing all of the user-mode code + +nuttx_user.elf: $(OBJS) + $(Q) $(LD) -o $@ $(USER_LDFLAGS) $(USER_LIBPATHS) $(OBJS) --start-group $(USER_LDLIBS) --end-group $(USER_LIBGCC) + +$(TOPDIR)$(DELIM)nuttx_user.elf: nuttx_user.elf + @echo "LD: nuttx_user.elf" + $(Q) cp -a nuttx_user.elf $(TOPDIR)$(DELIM)nuttx_user.elf +ifeq ($(CONFIG_INTELHEX_BINARY),y) + @echo "CP: nuttx_user.hex" + $(Q) $(OBJCOPY) $(OBJCOPYARGS) -O ihex nuttx_user.elf $(USER_HEXFILE) +endif +ifeq ($(CONFIG_MOTOROLA_SREC),y) + @echo "CP: nuttx_user.srec" + $(Q) $(OBJCOPY) $(OBJCOPYARGS) -O srec nuttx_user.elf $(USER_SRECFILE) +endif +ifeq ($(CONFIG_RAW_BINARY),y) + @echo "CP: nuttx_user.bin" + $(Q) $(OBJCOPY) $(OBJCOPYARGS) -O binary nuttx_user.elf $(USER_BINFILE) +endif + +$(TOPDIR)$(DELIM)User.map: nuttx_user.elf + @echo "MK: User.map" + $(Q) $(NM) nuttx_user.elf >$(TOPDIR)$(DELIM)User.map + $(Q) $(CROSSDEV)size nuttx_user.elf + +.depend: + +depend: .depend + +clean: + $(call DELFILE, nuttx_user.elf) + $(call DELFILE, "$(TOPDIR)$(DELIM)nuttx_user.*") + $(call DELFILE, "$(TOPDIR)$(DELIM)User.map") + $(call CLEAN) + +distclean: clean diff --git a/boards/arm/stm32f4/stm3240g-eval/kernel/stm32_userspace.c b/boards/arm/stm32f4/stm3240g-eval/kernel/stm32_userspace.c new file mode 100644 index 0000000000000..ca655d1ada4bc --- /dev/null +++ b/boards/arm/stm32f4/stm3240g-eval/kernel/stm32_userspace.c @@ -0,0 +1,110 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm3240g-eval/kernel/stm32_userspace.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include +#include +#include + +#if defined(CONFIG_BUILD_PROTECTED) && !defined(__KERNEL__) + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +#ifndef CONFIG_NUTTX_USERSPACE +# error "CONFIG_NUTTX_USERSPACE not defined" +#endif + +#if CONFIG_NUTTX_USERSPACE != 0x08040000 +# error "CONFIG_NUTTX_USERSPACE must be 0x08040000 to match memory.ld" +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static struct userspace_data_s g_userspace_data = +{ + .us_heap = &g_mmheap, +}; + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/* These 'addresses' of these values are setup by the linker script. */ + +extern uint8_t _stext[]; /* Start of .text */ +extern uint8_t _etext[]; /* End_1 of .text + .rodata */ +extern const uint8_t _eronly[]; /* End+1 of read only section (.text + .rodata) */ +extern uint8_t _sdata[]; /* Start of .data */ +extern uint8_t _edata[]; /* End+1 of .data */ +extern uint8_t _sbss[]; /* Start of .bss */ +extern uint8_t _ebss[]; /* End+1 of .bss */ + +const struct userspace_s userspace locate_data(".userspace") = +{ + /* General memory map */ + + .us_entrypoint = CONFIG_INIT_ENTRYPOINT, + .us_textstart = (uintptr_t)_stext, + .us_textend = (uintptr_t)_etext, + .us_datasource = (uintptr_t)_eronly, + .us_datastart = (uintptr_t)_sdata, + .us_dataend = (uintptr_t)_edata, + .us_bssstart = (uintptr_t)_sbss, + .us_bssend = (uintptr_t)_ebss, + + /* User data memory structure */ + + .us_data = &g_userspace_data, + + /* Task/thread startup routines */ + + .task_startup = nxtask_startup, + + /* Signal handler trampoline */ + + .signal_handler = up_signal_handler, + + /* User-space work queue support (declared in include/nuttx/wqueue.h) */ + +#ifdef CONFIG_LIBC_USRWORK + .work_usrstart = work_usrstart, +#endif +}; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +#endif /* CONFIG_BUILD_PROTECTED && !__KERNEL__ */ diff --git a/boards/arm/stm32f4/stm3240g-eval/scripts/Make.defs b/boards/arm/stm32f4/stm3240g-eval/scripts/Make.defs new file mode 100644 index 0000000000000..9f8df9bce9c68 --- /dev/null +++ b/boards/arm/stm32f4/stm3240g-eval/scripts/Make.defs @@ -0,0 +1,41 @@ +############################################################################ +# boards/arm/stm32f4/stm3240g-eval/scripts/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/.config +include $(TOPDIR)/tools/Config.mk +include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs + +LDSCRIPT = ld.script +ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) + +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32f4/stm3240g-eval/scripts/kernel-space.ld b/boards/arm/stm32f4/stm3240g-eval/scripts/kernel-space.ld new file mode 100644 index 0000000000000..7712a4771a100 --- /dev/null +++ b/boards/arm/stm32f4/stm3240g-eval/scripts/kernel-space.ld @@ -0,0 +1,100 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm3240g-eval/scripts/kernel-space.ld + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* NOTE: This depends on the memory.ld script having been included prior to + * this script. + */ + +OUTPUT_ARCH(arm) +EXTERN(_vectors) +ENTRY(_stext) +SECTIONS +{ + .text : { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > kflash + + .init_section : { + _sinit = ABSOLUTE(.); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) + _einit = ABSOLUTE(.); + } > kflash + + .ARM.extab : { + *(.ARM.extab*) + } > kflash + + __exidx_start = ABSOLUTE(.); + .ARM.exidx : { + *(.ARM.exidx*) + } > kflash + + __exidx_end = ABSOLUTE(.); + + _eronly = ABSOLUTE(.); + + .data : { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > ksram AT > kflash + + .bss : { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(8); + _ebss = ABSOLUTE(.); + } > ksram + + /* Stabs debugging sections */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/stm32f4/stm3240g-eval/scripts/ld.script b/boards/arm/stm32f4/stm3240g-eval/scripts/ld.script new file mode 100644 index 0000000000000..a4987bf37e078 --- /dev/null +++ b/boards/arm/stm32f4/stm3240g-eval/scripts/ld.script @@ -0,0 +1,126 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm3240g-eval/scripts/ld.script + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* The STM32F407VG has 1024Kb of FLASH beginning at address 0x0800:0000 and + * 192Kb of SRAM. SRAM is split up into three blocks: + * + * 1) 112Kb of SRAM beginning at address 0x2000:0000 + * 2) 16Kb of SRAM beginning at address 0x2001:c000 + * 3) 64Kb of CCM SRAM beginning at address 0x1000:0000 + * + * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 + * where the code expects to begin execution by jumping to the entry point in + * the 0x0800:0000 address + * range. + */ + +MEMORY +{ + flash (rx) : ORIGIN = 0x08000000, LENGTH = 1024K + sram (rwx) : ORIGIN = 0x20000000, LENGTH = 112K +} + +OUTPUT_ARCH(arm) +EXTERN(_vectors) +ENTRY(_stext) +SECTIONS +{ + .text : { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > flash + + .init_section : ALIGN(4) { + _sinit = ABSOLUTE(.); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) + _einit = ABSOLUTE(.); + } > flash + + .ARM.extab : ALIGN(4) { + *(.ARM.extab*) + } > flash + + .ARM.exidx : ALIGN(4) { + __exidx_start = ABSOLUTE(.); + *(.ARM.exidx*) + __exidx_end = ABSOLUTE(.); + } > flash + + .tdata : { + _stdata = ABSOLUTE(.); + *(.tdata .tdata.* .gnu.linkonce.td.*); + _etdata = ABSOLUTE(.); + } > flash + + .tbss : { + _stbss = ABSOLUTE(.); + *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); + _etbss = ABSOLUTE(.); + } > flash + + _eronly = ABSOLUTE(.); + + .data : ALIGN(4) { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > sram AT > flash + + .bss : ALIGN(4) { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + _ebss = ABSOLUTE(.); + } > sram + + /* Stabs debugging sections. */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/stm32f4/stm3240g-eval/scripts/memory.ld b/boards/arm/stm32f4/stm3240g-eval/scripts/memory.ld new file mode 100644 index 0000000000000..4f997fbe4f9ac --- /dev/null +++ b/boards/arm/stm32f4/stm3240g-eval/scripts/memory.ld @@ -0,0 +1,87 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm3240g-eval/scripts/memory.ld + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* The STM32F407VG has 1024Kb of FLASH beginning at address 0x0800:0000 and + * 192Kb of SRAM. SRAM is split up into three blocks: + * + * 1) 112KB of SRAM beginning at address 0x2000:0000 + * 2) 16KB of SRAM beginning at address 0x2001:c000 + * 3) 64KB of CCM SRAM beginning at address 0x1000:0000 + * + * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 + * where the code expects to begin execution by jumping to the entry point in + * the 0x0800:0000 address range. + * + * For MPU support, the kernel-mode NuttX section is assumed to be 256Kb of + * FLASH and 4Kb of SRAM. That is an excessive amount for the kernel which + * should fit into 64KB and, of course, can be optimized as needed (See + * also boards/arm/stm32f4/stm3240g-eval/scripts/kernel-space.ld). Allowing the + * additional does permit addition debug instrumentation to be added to the + * kernel space without overflowing the partition. + * + * Alignment of the user space FLASH partition is also a critical factor: + * The user space FLASH partition will be spanned with a single region of + * size 2**n bytes. The alignment of the user-space region must be the same. + * As a consequence, as the user-space increases in size, the alignment + * requirement also increases. + * + * This alignment requirement means that the largest user space FLASH region + * you can have will be 512KB at it would have to be positioned at + * 0x08800000. If you change this address, don't forget to change the + * CONFIG_NUTTX_USERSPACE configuration setting to match and to modify + * the check in kernel/userspace.c. + * + * For the same reasons, the maximum size of the SRAM mapping is limited to + * 4KB. Both of these alignment limitations could be reduced by using + * multiple regions to map the FLASH/SDRAM range or perhaps with some + * clever use of subregions. + * + * A detailed memory map for the 112KB SRAM region is as follows: + * + * 0x20000 0000: Kernel .data region. Typical size: 0.1KB + * ------- ---- Kernel .bss region. Typical size: 1.8KB + * 0x20000 0800: Kernel IDLE thread stack (approximate). Size is + * determined by CONFIG_IDLETHREAD_STACKSIZE and + * adjustments for alignment. Typical is 1KB. + * ------- ---- Padded to 4KB + * 0x20000 1000: User .data region. Size is variable. + * ------- ---- User .bss region Size is variable. + * 0x20000 2000: Beginning of kernel heap. Size determined by + * CONFIG_MM_KERNEL_HEAPSIZE. + * ------- ---- Beginning of user heap. Can vary with other settings. + * 0x20001 c000: End+1 of CPU RAM + */ + +MEMORY +{ + /* 1024Kb FLASH */ + + kflash (rx) : ORIGIN = 0x08000000, LENGTH = 256K + uflash (rx) : ORIGIN = 0x08040000, LENGTH = 256K + xflash (rx) : ORIGIN = 0x08080000, LENGTH = 512K + + /* 112Kb of contiguous SRAM */ + + ksram (rwx) : ORIGIN = 0x20000000, LENGTH = 6K + usram (rwx) : ORIGIN = 0x20001800, LENGTH = 4K + xsram (rwx) : ORIGIN = 0x20002800, LENGTH = 102K +} diff --git a/boards/arm/stm32f4/stm3240g-eval/scripts/user-space.ld b/boards/arm/stm32f4/stm3240g-eval/scripts/user-space.ld new file mode 100644 index 0000000000000..fd7922b7737e5 --- /dev/null +++ b/boards/arm/stm32f4/stm3240g-eval/scripts/user-space.ld @@ -0,0 +1,101 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm3240g-eval/scripts/user-space.ld + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* NOTE: This depends on the memory.ld script having been included prior to + * this script. + */ + +OUTPUT_ARCH(arm) +SECTIONS +{ + .userspace : { + *(.userspace) + } > uflash + + .text : { + _stext = ABSOLUTE(.); + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > uflash + + .init_section : { + _sinit = ABSOLUTE(.); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) + _einit = ABSOLUTE(.); + } > uflash + + .ARM.extab : { + *(.ARM.extab*) + } > uflash + + __exidx_start = ABSOLUTE(.); + .ARM.exidx : { + *(.ARM.exidx*) + } > uflash + + __exidx_end = ABSOLUTE(.); + + _eronly = ABSOLUTE(.); + + .data : { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > usram AT > uflash + + .bss : { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(8); + _ebss = ABSOLUTE(.); + } > usram + + /* Stabs debugging sections */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/stm32f4/stm3240g-eval/src/CMakeLists.txt b/boards/arm/stm32f4/stm3240g-eval/src/CMakeLists.txt new file mode 100644 index 0000000000000..1969d7755e529 --- /dev/null +++ b/boards/arm/stm32f4/stm3240g-eval/src/CMakeLists.txt @@ -0,0 +1,62 @@ +# ############################################################################## +# boards/arm/stm32f4/stm3240g-eval/src/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(SRCS stm32_boot.c stm32_bringup.c stm32_spi.c) + +if(CONFIG_ARCH_LEDS) + list(APPEND SRCS stm32_autoleds.c) +else() + list(APPEND SRCS stm32_userleds.c) +endif() + +if(CONFIG_ARCH_BUTTONS) + list(APPEND SRCS stm32_buttons.c) +endif() + +if(CONFIG_STM32_OTGFS) + list(APPEND SRCS stm32_usb.c) +endif() + +if(CONFIG_STM32_FSMC) + list(APPEND SRCS stm32_lcd.c stm32_selectlcd.c stm32_deselectlcd.c) + list(APPEND SRCS stm32_selectsram.c stm32_deselectsram.c stm32_extmem.c) +endif() + +if(CONFIG_ADC) + list(APPEND SRCS stm32_adc.c) +endif() + +if(CONFIG_PWM) + list(APPEND SRCS stm32_pwm.c) +endif() + +if(CONFIG_STM32_CAN_CHARDRIVER) + list(APPEND SRCS stm32_can.c) +endif() + +if(CONFIG_INPUT_STMPE811) + list(APPEND SRCS stm32_stmpe811.c) +endif() + +target_sources(board PRIVATE ${SRCS}) + +set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/ld.script") diff --git a/boards/arm/stm32f4/stm3240g-eval/src/Make.defs b/boards/arm/stm32f4/stm3240g-eval/src/Make.defs new file mode 100644 index 0000000000000..529bccfba93f0 --- /dev/null +++ b/boards/arm/stm32f4/stm3240g-eval/src/Make.defs @@ -0,0 +1,64 @@ +############################################################################ +# boards/arm/stm32f4/stm3240g-eval/src/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +CSRCS = stm32_boot.c stm32_bringup.c stm32_spi.c + +ifeq ($(CONFIG_ARCH_LEDS),y) +CSRCS += stm32_autoleds.c +else +CSRCS += stm32_userleds.c +endif + +ifeq ($(CONFIG_ARCH_BUTTONS),y) +CSRCS += stm32_buttons.c +endif + +ifeq ($(CONFIG_STM32_OTGFS),y) +CSRCS += stm32_usb.c +endif + +ifeq ($(CONFIG_STM32_FSMC),y) +CSRCS += stm32_lcd.c stm32_selectlcd.c stm32_deselectlcd.c +CSRCS += stm32_selectsram.c stm32_deselectsram.c stm32_extmem.c +endif + +ifeq ($(CONFIG_ADC),y) +CSRCS += stm32_adc.c +endif + +ifeq ($(CONFIG_PWM),y) +CSRCS += stm32_pwm.c +endif + +ifeq ($(CONFIG_STM32_CAN_CHARDRIVER),y) +CSRCS += stm32_can.c +endif + +ifeq ($(CONFIG_INPUT_STMPE811),y) +CSRCS += stm32_stmpe811.c +endif + +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/stm3240g-eval/src/stm3240g-eval.h b/boards/arm/stm32f4/stm3240g-eval/src/stm3240g-eval.h similarity index 99% rename from boards/arm/stm32/stm3240g-eval/src/stm3240g-eval.h rename to boards/arm/stm32f4/stm3240g-eval/src/stm3240g-eval.h index b607dc33408ba..da73e0674a9bd 100644 --- a/boards/arm/stm32/stm3240g-eval/src/stm3240g-eval.h +++ b/boards/arm/stm32f4/stm3240g-eval/src/stm3240g-eval.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm3240g-eval/src/stm3240g-eval.h + * boards/arm/stm32f4/stm3240g-eval/src/stm3240g-eval.h * * SPDX-License-Identifier: Apache-2.0 * @@ -30,7 +30,7 @@ #include #include #include -#include +#include /**************************************************************************** * Pre-processor Definitions diff --git a/boards/arm/stm32f4/stm3240g-eval/src/stm32_adc.c b/boards/arm/stm32f4/stm3240g-eval/src/stm32_adc.c new file mode 100644 index 0000000000000..ec49c4f1225d0 --- /dev/null +++ b/boards/arm/stm32f4/stm3240g-eval/src/stm32_adc.c @@ -0,0 +1,157 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm3240g-eval/src/stm32_adc.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32_pwm.h" +#include "stm3240g-eval.h" + +#ifdef CONFIG_ADC + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* Up to 3 ADC interfaces are supported */ + +#if STM32_NADC < 3 +# undef CONFIG_STM32_ADC3 +#endif + +#if STM32_NADC < 2 +# undef CONFIG_STM32_ADC2 +#endif + +#if STM32_NADC < 1 +# undef CONFIG_STM32_ADC1 +#endif + +#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) || defined(CONFIG_STM32_ADC3) +#ifndef CONFIG_STM32_ADC3 +# warning "Channel information only available for ADC3" +#endif + +/* The number of ADC channels in the conversion list */ + +#define ADC3_NCHANNELS 1 + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* The STM3240G-EVAL has a 10 Kohm potentiometer RV1 connected to PF9 of + * STM32F407IGH6 on the board: TIM14_CH1/FSMC_CD/ADC3_IN7 + */ + +/* Identifying number of each ADC channel: Variable Resistor. */ + +#ifdef CONFIG_STM32_ADC3 +static const uint8_t g_chanlist[ADC3_NCHANNELS] = +{ + 7 +}; + +/* Configurations of pins used byte each ADC channels */ + +static const uint32_t g_pinlist[ADC3_NCHANNELS] = +{ + GPIO_ADC3_IN7 +}; +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_adc_setup + * + * Description: + * Initialize ADC and register the ADC driver. + * + ****************************************************************************/ + +int stm32_adc_setup(void) +{ +#ifdef CONFIG_STM32_ADC3 + static bool initialized = false; + struct adc_dev_s *adc; + int ret; + int i; + + /* Check if we have already initialized */ + + if (!initialized) + { + /* Configure the pins as analog inputs for the selected channels */ + + for (i = 0; i < ADC3_NCHANNELS; i++) + { + stm32_configgpio(g_pinlist[i]); + } + + /* Call stm32_adcinitialize() to get an instance of the ADC interface */ + + adc = stm32_adcinitialize(3, g_chanlist, ADC3_NCHANNELS); + if (adc == NULL) + { + aerr("ERROR: Failed to get ADC interface\n"); + return -ENODEV; + } + + /* Register the ADC driver at "/dev/adc0" */ + + ret = adc_register("/dev/adc0", adc); + if (ret < 0) + { + aerr("ERROR: adc_register failed: %d\n", ret); + return ret; + } + + /* Now we are initialized */ + + initialized = true; + } + + return OK; +#else + return -ENOSYS; +#endif +} + +#endif /* CONFIG_STM32_ADC1 || CONFIG_STM32_ADC2 || CONFIG_STM32_ADC3 */ +#endif /* CONFIG_ADC */ diff --git a/boards/arm/stm32f4/stm3240g-eval/src/stm32_autoleds.c b/boards/arm/stm32f4/stm3240g-eval/src/stm32_autoleds.c new file mode 100644 index 0000000000000..d09719923af0a --- /dev/null +++ b/boards/arm/stm32f4/stm3240g-eval/src/stm32_autoleds.c @@ -0,0 +1,232 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm3240g-eval/src/stm32_autoleds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32.h" +#include "stm3240g-eval.h" + +#ifdef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* The following definitions map the encoded LED setting to GPIO settings */ + +#define STM3210E_LED1 (1 << 0) +#define STM3210E_LED2 (1 << 1) +#define STM3210E_LED3 (1 << 2) +#define STM3210E_LED4 (1 << 3) + +#define ON_SETBITS_SHIFT (0) +#define ON_CLRBITS_SHIFT (4) +#define OFF_SETBITS_SHIFT (8) +#define OFF_CLRBITS_SHIFT (12) + +#define ON_BITS(v) ((v) & 0xff) +#define OFF_BITS(v) (((v) >> 8) & 0x0ff) +#define SETBITS(b) ((b) & 0x0f) +#define CLRBITS(b) (((b) >> 4) & 0x0f) + +#define ON_SETBITS(v) (SETBITS(ON_BITS(v)) +#define ON_CLRBITS(v) (CLRBITS(ON_BITS(v)) +#define OFF_SETBITS(v) (SETBITS(OFF_BITS(v)) +#define OFF_CLRBITS(v) (CLRBITS(OFF_BITS(v)) + +#define LED_STARTED_ON_SETBITS ((STM3210E_LED1) << ON_SETBITS_SHIFT) +#define LED_STARTED_ON_CLRBITS ((STM3210E_LED2|STM3210E_LED3|STM3210E_LED4) << ON_CLRBITS_SHIFT) +#define LED_STARTED_OFF_SETBITS (0 << OFF_SETBITS_SHIFT) +#define LED_STARTED_OFF_CLRBITS ((STM3210E_LED1|STM3210E_LED2|STM3210E_LED3|STM3210E_LED4) << OFF_CLRBITS_SHIFT) + +#define LED_HEAPALLOCATE_ON_SETBITS ((STM3210E_LED2) << ON_SETBITS_SHIFT) +#define LED_HEAPALLOCATE_ON_CLRBITS ((STM3210E_LED1|STM3210E_LED3|STM3210E_LED4) << ON_CLRBITS_SHIFT) +#define LED_HEAPALLOCATE_OFF_SETBITS ((STM3210E_LED1) << OFF_SETBITS_SHIFT) +#define LED_HEAPALLOCATE_OFF_CLRBITS ((STM3210E_LED2|STM3210E_LED3|STM3210E_LED4) << OFF_CLRBITS_SHIFT) + +#define LED_IRQSENABLED_ON_SETBITS ((STM3210E_LED1|STM3210E_LED2) << ON_SETBITS_SHIFT) +#define LED_IRQSENABLED_ON_CLRBITS ((STM3210E_LED3|STM3210E_LED4) << ON_CLRBITS_SHIFT) +#define LED_IRQSENABLED_OFF_SETBITS ((STM3210E_LED2) << OFF_SETBITS_SHIFT) +#define LED_IRQSENABLED_OFF_CLRBITS ((STM3210E_LED1|STM3210E_LED3|STM3210E_LED4) << OFF_CLRBITS_SHIFT) + +#define LED_STACKCREATED_ON_SETBITS ((STM3210E_LED3) << ON_SETBITS_SHIFT) +#define LED_STACKCREATED_ON_CLRBITS ((STM3210E_LED1|STM3210E_LED2|STM3210E_LED4) << ON_CLRBITS_SHIFT) +#define LED_STACKCREATED_OFF_SETBITS ((STM3210E_LED1|STM3210E_LED2) << OFF_SETBITS_SHIFT) +#define LED_STACKCREATED_OFF_CLRBITS ((STM3210E_LED3|STM3210E_LED4) << OFF_CLRBITS_SHIFT) + +#define LED_INIRQ_ON_SETBITS ((STM3210E_LED1) << ON_SETBITS_SHIFT) +#define LED_INIRQ_ON_CLRBITS ((0) << ON_CLRBITS_SHIFT) +#define LED_INIRQ_OFF_SETBITS ((0) << OFF_SETBITS_SHIFT) +#define LED_INIRQ_OFF_CLRBITS ((STM3210E_LED1) << OFF_CLRBITS_SHIFT) + +#define LED_SIGNAL_ON_SETBITS ((STM3210E_LED2) << ON_SETBITS_SHIFT) +#define LED_SIGNAL_ON_CLRBITS ((0) << ON_CLRBITS_SHIFT) +#define LED_SIGNAL_OFF_SETBITS ((0) << OFF_SETBITS_SHIFT) +#define LED_SIGNAL_OFF_CLRBITS ((STM3210E_LED2) << OFF_CLRBITS_SHIFT) + +#define LED_ASSERTION_ON_SETBITS ((STM3210E_LED4) << ON_SETBITS_SHIFT) +#define LED_ASSERTION_ON_CLRBITS ((0) << ON_CLRBITS_SHIFT) +#define LED_ASSERTION_OFF_SETBITS ((0) << OFF_SETBITS_SHIFT) +#define LED_ASSERTION_OFF_CLRBITS ((STM3210E_LED4) << OFF_CLRBITS_SHIFT) + +#define LED_PANIC_ON_SETBITS ((STM3210E_LED4) << ON_SETBITS_SHIFT) +#define LED_PANIC_ON_CLRBITS ((0) << ON_CLRBITS_SHIFT) +#define LED_PANIC_OFF_SETBITS ((0) << OFF_SETBITS_SHIFT) +#define LED_PANIC_OFF_CLRBITS ((STM3210E_LED4) << OFF_CLRBITS_SHIFT) + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static const uint16_t g_ledbits[8] = +{ + (LED_STARTED_ON_SETBITS | LED_STARTED_ON_CLRBITS | + LED_STARTED_OFF_SETBITS | LED_STARTED_OFF_CLRBITS), + + (LED_HEAPALLOCATE_ON_SETBITS | LED_HEAPALLOCATE_ON_CLRBITS | + LED_HEAPALLOCATE_OFF_SETBITS | LED_HEAPALLOCATE_OFF_CLRBITS), + + (LED_IRQSENABLED_ON_SETBITS | LED_IRQSENABLED_ON_CLRBITS | + LED_IRQSENABLED_OFF_SETBITS | LED_IRQSENABLED_OFF_CLRBITS), + + (LED_STACKCREATED_ON_SETBITS | LED_STACKCREATED_ON_CLRBITS | + LED_STACKCREATED_OFF_SETBITS | LED_STACKCREATED_OFF_CLRBITS), + + (LED_INIRQ_ON_SETBITS | LED_INIRQ_ON_CLRBITS | + LED_INIRQ_OFF_SETBITS | LED_INIRQ_OFF_CLRBITS), + + (LED_SIGNAL_ON_SETBITS | LED_SIGNAL_ON_CLRBITS | + LED_SIGNAL_OFF_SETBITS | LED_SIGNAL_OFF_CLRBITS), + + (LED_ASSERTION_ON_SETBITS | LED_ASSERTION_ON_CLRBITS | + LED_ASSERTION_OFF_SETBITS | LED_ASSERTION_OFF_CLRBITS), + + (LED_PANIC_ON_SETBITS | LED_PANIC_ON_CLRBITS | + LED_PANIC_OFF_SETBITS | LED_PANIC_OFF_CLRBITS) +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +static inline void led_clrbits(unsigned int clrbits) +{ + if ((clrbits & STM3210E_LED1) != 0) + { + stm32_gpiowrite(GPIO_LED1, false); + } + + if ((clrbits & STM3210E_LED2) != 0) + { + stm32_gpiowrite(GPIO_LED2, false); + } + + if ((clrbits & STM3210E_LED3) != 0) + { + stm32_gpiowrite(GPIO_LED3, false); + } + + if ((clrbits & STM3210E_LED4) != 0) + { + stm32_gpiowrite(GPIO_LED4, false); + } +} + +static inline void led_setbits(unsigned int setbits) +{ + if ((setbits & STM3210E_LED1) != 0) + { + stm32_gpiowrite(GPIO_LED1, true); + } + + if ((setbits & STM3210E_LED2) != 0) + { + stm32_gpiowrite(GPIO_LED2, true); + } + + if ((setbits & STM3210E_LED3) != 0) + { + stm32_gpiowrite(GPIO_LED3, true); + } + + if ((setbits & STM3210E_LED4) != 0) + { + stm32_gpiowrite(GPIO_LED4, true); + } +} + +static void led_setonoff(unsigned int bits) +{ + led_clrbits(CLRBITS(bits)); + led_setbits(SETBITS(bits)); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_led_initialize + ****************************************************************************/ + +void stm32_led_initialize(void) +{ + /* Configure LED1-4 GPIOs for output */ + + stm32_configgpio(GPIO_LED1); + stm32_configgpio(GPIO_LED2); + stm32_configgpio(GPIO_LED3); + stm32_configgpio(GPIO_LED4); +} + +/**************************************************************************** + * Name: board_autoled_on + ****************************************************************************/ + +void board_autoled_on(int led) +{ + led_setonoff(ON_BITS(g_ledbits[led])); +} + +/**************************************************************************** + * Name: board_autoled_off + ****************************************************************************/ + +void board_autoled_off(int led) +{ + led_setonoff(OFF_BITS(g_ledbits[led])); +} + +#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32f4/stm3240g-eval/src/stm32_boot.c b/boards/arm/stm32f4/stm3240g-eval/src/stm32_boot.c new file mode 100644 index 0000000000000..f77dac198d8ec --- /dev/null +++ b/boards/arm/stm32f4/stm3240g-eval/src/stm32_boot.c @@ -0,0 +1,118 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm3240g-eval/src/stm32_boot.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include + +#include "stm3240g-eval.h" + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_boardinitialize + * + * Description: + * All STM32 architectures must provide the following entry point. + * This entry point is called early in the initialization -- after all + * memory has been configured and mapped but before any devices have been + * initialized. + * + ****************************************************************************/ + +void stm32_boardinitialize(void) +{ +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || defined(CONFIG_STM32_SPI3) + /* Configure SPI chip selects if 1) SPI is not disabled, and 2) + * the weak function stm32_spidev_initialize() has been brought into the + * link. + */ + + if (stm32_spidev_initialize) + { + stm32_spidev_initialize(); + } +#endif + +#ifdef CONFIG_STM32_FSMC + /* If the FSMC is enabled, then enable SRAM access */ + + stm32_selectsram(); +#endif + +#ifdef CONFIG_STM32_OTGFS + /* Initialize USB if the 1) OTG FS controller is in the configuration and + * 2) disabled, and 3) the weak function stm32_usbinitialize() has been + * brought the weak function stm32_usbinitialize() has been brought into + * the build. + * Presumably either CONFIG_USBDEV or CONFIG_USBHOST is also selected. + */ + + if (stm32_usbinitialize) + { + stm32_usbinitialize(); + } +#endif + +#ifdef CONFIG_ARCH_LEDS + /* Configure on-board LEDs if LED support has been selected. */ + + stm32_led_initialize(); +#endif +} + +/**************************************************************************** + * Name: board_late_initialize + * + * Description: + * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_late_initialize(). board_late_initialize() will be + * called immediately after up_initialize() is called and just before the + * initial application is started. This additional initialization phase + * may be used, for example, to initialize board-specific device drivers. + * + ****************************************************************************/ + +#ifdef CONFIG_BOARD_LATE_INITIALIZE +void board_late_initialize(void) +{ + /* Perform the board initialization on the start-up thread. Some + * initializations may fail in this case due to the limited capability of + * the start-up thread. + */ + + stm32_bringup(); +} +#endif diff --git a/boards/arm/stm32f4/stm3240g-eval/src/stm32_bringup.c b/boards/arm/stm32f4/stm3240g-eval/src/stm32_bringup.c new file mode 100644 index 0000000000000..80e06aa4a9aee --- /dev/null +++ b/boards/arm/stm32f4/stm3240g-eval/src/stm32_bringup.c @@ -0,0 +1,390 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm3240g-eval/src/stm32_bringup.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include +#include + +#ifdef CONFIG_STM32_SPI1 +# include +# include +#endif + +#ifdef CONFIG_STM32_SDIO +# include +# include +#endif + +#ifdef CONFIG_STM32_OTGFS +# include "stm32_usbhost.h" +#endif + +#ifdef CONFIG_RTC_DRIVER +# include +# include "stm32_rtc.h" +#endif + +#ifdef CONFIG_VIDEO_FB +# include +#endif + +#ifdef CONFIG_INPUT_STMPE811 +# include +#endif + +#include "stm32.h" +#include "stm32_i2c.h" +#include "stm3240g-eval.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* For now, don't build in any SPI1 support -- NSH is not using it */ + +#undef CONFIG_STM32_SPI1 + +/* Assume that we support everything until convinced otherwise */ + +#define HAVE_MMCSD 1 +#define HAVE_USBDEV 1 +#define HAVE_USBHOST 1 +#define HAVE_RTC_DRIVER 1 + +/* Can't support MMC/SD features if mountpoints are disabled or if SDIO + * support is not enabled. + */ + +#if defined(CONFIG_DISABLE_MOUNTPOINT) || !defined(CONFIG_STM32_SDIO) +# undef HAVE_MMCSD +#endif + +/* Default MMC/SD minor number */ + +#ifdef HAVE_MMCSD +# ifndef CONFIG_NSH_MMCSDMINOR +# define CONFIG_NSH_MMCSDMINOR 0 +# endif + +/* Default MMC/SD SLOT number */ + +# if defined(CONFIG_NSH_MMCSDSLOTNO) && CONFIG_NSH_MMCSDSLOTNO != 0 +# error "Only one MMC/SD slot" +# undef CONFIG_NSH_MMCSDSLOTNO +# endif + +# ifndef CONFIG_NSH_MMCSDSLOTNO +# define CONFIG_NSH_MMCSDSLOTNO 0 +# endif +#endif + +/* Can't support USB host or device features if USB OTG FS is not enabled */ + +#ifndef CONFIG_STM32_OTGFS +# undef HAVE_USBDEV +# undef HAVE_USBHOST +#endif + +/* Can't support USB device is USB device is not enabled */ + +#ifndef CONFIG_USBDEV +# undef HAVE_USBDEV +#endif + +/* Can't support USB host is USB host is not enabled */ + +#ifndef CONFIG_USBHOST +# undef HAVE_USBHOST +#endif + +/* Check if we can support the RTC driver */ + +#if !defined(CONFIG_RTC) || !defined(CONFIG_RTC_DRIVER) +# undef HAVE_RTC_DRIVER +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_i2c_register + * + * Description: + * Register one I2C drivers for the I2C tool. + * + ****************************************************************************/ + +#ifdef HAVE_I2CTOOL +static void stm32_i2c_register(int bus) +{ + struct i2c_master_s *i2c; + int ret; + + i2c = stm32_i2cbus_initialize(bus); + if (i2c == NULL) + { + _err("ERROR: Failed to get I2C%d interface\n", bus); + } + else + { + ret = i2c_register(i2c, bus); + if (ret < 0) + { + _err("ERROR: Failed to register I2C%d driver: %d\n", bus, ret); + stm32_i2cbus_uninitialize(i2c); + } + } +} +#endif + +/**************************************************************************** + * Name: stm32_i2ctool + * + * Description: + * Register I2C drivers for the I2C tool. + * + ****************************************************************************/ + +#ifdef HAVE_I2CTOOL +static void stm32_i2ctool(void) +{ +#ifdef CONFIG_STM32_I2C1 + stm32_i2c_register(1); +#endif +#ifdef CONFIG_STM32_I2C2 + stm32_i2c_register(2); +#endif +#ifdef CONFIG_STM32_I2C3 + stm32_i2c_register(3); +#endif +} +#else +# define stm32_i2ctool() +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_bringup + * + * Description: + * Perform architecture-specific initialization + * + * CONFIG_BOARD_LATE_INITIALIZE=y : + * Called from board_late_initialize(). + * + ****************************************************************************/ + +int stm32_bringup(void) +{ +#ifdef HAVE_RTC_DRIVER + struct rtc_lowerhalf_s *lower; +#endif +#ifdef CONFIG_STM32_SPI1 + struct spi_dev_s *spi; + struct mtd_dev_s *mtd; +#endif +#ifdef HAVE_MMCSD + struct sdio_dev_s *sdio; +#endif + int ret; + + /* Register I2C drivers on behalf of the I2C tool */ + + stm32_i2ctool(); + +#ifdef HAVE_RTC_DRIVER + /* Instantiate the STM32 lower-half RTC driver */ + + lower = stm32_rtc_lowerhalf(); + if (!lower) + { + syslog(LOG_ERR, + "ERROR: Failed to instantiate the RTC lower-half driver\n"); + } + else + { + /* Bind the lower half driver and register the combined RTC driver + * as /dev/rtc0 + */ + + ret = rtc_initialize(0, lower); + if (ret < 0) + { + syslog(LOG_ERR, + "ERROR: Failed to bind/register the RTC driver: %d\n", + ret); + } + } +#endif + + /* Configure SPI-based devices */ + +#ifdef CONFIG_STM32_SPI1 + /* Get the SPI port */ + + spi = stm32_spibus_initialize(1); + if (!spi) + { + syslog(LOG_ERR, "ERROR: Failed to initialize SPI port 0\n"); + } + else + { + /* Now bind the SPI interface to the M25P64/128 SPI FLASH driver */ + + mtd = m25p_initialize(spi); + if (!mtd) + { + syslog(LOG_ERR, + "ERROR: Failed to bind SPI port 0 to SPI FLASH driver\n"); + } + } + +#warning "Now what are we going to do with this SPI FLASH driver?" +#endif + +#ifdef HAVE_MMCSD + /* Mount the SDIO-based MMC/SD block driver */ + + /* First, get an instance of the SDIO interface */ + + sdio = sdio_initialize(CONFIG_NSH_MMCSDSLOTNO); + if (!sdio) + { + syslog(LOG_ERR, + "ERROR: Failed to initialize SDIO slot %d\n", + CONFIG_NSH_MMCSDSLOTNO); + } + else + { + /* Now bind the SDIO interface to the MMC/SD driver */ + + ret = mmcsd_slotinitialize(CONFIG_NSH_MMCSDMINOR, sdio); + if (ret != OK) + { + syslog(LOG_ERR, + "ERROR: Failed to bind SDIO to the MMC/SD driver: %d\n", + ret); + } + + /* Then let's guess and say that there is a card in the slot. I need + * to check to see if the STM3240G-EVAL board supports a GPIO to + * detect if there is a card in the slot. + */ + + sdio_mediachange(sdio, true); + } +#endif + +#ifdef CONFIG_FS_PROCFS + /* Mount the procfs file system */ + + ret = nx_mount(NULL, "/proc", "procfs", 0, NULL); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to mount procfs at /proc: %d\n", ret); + } +#endif + +#ifdef HAVE_USBHOST + /* Initialize USB host operation. stm32_usbhost_initialize() starts a + * thread that will monitor for USB connection and disconnection events. + */ + + ret = stm32_usbhost_initialize(); + if (ret != OK) + { + syslog(LOG_ERR, "ERROR: Failed to initialize USB host: %d\n", ret); + } +#endif + +#ifdef CONFIG_VIDEO_FB + /* Initialize and register the simulated framebuffer driver */ + + ret = fb_register(0, 0); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: fb_register() failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_INPUT_STMPE811 + /* Initialize the touchscreen. + * WARNING: stm32_tsc_setup() cannot be called from the IDLE thread. + */ + + ret = stm32_tsc_setup(0); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_tsc_setup failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_PWM + /* Initialize PWM and register the PWM device. */ + + ret = stm32_pwm_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_pwm_setup() failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_ADC + /* Initialize ADC and register the ADC driver. */ + + ret = stm32_adc_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_adc_setup failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_STM32_CAN_CHARDRIVER + /* Initialize CAN and register the CAN driver. */ + + ret = stm32_can_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_can_setup failed: %d\n", ret); + } +#endif + + UNUSED(ret); + return OK; +} diff --git a/boards/arm/stm32f4/stm3240g-eval/src/stm32_buttons.c b/boards/arm/stm32f4/stm3240g-eval/src/stm32_buttons.c new file mode 100644 index 0000000000000..6f53a11fb24d5 --- /dev/null +++ b/boards/arm/stm32f4/stm3240g-eval/src/stm32_buttons.c @@ -0,0 +1,164 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm3240g-eval/src/stm32_buttons.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include +#include + +#include "stm3240g-eval.h" + +#ifdef CONFIG_ARCH_BUTTONS + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/* Pin configuration for each STM3210E-EVAL button. This array is indexed by + * the BUTTON_* and JOYSTICK_* definitions in board.h + */ + +static const uint32_t g_buttons[NUM_BUTTONS] = +{ + GPIO_BTN_WAKEUP, GPIO_BTN_TAMPER, GPIO_BTN_USER +}; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_button_initialize + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. + * + ****************************************************************************/ + +uint32_t board_button_initialize(void) +{ + int i; + + /* Configure the GPIO pins as inputs. NOTE that EXTI interrupts are + * configured for all pins. + */ + + for (i = 0; i < NUM_BUTTONS; i++) + { + stm32_configgpio(g_buttons[i]); + } + + return NUM_BUTTONS; +} + +/**************************************************************************** + * Name: board_buttons + ****************************************************************************/ + +uint32_t board_buttons(void) +{ + uint32_t ret = 0; + int i; + + /* Check that state of each key */ + + for (i = 0; i < NUM_BUTTONS; i++) + { + /* A LOW value means that the key is pressed for most keys. + * The exception is the WAKEUP button. + */ + + bool released = stm32_gpioread(g_buttons[i]); + if (i == BUTTON_WAKEUP) + { + released = !released; + } + + /* Accumulate the set of depressed (not released) keys */ + + if (!released) + { + ret |= (1 << i); + } + } + + return ret; +} + +/**************************************************************************** + * Button support. + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. + * + * After board_button_initialize() has been called, board_buttons() may be + * called to collect the state of all buttons. board_buttons() returns an + * 32-bit bit set with each bit associated with a button. See the + * BUTTON_*_BIT definitions in board.h for the meaning of each bit. + * + * board_button_irq() may be called to register an interrupt handler that + * will be called when a button is depressed or released. The ID value is a + * button enumeration value that uniquely identifies a button resource. See + * the BUTTON_* definitions in board.h for the meaning of enumeration + * value. + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_IRQBUTTONS +int board_button_irq(int id, xcpt_t irqhandler, void *arg) +{ + int ret = -EINVAL; + + /* The following should be atomic */ + + if (id >= MIN_IRQBUTTON && id <= MAX_IRQBUTTON) + { + ret = stm32_gpiosetevent(g_buttons[id], true, true, true, + irqhandler, arg); + } + + return ret; +} +#endif +#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/stm32f4/stm3240g-eval/src/stm32_can.c b/boards/arm/stm32f4/stm3240g-eval/src/stm32_can.c new file mode 100644 index 0000000000000..ec742a605d557 --- /dev/null +++ b/boards/arm/stm32f4/stm3240g-eval/src/stm32_can.c @@ -0,0 +1,102 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm3240g-eval/src/stm32_can.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32.h" +#include "stm32_can.h" +#include "stm3240g-eval.h" + +#ifdef CONFIG_CAN + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +#if defined(CONFIG_STM32_CAN1) && defined(CONFIG_STM32_CAN2) +# warning "Both CAN1 and CAN2 are enabled. Assuming only CAN1." +# undef CONFIG_STM32_CAN2 +#endif + +#ifdef CONFIG_STM32_CAN1 +# define CAN_PORT 1 +#else +# define CAN_PORT 2 +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_can_setup + * + * Description: + * Initialize CAN and register the CAN device + * + ****************************************************************************/ + +int stm32_can_setup(void) +{ +#if defined(CONFIG_STM32_CAN1) || defined(CONFIG_STM32_CAN2) + struct can_dev_s *can; + int ret; + + /* Call stm32_caninitialize() to get an instance of the CAN interface */ + + can = stm32_caninitialize(CAN_PORT); + if (can == NULL) + { + canerr("ERROR: Failed to get CAN interface\n"); + return -ENODEV; + } + + /* Register the CAN driver at "/dev/can0" */ + + ret = can_register("/dev/can0", can); + if (ret < 0) + { + canerr("ERROR: can_register failed: %d\n", ret); + return ret; + } + + return OK; +#else + return -ENODEV; +#endif +} + +#endif /* CONFIG_CAN */ diff --git a/boards/arm/stm32f4/stm3240g-eval/src/stm32_deselectlcd.c b/boards/arm/stm32f4/stm3240g-eval/src/stm32_deselectlcd.c new file mode 100644 index 0000000000000..ff9e69d2c0daa --- /dev/null +++ b/boards/arm/stm32f4/stm3240g-eval/src/stm32_deselectlcd.c @@ -0,0 +1,80 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm3240g-eval/src/stm32_deselectlcd.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include "arm_internal.h" +#include "stm32.h" +#include "stm3240g-eval.h" + +#ifdef CONFIG_STM32_FSMC + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_deselectlcd + * + * Description: + * Disable the LCD + * + ****************************************************************************/ + +void stm32_deselectlcd(void) +{ + /* Restore registers to their power up settings */ + + putreg32(0xffffffff, STM32_FSMC_BCR4); + + /* Bank1 NOR/SRAM timing register configuration */ + + putreg32(0x0fffffff, STM32_FSMC_BTR4); + + /* Disable AHB clocking to the FSMC */ + + stm32_fsmc_disable(); +} + +#endif /* CONFIG_STM32_FSMC */ diff --git a/boards/arm/stm32f4/stm3240g-eval/src/stm32_deselectsram.c b/boards/arm/stm32f4/stm3240g-eval/src/stm32_deselectsram.c new file mode 100644 index 0000000000000..2ced0277d8fb1 --- /dev/null +++ b/boards/arm/stm32f4/stm3240g-eval/src/stm32_deselectsram.c @@ -0,0 +1,80 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm3240g-eval/src/stm32_deselectsram.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include "arm_internal.h" +#include "stm32.h" +#include "stm3240g-eval.h" + +#ifdef CONFIG_STM32_FSMC + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_deselectsram + * + * Description: + * Disable SRAM + * + ****************************************************************************/ + +void stm32_deselectsram(void) +{ + /* Restore registers to their power up settings */ + + putreg32(FSMC_BCR_RSTVALUE, STM32_FSMC_BCR2); + + /* Bank1 NOR/SRAM timing register configuration */ + + putreg32(FSMC_BTR_RSTVALUE, STM32_FSMC_BTR2); + + /* Disable AHB clocking to the FSMC */ + + stm32_fsmc_disable(); +} + +#endif /* CONFIG_STM32_FSMC */ diff --git a/boards/arm/stm32f4/stm3240g-eval/src/stm32_extmem.c b/boards/arm/stm32f4/stm3240g-eval/src/stm32_extmem.c new file mode 100644 index 0000000000000..46afe66b92805 --- /dev/null +++ b/boards/arm/stm32f4/stm3240g-eval/src/stm32_extmem.c @@ -0,0 +1,141 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm3240g-eval/src/stm32_extmem.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32_gpio.h" +#include "stm32.h" +#include "stm3240g-eval.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifndef CONFIG_STM32_FSMC +# warning "FSMC is not enabled" +#endif + +#if STM32_NGPIO_PORTS < 6 +# error "Required GPIO ports not enabled" +#endif + +#define STM32_FSMC_NADDRCONFIGS 26 +#define STM32_FSMC_NDATACONFIGS 16 + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/* GPIO configurations common to most external memories */ + +static const uint32_t g_addressconfig[STM32_FSMC_NADDRCONFIGS] = +{ + GPIO_FSMC_A0, GPIO_FSMC_A1, GPIO_FSMC_A2, + GPIO_FSMC_A3, GPIO_FSMC_A4, GPIO_FSMC_A5, + GPIO_FSMC_A6, GPIO_FSMC_A7, GPIO_FSMC_A8, + GPIO_FSMC_A9, GPIO_FSMC_A10, GPIO_FSMC_A11, + GPIO_FSMC_A12, GPIO_FSMC_A13, GPIO_FSMC_A14, + GPIO_FSMC_A15, GPIO_FSMC_A16, GPIO_FSMC_A17, + GPIO_FSMC_A18, GPIO_FSMC_A19, GPIO_FSMC_A20, + GPIO_FSMC_A21, GPIO_FSMC_A22, GPIO_FSMC_A23, + GPIO_FSMC_A24, GPIO_FSMC_A25 +}; + +static const uint32_t g_dataconfig[STM32_FSMC_NDATACONFIGS] = +{ + GPIO_FSMC_D0, GPIO_FSMC_D1, GPIO_FSMC_D2, + GPIO_FSMC_D3, GPIO_FSMC_D4, GPIO_FSMC_D5, + GPIO_FSMC_D6, GPIO_FSMC_D7, GPIO_FSMC_D8, + GPIO_FSMC_D9, GPIO_FSMC_D10, GPIO_FSMC_D11, + GPIO_FSMC_D12, GPIO_FSMC_D13, GPIO_FSMC_D14, + GPIO_FSMC_D15 +}; + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_extmemgpios + * + * Description: + * Initialize GPIOs for external memory usage + * + ****************************************************************************/ + +void stm32_extmemgpios(const uint32_t *gpios, int ngpios) +{ + int i; + + /* Configure GPIOs */ + + for (i = 0; i < ngpios; i++) + { + stm32_configgpio(gpios[i]); + } +} + +/**************************************************************************** + * Name: stm32_extmemaddr + * + * Description: + * Initialize address line GPIOs for external memory access + * + ****************************************************************************/ + +void stm32_extmemaddr(int naddrs) +{ + stm32_extmemgpios(g_addressconfig, naddrs); +} + +/**************************************************************************** + * Name: stm32_extmemdata + * + * Description: + * Initialize data line GPIOs for external memory access + * + ****************************************************************************/ + +void stm32_extmemdata(int ndata) +{ + stm32_extmemgpios(g_dataconfig, ndata); +} diff --git a/boards/arm/stm32f4/stm3240g-eval/src/stm32_lcd.c b/boards/arm/stm32f4/stm3240g-eval/src/stm32_lcd.c new file mode 100644 index 0000000000000..0bd00dd976be1 --- /dev/null +++ b/boards/arm/stm32f4/stm3240g-eval/src/stm32_lcd.c @@ -0,0 +1,1188 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm3240g-eval/src/stm32_lcd.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* This driver supports the following LCDs on the STM324xG_EVAL board: + * + * AM-240320L8TNQW00H (LCD_ILI9320 or LCD_ILI9321) OR + * AM-240320D5TOQW01H (LCD_ILI9325) + */ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include + +#include "arm_internal.h" +#include "stm32.h" +#include "stm3240g-eval.h" + +#if !defined(CONFIG_STM3240G_ILI9320_DISABLE) || !defined(CONFIG_STM3240G_ILI9325_DISABLE) + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* CONFIG_STM3240G_ILI9320_DISABLE may be defined to disabled the + * AM-240320L8TNQW00H(LCD_ILI9320 or LCD_ILI9321) + * CONFIG_STM3240G_ILI9325_DISABLE may be defined to disabled the + * AM-240320D5TOQW01H(LCD_ILI9325) + */ + +/* Check contrast selection */ + +#if !defined(CONFIG_LCD_MAXCONTRAST) +# define CONFIG_LCD_MAXCONTRAST 1 +#endif + +/* Check power setting */ + +#if !defined(CONFIG_LCD_MAXPOWER) || CONFIG_LCD_MAXPOWER < 1 +# define CONFIG_LCD_MAXPOWER 1 +#endif + +#if CONFIG_LCD_MAXPOWER > 255 +# error "CONFIG_LCD_MAXPOWER must be less than 256 to fit in uint8_t" +#endif + +/* Check orientation */ + +#if defined(CONFIG_LCD_PORTRAIT) +# if defined(CONFIG_LCD_LANDSCAPE) || defined(CONFIG_LCD_RLANDSCAPE) || defined(CONFIG_LCD_RPORTRAIT) +# error "Cannot define both portrait and any other orientations" +# endif +#elif defined(CONFIG_LCD_RPORTRAIT) +# if defined(CONFIG_LCD_LANDSCAPE) || defined(CONFIG_LCD_RLANDSCAPE) +# error "Cannot define both rportrait and any other orientations" +# endif +#elif defined(CONFIG_LCD_LANDSCAPE) +# ifdef CONFIG_LCD_RLANDSCAPE +# error "Cannot define both landscape and any other orientations" +# endif +#elif !defined(CONFIG_LCD_RLANDSCAPE) +# define CONFIG_LCD_LANDSCAPE 1 +#endif + +/* Display/Color Properties *************************************************/ + +/* Display Resolution */ + +#if defined(CONFIG_LCD_LANDSCAPE) || defined(CONFIG_LCD_RLANDSCAPE) +# define STM3240G_XRES 320 +# define STM3240G_YRES 240 +#else +# define STM3240G_XRES 240 +# define STM3240G_YRES 320 +#endif + +/* Color depth and format */ + +#define STM3240G_BPP 16 +#define STM3240G_COLORFMT FB_FMT_RGB16_565 + +/* STM3240G-EVAL LCD Hardware Definitions ***********************************/ + +/* LCD /CS is CE4, Bank 3 of NOR/SRAM Bank 1~4 */ + +#define STM3240G_LCDBASE ((uintptr_t)(0x60000000 | 0x08000000)) +#define LCD ((struct lcd_regs_s *)STM3240G_LCDBASE) + +#define LCD_REG_0 0x00 +#define LCD_REG_1 0x01 +#define LCD_REG_2 0x02 +#define LCD_REG_3 0x03 +#define LCD_REG_4 0x04 +#define LCD_REG_5 0x05 +#define LCD_REG_6 0x06 +#define LCD_REG_7 0x07 +#define LCD_REG_8 0x08 +#define LCD_REG_9 0x09 +#define LCD_REG_10 0x0a +#define LCD_REG_12 0x0c +#define LCD_REG_13 0x0d +#define LCD_REG_14 0x0e +#define LCD_REG_15 0x0f +#define LCD_REG_16 0x10 +#define LCD_REG_17 0x11 +#define LCD_REG_18 0x12 +#define LCD_REG_19 0x13 +#define LCD_REG_20 0x14 +#define LCD_REG_21 0x15 +#define LCD_REG_22 0x16 +#define LCD_REG_23 0x17 +#define LCD_REG_24 0x18 +#define LCD_REG_25 0x19 +#define LCD_REG_26 0x1a +#define LCD_REG_27 0x1b +#define LCD_REG_28 0x1c +#define LCD_REG_29 0x1d +#define LCD_REG_30 0x1e +#define LCD_REG_31 0x1f +#define LCD_REG_32 0x20 +#define LCD_REG_33 0x21 +#define LCD_REG_34 0x22 +#define LCD_REG_36 0x24 +#define LCD_REG_37 0x25 +#define LCD_REG_40 0x28 +#define LCD_REG_41 0x29 +#define LCD_REG_43 0x2b +#define LCD_REG_45 0x2d +#define LCD_REG_48 0x30 +#define LCD_REG_49 0x31 +#define LCD_REG_50 0x32 +#define LCD_REG_51 0x33 +#define LCD_REG_52 0x34 +#define LCD_REG_53 0x35 +#define LCD_REG_54 0x36 +#define LCD_REG_55 0x37 +#define LCD_REG_56 0x38 +#define LCD_REG_57 0x39 +#define LCD_REG_58 0x3a +#define LCD_REG_59 0x3b +#define LCD_REG_60 0x3c +#define LCD_REG_61 0x3d +#define LCD_REG_62 0x3e +#define LCD_REG_63 0x3f +#define LCD_REG_64 0x40 +#define LCD_REG_65 0x41 +#define LCD_REG_66 0x42 +#define LCD_REG_67 0x43 +#define LCD_REG_68 0x44 +#define LCD_REG_69 0x45 +#define LCD_REG_70 0x46 +#define LCD_REG_71 0x47 +#define LCD_REG_72 0x48 +#define LCD_REG_73 0x49 +#define LCD_REG_74 0x4a +#define LCD_REG_75 0x4b +#define LCD_REG_76 0x4c +#define LCD_REG_77 0x4d +#define LCD_REG_78 0x4e +#define LCD_REG_79 0x4f +#define LCD_REG_80 0x50 +#define LCD_REG_81 0x51 +#define LCD_REG_82 0x52 +#define LCD_REG_83 0x53 +#define LCD_REG_96 0x60 +#define LCD_REG_97 0x61 +#define LCD_REG_106 0x6a +#define LCD_REG_118 0x76 +#define LCD_REG_128 0x80 +#define LCD_REG_129 0x81 +#define LCD_REG_130 0x82 +#define LCD_REG_131 0x83 +#define LCD_REG_132 0x84 +#define LCD_REG_133 0x85 +#define LCD_REG_134 0x86 +#define LCD_REG_135 0x87 +#define LCD_REG_136 0x88 +#define LCD_REG_137 0x89 +#define LCD_REG_139 0x8b +#define LCD_REG_140 0x8c +#define LCD_REG_141 0x8d +#define LCD_REG_143 0x8f +#define LCD_REG_144 0x90 +#define LCD_REG_145 0x91 +#define LCD_REG_146 0x92 +#define LCD_REG_147 0x93 +#define LCD_REG_148 0x94 +#define LCD_REG_149 0x95 +#define LCD_REG_150 0x96 +#define LCD_REG_151 0x97 +#define LCD_REG_152 0x98 +#define LCD_REG_153 0x99 +#define LCD_REG_154 0x9a +#define LCD_REG_157 0x9d +#define LCD_REG_164 0xa4 +#define LCD_REG_192 0xc0 +#define LCD_REG_193 0xc1 +#define LCD_REG_229 0xe5 + +/* LCD IDs */ + +#define ILI9320_ID 0x9320 +#define ILI9321_ID 0x9321 +#define ILI9325_ID 0x9325 + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/* LCD type */ + +enum lcd_type_e +{ + LCD_TYPE_UNKNOWN = 0, + LCD_TYPE_ILI9320, + LCD_TYPE_ILI9325 +}; + +/* This structure describes the LCD registers */ + +struct lcd_regs_s +{ + volatile uint16_t address; + volatile uint16_t value; +}; + +/* This structure describes the state of this driver */ + +struct stm3240g_dev_s +{ + /* Publicly visible device structure */ + + struct lcd_dev_s dev; + + /* Private LCD-specific information follows */ + + uint8_t type; /* LCD type. See enum lcd_type_e */ + uint8_t power; /* Current power setting */ +}; + +/**************************************************************************** + * Private Function Protototypes + ****************************************************************************/ + +/* Low Level LCD access */ + +static void stm3240g_writereg(uint8_t regaddr, uint16_t regval); +static uint16_t stm3240g_readreg(uint8_t regaddr); +static inline void stm3240g_gramselect(void); +static inline void stm3240g_writegram(uint16_t rgbval); +static void stm3240g_readnosetup(uint16_t *accum); +static uint16_t stm3240g_readnoshift(uint16_t *accum); +static void stm3240g_setcursor(uint16_t col, uint16_t row); + +/* LCD Data Transfer Methods */ + +static int stm3240g_putrun(struct lcd_dev_s *dev, + fb_coord_t row, fb_coord_t col, + const uint8_t *buffer, size_t npixels); +static int stm3240g_getrun(struct lcd_dev_s *dev, + fb_coord_t row, fb_coord_t col, + uint8_t *buffer, size_t npixels); + +/* LCD Configuration */ + +static int stm3240g_getvideoinfo(struct lcd_dev_s *dev, + struct fb_videoinfo_s *vinfo); +static int stm3240g_getplaneinfo(struct lcd_dev_s *dev, + unsigned int planeno, + struct lcd_planeinfo_s *pinfo); + +/* LCD RGB Mapping */ + +#ifdef CONFIG_FB_CMAP +# error "RGB color mapping not supported by this driver" +#endif + +/* Cursor Controls */ + +#ifdef CONFIG_FB_HWCURSOR +# error "Cursor control not supported by this driver" +#endif + +/* LCD Specific Controls */ + +static int stm3240g_getpower(struct lcd_dev_s *dev); +static int stm3240g_setpower(struct lcd_dev_s *dev, int power); +static int stm3240g_getcontrast(struct lcd_dev_s *dev); +static int stm3240g_setcontrast(struct lcd_dev_s *dev, + unsigned int contrast); + +/* Initialization */ + +static inline void stm3240g_lcdinitialize(void); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* This is working memory allocated by the LCD driver for each LCD device + * and for each color plane. This memory will hold one raster line of data. + * The size of the allocated run buffer must therefore be at least + * (bpp * xres / 8). Actual alignment of the buffer must conform to the + * bitwidth of the underlying pixel type. + * + * If there are multiple planes, they may share the same working buffer + * because different planes will not be operate on concurrently. However, + * if there are multiple LCD devices, they must each have unique run buffers. + */ + +static uint16_t g_runbuffer[STM3240G_XRES]; + +/* This structure describes the overall LCD video controller */ + +static const struct fb_videoinfo_s g_videoinfo = +{ + .fmt = STM3240G_COLORFMT, /* Color format: RGB16-565: RRRR RGGG GGGB BBBB */ + .xres = STM3240G_XRES, /* Horizontal resolution in pixel columns */ + .yres = STM3240G_YRES, /* Vertical resolution in pixel rows */ + .nplanes = 1, /* Number of color planes supported */ +}; + +/* This is the standard, NuttX Plane information object */ + +static const struct lcd_planeinfo_s g_planeinfo = +{ + .putrun = stm3240g_putrun, /* Put a run into LCD memory */ + .getrun = stm3240g_getrun, /* Get a run from LCD memory */ + .buffer = (uint8_t *)g_runbuffer, /* Run scratch buffer */ + .bpp = STM3240G_BPP, /* Bits-per-pixel */ +}; + +/* This is the standard, NuttX LCD driver object */ + +static struct stm3240g_dev_s g_lcddev = +{ + .dev = + { + /* LCD Configuration */ + + .getvideoinfo = stm3240g_getvideoinfo, + .getplaneinfo = stm3240g_getplaneinfo, + + /* LCD RGB Mapping -- Not supported */ + + /* Cursor Controls -- Not supported */ + + /* LCD Specific Controls */ + + .getpower = stm3240g_getpower, + .setpower = stm3240g_setpower, + .getcontrast = stm3240g_getcontrast, + .setcontrast = stm3240g_setcontrast, + }, +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm3240g_writereg + * + * Description: + * Write to an LCD register + * + ****************************************************************************/ + +static void stm3240g_writereg(uint8_t regaddr, uint16_t regval) +{ + /* Write the register address then write the register value */ + + LCD->address = regaddr; + LCD->value = regval; +} + +/**************************************************************************** + * Name: stm3240g_readreg + * + * Description: + * Read from an LCD register + * + ****************************************************************************/ + +static uint16_t stm3240g_readreg(uint8_t regaddr) +{ + /* Write the register address then read the register value */ + + LCD->address = regaddr; + return LCD->value; +} + +/**************************************************************************** + * Name: stm3240g_gramselect + * + * Description: + * Setup to read or write multiple pixels to the GRAM memory + * + ****************************************************************************/ + +static inline void stm3240g_gramselect(void) +{ + LCD->address = LCD_REG_34; +} + +/**************************************************************************** + * Name: stm3240g_writegram + * + * Description: + * Write one pixel to the GRAM memory + * + ****************************************************************************/ + +static inline void stm3240g_writegram(uint16_t rgbval) +{ + /* Write the value (GRAM register already selected) */ + + LCD->value = rgbval; +} + +/**************************************************************************** + * Name: stm3240g_readnosetup + * + * Description: + * Prime the operation by reading one pixel from the GRAM memory if + * necessary for this LCD type. When reading 16-bit gram data, there may + * be some shifts in the returned data: + * + * - ILI932x: Discard first dummy read; no shift in the return data + * + ****************************************************************************/ + +static void stm3240g_readnosetup(uint16_t *accum) +{ + /* Read-ahead one pixel */ + + *accum = LCD->value; +} + +/**************************************************************************** + * Name: stm3240g_readnoshift + * + * Description: + * Read one correctly aligned pixel from the GRAM memory. Possibly + * shifting the data and possibly swapping red and green components. + * + * - ILI932x: Unknown -- assuming colors are in the color order + * + ****************************************************************************/ + +static uint16_t stm3240g_readnoshift(uint16_t *accum) +{ + /* Read the value (GRAM register already selected) */ + + return LCD->value; +} + +/**************************************************************************** + * Name: stm3240g_setcursor + * + * Description: + * Set the cursor position. In landscape mode, the "column" is actually + * the physical Y position and the "row" is the physical X position. + * + ****************************************************************************/ + +static void stm3240g_setcursor(uint16_t col, uint16_t row) +{ + stm3240g_writereg(LCD_REG_32, row); /* GRAM horizontal address */ + stm3240g_writereg(LCD_REG_33, col); /* GRAM vertical address */ +} + +/**************************************************************************** + * Name: stm3240g_putrun + * + * Description: + * This method can be used to write a partial raster line to the LCD: + * + * dev - The lcd device + * row - Starting row to write to (range: 0 <= row < yres) + * col - Starting column to write to (range: 0 <= col <= xres-npixels) + * buffer - The buffer containing the run to be written to the LCD + * npixels - The number of pixels to write to the LCD + * (range: 0 < npixels <= xres-col) + * + ****************************************************************************/ + +static int stm3240g_putrun(struct lcd_dev_s *dev, + fb_coord_t row, fb_coord_t col, + const uint8_t *buffer, size_t npixels) +{ + const uint16_t *src = (const uint16_t *)buffer; + int i; + + /* Buffer must be provided and aligned to a 16-bit address boundary */ + + lcdinfo("row: %d col: %d npixels: %d\n", row, col, npixels); + DEBUGASSERT(buffer && ((uintptr_t)buffer & 1) == 0); + + /* Write the run to GRAM. */ + +#ifdef CONFIG_LCD_LANDSCAPE + /* Convert coordinates -- Here the edge away from the row of buttons on + * the STM3240G-EVAL is used as the top. + */ + + /* Write the GRAM data, manually incrementing X */ + + for (i = 0; i < npixels; i++) + { + /* Write the next pixel to this position */ + + stm3240g_setcursor(col, row); + stm3240g_gramselect(); + stm3240g_writegram(*src++); + + /* Increment to next column */ + + col++; + } +#elif defined(CONFIG_LCD_RLANDSCAPE) + /* Convert coordinates -- Here the edge next to the row of buttons on + * the STM3240G-EVAL is used as the top. + */ + + col = (STM3240G_XRES - 1) - col; + row = (STM3240G_YRES - 1) - row; + + /* Set the cursor position */ + + stm3240g_setcursor(col, row); + + /* Then write the GRAM data, auto-decrementing X */ + + stm3240g_gramselect(); + for (i = 0; i < npixels; i++) + { + /* Write the next pixel to this position + * (auto-decrements to the next column) + */ + + stm3240g_writegram(*src++); + } +#elif defined(CONFIG_LCD_PORTRAIT) + + /* Convert coordinates. + * In this configuration, the top of the display is to the left of the + * buttons (if the board is held so that the buttons are at the bottom of + * the board). + */ + + col = (STM3240G_XRES - 1) - col; + + /* Then write the GRAM data, manually incrementing Y (which is col) */ + + for (i = 0; i < npixels; i++) + { + /* Write the next pixel to this position */ + + stm3240g_setcursor(row, col); + stm3240g_gramselect(); + stm3240g_writegram(*src++); + + /* Increment to next column */ + + col--; + } +#else /* CONFIG_LCD_RPORTRAIT */ + + /* Convert coordinates. + * In this configuration, the top of the display is to the right of the + * buttons (if the board is held so that the buttons are at the bottom of + * the board). + */ + + row = (STM3240G_YRES - 1) - row; + + /* Then write the GRAM data, manually incrementing Y (which is col) */ + + for (i = 0; i < npixels; i++) + { + /* Write the next pixel to this position */ + + stm3240g_setcursor(row, col); + stm3240g_gramselect(); + stm3240g_writegram(*src++); + + /* Decrement to next column */ + + col++; + } +#endif + + return OK; +} + +/**************************************************************************** + * Name: stm3240g_getrun + * + * Description: + * This method can be used to read a partial raster line from the LCD: + * + * dev - The lcd device + * row - Starting row to read from (range: 0 <= row < yres) + * col - Starting column to read read (range: 0 <= col <= xres-npixels) + * buffer - The buffer in which to return the run read from the LCD + * npixels - The number of pixels to read from the LCD + * (range: 0 < npixels <= xres-col) + * + ****************************************************************************/ + +static int stm3240g_getrun(struct lcd_dev_s *dev, + fb_coord_t row, fb_coord_t col, + uint8_t *buffer, size_t npixels) +{ + uint16_t *dest = (uint16_t *)buffer; + void (*readsetup)(uint16_t *accum); + uint16_t (*readgram)(uint16_t *accum); + uint16_t accum; + int i; + + /* Buffer must be provided and aligned to a 16-bit address boundary */ + + lcdinfo("row: %d col: %d npixels: %d\n", row, col, npixels); + DEBUGASSERT(buffer && ((uintptr_t)buffer & 1) == 0); + + /* Configure according to the LCD type. + * Kind of silly with only one LCD type. + */ + + switch (g_lcddev.type) + { + case LCD_TYPE_ILI9320: + case LCD_TYPE_ILI9325: + readsetup = stm3240g_readnosetup; + readgram = stm3240g_readnoshift; + break; + + default: /* Shouldn't happen */ + return -ENOSYS; + } + + /* Read the run from GRAM. */ + +#ifdef CONFIG_LCD_LANDSCAPE + /* Convert coordinates -- Here the edge away from the row of buttons on + * the STM3240G-EVAL is used as the top. + */ + + for (i = 0; i < npixels; i++) + { + /* Read the next pixel from this position */ + + stm3240g_setcursor(row, col); + stm3240g_gramselect(); + readsetup(&accum); + *dest++ = readgram(&accum); + + /* Increment to next column */ + + col++; + } +#elif defined(CONFIG_LCD_RLANDSCAPE) + /* Convert coordinates -- Here the edge next to the row of buttons on + * the STM3240G-EVAL is used as the top. + */ + + col = (STM3240G_XRES - 1) - col; + row = (STM3240G_YRES - 1) - row; + + /* Set the cursor position */ + + stm3240g_setcursor(col, row); + + /* Then read the GRAM data, auto-decrementing Y */ + + stm3240g_gramselect(); + + /* Prime the pump for unaligned read data */ + + readsetup(&accum); + + for (i = 0; i < npixels; i++) + { + /* Read the next pixel from this position + * (autoincrements to the next row) + */ + + *dest++ = readgram(&accum); + } +#elif defined(CONFIG_LCD_PORTRAIT) + /* Convert coordinates. + * In this configuration, the top of the display is to the left of the + * buttons (if the board is held so that the buttons are at the bottom of + * the board). + */ + + col = (STM3240G_XRES - 1) - col; + + /* Then read the GRAM data, manually incrementing Y (which is col) */ + + for (i = 0; i < npixels; i++) + { + /* Read the next pixel from this position */ + + stm3240g_setcursor(row, col); + stm3240g_gramselect(); + readsetup(&accum); + *dest++ = readgram(&accum); + + /* Increment to next column */ + + col--; + } +#else /* CONFIG_LCD_RPORTRAIT */ + /* Convert coordinates. + * In this configuration, the top of the display is to the right of the + * buttons (if the board is held so that the buttons are at the bottom of + * the board). + */ + + row = (STM3240G_YRES - 1) - row; + + /* Then write the GRAM data, manually incrementing Y (which is col) */ + + for (i = 0; i < npixels; i++) + { + /* Write the next pixel to this position */ + + stm3240g_setcursor(row, col); + stm3240g_gramselect(); + readsetup(&accum); + *dest++ = readgram(&accum); + + /* Decrement to next column */ + + col++; + } +#endif + + return OK; +} + +/**************************************************************************** + * Name: stm3240g_getvideoinfo + * + * Description: + * Get information about the LCD video controller configuration. + * + ****************************************************************************/ + +static int stm3240g_getvideoinfo(struct lcd_dev_s *dev, + struct fb_videoinfo_s *vinfo) +{ + DEBUGASSERT(dev && vinfo); + lcdinfo("fmt: %d xres: %d yres: %d nplanes: %d\n", + g_videoinfo.fmt, g_videoinfo.xres, + g_videoinfo.yres, g_videoinfo.nplanes); + memcpy(vinfo, &g_videoinfo, sizeof(struct fb_videoinfo_s)); + return OK; +} + +/**************************************************************************** + * Name: stm3240g_getplaneinfo + * + * Description: + * Get information about the configuration of each LCD color plane. + * + ****************************************************************************/ + +static int stm3240g_getplaneinfo(struct lcd_dev_s *dev, + unsigned int planeno, + struct lcd_planeinfo_s *pinfo) +{ + DEBUGASSERT(dev && pinfo && planeno == 0); + lcdinfo("planeno: %d bpp: %d\n", planeno, g_planeinfo.bpp); + memcpy(pinfo, &g_planeinfo, sizeof(struct lcd_planeinfo_s)); + pinfo->dev = dev; + return OK; +} + +/**************************************************************************** + * Name: stm3240g_getpower + * + * Description: + * Get the LCD panel power status + * (0: full off - CONFIG_LCD_MAXPOWER: full on). On backlit LCDs, + * this setting may correspond to the backlight setting. + * + ****************************************************************************/ + +static int stm3240g_getpower(struct lcd_dev_s *dev) +{ + lcdinfo("power: %d\n", 0); + return g_lcddev.power; +} + +/**************************************************************************** + * Name: stm3240g_poweroff + * + * Description: + * Enable/disable LCD panel power + * (0: full off - CONFIG_LCD_MAXPOWER: full on). On backlit LCDs, + * this setting may correspond to the backlight setting. + * + ****************************************************************************/ + +static int stm3240g_poweroff(void) +{ + /* Turn the display off */ + + stm3240g_writereg(LCD_REG_7, 0); + + /* Remember the power off state */ + + g_lcddev.power = 0; + return OK; +} + +/**************************************************************************** + * Name: stm3240g_setpower + * + * Description: + * Enable/disable LCD panel power + * (0: full off - CONFIG_LCD_MAXPOWER: full on). On backlit LCDs, + * this setting may correspond to the backlight setting. + * + ****************************************************************************/ + +static int stm3240g_setpower(struct lcd_dev_s *dev, int power) +{ + lcdinfo("power: %d\n", power); + DEBUGASSERT((unsigned)power <= CONFIG_LCD_MAXPOWER); + + /* Set new power level */ + + if (power > 0) + { + /* Then turn the display on */ + +#if !defined(CONFIG_STM3240G_ILI9320_DISABLE) || !defined(CONFIG_STM3240G_ILI9325_DISABLE) + stm3240g_writereg(LCD_REG_7, 0x0173); +#endif + g_lcddev.power = power; + } + else + { + /* Turn the display off */ + + stm3240g_poweroff(); + } + + return OK; +} + +/**************************************************************************** + * Name: stm3240g_getcontrast + * + * Description: + * Get the current contrast setting (0-CONFIG_LCD_MAXCONTRAST). + * + ****************************************************************************/ + +static int stm3240g_getcontrast(struct lcd_dev_s *dev) +{ + lcdinfo("Not implemented\n"); + return -ENOSYS; +} + +/**************************************************************************** + * Name: stm3240g_setcontrast + * + * Description: + * Set LCD panel contrast (0-CONFIG_LCD_MAXCONTRAST). + * + ****************************************************************************/ + +static int stm3240g_setcontrast(struct lcd_dev_s *dev, unsigned int contrast) +{ + lcdinfo("contrast: %d\n", contrast); + return -ENOSYS; +} + +/**************************************************************************** + * Name: stm3240g_lcdinitialize + * + * Description: + * Set LCD panel contrast (0-CONFIG_LCD_MAXCONTRAST). + * + ****************************************************************************/ + +static inline void stm3240g_lcdinitialize(void) +{ + uint16_t id; + + /* Check LCD ID */ + + id = stm3240g_readreg(LCD_REG_0); + lcdinfo("LCD ID: %04x\n", id); + + /* Check if the ID is for the STM32_ILI9320 (or ILI9321) or STM32_ILI9325 */ + +#if !defined(CONFIG_STM3240G_ILI9320_DISABLE) && !defined(CONFIG_STM3240G_ILI9325_DISABLE) + if (id == ILI9320_ID || id == ILI9321_ID || id == ILI9325_ID) +#elif !defined(CONFIG_STM3240G_ILI9320_DISABLE) && defined(CONFIG_STM3240G_ILI9325_DISABLE) + if (id == ILI9320_ID || id == ILI9321_ID) +#else /* if defined(CONFIG_STM3240G_ILI9320_DISABLE) && !defined(CONFIG_STM3240G_ILI9325_DISABLE)) */ + if (id == ILI9325_ID) +#endif + { + /* Save the LCD type + * (not actually used at for anything important) + */ + +#if !defined(CONFIG_STM3240G_ILI9320_DISABLE) +# if !defined(CONFIG_STM3240G_ILI9325_DISABLE) + if (id == ILI9325_ID) + { + g_lcddev.type = LCD_TYPE_ILI9325; + } + else +# endif + { + g_lcddev.type = LCD_TYPE_ILI9320; + stm3240g_writereg(LCD_REG_229, 0x8000); /* Set the internal vcore voltage */ + } +#else /* if !defined(CONFIG_STM3240G_ILI9325_DISABLE) */ + g_lcddev.type = LCD_TYPE_ILI9325; +#endif + lcdinfo("LCD type: %d\n", g_lcddev.type); + + /* Start Initial Sequence */ + + stm3240g_writereg(LCD_REG_0, 0x0001); /* Start internal OSC. */ + stm3240g_writereg(LCD_REG_1, 0x0100); /* Set SS and SM bit */ + stm3240g_writereg(LCD_REG_2, 0x0700); /* Set 1 line inversion */ + stm3240g_writereg(LCD_REG_3, 0x1030); /* Set GRAM write direction and BGR=1. */ + + /* stm3240g_writereg(LCD_REG_3, 0x1018); + * Set GRAM write direction and BGR=1. + */ + + stm3240g_writereg(LCD_REG_4, 0x0000); /* Resize register */ + stm3240g_writereg(LCD_REG_8, 0x0202); /* Set the back porch and front porch */ + stm3240g_writereg(LCD_REG_9, 0x0000); /* Set non-display area refresh cycle ISC[3:0] */ + stm3240g_writereg(LCD_REG_10, 0x0000); /* FMARK function */ + stm3240g_writereg(LCD_REG_12, 0x0000); /* RGB interface setting */ + stm3240g_writereg(LCD_REG_13, 0x0000); /* Frame marker Position */ + stm3240g_writereg(LCD_REG_15, 0x0000); /* RGB interface polarity */ + + /* Power On sequence */ + + stm3240g_writereg(LCD_REG_16, 0x0000); /* SAP, BT[3:0], AP, DSTB, SLP, STB */ + stm3240g_writereg(LCD_REG_17, 0x0000); /* DC1[2:0], DC0[2:0], VC[2:0] */ + stm3240g_writereg(LCD_REG_18, 0x0000); /* VREG1OUT voltage */ + stm3240g_writereg(LCD_REG_19, 0x0000); /* VDV[4:0] for VCOM amplitude */ + up_mdelay(200); /* Dis-charge capacitor power voltage (200ms) */ + + stm3240g_writereg(LCD_REG_16, 0x17b0); /* SAP, BT[3:0], AP, DSTB, SLP, STB */ + stm3240g_writereg(LCD_REG_17, 0x0137); /* DC1[2:0], DC0[2:0], VC[2:0] */ + up_mdelay(50); + + stm3240g_writereg(LCD_REG_18, 0x0139); /* VREG1OUT voltage */ + up_mdelay(50); + + stm3240g_writereg(LCD_REG_19, 0x1d00); /* VDV[4:0] for VCOM amplitude */ + stm3240g_writereg(LCD_REG_41, 0x0013); /* VCM[4:0] for VCOMH */ + up_mdelay(50); + + stm3240g_writereg(LCD_REG_32, 0x0000); /* GRAM horizontal Address */ + stm3240g_writereg(LCD_REG_33, 0x0000); /* GRAM Vertical Address */ + + /* Adjust the Gamma Curve (ILI9320/1) */ + +#if !defined(CONFIG_STM3240G_ILI9320_DISABLE) +# if !defined(CONFIG_STM3240G_ILI9325_DISABLE) + if (g_lcddev.type == LCD_TYPE_ILI9320) +# endif + { + stm3240g_writereg(LCD_REG_48, 0x0006); + stm3240g_writereg(LCD_REG_49, 0x0101); + stm3240g_writereg(LCD_REG_50, 0x0003); + stm3240g_writereg(LCD_REG_53, 0x0106); + stm3240g_writereg(LCD_REG_54, 0x0b02); + stm3240g_writereg(LCD_REG_55, 0x0302); + stm3240g_writereg(LCD_REG_56, 0x0707); + stm3240g_writereg(LCD_REG_57, 0x0007); + stm3240g_writereg(LCD_REG_60, 0x0600); + stm3240g_writereg(LCD_REG_61, 0x020b); + } +#endif + + /* Adjust the Gamma Curve (ILI9325) */ + +#if !defined(CONFIG_STM3240G_ILI9325_DISABLE) +# if !defined(CONFIG_STM3240G_ILI9320_DISABLE) + else +# endif + { + stm3240g_writereg(LCD_REG_48, 0x0007); + stm3240g_writereg(LCD_REG_49, 0x0302); + stm3240g_writereg(LCD_REG_50, 0x0105); + stm3240g_writereg(LCD_REG_53, 0x0206); + stm3240g_writereg(LCD_REG_54, 0x0808); + stm3240g_writereg(LCD_REG_55, 0x0206); + stm3240g_writereg(LCD_REG_56, 0x0504); + stm3240g_writereg(LCD_REG_57, 0x0007); + stm3240g_writereg(LCD_REG_60, 0x0105); + stm3240g_writereg(LCD_REG_61, 0x0808); + } +#endif + + /* Set GRAM area */ + + stm3240g_writereg(LCD_REG_80, 0x0000); /* Horizontal GRAM Start Address */ + stm3240g_writereg(LCD_REG_81, 0x00ef); /* Horizontal GRAM End Address */ + stm3240g_writereg(LCD_REG_82, 0x0000); /* Vertical GRAM Start Address */ + stm3240g_writereg(LCD_REG_83, 0x013f); /* Vertical GRAM End Address */ + stm3240g_writereg(LCD_REG_96, 0x2700); /* Gate Scan Line */ + + /* stm3240g_writereg(LCD_REG_96, 0xa700); + * Gate Scan Line(GS=1, scan direction is G320~G1) + */ + + stm3240g_writereg(LCD_REG_97, 0x0001); /* NDL,VLE, REV */ + stm3240g_writereg(LCD_REG_106, 0x0000); /* Set scrolling line */ + + /* Partial Display Control */ + + stm3240g_writereg(LCD_REG_128, 0x0000); + stm3240g_writereg(LCD_REG_129, 0x0000); + stm3240g_writereg(LCD_REG_130, 0x0000); + stm3240g_writereg(LCD_REG_131, 0x0000); + stm3240g_writereg(LCD_REG_132, 0x0000); + stm3240g_writereg(LCD_REG_133, 0x0000); + + /* Panel Control */ + + stm3240g_writereg(LCD_REG_144, 0x0010); + stm3240g_writereg(LCD_REG_146, 0x0000); + stm3240g_writereg(LCD_REG_147, 0x0003); + stm3240g_writereg(LCD_REG_149, 0x0110); + stm3240g_writereg(LCD_REG_151, 0x0000); + stm3240g_writereg(LCD_REG_152, 0x0000); + + /* Set GRAM write direction and BGR = 1 + * + * I/D=01 (Horizontal : increment, Vertical : decrement) + * AM=1 (address is updated in vertical writing direction) + */ + + stm3240g_writereg(LCD_REG_3, 0x1018); + stm3240g_writereg(LCD_REG_7, 0); /* Display off */ + } + else + { + lcderr("ERROR: Unsupported LCD type\n"); + } +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_lcd_initialize + * + * Description: + * Initialize the LCD video hardware. The initial state of the LCD is + * fully initialized, display memory cleared, and the LCD ready to use, + * but with the power setting at 0 (full off). + * + ****************************************************************************/ + +int board_lcd_initialize(void) +{ + lcdinfo("Initializing\n"); + + /* Configure GPIO pins and configure the FSMC to support the LCD */ + + stm32_selectlcd(); + + /* Configure and enable LCD */ + + up_mdelay(50); + stm3240g_lcdinitialize(); + + /* Clear the display (setting it to the color 0=black) */ + + stm3240g_lcdclear(0); + + /* Turn the display off */ + + stm3240g_poweroff(); + return OK; +} + +/**************************************************************************** + * Name: board_lcd_getdev + * + * Description: + * Return a a reference to the LCD object for the specified LCD. + * This allows support for multiple LCD devices. + * + ****************************************************************************/ + +struct lcd_dev_s *board_lcd_getdev(int lcddev) +{ + DEBUGASSERT(lcddev == 0); + return &g_lcddev.dev; +} + +/**************************************************************************** + * Name: board_lcd_uninitialize + * + * Description: + * Uninitialize the LCD support + * + ****************************************************************************/ + +void board_lcd_uninitialize(void) +{ + stm3240g_poweroff(); + stm32_deselectlcd(); +} + +/**************************************************************************** + * Name: stm3240g_lcdclear + * + * Description: + * This is a non-standard LCD interface just for the stm3240g-EVAL board. + * Because of the various rotations, clearing the display in the normal way + * by writing a sequences of runs that covers the entire display can be + * very slow. Here the display is cleared by simply setting all GRAM + * memory to the specified color. + * + ****************************************************************************/ + +void stm3240g_lcdclear(uint16_t color) +{ + uint32_t i = 0; + + stm3240g_setcursor(0, STM3240G_XRES - 1); + stm3240g_gramselect(); + for (i = 0; i < STM3240G_XRES * STM3240G_YRES; i++) + { + LCD->value = color; + } +} + +#endif /* !CONFIG_STM3240G_ILI9320_DISABLE || !CONFIG_STM3240G_ILI9325_DISABLE */ diff --git a/boards/arm/stm32f4/stm3240g-eval/src/stm32_pwm.c b/boards/arm/stm32f4/stm3240g-eval/src/stm32_pwm.c new file mode 100644 index 0000000000000..4182be207e593 --- /dev/null +++ b/boards/arm/stm32f4/stm3240g-eval/src/stm32_pwm.c @@ -0,0 +1,105 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm3240g-eval/src/stm32_pwm.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include + +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32_pwm.h" +#include "stm3240g-eval.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* PWM + * + * The STM3240G-Eval has no real on-board PWM devices, but the board can be + * configured to output a pulse train using variously unused pins on the + * board for PWM output (see board.h for details of pins). + */ + +#ifdef CONFIG_PWM + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_pwm_setup + * + * Description: + * Initialize PWM and register the PWM device. + * + ****************************************************************************/ + +int stm32_pwm_setup(void) +{ + static bool initialized = false; + struct pwm_lowerhalf_s *pwm; + int ret; + + /* Have we already initialized? */ + + if (!initialized) + { + /* Call stm32_pwminitialize() to get an instance of the PWM interface */ + + pwm = stm32_pwminitialize(STM3240G_EVAL_PWMTIMER); + if (!pwm) + { + aerr("ERROR: Failed to get the STM32 PWM lower half\n"); + return -ENODEV; + } + + /* Register the PWM driver at "/dev/pwm0" */ + + ret = pwm_register("/dev/pwm0", pwm); + if (ret < 0) + { + aerr("ERROR: pwm_register failed: %d\n", ret); + return ret; + } + + /* Now we are initialized */ + + initialized = true; + } + + return OK; +} + +#endif /* CONFIG_PWM */ diff --git a/boards/arm/stm32f4/stm3240g-eval/src/stm32_selectlcd.c b/boards/arm/stm32f4/stm3240g-eval/src/stm32_selectlcd.c new file mode 100644 index 0000000000000..e8ec7732462ec --- /dev/null +++ b/boards/arm/stm32f4/stm3240g-eval/src/stm32_selectlcd.c @@ -0,0 +1,155 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm3240g-eval/src/stm32_selectlcd.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32.h" +#include +#include "stm3240g-eval.h" + +#ifdef CONFIG_STM32_FSMC + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#if STM32_NGPIO_PORTS < 6 +# error "Required GPIO ports not enabled" +#endif + +/* SRAM pin definitions */ + +#define LCD_NADDRLINES 1 +#define LCD_NDATALINES 16 + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* Pin Usage (per schematic) + * SRAM LCD + * D[0..15] [0..15] [0..15] + * A[0..25] [0..22] [0] RS + * FSMC_NBL0 PE0 OUT --- --- + * FSMC_NBL1 PE1 OUT --- --- + * FSMC_NE2 PG9 OUT --- --- + * FSMC_NE3 PG10 OUT --- ~CS + * FSMC_NE4 PG12 OUT --- --- + * FSMC_NWE PD5 OUT --- ~WR/SCL + * FSMC_NOE PD4 OUT --- ~RD + * FSMC_NWAIT PD6 IN --- --- + * FSMC_INT2 PG6* IN --- --- + * FSMC_INT3 + * FSMC_INTR + * FSMC_CD + * FSMC_CLK + * FSMC_NCE2 + * FSMC_NCE3 + * FSMC_NCE4_1 + * FSMC_NCE4_2 + * FSMC_NIORD + * FSMC_NIOWR + * FSMC_NL + * FSMC_NREG + */ + +/* GPIO configurations unique to the LCD */ + +static const uint32_t g_lcdconfig[] = +{ + /* NOE, NWE, and NE3 */ + + GPIO_FSMC_NOE, GPIO_FSMC_NWE, GPIO_FSMC_NE3 +}; +#define NLCD_CONFIG (sizeof(g_lcdconfig)/sizeof(uint32_t)) + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_selectlcd + * + * Description: + * Initialize to the LCD + * + ****************************************************************************/ + +void stm32_selectlcd(void) +{ + /* Configure new GPIO pins */ + + stm32_extmemaddr(LCD_NADDRLINES); /* Common address lines: A0 */ + stm32_extmemdata(LCD_NDATALINES); /* Common data lines: D0-D15 */ + stm32_extmemgpios(g_lcdconfig, NLCD_CONFIG); /* LCD-specific control lines */ + + /* Enable AHB clocking to the FSMC */ + + stm32_fsmc_enable(); + + /* Color LCD configuration (LCD configured as follow): + * + * - Data/Address MUX = Disable "FSMC_BCR_MUXEN" just not enable it. + * - Extended Mode = Disable "FSMC_BCR_EXTMOD" + * - Memory Type = SRAM "FSMC_BCR_SRAM" + * - Data Width = 16bit "FSMC_BCR_MWID16" + * - Write Operation = Enable "FSMC_BCR_WREN" + * - Asynchronous Wait = Disable + */ + + /* Bank3 NOR/SRAM control register configuration */ + + putreg32(FSMC_BCR_SRAM | FSMC_BCR_MWID16 | FSMC_BCR_WREN, STM32_FSMC_BCR3); + + /* Bank3 NOR/SRAM timing register configuration */ + + putreg32(FSMC_BTR_ADDSET(5) | FSMC_BTR_ADDHLD(1) | + FSMC_BTR_DATAST(9) | FSMC_BTR_BUSTURN(1) | + FSMC_BTR_CLKDIV(1) | FSMC_BTR_DATLAT(2) | + FSMC_BTR_ACCMODA, STM32_FSMC_BTR3); + + putreg32(0xffffffff, STM32_FSMC_BWTR3); + + /* Enable the bank by setting the MBKEN bit */ + + putreg32(FSMC_BCR_MBKEN | FSMC_BCR_SRAM | + FSMC_BCR_MWID16 | FSMC_BCR_WREN, STM32_FSMC_BCR3); +} + +#endif /* CONFIG_STM32_FSMC */ diff --git a/boards/arm/stm32f4/stm3240g-eval/src/stm32_selectsram.c b/boards/arm/stm32f4/stm3240g-eval/src/stm32_selectsram.c new file mode 100644 index 0000000000000..2fd43e8b2fb50 --- /dev/null +++ b/boards/arm/stm32f4/stm3240g-eval/src/stm32_selectsram.c @@ -0,0 +1,186 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm3240g-eval/src/stm32_selectsram.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32.h" +#include +#include "stm3240g-eval.h" + +#ifdef CONFIG_STM32_FSMC + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#if STM32_NGPIO_PORTS < 6 +# error "Required GPIO ports not enabled" +#endif + +/* SRAM Timing */ + +#define SRAM_ADDRESS_SETUP_TIME 3 +#define SRAM_ADDRESS_HOLD_TIME 1 +#define SRAM_DATA_SETUP_TIME 6 +#define SRAM_BUS_TURNAROUND_DURATION 1 +#define SRAM_CLK_DIVISION 1 +#define SRAM_DATA_LATENCY 2 + +/* SRAM pin definitions */ + +#define SRAM_NADDRLINES 21 +#define SRAM_NDATALINES 16 + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* GPIOs Configuration ****************************************************** + * PD0 <-> FSMC_D2 PE0 <-> FSMC_NBL0 PF0 <-> FSMC_A0 PG0 <-> FSMC_A10 + * PD1 <-> FSMC_D3 PE1 <-> FSMC_NBL1 PF1 <-> FSMC_A1 PG1 <-> FSMC_A11 + * PD4 <-> FSMC_NOE PE3 <-> FSMC_A19 PF2 <-> FSMC_A2 PG2 <-> FSMC_A12 + * PD5 <-> FSMC_NWE PE4 <-> FSMC_A20 PF3 <-> FSMC_A3 PG3 <-> FSMC_A13 + * PD8 <-> FSMC_D13 PE7 <-> FSMC_D4 PF4 <-> FSMC_A4 PG4 <-> FSMC_A14 + * PD9 <-> FSMC_D14 PE8 <-> FSMC_D5 PF5 <-> FSMC_A5 PG5 <-> FSMC_A15 + * PD10 <-> FSMC_D15 PE9 <-> FSMC_D6 PF12 <-> FSMC_A6 PG9 <-> FSMC_NE2 + * PD11 <-> FSMC_A16 PE10 <-> FSMC_D7 PF13 <-> FSMC_A7 + * PD12 <-> FSMC_A17 PE11 <-> FSMC_D8 PF14 <-> FSMC_A8 + * PD13 <-> FSMC_A18 PE12 <-> FSMC_D9 PF15 <-> FSMC_A9 + * PD14 <-> FSMC_D0 PE13 <-> FSMC_D10 + * PD15 <-> FSMC_D1 PE14 <-> FSMC_D11 + * PE15 <-> FSMC_D12 + */ + +/* GPIO configurations unique to SRAM */ + +static const uint32_t g_sramconfig[] = +{ + /* NE3, NBL0, NBL1, */ + + GPIO_FSMC_NOE, GPIO_FSMC_NWE, GPIO_FSMC_NBL0, GPIO_FSMC_NBL1, GPIO_FSMC_NE2 +}; +#define NSRAM_CONFIG (sizeof(g_sramconfig)/sizeof(uint32_t)) + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_selectsram + * + * Description: + * Initialize to access external SRAM. SRAM will be visible at the FSMC + * Bank NOR/SRAM2 base address (0x64000000) + * + * General transaction rules. The requested AHB transaction data size can + * be 8-, 16- or 32-bit wide whereas the SRAM has a fixed 16-bit data + * width. Some simple transaction rules must be followed: + * + * Case 1: AHB transaction width and SRAM data width are equal + * There is no issue in this case. + * Case 2: AHB transaction size is greater than the memory size + * In this case, the FSMC splits the AHB transaction into smaller + * consecutive memory accesses in order to meet the external data width. + * Case 3: AHB transaction size is smaller than the memory size. + * SRAM supports the byte select feature. + * a) FSMC allows write transactions accessing the right data through its + * byte lanes (NBL[1:0]) + * b) Read transactions are allowed (the controller reads the entire + * memory word and uses the needed byte only). The NBL[1:0] are always + * kept low during read transactions. + * + ****************************************************************************/ + +void stm32_selectsram(void) +{ + /* Configure new GPIO pins */ + + stm32_extmemaddr(SRAM_NADDRLINES); /* Common address lines: A0-A20 */ + stm32_extmemdata(SRAM_NDATALINES); /* Common data lines: D0-D15 */ + stm32_extmemgpios(g_sramconfig, NSRAM_CONFIG); /* SRAM-specific control lines */ + + /* Enable AHB clocking to the FSMC */ + + stm32_fsmc_enable(); + + /* Bank1 NOR/SRAM control register configuration + * + * Bank enable : Not yet + * Data address mux : Disabled + * Memory Type : PSRAM + * Data bus width : 16-bits + * Flash access : Disabled + * Burst access mode : Disabled + * Polarity : Low + * Wrapped burst mode : Disabled + * Write timing : Before state + * Write enable : Yes + * Wait signal : Disabled + * Extended mode : Disabled + * Asynchronous wait : Disabled + * Write burst : Disabled + */ + + putreg32((FSMC_BCR_PSRAM | FSMC_BCR_MWID16 | + FSMC_BCR_WREN), STM32_FSMC_BCR2); + + /* Bank1 NOR/SRAM timing register configuration */ + + putreg32((FSMC_BTR_ADDSET(SRAM_ADDRESS_SETUP_TIME) | + FSMC_BTR_ADDHLD(SRAM_ADDRESS_HOLD_TIME) | + FSMC_BTR_DATAST(SRAM_DATA_SETUP_TIME) | + FSMC_BTR_BUSTURN(SRAM_BUS_TURNAROUND_DURATION) | + FSMC_BTR_CLKDIV(SRAM_CLK_DIVISION) | + FSMC_BTR_DATLAT(SRAM_DATA_LATENCY) | + FSMC_BTR_ACCMODA), + STM32_FSMC_BTR2); + + /* Bank1 NOR/SRAM timing register for write configuration, + * if extended mode is used + */ + + putreg32(0xffffffff, STM32_FSMC_BWTR2); /* Extended mode not used */ + + /* Enable the bank */ + + putreg32((FSMC_BCR_MBKEN | FSMC_BCR_PSRAM | + FSMC_BCR_MWID16 | FSMC_BCR_WREN), STM32_FSMC_BCR2); +} + +#endif /* CONFIG_STM32_FSMC */ diff --git a/boards/arm/stm32f4/stm3240g-eval/src/stm32_spi.c b/boards/arm/stm32f4/stm3240g-eval/src/stm32_spi.c new file mode 100644 index 0000000000000..b14ec2bd65965 --- /dev/null +++ b/boards/arm/stm32f4/stm3240g-eval/src/stm32_spi.c @@ -0,0 +1,129 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm3240g-eval/src/stm32_spi.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "arm_internal.h" +#include "chip.h" +#include "stm32.h" +#include "stm3240g-eval.h" + +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || defined(CONFIG_STM32_SPI3) + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_spidev_initialize + * + * Description: + * Called to configure SPI chip select GPIO pins for the STM3240G-EVAL + * board. + * + ****************************************************************************/ + +void weak_function stm32_spidev_initialize(void) +{ +#warning "Missing logic" +} + +/**************************************************************************** + * Name: stm32_spi1/2/3select and stm32_spi1/2/3status + * + * Description: + * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status + * must be provided by board-specific logic. They are implementations of + * the select and status methods of the SPI interface defined by struct + * spi_ops_s (see include/nuttx/spi/spi.h). All other methods + * (including stm32_spibus_initialize()) are provided by common STM32 + * logic. To use this common SPI logic on your board: + * + * 1. Provide logic in stm32_boardinitialize() to configure SPI chip select + * pins. + * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() functions + * in your board-specific logic. These functions will perform chip + * selection and status operations using GPIOs in the way your board is + * configured. + * 3. Add a calls to stm32_spibus_initialize() in your low level + * application initialization logic + * 4. The handle returned by stm32_spibus_initialize() may then be used to + * bind the SPI driver to higher level logic (e.g., calling + * mmcsd_spislotinitialize(), for example, will bind the SPI driver to + * the SPI MMC/SD driver). + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_SPI1 +void stm32_spi1select(struct spi_dev_s *dev, + uint32_t devid, bool selected) +{ + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); +} + +uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) +{ + return SPI_STATUS_PRESENT; +} +#endif + +#ifdef CONFIG_STM32_SPI2 +void stm32_spi2select(struct spi_dev_s *dev, + uint32_t devid, bool selected) +{ + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); +} + +uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) +{ + return SPI_STATUS_PRESENT; +} +#endif + +#ifdef CONFIG_STM32_SPI3 +void stm32_spi3select(struct spi_dev_s *dev, + uint32_t devid, bool selected) +{ + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); +} + +uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid) +{ + return SPI_STATUS_PRESENT; +} +#endif + +#endif /* CONFIG_STM32_SPI1 || CONFIG_STM32_SPI2 */ diff --git a/boards/arm/stm32f4/stm3240g-eval/src/stm32_stmpe811.c b/boards/arm/stm32f4/stm3240g-eval/src/stm32_stmpe811.c new file mode 100644 index 0000000000000..ec55412bec3fb --- /dev/null +++ b/boards/arm/stm32f4/stm3240g-eval/src/stm32_stmpe811.c @@ -0,0 +1,340 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm3240g-eval/src/stm32_stmpe811.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include + +#include "stm32.h" +#include "stm3240g-eval.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +#ifdef CONFIG_INPUT_STMPE811 +#ifndef CONFIG_INPUT +# error "STMPE811 support requires CONFIG_INPUT" +#endif + +#ifndef CONFIG_STM32_I2C1 +# error "STMPE811 support requires CONFIG_STM32_I2C1" +#endif + +#ifndef CONFIG_STMPE811_I2C +# error "Only the STMPE811 I2C interface is supported" +#endif + +#ifdef CONFIG_STMPE811_SPI +# error "Only the STMPE811 SPI interface is supported" +#endif + +#ifndef CONFIG_STMPE811_FREQUENCY +# define CONFIG_STMPE811_FREQUENCY 100000 +#endif + +#ifndef CONFIG_STMPE811_I2CDEV +# define CONFIG_STMPE811_I2CDEV 1 +#endif + +#if CONFIG_STMPE811_I2CDEV != 1 +# error "CONFIG_STMPE811_I2CDEV must be one" +#endif + +#ifndef CONFIG_STMPE811_DEVMINOR +# define CONFIG_STMPE811_DEVMINOR 0 +#endif + +/* Board definitions ********************************************************/ + +/* The STM3240G-EVAL has two STMPE811QTR I/O expanders on board both + * connected to the STM32 via I2C1. + * They share a common interrupt line: PI2. + * + * STMPE811 U24, I2C address 0x41 (7-bit) + * ------ ---- ---------------- -------------------------------------------- + * STPE11 PIN BOARD SIGNAL BOARD CONNECTION + * ------ ---- ---------------- -------------------------------------------- + * Y- TouchScreen_Y- LCD Connector XL + * X- TouchScreen_X- LCD Connector XR + * Y+ TouchScreen_Y+ LCD Connector XD + * X+ TouchScreen_X+ LCD Connector XU + * IN3 EXP_IO9 + * IN2 EXP_IO10 + * IN1 EXP_IO11 + * IN0 EXP_IO12 + * + * STMPE811 U29, I2C address 0x44 (7-bit) + * ------ ---- ---------------- -------------------------------------------- + * STPE11 PIN BOARD SIGNAL BOARD CONNECTION + * ------ ---- ---------------- -------------------------------------------- + * Y- EXP_IO1 + * X- EXP_IO2 + * Y+ EXP_IO3 + * X+ EXP_IO4 + * IN3 EXP_IO5 + * IN2 EXP_IO6 + * IN1 EXP_IO7 + * IN0 EXP_IO8 + */ + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +struct stm32_stmpe811config_s +{ + /* Configuration structure as seen by the STMPE811 driver */ + + struct stmpe811_config_s config; + + /* Additional private definitions only known to this driver */ + + STMPE811_HANDLE handle; /* The STMPE811 driver handle */ + xcpt_t handler; /* The STMPE811 interrupt handler */ + void *arg; /* Interrupt handler argument */ +}; + +/**************************************************************************** + * Static Function Prototypes + ****************************************************************************/ + +/* IRQ/GPIO access callbacks. These operations all hidden behind callbacks + * to isolate the STMPE811 driver from differences in GPIO + * interrupt handling by varying boards and MCUs.* so that contact and + * loss-of-contact events can be detected. + * + * attach - Attach the STMPE811 interrupt handler to the GPIO interrupt + * enable - Enable or disable the GPIO interrupt + * clear - Acknowledge/clear any pending GPIO interrupt + */ + +static int stmpe811_attach(struct stmpe811_config_s *state, xcpt_t isr, + void *arg); +static void stmpe811_enable(struct stmpe811_config_s *state, + bool enable); +static void stmpe811_clear(struct stmpe811_config_s *state); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* A reference to a structure of this type must be passed to the STMPE811 + * driver. This structure provides information about the configuration + * of the STMPE811 and provides some board-specific hooks. + * + * Memory for this structure is provided by the caller. It is not copied + * by the driver and is presumed to persist while the driver is active. The + * memory must be writable because, under certain circumstances, the driver + * may modify frequency or X plate resistance values. + */ + +#ifndef CONFIG_STMPE811_TSC_DISABLE +static struct stm32_stmpe811config_s g_stmpe811config = +{ + .config = + { +#ifdef CONFIG_STMPE811_I2C + .address = STMPE811_ADDR1, +#endif + .frequency = CONFIG_STMPE811_FREQUENCY, + +#ifdef CONFIG_STMPE811_MULTIPLE + .irq = STM32_IRQ_EXTI2, +#endif + .ctrl1 = (ADC_CTRL1_SAMPLE_TIME_80 | ADC_CTRL1_MOD_12B), + .ctrl2 = ADC_CTRL2_ADC_FREQ_3p25, + + .attach = stmpe811_attach, + .enable = stmpe811_enable, + .clear = stmpe811_clear, + }, + .handler = NULL, + .arg = NULL, +}; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/* IRQ/GPIO access callbacks. These operations all hidden behind + * callbacks to isolate the STMPE811 driver from differences in GPIO + * interrupt handling by varying boards and MCUs. + * + * attach - Attach the STMPE811 interrupt handler to the GPIO interrupt + * enable - Enable or disable the GPIO interrupt + * clear - Acknowledge/clear any pending GPIO interrupt + */ + +static int stmpe811_attach(struct stmpe811_config_s *state, xcpt_t isr, + void *arg) +{ + struct stm32_stmpe811config_s *priv = + (struct stm32_stmpe811config_s *)state; + + iinfo("Saving handler %p\n", isr); + DEBUGASSERT(priv); + + /* Just save the handler. + * We will use it when EXTI interruptsare enabled + */ + + priv->handler = isr; + priv->arg = arg; + return OK; +} + +static void stmpe811_enable(struct stmpe811_config_s *state, bool enable) +{ + struct stm32_stmpe811config_s *priv = + (struct stm32_stmpe811config_s *)state; + irqstate_t flags; + + /* Attach and enable, or detach and disable. Enabling and disabling GPIO + * interrupts is a multi-step process so the safest thing is to keep + * interrupts disabled during the reconfiguration. + */ + + flags = enter_critical_section(); + if (enable) + { + /* Configure the EXTI interrupt using the SAVED handler */ + + stm32_gpiosetevent(GPIO_IO_EXPANDER, true, true, true, + priv->handler, priv->arg); + } + else + { + /* Configure the EXTI interrupt with a NULL handler to disable it */ + + stm32_gpiosetevent(GPIO_IO_EXPANDER, false, false, false, + NULL, NULL); + } + + leave_critical_section(flags); +} + +static void stmpe811_clear(struct stmpe811_config_s *state) +{ + /* Does nothing */ +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_tsc_setup + * + * Description: + * This function is called by board-bringup logic to configure the + * touchscreen device. This function will register the driver as + * /dev/inputN where N is the minor device number. + * + * Input Parameters: + * minor - The input device minor number + * + * Returned Value: + * Zero is returned on success. Otherwise, a negated errno value is + * returned to indicate the nature of the failure. + * + ****************************************************************************/ + +int stm32_tsc_setup(int minor) +{ +#ifndef CONFIG_STMPE811_TSC_DISABLE + struct i2c_master_s *dev; + int ret; + + iinfo("minor %d\n", minor); + DEBUGASSERT(minor == 0); + + /* Check if we are already initialized */ + + if (!g_stmpe811config.handle) + { + iinfo("Initializing\n"); + + /* Configure the STMPE811 interrupt pin as an input */ + + stm32_configgpio(GPIO_IO_EXPANDER); + + /* Get an instance of the I2C interface */ + + dev = stm32_i2cbus_initialize(CONFIG_STMPE811_I2CDEV); + if (!dev) + { + ierr("ERROR: Failed to initialize I2C bus %d\n", + CONFIG_STMPE811_I2CDEV); + return -ENODEV; + } + + /* Instantiate the STMPE811 driver */ + + g_stmpe811config.handle = + stmpe811_instantiate(dev, + (struct stmpe811_config_s *)&g_stmpe811config); + if (!g_stmpe811config.handle) + { + ierr("ERROR: Failed to instantiate the STMPE811 driver\n"); + return -ENODEV; + } + + /* Initialize and register the I2C touchscreen device */ + + ret = stmpe811_register(g_stmpe811config.handle, + CONFIG_STMPE811_DEVMINOR); + if (ret < 0) + { + ierr("ERROR: Failed to register STMPE driver: %d\n", ret); + + /* stm32_i2cbus_uninitialize(dev); */ + + return -ENODEV; + } + } + + return OK; +#else + return -ENOSYS; +#endif +} + +#endif /* CONFIG_INPUT_STMPE811 */ diff --git a/boards/arm/stm32f4/stm3240g-eval/src/stm32_usb.c b/boards/arm/stm32f4/stm3240g-eval/src/stm32_usb.c new file mode 100644 index 0000000000000..9f7e3c0c97c6c --- /dev/null +++ b/boards/arm/stm32f4/stm3240g-eval/src/stm32_usb.c @@ -0,0 +1,304 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm3240g-eval/src/stm32_usb.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include "arm_internal.h" +#include "stm32.h" +#include "stm32_otgfs.h" +#include "stm3240g-eval.h" + +#ifdef CONFIG_STM32_OTGFS + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#if defined(CONFIG_USBDEV) || defined(CONFIG_USBHOST) +# define HAVE_USB 1 +#else +# warning "CONFIG_STM32_OTGFS is enabled but neither CONFIG_USBDEV nor CONFIG_USBHOST" +# undef HAVE_USB +#endif + +#ifndef CONFIG_USBHOST_DEFPRIO +# define CONFIG_USBHOST_DEFPRIO 50 +#endif + +#ifndef CONFIG_USBHOST_STACKSIZE +# ifdef CONFIG_USBHOST_HUB +# define CONFIG_USBHOST_STACKSIZE 1536 +# else +# define CONFIG_USBHOST_STACKSIZE 1024 +# endif +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +static struct usbhost_connection_s *g_usbconn; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: usbhost_waiter + * + * Description: + * Wait for USB devices to be connected. + * + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +static int usbhost_waiter(int argc, char *argv[]) +{ + struct usbhost_hubport_s *hport; + + uinfo("Running\n"); + for (; ; ) + { + /* Wait for the device to change state */ + + DEBUGVERIFY(CONN_WAIT(g_usbconn, &hport)); + uinfo("%s\n", hport->connected ? "connected" : "disconnected"); + + /* Did we just become connected? */ + + if (hport->connected) + { + /* Yes.. enumerate the newly connected device */ + + CONN_ENUMERATE(g_usbconn, hport); + } + } + + /* Keep the compiler from complaining */ + + return 0; +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_usbinitialize + * + * Description: + * Called from stm32_usbinitialize very early in initialization to setup + * USB-related GPIO pins for the STM3240G-EVAL board. + * + ****************************************************************************/ + +void stm32_usbinitialize(void) +{ + /* The OTG FS has an internal soft pull-up. + * No GPIO configuration is required + */ + + /* Configure the OTG FS VBUS sensing GPIO, + * Power On, and Overcurrent GPIOs + */ + +#ifdef CONFIG_STM32_OTGFS + stm32_configgpio(GPIO_OTGFS_VBUS); + stm32_configgpio(GPIO_OTGFS_PWRON); + stm32_configgpio(GPIO_OTGFS_OVER); +#endif +} + +/**************************************************************************** + * Name: stm32_usbhost_initialize + * + * Description: + * Called at application startup time to initialize the USB host + * functionality. + * This function will start a thread that will monitor for device + * connection/disconnection events. + * + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +int stm32_usbhost_initialize(void) +{ + int ret; + + /* First, register all of the class drivers needed to support the drivers + * that we care about: + */ + + uinfo("Register class drivers\n"); + +#ifdef CONFIG_USBHOST_MSC + /* Register the USB mass storage class class */ + + ret = usbhost_msc_initialize(); + if (ret != OK) + { + uerr("ERROR: Failed to register the mass storage class: %d\n", ret); + } +#endif + +#ifdef CONFIG_USBHOST_CDCACM + /* Register the CDC/ACM serial class */ + + ret = usbhost_cdcacm_initialize(); + if (ret != OK) + { + uerr("ERROR: Failed to register the CDC/ACM serial class: %d\n", ret); + } +#endif + + /* Then get an instance of the USB host interface */ + + uinfo("Initialize USB host\n"); + g_usbconn = stm32_otgfshost_initialize(0); + if (g_usbconn) + { + /* Start a thread to handle device connection. */ + + uinfo("Start usbhost_waiter\n"); + + ret = kthread_create("usbhost", CONFIG_USBHOST_DEFPRIO, + CONFIG_USBHOST_STACKSIZE, + usbhost_waiter, NULL); + return ret < 0 ? -ENOEXEC : OK; + } + + return -ENODEV; +} +#endif + +/**************************************************************************** + * Name: stm32_usbhost_vbusdrive + * + * Description: + * Enable/disable driving of VBUS 5V output. This function must be + * provided be each platform that implements the STM32 OTG FS host + * interface + * + * "On-chip 5 V VBUS generation is not supported. For this reason, a + * charge pump or, if 5 V are available on the application board, a + * basic power switch, must be added externally to drive the 5 V VBUS + * line. The external charge pump can be driven by any GPIO output. + * When the application decides to power on VBUS using the chosen GPIO, + * it must also set the port power bit in the host port control and + * status register (PPWR bit in OTG_FS_HPRT). + * + * "The application uses this field to control power to this port, + * and the core clears this bit on an overcurrent condition." + * + * Input Parameters: + * iface - For future growth to handle multiple USB host interface. + * Should be zero. + * enable - true: enable VBUS power; false: disable VBUS power + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +void stm32_usbhost_vbusdrive(int iface, bool enable) +{ + DEBUGASSERT(iface == 0); + + if (enable) + { + /* Enable the Power Switch by driving the enable pin low */ + + stm32_gpiowrite(GPIO_OTGFS_PWRON, false); + } + else + { + /* Disable the Power Switch by driving the enable pin high */ + + stm32_gpiowrite(GPIO_OTGFS_PWRON, true); + } +} +#endif + +/**************************************************************************** + * Name: stm32_setup_overcurrent + * + * Description: + * Setup to receive an interrupt-level callback if an overcurrent + * condition is detected. + * + * Input Parameters: + * handler - New overcurrent interrupt handler + * arg - The argument provided for the interrupt handler + * + * Returned Value: + * Zero (OK) is returned on success. Otherwise, a negated errno value + * is returned to indicate the nature of the failure. + * + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +int stm32_setup_overcurrent(xcpt_t handler, void *arg) +{ + return stm32_gpiosetevent(GPIO_OTGFS_OVER, true, true, true, handler, arg); +} +#endif + +/**************************************************************************** + * Name: stm32_usbsuspend + * + * Description: + * Board logic must provide the stm32_usbsuspend logic if the USBDEV + * driver is used. This function is called whenever the USB enters or + * leaves suspend mode. This is an opportunity for the board logic to + * shutdown clocks, power, etc. while the USB is suspended. + * + ****************************************************************************/ + +#ifdef CONFIG_USBDEV +void stm32_usbsuspend(struct usbdev_s *dev, bool resume) +{ + uinfo("resume: %d\n", resume); +} +#endif + +#endif /* CONFIG_STM32_OTGFS */ diff --git a/boards/arm/stm32f4/stm3240g-eval/src/stm32_userleds.c b/boards/arm/stm32f4/stm3240g-eval/src/stm32_userleds.c new file mode 100644 index 0000000000000..48f0eb969509f --- /dev/null +++ b/boards/arm/stm32f4/stm3240g-eval/src/stm32_userleds.c @@ -0,0 +1,96 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm3240g-eval/src/stm32_userleds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32.h" +#include "stm3240g-eval.h" + +#ifndef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* This array maps an LED number to GPIO pin configuration */ + +static uint32_t g_ledcfg[BOARD_NLEDS] = +{ + GPIO_LED1, GPIO_LED2, GPIO_LED3, GPIO_LED4 +}; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_userled_initialize + ****************************************************************************/ + +uint32_t board_userled_initialize(void) +{ + /* Configure LED1-4 GPIOs for output */ + + stm32_configgpio(GPIO_LED1); + stm32_configgpio(GPIO_LED2); + stm32_configgpio(GPIO_LED3); + stm32_configgpio(GPIO_LED4); + return BOARD_NLEDS; +} + +/**************************************************************************** + * Name: board_userled + ****************************************************************************/ + +void board_userled(int led, bool ledon) +{ + if ((unsigned)led < BOARD_NLEDS) + { + stm32_gpiowrite(g_ledcfg[led], ledon); + } +} + +/**************************************************************************** + * Name: board_userled_all + ****************************************************************************/ + +void board_userled_all(uint32_t ledset) +{ + stm32_gpiowrite(GPIO_LED1, (ledset & BOARD_LED1_BIT) == 0); + stm32_gpiowrite(GPIO_LED2, (ledset & BOARD_LED2_BIT) == 0); + stm32_gpiowrite(GPIO_LED3, (ledset & BOARD_LED3_BIT) == 0); + stm32_gpiowrite(GPIO_LED4, (ledset & BOARD_LED4_BIT) == 0); +} + +#endif /* !CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32f4/stm32f401rc-rs485/CMakeLists.txt b/boards/arm/stm32f4/stm32f401rc-rs485/CMakeLists.txt new file mode 100644 index 0000000000000..ef6c336e42215 --- /dev/null +++ b/boards/arm/stm32f4/stm32f401rc-rs485/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32f4/stm32f401rc-rs485/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/arm/stm32/stm32f401rc-rs485/Kconfig b/boards/arm/stm32f4/stm32f401rc-rs485/Kconfig similarity index 100% rename from boards/arm/stm32/stm32f401rc-rs485/Kconfig rename to boards/arm/stm32f4/stm32f401rc-rs485/Kconfig diff --git a/boards/arm/stm32f4/stm32f401rc-rs485/configs/adc/defconfig b/boards/arm/stm32f4/stm32f401rc-rs485/configs/adc/defconfig new file mode 100644 index 0000000000000..18ba4c3363436 --- /dev/null +++ b/boards/arm/stm32f4/stm32f401rc-rs485/configs/adc/defconfig @@ -0,0 +1,67 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +CONFIG_ADC=y +CONFIG_ANALOG=y +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f401rc-rs485" +CONFIG_ARCH_BOARD_STM32F401RC_RS485=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F401RC=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQBUTTONS=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL_USBDEVCTRL=y +CONFIG_BOARD_LOOPSPERMSEC=8499 +CONFIG_BUILTIN=y +CONFIG_CDCACM=y +CONFIG_CDCACM_CONSOLE=y +CONFIG_EXAMPLES_ADC=y +CONFIG_EXAMPLES_ADC_SWTRIG=y +CONFIG_EXAMPLES_BUTTONS=y +CONFIG_EXAMPLES_BUTTONS_NAME0="SW3" +CONFIG_EXAMPLES_BUTTONS_NAME1="SW4" +CONFIG_EXAMPLES_BUTTONS_NAME2="SW5" +CONFIG_EXAMPLES_BUTTONS_NAMES=y +CONFIG_EXAMPLES_BUTTONS_QTD=3 +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INPUT=y +CONFIG_INPUT_BUTTONS=y +CONFIG_INPUT_BUTTONS_LOWER=y +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=98304 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_SPI=y +CONFIG_START_DAY=5 +CONFIG_START_MONTH=5 +CONFIG_START_YEAR=2014 +CONFIG_STM32_ADC1=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PWR=y +CONFIG_STM32_USART6=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USBDEV=y diff --git a/boards/arm/stm32f4/stm32f401rc-rs485/configs/bmp280/defconfig b/boards/arm/stm32f4/stm32f401rc-rs485/configs/bmp280/defconfig new file mode 100644 index 0000000000000..702fd4ebb5f16 --- /dev/null +++ b/boards/arm/stm32f4/stm32f401rc-rs485/configs/bmp280/defconfig @@ -0,0 +1,69 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f401rc-rs485" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_STM32F401RC_RS485=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F401RC=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQBUTTONS=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BMP280_I2C_ADDR_77=y +CONFIG_BOARDCTL_USBDEVCTRL=y +CONFIG_BOARD_LOOPSPERMSEC=8499 +CONFIG_BUILTIN=y +CONFIG_CDCACM=y +CONFIG_CDCACM_CONSOLE=y +CONFIG_EXAMPLES_BMP280=y +CONFIG_EXAMPLES_BUTTONS=y +CONFIG_EXAMPLES_BUTTONS_NAME0="SW3" +CONFIG_EXAMPLES_BUTTONS_NAME1="SW4" +CONFIG_EXAMPLES_BUTTONS_NAME2="SW5" +CONFIG_EXAMPLES_BUTTONS_NAMES=y +CONFIG_EXAMPLES_BUTTONS_QTD=3 +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INPUT=y +CONFIG_INPUT_BUTTONS=y +CONFIG_INPUT_BUTTONS_LOWER=y +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_FLOATINGPOINT=y +CONFIG_LINE_MAX=64 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=98304 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_SENSORS=y +CONFIG_SENSORS_BMP280=y +CONFIG_SPI=y +CONFIG_START_DAY=5 +CONFIG_START_MONTH=5 +CONFIG_START_YEAR=2014 +CONFIG_STM32_I2C1=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PWR=y +CONFIG_STM32_USART6=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USBDEV=y diff --git a/boards/arm/stm32f4/stm32f401rc-rs485/configs/dac/defconfig b/boards/arm/stm32f4/stm32f401rc-rs485/configs/dac/defconfig new file mode 100644 index 0000000000000..dfa0032c87be6 --- /dev/null +++ b/boards/arm/stm32f4/stm32f401rc-rs485/configs/dac/defconfig @@ -0,0 +1,67 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f401rc-rs485" +CONFIG_ARCH_BOARD_STM32F401RC_RS485=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F401RC=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQBUTTONS=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL_USBDEVCTRL=y +CONFIG_BOARD_LOOPSPERMSEC=8499 +CONFIG_BUILTIN=y +CONFIG_CDCACM=y +CONFIG_CDCACM_CONSOLE=y +CONFIG_EXAMPLES_BUTTONS=y +CONFIG_EXAMPLES_BUTTONS_NAME0="SW3" +CONFIG_EXAMPLES_BUTTONS_NAME1="SW4" +CONFIG_EXAMPLES_BUTTONS_NAME2="SW5" +CONFIG_EXAMPLES_BUTTONS_NAMES=y +CONFIG_EXAMPLES_BUTTONS_QTD=3 +CONFIG_EXAMPLES_PWM=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INPUT=y +CONFIG_INPUT_BUTTONS=y +CONFIG_INPUT_BUTTONS_LOWER=y +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_PWM=y +CONFIG_RAM_SIZE=98304 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_SPI=y +CONFIG_START_DAY=5 +CONFIG_START_MONTH=5 +CONFIG_START_YEAR=2014 +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PWR=y +CONFIG_STM32_TIM3=y +CONFIG_STM32_TIM3_CH1OUT=y +CONFIG_STM32_TIM3_PWM=y +CONFIG_STM32_USART6=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USBDEV=y diff --git a/boards/arm/stm32f4/stm32f401rc-rs485/configs/hcsr04/defconfig b/boards/arm/stm32f4/stm32f401rc-rs485/configs/hcsr04/defconfig new file mode 100644 index 0000000000000..20321b364cd5f --- /dev/null +++ b/boards/arm/stm32f4/stm32f401rc-rs485/configs/hcsr04/defconfig @@ -0,0 +1,67 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f401rc-rs485" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_STM32F401RC_RS485=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F401RC=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQBUTTONS=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL_USBDEVCTRL=y +CONFIG_BOARD_LOOPSPERMSEC=8499 +CONFIG_BUILTIN=y +CONFIG_CDCACM=y +CONFIG_CDCACM_CONSOLE=y +CONFIG_EXAMPLES_BUTTONS=y +CONFIG_EXAMPLES_BUTTONS_NAME0="SW3" +CONFIG_EXAMPLES_BUTTONS_NAME1="SW4" +CONFIG_EXAMPLES_BUTTONS_NAME2="SW5" +CONFIG_EXAMPLES_BUTTONS_NAMES=y +CONFIG_EXAMPLES_BUTTONS_QTD=3 +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INPUT=y +CONFIG_INPUT_BUTTONS=y +CONFIG_INPUT_BUTTONS_LOWER=y +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=98304 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_SENSORS=y +CONFIG_SENSORS_HCSR04=y +CONFIG_SPI=y +CONFIG_START_DAY=5 +CONFIG_START_MONTH=5 +CONFIG_START_YEAR=2014 +CONFIG_STM32_FREERUN=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PWR=y +CONFIG_STM32_TIM1=y +CONFIG_STM32_USART6=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USBDEV=y diff --git a/boards/arm/stm32f4/stm32f401rc-rs485/configs/lcd1602/defconfig b/boards/arm/stm32f4/stm32f401rc-rs485/configs/lcd1602/defconfig new file mode 100644 index 0000000000000..9e5dd06e38d92 --- /dev/null +++ b/boards/arm/stm32f4/stm32f401rc-rs485/configs/lcd1602/defconfig @@ -0,0 +1,68 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f401rc-rs485" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_STM32F401RC_RS485=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F401RC=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQBUTTONS=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL_USBDEVCTRL=y +CONFIG_BOARD_LOOPSPERMSEC=8499 +CONFIG_BUILTIN=y +CONFIG_CDCACM=y +CONFIG_CDCACM_CONSOLE=y +CONFIG_EXAMPLES_BUTTONS=y +CONFIG_EXAMPLES_BUTTONS_NAME0="SW3" +CONFIG_EXAMPLES_BUTTONS_NAME1="SW4" +CONFIG_EXAMPLES_BUTTONS_NAME2="SW5" +CONFIG_EXAMPLES_BUTTONS_NAMES=y +CONFIG_EXAMPLES_BUTTONS_QTD=3 +CONFIG_EXAMPLES_SLCD=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_I2C=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INPUT=y +CONFIG_INPUT_BUTTONS=y +CONFIG_INPUT_BUTTONS_LOWER=y +CONFIG_INTELHEX_BINARY=y +CONFIG_LCD_BACKPACK=y +CONFIG_LINE_MAX=64 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=98304 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_SLCD=y +CONFIG_SPI=y +CONFIG_START_DAY=5 +CONFIG_START_MONTH=5 +CONFIG_START_YEAR=2014 +CONFIG_STM32_I2C1=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PWR=y +CONFIG_STM32_USART6=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USBDEV=y diff --git a/boards/arm/stm32f4/stm32f401rc-rs485/configs/lm75/defconfig b/boards/arm/stm32f4/stm32f401rc-rs485/configs/lm75/defconfig new file mode 100644 index 0000000000000..ab31f55aabe59 --- /dev/null +++ b/boards/arm/stm32f4/stm32f401rc-rs485/configs/lm75/defconfig @@ -0,0 +1,73 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f401rc-rs485" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_STM32F401RC_RS485=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F401RC=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQBUTTONS=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL_USBDEVCTRL=y +CONFIG_BOARD_LOOPSPERMSEC=8499 +CONFIG_BUILTIN=y +CONFIG_CDCACM=y +CONFIG_CDCACM_CONSOLE=y +CONFIG_EXAMPLES_BUTTONS=y +CONFIG_EXAMPLES_BUTTONS_NAME0="SW3" +CONFIG_EXAMPLES_BUTTONS_NAME1="SW4" +CONFIG_EXAMPLES_BUTTONS_NAME2="SW5" +CONFIG_EXAMPLES_BUTTONS_NAMES=y +CONFIG_EXAMPLES_BUTTONS_QTD=3 +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_I2CTOOL_MAXBUS=1 +CONFIG_I2CTOOL_MINBUS=1 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INPUT=y +CONFIG_INPUT_BUTTONS=y +CONFIG_INPUT_BUTTONS_LOWER=y +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_FLOATINGPOINT=y +CONFIG_LINE_MAX=64 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=98304 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_SENSORS=y +CONFIG_SENSORS_LM75=y +CONFIG_SPI=y +CONFIG_START_DAY=5 +CONFIG_START_MONTH=5 +CONFIG_START_YEAR=2014 +CONFIG_STM32_I2C1=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PWR=y +CONFIG_STM32_USART6=y +CONFIG_SYSTEM_I2CTOOL=y +CONFIG_SYSTEM_LM75=y +CONFIG_SYSTEM_LM75_CELSIUS=y +CONFIG_SYSTEM_LM75_DEVNAME="/dev/temp0" +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USBDEV=y diff --git a/boards/arm/stm32f4/stm32f401rc-rs485/configs/max7219/defconfig b/boards/arm/stm32f4/stm32f401rc-rs485/configs/max7219/defconfig new file mode 100644 index 0000000000000..71205dd34696a --- /dev/null +++ b/boards/arm/stm32f4/stm32f401rc-rs485/configs/max7219/defconfig @@ -0,0 +1,74 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_NX_DISABLE_1BPP is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f401rc-rs485" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_STM32F401RC_RS485=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F401RC=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQBUTTONS=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL_USBDEVCTRL=y +CONFIG_BOARD_LOOPSPERMSEC=8499 +CONFIG_BUILTIN=y +CONFIG_CDCACM=y +CONFIG_CDCACM_CONSOLE=y +CONFIG_EXAMPLES_BUTTONS=y +CONFIG_EXAMPLES_BUTTONS_NAME0="SW3" +CONFIG_EXAMPLES_BUTTONS_NAME1="SW4" +CONFIG_EXAMPLES_BUTTONS_NAME2="SW5" +CONFIG_EXAMPLES_BUTTONS_NAMES=y +CONFIG_EXAMPLES_BUTTONS_QTD=3 +CONFIG_EXAMPLES_NXHELLO=y +CONFIG_EXAMPLES_NXHELLO_BPP=1 +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INPUT=y +CONFIG_INPUT_BUTTONS=y +CONFIG_INPUT_BUTTONS_LOWER=y +CONFIG_INTELHEX_BINARY=y +CONFIG_LCD=y +CONFIG_LCD_FRAMEBUFFER=y +CONFIG_LCD_MAX7219=y +CONFIG_LCD_NOGETRUN=y +CONFIG_LINE_MAX=64 +CONFIG_MQ_MAXMSGSIZE=64 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_NX=y +CONFIG_NXFONT_MONO5X8=y +CONFIG_NX_BLOCKING=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=98304 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=5 +CONFIG_START_MONTH=5 +CONFIG_START_YEAR=2014 +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PWR=y +CONFIG_STM32_SPI1=y +CONFIG_STM32_USART6=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USBDEV=y diff --git a/boards/arm/stm32f4/stm32f401rc-rs485/configs/mfrc522/defconfig b/boards/arm/stm32f4/stm32f401rc-rs485/configs/mfrc522/defconfig new file mode 100644 index 0000000000000..bd6c560ffa67a --- /dev/null +++ b/boards/arm/stm32f4/stm32f401rc-rs485/configs/mfrc522/defconfig @@ -0,0 +1,66 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f401rc-rs485" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_STM32F401RC_RS485=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F401RC=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQBUTTONS=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL_USBDEVCTRL=y +CONFIG_BOARD_LOOPSPERMSEC=8499 +CONFIG_BUILTIN=y +CONFIG_CDCACM=y +CONFIG_CDCACM_CONSOLE=y +CONFIG_CL_MFRC522=y +CONFIG_DRIVERS_CONTACTLESS=y +CONFIG_EXAMPLES_BUTTONS=y +CONFIG_EXAMPLES_BUTTONS_NAME0="SW3" +CONFIG_EXAMPLES_BUTTONS_NAME1="SW4" +CONFIG_EXAMPLES_BUTTONS_NAME2="SW5" +CONFIG_EXAMPLES_BUTTONS_NAMES=y +CONFIG_EXAMPLES_BUTTONS_QTD=3 +CONFIG_EXAMPLES_RFID_READUID=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INPUT=y +CONFIG_INPUT_BUTTONS=y +CONFIG_INPUT_BUTTONS_LOWER=y +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=98304 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=5 +CONFIG_START_MONTH=5 +CONFIG_START_YEAR=2014 +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PWR=y +CONFIG_STM32_SPI1=y +CONFIG_STM32_USART6=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USBDEV=y diff --git a/boards/arm/stm32f4/stm32f401rc-rs485/configs/modbus_master/defconfig b/boards/arm/stm32f4/stm32f401rc-rs485/configs/modbus_master/defconfig new file mode 100644 index 0000000000000..09aa15441b04a --- /dev/null +++ b/boards/arm/stm32f4/stm32f401rc-rs485/configs/modbus_master/defconfig @@ -0,0 +1,77 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_MB_MASTER_FUNC_READWRITE_HOLDING_ENABLED is not set +# CONFIG_MB_MASTER_FUNC_READ_COILS_ENABLED is not set +# CONFIG_MB_MASTER_FUNC_READ_DISCRETE_INPUTS_ENABLED is not set +# CONFIG_MB_MASTER_FUNC_READ_INPUT_ENABLED is not set +# CONFIG_MB_MASTER_FUNC_WRITE_COIL_ENABLED is not set +# CONFIG_MB_MASTER_FUNC_WRITE_HOLDING_ENABLED is not set +# CONFIG_MB_MASTER_FUNC_WRITE_MULTIPLE_COILS_ENABLED is not set +# CONFIG_MB_MASTER_FUNC_WRITE_MULTIPLE_HOLDING_ENABLED is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f401rc-rs485" +CONFIG_ARCH_BOARD_STM32F401RC_RS485=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F401RC=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQBUTTONS=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=8499 +CONFIG_BUILTIN=y +CONFIG_EXAMPLES_BUTTONS=y +CONFIG_EXAMPLES_BUTTONS_NAME0="SW3" +CONFIG_EXAMPLES_BUTTONS_NAME1="SW4" +CONFIG_EXAMPLES_BUTTONS_NAME2="SW5" +CONFIG_EXAMPLES_BUTTONS_NAME3="SW6" +CONFIG_EXAMPLES_BUTTONS_NAMES=y +CONFIG_EXAMPLES_BUTTONS_QTD=4 +CONFIG_EXAMPLES_MODBUSMASTER=y +CONFIG_EXAMPLES_MODBUSMASTER_SLAVEADDR=10 +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INDUSTRY_MODBUS=y +CONFIG_INDUSTRY_MODBUS_MASTER=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INPUT=y +CONFIG_INPUT_BUTTONS=y +CONFIG_INPUT_BUTTONS_LOWER=y +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_MB_RTU_MASTER=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=98304 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_SPI=y +CONFIG_START_DAY=5 +CONFIG_START_MONTH=5 +CONFIG_START_YEAR=2014 +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PWR=y +CONFIG_STM32_USART2=y +CONFIG_STM32_USART6=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART2_BAUD=38400 +CONFIG_USART2_PARITY=2 +CONFIG_USART2_RS485=y +CONFIG_USART6_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f4/stm32f401rc-rs485/configs/modbus_slave/defconfig b/boards/arm/stm32f4/stm32f401rc-rs485/configs/modbus_slave/defconfig new file mode 100644 index 0000000000000..54650ba01e5ed --- /dev/null +++ b/boards/arm/stm32f4/stm32f401rc-rs485/configs/modbus_slave/defconfig @@ -0,0 +1,70 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_MB_ASCII_ENABLED is not set +# CONFIG_MB_TCP_ENABLED is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f401rc-rs485" +CONFIG_ARCH_BOARD_STM32F401RC_RS485=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F401RC=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQBUTTONS=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=8499 +CONFIG_BUILTIN=y +CONFIG_EXAMPLES_BUTTONS=y +CONFIG_EXAMPLES_BUTTONS_NAME0="SW3" +CONFIG_EXAMPLES_BUTTONS_NAME1="SW4" +CONFIG_EXAMPLES_BUTTONS_NAME2="SW5" +CONFIG_EXAMPLES_BUTTONS_NAME3="SW6" +CONFIG_EXAMPLES_BUTTONS_NAMES=y +CONFIG_EXAMPLES_BUTTONS_QTD=4 +CONFIG_EXAMPLES_MODBUS=y +CONFIG_EXAMPLES_MODBUS_PORT=1 +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INDUSTRY_MODBUS=y +CONFIG_INDUSTRY_MODBUS_SLAVE=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INPUT=y +CONFIG_INPUT_BUTTONS=y +CONFIG_INPUT_BUTTONS_LOWER=y +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=98304 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_SPI=y +CONFIG_START_DAY=5 +CONFIG_START_MONTH=5 +CONFIG_START_YEAR=2014 +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PWR=y +CONFIG_STM32_USART2=y +CONFIG_STM32_USART6=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART2_BAUD=38400 +CONFIG_USART2_PARITY=2 +CONFIG_USART2_RS485=y +CONFIG_USART6_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f4/stm32f401rc-rs485/configs/nsh/defconfig b/boards/arm/stm32f4/stm32f401rc-rs485/configs/nsh/defconfig new file mode 100644 index 0000000000000..6579a60a22385 --- /dev/null +++ b/boards/arm/stm32f4/stm32f401rc-rs485/configs/nsh/defconfig @@ -0,0 +1,59 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f401rc-rs485" +CONFIG_ARCH_BOARD_STM32F401RC_RS485=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F401RC=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQBUTTONS=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=8499 +CONFIG_BUILTIN=y +CONFIG_EXAMPLES_BUTTONS=y +CONFIG_EXAMPLES_BUTTONS_NAME0="SW3" +CONFIG_EXAMPLES_BUTTONS_NAME1="SW4" +CONFIG_EXAMPLES_BUTTONS_NAME2="SW5" +CONFIG_EXAMPLES_BUTTONS_NAMES=y +CONFIG_EXAMPLES_BUTTONS_QTD=3 +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INPUT=y +CONFIG_INPUT_BUTTONS=y +CONFIG_INPUT_BUTTONS_LOWER=y +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=98304 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_SPI=y +CONFIG_START_DAY=5 +CONFIG_START_MONTH=5 +CONFIG_START_YEAR=2014 +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PWR=y +CONFIG_STM32_USART6=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART6_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f4/stm32f401rc-rs485/configs/qencoder/defconfig b/boards/arm/stm32f4/stm32f401rc-rs485/configs/qencoder/defconfig new file mode 100644 index 0000000000000..6e145c65d59b9 --- /dev/null +++ b/boards/arm/stm32f4/stm32f401rc-rs485/configs/qencoder/defconfig @@ -0,0 +1,68 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f401rc-rs485" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_STM32F401RC_RS485=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F401RC=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQBUTTONS=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL_USBDEVCTRL=y +CONFIG_BOARD_LOOPSPERMSEC=8499 +CONFIG_BUILTIN=y +CONFIG_CDCACM=y +CONFIG_CDCACM_CONSOLE=y +CONFIG_EXAMPLES_BUTTONS=y +CONFIG_EXAMPLES_BUTTONS_NAME0="SW3" +CONFIG_EXAMPLES_BUTTONS_NAME1="SW4" +CONFIG_EXAMPLES_BUTTONS_NAME2="SW5" +CONFIG_EXAMPLES_BUTTONS_NAMES=y +CONFIG_EXAMPLES_BUTTONS_QTD=3 +CONFIG_EXAMPLES_QENCODER=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INPUT=y +CONFIG_INPUT_BUTTONS=y +CONFIG_INPUT_BUTTONS_LOWER=y +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=98304 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_SENSORS=y +CONFIG_SENSORS_QENCODER=y +CONFIG_SPI=y +CONFIG_START_DAY=5 +CONFIG_START_MONTH=5 +CONFIG_START_YEAR=2014 +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PWR=y +CONFIG_STM32_TIM3=y +CONFIG_STM32_TIM3_QE=y +CONFIG_STM32_USART6=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USBDEV=y diff --git a/boards/arm/stm32f4/stm32f401rc-rs485/configs/rndis/defconfig b/boards/arm/stm32f4/stm32f401rc-rs485/configs/rndis/defconfig new file mode 100644 index 0000000000000..be5813d65a637 --- /dev/null +++ b/boards/arm/stm32f4/stm32f401rc-rs485/configs/rndis/defconfig @@ -0,0 +1,87 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f401rc-rs485" +CONFIG_ARCH_BOARD_STM32F401RC_RS485=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F401RC=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQBUTTONS=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL_USBDEVCTRL=y +CONFIG_BOARD_LOOPSPERMSEC=8499 +CONFIG_BUILTIN=y +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_EXAMPLES_BUTTONS=y +CONFIG_EXAMPLES_BUTTONS_NAME0="SW3" +CONFIG_EXAMPLES_BUTTONS_NAME1="SW4" +CONFIG_EXAMPLES_BUTTONS_NAME2="SW5" +CONFIG_EXAMPLES_BUTTONS_NAMES=y +CONFIG_EXAMPLES_BUTTONS_QTD=3 +CONFIG_FS_PROCFS=y +CONFIG_FS_TMPFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INPUT=y +CONFIG_INPUT_BUTTONS=y +CONFIG_INPUT_BUTTONS_LOWER=y +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_MEMFD_ERROR=y +CONFIG_LINE_MAX=64 +CONFIG_NET=y +CONFIG_NETDB_DNSCLIENT=y +CONFIG_NETDB_DNSSERVER_IPv4ADDR=0x0 +CONFIG_NETDEV_LATEINIT=y +CONFIG_NETINIT_DHCPC=y +CONFIG_NETINIT_DRIPADDR=0x0 +CONFIG_NETINIT_NETMASK=0x0 +CONFIG_NETINIT_NOMAC=y +CONFIG_NETINIT_THREAD=y +CONFIG_NETUTILS_DHCPC=y +CONFIG_NETUTILS_TELNETD=y +CONFIG_NETUTILS_WEBCLIENT=y +CONFIG_NET_BROADCAST=y +CONFIG_NET_ICMP_SOCKET=y +CONFIG_NET_LOOPBACK=y +CONFIG_NET_STATISTICS=y +CONFIG_NET_TCP=y +CONFIG_NET_TCP_WRITE_BUFFERS=y +CONFIG_NET_UDP=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_DISABLE_IFUPDOWN=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=98304 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RNDIS=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_LPWORK=y +CONFIG_SCHED_WAITPID=y +CONFIG_SPI=y +CONFIG_START_DAY=5 +CONFIG_START_MONTH=5 +CONFIG_START_YEAR=2014 +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PWR=y +CONFIG_STM32_USART6=y +CONFIG_SYSTEM_NSH=y +CONFIG_SYSTEM_PING=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART6_SERIAL_CONSOLE=y +CONFIG_USBDEV=y diff --git a/boards/arm/stm32f4/stm32f401rc-rs485/configs/sdcard/defconfig b/boards/arm/stm32f4/stm32f401rc-rs485/configs/sdcard/defconfig new file mode 100644 index 0000000000000..cd419b48e967e --- /dev/null +++ b/boards/arm/stm32f4/stm32f401rc-rs485/configs/sdcard/defconfig @@ -0,0 +1,70 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_MMCSD_HAVE_WRITEPROTECT is not set +# CONFIG_MMCSD_SPI is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f401rc-rs485" +CONFIG_ARCH_BOARD_STM32F401RC_RS485=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F401RC=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQBUTTONS=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=8499 +CONFIG_BUILTIN=y +CONFIG_EXAMPLES_BUTTONS=y +CONFIG_EXAMPLES_BUTTONS_NAME0="SW3" +CONFIG_EXAMPLES_BUTTONS_NAME1="SW4" +CONFIG_EXAMPLES_BUTTONS_NAME2="SW5" +CONFIG_EXAMPLES_BUTTONS_NAME3="SW6" +CONFIG_EXAMPLES_BUTTONS_NAMES=y +CONFIG_EXAMPLES_BUTTONS_QTD=4 +CONFIG_FAT_LCNAMES=y +CONFIG_FAT_LFN=y +CONFIG_FS_FAT=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INPUT=y +CONFIG_INPUT_BUTTONS=y +CONFIG_INPUT_BUTTONS_LOWER=y +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_MMCSD=y +CONFIG_MMCSD_SDIO=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_DISABLE_IFUPDOWN=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=98304 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_WAITPID=y +CONFIG_SPI=y +CONFIG_START_DAY=5 +CONFIG_START_MONTH=5 +CONFIG_START_YEAR=2014 +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PWR=y +CONFIG_STM32_SDIO=y +CONFIG_STM32_SDIO_CARD=y +CONFIG_STM32_USART6=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART6_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f4/stm32f401rc-rs485/configs/ssd1309/defconfig b/boards/arm/stm32f4/stm32f401rc-rs485/configs/ssd1309/defconfig new file mode 100644 index 0000000000000..d9828a3ad379c --- /dev/null +++ b/boards/arm/stm32f4/stm32f401rc-rs485/configs/ssd1309/defconfig @@ -0,0 +1,70 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f401rc-rs485" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_STM32F401RC_RS485=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F401RC=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQBUTTONS=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL_USBDEVCTRL=y +CONFIG_BOARD_LOOPSPERMSEC=8499 +CONFIG_BUILTIN=y +CONFIG_CDCACM=y +CONFIG_CDCACM_CONSOLE=y +CONFIG_DRIVERS_VIDEO=y +CONFIG_EXAMPLES_BUTTONS=y +CONFIG_EXAMPLES_BUTTONS_NAME0="SW3" +CONFIG_EXAMPLES_BUTTONS_NAME1="SW4" +CONFIG_EXAMPLES_BUTTONS_NAME2="SW5" +CONFIG_EXAMPLES_BUTTONS_NAMES=y +CONFIG_EXAMPLES_BUTTONS_QTD=3 +CONFIG_EXAMPLES_FB=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INPUT=y +CONFIG_INPUT_BUTTONS=y +CONFIG_INPUT_BUTTONS_LOWER=y +CONFIG_INTELHEX_BINARY=y +CONFIG_LCD=y +CONFIG_LCD_DD12864WO4A=y +CONFIG_LCD_FRAMEBUFFER=y +CONFIG_LCD_NOGETRUN=y +CONFIG_LINE_MAX=64 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_DISABLE_IFUPDOWN=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=98304 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=5 +CONFIG_START_MONTH=5 +CONFIG_START_YEAR=2014 +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PWR=y +CONFIG_STM32_SPI1=y +CONFIG_STM32_USART6=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USBDEV=y +CONFIG_VIDEO_FB=y diff --git a/boards/arm/stm32f4/stm32f401rc-rs485/configs/telnetd/defconfig b/boards/arm/stm32f4/stm32f401rc-rs485/configs/telnetd/defconfig new file mode 100644 index 0000000000000..b29a0ff745914 --- /dev/null +++ b/boards/arm/stm32f4/stm32f401rc-rs485/configs/telnetd/defconfig @@ -0,0 +1,93 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_SYSTEM_TELNETD is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f401rc-rs485" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_STM32F401RC_RS485=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F401RC=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQBUTTONS=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL_RESET=y +CONFIG_BOARDCTL_USBDEVCTRL=y +CONFIG_BOARD_LOOPSPERMSEC=8499 +CONFIG_BUILTIN=y +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_EXAMPLES_BUTTONS=y +CONFIG_EXAMPLES_BUTTONS_NAME0="SW3" +CONFIG_EXAMPLES_BUTTONS_NAME1="SW4" +CONFIG_EXAMPLES_BUTTONS_NAME2="SW5" +CONFIG_EXAMPLES_BUTTONS_NAMES=y +CONFIG_EXAMPLES_BUTTONS_QTD=3 +CONFIG_EXAMPLES_TELNETD=y +CONFIG_EXAMPLES_TELNETD_DRIPADDR=0xC0A80101 +CONFIG_EXAMPLES_TELNETD_IPADDR=0xC0A80102 +CONFIG_FS_PROCFS=y +CONFIG_FS_TMPFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INPUT=y +CONFIG_INPUT_BUTTONS=y +CONFIG_INPUT_BUTTONS_LOWER=y +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_MEMFD_ERROR=y +CONFIG_LINE_MAX=64 +CONFIG_NET=y +CONFIG_NETDB_DNSCLIENT=y +CONFIG_NETDB_DNSSERVER_IPv4ADDR=0x0 +CONFIG_NETDEV_LATEINIT=y +CONFIG_NETINIT_DRIPADDR=0xC0A80101 +CONFIG_NETINIT_IPADDR=0xC0A80102 +CONFIG_NETINIT_NETMASK=0xFFFFFF00 +CONFIG_NETINIT_NOMAC=y +CONFIG_NETINIT_THREAD=y +CONFIG_NETUTILS_DHCPC=y +CONFIG_NETUTILS_TELNETD=y +CONFIG_NETUTILS_WEBCLIENT=y +CONFIG_NET_BROADCAST=y +CONFIG_NET_ICMP_SOCKET=y +CONFIG_NET_LOOPBACK=y +CONFIG_NET_STATISTICS=y +CONFIG_NET_TCP=y +CONFIG_NET_TCP_WRITE_BUFFERS=y +CONFIG_NET_UDP=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_DISABLE_IFUPDOWN=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=98304 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RNDIS=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_LPWORK=y +CONFIG_SCHED_WAITPID=y +CONFIG_SPI=y +CONFIG_START_DAY=5 +CONFIG_START_MONTH=5 +CONFIG_START_YEAR=2014 +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PWR=y +CONFIG_STM32_USART6=y +CONFIG_SYSTEM_NSH=y +CONFIG_SYSTEM_PING=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART6_SERIAL_CONSOLE=y +CONFIG_USBDEV=y diff --git a/boards/arm/stm32f4/stm32f401rc-rs485/configs/usbmsc/defconfig b/boards/arm/stm32f4/stm32f401rc-rs485/configs/usbmsc/defconfig new file mode 100644 index 0000000000000..95f8b90b02a9e --- /dev/null +++ b/boards/arm/stm32f4/stm32f401rc-rs485/configs/usbmsc/defconfig @@ -0,0 +1,75 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_MMCSD_HAVE_WRITEPROTECT is not set +# CONFIG_MMCSD_SPI is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f401rc-rs485" +CONFIG_ARCH_BOARD_STM32F401RC_RS485=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F401RC=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQBUTTONS=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=8499 +CONFIG_BUILTIN=y +CONFIG_EXAMPLES_BUTTONS=y +CONFIG_EXAMPLES_BUTTONS_NAME0="SW3" +CONFIG_EXAMPLES_BUTTONS_NAME1="SW4" +CONFIG_EXAMPLES_BUTTONS_NAME2="SW5" +CONFIG_EXAMPLES_BUTTONS_NAME3="SW6" +CONFIG_EXAMPLES_BUTTONS_NAMES=y +CONFIG_EXAMPLES_BUTTONS_QTD=4 +CONFIG_FAT_LCNAMES=y +CONFIG_FAT_LFN=y +CONFIG_FS_FAT=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INPUT=y +CONFIG_INPUT_BUTTONS=y +CONFIG_INPUT_BUTTONS_LOWER=y +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_MMCSD=y +CONFIG_MMCSD_SDIO=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_DISABLE_IFUPDOWN=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=98304 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_WAITPID=y +CONFIG_SPI=y +CONFIG_START_DAY=5 +CONFIG_START_MONTH=5 +CONFIG_START_YEAR=2014 +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PWR=y +CONFIG_STM32_SDIO=y +CONFIG_STM32_SDIO_CARD=y +CONFIG_STM32_USART6=y +CONFIG_SYSTEM_NSH=y +CONFIG_SYSTEM_USBMSC=y +CONFIG_SYSTEM_USBMSC_DEVMINOR1=0 +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART6_SERIAL_CONSOLE=y +CONFIG_USBDEV=y +CONFIG_USBMSC=y +CONFIG_USBMSC_REMOVABLE=y diff --git a/boards/arm/stm32f4/stm32f401rc-rs485/configs/usbnsh/defconfig b/boards/arm/stm32f4/stm32f401rc-rs485/configs/usbnsh/defconfig new file mode 100644 index 0000000000000..594ab62510eef --- /dev/null +++ b/boards/arm/stm32f4/stm32f401rc-rs485/configs/usbnsh/defconfig @@ -0,0 +1,62 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f401rc-rs485" +CONFIG_ARCH_BOARD_STM32F401RC_RS485=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F401RC=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQBUTTONS=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL_USBDEVCTRL=y +CONFIG_BOARD_LOOPSPERMSEC=8499 +CONFIG_BUILTIN=y +CONFIG_CDCACM=y +CONFIG_CDCACM_CONSOLE=y +CONFIG_EXAMPLES_BUTTONS=y +CONFIG_EXAMPLES_BUTTONS_NAME0="SW3" +CONFIG_EXAMPLES_BUTTONS_NAME1="SW4" +CONFIG_EXAMPLES_BUTTONS_NAME2="SW5" +CONFIG_EXAMPLES_BUTTONS_NAMES=y +CONFIG_EXAMPLES_BUTTONS_QTD=3 +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INPUT=y +CONFIG_INPUT_BUTTONS=y +CONFIG_INPUT_BUTTONS_LOWER=y +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=98304 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_SPI=y +CONFIG_START_DAY=5 +CONFIG_START_MONTH=5 +CONFIG_START_YEAR=2014 +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PWR=y +CONFIG_STM32_USART6=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USBDEV=y diff --git a/boards/arm/stm32f4/stm32f401rc-rs485/configs/ws2812/defconfig b/boards/arm/stm32f4/stm32f401rc-rs485/configs/ws2812/defconfig new file mode 100644 index 0000000000000..260bbbe3bf96f --- /dev/null +++ b/boards/arm/stm32f4/stm32f401rc-rs485/configs/ws2812/defconfig @@ -0,0 +1,68 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f401rc-rs485" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_STM32F401RC_RS485=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F401RC=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQBUTTONS=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL_USBDEVCTRL=y +CONFIG_BOARD_LOOPSPERMSEC=8499 +CONFIG_BUILTIN=y +CONFIG_CDCACM=y +CONFIG_CDCACM_CONSOLE=y +CONFIG_EXAMPLES_BUTTONS=y +CONFIG_EXAMPLES_BUTTONS_NAME0="SW3" +CONFIG_EXAMPLES_BUTTONS_NAME1="SW4" +CONFIG_EXAMPLES_BUTTONS_NAME2="SW5" +CONFIG_EXAMPLES_BUTTONS_NAMES=y +CONFIG_EXAMPLES_BUTTONS_QTD=3 +CONFIG_EXAMPLES_WS2812=y +CONFIG_EXAMPLES_WS2812_DEFAULT_DEV="/dev/leddrv0" +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INPUT=y +CONFIG_INPUT_BUTTONS=y +CONFIG_INPUT_BUTTONS_LOWER=y +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=98304 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=5 +CONFIG_START_MONTH=5 +CONFIG_START_YEAR=2014 +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PWR=y +CONFIG_STM32_SPI1=y +CONFIG_STM32_USART6=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USBDEV=y +CONFIG_WS2812=y +CONFIG_WS2812_FREQUENCY=9000000 +CONFIG_WS2812_LED_COUNT=10 diff --git a/boards/arm/stm32f4/stm32f401rc-rs485/include/board.h b/boards/arm/stm32f4/stm32f401rc-rs485/include/board.h new file mode 100644 index 0000000000000..4225ee4db7475 --- /dev/null +++ b/boards/arm/stm32f4/stm32f401rc-rs485/include/board.h @@ -0,0 +1,470 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f401rc-rs485/include/board.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_STM32F401RC_RS485_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32F401RC_RS485_INCLUDE_BOARD_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#ifndef __ASSEMBLY__ +# include +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Clocking *****************************************************************/ + +/* The STM32F401RC-RS485 uses an external 32kHz crystal (X2) to enable HSE + * clock. + * + * System Clock source : PLL (HSI) + * SYSCLK(Hz) : 84000000 Determined by PLL + * configuration + * HCLK(Hz) : 84000000 (STM32_RCC_CFGR_HPRE) + * AHB Prescaler : 1 (STM32_RCC_CFGR_HPRE) + * APB1 Prescaler : 2 (STM32_RCC_CFGR_PPRE1) + * APB2 Prescaler : 1 (STM32_RCC_CFGR_PPRE2) + * HSI Frequency(Hz) : 16000000 (nominal) + * PLLM : 16 (STM32_PLLCFG_PLLM) + * PLLN : 336 (STM32_PLLCFG_PLLN) + * PLLP : 4 (STM32_PLLCFG_PLLP) + * PLLQ : 7 (STM32_PLLCFG_PPQ) + * Flash Latency(WS) : 5 + * Prefetch Buffer : OFF + * Instruction cache : ON + * Data cache : ON + * Require 48MHz for USB OTG FS, : Enabled + * SDIO and RNG clock + */ + +/* HSI - 16 MHz RC factory-trimmed + * LSI - 32 KHz RC + * HSE - not installed + * LSE - not installed + */ + +#define STM32_HSI_FREQUENCY 16000000ul +#define STM32_LSI_FREQUENCY 32000 +#define STM32_BOARD_USEHSI 1 + +/* Main PLL Configuration. + * + * Formulae: + * + * VCO input frequency = PLL input clock frequency / PLLM, + * 2 <= PLLM <= 63 + * VCO output frequency = VCO input frequency × PLLN, + * 192 <= PLLN <= 432 + * PLL output clock frequency = VCO frequency / PLLP, + * PLLP = 2, 4, 6, or 8 + * USB OTG FS clock frequency = VCO frequency / PLLQ, + * 2 <= PLLQ <= 15 + * + * We would like to have SYSYCLK=84MHz and we must have the USB clock= 48MHz. + * Some possible solutions include: + * + * PLLN=210 PLLM=5 PLLP=8 PLLQ=14 SYSCLK=84000000 OTGFS=48000000 + * PLLN=210 PLLM=10 PLLP=4 PLLQ=7 SYSCLK=84000000 OTGFS=48000000 + * PLLN=336 PLLM=8 PLLP=8 PLLQ=14 SYSCLK=84000000 OTGFS=48000000 + * PLLN=336 PLLM=16 PLLP=4 PLLQ=7 SYSCLK=84000000 OTGFS=48000000 + * PLLN=420 PLLM=10 PLLP=8 PLLQ=14 SYSCLK=84000000 OTGFS=48000000 + * PLLN=420 PLLM=20 PLLP=4 PLLQ=7 SYSCLK=84000000 OTGFS=48000000 + * + * We will configure like this + * + * PLL source is HSI + * PLL_VCO = (STM32_HSI_FREQUENCY / PLLM) * PLLN + * = (16,000,000 / 16) * 336 + * = 336,000,000 + * SYSCLK = PLL_VCO / PLLP + * = 336,000,000 / 4 = 84,000,000 + * USB OTG FS and SDIO Clock + * = PLL_VCO / PLLQ + * = 336,000,000 / 7 = 48,000,000 + * + * REVISIT: Trimming of the HSI is not yet supported. + */ + +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(16) +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(336) +#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_4 +#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(7) + +#define STM32_SYSCLK_FREQUENCY 84000000ul + +/* AHB clock (HCLK) is SYSCLK (84MHz) */ + +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY + +/* APB1 clock (PCLK1) is HCLK/2 (42MHz) */ + +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd2 /* PCLK1 = HCLK / 2 */ +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/2) + +/* Timers driven from APB1 will be twice PCLK1 */ + +/* REVISIT */ + +#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) + +/* APB2 clock (PCLK2) is HCLK (84MHz) */ + +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ +#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/1) + +/* Timers driven from APB2 will be twice PCLK2 */ + +/* REVISIT */ + +#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM9_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB2_TIM10_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB2_TIM11_CLKIN (2*STM32_PCLK1_FREQUENCY) + +/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx + * otherwise frequency is 2xAPBx. + * Note: TIM1,8 are on APB2, others on APB1 + */ + +/* REVISIT */ + +#define BOARD_TIM1_FREQUENCY (2*STM32_PCLK2_FREQUENCY) +#define BOARD_TIM2_FREQUENCY (2*STM32_PCLK1_FREQUENCY) +#define BOARD_TIM3_FREQUENCY (2*STM32_PCLK1_FREQUENCY) +#define BOARD_TIM4_FREQUENCY (2*STM32_PCLK1_FREQUENCY) +#define BOARD_TIM5_FREQUENCY (2*STM32_PCLK1_FREQUENCY) +#define BOARD_TIM6_FREQUENCY (2*STM32_PCLK1_FREQUENCY) +#define BOARD_TIM7_FREQUENCY (2*STM32_PCLK1_FREQUENCY) +#define BOARD_TIM8_FREQUENCY (2*STM32_PCLK2_FREQUENCY) + +/* SDIO dividers. Note that slower clocking is required when DMA is disabled + * in order to avoid RX overrun/TX underrun errors due to delayed responses + * to service FIFOs in interrupt driven mode. These values have not been + * tuned!!! + * + * HCLK=72MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(178+2)=400 KHz + */ + +/* REVISIT */ + +#define SDIO_INIT_CLKDIV (178 << SDIO_CLKCR_CLKDIV_SHIFT) + +/* DMA ON: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(2+2)=18 MHz + * DMA OFF: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(3+2)=14.4 MHz + */ + +/* REVISIT */ + +#ifdef CONFIG_SDIO_DMA +# define SDIO_MMCXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT) +#else +# define SDIO_MMCXFR_CLKDIV (3 << SDIO_CLKCR_CLKDIV_SHIFT) +#endif + +/* DMA ON: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(1+2)=24 MHz + * DMA OFF: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(3+2)=14.4 MHz + */ + +/* REVISIT */ + +#ifdef CONFIG_SDIO_DMA +# define SDIO_SDXFR_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT) +#else +# define SDIO_SDXFR_CLKDIV (3 << SDIO_CLKCR_CLKDIV_SHIFT) +#endif + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* DMA Channel/Stream Selections ********************************************/ + +/* Stream selections are arbitrary for now but might become important in + * the future is we set aside more DMA channels/streams. + * + * SDIO DMA + *   DMAMAP_SDIO_1 = Channel 4, Stream 3 <- may later be used by SPI DMA + *   DMAMAP_SDIO_2 = Channel 4, Stream 6 + */ + +#define DMAMAP_SDIO DMAMAP_SDIO_1 + +/* Need to VERIFY fwb */ + +#define DMACHAN_SPI1_RX DMAMAP_SPI1_RX_1 +#define DMACHAN_SPI1_TX DMAMAP_SPI1_TX_1 +#define DMACHAN_SPI2_RX DMAMAP_SPI2_RX +#define DMACHAN_SPI2_TX DMAMAP_SPI2_TX + +/* Alternate function pin selections ****************************************/ + +/* USART2: + * RXD: PA3 CN4 pin 20 + * TXD: PA2 CN4 pin 18 + */ + +#ifdef CONFIG_USART2_RS485 + /* Lets use for RS485 */ + +# define GPIO_USART2_TX (GPIO_USART2_TX_1|GPIO_SPEED_100MHz) /* PA2 */ +# define GPIO_USART2_RX (GPIO_USART2_RX_1|GPIO_SPEED_100MHz) /* PA3 */ + + /* RS485 DIR pin: PA1 */ + +# define GPIO_USART2_RS485_DIR (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_50MHz |\ + GPIO_OUTPUT_CLEAR | GPIO_PORTA | GPIO_PIN1) + +#endif + +/* USART6: + * RXD: PC7 CN2 pin 15 + * TXD: PC6 CN2 pin 17 + */ + +#define GPIO_USART6_RX (GPIO_USART6_RX_1|GPIO_SPEED_100MHz) /* PC7 */ +#define GPIO_USART6_TX (GPIO_USART6_TX_1|GPIO_SPEED_100MHz) /* PC6 */ + +/* PWM + * + * The STM32F401RC-RS485 has no real on-board PWM devices, but the board + * can be configured to output a pulse train using TIM3 CH1 on PA6. + */ + +#define GPIO_TIM3_CH1OUT (GPIO_TIM3_CH1OUT_1|GPIO_SPEED_50MHz) + +/* Quadrature Encoder + * + * Use Timer 3 (TIM3) on channels 1 and 2 for QEncoder, using PB4 and PA7. + */ + +#define GPIO_TIM3_CH1IN GPIO_TIM3_CH1IN_2 +#define GPIO_TIM3_CH2IN GPIO_TIM3_CH2IN_1 + +/* HCSR04 driver */ + +/* Pins config to use with HC-SR04 sensor */ + +#define GPIO_HCSR04_INT (GPIO_INPUT |GPIO_FLOAT |GPIO_EXTI | GPIO_PORTB | GPIO_PIN1) +#define GPIO_HCSR04_TRIG (GPIO_OUTPUT_CLEAR | GPIO_OUTPUT | GPIO_SPEED_50MHz | GPIO_PORTB | GPIO_PIN0) + +#define BOARD_HCSR04_GPIO_INT GPIO_HCSR04_INT +#define BOARD_HCSR04_GPIO_TRIG GPIO_HCSR04_TRIG +#define BOARD_HCSR04_FRTIMER 1 /* TIM1 as free running timer */ + +/* I2C + * + * The optional _GPIO configurations allow the I2C driver to manually + * reset the bus to clear stuck slaves. They match the pin configuration, + * but are normally-high GPIOs. + */ + +#define GPIO_I2C1_SCL (GPIO_I2C1_SCL_2|GPIO_SPEED_50MHz) +#define GPIO_I2C1_SDA (GPIO_I2C1_SDA_1|GPIO_SPEED_50MHz) + +#define GPIO_I2C2_SCL (GPIO_I2C2_SCL_1|GPIO_SPEED_50MHz) +#define GPIO_I2C2_SDA (GPIO_I2C2_SDA_2|GPIO_SPEED_50MHz) + +/* SPI + * + * There are sensors on SPI1, and SPI2 is connected to the FRAM. + */ + +#define GPIO_SPI1_MISO (GPIO_SPI1_MISO_1|GPIO_SPEED_50MHz) +#define GPIO_SPI1_MOSI (GPIO_SPI1_MOSI_1|GPIO_SPEED_50MHz) +#define GPIO_SPI1_SCK (GPIO_SPI1_SCK_1|GPIO_SPEED_50MHz) + +#define GPIO_SPI2_MISO (GPIO_SPI2_MISO_1|GPIO_SPEED_50MHz) +#define GPIO_SPI2_MOSI (GPIO_SPI2_MOSI_1|GPIO_SPEED_50MHz) +#define GPIO_SPI2_SCK (GPIO_SPI2_SCK_2|GPIO_SPEED_50MHz) + +/* MAX7219 */ + +#define STM32_LCD_CS (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz|\ + GPIO_OUTPUT_SET|GPIO_PORTC|GPIO_PIN4) + +/* MFRC522 */ + +#define GPIO_RFID_CS (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz|\ + GPIO_OUTPUT_SET|GPIO_PORTC|GPIO_PIN5) + +/* MAX31855 */ + +#define GPIO_MAX31855_CS (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz|\ + GPIO_OUTPUT_SET|GPIO_PORTC|GPIO_PIN4) + +/* MAX6675 */ + +#define GPIO_MAX6675_CS (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz|\ + GPIO_OUTPUT_SET|GPIO_PORTC|GPIO_PIN5) +/* LEDs + * + * The STM32F401RC-RS485 boards provide 4 blue user LEDs. LD1, LD2, LD3 + * and LD4 that are connected to MCU I/O pins PC0, PC1, PC2 and PC3. + * - When the I/O is HIGH value, the LED is on. + * - When the I/O is LOW, the LED is off. + */ + +/* LED index values for use with board_userled() */ + +#define BOARD_LD1 0 +#define BOARD_LD2 1 +#define BOARD_LD3 2 +#define BOARD_LD4 3 +#define BOARD_NLEDS 4 + +/* LED bits for use with board_userled_all() */ + +#define BOARD_LED1_BIT (1 << BOARD_LD1) +#define BOARD_LED2_BIT (1 << BOARD_LD2) +#define BOARD_LED3_BIT (1 << BOARD_LD3) +#define BOARD_LED4_BIT (1 << BOARD_LD4) + +/* These LEDs are not used by the board port unless CONFIG_ARCH_LEDS is + * defined. In that case, the usage by the board port is defined in + * include/board.h and src/sam_leds.c. The LEDs are used to encode OS-related + * events as follows when the red LED (PE24) is available: + * + * SYMBOL Meaning LD2 + * ------------------- ----------------------- ----------- + * LED_STARTED NuttX has been started OFF + * LED_HEAPALLOCATE Heap has been allocated OFF + * LED_IRQSENABLED Interrupts enabled OFF + * LED_STACKCREATED Idle stack created ON + * LED_INIRQ In an interrupt No change + * LED_SIGNAL In a signal handler No change + * LED_ASSERTION An assertion failed No change + * LED_PANIC The system has crashed Blinking + * LED_IDLE MCU is in sleep mode Not used + * + * Thus if LD2, NuttX has successfully booted and is, apparently, running + * normally. If LD2 is flashing at approximately 2Hz, then a fatal error + * has been detected and the system has halted. + */ + +#define LED_STARTED 0 +#define LED_HEAPALLOCATE 0 +#define LED_IRQSENABLED 0 +#define LED_STACKCREATED 1 +#define LED_INIRQ 2 +#define LED_SIGNAL 2 +#define LED_ASSERTION 2 +#define LED_PANIC 1 + +/* Buttons + * The STM32F401RC-RS485 has 3 user buttons: SW3, SW4, and SW5. + * They are connected to PB13, PB14, and PB15 respectively. + */ + +#define BUTTON_SW3 0 +#define BUTTON_SW4 1 +#define BUTTON_SW5 2 +#define NUM_BUTTONS 3 + +#define BUTTON_SW3_BIT (1 << BUTTON_SW3) +#define BUTTON_SW4_BIT (1 << BUTTON_SW4) +#define BUTTON_SW5_BIT (1 << BUTTON_SW5) + +#define GPIO_TIM2_CH1IN (GPIO_TIM2_CH1IN_1 | GPIO_PULLUP | GPIO_SPEED_50MHz) +#define GPIO_TIM2_CH2IN (GPIO_TIM2_CH2IN_1 | GPIO_PULLUP | GPIO_SPEED_50MHz) + +/* Stepper Motor - DRV8266 */ + +#define GPIO_DIR (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz|\ + GPIO_OUTPUT_CLEAR|GPIO_PORTA|GPIO_PIN7) +#define GPIO_STEP (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz|\ + GPIO_OUTPUT_CLEAR|GPIO_PORTC|GPIO_PIN4) +#define GPIO_SLEEP (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz|\ + GPIO_OUTPUT_CLEAR|GPIO_PORTC|GPIO_PIN5) + +#define GPIO_M1 (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz|\ + GPIO_OUTPUT_CLEAR|GPIO_PORTB|GPIO_PIN0) +#define GPIO_M2 (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz|\ + GPIO_OUTPUT_CLEAR|GPIO_PORTB|GPIO_PIN1) +#define GPIO_M3 (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz|\ + GPIO_OUTPUT_CLEAR|GPIO_PORTB|GPIO_PIN2) + +#define GPIO_RESET (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz|\ + GPIO_OUTPUT_CLEAR|GPIO_PORTB|GPIO_PIN10) + +/* DAC */ + +#define GPIO_DAC1_OUT1 GPIO_DAC1_OUT1_0 +#define GPIO_DAC1_OUT2 GPIO_DAC1_OUT2_0 + +/* SDIO */ + +#define GPIO_SDIO_CK (GPIO_SDIO_CK_0|GPIO_SPEED_50MHz) +#define GPIO_SDIO_CMD (GPIO_SDIO_CMD_0|GPIO_SPEED_50MHz) +#define GPIO_SDIO_D0 (GPIO_SDIO_D0_0|GPIO_SPEED_50MHz) +#define GPIO_SDIO_D1 (GPIO_SDIO_D1_0|GPIO_SPEED_50MHz) +#define GPIO_SDIO_D2 (GPIO_SDIO_D2_0|GPIO_SPEED_50MHz) +#define GPIO_SDIO_D3 (GPIO_SDIO_D3_0|GPIO_SPEED_50MHz) + +/* USB OTG FS */ + +#define GPIO_OTGFS_DM (GPIO_OTGFS_DM_0|GPIO_SPEED_100MHz) +#define GPIO_OTGFS_DP (GPIO_OTGFS_DP_0|GPIO_SPEED_100MHz) +#define GPIO_OTGFS_ID (GPIO_OTGFS_ID_0|GPIO_SPEED_100MHz) +#define GPIO_OTGFS_SOF (GPIO_OTGFS_SOF_0|GPIO_SPEED_100MHz) + +#endif /* __BOARDS_ARM_STM32F401RC_RS485_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32f4/stm32f401rc-rs485/scripts/Make.defs b/boards/arm/stm32f4/stm32f401rc-rs485/scripts/Make.defs new file mode 100644 index 0000000000000..51422c125e678 --- /dev/null +++ b/boards/arm/stm32f4/stm32f401rc-rs485/scripts/Make.defs @@ -0,0 +1,46 @@ +############################################################################ +# boards/arm/stm32f4/stm32f401rc-rs485/scripts/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/.config +include $(TOPDIR)/tools/Config.mk +include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs + +ifeq ($(CONFIG_ARCH_CHIP_STM32F401RC),y) +LDSCRIPT = ld.script +endif + +ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) + +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) + +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 + diff --git a/boards/arm/stm32f4/stm32f401rc-rs485/scripts/ld.script b/boards/arm/stm32f4/stm32f401rc-rs485/scripts/ld.script new file mode 100644 index 0000000000000..fc6386990b81e --- /dev/null +++ b/boards/arm/stm32f4/stm32f401rc-rs485/scripts/ld.script @@ -0,0 +1,109 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f401rc-rs485/scripts/ld.script + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* The STM32F401RC has 256Kb of FLASH beginning at address 0x0800:0000 and + * 64Kb of SRAM beginning at address 0x2000:0000. When booting from FLASH, + * FLASH memory is aliased to address 0x0000:0000 where the code expects to + * begin execution by jumping to the entry point in the 0x0800:0000 address + * range. + */ + +MEMORY +{ + flash (rx) : ORIGIN = 0x08000000, LENGTH = 256K + sram (rwx) : ORIGIN = 0x20000000, LENGTH = 64K +} + +OUTPUT_ARCH(arm) +EXTERN(_vectors) +ENTRY(_stext) +SECTIONS +{ + .text : { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > flash + + .init_section : { + _sinit = ABSOLUTE(.); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array .ctors)) + _einit = ABSOLUTE(.); + } > flash + + .ARM.extab : { + *(.ARM.extab*) + } > flash + + __exidx_start = ABSOLUTE(.); + .ARM.exidx : { + *(.ARM.exidx*) + } > flash + __exidx_end = ABSOLUTE(.); + + _eronly = ABSOLUTE(.); + + /* The STM32F401RC has 128Kb of SRAM beginning at the following address */ + + .data : { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > sram AT > flash + + .bss : { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + _ebss = ABSOLUTE(.); + } > sram + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/stm32f4/stm32f401rc-rs485/src/CMakeLists.txt b/boards/arm/stm32f4/stm32f401rc-rs485/src/CMakeLists.txt new file mode 100644 index 0000000000000..968d1e9dd9244 --- /dev/null +++ b/boards/arm/stm32f4/stm32f401rc-rs485/src/CMakeLists.txt @@ -0,0 +1,82 @@ +# ############################################################################## +# boards/arm/stm32f4/stm32f401rc-rs485/src/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(SRCS stm32_boot.c stm32_bringup.c) + +if(CONFIG_ARCH_LEDS) + list(APPEND SRCS stm32_autoleds.c) +endif() + +if(CONFIG_USERLED) + list(APPEND SRCS stm32_userleds.c) +endif() + +if(CONFIG_ARCH_BUTTONS) + list(APPEND SRCS stm32_buttons.c) +endif() + +if(CONFIG_ADC) + list(APPEND SRCS stm32_adc.c) +endif() + +if(CONFIG_STM32_SDIO) + list(APPEND SRCS stm32_sdio.c) +endif() + +if(CONFIG_STM32_OTGFS) + list(APPEND SRCS stm32_usb.c) +endif() + +if(CONFIG_STM32_CONFIG_I2C_EE_24XXEEPROM) + list(APPEND SRCS stm32_at24.c) +endif() + +if(CONFIG_STM32_PWM) + list(APPEND SRCS stm32_pwm.c) +endif() + +if(CONFIG_USBMSC) + list(APPEND SRCS stm32_usbmsc.c) +endif() + +if(CONFIG_DEV_GPIO) + list(APPEND SRCS stm32_gpio.c) +endif() + +if(CONFIG_VIDEO_FB) + if(CONFIG_LCD_SSD1306) + list(APPEND SRCS stm32_lcd_ssd1306.c) + endif() + if(CONFIG_LCD_ST7735) + list(APPEND SRCS stm32_lcd_st7735.c) + endif() +endif() + +if(CONFIG_ADC_HX711) + list(APPEND SRCS stm32_hx711.c) +endif() + +target_sources(board PRIVATE ${SRCS}) + +if(CONFIG_ARCH_CHIP_STM32F401RC) + set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/ld.script") +endif() diff --git a/boards/arm/stm32f4/stm32f401rc-rs485/src/Make.defs b/boards/arm/stm32f4/stm32f401rc-rs485/src/Make.defs new file mode 100644 index 0000000000000..cc672de33d24d --- /dev/null +++ b/boards/arm/stm32f4/stm32f401rc-rs485/src/Make.defs @@ -0,0 +1,82 @@ +############################################################################ +# boards/arm/stm32f4/stm32f401rc-rs485/src/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +CSRCS = stm32_boot.c stm32_bringup.c stm32_spi.c + +ifeq ($(CONFIG_VIDEO_FB),y) + ifeq ($(CONFIG_LCD_SSD1306),y) + CSRCS += stm32_lcd_ssd1306.c + endif + ifeq ($(CONFIG_LCD_ST7735),y) + CSRCS += stm32_lcd_st7735.c + endif +endif + +ifeq ($(CONFIG_ARCH_LEDS),y) +CSRCS += stm32_autoleds.c +endif + +ifeq ($(CONFIG_USERLED),y) +CSRCS += stm32_userleds.c +endif + +ifeq ($(CONFIG_ARCH_BUTTONS),y) +CSRCS += stm32_buttons.c +endif + +ifeq ($(CONFIG_ADC),y) +CSRCS += stm32_adc.c +endif + +ifeq ($(CONFIG_STM32_SDIO),y) +CSRCS += stm32_sdio.c +endif + +ifeq ($(CONFIG_STM32_OTGFS),y) +CSRCS += stm32_usb.c +endif + +ifeq ($(CONFIG_I2C_EE_24XX),y) +CSRCS += stm32_at24.c +endif + +ifeq ($(CONFIG_STM32_PWM),y) +CSRCS += stm32_pwm.c +endif + +ifeq ($(CONFIG_USBMSC),y) +CSRCS += stm32_usbmsc.c +endif + +ifeq ($(CONFIG_DEV_GPIO),y) +CSRCS += stm32_gpio.c +endif + +ifeq ($(CONFIG_ADC_HX711),y) +CSRCS += stm32_hx711.c +endif + +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_adc.c b/boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_adc.c new file mode 100644 index 0000000000000..f9140a1421b46 --- /dev/null +++ b/boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_adc.c @@ -0,0 +1,119 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_adc.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32_pwm.h" +#include "stm32_adc.h" +#include "stm32f401rc-rs485.h" + +#ifdef CONFIG_STM32_ADC1 + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* The number of ADC channels in the conversion list */ + +#define ADC1_NCHANNELS 2 + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* Identifying number of each ADC channel. */ + +/* There are two trimpots on the board connected to ADC1_IN0 and ADC1_IN4 */ + +static const uint8_t g_adc1_chanlist[ADC1_NCHANNELS] = +{ + 0, 4 +}; + +/* Configurations of pins used byte each ADC channels */ + +static const uint32_t g_adc1_pinlist[ADC1_NCHANNELS] = +{ + GPIO_ADC1_IN0_0, + GPIO_ADC1_IN4_0 +}; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_adc_setup + * + * Description: + * Initialize ADC and register the ADC driver. + * + ****************************************************************************/ + +int stm32_adc_setup(void) +{ + struct adc_dev_s *adc; + int ret; + int i; + + /* Configure the pins as analog inputs for the selected channels */ + + for (i = 0; i < ADC1_NCHANNELS; i++) + { + stm32_configgpio(g_adc1_pinlist[i]); + } + + /* Call stm32_adcinitialize() to get an instance of the ADC interface */ + + adc = stm32_adcinitialize(1, g_adc1_chanlist, ADC1_NCHANNELS); + if (adc == NULL) + { + aerr("ERROR: Failed to get ADC interface\n"); + return -ENODEV; + } + + /* Register the ADC driver at "/dev/adc0" */ + + ret = adc_register("/dev/adc0", adc); + if (ret < 0) + { + aerr("ERROR: adc_register failed: %d\n", ret); + return ret; + } + + return OK; +} + +#endif /* CONFIG_STM32_ADC1 */ diff --git a/boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_at24.c b/boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_at24.c new file mode 100644 index 0000000000000..8cad42b70a299 --- /dev/null +++ b/boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_at24.c @@ -0,0 +1,96 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_at24.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include +#include +#include +#include + +#include +#include + +#include "stm32f401rc-rs485.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define AT24_I2C_BUS 1 /* EEPROM chip is configured to use I2C1 */ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_at24_init + * + * Description: + * Initialize and configure the AT24 serial EEPROM + * + ****************************************************************************/ + +int stm32_at24_init(char *path) +{ + struct i2c_master_s *i2c; + static bool initialized = false; + int ret; + + /* Have we already initialized? */ + + if (!initialized) + { + /* No.. Get the I2C bus driver */ + + finfo("Initialize I2C%d\n", AT24_I2C_BUS); + i2c = stm32_i2cbus_initialize(AT24_I2C_BUS); + if (!i2c) + { + ferr("ERROR: Failed to initialize I2C%d\n", AT24_I2C_BUS); + return -ENODEV; + } + + /* Now bind the I2C interface to the AT24 I2C EEPROM driver */ + + finfo("Bind the AT24 EEPROM driver to I2C%d\n", AT24_I2C_BUS); + ret = ee24xx_initialize(i2c, 0x50, path, EEPROM_AT24CM02, false); + if (ret < 0) + { + ferr("ERROR: Failed to bind I2C%d to the AT24 EEPROM driver\n", + AT24_I2C_BUS); + return -ENODEV; + } + + /* Now we are initialized */ + + initialized = true; + } + + return OK; +} diff --git a/boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_autoleds.c b/boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_autoleds.c new file mode 100644 index 0000000000000..1d02e1f7d139b --- /dev/null +++ b/boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_autoleds.c @@ -0,0 +1,83 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_autoleds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32.h" +#include "stm32f401rc-rs485.h" + +#include + +#ifdef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_autoled_initialize + ****************************************************************************/ + +void board_autoled_initialize(void) +{ + /* Configure LD2 GPIO for output */ + + stm32_configgpio(GPIO_LED1); +} + +/**************************************************************************** + * Name: board_autoled_on + ****************************************************************************/ + +void board_autoled_on(int led) +{ + if (led == 1) + { + stm32_gpiowrite(GPIO_LED1, true); + } +} + +/**************************************************************************** + * Name: board_autoled_off + ****************************************************************************/ + +void board_autoled_off(int led) +{ + if (led == 1) + { + stm32_gpiowrite(GPIO_LED1, false); + } +} + +#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_boot.c b/boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_boot.c new file mode 100644 index 0000000000000..eb622ee8ac4fa --- /dev/null +++ b/boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_boot.c @@ -0,0 +1,93 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_boot.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include + +#include + +#include "arm_internal.h" +#include "stm32f401rc-rs485.h" + +#include + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_boardinitialize + * + * Description: + * All STM32 architectures must provide the following entry point. + * This entry point is called early in the initialization -- after all + * memory has been configured and mapped but before any devices have been + * initialized. + * + ****************************************************************************/ + +void stm32_boardinitialize(void) +{ + /* Configure on-board LEDs if LED support has been selected. */ + +#ifdef CONFIG_ARCH_LEDS + board_autoled_initialize(); +#endif + + /* Configure SPI chip selects if + * 1) SPI is not disabled, and + * 2) the weak function stm32_spidev_initialize() has been brought into + * the link. + */ + +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) + stm32_spidev_initialize(); +#endif +} + +/**************************************************************************** + * Name: board_late_initialize + * + * Description: + * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_late_initialize(). board_late_initialize() will + * be called immediately after up_initialize() is called and just before + * the initial application is started. This additional initialization + * phase may be used, for example, to initialize board-specific device + * drivers. + * + ****************************************************************************/ + +#ifdef CONFIG_BOARD_LATE_INITIALIZE +void board_late_initialize(void) +{ + stm32_bringup(); +} +#endif diff --git a/boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_bringup.c b/boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_bringup.c new file mode 100644 index 0000000000000..61d5448a187f3 --- /dev/null +++ b/boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_bringup.c @@ -0,0 +1,405 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_bringup.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include +#include + +#include + +#ifdef CONFIG_USERLED +# include +#endif + +#ifdef CONFIG_INPUT_BUTTONS +# include +#endif + +#include "stm32f401rc-rs485.h" + +#include + +#ifdef CONFIG_SENSORS_LM75 +#include "stm32_lm75.h" +#endif + +#ifdef CONFIG_SENSORS_QENCODER +#include "board_qencoder.h" +#endif + +#ifdef CONFIG_RNDIS +# include +#endif + +#ifdef CONFIG_SENSORS_HCSR04 +#include "stm32_hcsr04.h" +#endif + +#ifdef CONFIG_LCD_MAX7219 +#include "stm32_max7219_matrix.h" +#endif + +#ifdef CONFIG_CL_MFRC522 +#include "stm32_mfrc522.h" +#endif + +#ifdef CONFIG_STEPPER_DRV8825 +#include "stm32_drv8266.h" +#endif + +#ifdef CONFIG_SENSORS_BMP280 +#include "stm32_bmp280.h" +#endif + +#ifdef CONFIG_LCD_BACKPACK +#include "stm32_lcd_backpack.h" +#endif + +#ifdef CONFIG_WS2812 +#include "stm32_ws2812.h" +#endif + +#ifdef CONFIG_SENSORS_BMP180 +#include "stm32_bmp180.h" +#endif + +#ifdef CONFIG_SENSORS_MAX31855 +#include "stm32_max31855.h" +#endif + +#ifdef CONFIG_SENSORS_MAX6675 +#include "stm32_max6675.h" +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_i2c_register + * + * Description: + * Register one I2C drivers for the I2C tool. + * + ****************************************************************************/ + +#if defined(CONFIG_I2C) && defined(CONFIG_SYSTEM_I2CTOOL) +static void stm32_i2c_register(int bus) +{ + struct i2c_master_s *i2c; + int ret; + + i2c = stm32_i2cbus_initialize(bus); + if (i2c == NULL) + { + syslog(LOG_ERR, "ERROR: Failed to get I2C%d interface\n", bus); + } + else + { + ret = i2c_register(i2c, bus); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to register I2C%d driver: %d\n", + bus, ret); + stm32_i2cbus_uninitialize(i2c); + } + } +} +#endif + +/**************************************************************************** + * Name: stm32_i2ctool + * + * Description: + * Register I2C drivers for the I2C tool. + * + ****************************************************************************/ + +#if defined(CONFIG_I2C) && defined(CONFIG_SYSTEM_I2CTOOL) +static void stm32_i2ctool(void) +{ + stm32_i2c_register(1); +#if 0 + stm32_i2c_register(1); + stm32_i2c_register(2); +#endif +} +#else +# define stm32_i2ctool() +#endif + +/**************************************************************************** + * Name: stm32_bringup + * + * Description: + * Perform architecture-specific initialization + * + * CONFIG_BOARD_LATE_INITIALIZE=y : + * Called from board_late_initialize(). + * + ****************************************************************************/ + +int stm32_bringup(void) +{ + int ret = OK; + +#ifdef CONFIG_USERLED + /* Register the LED driver */ + + ret = userled_lower_initialize("/dev/userleds"); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: userled_lower_initialize() failed: %d\n", ret); + } +#endif + +#if defined(CONFIG_I2C) && defined(CONFIG_SYSTEM_I2CTOOL) + stm32_i2ctool(); +#endif + +#ifdef CONFIG_SENSORS_MAX31855 + /* Register device 0 on spi channel 1 */ + + ret = board_max31855_initialize(0, 1); + if (ret < 0) + { + serr("ERROR: stm32_max31855initialize failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_SENSORS_MAX6675 + ret = board_max6675_initialize(0, 1); + if (ret < 0) + { + serr("ERROR: stm32_max6675initialize failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_I2C_EE_24XX + ret = stm32_at24_init("/dev/eeprom"); + if (ret < 0) + { + syslog(LOG_ERR, "Failed to initialize EEPROM HX24LCXXB: %d\n", ret); + return ret; + } +#endif + +#ifdef CONFIG_LM75_I2C + /* Configure and initialize the LM75 sensor */ + + ret = board_lm75_initialize(0, 1); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: board_lm75_initialize() failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_INPUT_BUTTONS + /* Register the BUTTON driver */ + + ret = btn_lower_initialize("/dev/buttons"); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: btn_lower_initialize() failed: %d\n", ret); + } +#endif + +#if defined(CONFIG_ADC) && defined(CONFIG_STM32_ADC1) + /* Initialize ADC and register the ADC driver. */ + + ret = stm32_adc_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_adc_setup failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_PWM + /* Initialize PWM and register the PWM device */ + + ret = stm32_pwm_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_pwm_setup() failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_LCD_MAX7219 + /* Configure and initialize the MAX7219 driver */ + + ret = board_max7219_matrix_initialize(1); + if (ret < 0) + { + syslog(LOG_ERR, \ + "ERROR: board_max7219_matrix_initialize failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_VIDEO_FB + /* Initialize and register the framebuffer driver */ + + ret = fb_register(0, 0); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: fb_register() failed: %d\n", ret); + } +#endif + +#ifdef HAVE_SDIO + /* Initialize the SDIO block driver */ + + ret = stm32_sdio_initialize(); + if (ret != OK) + { + syslog(LOG_ERR, "ERROR: Failed to initialize MMC/SD driver: %d\n", + ret); + return ret; + } +#endif + +#ifdef CONFIG_SENSORS_QENCODER + /* Initialize and register the qencoder driver */ + + ret = board_qencoder_initialize(0, STM32F401RCRS485_QETIMER); + if (ret != OK) + { + syslog(LOG_ERR, + "ERROR: Failed to register the qencoder: %d\n", + ret); + return ret; + } +#endif + +#if defined(CONFIG_RNDIS) && !defined(CONFIG_RNDIS_COMPOSITE) + uint8_t mac[6]; + mac[0] = 0xa0; /* TODO */ + mac[1] = (CONFIG_NETINIT_MACADDR_2 >> (8 * 0)) & 0xff; + mac[2] = (CONFIG_NETINIT_MACADDR_1 >> (8 * 3)) & 0xff; + mac[3] = (CONFIG_NETINIT_MACADDR_1 >> (8 * 2)) & 0xff; + mac[4] = (CONFIG_NETINIT_MACADDR_1 >> (8 * 1)) & 0xff; + mac[5] = (CONFIG_NETINIT_MACADDR_1 >> (8 * 0)) & 0xff; + usbdev_rndis_initialize(mac); +#endif + +#ifdef CONFIG_SENSORS_HCSR04 + /* Configure and initialize the HC-SR04 distance sensor */ + + ret = board_hcsr04_initialize(0); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: board_hcsr04_initialize() failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_STEPPER_DRV8825 + /* Configure and initialize the drv8825 driver */ + + ret = board_drv8825_initialize(0); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: board_drv8825_initialize failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_CL_MFRC522 + ret = stm32_mfrc522initialize("/dev/rfid0"); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_mfrc522initialize() failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_SENSORS_BMP280 + /* Initialize the BMP280 pressure sensor. */ + + ret = board_bmp280_initialize(0, 1); + if (ret < 0) + { + syslog(LOG_ERR, "Failed to initialize BMP280, error %d\n", ret); + return ret; + } +#endif + +#ifdef CONFIG_LCD_BACKPACK + /* slcd:0, i2c:1, rows=2, cols=16 */ + + ret = board_lcd_backpack_init(0, 1, 2, 16); + if (ret < 0) + { + syslog(LOG_ERR, "Failed to initialize PCF8574 LCD, error %d\n", ret); + return ret; + } +#endif + +#if defined(CONFIG_WS2812) && defined(CONFIG_WS2812_LED_COUNT) + /* Configure and initialize the WS2812 LEDs. */ + + ret = board_ws2812_initialize(0, WS2812_SPI, CONFIG_WS2812_LED_COUNT); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: board_ws2812_initialize() failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_DEV_GPIO + /* Initialize GPIO driver */ + + ret = stm32_gpio_initialize(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_gpio_initialize() failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_SENSORS_BMP180 + /* Initialize the BMP180 pressure sensor. */ + + ret = board_bmp180_initialize(0, 1); + if (ret < 0) + { + syslog(LOG_ERR, "Failed to initialize BMP180, error %d\n", ret); + return ret; + } +#endif + +#ifdef CONFIG_ADC_HX711 + ret = stm32_hx711_initialize(); + if (ret != OK) + { + aerr("ERROR: Failed to initialize hx711: %d\n", ret); + } +#endif + + return ret; +} diff --git a/boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_buttons.c b/boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_buttons.c new file mode 100644 index 0000000000000..9ab473a526722 --- /dev/null +++ b/boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_buttons.c @@ -0,0 +1,151 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_buttons.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include +#include + +#include "stm32.h" +#include "stm32f401rc-rs485.h" + +#ifdef CONFIG_ARCH_BUTTONS + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* Pin configuration for each STM32F401RC RS485 button. This array is indexed + * by the BUTTON_* definitions in board.h + */ + +static const uint32_t g_buttons[NUM_BUTTONS] = +{ + GPIO_BTN_SW3, GPIO_BTN_SW4, GPIO_BTN_SW5 +}; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_button_initialize + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. + * + ****************************************************************************/ + +uint32_t board_button_initialize(void) +{ + int i; + + /* Configure the GPIO pins as inputs. NOTE that EXTI interrupts are + * configured for all pins. + */ + + for (i = 0; i < NUM_BUTTONS; i++) + { + stm32_configgpio(g_buttons[i]); + } + + return NUM_BUTTONS; +} + +/**************************************************************************** + * Name: board_buttons + ****************************************************************************/ + +uint32_t board_buttons(void) +{ + uint32_t ret = 0; + int i; + + /* Check that state of each key */ + + for (i = 0; i < NUM_BUTTONS; i++) + { + /* A LOW value means that the key is pressed. */ + + bool released = stm32_gpioread(g_buttons[i]); + + /* Accumulate the set of depressed (not released) keys */ + + if (!released) + { + ret |= (1 << i); + } + } + + return ret; +} + +/**************************************************************************** + * Button support. + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. + * + * After board_button_initialize() has been called, board_buttons() may be + * called to collect the state of all buttons. board_buttons() returns an + * 32-bit bit set with each bit associated with a button. See the + * BUTTON_*_BIT definitions in board.h for the meaning of each bit. + * + * board_button_irq() may be called to register an interrupt handler that + * will be called when a button is depressed or released. The ID value is a + * button enumeration value that uniquely identifies a button resource. See + * the BUTTON_* definitions in board.h for the meaning of enumeration + * value. + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_IRQBUTTONS +int board_button_irq(int id, xcpt_t irqhandler, void *arg) +{ + int ret = -EINVAL; + + /* The following should be atomic */ + + if (id >= MIN_IRQBUTTON && id <= MAX_IRQBUTTON) + { + ret = stm32_gpiosetevent(g_buttons[id], true, true, true, + irqhandler, arg); + } + + return ret; +} +#endif +#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_gpio.c b/boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_gpio.c new file mode 100644 index 0000000000000..0cfe7d24a6755 --- /dev/null +++ b/boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_gpio.c @@ -0,0 +1,343 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_gpio.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include +#include + +#include + +#include "chip.h" +#include "stm32.h" +#include "stm32f401rc-rs485.h" + +#if defined(CONFIG_DEV_GPIO) && !defined(CONFIG_GPIO_LOWER_HALF) + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +struct stm32gpio_dev_s +{ + struct gpio_dev_s gpio; + uint8_t id; +}; + +struct stm32gpint_dev_s +{ + struct stm32gpio_dev_s stm32gpio; + pin_interrupt_t callback; +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +#if BOARD_NGPIOIN > 0 +static int gpin_read(struct gpio_dev_s *dev, bool *value); +#endif +#if BOARD_NGPIOOUT > 0 +static int gpout_read(struct gpio_dev_s *dev, bool *value); +static int gpout_write(struct gpio_dev_s *dev, bool value); +#endif +#if BOARD_NGPIOINT > 0 +static int gpint_read(struct gpio_dev_s *dev, bool *value); +static int gpint_attach(struct gpio_dev_s *dev, + pin_interrupt_t callback); +static int gpint_enable(struct gpio_dev_s *dev, bool enable); +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#if BOARD_NGPIOIN > 0 +static const struct gpio_operations_s gpin_ops = +{ + .go_read = gpin_read, + .go_write = NULL, + .go_attach = NULL, + .go_enable = NULL, +}; +#endif + +#if BOARD_NGPIOOUT > 0 +static const struct gpio_operations_s gpout_ops = +{ + .go_read = gpout_read, + .go_write = gpout_write, + .go_attach = NULL, + .go_enable = NULL, +}; +#endif + +#if BOARD_NGPIOINT > 0 +static const struct gpio_operations_s gpint_ops = +{ + .go_read = gpint_read, + .go_write = NULL, + .go_attach = gpint_attach, + .go_enable = gpint_enable, +}; +#endif + +#if BOARD_NGPIOIN > 0 +/* This array maps the GPIO pins used as INPUT */ + +static const uint32_t g_gpioinputs[BOARD_NGPIOIN] = +{ + GPIO_IN1, +}; + +static struct stm32gpio_dev_s g_gpin[BOARD_NGPIOIN]; +#endif + +#if BOARD_NGPIOOUT +/* This array maps the GPIO pins used as OUTPUT */ + +static const uint32_t g_gpiooutputs[BOARD_NGPIOOUT] = +{ + GPIO_OUT1, +}; + +static struct stm32gpio_dev_s g_gpout[BOARD_NGPIOOUT]; +#endif + +#if BOARD_NGPIOINT > 0 +/* This array maps the GPIO pins used as INTERRUPT INPUTS */ + +static const uint32_t g_gpiointinputs[BOARD_NGPIOINT] = +{ + GPIO_INT1, +}; + +static struct stm32gpint_dev_s g_gpint[BOARD_NGPIOINT]; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +#if BOARD_NGPIOINT > 0 +static int stm32gpio_interrupt(int irq, void *context, void *arg) +{ + struct stm32gpint_dev_s *stm32gpint = + (struct stm32gpint_dev_s *)arg; + + DEBUGASSERT(stm32gpint != NULL && stm32gpint->callback != NULL); + gpioinfo("Interrupt! callback=%p\n", stm32gpint->callback); + + stm32gpint->callback(&stm32gpint->stm32gpio.gpio, + stm32gpint->stm32gpio.id); + return OK; +} +#endif + +#if BOARD_NGPIOIN > 0 +static int gpin_read(struct gpio_dev_s *dev, bool *value) +{ + struct stm32gpio_dev_s *stm32gpio = + (struct stm32gpio_dev_s *)dev; + + DEBUGASSERT(stm32gpio != NULL && value != NULL); + DEBUGASSERT(stm32gpio->id < BOARD_NGPIOIN); + gpioinfo("Reading...\n"); + + *value = stm32_gpioread(g_gpioinputs[stm32gpio->id]); + return OK; +} +#endif + +#if BOARD_NGPIOOUT > 0 +static int gpout_read(struct gpio_dev_s *dev, bool *value) +{ + struct stm32gpio_dev_s *stm32gpio = + (struct stm32gpio_dev_s *)dev; + + DEBUGASSERT(stm32gpio != NULL && value != NULL); + DEBUGASSERT(stm32gpio->id < BOARD_NGPIOOUT); + gpioinfo("Reading...\n"); + + *value = stm32_gpioread(g_gpiooutputs[stm32gpio->id]); + return OK; +} + +static int gpout_write(struct gpio_dev_s *dev, bool value) +{ + struct stm32gpio_dev_s *stm32gpio = + (struct stm32gpio_dev_s *)dev; + + DEBUGASSERT(stm32gpio != NULL); + DEBUGASSERT(stm32gpio->id < BOARD_NGPIOOUT); + gpioinfo("Writing %d\n", (int)value); + + stm32_gpiowrite(g_gpiooutputs[stm32gpio->id], value); + return OK; +} +#endif + +#if BOARD_NGPIOINT > 0 +static int gpint_read(struct gpio_dev_s *dev, bool *value) +{ + struct stm32gpint_dev_s *stm32gpint = + (struct stm32gpint_dev_s *)dev; + + DEBUGASSERT(stm32gpint != NULL && value != NULL); + DEBUGASSERT(stm32gpint->stm32gpio.id < BOARD_NGPIOINT); + gpioinfo("Reading int pin...\n"); + + *value = stm32_gpioread(g_gpiointinputs[stm32gpint->stm32gpio.id]); + return OK; +} + +static int gpint_attach(struct gpio_dev_s *dev, + pin_interrupt_t callback) +{ + struct stm32gpint_dev_s *stm32gpint = + (struct stm32gpint_dev_s *)dev; + + gpioinfo("Attaching the callback\n"); + + /* Make sure the interrupt is disabled */ + + stm32_gpiosetevent(g_gpiointinputs[stm32gpint->stm32gpio.id], false, + false, false, NULL, NULL); + + gpioinfo("Attach %p\n", callback); + stm32gpint->callback = callback; + return OK; +} + +static int gpint_enable(struct gpio_dev_s *dev, bool enable) +{ + struct stm32gpint_dev_s *stm32gpint = + (struct stm32gpint_dev_s *)dev; + + if (enable) + { + if (stm32gpint->callback != NULL) + { + gpioinfo("Enabling the interrupt\n"); + + /* Configure the interrupt for rising edge */ + + stm32_gpiosetevent(g_gpiointinputs[stm32gpint->stm32gpio.id], + true, false, false, stm32gpio_interrupt, + &g_gpint[stm32gpint->stm32gpio.id]); + } + } + else + { + gpioinfo("Disable the interrupt\n"); + stm32_gpiosetevent(g_gpiointinputs[stm32gpint->stm32gpio.id], + false, false, false, NULL, NULL); + } + + return OK; +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_gpio_initialize + * + * Description: + * Initialize GPIO drivers for use with /apps/examples/gpio + * + ****************************************************************************/ + +int stm32_gpio_initialize(void) +{ + int i; + int pincount = 0; + +#if BOARD_NGPIOIN > 0 + for (i = 0; i < BOARD_NGPIOIN; i++) + { + /* Setup and register the GPIO pin */ + + g_gpin[i].gpio.gp_pintype = GPIO_INPUT_PIN; + g_gpin[i].gpio.gp_ops = &gpin_ops; + g_gpin[i].id = i; + gpio_pin_register(&g_gpin[i].gpio, pincount); + + /* Configure the pin that will be used as input */ + + stm32_configgpio(g_gpioinputs[i]); + + pincount++; + } +#endif + +#if BOARD_NGPIOOUT > 0 + for (i = 0; i < BOARD_NGPIOOUT; i++) + { + /* Setup and register the GPIO pin */ + + g_gpout[i].gpio.gp_pintype = GPIO_OUTPUT_PIN; + g_gpout[i].gpio.gp_ops = &gpout_ops; + g_gpout[i].id = i; + gpio_pin_register(&g_gpout[i].gpio, pincount); + + /* Configure the pin that will be used as output */ + + stm32_gpiowrite(g_gpiooutputs[i], 0); + stm32_configgpio(g_gpiooutputs[i]); + + pincount++; + } +#endif + +#if BOARD_NGPIOINT > 0 + for (i = 0; i < BOARD_NGPIOINT; i++) + { + /* Setup and register the GPIO pin */ + + g_gpint[i].stm32gpio.gpio.gp_pintype = GPIO_INTERRUPT_PIN; + g_gpint[i].stm32gpio.gpio.gp_ops = &gpint_ops; + g_gpint[i].stm32gpio.id = i; + gpio_pin_register(&g_gpint[i].stm32gpio.gpio, pincount); + + /* Configure the pin that will be used as interrupt input */ + + stm32_configgpio(g_gpiointinputs[i]); + + pincount++; + } +#endif + + return 0; +} +#endif /* CONFIG_DEV_GPIO && !CONFIG_GPIO_LOWER_HALF */ diff --git a/boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_hx711.c b/boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_hx711.c new file mode 100644 index 0000000000000..772a358f7d521 --- /dev/null +++ b/boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_hx711.c @@ -0,0 +1,104 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_hx711.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include +#include +#include +#include + +#include "stm32_gpio.h" +#include "stm32f401rc-rs485.h" + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +static int stm32_hx711_clock_set(unsigned char minor, int value); +static int stm32_hx711_data_read(unsigned char minor); +static int stm32_hx711_data_irq(unsigned char minor, + xcpt_t handler, void *arg); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +struct hx711_lower_s g_lower = +{ + .data_read = stm32_hx711_data_read, + .clock_set = stm32_hx711_clock_set, + .data_irq = stm32_hx711_data_irq, + .cleanup = NULL +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +static int stm32_hx711_clock_set(unsigned char minor, int value) +{ + UNUSED(minor); + + stm32_gpiowrite(HX711_CLK_PIN, value); + return OK; +} + +static int stm32_hx711_data_read(unsigned char minor) +{ + UNUSED(minor); + + return stm32_gpioread(HX711_DATA_PIN); +} + +static int stm32_hx711_data_irq(unsigned char minor, + xcpt_t handler, void *arg) +{ + UNUSED(minor); + + return stm32_gpiosetevent(HX711_DATA_PIN, false, true, true, handler, arg); +}; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +int stm32_hx711_initialize(void) +{ + int ret; + + stm32_configgpio(HX711_DATA_PIN); + stm32_configgpio(HX711_CLK_PIN); + + ret = hx711_register(0, &g_lower); + if (ret != 0) + { + aerr("ERROR: Failed to register hx711 device: %d\n", ret); + return -1; + } + + return OK; +} diff --git a/boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_lcd_ssd1306.c b/boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_lcd_ssd1306.c new file mode 100644 index 0000000000000..2bb64bfa1a2b5 --- /dev/null +++ b/boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_lcd_ssd1306.c @@ -0,0 +1,105 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_lcd_ssd1306.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include "stm32.h" +#include "stm32f401rc-rs485.h" + +#include "stm32_ssd1306.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define OLED_SPI_PORT 1 /* OLED display connected to SPI1 */ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_lcd_initialize + ****************************************************************************/ + +int board_lcd_initialize(void) +{ + int ret; + + /* Initialize the RESET and DC pins */ + + stm32_configgpio(GPIO_LCD_RESET); + stm32_configgpio(GPIO_LCD_DC); + + /* Reset the OLED display */ + + stm32_gpiowrite(GPIO_LCD_RESET, 0); + up_mdelay(1); + stm32_gpiowrite(GPIO_LCD_RESET, 1); + up_mdelay(120); + + ret = board_ssd1306_initialize(OLED_SPI_PORT); + if (ret < 0) + { + lcderr("ERROR: Failed to initialize SSD1306\n"); + return ret; + } + + return OK; +} + +/**************************************************************************** + * Name: board_lcd_getdev + ****************************************************************************/ + +struct lcd_dev_s *board_lcd_getdev(int devno) +{ + return board_ssd1306_getdev(); +} + +/**************************************************************************** + * Name: board_lcd_uninitialize + ****************************************************************************/ + +void board_lcd_uninitialize(void) +{ + /* TO-FIX */ +} diff --git a/boards/arm/stm32/stm32f401rc-rs485/src/stm32_lcd_st7735.c b/boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_lcd_st7735.c similarity index 98% rename from boards/arm/stm32/stm32f401rc-rs485/src/stm32_lcd_st7735.c rename to boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_lcd_st7735.c index 876e5b82346dc..bffad71e473ac 100644 --- a/boards/arm/stm32/stm32f401rc-rs485/src/stm32_lcd_st7735.c +++ b/boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_lcd_st7735.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f401rc-rs485/src/stm32_lcd_st7735.c + * boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_lcd_st7735.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_pwm.c b/boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_pwm.c new file mode 100644 index 0000000000000..2579135afcf3b --- /dev/null +++ b/boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_pwm.c @@ -0,0 +1,121 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_pwm.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32_pwm.h" +#include "stm32f401rc-rs485.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* PWM + * + * The STM32F401RC-RS485 has no real on-board PWM devices, but the board can + * be configured to output a pulse train using TIM3 CH1. + * + */ + +#define HAVE_PWM 1 + +#ifndef CONFIG_PWM +# undef HAVE_PWM +#endif + +#ifndef CONFIG_STM32_TIM3 +# undef HAVE_PWM +#endif + +#ifndef CONFIG_STM32_TIM3_PWM +# undef HAVE_PWM +#endif + +#if !defined(CONFIG_STM32_TIM3_CHANNEL) || CONFIG_STM32_TIM3_CHANNEL != STM32F401RCRS485_PWMCHANNEL +# undef HAVE_PWM +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_pwm_setup + * + * Description: + * Initialize PWM and register the PWM device. + * + ****************************************************************************/ + +int stm32_pwm_setup(void) +{ +#ifdef HAVE_PWM + static bool initialized = false; + struct pwm_lowerhalf_s *pwm; + int ret; + + /* Have we already initialized? */ + + if (!initialized) + { + /* Call stm32_pwminitialize() to get an instance of the PWM interface */ + + pwm = stm32_pwminitialize(STM32F401RCRS485_PWMTIMER); + if (!pwm) + { + aerr("ERROR: Failed to get the STM32 PWM lower half\n"); + return -ENODEV; + } + + /* Register the PWM driver at "/dev/pwm0" */ + + ret = pwm_register("/dev/pwm0", pwm); + if (ret < 0) + { + aerr("ERROR: pwm_register failed: %d\n", ret); + return ret; + } + + /* Now we are initialized */ + + initialized = true; + } + + return OK; +#else + return -ENODEV; +#endif +} diff --git a/boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_sdio.c b/boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_sdio.c new file mode 100644 index 0000000000000..959cc8637dbc5 --- /dev/null +++ b/boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_sdio.c @@ -0,0 +1,161 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_sdio.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include + +#include "stm32.h" +#include "stm32f401rc-rs485.h" + +#ifdef HAVE_SDIO + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* Card detections requires card support and a card detection GPIO */ + +#define HAVE_NCD 1 +#if !defined(HAVE_SDIO) || !defined(GPIO_SDIO_NCD) +# undef HAVE_NCD +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static struct sdio_dev_s *g_sdio_dev; +#ifdef HAVE_NCD +static bool g_sd_inserted; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_ncd_interrupt + * + * Description: + * Card detect interrupt handler. + * + ****************************************************************************/ + +#ifdef HAVE_NCD +static int stm32_ncd_interrupt(int irq, void *context, void *arg) +{ + bool present; + + present = !stm32_gpioread(GPIO_SDIO_NCD); + if (present != g_sd_inserted) + { + sdio_mediachange(g_sdio_dev, present); + g_sd_inserted = present; + } + + return OK; +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_sdio_initialize + * + * Description: + * Initialize SDIO-based MMC/SD card support + * + ****************************************************************************/ + +int stm32_sdio_initialize(void) +{ + int ret; + +#ifdef HAVE_NCD + /* Configure the card detect GPIO */ + + stm32_configgpio(GPIO_SDIO_NCD); + + /* Register an interrupt handler for the card detect pin */ + + stm32_gpiosetevent(GPIO_SDIO_NCD, true, true, true, + stm32_ncd_interrupt, NULL); +#endif + + /* Mount the SDIO-based MMC/SD block driver */ + + /* First, get an instance of the SDIO interface */ + + finfo("Initializing SDIO slot %d\n", SDIO_SLOTNO); + + g_sdio_dev = sdio_initialize(SDIO_SLOTNO); + if (!g_sdio_dev) + { + ferr("ERROR: Failed to initialize SDIO slot %d\n", SDIO_SLOTNO); + return -ENODEV; + } + + /* Now bind the SDIO interface to the MMC/SD driver */ + + finfo("Bind SDIO to the MMC/SD driver, minor=%d\n", SDIO_MINOR); + + ret = mmcsd_slotinitialize(SDIO_MINOR, g_sdio_dev); + if (ret != OK) + { + ferr("ERROR: Failed to bind SDIO to the MMC/SD driver: %d\n", ret); + return ret; + } + + finfo("Successfully bound SDIO to the MMC/SD driver\n"); + +#ifdef HAVE_NCD + /* Use SD card detect pin to check if a card is g_sd_inserted */ + + g_sd_inserted = !stm32_gpioread(GPIO_SDIO_NCD); + finfo("Card detect : %d\n", g_sd_inserted); + + sdio_mediachange(g_sdio_dev, g_sd_inserted); +#else + /* Assume that the SD card is inserted. What choice do we have? */ + + sdio_mediachange(g_sdio_dev, true); +#endif + + return OK; +} + +#endif /* HAVE_SDIO */ diff --git a/boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_spi.c b/boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_spi.c new file mode 100644 index 0000000000000..eef9dbcd0701f --- /dev/null +++ b/boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_spi.c @@ -0,0 +1,243 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_spi.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include + +#include "arm_internal.h" +#include "chip.h" +#include "stm32.h" +#include "stm32f401rc-rs485.h" + +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || \ + defined(CONFIG_STM32_SPI3) + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_spidev_initialize + * + * Description: + * Called to configure SPI chip select GPIO pins for the stm32f401rc-rs485 + * board. + * + ****************************************************************************/ + +void weak_function stm32_spidev_initialize(void) +{ +#if defined(CONFIG_LCD_SSD1306) || defined(CONFIG_LCD_ST7735) + stm32_configgpio(GPIO_LCD_CS); /* LCD chip select */ +#endif + +#ifdef CONFIG_LCD_MAX7219 + stm32_configgpio(STM32_LCD_CS); /* MAX7219 chip select */ +#endif + +#ifdef CONFIG_CL_MFRC522 + stm32_configgpio(GPIO_RFID_CS); /* MFRC522 chip select */ +#endif + +#if defined(CONFIG_STM32_SPI1) && defined(CONFIG_SENSORS_MAX31855) + stm32_configgpio(GPIO_MAX31855_CS); /* MAX31855 chip select */ +#endif + +#if defined(CONFIG_STM32_SPI1) && defined(CONFIG_SENSORS_MAX66755) + stm32_configgpio(GPIO_MAX6675_CS); /* MAX6675 chip select */ +#endif +} + +/**************************************************************************** + * Name: stm32_spi1/2/3select and stm32_spi1/2/3status + * + * Description: + * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status + * must be provided by board-specific logic. They are implementations of + * the select and status methods of the SPI interface defined by struct + * spi_ops_s (see include/nuttx/spi/spi.h). All other methods + * (including stm32_spibus_initialize()) are provided by common STM32 logic. + * To use this common SPI logic on your board: + * + * 1. Provide logic in stm32_boardinitialize() to configure SPI chip select + * pins. + * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() functions + * in your board-specific logic. These functions will perform chip + * selection and status operations using GPIOs in the way your board is + * configured. + * 3. Add a calls to stm32_spibus_initialize() in your low level + * application initialization logic + * 4. The handle returned by stm32_spibus_initialize() may then be used to + * bind the SPI driver to higher level logic (e.g., calling + * mmcsd_spislotinitialize(), for example, will bind the SPI driver to + * the SPI MMC/SD driver). + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_SPI1 +void stm32_spi1select(struct spi_dev_s *dev, + uint32_t devid, bool selected) +{ + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); + + #if defined(CONFIG_LCD_SSD1306) || defined(CONFIG_LCD_ST7735) + if (devid == SPIDEV_DISPLAY(0)) + { + stm32_gpiowrite(GPIO_LCD_CS, !selected); + } + #endif + + #ifdef CONFIG_LCD_MAX7219 + if (devid == SPIDEV_DISPLAY(0)) + { + stm32_gpiowrite(STM32_LCD_CS, !selected); + } + #endif + + #if defined(CONFIG_CL_MFRC522) + if (devid == SPIDEV_CONTACTLESS(0)) + { + stm32_gpiowrite(GPIO_RFID_CS, !selected); + } + #endif + + #if defined(CONFIG_SENSORS_MAX31855) + if (devid == SPIDEV_TEMPERATURE(0)) + { + stm32_gpiowrite(GPIO_MAX31855_CS, !selected); + } + #endif + + #if defined(CONFIG_SENSORS_MAX6675) + if (devid == SPIDEV_TEMPERATURE(0)) + { + stm32_gpiowrite(GPIO_MAX6675_CS, !selected); + } + #endif +} + +uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} +#endif + +#ifdef CONFIG_STM32_SPI2 +void stm32_spi2select(struct spi_dev_s *dev, + uint32_t devid, bool selected) +{ + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); +} + +uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} +#endif + +#ifdef CONFIG_STM32_SPI3 +void stm32_spi3select(struct spi_dev_s *dev, + uint32_t devid, bool selected) +{ + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); +} + +uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} +#endif + +/**************************************************************************** + * Name: stm32_spi1cmddata + * + * Description: + * Set or clear the SH1101A A0 or SD1306 D/C n bit to select data (true) + * or command (false). This function must be provided by platform-specific + * logic. This is an implementation of the cmddata method of the SPI + * interface defined by struct spi_ops_s (see include/nuttx/spi/spi.h). + * + * Input Parameters: + * + * spi - SPI device that controls the bus the device that requires the CMD/ + * DATA selection. + * devid - If there are multiple devices on the bus, this selects which one + * to select cmd or data. NOTE: This design restricts, for example, + * one one SPI display per SPI bus. + * cmd - true: select command; false: select data + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_SPI_CMDDATA +#ifdef CONFIG_STM32_SPI1 +int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) +{ +#if defined(CONFIG_LCD_SSD1306) || defined(CONFIG_LCD_ST7735) + if (devid == SPIDEV_DISPLAY(0)) + { + /* This is the Data/Command control pad which determines whether the + * data bits are data or a command. + */ + + stm32_gpiowrite(GPIO_LCD_DC, !cmd); + + return OK; + } +#endif + + return -ENODEV; +} +#endif + +#ifdef CONFIG_STM32_SPI2 +int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) +{ + return -ENODEV; +} +#endif + +#ifdef CONFIG_STM32_SPI3 +int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) +{ + return -ENODEV; +} +#endif +#endif /* CONFIG_SPI_CMDDATA */ + +#endif /* CONFIG_STM32_SPI1 || CONFIG_STM32_SPI2 */ diff --git a/boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_usb.c b/boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_usb.c new file mode 100644 index 0000000000000..c9ad90a99763c --- /dev/null +++ b/boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_usb.c @@ -0,0 +1,94 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_usb.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include "stm32_otgfs.h" +#include "stm32_gpio.h" +#include "stm32f401rc-rs485.h" + +#ifdef CONFIG_STM32_OTGFS + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifdef CONFIG_USBDEV +# define HAVE_USB 1 +#else +# warning "CONFIG_STM32_OTGFS is enabled but CONFIG_USBDEV is not" +# undef HAVE_USB +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_usb_configure + * + * Description: + * Called from stm32_boardinitialize very early in initialization to setup + * USB-related GPIO pins for the Olimex STM32 P407 board. + * + ****************************************************************************/ + +void stm32_usb_configure(void) +{ +#ifdef CONFIG_STM32_OTGFS + /* The OTG FS has an internal soft pull-up. + * No GPIO configuration is required + */ + + /* We don´t have the OTG FS VBUS sensing GPIO */ +#endif +} + +/**************************************************************************** + * Name: stm32_usbsuspend + * + * Description: + * Board logic must provide the stm32_usbsuspend logic if the USBDEV + * driver is used. This function is called whenever the USB enters or + * leaves suspend mode. + * This is an opportunity for the board logic to shutdown clocks, power, + * etc. while the USB is suspended. + * + ****************************************************************************/ + +#ifdef CONFIG_USBDEV +void stm32_usbsuspend(struct usbdev_s *dev, bool resume) +{ + uinfo("resume: %d\n", resume); +} +#endif + +#endif /* CONFIG_STM32_OTGFS */ diff --git a/boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_usbmsc.c b/boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_usbmsc.c new file mode 100644 index 0000000000000..506a30b7e7937 --- /dev/null +++ b/boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_usbmsc.c @@ -0,0 +1,71 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_usbmsc.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include + +#include "stm32.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +#ifndef CONFIG_SYSTEM_USBMSC_DEVMINOR1 +# define CONFIG_SYSTEM_USBMSC_DEVMINOR1 0 +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_usbmsc_initialize + * + * Description: + * Perform architecture specific initialization of the USB MSC device. + * + ****************************************************************************/ + +int board_usbmsc_initialize(int port) +{ + /* If system/usbmsc is built as an NSH command, then SD slot should + * already have been initialized. + * In this case, there is nothing further to be done here. + */ + +#ifndef CONFIG_NSH_BUILTIN_APPS + return stm32_mmcsd_initialize(port, CONFIG_SYSTEM_USBMSC_DEVMINOR1); +#else + return OK; +#endif +} diff --git a/boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_userleds.c b/boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_userleds.c new file mode 100644 index 0000000000000..7b97b71c8ece8 --- /dev/null +++ b/boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_userleds.c @@ -0,0 +1,216 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_userleds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32.h" +#include "stm32f401rc-rs485.h" + +#ifndef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* This array maps an LED number to GPIO pin configuration */ + +static uint32_t g_ledcfg[BOARD_NLEDS] = +{ + GPIO_LED1, GPIO_LED2, GPIO_LED3, GPIO_LED4 +}; + +/**************************************************************************** + * Private Function Protototypes + ****************************************************************************/ + +/* LED Power Management */ + +#ifdef CONFIG_PM +static void led_pm_notify(struct pm_callback_s *cb, int domain, + enum pm_state_e pmstate); +static int led_pm_prepare(struct pm_callback_s *cb, int domain, + enum pm_state_e pmstate); +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#ifdef CONFIG_PM +static struct pm_callback_s g_ledscb = +{ + .notify = led_pm_notify, + .prepare = led_pm_prepare, +}; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: led_pm_notify + * + * Description: + * Notify the driver of new power state. This callback is called after + * all drivers have had the opportunity to prepare for the new power state. + * + ****************************************************************************/ + +#ifdef CONFIG_PM +static void led_pm_notify(struct pm_callback_s *cb, int domain, + enum pm_state_e pmstate) +{ + switch (pmstate) + { + case PM_NORMAL: + { + /* Restore normal LEDs operation */ + } + break; + + case PM_IDLE: + { + /* Entering IDLE mode - Turn leds off */ + } + break; + + case PM_STANDBY: + { + /* Entering STANDBY mode - Logic for PM_STANDBY goes here */ + } + break; + + case PM_SLEEP: + { + /* Entering SLEEP mode - Logic for PM_SLEEP goes here */ + } + break; + + default: + { + /* Should not get here */ + } + break; + } +} +#endif + +/**************************************************************************** + * Name: led_pm_prepare + * + * Description: + * Request the driver to prepare for a new power state. This is a warning + * that the system is about to enter into a new power state. The driver + * should begin whatever operations that may be required to enter power + * state. The driver may abort the state change mode by returning a + * non-zero value from the callback function. + * + ****************************************************************************/ + +#ifdef CONFIG_PM +static int led_pm_prepare(struct pm_callback_s *cb, int domain, + enum pm_state_e pmstate) +{ + /* No preparation to change power modes is required by the LEDs driver. + * We always accept the state change by returning OK. + */ + + return OK; +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_userled_initialize + ****************************************************************************/ + +uint32_t board_userled_initialize(void) +{ + /* Configure LED1-4 GPIOs for output */ + + stm32_configgpio(GPIO_LED1); + stm32_configgpio(GPIO_LED2); + stm32_configgpio(GPIO_LED3); + stm32_configgpio(GPIO_LED4); + return BOARD_NLEDS; +} + +/**************************************************************************** + * Name: board_userled + ****************************************************************************/ + +void board_userled(int led, bool ledon) +{ + if ((unsigned)led < BOARD_NLEDS) + { + stm32_gpiowrite(g_ledcfg[led], ledon); + } +} + +/**************************************************************************** + * Name: board_userled_all + ****************************************************************************/ + +void board_userled_all(uint32_t ledset) +{ + stm32_gpiowrite(GPIO_LED1, (ledset & BOARD_LED1_BIT) != 0); + stm32_gpiowrite(GPIO_LED2, (ledset & BOARD_LED2_BIT) != 0); + stm32_gpiowrite(GPIO_LED3, (ledset & BOARD_LED3_BIT) != 0); + stm32_gpiowrite(GPIO_LED4, (ledset & BOARD_LED4_BIT) != 0); +} + +/**************************************************************************** + * Name: stm32_led_pminitialize + ****************************************************************************/ + +#ifdef CONFIG_PM +void stm32_led_pminitialize(void) +{ + /* Register to receive power management callbacks */ + + int ret = pm_register(&g_ledscb); + if (ret != OK) + { + board_autoled_on(LED_ASSERTION); + } +} +#endif /* CONFIG_PM */ + +#endif /* !CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/stm32f401rc-rs485/src/stm32f401rc-rs485.h b/boards/arm/stm32f4/stm32f401rc-rs485/src/stm32f401rc-rs485.h similarity index 99% rename from boards/arm/stm32/stm32f401rc-rs485/src/stm32f401rc-rs485.h rename to boards/arm/stm32f4/stm32f401rc-rs485/src/stm32f401rc-rs485.h index b8fbec7e25a6d..f6065bbdb8c63 100644 --- a/boards/arm/stm32/stm32f401rc-rs485/src/stm32f401rc-rs485.h +++ b/boards/arm/stm32f4/stm32f401rc-rs485/src/stm32f401rc-rs485.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f401rc-rs485/src/stm32f401rc-rs485.h + * boards/arm/stm32f4/stm32f401rc-rs485/src/stm32f401rc-rs485.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f4/stm32f411-minimum/CMakeLists.txt b/boards/arm/stm32f4/stm32f411-minimum/CMakeLists.txt new file mode 100644 index 0000000000000..f4b26f4eddd51 --- /dev/null +++ b/boards/arm/stm32f4/stm32f411-minimum/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32f4/stm32f411-minimum/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/arm/stm32f4/stm32f411-minimum/Kconfig b/boards/arm/stm32f4/stm32f411-minimum/Kconfig new file mode 100644 index 0000000000000..44ee6a9040708 --- /dev/null +++ b/boards/arm/stm32f4/stm32f411-minimum/Kconfig @@ -0,0 +1,86 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# + +if ARCH_BOARD_STM32F411_MINIMUM + +config STM32F411MINIMUM_USBHOST_STACKSIZE + int "USB host waiter stack size" + default 1024 + depends on USBHOST + +config STM32F411MINIMUM_USBHOST_PRIO + int "USB host waiter task priority" + default 100 + depends on USBHOST + +config STM32F411MINIMUM_FLASH + bool "MTD driver for external 8Mbyte W25Q64FV FLASH on SPI1" + default n + select MTD + select MTD_W25 + select MTD_SMART + select FS_SMARTFS + select STM32_SPI1 + select MTD_BYTE_WRITE + ---help--- + Configures an MTD device for use with the onboard flash + +config STM32F411MINIMUM_FLASH_MINOR + int "Minor number for the FLASH /dev/smart entry" + default 0 + depends on STM32F411MINIMUM_FLASH + ---help--- + Sets the minor number for the FLASH MTD /dev entry + +menuconfig STM32F411MINIMUM_HX711 + bool "Enable hx711 scale sensor" + default n + select ADC_HX711 + +if STM32F411MINIMUM_HX711 + +choice + prompt "Select GPIO port for clock pin" + default STM32F411MINIMUM_HX711_CLK_PORTA + +config STM32F411MINIMUM_HX711_CLK_PORTA + bool "Port A" +config STM32F411MINIMUM_HX711_CLK_PORTB + bool "Port B" + +endchoice # Select GPIO port for clock pin + +config STM32F411MINIMUM_HX711_CLK_PIN + int "Select GPIO pin number for clock pin" + default 1 + range 0 15 + +choice + prompt "Select GPIO port for data pin" + default STM32F411MINIMUM_HX711_DATA_PORTA + +config STM32F411MINIMUM_HX711_DATA_PORTA + bool "Port A" +config STM32F411MINIMUM_HX711_DATA_PORTB + bool "Port B" + +endchoice # Select GPIO port for data pin + +config STM32F411MINIMUM_HX711_DATA_PIN + int "Select GPIO pin number for data pin" + default 2 + range 0 15 + +endif # STM32F411MINIMUM_HX711 + +menuconfig STM32F411MINIMUM_GPIO + select DEV_GPIO + bool "enable gpio subsystem" + +if STM32F411MINIMUM_GPIO +source "boards/arm/stm32f4/stm32f411-minimum/Kconfig.gpio" +endif + +endif diff --git a/boards/arm/stm32/stm32f411-minimum/Kconfig.gpio b/boards/arm/stm32f4/stm32f411-minimum/Kconfig.gpio similarity index 100% rename from boards/arm/stm32/stm32f411-minimum/Kconfig.gpio rename to boards/arm/stm32f4/stm32f411-minimum/Kconfig.gpio diff --git a/boards/arm/stm32f4/stm32f411-minimum/configs/composite/defconfig b/boards/arm/stm32f4/stm32f411-minimum/configs/composite/defconfig new file mode 100644 index 0000000000000..f7e74ef5eb194 --- /dev/null +++ b/boards/arm/stm32f4/stm32f411-minimum/configs/composite/defconfig @@ -0,0 +1,67 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_DISABLE_OS_API is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_STM32_SYSCFG is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f411-minimum" +CONFIG_ARCH_BOARD_STM32F411_MINIMUM=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F411CE=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=8499 +CONFIG_BUILTIN=y +CONFIG_CDCACM=y +CONFIG_CDCACM_COMPOSITE=y +CONFIG_COMPOSITE_IAD=y +CONFIG_COMPOSITE_PRODUCTID=0x2022 +CONFIG_COMPOSITE_VENDORID=0x03eb +CONFIG_HAVE_CXX=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_DISABLE_LOSMART=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_OTG_ID_GPIO_DISABLE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=131072 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=2 +CONFIG_START_MONTH=4 +CONFIG_START_YEAR=2023 +CONFIG_STM32F411MINIMUM_FLASH=y +CONFIG_STM32_FLASH_CONFIG_E=y +CONFIG_STM32_FLASH_PREFETCH=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_USART1=y +CONFIG_SYSTEM_CDCACM=y +CONFIG_SYSTEM_COMPOSITE=y +CONFIG_SYSTEM_NSH=y +CONFIG_SYSTEM_USBMSC=y +CONFIG_SYSTEM_USBMSC_DEVMINOR1=0 +CONFIG_SYSTEM_USBMSC_DEVPATH1="/dev/smart0" +CONFIG_TASK_NAME_SIZE=15 +CONFIG_USART1_SERIAL_CONSOLE=y +CONFIG_USBDEV=y +CONFIG_USBDEV_BUSPOWERED=y +CONFIG_USBDEV_COMPOSITE=y +CONFIG_USBMSC=y +CONFIG_USBMSC_COMPOSITE=y diff --git a/boards/arm/stm32f4/stm32f411-minimum/configs/nsh/defconfig b/boards/arm/stm32f4/stm32f411-minimum/configs/nsh/defconfig new file mode 100644 index 0000000000000..6d7961ef2fa3c --- /dev/null +++ b/boards/arm/stm32f4/stm32f411-minimum/configs/nsh/defconfig @@ -0,0 +1,47 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_DISABLE_OS_API is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_STM32_SYSCFG is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f411-minimum" +CONFIG_ARCH_BOARD_STM32F411_MINIMUM=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F411CE=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=8499 +CONFIG_BUILTIN=y +CONFIG_HAVE_CXX=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=131072 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=6 +CONFIG_START_YEAR=2020 +CONFIG_STM32_FLASH_CONFIG_E=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_USART1=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f4/stm32f411-minimum/configs/pwm/defconfig b/boards/arm/stm32f4/stm32f411-minimum/configs/pwm/defconfig new file mode 100644 index 0000000000000..6d7545748b8b7 --- /dev/null +++ b/boards/arm/stm32f4/stm32f411-minimum/configs/pwm/defconfig @@ -0,0 +1,53 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_DISABLE_OS_API is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_STM32_SYSCFG is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f411-minimum" +CONFIG_ARCH_BOARD_STM32F411_MINIMUM=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F411CE=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=8499 +CONFIG_BUILTIN=y +CONFIG_EXAMPLES_PWM=y +CONFIG_HAVE_CXX=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_PWM=y +CONFIG_RAM_SIZE=131072 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=6 +CONFIG_START_YEAR=2020 +CONFIG_STM32_FLASH_CONFIG_E=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_TIM3=y +CONFIG_STM32_TIM3_CH3OUT=y +CONFIG_STM32_TIM3_CHANNEL=3 +CONFIG_STM32_TIM3_PWM=y +CONFIG_STM32_USART1=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f4/stm32f411-minimum/configs/rgbled/defconfig b/boards/arm/stm32f4/stm32f411-minimum/configs/rgbled/defconfig new file mode 100644 index 0000000000000..cadadfaea585d --- /dev/null +++ b/boards/arm/stm32f4/stm32f411-minimum/configs/rgbled/defconfig @@ -0,0 +1,70 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_DISABLE_OS_API is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_STM32_SYSCFG is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f411-minimum" +CONFIG_ARCH_BOARD_STM32F411_MINIMUM=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F411CE=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=8499 +CONFIG_BUILTIN=y +CONFIG_EXAMPLES_RGBLED=y +CONFIG_HAVE_CXX=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_PWM=y +CONFIG_PWM_NCHANNELS=3 +CONFIG_RAM_SIZE=131072 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RGBLED=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=6 +CONFIG_START_YEAR=2020 +CONFIG_STM32_FLASH_CONFIG_E=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_TIM1=y +CONFIG_STM32_TIM1_CH1OUT=y +CONFIG_STM32_TIM1_CHMODE=0 +CONFIG_STM32_TIM1_PWM=y +CONFIG_STM32_TIM2=y +CONFIG_STM32_TIM2_CH2OUT=y +CONFIG_STM32_TIM2_CHANNEL=2 +CONFIG_STM32_TIM2_CHMODE=0 +CONFIG_STM32_TIM2_PWM=y +CONFIG_STM32_TIM3=y +CONFIG_STM32_TIM3_CH3OUT=y +CONFIG_STM32_TIM3_CHANNEL=3 +CONFIG_STM32_TIM3_CHMODE=0 +CONFIG_STM32_TIM3_PWM=y +CONFIG_STM32_TIM4=y +CONFIG_STM32_TIM4_CH4OUT=y +CONFIG_STM32_TIM4_CHANNEL=4 +CONFIG_STM32_TIM4_CHMODE=0 +CONFIG_STM32_TIM4_PWM=y +CONFIG_STM32_USART1=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f4/stm32f411-minimum/configs/spifsnsh/defconfig b/boards/arm/stm32f4/stm32f411-minimum/configs/spifsnsh/defconfig new file mode 100644 index 0000000000000..d9edd314500c6 --- /dev/null +++ b/boards/arm/stm32f4/stm32f411-minimum/configs/spifsnsh/defconfig @@ -0,0 +1,50 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_DISABLE_OS_API is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_STM32_SYSCFG is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f411-minimum" +CONFIG_ARCH_BOARD_STM32F411_MINIMUM=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F411CE=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=8499 +CONFIG_BUILTIN=y +CONFIG_HAVE_CXX=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_DISABLE_LOSMART=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=131072 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=2 +CONFIG_START_MONTH=4 +CONFIG_START_YEAR=2023 +CONFIG_STM32F411MINIMUM_FLASH=y +CONFIG_STM32_FLASH_CONFIG_E=y +CONFIG_STM32_FLASH_PREFETCH=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_USART1=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=15 +CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f4/stm32f411-minimum/configs/usbmsc/defconfig b/boards/arm/stm32f4/stm32f411-minimum/configs/usbmsc/defconfig new file mode 100644 index 0000000000000..825535f82171a --- /dev/null +++ b/boards/arm/stm32f4/stm32f411-minimum/configs/usbmsc/defconfig @@ -0,0 +1,58 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_DISABLE_OS_API is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_STM32_SYSCFG is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f411-minimum" +CONFIG_ARCH_BOARD_STM32F411_MINIMUM=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F411CE=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=8499 +CONFIG_BUILTIN=y +CONFIG_HAVE_CXX=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_DISABLE_LOSMART=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_OTG_ID_GPIO_DISABLE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=131072 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=2 +CONFIG_START_MONTH=4 +CONFIG_START_YEAR=2023 +CONFIG_STM32F411MINIMUM_FLASH=y +CONFIG_STM32_FLASH_CONFIG_E=y +CONFIG_STM32_FLASH_PREFETCH=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_USART1=y +CONFIG_SYSTEM_NSH=y +CONFIG_SYSTEM_USBMSC=y +CONFIG_SYSTEM_USBMSC_DEVMINOR1=0 +CONFIG_SYSTEM_USBMSC_DEVPATH1="/dev/smart0" +CONFIG_TASK_NAME_SIZE=15 +CONFIG_USART1_SERIAL_CONSOLE=y +CONFIG_USBDEV=y +CONFIG_USBDEV_BUSPOWERED=y +CONFIG_USBMSC=y diff --git a/boards/arm/stm32f4/stm32f411-minimum/include/board.h b/boards/arm/stm32f4/stm32f411-minimum/include/board.h new file mode 100644 index 0000000000000..c90a3ade986b2 --- /dev/null +++ b/boards/arm/stm32f4/stm32f411-minimum/include/board.h @@ -0,0 +1,363 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f411-minimum/include/board.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_STM32_STM32F411_MINIMUM_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32_STM32F411_MINIMUM_INCLUDE_BOARD_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#ifndef __ASSEMBLY__ +# include +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Clocking *****************************************************************/ + +/* System Clock source : PLLCLK (HSE) + * SYSCLK(Hz) : 96000000 Determined by PLL config + * HCLK(Hz) : 96000000 (STM32_RCC_CFGR_HPRE) + * AHB Prescaler : 1 (STM32_RCC_CFGR_HPRE) + * APB1 Prescaler : 4 (STM32_RCC_CFGR_PPRE1) + * APB2 Prescaler : 2 (STM32_RCC_CFGR_PPRE2) + * HSI Frequency(Hz) : 16000000 (nominal) + * PLLM : 4 (STM32_PLLCFG_PLLM) + * PLLN : 192 (STM32_PLLCFG_PLLN) + * PLLP : 4 (STM32_PLLCFG_PLLP) + * PLLQ : 8 (STM32_PLLCFG_PPQ) + * Flash Latency(WS) : 3 + * Prefetch Buffer : OFF + * Instruction cache : ON + * Data cache : ON + * Require 48MHz for USB OTG FS, : Enabled + * SDIO and RNG clock + */ + +/* HSI - 16 MHz RC factory-trimmed + * LSI - 32 KHz RC + * HSE - 25 MHz Crystal + * LSE - 32 KHz Crystal + */ + +#define STM32_BOARD_XTAL 25000000ul + +#define STM32_HSI_FREQUENCY 16000000ul +#define STM32_LSI_FREQUENCY 32000 +#define STM32_LSE_FREQUENCY 32768 +#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL + +/* Main PLL Configuration. + * + * Formulae: + * + * VCO input freq = PLL input clock freq/PLLM 2 <= PLLM <= 63 + * VCO output freq = VCO input freq × PLLN, 192 <= PLLN <= 432 + * PLL output clock freq = VCO freq / PLLP, PLLP = 2,4,6 or 8 + * USB OTG FS clock freq = VCO freq / PLLQ, 2 <= PLLQ <= 15 + * + * There is no config for 100 MHz and 48 MHz for usb, + * so we would like to have SYSYCLK=96MHz and we must have the USB + * clock = 48MHz + * + * PLLQ = 2 PLLP = 2 PLLN=192 PLLM=25 + * + * We will configure like this + * + * PLL source is HSE + * PLL_VCO = (STM32_HSE_FREQUENCY / PLLM) * PLLN + * = (25,000,000 / 25) * 192 + * = 192,000,000 + * SYSCLK = PLL_VCO / PLLP + * = 192,000,000 / 2 = 96,000,000 + * USB OTG FS and SDIO Clock + * = PLL_VCO / PLLQ + * = 96,000,000 / 2 = 48,000,000 + */ + +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(25) +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(192) +#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_2 +#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(2) + +#define STM32_SYSCLK_FREQUENCY 96000000ul + +/* AHB clock (HCLK) is SYSCLK (96MHz) */ + +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY + +/* APB1 clock (PCLK1) is HCLK/4 (24MHz) */ + +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd4 /* PCLK1 = HCLK / 4 */ +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/4) + +/* Timers driven from APB1 will be twice PCLK1 */ + +/* REVISIT */ + +#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) + +/* APB2 clock (PCLK2) is HCLK (48MHz) */ + +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLKd2 /* PCLK2 = HCLK / 2 */ +#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/2) + +/* Timers driven from APB2 will be twice PCLK2 */ + +#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM9_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB2_TIM10_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB2_TIM11_CLKIN (2*STM32_PCLK1_FREQUENCY) + +/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx + * otherwise frequency is 2xAPBx. + * Note: TIM1,8 are on APB2, others on APB1 + */ + +/* REVISIT */ + +#define BOARD_TIM1_FREQUENCY (2 * STM32_PCLK2_FREQUENCY) +#define BOARD_TIM2_FREQUENCY (2 * STM32_PCLK1_FREQUENCY) +#define BOARD_TIM3_FREQUENCY (2 * STM32_PCLK1_FREQUENCY) +#define BOARD_TIM4_FREQUENCY (2 * STM32_PCLK1_FREQUENCY) +#define BOARD_TIM5_FREQUENCY (2 * STM32_PCLK1_FREQUENCY) +#define BOARD_TIM6_FREQUENCY (2 * STM32_PCLK1_FREQUENCY) +#define BOARD_TIM7_FREQUENCY (2 * STM32_PCLK1_FREQUENCY) +#define BOARD_TIM8_FREQUENCY (2 * STM32_PCLK2_FREQUENCY) + +/* SDIO dividers. Note that slower clocking is required when DMA is disabled + * in order to avoid RX overrun/TX underrun errors due to delayed responses + * to service FIFOs in interrupt driven mode. These values have not been + * tuned!!! + * + * HCLK=72MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(178+2)=400 KHz + */ + +/* REVISIT */ + +#define SDIO_INIT_CLKDIV (178 << SDIO_CLKCR_CLKDIV_SHIFT) + +/* DMA ON: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(2+2)=18 MHz + * DMA OFF: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(3+2)=14.4 MHz + */ + +/* REVISIT */ + +#ifdef CONFIG_SDIO_DMA +# define SDIO_MMCXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT) +#else +# define SDIO_MMCXFR_CLKDIV (3 << SDIO_CLKCR_CLKDIV_SHIFT) +#endif + +/* DMA ON: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(1+2)=24 MHz + * DMA OFF: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(3+2)=14.4 MHz + */ + +/* REVISIT */ + +#ifdef CONFIG_SDIO_DMA +# define SDIO_SDXFR_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT) +#else +# define SDIO_SDXFR_CLKDIV (3 << SDIO_CLKCR_CLKDIV_SHIFT) +#endif + +/* DMA Channel/Stream Selections ********************************************/ + +/* Stream selections are arbitrary for now but might become important in the + * future is we set aside more DMA channels/streams. + * + * SDIO DMA + *   DMAMAP_SDIO_1 = Channel 4, Stream 3 <- may later be used by SPI DMA + *   DMAMAP_SDIO_2 = Channel 4, Stream 6 + */ + +#define DMAMAP_SDIO DMAMAP_SDIO_1 + +/* Need to VERIFY fwb */ + +#define DMACHAN_SPI1_RX DMAMAP_SPI1_RX_1 +#define DMACHAN_SPI1_TX DMAMAP_SPI1_TX_1 +#define DMACHAN_SPI2_RX DMAMAP_SPI2_RX +#define DMACHAN_SPI2_TX DMAMAP_SPI2_TX + +/* Alternate function pin selections ****************************************/ + +/* USART1: + * RXD: PA10 CN9 pin 3, CN10 pin 33 + * PB7 CN7 pin 21 + * TXD: PA9 CN5 pin 1, CN10 pin 21 + * PB6 CN5 pin 3, CN10 pin 17 + */ + +#if 1 +# define GPIO_USART1_RX (GPIO_USART1_RX_1|GPIO_SPEED_100MHz) /* PA10 */ +# define GPIO_USART1_TX (GPIO_USART1_TX_1|GPIO_SPEED_100MHz) /* PA9 */ +#else +# define GPIO_USART1_RX (GPIO_USART1_RX_2|GPIO_SPEED_100MHz) /* PB7 */ +# define GPIO_USART1_TX (GPIO_USART1_TX_2|GPIO_SPEED_100MHz) /* PB6 */ +#endif + +/* USART2: + * RXD: PA3 CN9 pin 1 (See SB13, 14, 62, 63). CN10 pin 37 + * PD6 + * TXD: PA2 CN9 pin 2(See SB13, 14, 62, 63). CN10 pin 35 + * PD5 + */ + +#define GPIO_USART2_RX (GPIO_USART2_RX_1|GPIO_SPEED_100MHz) /* PA3 */ +#define GPIO_USART2_TX (GPIO_USART2_TX_1|GPIO_SPEED_100MHz) /* PA2 */ +#define GPIO_USART2_RTS GPIO_USART2_RTS_2 +#define GPIO_USART2_CTS GPIO_USART2_CTS_2 + +/* USART6: + * RXD: PC7 CN5 pin2, CN10 pin 19 + * PA12 CN10, pin 12 + * TXD: PC6 CN10, pin 4 + * PA11 CN10, pin 14 + */ + +#define GPIO_USART6_RX (GPIO_USART6_RX_1|GPIO_SPEED_100MHz) /* PC7 */ +#define GPIO_USART6_TX (GPIO_USART6_TX_1|GPIO_SPEED_100MHz) /* PC6 */ + +/* PWM + * + * The STM32F4 Discovery has no real on-board PWM devices, but the board + * can be configured to output a pulse train using TIM4 CH2 on PD13. + */ +#define GPIO_TIM1_CH1OUT (GPIO_TIM1_CH1OUT_1|GPIO_SPEED_50MHz) //PA8 +#define GPIO_TIM2_CH2OUT (GPIO_TIM2_CH2OUT_1|GPIO_SPEED_50MHz) //PA1 +#define GPIO_TIM3_CH3OUT (GPIO_TIM3_CH3OUT_1|GPIO_SPEED_50MHz) //PB0 +#define GPIO_TIM4_CH4OUT (GPIO_TIM4_CH4OUT_1|GPIO_SPEED_50MHz) //PB9 + +/* RGB LED + * + * R = TIM1 CH1 on PA8 | G = TIM2 CH2 on PA1 | B = TIM4 CH4 on PB9 + * + * Note: Pin boards: GPIO_TIM1_CH1OUT ; GPIO_TIM2_CH2OUT ; GPIO_TIM4_CH4OUT + */ + +#define RGBLED_RPWMTIMER 1 +#define RGBLED_RPWMCHANNEL 1 +#define RGBLED_GPWMTIMER 2 +#define RGBLED_GPWMCHANNEL 2 +#define RGBLED_BPWMTIMER 4 +#define RGBLED_BPWMCHANNEL 4 + +/* UART RX DMA configurations */ + +#define DMAMAP_USART1_RX DMAMAP_USART1_RX_2 +#define DMAMAP_USART6_RX DMAMAP_USART6_RX_2 + +/* I2C + * + * The optional _GPIO configurations allow the I2C driver to manually + * reset the bus to clear stuck slaves. They match the pin configuration, + * but are normally-high GPIOs. + */ + +#define GPIO_I2C1_SCL (GPIO_I2C1_SCL_2|GPIO_SPEED_50MHz) +#define GPIO_I2C1_SDA (GPIO_I2C1_SDA_2|GPIO_SPEED_50MHz) +#define GPIO_I2C1_SCL_GPIO \ + (GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTB|GPIO_PIN8) +#define GPIO_I2C1_SDA_GPIO \ + (GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTB|GPIO_PIN9) + +#define GPIO_I2C2_SCL (GPIO_I2C2_SCL_1|GPIO_SPEED_50MHz) +#define GPIO_I2C2_SDA (GPIO_I2C2_SDA_1|GPIO_SPEED_50MHz) +#define GPIO_I2C2_SCL_GPIO \ + (GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTB|GPIO_PIN10) +#define GPIO_I2C2_SDA_GPIO \ + (GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTB|GPIO_PIN11) + +/* SPI + * + * There are sensors on SPI1, and SPI2 is connected to the FRAM. + */ + +#define GPIO_SPI1_MISO (GPIO_SPI1_MISO_1|GPIO_SPEED_50MHz) +#define GPIO_SPI1_MOSI (GPIO_SPI1_MOSI_1|GPIO_SPEED_50MHz) +#define GPIO_SPI1_SCK (GPIO_SPI1_SCK_1|GPIO_SPEED_50MHz) + +#define GPIO_SPI2_MISO (GPIO_SPI2_MISO_1|GPIO_SPEED_50MHz) +#define GPIO_SPI2_MOSI (GPIO_SPI2_MOSI_1|GPIO_SPEED_50MHz) +#define GPIO_SPI2_SCK (GPIO_SPI2_SCK_2|GPIO_SPEED_50MHz) + +/* LEDs + * + * The STM32F411-Minimum (aka BlackPill) has a LED on PC13 pin. + */ + +/* The board has only one controllable LED */ + +#define LED_STARTED 0 /* No LEDs */ +#define LED_HEAPALLOCATE 1 /* LED1 on */ +#define LED_IRQSENABLED 2 /* LED1 on */ +#define LED_STACKCREATED 3 /* LED1 on */ +#define LED_INIRQ 4 /* LED1 on */ +#define LED_SIGNAL 5 /* LED1 on */ +#define LED_ASSERTION 6 /* LED1 on */ +#define LED_PANIC 7 /* LED1 blinking */ + +/* LED index values for use with board_userled() */ + +#define BOARD_LED1 0 +#define BOARD_NLEDS 1 + +/* LED bits for use with board_userled_all() */ + +#define BOARD_LED1_BIT (1 << BOARD_LED1) + +/* Buttons + * + * B1 USER: the user button is connected to the I/O PA0 of the STM32 + * microcontroller. + */ + +#define BUTTON_USER 0 +#define BUTTON_EXTERNAL 1 //External user button connected to PA1 +#define NUM_BUTTONS 2 + +#define BUTTON_USER_BIT (1 << BUTTON_USER) +#define BUTTON_EXTERNAL_BIT (1 << BUTTON_EXTERNAL) + +/* USB OTG FS */ + +#define GPIO_OTGFS_DM (GPIO_OTGFS_DM_0|GPIO_SPEED_100MHz) +#define GPIO_OTGFS_DP (GPIO_OTGFS_DP_0|GPIO_SPEED_100MHz) +#define GPIO_OTGFS_ID (GPIO_OTGFS_ID_0|GPIO_SPEED_100MHz) +#define GPIO_OTGFS_SOF (GPIO_OTGFS_SOF_0|GPIO_SPEED_100MHz) + +#endif /* __BOARDS_ARM_STM32_STM32F411_MINIMUM_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32f4/stm32f411-minimum/scripts/Make.defs b/boards/arm/stm32f4/stm32f411-minimum/scripts/Make.defs new file mode 100644 index 0000000000000..15e53eadfbdfe --- /dev/null +++ b/boards/arm/stm32f4/stm32f411-minimum/scripts/Make.defs @@ -0,0 +1,41 @@ +############################################################################ +# boards/arm/stm32f4/stm32f411-minimum/scripts/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/.config +include $(TOPDIR)/tools/Config.mk +include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs + +LDSCRIPT = stm32f411ce.ld +ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) + +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32/stm32f411-minimum/scripts/stm32f411ce.ld b/boards/arm/stm32f4/stm32f411-minimum/scripts/stm32f411ce.ld similarity index 98% rename from boards/arm/stm32/stm32f411-minimum/scripts/stm32f411ce.ld rename to boards/arm/stm32f4/stm32f411-minimum/scripts/stm32f411ce.ld index b5b77c8a49bb2..58afcc5198500 100644 --- a/boards/arm/stm32/stm32f411-minimum/scripts/stm32f411ce.ld +++ b/boards/arm/stm32f4/stm32f411-minimum/scripts/stm32f411ce.ld @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f411-minimum/scripts/stm32f411ce.ld + * boards/arm/stm32f4/stm32f411-minimum/scripts/stm32f411ce.ld * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f4/stm32f411-minimum/src/CMakeLists.txt b/boards/arm/stm32f4/stm32f411-minimum/src/CMakeLists.txt new file mode 100644 index 0000000000000..0b5473d5b55e5 --- /dev/null +++ b/boards/arm/stm32f4/stm32f411-minimum/src/CMakeLists.txt @@ -0,0 +1,76 @@ +# ############################################################################## +# boards/arm/stm32f4/stm32f411-minimum/src/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(SRCS stm32_boot.c stm32_bringup.c) + +if(CONFIG_ARCH_LEDS) + list(APPEND SRCS stm32_autoleds.c) +endif() + +if(CONFIG_USERLED) + list(APPEND SRCS stm32_userleds.c) +endif() + +if(CONFIG_ARCH_BUTTONS) + list(APPEND SRCS stm32_buttons.c) +endif() + +if(CONFIG_PWM) + list(APPEND SRCS stm32_pwm.c) +endif() + +if(CONFIG_RGBLED) + list(APPEND SRCS stm32_rgbled.c) +endif() + +if(CONFIG_SPI) + list(APPEND SRCS stm32_spi.c) +endif() + +if(CONFIG_MTD_W25) + list(APPEND SRCS stm32_w25.c) +endif() + +if(CONFIG_STM32_OTGFS) + list(APPEND SRCS stm32_usb.c) +endif() + +if(CONFIG_USBDEV_COMPOSITE) + list(APPEND SRCS stm32_composite.c) +endif() + +if(CONFIG_STM32F411MINIMUM_GPIO) + list(APPEND SRCS stm32_gpio.c) +endif() + +if(CONFIG_USBMSC) + list(APPEND SRCS stm32_usbmsc.c) +endif() + +if(CONFIG_ADC_HX711) + list(APPEND SRCS stm32_hx711.c) +endif() + +target_sources(board PRIVATE ${SRCS}) + +set_property(GLOBAL PROPERTY LD_SCRIPT + "${NUTTX_BOARD_DIR}/scripts/stm32f411ce.ld") diff --git a/boards/arm/stm32f4/stm32f411-minimum/src/Make.defs b/boards/arm/stm32f4/stm32f411-minimum/src/Make.defs new file mode 100644 index 0000000000000..dcda7c6643082 --- /dev/null +++ b/boards/arm/stm32f4/stm32f411-minimum/src/Make.defs @@ -0,0 +1,77 @@ +############################################################################ +# boards/arm/stm32f4/stm32f411-minimum/src/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +CSRCS = stm32_boot.c stm32_bringup.c + +ifeq ($(CONFIG_ARCH_LEDS),y) + CSRCS += stm32_autoleds.c +endif + +ifeq ($(CONFIG_USERLED),y) + CSRCS += stm32_userleds.c +endif + +ifeq ($(CONFIG_ARCH_BUTTONS),y) + CSRCS += stm32_buttons.c +endif + +ifeq ($(CONFIG_PWM),y) + CSRCS += stm32_pwm.c +endif + +ifeq ($(CONFIG_RGBLED),y) + CSRCS += stm32_rgbled.c +endif + +ifeq ($(CONFIG_ADC_HX711),y) + CSRCS += stm32_hx711.c +endif + +ifeq ($(CONFIG_SPI),y) + CSRCS += stm32_spi.c +endif + +ifeq ($(CONFIG_STM32F411MINIMUM_GPIO),y) + CSRCS += stm32_gpio.c +endif + +ifeq ($(CONFIG_MTD_W25),y) + CSRCS += stm32_w25.c +endif + +ifeq ($(CONFIG_STM32_OTGFS),y) + CSRCS += stm32_usb.c +endif + +ifeq ($(CONFIG_USBDEV_COMPOSITE),y) + CSRCS += stm32_composite.c +endif + +ifeq ($(CONFIG_USBMSC),y) +CSRCS += stm32_usbmsc.c +endif + +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32f4/stm32f411-minimum/src/stm32_autoleds.c b/boards/arm/stm32f4/stm32f411-minimum/src/stm32_autoleds.c new file mode 100644 index 0000000000000..5287975f236a5 --- /dev/null +++ b/boards/arm/stm32f4/stm32f411-minimum/src/stm32_autoleds.c @@ -0,0 +1,112 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f411-minimum/src/stm32_autoleds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32.h" +#include "stm32f411-minimum.h" + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +static inline void set_led(bool v) +{ + ledinfo("Turn LED %s\n", v? "on":"off"); + stm32_gpiowrite(GPIO_LED1, !v); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_autoled_initialize + ****************************************************************************/ + +#ifdef CONFIG_ARCH_LEDS +void board_autoled_initialize(void) +{ + /* Configure LED GPIO for output */ + + stm32_configgpio(GPIO_LED1); +} + +/**************************************************************************** + * Name: board_autoled_on + ****************************************************************************/ + +void board_autoled_on(int led) +{ + ledinfo("board_autoled_on(%d)\n", led); + + switch (led) + { + case LED_STARTED: + case LED_HEAPALLOCATE: + /* As the board provides only one soft controllable LED, we simply + * turn it on when the board boots. + */ + + set_led(true); + break; + + case LED_PANIC: + + /* For panic state, the LED is blinking */ + + set_led(true); + break; + } +} + +/**************************************************************************** + * Name: board_autoled_off + ****************************************************************************/ + +void board_autoled_off(int led) +{ + switch (led) + { + case LED_PANIC: + + /* For panic state, the LED is blinking */ + + set_led(false); + break; + } +} + +#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32f4/stm32f411-minimum/src/stm32_boot.c b/boards/arm/stm32f4/stm32f411-minimum/src/stm32_boot.c new file mode 100644 index 0000000000000..4bc171dc6a8a4 --- /dev/null +++ b/boards/arm/stm32f4/stm32f411-minimum/src/stm32_boot.c @@ -0,0 +1,101 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f411-minimum/src/stm32_boot.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include +#include + +#include + +#include "arm_internal.h" +#include "stm32f411-minimum.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_boardinitialize + * + * Description: + * All STM32 architectures must provide the following entry point. This + * entry point is called early in the initialization -- after all memory + * has been configured and mapped but before any devices have been + * initialized. + * + ****************************************************************************/ + +void stm32_boardinitialize(void) +{ +#ifdef CONFIG_ARCH_LEDS + /* Configure on-board LEDs if LED support has been selected. */ + + board_autoled_initialize(); +#endif + +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || \ + defined(CONFIG_STM32_SPI3) + /* Configure SPI chip selects if 1) SP2 is not disabled, and 2) the + * weak function stm32_spidev_initialize() has been brought into the link. + */ + + stm32_spidev_initialize(); +#endif + +#ifdef CONFIG_STM32_OTGFS + /* Initialize USB if the OTG FS controller is in the configuration. + * Presumably either CONFIG_USBDEV or CONFIG_USBHOST is also selected. + */ + + stm32_usbinitialize(); +#endif +} + +/**************************************************************************** + * Name: board_late_initialize + * + * Description: + * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_late_initialize(). board_late_initialize() will + * be called immediately after up_initialize() is called and just before + * the initial application is started. This additional initialization + * phase may be used, for example, to initialize board-specific device + * drivers. + * + ****************************************************************************/ + +#ifdef CONFIG_BOARD_LATE_INITIALIZE +void board_late_initialize(void) +{ + /* Perform board-specific initialization */ + + stm32_bringup(); +} +#endif diff --git a/boards/arm/stm32f4/stm32f411-minimum/src/stm32_bringup.c b/boards/arm/stm32f4/stm32f411-minimum/src/stm32_bringup.c new file mode 100644 index 0000000000000..9264b917c7dfe --- /dev/null +++ b/boards/arm/stm32f4/stm32f411-minimum/src/stm32_bringup.c @@ -0,0 +1,187 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f411-minimum/src/stm32_bringup.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include + +#include "stm32.h" + +#ifdef CONFIG_USERLED +# include +#endif + +#ifdef CONFIG_INPUT_BUTTONS +# include +#endif + +#ifdef CONFIG_STM32_OTGFS +# include "stm32_usbhost.h" +#endif + +#include "stm32f411-minimum.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Checking needed by W25 Flash */ + +#define HAVE_W25 1 + +/* Can't support the W25 device if it SPI1 or W25 support is not enabled */ + +#if !defined(CONFIG_STM32_SPI1) || !defined(CONFIG_MTD_W25) +# undef HAVE_W25 +#endif + +/* Can't support W25 features if mountpoints are disabled */ + +#ifdef CONFIG_DISABLE_MOUNTPOINT +# undef HAVE_W25 +#endif + +/* Default W25 minor number */ + +#if defined(HAVE_W25) && !defined(CONFIG_NSH_W25MINOR) +# define CONFIG_NSH_W25MINOR 0 +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_bringup + * + * Description: + * Perform architecture-specific initialization + * + * CONFIG_BOARD_LATE_INITIALIZE=y : + * Called from board_late_initialize(). + * + ****************************************************************************/ + +int stm32_bringup(void) +{ + int ret = OK; + +#ifdef CONFIG_USERLED + /* Register the LED driver */ + + ret = userled_lower_initialize("/dev/userleds"); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: userled_lower_initialize() failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_INPUT_BUTTONS + /* Register the BUTTON driver */ + + ret = btn_lower_initialize("/dev/buttons"); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: btn_lower_initialize() failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_PWM + /* Initialize PWM and register the PWM device. */ + + ret = stm32_pwm_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_pwm_setup() failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_RGBLED + /* Configure and initialize the RGB LED. */ + + ret = stm32_rgbled_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_rgbled_setup() failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO + ret = stm32_gpio_initialize(); + if (ret != OK) + { + gerr("ERROR: Failed to initialize gpio: %d\n", ret); + } +#endif + +#ifdef CONFIG_ADC_HX711 + ret = stm32_hx711_initialize(); + if (ret != OK) + { + aerr("ERROR: Failed to initialize hx711: %d\n", ret); + } +#endif + +#if defined(CONFIG_STM32_OTGFS) && defined(CONFIG_USBHOST) + /* Initialize USB host operation. stm32_usbhost_initialize() starts a + * thread will monitor for USB connection and disconnection events. + */ + + ret = stm32_usbhost_initialize(); + if (ret != OK) + { + uerr("ERROR: Failed to initialize USB host: %d\n", ret); + return ret; + } +#endif + +#ifdef HAVE_W25 + /* Initialize and register the W25 FLASH file system. */ + + ret = stm32_w25initialize(CONFIG_NSH_W25MINOR); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to initialize W25 minor %d: %d\n", + CONFIG_NSH_W25MINOR, ret); + return ret; + } +#endif + +#ifdef CONFIG_FS_PROCFS + /* Mount the procfs file system */ + + ret = nx_mount(NULL, STM32_PROCFS_MOUNTPOINT, "procfs", 0, NULL); + if (ret < 0) + { + ferr("ERROR: Failed to mount procfs at %s: %d\n", + STM32_PROCFS_MOUNTPOINT, ret); + } +#endif + + return ret; +} diff --git a/boards/arm/stm32f4/stm32f411-minimum/src/stm32_buttons.c b/boards/arm/stm32f4/stm32f411-minimum/src/stm32_buttons.c new file mode 100644 index 0000000000000..4ccae3e1a4d96 --- /dev/null +++ b/boards/arm/stm32f4/stm32f411-minimum/src/stm32_buttons.c @@ -0,0 +1,160 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f411-minimum/src/stm32_buttons.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include +#include + +#include "stm32_gpio.h" +#include "stm32f411-minimum.h" + +#if defined(CONFIG_ARCH_BUTTONS) + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#if defined(CONFIG_INPUT_BUTTONS) && !defined(CONFIG_ARCH_IRQBUTTONS) +# error "The NuttX Buttons Driver depends on IRQ support to work!\n" +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/* Pin configuration for each STM32F3Discovery button. This array is indexed + * by the BUTTON_* definitions in board.h + */ + +static const uint32_t g_buttons[NUM_BUTTONS] = +{ + GPIO_BTN_USER, GPIO_BTN_EXTERNAL +}; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_button_initialize + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. + * + ****************************************************************************/ + +uint32_t board_button_initialize(void) +{ + int i; + + /* Configure the GPIO pins as inputs. NOTE that EXTI interrupts are + * configured for all pins. + */ + + for (i = 0; i < NUM_BUTTONS; i++) + { + stm32_configgpio(g_buttons[i]); + } + + return NUM_BUTTONS; +} + +/**************************************************************************** + * Name: board_buttons + ****************************************************************************/ + +uint32_t board_buttons(void) +{ + uint32_t ret = 0; + int i; + + /* Check that state of each key */ + + for (i = 0; i < NUM_BUTTONS; i++) + { + /* A LOW value means that the key is pressed. */ + + bool released = stm32_gpioread(g_buttons[i]); + + /* Accumulate the set of depressed (not released) keys */ + + if (!released) + { + ret |= (1 << i); + } + } + + return ret; +} + +/**************************************************************************** + * Button support. + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. + * + * After board_button_initialize() has been called, board_buttons() may be + * called to collect the state of all buttons. board_buttons() returns + * an 32-bit bit set with each bit associated with a button. See the + * BUTTON_*_BIT definitions in board.h for the meaning of each bit. + * + * board_button_irq() may be called to register an interrupt handler that + * will be called when a button is depressed or released. The ID value is + * a button enumeration value that uniquely identifies a button resource. + * See the BUTTON_* definitions in board.h for the meaning of enumeration + * value. + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_IRQBUTTONS +int board_button_irq(int id, xcpt_t irqhandler, void *arg) +{ + int ret = -EINVAL; + + /* The following should be atomic */ + + if (id >= MIN_IRQBUTTON && id <= MAX_IRQBUTTON) + { + ret = stm32_gpiosetevent(g_buttons[id], true, true, true, irqhandler, + arg); + } + + return ret; +} +#endif + +#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/stm32f4/stm32f411-minimum/src/stm32_composite.c b/boards/arm/stm32f4/stm32f411-minimum/src/stm32_composite.c new file mode 100644 index 0000000000000..88e53ea4840ab --- /dev/null +++ b/boards/arm/stm32f4/stm32f411-minimum/src/stm32_composite.c @@ -0,0 +1,278 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f411-minimum/src/stm32_composite.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include +#include + +#include +#include +#include +#include + +#if defined(CONFIG_BOARDCTL_USBDEVCTRL) && defined(CONFIG_USBDEV_COMPOSITE) + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#ifdef CONFIG_USBMSC_COMPOSITE +static void *g_mschandle; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_mscclassobject + * + * Description: + * If the mass storage class driver is part of composite device, then + * its instantiation and configuration is a multi-step, board-specific, + * process (See comments for usbmsc_configure below). In this case, + * board-specific logic must provide board_mscclassobject(). + * + * board_mscclassobject() is called from the composite driver. It must + * encapsulate the instantiation and configuration of the mass storage + * class and the return the mass storage device's class driver instance + * to the composite driver. + * + * Input Parameters: + * classdev - The location to return the mass storage class' device + * instance. + * + * Returned Value: + * 0 on success; a negated errno on failure + * + ****************************************************************************/ + +#ifdef CONFIG_USBMSC_COMPOSITE +static int board_mscclassobject(int minor, + struct usbdev_devinfo_s *devinfo, + struct usbdevclass_driver_s **classdev) +{ + int ret; + + DEBUGASSERT(g_mschandle == NULL); + + /* Configure the mass storage device */ + + uinfo("Configuring with NLUNS=1\n"); + ret = usbmsc_configure(1, &g_mschandle); + if (ret < 0) + { + uerr("ERROR: usbmsc_configure failed: %d\n", -ret); + return ret; + } + + uinfo("MSC handle=%p\n", g_mschandle); + + /* Bind the LUN(s) */ + + uinfo("Bind LUN=0 to /dev/smart0\n"); + ret = usbmsc_bindlun(g_mschandle, "/dev/smart0", 0, 0, 0, false); + if (ret < 0) + { + uerr("ERROR: usbmsc_bindlun failed for LUN 1 at /dev/smart0: %d\n", + ret); + usbmsc_uninitialize(g_mschandle); + g_mschandle = NULL; + return ret; + } + + /* Get the mass storage device's class object */ + + ret = usbmsc_classobject(g_mschandle, devinfo, classdev); + if (ret < 0) + { + uerr("ERROR: usbmsc_classobject failed: %d\n", -ret); + usbmsc_uninitialize(g_mschandle); + g_mschandle = NULL; + } + + return ret; +} +#endif + +/**************************************************************************** + * Name: board_mscuninitialize + * + * Description: + * Un-initialize the USB storage class driver. + * This is just an application specific wrapper for usbmsc_unitialize() + * that is called form the composite device logic. + * + * Input Parameters: + * classdev - The class driver instance previously given to the composite + * driver by board_mscclassobject(). + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_USBMSC_COMPOSITE +static void board_mscuninitialize(struct usbdevclass_driver_s *classdev) +{ + if (g_mschandle) + { + usbmsc_uninitialize(g_mschandle); + } + + g_mschandle = NULL; +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_composite_initialize + * + * Description: + * Perform architecture specific initialization of a composite USB device. + * + ****************************************************************************/ + +int board_composite_initialize(int port) +{ + return OK; +} + +/**************************************************************************** + * Name: board_composite_connect + * + * Description: + * Connect the USB composite device on the specified USB device port using + * the specified configuration. The interpretation of the configid is + * board specific. + * + * Input Parameters: + * port - The USB device port. + * configid - The USB composite configuration + * + * Returned Value: + * A non-NULL handle value is returned on success. NULL is returned on + * any failure. + * + ****************************************************************************/ + +void *board_composite_connect(int port, int configid) +{ + /* Here we are composing the configuration of the usb composite device. + * + * The standard is to use one CDC/ACM and one USB mass storage device. + */ + + if (configid == 0) + { + struct composite_devdesc_s dev[2]; + int ifnobase = 0; + int strbase = COMPOSITE_NSTRIDS; + int dev_idx = 0; + +#ifdef CONFIG_USBMSC_COMPOSITE + /* Configure the mass storage device device */ + + /* Ask the usbmsc driver to fill in the constants we didn't + * know here. + */ + + usbmsc_get_composite_devdesc(&dev[dev_idx]); + + /* Overwrite and correct some values... */ + + /* The callback functions for the USBMSC class */ + + dev[dev_idx].classobject = board_mscclassobject; + dev[dev_idx].uninitialize = board_mscuninitialize; + + /* Interfaces */ + + dev[dev_idx].devinfo.ifnobase = ifnobase; /* Offset to Interface-IDs */ + dev[dev_idx].minor = 0; /* The minor interface number */ + + /* Strings */ + + dev[dev_idx].devinfo.strbase = strbase; /* Offset to String Numbers */ + + /* Endpoints */ + + dev[dev_idx].devinfo.epno[USBMSC_EP_BULKIN_IDX] = 3; + dev[dev_idx].devinfo.epno[USBMSC_EP_BULKOUT_IDX] = 3; + + /* Count up the base numbers */ + + ifnobase += dev[dev_idx].devinfo.ninterfaces; + strbase += dev[dev_idx].devinfo.nstrings; + dev_idx++; +#endif + +#ifdef CONFIG_CDCACM_COMPOSITE + /* Configure the CDC/ACM device */ + + /* Ask the cdcacm driver to fill in the constants we didn't + * know here. + */ + + cdcacm_get_composite_devdesc(&dev[dev_idx]); + + /* Overwrite and correct some values... */ + + /* The callback functions for the CDC/ACM class */ + + dev[dev_idx].classobject = cdcacm_classobject; + dev[dev_idx].uninitialize = cdcacm_uninitialize; + + /* Interfaces */ + + dev[dev_idx].devinfo.ifnobase = ifnobase; /* Offset to Interface-IDs */ + dev[dev_idx].minor = 0; /* The minor interface number */ + + /* Strings */ + + dev[dev_idx].devinfo.strbase = strbase; /* Offset to String Numbers */ + + /* Endpoints */ + + dev[dev_idx].devinfo.epno[CDCACM_EP_INTIN_IDX] = 1; + dev[dev_idx].devinfo.epno[CDCACM_EP_BULKIN_IDX] = 2; + dev[dev_idx].devinfo.epno[CDCACM_EP_BULKOUT_IDX] = 2; + dev_idx++; +#endif + + return composite_initialize(composite_getdevdescs(), dev, dev_idx); + } + else + { + return NULL; + } +} + +#endif /* CONFIG_BOARDCTL_USBDEVCTRL && CONFIG_USBDEV_COMPOSITE */ diff --git a/boards/arm/stm32f4/stm32f411-minimum/src/stm32_gpio.c b/boards/arm/stm32f4/stm32f411-minimum/src/stm32_gpio.c new file mode 100644 index 0000000000000..d7b499aaa79d3 --- /dev/null +++ b/boards/arm/stm32f4/stm32f411-minimum/src/stm32_gpio.c @@ -0,0 +1,741 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f411-minimum/src/stm32_gpio.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include +#include + +#include + +#include "chip.h" +#include "stm32.h" +#include "stm32f411-minimum.h" + +#if defined(CONFIG_DEV_GPIO) && !defined(CONFIG_GPIO_LOWER_HALF) + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +struct stm32gpio_dev_s +{ + struct gpio_dev_s gpio; + uint8_t id; +}; + +struct stm32gpint_dev_s +{ + struct stm32gpio_dev_s stm32gpio; + pin_interrupt_t callback; +}; + +struct stm32gpio_info_s +{ + uint32_t pin; + const char *pinname; /* Holds pin name like gpio_a0, gpio_custom_name */ +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +#if BOARD_NGPIO_IN > 0 +static int gpin_read(struct gpio_dev_s *dev, bool *value); +#endif + +#if BOARD_NGPIO_OUT > 0 +static int gpout_read(struct gpio_dev_s *dev, bool *value); +static int gpout_write(struct gpio_dev_s *dev, bool value); +#endif + +#if BOARD_NGPIO_INT > 0 +static int gpint_read(struct gpio_dev_s *dev, bool *value); +static int gpint_enable(struct gpio_dev_s *dev, bool enable); +static int gpint_attach(struct gpio_dev_s *dev, pin_interrupt_t callback); +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#if BOARD_NGPIO_IN > 0 +static const struct gpio_operations_s gpin_ops = +{ + .go_read = gpin_read, + .go_write = NULL, + .go_attach = NULL, + .go_enable = NULL, +}; + +static struct stm32gpio_dev_s g_gpin[BOARD_NGPIO_IN]; +static const struct stm32gpio_info_s g_gpio_inputs[BOARD_NGPIO_IN] = +{ +#ifdef CONFIG_STM32F411MINIMUM_GPIO_A0_IN + { .pin = GPIO_A0_IN, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A0_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_A1_IN + { .pin = GPIO_A1_IN, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A1_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_A2_IN + { .pin = GPIO_A2_IN, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A2_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_A3_IN + { .pin = GPIO_A3_IN, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A3_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_A4_IN + { .pin = GPIO_A4_IN, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A4_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_A5_IN + { .pin = GPIO_A5_IN, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A5_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_A6_IN + { .pin = GPIO_A6_IN, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A6_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_A7_IN + { .pin = GPIO_A7_IN, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A7_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_A8_IN + { .pin = GPIO_A8_IN, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A8_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_A9_IN + { .pin = GPIO_A9_IN, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A9_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_A10_IN + { .pin = GPIO_A10_IN, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A10_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_A11_IN + { .pin = GPIO_A11_IN, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A11_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_A12_IN + { .pin = GPIO_A12_IN, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A12_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_A15_IN + { .pin = GPIO_A15_IN, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A15_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_B0_IN + { .pin = GPIO_B0_IN, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B0_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_B1_IN + { .pin = GPIO_B1_IN, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B1_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_B2_IN + { .pin = GPIO_B2_IN, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B2_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_B3_IN + { .pin = GPIO_B3_IN, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B3_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_B4_IN + { .pin = GPIO_B4_IN, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B4_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_B5_IN + { .pin = GPIO_B5_IN, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B5_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_B6_IN + { .pin = GPIO_B6_IN, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B6_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_B7_IN + { .pin = GPIO_B7_IN, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B7_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_B8_IN + { .pin = GPIO_B8_IN, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B8_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_B9_IN + { .pin = GPIO_B9_IN, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B9_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_B10_IN + { .pin = GPIO_B10_IN, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B10_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_B12_IN + { .pin = GPIO_B12_IN, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B12_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_B13_IN + { .pin = GPIO_B13_IN, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B13_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_B14_IN + { .pin = GPIO_B14_IN, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B14_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_B15_IN + { .pin = GPIO_B15_IN, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B15_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_C13_IN + { .pin = GPIO_C13_IN, .pinname = CONFIG_STM32F411MINIMUM_GPIO_C13_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_C14_IN + { .pin = GPIO_C14_IN, .pinname = CONFIG_STM32F411MINIMUM_GPIO_C14_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_C15_IN + { .pin = GPIO_C15_IN, .pinname = CONFIG_STM32F411MINIMUM_GPIO_C15_NAME }, +#endif +}; +#endif /* BOARD_NGPIO_IN > 0 */ + +#if BOARD_NGPIO_OUT > 0 +static const struct gpio_operations_s gpout_ops = +{ + .go_read = gpout_read, + .go_write = gpout_write, + .go_attach = NULL, + .go_enable = NULL, +}; + +static struct stm32gpio_dev_s g_gpout[BOARD_NGPIO_OUT]; +static const struct stm32gpio_info_s g_gpio_outputs[BOARD_NGPIO_OUT] = +{ +#ifdef CONFIG_STM32F411MINIMUM_GPIO_A0_OUT + { .pin = GPIO_A0_OUT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A0_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_A1_OUT + { .pin = GPIO_A1_OUT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A1_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_A2_OUT + { .pin = GPIO_A2_OUT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A2_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_A3_OUT + { .pin = GPIO_A3_OUT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A3_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_A4_OUT + { .pin = GPIO_A4_OUT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A4_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_A5_OUT + { .pin = GPIO_A5_OUT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A5_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_A6_OUT + { .pin = GPIO_A6_OUT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A6_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_A7_OUT + { .pin = GPIO_A7_OUT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A7_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_A8_OUT + { .pin = GPIO_A8_OUT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A8_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_A9_OUT + { .pin = GPIO_A9_OUT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A9_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_A10_OUT + { .pin = GPIO_A10_OUT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A10_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_A11_OUT + { .pin = GPIO_A11_OUT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A11_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_A12_OUT + { .pin = GPIO_A12_OUT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A12_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_A15_OUT + { .pin = GPIO_A15_OUT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A15_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_B0_OUT + { .pin = GPIO_B0_OUT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B0_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_B1_OUT + { .pin = GPIO_B1_OUT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B1_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_B2_OUT + { .pin = GPIO_B2_OUT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B2_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_B3_OUT + { .pin = GPIO_B3_OUT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B3_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_B4_OUT + { .pin = GPIO_B4_OUT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B4_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_B5_OUT + { .pin = GPIO_B5_OUT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B5_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_B6_OUT + { .pin = GPIO_B6_OUT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B6_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_B7_OUT + { .pin = GPIO_B7_OUT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B7_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_B8_OUT + { .pin = GPIO_B8_OUT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B8_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_B9_OUT + { .pin = GPIO_B9_OUT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B9_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_B10_OUT + { .pin = GPIO_B10_OUT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B10_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_B12_OUT + { .pin = GPIO_B12_OUT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B12_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_B13_OUT + { .pin = GPIO_B13_OUT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B13_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_B14_OUT + { .pin = GPIO_B14_OUT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B14_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_B15_OUT + { .pin = GPIO_B15_OUT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B15_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_C13_OUT + { .pin = GPIO_C13_OUT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_C13_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_C14_OUT + { .pin = GPIO_C14_OUT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_C14_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_C15_OUT + { .pin = GPIO_C15_OUT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_C15_NAME }, +#endif +}; +#endif /* BOARD_NGPIO_OUT > 0 */ + +#if BOARD_NGPIO_INT > 0 +static const struct gpio_operations_s gpint_ops = +{ + .go_read = gpint_read, + .go_write = NULL, + .go_attach = gpint_attach, + .go_enable = gpint_enable, +}; + +static struct stm32gpint_dev_s g_gpint[BOARD_NGPIO_INT]; +static const struct stm32gpio_info_s g_gpio_int_inputs[BOARD_NGPIO_INT] = +{ +#ifdef CONFIG_STM32F411MINIMUM_GPIO_A0_INT + { .pin = GPIO_A0_INT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A0_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_A1_INT + { .pin = GPIO_A1_INT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A1_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_A2_INT + { .pin = GPIO_A2_INT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A2_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_A3_INT + { .pin = GPIO_A3_INT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A3_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_A4_INT + { .pin = GPIO_A4_INT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A4_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_A5_INT + { .pin = GPIO_A5_INT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A5_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_A6_INT + { .pin = GPIO_A6_INT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A6_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_A7_INT + { .pin = GPIO_A7_INT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A7_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_A8_INT + { .pin = GPIO_A8_INT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A8_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_A9_INT + { .pin = GPIO_A9_INT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A9_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_A10_INT + { .pin = GPIO_A10_INT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A10_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_A11_INT + { .pin = GPIO_A11_INT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A11_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_A12_INT + { .pin = GPIO_A12_INT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A12_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_A15_INT + { .pin = GPIO_A15_INT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A15_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_B0_INT + { .pin = GPIO_B0_INT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B0_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_B1_INT + { .pin = GPIO_B1_INT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B1_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_B2_INT + { .pin = GPIO_B2_INT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B2_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_B3_INT + { .pin = GPIO_B3_INT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B3_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_B4_INT + { .pin = GPIO_B4_INT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B4_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_B5_INT + { .pin = GPIO_B5_INT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B5_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_B6_INT + { .pin = GPIO_B6_INT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B6_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_B7_INT + { .pin = GPIO_B7_INT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B7_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_B8_INT + { .pin = GPIO_B8_INT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B8_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_B9_INT + { .pin = GPIO_B9_INT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B9_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_B10_INT + { .pin = GPIO_B10_INT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B10_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_B12_INT + { .pin = GPIO_B12_INT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B12_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_B13_INT + { .pin = GPIO_B13_INT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B13_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_B14_INT + { .pin = GPIO_B14_INT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B14_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_B15_INT + { .pin = GPIO_B15_INT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B15_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_C13_INT + { .pin = GPIO_C13_INT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_C13_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_C14_INT + { .pin = GPIO_C14_INT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_C14_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_C15_INT + { .pin = GPIO_C15_INT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_C15_NAME }, +#endif +}; +#endif /* BOARD_NGPIO_INT > 0 */ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: gpin_read + ****************************************************************************/ + +#if BOARD_NGPIO_IN > 0 +static int gpin_read(struct gpio_dev_s *dev, bool *value) +{ + struct stm32gpio_dev_s *stm32gpio = + (struct stm32gpio_dev_s *)dev; + + DEBUGASSERT(stm32gpio != NULL && value != NULL); + DEBUGASSERT(stm32gpio->id < BOARD_NGPIO_IN); + gpioinfo("Reading...\n"); + + *value = stm32_gpioread(g_gpio_inputs[stm32gpio->id].pin); + return OK; +} +#endif + +/**************************************************************************** + * Name: gpout_read + ****************************************************************************/ + +#if BOARD_NGPIO_OUT > 0 +static int gpout_read(struct gpio_dev_s *dev, bool *value) +{ + struct stm32gpio_dev_s *stm32gpio = + (struct stm32gpio_dev_s *)dev; + + DEBUGASSERT(stm32gpio != NULL && value != NULL); + DEBUGASSERT(stm32gpio->id < BOARD_NGPIO_OUT); + gpioinfo("Reading...\n"); + + *value = stm32_gpioread(g_gpio_outputs[stm32gpio->id].pin); + return OK; +} +#endif + +/**************************************************************************** + * Name: gpout_write + ****************************************************************************/ + +#if BOARD_NGPIO_OUT > 0 +static int gpout_write(struct gpio_dev_s *dev, bool value) +{ + struct stm32gpio_dev_s *stm32gpio = + (struct stm32gpio_dev_s *)dev; + + DEBUGASSERT(stm32gpio != NULL); + DEBUGASSERT(stm32gpio->id < BOARD_NGPIO_OUT); + gpioinfo("Writing %d\n", (int)value); + + stm32_gpiowrite(g_gpio_outputs[stm32gpio->id].pin, value); + return OK; +} +#endif + +/**************************************************************************** + * Name: gpint_read + ****************************************************************************/ + +#if BOARD_NGPIO_INT > 0 +static int gpint_read(struct gpio_dev_s *dev, bool *value) +{ + struct stm32gpint_dev_s *stm32gpint = + (struct stm32gpint_dev_s *)dev; + + DEBUGASSERT(stm32gpint != NULL && value != NULL); + DEBUGASSERT(stm32gpint->stm32gpio.id < BOARD_NGPIO_INT); + gpioinfo("Reading int pin...\n"); + + *value = stm32_gpioread(g_gpio_int_inputs[stm32gpint->stm32gpio.id].pin); + return OK; +} +#endif + +/**************************************************************************** + * Name: stm32gpio_interrupt + ****************************************************************************/ + +#if BOARD_NGPIO_INT > 0 +static int stm32gpio_interrupt(int irq, void *context, void *arg) +{ + struct stm32gpint_dev_s *stm32gpint = + (struct stm32gpint_dev_s *)arg; + + DEBUGASSERT(stm32gpint != NULL && stm32gpint->callback != NULL); + gpioinfo("Interrupt! callback=%p\n", stm32gpint->callback); + + stm32gpint->callback(&stm32gpint->stm32gpio.gpio, + stm32gpint->stm32gpio.id); + return OK; +} +#endif + +/**************************************************************************** + * Name: gpint_attach + ****************************************************************************/ + +#if BOARD_NGPIO_INT > 0 +static int gpint_attach(struct gpio_dev_s *dev, + pin_interrupt_t callback) +{ + struct stm32gpint_dev_s *stm32gpint = + (struct stm32gpint_dev_s *)dev; + + gpioinfo("Attaching the callback\n"); + + /* Make sure the interrupt is disabled */ + + stm32_gpiosetevent(g_gpio_int_inputs[stm32gpint->stm32gpio.id].pin, false, + false, false, NULL, NULL); + + gpioinfo("Attach %p\n", callback); + stm32gpint->callback = callback; + return OK; +} +#endif + +/**************************************************************************** + * Name: gpint_enable + ****************************************************************************/ + +#if BOARD_NGPIO_INT > 0 +static int gpint_enable(struct gpio_dev_s *dev, bool enable) +{ + struct stm32gpint_dev_s *stm32gpint = + (struct stm32gpint_dev_s *)dev; + + if (enable) + { + if (stm32gpint->callback != NULL) + { + gpioinfo("Enabling the interrupt\n"); + + /* Configure the interrupt for rising edge */ + + stm32_gpiosetevent(g_gpio_int_inputs[stm32gpint->stm32gpio.id].pin, + true, false, false, stm32gpio_interrupt, + &g_gpint[stm32gpint->stm32gpio.id]); + } + } + else + { + gpioinfo("Disable the interrupt\n"); + stm32_gpiosetevent(g_gpio_int_inputs[stm32gpint->stm32gpio.id].pin, + false, false, false, NULL, NULL); + } + + return OK; +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_gpio_initialize + * + * Description: + * Initialize GPIO drivers + * + ****************************************************************************/ + +int stm32_gpio_initialize(void) +{ + int i; + +#if BOARD_NGPIO_IN > 0 + for (i = 0; i < BOARD_NGPIO_IN; i++) + { + /* Setup and register the GPIO pin */ + + g_gpin[i].gpio.gp_pintype = GPIO_INPUT_PIN; + g_gpin[i].gpio.gp_ops = &gpin_ops; + g_gpin[i].id = i; + gpio_pin_register_byname(&g_gpin[i].gpio, g_gpio_inputs[i].pinname); + + /* Configure the pin that will be used as input */ + + stm32_configgpio(g_gpio_inputs[i].pin); + } +#endif + +#if BOARD_NGPIO_OUT > 0 + for (i = 0; i < BOARD_NGPIO_OUT; i++) + { + /* Setup and register the GPIO pin */ + + g_gpout[i].gpio.gp_pintype = GPIO_OUTPUT_PIN; + g_gpout[i].gpio.gp_ops = &gpout_ops; + g_gpout[i].id = i; + gpio_pin_register_byname(&g_gpout[i].gpio, g_gpio_outputs[i].pinname); + + /* Configure the pin that will be used as output */ + + stm32_gpiowrite(g_gpio_outputs[i].pin, 0); + stm32_configgpio(g_gpio_outputs[i].pin); + } +#endif + +#if BOARD_NGPIO_INT > 0 + for (i = 0; i < BOARD_NGPIO_INT; i++) + { + /* Setup and register the GPIO pin */ + + g_gpint[i].stm32gpio.gpio.gp_pintype = GPIO_INTERRUPT_PIN; + g_gpint[i].stm32gpio.gpio.gp_ops = &gpint_ops; + g_gpint[i].stm32gpio.id = i; + gpio_pin_register_byname(&g_gpint[i].stm32gpio.gpio, + g_gpio_int_inputs[i].pinname); + + /* Configure the pin that will be used as interrupt input */ + + stm32_configgpio(g_gpio_int_inputs[i].pin); + } +#endif + + return 0; +} +#endif /* CONFIG_DEV_GPIO && !CONFIG_GPIO_LOWER_HALF */ diff --git a/boards/arm/stm32f4/stm32f411-minimum/src/stm32_hx711.c b/boards/arm/stm32f4/stm32f411-minimum/src/stm32_hx711.c new file mode 100644 index 0000000000000..65db25d28fe38 --- /dev/null +++ b/boards/arm/stm32f4/stm32f411-minimum/src/stm32_hx711.c @@ -0,0 +1,104 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f411-minimum/src/stm32_hx711.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include +#include +#include +#include + +#include "stm32_gpio.h" +#include "stm32f411-minimum.h" + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +static int stm32_hx711_clock_set(unsigned char minor, int value); +static int stm32_hx711_data_read(unsigned char minor); +static int stm32_hx711_data_irq(unsigned char minor, + xcpt_t handler, void *arg); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +struct hx711_lower_s g_lower = +{ + .data_read = stm32_hx711_data_read, + .clock_set = stm32_hx711_clock_set, + .data_irq = stm32_hx711_data_irq, + .cleanup = NULL +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +static int stm32_hx711_clock_set(unsigned char minor, int value) +{ + UNUSED(minor); + + stm32_gpiowrite(HX711_CLK_PIN, value); + return OK; +} + +static int stm32_hx711_data_read(unsigned char minor) +{ + UNUSED(minor); + + return stm32_gpioread(HX711_DATA_PIN); +} + +static int stm32_hx711_data_irq(unsigned char minor, + xcpt_t handler, void *arg) +{ + UNUSED(minor); + + return stm32_gpiosetevent(HX711_DATA_PIN, false, true, true, handler, arg); +}; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +int stm32_hx711_initialize(void) +{ + int ret; + + stm32_configgpio(HX711_DATA_PIN); + stm32_configgpio(HX711_CLK_PIN); + + ret = hx711_register(0, &g_lower); + if (ret != 0) + { + aerr("ERROR: Failed to register hx711 device: %d\n", ret); + return -1; + } + + return OK; +} diff --git a/boards/arm/stm32f4/stm32f411-minimum/src/stm32_pwm.c b/boards/arm/stm32f4/stm32f411-minimum/src/stm32_pwm.c new file mode 100644 index 0000000000000..284affc8fbb0e --- /dev/null +++ b/boards/arm/stm32f4/stm32f411-minimum/src/stm32_pwm.c @@ -0,0 +1,127 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f411-minimum/src/stm32_pwm.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32_pwm.h" +#include "stm32f411-minimum.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* PWM + * + * The stm32f411-minimum has no real on-board PWM devices, but the board can + * be configured to output a pulse train using TIM4 CH2. + * This pin is used by FSMC is connect to CN5 just for this purpose: + * + * PB0 ADC12_IN8/TIM3_CH3 + * + */ + +#define HAVE_PWM 1 + +#ifndef CONFIG_PWM +# undef HAVE_PWM +#endif + +#ifndef CONFIG_STM32_TIM3 +# undef HAVE_PWM +#endif + +#ifndef CONFIG_STM32_TIM3_PWM +# undef HAVE_PWM +#endif + +#if !defined(CONFIG_STM32_TIM3_CHANNEL) || CONFIG_STM32_TIM3_CHANNEL != STM32F411MINIMUM_PWMCHANNEL +# undef HAVE_PWM +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_pwm_setup + * + * Description: + * Initialize PWM and register the PWM device. + * + ****************************************************************************/ + +int stm32_pwm_setup(void) +{ +#ifdef HAVE_PWM + static bool initialized = false; + struct pwm_lowerhalf_s *pwm; + int ret; + + /* Have we already initialized? */ + + if (!initialized) + { + /* Call stm32_pwminitialize() to get an instance of the PWM interface */ + + pwm = stm32_pwminitialize(STM32F411MINIMUM_PWMTIMER); + if (!pwm) + { + aerr("ERROR: Failed to get the STM32 PWM lower half\n"); + return -ENODEV; + } + + /* Register the PWM driver at "/dev/pwm0" */ + + ret = pwm_register("/dev/pwm0", pwm); + if (ret < 0) + { + aerr("ERROR: pwm_register failed: %d\n", ret); + return ret; + } + + /* Now we are initialized */ + + initialized = true; + } + + return OK; +#else + return -ENODEV; +#endif +} diff --git a/boards/arm/stm32f4/stm32f411-minimum/src/stm32_rgbled.c b/boards/arm/stm32f4/stm32f411-minimum/src/stm32_rgbled.c new file mode 100644 index 0000000000000..e142de19b15eb --- /dev/null +++ b/boards/arm/stm32f4/stm32f411-minimum/src/stm32_rgbled.c @@ -0,0 +1,185 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f411-minimum/src/stm32_rgbled.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32_pwm.h" +#include "stm32f411-minimum.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +#define HAVE_RGBLED 1 + +#ifndef CONFIG_PWM +# undef HAVE_RGBLED +#endif + +#ifndef CONFIG_STM32_TIM1 +# undef HAVE_RGBLED +#endif + +#ifndef CONFIG_STM32_TIM2 +# undef HAVE_RGBLED +#endif + +#ifndef CONFIG_STM32_TIM4 +# undef HAVE_RGBLED +#endif + +#ifndef CONFIG_STM32_TIM1_PWM +# undef HAVE_RGBLED +#endif + +#ifndef CONFIG_STM32_TIM2_PWM +# undef HAVE_RGBLED +#endif + +#ifndef CONFIG_STM32_TIM4_PWM +# undef HAVE_RGBLED +#endif + +#if CONFIG_STM32_TIM1_CHANNEL != RGBLED_RPWMCHANNEL +# undef HAVE_PWM +#endif + +#if CONFIG_STM32_TIM2_CHANNEL != RGBLED_GPWMCHANNEL +# undef HAVE_PWM +#endif + +#if CONFIG_STM32_TIM4_CHANNEL != RGBLED_BPWMCHANNEL +# undef HAVE_PWM +#endif + +#ifdef HAVE_RGBLED + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_rgbled_setup + * + * Description: + * Initial for support of a connected RGB LED using PWM. + * + ****************************************************************************/ + +int stm32_rgbled_setup(void) +{ + static bool initialized = false; + struct pwm_lowerhalf_s *ledr; + struct pwm_lowerhalf_s *ledg; + struct pwm_lowerhalf_s *ledb; + struct pwm_info_s info; + int ret; + + /* Have we already initialized? */ + + if (!initialized) + { + /* Call stm32_pwminitialize() to get an instance of the PWM interface */ + + ledr = stm32_pwminitialize(RGBLED_RPWMTIMER); + if (!ledr) + { + lederr("ERROR: Failed to get the STM32 PWM lower half to LEDR\n"); + return -ENODEV; + } + + /* Define frequency and duty cycle */ + + info.frequency = 100; + info.channels[0].duty = 0; + + /* Initialize LED R */ + + ledr->ops->setup(ledr); + ledr->ops->start(ledr, &info); + + /* Call stm32_pwminitialize() to get an instance of the PWM interface */ + + ledg = stm32_pwminitialize(RGBLED_GPWMTIMER); + if (!ledg) + { + lederr("ERROR: Failed to get the STM32 PWM lower half to LEDG\n"); + return -ENODEV; + } + + /* Initialize LED G */ + + ledg->ops->setup(ledg); + ledg->ops->start(ledg, &info); + + /* Call stm32_pwminitialize() to get an instance of the PWM interface */ + + ledb = stm32_pwminitialize(RGBLED_BPWMTIMER); + if (!ledb) + { + lederr("ERROR: Failed to get the STM32 PWM lower half to LEDB\n"); + return -ENODEV; + } + + /* Initialize LED B */ + + ledb->ops->setup(ledb); + ledb->ops->start(ledb, &info); + + /* Register the RGB LED diver at "/dev/rgbled0" */ + + ret = rgbled_register("/dev/rgbled0", ledr, ledg, ledb, + RGBLED_RPWMCHANNEL, RGBLED_GPWMCHANNEL, + RGBLED_BPWMCHANNEL); + if (ret < 0) + { + lederr("ERROR: rgbled_register failed: %d\n", ret); + return ret; + } + + /* Now we are initialized */ + + initialized = true; + } + + return OK; +} + +#else +# error "HAVE_RGBLED is undefined" +#endif /* HAVE_RGBLED */ diff --git a/boards/arm/stm32f4/stm32f411-minimum/src/stm32_spi.c b/boards/arm/stm32f4/stm32f411-minimum/src/stm32_spi.c new file mode 100644 index 0000000000000..43347015546e1 --- /dev/null +++ b/boards/arm/stm32f4/stm32f411-minimum/src/stm32_spi.c @@ -0,0 +1,175 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f411-minimum/src/stm32_spi.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "arm_internal.h" +#include "chip.h" +#include "stm32.h" +#include "stm32f411-minimum.h" + +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_spidev_initialize + * + * Description: + * Called to configure SPI chip select GPIO pins + * for the WeAct Studio MiniF4 board. + * + ****************************************************************************/ + +void stm32_spidev_initialize(void) +{ + /* NOTE: Clocking for SPI1 and/or SPI2 was already provided in stm32_rcc.c. + * Configurations of SPI pins is performed in stm32_spi.c. + * Here, we only initialize chip select pins unique to the board + * architecture. + */ + +#ifdef CONFIG_MTD_W25 + stm32_configgpio(FLASH_SPI1_CS); /* FLASH chip select */ +#endif + +#ifdef CONFIG_MMCSD_SPI + stm32_configgpio(GPIO_SDCARD_CS); /* SD/MMC Card chip select */ +#endif +} + +/**************************************************************************** + * Name: stm32_spi1/2select and stm32_spi1/2status + * + * Description: + * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status + * must be provided by board-specific logic. They are implementations of + * the select and status methods of the SPI interface defined by struct + * spi_ops_s (see include/nuttx/spi/spi.h). All other methods (including + * stm32_spibus_initialize()) are provided by common STM32 logic. + * To use this common SPI logic on your board: + * + * 1. Provide logic in stm32_boardinitialize() to configure SPI chip select + * pins. + * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() functions + * in your board-specific logic. These functions will perform chip + * selection and status operations using GPIOs in the way your board is + * configured. + * 3. Add a calls to stm32_spibus_initialize() in your low level + * application initialization logic + * 4. The handle returned by stm32_spibus_initialize() may then be used to + * bind the SPI driver to higher level logic (e.g., calling + * mmcsd_spislotinitialize(), for example, will bind the SPI driver to + * the SPI MMC/SD driver). + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_SPI1 +void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, + bool selected) +{ +#ifdef CONFIG_MMCSD_SPI + if (devid == SPIDEV_MMCSD(0)) + { + stm32_gpiowrite(GPIO_SDCARD_CS, !selected); + } +#endif + +#ifdef CONFIG_MTD_W25 + stm32_gpiowrite(FLASH_SPI1_CS, !selected); +#endif +} + +uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) +{ + uint8_t status = 0; + +#ifdef CONFIG_MMCSD_SPI + if (devid == SPIDEV_MMCSD(0)) + { + status |= SPI_STATUS_PRESENT; + } +#endif + + return status; +} +#endif + +#ifdef CONFIG_STM32_SPI2 +void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid, + bool selected) +{ +} + +uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} +#endif + +/**************************************************************************** + * Name: stm32_spi1cmddata + * + * Description: + * Set or clear the SH1101A A0 or SD1306 D/C n bit to select data (true) + * or command (false). This function must be provided by platform-specific + * logic. This is an implementation of the cmddata method of the SPI + * interface defined by struct spi_ops_s (see include/nuttx/spi/spi.h). + * + * Input Parameters: + * + * spi - SPI device that controls the bus the device that requires the CMD/ + * DATA selection. + * devid - If there are multiple devices on the bus, this selects which one + * to select cmd or data. NOTE: This design restricts, for example, + * one one SPI display per SPI bus. + * cmd - true: select command; false: select data + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_SPI_CMDDATA +#ifdef CONFIG_STM32_SPI1 +int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, + bool cmd) +{ + return -ENODEV; +} +#endif +#endif + +#endif /* CONFIG_STM32_SPI1 || CONFIG_STM32_SPI2 */ diff --git a/boards/arm/stm32f4/stm32f411-minimum/src/stm32_usb.c b/boards/arm/stm32f4/stm32f411-minimum/src/stm32_usb.c new file mode 100644 index 0000000000000..ff842eb11b4d1 --- /dev/null +++ b/boards/arm/stm32f4/stm32f411-minimum/src/stm32_usb.c @@ -0,0 +1,329 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f411-minimum/src/stm32_usb.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include "arm_internal.h" +#include "stm32.h" +#include "stm32_otgfs.h" +#include "stm32f411-minimum.h" + +#ifdef CONFIG_STM32_OTGFS + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#if !defined(CONFIG_USBDEV) && !defined(CONFIG_USBHOST) +# warning "CONFIG_STM32_OTGFS is enabled but neither CONFIG_USBDEV nor CONFIG_USBHOST" +#endif + +#ifndef CONFIG_STM32F411MINIMUM_USBHOST_PRIO +# define CONFIG_STM32F411MINIMUM_USBHOST_PRIO 100 +#endif + +#ifndef CONFIG_STM32F411MINIMUM_USBHOST_STACKSIZE +# define CONFIG_STM32F411MINIMUM_USBHOST_STACKSIZE 1024 +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +static struct usbhost_connection_s *g_usbconn; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: usbhost_waiter + * + * Description: + * Wait for USB devices to be connected. + * + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +static int usbhost_waiter(int argc, char *argv[]) +{ + struct usbhost_hubport_s *hport; + + uinfo("Running\n"); + for (; ; ) + { + /* Wait for the device to change state */ + + DEBUGVERIFY(CONN_WAIT(g_usbconn, &hport)); + uinfo("%s\n", hport->connected ? "connected" : "disconnected"); + + /* Did we just become connected? */ + + if (hport->connected) + { + /* Yes.. enumerate the newly connected device */ + + CONN_ENUMERATE(g_usbconn, hport); + } + } + + /* Keep the compiler from complaining */ + + return 0; +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_usbinitialize + * + * Description: + * Called from stm32_boardinitialize very early in initialization to setup + * USB-related GPIO pins for the WeAct Studio MiniF4 board. + * + ****************************************************************************/ + +void stm32_usbinitialize(void) +{ + /* The OTG FS has an internal soft pull-up. No GPIO configuration is + * required + * This board has no connections for VBUS, Power On, or Overcurrent + * GPIOs + */ +} + +/**************************************************************************** + * Name: stm32_usbhost_initialize + * + * Description: + * Called at application startup time to initialize the USB host + * functionality. This function will start a thread that will monitor for + * device connection/disconnection events. + * + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +int stm32_usbhost_initialize(void) +{ + int ret; + + /* First, register all of the class drivers needed to support the drivers + * that we care about: + */ + + uinfo("Register class drivers\n"); + +#ifdef CONFIG_USBHOST_HUB + /* Initialize USB hub class support */ + + ret = usbhost_hub_initialize(); + if (ret < 0) + { + uerr("ERROR: usbhost_hub_initialize failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_USBHOST_MSC + /* Register the USB mass storage class class */ + + ret = usbhost_msc_initialize(); + if (ret != OK) + { + uerr("ERROR: Failed to register the mass storage class: %d\n", ret); + } +#endif + +#ifdef CONFIG_USBHOST_CDCACM + /* Register the CDC/ACM serial class */ + + ret = usbhost_cdcacm_initialize(); + if (ret != OK) + { + uerr("ERROR: Failed to register the CDC/ACM serial class: %d\n", ret); + } +#endif + +#ifdef CONFIG_USBHOST_HIDKBD + /* Initialize the HID keyboard class */ + + ret = usbhost_kbdinit(); + if (ret != OK) + { + uerr("ERROR: Failed to register the HID keyboard class\n"); + } +#endif + +#ifdef CONFIG_USBHOST_HIDMOUSE + /* Initialize the HID mouse class */ + + ret = usbhost_mouse_init(); + if (ret != OK) + { + uerr("ERROR: Failed to register the HID mouse class\n"); + } +#endif + +#ifdef CONFIG_USBHOST_XBOXCONTROLLER + /* Initialize the HID mouse class */ + + ret = usbhost_xboxcontroller_init(); + if (ret != OK) + { + uerr("ERROR: Failed to register the XBox Controller class\n"); + } +#endif + + /* Then get an instance of the USB host interface */ + + uinfo("Initialize USB host\n"); + g_usbconn = stm32_otgfshost_initialize(0); + if (g_usbconn) + { + /* Start a thread to handle device connection. */ + + uinfo("Start usbhost_waiter\n"); + + ret = kthread_create("usbhost", CONFIG_STM32F411MINIMUM_USBHOST_PRIO, + CONFIG_STM32F411MINIMUM_USBHOST_STACKSIZE, + usbhost_waiter, NULL); + return ret < 0 ? -ENOEXEC : OK; + } + + return -ENODEV; +} +#endif + +/**************************************************************************** + * Name: stm32_usbhost_vbusdrive + * + * Description: + * Enable/disable driving of VBUS 5V output. This function must be + * provided be each platform that implements the STM32 OTG FS host + * interface + * + * "On-chip 5 V VBUS generation is not supported. For this reason, a charge + * pump or, if 5 V are available on the application board, a basic power + * switch, must be added externally to drive the 5 V VBUS line. The + * external charge pump can be driven by any GPIO output. When the + * application decides to power on VBUS using the chosen GPIO, it must + * also set the port power bit in the host port control and status + * register (PPWR bit in OTG_FS_HPRT). + * + * "The application uses this field to control power to this port, and the + * core clears this bit on an overcurrent condition." + * + * Input Parameters: + * iface - For future growth to handle multiple USB host interface. + * Should be zero. + * enable - true: enable VBUS power; false: disable VBUS power + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +void stm32_usbhost_vbusdrive(int iface, bool enable) +{ + DEBUGASSERT(iface == 0); + + if (enable) + { + /* Enable the Power Switch by driving the enable pin low */ + + stm32_gpiowrite(GPIO_OTGFS_PWRON, false); + } + else + { + /* Disable the Power Switch by driving the enable pin high */ + + stm32_gpiowrite(GPIO_OTGFS_PWRON, true); + } +} +#endif + +/**************************************************************************** + * Name: stm32_setup_overcurrent + * + * Description: + * Setup to receive an interrupt-level callback if an overcurrent condition + * is detected. + * + * Input Parameters: + * handler - New overcurrent interrupt handler + * arg - The argument provided for the interrupt handler + * + * Returned Value: + * Zero (OK) is returned on success. Otherwise, a negated errno value is + * returned to indicate the nature of the failure. + * + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +int stm32_setup_overcurrent(xcpt_t handler, void *arg) +{ + return stm32_gpiosetevent(GPIO_OTGFS_OVER, true, true, true, handler, arg); +} +#endif + +/**************************************************************************** + * Name: stm32_usbsuspend + * + * Description: + * Board logic must provide the stm32_usbsuspend logic if the USBDEV + * driver is used. This function is called whenever the USB enters or + * leaves suspend mode. + * This is an opportunity for the board logic to shutdown clocks, power, + * etc. while the USB is suspended. + * + ****************************************************************************/ + +#ifdef CONFIG_USBDEV +void stm32_usbsuspend(struct usbdev_s *dev, bool resume) +{ + uinfo("resume: %d\n", resume); +} +#endif + +#endif /* CONFIG_STM32_OTGFS */ diff --git a/boards/arm/stm32f4/stm32f411-minimum/src/stm32_usbmsc.c b/boards/arm/stm32f4/stm32f411-minimum/src/stm32_usbmsc.c new file mode 100644 index 0000000000000..14890201cacb6 --- /dev/null +++ b/boards/arm/stm32f4/stm32f411-minimum/src/stm32_usbmsc.c @@ -0,0 +1,71 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f411-minimum/src/stm32_usbmsc.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include + +#include "stm32.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +#ifndef CONFIG_SYSTEM_USBMSC_DEVMINOR1 +# define CONFIG_SYSTEM_USBMSC_DEVMINOR1 0 +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_usbmsc_initialize + * + * Description: + * Perform architecture specific initialization of the USB MSC device. + * + ****************************************************************************/ + +int board_usbmsc_initialize(int port) +{ + /* If system/usbmsc is built as an NSH command, then SD slot should + * already have been initialized. + * In this case, there is nothing further to be done here. + */ + +#ifndef CONFIG_NSH_BUILTIN_APPS + return stm32_w25initialize(CONFIG_SYSTEM_USBMSC_DEVMINOR1); +#else + return OK; +#endif +} diff --git a/boards/arm/stm32f4/stm32f411-minimum/src/stm32_userleds.c b/boards/arm/stm32f4/stm32f411-minimum/src/stm32_userleds.c new file mode 100644 index 0000000000000..660ef135af9ed --- /dev/null +++ b/boards/arm/stm32f4/stm32f411-minimum/src/stm32_userleds.c @@ -0,0 +1,102 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f411-minimum/src/stm32_userleds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include + +#include "chip.h" +#include "stm32.h" +#include "stm32f411-minimum.h" + +#ifndef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* This array maps an LED number to GPIO pin configuration */ + +static const uint32_t g_ledcfg[BOARD_NLEDS] = +{ + GPIO_LED1, +}; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_userled_initialize + ****************************************************************************/ + +uint32_t board_userled_initialize(void) +{ + int i; + + /* Configure LED GPIOs for output */ + + for (i = 0; i < BOARD_NLEDS; i++) + { + stm32_configgpio(g_ledcfg[i]); + } + + return BOARD_NLEDS; +} + +/**************************************************************************** + * Name: board_userled + ****************************************************************************/ + +void board_userled(int led, bool ledon) +{ + if ((unsigned)led < BOARD_NLEDS) + { + stm32_gpiowrite(g_ledcfg[led], ledon); + } +} + +/**************************************************************************** + * Name: board_userled_all + ****************************************************************************/ + +void board_userled_all(uint32_t ledset) +{ + int i; + + /* Configure LED GPIOs for output */ + + for (i = 0; i < BOARD_NLEDS; i++) + { + stm32_gpiowrite(g_ledcfg[i], (ledset & (1 << i)) != 0); + } +} + +#endif /* !CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32f4/stm32f411-minimum/src/stm32_w25.c b/boards/arm/stm32f4/stm32f411-minimum/src/stm32_w25.c new file mode 100644 index 0000000000000..e2c0ce64a4715 --- /dev/null +++ b/boards/arm/stm32f4/stm32f411-minimum/src/stm32_w25.c @@ -0,0 +1,156 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f411-minimum/src/stm32_w25.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include + +#ifdef CONFIG_STM32_SPI1 +# include +# include +# include +# include +#endif + +#include "stm32_spi.h" + +#include "stm32f411-minimum.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Debug ********************************************************************/ + +/* Non-standard debug that may be enabled just for testing the watchdog + * timer + */ + +#define W25_SPI_PORT 1 + +/* Configuration ************************************************************/ + +/* Can't support the W25 device if it SPI1 or W25 support is not enabled */ + +#define HAVE_W25 1 +#if !defined(CONFIG_STM32_SPI1) || !defined(CONFIG_MTD_W25) +# undef HAVE_W25 +#endif + +/* Can't support W25 features if mountpoints are disabled */ + +#if defined(CONFIG_DISABLE_MOUNTPOINT) +# undef HAVE_W25 +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_w25initialize + * + * Description: + * Initialize and register the W25 FLASH file system. + * + ****************************************************************************/ + +int stm32_w25initialize(int minor) +{ + int ret; +#ifdef HAVE_W25 + struct spi_dev_s *spi; + struct mtd_dev_s *mtd; + struct mtd_geometry_s geo; +#if defined(CONFIG_MTD_PARTITION_NAMES) + const char *partname = CONFIG_STM32F411MINIMUM_FLASH_PART_NAMES; +#endif + + /* Get the SPI port */ + + spi = stm32_spibus_initialize(W25_SPI_PORT); + if (!spi) + { + syslog(LOG_ERR, "ERROR: Failed to initialize SPI port %d\n", + W25_SPI_PORT); + return -ENODEV; + } + + /* Raise SPI frequency from default 400kHz to something usable + * SPI1 uses PCLK2 of 96MHz with DIV2 = 48Mbps max + * W25Q64 requires more dummy clocks above 26MHz + */ + + SPI_SETFREQUENCY(spi, 24000000); + + /* Now bind the SPI interface to the W25 SPI FLASH driver */ + + mtd = w25_initialize(spi); + if (!mtd) + { + syslog(LOG_ERR, "ERROR: Failed to bind SPI port %d to the Winbond" + "W25 FLASH driver\n", W25_SPI_PORT); + return -ENODEV; + } + +#ifndef CONFIG_FS_SMARTFS + /* Register the MTD driver */ + + char path[32]; + snprintf(path, sizeof(path), "/dev/mtdblock%d", minor); + ret = register_mtddriver(path, mtd, 0755, NULL); + if (ret < 0) + { + syslog(LOG_ERR, + "ERROR: Failed to register the MTD driver %s, ret %d\n", + path, ret); + return ret; + } +#else + /* Initialize to provide SMARTFS on the MTD interface */ + + /* Get the geometry of the FLASH device */ + + ret = mtd->ioctl(mtd, MTDIOC_GEOMETRY, (unsigned long)((uintptr_t)&geo)); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: mtd->ioctl failed: %d\n", ret); + return ret; + } + + /* Configure the device with no partition support */ + + smart_initialize(CONFIG_STM32F411MINIMUM_FLASH_MINOR, mtd, NULL); + +#endif /* CONFIG_FS_SMARTFS */ +#endif /* HAVE_W25 */ + + return OK; +} diff --git a/boards/arm/stm32/stm32f411-minimum/src/stm32f411-minimum-gpio.h b/boards/arm/stm32f4/stm32f411-minimum/src/stm32f411-minimum-gpio.h similarity index 99% rename from boards/arm/stm32/stm32f411-minimum/src/stm32f411-minimum-gpio.h rename to boards/arm/stm32f4/stm32f411-minimum/src/stm32f411-minimum-gpio.h index 1942732d68269..54b682fa67c7a 100644 --- a/boards/arm/stm32/stm32f411-minimum/src/stm32f411-minimum-gpio.h +++ b/boards/arm/stm32f4/stm32f411-minimum/src/stm32f411-minimum-gpio.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f411-minimum/src/stm32f411-minimum-gpio.h + * boards/arm/stm32f4/stm32f411-minimum/src/stm32f411-minimum-gpio.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32f411-minimum/src/stm32f411-minimum.h b/boards/arm/stm32f4/stm32f411-minimum/src/stm32f411-minimum.h similarity index 99% rename from boards/arm/stm32/stm32f411-minimum/src/stm32f411-minimum.h rename to boards/arm/stm32f4/stm32f411-minimum/src/stm32f411-minimum.h index 38d62a738ac44..fac30d9a1f9c1 100644 --- a/boards/arm/stm32/stm32f411-minimum/src/stm32f411-minimum.h +++ b/boards/arm/stm32f4/stm32f411-minimum/src/stm32f411-minimum.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f411-minimum/src/stm32f411-minimum.h + * boards/arm/stm32f4/stm32f411-minimum/src/stm32f411-minimum.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f4/stm32f411e-disco/CMakeLists.txt b/boards/arm/stm32f4/stm32f411e-disco/CMakeLists.txt new file mode 100644 index 0000000000000..7147e4505e556 --- /dev/null +++ b/boards/arm/stm32f4/stm32f411e-disco/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32f4/stm32f411e-disco/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/arm/stm32/stm32f411e-disco/Kconfig b/boards/arm/stm32f4/stm32f411e-disco/Kconfig similarity index 100% rename from boards/arm/stm32/stm32f411e-disco/Kconfig rename to boards/arm/stm32f4/stm32f411e-disco/Kconfig diff --git a/boards/arm/stm32f4/stm32f411e-disco/configs/nsh/defconfig b/boards/arm/stm32f4/stm32f411e-disco/configs/nsh/defconfig new file mode 100644 index 0000000000000..0a887cdf2dd11 --- /dev/null +++ b/boards/arm/stm32f4/stm32f411e-disco/configs/nsh/defconfig @@ -0,0 +1,48 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_ARCH_LEDS is not set +# CONFIG_DISABLE_OS_API is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_STM32_SYSCFG is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f411e-disco" +CONFIG_ARCH_BOARD_STM32F411E_DISCO=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F411VE=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=8499 +CONFIG_BUILTIN=y +CONFIG_HAVE_CXX=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=131072 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=14 +CONFIG_START_MONTH=10 +CONFIG_START_YEAR=2014 +CONFIG_STM32_FLASH_CONFIG_E=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f4/stm32f411e-disco/include/board.h b/boards/arm/stm32f4/stm32f411e-disco/include/board.h new file mode 100644 index 0000000000000..ce8aadff51251 --- /dev/null +++ b/boards/arm/stm32f4/stm32f411e-disco/include/board.h @@ -0,0 +1,358 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f411e-disco/include/board.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_STM32_STM32F411E_DISCO_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32_STM32F411E_DISCO_INCLUDE_BOARD_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#ifndef __ASSEMBLY__ +# include +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Clocking *****************************************************************/ + +/* System Clock source : PLLCLK (HSE) + * SYSCLK(Hz) : 96000000 Determined by PLL + * configuration + * HCLK(Hz) : 96000000 (STM32_RCC_CFGR_HPRE) + * AHB Prescaler : 1 (STM32_RCC_CFGR_HPRE) + * APB1 Prescaler : 4 (STM32_RCC_CFGR_PPRE1) + * APB2 Prescaler : 2 (STM32_RCC_CFGR_PPRE2) + * HSI Frequency(Hz) : 16000000 (nominal) + * PLLM : 4 (STM32_PLLCFG_PLLM) + * PLLN : 192 (STM32_PLLCFG_PLLN) + * PLLP : 4 (STM32_PLLCFG_PLLP) + * PLLQ : 8 (STM32_PLLCFG_PPQ) + * Flash Latency(WS) : 3 + * Prefetch Buffer : OFF + * Instruction cache : ON + * Data cache : ON + * Require 48MHz for USB OTG FS, : Enabled + * SDIO and RNG clock + */ + +/* HSI - 16 MHz RC factory-trimmed + * LSI - 32 KHz RC + * HSE - 8 MHz Crystal + * LSE - not installed + */ + +#define STM32_BOARD_XTAL 8000000ul + +#define STM32_HSI_FREQUENCY 16000000ul +#define STM32_LSI_FREQUENCY 32000 +#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL + +/* Main PLL Configuration. + * + * Formulae: + * + * VCO input frequency = PLL input clock frequency / PLLM, + * 2 <= PLLM <= 63 + * VCO output frequency = VCO input frequency × PLLN, + * 192 <= PLLN <= 432 + * PLL output clock frequency = VCO frequency / PLLP, + * PLLP = 2, 4, 6, or 8 + * USB OTG FS clock frequency = VCO frequency / PLLQ, + * 2 <= PLLQ <= 15 + * + * There is no config for 100 MHz and 48 MHz for usb, + * so we would like to have SYSYCLK=96MHz and we must have the + * USB clock= 48MHz. + * + * PLLQ = 8 PLLP = 4 PLLN=192 PLLM=4 + * + * We will configure like this + * + * PLL source is HSE + * PLL_VCO = (STM32_HSE_FREQUENCY / PLLM) * PLLN + * = (8,000,000 / 4) * 192 + * = 384,000,000 + * SYSCLK = PLL_VCO / PLLP + * = 384,000,000 / 4 = 96,000,000 + * USB OTG FS and SDIO Clock + * = PLL_VCO / PLLQ + * = 384,000,000 / 8 = 48,000,000 + */ + +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(4) +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(192) +#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_4 +#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(8) + +#define STM32_SYSCLK_FREQUENCY 96000000ul + +/* AHB clock (HCLK) is SYSCLK (96MHz) */ + +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY + +/* APB1 clock (PCLK1) is HCLK/4 (24MHz) */ + +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd4 /* PCLK1 = HCLK / 4 */ +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/4) + +/* Timers driven from APB1 will be twice PCLK1 */ + +/* REVISIT */ + +#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) + +/* APB2 clock (PCLK2) is HCLK (48MHz) */ + +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLKd2 /* PCLK2 = HCLK / 2 */ +#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/2) + +/* Timers driven from APB2 will be twice PCLK2 */ + +#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM9_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB2_TIM10_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB2_TIM11_CLKIN (2*STM32_PCLK1_FREQUENCY) + +/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx + * otherwise frequency is 2xAPBx. + * Note: TIM1,8 are on APB2, others on APB1 + */ + +/* REVISIT */ + +#define BOARD_TIM1_FREQUENCY (2 * STM32_PCLK2_FREQUENCY) +#define BOARD_TIM2_FREQUENCY (2 * STM32_PCLK1_FREQUENCY) +#define BOARD_TIM3_FREQUENCY (2 * STM32_PCLK1_FREQUENCY) +#define BOARD_TIM4_FREQUENCY (2 * STM32_PCLK1_FREQUENCY) +#define BOARD_TIM5_FREQUENCY (2 * STM32_PCLK1_FREQUENCY) +#define BOARD_TIM6_FREQUENCY (2 * STM32_PCLK1_FREQUENCY) +#define BOARD_TIM7_FREQUENCY (2 * STM32_PCLK1_FREQUENCY) +#define BOARD_TIM8_FREQUENCY (2 * STM32_PCLK2_FREQUENCY) + +/* SDIO dividers. Note that slower clocking is required when DMA is disabled + * in order to avoid RX overrun/TX underrun errors due to delayed responses + * to service FIFOs in interrupt driven mode. These values have not been + * tuned!!! + * + * HCLK=72MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(178+2)=400 KHz + */ + +/* REVISIT */ + +#define SDIO_INIT_CLKDIV (178 << SDIO_CLKCR_CLKDIV_SHIFT) + +/* DMA ON: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(2+2)=18 MHz + * DMA OFF: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(3+2)=14.4 MHz + */ + +/* REVISIT */ + +#ifdef CONFIG_SDIO_DMA +# define SDIO_MMCXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT) +#else +# define SDIO_MMCXFR_CLKDIV (3 << SDIO_CLKCR_CLKDIV_SHIFT) +#endif + +/* DMA ON: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(1+2)=24 MHz + * DMA OFF: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(3+2)=14.4 MHz + */ + +/* REVISIT */ + +#ifdef CONFIG_SDIO_DMA +# define SDIO_SDXFR_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT) +#else +# define SDIO_SDXFR_CLKDIV (3 << SDIO_CLKCR_CLKDIV_SHIFT) +#endif + +/* DMA Channel/Stream Selections ********************************************/ + +/* Stream selections are arbitrary for now but might become important in the + * future is we set aside more DMA channels/streams. + * + * SDIO DMA + *   DMAMAP_SDIO_1 = Channel 4, Stream 3 <- may later be used by SPI DMA + *   DMAMAP_SDIO_2 = Channel 4, Stream 6 + */ + +#define DMAMAP_SDIO DMAMAP_SDIO_1 + +/* Need to VERIFY fwb */ + +#define DMACHAN_SPI1_RX DMAMAP_SPI1_RX_1 +#define DMACHAN_SPI1_TX DMAMAP_SPI1_TX_1 +#define DMACHAN_SPI2_RX DMAMAP_SPI2_RX +#define DMACHAN_SPI2_TX DMAMAP_SPI2_TX + +/* Alternate function pin selections ****************************************/ + +/* USART1: + * RXD: PA10 CN9 pin 3, CN10 pin 33 + * PB7 CN7 pin 21 + * TXD: PA9 CN5 pin 1, CN10 pin 21 + * PB6 CN5 pin 3, CN10 pin 17 + */ + +#if 1 +# define GPIO_USART1_RX (GPIO_USART1_RX_1|GPIO_SPEED_100MHz) /* PA10 */ +# define GPIO_USART1_TX (GPIO_USART1_TX_1|GPIO_SPEED_100MHz) /* PA9 */ +#else +# define GPIO_USART1_RX (GPIO_USART1_RX_2|GPIO_SPEED_100MHz) /* PB7 */ +# define GPIO_USART1_TX (GPIO_USART1_TX_2|GPIO_SPEED_100MHz) /* PB6 */ +#endif + +/* USART2: + * RXD: PA3 CN9 pin 1 (See SB13, 14, 62, 63). CN10 pin 37 + * PD6 + * TXD: PA2 CN9 pin 2(See SB13, 14, 62, 63). CN10 pin 35 + * PD5 + */ + +#define GPIO_USART2_RX (GPIO_USART2_RX_1|GPIO_SPEED_100MHz) /* PA3 */ +#define GPIO_USART2_TX (GPIO_USART2_TX_1|GPIO_SPEED_100MHz) /* PA2 */ +#define GPIO_USART2_RTS GPIO_USART2_RTS_2 +#define GPIO_USART2_CTS GPIO_USART2_CTS_2 + +/* USART6: + * RXD: PC7 CN5 pin2, CN10 pin 19 + * PA12 CN10, pin 12 + * TXD: PC6 CN10, pin 4 + * PA11 CN10, pin 14 + */ + +#define GPIO_USART6_RX (GPIO_USART6_RX_1|GPIO_SPEED_100MHz) /* PC7 */ +#define GPIO_USART6_TX (GPIO_USART6_TX_1|GPIO_SPEED_100MHz) /* PC6 */ + +/* UART RX DMA configurations */ + +#define DMAMAP_USART1_RX DMAMAP_USART1_RX_2 +#define DMAMAP_USART6_RX DMAMAP_USART6_RX_2 + +/* I2C + * + * The optional _GPIO configurations allow the I2C driver to manually + * reset the bus to clear stuck slaves. They match the pin configuration, + * but are normally-high GPIOs. + */ + +#define GPIO_I2C1_SCL (GPIO_I2C1_SCL_2|GPIO_SPEED_50MHz) +#define GPIO_I2C1_SDA (GPIO_I2C1_SDA_2|GPIO_SPEED_50MHz) +#define GPIO_I2C1_SCL_GPIO \ + (GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTB|GPIO_PIN8) +#define GPIO_I2C1_SDA_GPIO \ + (GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTB|GPIO_PIN9) + +#define GPIO_I2C2_SCL (GPIO_I2C2_SCL_1|GPIO_SPEED_50MHz) +#define GPIO_I2C2_SDA (GPIO_I2C2_SDA_1|GPIO_SPEED_50MHz) +#define GPIO_I2C2_SCL_GPIO \ + (GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTB|GPIO_PIN10) +#define GPIO_I2C2_SDA_GPIO \ + (GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTB|GPIO_PIN11) + +/* SPI + * + * There are sensors on SPI1, and SPI2 is connected to the FRAM. + */ + +#define GPIO_SPI1_MISO (GPIO_SPI1_MISO_1|GPIO_SPEED_50MHz) +#define GPIO_SPI1_MOSI (GPIO_SPI1_MOSI_1|GPIO_SPEED_50MHz) +#define GPIO_SPI1_SCK (GPIO_SPI1_SCK_1|GPIO_SPEED_50MHz) + +#define GPIO_SPI2_MISO (GPIO_SPI2_MISO_1|GPIO_SPEED_50MHz) +#define GPIO_SPI2_MOSI (GPIO_SPI2_MOSI_1|GPIO_SPEED_50MHz) +#define GPIO_SPI2_SCK (GPIO_SPI2_SCK_2|GPIO_SPEED_50MHz) + +/* LEDs + * + * The STM32F411E Discovery board has four user leds + * LD3 connected to PD13. + * LD4 connected to PD12. + * LD5 connected to PD14. + * LD6 connected to PD15. + */ + +/* LED index values for use with board_userled() */ + +#define BOARD_LD3 0 +#define BOARD_LD4 1 +#define BOARD_LD5 2 +#define BOARD_LD6 3 +#define BOARD_NLEDS 4 + +/* LED bits for use with board_userled_all() */ + +#define BOARD_LD3_BIT (1 << BOARD_LD3) +#define BOARD_LD4_BIT (1 << BOARD_LD4) +#define BOARD_LD5_BIT (1 << BOARD_LD5) +#define BOARD_LD6_BIT (1 << BOARD_LD6) + +/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the LED on board. + * The following definitions describe how NuttX controls + * the LEDs: + * + * SYMBOL Meaning LED + * ------------------- ---------------------------- -------------------- + */ + +#define LED_STARTED 0 /* NuttX has been started None */ +#define LED_HEAPALLOCATE 1 /* Heap has been allocated ON(1), OFF(2) */ +#define LED_IRQSENABLED 2 /* Interrupts enabled OFF(1), ON(2) */ +#define LED_STACKCREATED 3 /* Idle stack created ON(1), ON(2) */ +#define LED_INIRQ 4 /* In an interrupt (no change) */ +#define LED_SIGNAL 5 /* In a signal handler (no change) */ +#define LED_ASSERTION 6 /* An assertion failed ON(3) */ +#define LED_PANIC 7 /* The system has crashed FLASH(1,2) */ +#define LED_IDLE 8 /* idle loop FLASH(4) */ + +/* Buttons + * + * B1 USER: the user button is connected to the I/O PA0 of the STM32 + * microcontroller. + */ + +#define BUTTON_USER 0 +#define NUM_BUTTONS 1 + +#define BUTTON_USER_BIT (1 << BUTTON_USER) + +/* USB OTG FS */ + +#define GPIO_OTGFS_DM (GPIO_OTGFS_DM_0|GPIO_SPEED_100MHz) +#define GPIO_OTGFS_DP (GPIO_OTGFS_DP_0|GPIO_SPEED_100MHz) +#define GPIO_OTGFS_ID (GPIO_OTGFS_ID_0|GPIO_SPEED_100MHz) +#define GPIO_OTGFS_SOF (GPIO_OTGFS_SOF_0|GPIO_SPEED_100MHz) + +#endif /* __BOARDS_ARM_STM32_STM32F411E_DISCO_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32f4/stm32f411e-disco/scripts/Make.defs b/boards/arm/stm32f4/stm32f411e-disco/scripts/Make.defs new file mode 100644 index 0000000000000..6442599a8f6ac --- /dev/null +++ b/boards/arm/stm32f4/stm32f411e-disco/scripts/Make.defs @@ -0,0 +1,41 @@ +############################################################################ +# boards/arm/stm32f4/stm32f411e-disco/scripts/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/.config +include $(TOPDIR)/tools/Config.mk +include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs + +LDSCRIPT = f411ve.ld +ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) + +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32/stm32f411e-disco/scripts/f411ve.ld b/boards/arm/stm32f4/stm32f411e-disco/scripts/f411ve.ld similarity index 98% rename from boards/arm/stm32/stm32f411e-disco/scripts/f411ve.ld rename to boards/arm/stm32f4/stm32f411e-disco/scripts/f411ve.ld index 4f0e398e08585..a7ae15bdd1af0 100644 --- a/boards/arm/stm32/stm32f411e-disco/scripts/f411ve.ld +++ b/boards/arm/stm32f4/stm32f411e-disco/scripts/f411ve.ld @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f411e-disco/scripts/f411ve.ld + * boards/arm/stm32f4/stm32f411e-disco/scripts/f411ve.ld * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f4/stm32f411e-disco/src/CMakeLists.txt b/boards/arm/stm32f4/stm32f411e-disco/src/CMakeLists.txt new file mode 100644 index 0000000000000..d92b2d6fbc12d --- /dev/null +++ b/boards/arm/stm32f4/stm32f411e-disco/src/CMakeLists.txt @@ -0,0 +1,31 @@ +# ############################################################################## +# boards/arm/stm32f4/stm32f411e-disco/src/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(SRCS stm32_boot.c stm32_bringup.c) + +if(CONFIG_STM32_OTGFS) + list(APPEND SRCS stm32_usb.c) +endif() + +target_sources(board PRIVATE ${SRCS}) + +set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/f411ve.ld") diff --git a/boards/arm/stm32f4/stm32f411e-disco/src/Make.defs b/boards/arm/stm32f4/stm32f411e-disco/src/Make.defs new file mode 100644 index 0000000000000..d979394c3dd7a --- /dev/null +++ b/boards/arm/stm32f4/stm32f411e-disco/src/Make.defs @@ -0,0 +1,43 @@ +############################################################################ +# boards/arm/stm32f4/stm32f411e-disco/src/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +CSRCS = stm32_boot.c stm32_bringup.c + +ifeq ($(CONFIG_ARCH_BUTTONS),y) + CSRCS += stm32_buttons.c +endif + +ifeq ($(CONFIG_ARCH_LEDS),y) + CSRCS += stm32_autoleds.c +else + CSRCS += stm32_userleds.c +endif + +ifeq ($(CONFIG_STM32_OTGFS),y) +CSRCS += stm32_usb.c +endif + +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32f4/stm32f411e-disco/src/stm32_autoleds.c b/boards/arm/stm32f4/stm32f411e-disco/src/stm32_autoleds.c new file mode 100644 index 0000000000000..532620b9c1434 --- /dev/null +++ b/boards/arm/stm32f4/stm32f411e-disco/src/stm32_autoleds.c @@ -0,0 +1,134 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f411e-disco/src/stm32_autoleds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32.h" +#include "stm32f411e-disco.h" + +#ifdef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_autoled_initialize + ****************************************************************************/ + +void board_autoled_initialize(void) +{ + /* Configure LED GPIO for output */ + + stm32_configgpio(GPIO_LD3); + stm32_configgpio(GPIO_LD4); + stm32_configgpio(GPIO_LD5); + stm32_configgpio(GPIO_LD6); +} + +/**************************************************************************** + * Name: board_autoled_on + ****************************************************************************/ + +void board_autoled_on(int led) +{ + switch (led) + { + case LED_HEAPALLOCATE: + { + stm32_gpiowrite(GPIO_LD3, true); + stm32_gpiowrite(GPIO_LD4, false); + } + break; + + case LED_IRQSENABLED: + { + stm32_gpiowrite(GPIO_LD3, false); + stm32_gpiowrite(GPIO_LD4, true); + } + break; + + case LED_STACKCREATED: + { + stm32_gpiowrite(GPIO_LD3, true); + stm32_gpiowrite(GPIO_LD4, true); + } + break; + + case LED_ASSERTION: + { + stm32_gpiowrite(GPIO_LD5, true); + } + break; + + case LED_PANIC: + { + stm32_gpiowrite(GPIO_LD3, true); + stm32_gpiowrite(GPIO_LD4, true); + } + break; + + case LED_IDLE: + { + stm32_gpiowrite(GPIO_LD6, true); + } + break; + } +} + +/**************************************************************************** + * Name: board_autoled_off + ****************************************************************************/ + +void board_autoled_off(int led) +{ + switch (led) + { + case LED_PANIC: + { + stm32_gpiowrite(GPIO_LD3, false); + stm32_gpiowrite(GPIO_LD4, false); + } + break; + + case LED_IDLE: + { + stm32_gpiowrite(GPIO_LD6, false); + } + break; + } +} + +#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32f4/stm32f411e-disco/src/stm32_boot.c b/boards/arm/stm32f4/stm32f411e-disco/src/stm32_boot.c new file mode 100644 index 0000000000000..ba49ba9262d70 --- /dev/null +++ b/boards/arm/stm32f4/stm32f411e-disco/src/stm32_boot.c @@ -0,0 +1,101 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f411e-disco/src/stm32_boot.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include +#include + +#include + +#include "arm_internal.h" +#include "stm32f411e-disco.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_boardinitialize + * + * Description: + * All STM32 architectures must provide the following entry point. + * This entry point is called early in the initialization -- after all + * memory has been configured and mapped but before any devices have been + * initialized. + * + ****************************************************************************/ + +void stm32_boardinitialize(void) +{ +#ifdef CONFIG_ARCH_LEDS + /* Configure on-board LEDs if LED support has been selected. */ + + board_autoled_initialize(); +#endif + +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || \ + defined(CONFIG_STM32_SPI3) + /* Configure SPI chip selects if 1) SP2 is not disabled, and 2) the + * weak function stm32_spidev_initialize() has been brought into the link. + */ + + stm32_spidev_initialize(); +#endif + +#ifdef CONFIG_STM32_OTGFS + /* Initialize USB if the OTG FS controller is in the configuration. + * Presumably either CONFIG_USBDEV or CONFIG_USBHOST is also selected. + */ + + stm32_usbinitialize(); +#endif +} + +/**************************************************************************** + * Name: board_late_initialize + * + * Description: + * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_late_initialize(). board_late_initialize() will + * be called immediately after up_initialize() is called and just before + * the initial application is started. This additional initialization + * phase may be used, for example, to initialize board-specific device + * drivers. + * + ****************************************************************************/ + +#ifdef CONFIG_BOARD_LATE_INITIALIZE +void board_late_initialize(void) +{ + /* Perform board-specific initialization */ + + stm32_bringup(); +} +#endif diff --git a/boards/arm/stm32f4/stm32f411e-disco/src/stm32_bringup.c b/boards/arm/stm32f4/stm32f411e-disco/src/stm32_bringup.c new file mode 100644 index 0000000000000..8d104e05902f9 --- /dev/null +++ b/boards/arm/stm32f4/stm32f411e-disco/src/stm32_bringup.c @@ -0,0 +1,113 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f411e-disco/src/stm32_bringup.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include + +#include "stm32.h" + +#ifdef CONFIG_STM32_OTGFS +# include "stm32_usbhost.h" +#endif + +#ifdef CONFIG_INPUT_BUTTONS +# include +#endif + +#ifdef CONFIG_USERLED +# include +#endif + +#include "stm32f411e-disco.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_bringup + * + * Description: + * Perform architecture-specific initialization + * + * CONFIG_BOARD_LATE_INITIALIZE=y : + * Called from board_late_initialize(). + * + ****************************************************************************/ + +int stm32_bringup(void) +{ + int ret = OK; + +#if defined(CONFIG_STM32_OTGFS) && defined(CONFIG_USBHOST) + /* Initialize USB host operation. stm32_usbhost_initialize() starts + * a thread will monitor for USB connection and disconnection events. + */ + + ret = stm32_usbhost_initialize(); + if (ret != OK) + { + uerr("ERROR: Failed to initialize USB host: %d\n", ret); + return ret; + } +#endif + +#ifdef CONFIG_FS_PROCFS + /* Mount the procfs file system */ + + ret = nx_mount(NULL, STM32_PROCFS_MOUNTPOINT, "procfs", 0, NULL); + if (ret < 0) + { + ferr("ERROR: Failed to mount procfs at %s: %d\n", + STM32_PROCFS_MOUNTPOINT, ret); + } +#endif + +#ifdef CONFIG_USERLED + /* Register the LED driver */ + + ret = userled_lower_initialize("/dev/userleds"); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: userled_lower_initialize() failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_INPUT_BUTTONS + /* Register the BUTTON driver */ + + ret = btn_lower_initialize("/dev/buttons"); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: btn_lower_initialize() failed: %d\n", ret); + } +#endif + + return ret; +} diff --git a/boards/arm/stm32f4/stm32f411e-disco/src/stm32_buttons.c b/boards/arm/stm32f4/stm32f411e-disco/src/stm32_buttons.c new file mode 100644 index 0000000000000..458b4443786f6 --- /dev/null +++ b/boards/arm/stm32f4/stm32f411e-disco/src/stm32_buttons.c @@ -0,0 +1,160 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f411e-disco/src/stm32_buttons.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include +#include + +#include "stm32_gpio.h" +#include "stm32f411e-disco.h" + +#if defined(CONFIG_ARCH_BUTTONS) + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#if defined(CONFIG_INPUT_BUTTONS) && !defined(CONFIG_ARCH_IRQBUTTONS) +# error "The NuttX Buttons Driver depends on IRQ support to work!\n" +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/* Pin configuration for each STM32F3Discovery button. This array is indexed + * by the BUTTON_* definitions in board.h + */ + +static const uint32_t g_buttons[NUM_BUTTONS] = +{ + GPIO_BTN_USER +}; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_button_initialize + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. + * + ****************************************************************************/ + +uint32_t board_button_initialize(void) +{ + int i; + + /* Configure the GPIO pins as inputs. NOTE that EXTI interrupts are + * configured for all pins. + */ + + for (i = 0; i < NUM_BUTTONS; i++) + { + stm32_configgpio(g_buttons[i]); + } + + return NUM_BUTTONS; +} + +/**************************************************************************** + * Name: board_buttons + ****************************************************************************/ + +uint32_t board_buttons(void) +{ + uint32_t ret = 0; + int i; + + /* Check that state of each key */ + + for (i = 0; i < NUM_BUTTONS; i++) + { + /* A LOW value means that the key is pressed. */ + + bool released = stm32_gpioread(g_buttons[i]); + + /* Accumulate the set of depressed (not released) keys */ + + if (!released) + { + ret |= (1 << i); + } + } + + return ret; +} + +/**************************************************************************** + * Button support. + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. + * + * After board_button_initialize() has been called, board_buttons() may be + * called to collect the state of all buttons. board_buttons() returns + * an 32-bit bit set with each bit associated with a button. See the + * BUTTON_*_BIT definitions in board.h for the meaning of each bit. + * + * board_button_irq() may be called to register an interrupt handler that + * will be called when a button is depressed or released. The ID value is + * a button enumeration value that uniquely identifies a button resource. + * See the BUTTON_* definitions in board.h for the meaning of enumeration + * value. + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_IRQBUTTONS +int board_button_irq(int id, xcpt_t irqhandler, void *arg) +{ + int ret = -EINVAL; + + /* The following should be atomic */ + + if (id >= MIN_IRQBUTTON && id <= MAX_IRQBUTTON) + { + ret = stm32_gpiosetevent(g_buttons[id], true, true, true, irqhandler, + arg); + } + + return ret; +} +#endif + +#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/stm32f4/stm32f411e-disco/src/stm32_usb.c b/boards/arm/stm32f4/stm32f411e-disco/src/stm32_usb.c new file mode 100644 index 0000000000000..3434d64f9eb48 --- /dev/null +++ b/boards/arm/stm32f4/stm32f411e-disco/src/stm32_usb.c @@ -0,0 +1,353 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f411e-disco/src/stm32_usb.c + * + * SPDX-License-Identifier: BSD-3-Clause + * SPDX-FileCopyrightText: 2017 Gregory Nutt. All rights reserved. + * SPDX-FileCopyrightText: 2017 Brian Webb. All rights reserved. + * SPDX-FileContributor: Gregory Nutt + * SPDX-FileContributor: Brian Webb + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include "arm_internal.h" +#include "stm32.h" +#include "stm32_otgfs.h" +#include "stm32f411e-disco.h" + +#ifdef CONFIG_STM32_OTGFS + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#if !defined(CONFIG_USBDEV) && !defined(CONFIG_USBHOST) +# warning "CONFIG_STM32_OTGFS is enabled but neither CONFIG_USBDEV nor CONFIG_USBHOST" +#endif + +#ifndef CONFIG_STM32F411DISCO_USBHOST_PRIO +# define CONFIG_STM32F411DISCO_USBHOST_PRIO 100 +#endif + +#ifndef CONFIG_STM32F411DISCO_USBHOST_STACKSIZE +# define CONFIG_STM32F411DISCO_USBHOST_STACKSIZE 1024 +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +static struct usbhost_connection_s *g_usbconn; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: usbhost_waiter + * + * Description: + * Wait for USB devices to be connected. + * + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +static int usbhost_waiter(int argc, char *argv[]) +{ + struct usbhost_hubport_s *hport; + + uinfo("Running\n"); + for (; ; ) + { + /* Wait for the device to change state */ + + DEBUGVERIFY(CONN_WAIT(g_usbconn, &hport)); + uinfo("%s\n", hport->connected ? "connected" : "disconnected"); + + /* Did we just become connected? */ + + if (hport->connected) + { + /* Yes.. enumerate the newly connected device */ + + CONN_ENUMERATE(g_usbconn, hport); + } + } + + /* Keep the compiler from complaining */ + + return 0; +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_usbinitialize + * + * Description: + * Called from stm32_usbinitialize very early in initialization to setup + * USB-related GPIO pins for the STM32F411 board. + * + ****************************************************************************/ + +void stm32_usbinitialize(void) +{ + /* The OTG FS has an internal soft pull-up. + * No GPIO configuration is required + */ + + /* Configure the OTG FS VBUS sensing GPIO, + * Power On, and Overcurrent GPIOs + */ + +#ifdef CONFIG_STM32_OTGFS + stm32_configgpio(GPIO_OTGFS_VBUS); + stm32_configgpio(GPIO_OTGFS_PWRON); + stm32_configgpio(GPIO_OTGFS_OVER); +#endif +} + +/**************************************************************************** + * Name: stm32_usbhost_initialize + * + * Description: + * Called at application startup time to initialize the USB host + * functionality. + * This function will start a thread that will monitor for device + * connection/disconnection events. + * + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +int stm32_usbhost_initialize(void) +{ + int ret; + + /* First, register all of the class drivers needed to support the drivers + * that we care about: + */ + + uinfo("Register class drivers\n"); + +#ifdef CONFIG_USBHOST_HUB + /* Initialize USB hub class support */ + + ret = usbhost_hub_initialize(); + if (ret < 0) + { + uerr("ERROR: usbhost_hub_initialize failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_USBHOST_MSC + /* Register the USB mass storage class class */ + + ret = usbhost_msc_initialize(); + if (ret != OK) + { + uerr("ERROR: Failed to register the mass storage class: %d\n", ret); + } +#endif + +#ifdef CONFIG_USBHOST_CDCACM + /* Register the CDC/ACM serial class */ + + ret = usbhost_cdcacm_initialize(); + if (ret != OK) + { + uerr("ERROR: Failed to register the CDC/ACM serial class: %d\n", ret); + } +#endif + +#ifdef CONFIG_USBHOST_HIDKBD + /* Initialize the HID keyboard class */ + + ret = usbhost_kbdinit(); + if (ret != OK) + { + uerr("ERROR: Failed to register the HID keyboard class\n"); + } +#endif + +#ifdef CONFIG_USBHOST_HIDMOUSE + /* Initialize the HID mouse class */ + + ret = usbhost_mouse_init(); + if (ret != OK) + { + uerr("ERROR: Failed to register the HID mouse class\n"); + } +#endif + +#ifdef CONFIG_USBHOST_XBOXCONTROLLER + /* Initialize the HID mouse class */ + + ret = usbhost_xboxcontroller_init(); + if (ret != OK) + { + uerr("ERROR: Failed to register the XBox Controller class\n"); + } +#endif + + /* Then get an instance of the USB host interface */ + + uinfo("Initialize USB host\n"); + g_usbconn = stm32_otgfshost_initialize(0); + if (g_usbconn) + { + /* Start a thread to handle device connection. */ + + uinfo("Start usbhost_waiter\n"); + + ret = kthread_create("usbhost", CONFIG_STM32F411DISCO_USBHOST_PRIO, + CONFIG_STM32F411DISCO_USBHOST_STACKSIZE, + usbhost_waiter, NULL); + return ret < 0 ? -ENOEXEC : OK; + } + + return -ENODEV; +} +#endif + +/**************************************************************************** + * Name: stm32_usbhost_vbusdrive + * + * Description: + * Enable/disable driving of VBUS 5V output. This function must be + * provided be each platform that implements the STM32 OTG FS host + * interface + * + * "On-chip 5 V VBUS generation is not supported. For this reason, a + * charge pump or, if 5 V are available on the application board, a + * basic power switch, must be added externally to drive the 5 V VBUS + * line. The external charge pump can be driven by any GPIO output. + * When the application decides to power on VBUS using the chosen GPIO, + * it must also set the port power bit in the host port control and + * status register (PPWR bit in OTG_FS_HPRT). + * + * "The application uses this field to control power to this port, + * and the core clears this bit on an overcurrent condition." + * + * Input Parameters: + * iface - For future growth to handle multiple USB host interface. + * Should be zero. + * enable - true: enable VBUS power; false: disable VBUS power + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +void stm32_usbhost_vbusdrive(int iface, bool enable) +{ + DEBUGASSERT(iface == 0); + + if (enable) + { + /* Enable the Power Switch by driving the enable pin low */ + + stm32_gpiowrite(GPIO_OTGFS_PWRON, false); + } + else + { + /* Disable the Power Switch by driving the enable pin high */ + + stm32_gpiowrite(GPIO_OTGFS_PWRON, true); + } +} +#endif + +/**************************************************************************** + * Name: stm32_setup_overcurrent + * + * Description: + * Setup to receive an interrupt-level callback if an overcurrent + * condition is detected. + * + * Input Parameters: + * handler - New overcurrent interrupt handler + * arg - The argument provided for the interrupt handler + * + * Returned Value: + * Zero (OK) is returned on success. Otherwise, a negated errno value + * is returned to indicate the nature of the failure. + * + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +int stm32_setup_overcurrent(xcpt_t handler, void *arg) +{ + return stm32_gpiosetevent(GPIO_OTGFS_OVER, true, true, true, handler, arg); +} +#endif + +/**************************************************************************** + * Name: stm32_usbsuspend + * + * Description: + * Board logic must provide the stm32_usbsuspend logic if the USBDEV + * driver is used. This function is called whenever the USB enters or + * leaves suspend mode. This is an opportunity for the board logic to + * shutdown clocks, power, etc. while the USB is suspended. + * + ****************************************************************************/ + +#ifdef CONFIG_USBDEV +void stm32_usbsuspend(struct usbdev_s *dev, bool resume) +{ + uinfo("resume: %d\n", resume); +} +#endif + +#endif /* CONFIG_STM32_OTGFS */ diff --git a/boards/arm/stm32f4/stm32f411e-disco/src/stm32_userleds.c b/boards/arm/stm32f4/stm32f411e-disco/src/stm32_userleds.c new file mode 100644 index 0000000000000..7a080b429835e --- /dev/null +++ b/boards/arm/stm32f4/stm32f411e-disco/src/stm32_userleds.c @@ -0,0 +1,105 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f411e-disco/src/stm32_userleds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include + +#include "chip.h" +#include "stm32.h" +#include "stm32f411e-disco.h" + +#ifndef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* This array maps an LED number to GPIO pin configuration */ + +static const uint32_t g_ledcfg[BOARD_NLEDS] = +{ + GPIO_LD3, + GPIO_LD4, + GPIO_LD5, + GPIO_LD6, +}; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_userled_initialize + ****************************************************************************/ + +uint32_t board_userled_initialize(void) +{ + int i; + + /* Configure LED GPIOs for output */ + + for (i = 0; i < BOARD_NLEDS; i++) + { + stm32_configgpio(g_ledcfg[i]); + } + + return BOARD_NLEDS; +} + +/**************************************************************************** + * Name: board_userled + ****************************************************************************/ + +void board_userled(int led, bool ledon) +{ + if ((unsigned)led < BOARD_NLEDS) + { + stm32_gpiowrite(g_ledcfg[led], ledon); + } +} + +/**************************************************************************** + * Name: board_userled_all + ****************************************************************************/ + +void board_userled_all(uint32_t ledset) +{ + int i; + + /* Configure LED GPIOs for output */ + + for (i = 0; i < BOARD_NLEDS; i++) + { + stm32_gpiowrite(g_ledcfg[i], (ledset & (1 << i)) != 0); + } +} + +#endif /* !CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/stm32f411e-disco/src/stm32f411e-disco.h b/boards/arm/stm32f4/stm32f411e-disco/src/stm32f411e-disco.h similarity index 99% rename from boards/arm/stm32/stm32f411e-disco/src/stm32f411e-disco.h rename to boards/arm/stm32f4/stm32f411e-disco/src/stm32f411e-disco.h index 993efb33dd7ba..625a7d463f336 100644 --- a/boards/arm/stm32/stm32f411e-disco/src/stm32f411e-disco.h +++ b/boards/arm/stm32f4/stm32f411e-disco/src/stm32f411e-disco.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f411e-disco/src/stm32f411e-disco.h + * boards/arm/stm32f4/stm32f411e-disco/src/stm32f411e-disco.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f4/stm32f429i-disco/CMakeLists.txt b/boards/arm/stm32f4/stm32f429i-disco/CMakeLists.txt new file mode 100644 index 0000000000000..581e2ba994ac2 --- /dev/null +++ b/boards/arm/stm32f4/stm32f429i-disco/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32f4/stm32f429i-disco/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/arm/stm32/stm32f429i-disco/Kconfig b/boards/arm/stm32f4/stm32f429i-disco/Kconfig similarity index 100% rename from boards/arm/stm32/stm32f429i-disco/Kconfig rename to boards/arm/stm32f4/stm32f429i-disco/Kconfig diff --git a/boards/arm/stm32f4/stm32f429i-disco/configs/adc/defconfig b/boards/arm/stm32f4/stm32f429i-disco/configs/adc/defconfig new file mode 100644 index 0000000000000..7a06ad371b54a --- /dev/null +++ b/boards/arm/stm32f4/stm32f429i-disco/configs/adc/defconfig @@ -0,0 +1,63 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_STM32_CCMEXCLUDE is not set +# CONFIG_STM32_FLASH_PREFETCH is not set +CONFIG_ADC=y +CONFIG_ANALOG=y +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f429i-disco" +CONFIG_ARCH_BOARD_STM32F429I_DISCO=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F429Z=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_EXAMPLES_ADC=y +CONFIG_EXAMPLES_ADC_GROUPSIZE=3 +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_HEAP2_BASE=0xD0000000 +CONFIG_HEAP2_SIZE=8388608 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_MM_REGIONS=3 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_STM32_ADC1=y +CONFIG_STM32_ADC1_DMA=y +CONFIG_STM32_ADC3=y +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_DMA1=y +CONFIG_STM32_DMA2=y +CONFIG_STM32_EXTERNAL_RAM=y +CONFIG_STM32_FMC=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_PWR=y +CONFIG_STM32_TIM1=y +CONFIG_STM32_TIM1_ADC=y +CONFIG_STM32_USART1=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f4/stm32f429i-disco/configs/bootlogo/defconfig b/boards/arm/stm32f4/stm32f429i-disco/configs/bootlogo/defconfig new file mode 100644 index 0000000000000..5610e2c3f0611 --- /dev/null +++ b/boards/arm/stm32f4/stm32f429i-disco/configs/bootlogo/defconfig @@ -0,0 +1,84 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_STM32_FB_CMAP is not set +# CONFIG_STM32_FLASH_PREFETCH is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f429i-disco" +CONFIG_ARCH_BOARD_STM32F429I_DISCO=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F429Z=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_DRIVERS_VIDEO=y +CONFIG_EXAMPLES_FB=y +CONFIG_EXAMPLES_FBOVERLAY=y +CONFIG_EXAMPLES_TOUCHSCREEN=y +CONFIG_FB_OVERLAY_BLIT=y +CONFIG_FB_SYNC=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_HEAP2_BASE=0xD0000000 +CONFIG_HEAP2_SIZE=7774208 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INPUT=y +CONFIG_INPUT_STMPE811=y +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=128 +CONFIG_MM_REGIONS=2 +CONFIG_MQ_MAXMSGSIZE=64 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_MAXARGUMENTS=17 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_WAITPID=y +CONFIG_SPI_CMDDATA=y +CONFIG_START_DAY=15 +CONFIG_START_MONTH=11 +CONFIG_START_YEAR=2017 +CONFIG_STM32F429I_DISCO_ILI9341=y +CONFIG_STM32_CCMEXCLUDE=y +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_DMA2D=y +CONFIG_STM32_DMA2D_FB_BASE=0xD07B5000 +CONFIG_STM32_DMA2D_FB_SIZE=307200 +CONFIG_STM32_DMA2D_LAYER_PPLINE=240 +CONFIG_STM32_DMA2D_NLAYERS=2 +CONFIG_STM32_EXTERNAL_RAM=y +CONFIG_STM32_FMC=y +CONFIG_STM32_I2C3=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_LTDC=y +CONFIG_STM32_LTDC_FB_BASE=0xD076A000 +CONFIG_STM32_LTDC_FB_SIZE=307200 +CONFIG_STM32_PWR=y +CONFIG_STM32_SPI5=y +CONFIG_STM32_USART1=y +CONFIG_STMPE811_ACTIVELOW=y +CONFIG_STMPE811_EDGE=y +CONFIG_STMPE811_THRESHX=39 +CONFIG_STMPE811_THRESHY=51 +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART1_SERIAL_CONSOLE=y +CONFIG_VIDEO_FB=y +CONFIG_VIDEO_FB_SPLASHSCREEN=y +CONFIG_VIDEO_FB_SPLASHSCREEN_BPP16=y +CONFIG_VIDEO_FB_SPLASHSCREEN_DISP_TIME=2 diff --git a/boards/arm/stm32f4/stm32f429i-disco/configs/extflash/defconfig b/boards/arm/stm32f4/stm32f429i-disco/configs/extflash/defconfig new file mode 100644 index 0000000000000..f35ce2450e611 --- /dev/null +++ b/boards/arm/stm32f4/stm32f429i-disco/configs/extflash/defconfig @@ -0,0 +1,65 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_STM32_FLASH_PREFETCH is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f429i-disco" +CONFIG_ARCH_BOARD_STM32F429I_DISCO=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F429Z=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_HEAP2_BASE=0xD0000000 +CONFIG_HEAP2_SIZE=8388608 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_MM_REGIONS=3 +CONFIG_MTD_CONFIG=y +CONFIG_MTD_CONFIG_RAM_CONSOLIDATE=y +CONFIG_MTD_PARTITION=y +CONFIG_MTD_PARTITION_NAMES=y +CONFIG_MTD_SMART_SECTOR_SIZE=512 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PLATFORM_CONFIGDATA=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_SMARTFS_MULTI_ROOT_DIRS=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_STM32F429I_DISCO_FLASH=y +CONFIG_STM32F429I_DISCO_FLASH_PART=y +CONFIG_STM32F429I_DISCO_RAMMTD=y +CONFIG_STM32F429I_DISCO_RAMMTD_SIZE=256 +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_EXTERNAL_RAM=y +CONFIG_STM32_FMC=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_PWR=y +CONFIG_STM32_RNG=y +CONFIG_STM32_SPI5=y +CONFIG_STM32_USART1=y +CONFIG_SYSTEM_FLASH_ERASEALL=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f4/stm32f429i-disco/configs/fb/defconfig b/boards/arm/stm32f4/stm32f429i-disco/configs/fb/defconfig new file mode 100644 index 0000000000000..e61f766cb1fcb --- /dev/null +++ b/boards/arm/stm32f4/stm32f429i-disco/configs/fb/defconfig @@ -0,0 +1,81 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_STM32_FB_CMAP is not set +# CONFIG_STM32_FLASH_PREFETCH is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f429i-disco" +CONFIG_ARCH_BOARD_STM32F429I_DISCO=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F429Z=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_DRIVERS_VIDEO=y +CONFIG_EXAMPLES_FB=y +CONFIG_EXAMPLES_FBOVERLAY=y +CONFIG_EXAMPLES_TOUCHSCREEN=y +CONFIG_FB_OVERLAY_BLIT=y +CONFIG_FB_SYNC=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_HEAP2_BASE=0xD0000000 +CONFIG_HEAP2_SIZE=7774208 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INPUT=y +CONFIG_INPUT_STMPE811=y +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=128 +CONFIG_MM_REGIONS=2 +CONFIG_MQ_MAXMSGSIZE=64 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_MAXARGUMENTS=17 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_WAITPID=y +CONFIG_SPI_CMDDATA=y +CONFIG_START_DAY=15 +CONFIG_START_MONTH=11 +CONFIG_START_YEAR=2017 +CONFIG_STM32F429I_DISCO_ILI9341=y +CONFIG_STM32_CCMEXCLUDE=y +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_DMA2D=y +CONFIG_STM32_DMA2D_FB_BASE=0xD07B5000 +CONFIG_STM32_DMA2D_FB_SIZE=307200 +CONFIG_STM32_DMA2D_LAYER_PPLINE=240 +CONFIG_STM32_DMA2D_NLAYERS=2 +CONFIG_STM32_EXTERNAL_RAM=y +CONFIG_STM32_FMC=y +CONFIG_STM32_I2C3=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_LTDC=y +CONFIG_STM32_LTDC_FB_BASE=0xD076A000 +CONFIG_STM32_LTDC_FB_SIZE=307200 +CONFIG_STM32_PWR=y +CONFIG_STM32_SPI5=y +CONFIG_STM32_USART1=y +CONFIG_STMPE811_ACTIVELOW=y +CONFIG_STMPE811_EDGE=y +CONFIG_STMPE811_THRESHX=39 +CONFIG_STMPE811_THRESHY=51 +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART1_SERIAL_CONSOLE=y +CONFIG_VIDEO_FB=y diff --git a/boards/arm/stm32f4/stm32f429i-disco/configs/gdbstub/defconfig b/boards/arm/stm32f4/stm32f429i-disco/configs/gdbstub/defconfig new file mode 100644 index 0000000000000..f44bd74c69d74 --- /dev/null +++ b/boards/arm/stm32f4/stm32f429i-disco/configs/gdbstub/defconfig @@ -0,0 +1,59 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_LIBC_FLOATINGPOINT is not set +# CONFIG_NSH_DISABLE_MW is not set +# CONFIG_STM32_FLASH_PREFETCH is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f429i-disco" +CONFIG_ARCH_BOARD_STM32F429I_DISCO=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F429Z=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_INTERRUPTSTACK=4096 +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_DEBUG_FEATURES=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_HEAP2_BASE=0xD0000000 +CONFIG_HEAP2_SIZE=8388608 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LIB_GDBSTUB=y +CONFIG_LIB_GDBSTUB_DEBUG=y +CONFIG_LINE_MAX=64 +CONFIG_MM_REGIONS=3 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_SERIAL_GDBSTUB=y +CONFIG_SPI=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_EXTERNAL_RAM=y +CONFIG_STM32_FMC=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_PWR=y +CONFIG_STM32_USART1=y +CONFIG_STM32_USART3=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f4/stm32f429i-disco/configs/highpri/defconfig b/boards/arm/stm32f4/stm32f429i-disco/configs/highpri/defconfig new file mode 100644 index 0000000000000..24deb19b35120 --- /dev/null +++ b/boards/arm/stm32f4/stm32f429i-disco/configs/highpri/defconfig @@ -0,0 +1,60 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_STM32_FLASH_PREFETCH is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f429i-disco" +CONFIG_ARCH_BOARD_STM32F429I_DISCO=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F429Z=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_HIPRI_INTERRUPT=y +CONFIG_ARCH_RAMVECTORS=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_DEBUG_NOOPT=y +CONFIG_HAVE_CXX=y +CONFIG_HEAP2_BASE=0xD0000000 +CONFIG_HEAP2_SIZE=8388608 +CONFIG_INIT_ENTRYPOINT="highpri_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBM=y +CONFIG_MM_REGIONS=2 +CONFIG_PREALLOC_TIMERS=4 +CONFIG_PWM=y +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_STM32F429I_DISCO_HIGHPRI=y +CONFIG_STM32_ADC1=y +CONFIG_STM32_ADC1_DMA=y +CONFIG_STM32_ADC1_DMA_CFG=1 +CONFIG_STM32_ADC1_EXTSEL=y +CONFIG_STM32_ADC1_INJECTED_CHAN=1 +CONFIG_STM32_ADC_LL_OPS=y +CONFIG_STM32_ADC_NOIRQ=y +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_DMA2=y +CONFIG_STM32_EXTERNAL_RAM=y +CONFIG_STM32_FMC=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_PWM_LL_OPS=y +CONFIG_STM32_PWR=y +CONFIG_STM32_TIM1=y +CONFIG_STM32_TIM1_PWM=y +CONFIG_STM32_USART1=y +CONFIG_SYSTEM_READLINE=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f4/stm32f429i-disco/configs/lcd/defconfig b/boards/arm/stm32f4/stm32f429i-disco/configs/lcd/defconfig new file mode 100644 index 0000000000000..dd6fdbb3aab40 --- /dev/null +++ b/boards/arm/stm32f4/stm32f429i-disco/configs/lcd/defconfig @@ -0,0 +1,66 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_NXFONTS_DISABLE_16BPP is not set +# CONFIG_NX_DISABLE_16BPP is not set +# CONFIG_STM32_FLASH_PREFETCH is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f429i-disco" +CONFIG_ARCH_BOARD_STM32F429I_DISCO=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F429Z=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_DEBUG_CUSTOMOPT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_EXAMPLES_NX=y +CONFIG_EXAMPLES_NX_BPP=16 +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_HEAP2_BASE=0xD0000000 +CONFIG_HEAP2_SIZE=8388608 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LCD=y +CONFIG_LCD_ILI9341=y +CONFIG_LCD_ILI9341_IFACE0=y +CONFIG_LINE_MAX=64 +CONFIG_MM_REGIONS=3 +CONFIG_MQ_MAXMSGSIZE=64 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_NX=y +CONFIG_NXFONT_MONO5X8=y +CONFIG_NX_BLOCKING=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_STM32F429I_DISCO_ILI9341=y +CONFIG_STM32F429I_DISCO_ILI9341_SPIBITS16=y +CONFIG_STM32F429I_DISCO_ILI9341_SPIFREQUENCY=20000000 +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_EXTERNAL_RAM=y +CONFIG_STM32_FMC=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_PWR=y +CONFIG_STM32_USART1=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f4/stm32f429i-disco/configs/lvgl/defconfig b/boards/arm/stm32f4/stm32f429i-disco/configs/lvgl/defconfig new file mode 100644 index 0000000000000..91927fed1227d --- /dev/null +++ b/boards/arm/stm32f4/stm32f429i-disco/configs/lvgl/defconfig @@ -0,0 +1,84 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_LV_BUILD_EXAMPLES is not set +# CONFIG_STM32_FB_CMAP is not set +# CONFIG_STM32_FLASH_PREFETCH is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f429i-disco" +CONFIG_ARCH_BOARD_STM32F429I_DISCO=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F429Z=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_DEBUG_CUSTOMOPT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_DRIVERS_VIDEO=y +CONFIG_EXAMPLES_FB=y +CONFIG_EXAMPLES_LVGLDEMO=y +CONFIG_EXAMPLES_TOUCHSCREEN=y +CONFIG_FB_OVERLAY=y +CONFIG_FS_PROCFS=y +CONFIG_GRAPHICS_LVGL=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_HEAP2_BASE=0xD0000000 +CONFIG_HEAP2_SIZE=8081408 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INPUT=y +CONFIG_INPUT_STMPE811=y +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_LV_USE_CLIB_MALLOC=y +CONFIG_LV_USE_CLIB_SPRINTF=y +CONFIG_LV_USE_CLIB_STRING=y +CONFIG_LV_USE_DEMO_WIDGETS=y +CONFIG_LV_USE_LOG=y +CONFIG_LV_USE_NUTTX=y +CONFIG_LV_USE_NUTTX_TOUCHSCREEN=y +CONFIG_MM_REGIONS=2 +CONFIG_MQ_MAXMSGSIZE=64 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_WAITPID=y +CONFIG_SPI_CMDDATA=y +CONFIG_START_DAY=15 +CONFIG_START_MONTH=11 +CONFIG_START_YEAR=2017 +CONFIG_STM32F429I_DISCO_ILI9341=y +CONFIG_STM32_CCMEXCLUDE=y +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_EXTERNAL_RAM=y +CONFIG_STM32_FMC=y +CONFIG_STM32_I2C3=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_LTDC=y +CONFIG_STM32_LTDC_FB_BASE=0xD07B5000 +CONFIG_STM32_LTDC_FB_SIZE=307200 +CONFIG_STM32_PWR=y +CONFIG_STM32_SPI5=y +CONFIG_STM32_USART1=y +CONFIG_STMPE811_ACTIVELOW=y +CONFIG_STMPE811_EDGE=y +CONFIG_STMPE811_THRESHX=39 +CONFIG_STMPE811_THRESHY=51 +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART1_SERIAL_CONSOLE=y +CONFIG_VIDEO_FB=y diff --git a/boards/arm/stm32f4/stm32f429i-disco/configs/nsh/defconfig b/boards/arm/stm32f4/stm32f429i-disco/configs/nsh/defconfig new file mode 100644 index 0000000000000..fec735c9fa5c8 --- /dev/null +++ b/boards/arm/stm32f4/stm32f429i-disco/configs/nsh/defconfig @@ -0,0 +1,52 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_STM32_FLASH_PREFETCH is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f429i-disco" +CONFIG_ARCH_BOARD_STM32F429I_DISCO=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F429Z=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_HEAP2_BASE=0xD0000000 +CONFIG_HEAP2_SIZE=8388608 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_MM_REGIONS=3 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_SPI=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_EXTERNAL_RAM=y +CONFIG_STM32_FMC=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_PWR=y +CONFIG_STM32_USART1=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f4/stm32f429i-disco/configs/nxhello/defconfig b/boards/arm/stm32f4/stm32f429i-disco/configs/nxhello/defconfig new file mode 100644 index 0000000000000..de8144a44945c --- /dev/null +++ b/boards/arm/stm32f4/stm32f429i-disco/configs/nxhello/defconfig @@ -0,0 +1,76 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_ARCH_LEDS is not set +# CONFIG_NXFONTS_DISABLE_16BPP is not set +# CONFIG_NX_DISABLE_16BPP is not set +# CONFIG_STM32_FB_CMAP is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f429i-disco" +CONFIG_ARCH_BOARD_STM32F429I_DISCO=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F429Z=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_DEV_LOOP=y +CONFIG_DRIVERS_VIDEO=y +CONFIG_EXAMPLES_NXHELLO=y +CONFIG_EXAMPLES_NXHELLO_BPP=16 +CONFIG_EXAMPLES_NXHELLO_SERVERPRIO=110 +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_HEAP2_BASE=0xD0000000 +CONFIG_HEAP2_SIZE=8388608 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_MAX_EXITFUNS=1 +CONFIG_LINE_MAX=64 +CONFIG_MM_REGIONS=3 +CONFIG_MQ_MAXMSGSIZE=64 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_NX=y +CONFIG_NXFONT_SANS22X29B=y +CONFIG_NX_BLOCKING=y +CONFIG_NX_WRITEONLY=y +CONFIG_NX_XYINPUT_TOUCHSCREEN=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=214688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=7 +CONFIG_START_MONTH=2 +CONFIG_START_YEAR=2019 +CONFIG_STM32F429I_DISCO_ILI9341=y +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_DMA2D=y +CONFIG_STM32_DMA2D_FB_BASE=0xD07B5000 +CONFIG_STM32_DMA2D_FB_SIZE=307200 +CONFIG_STM32_DMA2D_LAYER_PPLINE=240 +CONFIG_STM32_DMA2D_NLAYERS=2 +CONFIG_STM32_EXTERNAL_RAM=y +CONFIG_STM32_FMC=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_LTDC=y +CONFIG_STM32_LTDC_FB_BASE=0xD076A000 +CONFIG_STM32_LTDC_FB_SIZE=307200 +CONFIG_STM32_PWR=y +CONFIG_STM32_USART1=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART1_SERIAL_CONSOLE=y +CONFIG_VIDEO_FB=y diff --git a/boards/arm/stm32f4/stm32f429i-disco/configs/nxwm/defconfig b/boards/arm/stm32f4/stm32f429i-disco/configs/nxwm/defconfig new file mode 100644 index 0000000000000..571440c8d6748 --- /dev/null +++ b/boards/arm/stm32f4/stm32f429i-disco/configs/nxwm/defconfig @@ -0,0 +1,112 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_NXFONTS_DISABLE_16BPP is not set +# CONFIG_NXTK_DEFAULT_BORDERCOLORS is not set +# CONFIG_NX_DISABLE_16BPP is not set +# CONFIG_STM32_FLASH_PREFETCH is not set +# CONFIG_STM32_LTDC_L2 is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f429i-disco" +CONFIG_ARCH_BOARD_STM32F429I_DISCO=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F429Z=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_DEBUG_CUSTOMOPT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_DRIVERS_VIDEO=y +CONFIG_FAT_LCNAMES=y +CONFIG_FAT_LFN=y +CONFIG_FB_OVERLAY=y +CONFIG_FS_FAT=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_HEAP2_BASE=0xd0000000 +CONFIG_HEAP2_SIZE=8081408 +CONFIG_INIT_ENTRYPOINT="nxwm_main" +CONFIG_INPUT=y +CONFIG_INPUT_STMPE811=y +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_MAX_EXITFUNS=1 +CONFIG_LINE_MAX=64 +CONFIG_MM_REGIONS=2 +CONFIG_MQ_MAXMSGSIZE=64 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_LIBRARY=y +CONFIG_NSH_READLINE=y +CONFIG_NX=y +CONFIG_NXFONT_SANS22X29B=y +CONFIG_NXFONT_SANS23X27=y +CONFIG_NXTERM=y +CONFIG_NXTERM_CACHESIZE=32 +CONFIG_NXTERM_CURSORCHAR=95 +CONFIG_NXTERM_MXCHARS=325 +CONFIG_NXTERM_NXKBDIN=y +CONFIG_NXTK_BORDERCOLOR1=0x5cb7 +CONFIG_NXTK_BORDERCOLOR2=0x21c9 +CONFIG_NXTK_BORDERCOLOR3=0xffdf +CONFIG_NXWIDGETS=y +CONFIG_NXWIDGETS_BPP=16 +CONFIG_NXWIDGETS_CUSTOM_EDGECOLORS=y +CONFIG_NXWIDGETS_CUSTOM_FILLCOLORS=y +CONFIG_NXWIDGETS_DEFAULT_BACKGROUNDCOLOR=0x9dfb +CONFIG_NXWIDGETS_DEFAULT_HIGHLIGHTCOLOR=0xc618 +CONFIG_NXWIDGETS_DEFAULT_SELECTEDBACKGROUNDCOLOR=0xd73e +CONFIG_NXWIDGETS_DEFAULT_SHADOWEDGECOLOR=0x21e9 +CONFIG_NXWIDGETS_DEFAULT_SHINEEDGECOLOR=0xffdf +CONFIG_NXWIDGETS_SIZEOFCHAR=1 +CONFIG_NXWM=y +CONFIG_NXWM_CALIBRATION_AVERAGE=y +CONFIG_NXWM_CALIBRATION_MESSAGES=y +CONFIG_NXWM_CALIBRATION_NSAMPLES=2 +CONFIG_NXWM_HEXCALCULATOR_CUSTOM_FONTID=y +CONFIG_NXWM_HEXCALCULATOR_FONTID=5 +CONFIG_NXWM_KEYBOARD=y +CONFIG_NXWM_TASKBAR_LEFT=y +CONFIG_NXWM_TASKBAR_VSPACING=4 +CONFIG_NXWM_TOUCHSCREEN_LISTENERSTACK=1596 +CONFIG_NX_BLOCKING=y +CONFIG_NX_KBD=y +CONFIG_NX_XYINPUT_TOUCHSCREEN=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=192 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=15 +CONFIG_START_MONTH=11 +CONFIG_STM32F429I_DISCO_ILI9341=y +CONFIG_STM32_CCMEXCLUDE=y +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_EXTERNAL_RAM=y +CONFIG_STM32_FMC=y +CONFIG_STM32_I2C3=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_LTDC=y +CONFIG_STM32_LTDC_FB_BASE=0xD07B5000 +CONFIG_STM32_LTDC_FB_SIZE=307200 +CONFIG_STM32_PWR=y +CONFIG_STM32_USART1=y +CONFIG_STMPE811_ACTIVELOW=y +CONFIG_STMPE811_EDGE=y +CONFIG_STMPE811_THRESHX=39 +CONFIG_STMPE811_THRESHY=51 +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART1_SERIAL_CONSOLE=y +CONFIG_VIDEO_FB=y diff --git a/boards/arm/stm32f4/stm32f429i-disco/configs/ofloader/defconfig b/boards/arm/stm32f4/stm32f429i-disco/configs/ofloader/defconfig new file mode 100644 index 0000000000000..962af638709ee --- /dev/null +++ b/boards/arm/stm32f4/stm32f429i-disco/configs/ofloader/defconfig @@ -0,0 +1,57 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_STM32_FLASH_PREFETCH is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f429i-disco" +CONFIG_ARCH_BOARD_STM32F429I_DISCO=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F429Z=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BCH=y +CONFIG_BOARDCTL=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_DRVR_MKRD=y +CONFIG_FRAME_POINTER=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_HEAP2_BASE=0xD0000000 +CONFIG_HEAP2_SIZE=8388608 +CONFIG_INIT_ENTRYNAME="ofloader" +CONFIG_INIT_ENTRYPOINT="ofloader_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_MM_REGIONS=3 +CONFIG_MTD=y +CONFIG_MTD_PROGMEM=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_EXTERNAL_RAM=y +CONFIG_STM32_FLASH_CONFIG_I=y +CONFIG_STM32_FMC=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_USART1=y +CONFIG_SYSTEM_OFLOADER=y +CONFIG_SYSTEM_OFLOADER_BUFFERSIZE=4096 +CONFIG_SYSTEM_OFLOADER_DEBUG=y +CONFIG_SYSTEM_OFLOADER_TABLE="/dev/flash,0x08000000,0x20000" +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f4/stm32f429i-disco/configs/stack/defconfig b/boards/arm/stm32f4/stm32f429i-disco/configs/stack/defconfig new file mode 100644 index 0000000000000..00451cde08cf0 --- /dev/null +++ b/boards/arm/stm32f4/stm32f429i-disco/configs/stack/defconfig @@ -0,0 +1,57 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_STM32_FLASH_PREFETCH is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f429i-disco" +CONFIG_ARCH_BOARD_STM32F429I_DISCO=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F429Z=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_INSTRUMENT_ALL=y +CONFIG_ARCH_INTERRUPTSTACK=4096 +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_HEAP2_BASE=0xD0000000 +CONFIG_HEAP2_SIZE=8388608 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_MM_REGIONS=3 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_BACKTRACE=y +CONFIG_SCHED_STACK_RECORD=32 +CONFIG_SCHED_WAITPID=y +CONFIG_SPI=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_EXTERNAL_RAM=y +CONFIG_STM32_FMC=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_PWR=y +CONFIG_STM32_USART1=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f4/stm32f429i-disco/configs/systemview/defconfig b/boards/arm/stm32f4/stm32f429i-disco/configs/systemview/defconfig new file mode 100644 index 0000000000000..03aff6f431858 --- /dev/null +++ b/boards/arm/stm32f4/stm32f429i-disco/configs/systemview/defconfig @@ -0,0 +1,68 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_DRIVERS_NOTERAM is not set +# CONFIG_SERIAL_RTT_CONSOLE is not set +# CONFIG_STANDARD_SERIAL is not set +# CONFIG_STM32_FLASH_PREFETCH is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f429i-disco" +CONFIG_ARCH_BOARD_STM32F429I_DISCO=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F429Z=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_DRIVERS_NOTE=y +CONFIG_DRIVERS_NOTE_TASKNAME_BUFSIZE=0 +CONFIG_EXAMPLES_NOTEPRINTF=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_HEAP2_BASE=0xD0000000 +CONFIG_HEAP2_SIZE=8388608 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_MM_REGIONS=3 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_INSTRUMENTATION=y +CONFIG_SCHED_INSTRUMENTATION_DUMP=y +CONFIG_SCHED_INSTRUMENTATION_HEAP=y +CONFIG_SCHED_INSTRUMENTATION_IRQHANDLER=y +CONFIG_SCHED_INSTRUMENTATION_SWITCH=y +CONFIG_SCHED_INSTRUMENTATION_WDOG=y +CONFIG_SEGGER_SYSVIEW=y +CONFIG_SERIAL_RTT0=y +CONFIG_SPI=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_EXTERNAL_RAM=y +CONFIG_STM32_FMC=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_PWR=y +CONFIG_STM32_USART1=y +CONFIG_SYSLOG_CHAR=y +CONFIG_SYSLOG_RTT=y +CONFIG_SYSTEM_NSH=y +CONFIG_SYSTEM_SYSTEM=y +CONFIG_TASK_NAME_SIZE=16 +CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f4/stm32f429i-disco/configs/usbmsc/defconfig b/boards/arm/stm32f4/stm32f429i-disco/configs/usbmsc/defconfig new file mode 100644 index 0000000000000..7e6ab150d4a6e --- /dev/null +++ b/boards/arm/stm32f4/stm32f429i-disco/configs/usbmsc/defconfig @@ -0,0 +1,58 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_STM32_FLASH_PREFETCH is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f429i-disco" +CONFIG_ARCH_BOARD_STM32F429I_DISCO=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F429Z=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_FS_FAT=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_HEAP2_BASE=0xD0000000 +CONFIG_HEAP2_SIZE=8388608 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_MM_REGIONS=3 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=192 +CONFIG_SCHED_WAITPID=y +CONFIG_SPI=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_EXTERNAL_RAM=y +CONFIG_STM32_FMC=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_OTGHS=y +CONFIG_STM32_PWR=y +CONFIG_STM32_USART1=y +CONFIG_STM32_USBHOST=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART1_SERIAL_CONSOLE=y +CONFIG_USBHOST_MSC=y diff --git a/boards/arm/stm32f4/stm32f429i-disco/configs/usbnsh/defconfig b/boards/arm/stm32f4/stm32f429i-disco/configs/usbnsh/defconfig new file mode 100644 index 0000000000000..0a13ff515396f --- /dev/null +++ b/boards/arm/stm32f4/stm32f429i-disco/configs/usbnsh/defconfig @@ -0,0 +1,62 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_DEV_CONSOLE is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f429i-disco" +CONFIG_ARCH_BOARD_STM32F429I_DISCO=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F429Z=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL_USBDEVCTRL=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_CDCACM=y +CONFIG_CDCACM_CONSOLE=y +CONFIG_CDCACM_RXBUFSIZE=256 +CONFIG_CDCACM_TXBUFSIZE=256 +CONFIG_DEV_LOOP=y +CONFIG_FS_FAT=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_HEAP2_BASE=0xD0000000 +CONFIG_HEAP2_SIZE=8388608 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_PERROR_STDOUT=y +CONFIG_LIBC_STRERROR=y +CONFIG_LINE_MAX=64 +CONFIG_MM_REGIONS=3 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_SPI=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_EXTERNAL_RAM=y +CONFIG_STM32_FMC=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_OTGHS=y +CONFIG_STM32_PWR=y +CONFIG_STM32_USART1=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_TESTING_RAMTEST=y +CONFIG_USBDEV=y diff --git a/boards/arm/stm32f4/stm32f429i-disco/include/board.h b/boards/arm/stm32f4/stm32f429i-disco/include/board.h new file mode 100644 index 0000000000000..8d06febb0a6ad --- /dev/null +++ b/boards/arm/stm32f4/stm32f429i-disco/include/board.h @@ -0,0 +1,540 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f429i-disco/include/board.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_STM32_STM32F429I_DISCO_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32_STM32F429I_DISCO_INCLUDE_BOARD_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#ifndef __ASSEMBLY__ +# include +#endif + +/* DO NOT include STM32 internal header files here */ + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Clocking *****************************************************************/ + +/* The STM32F429I-DISCO board features a single 8MHz crystal. + * Space is provided for a 32kHz RTC backup crystal, but it is not stuffed. + * + * This is the canonical configuration: + * System Clock source : PLL (HSE) + * SYSCLK(Hz) : 180000000 Determined by PLL + * configuration + * HCLK(Hz) : 180000000 (STM32_RCC_CFGR_HPRE) + * AHB Prescaler : 1 (STM32_RCC_CFGR_HPRE) + * APB1 Prescaler : 4 (STM32_RCC_CFGR_PPRE1) + * APB2 Prescaler : 2 (STM32_RCC_CFGR_PPRE2) + * HSE Frequency(Hz) : 8000000 (STM32_BOARD_XTAL) + * PLLM : 8 (STM32_PLLCFG_PLLM) + * PLLN : 336 (STM32_PLLCFG_PLLN) + * PLLP : 2 (STM32_PLLCFG_PLLP) + * PLLQ : 7 (STM32_PLLCFG_PLLQ) + * Main regulator output voltage : Scale1 mode Needed for high speed + * SYSCLK + * Flash Latency(WS) : 5 + * Prefetch Buffer : OFF + * Instruction cache : ON + * Data cache : ON + * Require 48MHz for USB OTG FS, : Enabled + * SDIO and RNG clock + */ + +/* HSI - 16 MHz RC factory-trimmed + * LSI - 32 KHz RC + * HSE - On-board crystal frequency is 8MHz + * LSE - 32.768 kHz + */ + +#define STM32_BOARD_XTAL 8000000ul + +#define STM32_HSI_FREQUENCY 16000000ul +#define STM32_LSI_FREQUENCY 32000 +#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL +#define STM32_LSE_FREQUENCY 32768 + +/* Main PLL Configuration. + * + * PLL source is HSE + * PLL_VCO = (STM32_HSE_FREQUENCY / PLLM) * PLLN + * = (8,000,000 / 8) * 336 + * = 336,000,000 + * SYSCLK = PLL_VCO / PLLP + * = 336,000,000 / 2 = 168,000,000 + * USB OTG FS, SDIO and RNG Clock + * = PLL_VCO / PLLQ + * = 48,000,000 + */ + +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(8) +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(336) +#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_2 +#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(7) + +#define STM32_SYSCLK_FREQUENCY 168000000ul + +/* AHB clock (HCLK) is SYSCLK (168MHz) */ + +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY + +/* APB1 clock (PCLK1) is HCLK/4 (42MHz) */ + +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd4 /* PCLK1 = HCLK / 4 */ +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/4) + +/* Timers driven from APB1 will be twice PCLK1 */ + +#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) + +/* APB2 clock (PCLK2) is HCLK/2 (84MHz) */ + +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLKd2 /* PCLK2 = HCLK / 2 */ +#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/2) + +/* Timers driven from APB2 will be twice PCLK2 */ + +#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM9_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM10_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM11_CLKIN (2*STM32_PCLK2_FREQUENCY) + +/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx + * otherwise frequency is 2xAPBx. + * Note: TIM1,8 are on APB2, others on APB1 + */ + +#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM2_FREQUENCY (STM32_HCLK_FREQUENCY/2) +#define BOARD_TIM3_FREQUENCY (STM32_HCLK_FREQUENCY/2) +#define BOARD_TIM4_FREQUENCY (STM32_HCLK_FREQUENCY/2) +#define BOARD_TIM5_FREQUENCY (STM32_HCLK_FREQUENCY/2) +#define BOARD_TIM6_FREQUENCY (STM32_HCLK_FREQUENCY/2) +#define BOARD_TIM7_FREQUENCY (STM32_HCLK_FREQUENCY/2) +#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY + +/* LED definitions **********************************************************/ + +/* If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs in + * any way. The following definitions are used to access individual LEDs. + */ + +/* LED index values for use with board_userled() */ + +#define BOARD_LED1 0 +#define BOARD_LED2 1 +#define BOARD_NLEDS 2 + +#define BOARD_LED_GREEN BOARD_LED1 +#define BOARD_LED_ORANGE BOARD_LED2 + +/* LED bits for use with board_userled_all() */ + +#define BOARD_LED1_BIT (1 << BOARD_LED1) +#define BOARD_LED2_BIT (1 << BOARD_LED2) + +/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the 4 LEDs on + * board the stm32f429i-disco. + * The following definitions describe how NuttX controls the LEDs: + */ + +#define LED_STARTED 0 /* LED1 */ +#define LED_HEAPALLOCATE 1 /* LED2 */ +#define LED_IRQSENABLED 2 /* LED1 + LED2 */ +#define LED_STACKCREATED 3 /* LED3 */ +#define LED_INIRQ 4 /* LED1 + LED3 */ +#define LED_SIGNAL 5 /* LED2 + LED3 */ +#define LED_ASSERTION 6 /* LED1 + LED2 + LED3 */ +#define LED_PANIC 7 /* N/C + N/C + N/C + LED4 */ + +/* Button definitions *******************************************************/ + +/* The STM32F429I-DISCO supports one button: */ + +#define BUTTON_USER 0 + +#define NUM_BUTTONS 1 + +#define BUTTON_USER_BIT (1 << BUTTON_USER) + +/* Alternate function pin selections ****************************************/ + +/* USART1: + * + * The STM32F429I-DISCO has no on-board serial devices, but the console is + * brought out to PA9 (TX) and PA10 (RX) for connection to an external serial + * device. + */ + +#define GPIO_USART1_RX (GPIO_USART1_RX_1|GPIO_SPEED_100MHz) +#define GPIO_USART1_TX (GPIO_USART1_TX_1|GPIO_SPEED_100MHz) + +#define GPIO_USART3_RX (GPIO_USART3_RX_1|GPIO_SPEED_100MHz) +#define GPIO_USART3_TX (GPIO_USART3_TX_1|GPIO_SPEED_100MHz) + +/* CAN: */ + +#define GPIO_CAN1_RX (GPIO_CAN1_RX_2|GPIO_SPEED_50MHz) +#define GPIO_CAN1_TX (GPIO_CAN1_TX_2|GPIO_SPEED_50MHz) + +/* PWM + * + * The STM32F429I-DISCO has no real on-board PWM devices, but the board can + * be configured to output a pulse train using TIM4 CH2 on PD13. + */ + +#define GPIO_TIM4_CH2OUT (GPIO_TIM4_CH2OUT_2|GPIO_SPEED_50MHz) + +#define GPIO_TIM1_CH1OUT (GPIO_TIM1_CH1OUT_2|GPIO_SPEED_50MHz) /* PE9 */ +#define GPIO_TIM1_CH1NOUT GPIO_TIM1_CH1N_3 /* PE8 */ +#define GPIO_TIM1_CH2OUT (GPIO_TIM1_CH2OUT_2|GPIO_SPEED_50MHz) /* PE11 */ +#define GPIO_TIM1_CH2NOUT GPIO_TIM1_CH2N_3 /* PE10 */ +#define GPIO_TIM1_CH3OUT (GPIO_TIM1_CH3OUT_2|GPIO_SPEED_50MHz) /* PE13 */ +#define GPIO_TIM1_CH3NOUT GPIO_TIM1_CH3N_3 /* PE12 */ + +/* I2C - There is a STMPE811 TouchPanel on I2C3 using these pins: */ + +#define GPIO_I2C3_SCL (GPIO_I2C3_SCL_1|GPIO_SPEED_50MHz) +#define GPIO_I2C3_SDA (GPIO_I2C3_SDA_1|GPIO_SPEED_50MHz) + +/* SPI - There is a MEMS device on SPI5 using these pins: */ + +#define GPIO_SPI5_MISO (GPIO_SPI5_MISO_1|GPIO_SPEED_50MHz) +#define GPIO_SPI5_MOSI (GPIO_SPI5_MOSI_1|GPIO_SPEED_50MHz) +#define GPIO_SPI5_SCK (GPIO_SPI5_SCK_1|GPIO_SPEED_50MHz) + +/* SPI - External SPI flash may be connected on SPI4: */ + +#define GPIO_SPI4_MISO (GPIO_SPI4_MISO_1|GPIO_SPEED_50MHz) +#define GPIO_SPI4_MOSI (GPIO_SPI4_MOSI_1|GPIO_SPEED_50MHz) +#define GPIO_SPI4_SCK (GPIO_SPI4_SCK_1|GPIO_SPEED_50MHz) + +/* FMC - SDRAM */ + +#define GPIO_FMC_SDCKE1 (GPIO_FMC_SDCKE1_1|GPIO_SPEED_100MHz) +#define GPIO_FMC_SDNE1 (GPIO_FMC_SDNE1_1|GPIO_SPEED_100MHz) +#define GPIO_FMC_SDNWE (GPIO_FMC_SDNWE_1|GPIO_SPEED_100MHz) + +/* Timer Inputs/Outputs */ + +#define GPIO_TIM2_CH1IN (GPIO_TIM2_CH1IN_2|GPIO_SPEED_50MHz) +#define GPIO_TIM2_CH2IN (GPIO_TIM2_CH2IN_1|GPIO_SPEED_50MHz) + +#define GPIO_TIM8_CH1IN (GPIO_TIM8_CH1IN_1|GPIO_SPEED_50MHz) +#define GPIO_TIM8_CH2IN (GPIO_TIM8_CH2IN_1|GPIO_SPEED_50MHz) + +#ifdef CONFIG_STM32_LTDC +# ifdef CONFIG_STM32F429I_DISCO_ILI9341_FBIFACE + +/* LCD + * + * The STM32F429I-DISCO board contains an onboard TFT LCD connected to the + * LTDC interface of the uC. + * The LCD is 240x320 pixels. + * Define the parameters of the LCD and the interface here. + */ + +/* Panel configuration + * + * LCD Panel is Saef Technology Limited (SF-TC240T-9229A2-T) with integrated + * Ilitek ILI9341 LCD Single Chip Driver (240RGBx320) + * + * PLLSAI settings + * PLLSAIN : 192 + * PLLSAIR : 4 + * PLLSAIQ : 7 + * PLLSAIDIVR : 8 + * + * Timings + * Horizontal Front Porch : 10 (STM32_LTDC_HFP) + * Horizontal Back Porch : 20 (STM32_LTDC_HBP) + * Vertical Front Porch : 4 (STM32_LTDC_VFP) + * Vertical Back Porch : 2 (STM32_LTDC_VBP) + * + * Horizontal Sync : 10 (STM32_LTDC_HSYNC) + * Vertical Sync : 4 (STM32_LTDC_VSYNC) + * + * Active Width : 240 (STM32_LTDC_ACTIVEW) + * Active Height : 320 (STM32_LTDC_ACTIVEH) + */ + +/* LTDC PLL configuration + * + * PLLSAI_VCO = STM32_HSE_FREQUENCY / PLLM + * = 8000000ul / 8 + * = 1,000,000 + * + * PLL LCD clock output + * = PLLSAI_VCO * PLLSAIN / PLLSAIR / PLLSAIDIVR + * = 1,000,000 * 192 / 4 /8 + * = 6,000,000 + */ + +/* Defined panel settings */ + +#if defined(CONFIG_STM32F429I_DISCO_ILI9341_FBIFACE_LANDSCAPE) || \ + defined(CONFIG_STM32F429I_DISCO_ILI9341_FBIFACE_RLANDSCAPE) +# define BOARD_LTDC_WIDTH 320 +# define BOARD_LTDC_HEIGHT 240 +#else +# define BOARD_LTDC_WIDTH 240 +# define BOARD_LTDC_HEIGHT 320 +#endif + +#define BOARD_LTDC_OUTPUT_BPP 16 +#define BOARD_LTDC_HFP 10 +#define BOARD_LTDC_HBP 20 +#define BOARD_LTDC_VFP 4 +#define BOARD_LTDC_VBP 2 +#define BOARD_LTDC_HSYNC 10 +#define BOARD_LTDC_VSYNC 2 + +#define BOARD_LTDC_PLLSAIN 192 +#define BOARD_LTDC_PLLSAIR 4 +#define BOARD_LTDC_PLLSAIQ 7 + +/* Division factor for LCD clock */ + +#define STM32_RCC_DCKCFGR_PLLSAIDIVR RCC_DCKCFGR_PLLSAIDIVR_DIV8 + +/* Pixel Clock Polarity */ + +#define BOARD_LTDC_GCR_PCPOL 0 /* !LTDC_GCR_PCPOL */ + +/* Data Enable Polarity */ + +#define BOARD_LTDC_GCR_DEPOL 0 /* !LTDC_GCR_DEPOL */ + +/* Vertical Sync Polarity */ + +#define BOARD_LTDC_GCR_VSPOL 0 /* !LTDC_GCR_VSPOL */ + +/* Horizontal Sync Polarity */ + +#define BOARD_LTDC_GCR_HSPOL 0 /* !LTDC_GCR_HSPOL */ + +/* GPIO pinset */ + +#define GPIO_LTDC_PINS 18 /* 18-bit display */ + +#define GPIO_LTDC_R2 (GPIO_LTDC_R2_1|GPIO_SPEED_100MHz) +#define GPIO_LTDC_R3 (GPIO_LTDC_R3_1|GPIO_SPEED_100MHz) +#define GPIO_LTDC_R4 (GPIO_LTDC_R4_1|GPIO_SPEED_100MHz) +#define GPIO_LTDC_R5 (GPIO_LTDC_R5_1|GPIO_SPEED_100MHz) +#define GPIO_LTDC_R6 (GPIO_LTDC_R6_1|GPIO_SPEED_100MHz) +#define GPIO_LTDC_R7 (GPIO_LTDC_R7_1|GPIO_SPEED_100MHz) + +#define GPIO_LTDC_G2 (GPIO_LTDC_G2_1|GPIO_SPEED_100MHz) +#define GPIO_LTDC_G3 (GPIO_LTDC_G3_1|GPIO_SPEED_100MHz) +#define GPIO_LTDC_G4 (GPIO_LTDC_G4_1|GPIO_SPEED_100MHz) +#define GPIO_LTDC_G5 (GPIO_LTDC_G5_1|GPIO_SPEED_100MHz) +#define GPIO_LTDC_G6 (GPIO_LTDC_G6_1|GPIO_SPEED_100MHz) +#define GPIO_LTDC_G7 (GPIO_LTDC_G7_1|GPIO_SPEED_100MHz) + +#define GPIO_LTDC_B2 (GPIO_LTDC_B2_1|GPIO_SPEED_100MHz) +#define GPIO_LTDC_B3 (GPIO_LTDC_B3_1|GPIO_SPEED_100MHz) +#define GPIO_LTDC_B4 (GPIO_LTDC_B4_1|GPIO_SPEED_100MHz) +#define GPIO_LTDC_B5 (GPIO_LTDC_B5_1|GPIO_SPEED_100MHz) +#define GPIO_LTDC_B6 (GPIO_LTDC_B6_1|GPIO_SPEED_100MHz) +#define GPIO_LTDC_B7 (GPIO_LTDC_B7_1|GPIO_SPEED_100MHz) + +#define GPIO_LTDC_VSYNC GPIO_LTDC_VSYNC_1 +#define GPIO_LTDC_HSYNC GPIO_LTDC_HSYNC_1 +#define GPIO_LTDC_DE (GPIO_LTDC_DE_1|GPIO_SPEED_100MHz) +#define GPIO_LTDC_CLK GPIO_LTDC_CLK_1 + +#else +/* Custom LCD display configuration */ + +# define BOARD_LTDC_WIDTH ??? +# define BOARD_LTDC_HEIGHT ??? + +#define BOARD_LTDC_HFP ??? +#define BOARD_LTDC_HBP ??? +#define BOARD_LTDC_VFP ??? +#define BOARD_LTDC_VBP ??? +#define BOARD_LTDC_HSYNC ??? +#define BOARD_LTDC_VSYNC ??? + +#define BOARD_LTDC_PLLSAIN ??? +#define BOARD_LTDC_PLLSAIR ??? +#define BOARD_LTDC_PLLSAIQ ??? + +/* Division factor for LCD clock */ + +#define STM32_RCC_DCKCFGR_PLLSAIDIVR ??? + +/* Pixel Clock Polarity */ + +#define BOARD_LTDC_GCR_PCPOL ??? + +/* Data Enable Polarity */ + +#define BOARD_LTDC_GCR_DEPOL ??? + +/* Vertical Sync Polarity */ + +#define BOARD_LTDC_GCR_VSPOL ??? + +/* Horizontal Sync Polarity */ + +#define BOARD_LTDC_GCR_HSPOL ??? + +/* GPIO pinset */ + +#define GPIO_LTDC_PINS ??? + +#define GPIO_LTDC_R2 ??? +#define GPIO_LTDC_R3 ??? +#define GPIO_LTDC_R4 ??? +#define GPIO_LTDC_R5 ??? +#define GPIO_LTDC_R6 ??? +#define GPIO_LTDC_R7 ??? + +#define GPIO_LTDC_G2 ??? +#define GPIO_LTDC_G3 ??? +#define GPIO_LTDC_G4 ??? +#define GPIO_LTDC_G5 ??? +#define GPIO_LTDC_G6 ??? +#define GPIO_LTDC_G7 ??? + +#define GPIO_LTDC_B2 ??? +#define GPIO_LTDC_B3 ??? +#define GPIO_LTDC_B4 ??? +#define GPIO_LTDC_B5 ??? +#define GPIO_LTDC_B6 ??? +#define GPIO_LTDC_B7 ??? + +#define GPIO_LTDC_VSYNC ??? +#define GPIO_LTDC_HSYNC ??? +#define GPIO_LTDC_DE ??? +#define GPIO_LTDC_CLK ??? + +#endif /* Custom LCD display */ + +/* Configure PLLSAI */ + +#define STM32_RCC_PLLSAICFGR_PLLSAIN RCC_PLLSAICFGR_PLLSAIN(BOARD_LTDC_PLLSAIN) +#define STM32_RCC_PLLSAICFGR_PLLSAIR RCC_PLLSAICFGR_PLLSAIR(BOARD_LTDC_PLLSAIR) +#define STM32_RCC_PLLSAICFGR_PLLSAIQ RCC_PLLSAICFGR_PLLSAIQ(BOARD_LTDC_PLLSAIQ) + +#endif /* CONFIG_STM32_LTDC */ + +/* L3GD20 MEMS */ + +#define GPIO_L3GD20_DREADY (GPIO_INPUT|GPIO_FLOAT|GPIO_EXTI|GPIO_PORTA|GPIO_PIN2) +#define L3GD20_IRQ (2 + STM32_IRQ_EXTI0) + +#define BOARD_L3GD20_GPIO_DREADY GPIO_L3GD20_DREADY +#define BOARD_L3GD20_IRQ L3GD20_IRQ + +#define GPIO_LIS3DSH_EXT0 \ + (GPIO_INPUT|GPIO_FLOAT|GPIO_AF0|GPIO_SPEED_50MHz|GPIO_PORTE|GPIO_PIN0) + +#define BOARD_LIS3DSH_GPIO_EXT0 GPIO_LIS3DSH_EXT0 + +/* DMA **********************************************************************/ + +#define ADC1_DMA_CHAN DMAMAP_ADC1_1 + +/* USB OTG FS / OTG HS */ + +#define GPIO_OTGFS_DM (GPIO_OTGFS_DM_0|GPIO_SPEED_100MHz) +#define GPIO_OTGFS_DP (GPIO_OTGFS_DP_0|GPIO_SPEED_100MHz) +#define GPIO_OTGFS_ID (GPIO_OTGFS_ID_0|GPIO_SPEED_100MHz) +#define GPIO_OTGFS_SOF (GPIO_OTGFS_SOF_0|GPIO_SPEED_100MHz) +#define GPIO_OTGHS_DM (GPIO_OTGHS_DM_0|GPIO_SPEED_100MHz) +#define GPIO_OTGHS_DP (GPIO_OTGHS_DP_0|GPIO_SPEED_100MHz) +#define GPIO_OTGHS_ID GPIO_OTGHS_ID_0 +#define GPIO_OTGHS_SOF GPIO_OTGHS_SOF_0 + +/* SDIO */ + +#define GPIO_SDIO_CK (GPIO_SDIO_CK_0|GPIO_SPEED_50MHz) +#define GPIO_SDIO_CMD (GPIO_SDIO_CMD_0|GPIO_SPEED_50MHz) +#define GPIO_SDIO_D0 (GPIO_SDIO_D0_0|GPIO_SPEED_50MHz) +#define GPIO_SDIO_D1 (GPIO_SDIO_D1_0|GPIO_SPEED_50MHz) +#define GPIO_SDIO_D2 (GPIO_SDIO_D2_0|GPIO_SPEED_50MHz) +#define GPIO_SDIO_D3 (GPIO_SDIO_D3_0|GPIO_SPEED_50MHz) + +/* FMC SDRAM pins (referenced by board src) */ + +#define GPIO_FMC_D0 (GPIO_FMC_D0_0|GPIO_SPEED_100MHz) +#define GPIO_FMC_D1 (GPIO_FMC_D1_0|GPIO_SPEED_100MHz) +#define GPIO_FMC_D2 (GPIO_FMC_D2_0|GPIO_SPEED_100MHz) +#define GPIO_FMC_D3 (GPIO_FMC_D3_0|GPIO_SPEED_100MHz) +#define GPIO_FMC_D4 (GPIO_FMC_D4_0|GPIO_SPEED_100MHz) +#define GPIO_FMC_D5 (GPIO_FMC_D5_0|GPIO_SPEED_100MHz) +#define GPIO_FMC_D6 (GPIO_FMC_D6_0|GPIO_SPEED_100MHz) +#define GPIO_FMC_D7 (GPIO_FMC_D7_0|GPIO_SPEED_100MHz) +#define GPIO_FMC_D8 (GPIO_FMC_D8_0|GPIO_SPEED_100MHz) +#define GPIO_FMC_D9 (GPIO_FMC_D9_0|GPIO_SPEED_100MHz) +#define GPIO_FMC_D10 (GPIO_FMC_D10_0|GPIO_SPEED_100MHz) +#define GPIO_FMC_D11 (GPIO_FMC_D11_0|GPIO_SPEED_100MHz) +#define GPIO_FMC_D12 (GPIO_FMC_D12_0|GPIO_SPEED_100MHz) +#define GPIO_FMC_D13 (GPIO_FMC_D13_0|GPIO_SPEED_100MHz) +#define GPIO_FMC_D14 (GPIO_FMC_D14_0|GPIO_SPEED_100MHz) +#define GPIO_FMC_D15 (GPIO_FMC_D15_0|GPIO_SPEED_100MHz) +#define GPIO_FMC_A0 (GPIO_FMC_A0_0|GPIO_SPEED_100MHz) +#define GPIO_FMC_A1 (GPIO_FMC_A1_0|GPIO_SPEED_100MHz) +#define GPIO_FMC_A2 (GPIO_FMC_A2_0|GPIO_SPEED_100MHz) +#define GPIO_FMC_A3 (GPIO_FMC_A3_0|GPIO_SPEED_100MHz) +#define GPIO_FMC_A4 (GPIO_FMC_A4_0|GPIO_SPEED_100MHz) +#define GPIO_FMC_A5 (GPIO_FMC_A5_0|GPIO_SPEED_100MHz) +#define GPIO_FMC_A6 (GPIO_FMC_A6_0|GPIO_SPEED_100MHz) +#define GPIO_FMC_A7 (GPIO_FMC_A7_0|GPIO_SPEED_100MHz) +#define GPIO_FMC_A8 (GPIO_FMC_A8_0|GPIO_SPEED_100MHz) +#define GPIO_FMC_A9 (GPIO_FMC_A9_0|GPIO_SPEED_100MHz) +#define GPIO_FMC_A10 (GPIO_FMC_A10_0|GPIO_SPEED_100MHz) +#define GPIO_FMC_A11 (GPIO_FMC_A11_0|GPIO_SPEED_100MHz) +#define GPIO_FMC_NBL0 (GPIO_FMC_NBL0_0|GPIO_SPEED_100MHz) +#define GPIO_FMC_NBL1 (GPIO_FMC_NBL1_0|GPIO_SPEED_100MHz) +#define GPIO_FMC_SDCLK (GPIO_FMC_SDCLK_0|GPIO_SPEED_100MHz) +#define GPIO_FMC_SDNCAS (GPIO_FMC_SDNCAS_0|GPIO_SPEED_100MHz) +#define GPIO_FMC_SDNRAS (GPIO_FMC_SDNRAS_0|GPIO_SPEED_100MHz) +#define GPIO_FMC_BA0 (GPIO_FMC_BA0_0|GPIO_SPEED_100MHz) +#define GPIO_FMC_BA1 (GPIO_FMC_BA1_0|GPIO_SPEED_100MHz) + +/* USB OTGHSFS (HS in FS mode) */ + +#define GPIO_OTGHSFS_DM (GPIO_OTGHSFS_DM_0|GPIO_SPEED_100MHz) +#define GPIO_OTGHSFS_DP (GPIO_OTGHSFS_DP_0|GPIO_SPEED_100MHz) +#define GPIO_OTGHSFS_ID (GPIO_OTGHSFS_ID_0|GPIO_SPEED_100MHz) + +#endif /* __BOARDS_ARM_STM32_STM32F429I_DISCO_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32f4/stm32f429i-disco/scripts/Make.defs b/boards/arm/stm32f4/stm32f429i-disco/scripts/Make.defs new file mode 100644 index 0000000000000..5ecd6c7d19450 --- /dev/null +++ b/boards/arm/stm32f4/stm32f429i-disco/scripts/Make.defs @@ -0,0 +1,46 @@ +############################################################################ +# boards/arm/stm32f4/stm32f429i-disco/scripts/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/.config +include $(TOPDIR)/tools/Config.mk +include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs + +ifeq ($(CONFIG_SYSTEM_OFLOADER),y) +LDSCRIPT = ofloader.ld +else +LDSCRIPT = ld.script +endif + +ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) + +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32f4/stm32f429i-disco/scripts/kernel-space.ld b/boards/arm/stm32f4/stm32f429i-disco/scripts/kernel-space.ld new file mode 100644 index 0000000000000..b03d51ac65f8d --- /dev/null +++ b/boards/arm/stm32f4/stm32f429i-disco/scripts/kernel-space.ld @@ -0,0 +1,100 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f429i-disco/scripts/kernel-space.ld + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* NOTE: This depends on the memory.ld script having been included prior to + * this script. + */ + +OUTPUT_ARCH(arm) +EXTERN(_vectors) +ENTRY(_stext) +SECTIONS +{ + .text : { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > kflash + + .init_section : { + _sinit = ABSOLUTE(.); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) + _einit = ABSOLUTE(.); + } > kflash + + .ARM.extab : { + *(.ARM.extab*) + } > kflash + + __exidx_start = ABSOLUTE(.); + .ARM.exidx : { + *(.ARM.exidx*) + } > kflash + + __exidx_end = ABSOLUTE(.); + + _eronly = ABSOLUTE(.); + + .data : { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > ksram AT > kflash + + .bss : { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(8); + _ebss = ABSOLUTE(.); + } > ksram + + /* Stabs debugging sections */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/stm32f4/stm32f429i-disco/scripts/ld.script b/boards/arm/stm32f4/stm32f429i-disco/scripts/ld.script new file mode 100644 index 0000000000000..349f486d473a5 --- /dev/null +++ b/boards/arm/stm32f4/stm32f429i-disco/scripts/ld.script @@ -0,0 +1,133 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f429i-disco/scripts/ld.script + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* The STM32F429ZIT6 has 2048Kb of FLASH beginning at address 0x0800:0000 and + * 256Kb of SRAM. SRAM is split up into four blocks: + * + * 1) 112Kb of SRAM beginning at address 0x2000:0000 + * 2) 16Kb of SRAM beginning at address 0x2001:c000 + * 3) 64Kb of SRAM beginning at address 0x2002:0000 + * 4) 64Kb of CCM SRAM beginning at address 0x1000:0000 + * + * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 + * where the code expects to begin execution by jumping to the entry point in + * the 0x0800:0000 address + * range. + */ + +MEMORY +{ + flash (rx) : ORIGIN = 0x08000000, LENGTH = 2048K + sram (rwx) : ORIGIN = 0x20000000, LENGTH = 112K +} + +OUTPUT_ARCH(arm) +EXTERN(_vectors) +ENTRY(_stext) +SECTIONS +{ + .text : { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > flash + + .init_section : ALIGN(4) { + _sinit = ABSOLUTE(.); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) + _einit = ABSOLUTE(.); + } > flash + + .ARM.extab : ALIGN(4) { + *(.ARM.extab*) + } > flash + + .ARM.exidx : ALIGN(4) { + __exidx_start = ABSOLUTE(.); + *(.ARM.exidx*) + __exidx_end = ABSOLUTE(.); + } > flash + + .tdata : { + _stdata = ABSOLUTE(.); + *(.tdata .tdata.* .gnu.linkonce.td.*); + _etdata = ABSOLUTE(.); + } > flash + + .tbss : { + _stbss = ABSOLUTE(.); + *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); + _etbss = ABSOLUTE(.); + } > flash + + _eronly = ABSOLUTE(.); + + /* The RAM vector table (if present) should lie at the beginning of SRAM */ + + .ram_vectors : { + *(.ram_vectors) + } > sram + + .data : ALIGN(4) { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > sram AT > flash + + .bss : ALIGN(4) { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + _ebss = ABSOLUTE(.); + } > sram + + /* Stabs debugging sections. */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/stm32f4/stm32f429i-disco/scripts/memory.ld b/boards/arm/stm32f4/stm32f429i-disco/scripts/memory.ld new file mode 100644 index 0000000000000..75cf8f18e6ebd --- /dev/null +++ b/boards/arm/stm32f4/stm32f429i-disco/scripts/memory.ld @@ -0,0 +1,88 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f429i-disco/scripts/memory.ld + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* The STM32F429ZIT has 2048Kb of FLASH beginning at address 0x0800:0000 and + * 256Kb of SRAM. SRAM is split up into four blocks: + * + * 1) 112KB of SRAM beginning at address 0x2000:0000 + * 2) 16KB of SRAM beginning at address 0x2001:c000 + * 3) 64KB of SRAM beginning at address 0x2002:0000 + * 4) 64KB of CCM SRAM beginning at address 0x1000:0000 + * + * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 + * where the code expects to begin execution by jumping to the entry point in + * the 0x0800:0000 address range. + * + * For MPU support, the kernel-mode NuttX section is assumed to be 128Kb of + * FLASH and 4Kb of SRAM. That is an excessive amount for the kernel which + * should fit into 64KB and, of course, can be optimized as needed (See + * also boards/arm/stm32f4/stm32f429i-disco/scripts/kernel-space.ld). Allowing the + * additional does permit addition debug instrumentation to be added to the + * kernel space without overflowing the partition. + * + * Alignment of the user space FLASH partition is also a critical factor: + * The user space FLASH partition will be spanned with a single region of + * size 2**n bytes. The alignment of the user-space region must be the same. + * As a consequence, as the user-space increases in size, the alignment + * requirement also increases. + * + * This alignment requirement means that the largest user space FLASH region + * you can have will be 512KB at it would have to be positioned at + * 0x08800000. If you change this address, don't forget to change the + * CONFIG_NUTTX_USERSPACE configuration setting to match and to modify + * the check in kernel/userspace.c. + * + * For the same reasons, the maximum size of the SRAM mapping is limited to + * 4KB. Both of these alignment limitations could be reduced by using + * multiple regions to map the FLASH/SDRAM range or perhaps with some + * clever use of subregions. + * + * A detailed memory map for the 112KB SRAM region is as follows: + * + * 0x20000 0000: Kernel .data region. Typical size: 0.1KB + * ------- ---- Kernel .bss region. Typical size: 1.8KB + * 0x20000 0800: Kernel IDLE thread stack (approximate). Size is + * determined by CONFIG_IDLETHREAD_STACKSIZE and + * adjustments for alignment. Typical is 1KB. + * ------- ---- Padded to 4KB + * 0x20000 1000: User .data region. Size is variable. + * ------- ---- User .bss region Size is variable. + * 0x20000 2000: Beginning of kernel heap. Size determined by + * CONFIG_MM_KERNEL_HEAPSIZE. + * ------- ---- Beginning of user heap. Can vary with other settings. + * 0x20001 c000: End+1 of CPU RAM + */ + +MEMORY +{ + /* 1024Kb FLASH */ + + kflash (rx) : ORIGIN = 0x08000000, LENGTH = 128K + uflash (rx) : ORIGIN = 0x08020000, LENGTH = 128K + xflash (rx) : ORIGIN = 0x08040000, LENGTH = 768K + + /* 112Kb of contiguous SRAM */ + + ksram (rwx) : ORIGIN = 0x20000000, LENGTH = 4K + usram (rwx) : ORIGIN = 0x20001000, LENGTH = 4K + xsram (rwx) : ORIGIN = 0x20002000, LENGTH = 104K +} diff --git a/boards/arm/stm32/stm32f429i-disco/scripts/ofloader.ld b/boards/arm/stm32f4/stm32f429i-disco/scripts/ofloader.ld similarity index 98% rename from boards/arm/stm32/stm32f429i-disco/scripts/ofloader.ld rename to boards/arm/stm32f4/stm32f429i-disco/scripts/ofloader.ld index ab7554dc716ec..10857b3f77c73 100644 --- a/boards/arm/stm32/stm32f429i-disco/scripts/ofloader.ld +++ b/boards/arm/stm32f4/stm32f429i-disco/scripts/ofloader.ld @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f429i-disco/scripts/ofloader.ld + * boards/arm/stm32f4/stm32f429i-disco/scripts/ofloader.ld * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f4/stm32f429i-disco/scripts/user-space.ld b/boards/arm/stm32f4/stm32f429i-disco/scripts/user-space.ld new file mode 100644 index 0000000000000..9830e4080570a --- /dev/null +++ b/boards/arm/stm32f4/stm32f429i-disco/scripts/user-space.ld @@ -0,0 +1,114 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f429i-disco/scripts/user-space.ld + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* NOTE: This depends on the memory.ld script having been included prior to + * this script. + */ + +/* Make sure that the critical memory management functions are in user-space. + * the user heap memory manager will reside in user-space but be usable both + * by kernel- and user-space code + */ + +EXTERN(umm_initialize) +EXTERN(umm_addregion) + +EXTERN(malloc) +EXTERN(realloc) +EXTERN(zalloc) +EXTERN(free) + +OUTPUT_ARCH(arm) +SECTIONS +{ + .userspace : { + *(.userspace) + } > uflash + + .text : { + _stext = ABSOLUTE(.); + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > uflash + + .init_section : { + _sinit = ABSOLUTE(.); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) + _einit = ABSOLUTE(.); + } > uflash + + .ARM.extab : { + *(.ARM.extab*) + } > uflash + + __exidx_start = ABSOLUTE(.); + .ARM.exidx : { + *(.ARM.exidx*) + } > uflash + + __exidx_end = ABSOLUTE(.); + + _eronly = ABSOLUTE(.); + + .data : { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > usram AT > uflash + + .bss : { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(8); + _ebss = ABSOLUTE(.); + } > usram + + /* Stabs debugging sections */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/stm32f4/stm32f429i-disco/src/CMakeLists.txt b/boards/arm/stm32f4/stm32f429i-disco/src/CMakeLists.txt new file mode 100644 index 0000000000000..c4b340d84d8d9 --- /dev/null +++ b/boards/arm/stm32f4/stm32f429i-disco/src/CMakeLists.txt @@ -0,0 +1,79 @@ +# ############################################################################## +# boards/arm/stm32f4/stm32f429i-disco/src/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(SRCS stm32_boot.c stm32_bringup.c stm32_spi.c) + +if(CONFIG_ARCH_LEDS) + list(APPEND SRCS stm32_autoleds.c) +else() + list(APPEND SRCS stm32_userleds.c) +endif() + +if(CONFIG_ARCH_BUTTONS) + list(APPEND SRCS stm32_buttons.c) +endif() + +if(CONFIG_ARCH_IDLE_CUSTOM) + list(APPEND SRCS stm32_idle.c) +endif() + +if(CONFIG_STM32_FMC) + list(APPEND SRCS stm32_extmem.c) +endif() + +if(CONFIG_STM32_OTGHS) + list(APPEND SRCS stm32_usb.c) +endif() + +if(CONFIG_INPUT_STMPE811) + list(APPEND SRCS stm32_stmpe811.c) +endif() + +if(CONFIG_STM32F429I_DISCO_ILI9341) + list(APPEND SRCS stm32_ili93414ws.c) +endif() + +if(CONFIG_STM32F429I_DISCO_ILI9341_LCDIFACE + AND CONFIG_STM32F429I_DISCO_ILI9341_FBIFACE + AND CONFIG_STM32_LTDC) + list(APPEND SRCS stm32_lcd.c) +endif() + +if(CONFIG_PWM) + list(APPEND SRCS stm32_pwm.c) +endif() + +if(CONFIG_ADC) + list(APPEND SRCS stm32_adc.c) +endif() + +if(CONFIG_STM32_CAN_CHARDRIVER) + list(APPEND SRCS stm32_can.c) +endif() + +if(CONFIG_STM32F429I_DISCO_HIGHPRI) + list(APPEND SRCS stm32_highpri.c) +endif() + +target_sources(board PRIVATE ${SRCS}) + +set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/ld.script") diff --git a/boards/arm/stm32f4/stm32f429i-disco/src/Make.defs b/boards/arm/stm32f4/stm32f429i-disco/src/Make.defs new file mode 100644 index 0000000000000..a5df5de7384ad --- /dev/null +++ b/boards/arm/stm32f4/stm32f429i-disco/src/Make.defs @@ -0,0 +1,82 @@ +############################################################################ +# boards/arm/stm32f4/stm32f429i-disco/src/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +CSRCS = stm32_boot.c stm32_bringup.c stm32_spi.c + +ifeq ($(CONFIG_ARCH_LEDS),y) +CSRCS += stm32_autoleds.c +else +CSRCS += stm32_userleds.c +endif + +ifeq ($(CONFIG_ARCH_BUTTONS),y) +CSRCS += stm32_buttons.c +endif + +ifeq ($(CONFIG_ARCH_IDLE_CUSTOM),y) +CSRCS += stm32_idle.c +endif + +ifeq ($(CONFIG_STM32_FMC),y) +CSRCS += stm32_extmem.c +endif + +ifeq ($(CONFIG_STM32_OTGHS),y) +CSRCS += stm32_usb.c +endif + +ifeq ($(CONFIG_INPUT_STMPE811),y) +CSRCS += stm32_stmpe811.c +endif + +ifeq ($(CONFIG_STM32F429I_DISCO_ILI9341),y) +CSRCS += stm32_ili93414ws.c +endif + +ifeq ($(and \ + $(CONFIG_STM32F429I_DISCO_ILI9341_LCDIFACE), \ + $(CONFIG_STM32F429I_DISCO_ILI9341_FBIFACE), \ + $(CONFIG_STM32_LTDC)),) +CSRCS += stm32_lcd.c +endif + +ifeq ($(CONFIG_PWM),y) +CSRCS += stm32_pwm.c +endif + +ifeq ($(CONFIG_ADC),y) +CSRCS += stm32_adc.c +endif + +ifeq ($(CONFIG_STM32_CAN_CHARDRIVER),y) +CSRCS += stm32_can.c +endif + +ifeq ($(CONFIG_STM32F429I_DISCO_HIGHPRI),y) +CSRCS += stm32_highpri.c +endif + +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32f4/stm32f429i-disco/src/stm32_adc.c b/boards/arm/stm32f4/stm32f429i-disco/src/stm32_adc.c new file mode 100644 index 0000000000000..d7a1d4b33bed5 --- /dev/null +++ b/boards/arm/stm32f4/stm32f429i-disco/src/stm32_adc.c @@ -0,0 +1,237 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f429i-disco/src/stm32_adc.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "stm32.h" + +#if defined(CONFIG_ADC) && (defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC3)) + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* 1 or 2 ADC devices (DEV1, DEV2). + * ADC1 and ADC3 supported for now. + */ + +#if defined(CONFIG_STM32_ADC1) +# define DEV1_PORT 1 +#endif + +#if defined(CONFIG_STM32_ADC3) +# if defined(DEV1_PORT) +# define DEV2_PORT 3 +# else +# define DEV1_PORT 3 +# endif +#endif + +/* The number of ADC channels in the conversion list */ + +/* TODO DMA */ + +#define ADC1_NCHANNELS 2 +#define ADC3_NCHANNELS 1 + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* DEV 1 */ + +#if DEV1_PORT == 1 + +#define DEV1_NCHANNELS ADC1_NCHANNELS + +/* Identifying number of each ADC channel (even if NCHANNELS is less ) */ + +static const uint8_t g_chanlist1[2] = +{ + 5, + 13, +}; + +/* Configurations of pins used by each ADC channel */ + +static const uint32_t g_pinlist1[2] = +{ + GPIO_ADC1_IN5_0, /* PA5 */ + GPIO_ADC1_IN13_0, /* PC3 */ +}; + +#elif DEV1_PORT == 3 + +#define DEV1_NCHANNELS ADC3_NCHANNELS + +/* Identifying number of each ADC channel */ + +static const uint8_t g_chanlist1[1] = +{ + 4, +}; + +/* Configurations of pins used by each ADC channel */ + +static const uint32_t g_pinlist1[1] = +{ + GPIO_ADC3_IN4_0, /* PF6 */ +}; + +#endif /* DEV1_PORT == 1 */ + +#ifdef DEV2_PORT + +/* DEV 2 */ + +#if DEV2_PORT == 3 + +#define DEV2_NCHANNELS ADC3_NCHANNELS + +/* Identifying number of each ADC channel */ + +static const uint8_t g_chanlist2[3] = +{ + 8, + 9, + 10 +}; + +/* Configurations of pins used by each ADC channel */ + +static const uint32_t g_pinlist2[3] = +{ + GPIO_ADC3_IN8_0, /* PD11/A3 */ + GPIO_ADC3_IN9_0, /* PD12/A4 */ + GPIO_ADC3_IN10_0, /* PD13/A5 */ +}; + +#endif /* DEV2_PORT == 3 */ +#endif /* DEV2_PORT */ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_adc_setup + * + * Description: + * Initialize ADC and register the ADC driver. + * + ****************************************************************************/ + +int stm32_adc_setup(void) +{ + static bool initialized = false; + struct adc_dev_s *adc; + int ret; + int i; + + /* Check if we have already initialized */ + + if (!initialized) + { + /* DEV1 */ + + /* Configure the pins as analog inputs for the selected channels */ + + for (i = 0; i < DEV1_NCHANNELS; i++) + { + stm32_configgpio(g_pinlist1[i]); + } + + /* Call stm32_adcinitialize() to get an instance of the ADC interface */ + + adc = stm32_adcinitialize(DEV1_PORT, g_chanlist1, DEV1_NCHANNELS); + if (adc == NULL) + { + aerr("ERROR: Failed to get ADC interface 1\n"); + return -ENODEV; + } + + /* Register the ADC driver at "/dev/adc0" */ + + ret = adc_register("/dev/adc0", adc); + if (ret < 0) + { + aerr("ERROR: adc_register /dev/adc0 failed: %d\n", ret); + return ret; + } + +#ifdef DEV2_PORT + /* DEV2 */ + + /* Configure the pins as analog inputs for the selected channels */ + + for (i = 0; i < DEV2_NCHANNELS; i++) + { + stm32_configgpio(g_pinlist2[i]); + } + + /* Call stm32_adcinitialize() to get an instance of the ADC interface */ + + adc = stm32_adcinitialize(DEV2_PORT, g_chanlist2, DEV2_NCHANNELS); + if (adc == NULL) + { + aerr("ERROR: Failed to get ADC interface 2\n"); + return -ENODEV; + } + + /* Register the ADC driver at "/dev/adc1" */ + + ret = adc_register("/dev/adc1", adc); + if (ret < 0) + { + aerr("ERROR: adc_register /dev/adc1 failed: %d\n", ret); + return ret; + } +#endif + + initialized = true; + } + + return OK; +} + +#endif /* CONFIG_ADC && (CONFIG_STM32_ADC1 || CONFIG_STM32_ADC3) */ diff --git a/boards/arm/stm32f4/stm32f429i-disco/src/stm32_autoleds.c b/boards/arm/stm32f4/stm32f429i-disco/src/stm32_autoleds.c new file mode 100644 index 0000000000000..be4ca27083ea1 --- /dev/null +++ b/boards/arm/stm32f4/stm32f429i-disco/src/stm32_autoleds.c @@ -0,0 +1,208 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f429i-disco/src/stm32_autoleds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32.h" +#include "stm32f429i-disco.h" + +#ifdef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* The following definitions map the encoded LED setting to GPIO settings */ + +#define STM32F4_LED1 (1 << 0) +#define STM32F4_LED2 (1 << 1) + +#define ON_SETBITS_SHIFT (0) +#define ON_CLRBITS_SHIFT (4) +#define OFF_SETBITS_SHIFT (8) +#define OFF_CLRBITS_SHIFT (12) + +#define ON_BITS(v) ((v) & 0xff) +#define OFF_BITS(v) (((v) >> 8) & 0x0ff) +#define SETBITS(b) ((b) & 0x0f) +#define CLRBITS(b) (((b) >> 4) & 0x0f) + +#define ON_SETBITS(v) (SETBITS(ON_BITS(v)) +#define ON_CLRBITS(v) (CLRBITS(ON_BITS(v)) +#define OFF_SETBITS(v) (SETBITS(OFF_BITS(v)) +#define OFF_CLRBITS(v) (CLRBITS(OFF_BITS(v)) + +#define LED_STARTED_ON_SETBITS ((STM32F4_LED1) << ON_SETBITS_SHIFT) +#define LED_STARTED_ON_CLRBITS ((STM32F4_LED2) << ON_CLRBITS_SHIFT) +#define LED_STARTED_OFF_SETBITS (0 << OFF_SETBITS_SHIFT) +#define LED_STARTED_OFF_CLRBITS ((STM32F4_LED1|STM32F4_LED2) << OFF_CLRBITS_SHIFT) + +#define LED_HEAPALLOCATE_ON_SETBITS ((STM32F4_LED2) << ON_SETBITS_SHIFT) +#define LED_HEAPALLOCATE_ON_CLRBITS ((STM32F4_LED1) << ON_CLRBITS_SHIFT) +#define LED_HEAPALLOCATE_OFF_SETBITS ((STM32F4_LED1) << OFF_SETBITS_SHIFT) +#define LED_HEAPALLOCATE_OFF_CLRBITS ((STM32F4_LED2) << OFF_CLRBITS_SHIFT) + +#define LED_IRQSENABLED_ON_SETBITS ((STM32F4_LED1|STM32F4_LED2) << ON_SETBITS_SHIFT) +#define LED_IRQSENABLED_ON_CLRBITS ((STM32F4_LED2) << ON_CLRBITS_SHIFT) +#define LED_IRQSENABLED_OFF_SETBITS ((STM32F4_LED2) << OFF_SETBITS_SHIFT) +#define LED_IRQSENABLED_OFF_CLRBITS ((STM32F4_LED1) << OFF_CLRBITS_SHIFT) + +#define LED_STACKCREATED_ON_SETBITS ((STM32F4_LED1) << ON_SETBITS_SHIFT) +#define LED_STACKCREATED_ON_CLRBITS ((STM32F4_LED1|STM32F4_LED2) << ON_CLRBITS_SHIFT) +#define LED_STACKCREATED_OFF_SETBITS ((STM32F4_LED1|STM32F4_LED2) << OFF_SETBITS_SHIFT) +#define LED_STACKCREATED_OFF_CLRBITS ((STM32F4_LED1|STM32F4_LED2) << OFF_CLRBITS_SHIFT) + +#define LED_INIRQ_ON_SETBITS ((STM32F4_LED2) << ON_SETBITS_SHIFT) +#define LED_INIRQ_ON_CLRBITS ((0) << ON_CLRBITS_SHIFT) +#define LED_INIRQ_OFF_SETBITS ((0) << OFF_SETBITS_SHIFT) +#define LED_INIRQ_OFF_CLRBITS ((STM32F4_LED2) << OFF_CLRBITS_SHIFT) + +#define LED_SIGNAL_ON_SETBITS ((STM32F4_LED2) << ON_SETBITS_SHIFT) +#define LED_SIGNAL_ON_CLRBITS ((0) << ON_CLRBITS_SHIFT) +#define LED_SIGNAL_OFF_SETBITS ((0) << OFF_SETBITS_SHIFT) +#define LED_SIGNAL_OFF_CLRBITS ((STM32F4_LED2) << OFF_CLRBITS_SHIFT) + +#define LED_ASSERTION_ON_SETBITS ((STM32F4_LED2) << ON_SETBITS_SHIFT) +#define LED_ASSERTION_ON_CLRBITS ((0) << ON_CLRBITS_SHIFT) +#define LED_ASSERTION_OFF_SETBITS ((0) << OFF_SETBITS_SHIFT) +#define LED_ASSERTION_OFF_CLRBITS ((STM32F4_LED2) << OFF_CLRBITS_SHIFT) + +#define LED_PANIC_ON_SETBITS ((STM32F4_LED2) << ON_SETBITS_SHIFT) +#define LED_PANIC_ON_CLRBITS ((0) << ON_CLRBITS_SHIFT) +#define LED_PANIC_OFF_SETBITS ((0) << OFF_SETBITS_SHIFT) +#define LED_PANIC_OFF_CLRBITS ((STM32F4_LED2) << OFF_CLRBITS_SHIFT) + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static const uint16_t g_ledbits[8] = +{ + (LED_STARTED_ON_SETBITS | LED_STARTED_ON_CLRBITS | + LED_STARTED_OFF_SETBITS | LED_STARTED_OFF_CLRBITS), + + (LED_HEAPALLOCATE_ON_SETBITS | LED_HEAPALLOCATE_ON_CLRBITS | + LED_HEAPALLOCATE_OFF_SETBITS | LED_HEAPALLOCATE_OFF_CLRBITS), + + (LED_IRQSENABLED_ON_SETBITS | LED_IRQSENABLED_ON_CLRBITS | + LED_IRQSENABLED_OFF_SETBITS | LED_IRQSENABLED_OFF_CLRBITS), + + (LED_STACKCREATED_ON_SETBITS | LED_STACKCREATED_ON_CLRBITS | + LED_STACKCREATED_OFF_SETBITS | LED_STACKCREATED_OFF_CLRBITS), + + (LED_INIRQ_ON_SETBITS | LED_INIRQ_ON_CLRBITS | + LED_INIRQ_OFF_SETBITS | LED_INIRQ_OFF_CLRBITS), + + (LED_SIGNAL_ON_SETBITS | LED_SIGNAL_ON_CLRBITS | + LED_SIGNAL_OFF_SETBITS | LED_SIGNAL_OFF_CLRBITS), + + (LED_ASSERTION_ON_SETBITS | LED_ASSERTION_ON_CLRBITS | + LED_ASSERTION_OFF_SETBITS | LED_ASSERTION_OFF_CLRBITS), + + (LED_PANIC_ON_SETBITS | LED_PANIC_ON_CLRBITS | + LED_PANIC_OFF_SETBITS | LED_PANIC_OFF_CLRBITS) +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +static inline void led_clrbits(unsigned int clrbits) +{ + if ((clrbits & STM32F4_LED1) != 0) + { + stm32_gpiowrite(GPIO_LED1, false); + } + + if ((clrbits & STM32F4_LED2) != 0) + { + stm32_gpiowrite(GPIO_LED2, false); + } +} + +static inline void led_setbits(unsigned int setbits) +{ + if ((setbits & STM32F4_LED1) != 0) + { + stm32_gpiowrite(GPIO_LED1, true); + } + + if ((setbits & STM32F4_LED2) != 0) + { + stm32_gpiowrite(GPIO_LED2, true); + } +} + +static void led_setonoff(unsigned int bits) +{ + led_clrbits(CLRBITS(bits)); + led_setbits(SETBITS(bits)); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_autoled_initialize + ****************************************************************************/ + +void board_autoled_initialize(void) +{ + /* Configure LED1-4 GPIOs for output */ + + stm32_configgpio(GPIO_LED1); + stm32_configgpio(GPIO_LED2); +} + +/**************************************************************************** + * Name: board_autoled_on + ****************************************************************************/ + +void board_autoled_on(int led) +{ + led_setonoff(ON_BITS(g_ledbits[led])); +} + +/**************************************************************************** + * Name: board_autoled_off + ****************************************************************************/ + +void board_autoled_off(int led) +{ + led_setonoff(OFF_BITS(g_ledbits[led])); +} + +#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32f4/stm32f429i-disco/src/stm32_boot.c b/boards/arm/stm32f4/stm32f429i-disco/src/stm32_boot.c new file mode 100644 index 0000000000000..60fa8e9a75de2 --- /dev/null +++ b/boards/arm/stm32f4/stm32f429i-disco/src/stm32_boot.c @@ -0,0 +1,119 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f429i-disco/src/stm32_boot.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include +#include + +#include "arm_internal.h" +#include "stm32f429i-disco.h" +#include "stm32_ccm.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_boardinitialize + * + * Description: + * All STM32 architectures must provide the following entry point. + * This entry point is called early in the initialization -- after all + * memory has been configured and mapped but before any devices have been + * initialized. + * + ****************************************************************************/ + +void stm32_boardinitialize(void) +{ +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || \ + defined(CONFIG_STM32_SPI3) || defined(CONFIG_STM32_SPI4) || \ + defined(CONFIG_STM32_SPI5) + + /* Configure SPI chip selects if 1) SPI is not disabled, and 2) the weak + * function stm32_spidev_initialize() has been brought into the link. + */ + + if (stm32_spidev_initialize) + { + stm32_spidev_initialize(); + } +#endif + +#ifdef CONFIG_STM32_OTGHS + /* Initialize USB if the 1) OTG HS controller is in the configuration and + * 2) disabled, and 3) the weak function stm32_usbinitialize() has been + * brought into the build. Presumably either CONFIG_USBDEV or + * CONFIG_USBHOST is also selected. + */ + + if (stm32_usbinitialize) + { + stm32_usbinitialize(); + } +#endif + +#ifdef CONFIG_ARCH_LEDS + /* Configure on-board LEDs if LED support has been selected. */ + + board_autoled_initialize(); +#endif + +#ifdef CONFIG_STM32_FMC + stm32_sdram_initialize(); +#endif + +#ifdef HAVE_CCM_HEAP + /* Initialize CCM allocator */ + + ccm_initialize(); +#endif +} + +/**************************************************************************** + * Name: board_late_initialize + * + * Description: + * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_late_initialize(). board_late_initialize() will be + * called immediately after up_initialize() is called and just before the + * initial application is started. This additional initialization phase + * may be used, for example, to initialize board-specific device drivers. + * + ****************************************************************************/ + +#ifdef CONFIG_BOARD_LATE_INITIALIZE +void board_late_initialize(void) +{ + /* Perform board-specific initialization */ + + stm32_bringup(); +} +#endif diff --git a/boards/arm/stm32f4/stm32f429i-disco/src/stm32_bringup.c b/boards/arm/stm32f4/stm32f429i-disco/src/stm32_bringup.c new file mode 100644 index 0000000000000..5b59f2dcf00c6 --- /dev/null +++ b/boards/arm/stm32f4/stm32f429i-disco/src/stm32_bringup.c @@ -0,0 +1,429 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f429i-disco/src/stm32_bringup.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include +#include + +#ifdef CONFIG_STM32_SPI4 +# include +#endif + +#if defined(CONFIG_MTD_SST25XX) || defined(CONFIG_MTD_PROGMEM) +# include +#endif + +#ifdef CONFIG_VIDEO_FB +# include +#endif + +#ifdef CONFIG_USBMONITOR +# include +#endif + +#ifndef CONFIG_STM32F429I_DISCO_FLASH_MINOR +#define CONFIG_STM32F429I_DISCO_FLASH_MINOR 0 +#endif + +#ifdef CONFIG_STM32F429I_DISCO_FLASH_CONFIG_PART +#ifdef CONFIG_PLATFORM_CONFIGDATA +# include +#endif +#endif + +#ifdef CONFIG_STM32_OTGHS +# include "stm32_usbhost.h" +#endif + +#include "stm32.h" +#include "stm32f429i-disco.h" + +#ifdef CONFIG_INPUT_BUTTONS_LOWER +# include +#endif + +#ifdef CONFIG_SENSORS_L3GD20 +#include "stm32_l3gd20.h" +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_bringup + * + * Description: + * Perform architecture-specific initialization + * + * CONFIG_BOARD_LATE_INITIALIZE=y : + * Called from board_late_initialize(). + * + ****************************************************************************/ + +int stm32_bringup(void) +{ +#if defined(CONFIG_STM32_SPI4) + struct spi_dev_s *spi; +#endif +#if defined(CONFIG_MTD) + struct mtd_dev_s *mtd; +#if defined (CONFIG_MTD_SST25XX) + struct mtd_geometry_s geo; +#endif +#endif +#if defined(CONFIG_MTD_PARTITION_NAMES) + const char *partname = CONFIG_STM32F429I_DISCO_FLASH_PART_NAMES; +#endif + int ret; + +#ifdef HAVE_PROC + /* mount the proc filesystem */ + + ret = nx_mount(NULL, CONFIG_NSH_PROC_MOUNTPOINT, "procfs", 0, NULL); + if (ret < 0) + { + syslog(LOG_ERR, + "ERROR: Failed to mount the PROC filesystem: %d\n", ret); + return ret; + } +#endif + + /* Configure SPI-based devices */ + +#if defined(CONFIG_MTD) && defined(CONFIG_MTD_PROGMEM) + mtd = progmem_initialize(); + if (mtd == NULL) + { + syslog(LOG_ERR, "ERROR: progmem_initialize\n"); + } + + ret = register_mtddriver("/dev/flash", mtd, 0, mtd); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: register_mtddriver() failed: %d\n", ret); + } + +#endif + +#ifdef CONFIG_STM32_SPI4 + /* Get the SPI port */ + + syslog(LOG_INFO, "Initializing SPI port 4\n"); + + spi = stm32_spibus_initialize(4); + if (!spi) + { + syslog(LOG_ERR, "ERROR: Failed to initialize SPI port 4\n"); + return -ENODEV; + } + + syslog(LOG_INFO, "Successfully initialized SPI port 4\n"); + + /* Now bind the SPI interface to the SST25F064 SPI FLASH driver. This + * is a FLASH device that has been added external to the board (i.e. + * the board does not ship from STM with any on-board FLASH. + */ + +#if defined(CONFIG_MTD) && defined(CONFIG_MTD_SST25XX) + syslog(LOG_INFO, "Bind SPI to the SPI flash driver\n"); + + mtd = sst25xx_initialize(spi); + if (!mtd) + { + syslog(LOG_ERR, "ERROR: Failed to bind SPI port 4 to the SPI FLASH" + " driver\n"); + } + else + { + syslog(LOG_INFO, "Successfully bound SPI port 4 to the SPI FLASH" + " driver\n"); + + /* Get the geometry of the FLASH device */ + + ret = mtd->ioctl(mtd, MTDIOC_GEOMETRY, + (unsigned long)((uintptr_t)&geo)); + if (ret < 0) + { + ferr("ERROR: mtd->ioctl failed: %d\n", ret); + return ret; + } + +#ifdef CONFIG_STM32F429I_DISCO_FLASH_PART + { + int partno; + int partsize; + int partoffset; + int partszbytes; + int erasesize; + const char *partstring = CONFIG_STM32F429I_DISCO_FLASH_PART_LIST; + const char *ptr; + struct mtd_dev_s *mtd_part; + char partref[16]; + + /* Now create a partition on the FLASH device */ + + partno = 0; + ptr = partstring; + partoffset = 0; + + /* Get the Flash erase size */ + + erasesize = geo.erasesize; + + while (*ptr != '\0') + { + /* Get the partition size */ + + partsize = atoi(ptr); + partszbytes = (partsize << 10); /* partsize is defined in KB */ + + /* Check if partition size is bigger then erase block */ + + if (partszbytes < erasesize) + { + ferr("ERROR: Partition size is lesser than erasesize!\n"); + return -1; + } + + /* Check if partition size is multiple of erase block */ + + if ((partszbytes % erasesize) != 0) + { + ferr("ERROR: Partition size is not multiple of" + " erasesize!\n"); + return -1; + } + + mtd_part = mtd_partition(mtd, partoffset, + partszbytes / erasesize); + partoffset += partszbytes / erasesize; + +#ifdef CONFIG_STM32F429I_DISCO_FLASH_CONFIG_PART + /* Test if this is the config partition */ + + if (CONFIG_STM32F429I_DISCO_FLASH_CONFIG_PART_NUMBER == partno) + { + /* Register the partition as the config device */ + + mtdconfig_register(mtd_part); + } + else +#endif + { + /* Now initialize a SMART Flash block device and bind it + * to the MTD device. + */ + +#if defined(CONFIG_MTD_SMART) && defined(CONFIG_FS_SMARTFS) + snprintf(partref, sizeof(partref), "p%d", partno); + smart_initialize(CONFIG_STM32F429I_DISCO_FLASH_MINOR, + mtd_part, partref); +#endif + } + +#if defined(CONFIG_MTD_PARTITION_NAMES) + /* Set the partition name */ + + if (mtd_part == NULL) + { + ferr("ERROR: failed to create partition %s\n", partname); + return -1; + } + + mtd_setpartitionname(mtd_part, partname); + + /* Now skip to next name. We don't need to split the string + * here because the MTD partition logic will only display names + * up to the comma, thus allowing us to use a single static + * name in the code. + */ + + while (*partname != ',' && *partname != '\0') + { + /* Skip to next ',' */ + + partname++; + } + + if (*partname == ',') + { + partname++; + } +#endif + + /* Update the pointer to point to the next size in the list */ + + while ((*ptr >= '0') && (*ptr <= '9')) + { + ptr++; + } + + if (*ptr == ',') + { + ptr++; + } + + /* Increment the part number */ + + partno++; + } + } +#else /* CONFIG_STM32F429I_DISCO_FLASH_PART */ + + /* Configure the device with no partition support */ + + smart_initialize(CONFIG_STM32F429I_DISCO_FLASH_MINOR, mtd, NULL); + +#endif /* CONFIG_STM32F429I_DISCO_FLASH_PART */ + } + +#endif /* CONFIG_MTD */ +#endif /* CONFIG_STM32_SPI4 */ + +#ifdef CONFIG_VIDEO_FB + /* Initialize and register the framebuffer driver */ + + ret = fb_register(0, 0); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: fb_register() failed: %d\n", ret); + } +#endif + +#if defined(CONFIG_RAMMTD) && defined(CONFIG_STM32F429I_DISCO_RAMMTD) + /* Create a RAM MTD device if configured */ + + { + uint8_t *start = + kmm_malloc(CONFIG_STM32F429I_DISCO_RAMMTD_SIZE * 1024); + mtd = rammtd_initialize(start, + CONFIG_STM32F429I_DISCO_RAMMTD_SIZE * 1024); + mtd->ioctl(mtd, MTDIOC_BULKERASE, 0); + + /* Now initialize a SMART Flash block device and bind it to the MTD + * device + */ + +#if defined(CONFIG_MTD_SMART) && defined(CONFIG_FS_SMARTFS) + smart_initialize(CONFIG_STM32F429I_DISCO_RAMMTD_MINOR, mtd, NULL); +#endif + } + +#endif /* CONFIG_RAMMTD && CONFIG_STM32F429I_DISCO_RAMMTD */ + +#ifdef HAVE_USBHOST + /* Initialize USB host operation. stm32_usbhost_initialize() starts a + * thread will monitor for USB connection and disconnection events. + */ + + ret = stm32_usbhost_initialize(); + if (ret != OK) + { + syslog(LOG_ERR, "ERROR: Failed to initialize USB host: %d\n", ret); + return ret; + } +#endif + +#ifdef HAVE_USBMONITOR + /* Start the USB Monitor */ + + ret = usbmonitor_start(); + if (ret != OK) + { + syslog(LOG_ERR, "ERROR: Failed to start USB monitor: %d\n", ret); + } +#endif + +#ifdef CONFIG_INPUT_BUTTONS_LOWER + /* Register the BUTTON driver */ + + ret = btn_lower_initialize("/dev/buttons"); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: btn_lower_initialize() failed: %d\n", ret); + } +#endif /* CONFIG_INPUT_BUTTONS_LOWER */ + +#ifdef CONFIG_INPUT_STMPE811 + /* Initialize the touchscreen */ + + ret = stm32_tsc_setup(0); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_tsc_setup failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_SENSORS_L3GD20 + ret = board_l3gd20_initialize(0, 5); + if (ret != OK) + { + syslog(LOG_ERR, "ERROR: Failed to initialize l3gd20 sensor:" + " %d\n", ret); + } +#endif + +#ifdef CONFIG_PWM + /* Initialize PWM and register the PWM device. */ + + ret = stm32_pwm_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_pwm_setup() failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_ADC + /* Initialize ADC and register the ADC device. */ + + ret = stm32_adc_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_adc_setup() failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_STM32_CAN_CHARDRIVER + /* Initialize CAN and register the CAN driver. */ + + ret = stm32_can_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_can_setup failed: %d\n", ret); + } +#endif + + UNUSED(ret); + return OK; +} diff --git a/boards/arm/stm32f4/stm32f429i-disco/src/stm32_buttons.c b/boards/arm/stm32f4/stm32f429i-disco/src/stm32_buttons.c new file mode 100644 index 0000000000000..80439363c1a2e --- /dev/null +++ b/boards/arm/stm32f4/stm32f429i-disco/src/stm32_buttons.c @@ -0,0 +1,150 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f429i-disco/src/stm32_buttons.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include +#include + +#include "stm32f429i-disco.h" + +#ifdef CONFIG_ARCH_BUTTONS + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* Pin configuration for each STM32F4 Discovery button. This array is indexed + * by the BUTTON_* definitions in board.h + */ + +static const uint32_t g_buttons[NUM_BUTTONS] = +{ + GPIO_BTN_USER +}; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_button_initialize + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. + * + ****************************************************************************/ + +uint32_t board_button_initialize(void) +{ + int i; + + /* Configure the GPIO pins as inputs. NOTE that EXTI interrupts are + * configured for all pins. + */ + + for (i = 0; i < NUM_BUTTONS; i++) + { + stm32_configgpio(g_buttons[i]); + } + + return NUM_BUTTONS; +} + +/**************************************************************************** + * Name: board_buttons + ****************************************************************************/ + +uint32_t board_buttons(void) +{ + uint32_t ret = 0; + int i; + + /* Check that state of each key */ + + for (i = 0; i < NUM_BUTTONS; i++) + { + /* A LOW value means that the key is pressed. */ + + bool released = stm32_gpioread(g_buttons[i]); + + /* Accumulate the set of depressed (not released) keys */ + + if (!released) + { + ret |= (1 << i); + } + } + + return ret; +} + +/**************************************************************************** + * Button support. + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. + * + * After board_button_initialize() has been called, board_buttons() may be + * called to collect the state of all buttons. board_buttons() returns an + * 32-bit bit set with each bit associated with a button. See the + * BUTTON_*_BIT definitions in board.h for the meaning of each bit. + * + * board_button_irq() may be called to register an interrupt handler that + * will be called when a button is depressed or released. The ID value is a + * button enumeration value that uniquely identifies a button resource. See + * the BUTTON_* definitions in board.h for the meaning of enumeration + * value. + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_IRQBUTTONS +int board_button_irq(int id, xcpt_t irqhandler, void *arg) +{ + int ret = -EINVAL; + + /* The following should be atomic */ + + if (id >= MIN_IRQBUTTON && id <= MAX_IRQBUTTON) + { + ret = stm32_gpiosetevent(g_buttons[id], true, true, true, + irqhandler, arg); + } + + return ret; +} +#endif +#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/stm32f4/stm32f429i-disco/src/stm32_can.c b/boards/arm/stm32f4/stm32f429i-disco/src/stm32_can.c new file mode 100644 index 0000000000000..565420489dcd3 --- /dev/null +++ b/boards/arm/stm32f4/stm32f429i-disco/src/stm32_can.c @@ -0,0 +1,102 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f429i-disco/src/stm32_can.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32.h" +#include "stm32_can.h" +#include "stm32f429i-disco.h" + +#ifdef CONFIG_CAN + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +#if defined(CONFIG_STM32_CAN1) && defined(CONFIG_STM32_CAN2) +# warning "Both CAN1 and CAN2 are enabled. Assuming only CAN1." +# undef CONFIG_STM32_CAN2 +#endif + +#ifdef CONFIG_STM32_CAN1 +# define CAN_PORT 1 +#else +# define CAN_PORT 2 +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_can_setup + * + * Description: + * Initialize CAN and register the CAN device + * + ****************************************************************************/ + +int stm32_can_setup(void) +{ +#if defined(CONFIG_STM32_CAN1) || defined(CONFIG_STM32_CAN2) + struct can_dev_s *can; + int ret; + + /* Call stm32_caninitialize() to get an instance of the CAN interface */ + + can = stm32_caninitialize(CAN_PORT); + if (can == NULL) + { + canerr("ERROR: Failed to get CAN interface\n"); + return -ENODEV; + } + + /* Register the CAN driver at "/dev/can0" */ + + ret = can_register("/dev/can0", can); + if (ret < 0) + { + canerr("ERROR: can_register failed: %d\n", ret); + return ret; + } + + return OK; +#else + return -ENODEV; +#endif +} + +#endif /* CONFIG_CAN */ diff --git a/boards/arm/stm32f4/stm32f429i-disco/src/stm32_extmem.c b/boards/arm/stm32f4/stm32f429i-disco/src/stm32_extmem.c new file mode 100644 index 0000000000000..d0f2faf088d0b --- /dev/null +++ b/boards/arm/stm32f4/stm32f429i-disco/src/stm32_extmem.c @@ -0,0 +1,178 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f429i-disco/src/stm32_extmem.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32.h" +#include "stm32f429i-disco.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifndef CONFIG_STM32_FMC +#warning "FMC is not enabled" +#endif + +#if STM32_NGPIO_PORTS < 6 +#error "Required GPIO ports not enabled" +#endif + +#define STM32_SDRAM_CLKEN FMC_SDCMR_CMD_CLK_ENABLE | FMC_SDCMR_BANK_2 + +#define STM32_SDRAM_PALL FMC_SDCMR_CMD_PALL | FMC_SDCMR_BANK_2 + +#define STM32_SDRAM_REFRESH FMC_SDCMR_CMD_AUTO_REFRESH | FMC_SDCMR_BANK_2 |\ + FMC_SDCMR_NRFS(4) + +#define STM32_SDRAM_MODEREG FMC_SDCMR_CMD_LOAD_MODE | FMC_SDCMR_BANK_2 |\ + FMC_SDCMR_MDR_BURST_LENGTH_2 | \ + FMC_SDCMR_MDR_BURST_TYPE_SEQUENTIAL |\ + FMC_SDCMR_MDR_CAS_LATENCY_3 |\ + FMC_SDCMR_MDR_WBL_SINGLE + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* GPIO configurations common to most external memories */ + +static const uint32_t g_sdram_config[] = +{ + /* 16 data lines */ + + GPIO_FMC_D0, GPIO_FMC_D1, GPIO_FMC_D2, GPIO_FMC_D3, + GPIO_FMC_D4, GPIO_FMC_D5, GPIO_FMC_D6, GPIO_FMC_D7, + GPIO_FMC_D8, GPIO_FMC_D9, GPIO_FMC_D10, GPIO_FMC_D11, + GPIO_FMC_D12, GPIO_FMC_D13, GPIO_FMC_D14, GPIO_FMC_D15, + + /* 12 address lines */ + + GPIO_FMC_A0, GPIO_FMC_A1, GPIO_FMC_A2, GPIO_FMC_A3, + GPIO_FMC_A4, GPIO_FMC_A5, GPIO_FMC_A6, GPIO_FMC_A7, + GPIO_FMC_A8, GPIO_FMC_A9, GPIO_FMC_A10, GPIO_FMC_A11, + + /* control lines */ + + GPIO_FMC_SDCKE1, GPIO_FMC_SDNE1, GPIO_FMC_SDNWE, GPIO_FMC_NBL0, + GPIO_FMC_SDNRAS, GPIO_FMC_NBL1, GPIO_FMC_BA0, GPIO_FMC_BA1, + GPIO_FMC_SDCLK, GPIO_FMC_SDNCAS, +}; + +#define NUM_SDRAM_GPIOS (sizeof(g_sdram_config) / sizeof(uint32_t)) + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_sdram_initialize + * + * Description: + * Called from stm32_bringup to initialize external SDRAM access. + * + ****************************************************************************/ + +void stm32_sdram_initialize(void) +{ + uint32_t val; + int i; + volatile int count; + + /* Enable GPIOs as FMC / memory pins */ + + for (i = 0; i < NUM_SDRAM_GPIOS; i++) + { + stm32_configgpio(g_sdram_config[i]); + } + + /* Enable AHB clocking to the FMC */ + + stm32_fmc_enable(); + + /* Configure and enable the SDRAM bank1 + * + * FMC clock = 180MHz/2 = 90MHz + * 90MHz = 11,11 ns + * All timings from the datasheet for Speedgrade -7 (=7ns) + */ + + val = FMC_SDCR_RPIPE_1 | /* rpipe = 1 hclk */ + FMC_SDCR_SDCLK_2X | /* sdclk = 2 hclk */ + FMC_SDCR_CAS_LATENCY_3 | /* cas latency = 3 cycles */ + FMC_SDCR_NBANKS_4 | /* 4 internal banks */ + FMC_SDCR_WIDTH_16 | /* width = 16 bits */ + FMC_SDCR_ROWS_12 | /* numrows = 12 */ + FMC_SDCR_COLS_8; /* numcols = 8 bits */ + stm32_fmc_sdram_set_control(1, val); + stm32_fmc_sdram_set_control(2, val); + + val = FMC_SDTR_TRCD(3) | /* tRCD min = 15ns */ + FMC_SDTR_TRP(3) | /* tRP min = 15ns */ + FMC_SDTR_TWR(3) | /* tWR = 2CLK */ + FMC_SDTR_TRC(8) | /* tRC min = 63ns */ + FMC_SDTR_TRAS(5) | /* tRAS min = 42ns */ + FMC_SDTR_TXSR(8) | /* tXSR min = 70ns */ + FMC_SDTR_TMRD(3); /* tMRD = 2CLK */ + stm32_fmc_sdram_set_timing(2, val); + + /* SDRAM Initialization sequence */ + + stm32_fmc_sdram_command(STM32_SDRAM_CLKEN); /* Clock enable command */ + for (count = 0; count < 10000; count++); /* Delay */ + stm32_fmc_sdram_command(STM32_SDRAM_PALL); /* Precharge ALL command */ + stm32_fmc_sdram_command(STM32_SDRAM_REFRESH); /* Auto refresh command */ + stm32_fmc_sdram_command(STM32_SDRAM_MODEREG); /* Mode Register program */ + + /* Set refresh count + * + * FMC_CLK = 90MHz + * Refresh_Rate = 7.81us + * Counter = (FMC_CLK * Refresh_Rate) - 20 + */ + + stm32_fmc_sdram_set_refresh_rate(683); + + /* Disable write protection */ + + /* stm32_fmc_sdram_write_protect(2, false); */ +} diff --git a/boards/arm/stm32f4/stm32f429i-disco/src/stm32_highpri.c b/boards/arm/stm32f4/stm32f429i-disco/src/stm32_highpri.c new file mode 100644 index 0000000000000..66ec057d07c5b --- /dev/null +++ b/boards/arm/stm32f4/stm32f429i-disco/src/stm32_highpri.c @@ -0,0 +1,535 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f429i-disco/src/stm32_highpri.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include +#include + +#include "arm_internal.h" +#include "ram_vectors.h" + +#include "stm32_pwm.h" +#include "stm32_adc.h" +#include "stm32_dma.h" + +#include +#ifdef CONFIG_STM32F429I_DISCO_HIGHPRI + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +#ifndef CONFIG_ARCH_HIPRI_INTERRUPT +# error CONFIG_ARCH_HIPRI_INTERRUPT is required +#endif + +#ifndef CONFIG_ARCH_RAMVECTORS +# error CONFIG_ARCH_RAMVECTORS is required +#endif + +#ifndef CONFIG_ARCH_IRQPRIO +# error CONFIG_ARCH_IRQPRIO is required +#endif + +#ifndef CONFIG_ARCH_FPU +# warning Set CONFIG_ARCH_FPU for hardware FPU support +#endif + +#ifdef CONFIG_STM32_ADC1_DMA +# if defined(CONFIG_STM32_TIM1_PWM) +# define HIGHPRI_HAVE_TIM1 +# endif +# if (CONFIG_STM32_ADC1_DMA_CFG != 1) +# error ADC1 DMA must be configured in Circular Mode +# endif +# if !defined(HIGHPRI_HAVE_TIM1) +# error "Needs TIM1 to trigger ADC DMA" +# endif +#endif + +#if (CONFIG_STM32_ADC1_INJECTED_CHAN > 0) +# if (CONFIG_STM32_ADC1_INJECTED_CHAN > 1) +# error Max 1 injected channels supported for now +# else +# define HIGHPRI_HAVE_INJECTED +# endif +#endif + +#ifdef HIGHPRI_HAVE_INJECTED +# define INJ_NCHANNELS CONFIG_STM32_ADC1_INJECTED_CHAN +#else +# define INJ_NCHANNELS (0) +#endif + +#ifndef CONFIG_STM32_ADC1_DMA +# define REG_NCHANNELS (1) +#else +# define REG_NCHANNELS (1) +#endif + +#define ADC1_NCHANNELS (REG_NCHANNELS + INJ_NCHANNELS) + +#define DEV1_PORT (1) +#define DEV1_NCHANNELS ADC1_NCHANNELS +#define ADC_REF_VOLTAGE (3.3f) +#define ADC_VAL_MAX (4095) + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/* High priority example private data */ + +struct highpri_s +{ + struct stm32_adc_dev_s *adc1; +#ifdef HIGHPRI_HAVE_TIM1 + struct stm32_pwm_dev_s *pwm; +#endif + volatile uint32_t cntr1; + volatile uint32_t cntr2; + volatile uint8_t current; + uint16_t r_val[REG_NCHANNELS]; + float r_volt[REG_NCHANNELS]; +#ifdef HIGHPRI_HAVE_INJECTED + uint16_t j_val[INJ_NCHANNELS]; + float j_volt[INJ_NCHANNELS]; +#endif + bool lock; +}; + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* ADC channel list */ + +static const uint8_t g_chanlist1[DEV1_NCHANNELS] = +{ + 5, +#if INJ_NCHANNELS > 0 + 13, +#endif +}; + +/* Configurations of pins used by ADC channel */ + +static const uint32_t g_pinlist1[DEV1_NCHANNELS] = +{ + GPIO_ADC1_IN5_0, /* PA5 */ +#if INJ_NCHANNELS > 0 + GPIO_ADC1_IN13_0, /* PC3 */ +#endif +}; + +static struct highpri_s g_highpri; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: adc12_handler + * + * Description: + * This is the handler for the high speed ADC interrupt. + * + ****************************************************************************/ + +#if !defined(CONFIG_STM32_ADC1_DMA) || defined(HIGHPRI_HAVE_INJECTED) +void adc_handler(void) +{ + struct stm32_adc_dev_s *adc = g_highpri.adc1; + float ref = ADC_REF_VOLTAGE; + float bit = ADC_VAL_MAX; + uint32_t pending; +#ifdef HIGHPRI_HAVE_INJECTED + int i = 0; +#endif + + /* Get pending ADC1 interrupts */ + + pending = STM32_ADC_INT_GET(adc); + + if (g_highpri.lock == true) + { + goto irq_out; + } + +#ifndef CONFIG_STM32_ADC1_DMA + /* Regular channel end of conversion */ + + if (pending & ADC_ISR_EOC) + { + /* Increase regular sequence counter */ + + g_highpri.cntr1 += 1; + + /* Get regular data */ + + g_highpri.r_val[g_highpri.current] = STM32_ADC_REGDATA_GET(adc); + + /* Do some floating point operations */ + + g_highpri.r_volt[g_highpri.current] = + (float)g_highpri.r_val[g_highpri.current] * ref / bit; + + if (g_highpri.current >= REG_NCHANNELS - 1) + { + g_highpri.current = 0; + } + else + { + g_highpri.current += 1; + } + } +#endif + +#ifdef HIGHPRI_HAVE_INJECTED + /* Injected channel end of sequence */ + + if (pending & ADC_ISR_JEOC) + { + /* Increase injected sequence counter */ + + g_highpri.cntr2 += 1; + + /* Get injected channels */ + + for (i = 0; i < INJ_NCHANNELS; i += 1) + { + g_highpri.j_val[i] = STM32_ADC_INJDATA_GET(adc, i); + } + + /* Do some floating point operations */ + + for (i = 0; i < INJ_NCHANNELS; i += 1) + { + g_highpri.j_volt[i] = (float)g_highpri.j_val[i] * ref / bit; + } + } +#endif + +irq_out: + + /* Clear ADC pending interrupts */ + + STM32_ADC_INT_ACK(adc, pending); +} +#endif + +/**************************************************************************** + * Name: dma2s0_handler + * + * Description: + * This is the handler for the high speed ADC interrupt using DMA transfer. + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_ADC1_DMA +void dma2s0_handler(void) +{ + float ref = ADC_REF_VOLTAGE; + float bit = ADC_VAL_MAX; + uint8_t pending; + int i; + + pending = stm32_dma_intget(DMA2, DMA_STREAM0); + + if (g_highpri.lock == true) + { + goto irq_out; + } + + /* Increase regular sequence counter */ + + g_highpri.cntr1 += 1; + + for (i = 0; i < REG_NCHANNELS; i += 1) + { + /* Do some floating point operations */ + + g_highpri.r_volt[i] = (float)g_highpri.r_val[i] * ref / bit; + } + +irq_out: + + /* Clear DMA pending interrupts */ + + stm32_dma_intack(DMA2, DMA_STREAM0, pending); +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: highpri_main + * + * Description: + * Main entry point in into the high priority interrupt test. + * + ****************************************************************************/ + +int highpri_main(int argc, char *argv[]) +{ +#ifdef HIGHPRI_HAVE_TIM1 + struct stm32_pwm_dev_s *pwm1; +#endif + struct adc_dev_s *adc1; + struct highpri_s *highpri; + int ret; + int i; + + highpri = &g_highpri; + + /* Initialize highpri structure */ + + memset(highpri, 0, sizeof(struct highpri_s)); + + printf("\nhighpri_main: Started\n"); + + /* Configure the pins as analog inputs for the selected channels */ + + for (i = 0; i < DEV1_NCHANNELS; i++) + { + stm32_configgpio(g_pinlist1[i]); + } + + /* Initialize ADC driver */ + + adc1 = stm32_adcinitialize(DEV1_PORT, g_chanlist1, DEV1_NCHANNELS); + if (adc1 == NULL) + { + aerr("ERROR: Failed to get ADC interface 1\n"); + ret = EXIT_FAILURE; + goto errout; + } + + highpri->adc1 = (struct stm32_adc_dev_s *)adc1->ad_priv; + +#ifdef HIGHPRI_HAVE_TIM1 + /* Initialize TIM1 */ + + pwm1 = (struct stm32_pwm_dev_s *) stm32_pwminitialize(1); + if (pwm1 == NULL) + { + printf("ERROR: Failed to get PWM1 interface\n"); + ret = EXIT_FAILURE; + goto errout; + } + + highpri->pwm = pwm1; + + /* Setup PWM device */ + + PWM_SETUP(pwm1); + + /* Set timer frequency */ + + PWM_FREQ_UPDATE(pwm1, 1000); + + /* Set CCR1 */ + + PWM_CCR_UPDATE(pwm1, 1, 0x0f00); + + /* Enable TIM1 OUT1 */ + + PWM_OUTPUTS_ENABLE(pwm1, STM32_PWM_OUT1, true); + +#ifdef CONFIG_DEBUG_PWM_INFO + /* Print debug */ + + PWM_DUMP_REGS(pwm1); +#endif + +#endif /* HIGHPRI_HAVE_TIM1 */ + +#if !defined(CONFIG_STM32_ADC1_DMA) || defined(HIGHPRI_HAVE_INJECTED) + /* Attach ADC ram vector if no DMA or injected channels support */ + + ret = arm_ramvec_attach(STM32_IRQ_ADC, adc_handler); + if (ret < 0) + { + fprintf(stderr, "highpri_main: ERROR: arm_ramvec_attach failed: %d\n", + ret); + ret = EXIT_FAILURE; + goto errout; + } + + /* Set the priority of the ADC interrupt vector */ + + ret = up_prioritize_irq(STM32_IRQ_ADC, NVIC_SYSH_HIGH_PRIORITY); + if (ret < 0) + { + fprintf(stderr, "highpri_main: ERROR: up_prioritize_irq failed: %d\n", + ret); + ret = EXIT_FAILURE; + goto errout; + } + + up_enable_irq(STM32_IRQ_ADC); +#endif + +#ifdef CONFIG_STM32_ADC1_DMA + /* Attach DMA2 STREAM0 ram vector if DMA */ + + ret = arm_ramvec_attach(STM32_IRQ_DMA2S0, dma2s0_handler); + if (ret < 0) + { + fprintf(stderr, "highpri_main: ERROR: arm_ramvec_attach failed: %d\n", + ret); + ret = EXIT_FAILURE; + goto errout; + } + + /* Set the priority of the DMA2 STREAM0 interrupt vector */ + + ret = up_prioritize_irq(STM32_IRQ_DMA2S0, NVIC_SYSH_HIGH_PRIORITY); + if (ret < 0) + { + fprintf(stderr, "highpri_main: ERROR: up_prioritize_irq failed: %d\n", + ret); + ret = EXIT_FAILURE; + goto errout; + } + + up_enable_irq(STM32_IRQ_DMA2S0); +#endif + + /* Setup ADC hardware */ + + adc1->ad_ops->ao_setup(adc1); + + /* Configure regular channels trigger to T1CC1 */ + + STM32_ADC_EXTCFG_SET(highpri->adc1, + ADC1_EXTSEL_T1CC1 | ADC_EXTREG_EXTEN_DEFAULT); + +#ifndef CONFIG_STM32_ADC1_DMA + /* Enable ADC regular conversion interrupts if no DMA */ + + STM32_ADC_INT_ENABLE(highpri->adc1, ADC_IER_EOC); +#else + /* Note: ADC and DMA must be reset after overrun occurs. + * For this example we assume that overrun will not occur. + * This is true only if DMA and ADC trigger are properly configured. + * DMA configuration must be done before ADC trigger starts! + */ + + /* Register ADC buffer for DMA transfer */ + + STM32_ADC_REGBUF_REGISTER(highpri->adc1, g_highpri.r_val, REG_NCHANNELS); +#endif + +#ifdef HIGHPRI_HAVE_INJECTED + /* Enable ADC injected channels end of conversion interrupts */ + + STM32_ADC_INT_ENABLE(highpri->adc1, ADC_IER_JEOC); +#endif + +#ifdef HIGHPRI_HAVE_TIM1 + /* Enable timer counter after ADC and DMA configuration */ + + PWM_TIM_ENABLE(pwm1, true); +#endif + + while (1) + { +#ifndef CONFIG_STM32_ADC1_DMA + /* Software trigger for regular sequence */ + + adc1->ad_ops->ao_ioctl(adc1, IO_TRIGGER_REG, 0); + + nxsched_usleep(100); +#endif + +#ifdef HIGHPRI_HAVE_INJECTED + /* Software trigger for injected sequence */ + + adc1->ad_ops->ao_ioctl(adc1, IO_TRIGGER_INJ, 0); + + nxsched_usleep(100); +#endif + /* Lock global data */ + + g_highpri.lock = true; + +#ifndef CONFIG_STM32_ADC1_DMA + printf("%" PRId32 " [%d] %0.3fV\n", g_highpri.cntr1, g_highpri.current, + g_highpri.r_volt[g_highpri.current]); +#else + printf("%" PRId32 " ", g_highpri.cntr1); + + for (i = 0; i < REG_NCHANNELS; i += 1) + { + printf("r:[%d] %0.3fV, ", i, g_highpri.r_volt[i]); + } + + printf("\n"); +#endif + +#ifdef HIGHPRI_HAVE_INJECTED + /* Print data from injected channels */ + + printf("%" PRId32 " ", g_highpri.cntr2); + + for (i = 0; i < INJ_NCHANNELS; i += 1) + { + printf("j:[%d] %0.3fV, ", i, g_highpri.j_volt[i]); + } + + printf("\n"); +#endif + /* Unlock global data */ + + g_highpri.lock = false; + + nxsched_sleep(1); + } + +errout: + return ret; +} + +#endif /* CONFIG_STM32F429I_DISCO_HIGHPRI */ diff --git a/boards/arm/stm32f4/stm32f429i-disco/src/stm32_idle.c b/boards/arm/stm32f4/stm32f429i-disco/src/stm32_idle.c new file mode 100644 index 0000000000000..16b818e188a77 --- /dev/null +++ b/boards/arm/stm32f4/stm32f429i-disco/src/stm32_idle.c @@ -0,0 +1,263 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f429i-disco/src/stm32_idle.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include + +#include +#include +#include +#include + +#include + +#include "arm_internal.h" +#include "stm32_pm.h" +#include "stm32_rcc.h" +#include "stm32_exti.h" + +#include "stm32f429i-disco.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* Does the board support an IDLE LED to indicate that the board is in the + * IDLE state? + */ + +#if defined(CONFIG_ARCH_LEDS) && defined(LED_IDLE) +# define BEGIN_IDLE() board_autoled_on(LED_IDLE) +# define END_IDLE() board_autoled_off(LED_IDLE) +#else +# define BEGIN_IDLE() +# define END_IDLE() +#endif + +/* Values for the RTC Alarm to wake up from the PM_STANDBY mode */ + +#ifndef CONFIG_PM_ALARM_SEC +# define CONFIG_PM_ALARM_SEC 3 +#endif + +#ifndef CONFIG_PM_ALARM_NSEC +# define CONFIG_PM_ALARM_NSEC 0 +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#if defined(CONFIG_PM) && defined(CONFIG_RTC_ALARM) +static void stm32_alarmcb(void); +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_idlepm + * + * Description: + * Perform IDLE state power management. + * + ****************************************************************************/ + +#ifdef CONFIG_PM +static void stm32_idlepm(void) +{ +#ifdef CONFIG_RTC_ALARM + struct timespec alarmtime; +#endif + static enum pm_state_e oldstate = PM_NORMAL; + enum pm_state_e newstate; + irqstate_t flags; + int ret; + + /* Decide, which power saving level can be obtained */ + + newstate = pm_checkstate(PM_IDLE_DOMAIN); + + /* Check for state changes */ + + if (newstate != oldstate) + { + sinfo("newstate= %d oldstate=%d\n", newstate, oldstate); + + flags = enter_critical_section(); + + /* Force the global state change */ + + ret = pm_changestate(PM_IDLE_DOMAIN, newstate); + if (ret < 0) + { + /* The new state change failed, revert to the preceding state */ + + pm_changestate(PM_IDLE_DOMAIN, oldstate); + + /* No state change... */ + + goto errout; + } + + /* Then perform board-specific, state-dependent logic here */ + + switch (newstate) + { + case PM_NORMAL: + { + } + break; + + case PM_IDLE: + { + } + break; + + case PM_STANDBY: + { +#ifdef CONFIG_RTC_ALARM + /* Disable RTC Alarm interrupt */ + +#warning "missing logic" + + /* Configure the RTC alarm to Auto Wake the system */ + +#warning "missing logic" + + /* The tv_nsec value must not exceed 1,000,000,000. That + * would be an invalid time. + */ + +#warning "missing logic" + + /* Set the alarm */ + +#warning "missing logic" +#endif + /* Call the STM32 stop mode */ + + stm32_pmstop(true); + + /* We have been re-awakened by some even: A button press? + * An alarm? Cancel any pending alarm and resume the normal + * operation. + */ + +#ifdef CONFIG_RTC_ALARM +#warning "missing logic" +#endif + /* Resume normal operation */ + + pm_changestate(PM_IDLE_DOMAIN, PM_NORMAL); + newstate = PM_NORMAL; + } + break; + + case PM_SLEEP: + { + /* We should not return from standby mode. The only way out + * of standby is via the reset path. + */ + + stm32_pmstandby(); + } + break; + + default: + break; + } + + /* Save the new state */ + + oldstate = newstate; + +errout: + leave_critical_section(flags); + } +} +#else +# define stm32_idlepm() +#endif + +/**************************************************************************** + * Name: stm32_alarmcb + * + * Description: + * RTC alarm service routine + * + ****************************************************************************/ + +#if defined(CONFIG_PM) && defined(CONFIG_RTC_ALARM) +static void stm32_alarmcb(void) +{ + /* This alarm occurs because there wasn't any EXTI interrupt during the + * PM_STANDBY period. So just go to sleep. + */ + + pm_changestate(PM_IDLE_DOMAIN, PM_SLEEP); +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_idle + * + * Description: + * up_idle() is the logic that will be executed when their is no other + * ready-to-run task. This is processor idle time and will continue until + * some interrupt occurs to cause a context switch from the idle task. + * + * Processing in this state may be processor-specific. e.g., this is where + * power management operations might be performed. + * + ****************************************************************************/ + +void up_idle(void) +{ +#if defined(CONFIG_SUPPRESS_INTERRUPTS) || defined(CONFIG_SUPPRESS_TIMER_INTS) + /* If the system is idle and there are no timer interrupts, then process + * "fake" timer interrupts. Hopefully, something will wake up. + */ + + nxsched_process_timer(); +#else + + /* Perform IDLE mode power management */ + + BEGIN_IDLE(); + stm32_idlepm(); + END_IDLE(); +#endif +} diff --git a/boards/arm/stm32/stm32f429i-disco/src/stm32_ili93414ws.c b/boards/arm/stm32f4/stm32f429i-disco/src/stm32_ili93414ws.c similarity index 99% rename from boards/arm/stm32/stm32f429i-disco/src/stm32_ili93414ws.c rename to boards/arm/stm32f4/stm32f429i-disco/src/stm32_ili93414ws.c index 2171493eb4b9c..84c83f2113f32 100644 --- a/boards/arm/stm32/stm32f429i-disco/src/stm32_ili93414ws.c +++ b/boards/arm/stm32f4/stm32f429i-disco/src/stm32_ili93414ws.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f429i-disco/src/stm32_ili93414ws.c + * boards/arm/stm32f4/stm32f429i-disco/src/stm32_ili93414ws.c * * SPDX-License-Identifier: Apache-2.0 * @@ -57,7 +57,7 @@ #define ILI93414WS_SPI_DEVICE 5 -/* spi frequency based on arch/arm/src/stm32/stm32_spi.c */ +/* spi frequency based on arch/arm/src/common/stm32/stm32_spi.h */ #ifndef CONFIG_STM32F429I_DISCO_ILI9341_SPIFREQUENCY # define CONFIG_STM32F429I_DISCO_ILI9341_SPIFREQUENCY 20000000 @@ -209,7 +209,7 @@ struct ili93414ws_lcd_s g_lcddev; * * Description: * Clear and set bits in the CR register (based on - * arch/arm/src/stm32/stm32_spi.c). + * arch/arm/src/common/stm32/stm32_spi.h). * * Input Parameters: * reg - register to set @@ -951,14 +951,14 @@ static void stm32_ili93414ws_deselect(struct ili9341_lcd_s *lcd) /* Restore cr1 and cr2 register to be sure they will be usable * by default spi interface structure. (This is an important workaround as * long as half duplex mode is not supported by the spi interface in - * arch/arm/src/stm32/stm32_spi.c). + * arch/arm/src/common/stm32/stm32_spi.h). */ putreg16(priv->cr2, ILI93414WS_SPI_CR2); putreg16(priv->cr1, ILI93414WS_SPI_CR1); /* Enable spi device is default for initialized spi ports (see - * arch/arm/src/stm32/stm32_spi.c). + * arch/arm/src/common/stm32/stm32_spi.h). */ stm32_ili93414ws_spienable(); diff --git a/boards/arm/stm32f4/stm32f429i-disco/src/stm32_lcd.c b/boards/arm/stm32f4/stm32f429i-disco/src/stm32_lcd.c new file mode 100644 index 0000000000000..28e8c772a62e5 --- /dev/null +++ b/boards/arm/stm32f4/stm32f429i-disco/src/stm32_lcd.c @@ -0,0 +1,576 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f429i-disco/src/stm32_lcd.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include +#include +#include + +#include + +#include "arm_internal.h" +#include "stm32f429i-disco.h" +#include "stm32_ltdc.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifdef CONFIG_STM32F429I_DISCO_ILI9341_LCDDEVICE +# define ILI9341_LCD_DEVICE CONFIG_STM32F429I_DISCO_ILI9341_LCDDEVICE +#else +# define ILI9341_LCD_DEVICE 0 +#endif + +#ifdef CONFIG_STM32F429I_DISCO_ILI9341_FBIFACE + +/* Display settings */ + +/* Pixel Format Set (COLMOD) + * + * Note! RGB interface settings (DPI) is unimportant for the MCU interface + * mode but set the register to the defined state equal to the MCU interface + * pixel format. + * + * 16 Bit MCU: 01100101 / h65 + * + * DPI: 6 (RGB18-666 RGB interface) + * DBI: 5 (RGB16-565 MCU interface, not used set to default) + */ + +#define STM32_ILI9341_PIXSET_PARAM (ILI9341_PIXEL_FORMAT_SET_DPI(6) | \ + ILI9341_PIXEL_FORMAT_SET_DBI(5)) + +/* DE Mode RCM = 2, Sync Mode RCM = 3 + * Interface Mode Control + * + * EPL: 0 High enable for RGB interface + * DPL: 1 data fetched at the falling time + * HSPL: 0 Low level sync clock + * VSPL: 0 Low level sync clock + * RCM: 2 (DE Mode) + * ByPass_Mode: 1 (Memory) + */ + +#define STM32_ILI9341_IFMODE_PARAM (ILI9341_INTERFACE_CONTROL_DPL | \ + ILI9341_INTERFACE_CONTROL_RCM(2) | \ + ILI9341_INTERFACE_CONTROL_BPASS) + +/* Interface control (IFCTL) + * + * Parameter 1: 0x0001 + * MY_EOR: 0 + * MX_EOR: 0 + * MV_EOR: 0 + * BGR_EOR: 0 + * WEMODE: 1 Reset column and page if data transfer exceeds + */ + +#define STM32_ILI9341_IFCTL_PARAM1 (ILI9341_INTERFACE_CONTROL_WEMODE) + +/* Parameter 2: 0x0000 + * + * EPF: 0 65k color format for RGB interface + * MDT: 0 Display data transfer mode + * + */ +#define STM32_ILI9341_IFCTL_PARAM2 (ILI9341_INTERFACE_CONTROL_MDT(0) | \ + ILI9341_INTERFACE_CONTROL_EPF(0)) + +/* Parameter 3: 0x0000/0x0020 + * + * ENDIAN: 0 Big endian + * DM: 1 RGB Interface Mode + * RM: 1 RGB interface + * RIM: 0 18-bit 1 transfer/pixel RGB interface mode + * + */ +#define STM32_ILI9341_IFCTL_PARAM3 (ILI9341_INTERFACE_CONTROL_RM | \ + ILI9341_INTERFACE_CONTROL_DM(1)) + +/* Memory access control (MADCTL) */ + +/* Landscape: 00100000 / 00101000 / h28 + * + * MY: 0 + * MX: 0 + * MV: 1 + * ML: 0 + * BGR: 0/1 Depending on endian mode of the mcu? + * MH: 0 + */ + +#define ILI9341_MADCTL_LANDSCAPE_MY 0 +#define ILI9341_MADCTL_LANDSCAPE_MX 0 +#define ILI9341_MADCTL_LANDSCAPE_MV ILI9341_MEMORY_ACCESS_CONTROL_MV +#define ILI9341_MADCTL_LANDSCAPE_ML 0 +#ifdef CONFIG_ENDIAN_BIG +# define ILI9341_MADCTL_LANDSCAPE_BGR 0 +#else +# define ILI9341_MADCTL_LANDSCAPE_BGR ILI9341_MEMORY_ACCESS_CONTROL_BGR +#endif +#define ILI9341_MADCTL_LANDSCAPE_MH 0 + +#define ILI9341_MADCTL_LANDSCAPE_PARAM1 (ILI9341_MADCTL_LANDSCAPE_MY | \ + ILI9341_MADCTL_LANDSCAPE_MX | \ + ILI9341_MADCTL_LANDSCAPE_MV | \ + ILI9341_MADCTL_LANDSCAPE_ML | \ + ILI9341_MADCTL_LANDSCAPE_BGR | \ + ILI9341_MADCTL_LANDSCAPE_MH) + +/* Portrait: 00000000 / 00001000 / h08 + * + * MY: 0 + * MX: 0 + * MV: 0 + * ML: 0 + * BGR: 0/1 Depending on endian mode of the mcu? + * MH: 0 + */ + +#define ILI9341_MADCTL_PORTRAIT_MY 0 +#define ILI9341_MADCTL_PORTRAIT_MX ILI9341_MEMORY_ACCESS_CONTROL_MX +#define ILI9341_MADCTL_PORTRAIT_MV 0 +#define ILI9341_MADCTL_PORTRAIT_ML 0 +#ifdef CONFIG_ENDIAN_BIG +# define ILI9341_MADCTL_PORTRAIT_BGR 0 +#else +# define ILI9341_MADCTL_PORTRAIT_BGR ILI9341_MEMORY_ACCESS_CONTROL_BGR +#endif +#define ILI9341_MADCTL_PORTRAIT_MH 0 + +#define ILI9341_MADCTL_PORTRAIT_PARAM1 (ILI9341_MADCTL_PORTRAIT_MY | \ + ILI9341_MADCTL_PORTRAIT_MX | \ + ILI9341_MADCTL_PORTRAIT_MV | \ + ILI9341_MADCTL_PORTRAIT_ML | \ + ILI9341_MADCTL_PORTRAIT_BGR | \ + ILI9341_MADCTL_PORTRAIT_MH) + +/* RLandscape: 01100000 / 01101000 / h68 + * + * MY: 0 + * MX: 1 + * MV: 1 + * ML: 0 + * BGR: 0/1 Depending on endian mode of the mcu? + * MH: 0 + */ + +#define ILI9341_MADCTL_RLANDSCAPE_MY 0 +#define ILI9341_MADCTL_RLANDSCAPE_MX ILI9341_MEMORY_ACCESS_CONTROL_MX +#define ILI9341_MADCTL_RLANDSCAPE_MV ILI9341_MEMORY_ACCESS_CONTROL_MV +#define ILI9341_MADCTL_RLANDSCAPE_ML 0 +#ifdef CONFIG_ENDIAN_BIG +# define ILI9341_MADCTL_RLANDSCAPE_BGR 0 +#else +# define ILI9341_MADCTL_RLANDSCAPE_BGR ILI9341_MEMORY_ACCESS_CONTROL_BGR +#endif +#define ILI9341_MADCTL_RLANDSCAPE_MH 0 + +#define ILI9341_MADCTL_RLANDSCAPE_PARAM1 \ + (ILI9341_MADCTL_RLANDSCAPE_MY | \ + ILI9341_MADCTL_RLANDSCAPE_MX | \ + ILI9341_MADCTL_RLANDSCAPE_MV | \ + ILI9341_MADCTL_RLANDSCAPE_ML | \ + ILI9341_MADCTL_RLANDSCAPE_BGR | \ + ILI9341_MADCTL_RLANDSCAPE_MH) + +/* RPortrait: 11000000 / 11001000 / hc8 + * + * MY: 1 + * MX: 1 + * MV: 0 + * ML: 0 + * BGR: 0/1 Depending on endian mode of the mcu? + * MH: 0 + * + */ + +#define ILI9341_MADCTL_RPORTRAIT_MY ILI9341_MEMORY_ACCESS_CONTROL_MY +#define ILI9341_MADCTL_RPORTRAIT_MX 0 +#define ILI9341_MADCTL_RPORTRAIT_MV 0 +#define ILI9341_MADCTL_RPORTRAIT_ML 0 +#ifdef CONFIG_ENDIAN_BIG +# define ILI9341_MADCTL_RPORTRAIT_BGR 0 +#else +# define ILI9341_MADCTL_RPORTRAIT_BGR ILI9341_MEMORY_ACCESS_CONTROL_BGR +#endif +#define ILI9341_MADCTL_RPORTRAIT_MH 0 + +#define ILI9341_MADCTL_RPORTRAIT_PARAM1 (ILI9341_MADCTL_RPORTRAIT_MY | \ + ILI9341_MADCTL_RPORTRAIT_MX | \ + ILI9341_MADCTL_RPORTRAIT_MV | \ + ILI9341_MADCTL_RPORTRAIT_ML | \ + ILI9341_MADCTL_RPORTRAIT_BGR | \ + ILI9341_MADCTL_RPORTRAIT_MH) + +/* Set the display orientation */ + +#if defined(CONFIG_STM32F429I_DISCO_ILI9341_FBIFACE_LANDSCAPE) +# define STM32_ILI9341_MADCTL_PARAM ILI9341_MADCTL_LANDSCAPE_PARAM1 +# warning "ILI9341 doesn't support full landscape with RGB interface" +#elif defined(CONFIG_STM32F429I_DISCO_ILI9341_FBIFACE_PORTRAIT) +# define STM32_ILI9341_MADCTL_PARAM ILI9341_MADCTL_PORTRAIT_PARAM1 +#elif defined(CONFIG_STM32F429I_DISCO_ILI9341_FBIFACE_RLANDSCAPE) +# define STM32_ILI9341_MADCTL_PARAM ILI9341_MADCTL_RLANDSCAPE_PARAM1 +# warning "ILI9341 doesn't support full landscape with RGB interface" +#elif defined(CONFIG_STM32F429I_DISCO_ILI9341_FBIFACE_RPORTRAIT) +# define STM32_ILI9341_MADCTL_PARAM ILI9341_MADCTL_RPORTRAIT_PARAM1 +#else +# error "display orientation not defined" +#endif + +#define ILI9341_XRES BOARD_LTDC_WIDTH +#define ILI9341_YRES BOARD_LTDC_HEIGHT +#endif /* CONFIG_STM32F429I_DISCO_ILI9341_FBIFACE */ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#ifdef CONFIG_STM32F429I_DISCO_ILI9341_LCDIFACE +struct lcd_dev_s *g_lcd = NULL; +#endif + +#ifdef CONFIG_STM32F429I_DISCO_ILI9341_FBIFACE +struct ili9341_lcd_s *g_ltdc = NULL; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +#ifdef CONFIG_STM32F429I_DISCO_ILI9341_FBIFACE +/**************************************************************************** + * Name: stm32_ili9341_initialize + * + * Description: + * Initialize the ili9341 LCD controller to the RGB interface mode. + * + ****************************************************************************/ + +static int stm32_ili9341_initialize(void) +{ + struct ili9341_lcd_s *lcd = g_ltdc; + + lcd = stm32_ili93414ws_initialize(); + + if (lcd == NULL) + { + return ENODEV; + } + + /* Select spi device */ + + lcdinfo("Initialize ili9341 lcd driver\n"); + lcd->select(lcd); + +#ifdef CONFIG_DEBUG_LCD_INFO + /* Read display identification */ + + uint8_t param; + lcd->sendcmd(lcd, ILI9341_READ_ID1); + lcd->recvparam(lcd, ¶m); + lcdinfo("ili9341 LCD driver: LCD modules manufacturer ID: %d\n", param); + + lcd->sendcmd(lcd, ILI9341_READ_ID2); + lcd->recvparam(lcd, ¶m); + lcdinfo("ili9341 LCD driver: LCD modules driver version ID: %d\n", param); + + lcd->sendcmd(lcd, ILI9341_READ_ID3); + lcd->recvparam(lcd, ¶m); + lcdinfo("ili9341 LCD driver: LCD modules driver ID: %d\n", param); +#endif + + /* Reset the lcd display to the default state */ + + lcdinfo("ili9341 LCD driver: Software Reset\n"); + lcd->sendcmd(lcd, ILI9341_SOFTWARE_RESET); + up_mdelay(5); + + lcdinfo("ili9341 LCD driver: set Memory Access Control %08x\n", + STM32_ILI9341_MADCTL_PARAM); + lcd->sendcmd(lcd, ILI9341_MEMORY_ACCESS_CONTROL); + lcd->sendparam(lcd, STM32_ILI9341_MADCTL_PARAM); + + /* Pixel Format */ + + lcdinfo("ili9341 LCD driver: Set Pixel Format: %02x\n", + STM32_ILI9341_PIXSET_PARAM); + lcd->sendcmd(lcd, ILI9341_PIXEL_FORMAT_SET); + lcd->sendparam(lcd, STM32_ILI9341_PIXSET_PARAM); + + /* Select column */ + + lcdinfo("ili9341 LCD driver: Set Column Address\n"); + lcd->sendcmd(lcd, ILI9341_COLUMN_ADDRESS_SET); + lcd->sendparam(lcd, 0); + lcd->sendparam(lcd, 0); + lcd->sendparam(lcd, (ILI9341_XRES >> 8)); + lcd->sendparam(lcd, (ILI9341_XRES & 0xff)); + + /* Select page */ + + lcdinfo("ili9341 LCD driver: Set Page Address\n"); + lcd->sendcmd(lcd, ILI9341_PAGE_ADDRESS_SET); + lcd->sendparam(lcd, 0); + lcd->sendparam(lcd, 0); + lcd->sendparam(lcd, (ILI9341_YRES >> 8)); + lcd->sendparam(lcd, (ILI9341_YRES & 0xff)); + + /* RGB Interface signal control */ + + lcdinfo("ili9341 LCD driver: Set RGB Interface signal control: %02x\n", + STM32_ILI9341_IFMODE_PARAM); + lcd->sendcmd(lcd, ILI9341_RGB_SIGNAL_CONTROL); + lcd->sendparam(lcd, STM32_ILI9341_IFMODE_PARAM); + + /* Interface control */ + + lcdinfo("ili9341 LCD driver: Set Interface control: %d:%d:%d\n", + STM32_ILI9341_IFCTL_PARAM1, + STM32_ILI9341_IFCTL_PARAM2, + STM32_ILI9341_IFCTL_PARAM3); + + lcd->sendcmd(lcd, ILI9341_INTERFACE_CONTROL); + lcd->sendparam(lcd, STM32_ILI9341_IFCTL_PARAM1); + lcd->sendparam(lcd, STM32_ILI9341_IFCTL_PARAM2); + lcd->sendparam(lcd, STM32_ILI9341_IFCTL_PARAM3); + + /* Sleep out set to the end */ + + lcdinfo("ili9341 LCD driver: Sleep Out\n"); + lcd->sendcmd(lcd, ILI9341_SLEEP_OUT); + up_mdelay(5); /* 120? */ + + /* Display on */ + + lcdinfo("ili9341 LCD driver: Display On\n"); + lcd->sendcmd(lcd, ILI9341_DISPLAY_ON); + + /* Deselect spi device */ + + lcd->deselect(lcd); + + return OK; +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +#ifdef CONFIG_STM32F429I_DISCO_ILI9341_LCDIFACE +/**************************************************************************** + * Name: board_lcd_uninitialize + * + * Description: + * Uninitialize the LCD Device. + * + * Input Parameters: + * + * Returned Value: + * + ****************************************************************************/ + +void board_lcd_uninitialize(void) +{ + /* Set display off */ + + g_lcd->setpower(g_lcd, 0); + + g_lcd = NULL; +} + +/**************************************************************************** + * Name: board_lcd_getdev + * + * Description: + * Return a reference to the LCD object for the specified LCD Device. + * This allows support for multiple LCD devices. + * + * Input Parameters: + * lcddev - Number of the LDC Device. + * + * Returned Value: + * Reference to the LCD object if exist otherwise NULL + * + ****************************************************************************/ + +struct lcd_dev_s *board_lcd_getdev(int lcddev) +{ + if (lcddev == ILI9341_LCD_DEVICE) + { + return g_lcd; + } + + return NULL; +} + +/**************************************************************************** + * Name: board_lcd_initialize + * + * Description: + * Initialize the LCD video hardware. The initial state of the LCD is + * fully initialized, display memory cleared, and the LCD ready to use, but + * with the power setting at 0 (full off). + * + * Input Parameters: + * + * Returned Value: + * On success - Ok + * On error - Error Code + * + ****************************************************************************/ + +int board_lcd_initialize(void) +{ + /* check if always initialized */ + + if (!g_lcd) + { + /* Initialize the sub driver structure */ + + struct ili9341_lcd_s *dev = stm32_ili93414ws_initialize(); + + /* Initialize public lcd driver structure */ + + if (dev) + { + /* Get a reference to valid lcd driver structure to avoid repeated + * initialization of the LCD Device. Also enables uninitializing of + * the LCD Device. + */ + + g_lcd = ili9341_initialize(dev, ILI9341_LCD_DEVICE); + if (g_lcd) + { + return OK; + } + } + + return -ENODEV; + } + + return OK; +} +#endif /* CONFIG_STM32F429I_DISCO_ILI9341_LCDIFACE */ + +#ifdef CONFIG_STM32_LTDC +/**************************************************************************** + * Name: up_fbinitialize + * + * Description: + * Initialize the framebuffer video hardware associated with the display. + * + * Input Parameters: + * display - In the case of hardware with multiple displays, this + * specifies the display. Normally this is zero. + * + * Returned Value: + * Zero is returned on success; a negated errno value is returned on any + * failure. + * + ****************************************************************************/ + +int up_fbinitialize(int display) +{ + static bool initialized = false; + int ret = OK; + + if (!initialized) + { +#ifdef CONFIG_STM32F429I_DISCO_ILI9341_FBIFACE + /* Initialize the ili9341 LCD controller */ + + ret = stm32_ili9341_initialize(); + if (ret >= OK) + { + ret = stm32_ltdcinitialize(); + } + +#else + /* Custom LCD display with RGB interface */ + + ret = stm32_ltdcinitialize(); +#endif + + initialized = (ret >= OK); + } + + return ret; +} + +/**************************************************************************** + * Name: up_fbgetvplane + * + * Description: + * Return a a reference to the framebuffer object for the specified video + * plane of the specified plane. + * Many OSDs support multiple planes of video. + * + * Input Parameters: + * display - In the case of hardware with multiple displays, this + * specifies the display. Normally this is zero. + * vplane - Identifies the plane being queried. + * + * Returned Value: + * A non-NULL pointer to the frame buffer access structure is returned on + * success; NULL is returned on any failure. + * + ****************************************************************************/ + +struct fb_vtable_s *up_fbgetvplane(int display, int vplane) +{ + return stm32_ltdcgetvplane(vplane); +} + +/**************************************************************************** + * Name: up_fbuninitialize + * + * Description: + * Uninitialize the framebuffer support for the specified display. + * + * Input Parameters: + * display - In the case of hardware with multiple displays, this + * specifies the display. Normally this is zero. + * + * Returned Value: + * None + * + ****************************************************************************/ + +void up_fbuninitialize(int display) +{ + stm32_ltdcuninitialize(); +} +#endif /* CONFIG_STM32_LTDC */ diff --git a/boards/arm/stm32f4/stm32f429i-disco/src/stm32_pwm.c b/boards/arm/stm32f4/stm32f429i-disco/src/stm32_pwm.c new file mode 100644 index 0000000000000..318fe6a8521b5 --- /dev/null +++ b/boards/arm/stm32f4/stm32f429i-disco/src/stm32_pwm.c @@ -0,0 +1,116 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f429i-disco/src/stm32_pwm.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32_pwm.h" +#include "stm32f429i-disco.h" + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* PWM Timer */ + +#define STM32F429IDISCO_PWMTIMER 1 + +#define HAVE_PWM 1 + +#ifndef CONFIG_PWM +# undef HAVE_PWM +#endif + +#ifndef CONFIG_STM32_TIM1 +# undef HAVE_PWM +#endif + +#ifndef CONFIG_STM32_TIM1_PWM +# undef HAVE_PWM +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_pwm_setup + * + * Description: + * Initialize PWM and register the PWM device. + * + ****************************************************************************/ + +int stm32_pwm_setup(void) +{ +#ifdef HAVE_PWM + static bool initialized = false; + struct pwm_lowerhalf_s *pwm; + int ret; + + /* Have we already initialized? */ + + if (!initialized) + { + /* Call stm32_pwminitialize() to get an instance of the PWM interface */ + + pwm = stm32_pwminitialize(STM32F429IDISCO_PWMTIMER); + if (!pwm) + { + tmrerr("ERROR: Failed to get the STM32 PWM lower half\n"); + return -ENODEV; + } + + /* Register the PWM driver at "/dev/pwm0" */ + + ret = pwm_register("/dev/pwm0", pwm); + if (ret < 0) + { + tmrerr("ERROR: pwm_register failed: %d\n", ret); + return ret; + } + + /* Now we are initialized */ + + initialized = true; + } + + return OK; +#else + return -ENODEV; +#endif +} diff --git a/boards/arm/stm32f4/stm32f429i-disco/src/stm32_spi.c b/boards/arm/stm32f4/stm32f429i-disco/src/stm32_spi.c new file mode 100644 index 0000000000000..b45295dbf242e --- /dev/null +++ b/boards/arm/stm32f4/stm32f429i-disco/src/stm32_spi.c @@ -0,0 +1,299 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f429i-disco/src/stm32_spi.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include + +#include "arm_internal.h" +#include "chip.h" +#include "stm32.h" +#include "stm32f429i-disco.h" + +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || defined(CONFIG_STM32_SPI3) ||\ + defined(CONFIG_STM32_SPI4) || defined(CONFIG_STM32_SPI5) + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#ifdef CONFIG_STM32_SPI5 +struct spi_dev_s *g_spidev5 = NULL; +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_spidev_initialize + * + * Description: + * Called to configure SPI chip select GPIO pins for the stm32f429i-disco + * board. + * + ****************************************************************************/ + +void weak_function stm32_spidev_initialize(void) +{ +#ifdef CONFIG_STM32_SPI5 + stm32_configgpio(GPIO_CS_MEMS); /* MEMS chip select */ + stm32_configgpio(GPIO_CS_LCD); /* LCD chip select */ + stm32_configgpio(GPIO_LCD_DC); /* LCD Data/Command select */ + stm32_configgpio(GPIO_LCD_ENABLE); /* LCD enable select */ +#endif +#if defined(CONFIG_STM32_SPI4) && defined(CONFIG_MTD_SST25XX) + stm32_configgpio(GPIO_CS_SST25); /* SST25 FLASH chip select */ +#endif +} + +/**************************************************************************** + * Name: stm32_spi1/2/3/4/5select and stm32_spi1/2/3/4/5status + * + * Description: + * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status + * must be provided by board-specific logic. They are implementations of + * the select and status methods of the SPI interface defined by struct + * spi_ops_s (see include/nuttx/spi/spi.h). All other methods (including + * stm32_spibus_initialize()) are provided by common STM32 logic. + * To use this common SPI logic on your board: + * + * 1. Provide logic in stm32_boardinitialize() to configure SPI chip + * select pins. + * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() functions + * in your board-specific logic. These functions will perform chip + * selection and status operations using GPIOs in the way your board is + * configured. + * 3. Add a calls to stm32_spibus_initialize() in your low level + * application initialization logic + * 4. The handle returned by stm32_spibus_initialize() may then be used to + * bind the SPI driver to higher level logic (e.g., calling + * mmcsd_spislotinitialize(), for example, will bind the SPI driver to + * the SPI MMC/SD driver). + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_SPI1 +void stm32_spi1select(struct spi_dev_s *dev, + uint32_t devid, + bool selected) +{ + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); +} + +uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} +#endif + +#ifdef CONFIG_STM32_SPI2 +void stm32_spi2select(struct spi_dev_s *dev, + uint32_t devid, + bool selected) +{ + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); +} + +uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} +#endif + +#ifdef CONFIG_STM32_SPI3 +void stm32_spi3select(struct spi_dev_s *dev, + uint32_t devid, bool selected) +{ + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); +} + +uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} +#endif + +#ifdef CONFIG_STM32_SPI4 +void stm32_spi4select(struct spi_dev_s *dev, + uint32_t devid, bool selected) +{ +#if defined(CONFIG_MTD_SST25XX) + if (devid == SPIDEV_FLASH(0)) + { + stm32_gpiowrite(GPIO_CS_SST25, !selected); + } +#endif +} + +uint8_t stm32_spi4status(struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} +#endif + +#ifdef CONFIG_STM32_SPI5 +void stm32_spi5select(struct spi_dev_s *dev, + uint32_t devid, bool selected) +{ + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); + +#if defined(CONFIG_STM32F429I_DISCO_ILI9341) + if (devid == SPIDEV_DISPLAY(0)) + { + stm32_gpiowrite(GPIO_CS_LCD, !selected); + } + else +#endif + + { + stm32_gpiowrite(GPIO_CS_MEMS, !selected); + } +} + +uint8_t stm32_spi5status(struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} +#endif + +/**************************************************************************** + * Name: stm32_spi1cmddata + * + * Description: + * Set or clear the SH1101A A0 or SD1306 D/C n bit to select data (true) + * or command (false). This function must be provided by platform-specific + * logic. This is an implementation of the cmddata method of the SPI + * interface defined by struct spi_ops_s (see include/nuttx/spi/spi.h). + * + * Input Parameters: + * + * spi - SPI device that controls the bus the device that requires the CMD/ + * DATA selection. + * devid - If there are multiple devices on the bus, this selects which one + * to select cmd or data. NOTE: This design restricts, for example, + * one one SPI display per SPI bus. + * cmd - true: select command; false: select data + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_SPI_CMDDATA +#ifdef CONFIG_STM32_SPI1 +int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) +{ + return -ENODEV; +} +#endif + +#ifdef CONFIG_STM32_SPI2 +int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) +{ + return -ENODEV; +} +#endif + +#ifdef CONFIG_STM32_SPI3 +int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) +{ + return -ENODEV; +} +#endif + +#ifdef CONFIG_STM32_SPI4 +int stm32_spi4cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) +{ + return -ENODEV; +} +#endif + +#ifdef CONFIG_STM32_SPI5 +int stm32_spi5cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) +{ +#if defined(CONFIG_STM32F429I_DISCO_ILI9341) + if (devid == SPIDEV_DISPLAY(0)) + { + /* This is the Data/Command control pad which determines whether the + * data bits are data or a command. + */ + + stm32_gpiowrite(GPIO_LCD_DC, !cmd); + + return OK; + } +#endif + + return -ENODEV; +} +#endif + +#endif /* CONFIG_SPI_CMDDATA */ + +/**************************************************************************** + * Name: stm32_spi5initialize + * + * Description: + * Initialize the selected SPI port. + * As long as the method stm32_spibus_initialize recognized the initialized + * state of the spi device by the spi enable flag of the cr1 register, it + * isn't safe to disable the spi device outside of the nuttx spi interface + * structure. But this has to be done as long as the nuttx spi interface + * doesn't support bidirectional data transfer for multiple devices share + * one spi bus. This wrapper does nothing else than store the initialized + * state of the spi device after the first initializing and should be used + * by each driver who shares the spi5 bus. + * + * Input Parameters: + * + * Returned Value: + * Valid SPI device structure reference on success; a NULL on failure + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_SPI5 +struct spi_dev_s *stm32_spi5initialize(void) +{ + if (!g_spidev5) + { + g_spidev5 = stm32_spibus_initialize(5); + } + + return g_spidev5; +} +#endif +#endif /* CONFIG_STM32_SPI1 || ... CONFIG_STM32_SPI5 */ diff --git a/boards/arm/stm32f4/stm32f429i-disco/src/stm32_stmpe811.c b/boards/arm/stm32f4/stm32f429i-disco/src/stm32_stmpe811.c new file mode 100644 index 0000000000000..e6733b6f56921 --- /dev/null +++ b/boards/arm/stm32f4/stm32f429i-disco/src/stm32_stmpe811.c @@ -0,0 +1,337 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f429i-disco/src/stm32_stmpe811.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include + +#include "stm32.h" +#include "stm32f429i-disco.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +#ifdef CONFIG_INPUT_STMPE811 +#ifndef CONFIG_INPUT +# error "STMPE811 support requires CONFIG_INPUT" +#endif + +#ifndef CONFIG_STM32_I2C3 +# error "STMPE811 support requires CONFIG_STM32_I2C3" +#endif + +#ifndef CONFIG_STMPE811_I2C +# error "Only the STMPE811 I2C interface is supported" +#endif + +#ifdef CONFIG_STMPE811_SPI +# error "Only the STMPE811 SPI interface is supported" +#endif + +#ifndef CONFIG_STMPE811_FREQUENCY +# define CONFIG_STMPE811_FREQUENCY 100000 +#endif + +#ifndef CONFIG_STMPE811_I2CDEV +# define CONFIG_STMPE811_I2CDEV 3 +#endif + +#if CONFIG_STMPE811_I2CDEV != 3 +# error "CONFIG_STMPE811_I2CDEV must be three" +#endif + +#ifndef CONFIG_STMPE811_DEVMINOR +# define CONFIG_STMPE811_DEVMINOR 0 +#endif + +/* Board definitions ********************************************************/ + +/* The STM3240G-EVAL has two STMPE811QTR I/O expanders on board both + * connected to the STM32 via I2C1. They share a common interrupt line: PI2. + * + * STMPE811 U24, I2C address 0x41 (7-bit) + * ------ ---- ---------------- -------------------------------------------- + * STPE11 PIN BOARD SIGNAL BOARD CONNECTION + * ------ ---- ---------------- -------------------------------------------- + * Y- TouchScreen_Y- LCD Connector XL + * X- TouchScreen_X- LCD Connector XR + * Y+ TouchScreen_Y+ LCD Connector XD + * X+ TouchScreen_X+ LCD Connector XU + * IN3 EXP_IO9 + * IN2 EXP_IO10 + * IN1 EXP_IO11 + * IN0 EXP_IO12 + * + * STMPE811 U29, I2C address 0x44 (7-bit) + * ------ ---- ---------------- -------------------------------------------- + * STPE11 PIN BOARD SIGNAL BOARD CONNECTION + * ------ ---- ---------------- -------------------------------------------- + * Y- EXP_IO1 + * X- EXP_IO2 + * Y+ EXP_IO3 + * X+ EXP_IO4 + * IN3 EXP_IO5 + * IN2 EXP_IO6 + * IN1 EXP_IO7 + * IN0 EXP_IO8 + */ + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +struct stm32_stmpe811config_s +{ + /* Configuration structure as seen by the STMPE811 driver */ + + struct stmpe811_config_s config; + + /* Additional private definitions only known to this driver */ + + STMPE811_HANDLE handle; /* The STMPE811 driver handle */ + xcpt_t handler; /* The STMPE811 interrupt handler */ + void *arg; /* Interrupt handler argument */ +}; + +/**************************************************************************** + * Static Function Prototypes + ****************************************************************************/ + +/* IRQ/GPIO access callbacks. These operations all hidden behind callbacks + * to isolate the STMPE811 driver from differences in GPIO + * interrupt handling by varying boards and MCUs.* so that contact and loss- + * of-contact events can be detected. + * + * attach - Attach the STMPE811 interrupt handler to the GPIO interrupt + * enable - Enable or disable the GPIO interrupt + * clear - Acknowledge/clear any pending GPIO interrupt + */ + +static int stmpe811_attach(struct stmpe811_config_s *state, xcpt_t isr, + void *arg); +static void stmpe811_enable(struct stmpe811_config_s *state, + bool enable); +static void stmpe811_clear(struct stmpe811_config_s *state); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* A reference to a structure of this type must be passed to the STMPE811 + * driver. This structure provides information about the configuration + * of the STMPE811 and provides some board-specific hooks. + * + * Memory for this structure is provided by the caller. It is not copied + * by the driver and is presumed to persist while the driver is active. The + * memory must be writable because, under certain circumstances, the driver + * may modify frequency or X plate resistance values. + */ + +#ifndef CONFIG_STMPE811_TSC_DISABLE +static struct stm32_stmpe811config_s g_stmpe811config = +{ + .config = + { +#ifdef CONFIG_STMPE811_I2C + .address = STMPE811_ADDR1, +#endif + .frequency = CONFIG_STMPE811_FREQUENCY, + +#ifdef CONFIG_STMPE811_MULTIPLE + .irq = STM32_IRQ_EXTI2, +#endif + .ctrl1 = (ADC_CTRL1_SAMPLE_TIME_80 | ADC_CTRL1_MOD_12B), + .ctrl2 = ADC_CTRL2_ADC_FREQ_3p25, + + .attach = stmpe811_attach, + .enable = stmpe811_enable, + .clear = stmpe811_clear, + }, + .handler = NULL, + .arg = NULL, +}; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/* IRQ/GPIO access callbacks. These operations all hidden behind + * callbacks to isolate the STMPE811 driver from differences in GPIO + * interrupt handling by varying boards and MCUs. + * + * attach - Attach the STMPE811 interrupt handler to the GPIO interrupt + * enable - Enable or disable the GPIO interrupt + * clear - Acknowledge/clear any pending GPIO interrupt + */ + +static int stmpe811_attach(struct stmpe811_config_s *state, xcpt_t isr, + void *arg) +{ + struct stm32_stmpe811config_s *priv = + (struct stm32_stmpe811config_s *)state; + + iinfo("Saving handler %p\n", isr); + DEBUGASSERT(priv); + + /* Just save the handler. We will use it when EXTI interruptsare enabled */ + + priv->handler = isr; + priv->arg = arg; + return OK; +} + +static void stmpe811_enable(struct stmpe811_config_s *state, bool enable) +{ + struct stm32_stmpe811config_s *priv = + (struct stm32_stmpe811config_s *)state; + irqstate_t flags; + + /* Attach and enable, or detach and disable. Enabling and disabling GPIO + * interrupts is a multi-step process so the safest thing is to keep + * interrupts disabled during the reconfiguration. + */ + + flags = enter_critical_section(); + if (enable) + { + /* Configure the EXTI interrupt using the SAVED handler */ + + stm32_gpiosetevent(GPIO_IO_EXPANDER, true, true, true, + priv->handler, priv->arg); + } + else + { + /* Configure the EXTI interrupt with a NULL handler to disable it */ + + stm32_gpiosetevent(GPIO_IO_EXPANDER, false, false, false, + NULL, NULL); + } + + leave_critical_section(flags); +} + +static void stmpe811_clear(struct stmpe811_config_s *state) +{ + /* Does nothing */ +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_tsc_setup + * + * Description: + * This function is called by board-bringup logic to configure the + * touchscreen device. This function will register the driver as + * /dev/inputN where N is the minor device number. + * + * Input Parameters: + * minor - The input device minor number + * + * Returned Value: + * Zero is returned on success. Otherwise, a negated errno value is + * returned to indicate the nature of the failure. + * + ****************************************************************************/ + +int stm32_tsc_setup(int minor) +{ +#ifndef CONFIG_STMPE811_TSC_DISABLE + struct i2c_master_s *dev; + int ret; + + iinfo("minor %d\n", minor); + DEBUGASSERT(minor == 0); + + /* Check if we are already initialized */ + + if (!g_stmpe811config.handle) + { + iinfo("Initializing\n"); + + /* Configure the STMPE811 interrupt pin as an input */ + + stm32_configgpio(GPIO_IO_EXPANDER); + + /* Get an instance of the I2C interface */ + + dev = stm32_i2cbus_initialize(CONFIG_STMPE811_I2CDEV); + if (!dev) + { + ierr("ERROR: Failed to initialize I2C bus %d\n", + CONFIG_STMPE811_I2CDEV); + return -ENODEV; + } + + /* Instantiate the STMPE811 driver */ + + g_stmpe811config.handle = + stmpe811_instantiate(dev, + (struct stmpe811_config_s *)&g_stmpe811config); + if (!g_stmpe811config.handle) + { + ierr("ERROR: Failed to instantiate the STMPE811 driver\n"); + return -ENODEV; + } + + /* Initialize and register the I2C touchscreen device */ + + ret = stmpe811_register(g_stmpe811config.handle, + CONFIG_STMPE811_DEVMINOR); + if (ret < 0) + { + ierr("ERROR: Failed to register STMPE driver: %d\n", ret); + + /* stm32_i2cbus_uninitialize(dev); */ + + return -ENODEV; + } + } + + return OK; +#else + return -ENOSYS; +#endif +} + +#endif /* CONFIG_INPUT_STMPE811 */ diff --git a/boards/arm/stm32f4/stm32f429i-disco/src/stm32_usb.c b/boards/arm/stm32f4/stm32f429i-disco/src/stm32_usb.c new file mode 100644 index 0000000000000..64d1ec5758e37 --- /dev/null +++ b/boards/arm/stm32f4/stm32f429i-disco/src/stm32_usb.c @@ -0,0 +1,310 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f429i-disco/src/stm32_usb.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include "arm_internal.h" +#include "stm32.h" +#include "stm32_otghs.h" +#include "stm32f429i-disco.h" + +#ifdef CONFIG_STM32_OTGHS + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#if defined(CONFIG_USBDEV) || defined(CONFIG_USBHOST) +# define HAVE_USB 1 +#else +# warning "CONFIG_STM32_OTGHS is enabled but neither CONFIG_USBDEV nor CONFIG_USBHOST" +# undef HAVE_USB +#endif + +#ifndef CONFIG_STM32F429IDISCO_USBHOST_PRIO +# define CONFIG_STM32F429IDISCO_USBHOST_PRIO 100 +#endif + +#ifndef CONFIG_STM32F429IDISCO_USBHOST_STACKSIZE +# define CONFIG_STM32F429IDISCO_USBHOST_STACKSIZE 1024 +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +static struct usbhost_connection_s *g_usbconn; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: usbhost_waiter + * + * Description: + * Wait for USB devices to be connected. + * + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +static int usbhost_waiter(int argc, char *argv[]) +{ + struct usbhost_hubport_s *hport; + + uinfo("Running\n"); + for (; ; ) + { + /* Wait for the device to change state */ + + DEBUGVERIFY(CONN_WAIT(g_usbconn, &hport)); + uinfo("%s\n", hport->connected ? "connected" : "disconnected"); + + /* Did we just become connected? */ + + if (hport->connected) + { + /* Yes.. enumerate the newly connected device */ + + CONN_ENUMERATE(g_usbconn, hport); + } + } + + /* Keep the compiler from complaining */ + + return 0; +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_usbinitialize + * + * Description: + * Called from stm32_usbinitialize very early in initialization to setup + * USB-related GPIO pins for the STM32F4Discovery board. + * + ****************************************************************************/ + +void stm32_usbinitialize(void) +{ + /* The OTG FS has an internal soft pull-up. + * No GPIO configuration is required + */ + + /* Configure the OTG FS VBUS sensing GPIO, + * Power On, and Overcurrent GPIOs + */ + +#ifdef CONFIG_STM32_OTGHS + stm32_configgpio(GPIO_OTGHS_VBUS); + stm32_configgpio(GPIO_OTGHS_PWRON); + stm32_configgpio(GPIO_OTGHS_OVER); +#endif +} + +/**************************************************************************** + * Name: stm32_usbhost_initialize + * + * Description: + * Called at application startup time to initialize the USB host + * functionality. + * This function will start a thread that will monitor for device + * connection/disconnection events. + * + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +int stm32_usbhost_initialize(void) +{ + int ret; + + /* First, register all of the class drivers needed to support the drivers + * that we care about: + */ + + uinfo("Register class drivers\n"); + +#ifdef CONFIG_USBHOST_HUB + /* Initialize USB hub class support */ + + ret = usbhost_hub_initialize(); + if (ret < 0) + { + uerr("ERROR: usbhost_hub_initialize failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_USBHOST_MSC + /* Register the USB mass storage class class */ + + ret = usbhost_msc_initialize(); + if (ret != OK) + { + uerr("ERROR: Failed to register the mass storage class: %d\n", ret); + } +#endif + +#ifdef CONFIG_USBHOST_CDCACM + /* Register the CDC/ACM serial class */ + + ret = usbhost_cdcacm_initialize(); + if (ret != OK) + { + uerr("ERROR: Failed to register the CDC/ACM serial class: %d\n", ret); + } +#endif + + /* Then get an instance of the USB host interface */ + + uinfo("Initialize USB host\n"); + g_usbconn = stm32_otghshost_initialize(0); + if (g_usbconn) + { + /* Start a thread to handle device connection. */ + + uinfo("Start usbhost_waiter\n"); + + ret = kthread_create("usbhost", CONFIG_STM32F429IDISCO_USBHOST_PRIO, + CONFIG_STM32F429IDISCO_USBHOST_STACKSIZE, + usbhost_waiter, NULL); + return ret < 0 ? -ENOEXEC : OK; + } + + return -ENODEV; +} +#endif + +/**************************************************************************** + * Name: stm32_usbhost_vbusdrive + * + * Description: + * Enable/disable driving of VBUS 5V output. This function must be + * provided be each platform that implements the STM32 OTG FS host + * interface + * + * "On-chip 5 V VBUS generation is not supported. For this reason, a + * charge pump or, if 5 V are available on the application board, a + * basic power switch, must be added externally to drive the 5 V VBUS + * line. The external charge pump can be driven by any GPIO output. + * When the application decides to power on VBUS using the chosen GPIO, + * it must also set the port power bit in the host port control and + * status register (PPWR bit in OTG_FS_HPRT). + * + * "The application uses this field to control power to this port, + * and the core clears this bit on an overcurrent condition." + * + * Input Parameters: + * iface - For future growth to handle multiple USB host interface. + * Should be zero. + * enable - true: enable VBUS power; false: disable VBUS power + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +void stm32_usbhost_vbusdrive(int iface, bool enable) +{ + DEBUGASSERT(iface == 0); + + if (enable) + { + /* Enable the Power Switch by driving the enable pin low */ + + stm32_gpiowrite(GPIO_OTGHS_PWRON, false); + } + else + { + /* Disable the Power Switch by driving the enable pin high */ + + stm32_gpiowrite(GPIO_OTGHS_PWRON, true); + } +} +#endif + +/**************************************************************************** + * Name: stm32_setup_overcurrent + * + * Description: + * Setup to receive an interrupt-level callback if an overcurrent + * condition is detected. + * + * Input Parameters: + * handler - New overcurrent interrupt handler + * arg - The argument provided for the interrupt handler + * + * Returned Value: + * Zero (OK) is returned on success. Otherwise, a negated errno value + * is returned to indicate the nature of the failure. + * + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +int stm32_setup_overcurrent(xcpt_t handler, void *arg) +{ + return stm32_gpiosetevent(GPIO_OTGHS_OVER, true, true, true, handler, arg); +} +#endif + +/**************************************************************************** + * Name: stm32_usbsuspend + * + * Description: + * Board logic must provide the stm32_usbsuspend logic if the USBDEV + * driver is used. This function is called whenever the USB enters or + * leaves suspend mode. This is an opportunity for the board logic to + * shutdown clocks, power, etc. while the USB is suspended. + * + ****************************************************************************/ + +#ifdef CONFIG_USBDEV +void stm32_usbsuspend(struct usbdev_s *dev, bool resume) +{ + uinfo("resume: %d\n", resume); +} +#endif + +#endif /* CONFIG_STM32_OTGHS */ diff --git a/boards/arm/stm32f4/stm32f429i-disco/src/stm32_userleds.c b/boards/arm/stm32f4/stm32f429i-disco/src/stm32_userleds.c new file mode 100644 index 0000000000000..9ba0c74b5a5ab --- /dev/null +++ b/boards/arm/stm32f4/stm32f429i-disco/src/stm32_userleds.c @@ -0,0 +1,211 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f429i-disco/src/stm32_userleds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32.h" +#include "stm32f429i-disco.h" + +#ifndef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* This array maps an LED number to GPIO pin configuration */ + +static uint32_t g_ledcfg[BOARD_NLEDS] = +{ + GPIO_LED1, GPIO_LED2 +}; + +/**************************************************************************** + * Private Function Protototypes + ****************************************************************************/ + +/* LED Power Management */ + +#ifdef CONFIG_PM +static void led_pm_notify(struct pm_callback_s *cb, int domain, + enum pm_state_e pmstate); +static int led_pm_prepare(struct pm_callback_s *cb, int domain, + enum pm_state_e pmstate); +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#ifdef CONFIG_PM +static struct pm_callback_s g_ledscb = +{ + .notify = led_pm_notify, + .prepare = led_pm_prepare, +}; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: led_pm_notify + * + * Description: + * Notify the driver of new power state. This callback is called after + * all drivers have had the opportunity to prepare for the new power state. + * + ****************************************************************************/ + +#ifdef CONFIG_PM +static void led_pm_notify(struct pm_callback_s *cb, int domain, + enum pm_state_e pmstate) +{ + switch (pmstate) + { + case PM_NORMAL: + { + /* Restore normal LEDs operation */ + } + break; + + case PM_IDLE: + { + /* Entering IDLE mode - Turn leds off */ + } + break; + + case PM_STANDBY: + { + /* Entering STANDBY mode - Logic for PM_STANDBY goes here */ + } + break; + + case PM_SLEEP: + { + /* Entering SLEEP mode - Logic for PM_SLEEP goes here */ + } + break; + + default: + { + /* Should not get here */ + } + break; + } +} +#endif + +/**************************************************************************** + * Name: led_pm_prepare + * + * Description: + * Request the driver to prepare for a new power state. This is a warning + * that the system is about to enter into a new power state. The driver + * should begin whatever operations that may be required to enter power + * state. The driver may abort the state change mode by returning a + * non-zero value from the callback function. + * + ****************************************************************************/ + +#ifdef CONFIG_PM +static int led_pm_prepare(struct pm_callback_s *cb, int domain, + enum pm_state_e pmstate) +{ + /* No preparation to change power modes is required by the LEDs driver. + * We always accept the state change by returning OK. + */ + + return OK; +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_userled_initialize + ****************************************************************************/ + +uint32_t board_userled_initialize(void) +{ + /* Configure LED1-4 GPIOs for output */ + + stm32_configgpio(GPIO_LED1); + stm32_configgpio(GPIO_LED2); + return BOARD_NLEDS; +} + +/**************************************************************************** + * Name: board_userled + ****************************************************************************/ + +void board_userled(int led, bool ledon) +{ + if ((unsigned)led < BOARD_NLEDS) + { + stm32_gpiowrite(g_ledcfg[led], ledon); + } +} + +/**************************************************************************** + * Name: board_userled_all + ****************************************************************************/ + +void board_userled_all(uint32_t ledset) +{ + stm32_gpiowrite(GPIO_LED1, (ledset & BOARD_LED1_BIT) == 0); + stm32_gpiowrite(GPIO_LED2, (ledset & BOARD_LED2_BIT) == 0); +} + +/**************************************************************************** + * Name: stm32_ledpminitialize + ****************************************************************************/ + +#ifdef CONFIG_PM +void stm32_ledpminitialize(void) +{ + /* Register to receive power management callbacks */ + + int ret = pm_register(&g_ledscb); + if (ret != OK) + { + board_autoled_on(LED_ASSERTION); + } +} +#endif /* CONFIG_PM */ + +#endif /* !CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/stm32f429i-disco/src/stm32f429i-disco.h b/boards/arm/stm32f4/stm32f429i-disco/src/stm32f429i-disco.h similarity index 99% rename from boards/arm/stm32/stm32f429i-disco/src/stm32f429i-disco.h rename to boards/arm/stm32f4/stm32f429i-disco/src/stm32f429i-disco.h index 121f0380a7355..a9f7d7a5d6af3 100644 --- a/boards/arm/stm32/stm32f429i-disco/src/stm32f429i-disco.h +++ b/boards/arm/stm32f4/stm32f429i-disco/src/stm32f429i-disco.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f429i-disco/src/stm32f429i-disco.h + * boards/arm/stm32f4/stm32f429i-disco/src/stm32f429i-disco.h * * SPDX-License-Identifier: Apache-2.0 * @@ -35,7 +35,7 @@ #include #endif -#include +#include #include "stm32_gpio.h" diff --git a/boards/arm/stm32/stm32f429i-disco/tools/fbcalc.sh b/boards/arm/stm32f4/stm32f429i-disco/tools/fbcalc.sh similarity index 98% rename from boards/arm/stm32/stm32f429i-disco/tools/fbcalc.sh rename to boards/arm/stm32f4/stm32f429i-disco/tools/fbcalc.sh index d871b35a27d0f..b2df4b4f3b069 100755 --- a/boards/arm/stm32/stm32f429i-disco/tools/fbcalc.sh +++ b/boards/arm/stm32f4/stm32f429i-disco/tools/fbcalc.sh @@ -1,6 +1,6 @@ #!/usr/bin/env bash ############################################################################# - # boards/arm/stm32/stm32f429-disco/tools/fbcalc.sh + # boards/arm/stm32f4/stm32f429i-disco/tools/fbcalc.sh # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32f4/stm32f4discovery/CMakeLists.txt b/boards/arm/stm32f4/stm32f4discovery/CMakeLists.txt new file mode 100644 index 0000000000000..3aee03875c31f --- /dev/null +++ b/boards/arm/stm32f4/stm32f4discovery/CMakeLists.txt @@ -0,0 +1,30 @@ +# ############################################################################## +# boards/arm/stm32f4/stm32f4discovery/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) + +if(NOT CONFIG_BUILD_FLAT) + add_subdirectory(kernel) + set_property( + GLOBAL PROPERTY LD_SCRIPT_USER ${CMAKE_CURRENT_LIST_DIR}/scripts/memory.ld + ${CMAKE_CURRENT_LIST_DIR}/scripts/user-space.ld) +endif() diff --git a/boards/arm/stm32f4/stm32f4discovery/Kconfig b/boards/arm/stm32f4/stm32f4discovery/Kconfig new file mode 100644 index 0000000000000..8dfe3c0fc7940 --- /dev/null +++ b/boards/arm/stm32f4/stm32f4discovery/Kconfig @@ -0,0 +1,120 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# + +if ARCH_BOARD_STM32F4_DISCOVERY + +config STM32F4DISBB + bool "STM32F4DIS-BB base board" + default n + ---help--- + Select if you are using the STM32F4DIS-BB base board with the + STM32F4Discovery. + +config STM32F4DISCO_USBHOST_STACKSIZE + int "USB host waiter stack size" + default 1024 + depends on USBHOST + +config STM32F4DISCO_USBHOST_PRIO + int "USB host waiter task priority" + default 100 + depends on USBHOST + +config STM32F4DISCO_QETIMER + int "Timer to use with QE encoder" + default 2 + depends on SENSORS_QENCODER + +config STM32F4DISCO_TIMER + int "Timer to use with timer driver" + default 4 + depends on TIMER + +config STM32F4DISCO_LIS3DSH + bool "Enable LIS3DSH driver for the IMU on STM32F4Discovery (rev. MB997C)" + default n + depends on SPI + depends on LIS3DSH + default n + select SENSORS_LIS3DSH + ---help--- + Select to create a LIS3DSH driver instance for the builtin accelerometer of + STM32F4Discovery. Provides /dev/acc0 device file. + Also see apps/examples/lis3dsh_reader. + The LIS3DSH is available on the STM32F4Discovery rev. MB997C (see the board manual). + +config PM_BUTTONS + bool "PM button support" + default n + depends on PM && ARCH_IRQBUTTONS + ---help--- + Enable PM button EXTI interrupts to support PM testing + +config PM_BUTTON_ACTIVITY + int "Button PM activity weight" + default 10 + depends on PM_BUTTONS + ---help--- + The activity weight to report to the power management subsystem when + a button is pressed. + +config PM_ALARM_SEC + int "PM_STANDBY delay (seconds)" + default 15 + depends on PM && RTC_ALARM + ---help--- + Number of seconds to wait in PM_STANDBY before going to PM_STANDBY + mode. + +config PM_ALARM_NSEC + int "PM_STANDBY delay (nanoseconds)" + default 0 + depends on PM && RTC_ALARM + ---help--- + Number of additional nanoseconds to wait in PM_STANDBY before going + to PM_STANDBY mode. + +config PM_SLEEP_WAKEUP + bool "PM_SLEEP wake-up alarm" + default n + depends on PM && RTC_ALARM + ---help--- + Wake-up of PM_SLEEP mode after a delay and resume normal operation. + +config PM_SLEEP_WAKEUP_SEC + int "PM_SLEEP delay (seconds)" + default 10 + depends on PM && RTC_ALARM + ---help--- + Number of seconds to wait in PM_SLEEP before going to PM_STANDBY mode. + +config PM_SLEEP_WAKEUP_NSEC + int "PM_SLEEP delay (nanoseconds)" + default 0 + depends on PM && RTC_ALARM + ---help--- + Number of additional nanoseconds to wait in PM_SLEEP before going to + PM_STANDBY mode. + +if INPUT_KMATRIX_I2C + +config STM32_KMATRIX_I2C_BUS + int "I2C Bus Number" + default 1 + ---help--- + I2C bus number to use for the keyboard matrix GPIO expander. + Common values: 1 or 2 (depends on available I2C interfaces). + +config STM32_KMATRIX_I2C_ADDR + hex "I2C Slave Address of GPIO Expander" + default 0x20 + ---help--- + I2C slave address of the GPIO expander (PCF8574 or MCP23017). + PCF8574/MCP23017 default addresses (7-bit): + 0x20-0x27: varies with A0-A2 pins (default is 0x20) + +endif # INPUT_KMATRIX_I2C + +endif diff --git a/boards/arm/stm32f4/stm32f4discovery/configs/adb/defconfig b/boards/arm/stm32f4/stm32f4discovery/configs/adb/defconfig new file mode 100644 index 0000000000000..3edc516822576 --- /dev/null +++ b/boards/arm/stm32f4/stm32f4discovery/configs/adb/defconfig @@ -0,0 +1,74 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ADBD_FILE_SERVICE=y +CONFIG_ADBD_SHELL_SERVICE=y +CONFIG_ADBD_USB_SERVER=y +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f4discovery" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F407VG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL_RESET=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_DEV_URANDOM=y +CONFIG_ELF=y +CONFIG_EXAMPLES_HELLO=m +CONFIG_FAT_LFN=y +CONFIG_FS_FAT=y +CONFIG_FS_FATTIME=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=3072 +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_EXECFUNCS=y +CONFIG_LIBUV=y +CONFIG_LINE_MAX=128 +CONFIG_MMCSD=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_PSEUDOTERM=y +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_SCHED_CHILD_STATUS=y +CONFIG_SCHED_HAVE_PARENT=y +CONFIG_SCHED_LPWORK=y +CONFIG_SCHED_WAITPID=y +CONFIG_SENSORS=y +CONFIG_STACK_COLORATION=y +CONFIG_START_DAY=17 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2020 +CONFIG_STM32_DMA2=y +CONFIG_STM32_DMACAPABLE=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PWR=y +CONFIG_STM32_SPI2=y +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_ADBD=y +CONFIG_SYSTEM_NSH=y +CONFIG_TLS_TASK_NELEM=4 +CONFIG_USART2_SERIAL_CONSOLE=y +CONFIG_USBADB=y +CONFIG_USBDEV=y diff --git a/boards/arm/stm32f4/stm32f4discovery/configs/audio/defconfig b/boards/arm/stm32f4/stm32f4discovery/configs/audio/defconfig new file mode 100644 index 0000000000000..aec03f8df55f2 --- /dev/null +++ b/boards/arm/stm32f4/stm32f4discovery/configs/audio/defconfig @@ -0,0 +1,75 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f4discovery" +CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F407VG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_AUDIO=y +CONFIG_AUDIO_CS43L22=y +CONFIG_AUDIO_CUSTOM_DEV_PATH=y +CONFIG_AUDIO_EXCLUDE_TONE=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_DRIVERS_AUDIO=y +CONFIG_FAT_LCNAMES=y +CONFIG_FAT_LFN=y +CONFIG_FS_FAT=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_I2C=y +CONFIG_I2C_DRIVER=y +CONFIG_I2C_POLLED=y +CONFIG_I2C_RESET=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_MM_REGIONS=2 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_NXPLAYER_DEFAULT_MEDIADIR="/mnt/music" +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_STM32_DMA1=y +CONFIG_STM32_DMACAPABLE=y +CONFIG_STM32_I2C1=y +CONFIG_STM32_I2S3=y +CONFIG_STM32_I2S3_TX=y +CONFIG_STM32_I2S_MCK=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_OTGFS_SOFINTR=y +CONFIG_STM32_PWR=y +CONFIG_STM32_SPI1=y +CONFIG_STM32_SPI3=y +CONFIG_STM32_USART2=y +CONFIG_STM32_USBHOST=y +CONFIG_SYSTEM_NSH=y +CONFIG_SYSTEM_NXPLAYER=y +CONFIG_USART2_RXBUFSIZE=128 +CONFIG_USART2_SERIAL_CONSOLE=y +CONFIG_USART2_TXBUFSIZE=128 +CONFIG_USBHOST_ISOC_DISABLE=y +CONFIG_USBHOST_MSC=y diff --git a/boards/arm/stm32f4/stm32f4discovery/configs/brickmatch/defconfig b/boards/arm/stm32f4/stm32f4discovery/configs/brickmatch/defconfig new file mode 100644 index 0000000000000..0580be8f51bd9 --- /dev/null +++ b/boards/arm/stm32f4/stm32f4discovery/configs/brickmatch/defconfig @@ -0,0 +1,67 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_STM32_CCMEXCLUDE is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f4discovery" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F407VG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_DRIVERS_VIDEO=y +CONFIG_EXAMPLES_APDS9960=y +CONFIG_EXAMPLES_FB=y +CONFIG_EXAMPLES_FB_STACKSIZE=16000 +CONFIG_EXAMPLES_HELLO=y +CONFIG_FS_LARGEFILE=y +CONFIG_FS_PROCFS=y +CONFIG_GAMES_BRICKMATCH=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LCD=y +CONFIG_LCD_APA102=y +CONFIG_LCD_APA102_FREQUENCY=10000000 +CONFIG_LCD_FRAMEBUFFER=y +CONFIG_LINE_MAX=64 +CONFIG_MM_REGIONS=2 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_LPWORK=y +CONFIG_SCHED_WAITPID=y +CONFIG_SENSORS=y +CONFIG_SENSORS_APDS9960=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_STM32_DMA1=y +CONFIG_STM32_I2C1=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_PWR=y +CONFIG_STM32_SPI1=y +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_NSH=y +CONFIG_USART2_RXBUFSIZE=128 +CONFIG_USART2_SERIAL_CONSOLE=y +CONFIG_USART2_TXBUFSIZE=128 +CONFIG_VIDEO_FB=y diff --git a/boards/arm/stm32f4/stm32f4discovery/configs/canard/defconfig b/boards/arm/stm32f4/stm32f4discovery/configs/canard/defconfig new file mode 100644 index 0000000000000..6b7b18cc1b123 --- /dev/null +++ b/boards/arm/stm32f4/stm32f4discovery/configs/canard/defconfig @@ -0,0 +1,53 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f4discovery" +CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F407VG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_CANUTILS_LIBDRONECAN=y +CONFIG_CAN_EXTID=y +CONFIG_EXAMPLES_DRONECAN=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_MM_REGIONS=2 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_STM32_CAN1=y +CONFIG_STM32_CAN1_BAUD=500000 +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_PWR=y +CONFIG_STM32_SPI1=y +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_NSH=y +CONFIG_USART2_RXBUFSIZE=128 +CONFIG_USART2_SERIAL_CONSOLE=y +CONFIG_USART2_TXBUFSIZE=128 diff --git a/boards/arm/stm32f4/stm32f4discovery/configs/composite/defconfig b/boards/arm/stm32f4/stm32f4discovery/configs/composite/defconfig new file mode 100644 index 0000000000000..6125b59ae1516 --- /dev/null +++ b/boards/arm/stm32f4/stm32f4discovery/configs/composite/defconfig @@ -0,0 +1,101 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_SPI_CALLBACK is not set +CONFIG_ALLOW_BSD_COMPONENTS=y +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f4discovery" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F407VG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL_RESET=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_COMPOSITE_IAD=y +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_ELF=y +CONFIG_EXAMPLES_HELLO=m +CONFIG_FAT_LCNAMES=y +CONFIG_FAT_LFN=y +CONFIG_FS_FAT=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=3072 +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_ENVPATH=y +CONFIG_LIBC_EXECFUNCS=y +CONFIG_LINE_MAX=128 +CONFIG_MMCSD=y +CONFIG_NET=y +CONFIG_NETDB_DNSCLIENT=y +CONFIG_NETDB_DNSSERVER_IPv4ADDR=0x0 +CONFIG_NETINIT_DHCPC=y +CONFIG_NETINIT_DRIPADDR=0x0 +CONFIG_NETINIT_MACADDR_1=0xdeadcafe +CONFIG_NETINIT_NETMASK=0x0 +CONFIG_NETINIT_NOMAC=y +CONFIG_NETINIT_THREAD=y +CONFIG_NETUTILS_DHCPC=y +CONFIG_NETUTILS_IPERF=y +CONFIG_NETUTILS_TELNETD=y +CONFIG_NETUTILS_WEBCLIENT=y +CONFIG_NET_BROADCAST=y +CONFIG_NET_ICMP_SOCKET=y +CONFIG_NET_LOOPBACK=y +CONFIG_NET_STATISTICS=y +CONFIG_NET_TCP=y +CONFIG_NET_TCP_WRITE_BUFFERS=y +CONFIG_NET_UDP=y +CONFIG_NFS=y +CONFIG_NFS_STATISTICS=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_FILE_APPS=y +CONFIG_NSH_READLINE=y +CONFIG_NSH_SYMTAB=y +CONFIG_NSH_SYMTAB_ARRAYNAME="g_symtab" +CONFIG_NSH_SYMTAB_COUNTNAME="g_nsymbols" +CONFIG_PATH_INITIAL="/mnt/nfs/bin" +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RNDIS=y +CONFIG_RNDIS_COMPOSITE=y +CONFIG_SCHED_LPWORK=y +CONFIG_SCHED_WAITPID=y +CONFIG_SENSORS=y +CONFIG_START_DAY=13 +CONFIG_START_MONTH=9 +CONFIG_START_YEAR=2014 +CONFIG_STM32_DMA2=y +CONFIG_STM32_DMACAPABLE=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PWR=y +CONFIG_STM32_SPI2=y +CONFIG_STM32_USART2=y +CONFIG_SYMTAB_ORDEREDBYNAME=y +CONFIG_SYSTEM_COMPOSITE=y +CONFIG_SYSTEM_NSH=y +CONFIG_SYSTEM_PING=y +CONFIG_USART2_SERIAL_CONSOLE=y +CONFIG_USBDEV=y +CONFIG_USBDEV_COMPOSITE=y +CONFIG_USBMSC=y +CONFIG_USBMSC_COMPOSITE=y diff --git a/boards/arm/stm32f4/stm32f4discovery/configs/cxx-oot-build/defconfig b/boards/arm/stm32f4/stm32f4discovery/configs/cxx-oot-build/defconfig new file mode 100644 index 0000000000000..c76721660ac5d --- /dev/null +++ b/boards/arm/stm32f4/stm32f4discovery/configs/cxx-oot-build/defconfig @@ -0,0 +1,48 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_ARCH_LEDS is not set +# CONFIG_DISABLE_OS_API is not set +# CONFIG_SYSTEM_DD is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f4discovery" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F407VG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_CXX_EXCEPTION=y +CONFIG_CXX_STANDARD="c++17" +CONFIG_DRVR_MKRD=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_INIT_NONE=y +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBCXXTOOLCHAIN=y +CONFIG_LINE_MAX=64 +CONFIG_MM_REGIONS=2 +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_PWR=y +CONFIG_STM32_SPI1=y +CONFIG_STM32_USART2=y +CONFIG_USART2_RXBUFSIZE=128 +CONFIG_USART2_SERIAL_CONSOLE=y +CONFIG_USART2_TXBUFSIZE=128 diff --git a/boards/arm/stm32f4/stm32f4discovery/configs/cxxtest/defconfig b/boards/arm/stm32f4/stm32f4discovery/configs/cxxtest/defconfig new file mode 100644 index 0000000000000..e08ad78e23dad --- /dev/null +++ b/boards/arm/stm32f4/stm32f4discovery/configs/cxxtest/defconfig @@ -0,0 +1,42 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +CONFIG_ALLOW_GPL_COMPONENTS=y +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f4discovery" +CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F407VG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_DISABLE_MOUNTPOINT=y +CONFIG_HAVE_CXX=y +CONFIG_HOST_WINDOWS=y +CONFIG_INIT_ENTRYPOINT="cxxtest_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_MAX_EXITFUNS=4 +CONFIG_LIBM=y +CONFIG_MM_REGIONS=2 +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_START_DAY=2 +CONFIG_START_MONTH=11 +CONFIG_START_YEAR=2012 +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_USART2=y +CONFIG_SYMTAB_ORDEREDBYNAME=y +CONFIG_TESTING_CXXTEST=y +CONFIG_UCLIBCXX=y +CONFIG_USART2_RXBUFSIZE=128 +CONFIG_USART2_SERIAL_CONSOLE=y +CONFIG_USART2_TXBUFSIZE=128 diff --git a/boards/arm/stm32f4/stm32f4discovery/configs/elf/defconfig b/boards/arm/stm32f4/stm32f4discovery/configs/elf/defconfig new file mode 100644 index 0000000000000..5d723c21b0b27 --- /dev/null +++ b/boards/arm/stm32f4/stm32f4discovery/configs/elf/defconfig @@ -0,0 +1,44 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f4discovery" +CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F407VG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BINFMT_CONSTRUCTORS=y +CONFIG_BOARDCTL=y +CONFIG_BOARDCTL_ROMDISK=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_CONSOLE_SYSLOG=y +CONFIG_ELF=y +CONFIG_ELF_STACKSIZE=4096 +CONFIG_EXAMPLES_ELF=y +CONFIG_FS_ROMFS=y +CONFIG_HAVE_CXX=y +CONFIG_INIT_ENTRYPOINT="elf_main" +CONFIG_INIT_STACKSIZE=4096 +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_ENVPATH=y +CONFIG_MM_REGIONS=2 +CONFIG_PATH_INITIAL="/mnt/romfs" +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_START_DAY=26 +CONFIG_START_MONTH=10 +CONFIG_START_YEAR=2012 +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_USART2=y +CONFIG_SYMTAB_ORDEREDBYNAME=y +CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f4/stm32f4discovery/configs/ether_w5500/defconfig b/boards/arm/stm32f4/stm32f4discovery/configs/ether_w5500/defconfig new file mode 100644 index 0000000000000..34aeeb9e313c4 --- /dev/null +++ b/boards/arm/stm32f4/stm32f4discovery/configs/ether_w5500/defconfig @@ -0,0 +1,74 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f4discovery" +CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F407VG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BCH=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_EXAMPLES_HELLO=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_MM_REGIONS=2 +CONFIG_NET=y +CONFIG_NETDB_DNSCLIENT=y +CONFIG_NETDB_DNSSERVER_NOADDR=y +CONFIG_NETINIT_DRIPADDR=0xc0a80001 +CONFIG_NETINIT_IPADDR=0xc0a80010 +CONFIG_NETINIT_NOMAC=y +CONFIG_NETUTILS_TELNETD=y +CONFIG_NETUTILS_TFTPC=y +CONFIG_NETUTILS_WEBCLIENT=y +CONFIG_NET_BROADCAST=y +CONFIG_NET_ICMP_SOCKET=y +CONFIG_NET_MAX_LISTENPORTS=16 +CONFIG_NET_STATISTICS=y +CONFIG_NET_TCP=y +CONFIG_NET_TCP_PREALLOC_CONNS=16 +CONFIG_NET_UDP=y +CONFIG_NET_UDP_CHECKSUMS=y +CONFIG_NET_W5500=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_DISABLE_IFUPDOWN=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=192 +CONFIG_SCHED_HPWORKSTACKSIZE=1024 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_PWR=y +CONFIG_STM32_SPI1=y +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_DHCPC_RENEW=y +CONFIG_SYSTEM_NSH=y +CONFIG_SYSTEM_PING=y +CONFIG_USART2_RXBUFSIZE=128 +CONFIG_USART2_SERIAL_CONSOLE=y +CONFIG_USART2_TXBUFSIZE=128 diff --git a/boards/arm/stm32f4/stm32f4discovery/configs/ipv6/defconfig b/boards/arm/stm32f4/stm32f4discovery/configs/ipv6/defconfig new file mode 100644 index 0000000000000..0a856c6e1657d --- /dev/null +++ b/boards/arm/stm32f4/stm32f4discovery/configs/ipv6/defconfig @@ -0,0 +1,89 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_MMCSD_MMCSUPPORT is not set +# CONFIG_MMCSD_SPI is not set +# CONFIG_NET_IPv4 is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f4discovery" +CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F407VG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_ETH0_PHY_LAN8720=y +CONFIG_FAT_LCNAMES=y +CONFIG_FAT_LFN=y +CONFIG_FS_FAT=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_HOST_WINDOWS=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_HOSTNAME="STM32F4-Discovery" +CONFIG_LINE_MAX=64 +CONFIG_MMCSD=y +CONFIG_MMCSD_MULTIBLOCK_LIMIT=1 +CONFIG_MMCSD_SDIO=y +CONFIG_NET=y +CONFIG_NETINIT_IPv6NETMASK_8=0xff80 +CONFIG_NETINIT_NOMAC=y +CONFIG_NET_BROADCAST=y +CONFIG_NET_ICMPv6=y +CONFIG_NET_ICMPv6_NEIGHBOR=y +CONFIG_NET_ICMPv6_SOCKET=y +CONFIG_NET_IPv6=y +CONFIG_NET_SOCKOPTS=y +CONFIG_NET_SOLINGER=y +CONFIG_NET_TCP=y +CONFIG_NET_TCP_WRITE_BUFFERS=y +CONFIG_NET_UDP=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=192 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=13 +CONFIG_START_MONTH=9 +CONFIG_START_YEAR=2014 +CONFIG_STM32F4DISBB=y +CONFIG_STM32_DMA2=y +CONFIG_STM32_DMACAPABLE=y +CONFIG_STM32_ETHMAC=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_PHYADDR=0 +CONFIG_STM32_PHYSR=31 +CONFIG_STM32_PHYSR_100FD=0x0018 +CONFIG_STM32_PHYSR_100HD=0x0008 +CONFIG_STM32_PHYSR_10FD=0x0014 +CONFIG_STM32_PHYSR_10HD=0x0004 +CONFIG_STM32_PHYSR_ALTCONFIG=y +CONFIG_STM32_PHYSR_ALTMODE=0x001c +CONFIG_STM32_PWR=y +CONFIG_STM32_RMII_EXTCLK=y +CONFIG_STM32_SDIO=y +CONFIG_STM32_SPI1=y +CONFIG_STM32_USART6=y +CONFIG_SYSTEM_NSH=y +CONFIG_SYSTEM_PING6=y +CONFIG_USART6_RXBUFSIZE=64 +CONFIG_USART6_SERIAL_CONSOLE=y +CONFIG_USART6_TXBUFSIZE=64 diff --git a/boards/arm/stm32f4/stm32f4discovery/configs/kostest/Make.defs b/boards/arm/stm32f4/stm32f4discovery/configs/kostest/Make.defs new file mode 100644 index 0000000000000..8c981466a321e --- /dev/null +++ b/boards/arm/stm32f4/stm32f4discovery/configs/kostest/Make.defs @@ -0,0 +1,42 @@ +############################################################################ +# boards/arm/stm32f4/stm32f4discovery/configs/kostest/Make.defs +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/.config +include $(TOPDIR)/tools/Config.mk +include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs + +LDSCRIPT1 = memory.ld +LDSCRIPT2 = kernel-space.ld + +ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT1) +ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT2) + +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32f4/stm32f4discovery/configs/kostest/defconfig b/boards/arm/stm32f4/stm32f4discovery/configs/kostest/defconfig new file mode 100644 index 0000000000000..f24a077cc43d3 --- /dev/null +++ b/boards/arm/stm32f4/stm32f4discovery/configs/kostest/defconfig @@ -0,0 +1,51 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f4discovery" +CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F407VG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_ARM_MPU=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILD_PROTECTED=y +CONFIG_CONSOLE_SYSLOG=y +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_HARDFAULT_ALERT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_DISABLE_ENVIRON=y +CONFIG_DISABLE_MOUNTPOINT=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_INIT_ENTRYPOINT="ostest_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_MM_KERNEL_HEAPSIZE=16384 +CONFIG_MM_REGIONS=2 +CONFIG_NUTTX_USERSPACE=0x08020000 +CONFIG_PASS1_BUILDIR="boards/arm/stm32f4/stm32f4discovery/kernel" +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_STACK_COLORATION=y +CONFIG_START_DAY=22 +CONFIG_START_MONTH=3 +CONFIG_START_YEAR=2013 +CONFIG_STM32_CCMEXCLUDE=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_USART2=y +CONFIG_SYMTAB_ORDEREDBYNAME=y +CONFIG_TESTING_OSTEST=y +CONFIG_TESTING_OSTEST_NBARRIER_THREADS=3 +CONFIG_TESTING_OSTEST_STACKSIZE=2048 +CONFIG_USART2_RXBUFSIZE=128 +CONFIG_USART2_SERIAL_CONSOLE=y +CONFIG_USART2_TXBUFSIZE=128 diff --git a/boards/arm/stm32f4/stm32f4discovery/configs/lcd1602/defconfig b/boards/arm/stm32f4/stm32f4discovery/configs/lcd1602/defconfig new file mode 100644 index 0000000000000..90156f132df87 --- /dev/null +++ b/boards/arm/stm32f4/stm32f4discovery/configs/lcd1602/defconfig @@ -0,0 +1,56 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f4discovery" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F407VG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_EXAMPLES_HELLO=y +CONFIG_EXAMPLES_SLCD=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_I2C=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LCD_BACKPACK=y +CONFIG_LCD_LCD1602=y +CONFIG_LINE_MAX=64 +CONFIG_MM_REGIONS=2 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_SLCD=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_STM32_I2C1=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_PWR=y +CONFIG_STM32_SPI1=y +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_NSH=y +CONFIG_USART2_RXBUFSIZE=128 +CONFIG_USART2_SERIAL_CONSOLE=y +CONFIG_USART2_TXBUFSIZE=128 diff --git a/boards/arm/stm32f4/stm32f4discovery/configs/lwl/defconfig b/boards/arm/stm32f4/stm32f4discovery/configs/lwl/defconfig new file mode 100644 index 0000000000000..5f14cb57fe770 --- /dev/null +++ b/boards/arm/stm32f4/stm32f4discovery/configs/lwl/defconfig @@ -0,0 +1,47 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_SERIAL is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f4discovery" +CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F407VG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_EXAMPLES_HELLO=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_LWL_CONSOLE=y +CONFIG_MM_REGIONS=2 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_PWR=y +CONFIG_STM32_SPI1=y +CONFIG_SYSTEM_NSH=y diff --git a/boards/arm/stm32f4/stm32f4discovery/configs/max31855/defconfig b/boards/arm/stm32f4/stm32f4discovery/configs/max31855/defconfig new file mode 100644 index 0000000000000..098729374157a --- /dev/null +++ b/boards/arm/stm32f4/stm32f4discovery/configs/max31855/defconfig @@ -0,0 +1,54 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f4discovery" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F407VG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_EXAMPLES_MAX31855=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_HOST_WINDOWS=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_MM_REGIONS=2 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_SENSORS=y +CONFIG_SENSORS_MAX31855=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_PWR=y +CONFIG_STM32_SPI1=y +CONFIG_STM32_SPI2=y +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_NSH=y +CONFIG_USART2_RXBUFSIZE=128 +CONFIG_USART2_SERIAL_CONSOLE=y +CONFIG_USART2_TXBUFSIZE=128 diff --git a/boards/arm/stm32f4/stm32f4discovery/configs/max7219/defconfig b/boards/arm/stm32f4/stm32f4discovery/configs/max7219/defconfig new file mode 100644 index 0000000000000..bee74446f04bc --- /dev/null +++ b/boards/arm/stm32f4/stm32f4discovery/configs/max7219/defconfig @@ -0,0 +1,92 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_DISABLE_OS_API is not set +# CONFIG_DISABLE_PSEUDOFS_OPERATIONS is not set +# CONFIG_FS_PROCFS_EXCLUDE_BLOCKS is not set +# CONFIG_FS_PROCFS_EXCLUDE_ENVIRON is not set +# CONFIG_FS_PROCFS_EXCLUDE_MEMDUMP is not set +# CONFIG_FS_PROCFS_EXCLUDE_MEMINFO is not set +# CONFIG_FS_PROCFS_EXCLUDE_MOUNT is not set +# CONFIG_FS_PROCFS_EXCLUDE_MOUNTS is not set +# CONFIG_FS_PROCFS_EXCLUDE_PROCESS is not set +# CONFIG_FS_PROCFS_EXCLUDE_UPTIME is not set +# CONFIG_FS_PROCFS_EXCLUDE_USAGE is not set +# CONFIG_FS_PROCFS_EXCLUDE_VERSION is not set +# CONFIG_FS_PROCFS_INCLUDE_PROGMEM is not set +# CONFIG_NSH_DISABLEBG is not set +# CONFIG_NSH_DISABLESCRIPT is not set +# CONFIG_NSH_DISABLE_BASENAME is not set +# CONFIG_NSH_DISABLE_CMP is not set +# CONFIG_NSH_DISABLE_DF is not set +# CONFIG_NSH_DISABLE_DIRNAME is not set +# CONFIG_NSH_DISABLE_EXEC is not set +# CONFIG_NSH_DISABLE_EXIT is not set +# CONFIG_NSH_DISABLE_GET is not set +# CONFIG_NSH_DISABLE_HEXDUMP is not set +# CONFIG_NSH_DISABLE_ITEF is not set +# CONFIG_NSH_DISABLE_LOOPS is not set +# CONFIG_NSH_DISABLE_LOSETUP is not set +# CONFIG_NSH_DISABLE_MKRD is not set +# CONFIG_NSH_DISABLE_PUT is not set +# CONFIG_NSH_DISABLE_SEMICOLON is not set +# CONFIG_NSH_DISABLE_TIME is not set +# CONFIG_NSH_DISABLE_UNAME is not set +# CONFIG_NSH_DISABLE_WGET is not set +# CONFIG_NSH_DISABLE_XD is not set +# CONFIG_NX_DISABLE_1BPP is not set +# CONFIG_NX_WRITEONLY is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f4discovery" +CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F407VG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_DEFAULT_SMALL=y +CONFIG_EXAMPLES_NXHELLO=y +CONFIG_EXAMPLES_NXHELLO_BPP=1 +CONFIG_EXAMPLES_NXHELLO_LISTENER_STACKSIZE=1536 +CONFIG_EXAMPLES_NXHELLO_STACKSIZE=1536 +CONFIG_FS_PROCFS=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_LCD=y +CONFIG_LCD_FRAMEBUFFER=y +CONFIG_LCD_MAX7219=y +CONFIG_LCD_NOGETRUN=y +CONFIG_MAX7219_NHORIZONTALBLKS=4 +CONFIG_MM_REGIONS=2 +CONFIG_MQ_MAXMSGSIZE=64 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NX=y +CONFIG_NXFONT_MONO5X8=y +CONFIG_NXSTART_SERVERSTACK=1536 +CONFIG_NX_BLOCKING=y +CONFIG_NX_MXCLIENTMSGS=32 +CONFIG_PREALLOC_MQ_MSGS=16 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=192 +CONFIG_SCHED_WAITPID=y +CONFIG_SERIAL_TERMIOS=y +CONFIG_START_DAY=21 +CONFIG_START_MONTH=4 +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_PWR=y +CONFIG_STM32_SPI1=y +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_NSH=y +CONFIG_USART2_RXBUFSIZE=128 +CONFIG_USART2_SERIAL_CONSOLE=y +CONFIG_USART2_TXBUFSIZE=128 diff --git a/boards/arm/stm32f4/stm32f4discovery/configs/mmcsdspi/defconfig b/boards/arm/stm32f4/stm32f4discovery/configs/mmcsdspi/defconfig new file mode 100644 index 0000000000000..91350175be5b3 --- /dev/null +++ b/boards/arm/stm32f4/stm32f4discovery/configs/mmcsdspi/defconfig @@ -0,0 +1,72 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_MMCSD_HAVE_CARDDETECT is not set +# CONFIG_MMCSD_HAVE_WRITEPROTECT is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_SPI_CALLBACK is not set +# CONFIG_STM32_CCMEXCLUDE is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f4discovery" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F407VG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL_RESET=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_CODECS_HASH_MD5=y +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_EXAMPLES_HELLO=y +CONFIG_FAT_LFN=y +CONFIG_FS_FAT=y +CONFIG_FS_FATTIME=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_HEAP_COLORATION=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_MMCSD=y +CONFIG_MM_REGIONS=2 +CONFIG_NETUTILS_CODECS=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_READLINE_CMD_HISTORY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_LPWORK=y +CONFIG_SCHED_LPWORKPRIORITY=30 +CONFIG_SCHED_WAITPID=y +CONFIG_SENDFILE_BUFSIZE=1024 +CONFIG_STACK_COLORATION=y +CONFIG_START_DAY=17 +CONFIG_START_MONTH=10 +CONFIG_START_YEAR=2019 +CONFIG_STM32_DMA1=y +CONFIG_STM32_DMA2=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_PWR=y +CONFIG_STM32_SPI2=y +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_NSH=y +CONFIG_TESTING_OSTEST=y +CONFIG_USART2_RXBUFSIZE=128 +CONFIG_USART2_SERIAL_CONSOLE=y +CONFIG_USART2_TXBUFSIZE=128 diff --git a/boards/arm/stm32f4/stm32f4discovery/configs/modbus_slave/defconfig b/boards/arm/stm32f4/stm32f4discovery/configs/modbus_slave/defconfig new file mode 100644 index 0000000000000..9ca17e59aa35a --- /dev/null +++ b/boards/arm/stm32f4/stm32f4discovery/configs/modbus_slave/defconfig @@ -0,0 +1,62 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_MB_TCP_ENABLED is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_NSH_DISABLE_MB is not set +# CONFIG_NSH_DISABLE_MH is not set +# CONFIG_NSH_DISABLE_MW is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f4discovery" +CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F407VG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_EXAMPLES_HELLO=y +CONFIG_EXAMPLES_MODBUS=y +CONFIG_EXAMPLES_MODBUS_PORT=1 +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INDUSTRY_MODBUS=y +CONFIG_INDUSTRY_MODBUS_SLAVE=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_MM_REGIONS=2 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_SERIAL_TERMIOS=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_PWR=y +CONFIG_STM32_SPI1=y +CONFIG_STM32_USART1=y +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_NSH=y +CONFIG_USART1_BAUD=38400 +CONFIG_USART1_PARITY=2 +CONFIG_USART1_RS485=y +CONFIG_USART2_RXBUFSIZE=128 +CONFIG_USART2_SERIAL_CONSOLE=y +CONFIG_USART2_TXBUFSIZE=128 diff --git a/boards/arm/stm32f4/stm32f4discovery/configs/module/defconfig b/boards/arm/stm32f4/stm32f4discovery/configs/module/defconfig new file mode 100644 index 0000000000000..187cc9545643e --- /dev/null +++ b/boards/arm/stm32f4/stm32f4discovery/configs/module/defconfig @@ -0,0 +1,52 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f4discovery" +CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F407VG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL_ROMDISK=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_EXAMPLES_MODULE=y +CONFIG_FS_PROCFS=y +CONFIG_FS_ROMFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_MM_REGIONS=2 +CONFIG_MODULE=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_PWR=y +CONFIG_STM32_SPI1=y +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_NSH=y +CONFIG_USART2_RXBUFSIZE=128 +CONFIG_USART2_SERIAL_CONSOLE=y +CONFIG_USART2_TXBUFSIZE=128 diff --git a/boards/arm/stm32f4/stm32f4discovery/configs/mpr121_keypad/defconfig b/boards/arm/stm32f4/stm32f4discovery/configs/mpr121_keypad/defconfig new file mode 100644 index 0000000000000..ed7c5122192d4 --- /dev/null +++ b/boards/arm/stm32f4/stm32f4discovery/configs/mpr121_keypad/defconfig @@ -0,0 +1,58 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f4discovery" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F407VG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_DEBUG_FEATURES=y +CONFIG_EXAMPLES_HELLO=y +CONFIG_EXAMPLES_KEYBOARD=y +CONFIG_EXAMPLES_KEYBOARD_DEVPATH="/dev/keypad0" +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_I2C=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INPUT=y +CONFIG_INPUT_MPR121_KEYPAD=y +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_MM_REGIONS=2 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_LPWORK=y +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_STM32_I2C1=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_PWR=y +CONFIG_STM32_SPI1=y +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_NSH=y +CONFIG_USART2_RXBUFSIZE=128 +CONFIG_USART2_SERIAL_CONSOLE=y +CONFIG_USART2_TXBUFSIZE=128 diff --git a/boards/arm/stm32f4/stm32f4discovery/configs/mt6816/defconfig b/boards/arm/stm32f4/stm32f4discovery/configs/mt6816/defconfig new file mode 100644 index 0000000000000..54d22a0a69b4e --- /dev/null +++ b/boards/arm/stm32f4/stm32f4discovery/configs/mt6816/defconfig @@ -0,0 +1,56 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_DEBUG_ERROR is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f4discovery" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F407VG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_DEBUG_FEATURES=y +CONFIG_DEBUG_SENSORS=y +CONFIG_EXAMPLES_HELLO=y +CONFIG_EXAMPLES_QENCODER=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_MM_REGIONS=2 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_SENSORS=y +CONFIG_SENSORS_MT6816=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_PWR=y +CONFIG_STM32_SPI1=y +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_NSH=y +CONFIG_USART2_RXBUFSIZE=128 +CONFIG_USART2_SERIAL_CONSOLE=y +CONFIG_USART2_TXBUFSIZE=128 diff --git a/boards/arm/stm32f4/stm32f4discovery/configs/netnsh/defconfig b/boards/arm/stm32f4/stm32f4discovery/configs/netnsh/defconfig new file mode 100644 index 0000000000000..e7e4cc4c09599 --- /dev/null +++ b/boards/arm/stm32f4/stm32f4discovery/configs/netnsh/defconfig @@ -0,0 +1,93 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_MMCSD_MMCSUPPORT is not set +# CONFIG_MMCSD_SPI is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f4discovery" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F407VG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL_RESET=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_ETH0_PHY_LAN8720=y +CONFIG_FAT_LCNAMES=y +CONFIG_FAT_LFN=y +CONFIG_FS_FAT=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_HOST_WINDOWS=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_HOSTNAME="STM32F4-Discovery" +CONFIG_LINE_MAX=64 +CONFIG_MMCSD=y +CONFIG_MMCSD_MULTIBLOCK_LIMIT=1 +CONFIG_MMCSD_SDIO=y +CONFIG_NET=y +CONFIG_NETDB_DNSCLIENT=y +CONFIG_NETDB_DNSSERVER_NOADDR=y +CONFIG_NETDEV_PHY_IOCTL=y +CONFIG_NETINIT_NOMAC=y +CONFIG_NETINIT_THREAD=y +CONFIG_NETUTILS_TELNETD=y +CONFIG_NETUTILS_TFTPC=y +CONFIG_NETUTILS_WEBCLIENT=y +CONFIG_NET_BROADCAST=y +CONFIG_NET_ICMP_SOCKET=y +CONFIG_NET_SOLINGER=y +CONFIG_NET_TCP=y +CONFIG_NET_TCP_WRITE_BUFFERS=y +CONFIG_NET_UDP=y +CONFIG_NET_UDP_CHECKSUMS=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=192 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=13 +CONFIG_START_MONTH=9 +CONFIG_START_YEAR=2014 +CONFIG_STM32F4DISBB=y +CONFIG_STM32_DMA2=y +CONFIG_STM32_DMACAPABLE=y +CONFIG_STM32_ETHMAC=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_PHYADDR=0 +CONFIG_STM32_PHYSR=31 +CONFIG_STM32_PHYSR_100FD=0x0018 +CONFIG_STM32_PHYSR_100HD=0x0008 +CONFIG_STM32_PHYSR_10FD=0x0014 +CONFIG_STM32_PHYSR_10HD=0x0004 +CONFIG_STM32_PHYSR_ALTCONFIG=y +CONFIG_STM32_PHYSR_ALTMODE=0x001c +CONFIG_STM32_PWR=y +CONFIG_STM32_RMII_EXTCLK=y +CONFIG_STM32_SDIO=y +CONFIG_STM32_SPI1=y +CONFIG_STM32_USART6=y +CONFIG_SYSTEM_NSH=y +CONFIG_SYSTEM_PING=y +CONFIG_USART6_RXBUFSIZE=64 +CONFIG_USART6_SERIAL_CONSOLE=y +CONFIG_USART6_TXBUFSIZE=64 diff --git a/boards/arm/stm32f4/stm32f4discovery/configs/nsh/defconfig b/boards/arm/stm32f4/stm32f4discovery/configs/nsh/defconfig new file mode 100644 index 0000000000000..f81f20eeb8072 --- /dev/null +++ b/boards/arm/stm32f4/stm32f4discovery/configs/nsh/defconfig @@ -0,0 +1,50 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f4discovery" +CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F407VG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_EXAMPLES_HELLO=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_HOST_WINDOWS=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_MM_REGIONS=2 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_PWR=y +CONFIG_STM32_SPI1=y +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_NSH=y +CONFIG_USART2_RXBUFSIZE=128 +CONFIG_USART2_SERIAL_CONSOLE=y +CONFIG_USART2_TXBUFSIZE=128 diff --git a/boards/arm/stm32f4/stm32f4discovery/configs/nxlines/defconfig b/boards/arm/stm32f4/stm32f4discovery/configs/nxlines/defconfig new file mode 100644 index 0000000000000..b52478393f047 --- /dev/null +++ b/boards/arm/stm32f4/stm32f4discovery/configs/nxlines/defconfig @@ -0,0 +1,73 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_EXAMPLES_NXLINES_DEFAULT_COLORS is not set +# CONFIG_NXFONTS_DISABLE_16BPP is not set +# CONFIG_NXTK_DEFAULT_BORDERCOLORS is not set +# CONFIG_NX_DISABLE_16BPP is not set +# CONFIG_NX_PACKEDMSFIRST is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f4discovery" +CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F407VG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_EXAMPLES_NXLINES=y +CONFIG_EXAMPLES_NXLINES_BGCOLOR=0x0320 +CONFIG_EXAMPLES_NXLINES_BORDERCOLOR=0xffe0 +CONFIG_EXAMPLES_NXLINES_BORDERWIDTH=4 +CONFIG_EXAMPLES_NXLINES_BPP=16 +CONFIG_EXAMPLES_NXLINES_CIRCLECOLOR=0xf7bb +CONFIG_EXAMPLES_NXLINES_LINECOLOR=0xffe0 +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_HOST_WINDOWS=y +CONFIG_INIT_ENTRYPOINT="nxlines_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LCD=y +CONFIG_LCD_MAXCONTRAST=1 +CONFIG_LCD_MAXPOWER=255 +CONFIG_LCD_SSD1289=y +CONFIG_LINE_MAX=64 +CONFIG_MM_REGIONS=2 +CONFIG_MQ_MAXMSGSIZE=64 +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_LIBRARY=y +CONFIG_NSH_READLINE=y +CONFIG_NX=y +CONFIG_NXFONT_SANS22X29B=y +CONFIG_NXFONT_SANS23X27=y +CONFIG_NXTK_BORDERCOLOR1=0x5cb7 +CONFIG_NXTK_BORDERCOLOR2=0x21c9 +CONFIG_NXTK_BORDERCOLOR3=0xffdf +CONFIG_NX_BLOCKING=y +CONFIG_NX_KBD=y +CONFIG_NX_XYINPUT_MOUSE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_STM32_FSMC=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_PWR=y +CONFIG_STM32_SPI1=y +CONFIG_STM32_USART2=y +CONFIG_SYMTAB_ORDEREDBYNAME=y +CONFIG_USART2_RXBUFSIZE=128 +CONFIG_USART2_SERIAL_CONSOLE=y +CONFIG_USART2_TXBUFSIZE=128 diff --git a/boards/arm/stm32f4/stm32f4discovery/configs/nxscope_cdcacm/defconfig b/boards/arm/stm32f4/stm32f4discovery/configs/nxscope_cdcacm/defconfig new file mode 100644 index 0000000000000..44b4599511611 --- /dev/null +++ b/boards/arm/stm32f4/stm32f4discovery/configs/nxscope_cdcacm/defconfig @@ -0,0 +1,62 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_DEV_CONSOLE is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f4discovery" +CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F407VG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL=y +CONFIG_BOARDCTL_MKRD=y +CONFIG_BOARDCTL_USBDEVCTRL=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_CDCACM=y +CONFIG_CDCACM_RXBUFSIZE=256 +CONFIG_CDCACM_TXBUFSIZE=2048 +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_EXAMPLES_NXSCOPE=y +CONFIG_EXAMPLES_NXSCOPE_CDCACM=y +CONFIG_EXAMPLES_NXSCOPE_SERIAL_PATH="/dev/ttyACM0" +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_INIT_ENTRYPOINT="nxscope_main" +CONFIG_INIT_STACKSIZE=4096 +CONFIG_INTELHEX_BINARY=y +CONFIG_LOGGING_NXSCOPE=y +CONFIG_LOGGING_NXSCOPE_ACKFRAMES=y +CONFIG_LOGGING_NXSCOPE_DIVIDER=y +CONFIG_LOGGING_NXSCOPE_INTF_SERIAL=y +CONFIG_MM_REGIONS=2 +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAMLOG=y +CONFIG_RAMLOG_BUFSIZE=4096 +CONFIG_RAMLOG_SYSLOG=y +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_STACK_COLORATION=y +CONFIG_START_DAY=27 +CONFIG_START_YEAR=2013 +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PWR=y +CONFIG_STM32_SPI1=y +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_READLINE=y +CONFIG_USBDEV=y diff --git a/boards/arm/stm32f4/stm32f4discovery/configs/pm/defconfig b/boards/arm/stm32f4/stm32f4discovery/configs/pm/defconfig new file mode 100644 index 0000000000000..baab23750c31e --- /dev/null +++ b/boards/arm/stm32f4/stm32f4discovery/configs/pm/defconfig @@ -0,0 +1,56 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_ARCH_LEDS is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f4discovery" +CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F407VG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_CUSTOM_PMINIT=y +CONFIG_ARCH_IDLE_CUSTOM=y +CONFIG_ARCH_IRQBUTTONS=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_HOST_WINDOWS=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_MM_REGIONS=2 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PM=y +CONFIG_PM_BUTTONS=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_RTC_ALARM=y +CONFIG_RTC_DATETIME=y +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=192 +CONFIG_SCHED_HPWORKSTACKSIZE=1024 +CONFIG_SCHED_WAITPID=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_PWR=y +CONFIG_STM32_RTC=y +CONFIG_STM32_TIM1=y +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_NSH=y +CONFIG_USART2_RXBUFSIZE=128 +CONFIG_USART2_SERIAL_CONSOLE=y +CONFIG_USART2_TXBUFSIZE=128 diff --git a/boards/arm/stm32f4/stm32f4discovery/configs/posix_spawn/defconfig b/boards/arm/stm32f4/stm32f4discovery/configs/posix_spawn/defconfig new file mode 100644 index 0000000000000..71f4c3468486c --- /dev/null +++ b/boards/arm/stm32f4/stm32f4discovery/configs/posix_spawn/defconfig @@ -0,0 +1,49 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f4discovery" +CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F407VG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BINFMT_CONSTRUCTORS=y +CONFIG_BOARDCTL=y +CONFIG_BOARDCTL_APP_SYMTAB=y +CONFIG_BOARDCTL_ROMDISK=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_CONSOLE_SYSLOG=y +CONFIG_ELF=y +CONFIG_EXAMPLES_POSIXSPAWN=y +CONFIG_EXECFUNCS_HAVE_SYMTAB=y +CONFIG_EXECFUNCS_NSYMBOLS_VAR="g_spawn_nexports" +CONFIG_EXECFUNCS_SYMTAB_ARRAY="g_spawn_exports" +CONFIG_FS_ROMFS=y +CONFIG_HAVE_CXX=y +CONFIG_INIT_ENTRYPOINT="posix_spawn_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_ENVPATH=y +CONFIG_LIBC_EXECFUNCS=y +CONFIG_MM_REGIONS=2 +CONFIG_PATH_INITIAL="/mnt/romfs" +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_START_DAY=26 +CONFIG_START_MONTH=10 +CONFIG_START_YEAR=2012 +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_USART2=y +CONFIG_SYMTAB_ORDEREDBYNAME=y +CONFIG_USART2_RXBUFSIZE=128 +CONFIG_USART2_SERIAL_CONSOLE=y +CONFIG_USART2_TXBUFSIZE=128 diff --git a/boards/arm/stm32f4/stm32f4discovery/configs/pseudoterm/defconfig b/boards/arm/stm32f4/stm32f4discovery/configs/pseudoterm/defconfig new file mode 100644 index 0000000000000..2571bb23113bc --- /dev/null +++ b/boards/arm/stm32f4/stm32f4discovery/configs/pseudoterm/defconfig @@ -0,0 +1,54 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f4discovery" +CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F407VG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_EXAMPLES_PTYTEST=y +CONFIG_EXAMPLES_PTYTEST_POLL=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_MM_IOB=y +CONFIG_MM_REGIONS=2 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_PSEUDOTERM=y +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_SERIAL_TERMIOS=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_PWR=y +CONFIG_STM32_SPI1=y +CONFIG_STM32_USART2=y +CONFIG_STM32_USART3=y +CONFIG_SYSTEM_NSH=y +CONFIG_USART2_RXBUFSIZE=128 +CONFIG_USART2_SERIAL_CONSOLE=y +CONFIG_USART2_TXBUFSIZE=128 diff --git a/boards/arm/stm32f4/stm32f4discovery/configs/rgbled/defconfig b/boards/arm/stm32f4/stm32f4discovery/configs/rgbled/defconfig new file mode 100644 index 0000000000000..37c135b2c6f2d --- /dev/null +++ b/boards/arm/stm32f4/stm32f4discovery/configs/rgbled/defconfig @@ -0,0 +1,63 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f4discovery" +CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F407VG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_EXAMPLES_RGBLED=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INIT_ENTRYPOINT="rgbled_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_MM_REGIONS=2 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_PWM=y +CONFIG_PWM_NCHANNELS=3 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RGBLED=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PWR=y +CONFIG_STM32_SPI1=y +CONFIG_STM32_TIM1=y +CONFIG_STM32_TIM1_PWM=y +CONFIG_STM32_TIM2=y +CONFIG_STM32_TIM2_CH2OUT=y +CONFIG_STM32_TIM2_CHANNEL=2 +CONFIG_STM32_TIM2_PWM=y +CONFIG_STM32_TIM3=y +CONFIG_STM32_TIM3_CH3OUT=y +CONFIG_STM32_TIM3_CHANNEL=3 +CONFIG_STM32_TIM3_PWM=y +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_NSH=y +CONFIG_USART2_RXBUFSIZE=128 +CONFIG_USART2_SERIAL_CONSOLE=y +CONFIG_USART2_TXBUFSIZE=128 diff --git a/boards/arm/stm32f4/stm32f4discovery/configs/rndis/defconfig b/boards/arm/stm32f4/stm32f4discovery/configs/rndis/defconfig new file mode 100644 index 0000000000000..f57a05ca6c5bc --- /dev/null +++ b/boards/arm/stm32f4/stm32f4discovery/configs/rndis/defconfig @@ -0,0 +1,94 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ALLOW_BSD_COMPONENTS=y +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f4discovery" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F407VG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL_RESET=y +CONFIG_BOARDCTL_USBDEVCTRL=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_ELF=y +CONFIG_EXAMPLES_HELLO=m +CONFIG_FAT_LCNAMES=y +CONFIG_FAT_LFN=y +CONFIG_FS_FAT=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=3072 +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_ENVPATH=y +CONFIG_LIBC_EXECFUNCS=y +CONFIG_LINE_MAX=128 +CONFIG_NET=y +CONFIG_NETDB_DNSCLIENT=y +CONFIG_NETDB_DNSSERVER_IPv4ADDR=0x0 +CONFIG_NETINIT_DHCPC=y +CONFIG_NETINIT_DRIPADDR=0x0 +CONFIG_NETINIT_MACADDR_1=0xdeadcafe +CONFIG_NETINIT_NETMASK=0x0 +CONFIG_NETINIT_NOMAC=y +CONFIG_NETINIT_THREAD=y +CONFIG_NETUTILS_DHCPC=y +CONFIG_NETUTILS_IPERF=y +CONFIG_NETUTILS_TELNETD=y +CONFIG_NETUTILS_WEBCLIENT=y +CONFIG_NET_BROADCAST=y +CONFIG_NET_ICMP_SOCKET=y +CONFIG_NET_LOOPBACK=y +CONFIG_NET_STATISTICS=y +CONFIG_NET_TCP=y +CONFIG_NET_TCP_WRITE_BUFFERS=y +CONFIG_NET_UDP=y +CONFIG_NFS=y +CONFIG_NFS_STATISTICS=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_FILE_APPS=y +CONFIG_NSH_READLINE=y +CONFIG_NSH_SYMTAB=y +CONFIG_NSH_SYMTAB_ARRAYNAME="g_symtab" +CONFIG_NSH_SYMTAB_COUNTNAME="g_nsymbols" +CONFIG_PATH_INITIAL="/mnt/nfs/bin" +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RNDIS=y +CONFIG_SCHED_LPWORK=y +CONFIG_SCHED_WAITPID=y +CONFIG_SENSORS=y +CONFIG_START_DAY=13 +CONFIG_START_MONTH=9 +CONFIG_START_YEAR=2014 +CONFIG_STM32_DMA2=y +CONFIG_STM32_DMACAPABLE=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PWR=y +CONFIG_STM32_SPI1=y +CONFIG_STM32_USART2=y +CONFIG_SYMTAB_ORDEREDBYNAME=y +CONFIG_SYSTEM_NSH=y +CONFIG_SYSTEM_PING=y +CONFIG_USART2_SERIAL_CONSOLE=y +CONFIG_USBDEV=y diff --git a/boards/arm/stm32f4/stm32f4discovery/configs/sbutton/defconfig b/boards/arm/stm32f4/stm32f4discovery/configs/sbutton/defconfig new file mode 100644 index 0000000000000..569b7f230ceff --- /dev/null +++ b/boards/arm/stm32f4/stm32f4discovery/configs/sbutton/defconfig @@ -0,0 +1,56 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_ASSERTIONS_FILENAME is not set +# CONFIG_NDEBUG is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f4discovery" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F407VG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_EXAMPLES_HELLO=y +CONFIG_EXAMPLES_KEYBOARD=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INPUT=y +CONFIG_INPUT_SBUTTON=y +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_MM_REGIONS=2 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_PWR=y +CONFIG_STM32_SPI1=y +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_NSH=y +CONFIG_USART2_RXBUFSIZE=128 +CONFIG_USART2_SERIAL_CONSOLE=y +CONFIG_USART2_TXBUFSIZE=128 +CONFIG_WQUEUE_NOTIFIER=y diff --git a/boards/arm/stm32f4/stm32f4discovery/configs/sporadic/defconfig b/boards/arm/stm32f4/stm32f4discovery/configs/sporadic/defconfig new file mode 100644 index 0000000000000..5c8b151be4f70 --- /dev/null +++ b/boards/arm/stm32f4/stm32f4discovery/configs/sporadic/defconfig @@ -0,0 +1,50 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f4discovery" +CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F407VG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_FS_PROCFS=y +CONFIG_HOST_WINDOWS=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_MM_REGIONS=2 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_SCHED_SPORADIC=y +CONFIG_SCHED_SPORADIC_MAXREPL=5 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=3 +CONFIG_START_YEAR=2021 +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_PWR=y +CONFIG_STM32_SPI1=y +CONFIG_STM32_USART6=y +CONFIG_SYSTEM_NSH=y +CONFIG_TESTING_OSTEST=y +CONFIG_USART6_RXBUFSIZE=128 +CONFIG_USART6_SERIAL_CONSOLE=y +CONFIG_USART6_TXBUFSIZE=128 +CONFIG_USEC_PER_TICK=1000 diff --git a/boards/arm/stm32f4/stm32f4discovery/configs/st7567/defconfig b/boards/arm/stm32f4/stm32f4discovery/configs/st7567/defconfig new file mode 100644 index 0000000000000..c76f9ac1a12f6 --- /dev/null +++ b/boards/arm/stm32f4/stm32f4discovery/configs/st7567/defconfig @@ -0,0 +1,63 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f4discovery" +CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F407VG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_DRIVERS_VIDEO=y +CONFIG_EXAMPLES_FB=y +CONFIG_EXAMPLES_HELLO=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LCD=y +CONFIG_LCD_FRAMEBUFFER=y +CONFIG_LCD_NOGETRUN=y +CONFIG_LCD_ST7567=y +CONFIG_LINE_MAX=64 +CONFIG_MM_REGIONS=2 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_NXFONTS_DISABLE_1BPP=y +CONFIG_NXFONTS_DISABLE_24BPP=y +CONFIG_NXFONTS_DISABLE_2BPP=y +CONFIG_NXFONTS_DISABLE_32BPP=y +CONFIG_NXFONTS_DISABLE_4BPP=y +CONFIG_NXFONTS_DISABLE_8BPP=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_SPI_CMDDATA=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_PWR=y +CONFIG_STM32_SPI1=y +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_NSH=y +CONFIG_USART2_RXBUFSIZE=128 +CONFIG_USART2_SERIAL_CONSOLE=y +CONFIG_USART2_TXBUFSIZE=128 +CONFIG_VIDEO_FB=y diff --git a/boards/arm/stm32f4/stm32f4discovery/configs/st7789/defconfig b/boards/arm/stm32f4/stm32f4discovery/configs/st7789/defconfig new file mode 100644 index 0000000000000..2e36dbdc267c6 --- /dev/null +++ b/boards/arm/stm32f4/stm32f4discovery/configs/st7789/defconfig @@ -0,0 +1,64 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f4discovery" +CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F407VG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_DRIVERS_VIDEO=y +CONFIG_EXAMPLES_FB=y +CONFIG_EXAMPLES_HELLO=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LCD=y +CONFIG_LCD_FRAMEBUFFER=y +CONFIG_LCD_NOGETRUN=y +CONFIG_LCD_PORTRAIT=y +CONFIG_LCD_ST7789=y +CONFIG_LINE_MAX=64 +CONFIG_MM_REGIONS=2 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_NXFONTS_DISABLE_1BPP=y +CONFIG_NXFONTS_DISABLE_24BPP=y +CONFIG_NXFONTS_DISABLE_2BPP=y +CONFIG_NXFONTS_DISABLE_32BPP=y +CONFIG_NXFONTS_DISABLE_4BPP=y +CONFIG_NXFONTS_DISABLE_8BPP=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_SPI_CMDDATA=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_PWR=y +CONFIG_STM32_SPI1=y +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_NSH=y +CONFIG_USART2_RXBUFSIZE=128 +CONFIG_USART2_SERIAL_CONSOLE=y +CONFIG_USART2_TXBUFSIZE=128 +CONFIG_VIDEO_FB=y diff --git a/boards/arm/stm32f4/stm32f4discovery/configs/testlibcxx/defconfig b/boards/arm/stm32f4/stm32f4discovery/configs/testlibcxx/defconfig new file mode 100644 index 0000000000000..938dcea494fd6 --- /dev/null +++ b/boards/arm/stm32f4/stm32f4discovery/configs/testlibcxx/defconfig @@ -0,0 +1,52 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f4discovery" +CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F407VG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_CXX_LOCALIZATION=y +CONFIG_CXX_WCHAR=y +CONFIG_DISABLE_MOUNTPOINT=y +CONFIG_EXAMPLES_HELLOXX=y +CONFIG_HAVE_CXX=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBCXX=y +CONFIG_LIBC_FLOATINGPOINT=y +CONFIG_LIBC_LOCALE=y +CONFIG_LIBC_LOCALTIME=y +CONFIG_LIBC_MAX_EXITFUNS=4 +CONFIG_LIBM=y +CONFIG_MM_REGIONS=2 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=2 +CONFIG_START_MONTH=11 +CONFIG_START_YEAR=2012 +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_USART2=y +CONFIG_SYMTAB_ORDEREDBYNAME=y +CONFIG_SYSTEM_NSH=y +CONFIG_TLS_NELEM=16 +CONFIG_TLS_TASK_NELEM=8 +CONFIG_USART2_RXBUFSIZE=128 +CONFIG_USART2_SERIAL_CONSOLE=y +CONFIG_USART2_TXBUFSIZE=128 diff --git a/boards/arm/stm32f4/stm32f4discovery/configs/usbmsc/defconfig b/boards/arm/stm32f4/stm32f4discovery/configs/usbmsc/defconfig new file mode 100644 index 0000000000000..65c89a22460f8 --- /dev/null +++ b/boards/arm/stm32f4/stm32f4discovery/configs/usbmsc/defconfig @@ -0,0 +1,60 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f4discovery" +CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F407VG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_FAT_LCNAMES=y +CONFIG_FAT_LFN=y +CONFIG_FS_FAT=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_MM_REGIONS=2 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_DISABLE_IFUPDOWN=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=192 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=27 +CONFIG_START_YEAR=2013 +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PWR=y +CONFIG_STM32_SPI1=y +CONFIG_STM32_USART2=y +CONFIG_SYSLOG_CHAR=y +CONFIG_SYSLOG_DEVPATH="/dev/ttyS0" +CONFIG_SYSTEM_NSH=y +CONFIG_SYSTEM_USBMSC=y +CONFIG_SYSTEM_USBMSC_DEVMINOR1=0 +CONFIG_SYSTEM_USBMSC_DEVPATH1="/dev/ram0" +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART2_SERIAL_CONSOLE=y +CONFIG_USBDEV=y +CONFIG_USBMSC=y +CONFIG_USBMSC_REMOVABLE=y diff --git a/boards/arm/stm32f4/stm32f4discovery/configs/usbnsh/defconfig b/boards/arm/stm32f4/stm32f4discovery/configs/usbnsh/defconfig new file mode 100644 index 0000000000000..167fbd097ef5a --- /dev/null +++ b/boards/arm/stm32f4/stm32f4discovery/configs/usbnsh/defconfig @@ -0,0 +1,58 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_DEV_CONSOLE is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f4discovery" +CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F407VG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL_USBDEVCTRL=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_CDCACM=y +CONFIG_CDCACM_CONSOLE=y +CONFIG_CDCACM_RXBUFSIZE=256 +CONFIG_CDCACM_TXBUFSIZE=256 +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_EXAMPLES_HELLO=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_MM_REGIONS=2 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAMLOG=y +CONFIG_RAMLOG_BUFSIZE=4096 +CONFIG_RAMLOG_SYSLOG=y +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_STACK_COLORATION=y +CONFIG_START_DAY=27 +CONFIG_START_YEAR=2013 +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PWR=y +CONFIG_STM32_SPI1=y +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_NSH=y +CONFIG_USBDEV=y diff --git a/boards/arm/stm32f4/stm32f4discovery/configs/wifi/defconfig b/boards/arm/stm32f4/stm32f4discovery/configs/wifi/defconfig new file mode 100644 index 0000000000000..73a18bd96ac3f --- /dev/null +++ b/boards/arm/stm32f4/stm32f4discovery/configs/wifi/defconfig @@ -0,0 +1,104 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_MMCSD_HAVE_CARDDETECT is not set +# CONFIG_MMCSD_HAVE_WRITEPROTECT is not set +# CONFIG_NET_ARP is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_SPI_CALLBACK is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f4discovery" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F407VG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL_RESET=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_CODECS_HASH_MD5=y +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_HARDFAULT_ALERT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_DRIVERS_WIRELESS=y +CONFIG_ELF=y +CONFIG_EXAMPLES_HELLO=m +CONFIG_EXAMPLES_WEBSERVER=y +CONFIG_FAT_LFN=y +CONFIG_FS_FAT=y +CONFIG_FS_FATTIME=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_HEAP_COLORATION=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_ENVPATH=y +CONFIG_LIBC_EXECFUNCS=y +CONFIG_LINE_MAX=64 +CONFIG_MMCSD=y +CONFIG_MM_IOB=y +CONFIG_MM_REGIONS=2 +CONFIG_NET=y +CONFIG_NETDB_DNSCLIENT=y +CONFIG_NETINIT_NETLOCAL=y +CONFIG_NETUTILS_CODECS=y +CONFIG_NETUTILS_FTPC=y +CONFIG_NETUTILS_HTTPD_DIRLIST=y +CONFIG_NETUTILS_HTTPD_SENDFILE=y +CONFIG_NETUTILS_TELNETD=y +CONFIG_NETUTILS_WEBCLIENT=y +CONFIG_NETUTILS_WEBSERVER=y +CONFIG_NET_USRSOCK=y +CONFIG_NET_USRSOCK_PREALLOC_CONNS=16 +CONFIG_NET_USRSOCK_UDP=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_NSH_SYMTAB=y +CONFIG_NSH_SYMTAB_ARRAYNAME="g_symtab" +CONFIG_NSH_SYMTAB_COUNTNAME="g_nsymbols" +CONFIG_PATH_INITIAL="/mnt/sd0/bin" +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_READLINE_CMD_HISTORY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_LPWORKPRIORITY=30 +CONFIG_SCHED_WAITPID=y +CONFIG_SENDFILE_BUFSIZE=1024 +CONFIG_STACK_COLORATION=y +CONFIG_START_DAY=22 +CONFIG_START_MONTH=10 +CONFIG_START_YEAR=2019 +CONFIG_STM32_DMA1=y +CONFIG_STM32_DMA2=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_PWR=y +CONFIG_STM32_SPI2=y +CONFIG_STM32_SPI2_DMA=y +CONFIG_STM32_SPI3=y +CONFIG_STM32_SPI3_DMA=y +CONFIG_STM32_USART2=y +CONFIG_SYMTAB_ORDEREDBYNAME=y +CONFIG_SYSTEM_DHCPC_RENEW=y +CONFIG_SYSTEM_NSH=y +CONFIG_SYSTEM_NTPC=y +CONFIG_TESTING_OSTEST=y +CONFIG_USART2_RXBUFSIZE=128 +CONFIG_USART2_SERIAL_CONSOLE=y +CONFIG_USART2_TXBUFSIZE=128 +CONFIG_WIRELESS_GS2200M=y +CONFIG_WL_GS2200M=y +CONFIG_WL_GS2200M_DISABLE_DHCPC=y +CONFIG_WL_GS2200M_SPI_FREQUENCY=10000000 diff --git a/boards/arm/stm32f4/stm32f4discovery/configs/xen1210/defconfig b/boards/arm/stm32f4/stm32f4discovery/configs/xen1210/defconfig new file mode 100644 index 0000000000000..c7a5839e069aa --- /dev/null +++ b/boards/arm/stm32f4/stm32f4discovery/configs/xen1210/defconfig @@ -0,0 +1,56 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f4discovery" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F407VG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_MM_REGIONS=2 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_PWM=y +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_WAITPID=y +CONFIG_SENSORS=y +CONFIG_SENSORS_XEN1210=y +CONFIG_START_DAY=17 +CONFIG_START_MONTH=8 +CONFIG_START_YEAR=2016 +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_PWR=y +CONFIG_STM32_SPI1=y +CONFIG_STM32_TIM1=y +CONFIG_STM32_TIM1_CH1OUT=y +CONFIG_STM32_TIM1_PWM=y +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_NSH=y +CONFIG_USART2_RXBUFSIZE=128 +CONFIG_USART2_SERIAL_CONSOLE=y +CONFIG_USART2_TXBUFSIZE=128 diff --git a/boards/arm/stm32f4/stm32f4discovery/include/board.h b/boards/arm/stm32f4/stm32f4discovery/include/board.h new file mode 100644 index 0000000000000..d8bebb7ef980d --- /dev/null +++ b/boards/arm/stm32f4/stm32f4discovery/include/board.h @@ -0,0 +1,650 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f4discovery/include/board.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_STM32_STM32F4DISCOVERY_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32_STM32F4DISCOVERY_INCLUDE_BOARD_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#ifndef __ASSEMBLY__ +# include +# include +#endif + +/* Do not include STM32-specific header files here */ + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Clocking *****************************************************************/ + +/* The STM32F4 Discovery board features a single 8MHz crystal. + * Space is provided for a 32kHz RTC backup crystal, but it is not stuffed. + * + * This is the canonical configuration: + * System Clock source : PLL (HSE) + * SYSCLK(Hz) : 168000000 Determined by PLL + * configuration + * HCLK(Hz) : 168000000 (STM32_RCC_CFGR_HPRE) + * AHB Prescaler : 1 (STM32_RCC_CFGR_HPRE) + * APB1 Prescaler : 4 (STM32_RCC_CFGR_PPRE1) + * APB2 Prescaler : 2 (STM32_RCC_CFGR_PPRE2) + * HSE Frequency(Hz) : 8000000 (STM32_BOARD_XTAL) + * PLLM : 8 (STM32_PLLCFG_PLLM) + * PLLN : 336 (STM32_PLLCFG_PLLN) + * PLLP : 2 (STM32_PLLCFG_PLLP) + * PLLQ : 7 (STM32_PLLCFG_PLLQ) + * Main regulator output voltage : Scale1 mode Needed for high speed + * SYSCLK + * Flash Latency(WS) : 5 + * Prefetch Buffer : OFF + * Instruction cache : ON + * Data cache : ON + * Require 48MHz for USB OTG FS, : Enabled + * SDIO and RNG clock + */ + +/* HSI - 16 MHz RC factory-trimmed + * LSI - 32 KHz RC + * HSE - On-board crystal frequency is 8MHz + * LSE - 32.768 kHz + */ + +#define STM32_BOARD_XTAL 8000000ul + +#define STM32_HSI_FREQUENCY 16000000ul +#define STM32_LSI_FREQUENCY 32000 +#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL +#define STM32_LSE_FREQUENCY 32768 + +/* Main PLL Configuration. + * + * PLL source is HSE + * PLL_VCO = (STM32_HSE_FREQUENCY / PLLM) * PLLN + * = (8,000,000 / 8) * 336 + * = 336,000,000 + * SYSCLK = PLL_VCO / PLLP + * = 336,000,000 / 2 = 168,000,000 + * USB OTG FS, SDIO and RNG Clock + * = PLL_VCO / PLLQ + * = 48,000,000 + */ + +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(8) +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(336) +#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_2 +#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(7) + +#define STM32_SYSCLK_FREQUENCY 168000000ul + +/* AHB clock (HCLK) is SYSCLK (168MHz) */ + +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY + +/* APB1 clock (PCLK1) is HCLK/4 (42MHz) */ + +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd4 /* PCLK1 = HCLK / 4 */ +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/4) + +/* Timers driven from APB1 will be twice PCLK1 */ + +#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) + +/* APB2 clock (PCLK2) is HCLK/2 (84MHz) */ + +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLKd2 /* PCLK2 = HCLK / 2 */ +#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/2) + +/* Timers driven from APB2 will be twice PCLK2 */ + +#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM9_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM10_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM11_CLKIN (2*STM32_PCLK2_FREQUENCY) + +/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx + * otherwise frequency is 2xAPBx. + * Note: TIM1,8 are on APB2, others on APB1 + */ + +#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM2_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM3_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM4_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM5_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM6_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM7_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY + +/* SDIO dividers. Note that slower clocking is required when DMA is disabled + * in order to avoid RX overrun/TX underrun errors due to delayed responses + * to service FIFOs in interrupt driven mode. These values have not been + * tuned!!! + * + * SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(118+2)=400 KHz + */ + +#define SDIO_INIT_CLKDIV (118 << SDIO_CLKCR_CLKDIV_SHIFT) + +/* DMA ON: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(1+2)=16 MHz + * DMA OFF: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(2+2)=12 MHz + */ + +#ifdef CONFIG_SDIO_DMA +# define SDIO_MMCXFR_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT) +#else +# define SDIO_MMCXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT) +#endif + +/* DMA ON: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(1+2)=16 MHz + * DMA OFF: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(2+2)=12 MHz + */ + +#ifdef CONFIG_SDIO_DMA +# define SDIO_SDXFR_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT) +#else +# define SDIO_SDXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT) +#endif + +/* LED definitions **********************************************************/ + +/* If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs + * in any way. The following definitions are used to access individual LEDs. + */ + +/* LED index values for use with board_userled() */ + +#define BOARD_LED1 0 +#define BOARD_LED2 1 +#define BOARD_LED3 2 +#define BOARD_LED4 3 +#define BOARD_NLEDS 4 + +#define BOARD_LED_GREEN BOARD_LED1 +#define BOARD_LED_ORANGE BOARD_LED2 +#define BOARD_LED_RED BOARD_LED3 +#define BOARD_LED_BLUE BOARD_LED4 + +/* LED bits for use with board_userled_all() */ + +#define BOARD_LED1_BIT (1 << BOARD_LED1) +#define BOARD_LED2_BIT (1 << BOARD_LED2) +#define BOARD_LED3_BIT (1 << BOARD_LED3) +#define BOARD_LED4_BIT (1 << BOARD_LED4) + +/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the 4 LEDs on + * board the stm32f4discovery. The following definitions describe how NuttX + * controls the LEDs: + */ + +#define LED_STARTED 0 /* LED1 */ +#define LED_HEAPALLOCATE 1 /* LED2 */ +#define LED_IRQSENABLED 2 /* LED1 + LED2 */ +#define LED_STACKCREATED 3 /* LED3 */ +#define LED_INIRQ 4 /* LED1 + LED3 */ +#define LED_SIGNAL 5 /* LED2 + LED3 */ +#define LED_ASSERTION 6 /* LED1 + LED2 + LED3 */ +#define LED_PANIC 7 /* N/C + N/C + N/C + LED4 */ + +/* Button definitions *******************************************************/ + +/* The STM32F4 Discovery supports one button: */ + +#define BUTTON_USER 0 +#define NUM_BUTTONS 1 +#define BUTTON_USER_BIT (1 << BUTTON_USER) + +/* Alternate function pin selections ****************************************/ + +/* CAN */ + +#ifndef CONFIG_STM32_FSMC +# define GPIO_CAN1_RX (GPIO_CAN1_RX_3|GPIO_SPEED_50MHz) +# define GPIO_CAN1_TX (GPIO_CAN1_TX_3|GPIO_SPEED_50MHz) +#endif + +#ifndef CONFIG_STM32_ETHMAC +# define GPIO_CAN2_RX (GPIO_CAN2_RX_1|GPIO_SPEED_50MHz) +# define GPIO_CAN2_TX (GPIO_CAN2_TX_1|GPIO_SPEED_50MHz) +#endif + +/* USART1 */ + +#ifdef CONFIG_USART1_RS485 + /* Lets use for RS485 on pins: PB6 and PB7 */ + +# define GPIO_USART1_TX (GPIO_USART1_TX_2|GPIO_SPEED_100MHz) +# define GPIO_USART1_RX (GPIO_USART1_RX_2|GPIO_SPEED_100MHz) + + /* RS485 DIR pin: PA15 */ + +# define GPIO_USART1_RS485_DIR (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_50MHz |\ + GPIO_OUTPUT_CLEAR | GPIO_PORTA | GPIO_PIN15) + +#endif + +/* USART2: + * + * The STM32F4 Discovery has no on-board serial devices, but the console is + * brought out to PA2 (TX) and PA3 (RX) for connection to an external serial + * device. + * + * These pins selections, however, conflict with pin usage on the + * STM32F4DIS-BB. + */ + +#ifndef CONFIG_STM32F4DISBB +# define GPIO_USART2_RX (GPIO_USART2_RX_1|GPIO_SPEED_100MHz) /* PA3, P1 pin 13 */ +# define GPIO_USART2_TX (GPIO_USART2_TX_1|GPIO_SPEED_100MHz) /* PA2, P1 pin 14 */ +# define GPIO_USART2_CTS GPIO_USART2_CTS_1 /* PA0, P1 pin 11 */ +# define GPIO_USART2_RTS GPIO_USART2_RTS_1 /* PA1, P1 pin 12 (conflict with USER button) */ +#endif + +/* USART3: + * + * Used in pseudoterm configuration and also with the BT860 HCI UART. + * RTS/CTS Flow control support is needed by the HCI UART. + * + * There are conflicts with the STM32F4DIS-BB Ethernet in this configuration + * when Ethernet is enabled: + * + * PB-11 conflicts with Ethernet TXEN + * PB-13 conflicts with Ethernet TXD1 + * + * UART3 TXD and RXD are available on CON4 PD8 and PD8 of the STM32F4DIS-BB, + * respectively, but not CTS or RTS. For now we assume that Ethernet is not + * enabled if USART3 is used in a configuration with the STM32F4DIS-BB. + */ + +#define GPIO_USART3_TX (GPIO_USART3_TX_1|GPIO_SPEED_100MHz) /* PB10, P1 pin 34 (also MP45DT02 CLK_IN) */ +#define GPIO_USART3_RX (GPIO_USART3_RX_1|GPIO_SPEED_100MHz) /* PB11, P1 pin 35 */ +#define GPIO_USART3_CTS GPIO_USART3_CTS_1 /* PB13, P1 pin 37 */ +#define GPIO_USART3_RTS GPIO_USART3_RTS_1 /* PB14, P1 pin 38 */ + +/* USART6: + * + * The STM32F4DIS-BB base board provides RS-232 drivers and a DB9 connector + * for USART6. This is the preferred serial console for use with the + * STM32F4DIS-BB. + * + * NOTE: CTS and RTS are not brought out to the RS-232 connector on the + * baseboard. + */ + +#define GPIO_USART6_RX (GPIO_USART6_RX_1|GPIO_SPEED_100MHz) /* PC7 (also I2S3_MCK and P2 pin 48) */ +#define GPIO_USART6_TX (GPIO_USART6_TX_1|GPIO_SPEED_100MHz) /* PC6 (also P2 pin 47) */ + +/* PWM + * + * The STM32F4 Discovery has no real on-board PWM devices, but the board + * can be configured to output a pulse train using TIM4 CH2 on PD13. + */ + +#define GPIO_TIM4_CH2OUT (GPIO_TIM4_CH2OUT_2|GPIO_SPEED_50MHz) + +/* Capture + * + * The STM32F4 Discovery has no real on-board pwm capture devices, but the + * board can be configured to capture pwm using TIM3 CH2 PB5. + */ + +#define GPIO_TIM3_CH2IN (GPIO_TIM3_CH2IN_2|GPIO_SPEED_50MHz) +#define GPIO_TIM3_CH1IN (GPIO_TIM3_CH2IN_2|GPIO_SPEED_50MHz) + +/* RGB LED + * + * R = TIM1 CH1 on PE9 | G = TIM2 CH2 on PA1 | B = TIM3 CH3 on PB0 + */ + +#define GPIO_TIM1_CH1OUT (GPIO_TIM1_CH1OUT_2|GPIO_SPEED_50MHz) +#define GPIO_TIM2_CH2OUT (GPIO_TIM2_CH2OUT_1|GPIO_SPEED_50MHz) +#define GPIO_TIM3_CH3OUT (GPIO_TIM3_CH3OUT_1|GPIO_SPEED_50MHz) + +/* SPI - There is a MEMS device on SPI1 using these pins: */ + +#define GPIO_SPI1_MISO (GPIO_SPI1_MISO_1|GPIO_SPEED_50MHz) +#define GPIO_SPI1_MOSI (GPIO_SPI1_MOSI_1|GPIO_SPEED_50MHz) +#define GPIO_SPI1_SCK (GPIO_SPI1_SCK_1|GPIO_SPEED_50MHz) + +/* SPI DMA -- As used for I2S DMA transfer with the audio configuration */ + +#define DMACHAN_SPI1_RX DMAMAP_SPI1_RX_1 +#define DMACHAN_SPI1_TX DMAMAP_SPI1_TX_1 + +/* SPI2 - Test MAX31855 on SPI2 PB10 = SCK, PB14 = MISO */ + +#define GPIO_SPI2_MISO (GPIO_SPI2_MISO_1|GPIO_SPEED_50MHz) +#define GPIO_SPI2_MOSI (GPIO_SPI2_MOSI_1|GPIO_SPEED_50MHz) +#define GPIO_SPI2_SCK (GPIO_SPI2_SCK_1|GPIO_SPEED_50MHz) + +/* SPI2 DMA -- As used for MMC/SD SPI */ + +#define DMACHAN_SPI2_RX DMAMAP_SPI2_RX +#define DMACHAN_SPI2_TX DMAMAP_SPI2_TX + +/* SPI3 DMA -- As used for I2S DMA transfer with the audio configuration */ + +#define GPIO_SPI3_MISO (GPIO_SPI3_MISO_1|GPIO_SPEED_50MHz) +#define GPIO_SPI3_MOSI (GPIO_SPI3_MOSI_1|GPIO_SPEED_50MHz) +#define GPIO_SPI3_SCK (GPIO_SPI3_SCK_1|GPIO_SPEED_50MHz) + +#define DMACHAN_SPI3_RX DMAMAP_SPI3_RX_1 +#define DMACHAN_SPI3_TX DMAMAP_SPI3_TX_1 + +/* I2S3 - CS43L22 configuration uses I2S3 */ + +#define GPIO_I2S3_SD GPIO_I2S3_SD_2 +#define GPIO_I2S3_CK GPIO_I2S3_CK_2 +#define GPIO_I2S3_WS GPIO_I2S3_WS_1 + +#define DMACHAN_I2S3_RX DMAMAP_SPI3_RX_2 +#define DMACHAN_I2S3_TX DMAMAP_SPI3_TX_2 + +/* I2C. Only I2C1 is available on the stm32f4discovery. I2C1_SCL and + * I2C1_SDA are available on the following pins: + * + * - PB6 is I2C1_SCL + * - PB9 is I2C1_SDA + */ + +#define GPIO_I2C1_SCL (GPIO_I2C1_SCL_1|GPIO_SPEED_50MHz) +#define GPIO_I2C1_SDA (GPIO_I2C1_SDA_2|GPIO_SPEED_50MHz) + +/* Timer Inputs/Outputs */ + +#define GPIO_TIM2_CH1IN (GPIO_TIM2_CH1IN_2|GPIO_SPEED_50MHz) +#define GPIO_TIM2_CH2IN (GPIO_TIM2_CH2IN_1|GPIO_SPEED_50MHz) + +#define GPIO_TIM8_CH1IN (GPIO_TIM8_CH1IN_1|GPIO_SPEED_50MHz) +#define GPIO_TIM8_CH2IN (GPIO_TIM8_CH2IN_1|GPIO_SPEED_50MHz) + +/* Ethernet *****************************************************************/ + +#if defined(CONFIG_STM32F4DISBB) && defined(CONFIG_STM32_ETHMAC) + /* RMII interface to the LAN8720 PHY */ + +# ifndef CONFIG_STM32_RMII +# error CONFIG_STM32_RMII must be defined +# endif + + /* Clocking is provided by an external 25Mhz XTAL */ + +# ifndef CONFIG_STM32_RMII_EXTCLK +# error CONFIG_STM32_RMII_EXTCLK must be defined +# endif + + /* Pin disambiguation */ + +# define GPIO_ETH_RMII_TX_EN (GPIO_ETH_RMII_TX_EN_1|GPIO_SPEED_100MHz) +# define GPIO_ETH_RMII_TXD0 (GPIO_ETH_RMII_TXD0_1|GPIO_SPEED_100MHz) +# define GPIO_ETH_RMII_TXD1 (GPIO_ETH_RMII_TXD1_1|GPIO_SPEED_100MHz) +# define GPIO_ETH_PPS_OUT (GPIO_ETH_PPS_OUT_1|GPIO_SPEED_100MHz) + +#endif + +#ifdef CONFIG_MMCSD_SPI +#define GPIO_MMCSD_NSS (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_50MHz | \ + GPIO_OUTPUT_SET | GPIO_PORTB | GPIO_PIN12) + +#define GPIO_MMCSD_NCD (GPIO_INPUT | GPIO_FLOAT | GPIO_EXTI | \ + GPIO_PORTC | GPIO_PIN1) +#endif + +/* DMA Channel/Stream Selections ********************************************/ + +/* Stream selections are arbitrary for now but might become important in the + * future if we set aside more DMA channels/streams. + * + * SDIO DMA + * DMAMAP_SDIO_1 = Channel 4, Stream 3 + * DMAMAP_SDIO_2 = Channel 4, Stream 6 + */ + +#define DMAMAP_SDIO DMAMAP_SDIO_1 + +/* ZERO CROSS pin definition */ + +#define BOARD_ZEROCROSS_GPIO \ + (GPIO_INPUT|GPIO_FLOAT|GPIO_EXTI|GPIO_PORTD|GPIO_PIN0) + +/* Pin for APDS-9960 sensor */ + +#define GPIO_APDS9960_INT \ + (GPIO_INPUT|GPIO_FLOAT|GPIO_EXTI|GPIO_PORTE|GPIO_PIN0) + +#define BOARD_APDS9960_GPIO_INT GPIO_APDS9960_INT + +/* IRQ Pin for MPR121 Capacitive Keypad */ + +#define GPIO_MPR121_INT \ + (GPIO_INPUT|GPIO_PULLUP|GPIO_EXTI|GPIO_PORTB|GPIO_PIN0) + +#define BOARD_MPR121_GPIO_INT GPIO_MPR121_INT + +/* Pin for Magnetic Encoder MT6816 */ + +#define GPIO_CS_MT6816 (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz|\ + GPIO_OUTPUT_SET|GPIO_PORTE|GPIO_PIN3) + +/* LIS3DSH */ + +#define GPIO_LIS3DSH_EXT0 \ + (GPIO_INPUT|GPIO_FLOAT|GPIO_AF0|GPIO_SPEED_50MHz|GPIO_PORTE|GPIO_PIN0) + +#define BOARD_LIS3DSH_GPIO_EXT0 GPIO_LIS3DSH_EXT0 + +/* XEN1210 magnetic sensor */ + +#define GPIO_XEN1210_INT (GPIO_INPUT|GPIO_FLOAT|GPIO_EXTI|\ + GPIO_OPENDRAIN|GPIO_PORTA|GPIO_PIN5) + +#define GPIO_CS_XEN1210 (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz|\ + GPIO_OUTPUT_SET|GPIO_PORTA|GPIO_PIN4) + +#define BOARD_XEN1210_GPIO_INT GPIO_XEN1210_INT + +#define BOARD_SBUTTON_GPIO_INT (GPIO_INPUT|GPIO_FLOAT|GPIO_EXTI|\ + GPIO_OPENDRAIN|GPIO_PORTA|GPIO_PIN0) + +/* Define what timer to use as XEN1210 CLK (will use channel 1) */ + +#define BOARD_XEN1210_PWMTIMER 1 + +/* Keyboard Matrix Configuration */ + +/* Define keyboard matrix row pins (outputs) */ + +#define GPIO_KMATRIX_ROW0 (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz|\ + GPIO_OUTPUT_CLEAR|GPIO_PORTE|GPIO_PIN7) +#define GPIO_KMATRIX_ROW1 (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz|\ + GPIO_OUTPUT_CLEAR|GPIO_PORTE|GPIO_PIN8) +#define GPIO_KMATRIX_ROW2 (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz|\ + GPIO_OUTPUT_CLEAR|GPIO_PORTE|GPIO_PIN9) +#define GPIO_KMATRIX_ROW3 (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz|\ + GPIO_OUTPUT_CLEAR|GPIO_PORTE|GPIO_PIN10) + +/* Row pins as inputs with pull-up for early diagnostics */ + +#define GPIO_KMATRIX_ROW0_IN (GPIO_INPUT|GPIO_PULLUP|GPIO_SPEED_50MHz|\ + GPIO_PORTE|GPIO_PIN7) +#define GPIO_KMATRIX_ROW1_IN (GPIO_INPUT|GPIO_PULLUP|GPIO_SPEED_50MHz|\ + GPIO_PORTE|GPIO_PIN8) +#define GPIO_KMATRIX_ROW2_IN (GPIO_INPUT|GPIO_PULLUP|GPIO_SPEED_50MHz|\ + GPIO_PORTE|GPIO_PIN9) +#define GPIO_KMATRIX_ROW3_IN (GPIO_INPUT|GPIO_PULLUP|GPIO_SPEED_50MHz|\ + GPIO_PORTE|GPIO_PIN10) + +/* Define keyboard matrix column pins (inputs) */ + +#define GPIO_KMATRIX_COL0 (GPIO_INPUT|GPIO_PULLUP|GPIO_SPEED_50MHz|\ + GPIO_PORTE|GPIO_PIN11) +#define GPIO_KMATRIX_COL1 (GPIO_INPUT|GPIO_PULLUP|GPIO_SPEED_50MHz|\ + GPIO_PORTE|GPIO_PIN13) +#define GPIO_KMATRIX_COL2 (GPIO_INPUT|GPIO_PULLUP|GPIO_SPEED_50MHz|\ + GPIO_PORTE|GPIO_PIN14) + +/* Column pins as outputs for diagnostics only */ + +#define GPIO_KMATRIX_COL0_OUT (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz|\ + GPIO_OUTPUT_CLEAR|GPIO_PORTE|GPIO_PIN11) +#define GPIO_KMATRIX_COL1_OUT (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz|\ + GPIO_OUTPUT_CLEAR|GPIO_PORTE|GPIO_PIN13) +#define GPIO_KMATRIX_COL2_OUT (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz|\ + GPIO_OUTPUT_CLEAR|GPIO_PORTE|GPIO_PIN14) + +/* Board-level KMATRIX pin definitions */ + +#define BOARD_KMATRIX_ROW0 GPIO_KMATRIX_ROW0 +#define BOARD_KMATRIX_ROW1 GPIO_KMATRIX_ROW1 +#define BOARD_KMATRIX_ROW2 GPIO_KMATRIX_ROW2 +#define BOARD_KMATRIX_ROW3 GPIO_KMATRIX_ROW3 + +#define BOARD_KMATRIX_ROW0_IN GPIO_KMATRIX_ROW0_IN +#define BOARD_KMATRIX_ROW1_IN GPIO_KMATRIX_ROW1_IN +#define BOARD_KMATRIX_ROW2_IN GPIO_KMATRIX_ROW2_IN +#define BOARD_KMATRIX_ROW3_IN GPIO_KMATRIX_ROW3_IN + +#define BOARD_KMATRIX_COL0 GPIO_KMATRIX_COL0 +#define BOARD_KMATRIX_COL1 GPIO_KMATRIX_COL1 +#define BOARD_KMATRIX_COL2 GPIO_KMATRIX_COL2 + +#define BOARD_KMATRIX_COL0_OUT GPIO_KMATRIX_COL0_OUT +#define BOARD_KMATRIX_COL1_OUT GPIO_KMATRIX_COL1_OUT +#define BOARD_KMATRIX_COL2_OUT GPIO_KMATRIX_COL2_OUT + +#ifdef CONFIG_INPUT_KMATRIX +int board_kmatrix_diag(int loops, int delay_ms); +#endif + +/* Keyboard Matrix I2C Configuration */ + +#define CONFIG_STM32_KMATRIX_I2C_BUS 1 /* I2C1 */ +#define CONFIG_STM32_KMATRIX_I2C_ADDR 0x20 /* MCP23X08/PCA9538 address */ +#define CONFIG_STM32_KMATRIX_I2C_FREQ 400000 /* 400 kHz */ + +/* MCO and ETH inputs (referenced by arch/eth driver) */ + +#define GPIO_MCO1 (GPIO_MCO1_0|GPIO_SPEED_100MHz) +#define GPIO_ETH_MDC (GPIO_ETH_MDC_0|GPIO_SPEED_100MHz) +#define GPIO_ETH_MDIO (GPIO_ETH_MDIO_0|GPIO_SPEED_100MHz) +#define GPIO_ETH_RMII_CRS_DV (GPIO_ETH_RMII_CRS_DV_0|GPIO_SPEED_100MHz) +#define GPIO_ETH_RMII_REF_CLK (GPIO_ETH_RMII_REF_CLK_0|GPIO_SPEED_100MHz) +#define GPIO_ETH_RMII_RXD0 (GPIO_ETH_RMII_RXD0_0|GPIO_SPEED_100MHz) +#define GPIO_ETH_RMII_RXD1 (GPIO_ETH_RMII_RXD1_0|GPIO_SPEED_100MHz) + +/* SDIO */ + +#define GPIO_SDIO_CK (GPIO_SDIO_CK_0|GPIO_SPEED_50MHz) +#define GPIO_SDIO_CMD (GPIO_SDIO_CMD_0|GPIO_SPEED_50MHz) +#define GPIO_SDIO_D0 (GPIO_SDIO_D0_0|GPIO_SPEED_50MHz) +#define GPIO_SDIO_D1 (GPIO_SDIO_D1_0|GPIO_SPEED_50MHz) +#define GPIO_SDIO_D2 (GPIO_SDIO_D2_0|GPIO_SPEED_50MHz) +#define GPIO_SDIO_D3 (GPIO_SDIO_D3_0|GPIO_SPEED_50MHz) + +/* USB OTG FS / OTG HS */ + +#define GPIO_OTGFS_DM (GPIO_OTGFS_DM_0|GPIO_SPEED_100MHz) +#define GPIO_OTGFS_DP (GPIO_OTGFS_DP_0|GPIO_SPEED_100MHz) +#define GPIO_OTGFS_ID (GPIO_OTGFS_ID_0|GPIO_SPEED_100MHz) +#define GPIO_OTGFS_SOF (GPIO_OTGFS_SOF_0|GPIO_SPEED_100MHz) +#define GPIO_OTGHSFS_DM (GPIO_OTGHSFS_DM_0|GPIO_SPEED_100MHz) +#define GPIO_OTGHSFS_DP (GPIO_OTGHSFS_DP_0|GPIO_SPEED_100MHz) +#define GPIO_OTGHSFS_ID (GPIO_OTGHSFS_ID_0|GPIO_SPEED_100MHz) + +/* DAC */ + +#define GPIO_DAC1_OUT1 GPIO_DAC1_OUT1_0 +#define GPIO_DAC1_OUT2 GPIO_DAC1_OUT2_0 + +/* I2S3 MCK (referenced by audio driver) */ + +#define GPIO_I2S3_MCK GPIO_I2S3_MCK_0 + +/* FSMC SRAM/LCD pins */ + +#define GPIO_FSMC_A0 (GPIO_FSMC_A0_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A1 (GPIO_FSMC_A1_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A2 (GPIO_FSMC_A2_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A3 (GPIO_FSMC_A3_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A4 (GPIO_FSMC_A4_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A5 (GPIO_FSMC_A5_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A6 (GPIO_FSMC_A6_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A7 (GPIO_FSMC_A7_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A8 (GPIO_FSMC_A8_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A9 (GPIO_FSMC_A9_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A10 (GPIO_FSMC_A10_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A11 (GPIO_FSMC_A11_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A12 (GPIO_FSMC_A12_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A13 (GPIO_FSMC_A13_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A14 (GPIO_FSMC_A14_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A15 (GPIO_FSMC_A15_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A16 (GPIO_FSMC_A16_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A17 (GPIO_FSMC_A17_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A18 (GPIO_FSMC_A18_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A19 (GPIO_FSMC_A19_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A20 (GPIO_FSMC_A20_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A21 (GPIO_FSMC_A21_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A22 (GPIO_FSMC_A22_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A23 (GPIO_FSMC_A23_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A24 (GPIO_FSMC_A24_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A25 (GPIO_FSMC_A25_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_D0 (GPIO_FSMC_D0_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_D1 (GPIO_FSMC_D1_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_D2 (GPIO_FSMC_D2_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_D3 (GPIO_FSMC_D3_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_D4 (GPIO_FSMC_D4_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_D5 (GPIO_FSMC_D5_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_D6 (GPIO_FSMC_D6_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_D7 (GPIO_FSMC_D7_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_D8 (GPIO_FSMC_D8_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_D9 (GPIO_FSMC_D9_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_D10 (GPIO_FSMC_D10_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_D11 (GPIO_FSMC_D11_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_D12 (GPIO_FSMC_D12_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_D13 (GPIO_FSMC_D13_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_D14 (GPIO_FSMC_D14_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_D15 (GPIO_FSMC_D15_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_NOE (GPIO_FSMC_NOE_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_NWE (GPIO_FSMC_NWE_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_NE1 (GPIO_FSMC_NE1_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_NE2 (GPIO_FSMC_NE2_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_NE3 (GPIO_FSMC_NE3_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_NE4 (GPIO_FSMC_NE4_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_NBL0 (GPIO_FSMC_NBL0_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_NBL1 (GPIO_FSMC_NBL1_0|GPIO_SPEED_100MHz) + +#endif /* __BOARDS_ARM_STM32_STM32F4DISCOVERY_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32f4/stm32f4discovery/kernel/CMakeLists.txt b/boards/arm/stm32f4/stm32f4discovery/kernel/CMakeLists.txt new file mode 100644 index 0000000000000..7edffd00c7c5e --- /dev/null +++ b/boards/arm/stm32f4/stm32f4discovery/kernel/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32f4/stm32f4discovery/kernel/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +target_sources(nuttx_user PRIVATE stm32_userspace.c) diff --git a/boards/arm/stm32f4/stm32f4discovery/kernel/Makefile b/boards/arm/stm32f4/stm32f4discovery/kernel/Makefile new file mode 100644 index 0000000000000..94250906043bb --- /dev/null +++ b/boards/arm/stm32f4/stm32f4discovery/kernel/Makefile @@ -0,0 +1,94 @@ +############################################################################ +# boards/arm/stm32f4/stm32f4discovery/kernel/Makefile +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +# The entry point name (if none is provided in the .config file) + +CONFIG_INIT_ENTRYPOINT ?= user_start +ENTRYPT = $(patsubst "%",%,$(CONFIG_INIT_ENTRYPOINT)) + +# Get the paths to the libraries and the links script path in format that +# is appropriate for the host OS + +USER_LIBPATHS = $(addprefix -L,$(call CONVERT_PATH,$(addprefix $(TOPDIR)$(DELIM),$(dir $(USERLIBS))))) +USER_LDSCRIPT = -T $(call CONVERT_PATH,$(BOARD_DIR)$(DELIM)scripts$(DELIM)memory.ld) +USER_LDSCRIPT += -T $(call CONVERT_PATH,$(BOARD_DIR)$(DELIM)scripts$(DELIM)user-space.ld) +USER_HEXFILE += $(call CONVERT_PATH,$(TOPDIR)$(DELIM)nuttx_user.hex) +USER_SRECFILE += $(call CONVERT_PATH,$(TOPDIR)$(DELIM)nuttx_user.srec) +USER_BINFILE += $(call CONVERT_PATH,$(TOPDIR)$(DELIM)nuttx_user.bin) + +USER_LDFLAGS = --undefined=$(ENTRYPT) --entry=$(ENTRYPT) $(USER_LDSCRIPT) +USER_LDLIBS = $(patsubst lib%,-l%,$(basename $(notdir $(USERLIBS)))) +USER_LIBGCC = "${shell "$(CC)" $(ARCHCPUFLAGS) -print-libgcc-file-name}" + +# Source files + +CSRCS = stm32_userspace.c +COBJS = $(CSRCS:.c=$(OBJEXT)) +OBJS = $(COBJS) + +# Targets: + +all: $(TOPDIR)$(DELIM)nuttx_user.elf $(TOPDIR)$(DELIM)User.map +.PHONY: nuttx_user.elf depend clean distclean + +$(COBJS): %$(OBJEXT): %.c + $(call COMPILE, $<, $@) + +# Create the nuttx_user.elf file containing all of the user-mode code + +nuttx_user.elf: $(OBJS) + $(Q) $(LD) -o $@ $(USER_LDFLAGS) $(USER_LIBPATHS) $(OBJS) --start-group $(USER_LDLIBS) $(USER_LIBGCC) --end-group + +$(TOPDIR)$(DELIM)nuttx_user.elf: nuttx_user.elf + @echo "LD: nuttx_user.elf" + $(Q) cp -a nuttx_user.elf $(TOPDIR)$(DELIM)nuttx_user.elf +ifeq ($(CONFIG_INTELHEX_BINARY),y) + @echo "CP: nuttx_user.hex" + $(Q) $(OBJCOPY) $(OBJCOPYARGS) -O ihex nuttx_user.elf $(USER_HEXFILE) +endif +ifeq ($(CONFIG_MOTOROLA_SREC),y) + @echo "CP: nuttx_user.srec" + $(Q) $(OBJCOPY) $(OBJCOPYARGS) -O srec nuttx_user.elf $(USER_SRECFILE) +endif +ifeq ($(CONFIG_RAW_BINARY),y) + @echo "CP: nuttx_user.bin" + $(Q) $(OBJCOPY) $(OBJCOPYARGS) -O binary nuttx_user.elf $(USER_BINFILE) +endif + +$(TOPDIR)$(DELIM)User.map: nuttx_user.elf + @echo "MK: User.map" + $(Q) $(NM) nuttx_user.elf >$(TOPDIR)$(DELIM)User.map + $(Q) $(CROSSDEV)size nuttx_user.elf + +.depend: + +depend: .depend + +clean: + $(call DELFILE, nuttx_user.elf) + $(call DELFILE, "$(TOPDIR)$(DELIM)nuttx_user.*") + $(call DELFILE, "$(TOPDIR)$(DELIM)User.map") + $(call CLEAN) + +distclean: clean diff --git a/boards/arm/stm32f4/stm32f4discovery/kernel/stm32_userspace.c b/boards/arm/stm32f4/stm32f4discovery/kernel/stm32_userspace.c new file mode 100644 index 0000000000000..6bcb1ee9edf26 --- /dev/null +++ b/boards/arm/stm32f4/stm32f4discovery/kernel/stm32_userspace.c @@ -0,0 +1,111 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f4discovery/kernel/stm32_userspace.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include +#include +#include +#include + +#if defined(CONFIG_BUILD_PROTECTED) && !defined(__KERNEL__) + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +#ifndef CONFIG_NUTTX_USERSPACE +# error "CONFIG_NUTTX_USERSPACE not defined" +#endif + +#if CONFIG_NUTTX_USERSPACE != 0x08020000 +# error "CONFIG_NUTTX_USERSPACE must be 0x08020000 to match memory.ld" +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static struct userspace_data_s g_userspace_data = +{ + .us_heap = &g_mmheap, +}; + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/* These 'addresses' of these values are setup by the linker script. */ + +extern uint8_t _stext[]; /* Start of .text */ +extern uint8_t _etext[]; /* End_1 of .text + .rodata */ +extern const uint8_t _eronly[]; /* End+1 of read only section (.text + .rodata) */ +extern uint8_t _sdata[]; /* Start of .data */ +extern uint8_t _edata[]; /* End+1 of .data */ +extern uint8_t _sbss[]; /* Start of .bss */ +extern uint8_t _ebss[]; /* End+1 of .bss */ + +const struct userspace_s userspace locate_data(".userspace") = +{ + /* General memory map */ + + .us_entrypoint = CONFIG_INIT_ENTRYPOINT, + .us_textstart = (uintptr_t)_stext, + .us_textend = (uintptr_t)_etext, + .us_datasource = (uintptr_t)_eronly, + .us_datastart = (uintptr_t)_sdata, + .us_dataend = (uintptr_t)_edata, + .us_bssstart = (uintptr_t)_sbss, + .us_bssend = (uintptr_t)_ebss, + + /* User data memory structure */ + + .us_data = &g_userspace_data, + + /* Task/thread startup routines */ + + .task_startup = nxtask_startup, + + /* Signal handler trampoline */ + + .signal_handler = up_signal_handler, + + /* User-space work queue support (declared in include/nuttx/wqueue.h) */ + +#ifdef CONFIG_LIBC_USRWORK + .work_usrstart = work_usrstart, +#endif +}; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +#endif /* CONFIG_BUILD_PROTECTED && !__KERNEL__ */ diff --git a/boards/arm/stm32f4/stm32f4discovery/scripts/Make.defs b/boards/arm/stm32f4/stm32f4discovery/scripts/Make.defs new file mode 100644 index 0000000000000..9b89de7ed1c56 --- /dev/null +++ b/boards/arm/stm32f4/stm32f4discovery/scripts/Make.defs @@ -0,0 +1,41 @@ +############################################################################ +# boards/arm/stm32f4/stm32f4discovery/scripts/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/.config +include $(TOPDIR)/tools/Config.mk +include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs + +LDSCRIPT = ld.script +ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) + +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32f4/stm32f4discovery/scripts/kernel-space.ld b/boards/arm/stm32f4/stm32f4discovery/scripts/kernel-space.ld new file mode 100644 index 0000000000000..b6fff76f8b944 --- /dev/null +++ b/boards/arm/stm32f4/stm32f4discovery/scripts/kernel-space.ld @@ -0,0 +1,99 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f4discovery/scripts/kernel-space.ld + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* NOTE: This depends on the memory.ld script having been included prior to + * this script. + */ + +OUTPUT_ARCH(arm) +ENTRY(_stext) +SECTIONS +{ + .text : { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > kflash + + .init_section : { + _sinit = ABSOLUTE(.); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) + _einit = ABSOLUTE(.); + } > kflash + + .ARM.extab : { + *(.ARM.extab*) + } > kflash + + __exidx_start = ABSOLUTE(.); + .ARM.exidx : { + *(.ARM.exidx*) + } > kflash + + __exidx_end = ABSOLUTE(.); + + _eronly = ABSOLUTE(.); + + .data : { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > ksram AT > kflash + + .bss : { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(8); + _ebss = ABSOLUTE(.); + } > ksram + + /* Stabs debugging sections */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/stm32f4/stm32f4discovery/scripts/ld.script b/boards/arm/stm32f4/stm32f4discovery/scripts/ld.script new file mode 100644 index 0000000000000..d51d0c7f6b291 --- /dev/null +++ b/boards/arm/stm32f4/stm32f4discovery/scripts/ld.script @@ -0,0 +1,126 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f4discovery/scripts/ld.script + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* The STM32F407VG has 1024Kb of FLASH beginning at address 0x0800:0000 and + * 192Kb of SRAM. SRAM is split up into three blocks: + * + * 1) 112Kb of SRAM beginning at address 0x2000:0000 + * 2) 16Kb of SRAM beginning at address 0x2001:c000 + * 3) 64Kb of CCM SRAM beginning at address 0x1000:0000 + * + * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 + * where the code expects to begin execution by jumping to the entry point in + * the 0x0800:0000 address + * range. + */ + +MEMORY +{ + flash (rx) : ORIGIN = 0x08000000, LENGTH = 1024K + sram (rwx) : ORIGIN = 0x20000000, LENGTH = 112K +} + +OUTPUT_ARCH(arm) +ENTRY(_stext) +EXTERN(_vectors) +SECTIONS +{ + .text : { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > flash + + .init_section : ALIGN(4) { + _sinit = ABSOLUTE(.); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) + _einit = ABSOLUTE(.); + } > flash + + .ARM.extab : ALIGN(4) { + *(.ARM.extab*) + } > flash + + .ARM.exidx : ALIGN(4) { + __exidx_start = ABSOLUTE(.); + *(.ARM.exidx*) + __exidx_end = ABSOLUTE(.); + } > flash + + .tdata : { + _stdata = ABSOLUTE(.); + *(.tdata .tdata.* .gnu.linkonce.td.*); + _etdata = ABSOLUTE(.); + } > flash + + .tbss : { + _stbss = ABSOLUTE(.); + *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); + _etbss = ABSOLUTE(.); + } > flash + + _eronly = ABSOLUTE(.); + + .data : ALIGN(4) { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > sram AT > flash + + .bss : ALIGN(4) { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + _ebss = ABSOLUTE(.); + } > sram + + /* Stabs debugging sections. */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/stm32f4/stm32f4discovery/scripts/memory.ld b/boards/arm/stm32f4/stm32f4discovery/scripts/memory.ld new file mode 100644 index 0000000000000..0d1eadb712dcf --- /dev/null +++ b/boards/arm/stm32f4/stm32f4discovery/scripts/memory.ld @@ -0,0 +1,88 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f4discovery/scripts/memory.ld + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* The STM32F407VG has 1024Kb of FLASH beginning at address 0x0800:0000 and + * 192Kb of SRAM. SRAM is split up into three blocks: + * + * 1) 112KB of SRAM beginning at address 0x2000:0000 + * 2) 16KB of SRAM beginning at address 0x2001:c000 + * 3) 64KB of CCM SRAM beginning at address 0x1000:0000 + * + * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 + * where the code expects to begin execution by jumping to the entry point in + * the 0x0800:0000 address range. + * + * For MPU support, the kernel-mode NuttX section is assumed to be 128Kb of + * FLASH and 4Kb of SRAM. That is an excessive amount for the kernel which + * should fit into 64KB and, of course, can be optimized as needed (See + * also boards/arm/stm32f4/stm32f4discovery/scripts/kernel-space.ld). Allowing the + * additional does permit addition debug instrumentation to be added to the + * kernel space without overflowing the partition. + * + * Alignment of the user space FLASH partition is also a critical factor: + * The user space FLASH partition will be spanned with a single region of + * size 2**n bytes. The alignment of the user-space region must be the same. + * As a consequence, as the user-space increases in size, the alignment + * requirement also increases. + * + * This alignment requirement means that the largest user space FLASH region + * you can have will be 512KB at it would have to be positioned at + * 0x08800000. If you change this address, don't forget to change the + * CONFIG_NUTTX_USERSPACE configuration setting to match and to modify + * the check in kernel/userspace.c. + * + * For the same reasons, the maximum size of the SRAM mapping is limited to + * 4KB. Both of these alignment limitations could be reduced by using + * multiple regions to map the FLASH/SDRAM range or perhaps with some + * clever use of subregions. + * + * A detailed memory map for the 112KB SRAM region is as follows: + * + * 0x2000 0000: Kernel .data region. Typical size: 0.1KB + * ------ ---- Kernel .bss region. Typical size: 1.8KB + * 0x2000 0800: Kernel IDLE thread stack (approximate). Size is + * determined by CONFIG_IDLETHREAD_STACKSIZE and + * adjustments for alignment. Typical is 1KB. + * ------ ---- Padded to 8KB + * 0x2000 2000: User .data region. Size is variable. + * ------ ---- User .bss region Size is variable. + * 0x2000 4000: Beginning of kernel heap. Size determined by + * CONFIG_MM_KERNEL_HEAPSIZE which must be set to 16Kb. + * 0x2000 8000: Beginning of 32Kb user heap. + * 0x2001 0000: The remainder of SRAM is, unfortunately, wasted. + * 0x2001 c000: End+1 of CPU RAM + */ + +MEMORY +{ + /* 1024Kb FLASH */ + + kflash (rx) : ORIGIN = 0x08000000, LENGTH = 128K + uflash (rx) : ORIGIN = 0x08020000, LENGTH = 128K + xflash (rx) : ORIGIN = 0x08040000, LENGTH = 768K + + /* 112Kb of contiguous SRAM */ + + ksram (rwx) : ORIGIN = 0x20000000, LENGTH = 16K + usram (rwx) : ORIGIN = 0x20004000, LENGTH = 16K + xsram (rwx) : ORIGIN = 0x20008000, LENGTH = 80K +} diff --git a/boards/arm/stm32f4/stm32f4discovery/scripts/user-space.ld b/boards/arm/stm32f4/stm32f4discovery/scripts/user-space.ld new file mode 100644 index 0000000000000..24c62636c4680 --- /dev/null +++ b/boards/arm/stm32f4/stm32f4discovery/scripts/user-space.ld @@ -0,0 +1,114 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f4discovery/scripts/user-space.ld + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* NOTE: This depends on the memory.ld script having been included prior to + * this script. + */ + +/* Make sure that the critical memory management functions are in user-space. + * the user heap memory manager will reside in user-space but be usable both + * by kernel- and user-space code + */ + +EXTERN(umm_initialize) +EXTERN(umm_addregion) + +EXTERN(malloc) +EXTERN(realloc) +EXTERN(zalloc) +EXTERN(free) + +OUTPUT_ARCH(arm) +SECTIONS +{ + .userspace : { + KEEP(*(.userspace)) + } > uflash + + .text : { + _stext = ABSOLUTE(.); + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > uflash + + .init_section : { + _sinit = ABSOLUTE(.); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) + _einit = ABSOLUTE(.); + } > uflash + + .ARM.extab : { + *(.ARM.extab*) + } > uflash + + __exidx_start = ABSOLUTE(.); + .ARM.exidx : { + *(.ARM.exidx*) + } > uflash + + __exidx_end = ABSOLUTE(.); + + _eronly = ABSOLUTE(.); + + .data : { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > usram AT > uflash + + .bss : { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(8); + _ebss = ABSOLUTE(.); + } > usram + + /* Stabs debugging sections */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/stm32f4/stm32f4discovery/src/CMakeLists.txt b/boards/arm/stm32f4/stm32f4discovery/src/CMakeLists.txt new file mode 100644 index 0000000000000..36cebfbb8cf77 --- /dev/null +++ b/boards/arm/stm32f4/stm32f4discovery/src/CMakeLists.txt @@ -0,0 +1,226 @@ +# ############################################################################## +# boards/arm/stm32f4/stm32f4discovery/src/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(SRCS stm32_boot.c stm32_bringup.c stm32_spi.c) + +if(CONFIG_ARCH_LEDS) + list(APPEND SRCS stm32_autoleds.c) +else() + list(APPEND SRCS stm32_userleds.c) +endif() + +if(CONFIG_AUDIO_CS43L22) + list(APPEND SRCS stm32_cs43l22.c) +endif() + +if(CONFIG_ARCH_BUTTONS) + list(APPEND SRCS stm32_buttons.c) +endif() + +if(CONFIG_STM32_CAN_CHARDRIVER) + list(APPEND SRCS stm32_can.c) +endif() + +if(CONFIG_STM32_OTGFS) + list(APPEND SRCS stm32_usb.c) +endif() + +if(CONFIG_LCD_ST7567) + list(APPEND SRCS stm32_st7567.c) +endif() + +if(CONFIG_ENC28J60) + list(APPEND SRCS stm32_enc28j60.c) +endif() + +if(CONFIG_LPWAN_SX127X) + list(APPEND SRCS stm32_sx127x.c) +endif() + +if(CONFIG_LCD_MAX7219) + list(APPEND SRCS stm32_max7219.c) +endif() + +if(CONFIG_LCD_ST7032) + list(APPEND SRCS stm32_st7032.c) +endif() + +if(CONFIG_PCA9635PW) + list(APPEND SRCS stm32_pca9635.c) +endif() + +if(CONFIG_STM32_SDIO) + list(APPEND SRCS stm32_sdio.c) +endif() + +if(CONFIG_STM32_ETHMAC) + list(APPEND SRCS stm32_ethernet.c) +endif() + +if(CONFIG_LEDS_MAX7219) + list(APPEND SRCS stm32_max7219_leds.c) +endif() + +if(CONFIG_RGBLED) + list(APPEND SRCS stm32_rgbled.c) +endif() + +if(CONFIG_RTC_DS1307) + list(APPEND SRCS stm32_ds1307.c) +endif() + +if(CONFIG_PWM) + list(APPEND SRCS stm32_pwm.c) +endif() + +if(CONFIG_ARCH_CUSTOM_PMINIT) + list(APPEND SRCS stm32_pm.c) +endif() + +if(CONFIG_PM_BUTTONS) + list(APPEND SRCS stm32_pmbuttons.c) +endif() + +if(CONFIG_ARCH_IDLE_CUSTOM) + list(APPEND SRCS stm32_idle.c) +endif() + +if(CONFIG_STM32_FSMC) + list(APPEND SRCS stm32_extmem.c) + + if(CONFIG_LCD_SSD1289) + list(APPEND SRCS stm32_ssd1289.c) + endif() +endif() + +if(CONFIG_LCD_SSD1351) + list(APPEND SRCS stm32_ssd1351.c) +endif() + +if(CONFIG_LCD_UG2864AMBAG01) + list(APPEND SRCS stm32_ug2864ambag01.c) +endif() + +if(CONFIG_LCD_UG2864HSWEG01) + list(APPEND SRCS stm32_ug2864hsweg01.c) +endif() + +if(CONFIG_TIMER) + list(APPEND SRCS stm32_timer.c) +endif() + +if(CONFIG_STM32_HCIUART) + if(CONFIG_BLUETOOTH_UART) + list(APPEND SRCS stm32_hciuart.c) + endif() +endif() + +if(CONFIG_BOARDCTL_UNIQUEID) + list(APPEND SRCS stm32_uid.c) +endif() + +if(CONFIG_USBMSC) + list(APPEND SRCS stm32_usbmsc.c) +endif() + +if(NOT CONFIG_STM32_ETHMAC) + if(CONFIG_NETDEVICES) + list(APPEND SRCS stm32_netinit.c) + endif() +endif() + +if(CONFIG_MMCSD_SPI) + list(APPEND SRCS stm32_mmcsd.c) +endif() + +if(CONFIG_WL_GS2200M) + list(APPEND SRCS stm32_gs2200m.c) +endif() + +if(CONFIG_LCD_ST7789) + list(APPEND SRCS stm32_st7789.c) +endif() + +if(CONFIG_ADC_HX711) + list(APPEND SRCS stm32_hx711.c) +endif() + +target_sources(board PRIVATE ${SRCS}) + +# Set linker script based on build type +if(CONFIG_BUILD_PROTECTED) + set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/memory.ld" + "${NUTTX_BOARD_DIR}/scripts/kernel-space.ld") +else() + set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/ld.script") +endif() + +# TODO:move this to appropriate arch/toolchain level +set_property( + GLOBAL APPEND + PROPERTY COMPILE_OPTIONS $<$:-fno-strict-aliasing + -fomit-frame-pointer>) + +# TODO: see where to put pic flags set_property(TARGET nuttx APPEND PROPERTY +# NUTTX_COMPILE_OPTIONS $<$>:-fpic -msingle-pic-base +# -mpic-register=r10>) + +# ifeq ($(CONFIG_ARMV7M_TOOLCHAIN_CLANGL),y) ARCHCFLAGS += -nostdlib +# -ffreestanding ARCHCXXFLAGS += -nostdlib -ffreestanding else ARCHCFLAGS += +# -funwind-tables ARCHCXXFLAGS += -fno-rtti -funwind-tables ifneq +# ($(CONFIG_DEBUG_NOOPT),y) ARCHOPTIMIZATION += -fno-strength-reduce endif endif + +if(CONFIG_UNWINDER_ARM) + set_property( + TARGET nuttx + APPEND + PROPERTY NUTTX_COMPILE_OPTIONS -funwind-tables) + set_property(GLOBAL APPEND PROPERTY COMPILE_OPTIONS -fno-strength-reduce) +endif() + +# TODO: nxflat NXFLATLDFLAGS1 = -r -d -warn-common NXFLATLDFLAGS2 = +# $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld +# -no-check-sections LDNXFLATFLAGS = -e main -s 2048 + +# Loadable module definitions + +set_property( + TARGET nuttx + APPEND + PROPERTY NUTTX_ELF_MODULE_COMPILE_OPTIONS -mlong-calls) +set_property( + TARGET nuttx + APPEND + PROPERTY NUTTX_ELF_MODULE_LINK_OPTIONS -r -e module_initialize -T + ${NUTTX_DIR}/libs/libc/elf/gnu-elf.ld) + +# ELF module definitions + +set_property( + TARGET nuttx + APPEND + PROPERTY NUTTX_ELF_APP_COMPILE_OPTIONS -mlong-calls) +set_property( + TARGET nuttx + APPEND + PROPERTY NUTTX_ELF_APP_LINK_OPTIONS -r -e main + -T${NUTTX_BOARD_DIR}/scripts/gnu-elf.ld) diff --git a/boards/arm/stm32f4/stm32f4discovery/src/Make.defs b/boards/arm/stm32f4/stm32f4discovery/src/Make.defs new file mode 100644 index 0000000000000..78fe9c2a0afc2 --- /dev/null +++ b/boards/arm/stm32f4/stm32f4discovery/src/Make.defs @@ -0,0 +1,187 @@ +############################################################################ +# boards/arm/stm32f4/stm32f4discovery/src/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +CSRCS = stm32_boot.c stm32_bringup.c stm32_spi.c + +ifeq ($(CONFIG_ARCH_LEDS),y) +CSRCS += stm32_autoleds.c +else +CSRCS += stm32_userleds.c +endif + +ifeq ($(CONFIG_AUDIO_CS43L22),y) +CSRCS += stm32_cs43l22.c +endif + +ifeq ($(CONFIG_ARCH_BUTTONS),y) +CSRCS += stm32_buttons.c +endif + +ifeq ($(CONFIG_STM32_CAN_CHARDRIVER),y) +CSRCS += stm32_can.c +endif + +ifeq ($(CONFIG_STM32_OTGFS),y) +CSRCS += stm32_usb.c +endif + +ifeq ($(CONFIG_LCD_ST7567),y) +CSRCS += stm32_st7567.c +endif + +ifeq ($(CONFIG_ENC28J60),y) +CSRCS += stm32_enc28j60.c +endif + +ifeq ($(CONFIG_NET_W5500),y) +CSRCS += stm32_w5500.c +endif + +ifeq ($(CONFIG_LPWAN_SX127X),y) +CSRCS += stm32_sx127x.c +endif + +ifeq ($(CONFIG_LCD_MAX7219),y) +CSRCS += stm32_max7219.c +endif + +ifeq ($(CONFIG_LCD_ST7032),y) +CSRCS += stm32_st7032.c +endif + +ifeq ($(CONFIG_PCA9635PW),y) +CSRCS += stm32_pca9635.c +endif + +ifeq ($(CONFIG_STM32_SDIO),y) +CSRCS += stm32_sdio.c +endif + +ifeq ($(CONFIG_STM32_ETHMAC),y) +CSRCS += stm32_ethernet.c +endif + +ifeq ($(CONFIG_LEDS_MAX7219),y) +CSRCS += stm32_max7219_leds.c +endif + +ifeq ($(CONFIG_RGBLED),y) +CSRCS += stm32_rgbled.c +endif + +ifeq ($(CONFIG_PWM),y) +CSRCS += stm32_pwm.c +endif + +ifeq ($(CONFIG_CAPTURE),y) +CSRCS += stm32_capture.c +endif + +ifeq ($(CONFIG_ARCH_CUSTOM_PMINIT),y) +CSRCS += stm32_pm.c +endif + +ifeq ($(CONFIG_PM_BUTTONS),y) +CSRCS += stm32_pmbuttons.c +endif + +ifeq ($(CONFIG_ARCH_IDLE_CUSTOM),y) +CSRCS += stm32_idle.c +endif + +ifeq ($(CONFIG_STM32_FSMC),y) +CSRCS += stm32_extmem.c + +ifeq ($(CONFIG_LCD_SSD1289),y) +CSRCS += stm32_ssd1289.c +endif +endif + +ifeq ($(CONFIG_LCD_APA102),y) +CSRCS += stm32_apa102.c +endif + +ifeq ($(CONFIG_LCD_SSD1351),y) +CSRCS += stm32_ssd1351.c +endif + +ifeq ($(CONFIG_LCD_UG2864AMBAG01),y) +CSRCS += stm32_ug2864ambag01.c +endif + +ifeq ($(CONFIG_LCD_UG2864HSWEG01),y) +CSRCS += stm32_ug2864hsweg01.c +endif + +ifeq ($(CONFIG_TIMER),y) +CSRCS += stm32_timer.c +endif + +ifeq ($(CONFIG_STM32_HCIUART),y) +ifeq ($(CONFIG_BLUETOOTH_UART),y) +CSRCS += stm32_hciuart.c +endif +endif + +ifeq ($(CONFIG_BOARDCTL_UNIQUEID),y) +CSRCS += stm32_uid.c +endif + +ifeq ($(CONFIG_USBMSC),y) +CSRCS += stm32_usbmsc.c +endif + +ifneq ($(CONFIG_STM32_ETHMAC),y) +ifeq ($(CONFIG_NETDEVICES),y) +CSRCS += stm32_netinit.c +endif +endif + +ifeq ($(CONFIG_MMCSD_SPI),y) +CSRCS += stm32_mmcsd.c +endif + +ifeq ($(CONFIG_WL_GS2200M),y) +CSRCS += stm32_gs2200m.c +endif + +ifeq ($(CONFIG_LCD_ST7789),y) +CSRCS += stm32_st7789.c +endif + +ifeq ($(CONFIG_INPUT_DJOYSTICK),y) + CSRCS += stm32_djoystick.c +endif + +ifeq ($(CONFIG_USBDEV_COMPOSITE),y) + CSRCS += stm32_composite.c +endif + +ifeq ($(CONFIG_ADC_HX711),y) +CSRCS += stm32_hx711.c +endif + +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32f4/stm32f4discovery/src/stm32_apa102.c b/boards/arm/stm32f4/stm32f4discovery/src/stm32_apa102.c new file mode 100644 index 0000000000000..ee6b826ed9609 --- /dev/null +++ b/boards/arm/stm32f4/stm32f4discovery/src/stm32_apa102.c @@ -0,0 +1,110 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f4discovery/src/stm32_apa102.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include "stm32_gpio.h" +#include "stm32_spi.h" +#include "stm32f4discovery.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define LCD_SPI_PORTNO 1 /* On SPI1 */ + +#ifndef CONFIG_LCD_CONTRAST +# define CONFIG_LCD_CONTRAST 60 +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +struct spi_dev_s *g_spidev; +struct lcd_dev_s *g_lcddev; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_lcd_initialize + ****************************************************************************/ + +int board_lcd_initialize(void) +{ + g_spidev = stm32_spibus_initialize(LCD_SPI_PORTNO); + + if (!g_spidev) + { + lcderr("ERROR: Failed to initialize SPI port %d\n", LCD_SPI_PORTNO); + return -ENODEV; + } + + return OK; +} + +/**************************************************************************** + * Name: board_lcd_getdev + ****************************************************************************/ + +struct lcd_dev_s *board_lcd_getdev(int lcddev) +{ + g_lcddev = apa102_initialize(g_spidev, lcddev); + if (!g_lcddev) + { + lcderr("ERROR: Failed to bind SPI port 1 to LCD %d\n", lcddev); + } + else + { + lcdinfo("SPI port 1 bound to LCD %d\n", lcddev); + + return g_lcddev; + } + + return NULL; +} + +/**************************************************************************** + * Name: board_lcd_uninitialize + ****************************************************************************/ + +void board_lcd_uninitialize(void) +{ + /* TO-FIX */ +} diff --git a/boards/arm/stm32f4/stm32f4discovery/src/stm32_autoleds.c b/boards/arm/stm32f4/stm32f4discovery/src/stm32_autoleds.c new file mode 100644 index 0000000000000..ef69cc6c3ab7a --- /dev/null +++ b/boards/arm/stm32f4/stm32f4discovery/src/stm32_autoleds.c @@ -0,0 +1,232 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f4discovery/src/stm32_autoleds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32.h" +#include "stm32f4discovery.h" + +#ifdef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* The following definitions map the encoded LED setting to GPIO settings */ + +#define STM32F4_LED1 (1 << 0) +#define STM32F4_LED2 (1 << 1) +#define STM32F4_LED3 (1 << 2) +#define STM32F4_LED4 (1 << 3) + +#define ON_SETBITS_SHIFT (0) +#define ON_CLRBITS_SHIFT (4) +#define OFF_SETBITS_SHIFT (8) +#define OFF_CLRBITS_SHIFT (12) + +#define ON_BITS(v) ((v) & 0xff) +#define OFF_BITS(v) (((v) >> 8) & 0x0ff) +#define SETBITS(b) ((b) & 0x0f) +#define CLRBITS(b) (((b) >> 4) & 0x0f) + +#define ON_SETBITS(v) (SETBITS(ON_BITS(v)) +#define ON_CLRBITS(v) (CLRBITS(ON_BITS(v)) +#define OFF_SETBITS(v) (SETBITS(OFF_BITS(v)) +#define OFF_CLRBITS(v) (CLRBITS(OFF_BITS(v)) + +#define LED_STARTED_ON_SETBITS ((STM32F4_LED1) << ON_SETBITS_SHIFT) +#define LED_STARTED_ON_CLRBITS ((STM32F4_LED2|STM32F4_LED3|STM32F4_LED4) << ON_CLRBITS_SHIFT) +#define LED_STARTED_OFF_SETBITS (0 << OFF_SETBITS_SHIFT) +#define LED_STARTED_OFF_CLRBITS ((STM32F4_LED1|STM32F4_LED2|STM32F4_LED3|STM32F4_LED4) << OFF_CLRBITS_SHIFT) + +#define LED_HEAPALLOCATE_ON_SETBITS ((STM32F4_LED2) << ON_SETBITS_SHIFT) +#define LED_HEAPALLOCATE_ON_CLRBITS ((STM32F4_LED1|STM32F4_LED3|STM32F4_LED4) << ON_CLRBITS_SHIFT) +#define LED_HEAPALLOCATE_OFF_SETBITS ((STM32F4_LED1) << OFF_SETBITS_SHIFT) +#define LED_HEAPALLOCATE_OFF_CLRBITS ((STM32F4_LED2|STM32F4_LED3|STM32F4_LED4) << OFF_CLRBITS_SHIFT) + +#define LED_IRQSENABLED_ON_SETBITS ((STM32F4_LED1|STM32F4_LED2) << ON_SETBITS_SHIFT) +#define LED_IRQSENABLED_ON_CLRBITS ((STM32F4_LED3|STM32F4_LED4) << ON_CLRBITS_SHIFT) +#define LED_IRQSENABLED_OFF_SETBITS ((STM32F4_LED2) << OFF_SETBITS_SHIFT) +#define LED_IRQSENABLED_OFF_CLRBITS ((STM32F4_LED1|STM32F4_LED3|STM32F4_LED4) << OFF_CLRBITS_SHIFT) + +#define LED_STACKCREATED_ON_SETBITS ((STM32F4_LED3) << ON_SETBITS_SHIFT) +#define LED_STACKCREATED_ON_CLRBITS ((STM32F4_LED1|STM32F4_LED2|STM32F4_LED4) << ON_CLRBITS_SHIFT) +#define LED_STACKCREATED_OFF_SETBITS ((STM32F4_LED1|STM32F4_LED2) << OFF_SETBITS_SHIFT) +#define LED_STACKCREATED_OFF_CLRBITS ((STM32F4_LED3|STM32F4_LED4) << OFF_CLRBITS_SHIFT) + +#define LED_INIRQ_ON_SETBITS ((STM32F4_LED1) << ON_SETBITS_SHIFT) +#define LED_INIRQ_ON_CLRBITS ((0) << ON_CLRBITS_SHIFT) +#define LED_INIRQ_OFF_SETBITS ((0) << OFF_SETBITS_SHIFT) +#define LED_INIRQ_OFF_CLRBITS ((STM32F4_LED1) << OFF_CLRBITS_SHIFT) + +#define LED_SIGNAL_ON_SETBITS ((STM32F4_LED2) << ON_SETBITS_SHIFT) +#define LED_SIGNAL_ON_CLRBITS ((0) << ON_CLRBITS_SHIFT) +#define LED_SIGNAL_OFF_SETBITS ((0) << OFF_SETBITS_SHIFT) +#define LED_SIGNAL_OFF_CLRBITS ((STM32F4_LED2) << OFF_CLRBITS_SHIFT) + +#define LED_ASSERTION_ON_SETBITS ((STM32F4_LED4) << ON_SETBITS_SHIFT) +#define LED_ASSERTION_ON_CLRBITS ((0) << ON_CLRBITS_SHIFT) +#define LED_ASSERTION_OFF_SETBITS ((0) << OFF_SETBITS_SHIFT) +#define LED_ASSERTION_OFF_CLRBITS ((STM32F4_LED4) << OFF_CLRBITS_SHIFT) + +#define LED_PANIC_ON_SETBITS ((STM32F4_LED4) << ON_SETBITS_SHIFT) +#define LED_PANIC_ON_CLRBITS ((0) << ON_CLRBITS_SHIFT) +#define LED_PANIC_OFF_SETBITS ((0) << OFF_SETBITS_SHIFT) +#define LED_PANIC_OFF_CLRBITS ((STM32F4_LED4) << OFF_CLRBITS_SHIFT) + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static const uint16_t g_ledbits[8] = +{ + (LED_STARTED_ON_SETBITS | LED_STARTED_ON_CLRBITS | + LED_STARTED_OFF_SETBITS | LED_STARTED_OFF_CLRBITS), + + (LED_HEAPALLOCATE_ON_SETBITS | LED_HEAPALLOCATE_ON_CLRBITS | + LED_HEAPALLOCATE_OFF_SETBITS | LED_HEAPALLOCATE_OFF_CLRBITS), + + (LED_IRQSENABLED_ON_SETBITS | LED_IRQSENABLED_ON_CLRBITS | + LED_IRQSENABLED_OFF_SETBITS | LED_IRQSENABLED_OFF_CLRBITS), + + (LED_STACKCREATED_ON_SETBITS | LED_STACKCREATED_ON_CLRBITS | + LED_STACKCREATED_OFF_SETBITS | LED_STACKCREATED_OFF_CLRBITS), + + (LED_INIRQ_ON_SETBITS | LED_INIRQ_ON_CLRBITS | + LED_INIRQ_OFF_SETBITS | LED_INIRQ_OFF_CLRBITS), + + (LED_SIGNAL_ON_SETBITS | LED_SIGNAL_ON_CLRBITS | + LED_SIGNAL_OFF_SETBITS | LED_SIGNAL_OFF_CLRBITS), + + (LED_ASSERTION_ON_SETBITS | LED_ASSERTION_ON_CLRBITS | + LED_ASSERTION_OFF_SETBITS | LED_ASSERTION_OFF_CLRBITS), + + (LED_PANIC_ON_SETBITS | LED_PANIC_ON_CLRBITS | + LED_PANIC_OFF_SETBITS | LED_PANIC_OFF_CLRBITS) +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +static inline void led_clrbits(unsigned int clrbits) +{ + if ((clrbits & STM32F4_LED1) != 0) + { + stm32_gpiowrite(GPIO_LED1, false); + } + + if ((clrbits & STM32F4_LED2) != 0) + { + stm32_gpiowrite(GPIO_LED2, false); + } + + if ((clrbits & STM32F4_LED3) != 0) + { + stm32_gpiowrite(GPIO_LED3, false); + } + + if ((clrbits & STM32F4_LED4) != 0) + { + stm32_gpiowrite(GPIO_LED4, false); + } +} + +static inline void led_setbits(unsigned int setbits) +{ + if ((setbits & STM32F4_LED1) != 0) + { + stm32_gpiowrite(GPIO_LED1, true); + } + + if ((setbits & STM32F4_LED2) != 0) + { + stm32_gpiowrite(GPIO_LED2, true); + } + + if ((setbits & STM32F4_LED3) != 0) + { + stm32_gpiowrite(GPIO_LED3, true); + } + + if ((setbits & STM32F4_LED4) != 0) + { + stm32_gpiowrite(GPIO_LED4, true); + } +} + +static void led_setonoff(unsigned int bits) +{ + led_clrbits(CLRBITS(bits)); + led_setbits(SETBITS(bits)); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_autoled_initialize + ****************************************************************************/ + +void board_autoled_initialize(void) +{ + /* Configure LED1-4 GPIOs for output */ + + stm32_configgpio(GPIO_LED1); + stm32_configgpio(GPIO_LED2); + stm32_configgpio(GPIO_LED3); + stm32_configgpio(GPIO_LED4); +} + +/**************************************************************************** + * Name: board_autoled_on + ****************************************************************************/ + +void board_autoled_on(int led) +{ + led_setonoff(ON_BITS(g_ledbits[led])); +} + +/**************************************************************************** + * Name: board_autoled_off + ****************************************************************************/ + +void board_autoled_off(int led) +{ + led_setonoff(OFF_BITS(g_ledbits[led])); +} + +#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32f4/stm32f4discovery/src/stm32_boot.c b/boards/arm/stm32f4/stm32f4discovery/src/stm32_boot.c new file mode 100644 index 0000000000000..1ea43384fbf18 --- /dev/null +++ b/boards/arm/stm32f4/stm32f4discovery/src/stm32_boot.c @@ -0,0 +1,118 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f4discovery/src/stm32_boot.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include +#include + +#include "arm_internal.h" +#include "nvic.h" +#include "itm.h" + +#include "stm32.h" +#include "stm32f4discovery.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_boardinitialize + * + * Description: + * All STM32 architectures must provide the following entry point. This + * entry point is called early in the initialization -- after all memory + * has been configured and mapped but before any devices have been + * initialized. + * + ****************************************************************************/ + +void stm32_boardinitialize(void) +{ +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || defined(CONFIG_STM32_SPI3) + /* Configure SPI chip selects if 1) SPI is not disabled, and 2) the weak + * function stm32_spidev_initialize() has been brought into the link. + */ + + if (stm32_spidev_initialize) + { + stm32_spidev_initialize(); + } +#endif + +#ifdef CONFIG_STM32_OTGFS + /* Initialize USB if the 1) OTG FS controller is in the configuration and + * 2) disabled, and 3) the weak function stm32_usbinitialize() has been + * brought into the build. Presumably either CONFIG_USBDEV or + * CONFIG_USBHOST is also selected. + */ + + if (stm32_usbinitialize) + { + stm32_usbinitialize(); + } +#endif + +#ifdef HAVE_NETMONITOR + /* Configure board resources to support networking. */ + + if (stm32_netinitialize) + { + stm32_netinitialize(); + } +#endif + +#ifdef CONFIG_ARCH_LEDS + /* Configure on-board LEDs if LED support has been selected. */ + + board_autoled_initialize(); +#endif +} + +/**************************************************************************** + * Name: board_late_initialize + * + * Description: + * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_late_initialize(). board_late_initialize() will be + * called immediately after up_initialize() is called and just before the + * initial application is started. This additional initialization phase + * may be used, for example, to initialize board-specific device drivers. + * + ****************************************************************************/ + +#ifdef CONFIG_BOARD_LATE_INITIALIZE +void board_late_initialize(void) +{ + /* Perform board-specific initialization */ + + stm32_bringup(); +} +#endif diff --git a/boards/arm/stm32f4/stm32f4discovery/src/stm32_bringup.c b/boards/arm/stm32f4/stm32f4discovery/src/stm32_bringup.c new file mode 100644 index 0000000000000..16d4cbc15f25d --- /dev/null +++ b/boards/arm/stm32f4/stm32f4discovery/src/stm32_bringup.c @@ -0,0 +1,706 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f4discovery/src/stm32_bringup.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include + +#ifdef CONFIG_USBMONITOR +# include +#endif + +#include "stm32.h" +#ifdef CONFIG_STM32_ROMFS +# include "stm32_romfs.h" +#endif + +#ifdef CONFIG_STM32_OTGFS +# include "stm32_usbhost.h" +#endif + +#ifdef CONFIG_INPUT_BUTTONS +# include +#endif + +#ifdef CONFIG_USERLED +# include +#endif + +#ifdef CONFIG_RNDIS +# include +#endif + +#ifdef CONFIG_SENSORS_APDS9960 +#include "stm32_apds9960.h" +#endif + +#ifdef CONFIG_SENSORS_MT6816 +#include "stm32_mt6816.h" +#endif + +#ifdef CONFIG_INPUT_MPR121_KEYPAD +#include "stm32_mpr121.h" +#endif + +#ifdef CONFIG_CL_MFRC522 +#include "stm32_mfrc522.h" +#endif + +#include "stm32f4discovery.h" + +/* Conditional logic in stm32f4discovery.h will determine if certain features + * are supported. Tests for these features need to be made after including + * stm32f4discovery.h. + */ + +#ifdef HAVE_RTC_DRIVER +# include +# include "stm32_rtc.h" +#endif + +/* The following are includes from board-common logic */ + +#ifdef CONFIG_SENSORS_BMP180 +#include "stm32_bmp180.h" +#endif + +#ifdef CONFIG_RTC_DS1307 +#include "stm32_ds1307.h" +#endif + +#ifdef CONFIG_SENSORS_MS56XX +#include "stm32_ms5611.h" +#endif + +#ifdef CONFIG_SENSORS_MAX6675 +#include "stm32_max6675.h" +#endif + +#ifdef CONFIG_INPUT_NUNCHUCK +#include "stm32_nunchuck.h" +#endif + +#ifdef CONFIG_INPUT_SBUTTON +#include "board_sbutton.h" +#endif + +#ifdef CONFIG_INPUT_KMATRIX +#include "stm32_kmatrix_gpio.h" +#endif + +#ifdef CONFIG_INPUT_KMATRIX_I2C +#include "stm32_kmatrix_i2c.h" +#endif + +#ifdef CONFIG_SENSORS_ZEROCROSS +#include "stm32_zerocross.h" +#endif + +#ifdef CONFIG_SENSORS_QENCODER +#include "board_qencoder.h" +#endif + +#ifdef CONFIG_SENSORS_BH1750FVI +#include "stm32_bh1750.h" +#endif + +#ifdef CONFIG_LIS3DSH +#include "stm32_lis3dsh.h" +#endif + +#ifdef CONFIG_LCD_BACKPACK +#include "stm32_lcd_backpack.h" +#endif + +#ifdef CONFIG_SENSORS_MAX31855 +#include "stm32_max31855.h" +#endif + +#ifdef CONFIG_SENSORS_MLX90614 +#include "stm32_mlx90614.h" +#endif + +#ifdef CONFIG_SENSORS_XEN1210 +#include "stm32_xen1210.h" +#endif + +#ifdef CONFIG_USBADB +# include +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_i2c_register + * + * Description: + * Register one I2C drivers for the I2C tool. + * + ****************************************************************************/ + +#if defined(CONFIG_I2C) && defined(CONFIG_SYSTEM_I2CTOOL) +static void stm32_i2c_register(int bus) +{ + struct i2c_master_s *i2c; + int ret; + + i2c = stm32_i2cbus_initialize(bus); + if (i2c == NULL) + { + syslog(LOG_ERR, "ERROR: Failed to get I2C%d interface\n", bus); + } + else + { + ret = i2c_register(i2c, bus); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to register I2C%d driver: %d\n", + bus, ret); + stm32_i2cbus_uninitialize(i2c); + } + } +} +#endif + +/**************************************************************************** + * Name: stm32_i2ctool + * + * Description: + * Register I2C drivers for the I2C tool. + * + ****************************************************************************/ + +#if defined(CONFIG_I2C) && defined(CONFIG_SYSTEM_I2CTOOL) +static void stm32_i2ctool(void) +{ + stm32_i2c_register(1); +#if 0 + stm32_i2c_register(1); + stm32_i2c_register(2); +#endif +} +#else +# define stm32_i2ctool() +#endif + +/**************************************************************************** + * Name: stm32_bringup + * + * Description: + * Perform architecture-specific initialization + * + * CONFIG_BOARD_LATE_INITIALIZE=y : + * Called from board_late_initialize(). + * + ****************************************************************************/ + +int stm32_bringup(void) +{ +#ifdef HAVE_RTC_DRIVER + struct rtc_lowerhalf_s *lower; +#endif + int ret = OK; + +#if defined(CONFIG_I2C) && defined(CONFIG_SYSTEM_I2CTOOL) + stm32_i2ctool(); +#endif + +#ifdef CONFIG_SENSORS_BMP180 + /* Initialize the BMP180 pressure sensor. */ + + ret = board_bmp180_initialize(0, 1); + if (ret < 0) + { + syslog(LOG_ERR, "Failed to initialize BMP180, error %d\n", ret); + return ret; + } +#endif + +#ifdef CONFIG_SENSORS_MS56XX + /* Initialize the MS5611 pressure sensor. */ + + ret = board_ms5611_initialize(0, 1); + if (ret < 0) + { + syslog(LOG_ERR, "Failed to initialize MS5611, error %d\n", ret); + return ret; + } +#endif + +#ifdef CONFIG_SENSORS_BH1750FVI + ret = board_bh1750_initialize(0, 1); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_bh1750initialize() failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_SENSORS_ZEROCROSS + /* Configure the zero-crossing driver */ + + board_zerocross_initialize(0); +#endif + +#ifdef CONFIG_SENSORS_MT6816 + /* Initialize MT6816 as /dev/qe0 on SPI1 */ + + ret = board_mt6816_initialize(0, 1); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: board_mt6816_initialize failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_LEDS_MAX7219 + ret = stm32_max7219init("/dev/numdisp0"); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: max7219_leds_register failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_INPUT_MPR121_KEYPAD + /* Initialize MPR121 using I2C1 bus to /dev/keypad0 */ + + ret = board_mpr121_initialize(0, 1); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: board_mpr121_initialize failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_LCD_ST7032 + ret = stm32_st7032init("/dev/slcd0"); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: st7032_register failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_RGBLED + /* Configure the RGB LED driver */ + + stm32_rgbled_setup(); +#endif + +#if defined(CONFIG_PCA9635PW) + /* Initialize the PCA9635 chip */ + + ret = stm32_pca9635_initialize(); + if (ret < 0) + { + serr("ERROR: stm32_pca9635_initialize failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_VIDEO_FB + /* Initialize and register the framebuffer driver */ + + ret = fb_register(0, 0); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: fb_register() failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_LCD_BACKPACK + /* slcd:0, i2c:1, rows=2, cols=16 */ + + ret = board_lcd_backpack_init(0, 1, 2, 16); + if (ret < 0) + { + syslog(LOG_ERR, "Failed to initialize PCF8574 LCD, error %d\n", ret); + return ret; + } +#endif + +#ifdef HAVE_SDIO + /* Initialize the SDIO block driver */ + + ret = stm32_sdio_initialize(); + if (ret != OK) + { + ferr("ERROR: Failed to initialize MMC/SD driver: %d\n", ret); + return ret; + } +#endif + +#ifdef CONFIG_MMCSD_SPI + /* Initialize the MMC/SD SPI driver (SPI2 is used) */ + + ret = stm32_mmcsd_initialize(2, CONFIG_NSH_MMCSDMINOR); + if (ret < 0) + { + syslog(LOG_ERR, "Failed to initialize SD slot %d: %d\n", + CONFIG_NSH_MMCSDMINOR, ret); + } +#endif + +#ifdef HAVE_USBHOST + /* Initialize USB host operation. stm32_usbhost_initialize() starts a + * thread will monitor for USB connection and disconnection events. + */ + + ret = stm32_usbhost_initialize(); + if (ret != OK) + { + uerr("ERROR: Failed to initialize USB host: %d\n", ret); + return ret; + } +#endif + +#ifdef HAVE_USBMONITOR + /* Start the USB Monitor */ + + ret = usbmonitor_start(); + if (ret != OK) + { + uerr("ERROR: Failed to start USB monitor: %d\n", ret); + return ret; + } +#endif + +#ifdef CONFIG_PWM + /* Initialize PWM and register the PWM device. */ + + ret = stm32_pwm_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_pwm_setup() failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_TIMER + /* Initialize TIMER and register the TIMER device. */ + + ret = stm32_timer_driver_setup("/dev/timer0", CONFIG_STM32F4DISCO_TIMER); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_timer_driver_setup() failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_CAPTURE + /* Initialize Capture and register the Capture driver. */ + + ret = stm32_capture_setup("/dev/capture0"); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_capture_setup failed: %d\n", ret); + return ret; + } +#endif + +#ifdef CONFIG_STM32_CAN_CHARDRIVER + /* Initialize CAN and register the CAN driver. */ + + ret = stm32_can_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_can_setup failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_INPUT_BUTTONS + /* Register the BUTTON driver */ + + ret = btn_lower_initialize("/dev/buttons"); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: btn_lower_initialize() failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_INPUT_DJOYSTICK + ret = stm32_djoy_initialize(); + if (ret != OK) + { + syslog(LOG_ERR, "Failed to register djoystick driver: %d\n", ret); + } +#endif + +#ifdef CONFIG_INPUT_KMATRIX + /* Initialize and register the keyboard matrix driver */ + + ret = board_kmatrix_initialize(CONFIG_INPUT_KMATRIX_DEVPATH); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: board_kmatrix_initialize() failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_INPUT_KMATRIX_I2C + /* Initialize and register the keyboard matrix driver via I2C expander */ + + ret = board_kmatrix_i2c_initialize("/dev/kbd0"); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: board_kmatrix_i2c_initialize() failed: %d\n", + ret); + } +#endif + +#ifdef CONFIG_INPUT_NUNCHUCK + /* Register the Nunchuck driver */ + + ret = board_nunchuck_initialize(0, 1); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: nunchuck_initialize() failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_SENSORS_MLX90614 + ret = board_mlx90614_initialize(0, 1); + if (ret < 0) + { + syslog(LOG_ERR, "Failed to initialize MLX90614, error %d\n", ret); + return ret; + } +#endif + +#if defined(CONFIG_STM32_QE) && defined(CONFIG_SENSORS_QENCODER) + /* Initialize and register the qencoder driver */ + + ret = board_qencoder_initialize(0, CONFIG_STM32F4DISCO_QETIMER); + if (ret != OK) + { + syslog(LOG_ERR, + "ERROR: Failed to register the qencoder: %d\n", + ret); + return ret; + } +#endif + +#ifdef CONFIG_USERLED + /* Register the LED driver */ + + ret = userled_lower_initialize("/dev/userleds"); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: userled_lower_initialize() failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_INPUT_SBUTTON + /* Register the Single Button Dual Action driver */ + + ret = board_sbutton_initialize(0); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: board_sbtn_initialize() failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_SENSORS_APDS9960 + /* Register the APDS-9960 gesture sensor */ + + ret = board_apds9960_initialize(0, 1); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: board_apds9960_initialize() failed: %d\n", + ret); + } +#endif + +#ifdef CONFIG_RTC_DS1307 + ret = board_ds1307_initialize(1); + if (ret < 0) + { + syslog(LOG_ERR, "Failed to initialize DS1307 RTC driver: %d\n", ret); + return ret; + } +#endif + +#ifdef HAVE_RTC_DRIVER + /* Instantiate the STM32 lower-half RTC driver */ + + lower = stm32_rtc_lowerhalf(); + if (!lower) + { + serr("ERROR: Failed to instantiate the RTC lower-half driver\n"); + return -ENOMEM; + } + else + { + /* Bind the lower half driver and register the combined RTC driver + * as /dev/rtc0 + */ + + ret = rtc_initialize(0, lower); + if (ret < 0) + { + serr("ERROR: Failed to bind/register the RTC driver: %d\n", ret); + return ret; + } + } +#endif + +#ifdef HAVE_CS43L22 + /* Configure CS43L22 audio */ + + ret = stm32_cs43l22_initialize(1); + if (ret != OK) + { + serr("Failed to initialize CS43L22 audio: %d\n", ret); + } +#endif + +#ifdef CONFIG_SENSORS_MAX31855 + /* Register device 0 on spi channel 2 */ + + ret = board_max31855_initialize(0, 2); + if (ret < 0) + { + serr("ERROR: stm32_max31855initialize failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_SENSORS_MAX6675 + ret = board_max6675_initialize(0, 2); + if (ret < 0) + { + serr("ERROR: stm32_max6675initialize failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_FS_PROCFS + /* Mount the procfs file system */ + + ret = nx_mount(NULL, STM32_PROCFS_MOUNTPOINT, "procfs", 0, NULL); + if (ret < 0) + { + serr("ERROR: Failed to mount procfs at %s: %d\n", + STM32_PROCFS_MOUNTPOINT, ret); + } +#endif + +#ifdef CONFIG_FS_TMPFS + /* Mount the tmpfs file system */ + + ret = nx_mount(NULL, CONFIG_LIBC_TMPDIR, "tmpfs", 0, NULL); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to mount tmpfs at %s: %d\n", + CONFIG_LIBC_TMPDIR, ret); + } +#endif + +#ifdef CONFIG_STM32_ROMFS + ret = stm32_romfs_initialize(); + if (ret < 0) + { + serr("ERROR: Failed to mount romfs at %s: %d\n", + CONFIG_STM32_ROMFS_MOUNTPOINT, ret); + } +#endif + +#ifdef CONFIG_SENSORS_XEN1210 + ret = board_xen1210_initialize(0, 1); + if (ret < 0) + { + serr("ERROR: xen1210_archinitialize failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_LIS3DSH + /* Create a lis3dsh driver instance fitting the chip built into + * stm32f4discovery + */ + + ret = board_lis3dsh_initialize(0, 1); + if (ret < 0) + { + serr("ERROR: Failed to initialize LIS3DSH driver: %d\n", ret); + } +#endif + +#ifdef HAVE_HCIUART + ret = hciuart_dev_initialize(); + if (ret < 0) + { + serr("ERROR: Failed to initialize HCI UART driver: %d\n", ret); + } +#endif + +#if defined(CONFIG_RNDIS) && !defined(CONFIG_RNDIS_COMPOSITE) + uint8_t mac[6]; + mac[0] = 0xa0; /* TODO */ + mac[1] = (CONFIG_NETINIT_MACADDR_2 >> (8 * 0)) & 0xff; + mac[2] = (CONFIG_NETINIT_MACADDR_1 >> (8 * 3)) & 0xff; + mac[3] = (CONFIG_NETINIT_MACADDR_1 >> (8 * 2)) & 0xff; + mac[4] = (CONFIG_NETINIT_MACADDR_1 >> (8 * 1)) & 0xff; + mac[5] = (CONFIG_NETINIT_MACADDR_1 >> (8 * 0)) & 0xff; + usbdev_rndis_initialize(mac); +#endif + +#ifdef CONFIG_WL_GS2200M + ret = stm32_gs2200m_initialize("/dev/gs2200m", 3); + if (ret < 0) + { + serr("ERROR: Failed to initialize GS2200M: %d\n", ret); + } +#endif + +#ifdef CONFIG_LPWAN_SX127X + ret = stm32_lpwaninitialize(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to initialize wireless driver:" + " %d\n", ret); + } +#endif /* CONFIG_LPWAN_SX127X */ + +#ifdef CONFIG_USBADB + usbdev_adb_initialize(); +#endif + +#ifdef CONFIG_CL_MFRC522 + ret = stm32_mfrc522initialize("/dev/rfid0"); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_mfrc522initialize() failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_ADC_HX711 + ret = stm32_hx711_initialize(); + if (ret != OK) + { + aerr("ERROR: Failed to initialize hx711: %d\n", ret); + } +#endif + + return ret; +} diff --git a/boards/arm/stm32f4/stm32f4discovery/src/stm32_buttons.c b/boards/arm/stm32f4/stm32f4discovery/src/stm32_buttons.c new file mode 100644 index 0000000000000..db8e7e3f5e0ad --- /dev/null +++ b/boards/arm/stm32f4/stm32f4discovery/src/stm32_buttons.c @@ -0,0 +1,151 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f4discovery/src/stm32_buttons.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include +#include + +#include "stm32.h" +#include "stm32f4discovery.h" + +#ifdef CONFIG_ARCH_BUTTONS + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* Pin configuration for each STM32F4 Discovery button. This array is indexed + * by the BUTTON_* definitions in board.h + */ + +static const uint32_t g_buttons[NUM_BUTTONS] = +{ + GPIO_BTN_USER +}; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_button_initialize + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. + * + ****************************************************************************/ + +uint32_t board_button_initialize(void) +{ + int i; + + /* Configure the GPIO pins as inputs. NOTE that EXTI interrupts are + * configured for all pins. + */ + + for (i = 0; i < NUM_BUTTONS; i++) + { + stm32_configgpio(g_buttons[i]); + } + + return NUM_BUTTONS; +} + +/**************************************************************************** + * Name: board_buttons + ****************************************************************************/ + +uint32_t board_buttons(void) +{ + uint32_t ret = 0; + int i; + + /* Check that state of each key */ + + for (i = 0; i < NUM_BUTTONS; i++) + { + /* A LOW value means that the key is pressed. */ + + bool released = stm32_gpioread(g_buttons[i]); + + /* Accumulate the set of depressed (not released) keys */ + + if (!released) + { + ret |= (1 << i); + } + } + + return ret; +} + +/**************************************************************************** + * Button support. + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. + * + * After board_button_initialize() has been called, board_buttons() may be + * called to collect the state of all buttons. board_buttons() returns an + * 32-bit bit set with each bit associated with a button. See the + * BUTTON_*_BIT definitions in board.h for the meaning of each bit. + * + * board_button_irq() may be called to register an interrupt handler that + * will be called when a button is depressed or released. The ID value is a + * button enumeration value that uniquely identifies a button resource. See + * the BUTTON_* definitions in board.h for the meaning of enumeration + * value. + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_IRQBUTTONS +int board_button_irq(int id, xcpt_t irqhandler, void *arg) +{ + int ret = -EINVAL; + + /* The following should be atomic */ + + if (id >= MIN_IRQBUTTON && id <= MAX_IRQBUTTON) + { + ret = stm32_gpiosetevent(g_buttons[id], true, true, true, + irqhandler, arg); + } + + return ret; +} +#endif +#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/stm32f4/stm32f4discovery/src/stm32_can.c b/boards/arm/stm32f4/stm32f4discovery/src/stm32_can.c new file mode 100644 index 0000000000000..18a72d54f8a30 --- /dev/null +++ b/boards/arm/stm32f4/stm32f4discovery/src/stm32_can.c @@ -0,0 +1,102 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f4discovery/src/stm32_can.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32.h" +#include "stm32_can.h" +#include "stm32f4discovery.h" + +#ifdef CONFIG_CAN + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +#if defined(CONFIG_STM32_CAN1) && defined(CONFIG_STM32_CAN2) +# warning "Both CAN1 and CAN2 are enabled. Assuming only CAN1." +# undef CONFIG_STM32_CAN2 +#endif + +#ifdef CONFIG_STM32_CAN1 +# define CAN_PORT 1 +#else +# define CAN_PORT 2 +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_can_setup + * + * Description: + * Initialize CAN and register the CAN device + * + ****************************************************************************/ + +int stm32_can_setup(void) +{ +#if defined(CONFIG_STM32_CAN1) || defined(CONFIG_STM32_CAN2) + struct can_dev_s *can; + int ret; + + /* Call stm32_caninitialize() to get an instance of the CAN interface */ + + can = stm32_caninitialize(CAN_PORT); + if (can == NULL) + { + canerr("ERROR: Failed to get CAN interface\n"); + return -ENODEV; + } + + /* Register the CAN driver at "/dev/can0" */ + + ret = can_register("/dev/can0", can); + if (ret < 0) + { + canerr("ERROR: can_register failed: %d\n", ret); + return ret; + } + + return OK; +#else + return -ENODEV; +#endif +} + +#endif /* CONFIG_CAN */ diff --git a/boards/arm/stm32f4/stm32f4discovery/src/stm32_capture.c b/boards/arm/stm32f4/stm32f4discovery/src/stm32_capture.c new file mode 100644 index 0000000000000..f3e15b471d022 --- /dev/null +++ b/boards/arm/stm32f4/stm32f4discovery/src/stm32_capture.c @@ -0,0 +1,112 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f4discovery/src/stm32_capture.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include +#include +#include + +#include "chip.h" + +#include "stm32.h" +#include "stm32_capture.h" +#include "arm_internal.h" + +#include "stm32f4discovery.h" + +#if defined(CONFIG_CAPTURE) +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Capture + * + * The stm32f4discovery has no real on-board pwm capture devices, but the + * board can be configured to capture pwm using TIM3 CH2 PB5. + */ + +#define HAVE_CAPTURE 1 + +#ifndef CONFIG_CAPTURE +# undef HAVE_CAPTURE +#endif + +#ifndef CONFIG_STM32_TIM3 +# undef HAVE_CAPTURE +#endif + +#ifndef CONFIG_STM32_TIM3_CAP +# undef HAVE_CAPTURE +#endif + +#if !defined(CONFIG_STM32_TIM3_CHANNEL) || CONFIG_STM32_TIM3_CHANNEL != STM32F4DISCOVERY_CAPTURECHANNEL +# undef HAVE_CAPTURE +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_capture_setup + * + * Description: + * Initialize and register the pwm capture driver. + * + * Input parameters: + * devpath - The full path to the driver to register. E.g., "/dev/capture0" + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +int stm32_capture_setup(const char *devpath) +{ +#ifdef HAVE_CAPTURE + struct cap_lowerhalf_s *capture; + int ret; + + capture = stm32_cap_initialize(STM32F4DISCOVERY_CAPTURETIMER); + + /* Then register the pwm capture sensor */ + + ret = cap_register(devpath, capture); + if (ret < 0) + { + mtrerr("ERROR: Error registering capture\n"); + } + + return ret; +#else + return -ENODEV; +#endif +} + +#endif /* CONFIG_CAPTURE */ diff --git a/boards/arm/stm32f4/stm32f4discovery/src/stm32_composite.c b/boards/arm/stm32f4/stm32f4discovery/src/stm32_composite.c new file mode 100644 index 0000000000000..55103ee912e34 --- /dev/null +++ b/boards/arm/stm32f4/stm32f4discovery/src/stm32_composite.c @@ -0,0 +1,349 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f4discovery/src/stm32_composite.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include "stm32_otgfs.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define COMPOSITE0_DEV (3) + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#ifdef CONFIG_USBMSC_COMPOSITE +static void *g_mschandle; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_mscclassobject + * + * Description: + * If the mass storage class driver is part of composite device, then + * its instantiation and configuration is a multi-step, board-specific, + * process (See comments for usbmsc_configure below). In this case, + * board-specific logic must provide board_mscclassobject(). + * + * board_mscclassobject() is called from the composite driver. It must + * encapsulate the instantiation and configuration of the mass storage + * class and the return the mass storage device's class driver instance + * to the composite driver. + * + * Input Parameters: + * classdev - The location to return the mass storage class' device + * instance. + * + * Returned Value: + * 0 on success; a negated errno on failure + * + ****************************************************************************/ + +#ifdef CONFIG_USBMSC_COMPOSITE +static int board_mscclassobject(int minor, + struct usbdev_devinfo_s *devinfo, + struct usbdevclass_driver_s **classdev) +{ + int ret; + + DEBUGASSERT(g_mschandle == NULL); + + /* Configure the mass storage device */ + + uinfo("Configuring with NLUNS=1\n"); + ret = usbmsc_configure(1, &g_mschandle); + if (ret < 0) + { + uerr("ERROR: usbmsc_configure failed: %d\n", -ret); + return ret; + } + + uinfo("MSC handle=%p\n", g_mschandle); + + /* Bind the LUN(s) */ + + uinfo("Bind LUN=0 to /dev/mmcsd0\n"); + ret = usbmsc_bindlun(g_mschandle, "/dev/mmcsd0", 0, 0, 0, false); + if (ret < 0) + { + uerr("ERROR: usbmsc_bindlun failed for LUN 1 at /dev/mmcsd0: %d\n", + ret); + usbmsc_uninitialize(g_mschandle); + g_mschandle = NULL; + return ret; + } + + /* Get the mass storage device's class object */ + + ret = usbmsc_classobject(g_mschandle, devinfo, classdev); + if (ret < 0) + { + uerr("ERROR: usbmsc_classobject failed: %d\n", -ret); + usbmsc_uninitialize(g_mschandle); + g_mschandle = NULL; + } + + return ret; +} +#endif + +/**************************************************************************** + * Name: board_mscuninitialize + * + * Description: + * Un-initialize the USB storage class driver. + * This is just an application specific wrapper for usbmsc_unitialize() + * that is called form the composite device logic. + * + * Input Parameters: + * classdev - The class driver instance previously given to the composite + * driver by board_mscclassobject(). + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_USBMSC_COMPOSITE +static void board_mscuninitialize(struct usbdevclass_driver_s *classdev) +{ + if (g_mschandle) + { + usbmsc_uninitialize(g_mschandle); + } + + g_mschandle = NULL; +} +#endif + +/**************************************************************************** + * Name: board_composite_connect + * + * Description: + * Connect the USB composite device on the specified USB device port for + * configuration 0. + * + * Input Parameters: + * port - The USB device port. + * + * Returned Value: + * A non-NULL handle value is returned on success. NULL is returned on + * any failure. + * + ****************************************************************************/ + +static void *board_composite0_connect(int port) +{ + struct composite_devdesc_s dev[COMPOSITE0_DEV]; + int ifnobase = 0; + int strbase = COMPOSITE_NSTRIDS; + int dev_idx = 0; + int epin = 1; + int epout = 1; + +#ifdef CONFIG_RNDIS_COMPOSITE + /* Configure the RNDIS USB device */ + + /* Ask the rndis driver to fill in the constants we didn't + * know here. + */ + + usbdev_rndis_get_composite_devdesc(&dev[dev_idx]); + + /* Interfaces */ + + dev[dev_idx].devinfo.ifnobase = ifnobase; + dev[dev_idx].minor = 0; + + /* Strings */ + + dev[dev_idx].devinfo.strbase = strbase; + + /* Endpoints */ + + dev[dev_idx].devinfo.epno[RNDIS_EP_INTIN_IDX] = epin++; + dev[dev_idx].devinfo.epno[RNDIS_EP_BULKIN_IDX] = epin++; + dev[dev_idx].devinfo.epno[RNDIS_EP_BULKOUT_IDX] = epout++; + + /* Count up the base numbers */ + + ifnobase += dev[dev_idx].devinfo.ninterfaces; + strbase += dev[dev_idx].devinfo.nstrings; + + dev_idx += 1; +#endif + +#ifdef CONFIG_USBMSC_COMPOSITE + /* Configure the mass storage device device */ + + /* Ask the usbmsc driver to fill in the constants we didn't + * know here. + */ + + usbmsc_get_composite_devdesc(&dev[dev_idx]); + + /* Overwrite and correct some values... */ + + /* The callback functions for the USBMSC class */ + + dev[dev_idx].classobject = board_mscclassobject; + dev[dev_idx].uninitialize = board_mscuninitialize; + + /* Interfaces */ + + dev[dev_idx].devinfo.ifnobase = ifnobase; /* Offset to Interface-IDs */ + dev[dev_idx].minor = 0; /* The minor interface number */ + + /* Strings */ + + dev[dev_idx].devinfo.strbase = strbase; /* Offset to String Numbers */ + + /* Endpoints */ + + dev[dev_idx].devinfo.epno[USBMSC_EP_BULKIN_IDX] = epin++; + dev[dev_idx].devinfo.epno[USBMSC_EP_BULKOUT_IDX] = epout++; + + /* Count up the base numbers */ + + ifnobase += dev[dev_idx].devinfo.ninterfaces; + strbase += dev[dev_idx].devinfo.nstrings; + + dev_idx += 1; +#endif + +#ifdef CONFIG_CDCACM_COMPOSITE + /* Configure the CDC/ACM device */ + + /* Ask the cdcacm driver to fill in the constants we didn't + * know here. + */ + + cdcacm_get_composite_devdesc(&dev[dev_idx]); + + /* Overwrite and correct some values... */ + + /* The callback functions for the CDC/ACM class */ + + dev[dev_idx].classobject = cdcacm_classobject; + dev[dev_idx].uninitialize = cdcacm_uninitialize; + + /* Interfaces */ + + dev[dev_idx].devinfo.ifnobase = ifnobase; /* Offset to Interface-IDs */ + dev[dev_idx].minor = 0; /* The minor interface number */ + + /* Strings */ + + dev[dev_idx].devinfo.strbase = strbase; /* Offset to String Numbers */ + + /* Endpoints */ + + dev[dev_idx].devinfo.epno[CDCACM_EP_INTIN_IDX] = epin++; + dev[dev_idx].devinfo.epno[CDCACM_EP_BULKIN_IDX] = epin++; + dev[dev_idx].devinfo.epno[CDCACM_EP_BULKOUT_IDX] = epout++; + + /* Count up the base numbers */ + + ifnobase += dev[dev_idx].devinfo.ninterfaces; + strbase += dev[dev_idx].devinfo.nstrings; + + dev_idx += 1; +#endif + + /* Sanity checks */ + + DEBUGASSERT(epin < STM32_NENDPOINTS); + DEBUGASSERT(epout < STM32_NENDPOINTS); + + return composite_initialize(composite_getdevdescs(), dev, dev_idx); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_composite_initialize + * + * Description: + * Perform architecture specific initialization of a composite USB device. + * + ****************************************************************************/ + +int board_composite_initialize(int port) +{ + return OK; +} + +/**************************************************************************** + * Name: board_composite_connect + * + * Description: + * Connect the USB composite device on the specified USB device port using + * the specified configuration. The interpretation of the configid is + * board specific. + * + * Input Parameters: + * port - The USB device port. + * configid - The USB composite configuration + * + * Returned Value: + * A non-NULL handle value is returned on success. NULL is returned on + * any failure. + * + ****************************************************************************/ + +void *board_composite_connect(int port, int configid) +{ + if (configid == 0) + { + return board_composite0_connect(port); + } + else + { + return NULL; + } +} diff --git a/boards/arm/stm32/stm32f4discovery/src/stm32_cs43l22.c b/boards/arm/stm32f4/stm32f4discovery/src/stm32_cs43l22.c similarity index 99% rename from boards/arm/stm32/stm32f4discovery/src/stm32_cs43l22.c rename to boards/arm/stm32f4/stm32f4discovery/src/stm32_cs43l22.c index 32949202cf499..a50ef41c344b6 100644 --- a/boards/arm/stm32/stm32f4discovery/src/stm32_cs43l22.c +++ b/boards/arm/stm32f4/stm32f4discovery/src/stm32_cs43l22.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f4discovery/src/stm32_cs43l22.c + * boards/arm/stm32f4/stm32f4discovery/src/stm32_cs43l22.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f4/stm32f4discovery/src/stm32_djoystick.c b/boards/arm/stm32f4/stm32f4discovery/src/stm32_djoystick.c new file mode 100644 index 0000000000000..aa9fe97748a12 --- /dev/null +++ b/boards/arm/stm32f4/stm32f4discovery/src/stm32_djoystick.c @@ -0,0 +1,299 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f4discovery/src/stm32_djoystick.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include +#include +#include + +#include "stm32_gpio.h" +#include "stm32f4discovery.h" + +#ifdef CONFIG_INPUT_DJOYSTICK + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Number of Joystick discretes 5-WAY */ + +#define DJOY_NGPIOS 5 + +/* Bitset of supported Joystick discretes */ + +#define DJOY_SUPPORTED (DJOY_UP_BIT | DJOY_DOWN_BIT | DJOY_LEFT_BIT | \ + DJOY_RIGHT_BIT | DJOY_BUTTON_SELECT_BIT) + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +static djoy_buttonset_t + djoy_supported(const struct djoy_lowerhalf_s *lower); +static djoy_buttonset_t + djoy_sample(const struct djoy_lowerhalf_s *lower); +static void djoy_enable(const struct djoy_lowerhalf_s *lower, + djoy_buttonset_t press, djoy_buttonset_t release, + djoy_interrupt_t handler, void *arg); + +static void djoy_disable(void); +static int djoy_interrupt(int irq, void *context, void *arg); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* Pin configuration for each Olimex-P407 joystick "button." Index using + * DJOY_* definitions in include/nuttx/input/djoystick.h. + */ + +static const uint16_t g_joygpio[DJOY_NGPIOS] = +{ + GPIO_JOY_UP, GPIO_JOY_DOWN, GPIO_JOY_LEFT, GPIO_JOY_RIGHT, GPIO_JOY_CENTER +}; + +/* Current interrupt handler and argument */ + +static djoy_interrupt_t g_djoyhandler; +static void *g_djoyarg; + +/* This is the discrete joystick lower half driver interface */ + +static const struct djoy_lowerhalf_s g_djoylower = +{ + .dl_supported = djoy_supported, + .dl_sample = djoy_sample, + .dl_enable = djoy_enable, +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: djoy_supported + * + * Description: + * Return the set of buttons supported on the discrete joystick device + * + ****************************************************************************/ + +static djoy_buttonset_t + djoy_supported(const struct djoy_lowerhalf_s *lower) +{ + iinfo("Supported: %02x\n", DJOY_SUPPORTED); + return (djoy_buttonset_t)DJOY_SUPPORTED; +} + +/**************************************************************************** + * Name: djoy_sample + * + * Description: + * Return the current state of all discrete joystick buttons + * + ****************************************************************************/ + +static djoy_buttonset_t djoy_sample(const struct djoy_lowerhalf_s *lower) +{ + djoy_buttonset_t ret = 0; + int i; + + /* Read each joystick GPIO value */ + + for (i = 0; i < DJOY_NGPIOS; i++) + { + bool released = stm32_gpioread(g_joygpio[i]); + if (!released) + { + ret |= (1 << i); + } + } + + iinfo("Retuning: %02x\n", DJOY_SUPPORTED); + return ret; +} + +/**************************************************************************** + * Name: djoy_enable + * + * Description: + * Enable interrupts on the selected set of joystick buttons. And empty + * set will disable all interrupts. + * + ****************************************************************************/ + +static void djoy_enable(const struct djoy_lowerhalf_s *lower, + djoy_buttonset_t press, djoy_buttonset_t release, + djoy_interrupt_t handler, void *arg) +{ + irqstate_t flags; + djoy_buttonset_t either = press | release; + djoy_buttonset_t bit; + bool rising; + bool falling; + int i; + + /* Start with all interrupts disabled */ + + flags = enter_critical_section(); + djoy_disable(); + + iinfo("press: %02x release: %02x handler: %p arg: %p\n", + press, release, handler, arg); + + /* If no events are indicated or if no handler is provided, then this + * must really be a request to disable interrupts. + */ + + if (either && handler) + { + /* Save the new the handler and argument */ + + g_djoyhandler = handler; + g_djoyarg = arg; + + /* Check each GPIO. */ + + for (i = 0; i < DJOY_NGPIOS; i++) + { + /* Enable interrupts on each pin that has either a press or + * release event associated with it. + */ + + bit = (1 << i); + if ((either & bit) != 0) + { + /* Active low so a press corresponds to a falling edge and + * a release corresponds to a rising edge. + */ + + falling = ((press & bit) != 0); + rising = ((release & bit) != 0); + + iinfo("GPIO %d: rising: %d falling: %d\n", + i, rising, falling); + + stm32_gpiosetevent(g_joygpio[i], rising, falling, + true, djoy_interrupt, NULL); + } + } + } + + leave_critical_section(flags); +} + +/**************************************************************************** + * Name: djoy_disable + * + * Description: + * Disable all joystick interrupts + * + ****************************************************************************/ + +static void djoy_disable(void) +{ + irqstate_t flags; + int i; + + /* Disable each joystick interrupt */ + + flags = enter_critical_section(); + for (i = 0; i < DJOY_NGPIOS; i++) + { + stm32_gpiosetevent(g_joygpio[i], false, false, false, NULL, NULL); + } + + leave_critical_section(flags); + + /* Nullify the handler and argument */ + + g_djoyhandler = NULL; + g_djoyarg = NULL; +} + +/**************************************************************************** + * Name: djoy_interrupt + * + * Description: + * Discrete joystick interrupt handler + * + ****************************************************************************/ + +static int djoy_interrupt(int irq, void *context, void *arg) +{ + DEBUGASSERT(g_djoyhandler); + if (g_djoyhandler) + { + g_djoyhandler(&g_djoylower, g_djoyarg); + } + + return OK; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_djoy_initialize + * + * Description: + * Initialize and register the discrete joystick driver + * + ****************************************************************************/ + +int stm32_djoy_initialize(void) +{ + int i; + + /* Configure the GPIO pins as inputs. NOTE: This is unnecessary for + * interrupting pins since it will also be done by stm32_gpiosetevent(). + */ + + for (i = 0; i < DJOY_NGPIOS; i++) + { + stm32_configgpio(g_joygpio[i]); + } + + /* Make sure that all interrupts are disabled */ + + djoy_disable(); + + /* Register the joystick device as /dev/djoy0 */ + + return djoy_register("/dev/djoy0", &g_djoylower); +} + +#endif /* CONFIG_INPUT_DJOYSTICK */ diff --git a/boards/arm/stm32f4/stm32f4discovery/src/stm32_enc28j60.c b/boards/arm/stm32f4/stm32f4discovery/src/stm32_enc28j60.c new file mode 100644 index 0000000000000..1f81619aed881 --- /dev/null +++ b/boards/arm/stm32f4/stm32f4discovery/src/stm32_enc28j60.c @@ -0,0 +1,219 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f4discovery/src/stm32_enc28j60.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* 2MBit SPI FLASH OR ENC28J60 + * + * -- ---- ------------ ----------------------------------------------------- + * PIN NAME SIGNAL NOTES + * -- ---- ------------ ----------------------------------------------------- + * + * 29 PA4 PA4-SPI1-NSS 10Mbit ENC28J60, SPI 2M FLASH + * 30 PA5 PA5-SPI1-SCK 2.4" TFT + Touchscreen, 10Mbit ENC28J60, SPI 2M FLASH + * 31 PA6 PA6-SPI1-MISO 2.4" TFT + Touchscreen, 10Mbit ENC28J60, SPI 2M FLASH + * 32 PA7 PA7-SPI1-MOSI 2.4" TFT + Touchscreen, 10Mbit ENC28J60, SPI 2M FLASH + */ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include + +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32_spi.h" + +#include "stm32f4discovery.h" + +#ifdef CONFIG_ENC28J60 + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* ENC28J60 + * + * --- ------ -------------- ------------------------------------------------ + * PIN NAME SIGNAL NOTES + * --- ------ -------------- ------------------------------------------------ + * + * 29 PA4 PA4-SPI1-NSS 10Mbit ENC28J60, SPI 2M FLASH + * 30 PA5 PA5-SPI1-SCK 2.4" TFT + Touchscreen, + * 10Mbit ENC28J60, SPI 2M FLASH + * 31 PA6 PA6-SPI1-MISO 2.4" TFT + Touchscreen, + * 10Mbit ENC28J60, SPI 2M FLASH + * 32 PA7 PA7-SPI1-MOSI 2.4" TFT + Touchscreen, + * 10Mbit ENC28J60, SPI 2M FLASH + * 98 PE1 PE1-FSMC_NBL1 2.4" TFT + Touchscreen, + * 10Mbit EN28J60 Reset + * 4 PE5 (no name) 10Mbps ENC28J60 Interrupt + */ + +/* ENC28J60 is on SPI1 */ + +#ifndef CONFIG_STM32_SPI1 +# error "Need CONFIG_STM32_SPI1 in the configuration" +#endif + +/* SPI Assumptions **********************************************************/ + +#define ENC28J60_SPI_PORTNO 1 /* On SPI1 */ +#define ENC28J60_DEVNO 0 /* Only one ENC28J60 */ + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +struct stm32_lower_s +{ + const struct enc_lower_s lower; /* Low-level MCU interface */ + xcpt_t handler; /* ENC28J60 interrupt handler */ + void *arg; /* Argument that accompanies the interrupt */ +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +static int up_attach(const struct enc_lower_s *lower, xcpt_t handler, + void *arg); +static void up_enable(const struct enc_lower_s *lower); +static void up_disable(const struct enc_lower_s *lower); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* The ENC28J60 normal provides interrupts to the MCU via a GPIO pin. The + * following structure provides an MCU-independent mechanixm for controlling + * the ENC28J60 GPIO interrupt. + */ + +static struct stm32_lower_s g_enclower = +{ + .lower = + { + .attach = up_attach, + .enable = up_enable, + .disable = up_disable + }, + .handler = NULL, + .arg = NULL +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: struct enc_lower_s methods + ****************************************************************************/ + +static int up_attach(const struct enc_lower_s *lower, xcpt_t handler, + void *arg) +{ + struct stm32_lower_s *priv = (struct stm32_lower_s *)lower; + + /* Just save the handler for use when the interrupt is enabled */ + + priv->handler = handler; + priv->arg = arg; + return OK; +} + +static void up_enable(const struct enc_lower_s *lower) +{ + struct stm32_lower_s *priv = (struct stm32_lower_s *)lower; + + DEBUGASSERT(priv->handler); + stm32_gpiosetevent(GPIO_ENC28J60_INTR, false, true, true, + priv->handler, priv->arg); +} + +/* REVISIT: Since the interrupt is completely torn down, not just disabled, + * in interrupt requests that occurs while the interrupt is disabled will be + * lost. + */ + +static void up_disable(const struct enc_lower_s *lower) +{ + stm32_gpiosetevent(GPIO_ENC28J60_INTR, false, true, true, + NULL, NULL); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: arm_netinitialize + ****************************************************************************/ + +void arm_netinitialize(void) +{ + struct spi_dev_s *spi; + int ret; + + /* Assumptions: + * 1) ENC28J60 pins were configured in up_spi.c early in the boot-up phase. + * 2) Clocking for the SPI1 peripheral was also provided earlier in + * boot-up. + */ + + spi = stm32_spibus_initialize(ENC28J60_SPI_PORTNO); + if (!spi) + { + nerr("ERROR: Failed to initialize SPI port %d\n", ENC28J60_SPI_PORTNO); + return; + } + + /* Take ENC28J60 out of reset (active low) */ + + stm32_gpiowrite(GPIO_ENC28J60_RESET, true); + + /* Bind the SPI port to the ENC28J60 driver */ + + ret = enc_initialize(spi, &g_enclower.lower, ENC28J60_DEVNO); + if (ret < 0) + { + nerr("ERROR: Failed to bind SPI port %d ENC28J60 device %d: %d\n", + ENC28J60_SPI_PORTNO, ENC28J60_DEVNO, ret); + return; + } + + ninfo("Bound SPI port %d to ENC28J60 device %d\n", + ENC28J60_SPI_PORTNO, ENC28J60_DEVNO); +} + +#endif /* CONFIG_ENC28J60 */ diff --git a/boards/arm/stm32/stm32f4discovery/src/stm32_ethernet.c b/boards/arm/stm32f4/stm32f4discovery/src/stm32_ethernet.c similarity index 99% rename from boards/arm/stm32/stm32f4discovery/src/stm32_ethernet.c rename to boards/arm/stm32f4/stm32f4discovery/src/stm32_ethernet.c index 88cf550586e01..7907bedf1a2b9 100644 --- a/boards/arm/stm32/stm32f4discovery/src/stm32_ethernet.c +++ b/boards/arm/stm32f4/stm32f4discovery/src/stm32_ethernet.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f4discovery/src/stm32_ethernet.c + * boards/arm/stm32f4/stm32f4discovery/src/stm32_ethernet.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f4/stm32f4discovery/src/stm32_extmem.c b/boards/arm/stm32f4/stm32f4discovery/src/stm32_extmem.c new file mode 100644 index 0000000000000..5342769613125 --- /dev/null +++ b/boards/arm/stm32f4/stm32f4discovery/src/stm32_extmem.c @@ -0,0 +1,140 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f4discovery/src/stm32_extmem.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32.h" +#include "stm32f4discovery.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifndef CONFIG_STM32_FSMC +# warning "FSMC is not enabled" +#endif + +#if STM32_NGPIO_PORTS < 6 +# error "Required GPIO ports not enabled" +#endif + +#define STM32_FSMC_NADDRCONFIGS 26 +#define STM32_FSMC_NDATACONFIGS 16 + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/* GPIO configurations common to most external memories */ + +static const uint32_t g_addressconfig[STM32_FSMC_NADDRCONFIGS] = +{ + GPIO_FSMC_A0, GPIO_FSMC_A1, GPIO_FSMC_A2, + GPIO_FSMC_A3, GPIO_FSMC_A4, GPIO_FSMC_A5, + GPIO_FSMC_A6, GPIO_FSMC_A7, GPIO_FSMC_A8, + GPIO_FSMC_A9, GPIO_FSMC_A10, GPIO_FSMC_A11, + GPIO_FSMC_A12, GPIO_FSMC_A13, GPIO_FSMC_A14, + GPIO_FSMC_A15, GPIO_FSMC_A16, GPIO_FSMC_A17, + GPIO_FSMC_A18, GPIO_FSMC_A19, GPIO_FSMC_A20, + GPIO_FSMC_A21, GPIO_FSMC_A22, GPIO_FSMC_A23, + GPIO_FSMC_A24, GPIO_FSMC_A25 +}; + +static const uint32_t g_dataconfig[STM32_FSMC_NDATACONFIGS] = +{ + GPIO_FSMC_D0, GPIO_FSMC_D1, GPIO_FSMC_D2, + GPIO_FSMC_D3, GPIO_FSMC_D4, GPIO_FSMC_D5, + GPIO_FSMC_D6, GPIO_FSMC_D7, GPIO_FSMC_D8, + GPIO_FSMC_D9, GPIO_FSMC_D10, GPIO_FSMC_D11, + GPIO_FSMC_D12, GPIO_FSMC_D13, GPIO_FSMC_D14, + GPIO_FSMC_D15 +}; + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_extmemgpios + * + * Description: + * Initialize GPIOs for external memory usage + * + ****************************************************************************/ + +void stm32_extmemgpios(const uint32_t *gpios, int ngpios) +{ + int i; + + /* Configure GPIOs */ + + for (i = 0; i < ngpios; i++) + { + stm32_configgpio(gpios[i]); + } +} + +/**************************************************************************** + * Name: stm32_extmemaddr + * + * Description: + * Initialize address line GPIOs for external memory access + * + ****************************************************************************/ + +void stm32_extmemaddr(int naddrs) +{ + stm32_extmemgpios(g_addressconfig, naddrs); +} + +/**************************************************************************** + * Name: stm32_extmemdata + * + * Description: + * Initialize data line GPIOs for external memory access + * + ****************************************************************************/ + +void stm32_extmemdata(int ndata) +{ + stm32_extmemgpios(g_dataconfig, ndata); +} diff --git a/boards/arm/stm32/stm32f4discovery/src/stm32_gs2200m.c b/boards/arm/stm32f4/stm32f4discovery/src/stm32_gs2200m.c similarity index 99% rename from boards/arm/stm32/stm32f4discovery/src/stm32_gs2200m.c rename to boards/arm/stm32f4/stm32f4discovery/src/stm32_gs2200m.c index e53aba34f5b9e..44a5d77c1d835 100644 --- a/boards/arm/stm32/stm32f4discovery/src/stm32_gs2200m.c +++ b/boards/arm/stm32f4/stm32f4discovery/src/stm32_gs2200m.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f4discovery/src/stm32_gs2200m.c + * boards/arm/stm32f4/stm32f4discovery/src/stm32_gs2200m.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f4/stm32f4discovery/src/stm32_hciuart.c b/boards/arm/stm32f4/stm32f4discovery/src/stm32_hciuart.c new file mode 100644 index 0000000000000..12ac1ef084b75 --- /dev/null +++ b/boards/arm/stm32f4/stm32f4discovery/src/stm32_hciuart.c @@ -0,0 +1,84 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f4discovery/src/stm32_hciuart.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include + +#include "stm32_hciuart.h" +#include "stm32f4discovery.h" + +#include + +#ifdef HAVE_HCIUART + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: hciuart_dev_initialize + * + * Description: + * This function is called by board initialization logic to configure the + * Bluetooth HCI UART driver + * + * Input Parameters: + * None + * + * Returned Value: + * Zero is returned on success. Otherwise, a negated errno value is + * returned to indicate the nature of the failure. + * + ****************************************************************************/ + +int hciuart_dev_initialize(void) +{ + int ret; + + /* Perform one-time initialization */ + + hciuart_initialize(); + + /* Instantiate the HCI UART lower half interface + * Then initialize the HCI UART upper half driver with the bluetooth stack + */ + + ret = btuart_register(hciuart_instantiate(HCIUART_SERDEV)); + if (ret < 0) + { + wlerr("ERROR: btuart_register() failed: %d\n", ret); + } + + return ret; +} + +#endif /* HAVE_HCIUART */ diff --git a/boards/arm/stm32f4/stm32f4discovery/src/stm32_hx711.c b/boards/arm/stm32f4/stm32f4discovery/src/stm32_hx711.c new file mode 100644 index 0000000000000..17a22bd612563 --- /dev/null +++ b/boards/arm/stm32f4/stm32f4discovery/src/stm32_hx711.c @@ -0,0 +1,104 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f4discovery/src/stm32_hx711.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include +#include +#include +#include + +#include "stm32_gpio.h" +#include "stm32f4discovery.h" + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +static int stm32_hx711_clock_set(unsigned char minor, int value); +static int stm32_hx711_data_read(unsigned char minor); +static int stm32_hx711_data_irq(unsigned char minor, + xcpt_t handler, void *arg); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +struct hx711_lower_s g_lower = +{ + .data_read = stm32_hx711_data_read, + .clock_set = stm32_hx711_clock_set, + .data_irq = stm32_hx711_data_irq, + .cleanup = NULL +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +static int stm32_hx711_clock_set(unsigned char minor, int value) +{ + UNUSED(minor); + + stm32_gpiowrite(HX711_CLK_PIN, value); + return OK; +} + +static int stm32_hx711_data_read(unsigned char minor) +{ + UNUSED(minor); + + return stm32_gpioread(HX711_DATA_PIN); +} + +static int stm32_hx711_data_irq(unsigned char minor, + xcpt_t handler, void *arg) +{ + UNUSED(minor); + + return stm32_gpiosetevent(HX711_DATA_PIN, false, true, true, handler, arg); +}; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +int stm32_hx711_initialize(void) +{ + int ret; + + stm32_configgpio(HX711_DATA_PIN); + stm32_configgpio(HX711_CLK_PIN); + + ret = hx711_register(0, &g_lower); + if (ret != 0) + { + aerr("ERROR: Failed to register hx711 device: %d\n", ret); + return -1; + } + + return OK; +} diff --git a/boards/arm/stm32f4/stm32f4discovery/src/stm32_idle.c b/boards/arm/stm32f4/stm32f4discovery/src/stm32_idle.c new file mode 100644 index 0000000000000..b32240a9bdc24 --- /dev/null +++ b/boards/arm/stm32f4/stm32f4discovery/src/stm32_idle.c @@ -0,0 +1,260 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f4discovery/src/stm32_idle.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include + +#include +#include +#include +#include + +#include + +#include "arm_internal.h" +#include "stm32_pm.h" +#include "stm32_rcc.h" +#include "stm32_exti.h" + +#include "stm32f4discovery.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* Does the board support an IDLE LED to indicate that the board is in the + * IDLE state? + */ + +#if defined(CONFIG_ARCH_LEDS) && defined(LED_IDLE) +# define BEGIN_IDLE() board_autoled_on(LED_IDLE) +# define END_IDLE() board_autoled_off(LED_IDLE) +#else +# define BEGIN_IDLE() +# define END_IDLE() +#endif + +/* Values for the RTC Alarm to wake up from the PM_STANDBY mode */ + +#ifndef CONFIG_PM_ALARM_SEC +# define CONFIG_PM_ALARM_SEC 3 +#endif + +#ifndef CONFIG_PM_ALARM_NSEC +# define CONFIG_PM_ALARM_NSEC 0 +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#if 0 /* Not used */ +static void up_alarmcb(void); +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_idlepm + * + * Description: + * Perform IDLE state power management. + * + ****************************************************************************/ + +#ifdef CONFIG_PM +static void stm32_idlepm(void) +{ + static enum pm_state_e oldstate = PM_NORMAL; + enum pm_state_e newstate; + irqstate_t flags; + int ret; + + /* Decide, which power saving level can be obtained */ + + newstate = pm_checkstate(PM_IDLE_DOMAIN); + + /* Check for state changes */ + + if (newstate != oldstate) + { + sinfo("newstate= %d oldstate=%d\n", newstate, oldstate); + + flags = enter_critical_section(); + + /* Force the global state change */ + + ret = pm_changestate(PM_IDLE_DOMAIN, newstate); + if (ret < 0) + { + /* The new state change failed, revert to the preceding state */ + + pm_changestate(PM_IDLE_DOMAIN, oldstate); + + /* No state change... */ + + goto errout; + } + + /* Then perform board-specific, state-dependent logic here */ + + switch (newstate) + { + case PM_NORMAL: + { + } + break; + + case PM_IDLE: + { + } + break; + + case PM_STANDBY: + { +#ifdef CONFIG_RTC_ALARM + /* Disable RTC Alarm interrupt */ + +#warning "missing logic" + + /* Configure the RTC alarm to Auto Wake the system */ + +#warning "missing logic" + + /* The tv_nsec value must not exceed 1,000,000,000. That + * would be an invalid time. + */ + +#warning "missing logic" + + /* Set the alarm */ + +#warning "missing logic" +#endif + /* Call the STM32 stop mode */ + + stm32_pmstop(true); + + /* We have been re-awakened by some even: A button press? + * An alarm? Cancel any pending alarm and resume the normal + * operation. + */ + +#ifdef CONFIG_RTC_ALARM +#warning "missing logic" +#endif + /* Resume normal operation */ + + pm_changestate(PM_IDLE_DOMAIN, PM_NORMAL); + newstate = PM_NORMAL; + } + break; + + case PM_SLEEP: + { + /* We should not return from standby mode. The only way out + * of standby is via the reset path. + */ + + stm32_pmstandby(); + } + break; + + default: + break; + } + + /* Save the new state */ + + oldstate = newstate; + +errout: + leave_critical_section(flags); + } +} +#else +# define stm32_idlepm() +#endif + +/**************************************************************************** + * Name: up_alarmcb + * + * Description: + * RTC alarm service routine + * + ****************************************************************************/ + +#if 0 /* Not used */ +static void up_alarmcb(void) +{ + /* This alarm occurs because there wasn't any EXTI interrupt during the + * PM_STANDBY period. So just go to sleep. + */ + + pm_changestate(PM_IDLE_DOMAIN, PM_SLEEP); +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_idle + * + * Description: + * up_idle() is the logic that will be executed when their is no other + * ready-to-run task. This is processor idle time and will continue until + * some interrupt occurs to cause a context switch from the idle task. + * + * Processing in this state may be processor-specific. e.g., this is where + * power management operations might be performed. + * + ****************************************************************************/ + +void up_idle(void) +{ +#if defined(CONFIG_SUPPRESS_INTERRUPTS) || defined(CONFIG_SUPPRESS_TIMER_INTS) + /* If the system is idle and there are no timer interrupts, then process + * "fake" timer interrupts. Hopefully, something will wake up. + */ + + nxsched_process_timer(); +#else + + /* Perform IDLE mode power management */ + + BEGIN_IDLE(); + stm32_idlepm(); + END_IDLE(); +#endif +} diff --git a/boards/arm/stm32f4/stm32f4discovery/src/stm32_max7219.c b/boards/arm/stm32f4/stm32f4discovery/src/stm32_max7219.c new file mode 100644 index 0000000000000..b3cd7b43f6c55 --- /dev/null +++ b/boards/arm/stm32f4/stm32f4discovery/src/stm32_max7219.c @@ -0,0 +1,114 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f4discovery/src/stm32_max7219.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include "stm32_gpio.h" +#include "stm32_spi.h" +#include "stm32f4discovery.h" + +#ifdef CONFIG_NX_LCDDRIVER + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define LCD_SPI_PORTNO 1 /* On SPI1 */ + +#ifndef CONFIG_LCD_CONTRAST +# define CONFIG_LCD_CONTRAST 60 +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +struct spi_dev_s *g_spidev; +struct lcd_dev_s *g_lcddev; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_lcd_initialize + ****************************************************************************/ + +int board_lcd_initialize(void) +{ + g_spidev = stm32_spibus_initialize(LCD_SPI_PORTNO); + + if (g_spidev == NULL) + { + lcderr("ERROR: Failed to initialize SPI port %d\n", LCD_SPI_PORTNO); + return -ENODEV; + } + + return OK; +} + +/**************************************************************************** + * Name: board_lcd_getdev + ****************************************************************************/ + +struct lcd_dev_s *board_lcd_getdev(int lcddev) +{ + g_lcddev = max7219_initialize(g_spidev, lcddev); + if (!g_lcddev) + { + lcderr("ERROR: Failed to bind SPI port 1 to LCD %d\n", lcddev); + } + else + { + lcdinfo("SPI port 1 bound to LCD %d\n", lcddev); + + return g_lcddev; + } + + return NULL; +} + +/**************************************************************************** + * Name: board_lcd_uninitialize + ****************************************************************************/ + +void board_lcd_uninitialize(void) +{ + /* TO-FIX */ +} + +#endif /* CONFIG_NX_LCDDRIVER */ diff --git a/boards/arm/stm32/stm32f4discovery/src/stm32_max7219_leds.c b/boards/arm/stm32f4/stm32f4discovery/src/stm32_max7219_leds.c similarity index 97% rename from boards/arm/stm32/stm32f4discovery/src/stm32_max7219_leds.c rename to boards/arm/stm32f4/stm32f4discovery/src/stm32_max7219_leds.c index de429e9f91a13..4062a4006ba0a 100644 --- a/boards/arm/stm32/stm32f4discovery/src/stm32_max7219_leds.c +++ b/boards/arm/stm32f4/stm32f4discovery/src/stm32_max7219_leds.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f4discovery/src/stm32_max7219_leds.c + * boards/arm/stm32f4/stm32f4discovery/src/stm32_max7219_leds.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f4/stm32f4discovery/src/stm32_mmcsd.c b/boards/arm/stm32f4/stm32f4discovery/src/stm32_mmcsd.c new file mode 100644 index 0000000000000..1118bb880c6ed --- /dev/null +++ b/boards/arm/stm32f4/stm32f4discovery/src/stm32_mmcsd.c @@ -0,0 +1,106 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f4discovery/src/stm32_mmcsd.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "arm_internal.h" +#include "chip.h" +#include "stm32.h" + +#include +#include "stm32f4discovery.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifdef CONFIG_DISABLE_MOUNTPOINT +# error "SD driver requires CONFIG_DISABLE_MOUNTPOINT to be disabled" +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_spi1register + * + * Description: + * Registers media change callback + ****************************************************************************/ + +int stm32_spi2register(struct spi_dev_s *dev, spi_mediachange_t callback, + void *arg) +{ + /* TODO: media change callback */ + + return OK; +} + +/**************************************************************************** + * Name: stm32_mmcsd_initialize + * + * Description: + * Initialize SPI-based SD card and card detect thread. + ****************************************************************************/ + +int stm32_mmcsd_initialize(int port, int minor) +{ + struct spi_dev_s *spi; + int rv; + + stm32_configgpio(GPIO_MMCSD_NCD); /* Assign SD_DET */ + stm32_configgpio(GPIO_MMCSD_NSS); /* Assign CS */ + stm32_gpiowrite(GPIO_MMCSD_NSS, 1); /* Ensure the CS is inactive */ + + mcinfo("INFO: Initializing mmcsd port %d minor %d\n", + port, minor); + + spi = stm32_spibus_initialize(port); + if (spi == NULL) + { + mcerr("ERROR: Failed to initialize SPI port %d\n", port); + return -ENODEV; + } + + rv = mmcsd_spislotinitialize(minor, minor, spi); + if (rv < 0) + { + mcerr("ERROR: Failed to bind SPI port %d to SD slot %d\n", + port, minor); + return rv; + } + + spiinfo("INFO: mmcsd card has been initialized successfully\n"); + return OK; +} diff --git a/boards/arm/stm32f4/stm32f4discovery/src/stm32_netinit.c b/boards/arm/stm32f4/stm32f4discovery/src/stm32_netinit.c new file mode 100644 index 0000000000000..12e0b8aa0d9c0 --- /dev/null +++ b/boards/arm/stm32f4/stm32f4discovery/src/stm32_netinit.c @@ -0,0 +1,41 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f4discovery/src/stm32_netinit.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: arm_netinitialize + ****************************************************************************/ + +#if defined(CONFIG_NET) && !defined(CONFIG_NETDEV_LATEINIT) +void arm_netinitialize(void) +{ +} +#endif diff --git a/boards/arm/stm32/stm32f4discovery/src/stm32_pca9635.c b/boards/arm/stm32f4/stm32f4discovery/src/stm32_pca9635.c similarity index 97% rename from boards/arm/stm32/stm32f4discovery/src/stm32_pca9635.c rename to boards/arm/stm32f4/stm32f4discovery/src/stm32_pca9635.c index b5f8c9935abd6..fabe0a26b574f 100644 --- a/boards/arm/stm32/stm32f4discovery/src/stm32_pca9635.c +++ b/boards/arm/stm32f4/stm32f4discovery/src/stm32_pca9635.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f4discovery/src/stm32_pca9635.c + * boards/arm/stm32f4/stm32f4discovery/src/stm32_pca9635.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f4/stm32f4discovery/src/stm32_pm.c b/boards/arm/stm32f4/stm32f4discovery/src/stm32_pm.c new file mode 100644 index 0000000000000..1a490e035955f --- /dev/null +++ b/boards/arm/stm32f4/stm32f4discovery/src/stm32_pm.c @@ -0,0 +1,75 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f4discovery/src/stm32_pm.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include "arm_internal.h" +#include "stm32_pm.h" +#include "stm32f4discovery.h" + +#ifdef CONFIG_PM + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_pminitialize + * + * Description: + * This function is called by MCU-specific logic at power-on reset in + * order to provide one-time initialization the power management subsystem. + * This function must be called *very* early in the initialization sequence + * *before* any other device drivers are initialized (since they may + * attempt to register with the power management subsystem). + * + * Input Parameters: + * None. + * + * Returned Value: + * None. + * + ****************************************************************************/ + +void arm_pminitialize(void) +{ + /* Initialize the NuttX power management subsystem proper */ + + pm_initialize(); + +#if defined(CONFIG_ARCH_IDLE_CUSTOM) && defined(CONFIG_PM_BUTTONS) + /* Initialize the buttons to wake up the system from low power modes */ + + stm32_pm_buttons(); +#endif + + /* Initialize the LED PM */ + + stm32_led_pminitialize(); +} + +#endif /* CONFIG_PM */ diff --git a/boards/arm/stm32f4/stm32f4discovery/src/stm32_pmbuttons.c b/boards/arm/stm32f4/stm32f4discovery/src/stm32_pmbuttons.c new file mode 100644 index 0000000000000..bde3abd4658d5 --- /dev/null +++ b/boards/arm/stm32f4/stm32f4discovery/src/stm32_pmbuttons.c @@ -0,0 +1,122 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f4discovery/src/stm32_pmbuttons.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include +#include + +#include +#include +#include + +#include "arm_internal.h" +#include "nvic.h" +#include "stm32_pwr.h" +#include "stm32_pm.h" +#include "stm32f4discovery.h" + +#if defined(CONFIG_PM) && defined(CONFIG_ARCH_IDLE_CUSTOM) && defined(CONFIG_PM_BUTTONS) + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +#ifndef CONFIG_ARCH_BUTTONS +# error "CONFIG_ARCH_BUTTONS is not defined in the configuration" +#endif + +#ifndef CONFIG_ARCH_IRQBUTTONS +# warning "CONFIG_ARCH_IRQBUTTONS is not defined in the configuration" +#endif + +#ifndef CONFIG_PM_BUTTON_ACTIVITY +# define CONFIG_PM_BUTTON_ACTIVITY 10 +#endif + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +#ifdef CONFIG_ARCH_IRQBUTTONS +static int button_handler(int irq, void *context, void *arg); +#endif /* CONFIG_ARCH_IRQBUTTONS */ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: button_handler + * + * Description: + * Handle a button wake-up interrupt + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_IRQBUTTONS +static int button_handler(int irq, void *context, void *arg) +{ + /* At this point the MCU should have already awakened. The state + * change will be handled in the IDLE loop when the system is re-awakened + * The button interrupt handler should be totally ignorant of the PM + * activities and should report button activity as if nothing + * special happened. + */ + + pm_activity(PM_IDLE_DOMAIN, CONFIG_PM_BUTTON_ACTIVITY); + return OK; +} +#endif /* CONFIG_ARCH_IRQBUTTONS */ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_pm_buttons + * + * Description: + * Configure the user button of the STM32f4discovery board as EXTI, + * so it is able to wakeup the MCU from the PM_STANDBY mode + * + ****************************************************************************/ + +void stm32_pm_buttons(void) +{ + /* Initialize the button GPIOs */ + + board_button_initialize(); + +#ifdef CONFIG_ARCH_IRQBUTTONS + board_button_irq(0, button_handler, NULL); +#endif +} + +#endif /* CONFIG_PM && CONFIG_ARCH_IDLE_CUSTOM && CONFIG_PM_BUTTONS)*/ diff --git a/boards/arm/stm32f4/stm32f4discovery/src/stm32_pwm.c b/boards/arm/stm32f4/stm32f4discovery/src/stm32_pwm.c new file mode 100644 index 0000000000000..29fe4fe38db82 --- /dev/null +++ b/boards/arm/stm32f4/stm32f4discovery/src/stm32_pwm.c @@ -0,0 +1,125 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f4discovery/src/stm32_pwm.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32_pwm.h" +#include "stm32f4discovery.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* PWM + * + * The stm32f4discovery has no real on-board PWM devices, but the board can + * be configured to output a pulse train using TIM4 CH2. This pin is used by + * FSMC is connected to CN5 just for this purpose: + * + * PD13 FSMC_A18 / MC_TIM4_CH2OUT pin 33 (EnB) + * + * FSMC must be disabled in this case! + */ + +#define HAVE_PWM 1 + +#ifndef CONFIG_PWM +# undef HAVE_PWM +#endif + +#ifndef CONFIG_STM32_TIM4 +# undef HAVE_PWM +#endif + +#ifndef CONFIG_STM32_TIM4_PWM +# undef HAVE_PWM +#endif + +#if !defined(CONFIG_STM32_TIM4_CHANNEL) || CONFIG_STM32_TIM4_CHANNEL != STM32F4DISCOVERY_PWMCHANNEL +# undef HAVE_PWM +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_pwm_setup + * + * Description: + * Initialize PWM and register the PWM device. + * + ****************************************************************************/ + +int stm32_pwm_setup(void) +{ +#ifdef HAVE_PWM + static bool initialized = false; + struct pwm_lowerhalf_s *pwm; + int ret; + + /* Have we already initialized? */ + + if (!initialized) + { + /* Call stm32_pwminitialize() to get an instance of the PWM interface */ + + pwm = stm32_pwminitialize(STM32F4DISCOVERY_PWMTIMER); + if (!pwm) + { + aerr("ERROR: Failed to get the STM32 PWM lower half\n"); + return -ENODEV; + } + + /* Register the PWM driver at "/dev/pwm0" */ + + ret = pwm_register("/dev/pwm0", pwm); + if (ret < 0) + { + aerr("ERROR: pwm_register failed: %d\n", ret); + return ret; + } + + /* Now we are initialized */ + + initialized = true; + } + + return OK; +#else + return -ENODEV; +#endif +} diff --git a/boards/arm/stm32f4/stm32f4discovery/src/stm32_rgbled.c b/boards/arm/stm32f4/stm32f4discovery/src/stm32_rgbled.c new file mode 100644 index 0000000000000..dc245cd37389f --- /dev/null +++ b/boards/arm/stm32f4/stm32f4discovery/src/stm32_rgbled.c @@ -0,0 +1,173 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f4discovery/src/stm32_rgbled.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32_pwm.h" +#include "stm32f4discovery.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +#define HAVE_RGBLED 1 + +#ifndef CONFIG_PWM +# undef HAVE_RGBLED +#endif + +#ifndef CONFIG_STM32_TIM1 +# undef HAVE_RGBLED +#endif + +#ifndef CONFIG_STM32_TIM2 +# undef HAVE_RGBLED +#endif + +#ifndef CONFIG_STM32_TIM3 +# undef HAVE_RGBLED +#endif + +#ifndef CONFIG_STM32_TIM1_PWM +# undef HAVE_RGBLED +#endif + +#ifndef CONFIG_STM32_TIM2_PWM +# undef HAVE_RGBLED +#endif + +#ifndef CONFIG_STM32_TIM3_PWM +# undef HAVE_RGBLED +#endif + +#ifdef HAVE_RGBLED + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_rgbled_setup + * + * Description: + * Configure the RGB LED. + * + ****************************************************************************/ + +int stm32_rgbled_setup(void) +{ + static bool initialized = false; + struct pwm_lowerhalf_s *ledr; + struct pwm_lowerhalf_s *ledg; + struct pwm_lowerhalf_s *ledb; + struct pwm_info_s info; + int ret; + + /* Have we already initialized? */ + + if (!initialized) + { + /* Call stm32_pwminitialize() to get an instance of the PWM interface */ + + ledr = stm32_pwminitialize(1); + if (!ledr) + { + lederr("ERROR: Failed to get the STM32 PWM lower half to LEDR\n"); + return -ENODEV; + } + + /* Define frequency and duty cycle */ + + info.frequency = 100; + info.channels[0].duty = 0; + + /* Initialize LED R */ + + ledr->ops->setup(ledr); + ledr->ops->start(ledr, &info); + + /* Call stm32_pwminitialize() to get an instance of the PWM interface */ + + ledg = stm32_pwminitialize(2); + if (!ledg) + { + lederr("ERROR: Failed to get the STM32 PWM lower half to LEDG\n"); + return -ENODEV; + } + + /* Initialize LED G */ + + ledg->ops->setup(ledg); + ledg->ops->start(ledg, &info); + + /* Call stm32_pwminitialize() to get an instance of the PWM interface */ + + ledb = stm32_pwminitialize(3); + if (!ledb) + { + lederr("ERROR: Failed to get the STM32 PWM lower half to LEDB\n"); + return -ENODEV; + } + + /* Initialize LED B */ + + ledb->ops->setup(ledb); + ledb->ops->start(ledb, &info); + + /* Register the RGB LED diver at "/dev/rgbled0" */ + + ret = rgbled_register("/dev/rgbled0", ledr, ledg, ledb, + 1, CONFIG_STM32_TIM2_CHANNEL, + CONFIG_STM32_TIM3_CHANNEL); + if (ret < 0) + { + lederr("ERROR: rgbled_register failed: %d\n", ret); + return ret; + } + + /* Now we are initialized */ + + initialized = true; + } + + return OK; +} + +#else +# error "HAVE_RGBLED is undefined" +#endif /* HAVE_RGBLED */ diff --git a/boards/arm/stm32f4/stm32f4discovery/src/stm32_sdio.c b/boards/arm/stm32f4/stm32f4discovery/src/stm32_sdio.c new file mode 100644 index 0000000000000..a65801e5b3451 --- /dev/null +++ b/boards/arm/stm32f4/stm32f4discovery/src/stm32_sdio.c @@ -0,0 +1,161 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f4discovery/src/stm32_sdio.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include + +#include "stm32.h" +#include "stm32f4discovery.h" + +#ifdef HAVE_SDIO + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* Card detections requires card support and a card detection GPIO */ + +#define HAVE_NCD 1 +#if !defined(HAVE_SDIO) || !defined(GPIO_SDIO_NCD) +# undef HAVE_NCD +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static struct sdio_dev_s *g_sdio_dev; +#ifdef HAVE_NCD +static bool g_sd_inserted; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_ncd_interrupt + * + * Description: + * Card detect interrupt handler. + * + ****************************************************************************/ + +#ifdef HAVE_NCD +static int stm32_ncd_interrupt(int irq, void *context, void *arg) +{ + bool present; + + present = !stm32_gpioread(GPIO_SDIO_NCD); + if (present != g_sd_inserted) + { + sdio_mediachange(g_sdio_dev, present); + g_sd_inserted = present; + } + + return OK; +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_sdio_initialize + * + * Description: + * Initialize SDIO-based MMC/SD card support + * + ****************************************************************************/ + +int stm32_sdio_initialize(void) +{ + int ret; + +#ifdef HAVE_NCD + /* Configure the card detect GPIO */ + + stm32_configgpio(GPIO_SDIO_NCD); + + /* Register an interrupt handler for the card detect pin */ + + stm32_gpiosetevent(GPIO_SDIO_NCD, true, true, true, + stm32_ncd_interrupt, NULL); +#endif + + /* Mount the SDIO-based MMC/SD block driver */ + + /* First, get an instance of the SDIO interface */ + + finfo("Initializing SDIO slot %d\n", SDIO_SLOTNO); + + g_sdio_dev = sdio_initialize(SDIO_SLOTNO); + if (!g_sdio_dev) + { + ferr("ERROR: Failed to initialize SDIO slot %d\n", SDIO_SLOTNO); + return -ENODEV; + } + + /* Now bind the SDIO interface to the MMC/SD driver */ + + finfo("Bind SDIO to the MMC/SD driver, minor=%d\n", SDIO_MINOR); + + ret = mmcsd_slotinitialize(SDIO_MINOR, g_sdio_dev); + if (ret != OK) + { + ferr("ERROR: Failed to bind SDIO to the MMC/SD driver: %d\n", ret); + return ret; + } + + finfo("Successfully bound SDIO to the MMC/SD driver\n"); + +#ifdef HAVE_NCD + /* Use SD card detect pin to check if a card is g_sd_inserted */ + + g_sd_inserted = !stm32_gpioread(GPIO_SDIO_NCD); + finfo("Card detect : %d\n", g_sd_inserted); + + sdio_mediachange(g_sdio_dev, g_sd_inserted); +#else + /* Assume that the SD card is inserted. What choice do we have? */ + + sdio_mediachange(g_sdio_dev, true); +#endif + + return OK; +} + +#endif /* HAVE_SDIO */ diff --git a/boards/arm/stm32f4/stm32f4discovery/src/stm32_spi.c b/boards/arm/stm32f4/stm32f4discovery/src/stm32_spi.c new file mode 100644 index 0000000000000..dac42a7b178c5 --- /dev/null +++ b/boards/arm/stm32f4/stm32f4discovery/src/stm32_spi.c @@ -0,0 +1,376 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f4discovery/src/stm32_spi.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include + +#include "arm_internal.h" +#include "chip.h" +#include "stm32.h" + +#include "stm32f4discovery.h" + +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || defined(CONFIG_STM32_SPI3) + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_spidev_initialize + * + * Description: + * Called to configure SPI chip select GPIO pins for the stm32f4discovery + * board. + * + ****************************************************************************/ + +void weak_function stm32_spidev_initialize(void) +{ +#ifdef CONFIG_ENC28J60 + stm32_configgpio(GPIO_ENC28J60_CS); + stm32_configgpio(GPIO_ENC28J60_RESET); + stm32_configgpio(GPIO_ENC28J60_INTR); +#endif + +#ifdef CONFIG_NET_W5500 + stm32_configgpio(GPIO_W5500_CS); + stm32_configgpio(GPIO_W5500_RESET); + stm32_configgpio(GPIO_W5500_INTR); +#endif + +#if defined(CONFIG_STM32_SPI1) && defined(CONFIG_SENSORS_LIS3MDL) + stm32_configgpio(GPIO_CS_MEMS); /* MEMS chip select */ +#endif + +#if defined(CONFIG_STM32_SPI1) && defined(CONFIG_CL_MFRC522) + stm32_configgpio(GPIO_CS_MFRC522); /* MFRC522 chip select */ +#endif + +#if defined(CONFIG_STM32_SPI1) && defined(CONFIG_SENSORS_MT6816) + stm32_configgpio(GPIO_CS_MT6816); +#endif + +#if defined(CONFIG_STM32_SPI2) && defined(CONFIG_SENSORS_MAX31855) + stm32_configgpio(GPIO_MAX31855_CS); /* MAX31855 chip select */ +#endif +#if defined(CONFIG_LCD_MAX7219) || defined(CONFIG_LEDS_MAX7219) + stm32_configgpio(GPIO_MAX7219_CS); /* MAX7219 chip select */ +#endif +#ifdef CONFIG_LPWAN_SX127X + stm32_configgpio(GPIO_SX127X_CS); /* SX127x chip select */ +#endif + +#if defined(CONFIG_LCD_ST7567) || defined(CONFIG_LCD_ST7567) + stm32_configgpio(STM32_LCD_CS); /* ST7567/ST7789 chip select */ +#endif +#if defined(CONFIG_STM32_SPI2) && defined(CONFIG_SENSORS_MAX6675) + stm32_configgpio(GPIO_MAX6675_CS); /* MAX6675 chip select */ +#endif +#if defined(CONFIG_LCD_UG2864AMBAG01) || defined(CONFIG_LCD_UG2864HSWEG01) || \ + defined(CONFIG_LCD_SSD1351) + stm32_configgpio(GPIO_OLED_CS); /* OLED chip select */ +# if defined(CONFIG_LCD_UG2864AMBAG01) + stm32_configgpio(GPIO_OLED_A0); /* OLED Command/Data */ +# endif +# if defined(CONFIG_LCD_UG2864HSWEG01) || defined(CONFIG_LCD_SSD1351) + stm32_configgpio(GPIO_OLED_DC); /* OLED Command/Data */ +# endif +#endif +} + +/**************************************************************************** + * Name: stm32_spi1/2/3select and stm32_spi1/2/3status + * + * Description: + * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status + * must be provided by board-specific logic. They are implementations of + * the select and status methods of the SPI interface defined by struct + * spi_ops_s (see include/nuttx/spi/spi.h). All other methods (including + * stm32_spibus_initialize()) are provided by common STM32 logic. To use + * this common SPI logic on your board: + * + * 1. Provide logic in stm32_boardinitialize() to configure SPI chip select + * pins. + * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() functions + * in your board-specific logic. These functions will perform chip + * selection and status operations using GPIOs in the way your board + * is configured. + * 3. Add a calls to stm32_spibus_initialize() in your low level + * application initialization logic + * 4. The handle returned by stm32_spibus_initialize() may then be used to + * bind the SPI driver to higher level logic (e.g., calling + * mmcsd_spislotinitialize(), for example, will bind the SPI driver to + * the SPI MMC/SD driver). + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_SPI1 +void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, + bool selected) +{ + spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : + "de-assert"); + +#ifdef CONFIG_ENC28J60 + if (devid == SPIDEV_ETHERNET(0)) + { + /* Set the GPIO low to select and high to de-select */ + + stm32_gpiowrite(GPIO_ENC28J60_CS, !selected); + } +#endif + +#ifdef CONFIG_NET_W5500 + if (devid == SPIDEV_ETHERNET(0)) + { + /* Set the GPIO low to select and high to de-select */ + + stm32_gpiowrite(GPIO_W5500_CS, !selected); + } +#endif + +#ifdef CONFIG_LPWAN_SX127X + if (devid == SPIDEV_LPWAN(0)) + { + stm32_gpiowrite(GPIO_SX127X_CS, !selected); + } +#endif + +#if defined(CONFIG_LCD_ST7567) || defined(CONFIG_LCD_ST7789) + if (devid == SPIDEV_DISPLAY(0)) + { + stm32_gpiowrite(STM32_LCD_CS, !selected); + } +#endif + +#if defined(CONFIG_LCD_MAX7219) || defined(CONFIG_LEDS_MAX7219) + if (devid == SPIDEV_DISPLAY(0)) + { + stm32_gpiowrite(GPIO_MAX7219_CS, !selected); + } +#endif + +#if defined(CONFIG_LCD_UG2864AMBAG01) || defined(CONFIG_LCD_UG2864HSWEG01) || \ + defined(CONFIG_LCD_SSD1351) + if (devid == SPIDEV_DISPLAY(0)) + { + stm32_gpiowrite(GPIO_OLED_CS, !selected); + } +#endif + +#if defined (CONFIG_SENSORS_LIS3MDL) + if (devid == SPIDEV_ACCELEROMETER(0)) + { + stm32_gpiowrite(GPIO_CS_MEMS, !selected); + } +#endif + +#if defined (CONFIG_SENSORS_MT6816) + if (devid == SPIDEV_MAG_ENCODER(0)) + { + stm32_gpiowrite(GPIO_CS_MT6816, !selected); + } +#endif + +#if defined(CONFIG_CL_MFRC522) + if (devid == SPIDEV_CONTACTLESS(0)) + { + stm32_gpiowrite(GPIO_CS_MFRC522, !selected); + } +#endif +} + +uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) +{ + uint8_t status = 0; + +#ifdef CONFIG_LPWAN_SX127X + if (devid == SPIDEV_LPWAN(0)) + { + status |= SPI_STATUS_PRESENT; + } +#endif + + return status; +} +#endif + +#ifdef CONFIG_STM32_SPI2 +void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid, + bool selected) +{ + spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : + "de-assert"); + +#if defined(CONFIG_SENSORS_MAX31855) + if (devid == SPIDEV_TEMPERATURE(0)) + { + stm32_gpiowrite(GPIO_MAX31855_CS, !selected); + } +#endif + +#if defined(CONFIG_SENSORS_MAX6675) + if (devid == SPIDEV_TEMPERATURE(0)) + { + stm32_gpiowrite(GPIO_MAX6675_CS, !selected); + } +#endif + +#if defined(CONFIG_MMCSD_SPI) + if (devid == SPIDEV_MMCSD(0)) + { + stm32_gpiowrite(GPIO_MMCSD_NSS, !selected); + } +#endif +} + +uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) +{ + uint8_t ret = 0; +#if defined(CONFIG_MMCSD_SPI) + if (devid == SPIDEV_MMCSD(0)) + { + /* Note: SD_DET is pulled high when there's no SD card present. */ + + ret = stm32_gpioread(GPIO_MMCSD_NCD) ? 0 : 1; + } +#endif + + return ret; +} +#endif + +#ifdef CONFIG_STM32_SPI3 +void stm32_spi3select(struct spi_dev_s *dev, uint32_t devid, + bool selected) +{ + spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : + "de-assert"); + +#if defined(CONFIG_WL_GS2200M) + if (devid == SPIDEV_WIRELESS(0)) + { + stm32_gpiowrite(GPIO_GS2200M_CS, !selected); + } +#endif +} + +uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} +#endif + +/**************************************************************************** + * Name: stm32_spi1cmddata + * + * Description: + * Set or clear the SH1101A A0 or SD1306 D/C n bit to select data (true) + * or command (false). This function must be provided by platform-specific + * logic. This is an implementation of the cmddata method of the SPI + * interface defined by struct spi_ops_s (see include/nuttx/spi/spi.h). + * + * Input Parameters: + * + * spi - SPI device that controls the bus the device that requires the CMD/ + * DATA selection. + * devid - If there are multiple devices on the bus, this selects which one + * to select cmd or data. NOTE: This design restricts, for example, + * one one SPI display per SPI bus. + * cmd - true: select command; false: select data + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_SPI_CMDDATA +#ifdef CONFIG_STM32_SPI1 +int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) +{ +#if defined(CONFIG_LCD_ST7567) || defined(CONFIG_LCD_ST7789) + if (devid == SPIDEV_DISPLAY(0)) + { + /* This is the Data/Command control pad which determines whether the + * data bits are data or a command. + */ + + stm32_gpiowrite(STM32_LCD_RS, !cmd); + + return OK; + } +#endif + +#if defined(CONFIG_LCD_UG2864AMBAG01) || defined(CONFIG_LCD_UG2864HSWEG01) || \ + defined(CONFIG_LCD_SSD1351) + if (devid == SPIDEV_DISPLAY(0)) + { + /* "This is the Data/Command control pad which determines whether the + * data bits are data or a command. + * + * A0 = "H": the inputs at D0 to D7 are treated as display data. + * A0 = "L": the inputs at D0 to D7 are transferred to the command + * registers." + */ + +# if defined(CONFIG_LCD_UG2864AMBAG01) + stm32_gpiowrite(GPIO_OLED_A0, !cmd); +# endif +# if defined(CONFIG_LCD_UG2864HSWEG01) || defined(CONFIG_LCD_SSD1351) + stm32_gpiowrite(GPIO_OLED_DC, !cmd); +# endif + return OK; + } +#endif + + return -ENODEV; +} +#endif + +#ifdef CONFIG_STM32_SPI2 +int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) +{ + return -ENODEV; +} +#endif + +#ifdef CONFIG_STM32_SPI3 +int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) +{ + return -ENODEV; +} +#endif +#endif /* CONFIG_SPI_CMDDATA */ + +#endif /* CONFIG_STM32_SPI1 || CONFIG_STM32_SPI2 */ diff --git a/boards/arm/stm32f4/stm32f4discovery/src/stm32_ssd1289.c b/boards/arm/stm32f4/stm32f4discovery/src/stm32_ssd1289.c new file mode 100644 index 0000000000000..f01e75e149434 --- /dev/null +++ b/boards/arm/stm32f4/stm32f4discovery/src/stm32_ssd1289.c @@ -0,0 +1,390 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f4discovery/src/stm32_ssd1289.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include + +#include "arm_internal.h" +#include "stm32.h" +#include "stm32f4discovery.h" + +#ifdef CONFIG_LCD_SSD1289 + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +#ifndef CONFIG_STM32_FSMC +# error "CONFIG_STM32_FSMC is required to use the LCD" +#endif + +/* STM32F4Discovery LCD Hardware Definitions ********************************/ + +/* LCD /CS is CE1 == NOR/SRAM Bank 1 + * + * Bank 1 = 0x60000000 | 0x00000000 + * Bank 2 = 0x60000000 | 0x04000000 + * Bank 3 = 0x60000000 | 0x08000000 + * Bank 4 = 0x60000000 | 0x0c000000 + * + * FSMC address bit 16 is used to distinguish command and data. + * FSMC address bits 0-24 correspond to ARM address bits 1-25. + */ + +#define STM32_LCDBASE ((uintptr_t)(0x60000000 | 0x00000000)) +#define LCD_INDEX (STM32_LCDBASE) +#define LCD_DATA (STM32_LCDBASE + 0x00020000) + +/* SRAM pin definitions */ + +#define LCD_NADDRLINES 1 /* A16 */ +#define LCD_NDATALINES 16 /* D0-15 */ + +/**************************************************************************** + * Private Function Protototypes + ****************************************************************************/ + +/* Low Level LCD access */ + +static void stm32_select(struct ssd1289_lcd_s *dev); +static void stm32_deselect(struct ssd1289_lcd_s *dev); +static void stm32_index(struct ssd1289_lcd_s *dev, uint8_t index); +#ifndef CONFIG_SSD1289_WRONLY +static uint16_t stm32_read(struct ssd1289_lcd_s *dev); +#endif +static void stm32_write(struct ssd1289_lcd_s *dev, uint16_t data); +static void stm32_backlight(struct ssd1289_lcd_s *dev, int power); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* LCD pin mapping + * MAPPING TO STM32 F4: + * + * ---------------- ------------- ---------------------------------- + * STM32 FUNCTION LCD PIN STM32F4Discovery PIN + * ---------------- ------------- ---------------------------------- + * FSMC_D0 D0 pin 4 PD14 P1 pin 46 Conflict (Note 1) + * FSMC_D1 D1 pin 3 PD15 P1 pin 47 Conflict (Note 2) + * FSMC_D2 D2 pin 6 PD0 P2 pin 36 Free I/O + * FSMC_D3 D3 pin 5 PD1 P2 pin 33 Free I/O + * FSMC_D4 D4 pin 8 PE7 P1 pin 25 Free I/O + * FSMC_D5 D5 pin 7 PE8 P1 pin 26 Free I/O + * FSMC_D6 D6 pin 10 PE9 P1 pin 27 Free I/O + * FSMC_D7 D7 pin 9 PE10 P1 pin 28 Free I/O + * FSMC_D8 D8 pin 12 PE11 P1 pin 29 Free I/O + * FSMC_D9 D9 pin 11 PE12 P1 pin 30 Free I/O + * FSMC_D10 D10 pin 14 PE13 P1 pin 31 Free I/O + * FSMC_D11 D11 pin 13 PE14 P1 pin 32 Free I/O + * FSMC_D12 D12 pin 16 PE15 P1 pin 33 Free I/O + * FSMC_D13 D13 pin 15 PD8 P1 pin 40 Free I/O + * FSMC_D14 D14 pin 18 PD9 P1 pin 41 Free I/O + * FSMC_D15 D15 pin 17 PD10 P1 pin 42 Free I/O + * FSMC_A16 RS pin 19 PD11 P1 pin 27 Free I/O + * FSMC_NE1 ~CS pin 10 PD7 P2 pin 27 Free I/O + * FSMC_NWE ~WR pin 22 PD5 P2 pin 29 Conflict (Note 3) + * FSMC_NOE ~RD pin 21 PD4 P2 pin 32 Conflict (Note 4) + * PC6 RESET pin 24 PC6 P2 pin 47 Free I/O + * ---------------- ------------- ---------------------------------- + * + * 1 Used for the RED LED + * 2 Used for the BLUE LED + * 3 Used for the RED LED and for OTG FS Overcurrent. It may be okay to + * use for the parallel interface if PC0 is held high (or floating). + * PC0 enables the STMPS2141STR IC power switch that drives the OTG FS + * host VBUS. + * 4 Also the reset pin for the CS43L22 audio Codec. + */ + +#define GPIO_LCD_RESET (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz|\ + GPIO_OUTPUT_SET|GPIO_PORTC|GPIO_PIN6) + +/* GPIO configurations unique to the LCD */ + +static const uint32_t g_lcdconfig[] = +{ + /* PC6(RESET), FSMC_A16, FSMC_NOE, FSMC_NWE, and FSMC_NE1 */ + + GPIO_LCD_RESET, GPIO_FSMC_A16, GPIO_FSMC_NOE, GPIO_FSMC_NWE, GPIO_FSMC_NE1 +}; +#define NLCD_CONFIG (sizeof(g_lcdconfig)/sizeof(uint32_t)) + +/* This is the driver state structure + * (there is no retained state information) + */ + +static struct ssd1289_lcd_s g_ssd1289 = +{ + .select = stm32_select, + .deselect = stm32_deselect, + .index = stm32_index, +#ifndef CONFIG_SSD1289_WRONLY + .read = stm32_read, +#endif + .write = stm32_write, + .backlight = stm32_backlight +}; + +/* The saved instance of the LCD driver */ + +static struct lcd_dev_s *g_ssd1289drvr; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_select + * + * Description: + * Select the LCD device + * + ****************************************************************************/ + +static void stm32_select(struct ssd1289_lcd_s *dev) +{ + /* Does not apply to this hardware */ +} + +/**************************************************************************** + * Name: stm32_deselect + * + * Description: + * De-select the LCD device + * + ****************************************************************************/ + +static void stm32_deselect(struct ssd1289_lcd_s *dev) +{ + /* Does not apply to this hardware */ +} + +/**************************************************************************** + * Name: stm32_deselect + * + * Description: + * Set the index register + * + ****************************************************************************/ + +static void stm32_index(struct ssd1289_lcd_s *dev, uint8_t index) +{ + putreg16((uint16_t)index, LCD_INDEX); +} + +/**************************************************************************** + * Name: stm32_read + * + * Description: + * Read LCD data (GRAM data or register contents) + * + ****************************************************************************/ + +#ifndef CONFIG_SSD1289_WRONLY +static uint16_t stm32_read(struct ssd1289_lcd_s *dev) +{ + return getreg16(LCD_DATA); +} +#endif + +/**************************************************************************** + * Name: stm32_write + * + * Description: + * Write LCD data (GRAM data or register contents) + * + ****************************************************************************/ + +static void stm32_write(struct ssd1289_lcd_s *dev, uint16_t data) +{ + putreg16((uint16_t)data, LCD_DATA); +} + +/**************************************************************************** + * Name: stm32_write + * + * Description: + * Write LCD data (GRAM data or register contents) + * + ****************************************************************************/ + +static void stm32_backlight(struct ssd1289_lcd_s *dev, int power) +{ +#warning "Missing logic" +} + +/**************************************************************************** + * Name: stm32_selectlcd + * + * Description: + * Initialize to the LCD + * + ****************************************************************************/ + +void stm32_selectlcd(void) +{ + /* Configure GPIO pins */ + + stm32_extmemdata(LCD_NDATALINES); /* Common data lines: D0-D15 */ + stm32_extmemgpios(g_lcdconfig, NLCD_CONFIG); /* LCD-specific control lines */ + + /* Enable AHB clocking to the FSMC */ + + stm32_fsmc_enable(); + + /* Color LCD configuration (LCD configured as follow): + * + * - Data/Address MUX = Disable "FSMC_BCR_MUXEN" just not enable it. + * - Extended Mode = Disable "FSMC_BCR_EXTMOD" + * - Memory Type = SRAM "FSMC_BCR_SRAM" + * - Data Width = 16bit "FSMC_BCR_MWID16" + * - Write Operation = Enable "FSMC_BCR_WREN" + * - Asynchronous Wait = Disable + */ + + /* Bank1 NOR/SRAM control register configuration */ + + putreg32(FSMC_BCR_SRAM | FSMC_BCR_MWID16 | FSMC_BCR_WREN, STM32_FSMC_BCR1); + + /* Bank1 NOR/SRAM timing register configuration */ + + putreg32(FSMC_BTR_ADDSET(5) | FSMC_BTR_ADDHLD(1) | + FSMC_BTR_DATAST(9) | FSMC_BTR_BUSTURN(1) | + FSMC_BTR_CLKDIV(1) | FSMC_BTR_DATLAT(2) | + FSMC_BTR_ACCMODA, STM32_FSMC_BTR1); + + putreg32(0xffffffff, STM32_FSMC_BWTR1); + + /* Enable the bank by setting the MBKEN bit */ + + putreg32(FSMC_BCR_MBKEN | FSMC_BCR_SRAM | + FSMC_BCR_MWID16 | FSMC_BCR_WREN, STM32_FSMC_BCR1); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_lcd_initialize + * + * Description: + * Initialize the LCD video hardware. The initial state of the LCD is fully + * initialized, display memory cleared, and the LCD ready to use, but with + * the power setting at 0 (full off). + * + ****************************************************************************/ + +int board_lcd_initialize(void) +{ + /* Only initialize the driver once */ + + if (!g_ssd1289drvr) + { + lcdinfo("Initializing\n"); + + /* Configure GPIO pins and configure the FSMC to support the LCD */ + + stm32_selectlcd(); + + /* Reset the LCD (active low) */ + + stm32_gpiowrite(GPIO_LCD_RESET, false); + up_mdelay(5); + stm32_gpiowrite(GPIO_LCD_RESET, true); + + /* Configure and enable the LCD */ + + up_mdelay(50); + g_ssd1289drvr = ssd1289_lcdinitialize(&g_ssd1289); + if (!g_ssd1289drvr) + { + lcderr("ERROR: ssd1289_lcdinitialize failed\n"); + return -ENODEV; + } + } + + /* Clear the display (setting it to the color 0=black) */ + +#if 0 /* Already done in the driver */ + ssd1289_clear(g_ssd1289drvr, 0); +#endif + + /* Turn the display off */ + + g_ssd1289drvr->setpower(g_ssd1289drvr, 0); + return OK; +} + +/**************************************************************************** + * Name: board_lcd_getdev + * + * Description: + * Return a a reference to the LCD object for the specified LCD. + * This allows support for multiple LCD devices. + * + ****************************************************************************/ + +struct lcd_dev_s *board_lcd_getdev(int lcddev) +{ + DEBUGASSERT(lcddev == 0); + return g_ssd1289drvr; +} + +/**************************************************************************** + * Name: board_lcd_uninitialize + * + * Description: + * Uninitialize the LCD support + * + ****************************************************************************/ + +void board_lcd_uninitialize(void) +{ + /* Turn the display off */ + + g_ssd1289drvr->setpower(g_ssd1289drvr, 0); +} + +#endif /* CONFIG_LCD_SSD1289 */ diff --git a/boards/arm/stm32f4/stm32f4discovery/src/stm32_ssd1351.c b/boards/arm/stm32f4/stm32f4discovery/src/stm32_ssd1351.c new file mode 100644 index 0000000000000..d11616999a4fc --- /dev/null +++ b/boards/arm/stm32f4/stm32f4discovery/src/stm32_ssd1351.c @@ -0,0 +1,118 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f4discovery/src/stm32_ssd1351.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include +#include +#include +#include +#include + +#include "stm32_gpio.h" +#include "stm32_spi.h" + +#include "stm32f4discovery.h" + +#ifdef CONFIG_LCD_SSD1351 + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* The pin configurations here require that SPI1 is selected */ + +#ifndef CONFIG_STM32_SPI1 +# error "The OLED driver requires CONFIG_STM32_SPI1 in the configuration" +#endif + +#ifndef CONFIG_SSD1351_SPI4WIRE +# error "The configuration requires the SPI 4-wire interface" +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_graphics_setup + * + * Description: + * Called by NX initialization logic to configure the OLED. + * + ****************************************************************************/ + +struct lcd_dev_s *board_graphics_setup(unsigned int devno) +{ + struct spi_dev_s *spi; + struct lcd_dev_s *dev; + + /* Configure the OLED GPIOs. This initial configuration is RESET low, + * putting the OLED into reset state. + */ + + stm32_configgpio(GPIO_OLED_RESET); + + /* Wait a bit then release the OLED from the reset state */ + + up_mdelay(20); + stm32_gpiowrite(GPIO_OLED_RESET, true); + + /* Get the SPI1 port interface */ + + spi = stm32_spibus_initialize(1); + if (spi == NULL) + { + lcderr("ERROR: Failed to initialize SPI port 1\n"); + } + else + { + /* Bind the SPI port to the OLED */ + + dev = ssd1351_initialize(spi, devno); + if (dev == NULL) + { + lcderr("ERROR: Failed to bind SPI port 1 to OLED %d\n", devno); + } + else + { + lcdinfo("Bound SPI port 1 to OLED %d\n", devno); + + /* And turn the OLED on */ + + dev->setpower(dev, LCD_FULL_ON); + return dev; + } + } + + return NULL; +} + +#endif /* CONFIG_LCD_SSD1351 */ diff --git a/boards/arm/stm32/stm32f4discovery/src/stm32_st7032.c b/boards/arm/stm32f4/stm32f4discovery/src/stm32_st7032.c similarity index 97% rename from boards/arm/stm32/stm32f4discovery/src/stm32_st7032.c rename to boards/arm/stm32f4/stm32f4discovery/src/stm32_st7032.c index 6334b89e2ff61..24f3975ba30c6 100644 --- a/boards/arm/stm32/stm32f4discovery/src/stm32_st7032.c +++ b/boards/arm/stm32f4/stm32f4discovery/src/stm32_st7032.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f4discovery/src/stm32_st7032.c + * boards/arm/stm32f4/stm32f4discovery/src/stm32_st7032.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32f4discovery/src/stm32_st7567.c b/boards/arm/stm32f4/stm32f4discovery/src/stm32_st7567.c similarity index 98% rename from boards/arm/stm32/stm32f4discovery/src/stm32_st7567.c rename to boards/arm/stm32f4/stm32f4discovery/src/stm32_st7567.c index ec7a72af4bd41..8ce4280fa7099 100644 --- a/boards/arm/stm32/stm32f4discovery/src/stm32_st7567.c +++ b/boards/arm/stm32f4/stm32f4discovery/src/stm32_st7567.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f4discovery/src/stm32_st7567.c + * boards/arm/stm32f4/stm32f4discovery/src/stm32_st7567.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32f4discovery/src/stm32_st7789.c b/boards/arm/stm32f4/stm32f4discovery/src/stm32_st7789.c similarity index 98% rename from boards/arm/stm32/stm32f4discovery/src/stm32_st7789.c rename to boards/arm/stm32f4/stm32f4discovery/src/stm32_st7789.c index 79d9586028d12..43820a435bc1d 100644 --- a/boards/arm/stm32/stm32f4discovery/src/stm32_st7789.c +++ b/boards/arm/stm32f4/stm32f4discovery/src/stm32_st7789.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f4discovery/src/stm32_st7789.c + * boards/arm/stm32f4/stm32f4discovery/src/stm32_st7789.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f4/stm32f4discovery/src/stm32_sx127x.c b/boards/arm/stm32f4/stm32f4discovery/src/stm32_sx127x.c new file mode 100644 index 0000000000000..162d349a3fce1 --- /dev/null +++ b/boards/arm/stm32f4/stm32f4discovery/src/stm32_sx127x.c @@ -0,0 +1,203 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f4discovery/src/stm32_sx127x.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include "stm32_gpio.h" +#include "stm32_exti.h" +#include "stm32_spi.h" + +#include "stm32f4discovery.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* SX127X on SPI1 bus */ + +#define SX127X_SPI 1 + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +static void sx127x_chip_reset(void); +static int sx127x_opmode_change(int opmode); +static int sx127x_freq_select(uint32_t freq); +static int sx127x_pa_select(bool enable); +static int sx127x_irq0_attach(xcpt_t isr, void *arg); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +struct sx127x_lower_s lower = +{ + .irq0attach = sx127x_irq0_attach, + .reset = sx127x_chip_reset, + .opmode_change = sx127x_opmode_change, + .freq_select = sx127x_freq_select, + .pa_select = sx127x_pa_select, + .pa_force = false +}; + +static bool g_high_power_output = false; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: sx127x_irq0_attach + ****************************************************************************/ + +static int sx127x_irq0_attach(xcpt_t isr, void *arg) +{ + wlinfo("Attach DIO0 IRQ\n"); + + /* IRQ on rising edge */ + + stm32_gpiosetevent(GPIO_SX127X_DIO0, true, false, false, isr, arg); + return OK; +} + +/**************************************************************************** + * Name: sx127x_chip_reset + ****************************************************************************/ + +static void sx127x_chip_reset(void) +{ + wlinfo("SX127X RESET\n"); + + /* Configure reset as output */ + + stm32_configgpio(GPIO_SX127X_RESET); + + /* Set pin to zero */ + + stm32_gpiowrite(GPIO_SX127X_RESET, false); + + /* Wait 1 ms */ + + nxsched_usleep(1000); + + /* Configure reset as input */ + + stm32_configgpio(GPIO_SX127X_RESET | GPIO_INPUT | GPIO_FLOAT); + + /* Wait 10 ms */ + + nxsched_usleep(10000); +} + +/**************************************************************************** + * Name: sx127x_opmode_change + ****************************************************************************/ + +static int sx127x_opmode_change(int opmode) +{ + /* Nothing to do */ + + return OK; +} + +/**************************************************************************** + * Name: sx127x_freq_select + ****************************************************************************/ + +static int sx127x_freq_select(uint32_t freq) +{ + int ret = OK; + + /* Only HF supported (BAND3 - 860-930 MHz) */ + + if (freq < SX127X_HFBAND_THR) + { + ret = -EINVAL; + wlerr("LF band not supported\n"); + } + + return ret; +} + +/**************************************************************************** + * Name: sx127x_pa_select + ****************************************************************************/ + +static int sx127x_pa_select(bool enable) +{ + g_high_power_output = enable; + return OK; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +int stm32_lpwaninitialize(void) +{ + struct spi_dev_s *spidev; + int ret = OK; + + wlinfo("Register the sx127x module\n"); + + /* Setup DIO0 */ + + stm32_configgpio(GPIO_SX127X_DIO0); + + /* Init SPI bus */ + + spidev = stm32_spibus_initialize(SX127X_SPI); + if (!spidev) + { + wlerr("ERROR: Failed to initialize SPI %d bus\n", SX127X_SPI); + ret = -ENODEV; + goto errout; + } + + /* Initialize SX127X */ + + ret = sx127x_register(spidev, &lower); + if (ret < 0) + { + wlerr("ERROR: Failed to register sx127x\n"); + goto errout; + } + +errout: + return ret; +} diff --git a/boards/arm/stm32f4/stm32f4discovery/src/stm32_timer.c b/boards/arm/stm32f4/stm32f4discovery/src/stm32_timer.c new file mode 100644 index 0000000000000..4b89cf2f84487 --- /dev/null +++ b/boards/arm/stm32f4/stm32f4discovery/src/stm32_timer.c @@ -0,0 +1,67 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f4discovery/src/stm32_timer.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include + +#include "stm32_tim.h" +#include "stm32f4discovery.h" + +#ifdef CONFIG_TIMER + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_timer_driver_setup + * + * Description: + * Configure the timer driver. + * + * Input Parameters: + * devpath - The full path to the timer device. + * This should be of the form /dev/timer0 + * timer - The timer's number. + * + * Returned Value: + * Zero (OK) is returned on success; A negated errno value is returned + * to indicate the nature of any failure. + * + ****************************************************************************/ + +int stm32_timer_driver_setup(const char *devpath, int timer) +{ + return stm32_timer_initialize(devpath, timer); +} + +#endif diff --git a/boards/arm/stm32/stm32f4discovery/src/stm32_ug2864ambag01.c b/boards/arm/stm32f4/stm32f4discovery/src/stm32_ug2864ambag01.c similarity index 98% rename from boards/arm/stm32/stm32f4discovery/src/stm32_ug2864ambag01.c rename to boards/arm/stm32f4/stm32f4discovery/src/stm32_ug2864ambag01.c index 76be6cf99e1bf..17badadd6d0be 100644 --- a/boards/arm/stm32/stm32f4discovery/src/stm32_ug2864ambag01.c +++ b/boards/arm/stm32f4/stm32f4discovery/src/stm32_ug2864ambag01.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f4discovery/src/stm32_ug2864ambag01.c + * boards/arm/stm32f4/stm32f4discovery/src/stm32_ug2864ambag01.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32f4discovery/src/stm32_ug2864hsweg01.c b/boards/arm/stm32f4/stm32f4discovery/src/stm32_ug2864hsweg01.c similarity index 98% rename from boards/arm/stm32/stm32f4discovery/src/stm32_ug2864hsweg01.c rename to boards/arm/stm32f4/stm32f4discovery/src/stm32_ug2864hsweg01.c index e9d2fb8771ede..4b4d62620c907 100644 --- a/boards/arm/stm32/stm32f4discovery/src/stm32_ug2864hsweg01.c +++ b/boards/arm/stm32f4/stm32f4discovery/src/stm32_ug2864hsweg01.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f4discovery/src/stm32_ug2864hsweg01.c + * boards/arm/stm32f4/stm32f4discovery/src/stm32_ug2864hsweg01.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f4/stm32f4discovery/src/stm32_uid.c b/boards/arm/stm32f4/stm32f4discovery/src/stm32_uid.c new file mode 100644 index 0000000000000..65bbd76240920 --- /dev/null +++ b/boards/arm/stm32f4/stm32f4discovery/src/stm32_uid.c @@ -0,0 +1,68 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f4discovery/src/stm32_uid.c + * + * SPDX-License-Identifier: BSD-3-Clause + * SPDX-FileCopyrightText: 2015 Marawan Ragab. All rights reserved. + * SPDX-FileContributor: Marawan Ragab + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include "stm32_uid.h" + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +#if defined(CONFIG_BOARDCTL_UNIQUEID) +int board_uniqueid(uint8_t *uniqueid) +{ + if (uniqueid == NULL) + { + return -EINVAL; + } + + stm32_get_uniqueid(uniqueid); + return OK; +} +#endif diff --git a/boards/arm/stm32f4/stm32f4discovery/src/stm32_usb.c b/boards/arm/stm32f4/stm32f4discovery/src/stm32_usb.c new file mode 100644 index 0000000000000..34f386343430c --- /dev/null +++ b/boards/arm/stm32f4/stm32f4discovery/src/stm32_usb.c @@ -0,0 +1,340 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f4discovery/src/stm32_usb.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include "arm_internal.h" +#include "stm32.h" +#include "stm32_otgfs.h" +#include "stm32f4discovery.h" + +#ifdef CONFIG_STM32_OTGFS + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#if defined(CONFIG_USBDEV) || defined(CONFIG_USBHOST) +# define HAVE_USB 1 +#else +# warning "CONFIG_STM32_OTGFS is enabled but neither CONFIG_USBDEV nor CONFIG_USBHOST" +# undef HAVE_USB +#endif + +#ifndef CONFIG_STM32F4DISCO_USBHOST_PRIO +# define CONFIG_STM32F4DISCO_USBHOST_PRIO 100 +#endif + +#ifndef CONFIG_STM32F4DISCO_USBHOST_STACKSIZE +# define CONFIG_STM32F4DISCO_USBHOST_STACKSIZE 1024 +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +static struct usbhost_connection_s *g_usbconn; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: usbhost_waiter + * + * Description: + * Wait for USB devices to be connected. + * + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +static int usbhost_waiter(int argc, char *argv[]) +{ + struct usbhost_hubport_s *hport; + + uinfo("Running\n"); + for (; ; ) + { + /* Wait for the device to change state */ + + DEBUGVERIFY(CONN_WAIT(g_usbconn, &hport)); + uinfo("%s\n", hport->connected ? "connected" : "disconnected"); + + /* Did we just become connected? */ + + if (hport->connected) + { + /* Yes.. enumerate the newly connected device */ + + CONN_ENUMERATE(g_usbconn, hport); + } + } + + /* Keep the compiler from complaining */ + + return 0; +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_usbinitialize + * + * Description: + * Called from stm32_usbinitialize very early in initialization to setup + * USB-related GPIO pins for the STM32F4Discovery board. + * + ****************************************************************************/ + +void stm32_usbinitialize(void) +{ + /* The OTG FS has an internal soft pull-up. + * No GPIO configuration is required + */ + + /* Configure the OTG FS VBUS sensing GPIO, + * Power On, and Overcurrent GPIOs + */ + +#ifdef CONFIG_STM32_OTGFS + stm32_configgpio(GPIO_OTGFS_VBUS); + stm32_configgpio(GPIO_OTGFS_PWRON); + stm32_configgpio(GPIO_OTGFS_OVER); +#endif +} + +/**************************************************************************** + * Name: stm32_usbhost_initialize + * + * Description: + * Called at application startup time to initialize the USB host + * functionality. + * This function will start a thread that will monitor for device + * connection/disconnection events. + * + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +int stm32_usbhost_initialize(void) +{ + int ret; + + /* First, register all of the class drivers needed to support the drivers + * that we care about: + */ + + uinfo("Register class drivers\n"); + +#ifdef CONFIG_USBHOST_HUB + /* Initialize USB hub class support */ + + ret = usbhost_hub_initialize(); + if (ret < 0) + { + uerr("ERROR: usbhost_hub_initialize failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_USBHOST_MSC + /* Register the USB mass storage class class */ + + ret = usbhost_msc_initialize(); + if (ret != OK) + { + uerr("ERROR: Failed to register the mass storage class: %d\n", ret); + } +#endif + +#ifdef CONFIG_USBHOST_CDCACM + /* Register the CDC/ACM serial class */ + + ret = usbhost_cdcacm_initialize(); + if (ret != OK) + { + uerr("ERROR: Failed to register the CDC/ACM serial class: %d\n", ret); + } +#endif + +#ifdef CONFIG_USBHOST_HIDKBD + /* Initialize the HID keyboard class */ + + ret = usbhost_kbdinit(); + if (ret != OK) + { + uerr("ERROR: Failed to register the HID keyboard class\n"); + } +#endif + +#ifdef CONFIG_USBHOST_HIDMOUSE + /* Initialize the HID mouse class */ + + ret = usbhost_mouse_init(); + if (ret != OK) + { + uerr("ERROR: Failed to register the HID mouse class\n"); + } +#endif + +#ifdef CONFIG_USBHOST_XBOXCONTROLLER + /* Initialize the HID mouse class */ + + ret = usbhost_xboxcontroller_init(); + if (ret != OK) + { + uerr("ERROR: Failed to register the XBox Controller class\n"); + } +#endif + + /* Then get an instance of the USB host interface */ + + uinfo("Initialize USB host\n"); + g_usbconn = stm32_otgfshost_initialize(0); + if (g_usbconn) + { + /* Start a thread to handle device connection. */ + + uinfo("Start usbhost_waiter\n"); + + ret = kthread_create("usbhost", CONFIG_STM32F4DISCO_USBHOST_PRIO, + CONFIG_STM32F4DISCO_USBHOST_STACKSIZE, + usbhost_waiter, NULL); + return ret < 0 ? -ENOEXEC : OK; + } + + return -ENODEV; +} +#endif + +/**************************************************************************** + * Name: stm32_usbhost_vbusdrive + * + * Description: + * Enable/disable driving of VBUS 5V output. This function must be + * provided be each platform that implements the STM32 OTG FS host + * interface + * + * "On-chip 5 V VBUS generation is not supported. For this reason, a + * charge pump or, if 5 V are available on the application board, a + * basic power switch, must be added externally to drive the 5 V VBUS + * line. The external charge pump can be driven by any GPIO output. + * When the application decides to power on VBUS using the chosen GPIO, + * it must also set the port power bit in the host port control and + * status register (PPWR bit in OTG_FS_HPRT). + * + * "The application uses this field to control power to this port, + * and the core clears this bit on an overcurrent condition." + * + * Input Parameters: + * iface - For future growth to handle multiple USB host interface. + * Should be zero. + * enable - true: enable VBUS power; false: disable VBUS power + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +void stm32_usbhost_vbusdrive(int iface, bool enable) +{ + DEBUGASSERT(iface == 0); + + if (enable) + { + /* Enable the Power Switch by driving the enable pin low */ + + stm32_gpiowrite(GPIO_OTGFS_PWRON, false); + } + else + { + /* Disable the Power Switch by driving the enable pin high */ + + stm32_gpiowrite(GPIO_OTGFS_PWRON, true); + } +} +#endif + +/**************************************************************************** + * Name: stm32_setup_overcurrent + * + * Description: + * Setup to receive an interrupt-level callback if an overcurrent + * condition is detected. + * + * Input Parameters: + * handler - New overcurrent interrupt handler + * arg - The argument provided for the interrupt handler + * + * Returned Value: + * Zero (OK) is returned on success. Otherwise, a negated errno value + * is returned to indicate the nature of the failure. + * + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +int stm32_setup_overcurrent(xcpt_t handler, void *arg) +{ + return stm32_gpiosetevent(GPIO_OTGFS_OVER, true, true, true, handler, arg); +} +#endif + +/**************************************************************************** + * Name: stm32_usbsuspend + * + * Description: + * Board logic must provide the stm32_usbsuspend logic if the USBDEV + * driver is used. This function is called whenever the USB enters or + * leaves suspend mode. This is an opportunity for the board logic to + * shutdown clocks, power, etc. while the USB is suspended. + * + ****************************************************************************/ + +#ifdef CONFIG_USBDEV +void stm32_usbsuspend(struct usbdev_s *dev, bool resume) +{ + uinfo("resume: %d\n", resume); +} +#endif + +#endif /* CONFIG_STM32_OTGFS */ diff --git a/boards/arm/stm32f4/stm32f4discovery/src/stm32_usbmsc.c b/boards/arm/stm32f4/stm32f4discovery/src/stm32_usbmsc.c new file mode 100644 index 0000000000000..327275dd7fee7 --- /dev/null +++ b/boards/arm/stm32f4/stm32f4discovery/src/stm32_usbmsc.c @@ -0,0 +1,71 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f4discovery/src/stm32_usbmsc.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include + +#include "stm32.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +#ifndef CONFIG_SYSTEM_USBMSC_DEVMINOR1 +# define CONFIG_SYSTEM_USBMSC_DEVMINOR1 0 +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_usbmsc_initialize + * + * Description: + * Perform architecture specific initialization of the USB MSC device. + * + ****************************************************************************/ + +int board_usbmsc_initialize(int port) +{ + /* If system/usbmsc is built as an NSH command, then SD slot should + * already have been initialized. + * In this case, there is nothing further to be done here. + */ + +#ifndef CONFIG_NSH_BUILTIN_APPS + return stm32_mmcsd_initialize(2, CONFIG_SYSTEM_USBMSC_DEVMINOR1); +#else + return OK; +#endif +} diff --git a/boards/arm/stm32f4/stm32f4discovery/src/stm32_userleds.c b/boards/arm/stm32f4/stm32f4discovery/src/stm32_userleds.c new file mode 100644 index 0000000000000..289923108252a --- /dev/null +++ b/boards/arm/stm32f4/stm32f4discovery/src/stm32_userleds.c @@ -0,0 +1,216 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f4discovery/src/stm32_userleds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32.h" +#include "stm32f4discovery.h" + +#ifndef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* This array maps an LED number to GPIO pin configuration */ + +static uint32_t g_ledcfg[BOARD_NLEDS] = +{ + GPIO_LED1, GPIO_LED2, GPIO_LED3, GPIO_LED4 +}; + +/**************************************************************************** + * Private Function Protototypes + ****************************************************************************/ + +/* LED Power Management */ + +#ifdef CONFIG_PM +static void led_pm_notify(struct pm_callback_s *cb, int domain, + enum pm_state_e pmstate); +static int led_pm_prepare(struct pm_callback_s *cb, int domain, + enum pm_state_e pmstate); +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#ifdef CONFIG_PM +static struct pm_callback_s g_ledscb = +{ + .notify = led_pm_notify, + .prepare = led_pm_prepare, +}; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: led_pm_notify + * + * Description: + * Notify the driver of new power state. This callback is called after + * all drivers have had the opportunity to prepare for the new power state. + * + ****************************************************************************/ + +#ifdef CONFIG_PM +static void led_pm_notify(struct pm_callback_s *cb, int domain, + enum pm_state_e pmstate) +{ + switch (pmstate) + { + case PM_NORMAL: + { + /* Restore normal LEDs operation */ + } + break; + + case PM_IDLE: + { + /* Entering IDLE mode - Turn leds off */ + } + break; + + case PM_STANDBY: + { + /* Entering STANDBY mode - Logic for PM_STANDBY goes here */ + } + break; + + case PM_SLEEP: + { + /* Entering SLEEP mode - Logic for PM_SLEEP goes here */ + } + break; + + default: + { + /* Should not get here */ + } + break; + } +} +#endif + +/**************************************************************************** + * Name: led_pm_prepare + * + * Description: + * Request the driver to prepare for a new power state. This is a warning + * that the system is about to enter into a new power state. The driver + * should begin whatever operations that may be required to enter power + * state. The driver may abort the state change mode by returning a + * non-zero value from the callback function. + * + ****************************************************************************/ + +#ifdef CONFIG_PM +static int led_pm_prepare(struct pm_callback_s *cb, int domain, + enum pm_state_e pmstate) +{ + /* No preparation to change power modes is required by the LEDs driver. + * We always accept the state change by returning OK. + */ + + return OK; +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_userled_initialize + ****************************************************************************/ + +uint32_t board_userled_initialize(void) +{ + /* Configure LED1-4 GPIOs for output */ + + stm32_configgpio(GPIO_LED1); + stm32_configgpio(GPIO_LED2); + stm32_configgpio(GPIO_LED3); + stm32_configgpio(GPIO_LED4); + return BOARD_NLEDS; +} + +/**************************************************************************** + * Name: board_userled + ****************************************************************************/ + +void board_userled(int led, bool ledon) +{ + if ((unsigned)led < BOARD_NLEDS) + { + stm32_gpiowrite(g_ledcfg[led], ledon); + } +} + +/**************************************************************************** + * Name: board_userled_all + ****************************************************************************/ + +void board_userled_all(uint32_t ledset) +{ + stm32_gpiowrite(GPIO_LED1, (ledset & BOARD_LED1_BIT) == 0); + stm32_gpiowrite(GPIO_LED2, (ledset & BOARD_LED2_BIT) == 0); + stm32_gpiowrite(GPIO_LED3, (ledset & BOARD_LED3_BIT) == 0); + stm32_gpiowrite(GPIO_LED4, (ledset & BOARD_LED4_BIT) == 0); +} + +/**************************************************************************** + * Name: stm32_led_pminitialize + ****************************************************************************/ + +#ifdef CONFIG_PM +void stm32_led_pminitialize(void) +{ + /* Register to receive power management callbacks */ + + int ret = pm_register(&g_ledscb); + if (ret != OK) + { + board_autoled_on(LED_ASSERTION); + } +} +#endif /* CONFIG_PM */ + +#endif /* !CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/stm32f4discovery/src/stm32_w5500.c b/boards/arm/stm32f4/stm32f4discovery/src/stm32_w5500.c similarity index 99% rename from boards/arm/stm32/stm32f4discovery/src/stm32_w5500.c rename to boards/arm/stm32f4/stm32f4discovery/src/stm32_w5500.c index 210b7cb9e6042..1524ec0f16b4d 100644 --- a/boards/arm/stm32/stm32f4discovery/src/stm32_w5500.c +++ b/boards/arm/stm32f4/stm32f4discovery/src/stm32_w5500.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f4discovery/src/stm32_w5500.c + * boards/arm/stm32f4/stm32f4discovery/src/stm32_w5500.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32f4discovery/src/stm32f4discovery.h b/boards/arm/stm32f4/stm32f4discovery/src/stm32f4discovery.h similarity index 99% rename from boards/arm/stm32/stm32f4discovery/src/stm32f4discovery.h rename to boards/arm/stm32f4/stm32f4discovery/src/stm32f4discovery.h index ef99b4a2fa74a..2989dc8bc336c 100644 --- a/boards/arm/stm32/stm32f4discovery/src/stm32f4discovery.h +++ b/boards/arm/stm32f4/stm32f4discovery/src/stm32f4discovery.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f4discovery/src/stm32f4discovery.h + * boards/arm/stm32f4/stm32f4discovery/src/stm32f4discovery.h * * SPDX-License-Identifier: Apache-2.0 * @@ -30,7 +30,7 @@ #include #include #include -#include +#include /**************************************************************************** * Pre-processor Definitions diff --git a/boards/arm/stm32f7/common/CMakeLists.txt b/boards/arm/stm32f7/common/CMakeLists.txt index 91bb41fe7fe51..4f86eab35f4d4 100644 --- a/boards/arm/stm32f7/common/CMakeLists.txt +++ b/boards/arm/stm32f7/common/CMakeLists.txt @@ -20,5 +20,4 @@ # # ############################################################################## -add_subdirectory(src) -target_include_directories(board PRIVATE include) +add_subdirectory(${NUTTX_DIR}/boards/arm/common/stm32 stm32_common) diff --git a/boards/arm/stm32f7/common/Kconfig b/boards/arm/stm32f7/common/Kconfig deleted file mode 100644 index 2d926e6634d73..0000000000000 --- a/boards/arm/stm32f7/common/Kconfig +++ /dev/null @@ -1,180 +0,0 @@ -# -# For a description of the syntax of this configuration file, -# see the file kconfig-language.txt in the NuttX tools repository. -# - -config STM32F7_ROMFS - bool "Automount baked-in ROMFS image" - default n - depends on FS_ROMFS - ---help--- - Select STM32F7_ROMFS_IMAGEFILE, STM32F7_ROMFS_DEV_MINOR, STM32F7_ROMFS_MOUNTPOINT - -config STM32F7_ROMFS_DEV_MINOR - int "Minor for the block device backing the data" - depends on STM32F7_ROMFS - default 64 - -config STM32F7_ROMFS_MOUNTPOINT - string "Mountpoint of the custom romfs image" - depends on STM32F7_ROMFS - default "/rom" - -config STM32F7_ROMFS_IMAGEFILE - string "ROMFS image file to include into build" - depends on STM32F7_ROMFS - default "../../../rom.img" - -config STM32F7_SPI_TEST - bool "Enable SPI test" - default n - ---help--- - Enable Spi test - initialize and configure SPI to send - STM32F7_SPI_TEST_MESSAGE text. The text is sent on the - selected SPI Buses with the configured parameters. - Note the CS lines will not be asserted. - -if STM32F7_SPI_TEST - -config STM32F7_SPI_TEST_MESSAGE - string "Text to Send on SPI Bus(es)" - default "Hello World" - depends on STM32F7_SPI_TEST - ---help--- - Text to sent on SPI bus(es) - -config STM32F7_SPI1_TEST - bool "Test SPI bus 1" - default n - depends on STM32F7_SPI_TEST - ---help--- - Enable Spi test - on SPI BUS 1 - -if STM32F7_SPI1_TEST - -config STM32F7_SPI1_TEST_FREQ - int "SPI 1 Clock Freq in Hz" - default 1000000 - depends on STM32F7_SPI1_TEST - ---help--- - Sets SPI 1 Clock Freq - -config STM32F7_SPI1_TEST_BITS - int "SPI 1 number of bits" - default 8 - depends on STM32F7_SPI1_TEST - ---help--- - Sets SPI 1 bit length - -choice - prompt "SPI BUS 1 Clock Mode" - default STM32F7_SPI1_TEST_MODE3 - ---help--- - Sets SPI 1 clock mode - -config STM32F7_SPI1_TEST_MODE0 - bool "CPOL=0 CPHA=0" - -config STM32F7_SPI1_TEST_MODE1 - bool "CPOL=0 CPHA=1" - -config STM32F7_SPI1_TEST_MODE2 - bool "CPOL=1 CPHA=0" - -config STM32F7_SPI1_TEST_MODE3 - bool "CPOL=1 CPHA=1" - -endchoice # "SPI BUS 1 Clock Mode" - -endif # STM32F7_SPI1_TEST - -config STM32F7_SPI2_TEST - bool "Test SPI bus 2" - default n - depends on STM32F7_SPI_TEST - ---help--- - Enable Spi test - on SPI BUS 2 - -if STM32F7_SPI2_TEST - -config STM32F7_SPI2_TEST_FREQ - int "SPI 2 Clock Freq in Hz" - default 12000000 - depends on STM32F7_SPI2_TEST - ---help--- - Sets SPI 2 Clock Freq - -config STM32F7_SPI2_TEST_BITS - int "SPI 2 number of bits" - default 8 - depends on STM32F7_SPI2_TEST - ---help--- - Sets SPI 2 bit length - -choice - prompt "SPI BUS 2 Clock Mode" - default STM32F7_SPI2_TEST_MODE3 - ---help--- - Sets SPI 2 clock mode - -config STM32F7_SPI2_TEST_MODE0 - bool "CPOL=0 CPHA=0" - -config STM32F7_SPI2_TEST_MODE1 - bool "CPOL=0 CPHA=1" - -config STM32F7_SPI2_TEST_MODE2 - bool "CPOL=1 CPHA=0" - -config STM32F7_SPI2_TEST_MODE3 - bool "CPOL=1 CPHA=1" - -endchoice # "SPI BUS 2 Clock Mode" - -endif # STM32F7_SPI2_TEST - -config STM32F7_SPI3_TEST - bool "Test SPI bus 3" - default n - depends on STM32F7_SPI_TEST - ---help--- - Enable Spi test - on SPI BUS 3 - -if STM32F7_SPI3_TEST - -config STM32F7_SPI3_TEST_FREQ - int "SPI 3 Clock Freq in Hz" - default 40000000 - depends on STM32F7_SPI3_TEST - ---help--- - Sets SPI 3 Clock Freq - -config STM32F7_SPI3_TEST_BITS - int "SPI 3 number of bits" - default 8 - depends on STM32F7_SPI3_TEST - ---help--- - Sets SPI 3 bit length - -choice - prompt "SPI BUS 3 Clock Mode" - default STM32F7_SPI3_TEST_MODE3 - ---help--- - Sets SPI 3 clock mode - -config STM32F7_SPI3_TEST_MODE0 - bool "CPOL=0 CPHA=0" - -config STM32F7_SPI3_TEST_MODE1 - bool "CPOL=0 CPHA=1" - -config STM32F7_SPI3_TEST_MODE2 - bool "CPOL=1 CPHA=0" - -config STM32F7_SPI3_TEST_MODE3 - bool "CPOL=1 CPHA=1" - -endchoice # "SPI BUS 3 Clock Mode" - -endif # STM32F7_SPI3_TEST -endif # STM32F7_SPI_TEST diff --git a/boards/arm/stm32f7/common/Makefile b/boards/arm/stm32f7/common/Makefile index 7e0b3fe6cf5d5..ab1a17894f5d6 100644 --- a/boards/arm/stm32f7/common/Makefile +++ b/boards/arm/stm32f7/common/Makefile @@ -22,11 +22,12 @@ include $(TOPDIR)/Make.defs +STM32_BOARD_COMMON_DIR := $(TOPDIR)$(DELIM)boards$(DELIM)arm$(DELIM)common$(DELIM)stm32 + include board/Make.defs -include src/Make.defs +include $(STM32_BOARD_COMMON_DIR)$(DELIM)src$(DELIM)Make.defs DEPPATH += --dep-path board -DEPPATH += --dep-path src include $(TOPDIR)/boards/Board.mk diff --git a/boards/arm/stm32f7/common/include/stm32_bh1750.h b/boards/arm/stm32f7/common/include/stm32_bh1750.h deleted file mode 100644 index 0b2dd373d22e8..0000000000000 --- a/boards/arm/stm32f7/common/include/stm32_bh1750.h +++ /dev/null @@ -1,82 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32f7/common/include/stm32_bh1750.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __BOARDS_ARM_STM32F7_COMMON_INCLUDE_STM32_BH1750_H -#define __BOARDS_ARM_STM32F7_COMMON_INCLUDE_STM32_BH1750_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -#ifdef __cplusplus -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Inline Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: board_bh1750_initialize - * - * Description: - * Initialize and register the BH1750FVI Ambient Light driver. - * - * Input Parameters: - * devno - The device number, used to build the device path as /dev/lightN - * busno - The I2C bus number - * - * Returned Value: - * Zero (OK) on success; a negated errno value on failure. - * - ****************************************************************************/ - -int board_bh1750_initialize(int devno, int busno); - -#undef EXTERN -#ifdef __cplusplus -} -#endif - -#endif /* __BOARDS_ARM_STM32F7_COMMON_INCLUDE_STM32_BH1750_H */ diff --git a/boards/arm/stm32f7/common/include/stm32_romfs.h b/boards/arm/stm32f7/common/include/stm32_romfs.h deleted file mode 100644 index 3b52acfa36fa5..0000000000000 --- a/boards/arm/stm32f7/common/include/stm32_romfs.h +++ /dev/null @@ -1,77 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32f7/common/include/stm32_romfs.h - * - * SPDX-License-Identifier: BSD-3-Clause - * SPDX-FileCopyrightText: 2017 Tomasz Wozniak. All rights reserved. - * SPDX-FileContributor: Tomasz Wozniak - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -#ifndef __BOARDS_ARM_STM32F7_COMMON_INCLUDE_STM32_ROMFS_H -#define __BOARDS_ARM_STM32F7_COMMON_INCLUDE_STM32_ROMFS_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#ifdef CONFIG_STM32F7_ROMFS - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#define ROMFS_SECTOR_SIZE 64 - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_romfs_initialize - * - * Description: - * Registers built-in ROMFS image as block device and mounts it. - * - * Returned Value: - * Zero (OK) on success, a negated errno value on error. - * - * Assumptions/Limitations: - * Memory addresses [romfs_data_begin .. romfs_data_end) should contain - * ROMFS volume data, as included in the assembly snippet above (l. 84). - * - ****************************************************************************/ - -int stm32_romfs_initialize(void); - -#endif /* CONFIG_STM32F7_ROMFS */ - -#endif /* __BOARDS_ARM_STM32F7_COMMON_INCLUDE_STM32_ROMFS_H */ diff --git a/boards/arm/stm32f7/common/src/CMakeLists.txt b/boards/arm/stm32f7/common/src/CMakeLists.txt deleted file mode 100644 index f653591bd15e9..0000000000000 --- a/boards/arm/stm32f7/common/src/CMakeLists.txt +++ /dev/null @@ -1,58 +0,0 @@ -# ############################################################################## -# boards/arm/stm32f7/common/src/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -set(SRCS) - -if(CONFIG_SENSORS_BH1750FVI) - list(APPEND SRCS stm32_bh1750.c) -endif() - -if(CONFIG_SENSORS_BMI270_I2C) - list(APPEND SRCS stm32_bmi270.c) -endif() - -if(CONFIG_AUDIO_CS4344) - list(APPEND SRCS stm32_cs4344.c) -endif() - -if(CONFIG_STM32F7_CAN) - if(CONFIG_STM32F7_CAN_CHARDRIVER) - list(APPEND SRCS stm32_can_setup.c) - endif() - if(CONFIG_STM32F7_CAN_SOCKET) - list(APPEND SRCS stm32_cansock_setup.c) - endif() -endif() - -if(CONFIG_STM32F7_ROMFS) - list(APPEND SRCS stm32_romfs_initialize.c) -endif() - -if(CONFIG_BOARDCTL_RESET) - list(APPEND SRCS stm32_reset.c) -endif() - -if(CONFIG_STM32F7_SPI_TEST) - list(APPEND SRCS stm32_spitest.c) -endif() - -target_sources(board PRIVATE ${SRCS}) diff --git a/boards/arm/stm32f7/common/src/Make.defs b/boards/arm/stm32f7/common/src/Make.defs deleted file mode 100644 index 04321561a588b..0000000000000 --- a/boards/arm/stm32f7/common/src/Make.defs +++ /dev/null @@ -1,62 +0,0 @@ -############################################################################# -# boards/arm/stm32f7/common/src/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################# - -ifeq ($(CONFIG_ARCH_BOARD_COMMON),y) - -ifeq ($(CONFIG_SENSORS_BH1750FVI),y) - CSRCS += stm32_bh1750.c -endif - -ifeq ($(CONFIG_SENSORS_BMI270_I2C),y) - CSRCS += stm32_bmi270.c -endif - -ifeq ($(CONFIG_AUDIO_CS4344),y) - CSRCS += stm32_cs4344.c -endif - -ifeq ($(CONFIG_STM32F7_CAN),y) -ifeq ($(CONFIG_STM32F7_CAN_CHARDRIVER),y) -CSRCS += stm32_can_setup.c -endif -ifeq ($(CONFIG_STM32F7_CAN_SOCKET),y) -CSRCS += stm32_cansock_setup.c -endif -endif - -ifeq ($(CONFIG_STM32F7_ROMFS),y) -CSRCS += stm32_romfs_initialize.c -endif - -ifeq ($(CONFIG_BOARDCTL_RESET),y) -CSRCS += stm32_reset.c -endif - -ifeq ($(CONFIG_STM32F7_SPI_TEST),y) -CSRCS += stm32_spitest.c -endif - -DEPPATH += --dep-path src -VPATH += :src -CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)src - -endif diff --git a/boards/arm/stm32f7/common/src/stm32_bh1750.c b/boards/arm/stm32f7/common/src/stm32_bh1750.c deleted file mode 100644 index 7267173ec412a..0000000000000 --- a/boards/arm/stm32f7/common/src/stm32_bh1750.c +++ /dev/null @@ -1,89 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32f7/common/src/stm32_bh1750.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include -#include - -#include "stm32_i2c.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_bh1750initialize - * - * Description: - * Initialize and register the BH1750FVI Ambient Light driver. - * - * Input Parameters: - * devno - The device number, used to build the device path as /dev/lightN - * busno - The I2C bus number - * - * Returned Value: - * Zero (OK) on success; a negated errno value on failure. - * - ****************************************************************************/ - -int board_bh1750_initialize(int devno, int busno) -{ - struct i2c_master_s *i2c; - char devpath[16]; - int ret; - - sninfo("Initializing BH1750FVI!\n"); - - /* Initialize I2C */ - - i2c = stm32_i2cbus_initialize(busno); - if (!i2c) - { - return -ENODEV; - } - - /* Then register the ambient light sensor */ - - snprintf(devpath, sizeof(devpath), "/dev/light%d", devno); - ret = bh1750fvi_register(devpath, i2c, BH1750FVI_I2C_ADDR); - if (ret < 0) - { - snerr("ERROR: Error registering BH1750FVI\n"); - } - - return ret; -} - diff --git a/boards/arm/stm32f7/common/src/stm32_cs4344.c b/boards/arm/stm32f7/common/src/stm32_cs4344.c deleted file mode 100644 index 88debb7a9c585..0000000000000 --- a/boards/arm/stm32f7/common/src/stm32_cs4344.c +++ /dev/null @@ -1,170 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32f7/common/src/stm32_cs4344.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -#include - -#include "stm32_i2s.h" -#include "stm32_pwr.h" -#include "stm32_rcc.h" - -/**************************************************************************** - * Pre-Processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_cs4344_initialize - * - * Description: - * This function is called by platform-specific, setup logic to configure - * and register the CS4344 device. This function will register the driver - * as /dev/audio/pcm[x] where x is determined by the minor device number. - * - * Input Parameters: - * minor - The input device minor number - * - * Returned Value: - * Zero is returned on success. Otherwise, a negated errno value is - * returned to indicate the nature of the failure. - * - ****************************************************************************/ - -int board_cs4344_initialize(int devno, int port) -{ - struct audio_lowerhalf_s *cs4344; - struct audio_lowerhalf_s *pcm; - struct i2s_dev_s *i2s; - static bool initialized = false; - char devname[12]; - int ret; - - audinfo("minor %d\n", devno); - DEBUGASSERT(devno >= 0 && devno <= 25); - - /* Have we already initialized? Since we never uninitialize we must - * prevent multiple initializations. This is necessary, for example, - * when the touchscreen example is used as a built-in application in - * NSH and can be called numerous time. It will attempt to initialize - * each time. - */ - - if (!initialized) - { - /* Get an instance of the I2S interface for the CS4344 data channel */ - - i2s = stm32_i2sbus_initialize(port); - if (!i2s) - { - auderr("ERROR: Failed to initialize I2S%d\n", port); - ret = -ENODEV; - goto errout; - } - - /* Now we can use this I2S interface to initialize the CS4344 which - * will return an audio interface. - */ - - cs4344 = cs4344_initialize(i2s); - if (!cs4344) - { - auderr("ERROR: Failed to initialize the CS4344\n"); - ret = -ENODEV; - goto errout; - } - - /* No we can embed the CS4344/I2S conglomerate into a PCM decoder - * instance so that we will have a PCM front end for the CS4344 - * driver. - */ - - pcm = pcm_decode_initialize(cs4344); - if (!pcm) - { - auderr("ERROR: Failed create the PCM decoder\n"); - ret = -ENODEV; - goto errout; - } - - /* Create a device name */ - - snprintf(devname, sizeof(devname), "pcm%d", devno); - - /* Finally, we can register the PCM/CS4344/I2S audio device. - * - * Is anyone young enough to remember Rube Goldberg? - */ - - ret = audio_register(devname, pcm); - if (ret < 0) - { - auderr("ERROR: Failed to register /dev/%s device: %d\n", - devname, ret); - goto errout; - } - - /* Now we are initialized */ - - initialized = true; - } - - return OK; - -errout: - return ret; -} - diff --git a/boards/arm/stm32f7/common/src/stm32_reset.c b/boards/arm/stm32f7/common/src/stm32_reset.c deleted file mode 100644 index 1eaa28fe9c7cd..0000000000000 --- a/boards/arm/stm32f7/common/src/stm32_reset.c +++ /dev/null @@ -1,60 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32f7/common/src/stm32_reset.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_reset - * - * Description: - * Reset board. Support for this function is required by board-level - * logic if CONFIG_BOARDCTL_RESET is selected. - * - * Input Parameters: - * status - Status information provided with the reset event. This - * meaning of this status information is board-specific. If not - * used by a board, the value zero may be provided in calls to - * board_reset(). - * - * Returned Value: - * If this function returns, then it was not possible to power-off the - * board due to some constraints. The return value int this case is a - * board-specific reason for the failure to shutdown. - * - ****************************************************************************/ - -int board_reset(int status) -{ - up_systemreset(); - return 0; -} diff --git a/boards/arm/stm32f7/common/src/stm32_romfs_initialize.c b/boards/arm/stm32f7/common/src/stm32_romfs_initialize.c deleted file mode 100644 index 53fe0927d43ba..0000000000000 --- a/boards/arm/stm32f7/common/src/stm32_romfs_initialize.c +++ /dev/null @@ -1,151 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32f7/common/src/stm32_romfs_initialize.c - * - * SPDX-License-Identifier: BSD-3-Clause - * SPDX-FileCopyrightText: Tomasz Wozniak. All rights reserved. - * SPDX-FileContributor: Tomasz Wozniak - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include - -#include -#include -#include "stm32_romfs.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#ifndef CONFIG_STM32F7_ROMFS -# error "CONFIG_STM32F7_ROMFS must be defined" -#endif - -#ifndef CONFIG_STM32F7_ROMFS_IMAGEFILE -# error "CONFIG_STM32F7_ROMFS_IMAGEFILE must be defined" -#endif - -#ifndef CONFIG_STM32F7_ROMFS_DEV_MINOR -# error "CONFIG_STM32F7_ROMFS_DEV_MINOR must be defined" -#endif - -#ifndef CONFIG_STM32F7_ROMFS_MOUNTPOINT -# error "CONFIG_STM32F7_ROMFS_MOUNTPOINT must be defined" -#endif - -#define NSECTORS(size) (((size) + ROMFS_SECTOR_SIZE - 1)/ROMFS_SECTOR_SIZE) - -#define STR2(m) #m -#define STR(m) STR2(m) - -#define MKMOUNT_DEVNAME(m) "/dev/ram" STR(m) -#define MOUNT_DEVNAME MKMOUNT_DEVNAME(CONFIG_STM32F7_ROMFS_DEV_MINOR) - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -__asm__ ( - ".section .rodata, \"a\"\n" - ".balign 16\n" - ".globl romfs_data_begin\n" -"romfs_data_begin:\n" - ".incbin " STR(CONFIG_STM32F7_ROMFS_IMAGEFILE) "\n"\ - \ - ".balign " STR(ROMFS_SECTOR_SIZE) "\n" - ".globl romfs_data_end\n" -"romfs_data_end:\n"); - -extern const uint8_t romfs_data_begin[]; -extern const uint8_t romfs_data_end[]; - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_romfs_initialize - * - * Description: - * Registers the aboveincluded binary file as block device. - * Then mounts the block device as ROMFS filesystems. - * - * Returned Value: - * Zero (OK) on success, a negated errno value on error. - * - * Assumptions/Limitations: - * Memory addresses [romfs_data_begin .. romfs_data_end) should contain - * ROMFS volume data, as included in the assembly snippet above (l. 84). - * - ****************************************************************************/ - -int stm32_romfs_initialize(void) -{ - size_t romfs_data_len; - int ret; - - /* Create a ROM disk for the /etc filesystem */ - - romfs_data_len = romfs_data_end - romfs_data_begin; - - ret = romdisk_register(CONFIG_STM32F7_ROMFS_DEV_MINOR, romfs_data_begin, - NSECTORS(romfs_data_len), ROMFS_SECTOR_SIZE); - if (ret < 0) - { - ferr("ERROR: romdisk_register failed: %d\n", -ret); - return ret; - } - - /* Mount the file system */ - - finfo("Mounting ROMFS filesystem at target=%s with source=%s\n", - CONFIG_STM32F7_ROMFS_MOUNTPOINT, MOUNT_DEVNAME); - - ret = nx_mount(MOUNT_DEVNAME, CONFIG_STM32F7_ROMFS_MOUNTPOINT, - "romfs", MS_RDONLY, NULL); - if (ret < 0) - { - ferr("ERROR: nx_mount(%s,%s,romfs) failed: %d\n", - MOUNT_DEVNAME, CONFIG_STM32F7_ROMFS_MOUNTPOINT, ret); - return ret; - } - - return OK; -} diff --git a/boards/arm/stm32f7/common/src/stm32_spitest.c b/boards/arm/stm32f7/common/src/stm32_spitest.c deleted file mode 100644 index f82b9b8fe645e..0000000000000 --- a/boards/arm/stm32f7/common/src/stm32_spitest.c +++ /dev/null @@ -1,176 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32f7/common/src/stm32_spitest.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include - -#include -#include - -#include "arm_internal.h" -#include "chip.h" -#include "stm32_spi.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#if defined(CONFIG_STM32F7_SPI1_TEST) -# if defined(CONFIG_STM32F7_SPI1_TEST_MODE0) -# define CONFIG_STM32F7_SPI1_TEST_MODE SPIDEV_MODE0 -# elif defined(CONFIG_STM32F7_SPI1_TEST_MODE1) -# define CONFIG_STM32F7_SPI1_TEST_MODE SPIDEV_MODE1 -# elif defined(CONFIG_STM32F7_SPI1_TEST_MODE2) -# define CONFIG_STM32F7_SPI1_TEST_MODE SPIDEV_MODE2 -# elif defined(CONFIG_STM32F7_SPI1_TEST_MODE3) -# define CONFIG_STM32F7_SPI1_TEST_MODE SPIDEV_MODE3 -# else -# error "No CONFIG_STM32F7_SPI1_TEST_MODEx defined" -# endif -#endif - -#if defined(CONFIG_STM32F7_SPI2_TEST) -# if defined(CONFIG_STM32F7_SPI2_TEST_MODE0) -# define CONFIG_STM32F7_SPI2_TEST_MODE SPIDEV_MODE0 -# elif defined(CONFIG_STM32F7_SPI2_TEST_MODE1) -# define CONFIG_STM32F7_SPI2_TEST_MODE SPIDEV_MODE1 -# elif defined(CONFIG_STM32F7_SPI2_TEST_MODE2) -# define CONFIG_STM32F7_SPI2_TEST_MODE SPIDEV_MODE2 -# elif defined(CONFIG_STM32F7_SPI2_TEST_MODE3) -# define CONFIG_STM32F7_SPI2_TEST_MODE SPIDEV_MODE3 -# else -# error "No CONFIG_STM32F7_SPI2_TEST_MODEx defined" -# endif -#endif - -#if defined(CONFIG_STM32F7_SPI3_TEST) -# if defined(CONFIG_STM32F7_SPI3_TEST_MODE0) -# define CONFIG_STM32F7_SPI3_TEST_MODE SPIDEV_MODE0 -# elif defined(CONFIG_STM32F7_SPI3_TEST_MODE1) -# define CONFIG_STM32F7_SPI3_TEST_MODE SPIDEV_MODE1 -# elif defined(CONFIG_STM32F7_SPI3_TEST_MODE2) -# define CONFIG_STM32F7_SPI3_TEST_MODE SPIDEV_MODE2 -# elif defined(CONFIG_STM32F7_SPI3_TEST_MODE3) -# define CONFIG_STM32F7_SPI3_TEST_MODE SPIDEV_MODE3 -# else -# error "No CONFIG_STM32F7_SPI3_TEST_MODEx defined" -# endif -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -#if defined(CONFIG_STM32F7_SPI1) -struct spi_dev_s *g_spi1; -#endif -#if defined(CONFIG_STM32F7_SPI2) -struct spi_dev_s *g_spi2; -#endif -#if defined(CONFIG_STM32F7_SPI3) -struct spi_dev_s *g_spi3; -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_spidev_bus_test - * - * Description: - * Called to create the defined SPI buses and test them by initializing - * them and sending the CONFIG_STM32F7_SPI_TEST_MESSAGE (no chip select). - * - ****************************************************************************/ - -int stm32_spidev_bus_test(void) -{ - /* Configure and test SPI- */ - - uint8_t *tx = (uint8_t *)CONFIG_STM32F7_SPI_TEST_MESSAGE; - -#if defined(CONFIG_STM32F7_SPI1_TEST) - g_spi1 = stm32_spibus_initialize(1); - - if (!g_spi1) - { - syslog(LOG_ERR, "ERROR Failed to initialize SPI port 1\n"); - return -ENODEV; - } - - /* Default SPI1 to STM32F7_SPI1_FREQ and mode */ - - SPI_SETFREQUENCY(g_spi1, CONFIG_STM32F7_SPI1_TEST_FREQ); - SPI_SETBITS(g_spi1, CONFIG_STM32F7_SPI1_TEST_BITS); - SPI_SETMODE(g_spi1, CONFIG_STM32F7_SPI1_TEST_MODE); - SPI_EXCHANGE(g_spi1, tx, NULL, - nitems(CONFIG_STM32F7_SPI_TEST_MESSAGE)); -#endif - -#if defined(CONFIG_STM32F7_SPI2_TEST) - g_spi2 = stm32_spibus_initialize(2); - - if (!g_spi2) - { - syslog(LOG_ERR, "ERROR Failed to initialize SPI port 2\n"); - return -ENODEV; - } - - /* Default SPI2 to STM32F7_SPI2_FREQ and mode */ - - SPI_SETFREQUENCY(g_spi2, CONFIG_STM32F7_SPI2_TEST_FREQ); - SPI_SETBITS(g_spi2, CONFIG_STM32F7_SPI2_TEST_BITS); - SPI_SETMODE(g_spi2, CONFIG_STM32F7_SPI2_TEST_MODE); - SPI_EXCHANGE(g_spi2, tx, NULL, - nitems(CONFIG_STM32F7_SPI_TEST_MESSAGE)); -#endif - -#if defined(CONFIG_STM32F7_SPI3_TEST) - g_spi3 = stm32_spibus_initialize(3); - - if (!g_spi3) - { - syslog(LOG_ERR, "ERROR Failed to initialize SPI port 2\n"); - return -ENODEV; - } - - /* Default SPI3 to STM32F7_SPI3_FREQ and mode */ - - SPI_SETFREQUENCY(g_spi3, CONFIG_STM32F7_SPI3_TEST_FREQ); - SPI_SETBITS(g_spi3, CONFIG_STM32F7_SPI3_TEST_BITS); - SPI_SETMODE(g_spi3, CONFIG_STM32F7_SPI3_TEST_MODE); - SPI_EXCHANGE(g_spi3, tx, NULL, - nitems(CONFIG_STM32F7_SPI_TEST_MESSAGE)); -#endif - - return OK; -} diff --git a/boards/arm/stm32f7/nucleo-f722ze/Kconfig b/boards/arm/stm32f7/nucleo-f722ze/Kconfig index 60ec42530ca0c..884622e3a10b8 100644 --- a/boards/arm/stm32f7/nucleo-f722ze/Kconfig +++ b/boards/arm/stm32f7/nucleo-f722ze/Kconfig @@ -57,22 +57,22 @@ choice config NUCLEO_F722ZE_CONSOLE_ARDUINO bool "Arduino Connector" - select STM32F7_USART6 + select STM32_USART6 select USART6_SERIALDRIVER config NUCLEO_F722ZE_CONSOLE_VIRTUAL bool "Virtual Comport" - select STM32F7_USART3 + select STM32_USART3 select USART3_SERIALDRIVER config NUCLEO_F722ZE_CONSOLE_MORPHO bool "Morpho Connector" - select STM32F7_UART8 + select STM32_UART8 select UART8_SERIALDRIVER config NUCLEO_F722ZE_CONSOLE_MORPHO_UART4 bool "Morpho Connector UART4" - select STM32F7_UART4 + select STM32_UART4 select UART4_SERIALDRIVER config NUCLEO_F722ZE_CONSOLE_NONE @@ -83,7 +83,7 @@ endchoice # "Select Console wiring" choice prompt "CAN1 pins selection" default NUCLEO_F722ZE_CAN1_MAP_PD0PD1 - depends on STM32F7_CAN1 + depends on STM32_CAN1 config NUCLEO_F722ZE_CAN1_MAP_D14D15 bool "CAN1_TX=D14 CAN1_RX=D15" diff --git a/boards/arm/stm32f7/nucleo-f722ze/configs/can/defconfig b/boards/arm/stm32f7/nucleo-f722ze/configs/can/defconfig index 59f5aaad34ef0..1cb4871af1a92 100644 --- a/boards/arm/stm32f7/nucleo-f722ze/configs/can/defconfig +++ b/boards/arm/stm32f7/nucleo-f722ze/configs/can/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH_BOARD_COMMON=y CONFIG_ARCH_BOARD_NUCLEO_F722ZE=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32f7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F722ZE=y CONFIG_ARCH_CHIP_STM32F7=y CONFIG_ARCH_STACKDUMP=y @@ -46,12 +47,12 @@ CONFIG_STACK_COLORATION=y CONFIG_START_DAY=30 CONFIG_START_MONTH=11 CONFIG_START_YEAR=2015 -CONFIG_STM32F7_CAN1=y -CONFIG_STM32F7_CAN_TSEG1=15 -CONFIG_STM32F7_CAN_TSEG2=2 -CONFIG_STM32F7_SERIALBRK_BSDCOMPAT=y -CONFIG_STM32F7_SERIAL_DISABLE_REORDERING=y -CONFIG_STM32F7_USART_BREAKS=y +CONFIG_STM32_CAN1=y +CONFIG_STM32_CAN_TSEG1=15 +CONFIG_STM32_CAN_TSEG2=2 +CONFIG_STM32_SERIALBRK_BSDCOMPAT=y +CONFIG_STM32_SERIAL_DISABLE_REORDERING=y +CONFIG_STM32_USART_BREAKS=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART3_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f7/nucleo-f722ze/configs/cansock/defconfig b/boards/arm/stm32f7/nucleo-f722ze/configs/cansock/defconfig index c03ccde370cb4..59a299a009383 100644 --- a/boards/arm/stm32f7/nucleo-f722ze/configs/cansock/defconfig +++ b/boards/arm/stm32f7/nucleo-f722ze/configs/cansock/defconfig @@ -15,6 +15,7 @@ CONFIG_ARCH_BOARD_COMMON=y CONFIG_ARCH_BOARD_NUCLEO_F722ZE=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32f7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F722ZE=y CONFIG_ARCH_CHIP_STM32F7=y CONFIG_ARCH_STACKDUMP=y @@ -59,13 +60,13 @@ CONFIG_STACK_COLORATION=y CONFIG_START_DAY=30 CONFIG_START_MONTH=11 CONFIG_START_YEAR=2015 -CONFIG_STM32F7_CAN1=y -CONFIG_STM32F7_CAN_SOCKET=y -CONFIG_STM32F7_CAN_TSEG1=15 -CONFIG_STM32F7_CAN_TSEG2=2 -CONFIG_STM32F7_SERIALBRK_BSDCOMPAT=y -CONFIG_STM32F7_SERIAL_DISABLE_REORDERING=y -CONFIG_STM32F7_USART_BREAKS=y +CONFIG_STM32_CAN1=y +CONFIG_STM32_CAN_SOCKET=y +CONFIG_STM32_CAN_TSEG1=15 +CONFIG_STM32_CAN_TSEG2=2 +CONFIG_STM32_SERIALBRK_BSDCOMPAT=y +CONFIG_STM32_SERIAL_DISABLE_REORDERING=y +CONFIG_STM32_USART_BREAKS=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART3_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f7/nucleo-f722ze/configs/composite/defconfig b/boards/arm/stm32f7/nucleo-f722ze/configs/composite/defconfig index f856c74056476..c5ade09840d2a 100644 --- a/boards/arm/stm32f7/nucleo-f722ze/configs/composite/defconfig +++ b/boards/arm/stm32f7/nucleo-f722ze/configs/composite/defconfig @@ -11,6 +11,7 @@ CONFIG_ARCH_BOARD="nucleo-f722ze" CONFIG_ARCH_BOARD_NUCLEO_F722ZE=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32f7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F722ZE=y CONFIG_ARCH_CHIP_STM32F7=y CONFIG_ARCH_STACKDUMP=y @@ -70,10 +71,10 @@ CONFIG_STACK_COLORATION=y CONFIG_START_DAY=30 CONFIG_START_MONTH=11 CONFIG_START_YEAR=2015 -CONFIG_STM32F7_OTGFS=y -CONFIG_STM32F7_SERIALBRK_BSDCOMPAT=y -CONFIG_STM32F7_SERIAL_DISABLE_REORDERING=y -CONFIG_STM32F7_USART_BREAKS=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_SERIALBRK_BSDCOMPAT=y +CONFIG_STM32_SERIAL_DISABLE_REORDERING=y +CONFIG_STM32_USART_BREAKS=y CONFIG_SYSTEM_COMPOSITE=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 diff --git a/boards/arm/stm32f7/nucleo-f722ze/configs/nsh/defconfig b/boards/arm/stm32f7/nucleo-f722ze/configs/nsh/defconfig index 2e7c9a4dabd62..d1dd0b02677db 100644 --- a/boards/arm/stm32f7/nucleo-f722ze/configs/nsh/defconfig +++ b/boards/arm/stm32f7/nucleo-f722ze/configs/nsh/defconfig @@ -13,6 +13,7 @@ CONFIG_ARCH_BOARD="nucleo-f722ze" CONFIG_ARCH_BOARD_NUCLEO_F722ZE=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32f7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F722ZE=y CONFIG_ARCH_CHIP_STM32F7=y CONFIG_ARCH_STACKDUMP=y @@ -42,9 +43,9 @@ CONFIG_STACK_COLORATION=y CONFIG_START_DAY=30 CONFIG_START_MONTH=11 CONFIG_START_YEAR=2015 -CONFIG_STM32F7_SERIALBRK_BSDCOMPAT=y -CONFIG_STM32F7_SERIAL_DISABLE_REORDERING=y -CONFIG_STM32F7_USART_BREAKS=y +CONFIG_STM32_SERIALBRK_BSDCOMPAT=y +CONFIG_STM32_SERIAL_DISABLE_REORDERING=y +CONFIG_STM32_USART_BREAKS=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART6_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f7/nucleo-f722ze/include/board.h b/boards/arm/stm32f7/nucleo-f722ze/include/board.h index b1094208baea6..ad312ccc4d4aa 100644 --- a/boards/arm/stm32f7/nucleo-f722ze/include/board.h +++ b/boards/arm/stm32f7/nucleo-f722ze/include/board.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32F7_NUCLEO_F722ZE_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32F7_NUCLEO_F722ZE_INCLUDE_BOARD_H +#ifndef __BOARDS_ARM_STM32_NUCLEO_F722ZE_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32_NUCLEO_F722ZE_INCLUDE_BOARD_H /**************************************************************************** * Included Files @@ -106,7 +106,7 @@ /* Configure factors for PLLSAI clock */ -#define CONFIG_STM32F7_PLLSAI 1 +#define CONFIG_STM32_PLLSAI 1 #define STM32_RCC_PLLSAICFGR_PLLSAIN RCC_PLLSAICFGR_PLLSAIN(192) #define STM32_RCC_PLLSAICFGR_PLLSAIP RCC_PLLSAICFGR_PLLSAIP(8) #define STM32_RCC_PLLSAICFGR_PLLSAIQ RCC_PLLSAICFGR_PLLSAIQ(4) @@ -125,7 +125,7 @@ /* Configure factors for PLLI2S clock */ -#define CONFIG_STM32F7_PLLI2S 1 +#define CONFIG_STM32_PLLI2S 1 #define STM32_RCC_PLLI2SCFGR_PLLI2SN RCC_PLLI2SCFGR_PLLI2SN(192) #define STM32_RCC_PLLI2SCFGR_PLLI2SP RCC_PLLI2SCFGR_PLLI2SP(2) #define STM32_RCC_PLLI2SCFGR_PLLI2SQ RCC_PLLI2SCFGR_PLLI2SQ(2) @@ -567,4 +567,4 @@ #define GPIO_OTGFS_DP (GPIO_OTGFS_DP_0|GPIO_SPEED_100MHz) #define GPIO_OTGFS_ID (GPIO_OTGFS_ID_0|GPIO_SPEED_100MHz) -#endif /* __BOARDS_ARM_STM32F7_NUCLEO_F722ZE_INCLUDE_BOARD_H */ +#endif /* __BOARDS_ARM_STM32_NUCLEO_F722ZE_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32f7/nucleo-f722ze/src/CMakeLists.txt b/boards/arm/stm32f7/nucleo-f722ze/src/CMakeLists.txt index f8b17eb732e90..030ab2e985056 100644 --- a/boards/arm/stm32f7/nucleo-f722ze/src/CMakeLists.txt +++ b/boards/arm/stm32f7/nucleo-f722ze/src/CMakeLists.txt @@ -52,11 +52,11 @@ if(CONFIG_MMCSD) list(APPEND SRCS stm32_sdio.c) endif() -if(CONFIG_STM32F7_OTGFS) +if(CONFIG_STM32_OTGFS) list(APPEND SRCS stm32_usb.c) endif() -if(CONFIG_STM32F7_BBSRAM) +if(CONFIG_STM32_BBSRAM) list(APPEND SRCS stm32_bbsram.c) endif() diff --git a/boards/arm/stm32f7/nucleo-f722ze/src/Make.defs b/boards/arm/stm32f7/nucleo-f722ze/src/Make.defs index 084c954afc3c9..d39777f15f48e 100644 --- a/boards/arm/stm32f7/nucleo-f722ze/src/Make.defs +++ b/boards/arm/stm32f7/nucleo-f722ze/src/Make.defs @@ -54,11 +54,11 @@ ifeq ($(CONFIG_MMCSD),y) CSRCS += stm32_sdio.c endif -ifeq ($(CONFIG_STM32F7_OTGFS),y) +ifeq ($(CONFIG_STM32_OTGFS),y) CSRCS += stm32_usb.c endif -ifeq ($(CONFIG_STM32F7_BBSRAM),y) +ifeq ($(CONFIG_STM32_BBSRAM),y) CSRCS += stm32_bbsram.c endif diff --git a/boards/arm/stm32f7/nucleo-f722ze/src/nucleo-f722ze.h b/boards/arm/stm32f7/nucleo-f722ze/src/nucleo-f722ze.h index 1db1e63552c98..3f71cf026f959 100644 --- a/boards/arm/stm32f7/nucleo-f722ze/src/nucleo-f722ze.h +++ b/boards/arm/stm32f7/nucleo-f722ze/src/nucleo-f722ze.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32F7_NUCLEO_F722ZE_SRC_NUCLEO_F722ZE_H -#define __BOARDS_ARM_STM32F7_NUCLEO_F722ZE_SRC_NUCLEO_F722ZE_H +#ifndef __BOARDS_ARM_STM32_NUCLEO_F722ZE_SRC_NUCLEO_F722ZE_H +#define __BOARDS_ARM_STM32_NUCLEO_F722ZE_SRC_NUCLEO_F722ZE_H /**************************************************************************** * Included Files @@ -100,7 +100,7 @@ #define GPIO_SPI3_CS2 (GPIO_SPI_CS | GPIO_PORTG | GPIO_PIN6) #define GPIO_SPI3_CS3 (GPIO_SPI_CS | GPIO_PORTG | GPIO_PIN7) -#if defined(CONFIG_STM32F7_SDMMC1) || defined(CONFIG_STM32F7_SDMMC2) +#if defined(CONFIG_STM32_SDMMC1) || defined(CONFIG_STM32_SDMMC2) # define HAVE_SDIO #endif @@ -111,7 +111,7 @@ #define SDIO_SLOTNO 0 /* Only one slot */ #ifdef HAVE_SDIO -# if defined(CONFIG_STM32F7_SDMMC1) +# if defined(CONFIG_STM32_SDMMC1) # define GPIO_SDMMC1_NCD (GPIO_INPUT|GPIO_FLOAT|GPIO_EXTI | GPIO_PORTC | GPIO_PIN6) # endif @@ -153,9 +153,9 @@ /* GPIO pins used by the GPIO Subsystem */ #define BOARD_NGPIOIN 4 /* Amount of GPIO Input pins */ -#if defined(CONFIG_STM32F7_TIM1_CH1NOUT) && defined (CONFIG_STM32F7_TIM1_CH2NOUT) +#if defined(CONFIG_STM32_TIM1_CH1NOUT) && defined (CONFIG_STM32_TIM1_CH2NOUT) #define BOARD_NGPIOOUT 8 /* Amount of GPIO Output pins */ -#elif defined(CONFIG_STM32F7_TIM1_CH1NOUT) || defined (CONFIG_STM32F7_TIM1_CH2NOUT) +#elif defined(CONFIG_STM32_TIM1_CH1NOUT) || defined (CONFIG_STM32_TIM1_CH2NOUT) #define BOARD_NGPIOOUT 9 /* Amount of GPIO Output pins */ #else #define BOARD_NGPIOOUT 10 /* Amount of GPIO Output pins */ @@ -179,11 +179,11 @@ GPIO_OUTPUT_SET | GPIO_PORTA |GPIO_PIN5) #define GPIO_OUT5 (GPIO_OUTPUT | GPIO_SPEED_50MHz | \ GPIO_OUTPUT_SET | GPIO_PORTF | GPIO_PIN12) -#if !defined(CONFIG_STM32F7_TIM1_CH1NOUT) +#if !defined(CONFIG_STM32_TIM1_CH1NOUT) #define GPIO_OUT6 (GPIO_OUTPUT | GPIO_SPEED_50MHz | \ GPIO_OUTPUT_SET | GPIO_PORTE | GPIO_PIN8) #endif -#if !defined(CONFIG_STM32F7_TIM1_CH2NOUT) +#if !defined(CONFIG_STM32_TIM1_CH2NOUT) #define GPIO_OUT7 (GPIO_OUTPUT | GPIO_SPEED_50MHz | \ GPIO_OUTPUT_SET | GPIO_PORTE | GPIO_PIN10) #endif @@ -263,7 +263,7 @@ int stm32_sdio_initialize(void); * ****************************************************************************/ -#ifdef CONFIG_STM32F7_OTGFS +#ifdef CONFIG_STM32_OTGFS void stm32_usbinitialize(void); #endif @@ -295,7 +295,7 @@ int stm32_adc_setup(void); * Name: stm32_bbsram_int ****************************************************************************/ -#ifdef CONFIG_STM32F7_BBSRAM +#ifdef CONFIG_STM32_BBSRAM int stm32_bbsram_int(void); #endif @@ -316,4 +316,4 @@ int stm32_gpio_initialize(void); #endif #endif /* __ASSEMBLY__ */ -#endif /* __BOARDS_ARM_STM32F7_NUCLEO_F722ZE_SRC_NUCLEO_F722ZE_H */ +#endif /* __BOARDS_ARM_STM32_NUCLEO_F722ZE_SRC_NUCLEO_F722ZE_H */ diff --git a/boards/arm/stm32f7/nucleo-f722ze/src/stm32_adc.c b/boards/arm/stm32f7/nucleo-f722ze/src/stm32_adc.c index 11dab91d01c85..6f66e59090ff3 100644 --- a/boards/arm/stm32f7/nucleo-f722ze/src/stm32_adc.c +++ b/boards/arm/stm32f7/nucleo-f722ze/src/stm32_adc.c @@ -48,20 +48,20 @@ /* Up to 3 ADC interfaces are supported */ -#if STM32F7_NADC < 3 -# undef CONFIG_STM32F7_ADC3 +#if STM32_NADC < 3 +# undef CONFIG_STM32_ADC3 #endif -#if STM32F7_NADC < 2 -# undef CONFIG_STM32F7_ADC2 +#if STM32_NADC < 2 +# undef CONFIG_STM32_ADC2 #endif -#if STM32F7_NADC < 1 -# undef CONFIG_STM32F7_ADC1 +#if STM32_NADC < 1 +# undef CONFIG_STM32_ADC1 #endif -#if defined(CONFIG_STM32F7_ADC1) || defined(CONFIG_STM32F7_ADC2) || defined(CONFIG_STM32F7_ADC3) -#ifndef CONFIG_STM32F7_ADC1 +#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) || defined(CONFIG_STM32_ADC3) +#ifndef CONFIG_STM32_ADC1 # warning "Channel information only available for ADC1" #endif @@ -79,7 +79,7 @@ * {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 15}; */ -#ifdef CONFIG_STM32F7_ADC1 +#ifdef CONFIG_STM32_ADC1 static const uint8_t g_chanlist[ADC1_NCHANNELS] = { 3, 4, 10, 13 @@ -118,7 +118,7 @@ static const uint32_t g_pinlist[ADC1_NCHANNELS] = int stm32_adc_setup(void) { -#ifdef CONFIG_STM32F7_ADC1 +#ifdef CONFIG_STM32_ADC1 static bool initialized = false; struct adc_dev_s *adc; int ret; @@ -167,5 +167,5 @@ int stm32_adc_setup(void) #endif } -#endif /* CONFIG_STM32F7_ADC1 || CONFIG_STM32F7_ADC2 || CONFIG_STM32F7_ADC3 */ +#endif /* CONFIG_STM32_ADC1 || CONFIG_STM32_ADC2 || CONFIG_STM32_ADC3 */ #endif /* CONFIG_ADC */ diff --git a/boards/arm/stm32f7/nucleo-f722ze/src/stm32_bbsram.c b/boards/arm/stm32f7/nucleo-f722ze/src/stm32_bbsram.c index b0cf74eaf2d3e..ea3b1afbee949 100644 --- a/boards/arm/stm32f7/nucleo-f722ze/src/stm32_bbsram.c +++ b/boards/arm/stm32f7/nucleo-f722ze/src/stm32_bbsram.c @@ -47,7 +47,7 @@ #include "nucleo-f722ze.h" -#ifdef CONFIG_STM32F7_BBSRAM +#ifdef CONFIG_STM32_BBSRAM /**************************************************************************** * Pre-processor Definitions @@ -76,7 +76,7 @@ #define BBSRAM_USED ((4*BBSRAM_HEADER_SIZE)+ \ (BBSRAM_SIZE_FN0+BBSRAM_SIZE_FN1+ \ BBSRAM_SIZE_FN2)) -#define BBSRAM_REAMINING (STM32F7_BBSRAM_SIZE-BBSRAM_USED) +#define BBSRAM_REAMINING (STM32_BBSRAM_SIZE-BBSRAM_USED) #if CONFIG_ARCH_INTERRUPTSTACK <= 3 # define BBSRAM_NUMBER_STACKS 1 #else @@ -265,7 +265,7 @@ typedef struct * Private Data ****************************************************************************/ -static uint8_t g_sdata[STM32F7_BBSRAM_SIZE]; +static uint8_t g_sdata[STM32_BBSRAM_SIZE]; /**************************************************************************** * Private Functions @@ -288,7 +288,7 @@ static int hardfault_get_desc(struct bbsramd_s *desc) } else { - ret = file_ioctl(&filestruct, STM32F7_BBSRAM_GETDESC_IOCTL, + ret = file_ioctl(&filestruct, STM32_BBSRAM_GETDESC_IOCTL, (unsigned long)((uintptr_t)desc)); file_close(&filestruct); @@ -306,7 +306,7 @@ static int hardfault_get_desc(struct bbsramd_s *desc) * Name: copy_reverse ****************************************************************************/ -#if defined(CONFIG_STM32F7_SAVE_CRASHDUMP) +#if defined(CONFIG_STM32_SAVE_CRASHDUMP) static void copy_reverse(stack_word_t *dest, stack_word_t *src, int size) { while (size--) @@ -314,7 +314,7 @@ static void copy_reverse(stack_word_t *dest, stack_word_t *src, int size) *dest++ = *src--; } } -#endif /* CONFIG_STM32F7_SAVE_CRASHDUMP */ +#endif /* CONFIG_STM32_SAVE_CRASHDUMP */ /**************************************************************************** * Public Functions @@ -326,7 +326,7 @@ static void copy_reverse(stack_word_t *dest, stack_word_t *src, int size) int stm32_bbsram_int(void) { - int filesizes[CONFIG_STM32F7_BBSRAM_FILES + 1] = BSRAM_FILE_SIZES; + int filesizes[CONFIG_STM32_BBSRAM_FILES + 1] = BSRAM_FILE_SIZES; char buf[HEADER_TIME_FMT_LEN + 1]; struct bbsramd_s desc; int rv; @@ -338,7 +338,7 @@ int stm32_bbsram_int(void) stm32_bbsraminitialize(BBSRAM_PATH, filesizes); -#if defined(CONFIG_STM32F7_SAVE_CRASHDUMP) +#if defined(CONFIG_STM32_SAVE_CRASHDUMP) /* Panic Logging in Battery Backed Up Files */ /* Do we have an hard fault in BBSRAM? */ @@ -369,7 +369,7 @@ int stm32_bbsram_int(void) " [%s] (%d)\n", HARDFAULT_PATH, rv); } } -#endif /* CONFIG_STM32F7_SAVE_CRASHDUMP */ +#endif /* CONFIG_STM32_SAVE_CRASHDUMP */ return rv; } @@ -378,7 +378,7 @@ int stm32_bbsram_int(void) * Name: board_crashdump ****************************************************************************/ -#if defined(CONFIG_STM32F7_SAVE_CRASHDUMP) +#if defined(CONFIG_STM32_SAVE_CRASHDUMP) void board_crashdump(uintptr_t sp, struct tcb_s *tcb, const char *filename, int lineno, const char *msg, void *regs) @@ -514,6 +514,6 @@ void board_crashdump(uintptr_t sp, struct tcb_s *tcb, arm_lowputc('!'); } } -#endif /* CONFIG_STM32F7_SAVE_CRASHDUMP */ +#endif /* CONFIG_STM32_SAVE_CRASHDUMP */ #endif /* CONFIG_STM32_BBSRAM */ diff --git a/boards/arm/stm32f7/nucleo-f722ze/src/stm32_boot.c b/boards/arm/stm32f7/nucleo-f722ze/src/stm32_boot.c index 82194ab10bf40..41464d917d5b8 100644 --- a/boards/arm/stm32f7/nucleo-f722ze/src/stm32_boot.c +++ b/boards/arm/stm32f7/nucleo-f722ze/src/stm32_boot.c @@ -57,7 +57,7 @@ void stm32_boardinitialize(void) board_autoled_initialize(); #endif -#if defined(CONFIG_STM32F7_OTGFS) || defined(CONFIG_STM32F7_HOST) +#if defined(CONFIG_STM32_OTGFS) || defined(CONFIG_STM32_HOST) stm32_usbinitialize(); #endif diff --git a/boards/arm/stm32f7/nucleo-f722ze/src/stm32_bringup.c b/boards/arm/stm32f7/nucleo-f722ze/src/stm32_bringup.c index 7c848385d0c3a..6339b20c21f21 100644 --- a/boards/arm/stm32f7/nucleo-f722ze/src/stm32_bringup.c +++ b/boards/arm/stm32f7/nucleo-f722ze/src/stm32_bringup.c @@ -40,19 +40,19 @@ #include "stm32_i2c.h" -#ifdef CONFIG_STM32F7_CAN_CHARDRIVER +#ifdef CONFIG_STM32_CAN_CHARDRIVER # include "stm32_can_setup.h" #endif -#ifdef CONFIG_STM32F7_CAN_SOCKET +#ifdef CONFIG_STM32_CAN_SOCKET # include "stm32_cansock_setup.h" #endif -#ifdef CONFIG_STM32F7_ROMFS +#ifdef CONFIG_STM32_ROMFS # include "stm32_romfs.h" #endif -#ifdef CONFIG_STM32F7_SPI_TEST +#ifdef CONFIG_STM32_SPI_TEST # include "stm32_spitest.h" #endif @@ -97,14 +97,14 @@ int stm32_bringup(void) } #endif -#ifdef CONFIG_STM32F7_ROMFS +#ifdef CONFIG_STM32_ROMFS /* Mount the romfs partition */ ret = stm32_romfs_initialize(); if (ret < 0) { syslog(LOG_ERR, "ERROR: Failed to mount romfs at %s: %d\n", - CONFIG_STM32F7_ROMFS_MOUNTPOINT, ret); + CONFIG_STM32_ROMFS_MOUNTPOINT, ret); } #endif @@ -139,7 +139,7 @@ int stm32_bringup(void) } #endif -#ifdef CONFIG_STM32F7_BBSRAM +#ifdef CONFIG_STM32_BBSRAM /* Initialize battery-backed RAM */ stm32_bbsram_int(); @@ -152,7 +152,7 @@ int stm32_bringup(void) } #endif -#ifdef CONFIG_STM32F7_SPI_TEST +#ifdef CONFIG_STM32_SPI_TEST /* Create SPI interfaces */ ret = stm32_spidev_bus_test(); @@ -188,7 +188,7 @@ int stm32_bringup(void) #ifdef CONFIG_SENSORS_QENCODER char buf[9]; -#ifdef CONFIG_STM32F7_TIM1_QE +#ifdef CONFIG_STM32_TIM1_QE snprintf(buf, sizeof(buf), "/dev/qe0"); ret = stm32_qencoder_initialize(buf, 1); if (ret < 0) @@ -200,7 +200,7 @@ int stm32_bringup(void) } #endif -#ifdef CONFIG_STM32F7_TIM3_QE +#ifdef CONFIG_STM32_TIM3_QE snprintf(buf, sizeof(buf), "/dev/qe2"); ret = stm32_qencoder_initialize(buf, 3); if (ret < 0) @@ -212,7 +212,7 @@ int stm32_bringup(void) } #endif -#ifdef CONFIG_STM32F7_TIM4_QE +#ifdef CONFIG_STM32_TIM4_QE snprintf(buf, sizeof(buf), "/dev/qe3"); ret = stm32_qencoder_initialize(buf, 4); if (ret < 0) @@ -224,7 +224,7 @@ int stm32_bringup(void) } #endif -#ifdef CONFIG_STM32F7_TIM8_QE +#ifdef CONFIG_STM32_TIM8_QE snprintf(buf, sizeof(buf), "/dev/qe4"); ret = stm32_qencoder_initialize(buf, 8); if (ret < 0) @@ -238,7 +238,7 @@ int stm32_bringup(void) #endif -#ifdef CONFIG_STM32F7_CAN_CHARDRIVER +#ifdef CONFIG_STM32_CAN_CHARDRIVER ret = stm32_can_setup(); if (ret < 0) { @@ -247,7 +247,7 @@ int stm32_bringup(void) } #endif -#ifdef CONFIG_STM32F7_CAN_SOCKET +#ifdef CONFIG_STM32_CAN_SOCKET ret = stm32_cansock_setup(); if (ret < 0) { @@ -255,7 +255,7 @@ int stm32_bringup(void) } #endif -#if defined(CONFIG_I2C) && defined(CONFIG_STM32F7_I2C1) +#if defined(CONFIG_I2C) && defined(CONFIG_STM32_I2C1) i2c_bus = 1; i2c = stm32_i2cbus_initialize(i2c_bus); if (i2c == NULL) diff --git a/boards/arm/stm32f7/nucleo-f722ze/src/stm32_gpio.c b/boards/arm/stm32f7/nucleo-f722ze/src/stm32_gpio.c index 2ab163679c5dc..20272a1dac87a 100644 --- a/boards/arm/stm32f7/nucleo-f722ze/src/stm32_gpio.c +++ b/boards/arm/stm32f7/nucleo-f722ze/src/stm32_gpio.c @@ -125,10 +125,10 @@ static const uint32_t g_gpiooutputs[BOARD_NGPIOOUT] = GPIO_OUT3, GPIO_OUT4, GPIO_OUT5, -#if !defined(CONFIG_STM32F7_TIM1_CH1NOUT) +#if !defined(CONFIG_STM32_TIM1_CH1NOUT) GPIO_OUT6, #endif -#if !defined(CONFIG_STM32F7_TIM1_CH2NOUT) +#if !defined(CONFIG_STM32_TIM1_CH2NOUT) GPIO_OUT7, #endif }; diff --git a/boards/arm/stm32f7/nucleo-f722ze/src/stm32_pwm.c b/boards/arm/stm32f7/nucleo-f722ze/src/stm32_pwm.c index 1adc20c2cae70..8614a43c51595 100644 --- a/boards/arm/stm32f7/nucleo-f722ze/src/stm32_pwm.c +++ b/boards/arm/stm32f7/nucleo-f722ze/src/stm32_pwm.c @@ -73,7 +73,7 @@ int stm32_pwm_setup(void) { /* Call stm32_pwminitialize() to get an instance of the PWM interface */ -#if defined(CONFIG_STM32F7_TIM1_PWM) +#if defined(CONFIG_STM32_TIM1_PWM) pwm = stm32_pwminitialize(1); if (!pwm) { @@ -89,7 +89,7 @@ int stm32_pwm_setup(void) } #endif -#if defined(CONFIG_STM32F7_TIM2_PWM) +#if defined(CONFIG_STM32_TIM2_PWM) pwm = stm32_pwminitialize(2); if (!pwm) { @@ -105,7 +105,7 @@ int stm32_pwm_setup(void) } #endif -#if defined(CONFIG_STM32F7_TIM3_PWM) +#if defined(CONFIG_STM32_TIM3_PWM) pwm = stm32_pwminitialize(3); if (!pwm) { @@ -121,7 +121,7 @@ int stm32_pwm_setup(void) } #endif -#if defined(CONFIG_STM32F7_TIM4_PWM) +#if defined(CONFIG_STM32_TIM4_PWM) pwm = stm32_pwminitialize(4); if (!pwm) { diff --git a/boards/arm/stm32f7/nucleo-f722ze/src/stm32_spi.c b/boards/arm/stm32f7/nucleo-f722ze/src/stm32_spi.c index c38a390ca09b7..26f3bf756fd1f 100644 --- a/boards/arm/stm32f7/nucleo-f722ze/src/stm32_spi.c +++ b/boards/arm/stm32f7/nucleo-f722ze/src/stm32_spi.c @@ -53,7 +53,7 @@ * Private Data ****************************************************************************/ -#if defined(CONFIG_STM32F7_SPI1) +#if defined(CONFIG_STM32_SPI1) static const uint32_t g_spi1gpio[] = { # if defined(GPIO_SPI1_CS0) @@ -79,7 +79,7 @@ static const uint32_t g_spi1gpio[] = }; #endif -#if defined(CONFIG_STM32F7_SPI2) +#if defined(CONFIG_STM32_SPI2) static const uint32_t g_spi2gpio[] = { # if defined(GPIO_SPI2_CS0) @@ -105,7 +105,7 @@ static const uint32_t g_spi2gpio[] = }; #endif -#if defined(CONFIG_STM32F7_SPI3) +#if defined(CONFIG_STM32_SPI3) static const uint32_t g_spi3gpio[] = { # if defined(GPIO_SPI3_CS0) @@ -148,7 +148,7 @@ void weak_function stm32_spidev_initialize(void) { /* Configure SPI CS GPIO for output */ -#if defined(CONFIG_STM32F7_SPI1) +#if defined(CONFIG_STM32_SPI1) for (int i = 0; i < nitems(g_spi1gpio); i++) { if (g_spi1gpio[i] != 0) @@ -158,7 +158,7 @@ void weak_function stm32_spidev_initialize(void) } #endif -#if defined(CONFIG_STM32F7_SPI2) +#if defined(CONFIG_STM32_SPI2) for (int i = 0; i < nitems(g_spi2gpio); i++) { if (g_spi2gpio[i] != 0) @@ -168,7 +168,7 @@ void weak_function stm32_spidev_initialize(void) } #endif -#if defined(CONFIG_STM32F7_SPI3) +#if defined(CONFIG_STM32_SPI3) for (int i = 0; i < nitems(g_spi3gpio); i++) { if (g_spi3gpio[i] != 0) @@ -206,7 +206,7 @@ void weak_function stm32_spidev_initialize(void) * ****************************************************************************/ -#ifdef CONFIG_STM32F7_SPI1 +#ifdef CONFIG_STM32_SPI1 void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -227,7 +227,7 @@ uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32F7_SPI2 +#ifdef CONFIG_STM32_SPI2 void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -248,7 +248,7 @@ uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32F7_SPI3 +#ifdef CONFIG_STM32_SPI3 void stm32_spi3select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -269,7 +269,7 @@ uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32F7_SPI4 +#ifdef CONFIG_STM32_SPI4 void stm32_spi4select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -283,7 +283,7 @@ uint8_t stm32_spi4status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32F7_SPI5 +#ifdef CONFIG_STM32_SPI5 void stm32_spi5select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -297,7 +297,7 @@ uint8_t stm32_spi5status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32F7_SPI6 +#ifdef CONFIG_STM32_SPI6 void stm32_spi6select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -335,42 +335,42 @@ uint8_t stm32_spi6status(struct spi_dev_s *dev, uint32_t devid) ****************************************************************************/ #ifdef CONFIG_SPI_CMDDATA -#ifdef CONFIG_STM32F7_SPI1 +#ifdef CONFIG_STM32_SPI1 int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32F7_SPI2 +#ifdef CONFIG_STM32_SPI2 int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32F7_SPI3 +#ifdef CONFIG_STM32_SPI3 int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32F7_SPI4 +#ifdef CONFIG_STM32_SPI4 int stm32_spi4cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32F7_SPI5 +#ifdef CONFIG_STM32_SPI5 int stm32_spi5cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32F7_SPI6 +#ifdef CONFIG_STM32_SPI6 int stm32_spi6cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; diff --git a/boards/arm/stm32f7/nucleo-f722ze/src/stm32_usb.c b/boards/arm/stm32f7/nucleo-f722ze/src/stm32_usb.c index 57a304d3a3e64..1a4e5d2f19e4c 100644 --- a/boards/arm/stm32f7/nucleo-f722ze/src/stm32_usb.c +++ b/boards/arm/stm32f7/nucleo-f722ze/src/stm32_usb.c @@ -45,7 +45,7 @@ #include "stm32_otg.h" #include "nucleo-f722ze.h" -#ifdef CONFIG_STM32F7_OTGFS +#ifdef CONFIG_STM32_OTGFS /**************************************************************************** * Pre-processor Definitions @@ -138,7 +138,7 @@ void stm32_usbinitialize(void) * Power On, and Overcurrent GPIOs */ -#ifdef CONFIG_STM32F7_OTGFS +#ifdef CONFIG_STM32_OTGFS stm32_configgpio(GPIO_OTGFS_VBUS); stm32_configgpio(GPIO_OTGFS_PWRON); stm32_configgpio(GPIO_OTGFS_OVER); diff --git a/boards/arm/stm32f7/nucleo-f746zg/Kconfig b/boards/arm/stm32f7/nucleo-f746zg/Kconfig index c1d96afcf0bcd..d59a47ec85b41 100644 --- a/boards/arm/stm32f7/nucleo-f746zg/Kconfig +++ b/boards/arm/stm32f7/nucleo-f746zg/Kconfig @@ -57,22 +57,22 @@ choice config NUCLEO_F746ZG_CONSOLE_ARDUINO bool "Arduino Connector" - select STM32F7_USART6 + select STM32_USART6 select USART6_SERIALDRIVER config NUCLEO_F746ZG_CONSOLE_VIRTUAL bool "Virtual Comport" - select STM32F7_USART3 + select STM32_USART3 select USART3_SERIALDRIVER config NUCLEO_F746ZG_CONSOLE_MORPHO bool "Morpho Connector" - select STM32F7_UART8 + select STM32_UART8 select UART8_SERIALDRIVER config NUCLEO_F746ZG_CONSOLE_MORPHO_UART4 bool "Morpho Connector UART4" - select STM32F7_UART4 + select STM32_UART4 select UART4_SERIALDRIVER config NUCLEO_F746ZG_CONSOLE_NONE @@ -83,7 +83,7 @@ endchoice # "Select Console wiring" choice prompt "CAN1 pins selection" default NUCLEO_F746ZG_CAN1_MAP_PD0PD1 - depends on STM32F7_CAN1 + depends on STM32_CAN1 config NUCLEO_F746ZG_CAN1_MAP_D14D15 bool "CAN1_TX=D14 CAN1_RX=D15" diff --git a/boards/arm/stm32f7/nucleo-f746zg/configs/evalos/defconfig b/boards/arm/stm32f7/nucleo-f746zg/configs/evalos/defconfig index d32e6ac0e4cdf..95125cef76058 100644 --- a/boards/arm/stm32f7/nucleo-f746zg/configs/evalos/defconfig +++ b/boards/arm/stm32f7/nucleo-f746zg/configs/evalos/defconfig @@ -15,6 +15,7 @@ CONFIG_ARCH_BOARD="nucleo-f746zg" CONFIG_ARCH_BOARD_NUCLEO_F746ZG=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32f7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F746ZG=y CONFIG_ARCH_CHIP_STM32F7=y CONFIG_ARCH_STACKDUMP=y @@ -52,9 +53,9 @@ CONFIG_STACK_COLORATION=y CONFIG_START_DAY=30 CONFIG_START_MONTH=11 CONFIG_START_YEAR=2015 -CONFIG_STM32F7_SERIALBRK_BSDCOMPAT=y -CONFIG_STM32F7_SERIAL_DISABLE_REORDERING=y -CONFIG_STM32F7_USART_BREAKS=y +CONFIG_STM32_SERIALBRK_BSDCOMPAT=y +CONFIG_STM32_SERIAL_DISABLE_REORDERING=y +CONFIG_STM32_USART_BREAKS=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART3_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f7/nucleo-f746zg/configs/note/defconfig b/boards/arm/stm32f7/nucleo-f746zg/configs/note/defconfig index 0112b71b52d77..0997aceb7edba 100644 --- a/boards/arm/stm32f7/nucleo-f746zg/configs/note/defconfig +++ b/boards/arm/stm32f7/nucleo-f746zg/configs/note/defconfig @@ -15,6 +15,7 @@ CONFIG_ARCH_BOARD_COMMON=y CONFIG_ARCH_BOARD_NUCLEO_F746ZG=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32f7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F746ZG=y CONFIG_ARCH_CHIP_STM32F7=y CONFIG_ARCH_RAMVECTORS=y @@ -95,46 +96,46 @@ CONFIG_SPI=y CONFIG_START_DAY=30 CONFIG_START_MONTH=11 CONFIG_START_YEAR=2015 -CONFIG_STM32F7_ADC1=y -CONFIG_STM32F7_ADC1_DMA=y -CONFIG_STM32F7_ADC1_SAMPLE_FREQUENCY=5000 -CONFIG_STM32F7_ADC1_TIMTRIG=1 -CONFIG_STM32F7_CAN1=y -CONFIG_STM32F7_CAN1_BAUD=500000 -CONFIG_STM32F7_CAN_TSEG1=5 -CONFIG_STM32F7_CAN_TSEG2=6 -CONFIG_STM32F7_DMA1=y -CONFIG_STM32F7_DMA2=y -CONFIG_STM32F7_ETHMAC=y -CONFIG_STM32F7_PHYADDR=0 -CONFIG_STM32F7_PHYSR=31 -CONFIG_STM32F7_PHYSR_100FD=0x0018 -CONFIG_STM32F7_PHYSR_100HD=0x0008 -CONFIG_STM32F7_PHYSR_10FD=0x0014 -CONFIG_STM32F7_PHYSR_10HD=0x0004 -CONFIG_STM32F7_PHYSR_ALTCONFIG=y -CONFIG_STM32F7_PHYSR_ALTMODE=0x001c -CONFIG_STM32F7_PWM_MULTICHAN=y -CONFIG_STM32F7_SERIALBRK_BSDCOMPAT=y -CONFIG_STM32F7_SERIAL_DISABLE_REORDERING=y -CONFIG_STM32F7_TIM1=y -CONFIG_STM32F7_TIM1_CH1NOUT=y -CONFIG_STM32F7_TIM1_CH1OUT=y -CONFIG_STM32F7_TIM1_CH2NOUT=y -CONFIG_STM32F7_TIM1_CH2OUT=y -CONFIG_STM32F7_TIM1_CHANNEL1=y -CONFIG_STM32F7_TIM1_CHANNEL2=y -CONFIG_STM32F7_TIM1_DEADTIME=10 -CONFIG_STM32F7_TIM1_PWM=y -CONFIG_STM32F7_TIM2=y -CONFIG_STM32F7_TIM2_ADC=y -CONFIG_STM32F7_TIM3=y -CONFIG_STM32F7_TIM3_QE=y -CONFIG_STM32F7_TIM4=y -CONFIG_STM32F7_TIM4_QE=y -CONFIG_STM32F7_TIM8=y -CONFIG_STM32F7_TIM8_QE=y -CONFIG_STM32F7_USART_BREAKS=y +CONFIG_STM32_ADC1=y +CONFIG_STM32_ADC1_DMA=y +CONFIG_STM32_ADC1_SAMPLE_FREQUENCY=5000 +CONFIG_STM32_ADC1_TIMTRIG=1 +CONFIG_STM32_CAN1=y +CONFIG_STM32_CAN1_BAUD=500000 +CONFIG_STM32_CAN_TSEG1=5 +CONFIG_STM32_CAN_TSEG2=6 +CONFIG_STM32_DMA1=y +CONFIG_STM32_DMA2=y +CONFIG_STM32_ETHMAC=y +CONFIG_STM32_PHYADDR=0 +CONFIG_STM32_PHYSR=31 +CONFIG_STM32_PHYSR_100FD=0x0018 +CONFIG_STM32_PHYSR_100HD=0x0008 +CONFIG_STM32_PHYSR_10FD=0x0014 +CONFIG_STM32_PHYSR_10HD=0x0004 +CONFIG_STM32_PHYSR_ALTCONFIG=y +CONFIG_STM32_PHYSR_ALTMODE=0x001c +CONFIG_STM32_PWM_MULTICHAN=y +CONFIG_STM32_SERIALBRK_BSDCOMPAT=y +CONFIG_STM32_SERIAL_DISABLE_REORDERING=y +CONFIG_STM32_TIM1=y +CONFIG_STM32_TIM1_CH1NOUT=y +CONFIG_STM32_TIM1_CH1OUT=y +CONFIG_STM32_TIM1_CH2NOUT=y +CONFIG_STM32_TIM1_CH2OUT=y +CONFIG_STM32_TIM1_CHANNEL1=y +CONFIG_STM32_TIM1_CHANNEL2=y +CONFIG_STM32_TIM1_DEADTIME=10 +CONFIG_STM32_TIM1_PWM=y +CONFIG_STM32_TIM2=y +CONFIG_STM32_TIM2_ADC=y +CONFIG_STM32_TIM3=y +CONFIG_STM32_TIM3_QE=y +CONFIG_STM32_TIM4=y +CONFIG_STM32_TIM4_QE=y +CONFIG_STM32_TIM8=y +CONFIG_STM32_TIM8_QE=y +CONFIG_STM32_USART_BREAKS=y CONFIG_SYSTEM_DHCPC_RENEW=y CONFIG_SYSTEM_NOTE=y CONFIG_SYSTEM_NSH=y diff --git a/boards/arm/stm32f7/nucleo-f746zg/configs/nsh/defconfig b/boards/arm/stm32f7/nucleo-f746zg/configs/nsh/defconfig index ae9b97ca15ce3..c1b3531bf8a6a 100644 --- a/boards/arm/stm32f7/nucleo-f746zg/configs/nsh/defconfig +++ b/boards/arm/stm32f7/nucleo-f746zg/configs/nsh/defconfig @@ -13,6 +13,7 @@ CONFIG_ARCH_BOARD="nucleo-f746zg" CONFIG_ARCH_BOARD_NUCLEO_F746ZG=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32f7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F746ZG=y CONFIG_ARCH_CHIP_STM32F7=y CONFIG_ARCH_STACKDUMP=y @@ -43,10 +44,10 @@ CONFIG_STACK_COLORATION=y CONFIG_START_DAY=30 CONFIG_START_MONTH=11 CONFIG_START_YEAR=2015 -CONFIG_STM32F7_DTCMEXCLUDE=y -CONFIG_STM32F7_SERIALBRK_BSDCOMPAT=y -CONFIG_STM32F7_SERIAL_DISABLE_REORDERING=y -CONFIG_STM32F7_USART_BREAKS=y +CONFIG_STM32_DTCMEXCLUDE=y +CONFIG_STM32_SERIALBRK_BSDCOMPAT=y +CONFIG_STM32_SERIAL_DISABLE_REORDERING=y +CONFIG_STM32_USART_BREAKS=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART3_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f7/nucleo-f746zg/configs/pysim/defconfig b/boards/arm/stm32f7/nucleo-f746zg/configs/pysim/defconfig index 291c438c26cd2..fe194da3bafe0 100644 --- a/boards/arm/stm32f7/nucleo-f746zg/configs/pysim/defconfig +++ b/boards/arm/stm32f7/nucleo-f746zg/configs/pysim/defconfig @@ -6,7 +6,7 @@ # modifications. # # CONFIG_NDEBUG is not set -# CONFIG_STM32F7_DTCMEXCLUDE is not set +# CONFIG_STM32_DTCMEXCLUDE is not set CONFIG_ADC=y CONFIG_ADC_FIFOSIZE=16 CONFIG_ANALOG=y @@ -16,6 +16,7 @@ CONFIG_ARCH_BOARD_COMMON=y CONFIG_ARCH_BOARD_NUCLEO_F746ZG=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32f7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F746ZG=y CONFIG_ARCH_CHIP_STM32F7=y CONFIG_ARCH_RAMVECTORS=y @@ -91,46 +92,46 @@ CONFIG_SPI=y CONFIG_START_DAY=30 CONFIG_START_MONTH=11 CONFIG_START_YEAR=2015 -CONFIG_STM32F7_ADC1=y -CONFIG_STM32F7_ADC1_DMA=y -CONFIG_STM32F7_ADC1_SAMPLE_FREQUENCY=5000 -CONFIG_STM32F7_ADC1_TIMTRIG=1 -CONFIG_STM32F7_CAN1=y -CONFIG_STM32F7_CAN1_BAUD=500000 -CONFIG_STM32F7_CAN_TSEG1=5 -CONFIG_STM32F7_CAN_TSEG2=6 -CONFIG_STM32F7_DMA1=y -CONFIG_STM32F7_DMA2=y -CONFIG_STM32F7_ETHMAC=y -CONFIG_STM32F7_PHYADDR=0 -CONFIG_STM32F7_PHYSR=31 -CONFIG_STM32F7_PHYSR_100FD=0x0018 -CONFIG_STM32F7_PHYSR_100HD=0x0008 -CONFIG_STM32F7_PHYSR_10FD=0x0014 -CONFIG_STM32F7_PHYSR_10HD=0x0004 -CONFIG_STM32F7_PHYSR_ALTCONFIG=y -CONFIG_STM32F7_PHYSR_ALTMODE=0x001c -CONFIG_STM32F7_PWM_MULTICHAN=y -CONFIG_STM32F7_SERIALBRK_BSDCOMPAT=y -CONFIG_STM32F7_SERIAL_DISABLE_REORDERING=y -CONFIG_STM32F7_TIM1=y -CONFIG_STM32F7_TIM1_CH1NOUT=y -CONFIG_STM32F7_TIM1_CH1OUT=y -CONFIG_STM32F7_TIM1_CH2NOUT=y -CONFIG_STM32F7_TIM1_CH2OUT=y -CONFIG_STM32F7_TIM1_CHANNEL1=y -CONFIG_STM32F7_TIM1_CHANNEL2=y -CONFIG_STM32F7_TIM1_DEADTIME=10 -CONFIG_STM32F7_TIM1_PWM=y -CONFIG_STM32F7_TIM2=y -CONFIG_STM32F7_TIM2_ADC=y -CONFIG_STM32F7_TIM3=y -CONFIG_STM32F7_TIM3_QE=y -CONFIG_STM32F7_TIM4=y -CONFIG_STM32F7_TIM4_QE=y -CONFIG_STM32F7_TIM8=y -CONFIG_STM32F7_TIM8_QE=y -CONFIG_STM32F7_USART_BREAKS=y +CONFIG_STM32_ADC1=y +CONFIG_STM32_ADC1_DMA=y +CONFIG_STM32_ADC1_SAMPLE_FREQUENCY=5000 +CONFIG_STM32_ADC1_TIMTRIG=1 +CONFIG_STM32_CAN1=y +CONFIG_STM32_CAN1_BAUD=500000 +CONFIG_STM32_CAN_TSEG1=5 +CONFIG_STM32_CAN_TSEG2=6 +CONFIG_STM32_DMA1=y +CONFIG_STM32_DMA2=y +CONFIG_STM32_ETHMAC=y +CONFIG_STM32_PHYADDR=0 +CONFIG_STM32_PHYSR=31 +CONFIG_STM32_PHYSR_100FD=0x0018 +CONFIG_STM32_PHYSR_100HD=0x0008 +CONFIG_STM32_PHYSR_10FD=0x0014 +CONFIG_STM32_PHYSR_10HD=0x0004 +CONFIG_STM32_PHYSR_ALTCONFIG=y +CONFIG_STM32_PHYSR_ALTMODE=0x001c +CONFIG_STM32_PWM_MULTICHAN=y +CONFIG_STM32_SERIALBRK_BSDCOMPAT=y +CONFIG_STM32_SERIAL_DISABLE_REORDERING=y +CONFIG_STM32_TIM1=y +CONFIG_STM32_TIM1_CH1NOUT=y +CONFIG_STM32_TIM1_CH1OUT=y +CONFIG_STM32_TIM1_CH2NOUT=y +CONFIG_STM32_TIM1_CH2OUT=y +CONFIG_STM32_TIM1_CHANNEL1=y +CONFIG_STM32_TIM1_CHANNEL2=y +CONFIG_STM32_TIM1_DEADTIME=10 +CONFIG_STM32_TIM1_PWM=y +CONFIG_STM32_TIM2=y +CONFIG_STM32_TIM2_ADC=y +CONFIG_STM32_TIM3=y +CONFIG_STM32_TIM3_QE=y +CONFIG_STM32_TIM4=y +CONFIG_STM32_TIM4_QE=y +CONFIG_STM32_TIM8=y +CONFIG_STM32_TIM8_QE=y +CONFIG_STM32_USART_BREAKS=y CONFIG_SYSTEM_DHCPC_RENEW=y CONFIG_SYSTEM_NSH=y CONFIG_SYSTEM_PING=y diff --git a/boards/arm/stm32f7/nucleo-f746zg/include/board.h b/boards/arm/stm32f7/nucleo-f746zg/include/board.h index e2e37b73c08ed..95d61afca086b 100644 --- a/boards/arm/stm32f7/nucleo-f746zg/include/board.h +++ b/boards/arm/stm32f7/nucleo-f746zg/include/board.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32F7_NUCLEO_F746ZG_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32F7_NUCLEO_F746ZG_INCLUDE_BOARD_H +#ifndef __BOARDS_ARM_STM32_NUCLEO_F746ZG_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32_NUCLEO_F746ZG_INCLUDE_BOARD_H /**************************************************************************** * Included Files @@ -106,7 +106,7 @@ /* Configure factors for PLLSAI clock */ -#define CONFIG_STM32F7_PLLSAI 1 +#define CONFIG_STM32_PLLSAI 1 #define STM32_RCC_PLLSAICFGR_PLLSAIN RCC_PLLSAICFGR_PLLSAIN(192) #define STM32_RCC_PLLSAICFGR_PLLSAIP RCC_PLLSAICFGR_PLLSAIP(8) #define STM32_RCC_PLLSAICFGR_PLLSAIQ RCC_PLLSAICFGR_PLLSAIQ(4) @@ -125,7 +125,7 @@ /* Configure factors for PLLI2S clock */ -#define CONFIG_STM32F7_PLLI2S 1 +#define CONFIG_STM32_PLLI2S 1 #define STM32_RCC_PLLI2SCFGR_PLLI2SN RCC_PLLI2SCFGR_PLLI2SN(192) #define STM32_RCC_PLLI2SCFGR_PLLI2SP RCC_PLLI2SCFGR_PLLI2SP(2) #define STM32_RCC_PLLI2SCFGR_PLLI2SQ RCC_PLLI2SCFGR_PLLI2SQ(2) @@ -567,4 +567,4 @@ #define GPIO_OTGFS_DP (GPIO_OTGFS_DP_0|GPIO_SPEED_100MHz) #define GPIO_OTGFS_ID (GPIO_OTGFS_ID_0|GPIO_SPEED_100MHz) -#endif /* __BOARDS_ARM_STM32F7_NUCLEO_F746ZG_INCLUDE_BOARD_H */ +#endif /* __BOARDS_ARM_STM32_NUCLEO_F746ZG_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32f7/nucleo-f746zg/src/CMakeLists.txt b/boards/arm/stm32f7/nucleo-f746zg/src/CMakeLists.txt index 73a308ecf1c88..1c42f13728819 100644 --- a/boards/arm/stm32f7/nucleo-f746zg/src/CMakeLists.txt +++ b/boards/arm/stm32f7/nucleo-f746zg/src/CMakeLists.txt @@ -52,11 +52,11 @@ if(CONFIG_MMCSD) list(APPEND SRCS stm32_sdio.c) endif() -if(CONFIG_STM32F7_OTGFS) +if(CONFIG_STM32_OTGFS) list(APPEND SRCS stm32_usb.c) endif() -if(CONFIG_STM32F7_BBSRAM) +if(CONFIG_STM32_BBSRAM) list(APPEND SRCS stm32_bbsram.c) endif() diff --git a/boards/arm/stm32f7/nucleo-f746zg/src/Make.defs b/boards/arm/stm32f7/nucleo-f746zg/src/Make.defs index 92eaf789e5872..78a75d54df0c4 100644 --- a/boards/arm/stm32f7/nucleo-f746zg/src/Make.defs +++ b/boards/arm/stm32f7/nucleo-f746zg/src/Make.defs @@ -54,11 +54,11 @@ ifeq ($(CONFIG_MMCSD),y) CSRCS += stm32_sdio.c endif -ifeq ($(CONFIG_STM32F7_OTGFS),y) +ifeq ($(CONFIG_STM32_OTGFS),y) CSRCS += stm32_usb.c endif -ifeq ($(CONFIG_STM32F7_BBSRAM),y) +ifeq ($(CONFIG_STM32_BBSRAM),y) CSRCS += stm32_bbsram.c endif diff --git a/boards/arm/stm32f7/nucleo-f746zg/src/nucleo-f746zg.h b/boards/arm/stm32f7/nucleo-f746zg/src/nucleo-f746zg.h index a71f98a2c345a..febcb0582abe8 100644 --- a/boards/arm/stm32f7/nucleo-f746zg/src/nucleo-f746zg.h +++ b/boards/arm/stm32f7/nucleo-f746zg/src/nucleo-f746zg.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32F7_NUCLEO_F746ZG_SRC_NUCLEO_F746ZG_H -#define __BOARDS_ARM_STM32F7_NUCLEO_F746ZG_SRC_NUCLEO_F746ZG_H +#ifndef __BOARDS_ARM_STM32_NUCLEO_F746ZG_SRC_NUCLEO_F746ZG_H +#define __BOARDS_ARM_STM32_NUCLEO_F746ZG_SRC_NUCLEO_F746ZG_H /**************************************************************************** * Included Files @@ -100,7 +100,7 @@ #define GPIO_SPI3_CS2 (GPIO_SPI_CS | GPIO_PORTG | GPIO_PIN6) #define GPIO_SPI3_CS3 (GPIO_SPI_CS | GPIO_PORTG | GPIO_PIN7) -#if defined(CONFIG_STM32F7_SDMMC1) || defined(CONFIG_STM32F7_SDMMC2) +#if defined(CONFIG_STM32_SDMMC1) || defined(CONFIG_STM32_SDMMC2) # define HAVE_SDIO #endif @@ -111,7 +111,7 @@ #define SDIO_SLOTNO 0 /* Only one slot */ #ifdef HAVE_SDIO -# if defined(CONFIG_STM32F7_SDMMC1) +# if defined(CONFIG_STM32_SDMMC1) # define GPIO_SDMMC1_NCD (GPIO_INPUT|GPIO_FLOAT|GPIO_EXTI | GPIO_PORTC | GPIO_PIN6) # endif @@ -153,9 +153,9 @@ /* GPIO pins used by the GPIO Subsystem */ #define BOARD_NGPIOIN 4 /* Amount of GPIO Input pins */ -#if defined(CONFIG_STM32F7_TIM1_CH1NOUT) && defined (CONFIG_STM32F7_TIM1_CH2NOUT) +#if defined(CONFIG_STM32_TIM1_CH1NOUT) && defined (CONFIG_STM32_TIM1_CH2NOUT) #define BOARD_NGPIOOUT 8 /* Amount of GPIO Output pins */ -#elif defined(CONFIG_STM32F7_TIM1_CH1NOUT) || defined (CONFIG_STM32F7_TIM1_CH2NOUT) +#elif defined(CONFIG_STM32_TIM1_CH1NOUT) || defined (CONFIG_STM32_TIM1_CH2NOUT) #define BOARD_NGPIOOUT 9 /* Amount of GPIO Output pins */ #else #define BOARD_NGPIOOUT 10 /* Amount of GPIO Output pins */ @@ -179,11 +179,11 @@ GPIO_OUTPUT_SET | GPIO_PORTA |GPIO_PIN5) #define GPIO_OUT5 (GPIO_OUTPUT | GPIO_SPEED_50MHz | \ GPIO_OUTPUT_SET | GPIO_PORTF | GPIO_PIN12) -#if !defined(CONFIG_STM32F7_TIM1_CH1NOUT) +#if !defined(CONFIG_STM32_TIM1_CH1NOUT) #define GPIO_OUT6 (GPIO_OUTPUT | GPIO_SPEED_50MHz | \ GPIO_OUTPUT_SET | GPIO_PORTE | GPIO_PIN8) #endif -#if !defined(CONFIG_STM32F7_TIM1_CH2NOUT) +#if !defined(CONFIG_STM32_TIM1_CH2NOUT) #define GPIO_OUT7 (GPIO_OUTPUT | GPIO_SPEED_50MHz | \ GPIO_OUTPUT_SET | GPIO_PORTE | GPIO_PIN10) #endif @@ -276,7 +276,7 @@ int stm32_sdio_initialize(void); * ****************************************************************************/ -#ifdef CONFIG_STM32F7_OTGFS +#ifdef CONFIG_STM32_OTGFS void stm32_usbinitialize(void); #endif @@ -308,7 +308,7 @@ int stm32_adc_setup(void); * Name: stm32_bbsram_int ****************************************************************************/ -#ifdef CONFIG_STM32F7_BBSRAM +#ifdef CONFIG_STM32_BBSRAM int stm32_bbsram_int(void); #endif @@ -329,4 +329,4 @@ int stm32_gpio_initialize(void); #endif #endif /* __ASSEMBLY__ */ -#endif /* __BOARDS_ARM_STM32F7_NUCLEO_F746ZG_SRC_NUCLEO_F746ZG_H */ +#endif /* __BOARDS_ARM_STM32_NUCLEO_F746ZG_SRC_NUCLEO_F746ZG_H */ diff --git a/boards/arm/stm32f7/nucleo-f746zg/src/stm32_adc.c b/boards/arm/stm32f7/nucleo-f746zg/src/stm32_adc.c index 76e270d40d32d..c1f68f2008364 100644 --- a/boards/arm/stm32f7/nucleo-f746zg/src/stm32_adc.c +++ b/boards/arm/stm32f7/nucleo-f746zg/src/stm32_adc.c @@ -48,20 +48,20 @@ /* Up to 3 ADC interfaces are supported */ -#if STM32F7_NADC < 3 -# undef CONFIG_STM32F7_ADC3 +#if STM32_NADC < 3 +# undef CONFIG_STM32_ADC3 #endif -#if STM32F7_NADC < 2 -# undef CONFIG_STM32F7_ADC2 +#if STM32_NADC < 2 +# undef CONFIG_STM32_ADC2 #endif -#if STM32F7_NADC < 1 -# undef CONFIG_STM32F7_ADC1 +#if STM32_NADC < 1 +# undef CONFIG_STM32_ADC1 #endif -#if defined(CONFIG_STM32F7_ADC1) || defined(CONFIG_STM32F7_ADC2) || defined(CONFIG_STM32F7_ADC3) -#ifndef CONFIG_STM32F7_ADC1 +#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) || defined(CONFIG_STM32_ADC3) +#ifndef CONFIG_STM32_ADC1 # warning "Channel information only available for ADC1" #endif @@ -79,7 +79,7 @@ * {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 15}; */ -#ifdef CONFIG_STM32F7_ADC1 +#ifdef CONFIG_STM32_ADC1 static const uint8_t g_chanlist[ADC1_NCHANNELS] = { 3, 4, 10, 13 @@ -118,7 +118,7 @@ static const uint32_t g_pinlist[ADC1_NCHANNELS] = int stm32_adc_setup(void) { -#ifdef CONFIG_STM32F7_ADC1 +#ifdef CONFIG_STM32_ADC1 static bool initialized = false; struct adc_dev_s *adc; int ret; @@ -167,5 +167,5 @@ int stm32_adc_setup(void) #endif } -#endif /* CONFIG_STM32F7_ADC1 || CONFIG_STM32F7_ADC2 || CONFIG_STM32F7_ADC3 */ +#endif /* CONFIG_STM32_ADC1 || CONFIG_STM32_ADC2 || CONFIG_STM32_ADC3 */ #endif /* CONFIG_ADC */ diff --git a/boards/arm/stm32f7/nucleo-f746zg/src/stm32_bbsram.c b/boards/arm/stm32f7/nucleo-f746zg/src/stm32_bbsram.c index f6d8279ebb12f..1595f88879be2 100644 --- a/boards/arm/stm32f7/nucleo-f746zg/src/stm32_bbsram.c +++ b/boards/arm/stm32f7/nucleo-f746zg/src/stm32_bbsram.c @@ -47,7 +47,7 @@ #include "nucleo-f746zg.h" -#ifdef CONFIG_STM32F7_BBSRAM +#ifdef CONFIG_STM32_BBSRAM /**************************************************************************** * Pre-processor Definitions @@ -76,7 +76,7 @@ #define BBSRAM_USED ((4*BBSRAM_HEADER_SIZE)+ \ (BBSRAM_SIZE_FN0+BBSRAM_SIZE_FN1+ \ BBSRAM_SIZE_FN2)) -#define BBSRAM_REAMINING (STM32F7_BBSRAM_SIZE-BBSRAM_USED) +#define BBSRAM_REAMINING (STM32_BBSRAM_SIZE-BBSRAM_USED) #if CONFIG_ARCH_INTERRUPTSTACK <= 3 # define BBSRAM_NUMBER_STACKS 1 #else @@ -265,7 +265,7 @@ typedef struct * Private Data ****************************************************************************/ -static uint8_t g_sdata[STM32F7_BBSRAM_SIZE]; +static uint8_t g_sdata[STM32_BBSRAM_SIZE]; /**************************************************************************** * Private Functions @@ -288,7 +288,7 @@ static int hardfault_get_desc(struct bbsramd_s *desc) } else { - ret = file_ioctl(&filestruct, STM32F7_BBSRAM_GETDESC_IOCTL, + ret = file_ioctl(&filestruct, STM32_BBSRAM_GETDESC_IOCTL, (unsigned long)((uintptr_t)desc)); file_close(&filestruct); @@ -306,7 +306,7 @@ static int hardfault_get_desc(struct bbsramd_s *desc) * Name: copy_reverse ****************************************************************************/ -#if defined(CONFIG_STM32F7_SAVE_CRASHDUMP) +#if defined(CONFIG_STM32_SAVE_CRASHDUMP) static void copy_reverse(stack_word_t *dest, stack_word_t *src, int size) { while (size--) @@ -314,7 +314,7 @@ static void copy_reverse(stack_word_t *dest, stack_word_t *src, int size) *dest++ = *src--; } } -#endif /* CONFIG_STM32F7_SAVE_CRASHDUMP */ +#endif /* CONFIG_STM32_SAVE_CRASHDUMP */ /**************************************************************************** * Public Functions @@ -326,7 +326,7 @@ static void copy_reverse(stack_word_t *dest, stack_word_t *src, int size) int stm32_bbsram_int(void) { - int filesizes[CONFIG_STM32F7_BBSRAM_FILES + 1] = BSRAM_FILE_SIZES; + int filesizes[CONFIG_STM32_BBSRAM_FILES + 1] = BSRAM_FILE_SIZES; char buf[HEADER_TIME_FMT_LEN + 1]; struct bbsramd_s desc; int rv; @@ -338,7 +338,7 @@ int stm32_bbsram_int(void) stm32_bbsraminitialize(BBSRAM_PATH, filesizes); -#if defined(CONFIG_STM32F7_SAVE_CRASHDUMP) +#if defined(CONFIG_STM32_SAVE_CRASHDUMP) /* Panic Logging in Battery Backed Up Files */ /* Do we have an hard fault in BBSRAM? */ @@ -369,7 +369,7 @@ int stm32_bbsram_int(void) " [%s] (%d)\n", HARDFAULT_PATH, rv); } } -#endif /* CONFIG_STM32F7_SAVE_CRASHDUMP */ +#endif /* CONFIG_STM32_SAVE_CRASHDUMP */ return rv; } @@ -378,7 +378,7 @@ int stm32_bbsram_int(void) * Name: board_crashdump ****************************************************************************/ -#if defined(CONFIG_STM32F7_SAVE_CRASHDUMP) +#if defined(CONFIG_STM32_SAVE_CRASHDUMP) void board_crashdump(uintptr_t sp, struct tcb_s *tcb, const char *filename, int lineno, const char *msg, void *regs) @@ -514,6 +514,6 @@ void board_crashdump(uintptr_t sp, struct tcb_s *tcb, arm_lowputc('!'); } } -#endif /* CONFIG_STM32F7_SAVE_CRASHDUMP */ +#endif /* CONFIG_STM32_SAVE_CRASHDUMP */ #endif /* CONFIG_STM32_BBSRAM */ diff --git a/boards/arm/stm32f7/nucleo-f746zg/src/stm32_boot.c b/boards/arm/stm32f7/nucleo-f746zg/src/stm32_boot.c index adab9af41bb27..b30ff20886d3a 100644 --- a/boards/arm/stm32f7/nucleo-f746zg/src/stm32_boot.c +++ b/boards/arm/stm32f7/nucleo-f746zg/src/stm32_boot.c @@ -57,7 +57,7 @@ void stm32_boardinitialize(void) board_autoled_initialize(); #endif -#if defined(CONFIG_STM32F7_OTGFS) || defined(CONFIG_STM32F7_HOST) +#if defined(CONFIG_STM32_OTGFS) || defined(CONFIG_STM32_HOST) stm32_usbinitialize(); #endif diff --git a/boards/arm/stm32f7/nucleo-f746zg/src/stm32_bringup.c b/boards/arm/stm32f7/nucleo-f746zg/src/stm32_bringup.c index 39d379e5c8dd3..f7cc0a58d8154 100644 --- a/boards/arm/stm32f7/nucleo-f746zg/src/stm32_bringup.c +++ b/boards/arm/stm32f7/nucleo-f746zg/src/stm32_bringup.c @@ -40,19 +40,19 @@ #include "stm32_i2c.h" -#ifdef CONFIG_STM32F7_CAN_CHARDRIVER +#ifdef CONFIG_STM32_CAN_CHARDRIVER # include "stm32_can_setup.h" #endif -#ifdef CONFIG_STM32F7_CAN_SOCKET +#ifdef CONFIG_STM32_CAN_SOCKET # include "stm32_cansock_setup.h" #endif -#ifdef CONFIG_STM32F7_ROMFS +#ifdef CONFIG_STM32_ROMFS # include "stm32_romfs.h" #endif -#ifdef CONFIG_STM32F7_SPI_TEST +#ifdef CONFIG_STM32_SPI_TEST # include "stm32_spitest.h" #endif @@ -97,14 +97,14 @@ int stm32_bringup(void) } #endif -#ifdef CONFIG_STM32F7_ROMFS +#ifdef CONFIG_STM32_ROMFS /* Mount the romfs partition */ ret = stm32_romfs_initialize(); if (ret < 0) { syslog(LOG_ERR, "ERROR: Failed to mount romfs at %s: %d\n", - CONFIG_STM32F7_ROMFS_MOUNTPOINT, ret); + CONFIG_STM32_ROMFS_MOUNTPOINT, ret); } #endif @@ -139,7 +139,7 @@ int stm32_bringup(void) } #endif -#ifdef CONFIG_STM32F7_BBSRAM +#ifdef CONFIG_STM32_BBSRAM /* Initialize battery-backed RAM */ stm32_bbsram_int(); @@ -152,7 +152,7 @@ int stm32_bringup(void) } #endif -#ifdef CONFIG_STM32F7_SPI_TEST +#ifdef CONFIG_STM32_SPI_TEST /* Create SPI interfaces */ ret = stm32_spidev_bus_test(); @@ -188,7 +188,7 @@ int stm32_bringup(void) #ifdef CONFIG_SENSORS_QENCODER char buf[9]; -#ifdef CONFIG_STM32F7_TIM1_QE +#ifdef CONFIG_STM32_TIM1_QE snprintf(buf, sizeof(buf), "/dev/qe0"); ret = stm32_qencoder_initialize(buf, 1); if (ret < 0) @@ -200,7 +200,7 @@ int stm32_bringup(void) } #endif -#ifdef CONFIG_STM32F7_TIM3_QE +#ifdef CONFIG_STM32_TIM3_QE snprintf(buf, sizeof(buf), "/dev/qe2"); ret = stm32_qencoder_initialize(buf, 3); if (ret < 0) @@ -212,7 +212,7 @@ int stm32_bringup(void) } #endif -#ifdef CONFIG_STM32F7_TIM4_QE +#ifdef CONFIG_STM32_TIM4_QE snprintf(buf, sizeof(buf), "/dev/qe3"); ret = stm32_qencoder_initialize(buf, 4); if (ret < 0) @@ -224,7 +224,7 @@ int stm32_bringup(void) } #endif -#ifdef CONFIG_STM32F7_TIM8_QE +#ifdef CONFIG_STM32_TIM8_QE snprintf(buf, sizeof(buf), "/dev/qe4"); ret = stm32_qencoder_initialize(buf, 8); if (ret < 0) @@ -238,7 +238,7 @@ int stm32_bringup(void) #endif -#ifdef CONFIG_STM32F7_CAN_CHARDRIVER +#ifdef CONFIG_STM32_CAN_CHARDRIVER ret = stm32_can_setup(); if (ret < 0) { @@ -247,7 +247,7 @@ int stm32_bringup(void) } #endif -#ifdef CONFIG_STM32F7_CAN_SOCKET +#ifdef CONFIG_STM32_CAN_SOCKET ret = stm32_cansock_setup(); if (ret < 0) { @@ -255,7 +255,7 @@ int stm32_bringup(void) } #endif -#if defined(CONFIG_I2C) && defined(CONFIG_STM32F7_I2C1) +#if defined(CONFIG_I2C) && defined(CONFIG_STM32_I2C1) i2c_bus = 1; i2c = stm32_i2cbus_initialize(i2c_bus); if (i2c == NULL) diff --git a/boards/arm/stm32f7/nucleo-f746zg/src/stm32_gpio.c b/boards/arm/stm32f7/nucleo-f746zg/src/stm32_gpio.c index bb3c0cfae36b3..983a1bddb5648 100644 --- a/boards/arm/stm32f7/nucleo-f746zg/src/stm32_gpio.c +++ b/boards/arm/stm32f7/nucleo-f746zg/src/stm32_gpio.c @@ -125,10 +125,10 @@ static const uint32_t g_gpiooutputs[BOARD_NGPIOOUT] = GPIO_OUT3, GPIO_OUT4, GPIO_OUT5, -#if !defined(CONFIG_STM32F7_TIM1_CH1NOUT) +#if !defined(CONFIG_STM32_TIM1_CH1NOUT) GPIO_OUT6, #endif -#if !defined(CONFIG_STM32F7_TIM1_CH2NOUT) +#if !defined(CONFIG_STM32_TIM1_CH2NOUT) GPIO_OUT7, #endif }; diff --git a/boards/arm/stm32f7/nucleo-f746zg/src/stm32_pwm.c b/boards/arm/stm32f7/nucleo-f746zg/src/stm32_pwm.c index a2de94884cc73..8100783be1934 100644 --- a/boards/arm/stm32f7/nucleo-f746zg/src/stm32_pwm.c +++ b/boards/arm/stm32f7/nucleo-f746zg/src/stm32_pwm.c @@ -73,7 +73,7 @@ int stm32_pwm_setup(void) { /* Call stm32_pwminitialize() to get an instance of the PWM interface */ -#if defined(CONFIG_STM32F7_TIM1_PWM) +#if defined(CONFIG_STM32_TIM1_PWM) pwm = stm32_pwminitialize(1); if (!pwm) { @@ -89,7 +89,7 @@ int stm32_pwm_setup(void) } #endif -#if defined(CONFIG_STM32F7_TIM2_PWM) +#if defined(CONFIG_STM32_TIM2_PWM) pwm = stm32_pwminitialize(2); if (!pwm) { @@ -105,7 +105,7 @@ int stm32_pwm_setup(void) } #endif -#if defined(CONFIG_STM32F7_TIM3_PWM) +#if defined(CONFIG_STM32_TIM3_PWM) pwm = stm32_pwminitialize(3); if (!pwm) { @@ -121,7 +121,7 @@ int stm32_pwm_setup(void) } #endif -#if defined(CONFIG_STM32F7_TIM4_PWM) +#if defined(CONFIG_STM32_TIM4_PWM) pwm = stm32_pwminitialize(4); if (!pwm) { diff --git a/boards/arm/stm32f7/nucleo-f746zg/src/stm32_spi.c b/boards/arm/stm32f7/nucleo-f746zg/src/stm32_spi.c index ee391eb04ad6e..417e00c2ae1d3 100644 --- a/boards/arm/stm32f7/nucleo-f746zg/src/stm32_spi.c +++ b/boards/arm/stm32f7/nucleo-f746zg/src/stm32_spi.c @@ -53,7 +53,7 @@ * Private Data ****************************************************************************/ -#if defined(CONFIG_STM32F7_SPI1) +#if defined(CONFIG_STM32_SPI1) static const uint32_t g_spi1gpio[] = { # if defined(GPIO_SPI1_CS0) @@ -79,7 +79,7 @@ static const uint32_t g_spi1gpio[] = }; #endif -#if defined(CONFIG_STM32F7_SPI2) +#if defined(CONFIG_STM32_SPI2) static const uint32_t g_spi2gpio[] = { # if defined(GPIO_SPI2_CS0) @@ -105,7 +105,7 @@ static const uint32_t g_spi2gpio[] = }; #endif -#if defined(CONFIG_STM32F7_SPI3) +#if defined(CONFIG_STM32_SPI3) static const uint32_t g_spi3gpio[] = { # if defined(GPIO_SPI3_CS0) @@ -148,7 +148,7 @@ void weak_function stm32_spidev_initialize(void) { /* Configure SPI CS GPIO for output */ -#if defined(CONFIG_STM32F7_SPI1) +#if defined(CONFIG_STM32_SPI1) for (int i = 0; i < nitems(g_spi1gpio); i++) { if (g_spi1gpio[i] != 0) @@ -158,7 +158,7 @@ void weak_function stm32_spidev_initialize(void) } #endif -#if defined(CONFIG_STM32F7_SPI2) +#if defined(CONFIG_STM32_SPI2) for (int i = 0; i < nitems(g_spi2gpio); i++) { if (g_spi2gpio[i] != 0) @@ -168,7 +168,7 @@ void weak_function stm32_spidev_initialize(void) } #endif -#if defined(CONFIG_STM32F7_SPI3) +#if defined(CONFIG_STM32_SPI3) for (int i = 0; i < nitems(g_spi3gpio); i++) { if (g_spi3gpio[i] != 0) @@ -206,7 +206,7 @@ void weak_function stm32_spidev_initialize(void) * ****************************************************************************/ -#ifdef CONFIG_STM32F7_SPI1 +#ifdef CONFIG_STM32_SPI1 void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -227,7 +227,7 @@ uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32F7_SPI2 +#ifdef CONFIG_STM32_SPI2 void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -248,7 +248,7 @@ uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32F7_SPI3 +#ifdef CONFIG_STM32_SPI3 void stm32_spi3select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -269,7 +269,7 @@ uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32F7_SPI4 +#ifdef CONFIG_STM32_SPI4 void stm32_spi4select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -283,7 +283,7 @@ uint8_t stm32_spi4status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32F7_SPI5 +#ifdef CONFIG_STM32_SPI5 void stm32_spi5select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -297,7 +297,7 @@ uint8_t stm32_spi5status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32F7_SPI6 +#ifdef CONFIG_STM32_SPI6 void stm32_spi6select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -335,42 +335,42 @@ uint8_t stm32_spi6status(struct spi_dev_s *dev, uint32_t devid) ****************************************************************************/ #ifdef CONFIG_SPI_CMDDATA -#ifdef CONFIG_STM32F7_SPI1 +#ifdef CONFIG_STM32_SPI1 int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32F7_SPI2 +#ifdef CONFIG_STM32_SPI2 int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32F7_SPI3 +#ifdef CONFIG_STM32_SPI3 int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32F7_SPI4 +#ifdef CONFIG_STM32_SPI4 int stm32_spi4cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32F7_SPI5 +#ifdef CONFIG_STM32_SPI5 int stm32_spi5cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32F7_SPI6 +#ifdef CONFIG_STM32_SPI6 int stm32_spi6cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; diff --git a/boards/arm/stm32f7/nucleo-f746zg/src/stm32_usb.c b/boards/arm/stm32f7/nucleo-f746zg/src/stm32_usb.c index 1e3c23c0ad729..fe457155c2a08 100644 --- a/boards/arm/stm32f7/nucleo-f746zg/src/stm32_usb.c +++ b/boards/arm/stm32f7/nucleo-f746zg/src/stm32_usb.c @@ -45,7 +45,7 @@ #include "stm32_otg.h" #include "nucleo-f746zg.h" -#ifdef CONFIG_STM32F7_OTGFS +#ifdef CONFIG_STM32_OTGFS /**************************************************************************** * Pre-processor Definitions @@ -138,7 +138,7 @@ void stm32_usbinitialize(void) * Power On, and Overcurrent GPIOs */ -#ifdef CONFIG_STM32F7_OTGFS +#ifdef CONFIG_STM32_OTGFS stm32_configgpio(GPIO_OTGFS_VBUS); stm32_configgpio(GPIO_OTGFS_PWRON); stm32_configgpio(GPIO_OTGFS_OVER); diff --git a/boards/arm/stm32f7/nucleo-f767zi/Kconfig b/boards/arm/stm32f7/nucleo-f767zi/Kconfig index e8eb80d5fab6a..e01d882951fa5 100644 --- a/boards/arm/stm32f7/nucleo-f767zi/Kconfig +++ b/boards/arm/stm32f7/nucleo-f767zi/Kconfig @@ -57,22 +57,22 @@ choice config NUCLEO_F767ZI_CONSOLE_ARDUINO bool "Arduino Connector" - select STM32F7_USART6 + select STM32_USART6 select USART6_SERIALDRIVER config NUCLEO_F767ZI_CONSOLE_VIRTUAL bool "Virtual Comport" - select STM32F7_USART3 + select STM32_USART3 select USART3_SERIALDRIVER config NUCLEO_F767ZI_CONSOLE_MORPHO bool "Morpho Connector" - select STM32F7_UART8 + select STM32_UART8 select UART8_SERIALDRIVER config NUCLEO_F767ZI_CONSOLE_MORPHO_UART4 bool "Morpho Connector UART4" - select STM32F7_UART4 + select STM32_UART4 select UART4_SERIALDRIVER config NUCLEO_F767ZI_CONSOLE_NONE @@ -83,7 +83,7 @@ endchoice # "Select Console wiring" choice prompt "CAN1 pins selection" default NUCLEO_F767ZI_CAN1_MAP_PD0PD1 - depends on STM32F7_CAN1 + depends on STM32_CAN1 config NUCLEO_F767ZI_CAN1_MAP_D14D15 bool "CAN1_TX=D14 CAN1_RX=D15" diff --git a/boards/arm/stm32f7/nucleo-f767zi/configs/evalos/defconfig b/boards/arm/stm32f7/nucleo-f767zi/configs/evalos/defconfig index 3baad155b05b7..93030ce725802 100644 --- a/boards/arm/stm32f7/nucleo-f767zi/configs/evalos/defconfig +++ b/boards/arm/stm32f7/nucleo-f767zi/configs/evalos/defconfig @@ -15,6 +15,7 @@ CONFIG_ARCH_BOARD="nucleo-f767zi" CONFIG_ARCH_BOARD_NUCLEO_F767ZI=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32f7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F767ZI=y CONFIG_ARCH_CHIP_STM32F7=y CONFIG_ARCH_STACKDUMP=y @@ -55,10 +56,10 @@ CONFIG_STACK_COLORATION=y CONFIG_START_DAY=30 CONFIG_START_MONTH=11 CONFIG_START_YEAR=2015 -CONFIG_STM32F7_I2C1=y -CONFIG_STM32F7_SERIALBRK_BSDCOMPAT=y -CONFIG_STM32F7_SERIAL_DISABLE_REORDERING=y -CONFIG_STM32F7_USART_BREAKS=y +CONFIG_STM32_I2C1=y +CONFIG_STM32_SERIALBRK_BSDCOMPAT=y +CONFIG_STM32_SERIAL_DISABLE_REORDERING=y +CONFIG_STM32_USART_BREAKS=y CONFIG_SYSTEM_I2CTOOL=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 diff --git a/boards/arm/stm32f7/nucleo-f767zi/configs/netnsh/defconfig b/boards/arm/stm32f7/nucleo-f767zi/configs/netnsh/defconfig index 6ddfdc068527d..240cfc4a2e93f 100644 --- a/boards/arm/stm32f7/nucleo-f767zi/configs/netnsh/defconfig +++ b/boards/arm/stm32f7/nucleo-f767zi/configs/netnsh/defconfig @@ -10,6 +10,7 @@ CONFIG_ARCH_BOARD="nucleo-f767zi" CONFIG_ARCH_BOARD_NUCLEO_F767ZI=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32f7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F767ZI=y CONFIG_ARCH_CHIP_STM32F7=y CONFIG_ARCH_STACKDUMP=y @@ -62,15 +63,15 @@ CONFIG_STACK_COLORATION=y CONFIG_START_DAY=30 CONFIG_START_MONTH=11 CONFIG_START_YEAR=2015 -CONFIG_STM32F7_ETHMAC=y -CONFIG_STM32F7_PHYADDR=0 -CONFIG_STM32F7_PHYSR=31 -CONFIG_STM32F7_PHYSR_100FD=0x0018 -CONFIG_STM32F7_PHYSR_100HD=0x0008 -CONFIG_STM32F7_PHYSR_10FD=0x0014 -CONFIG_STM32F7_PHYSR_10HD=0x0004 -CONFIG_STM32F7_PHYSR_ALTCONFIG=y -CONFIG_STM32F7_PHYSR_ALTMODE=0x001c +CONFIG_STM32_ETHMAC=y +CONFIG_STM32_PHYADDR=0 +CONFIG_STM32_PHYSR=31 +CONFIG_STM32_PHYSR_100FD=0x0018 +CONFIG_STM32_PHYSR_100HD=0x0008 +CONFIG_STM32_PHYSR_10FD=0x0014 +CONFIG_STM32_PHYSR_10HD=0x0004 +CONFIG_STM32_PHYSR_ALTCONFIG=y +CONFIG_STM32_PHYSR_ALTMODE=0x001c CONFIG_SYSTEM_DHCPC_RENEW=y CONFIG_SYSTEM_NSH=y CONFIG_SYSTEM_PING=y diff --git a/boards/arm/stm32f7/nucleo-f767zi/configs/nsh/defconfig b/boards/arm/stm32f7/nucleo-f767zi/configs/nsh/defconfig index bc43b47e6f84b..c78a21c59fa35 100644 --- a/boards/arm/stm32f7/nucleo-f767zi/configs/nsh/defconfig +++ b/boards/arm/stm32f7/nucleo-f767zi/configs/nsh/defconfig @@ -13,6 +13,7 @@ CONFIG_ARCH_BOARD="nucleo-f767zi" CONFIG_ARCH_BOARD_NUCLEO_F767ZI=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32f7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F767ZI=y CONFIG_ARCH_CHIP_STM32F7=y CONFIG_ARCH_STACKDUMP=y diff --git a/boards/arm/stm32f7/nucleo-f767zi/include/board.h b/boards/arm/stm32f7/nucleo-f767zi/include/board.h index 1dd891145582b..357e8d0129241 100644 --- a/boards/arm/stm32f7/nucleo-f767zi/include/board.h +++ b/boards/arm/stm32f7/nucleo-f767zi/include/board.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32F7_NUCLEO_F767ZI_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32F7_NUCLEO_F767ZI_INCLUDE_BOARD_H +#ifndef __BOARDS_ARM_STM32_NUCLEO_F767ZI_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32_NUCLEO_F767ZI_INCLUDE_BOARD_H /**************************************************************************** * Included Files @@ -106,7 +106,7 @@ /* Configure factors for PLLSAI clock */ -#define CONFIG_STM32F7_PLLSAI 1 +#define CONFIG_STM32_PLLSAI 1 #define STM32_RCC_PLLSAICFGR_PLLSAIN RCC_PLLSAICFGR_PLLSAIN(192) #define STM32_RCC_PLLSAICFGR_PLLSAIP RCC_PLLSAICFGR_PLLSAIP(8) #define STM32_RCC_PLLSAICFGR_PLLSAIQ RCC_PLLSAICFGR_PLLSAIQ(4) @@ -125,7 +125,7 @@ /* Configure factors for PLLI2S clock */ -#define CONFIG_STM32F7_PLLI2S 1 +#define CONFIG_STM32_PLLI2S 1 #define STM32_RCC_PLLI2SCFGR_PLLI2SN RCC_PLLI2SCFGR_PLLI2SN(192) #define STM32_RCC_PLLI2SCFGR_PLLI2SP RCC_PLLI2SCFGR_PLLI2SP(2) #define STM32_RCC_PLLI2SCFGR_PLLI2SQ RCC_PLLI2SCFGR_PLLI2SQ(2) @@ -598,4 +598,4 @@ #define GPIO_OTGFS_DP (GPIO_OTGFS_DP_0|GPIO_SPEED_100MHz) #define GPIO_OTGFS_ID (GPIO_OTGFS_ID_0|GPIO_SPEED_100MHz) -#endif /* __BOARDS_ARM_STM32F7_NUCLEO_F767ZI_INCLUDE_BOARD_H */ +#endif /* __BOARDS_ARM_STM32_NUCLEO_F767ZI_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32f7/nucleo-f767zi/src/CMakeLists.txt b/boards/arm/stm32f7/nucleo-f767zi/src/CMakeLists.txt index 28d7f560bef67..b9e35dee70508 100644 --- a/boards/arm/stm32f7/nucleo-f767zi/src/CMakeLists.txt +++ b/boards/arm/stm32f7/nucleo-f767zi/src/CMakeLists.txt @@ -52,11 +52,11 @@ if(CONFIG_MMCSD) list(APPEND SRCS stm32_sdio.c) endif() -if(CONFIG_STM32F7_OTGFS) +if(CONFIG_STM32_OTGFS) list(APPEND SRCS stm32_usb.c) endif() -if(CONFIG_STM32F7_BBSRAM) +if(CONFIG_STM32_BBSRAM) list(APPEND SRCS stm32_bbsram.c) endif() diff --git a/boards/arm/stm32f7/nucleo-f767zi/src/Make.defs b/boards/arm/stm32f7/nucleo-f767zi/src/Make.defs index b4c24d64fec26..77197f80a79e0 100644 --- a/boards/arm/stm32f7/nucleo-f767zi/src/Make.defs +++ b/boards/arm/stm32f7/nucleo-f767zi/src/Make.defs @@ -54,11 +54,11 @@ ifeq ($(CONFIG_MMCSD),y) CSRCS += stm32_sdio.c endif -ifeq ($(CONFIG_STM32F7_OTGFS),y) +ifeq ($(CONFIG_STM32_OTGFS),y) CSRCS += stm32_usb.c endif -ifeq ($(CONFIG_STM32F7_BBSRAM),y) +ifeq ($(CONFIG_STM32_BBSRAM),y) CSRCS += stm32_bbsram.c endif diff --git a/boards/arm/stm32f7/nucleo-f767zi/src/nucleo-f767zi.h b/boards/arm/stm32f7/nucleo-f767zi/src/nucleo-f767zi.h index 60c9ab458c9a0..84fafbbf8cffd 100644 --- a/boards/arm/stm32f7/nucleo-f767zi/src/nucleo-f767zi.h +++ b/boards/arm/stm32f7/nucleo-f767zi/src/nucleo-f767zi.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32F7_NUCLEO_767ZI_SRC_NUCLEO_767ZI_H -#define __BOARDS_ARM_STM32F7_NUCLEO_767ZI_SRC_NUCLEO_767ZI_H +#ifndef __BOARDS_ARM_STM32_NUCLEO_767ZI_SRC_NUCLEO_767ZI_H +#define __BOARDS_ARM_STM32_NUCLEO_767ZI_SRC_NUCLEO_767ZI_H /**************************************************************************** * Included Files @@ -126,7 +126,7 @@ #define GPIO_SPI3_CS2 (GPIO_SPI_CS | GPIO_PORTG | GPIO_PIN6) #define GPIO_SPI3_CS3 (GPIO_SPI_CS | GPIO_PORTG | GPIO_PIN7) -#if defined(CONFIG_STM32F7_SDMMC1) || defined(CONFIG_STM32F7_SDMMC2) +#if defined(CONFIG_STM32_SDMMC1) || defined(CONFIG_STM32_SDMMC2) # define HAVE_SDIO #endif @@ -137,7 +137,7 @@ #define SDIO_SLOTNO 0 /* Only one slot */ #ifdef HAVE_SDIO -# if defined(CONFIG_STM32F7_SDMMC1) +# if defined(CONFIG_STM32_SDMMC1) # define GPIO_SDMMC1_NCD (GPIO_INPUT|GPIO_FLOAT|GPIO_EXTI | GPIO_PORTC | GPIO_PIN6) # endif @@ -179,9 +179,9 @@ /* GPIO pins used by the GPIO Subsystem */ #define BOARD_NGPIOIN 4 /* Amount of GPIO Input pins */ -#if defined(CONFIG_STM32F7_TIM1_CH1NOUT) && defined (CONFIG_STM32F7_TIM1_CH2NOUT) +#if defined(CONFIG_STM32_TIM1_CH1NOUT) && defined (CONFIG_STM32_TIM1_CH2NOUT) #define BOARD_NGPIOOUT 8 /* Amount of GPIO Output pins */ -#elif defined(CONFIG_STM32F7_TIM1_CH1NOUT) || defined (CONFIG_STM32F7_TIM1_CH2NOUT) +#elif defined(CONFIG_STM32_TIM1_CH1NOUT) || defined (CONFIG_STM32_TIM1_CH2NOUT) #define BOARD_NGPIOOUT 9 /* Amount of GPIO Output pins */ #else #define BOARD_NGPIOOUT 10 /* Amount of GPIO Output pins */ @@ -205,11 +205,11 @@ GPIO_OUTPUT_SET | GPIO_PORTA |GPIO_PIN5) #define GPIO_OUT5 (GPIO_OUTPUT | GPIO_SPEED_50MHz | \ GPIO_OUTPUT_SET | GPIO_PORTF | GPIO_PIN12) -#if !defined(CONFIG_STM32F7_TIM1_CH1NOUT) +#if !defined(CONFIG_STM32_TIM1_CH1NOUT) #define GPIO_OUT6 (GPIO_OUTPUT | GPIO_SPEED_50MHz | \ GPIO_OUTPUT_SET | GPIO_PORTE | GPIO_PIN8) #endif -#if !defined(CONFIG_STM32F7_TIM1_CH2NOUT) +#if !defined(CONFIG_STM32_TIM1_CH2NOUT) #define GPIO_OUT7 (GPIO_OUTPUT | GPIO_SPEED_50MHz | \ GPIO_OUTPUT_SET | GPIO_PORTE | GPIO_PIN10) #endif @@ -301,7 +301,7 @@ int stm32_sdio_initialize(void); * ****************************************************************************/ -#ifdef CONFIG_STM32F7_OTGFS +#ifdef CONFIG_STM32_OTGFS void stm32_usbinitialize(void); #endif @@ -333,7 +333,7 @@ int stm32_adc_setup(void); * Name: stm32_bbsram_int ****************************************************************************/ -#ifdef CONFIG_STM32F7_BBSRAM +#ifdef CONFIG_STM32_BBSRAM int stm32_bbsram_int(void); #endif @@ -354,4 +354,4 @@ int stm32_gpio_initialize(void); #endif #endif /* __ASSEMBLY__ */ -#endif /* __BOARDS_ARM_STM32F7_NUCLEO_767ZI_SRC_NUCLEO_767ZI_H */ +#endif /* __BOARDS_ARM_STM32_NUCLEO_767ZI_SRC_NUCLEO_767ZI_H */ diff --git a/boards/arm/stm32f7/nucleo-f767zi/src/stm32_adc.c b/boards/arm/stm32f7/nucleo-f767zi/src/stm32_adc.c index d8c2ca1239b66..7c871a67cd279 100644 --- a/boards/arm/stm32f7/nucleo-f767zi/src/stm32_adc.c +++ b/boards/arm/stm32f7/nucleo-f767zi/src/stm32_adc.c @@ -48,20 +48,20 @@ /* Up to 3 ADC interfaces are supported */ -#if STM32F7_NADC < 3 -# undef CONFIG_STM32F7_ADC3 +#if STM32_NADC < 3 +# undef CONFIG_STM32_ADC3 #endif -#if STM32F7_NADC < 2 -# undef CONFIG_STM32F7_ADC2 +#if STM32_NADC < 2 +# undef CONFIG_STM32_ADC2 #endif -#if STM32F7_NADC < 1 -# undef CONFIG_STM32F7_ADC1 +#if STM32_NADC < 1 +# undef CONFIG_STM32_ADC1 #endif -#if defined(CONFIG_STM32F7_ADC1) || defined(CONFIG_STM32F7_ADC2) || defined(CONFIG_STM32F7_ADC3) -#ifndef CONFIG_STM32F7_ADC1 +#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) || defined(CONFIG_STM32_ADC3) +#ifndef CONFIG_STM32_ADC1 # warning "Channel information only available for ADC1" #endif @@ -79,7 +79,7 @@ * {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 15}; */ -#ifdef CONFIG_STM32F7_ADC1 +#ifdef CONFIG_STM32_ADC1 static const uint8_t g_chanlist[ADC1_NCHANNELS] = { 3, 4, 10, 13 @@ -118,7 +118,7 @@ static const uint32_t g_pinlist[ADC1_NCHANNELS] = int stm32_adc_setup(void) { -#ifdef CONFIG_STM32F7_ADC1 +#ifdef CONFIG_STM32_ADC1 static bool initialized = false; struct adc_dev_s *adc; int ret; @@ -167,5 +167,5 @@ int stm32_adc_setup(void) #endif } -#endif /* CONFIG_STM32F7_ADC1 || CONFIG_STM32F7_ADC2 || CONFIG_STM32F7_ADC3 */ +#endif /* CONFIG_STM32_ADC1 || CONFIG_STM32_ADC2 || CONFIG_STM32_ADC3 */ #endif /* CONFIG_ADC */ diff --git a/boards/arm/stm32f7/nucleo-f767zi/src/stm32_bbsram.c b/boards/arm/stm32f7/nucleo-f767zi/src/stm32_bbsram.c index 73db1b71a2d15..39d97d4d6ccd4 100644 --- a/boards/arm/stm32f7/nucleo-f767zi/src/stm32_bbsram.c +++ b/boards/arm/stm32f7/nucleo-f767zi/src/stm32_bbsram.c @@ -47,7 +47,7 @@ #include "nucleo-f767zi.h" -#ifdef CONFIG_STM32F7_BBSRAM +#ifdef CONFIG_STM32_BBSRAM /**************************************************************************** * Pre-processor Definitions @@ -76,7 +76,7 @@ #define BBSRAM_USED ((4*BBSRAM_HEADER_SIZE)+ \ (BBSRAM_SIZE_FN0+BBSRAM_SIZE_FN1+ \ BBSRAM_SIZE_FN2)) -#define BBSRAM_REAMINING (STM32F7_BBSRAM_SIZE-BBSRAM_USED) +#define BBSRAM_REAMINING (STM32_BBSRAM_SIZE-BBSRAM_USED) #if CONFIG_ARCH_INTERRUPTSTACK <= 3 # define BBSRAM_NUMBER_STACKS 1 #else @@ -265,7 +265,7 @@ typedef struct * Private Data ****************************************************************************/ -static uint8_t g_sdata[STM32F7_BBSRAM_SIZE]; +static uint8_t g_sdata[STM32_BBSRAM_SIZE]; /**************************************************************************** * Private Functions @@ -288,7 +288,7 @@ static int hardfault_get_desc(struct bbsramd_s *desc) } else { - ret = file_ioctl(&filestruct, STM32F7_BBSRAM_GETDESC_IOCTL, + ret = file_ioctl(&filestruct, STM32_BBSRAM_GETDESC_IOCTL, (unsigned long)((uintptr_t)desc)); file_close(&filestruct); @@ -306,7 +306,7 @@ static int hardfault_get_desc(struct bbsramd_s *desc) * Name: copy_reverse ****************************************************************************/ -#if defined(CONFIG_STM32F7_SAVE_CRASHDUMP) +#if defined(CONFIG_STM32_SAVE_CRASHDUMP) static void copy_reverse(stack_word_t *dest, stack_word_t *src, int size) { while (size--) @@ -314,7 +314,7 @@ static void copy_reverse(stack_word_t *dest, stack_word_t *src, int size) *dest++ = *src--; } } -#endif /* CONFIG_STM32F7_SAVE_CRASHDUMP */ +#endif /* CONFIG_STM32_SAVE_CRASHDUMP */ /**************************************************************************** * Public Functions @@ -326,7 +326,7 @@ static void copy_reverse(stack_word_t *dest, stack_word_t *src, int size) int stm32_bbsram_int(void) { - int filesizes[CONFIG_STM32F7_BBSRAM_FILES + 1] = BSRAM_FILE_SIZES; + int filesizes[CONFIG_STM32_BBSRAM_FILES + 1] = BSRAM_FILE_SIZES; char buf[HEADER_TIME_FMT_LEN + 1]; struct bbsramd_s desc; int rv; @@ -338,7 +338,7 @@ int stm32_bbsram_int(void) stm32_bbsraminitialize(BBSRAM_PATH, filesizes); -#if defined(CONFIG_STM32F7_SAVE_CRASHDUMP) +#if defined(CONFIG_STM32_SAVE_CRASHDUMP) /* Panic Logging in Battery Backed Up Files */ /* Do we have an hard fault in BBSRAM? */ @@ -369,7 +369,7 @@ int stm32_bbsram_int(void) " [%s] (%d)\n", HARDFAULT_PATH, rv); } } -#endif /* CONFIG_STM32F7_SAVE_CRASHDUMP */ +#endif /* CONFIG_STM32_SAVE_CRASHDUMP */ return rv; } @@ -378,7 +378,7 @@ int stm32_bbsram_int(void) * Name: board_crashdump ****************************************************************************/ -#if defined(CONFIG_STM32F7_SAVE_CRASHDUMP) +#if defined(CONFIG_STM32_SAVE_CRASHDUMP) void board_crashdump(uintptr_t sp, struct tcb_s *tcb, const char *filename, int lineno, const char *msg, void *regs) @@ -514,6 +514,6 @@ void board_crashdump(uintptr_t sp, struct tcb_s *tcb, arm_lowputc('!'); } } -#endif /* CONFIG_STM32F7_SAVE_CRASHDUMP */ +#endif /* CONFIG_STM32_SAVE_CRASHDUMP */ #endif /* CONFIG_STM32_BBSRAM */ diff --git a/boards/arm/stm32f7/nucleo-f767zi/src/stm32_boot.c b/boards/arm/stm32f7/nucleo-f767zi/src/stm32_boot.c index c6bf11bbf24da..c6224cb823cda 100644 --- a/boards/arm/stm32f7/nucleo-f767zi/src/stm32_boot.c +++ b/boards/arm/stm32f7/nucleo-f767zi/src/stm32_boot.c @@ -57,7 +57,7 @@ void stm32_boardinitialize(void) board_autoled_initialize(); #endif -#if defined(CONFIG_STM32F7_OTGFS) || defined(CONFIG_STM32F7_HOST) +#if defined(CONFIG_STM32_OTGFS) || defined(CONFIG_STM32_HOST) stm32_usbinitialize(); #endif diff --git a/boards/arm/stm32f7/nucleo-f767zi/src/stm32_bringup.c b/boards/arm/stm32f7/nucleo-f767zi/src/stm32_bringup.c index 4213f82a5a23e..8f705ee31e107 100644 --- a/boards/arm/stm32f7/nucleo-f767zi/src/stm32_bringup.c +++ b/boards/arm/stm32f7/nucleo-f767zi/src/stm32_bringup.c @@ -40,19 +40,19 @@ #include "stm32_i2c.h" -#ifdef CONFIG_STM32F7_CAN_CHARDRIVER +#ifdef CONFIG_STM32_CAN_CHARDRIVER # include "stm32_can_setup.h" #endif -#ifdef CONFIG_STM32F7_CAN_SOCKET +#ifdef CONFIG_STM32_CAN_SOCKET # include "stm32_cansock_setup.h" #endif -#ifdef CONFIG_STM32F7_ROMFS +#ifdef CONFIG_STM32_ROMFS # include "stm32_romfs.h" #endif -#ifdef CONFIG_STM32F7_SPI_TEST +#ifdef CONFIG_STM32_SPI_TEST # include "stm32_spitest.h" #endif @@ -112,14 +112,14 @@ int stm32_bringup(void) } #endif -#ifdef CONFIG_STM32F7_ROMFS +#ifdef CONFIG_STM32_ROMFS /* Mount the romfs partition */ ret = stm32_romfs_initialize(); if (ret < 0) { syslog(LOG_ERR, "ERROR: Failed to mount romfs at %s: %d\n", - CONFIG_STM32F7_ROMFS_MOUNTPOINT, ret); + CONFIG_STM32_ROMFS_MOUNTPOINT, ret); } #endif @@ -154,7 +154,7 @@ int stm32_bringup(void) } #endif -#ifdef CONFIG_STM32F7_BBSRAM +#ifdef CONFIG_STM32_BBSRAM /* Initialize battery-backed RAM */ stm32_bbsram_int(); @@ -167,7 +167,7 @@ int stm32_bringup(void) } #endif -#ifdef CONFIG_STM32F7_SPI_TEST +#ifdef CONFIG_STM32_SPI_TEST /* Create SPI interfaces */ ret = stm32_spidev_bus_test(); @@ -203,7 +203,7 @@ int stm32_bringup(void) #ifdef CONFIG_SENSORS_QENCODER char buf[9]; -#ifdef CONFIG_STM32F7_TIM1_QE +#ifdef CONFIG_STM32_TIM1_QE snprintf(buf, sizeof(buf), "/dev/qe0"); ret = stm32_qencoder_initialize(buf, 1); if (ret < 0) @@ -215,7 +215,7 @@ int stm32_bringup(void) } #endif -#ifdef CONFIG_STM32F7_TIM3_QE +#ifdef CONFIG_STM32_TIM3_QE snprintf(buf, sizeof(buf), "/dev/qe2"); ret = stm32_qencoder_initialize(buf, 3); if (ret < 0) @@ -227,7 +227,7 @@ int stm32_bringup(void) } #endif -#ifdef CONFIG_STM32F7_TIM4_QE +#ifdef CONFIG_STM32_TIM4_QE snprintf(buf, sizeof(buf), "/dev/qe3"); ret = stm32_qencoder_initialize(buf, 4); if (ret < 0) @@ -239,7 +239,7 @@ int stm32_bringup(void) } #endif -#ifdef CONFIG_STM32F7_TIM8_QE +#ifdef CONFIG_STM32_TIM8_QE snprintf(buf, sizeof(buf), "/dev/qe4"); ret = stm32_qencoder_initialize(buf, 8); if (ret < 0) @@ -253,7 +253,7 @@ int stm32_bringup(void) #endif -#ifdef CONFIG_STM32F7_CAN_CHARDRIVER +#ifdef CONFIG_STM32_CAN_CHARDRIVER ret = stm32_can_setup(); if (ret < 0) { @@ -262,7 +262,7 @@ int stm32_bringup(void) } #endif -#ifdef CONFIG_STM32F7_CAN_SOCKET +#ifdef CONFIG_STM32_CAN_SOCKET ret = stm32_cansock_setup(); if (ret < 0) { @@ -270,7 +270,7 @@ int stm32_bringup(void) } #endif -#if defined(CONFIG_I2C) && defined(CONFIG_STM32F7_I2C1) +#if defined(CONFIG_I2C) && defined(CONFIG_STM32_I2C1) i2c_bus = 1; i2c = stm32_i2cbus_initialize(i2c_bus); if (i2c == NULL) diff --git a/boards/arm/stm32f7/nucleo-f767zi/src/stm32_gpio.c b/boards/arm/stm32f7/nucleo-f767zi/src/stm32_gpio.c index 9ddb493829273..b6619c433102f 100644 --- a/boards/arm/stm32f7/nucleo-f767zi/src/stm32_gpio.c +++ b/boards/arm/stm32f7/nucleo-f767zi/src/stm32_gpio.c @@ -125,10 +125,10 @@ static const uint32_t g_gpiooutputs[BOARD_NGPIOOUT] = GPIO_OUT3, GPIO_OUT4, GPIO_OUT5, -#if !defined(CONFIG_STM32F7_TIM1_CH1NOUT) +#if !defined(CONFIG_STM32_TIM1_CH1NOUT) GPIO_OUT6, #endif -#if !defined(CONFIG_STM32F7_TIM1_CH2NOUT) +#if !defined(CONFIG_STM32_TIM1_CH2NOUT) GPIO_OUT7, #endif }; diff --git a/boards/arm/stm32f7/nucleo-f767zi/src/stm32_pwm.c b/boards/arm/stm32f7/nucleo-f767zi/src/stm32_pwm.c index 800b70d45d06e..9dbd545ea854d 100644 --- a/boards/arm/stm32f7/nucleo-f767zi/src/stm32_pwm.c +++ b/boards/arm/stm32f7/nucleo-f767zi/src/stm32_pwm.c @@ -73,7 +73,7 @@ int stm32_pwm_setup(void) { /* Call stm32_pwminitialize() to get an instance of the PWM interface */ -#if defined(CONFIG_STM32F7_TIM1_PWM) +#if defined(CONFIG_STM32_TIM1_PWM) pwm = stm32_pwminitialize(1); if (!pwm) { @@ -89,7 +89,7 @@ int stm32_pwm_setup(void) } #endif -#if defined(CONFIG_STM32F7_TIM2_PWM) +#if defined(CONFIG_STM32_TIM2_PWM) pwm = stm32_pwminitialize(2); if (!pwm) { @@ -105,7 +105,7 @@ int stm32_pwm_setup(void) } #endif -#if defined(CONFIG_STM32F7_TIM3_PWM) +#if defined(CONFIG_STM32_TIM3_PWM) pwm = stm32_pwminitialize(3); if (!pwm) { @@ -121,7 +121,7 @@ int stm32_pwm_setup(void) } #endif -#if defined(CONFIG_STM32F7_TIM4_PWM) +#if defined(CONFIG_STM32_TIM4_PWM) pwm = stm32_pwminitialize(4); if (!pwm) { diff --git a/boards/arm/stm32f7/nucleo-f767zi/src/stm32_spi.c b/boards/arm/stm32f7/nucleo-f767zi/src/stm32_spi.c index 3b19fd2fa6631..788b0c1963c5d 100644 --- a/boards/arm/stm32f7/nucleo-f767zi/src/stm32_spi.c +++ b/boards/arm/stm32f7/nucleo-f767zi/src/stm32_spi.c @@ -53,7 +53,7 @@ * Private Data ****************************************************************************/ -#if defined(CONFIG_STM32F7_SPI1) +#if defined(CONFIG_STM32_SPI1) static const uint32_t g_spi1gpio[] = { # if defined(GPIO_SPI1_CS0) @@ -79,7 +79,7 @@ static const uint32_t g_spi1gpio[] = }; #endif -#if defined(CONFIG_STM32F7_SPI2) +#if defined(CONFIG_STM32_SPI2) static const uint32_t g_spi2gpio[] = { # if defined(GPIO_SPI2_CS0) @@ -105,7 +105,7 @@ static const uint32_t g_spi2gpio[] = }; #endif -#if defined(CONFIG_STM32F7_SPI3) +#if defined(CONFIG_STM32_SPI3) static const uint32_t g_spi3gpio[] = { # if defined(GPIO_SPI3_CS0) @@ -148,7 +148,7 @@ void weak_function stm32_spidev_initialize(void) { /* Configure SPI CS GPIO for output */ -#if defined(CONFIG_STM32F7_SPI1) +#if defined(CONFIG_STM32_SPI1) for (int i = 0; i < nitems(g_spi1gpio); i++) { if (g_spi1gpio[i] != 0) @@ -158,7 +158,7 @@ void weak_function stm32_spidev_initialize(void) } #endif -#if defined(CONFIG_STM32F7_SPI2) +#if defined(CONFIG_STM32_SPI2) for (int i = 0; i < nitems(g_spi2gpio); i++) { if (g_spi2gpio[i] != 0) @@ -168,7 +168,7 @@ void weak_function stm32_spidev_initialize(void) } #endif -#if defined(CONFIG_STM32F7_SPI3) +#if defined(CONFIG_STM32_SPI3) for (int i = 0; i < nitems(g_spi3gpio); i++) { if (g_spi3gpio[i] != 0) @@ -206,7 +206,7 @@ void weak_function stm32_spidev_initialize(void) * ****************************************************************************/ -#ifdef CONFIG_STM32F7_SPI1 +#ifdef CONFIG_STM32_SPI1 void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -227,7 +227,7 @@ uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32F7_SPI2 +#ifdef CONFIG_STM32_SPI2 void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -248,7 +248,7 @@ uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32F7_SPI3 +#ifdef CONFIG_STM32_SPI3 void stm32_spi3select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -269,7 +269,7 @@ uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32F7_SPI4 +#ifdef CONFIG_STM32_SPI4 void stm32_spi4select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -283,7 +283,7 @@ uint8_t stm32_spi4status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32F7_SPI5 +#ifdef CONFIG_STM32_SPI5 void stm32_spi5select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -297,7 +297,7 @@ uint8_t stm32_spi5status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32F7_SPI6 +#ifdef CONFIG_STM32_SPI6 void stm32_spi6select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -335,42 +335,42 @@ uint8_t stm32_spi6status(struct spi_dev_s *dev, uint32_t devid) ****************************************************************************/ #ifdef CONFIG_SPI_CMDDATA -#ifdef CONFIG_STM32F7_SPI1 +#ifdef CONFIG_STM32_SPI1 int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32F7_SPI2 +#ifdef CONFIG_STM32_SPI2 int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32F7_SPI3 +#ifdef CONFIG_STM32_SPI3 int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32F7_SPI4 +#ifdef CONFIG_STM32_SPI4 int stm32_spi4cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32F7_SPI5 +#ifdef CONFIG_STM32_SPI5 int stm32_spi5cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32F7_SPI6 +#ifdef CONFIG_STM32_SPI6 int stm32_spi6cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; diff --git a/boards/arm/stm32f7/nucleo-f767zi/src/stm32_usb.c b/boards/arm/stm32f7/nucleo-f767zi/src/stm32_usb.c index 1e4c86e262326..f153ccd2c64e0 100644 --- a/boards/arm/stm32f7/nucleo-f767zi/src/stm32_usb.c +++ b/boards/arm/stm32f7/nucleo-f767zi/src/stm32_usb.c @@ -45,7 +45,7 @@ #include "stm32_otg.h" #include "nucleo-f767zi.h" -#ifdef CONFIG_STM32F7_OTGFS +#ifdef CONFIG_STM32_OTGFS /**************************************************************************** * Pre-processor Definitions @@ -138,7 +138,7 @@ void stm32_usbinitialize(void) * Power On, and Overcurrent GPIOs */ -#ifdef CONFIG_STM32F7_OTGFS +#ifdef CONFIG_STM32_OTGFS stm32_configgpio(GPIO_OTGFS_VBUS); stm32_configgpio(GPIO_OTGFS_PWRON); stm32_configgpio(GPIO_OTGFS_OVER); diff --git a/boards/arm/stm32f7/steval-eth001v1/Kconfig b/boards/arm/stm32f7/steval-eth001v1/Kconfig index 6d1513de7bcc5..64f4caa11eb29 100644 --- a/boards/arm/stm32f7/steval-eth001v1/Kconfig +++ b/boards/arm/stm32f7/steval-eth001v1/Kconfig @@ -5,12 +5,12 @@ if ARCH_BOARD_STEVAL_ETH001V1 -if STM32F7_FOC +if STM32_FOC config BOARD_STM32F7_STEVALETH001V1_FOC_VBUS bool "STEVAL-ETH001V1 board VBUS sense" default n -endif # STM32F7_FOC +endif # STM32_FOC endif # ARCH_BOARD_STEVAL_ETH001V1 diff --git a/boards/arm/stm32f7/steval-eth001v1/configs/foc_b16/defconfig b/boards/arm/stm32f7/steval-eth001v1/configs/foc_b16/defconfig index 89261567704a3..04b8ea48f2c33 100644 --- a/boards/arm/stm32f7/steval-eth001v1/configs/foc_b16/defconfig +++ b/boards/arm/stm32f7/steval-eth001v1/configs/foc_b16/defconfig @@ -15,6 +15,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="steval-eth001v1" CONFIG_ARCH_BOARD_STEVAL_ETH001V1=y CONFIG_ARCH_CHIP="stm32f7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F767ZI=y CONFIG_ARCH_CHIP_STM32F7=y CONFIG_ARCH_STACKDUMP=y @@ -59,17 +60,17 @@ CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32F7_ADC1_ANIOC_TRIGGER=1 -CONFIG_STM32F7_ADC1_DMA=y -CONFIG_STM32F7_ADC1_DMA_CFG=1 -CONFIG_STM32F7_ADC1_INJECTED_CHAN=3 -CONFIG_STM32F7_DMA2=y -CONFIG_STM32F7_FOC=y -CONFIG_STM32F7_FOC_ADC_CCR4=y -CONFIG_STM32F7_FOC_FOC0=y -CONFIG_STM32F7_FOC_HAS_PWM_COMPLEMENTARY=y -CONFIG_STM32F7_TIM1_MODE=2 -CONFIG_STM32F7_USART3=y +CONFIG_STM32_ADC1_ANIOC_TRIGGER=1 +CONFIG_STM32_ADC1_DMA=y +CONFIG_STM32_ADC1_DMA_CFG=1 +CONFIG_STM32_ADC1_INJECTED_CHAN=3 +CONFIG_STM32_DMA2=y +CONFIG_STM32_FOC=y +CONFIG_STM32_FOC_ADC_CCR4=y +CONFIG_STM32_FOC_FOC0=y +CONFIG_STM32_FOC_HAS_PWM_COMPLEMENTARY=y +CONFIG_STM32_TIM1_MODE=2 +CONFIG_STM32_USART3=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART3_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f7/steval-eth001v1/configs/foc_f32/defconfig b/boards/arm/stm32f7/steval-eth001v1/configs/foc_f32/defconfig index 2d3229bf10e2e..244c71c100b45 100644 --- a/boards/arm/stm32f7/steval-eth001v1/configs/foc_f32/defconfig +++ b/boards/arm/stm32f7/steval-eth001v1/configs/foc_f32/defconfig @@ -15,6 +15,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="steval-eth001v1" CONFIG_ARCH_BOARD_STEVAL_ETH001V1=y CONFIG_ARCH_CHIP="stm32f7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F767ZI=y CONFIG_ARCH_CHIP_STM32F7=y CONFIG_ARCH_STACKDUMP=y @@ -59,17 +60,17 @@ CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32F7_ADC1_ANIOC_TRIGGER=1 -CONFIG_STM32F7_ADC1_DMA=y -CONFIG_STM32F7_ADC1_DMA_CFG=1 -CONFIG_STM32F7_ADC1_INJECTED_CHAN=3 -CONFIG_STM32F7_DMA2=y -CONFIG_STM32F7_FOC=y -CONFIG_STM32F7_FOC_ADC_CCR4=y -CONFIG_STM32F7_FOC_FOC0=y -CONFIG_STM32F7_FOC_HAS_PWM_COMPLEMENTARY=y -CONFIG_STM32F7_TIM1_MODE=2 -CONFIG_STM32F7_USART3=y +CONFIG_STM32_ADC1_ANIOC_TRIGGER=1 +CONFIG_STM32_ADC1_DMA=y +CONFIG_STM32_ADC1_DMA_CFG=1 +CONFIG_STM32_ADC1_INJECTED_CHAN=3 +CONFIG_STM32_DMA2=y +CONFIG_STM32_FOC=y +CONFIG_STM32_FOC_ADC_CCR4=y +CONFIG_STM32_FOC_FOC0=y +CONFIG_STM32_FOC_HAS_PWM_COMPLEMENTARY=y +CONFIG_STM32_TIM1_MODE=2 +CONFIG_STM32_USART3=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART3_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f7/steval-eth001v1/configs/nsh/defconfig b/boards/arm/stm32f7/steval-eth001v1/configs/nsh/defconfig index cf898372ae82d..4e4dea5daa432 100644 --- a/boards/arm/stm32f7/steval-eth001v1/configs/nsh/defconfig +++ b/boards/arm/stm32f7/steval-eth001v1/configs/nsh/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="steval-eth001v1" CONFIG_ARCH_BOARD_STEVAL_ETH001V1=y CONFIG_ARCH_CHIP="stm32f7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F767ZI=y CONFIG_ARCH_CHIP_STM32F7=y CONFIG_ARCH_STACKDUMP=y @@ -39,7 +40,7 @@ CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32F7_USART3=y +CONFIG_STM32_USART3=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART3_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f7/steval-eth001v1/include/board.h b/boards/arm/stm32f7/steval-eth001v1/include/board.h index cc62976fda671..8b6cb2f790f61 100644 --- a/boards/arm/stm32f7/steval-eth001v1/include/board.h +++ b/boards/arm/stm32f7/steval-eth001v1/include/board.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32F7_STEVAL_ETH001V1_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32F7_STEVAL_ETH001V1_INCLUDE_BOARD_H +#ifndef __BOARDS_ARM_STM32_STEVAL_ETH001V1_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32_STEVAL_ETH001V1_INCLUDE_BOARD_H /**************************************************************************** * Included Files @@ -241,4 +241,4 @@ #define GPIO_TIM2_CH2IN (GPIO_TIM2_CH2IN_1|GPIO_SPEED_50MHz) /* PA1 */ #define GPIO_TIM2_CH3IN (GPIO_TIM2_CH3IN_1|GPIO_SPEED_50MHz) /* PA2 */ -#endif /* __BOARDS_ARM_STM32F7_STEVAL_ETH001V1_INCLUDE_BOARD_H */ +#endif /* __BOARDS_ARM_STM32_STEVAL_ETH001V1_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32f7/steval-eth001v1/src/CMakeLists.txt b/boards/arm/stm32f7/steval-eth001v1/src/CMakeLists.txt index 0082f8f94996b..fb3a6271dbe90 100644 --- a/boards/arm/stm32f7/steval-eth001v1/src/CMakeLists.txt +++ b/boards/arm/stm32f7/steval-eth001v1/src/CMakeLists.txt @@ -22,7 +22,7 @@ set(SRCS stm32_boot.c stm32_bringup.c) -if(CONFIG_STM32F7_FOC) +if(CONFIG_STM32_FOC) list(APPEND SRCS stm32_foc.c) endif() diff --git a/boards/arm/stm32f7/steval-eth001v1/src/Make.defs b/boards/arm/stm32f7/steval-eth001v1/src/Make.defs index ace68763fc406..6d4a16a40b5d8 100644 --- a/boards/arm/stm32f7/steval-eth001v1/src/Make.defs +++ b/boards/arm/stm32f7/steval-eth001v1/src/Make.defs @@ -24,7 +24,7 @@ include $(TOPDIR)/Make.defs CSRCS = stm32_boot.c stm32_bringup.c -ifeq ($(CONFIG_STM32F7_FOC),y) +ifeq ($(CONFIG_STM32_FOC),y) CSRCS += stm32_foc.c endif diff --git a/boards/arm/stm32f7/steval-eth001v1/src/steval-eth001v1.h b/boards/arm/stm32f7/steval-eth001v1/src/steval-eth001v1.h index 22026d5156f7f..ffa6fb87c1df1 100644 --- a/boards/arm/stm32f7/steval-eth001v1/src/steval-eth001v1.h +++ b/boards/arm/stm32f7/steval-eth001v1/src/steval-eth001v1.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32F7_STEVAL_ETH001V1_SRC_STEVAL_ETH001V1_H -#define __BOARDS_ARM_STM32F7_STEVAL_ETH001V1_SRC_STEVAL_ETH001V1_H +#ifndef __BOARDS_ARM_STM32_STEVAL_ETH001V1_SRC_STEVAL_ETH001V1_H +#define __BOARDS_ARM_STM32_STEVAL_ETH001V1_SRC_STEVAL_ETH001V1_H /**************************************************************************** * Included Files @@ -72,7 +72,7 @@ int stm32_bringup(void); * ****************************************************************************/ -#ifdef CONFIG_STM32F7_FOC +#ifdef CONFIG_STM32_FOC int stm32_foc_setup(void); #endif @@ -90,4 +90,4 @@ int stm32_adc_setup(void); #endif /* __ASSEMBLY__ */ -#endif /* __BOARDS_ARM_STM32F7_STEVAL_ETH001V1_SRC_STEVAL_ETH001V1_H */ +#endif /* __BOARDS_ARM_STM32_STEVAL_ETH001V1_SRC_STEVAL_ETH001V1_H */ diff --git a/boards/arm/stm32f7/steval-eth001v1/src/stm32_bringup.c b/boards/arm/stm32f7/steval-eth001v1/src/stm32_bringup.c index 1ef16e93ce097..b69d7f7481979 100644 --- a/boards/arm/stm32f7/steval-eth001v1/src/stm32_bringup.c +++ b/boards/arm/stm32f7/steval-eth001v1/src/stm32_bringup.c @@ -65,7 +65,7 @@ int stm32_bringup(void) } #endif -#ifdef CONFIG_STM32F7_FOC +#ifdef CONFIG_STM32_FOC /* Initialize and register the FOC device - must be before ADC setup */ ret = stm32_foc_setup(); diff --git a/boards/arm/stm32f7/steval-eth001v1/src/stm32_foc.c b/boards/arm/stm32f7/steval-eth001v1/src/stm32_foc.c index 9a27e7bc94852..93d7ec8bd1e28 100644 --- a/boards/arm/stm32f7/steval-eth001v1/src/stm32_foc.c +++ b/boards/arm/stm32f7/steval-eth001v1/src/stm32_foc.c @@ -54,33 +54,33 @@ * 2. PWM complementary channels must have positive polarity */ -#ifndef CONFIG_STM32F7_FOC_HAS_PWM_COMPLEMENTARY +#ifndef CONFIG_STM32_FOC_HAS_PWM_COMPLEMENTARY # error #endif -#if CONFIG_STM32F7_TIM1_CH1POL != 0 +#if CONFIG_STM32_TIM1_CH1POL != 0 # error #endif -#if CONFIG_STM32F7_TIM1_CH2POL != 0 +#if CONFIG_STM32_TIM1_CH2POL != 0 # error #endif -#if CONFIG_STM32F7_TIM1_CH3POL != 0 +#if CONFIG_STM32_TIM1_CH3POL != 0 # error #endif -#if CONFIG_STM32F7_TIM1_CH1NPOL != 0 +#if CONFIG_STM32_TIM1_CH1NPOL != 0 # error #endif -#if CONFIG_STM32F7_TIM1_CH2NPOL != 0 +#if CONFIG_STM32_TIM1_CH2NPOL != 0 # error #endif -#if CONFIG_STM32F7_TIM1_CH3NPOL != 0 +#if CONFIG_STM32_TIM1_CH3NPOL != 0 # error #endif /* Aux ADC needs DMA enabled */ #ifdef CONFIG_ADC -# ifndef CONFIG_STM32F7_ADC1_DMA +# ifndef CONFIG_STM32_ADC1_DMA # error # endif #endif @@ -122,7 +122,7 @@ #define ADC1_INJECTED (CONFIG_MOTOR_FOC_SHUNTS) -#ifdef CONFIG_BOARD_STM32F7_STEVALETH001V1_FOC_VBUS +#ifdef CONFIG_BOARD_STM32_STEVALETH001V1_FOC_VBUS # define STEVALETH001V1_FOC_VBUS 1 #else # define STEVALETH001V1_FOC_VBUS 0 @@ -133,11 +133,11 @@ /* Check ADC1 configuration */ -#if ADC1_INJECTED != CONFIG_STM32F7_ADC1_INJECTED_CHAN +#if ADC1_INJECTED != CONFIG_STM32_ADC1_INJECTED_CHAN # error #endif -#if CONFIG_STM32F7_ADC1_RESOLUTION != 0 +#if CONFIG_STM32_ADC1_RESOLUTION != 0 # error #endif @@ -186,7 +186,7 @@ static void board_foc_trace(struct foc_dev_s *dev, int type, bool state); static uint8_t g_adc1_chan[] = { -#ifdef CONFIG_BOARD_STM32F7_STEVALETH001V1_FOC_VBUS +#ifdef CONFIG_BOARD_STM32_STEVALETH001V1_FOC_VBUS 14, /* ADC1 REG - VBUS */ #endif 15, /* ADC1 INJ1 - PHASE 1 */ @@ -196,7 +196,7 @@ static uint8_t g_adc1_chan[] = static uint32_t g_adc1_pins[] = { -#ifdef CONFIG_BOARD_STM32F7_STEVALETH001V1_FOC_VBUS +#ifdef CONFIG_BOARD_STM32_STEVALETH001V1_FOC_VBUS GPIO_ADC1_IN14, #endif GPIO_ADC1_IN15, @@ -208,7 +208,7 @@ static uint32_t g_adc1_pins[] = static adc_channel_t g_adc1_stime[] = { -#ifdef CONFIG_BOARD_STM32F7_STEVALETH001V1_FOC_VBUS +#ifdef CONFIG_BOARD_STM32_STEVALETH001V1_FOC_VBUS { .channel = 14, .sample_time = VBUS_SAMPLE_TIME diff --git a/boards/arm/stm32f7/stm32f746-ws/configs/nsh/defconfig b/boards/arm/stm32f7/stm32f746-ws/configs/nsh/defconfig index 378ee084c7f8b..30bf96e0d37bc 100644 --- a/boards/arm/stm32f7/stm32f746-ws/configs/nsh/defconfig +++ b/boards/arm/stm32f7/stm32f746-ws/configs/nsh/defconfig @@ -15,6 +15,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32f746-ws" CONFIG_ARCH_BOARD_STM32F746_WS=y CONFIG_ARCH_CHIP="stm32f7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F746IG=y CONFIG_ARCH_CHIP_STM32F7=y CONFIG_ARCH_INTERRUPTSTACK=2600 @@ -75,15 +76,15 @@ CONFIG_STACK_COLORATION=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32F7_ADC1=y -CONFIG_STM32F7_DMA2=y -CONFIG_STM32F7_DMACAPABLE=y -CONFIG_STM32F7_I2C1=y -CONFIG_STM32F7_OTGFS=y -CONFIG_STM32F7_SDMMC1=y -CONFIG_STM32F7_SDMMC_DMA=y -CONFIG_STM32F7_SPI1=y -CONFIG_STM32F7_USART6=y +CONFIG_STM32_ADC1=y +CONFIG_STM32_DMA2=y +CONFIG_STM32_DMACAPABLE=y +CONFIG_STM32_I2C1=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_SDMMC1=y +CONFIG_STM32_SDMMC_DMA=y +CONFIG_STM32_SPI1=y +CONFIG_STM32_USART6=y CONFIG_SYSTEM_CDCACM=y CONFIG_SYSTEM_I2CTOOL=y CONFIG_SYSTEM_NSH=y diff --git a/boards/arm/stm32f7/stm32f746-ws/include/board.h b/boards/arm/stm32f7/stm32f746-ws/include/board.h index b525313ee6549..9bc6dc43c7c33 100644 --- a/boards/arm/stm32f7/stm32f746-ws/include/board.h +++ b/boards/arm/stm32f7/stm32f746-ws/include/board.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32F7_STM32F746_WS_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32F7_STM32F746_WS_INCLUDE_BOARD_H +#ifndef __BOARDS_ARM_STM32_STM32F746_WS_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32_STM32F746_WS_INCLUDE_BOARD_H /**************************************************************************** * Included Files @@ -108,7 +108,7 @@ /* Configure factors for PLLSAI clock */ -#define CONFIG_STM32F7_PLLSAI 1 +#define CONFIG_STM32_PLLSAI 1 #define STM32_RCC_PLLSAICFGR_PLLSAIN RCC_PLLSAICFGR_PLLSAIN(192) #define STM32_RCC_PLLSAICFGR_PLLSAIP RCC_PLLSAICFGR_PLLSAIP(2) #define STM32_RCC_PLLSAICFGR_PLLSAIQ RCC_PLLSAICFGR_PLLSAIQ(2) @@ -127,7 +127,7 @@ /* Configure factors for PLLI2S clock */ -#define CONFIG_STM32F7_PLLI2S 1 +#define CONFIG_STM32_PLLI2S 1 #define STM32_RCC_PLLI2SCFGR_PLLI2SN RCC_PLLI2SCFGR_PLLI2SN(192) #define STM32_RCC_PLLI2SCFGR_PLLI2SP RCC_PLLI2SCFGR_PLLI2SP(2) #define STM32_RCC_PLLI2SCFGR_PLLI2SQ RCC_PLLI2SCFGR_PLLI2SQ(2) @@ -316,4 +316,4 @@ #define GPIO_OTGFS_DP (GPIO_OTGFS_DP_0|GPIO_SPEED_100MHz) #define GPIO_OTGFS_ID (GPIO_OTGFS_ID_0|GPIO_SPEED_100MHz) -#endif /* __BOARDS_ARM_STM32F7_STM32F746_WS_INCLUDE_BOARD_H */ +#endif /* __BOARDS_ARM_STM32_STM32F746_WS_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32f7/stm32f746-ws/src/CMakeLists.txt b/boards/arm/stm32f7/stm32f746-ws/src/CMakeLists.txt index 973faf1d30432..00b881c28cf6a 100644 --- a/boards/arm/stm32f7/stm32f746-ws/src/CMakeLists.txt +++ b/boards/arm/stm32f7/stm32f746-ws/src/CMakeLists.txt @@ -22,11 +22,11 @@ set(SRCS stm32_boot.c stm32_spi.c stm32_dma_alloc.c) -if(CONFIG_STM32F7_OTGFS) +if(CONFIG_STM32_OTGFS) list(APPEND SRCS stm32_usb.c) endif() -if(CONFIG_STM32F7_SDMMC1) +if(CONFIG_STM32_SDMMC1) list(APPEND SRCS stm32_sdmmc.c) endif() diff --git a/boards/arm/stm32f7/stm32f746-ws/src/Make.defs b/boards/arm/stm32f7/stm32f746-ws/src/Make.defs index 80e52803544eb..67df23791a92a 100644 --- a/boards/arm/stm32f7/stm32f746-ws/src/Make.defs +++ b/boards/arm/stm32f7/stm32f746-ws/src/Make.defs @@ -24,11 +24,11 @@ include $(TOPDIR)/Make.defs CSRCS = stm32_boot.c stm32_spi.c stm32_dma_alloc.c -ifeq ($(CONFIG_STM32F7_OTGFS),y) +ifeq ($(CONFIG_STM32_OTGFS),y) CSRCS += stm32_usb.c endif -ifeq ($(CONFIG_STM32F7_SDMMC1),y) +ifeq ($(CONFIG_STM32_SDMMC1),y) CSRCS += stm32_sdmmc.c endif diff --git a/boards/arm/stm32f7/stm32f746-ws/src/stm32_boot.c b/boards/arm/stm32f7/stm32f746-ws/src/stm32_boot.c index eb4801aefb4ca..16dc06038d050 100644 --- a/boards/arm/stm32f7/stm32f746-ws/src/stm32_boot.c +++ b/boards/arm/stm32f7/stm32f746-ws/src/stm32_boot.c @@ -86,9 +86,9 @@ static void stm32_i2ctool(void) void stm32_boardinitialize(void) { -#if defined(CONFIG_STM32F7_SPI1) || defined(CONFIG_STM32F7_SPI2) || \ - defined(CONFIG_STM32F7_SPI3) || defined(CONFIG_STM32F7_SPI4) || \ - defined(CONFIG_STM32F7_SPI5) || defined(CONFIG_STM32F7_SPI6) +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || \ + defined(CONFIG_STM32_SPI3) || defined(CONFIG_STM32_SPI4) || \ + defined(CONFIG_STM32_SPI5) || defined(CONFIG_STM32_SPI6) /* Configure SPI chip selects if 1) SPI is not disabled, and 2) the weak * function stm32_spidev_initialize() has been brought into the link. */ @@ -127,7 +127,7 @@ void board_late_initialize(void) } #endif -#ifdef CONFIG_STM32F7_SDMMC1 +#ifdef CONFIG_STM32_SDMMC1 /* Initialize the SDIO block driver */ int ret = OK; diff --git a/boards/arm/stm32f7/stm32f746-ws/src/stm32_spi.c b/boards/arm/stm32f7/stm32f746-ws/src/stm32_spi.c index 9d86414318e99..17ca34d8bfaad 100644 --- a/boards/arm/stm32f7/stm32f746-ws/src/stm32_spi.c +++ b/boards/arm/stm32f7/stm32f746-ws/src/stm32_spi.c @@ -40,9 +40,9 @@ #include "stm32f746-ws.h" -#if defined(CONFIG_STM32F7_SPI1) || defined(CONFIG_STM32F7_SPI2) || \ - defined(CONFIG_STM32F7_SPI3) || defined(CONFIG_STM32F7_SPI4) || \ - defined(CONFIG_STM32F7_SPI5) || defined(CONFIG_STM32F7_SPI6) +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || \ + defined(CONFIG_STM32_SPI3) || defined(CONFIG_STM32_SPI4) || \ + defined(CONFIG_STM32_SPI5) || defined(CONFIG_STM32_SPI6) /**************************************************************************** * Public Functions @@ -87,7 +87,7 @@ void weak_function stm32_spidev_initialize(void) * ****************************************************************************/ -#ifdef CONFIG_STM32F7_SPI1 +#ifdef CONFIG_STM32_SPI1 void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -101,7 +101,7 @@ uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32F7_SPI2 +#ifdef CONFIG_STM32_SPI2 void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -115,7 +115,7 @@ uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32F7_SPI3 +#ifdef CONFIG_STM32_SPI3 void stm32_spi3select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -129,7 +129,7 @@ uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32F7_SPI4 +#ifdef CONFIG_STM32_SPI4 void stm32_spi4select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -143,7 +143,7 @@ uint8_t stm32_spi4status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32F7_SPI5 +#ifdef CONFIG_STM32_SPI5 void stm32_spi5select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -157,7 +157,7 @@ uint8_t stm32_spi5status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32F7_SPI6 +#ifdef CONFIG_STM32_SPI6 void stm32_spi6select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -195,42 +195,42 @@ uint8_t stm32_spi6status(struct spi_dev_s *dev, uint32_t devid) ****************************************************************************/ #ifdef CONFIG_SPI_CMDDATA -#ifdef CONFIG_STM32F7_SPI1 +#ifdef CONFIG_STM32_SPI1 int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32F7_SPI2 +#ifdef CONFIG_STM32_SPI2 int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32F7_SPI3 +#ifdef CONFIG_STM32_SPI3 int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32F7_SPI4 +#ifdef CONFIG_STM32_SPI4 int stm32_spi4cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32F7_SPI5 +#ifdef CONFIG_STM32_SPI5 int stm32_spi5cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32F7_SPI6 +#ifdef CONFIG_STM32_SPI6 int stm32_spi6cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; @@ -238,4 +238,4 @@ int stm32_spi6cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) #endif #endif /* CONFIG_SPI_CMDDATA */ -#endif /* CONFIG_STM32F7_SPI1 || ... CONFIG_STM32F7_SPI6 */ +#endif /* CONFIG_STM32_SPI1 || ... CONFIG_STM32_SPI6 */ diff --git a/boards/arm/stm32f7/stm32f746-ws/src/stm32_usb.c b/boards/arm/stm32f7/stm32f746-ws/src/stm32_usb.c index b4a9bf9f1926f..4625864a28b2e 100644 --- a/boards/arm/stm32f7/stm32f746-ws/src/stm32_usb.c +++ b/boards/arm/stm32f7/stm32f746-ws/src/stm32_usb.c @@ -44,7 +44,7 @@ #include "stm32_gpio.h" #include "stm32f746-ws.h" -#ifdef CONFIG_STM32F7_OTGFS +#ifdef CONFIG_STM32_OTGFS /**************************************************************************** * Pre-processor Definitions @@ -53,7 +53,7 @@ #if defined(CONFIG_USBDEV) || defined(CONFIG_USBHOST) # define HAVE_USB 1 #else -# warning "CONFIG_STM32F7_OTGFS is enabled but neither CONFIG_USBDEV nor CONFIG_USBHOST" +# warning "CONFIG_STM32_OTGFS is enabled but neither CONFIG_USBDEV nor CONFIG_USBHOST" # undef HAVE_USB #endif @@ -137,7 +137,7 @@ void stm32_usbinitialize(void) * Power On, and Overcurrent GPIOs */ -#ifdef CONFIG_STM32F7_OTGFS +#ifdef CONFIG_STM32_OTGFS stm32_configgpio(GPIO_OTGFS_VBUS); #ifdef CONFIG_USBHOST @@ -330,4 +330,4 @@ void stm32_usbsuspend(struct usbdev_s *dev, bool resume) } #endif -#endif /* CONFIG_STM32F7_OTGFS */ +#endif /* CONFIG_STM32_OTGFS */ diff --git a/boards/arm/stm32f7/stm32f746-ws/src/stm32f746-ws.h b/boards/arm/stm32f7/stm32f746-ws/src/stm32f746-ws.h index 80532801ade46..ddc9e0711e458 100644 --- a/boards/arm/stm32f7/stm32f746-ws/src/stm32f746-ws.h +++ b/boards/arm/stm32f7/stm32f746-ws/src/stm32f746-ws.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32F7_STM32F746_WS_SRC_STM32F746_WS_H -#define __BOARDS_ARM_STM32F7_STM32F746_WS_SRC_STM32F746_WS_H +#ifndef __BOARDS_ARM_STM32_STM32F746_WS_SRC_STM32F746_WS_H +#define __BOARDS_ARM_STM32_STM32F746_WS_SRC_STM32F746_WS_H /**************************************************************************** * Included Files @@ -108,7 +108,7 @@ void weak_function stm32_spidev_initialize(void); * ****************************************************************************/ -#if !defined(CONFIG_DISABLE_MOUNTPOINT) && defined(CONFIG_STM32F7_SDMMC1) +#if !defined(CONFIG_DISABLE_MOUNTPOINT) && defined(CONFIG_STM32_SDMMC1) int stm32_sdio_initialize(void); #endif @@ -128,4 +128,4 @@ int stm32_dma_alloc_init(void); #endif #endif /* __ASSEMBLY__ */ -#endif /* __BOARDS_ARM_STM32F7_STM32F746_WS_SRC_STM32F746_WS_H */ +#endif /* __BOARDS_ARM_STM32_STM32F746_WS_SRC_STM32F746_WS_H */ diff --git a/boards/arm/stm32f7/stm32f746g-disco/Kconfig b/boards/arm/stm32f7/stm32f746g-disco/Kconfig index 40785710b6d8e..15c51d8a03e1d 100644 --- a/boards/arm/stm32f7/stm32f746g-disco/Kconfig +++ b/boards/arm/stm32f7/stm32f746g-disco/Kconfig @@ -12,7 +12,7 @@ config STM32F746GDISCO_FLASH select MTD_N25QXXX select MTD_SMART select FS_SMARTFS - select STM32F7_QUADSPI + select STM32_QSPI select MTD_BYTE_WRITE ---help--- Configures an MTD device for use with the onboard flash diff --git a/boards/arm/stm32f7/stm32f746g-disco/configs/audio/defconfig b/boards/arm/stm32f7/stm32f746g-disco/configs/audio/defconfig index 0205e65dc256e..59a85748ed622 100644 --- a/boards/arm/stm32f7/stm32f746g-disco/configs/audio/defconfig +++ b/boards/arm/stm32f7/stm32f746g-disco/configs/audio/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH_BOARD="stm32f746g-disco" CONFIG_ARCH_BOARD_STM32F746G_DISCO=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32f7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F746NG=y CONFIG_ARCH_CHIP_STM32F7=y CONFIG_ARCH_STACKDUMP=y @@ -59,13 +60,13 @@ CONFIG_SPI=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32F7_DMA2=y -CONFIG_STM32F7_I2C3=y -CONFIG_STM32F7_SAI2=y -CONFIG_STM32F7_SAI2_A=y -CONFIG_STM32F7_SAI2_B=y -CONFIG_STM32F7_SAI2_B_SYNC_WITH_A=y -CONFIG_STM32F7_USART1=y +CONFIG_STM32_DMA2=y +CONFIG_STM32_I2C3=y +CONFIG_STM32_SAI2=y +CONFIG_STM32_SAI2_A=y +CONFIG_STM32_SAI2_B=y +CONFIG_STM32_SAI2_B_SYNC_WITH_A=y +CONFIG_STM32_USART1=y CONFIG_SYSLOG_CHAR=y CONFIG_SYSLOG_DEVPATH="/dev/ttyS0" CONFIG_SYSTEM_NSH=y diff --git a/boards/arm/stm32f7/stm32f746g-disco/configs/fb/defconfig b/boards/arm/stm32f7/stm32f746g-disco/configs/fb/defconfig index 1a6201d978f27..f437e6b8e7165 100644 --- a/boards/arm/stm32f7/stm32f746g-disco/configs/fb/defconfig +++ b/boards/arm/stm32f7/stm32f746g-disco/configs/fb/defconfig @@ -8,13 +8,14 @@ # CONFIG_ARCH_FPU is not set # CONFIG_NSH_DISABLE_IFCONFIG is not set # CONFIG_NSH_DISABLE_PS is not set -# CONFIG_STM32F7_FB_CMAP is not set -# CONFIG_STM32F7_LTDC_L2 is not set +# CONFIG_STM32_FB_CMAP is not set +# CONFIG_STM32_LTDC_L2 is not set CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32f746g-disco" CONFIG_ARCH_BOARD_STM32F746G_DISCO=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32f7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F746NG=y CONFIG_ARCH_CHIP_STM32F7=y CONFIG_ARCH_STACKDUMP=y @@ -48,11 +49,11 @@ CONFIG_SPI=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32F7_FMC=y -CONFIG_STM32F7_LTDC=y -CONFIG_STM32F7_LTDC_FB_BASE=0xc0000000 -CONFIG_STM32F7_LTDC_FB_SIZE=261120 -CONFIG_STM32F7_USART1=y +CONFIG_STM32_FMC=y +CONFIG_STM32_LTDC=y +CONFIG_STM32_LTDC_FB_BASE=0xc0000000 +CONFIG_STM32_LTDC_FB_SIZE=261120 +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f7/stm32f746g-disco/configs/lvgl/defconfig b/boards/arm/stm32f7/stm32f746g-disco/configs/lvgl/defconfig index cb454fadbe662..4783972604f05 100644 --- a/boards/arm/stm32f7/stm32f746g-disco/configs/lvgl/defconfig +++ b/boards/arm/stm32f7/stm32f746g-disco/configs/lvgl/defconfig @@ -9,13 +9,14 @@ # CONFIG_LV_BUILD_EXAMPLES is not set # CONFIG_NSH_DISABLE_IFCONFIG is not set # CONFIG_NSH_DISABLE_PS is not set -# CONFIG_STM32F7_FB_CMAP is not set -# CONFIG_STM32F7_LTDC_L2 is not set +# CONFIG_STM32_FB_CMAP is not set +# CONFIG_STM32_LTDC_L2 is not set CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32f746g-disco" CONFIG_ARCH_BOARD_STM32F746G_DISCO=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32f7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F746NG=y CONFIG_ARCH_CHIP_STM32F7=y CONFIG_ARCH_STACKDUMP=y @@ -61,13 +62,13 @@ CONFIG_RR_INTERVAL=200 CONFIG_SCHED_HPWORK=y CONFIG_SCHED_WAITPID=y CONFIG_STM32F746GDISCO_TOUCHSCREEN_SWAPXY=y -CONFIG_STM32F7_EXTERNAL_RAM=y -CONFIG_STM32F7_FMC=y -CONFIG_STM32F7_I2C3=y -CONFIG_STM32F7_LTDC=y -CONFIG_STM32F7_LTDC_FB_BASE=0xc0000000 -CONFIG_STM32F7_LTDC_FB_SIZE=261120 -CONFIG_STM32F7_USART1=y +CONFIG_STM32_EXTERNAL_RAM=y +CONFIG_STM32_FMC=y +CONFIG_STM32_I2C3=y +CONFIG_STM32_LTDC=y +CONFIG_STM32_LTDC_FB_BASE=0xc0000000 +CONFIG_STM32_LTDC_FB_SIZE=261120 +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_USART1_SERIAL_CONSOLE=y CONFIG_VIDEO_FB=y diff --git a/boards/arm/stm32f7/stm32f746g-disco/configs/netnsh/defconfig b/boards/arm/stm32f7/stm32f746g-disco/configs/netnsh/defconfig index a72895966d05c..ea305fd81647f 100644 --- a/boards/arm/stm32f7/stm32f746g-disco/configs/netnsh/defconfig +++ b/boards/arm/stm32f7/stm32f746g-disco/configs/netnsh/defconfig @@ -11,6 +11,7 @@ CONFIG_ARCH_BOARD="stm32f746g-disco" CONFIG_ARCH_BOARD_STM32F746G_DISCO=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32f7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F746NG=y CONFIG_ARCH_CHIP_STM32F7=y CONFIG_ARCH_STACKDUMP=y @@ -61,16 +62,16 @@ CONFIG_RR_INTERVAL=20 CONFIG_SCHED_HPWORK=y CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=14 -CONFIG_STM32F7_ETHMAC=y -CONFIG_STM32F7_PHYADDR=0 -CONFIG_STM32F7_PHYSR=31 -CONFIG_STM32F7_PHYSR_100FD=0x0018 -CONFIG_STM32F7_PHYSR_100HD=0x0008 -CONFIG_STM32F7_PHYSR_10FD=0x0014 -CONFIG_STM32F7_PHYSR_10HD=0x0004 -CONFIG_STM32F7_PHYSR_ALTCONFIG=y -CONFIG_STM32F7_PHYSR_ALTMODE=0x001c -CONFIG_STM32F7_USART1=y +CONFIG_STM32_ETHMAC=y +CONFIG_STM32_PHYADDR=0 +CONFIG_STM32_PHYSR=31 +CONFIG_STM32_PHYSR_100FD=0x0018 +CONFIG_STM32_PHYSR_100HD=0x0008 +CONFIG_STM32_PHYSR_10FD=0x0014 +CONFIG_STM32_PHYSR_10HD=0x0004 +CONFIG_STM32_PHYSR_ALTCONFIG=y +CONFIG_STM32_PHYSR_ALTMODE=0x001c +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f7/stm32f746g-disco/configs/nsh/defconfig b/boards/arm/stm32f7/stm32f746g-disco/configs/nsh/defconfig index b7d6e8247b10a..870f454c8061e 100644 --- a/boards/arm/stm32f7/stm32f746g-disco/configs/nsh/defconfig +++ b/boards/arm/stm32f7/stm32f746g-disco/configs/nsh/defconfig @@ -13,6 +13,7 @@ CONFIG_ARCH_BOARD="stm32f746g-disco" CONFIG_ARCH_BOARD_STM32F746G_DISCO=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32f7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F746NG=y CONFIG_ARCH_CHIP_STM32F7=y CONFIG_ARCH_STACKDUMP=y @@ -43,7 +44,7 @@ CONFIG_SPI=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32F7_USART1=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f7/stm32f746g-disco/configs/nxdemo/defconfig b/boards/arm/stm32f7/stm32f746g-disco/configs/nxdemo/defconfig index bef22e038407a..3ac4ed78996c0 100644 --- a/boards/arm/stm32f7/stm32f746g-disco/configs/nxdemo/defconfig +++ b/boards/arm/stm32f7/stm32f746g-disco/configs/nxdemo/defconfig @@ -9,13 +9,14 @@ # CONFIG_NSH_DISABLE_IFCONFIG is not set # CONFIG_NSH_DISABLE_PS is not set # CONFIG_NX_DISABLE_16BPP is not set -# CONFIG_STM32F7_FB_CMAP is not set -# CONFIG_STM32F7_LTDC_L2 is not set +# CONFIG_STM32_FB_CMAP is not set +# CONFIG_STM32_LTDC_L2 is not set CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32f746g-disco" CONFIG_ARCH_BOARD_STM32F746G_DISCO=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32f7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F746NG=y CONFIG_ARCH_CHIP_STM32F7=y CONFIG_ARCH_STACKDUMP=y @@ -57,11 +58,11 @@ CONFIG_RAM_START=0x20010000 CONFIG_RAW_BINARY=y CONFIG_RR_INTERVAL=200 CONFIG_SCHED_WAITPID=y -CONFIG_STM32F7_FMC=y -CONFIG_STM32F7_LTDC=y -CONFIG_STM32F7_LTDC_FB_BASE=0xc0000000 -CONFIG_STM32F7_LTDC_FB_SIZE=261120 -CONFIG_STM32F7_USART1=y +CONFIG_STM32_FMC=y +CONFIG_STM32_LTDC=y +CONFIG_STM32_LTDC_FB_BASE=0xc0000000 +CONFIG_STM32_LTDC_FB_SIZE=261120 +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_USART1_SERIAL_CONSOLE=y CONFIG_VIDEO_FB=y diff --git a/boards/arm/stm32f7/stm32f746g-disco/configs/nxterm/defconfig b/boards/arm/stm32f7/stm32f746g-disco/configs/nxterm/defconfig index b1d0a83557572..59395d2b919fb 100644 --- a/boards/arm/stm32f7/stm32f746g-disco/configs/nxterm/defconfig +++ b/boards/arm/stm32f7/stm32f746g-disco/configs/nxterm/defconfig @@ -10,13 +10,14 @@ # CONFIG_NSH_DISABLE_PS is not set # CONFIG_NXFONTS_DISABLE_16BPP is not set # CONFIG_NX_DISABLE_16BPP is not set -# CONFIG_STM32F7_FB_CMAP is not set -# CONFIG_STM32F7_LTDC_L2 is not set +# CONFIG_STM32_FB_CMAP is not set +# CONFIG_STM32_LTDC_L2 is not set CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32f746g-disco" CONFIG_ARCH_BOARD_STM32F746G_DISCO=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32f7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F746NG=y CONFIG_ARCH_CHIP_STM32F7=y CONFIG_ARCH_STACKDUMP=y @@ -50,11 +51,11 @@ CONFIG_RAM_START=0x20010000 CONFIG_RAW_BINARY=y CONFIG_RR_INTERVAL=200 CONFIG_SCHED_WAITPID=y -CONFIG_STM32F7_FMC=y -CONFIG_STM32F7_LTDC=y -CONFIG_STM32F7_LTDC_FB_BASE=0xc0000000 -CONFIG_STM32F7_LTDC_FB_SIZE=261120 -CONFIG_STM32F7_USART1=y +CONFIG_STM32_FMC=y +CONFIG_STM32_LTDC=y +CONFIG_STM32_LTDC_FB_BASE=0xc0000000 +CONFIG_STM32_LTDC_FB_SIZE=261120 +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_USART1_SERIAL_CONSOLE=y CONFIG_VIDEO_FB=y diff --git a/boards/arm/stm32f7/stm32f746g-disco/include/board.h b/boards/arm/stm32f7/stm32f746g-disco/include/board.h index b390498974974..f082dfa5aa885 100644 --- a/boards/arm/stm32f7/stm32f746g-disco/include/board.h +++ b/boards/arm/stm32f7/stm32f746g-disco/include/board.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32F7_STM32F746G_DISCO_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32F7_STM32F746G_DISCO_INCLUDE_BOARD_H +#ifndef __BOARDS_ARM_STM32_STM32F746G_DISCO_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32_STM32F746G_DISCO_INCLUDE_BOARD_H /**************************************************************************** * Included Files @@ -90,7 +90,7 @@ * 2 <= PLLQ <= 15 */ -#if defined(CONFIG_STM32F7_OTGFS) +#if defined(CONFIG_STM32_OTGFS) /* Highest SYSCLK with USB OTG FS clock = 48 MHz * * PLL_VCO = (25,000,000 / 25) * 384 = 384 MHz @@ -107,7 +107,7 @@ #define STM32_SYSCLK_FREQUENCY (STM32_VCO_FREQUENCY / 2) #define STM32_OTGFS_FREQUENCY (STM32_VCO_FREQUENCY / 8) -#elif defined(CONFIG_STM32F7_SDMMC1) || defined(CONFIG_STM32F7_RNG) +#elif defined(CONFIG_STM32_SDMMC1) || defined(CONFIG_STM32_RNG) /* Highest SYSCLK with USB OTG FS clock <= 48MHz * * PLL_VCO = (25,000,000 / 25) * 432 = 432 MHz @@ -143,7 +143,7 @@ /* Configure factors for PLLSAI clock */ -#define CONFIG_STM32F7_PLLSAI 1 +#define CONFIG_STM32_PLLSAI 1 #define STM32_RCC_PLLSAICFGR_PLLSAIN RCC_PLLSAICFGR_PLLSAIN(BOARD_LTDC_PLLSAIN) #define STM32_RCC_PLLSAICFGR_PLLSAIP RCC_PLLSAICFGR_PLLSAIP(2) #define STM32_RCC_PLLSAICFGR_PLLSAIQ RCC_PLLSAICFGR_PLLSAIQ(2) @@ -152,8 +152,8 @@ /* SAIx input frequency = 25 / M * N / Q / P * 25000000 / 25 * 192 / 2 / 1 */ -#define STM32F7_SAI1_FREQUENCY (49142857) -#define STM32F7_SAI2_FREQUENCY (49142857) +#define STM32_SAI1_FREQUENCY (49142857) +#define STM32_SAI2_FREQUENCY (49142857) /* Configure Dedicated Clock Configuration Register */ @@ -168,7 +168,7 @@ /* Configure factors for PLLI2S clock */ -#define CONFIG_STM32F7_PLLI2S 1 +#define CONFIG_STM32_PLLI2S 1 #define STM32_RCC_PLLI2SCFGR_PLLI2SN RCC_PLLI2SCFGR_PLLI2SN(344) #define STM32_RCC_PLLI2SCFGR_PLLI2SP RCC_PLLI2SCFGR_PLLI2SP(2) #define STM32_RCC_PLLI2SCFGR_PLLI2SQ RCC_PLLI2SCFGR_PLLI2SQ(7) @@ -528,7 +528,7 @@ /* SAI2 pinset */ -#if defined(CONFIG_STM32F7_SAI2) && defined(CONFIG_STM32F7_SAI2_A) +#if defined(CONFIG_STM32_SAI2) && defined(CONFIG_STM32_SAI2_A) # define GPIO_SAI2_SD_A (GPIO_SAI2_SD_A_2|GPIO_SPEED_100MHz) # define GPIO_SAI2_FS_A (GPIO_SAI2_FS_A_2|GPIO_SPEED_100MHz) # define GPIO_SAI2_SCK_A (GPIO_SAI2_SCK_A_2|GPIO_SPEED_100MHz) @@ -579,4 +579,4 @@ #define GPIO_FMC_SDNE0 (GPIO_FMC_SDNE0_3|GPIO_SPEED_100MHz) #define GPIO_FMC_SDNWE (GPIO_FMC_SDNWE_3|GPIO_SPEED_100MHz) -#endif /* __BOARDS_ARM_STM32F7_STM32F746G_DISCO_INCLUDE_BOARD_H */ +#endif /* __BOARDS_ARM_STM32_STM32F746G_DISCO_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32f7/stm32f746g-disco/src/CMakeLists.txt b/boards/arm/stm32f7/stm32f746g-disco/src/CMakeLists.txt index fa3921f051cc2..3b1baaf5cb3d0 100644 --- a/boards/arm/stm32f7/stm32f746g-disco/src/CMakeLists.txt +++ b/boards/arm/stm32f7/stm32f746g-disco/src/CMakeLists.txt @@ -40,11 +40,11 @@ if(CONFIG_SPORADIC_INSTRUMENTATION) list(APPEND SRCS stm32_sporadic.c) endif() -if(CONFIG_STM32F7_LTDC) +if(CONFIG_STM32_LTDC) list(APPEND SRCS stm32_lcd.c) endif() -if(CONFIG_STM32F7_FMC) +if(CONFIG_STM32_FMC) list(APPEND SRCS stm32_extmem.c) endif() @@ -56,13 +56,13 @@ if(CONFIG_MTD_N25QXXX) list(APPEND SRCS stm32_n25q.c) endif() -if(CONFIG_STM32F7_OTGFS) +if(CONFIG_STM32_OTGFS) list(APPEND SRCS stm32_usb.c) -elseif(CONFIG_STM32F7_OTGFSHS) +elseif(CONFIG_STM32_OTGFSHS) list(APPEND SRCS stm32_usb.c) endif() -if(CONFIG_STM32F7_SDMMC) +if(CONFIG_STM32_SDMMC) list(APPEND SRCS stm32_sdmmc.c) endif() diff --git a/boards/arm/stm32f7/stm32f746g-disco/src/Make.defs b/boards/arm/stm32f7/stm32f746g-disco/src/Make.defs index ddc33cdca5ba3..bfa456fb8a532 100644 --- a/boards/arm/stm32f7/stm32f746g-disco/src/Make.defs +++ b/boards/arm/stm32f7/stm32f746g-disco/src/Make.defs @@ -42,11 +42,11 @@ ifeq ($(CONFIG_SPORADIC_INSTRUMENTATION),y) CSRCS += stm32_sporadic.c endif -ifeq ($(CONFIG_STM32F7_LTDC),y) +ifeq ($(CONFIG_STM32_LTDC),y) CSRCS += stm32_lcd.c endif -ifeq ($(CONFIG_STM32F7_FMC),y) +ifeq ($(CONFIG_STM32_FMC),y) CSRCS += stm32_extmem.c endif @@ -58,13 +58,13 @@ ifeq ($(CONFIG_MTD_N25QXXX),y) CSRCS += stm32_n25q.c endif -ifeq ($(CONFIG_STM32F7_OTGFS),y) +ifeq ($(CONFIG_STM32_OTGFS),y) CSRCS += stm32_usb.c -else ifeq ($(CONFIG_STM32F7_OTGFSHS),y) +else ifeq ($(CONFIG_STM32_OTGFSHS),y) CSRCS += stm32_usb.c endif -ifeq ($(CONFIG_STM32F7_SDMMC),y) +ifeq ($(CONFIG_STM32_SDMMC),y) CSRCS += stm32_sdmmc.c endif diff --git a/boards/arm/stm32f7/stm32f746g-disco/src/stm32_adc.c b/boards/arm/stm32f7/stm32f746g-disco/src/stm32_adc.c index db7cfae782795..374703bb0cb60 100644 --- a/boards/arm/stm32f7/stm32f746g-disco/src/stm32_adc.c +++ b/boards/arm/stm32f7/stm32f746g-disco/src/stm32_adc.c @@ -36,11 +36,11 @@ #include "stm32_gpio.h" #include "stm32_adc.h" -#ifndef CONFIG_STM32F7_ADC3 +#ifndef CONFIG_STM32_ADC3 # error "Only ADC3 channels are available on the arduino header of the board" #endif -#if defined(CONFIG_ADC) && defined(CONFIG_STM32F7_ADC3) +#if defined(CONFIG_ADC) && defined(CONFIG_STM32_ADC3) /**************************************************************************** * Pre-processor Definitions @@ -104,7 +104,7 @@ static const uint32_t g_pinlist[6] = int stm32_adc_setup(void) { -#ifdef CONFIG_STM32F7_ADC3 +#ifdef CONFIG_STM32_ADC3 static bool initialized = false; struct adc_dev_s *adc; int ret; @@ -150,4 +150,4 @@ int stm32_adc_setup(void) #endif } -#endif /* (CONFIG_ADC) && (CONFIG_STM32F7_ADC3) */ +#endif /* (CONFIG_ADC) && (CONFIG_STM32_ADC3) */ diff --git a/boards/arm/stm32f7/stm32f746g-disco/src/stm32_boot.c b/boards/arm/stm32f7/stm32f746g-disco/src/stm32_boot.c index 3992542c13fa8..bc89ac56e8c82 100644 --- a/boards/arm/stm32f7/stm32f746g-disco/src/stm32_boot.c +++ b/boards/arm/stm32f7/stm32f746g-disco/src/stm32_boot.c @@ -52,9 +52,9 @@ void stm32_boardinitialize(void) { -#if defined(CONFIG_STM32F7_SPI1) || defined(CONFIG_STM32F7_SPI2) || \ - defined(CONFIG_STM32F7_SPI3) || defined(CONFIG_STM32F7_SPI4) || \ - defined(CONFIG_STM32F7_SPI5) +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || \ + defined(CONFIG_STM32_SPI3) || defined(CONFIG_STM32_SPI4) || \ + defined(CONFIG_STM32_SPI5) /* Configure SPI chip selects if 1) SPI is not disabled, and 2) the weak * function stm32_spidev_initialize() has been brought into the link. @@ -81,13 +81,13 @@ void stm32_boardinitialize(void) board_autoled_initialize(); #endif -#if defined(CONFIG_STM32F7_OTGFS) || defined(CONFIG_STM32F7_HOST) +#if defined(CONFIG_STM32_OTGFS) || defined(CONFIG_STM32_HOST) /* Initialize USB */ stm32_usbinitialize(); #endif -#ifdef CONFIG_STM32F7_FMC +#ifdef CONFIG_STM32_FMC stm32_enablefmc(); #endif } diff --git a/boards/arm/stm32f7/stm32f746g-disco/src/stm32_extmem.c b/boards/arm/stm32f7/stm32f746g-disco/src/stm32_extmem.c index 774f9204fb621..bd6e034d810af 100644 --- a/boards/arm/stm32f7/stm32f746g-disco/src/stm32_extmem.c +++ b/boards/arm/stm32f7/stm32f746g-disco/src/stm32_extmem.c @@ -57,11 +57,11 @@ * Pre-processor Definitions ****************************************************************************/ -#ifndef CONFIG_STM32F7_FMC +#ifndef CONFIG_STM32_FMC # warning "FMC is not enabled" #endif -#if STM32F7_NGPIO < 7 +#if STM32_NGPIO < 7 # error "Required GPIO ports not enabled" #endif diff --git a/boards/arm/stm32f7/stm32f746g-disco/src/stm32_lcd.c b/boards/arm/stm32f7/stm32f746g-disco/src/stm32_lcd.c index cef610f4c3de9..c353723e5d053 100644 --- a/boards/arm/stm32f7/stm32f746g-disco/src/stm32_lcd.c +++ b/boards/arm/stm32f7/stm32f746g-disco/src/stm32_lcd.c @@ -40,7 +40,7 @@ #include "stm32_gpio.h" #include "stm32_ltdc.h" -#ifdef CONFIG_STM32F7_LTDC +#ifdef CONFIG_STM32_LTDC /**************************************************************************** * Public Functions ****************************************************************************/ diff --git a/boards/arm/stm32f7/stm32f746g-disco/src/stm32_n25q.c b/boards/arm/stm32f7/stm32f746g-disco/src/stm32_n25q.c index 6524920c68034..3249fb4ac01cb 100644 --- a/boards/arm/stm32f7/stm32f746g-disco/src/stm32_n25q.c +++ b/boards/arm/stm32f7/stm32f746g-disco/src/stm32_n25q.c @@ -81,7 +81,7 @@ int stm32_n25qxxx_setup(void) struct mtd_dev_s *mtd_dev; int ret = -1; - qspi_dev = stm32f7_qspi_initialize(0); + qspi_dev = stm32_qspi_initialize(0); if (!qspi_dev) { _err("ERROR: Failed to initialize W25 minor %d: %d\n", diff --git a/boards/arm/stm32f7/stm32f746g-disco/src/stm32_spi.c b/boards/arm/stm32f7/stm32f746g-disco/src/stm32_spi.c index 66c889a5c926b..9ebe6730adc12 100644 --- a/boards/arm/stm32f7/stm32f746g-disco/src/stm32_spi.c +++ b/boards/arm/stm32f7/stm32f746g-disco/src/stm32_spi.c @@ -40,9 +40,9 @@ #include "stm32f746g-disco.h" -#if defined(CONFIG_STM32F7_SPI1) || defined(CONFIG_STM32F7_SPI2) || \ - defined(CONFIG_STM32F7_SPI3) || defined(CONFIG_STM32F7_SPI4) || \ - defined(CONFIG_STM32F7_SPI5) +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || \ + defined(CONFIG_STM32_SPI3) || defined(CONFIG_STM32_SPI4) || \ + defined(CONFIG_STM32_SPI5) /**************************************************************************** * Public Functions @@ -87,7 +87,7 @@ void weak_function stm32_spidev_initialize(void) * ****************************************************************************/ -#ifdef CONFIG_STM32F7_SPI1 +#ifdef CONFIG_STM32_SPI1 void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -101,7 +101,7 @@ uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32F7_SPI2 +#ifdef CONFIG_STM32_SPI2 void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -115,7 +115,7 @@ uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32F7_SPI3 +#ifdef CONFIG_STM32_SPI3 void stm32_spi3select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -129,7 +129,7 @@ uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32F7_SPI4 +#ifdef CONFIG_STM32_SPI4 void stm32_spi4select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -143,7 +143,7 @@ uint8_t stm32_spi4status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32F7_SPI5 +#ifdef CONFIG_STM32_SPI5 void stm32_spi5select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -181,35 +181,35 @@ uint8_t stm32_spi5status(struct spi_dev_s *dev, uint32_t devid) ****************************************************************************/ #ifdef CONFIG_SPI_CMDDATA -#ifdef CONFIG_STM32F7_SPI1 +#ifdef CONFIG_STM32_SPI1 int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32F7_SPI2 +#ifdef CONFIG_STM32_SPI2 int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32F7_SPI3 +#ifdef CONFIG_STM32_SPI3 int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32F7_SPI4 +#ifdef CONFIG_STM32_SPI4 int stm32_spi4cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32F7_SPI5 +#ifdef CONFIG_STM32_SPI5 int stm32_spi5cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; @@ -217,4 +217,4 @@ int stm32_spi5cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) #endif #endif /* CONFIG_SPI_CMDDATA */ -#endif /* CONFIG_STM32F7_SPI1 || ... CONFIG_STM32F7_SPI5 */ +#endif /* CONFIG_STM32_SPI1 || ... CONFIG_STM32_SPI5 */ diff --git a/boards/arm/stm32f7/stm32f746g-disco/src/stm32_touchscreen.c b/boards/arm/stm32f7/stm32f746g-disco/src/stm32_touchscreen.c index cb7c130d8cb02..627dd0b399a28 100644 --- a/boards/arm/stm32f7/stm32f746g-disco/src/stm32_touchscreen.c +++ b/boards/arm/stm32f7/stm32f746g-disco/src/stm32_touchscreen.c @@ -48,8 +48,8 @@ # error "FT5x06 support requires CONFIG_INPUT" #endif -#ifndef CONFIG_STM32F7_I2C3 -# error "FT5x06 support requires CONFIG_STM32F7_I2C3" +#ifndef CONFIG_STM32_I2C3 +# error "FT5x06 support requires CONFIG_STM32_I2C3" #endif #ifndef CONFIG_FT5X06_I2CDEV diff --git a/boards/arm/stm32f7/stm32f746g-disco/src/stm32_usb.c b/boards/arm/stm32f7/stm32f746g-disco/src/stm32_usb.c index 8d556b459eca1..7df40f874e304 100644 --- a/boards/arm/stm32f7/stm32f746g-disco/src/stm32_usb.c +++ b/boards/arm/stm32f7/stm32f746g-disco/src/stm32_usb.c @@ -46,7 +46,7 @@ #include "stm32_gpio.h" #include "stm32f746g-disco.h" -#ifdef CONFIG_STM32F7_OTGFS +#ifdef CONFIG_STM32_OTGFS /**************************************************************************** * Pre-processor Definitions @@ -55,7 +55,7 @@ #if defined(CONFIG_USBDEV) || defined(CONFIG_USBHOST) # define HAVE_USB 1 #else -# warning "CONFIG_STM32F7_OTGFS is enabled but neither CONFIG_USBDEV nor CONFIG_USBHOST" +# warning "CONFIG_STM32_OTGFS is enabled but neither CONFIG_USBDEV nor CONFIG_USBHOST" # undef HAVE_USB #endif @@ -139,7 +139,7 @@ void stm32_usbinitialize(void) * Power On, and Overcurrent GPIOs */ -#ifdef CONFIG_STM32F7_OTGFS +#ifdef CONFIG_STM32_OTGFS stm32_configgpio(GPIO_OTGFS_VBUS); #ifdef CONFIG_USBHOST @@ -334,4 +334,4 @@ void stm32_usbsuspend(struct usbdev_s *dev, bool resume) } #endif -#endif /* CONFIG_STM32F7_OTGFS */ +#endif /* CONFIG_STM32_OTGFS */ diff --git a/boards/arm/stm32f7/stm32f746g-disco/src/stm32f746g-disco.h b/boards/arm/stm32f7/stm32f746g-disco/src/stm32f746g-disco.h index 1bbf837dd78a3..cd5d5c18e06f6 100644 --- a/boards/arm/stm32f7/stm32f746g-disco/src/stm32f746g-disco.h +++ b/boards/arm/stm32f7/stm32f746g-disco/src/stm32f746g-disco.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32F7_STM32F746G_DISCO_SRC_STM32F746G_DISCO_H -#define __BOARDS_ARM_STM32F7_STM32F746G_DISCO_SRC_STM32F746G_DISCO_H +#ifndef __BOARDS_ARM_STM32_STM32F746G_DISCO_SRC_STM32F746G_DISCO_H +#define __BOARDS_ARM_STM32_STM32F746G_DISCO_SRC_STM32F746G_DISCO_H /**************************************************************************** * Included Files @@ -43,7 +43,7 @@ /* Can't support USB host or device features if USB OTG FS is not enabled */ -#ifndef CONFIG_STM32F7_OTGFS +#ifndef CONFIG_STM32_OTGFS # undef HAVE_USBDEV # undef HAVE_USBHOST #endif @@ -84,7 +84,7 @@ # endif #endif -#ifdef CONFIG_STM32F7_SDMMC +#ifdef CONFIG_STM32_SDMMC #define HAVE_SDIO #else #undef HAVE_SDIO @@ -212,7 +212,7 @@ void arch_sporadic_initialize(void); * ****************************************************************************/ -#ifdef CONFIG_STM32F7_FMC +#ifdef CONFIG_STM32_FMC void stm32_enablefmc(void); #endif @@ -224,7 +224,7 @@ void stm32_enablefmc(void); * ****************************************************************************/ -#ifdef CONFIG_STM32F7_FMC +#ifdef CONFIG_STM32_FMC void stm32_disablefmc(void); #endif @@ -263,4 +263,4 @@ int stm32_wm8994_initialize(int minor); #endif /* __ASSEMBLY__ */ -#endif /* __BOARDS_ARM_STM32F7_STM32F746G_DISCO_SRC_STM32F746G_DISCO_H */ +#endif /* __BOARDS_ARM_STM32_STM32F746G_DISCO_SRC_STM32F746G_DISCO_H */ diff --git a/boards/arm/stm32f7/stm32f769i-disco/configs/netnsh/defconfig b/boards/arm/stm32f7/stm32f769i-disco/configs/netnsh/defconfig index 74e1fa7b56801..a6feb52f19f0f 100644 --- a/boards/arm/stm32f7/stm32f769i-disco/configs/netnsh/defconfig +++ b/boards/arm/stm32f7/stm32f769i-disco/configs/netnsh/defconfig @@ -11,6 +11,7 @@ CONFIG_ARCH_BOARD="stm32f769i-disco" CONFIG_ARCH_BOARD_STM32F769I_DISCO=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32f7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F769NI=y CONFIG_ARCH_CHIP_STM32F7=y CONFIG_ARCH_STACKDUMP=y @@ -57,25 +58,25 @@ CONFIG_SCHED_LPWORK=y CONFIG_SCHED_WAITPID=y CONFIG_SPI=y CONFIG_START_DAY=14 -CONFIG_STM32F7_BKPSRAM=y -CONFIG_STM32F7_CEC=y -CONFIG_STM32F7_DMA1=y -CONFIG_STM32F7_DMA2=y -CONFIG_STM32F7_ETHMAC=y -CONFIG_STM32F7_I2C4=y -CONFIG_STM32F7_PHYADDR=0 -CONFIG_STM32F7_PHYSR=31 -CONFIG_STM32F7_PHYSR_100FD=0x18 -CONFIG_STM32F7_PHYSR_100HD=0x8 -CONFIG_STM32F7_PHYSR_10FD=0x14 -CONFIG_STM32F7_PHYSR_10HD=0x4 -CONFIG_STM32F7_PHYSR_ALTCONFIG=y -CONFIG_STM32F7_PHYSR_ALTMODE=0x1C -CONFIG_STM32F7_RNG=y -CONFIG_STM32F7_SDMMC2=y -CONFIG_STM32F7_SDMMC_DMA=y -CONFIG_STM32F7_USART1=y -CONFIG_STM32F7_USART6=y +CONFIG_STM32_BKPSRAM=y +CONFIG_STM32_CEC=y +CONFIG_STM32_DMA1=y +CONFIG_STM32_DMA2=y +CONFIG_STM32_ETHMAC=y +CONFIG_STM32_I2C4=y +CONFIG_STM32_PHYADDR=0 +CONFIG_STM32_PHYSR=31 +CONFIG_STM32_PHYSR_100FD=0x18 +CONFIG_STM32_PHYSR_100HD=0x8 +CONFIG_STM32_PHYSR_10FD=0x14 +CONFIG_STM32_PHYSR_10HD=0x4 +CONFIG_STM32_PHYSR_ALTCONFIG=y +CONFIG_STM32_PHYSR_ALTMODE=0x1C +CONFIG_STM32_RNG=y +CONFIG_STM32_SDMMC2=y +CONFIG_STM32_SDMMC_DMA=y +CONFIG_STM32_USART1=y +CONFIG_STM32_USART6=y CONFIG_SYSTEM_DHCPC_RENEW=y CONFIG_SYSTEM_NSH=y CONFIG_SYSTEM_PING=y diff --git a/boards/arm/stm32f7/stm32f769i-disco/configs/nsh/defconfig b/boards/arm/stm32f7/stm32f769i-disco/configs/nsh/defconfig index 0f40ae305257a..df8d9cd8a8431 100644 --- a/boards/arm/stm32f7/stm32f769i-disco/configs/nsh/defconfig +++ b/boards/arm/stm32f7/stm32f769i-disco/configs/nsh/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH_BOARD="stm32f769i-disco" CONFIG_ARCH_BOARD_STM32F769I_DISCO=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32f7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F769NI=y CONFIG_ARCH_CHIP_STM32F7=y CONFIG_ARCH_STACKDUMP=y @@ -38,7 +39,7 @@ CONFIG_RR_INTERVAL=200 CONFIG_SCHED_WAITPID=y CONFIG_SPI=y CONFIG_START_DAY=14 -CONFIG_STM32F7_USART1=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f7/stm32f769i-disco/include/board.h b/boards/arm/stm32f7/stm32f769i-disco/include/board.h index 028b29b002318..21f6d2ffc77ed 100644 --- a/boards/arm/stm32f7/stm32f769i-disco/include/board.h +++ b/boards/arm/stm32f7/stm32f769i-disco/include/board.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32F7_STM32F769I_DISCO_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32F7_STM32F769I_DISCO_INCLUDE_BOARD_H +#ifndef __BOARDS_ARM_STM32_STM32F769I_DISCO_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32_STM32F769I_DISCO_INCLUDE_BOARD_H /**************************************************************************** * Included Files @@ -88,7 +88,7 @@ * 2 <= PLLQ <= 15 */ -#if defined(CONFIG_STM32F7_OTGFS) +#if defined(CONFIG_STM32_OTGFS) /* USB OTG FS clock (= SDMMCCLK = RNGCLK) must be 48 MHz * * PLL_VCO = (25,000,000 / 25) * 384 = 384 MHz @@ -107,7 +107,7 @@ #define STM32_SYSCLK_FREQUENCY (STM32_VCO_FREQUENCY / 2) #define STM32_OTGFS_FREQUENCY (STM32_VCO_FREQUENCY / 8) -#elif defined(CONFIG_STM32F7_SDMMC1) || defined(CONFIG_STM32F7_SDMMC2) || defined(CONFIG_STM32F7_RNG) +#elif defined(CONFIG_STM32_SDMMC1) || defined(CONFIG_STM32_SDMMC2) || defined(CONFIG_STM32_RNG) /* SDMMCCLK (= USB OTG FS clock = RNGCLK) should be <= 48MHz * * PLL_VCO = (25,000,000 / 25) * 432 = 432 MHz @@ -483,4 +483,4 @@ #define GPIO_SDMMC2_D2 (GPIO_SDMMC2_D2_1|GPIO_SPEED_50MHz) #define GPIO_SDMMC2_D3 (GPIO_SDMMC2_D3_1|GPIO_SPEED_50MHz) -#endif /* __BOARDS_ARM_STM32F7_STM32F769I_DISCO_INCLUDE_BOARD_H */ +#endif /* __BOARDS_ARM_STM32_STM32F769I_DISCO_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32f7/stm32f769i-disco/src/CMakeLists.txt b/boards/arm/stm32f7/stm32f769i-disco/src/CMakeLists.txt index b41627ab51855..1c726649844fe 100644 --- a/boards/arm/stm32f7/stm32f769i-disco/src/CMakeLists.txt +++ b/boards/arm/stm32f7/stm32f769i-disco/src/CMakeLists.txt @@ -40,7 +40,7 @@ if(CONFIG_SPORADIC_INSTRUMENTATION) list(APPEND SRCS stm32_sporadic.c) endif() -if(CONFIG_STM32F7_FMC) +if(CONFIG_STM32_FMC) list(APPEND SRCS stm32_extmem.c) endif() diff --git a/boards/arm/stm32f7/stm32f769i-disco/src/Make.defs b/boards/arm/stm32f7/stm32f769i-disco/src/Make.defs index 82a79440d22a7..dacf581a7a28c 100644 --- a/boards/arm/stm32f7/stm32f769i-disco/src/Make.defs +++ b/boards/arm/stm32f7/stm32f769i-disco/src/Make.defs @@ -42,7 +42,7 @@ ifeq ($(CONFIG_SPORADIC_INSTRUMENTATION),y) CSRCS += stm32_sporadic.c endif -ifeq ($(CONFIG_STM32F7_FMC),y) +ifeq ($(CONFIG_STM32_FMC),y) CSRCS += stm32_extmem.c endif diff --git a/boards/arm/stm32f7/stm32f769i-disco/src/stm32_boot.c b/boards/arm/stm32f7/stm32f769i-disco/src/stm32_boot.c index 1ba49ec977e8e..42880e2706db7 100644 --- a/boards/arm/stm32f7/stm32f769i-disco/src/stm32_boot.c +++ b/boards/arm/stm32f7/stm32f769i-disco/src/stm32_boot.c @@ -59,9 +59,9 @@ void stm32_boardinitialize(void) { -#if defined(CONFIG_STM32F7_SPI1) || defined(CONFIG_STM32F7_SPI2) || \ - defined(CONFIG_STM32F7_SPI3) || defined(CONFIG_STM32F7_SPI4) || \ - defined(CONFIG_STM32F7_SPI5) +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || \ + defined(CONFIG_STM32_SPI3) || defined(CONFIG_STM32_SPI4) || \ + defined(CONFIG_STM32_SPI5) /* Configure SPI chip selects if 1) SPI is not disabled, and 2) the weak * function stm32_spidev_initialize() has been brought into the link. */ @@ -87,7 +87,7 @@ void stm32_boardinitialize(void) board_autoled_initialize(); #endif -#ifdef CONFIG_STM32F7_FMC +#ifdef CONFIG_STM32_FMC stm32_sdram_initialize(); #endif } diff --git a/boards/arm/stm32f7/stm32f769i-disco/src/stm32_extmem.c b/boards/arm/stm32f7/stm32f769i-disco/src/stm32_extmem.c index 26ee7b72fd32f..a74c94d43f002 100644 --- a/boards/arm/stm32f7/stm32f769i-disco/src/stm32_extmem.c +++ b/boards/arm/stm32f7/stm32f769i-disco/src/stm32_extmem.c @@ -43,11 +43,11 @@ * Pre-processor Definitions ****************************************************************************/ -#ifndef CONFIG_STM32F7_FMC +#ifndef CONFIG_STM32_FMC # warning "FMC is not enabled" #endif -#if STM32F7_NGPIO < 8 +#if STM32_NGPIO < 8 # error "Required GPIO ports not enabled" #endif diff --git a/boards/arm/stm32f7/stm32f769i-disco/src/stm32_spi.c b/boards/arm/stm32f7/stm32f769i-disco/src/stm32_spi.c index 4f36938bb58b0..ef0f7aef17db7 100644 --- a/boards/arm/stm32f7/stm32f769i-disco/src/stm32_spi.c +++ b/boards/arm/stm32f7/stm32f769i-disco/src/stm32_spi.c @@ -40,9 +40,9 @@ #include "stm32f769i-disco.h" -#if defined(CONFIG_STM32F7_SPI1) || defined(CONFIG_STM32F7_SPI2) || \ - defined(CONFIG_STM32F7_SPI3) || defined(CONFIG_STM32F7_SPI4) || \ - defined(CONFIG_STM32F7_SPI5) +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || \ + defined(CONFIG_STM32_SPI3) || defined(CONFIG_STM32_SPI4) || \ + defined(CONFIG_STM32_SPI5) /**************************************************************************** * Public Functions @@ -87,7 +87,7 @@ void weak_function stm32_spidev_initialize(void) * ****************************************************************************/ -#ifdef CONFIG_STM32F7_SPI1 +#ifdef CONFIG_STM32_SPI1 void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -101,7 +101,7 @@ uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32F7_SPI2 +#ifdef CONFIG_STM32_SPI2 void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -115,7 +115,7 @@ uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32F7_SPI3 +#ifdef CONFIG_STM32_SPI3 void stm32_spi3select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -129,7 +129,7 @@ uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32F7_SPI4 +#ifdef CONFIG_STM32_SPI4 void stm32_spi4select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -143,7 +143,7 @@ uint8_t stm32_spi4status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32F7_SPI5 +#ifdef CONFIG_STM32_SPI5 void stm32_spi5select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -181,35 +181,35 @@ uint8_t stm32_spi5status(struct spi_dev_s *dev, uint32_t devid) ****************************************************************************/ #ifdef CONFIG_SPI_CMDDATA -#ifdef CONFIG_STM32F7_SPI1 +#ifdef CONFIG_STM32_SPI1 int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32F7_SPI2 +#ifdef CONFIG_STM32_SPI2 int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32F7_SPI3 +#ifdef CONFIG_STM32_SPI3 int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32F7_SPI4 +#ifdef CONFIG_STM32_SPI4 int stm32_spi4cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32F7_SPI5 +#ifdef CONFIG_STM32_SPI5 int stm32_spi5cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; @@ -217,4 +217,4 @@ int stm32_spi5cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) #endif #endif /* CONFIG_SPI_CMDDATA */ -#endif /* CONFIG_STM32F7_SPI1 || ... CONFIG_STM32F7_SPI5 */ +#endif /* CONFIG_STM32_SPI1 || ... CONFIG_STM32_SPI5 */ diff --git a/boards/arm/stm32f7/stm32f769i-disco/src/stm32f769i-disco.h b/boards/arm/stm32f7/stm32f769i-disco/src/stm32f769i-disco.h index 5c2ad841e97c2..36111aa9f74dd 100644 --- a/boards/arm/stm32f7/stm32f769i-disco/src/stm32f769i-disco.h +++ b/boards/arm/stm32f7/stm32f769i-disco/src/stm32f769i-disco.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32F7_STM32F769I_DISCO_SRC_STM32F769I_DISCO_H -#define __BOARDS_ARM_STM32F7_STM32F769I_DISCO_SRC_STM32F769I_DISCO_H +#ifndef __BOARDS_ARM_STM32_STM32F769I_DISCO_SRC_STM32F769I_DISCO_H +#define __BOARDS_ARM_STM32_STM32F769I_DISCO_SRC_STM32F769I_DISCO_H /**************************************************************************** * Included Files @@ -158,9 +158,9 @@ void arch_sporadic_initialize(void); * ****************************************************************************/ -#ifdef CONFIG_STM32F7_FMC +#ifdef CONFIG_STM32_FMC void stm32_sdram_initialize(void); #endif #endif /* __ASSEMBLY__ */ -#endif /* __BOARDS_ARM_STM32F7_STM32F769I_DISCO_SRC_STM32F769I_DISCO_H */ +#endif /* __BOARDS_ARM_STM32_STM32F769I_DISCO_SRC_STM32F769I_DISCO_H */ diff --git a/boards/arm/stm32f7/stm32f777zit6-meadow/configs/dualcdcacm/defconfig b/boards/arm/stm32f7/stm32f777zit6-meadow/configs/dualcdcacm/defconfig index cf9cf1cb87d21..104b3eec356d3 100644 --- a/boards/arm/stm32f7/stm32f777zit6-meadow/configs/dualcdcacm/defconfig +++ b/boards/arm/stm32f7/stm32f777zit6-meadow/configs/dualcdcacm/defconfig @@ -10,6 +10,7 @@ CONFIG_ARCH_BOARD="stm32f777zit6-meadow" CONFIG_ARCH_BOARD_COMMON=y CONFIG_ARCH_BOARD_MEADOW_F7MICRO=y CONFIG_ARCH_CHIP="stm32f7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F777ZI=y CONFIG_ARCH_CHIP_STM32F7=y CONFIG_ARCH_STACKDUMP=y @@ -45,8 +46,8 @@ CONFIG_RR_INTERVAL=200 CONFIG_SCHED_WAITPID=y CONFIG_SPI=y CONFIG_START_DAY=14 -CONFIG_STM32F7_OTGFS=y -CONFIG_STM32F7_USART1=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_COMPOSITE=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 diff --git a/boards/arm/stm32f7/stm32f777zit6-meadow/configs/f7corecomp/defconfig b/boards/arm/stm32f7/stm32f777zit6-meadow/configs/f7corecomp/defconfig index 0361ac3973f4a..5be0771023dcc 100644 --- a/boards/arm/stm32f7/stm32f777zit6-meadow/configs/f7corecomp/defconfig +++ b/boards/arm/stm32f7/stm32f777zit6-meadow/configs/f7corecomp/defconfig @@ -11,6 +11,7 @@ CONFIG_ARCH_BOARD="stm32f777zit6-meadow" CONFIG_ARCH_BOARD_COMMON=y CONFIG_ARCH_BOARD_MEADOW_F7MICRO=y CONFIG_ARCH_CHIP="stm32f7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F777ZI=y CONFIG_ARCH_CHIP_STM32F7=y CONFIG_ARCH_STACKDUMP=y @@ -62,14 +63,14 @@ CONFIG_SCHED_WAITPID=y CONFIG_SDMMC2_SDIO_MODE=y CONFIG_SPI=y CONFIG_START_DAY=14 -CONFIG_STM32F7_DMA1=y -CONFIG_STM32F7_DMA2=y -CONFIG_STM32F7_OTGFS=y -CONFIG_STM32F7_QSPI_POLLING=y -CONFIG_STM32F7_QUADSPI=y -CONFIG_STM32F7_SDMMC2=y -CONFIG_STM32F7_SDMMC_DMA=y -CONFIG_STM32F7_USART1=y +CONFIG_STM32_DMA1=y +CONFIG_STM32_DMA2=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_QSPI=y +CONFIG_STM32_QSPI_POLLING=y +CONFIG_STM32_SDMMC2=y +CONFIG_STM32_SDMMC_DMA=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_FLASH_ERASEALL=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=64 diff --git a/boards/arm/stm32f7/stm32f777zit6-meadow/configs/i2s/defconfig b/boards/arm/stm32f7/stm32f777zit6-meadow/configs/i2s/defconfig index 2a5630c8763f9..62cd75915ad6a 100644 --- a/boards/arm/stm32f7/stm32f777zit6-meadow/configs/i2s/defconfig +++ b/boards/arm/stm32f7/stm32f777zit6-meadow/configs/i2s/defconfig @@ -10,6 +10,7 @@ CONFIG_ARCH_BOARD="stm32f777zit6-meadow" CONFIG_ARCH_BOARD_COMMON=y CONFIG_ARCH_BOARD_MEADOW_F7MICRO=y CONFIG_ARCH_CHIP="stm32f7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F777ZI=y CONFIG_ARCH_CHIP_STM32F7=y CONFIG_ARCH_STACKDUMP=y @@ -88,14 +89,14 @@ CONFIG_SCHED_HPWORK=y CONFIG_SCHED_WAITPID=y CONFIG_SPI=y CONFIG_START_DAY=14 -CONFIG_STM32F7_DMA1=y -CONFIG_STM32F7_I2S2=y -CONFIG_STM32F7_I2S2_MCK=y -CONFIG_STM32F7_I2S2_TX=y -CONFIG_STM32F7_OTGFS=y -CONFIG_STM32F7_QSPI_POLLING=y -CONFIG_STM32F7_QUADSPI=y -CONFIG_STM32F7_USART1=y +CONFIG_STM32_DMA1=y +CONFIG_STM32_I2S2=y +CONFIG_STM32_I2S2_MCK=y +CONFIG_STM32_I2S2_TX=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_QSPI=y +CONFIG_STM32_QSPI_POLLING=y +CONFIG_STM32_USART1=y CONFIG_SYSLOG_DEFAULT=y CONFIG_SYSLOG_DEVPATH="/dev/ttyS1" CONFIG_SYSLOG_MAX_CHANNELS=2 diff --git a/boards/arm/stm32f7/stm32f777zit6-meadow/configs/meadow_os/defconfig b/boards/arm/stm32f7/stm32f777zit6-meadow/configs/meadow_os/defconfig index 8f9a71be40497..b5f1c6d5b171f 100644 --- a/boards/arm/stm32f7/stm32f777zit6-meadow/configs/meadow_os/defconfig +++ b/boards/arm/stm32f7/stm32f777zit6-meadow/configs/meadow_os/defconfig @@ -10,6 +10,7 @@ CONFIG_ARCH_BOARD="stm32f777zit6-meadow" CONFIG_ARCH_BOARD_COMMON=y CONFIG_ARCH_BOARD_MEADOW_F7MICRO=y CONFIG_ARCH_CHIP="stm32f7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F777ZI=y CONFIG_ARCH_CHIP_STM32F7=y CONFIG_ARCH_STACKDUMP=y @@ -48,8 +49,8 @@ CONFIG_RAW_BINARY=y CONFIG_RR_INTERVAL=200 CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=14 -CONFIG_STM32F7_OTGFS=y -CONFIG_STM32F7_USART1=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=64 CONFIG_USBDEV=y diff --git a/boards/arm/stm32f7/stm32f777zit6-meadow/configs/nsh/defconfig b/boards/arm/stm32f7/stm32f777zit6-meadow/configs/nsh/defconfig index b63aa4ec89f9b..290478e8ab3bd 100644 --- a/boards/arm/stm32f7/stm32f777zit6-meadow/configs/nsh/defconfig +++ b/boards/arm/stm32f7/stm32f777zit6-meadow/configs/nsh/defconfig @@ -10,6 +10,7 @@ CONFIG_ARCH_BOARD="stm32f777zit6-meadow" CONFIG_ARCH_BOARD_COMMON=y CONFIG_ARCH_BOARD_MEADOW_F7MICRO=y CONFIG_ARCH_CHIP="stm32f7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F777ZI=y CONFIG_ARCH_CHIP_STM32F7=y CONFIG_ARCH_STACKDUMP=y @@ -36,7 +37,7 @@ CONFIG_RR_INTERVAL=200 CONFIG_SCHED_WAITPID=y CONFIG_SPI=y CONFIG_START_DAY=14 -CONFIG_STM32F7_USART1=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f7/stm32f777zit6-meadow/configs/projectlab/defconfig b/boards/arm/stm32f7/stm32f777zit6-meadow/configs/projectlab/defconfig index e4d37559d9d58..70331b5896eb2 100644 --- a/boards/arm/stm32f7/stm32f777zit6-meadow/configs/projectlab/defconfig +++ b/boards/arm/stm32f7/stm32f777zit6-meadow/configs/projectlab/defconfig @@ -10,6 +10,7 @@ CONFIG_ARCH_BOARD="stm32f777zit6-meadow" CONFIG_ARCH_BOARD_COMMON=y CONFIG_ARCH_BOARD_MEADOW_F7MICRO=y CONFIG_ARCH_CHIP="stm32f7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F777ZI=y CONFIG_ARCH_CHIP_STM32F7=y CONFIG_ARCH_STACKDUMP=y @@ -64,10 +65,10 @@ CONFIG_SENSORS_BMI270=y CONFIG_SENSORS_BMI270_I2C=y CONFIG_SPI=y CONFIG_START_DAY=14 -CONFIG_STM32F7_I2C1=y -CONFIG_STM32F7_OTGFS=y -CONFIG_STM32F7_QUADSPI=y -CONFIG_STM32F7_USART1=y +CONFIG_STM32_I2C1=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_QSPI=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_FLASH_ERASEALL=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=64 diff --git a/boards/arm/stm32f7/stm32f777zit6-meadow/configs/sdram/defconfig b/boards/arm/stm32f7/stm32f777zit6-meadow/configs/sdram/defconfig index 26e856613c856..aac213c9285b0 100644 --- a/boards/arm/stm32f7/stm32f777zit6-meadow/configs/sdram/defconfig +++ b/boards/arm/stm32f7/stm32f777zit6-meadow/configs/sdram/defconfig @@ -10,6 +10,7 @@ CONFIG_ARCH_BOARD="stm32f777zit6-meadow" CONFIG_ARCH_BOARD_COMMON=y CONFIG_ARCH_BOARD_MEADOW_F7MICRO=y CONFIG_ARCH_CHIP="stm32f7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F777ZI=y CONFIG_ARCH_CHIP_STM32F7=y CONFIG_ARCH_STACKDUMP=y @@ -38,9 +39,9 @@ CONFIG_RR_INTERVAL=200 CONFIG_SCHED_WAITPID=y CONFIG_SPI=y CONFIG_START_DAY=14 -CONFIG_STM32F7_EXTERNAL_RAM=y -CONFIG_STM32F7_FMC=y -CONFIG_STM32F7_USART1=y +CONFIG_STM32_EXTERNAL_RAM=y +CONFIG_STM32_FMC=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_TESTING_RAMTEST=y diff --git a/boards/arm/stm32f7/stm32f777zit6-meadow/configs/usbnsh/defconfig b/boards/arm/stm32f7/stm32f777zit6-meadow/configs/usbnsh/defconfig index 6fb257d819b01..e06beff8f4caa 100644 --- a/boards/arm/stm32f7/stm32f777zit6-meadow/configs/usbnsh/defconfig +++ b/boards/arm/stm32f7/stm32f777zit6-meadow/configs/usbnsh/defconfig @@ -10,6 +10,7 @@ CONFIG_ARCH_BOARD="stm32f777zit6-meadow" CONFIG_ARCH_BOARD_COMMON=y CONFIG_ARCH_BOARD_MEADOW_F7MICRO=y CONFIG_ARCH_CHIP="stm32f7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F777ZI=y CONFIG_ARCH_CHIP_STM32F7=y CONFIG_ARCH_STACKDUMP=y @@ -54,9 +55,9 @@ CONFIG_RR_INTERVAL=200 CONFIG_SCHED_WAITPID=y CONFIG_SPI=y CONFIG_START_DAY=14 -CONFIG_STM32F7_OTGFS=y -CONFIG_STM32F7_QUADSPI=y -CONFIG_STM32F7_USART1=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_QSPI=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_FLASH_ERASEALL=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=64 diff --git a/boards/arm/stm32f7/stm32f777zit6-meadow/include/board.h b/boards/arm/stm32f7/stm32f777zit6-meadow/include/board.h index 9f5fb71fe13a2..fd495d6838f09 100644 --- a/boards/arm/stm32f7/stm32f777zit6-meadow/include/board.h +++ b/boards/arm/stm32f7/stm32f777zit6-meadow/include/board.h @@ -88,7 +88,7 @@ * 2 <= PLLQ <= 15 */ -#if defined(CONFIG_STM32F7_OTGFS) +#if defined(CONFIG_STM32_OTGFS) /* USB OTG FS clock (= SDMMCCLK = RNGCLK) must be 48 MHz * * PLL_VCO = (25,000,000 / 25) * 384 = 384 MHz @@ -107,7 +107,7 @@ #define STM32_SYSCLK_FREQUENCY (STM32_VCO_FREQUENCY / 2) #define STM32_OTGFS_FREQUENCY (STM32_VCO_FREQUENCY / 8) -#elif defined(CONFIG_STM32F7_SDMMC1) || defined(CONFIG_STM32F7_SDMMC2) || defined(CONFIG_STM32F7_RNG) +#elif defined(CONFIG_STM32_SDMMC1) || defined(CONFIG_STM32_SDMMC2) || defined(CONFIG_STM32_RNG) /* SDMMCCLK (= USB OTG FS clock = RNGCLK) should be <= 48MHz * * PLL_VCO = (25,000,000 / 25) * 432 = 432 MHz @@ -148,7 +148,7 @@ /* Configure factors for PLLSAI clock */ -#define CONFIG_STM32F7_PLLSAI 1 +#define CONFIG_STM32_PLLSAI 1 #define STM32_RCC_PLLSAICFGR_PLLSAIN RCC_PLLSAICFGR_PLLSAIN(384) #define STM32_RCC_PLLSAICFGR_PLLSAIP RCC_PLLSAICFGR_PLLSAIP(8) #define STM32_RCC_PLLSAICFGR_PLLSAIQ RCC_PLLSAICFGR_PLLSAIQ(2) @@ -158,8 +158,8 @@ * 25000000 / 25 * 384 / 2 / 8 */ -#define STM32F7_SAI1_FREQUENCY (49142857) -#define STM32F7_SAI2_FREQUENCY (49142857) +#define STM32_SAI1_FREQUENCY (49142857) +#define STM32_SAI2_FREQUENCY (49142857) /* Configure Dedicated Clock Configuration Register */ @@ -174,7 +174,7 @@ /* Configure factors for PLLI2S clock */ -#define CONFIG_STM32F7_PLLI2S 1 +#define CONFIG_STM32_PLLI2S 1 #define STM32_RCC_PLLI2SCFGR_PLLI2SN RCC_PLLI2SCFGR_PLLI2SN(192) #define STM32_RCC_PLLI2SCFGR_PLLI2SP RCC_PLLI2SCFGR_PLLI2SP(4) #define STM32_RCC_PLLI2SCFGR_PLLI2SQ RCC_PLLI2SCFGR_PLLI2SQ(4) diff --git a/boards/arm/stm32f7/stm32f777zit6-meadow/src/CMakeLists.txt b/boards/arm/stm32f7/stm32f777zit6-meadow/src/CMakeLists.txt index a22e8a9afed18..a1c6ad74cb798 100644 --- a/boards/arm/stm32f7/stm32f777zit6-meadow/src/CMakeLists.txt +++ b/boards/arm/stm32f7/stm32f777zit6-meadow/src/CMakeLists.txt @@ -44,13 +44,13 @@ if(CONFIG_SPORADIC_INSTRUMENTATION) list(APPEND SRCS stm32_sporadic.c) endif() -if(CONFIG_STM32F7_FMC) +if(CONFIG_STM32_FMC) list(APPEND SRCS stm32_extmem.c) endif() -if(CONFIG_STM32F7_OTGFS) +if(CONFIG_STM32_OTGFS) list(APPEND SRCS stm32_usb.c) -elseif(CONFIG_STM32F7_OTGFSHS) +elseif(CONFIG_STM32_OTGFSHS) list(APPEND SRCS stm32_usb.c) endif() diff --git a/boards/arm/stm32f7/stm32f777zit6-meadow/src/Make.defs b/boards/arm/stm32f7/stm32f777zit6-meadow/src/Make.defs index 8d6ef41b3a6f9..8b662918a3f55 100644 --- a/boards/arm/stm32f7/stm32f777zit6-meadow/src/Make.defs +++ b/boards/arm/stm32f7/stm32f777zit6-meadow/src/Make.defs @@ -47,13 +47,13 @@ ifeq ($(CONFIG_SPORADIC_INSTRUMENTATION),y) CSRCS += stm32_sporadic.c endif -ifeq ($(CONFIG_STM32F7_FMC),y) +ifeq ($(CONFIG_STM32_FMC),y) CSRCS += stm32_extmem.c endif -ifeq ($(CONFIG_STM32F7_OTGFS),y) +ifeq ($(CONFIG_STM32_OTGFS),y) CSRCS += stm32_usb.c -else ifeq ($(CONFIG_STM32F7_OTGFSHS),y) +else ifeq ($(CONFIG_STM32_OTGFSHS),y) CSRCS += stm32_usb.c endif @@ -65,7 +65,7 @@ ifeq ($(CONFIG_ARCH_IDLE_CUSTOM),y) CSRCS += stm32_idle.c endif -ifeq ($(CONFIG_STM32F7_SDMMC2),y) +ifeq ($(CONFIG_STM32_SDMMC2),y) CSRCS += stm32_sdmmc.c endif diff --git a/boards/arm/stm32f7/stm32f777zit6-meadow/src/stm32_boot.c b/boards/arm/stm32f7/stm32f777zit6-meadow/src/stm32_boot.c index fbf4f961fc5b7..bbf5cd536c139 100644 --- a/boards/arm/stm32f7/stm32f777zit6-meadow/src/stm32_boot.c +++ b/boards/arm/stm32f7/stm32f777zit6-meadow/src/stm32_boot.c @@ -36,7 +36,7 @@ #include "stm32f777zit6-meadow.h" -#ifdef CONFIG_STM32F7_QUADSPI +#ifdef CONFIG_STM32_QSPI # include "stm32_qspi.h" # ifdef CONFIG_FS_FAT @@ -46,7 +46,7 @@ /* MEADOW FIXME: header clash? */ -extern struct qspi_dev_s *stm32f7_qspi_initialize(int intf); +extern struct qspi_dev_s *stm32_qspi_initialize(int intf); #endif /**************************************************************************** @@ -74,9 +74,9 @@ extern struct qspi_dev_s *stm32f7_qspi_initialize(int intf); void stm32_boardinitialize(void) { -#if defined(CONFIG_STM32F7_SPI1) || defined(CONFIG_STM32F7_SPI2) || \ - defined(CONFIG_STM32F7_SPI3) || defined(CONFIG_STM32F7_SPI4) || \ - defined(CONFIG_STM32F7_SPI5) +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || \ + defined(CONFIG_STM32_SPI3) || defined(CONFIG_STM32_SPI4) || \ + defined(CONFIG_STM32_SPI5) /* Configure SPI chip selects if 1) SPI is not disabled, and 2) the weak * function stm32_spidev_initialize() has been brought into the link. */ @@ -102,7 +102,7 @@ void stm32_boardinitialize(void) board_autoled_initialize(); #endif -#ifdef CONFIG_STM32F7_FMC +#ifdef CONFIG_STM32_FMC stm32_sdram_initialize(); #endif } @@ -124,7 +124,7 @@ void stm32_boardinitialize(void) #ifdef CONFIG_BOARD_LATE_INITIALIZE void board_late_initialize(void) { -#ifdef CONFIG_STM32F7_QUADSPI +#ifdef CONFIG_STM32_QSPI struct qspi_dev_s *qspi; struct mtd_dev_s *mtd; @@ -132,7 +132,7 @@ void board_late_initialize(void) int ret; - qspi = stm32f7_qspi_initialize(0); + qspi = stm32_qspi_initialize(0); if (!qspi) { syslog(LOG_ERR, "ERROR: sam_qspi_initialize failed\n"); @@ -159,7 +159,7 @@ void board_late_initialize(void) meminfo.buflen = 0; meminfo.buffer = NULL; - stm32f7_qspi_enter_memorymapped(qspi, &meminfo, 80000000); + stm32_qspi_enter_memorymapped(qspi, &meminfo, 80000000); /* FIXME: stm32_mpu_uheap depends on PROTECTED && MPU * diff --git a/boards/arm/stm32f7/stm32f777zit6-meadow/src/stm32_extmem.c b/boards/arm/stm32f7/stm32f777zit6-meadow/src/stm32_extmem.c index a73495f2e0c29..e2a62c396a90c 100644 --- a/boards/arm/stm32f7/stm32f777zit6-meadow/src/stm32_extmem.c +++ b/boards/arm/stm32f7/stm32f777zit6-meadow/src/stm32_extmem.c @@ -43,11 +43,11 @@ * Pre-processor Definitions ****************************************************************************/ -#ifndef CONFIG_STM32F7_FMC +#ifndef CONFIG_STM32_FMC # warning "FMC is not enabled" #endif -#if STM32F7_NGPIO < 6 +#if STM32_NGPIO < 6 # error "Required GPIO ports not enabled" #endif diff --git a/boards/arm/stm32f7/stm32f777zit6-meadow/src/stm32_spi.c b/boards/arm/stm32f7/stm32f777zit6-meadow/src/stm32_spi.c index fec4e8256a6be..0d4fb153ceb02 100644 --- a/boards/arm/stm32f7/stm32f777zit6-meadow/src/stm32_spi.c +++ b/boards/arm/stm32f7/stm32f777zit6-meadow/src/stm32_spi.c @@ -40,9 +40,9 @@ #include "stm32f777zit6-meadow.h" -#if defined(CONFIG_STM32F7_SPI1) || defined(CONFIG_STM32F7_SPI2) || \ - defined(CONFIG_STM32F7_SPI3) || defined(CONFIG_STM32F7_SPI4) || \ - defined(CONFIG_STM32F7_SPI5) +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || \ + defined(CONFIG_STM32_SPI3) || defined(CONFIG_STM32_SPI4) || \ + defined(CONFIG_STM32_SPI5) /**************************************************************************** * Public Functions @@ -87,7 +87,7 @@ void weak_function stm32_spidev_initialize(void) * ****************************************************************************/ -#ifdef CONFIG_STM32F7_SPI1 +#ifdef CONFIG_STM32_SPI1 void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -101,7 +101,7 @@ uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32F7_SPI2 +#ifdef CONFIG_STM32_SPI2 void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -117,7 +117,7 @@ uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32F7_SPI3 +#ifdef CONFIG_STM32_SPI3 void stm32_spi3select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -131,7 +131,7 @@ uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32F7_SPI4 +#ifdef CONFIG_STM32_SPI4 void stm32_spi4select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -145,7 +145,7 @@ uint8_t stm32_spi4status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32F7_SPI5 +#ifdef CONFIG_STM32_SPI5 void stm32_spi5select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -183,35 +183,35 @@ uint8_t stm32_spi5status(struct spi_dev_s *dev, uint32_t devid) ****************************************************************************/ #ifdef CONFIG_SPI_CMDDATA -#ifdef CONFIG_STM32F7_SPI1 +#ifdef CONFIG_STM32_SPI1 int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32F7_SPI2 +#ifdef CONFIG_STM32_SPI2 int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32F7_SPI3 +#ifdef CONFIG_STM32_SPI3 int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32F7_SPI4 +#ifdef CONFIG_STM32_SPI4 int stm32_spi4cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32F7_SPI5 +#ifdef CONFIG_STM32_SPI5 int stm32_spi5cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; @@ -219,4 +219,4 @@ int stm32_spi5cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) #endif #endif /* CONFIG_SPI_CMDDATA */ -#endif /* CONFIG_STM32F7_SPI1 || ... CONFIG_STM32F7_SPI5 */ +#endif /* CONFIG_STM32_SPI1 || ... CONFIG_STM32_SPI5 */ diff --git a/boards/arm/stm32f7/stm32f777zit6-meadow/src/stm32_usb.c b/boards/arm/stm32f7/stm32f777zit6-meadow/src/stm32_usb.c index 49a5b7310f706..be5332f7f44dd 100644 --- a/boards/arm/stm32f7/stm32f777zit6-meadow/src/stm32_usb.c +++ b/boards/arm/stm32f7/stm32f777zit6-meadow/src/stm32_usb.c @@ -46,7 +46,7 @@ #include "stm32_gpio.h" #include "stm32f777zit6-meadow.h" -#ifdef CONFIG_STM32F7_OTGFS +#ifdef CONFIG_STM32_OTGFS /**************************************************************************** * Pre-processor Definitions @@ -55,7 +55,7 @@ #if defined(CONFIG_USBDEV) || defined(CONFIG_USBHOST) # define HAVE_USB 1 #else -# warning "CONFIG_STM32F7_OTGFS is enabled but neither CONFIG_USBDEV nor CONFIG_USBHOST" +# warning "CONFIG_STM32_OTGFS is enabled but neither CONFIG_USBDEV nor CONFIG_USBHOST" # undef HAVE_USB #endif @@ -139,7 +139,7 @@ void stm32_usbinitialize(void) * Power On, and Overcurrent GPIOs */ -#ifdef CONFIG_STM32F7_OTGFS +#ifdef CONFIG_STM32_OTGFS stm32_configgpio(GPIO_OTGFS_VBUS); # ifdef CONFIG_USBHOST stm32_configgpio(GPIO_OTGFS_PWRON); @@ -339,4 +339,4 @@ void stm32_usbsuspend(struct usbdev_s *dev, bool resume) } #endif -#endif /* CONFIG_STM32F7_OTGFS */ +#endif /* CONFIG_STM32_OTGFS */ diff --git a/boards/arm/stm32f7/stm32f777zit6-meadow/src/stm32f777zit6-meadow.h b/boards/arm/stm32f7/stm32f777zit6-meadow/src/stm32f777zit6-meadow.h index 827959faa5766..6fd24bd22f0bb 100644 --- a/boards/arm/stm32f7/stm32f777zit6-meadow/src/stm32f777zit6-meadow.h +++ b/boards/arm/stm32f7/stm32f777zit6-meadow/src/stm32f777zit6-meadow.h @@ -47,7 +47,7 @@ /* SDCard validation */ -#if defined(CONFIG_STM32F7_SDMMC1) || defined(CONFIG_STM32F7_SDMMC2) +#if defined(CONFIG_STM32_SDMMC1) || defined(CONFIG_STM32_SDMMC2) # define HAVE_SDIO #endif @@ -165,7 +165,7 @@ void arch_sporadic_initialize(void); * ****************************************************************************/ -#ifdef CONFIG_STM32F7_FMC +#ifdef CONFIG_STM32_FMC void stm32_sdram_initialize(void); void stm32_disablefmc(void); #endif @@ -178,7 +178,7 @@ void stm32_disablefmc(void); * ****************************************************************************/ -#if !defined(CONFIG_DISABLE_MOUNTPOINT) && defined(CONFIG_STM32F7_SDMMC2) +#if !defined(CONFIG_DISABLE_MOUNTPOINT) && defined(CONFIG_STM32_SDMMC2) int stm32_sdio_initialize(void); #endif diff --git a/boards/arm/stm32g0/common/CMakeLists.txt b/boards/arm/stm32g0/common/CMakeLists.txt new file mode 100644 index 0000000000000..4a04cc45ad2f9 --- /dev/null +++ b/boards/arm/stm32g0/common/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32g0/common/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(${NUTTX_DIR}/boards/arm/common/stm32 stm32_common) diff --git a/boards/arm/stm32g0/common/Kconfig b/boards/arm/stm32g0/common/Kconfig new file mode 100644 index 0000000000000..5c48f62a0258b --- /dev/null +++ b/boards/arm/stm32g0/common/Kconfig @@ -0,0 +1,6 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# + +source "boards/arm/common/stm32/Kconfig" diff --git a/boards/arm/stm32g0/common/Makefile b/boards/arm/stm32g0/common/Makefile new file mode 100644 index 0000000000000..8919a4ba78378 --- /dev/null +++ b/boards/arm/stm32g0/common/Makefile @@ -0,0 +1,39 @@ +############################################################################# +# boards/arm/stm32g0/common/Makefile +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################# + +include $(TOPDIR)/Make.defs + +STM32_BOARD_COMMON_DIR := $(TOPDIR)$(DELIM)boards$(DELIM)arm$(DELIM)common$(DELIM)stm32 +STM32_COMMON_SRCDIR := $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)common$(DELIM)stm32 + +include board/Make.defs +include $(STM32_BOARD_COMMON_DIR)$(DELIM)src$(DELIM)Make.defs + +DEPPATH += --dep-path board + +include $(TOPDIR)/boards/Board.mk + +ARCHSRCDIR = $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src +BOARDDIR = $(ARCHSRCDIR)$(DELIM)board +CFLAGS += ${INCDIR_PREFIX}$(BOARDDIR)$(DELIM)include +CFLAGS += ${INCDIR_PREFIX}$(STM32_COMMON_SRCDIR) +CXXFLAGS += ${INCDIR_PREFIX}$(STM32_COMMON_SRCDIR) diff --git a/boards/arm/stm32g0/nucleo-g070rb/CMakeLists.txt b/boards/arm/stm32g0/nucleo-g070rb/CMakeLists.txt new file mode 100644 index 0000000000000..f505090d81c82 --- /dev/null +++ b/boards/arm/stm32g0/nucleo-g070rb/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32g0/nucleo-g070rb/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/arm/stm32f0l0g0/nucleo-g070rb/Kconfig b/boards/arm/stm32g0/nucleo-g070rb/Kconfig similarity index 100% rename from boards/arm/stm32f0l0g0/nucleo-g070rb/Kconfig rename to boards/arm/stm32g0/nucleo-g070rb/Kconfig diff --git a/boards/arm/stm32g0/nucleo-g070rb/configs/nsh/defconfig b/boards/arm/stm32g0/nucleo-g070rb/configs/nsh/defconfig new file mode 100644 index 0000000000000..f78e5a4b951d6 --- /dev/null +++ b/boards/arm/stm32g0/nucleo-g070rb/configs/nsh/defconfig @@ -0,0 +1,107 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_ARGCAT is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nucleo-g070rb" +CONFIG_ARCH_BOARD_NUCLEO_G070RB=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32g0" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32G070RB=y +CONFIG_ARCH_CHIP_STM32G0=y +CONFIG_ARCH_IRQBUTTONS=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=2796 +CONFIG_BUILTIN=y +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_DEV_GPIO=y +CONFIG_DISABLE_ENVIRON=y +CONFIG_DISABLE_MOUNTPOINT=y +CONFIG_DISABLE_MQUEUE=y +CONFIG_DISABLE_POSIX_TIMERS=y +CONFIG_DISABLE_PSEUDOFS_OPERATIONS=y +CONFIG_EXAMPLES_BUTTONS=y +CONFIG_EXAMPLES_GPIO=y +CONFIG_EXAMPLES_HELLO=y +CONFIG_EXAMPLES_PWM=y +CONFIG_EXAMPLES_TIMER=y +CONFIG_I2C=y +CONFIG_I2CTOOL_MAXADDR=0xff +CONFIG_I2CTOOL_MINADDR=0x00 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=1536 +CONFIG_INPUT=y +CONFIG_INPUT_BUTTONS=y +CONFIG_INPUT_BUTTONS_LOWER=y +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=64 +CONFIG_NSH_READLINE=y +CONFIG_NUNGET_CHARS=0 +CONFIG_POSIX_SPAWN_DEFAULT_STACKSIZE=1536 +CONFIG_PTHREAD_MUTEX_UNSAFE=y +CONFIG_PTHREAD_STACK_DEFAULT=1536 +CONFIG_PWM=y +CONFIG_RAM_SIZE=20480 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=19 +CONFIG_START_MONTH=5 +CONFIG_START_YEAR=2013 +CONFIG_STDIO_DISABLE_BUFFERING=y +CONFIG_STM32_I2C1=y +CONFIG_STM32_PWM_MULTICHAN=y +CONFIG_STM32_PWR=y +CONFIG_STM32_TIM14=y +CONFIG_STM32_TIM14_CH1OUT=y +CONFIG_STM32_TIM14_CHANNEL1=y +CONFIG_STM32_TIM14_PWM=y +CONFIG_STM32_TIM15=y +CONFIG_STM32_TIM15_CH1OUT=y +CONFIG_STM32_TIM15_CHANNEL1=y +CONFIG_STM32_TIM15_PWM=y +CONFIG_STM32_TIM16=y +CONFIG_STM32_TIM16_CH1OUT=y +CONFIG_STM32_TIM16_CHANNEL1=y +CONFIG_STM32_TIM16_PWM=y +CONFIG_STM32_TIM17=y +CONFIG_STM32_TIM17_CH1OUT=y +CONFIG_STM32_TIM17_CHANNEL1=y +CONFIG_STM32_TIM17_PWM=y +CONFIG_STM32_TIM1=y +CONFIG_STM32_TIM1_CH1OUT=y +CONFIG_STM32_TIM1_CH2OUT=y +CONFIG_STM32_TIM1_CH3OUT=y +CONFIG_STM32_TIM1_CH4OUT=y +CONFIG_STM32_TIM1_CHANNEL1=y +CONFIG_STM32_TIM1_CHANNEL2=y +CONFIG_STM32_TIM1_CHANNEL3=y +CONFIG_STM32_TIM1_CHANNEL4=y +CONFIG_STM32_TIM1_PWM=y +CONFIG_STM32_TIM3=y +CONFIG_STM32_TIM3_CH1OUT=y +CONFIG_STM32_TIM3_CH2OUT=y +CONFIG_STM32_TIM3_CH3OUT=y +CONFIG_STM32_TIM3_CH4OUT=y +CONFIG_STM32_TIM3_CHANNEL1=y +CONFIG_STM32_TIM3_CHANNEL2=y +CONFIG_STM32_TIM3_CHANNEL3=y +CONFIG_STM32_TIM3_CHANNEL4=y +CONFIG_STM32_TIM3_PWM=y +CONFIG_STM32_TIM6=y +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_I2CTOOL=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_TIMER=y +CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32g0/nucleo-g070rb/include/board.h b/boards/arm/stm32g0/nucleo-g070rb/include/board.h new file mode 100644 index 0000000000000..2a65558b105d0 --- /dev/null +++ b/boards/arm/stm32g0/nucleo-g070rb/include/board.h @@ -0,0 +1,246 @@ +/**************************************************************************** + * boards/arm/stm32g0/nucleo-g070rb/include/board.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_STM32F0L0G0_NUCLEO_G070RB_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32F0L0G0_NUCLEO_G070RB_INCLUDE_BOARD_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#ifndef __ASSEMBLY__ +# include +# include +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Clocking *****************************************************************/ + +/* HSI - Internal 16 MHz RC Oscillator + * LSI - 32 KHz RC + * HSE - 8 MHz from MCO output of ST-LINK (disabled by default) + * LSE - 32.768 kHz + */ + +#define STM32_BOARD_XTAL 8000000ul /* 8MHz */ + +#define STM32_HSI_FREQUENCY 16000000ul /* 16MHz */ +#define STM32_LSI_FREQUENCY 32000 /* Between 30kHz and 60kHz */ +#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL +#define STM32_LSE_FREQUENCY 32768 /* X2 on board */ + +/* Main PLL Configuration. + * + * PLL_VCO = (PLL_SOURCE_FREQUENCY / PLL_M) * PLL_N + * SYSCLK = PLLCLK = PLLR = PLL_VCO / PLL_DIV_R + * PLLP = PLL_VCO / PLL_DIV_P + * + * Subject to: + * + * PLL_SOURCE_FREQUENCY is one of {STM32_HSE_FREQUENCY, STM32_HSI_FREQUENCY} + * + * 1 <= PLL_DIV_M <= 8 + * 8 <= PLL_DIV_N <= 86 + * 2 <= PLL_DIV_P <= 32 + * 2 <= PLL_DIV_R <= 8 + * 4 MHz <= PLL_SOURCE_FREQUENCY <= 48 MHz + * 96 MHz <= PLL_VCO <= 344MHz + */ + +/* Considering: + * - PLL_SOURCE_FREQUENCY = STM32_HSI_FREQUENCY = 16,000,000 + * - PLL_DIV_M = 1 + * - PLL_DIV_N = 8 + * - PLL_DIV_R = 2 + * - PLL_DIV_P = 2 + * + * PLL_VCO = (16,000,000 / 1) * 8 = 128 MHz + * PLLP = (PLL_VCO / 2) = 64 MHz + * PLLR = (PLL_VCO / 2) = 64 MHz + */ + +#define STM32_PLLCFG_PLLSRC RCC_PLLCFG_PLLSRC_HSI +#define STM32_PLLCFG_PLLCFG (RCC_PLLCFG_PLLPEN | \ + RCC_PLLCFG_PLLREN) + +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(8) +#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP(2) +#define STM32_PLLCFG_PLLR RCC_PLLCFG_PLLR(2) + +#define STM32_VCO_FREQUENCY ((STM32_HSI_FREQUENCY / 1) * 8) +#define STM32_PLLP_FREQUENCY (STM32_VCO_FREQUENCY / 2) +#define STM32_PLLR_FREQUENCY (STM32_VCO_FREQUENCY / 2) + +/* Use the PLL and set the SYSCLK source to be the PLLR (64 MHz) */ + +#define STM32_SYSCLK_SW RCC_CFGR_SW_PLL +#define STM32_SYSCLK_SWS RCC_CFGR_SWS_PLL +#define STM32_SYSCLK_FREQUENCY (STM32_PLLR_FREQUENCY) + +/* AHB clock (HCLK) is SYSCLK (64 MHz) */ + +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY + +/* APB1 clock (PCLK1) is HCLK (64 MHz) */ + +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK +#define STM32_PCLK1_FREQUENCY STM32_HCLK_FREQUENCY + +/* Timer clock frequencies */ + +/* Timers driven from APB1. Frequency = PCLK1 */ + +#define STM32_APB1_TIM3_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (STM32_PCLK1_FREQUENCY) + +/* Timers driven from APB2 is equal to PCLK1 */ + +#define STM32_APB2_TIM1_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB2_TIM14_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB2_TIM15_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB2_TIM16_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB2_TIM17_CLKIN (STM32_PCLK1_FREQUENCY) + +/* LED definitions **********************************************************/ + +/* Nucleo G070RB board has three LEDs. Two of these are controlled by + * logic on the board and are not available for software control: + * + * LD1 COM: LD1 default status is red. LD1 turns to green to indicate that + * communications are in progress between the PC and the + * ST-LINK/V2-1. + * LD3 5V_PWR: green LED indicates that the board is powered by a 5V source. + * + * And one can be controlled by software: + * + * User LD4: green LED is a user LED connected to STM32 I/O PA5. + * + * If CONFIG_ARCH_LEDS is not defined, then the user can control the LED in + * any way. The following definition is used to access the LED. + */ + +/* LED index values for use with board_userled() */ + +#define BOARD_LED1 0 /* User LD4 */ +#define BOARD_NLEDS 1 + +/* LED bits for use with board_userled_all() */ + +#define BOARD_LED1_BIT (1 << BOARD_LED1) + +/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the LED on the + * board. The following definitions describe how NuttX controls + * the LED: + * + * SYMBOL Meaning LED1 state + * ------------------ ----------------------- ---------- + * LED_STARTED NuttX has been started OFF + * LED_HEAPALLOCATE Heap has been allocated OFF + * LED_IRQSENABLED Interrupts enabled OFF + * LED_STACKCREATED Idle stack created ON + * LED_INIRQ In an interrupt No change + * LED_SIGNAL In a signal handler No change + * LED_ASSERTION An assertion failed No change + * LED_PANIC The system has crashed Blinking + * LED_IDLE STM32 is in sleep mode Not used + */ + +#define LED_STARTED 0 +#define LED_HEAPALLOCATE 0 +#define LED_IRQSENABLED 0 +#define LED_STACKCREATED 1 +#define LED_INIRQ 2 +#define LED_SIGNAL 2 +#define LED_ASSERTION 2 +#define LED_PANIC 1 + +/* Button definitions *******************************************************/ + +/* Nucleo G070RB board supports two buttons; only one button is controllable + * by software: + * + * B1 USER: user button connected to STM32 I/O PC13. + * B2 RESET: push button connected to NRST; used to RESET the MCU. + */ + +#define BUTTON_USER 0 /* User B1 */ +#define NUM_BUTTONS 1 + +#define BUTTON_USER_BIT (1 << BUTTON_USER) + +/* Alternate function pin selections ****************************************/ + +/* I2C */ + +#define GPIO_I2C1_SCL (GPIO_I2C1_SCL_3|GPIO_SPEED_LOW) /* PB8 */ +#define GPIO_I2C1_SDA (GPIO_I2C1_SDA_3|GPIO_SPEED_LOW) /* PB9 */ + +/* TIM */ + +#define GPIO_TIM1_CH1OUT (GPIO_TIM1_CH1OUT_1|GPIO_SPEED_LOW) /* PA8 */ +#define GPIO_TIM1_CH2OUT (GPIO_TIM1_CH2OUT_2|GPIO_SPEED_LOW) /* PB3 */ +#define GPIO_TIM1_CH3OUT (GPIO_TIM1_CH3OUT_2|GPIO_SPEED_LOW) /* PB6 */ +#define GPIO_TIM1_CH4OUT (GPIO_TIM1_CH4OUT_1|GPIO_SPEED_LOW) /* PA11 */ +#define GPIO_TIM1_CH1NOUT (GPIO_TIM1_CH1NOUT_2|GPIO_SPEED_LOW) /* PB13 */ +#define GPIO_TIM1_CH2NOUT (GPIO_TIM1_CH2NOUT_2|GPIO_SPEED_LOW) /* PB14 */ +#define GPIO_TIM1_CH3NOUT (GPIO_TIM1_CH3NOUT_2|GPIO_SPEED_LOW) /* PB15 */ + +#define GPIO_TIM3_CH1OUT (GPIO_TIM3_CH1OUT_2|GPIO_SPEED_LOW) /* PB4 */ +#define GPIO_TIM3_CH2OUT (GPIO_TIM3_CH2OUT_2|GPIO_SPEED_LOW) /* PB5 */ +#define GPIO_TIM3_CH3OUT (GPIO_TIM3_CH3OUT_1|GPIO_SPEED_LOW) /* PB0 */ +#define GPIO_TIM3_CH4OUT (GPIO_TIM3_CH4OUT_1|GPIO_SPEED_LOW) /* PB1 */ + +#define GPIO_TIM14_CH1OUT (GPIO_TIM14_CH1OUT_2|GPIO_SPEED_LOW) /* PA7 */ + +#define GPIO_TIM15_CH1OUT (GPIO_TIM15_CH1OUT_3|GPIO_SPEED_LOW) /* PC1 */ +#define GPIO_TIM15_CH2OUT (GPIO_TIM15_CH2OUT_3|GPIO_SPEED_LOW) /* PC2 */ +#define GPIO_TIM15_CH1NOUT (GPIO_TIM15_CH1NOUT_1|GPIO_SPEED_LOW) /* PA1 */ + +#define GPIO_TIM16_CH1OUT (GPIO_TIM16_CH1OUT_3|GPIO_SPEED_LOW) /* PD0 */ + +#define GPIO_TIM17_CH1OUT (GPIO_TIM17_CH1OUT_2|GPIO_SPEED_LOW) /* PD1 */ + +/* USART */ + +/* By default the USART2 is connected to STLINK Virtual COM Port: + * USART2_RX - PA3 + * USART2_TX - PA2 + */ + +#define GPIO_USART2_RX (GPIO_USART2_RX_1|GPIO_SPEED_HIGH) /* PA3 */ +#define GPIO_USART2_TX (GPIO_USART2_TX_1|GPIO_SPEED_HIGH) /* PA2 */ + +/* DMA channels *************************************************************/ + +/* ADC */ + +/* TODO ADC */ + +#endif /* __BOARDS_ARM_STM32F0L0G0_NUCLEO_G070RB_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32g0/nucleo-g070rb/scripts/Make.defs b/boards/arm/stm32g0/nucleo-g070rb/scripts/Make.defs new file mode 100644 index 0000000000000..2e92c773e09d4 --- /dev/null +++ b/boards/arm/stm32g0/nucleo-g070rb/scripts/Make.defs @@ -0,0 +1,41 @@ +############################################################################ +# boards/arm/stm32g0/nucleo-g070rb/scripts/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/.config +include $(TOPDIR)/tools/Config.mk +include $(TOPDIR)/arch/arm/src/armv6-m/Toolchain.defs + +LDSCRIPT = ld.script +ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) + +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32g0/nucleo-g070rb/scripts/ld.script b/boards/arm/stm32g0/nucleo-g070rb/scripts/ld.script new file mode 100644 index 0000000000000..96714a97dd6b7 --- /dev/null +++ b/boards/arm/stm32g0/nucleo-g070rb/scripts/ld.script @@ -0,0 +1,115 @@ +/**************************************************************************** + * boards/arm/stm32g0/nucleo-g070rb/scripts/ld.script + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* The STM32G070RB has 128Kb of FLASH beginning at address 0x0800:0000 and + * 32Kb/36Kb of SRAM. + * + * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 + * where the code expects to begin execution by jumping to the entry point in + * the 0x0800:0000 address range. + */ + +MEMORY +{ + flash (rx) : ORIGIN = 0x08000000, LENGTH = 128K + sram (rwx) : ORIGIN = 0x20000000, LENGTH = 36K +} + +OUTPUT_ARCH(arm) +EXTERN(_vectors) +ENTRY(_stext) +SECTIONS +{ + .text : { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > flash + + .init_section : ALIGN(4) { + _sinit = ABSOLUTE(.); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) + _einit = ABSOLUTE(.); + } > flash + + .ARM.extab : ALIGN(4) { + *(.ARM.extab*) + } > flash + + .ARM.exidx : ALIGN(4) { + __exidx_start = ABSOLUTE(.); + *(.ARM.exidx*) + __exidx_end = ABSOLUTE(.); + } > flash + + _eronly = ABSOLUTE(.); + + /* The RAM vector table (if present) should lie at the beginning of SRAM */ + + .ram_vectors : { + *(.ram_vectors) + } > sram + + .data : ALIGN(4) { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > sram AT > flash + + .bss : ALIGN(4) { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + _ebss = ABSOLUTE(.); + } > sram + + /* Stabs debugging sections. */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/stm32g0/nucleo-g070rb/src/CMakeLists.txt b/boards/arm/stm32g0/nucleo-g070rb/src/CMakeLists.txt new file mode 100644 index 0000000000000..cea0f3cd6a324 --- /dev/null +++ b/boards/arm/stm32g0/nucleo-g070rb/src/CMakeLists.txt @@ -0,0 +1,49 @@ +# ############################################################################## +# boards/arm/stm32g0/nucleo-g070rb/src/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(SRCS stm32_boot.c stm32_bringup.c) + +if(CONFIG_ARCH_LEDS) + list(APPEND SRCS stm32_autoleds.c) +else() + list(APPEND SRCS stm32_userleds.c) +endif() + +if(CONFIG_ARCH_BUTTONS) + list(APPEND SRCS stm32_buttons.c) +endif() + +if(CONFIG_DEV_GPIO) + list(APPEND SRCS stm32_gpio.c) +endif() + +if(CONFIG_PWM) + list(APPEND SRCS stm32_pwm.c) +endif() + +if(CONFIG_TIMER) + list(APPEND SRCS stm32_timer.c) +endif() + +target_sources(board PRIVATE ${SRCS}) + +set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/ld.script") diff --git a/boards/arm/stm32g0/nucleo-g070rb/src/Make.defs b/boards/arm/stm32g0/nucleo-g070rb/src/Make.defs new file mode 100644 index 0000000000000..e7b3454bb3201 --- /dev/null +++ b/boards/arm/stm32g0/nucleo-g070rb/src/Make.defs @@ -0,0 +1,51 @@ +############################################################################ +# boards/arm/stm32g0/nucleo-g070rb/src/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +CSRCS = stm32_boot.c stm32_bringup.c + +ifeq ($(CONFIG_ARCH_LEDS),y) +CSRCS += stm32_autoleds.c +else +CSRCS += stm32_userleds.c +endif + +ifeq ($(CONFIG_ARCH_BUTTONS),y) +CSRCS += stm32_buttons.c +endif + +ifeq ($(CONFIG_DEV_GPIO),y) +CSRCS += stm32_gpio.c +endif + +ifeq ($(CONFIG_PWM),y) +CSRCS += stm32_pwm.c +endif + +ifeq ($(CONFIG_TIMER),y) +CSRCS += stm32_timer.c +endif + +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32f0l0g0/nucleo-g070rb/src/nucleo-g070rb.h b/boards/arm/stm32g0/nucleo-g070rb/src/nucleo-g070rb.h similarity index 98% rename from boards/arm/stm32f0l0g0/nucleo-g070rb/src/nucleo-g070rb.h rename to boards/arm/stm32g0/nucleo-g070rb/src/nucleo-g070rb.h index c48523c418437..7db19ce4ced36 100644 --- a/boards/arm/stm32f0l0g0/nucleo-g070rb/src/nucleo-g070rb.h +++ b/boards/arm/stm32g0/nucleo-g070rb/src/nucleo-g070rb.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-g070rb/src/nucleo-g070rb.h + * boards/arm/stm32g0/nucleo-g070rb/src/nucleo-g070rb.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32g0/nucleo-g070rb/src/stm32_autoleds.c b/boards/arm/stm32g0/nucleo-g070rb/src/stm32_autoleds.c new file mode 100644 index 0000000000000..185304a690388 --- /dev/null +++ b/boards/arm/stm32g0/nucleo-g070rb/src/stm32_autoleds.c @@ -0,0 +1,81 @@ +/**************************************************************************** + * boards/arm/stm32g0/nucleo-g070rb/src/stm32_autoleds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include + +#include "stm32_gpio.h" +#include "nucleo-g070rb.h" + +#include + +#ifdef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_autoled_initialize + ****************************************************************************/ + +void board_autoled_initialize(void) +{ + /* Configure LED1 GPIO for output */ + + stm32_configgpio(GPIO_LED1); +} + +/**************************************************************************** + * Name: board_autoled_on + ****************************************************************************/ + +void board_autoled_on(int led) +{ + if (led == BOARD_LED1) + { + stm32_gpiowrite(GPIO_LED1, true); + } +} + +/**************************************************************************** + * Name: board_autoled_off + ****************************************************************************/ + +void board_autoled_off(int led) +{ + if (led == BOARD_LED1) + { + stm32_gpiowrite(GPIO_LED1, false); + } +} + +#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32g0/nucleo-g070rb/src/stm32_boot.c b/boards/arm/stm32g0/nucleo-g070rb/src/stm32_boot.c new file mode 100644 index 0000000000000..c5fbfbc30471b --- /dev/null +++ b/boards/arm/stm32g0/nucleo-g070rb/src/stm32_boot.c @@ -0,0 +1,83 @@ +/**************************************************************************** + * boards/arm/stm32g0/nucleo-g070rb/src/stm32_boot.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include "nucleo-g070rb.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_boardinitialize + * + * Description: + * All STM32 architectures must provide the following entry point. This + * entry point is called early in the initialization -- after all memory + * has been configured and mapped but before any devices have been + * initialized. + * + ****************************************************************************/ + +void stm32_boardinitialize(void) +{ +#ifdef CONFIG_ARCH_LEDS + /* Configure on-board LEDs if LED support has been selected. */ + + board_autoled_initialize(); +#endif + +#ifdef CONFIG_STM32_SPI + /* Configure SPI chip selects */ + + stm32_spidev_initialize(); +#endif +} + +/**************************************************************************** + * Name: board_late_initialize + * + * Description: + * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_late_initialize(). board_late_initialize() will + * be called immediately after up_initialize() is called and just before + * the initial application is started. This additional initialization + * phase may be used, for example, to initialize board-specific device + * drivers. + * + ****************************************************************************/ + +#ifdef CONFIG_BOARD_LATE_INITIALIZE +void board_late_initialize(void) +{ + stm32_bringup(); +} +#endif diff --git a/boards/arm/stm32g0/nucleo-g070rb/src/stm32_bringup.c b/boards/arm/stm32g0/nucleo-g070rb/src/stm32_bringup.c new file mode 100644 index 0000000000000..8ca8dd171b865 --- /dev/null +++ b/boards/arm/stm32g0/nucleo-g070rb/src/stm32_bringup.c @@ -0,0 +1,213 @@ +/**************************************************************************** + * boards/arm/stm32g0/nucleo-g070rb/src/stm32_bringup.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include +#include + +#include "nucleo-g070rb.h" +#include "stm32_i2c.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#undef HAVE_LEDS +#undef HAVE_DAC + +#if !defined(CONFIG_ARCH_LEDS) && defined(CONFIG_USERLED_LOWER) +# define HAVE_LEDS 1 +#endif + +/* TODO ??? */ + +#if defined(CONFIG_DAC) +# define HAVE_DAC1 1 +# define HAVE_DAC2 1 +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_i2c_register + * + * Description: + * Register one I2C drivers for the I2C tool. + * + ****************************************************************************/ + +#if defined(CONFIG_I2C) && defined(CONFIG_SYSTEM_I2CTOOL) +static void stm32_i2c_register(int bus) +{ + struct i2c_master_s *i2c; + int ret; + + i2c = stm32_i2cbus_initialize(bus); + if (i2c == NULL) + { + syslog(LOG_ERR, "ERROR: Failed to get I2C%d interface\n", bus); + } + else + { + ret = i2c_register(i2c, bus); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to register I2C%d driver: %d\n", + bus, ret); + stm32_i2cbus_uninitialize(i2c); + } + } +} +#endif + +/**************************************************************************** + * Name: stm32_i2ctool + * + * Description: + * Register I2C drivers for the I2C tool. + * + ****************************************************************************/ + +#if defined(CONFIG_I2C) && defined(CONFIG_SYSTEM_I2CTOOL) +static void stm32_i2ctool(void) +{ +#ifdef CONFIG_STM32_I2C1 + stm32_i2c_register(1); +#endif +#ifdef CONFIG_STM32_I2C2 + stm32_i2c_register(2); +#endif +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_bringup + * + * Description: + * Perform architecture-specific initialization + * + * CONFIG_BOARD_LATE_INITIALIZE=y : + * Called from board_late_initialize(). + * + ****************************************************************************/ + +int stm32_bringup(void) +{ + int ret; + +#ifdef HAVE_LEDS + /* Register the LED driver */ + + ret = userled_lower_initialize(LED_DRIVER_PATH); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: userled_lower_initialize() failed: %d\n", ret); + return ret; + } +#endif + +#if defined(CONFIG_I2C) && defined(CONFIG_SYSTEM_I2CTOOL) + stm32_i2ctool(); +#endif + +#ifdef CONFIG_INPUT_BUTTONS + /* Register the BUTTON driver */ + + ret = btn_lower_initialize("/dev/buttons"); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: btn_lower_initialize() failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_DEV_GPIO + /* Register the GPIO driver */ + + ret = stm32_gpio_initialize(); + if (ret < 0) + { + syslog(LOG_ERR, "Failed to initialize GPIO Driver: %d\n", ret); + } +#endif + +#ifdef CONFIG_ADC + /* Initialize ADC and register the ADC driver. */ + + ret = stm32_adc_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_adc_setup failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_TIMER + /* Initialize basic timers */ + +#if defined(CONFIG_STM32_TIM6) + syslog(LOG_ERR, "Init timer\n"); + ret = stm32_timer_driver_setup("/dev/timer0", 6); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_timer_driver_setup failed. TIM6: %d\n", + ret); + } +#endif + +#if defined(CONFIG_STM32_TIM7) + ret = stm32_timer_driver_setup("/dev/timer1", 7); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_timer_driver_setup failed. TIM7: %d\n", + ret); + } + +#endif +#endif + +#if defined(CONFIG_PWM) + /* Initialize PWM and register the PWM device */ + + ret = stm32_pwm_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_pwm_setup() failed: %d\n", ret); + } +#endif + + UNUSED(ret); + return OK; +} diff --git a/boards/arm/stm32g0/nucleo-g070rb/src/stm32_buttons.c b/boards/arm/stm32g0/nucleo-g070rb/src/stm32_buttons.c new file mode 100644 index 0000000000000..4b711729ba839 --- /dev/null +++ b/boards/arm/stm32g0/nucleo-g070rb/src/stm32_buttons.c @@ -0,0 +1,118 @@ +/**************************************************************************** + * boards/arm/stm32g0/nucleo-g070rb/src/stm32_buttons.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "stm32_gpio.h" +#include "nucleo-g070rb.h" + +#include + +#ifdef CONFIG_ARCH_BUTTONS + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_button_initialize + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. + * + ****************************************************************************/ + +uint32_t board_button_initialize(void) +{ + /* Configure the single button as an input. NOTE that EXTI interrupts are + * also configured for the pin. + */ + + stm32_configgpio(GPIO_BTN_USER); + return NUM_BUTTONS; +} + +/**************************************************************************** + * Name: board_buttons + ****************************************************************************/ + +uint32_t board_buttons(void) +{ + /* Check that state of each USER button. A LOW value means that the key is + * pressed. + */ + + bool released = stm32_gpioread(GPIO_BTN_USER); + return !released; +} + +/**************************************************************************** + * Button support. + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. + * + * After board_button_initialize() has been called, board_buttons() may be + * called to collect the state of all buttons. board_buttons() returns an + * 32-bit bit set with each bit associated with a button. See the + * BUTTON_*_BIT definitions in board.h for the meaning of each bit. + * + * board_button_irq() may be called to register an interrupt handler that + * will be called when a button is depressed or released. The ID value is a + * button enumeration value that uniquely identifies a button resource. See + * the BUTTON_* definitions in board.h for the meaning of enumeration + * value. + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_IRQBUTTONS +int board_button_irq(int id, xcpt_t irqhandler, void *arg) +{ + int ret = -EINVAL; + + if (id == BUTTON_USER) + { + ret = stm32_gpiosetevent(GPIO_BTN_USER, true, true, true, irqhandler, + arg); + } + + return ret; +} +#endif +#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/stm32g0/nucleo-g070rb/src/stm32_gpio.c b/boards/arm/stm32g0/nucleo-g070rb/src/stm32_gpio.c new file mode 100644 index 0000000000000..d414c7c3e0599 --- /dev/null +++ b/boards/arm/stm32g0/nucleo-g070rb/src/stm32_gpio.c @@ -0,0 +1,364 @@ +/**************************************************************************** + * boards/arm/stm32g0/nucleo-g070rb/src/stm32_gpio.c + * + * SPDX-License-Identifier: BSD-3-Clause + * SPDX-FileCopyrightText: Fundação CERTI. All rights reserved. + * SPDX-FileContributor: Daniel Pereira Volpato + * SPDX-FileContributor: Guillherme da Silva Amaral + * SPDX-FileContributor: Alan Carvalho de Assis + * SPDX-FileContributor: Philippe Coval + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include +#include + +#include + +#include "chip.h" +#include "stm32_gpio.h" +#include "nucleo-g070rb.h" + +#if defined(CONFIG_DEV_GPIO) && !defined(CONFIG_GPIO_LOWER_HALF) + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +struct stm32gpio_dev_s +{ + struct gpio_dev_s gpio; + uint8_t id; +}; + +struct stm32gpint_dev_s +{ + struct stm32gpio_dev_s stm32gpio; + pin_interrupt_t callback; +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +static int gpin_read(struct gpio_dev_s *dev, bool *value); +static int gpout_read(struct gpio_dev_s *dev, bool *value); +static int gpout_write(struct gpio_dev_s *dev, bool value); +static int gpint_read(struct gpio_dev_s *dev, bool *value); +static int gpint_attach(struct gpio_dev_s *dev, + pin_interrupt_t callback); +static int gpint_enable(struct gpio_dev_s *dev, bool enable); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static const struct gpio_operations_s gpin_ops = +{ + .go_read = gpin_read, + .go_write = NULL, + .go_attach = NULL, + .go_enable = NULL, +}; + +static const struct gpio_operations_s gpout_ops = +{ + .go_read = gpout_read, + .go_write = gpout_write, + .go_attach = NULL, + .go_enable = NULL, +}; + +static const struct gpio_operations_s gpint_ops = +{ + .go_read = gpint_read, + .go_write = NULL, + .go_attach = gpint_attach, + .go_enable = gpint_enable, +}; + +#if BOARD_NGPIOIN > 0 +/* This array maps the GPIO pins used as INPUT */ + +static const uint32_t g_gpioinputs[BOARD_NGPIOIN] = +{ + GPIO_IN1, +}; + +static struct stm32gpio_dev_s g_gpin[BOARD_NGPIOIN]; +#endif + +#if BOARD_NGPIOOUT > 0 +/* This array maps the GPIO pins used as OUTPUT */ + +static const uint32_t g_gpiooutputs[BOARD_NGPIOOUT] = +{ + GPIO_OUT1, +}; + +static struct stm32gpio_dev_s g_gpout[BOARD_NGPIOOUT]; +#endif + +#if BOARD_NGPIOINT > 0 +/* This array maps the GPIO pins used as INTERRUPT INPUTS */ + +static const uint32_t g_gpiointinputs[BOARD_NGPIOINT] = +{ + GPIO_INT1, +}; + +static struct stm32gpint_dev_s g_gpint[BOARD_NGPIOINT]; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +static int stm32gpio_interrupt(int irq, void *context, void *arg) +{ + struct stm32gpint_dev_s *stm32gpint = + (struct stm32gpint_dev_s *)arg; + + DEBUGASSERT(stm32gpint != NULL && stm32gpint->callback != NULL); + gpioinfo("Interrupt! callback=%p\n", stm32gpint->callback); + + stm32gpint->callback(&stm32gpint->stm32gpio.gpio, + stm32gpint->stm32gpio.id); + return OK; +} + +static int gpin_read(struct gpio_dev_s *dev, bool *value) +{ +#if BOARD_NGPIOIN > 0 + struct stm32gpio_dev_s *stm32gpio = + (struct stm32gpio_dev_s *)dev; + + DEBUGASSERT(stm32gpio != NULL && value != NULL); + DEBUGASSERT(stm32gpio->id < BOARD_NGPIOIN); + gpioinfo("Reading...\n"); + + *value = stm32_gpioread(g_gpioinputs[stm32gpio->id]); + return OK; +#else + return ERROR; +#endif +} + +static int gpout_read(struct gpio_dev_s *dev, bool *value) +{ +#if BOARD_NGPIOOUT > 0 + struct stm32gpio_dev_s *stm32gpio = + (struct stm32gpio_dev_s *)dev; + + DEBUGASSERT(stm32gpio != NULL && value != NULL); + DEBUGASSERT(stm32gpio->id < BOARD_NGPIOOUT); + gpioinfo("Reading...\n"); + + *value = stm32_gpioread(g_gpiooutputs[stm32gpio->id]); + return OK; +#else + return ERROR; +#endif +} + +static int gpout_write(struct gpio_dev_s *dev, bool value) +{ +#if BOARD_NGPIOOUT > 0 + struct stm32gpio_dev_s *stm32gpio = + (struct stm32gpio_dev_s *)dev; + + DEBUGASSERT(stm32gpio != NULL); + DEBUGASSERT(stm32gpio->id < BOARD_NGPIOOUT); + gpioinfo("Writing %d\n", (int)value); + + stm32_gpiowrite(g_gpiooutputs[stm32gpio->id], value); + return OK; +#else + return ERROR; +#endif +} + +static int gpint_read(struct gpio_dev_s *dev, bool *value) +{ +#if BOARD_NGPIOINT > 0 + struct stm32gpint_dev_s *stm32gpint = + (struct stm32gpint_dev_s *)dev; + + DEBUGASSERT(stm32gpint != NULL && value != NULL); + DEBUGASSERT(stm32gpint->stm32gpio.id < BOARD_NGPIOINT); + gpioinfo("Reading int pin...\n"); + + *value = stm32_gpioread(g_gpiointinputs[stm32gpint->stm32gpio.id]); + return OK; +#else + return ERROR; +#endif +} + +static int gpint_attach(struct gpio_dev_s *dev, + pin_interrupt_t callback) +{ +#if BOARD_NGPIOINT > 0 + struct stm32gpint_dev_s *stm32gpint = + (struct stm32gpint_dev_s *)dev; + + gpioinfo("Attaching the callback\n"); + + /* Make sure the interrupt is disabled */ + + stm32_gpiosetevent(g_gpiointinputs[stm32gpint->stm32gpio.id], false, + false, false, NULL, NULL); + + gpioinfo("Attach %p\n", callback); + stm32gpint->callback = callback; + return OK; +#else + return ERROR; +#endif +} + +static int gpint_enable(struct gpio_dev_s *dev, bool enable) +{ +#if BOARD_NGPIOINT > 0 + struct stm32gpint_dev_s *stm32gpint = + (struct stm32gpint_dev_s *)dev; + + if (enable) + { + if (stm32gpint->callback != NULL) + { + gpioinfo("Enabling the interrupt\n"); + + /* Configure the interrupt for rising edge */ + + stm32_gpiosetevent(g_gpiointinputs[stm32gpint->stm32gpio.id], + true, false, false, stm32gpio_interrupt, + &g_gpint[stm32gpint->stm32gpio.id]); + } + } + else + { + gpioinfo("Disable the interrupt\n"); + stm32_gpiosetevent(g_gpiointinputs[stm32gpint->stm32gpio.id], + false, false, false, NULL, NULL); + } + + return OK; +#else + return ERROR; +#endif +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_gpio_initialize + * + * Description: + * Initialize GPIO drivers for use with /apps/examples/gpio + * + ****************************************************************************/ + +int stm32_gpio_initialize(void) +{ + int i; + int pincount = 0; + +#if BOARD_NGPIOIN > 0 + for (i = 0; i < BOARD_NGPIOIN; i++) + { + /* Setup and register the GPIO pin */ + + g_gpin[i].gpio.gp_pintype = GPIO_INPUT_PIN; + g_gpin[i].gpio.gp_ops = &gpin_ops; + g_gpin[i].id = i; + gpio_pin_register(&g_gpin[i].gpio, pincount); + + /* Configure the pin that will be used as input */ + + stm32_configgpio(g_gpioinputs[i]); + + pincount++; + } +#endif + +#if BOARD_NGPIOOUT > 0 + for (i = 0; i < BOARD_NGPIOOUT; i++) + { + /* Setup and register the GPIO pin */ + + g_gpout[i].gpio.gp_pintype = GPIO_OUTPUT_PIN; + g_gpout[i].gpio.gp_ops = &gpout_ops; + g_gpout[i].id = i; + gpio_pin_register(&g_gpout[i].gpio, pincount); + + /* Configure the pin that will be used as output */ + + stm32_gpiowrite(g_gpiooutputs[i], 0); + stm32_configgpio(g_gpiooutputs[i]); + + pincount++; + } +#endif + +#if BOARD_NGPIOINT > 0 + for (i = 0; i < BOARD_NGPIOINT; i++) + { + /* Setup and register the GPIO pin */ + + g_gpint[i].stm32gpio.gpio.gp_pintype = GPIO_INTERRUPT_PIN; + g_gpint[i].stm32gpio.gpio.gp_ops = &gpint_ops; + g_gpint[i].stm32gpio.id = i; + gpio_pin_register(&g_gpint[i].stm32gpio.gpio, pincount); + + /* Configure the pin that will be used as interrupt input */ + + stm32_configgpio(g_gpiointinputs[i]); + + pincount++; + } +#endif + + return 0; +} +#endif /* CONFIG_DEV_GPIO && !CONFIG_GPIO_LOWER_HALF */ diff --git a/boards/arm/stm32g0/nucleo-g070rb/src/stm32_pwm.c b/boards/arm/stm32g0/nucleo-g070rb/src/stm32_pwm.c new file mode 100644 index 0000000000000..cfcbef9088a36 --- /dev/null +++ b/boards/arm/stm32g0/nucleo-g070rb/src/stm32_pwm.c @@ -0,0 +1,208 @@ +/**************************************************************************** + * boards/arm/stm32g0/nucleo-g070rb/src/stm32_pwm.c + * + * SPDX-License-Identifier: BSD-3-Clause + * SPDX-FileCopyrightText: Fundação CERTI. All rights reserved. + * SPDX-FileContributor: Daniel Pereira Volpato + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "nucleo-g070rb.h" +#include "stm32_pwm.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define HAVE_PWM 1 +#ifndef CONFIG_PWM +# undef HAVE_PWM +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_pwm_setup + * + * Description: + * Initialize PWM and register the PWM device. + * + ****************************************************************************/ + +int stm32_pwm_setup(void) +{ +#ifdef HAVE_PWM + static bool initialized = false; + struct pwm_lowerhalf_s *pwm; + int ret; + + /* Have we already initialized? */ + + if (!initialized) + { + /* Call stm32_pwminitialize() to get an instance of the PWM interface */ + +#if defined(CONFIG_STM32_TIM1_PWM) + pwm = stm32_pwminitialize(1); + if (!pwm) + { + aerr("ERROR: Failed to get the STM32 PWM lower half\n"); + return -ENODEV; + } + + ret = pwm_register("/dev/pwm0", pwm); + if (ret < 0) + { + aerr("ERROR: pwm_register failed: %d\n", ret); + return ret; + } +#endif + +#if defined(CONFIG_STM32_TIM2_PWM) + pwm = stm32_pwminitialize(2); + if (!pwm) + { + aerr("ERROR: Failed to get the STM32 PWM lower half\n"); + return -ENODEV; + } + + ret = pwm_register("/dev/pwm1", pwm); + if (ret < 0) + { + aerr("ERROR: pwm_register failed: %d\n", ret); + return ret; + } +#endif + +#if defined(CONFIG_STM32_TIM3_PWM) + pwm = stm32_pwminitialize(3); + if (!pwm) + { + aerr("ERROR: Failed to get the STM32 PWM lower half\n"); + return -ENODEV; + } + + ret = pwm_register("/dev/pwm2", pwm); + if (ret < 0) + { + aerr("ERROR: pwm_register failed: %d\n", ret); + return ret; + } +#endif + +#if defined(CONFIG_STM32_TIM14_PWM) + pwm = stm32_pwminitialize(14); + if (!pwm) + { + aerr("ERROR: Failed to get the STM32 PWM lower half\n"); + return -ENODEV; + } + + ret = pwm_register("/dev/pwm13", pwm); + if (ret < 0) + { + aerr("ERROR: pwm_register failed: %d\n", ret); + return ret; + } +#endif + +#if defined(CONFIG_STM32_TIM15_PWM) + pwm = stm32_pwminitialize(15); + if (!pwm) + { + aerr("ERROR: Failed to get the STM32 PWM lower half\n"); + return -ENODEV; + } + + ret = pwm_register("/dev/pwm14", pwm); + if (ret < 0) + { + aerr("ERROR: pwm_register failed: %d\n", ret); + return ret; + } +#endif + +#if defined(CONFIG_STM32_TIM16_PWM) + pwm = stm32_pwminitialize(16); + if (!pwm) + { + aerr("ERROR: Failed to get the STM32 PWM lower half\n"); + return -ENODEV; + } + + ret = pwm_register("/dev/pwm15", pwm); + if (ret < 0) + { + aerr("ERROR: pwm_register failed: %d\n", ret); + return ret; + } +#endif + +#if defined(CONFIG_STM32_TIM17_PWM) + pwm = stm32_pwminitialize(17); + if (!pwm) + { + aerr("ERROR: Failed to get the STM32 PWM lower half\n"); + return -ENODEV; + } + + ret = pwm_register("/dev/pwm16", pwm); + if (ret < 0) + { + aerr("ERROR: pwm_register failed: %d\n", ret); + return ret; + } +#endif + + /* Now we are initialized */ + + initialized = true; + } + + return OK; +#else + return -ENODEV; +#endif +} diff --git a/boards/arm/stm32g0/nucleo-g070rb/src/stm32_timer.c b/boards/arm/stm32g0/nucleo-g070rb/src/stm32_timer.c new file mode 100644 index 0000000000000..886e6f72ca06e --- /dev/null +++ b/boards/arm/stm32g0/nucleo-g070rb/src/stm32_timer.c @@ -0,0 +1,81 @@ +/**************************************************************************** + * boards/arm/stm32g0/nucleo-g070rb/src/stm32_timer.c + * + * SPDX-License-Identifier: BSD-3-Clause + * SPDX-FileCopyrightText: Fundação CERTI. All rights reserved. + * SPDX-FileContributor: Daniel Pereira Volpato + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include + +#include "stm32_tim.h" +#include "nucleo-g070rb.h" + +#ifdef CONFIG_TIMER + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_timer_driver_setup + * + * Description: + * Configure the timer driver. + * + * Input Parameters: + * devpath - The full path to the timer device. This should be of the form + * /dev/timer0 + * timer - The timer's number. + * + * Returned Value: + * Zero (OK) is returned on success; A negated errno value is returned + * to indicate the nature of any failure. + * + ****************************************************************************/ + +int stm32_timer_driver_setup(const char *devpath, int timer) +{ + return stm32_timer_initialize(devpath, timer); +} + +#endif /* CONFIG_TIMER */ diff --git a/boards/arm/stm32g0/nucleo-g071rb/CMakeLists.txt b/boards/arm/stm32g0/nucleo-g071rb/CMakeLists.txt new file mode 100644 index 0000000000000..4d11fab0a1873 --- /dev/null +++ b/boards/arm/stm32g0/nucleo-g071rb/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32g0/nucleo-g071rb/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/arm/stm32f0l0g0/nucleo-g071rb/Kconfig b/boards/arm/stm32g0/nucleo-g071rb/Kconfig similarity index 100% rename from boards/arm/stm32f0l0g0/nucleo-g071rb/Kconfig rename to boards/arm/stm32g0/nucleo-g071rb/Kconfig diff --git a/boards/arm/stm32g0/nucleo-g071rb/configs/nsh/defconfig b/boards/arm/stm32g0/nucleo-g071rb/configs/nsh/defconfig new file mode 100644 index 0000000000000..fd83983a8e0b2 --- /dev/null +++ b/boards/arm/stm32g0/nucleo-g071rb/configs/nsh/defconfig @@ -0,0 +1,50 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_ARGCAT is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nucleo-g071rb" +CONFIG_ARCH_BOARD_NUCLEO_G071RB=y +CONFIG_ARCH_CHIP="stm32g0" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32G071RB=y +CONFIG_ARCH_CHIP_STM32G0=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=2796 +CONFIG_BUILTIN=y +CONFIG_DISABLE_ENVIRON=y +CONFIG_DISABLE_MOUNTPOINT=y +CONFIG_DISABLE_MQUEUE=y +CONFIG_DISABLE_POSIX_TIMERS=y +CONFIG_DISABLE_PSEUDOFS_OPERATIONS=y +CONFIG_EXAMPLES_HELLO=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=1536 +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=64 +CONFIG_NSH_READLINE=y +CONFIG_NUNGET_CHARS=0 +CONFIG_POSIX_SPAWN_DEFAULT_STACKSIZE=1536 +CONFIG_PTHREAD_MUTEX_UNSAFE=y +CONFIG_PTHREAD_STACK_DEFAULT=1536 +CONFIG_RAM_SIZE=20480 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=19 +CONFIG_START_MONTH=5 +CONFIG_START_YEAR=2013 +CONFIG_STDIO_DISABLE_BUFFERING=y +CONFIG_STM32_PWR=y +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32g0/nucleo-g071rb/include/board.h b/boards/arm/stm32g0/nucleo-g071rb/include/board.h new file mode 100644 index 0000000000000..bf18ab683b9a2 --- /dev/null +++ b/boards/arm/stm32g0/nucleo-g071rb/include/board.h @@ -0,0 +1,210 @@ +/**************************************************************************** + * boards/arm/stm32g0/nucleo-g071rb/include/board.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_STM32F0L0G0_NUCLEO_G071RB_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32F0L0G0_NUCLEO_G071RB_INCLUDE_BOARD_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#ifndef __ASSEMBLY__ +# include +# include +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Clocking *****************************************************************/ + +/* HSI - Internal 16 MHz RC Oscillator + * LSI - 32 KHz RC + * HSE - 8 MHz from MCO output of ST-LINK (disabled by default) + * LSE - 32.768 kHz + */ + +#define STM32_BOARD_XTAL 8000000ul + +#define STM32_HSI_FREQUENCY 16000000ul +#define STM32_LSI_FREQUENCY 32000 /* Between 30kHz and 60kHz */ +#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL +#define STM32_LSE_FREQUENCY 32768 /* X2 on board */ + +/* Main PLL Configuration. + * + * PLL source is HSI = 16,000,000 + * + * PLL_VCOx = (STM32_HSE_FREQUENCY / PLLM) * PLLN + * Subject to: + * + * 1 <= PLLM <= 8 + * 8 <= PLLN <= 86 + * 4 MHz <= PLL_IN <= 16MHz + * 64 MHz <= PLL_VCO <= 344MHz + * SYSCLK = PLLRCLK = PLL_VCO / PLLR + * + */ + +/* PLL source is HSI, PLLN=50, PLLM=4 + * PLLP enable, PLLQ enable, PLLR enable + * + * 2 <= PLLP <= 32 + * 2 <= PLLQ <= 8 + * 2 <= PLLR <= 8 + * + * PLLR <= 64MHz + * PLLQ <= 128MHz + * PLLP <= 128MHz + * + * PLL_VCO = (16,000,000 / 4) * 50 = 200 MHz + * + * PLLP = PLL_VCO/4 = 200 MHz / 4 = 40 MHz + * PLLQ = PLL_VCO/4 = 200 MHz / 4 = 40 MHz + * PLLR = PLL_VCO/4 = 200 MHz / 4 = 40 MHz + */ + +#define STM32_PLLCFG_PLLSRC RCC_PLLCFG_PLLSRC_HSI +#define STM32_PLLCFG_PLLCFG (RCC_PLLCFG_PLLPEN | \ + RCC_PLLCFG_PLLQEN | \ + RCC_PLLCFG_PLLREN) + +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(4) +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(50) +#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP(4) +#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(4) +#define STM32_PLLCFG_PLLR RCC_PLLCFG_PLLR(4) + +#define STM32_VCO_FREQUENCY ((STM32_HSE_FREQUENCY / 2) * 50) +#define STM32_PLLP_FREQUENCY (STM32_VCO_FREQUENCY / 4) +#define STM32_PLLQ_FREQUENCY (STM32_VCO_FREQUENCY / 4) +#define STM32_PLLR_FREQUENCY (STM32_VCO_FREQUENCY / 4) + +/* Use the PLL and set the SYSCLK source to be the PLLR (40MHz) */ + +#define STM32_SYSCLK_SW RCC_CFGR_SW_PLL +#define STM32_SYSCLK_SWS RCC_CFGR_SWS_PLL +#define STM32_SYSCLK_FREQUENCY (STM32_PLLR_FREQUENCY) + +/* AHB clock (HCLK) is SYSCLK (40MHz) */ + +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY + +/* APB1 clock (PCLK1) is HCLK/2 (20MHz) */ + +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd2 +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/2) + +/* TODO: timers */ + +/* LED definitions **********************************************************/ + +/* The Nucleo LO73RZ board has three LEDs. Two of these are controlled by + * logic on the board and are not available for software control: + * + * LD1 COM: LD1 default status is red. LD1 turns to green to indicate that + * communications are in progress between the PC and the + * ST-LINK/V2-1. + * LD3 PWR: red LED indicates that the board is powered. + * + * And one can be controlled by software: + * + * User LD2: green LED is a user LED connected to the I/O PA5 of the + * STM32LO73RZ. + * + * If CONFIG_ARCH_LEDS is not defined, then the user can control the LED in + * any way. The following definition is used to access the LED. + */ + +/* LED index values for use with board_userled() */ + +#define BOARD_LED1 0 /* User LD2 */ +#define BOARD_NLEDS 1 + +/* LED bits for use with board_userled_all() */ + +#define BOARD_LED1_BIT (1 << BOARD_LED1) + +/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the LED on board + * the Nucleo LO73RZ. The following definitions describe how NuttX controls + * the LED: + * + * SYMBOL Meaning LED1 state + * ------------------ ----------------------- ---------- + * LED_STARTED NuttX has been started OFF + * LED_HEAPALLOCATE Heap has been allocated OFF + * LED_IRQSENABLED Interrupts enabled OFF + * LED_STACKCREATED Idle stack created ON + * LED_INIRQ In an interrupt No change + * LED_SIGNAL In a signal handler No change + * LED_ASSERTION An assertion failed No change + * LED_PANIC The system has crashed Blinking + * LED_IDLE STM32 is in sleep mode Not used + */ + +#define LED_STARTED 0 +#define LED_HEAPALLOCATE 0 +#define LED_IRQSENABLED 0 +#define LED_STACKCREATED 1 +#define LED_INIRQ 2 +#define LED_SIGNAL 2 +#define LED_ASSERTION 2 +#define LED_PANIC 1 + +/* Button definitions *******************************************************/ + +/* The Nucleo LO73RZ supports two buttons; only one button is controllable + * by software: + * + * B1 USER: user button connected to the I/O PC13 of the STM32LO73RZ. + * B2 RESET: push button connected to NRST is used to RESET the + * STM32LO73RZ. + */ + +#define BUTTON_USER 0 +#define NUM_BUTTONS 1 + +#define BUTTON_USER_BIT (1 << BUTTON_USER) + +/* Alternate function pin selections ****************************************/ + +/* USART */ + +/* By default the USART2 is connected to STLINK Virtual COM Port: + * USART2_RX - PA3 + * USART2_TX - PA2 + */ + +#define GPIO_USART2_RX (GPIO_USART2_RX_1|GPIO_SPEED_HIGH) /* PA3 */ +#define GPIO_USART2_TX (GPIO_USART2_TX_1|GPIO_SPEED_HIGH) /* PA2 */ + +/* DMA channels *************************************************************/ + +/* ADC */ + +#define ADC1_DMA_CHAN DMACHAN_ADC1 /* DMA1_CH1 */ + +#endif /* __BOARDS_ARM_STM32F0L0G0_NUCLEO_LO73RZ_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32g0/nucleo-g071rb/scripts/Make.defs b/boards/arm/stm32g0/nucleo-g071rb/scripts/Make.defs new file mode 100644 index 0000000000000..dfc69a1d5bf71 --- /dev/null +++ b/boards/arm/stm32g0/nucleo-g071rb/scripts/Make.defs @@ -0,0 +1,41 @@ +############################################################################ +# boards/arm/stm32g0/nucleo-g071rb/scripts/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/.config +include $(TOPDIR)/tools/Config.mk +include $(TOPDIR)/arch/arm/src/armv6-m/Toolchain.defs + +LDSCRIPT = ld.script +ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) + +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32g0/nucleo-g071rb/scripts/ld.script b/boards/arm/stm32g0/nucleo-g071rb/scripts/ld.script new file mode 100644 index 0000000000000..9ea7803e49ae5 --- /dev/null +++ b/boards/arm/stm32g0/nucleo-g071rb/scripts/ld.script @@ -0,0 +1,115 @@ +/**************************************************************************** + * boards/arm/stm32g0/nucleo-g071rb/scripts/ld.script + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* The STM32GO71RB has 128Kb of FLASH beginning at address 0x0800:0000. + * 32Kb/36Kb of SRAM + * + * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 + * where the code expects to begin execution by jumping to the entry point in + * the 0x0800:0000 address range. + */ + +MEMORY +{ + flash (rx) : ORIGIN = 0x08000000, LENGTH = 128K + sram (rwx) : ORIGIN = 0x20000000, LENGTH = 36K +} + +OUTPUT_ARCH(arm) +EXTERN(_vectors) +ENTRY(_stext) +SECTIONS +{ + .text : { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > flash + + .init_section : ALIGN(4) { + _sinit = ABSOLUTE(.); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) + _einit = ABSOLUTE(.); + } > flash + + .ARM.extab : ALIGN(4) { + *(.ARM.extab*) + } > flash + + .ARM.exidx : ALIGN(4) { + __exidx_start = ABSOLUTE(.); + *(.ARM.exidx*) + __exidx_end = ABSOLUTE(.); + } > flash + + _eronly = ABSOLUTE(.); + + /* The RAM vector table (if present) should lie at the beginning of SRAM */ + + .ram_vectors : { + *(.ram_vectors) + } > sram + + .data : ALIGN(4) { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > sram AT > flash + + .bss : ALIGN(4) { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + _ebss = ABSOLUTE(.); + } > sram + + /* Stabs debugging sections. */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/stm32g0/nucleo-g071rb/src/CMakeLists.txt b/boards/arm/stm32g0/nucleo-g071rb/src/CMakeLists.txt new file mode 100644 index 0000000000000..4a054473a96d2 --- /dev/null +++ b/boards/arm/stm32g0/nucleo-g071rb/src/CMakeLists.txt @@ -0,0 +1,37 @@ +# ############################################################################## +# boards/arm/stm32g0/nucleo-g071rb/src/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(SRCS stm32_boot.c stm32_bringup.c) + +if(CONFIG_ARCH_LEDS) + list(APPEND SRCS stm32_autoleds.c) +else() + list(APPEND SRCS stm32_userleds.c) +endif() + +if(CONFIG_ARCH_BUTTONS) + list(APPEND SRCS stm32_buttons.c) +endif() + +target_sources(board PRIVATE ${SRCS}) + +set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/ld.script") diff --git a/boards/arm/stm32g0/nucleo-g071rb/src/Make.defs b/boards/arm/stm32g0/nucleo-g071rb/src/Make.defs new file mode 100644 index 0000000000000..3fa2cd2f85f94 --- /dev/null +++ b/boards/arm/stm32g0/nucleo-g071rb/src/Make.defs @@ -0,0 +1,39 @@ +############################################################################ +# boards/arm/stm32g0/nucleo-g071rb/src/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +CSRCS = stm32_boot.c stm32_bringup.c + +ifeq ($(CONFIG_ARCH_LEDS),y) +CSRCS += stm32_autoleds.c +else +CSRCS += stm32_userleds.c +endif + +ifeq ($(CONFIG_ARCH_BUTTONS),y) +CSRCS += stm32_buttons.c +endif + +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32f0l0g0/nucleo-g071rb/src/nucleo-g071rb.h b/boards/arm/stm32g0/nucleo-g071rb/src/nucleo-g071rb.h similarity index 98% rename from boards/arm/stm32f0l0g0/nucleo-g071rb/src/nucleo-g071rb.h rename to boards/arm/stm32g0/nucleo-g071rb/src/nucleo-g071rb.h index 32e9d86e5fbe8..cda374f9f4393 100644 --- a/boards/arm/stm32f0l0g0/nucleo-g071rb/src/nucleo-g071rb.h +++ b/boards/arm/stm32g0/nucleo-g071rb/src/nucleo-g071rb.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-g071rb/src/nucleo-g071rb.h + * boards/arm/stm32g0/nucleo-g071rb/src/nucleo-g071rb.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32g0/nucleo-g071rb/src/stm32_autoleds.c b/boards/arm/stm32g0/nucleo-g071rb/src/stm32_autoleds.c new file mode 100644 index 0000000000000..38287bbc4a15a --- /dev/null +++ b/boards/arm/stm32g0/nucleo-g071rb/src/stm32_autoleds.c @@ -0,0 +1,81 @@ +/**************************************************************************** + * boards/arm/stm32g0/nucleo-g071rb/src/stm32_autoleds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include + +#include "stm32_gpio.h" +#include "nucleo-g071rb.h" + +#include + +#ifdef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_autoled_initialize + ****************************************************************************/ + +void board_autoled_initialize(void) +{ + /* Configure LED1 GPIO for output */ + + stm32_configgpio(GPIO_LED1); +} + +/**************************************************************************** + * Name: board_autoled_on + ****************************************************************************/ + +void board_autoled_on(int led) +{ + if (led == BOARD_LED1) + { + stm32_gpiowrite(GPIO_LED1, true); + } +} + +/**************************************************************************** + * Name: board_autoled_off + ****************************************************************************/ + +void board_autoled_off(int led) +{ + if (led == BOARD_LED1) + { + stm32_gpiowrite(GPIO_LED1, false); + } +} + +#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32g0/nucleo-g071rb/src/stm32_boot.c b/boards/arm/stm32g0/nucleo-g071rb/src/stm32_boot.c new file mode 100644 index 0000000000000..5f891341e72ee --- /dev/null +++ b/boards/arm/stm32g0/nucleo-g071rb/src/stm32_boot.c @@ -0,0 +1,85 @@ +/**************************************************************************** + * boards/arm/stm32g0/nucleo-g071rb/src/stm32_boot.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include "nucleo-g071rb.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_boardinitialize + * + * Description: + * All STM32 architectures must provide the following entry point. This + * entry point is called early in the initialization -- after all memory + * has been configured and mapped but before any devices have been + * initialized. + * + ****************************************************************************/ + +void stm32_boardinitialize(void) +{ +#ifdef CONFIG_ARCH_LEDS + /* Configure on-board LEDs if LED support has been selected. */ + + board_autoled_initialize(); +#endif + +#ifdef CONFIG_STM32_SPI + /* Configure SPI chip selects */ + + stm32_spidev_initialize(); +#endif +} + +/**************************************************************************** + * Name: board_late_initialize + * + * Description: + * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_late_initialize(). board_late_initialize() will + * be called immediately after up_initialize() is called and just before + * the initial application is started. This additional initialization + * phase may be used, for example, to initialize board-specific device + * drivers. + * + ****************************************************************************/ + +#ifdef CONFIG_BOARD_LATE_INITIALIZE +void board_late_initialize(void) +{ + /* Perform board-specific initialization */ + + stm32_bringup(); +} +#endif diff --git a/boards/arm/stm32g0/nucleo-g071rb/src/stm32_bringup.c b/boards/arm/stm32g0/nucleo-g071rb/src/stm32_bringup.c new file mode 100644 index 0000000000000..d36512d8e58ba --- /dev/null +++ b/boards/arm/stm32g0/nucleo-g071rb/src/stm32_bringup.c @@ -0,0 +1,152 @@ +/**************************************************************************** + * boards/arm/stm32g0/nucleo-g071rb/src/stm32_bringup.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include + +#include "nucleo-g071rb.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#undef HAVE_LEDS +#undef HAVE_DAC + +#if !defined(CONFIG_ARCH_LEDS) && defined(CONFIG_USERLED_LOWER) +# define HAVE_LEDS 1 +#endif + +#if defined(CONFIG_DAC) +# define HAVE_DAC1 1 +# define HAVE_DAC2 1 +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_bringup + * + * Description: + * Perform architecture-specific initialization + * + * CONFIG_BOARD_LATE_INITIALIZE=y : + * Called from board_late_initialize(). + * + ****************************************************************************/ + +int stm32_bringup(void) +{ + int ret; + +#ifdef HAVE_LEDS + /* Register the LED driver */ + + ret = userled_lower_initialize(LED_DRIVER_PATH); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: userled_lower_initialize() failed: %d\n", + ret); + return ret; + } +#endif + +#ifdef CONFIG_ADC + /* Initialize ADC and register the ADC driver. */ + + ret = stm32_adc_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_adc_setup failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_DAC + /* Initialize DAC and register the DAC driver. */ + + ret = stm32_dac_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_dac_setup failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_COMP + /* Initialize COMP and register the COMP driver. */ + + ret = stm32_comp_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_comp_setup failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_OPAMP + /* Initialize OPAMP and register the OPAMP driver. */ + + ret = stm32_opamp_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_opamp_setup failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_WL_NRF24L01 + ret = stm32_wlinitialize(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to initialize wireless driver: %d\n", + ret); + } +#endif /* CONFIG_WL_NRF24L01 */ + +#ifdef CONFIG_LPWAN_SX127X + ret = stm32_lpwaninitialize(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to initialize wireless driver: %d\n", + ret); + } +#endif /* CONFIG_LPWAN_SX127X */ + +#ifdef CONFIG_CL_MFRC522 + ret = stm32_mfrc522initialize("/dev/rfid0"); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_mfrc522initialize() failed: %d\n", ret); + } +#endif /* CONFIG_CL_MFRC522 */ + + UNUSED(ret); + return OK; +} diff --git a/boards/arm/stm32g0/nucleo-g071rb/src/stm32_buttons.c b/boards/arm/stm32g0/nucleo-g071rb/src/stm32_buttons.c new file mode 100644 index 0000000000000..881950a0dbc6f --- /dev/null +++ b/boards/arm/stm32g0/nucleo-g071rb/src/stm32_buttons.c @@ -0,0 +1,118 @@ +/**************************************************************************** + * boards/arm/stm32g0/nucleo-g071rb/src/stm32_buttons.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "stm32_gpio.h" +#include "nucleo-g071rb.h" + +#include + +#ifdef CONFIG_ARCH_BUTTONS + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_button_initialize + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. + * + ****************************************************************************/ + +uint32_t board_button_initialize(void) +{ + /* Configure the single button as an input. NOTE that EXTI interrupts are + * also configured for the pin. + */ + + stm32_configgpio(GPIO_BTN_USER); + return NUM_BUTTONS; +} + +/**************************************************************************** + * Name: board_buttons + ****************************************************************************/ + +uint32_t board_buttons(void) +{ + /* Check that state of each USER button. A LOW value means that the key is + * pressed. + */ + + bool released = stm32_gpioread(GPIO_BTN_USER); + return !released; +} + +/**************************************************************************** + * Button support. + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. + * + * After board_button_initialize() has been called, board_buttons() may be + * called to collect the state of all buttons. board_buttons() returns an + * 32-bit bit set with each bit associated with a button. See the + * BUTTON_*_BIT definitions in board.h for the meaning of each bit. + * + * board_button_irq() may be called to register an interrupt handler that + * will be called when a button is depressed or released. The ID value is a + * button enumeration value that uniquely identifies a button resource. See + * the BUTTON_* definitions in board.h for the meaning of enumeration + * value. + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_IRQBUTTONS +int board_button_irq(int id, xcpt_t irqhandler, void *arg) +{ + int ret = -EINVAL; + + if (id == BUTTON_USER) + { + ret = stm32_gpiosetevent(GPIO_BTN_USER, true, true, true, + irqhandler, arg); + } + + return ret; +} +#endif +#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/stm32g0/nucleo-g0b1re/CMakeLists.txt b/boards/arm/stm32g0/nucleo-g0b1re/CMakeLists.txt new file mode 100644 index 0000000000000..7acee0b7feda7 --- /dev/null +++ b/boards/arm/stm32g0/nucleo-g0b1re/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32g0/nucleo-g0b1re/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/arm/stm32f0l0g0/nucleo-g0b1re/Kconfig b/boards/arm/stm32g0/nucleo-g0b1re/Kconfig similarity index 100% rename from boards/arm/stm32f0l0g0/nucleo-g0b1re/Kconfig rename to boards/arm/stm32g0/nucleo-g0b1re/Kconfig diff --git a/boards/arm/stm32g0/nucleo-g0b1re/configs/adc/defconfig b/boards/arm/stm32g0/nucleo-g0b1re/configs/adc/defconfig new file mode 100644 index 0000000000000..c72cc65d0a792 --- /dev/null +++ b/boards/arm/stm32g0/nucleo-g0b1re/configs/adc/defconfig @@ -0,0 +1,57 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_ARGCAT is not set +CONFIG_ADC=y +CONFIG_ANALOG=y +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nucleo-g0b1re" +CONFIG_ARCH_BOARD_NUCLEO_G0B1RE=y +CONFIG_ARCH_CHIP="stm32g0" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32G0=y +CONFIG_ARCH_CHIP_STM32G0B1RE=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=4164 +CONFIG_BUILTIN=y +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_DISABLE_ENVIRON=y +CONFIG_DISABLE_MQUEUE=y +CONFIG_DISABLE_POSIX_TIMERS=y +CONFIG_DISABLE_PSEUDOFS_OPERATIONS=y +CONFIG_EXAMPLES_ADC=y +CONFIG_EXAMPLES_ADC_GROUPSIZE=1 +CONFIG_EXAMPLES_ADC_NSAMPLES=1 +CONFIG_EXAMPLES_HELLO=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=1536 +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=64 +CONFIG_NSH_READLINE=y +CONFIG_NUNGET_CHARS=0 +CONFIG_POSIX_SPAWN_DEFAULT_STACKSIZE=1536 +CONFIG_PTHREAD_MUTEX_UNSAFE=y +CONFIG_PTHREAD_STACK_DEFAULT=1536 +CONFIG_RAM_SIZE=147456 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=19 +CONFIG_START_MONTH=5 +CONFIG_START_YEAR=2013 +CONFIG_STDIO_DISABLE_BUFFERING=y +CONFIG_STM32_ADC1=y +CONFIG_STM32_PWR=y +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32g0/nucleo-g0b1re/configs/adc_dma/defconfig b/boards/arm/stm32g0/nucleo-g0b1re/configs/adc_dma/defconfig new file mode 100644 index 0000000000000..6b0f6cd7c324f --- /dev/null +++ b/boards/arm/stm32g0/nucleo-g0b1re/configs/adc_dma/defconfig @@ -0,0 +1,68 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_ARGCAT is not set +CONFIG_ADC=y +CONFIG_ADC_FIFOSIZE=64 +CONFIG_ANALOG=y +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nucleo-g0b1re" +CONFIG_ARCH_BOARD_NUCLEO_G0B1RE=y +CONFIG_ARCH_CHIP="stm32g0" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32G0=y +CONFIG_ARCH_CHIP_STM32G0B1RE=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL=y +CONFIG_BOARD_LOOPSPERMSEC=4164 +CONFIG_BUILTIN=y +CONFIG_DEBUG_FEATURES=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_DISABLE_ENVIRON=y +CONFIG_DISABLE_MOUNTPOINT=y +CONFIG_DISABLE_MQUEUE=y +CONFIG_DISABLE_POSIX_TIMERS=y +CONFIG_DISABLE_PSEUDOFS_OPERATIONS=y +CONFIG_EXAMPLES_ADC=y +CONFIG_EXAMPLES_ADC_NSAMPLES=1 +CONFIG_EXAMPLES_HELLO=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=1536 +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=64 +CONFIG_NSH_READLINE=y +CONFIG_NUNGET_CHARS=0 +CONFIG_POSIX_SPAWN_DEFAULT_STACKSIZE=1536 +CONFIG_PTHREAD_MUTEX_UNSAFE=y +CONFIG_PTHREAD_STACK_DEFAULT=1536 +CONFIG_RAM_SIZE=147456 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=19 +CONFIG_START_MONTH=5 +CONFIG_START_YEAR=2013 +CONFIG_STDIO_DISABLE_BUFFERING=y +CONFIG_STM32_ADC1=y +CONFIG_STM32_ADC1_CONTINUOUS=y +CONFIG_STM32_ADC1_DMA=y +CONFIG_STM32_ADC1_DMA_CFG=1 +CONFIG_STM32_ADC_CHANGE_SAMPLETIME=y +CONFIG_STM32_ADC_LL_OPS=y +CONFIG_STM32_ADC_OVERSAMPLE=y +CONFIG_STM32_ADC_OVSR=7 +CONFIG_STM32_ADC_OVSS=4 +CONFIG_STM32_DMA1=y +CONFIG_STM32_PWR=y +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32g0/nucleo-g0b1re/configs/nsh/defconfig b/boards/arm/stm32g0/nucleo-g0b1re/configs/nsh/defconfig new file mode 100644 index 0000000000000..05e08970e6c0d --- /dev/null +++ b/boards/arm/stm32g0/nucleo-g0b1re/configs/nsh/defconfig @@ -0,0 +1,50 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_ARGCAT is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nucleo-g0b1re" +CONFIG_ARCH_BOARD_NUCLEO_G0B1RE=y +CONFIG_ARCH_CHIP="stm32g0" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32G0=y +CONFIG_ARCH_CHIP_STM32G0B1RE=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=4164 +CONFIG_BUILTIN=y +CONFIG_DISABLE_ENVIRON=y +CONFIG_DISABLE_MOUNTPOINT=y +CONFIG_DISABLE_MQUEUE=y +CONFIG_DISABLE_POSIX_TIMERS=y +CONFIG_DISABLE_PSEUDOFS_OPERATIONS=y +CONFIG_EXAMPLES_HELLO=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=1536 +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=64 +CONFIG_NSH_READLINE=y +CONFIG_NUNGET_CHARS=0 +CONFIG_POSIX_SPAWN_DEFAULT_STACKSIZE=1536 +CONFIG_PTHREAD_MUTEX_UNSAFE=y +CONFIG_PTHREAD_STACK_DEFAULT=1536 +CONFIG_RAM_SIZE=147456 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=19 +CONFIG_START_MONTH=5 +CONFIG_START_YEAR=2013 +CONFIG_STDIO_DISABLE_BUFFERING=y +CONFIG_STM32_PWR=y +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32g0/nucleo-g0b1re/include/board.h b/boards/arm/stm32g0/nucleo-g0b1re/include/board.h new file mode 100644 index 0000000000000..6120aad294eda --- /dev/null +++ b/boards/arm/stm32g0/nucleo-g0b1re/include/board.h @@ -0,0 +1,224 @@ +/**************************************************************************** + * boards/arm/stm32g0/nucleo-g0b1re/include/board.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_STM32F0L0G0_NUCLEO_G0B1RE_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32F0L0G0_NUCLEO_G0B1RE_INCLUDE_BOARD_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#ifndef __ASSEMBLY__ +# include +# include +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Clocking *****************************************************************/ + +/* HSI - Internal 16 MHz RC Oscillator + * LSI - 32 KHz RC + * HSE - 8 MHz from MCO output of ST-LINK (disabled by default) + * LSE - 32.768 kHz + */ + +#define STM32_BOARD_XTAL 8000000ul + +#define STM32_HSI_FREQUENCY 16000000ul +#define STM32_LSI_FREQUENCY 32000 /* Between 30kHz and 60kHz */ +#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL +#define STM32_LSE_FREQUENCY 32768 /* X2 on board */ + +/* Main PLL Configuration. + * + * PLL source is HSI = 16,000,000 + * + * PLL_VCOx = (STM32_HSE_FREQUENCY / PLLM) * PLLN + * Subject to: + * + * 1 <= PLLM <= 8 + * 8 <= PLLN <= 86 + * 4 MHz <= PLL_IN <= 16MHz + * 64 MHz <= PLL_VCO <= 344MHz + * SYSCLK = PLLRCLK = PLL_VCO / PLLR + * + */ + +/* PLL source is HSI, PLLN=50, PLLM=4 + * PLLP enable, PLLQ enable, PLLR enable + * + * 2 <= PLLP <= 32 + * 2 <= PLLQ <= 8 + * 2 <= PLLR <= 8 + * + * PLLR <= 64MHz + * PLLQ <= 64MHz + * PLLP <= 64MHz + * + * PLL_VCO = (16,000,000 / 2) * 32 = 256 MHz + * + * PLLP = PLL_VCO/4 = 256 MHz / 4 = 64 MHz + * PLLQ = PLL_VCO/4 = 256 MHz / 4 = 64 MHz + * PLLR = PLL_VCO/4 = 256 MHz / 4 = 64 MHz + */ + +#define STM32_PLLCFG_PLLSRC RCC_PLLCFG_PLLSRC_HSI +#define STM32_PLLCFG_PLLCFG (RCC_PLLCFG_PLLPEN | \ + RCC_PLLCFG_PLLQEN | \ + RCC_PLLCFG_PLLREN) + +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(2) +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(64) +#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP(4) +#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(4) +#define STM32_PLLCFG_PLLR RCC_PLLCFG_PLLR(4) + +#define STM32_VCO_FREQUENCY ((STM32_HSI_FREQUENCY / 2) * 64) +#define STM32_PLLP_FREQUENCY (STM32_VCO_FREQUENCY / 4) +#define STM32_PLLQ_FREQUENCY (STM32_VCO_FREQUENCY / 4) +#define STM32_PLLR_FREQUENCY (STM32_VCO_FREQUENCY / 4) + +/* Use the PLL and set the SYSCLK source to be the PLLR (40MHz) */ + +#define STM32_SYSCLK_SW RCC_CFGR_SW_PLL +#define STM32_SYSCLK_SWS RCC_CFGR_SWS_PLL +#define STM32_SYSCLK_FREQUENCY (STM32_PLLR_FREQUENCY) + +/* AHB clock (HCLK) is SYSCLK (40MHz) */ + +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY + +/* APB1 clock (PCLK1) is HCLK/2 (20MHz) */ + +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd2 +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/2) + +/* ADC1 clock prescaled is SYSCLK (64MHz) / 2 = 32MHz */ + +#define STM32_ADC_CLK_FREQUENCY STM32_SYSCLK_FREQUENCY +#define STM32_RCC_CCIPR_ADCSEL RCC_CCIPR_ADCSEL_SYSCLK +#define STM32_ADC_CFGR2_CKMODE ADC_CFGR2_CKMODE_ADCCLK +#define STM32_ADC_CCR_PRESC ADC_CCR_PRESC_DIV2 + +/* LED definitions **********************************************************/ + +/* The Nucleo G0B1RE board has four LEDs. Three of these are controlled by + * logic on the board and are not available for software control: + * + * LD1 COM: LD1 default status is red. LD1 turns to green to indicate that + * communications are in progress between the PC and the + * ST-LINK/V2-1. + * + * LD2 5V_USB_CHG: Green LED is on when board is powered by 5V source. + * + * LD3 PWR: red LED indicates that the board is powered. + * + * And one can be controlled by software: + * + * User LD4: green LED is a user LED connected to the I/O PA5 of the + * STM32G0B1RE. + * + * If CONFIG_ARCH_LEDS is not defined, then the user can control the LED in + * any way. The following definition is used to access the LED. + */ + +/* LED index values for use with board_userled() */ + +#define BOARD_LED1 0 /* User LD4 */ +#define BOARD_NLEDS 1 + +/* LED bits for use with board_userled_all() */ + +#define BOARD_LED1_BIT (1 << BOARD_LED1) + +/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the LED on board + * the Nucleo G0B1RE. The following definitions describe how NuttX controls + * the LED: + * + * SYMBOL Meaning LED1 state + * ------------------ ----------------------- ---------- + * LED_STARTED NuttX has been started OFF + * LED_HEAPALLOCATE Heap has been allocated OFF + * LED_IRQSENABLED Interrupts enabled OFF + * LED_STACKCREATED Idle stack created ON + * LED_INIRQ In an interrupt No change + * LED_SIGNAL In a signal handler No change + * LED_ASSERTION An assertion failed No change + * LED_PANIC The system has crashed Blinking + * LED_IDLE STM32 is in sleep mode Not used + */ + +#define LED_STARTED 0 +#define LED_HEAPALLOCATE 0 +#define LED_IRQSENABLED 0 +#define LED_STACKCREATED 1 +#define LED_INIRQ 2 +#define LED_SIGNAL 2 +#define LED_ASSERTION 2 +#define LED_PANIC 1 + +/* Button definitions *******************************************************/ + +/* The Nucleo G0B1RE supports two buttons; only one button is controllable + * by software: + * + * B1 USER: user button connected to the I/O PC13 of the MCU. + * B2 RESET: push button connected to NRST is used to RESET the MCU. + */ + +#define BUTTON_USER 0 +#define NUM_BUTTONS 1 + +#define BUTTON_USER_BIT (1 << BUTTON_USER) + +/* Alternate function pin selections ****************************************/ + +/* USART */ + +/* By default the USART2 is connected to STLINK Virtual COM Port: + * USART2_RX - PA3 + * USART2_TX - PA2 + */ + +#define GPIO_USART2_RX (GPIO_USART2_RX_1|GPIO_SPEED_HIGH) /* PA3 */ +#define GPIO_USART2_TX (GPIO_USART2_TX_1|GPIO_SPEED_HIGH) /* PA2 */ + +/* ADC */ + +#define GPIO_ADC1_A0 GPIO_ADC1_IN0_1 +#define GPIO_ADC1_A1 GPIO_ADC1_IN1_1 +#define GPIO_ADC1_A2 GPIO_ADC1_IN4_1 +#define GPIO_ADC1_A3 GPIO_ADC1_IN9_1 + +/* DMA channels *************************************************************/ + +/* ADC */ + +#define ADC1_DMA_CHAN DMAMAP_DMA1_ADC1 + +#endif /* __BOARDS_ARM_STM32F0L0G0_NUCLEO_G0B1RE_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32g0/nucleo-g0b1re/scripts/Make.defs b/boards/arm/stm32g0/nucleo-g0b1re/scripts/Make.defs new file mode 100644 index 0000000000000..5090b0ed9603a --- /dev/null +++ b/boards/arm/stm32g0/nucleo-g0b1re/scripts/Make.defs @@ -0,0 +1,41 @@ +############################################################################ +# boards/arm/stm32g0/nucleo-g0b1re/scripts/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/.config +include $(TOPDIR)/tools/Config.mk +include $(TOPDIR)/arch/arm/src/armv6-m/Toolchain.defs + +LDSCRIPT = ld.script +ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) + +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32g0/nucleo-g0b1re/scripts/ld.script b/boards/arm/stm32g0/nucleo-g0b1re/scripts/ld.script new file mode 100644 index 0000000000000..0010b5241542b --- /dev/null +++ b/boards/arm/stm32g0/nucleo-g0b1re/scripts/ld.script @@ -0,0 +1,115 @@ +/**************************************************************************** + * boards/arm/stm32g0/nucleo-g0b1re/scripts/ld.script + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* The STM32GOB1RE has 512Kb of FLASH beginning at address 0x0800:0000. + * 128Kb (with parity) or 144Kb (without parity) of SRAM + * + * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 + * where the code expects to begin execution by jumping to the entry point in + * the 0x0800:0000 address range. + */ + +MEMORY +{ + flash (rx) : ORIGIN = 0x08000000, LENGTH = 512K + sram (rwx) : ORIGIN = 0x20000000, LENGTH = 144K +} + +OUTPUT_ARCH(arm) +EXTERN(_vectors) +ENTRY(_stext) +SECTIONS +{ + .text : { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > flash + + .init_section : ALIGN(4) { + _sinit = ABSOLUTE(.); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) + _einit = ABSOLUTE(.); + } > flash + + .ARM.extab : ALIGN(4) { + *(.ARM.extab*) + } > flash + + .ARM.exidx : ALIGN(4) { + __exidx_start = ABSOLUTE(.); + *(.ARM.exidx*) + __exidx_end = ABSOLUTE(.); + } > flash + + _eronly = ABSOLUTE(.); + + /* The RAM vector table (if present) should lie at the beginning of SRAM */ + + .ram_vectors : { + *(.ram_vectors) + } > sram + + .data : ALIGN(4) { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > sram AT > flash + + .bss : ALIGN(4) { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + _ebss = ABSOLUTE(.); + } > sram + + /* Stabs debugging sections. */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/stm32g0/nucleo-g0b1re/src/CMakeLists.txt b/boards/arm/stm32g0/nucleo-g0b1re/src/CMakeLists.txt new file mode 100644 index 0000000000000..cfb9418e3d3a9 --- /dev/null +++ b/boards/arm/stm32g0/nucleo-g0b1re/src/CMakeLists.txt @@ -0,0 +1,37 @@ +# ############################################################################## +# boards/arm/stm32g0/nucleo-g0b1re/src/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(SRCS stm32_boot.c stm32_bringup.c) + +if(CONFIG_ARCH_LEDS) + list(APPEND SRCS stm32_autoleds.c) +else() + list(APPEND SRCS stm32_userleds.c) +endif() + +if(CONFIG_ARCH_BUTTONS) + list(APPEND SRCS stm32_buttons.c) +endif() + +target_sources(board PRIVATE ${SRCS}) + +set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/ld.script") diff --git a/boards/arm/stm32g0/nucleo-g0b1re/src/Make.defs b/boards/arm/stm32g0/nucleo-g0b1re/src/Make.defs new file mode 100644 index 0000000000000..63f203ffda0e0 --- /dev/null +++ b/boards/arm/stm32g0/nucleo-g0b1re/src/Make.defs @@ -0,0 +1,43 @@ +############################################################################ +# boards/arm/stm32g0/nucleo-g0b1re/src/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +CSRCS = stm32_boot.c stm32_bringup.c + +ifeq ($(CONFIG_ARCH_LEDS),y) +CSRCS += stm32_autoleds.c +else +CSRCS += stm32_userleds.c +endif + +ifeq ($(CONFIG_ARCH_BUTTONS),y) +CSRCS += stm32_buttons.c +endif + +ifeq ($(CONFIG_ADC),y) +CSRCS += stm32_adc.c +endif + +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32f0l0g0/nucleo-g0b1re/src/nucleo-g0b1re.h b/boards/arm/stm32g0/nucleo-g0b1re/src/nucleo-g0b1re.h similarity index 98% rename from boards/arm/stm32f0l0g0/nucleo-g0b1re/src/nucleo-g0b1re.h rename to boards/arm/stm32g0/nucleo-g0b1re/src/nucleo-g0b1re.h index 66318689a0f64..30f9bd80a2ccc 100644 --- a/boards/arm/stm32f0l0g0/nucleo-g0b1re/src/nucleo-g0b1re.h +++ b/boards/arm/stm32g0/nucleo-g0b1re/src/nucleo-g0b1re.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-g0b1re/src/nucleo-g0b1re.h + * boards/arm/stm32g0/nucleo-g0b1re/src/nucleo-g0b1re.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32g0/nucleo-g0b1re/src/stm32_adc.c b/boards/arm/stm32g0/nucleo-g0b1re/src/stm32_adc.c new file mode 100644 index 0000000000000..21ab51079be17 --- /dev/null +++ b/boards/arm/stm32g0/nucleo-g0b1re/src/stm32_adc.c @@ -0,0 +1,137 @@ +/**************************************************************************** + * boards/arm/stm32g0/nucleo-g0b1re/src/stm32_adc.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include + +#include + +#include "stm32.h" + +#if defined(CONFIG_ADC) && defined(CONFIG_STM32_ADC1) + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* The number of ADC channels in the conversion list */ + +#define ADC1_NCHANNELS 4 + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* Identifying number of each ADC channel (even if NCHANNELS is less ) */ + +static const uint8_t g_chanlist1[ADC1_NCHANNELS] = +{ + 0, + 1, + 4, + 9 +}; + +/* Configurations of pins used by each ADC channel */ + +static const uint32_t g_pinlist1[ADC1_NCHANNELS] = +{ + GPIO_ADC1_A0, + GPIO_ADC1_A1, + GPIO_ADC1_A2, + GPIO_ADC1_A3 +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_adc_setup + * + * Description: + * Initialize ADC and register the ADC driver. + * + ****************************************************************************/ + +int stm32_adc_setup(void) +{ + static bool initialized = false; + struct adc_dev_s *adc; + int ret; + int i; + + /* Check if we have already initialized */ + + if (!initialized) + { + /* Configure the pins as analog inputs for the selected channels */ + + for (i = 0; i < ADC1_NCHANNELS; i++) + { + stm32_configgpio(g_pinlist1[i]); + } + + /* Call stm32_adcinitialize() to get an instance of the ADC interface */ + + adc = stm32_adcinitialize(1, g_chanlist1, ADC1_NCHANNELS); + if (adc == NULL) + { + aerr("ERROR: Failed to get ADC interface 1\n"); + return -ENODEV; + } + + /* Register the ADC driver at "/dev/adc0" */ + + ret = adc_register("/dev/adc0", adc); + if (ret < 0) + { + aerr("ERROR: adc_register /dev/adc0 failed: %d\n", ret); + return ret; + } + + initialized = true; + } + + return OK; +} + +#endif diff --git a/boards/arm/stm32g0/nucleo-g0b1re/src/stm32_autoleds.c b/boards/arm/stm32g0/nucleo-g0b1re/src/stm32_autoleds.c new file mode 100644 index 0000000000000..248a297f61745 --- /dev/null +++ b/boards/arm/stm32g0/nucleo-g0b1re/src/stm32_autoleds.c @@ -0,0 +1,81 @@ +/**************************************************************************** + * boards/arm/stm32g0/nucleo-g0b1re/src/stm32_autoleds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include + +#include "stm32_gpio.h" +#include "nucleo-g0b1re.h" + +#include + +#ifdef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_autoled_initialize + ****************************************************************************/ + +void board_autoled_initialize(void) +{ + /* Configure LED1 GPIO for output */ + + stm32_configgpio(GPIO_LED1); +} + +/**************************************************************************** + * Name: board_autoled_on + ****************************************************************************/ + +void board_autoled_on(int led) +{ + if (led == BOARD_LED1) + { + stm32_gpiowrite(GPIO_LED1, true); + } +} + +/**************************************************************************** + * Name: board_autoled_off + ****************************************************************************/ + +void board_autoled_off(int led) +{ + if (led == BOARD_LED1) + { + stm32_gpiowrite(GPIO_LED1, false); + } +} + +#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32g0/nucleo-g0b1re/src/stm32_boot.c b/boards/arm/stm32g0/nucleo-g0b1re/src/stm32_boot.c new file mode 100644 index 0000000000000..231a9256892b7 --- /dev/null +++ b/boards/arm/stm32g0/nucleo-g0b1re/src/stm32_boot.c @@ -0,0 +1,85 @@ +/**************************************************************************** + * boards/arm/stm32g0/nucleo-g0b1re/src/stm32_boot.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include "nucleo-g0b1re.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_boardinitialize + * + * Description: + * All STM32 architectures must provide the following entry point. This + * entry point is called early in the initialization -- after all memory + * has been configured and mapped but before any devices have been + * initialized. + * + ****************************************************************************/ + +void stm32_boardinitialize(void) +{ +#ifdef CONFIG_ARCH_LEDS + /* Configure on-board LEDs if LED support has been selected. */ + + board_autoled_initialize(); +#endif + +#ifdef CONFIG_STM32_SPI + /* Configure SPI chip selects */ + + stm32_spidev_initialize(); +#endif +} + +/**************************************************************************** + * Name: board_late_initialize + * + * Description: + * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_late_initialize(). board_late_initialize() will + * be called immediately after up_initialize() is called and just before + * the initial application is started. This additional initialization + * phase may be used, for example, to initialize board-specific device + * drivers. + * + ****************************************************************************/ + +#ifdef CONFIG_BOARD_LATE_INITIALIZE +void board_late_initialize(void) +{ + /* Perform board-specific initialization */ + + stm32_bringup(); +} +#endif diff --git a/boards/arm/stm32g0/nucleo-g0b1re/src/stm32_bringup.c b/boards/arm/stm32g0/nucleo-g0b1re/src/stm32_bringup.c new file mode 100644 index 0000000000000..d852c55b2a2fd --- /dev/null +++ b/boards/arm/stm32g0/nucleo-g0b1re/src/stm32_bringup.c @@ -0,0 +1,156 @@ +/**************************************************************************** + * boards/arm/stm32g0/nucleo-g0b1re/src/stm32_bringup.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include +#include +#include + +#include "nucleo-g0b1re.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#undef HAVE_LEDS +#undef HAVE_DAC + +#if !defined(CONFIG_ARCH_LEDS) && defined(CONFIG_USERLED_LOWER) +# define HAVE_LEDS 1 +#endif + +#if defined(CONFIG_DAC) +# define HAVE_DAC1 1 +# define HAVE_DAC2 1 +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_bringup + * + * Description: + * Perform architecture-specific initialization + * + * CONFIG_BOARD_LATE_INITIALIZE=y : + * Called from board_late_initialize(). + * + ****************************************************************************/ + +int stm32_bringup(void) +{ + int ret; + +#ifdef HAVE_LEDS + /* Register the LED driver */ + + ret = userled_lower_initialize(LED_DRIVER_PATH); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: userled_lower_initialize() failed: %d\n", + ret); + return ret; + } +#endif + +#ifdef CONFIG_ADC + /* Initialize ADC and register the ADC driver. */ + + ret = stm32_adc_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_adc_setup failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_DAC + /* Initialize DAC and register the DAC driver. */ + + ret = stm32_dac_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_dac_setup failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_COMP + /* Initialize COMP and register the COMP driver. */ + + ret = stm32_comp_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_comp_setup failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_OPAMP + /* Initialize OPAMP and register the OPAMP driver. */ + + ret = stm32_opamp_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_opamp_setup failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_WL_NRF24L01 + ret = stm32_wlinitialize(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to initialize wireless driver: %d\n", + ret); + } +#endif /* CONFIG_WL_NRF24L01 */ + +#ifdef CONFIG_LPWAN_SX127X + ret = stm32_lpwaninitialize(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to initialize wireless driver: %d\n", + ret); + } +#endif /* CONFIG_LPWAN_SX127X */ + +#ifdef CONFIG_CL_MFRC522 + ret = stm32_mfrc522initialize("/dev/rfid0"); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_mfrc522initialize() failed: %d\n", ret); + } +#endif /* CONFIG_CL_MFRC522 */ + + UNUSED(ret); + return OK; +} diff --git a/boards/arm/stm32g0/nucleo-g0b1re/src/stm32_buttons.c b/boards/arm/stm32g0/nucleo-g0b1re/src/stm32_buttons.c new file mode 100644 index 0000000000000..8a389b06aef13 --- /dev/null +++ b/boards/arm/stm32g0/nucleo-g0b1re/src/stm32_buttons.c @@ -0,0 +1,118 @@ +/**************************************************************************** + * boards/arm/stm32g0/nucleo-g0b1re/src/stm32_buttons.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "stm32_gpio.h" +#include "nucleo-g0b1re.h" + +#include + +#ifdef CONFIG_ARCH_BUTTONS + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_button_initialize + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. + * + ****************************************************************************/ + +uint32_t board_button_initialize(void) +{ + /* Configure the single button as an input. NOTE that EXTI interrupts are + * also configured for the pin. + */ + + stm32_configgpio(GPIO_BTN_USER); + return NUM_BUTTONS; +} + +/**************************************************************************** + * Name: board_buttons + ****************************************************************************/ + +uint32_t board_buttons(void) +{ + /* Check that state of each USER button. A LOW value means that the key is + * pressed. + */ + + bool released = stm32_gpioread(GPIO_BTN_USER); + return !released; +} + +/**************************************************************************** + * Button support. + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. + * + * After board_button_initialize() has been called, board_buttons() may be + * called to collect the state of all buttons. board_buttons() returns an + * 32-bit bit set with each bit associated with a button. See the + * BUTTON_*_BIT definitions in board.h for the meaning of each bit. + * + * board_button_irq() may be called to register an interrupt handler that + * will be called when a button is depressed or released. The ID value is a + * button enumeration value that uniquely identifies a button resource. See + * the BUTTON_* definitions in board.h for the meaning of enumeration + * value. + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_IRQBUTTONS +int board_button_irq(int id, xcpt_t irqhandler, void *arg) +{ + int ret = -EINVAL; + + if (id == BUTTON_USER) + { + ret = stm32_gpiosetevent(GPIO_BTN_USER, true, true, true, + irqhandler, arg); + } + + return ret; +} +#endif +#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/stm32g0/stm32g071b-disco/CMakeLists.txt b/boards/arm/stm32g0/stm32g071b-disco/CMakeLists.txt new file mode 100644 index 0000000000000..2b50926e86709 --- /dev/null +++ b/boards/arm/stm32g0/stm32g071b-disco/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32g0/stm32g071b-disco/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/arm/stm32f0l0g0/stm32g071b-disco/Kconfig b/boards/arm/stm32g0/stm32g071b-disco/Kconfig similarity index 100% rename from boards/arm/stm32f0l0g0/stm32g071b-disco/Kconfig rename to boards/arm/stm32g0/stm32g071b-disco/Kconfig diff --git a/boards/arm/stm32g0/stm32g071b-disco/configs/nsh/defconfig b/boards/arm/stm32g0/stm32g071b-disco/configs/nsh/defconfig new file mode 100644 index 0000000000000..0fc28153e81b9 --- /dev/null +++ b/boards/arm/stm32g0/stm32g071b-disco/configs/nsh/defconfig @@ -0,0 +1,57 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_LEDS is not set +# CONFIG_NSH_ARGCAT is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32g071b-disco" +CONFIG_ARCH_BOARD_STM32G071B_DISCO=y +CONFIG_ARCH_CHIP="stm32g0" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32G071RB=y +CONFIG_ARCH_CHIP_STM32G0=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=2796 +CONFIG_BUILTIN=y +CONFIG_DISABLE_ENVIRON=y +CONFIG_DISABLE_MOUNTPOINT=y +CONFIG_DISABLE_MQUEUE=y +CONFIG_DISABLE_POSIX_TIMERS=y +CONFIG_DISABLE_PSEUDOFS_OPERATIONS=y +CONFIG_EXAMPLES_DJOYSTICK=y +CONFIG_EXAMPLES_HELLO=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=1536 +CONFIG_INPUT=y +CONFIG_INPUT_DJOYSTICK=y +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_MM_SMALL=y +CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=64 +CONFIG_NSH_READLINE=y +CONFIG_NUNGET_CHARS=0 +CONFIG_POSIX_SPAWN_DEFAULT_STACKSIZE=1536 +CONFIG_PTHREAD_MUTEX_UNSAFE=y +CONFIG_PTHREAD_STACK_DEFAULT=1536 +CONFIG_RAM_SIZE=32760 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=19 +CONFIG_START_MONTH=5 +CONFIG_START_YEAR=2013 +CONFIG_STDIO_DISABLE_BUFFERING=y +CONFIG_STM32_PWR=y +CONFIG_STM32_USART3=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART3_SERIAL_CONSOLE=y +CONFIG_USERLED=y +CONFIG_USERLED_LOWER=y diff --git a/boards/arm/stm32g0/stm32g071b-disco/configs/oled/defconfig b/boards/arm/stm32g0/stm32g071b-disco/configs/oled/defconfig new file mode 100644 index 0000000000000..37dc8896e4144 --- /dev/null +++ b/boards/arm/stm32g0/stm32g071b-disco/configs/oled/defconfig @@ -0,0 +1,81 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_LEDS is not set +# CONFIG_EXAMPLES_NXLINES_DEFAULT_COLORS is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NX_DISABLE_1BPP is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32g071b-disco" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_STM32G071B_DISCO=y +CONFIG_ARCH_CHIP="stm32g0" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32G071RB=y +CONFIG_ARCH_CHIP_STM32G0=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=2796 +CONFIG_BUILTIN=y +CONFIG_DEBUG_FEATURES=y +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_DISABLE_ENVIRON=y +CONFIG_DISABLE_MOUNTPOINT=y +CONFIG_DISABLE_POSIX_TIMERS=y +CONFIG_DISABLE_PSEUDOFS_OPERATIONS=y +CONFIG_EXAMPLES_DJOYSTICK=y +CONFIG_EXAMPLES_HELLO=y +CONFIG_EXAMPLES_NXHELLO=y +CONFIG_EXAMPLES_NXHELLO_BPP=1 +CONFIG_EXAMPLES_NXLINES=y +CONFIG_EXAMPLES_NXLINES_BORDERWIDTH=1 +CONFIG_EXAMPLES_NXLINES_BPP=1 +CONFIG_EXAMPLES_NXLINES_LINECOLOR=0xff +CONFIG_EXAMPLES_NXLINES_LINEWIDTH=1 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=1536 +CONFIG_INPUT=y +CONFIG_INPUT_DJOYSTICK=y +CONFIG_INTELHEX_BINARY=y +CONFIG_LCD=y +CONFIG_LCD_MAXCONTRAST=255 +CONFIG_LCD_RLANDSCAPE=y +CONFIG_LCD_SSD1306_CUSTOM=y +CONFIG_LINE_MAX=64 +CONFIG_MM_SMALL=y +CONFIG_MQ_MAXMSGSIZE=64 +CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=64 +CONFIG_NSH_READLINE=y +CONFIG_NUNGET_CHARS=0 +CONFIG_NX=y +CONFIG_NXFONTS_DISABLE_1BPP=y +CONFIG_NXFONT_MONO5X8=y +CONFIG_NX_BLOCKING=y +CONFIG_POSIX_SPAWN_DEFAULT_STACKSIZE=1536 +CONFIG_PTHREAD_MUTEX_UNSAFE=y +CONFIG_PTHREAD_STACK_DEFAULT=1536 +CONFIG_RAM_SIZE=32760 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_SPI_CMDDATA=y +CONFIG_START_DAY=19 +CONFIG_START_MONTH=5 +CONFIG_START_YEAR=2013 +CONFIG_STDIO_DISABLE_BUFFERING=y +CONFIG_STM32_PWR=y +CONFIG_STM32_SPI1=y +CONFIG_STM32_SPI1_COMMTYPE=1 +CONFIG_STM32_USART3=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART3_SERIAL_CONSOLE=y +CONFIG_USERLED=y +CONFIG_USERLED_LOWER=y diff --git a/boards/arm/stm32g0/stm32g071b-disco/include/board.h b/boards/arm/stm32g0/stm32g071b-disco/include/board.h new file mode 100644 index 0000000000000..86274e4365e42 --- /dev/null +++ b/boards/arm/stm32g0/stm32g071b-disco/include/board.h @@ -0,0 +1,180 @@ +/**************************************************************************** + * boards/arm/stm32g0/stm32g071b-disco/include/board.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_STM32F0L0G0_STM32G071B_DISCO_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32F0L0G0_STM32G071B_DISCO_INCLUDE_BOARD_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Clocking *****************************************************************/ + +/* HSI - Internal 16 MHz RC Oscillator + * LSI - 32 KHz RC + * HSE - 8 MHz from MCO output of ST-LINK + * LSE - 32.768 kHz + */ + +#define STM32_BOARD_XTAL 8000000ul + +#define STM32_HSI_FREQUENCY 16000000ul +#define STM32_LSI_FREQUENCY 32000 /* Between 30kHz and 60kHz */ +#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL +#define STM32_LSE_FREQUENCY 32768 /* X2 on board */ + +/* Main PLL Configuration. + * + * PLL source is HSI = 16,000,000 + * + * PLL_VCOx = (STM32_HSE_FREQUENCY / PLLM) * PLLN + * Subject to: + * + * 1 <= PLLM <= 8 + * 8 <= PLLN <= 86 + * 4 MHz <= PLL_IN <= 16MHz + * 64 MHz <= PLL_VCO <= 344MHz + * SYSCLK = PLLRCLK = PLL_VCO / PLLR + * + */ + +/* PLL source is HSI, PLLN=50, PLLM=4 + * PLLP enable, PLLQ enable, PLLR enable + * + * 2 <= PLLP <= 32 + * 2 <= PLLQ <= 8 + * 2 <= PLLR <= 8 + * + * PLLR <= 64MHz + * PLLQ <= 128MHz + * PLLP <= 128MHz + * + * PLL_VCO = (16,000,000 / 4) * 50 = 200 MHz + * + * PLLP = PLL_VCO/4 = 200 MHz / 4 = 40 MHz + * PLLQ = PLL_VCO/4 = 200 MHz / 4 = 40 MHz + * PLLR = PLL_VCO/4 = 200 MHz / 4 = 40 MHz + */ + +#define STM32_PLLCFG_PLLSRC RCC_PLLCFG_PLLSRC_HSI +#define STM32_PLLCFG_PLLCFG (RCC_PLLCFG_PLLPEN | \ + RCC_PLLCFG_PLLQEN | \ + RCC_PLLCFG_PLLREN) + +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(4) +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(50) +#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP(4) +#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(4) +#define STM32_PLLCFG_PLLR RCC_PLLCFG_PLLR(4) + +#define STM32_VCO_FREQUENCY ((STM32_HSE_FREQUENCY / 2) * 50) +#define STM32_PLLP_FREQUENCY (STM32_VCO_FREQUENCY / 4) +#define STM32_PLLQ_FREQUENCY (STM32_VCO_FREQUENCY / 4) +#define STM32_PLLR_FREQUENCY (STM32_VCO_FREQUENCY / 4) + +/* Use the PLL and set the SYSCLK source to be the PLLR (40MHz) */ + +#define STM32_SYSCLK_SW RCC_CFGR_SW_PLL +#define STM32_SYSCLK_SWS RCC_CFGR_SWS_PLL +#define STM32_SYSCLK_FREQUENCY (STM32_PLLR_FREQUENCY) +#define STM32_SYSCLK_FREQUENCY (STM32_PLLR_FREQUENCY) + +/* AHB clock (HCLK) is SYSCLK (40MHz) */ + +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY + +/* APB1 clock (PCLK1) is HCLK/2 (20MHz) */ + +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd2 +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/2) + +/* LED definitions **********************************************************/ + +/* LED index values for use with board_userled() */ + +#define BOARD_LEDSINK 0 /* LD4: SINK mode LED */ +#define BOARD_LEDSOURCE 1 /* LD5: SOURCE mode LED */ +#define BOARD_LEDSPY 2 /* LD6: SPY mode LED */ +#define BOARD_LEDCC 3 /* LD7: CC mode LED */ +#define BOARD_NLEDS 4 + +/* LED bits for use with board_userled_all() */ + +#define BOARD_LEDSINK_BIT (1 << BOARD_LEDSINK) +#define BOARD_LEDSOURCE_BIT (1 << BOARD_LEDSOURCE) +#define BOARD_LEDSPY_BIT (1 << BOARD_LEDSPY) +#define BOARD_LEDCC_BIT (1 << BOARD_LEDCC) + +/* Button definitions *******************************************************/ + +/* The STM32G071B-DISO supports one buttons: + * + * B1 RESET: push button connected to NRST is used to RESET the + * STM32G071RB. + * + * and a Joystick: + * + * Joystick center - PC0 + * Joystick down - PC2 + * Joystick left - PC1 + * Joystick right - PC3 + * Joystick up - PC4 + */ + +/* Alternate function pin selections ****************************************/ + +/* USART */ + +/* By default the USART3 is connected to STLINK Virtual COM Port: + * USART3_RX - PC11 + * USART3_TX - PC10 + */ + +#define GPIO_USART3_RX (GPIO_USART3_RX_6|GPIO_SPEED_HIGH) /* PC11 */ +#define GPIO_USART3_TX (GPIO_USART3_TX_6|GPIO_SPEED_HIGH) /* PC10 */ + +/* I2C1 + * I2C1_SCL - PB6 + * I2C1_SDA - PB7 + */ + +#define GPIO_I2C1_SCL (GPIO_I2C1_SCL_2|GPIO_SPEED_LOW) /* PB6 */ +#define GPIO_I2C1_SDA (GPIO_I2C1_SDA_2|GPIO_SPEED_LOW) /* PB7 */ + +/* SPI1 - OLED display + * SPI1_MISO - not used + * SPI1_MOSI - PA2 + * SPI1_SCK - PA1 + */ + +#define GPIO_SPI1_MISO (0) /* Not used - simplex tx */ +#define GPIO_SPI1_MOSI (GPIO_SPI1_MOSI_1|GPIO_SPEED_MEDIUM) /* PA2 */ +#define GPIO_SPI1_SCK (GPIO_SPI1_SCK_1|GPIO_SPEED_MEDIUM) /* PA1 */ + +#endif /* __BOARDS_ARM_STM32F0L0G0_STM32G071B_DISCO_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32g0/stm32g071b-disco/scripts/Make.defs b/boards/arm/stm32g0/stm32g071b-disco/scripts/Make.defs new file mode 100644 index 0000000000000..86966d95270e6 --- /dev/null +++ b/boards/arm/stm32g0/stm32g071b-disco/scripts/Make.defs @@ -0,0 +1,41 @@ +############################################################################ +# boards/arm/stm32g0/stm32g071b-disco/scripts/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/.config +include $(TOPDIR)/tools/Config.mk +include $(TOPDIR)/arch/arm/src/armv6-m/Toolchain.defs + +LDSCRIPT = ld.script +ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) + +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32g0/stm32g071b-disco/scripts/ld.script b/boards/arm/stm32g0/stm32g071b-disco/scripts/ld.script new file mode 100644 index 0000000000000..b39bb951fed56 --- /dev/null +++ b/boards/arm/stm32g0/stm32g071b-disco/scripts/ld.script @@ -0,0 +1,115 @@ +/**************************************************************************** + * boards/arm/stm32g0/stm32g071b-disco/scripts/ld.script + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* The STM32GO71RB has 128Kb of FLASH beginning at address 0x0800:0000. + * 32Kb of SRAM + * + * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 + * where the code expects to begin execution by jumping to the entry point in + * the 0x0800:0000 address range. + */ + +MEMORY +{ + flash (rx) : ORIGIN = 0x08000000, LENGTH = 128K + sram (rwx) : ORIGIN = 0x20000000, LENGTH = 32K +} + +OUTPUT_ARCH(arm) +EXTERN(_vectors) +ENTRY(_stext) +SECTIONS +{ + .text : { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > flash + + .init_section : ALIGN(4) { + _sinit = ABSOLUTE(.); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) + _einit = ABSOLUTE(.); + } > flash + + .ARM.extab : ALIGN(4) { + *(.ARM.extab*) + } > flash + + .ARM.exidx : ALIGN(4) { + __exidx_start = ABSOLUTE(.); + *(.ARM.exidx*) + __exidx_end = ABSOLUTE(.); + } > flash + + _eronly = ABSOLUTE(.); + + /* The RAM vector table (if present) should lie at the beginning of SRAM */ + + .ram_vectors : { + *(.ram_vectors) + } > sram + + .data : ALIGN(4) { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > sram AT > flash + + .bss : ALIGN(4) { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + _ebss = ABSOLUTE(.); + } > sram + + /* Stabs debugging sections. */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/stm32g0/stm32g071b-disco/src/CMakeLists.txt b/boards/arm/stm32g0/stm32g071b-disco/src/CMakeLists.txt new file mode 100644 index 0000000000000..2757b87d9fd47 --- /dev/null +++ b/boards/arm/stm32g0/stm32g071b-disco/src/CMakeLists.txt @@ -0,0 +1,52 @@ +# ############################################################################## +# boards/arm/stm32g0/stm32g071b-disco/src/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(SRCS stm32_boot.c stm32_bringup.c) + +# no auto leds +if(CONFIG_USERLED) + list(APPEND SRCS stm32_userleds.c) +endif() + +if(CONFIG_SPI) + list(APPEND SRCS stm32_spi.c) +endif() + +if(CONFIG_INPUT_DJOYSTICK) + list(APPEND SRCS stm32_djoystick.c) +endif() + +if(CONFIG_LCD_SSD1306) + list(APPEND SRCS stm32_lcd_ssd1306.c) +endif() + +if(CONFIG_SENSORS_INA226) + list(APPEND SRCS stm32_ina226.c) +endif() + +if(CONFIG_DEV_GPIO) + list(APPEND SRCS stm32_gpio.c) +endif() + +target_sources(board PRIVATE ${SRCS}) + +set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/ld.script") diff --git a/boards/arm/stm32g0/stm32g071b-disco/src/Make.defs b/boards/arm/stm32g0/stm32g071b-disco/src/Make.defs new file mode 100644 index 0000000000000..0adb2e6de3efc --- /dev/null +++ b/boards/arm/stm32g0/stm32g071b-disco/src/Make.defs @@ -0,0 +1,54 @@ +############################################################################ +# boards/arm/stm32g0/stm32g071b-disco/src/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +CSRCS = stm32_boot.c stm32_bringup.c + +# no auto leds +ifeq ($(CONFIG_USERLED),y) +CSRCS += stm32_userleds.c +endif + +ifeq ($(CONFIG_SPI),y) +CSRCS += stm32_spi.c +endif + +ifeq ($(CONFIG_INPUT_DJOYSTICK),y) +CSRCS += stm32_djoystick.c +endif + +ifeq ($(CONFIG_LCD_SSD1306),y) +CSRCS += stm32_lcd_ssd1306.c +endif + +ifeq ($(CONFIG_SENSORS_INA226),y) +CSRCS += stm32_ina226.c +endif + +ifeq ($(CONFIG_DEV_GPIO),y) +CSRCS += stm32_gpio.c +endif + +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32g0/stm32g071b-disco/src/stm32_boot.c b/boards/arm/stm32g0/stm32g071b-disco/src/stm32_boot.c new file mode 100644 index 0000000000000..9ceb6f99b0531 --- /dev/null +++ b/boards/arm/stm32g0/stm32g071b-disco/src/stm32_boot.c @@ -0,0 +1,85 @@ +/**************************************************************************** + * boards/arm/stm32g0/stm32g071b-disco/src/stm32_boot.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include "stm32g071b-disco.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_boardinitialize + * + * Description: + * All STM32 architectures must provide the following entry point. This + * entry point is called early in the initialization -- after all memory + * has been configured and mapped but before any devices have been + * initialized. + * + ****************************************************************************/ + +void stm32_boardinitialize(void) +{ +#ifdef CONFIG_ARCH_LEDS + /* Configure on-board LEDs if LED support has been selected. */ + + board_autoled_initialize(); +#endif + +#ifdef CONFIG_STM32_SPI + /* Configure SPI chip selects */ + + stm32_spidev_initialize(); +#endif +} + +/**************************************************************************** + * Name: board_late_initialize + * + * Description: + * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_late_initialize(). board_late_initialize() will + * be called immediately after up_initialize() is called and just before + * the initial application is started. This additional initialization + * phase may be used, for example, to initialize board-specific device + * drivers. + * + ****************************************************************************/ + +#ifdef CONFIG_BOARD_LATE_INITIALIZE +void board_late_initialize(void) +{ + /* Perform board-specific initialization */ + + stm32_bringup(); +} +#endif diff --git a/boards/arm/stm32g0/stm32g071b-disco/src/stm32_bringup.c b/boards/arm/stm32g0/stm32g071b-disco/src/stm32_bringup.c new file mode 100644 index 0000000000000..09ca37d7392ea --- /dev/null +++ b/boards/arm/stm32g0/stm32g071b-disco/src/stm32_bringup.c @@ -0,0 +1,114 @@ +/**************************************************************************** + * boards/arm/stm32g0/stm32g071b-disco/src/stm32_bringup.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include + +#include "stm32g071b-disco.h" + +#ifdef CONFIG_USERLED +# include +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_bringup + * + * Description: + * Perform architecture-specific initialization + * + * CONFIG_BOARD_LATE_INITIALIZE=y : + * Called from board_late_initialize(). + * + ****************************************************************************/ + +int stm32_bringup(void) +{ + int ret; + +#ifdef CONFIG_USERLED + /* Register the LED driver */ + + ret = userled_lower_initialize(LED_DRIVER_PATH); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: userled_lower_initialize() failed: %d\n", + ret); + return ret; + } +#endif + +#ifdef CONFIG_INPUT_DJOYSTICK + /* Initialize and register the joystick driver */ + + ret = stm32_djoy_initialization(); + if (ret != OK) + { + syslog(LOG_ERR, + "ERROR: Failed to register the joystick driver: %d\n", ret); + return ret; + } + + syslog(LOG_INFO, "Successfully registered the joystick driver\n"); +#endif + +#ifdef CONFIG_LCD_SSD1306_SPI + /* NOTE: SSD1315Z is compatible with the SSD1306 driver */ + + board_lcd_initialize(); +#endif + +#ifdef CONFIG_SENSORS_INA226 + /* Initialize and register the INA226 */ + + ret = stm32_ina226_initialization(); + if (ret != OK) + { + syslog(LOG_ERR, + "ERROR: Failed to register the INA226 drivers: %d\n", ret); + return ret; + } +#endif + +#ifdef CONFIG_DEV_GPIO + ret = stm32_gpio_initialize(); + if (ret < 0) + { + syslog(LOG_ERR, "Failed to initialize GPIO Driver: %d\n", ret); + return ret; + } +#endif + + UNUSED(ret); + return OK; +} diff --git a/boards/arm/stm32g0/stm32g071b-disco/src/stm32_djoystick.c b/boards/arm/stm32g0/stm32g071b-disco/src/stm32_djoystick.c new file mode 100644 index 0000000000000..0eae75d75e281 --- /dev/null +++ b/boards/arm/stm32g0/stm32g071b-disco/src/stm32_djoystick.c @@ -0,0 +1,296 @@ +/**************************************************************************** + * boards/arm/stm32g0/stm32g071b-disco/src/stm32_djoystick.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include +#include +#include + +#include "stm32_gpio.h" +#include "stm32g071b-disco.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Number of Joystick discretes */ + +#define DJOY_NGPIOS 5 + +/* Bitset of supported Joystick discretes */ + +#define DJOY_SUPPORTED (DJOY_UP_BIT | DJOY_DOWN_BIT | DJOY_LEFT_BIT | \ + DJOY_RIGHT_BIT | DJOY_BUTTON_SELECT_BIT) + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +static djoy_buttonset_t +djoy_supported(const struct djoy_lowerhalf_s *lower); +static djoy_buttonset_t +djoy_sample(const struct djoy_lowerhalf_s *lower); +static void djoy_enable(const struct djoy_lowerhalf_s *lower, + djoy_buttonset_t press, djoy_buttonset_t release, + djoy_interrupt_t handler, void *arg); + +static void djoy_disable(void); +static int djoy_interrupt(int irq, void *context, void *arg); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* Pin configuration for each stm32g071b-disco joystick "button." + * Index using DJOY_* definitions in include/nuttx/input/djoystick.h. + */ + +static const uint32_t g_joygpio[DJOY_NGPIOS] = +{ + GPIO_JOY_UP, GPIO_JOY_DOWN, GPIO_JOY_LEFT, GPIO_JOY_RIGHT, GPIO_JOY_SEL +}; + +/* Current interrupt handler and argument */ + +static djoy_interrupt_t g_djoyhandler; +static void *g_djoyarg; + +/* This is the discrete joystick lower half driver interface */ + +static const struct djoy_lowerhalf_s g_djoylower = +{ + .dl_supported = djoy_supported, + .dl_sample = djoy_sample, + .dl_enable = djoy_enable, +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: djoy_supported + * + * Description: + * Return the set of buttons supported on the discrete joystick device + * + ****************************************************************************/ + +static djoy_buttonset_t +djoy_supported(const struct djoy_lowerhalf_s *lower) +{ + iinfo("Supported: %02x\n", DJOY_SUPPORTED); + return (djoy_buttonset_t)DJOY_SUPPORTED; +} + +/**************************************************************************** + * Name: djoy_sample + * + * Description: + * Return the current state of all discrete joystick buttons + * + ****************************************************************************/ + +static djoy_buttonset_t djoy_sample(const struct djoy_lowerhalf_s *lower) +{ + djoy_buttonset_t ret = 0; + int i; + bool released; + + /* Read each joystick GPIO value */ + + for (i = 0; i < DJOY_NGPIOS; i++) + { + released = stm32_gpioread(g_joygpio[i]); + if (!released) + { + ret |= (1 << i); + } + } + + iinfo("Retuning: %02x\n", DJOY_SUPPORTED); + return ret; +} + +/**************************************************************************** + * Name: djoy_enable + * + * Description: + * Enable interrupts on the selected set of joystick buttons. And empty + * set will disable all interrupts. + * + ****************************************************************************/ + +static void djoy_enable(const struct djoy_lowerhalf_s *lower, + djoy_buttonset_t press, djoy_buttonset_t release, + djoy_interrupt_t handler, void *arg) +{ + irqstate_t flags; + djoy_buttonset_t either = press | release; + djoy_buttonset_t bit; + bool rising; + bool falling; + int i; + + /* Start with all interrupts disabled */ + + flags = enter_critical_section(); + djoy_disable(); + + iinfo("press: %02x release: %02x handler: %p arg: %p\n", + press, release, handler, arg); + + /* If no events are indicated or if no handler is provided, then this + * must really be a request to disable interrupts. + */ + + if (either && handler) + { + /* Save the new the handler and argument */ + + g_djoyhandler = handler; + g_djoyarg = arg; + + /* Check each GPIO. */ + + for (i = 0; i < DJOY_NGPIOS; i++) + { + /* Enable interrupts on each pin that has either a press or + * release event associated with it. + */ + + bit = (1 << i); + if ((either & bit) != 0) + { + /* Active low so a press corresponds to a falling edge and + * a release corresponds to a rising edge. + */ + + falling = ((press & bit) != 0); + rising = ((release & bit) != 0); + + iinfo("GPIO %d: rising: %d falling: %d\n", + i, rising, falling); + + stm32_gpiosetevent(g_joygpio[i], rising, falling, + true, djoy_interrupt, NULL); + } + } + } + + leave_critical_section(flags); +} + +/**************************************************************************** + * Name: djoy_disable + * + * Description: + * Disable all joystick interrupts + * + ****************************************************************************/ + +static void djoy_disable(void) +{ + irqstate_t flags; + int i; + + /* Disable each joystick interrupt */ + + flags = enter_critical_section(); + for (i = 0; i < DJOY_NGPIOS; i++) + { + stm32_gpiosetevent(g_joygpio[i], false, false, false, NULL, NULL); + } + + leave_critical_section(flags); + + /* Nullify the handler and argument */ + + g_djoyhandler = NULL; + g_djoyarg = NULL; +} + +/**************************************************************************** + * Name: djoy_interrupt + * + * Description: + * Discrete joystick interrupt handler + * + ****************************************************************************/ + +static int djoy_interrupt(int irq, void *context, void *arg) +{ + DEBUGASSERT(g_djoyhandler); + if (g_djoyhandler) + { + g_djoyhandler(&g_djoylower, g_djoyarg); + } + + return OK; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_djoy_initialization + * + * Description: + * Initialize and register the discrete joystick driver + * + ****************************************************************************/ + +int stm32_djoy_initialization(void) +{ + int i; + + /* Configure the GPIO pins as inputs. NOTE: This is unnecessary for + * interrupting pins since it will also be done by stm32_gpiosetevent(). + */ + + for (i = 0; i < DJOY_NGPIOS; i++) + { + stm32_configgpio(g_joygpio[i]); + } + + /* Make sure that all interrupts are disabled */ + + djoy_disable(); + + /* Register the joystick device as /dev/djoy0 */ + + return djoy_register("/dev/djoy0", &g_djoylower); +} diff --git a/boards/arm/stm32g0/stm32g071b-disco/src/stm32_gpio.c b/boards/arm/stm32g0/stm32g071b-disco/src/stm32_gpio.c new file mode 100644 index 0000000000000..edc72b34f92e2 --- /dev/null +++ b/boards/arm/stm32g0/stm32g071b-disco/src/stm32_gpio.c @@ -0,0 +1,322 @@ +/**************************************************************************** + * boards/arm/stm32g0/stm32g071b-disco/src/stm32_gpio.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include + +#include + +#include "stm32_gpio.h" + +#include "stm32g071b-disco.h" + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +struct stm32gpio_dev_s +{ + struct gpio_dev_s gpio; + uint8_t id; +}; + +struct stm32gpint_dev_s +{ + struct stm32gpio_dev_s stm32gpio; + pin_interrupt_t callback; +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +static int gpin_read(struct gpio_dev_s *dev, bool *value); +static int gpout_read(struct gpio_dev_s *dev, bool *value); +static int gpout_write(struct gpio_dev_s *dev, bool value); +static int gpint_read(struct gpio_dev_s *dev, bool *value); +static int gpint_attach(struct gpio_dev_s *dev, + pin_interrupt_t callback); +static int gpint_enable(struct gpio_dev_s *dev, bool enable); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static const struct gpio_operations_s gpin_ops = +{ + .go_read = gpin_read, + .go_write = NULL, + .go_attach = NULL, + .go_enable = NULL, +}; + +static const struct gpio_operations_s gpout_ops = +{ + .go_read = gpout_read, + .go_write = gpout_write, + .go_attach = NULL, + .go_enable = NULL, +}; + +static const struct gpio_operations_s gpint_ops = +{ + .go_read = gpint_read, + .go_write = NULL, + .go_attach = gpint_attach, + .go_enable = gpint_enable, +}; + +#if BOARD_NGPIOIN > 0 +/* This array maps the GPIO pins used as INPUT */ + +static const uint32_t g_gpioinputs[BOARD_NGPIOIN] = +{ + GPIO_IN1, + GPIO_IN2 +}; + +static struct stm32gpio_dev_s g_gpin[BOARD_NGPIOIN]; +#endif + +#if BOARD_NGPIOOUT +/* This array maps the GPIO pins used as OUTPUT */ + +static const uint32_t g_gpiooutputs[BOARD_NGPIOOUT] = +{ + GPIO_OUT1, + GPIO_OUT2, + GPIO_OUT3, + GPIO_OUT4 +}; + +static struct stm32gpio_dev_s g_gpout[BOARD_NGPIOOUT]; +#endif + +#if BOARD_NGPIOINT > 0 +/* This array maps the GPIO pins used as INTERRUPT INPUTS */ + +static const uint32_t g_gpiointinputs[BOARD_NGPIOINT] = +{ + GPIO_INT1, +}; + +static struct stm32gpint_dev_s g_gpint[BOARD_NGPIOINT]; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +static int stm32gpio_interrupt(int irq, void *context, void *arg) +{ + struct stm32gpint_dev_s *stm32gpint = + (struct stm32gpint_dev_s *)arg; + + DEBUGASSERT(stm32gpint != NULL && stm32gpint->callback != NULL); + gpioinfo("Interrupt! callback=%p\n", stm32gpint->callback); + + stm32gpint->callback(&stm32gpint->stm32gpio.gpio, + stm32gpint->stm32gpio.id); + return OK; +} + +static int gpin_read(struct gpio_dev_s *dev, bool *value) +{ + struct stm32gpio_dev_s *stm32gpio = + (struct stm32gpio_dev_s *)dev; + + DEBUGASSERT(stm32gpio != NULL && value != NULL); + DEBUGASSERT(stm32gpio->id < BOARD_NGPIOIN); + gpioinfo("Reading...\n"); + + *value = stm32_gpioread(g_gpioinputs[stm32gpio->id]); + return OK; +} + +static int gpout_read(struct gpio_dev_s *dev, bool *value) +{ + struct stm32gpio_dev_s *stm32gpio = + (struct stm32gpio_dev_s *)dev; + + DEBUGASSERT(stm32gpio != NULL && value != NULL); + DEBUGASSERT(stm32gpio->id < BOARD_NGPIOOUT); + gpioinfo("Reading...\n"); + + *value = stm32_gpioread(g_gpiooutputs[stm32gpio->id]); + return OK; +} + +static int gpout_write(struct gpio_dev_s *dev, bool value) +{ + struct stm32gpio_dev_s *stm32gpio = + (struct stm32gpio_dev_s *)dev; + + DEBUGASSERT(stm32gpio != NULL); + DEBUGASSERT(stm32gpio->id < BOARD_NGPIOOUT); + gpioinfo("Writing %d\n", (int)value); + + stm32_gpiowrite(g_gpiooutputs[stm32gpio->id], value); + return OK; +} + +static int gpint_read(struct gpio_dev_s *dev, bool *value) +{ + struct stm32gpint_dev_s *stm32gpint = + (struct stm32gpint_dev_s *)dev; + + DEBUGASSERT(stm32gpint != NULL && value != NULL); + DEBUGASSERT(stm32gpint->stm32gpio.id < BOARD_NGPIOINT); + gpioinfo("Reading int pin...\n"); + + *value = stm32_gpioread(g_gpiointinputs[stm32gpint->stm32gpio.id]); + return OK; +} + +static int gpint_attach(struct gpio_dev_s *dev, + pin_interrupt_t callback) +{ + struct stm32gpint_dev_s *stm32gpint = + (struct stm32gpint_dev_s *)dev; + + gpioinfo("Attaching the callback\n"); + + /* Make sure the interrupt is disabled */ + + stm32_gpiosetevent(g_gpiointinputs[stm32gpint->stm32gpio.id], false, + false, false, NULL, NULL); + + gpioinfo("Attach %p\n", callback); + stm32gpint->callback = callback; + return OK; +} + +static int gpint_enable(struct gpio_dev_s *dev, bool enable) +{ + struct stm32gpint_dev_s *stm32gpint = + (struct stm32gpint_dev_s *)dev; + + if (enable) + { + if (stm32gpint->callback != NULL) + { + gpioinfo("Enabling the interrupt\n"); + + /* Configure the interrupt for rising edge */ + + stm32_gpiosetevent(g_gpiointinputs[stm32gpint->stm32gpio.id], + true, false, false, stm32gpio_interrupt, + &g_gpint[stm32gpint->stm32gpio.id]); + } + } + else + { + gpioinfo("Disable the interrupt\n"); + stm32_gpiosetevent(g_gpiointinputs[stm32gpint->stm32gpio.id], + false, false, false, NULL, NULL); + } + + return OK; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_gpio_initialize + * + * Description: + * Initialize GPIO drivers for use with /apps/examples/gpio + * + ****************************************************************************/ + +int stm32_gpio_initialize(void) +{ + int i; + int pincount = 0; + +#if BOARD_NGPIOIN > 0 + for (i = 0; i < BOARD_NGPIOIN; i++) + { + /* Setup and register the GPIO pin */ + + g_gpin[i].gpio.gp_pintype = GPIO_INPUT_PIN; + g_gpin[i].gpio.gp_ops = &gpin_ops; + g_gpin[i].id = i; + gpio_pin_register(&g_gpin[i].gpio, pincount); + + /* Configure the pin that will be used as input */ + + stm32_configgpio(g_gpioinputs[i]); + + pincount++; + } +#endif + +#if BOARD_NGPIOOUT > 0 + for (i = 0; i < BOARD_NGPIOOUT; i++) + { + /* Setup and register the GPIO pin */ + + g_gpout[i].gpio.gp_pintype = GPIO_OUTPUT_PIN; + g_gpout[i].gpio.gp_ops = &gpout_ops; + g_gpout[i].id = i; + gpio_pin_register(&g_gpout[i].gpio, pincount); + + /* Configure the pin that will be used as output */ + + stm32_gpiowrite(g_gpiooutputs[i], 0); + stm32_configgpio(g_gpiooutputs[i]); + + pincount++; + } +#endif + +#if BOARD_NGPIOINT > 0 + for (i = 0; i < BOARD_NGPIOINT; i++) + { + /* Setup and register the GPIO pin */ + + g_gpint[i].stm32gpio.gpio.gp_pintype = GPIO_INTERRUPT_PIN; + g_gpint[i].stm32gpio.gpio.gp_ops = &gpint_ops; + g_gpint[i].stm32gpio.id = i; + gpio_pin_register(&g_gpint[i].stm32gpio.gpio, pincount); + + /* Configure the pin that will be used as interrupt input */ + + stm32_configgpio(g_gpiointinputs[i]); + + pincount++; + } +#endif + + return 0; +} diff --git a/boards/arm/stm32f0l0g0/stm32g071b-disco/src/stm32_ina226.c b/boards/arm/stm32g0/stm32g071b-disco/src/stm32_ina226.c similarity index 97% rename from boards/arm/stm32f0l0g0/stm32g071b-disco/src/stm32_ina226.c rename to boards/arm/stm32g0/stm32g071b-disco/src/stm32_ina226.c index 21acd958ab7a2..5655d41731c8a 100644 --- a/boards/arm/stm32f0l0g0/stm32g071b-disco/src/stm32_ina226.c +++ b/boards/arm/stm32g0/stm32g071b-disco/src/stm32_ina226.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/stm32g071b-disco/src/stm32_ina226.c + * boards/arm/stm32g0/stm32g071b-disco/src/stm32_ina226.c * * SPDX-License-Identifier: Apache-2.0 * @@ -39,7 +39,7 @@ * Pre-processor Definitions ****************************************************************************/ -#ifndef CONFIG_STM32F0L0G0_I2C1 +#ifndef CONFIG_STM32_I2C1 # error I2C1 must be enabled! #endif diff --git a/boards/arm/stm32g0/stm32g071b-disco/src/stm32_lcd_ssd1306.c b/boards/arm/stm32g0/stm32g071b-disco/src/stm32_lcd_ssd1306.c new file mode 100644 index 0000000000000..db74b668500e7 --- /dev/null +++ b/boards/arm/stm32g0/stm32g071b-disco/src/stm32_lcd_ssd1306.c @@ -0,0 +1,103 @@ +/**************************************************************************** + * boards/arm/stm32g0/stm32g071b-disco/src/stm32_lcd_ssd1306.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include +#include +#include + +#include "stm32_gpio.h" + +#include "stm32g071b-disco.h" + +#include "stm32_ssd1306.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define OLED_SPI_PORT 1 /* OLED display connected to SPI1 */ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_lcd_initialize + ****************************************************************************/ + +int board_lcd_initialize(void) +{ + int ret; + + /* Configure the OLED GPIOs. This initial configuration is RESET low, + * putting the OLED into reset state. + */ + + stm32_configgpio(GPIO_SSD1306_RST); + stm32_gpiowrite(GPIO_SSD1306_RST, 0); + + /* Wait a bit then release the OLED from the reset state */ + + up_mdelay(20); + stm32_gpiowrite(GPIO_SSD1306_RST, 1); + + /* Initialize OLED */ + + ret = board_ssd1306_initialize(OLED_SPI_PORT); + if (ret < 0) + { + lcderr("ERROR: Failed to initialize SSD1306\n"); + return ret; + } + + return OK; +} + +/**************************************************************************** + * Name: board_lcd_getdev + ****************************************************************************/ + +struct lcd_dev_s *board_lcd_getdev(int devno) +{ + return board_ssd1306_getdev(); +} + +/**************************************************************************** + * Name: board_lcd_uninitialize + ****************************************************************************/ + +void board_lcd_uninitialize(void) +{ + /* TO-FIX */ +} diff --git a/boards/arm/stm32g0/stm32g071b-disco/src/stm32_spi.c b/boards/arm/stm32g0/stm32g071b-disco/src/stm32_spi.c new file mode 100644 index 0000000000000..f75d17e3bd111 --- /dev/null +++ b/boards/arm/stm32g0/stm32g071b-disco/src/stm32_spi.c @@ -0,0 +1,213 @@ +/**************************************************************************** + * boards/arm/stm32g0/stm32g071b-disco/src/stm32_spi.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include + +#include "stm32_gpio.h" +#include "stm32_spi.h" + +#include + +#include "stm32g071b-disco.h" + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/* Global driver instances */ + +#ifdef CONFIG_STM32_SPI1 +struct spi_dev_s *g_spi1; +#endif +#ifdef CONFIG_STM32_SPI2 +struct spi_dev_s *g_spi2; +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_spidev_initialize + * + * Description: + * Called to configure SPI chip select GPIO pins for the Nucleo-F401RE and + * Nucleo-F411RE boards. + * + ****************************************************************************/ + +void weak_function stm32_spidev_initialize(void) +{ +#ifdef CONFIG_STM32_SPI1 + /* Configure SPI-based devices */ + + g_spi1 = stm32_spibus_initialize(1); + if (!g_spi1) + { + spierr("ERROR: FAILED to initialize SPI port 1\n"); + } +#endif + +#ifdef CONFIG_LCD_SSD1306_SPI + stm32_configgpio(GPIO_SSD1306_CS); /* SSD1306 chip select */ + stm32_configgpio(GPIO_SSD1306_CMD); /* SSD1306 data/!command */ +#endif +} + +/**************************************************************************** + * Name: stm32_spi1/2/3select and stm32_spi1/2/3status + * + * Description: + * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status + * must be provided by board-specific logic. They are implementations of + * the select and status methods of the SPI interface defined by struct + * spi_ops_s (see include/nuttx/spi/spi.h). All other methods (including + * stm32_spibus_initialize()) are provided by common STM32 logic. To use + * this common SPI logic on your board: + * + * 1. Provide logic in stm32_boardinitialize() to configure SPI chip select + * pins. + * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() functions + * in your board-specific logic. These functions will perform chip + * selection and status operations using GPIOs in the way your board is + * configured. + * 3. Add a calls to stm32_spibus_initialize() in your low level + * application initialization logic + * 4. The handle returned by stm32_spibus_initialize() may then be used to + * bind the SPI driver to higher level logic (e.g., calling + * mmcsd_spislotinitialize(), for example, will bind the SPI driver to + * the SPI MMC/SD driver). + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_SPI1 +void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, + bool selected) +{ + spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : + "de-assert"); + +#if defined(CONFIG_LCD_SSD1306_SPI) + if (devid == SPIDEV_DISPLAY(0)) + { + stm32_gpiowrite(GPIO_SSD1306_CS, !selected); + } +#endif +} + +uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} +#endif + +#ifdef CONFIG_STM32_SPI2 +void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid, + bool selected) +{ + spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : + "de-assert"); +} + +uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} +#endif + +#ifdef CONFIG_STM32_SPI3 +void stm32_spi3select(struct spi_dev_s *dev, uint32_t devid, + bool selected) +{ + spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : + "de-assert"); +} + +uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} +#endif + +/**************************************************************************** + * Name: stm32_spi1cmddata + * + * Description: + * Set or clear the SD1306 D/C n bit to select data (true) or command + * (false). This function must be provided by platform-specific + * logic. This is an implementation of the cmddata method of the SPI + * interface defined by struct spi_ops_s (see include/nuttx/spi/spi.h). + * + * Input Parameters: + * + * spi - SPI device that controls the bus the device that requires the CMD/ + * DATA selection. + * devid - If there are multiple devices on the bus, this selects which one + * to select cmd or data. NOTE: This design restricts, for example, + * one one SPI display per SPI bus. + * cmd - true: select command; false: select data + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_SPI_CMDDATA +#ifdef CONFIG_STM32_SPI1 +int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) +{ +#if defined(CONFIG_LCD_SSD1306_SPI) + if (devid == SPIDEV_DISPLAY(0)) + { + stm32_gpiowrite(GPIO_SSD1306_CMD, !cmd); + } +#endif + + return OK; +} +#endif + +#ifdef CONFIG_STM32_SPI2 +int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) +{ + return OK; +} +#endif + +#ifdef CONFIG_STM32_SPI3 +int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) +{ + return OK; +} +#endif +#endif /* CONFIG_SPI_CMDDATA */ diff --git a/boards/arm/stm32g0/stm32g071b-disco/src/stm32_userleds.c b/boards/arm/stm32g0/stm32g071b-disco/src/stm32_userleds.c new file mode 100644 index 0000000000000..c1341209dff81 --- /dev/null +++ b/boards/arm/stm32g0/stm32g071b-disco/src/stm32_userleds.c @@ -0,0 +1,92 @@ +/**************************************************************************** + * boards/arm/stm32g0/stm32g071b-disco/src/stm32_userleds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include + +#include "stm32_gpio.h" +#include "stm32g071b-disco.h" + +#include + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* This array maps an LED number to GPIO pin configuration */ + +static uint32_t g_ledcfg[BOARD_NLEDS] = +{ + GPIO_LEDSINK, GPIO_LEDSOURCE, GPIO_LEDSPY, GPIO_LEDCC +}; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_userled_initialize + ****************************************************************************/ + +uint32_t board_userled_initialize(void) +{ + /* Configure LED GPIOs for output */ + + stm32_configgpio(GPIO_LEDSINK); + stm32_configgpio(GPIO_LEDSOURCE); + stm32_configgpio(GPIO_LEDSPY); + stm32_configgpio(GPIO_LEDCC); + + return BOARD_NLEDS; +} + +/**************************************************************************** + * Name: board_userled + ****************************************************************************/ + +void board_userled(int led, bool ledon) +{ + if ((unsigned)led < BOARD_NLEDS) + { + stm32_gpiowrite(g_ledcfg[led], !ledon); + } +} + +/**************************************************************************** + * Name: board_userled_all + ****************************************************************************/ + +void board_userled_all(uint32_t ledset) +{ + stm32_gpiowrite(GPIO_LEDSINK, (ledset & BOARD_LEDSINK_BIT) != 0); + stm32_gpiowrite(GPIO_LEDSOURCE, (ledset & BOARD_LEDSOURCE_BIT) != 0); + stm32_gpiowrite(GPIO_LEDSPY, (ledset & BOARD_LEDSPY_BIT) != 0); + stm32_gpiowrite(GPIO_LEDCC, (ledset & BOARD_LEDCC_BIT) != 0); +} diff --git a/boards/arm/stm32f0l0g0/stm32g071b-disco/src/stm32g071b-disco.h b/boards/arm/stm32g0/stm32g071b-disco/src/stm32g071b-disco.h similarity index 99% rename from boards/arm/stm32f0l0g0/stm32g071b-disco/src/stm32g071b-disco.h rename to boards/arm/stm32g0/stm32g071b-disco/src/stm32g071b-disco.h index f8c27839f17e0..69585d3f7b1cb 100644 --- a/boards/arm/stm32f0l0g0/stm32g071b-disco/src/stm32g071b-disco.h +++ b/boards/arm/stm32g0/stm32g071b-disco/src/stm32g071b-disco.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/stm32g071b-disco/src/stm32g071b-disco.h + * boards/arm/stm32g0/stm32g071b-disco/src/stm32g071b-disco.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32g4/b-g431b-esc1/CMakeLists.txt b/boards/arm/stm32g4/b-g431b-esc1/CMakeLists.txt new file mode 100644 index 0000000000000..c06c5331c111b --- /dev/null +++ b/boards/arm/stm32g4/b-g431b-esc1/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32g4/b-g431b-esc1/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/arm/stm32/b-g431b-esc1/Kconfig b/boards/arm/stm32g4/b-g431b-esc1/Kconfig similarity index 100% rename from boards/arm/stm32/b-g431b-esc1/Kconfig rename to boards/arm/stm32g4/b-g431b-esc1/Kconfig diff --git a/boards/arm/stm32g4/b-g431b-esc1/configs/can/defconfig b/boards/arm/stm32g4/b-g431b-esc1/configs/can/defconfig new file mode 100644 index 0000000000000..87e330cdcf3b0 --- /dev/null +++ b/boards/arm/stm32g4/b-g431b-esc1/configs/can/defconfig @@ -0,0 +1,54 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="b-g431b-esc1" +CONFIG_ARCH_BOARD_B_G431B_ESC1=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32g4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32G431C=y +CONFIG_ARCH_CHIP_STM32G4=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=8499 +CONFIG_BOARD_STM32_BG431BESC1_USE_HSE=y +CONFIG_BUILTIN=y +CONFIG_CAN_ERRORS=y +CONFIG_CAN_EXTID=y +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_EXAMPLES_CAN=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=22528 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=14 +CONFIG_START_MONTH=10 +CONFIG_START_YEAR=2014 +CONFIG_STM32_FDCAN1=y +CONFIG_STM32_FDCAN1_BITRATE=250000 +CONFIG_STM32_FDCAN1_NTSEG1=23 +CONFIG_STM32_FDCAN1_NTSEG2=8 +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32g4/b-g431b-esc1/configs/cansock/defconfig b/boards/arm/stm32g4/b-g431b-esc1/configs/cansock/defconfig new file mode 100644 index 0000000000000..320b24936f0a3 --- /dev/null +++ b/boards/arm/stm32g4/b-g431b-esc1/configs/cansock/defconfig @@ -0,0 +1,62 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NET_ETHERNET is not set +# CONFIG_NET_IPv4 is not set +CONFIG_ALLOW_BSD_COMPONENTS=y +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="b-g431b-esc1" +CONFIG_ARCH_BOARD_B_G431B_ESC1=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32g4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32G431C=y +CONFIG_ARCH_CHIP_STM32G4=y +CONFIG_ARCH_INTERRUPTSTACK=1024 +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=8499 +CONFIG_BOARD_STM32_BG431BESC1_USE_HSE=y +CONFIG_BUILTIN=y +CONFIG_CANUTILS_CANDUMP=y +CONFIG_CANUTILS_CANSEND=y +CONFIG_CANUTILS_LIBCANUTILS=y +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_FS_PROCFS=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_IOB_BUFSIZE=128 +CONFIG_IOB_NBUFFERS=10 +CONFIG_LINE_MAX=64 +CONFIG_NET=y +CONFIG_NETDEV_IFINDEX=y +CONFIG_NETDEV_LATEINIT=y +CONFIG_NET_CAN=y +CONFIG_NET_SOCKOPTS=y +CONFIG_NET_STATISTICS=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_RAM_SIZE=22528 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_LPWORK=y +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=14 +CONFIG_START_MONTH=10 +CONFIG_START_YEAR=2014 +CONFIG_STM32_FDCAN1=y +CONFIG_STM32_FDCAN1_BITRATE=250000 +CONFIG_STM32_FDCAN1_NTSEG1=23 +CONFIG_STM32_FDCAN1_NTSEG2=8 +CONFIG_STM32_FDCAN_SOCKET=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32g4/b-g431b-esc1/configs/foc_b16/defconfig b/boards/arm/stm32g4/b-g431b-esc1/configs/foc_b16/defconfig new file mode 100644 index 0000000000000..d24c0ae4314ba --- /dev/null +++ b/boards/arm/stm32g4/b-g431b-esc1/configs/foc_b16/defconfig @@ -0,0 +1,88 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_DISABLE_MQUEUE is not set +# CONFIG_DISABLE_PTHREAD is not set +CONFIG_ADC=y +CONFIG_ADC_FIFOSIZE=3 +CONFIG_ANALOG=y +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="b-g431b-esc1" +CONFIG_ARCH_BOARD_B_G431B_ESC1=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32g4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32G431C=y +CONFIG_ARCH_CHIP_STM32G4=y +CONFIG_ARCH_INTERRUPTSTACK=1024 +CONFIG_ARCH_IRQBUTTONS=y +CONFIG_ARMV7M_LIBM=y +CONFIG_BOARDCTL=y +CONFIG_BOARD_LOOPSPERMSEC=8499 +CONFIG_BOARD_STM32_BG431BESC1_FOC_POT=y +CONFIG_BOARD_STM32_BG431BESC1_FOC_VBUS=y +CONFIG_BUILTIN=y +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_DEFAULT_SMALL=y +CONFIG_DEFAULT_TASK_STACKSIZE=1024 +CONFIG_EXAMPLES_FOC=y +CONFIG_EXAMPLES_FOC_ADC_MAX=4095 +CONFIG_EXAMPLES_FOC_ADC_VREF=3300 +CONFIG_EXAMPLES_FOC_CONTROL_STACKSIZE=2048 +CONFIG_EXAMPLES_FOC_FIXED16_INST=1 +CONFIG_EXAMPLES_FOC_HAVE_BUTTON=y +CONFIG_EXAMPLES_FOC_NOTIFIER_FREQ=10000 +CONFIG_EXAMPLES_FOC_PWM_FREQ=20000 +CONFIG_EXAMPLES_FOC_RAMP_ACC=200000 +CONFIG_EXAMPLES_FOC_RAMP_DEC=200000 +CONFIG_EXAMPLES_FOC_RAMP_THR=10000 +CONFIG_EXAMPLES_FOC_SETPOINT_ADC=y +CONFIG_EXAMPLES_FOC_VBUS_ADC=y +CONFIG_EXAMPLES_FOC_VBUS_SCALE=10400 +CONFIG_INDUSTRY_FOC=y +CONFIG_INDUSTRY_FOC_FIXED16=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INPUT=y +CONFIG_INPUT_BUTTONS=y +CONFIG_INPUT_BUTTONS_LOWER=y +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBM=y +CONFIG_MOTOR=y +CONFIG_MOTOR_FOC=y +CONFIG_MOTOR_FOC_SHUNTS=2 +CONFIG_MQ_MAXMSGSIZE=5 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_RAM_SIZE=22528 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=14 +CONFIG_START_MONTH=10 +CONFIG_START_YEAR=2014 +CONFIG_STM32_ADC1_ANIOC_TRIGGER=1 +CONFIG_STM32_ADC1_DMA=y +CONFIG_STM32_ADC1_DMA_CFG=1 +CONFIG_STM32_ADC1_INJECTED_CHAN=3 +CONFIG_STM32_DMA1=y +CONFIG_STM32_DMA2=y +CONFIG_STM32_DMAMUX1=y +CONFIG_STM32_FOC=y +CONFIG_STM32_FOC_FOC0=y +CONFIG_STM32_FOC_G4_ADCCHAN0_WORKAROUND=y +CONFIG_STM32_FOC_HAS_PWM_COMPLEMENTARY=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_TIM1_CH1MODE=0 +CONFIG_STM32_TIM1_CH2MODE=0 +CONFIG_STM32_TIM1_CH3MODE=0 +CONFIG_STM32_TIM1_MODE=2 +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART2_SERIAL_CONSOLE=y +CONFIG_USART2_TXDMA=y diff --git a/boards/arm/stm32g4/b-g431b-esc1/configs/foc_f32/defconfig b/boards/arm/stm32g4/b-g431b-esc1/configs/foc_f32/defconfig new file mode 100644 index 0000000000000..b8a719cfc1ca3 --- /dev/null +++ b/boards/arm/stm32g4/b-g431b-esc1/configs/foc_f32/defconfig @@ -0,0 +1,89 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_DISABLE_MQUEUE is not set +# CONFIG_DISABLE_PTHREAD is not set +CONFIG_ADC=y +CONFIG_ADC_FIFOSIZE=3 +CONFIG_ANALOG=y +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="b-g431b-esc1" +CONFIG_ARCH_BOARD_B_G431B_ESC1=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32g4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32G431C=y +CONFIG_ARCH_CHIP_STM32G4=y +CONFIG_ARCH_INTERRUPTSTACK=1024 +CONFIG_ARCH_IRQBUTTONS=y +CONFIG_ARMV7M_LIBM=y +CONFIG_BOARDCTL=y +CONFIG_BOARD_LOOPSPERMSEC=8499 +CONFIG_BOARD_STM32_BG431BESC1_FOC_POT=y +CONFIG_BOARD_STM32_BG431BESC1_FOC_VBUS=y +CONFIG_BUILTIN=y +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_DEFAULT_SMALL=y +CONFIG_DEFAULT_TASK_STACKSIZE=1024 +CONFIG_EXAMPLES_FOC=y +CONFIG_EXAMPLES_FOC_ADC_MAX=4095 +CONFIG_EXAMPLES_FOC_ADC_VREF=3300 +CONFIG_EXAMPLES_FOC_CONTROL_STACKSIZE=2048 +CONFIG_EXAMPLES_FOC_FLOAT_INST=1 +CONFIG_EXAMPLES_FOC_HAVE_BUTTON=y +CONFIG_EXAMPLES_FOC_NOTIFIER_FREQ=10000 +CONFIG_EXAMPLES_FOC_PWM_FREQ=20000 +CONFIG_EXAMPLES_FOC_RAMP_ACC=200000 +CONFIG_EXAMPLES_FOC_RAMP_DEC=200000 +CONFIG_EXAMPLES_FOC_RAMP_THR=10000 +CONFIG_EXAMPLES_FOC_SETPOINT_ADC=y +CONFIG_EXAMPLES_FOC_VBUS_ADC=y +CONFIG_EXAMPLES_FOC_VBUS_SCALE=10400 +CONFIG_INDUSTRY_FOC=y +CONFIG_INDUSTRY_FOC_FLOAT=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INPUT=y +CONFIG_INPUT_BUTTONS=y +CONFIG_INPUT_BUTTONS_LOWER=y +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_FLOATINGPOINT=y +CONFIG_LIBM=y +CONFIG_MOTOR=y +CONFIG_MOTOR_FOC=y +CONFIG_MOTOR_FOC_SHUNTS=2 +CONFIG_MQ_MAXMSGSIZE=5 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_RAM_SIZE=22528 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=14 +CONFIG_START_MONTH=10 +CONFIG_START_YEAR=2014 +CONFIG_STM32_ADC1_ANIOC_TRIGGER=1 +CONFIG_STM32_ADC1_DMA=y +CONFIG_STM32_ADC1_DMA_CFG=1 +CONFIG_STM32_ADC1_INJECTED_CHAN=3 +CONFIG_STM32_DMA1=y +CONFIG_STM32_DMA2=y +CONFIG_STM32_DMAMUX1=y +CONFIG_STM32_FOC=y +CONFIG_STM32_FOC_FOC0=y +CONFIG_STM32_FOC_G4_ADCCHAN0_WORKAROUND=y +CONFIG_STM32_FOC_HAS_PWM_COMPLEMENTARY=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_TIM1_CH1MODE=0 +CONFIG_STM32_TIM1_CH2MODE=0 +CONFIG_STM32_TIM1_CH3MODE=0 +CONFIG_STM32_TIM1_MODE=2 +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART2_SERIAL_CONSOLE=y +CONFIG_USART2_TXDMA=y diff --git a/boards/arm/stm32g4/b-g431b-esc1/configs/nsh/defconfig b/boards/arm/stm32g4/b-g431b-esc1/configs/nsh/defconfig new file mode 100644 index 0000000000000..89e273fb43927 --- /dev/null +++ b/boards/arm/stm32g4/b-g431b-esc1/configs/nsh/defconfig @@ -0,0 +1,49 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="b-g431b-esc1" +CONFIG_ARCH_BOARD_B_G431B_ESC1=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32g4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32G431C=y +CONFIG_ARCH_CHIP_STM32G4=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=8499 +CONFIG_BUILTIN=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_LTO_FULL=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=22528 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=14 +CONFIG_START_MONTH=10 +CONFIG_START_YEAR=2014 +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_TESTING_OSTEST=y +CONFIG_TESTING_OSTEST_STACKSIZE=1024 +CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32g4/b-g431b-esc1/include/board.h b/boards/arm/stm32g4/b-g431b-esc1/include/board.h new file mode 100644 index 0000000000000..006e80f98f3c8 --- /dev/null +++ b/boards/arm/stm32g4/b-g431b-esc1/include/board.h @@ -0,0 +1,380 @@ +/**************************************************************************** + * boards/arm/stm32g4/b-g431b-esc1/include/board.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_STM32_B_G431B_ESC1_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32_B_G431B_ESC1_INCLUDE_BOARD_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Clocking *****************************************************************/ + +#define STM32_BOARD_XTAL 8000000 /* 8MHz */ + +#define STM32_HSI_FREQUENCY 16000000ul /* 16MHz */ +#define STM32_LSI_FREQUENCY 32000 /* 32kHz */ +#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL /* Y2 on board */ +#undef STM32_LSE_FREQUENCY /* Not available on this board */ + +#ifdef CONFIG_BOARD_STM32_BG431BESC1_USE_HSI + +/* Main PLL Configuration. + * + * PLL source is HSI = 16MHz + * PLLN = 85, PLLM = 4, PLLP = 10, PLLQ = 2, PLLR = 2 + * + * f(VCO Clock) = f(PLL Clock Input) x (PLLN / PLLM) + * f(PLL_P) = f(VCO Clock) / PLLP + * f(PLL_Q) = f(VCO Clock) / PLLQ + * f(PLL_R) = f(VCO Clock) / PLLR + * + * Where: + * 8 <= PLLN <= 127 + * 1 <= PLLM <= 16 + * PLLP = 2 through 31 + * PLLQ = 2, 4, 6, or 8 + * PLLR = 2, 4, 6, or 8 + * + * Do not exceed 170MHz on f(PLL_P), f(PLL_Q), or f(PLL_R). + * 64MHz <= f(VCO Clock) <= 344MHz. + * + * Given the above: + * + * f(VCO Clock) = HSI x PLLN / PLLM + * = 16MHz x 85 / 4 + * = 340MHz + * + * PLLPCLK = f(VCO Clock) / PLLP + * = 340MHz / 10 + * = 34MHz + * (May be used for ADC) + * + * PLLQCLK = f(VCO Clock) / PLLQ + * = 340MHz / 2 + * = 170MHz + * (May be used for QUADSPI, FDCAN, SAI1, I2S3. If set to + * 48MHz, may be used for USB, RNG.) + * + * PLLRCLK = f(VCO Clock) / PLLR + * = 340MHz / 2 + * = 170MHz + * (May be used for SYSCLK and most peripherals.) + */ + +#define STM32_PLLCFGR_PLLSRC RCC_PLLCFGR_PLLSRC_HSI +#define STM32_PLLCFGR_PLLCFG (RCC_PLLCFGR_PLLPEN | \ + RCC_PLLCFGR_PLLQEN | \ + RCC_PLLCFGR_PLLREN) + +#define STM32_PLLCFGR_PLLN RCC_PLLCFGR_PLLN(85) +#define STM32_PLLCFGR_PLLM RCC_PLLCFGR_PLLM(4) +#define STM32_PLLCFGR_PLLP RCC_PLLCFGR_PLLPDIV(10) +#define STM32_PLLCFGR_PLLQ RCC_PLLCFGR_PLLQ_2 +#define STM32_PLLCFGR_PLLR RCC_PLLCFGR_PLLR_2 + +#define STM32_VCO_FREQUENCY ((STM32_HSI_FREQUENCY / 4) * 85) +#define STM32_PLLP_FREQUENCY (STM32_VCO_FREQUENCY / 10) +#define STM32_PLLQ_FREQUENCY (STM32_VCO_FREQUENCY / 2) +#define STM32_PLLR_FREQUENCY (STM32_VCO_FREQUENCY / 2) + +/* Use the PLL and set the SYSCLK source to be PLLR (170MHz) */ + +#define STM32_SYSCLK_SW RCC_CFGR_SW_PLL +#define STM32_SYSCLK_SWS RCC_CFGR_SWS_PLL +#define STM32_SYSCLK_FREQUENCY STM32_PLLR_FREQUENCY + +/* AHB clock (HCLK) is SYSCLK (170MHz) */ + +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY + +/* APB1 clock (PCLK1) is HCLK (170MHz) */ + +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK +#define STM32_PCLK1_FREQUENCY STM32_HCLK_FREQUENCY + +/* APB2 clock (PCLK2) is HCLK (170MHz) */ + +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK +#define STM32_PCLK2_FREQUENCY STM32_HCLK_FREQUENCY + +#endif /* CONFIG_BOARD_STM32_BG431BESC1_USE_HSI */ + +#ifdef CONFIG_BOARD_STM32_BG431BESC1_USE_HSE + +/* Main PLL Configuration. + * + * PLL source is HSE = 8MHz + * PLLN = 85, PLLM = 2, PLLP = 10, PLLQ = 2, PLLR = 2 + * + * f(VCO Clock) = f(PLL Clock Input) x (PLLN / PLLM) + * f(PLL_P) = f(VCO Clock) / PLLP + * f(PLL_Q) = f(VCO Clock) / PLLQ + * f(PLL_R) = f(VCO Clock) / PLLR + * + * Where: + * 8 <= PLLN <= 127 + * 1 <= PLLM <= 16 + * PLLP = 2 through 31 + * PLLQ = 2, 4, 6, or 8 + * PLLR = 2, 4, 6, or 8 + * + * Do not exceed 170MHz on f(PLL_P), f(PLL_Q), or f(PLL_R). + * 64MHz <= f(VCO Clock) <= 344MHz. + * + * Given the above: + * + * f(VCO Clock) = HSI x PLLN / PLLM + * = 8MHz x 85 / 2 + * = 340MHz + * + * PLLPCLK = f(VCO Clock) / PLLP + * = 340MHz / 10 + * = 34MHz + * (May be used for ADC) + * + * PLLQCLK = f(VCO Clock) / PLLQ + * = 340MHz / 2 + * = 170MHz + * (May be used for QUADSPI, FDCAN, SAI1, I2S3. If set to + * 48MHz, may be used for USB, RNG.) + * + * PLLRCLK = f(VCO Clock) / PLLR + * = 340MHz / 2 + * = 170MHz + * (May be used for SYSCLK and most peripherals.) + */ + +#define STM32_PLLCFGR_PLLSRC RCC_PLLCFGR_PLLSRC_HSE +#define STM32_PLLCFGR_PLLCFG (RCC_PLLCFGR_PLLPEN | \ + RCC_PLLCFGR_PLLQEN | \ + RCC_PLLCFGR_PLLREN) + +#define STM32_PLLCFGR_PLLN RCC_PLLCFGR_PLLN(85) +#define STM32_PLLCFGR_PLLM RCC_PLLCFGR_PLLM(2) +#define STM32_PLLCFGR_PLLP RCC_PLLCFGR_PLLPDIV(10) +#define STM32_PLLCFGR_PLLQ RCC_PLLCFGR_PLLQ_2 +#define STM32_PLLCFGR_PLLR RCC_PLLCFGR_PLLR_2 + +#define STM32_VCO_FREQUENCY ((STM32_HSI_FREQUENCY / 4) * 85) +#define STM32_PLLP_FREQUENCY (STM32_VCO_FREQUENCY / 10) +#define STM32_PLLQ_FREQUENCY (STM32_VCO_FREQUENCY / 2) +#define STM32_PLLR_FREQUENCY (STM32_VCO_FREQUENCY / 2) + +/* Use the PLL and set the SYSCLK source to be PLLR (170MHz) */ + +#define STM32_SYSCLK_SW RCC_CFGR_SW_PLL +#define STM32_SYSCLK_SWS RCC_CFGR_SWS_PLL +#define STM32_SYSCLK_FREQUENCY STM32_PLLR_FREQUENCY + +/* AHB clock (HCLK) is SYSCLK (170MHz) */ + +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY + +/* APB1 clock (PCLK1) is HCLK (170MHz) */ + +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK +#define STM32_PCLK1_FREQUENCY STM32_HCLK_FREQUENCY + +/* APB2 clock (PCLK2) is HCLK (170MHz) */ + +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK +#define STM32_PCLK2_FREQUENCY STM32_HCLK_FREQUENCY + +#endif /* CONFIG_BOARD_STM32_BG431BESC1_USE_HSE */ + +/* APB2 timers 1, 8, 20 and 15-17 will receive PCLK2. */ + +/* Timers driven from APB2 will be PCLK2 */ + +#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB1_TIM15_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB1_TIM16_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB1_TIM17_CLKIN (STM32_PCLK2_FREQUENCY) + +/* APB1 timers 2-7 will be twice PCLK1 */ + +#define STM32_APB1_TIM2_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (STM32_PCLK1_FREQUENCY) + +/* USB divider -- Divide PLL clock by 1.5 */ + +#define STM32_CFGR_USBPRE 0 + +/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx + * otherwise frequency is 2xAPBx. + */ + +#define BOARD_TIM1_FREQUENCY (STM32_PCLK2_FREQUENCY) +#define BOARD_TIM2_FREQUENCY (STM32_PCLK1_FREQUENCY) +#define BOARD_TIM3_FREQUENCY (STM32_PCLK1_FREQUENCY) +#define BOARD_TIM4_FREQUENCY (STM32_PCLK1_FREQUENCY) +#define BOARD_TIM5_FREQUENCY (STM32_PCLK1_FREQUENCY) +#define BOARD_TIM6_FREQUENCY (STM32_PCLK1_FREQUENCY) +#define BOARD_TIM7_FREQUENCY (STM32_PCLK1_FREQUENCY) +#define BOARD_TIM8_FREQUENCY (STM32_PCLK2_FREQUENCY) +#define BOARD_TIM15_FREQUENCY (STM32_PCLK2_FREQUENCY) +#define BOARD_TIM16_FREQUENCY (STM32_PCLK2_FREQUENCY) +#define BOARD_TIM17_FREQUENCY (STM32_PCLK2_FREQUENCY) +#define BOARD_TIM20_FREQUENCY (STM32_PCLK2_FREQUENCY) + +#ifdef CONFIG_STM32_FDCAN +# ifdef CONFIG_BOARD_STM32_BG431BESC1_USE_HSE +# define STM32_CCIPR_FDCANSRC (RCC_CCIPR_FDCANSEL_HSE) +# define STM32_FDCAN_FREQUENCY (STM32_HSE_FREQUENCY) +# else +# error For now FDCAN supported only if HSE enabled +# endif +#endif + +/* LED definitions **********************************************************/ + +/* The B-G431B-ESC1 has four user LEDs. + * + * If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs in + * any way. The following definitions are used to access individual LEDs. + */ + +/* LED index values for use with board_userled() */ + +#define BOARD_LED1 0 /* User LD2 */ +#define BOARD_NLEDS 1 + +/* LED bits for use with board_userled_all() */ + +#define BOARD_LED1_BIT (1 << BOARD_LED1) + +/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the LED on board + * the Nucleo G431RB. The following definitions describe how NuttX controls + * the LED: + * + * SYMBOL Meaning LED1 state + * ------------------ ----------------------- ---------- + * LED_STARTED NuttX has been started OFF + * LED_HEAPALLOCATE Heap has been allocated OFF + * LED_IRQSENABLED Interrupts enabled OFF + * LED_STACKCREATED Idle stack created ON + * LED_INIRQ In an interrupt No change + * LED_SIGNAL In a signal handler No change + * LED_ASSERTION An assertion failed No change + * LED_PANIC The system has crashed Blinking + * LED_IDLE STM32 is in sleep mode Not used + */ + +#define LED_STARTED 0 +#define LED_HEAPALLOCATE 0 +#define LED_IRQSENABLED 0 +#define LED_STACKCREATED 1 +#define LED_INIRQ 2 +#define LED_SIGNAL 2 +#define LED_ASSERTION 2 +#define LED_PANIC 1 + +/* Button definitions *******************************************************/ + +/* The B-G431B-ESC supports one buttons controllabe by software: + * + * B1 USER: user button connected to the I/O PC10. + */ + +#define BUTTON_USER 0 +#define NUM_BUTTONS 1 + +#define BUTTON_USER_BIT (1 << BUTTON_USER) + +/* Alternate function pin selections ****************************************/ + +/* ADC1 */ + +#define GPIO_ADC1_IN1 GPIO_ADC1_IN1_0 /* PA0 */ +#define GPIO_ADC1_IN2 GPIO_ADC1_IN2_0 /* PA1 */ +#define GPIO_ADC1_IN3 GPIO_ADC1_IN3_0 /* PA2 */ +#define GPIO_ADC1_IN4 GPIO_ADC1_IN4_0 /* PA3 */ +#define GPIO_ADC1_IN5 GPIO_ADC1_IN5_0 /* PB14 */ +#define GPIO_ADC1_IN10 GPIO_ADC1_IN10_0 /* PF0 */ +#define GPIO_ADC1_IN11 GPIO_ADC1_IN11_0 /* PB12 */ +#define GPIO_ADC1_IN12 GPIO_ADC1_IN12_0 /* PB1 */ +#define GPIO_ADC1_IN14 GPIO_ADC1_IN14_0 /* PB11 */ +#define GPIO_ADC1_IN15 GPIO_ADC1_IN15_0 /* PB0 */ + +/* USART2 (ST LINK Virtual Console and J3 pads) */ + +#define GPIO_USART2_TX GPIO_USART2_TX_3 /* PB3 */ +#define GPIO_USART2_RX GPIO_USART2_RX_3 /* PB4 */ + +/* TIM1 configuration *******************************************************/ + +#define GPIO_TIM1_CH1OUT (GPIO_TIM1_CH1OUT_0 | GPIO_SPEED_50MHz) /* TIM1 CH1 - PA8 - U high */ +#define GPIO_TIM1_CH2OUT (GPIO_TIM1_CH2OUT_0 | GPIO_SPEED_50MHz) /* TIM1 CH2 - PA9 - V high */ +#define GPIO_TIM1_CH3OUT (GPIO_TIM1_CH3OUT_0 | GPIO_SPEED_50MHz) /* TIM1 CH3 - PA10 - W high */ +#define GPIO_TIM1_CH1NOUT (GPIO_TIM1_CH1NOUT_4 | GPIO_SPEED_50MHz) /* TIM1 CH1N - PC13 - U low */ +#define GPIO_TIM1_CH2NOUT (GPIO_TIM1_CH2NOUT_1 | GPIO_SPEED_50MHz) /* TIM1 CH2N - PA12 - V low */ +#define GPIO_TIM1_CH3NOUT (GPIO_TIM1_CH3NOUT_3 | GPIO_SPEED_50MHz) /* TIM1 CH3N - PB15 - W low */ + +/* TIM4 QE configuration ****************************************************/ + +#define GPIO_TIM4_CH1IN (GPIO_TIM4_CH1IN_2 | GPIO_SPEED_50MHz) /* TIM4 CH1 - PB6 */ +#define GPIO_TIM4_CH2IN (GPIO_TIM4_CH2IN_2 | GPIO_SPEED_50MHz) /* TIM4 CH2 - PB7 */ + +/* OPAMP configuration ******************************************************/ + +#define GPIO_OPAMP1_VINM0 (GPIO_OPAMP1_VINM0_0) /* PA3 */ +#define GPIO_OPAMP1_VINP0 (GPIO_OPAMP1_VINP0_0) /* PA1 */ +#define GPIO_OPAMP1_VOUT (GPIO_OPAMP1_VOUT_0) /* PA2 */ + +#define GPIO_OPAMP2_VINM0 (GPIO_OPAMP2_VINM0_0) /* PA5 */ +#define GPIO_OPAMP2_VINP0 (GPIO_OPAMP2_VINP0_0) /* PA7 */ +#define GPIO_OPAMP2_VOUT (GPIO_OPAMP2_VOUT_0) /* PA6 */ + +#define GPIO_OPAMP3_VINM0 (GPIO_OPAMP3_VINM0_0) /* PB2 */ +#define GPIO_OPAMP3_VINP0 (GPIO_OPAMP3_VINP0_0) /* PB0 */ +#define GPIO_OPAMP3_VOUT (GPIO_OPAMP3_VOUT_0) /* PB1 */ + +/* CAN configuration ********************************************************/ + +#define GPIO_FDCAN1_RX (GPIO_FDCAN1_RX_1 | GPIO_SPEED_50MHz) /* PA11 */ +#define GPIO_FDCAN1_TX (GPIO_FDCAN1_TX_2 | GPIO_SPEED_50MHz) /* PB9 */ + +/* DMA channels *************************************************************/ + +/* ADC */ + +#define ADC1_DMA_CHAN DMAMAP_DMA12_ADC1_0 /* DMA1 */ + +/* USART2 */ + +#define DMACHAN_USART2_TX DMAMAP_DMA12_USART2TX_0 /* DMA1 */ +#define DMACHAN_USART2_RX DMAMAP_DMA12_USART2RX_0 /* DMA1 */ + +#endif /* __BOARDS_ARM_STM32_B_G431B_ESC1_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32g4/b-g431b-esc1/scripts/Make.defs b/boards/arm/stm32g4/b-g431b-esc1/scripts/Make.defs new file mode 100644 index 0000000000000..79f59cc5dc22e --- /dev/null +++ b/boards/arm/stm32g4/b-g431b-esc1/scripts/Make.defs @@ -0,0 +1,51 @@ +############################################################################ +# boards/arm/stm32g4/b-g431b-esc1/scripts/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/.config +include $(TOPDIR)/tools/Config.mk +include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs + +ifeq ($(CONFIG_STM32_DFU),y) + LDSCRIPT = ld.script.dfu +else + LDSCRIPT = ld.script +endif + +ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) + +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 + +# Embed absolute path to source file in debug information so that Eclipse +# source level debugging won't get confused. See: +# https://stackoverflow.com/questions/1275476/gcc-gdb-how-to-embed-absolute-path-to-source-file-in-debug-information +CFLAGS += -fdebug-prefix-map=..=$(readlink -f ..) diff --git a/boards/arm/stm32g4/b-g431b-esc1/scripts/ld.script b/boards/arm/stm32g4/b-g431b-esc1/scripts/ld.script new file mode 100644 index 0000000000000..6eecf3272e4c6 --- /dev/null +++ b/boards/arm/stm32g4/b-g431b-esc1/scripts/ld.script @@ -0,0 +1,139 @@ +/**************************************************************************** + * boards/arm/stm32g4/b-g431b-esc1/scripts/ld.script + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* The STM32G431CB has 128 KiB of FLASH beginning at address 0x0800:0000. + * + * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 + * where the code expects to begin execution by jumping to the entry point in + * the 0x0800:0000 address range. + * + * The STM32G431CB has a total of 32 KiB of SRAM in three separate areas: + * + * 1) 16 KiB SRAM1 mapped at 0x2000:0000 thru 0x2000:3fff. + * 2) 6 KiB SRAM2 mapped at 0x2000:4000 thru 0x2000:57ff. + * + * CCM SRAM (Routine Booster): + * + * 3) 10 KiB CCM SRAM mapped at 0x1000:0000 thru 0x1000:27ff + * but also aliased at at 0x2000:5800 thru 0x2000:7fff to be contiguous + * with the SRAM1 and SRAM2. + * + * Because SRAM1 and SRAM2 are contiguous, they are treated as one region + * by this logic. + * + * CCM SRAM is also contiguous to SRAM1 and SRAM2, however it is excluded + * from this linker script, to keep it reserved for special uses in code. + * REVISIT: Is this the correct way to handle CCM SRAM? + */ + +MEMORY +{ + flash (rx) : ORIGIN = 0x08000000, LENGTH = 128K + sram (rwx) : ORIGIN = 0x20000000, LENGTH = 22K +} + +OUTPUT_ARCH(arm) +EXTERN(_vectors) +ENTRY(_stext) + +SECTIONS +{ + .text : { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > flash + + .init_section : ALIGN(4) { + _sinit = ABSOLUTE(.); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) + _einit = ABSOLUTE(.); + } > flash + + .ARM.extab : ALIGN(4) { + *(.ARM.extab*) + } > flash + + .ARM.exidx : ALIGN(4) { + __exidx_start = ABSOLUTE(.); + *(.ARM.exidx*) + __exidx_end = ABSOLUTE(.); + } > flash + + .tdata : { + _stdata = ABSOLUTE(.); + *(.tdata .tdata.* .gnu.linkonce.td.*); + _etdata = ABSOLUTE(.); + } > flash + + .tbss : { + _stbss = ABSOLUTE(.); + *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); + _etbss = ABSOLUTE(.); + } > flash + + _eronly = ABSOLUTE(.); + + .data : ALIGN(4) { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > sram AT > flash + + .bss : ALIGN(4) { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + _ebss = ABSOLUTE(.); + } > sram + + /* Stabs debugging sections. */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/stm32/b-g431b-esc1/src/.gitignore b/boards/arm/stm32g4/b-g431b-esc1/src/.gitignore similarity index 100% rename from boards/arm/stm32/b-g431b-esc1/src/.gitignore rename to boards/arm/stm32g4/b-g431b-esc1/src/.gitignore diff --git a/boards/arm/stm32g4/b-g431b-esc1/src/CMakeLists.txt b/boards/arm/stm32g4/b-g431b-esc1/src/CMakeLists.txt new file mode 100644 index 0000000000000..3c5362a634c68 --- /dev/null +++ b/boards/arm/stm32g4/b-g431b-esc1/src/CMakeLists.txt @@ -0,0 +1,50 @@ +# ############################################################################## +# boards/arm/stm32g4/b-g431b-esc1/src/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(SRCS stm32_boot.c stm32_bringup.c) + +if(CONFIG_ARCH_LEDS) + list(APPEND SRCS stm32_autoleds.c) +else() + list(APPEND SRCS stm32_userleds.c) +endif() + +if(CONFIG_ARCH_BUTTONS) + list(APPEND SRCS stm32_buttons.c) +endif() + +if(CONFIG_STM32_FOC) + list(APPEND SRCS stm32_foc.c) +endif() + +if(CONFIG_STM32_FDCAN) + if(CONFIG_STM32_FDCAN_CHARDRIVER) + list(APPEND SRCS stm32_can.c) + endif() + if(CONFIG_STM32_FDCAN_SOCKET) + list(APPEND SRCS stm32_cansock.c) + endif() +endif() + +target_sources(board PRIVATE ${SRCS}) + +set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/ld.script") diff --git a/boards/arm/stm32g4/b-g431b-esc1/src/Make.defs b/boards/arm/stm32g4/b-g431b-esc1/src/Make.defs new file mode 100644 index 0000000000000..04209293fc896 --- /dev/null +++ b/boards/arm/stm32g4/b-g431b-esc1/src/Make.defs @@ -0,0 +1,53 @@ +############################################################################ +# boards/arm/stm32g4/b-g431b-esc1/src/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +ASRCS = +CSRCS = stm32_boot.c stm32_bringup.c + +ifeq ($(CONFIG_ARCH_LEDS),y) +CSRCS += stm32_autoleds.c +else +CSRCS += stm32_userleds.c +endif + +ifeq ($(CONFIG_ARCH_BUTTONS),y) +CSRCS += stm32_buttons.c +endif + +ifeq ($(CONFIG_STM32_FOC),y) +CSRCS += stm32_foc.c +endif + +ifeq ($(CONFIG_STM32_FDCAN),y) +ifeq ($(CONFIG_STM32_FDCAN_CHARDRIVER),y) +CSRCS += stm32_can.c +endif +ifeq ($(CONFIG_STM32_FDCAN_SOCKET),y) +CSRCS += stm32_cansock.c +endif +endif + +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/b-g431b-esc1/src/b-g431b-esc1.h b/boards/arm/stm32g4/b-g431b-esc1/src/b-g431b-esc1.h similarity index 99% rename from boards/arm/stm32/b-g431b-esc1/src/b-g431b-esc1.h rename to boards/arm/stm32g4/b-g431b-esc1/src/b-g431b-esc1.h index 40e7863bd06f5..708c07fdbd26f 100644 --- a/boards/arm/stm32/b-g431b-esc1/src/b-g431b-esc1.h +++ b/boards/arm/stm32g4/b-g431b-esc1/src/b-g431b-esc1.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/b-g431b-esc1/src/b-g431b-esc1.h + * boards/arm/stm32g4/b-g431b-esc1/src/b-g431b-esc1.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32g4/b-g431b-esc1/src/stm32_autoleds.c b/boards/arm/stm32g4/b-g431b-esc1/src/stm32_autoleds.c new file mode 100644 index 0000000000000..23784ea51aa1b --- /dev/null +++ b/boards/arm/stm32g4/b-g431b-esc1/src/stm32_autoleds.c @@ -0,0 +1,80 @@ +/**************************************************************************** + * boards/arm/stm32g4/b-g431b-esc1/src/stm32_autoleds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "stm32.h" +#include "b-g431b-esc1.h" + +#if defined(CONFIG_ARCH_LEDS) + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_autoled_initialize + ****************************************************************************/ + +void board_autoled_initialize(void) +{ + /* Configure LED GPIOs for output */ + + stm32_configgpio(GPIO_LED1); +} + +/**************************************************************************** + * Name: board_autoled_on + ****************************************************************************/ + +void board_autoled_on(int led) +{ + if (led == BOARD_LED1) + { + stm32_gpiowrite(GPIO_LED1, true); + } +} + +/**************************************************************************** + * Name: board_autoled_off + ****************************************************************************/ + +void board_autoled_off(int led) +{ + if (led == BOARD_LED1) + { + stm32_gpiowrite(GPIO_LED1, false); + } +} + +#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32g4/b-g431b-esc1/src/stm32_boot.c b/boards/arm/stm32g4/b-g431b-esc1/src/stm32_boot.c new file mode 100644 index 0000000000000..09acc6b61f631 --- /dev/null +++ b/boards/arm/stm32g4/b-g431b-esc1/src/stm32_boot.c @@ -0,0 +1,95 @@ +/**************************************************************************** + * boards/arm/stm32g4/b-g431b-esc1/src/stm32_boot.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include "b-g431b-esc1.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_boardinitialize + * + * Description: + * All STM32 architectures must provide the following entry point. This + * entry point is called early in the initialization -- after all memory + * has been configured and mapped but before any devices have been + * initialized. + * + ****************************************************************************/ + +void stm32_boardinitialize(void) +{ + /* Configure on-board LEDs if LED support has been selected. */ + +#ifdef CONFIG_ARCH_LEDS + board_autoled_initialize(); +#endif +} + +/**************************************************************************** + * Name: board_late_initialize + * + * Description: + * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_late_initialize(). board_late_initialize() will + * be called immediately after up_initialize() is called and just before + * the initial application is started. This additional initialization + * phase may be used, for example, to initialize board-specific device + * drivers. + * + ****************************************************************************/ + +#ifdef CONFIG_BOARD_LATE_INITIALIZE +void board_late_initialize(void) +{ + /* Perform board-specific initialization */ + + stm32_bringup(); +} +#endif diff --git a/boards/arm/stm32g4/b-g431b-esc1/src/stm32_bringup.c b/boards/arm/stm32g4/b-g431b-esc1/src/stm32_bringup.c new file mode 100644 index 0000000000000..8a4aed406f078 --- /dev/null +++ b/boards/arm/stm32g4/b-g431b-esc1/src/stm32_bringup.c @@ -0,0 +1,185 @@ +/**************************************************************************** + * boards/arm/stm32g4/b-g431b-esc1/src/stm32_bringup.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include + +#include + +#ifdef CONFIG_USERLED +# include +#endif + +#ifdef CONFIG_INPUT_BUTTONS +# include +#endif + +#ifdef CONFIG_SENSORS_QENCODER +# include "board_qencoder.h" +#endif + +#ifdef CONFIG_SENSORS_HALL3PHASE +# include "board_hall3ph.h" +#endif + +#include "b-g431b-esc1.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#undef HAVE_LEDS + +#if !defined(CONFIG_ARCH_LEDS) && defined(CONFIG_USERLED_LOWER) +# define HAVE_LEDS 1 +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_bringup + * + * Description: + * Perform architecture-specific initialization + * + * CONFIG_BOARD_LATE_INITIALIZE=y : + * Called from board_late_initialize(). + * + ****************************************************************************/ + +int stm32_bringup(void) +{ + int ret; + +#ifdef CONFIG_FS_PROCFS + /* Mount the procfs file system */ + + ret = nx_mount(NULL, STM32_PROCFS_MOUNTPOINT, "procfs", 0, NULL); + if (ret < 0) + { + syslog(LOG_ERR, + "ERROR: Failed to mount the PROC filesystem: %d\n", ret); + } +#endif /* CONFIG_FS_PROCFS */ + +#ifdef CONFIG_INPUT_BUTTONS + /* Register the BUTTON driver */ + + ret = btn_lower_initialize("/dev/buttons"); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: btn_lower_initialize() failed: %d\n", ret); + } +#endif + +#if defined(HAVE_LEDS) + /* Register the LED driver */ + + ret = userled_lower_initialize(LED_DRIVER_PATH); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: userled_lower_initialize() failed: %d\n", ret); + return ret; + } +#endif + +#ifdef CONFIG_STM32_FOC + /* Initialize and register the FOC device - must be before ADC setup */ + + ret = stm32_foc_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_foc_setup failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_ADC + /* Initialize ADC and register the ADC driver. */ + + ret = stm32_adc_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_adc_setup failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_SENSORS_QENCODER + /* Initialize and register the qencoder driver - TIM4 */ + + ret = board_qencoder_initialize(0, 4); + if (ret != OK) + { + syslog(LOG_ERR, + "ERROR: Failed to register the qencoder: %d\n", + ret); + return ret; + } +#endif + +#ifdef CONFIG_SENSORS_HALL3PHASE + /* Initialize and register the 3-phase Hall effect sensor driver */ + + ret = board_hall3ph_initialize(0, GPIO_HALL_PHA, GPIO_HALL_PHB, + GPIO_HALL_PHC); + if (ret != OK) + { + syslog(LOG_ERR, + "ERROR: Failed to register the hall : %d\n", + ret); + return ret; + } +#endif + +#ifdef CONFIG_STM32_FDCAN_CHARDRIVER + /* Initialize CAN and register the CAN driver. */ + + ret = stm32_can_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_fdcan_setup failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_STM32_FDCAN_SOCKET + /* Initialize CAN socket interface */ + + ret = stm32_cansock_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_cansock_setup failed: %d\n", ret); + } +#endif + + UNUSED(ret); + return OK; +} diff --git a/boards/arm/stm32g4/b-g431b-esc1/src/stm32_buttons.c b/boards/arm/stm32g4/b-g431b-esc1/src/stm32_buttons.c new file mode 100644 index 0000000000000..ac13875fa0cbe --- /dev/null +++ b/boards/arm/stm32g4/b-g431b-esc1/src/stm32_buttons.c @@ -0,0 +1,113 @@ +/**************************************************************************** + * boards/arm/stm32g4/b-g431b-esc1/src/stm32_buttons.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "stm32.h" +#include "b-g431b-esc1.h" + +#ifdef CONFIG_ARCH_BUTTONS + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_button_initialize + * + * Description: + * board_button_initialize() must be called to initialize button + * resources. After that, board_buttons() may be called to collect the + * current state of all buttons or board_button_irq() may be called to + * register button interrupt handlers. + * + ****************************************************************************/ + +uint32_t board_button_initialize(void) +{ + /* Configure the single button as an input. NOTE that EXTI interrupts are + * also configured for the pin. + */ + + stm32_configgpio(GPIO_BTN_USER); + return NUM_BUTTONS; +} + +/**************************************************************************** + * Name: board_buttons + * + * Description: + * After board_button_initialize() has been called, board_buttons() may be + * called to collect the state of all buttons. board_buttons() returns an + * 32-bit unsigned integer with each bit associated with a button. See the + * BUTTON_*_BIT definitions in board.h for the meaning of each bit. + * + ****************************************************************************/ + +uint32_t board_buttons(void) +{ + /* Check the state of the USER button. A LOW value means that the key is + * pressed. + */ + + return stm32_gpioread(GPIO_BTN_USER) ? 0 : BUTTON_USER_BIT; +} + +/**************************************************************************** + * Name: board_button_irq + * + * Description: + * board_button_irq() may be called to register an interrupt handler that + * will be called when a button is depressed or released. The ID value is + * a button enumeration value that uniquely identifies a button resource. + * See the BUTTON_* definitions in board.h for the meaning of the + * enumeration value. + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_IRQBUTTONS +int board_button_irq(int id, xcpt_t irqhandler, void *arg) +{ + int ret = -EINVAL; + + if (id == BUTTON_USER) + { + ret = stm32_gpiosetevent(GPIO_BTN_USER, true, true, true, irqhandler, + arg); + } + + return ret; +} +#endif + +#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/stm32g4/b-g431b-esc1/src/stm32_can.c b/boards/arm/stm32g4/b-g431b-esc1/src/stm32_can.c new file mode 100644 index 0000000000000..7061003ba9098 --- /dev/null +++ b/boards/arm/stm32g4/b-g431b-esc1/src/stm32_can.c @@ -0,0 +1,105 @@ +/**************************************************************************** + * boards/arm/stm32g4/b-g431b-esc1/src/stm32_can.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32.h" +#include "stm32_fdcan.h" +#include "b-g431b-esc1.h" + +#ifdef CONFIG_CAN + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +#if !defined(CONFIG_STM32_FDCAN1) +# error "No CAN is enable. Please enable at least one CAN device" +#endif + +#ifdef CONFIG_BOARD_STM32_BG431BESC1_CANTERM +# define BG431BESC1_CANTERM (true) +#else +# define BG431BESC1_CANTERM (false) +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_can_setup + * + * Description: + * Initialize CAN and register the CAN device + * + ****************************************************************************/ + +int stm32_can_setup(void) +{ + struct can_dev_s *can; + int ret; + + /* Call stm32_fdcaninitialize() to get an instance of the CAN interface */ + + can = stm32_fdcaninitialize(1); + if (can == NULL) + { + canerr("ERROR: Failed to get CAN interface\n"); + return -ENODEV; + } + + /* Register the CAN driver at "/dev/can0" */ + + ret = can_register("/dev/can0", can); + if (ret < 0) + { + canerr("ERROR: can_register failed: %d\n", ret); + return ret; + } + + /* Configure CAN_TERM pin for output */ + + stm32_configgpio(GPIO_CANTERM); + + /* Set CAN_TERM pin high or low */ + + stm32_gpiowrite(GPIO_CANTERM, BG431BESC1_CANTERM); + + return OK; +} + +#endif /* CONFIG_CAN */ diff --git a/boards/arm/stm32g4/b-g431b-esc1/src/stm32_cansock.c b/boards/arm/stm32g4/b-g431b-esc1/src/stm32_cansock.c new file mode 100644 index 0000000000000..eb0d3acfdf26f --- /dev/null +++ b/boards/arm/stm32g4/b-g431b-esc1/src/stm32_cansock.c @@ -0,0 +1,84 @@ +/**************************************************************************** + * boards/arm/stm32g4/b-g431b-esc1/src/stm32_cansock.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include "stm32_fdcan.h" +#include "b-g431b-esc1.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +#if !defined(CONFIG_STM32_FDCAN1) +# error "No CAN is enable. Please enable at least one CAN device" +#endif + +#ifdef CONFIG_BOARD_STM32_BG431BESC1_CANTERM +# define BG431BESC1_CANTERM (true) +#else +# define BG431BESC1_CANTERM (false) +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_cansock_setup + * + * Description: + * Initialize CAN socket interface + * + ****************************************************************************/ + +int stm32_cansock_setup(void) +{ + int ret; + + /* Call stm32_fdcaninitialize() to get an instance of the FDCAN interface */ + + ret = stm32_fdcansockinitialize(1); + if (ret < 0) + { + canerr("ERROR: Failed to get FDCAN interface %d\n", ret); + return ret; + } + + /* Configure CAN_TERM pin for output */ + + stm32_configgpio(GPIO_CANTERM); + + /* Set CAN_TERM pin high or low */ + + stm32_gpiowrite(GPIO_CANTERM, BG431BESC1_CANTERM); + + return OK; +} diff --git a/boards/arm/stm32g4/b-g431b-esc1/src/stm32_foc.c b/boards/arm/stm32g4/b-g431b-esc1/src/stm32_foc.c new file mode 100644 index 0000000000000..c20d43a435e53 --- /dev/null +++ b/boards/arm/stm32g4/b-g431b-esc1/src/stm32_foc.c @@ -0,0 +1,766 @@ +/**************************************************************************** + * boards/arm/stm32g4/b-g431b-esc1/src/stm32_foc.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include + +#include + +#include "hardware/stm32g4xxxx_opamp.h" + +#if defined(CONFIG_SENSORS_QENCODER) || defined(CONFIG_SENSORS_HALL3PHASE) +# include "hardware/stm32g4xxxx_pwr.h" +#endif + +#include "stm32_foc.h" + +#ifdef CONFIG_SENSORS_QENCODER +# include "stm32_qencoder.h" +#endif + +#include "arm_internal.h" +#include "b-g431b-esc1.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* We don't use phase 2 feedback as it is no connected to ADC1 */ + +#if CONFIG_MOTOR_FOC_SHUNTS != 2 +# error Only 2-shunts configuration is supported +#endif + +/* Configuration specific for L6387ED: + * 1. PWM channels must have positive polarity + * 2. PWM complementary channels must have positive polarity + */ + +#ifndef CONFIG_STM32_FOC_HAS_PWM_COMPLEMENTARY +# error +#endif + +#if CONFIG_STM32_TIM1_CH1POL != 0 +# error +#endif +#if CONFIG_STM32_TIM1_CH2POL != 0 +# error +#endif +#if CONFIG_STM32_TIM1_CH3POL != 0 +# error +#endif +#if CONFIG_STM32_TIM1_CH1NPOL != 0 +# error +#endif +#if CONFIG_STM32_TIM1_CH2NPOL != 0 +# error +#endif +#if CONFIG_STM32_TIM1_CH3NPOL != 0 +# error +#endif + +/* SYSCFG must be enabled for OPAMP */ + +#ifndef CONFIG_STM32_SYSCFG +# error +#endif + +/* Aux ADC needs DMA enabled and workaround for G4 ADC CHAN0 enabled */ + +#ifdef CONFIG_ADC +# ifndef CONFIG_STM32_ADC1_DMA +# error +# endif +# ifndef CONFIG_STM32_FOC_G4_ADCCHAN0_WORKAROUND +# error +# endif +#endif + +/* REVISIT: */ + +#define PWM_DEADTIME (20) +#define PWM_DEADTIME_NS (500) + +/* Devpath for FOC driver */ + +#define FOC_DEVPATH "/dev/foc0" + +/* Board parameters: + * Current shunt resistance = 0.003 + * PGA gain = 16 + * Current sense gain = -9.14 (inverted current) + * Vbus sense gain = 0.0962 + * Vbus min = 7V + * Vbus max = 25V (6S LiPo battery pack) + * Iout max = 40A peak + * IPHASE_RATIO = 1/(R_shunt*gain) = -36.47 + * ADC_REF_VOLTAGE = 3.3 + * ADC_VAL_MAX = 4095 + * ADC_TO_VOLT = ADC_REF_VOLTAGE / ADC_VAL_MAX + * IPHASE_ADC = IPHASE_RATIO * ADC_TO_VOLT = -0.02939 + * VBUS_RATIO = 1/VBUS_gain = 10.4 + */ + +/* OPAMP gain */ + +#define CURRENT_PGA_GAIN 16 + +/* Center-aligned PWM duty cycle limits */ + +#define MAX_DUTY_B16 ftob16(0.95f) + +/* ADC sample time */ + +#define CURRENT_SAMPLE_TIME ADC_SMPR_2p5 +#define VOLTAGE_SAMPLE_TIME ADC_SMPR_2p5 +#define VBUS_SAMPLE_TIME ADC_SMPR_640p5 +#define POT_SAMPLE_TIME ADC_SMPR_640p5 + +/* ADC1 channels used in this example */ + +#define ADC1_INJECTED (CONFIG_MOTOR_FOC_SHUNTS) + +#ifdef CONFIG_BOARD_STM32_BG431BESC1_FOC_VBUS +# define BG431BESC1_FOC_VBUS 1 +#else +# define BG431BESC1_FOC_VBUS 0 +#endif + +#ifdef CONFIG_BOARD_STM32_BG431BESC1_FOC_POT +# define BG431BESC1_FOC_POT 1 +#else +# define BG431BESC1_FOC_POT 0 +#endif + +#define ADC1_REGULAR (BG431BESC1_FOC_VBUS + BG431BESC1_FOC_POT) +#define ADC1_NCHANNELS (ADC1_INJECTED + ADC1_REGULAR) + +#ifdef CONFIG_MOTOR_FOC_BEMF_SENSE +/* ADC2 channels used for BEMF sensing */ + +# define ADC2_INJECTED (CONFIG_MOTOR_FOC_PHASES) +# define ADC2_REGULAR (0) +# define ADC2_NCHANNELS (ADC2_INJECTED + ADC2_REGULAR) +#endif + +/* Check ADC1 configuration */ + +#ifdef CONFIG_STM32_FOC_G4_ADCCHAN0_WORKAROUND +# if ADC1_INJECTED != (CONFIG_STM32_ADC1_INJECTED_CHAN - 1) +# error +# endif +#else +# if ADC1_INJECTED != CONFIG_STM32_ADC1_INJECTED_CHAN +# error +# endif +#endif + +#if CONFIG_STM32_ADC1_RESOLUTION != 0 +# error +#endif + +/* Qenco configuration - only TIM4 */ + +#ifdef CONFIG_SENSORS_QENCODER +# ifndef CONFIG_STM32_TIM4_QE +# error +# endif +# if CONFIG_STM32_TIM4_QEPSC != 0 +# error +# endif +#endif + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/**************************************************************************** + * Private Function Protototypes + ****************************************************************************/ + +static int board_foc_setup(struct foc_dev_s *dev); +static int board_foc_shutdown(struct foc_dev_s *dev); +static int board_foc_calibration(struct foc_dev_s *dev, bool state); +static int board_foc_fault_clear(struct foc_dev_s *dev); +static int board_foc_pwm_start(struct foc_dev_s *dev, bool state); +static int board_foc_current_get(struct foc_dev_s *dev, + int16_t *curr_raw, + foc_current_t *curr); +#ifdef CONFIG_MOTOR_FOC_BEMF_SENSE +static int board_foc_voltage_get(struct foc_dev_s *dev, + int16_t *volt_raw, + foc_voltage_t *volt); +#endif +static int board_foc_info_get(struct foc_dev_s *dev, + struct foc_info_s *info); +#ifdef CONFIG_MOTOR_FOC_TRACE +static int board_foc_trace_init(struct foc_dev_s *dev); +static void board_foc_trace(struct foc_dev_s *dev, int type, bool state); +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* OPAMP configuration: + * - connected with ADC through output pin (OPAINTOEN=0) + * - Current U+ - OPAMP1_VINP0 (PA1) + * - Current U- - OPAMP1_VINP0 (PA3) + * - Current V+ - OPAMP2_VINP0 (PA7) + * - Current V- - OPAMP2_VINP0 (PA5) + * - Current W+ - OPAMP3_VINP0 (PB0) + * - Current W- - OPAMP3_VINP0 (PB2) + * + * ADC configuration: + * - Current Phase V -> ADC1 INJ1 -> ADC1_IN3 (OPAMP1_VOUT/PA2) + * - Current Phase U -> Not used, no ADC1 connection + * - Current Phase W -> ADC1 INJ2 -> ADC1_IN12 (OPAMP3_VOUT/PB12) + * optional: + * - VBUS -> ADC1 REG -> ADC1_IN1 (PA0) + * - POT -> ADC1 REG -> ADC1_IN11 (PB12) + * + * TIM1 PWM configuration: + * - Phase U high -> TIM1_CH1 (PA8) + * - Phase U low -> TIM1_CH1N (PC13) + * - Phase V high -> TIM1_CH2 (PA9) + * - Phase V low -> TIM1_CH2N (PA12) + * - Phase W high -> TIM1_CH3 (PA10) + * - Phase W low -> TIM1_CH3N (PB15) + */ + +static uint8_t g_adc1_chan[] = +{ +#ifdef CONFIG_BOARD_STM32_BG431BESC1_FOC_VBUS + 1, /* ADC1 REG - VBUS */ +#endif +#ifdef CONFIG_BOARD_STM32_BG431BESC1_FOC_POT + 11, /* ADC1 REG - POT */ +#endif + 3, /* ADC1 INJ1 - PHASE 1 */ + 12, /* ADC1 INJ2 - PHASE 3 */ +}; + +static uint32_t g_adc1_pins[] = +{ +#ifdef CONFIG_BOARD_STM32_BG431BESC1_FOC_VBUS + GPIO_ADC1_IN1, +#endif +#ifdef CONFIG_BOARD_STM32_BG431BESC1_FOC_POT + GPIO_ADC1_IN11, +#endif + GPIO_ADC1_IN3, + GPIO_ADC1_IN12, +}; + +/* ADC1 sample time configuration */ + +static adc_channel_t g_adc1_stime[] = +{ +#ifdef CONFIG_BOARD_STM32_BG431BESC1_FOC_VBUS + { + .channel = 1, + .sample_time = VBUS_SAMPLE_TIME + }, +#endif +#ifdef CONFIG_BOARD_STM32_BG431BESC1_FOC_POT + { + .channel = 11, + .sample_time = POT_SAMPLE_TIME + }, +#endif + { + .channel = 3, + .sample_time = CURRENT_SAMPLE_TIME + }, + { + .channel = 12, + .sample_time = CURRENT_SAMPLE_TIME + }, +}; + +/* Board specific ADC configuration for FOC */ + +static struct stm32_foc_adc_s g_adc_cfg = +{ + .chan = g_adc1_chan, + .pins = g_adc1_pins, + .stime = g_adc1_stime, + .nchan = ADC1_NCHANNELS, + .regch = ADC1_REGULAR, + .intf = 1 +}; + +#ifdef CONFIG_MOTOR_FOC_BEMF_SENSE +static uint8_t g_adc2_chan[] = +{ + 17, /* ADC2 INJ1 - PHASE 1 */ + 5, /* ADC2 INJ2 - PHASE 2 */ + 14, /* ADC2 INJ3 - PHASE 3 */ +}; + +static uint32_t g_adc2_pins[] = +{ + GPIO_ADC2_IN17, + GPIO_ADC2_IN5, + GPIO_ADC2_IN14, +}; + +/* ADC2 sample time configuration */ + +static adc_channel_t g_adc2_stime[] = +{ + { + .channel = 17, + .sample_time = VOLTAGE_SAMPLE_TIME + }, + { + .channel = 5, + .sample_time = VOLTAGE_SAMPLE_TIME + }, + { + .channel = 14, + .sample_time = VOLTAGE_SAMPLE_TIME + }, +}; + +/* Board specific ADC configuration for BEMF */ + +static struct stm32_foc_adc_s g_vadc_cfg = +{ + .chan = g_adc2_chan, + .pins = g_adc2_pins, + .stime = g_adc2_stime, + .nchan = ADC2_NCHANNELS, + .regch = ADC2_REGULAR, + .intf = 2 +}; +#endif + +/* Board specific ops */ + +static struct stm32_foc_board_ops_s g_stm32_foc_board_ops = +{ + .setup = board_foc_setup, + .shutdown = board_foc_shutdown, + .calibration = board_foc_calibration, + .fault_clear = board_foc_fault_clear, + .pwm_start = board_foc_pwm_start, + .current_get = board_foc_current_get, +#ifdef CONFIG_MOTOR_FOC_BEMF_SENSE + .voltage_get = board_foc_voltage_get, +#endif + .info_get = board_foc_info_get, +#ifdef CONFIG_MOTOR_FOC_TRACE + .trace_init = board_foc_trace_init, + .trace = board_foc_trace +#endif +}; + +/* Board specific data */ + +static struct stm32_foc_board_data_s g_stm32_foc_board_data = +{ + .adc_cfg = &g_adc_cfg, +#ifdef CONFIG_MOTOR_FOC_BEMF_SENSE + .vadc_cfg = &g_vadc_cfg, +#endif + .pwm_dt = PWM_DEADTIME +}; + +/* Board specific configuration */ + +static struct stm32_foc_board_s g_stm32_foc_board = +{ + .data = &g_stm32_foc_board_data, + .ops = &g_stm32_foc_board_ops, +}; + +/* Global pointer to the upper FOC driver */ + +static struct foc_dev_s *g_foc_dev = NULL; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_foc_setup + ****************************************************************************/ + +static int board_foc_setup(struct foc_dev_s *dev) +{ + uint32_t regval = 0; + + DEBUGASSERT(dev); + + UNUSED(dev); + + /* OPAMP1/2/3 pins: + * OPAMP1_VINM - PA3 (VINM0) + * OPAMP1_VINP - PA1 (VINP0) + * OPAMP2_VINM - PA5 (VINM0) + * OPAMP2_VINP - PA7 (VINP0) + * OPAMP3_VINM - PB2 (VINM0) + * OPAMP3_VINP - PB0 (VINP0) + */ + + /* Configure GPIO */ + + stm32_configgpio(GPIO_OPAMP1_VINM0); + stm32_configgpio(GPIO_OPAMP1_VINP0); + stm32_configgpio(GPIO_OPAMP1_VOUT); + stm32_configgpio(GPIO_OPAMP2_VINM0); + stm32_configgpio(GPIO_OPAMP2_VINP0); + stm32_configgpio(GPIO_OPAMP2_VOUT); + stm32_configgpio(GPIO_OPAMP3_VINM0); + stm32_configgpio(GPIO_OPAMP3_VINP0); + stm32_configgpio(GPIO_OPAMP3_VOUT); +#ifdef CONFIG_MOTOR_FOC_BEMF_SENSE + stm32_configgpio(GPIO_GPIOBEMF); +#endif + + /* Configure OPAMP inputs */ + + regval += (OPAMP_CSR_VPSEL_VINP0 | OPAMP_CSR_VMSEL_PGA); + + /* PGA mode, non-inverting configuration with external bias on VINM0 */ + +#if CURRENT_PGA_GAIN == 16 + regval += ((0b01011 << OPAMP_CSR_PGAGAIN_SHIFT) & OPAMP_CSR_PGAGAIN_MASK); +#else +# error Not supported +#endif + + /* Enable high-speed mode */ + + regval += OPAMP_CSR_OPAHSM; + + /* Write configuration */ + + putreg32(regval, STM32_OPAMP1_CSR); + putreg32(regval, STM32_OPAMP2_CSR); + putreg32(regval, STM32_OPAMP3_CSR); + + /* Enable OPAMPs in separate write */ + + regval += OPAMP_CSR_OPAMPEN; + + putreg32(regval, STM32_OPAMP1_CSR); + putreg32(regval, STM32_OPAMP2_CSR); + putreg32(regval, STM32_OPAMP3_CSR); + +#ifdef CONFIG_MOTOR_FOC_BEMF_SENSE + /* Keep GPIO_BEMF low to create BEMF voltage divider */ + + stm32_gpiowrite(GPIO_GPIOBEMF, false); +#endif + + return OK; +} + +/**************************************************************************** + * Name: board_foc_shutdown + ****************************************************************************/ + +static int board_foc_shutdown(struct foc_dev_s *dev) +{ + DEBUGASSERT(dev); + + UNUSED(dev); + + return OK; +} + +/**************************************************************************** + * Name: board_foc_calibration + ****************************************************************************/ + +static int board_foc_calibration(struct foc_dev_s *dev, bool state) +{ + DEBUGASSERT(dev); + + UNUSED(dev); + + return OK; +} + +/**************************************************************************** + * Name: board_foc_fault_clear + ****************************************************************************/ + +static int board_foc_fault_clear(struct foc_dev_s *dev) +{ + DEBUGASSERT(dev); + + UNUSED(dev); + + return OK; +} + +/**************************************************************************** + * Name: board_foc_pwm_start + ****************************************************************************/ + +static int board_foc_pwm_start(struct foc_dev_s *dev, bool state) +{ + DEBUGASSERT(dev); + + UNUSED(dev); + + return OK; +} + +/**************************************************************************** + * Name: board_foc_current_get + ****************************************************************************/ + +static int board_foc_current_get(struct foc_dev_s *dev, + int16_t *curr_raw, + foc_current_t *curr) +{ + DEBUGASSERT(dev); + DEBUGASSERT(curr_raw); + DEBUGASSERT(curr); + + /* Get currents */ + + curr[0] = curr_raw[0]; + curr[2] = curr_raw[1]; + + /* Phase 2 reconstruction */ + + curr[1] = -(curr_raw[0] + curr_raw[1]); + + return OK; +} + +#ifdef CONFIG_MOTOR_FOC_BEMF_SENSE +/**************************************************************************** + * Name: board_foc_voltage_get + ****************************************************************************/ + +static int board_foc_voltage_get(struct foc_dev_s *dev, + int16_t *volt_raw, + foc_voltage_t *volt) +{ + DEBUGASSERT(dev); + DEBUGASSERT(volt_raw); + DEBUGASSERT(volt); + + /* Get voltages */ + + volt[0] = volt_raw[0]; + volt[1] = volt_raw[1]; + volt[2] = volt_raw[2]; + + return OK; +} +#endif + +/**************************************************************************** + * Name: board_foc_info_get + ****************************************************************************/ + +static int board_foc_info_get(struct foc_dev_s *dev, struct foc_info_s *info) +{ + DEBUGASSERT(dev); + DEBUGASSERT(info); + + UNUSED(dev); + + /* PWM */ + + info->hw_cfg.pwm_dt_ns = PWM_DEADTIME_NS; + info->hw_cfg.pwm_max = MAX_DUTY_B16; + + /* ADC BEMF */ + +#ifdef CONFIG_MOTOR_FOC_BEMF_SENSE + info->hw_cfg.bemf_scale = 0; /* TODO */ +#endif + + /* ADC Current - dynamic current scale not supported */ + + info->hw_cfg.iphase_max = 40000; + info->hw_cfg.iphase_scale = -2939; + + return OK; +} + +#ifdef CONFIG_MOTOR_FOC_TRACE +/**************************************************************************** + * Name: board_foc_trace_init + ****************************************************************************/ + +static int board_foc_trace_init(struct foc_dev_s *dev) +{ + DEBUGASSERT(dev); + + UNUSED(dev); + + /* Not supported */ + + return -1; +} + +/**************************************************************************** + * Name: board_foc_trace + ****************************************************************************/ + +static void board_foc_trace(struct foc_dev_s *dev, int type, bool state) +{ + DEBUGASSERT(dev); + + UNUSED(dev); +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_foc_setup + * + * Description: + * Initialize FOC driver. + * + * Returned Value: + * 0 on success, a negated errno value on failure + * + ****************************************************************************/ + +int stm32_foc_setup(void) +{ + struct foc_dev_s *foc = NULL; + int ret = OK; + + /* Initialize only once */ + + if (g_foc_dev == NULL) + { +#if defined(CONFIG_SENSORS_QENCODER) || defined(CONFIG_SENSORS_HALL3PHASE) + /* Disable USB Type-C and Power Delivery Dead Battery */ + + modifyreg32(STM32_PWR_CR3, 0, PWR_CR3_UCPD1_DBDIS); +#endif + +#if defined(CONFIG_SENSORS_QENCODER) && defined(CONFIG_STM32_QENCODER_INDEX_PIN) + /* Configure encoder index GPIO */ + + ret = stm32_qe_index_init(4, QENCODER_TIM4_INDEX_GPIO); + if (ret < 0) + { + mtrerr("Failed to register encoder index pin %d\n", ret); + ret = -EACCES; + goto errout; + } +#endif + + /* Initialize arch specific FOC lower-half */ + + foc = stm32_foc_initialize(0, &g_stm32_foc_board); + if (foc == NULL) + { + ret = -errno; + mtrerr("Failed to initialize STM32 FOC: %d\n", ret); + goto errout; + } + + DEBUGASSERT(foc->lower); + + /* Register FOC device */ + + ret = foc_register(FOC_DEVPATH, foc); + if (ret < 0) + { + mtrerr("Failed to register FOC device: %d\n", ret); + goto errout; + } + + /* Store pointer to driver */ + + g_foc_dev = foc; + } + +errout: + return ret; +} + +#ifdef CONFIG_ADC +/**************************************************************************** + * Name: stm32_adc_setup + * + * Description: + * Initialize ADC and register the ADC driver. + * + ****************************************************************************/ + +int stm32_adc_setup(void) +{ + struct adc_dev_s *adc = NULL; + int ret = OK; + static bool initialized = false; + + /* Initialize only once */ + + if (initialized == false) + { + if (g_foc_dev == NULL) + { + mtrerr("Failed to get g_foc_dev device\n"); + ret = -EACCES; + goto errout; + } + + /* Register regular channel ADC */ + + adc = stm32_foc_adcget(g_foc_dev); + if (adc == NULL) + { + mtrerr("Failed to get ADC device: %d\n", ret); + goto errout; + } + + ret = adc_register("/dev/adc0", adc); + if (ret < 0) + { + mtrerr("adc_register failed: %d\n", ret); + goto errout; + } + + initialized = true; + } + +errout: + return ret; +} +#endif diff --git a/boards/arm/stm32g4/b-g431b-esc1/src/stm32_userleds.c b/boards/arm/stm32g4/b-g431b-esc1/src/stm32_userleds.c new file mode 100644 index 0000000000000..debdfde7e98d3 --- /dev/null +++ b/boards/arm/stm32g4/b-g431b-esc1/src/stm32_userleds.c @@ -0,0 +1,77 @@ +/**************************************************************************** + * boards/arm/stm32g4/b-g431b-esc1/src/stm32_userleds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include + +#include "stm32.h" +#include "b-g431b-esc1.h" + +#if !defined(CONFIG_ARCH_LEDS) + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_userled_initialize + ****************************************************************************/ + +uint32_t board_userled_initialize(void) +{ + /* Configure LED GPIOs for output */ + + stm32_configgpio(GPIO_LED1); + return BOARD_NLEDS; +} + +/**************************************************************************** + * Name: board_userled + ****************************************************************************/ + +void board_userled(int led, bool ledon) +{ + if (led == BOARD_LED1) + { + stm32_gpiowrite(GPIO_LED1, ledon); + } +} + +/**************************************************************************** + * Name: board_userled_all + ****************************************************************************/ + +void board_userled_all(uint32_t ledset) +{ + stm32_gpiowrite(GPIO_LED1, (ledset & BOARD_LED1_BIT) != 0); +} + +#endif /* !CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32g4/b-g474e-dpow1/CMakeLists.txt b/boards/arm/stm32g4/b-g474e-dpow1/CMakeLists.txt new file mode 100644 index 0000000000000..d5b7816aff587 --- /dev/null +++ b/boards/arm/stm32g4/b-g474e-dpow1/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32g4/b-g474e-dpow1/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/arm/stm32/b-g474e-dpow1/Kconfig b/boards/arm/stm32g4/b-g474e-dpow1/Kconfig similarity index 100% rename from boards/arm/stm32/b-g474e-dpow1/Kconfig rename to boards/arm/stm32g4/b-g474e-dpow1/Kconfig diff --git a/boards/arm/stm32g4/b-g474e-dpow1/configs/buckboost/defconfig b/boards/arm/stm32g4/b-g474e-dpow1/configs/buckboost/defconfig new file mode 100644 index 0000000000000..9bc515466ce87 --- /dev/null +++ b/boards/arm/stm32g4/b-g474e-dpow1/configs/buckboost/defconfig @@ -0,0 +1,90 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_LEDS is not set +CONFIG_ADC=y +CONFIG_ANALOG=y +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="b-g474e-dpow1" +CONFIG_ARCH_BOARD_B_G474E_DPOW1=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32g4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32G474R=y +CONFIG_ARCH_CHIP_STM32G4=y +CONFIG_ARCH_HIPRI_INTERRUPT=y +CONFIG_ARCH_RAMVECTORS=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_DISABLE_ENVIRON=y +CONFIG_DISABLE_MQUEUE=y +CONFIG_DISABLE_POSIX_TIMERS=y +CONFIG_DISABLE_PTHREAD=y +CONFIG_DRIVERS_SMPS=y +CONFIG_EXAMPLES_SMPS=y +CONFIG_EXAMPLES_SMPS_DEVPATH="/dev/smps0" +CONFIG_EXAMPLES_SMPS_IN_VOLTAGE_LIMIT=10000 +CONFIG_EXAMPLES_SMPS_OUT_CURRENT_LIMIT=100 +CONFIG_EXAMPLES_SMPS_OUT_POWER_LIMIT=100 +CONFIG_EXAMPLES_SMPS_OUT_VOLTAGE_DEFAULT=5000 +CONFIG_EXAMPLES_SMPS_OUT_VOLTAGE_LIMIT=10000 +CONFIG_EXAMPLES_SMPS_TIME_DEFAULT=10 +CONFIG_FDCLONE_STDIO=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=1024 +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBDSP=y +CONFIG_LIBM=y +CONFIG_LINE_MAX=64 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=256 +CONFIG_NSH_READLINE=y +CONFIG_POSIX_SPAWN_DEFAULT_STACKSIZE=512 +CONFIG_PTHREAD_STACK_DEFAULT=1024 +CONFIG_PTHREAD_STACK_MIN=1024 +CONFIG_RAM_SIZE=98304 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_SMPS_HAVE_INPUT_VOLTAGE=y +CONFIG_SMPS_HAVE_OUTPUT_VOLTAGE=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_STDIO_BUFFER_SIZE=128 +CONFIG_STM32_ADC1=y +CONFIG_STM32_ADC1_INJECTED_CHAN=2 +CONFIG_STM32_ADC_CHANGE_SAMPLETIME=y +CONFIG_STM32_ADC_LL_OPS=y +CONFIG_STM32_ADC_NOIRQ=y +CONFIG_STM32_CCMEXCLUDE=y +CONFIG_STM32_HRTIM1=y +CONFIG_STM32_HRTIM_ADC1_TRG2=y +CONFIG_STM32_HRTIM_ADC=y +CONFIG_STM32_HRTIM_DEADTIME=y +CONFIG_STM32_HRTIM_DISABLE_CHARDRV=y +CONFIG_STM32_HRTIM_PWM=y +CONFIG_STM32_HRTIM_TIMC=y +CONFIG_STM32_HRTIM_TIMC_DT=y +CONFIG_STM32_HRTIM_TIMC_PWM=y +CONFIG_STM32_HRTIM_TIMC_PWM_CH1=y +CONFIG_STM32_HRTIM_TIMC_PWM_CH2=y +CONFIG_STM32_HRTIM_TIMD=y +CONFIG_STM32_HRTIM_TIMD_DT=y +CONFIG_STM32_HRTIM_TIMD_PWM=y +CONFIG_STM32_HRTIM_TIMD_PWM_CH1=y +CONFIG_STM32_HRTIM_TIMD_PWM_CH2=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_PWR=y +CONFIG_STM32_USART3=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART3_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32g4/b-g474e-dpow1/configs/nsh/defconfig b/boards/arm/stm32g4/b-g474e-dpow1/configs/nsh/defconfig new file mode 100644 index 0000000000000..f2c942f86dbcd --- /dev/null +++ b/boards/arm/stm32g4/b-g474e-dpow1/configs/nsh/defconfig @@ -0,0 +1,42 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_LEDS is not set +# CONFIG_DISABLE_OS_API is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="b-g474e-dpow1" +CONFIG_ARCH_BOARD_B_G474E_DPOW1=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32g4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32G474R=y +CONFIG_ARCH_CHIP_STM32G4=y +CONFIG_ARCH_HIPRI_INTERRUPT=y +CONFIG_ARCH_RAMVECTORS=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_ARMV7M_LIBM=y +CONFIG_ARMV7M_MEMCPY=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_DEBUG_FEATURES=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_LIBM=y +CONFIG_LINE_MAX=64 +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PRIORITY_INHERITANCE=y +CONFIG_RAM_SIZE=98304 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_LPWORK=y +CONFIG_SCHED_WAITPID=y +CONFIG_STM32_USART3=y +CONFIG_SYSTEM_NSH=y +CONFIG_USART3_SERIAL_CONSOLE=y +CONFIG_USERLED=y +CONFIG_USERLED_LOWER=y diff --git a/boards/arm/stm32g4/b-g474e-dpow1/configs/ostest/defconfig b/boards/arm/stm32g4/b-g474e-dpow1/configs/ostest/defconfig new file mode 100644 index 0000000000000..de16a9a8cabcb --- /dev/null +++ b/boards/arm/stm32g4/b-g474e-dpow1/configs/ostest/defconfig @@ -0,0 +1,44 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_LEDS is not set +# CONFIG_DISABLE_OS_API is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="b-g474e-dpow1" +CONFIG_ARCH_BOARD_B_G474E_DPOW1=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32g4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32G474R=y +CONFIG_ARCH_CHIP_STM32G4=y +CONFIG_ARCH_HIPRI_INTERRUPT=y +CONFIG_ARCH_RAMVECTORS=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_ARMV7M_LIBM=y +CONFIG_ARMV7M_MEMCPY=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_DEBUG_FEATURES=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_LIBM=y +CONFIG_LINE_MAX=64 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_RAM_SIZE=98304 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_LPWORK=y +CONFIG_SCHED_WAITPID=y +CONFIG_STM32_USART3=y +CONFIG_SYSTEM_NSH=y +CONFIG_TESTING_OSTEST=y +CONFIG_USART3_SERIAL_CONSOLE=y +CONFIG_USERLED=y +CONFIG_USERLED_LOWER=y diff --git a/boards/arm/stm32g4/b-g474e-dpow1/include/board.h b/boards/arm/stm32g4/b-g474e-dpow1/include/board.h new file mode 100644 index 0000000000000..d06e0188bf6d9 --- /dev/null +++ b/boards/arm/stm32g4/b-g474e-dpow1/include/board.h @@ -0,0 +1,256 @@ +/**************************************************************************** + * boards/arm/stm32g4/b-g474e-dpow1/include/board.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_STM32_B_G474E_DPOW1_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32_B_G474E_DPOW1_INCLUDE_BOARD_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Clocking *****************************************************************/ + +#undef STM32_BOARD_XTAL /* Not installed by default */ + +#define STM32_HSI_FREQUENCY 16000000ul /* 16MHz */ +#define STM32_LSI_FREQUENCY 32000 /* 32kHz */ +#undef STM32_HSE_FREQUENCY /* Not installed by default */ +#undef STM32_LSE_FREQUENCY /* Not available on this board */ + +/* Main PLL Configuration. + * + * PLL source is HSI = 16MHz + * PLLN = 85, PLLM = 4, PLLP = 10, PLLQ = 2, PLLR = 2 + * + * f(VCO Clock) = f(PLL Clock Input) x (PLLN / PLLM) + * f(PLL_P) = f(VCO Clock) / PLLP + * f(PLL_Q) = f(VCO Clock) / PLLQ + * f(PLL_R) = f(VCO Clock) / PLLR + * + * Where: + * 8 <= PLLN <= 127 + * 1 <= PLLM <= 16 + * PLLP = 2 through 31 + * PLLQ = 2, 4, 6, or 8 + * PLLR = 2, 4, 6, or 8 + * + * Do not exceed 170MHz on f(PLL_P), f(PLL_Q), or f(PLL_R). + * 64MHz <= f(VCO Clock) <= 344MHz. + * + * Given the above: + * + * f(VCO Clock) = HSI x PLLN / PLLM + * = 16MHz x 85 / 4 + * = 340MHz + * + * PLLPCLK = f(VCO Clock) / PLLP + * = 340MHz / 10 + * = 34MHz + * (May be used for ADC) + * + * PLLQCLK = f(VCO Clock) / PLLQ + * = 340MHz / 2 + * = 170MHz + * (May be used for QUADSPI, FDCAN, SAI1, I2S3. If set to + * 48MHz, may be used for USB, RNG.) + * + * PLLRCLK = f(VCO Clock) / PLLR + * = 340MHz / 2 + * = 170MHz + * (May be used for SYSCLK and most peripherals.) + */ + +#define STM32_PLLCFGR_PLLSRC RCC_PLLCFGR_PLLSRC_HSI +#define STM32_PLLCFGR_PLLCFG (RCC_PLLCFGR_PLLPEN | \ + RCC_PLLCFGR_PLLQEN | \ + RCC_PLLCFGR_PLLREN) + +#define STM32_PLLCFGR_PLLN RCC_PLLCFGR_PLLN(85) +#define STM32_PLLCFGR_PLLM RCC_PLLCFGR_PLLM(4) +#define STM32_PLLCFGR_PLLP RCC_PLLCFGR_PLLPDIV(10) +#define STM32_PLLCFGR_PLLQ RCC_PLLCFGR_PLLQ_2 +#define STM32_PLLCFGR_PLLR RCC_PLLCFGR_PLLR_2 + +#define STM32_VCO_FREQUENCY ((STM32_HSI_FREQUENCY / 4) * 85) +#define STM32_PLLP_FREQUENCY (STM32_VCO_FREQUENCY / 10) +#define STM32_PLLQ_FREQUENCY (STM32_VCO_FREQUENCY / 2) +#define STM32_PLLR_FREQUENCY (STM32_VCO_FREQUENCY / 2) + +/* Use the PLL and set the SYSCLK source to be PLLR (170MHz) */ + +#define STM32_SYSCLK_SW RCC_CFGR_SW_PLL +#define STM32_SYSCLK_SWS RCC_CFGR_SWS_PLL +#define STM32_SYSCLK_FREQUENCY STM32_PLLR_FREQUENCY + +/* AHB clock (HCLK) is SYSCLK (170MHz) */ + +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY + +/* APB1 clock (PCLK1) is HCLK (170MHz) */ + +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK +#define STM32_PCLK1_FREQUENCY STM32_HCLK_FREQUENCY + +/* APB2 clock (PCLK2) is HCLK (170MHz) */ + +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK +#define STM32_PCLK2_FREQUENCY STM32_HCLK_FREQUENCY + +/* LED definitions **********************************************************/ + +/* The B-G474E-DPOW1 Discovery kit has four user LEDs. + * + * If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs in + * any way. The following definitions are used to access individual LEDs. + */ + +/* LED index values for use with board_userled() */ + +#define BOARD_LED1 0 /* User LD2 (Blue) */ +#define BOARD_LED2 1 /* User LD3 (Orange) */ +#define BOARD_LED3 2 /* User LD4 (Green) */ +#define BOARD_LED4 3 /* User LD5 (Red)*/ +#define BOARD_NLEDS 4 + +/* LED bits for use with board_userled_all() */ + +#define BOARD_LED1_BIT (1 << BOARD_LED1) +#define BOARD_LED2_BIT (1 << BOARD_LED2) +#define BOARD_LED3_BIT (1 << BOARD_LED3) +#define BOARD_LED4_BIT (1 << BOARD_LED4) + +/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the 4 user LEDs + * on the board. The following definitions describe how NuttX controls the + * LEDs: + * + * |--------------------|-------------------------|------------| + * | SYMBOL | Meaning | LED states | + * |--------------------|-------------------------|------------| + * | LED_STARTED | NuttX has been started | 0 0 0 0 | + * | LED_HEAPALLOCATE | Heap has been allocated | 0 0 0 0 | + * | LED_IRQSENABLED | Interrupts enabled | 0 0 0 0 | + * | LED_STACKCREATED | Idle stack created | 1 0 0 0 | + * | LED_INIRQ | In an interrupt | No change | + * | LED_SIGNAL | In a signal handler | No change | + * | LED_ASSERTION | An assertion failed | No change | + * | LED_PANIC | The system has crashed | 0 B 0 0 | + * | LED_IDLE | STM32 is in sleep mode | Not used | + * |--------------------|-------------------------|------------| + * + * LED states legend: + * 0 = off + * 1 = on + * B = blink + */ + +#define LED_STARTED 0 +#define LED_HEAPALLOCATE 0 +#define LED_IRQSENABLED 0 +#define LED_STACKCREATED 1 +#define LED_INIRQ 2 +#define LED_SIGNAL 2 +#define LED_ASSERTION 2 +#define LED_PANIC 3 + +/* Button definitions *******************************************************/ + +/* Alternate function pin selections ****************************************/ + +/* USART3 (ST LINK V3E Virtual Console) */ + +#define GPIO_USART3_TX GPIO_USART3_TX_3 /* PC10 */ +#define GPIO_USART3_RX GPIO_USART3_RX_3 /* PC11 */ + +/* Board configuration for SMPS example: + * PB12 - HRTIM1_CHC1 + * PB13 - HRTIM1_CHC2 + * PB14 - HRTIM1_CHD1 + * PB15 - HRTIM1_CHD2 + * VIN - ADC Channel 2 (PA1) + * VOUT - ADC Channel 4 (PA3) + */ + +#if defined(CONFIG_EXAMPLES_SMPS) + +/* HRTIM configuration ******************************************************/ + +/* Timer C configuration - Buck operations */ + +#define HRTIM_TIMC_PRESCALER HRTIM_PRESCALER_1 +#define HRTIM_TIMC_MODE HRTIM_MODE_CONT +#define HRTIM_TIMC_UPDATE 0 +#define HRTIM_TIMC_RESET 0 + +#define HRTIM_TIMC_CH1_SET HRTIM_OUT_SET_NONE +#define HRTIM_TIMC_CH1_RST HRTIM_OUT_RST_NONE +#define HRTIM_TIMC_CH2_SET HRTIM_OUT_SET_NONE +#define HRTIM_TIMC_CH2_RST HRTIM_OUT_RST_NONE + +#define HRTIM_TIMC_DT_FSLOCK HRTIM_DT_LOCK +#define HRTIM_TIMC_DT_RSLOCK HRTIM_DT_LOCK +#define HRTIM_TIMC_DT_FVLOCK HRTIM_DT_RW +#define HRTIM_TIMC_DT_RVLOCK HRTIM_DT_RW +#define HRTIM_TIMC_DT_FSIGN HRTIM_DT_SIGN_POSITIVE +#define HRTIM_TIMC_DT_RSIGN HRTIM_DT_SIGN_POSITIVE +#define HRTIM_TIMC_DT_PRESCALER HRTIM_DEADTIME_PRESCALER_1 + +/* Timer D configuration - Boost operations */ + +#define HRTIM_TIMD_PRESCALER HRTIM_PRESCALER_1 +#define HRTIM_TIMD_MODE HRTIM_MODE_CONT +#define HRTIM_TIMD_UPDATE 0 +#define HRTIM_TIMD_RESET 0 + +#define HRTIM_TIMD_CH1_SET HRTIM_OUT_SET_NONE +#define HRTIM_TIMD_CH1_RST HRTIM_OUT_RST_NONE +#define HRTIM_TIMD_CH2_SET HRTIM_OUT_SET_NONE +#define HRTIM_TIMD_CH2_RST HRTIM_OUT_RST_NONE + +#define HRTIM_TIMD_DT_FSLOCK HRTIM_DT_LOCK +#define HRTIM_TIMD_DT_RSLOCK HRTIM_DT_LOCK +#define HRTIM_TIMD_DT_FVLOCK HRTIM_DT_RW +#define HRTIM_TIMD_DT_RVLOCK HRTIM_DT_RW +#define HRTIM_TIMD_DT_FSIGN HRTIM_DT_SIGN_POSITIVE +#define HRTIM_TIMD_DT_RSIGN HRTIM_DT_SIGN_POSITIVE +#define HRTIM_TIMD_DT_PRESCALER HRTIM_DEADTIME_PRESCALER_1 + +#define HRTIM_ADC_TRG2 HRTIM_ADCTRG24_CC4 + +/* DMA channels *************************************************************/ + +#endif /* CONFIG_EXAMPLES_SMPS */ + +/* HRTIM */ + +#define GPIO_HRTIM1_CHC1 GPIO_HRTIM1_CHC1_0 +#define GPIO_HRTIM1_CHC2 GPIO_HRTIM1_CHC2_0 +#define GPIO_HRTIM1_CHD1 GPIO_HRTIM1_CHD1_0 +#define GPIO_HRTIM1_CHD2 GPIO_HRTIM1_CHD2_0 + +#endif /* __BOARDS_ARM_STM32_B_G474E_DPOW1_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32g4/b-g474e-dpow1/scripts/Make.defs b/boards/arm/stm32g4/b-g474e-dpow1/scripts/Make.defs new file mode 100644 index 0000000000000..a70ca28ceb57f --- /dev/null +++ b/boards/arm/stm32g4/b-g474e-dpow1/scripts/Make.defs @@ -0,0 +1,51 @@ +############################################################################ +# boards/arm/stm32g4/b-g474e-dpow1/scripts/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/.config +include $(TOPDIR)/tools/Config.mk +include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs + +ifeq ($(CONFIG_STM32_DFU),y) + LDSCRIPT = ld.script.dfu +else + LDSCRIPT = ld.script +endif + +ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) + +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 + +# Embed absolute path to source file in debug information so that Eclipse +# source level debugging won't get confused. See: +# https://stackoverflow.com/questions/1275476/gcc-gdb-how-to-embed-absolute-path-to-source-file-in-debug-information +CFLAGS += -fdebug-prefix-map=..=$(readlink -f ..) diff --git a/boards/arm/stm32g4/b-g474e-dpow1/scripts/ld.script b/boards/arm/stm32g4/b-g474e-dpow1/scripts/ld.script new file mode 100644 index 0000000000000..94b8086bd4903 --- /dev/null +++ b/boards/arm/stm32g4/b-g474e-dpow1/scripts/ld.script @@ -0,0 +1,139 @@ +/**************************************************************************** + * boards/arm/stm32g4/b-g474e-dpow1/scripts/ld.script + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* The STM32G474RE has 512 KiB of FLASH beginning at address 0x0800:0000. + * + * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 + * where the code expects to begin execution by jumping to the entry point in + * the 0x0800:0000 address range. + * + * The STM32G474RE has a total of 128 KiB of SRAM in three separate areas: + * + * 1) 80 KiB SRAM1 mapped at 0x2000:0000 thru 0x2001:3fff. + * 2) 16 KiB SRAM2 mapped at 0x2001:4000 thru 0x2001:7fff. + * + * CCM SRAM (Routine Booster): + * + * 3) 32 KiB CCM SRAM mapped at 0x1000:0000 thru 0x1000:7fff + * but also aliased at at 0x2001:8000 thru 0x2001:ffff to be contiguous + * with the SRAM1 and SRAM2. + * + * Because SRAM1 and SRAM2 are contiguous, they are treated as one region + * by this logic. + * + * CCM SRAM is also contiguous to SRAM1 and SRAM2, however it is excluded + * from this linker script, to keep it reserved for special uses in code. + * REVISIT: Is this the correct way to handle CCM SRAM? + */ + +MEMORY +{ + flash (rx) : ORIGIN = 0x08000000, LENGTH = 512K + sram (rwx) : ORIGIN = 0x20000000, LENGTH = 96K +} + +OUTPUT_ARCH(arm) +EXTERN(_vectors) +ENTRY(_stext) + +SECTIONS +{ + .text : { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > flash + + .init_section : ALIGN(4) { + _sinit = ABSOLUTE(.); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) + _einit = ABSOLUTE(.); + } > flash + + .ARM.extab : ALIGN(4) { + *(.ARM.extab*) + } > flash + + .ARM.exidx : ALIGN(4) { + __exidx_start = ABSOLUTE(.); + *(.ARM.exidx*) + __exidx_end = ABSOLUTE(.); + } > flash + + .tdata : { + _stdata = ABSOLUTE(.); + *(.tdata .tdata.* .gnu.linkonce.td.*); + _etdata = ABSOLUTE(.); + } > flash + + .tbss : { + _stbss = ABSOLUTE(.); + *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); + _etbss = ABSOLUTE(.); + } > flash + + _eronly = ABSOLUTE(.); + + .data : ALIGN(4) { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > sram AT > flash + + .bss : ALIGN(4) { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + _ebss = ABSOLUTE(.); + } > sram + + /* Stabs debugging sections. */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/stm32g4/b-g474e-dpow1/scripts/ld.script.dfu b/boards/arm/stm32g4/b-g474e-dpow1/scripts/ld.script.dfu new file mode 100644 index 0000000000000..bef0887a3a80d --- /dev/null +++ b/boards/arm/stm32g4/b-g474e-dpow1/scripts/ld.script.dfu @@ -0,0 +1,142 @@ +/**************************************************************************** + * boards/arm/stm32g4/b-g474e-dpow1/scripts/ld.script + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* The STM32G474RE has 512 KiB of FLASH beginning at address 0x0800:0000. + * + * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 + * where the code expects to begin execution by jumping to the entry point in + * the 0x0800:0000 address range. The FLASH bootloader is located there and + * allocated up to 24KiB (6 pages of 4k if single bank mode or 12 pages of 2k + * if dual bank mode), so our executable will begin at 0x0800:6000, leaving + * 488KiB. + * + * The STM32G474RE has a total of 128 KiB of SRAM in three separate areas: + * + * 1) 80 KiB SRAM1 mapped at 0x2000:0000 thru 0x2001:3fff. + * 2) 16 KiB SRAM2 mapped at 0x2001:4000 thru 0x2001:7fff. + * + * CCM SRAM (Routine Booster): + * + * 3) 32 KiB CCM SRAM mapped at 0x1000:0000 thru 0x1000:7fff + * but also aliased at at 0x2001:8000 thru 0x2001:ffff to be contiguous + * with the SRAM1 and SRAM2. + * + * Because SRAM1 and SRAM2 are contiguous, they are treated as one region + * by this logic. + * + * CCM SRAM is also contiguous to SRAM1 and SRAM2, however it is excluded + * from this linker script, to keep it reserved for special uses in code. + * REVISIT: Is this the correct way to handle CCM SRAM? + */ + +MEMORY +{ + flash (rx) : ORIGIN = 0x08006000, LENGTH = 488K + sram (rwx) : ORIGIN = 0x20000000, LENGTH = 96K +} + +OUTPUT_ARCH(arm) +EXTERN(_vectors) +ENTRY(_stext) + +SECTIONS +{ + .text : { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > flash + + .init_section : ALIGN(4) { + _sinit = ABSOLUTE(.); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) + _einit = ABSOLUTE(.); + } > flash + + .ARM.extab : ALIGN(4) { + *(.ARM.extab*) + } > flash + + .ARM.exidx : ALIGN(4) { + __exidx_start = ABSOLUTE(.); + *(.ARM.exidx*) + __exidx_end = ABSOLUTE(.); + } > flash + + .tdata : { + _stdata = ABSOLUTE(.); + *(.tdata .tdata.* .gnu.linkonce.td.*); + _etdata = ABSOLUTE(.); + } > flash + + .tbss : { + _stbss = ABSOLUTE(.); + *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); + _etbss = ABSOLUTE(.); + } > flash + + _eronly = ABSOLUTE(.); + + .data : ALIGN(4) { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > sram AT > flash + + .bss : ALIGN(4) { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + _ebss = ABSOLUTE(.); + } > sram + + /* Stabs debugging sections. */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/stm32/b-g474e-dpow1/src/.gitignore b/boards/arm/stm32g4/b-g474e-dpow1/src/.gitignore similarity index 100% rename from boards/arm/stm32/b-g474e-dpow1/src/.gitignore rename to boards/arm/stm32g4/b-g474e-dpow1/src/.gitignore diff --git a/boards/arm/stm32g4/b-g474e-dpow1/src/CMakeLists.txt b/boards/arm/stm32g4/b-g474e-dpow1/src/CMakeLists.txt new file mode 100644 index 0000000000000..5a6c304b0f2de --- /dev/null +++ b/boards/arm/stm32g4/b-g474e-dpow1/src/CMakeLists.txt @@ -0,0 +1,37 @@ +# ############################################################################## +# boards/arm/stm32g4/b-g474e-dpow1/src/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(SRCS stm32_boot.c) + +if(CONFIG_ARCH_LEDS) + list(APPEND SRCS stm32_autoleds.c) +else() + list(APPEND SRCS stm32_userleds.c) +endif() + +if(CONFIG_DRIVERS_SMPS) + list(APPEND SRCS stm32_smps.c) +endif() + +target_sources(board PRIVATE ${SRCS}) + +set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/ld.script") diff --git a/boards/arm/stm32g4/b-g474e-dpow1/src/Make.defs b/boards/arm/stm32g4/b-g474e-dpow1/src/Make.defs new file mode 100644 index 0000000000000..172dcb8b09960 --- /dev/null +++ b/boards/arm/stm32g4/b-g474e-dpow1/src/Make.defs @@ -0,0 +1,40 @@ +############################################################################ +# boards/arm/stm32g4/b-g474e-dpow1/src/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +ASRCS = +CSRCS = stm32_boot.c + +ifeq ($(CONFIG_ARCH_LEDS),y) +CSRCS += stm32_autoleds.c +else +CSRCS += stm32_userleds.c +endif + +ifeq ($(CONFIG_DRIVERS_SMPS),y) +CSRCS += stm32_smps.c +endif + +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/b-g474e-dpow1/src/b-g474e-dpow1.h b/boards/arm/stm32g4/b-g474e-dpow1/src/b-g474e-dpow1.h similarity index 98% rename from boards/arm/stm32/b-g474e-dpow1/src/b-g474e-dpow1.h rename to boards/arm/stm32g4/b-g474e-dpow1/src/b-g474e-dpow1.h index f7c09937e7f69..f981e5ed105b6 100644 --- a/boards/arm/stm32/b-g474e-dpow1/src/b-g474e-dpow1.h +++ b/boards/arm/stm32g4/b-g474e-dpow1/src/b-g474e-dpow1.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/b-g474e-dpow1/src/b-g474e-dpow1.h + * boards/arm/stm32g4/b-g474e-dpow1/src/b-g474e-dpow1.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32g4/b-g474e-dpow1/src/stm32_autoleds.c b/boards/arm/stm32g4/b-g474e-dpow1/src/stm32_autoleds.c new file mode 100644 index 0000000000000..41f87f2130b06 --- /dev/null +++ b/boards/arm/stm32g4/b-g474e-dpow1/src/stm32_autoleds.c @@ -0,0 +1,111 @@ +/**************************************************************************** + * boards/arm/stm32g4/b-g474e-dpow1/src/stm32_autoleds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "stm32.h" +#include "b-g474e-dpow1.h" + +#if defined(CONFIG_ARCH_LEDS) + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_autoled_initialize + ****************************************************************************/ + +void board_autoled_initialize(void) +{ + /* Configure LED GPIOs for output */ + + stm32_configgpio(GPIO_LED1); + stm32_configgpio(GPIO_LED2); + stm32_configgpio(GPIO_LED3); + stm32_configgpio(GPIO_LED4); +} + +/**************************************************************************** + * Name: board_autoled_on + ****************************************************************************/ + +void board_autoled_on(int led) +{ + switch (led) + { + case BOARD_LED1: + stm32_gpiowrite(GPIO_LED1, true); + break; + + case BOARD_LED2: + stm32_gpiowrite(GPIO_LED2, true); + break; + + case BOARD_LED3: + stm32_gpiowrite(GPIO_LED3, true); + break; + + case BOARD_LED4: + stm32_gpiowrite(GPIO_LED4, true); + break; + } +} + +/**************************************************************************** + * Name: board_autoled_off + ****************************************************************************/ + +void board_autoled_off(int led) +{ + switch (led) + { + case BOARD_LED1: + stm32_gpiowrite(GPIO_LED1, false); + break; + + case BOARD_LED2: + stm32_gpiowrite(GPIO_LED2, false); + break; + + case BOARD_LED3: + stm32_gpiowrite(GPIO_LED3, false); + break; + + case BOARD_LED4: + stm32_gpiowrite(GPIO_LED4, false); + break; + } +} + +#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32g4/b-g474e-dpow1/src/stm32_boot.c b/boards/arm/stm32g4/b-g474e-dpow1/src/stm32_boot.c new file mode 100644 index 0000000000000..a7bbb7138b0be --- /dev/null +++ b/boards/arm/stm32g4/b-g474e-dpow1/src/stm32_boot.c @@ -0,0 +1,125 @@ +/**************************************************************************** + * boards/arm/stm32g4/b-g474e-dpow1/src/stm32_boot.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include +#include + +#include "b-g474e-dpow1.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#undef HAVE_LEDS + +#if !defined(CONFIG_ARCH_LEDS) && defined(CONFIG_USERLED_LOWER) +# define HAVE_LEDS 1 +#endif + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_boardinitialize + * + * Description: + * All STM32 architectures must provide the following entry point. This + * entry point is called early in the initialization -- after all memory + * has been configured and mapped but before any devices have been + * initialized. + * + ****************************************************************************/ + +void stm32_boardinitialize(void) +{ +#if defined(CONFIG_ARCH_LEDS) + /* Configure on-board LEDs if LED support has been selected. */ + + board_autoled_initialize(); +#endif +} + +/**************************************************************************** + * Name: board_late_initialize + * + * Description: + * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_late_initialize(). board_late_initialize() will be + * called immediately after up_initialize() is called and just before the + * initial application is started. This additional initialization phase + * may be used, for example, to initialize board-specific device drivers. + * + ****************************************************************************/ + +#ifdef CONFIG_BOARD_LATE_INITIALIZE +void board_late_initialize(void) +{ + int ret; + +#if defined(HAVE_LEDS) + /* Register the LED driver */ + + ret = userled_lower_initialize(LED_DRIVER_PATH); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: userled_lower_initialize() failed: %d\n", ret); + return; + } +#endif + +#ifdef CONFIG_DRIVERS_SMPS + /* Initialize smps and register the smps driver */ + + ret = stm32_smps_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_smps_setup failed: %d\n", ret); + } +#endif + + UNUSED(ret); +} +#endif diff --git a/boards/arm/stm32g4/b-g474e-dpow1/src/stm32_smps.c b/boards/arm/stm32g4/b-g474e-dpow1/src/stm32_smps.c new file mode 100644 index 0000000000000..9a51ba2908446 --- /dev/null +++ b/boards/arm/stm32g4/b-g474e-dpow1/src/stm32_smps.c @@ -0,0 +1,1262 @@ +/**************************************************************************** + * boards/arm/stm32g4/b-g474e-dpow1/src/stm32_smps.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#include + +#include "arm_internal.h" +#include "ram_vectors.h" + +#include "stm32_hrtim.h" +#include "stm32_adc.h" + +#include + +#if defined(CONFIG_EXAMPLES_SMPS) && defined(CONFIG_DRIVERS_SMPS) + +#ifndef CONFIG_LIBDSP +# error CONFIG_LIBDSP is required +#endif + +#ifndef CONFIG_ARCH_HIPRI_INTERRUPT +# error CONFIG_ARCH_HIPRI_INTERRUPT is required +#endif + +#ifndef CONFIG_ARCH_RAMVECTORS +# error CONFIG_ARCH_RAMVECTORS is required +#endif + +#ifndef CONFIG_ARCH_IRQPRIO +# error CONFIG_ARCH_IRQPRIO is required +#endif + +#ifndef CONFIG_ARCH_FPU +# warning Set CONFIG_ARCH_FPU for hardware FPU support +#endif + +#if !defined(CONFIG_STM32_HRTIM1) || !defined(CONFIG_STM32_HRTIM) +# error "SMPS example requires HRTIM1 support" +#endif + +#if !defined(CONFIG_STM32_ADC1) || !defined(CONFIG_ADC) +# error "SMPS example requires ADC1 support" +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* ADC1 channels used in this example */ + +#define ADC1_NCHANNELS 2 + +/* ADC1 injected channels numeration */ + +#define V_IN_ADC_INJ_CHANNEL 0 +#define V_OUT_ADC_INJ_CHANNEL 1 + +/* Voltage reference for ADC */ + +#define ADC_REF_VOLTAGE ((float)3.3) + +/* ADC resolution */ + +#define ADC_VAL_MAX 4095 + +/* Input voltage conversion ratio - 6.8k/(6.8k + 27k) */ + +#define V_IN_RATIO (float)((float)(6800+27000)/(float)6800) + +/* Output voltage conversion ratio - 3.3k/(3.3k + 13.3k) */ + +#define V_OUT_RATIO (float)((float)(3300+13300)/(float)3300) + +/* Some absolute limits */ + +#define SMPS_ABSOLUTE_OUT_CURRENT_LIMIT_mA 250 +#define SMPS_ABSOLUTE_OUT_VOLTAGE_LIMIT_mV 15000 +#define SMPS_ABSOLUTE_IN_VOLTAGE_LIMIT_mV 15000 + +#if CONFIG_EXAMPLES_SMPS_OUT_CURRENT_LIMIT > SMPS_ABSOLUTE_OUT_CURRENT_LIMIT_mA +# error "Output current limit great than absolute limit!" +#endif +#if CONFIG_EXAMPLES_SMPS_OUT_VOLTAGE_LIMIT > SMPS_ABSOLUTE_OUT_VOLTAGE_LIMIT_mV +# error "Output voltage limit greater than absolute limit!" +#endif +#if CONFIG_EXAMPLES_SMPS_IN_VOLTAGE_LIMIT > SMPS_ABSOLUTE_IN_VOLTAGE_LIMIT_mV +# error "Input voltage limit greater than absolute limit!" +#endif + +/* Maximum output voltage for boost converter in float */ + +#define BOOST_VOLT_MAX ((float)CONFIG_EXAMPLES_SMPS_OUT_VOLTAGE_LIMIT/1000.0) + +/* At this time only PID controller implemented */ + +#define SMPS_CONTROLLER_PID 1 + +/* Converter's finite accuracy */ + +#define SMPS_VOLTAGE_ACCURACY ((float)0.01) + +/* Buck-boost mode threshold */ + +#define SMPS_BUCKBOOST_RANGE ((float)0.5) + +/* PID controller configuration */ + +#define PID_KP ((float)1.0) +#define PID_KI ((float)0.1) +#define PID_KD ((float)0.0) + +/* Converter frequencies: + * - TIMC_PWM_FREQ - buck converter 250kHz + * - TIMD_PWM_FREQ - boost converter 250kHz + */ + +#define TIMC_PWM_FREQ 250000 +#define TIMD_PWM_FREQ 250000 + +/* Deadtime configuration */ + +#define DT_RISING 0x0B0 +#define DT_FALLING 0x0B0 + +/* Helper macros */ + +#define HRTIM_ALL_OUTPUTS_ENABLE(hrtim, state) \ + HRTIM_OUTPUTS_ENABLE(hrtim, HRTIM_OUT_TIMC_CH1|HRTIM_OUT_TIMC_CH2| \ + HRTIM_OUT_TIMD_CH1|HRTIM_OUT_TIMD_CH2, state); + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/* Current converter mode */ + +enum converter_mode_e +{ + CONVERTER_MODE_INIT, /* Initial mode */ + CONVERTER_MODE_BUCK, /* Buck mode operations (V_in > V_out) */ + CONVERTER_MODE_BOOST, /* Boost mode operations (V_in < V_out) */ + CONVERTER_MODE_BUCKBOOST, /* Buck-boost operations (V_in near V_out) */ +}; + +/* SMPS lower drivers structure */ + +struct smps_lower_dev_s +{ + struct hrtim_dev_s *hrtim; /* PWM generation */ + struct stm32_adc_dev_s *adc; /* input and output voltage sense */ + struct comp_dev_s *comp; /* not used in this demo - only as reference */ + struct dac_dev_s *dac; /* not used in this demo - only as reference */ + struct opamp_dev_s *opamp; /* not used in this demo - only as reference */ +}; + +/* Private data for smps */ + +struct smps_priv_s +{ + uint8_t conv_mode; /* Converter mode */ + uint16_t v_in_raw; /* Voltage input RAW value */ + uint16_t v_out_raw; /* Voltage output RAW value */ + float v_in; /* Voltage input real value in V */ + float v_out; /* Voltage output real value in V */ + bool running; /* Running flag */ + pid_controller_f32_t pid; /* PID controller */ + float *c_limit_tab; /* Current limit tab */ +}; + +/**************************************************************************** + * Private Function Protototypes + ****************************************************************************/ + +static int smps_setup(struct smps_dev_s *dev); +static int smps_shutdown(struct smps_dev_s *dev); +static int smps_start(struct smps_dev_s *dev); +static int smps_stop(struct smps_dev_s *dev); +static int smps_params_set(struct smps_dev_s *dev, + struct smps_params_s *param); +static int smps_mode_set(struct smps_dev_s *dev, uint8_t mode); +static int smps_limits_set(struct smps_dev_s *dev, + struct smps_limits_s *limits); +static int smps_state_get(struct smps_dev_s *dev, + struct smps_state_s *state); +static int smps_fault_set(struct smps_dev_s *dev, uint8_t fault); +static int smps_fault_get(struct smps_dev_s *dev, + uint8_t *fault); +static int smps_fault_clean(struct smps_dev_s *dev, + uint8_t fault); +static int smps_ioctl(struct smps_dev_s *dev, int cmd, + unsigned long arg); + +static void smps_conv_mode_set(struct smps_priv_s *priv, + struct smps_lower_dev_s *lower, + uint8_t mode); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +struct smps_lower_dev_s g_smps_lower; +struct smps_priv_s g_smps_priv; +struct smps_s g_smps; + +struct smps_ops_s g_smps_ops = +{ + .setup = smps_setup, + .shutdown = smps_shutdown, + .start = smps_start, + .stop = smps_stop, + .params_set = smps_params_set, + .mode_set = smps_mode_set, + .limits_set = smps_limits_set, + .fault_set = smps_fault_set, + .state_get = smps_state_get, + .fault_get = smps_fault_get, + .fault_clean = smps_fault_clean, + .ioctl = smps_ioctl +}; + +struct smps_dev_s g_smps_dev = +{ + .ops = &g_smps_ops, + .priv = &g_smps, + .lower = NULL +}; + +/* ADC configuration: + * - Input voltage (V_IN) - ADC1 Channel 2 (PA1) + * - Output voltage (V_OUT) - ADC1 Channel 4 (PA3) + * + * ADC channels configured in injected mode. + * + * Transistors configuration in buck mode: + * - T6 - ON + * - T2 - OFF + * - T5 and T1 - buck operation + * Transistors configuration in boost mode: + * - T5 - ON + * - T1 - OFF + * - T6 and T2 - boost operation + * Transistors configuration in buck-boost mode: + * - T5 and T1 - buck operation + * - T6 and T2 - boost operation + * + * HRTIM outputs configuration: + * - T5 -> PB12 -> HRTIM_CHC1 + * - T6 -> PB14 -> HRTIM_CHD1 + * - T1 -> PB13 -> HRTIM_CHC2 + * - T2 -> PB15 -> HRTIM_CHD2 + */ + +/* ADC channel list */ + +static const uint8_t g_adc1chan[ADC1_NCHANNELS] = +{ + 2, + 4 +}; + +/* Configurations of pins used by ADC channel */ + +static const uint32_t g_adc1pins[ADC1_NCHANNELS] = +{ + GPIO_ADC1_IN2_0, /* PA1 - V_IN */ + GPIO_ADC1_IN4_0, /* PA3 - V_OUT */ +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: smps_setup + * + * Description: + * + * Returned Value: + * 0 on success, a negated errno value on failure + * + ****************************************************************************/ + +static int smps_setup(struct smps_dev_s *dev) +{ + struct smps_lower_dev_s *lower = dev->lower; + struct smps_s *smps = (struct smps_s *)dev->priv; + struct hrtim_dev_s *hrtim = NULL; + struct stm32_adc_dev_s *adc = NULL; + struct smps_priv_s *priv; + struct adc_channel_s channels[ADC1_NCHANNELS]; + struct adc_sample_time_s stime; + int ret = OK; + int i = 0; + + /* Initialize smps structure */ + + smps->opmode = SMPS_OPMODE_INIT; + smps->state.state = SMPS_STATE_INIT; + smps->priv = &g_smps_priv; + + /* Check lower half drivers */ + + hrtim = lower->hrtim; + if (hrtim == NULL) + { + pwrerr("ERROR: Failed to get hrtim "); + ret = ERROR; + goto errout; + } + + adc = lower->adc; + if (adc == NULL) + { + pwrerr("ERROR: Failed to get ADC lower level interface"); + ret = ERROR; + goto errout; + } + + /* Update ADC sample time */ + + for (i = 0; i < ADC1_NCHANNELS; i += 1) + { + channels[i].sample_time = ADC_SMPR_92p5; + channels[i].channel = g_adc1chan[i]; + } + + memset(&stime, 0, sizeof(struct adc_sample_time_s)); + + stime.channels_nbr = ADC1_NCHANNELS; + stime.channel = channels; + + STM32_ADC_SAMPLETIME_SET(adc, &stime); + STM32_ADC_SAMPLETIME_WRITE(adc); + + /* TODO: create current limit table */ + + UNUSED(priv); + +errout: + return ret; +} + +/**************************************************************************** + * Name: smps_shutdown + * + * Description: + * + * Returned Value: + * 0 on success, a negated errno value on failure + * + ****************************************************************************/ + +static int smps_shutdown(struct smps_dev_s *dev) +{ + struct smps_s *smps = (struct smps_s *)dev->priv; + struct smps_priv_s *priv = (struct smps_priv_s *)smps->priv; + + /* Stop smps if running */ + + if (priv->running == true) + { + smps_stop(dev); + } + + /* Reset smps structure */ + + memset(smps, 0, sizeof(struct smps_s)); + + return OK; +} + +/**************************************************************************** + * Name: smps_start + * + * Description: + * + * Returned Value: + * 0 on success, a negated errno value on failure + * + ****************************************************************************/ + +static int smps_start(struct smps_dev_s *dev) +{ + struct smps_lower_dev_s *lower = dev->lower; + struct smps_s *smps = (struct smps_s *)dev->priv; + struct smps_priv_s *priv = (struct smps_priv_s *)smps->priv; + struct hrtim_dev_s *hrtim = lower->hrtim; + struct stm32_adc_dev_s *adc = lower->adc; + volatile uint64_t per = 0; + uint64_t fclk = 0; + int ret = OK; + + /* Disable HRTIM outputs */ + + HRTIM_ALL_OUTPUTS_ENABLE(hrtim, false); + + /* Reset SMPS private structure */ + + memset(priv, 0, sizeof(struct smps_priv_s)); + +#ifdef SMPS_CONTROLLER_PID + /* Initialize PID controller */ + + pid_controller_init(&priv->pid, PID_KP, PID_KI, PID_KD); + + /* Set PID controller saturation */ + + pid_saturation_set(&priv->pid, 0.0, BOOST_VOLT_MAX); + + /* Reset PI integral if saturated */ + + pi_ireset_enable(&priv->pid, true); +#endif + + /* Get TIMC period value for given frequency */ + + fclk = HRTIM_FCLK_GET(hrtim, HRTIM_TIMER_TIMC); + per = fclk / TIMC_PWM_FREQ; + if (per > HRTIM_PER_MAX) + { + pwrerr("ERROR: Can not achieve timc pwm " + "freq=%" PRIu32 " if fclk=%" PRIu64 "\n", + (uint32_t)TIMC_PWM_FREQ, fclk); + ret = -EINVAL; + goto errout; + } + + /* Set TIMC period value */ + + HRTIM_PER_SET(hrtim, HRTIM_TIMER_TIMC, (uint16_t)per); + + /* Get TIMD period value for given frequency */ + + fclk = HRTIM_FCLK_GET(hrtim, HRTIM_TIMER_TIMD); + per = fclk / TIMD_PWM_FREQ; + if (per > HRTIM_PER_MAX) + { + pwrerr("ERROR: Can not achieve timd pwm " + "freq=%" PRIu32 " if fclk=%" PRIu64 "\n", + (uint32_t)TIMD_PWM_FREQ, fclk); + ret = -EINVAL; + goto errout; + } + + /* Set TIMD period value */ + + HRTIM_PER_SET(hrtim, HRTIM_TIMER_TIMD, (uint16_t)per); + + /* ADC trigger on TIMC CMP4 */ + + HRTIM_CMP_SET(hrtim, HRTIM_TIMER_TIMC, HRTIM_CMP4, 10000); + + /* Configure TIMER C and TIMER D deadtime mode + * + * NOTE: In deadtime mode we have to configure output 1 only + * (SETx1, RSTx1), output 2 configuration is not significant. + */ + + HRTIM_DEADTIME_UPDATE(hrtim, HRTIM_TIMER_TIMC, HRTIM_DT_EDGE_RISING, + DT_RISING); + HRTIM_DEADTIME_UPDATE(hrtim, HRTIM_TIMER_TIMC, HRTIM_DT_EDGE_FALLING, + DT_FALLING); + HRTIM_DEADTIME_UPDATE(hrtim, HRTIM_TIMER_TIMD, HRTIM_DT_EDGE_RISING, + DT_RISING); + HRTIM_DEADTIME_UPDATE(hrtim, HRTIM_TIMER_TIMD, HRTIM_DT_EDGE_FALLING, + DT_FALLING); + + /* Set T5 and T2 to a low state. + * Deadtime mode force T1 and T6 to a high state. + */ + + HRTIM_OUTPUT_SET_SET(hrtim, HRTIM_OUT_TIMC_CH1, HRTIM_OUT_SET_NONE); + HRTIM_OUTPUT_RST_SET(hrtim, HRTIM_OUT_TIMC_CH1, HRTIM_OUT_RST_PER); + + HRTIM_OUTPUT_SET_SET(hrtim, HRTIM_OUT_TIMD_CH1, HRTIM_OUT_SET_NONE); + HRTIM_OUTPUT_RST_SET(hrtim, HRTIM_OUT_TIMD_CH1, HRTIM_OUT_RST_PER); + + /* Set running flag */ + + priv->running = true; + + HRTIM_ALL_OUTPUTS_ENABLE(hrtim, true); + + /* Enable ADC JEOS interrupts */ + + STM32_ADC_INT_ENABLE(adc, ADC_INT_JEOS); + + /* Enable ADC12 interrupts */ + + up_enable_irq(STM32_IRQ_ADC12); + + /* Start injected conversion */ + + STM32_ADC_INJ_STARTCONV(adc, true); + +errout: + return ret; +} + +/**************************************************************************** + * Name: smps_stop + * + * Description: + * + * Returned Value: + * 0 on success, a negated errno value on failure + * + ****************************************************************************/ + +static int smps_stop(struct smps_dev_s *dev) +{ + struct smps_lower_dev_s *lower = dev->lower; + struct smps_s *smps = (struct smps_s *)dev->priv; + struct smps_priv_s *priv = (struct smps_priv_s *)smps->priv; + struct hrtim_dev_s *hrtim = lower->hrtim; + struct stm32_adc_dev_s *adc = lower->adc; + + /* Disable HRTIM outputs */ + + HRTIM_ALL_OUTPUTS_ENABLE(hrtim, false); + + /* Stop injected conversion */ + + STM32_ADC_INJ_STARTCONV(adc, false); + + /* Disable ADC JEOS interrupts */ + + STM32_ADC_INT_DISABLE(adc, ADC_INT_JEOS); + + /* Disable ADC12 interrupts */ + + up_disable_irq(STM32_IRQ_ADC12); + + /* Reset running flag */ + + priv->running = false; + + return OK; +} + +/**************************************************************************** + * Name: smps_params_set + * + * Description: + * + * Returned Value: + * 0 on success, a negated errno value on failure + * + ****************************************************************************/ + +static int smps_params_set(struct smps_dev_s *dev, + struct smps_params_s *param) +{ + struct smps_s *smps = (struct smps_s *)dev->priv; + int ret = OK; + + /* Only output voltage */ + + smps->param.v_out = param->v_out; + + /* REVISIT: use current and power parameters ? */ + + if (param->i_out > 0) + { + pwrwarn("WARNING: Output current parameters not used in this demo\n"); + } + + if (param->p_out > 0) + { + pwrwarn("WARNING: Output power parameters not used in this demo\n"); + } + + return ret; +} + +/**************************************************************************** + * Name: smps_mode_set + * + * Description: + * + * Returned Value: + * 0 on success, a negated errno value on failure + * + ****************************************************************************/ + +static int smps_mode_set(struct smps_dev_s *dev, uint8_t mode) +{ + struct smps_s *smps = (struct smps_s *)dev->priv; + int ret = OK; + + /* Only constant voltage mode supported */ + + if (mode == SMPS_OPMODE_CV) + { + smps->opmode = mode; + } + else + { + pwrerr("ERROR: Unsupported SMPS mode %d!\n", mode); + ret = ERROR; + goto errout; + } + +errout: + return ret; +} + +/**************************************************************************** + * Name: smps_limits_set + * + * Description: + * + * Returned Value: + * 0 on success, a negated errno value on failure + * + ****************************************************************************/ + +static int smps_limits_set(struct smps_dev_s *dev, + struct smps_limits_s *limits) +{ + struct smps_s *smps = (struct smps_s *)dev->priv; + int ret = OK; + + /* Some assertions */ + + if (limits->v_out <= 0) + { + pwrerr("ERROR: Output voltage limit must be set!\n"); + ret = ERROR; + goto errout; + } + + if (limits->v_in <= 0) + { + pwrerr("ERROR: Input voltage limit must be set!\n"); + ret = ERROR; + goto errout; + } + + if (limits->i_out <= 0) + { + pwrerr("ERROR: Output current limit must be set!\n"); + ret = ERROR; + goto errout; + } + + if (limits->v_out * 1000 > CONFIG_EXAMPLES_SMPS_OUT_VOLTAGE_LIMIT) + { + limits->v_out = (float)CONFIG_EXAMPLES_SMPS_OUT_VOLTAGE_LIMIT / 1000.0; + pwrwarn("WARNING: " + "SMPS output voltage limiit > SMPS absolute output voltage " + "limit. Set output voltage limit to %.2f.\n", + limits->v_out); + } + + if (limits->v_in * 1000 > CONFIG_EXAMPLES_SMPS_IN_VOLTAGE_LIMIT) + { + limits->v_in = (float)CONFIG_EXAMPLES_SMPS_IN_VOLTAGE_LIMIT / 1000.0; + pwrwarn("WARNING: " + "SMPS input voltage limiit > SMPS absolute input voltage " + "limit. Set input voltage limit to %.2f.\n", + limits->v_in); + } + + if (limits->i_out * 1000 > CONFIG_EXAMPLES_SMPS_OUT_CURRENT_LIMIT) + { + limits->i_out = (float)CONFIG_EXAMPLES_SMPS_OUT_CURRENT_LIMIT / 1000.0; + pwrwarn("WARNING: " + "SMPS output current limiit > SMPS absolute output current " + "limit. Set output current limit to %.2f.\n", + limits->i_out); + } + + /* Set output voltage limit */ + + smps->limits.v_out = limits->v_out; + + /* Set input voltage limit */ + + smps->limits.v_in = limits->v_in; + + /* Set current limit */ + + smps->limits.i_out = limits->i_out; + + /* Lock limits */ + + smps->limits.lock = true; + +errout: + return ret; +} + +/**************************************************************************** + * Name: smps_state_get + * + * Description: + * + * Returned Value: + * 0 on success, a negated errno value on failure + * + ****************************************************************************/ + +static int smps_state_get(struct smps_dev_s *dev, + struct smps_state_s *state) +{ + struct smps_s *smps = (struct smps_s *)dev->priv; + + /* Copy locally stored feedbacks data to status structure */ + + smps->state.fb.v_in = g_smps_priv.v_in; + smps->state.fb.v_out = g_smps_priv.v_out; + + /* Return state structure to caller */ + + memcpy(state, &smps->state, sizeof(struct smps_state_s)); + + return OK; +} + +/**************************************************************************** + * Name: smps_fault_set + * + * Description: + * + * Returned Value: + * 0 on success, a negated errno value on failure + * + ****************************************************************************/ + +static int smps_fault_set(struct smps_dev_s *dev, uint8_t fault) +{ + return OK; +} + +/**************************************************************************** + * Name: smps_fault_get + * + * Description: + * + * Returned Value: + * 0 on success, a negated errno value on failure + * + ****************************************************************************/ + +static int smps_fault_get(struct smps_dev_s *dev, uint8_t *fault) +{ + return OK; +} + +/**************************************************************************** + * Name: smps_fault_clean + * + * Description: + * + * Returned Value: + * 0 on success, a negated errno value on failure + * + ****************************************************************************/ + +static int smps_fault_clean(struct smps_dev_s *dev, uint8_t fault) +{ + return OK; +} + +/**************************************************************************** + * Name: smps_state_get + * + * Description: + * + * Returned Value: + * 0 on success, a negated errno value on failure + * + ****************************************************************************/ + +static int smps_ioctl(struct smps_dev_s *dev, int cmd, unsigned long arg) +{ + return OK; +} + +/**************************************************************************** + * Name: smps_controller + * + * Description: + * + * Returned Value: + * + ****************************************************************************/ + +static float smps_controller(struct smps_priv_s *priv, float err) +{ + float out = 0.0; + +#ifdef SMPS_CONTROLLER_PID + out = pid_controller(&priv->pid, err); +#else +# error "At this time only PID controller implemented" +#endif + + return out; +} + +/**************************************************************************** + * Name: smps_duty_set + * + * Description: + * + * Returned Value: + * + ****************************************************************************/ + +static void smps_duty_set(struct smps_priv_s *priv, + struct smps_lower_dev_s *lower, + float out) +{ + struct hrtim_dev_s *hrtim = lower->hrtim; + uint8_t mode = priv->conv_mode; + uint16_t cmp = 0; + float duty = 0.0; + uint16_t per = 0; + + switch (mode) + { + case CONVERTER_MODE_INIT: + { + /* Do nothing */ + + break; + } + + case CONVERTER_MODE_BUCK: + { + if (out >= priv->v_in) out = priv->v_in; + if (out < 0.0) out = 0.0; + + duty = out / priv->v_in; + +#warning TODO: current limit in buck mode + + per = HRTIM_PER_GET(hrtim, HRTIM_TIMER_TIMC); + + cmp = (uint16_t)(per * duty); + + if (cmp > per - 30) cmp = per - 30; + + /* Set T5 duty cycle. T1 is complementary to T5 */ + + HRTIM_CMP_SET(hrtim, HRTIM_TIMER_TIMC, HRTIM_CMP1, cmp); + + break; + } + + case CONVERTER_MODE_BOOST: + { + per = HRTIM_PER_GET(hrtim, HRTIM_TIMER_TIMC); + + if (out < priv->v_in) out = priv->v_in; + if (out >= BOOST_VOLT_MAX) out = BOOST_VOLT_MAX; + + duty = 1.0 - priv->v_in / out; + +#warning TODO: current limit in boost mode + + cmp = (uint16_t)(per * duty); + + /* Set T2 duty cycle. T6 is complementary to T2 */ + + HRTIM_CMP_SET(hrtim, HRTIM_TIMER_TIMD, HRTIM_CMP1, cmp); + + break; + } + + case CONVERTER_MODE_BUCKBOOST: + { + /* Buck converter is set to fixed duty cycle (80%). + * Now we need set boost converter + */ + + per = HRTIM_PER_GET(hrtim, HRTIM_TIMER_TIMC); + + if (out < priv->v_in) out = priv->v_in; + if (out >= BOOST_VOLT_MAX) out = BOOST_VOLT_MAX; + + duty = 1.0 - priv->v_in / out; + +#warning TODO: current limit in buck boost mode + + cmp = (uint16_t)(per * duty); + + /* Set T2 duty cycle. T6 is complementary to T2 */ + + HRTIM_CMP_SET(hrtim, HRTIM_TIMER_TIMD, HRTIM_CMP1, cmp); + + break; + } + + default: + { + pwrerr("ERROR: Unknown converter mode %d!\n", mode); + break; + } + } +} + +/**************************************************************************** + * Name: smps_conv_mode_set + * + * Description: + * Change converter mode (buck/boost/buck-boost). + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void smps_conv_mode_set(struct smps_priv_s *priv, + struct smps_lower_dev_s *lower, + uint8_t mode) +{ + struct hrtim_dev_s *hrtim = lower->hrtim; + + /* Disable all outputs */ + + HRTIM_ALL_OUTPUTS_ENABLE(hrtim, false); + + switch (mode) + { + case CONVERTER_MODE_INIT: + { + break; + } + + case CONVERTER_MODE_BUCK: + { + /* Set T2 low (T6 high) on the next PER */ + + HRTIM_OUTPUT_SET_SET(hrtim, HRTIM_OUT_TIMD_CH1, + HRTIM_OUT_SET_NONE); + HRTIM_OUTPUT_RST_SET(hrtim, HRTIM_OUT_TIMD_CH1, + HRTIM_OUT_RST_PER); + + /* Set T5 to a high state on PER and reset on CMP1. + * T1 is complementary to T5. + */ + + HRTIM_OUTPUT_SET_SET(hrtim, HRTIM_OUT_TIMC_CH1, + HRTIM_OUT_SET_PER); + HRTIM_OUTPUT_RST_SET(hrtim, HRTIM_OUT_TIMC_CH1, + HRTIM_OUT_RST_CMP1); + + break; + } + + case CONVERTER_MODE_BOOST: + { + /* Set T4 high (T11 low) on the next PER */ + + HRTIM_OUTPUT_SET_SET(hrtim, HRTIM_OUT_TIMC_CH1, + HRTIM_OUT_SET_PER); + HRTIM_OUTPUT_RST_SET(hrtim, HRTIM_OUT_TIMC_CH1, + HRTIM_OUT_RST_NONE); + + /* Set T12 to a high state on PER and reset on CMP1. + * T5 is complementary to T12. + */ + + HRTIM_OUTPUT_SET_SET(hrtim, HRTIM_OUT_TIMD_CH1, + HRTIM_OUT_SET_PER); + HRTIM_OUTPUT_RST_SET(hrtim, HRTIM_OUT_TIMD_CH1, + HRTIM_OUT_RST_CMP1); + + break; + } + + case CONVERTER_MODE_BUCKBOOST: + { + /* Set T4 to a high state on PER and reset on CMP1. + * T11 is complementary to T4. + */ + + HRTIM_OUTPUT_SET_SET(hrtim, HRTIM_OUT_TIMC_CH1, + HRTIM_OUT_SET_PER); + HRTIM_OUTPUT_RST_SET(hrtim, HRTIM_OUT_TIMC_CH1, + HRTIM_OUT_RST_CMP1); + + /* Set T12 to a high state on PER and reset on CMP1. + * T5 is complementary to T12. + */ + + HRTIM_OUTPUT_SET_SET(hrtim, HRTIM_OUT_TIMD_CH1, + HRTIM_OUT_SET_PER); + HRTIM_OUTPUT_RST_SET(hrtim, HRTIM_OUT_TIMD_CH1, + HRTIM_OUT_RST_CMP1); + + /* Set fixed duty cycle (80%) on buck converter (T4 and T11) */ + + HRTIM_CMP_SET(hrtim, HRTIM_TIMER_TIMC, HRTIM_CMP1, + 0.8 * ((uint16_t)HRTIM_PER_GET(hrtim, + HRTIM_TIMER_TIMC))); + + break; + } + + default: + { + pwrerr("ERROR: Unknown converter mode %d!\n", mode); + break; + } + } + + /* Set mode in private data */ + + priv->conv_mode = mode; + + /* Enable outputs */ + + HRTIM_ALL_OUTPUTS_ENABLE(hrtim, true); +} + +/**************************************************************************** + * Name: adc12_handler + ****************************************************************************/ + +static void adc12_handler(void) +{ + struct smps_dev_s *dev = &g_smps_dev; + struct smps_s *smps = (struct smps_s *)dev->priv; + struct smps_priv_s *priv = (struct smps_priv_s *)smps->priv; + struct smps_lower_dev_s *lower = dev->lower; + struct stm32_adc_dev_s *adc = lower->adc; + uint32_t pending; + float ref = ADC_REF_VOLTAGE; + float bit = ADC_VAL_MAX; + float err; + float out; + uint8_t mode; + + pending = STM32_ADC_INT_GET(adc); + + if (pending & ADC_INT_JEOC && priv->running == true) + { + /* Get raw ADC values */ + + priv->v_out_raw = STM32_ADC_INJDATA_GET(adc, V_OUT_ADC_INJ_CHANNEL); + priv->v_in_raw = STM32_ADC_INJDATA_GET(adc, V_IN_ADC_INJ_CHANNEL); + + /* Convert raw values to real values */ + + priv->v_out = (priv->v_out_raw * ref / bit) * V_OUT_RATIO; + priv->v_in = (priv->v_in_raw * ref / bit) * V_IN_RATIO; + + /* According to measured voltages we set converter + * in appropriate mode + */ + + if (smps->param.v_out > (priv->v_in + SMPS_BUCKBOOST_RANGE)) + { + /* Desired output voltage greater than input voltage - set + * boost converter + */ + + mode = CONVERTER_MODE_BOOST; + } + + else if (smps->param.v_out < (priv->v_in - SMPS_BUCKBOOST_RANGE)) + { + /* Desired output voltage lower than input voltage - set + * buck converter + */ + + mode = CONVERTER_MODE_BUCK; + } + + else + { + /* Desired output voltage close to input voltage - set + * buck-boost converter + */ + + mode = CONVERTER_MODE_BUCKBOOST; + } + + /* Configure converter to the new mode if needed */ + + if (priv->conv_mode != mode) + { + smps_conv_mode_set(priv, lower, mode); + } + + /* Get regulator error */ + + err = smps->param.v_out - priv->v_out; + + if (err >= SMPS_VOLTAGE_ACCURACY || err <= (-SMPS_VOLTAGE_ACCURACY)) + { + /* PID controller */ + + out = smps_controller(priv, err); + + /* Update duty cycle */ + + smps_duty_set(priv, lower, out); + } + } + + /* Clear pending */ + + STM32_ADC_INT_ACK(adc, pending); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_smps_setup + * + * Description: + * Initialize SMPS driver. + * + * Returned Value: + * 0 on success, a negated errno value on failure + * + ****************************************************************************/ + +int stm32_smps_setup(void) +{ + struct smps_lower_dev_s *lower = &g_smps_lower; + struct smps_dev_s *smps = &g_smps_dev; + struct hrtim_dev_s *hrtim = NULL; + struct adc_dev_s *adc = NULL; + static bool initialized = false; + int ret = OK; + int i; + + /* Initialize only once */ + + if (!initialized) + { + /* Get the HRTIM interface */ + + hrtim = stm32_hrtiminitialize(); + if (hrtim == NULL) + { + pwrerr("ERROR: Failed to get HRTIM1 interface\n"); + return -ENODEV; + } + + /* Configure the pins as analog inputs for the selected channels */ + + for (i = 0; i < ADC1_NCHANNELS; i++) + { + stm32_configgpio(g_adc1pins[i]); + } + + /* Get the ADC interface */ + + adc = stm32_adcinitialize(1, g_adc1chan, ADC1_NCHANNELS); + if (adc == NULL) + { + pwrerr("ERROR: Failed to get ADC %d interface\n", 1); + return -ENODEV; + } + + /* Initialize SMPS lower driver interfaces */ + + lower->hrtim = hrtim; + lower->adc = adc->ad_priv; + lower->comp = NULL; + lower->dac = NULL; + lower->opamp = NULL; + + /* Attach ADC12 ram vector */ + + ret = arm_ramvec_attach(STM32_IRQ_ADC12, adc12_handler); + if (ret < 0) + { + pwrerr("ERROR: arm_ramvec_attach failed: %d\n", ret); + ret = EXIT_FAILURE; + goto errout; + } + + /* Set the priority of the ADC12 interrupt vector */ + + ret = up_prioritize_irq(STM32_IRQ_ADC12, NVIC_SYSH_HIGH_PRIORITY); + if (ret < 0) + { + pwrerr("ERROR: up_prioritize_irq failed: %d\n", ret); + ret = EXIT_FAILURE; + goto errout; + } + + /* Setup ADC hardware */ + + adc->ad_ops->ao_setup(adc); + + /* We do not need register character drivers for SMPS lower + * peripherals. All control should be done via SMPS character + * driver. + */ + + ret = smps_register(CONFIG_EXAMPLES_SMPS_DEVPATH, smps, (void *)lower); + if (ret < 0) + { + pwrerr("ERROR: smps_register failed: %d\n", ret); + return ret; + } + + initialized = true; + } + +errout: + return ret; +} + +#endif /* CONFIG_EXAMPLE_SMPS && CONFIG_DRIVERS_SMPS*/ diff --git a/boards/arm/stm32g4/b-g474e-dpow1/src/stm32_userleds.c b/boards/arm/stm32g4/b-g474e-dpow1/src/stm32_userleds.c new file mode 100644 index 0000000000000..c96b727857092 --- /dev/null +++ b/boards/arm/stm32g4/b-g474e-dpow1/src/stm32_userleds.c @@ -0,0 +1,124 @@ +/**************************************************************************** + * boards/arm/stm32g4/b-g474e-dpow1/src/stm32_userleds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include + +#include "stm32.h" +#include "b-g474e-dpow1.h" + +#if !defined(CONFIG_ARCH_LEDS) + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_userled_initialize + * + * Description: + * Initialize the user LEDs before use. Note: For this function to be + * available to user application logic, CONFIG_ARCH_LEDS must not be + * defined. + ****************************************************************************/ + +uint32_t board_userled_initialize(void) +{ + /* Configure LED GPIOs for output */ + + stm32_configgpio(GPIO_LED1); + stm32_configgpio(GPIO_LED2); + stm32_configgpio(GPIO_LED3); + stm32_configgpio(GPIO_LED4); + return BOARD_NLEDS; +} + +/**************************************************************************** + * Name: board_userled + * + * Description: + * Allow user application logic to control LEDs one at a time. Note: For + * this function to be available to user application logic, + * CONFIG_ARCH_LEDS must not be defined. + * + * Parameters: + * led: Index to the LED, which may be one of the defines BOARD_LED1, + * BOARD_LED2, BOARD_LED3, or BOARD_LED4. + * ledon: true to turn the LED on, false to turn it off. + ****************************************************************************/ + +void board_userled(int led, bool ledon) +{ + switch (led) + { + case BOARD_LED1: + stm32_gpiowrite(GPIO_LED1, ledon); + break; + + case BOARD_LED2: + stm32_gpiowrite(GPIO_LED2, ledon); + break; + + case BOARD_LED3: + stm32_gpiowrite(GPIO_LED3, ledon); + break; + + case BOARD_LED4: + stm32_gpiowrite(GPIO_LED4, ledon); + break; + } +} + +/**************************************************************************** + * Name: board_userled_all + * + * Description: + * Allow user application logic to control all LEDs in one function call. + * Note: For this function to be available to user application logic, + * CONFIG_ARCH_LEDS must not be defined. + * + * Parameters: + * ledset: Bitmask indicating the new state for all LEDs, where a set bit + * indicates LED on and a clear bit indicates LED off. To + * construct the bitmask, using a bitwise OR of the defines + * BOARD_LED1_BIT, BOARD_LED2_BIT, BOARD_LED3_BIT, and/or + * BOARD_LED4_BIT. + ****************************************************************************/ + +void board_userled_all(uint32_t ledset) +{ + stm32_gpiowrite(GPIO_LED1, (ledset & BOARD_LED1_BIT) != 0); + stm32_gpiowrite(GPIO_LED2, (ledset & BOARD_LED2_BIT) != 0); + stm32_gpiowrite(GPIO_LED3, (ledset & BOARD_LED3_BIT) != 0); + stm32_gpiowrite(GPIO_LED4, (ledset & BOARD_LED4_BIT) != 0); +} + +#endif /* !CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32g4/common/CMakeLists.txt b/boards/arm/stm32g4/common/CMakeLists.txt new file mode 100644 index 0000000000000..ad0187882181e --- /dev/null +++ b/boards/arm/stm32g4/common/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32g4/common/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(${NUTTX_DIR}/boards/arm/common/stm32 stm32_common) diff --git a/boards/arm/stm32g4/common/Kconfig b/boards/arm/stm32g4/common/Kconfig new file mode 100644 index 0000000000000..5c48f62a0258b --- /dev/null +++ b/boards/arm/stm32g4/common/Kconfig @@ -0,0 +1,6 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# + +source "boards/arm/common/stm32/Kconfig" diff --git a/boards/arm/stm32g4/common/Makefile b/boards/arm/stm32g4/common/Makefile new file mode 100644 index 0000000000000..e43e0794f5af3 --- /dev/null +++ b/boards/arm/stm32g4/common/Makefile @@ -0,0 +1,39 @@ +############################################################################# +# boards/arm/stm32g4/common/Makefile +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################# + +include $(TOPDIR)/Make.defs + +STM32_BOARD_COMMON_DIR := $(TOPDIR)$(DELIM)boards$(DELIM)arm$(DELIM)common$(DELIM)stm32 +STM32_COMMON_SRCDIR := $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)common$(DELIM)stm32 + +include board/Make.defs +include $(STM32_BOARD_COMMON_DIR)$(DELIM)src$(DELIM)Make.defs + +DEPPATH += --dep-path board + +include $(TOPDIR)/boards/Board.mk + +ARCHSRCDIR = $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src +BOARDDIR = $(ARCHSRCDIR)$(DELIM)board +CFLAGS += ${INCDIR_PREFIX}$(BOARDDIR)$(DELIM)include +CFLAGS += ${INCDIR_PREFIX}$(STM32_COMMON_SRCDIR) +CXXFLAGS += ${INCDIR_PREFIX}$(STM32_COMMON_SRCDIR) diff --git a/boards/arm/stm32g4/nucleo-g431kb/CMakeLists.txt b/boards/arm/stm32g4/nucleo-g431kb/CMakeLists.txt new file mode 100644 index 0000000000000..2b117337231c6 --- /dev/null +++ b/boards/arm/stm32g4/nucleo-g431kb/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32g4/nucleo-g431kb/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/arm/stm32/nucleo-g431kb/Kconfig b/boards/arm/stm32g4/nucleo-g431kb/Kconfig similarity index 100% rename from boards/arm/stm32/nucleo-g431kb/Kconfig rename to boards/arm/stm32g4/nucleo-g431kb/Kconfig diff --git a/boards/arm/stm32g4/nucleo-g431kb/configs/comp/defconfig b/boards/arm/stm32g4/nucleo-g431kb/configs/comp/defconfig new file mode 100644 index 0000000000000..d47e5c3e774e0 --- /dev/null +++ b/boards/arm/stm32g4/nucleo-g431kb/configs/comp/defconfig @@ -0,0 +1,49 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +CONFIG_ANALOG=y +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nucleo-g431kb" +CONFIG_ARCH_BOARD_NUCLEO_G431KB=y +CONFIG_ARCH_CHIP="stm32g4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32G431K=y +CONFIG_ARCH_CHIP_STM32G4=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=5483 +CONFIG_BUILTIN=y +CONFIG_COMP=y +CONFIG_DAC=y +CONFIG_DEFAULT_SMALL=y +CONFIG_EXAMPLES_DAC=y +CONFIG_EXAMPLES_DAC_DEVPATH="/dev/dac5" +CONFIG_FILE_STREAM=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_RAM_SIZE=22528 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=15 +CONFIG_START_MONTH=6 +CONFIG_START_YEAR=2021 +CONFIG_STM32_COMP2=y +CONFIG_STM32_COMP2_HYST=3 +CONFIG_STM32_COMP2_INM=4 +CONFIG_STM32_COMP2_OUT=y +CONFIG_STM32_DAC3=y +CONFIG_STM32_DAC3CH2=y +CONFIG_STM32_DAC3CH2_MODE=3 +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_FORCEPOWER=y +CONFIG_STM32_JTAG_FULL_ENABLE=y +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32g4/nucleo-g431kb/configs/nsh/defconfig b/boards/arm/stm32g4/nucleo-g431kb/configs/nsh/defconfig new file mode 100644 index 0000000000000..e848946ed7e20 --- /dev/null +++ b/boards/arm/stm32g4/nucleo-g431kb/configs/nsh/defconfig @@ -0,0 +1,48 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nucleo-g431kb" +CONFIG_ARCH_BOARD_NUCLEO_G431KB=y +CONFIG_ARCH_CHIP="stm32g4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32G431K=y +CONFIG_ARCH_CHIP_STM32G4=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=8499 +CONFIG_BUILTIN=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_LTO_FULL=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=22528 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=14 +CONFIG_START_MONTH=10 +CONFIG_START_YEAR=2014 +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_TESTING_OSTEST=y +CONFIG_TESTING_OSTEST_STACKSIZE=1024 +CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32g4/nucleo-g431kb/configs/pwm/defconfig b/boards/arm/stm32g4/nucleo-g431kb/configs/pwm/defconfig new file mode 100644 index 0000000000000..8fbb0dc6b8760 --- /dev/null +++ b/boards/arm/stm32g4/nucleo-g431kb/configs/pwm/defconfig @@ -0,0 +1,41 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nucleo-g431kb" +CONFIG_ARCH_BOARD_NUCLEO_G431KB=y +CONFIG_ARCH_CHIP="stm32g4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32G431K=y +CONFIG_ARCH_CHIP_STM32G4=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=5483 +CONFIG_BUILTIN=y +CONFIG_DEFAULT_SMALL=y +CONFIG_EXAMPLES_PWM=y +CONFIG_FILE_STREAM=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_PWM=y +CONFIG_RAM_SIZE=22528 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=14 +CONFIG_START_YEAR=2021 +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_FORCEPOWER=y +CONFIG_STM32_JTAG_FULL_ENABLE=y +CONFIG_STM32_TIM1=y +CONFIG_STM32_TIM1_CH1OUT=y +CONFIG_STM32_TIM1_PWM=y +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32g4/nucleo-g431kb/include/board.h b/boards/arm/stm32g4/nucleo-g431kb/include/board.h new file mode 100644 index 0000000000000..c3a80f1c3122c --- /dev/null +++ b/boards/arm/stm32g4/nucleo-g431kb/include/board.h @@ -0,0 +1,258 @@ +/**************************************************************************** + * boards/arm/stm32g4/nucleo-g431kb/include/board.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_STM32_NUCLEO_G431KB_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32_NUCLEO_G431KB_INCLUDE_BOARD_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Clocking *****************************************************************/ + +/* The Nucleo-G431KB supports four ways to configure high-speed clock + * + * - HSI configuration (default): 16 MHz high-speed internal RC oscillator. + * - HSE bypass configuration (from ST-LINK): The input clock is the + * ST-LINK MCO output. The frequency is fixed to 25 MHz, and connected + * to the PF0-OSC_IN of the STM32G4 microcontroller. + * - HSE bypass configuration (from ARDUINO D7): The clock is coming from + * an external oscillator through the pin PF0 (ARDUINO D7 pin 10 of the + * CN4 connector). + * - HSE oscillator configuration: The clock is provided by an external + * 24MHz crystal (X2) available in the PCB. + */ + +#define STM32_BOARD_XTAL 24000000ul /* 24MHz */ + +#define STM32_HSI_FREQUENCY 16000000ul /* 16MHz */ +#define STM32_LSI_FREQUENCY 32000 /* 32kHz */ +#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL +#undef STM32_LSE_FREQUENCY /* Not available on this board */ + +/* Main PLL Configuration. + * + * PLL source is HSI = 16MHz + * PLLN = 85, PLLM = 4, PLLP = 10, PLLQ = 2, PLLR = 2 + * + * f(VCO Clock) = f(PLL Clock Input) x (PLLN / PLLM) + * f(PLL_P) = f(VCO Clock) / PLLP + * f(PLL_Q) = f(VCO Clock) / PLLQ + * f(PLL_R) = f(VCO Clock) / PLLR + * + * Where: + * 8 <= PLLN <= 127 + * 1 <= PLLM <= 16 + * PLLP = 2 through 31 + * PLLQ = 2, 4, 6, or 8 + * PLLR = 2, 4, 6, or 8 + * + * Do not exceed 170MHz on f(PLL_P), f(PLL_Q), or f(PLL_R). + * 64MHz <= f(VCO Clock) <= 344MHz. + * + * Given the above: + * + * f(VCO Clock) = HSI x PLLN / PLLM + * = 16MHz x 85 / 4 + * = 340MHz + * + * PLLPCLK = f(VCO Clock) / PLLP + * = 340MHz / 10 + * = 34MHz + * (May be used for ADC) + * + * PLLQCLK = f(VCO Clock) / PLLQ + * = 340MHz / 2 + * = 170MHz + * (May be used for QUADSPI, FDCAN, SAI1, I2S3. If set to + * 48MHz, may be used for USB, RNG.) + * + * PLLRCLK = f(VCO Clock) / PLLR + * = 340MHz / 2 + * = 170MHz + * (May be used for SYSCLK and most peripherals.) + */ + +#define STM32_PLLCFGR_PLLSRC RCC_PLLCFGR_PLLSRC_HSI +#define STM32_PLLCFGR_PLLCFG (RCC_PLLCFGR_PLLPEN | \ + RCC_PLLCFGR_PLLQEN | \ + RCC_PLLCFGR_PLLREN) + +#define STM32_PLLCFGR_PLLN RCC_PLLCFGR_PLLN(85) +#define STM32_PLLCFGR_PLLM RCC_PLLCFGR_PLLM(4) +#define STM32_PLLCFGR_PLLP RCC_PLLCFGR_PLLPDIV(10) +#define STM32_PLLCFGR_PLLQ RCC_PLLCFGR_PLLQ_2 +#define STM32_PLLCFGR_PLLR RCC_PLLCFGR_PLLR_2 + +#define STM32_VCO_FREQUENCY ((STM32_HSI_FREQUENCY / 4) * 85) +#define STM32_PLLP_FREQUENCY (STM32_VCO_FREQUENCY / 10) +#define STM32_PLLQ_FREQUENCY (STM32_VCO_FREQUENCY / 2) +#define STM32_PLLR_FREQUENCY (STM32_VCO_FREQUENCY / 2) + +/* Use the PLL and set the SYSCLK source to be PLLR (170MHz) */ + +#define STM32_SYSCLK_SW RCC_CFGR_SW_PLL +#define STM32_SYSCLK_SWS RCC_CFGR_SWS_PLL +#define STM32_SYSCLK_FREQUENCY STM32_PLLR_FREQUENCY + +/* AHB clock (HCLK) is SYSCLK (170MHz) */ + +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY + +/* APB1 clock (PCLK1) is HCLK (170MHz) */ + +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK +#define STM32_PCLK1_FREQUENCY STM32_HCLK_FREQUENCY + +/* APB2 clock (PCLK2) is HCLK (170MHz) */ + +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK +#define STM32_PCLK2_FREQUENCY STM32_HCLK_FREQUENCY + +/* APB2 timers 1, 8, 20 and 15-17 will receive PCLK2. */ + +/* Timers driven from APB2 will be PCLK2 */ + +#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB1_TIM15_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB1_TIM16_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB1_TIM17_CLKIN (STM32_PCLK2_FREQUENCY) + +/* APB1 timers 2-7 will be twice PCLK1 */ + +#define STM32_APB1_TIM2_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (STM32_PCLK1_FREQUENCY) + +/* USB divider -- Divide PLL clock by 1.5 */ + +#define STM32_CFGR_USBPRE 0 + +/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx + * otherwise frequency is 2xAPBx. + */ + +#define BOARD_TIM1_FREQUENCY (STM32_PCLK2_FREQUENCY) +#define BOARD_TIM2_FREQUENCY (STM32_PCLK1_FREQUENCY) +#define BOARD_TIM3_FREQUENCY (STM32_PCLK1_FREQUENCY) +#define BOARD_TIM4_FREQUENCY (STM32_PCLK1_FREQUENCY) +#define BOARD_TIM5_FREQUENCY (STM32_PCLK1_FREQUENCY) +#define BOARD_TIM6_FREQUENCY (STM32_PCLK1_FREQUENCY) +#define BOARD_TIM7_FREQUENCY (STM32_PCLK1_FREQUENCY) +#define BOARD_TIM8_FREQUENCY (STM32_PCLK2_FREQUENCY) +#define BOARD_TIM15_FREQUENCY (STM32_PCLK2_FREQUENCY) +#define BOARD_TIM16_FREQUENCY (STM32_PCLK2_FREQUENCY) +#define BOARD_TIM17_FREQUENCY (STM32_PCLK2_FREQUENCY) +#define BOARD_TIM20_FREQUENCY (STM32_PCLK2_FREQUENCY) + +/* LED definitions **********************************************************/ + +/* The Nucleo-G431KB board has only one user LED, LD2. LD2 is a green LED + * connected to the following STM32G4 pins + * - PB8 (default) + * - PB3 + * It is also connected to Arduino signal D13. + * + * If CONFIG_ARCH_LEDS is not defined, then the user can control this LED in + * any way. The following definitions are used to access individual LEDs. + */ + +/* LED index values for use with board_userled() */ + +#define BOARD_LED2 0 /* User LD2 */ +#define BOARD_NLEDS 1 + +/* LED bits for use with board_userled_all() */ + +#define BOARD_LED2_BIT (1 << BOARD_LED2) + +/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the LED on board + * the Nucleo-G431KB. The following definitions describe how NuttX controls + * the LED: + * + * SYMBOL Meaning LED1 state + * ------------------ ----------------------- ---------- + * LED_STARTED NuttX has been started OFF + * LED_HEAPALLOCATE Heap has been allocated OFF + * LED_IRQSENABLED Interrupts enabled OFF + * LED_STACKCREATED Idle stack created ON + * LED_INIRQ In an interrupt No change + * LED_SIGNAL In a signal handler No change + * LED_ASSERTION An assertion failed No change + * LED_PANIC The system has crashed Blinking + * LED_IDLE STM32 is in sleep mode Not used + */ + +#define LED_STARTED 0 +#define LED_HEAPALLOCATE 0 +#define LED_IRQSENABLED 0 +#define LED_STACKCREATED 1 +#define LED_INIRQ 2 +#define LED_SIGNAL 2 +#define LED_ASSERTION 2 +#define LED_PANIC 1 + +/* Button definitions *******************************************************/ + +/* The Nucleo G431KB don't have buttons that are controllable by software: + * + * B1 RESET: push button connected to NRST is used to RESET the + * STM32G431KB. + */ + +/* Alternate function pin selections ****************************************/ + +/* USART2 (STLINK Virtual COM Port) */ + +#define GPIO_USART2_TX GPIO_USART2_TX_1 /* PA2 */ +#define GPIO_USART2_RX GPIO_USART2_RX_1 /* PA3 */ + +/* PWM configuration ********************************************************/ + +/* TIM1 PWM */ + +#define GPIO_TIM1_CH1OUT (GPIO_TIM1_CH1OUT_1|GPIO_SPEED_50MHz) /* PA8 */ + +/* Comparators configuration ************************************************/ + +#define GPIO_COMP2_OUT GPIO_COMP2_OUT_3 /* PA12 */ +#define GPIO_COMP2_INP GPIO_COMP2_INP_2 /* PA7 */ +#define GPIO_COMP2_INM GPIO_COMP2_INM_2 /* PA5 check solder bridge SB2 */ + +/* DMA channels *************************************************************/ + +/* USART2 */ + +#define DMACHAN_USART2_TX DMAMAP_DMA12_USART2TX_0 /* DMA1 */ +#define DMACHAN_USART2_RX DMAMAP_DMA12_USART2RX_0 /* DMA1 */ + +#endif /* __BOARDS_ARM_STM32_NUCLEO_G431KB_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32g4/nucleo-g431kb/scripts/Make.defs b/boards/arm/stm32g4/nucleo-g431kb/scripts/Make.defs new file mode 100644 index 0000000000000..0018145617a8a --- /dev/null +++ b/boards/arm/stm32g4/nucleo-g431kb/scripts/Make.defs @@ -0,0 +1,51 @@ +############################################################################ +# boards/arm/stm32g4/nucleo-g431kb/scripts/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/.config +include $(TOPDIR)/tools/Config.mk +include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs + +ifeq ($(CONFIG_STM32_DFU),y) + LDSCRIPT = ld.script.dfu +else + LDSCRIPT = ld.script +endif + +ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) + +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 + +# Embed absolute path to source file in debug information so that Eclipse +# source level debugging won't get confused. See: +# https://stackoverflow.com/questions/1275476/gcc-gdb-how-to-embed-absolute-path-to-source-file-in-debug-information +CFLAGS += -fdebug-prefix-map=..=$(readlink -f ..) diff --git a/boards/arm/stm32g4/nucleo-g431kb/scripts/ld.script b/boards/arm/stm32g4/nucleo-g431kb/scripts/ld.script new file mode 100644 index 0000000000000..4c8eebff5b13b --- /dev/null +++ b/boards/arm/stm32g4/nucleo-g431kb/scripts/ld.script @@ -0,0 +1,139 @@ +/**************************************************************************** + * boards/arm/stm32g4/nucleo-g431kb/scripts/ld.script + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* The STM32G431KB has 128 KiB of FLASH beginning at address 0x0800:0000. + * + * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 + * where the code expects to begin execution by jumping to the entry point in + * the 0x0800:0000 address range. + * + * The STM32G431KB has a total of 32 KiB of SRAM in three separate areas: + * + * 1) 16 KiB SRAM1 mapped at 0x2000:0000 thru 0x2000:3fff. + * 2) 6 KiB SRAM2 mapped at 0x2000:4000 thru 0x2000:57ff. + * + * CCM SRAM (Routine Booster): + * + * 3) 10 KiB CCM SRAM mapped at 0x1000:0000 thru 0x1000:27ff + * but also aliased at at 0x2000:5800 thru 0x2000:7fff to be contiguous + * with the SRAM1 and SRAM2. + * + * Because SRAM1 and SRAM2 are contiguous, they are treated as one region + * by this logic. + * + * CCM SRAM is also contiguous to SRAM1 and SRAM2, however it is excluded + * from this linker script, to keep it reserved for special uses in code. + * REVISIT: Is this the correct way to handle CCM SRAM? + */ + +MEMORY +{ + flash (rx) : ORIGIN = 0x08000000, LENGTH = 128K + sram (rwx) : ORIGIN = 0x20000000, LENGTH = 22K +} + +OUTPUT_ARCH(arm) +EXTERN(_vectors) +ENTRY(_stext) + +SECTIONS +{ + .text : { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > flash + + .init_section : ALIGN(4) { + _sinit = ABSOLUTE(.); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) + _einit = ABSOLUTE(.); + } > flash + + .ARM.extab : ALIGN(4) { + *(.ARM.extab*) + } > flash + + .ARM.exidx : ALIGN(4) { + __exidx_start = ABSOLUTE(.); + *(.ARM.exidx*) + __exidx_end = ABSOLUTE(.); + } > flash + + .tdata : { + _stdata = ABSOLUTE(.); + *(.tdata .tdata.* .gnu.linkonce.td.*); + _etdata = ABSOLUTE(.); + } > flash + + .tbss : { + _stbss = ABSOLUTE(.); + *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); + _etbss = ABSOLUTE(.); + } > flash + + _eronly = ABSOLUTE(.); + + .data : ALIGN(4) { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > sram AT > flash + + .bss : ALIGN(4) { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + _ebss = ABSOLUTE(.); + } > sram + + /* Stabs debugging sections. */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/stm32/nucleo-g431kb/src/.gitignore b/boards/arm/stm32g4/nucleo-g431kb/src/.gitignore similarity index 100% rename from boards/arm/stm32/nucleo-g431kb/src/.gitignore rename to boards/arm/stm32g4/nucleo-g431kb/src/.gitignore diff --git a/boards/arm/stm32g4/nucleo-g431kb/src/CMakeLists.txt b/boards/arm/stm32g4/nucleo-g431kb/src/CMakeLists.txt new file mode 100644 index 0000000000000..eb079f995679d --- /dev/null +++ b/boards/arm/stm32g4/nucleo-g431kb/src/CMakeLists.txt @@ -0,0 +1,45 @@ +# ############################################################################## +# boards/arm/stm32g4/nucleo-g431kb/src/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(SRCS stm32_boot.c stm32_bringup.c) + +if(CONFIG_ARCH_LEDS) + list(APPEND SRCS stm32_autoleds.c) +else() + list(APPEND SRCS stm32_userleds.c) +endif() + +if(CONFIG_PWM) + list(APPEND SRCS stm32_pwm.c) +endif() + +if(CONFIG_STM32_COMP) + list(APPEND SRCS stm32_comp.c) +endif() + +if(CONFIG_STM32_DAC) + list(APPEND SRCS stm32_dac.c) +endif() + +target_sources(board PRIVATE ${SRCS}) + +set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/ld.script") diff --git a/boards/arm/stm32g4/nucleo-g431kb/src/Make.defs b/boards/arm/stm32g4/nucleo-g431kb/src/Make.defs new file mode 100644 index 0000000000000..d0b9afc162954 --- /dev/null +++ b/boards/arm/stm32g4/nucleo-g431kb/src/Make.defs @@ -0,0 +1,48 @@ +############################################################################ +# boards/arm/stm32g4/nucleo-g431kb/src/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +ASRCS = +CSRCS = stm32_boot.c stm32_bringup.c + +ifeq ($(CONFIG_ARCH_LEDS),y) +CSRCS += stm32_autoleds.c +else +CSRCS += stm32_userleds.c +endif + +ifeq ($(CONFIG_PWM),y) +CSRCS += stm32_pwm.c +endif + +ifeq ($(CONFIG_STM32_COMP),y) +CSRCS += stm32_comp.c +endif + +ifeq ($(CONFIG_STM32_DAC),y) +CSRCS += stm32_dac.c +endif + +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/nucleo-g431kb/src/nucleo-g431kb.h b/boards/arm/stm32g4/nucleo-g431kb/src/nucleo-g431kb.h similarity index 98% rename from boards/arm/stm32/nucleo-g431kb/src/nucleo-g431kb.h rename to boards/arm/stm32g4/nucleo-g431kb/src/nucleo-g431kb.h index 147f4c3479d1f..79f0f56b4726d 100644 --- a/boards/arm/stm32/nucleo-g431kb/src/nucleo-g431kb.h +++ b/boards/arm/stm32g4/nucleo-g431kb/src/nucleo-g431kb.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-g431kb/src/nucleo-g431kb.h + * boards/arm/stm32g4/nucleo-g431kb/src/nucleo-g431kb.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32g4/nucleo-g431kb/src/stm32_autoleds.c b/boards/arm/stm32g4/nucleo-g431kb/src/stm32_autoleds.c new file mode 100644 index 0000000000000..918b2ad9fbf72 --- /dev/null +++ b/boards/arm/stm32g4/nucleo-g431kb/src/stm32_autoleds.c @@ -0,0 +1,80 @@ +/**************************************************************************** + * boards/arm/stm32g4/nucleo-g431kb/src/stm32_autoleds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "stm32.h" +#include "nucleo-g431kb.h" + +#if defined(CONFIG_ARCH_LEDS) + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_autoled_initialize + ****************************************************************************/ + +void board_autoled_initialize(void) +{ + /* Configure LED GPIOs for output */ + + stm32_configgpio(GPIO_LED1); +} + +/**************************************************************************** + * Name: board_autoled_on + ****************************************************************************/ + +void board_autoled_on(int led) +{ + if (led == BOARD_LED2) + { + stm32_gpiowrite(GPIO_LED1, true); + } +} + +/**************************************************************************** + * Name: board_autoled_off + ****************************************************************************/ + +void board_autoled_off(int led) +{ + if (led == BOARD_LED2) + { + stm32_gpiowrite(GPIO_LED1, false); + } +} + +#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32g4/nucleo-g431kb/src/stm32_boot.c b/boards/arm/stm32g4/nucleo-g431kb/src/stm32_boot.c new file mode 100644 index 0000000000000..3b9024b9b1f76 --- /dev/null +++ b/boards/arm/stm32g4/nucleo-g431kb/src/stm32_boot.c @@ -0,0 +1,95 @@ +/**************************************************************************** + * boards/arm/stm32g4/nucleo-g431kb/src/stm32_boot.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include "nucleo-g431kb.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_boardinitialize + * + * Description: + * All STM32 architectures must provide the following entry point. This + * entry point is called early in the initialization -- after all memory + * has been configured and mapped but before any devices have been + * initialized. + * + ****************************************************************************/ + +void stm32_boardinitialize(void) +{ + /* Configure on-board LEDs if LED support has been selected. */ + +#ifdef CONFIG_ARCH_LEDS + board_autoled_initialize(); +#endif +} + +/**************************************************************************** + * Name: board_late_initialize + * + * Description: + * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_late_initialize(). board_late_initialize() will + * be called immediately after up_initialize() is called and just before + * the initial application is started. This additional initialization + * phase may be used, for example, to initialize board-specific device + * drivers. + * + ****************************************************************************/ + +#ifdef CONFIG_BOARD_LATE_INITIALIZE +void board_late_initialize(void) +{ + /* Perform board-specific initialization */ + + stm32_bringup(); +} +#endif diff --git a/boards/arm/stm32g4/nucleo-g431kb/src/stm32_bringup.c b/boards/arm/stm32g4/nucleo-g431kb/src/stm32_bringup.c new file mode 100644 index 0000000000000..c20ef2f5cdd78 --- /dev/null +++ b/boards/arm/stm32g4/nucleo-g431kb/src/stm32_bringup.c @@ -0,0 +1,112 @@ +/**************************************************************************** + * boards/arm/stm32g4/nucleo-g431kb/src/stm32_bringup.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include + +#ifdef CONFIG_USERLED +# include +#endif + +#include "nucleo-g431kb.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#undef HAVE_LEDS + +#if !defined(CONFIG_ARCH_LEDS) && defined(CONFIG_USERLED_LOWER) +# define HAVE_LEDS 1 +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_bringup + * + * Description: + * Perform architecture-specific initialization + * + * CONFIG_BOARD_LATE_INITIALIZE=y : + * Called from board_late_initialize(). + * + ****************************************************************************/ + +int stm32_bringup(void) +{ + int ret; + +#ifdef HAVE_LEDS + /* Register the LED driver */ + + ret = userled_lower_initialize(LED_DRIVER_PATH); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: userled_lower_initialize() failed: %d\n", ret); + return ret; + } +#endif + +#ifdef CONFIG_PWM + /* Initialize PWM and register the PWM driver. */ + + ret = stm32_pwm_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_pwm_setup failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_STM32_COMP + /* Initialize and register the COMP driver. */ + + ret = stm32_comp_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_comp_setup failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_DAC + /* Initialize and register the DAC driver. */ + + ret = stm32_dac_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_dac_setup failed: %d\n", ret); + } +#endif + + UNUSED(ret); + return OK; +} diff --git a/boards/arm/stm32g4/nucleo-g431kb/src/stm32_comp.c b/boards/arm/stm32g4/nucleo-g431kb/src/stm32_comp.c new file mode 100644 index 0000000000000..17cb1960b994a --- /dev/null +++ b/boards/arm/stm32g4/nucleo-g431kb/src/stm32_comp.c @@ -0,0 +1,148 @@ +/**************************************************************************** + * boards/arm/stm32g4/nucleo-g431kb/src/stm32_comp.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "stm32.h" + +#if defined(CONFIG_STM32_COMP) && (defined(CONFIG_STM32_COMP1) || \ + defined(CONFIG_STM32_COMP2) || \ + defined(CONFIG_STM32_COMP3) || \ + defined(CONFIG_STM32_COMP4)) + +#ifdef CONFIG_STM32_COMP1 +# if defined(CONFIG_STM32_COMP2) || \ + defined(CONFIG_STM32_COMP3) || \ + defined(CONFIG_STM32_COMP4) +# error "Currently only one COMP device supported" +# endif +#elif CONFIG_STM32_COMP2 +# if defined(CONFIG_STM32_COMP1) || \ + defined(CONFIG_STM32_COMP3) || \ + defined(CONFIG_STM32_COMP4) +# error "Currently only one COMP device supported" +# endif +#elif CONFIG_STM32_COMP3 +# if defined(CONFIG_STM32_COMP1) || \ + defined(CONFIG_STM32_COMP2) || \ + defined(CONFIG_STM32_COMP4) +# error "Currently only one COMP device supported" +# endif +#elif CONFIG_STM32_COMP4 +# if defined(CONFIG_STM32_COMP1) || \ + defined(CONFIG_STM32_COMP2) || \ + defined(CONFIG_STM32_COMP3) +# error "Currently only one COMP device supported" +# endif +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_comp_setup + * + * Description: + * Initialize COMP + * + ****************************************************************************/ + +int stm32_comp_setup(void) +{ + static bool initialized = false; + struct comp_dev_s *comp = NULL; + int ret = OK; + + if (!initialized) + { + /* Get the comparator interface */ + +#ifdef CONFIG_STM32_COMP1 + comp = stm32_compinitialize(1); + if (comp == NULL) + { + aerr("ERROR: Failed to get COMP%d interface\n", 1); + return -ENODEV; + } +#endif + +#ifdef CONFIG_STM32_COMP2 + comp = stm32_compinitialize(2); + if (comp == NULL) + { + aerr("ERROR: Failed to get COMP%d interface\n", 2); + return -ENODEV; + } +#endif + +#ifdef CONFIG_STM32_COMP3 + comp = stm32_compinitialize(3); + if (comp == NULL) + { + aerr("ERROR: Failed to get COMP%d interface\n", 3); + return -ENODEV; + } +#endif + +#ifdef CONFIG_STM32_COMP4 + comp = stm32_compinitialize(4); + if (comp == NULL) + { + aerr("ERROR: Failed to get COMP%d interface\n", 4); + return -ENODEV; + } +#endif + +#ifdef CONFIG_COMP + + /* Register the comparator character driver at /dev/comp0 */ + + ret = comp_register("/dev/comp0", comp); + if (ret < 0) + { + aerr("ERROR: comp_register failed: %d\n", ret); + return ret; + } +#endif + + initialized = true; + } + + return ret; +} + +#endif /* CONFIG_COMP && (CONFIG_STM32_COMP1 || + * CONFIG_STM32_COMP2 || + * CONFIG_STM32_COMP3 || + * CONFIG_STM32_COMP4) */ diff --git a/boards/arm/stm32g4/nucleo-g431kb/src/stm32_dac.c b/boards/arm/stm32g4/nucleo-g431kb/src/stm32_dac.c new file mode 100644 index 0000000000000..c67d3d78edf43 --- /dev/null +++ b/boards/arm/stm32g4/nucleo-g431kb/src/stm32_dac.c @@ -0,0 +1,114 @@ +/**************************************************************************** + * boards/arm/stm32g4/nucleo-g431kb/src/stm32_dac.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include + +#include +#include + +#include "stm32_dac.h" +#include "nucleo-g431kb.h" + +#ifdef CONFIG_DAC + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#ifdef CONFIG_STM32_DAC1CH1 +static struct dac_dev_s *g_dac1; +#endif + +#ifdef CONFIG_STM32_DAC3CH2 +static struct dac_dev_s *g_dac5; +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_dac_setup + * + * Description: + * Initialize and register the DAC driver. + * + * Input parameters: + * devpath - The full path to the driver to register. E.g., "/dev/dac0" + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +int stm32_dac_setup(void) +{ + int ret; +#ifdef CONFIG_STM32_DAC1CH1 + g_dac1 = stm32_dacinitialize(1); + if (g_dac1 == NULL) + { + aerr("ERROR: Failed to get DAC interface\n"); + return -ENODEV; + } + + /* Register the DAC driver at "/dev/dac0" */ + + ret = dac_register("/dev/dac0", g_dac1); + if (ret < 0) + { + aerr("ERROR: dac_register() failed: %d\n", ret); + return ret; + } + +#endif + +#ifdef CONFIG_STM32_DAC3CH2 + g_dac5 = stm32_dacinitialize(5); + if (g_dac5 == NULL) + { + aerr("ERROR: Failed to get DAC interface\n"); + return -ENODEV; + } + + /* Register the DAC driver at "/dev/dac5" */ + + ret = dac_register("/dev/dac5", g_dac5); + if (ret < 0) + { + aerr("ERROR: dac_register() failed: %d\n", ret); + return ret; + } + +#endif + + UNUSED(ret); + return OK; +} + +#endif /* CONFIG_DAC */ diff --git a/boards/arm/stm32g4/nucleo-g431kb/src/stm32_pwm.c b/boards/arm/stm32g4/nucleo-g431kb/src/stm32_pwm.c new file mode 100644 index 0000000000000..b20b3c2dcad68 --- /dev/null +++ b/boards/arm/stm32g4/nucleo-g431kb/src/stm32_pwm.c @@ -0,0 +1,86 @@ +/**************************************************************************** + * boards/arm/stm32g4/nucleo-g431kb/src/stm32_pwm.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32_pwm.h" +#include "nucleo-g431kb.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_pwm_setup + * + * Description: + * Initialize PWM and register the PWM device. + * + ****************************************************************************/ + +int stm32_pwm_setup(void) +{ + static bool initialized = false; + struct pwm_lowerhalf_s *pwm; + int ret; + + /* Have we already initialized? */ + + if (!initialized) + { + /* Call stm32_pwminitialize() to get an instance of the PWM interface */ + + pwm = stm32_pwminitialize(NUCLEOG431KB_PWM_TIMER); + if (!pwm) + { + tmrerr("Failed to get the STM32 PWM lower half\n"); + return -ENODEV; + } + + /* Register the PWM driver at "/dev/pwm0" */ + + ret = pwm_register(NUCLEOG431KB_PWM_PATH, pwm); + if (ret < 0) + { + tmrerr("pwm_register failed: %d\n", ret); + return ret; + } + + /* Now we are initialized */ + + initialized = true; + } + + return OK; +} diff --git a/boards/arm/stm32g4/nucleo-g431kb/src/stm32_userleds.c b/boards/arm/stm32g4/nucleo-g431kb/src/stm32_userleds.c new file mode 100644 index 0000000000000..2d20146d07ef7 --- /dev/null +++ b/boards/arm/stm32g4/nucleo-g431kb/src/stm32_userleds.c @@ -0,0 +1,77 @@ +/**************************************************************************** + * boards/arm/stm32g4/nucleo-g431kb/src/stm32_userleds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include + +#include "stm32.h" +#include "nucleo-g431kb.h" + +#if !defined(CONFIG_ARCH_LEDS) + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_userled_initialize + ****************************************************************************/ + +uint32_t board_userled_initialize(void) +{ + /* Configure LED GPIOs for output */ + + stm32_configgpio(GPIO_LED1); + return BOARD_NLEDS; +} + +/**************************************************************************** + * Name: board_userled + ****************************************************************************/ + +void board_userled(int led, bool ledon) +{ + if (led == BOARD_LED1) + { + stm32_gpiowrite(GPIO_LED1, ledon); + } +} + +/**************************************************************************** + * Name: board_userled_all + ****************************************************************************/ + +void board_userled_all(uint32_t ledset) +{ + stm32_gpiowrite(GPIO_LED1, (ledset & BOARD_LED1_BIT) != 0); +} + +#endif /* !CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32g4/nucleo-g431rb/CMakeLists.txt b/boards/arm/stm32g4/nucleo-g431rb/CMakeLists.txt new file mode 100644 index 0000000000000..bc497249c8354 --- /dev/null +++ b/boards/arm/stm32g4/nucleo-g431rb/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32g4/nucleo-g431rb/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/arm/stm32/nucleo-g431rb/Kconfig b/boards/arm/stm32g4/nucleo-g431rb/Kconfig similarity index 100% rename from boards/arm/stm32/nucleo-g431rb/Kconfig rename to boards/arm/stm32g4/nucleo-g431rb/Kconfig diff --git a/boards/arm/stm32g4/nucleo-g431rb/configs/adc/defconfig b/boards/arm/stm32g4/nucleo-g431rb/configs/adc/defconfig new file mode 100644 index 0000000000000..2154e927ac434 --- /dev/null +++ b/boards/arm/stm32g4/nucleo-g431rb/configs/adc/defconfig @@ -0,0 +1,92 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_SYSTEM_DD is not set +CONFIG_ADC=y +CONFIG_ANALOG=y +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nucleo-g431rb" +CONFIG_ARCH_BOARD_NUCLEO_G431RB=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32g4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32G431R=y +CONFIG_ARCH_CHIP_STM32G4=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_DISABLE_ENVIRON=y +CONFIG_DISABLE_MQUEUE=y +CONFIG_DISABLE_POSIX_TIMERS=y +CONFIG_DISABLE_PTHREAD=y +CONFIG_FDCLONE_STDIO=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=1024 +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_NAME_MAX=16 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_DISABLE_BASENAME=y +CONFIG_NSH_DISABLE_CAT=y +CONFIG_NSH_DISABLE_CD=y +CONFIG_NSH_DISABLE_CMP=y +CONFIG_NSH_DISABLE_CP=y +CONFIG_NSH_DISABLE_DF=y +CONFIG_NSH_DISABLE_DIRNAME=y +CONFIG_NSH_DISABLE_EXEC=y +CONFIG_NSH_DISABLE_EXIT=y +CONFIG_NSH_DISABLE_GET=y +CONFIG_NSH_DISABLE_HEXDUMP=y +CONFIG_NSH_DISABLE_KILL=y +CONFIG_NSH_DISABLE_LOSETUP=y +CONFIG_NSH_DISABLE_LS=y +CONFIG_NSH_DISABLE_MKDIR=y +CONFIG_NSH_DISABLE_MKRD=y +CONFIG_NSH_DISABLE_MOUNT=y +CONFIG_NSH_DISABLE_MV=y +CONFIG_NSH_DISABLE_PUT=y +CONFIG_NSH_DISABLE_PWD=y +CONFIG_NSH_DISABLE_RM=y +CONFIG_NSH_DISABLE_RMDIR=y +CONFIG_NSH_DISABLE_SET=y +CONFIG_NSH_DISABLE_SLEEP=y +CONFIG_NSH_DISABLE_SOURCE=y +CONFIG_NSH_DISABLE_TEST=y +CONFIG_NSH_DISABLE_TIME=y +CONFIG_NSH_DISABLE_UMOUNT=y +CONFIG_NSH_DISABLE_UNAME=y +CONFIG_NSH_DISABLE_UNSET=y +CONFIG_NSH_DISABLE_USLEEP=y +CONFIG_NSH_DISABLE_WGET=y +CONFIG_NSH_DISABLE_XD=y +CONFIG_NSH_FILEIOSIZE=256 +CONFIG_NSH_READLINE=y +CONFIG_POSIX_SPAWN_DEFAULT_STACKSIZE=512 +CONFIG_PTHREAD_STACK_DEFAULT=1024 +CONFIG_PTHREAD_STACK_MIN=1024 +CONFIG_RAM_SIZE=22528 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_STM32_ADC1=y +CONFIG_STM32_ADC1_DMA=y +CONFIG_STM32_ADC2=y +CONFIG_STM32_DMA1=y +CONFIG_STM32_DMAMUX1=y +CONFIG_STM32_FORCEPOWER=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_TIM1=y +CONFIG_STM32_TIM1_ADC=y +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32g4/nucleo-g431rb/configs/can/defconfig b/boards/arm/stm32g4/nucleo-g431rb/configs/can/defconfig new file mode 100644 index 0000000000000..2aa1ede955e72 --- /dev/null +++ b/boards/arm/stm32g4/nucleo-g431rb/configs/can/defconfig @@ -0,0 +1,55 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nucleo-g431rb" +CONFIG_ARCH_BOARD_NUCLEO_G431RB=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32g4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32G431R=y +CONFIG_ARCH_CHIP_STM32G4=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=8499 +CONFIG_BOARD_NUCLEO_G431RB_USE_HSE=y +CONFIG_BUILTIN=y +CONFIG_CAN_ERRORS=y +CONFIG_CAN_EXTID=y +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_EXAMPLES_CAN=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=22528 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=14 +CONFIG_START_MONTH=10 +CONFIG_START_YEAR=2014 +CONFIG_STDIO_BUFFER_SIZE=512 +CONFIG_STM32_FDCAN1=y +CONFIG_STM32_FDCAN1_BITRATE=250000 +CONFIG_STM32_FDCAN1_NTSEG1=71 +CONFIG_STM32_FDCAN1_NTSEG2=24 +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32g4/nucleo-g431rb/configs/cansock/defconfig b/boards/arm/stm32g4/nucleo-g431rb/configs/cansock/defconfig new file mode 100644 index 0000000000000..c139bf6d9b5dc --- /dev/null +++ b/boards/arm/stm32g4/nucleo-g431rb/configs/cansock/defconfig @@ -0,0 +1,60 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NET_ETHERNET is not set +# CONFIG_NET_IPv4 is not set +CONFIG_ALLOW_BSD_COMPONENTS=y +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nucleo-g431rb" +CONFIG_ARCH_BOARD_NUCLEO_G431RB=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32g4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32G431R=y +CONFIG_ARCH_CHIP_STM32G4=y +CONFIG_ARCH_INTERRUPTSTACK=1024 +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=8499 +CONFIG_BOARD_NUCLEO_G431RB_USE_HSE=y +CONFIG_BUILTIN=y +CONFIG_CANUTILS_CANDUMP=y +CONFIG_CANUTILS_CANSEND=y +CONFIG_CANUTILS_LIBCANUTILS=y +CONFIG_FS_PROCFS=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_IOB_BUFSIZE=128 +CONFIG_IOB_NBUFFERS=10 +CONFIG_LINE_MAX=64 +CONFIG_NET=y +CONFIG_NETDEV_IFINDEX=y +CONFIG_NETDEV_LATEINIT=y +CONFIG_NET_CAN=y +CONFIG_NET_SOCKOPTS=y +CONFIG_NET_STATISTICS=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_RAM_SIZE=22528 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_LPWORK=y +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=14 +CONFIG_START_MONTH=10 +CONFIG_START_YEAR=2014 +CONFIG_STM32_FDCAN1=y +CONFIG_STM32_FDCAN1_BITRATE=250000 +CONFIG_STM32_FDCAN1_NTSEG1=71 +CONFIG_STM32_FDCAN1_NTSEG2=24 +CONFIG_STM32_FDCAN_SOCKET=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32g4/nucleo-g431rb/configs/cordic/defconfig b/boards/arm/stm32g4/nucleo-g431rb/configs/cordic/defconfig new file mode 100644 index 0000000000000..1490159995b5a --- /dev/null +++ b/boards/arm/stm32g4/nucleo-g431rb/configs/cordic/defconfig @@ -0,0 +1,52 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nucleo-g431rb" +CONFIG_ARCH_BOARD_NUCLEO_G431RB=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32g4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32G431R=y +CONFIG_ARCH_CHIP_STM32G4=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=8499 +CONFIG_BUILTIN=y +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_EXAMPLES_CORDIC=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_FLOATINGPOINT=y +CONFIG_LINE_MAX=64 +CONFIG_MATH_CORDIC=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=22528 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=14 +CONFIG_START_MONTH=10 +CONFIG_START_YEAR=2014 +CONFIG_STM32_CORDIC=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32g4/nucleo-g431rb/configs/ihm16m1_b16/defconfig b/boards/arm/stm32g4/nucleo-g431rb/configs/ihm16m1_b16/defconfig new file mode 100644 index 0000000000000..ded5f303e7c78 --- /dev/null +++ b/boards/arm/stm32g4/nucleo-g431rb/configs/ihm16m1_b16/defconfig @@ -0,0 +1,88 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_DISABLE_MQUEUE is not set +# CONFIG_DISABLE_PTHREAD is not set +CONFIG_ADC=y +CONFIG_ADC_FIFOSIZE=3 +CONFIG_ANALOG=y +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nucleo-g431rb" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_NUCLEO_G431RB=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32g4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32G431R=y +CONFIG_ARCH_CHIP_STM32G4=y +CONFIG_ARCH_INTERRUPTSTACK=1024 +CONFIG_ARCH_IRQBUTTONS=y +CONFIG_ARMV7M_LIBM=y +CONFIG_BOARDCTL=y +CONFIG_BOARD_LOOPSPERMSEC=8499 +CONFIG_BOARD_STM32_IHM16M1=y +CONFIG_BOARD_STM32_IHM16M1_POT=y +CONFIG_BOARD_STM32_IHM16M1_VBUS=y +CONFIG_BUILTIN=y +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_DEFAULT_SMALL=y +CONFIG_DEFAULT_TASK_STACKSIZE=1024 +CONFIG_EXAMPLES_FOC=y +CONFIG_EXAMPLES_FOC_ADC_MAX=4095 +CONFIG_EXAMPLES_FOC_ADC_VREF=3300 +CONFIG_EXAMPLES_FOC_CONTROL_STACKSIZE=2048 +CONFIG_EXAMPLES_FOC_FIXED16_INST=1 +CONFIG_EXAMPLES_FOC_HAVE_BUTTON=y +CONFIG_EXAMPLES_FOC_NOTIFIER_FREQ=10000 +CONFIG_EXAMPLES_FOC_PWM_FREQ=20000 +CONFIG_EXAMPLES_FOC_RAMP_ACC=1000000 +CONFIG_EXAMPLES_FOC_RAMP_DEC=1000000 +CONFIG_EXAMPLES_FOC_RAMP_THR=10000 +CONFIG_EXAMPLES_FOC_SETPOINT_ADC=y +CONFIG_EXAMPLES_FOC_VBUS_ADC=y +CONFIG_EXAMPLES_FOC_VBUS_SCALE=16000 +CONFIG_INDUSTRY_FOC=y +CONFIG_INDUSTRY_FOC_FIXED16=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INPUT=y +CONFIG_INPUT_BUTTONS=y +CONFIG_INPUT_BUTTONS_LOWER=y +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBM=y +CONFIG_MOTOR=y +CONFIG_MOTOR_FOC=y +CONFIG_MOTOR_FOC_TRACE=y +CONFIG_MQ_MAXMSGSIZE=5 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_RAM_SIZE=22528 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=14 +CONFIG_START_MONTH=10 +CONFIG_START_YEAR=2014 +CONFIG_STM32_ADC1_ANIOC_TRIGGER=1 +CONFIG_STM32_ADC1_DMA=y +CONFIG_STM32_ADC1_DMA_CFG=1 +CONFIG_STM32_ADC1_INJECTED_CHAN=3 +CONFIG_STM32_DMA1=y +CONFIG_STM32_DMA2=y +CONFIG_STM32_DMAMUX1=y +CONFIG_STM32_FOC=y +CONFIG_STM32_FOC_FOC0=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_TIM1_CH1MODE=0 +CONFIG_STM32_TIM1_CH2MODE=0 +CONFIG_STM32_TIM1_CH3MODE=0 +CONFIG_STM32_TIM1_MODE=2 +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART2_SERIAL_CONSOLE=y +CONFIG_USART2_TXDMA=y diff --git a/boards/arm/stm32g4/nucleo-g431rb/configs/ihm16m1_f32/defconfig b/boards/arm/stm32g4/nucleo-g431rb/configs/ihm16m1_f32/defconfig new file mode 100644 index 0000000000000..d70d9724fe0e9 --- /dev/null +++ b/boards/arm/stm32g4/nucleo-g431rb/configs/ihm16m1_f32/defconfig @@ -0,0 +1,88 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_DISABLE_MQUEUE is not set +# CONFIG_DISABLE_PTHREAD is not set +CONFIG_ADC=y +CONFIG_ADC_FIFOSIZE=3 +CONFIG_ANALOG=y +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nucleo-g431rb" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_NUCLEO_G431RB=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32g4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32G431R=y +CONFIG_ARCH_CHIP_STM32G4=y +CONFIG_ARCH_INTERRUPTSTACK=1024 +CONFIG_ARCH_IRQBUTTONS=y +CONFIG_ARMV7M_LIBM=y +CONFIG_BOARDCTL=y +CONFIG_BOARD_LOOPSPERMSEC=8499 +CONFIG_BOARD_STM32_IHM16M1=y +CONFIG_BOARD_STM32_IHM16M1_POT=y +CONFIG_BOARD_STM32_IHM16M1_VBUS=y +CONFIG_BUILTIN=y +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_DEFAULT_SMALL=y +CONFIG_DEFAULT_TASK_STACKSIZE=1024 +CONFIG_EXAMPLES_FOC=y +CONFIG_EXAMPLES_FOC_ADC_MAX=4095 +CONFIG_EXAMPLES_FOC_ADC_VREF=3300 +CONFIG_EXAMPLES_FOC_CONTROL_STACKSIZE=2048 +CONFIG_EXAMPLES_FOC_FLOAT_INST=1 +CONFIG_EXAMPLES_FOC_HAVE_BUTTON=y +CONFIG_EXAMPLES_FOC_NOTIFIER_FREQ=10000 +CONFIG_EXAMPLES_FOC_PWM_FREQ=20000 +CONFIG_EXAMPLES_FOC_RAMP_ACC=1000000 +CONFIG_EXAMPLES_FOC_RAMP_DEC=1000000 +CONFIG_EXAMPLES_FOC_RAMP_THR=10000 +CONFIG_EXAMPLES_FOC_SETPOINT_ADC=y +CONFIG_EXAMPLES_FOC_VBUS_ADC=y +CONFIG_EXAMPLES_FOC_VBUS_SCALE=16000 +CONFIG_INDUSTRY_FOC=y +CONFIG_INDUSTRY_FOC_FLOAT=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INPUT=y +CONFIG_INPUT_BUTTONS=y +CONFIG_INPUT_BUTTONS_LOWER=y +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBM=y +CONFIG_MOTOR=y +CONFIG_MOTOR_FOC=y +CONFIG_MOTOR_FOC_TRACE=y +CONFIG_MQ_MAXMSGSIZE=5 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_RAM_SIZE=22528 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=14 +CONFIG_START_MONTH=10 +CONFIG_START_YEAR=2014 +CONFIG_STM32_ADC1_ANIOC_TRIGGER=1 +CONFIG_STM32_ADC1_DMA=y +CONFIG_STM32_ADC1_DMA_CFG=1 +CONFIG_STM32_ADC1_INJECTED_CHAN=3 +CONFIG_STM32_DMA1=y +CONFIG_STM32_DMA2=y +CONFIG_STM32_DMAMUX1=y +CONFIG_STM32_FOC=y +CONFIG_STM32_FOC_FOC0=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_TIM1_CH1MODE=0 +CONFIG_STM32_TIM1_CH2MODE=0 +CONFIG_STM32_TIM1_CH3MODE=0 +CONFIG_STM32_TIM1_MODE=2 +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART2_SERIAL_CONSOLE=y +CONFIG_USART2_TXDMA=y diff --git a/boards/arm/stm32g4/nucleo-g431rb/configs/nsh/defconfig b/boards/arm/stm32g4/nucleo-g431rb/configs/nsh/defconfig new file mode 100644 index 0000000000000..2741f79a4ff4b --- /dev/null +++ b/boards/arm/stm32g4/nucleo-g431rb/configs/nsh/defconfig @@ -0,0 +1,49 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nucleo-g431rb" +CONFIG_ARCH_BOARD_NUCLEO_G431RB=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32g4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32G431R=y +CONFIG_ARCH_CHIP_STM32G4=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=8499 +CONFIG_BUILTIN=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_LTO_FULL=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=22528 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=14 +CONFIG_START_MONTH=10 +CONFIG_START_YEAR=2014 +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_TESTING_OSTEST=y +CONFIG_TESTING_OSTEST_STACKSIZE=1024 +CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32g4/nucleo-g431rb/configs/pwm/defconfig b/boards/arm/stm32g4/nucleo-g431rb/configs/pwm/defconfig new file mode 100644 index 0000000000000..7bb17b75b5be1 --- /dev/null +++ b/boards/arm/stm32g4/nucleo-g431rb/configs/pwm/defconfig @@ -0,0 +1,62 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nucleo-g431rb" +CONFIG_ARCH_BOARD_NUCLEO_G431RB=y +CONFIG_ARCH_CHIP="stm32g4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32G431R=y +CONFIG_ARCH_CHIP_STM32G4=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=5483 +CONFIG_BUILTIN=y +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_DEFAULT_SMALL=y +CONFIG_EXAMPLES_PWM=y +CONFIG_FILE_STREAM=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=80 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=1024 +CONFIG_PWM=y +CONFIG_PWM_NCHANNELS=4 +CONFIG_RAM_SIZE=22528 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=192 +CONFIG_SCHED_WAITPID=y +CONFIG_SERIAL_TERMIOS=y +CONFIG_START_DAY=5 +CONFIG_START_MONTH=7 +CONFIG_START_YEAR=2011 +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_FORCEPOWER=y +CONFIG_STM32_JTAG_FULL_ENABLE=y +CONFIG_STM32_PWM_MULTICHAN=y +CONFIG_STM32_TIM1=y +CONFIG_STM32_TIM1_CH1NOUT=y +CONFIG_STM32_TIM1_CH1OUT=y +CONFIG_STM32_TIM1_CH2NOUT=y +CONFIG_STM32_TIM1_CH2OUT=y +CONFIG_STM32_TIM1_CH3NOUT=y +CONFIG_STM32_TIM1_CH3OUT=y +CONFIG_STM32_TIM1_CH4OUT=y +CONFIG_STM32_TIM1_CHANNEL1=y +CONFIG_STM32_TIM1_CHANNEL2=y +CONFIG_STM32_TIM1_CHANNEL3=y +CONFIG_STM32_TIM1_CHANNEL4=y +CONFIG_STM32_TIM1_PWM=y +CONFIG_STM32_USART2=y +CONFIG_SYMTAB_ORDEREDBYNAME=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32g4/nucleo-g431rb/configs/qenco/defconfig b/boards/arm/stm32g4/nucleo-g431rb/configs/qenco/defconfig new file mode 100644 index 0000000000000..f593ed1dac3d3 --- /dev/null +++ b/boards/arm/stm32g4/nucleo-g431rb/configs/qenco/defconfig @@ -0,0 +1,57 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nucleo-g431rb" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_NUCLEO_G431RB=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32g4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32G431R=y +CONFIG_ARCH_CHIP_STM32G4=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=8499 +CONFIG_BUILTIN=y +CONFIG_EXAMPLES_QENCODER=y +CONFIG_EXAMPLES_QENCODER_HAVE_MAXPOS=y +CONFIG_EXAMPLES_QENCODER_MAXPOS=8192 +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=22528 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_SENSORS=y +CONFIG_SENSORS_QENCODER=y +CONFIG_START_DAY=14 +CONFIG_START_MONTH=10 +CONFIG_START_YEAR=2014 +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_QENCODER_DISABLE_EXTEND16BTIMERS=y +CONFIG_STM32_QENCODER_SAMPLE_FDTS_2=y +CONFIG_STM32_TIM2=y +CONFIG_STM32_TIM2_QE=y +CONFIG_STM32_TIM2_QEPSC=0 +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32g4/nucleo-g431rb/include/board.h b/boards/arm/stm32g4/nucleo-g431rb/include/board.h new file mode 100644 index 0000000000000..75cc137c57439 --- /dev/null +++ b/boards/arm/stm32g4/nucleo-g431rb/include/board.h @@ -0,0 +1,399 @@ +/**************************************************************************** + * boards/arm/stm32g4/nucleo-g431rb/include/board.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_STM32_NUCLEO_G431RB_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32_NUCLEO_G431RB_INCLUDE_BOARD_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Clocking *****************************************************************/ + +#define STM32_BOARD_XTAL 24000000 /* 8MHz */ + +#define STM32_HSI_FREQUENCY 16000000ul /* 16MHz */ +#define STM32_LSI_FREQUENCY 32000 /* 32kHz */ +#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL +#undef STM32_LSE_FREQUENCY /* Not available on this board */ + +#ifdef CONFIG_BOARD_NUCLEO_G431RB_USE_HSI + +/* Main PLL Configuration. + * + * PLL source is HSI = 16MHz + * PLLN = 85, PLLM = 4, PLLP = 10, PLLQ = 2, PLLR = 2 + * + * f(VCO Clock) = f(PLL Clock Input) x (PLLN / PLLM) + * f(PLL_P) = f(VCO Clock) / PLLP + * f(PLL_Q) = f(VCO Clock) / PLLQ + * f(PLL_R) = f(VCO Clock) / PLLR + * + * Where: + * 8 <= PLLN <= 127 + * 1 <= PLLM <= 16 + * PLLP = 2 through 31 + * PLLQ = 2, 4, 6, or 8 + * PLLR = 2, 4, 6, or 8 + * + * Do not exceed 170MHz on f(PLL_P), f(PLL_Q), or f(PLL_R). + * 64MHz <= f(VCO Clock) <= 344MHz. + * + * Given the above: + * + * f(VCO Clock) = HSI x PLLN / PLLM + * = 16MHz x 85 / 4 + * = 340MHz + * + * PLLPCLK = f(VCO Clock) / PLLP + * = 340MHz / 10 + * = 34MHz + * (May be used for ADC) + * + * PLLQCLK = f(VCO Clock) / PLLQ + * = 340MHz / 2 + * = 170MHz + * (May be used for QUADSPI, FDCAN, SAI1, I2S3. If set to + * 48MHz, may be used for USB, RNG.) + * + * PLLRCLK = f(VCO Clock) / PLLR + * = 340MHz / 2 + * = 170MHz + * (May be used for SYSCLK and most peripherals.) + */ + +#define STM32_PLLCFGR_PLLSRC RCC_PLLCFGR_PLLSRC_HSI +#define STM32_PLLCFGR_PLLCFG (RCC_PLLCFGR_PLLPEN | \ + RCC_PLLCFGR_PLLQEN | \ + RCC_PLLCFGR_PLLREN) + +#define STM32_PLLCFGR_PLLN RCC_PLLCFGR_PLLN(85) +#define STM32_PLLCFGR_PLLM RCC_PLLCFGR_PLLM(4) +#define STM32_PLLCFGR_PLLP RCC_PLLCFGR_PLLPDIV(10) +#define STM32_PLLCFGR_PLLQ RCC_PLLCFGR_PLLQ_2 +#define STM32_PLLCFGR_PLLR RCC_PLLCFGR_PLLR_2 + +#define STM32_VCO_FREQUENCY ((STM32_HSI_FREQUENCY / 4) * 85) +#define STM32_PLLP_FREQUENCY (STM32_VCO_FREQUENCY / 10) +#define STM32_PLLQ_FREQUENCY (STM32_VCO_FREQUENCY / 2) +#define STM32_PLLR_FREQUENCY (STM32_VCO_FREQUENCY / 2) + +/* Use the PLL and set the SYSCLK source to be PLLR (170MHz) */ + +#define STM32_SYSCLK_SW RCC_CFGR_SW_PLL +#define STM32_SYSCLK_SWS RCC_CFGR_SWS_PLL +#define STM32_SYSCLK_FREQUENCY STM32_PLLR_FREQUENCY + +/* AHB clock (HCLK) is SYSCLK (170MHz) */ + +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY + +/* APB1 clock (PCLK1) is HCLK (170MHz) */ + +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK +#define STM32_PCLK1_FREQUENCY STM32_HCLK_FREQUENCY + +/* APB2 clock (PCLK2) is HCLK (170MHz) */ + +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK +#define STM32_PCLK2_FREQUENCY STM32_HCLK_FREQUENCY + +#endif /* CONFIG_BOARD_NUCLEO_G431RB_USE_HSI */ + +#ifdef CONFIG_BOARD_NUCLEO_G431RB_USE_HSE + +/* Main PLL Configuration. + * + * PLL source is HSE = 24MHz + * PLLN = 86, PLLM = 6, PLLP = 10, PLLQ = 2, PLLR = 2 + * + * f(VCO Clock) = f(PLL Clock Input) x (PLLN / PLLM) + * f(PLL_P) = f(VCO Clock) / PLLP + * f(PLL_Q) = f(VCO Clock) / PLLQ + * f(PLL_R) = f(VCO Clock) / PLLR + * + * Where: + * 8 <= PLLN <= 127 + * 1 <= PLLM <= 16 + * PLLP = 2 through 31 + * PLLQ = 2, 4, 6, or 8 + * PLLR = 2, 4, 6, or 8 + * + * Do not exceed 170MHz on f(PLL_P), f(PLL_Q), or f(PLL_R). + * 64MHz <= f(VCO Clock) <= 344MHz. + * + * Given the above: + * + * f(VCO Clock) = HSE x PLLN / PLLM + * = 24MHz x 86 / 6 + * = 340MHz + * + * PLLPCLK = f(VCO Clock) / PLLP + * = 340MHz / 10 + * = 34MHz + * (May be used for ADC) + * + * PLLQCLK = f(VCO Clock) / PLLQ + * = 340MHz / 2 + * = 170MHz + * (May be used for QUADSPI, FDCAN, SAI1, I2S3. If set to + * 48MHz, may be used for USB, RNG.) + * + * PLLRCLK = f(VCO Clock) / PLLR + * = 340MHz / 2 + * = 170MHz + * (May be used for SYSCLK and most peripherals.) + */ + +#define STM32_PLLCFGR_PLLSRC RCC_PLLCFGR_PLLSRC_HSE +#define STM32_PLLCFGR_PLLCFG (RCC_PLLCFGR_PLLPEN | \ + RCC_PLLCFGR_PLLQEN | \ + RCC_PLLCFGR_PLLREN) + +#define STM32_PLLCFGR_PLLN RCC_PLLCFGR_PLLN(86) +#define STM32_PLLCFGR_PLLM RCC_PLLCFGR_PLLM(6) +#define STM32_PLLCFGR_PLLP RCC_PLLCFGR_PLLPDIV(10) +#define STM32_PLLCFGR_PLLQ RCC_PLLCFGR_PLLQ_2 +#define STM32_PLLCFGR_PLLR RCC_PLLCFGR_PLLR_2 + +#define STM32_VCO_FREQUENCY ((STM32_HSI_FREQUENCY / 4) * 85) +#define STM32_PLLP_FREQUENCY (STM32_VCO_FREQUENCY / 10) +#define STM32_PLLQ_FREQUENCY (STM32_VCO_FREQUENCY / 2) +#define STM32_PLLR_FREQUENCY (STM32_VCO_FREQUENCY / 2) + +/* Use the PLL and set the SYSCLK source to be PLLR (170MHz) */ + +#define STM32_SYSCLK_SW RCC_CFGR_SW_PLL +#define STM32_SYSCLK_SWS RCC_CFGR_SWS_PLL +#define STM32_SYSCLK_FREQUENCY STM32_PLLR_FREQUENCY + +/* AHB clock (HCLK) is SYSCLK (170MHz) */ + +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY + +/* APB1 clock (PCLK1) is HCLK (170MHz) */ + +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK +#define STM32_PCLK1_FREQUENCY STM32_HCLK_FREQUENCY + +/* APB2 clock (PCLK2) is HCLK (170MHz) */ + +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK +#define STM32_PCLK2_FREQUENCY STM32_HCLK_FREQUENCY + +#endif /* CONFIG_BOARD_NUCLEO_G431RB_USE_HSE */ + +/* APB2 timers 1, 8, 20 and 15-17 will receive PCLK2. */ + +/* Timers driven from APB2 will be PCLK2 */ + +#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB1_TIM15_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB1_TIM16_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB1_TIM17_CLKIN (STM32_PCLK2_FREQUENCY) + +/* APB1 timers 2-7 will be twice PCLK1 */ + +#define STM32_APB1_TIM2_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (STM32_PCLK1_FREQUENCY) + +/* USB divider -- Divide PLL clock by 1.5 */ + +#define STM32_CFGR_USBPRE 0 + +/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx + * otherwise frequency is 2xAPBx. + */ + +#define BOARD_TIM1_FREQUENCY (STM32_PCLK2_FREQUENCY) +#define BOARD_TIM2_FREQUENCY (STM32_PCLK1_FREQUENCY) +#define BOARD_TIM3_FREQUENCY (STM32_PCLK1_FREQUENCY) +#define BOARD_TIM4_FREQUENCY (STM32_PCLK1_FREQUENCY) +#define BOARD_TIM5_FREQUENCY (STM32_PCLK1_FREQUENCY) +#define BOARD_TIM6_FREQUENCY (STM32_PCLK1_FREQUENCY) +#define BOARD_TIM7_FREQUENCY (STM32_PCLK1_FREQUENCY) +#define BOARD_TIM8_FREQUENCY (STM32_PCLK2_FREQUENCY) +#define BOARD_TIM15_FREQUENCY (STM32_PCLK2_FREQUENCY) +#define BOARD_TIM16_FREQUENCY (STM32_PCLK2_FREQUENCY) +#define BOARD_TIM17_FREQUENCY (STM32_PCLK2_FREQUENCY) +#define BOARD_TIM20_FREQUENCY (STM32_PCLK2_FREQUENCY) + +#ifdef CONFIG_STM32_FDCAN +# ifdef CONFIG_BOARD_NUCLEO_G431RB_USE_HSE +# define STM32_CCIPR_FDCANSRC (RCC_CCIPR_FDCANSEL_HSE) +# define STM32_FDCAN_FREQUENCY (STM32_HSE_FREQUENCY) +# else +# error For now FDCAN supported only if HSE enabled +# endif +#endif + +/* LED definitions **********************************************************/ + +/* The NUCLEO-G431RB has four user LEDs. + * + * If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs in + * any way. The following definitions are used to access individual LEDs. + */ + +/* LED index values for use with board_userled() */ + +#define BOARD_LED1 0 /* User LD2 */ +#define BOARD_NLEDS 1 + +/* LED bits for use with board_userled_all() */ + +#define BOARD_LED1_BIT (1 << BOARD_LED1) + +/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the LED on board + * the Nucleo G431RB. The following definitions describe how NuttX controls + * the LED: + * + * SYMBOL Meaning LED1 state + * ------------------ ----------------------- ---------- + * LED_STARTED NuttX has been started OFF + * LED_HEAPALLOCATE Heap has been allocated OFF + * LED_IRQSENABLED Interrupts enabled OFF + * LED_STACKCREATED Idle stack created ON + * LED_INIRQ In an interrupt No change + * LED_SIGNAL In a signal handler No change + * LED_ASSERTION An assertion failed No change + * LED_PANIC The system has crashed Blinking + * LED_IDLE STM32 is in sleep mode Not used + */ + +#define LED_STARTED 0 +#define LED_HEAPALLOCATE 0 +#define LED_IRQSENABLED 0 +#define LED_STACKCREATED 1 +#define LED_INIRQ 2 +#define LED_SIGNAL 2 +#define LED_ASSERTION 2 +#define LED_PANIC 1 + +/* Button definitions *******************************************************/ + +/* The Nucleo G431RB supports two buttons; only one button is controllable + * by software: + * + * B1 USER: user button connected to the I/O PC13 of the STM32G431RB. + * B2 RESET: push button connected to NRST is used to RESET the + * STM32G431RB. + */ + +#define BUTTON_USER 0 +#define NUM_BUTTONS 1 + +#define BUTTON_USER_BIT (1 << BUTTON_USER) + +/* Alternate function pin selections ****************************************/ + +/* TIM2 input ***************************************************************/ + +#define GPIO_TIM2_CH1IN (GPIO_TIM2_CH1IN_3 | GPIO_PULLUP | GPIO_SPEED_50MHz) /* PA15 */ +#define GPIO_TIM2_CH2IN (GPIO_TIM2_CH2IN_2 | GPIO_PULLUP | GPIO_SPEED_50MHz) /* PB3 */ + +/* USART2 (STLINK Virtual COM Port) */ + +#define GPIO_USART2_TX GPIO_USART2_TX_1 /* PA2 */ +#define GPIO_USART2_RX GPIO_USART2_RX_1 /* PA3 */ + +/* PWM configuration ********************************************************/ + +/* TIM1 PWM */ + +#define GPIO_TIM1_CH1OUT (GPIO_TIM1_CH1OUT_1|GPIO_SPEED_50MHz) /* PA8 */ +#define GPIO_TIM1_CH1NOUT (GPIO_TIM1_CH1NOUT_2|GPIO_SPEED_50MHz) /* PA11 */ +#define GPIO_TIM1_CH2OUT (GPIO_TIM1_CH2OUT_1|GPIO_SPEED_50MHz) /* PA9 */ +#define GPIO_TIM1_CH2NOUT (GPIO_TIM1_CH2NOUT_1|GPIO_SPEED_50MHz) /* PA12 */ +#define GPIO_TIM1_CH3OUT (GPIO_TIM1_CH3OUT_1|GPIO_SPEED_50MHz) /* PA10 */ +#define GPIO_TIM1_CH3NOUT (GPIO_TIM1_CH3NOUT_1|GPIO_SPEED_50MHz) /* PB1 */ +#define GPIO_TIM1_CH4OUT (GPIO_TIM1_CH4OUT_2|GPIO_SPEED_50MHz) /* PC3 */ + +/* CAN configuration ********************************************************/ + +#define GPIO_FDCAN1_RX (GPIO_FDCAN1_RX_2|GPIO_SPEED_50MHz) /* PB8 */ +#define GPIO_FDCAN1_TX (GPIO_FDCAN1_TX_2|GPIO_SPEED_50MHz) /* PB9 */ + +/* DMA channels *************************************************************/ + +/* ADC */ + +#define ADC1_DMA_CHAN DMAMAP_DMA12_ADC1_0 /* DMA1 */ + +/* USART2 */ + +#define DMACHAN_USART2_TX DMAMAP_DMA12_USART2TX_0 /* DMA1 */ +#define DMACHAN_USART2_RX DMAMAP_DMA12_USART2RX_0 /* DMA1 */ + +#ifdef CONFIG_BOARD_STM32_IHM16M1 + +/* Configuration specific for the X-NUCLEO-IHM16M1 expansion board with + * the STSPIN830 driver. + */ + +/* TIM1 configuration *******************************************************/ + +# define GPIO_TIM1_CH1OUT (GPIO_TIM1_CH1OUT_1|GPIO_SPEED_50MHz) /* TIM1 CH1 - PA8 - U high */ +# define GPIO_TIM1_CH2OUT (GPIO_TIM1_CH2OUT_1|GPIO_SPEED_50MHz) /* TIM1 CH2 - PA9 - V high */ +# define GPIO_TIM1_CH3OUT (GPIO_TIM1_CH3OUT_1|GPIO_SPEED_50MHz) /* TIM1 CH3 - PA10 - W high */ +# define GPIO_TIM1_CH4OUT 0 /* not used as output */ + +/* UVW ENABLE */ + +# define GPIO_FOC_EN_U (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz| \ + GPIO_OUTPUT_CLEAR|GPIO_PORTB|GPIO_PIN13) +# define GPIO_FOC_EN_V (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz| \ + GPIO_OUTPUT_CLEAR|GPIO_PORTB|GPIO_PIN14) +# define GPIO_FOC_EN_W (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz| \ + GPIO_OUTPUT_CLEAR|GPIO_PORTB|GPIO_PIN15) + +/* EN_FAULT */ + +# define GPIO_FOC_ENFAULT (GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz| \ + GPIO_OUTPUT_CLEAR|GPIO_PORTB|GPIO_PIN12) + +/* Debug pins */ + +# define GPIO_FOC_DEBUG0 (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz| \ + GPIO_OUTPUT_CLEAR|GPIO_PORTB|GPIO_PIN8) +# define GPIO_FOC_DEBUG1 (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz| \ + GPIO_OUTPUT_CLEAR|GPIO_PORTB|GPIO_PIN9) +# define GPIO_FOC_DEBUG2 (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz| \ + GPIO_OUTPUT_CLEAR|GPIO_PORTC|GPIO_PIN6) +# define GPIO_FOC_DEBUG3 (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz| \ + GPIO_OUTPUT_CLEAR|GPIO_PORTA|GPIO_PIN12) + +#endif /* CONFIG_BOARD_STM32_IHM16M1 */ + +#endif /* __BOARDS_ARM_STM32_NUCLEO_G431RB_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32g4/nucleo-g431rb/scripts/Make.defs b/boards/arm/stm32g4/nucleo-g431rb/scripts/Make.defs new file mode 100644 index 0000000000000..2eb0f2b84635d --- /dev/null +++ b/boards/arm/stm32g4/nucleo-g431rb/scripts/Make.defs @@ -0,0 +1,51 @@ +############################################################################ +# boards/arm/stm32g4/nucleo-g431rb/scripts/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/.config +include $(TOPDIR)/tools/Config.mk +include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs + +ifeq ($(CONFIG_STM32_DFU),y) + LDSCRIPT = ld.script.dfu +else + LDSCRIPT = ld.script +endif + +ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) + +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 + +# Embed absolute path to source file in debug information so that Eclipse +# source level debugging won't get confused. See: +# https://stackoverflow.com/questions/1275476/gcc-gdb-how-to-embed-absolute-path-to-source-file-in-debug-information +CFLAGS += -fdebug-prefix-map=..=$(readlink -f ..) diff --git a/boards/arm/stm32g4/nucleo-g431rb/scripts/ld.script b/boards/arm/stm32g4/nucleo-g431rb/scripts/ld.script new file mode 100644 index 0000000000000..bd82a15d578b7 --- /dev/null +++ b/boards/arm/stm32g4/nucleo-g431rb/scripts/ld.script @@ -0,0 +1,139 @@ +/**************************************************************************** + * boards/arm/stm32g4/nucleo-g431rb/scripts/ld.script + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* The STM32G431RB has 128 KiB of FLASH beginning at address 0x0800:0000. + * + * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 + * where the code expects to begin execution by jumping to the entry point in + * the 0x0800:0000 address range. + * + * The STM32G431RB has a total of 32 KiB of SRAM in three separate areas: + * + * 1) 16 KiB SRAM1 mapped at 0x2000:0000 thru 0x2000:3fff. + * 2) 6 KiB SRAM2 mapped at 0x2000:4000 thru 0x2000:57ff. + * + * CCM SRAM (Routine Booster): + * + * 3) 10 KiB CCM SRAM mapped at 0x1000:0000 thru 0x1000:27ff + * but also aliased at at 0x2000:5800 thru 0x2000:7fff to be contiguous + * with the SRAM1 and SRAM2. + * + * Because SRAM1 and SRAM2 are contiguous, they are treated as one region + * by this logic. + * + * CCM SRAM is also contiguous to SRAM1 and SRAM2, however it is excluded + * from this linker script, to keep it reserved for special uses in code. + * REVISIT: Is this the correct way to handle CCM SRAM? + */ + +MEMORY +{ + flash (rx) : ORIGIN = 0x08000000, LENGTH = 128K + sram (rwx) : ORIGIN = 0x20000000, LENGTH = 22K +} + +OUTPUT_ARCH(arm) +EXTERN(_vectors) +ENTRY(_stext) + +SECTIONS +{ + .text : { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > flash + + .init_section : ALIGN(4) { + _sinit = ABSOLUTE(.); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) + _einit = ABSOLUTE(.); + } > flash + + .ARM.extab : ALIGN(4) { + *(.ARM.extab*) + } > flash + + .ARM.exidx : ALIGN(4) { + __exidx_start = ABSOLUTE(.); + *(.ARM.exidx*) + __exidx_end = ABSOLUTE(.); + } > flash + + .tdata : { + _stdata = ABSOLUTE(.); + *(.tdata .tdata.* .gnu.linkonce.td.*); + _etdata = ABSOLUTE(.); + } > flash + + .tbss : { + _stbss = ABSOLUTE(.); + *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); + _etbss = ABSOLUTE(.); + } > flash + + _eronly = ABSOLUTE(.); + + .data : ALIGN(4) { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > sram AT > flash + + .bss : ALIGN(4) { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + _ebss = ABSOLUTE(.); + } > sram + + /* Stabs debugging sections. */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/stm32/nucleo-g431rb/src/.gitignore b/boards/arm/stm32g4/nucleo-g431rb/src/.gitignore similarity index 100% rename from boards/arm/stm32/nucleo-g431rb/src/.gitignore rename to boards/arm/stm32g4/nucleo-g431rb/src/.gitignore diff --git a/boards/arm/stm32g4/nucleo-g431rb/src/CMakeLists.txt b/boards/arm/stm32g4/nucleo-g431rb/src/CMakeLists.txt new file mode 100644 index 0000000000000..21262028d4494 --- /dev/null +++ b/boards/arm/stm32g4/nucleo-g431rb/src/CMakeLists.txt @@ -0,0 +1,64 @@ +# ############################################################################## +# boards/arm/stm32g4/nucleo-g431rb/src/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(SRCS stm32_boot.c stm32_bringup.c) + +if(CONFIG_ARCH_LEDS) + list(APPEND SRCS stm32_autoleds.c) +else() + list(APPEND SRCS stm32_userleds.c) +endif() + +if(CONFIG_ARCH_BUTTONS) + list(APPEND SRCS stm32_buttons.c) +endif() + +if(NOT CONFIG_STM32_FOC) + if(CONFIG_PWM) + list(APPEND SRCS stm32_pwm.c) + endif() + + if(CONFIG_ADC) + list(APPEND SRCS stm32_adc.c) + endif() +endif() + +if(CONFIG_BOARD_STM32_IHM16M1) + list(APPEND SRCS stm32_foc_ihm16m1.c) +endif() + +if(CONFIG_MATH_CORDIC) + list(APPEND SRCS stm32_cordic.c) +endif() + +if(CONFIG_STM32_FDCAN) + if(CONFIG_STM32_FDCAN_CHARDRIVER) + list(APPEND SRCS stm32_can.c) + endif() + if(CONFIG_STM32_FDCAN_SOCKET) + list(APPEND SRCS stm32_cansock.c) + endif() +endif() + +target_sources(board PRIVATE ${SRCS}) + +set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/ld.script") diff --git a/boards/arm/stm32g4/nucleo-g431rb/src/Make.defs b/boards/arm/stm32g4/nucleo-g431rb/src/Make.defs new file mode 100644 index 0000000000000..17328e8d98967 --- /dev/null +++ b/boards/arm/stm32g4/nucleo-g431rb/src/Make.defs @@ -0,0 +1,67 @@ +############################################################################ +# boards/arm/stm32g4/nucleo-g431rb/src/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +ASRCS = +CSRCS = stm32_boot.c stm32_bringup.c + +ifeq ($(CONFIG_ARCH_LEDS),y) +CSRCS += stm32_autoleds.c +else +CSRCS += stm32_userleds.c +endif + +ifeq ($(CONFIG_ARCH_BUTTONS),y) +CSRCS += stm32_buttons.c +endif + +ifneq ($(CONFIG_STM32_FOC),y) +ifeq ($(CONFIG_PWM),y) +CSRCS += stm32_pwm.c +endif + +ifeq ($(CONFIG_ADC),y) +CSRCS += stm32_adc.c +endif +endif + +ifeq ($(CONFIG_BOARD_STM32_IHM16M1),y) +CSRCS += stm32_foc_ihm16m1.c +endif + +ifeq ($(CONFIG_MATH_CORDIC),y) +CSRCS += stm32_cordic.c +endif + +ifeq ($(CONFIG_STM32_FDCAN),y) +ifeq ($(CONFIG_STM32_FDCAN_CHARDRIVER),y) +CSRCS += stm32_can.c +endif +ifeq ($(CONFIG_STM32_FDCAN_SOCKET),y) +CSRCS += stm32_cansock.c +endif +endif + +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/nucleo-g431rb/src/nucleo-g431rb.h b/boards/arm/stm32g4/nucleo-g431rb/src/nucleo-g431rb.h similarity index 99% rename from boards/arm/stm32/nucleo-g431rb/src/nucleo-g431rb.h rename to boards/arm/stm32g4/nucleo-g431rb/src/nucleo-g431rb.h index a00571f7c2ead..c1aab3f25c279 100644 --- a/boards/arm/stm32/nucleo-g431rb/src/nucleo-g431rb.h +++ b/boards/arm/stm32g4/nucleo-g431rb/src/nucleo-g431rb.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-g431rb/src/nucleo-g431rb.h + * boards/arm/stm32g4/nucleo-g431rb/src/nucleo-g431rb.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32g4/nucleo-g431rb/src/stm32_adc.c b/boards/arm/stm32g4/nucleo-g431rb/src/stm32_adc.c new file mode 100644 index 0000000000000..23dcbdf7b6e57 --- /dev/null +++ b/boards/arm/stm32g4/nucleo-g431rb/src/stm32_adc.c @@ -0,0 +1,240 @@ +/**************************************************************************** + * boards/arm/stm32g4/nucleo-g431rb/src/stm32_adc.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "stm32.h" + +#if defined(CONFIG_ADC) && (defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2)) + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* 1 or 2 ADC devices (DEV1, DEV2) */ + +#if defined(CONFIG_STM32_ADC1) +# define DEV1_PORT 1 +#endif + +#if defined(CONFIG_STM32_ADC2) +# if defined(DEV1_PORT) +# define DEV2_PORT 2 +# else +# define DEV1_PORT 2 +# endif +#endif + +/* The number of ADC channels in the conversion list */ + +#define ADC1_NCHANNELS 3 +#define ADC2_NCHANNELS 3 + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* DEV 1 */ + +#if DEV1_PORT == 1 + +#define DEV1_NCHANNELS ADC1_NCHANNELS + +/* Identifying number of each ADC channel (even if NCHANNELS is less ) */ + +static const uint8_t g_chanlist1[3] = +{ + 1, + 2, + 15 +}; + +/* Configurations of pins used by each ADC channel */ + +static const uint32_t g_pinlist1[3] = +{ + GPIO_ADC1_IN1_0, /* PA0/A0 */ + GPIO_ADC1_IN2_0, /* PA1/A1 */ + GPIO_ADC1_IN15_0, /* PB0/A3 */ +}; + +#elif DEV1_PORT == 2 + +#define DEV1_NCHANNELS ADC2_NCHANNELS + +/* Identifying number of each ADC channel */ + +static const uint8_t g_chanlist1[3] = +{ + 17, + 7, + 6 +}; + +/* Configurations of pins used by each ADC channel */ + +static const uint32_t g_pinlist1[3] = +{ + GPIO_ADC2_IN17_0, /* PA4/A2 */ + GPIO_ADC2_IN7_0, /* PC1/A4 */ + GPIO_ADC2_IN6_0, /* PC0/A5 */ +}; + +#endif /* DEV1_PORT == 1 */ + +#ifdef DEV2_PORT + +/* DEV 2 */ + +#if DEV2_PORT == 2 + +#define DEV2_NCHANNELS ADC2_NCHANNELS + +/* Identifying number of each ADC channel */ + +static const uint8_t g_chanlist2[3] = +{ + 17, + 7, + 6 +}; + +/* Configurations of pins used by each ADC channel */ + +static const uint32_t g_pinlist2[3] = +{ + GPIO_ADC2_IN17_0, /* PA4/A2 */ + GPIO_ADC2_IN7_0, /* PC1/A4 */ + GPIO_ADC2_IN6_0, /* PC0/A5 */ +}; + +#endif /* DEV2_PORT == 2 */ +#endif /* DEV2_PORT */ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_adc_setup + * + * Description: + * Initialize ADC and register the ADC driver. + * + ****************************************************************************/ + +int stm32_adc_setup(void) +{ + static bool initialized = false; + struct adc_dev_s *adc; + int ret; + int i; + + /* Check if we have already initialized */ + + if (!initialized) + { + /* DEV1 */ + + /* Configure the pins as analog inputs for the selected channels */ + + for (i = 0; i < DEV1_NCHANNELS; i++) + { + stm32_configgpio(g_pinlist1[i]); + } + + /* Call stm32_adcinitialize() to get an instance of the ADC interface */ + + adc = stm32_adcinitialize(DEV1_PORT, g_chanlist1, DEV1_NCHANNELS); + if (adc == NULL) + { + aerr("Failed to get ADC interface 1\n"); + return -ENODEV; + } + + /* Register the ADC driver at "/dev/adc0" */ + + ret = adc_register("/dev/adc0", adc); + if (ret < 0) + { + aerr("adc_register /dev/adc0 failed: %d\n", ret); + return ret; + } + +#ifdef DEV2_PORT + + /* DEV2 */ + + /* Configure the pins as analog inputs for the selected channels */ + + for (i = 0; i < DEV2_NCHANNELS; i++) + { + stm32_configgpio(g_pinlist2[i]); + } + + /* Call stm32_adcinitialize() to get an instance of the ADC interface */ + + adc = stm32_adcinitialize(DEV2_PORT, g_chanlist2, DEV2_NCHANNELS); + if (adc == NULL) + { + aerr("Failed to get ADC interface 2\n"); + return -ENODEV; + } + + /* Register the ADC driver at "/dev/adc1" */ + + ret = adc_register("/dev/adc1", adc); + if (ret < 0) + { + aerr("adc_register /dev/adc1 failed: %d\n", ret); + return ret; + } +#endif + + initialized = true; + } + + return OK; +} + +#endif /* CONFIG_ADC && (CONFIG_STM32_ADC1 || CONFIG_STM32_ADC2) */ diff --git a/boards/arm/stm32g4/nucleo-g431rb/src/stm32_autoleds.c b/boards/arm/stm32g4/nucleo-g431rb/src/stm32_autoleds.c new file mode 100644 index 0000000000000..74c7bf61f79cf --- /dev/null +++ b/boards/arm/stm32g4/nucleo-g431rb/src/stm32_autoleds.c @@ -0,0 +1,80 @@ +/**************************************************************************** + * boards/arm/stm32g4/nucleo-g431rb/src/stm32_autoleds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "stm32.h" +#include "nucleo-g431rb.h" + +#if defined(CONFIG_ARCH_LEDS) + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_autoled_initialize + ****************************************************************************/ + +void board_autoled_initialize(void) +{ + /* Configure LED GPIOs for output */ + + stm32_configgpio(GPIO_LED1); +} + +/**************************************************************************** + * Name: board_autoled_on + ****************************************************************************/ + +void board_autoled_on(int led) +{ + if (led == BOARD_LED1) + { + stm32_gpiowrite(GPIO_LED1, true); + } +} + +/**************************************************************************** + * Name: board_autoled_off + ****************************************************************************/ + +void board_autoled_off(int led) +{ + if (led == BOARD_LED1) + { + stm32_gpiowrite(GPIO_LED1, false); + } +} + +#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32g4/nucleo-g431rb/src/stm32_boot.c b/boards/arm/stm32g4/nucleo-g431rb/src/stm32_boot.c new file mode 100644 index 0000000000000..8f5ac067df973 --- /dev/null +++ b/boards/arm/stm32g4/nucleo-g431rb/src/stm32_boot.c @@ -0,0 +1,95 @@ +/**************************************************************************** + * boards/arm/stm32g4/nucleo-g431rb/src/stm32_boot.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include "nucleo-g431rb.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_boardinitialize + * + * Description: + * All STM32 architectures must provide the following entry point. This + * entry point is called early in the initialization -- after all memory + * has been configured and mapped but before any devices have been + * initialized. + * + ****************************************************************************/ + +void stm32_boardinitialize(void) +{ + /* Configure on-board LEDs if LED support has been selected. */ + +#ifdef CONFIG_ARCH_LEDS + board_autoled_initialize(); +#endif +} + +/**************************************************************************** + * Name: board_late_initialize + * + * Description: + * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_late_initialize(). board_late_initialize() will + * be called immediately after up_initialize() is called and just before + * the initial application is started. This additional initialization + * phase may be used, for example, to initialize board-specific device + * drivers. + * + ****************************************************************************/ + +#ifdef CONFIG_BOARD_LATE_INITIALIZE +void board_late_initialize(void) +{ + /* Perform board-specific initialization */ + + stm32_bringup(); +} +#endif diff --git a/boards/arm/stm32g4/nucleo-g431rb/src/stm32_bringup.c b/boards/arm/stm32g4/nucleo-g431rb/src/stm32_bringup.c new file mode 100644 index 0000000000000..82b3a8be71f0b --- /dev/null +++ b/boards/arm/stm32g4/nucleo-g431rb/src/stm32_bringup.c @@ -0,0 +1,185 @@ +/**************************************************************************** + * boards/arm/stm32g4/nucleo-g431rb/src/stm32_bringup.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include + +#ifdef CONFIG_USERLED +# include +#endif + +#ifdef CONFIG_INPUT_BUTTONS +# include +#endif + +#ifdef CONFIG_SENSORS_QENCODER +# include "board_qencoder.h" +#endif + +#include "nucleo-g431rb.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#undef HAVE_LEDS + +#if !defined(CONFIG_ARCH_LEDS) && defined(CONFIG_USERLED_LOWER) +# define HAVE_LEDS 1 +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_bringup + * + * Description: + * Perform architecture-specific initialization + * + * CONFIG_BOARD_LATE_INITIALIZE=y : + * Called from board_late_initialize(). + * + ****************************************************************************/ + +int stm32_bringup(void) +{ + int ret; + +#ifdef CONFIG_FS_PROCFS + /* Mount the procfs file system */ + + ret = nx_mount(NULL, STM32_PROCFS_MOUNTPOINT, "procfs", 0, NULL); + if (ret < 0) + { + syslog(LOG_ERR, + "ERROR: Failed to mount the PROC filesystem: %d\n", ret); + } +#endif /* CONFIG_FS_PROCFS */ + +#ifdef CONFIG_INPUT_BUTTONS + /* Register the BUTTON driver */ + + ret = btn_lower_initialize("/dev/buttons"); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: btn_lower_initialize() failed: %d\n", ret); + } +#endif + +#ifdef HAVE_LEDS + /* Register the LED driver */ + + ret = userled_lower_initialize(LED_DRIVER_PATH); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: userled_lower_initialize() failed: %d\n", ret); + return ret; + } +#endif + +#ifdef CONFIG_PWM + /* Initialize PWM and register the PWM driver. */ + + ret = stm32_pwm_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_pwm_setup failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_STM32_FOC + /* Initialize and register the FOC device - must be before ADC setup */ + + ret = stm32_foc_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_foc_setup failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_ADC + /* Initialize ADC and register the ADC driver. */ + + ret = stm32_adc_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_adc_setup failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_MATH_CORDIC + /* Initialize CORDIC and register the CORDIC driver. */ + + ret = stm32_cordic_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_cordic_setup failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_SENSORS_QENCODER + /* Initialize and register the qencoder driver */ + + ret = board_qencoder_initialize(0, CONFIG_NUCLEO_G431RB_QETIMER); + if (ret != OK) + { + syslog(LOG_ERR, + "ERROR: Failed to register the qencoder: %d\n", + ret); + return ret; + } +#endif + +#ifdef CONFIG_STM32_FDCAN_CHARDRIVER + /* Initialize CAN and register the CAN driver. */ + + ret = stm32_can_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_fdcan_setup failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_STM32_FDCAN_SOCKET + /* Initialize CAN socket interface */ + + ret = stm32_cansock_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_cansock_setup failed: %d\n", ret); + } +#endif + + UNUSED(ret); + return OK; +} diff --git a/boards/arm/stm32g4/nucleo-g431rb/src/stm32_buttons.c b/boards/arm/stm32g4/nucleo-g431rb/src/stm32_buttons.c new file mode 100644 index 0000000000000..f6bf2f0c90ff9 --- /dev/null +++ b/boards/arm/stm32g4/nucleo-g431rb/src/stm32_buttons.c @@ -0,0 +1,113 @@ +/**************************************************************************** + * boards/arm/stm32g4/nucleo-g431rb/src/stm32_buttons.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "stm32.h" +#include "nucleo-g431rb.h" + +#ifdef CONFIG_ARCH_BUTTONS + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_button_initialize + * + * Description: + * board_button_initialize() must be called to initialize button + * resources. After that, board_buttons() may be called to collect the + * current state of all buttons or board_button_irq() may be called to + * register button interrupt handlers. + * + ****************************************************************************/ + +uint32_t board_button_initialize(void) +{ + /* Configure the single button as an input. NOTE that EXTI interrupts are + * also configured for the pin. + */ + + stm32_configgpio(GPIO_BTN_USER); + return NUM_BUTTONS; +} + +/**************************************************************************** + * Name: board_buttons + * + * Description: + * After board_button_initialize() has been called, board_buttons() may be + * called to collect the state of all buttons. board_buttons() returns an + * 32-bit unsigned integer with each bit associated with a button. See the + * BUTTON_*_BIT definitions in board.h for the meaning of each bit. + * + ****************************************************************************/ + +uint32_t board_buttons(void) +{ + /* Check the state of the USER button. A HIGH value means that the key is + * pressed. + */ + + return stm32_gpioread(GPIO_BTN_USER) ? BUTTON_USER_BIT : 0; +} + +/**************************************************************************** + * Name: board_button_irq + * + * Description: + * board_button_irq() may be called to register an interrupt handler that + * will be called when a button is depressed or released. The ID value is + * a button enumeration value that uniquely identifies a button resource. + * See the BUTTON_* definitions in board.h for the meaning of the + * enumeration value. + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_IRQBUTTONS +int board_button_irq(int id, xcpt_t irqhandler, void *arg) +{ + int ret = -EINVAL; + + if (id == BUTTON_USER) + { + ret = stm32_gpiosetevent(GPIO_BTN_USER, true, true, true, irqhandler, + arg); + } + + return ret; +} +#endif + +#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/stm32g4/nucleo-g431rb/src/stm32_can.c b/boards/arm/stm32g4/nucleo-g431rb/src/stm32_can.c new file mode 100644 index 0000000000000..5a91c6e2fe0f6 --- /dev/null +++ b/boards/arm/stm32g4/nucleo-g431rb/src/stm32_can.c @@ -0,0 +1,91 @@ +/**************************************************************************** + * boards/arm/stm32g4/nucleo-g431rb/src/stm32_can.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32.h" +#include "stm32_fdcan.h" +#include "nucleo-g431rb.h" + +#ifdef CONFIG_CAN + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +#if !defined(CONFIG_STM32_FDCAN1) +# error "No CAN is enable. Please enable at least one CAN device" +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_can_setup + * + * Description: + * Initialize CAN and register the CAN device + * + ****************************************************************************/ + +int stm32_can_setup(void) +{ + struct can_dev_s *can; + int ret; + + /* Call stm32_fdcaninitialize() to get an instance of the CAN interface */ + + can = stm32_fdcaninitialize(1); + if (can == NULL) + { + canerr("ERROR: Failed to get CAN interface\n"); + return -ENODEV; + } + + /* Register the CAN driver at "/dev/can0" */ + + ret = can_register("/dev/can0", can); + if (ret < 0) + { + canerr("ERROR: can_register failed: %d\n", ret); + return ret; + } + + return OK; +} + +#endif /* CONFIG_CAN */ diff --git a/boards/arm/stm32g4/nucleo-g431rb/src/stm32_cansock.c b/boards/arm/stm32g4/nucleo-g431rb/src/stm32_cansock.c new file mode 100644 index 0000000000000..c76c3ce5b2add --- /dev/null +++ b/boards/arm/stm32g4/nucleo-g431rb/src/stm32_cansock.c @@ -0,0 +1,59 @@ +/**************************************************************************** + * boards/arm/stm32g4/nucleo-g431rb/src/stm32_cansock.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include "stm32_fdcan.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_cansock_setup + * + * Description: + * Initialize CAN socket interface + * + ****************************************************************************/ + +int stm32_cansock_setup(void) +{ + int ret; + + /* Call stm32_fdcaninitialize() to get an instance of the FDCAN interface */ + + ret = stm32_fdcansockinitialize(1); + if (ret < 0) + { + canerr("ERROR: Failed to get FDCAN interface %d\n", ret); + return ret; + } + + return OK; +} diff --git a/boards/arm/stm32g4/nucleo-g431rb/src/stm32_cordic.c b/boards/arm/stm32g4/nucleo-g431rb/src/stm32_cordic.c new file mode 100644 index 0000000000000..9318847fd2d55 --- /dev/null +++ b/boards/arm/stm32g4/nucleo-g431rb/src/stm32_cordic.c @@ -0,0 +1,89 @@ +/**************************************************************************** + * boards/arm/stm32g4/nucleo-g431rb/src/stm32_cordic.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include + +#include "stm32_cordic.h" + +#include "nucleo-g431rb.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_cordic_setup + * + * Description: + * Initialize CORDIC and register the CORDIC device. + * + ****************************************************************************/ + +int stm32_cordic_setup(void) +{ + struct cordic_lowerhalf_s *cordic = NULL; + static bool initialized = false; + int ret = OK; + + /* Have we already initialized? */ + + if (!initialized) + { + /* Call stm32_cordicinitialize() to get an instance of the CORDIC + * interface + */ + + cordic = stm32_cordicinitialize(); + if (!cordic) + { + tmrerr("Failed to get the STM32 CORDIC lower half\n"); + ret = -ENODEV; + goto errout; + } + + /* Register the CORDIC driver at "/dev/cordic0" */ + + ret = cordic_register("/dev/cordic0", cordic); + if (ret < 0) + { + tmrerr("cordic_register failed: %d\n", ret); + goto errout; + } + + /* Now we are initialized */ + + initialized = true; + } + +errout: + return ret; +} diff --git a/boards/arm/stm32/nucleo-g431rb/src/stm32_foc_ihm16m1.c b/boards/arm/stm32g4/nucleo-g431rb/src/stm32_foc_ihm16m1.c similarity index 98% rename from boards/arm/stm32/nucleo-g431rb/src/stm32_foc_ihm16m1.c rename to boards/arm/stm32g4/nucleo-g431rb/src/stm32_foc_ihm16m1.c index 73316003dd0e7..bf5f99735eb70 100644 --- a/boards/arm/stm32/nucleo-g431rb/src/stm32_foc_ihm16m1.c +++ b/boards/arm/stm32g4/nucleo-g431rb/src/stm32_foc_ihm16m1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-g431rb/src/stm32_foc_ihm16m1.c + * boards/arm/stm32g4/nucleo-g431rb/src/stm32_foc_ihm16m1.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32g4/nucleo-g431rb/src/stm32_pwm.c b/boards/arm/stm32g4/nucleo-g431rb/src/stm32_pwm.c new file mode 100644 index 0000000000000..c91702c323e3e --- /dev/null +++ b/boards/arm/stm32g4/nucleo-g431rb/src/stm32_pwm.c @@ -0,0 +1,86 @@ +/**************************************************************************** + * boards/arm/stm32g4/nucleo-g431rb/src/stm32_pwm.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32_pwm.h" +#include "nucleo-g431rb.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_pwm_setup + * + * Description: + * Initialize PWM and register the PWM device. + * + ****************************************************************************/ + +int stm32_pwm_setup(void) +{ + static bool initialized = false; + struct pwm_lowerhalf_s *pwm; + int ret; + + /* Have we already initialized? */ + + if (!initialized) + { + /* Call stm32_pwminitialize() to get an instance of the PWM interface */ + + pwm = stm32_pwminitialize(NUCLEOG431RB_PWMTIMER); + if (!pwm) + { + tmrerr("Failed to get the STM32 PWM lower half\n"); + return -ENODEV; + } + + /* Register the PWM driver at "/dev/pwm0" */ + + ret = pwm_register("/dev/pwm0", pwm); + if (ret < 0) + { + tmrerr("pwm_register failed: %d\n", ret); + return ret; + } + + /* Now we are initialized */ + + initialized = true; + } + + return OK; +} diff --git a/boards/arm/stm32g4/nucleo-g431rb/src/stm32_userleds.c b/boards/arm/stm32g4/nucleo-g431rb/src/stm32_userleds.c new file mode 100644 index 0000000000000..6d6bc7e72b0da --- /dev/null +++ b/boards/arm/stm32g4/nucleo-g431rb/src/stm32_userleds.c @@ -0,0 +1,77 @@ +/**************************************************************************** + * boards/arm/stm32g4/nucleo-g431rb/src/stm32_userleds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include + +#include "stm32.h" +#include "nucleo-g431rb.h" + +#if !defined(CONFIG_ARCH_LEDS) + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_userled_initialize + ****************************************************************************/ + +uint32_t board_userled_initialize(void) +{ + /* Configure LED GPIOs for output */ + + stm32_configgpio(GPIO_LED1); + return BOARD_NLEDS; +} + +/**************************************************************************** + * Name: board_userled + ****************************************************************************/ + +void board_userled(int led, bool ledon) +{ + if (led == BOARD_LED1) + { + stm32_gpiowrite(GPIO_LED1, ledon); + } +} + +/**************************************************************************** + * Name: board_userled_all + ****************************************************************************/ + +void board_userled_all(uint32_t ledset) +{ + stm32_gpiowrite(GPIO_LED1, (ledset & BOARD_LED1_BIT) != 0); +} + +#endif /* !CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32g4/nucleo-g474re/CMakeLists.txt b/boards/arm/stm32g4/nucleo-g474re/CMakeLists.txt new file mode 100644 index 0000000000000..4f4bba4b7afca --- /dev/null +++ b/boards/arm/stm32g4/nucleo-g474re/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32g4/nucleo-g474re/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/arm/stm32/nucleo-g474re/Kconfig b/boards/arm/stm32g4/nucleo-g474re/Kconfig similarity index 100% rename from boards/arm/stm32/nucleo-g474re/Kconfig rename to boards/arm/stm32g4/nucleo-g474re/Kconfig diff --git a/boards/arm/stm32g4/nucleo-g474re/configs/lpuartnsh/defconfig b/boards/arm/stm32g4/nucleo-g474re/configs/lpuartnsh/defconfig new file mode 100644 index 0000000000000..ee2a8c2db94c2 --- /dev/null +++ b/boards/arm/stm32g4/nucleo-g474re/configs/lpuartnsh/defconfig @@ -0,0 +1,47 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_LEDS is not set +# CONFIG_DISABLE_OS_API is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nucleo-g474re" +CONFIG_ARCH_BOARD_NUCLEO_G474RE=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32g4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32G474R=y +CONFIG_ARCH_CHIP_STM32G4=y +CONFIG_ARCH_HIPRI_INTERRUPT=y +CONFIG_ARCH_RAMVECTORS=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_ARMV7M_LIBM=y +CONFIG_ARMV7M_MEMCPY=y +CONFIG_BOARD_LOOPSPERMSEC=0 +CONFIG_DEBUG_FEATURES=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_LIBM=y +CONFIG_LINE_MAX=64 +CONFIG_LPUART1_SERIAL_CONSOLE=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PRIORITY_INHERITANCE=y +CONFIG_RAM_SIZE=98304 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_LPWORK=y +CONFIG_SCHED_WAITPID=y +CONFIG_STM32_DMA1=y +CONFIG_STM32_DMA2=y +CONFIG_STM32_DMAMUX1=y +CONFIG_STM32_FLASH_CONFIG_E=y +CONFIG_STM32_LPUART1=y +CONFIG_STM32_USART3=y +CONFIG_SYSTEM_NSH=y +CONFIG_USERLED=y +CONFIG_USERLED_LOWER=y diff --git a/boards/arm/stm32g4/nucleo-g474re/configs/nsh/defconfig b/boards/arm/stm32g4/nucleo-g474re/configs/nsh/defconfig new file mode 100644 index 0000000000000..6a8c6317f5719 --- /dev/null +++ b/boards/arm/stm32g4/nucleo-g474re/configs/nsh/defconfig @@ -0,0 +1,42 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_LEDS is not set +# CONFIG_DISABLE_OS_API is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nucleo-g474re" +CONFIG_ARCH_BOARD_NUCLEO_G474RE=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32g4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32G474R=y +CONFIG_ARCH_CHIP_STM32G4=y +CONFIG_ARCH_HIPRI_INTERRUPT=y +CONFIG_ARCH_RAMVECTORS=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_ARMV7M_LIBM=y +CONFIG_ARMV7M_MEMCPY=y +CONFIG_BOARD_LOOPSPERMSEC=0 +CONFIG_DEBUG_FEATURES=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_LIBM=y +CONFIG_LINE_MAX=64 +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PRIORITY_INHERITANCE=y +CONFIG_RAM_SIZE=98304 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_LPWORK=y +CONFIG_SCHED_WAITPID=y +CONFIG_STM32_USART3=y +CONFIG_SYSTEM_NSH=y +CONFIG_USART3_SERIAL_CONSOLE=y +CONFIG_USERLED=y +CONFIG_USERLED_LOWER=y diff --git a/boards/arm/stm32g4/nucleo-g474re/configs/usbserial/defconfig b/boards/arm/stm32g4/nucleo-g474re/configs/usbserial/defconfig new file mode 100644 index 0000000000000..405eabc8cdb02 --- /dev/null +++ b/boards/arm/stm32g4/nucleo-g474re/configs/usbserial/defconfig @@ -0,0 +1,52 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_LEDS is not set +# CONFIG_DISABLE_OS_API is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nucleo-g474re" +CONFIG_ARCH_BOARD_NUCLEO_G474RE=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32g4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32G474R=y +CONFIG_ARCH_CHIP_STM32G4=y +CONFIG_ARCH_HIPRI_INTERRUPT=y +CONFIG_ARCH_RAMVECTORS=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_ARMV7M_LIBM=y +CONFIG_ARMV7M_MEMCPY=y +CONFIG_BOARD_LOOPSPERMSEC=0 +CONFIG_CDCACM=y +CONFIG_DEBUG_FEATURES=y +CONFIG_DEBUG_HARDFAULT_INFO=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_DEBUG_USB=y +CONFIG_DEBUG_USB_ERROR=y +CONFIG_DEBUG_USB_WARN=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_LIBM=y +CONFIG_LINE_MAX=64 +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PRIORITY_INHERITANCE=y +CONFIG_RAM_SIZE=98304 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_LPWORK=y +CONFIG_SCHED_WAITPID=y +CONFIG_STM32_USART3=y +CONFIG_STM32_USBFS=y +CONFIG_SYSTEM_NSH=y +CONFIG_USART3_SERIAL_CONSOLE=y +CONFIG_USBDEV_BUSPOWERED=y +CONFIG_USBDEV_DUALSPEED=y +CONFIG_USBDEV_ISOCHRONOUS=y +CONFIG_USBDEV_MAXPOWER=500 +CONFIG_USERLED=y +CONFIG_USERLED_LOWER=y diff --git a/boards/arm/stm32g4/nucleo-g474re/include/board.h b/boards/arm/stm32g4/nucleo-g474re/include/board.h new file mode 100644 index 0000000000000..8fbf7924c8ee6 --- /dev/null +++ b/boards/arm/stm32g4/nucleo-g474re/include/board.h @@ -0,0 +1,191 @@ +/**************************************************************************** + * boards/arm/stm32g4/nucleo-g474re/include/board.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_STM32_NUCLEO-G474RE_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32_NUCLEO-G474RE_INCLUDE_BOARD_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Clocking *****************************************************************/ + +#undef STM32_BOARD_XTAL /* Not installed by default */ + +#define STM32_HSI_FREQUENCY 16000000ul /* 16MHz */ +#define STM32_LSI_FREQUENCY 32000 /* 32kHz */ +#undef STM32_HSE_FREQUENCY /* Not installed by default */ +#undef STM32_LSE_FREQUENCY /* Not available on this board */ + +/* Main PLL Configuration. + * + * PLL source is HSI = 16MHz + * PLLN = 85, PLLM = 4, PLLP = 10, PLLQ = 2, PLLR = 2 + * + * f(VCO Clock) = f(PLL Clock Input) x (PLLN / PLLM) + * f(PLL_P) = f(VCO Clock) / PLLP + * f(PLL_Q) = f(VCO Clock) / PLLQ + * f(PLL_R) = f(VCO Clock) / PLLR + * + * Where: + * 8 <= PLLN <= 127 + * 1 <= PLLM <= 16 + * PLLP = 2 through 31 + * PLLQ = 2, 4, 6, or 8 + * PLLR = 2, 4, 6, or 8 + * + * Do not exceed 170MHz on f(PLL_P), f(PLL_Q), or f(PLL_R). + * 64MHz <= f(VCO Clock) <= 344MHz. + * + * Given the above: + * + * f(VCO Clock) = HSI x PLLN / PLLM + * = 16MHz x 85 / 4 + * = 340MHz + * + * PLLPCLK = f(VCO Clock) / PLLP + * = 340MHz / 10 + * = 34MHz + * (May be used for ADC) + * + * PLLQCLK = f(VCO Clock) / PLLQ + * = 340MHz / 2 + * = 170MHz + * (May be used for QUADSPI, FDCAN, SAI1, I2S3. If set to + * 48MHz, may be used for USB, RNG.) + * + * PLLRCLK = f(VCO Clock) / PLLR + * = 340MHz / 2 + * = 170MHz + * (May be used for SYSCLK and most peripherals.) + */ + +#define STM32_PLLCFGR_PLLSRC RCC_PLLCFGR_PLLSRC_HSI +#define STM32_PLLCFGR_PLLCFG (RCC_PLLCFGR_PLLPEN | \ + RCC_PLLCFGR_PLLQEN | \ + RCC_PLLCFGR_PLLREN) + +#define STM32_PLLCFGR_PLLN RCC_PLLCFGR_PLLN(85) +#define STM32_PLLCFGR_PLLM RCC_PLLCFGR_PLLM(4) +#define STM32_PLLCFGR_PLLP RCC_PLLCFGR_PLLPDIV(10) +#define STM32_PLLCFGR_PLLQ RCC_PLLCFGR_PLLQ_2 +#define STM32_PLLCFGR_PLLR RCC_PLLCFGR_PLLR_2 + +#define STM32_VCO_FREQUENCY ((STM32_HSI_FREQUENCY / 4) * 85) +#define STM32_PLLP_FREQUENCY (STM32_VCO_FREQUENCY / 10) +#define STM32_PLLQ_FREQUENCY (STM32_VCO_FREQUENCY / 2) +#define STM32_PLLR_FREQUENCY (STM32_VCO_FREQUENCY / 2) + +/* Use the PLL and set the SYSCLK source to be PLLR (170MHz) */ + +#define STM32_SYSCLK_SW RCC_CFGR_SW_PLL +#define STM32_SYSCLK_SWS RCC_CFGR_SWS_PLL +#define STM32_SYSCLK_FREQUENCY STM32_PLLR_FREQUENCY + +/* AHB clock (HCLK) is SYSCLK (170MHz) */ + +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY + +/* APB1 clock (PCLK1) is HCLK (170MHz) */ + +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK +#define STM32_PCLK1_FREQUENCY STM32_HCLK_FREQUENCY + +/* APB2 clock (PCLK2) is HCLK (170MHz) */ + +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK +#define STM32_PCLK2_FREQUENCY STM32_HCLK_FREQUENCY + +/* LED definitions **********************************************************/ + +/* The NucleoG474RE board has one user LED. + * + * If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs in + * any way. The following definitions are used to access individual LEDs. + */ + +/* LED index values for use with board_userled() */ + +#define BOARD_LED1 0 /* LD2 (Green) */ +#define BOARD_NLEDS 1 + +/* LED bits for use with board_userled_all() */ + +#define BOARD_LED1_BIT (1 << BOARD_LED1) + +/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the 4 user LEDs + * on the board. The following definitions describe how NuttX controls the + * LEDs: + * + * |--------------------|-------------------------|------------| + * | SYMBOL | Meaning | LED states | + * |--------------------|-------------------------|------------| + * | LED_STARTED | NuttX has been started | 0 0 0 0 | + * | LED_HEAPALLOCATE | Heap has been allocated | 0 0 0 0 | + * | LED_IRQSENABLED | Interrupts enabled | 0 0 0 0 | + * | LED_STACKCREATED | Idle stack created | 1 0 0 0 | + * | LED_INIRQ | In an interrupt | No change | + * | LED_SIGNAL | In a signal handler | No change | + * | LED_ASSERTION | An assertion failed | No change | + * | LED_PANIC | The system has crashed | 0 B 0 0 | + * | LED_IDLE | STM32 is in sleep mode | Not used | + * |--------------------|-------------------------|------------| + * + * LED states legend: + * 0 = off + * 1 = on + * B = blink + */ + +#define LED_STARTED 0 +#define LED_HEAPALLOCATE 0 +#define LED_IRQSENABLED 0 +#define LED_STACKCREATED 1 +#define LED_INIRQ 2 +#define LED_SIGNAL 2 +#define LED_ASSERTION 2 +#define LED_PANIC 3 + +/* Button definitions *******************************************************/ + +/* Alternate function pin selections ****************************************/ + +/* LPUART1 (ST LINK V3E Virtual Console) */ +#define GPIO_LPUART1_TX GPIO_LPUART1_TX_1 /* PA2 */ +#define GPIO_LPUART1_RX GPIO_LPUART1_RX_1 /* PA3 */ +#define GPIO_LPUART1_CTS GPIO_LPUART1_CTS_1 /* PA6 */ +#define GPIO_LPUART1_RTS GPIO_LPUART1_RTS_1 /* PB1 */ + +/* USART3 Pins CN7 Pins 1 and 2 */ +#define GPIO_USART3_TX GPIO_USART3_TX_3 /* PC10 */ +#define GPIO_USART3_RX GPIO_USART3_RX_3 /* PC11 */ + +/* Pin Multiplexing Disambiguation ******************************************/ + +#endif /* __BOARDS_ARM_STM32_NUCLEO_G474RE_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32g4/nucleo-g474re/scripts/Make.defs b/boards/arm/stm32g4/nucleo-g474re/scripts/Make.defs new file mode 100644 index 0000000000000..1ab6247f01c1c --- /dev/null +++ b/boards/arm/stm32g4/nucleo-g474re/scripts/Make.defs @@ -0,0 +1,51 @@ +############################################################################ +# boards/arm/stm32g4/nucleo-g474re/scripts/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/.config +include $(TOPDIR)/tools/Config.mk +include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs + +ifeq ($(CONFIG_STM32_DFU),y) + LDSCRIPT = ld.script.dfu +else + LDSCRIPT = ld.script +endif + +ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) + +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 + +# Embed absolute path to source file in debug information so that Eclipse +# source level debugging won't get confused. See: +# https://stackoverflow.com/questions/1275476/gcc-gdb-how-to-embed-absolute-path-to-source-file-in-debug-information +CFLAGS += -fdebug-prefix-map=..=$(readlink -f ..) diff --git a/boards/arm/stm32g4/nucleo-g474re/scripts/ld.script b/boards/arm/stm32g4/nucleo-g474re/scripts/ld.script new file mode 100644 index 0000000000000..4aca8670722cb --- /dev/null +++ b/boards/arm/stm32g4/nucleo-g474re/scripts/ld.script @@ -0,0 +1,139 @@ +/**************************************************************************** + * boards/arm/stm32g4/nucleo-g474re/scripts/ld.script + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* The STM32G474RE has 512 KiB of FLASH beginning at address 0x0800:0000. + * + * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 + * where the code expects to begin execution by jumping to the entry point in + * the 0x0800:0000 address range. + * + * The STM32G474RE has a total of 128 KiB of SRAM in three separate areas: + * + * 1) 80 KiB SRAM1 mapped at 0x2000:0000 thru 0x2001:3fff. + * 2) 16 KiB SRAM2 mapped at 0x2001:4000 thru 0x2001:7fff. + * + * CCM SRAM (Routine Booster): + * + * 3) 32 KiB CCM SRAM mapped at 0x1000:0000 thru 0x1000:7fff + * but also aliased at at 0x2001:8000 thru 0x2001:ffff to be contiguous + * with the SRAM1 and SRAM2. + * + * Because SRAM1 and SRAM2 are contiguous, they are treated as one region + * by this logic. + * + * CCM SRAM is also contiguous to SRAM1 and SRAM2, however it is excluded + * from this linker script, to keep it reserved for special uses in code. + * REVISIT: Is this the correct way to handle CCM SRAM? + */ + +MEMORY +{ + flash (rx) : ORIGIN = 0x08000000, LENGTH = 512K + sram (rwx) : ORIGIN = 0x20000000, LENGTH = 96K +} + +OUTPUT_ARCH(arm) +EXTERN(_vectors) +ENTRY(_stext) + +SECTIONS +{ + .text : { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > flash + + .init_section : ALIGN(4) { + _sinit = ABSOLUTE(.); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) + _einit = ABSOLUTE(.); + } > flash + + .ARM.extab : ALIGN(4) { + *(.ARM.extab*) + } > flash + + .ARM.exidx : ALIGN(4) { + __exidx_start = ABSOLUTE(.); + *(.ARM.exidx*) + __exidx_end = ABSOLUTE(.); + } > flash + + .tdata : { + _stdata = ABSOLUTE(.); + *(.tdata .tdata.* .gnu.linkonce.td.*); + _etdata = ABSOLUTE(.); + } > flash + + .tbss : { + _stbss = ABSOLUTE(.); + *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); + _etbss = ABSOLUTE(.); + } > flash + + _eronly = ABSOLUTE(.); + + .data : ALIGN(4) { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > sram AT > flash + + .bss : ALIGN(4) { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + _ebss = ABSOLUTE(.); + } > sram + + /* Stabs debugging sections. */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/stm32g4/nucleo-g474re/scripts/ld.script.dfu b/boards/arm/stm32g4/nucleo-g474re/scripts/ld.script.dfu new file mode 100644 index 0000000000000..152d9a3852f63 --- /dev/null +++ b/boards/arm/stm32g4/nucleo-g474re/scripts/ld.script.dfu @@ -0,0 +1,142 @@ +/**************************************************************************** + * boards/arm/stm32g4/nucleo-g474re/scripts/ld.script + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* The STM32G474RE has 512 KiB of FLASH beginning at address 0x0800:0000. + * + * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 + * where the code expects to begin execution by jumping to the entry point in + * the 0x0800:0000 address range. The FLASH bootloader is located there and + * allocated up to 24KiB (6 pages of 4k if single bank mode or 12 pages of 2k + * if dual bank mode), so our executable will begin at 0x0800:6000, leaving + * 488KiB. + * + * The STM32G474RE has a total of 128 KiB of SRAM in three separate areas: + * + * 1) 80 KiB SRAM1 mapped at 0x2000:0000 thru 0x2001:3fff. + * 2) 16 KiB SRAM2 mapped at 0x2001:4000 thru 0x2001:7fff. + * + * CCM SRAM (Routine Booster): + * + * 3) 32 KiB CCM SRAM mapped at 0x1000:0000 thru 0x1000:7fff + * but also aliased at at 0x2001:8000 thru 0x2001:ffff to be contiguous + * with the SRAM1 and SRAM2. + * + * Because SRAM1 and SRAM2 are contiguous, they are treated as one region + * by this logic. + * + * CCM SRAM is also contiguous to SRAM1 and SRAM2, however it is excluded + * from this linker script, to keep it reserved for special uses in code. + * REVISIT: Is this the correct way to handle CCM SRAM? + */ + +MEMORY +{ + flash (rx) : ORIGIN = 0x08006000, LENGTH = 488K + sram (rwx) : ORIGIN = 0x20000000, LENGTH = 96K +} + +OUTPUT_ARCH(arm) +EXTERN(_vectors) +ENTRY(_stext) + +SECTIONS +{ + .text : { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > flash + + .init_section : ALIGN(4) { + _sinit = ABSOLUTE(.); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) + _einit = ABSOLUTE(.); + } > flash + + .ARM.extab : ALIGN(4) { + *(.ARM.extab*) + } > flash + + .ARM.exidx : ALIGN(4) { + __exidx_start = ABSOLUTE(.); + *(.ARM.exidx*) + __exidx_end = ABSOLUTE(.); + } > flash + + .tdata : { + _stdata = ABSOLUTE(.); + *(.tdata .tdata.* .gnu.linkonce.td.*); + _etdata = ABSOLUTE(.); + } > flash + + .tbss : { + _stbss = ABSOLUTE(.); + *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); + _etbss = ABSOLUTE(.); + } > flash + + _eronly = ABSOLUTE(.); + + .data : ALIGN(4) { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > sram AT > flash + + .bss : ALIGN(4) { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + _ebss = ABSOLUTE(.); + } > sram + + /* Stabs debugging sections. */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/stm32/nucleo-g474re/src/.gitignore b/boards/arm/stm32g4/nucleo-g474re/src/.gitignore similarity index 100% rename from boards/arm/stm32/nucleo-g474re/src/.gitignore rename to boards/arm/stm32g4/nucleo-g474re/src/.gitignore diff --git a/boards/arm/stm32g4/nucleo-g474re/src/CMakeLists.txt b/boards/arm/stm32g4/nucleo-g474re/src/CMakeLists.txt new file mode 100644 index 0000000000000..494c3bcb57767 --- /dev/null +++ b/boards/arm/stm32g4/nucleo-g474re/src/CMakeLists.txt @@ -0,0 +1,37 @@ +# ############################################################################## +# boards/arm/stm32g4/nucleo-g474re/src/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(SRCS stm32_boot.c stm32_bringup.c) + +if(CONFIG_ARCH_LEDS) + list(APPEND SRCS stm32_autoleds.c) +else() + list(APPEND SRCS stm32_userleds.c) +endif() + +if(CONFIG_USBDEV) + list(APPEND SRCS stm32_usbdev.c) +endif() + +target_sources(board PRIVATE ${SRCS}) + +set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/ld.script") diff --git a/boards/arm/stm32g4/nucleo-g474re/src/Make.defs b/boards/arm/stm32g4/nucleo-g474re/src/Make.defs new file mode 100644 index 0000000000000..7d2f9725ab003 --- /dev/null +++ b/boards/arm/stm32g4/nucleo-g474re/src/Make.defs @@ -0,0 +1,40 @@ +############################################################################ +# boards/arm/stm32g4/nucleo-g474re/src/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +ASRCS = +CSRCS = stm32_boot.c stm32_bringup.c + +ifeq ($(CONFIG_ARCH_LEDS),y) +CSRCS += stm32_autoleds.c +else +CSRCS += stm32_userleds.c +endif + +ifeq ($(CONFIG_USBDEV),y) + CSRCS += stm32_usbdev.c +endif + +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/nucleo-g474re/src/nucleo-g474re.h b/boards/arm/stm32g4/nucleo-g474re/src/nucleo-g474re.h similarity index 98% rename from boards/arm/stm32/nucleo-g474re/src/nucleo-g474re.h rename to boards/arm/stm32g4/nucleo-g474re/src/nucleo-g474re.h index 3609b90e7e581..e50ff639c455d 100644 --- a/boards/arm/stm32/nucleo-g474re/src/nucleo-g474re.h +++ b/boards/arm/stm32g4/nucleo-g474re/src/nucleo-g474re.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-g474re/src/nucleo-g474re.h + * boards/arm/stm32g4/nucleo-g474re/src/nucleo-g474re.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32g4/nucleo-g474re/src/stm32_autoleds.c b/boards/arm/stm32g4/nucleo-g474re/src/stm32_autoleds.c new file mode 100644 index 0000000000000..28380bf71d735 --- /dev/null +++ b/boards/arm/stm32g4/nucleo-g474re/src/stm32_autoleds.c @@ -0,0 +1,84 @@ +/**************************************************************************** + * boards/arm/stm32g4/nucleo-g474re/src/stm32_autoleds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "stm32.h" +#include "nucleo-g474re.h" + +#if defined(CONFIG_ARCH_LEDS) + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_autoled_initialize + ****************************************************************************/ + +void board_autoled_initialize(void) +{ + /* Configure LED1 GPIO for output */ + + stm32_configgpio(GPIO_LED1); +} + +/**************************************************************************** + * Name: board_autoled_on + ****************************************************************************/ + +void board_autoled_on(int led) +{ + switch (led) + { + case BOARD_LED1: + stm32_gpiowrite(GPIO_LED1, true); + break; + } +} + +/**************************************************************************** + * Name: board_autoled_off + ****************************************************************************/ + +void board_autoled_off(int led) +{ + switch (led) + { + case BOARD_LED1: + stm32_gpiowrite(GPIO_LED1, false); + break; + } +} + +#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32g4/nucleo-g474re/src/stm32_boot.c b/boards/arm/stm32g4/nucleo-g474re/src/stm32_boot.c new file mode 100644 index 0000000000000..9b8eced144d8e --- /dev/null +++ b/boards/arm/stm32g4/nucleo-g474re/src/stm32_boot.c @@ -0,0 +1,93 @@ +/**************************************************************************** + * boards/arm/stm32g4/nucleo-g474re/src/stm32_boot.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include "nucleo-g474re.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_boardinitialize + * + * Description: + * All STM32 architectures must provide the following entry point. This + * entry point is called early in the initialization -- after all memory + * has been configured and mapped but before any devices have been + * initialized. + * + ****************************************************************************/ + +void stm32_boardinitialize(void) +{ +#if defined(CONFIG_ARCH_LEDS) + /* Configure on-board LEDs if LED support has been selected. */ + + board_autoled_initialize(); +#endif +} + +/**************************************************************************** + * Name: board_late_initialize + * + * Description: + * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_late_initialize(). board_late_initialize() + * will be called immediately after up_initialize() is called and just + * before the initial application is started. + * This additional initialization phase may be used, for example, to + * initialize board-specific device drivers. + * + ****************************************************************************/ + +#ifdef CONFIG_BOARD_LATE_INITIALIZE +void board_late_initialize(void) +{ + stm32_bringup(); +} +#endif diff --git a/boards/arm/stm32g4/nucleo-g474re/src/stm32_bringup.c b/boards/arm/stm32g4/nucleo-g474re/src/stm32_bringup.c new file mode 100644 index 0000000000000..89d86a499fe21 --- /dev/null +++ b/boards/arm/stm32g4/nucleo-g474re/src/stm32_bringup.c @@ -0,0 +1,92 @@ +/**************************************************************************** + * boards/arm/stm32g4/nucleo-g474re/src/stm32_bringup.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include +#include + +#include "nucleo-g474re.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#undef HAVE_LEDS + +#if !defined(CONFIG_ARCH_LEDS) && defined(CONFIG_USERLED_LOWER) +# define HAVE_LEDS 1 +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_bringup + * + * Description: + * Perform architecture-specific initialization + * + * CONFIG_BOARD_LATE_INITIALIZE=y : + * Called from board_late_initialize(). + * + ****************************************************************************/ + +int stm32_bringup(void) +{ + int ret; + +#if defined(HAVE_LEDS) + /* Register the LED driver */ + + ret = userled_lower_initialize(LED_DRIVER_PATH); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: userled_lower_initialize() failed: %d\n", ret); + return ret; + } +#endif + +#if defined(CONFIG_CDCACM) && !defined(CONFIG_CDCACM_CONSOLE) + /* Initialize CDCACM */ + + syslog(LOG_INFO, "Initialize CDCACM device\n"); + + ret = cdcacm_initialize(0, NULL); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: cdcacm_initialize failed: %d\n", ret); + } +#endif /* CONFIG_CDCACM & !CONFIG_CDCACM_CONSOLE */ + + UNUSED(ret); + return OK; +} diff --git a/boards/arm/stm32g4/nucleo-g474re/src/stm32_usbdev.c b/boards/arm/stm32g4/nucleo-g474re/src/stm32_usbdev.c new file mode 100644 index 0000000000000..389fb718f11d3 --- /dev/null +++ b/boards/arm/stm32g4/nucleo-g474re/src/stm32_usbdev.c @@ -0,0 +1,59 @@ +/**************************************************************************** + * boards/arm/stm32g4/nucleo-g474re/src/stm32_usbdev.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include + +#include "arm_internal.h" +#include "stm32.h" +#include "nucleo-g474re.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_usbsuspend + * + * Description: + * Board logic must provide the stm32_usbsuspend logic if the USBDEV driver + * is used. This function is called whenever the USB enters or leaves + * suspend mode. This is an opportunity for the board logic to shutdown + * clocks, power, etc. while the USB is suspended. + * + ****************************************************************************/ + +void stm32_usbsuspend(struct usbdev_s *dev, bool resume) +{ + uinfo("resume: %d\n", resume); +} diff --git a/boards/arm/stm32g4/nucleo-g474re/src/stm32_userleds.c b/boards/arm/stm32g4/nucleo-g474re/src/stm32_userleds.c new file mode 100644 index 0000000000000..16dcca37aee5f --- /dev/null +++ b/boards/arm/stm32g4/nucleo-g474re/src/stm32_userleds.c @@ -0,0 +1,106 @@ +/**************************************************************************** + * boards/arm/stm32g4/nucleo-g474re/src/stm32_userleds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include + +#include "stm32.h" +#include "nucleo-g474re.h" + +#if !defined(CONFIG_ARCH_LEDS) + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_userled_initialize + * + * Description: + * Initialize the user LEDs before use. Note: For this function to be + * available to user application logic, CONFIG_ARCH_LEDS must not be + * defined. + ****************************************************************************/ + +uint32_t board_userled_initialize(void) +{ + /* Configure LED GPIOs for output */ + + stm32_configgpio(GPIO_LED1); + return BOARD_NLEDS; +} + +/**************************************************************************** + * Name: board_userled + * + * Description: + * Allow user application logic to control LEDs one at a time. Note: For + * this function to be available to user application logic, + * CONFIG_ARCH_LEDS must not be defined. + * + * Parameters: + * led: Index to the LED, which may be one of the defines BOARD_LED1, + * BOARD_LED2, BOARD_LED3, or BOARD_LED4. + * ledon: true to turn the LED on, false to turn it off. + ****************************************************************************/ + +void board_userled(int led, bool ledon) +{ + switch (led) + { + case BOARD_LED1: + stm32_gpiowrite(GPIO_LED1, ledon); + break; + } +} + +/**************************************************************************** + * Name: board_userled_all + * + * Description: + * Allow user application logic to control all LEDs in one function call. + * Note: For this function to be available to user application logic, + * CONFIG_ARCH_LEDS must not be defined. + * + * Parameters: + * ledset: Bitmask indicating the new state for all LEDs, where a set bit + * indicates LED on and a clear bit indicates LED off. To + * construct the bitmask, using a bitwise OR of the defines + * BOARD_LED1_BIT, BOARD_LED2_BIT, BOARD_LED3_BIT, and/or + * BOARD_LED4_BIT. + ****************************************************************************/ + +void board_userled_all(uint32_t ledset) +{ + stm32_gpiowrite(GPIO_LED1, (ledset & BOARD_LED1_BIT) != 0); +} + +#endif /* !CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32h5/common/CMakeLists.txt b/boards/arm/stm32h5/common/CMakeLists.txt new file mode 100644 index 0000000000000..4e3c35d7a99d1 --- /dev/null +++ b/boards/arm/stm32h5/common/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32h5/common/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(${NUTTX_DIR}/boards/arm/common/stm32 stm32_common) diff --git a/boards/arm/stm32h5/common/Makefile b/boards/arm/stm32h5/common/Makefile new file mode 100644 index 0000000000000..943009ffb04f5 --- /dev/null +++ b/boards/arm/stm32h5/common/Makefile @@ -0,0 +1,36 @@ +############################################################################# +# boards/arm/stm32h5/common/Makefile +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################# + +include $(TOPDIR)/Make.defs + +STM32_BOARD_COMMON_DIR := $(TOPDIR)$(DELIM)boards$(DELIM)arm$(DELIM)common$(DELIM)stm32 + +include board/Make.defs +include $(STM32_BOARD_COMMON_DIR)$(DELIM)src$(DELIM)Make.defs + +DEPPATH += --dep-path board + +include $(TOPDIR)/boards/Board.mk + +ARCHSRCDIR = $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src +BOARDDIR = $(ARCHSRCDIR)$(DELIM)board +CFLAGS += ${INCDIR_PREFIX}$(BOARDDIR)$(DELIM)include diff --git a/boards/arm/stm32h5/nucleo-h563zi/Kconfig b/boards/arm/stm32h5/nucleo-h563zi/Kconfig index e0838b56a45b9..875646f6c5c45 100644 --- a/boards/arm/stm32h5/nucleo-h563zi/Kconfig +++ b/boards/arm/stm32h5/nucleo-h563zi/Kconfig @@ -5,7 +5,7 @@ if ARCH_BOARD_NUCLEO_H563ZI -config STM32H5_USE_HSE +config STM32_USE_HSE bool "Use on-board HSE" default n ---help--- diff --git a/boards/arm/stm32h5/nucleo-h563zi/configs/adc/defconfig b/boards/arm/stm32h5/nucleo-h563zi/configs/adc/defconfig index 47aa7fb2cfe23..0b0e405f95008 100644 --- a/boards/arm/stm32h5/nucleo-h563zi/configs/adc/defconfig +++ b/boards/arm/stm32h5/nucleo-h563zi/configs/adc/defconfig @@ -14,6 +14,7 @@ CONFIG_ARCH_BOARD="nucleo-h563zi" CONFIG_ARCH_BOARD_NUCLEO_H563ZI=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32h5" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H563ZI=y CONFIG_ARCH_CHIP_STM32H5=y CONFIG_ARCH_INTERRUPTSTACK=2048 @@ -48,8 +49,8 @@ CONFIG_READLINE_TABCOMPLETION=y CONFIG_RR_INTERVAL=200 CONFIG_SCHED_WAITPID=y CONFIG_STACK_COLORATION=y -CONFIG_STM32H5_ADC1=y -CONFIG_STM32H5_USART3=y +CONFIG_STM32_ADC1=y +CONFIG_STM32_USART3=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART3_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32h5/nucleo-h563zi/configs/adc_watchdog/defconfig b/boards/arm/stm32h5/nucleo-h563zi/configs/adc_watchdog/defconfig index f5fde0ba1a74c..748044ad5fcd6 100644 --- a/boards/arm/stm32h5/nucleo-h563zi/configs/adc_watchdog/defconfig +++ b/boards/arm/stm32h5/nucleo-h563zi/configs/adc_watchdog/defconfig @@ -14,6 +14,7 @@ CONFIG_ARCH_BOARD="nucleo-h563zi" CONFIG_ARCH_BOARD_NUCLEO_H563ZI=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32h5" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H563ZI=y CONFIG_ARCH_CHIP_STM32H5=y CONFIG_ARCH_INTERRUPTSTACK=2048 @@ -49,13 +50,13 @@ CONFIG_RR_INTERVAL=200 CONFIG_SCHED_HPWORK=y CONFIG_SCHED_WAITPID=y CONFIG_STACK_COLORATION=y -CONFIG_STM32H5_ADC1=y -CONFIG_STM32H5_ADC1_DMA=y -CONFIG_STM32H5_ADC1_DMA_CFG=y -CONFIG_STM32H5_ADC1_WDG1=y -CONFIG_STM32H5_ADC1_WDG1_HIGHTHRESH=2048 -CONFIG_STM32H5_DMA1=y -CONFIG_STM32H5_USART3=y +CONFIG_STM32_ADC1=y +CONFIG_STM32_ADC1_DMA=y +CONFIG_STM32_ADC1_DMA_CFG=1 +CONFIG_STM32_ADC1_WDG1=y +CONFIG_STM32_ADC1_WDG1_HIGHTHRESH=2048 +CONFIG_STM32_DMA1=y +CONFIG_STM32_USART3=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART3_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32h5/nucleo-h563zi/configs/dts/defconfig b/boards/arm/stm32h5/nucleo-h563zi/configs/dts/defconfig index 23e83ae917777..343a78089465d 100644 --- a/boards/arm/stm32h5/nucleo-h563zi/configs/dts/defconfig +++ b/boards/arm/stm32h5/nucleo-h563zi/configs/dts/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH_BOARD="nucleo-h563zi" CONFIG_ARCH_BOARD_NUCLEO_H563ZI=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32h5" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H563ZI=y CONFIG_ARCH_CHIP_STM32H5=y CONFIG_ARCH_INTERRUPTSTACK=2048 @@ -43,9 +44,9 @@ CONFIG_RR_INTERVAL=200 CONFIG_SCHED_WAITPID=y CONFIG_SENSORS=y CONFIG_STACK_COLORATION=y -CONFIG_STM32H5_DTS=y -CONFIG_STM32H5_DTS_SMP_TIME=15 -CONFIG_STM32H5_USART3=y +CONFIG_STM32_DTS=y +CONFIG_STM32_DTS_SMP_TIME=15 +CONFIG_STM32_USART3=y CONFIG_SYSTEM_NSH=y CONFIG_SYSTEM_SENSORTEST=y CONFIG_TASK_NAME_SIZE=0 diff --git a/boards/arm/stm32h5/nucleo-h563zi/configs/fdcan1/defconfig b/boards/arm/stm32h5/nucleo-h563zi/configs/fdcan1/defconfig index d6a00523dbb80..dbd9341b0a6a0 100644 --- a/boards/arm/stm32h5/nucleo-h563zi/configs/fdcan1/defconfig +++ b/boards/arm/stm32h5/nucleo-h563zi/configs/fdcan1/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH_BOARD="nucleo-h563zi" CONFIG_ARCH_BOARD_NUCLEO_H563ZI=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32h5" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H563ZI=y CONFIG_ARCH_CHIP_STM32H5=y CONFIG_ARCH_INTERRUPTSTACK=2048 @@ -45,10 +46,10 @@ CONFIG_READLINE_TABCOMPLETION=y CONFIG_RR_INTERVAL=200 CONFIG_SCHED_WAITPID=y CONFIG_STACK_COLORATION=y -CONFIG_STM32H5_FDCAN1=y -CONFIG_STM32H5_FDCAN1_FD=y -CONFIG_STM32H5_FDCAN1_LOOPBACK=y -CONFIG_STM32H5_USART3=y +CONFIG_STM32_FDCAN1=y +CONFIG_STM32_FDCAN1_FD=y +CONFIG_STM32_FDCAN1_LOOPBACK=y +CONFIG_STM32_USART3=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART3_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32h5/nucleo-h563zi/configs/nsh/defconfig b/boards/arm/stm32h5/nucleo-h563zi/configs/nsh/defconfig index d2a59492c4b05..70c92e4427832 100644 --- a/boards/arm/stm32h5/nucleo-h563zi/configs/nsh/defconfig +++ b/boards/arm/stm32h5/nucleo-h563zi/configs/nsh/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH_BOARD="nucleo-h563zi" CONFIG_ARCH_BOARD_NUCLEO_H563ZI=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32h5" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H563ZI=y CONFIG_ARCH_CHIP_STM32H5=y CONFIG_ARCH_INTERRUPTSTACK=2048 @@ -42,7 +43,7 @@ CONFIG_READLINE_TABCOMPLETION=y CONFIG_RR_INTERVAL=200 CONFIG_SCHED_WAITPID=y CONFIG_STACK_COLORATION=y -CONFIG_STM32H5_USART3=y +CONFIG_STM32_USART3=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART3_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32h5/nucleo-h563zi/configs/nshusbnet/defconfig b/boards/arm/stm32h5/nucleo-h563zi/configs/nshusbnet/defconfig index 1c47ce601a8d7..e4316e5ec38e8 100644 --- a/boards/arm/stm32h5/nucleo-h563zi/configs/nshusbnet/defconfig +++ b/boards/arm/stm32h5/nucleo-h563zi/configs/nshusbnet/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH_BOARD="nucleo-h563zi" CONFIG_ARCH_BOARD_NUCLEO_H563ZI=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32h5" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H563ZI=y CONFIG_ARCH_CHIP_STM32H5=y CONFIG_ARCH_INTERRUPTSTACK=2048 @@ -58,9 +59,9 @@ CONFIG_SCHED_LPWORK=y CONFIG_SCHED_LPWORKSTACKSIZE=4096 CONFIG_SCHED_WAITPID=y CONFIG_STACK_COLORATION=y -CONFIG_STM32H5_USART3=y -CONFIG_STM32H5_USBFS_HOST=y -CONFIG_STM32H5_USE_HSE=y +CONFIG_STM32_USART3=y +CONFIG_STM32_USBFS_HOST=y +CONFIG_STM32_USE_HSE=y CONFIG_SYSTEM_NSH=y CONFIG_SYSTEM_PING=y CONFIG_TASK_NAME_SIZE=0 diff --git a/boards/arm/stm32h5/nucleo-h563zi/configs/pwm/defconfig b/boards/arm/stm32h5/nucleo-h563zi/configs/pwm/defconfig index 3b73e316f4e90..7b29390dc44db 100644 --- a/boards/arm/stm32h5/nucleo-h563zi/configs/pwm/defconfig +++ b/boards/arm/stm32h5/nucleo-h563zi/configs/pwm/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH_BOARD="nucleo-h563zi" CONFIG_ARCH_BOARD_NUCLEO_H563ZI=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32h5" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H563ZI=y CONFIG_ARCH_CHIP_STM32H5=y CONFIG_ARCH_INTERRUPTSTACK=2048 @@ -45,10 +46,10 @@ CONFIG_READLINE_TABCOMPLETION=y CONFIG_RR_INTERVAL=200 CONFIG_SCHED_WAITPID=y CONFIG_STACK_COLORATION=y -CONFIG_STM32H5_TIM1=y -CONFIG_STM32H5_TIM1_CH1OUT=y -CONFIG_STM32H5_TIM1_PWM=y -CONFIG_STM32H5_USART3=y +CONFIG_STM32_TIM1=y +CONFIG_STM32_TIM1_CH1OUT=y +CONFIG_STM32_TIM1_PWM=y +CONFIG_STM32_USART3=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_TIMER=y diff --git a/boards/arm/stm32h5/nucleo-h563zi/configs/usbmsc/defconfig b/boards/arm/stm32h5/nucleo-h563zi/configs/usbmsc/defconfig index e2a645bc025a6..0e375794ff15f 100644 --- a/boards/arm/stm32h5/nucleo-h563zi/configs/usbmsc/defconfig +++ b/boards/arm/stm32h5/nucleo-h563zi/configs/usbmsc/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH_BOARD="nucleo-h563zi" CONFIG_ARCH_BOARD_NUCLEO_H563ZI=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32h5" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H563ZI=y CONFIG_ARCH_CHIP_STM32H5=y CONFIG_ARCH_INTERRUPTSTACK=2048 @@ -47,9 +48,9 @@ CONFIG_RR_INTERVAL=200 CONFIG_SCHED_LPWORK=y CONFIG_SCHED_WAITPID=y CONFIG_STACK_COLORATION=y -CONFIG_STM32H5_USART3=y -CONFIG_STM32H5_USBFS_HOST=y -CONFIG_STM32H5_USE_HSE=y +CONFIG_STM32_USART3=y +CONFIG_STM32_USBFS_HOST=y +CONFIG_STM32_USE_HSE=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART3_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32h5/nucleo-h563zi/configs/usbnsh/defconfig b/boards/arm/stm32h5/nucleo-h563zi/configs/usbnsh/defconfig index 6772b433f1f1e..7d01dc6fdeeab 100644 --- a/boards/arm/stm32h5/nucleo-h563zi/configs/usbnsh/defconfig +++ b/boards/arm/stm32h5/nucleo-h563zi/configs/usbnsh/defconfig @@ -13,6 +13,7 @@ CONFIG_ARCH_BOARD="nucleo-h563zi" CONFIG_ARCH_BOARD_NUCLEO_H563ZI=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32h5" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H563ZI=y CONFIG_ARCH_CHIP_STM32H5=y CONFIG_ARCH_INTERRUPTSTACK=4096 @@ -48,7 +49,7 @@ CONFIG_READLINE_TABCOMPLETION=y CONFIG_RR_INTERVAL=200 CONFIG_SCHED_WAITPID=y CONFIG_STACK_COLORATION=y -CONFIG_STM32H5_USART3=y -CONFIG_STM32H5_USBFS=y +CONFIG_STM32_USART3=y +CONFIG_STM32_USBFS=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 diff --git a/boards/arm/stm32h5/nucleo-h563zi/include/board.h b/boards/arm/stm32h5/nucleo-h563zi/include/board.h index 11ff18fb03729..1c9caa9d66353 100644 --- a/boards/arm/stm32h5/nucleo-h563zi/include/board.h +++ b/boards/arm/stm32h5/nucleo-h563zi/include/board.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32H5_NUCLEO_H563ZI_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32H5_NUCLEO_H563ZI_INCLUDE_BOARD_H +#ifndef __BOARDS_ARM_STM32_NUCLEO_H563ZI_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32_NUCLEO_H563ZI_INCLUDE_BOARD_H /**************************************************************************** * Included Files @@ -36,7 +36,7 @@ * Pre-processor Definitions ****************************************************************************/ -#if defined(CONFIG_STM32H5_USBFS_HOST) && !defined(CONFIG_STM32H5_USE_HSE) +#if defined(CONFIG_STM32_USBFS_HOST) && !defined(CONFIG_STM32_USE_HSE) #error "This board config requires HSE to use the USB HOST." "HSI48 is not stable enough to use as a host." "To use HSE on the nucleo-H563ZI," @@ -65,7 +65,7 @@ #define STM32_LSI_FREQUENCY 32000 #define STM32_LSE_FREQUENCY 32768 -#ifdef CONFIG_STM32H5_USE_HSE +#ifdef CONFIG_STM32_USE_HSE #define STM32_HSE_FREQUENCY 25000000ul #define STM32_BOARD_USEHSE @@ -108,7 +108,7 @@ #define STM32_VCO2_FRQ ((STM32_HSE_FREQUENCY / 5) * 60) #define STM32_PLL2R_FREQUENCY (STM32_VCO2_FRQ / 4) -#if defined(CONFIG_STM32H5_USBFS_HOST) +#if defined(CONFIG_STM32_USBFS_HOST) /* PLL3 config: Generate 48 MHz for USB from 25 MHz HSE. * VCO input = 25 MHz / 5 = 5 MHz * VCO output = 5 MHz * 96 = 480 MHz @@ -132,9 +132,9 @@ #define STM32_PLL3Q_FREQUENCY (STM32_VCO3_FRQ / 10) /* 48 MHz */ /* Use PLL3Q (48 MHz) for USB - more stable than HSI48 */ -#define STM32H5_CLKUSB_SEL RCC_CCIPR4_USBSEL_PLL3QCK +#define STM32_CLKUSB_SEL RCC_CCIPR4_USBSEL_PLL3QCK -#endif /* CONFIG_STM32H5_USBFS_HOST */ +#endif /* CONFIG_STM32_USBFS_HOST */ #else @@ -181,23 +181,23 @@ #define STM32_VCO2_FRQ ((STM32_HSI_FREQUENCY / 8) * 75) #define STM32_PLL2R_FREQUENCY (STM32_VCO2_FRQ / 4) -#endif /* CONFIG_STM32H5_USE_HSE*/ +#endif /* CONFIG_STM32_USE_HSE*/ /* Enable CLK48; get it from HSI48 */ -#if defined(CONFIG_STM32H5_USBFS) || defined(CONFIG_STM32H5_RNG) -# define STM32H5_USE_CLK48 1 +#if defined(CONFIG_STM32_USBFS) || defined(CONFIG_STM32_RNG) +# define STM32_USE_CLK48 1 #endif -#if defined(CONFIG_STM32H5_USBFS) -# define STM32H5_CLKUSB_SEL RCC_CCIPR4_USBSEL_HSI48KERCK -# define STM32H5_HSI48_SYNCSRC SYNCSRC_USB +#if defined(CONFIG_STM32_USBFS) +# define STM32_CLKUSB_SEL RCC_CCIPR4_USBSEL_HSI48KERCK +# define STM32_HSI48_SYNCSRC SYNCSRC_USB #else -# define STM32H5_HSI48_SYNCSRC SYNCSRC_NONE +# define STM32_HSI48_SYNCSRC SYNCSRC_NONE #endif -#if defined(CONFIG_STM32H5_RNG) -# define STM32H5_CLKRNG_SEL RCC_CCIPR5_RNGSEL_HSI48KERCK +#if defined(CONFIG_STM32_RNG) +# define STM32_CLKRNG_SEL RCC_CCIPR5_RNGSEL_HSI48KERCK #endif /* Enable LSE (for the RTC) */ @@ -426,4 +426,4 @@ void stm32_board_initialize(void); #endif #endif /* __ASSEMBLY__ */ -#endif /* __BOARDS_ARM_STM32H5_NUCLEO_H563ZI_INCLUDE_BOARD_H */ +#endif /* __BOARDS_ARM_STM32_NUCLEO_H563ZI_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32h5/nucleo-h563zi/src/CMakeLists.txt b/boards/arm/stm32h5/nucleo-h563zi/src/CMakeLists.txt index 7dca629677e6b..7a979d50c302b 100644 --- a/boards/arm/stm32h5/nucleo-h563zi/src/CMakeLists.txt +++ b/boards/arm/stm32h5/nucleo-h563zi/src/CMakeLists.txt @@ -36,15 +36,15 @@ if(CONFIG_ADC) list(APPEND SRCS stm32_adc.c) endif() -if(CONFIG_STM32H5_DTS) +if(CONFIG_STM32_DTS) list(APPEND SRCS stm32_dts.c) endif() -if(CONFIG_STM32H5_FDCAN) +if(CONFIG_STM32_FDCAN) list(APPEND SRCS stm32_can.c) endif() -if(CONFIG_STM32H5_USBFS_HOST) +if(CONFIG_STM32_USBFS_HOST) list(APPEND SRCS stm32_usb.c) endif() diff --git a/boards/arm/stm32h5/nucleo-h563zi/src/Make.defs b/boards/arm/stm32h5/nucleo-h563zi/src/Make.defs new file mode 100644 index 0000000000000..58888944b0f4f --- /dev/null +++ b/boards/arm/stm32h5/nucleo-h563zi/src/Make.defs @@ -0,0 +1,59 @@ +############################################################################ +# boards/arm/stm32h5/nucleo-h563zi/src/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +CSRCS = stm32_boot.c stm32_bringup.c stm32_clockconfig.c + +ifeq ($(CONFIG_ARCH_LEDS),y) +CSRCS += stm32_autoleds.c +else +CSRCS += stm32_userleds.c +endif + +ifeq ($(CONFIG_ARCH_BUTTONS),y) +CSRCS += stm32_buttons.c +endif + +ifeq ($(CONFIG_ADC),y) +CSRCS += stm32_adc.c +endif + +ifeq ($(CONFIG_STM32_DTS),y) +CSRCS += stm32_dts.c +endif + +ifeq ($(CONFIG_STM32_FDCAN),y) +CSRCS += stm32_can.c +endif + +ifeq ($(CONFIG_STM32_PWM),y) +CSRCS += stm32_pwm.c +endif + +ifeq ($(CONFIG_STM32_USBFS_HOST),y) +CSRCS += stm32_usb.c +endif + +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32h5/nucleo-h563zi/src/Makefile b/boards/arm/stm32h5/nucleo-h563zi/src/Makefile deleted file mode 100644 index 015b4463999df..0000000000000 --- a/boards/arm/stm32h5/nucleo-h563zi/src/Makefile +++ /dev/null @@ -1,58 +0,0 @@ -############################################################################## -# boards/arm/stm32h5/nucleo-h563zi/src/Makefile -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################## - --include $(TOPDIR)/Make.defs - -ASRCS = -CSRCS = stm32_boot.c stm32_bringup.c stm32_clockconfig.c - -ifeq ($(CONFIG_ARCH_LEDS),y) -CSRCS += stm32_autoleds.c -else -CSRCS += stm32_userleds.c -endif - -ifeq ($(CONFIG_ARCH_BUTTONS),y) -CSRCS += stm32_buttons.c -endif - -ifeq ($(CONFIG_ADC),y) -CSRCS += stm32_adc.c -endif - -ifeq ($(CONFIG_STM32H5_DTS),y) -CSRCS += stm32_dts.c -endif - -ifeq ($(CONFIG_STM32H5_FDCAN),y) -CSRCS += stm32_can.c -endif - -ifeq ($(CONFIG_STM32H5_PWM),y) -CSRCS += stm32_pwm.c -endif - -ifeq ($(CONFIG_STM32H5_USBFS_HOST),y) -CSRCS += stm32_usb.c -endif - -include $(TOPDIR)/boards/Board.mk diff --git a/boards/arm/stm32h5/nucleo-h563zi/src/nucleo-h563zi.h b/boards/arm/stm32h5/nucleo-h563zi/src/nucleo-h563zi.h index 0d30bde00d792..693654353ae3e 100644 --- a/boards/arm/stm32h5/nucleo-h563zi/src/nucleo-h563zi.h +++ b/boards/arm/stm32h5/nucleo-h563zi/src/nucleo-h563zi.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32H5_NUCLEO_H563ZI_SRC_NUCLEO_H563ZI_H -#define __BOARDS_ARM_STM32H5_NUCLEO_H563ZI_SRC_NUCLEO_H563ZI_H +#ifndef __BOARDS_ARM_STM32_NUCLEO_H563ZI_SRC_NUCLEO_H563ZI_H +#define __BOARDS_ARM_STM32_NUCLEO_H563ZI_SRC_NUCLEO_H563ZI_H /**************************************************************************** * Included Files @@ -126,7 +126,7 @@ int stm32_bringup(void); int stm32_adc_setup(void); #endif -#ifdef CONFIG_STM32H5_DTS +#ifdef CONFIG_STM32_DTS int stm32_dts_setup(int devno); #endif @@ -138,7 +138,7 @@ int stm32_dts_setup(int devno); * ****************************************************************************/ -#ifdef CONFIG_STM32H5_FDCAN_CHARDRIVER +#ifdef CONFIG_STM32_FDCAN_CHARDRIVER int stm32_can_setup(uint8_t port); #endif @@ -159,4 +159,4 @@ int stm32_usbhost_initialize(void); #endif #endif /* __ASSEMBLY__ */ -#endif /* __BOARDS_ARM_STM32H5_NUCLEO_H563ZI_SRC_NUCLEO_H563ZI_H */ +#endif /* __BOARDS_ARM_STM32_NUCLEO_H563ZI_SRC_NUCLEO_H563ZI_H */ diff --git a/boards/arm/stm32h5/nucleo-h563zi/src/stm32_adc.c b/boards/arm/stm32h5/nucleo-h563zi/src/stm32_adc.c index ff662f03c1fd3..08f0568ed2484 100644 --- a/boards/arm/stm32h5/nucleo-h563zi/src/stm32_adc.c +++ b/boards/arm/stm32h5/nucleo-h563zi/src/stm32_adc.c @@ -37,7 +37,7 @@ #include "stm32.h" #if defined(CONFIG_ADC) -#if defined(CONFIG_STM32H5_ADC1) || defined(CONFIG_STM32H5_ADC2) +#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) /**************************************************************************** * Pre-processor Definitions @@ -67,7 +67,7 @@ /* Identifying number of each ADC channel (even if NCHANNELS is less ) */ -#ifdef CONFIG_STM32H5_ADC1 +#ifdef CONFIG_STM32_ADC1 static const uint8_t g_chanlist1[ADC1_NCHANNELS] = { @@ -101,10 +101,10 @@ static uint32_t g_pinlist1[ADC1_NPINS] = int stm32_adc_setup(void) { static bool initialized = false; -#ifdef CONFIG_STM32H5_ADC1 +#ifdef CONFIG_STM32_ADC1 struct adc_dev_s *adc1; #endif -#ifdef CONFIG_STM32H5_ADC2 +#ifdef CONFIG_STM32_ADC2 struct adc_dev_s *adc2; #endif int ret; @@ -116,13 +116,13 @@ int stm32_adc_setup(void) { /* Configure the pins as analog inputs for the selected channels */ -#ifdef CONFIG_STM32H5_ADC1 +#ifdef CONFIG_STM32_ADC1 for (i = 0; i < ADC1_NCHANNELS; i++) { stm32_configgpio(g_pinlist1[i]); } - adc1 = stm32h5_adc_initialize(1, g_chanlist1, ADC1_NCHANNELS); + adc1 = stm32_adc_initialize(1, g_chanlist1, ADC1_NCHANNELS); if (adc1 == NULL) { aerr("ERROR: Failed to get ADC interface 1\n"); @@ -139,13 +139,13 @@ int stm32_adc_setup(void) } #endif -#ifdef CONFIG_STM32H5_ADC2 +#ifdef CONFIG_STM32_ADC2 for (i = 0; i < ADC2_NCHANNELS; i++) { stm32_configgpio(g_pinlist2[i]); } - adc2 = stm32h5_adc_initialize(2, g_chanlist2, ADC2_NCHANNELS); + adc2 = stm32_adc_initialize(2, g_chanlist2, ADC2_NCHANNELS); if (adc2 == NULL) { aerr("ERROR: Failed to get ADC interface 1\n"); @@ -168,5 +168,5 @@ int stm32_adc_setup(void) return OK; } -#endif /* CONFIG_STM32H5_ADC1 || CONFIG_STM32H5_ADC2 */ +#endif /* CONFIG_STM32_ADC1 || CONFIG_STM32_ADC2 */ #endif /* CONFIG_ADC */ diff --git a/boards/arm/stm32h5/nucleo-h563zi/src/stm32_bringup.c b/boards/arm/stm32h5/nucleo-h563zi/src/stm32_bringup.c index 1653b49962636..4139cb487f91e 100644 --- a/boards/arm/stm32h5/nucleo-h563zi/src/stm32_bringup.c +++ b/boards/arm/stm32h5/nucleo-h563zi/src/stm32_bringup.c @@ -107,7 +107,7 @@ int stm32_bringup(void) } #endif /* CONFIG_ADC*/ -#ifdef CONFIG_STM32H5_DTS +#ifdef CONFIG_STM32_DTS /* devno == 0 creates /dev/sensor_temp0 */ ret = stm32_dts_setup(0); @@ -117,9 +117,9 @@ int stm32_bringup(void) } #endif -#ifdef CONFIG_STM32H5_FDCAN_CHARDRIVER +#ifdef CONFIG_STM32_FDCAN_CHARDRIVER /* Initialize CAN and register the CAN driver. */ -# ifdef CONFIG_STM32H5_FDCAN1 +# ifdef CONFIG_STM32_FDCAN1 ret = stm32_can_setup(1); if (ret < 0) { @@ -127,7 +127,7 @@ int stm32_bringup(void) } # endif -# ifdef CONFIG_STM32H5_FDCAN2 +# ifdef CONFIG_STM32_FDCAN2 ret = stm32_can_setup(2); if (ret < 0) { diff --git a/boards/arm/stm32h5/nucleo-h563zi/src/stm32_can.c b/boards/arm/stm32h5/nucleo-h563zi/src/stm32_can.c index caa6709a4c30a..d33b11c390bc3 100644 --- a/boards/arm/stm32h5/nucleo-h563zi/src/stm32_can.c +++ b/boards/arm/stm32h5/nucleo-h563zi/src/stm32_can.c @@ -46,7 +46,7 @@ /* Configuration ************************************************************/ -#if !defined(CONFIG_STM32H5_FDCAN1) && !defined(CONFIG_STM32H5_FDCAN2) +#if !defined(CONFIG_STM32_FDCAN1) && !defined(CONFIG_STM32_FDCAN2) # error "No CAN device is enabled. Please enable at least one CAN device" #endif diff --git a/boards/arm/stm32h5/nucleo-h563zi/src/stm32_clockconfig.c b/boards/arm/stm32h5/nucleo-h563zi/src/stm32_clockconfig.c index e1b23b88046c8..03e7b8d1e7065 100644 --- a/boards/arm/stm32h5/nucleo-h563zi/src/stm32_clockconfig.c +++ b/boards/arm/stm32h5/nucleo-h563zi/src/stm32_clockconfig.c @@ -37,13 +37,13 @@ * Currently the NUCLEO-H563ZI board support is restricted to running NuttX * in the Non-Secure domain together with TrustedFirmware-M (TFM). In this * setup the clock configuration is done by TFM, not by NuttX. Thus, the - * board's configuration sets CONFIG_ARCH_BOARD_STM32H5_CUSTOM_CLOCKCONFIG + * board's configuration sets CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG * to avoid the standard clock config logic to run and instead do just * nothing in this function. * ****************************************************************************/ -#if defined(CONFIG_ARCH_BOARD_STM32H5_CUSTOM_CLOCKCONFIG) +#if defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) void stm32_board_clockconfig(void) { } diff --git a/boards/arm/stm32h5/nucleo-h563zi/src/stm32_dts.c b/boards/arm/stm32h5/nucleo-h563zi/src/stm32_dts.c index 4b1fbd9a713a4..422b7a3ec5a80 100644 --- a/boards/arm/stm32h5/nucleo-h563zi/src/stm32_dts.c +++ b/boards/arm/stm32h5/nucleo-h563zi/src/stm32_dts.c @@ -34,7 +34,7 @@ #include "stm32.h" -#if defined(CONFIG_STM32H5_DTS) +#if defined(CONFIG_STM32_DTS) /**************************************************************************** * Pre-processor Definitions @@ -75,7 +75,7 @@ int stm32_dts_setup(int devno) { /* Register the DTS driver at "/dev/sensor_temp0" */ - ret = stm32h5_dts_register(0); + ret = stm32_dts_register(0); if (ret < 0) { aerr("ERROR: dts_register /dev/dts0 failed: %d\n", ret); diff --git a/boards/arm/stm32h5/nucleo-h563zi/src/stm32_pwm.c b/boards/arm/stm32h5/nucleo-h563zi/src/stm32_pwm.c index 84c307b71813a..ede1d26a5ba2e 100644 --- a/boards/arm/stm32h5/nucleo-h563zi/src/stm32_pwm.c +++ b/boards/arm/stm32h5/nucleo-h563zi/src/stm32_pwm.c @@ -49,11 +49,11 @@ # undef HAVE_PWM #endif -#ifndef CONFIG_STM32H5_TIM1 +#ifndef CONFIG_STM32_TIM1 # undef HAVE_PWM #endif -#ifndef CONFIG_STM32H5_TIM1_PWM +#ifndef CONFIG_STM32_TIM1_PWM # undef HAVE_PWM #endif diff --git a/boards/arm/stm32h5/nucleo-h563zi/src/stm32_usb.c b/boards/arm/stm32h5/nucleo-h563zi/src/stm32_usb.c index cb293dd7f6eba..f0d920a6ce620 100644 --- a/boards/arm/stm32h5/nucleo-h563zi/src/stm32_usb.c +++ b/boards/arm/stm32h5/nucleo-h563zi/src/stm32_usb.c @@ -42,7 +42,7 @@ #include "stm32.h" #include "stm32_usbdrdhost.h" -#ifdef CONFIG_STM32H5_USBFS_HOST +#ifdef CONFIG_STM32_USBFS_HOST /**************************************************************************** * Pre-processor Definitions @@ -185,7 +185,7 @@ int stm32_usbhost_initialize(void) /* Then get an instance of the USB host interface */ uinfo("Initialize USB host\n"); - g_usbconn = stm32h5_usbhost_initialize(); + g_usbconn = stm32_usbdrdhost_initialize(); if (g_usbconn) { /* Start a thread to handle device connection. */ @@ -203,7 +203,7 @@ int stm32_usbhost_initialize(void) #endif /**************************************************************************** - * Name: stm32_usbhost_vbusdrive + * Name: stm32_usbdrdhost_vbusdrive * * Description: * Enable/disable driving of VBUS 5V output. This function must be @@ -232,7 +232,7 @@ int stm32_usbhost_initialize(void) ****************************************************************************/ #ifdef CONFIG_USBHOST -void stm32h5_usbhost_vbusdrive(int port, bool enable) +void stm32_usbdrdhost_vbusdrive(int port, bool enable) { /* The Nucleo-h563zi doesn't have hardware for a vbus drive. * Instead to get host working, you need to put an extra jumper @@ -265,4 +265,4 @@ int board_usbhost_select_configuration(FAR struct usbhost_hubport_s *hport, } #endif -#endif /* CONFIG_STM32H5_USBFS_HOST */ +#endif /* CONFIG_STM32_USBFS_HOST */ diff --git a/boards/arm/stm32h7/common/CMakeLists.txt b/boards/arm/stm32h7/common/CMakeLists.txt new file mode 100644 index 0000000000000..cad2f907e57fe --- /dev/null +++ b/boards/arm/stm32h7/common/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32h7/common/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(${NUTTX_DIR}/boards/arm/common/stm32 stm32_common) diff --git a/boards/arm/stm32h7/common/Makefile b/boards/arm/stm32h7/common/Makefile new file mode 100644 index 0000000000000..dd26b60c33f68 --- /dev/null +++ b/boards/arm/stm32h7/common/Makefile @@ -0,0 +1,36 @@ +############################################################################# +# boards/arm/stm32h7/common/Makefile +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################# + +include $(TOPDIR)/Make.defs + +STM32_BOARD_COMMON_DIR := $(TOPDIR)$(DELIM)boards$(DELIM)arm$(DELIM)common$(DELIM)stm32 + +include board/Make.defs +include $(STM32_BOARD_COMMON_DIR)$(DELIM)src$(DELIM)Make.defs + +DEPPATH += --dep-path board + +include $(TOPDIR)/boards/Board.mk + +ARCHSRCDIR = $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src +BOARDDIR = $(ARCHSRCDIR)$(DELIM)board +CFLAGS += ${INCDIR_PREFIX}$(BOARDDIR)$(DELIM)include diff --git a/boards/arm/stm32h7/linum-stm32h753bi/configs/buzzer/defconfig b/boards/arm/stm32h7/linum-stm32h753bi/configs/buzzer/defconfig index 81256b344b366..6c5b66cd26959 100644 --- a/boards/arm/stm32h7/linum-stm32h753bi/configs/buzzer/defconfig +++ b/boards/arm/stm32h7/linum-stm32h753bi/configs/buzzer/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="linum-stm32h753bi" CONFIG_ARCH_BOARD_LINUM_STM32H753BI=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H753BI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -47,13 +48,13 @@ CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_PWR=y -CONFIG_STM32H7_RTC=y -CONFIG_STM32H7_TIM4=y -CONFIG_STM32H7_TIM4_CH2OUT=y -CONFIG_STM32H7_TIM4_CHANNEL=2 -CONFIG_STM32H7_TIM4_PWM=y -CONFIG_STM32H7_USART1=y +CONFIG_STM32_PWR=y +CONFIG_STM32_RTC=y +CONFIG_STM32_TIM4=y +CONFIG_STM32_TIM4_CH2OUT=y +CONFIG_STM32_TIM4_CHANNEL=2 +CONFIG_STM32_TIM4_PWM=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32h7/linum-stm32h753bi/configs/eeprom/defconfig b/boards/arm/stm32h7/linum-stm32h753bi/configs/eeprom/defconfig index 5ead89d6a20dc..007834df6637b 100644 --- a/boards/arm/stm32h7/linum-stm32h753bi/configs/eeprom/defconfig +++ b/boards/arm/stm32h7/linum-stm32h753bi/configs/eeprom/defconfig @@ -10,6 +10,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="linum-stm32h753bi" CONFIG_ARCH_BOARD_LINUM_STM32H753BI=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H753BI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -48,10 +49,10 @@ CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_I2C3=y -CONFIG_STM32H7_PWR=y -CONFIG_STM32H7_RTC=y -CONFIG_STM32H7_USART1=y +CONFIG_STM32_I2C3=y +CONFIG_STM32_PWR=y +CONFIG_STM32_RTC=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32h7/linum-stm32h753bi/configs/leds/defconfig b/boards/arm/stm32h7/linum-stm32h753bi/configs/leds/defconfig index 2f5b1ee1c58e2..dad3146608797 100644 --- a/boards/arm/stm32h7/linum-stm32h753bi/configs/leds/defconfig +++ b/boards/arm/stm32h7/linum-stm32h753bi/configs/leds/defconfig @@ -14,6 +14,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="linum-stm32h753bi" CONFIG_ARCH_BOARD_LINUM_STM32H753BI=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H753BI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -50,9 +51,9 @@ CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_PWR=y -CONFIG_STM32H7_RTC=y -CONFIG_STM32H7_USART1=y +CONFIG_STM32_PWR=y +CONFIG_STM32_RTC=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32h7/linum-stm32h753bi/configs/littlefs/defconfig b/boards/arm/stm32h7/linum-stm32h753bi/configs/littlefs/defconfig index ef1fdd8f3fa13..ed872fc7b3ba9 100644 --- a/boards/arm/stm32h7/linum-stm32h753bi/configs/littlefs/defconfig +++ b/boards/arm/stm32h7/linum-stm32h753bi/configs/littlefs/defconfig @@ -13,6 +13,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="linum-stm32h753bi" CONFIG_ARCH_BOARD_LINUM_STM32H753BI=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H753BI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -57,11 +58,11 @@ CONFIG_SPI=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_PWR=y -CONFIG_STM32H7_QSPI_INTERRUPTS=y -CONFIG_STM32H7_QUADSPI=y -CONFIG_STM32H7_RTC=y -CONFIG_STM32H7_USART1=y +CONFIG_STM32_PWR=y +CONFIG_STM32_QSPI=y +CONFIG_STM32_QSPI_INTERRUPTS=y +CONFIG_STM32_RTC=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_SYSTEM_NSH_STACKSIZE=2048 CONFIG_TASK_NAME_SIZE=0 diff --git a/boards/arm/stm32h7/linum-stm32h753bi/configs/lvgl/defconfig b/boards/arm/stm32h7/linum-stm32h753bi/configs/lvgl/defconfig index 0478f18677610..676f5681af176 100644 --- a/boards/arm/stm32h7/linum-stm32h753bi/configs/lvgl/defconfig +++ b/boards/arm/stm32h7/linum-stm32h753bi/configs/lvgl/defconfig @@ -6,13 +6,14 @@ # modifications. # # CONFIG_STANDARD_SERIAL is not set -# CONFIG_STM32H7_FB_CMAP is not set -# CONFIG_STM32H7_LTDC_L1_CHROMAKEYEN is not set -# CONFIG_STM32H7_LTDC_L2 is not set +# CONFIG_STM32_FB_CMAP is not set +# CONFIG_STM32_LTDC_L1_CHROMAKEYEN is not set +# CONFIG_STM32_LTDC_L2 is not set CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="linum-stm32h753bi" CONFIG_ARCH_BOARD_LINUM_STM32H753BI=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H753BI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -66,14 +67,14 @@ CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_FMC=y -CONFIG_STM32H7_I2C3=y -CONFIG_STM32H7_LTDC=y -CONFIG_STM32H7_LTDC_FB_BASE=0xC0600000 -CONFIG_STM32H7_LTDC_FB_SIZE=2097152 -CONFIG_STM32H7_PWR=y -CONFIG_STM32H7_RTC=y -CONFIG_STM32H7_USART1=y +CONFIG_STM32_FMC=y +CONFIG_STM32_I2C3=y +CONFIG_STM32_LTDC=y +CONFIG_STM32_LTDC_FB_BASE=0xC0600000 +CONFIG_STM32_LTDC_FB_SIZE=2097152 +CONFIG_STM32_PWR=y +CONFIG_STM32_RTC=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_TESTING_RAMTEST=y diff --git a/boards/arm/stm32h7/linum-stm32h753bi/configs/mfrc522/defconfig b/boards/arm/stm32h7/linum-stm32h753bi/configs/mfrc522/defconfig index 5f25013c7d1b1..a1d0ec0844fe7 100644 --- a/boards/arm/stm32h7/linum-stm32h753bi/configs/mfrc522/defconfig +++ b/boards/arm/stm32h7/linum-stm32h753bi/configs/mfrc522/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="linum-stm32h753bi" CONFIG_ARCH_BOARD_LINUM_STM32H753BI=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H753BI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -48,10 +49,10 @@ CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_PWR=y -CONFIG_STM32H7_RTC=y -CONFIG_STM32H7_SPI4=y -CONFIG_STM32H7_USART1=y +CONFIG_STM32_PWR=y +CONFIG_STM32_RTC=y +CONFIG_STM32_SPI4=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32h7/linum-stm32h753bi/configs/modbus_master/defconfig b/boards/arm/stm32h7/linum-stm32h753bi/configs/modbus_master/defconfig index 6486a55fbbb22..8f04d2c7ab6c3 100644 --- a/boards/arm/stm32h7/linum-stm32h753bi/configs/modbus_master/defconfig +++ b/boards/arm/stm32h7/linum-stm32h753bi/configs/modbus_master/defconfig @@ -20,6 +20,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="linum-stm32h753bi" CONFIG_ARCH_BOARD_LINUM_STM32H753BI=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H753BI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -60,11 +61,11 @@ CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_PWR=y -CONFIG_STM32H7_RTC=y -CONFIG_STM32H7_UART4=y -CONFIG_STM32H7_USART1=y -CONFIG_STM32H7_USART6=y +CONFIG_STM32_PWR=y +CONFIG_STM32_RTC=y +CONFIG_STM32_UART4=y +CONFIG_STM32_USART1=y +CONFIG_STM32_USART6=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_UART4_BAUD=38400 diff --git a/boards/arm/stm32h7/linum-stm32h753bi/configs/modbus_slave/defconfig b/boards/arm/stm32h7/linum-stm32h753bi/configs/modbus_slave/defconfig index 2579b2ca842aa..8498dcc669e02 100644 --- a/boards/arm/stm32h7/linum-stm32h753bi/configs/modbus_slave/defconfig +++ b/boards/arm/stm32h7/linum-stm32h753bi/configs/modbus_slave/defconfig @@ -14,6 +14,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="linum-stm32h753bi" CONFIG_ARCH_BOARD_LINUM_STM32H753BI=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H753BI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -51,11 +52,11 @@ CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_PWR=y -CONFIG_STM32H7_RTC=y -CONFIG_STM32H7_UART4=y -CONFIG_STM32H7_USART1=y -CONFIG_STM32H7_USART6=y +CONFIG_STM32_PWR=y +CONFIG_STM32_RTC=y +CONFIG_STM32_UART4=y +CONFIG_STM32_USART1=y +CONFIG_STM32_USART6=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_UART4_BAUD=38400 diff --git a/boards/arm/stm32h7/linum-stm32h753bi/configs/netnsh/defconfig b/boards/arm/stm32h7/linum-stm32h753bi/configs/netnsh/defconfig index 8d434e7ed5ea7..0f07506b59bb2 100644 --- a/boards/arm/stm32h7/linum-stm32h753bi/configs/netnsh/defconfig +++ b/boards/arm/stm32h7/linum-stm32h753bi/configs/netnsh/defconfig @@ -10,6 +10,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="linum-stm32h753bi" CONFIG_ARCH_BOARD_LINUM_STM32H753BI=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H753BI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -69,18 +70,18 @@ CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_ETHMAC=y -CONFIG_STM32H7_PHYSR=30 -CONFIG_STM32H7_PHYSR_100FD=0x6 -CONFIG_STM32H7_PHYSR_100HD=0x2 -CONFIG_STM32H7_PHYSR_10FD=0x5 -CONFIG_STM32H7_PHYSR_10HD=0x1 -CONFIG_STM32H7_PHYSR_ALTCONFIG=y -CONFIG_STM32H7_PHYSR_ALTMODE=0x7 -CONFIG_STM32H7_PWR=y -CONFIG_STM32H7_RMII_MCO1=y -CONFIG_STM32H7_RTC=y -CONFIG_STM32H7_USART1=y +CONFIG_STM32_ETHMAC=y +CONFIG_STM32_PHYSR=30 +CONFIG_STM32_PHYSR_100FD=0x6 +CONFIG_STM32_PHYSR_100HD=0x2 +CONFIG_STM32_PHYSR_10FD=0x5 +CONFIG_STM32_PHYSR_10HD=0x1 +CONFIG_STM32_PHYSR_ALTCONFIG=y +CONFIG_STM32_PHYSR_ALTMODE=0x7 +CONFIG_STM32_PWR=y +CONFIG_STM32_RMII_MCO1=y +CONFIG_STM32_RTC=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_SYSTEM_PING=y CONFIG_TASK_NAME_SIZE=0 diff --git a/boards/arm/stm32h7/linum-stm32h753bi/configs/nsh/defconfig b/boards/arm/stm32h7/linum-stm32h753bi/configs/nsh/defconfig index 293a768c652ec..4f5046b5bf403 100644 --- a/boards/arm/stm32h7/linum-stm32h753bi/configs/nsh/defconfig +++ b/boards/arm/stm32h7/linum-stm32h753bi/configs/nsh/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="linum-stm32h753bi" CONFIG_ARCH_BOARD_LINUM_STM32H753BI=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H753BI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -45,9 +46,9 @@ CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_PWR=y -CONFIG_STM32H7_RTC=y -CONFIG_STM32H7_USART1=y +CONFIG_STM32_PWR=y +CONFIG_STM32_RTC=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32h7/linum-stm32h753bi/configs/nxffs/defconfig b/boards/arm/stm32h7/linum-stm32h753bi/configs/nxffs/defconfig index c04492147c903..b15a5f909aa49 100644 --- a/boards/arm/stm32h7/linum-stm32h753bi/configs/nxffs/defconfig +++ b/boards/arm/stm32h7/linum-stm32h753bi/configs/nxffs/defconfig @@ -13,6 +13,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="linum-stm32h753bi" CONFIG_ARCH_BOARD_LINUM_STM32H753BI=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H753BI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -51,11 +52,11 @@ CONFIG_SPI=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_PWR=y -CONFIG_STM32H7_QSPI_INTERRUPTS=y -CONFIG_STM32H7_QUADSPI=y -CONFIG_STM32H7_RTC=y -CONFIG_STM32H7_USART1=y +CONFIG_STM32_PWR=y +CONFIG_STM32_QSPI=y +CONFIG_STM32_QSPI_INTERRUPTS=y +CONFIG_STM32_RTC=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_TESTING_NXFFS=y diff --git a/boards/arm/stm32h7/linum-stm32h753bi/configs/qencoder/defconfig b/boards/arm/stm32h7/linum-stm32h753bi/configs/qencoder/defconfig index 790cb3c5968ed..483c66da52433 100644 --- a/boards/arm/stm32h7/linum-stm32h753bi/configs/qencoder/defconfig +++ b/boards/arm/stm32h7/linum-stm32h753bi/configs/qencoder/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="linum-stm32h753bi" CONFIG_ARCH_BOARD_LINUM_STM32H753BI=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H753BI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -48,11 +49,11 @@ CONFIG_SENSORS_QENCODER=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_PWR=y -CONFIG_STM32H7_RTC=y -CONFIG_STM32H7_TIM5=y -CONFIG_STM32H7_TIM5_QE=y -CONFIG_STM32H7_USART1=y +CONFIG_STM32_PWR=y +CONFIG_STM32_RTC=y +CONFIG_STM32_TIM5=y +CONFIG_STM32_TIM5_QE=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32h7/linum-stm32h753bi/configs/rndis/defconfig b/boards/arm/stm32h7/linum-stm32h753bi/configs/rndis/defconfig index c50bb27796069..ccccc22e495df 100644 --- a/boards/arm/stm32h7/linum-stm32h753bi/configs/rndis/defconfig +++ b/boards/arm/stm32h7/linum-stm32h753bi/configs/rndis/defconfig @@ -10,6 +10,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="linum-stm32h753bi" CONFIG_ARCH_BOARD_LINUM_STM32H753BI=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H753BI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -68,11 +69,11 @@ CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_HSI48=y -CONFIG_STM32H7_OTGFS=y -CONFIG_STM32H7_PWR=y -CONFIG_STM32H7_RTC=y -CONFIG_STM32H7_USART1=y +CONFIG_STM32_HSI48=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PWR=y +CONFIG_STM32_RTC=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_SYSTEM_PING=y CONFIG_TASK_NAME_SIZE=0 diff --git a/boards/arm/stm32h7/linum-stm32h753bi/configs/sdcard/defconfig b/boards/arm/stm32h7/linum-stm32h753bi/configs/sdcard/defconfig index 3dbb6830e6954..f341419ebfccd 100644 --- a/boards/arm/stm32h7/linum-stm32h753bi/configs/sdcard/defconfig +++ b/boards/arm/stm32h7/linum-stm32h753bi/configs/sdcard/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="linum-stm32h753bi" CONFIG_ARCH_BOARD_LINUM_STM32H753BI=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H753BI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -58,11 +59,11 @@ CONFIG_SDMMC1_SDIO_MODE=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_HSI48=y -CONFIG_STM32H7_PWR=y -CONFIG_STM32H7_RTC=y -CONFIG_STM32H7_SDMMC1=y -CONFIG_STM32H7_USART1=y +CONFIG_STM32_HSI48=y +CONFIG_STM32_PWR=y +CONFIG_STM32_RTC=y +CONFIG_STM32_SDMMC1=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32h7/linum-stm32h753bi/configs/sdram/defconfig b/boards/arm/stm32h7/linum-stm32h753bi/configs/sdram/defconfig index b7502e7c4a2c9..3578ec87beb2d 100644 --- a/boards/arm/stm32h7/linum-stm32h753bi/configs/sdram/defconfig +++ b/boards/arm/stm32h7/linum-stm32h753bi/configs/sdram/defconfig @@ -10,6 +10,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="linum-stm32h753bi" CONFIG_ARCH_BOARD_LINUM_STM32H753BI=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H753BI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -45,10 +46,10 @@ CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_FMC=y -CONFIG_STM32H7_PWR=y -CONFIG_STM32H7_RTC=y -CONFIG_STM32H7_USART1=y +CONFIG_STM32_FMC=y +CONFIG_STM32_PWR=y +CONFIG_STM32_RTC=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_TESTING_RAMTEST=y diff --git a/boards/arm/stm32h7/linum-stm32h753bi/configs/socketcan/defconfig b/boards/arm/stm32h7/linum-stm32h753bi/configs/socketcan/defconfig index f79049ddbd2c2..7ef37a7cbf763 100644 --- a/boards/arm/stm32h7/linum-stm32h753bi/configs/socketcan/defconfig +++ b/boards/arm/stm32h7/linum-stm32h753bi/configs/socketcan/defconfig @@ -13,6 +13,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="linum-stm32h753bi" CONFIG_ARCH_BOARD_LINUM_STM32H753BI=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H753BI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -66,9 +67,9 @@ CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_FDCAN1=y -CONFIG_STM32H7_FDCAN2=y -CONFIG_STM32H7_USART1=y +CONFIG_STM32_FDCAN1=y +CONFIG_STM32_FDCAN2=y +CONFIG_STM32_USART1=y CONFIG_SYSLOG_TIMESTAMP=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 diff --git a/boards/arm/stm32h7/linum-stm32h753bi/configs/tone/defconfig b/boards/arm/stm32h7/linum-stm32h753bi/configs/tone/defconfig index 7f6c62f7326f6..2dec3ec83891d 100644 --- a/boards/arm/stm32h7/linum-stm32h753bi/configs/tone/defconfig +++ b/boards/arm/stm32h7/linum-stm32h753bi/configs/tone/defconfig @@ -14,6 +14,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="linum-stm32h753bi" CONFIG_ARCH_BOARD_LINUM_STM32H753BI=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H753BI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -55,15 +56,15 @@ CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_ONESHOT=y -CONFIG_STM32H7_PWR=y -CONFIG_STM32H7_RTC=y -CONFIG_STM32H7_TIM17=y -CONFIG_STM32H7_TIM4=y -CONFIG_STM32H7_TIM4_CH2OUT=y -CONFIG_STM32H7_TIM4_CHANNEL=2 -CONFIG_STM32H7_TIM4_PWM=y -CONFIG_STM32H7_USART1=y +CONFIG_STM32_ONESHOT=y +CONFIG_STM32_PWR=y +CONFIG_STM32_RTC=y +CONFIG_STM32_TIM17=y +CONFIG_STM32_TIM4=y +CONFIG_STM32_TIM4_CH2OUT=y +CONFIG_STM32_TIM4_CHANNEL=2 +CONFIG_STM32_TIM4_PWM=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_CLE=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 diff --git a/boards/arm/stm32h7/linum-stm32h753bi/configs/usbmsc-sdcard/defconfig b/boards/arm/stm32h7/linum-stm32h753bi/configs/usbmsc-sdcard/defconfig index 0c36755c1c72a..3a56b8e9afa90 100644 --- a/boards/arm/stm32h7/linum-stm32h753bi/configs/usbmsc-sdcard/defconfig +++ b/boards/arm/stm32h7/linum-stm32h753bi/configs/usbmsc-sdcard/defconfig @@ -8,11 +8,12 @@ # CONFIG_MMCSD_HAVE_WRITEPROTECT is not set # CONFIG_MMCSD_MMCSUPPORT is not set # CONFIG_STANDARD_SERIAL is not set -# CONFIG_STM32H7_SDMMC_IDMA is not set +# CONFIG_STM32_SDMMC_IDMA is not set CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="linum-stm32h753bi" CONFIG_ARCH_BOARD_LINUM_STM32H753BI=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H753BI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -60,12 +61,12 @@ CONFIG_SDMMC1_SDIO_MODE=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_HSI48=y -CONFIG_STM32H7_OTGFS=y -CONFIG_STM32H7_PWR=y -CONFIG_STM32H7_RTC=y -CONFIG_STM32H7_SDMMC1=y -CONFIG_STM32H7_USART1=y +CONFIG_STM32_HSI48=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PWR=y +CONFIG_STM32_RTC=y +CONFIG_STM32_SDMMC1=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_SYSTEM_USBMSC=y CONFIG_SYSTEM_USBMSC_DEVMINOR1=0 diff --git a/boards/arm/stm32h7/linum-stm32h753bi/configs/usbnsh/defconfig b/boards/arm/stm32h7/linum-stm32h753bi/configs/usbnsh/defconfig index 77d040d77ad81..3772f3440ed27 100644 --- a/boards/arm/stm32h7/linum-stm32h753bi/configs/usbnsh/defconfig +++ b/boards/arm/stm32h7/linum-stm32h753bi/configs/usbnsh/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="linum-stm32h753bi" CONFIG_ARCH_BOARD_LINUM_STM32H753BI=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H753BI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -49,11 +50,11 @@ CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_HSI48=y -CONFIG_STM32H7_OTGFS=y -CONFIG_STM32H7_PWR=y -CONFIG_STM32H7_RTC=y -CONFIG_STM32H7_USART1=y +CONFIG_STM32_HSI48=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PWR=y +CONFIG_STM32_RTC=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USBDEV=y diff --git a/boards/arm/stm32h7/linum-stm32h753bi/configs/zmodem/defconfig b/boards/arm/stm32h7/linum-stm32h753bi/configs/zmodem/defconfig index 12364f56d134b..e2faa065b1b7a 100644 --- a/boards/arm/stm32h7/linum-stm32h753bi/configs/zmodem/defconfig +++ b/boards/arm/stm32h7/linum-stm32h753bi/configs/zmodem/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="linum-stm32h753bi" CONFIG_ARCH_BOARD_LINUM_STM32H753BI=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H753BI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -65,12 +66,12 @@ CONFIG_SDMMC1_SDIO_MODE=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_HSI48=y -CONFIG_STM32H7_OTGFS=y -CONFIG_STM32H7_PWR=y -CONFIG_STM32H7_RTC=y -CONFIG_STM32H7_SDMMC1=y -CONFIG_STM32H7_USART1=y +CONFIG_STM32_HSI48=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PWR=y +CONFIG_STM32_RTC=y +CONFIG_STM32_SDMMC1=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_SYSTEM_ZMODEM=y CONFIG_SYSTEM_ZMODEM_PKTBUFSIZE=1024 diff --git a/boards/arm/stm32h7/linum-stm32h753bi/include/board.h b/boards/arm/stm32h7/linum-stm32h753bi/include/board.h index 3072adbe60fba..d4283242bc221 100644 --- a/boards/arm/stm32h7/linum-stm32h753bi/include/board.h +++ b/boards/arm/stm32h7/linum-stm32h753bi/include/board.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32H7_LINUM_STM32H753BI_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32H7_LINUM_STM32H753BI_INCLUDE_BOARD_H +#ifndef __BOARDS_ARM_STM32_LINUM_STM32H753BI_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32_LINUM_STM32H753BI_INCLUDE_BOARD_H /**************************************************************************** * Included Files @@ -488,7 +488,7 @@ * linum board routes only DQ[15:0] bits. */ -#if CONFIG_STM32H7_FMC +#if CONFIG_STM32_FMC # define FMC_SDCLK_FREQUENCY (STM32_HCLK_FREQUENCY / 2) # if FMC_SDCLK_FREQUENCY > 120000000 # error "FMC SDRAM settings need to be adjusted for a higher FMC_SDCLK frequency" @@ -502,7 +502,7 @@ * this value will need to be doubled. */ -#ifdef CONFIG_STM32H7_LTDC +#ifdef CONFIG_STM32_LTDC # define BOARD_SDRAM1_SIZE (6*1024*1024) #else # define BOARD_SDRAM1_SIZE (8*1024*1024) @@ -684,4 +684,4 @@ extern "C" #endif #endif /* __ASSEMBLY__ */ -#endif /* __BOARDS_ARM_STM32H7_LINUM_STM32H753BI_INCLUDE_BOARD_H */ +#endif /* __BOARDS_ARM_STM32_LINUM_STM32H753BI_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32h7/linum-stm32h753bi/src/CMakeLists.txt b/boards/arm/stm32h7/linum-stm32h753bi/src/CMakeLists.txt index d0d7904d73a2b..e4b1d4e927545 100644 --- a/boards/arm/stm32h7/linum-stm32h753bi/src/CMakeLists.txt +++ b/boards/arm/stm32h7/linum-stm32h753bi/src/CMakeLists.txt @@ -30,11 +30,11 @@ if(CONFIG_USERLED) list(APPEND SRCS stm32_userled.c) endif() -if(CONFIG_STM32H7_OTGFS) +if(CONFIG_STM32_OTGFS) list(APPEND SRCS stm32_usb.c) endif() -if(CONFIG_STM32H7_SDMMC) +if(CONFIG_STM32_SDMMC) list(APPEND SRCS stm32_sdmmc.c) endif() @@ -70,7 +70,7 @@ if(CONFIG_CL_MFRC522) list(APPEND SRCS stm32_mfrc522.c) endif() -if(CONFIG_STM32H7_LTDC) +if(CONFIG_STM32_LTDC) list(APPEND SRCS stm32_lcd.c) endif() diff --git a/boards/arm/stm32h7/linum-stm32h753bi/src/Make.defs b/boards/arm/stm32h7/linum-stm32h753bi/src/Make.defs new file mode 100644 index 0000000000000..84da9cb175914 --- /dev/null +++ b/boards/arm/stm32h7/linum-stm32h753bi/src/Make.defs @@ -0,0 +1,85 @@ +############################################################################ +# boards/arm/stm32h7/linum-stm32h753bi/src/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +CSRCS = stm32_boot.c stm32_bringup.c stm32_spi.c + +ifeq ($(CONFIG_ARCH_LEDS),y) +CSRCS += stm32_autoleds.c +else + ifeq ($(CONFIG_USERLED),y) + CSRCS += stm32_userleds.c + endif +endif + +ifeq ($(CONFIG_STM32_OTGFS),y) +CSRCS += stm32_usb.c +endif + +ifeq ($(CONFIG_STM32_SDMMC),y) +CSRCS += stm32_sdmmc.c +endif + +ifeq ($(CONFIG_FAT_DMAMEMORY),y) +CSRCS += stm32_dma_alloc.c +endif + +ifeq ($(CONFIG_I2C_EE_24XX),y) +CSRCS += stm32_at24.c +endif + +ifeq ($(CONFIG_PWM),y) +CSRCS += stm32_pwm.c +endif + +ifeq ($(CONFIG_MTD_W25QXXXJV),y) +CSRCS += stm32_w25q.c +endif + +ifeq ($(CONFIG_USBMSC),y) +CSRCS += stm32_usbmsc.c +endif + +ifeq ($(CONFIG_SENSORS_QENCODER),y) +CSRCS += stm32_qencoder.c +endif + +ifeq ($(CONFIG_CL_MFRC522),y) + CSRCS += stm32_mfrc522.c +endif + +ifeq ($(CONFIG_STM32_LTDC),y) +CSRCS += stm32_lcd.c +endif + +ifeq ($(CONFIG_AUDIO_TONE),y) + CSRCS += stm32_tone.c +endif + +ifeq ($(CONFIG_INPUT_FT5X06),y) +CSRCS += stm32_touchscreen.c +endif + +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32h7/linum-stm32h753bi/src/Makefile b/boards/arm/stm32h7/linum-stm32h753bi/src/Makefile deleted file mode 100644 index c2ae5df6f581a..0000000000000 --- a/boards/arm/stm32h7/linum-stm32h753bi/src/Makefile +++ /dev/null @@ -1,83 +0,0 @@ -############################################################################ -# boards/arm/stm32h7/linum-stm32h753bi/src/Makefile -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/Make.defs - -CSRCS = stm32_boot.c stm32_bringup.c stm32_spi.c - -ifeq ($(CONFIG_ARCH_LEDS),y) -CSRCS += stm32_autoleds.c -else - ifeq ($(CONFIG_USERLED),y) - CSRCS += stm32_userleds.c - endif -endif - -ifeq ($(CONFIG_STM32H7_OTGFS),y) -CSRCS += stm32_usb.c -endif - -ifeq ($(CONFIG_STM32H7_SDMMC),y) -CSRCS += stm32_sdmmc.c -endif - -ifeq ($(CONFIG_FAT_DMAMEMORY),y) -CSRCS += stm32_dma_alloc.c -endif - -ifeq ($(CONFIG_I2C_EE_24XX),y) -CSRCS += stm32_at24.c -endif - -ifeq ($(CONFIG_PWM),y) -CSRCS += stm32_pwm.c -endif - -ifeq ($(CONFIG_MTD_W25QXXXJV),y) -CSRCS += stm32_w25q.c -endif - -ifeq ($(CONFIG_USBMSC),y) -CSRCS += stm32_usbmsc.c -endif - -ifeq ($(CONFIG_SENSORS_QENCODER),y) -CSRCS += stm32_qencoder.c -endif - -ifeq ($(CONFIG_CL_MFRC522),y) - CSRCS += stm32_mfrc522.c -endif - -ifeq ($(CONFIG_STM32H7_LTDC),y) -CSRCS += stm32_lcd.c -endif - -ifeq ($(CONFIG_AUDIO_TONE),y) - CSRCS += stm32_tone.c -endif - -ifeq ($(CONFIG_INPUT_FT5X06),y) -CSRCS += stm32_touchscreen.c -endif - -include $(TOPDIR)/boards/Board.mk diff --git a/boards/arm/stm32h7/linum-stm32h753bi/src/linum-stm32h753bi.h b/boards/arm/stm32h7/linum-stm32h753bi/src/linum-stm32h753bi.h index 8ce1c6eee650e..f08543a9734f1 100644 --- a/boards/arm/stm32h7/linum-stm32h753bi/src/linum-stm32h753bi.h +++ b/boards/arm/stm32h7/linum-stm32h753bi/src/linum-stm32h753bi.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32H7_LINUM_STM32H753BI_SRC_LINUM_STM32H753BI_H -#define __BOARDS_ARM_STM32H7_LINUM_STM32H753BI_SRC_LINUM_STM32H753BI_H +#ifndef __BOARDS_ARM_STM32_LINUM_STM32H753BI_SRC_LINUM_STM32H753BI_H +#define __BOARDS_ARM_STM32_LINUM_STM32H753BI_SRC_LINUM_STM32H753BI_H /**************************************************************************** * Included Files @@ -86,7 +86,7 @@ * PD7 Enable power supply SD Card pin */ -#if defined(CONFIG_STM32H7_SDMMC1) +#if defined(CONFIG_STM32_SDMMC1) # define HAVE_SDIO #endif @@ -162,7 +162,7 @@ int stm32_bringup(void); * ****************************************************************************/ -#ifdef CONFIG_STM32H7_OTGFS +#ifdef CONFIG_STM32_OTGFS void weak_function stm32_usbinitialize(void); #endif @@ -225,7 +225,7 @@ int stm32_pwm_setup(void); * ****************************************************************************/ -#ifdef CONFIG_STM32H7_SPI +#ifdef CONFIG_STM32_SPI void stm32_spidev_initialize(void); #endif @@ -305,4 +305,4 @@ int board_tone_initialize(int devno); int stm32_tsc_setup(int minor); #endif -#endif /* __BOARDS_ARM_STM32H7_LINUM_STM32H753BI_SRC_LINUM_STM32H753BI_H */ +#endif /* __BOARDS_ARM_STM32_LINUM_STM32H753BI_SRC_LINUM_STM32H753BI_H */ diff --git a/boards/arm/stm32h7/linum-stm32h753bi/src/stm32_bringup.c b/boards/arm/stm32h7/linum-stm32h753bi/src/stm32_bringup.c index bab56899d14b3..02f6a1cc0ae3b 100644 --- a/boards/arm/stm32h7/linum-stm32h753bi/src/stm32_bringup.c +++ b/boards/arm/stm32h7/linum-stm32h753bi/src/stm32_bringup.c @@ -47,7 +47,7 @@ # include "stm32_rtc.h" #endif -#ifdef CONFIG_STM32H7_FDCAN +#ifdef CONFIG_STM32_FDCAN #include "stm32_fdcan_sock.h" #endif @@ -132,10 +132,10 @@ static void stm32_i2c_register(int bus) #if defined(CONFIG_I2C) && defined(CONFIG_SYSTEM_I2CTOOL) static void stm32_i2ctool(void) { -#ifdef CONFIG_STM32H7_I2C3 +#ifdef CONFIG_STM32_I2C3 stm32_i2c_register(3); #endif -#ifdef CONFIG_STM32H7_I2C4 +#ifdef CONFIG_STM32_I2C4 stm32_i2c_register(4); #endif } @@ -166,7 +166,7 @@ int stm32_bringup(void) struct rtc_lowerhalf_s *lower; #endif -#ifdef CONFIG_STM32H7_RMII +#ifdef CONFIG_STM32_RMII /* Reset Ethernet PHY */ stm32_configgpio(GPIO_ETH_RESET); @@ -289,7 +289,7 @@ int stm32_bringup(void) #ifdef CONFIG_NETDEV_LATEINIT -# ifdef CONFIG_STM32H7_FDCAN1 +# ifdef CONFIG_STM32_FDCAN1 /* Enable and configure CAN1 */ @@ -298,7 +298,7 @@ int stm32_bringup(void) stm32_fdcansockinitialize(0); # endif -# ifdef CONFIG_STM32H7_FDCAN2 +# ifdef CONFIG_STM32_FDCAN2 /* Enable and configure CAN2 */ diff --git a/boards/arm/stm32h7/linum-stm32h753bi/src/stm32_lcd.c b/boards/arm/stm32h7/linum-stm32h753bi/src/stm32_lcd.c index 15113bb0f06d5..bc5b9ffcacb12 100644 --- a/boards/arm/stm32h7/linum-stm32h753bi/src/stm32_lcd.c +++ b/boards/arm/stm32h7/linum-stm32h753bi/src/stm32_lcd.c @@ -39,7 +39,7 @@ #include "linum-stm32h753bi.h" -#ifdef CONFIG_STM32H7_LTDC +#ifdef CONFIG_STM32_LTDC /**************************************************************************** * Public Functions ****************************************************************************/ diff --git a/boards/arm/stm32h7/linum-stm32h753bi/src/stm32_mfrc522.c b/boards/arm/stm32h7/linum-stm32h753bi/src/stm32_mfrc522.c index de8539d1a6fcd..097d5fc17aee2 100644 --- a/boards/arm/stm32h7/linum-stm32h753bi/src/stm32_mfrc522.c +++ b/boards/arm/stm32h7/linum-stm32h753bi/src/stm32_mfrc522.c @@ -36,7 +36,7 @@ #include "linum-stm32h753bi.h" #include "stm32_spi.h" -#if defined(CONFIG_SPI) && defined(CONFIG_STM32H7_SPI4) && defined(CONFIG_CL_MFRC522) +#if defined(CONFIG_SPI) && defined(CONFIG_STM32_SPI4) && defined(CONFIG_CL_MFRC522) /**************************************************************************** * Pre-processor Definitions @@ -83,4 +83,4 @@ int stm32_mfrc522initialize(const char *devpath) return ret; } -#endif /* CONFIG_SPI && CONFIG_STM32H7_SPI4 && CONFIG_MFRC522 */ +#endif /* CONFIG_SPI && CONFIG_STM32_SPI4 && CONFIG_MFRC522 */ diff --git a/boards/arm/stm32h7/linum-stm32h753bi/src/stm32_pwm.c b/boards/arm/stm32h7/linum-stm32h753bi/src/stm32_pwm.c index b64a561aa2a99..18b39f615b11a 100644 --- a/boards/arm/stm32h7/linum-stm32h753bi/src/stm32_pwm.c +++ b/boards/arm/stm32h7/linum-stm32h753bi/src/stm32_pwm.c @@ -49,11 +49,11 @@ # undef HAVE_PWM #endif -#ifndef CONFIG_STM32H7_TIM4 +#ifndef CONFIG_STM32_TIM4 # undef HAVE_PWM #endif -#ifndef CONFIG_STM32H7_TIM4_PWM +#ifndef CONFIG_STM32_TIM4_PWM # undef HAVE_PWM #endif diff --git a/boards/arm/stm32h7/linum-stm32h753bi/src/stm32_spi.c b/boards/arm/stm32h7/linum-stm32h753bi/src/stm32_spi.c index cf5467941e08a..77db8bb8c3f4c 100644 --- a/boards/arm/stm32h7/linum-stm32h753bi/src/stm32_spi.c +++ b/boards/arm/stm32h7/linum-stm32h753bi/src/stm32_spi.c @@ -41,7 +41,7 @@ #include "linum-stm32h753bi.h" #include -#ifdef CONFIG_STM32H7_SPI +#ifdef CONFIG_STM32_SPI /**************************************************************************** * Public Functions @@ -89,7 +89,7 @@ void stm32_spidev_initialize(void) * ****************************************************************************/ -#ifdef CONFIG_STM32H7_SPI4 +#ifdef CONFIG_STM32_SPI4 void stm32_spi4select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -132,7 +132,7 @@ uint8_t stm32_spi4status(struct spi_dev_s *dev, uint32_t devid) ****************************************************************************/ #ifdef CONFIG_SPI_CMDDATA -#ifdef CONFIG_STM32H7_SPI4 +#ifdef CONFIG_STM32_SPI4 int stm32_spi4cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; @@ -140,4 +140,4 @@ int stm32_spi4cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) #endif #endif /* CONFIG_SPI_CMDDATA */ -#endif /* CONFIG_STM32H7_SPI4 */ +#endif /* CONFIG_STM32_SPI4 */ diff --git a/boards/arm/stm32h7/linum-stm32h753bi/src/stm32_touchscreen.c b/boards/arm/stm32h7/linum-stm32h753bi/src/stm32_touchscreen.c index 0ffbbc6e81ae7..76ff702a627bd 100644 --- a/boards/arm/stm32h7/linum-stm32h753bi/src/stm32_touchscreen.c +++ b/boards/arm/stm32h7/linum-stm32h753bi/src/stm32_touchscreen.c @@ -48,8 +48,8 @@ # error "FT5x06 support requires CONFIG_INPUT" #endif -#ifndef CONFIG_STM32H7_I2C3 -# error "FT5x06 support requires CONFIG_STM32H7_I2C3" +#ifndef CONFIG_STM32_I2C3 +# error "FT5x06 support requires CONFIG_STM32_I2C3" #endif #ifndef CONFIG_FT5X06_I2CDEV diff --git a/boards/arm/stm32h7/linum-stm32h753bi/src/stm32_usb.c b/boards/arm/stm32h7/linum-stm32h753bi/src/stm32_usb.c index 88b139eb458ed..884e370b0c9fd 100644 --- a/boards/arm/stm32h7/linum-stm32h753bi/src/stm32_usb.c +++ b/boards/arm/stm32h7/linum-stm32h753bi/src/stm32_usb.c @@ -45,7 +45,7 @@ #include "stm32_otg.h" #include "linum-stm32h753bi.h" -#ifdef CONFIG_STM32H7_OTGFS +#ifdef CONFIG_STM32_OTGFS /**************************************************************************** * Pre-processor Definitions @@ -138,7 +138,7 @@ void stm32_usbinitialize(void) * Power On, and Overcurrent GPIOs */ -#ifdef CONFIG_STM32H7_OTGFS +#ifdef CONFIG_STM32_OTGFS stm32_configgpio(GPIO_OTGFS_VBUS); stm32_configgpio(GPIO_OTGFS_PWRON); stm32_configgpio(GPIO_OTGFS_OVER); diff --git a/boards/arm/stm32h7/linum-stm32h753bi/src/stm32_w25q.c b/boards/arm/stm32h7/linum-stm32h753bi/src/stm32_w25q.c index 26a494c7619a6..98c8454c49c6b 100644 --- a/boards/arm/stm32h7/linum-stm32h753bi/src/stm32_w25q.c +++ b/boards/arm/stm32h7/linum-stm32h753bi/src/stm32_w25q.c @@ -79,7 +79,7 @@ int stm32_w25qxxx_setup(void) struct mtd_dev_s *mtd_dev; int ret = -1; - qspi_dev = stm32h7_qspi_initialize(0); + qspi_dev = stm32_qspi_initialize(0); if (!qspi_dev) { _err("ERROR: Failed to initialize W25 minor %d: %d\n", diff --git a/boards/arm/stm32h7/nucleo-h723zg/configs/netnsh/defconfig b/boards/arm/stm32h7/nucleo-h723zg/configs/netnsh/defconfig index 9008dcbeb9583..e73fc9f8fa830 100644 --- a/boards/arm/stm32h7/nucleo-h723zg/configs/netnsh/defconfig +++ b/boards/arm/stm32h7/nucleo-h723zg/configs/netnsh/defconfig @@ -10,6 +10,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-h723zg" CONFIG_ARCH_BOARD_NUCLEO_H723ZG=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H723ZG=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -67,19 +68,19 @@ CONFIG_SPI=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_DTCMEXCLUDE=y -CONFIG_STM32H7_ETHMAC=y -CONFIG_STM32H7_FLASH_OVERRIDE_G=y -CONFIG_STM32H7_HSI48=y -CONFIG_STM32H7_PHYSR=31 -CONFIG_STM32H7_PHYSR_100FD=0x0018 -CONFIG_STM32H7_PHYSR_100HD=0x0008 -CONFIG_STM32H7_PHYSR_10FD=0x0014 -CONFIG_STM32H7_PHYSR_10HD=0x0004 -CONFIG_STM32H7_PHYSR_ALTCONFIG=y -CONFIG_STM32H7_PHYSR_ALTMODE=0x001c -CONFIG_STM32H7_SRAM4EXCLUDE=y -CONFIG_STM32H7_USART3=y +CONFIG_STM32_DTCMEXCLUDE=y +CONFIG_STM32_ETHMAC=y +CONFIG_STM32_FLASH_OVERRIDE_G=y +CONFIG_STM32_HSI48=y +CONFIG_STM32_PHYSR=31 +CONFIG_STM32_PHYSR_100FD=0x0018 +CONFIG_STM32_PHYSR_100HD=0x0008 +CONFIG_STM32_PHYSR_10FD=0x0014 +CONFIG_STM32_PHYSR_10HD=0x0004 +CONFIG_STM32_PHYSR_ALTCONFIG=y +CONFIG_STM32_PHYSR_ALTMODE=0x001c +CONFIG_STM32_SRAM4EXCLUDE=y +CONFIG_STM32_USART3=y CONFIG_SYSTEM_DHCPC_RENEW=y CONFIG_SYSTEM_NSH=y CONFIG_SYSTEM_PING=y diff --git a/boards/arm/stm32h7/nucleo-h723zg/configs/nsh/defconfig b/boards/arm/stm32h7/nucleo-h723zg/configs/nsh/defconfig index bd2ea04db96f7..11f85e483ede7 100644 --- a/boards/arm/stm32h7/nucleo-h723zg/configs/nsh/defconfig +++ b/boards/arm/stm32h7/nucleo-h723zg/configs/nsh/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-h723zg" CONFIG_ARCH_BOARD_NUCLEO_H723ZG=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H723ZG=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -45,10 +46,10 @@ CONFIG_SPI=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_DTCMEXCLUDE=y -CONFIG_STM32H7_FLASH_OVERRIDE_G=y -CONFIG_STM32H7_SRAM4EXCLUDE=y -CONFIG_STM32H7_USART3=y +CONFIG_STM32_DTCMEXCLUDE=y +CONFIG_STM32_FLASH_OVERRIDE_G=y +CONFIG_STM32_SRAM4EXCLUDE=y +CONFIG_STM32_USART3=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART3_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32h7/nucleo-h723zg/configs/oa_tc6/defconfig b/boards/arm/stm32h7/nucleo-h723zg/configs/oa_tc6/defconfig index 314c36575b7f0..715f1f0df18b0 100644 --- a/boards/arm/stm32h7/nucleo-h723zg/configs/oa_tc6/defconfig +++ b/boards/arm/stm32h7/nucleo-h723zg/configs/oa_tc6/defconfig @@ -10,6 +10,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-h723zg" CONFIG_ARCH_BOARD_NUCLEO_H723ZG=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H723ZG=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -73,11 +74,11 @@ CONFIG_STACK_COLORATION=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_DTCMEXCLUDE=y -CONFIG_STM32H7_FLASH_OVERRIDE_G=y -CONFIG_STM32H7_SPI3=y -CONFIG_STM32H7_SRAM4EXCLUDE=y -CONFIG_STM32H7_USART3=y +CONFIG_STM32_DTCMEXCLUDE=y +CONFIG_STM32_FLASH_OVERRIDE_G=y +CONFIG_STM32_SPI3=y +CONFIG_STM32_SRAM4EXCLUDE=y +CONFIG_STM32_USART3=y CONFIG_SYSTEM_DHCPC_RENEW=y CONFIG_SYSTEM_NSH=y CONFIG_SYSTEM_PING6=y diff --git a/boards/arm/stm32h7/nucleo-h723zg/include/board.h b/boards/arm/stm32h7/nucleo-h723zg/include/board.h index e2dba2fa23a41..41d7e715f06a1 100644 --- a/boards/arm/stm32h7/nucleo-h723zg/include/board.h +++ b/boards/arm/stm32h7/nucleo-h723zg/include/board.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32H7_NUCLEO_H723ZG_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32H7_NUCLEO_H723ZG_INCLUDE_BOARD_H +#ifndef __BOARDS_ARM_STM32_NUCLEO_H723ZG_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32_NUCLEO_H723ZG_INCLUDE_BOARD_H /**************************************************************************** * Included Files @@ -518,4 +518,4 @@ extern "C" #endif #endif /* __ASSEMBLY__ */ -#endif /* __BOARDS_ARM_STM32H7_NUCLEO_H723ZG_INCLUDE_BOARD_H */ +#endif /* __BOARDS_ARM_STM32_NUCLEO_H723ZG_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32h7/nucleo-h723zg/src/CMakeLists.txt b/boards/arm/stm32h7/nucleo-h723zg/src/CMakeLists.txt index f27901f9491cb..95677ecec03e2 100644 --- a/boards/arm/stm32h7/nucleo-h723zg/src/CMakeLists.txt +++ b/boards/arm/stm32h7/nucleo-h723zg/src/CMakeLists.txt @@ -36,11 +36,11 @@ if(CONFIG_ARCH_BUTTONS) list(APPEND SRCS stm32_buttons.c) endif() -if(CONFIG_STM32H7_SPI) +if(CONFIG_STM32_SPI) list(APPEND SRCS stm32_spi.c) endif() -if(CONFIG_STM32H7_OTGHS) +if(CONFIG_STM32_OTGHS) list(APPEND SRCS stm32_usb.c) endif() @@ -56,10 +56,6 @@ if(CONFIG_PWM) list(APPEND SRCS stm32_pwm.c) endif() -if(CONFIG_BOARDCTL_RESET) - list(APPEND SRCS stm32_reset.c) -endif() - if(CONFIG_NET_OA_TC6) list(APPEND SRCS stm32_oa_tc6.c) endif() diff --git a/boards/arm/stm32h7/nucleo-h723zg/src/Make.defs b/boards/arm/stm32h7/nucleo-h723zg/src/Make.defs new file mode 100644 index 0000000000000..21b86d15ae5d5 --- /dev/null +++ b/boards/arm/stm32h7/nucleo-h723zg/src/Make.defs @@ -0,0 +1,67 @@ +############################################################################ +# boards/arm/stm32h7/nucleo-h723zg/src/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +CSRCS = stm32_boot.c stm32_bringup.c + +ifeq ($(CONFIG_ADC),y) +CSRCS += stm32_adc.c +endif + +ifeq ($(CONFIG_ARCH_LEDS),y) +CSRCS += stm32_autoleds.c +else +CSRCS += stm32_userleds.c +endif + +ifeq ($(CONFIG_ARCH_BUTTONS),y) +CSRCS += stm32_buttons.c +endif + +ifeq ($(CONFIG_STM32_SPI),y) +CSRCS += stm32_spi.c +endif + +ifeq ($(CONFIG_STM32_OTGHS),y) +CSRCS += stm32_usb.c +endif + +ifeq ($(CONFIG_BOARDCTL_UNIQUEID),y) +CSRCS += stm32_uid.c +endif + +ifeq ($(CONFIG_DEV_GPIO),y) +CSRCS += stm32_gpio.c +endif + +ifeq ($(CONFIG_PWM),y) +CSRCS += stm32_pwm.c +endif + +ifeq ($(CONFIG_NET_OA_TC6),y) +CSRCS += stm32_oa_tc6.c +endif + +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32h7/nucleo-h723zg/src/Makefile b/boards/arm/stm32h7/nucleo-h723zg/src/Makefile deleted file mode 100644 index dedc375fb9c05..0000000000000 --- a/boards/arm/stm32h7/nucleo-h723zg/src/Makefile +++ /dev/null @@ -1,69 +0,0 @@ -############################################################################ -# boards/arm/stm32h7/nucleo-h723zg/src/Makefile -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/Make.defs - -CSRCS = stm32_boot.c stm32_bringup.c - -ifeq ($(CONFIG_ADC),y) -CSRCS += stm32_adc.c -endif - -ifeq ($(CONFIG_ARCH_LEDS),y) -CSRCS += stm32_autoleds.c -else -CSRCS += stm32_userleds.c -endif - -ifeq ($(CONFIG_ARCH_BUTTONS),y) -CSRCS += stm32_buttons.c -endif - -ifeq ($(CONFIG_STM32H7_SPI),y) -CSRCS += stm32_spi.c -endif - -ifeq ($(CONFIG_STM32H7_OTGHS),y) -CSRCS += stm32_usb.c -endif - -ifeq ($(CONFIG_BOARDCTL_UNIQUEID),y) -CSRCS += stm32_uid.c -endif - -ifeq ($(CONFIG_DEV_GPIO),y) -CSRCS += stm32_gpio.c -endif - -ifeq ($(CONFIG_PWM),y) -CSRCS += stm32_pwm.c -endif - -ifeq ($(CONFIG_BOARDCTL_RESET),y) -CSRCS += stm32_reset.c -endif - -ifeq ($(CONFIG_NET_OA_TC6),y) -CSRCS += stm32_oa_tc6.c -endif - -include $(TOPDIR)/boards/Board.mk diff --git a/boards/arm/stm32h7/nucleo-h723zg/src/nucleo-h723zg.h b/boards/arm/stm32h7/nucleo-h723zg/src/nucleo-h723zg.h index b9036604f880b..58d1bb2ca7b11 100644 --- a/boards/arm/stm32h7/nucleo-h723zg/src/nucleo-h723zg.h +++ b/boards/arm/stm32h7/nucleo-h723zg/src/nucleo-h723zg.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32H7_NUCLEO_H723ZG_SRC_NUCLEO_H723ZG_H -#define __BOARDS_ARM_STM32H7_NUCLEO_H723ZG_SRC_NUCLEO_H723ZG_H +#ifndef __BOARDS_ARM_STM32_NUCLEO_H723ZG_SRC_NUCLEO_H723ZG_H +#define __BOARDS_ARM_STM32_NUCLEO_H723ZG_SRC_NUCLEO_H723ZG_H /**************************************************************************** * Included Files @@ -46,7 +46,7 @@ /* Can't support USB host or device features if USB OTG HS is not enabled */ -#ifndef CONFIG_STM32H7_OTGHS +#ifndef CONFIG_STM32_OTGHS # undef HAVE_USBDEV #endif @@ -74,7 +74,7 @@ # undef HAVE_USBMONITOR #endif -#if !defined(CONFIG_STM32H7_PROGMEM) || !defined(CONFIG_MTD_PROGMEM) +#if !defined(CONFIG_STM32_PROGMEM) || !defined(CONFIG_MTD_PROGMEM) # undef HAVE_PROGMEM_CHARDEV #endif @@ -213,7 +213,7 @@ int stm32_bringup(void); * ****************************************************************************/ -#ifdef CONFIG_STM32H7_SPI +#ifdef CONFIG_STM32_SPI void stm32_spidev_initialize(void); #endif @@ -250,7 +250,7 @@ int stm32_gpio_initialize(void); * ****************************************************************************/ -#ifdef CONFIG_STM32H7_OTGHS +#ifdef CONFIG_STM32_OTGHS void weak_function stm32_usbinitialize(void); #endif @@ -278,4 +278,4 @@ int stm32_pwm_setup(void); int stm32_oa_tc6_initialize(void); #endif -#endif /* __BOARDS_ARM_STM32H7_NUCLEO_H723ZG_SRC_NUCLEO_H723ZG_H */ +#endif /* __BOARDS_ARM_STM32_NUCLEO_H723ZG_SRC_NUCLEO_H723ZG_H */ diff --git a/boards/arm/stm32h7/nucleo-h723zg/src/stm32_adc.c b/boards/arm/stm32h7/nucleo-h723zg/src/stm32_adc.c index 8170b1decc7f3..1a4bc8d2eafa4 100644 --- a/boards/arm/stm32h7/nucleo-h723zg/src/stm32_adc.c +++ b/boards/arm/stm32h7/nucleo-h723zg/src/stm32_adc.c @@ -48,8 +48,8 @@ /* Up to 3 ADC interfaces are supported */ -#if defined(CONFIG_STM32H7_ADC1) || defined(CONFIG_STM32H7_ADC2) || \ - defined(CONFIG_STM32H7_ADC3) +#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) || \ + defined(CONFIG_STM32_ADC3) /* The number of ADC channels in the conversion list */ @@ -61,7 +61,7 @@ * Private Data ****************************************************************************/ -#ifdef CONFIG_STM32H7_ADC1 +#ifdef CONFIG_STM32_ADC1 /* Identifying number of each ADC channel: Variable Resistor. * * ADC1: {5, 10, 15, 18, 19, 7, 12}; @@ -83,12 +83,12 @@ static const uint32_t g_adc1_pinlist[ADC1_NCHANNELS] = GPIO_ADC123_INP12 }; -#endif /* CONFIG_STM32H7_ADC1 */ +#endif /* CONFIG_STM32_ADC1 */ /**************************************************************************** * ADC2 ****************************************************************************/ -#ifdef CONFIG_STM32H7_ADC2 +#ifdef CONFIG_STM32_ADC2 static const uint8_t g_adc2_chanlist[ADC2_NCHANNELS] = { @@ -103,9 +103,9 @@ static const uint32_t g_adc2_pinlist[ADC2_NCHANNELS] = GPIO_ADC12_INP4, GPIO_ADC12_INP8 }; -#endif /* CONFIG_STM32H7_ADC2 */ +#endif /* CONFIG_STM32_ADC2 */ -#ifdef CONFIG_STM32H7_ADC3 +#ifdef CONFIG_STM32_ADC3 /* Identifying number of each ADC channel: Variable Resistor. * * ADC3: {6,}; @@ -146,7 +146,7 @@ static const uint32_t g_adc3_pinlist[ADC3_NCHANNELS] = int stm32_adc_setup(void) { -#if defined(CONFIG_STM32H7_ADC1) || defined(CONFIG_STM32H7_ADC3) +#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC3) static bool initialized = false; struct adc_dev_s *adc; int ret; @@ -158,7 +158,7 @@ int stm32_adc_setup(void) if (!initialized) { #endif -#if defined(CONFIG_STM32H7_ADC1) +#if defined(CONFIG_STM32_ADC1) /* Configure the pins as analog inputs for the selected channels */ for (i = 0; i < ADC1_NCHANNELS; i++) @@ -171,7 +171,7 @@ int stm32_adc_setup(void) /* Call stm32_adcinitialize() to get an instance of the ADC interface */ - adc = stm32h7_adc_initialize(1, g_adc1_chanlist, ADC1_NCHANNELS); + adc = stm32_adc_initialize(1, g_adc1_chanlist, ADC1_NCHANNELS); if (adc == NULL) { aerr("ERROR: Failed to get ADC1 interface\n"); @@ -190,7 +190,7 @@ int stm32_adc_setup(void) devname[8]++; #endif -#ifdef CONFIG_STM32H7_ADC2 +#ifdef CONFIG_STM32_ADC2 /* Configure the pins as analog inputs for the selected channels */ for (i = 0; i < ADC2_NCHANNELS; i++) @@ -203,7 +203,7 @@ int stm32_adc_setup(void) /* Call stm32_adcinitialize() to get an instance of the ADC interface */ - adc = stm32h7_adc_initialize(2, g_adc2_chanlist, ADC2_NCHANNELS); + adc = stm32_adc_initialize(2, g_adc2_chanlist, ADC2_NCHANNELS); if (adc == NULL) { aerr("ERROR: Failed to get ADC2 interface\n"); @@ -222,7 +222,7 @@ int stm32_adc_setup(void) devname[8]++; #endif -#if defined(CONFIG_STM32H7_ADC3) +#if defined(CONFIG_STM32_ADC3) /* Configure the pins as analog inputs for the selected channels */ for (i = 0; i < ADC3_NCHANNELS; i++) @@ -235,7 +235,7 @@ int stm32_adc_setup(void) /* Call stm32_adcinitialize() to get an instance of the ADC interface */ - adc = stm32h7_adc_initialize(3, g_adc3_chanlist, ADC3_NCHANNELS); + adc = stm32_adc_initialize(3, g_adc3_chanlist, ADC3_NCHANNELS); if (adc == NULL) { aerr("ERROR: Failed to get ADC3 interface\n"); @@ -252,8 +252,8 @@ int stm32_adc_setup(void) } #endif -#if defined(CONFIG_STM32H7_ADC1) || defined(CONFIG_STM32H7_ADC2) || \ - defined(CONFIG_STM32H7_ADC3) +#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) || \ + defined(CONFIG_STM32_ADC3) /* Now we are initialized */ initialized = true; @@ -265,5 +265,5 @@ int stm32_adc_setup(void) #endif } -#endif /* CONFIG_STM32H7_ADC1 || CONFIG_STM32H7_ADC2 || CONFIG_STM32H7_ADC3 */ +#endif /* CONFIG_STM32_ADC1 || CONFIG_STM32_ADC2 || CONFIG_STM32_ADC3 */ #endif /* CONFIG_ADC */ diff --git a/boards/arm/stm32h7/nucleo-h723zg/src/stm32_boot.c b/boards/arm/stm32h7/nucleo-h723zg/src/stm32_boot.c index 4b07cc7033582..ffddcc7d01a61 100644 --- a/boards/arm/stm32h7/nucleo-h723zg/src/stm32_boot.c +++ b/boards/arm/stm32h7/nucleo-h723zg/src/stm32_boot.c @@ -58,13 +58,13 @@ void stm32_boardinitialize(void) board_autoled_initialize(); #endif -#if defined(CONFIG_STM32H7_OTGFS) || defined(CONFIG_STM32H7_HOST) +#if defined(CONFIG_STM32_OTGFS) || defined(CONFIG_STM32_HOST) /* Initialize USB */ stm32_usbinitialize(); #endif -#ifdef CONFIG_STM32H7_SPI +#ifdef CONFIG_STM32_SPI /* Configure SPI chip selects */ stm32_spidev_initialize(); diff --git a/boards/arm/stm32h7/nucleo-h723zg/src/stm32_bringup.c b/boards/arm/stm32h7/nucleo-h723zg/src/stm32_bringup.c index 445db3e67578d..43d7a676c91f1 100644 --- a/boards/arm/stm32h7/nucleo-h723zg/src/stm32_bringup.c +++ b/boards/arm/stm32h7/nucleo-h723zg/src/stm32_bringup.c @@ -97,16 +97,16 @@ static void stm32_i2c_register(int bus) #if defined(CONFIG_I2C) && defined(CONFIG_SYSTEM_I2CTOOL) static void stm32_i2ctool(void) { -#ifdef CONFIG_STM32H7_I2C1 +#ifdef CONFIG_STM32_I2C1 stm32_i2c_register(1); #endif -#ifdef CONFIG_STM32H7_I2C2 +#ifdef CONFIG_STM32_I2C2 stm32_i2c_register(2); #endif -#ifdef CONFIG_STM32H7_I2C3 +#ifdef CONFIG_STM32_I2C3 stm32_i2c_register(3); #endif -#ifdef CONFIG_STM32H7_I2C4 +#ifdef CONFIG_STM32_I2C4 stm32_i2c_register(4); #endif } diff --git a/boards/arm/stm32h7/nucleo-h723zg/src/stm32_pwm.c b/boards/arm/stm32h7/nucleo-h723zg/src/stm32_pwm.c index 8df03e001094c..f8b200de7681c 100644 --- a/boards/arm/stm32h7/nucleo-h723zg/src/stm32_pwm.c +++ b/boards/arm/stm32h7/nucleo-h723zg/src/stm32_pwm.c @@ -49,11 +49,11 @@ # undef HAVE_PWM #endif -#ifndef CONFIG_STM32H7_TIM1 +#ifndef CONFIG_STM32_TIM1 # undef HAVE_PWM #endif -#ifndef CONFIG_STM32H7_TIM1_PWM +#ifndef CONFIG_STM32_TIM1_PWM # undef HAVE_PWM #endif diff --git a/boards/arm/stm32h7/nucleo-h723zg/src/stm32_reset.c b/boards/arm/stm32h7/nucleo-h723zg/src/stm32_reset.c deleted file mode 100644 index 63b6ff97c8639..0000000000000 --- a/boards/arm/stm32h7/nucleo-h723zg/src/stm32_reset.c +++ /dev/null @@ -1,64 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32h7/nucleo-h723zg/src/stm32_reset.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#ifdef CONFIG_BOARDCTL_RESET - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_reset - * - * Description: - * Reset board. Support for this function is required by board-level - * logic if CONFIG_BOARDCTL_RESET is selected. - * - * Input Parameters: - * status - Status information provided with the reset event. This - * meaning of this status information is board-specific. If not - * used by a board, the value zero may be provided in calls to - * board_reset(). - * - * Returned Value: - * If this function returns, then it was not possible to power-off the - * board due to some constraints. The return value int this case is a - * board-specific reason for the failure to shutdown. - * - ****************************************************************************/ - -int board_reset(int status) -{ - up_systemreset(); - return 0; -} - -#endif /* CONFIG_BOARDCTL_RESET */ diff --git a/boards/arm/stm32h7/nucleo-h723zg/src/stm32_spi.c b/boards/arm/stm32h7/nucleo-h723zg/src/stm32_spi.c index 23d61b098aa0e..0570f528631fe 100644 --- a/boards/arm/stm32h7/nucleo-h723zg/src/stm32_spi.c +++ b/boards/arm/stm32h7/nucleo-h723zg/src/stm32_spi.c @@ -41,7 +41,7 @@ #include "nucleo-h723zg.h" #include -#ifdef CONFIG_STM32H7_SPI +#ifdef CONFIG_STM32_SPI /**************************************************************************** * Public Functions @@ -63,7 +63,7 @@ void stm32_spidev_initialize(void) * architecture. */ -#ifdef CONFIG_STM32H7_SPI3 +#ifdef CONFIG_STM32_SPI3 spiinfo("Configure GPIO for SPI3/CS\n"); # ifdef CONFIG_NET_OA_TC6 @@ -101,7 +101,7 @@ void stm32_spidev_initialize(void) * ****************************************************************************/ -#ifdef CONFIG_STM32H7_SPI1 +#ifdef CONFIG_STM32_SPI1 void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -115,7 +115,7 @@ uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32H7_SPI2 +#ifdef CONFIG_STM32_SPI2 void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -129,7 +129,7 @@ uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32H7_SPI3 +#ifdef CONFIG_STM32_SPI3 void stm32_spi3select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -159,7 +159,7 @@ uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32H7_SPI4 +#ifdef CONFIG_STM32_SPI4 void stm32_spi4select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -173,7 +173,7 @@ uint8_t stm32_spi4status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32H7_SPI5 +#ifdef CONFIG_STM32_SPI5 void stm32_spi5select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -187,7 +187,7 @@ uint8_t stm32_spi5status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32H7_SPI6 +#ifdef CONFIG_STM32_SPI6 void stm32_spi6select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -225,42 +225,42 @@ uint8_t stm32_spi6status(struct spi_dev_s *dev, uint32_t devid) ****************************************************************************/ #ifdef CONFIG_SPI_CMDDATA -#ifdef CONFIG_STM32H7_SPI1 +#ifdef CONFIG_STM32_SPI1 int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32H7_SPI2 +#ifdef CONFIG_STM32_SPI2 int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32H7_SPI3 +#ifdef CONFIG_STM32_SPI3 int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32H7_SPI4 +#ifdef CONFIG_STM32_SPI4 int stm32_spi4cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32H7_SPI5 +#ifdef CONFIG_STM32_SPI5 int stm32_spi5cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32H7_SPI6 +#ifdef CONFIG_STM32_SPI6 int stm32_spi5cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; @@ -268,4 +268,4 @@ int stm32_spi5cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) #endif #endif /* CONFIG_SPI_CMDDATA */ -#endif /* CONFIG_STM32H7_SPI */ +#endif /* CONFIG_STM32_SPI */ diff --git a/boards/arm/stm32h7/nucleo-h723zg/src/stm32_usb.c b/boards/arm/stm32h7/nucleo-h723zg/src/stm32_usb.c index 2216484a5086f..953b452e86f95 100644 --- a/boards/arm/stm32h7/nucleo-h723zg/src/stm32_usb.c +++ b/boards/arm/stm32h7/nucleo-h723zg/src/stm32_usb.c @@ -78,7 +78,7 @@ void stm32_usbinitialize(void) * Power On, and Overcurrent GPIOs */ -#ifdef CONFIG_STM32H7_OTGHS +#ifdef CONFIG_STM32_OTGHS stm32_configgpio(GPIO_OTGHS_VBUS); stm32_configgpio(GPIO_OTGHS_PWRON); stm32_configgpio(GPIO_OTGHS_OVER); diff --git a/boards/arm/stm32h7/nucleo-h743zi/configs/capture/defconfig b/boards/arm/stm32h7/nucleo-h743zi/configs/capture/defconfig index 3596119057564..2ffafc58713c2 100644 --- a/boards/arm/stm32h7/nucleo-h743zi/configs/capture/defconfig +++ b/boards/arm/stm32h7/nucleo-h743zi/configs/capture/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH_BOARD="nucleo-h743zi" CONFIG_ARCH_BOARD_NUCLEO_H743ZI=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H743ZI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -43,9 +44,9 @@ CONFIG_SPI=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_TIM4=y -CONFIG_STM32H7_TIM4_CAP=y -CONFIG_STM32H7_USART3=y +CONFIG_STM32_TIM4=y +CONFIG_STM32_TIM4_CAP=y +CONFIG_STM32_USART3=y CONFIG_SYSTEM_NSH=y CONFIG_TIMER=y CONFIG_USART3_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32h7/nucleo-h743zi/configs/composite/defconfig b/boards/arm/stm32h7/nucleo-h743zi/configs/composite/defconfig index 81c3cdcdab630..b36d0f21e255b 100644 --- a/boards/arm/stm32h7/nucleo-h743zi/configs/composite/defconfig +++ b/boards/arm/stm32h7/nucleo-h743zi/configs/composite/defconfig @@ -11,6 +11,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-h743zi" CONFIG_ARCH_BOARD_NUCLEO_H743ZI=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H743ZI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -75,10 +76,10 @@ CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_HSI48=y -CONFIG_STM32H7_OTGFS=y -CONFIG_STM32H7_SPI3=y -CONFIG_STM32H7_USART3=y +CONFIG_STM32_HSI48=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_SPI3=y +CONFIG_STM32_USART3=y CONFIG_SYSTEM_COMPOSITE=y CONFIG_SYSTEM_NSH=y CONFIG_SYSTEM_USBMSC=y diff --git a/boards/arm/stm32h7/nucleo-h743zi/configs/elf/defconfig b/boards/arm/stm32h7/nucleo-h743zi/configs/elf/defconfig index 2fa4212858e45..f21cc7d12f1b9 100644 --- a/boards/arm/stm32h7/nucleo-h743zi/configs/elf/defconfig +++ b/boards/arm/stm32h7/nucleo-h743zi/configs/elf/defconfig @@ -8,11 +8,13 @@ # CONFIG_NSH_DISABLE_IFCONFIG is not set # CONFIG_NSH_DISABLE_PS is not set # CONFIG_STANDARD_SERIAL is not set -# CONFIG_STM32H7_DTCMEXCLUDE is not set +# CONFIG_STM32_DTCMEXCLUDE is not set CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-h743zi" +CONFIG_ARCH_BOARD_COMMON=y CONFIG_ARCH_BOARD_NUCLEO_H743ZI=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H743ZI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -54,9 +56,9 @@ CONFIG_SPI=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_USART3=y CONFIG_STM32_ROMFS=y CONFIG_STM32_ROMFS_IMAGEFILE="../../apps/examples/elf/main/elf_romfs.img" +CONFIG_STM32_USART3=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_TLS_NELEM=4 diff --git a/boards/arm/stm32h7/nucleo-h743zi/configs/mcuboot-app/defconfig b/boards/arm/stm32h7/nucleo-h743zi/configs/mcuboot-app/defconfig index 6966a2baf2025..dd7faf05d87b3 100644 --- a/boards/arm/stm32h7/nucleo-h743zi/configs/mcuboot-app/defconfig +++ b/boards/arm/stm32h7/nucleo-h743zi/configs/mcuboot-app/defconfig @@ -8,8 +8,10 @@ # CONFIG_STANDARD_SERIAL is not set CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-h743zi" +CONFIG_ARCH_BOARD_COMMON=y CONFIG_ARCH_BOARD_NUCLEO_H743ZI=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H743ZI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -73,18 +75,18 @@ CONFIG_SPI=y CONFIG_START_DAY=28 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2021 -CONFIG_STM32H7_ETHMAC=y -CONFIG_STM32H7_FLASH_OVERRIDE_I=y -CONFIG_STM32H7_PHYSR=31 -CONFIG_STM32H7_PHYSR_100FD=0x0018 -CONFIG_STM32H7_PHYSR_100HD=0x0008 -CONFIG_STM32H7_PHYSR_10FD=0x0014 -CONFIG_STM32H7_PHYSR_10HD=0x0004 -CONFIG_STM32H7_PHYSR_ALTCONFIG=y -CONFIG_STM32H7_PHYSR_ALTMODE=0x001c -CONFIG_STM32H7_USART3=y CONFIG_STM32_APP_FORMAT_MCUBOOT=y +CONFIG_STM32_ETHMAC=y +CONFIG_STM32_FLASH_OVERRIDE_I=y +CONFIG_STM32_PHYSR=31 +CONFIG_STM32_PHYSR_100FD=0x0018 +CONFIG_STM32_PHYSR_100HD=0x0008 +CONFIG_STM32_PHYSR_10FD=0x0014 +CONFIG_STM32_PHYSR_10HD=0x0004 +CONFIG_STM32_PHYSR_ALTCONFIG=y +CONFIG_STM32_PHYSR_ALTMODE=0x001c CONFIG_STM32_PROGMEM_OTA_PARTITION=y +CONFIG_STM32_USART3=y CONFIG_SYSTEM_DHCPC_RENEW=y CONFIG_SYSTEM_NSH=y CONFIG_SYSTEM_PING=y diff --git a/boards/arm/stm32h7/nucleo-h743zi/configs/mcuboot-loader/defconfig b/boards/arm/stm32h7/nucleo-h743zi/configs/mcuboot-loader/defconfig index 73d680b2e78cd..42e24eaed4c3c 100644 --- a/boards/arm/stm32h7/nucleo-h743zi/configs/mcuboot-loader/defconfig +++ b/boards/arm/stm32h7/nucleo-h743zi/configs/mcuboot-loader/defconfig @@ -7,8 +7,10 @@ # CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-h743zi" +CONFIG_ARCH_BOARD_COMMON=y CONFIG_ARCH_BOARD_NUCLEO_H743ZI=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H743ZI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -55,10 +57,10 @@ CONFIG_SPI=y CONFIG_START_DAY=28 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2021 -CONFIG_STM32H7_FLASH_OVERRIDE_I=y -CONFIG_STM32H7_USART3=y CONFIG_STM32_APP_FORMAT_MCUBOOT=y +CONFIG_STM32_FLASH_OVERRIDE_I=y CONFIG_STM32_PROGMEM_OTA_PARTITION=y +CONFIG_STM32_USART3=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART3_SERIAL_CONSOLE=y CONFIG_WQUEUE_NOTIFIER=y diff --git a/boards/arm/stm32h7/nucleo-h743zi/configs/netnsh/defconfig b/boards/arm/stm32h7/nucleo-h743zi/configs/netnsh/defconfig index 67f590adaf0aa..ec57eb558ba55 100644 --- a/boards/arm/stm32h7/nucleo-h743zi/configs/netnsh/defconfig +++ b/boards/arm/stm32h7/nucleo-h743zi/configs/netnsh/defconfig @@ -10,6 +10,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-h743zi" CONFIG_ARCH_BOARD_NUCLEO_H743ZI=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H743ZI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -65,17 +66,17 @@ CONFIG_SPI=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_ETHMAC=y -CONFIG_STM32H7_HSI48=y -CONFIG_STM32H7_OTGFS=y -CONFIG_STM32H7_PHYSR=31 -CONFIG_STM32H7_PHYSR_100FD=0x0018 -CONFIG_STM32H7_PHYSR_100HD=0x0008 -CONFIG_STM32H7_PHYSR_10FD=0x0014 -CONFIG_STM32H7_PHYSR_10HD=0x0004 -CONFIG_STM32H7_PHYSR_ALTCONFIG=y -CONFIG_STM32H7_PHYSR_ALTMODE=0x001c -CONFIG_STM32H7_USART3=y +CONFIG_STM32_ETHMAC=y +CONFIG_STM32_HSI48=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PHYSR=31 +CONFIG_STM32_PHYSR_100FD=0x0018 +CONFIG_STM32_PHYSR_100HD=0x0008 +CONFIG_STM32_PHYSR_10FD=0x0014 +CONFIG_STM32_PHYSR_10HD=0x0004 +CONFIG_STM32_PHYSR_ALTCONFIG=y +CONFIG_STM32_PHYSR_ALTMODE=0x001c +CONFIG_STM32_USART3=y CONFIG_SYSTEM_DHCPC_RENEW=y CONFIG_SYSTEM_NSH=y CONFIG_SYSTEM_PING=y diff --git a/boards/arm/stm32h7/nucleo-h743zi/configs/nsh/defconfig b/boards/arm/stm32h7/nucleo-h743zi/configs/nsh/defconfig index 7fe65a420a164..788de2f32ef0c 100644 --- a/boards/arm/stm32h7/nucleo-h743zi/configs/nsh/defconfig +++ b/boards/arm/stm32h7/nucleo-h743zi/configs/nsh/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-h743zi" CONFIG_ARCH_BOARD_NUCLEO_H743ZI=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H743ZI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -43,7 +44,7 @@ CONFIG_SPI=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_USART3=y +CONFIG_STM32_USART3=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART3_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32h7/nucleo-h743zi/configs/nxboot-app/defconfig b/boards/arm/stm32h7/nucleo-h743zi/configs/nxboot-app/defconfig index 7afab9a891584..ce2e87133e261 100644 --- a/boards/arm/stm32h7/nucleo-h743zi/configs/nxboot-app/defconfig +++ b/boards/arm/stm32h7/nucleo-h743zi/configs/nxboot-app/defconfig @@ -8,8 +8,10 @@ # CONFIG_STANDARD_SERIAL is not set CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-h743zi" +CONFIG_ARCH_BOARD_COMMON=y CONFIG_ARCH_BOARD_NUCLEO_H743ZI=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H743ZI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -54,10 +56,10 @@ CONFIG_SPI=y CONFIG_START_DAY=28 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2021 -CONFIG_STM32H7_FLASH_OVERRIDE_I=y -CONFIG_STM32H7_USART3=y CONFIG_STM32_APP_FORMAT_NXBOOT=y +CONFIG_STM32_FLASH_OVERRIDE_I=y CONFIG_STM32_PROGMEM_OTA_PARTITION=y +CONFIG_STM32_USART3=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART3_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32h7/nucleo-h743zi/configs/nxboot-loader/defconfig b/boards/arm/stm32h7/nucleo-h743zi/configs/nxboot-loader/defconfig index 108860120e5ea..ec79fa1b09cfc 100644 --- a/boards/arm/stm32h7/nucleo-h743zi/configs/nxboot-loader/defconfig +++ b/boards/arm/stm32h7/nucleo-h743zi/configs/nxboot-loader/defconfig @@ -7,8 +7,10 @@ # CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-h743zi" +CONFIG_ARCH_BOARD_COMMON=y CONFIG_ARCH_BOARD_NUCLEO_H743ZI=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H743ZI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -56,10 +58,10 @@ CONFIG_SPI=y CONFIG_START_DAY=28 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2021 -CONFIG_STM32H7_FLASH_OVERRIDE_I=y -CONFIG_STM32H7_USART3=y CONFIG_STM32_APP_FORMAT_NXBOOT=y +CONFIG_STM32_FLASH_OVERRIDE_I=y CONFIG_STM32_PROGMEM_OTA_PARTITION=y +CONFIG_STM32_USART3=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART3_SERIAL_CONSOLE=y CONFIG_WQUEUE_NOTIFIER=y diff --git a/boards/arm/stm32h7/nucleo-h743zi/configs/nxlines_oled/defconfig b/boards/arm/stm32h7/nucleo-h743zi/configs/nxlines_oled/defconfig index 8f193c58d45ab..86c0aa28e5dab 100644 --- a/boards/arm/stm32h7/nucleo-h743zi/configs/nxlines_oled/defconfig +++ b/boards/arm/stm32h7/nucleo-h743zi/configs/nxlines_oled/defconfig @@ -15,6 +15,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-h743zi" CONFIG_ARCH_BOARD_NUCLEO_H743ZI=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H743ZI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -59,8 +60,8 @@ CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_I2C2=y -CONFIG_STM32H7_USART3=y +CONFIG_STM32_I2C2=y +CONFIG_STM32_USART3=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART3_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32h7/nucleo-h743zi/configs/otg_fs_host/defconfig b/boards/arm/stm32h7/nucleo-h743zi/configs/otg_fs_host/defconfig index 258614328286d..5977b0463baea 100644 --- a/boards/arm/stm32h7/nucleo-h743zi/configs/otg_fs_host/defconfig +++ b/boards/arm/stm32h7/nucleo-h743zi/configs/otg_fs_host/defconfig @@ -10,6 +10,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-h743zi" CONFIG_ARCH_BOARD_NUCLEO_H743ZI=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H743ZI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -48,9 +49,9 @@ CONFIG_SPI=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_HSI48=y -CONFIG_STM32H7_OTGFS=y -CONFIG_STM32H7_USART3=y +CONFIG_STM32_HSI48=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_USART3=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART3_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32h7/nucleo-h743zi/configs/pwm/defconfig b/boards/arm/stm32h7/nucleo-h743zi/configs/pwm/defconfig index 36c6b375d46e0..e43edd2ca1ddd 100644 --- a/boards/arm/stm32h7/nucleo-h743zi/configs/pwm/defconfig +++ b/boards/arm/stm32h7/nucleo-h743zi/configs/pwm/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-h743zi" CONFIG_ARCH_BOARD_NUCLEO_H743ZI=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H743ZI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -45,21 +46,21 @@ CONFIG_SPI=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_PWM_MULTICHAN=y -CONFIG_STM32H7_TIM1=y -CONFIG_STM32H7_TIM1_CH1NOUT=y -CONFIG_STM32H7_TIM1_CH1OUT=y -CONFIG_STM32H7_TIM1_CH2NOUT=y -CONFIG_STM32H7_TIM1_CH2OUT=y -CONFIG_STM32H7_TIM1_CH3NOUT=y -CONFIG_STM32H7_TIM1_CH3OUT=y -CONFIG_STM32H7_TIM1_CH4OUT=y -CONFIG_STM32H7_TIM1_CHANNEL1=y -CONFIG_STM32H7_TIM1_CHANNEL2=y -CONFIG_STM32H7_TIM1_CHANNEL3=y -CONFIG_STM32H7_TIM1_CHANNEL4=y -CONFIG_STM32H7_TIM1_PWM=y -CONFIG_STM32H7_USART3=y +CONFIG_STM32_PWM_MULTICHAN=y +CONFIG_STM32_TIM1=y +CONFIG_STM32_TIM1_CH1NOUT=y +CONFIG_STM32_TIM1_CH1OUT=y +CONFIG_STM32_TIM1_CH2NOUT=y +CONFIG_STM32_TIM1_CH2OUT=y +CONFIG_STM32_TIM1_CH3NOUT=y +CONFIG_STM32_TIM1_CH3OUT=y +CONFIG_STM32_TIM1_CH4OUT=y +CONFIG_STM32_TIM1_CHANNEL1=y +CONFIG_STM32_TIM1_CHANNEL2=y +CONFIG_STM32_TIM1_CHANNEL3=y +CONFIG_STM32_TIM1_CHANNEL4=y +CONFIG_STM32_TIM1_PWM=y +CONFIG_STM32_USART3=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART3_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32h7/nucleo-h743zi/configs/rndis/defconfig b/boards/arm/stm32h7/nucleo-h743zi/configs/rndis/defconfig index 9060c7e249b52..914de95443f0f 100644 --- a/boards/arm/stm32h7/nucleo-h743zi/configs/rndis/defconfig +++ b/boards/arm/stm32h7/nucleo-h743zi/configs/rndis/defconfig @@ -10,6 +10,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-h743zi" CONFIG_ARCH_BOARD_NUCLEO_H743ZI=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H743ZI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -69,9 +70,9 @@ CONFIG_SPI=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_HSI48=y -CONFIG_STM32H7_OTGFS=y -CONFIG_STM32H7_USART3=y +CONFIG_STM32_HSI48=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_USART3=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART3_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32h7/nucleo-h743zi/include/board.h b/boards/arm/stm32h7/nucleo-h743zi/include/board.h index f3417aef1553e..744ddeede6069 100644 --- a/boards/arm/stm32h7/nucleo-h743zi/include/board.h +++ b/boards/arm/stm32h7/nucleo-h743zi/include/board.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32H7_NUCLEO_H743ZI_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32H7_NUCLEO_H743ZI_INCLUDE_BOARD_H +#ifndef __BOARDS_ARM_STM32_NUCLEO_H743ZI_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32_NUCLEO_H743ZI_INCLUDE_BOARD_H /**************************************************************************** * Included Files @@ -515,4 +515,4 @@ extern "C" #endif #endif /* __ASSEMBLY__ */ -#endif /* __BOARDS_ARM_STM32H7_NUCLEO_H743ZI_INCLUDE_BOARD_H */ +#endif /* __BOARDS_ARM_STM32_NUCLEO_H743ZI_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32h7/nucleo-h743zi/src/CMakeLists.txt b/boards/arm/stm32h7/nucleo-h743zi/src/CMakeLists.txt index d4e92b8f5ed14..6fed42e117649 100644 --- a/boards/arm/stm32h7/nucleo-h743zi/src/CMakeLists.txt +++ b/boards/arm/stm32h7/nucleo-h743zi/src/CMakeLists.txt @@ -36,15 +36,11 @@ if(CONFIG_ARCH_BUTTONS) list(APPEND SRCS stm32_buttons.c) endif() -if(CONFIG_STM32_ROMFS) - list(APPEND SRCS stm32_romfs_initialize.c) -endif() - -if(CONFIG_STM32H7_SPI) +if(CONFIG_STM32_SPI) list(APPEND SRCS stm32_spi.c) endif() -if(CONFIG_STM32H7_OTGFS) +if(CONFIG_STM32_OTGFS) list(APPEND SRCS stm32_usb.c) endif() @@ -72,7 +68,7 @@ if(CONFIG_LCD_SSD1306) list(APPEND SRCS stm32_ssd1306.c) endif() -if(CONFIG_STM32H7_PROGMEM) +if(CONFIG_STM32_PROGMEM) list(APPEND SRCS stm32_progmem.c) endif() @@ -88,10 +84,6 @@ if(CONFIG_PWM) list(APPEND SRCS stm32_pwm.c) endif() -if(CONFIG_BOARDCTL_RESET) - list(APPEND SRCS stm32_reset.c) -endif() - if(CONFIG_BOARDCTL_BOOT_IMAGE) list(APPEND SRCS stm32_boot_image.c) endif() diff --git a/boards/arm/stm32h7/nucleo-h743zi/src/Make.defs b/boards/arm/stm32h7/nucleo-h743zi/src/Make.defs new file mode 100644 index 0000000000000..b1afe513ef8f6 --- /dev/null +++ b/boards/arm/stm32h7/nucleo-h743zi/src/Make.defs @@ -0,0 +1,107 @@ +############################################################################ +# boards/arm/stm32h7/nucleo-h743zi/src/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +CSRCS = stm32_boot.c stm32_bringup.c + +ifeq ($(CONFIG_ADC),y) +CSRCS += stm32_adc.c +endif + +ifeq ($(CONFIG_ARCH_LEDS),y) +CSRCS += stm32_autoleds.c +else +CSRCS += stm32_userleds.c +endif + +ifeq ($(CONFIG_ARCH_BUTTONS),y) +CSRCS += stm32_buttons.c +endif + +ifeq ($(CONFIG_STM32_SPI),y) +CSRCS += stm32_spi.c +endif + +ifeq ($(CONFIG_STM32_OTGFS),y) +CSRCS += stm32_usb.c +endif + +ifeq ($(CONFIG_BOARDCTL_UNIQUEID),y) +CSRCS += stm32_uid.c +endif + +ifeq ($(CONFIG_SENSORS_LSM6DSL),y) +CSRCS += stm32_lsm6dsl.c +endif + +ifeq ($(CONFIG_SENSORS_LSM9DS1),y) +CSRCS += stm32_lsm9ds1.c +endif + +ifeq ($(CONFIG_SENSORS_LSM303AGR),y) +CSRCS += stm32_lsm303agr.c +endif + +ifeq ($(CONFIG_PCA9635PW),y) +CSRCS += stm32_pca9635.c +endif + +ifeq ($(CONFIG_LCD_SSD1306),y) +CSRCS += stm32_ssd1306.c +endif + +ifeq ($(CONFIG_STM32_PROGMEM),y) +CSRCS += stm32_progmem.c +endif + +ifeq ($(CONFIG_WL_NRF24L01),y) +CSRCS += stm32_nrf24l01.c +endif + +ifeq ($(CONFIG_DEV_GPIO),y) +CSRCS += stm32_gpio.c +endif + +ifeq ($(CONFIG_PWM),y) +CSRCS += stm32_pwm.c +endif + +ifeq ($(CONFIG_BOARDCTL_BOOT_IMAGE),y) +CSRCS += stm32_boot_image.c +endif + +ifeq ($(CONFIG_USBMSC),y) +CSRCS += stm32_usbmsc.c +endif + +ifeq ($(CONFIG_USBDEV_COMPOSITE),y) +CSRCS += stm32_composite.c +endif + +ifeq ($(CONFIG_MMCSD),y) +CSRCS += stm32_mmcsd.c +endif + +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32h7/nucleo-h743zi/src/Makefile b/boards/arm/stm32h7/nucleo-h743zi/src/Makefile deleted file mode 100644 index 985900a61a9d7..0000000000000 --- a/boards/arm/stm32h7/nucleo-h743zi/src/Makefile +++ /dev/null @@ -1,113 +0,0 @@ -############################################################################ -# boards/arm/stm32h7/nucleo-h743zi/src/Makefile -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/Make.defs - -CSRCS = stm32_boot.c stm32_bringup.c - -ifeq ($(CONFIG_ADC),y) -CSRCS += stm32_adc.c -endif - -ifeq ($(CONFIG_ARCH_LEDS),y) -CSRCS += stm32_autoleds.c -else -CSRCS += stm32_userleds.c -endif - -ifeq ($(CONFIG_ARCH_BUTTONS),y) -CSRCS += stm32_buttons.c -endif - -ifeq ($(CONFIG_STM32_ROMFS),y) -CSRCS += stm32_romfs_initialize.c -endif - -ifeq ($(CONFIG_STM32H7_SPI),y) -CSRCS += stm32_spi.c -endif - -ifeq ($(CONFIG_STM32H7_OTGFS),y) -CSRCS += stm32_usb.c -endif - -ifeq ($(CONFIG_BOARDCTL_UNIQUEID),y) -CSRCS += stm32_uid.c -endif - -ifeq ($(CONFIG_SENSORS_LSM6DSL),y) -CSRCS += stm32_lsm6dsl.c -endif - -ifeq ($(CONFIG_SENSORS_LSM9DS1),y) -CSRCS += stm32_lsm9ds1.c -endif - -ifeq ($(CONFIG_SENSORS_LSM303AGR),y) -CSRCS += stm32_lsm303agr.c -endif - -ifeq ($(CONFIG_PCA9635PW),y) -CSRCS += stm32_pca9635.c -endif - -ifeq ($(CONFIG_LCD_SSD1306),y) -CSRCS += stm32_ssd1306.c -endif - -ifeq ($(CONFIG_STM32H7_PROGMEM),y) -CSRCS += stm32_progmem.c -endif - -ifeq ($(CONFIG_WL_NRF24L01),y) -CSRCS += stm32_nrf24l01.c -endif - -ifeq ($(CONFIG_DEV_GPIO),y) -CSRCS += stm32_gpio.c -endif - -ifeq ($(CONFIG_PWM),y) -CSRCS += stm32_pwm.c -endif - -ifeq ($(CONFIG_BOARDCTL_RESET),y) -CSRCS += stm32_reset.c -endif - -ifeq ($(CONFIG_BOARDCTL_BOOT_IMAGE),y) -CSRCS += stm32_boot_image.c -endif - -ifeq ($(CONFIG_USBMSC),y) -CSRCS += stm32_usbmsc.c -endif - -ifeq ($(CONFIG_USBDEV_COMPOSITE),y) -CSRCS += stm32_composite.c -endif - -ifeq ($(CONFIG_MMCSD),y) -CSRCS += stm32_mmcsd.c -endif - -include $(TOPDIR)/boards/Board.mk diff --git a/boards/arm/stm32h7/nucleo-h743zi/src/nucleo-h743zi.h b/boards/arm/stm32h7/nucleo-h743zi/src/nucleo-h743zi.h index 4bcfe00d50ba4..9ecd89b25790f 100644 --- a/boards/arm/stm32h7/nucleo-h743zi/src/nucleo-h743zi.h +++ b/boards/arm/stm32h7/nucleo-h743zi/src/nucleo-h743zi.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32H7_NUCLEO_H743ZI_SRC_NUCLEO_H743ZI_H -#define __BOARDS_ARM_STM32H7_NUCLEO_H743ZI_SRC_NUCLEO_H743ZI_H +#ifndef __BOARDS_ARM_STM32_NUCLEO_H743ZI_SRC_NUCLEO_H743ZI_H +#define __BOARDS_ARM_STM32_NUCLEO_H743ZI_SRC_NUCLEO_H743ZI_H /**************************************************************************** * Included Files @@ -47,7 +47,7 @@ /* Can't support USB host or device features if USB OTG FS is not enabled */ -#ifndef CONFIG_STM32H7_OTGFS +#ifndef CONFIG_STM32_OTGFS # undef HAVE_USBDEV # undef HAVE_USBHOST #endif @@ -82,7 +82,7 @@ # undef HAVE_USBMONITOR #endif -#if !defined(CONFIG_STM32H7_PROGMEM) || !defined(CONFIG_MTD_PROGMEM) +#if !defined(CONFIG_STM32_PROGMEM) || !defined(CONFIG_MTD_PROGMEM) # undef HAVE_PROGMEM_CHARDEV #endif @@ -251,7 +251,7 @@ int stm32_bringup(void); * ****************************************************************************/ -#ifdef CONFIG_STM32H7_SPI +#ifdef CONFIG_STM32_SPI void stm32_spidev_initialize(void); #endif @@ -288,7 +288,7 @@ int stm32_gpio_initialize(void); * ****************************************************************************/ -#ifdef CONFIG_STM32H7_OTGFS +#ifdef CONFIG_STM32_OTGFS void weak_function stm32_usbinitialize(void); #endif @@ -302,7 +302,7 @@ void weak_function stm32_usbinitialize(void); * ****************************************************************************/ -#if defined(CONFIG_STM32H7_OTGFS) && defined(CONFIG_USBHOST) +#if defined(CONFIG_STM32_OTGFS) && defined(CONFIG_USBHOST) int stm32_usbhost_initialize(void); #endif @@ -401,4 +401,4 @@ int stm32_progmem_init(void); int stm32_mmcsd_initialize(int minor); #endif -#endif /* __BOARDS_ARM_STM32H7_NUCLEO_H743ZI_SRC_NUCLEO_H743ZI_H */ +#endif /* __BOARDS_ARM_STM32_NUCLEO_H743ZI_SRC_NUCLEO_H743ZI_H */ diff --git a/boards/arm/stm32h7/nucleo-h743zi/src/stm32_adc.c b/boards/arm/stm32h7/nucleo-h743zi/src/stm32_adc.c index 46744e439defb..1b0a972921a9e 100644 --- a/boards/arm/stm32h7/nucleo-h743zi/src/stm32_adc.c +++ b/boards/arm/stm32h7/nucleo-h743zi/src/stm32_adc.c @@ -48,8 +48,8 @@ /* Up to 3 ADC interfaces are supported */ -#if defined(CONFIG_STM32H7_ADC1) || defined(CONFIG_STM32H7_ADC2) || \ - defined(CONFIG_STM32H7_ADC3) +#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) || \ + defined(CONFIG_STM32_ADC3) /* The number of ADC channels in the conversion list */ @@ -61,7 +61,7 @@ * Private Data ****************************************************************************/ -#ifdef CONFIG_STM32H7_ADC1 +#ifdef CONFIG_STM32_ADC1 /* Identifying number of each ADC channel: Variable Resistor. * * ADC1: {5, 10, 15, 18, 19, 7, 12}; @@ -83,12 +83,12 @@ static const uint32_t g_adc1_pinlist[ADC1_NCHANNELS] = GPIO_ADC123_INP12 }; -#endif /* CONFIG_STM32H7_ADC1 */ +#endif /* CONFIG_STM32_ADC1 */ /**************************************************************************** * ADC2 ****************************************************************************/ -#ifdef CONFIG_STM32H7_ADC2 +#ifdef CONFIG_STM32_ADC2 static const uint8_t g_adc2_chanlist[ADC2_NCHANNELS] = { @@ -103,9 +103,9 @@ static const uint32_t g_adc2_pinlist[ADC2_NCHANNELS] = GPIO_ADC12_INP4, GPIO_ADC12_INP8 }; -#endif /* CONFIG_STM32H7_ADC2 */ +#endif /* CONFIG_STM32_ADC2 */ -#ifdef CONFIG_STM32H7_ADC3 +#ifdef CONFIG_STM32_ADC3 /* Identifying number of each ADC channel: Variable Resistor. * * ADC3: {6,}; @@ -146,7 +146,7 @@ static const uint32_t g_adc3_pinlist[ADC3_NCHANNELS] = int stm32_adc_setup(void) { -#if defined(CONFIG_STM32H7_ADC1) || defined(CONFIG_STM32H7_ADC3) +#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC3) static bool initialized = false; struct adc_dev_s *adc; int ret; @@ -158,7 +158,7 @@ int stm32_adc_setup(void) if (!initialized) { #endif -#if defined(CONFIG_STM32H7_ADC1) +#if defined(CONFIG_STM32_ADC1) /* Configure the pins as analog inputs for the selected channels */ for (i = 0; i < ADC1_NCHANNELS; i++) @@ -171,7 +171,7 @@ int stm32_adc_setup(void) /* Call stm32_adcinitialize() to get an instance of the ADC interface */ - adc = stm32h7_adc_initialize(1, g_adc1_chanlist, ADC1_NCHANNELS); + adc = stm32_adc_initialize(1, g_adc1_chanlist, ADC1_NCHANNELS); if (adc == NULL) { aerr("ERROR: Failed to get ADC1 interface\n"); @@ -190,7 +190,7 @@ int stm32_adc_setup(void) devname[8]++; #endif -#ifdef CONFIG_STM32H7_ADC2 +#ifdef CONFIG_STM32_ADC2 /* Configure the pins as analog inputs for the selected channels */ for (i = 0; i < ADC2_NCHANNELS; i++) @@ -203,7 +203,7 @@ int stm32_adc_setup(void) /* Call stm32_adcinitialize() to get an instance of the ADC interface */ - adc = stm32h7_adc_initialize(2, g_adc2_chanlist, ADC2_NCHANNELS); + adc = stm32_adc_initialize(2, g_adc2_chanlist, ADC2_NCHANNELS); if (adc == NULL) { aerr("ERROR: Failed to get ADC2 interface\n"); @@ -222,7 +222,7 @@ int stm32_adc_setup(void) devname[8]++; #endif -#if defined(CONFIG_STM32H7_ADC3) +#if defined(CONFIG_STM32_ADC3) /* Configure the pins as analog inputs for the selected channels */ for (i = 0; i < ADC3_NCHANNELS; i++) @@ -235,7 +235,7 @@ int stm32_adc_setup(void) /* Call stm32_adcinitialize() to get an instance of the ADC interface */ - adc = stm32h7_adc_initialize(3, g_adc3_chanlist, ADC3_NCHANNELS); + adc = stm32_adc_initialize(3, g_adc3_chanlist, ADC3_NCHANNELS); if (adc == NULL) { aerr("ERROR: Failed to get ADC3 interface\n"); @@ -252,8 +252,8 @@ int stm32_adc_setup(void) } #endif -#if defined(CONFIG_STM32H7_ADC1) || defined(CONFIG_STM32H7_ADC2) || \ - defined(CONFIG_STM32H7_ADC3) +#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) || \ + defined(CONFIG_STM32_ADC3) /* Now we are initialized */ initialized = true; @@ -265,5 +265,5 @@ int stm32_adc_setup(void) #endif } -#endif /* CONFIG_STM32H7_ADC1 || CONFIG_STM32H7_ADC2 || CONFIG_STM32H7_ADC3 */ +#endif /* CONFIG_STM32_ADC1 || CONFIG_STM32_ADC2 || CONFIG_STM32_ADC3 */ #endif /* CONFIG_ADC */ diff --git a/boards/arm/stm32h7/nucleo-h743zi/src/stm32_boot.c b/boards/arm/stm32h7/nucleo-h743zi/src/stm32_boot.c index 17cfeed669d98..48da9194419b7 100644 --- a/boards/arm/stm32h7/nucleo-h743zi/src/stm32_boot.c +++ b/boards/arm/stm32h7/nucleo-h743zi/src/stm32_boot.c @@ -58,13 +58,13 @@ void stm32_boardinitialize(void) board_autoled_initialize(); #endif -#if defined(CONFIG_STM32H7_OTGFS) || defined(CONFIG_STM32H7_HOST) +#if defined(CONFIG_STM32_OTGFS) || defined(CONFIG_STM32_HOST) /* Initialize USB */ stm32_usbinitialize(); #endif -#ifdef CONFIG_STM32H7_SPI +#ifdef CONFIG_STM32_SPI /* Configure SPI chip selects */ stm32_spidev_initialize(); diff --git a/boards/arm/stm32h7/nucleo-h743zi/src/stm32_bringup.c b/boards/arm/stm32h7/nucleo-h743zi/src/stm32_bringup.c index a8999a87a404b..ac08dece22d0c 100644 --- a/boards/arm/stm32h7/nucleo-h743zi/src/stm32_bringup.c +++ b/boards/arm/stm32h7/nucleo-h743zi/src/stm32_bringup.c @@ -38,7 +38,7 @@ # include #endif -#ifdef CONFIG_STM32H7_OTGFS +#ifdef CONFIG_STM32_OTGFS # include "stm32_usbhost.h" #endif @@ -62,7 +62,7 @@ # include "stm32_capture.h" #endif -#ifdef CONFIG_STM32H7_IWDG +#ifdef CONFIG_STM32_IWDG # include "stm32_wdg.h" #endif @@ -96,40 +96,40 @@ static int stm32_capture_setup(void) int ret; struct cap_lowerhalf_s *lower[] = { -#if defined(CONFIG_STM32H7_TIM1_CAP) +#if defined(CONFIG_STM32_TIM1_CAP) stm32_cap_initialize(1), #endif -#if defined(CONFIG_STM32H7_TIM2_CAP) +#if defined(CONFIG_STM32_TIM2_CAP) stm32_cap_initialize(2), #endif -#if defined(CONFIG_STM32H7_TIM3_CAP) +#if defined(CONFIG_STM32_TIM3_CAP) stm32_cap_initialize(3), #endif -#if defined(CONFIG_STM32H7_TIM4_CAP) +#if defined(CONFIG_STM32_TIM4_CAP) stm32_cap_initialize(4), #endif -#if defined(CONFIG_STM32H7_TIM5_CAP) +#if defined(CONFIG_STM32_TIM5_CAP) stm32_cap_initialize(5), #endif -#if defined(CONFIG_STM32H7_TIM8_CAP) +#if defined(CONFIG_STM32_TIM8_CAP) stm32_cap_initialize(8), #endif -#if defined(CONFIG_STM32H7_TIM12_CAP) +#if defined(CONFIG_STM32_TIM12_CAP) stm32_cap_initialize(12), #endif -#if defined(CONFIG_STM32H7_TIM13_CAP) +#if defined(CONFIG_STM32_TIM13_CAP) stm32_cap_initialize(13), #endif -#if defined(CONFIG_STM32H7_TIM14_CAP) +#if defined(CONFIG_STM32_TIM14_CAP) stm32_cap_initialize(14), #endif -#if defined(CONFIG_STM32H7_TIM15_CAP) +#if defined(CONFIG_STM32_TIM15_CAP) stm32_cap_initialize(15), #endif -#if defined(CONFIG_STM32H7_TIM16_CAP) +#if defined(CONFIG_STM32_TIM16_CAP) stm32_cap_initialize(16), #endif -#if defined(CONFIG_STM32H7_TIM17_CAP) +#if defined(CONFIG_STM32_TIM17_CAP) stm32_cap_initialize(17), #endif /* TODO: LPTIMy_CAP */ @@ -216,16 +216,16 @@ static void stm32_i2c_register(int bus) #if defined(CONFIG_I2C) && defined(CONFIG_SYSTEM_I2CTOOL) static void stm32_i2ctool(void) { -#ifdef CONFIG_STM32H7_I2C1 +#ifdef CONFIG_STM32_I2C1 stm32_i2c_register(1); #endif -#ifdef CONFIG_STM32H7_I2C2 +#ifdef CONFIG_STM32_I2C2 stm32_i2c_register(2); #endif -#ifdef CONFIG_STM32H7_I2C3 +#ifdef CONFIG_STM32_I2C3 stm32_i2c_register(3); #endif -#ifdef CONFIG_STM32H7_I2C4 +#ifdef CONFIG_STM32_I2C4 stm32_i2c_register(4); #endif } @@ -487,7 +487,7 @@ int stm32_bringup(void) #endif /* HAVE_PROGMEM_CHARDEV */ #endif /* CONFIG_MTD */ -#ifdef CONFIG_STM32H7_IWDG +#ifdef CONFIG_STM32_IWDG /* Initialize the watchdog timer */ stm32_iwdginitialize("/dev/watchdog0", STM32_LSI_FREQUENCY); diff --git a/boards/arm/stm32h7/nucleo-h743zi/src/stm32_lsm303agr.c b/boards/arm/stm32h7/nucleo-h743zi/src/stm32_lsm303agr.c index 6412aca6a93d5..6017b9b69ad3e 100644 --- a/boards/arm/stm32h7/nucleo-h743zi/src/stm32_lsm303agr.c +++ b/boards/arm/stm32h7/nucleo-h743zi/src/stm32_lsm303agr.c @@ -39,8 +39,8 @@ * Pre-processor Definitions ****************************************************************************/ -#ifndef CONFIG_STM32H7_I2C1 -# error "LSM303AGR driver requires CONFIG_STM32H7_I2C1 to be enabled" +#ifndef CONFIG_STM32_I2C1 +# error "LSM303AGR driver requires CONFIG_STM32_I2C1 to be enabled" #endif /**************************************************************************** @@ -62,7 +62,7 @@ int stm32_lsm303agr_initialize(char *devpath) sninfo("INFO: Initializing LMS303AGR sensor over I2C\n"); -#if defined(CONFIG_STM32H7_I2C1) +#if defined(CONFIG_STM32_I2C1) i2c = stm32_i2cbus_initialize(1); if (i2c == NULL) { diff --git a/boards/arm/stm32h7/nucleo-h743zi/src/stm32_lsm6dsl.c b/boards/arm/stm32h7/nucleo-h743zi/src/stm32_lsm6dsl.c index a7037b3c4cc85..0d1e880723802 100644 --- a/boards/arm/stm32h7/nucleo-h743zi/src/stm32_lsm6dsl.c +++ b/boards/arm/stm32h7/nucleo-h743zi/src/stm32_lsm6dsl.c @@ -39,8 +39,8 @@ * Pre-processor Definitions ****************************************************************************/ -#ifndef CONFIG_STM32H7_I2C1 -# error "LSM6DSL driver requires CONFIG_STM32H7_I2C1 to be enabled" +#ifndef CONFIG_STM32_I2C1 +# error "LSM6DSL driver requires CONFIG_STM32_I2C1 to be enabled" #endif /**************************************************************************** @@ -66,7 +66,7 @@ int stm32_lsm6dsl_initialize(char *devpath) stm32_configgpio(GPIO_LPS22HB_INT1); -#if defined(CONFIG_STM32H7_I2C1) +#if defined(CONFIG_STM32_I2C1) i2c = stm32_i2cbus_initialize(1); if (i2c == NULL) { diff --git a/boards/arm/stm32h7/nucleo-h743zi/src/stm32_lsm9ds1.c b/boards/arm/stm32h7/nucleo-h743zi/src/stm32_lsm9ds1.c index 6f5276f12d6e6..bb50400bd619d 100644 --- a/boards/arm/stm32h7/nucleo-h743zi/src/stm32_lsm9ds1.c +++ b/boards/arm/stm32h7/nucleo-h743zi/src/stm32_lsm9ds1.c @@ -39,8 +39,8 @@ * Pre-processor Definitions ****************************************************************************/ -#ifndef CONFIG_STM32H7_I2C1 -# error "LSM9DS1 driver requires CONFIG_STM32H7_I2C1 to be enabled" +#ifndef CONFIG_STM32_I2C1 +# error "LSM9DS1 driver requires CONFIG_STM32_I2C1 to be enabled" #endif #define LSM9DS1MAG_DEVPATH "/dev/lsm9ds1mag0" @@ -66,7 +66,7 @@ int stm32_lsm9ds1_initialize(void) sninfo("Initializing LMS9DS1!\n"); -#if defined(CONFIG_STM32H7_I2C1) +#if defined(CONFIG_STM32_I2C1) i2c = stm32_i2cbus_initialize(LMS9DS1_I2CBUS); if (i2c == NULL) { diff --git a/boards/arm/stm32h7/nucleo-h743zi/src/stm32_mmcsd.c b/boards/arm/stm32h7/nucleo-h743zi/src/stm32_mmcsd.c index 40dbe2fcbf451..7979ef412b81e 100644 --- a/boards/arm/stm32h7/nucleo-h743zi/src/stm32_mmcsd.c +++ b/boards/arm/stm32h7/nucleo-h743zi/src/stm32_mmcsd.c @@ -44,7 +44,7 @@ # error "SD driver requires CONFIG_DISABLE_MOUNTPOINT to be disabled" #endif -#ifndef CONFIG_STM32H7_SPI3 +#ifndef CONFIG_STM32_SPI3 # error "MMC/SD requires SPI3 enabled" #endif diff --git a/boards/arm/stm32h7/nucleo-h743zi/src/stm32_pwm.c b/boards/arm/stm32h7/nucleo-h743zi/src/stm32_pwm.c index 0631fcba68842..fba60268a2f54 100644 --- a/boards/arm/stm32h7/nucleo-h743zi/src/stm32_pwm.c +++ b/boards/arm/stm32h7/nucleo-h743zi/src/stm32_pwm.c @@ -49,11 +49,11 @@ # undef HAVE_PWM #endif -#ifndef CONFIG_STM32H7_TIM1 +#ifndef CONFIG_STM32_TIM1 # undef HAVE_PWM #endif -#ifndef CONFIG_STM32H7_TIM1_PWM +#ifndef CONFIG_STM32_TIM1_PWM # undef HAVE_PWM #endif diff --git a/boards/arm/stm32h7/nucleo-h743zi/src/stm32_reset.c b/boards/arm/stm32h7/nucleo-h743zi/src/stm32_reset.c deleted file mode 100644 index be800712641cb..0000000000000 --- a/boards/arm/stm32h7/nucleo-h743zi/src/stm32_reset.c +++ /dev/null @@ -1,64 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32h7/nucleo-h743zi/src/stm32_reset.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#ifdef CONFIG_BOARDCTL_RESET - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_reset - * - * Description: - * Reset board. Support for this function is required by board-level - * logic if CONFIG_BOARDCTL_RESET is selected. - * - * Input Parameters: - * status - Status information provided with the reset event. This - * meaning of this status information is board-specific. If not - * used by a board, the value zero may be provided in calls to - * board_reset(). - * - * Returned Value: - * If this function returns, then it was not possible to power-off the - * board due to some constraints. The return value int this case is a - * board-specific reason for the failure to shutdown. - * - ****************************************************************************/ - -int board_reset(int status) -{ - up_systemreset(); - return 0; -} - -#endif /* CONFIG_BOARDCTL_RESET */ diff --git a/boards/arm/stm32h7/nucleo-h743zi/src/stm32_romfs.h b/boards/arm/stm32h7/nucleo-h743zi/src/stm32_romfs.h deleted file mode 100644 index 6e90378c8fd43..0000000000000 --- a/boards/arm/stm32h7/nucleo-h743zi/src/stm32_romfs.h +++ /dev/null @@ -1,63 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32h7/nucleo-h743zi/src/stm32_romfs.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __BOARDS_ARM_STM32H7_NUCLEO_H743ZI_SRC_STM32_ROMFS_H -#define __BOARDS_ARM_STM32H7_NUCLEO_H743ZI_SRC_STM32_ROMFS_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#ifdef CONFIG_STM32_ROMFS - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#define ROMFS_SECTOR_SIZE 64 - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_romfs_initialize - * - * Description: - * Registers built-in ROMFS image as block device and mounts it. - * - * Returned Value: - * Zero (OK) on success, a negated errno value on error. - * - * Assumptions/Limitations: - * Memory addresses [romfs_data_begin .. romfs_data_end) should contain - * ROMFS volume data, as included in the assembly snippet above (l. 84). - * - ****************************************************************************/ - -int stm32_romfs_initialize(void); - -#endif /* CONFIG_STM32_ROMFS */ - -#endif /* __BOARDS_ARM_STM32H7_NUCLEO_H743ZI_SRC_STM32_ROMFS_H */ diff --git a/boards/arm/stm32h7/nucleo-h743zi/src/stm32_romfs_initialize.c b/boards/arm/stm32h7/nucleo-h743zi/src/stm32_romfs_initialize.c deleted file mode 100644 index 414b734317442..0000000000000 --- a/boards/arm/stm32h7/nucleo-h743zi/src/stm32_romfs_initialize.c +++ /dev/null @@ -1,139 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32h7/nucleo-h743zi/src/stm32_romfs_initialize.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include - -#include -#include -#include "stm32_romfs.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#ifndef CONFIG_STM32_ROMFS -# error "CONFIG_STM32_ROMFS must be defined" -#else - -#ifndef CONFIG_STM32_ROMFS_IMAGEFILE -# error "CONFIG_STM32_ROMFS_IMAGEFILE must be defined" -#endif - -#ifndef CONFIG_STM32_ROMFS_DEV_MINOR -# error "CONFIG_STM32_ROMFS_DEV_MINOR must be defined" -#endif - -#ifndef CONFIG_STM32_ROMFS_MOUNTPOINT -# error "CONFIG_STM32_ROMFS_MOUNTPOINT must be defined" -#endif - -#define NSECTORS(size) (((size) + ROMFS_SECTOR_SIZE - 1)/ROMFS_SECTOR_SIZE) - -#define STR2(m) #m -#define STR(m) STR2(m) - -#define MKMOUNT_DEVNAME(m) "/dev/ram" STR(m) -#define MOUNT_DEVNAME MKMOUNT_DEVNAME(CONFIG_STM32_ROMFS_DEV_MINOR) - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -__asm__ ( - " .section .rodata, \"a\" \n" - " .balign 16 \n" - " .globl romfs_data_begin \n" - "romfs_data_begin: \n" - " .incbin " STR(CONFIG_STM32_ROMFS_IMAGEFILE)"\n" - " .balign " STR(ROMFS_SECTOR_SIZE) "\n" - " .globl romfs_data_end \n" - "romfs_data_end: \n" - ); - -extern const uint8_t romfs_data_begin[]; -extern const uint8_t romfs_data_end[]; - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_romfs_initialize - * - * Description: - * Registers the aboveincluded binary file as block device. - * Then mounts the block device as ROMFS filesystems. - * - * Returned Value: - * Zero (OK) on success, a negated errno value on error. - * - * Assumptions/Limitations: - * Memory addresses [romfs_data_begin .. romfs_data_end) should contain - * ROMFS volume data, as included in the assembly snippet above (l. 84). - * - ****************************************************************************/ - -int stm32_romfs_initialize(void) -{ - size_t romfs_data_len; - int ret; - - /* Create a ROM disk for the /etc filesystem */ - - romfs_data_len = romfs_data_end - romfs_data_begin; - - ret = romdisk_register(CONFIG_STM32_ROMFS_DEV_MINOR, romfs_data_begin, - NSECTORS(romfs_data_len), ROMFS_SECTOR_SIZE); - if (ret < 0) - { - ferr("ERROR: romdisk_register failed: %d\n", -ret); - return ret; - } - - /* Mount the file system */ - - finfo("Mounting ROMFS filesystem at target=%s with source=%s\n", - CONFIG_STM32_ROMFS_MOUNTPOINT, MOUNT_DEVNAME); - - ret = nx_mount(MOUNT_DEVNAME, CONFIG_STM32_ROMFS_MOUNTPOINT, - "romfs", MS_RDONLY, NULL); - if (ret < 0) - { - ferr("ERROR: nx_mount(%s,%s,romfs) failed: %d\n", - MOUNT_DEVNAME, CONFIG_STM32_ROMFS_MOUNTPOINT, ret); - return ret; - } - - return OK; -} - -#endif /* CONFIG_STM32_ROMFS */ diff --git a/boards/arm/stm32h7/nucleo-h743zi/src/stm32_spi.c b/boards/arm/stm32h7/nucleo-h743zi/src/stm32_spi.c index 04b75b9f41d7f..42f9a514fe6a2 100644 --- a/boards/arm/stm32h7/nucleo-h743zi/src/stm32_spi.c +++ b/boards/arm/stm32h7/nucleo-h743zi/src/stm32_spi.c @@ -41,7 +41,7 @@ #include "nucleo-h743zi.h" #include -#ifdef CONFIG_STM32H7_SPI +#ifdef CONFIG_STM32_SPI /**************************************************************************** * Public Functions @@ -63,7 +63,7 @@ void stm32_spidev_initialize(void) * architecture. */ -#ifdef CONFIG_STM32H7_SPI3 +#ifdef CONFIG_STM32_SPI3 spiinfo("Configure GPIO for SPI3/CS\n"); # ifdef CONFIG_WL_NRF24L01 @@ -108,7 +108,7 @@ void stm32_spidev_initialize(void) * ****************************************************************************/ -#ifdef CONFIG_STM32H7_SPI1 +#ifdef CONFIG_STM32_SPI1 void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -122,7 +122,7 @@ uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32H7_SPI2 +#ifdef CONFIG_STM32_SPI2 void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -136,7 +136,7 @@ uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32H7_SPI3 +#ifdef CONFIG_STM32_SPI3 void stm32_spi3select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -192,7 +192,7 @@ uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32H7_SPI4 +#ifdef CONFIG_STM32_SPI4 void stm32_spi4select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -206,7 +206,7 @@ uint8_t stm32_spi4status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32H7_SPI5 +#ifdef CONFIG_STM32_SPI5 void stm32_spi5select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -220,7 +220,7 @@ uint8_t stm32_spi5status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32H7_SPI6 +#ifdef CONFIG_STM32_SPI6 void stm32_spi6select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -258,42 +258,42 @@ uint8_t stm32_spi6status(struct spi_dev_s *dev, uint32_t devid) ****************************************************************************/ #ifdef CONFIG_SPI_CMDDATA -#ifdef CONFIG_STM32H7_SPI1 +#ifdef CONFIG_STM32_SPI1 int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32H7_SPI2 +#ifdef CONFIG_STM32_SPI2 int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32H7_SPI3 +#ifdef CONFIG_STM32_SPI3 int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32H7_SPI4 +#ifdef CONFIG_STM32_SPI4 int stm32_spi4cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32H7_SPI5 +#ifdef CONFIG_STM32_SPI5 int stm32_spi5cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32H7_SPI6 +#ifdef CONFIG_STM32_SPI6 int stm32_spi5cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; @@ -301,4 +301,4 @@ int stm32_spi5cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) #endif #endif /* CONFIG_SPI_CMDDATA */ -#endif /* CONFIG_STM32H7_SPI */ +#endif /* CONFIG_STM32_SPI */ diff --git a/boards/arm/stm32h7/nucleo-h743zi/src/stm32_usb.c b/boards/arm/stm32h7/nucleo-h743zi/src/stm32_usb.c index 3efae55c0f72a..ed51bc585789b 100644 --- a/boards/arm/stm32h7/nucleo-h743zi/src/stm32_usb.c +++ b/boards/arm/stm32h7/nucleo-h743zi/src/stm32_usb.c @@ -45,7 +45,7 @@ #include "stm32_otg.h" #include "nucleo-h743zi.h" -#ifdef CONFIG_STM32H7_OTGFS +#ifdef CONFIG_STM32_OTGFS /**************************************************************************** * Pre-processor Definitions @@ -138,7 +138,7 @@ void stm32_usbinitialize(void) * Power On, and Overcurrent GPIOs */ -#ifdef CONFIG_STM32H7_OTGFS +#ifdef CONFIG_STM32_OTGFS stm32_configgpio(GPIO_OTGFS_VBUS); stm32_configgpio(GPIO_OTGFS_PWRON); stm32_configgpio(GPIO_OTGFS_OVER); diff --git a/boards/arm/stm32h7/nucleo-h743zi2/configs/jumbo/defconfig b/boards/arm/stm32h7/nucleo-h743zi2/configs/jumbo/defconfig index 23c77196423b0..f6ea962097980 100644 --- a/boards/arm/stm32h7/nucleo-h743zi2/configs/jumbo/defconfig +++ b/boards/arm/stm32h7/nucleo-h743zi2/configs/jumbo/defconfig @@ -9,9 +9,11 @@ # CONFIG_STANDARD_SERIAL is not set CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-h743zi2" +CONFIG_ARCH_BOARD_COMMON=y CONFIG_ARCH_BOARD_NUCLEO_H743ZI2=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H743ZI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -104,19 +106,19 @@ CONFIG_STACK_COLORATION=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_ETHMAC=y -CONFIG_STM32H7_HSI48=y -CONFIG_STM32H7_OTGFS=y -CONFIG_STM32H7_PHYSR=31 -CONFIG_STM32H7_PHYSR_100FD=0x0018 -CONFIG_STM32H7_PHYSR_100HD=0x0008 -CONFIG_STM32H7_PHYSR_10FD=0x0014 -CONFIG_STM32H7_PHYSR_10HD=0x0004 -CONFIG_STM32H7_PHYSR_ALTCONFIG=y -CONFIG_STM32H7_PHYSR_ALTMODE=0x001c -CONFIG_STM32H7_TIM8=y -CONFIG_STM32H7_TIM8_PULSECOUNT=y -CONFIG_STM32H7_USART3=y +CONFIG_STM32_ETHMAC=y +CONFIG_STM32_HSI48=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PHYSR=31 +CONFIG_STM32_PHYSR_100FD=0x0018 +CONFIG_STM32_PHYSR_100HD=0x0008 +CONFIG_STM32_PHYSR_10FD=0x0014 +CONFIG_STM32_PHYSR_10HD=0x0004 +CONFIG_STM32_PHYSR_ALTCONFIG=y +CONFIG_STM32_PHYSR_ALTMODE=0x001c +CONFIG_STM32_TIM8=y +CONFIG_STM32_TIM8_PULSECOUNT=y +CONFIG_STM32_USART3=y CONFIG_SYSLOG_INTBUFFER=y CONFIG_SYSLOG_PRIORITY=y CONFIG_SYSLOG_PROCESS_NAME=y diff --git a/boards/arm/stm32h7/nucleo-h743zi2/configs/netnsh/defconfig b/boards/arm/stm32h7/nucleo-h743zi2/configs/netnsh/defconfig index 42df2d25cf260..c5bbd8b5b2747 100644 --- a/boards/arm/stm32h7/nucleo-h743zi2/configs/netnsh/defconfig +++ b/boards/arm/stm32h7/nucleo-h743zi2/configs/netnsh/defconfig @@ -10,6 +10,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-h743zi2" CONFIG_ARCH_BOARD_NUCLEO_H743ZI2=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H743ZI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -65,17 +66,17 @@ CONFIG_SPI=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_ETHMAC=y -CONFIG_STM32H7_HSI48=y -CONFIG_STM32H7_OTGFS=y -CONFIG_STM32H7_PHYSR=31 -CONFIG_STM32H7_PHYSR_100FD=0x0018 -CONFIG_STM32H7_PHYSR_100HD=0x0008 -CONFIG_STM32H7_PHYSR_10FD=0x0014 -CONFIG_STM32H7_PHYSR_10HD=0x0004 -CONFIG_STM32H7_PHYSR_ALTCONFIG=y -CONFIG_STM32H7_PHYSR_ALTMODE=0x001c -CONFIG_STM32H7_USART3=y +CONFIG_STM32_ETHMAC=y +CONFIG_STM32_HSI48=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PHYSR=31 +CONFIG_STM32_PHYSR_100FD=0x0018 +CONFIG_STM32_PHYSR_100HD=0x0008 +CONFIG_STM32_PHYSR_10FD=0x0014 +CONFIG_STM32_PHYSR_10HD=0x0004 +CONFIG_STM32_PHYSR_ALTCONFIG=y +CONFIG_STM32_PHYSR_ALTMODE=0x001c +CONFIG_STM32_USART3=y CONFIG_SYSTEM_DHCPC_RENEW=y CONFIG_SYSTEM_NSH=y CONFIG_SYSTEM_PING=y diff --git a/boards/arm/stm32h7/nucleo-h743zi2/configs/nsh/defconfig b/boards/arm/stm32h7/nucleo-h743zi2/configs/nsh/defconfig index 238e410712d45..66ec35fe74b38 100644 --- a/boards/arm/stm32h7/nucleo-h743zi2/configs/nsh/defconfig +++ b/boards/arm/stm32h7/nucleo-h743zi2/configs/nsh/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-h743zi2" CONFIG_ARCH_BOARD_NUCLEO_H743ZI2=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H743ZI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -39,7 +40,7 @@ CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_USART3=y +CONFIG_STM32_USART3=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART3_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32h7/nucleo-h743zi2/configs/pysim/defconfig b/boards/arm/stm32h7/nucleo-h743zi2/configs/pysim/defconfig index 1148378b85553..2f4276ac9c9c0 100644 --- a/boards/arm/stm32h7/nucleo-h743zi2/configs/pysim/defconfig +++ b/boards/arm/stm32h7/nucleo-h743zi2/configs/pysim/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-h743zi2" CONFIG_ARCH_BOARD_NUCLEO_H743ZI2=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H743ZI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -88,32 +89,32 @@ CONFIG_SPI=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_ADC1=y -CONFIG_STM32H7_ADC1_SAMPLE_FREQUENCY=5000 -CONFIG_STM32H7_ADC1_TIMTRIG=1 -CONFIG_STM32H7_DMA1=y -CONFIG_STM32H7_ETHMAC=y -CONFIG_STM32H7_HSI48=y -CONFIG_STM32H7_OTGFS=y -CONFIG_STM32H7_PHYSR=31 -CONFIG_STM32H7_PHYSR_100FD=0x0018 -CONFIG_STM32H7_PHYSR_100HD=0x0008 -CONFIG_STM32H7_PHYSR_10FD=0x0014 -CONFIG_STM32H7_PHYSR_10HD=0x0004 -CONFIG_STM32H7_PHYSR_ALTCONFIG=y -CONFIG_STM32H7_PHYSR_ALTMODE=0x001c -CONFIG_STM32H7_PWM_MULTICHAN=y -CONFIG_STM32H7_TIM1=y -CONFIG_STM32H7_TIM1_QE=y -CONFIG_STM32H7_TIM2=y -CONFIG_STM32H7_TIM2_ADC=y -CONFIG_STM32H7_TIM3=y -CONFIG_STM32H7_TIM3_CH1OUT=y -CONFIG_STM32H7_TIM3_CH2OUT=y -CONFIG_STM32H7_TIM3_CHANNEL1=y -CONFIG_STM32H7_TIM3_CHANNEL2=y -CONFIG_STM32H7_TIM3_PWM=y -CONFIG_STM32H7_USART3=y +CONFIG_STM32_ADC1=y +CONFIG_STM32_ADC1_SAMPLE_FREQUENCY=5000 +CONFIG_STM32_ADC1_TIMTRIG=1 +CONFIG_STM32_DMA1=y +CONFIG_STM32_ETHMAC=y +CONFIG_STM32_HSI48=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PHYSR=31 +CONFIG_STM32_PHYSR_100FD=0x0018 +CONFIG_STM32_PHYSR_100HD=0x0008 +CONFIG_STM32_PHYSR_10FD=0x0014 +CONFIG_STM32_PHYSR_10HD=0x0004 +CONFIG_STM32_PHYSR_ALTCONFIG=y +CONFIG_STM32_PHYSR_ALTMODE=0x001c +CONFIG_STM32_PWM_MULTICHAN=y +CONFIG_STM32_TIM1=y +CONFIG_STM32_TIM1_QE=y +CONFIG_STM32_TIM2=y +CONFIG_STM32_TIM2_ADC=y +CONFIG_STM32_TIM3=y +CONFIG_STM32_TIM3_CH1OUT=y +CONFIG_STM32_TIM3_CH2OUT=y +CONFIG_STM32_TIM3_CHANNEL1=y +CONFIG_STM32_TIM3_CHANNEL2=y +CONFIG_STM32_TIM3_PWM=y +CONFIG_STM32_USART3=y CONFIG_SYSTEM_DHCPC_RENEW=y CONFIG_SYSTEM_NSH=y CONFIG_SYSTEM_PING=y diff --git a/boards/arm/stm32h7/nucleo-h743zi2/configs/socketcan/defconfig b/boards/arm/stm32h7/nucleo-h743zi2/configs/socketcan/defconfig index 5eb5fce08d013..68c89eacc79d3 100644 --- a/boards/arm/stm32h7/nucleo-h743zi2/configs/socketcan/defconfig +++ b/boards/arm/stm32h7/nucleo-h743zi2/configs/socketcan/defconfig @@ -13,6 +13,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-h743zi2" CONFIG_ARCH_BOARD_NUCLEO_H743ZI2=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H743ZI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -62,9 +63,9 @@ CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_FDCAN1=y -CONFIG_STM32H7_FDCAN2=y -CONFIG_STM32H7_USART3=y +CONFIG_STM32_FDCAN1=y +CONFIG_STM32_FDCAN2=y +CONFIG_STM32_USART3=y CONFIG_SYSLOG_TIMESTAMP=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 diff --git a/boards/arm/stm32h7/nucleo-h743zi2/include/board.h b/boards/arm/stm32h7/nucleo-h743zi2/include/board.h index 9f06515763291..d9a2041fb6716 100644 --- a/boards/arm/stm32h7/nucleo-h743zi2/include/board.h +++ b/boards/arm/stm32h7/nucleo-h743zi2/include/board.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32H7_NUCLEO_H743ZI2_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32H7_NUCLEO_H743ZI2_INCLUDE_BOARD_H +#ifndef __BOARDS_ARM_STM32_NUCLEO_H743ZI2_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32_NUCLEO_H743ZI2_INCLUDE_BOARD_H /**************************************************************************** * Included Files @@ -472,4 +472,4 @@ extern "C" #endif #endif /* __ASSEMBLY__ */ -#endif /* __BOARDS_ARM_STM32H7_NUCLEO_H743ZI2_INCLUDE_BOARD_H */ +#endif /* __BOARDS_ARM_STM32_NUCLEO_H743ZI2_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32h7/nucleo-h743zi2/src/CMakeLists.txt b/boards/arm/stm32h7/nucleo-h743zi2/src/CMakeLists.txt index ce26e66e8cc9d..1b725d66c14d7 100644 --- a/boards/arm/stm32h7/nucleo-h743zi2/src/CMakeLists.txt +++ b/boards/arm/stm32h7/nucleo-h743zi2/src/CMakeLists.txt @@ -32,7 +32,7 @@ else() list(APPEND SRCS stm32_userleds.c) endif() -if(CONFIG_STM32H7_OTGFS) +if(CONFIG_STM32_OTGFS) list(APPEND SRCS stm32_usb.c) endif() @@ -48,10 +48,6 @@ if(CONFIG_SENSORS_QENCODER) list(APPEND SRCS stm32_qencoder.c) endif() -if(CONFIG_BOARDCTL_RESET) - list(APPEND SRCS stm32_reset.c) -endif() - if(CONFIG_ARCH_BUTTONS) list(APPEND SRCS stm32_buttons.c) endif() diff --git a/boards/arm/stm32h7/nucleo-h743zi2/src/Make.defs b/boards/arm/stm32h7/nucleo-h743zi2/src/Make.defs new file mode 100644 index 0000000000000..eb387e1868145 --- /dev/null +++ b/boards/arm/stm32h7/nucleo-h743zi2/src/Make.defs @@ -0,0 +1,59 @@ +############################################################################ +# boards/arm/stm32h7/nucleo-h743zi2/src/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +CSRCS = stm32_boot.c stm32_bringup.c + +ifeq ($(CONFIG_ADC),y) +CSRCS += stm32_adc.c +endif + +ifeq ($(CONFIG_ARCH_LEDS),y) +CSRCS += stm32_autoleds.c +else +CSRCS += stm32_userleds.c +endif + +ifeq ($(CONFIG_ARCH_BUTTONS),y) +CSRCS += stm32_buttons.c +endif + +ifeq ($(CONFIG_STM32_OTGFS),y) +CSRCS += stm32_usb.c +endif + +ifeq ($(CONFIG_DEV_GPIO),y) +CSRCS += stm32_gpio.c +endif + +ifeq ($(CONFIG_PWM),y) +CSRCS += stm32_pwm.c +endif + +ifeq ($(CONFIG_SENSORS_QENCODER),y) +CSRCS += stm32_qencoder.c +endif + +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32h7/nucleo-h743zi2/src/Makefile b/boards/arm/stm32h7/nucleo-h743zi2/src/Makefile deleted file mode 100644 index 9991b451550b5..0000000000000 --- a/boards/arm/stm32h7/nucleo-h743zi2/src/Makefile +++ /dev/null @@ -1,61 +0,0 @@ -############################################################################ -# boards/arm/stm32h7/nucleo-h743zi2/src/Makefile -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/Make.defs - -CSRCS = stm32_boot.c stm32_bringup.c - -ifeq ($(CONFIG_ADC),y) -CSRCS += stm32_adc.c -endif - -ifeq ($(CONFIG_ARCH_LEDS),y) -CSRCS += stm32_autoleds.c -else -CSRCS += stm32_userleds.c -endif - -ifeq ($(CONFIG_ARCH_BUTTONS),y) -CSRCS += stm32_buttons.c -endif - -ifeq ($(CONFIG_STM32H7_OTGFS),y) -CSRCS += stm32_usb.c -endif - -ifeq ($(CONFIG_DEV_GPIO),y) -CSRCS += stm32_gpio.c -endif - -ifeq ($(CONFIG_PWM),y) -CSRCS += stm32_pwm.c -endif - -ifeq ($(CONFIG_SENSORS_QENCODER),y) -CSRCS += stm32_qencoder.c -endif - -ifeq ($(CONFIG_BOARDCTL_RESET),y) -CSRCS += stm32_reset.c -endif - -include $(TOPDIR)/boards/Board.mk diff --git a/boards/arm/stm32h7/nucleo-h743zi2/src/nucleo-h743zi2.h b/boards/arm/stm32h7/nucleo-h743zi2/src/nucleo-h743zi2.h index ad98bd39fd379..75674b8a01f0c 100644 --- a/boards/arm/stm32h7/nucleo-h743zi2/src/nucleo-h743zi2.h +++ b/boards/arm/stm32h7/nucleo-h743zi2/src/nucleo-h743zi2.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32H7_NUCLEO_H743ZI2_SRC_NUCLEO_H743ZI2_H -#define __BOARDS_ARM_STM32H7_NUCLEO_H743ZI2_SRC_NUCLEO_H743ZI2_H +#ifndef __BOARDS_ARM_STM32_NUCLEO_H743ZI2_SRC_NUCLEO_H743ZI2_H +#define __BOARDS_ARM_STM32_NUCLEO_H743ZI2_SRC_NUCLEO_H743ZI2_H /**************************************************************************** * Included Files @@ -44,7 +44,7 @@ /* Can't support USB host or device features if USB OTG FS is not enabled */ -#ifndef CONFIG_STM32H7_OTGFS +#ifndef CONFIG_STM32_OTGFS # undef HAVE_USBDEV # undef HAVE_USBHOST #endif @@ -143,7 +143,7 @@ /* PWM */ -#if defined(CONFIG_STM32H7_TIM1_PWM) +#if defined(CONFIG_STM32_TIM1_PWM) # define NUCLEOH743ZI2_PWMTIMER 1 #else # define NUCLEOH743ZI2_PWMTIMER 3 @@ -175,7 +175,7 @@ int stm32_bringup(void); * ****************************************************************************/ -#ifdef CONFIG_STM32H7_OTGFS +#ifdef CONFIG_STM32_OTGFS void weak_function stm32_usbinitialize(void); #endif @@ -213,7 +213,7 @@ int stm32_gpio_initialize(void); * ****************************************************************************/ -#if defined(CONFIG_STM32H7_OTGFS) && defined(CONFIG_USBHOST) +#if defined(CONFIG_STM32_OTGFS) && defined(CONFIG_USBHOST) int stm32_usbhost_initialize(void); #endif @@ -241,4 +241,4 @@ int stm32_pwm_setup(void); int stm32_qencoder_initialize(const char *devpath, int timer); #endif -#endif /* __BOARDS_ARM_STM32H7_NUCLEO_H743ZI2_SRC_NUCLEO_H743ZI2_H */ +#endif /* __BOARDS_ARM_STM32_NUCLEO_H743ZI2_SRC_NUCLEO_H743ZI2_H */ diff --git a/boards/arm/stm32h7/nucleo-h743zi2/src/stm32_adc.c b/boards/arm/stm32h7/nucleo-h743zi2/src/stm32_adc.c index 04a0ef65f5db7..3d2ddaf2c32b5 100644 --- a/boards/arm/stm32h7/nucleo-h743zi2/src/stm32_adc.c +++ b/boards/arm/stm32h7/nucleo-h743zi2/src/stm32_adc.c @@ -48,9 +48,9 @@ /* Up to 3 ADC interfaces are supported */ -#if defined(CONFIG_STM32H7_ADC1) || defined(CONFIG_STM32H7_ADC2) || \ - defined(CONFIG_STM32H7_ADC3) -#ifndef CONFIG_STM32H7_ADC1 +#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) || \ + defined(CONFIG_STM32_ADC3) +#ifndef CONFIG_STM32_ADC1 # warning "Channel information only available for ADC1" #endif @@ -63,7 +63,7 @@ * Private Data ****************************************************************************/ -#ifdef CONFIG_STM32H7_ADC1 +#ifdef CONFIG_STM32_ADC1 /* Identifying number of each ADC channel: Variable Resistor. * * ADC1: {5, 10, 12, 13, 15}; @@ -91,7 +91,7 @@ static const uint32_t g_adc1_pinlist[ADC1_NCHANNELS] = }; #endif -#ifdef CONFIG_STM32H7_ADC3 +#ifdef CONFIG_STM32_ADC3 /* Identifying number of each ADC channel: Variable Resistor. * * ADC3: {6,}; @@ -132,7 +132,7 @@ static const uint32_t g_adc3_pinlist[ADC3_NCHANNELS] = int stm32_adc_setup(void) { -#if defined(CONFIG_STM32H7_ADC1) || defined(CONFIG_STM32H7_ADC3) +#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC3) static bool initialized = false; struct adc_dev_s *adc; int ret; @@ -144,7 +144,7 @@ int stm32_adc_setup(void) if (!initialized) { #endif -#if defined(CONFIG_STM32H7_ADC1) +#if defined(CONFIG_STM32_ADC1) /* Configure the pins as analog inputs for the selected channels */ for (i = 0; i < ADC1_NCHANNELS; i++) @@ -157,7 +157,7 @@ int stm32_adc_setup(void) /* Call stm32_adcinitialize() to get an instance of the ADC interface */ - adc = stm32h7_adc_initialize(1, g_adc1_chanlist, ADC1_NCHANNELS); + adc = stm32_adc_initialize(1, g_adc1_chanlist, ADC1_NCHANNELS); if (adc == NULL) { aerr("ERROR: Failed to get ADC1 interface\n"); @@ -175,7 +175,7 @@ int stm32_adc_setup(void) devname[8]++; #endif -#if defined(CONFIG_STM32H7_ADC3) +#if defined(CONFIG_STM32_ADC3) /* Configure the pins as analog inputs for the selected channels */ for (i = 0; i < ADC3_NCHANNELS; i++) @@ -188,7 +188,7 @@ int stm32_adc_setup(void) /* Call stm32_adcinitialize() to get an instance of the ADC interface */ - adc = stm32h7_adc_initialize(3, g_adc3_chanlist, ADC3_NCHANNELS); + adc = stm32_adc_initialize(3, g_adc3_chanlist, ADC3_NCHANNELS); if (adc == NULL) { aerr("ERROR: Failed to get ADC3 interface\n"); @@ -205,7 +205,7 @@ int stm32_adc_setup(void) } #endif -#if defined(CONFIG_STM32H7_ADC1) || defined(CONFIG_STM32H7_ADC3) +#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC3) /* Now we are initialized */ initialized = true; @@ -217,5 +217,5 @@ int stm32_adc_setup(void) #endif } -#endif /* CONFIG_STM32H7_ADC1 || CONFIG_STM32H7_ADC2 || CONFIG_STM32H7_ADC3 */ +#endif /* CONFIG_STM32_ADC1 || CONFIG_STM32_ADC2 || CONFIG_STM32_ADC3 */ #endif /* CONFIG_ADC */ diff --git a/boards/arm/stm32h7/nucleo-h743zi2/src/stm32_boot.c b/boards/arm/stm32h7/nucleo-h743zi2/src/stm32_boot.c index be6710f36d0a9..29d8de24ef8bb 100644 --- a/boards/arm/stm32h7/nucleo-h743zi2/src/stm32_boot.c +++ b/boards/arm/stm32h7/nucleo-h743zi2/src/stm32_boot.c @@ -58,7 +58,7 @@ void stm32_boardinitialize(void) board_autoled_initialize(); #endif -#if defined(CONFIG_STM32H7_OTGFS) || defined(CONFIG_STM32H7_HOST) +#if defined(CONFIG_STM32_OTGFS) || defined(CONFIG_STM32_HOST) /* Initialize USB */ stm32_usbinitialize(); diff --git a/boards/arm/stm32h7/nucleo-h743zi2/src/stm32_bringup.c b/boards/arm/stm32h7/nucleo-h743zi2/src/stm32_bringup.c index f0d0a7df159bd..f526cd6876ba9 100644 --- a/boards/arm/stm32h7/nucleo-h743zi2/src/stm32_bringup.c +++ b/boards/arm/stm32h7/nucleo-h743zi2/src/stm32_bringup.c @@ -35,11 +35,11 @@ #include #include -#ifdef CONFIG_STM32H7_OTGFS +#ifdef CONFIG_STM32_OTGFS #include "stm32_usbhost.h" #endif -#ifdef CONFIG_STM32H7_FDCAN +#ifdef CONFIG_STM32_FDCAN #include "stm32_fdcan_sock.h" #endif @@ -242,18 +242,18 @@ int stm32_bringup(void) #ifdef CONFIG_NETDEV_LATEINIT -# ifdef CONFIG_STM32H7_FDCAN1 +# ifdef CONFIG_STM32_FDCAN1 stm32_fdcansockinitialize(0); # endif -# ifdef CONFIG_STM32H7_FDCAN2 +# ifdef CONFIG_STM32_FDCAN2 stm32_fdcansockinitialize(1); # endif #endif #ifdef CONFIG_SENSORS_QENCODER -#ifdef CONFIG_STM32H7_TIM1_QE +#ifdef CONFIG_STM32_TIM1_QE ret = stm32_qencoder_initialize("/dev/qe0", 1); if (ret < 0) { @@ -264,7 +264,7 @@ int stm32_bringup(void) } #endif -#ifdef CONFIG_STM32H7_TIM3_QE +#ifdef CONFIG_STM32_TIM3_QE ret = stm32_qencoder_initialize("/dev/qe2", 3); if (ret < 0) { @@ -275,7 +275,7 @@ int stm32_bringup(void) } #endif -#ifdef CONFIG_STM32H7_TIM4_QE +#ifdef CONFIG_STM32_TIM4_QE ret = stm32_qencoder_initialize("/dev/qe3", 4); if (ret < 0) { diff --git a/boards/arm/stm32h7/nucleo-h743zi2/src/stm32_pwm.c b/boards/arm/stm32h7/nucleo-h743zi2/src/stm32_pwm.c index 51afc1e4447bd..943a4c4a8846d 100644 --- a/boards/arm/stm32h7/nucleo-h743zi2/src/stm32_pwm.c +++ b/boards/arm/stm32h7/nucleo-h743zi2/src/stm32_pwm.c @@ -84,7 +84,7 @@ int stm32_pwm_setup(void) /* Register the PWM driver at "/dev/pwm0" */ - #if defined(CONFIG_STM32H7_TIM1_PWM) + #if defined(CONFIG_STM32_TIM1_PWM) ret = pwm_register("/dev/pwm0", pwm); if (ret < 0) { @@ -93,7 +93,7 @@ int stm32_pwm_setup(void) } #endif -#if defined(CONFIG_STM32H7_TIM3_PWM) +#if defined(CONFIG_STM32_TIM3_PWM) ret = pwm_register("/dev/pwm2", pwm); if (ret < 0) { diff --git a/boards/arm/stm32h7/nucleo-h743zi2/src/stm32_reset.c b/boards/arm/stm32h7/nucleo-h743zi2/src/stm32_reset.c deleted file mode 100644 index 5ed1e65ea63d4..0000000000000 --- a/boards/arm/stm32h7/nucleo-h743zi2/src/stm32_reset.c +++ /dev/null @@ -1,64 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32h7/nucleo-h743zi2/src/stm32_reset.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#ifdef CONFIG_BOARDCTL_RESET - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_reset - * - * Description: - * Reset board. Support for this function is required by board-level - * logic if CONFIG_BOARDCTL_RESET is selected. - * - * Input Parameters: - * status - Status information provided with the reset event. This - * meaning of this status information is board-specific. If not - * used by a board, the value zero may be provided in calls to - * board_reset(). - * - * Returned Value: - * If this function returns, then it was not possible to power-off the - * board due to some constraints. The return value int this case is a - * board-specific reason for the failure to shutdown. - * - ****************************************************************************/ - -int board_reset(int status) -{ - up_systemreset(); - return 0; -} - -#endif /* CONFIG_BOARDCTL_RESET */ diff --git a/boards/arm/stm32h7/nucleo-h743zi2/src/stm32_usb.c b/boards/arm/stm32h7/nucleo-h743zi2/src/stm32_usb.c index 547fda201e64a..3b7a541084ed6 100644 --- a/boards/arm/stm32h7/nucleo-h743zi2/src/stm32_usb.c +++ b/boards/arm/stm32h7/nucleo-h743zi2/src/stm32_usb.c @@ -45,7 +45,7 @@ #include "stm32_otg.h" #include "nucleo-h743zi2.h" -#ifdef CONFIG_STM32H7_OTGFS +#ifdef CONFIG_STM32_OTGFS /**************************************************************************** * Pre-processor Definitions @@ -138,7 +138,7 @@ void stm32_usbinitialize(void) * Power On, and Overcurrent GPIOs */ -#ifdef CONFIG_STM32H7_OTGFS +#ifdef CONFIG_STM32_OTGFS stm32_configgpio(GPIO_OTGFS_VBUS); stm32_configgpio(GPIO_OTGFS_PWRON); stm32_configgpio(GPIO_OTGFS_OVER); diff --git a/boards/arm/stm32h7/nucleo-h745zi/Kconfig b/boards/arm/stm32h7/nucleo-h745zi/Kconfig index bff59a181839a..bdc477c0e3970 100644 --- a/boards/arm/stm32h7/nucleo-h745zi/Kconfig +++ b/boards/arm/stm32h7/nucleo-h745zi/Kconfig @@ -11,7 +11,7 @@ choice config NUCLEOH745ZI_SMPS bool "Internal SMPS only (default)" - select STM32H7_PWR_DIRECT_SMPS_SUPPLY + select STM32_PWR_DIRECT_SMPS_SUPPLY config NUCLEOH745ZI_LDO bool "Internal LDO only" diff --git a/boards/arm/stm32h7/nucleo-h745zi/configs/nsh_cm4/defconfig b/boards/arm/stm32h7/nucleo-h745zi/configs/nsh_cm4/defconfig index 4d056b4494f3b..66d8897395cf1 100644 --- a/boards/arm/stm32h7/nucleo-h745zi/configs/nsh_cm4/defconfig +++ b/boards/arm/stm32h7/nucleo-h745zi/configs/nsh_cm4/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-h745zi" CONFIG_ARCH_BOARD_NUCLEO_H745ZI=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H745ZI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM4=y @@ -38,6 +39,6 @@ CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_USART1=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32h7/nucleo-h745zi/configs/nsh_cm4_rptun/defconfig b/boards/arm/stm32h7/nucleo-h745zi/configs/nsh_cm4_rptun/defconfig index f404c9aca7cc4..f339a51f05253 100644 --- a/boards/arm/stm32h7/nucleo-h745zi/configs/nsh_cm4_rptun/defconfig +++ b/boards/arm/stm32h7/nucleo-h745zi/configs/nsh_cm4_rptun/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-h745zi" CONFIG_ARCH_BOARD_NUCLEO_H745ZI=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H745ZI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM4=y diff --git a/boards/arm/stm32h7/nucleo-h745zi/configs/nsh_cm7/defconfig b/boards/arm/stm32h7/nucleo-h745zi/configs/nsh_cm7/defconfig index a4a5abb06fc0e..5aed179743265 100644 --- a/boards/arm/stm32h7/nucleo-h745zi/configs/nsh_cm7/defconfig +++ b/boards/arm/stm32h7/nucleo-h745zi/configs/nsh_cm7/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-h745zi" CONFIG_ARCH_BOARD_NUCLEO_H745ZI=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H745ZI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -42,6 +43,6 @@ CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_USART3=y +CONFIG_STM32_USART3=y CONFIG_SYSTEM_NSH=y CONFIG_USART3_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32h7/nucleo-h745zi/configs/nsh_cm7_rptun/defconfig b/boards/arm/stm32h7/nucleo-h745zi/configs/nsh_cm7_rptun/defconfig index 32deeca58262e..b64fcb0e0aa8f 100644 --- a/boards/arm/stm32h7/nucleo-h745zi/configs/nsh_cm7_rptun/defconfig +++ b/boards/arm/stm32h7/nucleo-h745zi/configs/nsh_cm7_rptun/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-h745zi" CONFIG_ARCH_BOARD_NUCLEO_H745ZI=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H745ZI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -48,7 +49,7 @@ CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_USART3=y +CONFIG_STM32_USART3=y CONFIG_SYSTEM_CUTERM=y CONFIG_SYSTEM_NSH=y CONFIG_USART3_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32h7/nucleo-h745zi/configs/pysim_cm7/defconfig b/boards/arm/stm32h7/nucleo-h745zi/configs/pysim_cm7/defconfig index 5876e49c1e4e4..2d7fa0de5d037 100644 --- a/boards/arm/stm32h7/nucleo-h745zi/configs/pysim_cm7/defconfig +++ b/boards/arm/stm32h7/nucleo-h745zi/configs/pysim_cm7/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-h745zi" CONFIG_ARCH_BOARD_NUCLEO_H745ZI=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H745ZI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -88,32 +89,32 @@ CONFIG_SPI=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_ADC1=y -CONFIG_STM32H7_ADC1_SAMPLE_FREQUENCY=5000 -CONFIG_STM32H7_ADC1_TIMTRIG=1 -CONFIG_STM32H7_DMA1=y -CONFIG_STM32H7_ETHMAC=y -CONFIG_STM32H7_HSI48=y -CONFIG_STM32H7_OTGFS=y -CONFIG_STM32H7_PHYSR=31 -CONFIG_STM32H7_PHYSR_100FD=0x0018 -CONFIG_STM32H7_PHYSR_100HD=0x0008 -CONFIG_STM32H7_PHYSR_10FD=0x0014 -CONFIG_STM32H7_PHYSR_10HD=0x0004 -CONFIG_STM32H7_PHYSR_ALTCONFIG=y -CONFIG_STM32H7_PHYSR_ALTMODE=0x001c -CONFIG_STM32H7_PWM_MULTICHAN=y -CONFIG_STM32H7_TIM1=y -CONFIG_STM32H7_TIM1_QE=y -CONFIG_STM32H7_TIM2=y -CONFIG_STM32H7_TIM2_ADC=y -CONFIG_STM32H7_TIM3=y -CONFIG_STM32H7_TIM3_CH1OUT=y -CONFIG_STM32H7_TIM3_CH2OUT=y -CONFIG_STM32H7_TIM3_CHANNEL1=y -CONFIG_STM32H7_TIM3_CHANNEL2=y -CONFIG_STM32H7_TIM3_PWM=y -CONFIG_STM32H7_USART3=y +CONFIG_STM32_ADC1=y +CONFIG_STM32_ADC1_SAMPLE_FREQUENCY=5000 +CONFIG_STM32_ADC1_TIMTRIG=1 +CONFIG_STM32_DMA1=y +CONFIG_STM32_ETHMAC=y +CONFIG_STM32_HSI48=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PHYSR=31 +CONFIG_STM32_PHYSR_100FD=0x0018 +CONFIG_STM32_PHYSR_100HD=0x0008 +CONFIG_STM32_PHYSR_10FD=0x0014 +CONFIG_STM32_PHYSR_10HD=0x0004 +CONFIG_STM32_PHYSR_ALTCONFIG=y +CONFIG_STM32_PHYSR_ALTMODE=0x001c +CONFIG_STM32_PWM_MULTICHAN=y +CONFIG_STM32_TIM1=y +CONFIG_STM32_TIM1_QE=y +CONFIG_STM32_TIM2=y +CONFIG_STM32_TIM2_ADC=y +CONFIG_STM32_TIM3=y +CONFIG_STM32_TIM3_CH1OUT=y +CONFIG_STM32_TIM3_CH2OUT=y +CONFIG_STM32_TIM3_CHANNEL1=y +CONFIG_STM32_TIM3_CHANNEL2=y +CONFIG_STM32_TIM3_PWM=y +CONFIG_STM32_USART3=y CONFIG_SYSTEM_DHCPC_RENEW=y CONFIG_SYSTEM_NSH=y CONFIG_SYSTEM_PING=y diff --git a/boards/arm/stm32h7/nucleo-h745zi/include/board.h b/boards/arm/stm32h7/nucleo-h745zi/include/board.h index ff06353a65342..5ac9a8b7a4690 100644 --- a/boards/arm/stm32h7/nucleo-h745zi/include/board.h +++ b/boards/arm/stm32h7/nucleo-h745zi/include/board.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32H7_NUCLEO_H745ZI_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32H7_NUCLEO_H745ZI_INCLUDE_BOARD_H +#ifndef __BOARDS_ARM_STM32_NUCLEO_H745ZI_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32_NUCLEO_H745ZI_INCLUDE_BOARD_H /**************************************************************************** * Included Files @@ -435,4 +435,4 @@ extern "C" #endif #endif /* __ASSEMBLY__ */ -#endif /* __BOARDS_ARM_STM32H7_NUCLEO_H745ZI_INCLUDE_BOARD_H */ +#endif /* __BOARDS_ARM_STM32_NUCLEO_H745ZI_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32h7/nucleo-h745zi/scripts/flash.ld b/boards/arm/stm32h7/nucleo-h745zi/scripts/flash.ld index c4bf2bd60d66d..56c5da03c479d 100644 --- a/boards/arm/stm32h7/nucleo-h745zi/scripts/flash.ld +++ b/boards/arm/stm32h7/nucleo-h745zi/scripts/flash.ld @@ -22,7 +22,7 @@ #include -#ifndef CONFIG_STM32H7_CORTEXM4_ENABLED +#ifndef CONFIG_STM32_CORTEXM4_ENABLED MEMORY { itcm (rwx) : ORIGIN = 0x00000000, LENGTH = 64K @@ -40,7 +40,7 @@ MEMORY MEMORY { itcm (rwx) : ORIGIN = 0x00000000, LENGTH = 64K - flash (rx) : ORIGIN = 0x08000000, LENGTH = CONFIG_STM32H7_CORTEXM7_FLASH_SIZE + flash (rx) : ORIGIN = 0x08000000, LENGTH = CONFIG_STM32_CORTEXM7_FLASH_SIZE dtcm1 (rwx) : ORIGIN = 0x20000000, LENGTH = 64K dtcm2 (rwx) : ORIGIN = 0x20010000, LENGTH = 64K sram (rwx) : ORIGIN = 0x24000000, LENGTH = 512K diff --git a/boards/arm/stm32h7/nucleo-h745zi/scripts/flash_m4.ld b/boards/arm/stm32h7/nucleo-h745zi/scripts/flash_m4.ld index b24bcef0596ff..7c33bec3bd892 100644 --- a/boards/arm/stm32h7/nucleo-h745zi/scripts/flash_m4.ld +++ b/boards/arm/stm32h7/nucleo-h745zi/scripts/flash_m4.ld @@ -22,9 +22,9 @@ #include -#define STM32M4_FLASH_START (0x08000000 + CONFIG_STM32H7_CORTEXM7_FLASH_SIZE) +#define STM32M4_FLASH_START (0x08000000 + CONFIG_STM32_CORTEXM7_FLASH_SIZE) -#if CONFIG_STM32H7_CORTEXM7_FLASH_SIZE != 1048576 +#if CONFIG_STM32_CORTEXM7_FLASH_SIZE != 1048576 # error TODO: not supported yet - BCM4_ADD0 must be configured #endif @@ -34,7 +34,7 @@ MEMORY { flash (rx) : ORIGIN = STM32M4_FLASH_START, - LENGTH = (2048K - CONFIG_STM32H7_CORTEXM7_FLASH_SIZE) + LENGTH = (2048K - CONFIG_STM32_CORTEXM7_FLASH_SIZE) /* SRAM1 and SRAM2 */ diff --git a/boards/arm/stm32h7/nucleo-h745zi/src/Make.defs b/boards/arm/stm32h7/nucleo-h745zi/src/Make.defs new file mode 100644 index 0000000000000..51e5d21b913fc --- /dev/null +++ b/boards/arm/stm32h7/nucleo-h745zi/src/Make.defs @@ -0,0 +1,55 @@ +############################################################################ +# boards/arm/stm32h7/nucleo-h745zi/src/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +CSRCS = stm32_boot.c stm32_bringup.c + +ifeq ($(CONFIG_ADC),y) +CSRCS += stm32_adc.c +endif + +ifeq ($(CONFIG_ARCH_LEDS),y) +CSRCS += stm32_autoleds.c +else +CSRCS += stm32_userleds.c +endif + +ifeq ($(CONFIG_STM32_OTGFS),y) +CSRCS += stm32_usb.c +endif + +ifeq ($(CONFIG_DEV_GPIO),y) +CSRCS += stm32_gpio.c +endif + +ifeq ($(CONFIG_PWM),y) +CSRCS += stm32_pwm.c +endif + +ifeq ($(CONFIG_SENSORS_QENCODER),y) +CSRCS += stm32_qencoder.c +endif + +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32h7/nucleo-h745zi/src/Makefile b/boards/arm/stm32h7/nucleo-h745zi/src/Makefile deleted file mode 100644 index df3be92d50930..0000000000000 --- a/boards/arm/stm32h7/nucleo-h745zi/src/Makefile +++ /dev/null @@ -1,57 +0,0 @@ -############################################################################ -# boards/arm/stm32h7/nucleo-h745zi/src/Makefile -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/Make.defs - -CSRCS = stm32_boot.c stm32_bringup.c - -ifeq ($(CONFIG_ADC),y) -CSRCS += stm32_adc.c -endif - -ifeq ($(CONFIG_ARCH_LEDS),y) -CSRCS += stm32_autoleds.c -else -CSRCS += stm32_userleds.c -endif - -ifeq ($(CONFIG_STM32H7_OTGFS),y) -CSRCS += stm32_usb.c -endif - -ifeq ($(CONFIG_DEV_GPIO),y) -CSRCS += stm32_gpio.c -endif - -ifeq ($(CONFIG_PWM),y) -CSRCS += stm32_pwm.c -endif - -ifeq ($(CONFIG_SENSORS_QENCODER),y) -CSRCS += stm32_qencoder.c -endif - -ifeq ($(CONFIG_BOARDCTL_RESET),y) -CSRCS += stm32_reset.c -endif - -include $(TOPDIR)/boards/Board.mk diff --git a/boards/arm/stm32h7/nucleo-h745zi/src/nucleo-h745zi.h b/boards/arm/stm32h7/nucleo-h745zi/src/nucleo-h745zi.h index b3b16bee6f644..6d8ffc5e3ed49 100644 --- a/boards/arm/stm32h7/nucleo-h745zi/src/nucleo-h745zi.h +++ b/boards/arm/stm32h7/nucleo-h745zi/src/nucleo-h745zi.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32H7_NUCLEO_H745ZI_SRC_NUCLEO_H745ZI_H -#define __BOARDS_ARM_STM32H7_NUCLEO_H745ZI_SRC_NUCLEO_H745ZI_H +#ifndef __BOARDS_ARM_STM32_NUCLEO_H745ZI_SRC_NUCLEO_H745ZI_H +#define __BOARDS_ARM_STM32_NUCLEO_H745ZI_SRC_NUCLEO_H745ZI_H /**************************************************************************** * Included Files @@ -47,7 +47,7 @@ /* Can't support USB host or device features if USB OTG FS is not enabled */ -#ifndef CONFIG_STM32H7_OTGFS +#ifndef CONFIG_STM32_OTGFS # undef HAVE_USBDEV # undef HAVE_USBHOST #endif @@ -82,7 +82,7 @@ # undef HAVE_USBMONITOR #endif -#if !defined(CONFIG_STM32H7_PROGMEM) || !defined(CONFIG_MTD_PROGMEM) +#if !defined(CONFIG_STM32_PROGMEM) || !defined(CONFIG_MTD_PROGMEM) # undef HAVE_PROGMEM_CHARDEV #endif @@ -226,7 +226,7 @@ /* PWM */ -#if defined(CONFIG_STM32H7_TIM1_PWM) +#if defined(CONFIG_STM32_TIM1_PWM) #define NUCLEOH745ZI_PWMTIMER 1 #else #define NUCLEOH745ZI_PWMTIMER 3 @@ -249,7 +249,7 @@ int stm32_bringup(void); -#ifdef CONFIG_STM32H7_OTGFS +#ifdef CONFIG_STM32_OTGFS void weak_function stm32_usbinitialize(void); #endif @@ -287,7 +287,7 @@ int stm32_gpio_initialize(void); * ****************************************************************************/ -#if defined(CONFIG_STM32H7_OTGFS) && defined(CONFIG_USBHOST) +#if defined(CONFIG_STM32_OTGFS) && defined(CONFIG_USBHOST) int stm32_usbhost_initialize(void); #endif @@ -315,4 +315,4 @@ int stm32_pwm_setup(void); int stm32_qencoder_initialize(const char *devpath, int timer); #endif -#endif /* __BOARDS_ARM_STM32H7_NUCLEO_H745ZI_SRC_NUCLEO_H745ZI_H */ +#endif /* __BOARDS_ARM_STM32_NUCLEO_H745ZI_SRC_NUCLEO_H745ZI_H */ diff --git a/boards/arm/stm32h7/nucleo-h745zi/src/stm32_adc.c b/boards/arm/stm32h7/nucleo-h745zi/src/stm32_adc.c index 731b1421e9313..cba9c51771b22 100644 --- a/boards/arm/stm32h7/nucleo-h745zi/src/stm32_adc.c +++ b/boards/arm/stm32h7/nucleo-h745zi/src/stm32_adc.c @@ -49,9 +49,9 @@ /* Up to 3 ADC interfaces are supported */ -#if defined(CONFIG_STM32H7_ADC1) || defined(CONFIG_STM32H7_ADC2) || \ - defined(CONFIG_STM32H7_ADC3) -#ifndef CONFIG_STM32H7_ADC1 +#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) || \ + defined(CONFIG_STM32_ADC3) +#ifndef CONFIG_STM32_ADC1 # warning "Channel information only available for ADC1" #endif @@ -64,7 +64,7 @@ * Private Data ****************************************************************************/ -#ifdef CONFIG_STM32H7_ADC1 +#ifdef CONFIG_STM32_ADC1 /* Identifying number of each ADC channel: Variable Resistor. * * ADC1: {5, 10, 12, 13, 15}; @@ -92,7 +92,7 @@ static const uint32_t g_adc1_pinlist[ADC1_NCHANNELS] = }; #endif -#ifdef CONFIG_STM32H7_ADC3 +#ifdef CONFIG_STM32_ADC3 /* Identifying number of each ADC channel: Variable Resistor. * * ADC3: {6,}; @@ -133,7 +133,7 @@ static const uint32_t g_adc3_pinlist[ADC3_NCHANNELS] = int stm32_adc_setup(int adcno) { -#if defined(CONFIG_STM32H7_ADC1) || defined(CONFIG_STM32H7_ADC3) +#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC3) static bool initialized = false; struct adc_dev_s *adc; int ret; @@ -147,7 +147,7 @@ int stm32_adc_setup(int adcno) snprintf(devname, sizeof(devname), "/dev/adc%d", adcno); #endif -#if defined(CONFIG_STM32H7_ADC1) +#if defined(CONFIG_STM32_ADC1) /* Configure the pins as analog inputs for the selected channels */ for (i = 0; i < ADC1_NCHANNELS; i++) @@ -160,7 +160,7 @@ int stm32_adc_setup(int adcno) /* Call stm32_adcinitialize() to get an instance of the ADC interface */ - adc = stm32h7_adc_initialize(1, g_adc1_chanlist, ADC1_NCHANNELS); + adc = stm32_adc_initialize(1, g_adc1_chanlist, ADC1_NCHANNELS); if (adc == NULL) { aerr("ERROR: Failed to get ADC1 interface\n"); @@ -178,7 +178,7 @@ int stm32_adc_setup(int adcno) devname[8]++; #endif -#if defined(CONFIG_STM32H7_ADC3) +#if defined(CONFIG_STM32_ADC3) /* Configure the pins as analog inputs for the selected channels */ for (i = 0; i < ADC3_NCHANNELS; i++) @@ -191,7 +191,7 @@ int stm32_adc_setup(int adcno) /* Call stm32_adcinitialize() to get an instance of the ADC interface */ - adc = stm32h7_adc_initialize(3, g_adc3_chanlist, ADC3_NCHANNELS); + adc = stm32_adc_initialize(3, g_adc3_chanlist, ADC3_NCHANNELS); if (adc == NULL) { aerr("ERROR: Failed to get ADC3 interface\n"); @@ -208,7 +208,7 @@ int stm32_adc_setup(int adcno) } #endif -#if defined(CONFIG_STM32H7_ADC1) || defined(CONFIG_STM32H7_ADC3) +#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC3) /* Now we are initialized */ initialized = true; @@ -220,5 +220,5 @@ int stm32_adc_setup(int adcno) #endif } -#endif /* CONFIG_STM32H7_ADC1 || CONFIG_STM32H7_ADC2 || CONFIG_STM32H7_ADC3 */ +#endif /* CONFIG_STM32_ADC1 || CONFIG_STM32_ADC2 || CONFIG_STM32_ADC3 */ #endif /* CONFIG_ADC */ diff --git a/boards/arm/stm32h7/nucleo-h745zi/src/stm32_boot.c b/boards/arm/stm32h7/nucleo-h745zi/src/stm32_boot.c index dfbbfecba2b73..265a4399fef3b 100644 --- a/boards/arm/stm32h7/nucleo-h745zi/src/stm32_boot.c +++ b/boards/arm/stm32h7/nucleo-h745zi/src/stm32_boot.c @@ -58,13 +58,13 @@ void stm32_boardinitialize(void) board_autoled_initialize(); #endif -#if defined(CONFIG_STM32H7_OTGFS) || defined(CONFIG_STM32H7_HOST) +#if defined(CONFIG_STM32_OTGFS) || defined(CONFIG_STM32_HOST) /* Initialize USB */ stm32_usbinitialize(); #endif -#ifdef CONFIG_STM32H7_SPI +#ifdef CONFIG_STM32_SPI /* Configure SPI chip selects */ stm32_spidev_initialize(); diff --git a/boards/arm/stm32h7/nucleo-h745zi/src/stm32_bringup.c b/boards/arm/stm32h7/nucleo-h745zi/src/stm32_bringup.c index a8e26a5b59120..aa9ab6abbc6de 100644 --- a/boards/arm/stm32h7/nucleo-h745zi/src/stm32_bringup.c +++ b/boards/arm/stm32h7/nucleo-h745zi/src/stm32_bringup.c @@ -144,11 +144,11 @@ int stm32_bringup(void) int adcno = 0; -#ifdef CONFIG_STM32H7_ADC1 +#ifdef CONFIG_STM32_ADC1 adcno = 0; #endif -#ifdef CONFIG_STM32H7_ADC3 +#ifdef CONFIG_STM32_ADC3 adcno = 2; #endif @@ -172,18 +172,18 @@ int stm32_bringup(void) #ifdef CONFIG_NETDEV_LATEINIT -# ifdef CONFIG_STM32H7_FDCAN1 +# ifdef CONFIG_STM32_FDCAN1 stm32_fdcansockinitialize(0); # endif -# ifdef CONFIG_STM32H7_FDCAN2 +# ifdef CONFIG_STM32_FDCAN2 stm32_fdcansockinitialize(1); # endif #endif #ifdef CONFIG_SENSORS_QENCODER -#ifdef CONFIG_STM32H7_TIM1_QE +#ifdef CONFIG_STM32_TIM1_QE ret = stm32_qencoder_initialize("/dev/qe0", 1); if (ret < 0) { @@ -194,7 +194,7 @@ int stm32_bringup(void) } #endif -#ifdef CONFIG_STM32H7_TIM3_QE +#ifdef CONFIG_STM32_TIM3_QE ret = stm32_qencoder_initialize("/dev/qe2", 3); if (ret < 0) { @@ -205,7 +205,7 @@ int stm32_bringup(void) } #endif -#ifdef CONFIG_STM32H7_TIM4_QE +#ifdef CONFIG_STM32_TIM4_QE ret = stm32_qencoder_initialize("/dev/qe3", 4); if (ret < 0) { diff --git a/boards/arm/stm32h7/nucleo-h745zi/src/stm32_pwm.c b/boards/arm/stm32h7/nucleo-h745zi/src/stm32_pwm.c index 1e34ac8a09359..adeaaf3673c93 100644 --- a/boards/arm/stm32h7/nucleo-h745zi/src/stm32_pwm.c +++ b/boards/arm/stm32h7/nucleo-h745zi/src/stm32_pwm.c @@ -84,7 +84,7 @@ int stm32_pwm_setup(void) /* Register the PWM driver at "/dev/pwm0" */ - #if defined(CONFIG_STM32H7_TIM1_PWM) + #if defined(CONFIG_STM32_TIM1_PWM) ret = pwm_register("/dev/pwm0", pwm); if (ret < 0) { @@ -93,7 +93,7 @@ int stm32_pwm_setup(void) } #endif -#if defined(CONFIG_STM32H7_TIM3_PWM) +#if defined(CONFIG_STM32_TIM3_PWM) ret = pwm_register("/dev/pwm2", pwm); if (ret < 0) { diff --git a/boards/arm/stm32h7/nucleo-h745zi/src/stm32_usb.c b/boards/arm/stm32h7/nucleo-h745zi/src/stm32_usb.c index 77b5638be1f6c..c06f89ef35a20 100644 --- a/boards/arm/stm32h7/nucleo-h745zi/src/stm32_usb.c +++ b/boards/arm/stm32h7/nucleo-h745zi/src/stm32_usb.c @@ -45,7 +45,7 @@ #include "stm32_otg.h" #include "nucleo-h745zi.h" -#ifdef CONFIG_STM32H7_OTGFS +#ifdef CONFIG_STM32_OTGFS /**************************************************************************** * Pre-processor Definitions @@ -138,7 +138,7 @@ void stm32_usbinitialize(void) * Power On, and Overcurrent GPIOs */ -#ifdef CONFIG_STM32H7_OTGFS +#ifdef CONFIG_STM32_OTGFS stm32_configgpio(GPIO_OTGFS_VBUS); stm32_configgpio(GPIO_OTGFS_PWRON); stm32_configgpio(GPIO_OTGFS_OVER); diff --git a/boards/arm/stm32h7/nucleo-h753zi/configs/crypto/defconfig b/boards/arm/stm32h7/nucleo-h753zi/configs/crypto/defconfig index e36ef99884439..9f75e257f097e 100644 --- a/boards/arm/stm32h7/nucleo-h753zi/configs/crypto/defconfig +++ b/boards/arm/stm32h7/nucleo-h753zi/configs/crypto/defconfig @@ -16,6 +16,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-h753zi" CONFIG_ARCH_BOARD_NUCLEO_H753ZI=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H753ZI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -47,8 +48,8 @@ CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_CRYP=y -CONFIG_STM32H7_USART3=y +CONFIG_STM32_CRYP=y +CONFIG_STM32_USART3=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_TESTING_CRYPTO=y diff --git a/boards/arm/stm32h7/nucleo-h753zi/configs/jumbo/defconfig b/boards/arm/stm32h7/nucleo-h753zi/configs/jumbo/defconfig index 4482d9ba53b8a..798c4794b4c76 100644 --- a/boards/arm/stm32h7/nucleo-h753zi/configs/jumbo/defconfig +++ b/boards/arm/stm32h7/nucleo-h753zi/configs/jumbo/defconfig @@ -9,9 +9,11 @@ # CONFIG_STANDARD_SERIAL is not set CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-h753zi" +CONFIG_ARCH_BOARD_COMMON=y CONFIG_ARCH_BOARD_NUCLEO_H753ZI=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H753ZI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -103,17 +105,17 @@ CONFIG_STACK_COLORATION=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_ETHMAC=y -CONFIG_STM32H7_HSI48=y -CONFIG_STM32H7_OTGFS=y -CONFIG_STM32H7_PHYSR=31 -CONFIG_STM32H7_PHYSR_100FD=0x0018 -CONFIG_STM32H7_PHYSR_100HD=0x0008 -CONFIG_STM32H7_PHYSR_10FD=0x0014 -CONFIG_STM32H7_PHYSR_10HD=0x0004 -CONFIG_STM32H7_PHYSR_ALTCONFIG=y -CONFIG_STM32H7_PHYSR_ALTMODE=0x001c -CONFIG_STM32H7_USART3=y +CONFIG_STM32_ETHMAC=y +CONFIG_STM32_HSI48=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PHYSR=31 +CONFIG_STM32_PHYSR_100FD=0x0018 +CONFIG_STM32_PHYSR_100HD=0x0008 +CONFIG_STM32_PHYSR_10FD=0x0014 +CONFIG_STM32_PHYSR_10HD=0x0004 +CONFIG_STM32_PHYSR_ALTCONFIG=y +CONFIG_STM32_PHYSR_ALTMODE=0x001c +CONFIG_STM32_USART3=y CONFIG_SYSLOG_INTBUFFER=y CONFIG_SYSLOG_PRIORITY=y CONFIG_SYSLOG_PROCESS_NAME=y diff --git a/boards/arm/stm32h7/nucleo-h753zi/configs/netnsh/defconfig b/boards/arm/stm32h7/nucleo-h753zi/configs/netnsh/defconfig index 6d3d69392c974..690987ab92fcd 100644 --- a/boards/arm/stm32h7/nucleo-h753zi/configs/netnsh/defconfig +++ b/boards/arm/stm32h7/nucleo-h753zi/configs/netnsh/defconfig @@ -10,6 +10,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-h753zi" CONFIG_ARCH_BOARD_NUCLEO_H753ZI=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H753ZI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -65,17 +66,17 @@ CONFIG_SPI=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_ETHMAC=y -CONFIG_STM32H7_HSI48=y -CONFIG_STM32H7_OTGFS=y -CONFIG_STM32H7_PHYSR=31 -CONFIG_STM32H7_PHYSR_100FD=0x0018 -CONFIG_STM32H7_PHYSR_100HD=0x0008 -CONFIG_STM32H7_PHYSR_10FD=0x0014 -CONFIG_STM32H7_PHYSR_10HD=0x0004 -CONFIG_STM32H7_PHYSR_ALTCONFIG=y -CONFIG_STM32H7_PHYSR_ALTMODE=0x001c -CONFIG_STM32H7_USART3=y +CONFIG_STM32_ETHMAC=y +CONFIG_STM32_HSI48=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PHYSR=31 +CONFIG_STM32_PHYSR_100FD=0x0018 +CONFIG_STM32_PHYSR_100HD=0x0008 +CONFIG_STM32_PHYSR_10FD=0x0014 +CONFIG_STM32_PHYSR_10HD=0x0004 +CONFIG_STM32_PHYSR_ALTCONFIG=y +CONFIG_STM32_PHYSR_ALTMODE=0x001c +CONFIG_STM32_USART3=y CONFIG_SYSTEM_DHCPC_RENEW=y CONFIG_SYSTEM_NSH=y CONFIG_SYSTEM_PING=y diff --git a/boards/arm/stm32h7/nucleo-h753zi/configs/nsh/defconfig b/boards/arm/stm32h7/nucleo-h753zi/configs/nsh/defconfig index 4e017f8e0db0a..d4005fc697a06 100644 --- a/boards/arm/stm32h7/nucleo-h753zi/configs/nsh/defconfig +++ b/boards/arm/stm32h7/nucleo-h753zi/configs/nsh/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-h753zi" CONFIG_ARCH_BOARD_NUCLEO_H753ZI=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H753ZI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -39,7 +40,7 @@ CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_USART3=y +CONFIG_STM32_USART3=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART3_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32h7/nucleo-h753zi/configs/pysim/defconfig b/boards/arm/stm32h7/nucleo-h753zi/configs/pysim/defconfig index 6851a571ec6db..d6e8735235260 100644 --- a/boards/arm/stm32h7/nucleo-h753zi/configs/pysim/defconfig +++ b/boards/arm/stm32h7/nucleo-h753zi/configs/pysim/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-h753zi" CONFIG_ARCH_BOARD_NUCLEO_H753ZI=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H753ZI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -88,32 +89,32 @@ CONFIG_SPI=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_ADC1=y -CONFIG_STM32H7_ADC1_SAMPLE_FREQUENCY=5000 -CONFIG_STM32H7_ADC1_TIMTRIG=1 -CONFIG_STM32H7_DMA1=y -CONFIG_STM32H7_ETHMAC=y -CONFIG_STM32H7_HSI48=y -CONFIG_STM32H7_OTGFS=y -CONFIG_STM32H7_PHYSR=31 -CONFIG_STM32H7_PHYSR_100FD=0x0018 -CONFIG_STM32H7_PHYSR_100HD=0x0008 -CONFIG_STM32H7_PHYSR_10FD=0x0014 -CONFIG_STM32H7_PHYSR_10HD=0x0004 -CONFIG_STM32H7_PHYSR_ALTCONFIG=y -CONFIG_STM32H7_PHYSR_ALTMODE=0x001c -CONFIG_STM32H7_PWM_MULTICHAN=y -CONFIG_STM32H7_TIM1=y -CONFIG_STM32H7_TIM1_QE=y -CONFIG_STM32H7_TIM2=y -CONFIG_STM32H7_TIM2_ADC=y -CONFIG_STM32H7_TIM3=y -CONFIG_STM32H7_TIM3_CH1OUT=y -CONFIG_STM32H7_TIM3_CH2OUT=y -CONFIG_STM32H7_TIM3_CHANNEL1=y -CONFIG_STM32H7_TIM3_CHANNEL2=y -CONFIG_STM32H7_TIM3_PWM=y -CONFIG_STM32H7_USART3=y +CONFIG_STM32_ADC1=y +CONFIG_STM32_ADC1_SAMPLE_FREQUENCY=5000 +CONFIG_STM32_ADC1_TIMTRIG=1 +CONFIG_STM32_DMA1=y +CONFIG_STM32_ETHMAC=y +CONFIG_STM32_HSI48=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PHYSR=31 +CONFIG_STM32_PHYSR_100FD=0x0018 +CONFIG_STM32_PHYSR_100HD=0x0008 +CONFIG_STM32_PHYSR_10FD=0x0014 +CONFIG_STM32_PHYSR_10HD=0x0004 +CONFIG_STM32_PHYSR_ALTCONFIG=y +CONFIG_STM32_PHYSR_ALTMODE=0x001c +CONFIG_STM32_PWM_MULTICHAN=y +CONFIG_STM32_TIM1=y +CONFIG_STM32_TIM1_QE=y +CONFIG_STM32_TIM2=y +CONFIG_STM32_TIM2_ADC=y +CONFIG_STM32_TIM3=y +CONFIG_STM32_TIM3_CH1OUT=y +CONFIG_STM32_TIM3_CH2OUT=y +CONFIG_STM32_TIM3_CHANNEL1=y +CONFIG_STM32_TIM3_CHANNEL2=y +CONFIG_STM32_TIM3_PWM=y +CONFIG_STM32_USART3=y CONFIG_SYSTEM_DHCPC_RENEW=y CONFIG_SYSTEM_NSH=y CONFIG_SYSTEM_PING=y diff --git a/boards/arm/stm32h7/nucleo-h753zi/configs/socketcan/defconfig b/boards/arm/stm32h7/nucleo-h753zi/configs/socketcan/defconfig index 602d566130dda..f9643ef1a1a8f 100644 --- a/boards/arm/stm32h7/nucleo-h753zi/configs/socketcan/defconfig +++ b/boards/arm/stm32h7/nucleo-h753zi/configs/socketcan/defconfig @@ -13,6 +13,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-h753zi" CONFIG_ARCH_BOARD_NUCLEO_H753ZI=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H753ZI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -62,9 +63,9 @@ CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_FDCAN1=y -CONFIG_STM32H7_FDCAN2=y -CONFIG_STM32H7_USART3=y +CONFIG_STM32_FDCAN1=y +CONFIG_STM32_FDCAN2=y +CONFIG_STM32_USART3=y CONFIG_SYSLOG_TIMESTAMP=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 diff --git a/boards/arm/stm32h7/nucleo-h753zi/include/board.h b/boards/arm/stm32h7/nucleo-h753zi/include/board.h index 504c40be53901..66b77b6ff83ef 100644 --- a/boards/arm/stm32h7/nucleo-h753zi/include/board.h +++ b/boards/arm/stm32h7/nucleo-h753zi/include/board.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32H7_NUCLEO_H753ZI_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32H7_NUCLEO_H753ZI_INCLUDE_BOARD_H +#ifndef __BOARDS_ARM_STM32_NUCLEO_H753ZI_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32_NUCLEO_H753ZI_INCLUDE_BOARD_H /**************************************************************************** * Included Files @@ -468,4 +468,4 @@ extern "C" #endif #endif /* __ASSEMBLY__ */ -#endif /* __BOARDS_ARM_STM32H7_NUCLEO_H753ZI_INCLUDE_BOARD_H */ +#endif /* __BOARDS_ARM_STM32_NUCLEO_H753ZI_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32h7/nucleo-h753zi/src/CMakeLists.txt b/boards/arm/stm32h7/nucleo-h753zi/src/CMakeLists.txt index 73ac7a500a71d..97d733a628051 100644 --- a/boards/arm/stm32h7/nucleo-h753zi/src/CMakeLists.txt +++ b/boards/arm/stm32h7/nucleo-h753zi/src/CMakeLists.txt @@ -32,7 +32,7 @@ else() list(APPEND SRCS stm32_userleds.c) endif() -if(CONFIG_STM32H7_OTGFS) +if(CONFIG_STM32_OTGFS) list(APPEND SRCS stm32_usb.c) endif() @@ -48,10 +48,6 @@ if(CONFIG_SENSORS_QENCODER) list(APPEND SRCS stm32_qencoder.c) endif() -if(CONFIG_BOARDCTL_RESET) - list(APPEND SRCS stm32_reset.c) -endif() - if(CONFIG_ARCH_BUTTONS) list(APPEND SRCS stm32_buttons.c) endif() diff --git a/boards/arm/stm32h7/nucleo-h753zi/src/Make.defs b/boards/arm/stm32h7/nucleo-h753zi/src/Make.defs new file mode 100644 index 0000000000000..9e33e8b94802a --- /dev/null +++ b/boards/arm/stm32h7/nucleo-h753zi/src/Make.defs @@ -0,0 +1,59 @@ +############################################################################ +# boards/arm/stm32h7/nucleo-h753zi/src/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +CSRCS = stm32_boot.c stm32_bringup.c + +ifeq ($(CONFIG_ADC),y) +CSRCS += stm32_adc.c +endif + +ifeq ($(CONFIG_ARCH_LEDS),y) +CSRCS += stm32_autoleds.c +else +CSRCS += stm32_userleds.c +endif + +ifeq ($(CONFIG_ARCH_BUTTONS),y) +CSRCS += stm32_buttons.c +endif + +ifeq ($(CONFIG_STM32_OTGFS),y) +CSRCS += stm32_usb.c +endif + +ifeq ($(CONFIG_DEV_GPIO),y) +CSRCS += stm32_gpio.c +endif + +ifeq ($(CONFIG_PWM),y) +CSRCS += stm32_pwm.c +endif + +ifeq ($(CONFIG_SENSORS_QENCODER),y) +CSRCS += stm32_qencoder.c +endif + +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32h7/nucleo-h753zi/src/Makefile b/boards/arm/stm32h7/nucleo-h753zi/src/Makefile deleted file mode 100644 index 0f164c5b1a4d1..0000000000000 --- a/boards/arm/stm32h7/nucleo-h753zi/src/Makefile +++ /dev/null @@ -1,61 +0,0 @@ -############################################################################ -# boards/arm/stm32h7/nucleo-h753zi/src/Makefile -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/Make.defs - -CSRCS = stm32_boot.c stm32_bringup.c - -ifeq ($(CONFIG_ADC),y) -CSRCS += stm32_adc.c -endif - -ifeq ($(CONFIG_ARCH_LEDS),y) -CSRCS += stm32_autoleds.c -else -CSRCS += stm32_userleds.c -endif - -ifeq ($(CONFIG_ARCH_BUTTONS),y) -CSRCS += stm32_buttons.c -endif - -ifeq ($(CONFIG_STM32H7_OTGFS),y) -CSRCS += stm32_usb.c -endif - -ifeq ($(CONFIG_DEV_GPIO),y) -CSRCS += stm32_gpio.c -endif - -ifeq ($(CONFIG_PWM),y) -CSRCS += stm32_pwm.c -endif - -ifeq ($(CONFIG_SENSORS_QENCODER),y) -CSRCS += stm32_qencoder.c -endif - -ifeq ($(CONFIG_BOARDCTL_RESET),y) -CSRCS += stm32_reset.c -endif - -include $(TOPDIR)/boards/Board.mk diff --git a/boards/arm/stm32h7/nucleo-h753zi/src/nucleo-h753zi.h b/boards/arm/stm32h7/nucleo-h753zi/src/nucleo-h753zi.h index 8549c8b633afc..17472c9fffe35 100644 --- a/boards/arm/stm32h7/nucleo-h753zi/src/nucleo-h753zi.h +++ b/boards/arm/stm32h7/nucleo-h753zi/src/nucleo-h753zi.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32H7_NUCLEO_H753ZI_SRC_NUCLEO_H753ZI_H -#define __BOARDS_ARM_STM32H7_NUCLEO_H753ZI_SRC_NUCLEO_H753ZI_H +#ifndef __BOARDS_ARM_STM32_NUCLEO_H753ZI_SRC_NUCLEO_H753ZI_H +#define __BOARDS_ARM_STM32_NUCLEO_H753ZI_SRC_NUCLEO_H753ZI_H /**************************************************************************** * Included Files @@ -44,7 +44,7 @@ /* Can't support USB host or device features if USB OTG FS is not enabled */ -#ifndef CONFIG_STM32H7_OTGFS +#ifndef CONFIG_STM32_OTGFS # undef HAVE_USBDEV # undef HAVE_USBHOST #endif @@ -143,7 +143,7 @@ /* PWM */ -#if defined(CONFIG_STM32H7_TIM1_PWM) +#if defined(CONFIG_STM32_TIM1_PWM) # define NUCLEOH753ZI_PWMTIMER 1 #else # define NUCLEOH753ZI_PWMTIMER 3 @@ -175,7 +175,7 @@ int stm32_bringup(void); * ****************************************************************************/ -#ifdef CONFIG_STM32H7_OTGFS +#ifdef CONFIG_STM32_OTGFS void weak_function stm32_usbinitialize(void); #endif @@ -213,7 +213,7 @@ int stm32_gpio_initialize(void); * ****************************************************************************/ -#if defined(CONFIG_STM32H7_OTGFS) && defined(CONFIG_USBHOST) +#if defined(CONFIG_STM32_OTGFS) && defined(CONFIG_USBHOST) int stm32_usbhost_initialize(void); #endif @@ -241,4 +241,4 @@ int stm32_pwm_setup(void); int stm32_qencoder_initialize(const char *devpath, int timer); #endif -#endif /* __BOARDS_ARM_STM32H7_NUCLEO_H753ZI_SRC_NUCLEO_H753ZI_H */ +#endif /* __BOARDS_ARM_STM32_NUCLEO_H753ZI_SRC_NUCLEO_H753ZI_H */ diff --git a/boards/arm/stm32h7/nucleo-h753zi/src/stm32_adc.c b/boards/arm/stm32h7/nucleo-h753zi/src/stm32_adc.c index 3bd182ef3820a..fca934607efbf 100644 --- a/boards/arm/stm32h7/nucleo-h753zi/src/stm32_adc.c +++ b/boards/arm/stm32h7/nucleo-h753zi/src/stm32_adc.c @@ -48,9 +48,9 @@ /* Up to 3 ADC interfaces are supported */ -#if defined(CONFIG_STM32H7_ADC1) || defined(CONFIG_STM32H7_ADC2) || \ - defined(CONFIG_STM32H7_ADC3) -#ifndef CONFIG_STM32H7_ADC1 +#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) || \ + defined(CONFIG_STM32_ADC3) +#ifndef CONFIG_STM32_ADC1 # warning "Channel information only available for ADC1" #endif @@ -63,7 +63,7 @@ * Private Data ****************************************************************************/ -#ifdef CONFIG_STM32H7_ADC1 +#ifdef CONFIG_STM32_ADC1 /* Identifying number of each ADC channel: Variable Resistor. * * ADC1: {5, 10, 12, 13, 15}; @@ -91,7 +91,7 @@ static const uint32_t g_adc1_pinlist[ADC1_NCHANNELS] = }; #endif -#ifdef CONFIG_STM32H7_ADC3 +#ifdef CONFIG_STM32_ADC3 /* Identifying number of each ADC channel: Variable Resistor. * * ADC3: {6,}; @@ -132,7 +132,7 @@ static const uint32_t g_adc3_pinlist[ADC3_NCHANNELS] = int stm32_adc_setup(void) { -#if defined(CONFIG_STM32H7_ADC1) || defined(CONFIG_STM32H7_ADC3) +#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC3) static bool initialized = false; struct adc_dev_s *adc; int ret; @@ -144,7 +144,7 @@ int stm32_adc_setup(void) if (!initialized) { #endif -#if defined(CONFIG_STM32H7_ADC1) +#if defined(CONFIG_STM32_ADC1) /* Configure the pins as analog inputs for the selected channels */ for (i = 0; i < ADC1_NCHANNELS; i++) @@ -157,7 +157,7 @@ int stm32_adc_setup(void) /* Call stm32_adcinitialize() to get an instance of the ADC interface */ - adc = stm32h7_adc_initialize(1, g_adc1_chanlist, ADC1_NCHANNELS); + adc = stm32_adc_initialize(1, g_adc1_chanlist, ADC1_NCHANNELS); if (adc == NULL) { aerr("ERROR: Failed to get ADC1 interface\n"); @@ -175,7 +175,7 @@ int stm32_adc_setup(void) devname[8]++; #endif -#if defined(CONFIG_STM32H7_ADC3) +#if defined(CONFIG_STM32_ADC3) /* Configure the pins as analog inputs for the selected channels */ for (i = 0; i < ADC3_NCHANNELS; i++) @@ -188,7 +188,7 @@ int stm32_adc_setup(void) /* Call stm32_adcinitialize() to get an instance of the ADC interface */ - adc = stm32h7_adc_initialize(3, g_adc3_chanlist, ADC3_NCHANNELS); + adc = stm32_adc_initialize(3, g_adc3_chanlist, ADC3_NCHANNELS); if (adc == NULL) { aerr("ERROR: Failed to get ADC3 interface\n"); @@ -205,7 +205,7 @@ int stm32_adc_setup(void) } #endif -#if defined(CONFIG_STM32H7_ADC1) || defined(CONFIG_STM32H7_ADC3) +#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC3) /* Now we are initialized */ initialized = true; @@ -217,5 +217,5 @@ int stm32_adc_setup(void) #endif } -#endif /* CONFIG_STM32H7_ADC1 || CONFIG_STM32H7_ADC2 || CONFIG_STM32H7_ADC3 */ +#endif /* CONFIG_STM32_ADC1 || CONFIG_STM32_ADC2 || CONFIG_STM32_ADC3 */ #endif /* CONFIG_ADC */ diff --git a/boards/arm/stm32h7/nucleo-h753zi/src/stm32_boot.c b/boards/arm/stm32h7/nucleo-h753zi/src/stm32_boot.c index 027cde005d767..417ba5b8bcdd4 100644 --- a/boards/arm/stm32h7/nucleo-h753zi/src/stm32_boot.c +++ b/boards/arm/stm32h7/nucleo-h753zi/src/stm32_boot.c @@ -58,7 +58,7 @@ void stm32_boardinitialize(void) board_autoled_initialize(); #endif -#if defined(CONFIG_STM32H7_OTGFS) || defined(CONFIG_STM32H7_HOST) +#if defined(CONFIG_STM32_OTGFS) || defined(CONFIG_STM32_HOST) /* Initialize USB */ stm32_usbinitialize(); diff --git a/boards/arm/stm32h7/nucleo-h753zi/src/stm32_bringup.c b/boards/arm/stm32h7/nucleo-h753zi/src/stm32_bringup.c index be030dcb4d2c8..805c1c4636885 100644 --- a/boards/arm/stm32h7/nucleo-h753zi/src/stm32_bringup.c +++ b/boards/arm/stm32h7/nucleo-h753zi/src/stm32_bringup.c @@ -36,11 +36,11 @@ #include #include -#ifdef CONFIG_STM32H7_OTGFS +#ifdef CONFIG_STM32_OTGFS #include "stm32_usbhost.h" #endif -#ifdef CONFIG_STM32H7_FDCAN +#ifdef CONFIG_STM32_FDCAN #include "stm32_fdcan_sock.h" #endif @@ -218,18 +218,18 @@ int stm32_bringup(void) #ifdef CONFIG_NETDEV_LATEINIT -# ifdef CONFIG_STM32H7_FDCAN1 +# ifdef CONFIG_STM32_FDCAN1 stm32_fdcansockinitialize(0); # endif -# ifdef CONFIG_STM32H7_FDCAN2 +# ifdef CONFIG_STM32_FDCAN2 stm32_fdcansockinitialize(1); # endif #endif #ifdef CONFIG_SENSORS_QENCODER -#ifdef CONFIG_STM32H7_TIM1_QE +#ifdef CONFIG_STM32_TIM1_QE ret = stm32_qencoder_initialize("/dev/qe0", 1); if (ret < 0) { @@ -240,7 +240,7 @@ int stm32_bringup(void) } #endif -#ifdef CONFIG_STM32H7_TIM3_QE +#ifdef CONFIG_STM32_TIM3_QE ret = stm32_qencoder_initialize("/dev/qe2", 3); if (ret < 0) { @@ -251,7 +251,7 @@ int stm32_bringup(void) } #endif -#ifdef CONFIG_STM32H7_TIM4_QE +#ifdef CONFIG_STM32_TIM4_QE ret = stm32_qencoder_initialize("/dev/qe3", 4); if (ret < 0) { diff --git a/boards/arm/stm32h7/nucleo-h753zi/src/stm32_pwm.c b/boards/arm/stm32h7/nucleo-h753zi/src/stm32_pwm.c index 24eae1bc1cf1d..8898b9655fa77 100644 --- a/boards/arm/stm32h7/nucleo-h753zi/src/stm32_pwm.c +++ b/boards/arm/stm32h7/nucleo-h753zi/src/stm32_pwm.c @@ -84,7 +84,7 @@ int stm32_pwm_setup(void) /* Register the PWM driver at "/dev/pwm0" */ - #if defined(CONFIG_STM32H7_TIM1_PWM) + #if defined(CONFIG_STM32_TIM1_PWM) ret = pwm_register("/dev/pwm0", pwm); if (ret < 0) { @@ -93,7 +93,7 @@ int stm32_pwm_setup(void) } #endif -#if defined(CONFIG_STM32H7_TIM3_PWM) +#if defined(CONFIG_STM32_TIM3_PWM) ret = pwm_register("/dev/pwm2", pwm); if (ret < 0) { diff --git a/boards/arm/stm32h7/nucleo-h753zi/src/stm32_reset.c b/boards/arm/stm32h7/nucleo-h753zi/src/stm32_reset.c deleted file mode 100644 index 5eb902c30fc6d..0000000000000 --- a/boards/arm/stm32h7/nucleo-h753zi/src/stm32_reset.c +++ /dev/null @@ -1,64 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32h7/nucleo-h753zi/src/stm32_reset.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#ifdef CONFIG_BOARDCTL_RESET - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_reset - * - * Description: - * Reset board. Support for this function is required by board-level - * logic if CONFIG_BOARDCTL_RESET is selected. - * - * Input Parameters: - * status - Status information provided with the reset event. This - * meaning of this status information is board-specific. If not - * used by a board, the value zero may be provided in calls to - * board_reset(). - * - * Returned Value: - * If this function returns, then it was not possible to power-off the - * board due to some constraints. The return value int this case is a - * board-specific reason for the failure to shutdown. - * - ****************************************************************************/ - -int board_reset(int status) -{ - up_systemreset(); - return 0; -} - -#endif /* CONFIG_BOARDCTL_RESET */ diff --git a/boards/arm/stm32h7/nucleo-h753zi/src/stm32_usb.c b/boards/arm/stm32h7/nucleo-h753zi/src/stm32_usb.c index 668f6ac2e232f..73ddf89178f30 100644 --- a/boards/arm/stm32h7/nucleo-h753zi/src/stm32_usb.c +++ b/boards/arm/stm32h7/nucleo-h753zi/src/stm32_usb.c @@ -45,7 +45,7 @@ #include "stm32_otg.h" #include "nucleo-h753zi.h" -#ifdef CONFIG_STM32H7_OTGFS +#ifdef CONFIG_STM32_OTGFS /**************************************************************************** * Pre-processor Definitions @@ -138,7 +138,7 @@ void stm32_usbinitialize(void) * Power On, and Overcurrent GPIOs */ -#ifdef CONFIG_STM32H7_OTGFS +#ifdef CONFIG_STM32_OTGFS stm32_configgpio(GPIO_OTGFS_VBUS); stm32_configgpio(GPIO_OTGFS_PWRON); stm32_configgpio(GPIO_OTGFS_OVER); diff --git a/boards/arm/stm32h7/openh743i/configs/composite_fs/defconfig b/boards/arm/stm32h7/openh743i/configs/composite_fs/defconfig index ad92a680c9987..8bca88575835d 100644 --- a/boards/arm/stm32h7/openh743i/configs/composite_fs/defconfig +++ b/boards/arm/stm32h7/openh743i/configs/composite_fs/defconfig @@ -11,6 +11,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="openh743i" CONFIG_ARCH_BOARD_OPENH743I=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H743II=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -75,9 +76,9 @@ CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_HSI48=y -CONFIG_STM32H7_OTGFS=y -CONFIG_STM32H7_SDMMC1=y +CONFIG_STM32_HSI48=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_SDMMC1=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USBDEV=y diff --git a/boards/arm/stm32h7/openh743i/configs/composite_hs/defconfig b/boards/arm/stm32h7/openh743i/configs/composite_hs/defconfig index 42eadf579ad14..5cf6dd2376c6b 100644 --- a/boards/arm/stm32h7/openh743i/configs/composite_hs/defconfig +++ b/boards/arm/stm32h7/openh743i/configs/composite_hs/defconfig @@ -11,6 +11,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="openh743i" CONFIG_ARCH_BOARD_OPENH743I=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H743II=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -72,11 +73,11 @@ CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_HSI48=y -CONFIG_STM32H7_OTGHS=y -CONFIG_STM32H7_OTGHS_EXTERNAL_ULPI=y -CONFIG_STM32H7_SDMMC1=y -CONFIG_STM32H7_SYSCFG_IOCOMPENSATION=y +CONFIG_STM32_HSI48=y +CONFIG_STM32_OTGHS=y +CONFIG_STM32_OTGHS_EXTERNAL_ULPI=y +CONFIG_STM32_SDMMC1=y +CONFIG_STM32_SYSCFG_IOCOMPENSATION=y CONFIG_SYSTEM_COMPOSITE=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 diff --git a/boards/arm/stm32h7/openh743i/configs/nsh/defconfig b/boards/arm/stm32h7/openh743i/configs/nsh/defconfig index 51e03a5d33f8d..e3de0edfcdef4 100644 --- a/boards/arm/stm32h7/openh743i/configs/nsh/defconfig +++ b/boards/arm/stm32h7/openh743i/configs/nsh/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="openh743i" CONFIG_ARCH_BOARD_OPENH743I=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H743II=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -42,7 +43,7 @@ CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_USART1=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32h7/openh743i/configs/usbdev_hs_host_fs/defconfig b/boards/arm/stm32h7/openh743i/configs/usbdev_hs_host_fs/defconfig index 5122941e7e509..6c37d27f4ad3a 100644 --- a/boards/arm/stm32h7/openh743i/configs/usbdev_hs_host_fs/defconfig +++ b/boards/arm/stm32h7/openh743i/configs/usbdev_hs_host_fs/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="openh743i" CONFIG_ARCH_BOARD_OPENH743I=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H743II=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -55,12 +56,12 @@ CONFIG_STACK_USAGE=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_HSI48=y -CONFIG_STM32H7_OTGFS=y -CONFIG_STM32H7_OTGFS_HOST=y -CONFIG_STM32H7_OTGHS=y -CONFIG_STM32H7_OTGHS_EXTERNAL_ULPI=y -CONFIG_STM32H7_SYSCFG_IOCOMPENSATION=y +CONFIG_STM32_HSI48=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_OTGFS_HOST=y +CONFIG_STM32_OTGHS=y +CONFIG_STM32_OTGHS_EXTERNAL_ULPI=y +CONFIG_STM32_SYSCFG_IOCOMPENSATION=y CONFIG_SYSTEM_CDCACM=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=32 diff --git a/boards/arm/stm32h7/openh743i/include/board.h b/boards/arm/stm32h7/openh743i/include/board.h index 99a5899c0a3dc..ac18190003e0a 100644 --- a/boards/arm/stm32h7/openh743i/include/board.h +++ b/boards/arm/stm32h7/openh743i/include/board.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32H7_OPENH743I_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32H7_OPENH743I_INCLUDE_BOARD_H +#ifndef __BOARDS_ARM_STM32_OPENH743I_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32_OPENH743I_INCLUDE_BOARD_H /**************************************************************************** * Included Files @@ -378,4 +378,4 @@ extern "C" #endif #endif /* __ASSEMBLY__ */ -#endif /* __BOARDS_ARM_STM32H7_OPENH743I_INCLUDE_BOARD_H */ +#endif /* __BOARDS_ARM_STM32_OPENH743I_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32h7/openh743i/src/CMakeLists.txt b/boards/arm/stm32h7/openh743i/src/CMakeLists.txt index d6e3a6040cbf4..7e8e6aa233421 100644 --- a/boards/arm/stm32h7/openh743i/src/CMakeLists.txt +++ b/boards/arm/stm32h7/openh743i/src/CMakeLists.txt @@ -22,7 +22,7 @@ set(SRCS stm32_boot.c stm32_bringup.c) -if(CONFIG_STM32H7_SDMMC) +if(CONFIG_STM32_SDMMC) list(APPEND SRCS stm32_sdmmc.c) endif() diff --git a/boards/arm/stm32h7/openh743i/src/Make.defs b/boards/arm/stm32h7/openh743i/src/Make.defs new file mode 100644 index 0000000000000..bd6094b33ab27 --- /dev/null +++ b/boards/arm/stm32h7/openh743i/src/Make.defs @@ -0,0 +1,47 @@ +############################################################################ +# boards/arm/stm32h7/openh743i/src/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +CSRCS = stm32_boot.c stm32_bringup.c + +ifeq ($(CONFIG_STM32_SDMMC),y) +CSRCS += stm32_sdmmc.c +endif + +ifeq ($(CONFIG_USBDEV),y) +CSRCS += stm32_usb.c +else ifeq ($(CONFIG_USBHOST),y) +CSRCS += stm32_usb.c +endif + +ifeq ($(CONFIG_USBMSC),y) +CSRCS += stm32_usbmsc.c +endif + +ifeq ($(CONFIG_USBDEV_COMPOSITE),y) +CSRCS += stm32_composite.c +endif + +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32h7/openh743i/src/Makefile b/boards/arm/stm32h7/openh743i/src/Makefile deleted file mode 100644 index eda04e7c3af25..0000000000000 --- a/boards/arm/stm32h7/openh743i/src/Makefile +++ /dev/null @@ -1,45 +0,0 @@ -############################################################################ -# boards/arm/stm32h7/openh743i/src/Makefile -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/Make.defs - -CSRCS = stm32_boot.c stm32_bringup.c - -ifeq ($(CONFIG_STM32H7_SDMMC),y) -CSRCS += stm32_sdmmc.c -endif - -ifeq ($(CONFIG_USBDEV),y) -CSRCS += stm32_usb.c -else ifeq ($(CONFIG_USBHOST),y) -CSRCS += stm32_usb.c -endif - -ifeq ($(CONFIG_USBMSC),y) -CSRCS += stm32_usbmsc.c -endif - -ifeq ($(CONFIG_USBDEV_COMPOSITE),y) -CSRCS += stm32_composite.c -endif - -include $(TOPDIR)/boards/Board.mk diff --git a/boards/arm/stm32h7/openh743i/src/openh743i.h b/boards/arm/stm32h7/openh743i/src/openh743i.h index 1645ce0118242..0bd3f2c1a9b06 100644 --- a/boards/arm/stm32h7/openh743i/src/openh743i.h +++ b/boards/arm/stm32h7/openh743i/src/openh743i.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32H7_OPENH743I_SRC_OPENH743I_H -#define __BOARDS_ARM_STM32H7_OPENH743I_SRC_OPENH743I_H +#ifndef __BOARDS_ARM_STM32_OPENH743I_SRC_OPENH743I_H +#define __BOARDS_ARM_STM32_OPENH743I_SRC_OPENH743I_H /**************************************************************************** * Included Files @@ -105,7 +105,7 @@ int stm32_bringup(void); * ****************************************************************************/ -#ifdef CONFIG_STM32H7_SDMMC +#ifdef CONFIG_STM32_SDMMC int stm32_sdio_initialize(void); #endif @@ -118,7 +118,7 @@ int stm32_sdio_initialize(void); * ****************************************************************************/ -#ifdef CONFIG_STM32H7_OTGFS +#ifdef CONFIG_STM32_OTGFS void weak_function stm32_usbinitialize(void); #endif @@ -136,4 +136,4 @@ void weak_function stm32_usbinitialize(void); int stm32_usbhost_initialize(void); #endif -#endif /* __BOARDS_ARM_STM32H7_OPENH743I_SRC_OPENH743I_H */ +#endif /* __BOARDS_ARM_STM32_OPENH743I_SRC_OPENH743I_H */ diff --git a/boards/arm/stm32h7/openh743i/src/stm32_boot.c b/boards/arm/stm32h7/openh743i/src/stm32_boot.c index df105a23b30aa..a6193210adae8 100644 --- a/boards/arm/stm32h7/openh743i/src/stm32_boot.c +++ b/boards/arm/stm32h7/openh743i/src/stm32_boot.c @@ -52,7 +52,7 @@ void stm32_boardinitialize(void) { -#if defined(CONFIG_STM32H7_OTGFS_HOST) || defined(CONFIG_STM32H7_OTGHS_HOST) +#if defined(CONFIG_STM32_OTGFS_HOST) || defined(CONFIG_STM32_OTGHS_HOST) /* Initialize USB */ stm32_usbinitialize(); diff --git a/boards/arm/stm32h7/openh743i/src/stm32_bringup.c b/boards/arm/stm32h7/openh743i/src/stm32_bringup.c index 1bf485416d91c..a9dbd9ae9e715 100644 --- a/boards/arm/stm32h7/openh743i/src/stm32_bringup.c +++ b/boards/arm/stm32h7/openh743i/src/stm32_bringup.c @@ -38,7 +38,7 @@ # include #endif -#ifdef CONFIG_STM32H7_OTGFS +#ifdef CONFIG_STM32_OTGFS # include "stm32_usbhost.h" #endif @@ -91,7 +91,7 @@ int stm32_bringup(void) usbdev_rndis_initialize(mac); #endif -#if defined(CONFIG_STM32H7_SDMMC) && !defined(CONFIG_CDCACM_CONSOLE) +#if defined(CONFIG_STM32_SDMMC) && !defined(CONFIG_CDCACM_CONSOLE) /* Initialize the SDIO block driver */ ret = stm32_sdio_initialize(); diff --git a/boards/arm/stm32h7/openh743i/src/stm32_sdmmc.c b/boards/arm/stm32h7/openh743i/src/stm32_sdmmc.c index 600ace9250ac7..eb8a354de6a78 100644 --- a/boards/arm/stm32h7/openh743i/src/stm32_sdmmc.c +++ b/boards/arm/stm32h7/openh743i/src/stm32_sdmmc.c @@ -45,13 +45,13 @@ /* Configuration ************************************************************/ -#ifndef CONFIG_STM32H7_SDMMC1 +#ifndef CONFIG_STM32_SDMMC1 # error SDMMC1 supported only #endif /* If IDMA is enabled, internal SRAM must be excluded from heap */ -#if CONFIG_MM_REGIONS > 1 && defined(CONFIG_STM32H7_SDMMC_IDMA) +#if CONFIG_MM_REGIONS > 1 && defined(CONFIG_STM32_SDMMC_IDMA) # error SDMMC1 with IDMA does not work CONFIG_MM_REGIONS > 1 #endif diff --git a/boards/arm/stm32h7/openh743i/src/stm32_usb.c b/boards/arm/stm32h7/openh743i/src/stm32_usb.c index 5e53687605cbd..59dbdf27b088c 100644 --- a/boards/arm/stm32h7/openh743i/src/stm32_usb.c +++ b/boards/arm/stm32h7/openh743i/src/stm32_usb.c @@ -44,7 +44,7 @@ * Pre-processor Definitions ****************************************************************************/ -#if defined(CONFIG_STM32H7_OTGFS_HOST) && defined(CONFIG_STM32H7_OTGHS_USBDEV) +#if defined(CONFIG_STM32_OTGFS_HOST) && defined(CONFIG_STM32_OTGHS_USBDEV) # ifndef CONFIG_OPENH743I_DISABLE_OTGFS_PWRON # error PWRON must be disabled for this configuration # endif @@ -121,7 +121,7 @@ void stm32_usbinitialize(void) * Power On, and Overcurrent GPIOs */ -#ifdef CONFIG_STM32H7_OTGFS +#ifdef CONFIG_STM32_OTGFS stm32_configgpio(GPIO_OTGFS_VBUS); stm32_configgpio(GPIO_OTGFS_PWRON); stm32_configgpio(GPIO_OTGFS_OVER); @@ -307,7 +307,7 @@ void stm32_usbsuspend(struct usbdev_s *dev, bool resume) uinfo("resume: %d\n", resume); } -#ifdef CONFIG_STM32H7_OTGHS_EXTERNAL_ULPI +#ifdef CONFIG_STM32_OTGHS_EXTERNAL_ULPI /**************************************************************************** * Name: stm32_usbulpireset * diff --git a/boards/arm/stm32h7/portenta-h7/configs/jumbo_cm7/defconfig b/boards/arm/stm32h7/portenta-h7/configs/jumbo_cm7/defconfig index c8778936d3ef9..f324baba7d729 100644 --- a/boards/arm/stm32h7/portenta-h7/configs/jumbo_cm7/defconfig +++ b/boards/arm/stm32h7/portenta-h7/configs/jumbo_cm7/defconfig @@ -10,6 +10,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="portenta-h7" CONFIG_ARCH_BOARD_PORTENTA_H7=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H747XI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -56,9 +57,9 @@ CONFIG_SIGNAL_FD=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_I2C1=y -CONFIG_STM32H7_I2C3=y -CONFIG_STM32H7_USART1=y +CONFIG_STM32_I2C1=y +CONFIG_STM32_I2C3=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_CLE=y CONFIG_SYSTEM_CUTERM=y CONFIG_SYSTEM_I2CTOOL=y diff --git a/boards/arm/stm32h7/portenta-h7/configs/nsh_cm7/defconfig b/boards/arm/stm32h7/portenta-h7/configs/nsh_cm7/defconfig index e3c035673f464..8b65fcd4526bd 100644 --- a/boards/arm/stm32h7/portenta-h7/configs/nsh_cm7/defconfig +++ b/boards/arm/stm32h7/portenta-h7/configs/nsh_cm7/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="portenta-h7" CONFIG_ARCH_BOARD_PORTENTA_H7=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H747XI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -42,6 +43,6 @@ CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_USART1=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32h7/portenta-h7/include/board.h b/boards/arm/stm32h7/portenta-h7/include/board.h index 362badffdbe01..14d214598f0d3 100644 --- a/boards/arm/stm32h7/portenta-h7/include/board.h +++ b/boards/arm/stm32h7/portenta-h7/include/board.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32H7_PORTENTA_H7_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32H7_PORTENTA_H7_INCLUDE_BOARD_H +#ifndef __BOARDS_ARM_STM32_PORTENTA_H7_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32_PORTENTA_H7_INCLUDE_BOARD_H /**************************************************************************** * Included Files @@ -360,4 +360,4 @@ extern "C" #endif #endif /* __ASSEMBLY__ */ -#endif /* __BOARDS_ARM_STM32H7_PORTENTA_H7_INCLUDE_BOARD_H */ +#endif /* __BOARDS_ARM_STM32_PORTENTA_H7_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32h7/portenta-h7/scripts/flash.ld b/boards/arm/stm32h7/portenta-h7/scripts/flash.ld index ad17d4464f008..b6cbb61a0c105 100644 --- a/boards/arm/stm32h7/portenta-h7/scripts/flash.ld +++ b/boards/arm/stm32h7/portenta-h7/scripts/flash.ld @@ -28,7 +28,7 @@ # define FLASH_START 0x08000000 #endif -#ifndef CONFIG_STM32H7_CORTEXM4_ENABLED +#ifndef CONFIG_STM32_CORTEXM4_ENABLED MEMORY { itcm (rwx) : ORIGIN = 0x00000000, LENGTH = 64K @@ -46,7 +46,7 @@ MEMORY MEMORY { itcm (rwx) : ORIGIN = 0x00000000, LENGTH = 64K - flash (rx) : ORIGIN = FLASH_START, LENGTH = CONFIG_STM32H7_CORTEXM7_FLASH_SIZE + flash (rx) : ORIGIN = FLASH_START, LENGTH = CONFIG_STM32_CORTEXM7_FLASH_SIZE dtcm1 (rwx) : ORIGIN = 0x20000000, LENGTH = 64K dtcm2 (rwx) : ORIGIN = 0x20010000, LENGTH = 64K sram (rwx) : ORIGIN = 0x24000000, LENGTH = 512K diff --git a/boards/arm/stm32h7/portenta-h7/scripts/flash_m4.ld b/boards/arm/stm32h7/portenta-h7/scripts/flash_m4.ld index c8122812f9406..8627f09500480 100644 --- a/boards/arm/stm32h7/portenta-h7/scripts/flash_m4.ld +++ b/boards/arm/stm32h7/portenta-h7/scripts/flash_m4.ld @@ -22,9 +22,9 @@ #include -#define STM32M4_FLASH_START (0x08000000 + CONFIG_STM32H7_CORTEXM7_FLASH_SIZE) +#define STM32M4_FLASH_START (0x08000000 + CONFIG_STM32_CORTEXM7_FLASH_SIZE) -#if CONFIG_STM32H7_CORTEXM7_FLASH_SIZE != 1048576 +#if CONFIG_STM32_CORTEXM7_FLASH_SIZE != 1048576 # error TODO: not supported yet - BCM4_ADD0 must be configured #endif @@ -34,7 +34,7 @@ MEMORY { flash (rx) : ORIGIN = STM32M4_FLASH_START, - LENGTH = (2048K - CONFIG_STM32H7_CORTEXM7_FLASH_SIZE) + LENGTH = (2048K - CONFIG_STM32_CORTEXM7_FLASH_SIZE) /* SRAM1 and SRAM2 */ diff --git a/boards/arm/stm32h7/portenta-h7/src/Make.defs b/boards/arm/stm32h7/portenta-h7/src/Make.defs new file mode 100644 index 0000000000000..90dbd1710370f --- /dev/null +++ b/boards/arm/stm32h7/portenta-h7/src/Make.defs @@ -0,0 +1,33 @@ +############################################################################ +# boards/arm/stm32h7/portenta-h7/src/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +CSRCS = stm32_boot.c stm32_bringup.c + +ifeq ($(CONFIG_ARCH_LEDS),y) +CSRCS += stm32_autoleds.c +endif + +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32h7/portenta-h7/src/Makefile b/boards/arm/stm32h7/portenta-h7/src/Makefile deleted file mode 100644 index adca38bed3e6c..0000000000000 --- a/boards/arm/stm32h7/portenta-h7/src/Makefile +++ /dev/null @@ -1,31 +0,0 @@ -############################################################################ -# boards/arm/stm32h7/portenta-h7/src/Makefile -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/Make.defs - -CSRCS = stm32_boot.c stm32_bringup.c - -ifeq ($(CONFIG_ARCH_LEDS),y) -CSRCS += stm32_autoleds.c -endif - -include $(TOPDIR)/boards/Board.mk diff --git a/boards/arm/stm32h7/portenta-h7/src/portenta-h7.h b/boards/arm/stm32h7/portenta-h7/src/portenta-h7.h index 157269188172e..a5672b1f46a31 100644 --- a/boards/arm/stm32h7/portenta-h7/src/portenta-h7.h +++ b/boards/arm/stm32h7/portenta-h7/src/portenta-h7.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32H7_PORTENTA_H7_SRC_PORTENTA_H7_H -#define __BOARDS_ARM_STM32H7_PORTENTA_H7_SRC_PORTENTA_H7_H +#ifndef __BOARDS_ARM_STM32_PORTENTA_H7_SRC_PORTENTA_H7_H +#define __BOARDS_ARM_STM32_PORTENTA_H7_SRC_PORTENTA_H7_H /**************************************************************************** * Included Files @@ -85,4 +85,4 @@ int stm32_bringup(void); -#endif /* __BOARDS_ARM_STM32H7_PORTENTA_H7_SRC_PORTENTA_H7_H */ +#endif /* __BOARDS_ARM_STM32_PORTENTA_H7_SRC_PORTENTA_H7_H */ diff --git a/boards/arm/stm32h7/portenta-h7/src/stm32_bringup.c b/boards/arm/stm32h7/portenta-h7/src/stm32_bringup.c index a61fab1bb6488..cfbcb8fec4cf6 100644 --- a/boards/arm/stm32h7/portenta-h7/src/stm32_bringup.c +++ b/boards/arm/stm32h7/portenta-h7/src/stm32_bringup.c @@ -85,16 +85,16 @@ static void stm32_i2c_register(int bus) #if defined(CONFIG_I2C) && defined(CONFIG_SYSTEM_I2CTOOL) static void stm32_i2ctool(void) { -#ifdef CONFIG_STM32H7_I2C1 +#ifdef CONFIG_STM32_I2C1 stm32_i2c_register(1); #endif -#ifdef CONFIG_STM32H7_I2C2 +#ifdef CONFIG_STM32_I2C2 stm32_i2c_register(2); #endif -#ifdef CONFIG_STM32H7_I2C3 +#ifdef CONFIG_STM32_I2C3 stm32_i2c_register(3); #endif -#ifdef CONFIG_STM32H7_I2C4 +#ifdef CONFIG_STM32_I2C4 stm32_i2c_register(4); #endif } diff --git a/boards/arm/stm32h7/stm32h745i-disco/configs/lvgl/defconfig b/boards/arm/stm32h7/stm32h745i-disco/configs/lvgl/defconfig index 5690c750d3736..e1284a69ff073 100644 --- a/boards/arm/stm32h7/stm32h745i-disco/configs/lvgl/defconfig +++ b/boards/arm/stm32h7/stm32h745i-disco/configs/lvgl/defconfig @@ -6,15 +6,16 @@ # modifications. # # CONFIG_STANDARD_SERIAL is not set -# CONFIG_STM32H7_CORTEXM4_ENABLED is not set -# CONFIG_STM32H7_FB_CMAP is not set -# CONFIG_STM32H7_LTDC_L1_CHROMAKEYEN is not set -# CONFIG_STM32H7_LTDC_L2 is not set +# CONFIG_STM32_CORTEXM4_ENABLED is not set +# CONFIG_STM32_FB_CMAP is not set +# CONFIG_STM32_LTDC_L1_CHROMAKEYEN is not set +# CONFIG_STM32_LTDC_L2 is not set CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32h745i-disco" CONFIG_ARCH_BOARD_STM32H745I_DISCO=y CONFIG_ARCH_BOARD_STM32H745I_DISCO_TOUCHSCREEN_SWAPXY=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H745XI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -65,15 +66,15 @@ CONFIG_SIG_DEFAULT=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_DMA1=y -CONFIG_STM32H7_DMA2=y -CONFIG_STM32H7_FMC=y -CONFIG_STM32H7_I2C4=y -CONFIG_STM32H7_LTDC=y -CONFIG_STM32H7_LTDC_FB_BASE=0x24020000 -CONFIG_STM32H7_LTDC_FB_SIZE=261120 -CONFIG_STM32H7_PWR_DIRECT_SMPS_SUPPLY=y -CONFIG_STM32H7_USART3=y +CONFIG_STM32_DMA1=y +CONFIG_STM32_DMA2=y +CONFIG_STM32_FMC=y +CONFIG_STM32_I2C4=y +CONFIG_STM32_LTDC=y +CONFIG_STM32_LTDC_FB_BASE=0x24020000 +CONFIG_STM32_LTDC_FB_SIZE=261120 +CONFIG_STM32_PWR_DIRECT_SMPS_SUPPLY=y +CONFIG_STM32_USART3=y CONFIG_SYSTEM_NSH=y CONFIG_TTY_SIGINT=y CONFIG_USART3_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32h7/stm32h745i-disco/configs/netnsh/defconfig b/boards/arm/stm32h7/stm32h745i-disco/configs/netnsh/defconfig index a8fe4e516efa7..ea4a80f74f384 100644 --- a/boards/arm/stm32h7/stm32h745i-disco/configs/netnsh/defconfig +++ b/boards/arm/stm32h7/stm32h745i-disco/configs/netnsh/defconfig @@ -6,11 +6,12 @@ # modifications. # # CONFIG_STANDARD_SERIAL is not set -# CONFIG_STM32H7_CORTEXM4_ENABLED is not set +# CONFIG_STM32_CORTEXM4_ENABLED is not set CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32h745i-disco" CONFIG_ARCH_BOARD_STM32H745I_DISCO=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H745XI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -63,19 +64,19 @@ CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_ETHMAC=y -CONFIG_STM32H7_FMC=y -CONFIG_STM32H7_MII=y -CONFIG_STM32H7_PHYADDR=1 -CONFIG_STM32H7_PHYSR=31 -CONFIG_STM32H7_PHYSR_100FD=0x0018 -CONFIG_STM32H7_PHYSR_100HD=0x0008 -CONFIG_STM32H7_PHYSR_10FD=0x0014 -CONFIG_STM32H7_PHYSR_10HD=0x0004 -CONFIG_STM32H7_PHYSR_ALTCONFIG=y -CONFIG_STM32H7_PHYSR_ALTMODE=0x001c -CONFIG_STM32H7_PWR_DIRECT_SMPS_SUPPLY=y -CONFIG_STM32H7_USART3=y +CONFIG_STM32_ETHMAC=y +CONFIG_STM32_FMC=y +CONFIG_STM32_MII=y +CONFIG_STM32_PHYADDR=1 +CONFIG_STM32_PHYSR=31 +CONFIG_STM32_PHYSR_100FD=0x0018 +CONFIG_STM32_PHYSR_100HD=0x0008 +CONFIG_STM32_PHYSR_10FD=0x0014 +CONFIG_STM32_PHYSR_10HD=0x0004 +CONFIG_STM32_PHYSR_ALTCONFIG=y +CONFIG_STM32_PHYSR_ALTMODE=0x001c +CONFIG_STM32_PWR_DIRECT_SMPS_SUPPLY=y +CONFIG_STM32_USART3=y CONFIG_SYSTEM_DHCPC_RENEW=y CONFIG_SYSTEM_NSH=y CONFIG_SYSTEM_PING=y diff --git a/boards/arm/stm32h7/stm32h745i-disco/configs/nsh/defconfig b/boards/arm/stm32h7/stm32h745i-disco/configs/nsh/defconfig index c138b61ca0154..28dcea36030b6 100644 --- a/boards/arm/stm32h7/stm32h745i-disco/configs/nsh/defconfig +++ b/boards/arm/stm32h7/stm32h745i-disco/configs/nsh/defconfig @@ -8,11 +8,12 @@ # CONFIG_NSH_DISABLE_IFCONFIG is not set # CONFIG_NSH_DISABLE_PS is not set # CONFIG_STANDARD_SERIAL is not set -# CONFIG_STM32H7_CORTEXM4_ENABLED is not set +# CONFIG_STM32_CORTEXM4_ENABLED is not set CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32h745i-disco" CONFIG_ARCH_BOARD_STM32H745I_DISCO=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H745XI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -41,9 +42,9 @@ CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_FMC=y -CONFIG_STM32H7_PWR_DIRECT_SMPS_SUPPLY=y -CONFIG_STM32H7_USART3=y +CONFIG_STM32_FMC=y +CONFIG_STM32_PWR_DIRECT_SMPS_SUPPLY=y +CONFIG_STM32_USART3=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART3_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32h7/stm32h745i-disco/configs/nsh_cm4/defconfig b/boards/arm/stm32h7/stm32h745i-disco/configs/nsh_cm4/defconfig index b1c3acf72f095..d4f0bbb49a957 100644 --- a/boards/arm/stm32h7/stm32h745i-disco/configs/nsh_cm4/defconfig +++ b/boards/arm/stm32h7/stm32h745i-disco/configs/nsh_cm4/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32h745i-disco" CONFIG_ARCH_BOARD_STM32H745I_DISCO=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H745XI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM4=y @@ -38,9 +39,9 @@ CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_FMC=y -CONFIG_STM32H7_PWR_DIRECT_SMPS_SUPPLY=y -CONFIG_STM32H7_UART7=y +CONFIG_STM32_FMC=y +CONFIG_STM32_PWR_DIRECT_SMPS_SUPPLY=y +CONFIG_STM32_UART7=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_UART7_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32h7/stm32h745i-disco/configs/nsh_cm4_rptun/defconfig b/boards/arm/stm32h7/stm32h745i-disco/configs/nsh_cm4_rptun/defconfig index d3dd2789880b0..35697fcdf3714 100644 --- a/boards/arm/stm32h7/stm32h745i-disco/configs/nsh_cm4_rptun/defconfig +++ b/boards/arm/stm32h7/stm32h745i-disco/configs/nsh_cm4_rptun/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32h745i-disco" CONFIG_ARCH_BOARD_STM32H745I_DISCO=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H745XI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM4=y @@ -43,7 +44,7 @@ CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_FMC=y -CONFIG_STM32H7_PWR_DIRECT_SMPS_SUPPLY=y +CONFIG_STM32_FMC=y +CONFIG_STM32_PWR_DIRECT_SMPS_SUPPLY=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 diff --git a/boards/arm/stm32h7/stm32h745i-disco/configs/nsh_cm7/defconfig b/boards/arm/stm32h7/stm32h745i-disco/configs/nsh_cm7/defconfig index e02a55c70a6d2..dcee32242f047 100644 --- a/boards/arm/stm32h7/stm32h745i-disco/configs/nsh_cm7/defconfig +++ b/boards/arm/stm32h7/stm32h745i-disco/configs/nsh_cm7/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32h745i-disco" CONFIG_ARCH_BOARD_STM32H745I_DISCO=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H745XI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -42,9 +43,9 @@ CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_FMC=y -CONFIG_STM32H7_PWR_DIRECT_SMPS_SUPPLY=y -CONFIG_STM32H7_USART3=y +CONFIG_STM32_FMC=y +CONFIG_STM32_PWR_DIRECT_SMPS_SUPPLY=y +CONFIG_STM32_USART3=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART3_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32h7/stm32h745i-disco/configs/nsh_cm7_rptun/defconfig b/boards/arm/stm32h7/stm32h745i-disco/configs/nsh_cm7_rptun/defconfig index 52f90e5c3f8c3..9ee4b9596d6ab 100644 --- a/boards/arm/stm32h7/stm32h745i-disco/configs/nsh_cm7_rptun/defconfig +++ b/boards/arm/stm32h7/stm32h745i-disco/configs/nsh_cm7_rptun/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32h745i-disco" CONFIG_ARCH_BOARD_STM32H745I_DISCO=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H745XI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -48,9 +49,9 @@ CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_FMC=y -CONFIG_STM32H7_PWR_DIRECT_SMPS_SUPPLY=y -CONFIG_STM32H7_USART3=y +CONFIG_STM32_FMC=y +CONFIG_STM32_PWR_DIRECT_SMPS_SUPPLY=y +CONFIG_STM32_USART3=y CONFIG_SYSTEM_CUTERM=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 diff --git a/boards/arm/stm32h7/stm32h745i-disco/configs/touchtest/defconfig b/boards/arm/stm32h7/stm32h745i-disco/configs/touchtest/defconfig index d187e442ce272..665a08ff3b2ac 100644 --- a/boards/arm/stm32h7/stm32h745i-disco/configs/touchtest/defconfig +++ b/boards/arm/stm32h7/stm32h745i-disco/configs/touchtest/defconfig @@ -6,12 +6,13 @@ # modifications. # # CONFIG_STANDARD_SERIAL is not set -# CONFIG_STM32H7_CORTEXM4_ENABLED is not set +# CONFIG_STM32_CORTEXM4_ENABLED is not set CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32h745i-disco" CONFIG_ARCH_BOARD_STM32H745I_DISCO=y CONFIG_ARCH_BOARD_STM32H745I_DISCO_TOUCHSCREEN_SWAPXY=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H745XI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -51,10 +52,10 @@ CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_FMC=y -CONFIG_STM32H7_I2C4=y -CONFIG_STM32H7_PWR_DIRECT_SMPS_SUPPLY=y -CONFIG_STM32H7_USART3=y +CONFIG_STM32_FMC=y +CONFIG_STM32_I2C4=y +CONFIG_STM32_PWR_DIRECT_SMPS_SUPPLY=y +CONFIG_STM32_USART3=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART3_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32h7/stm32h745i-disco/include/board.h b/boards/arm/stm32h7/stm32h745i-disco/include/board.h index 1593c65b03275..51fa696247120 100644 --- a/boards/arm/stm32h7/stm32h745i-disco/include/board.h +++ b/boards/arm/stm32h7/stm32h745i-disco/include/board.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32H7_STM32H745I_DISCO_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32H7_STM32H745I_DISCO_INCLUDE_BOARD_H +#ifndef __BOARDS_ARM_STM32_STM32H745I_DISCO_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32_STM32H745I_DISCO_INCLUDE_BOARD_H /**************************************************************************** * Included Files @@ -343,7 +343,7 @@ #define BOARD_FMC_CLK RCC_D1CCIPR_FMCSEL_HCLK -#if CONFIG_STM32H7_FMC +#if CONFIG_STM32_FMC # define FMC_SDCLK_FREQUENCY (STM32_HCLK_FREQUENCY / 2) # if FMC_SDCLK_FREQUENCY > 100000000 # error "FMC SDRAM settings need to be adjusted for a higher FMC_SDCLK frequency" @@ -614,4 +614,4 @@ extern "C" #endif #endif /* __ASSEMBLY__ */ -#endif /* __BOARDS_ARM_STM32H7_STM32H745I_DISCO_INCLUDE_BOARD_H */ +#endif /* __BOARDS_ARM_STM32_STM32H745I_DISCO_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32h7/stm32h745i-disco/scripts/flash.ld b/boards/arm/stm32h7/stm32h745i-disco/scripts/flash.ld index e0f982d7c648d..3ed5b169c6c90 100644 --- a/boards/arm/stm32h7/stm32h745i-disco/scripts/flash.ld +++ b/boards/arm/stm32h7/stm32h745i-disco/scripts/flash.ld @@ -97,7 +97,7 @@ #include -#ifndef CONFIG_STM32H7_CORTEXM4_ENABLED +#ifndef CONFIG_STM32_CORTEXM4_ENABLED MEMORY { itcm (rwx) : ORIGIN = 0x00000000, LENGTH = 64K @@ -115,7 +115,7 @@ MEMORY MEMORY { itcm (rwx) : ORIGIN = 0x00000000, LENGTH = 64K - flash (rx) : ORIGIN = 0x08000000, LENGTH = CONFIG_STM32H7_CORTEXM7_FLASH_SIZE + flash (rx) : ORIGIN = 0x08000000, LENGTH = CONFIG_STM32_CORTEXM7_FLASH_SIZE dtcm1 (rwx) : ORIGIN = 0x20000000, LENGTH = 64K dtcm2 (rwx) : ORIGIN = 0x20010000, LENGTH = 64K sram (rwx) : ORIGIN = 0x24000000, LENGTH = 512K @@ -192,7 +192,7 @@ SECTIONS _ebss = ABSOLUTE(.); } > sram -#ifdef CONFIG_STM32H7_CORTEXM4_ENABLED +#ifdef CONFIG_STM32_CORTEXM4_ENABLED .shmem (NOLOAD): { . = ALIGN(4); diff --git a/boards/arm/stm32h7/stm32h745i-disco/scripts/flash_m4.ld b/boards/arm/stm32h7/stm32h745i-disco/scripts/flash_m4.ld index 74787002507c2..98296d3ffd1f5 100644 --- a/boards/arm/stm32h7/stm32h745i-disco/scripts/flash_m4.ld +++ b/boards/arm/stm32h7/stm32h745i-disco/scripts/flash_m4.ld @@ -22,9 +22,9 @@ #include -#define STM32M4_FLASH_START (0x08000000 + CONFIG_STM32H7_CORTEXM7_FLASH_SIZE) +#define STM32M4_FLASH_START (0x08000000 + CONFIG_STM32_CORTEXM7_FLASH_SIZE) -#if CONFIG_STM32H7_CORTEXM7_FLASH_SIZE != 1048576 +#if CONFIG_STM32_CORTEXM7_FLASH_SIZE != 1048576 # error TODO: not supported yet - BCM4_ADD0 must be configured #endif @@ -34,7 +34,7 @@ MEMORY { flash (rx) : ORIGIN = STM32M4_FLASH_START, - LENGTH = (2048K - CONFIG_STM32H7_CORTEXM7_FLASH_SIZE) + LENGTH = (2048K - CONFIG_STM32_CORTEXM7_FLASH_SIZE) /* SRAM1 and SRAM2 */ diff --git a/boards/arm/stm32h7/stm32h745i-disco/src/CMakeLists.txt b/boards/arm/stm32h7/stm32h745i-disco/src/CMakeLists.txt index 424170bc1a1db..276181929cc37 100644 --- a/boards/arm/stm32h7/stm32h745i-disco/src/CMakeLists.txt +++ b/boards/arm/stm32h7/stm32h745i-disco/src/CMakeLists.txt @@ -28,7 +28,7 @@ else() list(APPEND SRCS stm32_userleds.c) endif() -if(CONFIG_STM32H7_OTGFS) +if(CONFIG_STM32_OTGFS) list(APPEND SRCS stm32_usb.c) endif() @@ -36,15 +36,11 @@ if(CONFIG_TESTING_OSTEST) list(APPEND SRCS stm32_ostest.c) endif() -if(CONFIG_BOARDCTL_RESET) - list(APPEND SRCS stm32_reset.c) -endif() - if(CONFIG_INPUT_FT5X06) list(APPEND SRCS stm32_ft5x06.c) endif() -if(CONFIG_STM32H7_LTDC) +if(CONFIG_STM32_LTDC) list(APPEND SRCS stm32_lcd.c) endif() diff --git a/boards/arm/stm32h7/stm32h745i-disco/src/Make.defs b/boards/arm/stm32h7/stm32h745i-disco/src/Make.defs new file mode 100644 index 0000000000000..dfa13ad3ab285 --- /dev/null +++ b/boards/arm/stm32h7/stm32h745i-disco/src/Make.defs @@ -0,0 +1,51 @@ +############################################################################ +# boards/arm/stm32h7/stm32h745i-disco/src/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +CSRCS = stm32_boot.c stm32_bringup.c + +ifeq ($(CONFIG_ARCH_LEDS),y) +CSRCS += stm32_autoleds.c +else +CSRCS += stm32_userleds.c +endif + +ifeq ($(CONFIG_STM32_OTGFS),y) +CSRCS += stm32_usb.c +endif + +ifeq ($(CONFIG_TESTING_OSTEST),y) +CSRCS += stm32_ostest.c +endif + +ifeq ($(CONFIG_INPUT_FT5X06),y) +CSRCS += stm32_ft5x06.c +endif + +ifeq ($(CONFIG_STM32_LTDC),y) +CSRCS += stm32_lcd.c +endif + +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32h7/stm32h745i-disco/src/Makefile b/boards/arm/stm32h7/stm32h745i-disco/src/Makefile deleted file mode 100644 index 59db9b7cd6a76..0000000000000 --- a/boards/arm/stm32h7/stm32h745i-disco/src/Makefile +++ /dev/null @@ -1,53 +0,0 @@ -############################################################################ -# boards/arm/stm32h7/stm32h745i-disco/src/Makefile -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/Make.defs - -CSRCS = stm32_boot.c stm32_bringup.c - -ifeq ($(CONFIG_ARCH_LEDS),y) -CSRCS += stm32_autoleds.c -else -CSRCS += stm32_userleds.c -endif - -ifeq ($(CONFIG_STM32H7_OTGFS),y) -CSRCS += stm32_usb.c -endif - -ifeq ($(CONFIG_TESTING_OSTEST),y) -CSRCS += stm32_ostest.c -endif - -ifeq ($(CONFIG_BOARDCTL_RESET),y) -CSRCS += stm32_reset.c -endif - -ifeq ($(CONFIG_INPUT_FT5X06),y) -CSRCS += stm32_ft5x06.c -endif - -ifeq ($(CONFIG_STM32H7_LTDC),y) -CSRCS += stm32_lcd.c -endif - -include $(TOPDIR)/boards/Board.mk diff --git a/boards/arm/stm32h7/stm32h745i-disco/src/stm32_boot.c b/boards/arm/stm32h7/stm32h745i-disco/src/stm32_boot.c index 24b1520287482..786f655db5312 100644 --- a/boards/arm/stm32h7/stm32h745i-disco/src/stm32_boot.c +++ b/boards/arm/stm32h7/stm32h745i-disco/src/stm32_boot.c @@ -56,7 +56,7 @@ void stm32_boardinitialize(void) board_autoled_initialize(); #endif -#if defined(CONFIG_STM32H7_OTGFS) || defined(CONFIG_STM32H7_HOST) +#if defined(CONFIG_STM32_OTGFS) || defined(CONFIG_STM32_HOST) /* Initialize USB */ stm32_usbinitialize(); diff --git a/boards/arm/stm32h7/stm32h745i-disco/src/stm32_bringup.c b/boards/arm/stm32h7/stm32h745i-disco/src/stm32_bringup.c index 5af6ac7f31f97..def80baa81051 100644 --- a/boards/arm/stm32h7/stm32h745i-disco/src/stm32_bringup.c +++ b/boards/arm/stm32h7/stm32h745i-disco/src/stm32_bringup.c @@ -35,7 +35,7 @@ #include #include -#ifdef CONFIG_STM32H7_OTGFS +#ifdef CONFIG_STM32_OTGFS #include "stm32_usbhost.h" #endif diff --git a/boards/arm/stm32h7/stm32h745i-disco/src/stm32_ft5x06.c b/boards/arm/stm32h7/stm32h745i-disco/src/stm32_ft5x06.c index df62ee84f7dbb..639db95d733a7 100644 --- a/boards/arm/stm32h7/stm32h745i-disco/src/stm32_ft5x06.c +++ b/boards/arm/stm32h7/stm32h745i-disco/src/stm32_ft5x06.c @@ -49,8 +49,8 @@ # error "FT5x06 support requires CONFIG_INPUT" #endif -#ifndef CONFIG_STM32H7_I2C4 -# error "FT5x06 support requires CONFIG_STM32H7_I2C4" +#ifndef CONFIG_STM32_I2C4 +# error "FT5x06 support requires CONFIG_STM32_I2C4" #endif #ifndef CONFIG_FT5X06_I2CDEV diff --git a/boards/arm/stm32h7/stm32h745i-disco/src/stm32_lcd.c b/boards/arm/stm32h7/stm32h745i-disco/src/stm32_lcd.c index 7a5b17ad617f9..eb02f937d6e27 100644 --- a/boards/arm/stm32h7/stm32h745i-disco/src/stm32_lcd.c +++ b/boards/arm/stm32h7/stm32h745i-disco/src/stm32_lcd.c @@ -39,7 +39,7 @@ #include "stm32h745i_disco.h" -#ifdef CONFIG_STM32H7_LTDC +#ifdef CONFIG_STM32_LTDC /**************************************************************************** * Public Functions ****************************************************************************/ diff --git a/boards/arm/stm32h7/stm32h745i-disco/src/stm32_reset.c b/boards/arm/stm32h7/stm32h745i-disco/src/stm32_reset.c deleted file mode 100644 index ed84aebc4db21..0000000000000 --- a/boards/arm/stm32h7/stm32h745i-disco/src/stm32_reset.c +++ /dev/null @@ -1,64 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32h7/stm32h745i-disco/src/stm32_reset.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#ifdef CONFIG_BOARDCTL_RESET - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_reset - * - * Description: - * Reset board. Support for this function is required by board-level - * logic if CONFIG_BOARDCTL_RESET is selected. - * - * Input Parameters: - * status - Status information provided with the reset event. This - * meaning of this status information is board-specific. If not - * used by a board, the value zero may be provided in calls to - * board_reset(). - * - * Returned Value: - * If this function returns, then it was not possible to power-off the - * board due to some constraints. The return value int this case is a - * board-specific reason for the failure to shutdown. - * - ****************************************************************************/ - -int board_reset(int status) -{ - up_systemreset(); - return 0; -} - -#endif /* CONFIG_BOARDCTL_RESET */ diff --git a/boards/arm/stm32h7/stm32h745i-disco/src/stm32_usb.c b/boards/arm/stm32h7/stm32h745i-disco/src/stm32_usb.c index d08defcdbc5ad..07f43943a3e68 100644 --- a/boards/arm/stm32h7/stm32h745i-disco/src/stm32_usb.c +++ b/boards/arm/stm32h7/stm32h745i-disco/src/stm32_usb.c @@ -45,7 +45,7 @@ #include "stm32h745i_disco.h" -#ifdef CONFIG_STM32H7_OTGFS +#ifdef CONFIG_STM32_OTGFS /**************************************************************************** * Pre-processor Definitions @@ -138,7 +138,7 @@ void stm32_usbinitialize(void) * Power On, and Overcurrent GPIOs */ -#ifdef CONFIG_STM32H7_OTGFS +#ifdef CONFIG_STM32_OTGFS stm32_configgpio(GPIO_OTGFS_VBUS); stm32_configgpio(GPIO_OTGFS_PWRON); stm32_configgpio(GPIO_OTGFS_OVER); diff --git a/boards/arm/stm32h7/stm32h745i-disco/src/stm32h745i_disco.h b/boards/arm/stm32h7/stm32h745i-disco/src/stm32h745i_disco.h index 57ef2b05e63b0..e432a122d3073 100644 --- a/boards/arm/stm32h7/stm32h745i-disco/src/stm32h745i_disco.h +++ b/boards/arm/stm32h7/stm32h745i-disco/src/stm32h745i_disco.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32H7_STM32H745I_DISCO_SRC_STM32H745I_DISCO_H -#define __BOARDS_ARM_STM32H7_STM32H745I_DISCO_SRC_STM32H745I_DISCO_H +#ifndef __BOARDS_ARM_STM32_STM32H745I_DISCO_SRC_STM32H745I_DISCO_H +#define __BOARDS_ARM_STM32_STM32H745I_DISCO_SRC_STM32H745I_DISCO_H /**************************************************************************** * Included Files @@ -44,7 +44,7 @@ /* Can't support USB host or device features if USB OTG FS is not enabled */ -#ifndef CONFIG_STM32H7_OTGFS +#ifndef CONFIG_STM32_OTGFS # undef HAVE_USBDEV # undef HAVE_USBHOST #endif @@ -184,7 +184,7 @@ int stm32_bringup(void); * ****************************************************************************/ -#ifdef CONFIG_STM32H7_OTGFS +#ifdef CONFIG_STM32_OTGFS void weak_function stm32_usbinitialize(void); #endif @@ -198,7 +198,7 @@ void weak_function stm32_usbinitialize(void); * ****************************************************************************/ -#if defined(CONFIG_STM32H7_OTGFS) && defined(CONFIG_USBHOST) +#if defined(CONFIG_STM32_OTGFS) && defined(CONFIG_USBHOST) int stm32_usbhost_initialize(void); #endif @@ -216,4 +216,4 @@ int stm32_usbhost_initialize(void); int stm32_tsc_setup(int minor); #endif -#endif /* __BOARDS_ARM_STM32H7_STM32H745I_DISCO_SRC_STM32H745I_DISCO_H */ +#endif /* __BOARDS_ARM_STM32_STM32H745I_DISCO_SRC_STM32H745I_DISCO_H */ diff --git a/boards/arm/stm32h7/stm32h747i-disco/configs/nsh/defconfig b/boards/arm/stm32h7/stm32h747i-disco/configs/nsh/defconfig index 43a7a87143ca3..3ddf480334a8c 100644 --- a/boards/arm/stm32h7/stm32h747i-disco/configs/nsh/defconfig +++ b/boards/arm/stm32h7/stm32h747i-disco/configs/nsh/defconfig @@ -8,11 +8,12 @@ # CONFIG_NSH_DISABLE_IFCONFIG is not set # CONFIG_NSH_DISABLE_PS is not set # CONFIG_STANDARD_SERIAL is not set -# CONFIG_STM32H7_CORTEXM4_ENABLED is not set +# CONFIG_STM32_CORTEXM4_ENABLED is not set CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32h747i-disco" CONFIG_ARCH_BOARD_STM32H747I_DISCO=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H747XI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -44,7 +45,7 @@ CONFIG_SPI=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_USART1=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32h7/stm32h747i-disco/include/board.h b/boards/arm/stm32h7/stm32h747i-disco/include/board.h index 2eeaba7d62ce8..54701cc1ac72d 100644 --- a/boards/arm/stm32h7/stm32h747i-disco/include/board.h +++ b/boards/arm/stm32h7/stm32h747i-disco/include/board.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32H7_STM32H747I_DISCO_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32H7_STM32H747I_DISCO_INCLUDE_BOARD_H +#ifndef __BOARDS_ARM_STM32_STM32H747I_DISCO_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32_STM32H747I_DISCO_INCLUDE_BOARD_H /**************************************************************************** * Included Files @@ -471,4 +471,4 @@ extern "C" #endif #endif /* __ASSEMBLY__ */ -#endif /* __BOARDS_ARM_STM32H7_STM32H747I_DISCO_INCLUDE_BOARD_H */ +#endif /* __BOARDS_ARM_STM32_STM32H747I_DISCO_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32h7/stm32h747i-disco/src/CMakeLists.txt b/boards/arm/stm32h7/stm32h747i-disco/src/CMakeLists.txt index 2aff1364c448c..4583b43c5e703 100644 --- a/boards/arm/stm32h7/stm32h747i-disco/src/CMakeLists.txt +++ b/boards/arm/stm32h7/stm32h747i-disco/src/CMakeLists.txt @@ -36,11 +36,11 @@ if(CONFIG_ARCH_BUTTONS) list(APPEND SRCS stm32_buttons.c) endif() -if(CONFIG_STM32H7_SPI) +if(CONFIG_STM32_SPI) list(APPEND SRCS stm32_spi.c) endif() -if(CONFIG_STM32H7_OTGHS) +if(CONFIG_STM32_OTGHS) list(APPEND SRCS stm32_usb.c) endif() @@ -48,7 +48,7 @@ if(CONFIG_BOARDCTL_UNIQUEID) list(APPEND SRCS stm32_uid.c) endif() -if(CONFIG_STM32H7_SDMMC) +if(CONFIG_STM32_SDMMC) list(APPEND SRCS stm32_sdmmc.c) endif() diff --git a/boards/arm/stm32h7/stm32h747i-disco/src/Make.defs b/boards/arm/stm32h7/stm32h747i-disco/src/Make.defs new file mode 100644 index 0000000000000..d25798a6cbeb8 --- /dev/null +++ b/boards/arm/stm32h7/stm32h747i-disco/src/Make.defs @@ -0,0 +1,63 @@ +############################################################################ +# boards/arm/stm32h7/stm32h747i-disco/src/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +CSRCS = stm32_boot.c stm32_bringup.c + +ifeq ($(CONFIG_ADC),y) +CSRCS += stm32_adc.c +endif + +ifeq ($(CONFIG_ARCH_LEDS),y) +CSRCS += stm32_autoleds.c +else +CSRCS += stm32_userleds.c +endif + +ifeq ($(CONFIG_ARCH_BUTTONS),y) +CSRCS += stm32_buttons.c +endif + +ifeq ($(CONFIG_STM32_SPI),y) +CSRCS += stm32_spi.c +endif + +ifeq ($(CONFIG_STM32_OTGHS),y) +CSRCS += stm32_usb.c +endif + +ifeq ($(CONFIG_BOARDCTL_UNIQUEID),y) +CSRCS += stm32_uid.c +endif + +ifeq ($(CONFIG_STM32_SDMMC),y) +CSRCS += stm32_sdmmc.c +endif + +ifeq ($(CONFIG_FAT_DMAMEMORY),y) +CSRCS += stm32_dma_alloc.c +endif + +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32h7/stm32h747i-disco/src/Makefile b/boards/arm/stm32h7/stm32h747i-disco/src/Makefile deleted file mode 100644 index 788e0f0d91f20..0000000000000 --- a/boards/arm/stm32h7/stm32h747i-disco/src/Makefile +++ /dev/null @@ -1,61 +0,0 @@ -############################################################################ -# boards/arm/stm32h7/stm32h747i-disco/src/Makefile -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/Make.defs - -CSRCS = stm32_boot.c stm32_bringup.c - -ifeq ($(CONFIG_ADC),y) -CSRCS += stm32_adc.c -endif - -ifeq ($(CONFIG_ARCH_LEDS),y) -CSRCS += stm32_autoleds.c -else -CSRCS += stm32_userleds.c -endif - -ifeq ($(CONFIG_ARCH_BUTTONS),y) -CSRCS += stm32_buttons.c -endif - -ifeq ($(CONFIG_STM32H7_SPI),y) -CSRCS += stm32_spi.c -endif - -ifeq ($(CONFIG_STM32H7_OTGHS),y) -CSRCS += stm32_usb.c -endif - -ifeq ($(CONFIG_BOARDCTL_UNIQUEID),y) -CSRCS += stm32_uid.c -endif - -ifeq ($(CONFIG_STM32H7_SDMMC),y) -CSRCS += stm32_sdmmc.c -endif - -ifeq ($(CONFIG_FAT_DMAMEMORY),y) -CSRCS += stm32_dma_alloc.c -endif - -include $(TOPDIR)/boards/Board.mk diff --git a/boards/arm/stm32h7/stm32h747i-disco/src/stm32_adc.c b/boards/arm/stm32h7/stm32h747i-disco/src/stm32_adc.c index 43d90ea1c5857..de53c2b874209 100644 --- a/boards/arm/stm32h7/stm32h747i-disco/src/stm32_adc.c +++ b/boards/arm/stm32h7/stm32h747i-disco/src/stm32_adc.c @@ -48,9 +48,9 @@ /* Up to 3 ADC interfaces are supported */ -#if defined(CONFIG_STM32H7_ADC1) || defined(CONFIG_STM32H7_ADC2) || \ - defined(CONFIG_STM32H7_ADC3) -#ifndef CONFIG_STM32H7_ADC1 +#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) || \ + defined(CONFIG_STM32_ADC3) +#ifndef CONFIG_STM32_ADC1 # warning "Channel information only available for ADC1" #endif @@ -63,7 +63,7 @@ * Private Data ****************************************************************************/ -#ifdef CONFIG_STM32H7_ADC1 +#ifdef CONFIG_STM32_ADC1 /* Identifying number of each ADC channel: Variable Resistor. * * ADC1: {5, 10, 12, 13, 15}; @@ -87,7 +87,7 @@ static const uint32_t g_adc1_pinlist[ADC1_NCHANNELS] = }; #endif -#ifdef CONFIG_STM32H7_ADC3 +#ifdef CONFIG_STM32_ADC3 /* Identifying number of each ADC channel: Variable Resistor. * * ADC3: {6,}; @@ -124,7 +124,7 @@ static const uint32_t g_adc3_pinlist[ADC3_NCHANNELS] = int stm32_adc_setup(void) { -#if defined(CONFIG_STM32H7_ADC1) || defined(CONFIG_STM32H7_ADC3) +#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC3) static bool initialized = false; struct adc_dev_s *adc; int ret; @@ -136,7 +136,7 @@ int stm32_adc_setup(void) if (!initialized) { #endif -#if defined(CONFIG_STM32H7_ADC1) +#if defined(CONFIG_STM32_ADC1) /* Configure the pins as analog inputs for the selected channels */ for (i = 0; i < ADC1_NCHANNELS; i++) @@ -149,7 +149,7 @@ int stm32_adc_setup(void) /* Call stm32_adcinitialize() to get an instance of the ADC interface */ - adc = stm32h7_adc_initialize(1, g_adc1_chanlist, ADC1_NCHANNELS); + adc = stm32_adc_initialize(1, g_adc1_chanlist, ADC1_NCHANNELS); if (adc == NULL) { aerr("ERROR: Failed to get ADC1 interface\n"); @@ -167,7 +167,7 @@ int stm32_adc_setup(void) devname[8]++; #endif -#if defined(CONFIG_STM32H7_ADC3) +#if defined(CONFIG_STM32_ADC3) /* Configure the pins as analog inputs for the selected channels */ for (i = 0; i < ADC3_NCHANNELS; i++) @@ -180,7 +180,7 @@ int stm32_adc_setup(void) /* Call stm32_adcinitialize() to get an instance of the ADC interface */ - adc = stm32h7_adc_initialize(3, g_adc3_chanlist, ADC3_NCHANNELS); + adc = stm32_adc_initialize(3, g_adc3_chanlist, ADC3_NCHANNELS); if (adc == NULL) { aerr("ERROR: Failed to get ADC3 interface\n"); @@ -197,7 +197,7 @@ int stm32_adc_setup(void) } #endif -#if defined(CONFIG_STM32H7_ADC1) || defined(CONFIG_STM32H7_ADC3) +#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC3) /* Now we are initialized */ initialized = true; @@ -209,5 +209,5 @@ int stm32_adc_setup(void) #endif } -#endif /* CONFIG_STM32H7_ADC1 || CONFIG_STM32H7_ADC2 || CONFIG_STM32H7_ADC3 */ +#endif /* CONFIG_STM32_ADC1 || CONFIG_STM32_ADC2 || CONFIG_STM32_ADC3 */ #endif /* CONFIG_ADC */ diff --git a/boards/arm/stm32h7/stm32h747i-disco/src/stm32_boot.c b/boards/arm/stm32h7/stm32h747i-disco/src/stm32_boot.c index 595a6acb393f9..2fe6598915c7e 100644 --- a/boards/arm/stm32h7/stm32h747i-disco/src/stm32_boot.c +++ b/boards/arm/stm32h7/stm32h747i-disco/src/stm32_boot.c @@ -58,13 +58,13 @@ void stm32_boardinitialize(void) board_autoled_initialize(); #endif -#if defined(CONFIG_STM32H7_OTGHS) || defined(CONFIG_STM32H7_HOST) +#if defined(CONFIG_STM32_OTGHS) || defined(CONFIG_STM32_HOST) /* Initialize USB */ stm32_usbinitialize(); #endif -#ifdef CONFIG_STM32H7_SPI +#ifdef CONFIG_STM32_SPI /* Configure SPI chip selects */ stm32_spidev_initialize(); diff --git a/boards/arm/stm32h7/stm32h747i-disco/src/stm32_bringup.c b/boards/arm/stm32h7/stm32h747i-disco/src/stm32_bringup.c index 84e93d0e9977b..12a8a37d4fdd0 100644 --- a/boards/arm/stm32h7/stm32h747i-disco/src/stm32_bringup.c +++ b/boards/arm/stm32h7/stm32h747i-disco/src/stm32_bringup.c @@ -90,16 +90,16 @@ static void stm32_i2c_register(int bus) #if defined(CONFIG_I2C) && defined(CONFIG_SYSTEM_I2CTOOL) static void stm32_i2ctool(void) { -#ifdef CONFIG_STM32H7_I2C1 +#ifdef CONFIG_STM32_I2C1 stm32_i2c_register(1); #endif -#ifdef CONFIG_STM32H7_I2C2 +#ifdef CONFIG_STM32_I2C2 stm32_i2c_register(2); #endif -#ifdef CONFIG_STM32H7_I2C3 +#ifdef CONFIG_STM32_I2C3 stm32_i2c_register(3); #endif -#ifdef CONFIG_STM32H7_I2C4 +#ifdef CONFIG_STM32_I2C4 stm32_i2c_register(4); #endif } diff --git a/boards/arm/stm32h7/stm32h747i-disco/src/stm32_spi.c b/boards/arm/stm32h7/stm32h747i-disco/src/stm32_spi.c index a5885be43e0f7..b038469e60bdd 100644 --- a/boards/arm/stm32h7/stm32h747i-disco/src/stm32_spi.c +++ b/boards/arm/stm32h7/stm32h747i-disco/src/stm32_spi.c @@ -41,7 +41,7 @@ #include "stm32h747i-disco.h" #include -#ifdef CONFIG_STM32H7_SPI +#ifdef CONFIG_STM32_SPI /**************************************************************************** * Public Functions @@ -91,7 +91,7 @@ void stm32_spidev_initialize(void) * ****************************************************************************/ -#ifdef CONFIG_STM32H7_SPI1 +#ifdef CONFIG_STM32_SPI1 void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -105,7 +105,7 @@ uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32H7_SPI2 +#ifdef CONFIG_STM32_SPI2 void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -119,7 +119,7 @@ uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32H7_SPI3 +#ifdef CONFIG_STM32_SPI3 void stm32_spi3select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -143,7 +143,7 @@ uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32H7_SPI4 +#ifdef CONFIG_STM32_SPI4 void stm32_spi4select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -157,7 +157,7 @@ uint8_t stm32_spi4status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32H7_SPI5 +#ifdef CONFIG_STM32_SPI5 void stm32_spi5select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -171,7 +171,7 @@ uint8_t stm32_spi5status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32H7_SPI6 +#ifdef CONFIG_STM32_SPI6 void stm32_spi6select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -209,42 +209,42 @@ uint8_t stm32_spi6status(struct spi_dev_s *dev, uint32_t devid) ****************************************************************************/ #ifdef CONFIG_SPI_CMDDATA -#ifdef CONFIG_STM32H7_SPI1 +#ifdef CONFIG_STM32_SPI1 int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32H7_SPI2 +#ifdef CONFIG_STM32_SPI2 int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32H7_SPI3 +#ifdef CONFIG_STM32_SPI3 int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32H7_SPI4 +#ifdef CONFIG_STM32_SPI4 int stm32_spi4cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32H7_SPI5 +#ifdef CONFIG_STM32_SPI5 int stm32_spi5cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32H7_SPI6 +#ifdef CONFIG_STM32_SPI6 int stm32_spi5cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; @@ -252,4 +252,4 @@ int stm32_spi5cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) #endif #endif /* CONFIG_SPI_CMDDATA */ -#endif /* CONFIG_STM32H7_SPI */ +#endif /* CONFIG_STM32_SPI */ diff --git a/boards/arm/stm32h7/stm32h747i-disco/src/stm32_usb.c b/boards/arm/stm32h7/stm32h747i-disco/src/stm32_usb.c index 7295b74cebe64..84c95e9204b51 100644 --- a/boards/arm/stm32h7/stm32h747i-disco/src/stm32_usb.c +++ b/boards/arm/stm32h7/stm32h747i-disco/src/stm32_usb.c @@ -45,7 +45,7 @@ #include "stm32_otg.h" #include "stm32h747i-disco.h" -#ifdef CONFIG_STM32H7_OTGHS +#ifdef CONFIG_STM32_OTGHS /**************************************************************************** * Pre-processor Definitions @@ -54,7 +54,7 @@ #if defined(CONFIG_USBDEV) || defined(CONFIG_USBHOST) # define HAVE_USB 1 #else -# warning "CONFIG_STM32H7_OTGHS is enabled but neither CONFIG_USBDEV nor CONFIG_USBHOST" +# warning "CONFIG_STM32_OTGHS is enabled but neither CONFIG_USBDEV nor CONFIG_USBHOST" # undef HAVE_USB #endif @@ -132,7 +132,7 @@ void stm32_usbinitialize(void) { /* Configure the Overcurrent GPIO */ -#ifdef CONFIG_STM32H7_OTGHS +#ifdef CONFIG_STM32_OTGHS stm32_configgpio(GPIO_OTGHS_OVER); #endif } diff --git a/boards/arm/stm32h7/stm32h747i-disco/src/stm32h747i-disco.h b/boards/arm/stm32h7/stm32h747i-disco/src/stm32h747i-disco.h index c53bb6f8a765e..8a3f154959761 100644 --- a/boards/arm/stm32h7/stm32h747i-disco/src/stm32h747i-disco.h +++ b/boards/arm/stm32h7/stm32h747i-disco/src/stm32h747i-disco.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32H7_STM32H747I_DISCO_SRC_STM32H747I_DISCO_H -#define __BOARDS_ARM_STM32H7_STM32H747I_DISCO_SRC_STM32H747I_DISCO_H +#ifndef __BOARDS_ARM_STM32_STM32H747I_DISCO_SRC_STM32H747I_DISCO_H +#define __BOARDS_ARM_STM32_STM32H747I_DISCO_SRC_STM32H747I_DISCO_H /**************************************************************************** * Included Files @@ -95,7 +95,7 @@ /* SD/TF Card'detected pin */ -#if defined(CONFIG_STM32H7_SDMMC1) +#if defined(CONFIG_STM32_SDMMC1) # define HAVE_SDIO #endif @@ -129,7 +129,7 @@ int stm32_bringup(void); * ****************************************************************************/ -#ifdef CONFIG_STM32H7_SPI +#ifdef CONFIG_STM32_SPI void stm32_spidev_initialize(void); #endif @@ -172,4 +172,4 @@ int stm32_dma_alloc_init(void); int stm32_sdio_initialize(void); #endif -#endif /* __BOARDS_ARM_STM32H7_STM32H747I_DISCO_SRC_STM32H747I_DISCO_H */ +#endif /* __BOARDS_ARM_STM32_STM32H747I_DISCO_SRC_STM32H747I_DISCO_H */ diff --git a/boards/arm/stm32h7/stm32h750b-dk/configs/lvgl/defconfig b/boards/arm/stm32h7/stm32h750b-dk/configs/lvgl/defconfig index f4913aa50bb86..66fe8ef9f0554 100644 --- a/boards/arm/stm32h7/stm32h750b-dk/configs/lvgl/defconfig +++ b/boards/arm/stm32h7/stm32h750b-dk/configs/lvgl/defconfig @@ -6,14 +6,15 @@ # modifications. # # CONFIG_STANDARD_SERIAL is not set -# CONFIG_STM32H7_FB_CMAP is not set -# CONFIG_STM32H7_LTDC_L1_CHROMAKEYEN is not set -# CONFIG_STM32H7_LTDC_L2 is not set +# CONFIG_STM32_FB_CMAP is not set +# CONFIG_STM32_LTDC_L1_CHROMAKEYEN is not set +# CONFIG_STM32_LTDC_L2 is not set CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32h750b-dk" CONFIG_ARCH_BOARD_STM32H750B_DK=y CONFIG_ARCH_BOARD_STM32H750B_DK_TOUCHSCREEN_SWAPXY=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H750XB=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -67,14 +68,14 @@ CONFIG_SIG_DEFAULT=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_DMA1=y -CONFIG_STM32H7_DMA2=y -CONFIG_STM32H7_FMC=y -CONFIG_STM32H7_I2C4=y -CONFIG_STM32H7_LTDC=y -CONFIG_STM32H7_LTDC_FB_BASE=0xd0000000 -CONFIG_STM32H7_LTDC_FB_SIZE=522240 -CONFIG_STM32H7_USART3=y +CONFIG_STM32_DMA1=y +CONFIG_STM32_DMA2=y +CONFIG_STM32_FMC=y +CONFIG_STM32_I2C4=y +CONFIG_STM32_LTDC=y +CONFIG_STM32_LTDC_FB_BASE=0xd0000000 +CONFIG_STM32_LTDC_FB_SIZE=522240 +CONFIG_STM32_USART3=y CONFIG_SYSTEM_NSH=y CONFIG_TTY_SIGINT=y CONFIG_USART3_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32h7/stm32h750b-dk/include/board.h b/boards/arm/stm32h7/stm32h750b-dk/include/board.h index c63ca3b3fdc21..6f7b603a38cbd 100644 --- a/boards/arm/stm32h7/stm32h750b-dk/include/board.h +++ b/boards/arm/stm32h7/stm32h750b-dk/include/board.h @@ -18,8 +18,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32H7_STM32H750B_DK_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32H7_STM32H750B_DK_INCLUDE_BOARD_H +#ifndef __BOARDS_ARM_STM32_STM32H750B_DK_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32_STM32H750B_DK_INCLUDE_BOARD_H /**************************************************************************** * Included Files @@ -340,7 +340,7 @@ #define BOARD_FMC_CLK RCC_D1CCIPR_FMCSEL_HCLK -#if CONFIG_STM32H7_FMC +#if CONFIG_STM32_FMC # define FMC_SDCLK_FREQUENCY (STM32_HCLK_FREQUENCY / 2) # if FMC_SDCLK_FREQUENCY > 100000000 # error "FMC SDRAM settings need to be adjusted for a higher FMC_SDCLK frequency" @@ -611,4 +611,4 @@ extern "C" #endif #endif /* __ASSEMBLY__ */ -#endif /* __BOARDS_ARM_STM32H7_STM32H750B_DK_INCLUDE_BOARD_H */ +#endif /* __BOARDS_ARM_STM32_STM32H750B_DK_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32h7/stm32h750b-dk/scripts/flash.ld b/boards/arm/stm32h7/stm32h750b-dk/scripts/flash.ld index eae68e2f5a1a0..d08b0b9d47522 100644 --- a/boards/arm/stm32h7/stm32h750b-dk/scripts/flash.ld +++ b/boards/arm/stm32h7/stm32h750b-dk/scripts/flash.ld @@ -95,7 +95,7 @@ #include -#ifndef CONFIG_STM32H7_CORTEXM4_ENABLED +#ifndef CONFIG_STM32_CORTEXM4_ENABLED MEMORY { itcm (rwx) : ORIGIN = 0x00000000, LENGTH = 64K @@ -114,7 +114,7 @@ MEMORY MEMORY { itcm (rwx) : ORIGIN = 0x00000000, LENGTH = 64K - flash (rx) : ORIGIN = 0x08000000, LENGTH = CONFIG_STM32H7_CORTEXM7_FLASH_SIZE + flash (rx) : ORIGIN = 0x08000000, LENGTH = CONFIG_STM32_CORTEXM7_FLASH_SIZE dtcm1 (rwx) : ORIGIN = 0x20000000, LENGTH = 64K dtcm2 (rwx) : ORIGIN = 0x20010000, LENGTH = 64K sram (rwx) : ORIGIN = 0x24000000, LENGTH = 512K @@ -191,7 +191,7 @@ SECTIONS _ebss = ABSOLUTE(.); } > sram -#ifdef CONFIG_STM32H7_CORTEXM4_ENABLED +#ifdef CONFIG_STM32_CORTEXM4_ENABLED .shmem (NOLOAD): { . = ALIGN(4); diff --git a/boards/arm/stm32h7/stm32h750b-dk/scripts/flash_m4.ld b/boards/arm/stm32h7/stm32h750b-dk/scripts/flash_m4.ld index ed39a30ec56d0..d6f3372fd3723 100644 --- a/boards/arm/stm32h7/stm32h750b-dk/scripts/flash_m4.ld +++ b/boards/arm/stm32h7/stm32h750b-dk/scripts/flash_m4.ld @@ -20,9 +20,9 @@ #include -#define STM32M4_FLASH_START (0x08000000 + CONFIG_STM32H7_CORTEXM7_FLASH_SIZE) +#define STM32M4_FLASH_START (0x08000000 + CONFIG_STM32_CORTEXM7_FLASH_SIZE) -#if CONFIG_STM32H7_CORTEXM7_FLASH_SIZE != 1048576 +#if CONFIG_STM32_CORTEXM7_FLASH_SIZE != 1048576 # error TODO: not supported yet - BCM4_ADD0 must be configured #endif @@ -32,7 +32,7 @@ MEMORY { flash (rx) : ORIGIN = STM32M4_FLASH_START, - LENGTH = (2048K - CONFIG_STM32H7_CORTEXM7_FLASH_SIZE) + LENGTH = (2048K - CONFIG_STM32_CORTEXM7_FLASH_SIZE) /* SRAM1 and SRAM2 */ diff --git a/boards/arm/stm32h7/stm32h750b-dk/src/CMakeLists.txt b/boards/arm/stm32h7/stm32h750b-dk/src/CMakeLists.txt index d89067b817f11..1e00764ac9ce7 100644 --- a/boards/arm/stm32h7/stm32h750b-dk/src/CMakeLists.txt +++ b/boards/arm/stm32h7/stm32h750b-dk/src/CMakeLists.txt @@ -26,7 +26,7 @@ else() list(APPEND SRCS stm32_userleds.c) endif() -if(CONFIG_STM32H7_OTGFS) +if(CONFIG_STM32_OTGFS) list(APPEND SRCS stm32_usb.c) endif() @@ -34,15 +34,11 @@ if(CONFIG_TESTING_OSTEST) list(APPEND SRCS stm32_ostest.c) endif() -if(CONFIG_BOARDCTL_RESET) - list(APPEND SRCS stm32_reset.c) -endif() - if(CONFIG_INPUT_FT5X06) list(APPEND SRCS stm32_ft5x06.c) endif() -if(CONFIG_STM32H7_LTDC) +if(CONFIG_STM32_LTDC) list(APPEND SRCS stm32_lcd.c) endif() diff --git a/boards/arm/stm32h7/stm32h750b-dk/src/Make.defs b/boards/arm/stm32h7/stm32h750b-dk/src/Make.defs new file mode 100644 index 0000000000000..4fc260f6b9152 --- /dev/null +++ b/boards/arm/stm32h7/stm32h750b-dk/src/Make.defs @@ -0,0 +1,49 @@ +############################################################################ +# boards/arm/stm32h7/stm32h750b-dk/src/Make.defs +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +CSRCS = stm32_boot.c stm32_bringup.c + +ifeq ($(CONFIG_ARCH_LEDS),y) +CSRCS += stm32_autoleds.c +else +CSRCS += stm32_userleds.c +endif + +ifeq ($(CONFIG_STM32_OTGFS),y) +CSRCS += stm32_usb.c +endif + +ifeq ($(CONFIG_TESTING_OSTEST),y) +CSRCS += stm32_ostest.c +endif + +ifeq ($(CONFIG_INPUT_FT5X06),y) +CSRCS += stm32_ft5x06.c +endif + +ifeq ($(CONFIG_STM32_LTDC),y) +CSRCS += stm32_lcd.c +endif + +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32h7/stm32h750b-dk/src/Makefile b/boards/arm/stm32h7/stm32h750b-dk/src/Makefile deleted file mode 100644 index 7dec83d2100fc..0000000000000 --- a/boards/arm/stm32h7/stm32h750b-dk/src/Makefile +++ /dev/null @@ -1,51 +0,0 @@ -############################################################################ -# boards/arm/stm32h7/stm32h750b-dk/src/Makefile -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/Make.defs - -CSRCS = stm32_boot.c stm32_bringup.c - -ifeq ($(CONFIG_ARCH_LEDS),y) -CSRCS += stm32_autoleds.c -else -CSRCS += stm32_userleds.c -endif - -ifeq ($(CONFIG_STM32H7_OTGFS),y) -CSRCS += stm32_usb.c -endif - -ifeq ($(CONFIG_TESTING_OSTEST),y) -CSRCS += stm32_ostest.c -endif - -ifeq ($(CONFIG_BOARDCTL_RESET),y) -CSRCS += stm32_reset.c -endif - -ifeq ($(CONFIG_INPUT_FT5X06),y) -CSRCS += stm32_ft5x06.c -endif - -ifeq ($(CONFIG_STM32H7_LTDC),y) -CSRCS += stm32_lcd.c -endif - -include $(TOPDIR)/boards/Board.mk diff --git a/boards/arm/stm32h7/stm32h750b-dk/src/stm32_boot.c b/boards/arm/stm32h7/stm32h750b-dk/src/stm32_boot.c index 0095a26c9b816..e0fe3d7317508 100644 --- a/boards/arm/stm32h7/stm32h750b-dk/src/stm32_boot.c +++ b/boards/arm/stm32h7/stm32h750b-dk/src/stm32_boot.c @@ -54,7 +54,7 @@ void stm32_boardinitialize(void) board_autoled_initialize(); #endif -#if defined(CONFIG_STM32H7_OTGFS) || defined(CONFIG_STM32H7_HOST) +#if defined(CONFIG_STM32_OTGFS) || defined(CONFIG_STM32_HOST) /* Initialize USB */ stm32_usbinitialize(); diff --git a/boards/arm/stm32h7/stm32h750b-dk/src/stm32_bringup.c b/boards/arm/stm32h7/stm32h750b-dk/src/stm32_bringup.c index a7200dffe19a8..8282101411b50 100644 --- a/boards/arm/stm32h7/stm32h750b-dk/src/stm32_bringup.c +++ b/boards/arm/stm32h7/stm32h750b-dk/src/stm32_bringup.c @@ -33,7 +33,7 @@ #include #include -#ifdef CONFIG_STM32H7_OTGFS +#ifdef CONFIG_STM32_OTGFS #include "stm32_usbhost.h" #endif diff --git a/boards/arm/stm32h7/stm32h750b-dk/src/stm32_ft5x06.c b/boards/arm/stm32h7/stm32h750b-dk/src/stm32_ft5x06.c index e719e3ac6fd94..72e3d357b3477 100644 --- a/boards/arm/stm32h7/stm32h750b-dk/src/stm32_ft5x06.c +++ b/boards/arm/stm32h7/stm32h750b-dk/src/stm32_ft5x06.c @@ -47,8 +47,8 @@ # error "FT5x06 support requires CONFIG_INPUT" #endif -#ifndef CONFIG_STM32H7_I2C4 -# error "FT5x06 support requires CONFIG_STM32H7_I2C4" +#ifndef CONFIG_STM32_I2C4 +# error "FT5x06 support requires CONFIG_STM32_I2C4" #endif #ifndef CONFIG_FT5X06_I2CDEV diff --git a/boards/arm/stm32h7/stm32h750b-dk/src/stm32_lcd.c b/boards/arm/stm32h7/stm32h750b-dk/src/stm32_lcd.c index de3e72c627fe5..9ffca9632b1e6 100644 --- a/boards/arm/stm32h7/stm32h750b-dk/src/stm32_lcd.c +++ b/boards/arm/stm32h7/stm32h750b-dk/src/stm32_lcd.c @@ -37,7 +37,7 @@ #include "stm32h750b-dk.h" -#ifdef CONFIG_STM32H7_LTDC +#ifdef CONFIG_STM32_LTDC /**************************************************************************** * Public Functions ****************************************************************************/ diff --git a/boards/arm/stm32h7/stm32h750b-dk/src/stm32_reset.c b/boards/arm/stm32h7/stm32h750b-dk/src/stm32_reset.c deleted file mode 100644 index 7bb3feed5f531..0000000000000 --- a/boards/arm/stm32h7/stm32h750b-dk/src/stm32_reset.c +++ /dev/null @@ -1,62 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32h7/stm32h750b-dk/src/stm32_reset.c - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#ifdef CONFIG_BOARDCTL_RESET - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_reset - * - * Description: - * Reset board. Support for this function is required by board-level - * logic if CONFIG_BOARDCTL_RESET is selected. - * - * Input Parameters: - * status - Status information provided with the reset event. This - * meaning of this status information is board-specific. If not - * used by a board, the value zero may be provided in calls to - * board_reset(). - * - * Returned Value: - * If this function returns, then it was not possible to power-off the - * board due to some constraints. The return value int this case is a - * board-specific reason for the failure to shutdown. - * - ****************************************************************************/ - -int board_reset(int status) -{ - up_systemreset(); - return 0; -} - -#endif /* CONFIG_BOARDCTL_RESET */ diff --git a/boards/arm/stm32h7/stm32h750b-dk/src/stm32_usb.c b/boards/arm/stm32h7/stm32h750b-dk/src/stm32_usb.c index 882307c69852f..50d12205e6557 100644 --- a/boards/arm/stm32h7/stm32h750b-dk/src/stm32_usb.c +++ b/boards/arm/stm32h7/stm32h750b-dk/src/stm32_usb.c @@ -43,7 +43,7 @@ #include "stm32h750b-dk.h" -#ifdef CONFIG_STM32H7_OTGFS +#ifdef CONFIG_STM32_OTGFS /**************************************************************************** * Pre-processor Definitions @@ -136,7 +136,7 @@ void stm32_usbinitialize(void) * Power On, and Overcurrent GPIOs */ -#ifdef CONFIG_STM32H7_OTGFS +#ifdef CONFIG_STM32_OTGFS stm32_configgpio(GPIO_OTGFS_VBUS); stm32_configgpio(GPIO_OTGFS_PWRON); stm32_configgpio(GPIO_OTGFS_OVER); diff --git a/boards/arm/stm32h7/stm32h750b-dk/src/stm32h750b-dk.h b/boards/arm/stm32h7/stm32h750b-dk/src/stm32h750b-dk.h index 5e0e6b7f2de52..e0579a31433e7 100644 --- a/boards/arm/stm32h7/stm32h750b-dk/src/stm32h750b-dk.h +++ b/boards/arm/stm32h7/stm32h750b-dk/src/stm32h750b-dk.h @@ -18,8 +18,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32H7_STM32H750B_DK_SRC_STM32H750B_DK_H -#define __BOARDS_ARM_STM32H7_STM32H750B_DK_SRC_STM32H750B_DK_H +#ifndef __BOARDS_ARM_STM32_STM32H750B_DK_SRC_STM32H750B_DK_H +#define __BOARDS_ARM_STM32_STM32H750B_DK_SRC_STM32H750B_DK_H /**************************************************************************** * Included Files @@ -42,7 +42,7 @@ /* Can't support USB host or device features if USB OTG FS is not enabled */ -#ifndef CONFIG_STM32H7_OTGFS +#ifndef CONFIG_STM32_OTGFS # undef HAVE_USBDEV # undef HAVE_USBHOST #endif @@ -182,7 +182,7 @@ int stm32_bringup(void); * ****************************************************************************/ -#ifdef CONFIG_STM32H7_OTGFS +#ifdef CONFIG_STM32_OTGFS void weak_function stm32_usbinitialize(void); #endif @@ -196,7 +196,7 @@ void weak_function stm32_usbinitialize(void); * ****************************************************************************/ -#if defined(CONFIG_STM32H7_OTGFS) && defined(CONFIG_USBHOST) +#if defined(CONFIG_STM32_OTGFS) && defined(CONFIG_USBHOST) int stm32_usbhost_initialize(void); #endif @@ -214,4 +214,4 @@ int stm32_usbhost_initialize(void); int stm32_tsc_setup(int minor); #endif -#endif /* __BOARDS_ARM_STM32H7_STM32H750B_DK_SRC_STM32H750B_DK_H */ +#endif /* __BOARDS_ARM_STM32_STM32H750B_DK_SRC_STM32H750B_DK_H */ diff --git a/boards/arm/stm32h7/weact-stm32h743/configs/nsh/defconfig b/boards/arm/stm32h7/weact-stm32h743/configs/nsh/defconfig index 3a3b4caf7f828..3ed170d4ccea1 100644 --- a/boards/arm/stm32h7/weact-stm32h743/configs/nsh/defconfig +++ b/boards/arm/stm32h7/weact-stm32h743/configs/nsh/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="weact-stm32h743" CONFIG_ARCH_BOARD_WEACT_STM32H743=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H743VI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -43,7 +44,7 @@ CONFIG_SPI=y CONFIG_START_DAY=11 CONFIG_START_MONTH=5 CONFIG_START_YEAR=2024 -CONFIG_STM32H7_USART1=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32h7/weact-stm32h743/configs/sdcard/defconfig b/boards/arm/stm32h7/weact-stm32h743/configs/sdcard/defconfig index bb9f06926d9f7..52d6fd71d4d24 100644 --- a/boards/arm/stm32h7/weact-stm32h743/configs/sdcard/defconfig +++ b/boards/arm/stm32h7/weact-stm32h743/configs/sdcard/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="weact-stm32h743" CONFIG_ARCH_BOARD_WEACT_STM32H743=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H743VI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -58,10 +59,10 @@ CONFIG_SDMMC1_SDIO_MODE=y CONFIG_START_DAY=11 CONFIG_START_MONTH=5 CONFIG_START_YEAR=2024 -CONFIG_STM32H7_PWR=y -CONFIG_STM32H7_RTC=y -CONFIG_STM32H7_SDMMC1=y -CONFIG_STM32H7_USART1=y +CONFIG_STM32_PWR=y +CONFIG_STM32_RTC=y +CONFIG_STM32_SDMMC1=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32h7/weact-stm32h743/configs/st7735/defconfig b/boards/arm/stm32h7/weact-stm32h743/configs/st7735/defconfig index 5aedb0aeceee3..fc9b8d1a0175f 100644 --- a/boards/arm/stm32h7/weact-stm32h743/configs/st7735/defconfig +++ b/boards/arm/stm32h7/weact-stm32h743/configs/st7735/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="weact-stm32h743" CONFIG_ARCH_BOARD_WEACT_STM32H743=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H743VI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -55,8 +56,8 @@ CONFIG_SPI_CMDDATA=y CONFIG_START_DAY=11 CONFIG_START_MONTH=5 CONFIG_START_YEAR=2024 -CONFIG_STM32H7_SPI4=y -CONFIG_STM32H7_USART1=y +CONFIG_STM32_SPI4=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32h7/weact-stm32h743/configs/usbnsh/defconfig b/boards/arm/stm32h7/weact-stm32h743/configs/usbnsh/defconfig index 537159322559c..e2a79412f1c59 100644 --- a/boards/arm/stm32h7/weact-stm32h743/configs/usbnsh/defconfig +++ b/boards/arm/stm32h7/weact-stm32h743/configs/usbnsh/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="weact-stm32h743" CONFIG_ARCH_BOARD_WEACT_STM32H743=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H743VI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -47,9 +48,9 @@ CONFIG_SPI=y CONFIG_START_DAY=11 CONFIG_START_MONTH=5 CONFIG_START_YEAR=2024 -CONFIG_STM32H7_HSI48=y -CONFIG_STM32H7_OTGFS=y -CONFIG_STM32H7_USART1=y +CONFIG_STM32_HSI48=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USBDEV=y diff --git a/boards/arm/stm32h7/weact-stm32h743/include/board.h b/boards/arm/stm32h7/weact-stm32h743/include/board.h index b0b0a6cbcc06e..366a3af7cdb76 100644 --- a/boards/arm/stm32h7/weact-stm32h743/include/board.h +++ b/boards/arm/stm32h7/weact-stm32h743/include/board.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32H7_WEACT_STM32H743_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32H7_WEACT_STM32H743_INCLUDE_BOARD_H +#ifndef __BOARDS_ARM_STM32_WEACT_STM32H743_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32_WEACT_STM32H743_INCLUDE_BOARD_H /**************************************************************************** * Included Files @@ -406,4 +406,4 @@ extern "C" #endif #endif /* __ASSEMBLY__ */ -#endif /* __BOARDS_ARM_STM32H7_WEACT_STM32H743_INCLUDE_BOARD_H */ +#endif /* __BOARDS_ARM_STM32_WEACT_STM32H743_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32h7/weact-stm32h743/src/CMakeLists.txt b/boards/arm/stm32h7/weact-stm32h743/src/CMakeLists.txt index af3c82ac515ef..6f41b679d009e 100644 --- a/boards/arm/stm32h7/weact-stm32h743/src/CMakeLists.txt +++ b/boards/arm/stm32h7/weact-stm32h743/src/CMakeLists.txt @@ -34,7 +34,7 @@ if(CONFIG_VIDEO_FB) endif() endif() -if(CONFIG_STM32H7_SDMMC) +if(CONFIG_STM32_SDMMC) list(APPEND SRCS stm32_sdmmc.c) endif() diff --git a/boards/arm/stm32h7/weact-stm32h743/src/Make.defs b/boards/arm/stm32h7/weact-stm32h743/src/Make.defs new file mode 100644 index 0000000000000..4aac69d54d0c5 --- /dev/null +++ b/boards/arm/stm32h7/weact-stm32h743/src/Make.defs @@ -0,0 +1,49 @@ +############################################################################ +# boards/arm/stm32h7/weact-stm32h743/src/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +CSRCS = stm32_boot.c stm32_bringup.c stm32_usb.c stm32_ioctl.c stm32_spi.c + +ifeq ($(CONFIG_ARCH_LEDS),y) +CSRCS += stm32_autoleds.c +else +CSRCS += stm32_userleds.c +endif + +ifeq ($(CONFIG_VIDEO_FB),y) + ifeq ($(CONFIG_LCD_ST7735),y) + CSRCS += stm32_lcd_st7735.c + endif +endif + +ifeq ($(CONFIG_STM32_SDMMC),y) +CSRCS += stm32_sdmmc.c +endif + +ifeq ($(CONFIG_FAT_DMAMEMORY),y) +CSRCS += stm32_dma_alloc.c +endif + +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32h7/weact-stm32h743/src/Makefile b/boards/arm/stm32h7/weact-stm32h743/src/Makefile deleted file mode 100644 index 3d686ef415e02..0000000000000 --- a/boards/arm/stm32h7/weact-stm32h743/src/Makefile +++ /dev/null @@ -1,47 +0,0 @@ -############################################################################ -# boards/arm/stm32h7/weact-stm32h743/src/Makefile -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/Make.defs - -CSRCS = stm32_boot.c stm32_bringup.c stm32_usb.c stm32_ioctl.c stm32_spi.c - -ifeq ($(CONFIG_ARCH_LEDS),y) -CSRCS += stm32_autoleds.c -else -CSRCS += stm32_userleds.c -endif - -ifeq ($(CONFIG_VIDEO_FB),y) - ifeq ($(CONFIG_LCD_ST7735),y) - CSRCS += stm32_lcd_st7735.c - endif -endif - -ifeq ($(CONFIG_STM32H7_SDMMC),y) -CSRCS += stm32_sdmmc.c -endif - -ifeq ($(CONFIG_FAT_DMAMEMORY),y) -CSRCS += stm32_dma_alloc.c -endif - -include $(TOPDIR)/boards/Board.mk diff --git a/boards/arm/stm32h7/weact-stm32h743/src/stm32_boot.c b/boards/arm/stm32h7/weact-stm32h743/src/stm32_boot.c index 4c09ec8ce107d..6173d41518e55 100644 --- a/boards/arm/stm32h7/weact-stm32h743/src/stm32_boot.c +++ b/boards/arm/stm32h7/weact-stm32h743/src/stm32_boot.c @@ -52,9 +52,9 @@ void stm32_boardinitialize(void) { -#if defined(CONFIG_STM32H7_SPI1) || defined(CONFIG_STM32H7_SPI2) || \ - defined(CONFIG_STM32H7_SPI3) || defined(CONFIG_STM32H7_SPI4) || \ - defined(CONFIG_STM32H7_SPI6) +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || \ + defined(CONFIG_STM32_SPI3) || defined(CONFIG_STM32_SPI4) || \ + defined(CONFIG_STM32_SPI6) /* Configure SPI chip selects if 1) SPI is not disabled, and 2) the weak * function stm32_spidev_initialize() has been brought into the link. */ diff --git a/boards/arm/stm32h7/weact-stm32h743/src/stm32_spi.c b/boards/arm/stm32h7/weact-stm32h743/src/stm32_spi.c index a11654bc8faaf..91513bcf09139 100644 --- a/boards/arm/stm32h7/weact-stm32h743/src/stm32_spi.c +++ b/boards/arm/stm32h7/weact-stm32h743/src/stm32_spi.c @@ -87,7 +87,7 @@ void stm32_spidev_initialize(void) * ****************************************************************************/ -#ifdef CONFIG_STM32H7_SPI4 +#ifdef CONFIG_STM32_SPI4 void stm32_spi4select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -130,7 +130,7 @@ uint8_t stm32_spi4status(struct spi_dev_s *dev, uint32_t devid) ****************************************************************************/ #ifdef CONFIG_SPI_CMDDATA -#ifdef CONFIG_STM32H7_SPI4 +#ifdef CONFIG_STM32_SPI4 int stm32_spi4cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { #ifdef CONFIG_LCD_ST7735 diff --git a/boards/arm/stm32h7/weact-stm32h743/src/stm32_usb.c b/boards/arm/stm32h7/weact-stm32h743/src/stm32_usb.c index eb46659de268a..4aff43a107a86 100644 --- a/boards/arm/stm32h7/weact-stm32h743/src/stm32_usb.c +++ b/boards/arm/stm32h7/weact-stm32h743/src/stm32_usb.c @@ -45,7 +45,7 @@ #include "stm32_otg.h" #include "weact-stm32h743.h" -#ifdef CONFIG_STM32H7_OTGFS +#ifdef CONFIG_STM32_OTGFS /**************************************************************************** * Pre-processor Definitions diff --git a/boards/arm/stm32h7/weact-stm32h743/src/weact-stm32h743.h b/boards/arm/stm32h7/weact-stm32h743/src/weact-stm32h743.h index 34f91044d7ec8..59e0f9ebd9fe9 100644 --- a/boards/arm/stm32h7/weact-stm32h743/src/weact-stm32h743.h +++ b/boards/arm/stm32h7/weact-stm32h743/src/weact-stm32h743.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32H7_WEACT_STM32H743_SRC_WEACT_STM32H743_H -#define __BOARDS_ARM_STM32H7_WEACT_STM32H743_SRC_WEACT_STM32H743_H +#ifndef __BOARDS_ARM_STM32_WEACT_STM32H743_SRC_WEACT_STM32H743_H +#define __BOARDS_ARM_STM32_WEACT_STM32H743_SRC_WEACT_STM32H743_H /**************************************************************************** * Included Files @@ -53,7 +53,7 @@ /* Can't support USB host or device features if USB OTG FS is not enabled */ -#ifndef CONFIG_STM32H7_OTGFS +#ifndef CONFIG_STM32_OTGFS # undef HAVE_USBDEV # undef HAVE_USBHOST #endif @@ -88,7 +88,7 @@ # undef HAVE_USBMONITOR #endif -#if !defined(CONFIG_STM32H7_PROGMEM) || !defined(CONFIG_MTD_PROGMEM) +#if !defined(CONFIG_STM32_PROGMEM) || !defined(CONFIG_MTD_PROGMEM) # undef HAVE_PROGMEM_CHARDEV #endif @@ -131,7 +131,7 @@ * PD4 Card detected pin */ -#if defined(CONFIG_STM32H7_SDMMC1) +#if defined(CONFIG_STM32_SDMMC1) # define HAVE_SDIO #endif @@ -199,4 +199,4 @@ int stm32_dma_alloc_init(void); int stm32_sdio_initialize(void); #endif -#endif /* __BOARDS_ARM_STM32H7_WEACT_STM32H743_SRC_WEACT_STM32H743_H */ +#endif /* __BOARDS_ARM_STM32_WEACT_STM32H743_SRC_WEACT_STM32H743_H */ diff --git a/boards/arm/stm32h7/weact-stm32h750/configs/nsh/defconfig b/boards/arm/stm32h7/weact-stm32h750/configs/nsh/defconfig index 70ab99d673af9..edb8697b24eeb 100644 --- a/boards/arm/stm32h7/weact-stm32h750/configs/nsh/defconfig +++ b/boards/arm/stm32h7/weact-stm32h750/configs/nsh/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="weact-stm32h750" CONFIG_ARCH_BOARD_WEACT_STM32H750=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H750VB=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -42,7 +43,7 @@ CONFIG_SPI=y CONFIG_START_DAY=11 CONFIG_START_MONTH=5 CONFIG_START_YEAR=2024 -CONFIG_STM32H7_USART1=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32h7/weact-stm32h750/configs/sdcard/defconfig b/boards/arm/stm32h7/weact-stm32h750/configs/sdcard/defconfig index d1fa7662bd6d8..ffe5056a9843d 100644 --- a/boards/arm/stm32h7/weact-stm32h750/configs/sdcard/defconfig +++ b/boards/arm/stm32h7/weact-stm32h750/configs/sdcard/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="weact-stm32h750" CONFIG_ARCH_BOARD_WEACT_STM32H750=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H750VB=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -59,10 +60,10 @@ CONFIG_SDMMC1_SDIO_MODE=y CONFIG_START_DAY=11 CONFIG_START_MONTH=5 CONFIG_START_YEAR=2024 -CONFIG_STM32H7_PWR=y -CONFIG_STM32H7_RTC=y -CONFIG_STM32H7_SDMMC1=y -CONFIG_STM32H7_USART1=y +CONFIG_STM32_PWR=y +CONFIG_STM32_RTC=y +CONFIG_STM32_SDMMC1=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32h7/weact-stm32h750/configs/st7735/defconfig b/boards/arm/stm32h7/weact-stm32h750/configs/st7735/defconfig index 5098495e7f2a6..df870df8aefb9 100644 --- a/boards/arm/stm32h7/weact-stm32h750/configs/st7735/defconfig +++ b/boards/arm/stm32h7/weact-stm32h750/configs/st7735/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="weact-stm32h750" CONFIG_ARCH_BOARD_WEACT_STM32H750=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H750VB=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -56,8 +57,8 @@ CONFIG_SPI_CMDDATA=y CONFIG_START_DAY=11 CONFIG_START_MONTH=5 CONFIG_START_YEAR=2024 -CONFIG_STM32H7_SPI4=y -CONFIG_STM32H7_USART1=y +CONFIG_STM32_SPI4=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32h7/weact-stm32h750/configs/usbnsh/defconfig b/boards/arm/stm32h7/weact-stm32h750/configs/usbnsh/defconfig index f8e8e73032111..bb2110e286298 100644 --- a/boards/arm/stm32h7/weact-stm32h750/configs/usbnsh/defconfig +++ b/boards/arm/stm32h7/weact-stm32h750/configs/usbnsh/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="weact-stm32h750" CONFIG_ARCH_BOARD_WEACT_STM32H750=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H750VB=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -48,9 +49,9 @@ CONFIG_SPI=y CONFIG_START_DAY=11 CONFIG_START_MONTH=5 CONFIG_START_YEAR=2024 -CONFIG_STM32H7_HSI48=y -CONFIG_STM32H7_OTGFS=y -CONFIG_STM32H7_USART1=y +CONFIG_STM32_HSI48=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USBDEV=y diff --git a/boards/arm/stm32h7/weact-stm32h750/include/board.h b/boards/arm/stm32h7/weact-stm32h750/include/board.h index e85bde12df7e3..321f5f4417cc4 100644 --- a/boards/arm/stm32h7/weact-stm32h750/include/board.h +++ b/boards/arm/stm32h7/weact-stm32h750/include/board.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32H7_WEACT_STM32H750_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32H7_WEACT_STM32H750_INCLUDE_BOARD_H +#ifndef __BOARDS_ARM_STM32_WEACT_STM32H750_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32_WEACT_STM32H750_INCLUDE_BOARD_H /**************************************************************************** * Included Files @@ -406,4 +406,4 @@ extern "C" #endif #endif /* __ASSEMBLY__ */ -#endif /* __BOARDS_ARM_STM32H7_WEACT_STM32H750_INCLUDE_BOARD_H */ +#endif /* __BOARDS_ARM_STM32_WEACT_STM32H750_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32h7/weact-stm32h750/src/CMakeLists.txt b/boards/arm/stm32h7/weact-stm32h750/src/CMakeLists.txt index 6c5220cccc2ab..2d99034462275 100644 --- a/boards/arm/stm32h7/weact-stm32h750/src/CMakeLists.txt +++ b/boards/arm/stm32h7/weact-stm32h750/src/CMakeLists.txt @@ -34,15 +34,15 @@ if(CONFIG_VIDEO_FB) endif() endif() -if(CONFIG_STM32H7_SPI) +if(CONFIG_STM32_SPI) list(APPEND SRCS stm32_spi.c) endif() -if(CONFIG_STM32H7_SDMMC) +if(CONFIG_STM32_SDMMC) list(APPEND SRCS stm32_sdmmc.c) endif() -if(CONFIG_STM32H7_OTGFS) +if(CONFIG_STM32_OTGFS) list(APPEND SRCS stm32_usb.c) endif() diff --git a/boards/arm/stm32h7/weact-stm32h750/src/Make.defs b/boards/arm/stm32h7/weact-stm32h750/src/Make.defs new file mode 100644 index 0000000000000..b9296329d36a6 --- /dev/null +++ b/boards/arm/stm32h7/weact-stm32h750/src/Make.defs @@ -0,0 +1,49 @@ +############################################################################ +# boards/arm/stm32h7/weact-stm32h750/src/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +CSRCS = stm32_boot.c stm32_bringup.c stm32_usb.c stm32_ioctl.c stm32_spi.c + +ifeq ($(CONFIG_ARCH_LEDS),y) +CSRCS += stm32_autoleds.c +else +CSRCS += stm32_userleds.c +endif + +ifeq ($(CONFIG_VIDEO_FB),y) + ifeq ($(CONFIG_LCD_ST7735),y) + CSRCS += stm32_lcd_st7735.c + endif +endif + +ifeq ($(CONFIG_STM32_SDMMC),y) +CSRCS += stm32_sdmmc.c +endif + +ifeq ($(CONFIG_FAT_DMAMEMORY),y) +CSRCS += stm32_dma_alloc.c +endif + +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32h7/weact-stm32h750/src/Makefile b/boards/arm/stm32h7/weact-stm32h750/src/Makefile deleted file mode 100644 index 80033455ab338..0000000000000 --- a/boards/arm/stm32h7/weact-stm32h750/src/Makefile +++ /dev/null @@ -1,47 +0,0 @@ -############################################################################ -# boards/arm/stm32h7/weact-stm32h750/src/Makefile -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/Make.defs - -CSRCS = stm32_boot.c stm32_bringup.c stm32_usb.c stm32_ioctl.c stm32_spi.c - -ifeq ($(CONFIG_ARCH_LEDS),y) -CSRCS += stm32_autoleds.c -else -CSRCS += stm32_userleds.c -endif - -ifeq ($(CONFIG_VIDEO_FB),y) - ifeq ($(CONFIG_LCD_ST7735),y) - CSRCS += stm32_lcd_st7735.c - endif -endif - -ifeq ($(CONFIG_STM32H7_SDMMC),y) -CSRCS += stm32_sdmmc.c -endif - -ifeq ($(CONFIG_FAT_DMAMEMORY),y) -CSRCS += stm32_dma_alloc.c -endif - -include $(TOPDIR)/boards/Board.mk diff --git a/boards/arm/stm32h7/weact-stm32h750/src/stm32_boot.c b/boards/arm/stm32h7/weact-stm32h750/src/stm32_boot.c index 34102ce9f2d4f..4c9423b7a3b84 100644 --- a/boards/arm/stm32h7/weact-stm32h750/src/stm32_boot.c +++ b/boards/arm/stm32h7/weact-stm32h750/src/stm32_boot.c @@ -52,9 +52,9 @@ void stm32_boardinitialize(void) { -#if defined(CONFIG_STM32H7_SPI1) || defined(CONFIG_STM32H7_SPI2) || \ - defined(CONFIG_STM32H7_SPI3) || defined(CONFIG_STM32H7_SPI4) || \ - defined(CONFIG_STM32H7_SPI6) +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || \ + defined(CONFIG_STM32_SPI3) || defined(CONFIG_STM32_SPI4) || \ + defined(CONFIG_STM32_SPI6) /* Configure SPI chip selects if 1) SPI is not disabled, and 2) the weak * function stm32_spidev_initialize() has been brought into the link. */ diff --git a/boards/arm/stm32h7/weact-stm32h750/src/stm32_spi.c b/boards/arm/stm32h7/weact-stm32h750/src/stm32_spi.c index 226882d0e6c40..46b87280b62d8 100644 --- a/boards/arm/stm32h7/weact-stm32h750/src/stm32_spi.c +++ b/boards/arm/stm32h7/weact-stm32h750/src/stm32_spi.c @@ -87,7 +87,7 @@ void stm32_spidev_initialize(void) * ****************************************************************************/ -#ifdef CONFIG_STM32H7_SPI4 +#ifdef CONFIG_STM32_SPI4 void stm32_spi4select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -130,7 +130,7 @@ uint8_t stm32_spi4status(struct spi_dev_s *dev, uint32_t devid) ****************************************************************************/ #ifdef CONFIG_SPI_CMDDATA -#ifdef CONFIG_STM32H7_SPI4 +#ifdef CONFIG_STM32_SPI4 int stm32_spi4cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { #ifdef CONFIG_LCD_ST7735 diff --git a/boards/arm/stm32h7/weact-stm32h750/src/stm32_usb.c b/boards/arm/stm32h7/weact-stm32h750/src/stm32_usb.c index ca8e4cbab7bab..506bb238ed0bd 100644 --- a/boards/arm/stm32h7/weact-stm32h750/src/stm32_usb.c +++ b/boards/arm/stm32h7/weact-stm32h750/src/stm32_usb.c @@ -45,7 +45,7 @@ #include "stm32_otg.h" #include "weact-stm32h750.h" -#ifdef CONFIG_STM32H7_OTGFS +#ifdef CONFIG_STM32_OTGFS /**************************************************************************** * Pre-processor Definitions diff --git a/boards/arm/stm32h7/weact-stm32h750/src/weact-stm32h750.h b/boards/arm/stm32h7/weact-stm32h750/src/weact-stm32h750.h index ecf03db790700..d39ffd16f4eec 100644 --- a/boards/arm/stm32h7/weact-stm32h750/src/weact-stm32h750.h +++ b/boards/arm/stm32h7/weact-stm32h750/src/weact-stm32h750.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32H7_WEACT_STM32H750_SRC_WEACT_STM32H750_H -#define __BOARDS_ARM_STM32H7_WEACT_STM32H750_SRC_WEACT_STM32H750_H +#ifndef __BOARDS_ARM_STM32_WEACT_STM32H750_SRC_WEACT_STM32H750_H +#define __BOARDS_ARM_STM32_WEACT_STM32H750_SRC_WEACT_STM32H750_H /**************************************************************************** * Included Files @@ -53,7 +53,7 @@ /* Can't support USB host or device features if USB OTG FS is not enabled */ -#ifndef CONFIG_STM32H7_OTGFS +#ifndef CONFIG_STM32_OTGFS # undef HAVE_USBDEV # undef HAVE_USBHOST #endif @@ -88,7 +88,7 @@ # undef HAVE_USBMONITOR #endif -#if !defined(CONFIG_STM32H7_PROGMEM) || !defined(CONFIG_MTD_PROGMEM) +#if !defined(CONFIG_STM32_PROGMEM) || !defined(CONFIG_MTD_PROGMEM) # undef HAVE_PROGMEM_CHARDEV #endif @@ -131,7 +131,7 @@ * PD4 Card detected pin */ -#if defined(CONFIG_STM32H7_SDMMC1) +#if defined(CONFIG_STM32_SDMMC1) # define HAVE_SDIO #endif @@ -199,4 +199,4 @@ int stm32_dma_alloc_init(void); int stm32_sdio_initialize(void); #endif -#endif /* __BOARDS_ARM_STM32H7_WEACT_STM32H750_SRC_WEACT_STM32H750_H */ +#endif /* __BOARDS_ARM_STM32_WEACT_STM32H750_SRC_WEACT_STM32H750_H */ diff --git a/boards/arm/stm32l0/b-l072z-lrwan1/CMakeLists.txt b/boards/arm/stm32l0/b-l072z-lrwan1/CMakeLists.txt new file mode 100644 index 0000000000000..f474a7db2a1e0 --- /dev/null +++ b/boards/arm/stm32l0/b-l072z-lrwan1/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32l0/b-l072z-lrwan1/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/Kconfig b/boards/arm/stm32l0/b-l072z-lrwan1/Kconfig similarity index 100% rename from boards/arm/stm32f0l0g0/b-l072z-lrwan1/Kconfig rename to boards/arm/stm32l0/b-l072z-lrwan1/Kconfig diff --git a/boards/arm/stm32l0/b-l072z-lrwan1/configs/adc/defconfig b/boards/arm/stm32l0/b-l072z-lrwan1/configs/adc/defconfig new file mode 100644 index 0000000000000..016388d1db9a4 --- /dev/null +++ b/boards/arm/stm32l0/b-l072z-lrwan1/configs/adc/defconfig @@ -0,0 +1,59 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_ARGCAT is not set +CONFIG_ADC=y +CONFIG_ANALOG=y +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="b-l072z-lrwan1" +CONFIG_ARCH_BOARD_B_L072Z_LRWAN1=y +CONFIG_ARCH_CHIP="stm32l0" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32L072CZ=y +CONFIG_ARCH_CHIP_STM32L072XX=y +CONFIG_ARCH_CHIP_STM32L0=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL=y +CONFIG_BOARD_LOOPSPERMSEC=2796 +CONFIG_BUILTIN=y +CONFIG_DISABLE_ENVIRON=y +CONFIG_DISABLE_MOUNTPOINT=y +CONFIG_DISABLE_MQUEUE=y +CONFIG_DISABLE_PSEUDOFS_OPERATIONS=y +CONFIG_EXAMPLES_ADC=y +CONFIG_EXAMPLES_ADC_SWTRIG=y +CONFIG_EXPERIMENTAL=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=1536 +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=64 +CONFIG_NSH_READLINE=y +CONFIG_NUNGET_CHARS=0 +CONFIG_POSIX_SPAWN_DEFAULT_STACKSIZE=1536 +CONFIG_PREALLOC_TIMERS=0 +CONFIG_PTHREAD_MUTEX_UNSAFE=y +CONFIG_PTHREAD_STACK_DEFAULT=1536 +CONFIG_RAM_SIZE=20480 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=19 +CONFIG_START_MONTH=5 +CONFIG_START_YEAR=2013 +CONFIG_STDIO_DISABLE_BUFFERING=y +CONFIG_STM32_ADC1=y +CONFIG_STM32_ADC1_DMA=y +CONFIG_STM32_DMA1=y +CONFIG_STM32_PWR=y +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32l0/b-l072z-lrwan1/configs/nsh/defconfig b/boards/arm/stm32l0/b-l072z-lrwan1/configs/nsh/defconfig new file mode 100644 index 0000000000000..f8dc57d278479 --- /dev/null +++ b/boards/arm/stm32l0/b-l072z-lrwan1/configs/nsh/defconfig @@ -0,0 +1,52 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_ARGCAT is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="b-l072z-lrwan1" +CONFIG_ARCH_BOARD_B_L072Z_LRWAN1=y +CONFIG_ARCH_CHIP="stm32l0" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32L072CZ=y +CONFIG_ARCH_CHIP_STM32L072XX=y +CONFIG_ARCH_CHIP_STM32L0=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=2796 +CONFIG_BUILTIN=y +CONFIG_DISABLE_ENVIRON=y +CONFIG_DISABLE_MOUNTPOINT=y +CONFIG_DISABLE_MQUEUE=y +CONFIG_DISABLE_POSIX_TIMERS=y +CONFIG_DISABLE_PSEUDOFS_OPERATIONS=y +CONFIG_EXAMPLES_HELLO=y +CONFIG_EXPERIMENTAL=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=1536 +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=64 +CONFIG_NSH_READLINE=y +CONFIG_NUNGET_CHARS=0 +CONFIG_POSIX_SPAWN_DEFAULT_STACKSIZE=1536 +CONFIG_PTHREAD_MUTEX_UNSAFE=y +CONFIG_PTHREAD_STACK_DEFAULT=1536 +CONFIG_RAM_SIZE=20480 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=19 +CONFIG_START_MONTH=5 +CONFIG_START_YEAR=2013 +CONFIG_STDIO_DISABLE_BUFFERING=y +CONFIG_STM32_PWR=y +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32l0/b-l072z-lrwan1/configs/nxlines_oled/defconfig b/boards/arm/stm32l0/b-l072z-lrwan1/configs/nxlines_oled/defconfig new file mode 100644 index 0000000000000..b2c85a1eebb42 --- /dev/null +++ b/boards/arm/stm32l0/b-l072z-lrwan1/configs/nxlines_oled/defconfig @@ -0,0 +1,65 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_EXAMPLES_NXLINES_DEFAULT_COLORS is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NX_DISABLE_1BPP is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="b-l072z-lrwan1" +CONFIG_ARCH_BOARD_B_L072Z_LRWAN1=y +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_CHIP="stm32l0" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32L072CZ=y +CONFIG_ARCH_CHIP_STM32L072XX=y +CONFIG_ARCH_CHIP_STM32L0=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=2796 +CONFIG_BUILTIN=y +CONFIG_EXAMPLES_NXLINES=y +CONFIG_EXAMPLES_NXLINES_BORDERWIDTH=1 +CONFIG_EXAMPLES_NXLINES_BPP=1 +CONFIG_EXAMPLES_NXLINES_LINECOLOR=0xff +CONFIG_EXAMPLES_NXLINES_LINEWIDTH=1 +CONFIG_EXPERIMENTAL=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=1536 +CONFIG_INTELHEX_BINARY=y +CONFIG_LCD=y +CONFIG_LCD_MAXCONTRAST=255 +CONFIG_LCD_SH1106_OLED_132=y +CONFIG_LCD_SSD1306_I2C=y +CONFIG_LINE_MAX=64 +CONFIG_MQ_MAXMSGSIZE=64 +CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=64 +CONFIG_NSH_READLINE=y +CONFIG_NUNGET_CHARS=0 +CONFIG_NX=y +CONFIG_NXFONT_MONO5X8=y +CONFIG_NX_BLOCKING=y +CONFIG_POSIX_SPAWN_DEFAULT_STACKSIZE=1536 +CONFIG_PREALLOC_TIMERS=0 +CONFIG_PTHREAD_MUTEX_UNSAFE=y +CONFIG_PTHREAD_STACK_DEFAULT=1536 +CONFIG_RAM_SIZE=20480 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=19 +CONFIG_START_MONTH=5 +CONFIG_START_YEAR=2013 +CONFIG_STDIO_DISABLE_BUFFERING=y +CONFIG_STM32_I2C1=y +CONFIG_STM32_PWR=y +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_NSH=y +CONFIG_SYSTEM_NSH_STACKSIZE=1024 +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32l0/b-l072z-lrwan1/configs/sx127x/defconfig b/boards/arm/stm32l0/b-l072z-lrwan1/configs/sx127x/defconfig new file mode 100644 index 0000000000000..1f5723aba0a06 --- /dev/null +++ b/boards/arm/stm32l0/b-l072z-lrwan1/configs/sx127x/defconfig @@ -0,0 +1,62 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_ARGCAT is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="b-l072z-lrwan1" +CONFIG_ARCH_BOARD_B_L072Z_LRWAN1=y +CONFIG_ARCH_CHIP="stm32l0" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32L072CZ=y +CONFIG_ARCH_CHIP_STM32L072XX=y +CONFIG_ARCH_CHIP_STM32L0=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=2796 +CONFIG_BUILTIN=y +CONFIG_DISABLE_ENVIRON=y +CONFIG_DISABLE_MOUNTPOINT=y +CONFIG_DISABLE_MQUEUE=y +CONFIG_DISABLE_POSIX_TIMERS=y +CONFIG_DISABLE_PSEUDOFS_OPERATIONS=y +CONFIG_DRIVERS_LPWAN=y +CONFIG_DRIVERS_WIRELESS=y +CONFIG_EXAMPLES_HELLO=y +CONFIG_EXAMPLES_SX127X=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=1536 +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_LPWAN_SX127X=y +CONFIG_LPWAN_SX127X_FSKOOK=y +CONFIG_LPWAN_SX127X_MODULATION_DEFAULT=1 +CONFIG_LPWAN_SX127X_RFFREQ_DEFAULT=930000000 +CONFIG_LPWAN_SX127X_RXSUPPORT=y +CONFIG_LPWAN_SX127X_TXSUPPORT=y +CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=64 +CONFIG_NSH_READLINE=y +CONFIG_NUNGET_CHARS=0 +CONFIG_POSIX_SPAWN_DEFAULT_STACKSIZE=1536 +CONFIG_PTHREAD_MUTEX_UNSAFE=y +CONFIG_PTHREAD_STACK_DEFAULT=1536 +CONFIG_RAM_SIZE=20480 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=19 +CONFIG_START_MONTH=5 +CONFIG_START_YEAR=2013 +CONFIG_STDIO_DISABLE_BUFFERING=y +CONFIG_STM32_PWR=y +CONFIG_STM32_SPI1=y +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32l0/b-l072z-lrwan1/include/board.h b/boards/arm/stm32l0/b-l072z-lrwan1/include/board.h new file mode 100644 index 0000000000000..2029f595402a0 --- /dev/null +++ b/boards/arm/stm32l0/b-l072z-lrwan1/include/board.h @@ -0,0 +1,270 @@ +/**************************************************************************** + * boards/arm/stm32l0/b-l072z-lrwan1/include/board.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_STM32F0L0G0_B_L072Z_LRWAN1_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32F0L0G0_B_L072Z_LRWAN1_INCLUDE_BOARD_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#ifndef __ASSEMBLY__ +# include +# include +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Clocking *****************************************************************/ + +/* HSI - Internal 16 MHz RC Oscillator + * LSI - 32 KHz RC + * HSE - 8 MHz from MCO output of ST-LINK (default OFF on board) + * LSE - 32.768 kHz + */ + +#define STM32_BOARD_XTAL 8000000ul + +#define STM32_HSI_FREQUENCY 16000000ul +#define STM32_LSI_FREQUENCY 32000 /* Between 30kHz and 60kHz */ +#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL +#define STM32_LSE_FREQUENCY 32768 /* X2 on board */ + +/* PLL source is HSI/1, PLL multiplier is 4: + * PLL frequency is 16MHz (XTAL) x 4 = 64MHz + */ + +#define STM32_CFGR_PLLSRC 0 +#define STM32_CFGR_PLLXTPRE 0 +#define STM32_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx4 +#define STM32_PLL_FREQUENCY (4*STM32_HSI_FREQUENCY) + +/* Use the PLL and set the SYSCLK source to be the PLL/2 (32MHz) */ + +#define STM32_SYSCLK_SW RCC_CFGR_SW_PLL +#define STM32_SYSCLK_SWS RCC_CFGR_SWS_PLL +#define STM32_CFGR_PLLDIV RCC_CFGR_PLLDIV_2 +#define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY/2 + +/* AHB clock (HCLK) is SYSCLK (32MHz) */ + +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY + +/* APB2 clock (PCLK2) is HCLK (32MHz) */ + +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK +#define STM32_PCLK2_FREQUENCY STM32_HCLK_FREQUENCY +#define STM32_APB2_CLKIN (STM32_PCLK2_FREQUENCY) + +/* APB1 clock (PCLK1) is HCLK/2 (16MHz) */ + +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd2 +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/2) + +/* 48MHz clock configuration */ + +#if defined(CONFIG_STM32_USB) || defined(CONFIG_STM32_RNG) +# define STM32_USE_CLK48 1 +# define STM32_CLK48_SEL RCC_CCIPR_CLK48SEL_HSI48 +# define STM32_HSI48_SYNCSRC SYNCSRC_NONE +#endif + +/* TODO: timers */ + +/* LED definitions **********************************************************/ + +/* The Nucleo LO73RZ board has three LEDs. Two of these are controlled by + * logic on the board and are not available for software control: + * + * LD1 COM: LD1 default status is red. LD1 turns to green to indicate that + * communications are in progress between the PC and the + * ST-LINK/V2-1. + * LD3 PWR: red LED indicates that the board is powered. + * + * And one can be controlled by software: + * + * User LD2: green LED is a user LED connected to the I/O PA5 of the + * STM32LO73RZ. + * + * If CONFIG_ARCH_LEDS is not defined, then the user can control the LED in + * any way. The following definition is used to access the LED. + */ + +/* LED index values for use with board_userled() */ + +#define BOARD_LED1 0 /* User LD2 */ +#define BOARD_NLEDS 1 + +/* LED bits for use with board_userled_all() */ + +#define BOARD_LED1_BIT (1 << BOARD_LED1) + +/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the LED on board + * the Nucleo LO73RZ. The following definitions describe how NuttX controls + * the LED: + * + * SYMBOL Meaning LED1 state + * ------------------ ----------------------- ---------- + * LED_STARTED NuttX has been started OFF + * LED_HEAPALLOCATE Heap has been allocated OFF + * LED_IRQSENABLED Interrupts enabled OFF + * LED_STACKCREATED Idle stack created ON + * LED_INIRQ In an interrupt No change + * LED_SIGNAL In a signal handler No change + * LED_ASSERTION An assertion failed No change + * LED_PANIC The system has crashed Blinking + * LED_IDLE STM32 is in sleep mode Not used + */ + +#define LED_STARTED 0 +#define LED_HEAPALLOCATE 0 +#define LED_IRQSENABLED 0 +#define LED_STACKCREATED 1 +#define LED_INIRQ 2 +#define LED_SIGNAL 2 +#define LED_ASSERTION 2 +#define LED_PANIC 1 + +/* Button definitions *******************************************************/ + +/* The Nucleo LO73RZ supports two buttons; only one button is controllable + * by software: + * + * B1 USER: user button connected to the I/O PB2/PA0 of the STM32LO73RZ. + * B2 RESET: push button connected to NRST is used to RESET the + * STM32LO73RZ. + */ + +#define BUTTON_USER 0 +#define NUM_BUTTONS 1 + +#define BUTTON_USER_BIT (1 << BUTTON_USER) + +/* Alternate function pin selections ****************************************/ + +/* CMWX1ZZABZ-091 module pinout and internal connections + * + * STM32L072CZ | Function + * ------------+----------- + * PC0 | SX1276_CE (NRESET) + * PA7 | SX1276_MOSI + * PA6 | SX1276_MISO + * PB3 | SX1276_SCK + * PA15 | SX1276_NSS + * PB4 | SX1276_DIO0 + * PB1 | SX1276_DIO1 + * PB0 | SX1276_DIO2 + * PC13 | SX1276_DIO3 + * PA5 | SX1276_DIO4 optional / LED5 + * PA4 | SX1276_DIO5 optional + * PA1 | CRF1 + * PC1 | CRF2 + * PC2 | CRF3 + * PA3 | STLINK Virtual COM RX + * PA2 | STLINK Virtual COM TX + * PA10 | USART1_RX + * PA9 | USART1_TX + * PB15 | SPI2_MOSI + * PB14 | SPI2_MISO + * PB13 | SPI2_SCK + * PB12 | SPI2_NSS + * PB5 | LPTIM1_INI / LED2 + * PB6 | LPTIM1_ETR / LED3 + * PB7 | LPTIM1_IN2 / LED4 + * PB2 | LPTIM1_OUT / BUTTON + * PA0 | BUTTON (optional) + * PB9 | I2C1_SDA + * PB8 | I2C1_SCL + * PA12 | USB_DP optional / TCXO_VCC + * PA11 | USB_DM optional + * + */ + +/* ADC */ + +#define GPIO_ADC1_IN0 (GPIO_ADC1_IN0_0) /* PA0 */ +#define GPIO_ADC1_IN1 (GPIO_ADC1_IN1_0) /* PA1 */ +#define GPIO_ADC1_IN2 (GPIO_ADC1_IN2_0) /* PA2 */ +#define GPIO_ADC1_IN3 (GPIO_ADC1_IN3_0) /* PA3 */ +#define GPIO_ADC1_IN4 (GPIO_ADC1_IN4_0) /* PA4 */ +#define GPIO_ADC1_IN5 (GPIO_ADC1_IN5_0) /* PA5 */ +#define GPIO_ADC1_IN6 (GPIO_ADC1_IN6_0) /* PA6 */ +#define GPIO_ADC1_IN7 (GPIO_ADC1_IN7_0) /* PA7 */ +#define GPIO_ADC1_IN8 (GPIO_ADC1_IN8_0) /* PB0 */ +#define GPIO_ADC1_IN9 (GPIO_ADC1_IN9_0) /* PB1 */ +#define GPIO_ADC1_IN10 (GPIO_ADC1_IN10_0) /* PC0 */ +#define GPIO_ADC1_IN11 (GPIO_ADC1_IN11_0) /* PC1 */ +#define GPIO_ADC1_IN12 (GPIO_ADC1_IN12_0) /* PC2 */ +#define GPIO_ADC1_IN13 (GPIO_ADC1_IN13_0) /* PC3 */ +#define GPIO_ADC1_IN14 (GPIO_ADC1_IN14_0) /* PC4 */ +#define GPIO_ADC1_IN15 (GPIO_ADC1_IN15_0) /* PC5 */ + +/* USART */ + +/* USART1 */ + +#define GPIO_USART1_RX (GPIO_USART1_RX_1|GPIO_SPEED_HIGH) /* PA10 */ +#define GPIO_USART1_TX (GPIO_USART1_TX_1|GPIO_SPEED_HIGH) /* PA9 */ + +/* By default the USART2 is connected to STLINK Virtual COM Port: + * USART2_RX - PA3 + * USART2_TX - PA2 + */ + +#define GPIO_USART2_RX (GPIO_USART2_RX_1|GPIO_SPEED_HIGH) /* PA3 */ +#define GPIO_USART2_TX (GPIO_USART2_TX_1|GPIO_SPEED_HIGH) /* PA2 */ + +/* SPI */ + +/* SPI1 is connected to SX1276 radio */ + +#define GPIO_SPI1_MOSI (GPIO_SPI1_MOSI_2|GPIO_SPEED_MEDIUM) /* PA7 */ +#define GPIO_SPI1_MISO (GPIO_SPI1_MISO_2|GPIO_SPEED_MEDIUM) /* PA6 */ +#define GPIO_SPI1_SCK (GPIO_SPI1_SCK_2|GPIO_SPEED_MEDIUM) /* PB3 */ +#define GPIO_SPI1_NSS (GPIO_SPI1_NSS_1|GPIO_SPEED_MEDIUM) /* PA15 */ + +/* SPI2 */ + +#define GPIO_SPI2_MOSI (GPIO_SPI2_MOSI_1|GPIO_SPEED_MEDIUM) /* PB15 */ +#define GPIO_SPI2_MISO (GPIO_SPI2_MISO_1|GPIO_SPEED_MEDIUM) /* PB14 */ +#define GPIO_SPI2_SCK (GPIO_SPI2_SCK_3|GPIO_SPEED_MEDIUM) /* PB13 */ +#define GPIO_SPI2_NSS (GPIO_SPI2_NSS_1|GPIO_SPEED_MEDIUM) /* PB12 */ + +/* I2C */ + +/* I2C1 */ + +#define GPIO_I2C1_SDA (GPIO_I2C1_SDA_2|GPIO_SPEED_LOW) /* PB9 */ +#define GPIO_I2C1_SCL (GPIO_I2C1_SCL_2|GPIO_SPEED_LOW) /* PB8 */ + +/* DMA channels *************************************************************/ + +/* ADC */ + +#define ADC1_DMA_CHAN DMACHAN_ADC1_1 /* DMA1_CH1 */ + +#endif /* __BOARDS_ARM_STM32F0L0G0_B_L072Z_LRWAN1_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32l0/b-l072z-lrwan1/scripts/Make.defs b/boards/arm/stm32l0/b-l072z-lrwan1/scripts/Make.defs new file mode 100644 index 0000000000000..74fc513e986a0 --- /dev/null +++ b/boards/arm/stm32l0/b-l072z-lrwan1/scripts/Make.defs @@ -0,0 +1,41 @@ +############################################################################ +# boards/arm/stm32l0/b-l072z-lrwan1/scripts/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/.config +include $(TOPDIR)/tools/Config.mk +include $(TOPDIR)/arch/arm/src/armv6-m/Toolchain.defs + +LDSCRIPT = ld.script +ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) + +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32l0/b-l072z-lrwan1/scripts/ld.script b/boards/arm/stm32l0/b-l072z-lrwan1/scripts/ld.script new file mode 100644 index 0000000000000..1c6f4b40e82c3 --- /dev/null +++ b/boards/arm/stm32l0/b-l072z-lrwan1/scripts/ld.script @@ -0,0 +1,115 @@ +/**************************************************************************** + * boards/arm/stm32l0/b-l072z-lrwan1/scripts/ld.script + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* The STM32LO72CZ has 192Kb of FLASH beginning at address 0x0800:0000. + * 20Kb of SRAM and 6Kb of EEPROM + * + * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 + * where the code expects to begin execution by jumping to the entry point in + * the 0x0800:0000 address range. + */ + +MEMORY +{ + flash (rx) : ORIGIN = 0x08000000, LENGTH = 192K + sram (rwx) : ORIGIN = 0x20000000, LENGTH = 20K +} + +OUTPUT_ARCH(arm) +EXTERN(_vectors) +ENTRY(_stext) +SECTIONS +{ + .text : { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > flash + + .init_section : ALIGN(4) { + _sinit = ABSOLUTE(.); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) + _einit = ABSOLUTE(.); + } > flash + + .ARM.extab : ALIGN(4) { + *(.ARM.extab*) + } > flash + + .ARM.exidx : ALIGN(4) { + __exidx_start = ABSOLUTE(.); + *(.ARM.exidx*) + __exidx_end = ABSOLUTE(.); + } > flash + + _eronly = ABSOLUTE(.); + + /* The RAM vector table (if present) should lie at the beginning of SRAM */ + + .ram_vectors : { + *(.ram_vectors) + } > sram + + .data : ALIGN(4) { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > sram AT > flash + + .bss : ALIGN(4) { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + _ebss = ABSOLUTE(.); + } > sram + + /* Stabs debugging sections. */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/stm32l0/b-l072z-lrwan1/src/CMakeLists.txt b/boards/arm/stm32l0/b-l072z-lrwan1/src/CMakeLists.txt new file mode 100644 index 0000000000000..3c1bf3c65f31a --- /dev/null +++ b/boards/arm/stm32l0/b-l072z-lrwan1/src/CMakeLists.txt @@ -0,0 +1,53 @@ +# ############################################################################## +# boards/arm/stm32l0/b-l072z-lrwan1/src/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(SRCS stm32_boot.c stm32_bringup.c) + +if(CONFIG_ARCH_LEDS) + list(APPEND SRCS stm32_autoleds.c) +else() + list(APPEND SRCS stm32_userleds.c) +endif() + +if(CONFIG_ARCH_BUTTONS) + list(APPEND SRCS stm32_buttons.c) +endif() + +if(CONFIG_STM32_SPI) + list(APPEND SRCS stm32_spi.c) +endif() + +if(CONFIG_LPWAN_SX127X) + list(APPEND SRCS stm32_sx127x.c) +endif() + +if(CONFIG_ADC) + list(APPEND SRCS stm32_adc.c) +endif() + +if(CONFIG_LCD_SSD1306) + list(APPEND SRCS stm32_lcd_ssd1306.c) +endif() + +target_sources(board PRIVATE ${SRCS}) + +set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/ld.script") diff --git a/boards/arm/stm32l0/b-l072z-lrwan1/src/Make.defs b/boards/arm/stm32l0/b-l072z-lrwan1/src/Make.defs new file mode 100644 index 0000000000000..0ef4cef9f33ed --- /dev/null +++ b/boards/arm/stm32l0/b-l072z-lrwan1/src/Make.defs @@ -0,0 +1,55 @@ +############################################################################ +# boards/arm/stm32l0/b-l072z-lrwan1/src/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +CSRCS = stm32_boot.c stm32_bringup.c + +ifeq ($(CONFIG_ARCH_LEDS),y) +CSRCS += stm32_autoleds.c +else +CSRCS += stm32_userleds.c +endif + +ifeq ($(CONFIG_ARCH_BUTTONS),y) +CSRCS += stm32_buttons.c +endif + +ifeq ($(CONFIG_STM32_SPI),y) +CSRCS += stm32_spi.c +endif + +ifeq ($(CONFIG_LPWAN_SX127X),y) +CSRCS += stm32_sx127x.c +endif + +ifeq ($(CONFIG_ADC),y) +CSRCS += stm32_adc.c +endif + +ifeq ($(CONFIG_LCD_SSD1306),y) +CSRCS += stm32_lcd_ssd1306.c +endif + +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/b-l072z-lrwan1.h b/boards/arm/stm32l0/b-l072z-lrwan1/src/b-l072z-lrwan1.h similarity index 98% rename from boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/b-l072z-lrwan1.h rename to boards/arm/stm32l0/b-l072z-lrwan1/src/b-l072z-lrwan1.h index 04013570d18bf..dfbc614c32214 100644 --- a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/b-l072z-lrwan1.h +++ b/boards/arm/stm32l0/b-l072z-lrwan1/src/b-l072z-lrwan1.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/b-l072z-lrwan1.h + * boards/arm/stm32l0/b-l072z-lrwan1/src/b-l072z-lrwan1.h * * SPDX-License-Identifier: Apache-2.0 * @@ -137,7 +137,7 @@ int stm32_bringup(void); * ****************************************************************************/ -#ifdef CONFIG_STM32F0L0G0_SPI +#ifdef CONFIG_STM32_SPI void stm32_spidev_initialize(void); #endif diff --git a/boards/arm/stm32l0/b-l072z-lrwan1/src/stm32_adc.c b/boards/arm/stm32l0/b-l072z-lrwan1/src/stm32_adc.c new file mode 100644 index 0000000000000..593a484fd8397 --- /dev/null +++ b/boards/arm/stm32l0/b-l072z-lrwan1/src/stm32_adc.c @@ -0,0 +1,133 @@ +/**************************************************************************** + * boards/arm/stm32l0/b-l072z-lrwan1/src/stm32_adc.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include + +#include + +#include "stm32.h" + +#if defined(CONFIG_ADC) && defined(CONFIG_STM32_ADC1) + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* The number of ADC channels in the conversion list */ + +#define ADC1_NCHANNELS 2 + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* Identifying number of each ADC channel (even if NCHANNELS is less ) */ + +static const uint8_t g_chanlist1[2] = +{ + 0, + 4, +}; + +/* Configurations of pins used by each ADC channel */ + +static const uint32_t g_pinlist1[2] = +{ + GPIO_ADC1_IN0, /* PA0/A0 */ + GPIO_ADC1_IN4 /* PA4/A2 */ +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_adc_setup + * + * Description: + * Initialize ADC and register the ADC driver. + * + ****************************************************************************/ + +int stm32_adc_setup(void) +{ + static bool initialized = false; + struct adc_dev_s *adc; + int ret; + int i; + + /* Check if we have already initialized */ + + if (!initialized) + { + /* Configure the pins as analog inputs for the selected channels */ + + for (i = 0; i < ADC1_NCHANNELS; i++) + { + stm32_configgpio(g_pinlist1[i]); + } + + /* Call stm32_adcinitialize() to get an instance of the ADC interface */ + + adc = stm32_adcinitialize(1, g_chanlist1, ADC1_NCHANNELS); + if (adc == NULL) + { + aerr("ERROR: Failed to get ADC interface 1\n"); + return -ENODEV; + } + + /* Register the ADC driver at "/dev/adc0" */ + + ret = adc_register("/dev/adc0", adc); + if (ret < 0) + { + aerr("ERROR: adc_register /dev/adc0 failed: %d\n", ret); + return ret; + } + + initialized = true; + } + + return OK; +} + +#endif /* CONFIG_ADC && CONFIG_STM32_ADC1 */ diff --git a/boards/arm/stm32l0/b-l072z-lrwan1/src/stm32_autoleds.c b/boards/arm/stm32l0/b-l072z-lrwan1/src/stm32_autoleds.c new file mode 100644 index 0000000000000..1b0b8cd55b38e --- /dev/null +++ b/boards/arm/stm32l0/b-l072z-lrwan1/src/stm32_autoleds.c @@ -0,0 +1,80 @@ +/**************************************************************************** + * boards/arm/stm32l0/b-l072z-lrwan1/src/stm32_autoleds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "stm32_gpio.h" +#include "b-l072z-lrwan1.h" + +#ifdef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_autoled_initialize + ****************************************************************************/ + +void board_autoled_initialize(void) +{ + /* Configure LED1 GPIO for output */ + + stm32_configgpio(GPIO_LED1); +} + +/**************************************************************************** + * Name: board_autoled_on + ****************************************************************************/ + +void board_autoled_on(int led) +{ + if (led == BOARD_LED1) + { + stm32_gpiowrite(GPIO_LED1, true); + } +} + +/**************************************************************************** + * Name: board_autoled_off + ****************************************************************************/ + +void board_autoled_off(int led) +{ + if (led == BOARD_LED1) + { + stm32_gpiowrite(GPIO_LED1, false); + } +} + +#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32l0/b-l072z-lrwan1/src/stm32_boot.c b/boards/arm/stm32l0/b-l072z-lrwan1/src/stm32_boot.c new file mode 100644 index 0000000000000..aad79dbb41f83 --- /dev/null +++ b/boards/arm/stm32l0/b-l072z-lrwan1/src/stm32_boot.c @@ -0,0 +1,101 @@ +/**************************************************************************** + * boards/arm/stm32l0/b-l072z-lrwan1/src/stm32_boot.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include "b-l072z-lrwan1.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_boardinitialize + * + * Description: + * All STM32 architectures must provide the following entry point. This + * entry point is called early in the initialization -- after all memory + * has been configured and mapped but before any devices have been + * initialized. + * + ****************************************************************************/ + +void stm32_boardinitialize(void) +{ +#ifdef CONFIG_ARCH_LEDS + /* Configure on-board LEDs if LED support has been selected. */ + + board_autoled_initialize(); +#endif + +#ifdef CONFIG_STM32_SPI + /* Configure SPI chip selects */ + + stm32_spidev_initialize(); +#endif +} + +/**************************************************************************** + * Name: board_late_initialize + * + * Description: + * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_late_initialize(). board_late_initialize() will + * be called immediately after up_initialize() is called and just before + * the initial application is started. This additional initialization + * phase may be used, for example, to initialize board-specific device + * drivers. + * + ****************************************************************************/ + +#ifdef CONFIG_BOARD_LATE_INITIALIZE +void board_late_initialize(void) +{ + /* Perform board-specific initialization */ + + stm32_bringup(); +} +#endif diff --git a/boards/arm/stm32l0/b-l072z-lrwan1/src/stm32_bringup.c b/boards/arm/stm32l0/b-l072z-lrwan1/src/stm32_bringup.c new file mode 100644 index 0000000000000..c3935c1ff164f --- /dev/null +++ b/boards/arm/stm32l0/b-l072z-lrwan1/src/stm32_bringup.c @@ -0,0 +1,173 @@ +/**************************************************************************** + * boards/arm/stm32l0/b-l072z-lrwan1/src/stm32_bringup.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include + +#include "b-l072z-lrwan1.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#undef HAVE_LEDS +#undef HAVE_DAC + +#if !defined(CONFIG_ARCH_LEDS) && defined(CONFIG_USERLED_LOWER) +# define HAVE_LEDS 1 +#endif + +#if defined(CONFIG_DAC) +# define HAVE_DAC1 1 +# define HAVE_DAC2 1 +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_i2c_register + * + * Description: + * Register one I2C drivers for the I2C tool. + * + ****************************************************************************/ + +#if defined(CONFIG_I2C) && defined(CONFIG_SYSTEM_I2CTOOL) +static void stm32_i2c_register(int bus) +{ + struct i2c_master_s *i2c; + int ret; + + i2c = stm32_i2cbus_initialize(bus); + if (i2c == NULL) + { + syslog(LOG_ERR, "ERROR: Failed to get I2C%d interface\n", bus); + } + else + { + ret = i2c_register(i2c, bus); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to register I2C%d driver: %d\n", + bus, ret); + stm32_i2cbus_uninitialize(i2c); + } + } +} +#endif + +/**************************************************************************** + * Name: stm32_i2ctool + * + * Description: + * Register I2C drivers for the I2C tool. + * + ****************************************************************************/ + +#if defined(CONFIG_I2C) && defined(CONFIG_SYSTEM_I2CTOOL) +static void stm32_i2ctool(void) +{ +#ifdef CONFIG_STM32_I2C1 + stm32_i2c_register(1); +#endif +#ifdef CONFIG_STM32_I2C2 + stm32_i2c_register(2); +#endif +#ifdef CONFIG_STM32_I2C3 + stm32_i2c_register(3); +#endif +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_bringup + * + * Description: + * Perform architecture-specific initialization + * + * CONFIG_BOARD_LATE_INITIALIZE=y : + * Called from board_late_initialize(). + * + ****************************************************************************/ + +int stm32_bringup(void) +{ + int ret; + +#ifdef HAVE_LEDS + /* Register the LED driver */ + + ret = userled_lower_initialize(LED_DRIVER_PATH); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: userled_lower_initialize() failed: %d\n", ret); + return ret; + } +#endif + +#ifdef CONFIG_ADC + /* Initialize ADC and register the ADC driver. */ + + ret = stm32_adc_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_adc_setup failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_DAC + /* Initialize DAC and register the DAC driver. */ + + ret = stm32_dac_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_dac_setup failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_LPWAN_SX127X + ret = stm32_lpwaninitialize(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to initialize wireless driver: %d\n", + ret); + } +#endif /* CONFIG_LPWAN_SX127X */ + + UNUSED(ret); + return OK; +} diff --git a/boards/arm/stm32l0/b-l072z-lrwan1/src/stm32_lcd_ssd1306.c b/boards/arm/stm32l0/b-l072z-lrwan1/src/stm32_lcd_ssd1306.c new file mode 100644 index 0000000000000..9644213f06626 --- /dev/null +++ b/boards/arm/stm32l0/b-l072z-lrwan1/src/stm32_lcd_ssd1306.c @@ -0,0 +1,78 @@ +/**************************************************************************** + * boards/arm/stm32l0/b-l072z-lrwan1/src/stm32_lcd_ssd1306.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include +#include +#include + +#include "stm32.h" +#include "b-l072z-lrwan1.h" + +#include "stm32_ssd1306.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_lcd_initialize + ****************************************************************************/ + +int board_lcd_initialize(void) +{ + int ret; + + ret = board_ssd1306_initialize(OLED_I2C_PORT); + if (ret < 0) + { + lcderr("ERROR: Failed to initialize SSD1306\n"); + return ret; + } + + return OK; +} + +/**************************************************************************** + * Name: board_lcd_getdev + ****************************************************************************/ + +struct lcd_dev_s *board_lcd_getdev(int devno) +{ + return board_ssd1306_getdev(); +} + +/**************************************************************************** + * Name: board_lcd_uninitialize + ****************************************************************************/ + +void board_lcd_uninitialize(void) +{ + /* TO-FIX */ +} diff --git a/boards/arm/stm32l0/b-l072z-lrwan1/src/stm32_spi.c b/boards/arm/stm32l0/b-l072z-lrwan1/src/stm32_spi.c new file mode 100644 index 0000000000000..368df13bf056d --- /dev/null +++ b/boards/arm/stm32l0/b-l072z-lrwan1/src/stm32_spi.c @@ -0,0 +1,187 @@ +/**************************************************************************** + * boards/arm/stm32l0/b-l072z-lrwan1/src/stm32_spi.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include + +#include "arm_internal.h" +#include "chip.h" +#include "stm32_gpio.h" +#include "stm32_spi.h" + +#include "b-l072z-lrwan1.h" +#include + +#ifdef CONFIG_STM32_SPI + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_spidev_initialize + * + * Description: + * Called to configure SPI chip select GPIO pins for the Nucleo-144 board. + * + ****************************************************************************/ + +void stm32_spidev_initialize(void) +{ + /* NOTE: Clocking for SPI1 and/or SPI2 was already provided in stm32_rcc.c. + * Configurations of SPI pins is performed in stm32_spi.c. + * Here, we only initialize chip select pins unique to the board + * architecture. + */ + +#ifdef CONFIG_STM32_SPI1 +# ifdef CONFIG_LPWAN_SX127X + /* Configure the SPI-based SX127X chip select GPIO */ + + spiinfo("Configure GPIO for SX127X SPI1/CS\n"); + + stm32_configgpio(GPIO_SX127X_CS); + stm32_gpiowrite(GPIO_SX127X_CS, true); +# endif +#endif +} + +/**************************************************************************** + * Name: stm32_spi1/2/select and stm32_spi1/2/status + * + * Description: + * The external functions, stm32_spi1/2select and stm32_spi1/2status + * must be provided by board-specific logic. They are implementations of + * the select and status methods of the SPI interface defined by struct + * spi_ops_s (see include/nuttx/spi/spi.h). All other methods (including + * stm32_spibus_initialize()) are provided by common STM32 logic. + * To use this common SPI logic on your board: + * + * 1. Provide logic in stm32_boardinitialize() to configure SPI chip select + * pins. + * 2. Provide stm32_spi1/2select() and stm32_spi1/2status() functions + * in your board-specific logic. These functions will perform chip + * selection and status operations using GPIOs in the way your board is + * configured. + * 3. Add a calls to stm32_spibus_initialize() in your low level + * application initialization logic + * 4. The handle returned by stm32_spibus_initialize() may then be used to + * bind the SPI driver to higher level logic (e.g., calling + * mmcsd_spislotinitialize(), for example, will bind the SPI driver to + * the SPI MMC/SD driver). + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_SPI1 +void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, + bool selected) +{ + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); + + switch (devid) + { +#ifdef CONFIG_LPWAN_SX127X + case SPIDEV_LPWAN(0): + { + spiinfo("SX127X device %s\n", + selected ? "asserted" : "de-asserted"); + + /* Set the GPIO low to select and high to de-select */ + + stm32_gpiowrite(GPIO_SX127X_CS, !selected); + break; + } +#endif + + default: + { + break; + } + } +} + +uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) +{ + uint8_t status = 0; + + switch (devid) + { +#ifdef CONFIG_LPWAN_SX127X + case SPIDEV_LPWAN(0): + { + status |= SPI_STATUS_PRESENT; + break; + } +#endif + + default: + { + break; + } + } + + return status; +} +#endif /* CONFIG_STM32_SPI1 */ + +#ifdef CONFIG_STM32_SPI2 +void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid, + bool selected) +{ + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); +} + +uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} +#endif /* CONFIG_STM32_SPI2 */ + +#endif /* CONFIG_STM32_SPI */ diff --git a/boards/arm/stm32l0/b-l072z-lrwan1/src/stm32_sx127x.c b/boards/arm/stm32l0/b-l072z-lrwan1/src/stm32_sx127x.c new file mode 100644 index 0000000000000..e6ffc4681397d --- /dev/null +++ b/boards/arm/stm32l0/b-l072z-lrwan1/src/stm32_sx127x.c @@ -0,0 +1,277 @@ +/**************************************************************************** + * boards/arm/stm32l0/b-l072z-lrwan1/src/stm32_sx127x.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include "stm32_gpio.h" +#include "stm32_exti.h" +#include "stm32_spi.h" + +#include "b-l072z-lrwan1.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* SX127X on SPI1 bus */ + +#define SX127X_SPI 1 + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +static void sx127x_chip_reset(void); +static int sx127x_opmode_change(int opmode); +static int sx127x_freq_select(uint32_t freq); +static int sx127x_pa_select(bool enable); +static int sx127x_irq0_attach(xcpt_t isr, void *arg); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +struct sx127x_lower_s lower = +{ + .irq0attach = sx127x_irq0_attach, + .reset = sx127x_chip_reset, + .opmode_change = sx127x_opmode_change, + .freq_select = sx127x_freq_select, + .pa_select = sx127x_pa_select, + .pa_force = false +}; + +static bool g_high_power_output = false; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: sx127x_irq0_attach + ****************************************************************************/ + +static int sx127x_irq0_attach(xcpt_t isr, void *arg) +{ + wlinfo("Attach DIO0 IRQ\n"); + + /* IRQ on rising edge */ + + stm32_gpiosetevent(GPIO_SX127X_DIO0, true, false, false, isr, arg); + return OK; +} + +/**************************************************************************** + * Name: sx127x_chip_reset + ****************************************************************************/ + +static void sx127x_chip_reset(void) +{ + wlinfo("SX127X RESET\n"); + + /* Configure reset as output */ + + stm32_configgpio(GPIO_SX127X_RESET | GPIO_OUTPUT | GPIO_SPEED_HIGH | + GPIO_OUTPUT_CLEAR); + + /* Set pin to zero */ + + stm32_gpiowrite(GPIO_SX127X_RESET, false); + + /* Wait 1 ms */ + + nxsched_usleep(1000); + + /* Configure reset as input */ + + stm32_configgpio(GPIO_SX127X_RESET | GPIO_INPUT | GPIO_FLOAT); + + /* Wait 10 ms */ + + nxsched_usleep(10000); +} + +/**************************************************************************** + * Name: sx127x_opmode_change + ****************************************************************************/ + +static int sx127x_opmode_change(int opmode) +{ + int ret = OK; + + /* Configure antena switch outputs in SLEEP mode */ + + if (opmode == SX127X_OPMODE_SLEEP) + { + stm32_gpiowrite(GPIO_SX127X_CRF1, false); + stm32_gpiowrite(GPIO_SX127X_CRF2, false); + stm32_gpiowrite(GPIO_SX127X_CRF3, false); + + stm32_configgpio(GPIO_SX127X_CRF1 | GPIO_ANALOG); + stm32_configgpio(GPIO_SX127X_CRF2 | GPIO_ANALOG); + stm32_configgpio(GPIO_SX127X_CRF3 | GPIO_ANALOG); + + goto errout; + } + + /* Configure antena switch outputs */ + + stm32_configgpio(GPIO_SX127X_CRF1 | GPIO_OUTPUT | GPIO_OUTPUT_CLEAR); + stm32_configgpio(GPIO_SX127X_CRF2 | GPIO_OUTPUT | GPIO_OUTPUT_CLEAR); + stm32_configgpio(GPIO_SX127X_CRF3 | GPIO_OUTPUT | GPIO_OUTPUT_CLEAR); + + stm32_gpiowrite(GPIO_SX127X_CRF1, false); + stm32_gpiowrite(GPIO_SX127X_CRF2, false); + stm32_gpiowrite(GPIO_SX127X_CRF3, false); + + switch (opmode) + { + case SX127X_OPMODE_STANDBY: + case SX127X_OPMODE_FSRX: + case SX127X_OPMODE_FSTX: + { + break; + } + + case SX127X_OPMODE_TX: + { + /* Set TX RFO or TX BOOST */ + + if (g_high_power_output == true) + { + wlinfo("SET CRF3\n"); + stm32_gpiowrite(GPIO_SX127X_CRF3, true); + } + else + { + wlinfo("SET CRF2\n"); + stm32_gpiowrite(GPIO_SX127X_CRF2, true); + } + + break; + } + + case SX127X_OPMODE_RX: + case SX127X_OPMODE_RXSINGLE: + case SX127X_OPMODE_CAD: + { + /* Set antena RX */ + + wlinfo("SET CRF1\n"); + stm32_gpiowrite(GPIO_SX127X_CRF1, true); + + break; + } + + default: + { + wlerr("ERROR: invalid mode %d\n", opmode); + ret = -EINVAL; + break; + } + } + +errout: + return ret; +} + +/**************************************************************************** + * Name: sx127x_freq_select + ****************************************************************************/ + +static int sx127x_freq_select(uint32_t freq) +{ + int ret = OK; + + /* Only HF supported (BAND3 - 860-930 MHz) */ + + if (freq < SX127X_HFBAND_THR) + { + ret = -EINVAL; + wlerr("LF band not supported\n"); + } + + return ret; +} + +/**************************************************************************** + * Name: sx127x_pa_select + ****************************************************************************/ + +static int sx127x_pa_select(bool enable) +{ + g_high_power_output = enable; + return OK; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +int stm32_lpwaninitialize(void) +{ + struct spi_dev_s *spidev; + int ret = OK; + + wlinfo("Register the sx127x module\n"); + + /* Setup DIO0 */ + + stm32_configgpio(GPIO_SX127X_DIO0); + + /* Init SPI bus */ + + spidev = stm32_spibus_initialize(SX127X_SPI); + if (!spidev) + { + wlerr("ERROR: Failed to initialize SPI %d bus\n", SX127X_SPI); + ret = -ENODEV; + goto errout; + } + + /* Initialize SX127X */ + + ret = sx127x_register(spidev, &lower); + if (ret < 0) + { + wlerr("ERROR: Failed to register sx127x\n"); + goto errout; + } + +errout: + return ret; +} diff --git a/boards/arm/stm32l0/common/CMakeLists.txt b/boards/arm/stm32l0/common/CMakeLists.txt new file mode 100644 index 0000000000000..4ae413b13be07 --- /dev/null +++ b/boards/arm/stm32l0/common/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32l0/common/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(${NUTTX_DIR}/boards/arm/common/stm32 stm32_common) diff --git a/boards/arm/stm32l0/common/Kconfig b/boards/arm/stm32l0/common/Kconfig new file mode 100644 index 0000000000000..5c48f62a0258b --- /dev/null +++ b/boards/arm/stm32l0/common/Kconfig @@ -0,0 +1,6 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# + +source "boards/arm/common/stm32/Kconfig" diff --git a/boards/arm/stm32l0/common/Makefile b/boards/arm/stm32l0/common/Makefile new file mode 100644 index 0000000000000..17c365d758c87 --- /dev/null +++ b/boards/arm/stm32l0/common/Makefile @@ -0,0 +1,39 @@ +############################################################################# +# boards/arm/stm32l0/common/Makefile +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################# + +include $(TOPDIR)/Make.defs + +STM32_BOARD_COMMON_DIR := $(TOPDIR)$(DELIM)boards$(DELIM)arm$(DELIM)common$(DELIM)stm32 +STM32_COMMON_SRCDIR := $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)common$(DELIM)stm32 + +include board/Make.defs +include $(STM32_BOARD_COMMON_DIR)$(DELIM)src$(DELIM)Make.defs + +DEPPATH += --dep-path board + +include $(TOPDIR)/boards/Board.mk + +ARCHSRCDIR = $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src +BOARDDIR = $(ARCHSRCDIR)$(DELIM)board +CFLAGS += ${INCDIR_PREFIX}$(BOARDDIR)$(DELIM)include +CFLAGS += ${INCDIR_PREFIX}$(STM32_COMMON_SRCDIR) +CXXFLAGS += ${INCDIR_PREFIX}$(STM32_COMMON_SRCDIR) diff --git a/boards/arm/stm32l0/nucleo-l073rz/CMakeLists.txt b/boards/arm/stm32l0/nucleo-l073rz/CMakeLists.txt new file mode 100644 index 0000000000000..d660ec8525f44 --- /dev/null +++ b/boards/arm/stm32l0/nucleo-l073rz/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32l0/nucleo-l073rz/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/arm/stm32f0l0g0/nucleo-l073rz/Kconfig b/boards/arm/stm32l0/nucleo-l073rz/Kconfig similarity index 100% rename from boards/arm/stm32f0l0g0/nucleo-l073rz/Kconfig rename to boards/arm/stm32l0/nucleo-l073rz/Kconfig diff --git a/boards/arm/stm32l0/nucleo-l073rz/configs/nsh/defconfig b/boards/arm/stm32l0/nucleo-l073rz/configs/nsh/defconfig new file mode 100644 index 0000000000000..d4ddb1d55dd86 --- /dev/null +++ b/boards/arm/stm32l0/nucleo-l073rz/configs/nsh/defconfig @@ -0,0 +1,52 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_ARGCAT is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nucleo-l073rz" +CONFIG_ARCH_BOARD_NUCLEO_L073RZ=y +CONFIG_ARCH_CHIP="stm32l0" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32L073RZ=y +CONFIG_ARCH_CHIP_STM32L073XX=y +CONFIG_ARCH_CHIP_STM32L0=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=2796 +CONFIG_BUILTIN=y +CONFIG_DISABLE_ENVIRON=y +CONFIG_DISABLE_MOUNTPOINT=y +CONFIG_DISABLE_MQUEUE=y +CONFIG_DISABLE_POSIX_TIMERS=y +CONFIG_DISABLE_PSEUDOFS_OPERATIONS=y +CONFIG_EXAMPLES_HELLO=y +CONFIG_EXPERIMENTAL=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=1536 +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=64 +CONFIG_NSH_READLINE=y +CONFIG_NUNGET_CHARS=0 +CONFIG_POSIX_SPAWN_DEFAULT_STACKSIZE=1536 +CONFIG_PTHREAD_MUTEX_UNSAFE=y +CONFIG_PTHREAD_STACK_DEFAULT=1536 +CONFIG_RAM_SIZE=20480 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=19 +CONFIG_START_MONTH=5 +CONFIG_START_YEAR=2013 +CONFIG_STDIO_DISABLE_BUFFERING=y +CONFIG_STM32_PWR=y +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32l0/nucleo-l073rz/configs/sx127x/defconfig b/boards/arm/stm32l0/nucleo-l073rz/configs/sx127x/defconfig new file mode 100644 index 0000000000000..32220b19127c1 --- /dev/null +++ b/boards/arm/stm32l0/nucleo-l073rz/configs/sx127x/defconfig @@ -0,0 +1,62 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_ARGCAT is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nucleo-l073rz" +CONFIG_ARCH_BOARD_NUCLEO_L073RZ=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32l0" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32L073RZ=y +CONFIG_ARCH_CHIP_STM32L073XX=y +CONFIG_ARCH_CHIP_STM32L0=y +CONFIG_ARCH_IRQBUTTONS=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=2796 +CONFIG_BUILTIN=y +CONFIG_DISABLE_ENVIRON=y +CONFIG_DISABLE_MOUNTPOINT=y +CONFIG_DISABLE_MQUEUE=y +CONFIG_DISABLE_POSIX_TIMERS=y +CONFIG_DISABLE_PSEUDOFS_OPERATIONS=y +CONFIG_DRIVERS_LPWAN=y +CONFIG_DRIVERS_WIRELESS=y +CONFIG_EXAMPLES_HELLO=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=1536 +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_LPWAN_SX127X=y +CONFIG_LPWAN_SX127X_FSKOOK=y +CONFIG_LPWAN_SX127X_MODULATION_DEFAULT=1 +CONFIG_LPWAN_SX127X_RXSUPPORT=y +CONFIG_LPWAN_SX127X_TXSUPPORT=y +CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=64 +CONFIG_NSH_READLINE=y +CONFIG_NUNGET_CHARS=0 +CONFIG_POSIX_SPAWN_DEFAULT_STACKSIZE=1536 +CONFIG_PTHREAD_MUTEX_UNSAFE=y +CONFIG_PTHREAD_STACK_DEFAULT=1536 +CONFIG_RAM_SIZE=20480 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=19 +CONFIG_START_MONTH=5 +CONFIG_START_YEAR=2013 +CONFIG_STDIO_DISABLE_BUFFERING=y +CONFIG_STM32_PWR=y +CONFIG_STM32_SPI1=y +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32l0/nucleo-l073rz/include/board.h b/boards/arm/stm32l0/nucleo-l073rz/include/board.h new file mode 100644 index 0000000000000..af284ca168eaf --- /dev/null +++ b/boards/arm/stm32l0/nucleo-l073rz/include/board.h @@ -0,0 +1,203 @@ +/**************************************************************************** + * boards/arm/stm32l0/nucleo-l073rz/include/board.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_STM32F0L0G0_NUCLEO_L073RZ_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32F0L0G0_NUCLEO_L073RZ_INCLUDE_BOARD_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#ifndef __ASSEMBLY__ +# include +# include +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Clocking *****************************************************************/ + +/* HSI - Internal 8 MHz RC Oscillator + * LSI - 32 KHz RC + * HSE - 8 MHz from MCO output of ST-LINK + * LSE - 32.768 kHz + */ + +#define STM32_BOARD_XTAL 8000000ul + +#define STM32_HSEBYP_ENABLE +#define STM32_HSI_FREQUENCY 8000000ul +#define STM32_LSI_FREQUENCY 32000 /* Between 30kHz and 60kHz */ +#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL +#define STM32_LSE_FREQUENCY 32768 /* X2 on board */ + +/* PLL source is HSE/1, PLL multiplier is 8: + * PLL frequency is 8MHz (XTAL) x 8 = 64MHz + */ + +#define STM32_CFGR_PLLSRC RCC_CFGR_PLLSRC +#define STM32_CFGR_PLLXTPRE 0 +#define STM32_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx8 +#define STM32_PLL_FREQUENCY (8*STM32_BOARD_XTAL) + +/* Use the PLL and set the SYSCLK source to be the PLL/2 (32MHz) */ + +#define STM32_SYSCLK_SW RCC_CFGR_SW_PLL +#define STM32_SYSCLK_SWS RCC_CFGR_SWS_PLL +#define STM32_CFGR_PLLDIV RCC_CFGR_PLLDIV_2 +#define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY/2 + +/* AHB clock (HCLK) is SYSCLK (32MHz) */ + +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY + +/* APB2 clock (PCLK2) is HCLK (32MHz) */ + +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK +#define STM32_PCLK2_FREQUENCY STM32_HCLK_FREQUENCY +#define STM32_APB2_CLKIN (STM32_PCLK2_FREQUENCY) + +/* APB1 clock (PCLK1) is HCLK/2 (16MHz) */ + +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd2 +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/2) + +/* 48MHz clock configuration */ + +#if defined(CONFIG_STM32_USB) || defined(CONFIG_STM32_RNG) +# define STM32_USE_CLK48 1 +# define STM32_CLK48_SEL RCC_CCIPR_CLK48SEL_HSI48 +# define STM32_HSI48_SYNCSRC SYNCSRC_NONE +#endif + +/* TODO: timers */ + +/* LED definitions **********************************************************/ + +/* The Nucleo LO73RZ board has three LEDs. Two of these are controlled by + * logic on the board and are not available for software control: + * + * LD1 COM: LD1 default status is red. LD1 turns to green to indicate that + * communications are in progress between the PC and the + * ST-LINK/V2-1. + * LD3 PWR: red LED indicates that the board is powered. + * + * And one can be controlled by software: + * + * User LD2: green LED is a user LED connected to the I/O PA5 of the + * STM32LO73RZ. + * + * If CONFIG_ARCH_LEDS is not defined, then the user can control the LED in + * any way. The following definition is used to access the LED. + */ + +/* LED index values for use with board_userled() */ + +#define BOARD_LED1 0 /* User LD2 */ +#define BOARD_NLEDS 1 + +/* LED bits for use with board_userled_all() */ + +#define BOARD_LED1_BIT (1 << BOARD_LED1) + +/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the LED on board + * the Nucleo LO73RZ. The following definitions describe how NuttX controls + * the LED: + * + * SYMBOL Meaning LED1 state + * ------------------ ----------------------- ---------- + * LED_STARTED NuttX has been started OFF + * LED_HEAPALLOCATE Heap has been allocated OFF + * LED_IRQSENABLED Interrupts enabled OFF + * LED_STACKCREATED Idle stack created ON + * LED_INIRQ In an interrupt No change + * LED_SIGNAL In a signal handler No change + * LED_ASSERTION An assertion failed No change + * LED_PANIC The system has crashed Blinking + * LED_IDLE STM32 is in sleep mode Not used + */ + +#define LED_STARTED 0 +#define LED_HEAPALLOCATE 0 +#define LED_IRQSENABLED 0 +#define LED_STACKCREATED 1 +#define LED_INIRQ 2 +#define LED_SIGNAL 2 +#define LED_ASSERTION 2 +#define LED_PANIC 1 + +/* Button definitions *******************************************************/ + +/* The Nucleo LO73RZ supports two buttons; only one button is controllable + * by software: + * + * B1 USER: user button connected to the I/O PC13 of the STM32LO73RZ. + * B2 RESET: push button connected to NRST is used to RESET the + * STM32LO73RZ. + */ + +#define BUTTON_USER 0 +#define NUM_BUTTONS 1 + +#define BUTTON_USER_BIT (1 << BUTTON_USER) + +/* Alternate function pin selections ****************************************/ + +/* I2C */ + +#define GPIO_I2C1_SCL (GPIO_I2C1_SCL_2|GPIO_SPEED_LOW) /* D15 - PB8 */ +#define GPIO_I2C1_SDA (GPIO_I2C1_SDA_2|GPIO_SPEED_LOW) /* D14 - PB9 */ + +/* SPI1 */ + +#define GPIO_SPI1_MISO (GPIO_SPI1_MISO_2|GPIO_SPEED_MEDIUM) /* D12 - PA6 */ +#define GPIO_SPI1_MOSI (GPIO_SPI1_MOSI_2|GPIO_SPEED_MEDIUM) /* D11 - PA7 */ +#define GPIO_SPI1_SCK (GPIO_SPI1_SCK_1|GPIO_SPEED_MEDIUM) /* D13 - PA5 */ + +/* SPI2 */ + +#define GPIO_SPI2_MISO (GPIO_SPI2_MISO_1|GPIO_SPEED_MEDIUM) /* PB14 */ +#define GPIO_SPI2_MOSI (GPIO_SPI2_MOSI_1|GPIO_SPEED_MEDIUM) /* PB15 */ +#define GPIO_SPI2_SCK (GPIO_SPI2_SCK_1|GPIO_SPEED_MEDIUM) /* PB10 */ + +/* USART */ + +/* By default the USART2 is connected to STLINK Virtual COM Port: + * USART2_RX - PA3 + * USART2_TX - PA2 + */ + +#define GPIO_USART2_RX (GPIO_USART2_RX_1|GPIO_SPEED_HIGH) /* PA3 */ +#define GPIO_USART2_TX (GPIO_USART2_TX_1|GPIO_SPEED_HIGH) /* PA2 */ + +/* DMA channels *************************************************************/ + +/* ADC */ + +#define ADC1_DMA_CHAN DMACHAN_ADC1 /* DMA1_CH1 */ + +#endif /* __BOARDS_ARM_STM32F0L0G0_NUCLEO_LO73RZ_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32l0/nucleo-l073rz/scripts/Make.defs b/boards/arm/stm32l0/nucleo-l073rz/scripts/Make.defs new file mode 100644 index 0000000000000..596e9665da7c2 --- /dev/null +++ b/boards/arm/stm32l0/nucleo-l073rz/scripts/Make.defs @@ -0,0 +1,41 @@ +############################################################################ +# boards/arm/stm32l0/nucleo-l073rz/scripts/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/.config +include $(TOPDIR)/tools/Config.mk +include $(TOPDIR)/arch/arm/src/armv6-m/Toolchain.defs + +LDSCRIPT = ld.script +ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) + +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32l0/nucleo-l073rz/scripts/ld.script b/boards/arm/stm32l0/nucleo-l073rz/scripts/ld.script new file mode 100644 index 0000000000000..2156f68042fc3 --- /dev/null +++ b/boards/arm/stm32l0/nucleo-l073rz/scripts/ld.script @@ -0,0 +1,115 @@ +/**************************************************************************** + * boards/arm/stm32l0/nucleo-l073rz/scripts/ld.script + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* The STM32LO73RZ has 192Kb of FLASH beginning at address 0x0800:0000. + * 20Kb of SRAM and 6Kb of EEPROM + * + * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 + * where the code expects to begin execution by jumping to the entry point in + * the 0x0800:0000 address range. + */ + +MEMORY +{ + flash (rx) : ORIGIN = 0x08000000, LENGTH = 192K + sram (rwx) : ORIGIN = 0x20000000, LENGTH = 20K +} + +OUTPUT_ARCH(arm) +EXTERN(_vectors) +ENTRY(_stext) +SECTIONS +{ + .text : { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > flash + + .init_section : ALIGN(4) { + _sinit = ABSOLUTE(.); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) + _einit = ABSOLUTE(.); + } > flash + + .ARM.extab : ALIGN(4) { + *(.ARM.extab*) + } > flash + + .ARM.exidx : ALIGN(4) { + __exidx_start = ABSOLUTE(.); + *(.ARM.exidx*) + __exidx_end = ABSOLUTE(.); + } > flash + + _eronly = ABSOLUTE(.); + + /* The RAM vector table (if present) should lie at the beginning of SRAM */ + + .ram_vectors : { + *(.ram_vectors) + } > sram + + .data : ALIGN(4) { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > sram AT > flash + + .bss : ALIGN(4) { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + _ebss = ABSOLUTE(.); + } > sram + + /* Stabs debugging sections. */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/stm32l0/nucleo-l073rz/src/CMakeLists.txt b/boards/arm/stm32l0/nucleo-l073rz/src/CMakeLists.txt new file mode 100644 index 0000000000000..b70c2615c82b6 --- /dev/null +++ b/boards/arm/stm32l0/nucleo-l073rz/src/CMakeLists.txt @@ -0,0 +1,53 @@ +# ############################################################################## +# boards/arm/stm32l0/nucleo-l073rz/src/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(SRCS stm32_boot.c stm32_bringup.c) + +if(CONFIG_ARCH_LEDS) + list(APPEND SRCS stm32_autoleds.c) +else() + list(APPEND SRCS stm32_userleds.c) +endif() + +if(CONFIG_ARCH_BUTTONS) + list(APPEND SRCS stm32_buttons.c) +endif() + +if(CONFIG_STM32_SPI) + list(APPEND SRCS stm32_spi.c) +endif() + +if(CONFIG_WL_NRF24L01) + list(APPEND SRCS stm32_nrf24l01.c) +endif() + +if(CONFIG_LPWAN_SX127X) + list(APPEND SRCS stm32_sx127x.c) +endif() + +if(CONFIG_CL_MFRC522) + list(APPEND SRCS stm32_mfrc522.c) +endif() + +target_sources(board PRIVATE ${SRCS}) + +set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/ld.script") diff --git a/boards/arm/stm32l0/nucleo-l073rz/src/Make.defs b/boards/arm/stm32l0/nucleo-l073rz/src/Make.defs new file mode 100644 index 0000000000000..f29673903468f --- /dev/null +++ b/boards/arm/stm32l0/nucleo-l073rz/src/Make.defs @@ -0,0 +1,55 @@ +############################################################################ +# boards/arm/stm32l0/nucleo-l073rz/src/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +CSRCS = stm32_boot.c stm32_bringup.c + +ifeq ($(CONFIG_ARCH_LEDS),y) +CSRCS += stm32_autoleds.c +else +CSRCS += stm32_userleds.c +endif + +ifeq ($(CONFIG_ARCH_BUTTONS),y) +CSRCS += stm32_buttons.c +endif + +ifeq ($(CONFIG_STM32_SPI),y) +CSRCS += stm32_spi.c +endif + +ifeq ($(CONFIG_WL_NRF24L01),y) +CSRCS += stm32_nrf24l01.c +endif + +ifeq ($(CONFIG_LPWAN_SX127X),y) +CSRCS += stm32_sx127x.c +endif + +ifeq ($(CONFIG_CL_MFRC522),y) +CSRCS += stm32_mfrc522.c +endif + +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32f0l0g0/nucleo-l073rz/src/nucleo-l073rz.h b/boards/arm/stm32l0/nucleo-l073rz/src/nucleo-l073rz.h similarity index 98% rename from boards/arm/stm32f0l0g0/nucleo-l073rz/src/nucleo-l073rz.h rename to boards/arm/stm32l0/nucleo-l073rz/src/nucleo-l073rz.h index 7e17a772c3682..f72a20312f5fd 100644 --- a/boards/arm/stm32f0l0g0/nucleo-l073rz/src/nucleo-l073rz.h +++ b/boards/arm/stm32l0/nucleo-l073rz/src/nucleo-l073rz.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-l073rz/src/nucleo-l073rz.h + * boards/arm/stm32l0/nucleo-l073rz/src/nucleo-l073rz.h * * SPDX-License-Identifier: Apache-2.0 * @@ -140,7 +140,7 @@ int stm32_bringup(void); * ****************************************************************************/ -#ifdef CONFIG_STM32F0L0G0_SPI +#ifdef CONFIG_STM32_SPI void stm32_spidev_initialize(void); #endif diff --git a/boards/arm/stm32l0/nucleo-l073rz/src/stm32_autoleds.c b/boards/arm/stm32l0/nucleo-l073rz/src/stm32_autoleds.c new file mode 100644 index 0000000000000..ffe74f73f87a8 --- /dev/null +++ b/boards/arm/stm32l0/nucleo-l073rz/src/stm32_autoleds.c @@ -0,0 +1,81 @@ +/**************************************************************************** + * boards/arm/stm32l0/nucleo-l073rz/src/stm32_autoleds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include + +#include "stm32_gpio.h" +#include "nucleo-l073rz.h" + +#include + +#ifdef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_autoled_initialize + ****************************************************************************/ + +void board_autoled_initialize(void) +{ + /* Configure LED1 GPIO for output */ + + stm32_configgpio(GPIO_LED1); +} + +/**************************************************************************** + * Name: board_autoled_on + ****************************************************************************/ + +void board_autoled_on(int led) +{ + if (led == BOARD_LED1) + { + stm32_gpiowrite(GPIO_LED1, true); + } +} + +/**************************************************************************** + * Name: board_autoled_off + ****************************************************************************/ + +void board_autoled_off(int led) +{ + if (led == BOARD_LED1) + { + stm32_gpiowrite(GPIO_LED1, false); + } +} + +#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32l0/nucleo-l073rz/src/stm32_boot.c b/boards/arm/stm32l0/nucleo-l073rz/src/stm32_boot.c new file mode 100644 index 0000000000000..8ee936849c333 --- /dev/null +++ b/boards/arm/stm32l0/nucleo-l073rz/src/stm32_boot.c @@ -0,0 +1,101 @@ +/**************************************************************************** + * boards/arm/stm32l0/nucleo-l073rz/src/stm32_boot.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include "nucleo-l073rz.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_boardinitialize + * + * Description: + * All STM32 architectures must provide the following entry point. This + * entry point is called early in the initialization -- after all memory + * has been configured and mapped but before any devices have been + * initialized. + * + ****************************************************************************/ + +void stm32_boardinitialize(void) +{ +#ifdef CONFIG_ARCH_LEDS + /* Configure on-board LEDs if LED support has been selected. */ + + board_autoled_initialize(); +#endif + +#ifdef CONFIG_STM32_SPI + /* Configure SPI chip selects */ + + stm32_spidev_initialize(); +#endif +} + +/**************************************************************************** + * Name: board_late_initialize + * + * Description: + * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_late_initialize(). board_late_initialize() will + * be called immediately after up_initialize() is called and just before + * the initial application is started. This additional initialization + * phase may be used, for example, to initialize board-specific device + * drivers. + * + ****************************************************************************/ + +#ifdef CONFIG_BOARD_LATE_INITIALIZE +void board_late_initialize(void) +{ + /* Perform board-specific initialization */ + + stm32_bringup(); +} +#endif diff --git a/boards/arm/stm32l0/nucleo-l073rz/src/stm32_bringup.c b/boards/arm/stm32l0/nucleo-l073rz/src/stm32_bringup.c new file mode 100644 index 0000000000000..3a573ba1c8d59 --- /dev/null +++ b/boards/arm/stm32l0/nucleo-l073rz/src/stm32_bringup.c @@ -0,0 +1,151 @@ +/**************************************************************************** + * boards/arm/stm32l0/nucleo-l073rz/src/stm32_bringup.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include + +#include "nucleo-l073rz.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#undef HAVE_LEDS +#undef HAVE_DAC + +#if !defined(CONFIG_ARCH_LEDS) && defined(CONFIG_USERLED_LOWER) +# define HAVE_LEDS 1 +#endif + +#if defined(CONFIG_DAC) +# define HAVE_DAC1 1 +# define HAVE_DAC2 1 +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_bringup + * + * Description: + * Perform architecture-specific initialization + * + * CONFIG_BOARD_LATE_INITIALIZE=y : + * Called from board_late_initialize(). + * + ****************************************************************************/ + +int stm32_bringup(void) +{ + int ret; + +#ifdef HAVE_LEDS + /* Register the LED driver */ + + ret = userled_lower_initialize(LED_DRIVER_PATH); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: userled_lower_initialize() failed: %d\n", ret); + return ret; + } +#endif + +#ifdef CONFIG_ADC + /* Initialize ADC and register the ADC driver. */ + + ret = stm32_adc_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_adc_setup failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_DAC + /* Initialize DAC and register the DAC driver. */ + + ret = stm32_dac_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_dac_setup failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_COMP + /* Initialize COMP and register the COMP driver. */ + + ret = stm32_comp_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_comp_setup failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_OPAMP + /* Initialize OPAMP and register the OPAMP driver. */ + + ret = stm32_opamp_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_opamp_setup failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_WL_NRF24L01 + ret = stm32_wlinitialize(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to initialize wireless driver: %d\n", + ret); + } +#endif /* CONFIG_WL_NRF24L01 */ + +#ifdef CONFIG_LPWAN_SX127X + ret = stm32_lpwaninitialize(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to initialize wireless driver: %d\n", + ret); + } +#endif /* CONFIG_LPWAN_SX127X */ + +#ifdef CONFIG_CL_MFRC522 + ret = stm32_mfrc522initialize("/dev/rfid0"); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_mfrc522initialize() failed: %d\n", ret); + } +#endif /* CONFIG_CL_MFRC522 */ + + UNUSED(ret); + return OK; +} diff --git a/boards/arm/stm32l0/nucleo-l073rz/src/stm32_buttons.c b/boards/arm/stm32l0/nucleo-l073rz/src/stm32_buttons.c new file mode 100644 index 0000000000000..5f59392762ab5 --- /dev/null +++ b/boards/arm/stm32l0/nucleo-l073rz/src/stm32_buttons.c @@ -0,0 +1,118 @@ +/**************************************************************************** + * boards/arm/stm32l0/nucleo-l073rz/src/stm32_buttons.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "stm32_gpio.h" +#include "nucleo-l073rz.h" + +#include + +#ifdef CONFIG_ARCH_BUTTONS + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_button_initialize + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. + * + ****************************************************************************/ + +uint32_t board_button_initialize(void) +{ + /* Configure the single button as an input. NOTE that EXTI interrupts are + * also configured for the pin. + */ + + stm32_configgpio(GPIO_BTN_USER); + return NUM_BUTTONS; +} + +/**************************************************************************** + * Name: board_buttons + ****************************************************************************/ + +uint32_t board_buttons(void) +{ + /* Check that state of each USER button. A LOW value means that the key is + * pressed. + */ + + bool released = stm32_gpioread(GPIO_BTN_USER); + return !released; +} + +/**************************************************************************** + * Button support. + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. + * + * After board_button_initialize() has been called, board_buttons() may be + * called to collect the state of all buttons. board_buttons() returns an + * 32-bit bit set with each bit associated with a button. See the + * BUTTON_*_BIT definitions in board.h for the meaning of each bit. + * + * board_button_irq() may be called to register an interrupt handler that + * will be called when a button is depressed or released. The ID value is a + * button enumeration value that uniquely identifies a button resource. See + * the BUTTON_* definitions in board.h for the meaning of enumeration + * value. + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_IRQBUTTONS +int board_button_irq(int id, xcpt_t irqhandler, void *arg) +{ + int ret = -EINVAL; + + if (id == BUTTON_USER) + { + ret = stm32_gpiosetevent(GPIO_BTN_USER, true, true, true, + irqhandler, arg); + } + + return ret; +} +#endif +#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/stm32l0/nucleo-l073rz/src/stm32_mfrc522.c b/boards/arm/stm32l0/nucleo-l073rz/src/stm32_mfrc522.c new file mode 100644 index 0000000000000..4cbc3ee003cad --- /dev/null +++ b/boards/arm/stm32l0/nucleo-l073rz/src/stm32_mfrc522.c @@ -0,0 +1,97 @@ +/**************************************************************************** + * boards/arm/stm32l0/nucleo-l073rz/src/stm32_mfrc522.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include + +#include "stm32.h" +#include "stm32_spi.h" +#include "nucleo-l073rz.h" + +#if defined(CONFIG_SPI) && defined(CONFIG_STM32_SPI2) && defined(CONFIG_CL_MFRC522) + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define MFRC522_SPI_PORTNO 2 /* On SPI2 */ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_mfrc522initialize + * + * Description: + * Initialize and register the MFRC522 RFID driver. + * + * Input Parameters: + * devpath - The full path to the driver to register. E.g., "/dev/rfid0" + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +int stm32_mfrc522initialize(const char *devpath) +{ + struct spi_dev_s *spi; + int ret; + + /* Configure MFRC522 reset */ + + stm32_configgpio(GPIO_MFRC522_RESET); + + /* MFRC522 hardware reset on rising edge */ + + stm32_gpiowrite(GPIO_MFRC522_RESET, true); + + /* Initialize SPI */ + + spi = stm32_spibus_initialize(MFRC522_SPI_PORTNO); + if (!spi) + { + return -ENODEV; + } + + /* Then register the MFRC522 */ + + ret = mfrc522_register(devpath, spi); + if (ret < 0) + { + snerr("ERROR: Error registering MFRC522\n"); + } + + return ret; +} + +#endif /* CONFIG_SPI && CONFIG_MFRC522 */ diff --git a/boards/arm/stm32l0/nucleo-l073rz/src/stm32_nrf24l01.c b/boards/arm/stm32l0/nucleo-l073rz/src/stm32_nrf24l01.c new file mode 100644 index 0000000000000..4b3e1311e5823 --- /dev/null +++ b/boards/arm/stm32l0/nucleo-l073rz/src/stm32_nrf24l01.c @@ -0,0 +1,123 @@ +/**************************************************************************** + * boards/arm/stm32l0/nucleo-l073rz/src/stm32_nrf24l01.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include +#include + +#include "arm_internal.h" +#include "chip.h" +#include "stm32.h" +#include "nucleo-l073rz.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define NRF24L01_SPI 1 + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +static int nrf24l01_irq_attach(xcpt_t isr, void *arg); +static void nrf24l01_chip_enable(bool enable); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static struct nrf24l01_config_s nrf_cfg = +{ + .irqattach = nrf24l01_irq_attach, + .chipenable = nrf24l01_chip_enable, +}; + +static xcpt_t g_isr; +static void *g_arg; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +static int nrf24l01_irq_attach(xcpt_t isr, void *arg) +{ + wlinfo("Attach IRQ\n"); + g_isr = isr; + g_arg = arg; + stm32_gpiosetevent(GPIO_NRF24L01_IRQ, false, true, false, g_isr, g_arg); + return OK; +} + +static void nrf24l01_chip_enable(bool enable) +{ + wlinfo("CE:%d\n", enable); + stm32_gpiowrite(GPIO_NRF24L01_CE, enable); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +int stm32_wlinitialize(void) +{ + struct spi_dev_s *spidev; + int ret = OK; + + syslog(LOG_INFO, "Register the nRF24L01 module\n"); + + /* Setup CE & IRQ line IOs */ + + stm32_configgpio(GPIO_NRF24L01_CE); + stm32_configgpio(GPIO_NRF24L01_IRQ); + + /* Init SPI bus */ + + spidev = stm32_spibus_initialize(NRF24L01_SPI); + if (!spidev) + { + wlerr("ERROR: Failed to initialize SPI %d bus\n", NRF24L01_SPI); + ret = -ENODEV; + goto errout; + } + + ret = nrf24l01_register(spidev, &nrf_cfg); + if (ret != OK) + { + wlerr("ERROR: Failed to register initialize SPI bus\n"); + goto errout; + } + +errout: + return ret; +} diff --git a/boards/arm/stm32l0/nucleo-l073rz/src/stm32_spi.c b/boards/arm/stm32l0/nucleo-l073rz/src/stm32_spi.c new file mode 100644 index 0000000000000..3daa75311914e --- /dev/null +++ b/boards/arm/stm32l0/nucleo-l073rz/src/stm32_spi.c @@ -0,0 +1,261 @@ +/**************************************************************************** + * boards/arm/stm32l0/nucleo-l073rz/src/stm32_spi.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include + +#include "arm_internal.h" +#include "chip.h" +#include "stm32_gpio.h" +#include "stm32_spi.h" + +#include "nucleo-l073rz.h" +#include + +#ifdef CONFIG_STM32_SPI + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_spidev_initialize + * + * Description: + * Called to configure SPI chip select GPIO pins for the Nucleo-144 board. + * + ****************************************************************************/ + +void stm32_spidev_initialize(void) +{ + /* NOTE: Clocking for SPI1 and/or SPI3 was already provided in stm32_rcc.c. + * Configurations of SPI pins is performed in stm32_spi.c. + * Here, we only initialize chip select pins unique to the board + * architecture. + */ + +#ifdef CONFIG_STM32_SPI1 + +# ifdef CONFIG_WL_NRF24L01 + /* Configure the SPI-based NRF24L01 chip select GPIO */ + + spiinfo("Configure GPIO for NRF24L01 SPI1/CS\n"); + + stm32_configgpio(GPIO_NRF24L01_CS); + stm32_gpiowrite(GPIO_NRF24L01_CS, true); +# endif + +# ifdef CONFIG_LPWAN_SX127X + /* Configure the SPI-based SX127X chip select GPIO */ + + spiinfo("Configure GPIO for SX127X SPI1/CS\n"); + + stm32_configgpio(GPIO_SX127X_CS); + stm32_gpiowrite(GPIO_SX127X_CS, true); +# endif + +#endif /* CONFIG_STM32_SPI1 */ + +#ifdef CONFIG_STM32_SPI2 + /* Configure the SPI-based MFRC522 chip select GPIO */ + +# ifdef CONFIG_CL_MFRC522 + stm32_configgpio(GPIO_MFRC522_CS); +# endif + +#endif /* CONFIG_STM32_SPI2 */ +} + +/**************************************************************************** + * Name: stm32_spi1/2/select and stm32_spi1/2/status + * + * Description: + * The external functions, stm32_spi1/2select and stm32_spi1/2status + * must be provided by board-specific logic. They are implementations of + * the select and status methods of the SPI interface defined by struct + * spi_ops_s (see include/nuttx/spi/spi.h). All other methods (including + * stm32_spibus_initialize()) are provided by common STM32 logic. + * To use this common SPI logic on your board: + * + * 1. Provide logic in stm32_boardinitialize() to configure SPI chip select + * pins. + * 2. Provide stm32_spi1/2select() and stm32_spi1/2status() functions + * in your board-specific logic. These functions will perform chip + * selection and status operations using GPIOs in the way your board is + * configured. + * 3. Add a calls to stm32_spibus_initialize() in your low level + * application initialization logic + * 4. The handle returned by stm32_spibus_initialize() may then be used to + * bind the SPI driver to higher level logic (e.g., calling + * mmcsd_spislotinitialize(), for example, will bind the SPI driver to + * the SPI MMC/SD driver). + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_SPI1 +void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, + bool selected) +{ + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); + + switch (devid) + { +#ifdef CONFIG_WL_NRF24L01 + case SPIDEV_WIRELESS(0): + { + spiinfo("nRF24L01 device %s\n", + selected ? "asserted" : "de-asserted"); + + /* Set the GPIO low to select and high to de-select */ + + stm32_gpiowrite(GPIO_NRF24L01_CS, !selected); + break; + } +#endif + +#ifdef CONFIG_LPWAN_SX127X + case SPIDEV_LPWAN(0): + { + spiinfo("SX127X device %s\n", + selected ? "asserted" : "de-asserted"); + + /* Set the GPIO low to select and high to de-select */ + + stm32_gpiowrite(GPIO_SX127X_CS, !selected); + break; + } +#endif + + default: + { + break; + } + } +} + +uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) +{ + uint8_t status = 0; + + switch (devid) + { +#ifdef CONFIG_WL_NRF24L01 + case SPIDEV_WIRELESS(0): + { + status |= SPI_STATUS_PRESENT; + break; + } +#endif + +#ifdef CONFIG_LPWAN_SX127X + case SPIDEV_LPWAN(0): + { + status |= SPI_STATUS_PRESENT; + break; + } +#endif + + default: + { + break; + } + } + + return status; +} +#endif /* CONFIG_STM32_SPI1 */ + +#ifdef CONFIG_STM32_SPI2 +void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid, + bool selected) +{ + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); + + switch (devid) + { +#ifdef CONFIG_CL_MFRC522 + case SPIDEV_CONTACTLESS(0): + { + stm32_gpiowrite(GPIO_MFRC522_CS, !selected); + } +#endif + + default: + { + break; + } + } +} + +uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) +{ + uint8_t status = 0; + + switch (devid) + { +#ifdef CONFIG_CL_MFRC522 + case SPIDEV_CONTACTLESS(0): + { + status |= SPI_STATUS_PRESENT; + break; + } +#endif + + default: + { + break; + } + } + + return status; +} +#endif /* CONFIG_STM32_SPI2 */ + +#endif diff --git a/boards/arm/stm32l0/nucleo-l073rz/src/stm32_sx127x.c b/boards/arm/stm32l0/nucleo-l073rz/src/stm32_sx127x.c new file mode 100644 index 0000000000000..1893e1797354d --- /dev/null +++ b/boards/arm/stm32l0/nucleo-l073rz/src/stm32_sx127x.c @@ -0,0 +1,212 @@ +/**************************************************************************** + * boards/arm/stm32l0/nucleo-l073rz/src/stm32_sx127x.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include "stm32_gpio.h" +#include "stm32_exti.h" +#include "stm32_spi.h" + +#include "nucleo-l073rz.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* SX127X on SPI1 bus */ + +#define SX127X_SPI 1 + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +static void sx127x_chip_reset(void); +static int sx127x_opmode_change(int opmode); +static int sx127x_freq_select(uint32_t freq); +static int sx127x_pa_select(bool enable); +static int sx127x_irq0_attach(xcpt_t isr, void *arg); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +struct sx127x_lower_s lower = +{ + .irq0attach = sx127x_irq0_attach, + .reset = sx127x_chip_reset, + .opmode_change = sx127x_opmode_change, + .freq_select = sx127x_freq_select, + .pa_select = sx127x_pa_select, + .pa_force = true +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: sx127x_irq0_attach + ****************************************************************************/ + +static int sx127x_irq0_attach(xcpt_t isr, void *arg) +{ + wlinfo("Attach DIO0 IRQ\n"); + + /* IRQ on rising edge */ + + stm32_gpiosetevent(GPIO_SX127X_DIO0, true, false, false, isr, arg); + return OK; +} + +/**************************************************************************** + * Name: sx127x_chip_reset + ****************************************************************************/ + +static void sx127x_chip_reset(void) +{ + wlinfo("SX127X RESET\n"); + + /* Configure reset as output */ + + stm32_configgpio(GPIO_SX127X_RESET | GPIO_OUTPUT | GPIO_SPEED_HIGH | + GPIO_OUTPUT_CLEAR); + + /* Set pin to zero */ + + stm32_gpiowrite(GPIO_SX127X_RESET, false); + + /* Wait 1 ms */ + + nxsched_usleep(1000); + + /* Configure reset as input */ + + stm32_configgpio(GPIO_SX127X_RESET | GPIO_INPUT | GPIO_FLOAT); + + /* Wait 10 ms */ + + nxsched_usleep(10000); +} + +/**************************************************************************** + * Name: sx127x_opmode_change + ****************************************************************************/ + +static int sx127x_opmode_change(int opmode) +{ + /* Do nothing */ + + return OK; +} + +/**************************************************************************** + * Name: sx127x_freq_select + ****************************************************************************/ + +static int sx127x_freq_select(uint32_t freq) +{ + int ret = OK; + + /* NOTE: this depends on your module version */ + + if (freq > SX127X_HFBAND_THR) + { + ret = -EINVAL; + wlerr("HF band not supported\n"); + } + + return ret; +} + +/**************************************************************************** + * Name: sx127x_pa_select + ****************************************************************************/ + +static int sx127x_pa_select(bool enable) +{ + int ret = OK; + + /* Only PA_BOOST output connected to antenna */ + + if (enable == false) + { + ret = -EINVAL; + wlerr("Module supports only PA_BOOST pin, " + "so PA_SELECT must be enabled!\n"); + } + + return ret; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +int stm32_lpwaninitialize(void) +{ + struct spi_dev_s *spidev; + int ret = OK; + + wlinfo("Register the sx127x module\n"); + + /* Setup DIO0 */ + + stm32_configgpio(GPIO_SX127X_DIO0); + + /* Init SPI bus */ + + spidev = stm32_spibus_initialize(SX127X_SPI); + if (!spidev) + { + wlerr("ERROR: Failed to initialize SPI %d bus\n", SX127X_SPI); + ret = -ENODEV; + goto errout; + } + + /* Initialize SX127X */ + + ret = sx127x_register(spidev, &lower); + if (ret < 0) + { + wlerr("ERROR: Failed to register sx127x\n"); + goto errout; + } + +errout: + return ret; +} diff --git a/boards/arm/stm32l0/stm32l0538-disco/CMakeLists.txt b/boards/arm/stm32l0/stm32l0538-disco/CMakeLists.txt new file mode 100644 index 0000000000000..32e681f9f1be1 --- /dev/null +++ b/boards/arm/stm32l0/stm32l0538-disco/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32l0/stm32l0538-disco/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/arm/stm32f0l0g0/stm32l0538-disco/Kconfig b/boards/arm/stm32l0/stm32l0538-disco/Kconfig similarity index 100% rename from boards/arm/stm32f0l0g0/stm32l0538-disco/Kconfig rename to boards/arm/stm32l0/stm32l0538-disco/Kconfig diff --git a/boards/arm/stm32l0/stm32l0538-disco/configs/nsh/defconfig b/boards/arm/stm32l0/stm32l0538-disco/configs/nsh/defconfig new file mode 100644 index 0000000000000..7a823b72968f6 --- /dev/null +++ b/boards/arm/stm32l0/stm32l0538-disco/configs/nsh/defconfig @@ -0,0 +1,49 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_SYSTEM_DD_STATS is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32l0538-disco" +CONFIG_ARCH_BOARD_STM32L0538_DISCO=y +CONFIG_ARCH_CHIP="stm32l0" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32L053C8=y +CONFIG_ARCH_CHIP_STM32L053XX=y +CONFIG_ARCH_CHIP_STM32L0=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=2796 +CONFIG_BUILTIN=y +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_DEFAULT_TASK_STACKSIZE=1024 +CONFIG_DISABLE_ENVIRON=y +CONFIG_DISABLE_MOUNTPOINT=y +CONFIG_DISABLE_MQUEUE=y +CONFIG_DISABLE_POSIX_TIMERS=y +CONFIG_DISABLE_PSEUDOFS_OPERATIONS=y +CONFIG_EXAMPLES_HELLO=y +CONFIG_EXPERIMENTAL=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NUNGET_CHARS=0 +CONFIG_PTHREAD_MUTEX_UNSAFE=y +CONFIG_RAM_SIZE=8192 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=19 +CONFIG_START_MONTH=5 +CONFIG_START_YEAR=2013 +CONFIG_STDIO_DISABLE_BUFFERING=y +CONFIG_STM32_PWR=y +CONFIG_STM32_USART1=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32l0/stm32l0538-disco/include/board.h b/boards/arm/stm32l0/stm32l0538-disco/include/board.h new file mode 100644 index 0000000000000..f1ba04878c682 --- /dev/null +++ b/boards/arm/stm32l0/stm32l0538-disco/include/board.h @@ -0,0 +1,195 @@ +/**************************************************************************** + * boards/arm/stm32l0/stm32l0538-disco/include/board.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_STM32F0L0G0_STM32L0538_DISCO_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32F0L0G0_STM32L0538_DISCO_INCLUDE_BOARD_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Clocking *****************************************************************/ + +/* HSI - Internal 16 MHz RC Oscillator + * LSI - 32 KHz RC + * HSE - 8 MHz from MCO output of ST-LINK + * LSE - 32.768 kHz + */ + +#define STM32_BOARD_XTAL 8000000ul + +#define STM32_HSEBYP_ENABLE +#define STM32_HSI_FREQUENCY 16000000ul +#define STM32_LSI_FREQUENCY 32000 /* Between 30kHz and 60kHz */ +#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL +#define STM32_LSE_FREQUENCY 32768 /* X2 on board */ + +/* PLL source is HSE/1, PLL multiplier is 8: + * PLL frequency is 8MHz (XTAL) x 8 = 64MHz + */ + +#define STM32_CFGR_PLLSRC RCC_CFGR_PLLSRC +#define STM32_CFGR_PLLXTPRE 0 +#define STM32_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx8 +#define STM32_PLL_FREQUENCY (8*STM32_BOARD_XTAL) + +/* Use the PLL and set the SYSCLK source to be the PLL/2 (32MHz) */ + +#define STM32_SYSCLK_SW RCC_CFGR_SW_PLL +#define STM32_SYSCLK_SWS RCC_CFGR_SWS_PLL +#define STM32_CFGR_PLLDIV RCC_CFGR_PLLDIV_2 +#define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY/2 + +/* AHB clock (HCLK) is SYSCLK (32MHz) */ + +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY + +/* APB2 clock (PCLK2) is HCLK (32MHz) */ + +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK +#define STM32_PCLK2_FREQUENCY STM32_HCLK_FREQUENCY +#define STM32_APB2_CLKIN (STM32_PCLK2_FREQUENCY) + +/* APB1 clock (PCLK1) is HCLK/2 (16MHz) */ + +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd2 +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/2) + +/* 48MHz clock configuration */ + +#if defined(CONFIG_STM32_USB) || defined(CONFIG_STM32_RNG) +# define STM32_USE_CLK48 1 +# define STM32_CLK48_SEL RCC_CCIPR_CLK48SEL_HSI48 +# define STM32_HSI48_SYNCSRC SYNCSRC_NONE +#endif + +/* TODO: timers */ + +/* LED definitions **********************************************************/ + +/* The STM32L0538-DISCO board has three LEDs. Two of these are controlled by + * logic on the board and are not available for software control: + * + * LD1 COM: LD1 default status is red. LD1 turns to green to indicate that + * communications are in progress between the PC and the + * ST-LINK/V2-1. + * LD3 PWR: red LED indicates that the board is powered. + * + * And one can be controlled by software: + * + * User LD2: green LED is a user LED connected to the I/O PA5 of the + * STM32L053C8T6. + * + * If CONFIG_ARCH_LEDS is not defined, then the user can control the LED in + * any way. The following definition is used to access the LED. + */ + +/* LED index values for use with board_userled() */ + +#define BOARD_LED1 0 /* User LD2 */ +#define BOARD_NLEDS 1 + +/* LED bits for use with board_userled_all() */ + +#define BOARD_LED1_BIT (1 << BOARD_LED1) + +/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the LED on board + * the STM32L0538-DISCO. The following definitions describe how NuttX + * controls the LED: + * + * SYMBOL Meaning LED1 state + * ------------------ ----------------------- ---------- + * LED_STARTED NuttX has been started OFF + * LED_HEAPALLOCATE Heap has been allocated OFF + * LED_IRQSENABLED Interrupts enabled OFF + * LED_STACKCREATED Idle stack created ON + * LED_INIRQ In an interrupt No change + * LED_SIGNAL In a signal handler No change + * LED_ASSERTION An assertion failed No change + * LED_PANIC The system has crashed Blinking + * LED_IDLE STM32 is in sleep mode Not used + */ + +#define LED_STARTED 0 +#define LED_HEAPALLOCATE 0 +#define LED_IRQSENABLED 0 +#define LED_STACKCREATED 1 +#define LED_INIRQ 2 +#define LED_SIGNAL 2 +#define LED_ASSERTION 2 +#define LED_PANIC 1 + +/* Button definitions *******************************************************/ + +/* The STM32L0538-DISCO supports two buttons; only one button is controllable + * by software: + * + * B1 USER: user button connected to the I/O PA0 of the STM32L053C8T6. + * B2 RESET: push button connected to NRST is used to RESET the + * STM32L053C8T6. + */ + +#define BUTTON_USER 0 +#define NUM_BUTTONS 1 + +#define BUTTON_USER_BIT (1 << BUTTON_USER) + +/* Alternate function pin selections ****************************************/ + +/* USART */ + +/* By default the USART1 is connected to STLINK Virtual COM Port: + * USART1_RX - PA10 + * USART1_TX - PA9 + */ + +#define GPIO_USART1_RX (GPIO_USART1_RX_1|GPIO_SPEED_HIGH) /* PA10 */ +#define GPIO_USART1_TX (GPIO_USART1_TX_1|GPIO_SPEED_HIGH) /* PA9 */ + +/* SPI1 - E-papper display: + * SPI1_MISO - not used + * SPI1_MOSI - PB5 + * SPI1_SCK - PB3 + */ + +#undef GPIO_SPI1_MISO /* Not used */ +#define GPIO_SPI1_MOSI (GPIO_SPI1_MOSI_3|GPIO_SPEED_MEDIUM) /* PB5 */ +#define GPIO_SPI1_SCK (GPIO_SPI1_SCK_2|GPIO_SPEED_MEDIUM) /* PB3 */ + +/* SPI2 - NFC connector: + * SPI2_MISO - PB14 + * SPI2_MOSI - PB15 + * SPI2_SCK - PB13 + */ + +#define GPIO_SPI2_MISO (GPIO_SPI2_MISO_1|GPIO_SPEED_MEDIUM) /* PB14 */ +#define GPIO_SPI2_MOSI (GPIO_SPI2_MOSI_1|GPIO_SPEED_MEDIUM) /* PB15 */ +#define GPIO_SPI2_SCK (GPIO_SPI2_SCK_3|GPIO_SPEED_MEDIUM) /* PB13 */ + +#endif /* __BOARDS_ARM_STM32F0L0G0_STM32L0538_DISCO_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32l0/stm32l0538-disco/scripts/Make.defs b/boards/arm/stm32l0/stm32l0538-disco/scripts/Make.defs new file mode 100644 index 0000000000000..5a209945f33c2 --- /dev/null +++ b/boards/arm/stm32l0/stm32l0538-disco/scripts/Make.defs @@ -0,0 +1,43 @@ +############################################################################ +# boards/arm/stm32l0/stm32l0538-disco/scripts/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/.config +include $(TOPDIR)/tools/Config.mk +include $(TOPDIR)/arch/arm/src/armv6-m/Toolchain.defs + +LDSCRIPT = ld.script +ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) + +ARCHWARNINGS = -Wall -Wstrict-prototypes -Wshadow -Wundef +ARCHWARNINGSXX = -Wall -Wshadow -Wundef +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS := $(ARCHCFLAGS) $(ARCHWARNINGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHWARNINGSXX) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32l0/stm32l0538-disco/scripts/ld.script b/boards/arm/stm32l0/stm32l0538-disco/scripts/ld.script new file mode 100644 index 0000000000000..9eb309a0097b7 --- /dev/null +++ b/boards/arm/stm32l0/stm32l0538-disco/scripts/ld.script @@ -0,0 +1,115 @@ +/**************************************************************************** + * boards/arm/stm32l0/stm32l0538-disco/scripts/ld.script + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* The STM32L0538-DISCO has 64Kb of FLASH beginning at address 0x0800:0000. + * 8Kb of SRAM and 6Kb of EEPROM + * + * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 + * where the code expects to begin execution by jumping to the entry point in + * the 0x0800:0000 address range. + */ + +MEMORY +{ + flash (rx) : ORIGIN = 0x08000000, LENGTH = 64K + sram (rwx) : ORIGIN = 0x20000000, LENGTH = 8K +} + +OUTPUT_ARCH(arm) +EXTERN(_vectors) +ENTRY(_stext) +SECTIONS +{ + .text : { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > flash + + .init_section : ALIGN(4) { + _sinit = ABSOLUTE(.); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) + _einit = ABSOLUTE(.); + } > flash + + .ARM.extab : ALIGN(4) { + *(.ARM.extab*) + } > flash + + .ARM.exidx : ALIGN(4) { + __exidx_start = ABSOLUTE(.); + *(.ARM.exidx*) + __exidx_end = ABSOLUTE(.); + } > flash + + _eronly = ABSOLUTE(.); + + /* The RAM vector table (if present) should lie at the beginning of SRAM */ + + .ram_vectors : { + *(.ram_vectors) + } > sram + + .data : ALIGN(4) { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > sram AT > flash + + .bss : ALIGN(4) { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + _ebss = ABSOLUTE(.); + } > sram + + /* Stabs debugging sections. */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/stm32l0/stm32l0538-disco/src/CMakeLists.txt b/boards/arm/stm32l0/stm32l0538-disco/src/CMakeLists.txt new file mode 100644 index 0000000000000..7819e8f72267f --- /dev/null +++ b/boards/arm/stm32l0/stm32l0538-disco/src/CMakeLists.txt @@ -0,0 +1,37 @@ +# ############################################################################## +# boards/arm/stm32l0/stm32l0538-disco/src/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(SRCS stm32_boot.c stm32_bringup.c) + +if(CONFIG_ARCH_LEDS) + list(APPEND SRCS stm32_autoleds.c) +else() + list(APPEND SRCS stm32_userleds.c) +endif() + +if(CONFIG_ARCH_BUTTONS) + list(APPEND SRCS stm32_buttons.c) +endif() + +target_sources(board PRIVATE ${SRCS}) + +set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/ld.script") diff --git a/boards/arm/stm32l0/stm32l0538-disco/src/Make.defs b/boards/arm/stm32l0/stm32l0538-disco/src/Make.defs new file mode 100644 index 0000000000000..6d6fb20db57c7 --- /dev/null +++ b/boards/arm/stm32l0/stm32l0538-disco/src/Make.defs @@ -0,0 +1,39 @@ +############################################################################ +# boards/arm/stm32l0/stm32l0538-disco/src/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +CSRCS = stm32_boot.c stm32_bringup.c + +ifeq ($(CONFIG_ARCH_LEDS),y) +CSRCS += stm32_autoleds.c +else +CSRCS += stm32_userleds.c +endif + +ifeq ($(CONFIG_ARCH_BUTTONS),y) +CSRCS += stm32_buttons.c +endif + +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32l0/stm32l0538-disco/src/stm32_autoleds.c b/boards/arm/stm32l0/stm32l0538-disco/src/stm32_autoleds.c new file mode 100644 index 0000000000000..9e28a2427ef07 --- /dev/null +++ b/boards/arm/stm32l0/stm32l0538-disco/src/stm32_autoleds.c @@ -0,0 +1,80 @@ +/**************************************************************************** + * boards/arm/stm32l0/stm32l0538-disco/src/stm32_autoleds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include + +#include "stm32_gpio.h" +#include "stm32l0538-disco.h" + +#include + +#ifdef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_autoled_initialize + ****************************************************************************/ + +void board_autoled_initialize(void) +{ + /* Configure LED1 GPIO for output */ + + stm32_configgpio(GPIO_LED1); +} + +/**************************************************************************** + * Name: board_autoled_on + ****************************************************************************/ + +void board_autoled_on(int led) +{ + if (led == BOARD_LED1) + { + stm32_gpiowrite(GPIO_LED1, true); + } +} + +/**************************************************************************** + * Name: board_autoled_off + ****************************************************************************/ + +void board_autoled_off(int led) +{ + if (led == BOARD_LED1) + { + stm32_gpiowrite(GPIO_LED1, false); + } +} + +#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32l0/stm32l0538-disco/src/stm32_boot.c b/boards/arm/stm32l0/stm32l0538-disco/src/stm32_boot.c new file mode 100644 index 0000000000000..b3a0d820c4826 --- /dev/null +++ b/boards/arm/stm32l0/stm32l0538-disco/src/stm32_boot.c @@ -0,0 +1,79 @@ +/**************************************************************************** + * boards/arm/stm32l0/stm32l0538-disco/src/stm32_boot.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include "stm32l0538-disco.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_boardinitialize + * + * Description: + * All STM32 architectures must provide the following entry point. This + * entry point is called early in the initialization -- after all memory + * has been configured and mapped but before any devices have been + * initialized. + * + ****************************************************************************/ + +void stm32_boardinitialize(void) +{ +#ifdef CONFIG_ARCH_LEDS + /* Configure on-board LEDs if LED support has been selected. */ + + board_autoled_initialize(); +#endif +} + +/**************************************************************************** + * Name: board_late_initialize + * + * Description: + * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_late_initialize(). board_late_initialize() will + * be called immediately after up_initialize() is called and just before + * the initial application is started. This additional initialization + * phase may be used, for example, to initialize board-specific device + * drivers. + * + ****************************************************************************/ + +#ifdef CONFIG_BOARD_LATE_INITIALIZE +void board_late_initialize(void) +{ + /* Perform board-specific initialization */ + + stm32_bringup(); +} +#endif diff --git a/boards/arm/stm32l0/stm32l0538-disco/src/stm32_bringup.c b/boards/arm/stm32l0/stm32l0538-disco/src/stm32_bringup.c new file mode 100644 index 0000000000000..1bc7e9a74e645 --- /dev/null +++ b/boards/arm/stm32l0/stm32l0538-disco/src/stm32_bringup.c @@ -0,0 +1,84 @@ +/**************************************************************************** + * boards/arm/stm32l0/stm32l0538-disco/src/stm32_bringup.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include "stm32l0538-disco.h" + +#ifdef CONFIG_INPUT_BUTTONS +# include +#endif + +#ifdef CONFIG_USERLED +# include +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_bringup + * + * Description: + * Perform architecture-specific initialization + * + * CONFIG_BOARD_LATE_INITIALIZE=y : + * Called from board_late_initialize(). + * + ****************************************************************************/ + +int stm32_bringup(void) +{ + int ret; + +#ifdef CONFIG_INPUT_BUTTONS + /* Register the BUTTON driver */ + + ret = btn_lower_initialize("/dev/buttons"); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: btn_lower_initialize() failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_USERLED + /* Register the LED driver */ + + ret = userled_lower_initialize(LED_DRIVER_PATH); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: userled_lower_initialize() failed: %d\n", ret); + return ret; + } +#endif + + UNUSED(ret); + return OK; +} diff --git a/boards/arm/stm32l0/stm32l0538-disco/src/stm32_buttons.c b/boards/arm/stm32l0/stm32l0538-disco/src/stm32_buttons.c new file mode 100644 index 0000000000000..73295823d915a --- /dev/null +++ b/boards/arm/stm32l0/stm32l0538-disco/src/stm32_buttons.c @@ -0,0 +1,118 @@ +/**************************************************************************** + * boards/arm/stm32l0/stm32l0538-disco/src/stm32_buttons.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "stm32_gpio.h" +#include "stm32l0538-disco.h" + +#include + +#ifdef CONFIG_ARCH_BUTTONS + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_button_initialize + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. + * + ****************************************************************************/ + +uint32_t board_button_initialize(void) +{ + /* Configure the single button as an input. NOTE that EXTI interrupts are + * also configured for the pin. + */ + + stm32_configgpio(GPIO_BTN_USER); + return NUM_BUTTONS; +} + +/**************************************************************************** + * Name: board_buttons + ****************************************************************************/ + +uint32_t board_buttons(void) +{ + /* Check that state of each USER button. A LOW value means that the key is + * pressed. + */ + + bool released = stm32_gpioread(GPIO_BTN_USER); + return !released; +} + +/**************************************************************************** + * Button support. + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. + * + * After board_button_initialize() has been called, board_buttons() may be + * called to collect the state of all buttons. board_buttons() returns an + * 32-bit bit set with each bit associated with a button. See the + * BUTTON_*_BIT definitions in board.h for the meaning of each bit. + * + * board_button_irq() may be called to register an interrupt handler that + * will be called when a button is depressed or released. The ID value is a + * button enumeration value that uniquely identifies a button resource. See + * the BUTTON_* definitions in board.h for the meaning of enumeration + * value. + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_IRQBUTTONS +int board_button_irq(int id, xcpt_t irqhandler, void *arg) +{ + int ret = -EINVAL; + + if (id == BUTTON_USER) + { + ret = stm32_gpiosetevent(GPIO_BTN_USER, true, true, true, + irqhandler, arg); + } + + return ret; +} +#endif +#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/stm32f0l0g0/stm32l0538-disco/src/stm32l0538-disco.h b/boards/arm/stm32l0/stm32l0538-disco/src/stm32l0538-disco.h similarity index 98% rename from boards/arm/stm32f0l0g0/stm32l0538-disco/src/stm32l0538-disco.h rename to boards/arm/stm32l0/stm32l0538-disco/src/stm32l0538-disco.h index 34b45f2a99444..38e14d22f82a8 100644 --- a/boards/arm/stm32f0l0g0/stm32l0538-disco/src/stm32l0538-disco.h +++ b/boards/arm/stm32l0/stm32l0538-disco/src/stm32l0538-disco.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/stm32l0538-disco/src/stm32l0538-disco.h + * boards/arm/stm32l0/stm32l0538-disco/src/stm32l0538-disco.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32l1/common/CMakeLists.txt b/boards/arm/stm32l1/common/CMakeLists.txt new file mode 100644 index 0000000000000..92e3c5d09db04 --- /dev/null +++ b/boards/arm/stm32l1/common/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32l1/common/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(${NUTTX_DIR}/boards/arm/common/stm32 stm32_common) diff --git a/boards/arm/stm32l1/common/Kconfig b/boards/arm/stm32l1/common/Kconfig new file mode 100644 index 0000000000000..5c48f62a0258b --- /dev/null +++ b/boards/arm/stm32l1/common/Kconfig @@ -0,0 +1,6 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# + +source "boards/arm/common/stm32/Kconfig" diff --git a/boards/arm/stm32l1/common/Makefile b/boards/arm/stm32l1/common/Makefile new file mode 100644 index 0000000000000..8217b07f906ae --- /dev/null +++ b/boards/arm/stm32l1/common/Makefile @@ -0,0 +1,39 @@ +############################################################################# +# boards/arm/stm32l1/common/Makefile +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################# + +include $(TOPDIR)/Make.defs + +STM32_BOARD_COMMON_DIR := $(TOPDIR)$(DELIM)boards$(DELIM)arm$(DELIM)common$(DELIM)stm32 +STM32_COMMON_SRCDIR := $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)common$(DELIM)stm32 + +include board/Make.defs +include $(STM32_BOARD_COMMON_DIR)$(DELIM)src$(DELIM)Make.defs + +DEPPATH += --dep-path board + +include $(TOPDIR)/boards/Board.mk + +ARCHSRCDIR = $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src +BOARDDIR = $(ARCHSRCDIR)$(DELIM)board +CFLAGS += ${INCDIR_PREFIX}$(BOARDDIR)$(DELIM)include +CFLAGS += ${INCDIR_PREFIX}$(STM32_COMMON_SRCDIR) +CXXFLAGS += ${INCDIR_PREFIX}$(STM32_COMMON_SRCDIR) diff --git a/boards/arm/stm32l1/nucleo-l152re/CMakeLists.txt b/boards/arm/stm32l1/nucleo-l152re/CMakeLists.txt new file mode 100644 index 0000000000000..199de2f567a0c --- /dev/null +++ b/boards/arm/stm32l1/nucleo-l152re/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32l1/nucleo-l152re/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/arm/stm32/nucleo-l152re/Kconfig b/boards/arm/stm32l1/nucleo-l152re/Kconfig similarity index 100% rename from boards/arm/stm32/nucleo-l152re/Kconfig rename to boards/arm/stm32l1/nucleo-l152re/Kconfig diff --git a/boards/arm/stm32l1/nucleo-l152re/configs/lcd/defconfig b/boards/arm/stm32l1/nucleo-l152re/configs/lcd/defconfig new file mode 100644 index 0000000000000..73ee4c8eb4ec2 --- /dev/null +++ b/boards/arm/stm32l1/nucleo-l152re/configs/lcd/defconfig @@ -0,0 +1,72 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NX_DISABLE_16BPP is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nucleo-l152re" +CONFIG_ARCH_BOARD_NUCLEO_L152RE=y +CONFIG_ARCH_CHIP="stm32l1" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32L152RE=y +CONFIG_ARCH_CHIP_STM32L1=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=2796 +CONFIG_BUILTIN=y +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_DISABLE_ENVIRON=y +CONFIG_EXAMPLES_HELLO=y +CONFIG_EXAMPLES_NX=y +CONFIG_EXAMPLES_NXDEMO=y +CONFIG_EXAMPLES_NXDEMO_BPP=16 +CONFIG_EXAMPLES_NX_BPP=16 +CONFIG_FS_PROCFS=y +CONFIG_FS_PROCFS_REGISTER=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=1536 +CONFIG_INTELHEX_BINARY=y +CONFIG_LCD=y +CONFIG_LCD_EXTERNINIT=y +CONFIG_LCD_FRAMEBUFFER=y +CONFIG_LCD_ILI9341=y +CONFIG_LCD_ILI9341_IFACE0=y +CONFIG_LCD_ILI9341_IFACE0_PORTRAIT=y +CONFIG_LCD_PORTRAIT=y +CONFIG_LINE_MAX=64 +CONFIG_MQ_MAXMSGSIZE=64 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_NUNGET_CHARS=0 +CONFIG_NX=y +CONFIG_NXFONT_MONO5X8=y +CONFIG_NXFONT_SANS22X29B=y +CONFIG_NXFONT_SANS23X27=y +CONFIG_NX_BLOCKING=y +CONFIG_POSIX_SPAWN_DEFAULT_STACKSIZE=1536 +CONFIG_PREALLOC_TIMERS=4 +CONFIG_PTHREAD_MUTEX_UNSAFE=y +CONFIG_PTHREAD_STACK_DEFAULT=1536 +CONFIG_RAM_SIZE=81920 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=19 +CONFIG_START_MONTH=5 +CONFIG_START_YEAR=2013 +CONFIG_STDIO_DISABLE_BUFFERING=y +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_PWR=y +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32l1/nucleo-l152re/configs/nsh/defconfig b/boards/arm/stm32l1/nucleo-l152re/configs/nsh/defconfig new file mode 100644 index 0000000000000..3b73a53c8df5c --- /dev/null +++ b/boards/arm/stm32l1/nucleo-l152re/configs/nsh/defconfig @@ -0,0 +1,54 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_ARGCAT is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nucleo-l152re" +CONFIG_ARCH_BOARD_NUCLEO_L152RE=y +CONFIG_ARCH_CHIP="stm32l1" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32L152RE=y +CONFIG_ARCH_CHIP_STM32L1=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=2796 +CONFIG_BUILTIN=y +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_DISABLE_ENVIRON=y +CONFIG_DISABLE_MOUNTPOINT=y +CONFIG_DISABLE_MQUEUE=y +CONFIG_DISABLE_POSIX_TIMERS=y +CONFIG_DISABLE_PSEUDOFS_OPERATIONS=y +CONFIG_EXAMPLES_HELLO=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=1536 +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=64 +CONFIG_NSH_READLINE=y +CONFIG_NUNGET_CHARS=0 +CONFIG_POSIX_SPAWN_DEFAULT_STACKSIZE=1536 +CONFIG_PTHREAD_MUTEX_UNSAFE=y +CONFIG_PTHREAD_STACK_DEFAULT=1536 +CONFIG_RAM_SIZE=81920 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=19 +CONFIG_START_MONTH=5 +CONFIG_START_YEAR=2013 +CONFIG_STDIO_DISABLE_BUFFERING=y +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_PWR=y +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32l1/nucleo-l152re/include/board.h b/boards/arm/stm32l1/nucleo-l152re/include/board.h new file mode 100644 index 0000000000000..a8e89cabee046 --- /dev/null +++ b/boards/arm/stm32l1/nucleo-l152re/include/board.h @@ -0,0 +1,227 @@ +/**************************************************************************** + * boards/arm/stm32l1/nucleo-l152re/include/board.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_STM32_NUCLEOL152RE_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32_NUCLEOL152RE_INCLUDE_BOARD_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#ifndef __ASSEMBLY__ +# include +# include +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Clocking *****************************************************************/ + +/* Four different clock sources can be used to drive the system clock + * (SYSCLK): + * + * - HSI high-speed internal oscillator clock + * Generated from an internal 16 MHz RC oscillator + * - HSE high-speed external oscillator clock. 8 MHz from MCO output of + * ST-LINK. + * - PLL clock + * - MSI multispeed internal oscillator clock + * The MSI clock signal is generated from an internal RC oscillator. + * Seven frequency ranges are available: 65.536 kHz, 131.072 kHz, + * 262.144 kHz, 524.288 kHz, 1.048 MHz, 2.097 MHz (default value) + * and 4.194 MHz. + * + * The devices have the following two secondary clock sources + * - LSI low-speed internal RC clock + * Drives the watchdog and RTC. Approximately 37KHz + * - LSE low-speed external oscillator clock + * Driven by 32.768KHz crystal (X2) on the OSC32_IN and OSC32_OUT pins. + */ + +#define STM32_BOARD_XTAL 8000000ul + +#define STM32_HSI_FREQUENCY 16000000ul +#define STM32_LSI_FREQUENCY 37000 /* Approximately 37KHz */ +#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL +#define STM32_LSE_FREQUENCY 32768 /* X2 on board */ + +/* PLL Configuration + * + * - PLL source is HSE -> 8MHz + * - PLL multiplier is 12 -> 96MHz PLL VCO clock output + * - PLL output divider 3 -> 32MHz divided down PLL VCO clock output + * + * Resulting SYSCLK frequency is 8MHz x 12 / 3 = 32MHz + * + * USB/SDIO: + * If the USB or SDIO interface is used in the application, the PLL VCO + * clock (defined by STM32_CFGR_PLLMUL) must be programmed to output a 96 + * MHz frequency. This is required to provide a 48 MHz clock to the USB or + * SDIO (SDIOCLK or USBCLK = PLLVCO/2). + * SYSCLK + * The system clock is derived from the PLL VCO divided by the output + * division factor. + * Limitations: + * 96 MHz as PLLVCO when the product is in range 1 (1.8V), + * 48 MHz as PLLVCO when the product is in range 2 (1.5V), + * 24 MHz when the product is in range 3 (1.2V). + * Output division to avoid exceeding 32 MHz as SYSCLK. + * The minimum input clock frequency for PLL is 2 MHz (when using HSE as + * PLL source). + */ + +#if 1 +#define STM32_CFGR_PLLSRC RCC_CFGR_PLLSRC /* PLL clocked by the HSE */ +#define STM32_HSEBYP_ENABLE 1 +#define STM32_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx12 /* PLLMUL = 12 */ +#define STM32_CFGR_PLLDIV RCC_CFGR_PLLDIV_3 /* PLLDIV = 3 */ +#define STM32_PLL_FREQUENCY (12*STM32_BOARD_XTAL) /* PLL VCO Frequency is 96MHz */ +#else +#define STM32_CFGR_PLLSRC 0 /* PLL clocked by the HSI RC */ +#define STM32_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx6 /* PLLMUL = 6 */ +#define STM32_CFGR_PLLDIV RCC_CFGR_PLLDIV_3 /* PLLDIV = 3 */ +#define STM32_PLL_FREQUENCY (6*STM32_HSI_FREQUENCY) /* PLL VCO Frequency is 96MHz */ +#endif + +/* Use the PLL and set the SYSCLK source to be the divided down PLL VCO + * output frequency (STM32_PLL_FREQUENCY divided by the PLLDIV value). + */ + +#define STM32_SYSCLK_SW RCC_CFGR_SW_PLL +#define STM32_SYSCLK_SWS RCC_CFGR_SWS_PLL +#define STM32_SYSCLK_FREQUENCY (STM32_PLL_FREQUENCY/3) + +/* AHB clock (HCLK) is SYSCLK (32MHz) */ + +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY + +/* APB2 clock (PCLK2) is HCLK (32MHz) */ + +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK +#define STM32_PCLK2_FREQUENCY STM32_HCLK_FREQUENCY +#define STM32_APB2_CLKIN STM32_PCLK2_FREQUENCY + +/* APB1 clock (PCLK1) is HCLK (32MHz) */ + +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK +#define STM32_PCLK1_FREQUENCY STM32_HCLK_FREQUENCY + +/* TODO: Timers */ + +/* LED definitions **********************************************************/ + +/* The Nucleo L152RE board has three LEDs. Two of these are controlled by + * logic on the board and are not available for software control: + * + * LD1 COM: LD1 default status is red. LD1 turns to green to indicate that + * communications are in progress between the PC and the + * ST-LINK/V2-1. + * LD3 PWR: red LED indicates that the board is powered. + * + * And one can be controlled by software: + * + * User LD2: green LED is a user LED connected to the I/O PA5 of the + * STM32L152RET6. + * + * If CONFIG_ARCH_LEDS is not defined, then the user can control the LED in + * any way. The following definition is used to access the LED. + */ + +/* LED index values for use with board_userled() */ + +#define BOARD_LED1 0 /* User LD2 */ +#define BOARD_NLEDS 1 + +/* LED bits for use with board_userled_all() */ + +#define BOARD_LED1_BIT (1 << BOARD_LED1) + +/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the LED on board + * the Nucleo L152RE. The following definitions describe how NuttX controls + * the LED: + * + * SYMBOL Meaning LED1 state + * ------------------ ----------------------- ---------- + * LED_STARTED NuttX has been started OFF + * LED_HEAPALLOCATE Heap has been allocated OFF + * LED_IRQSENABLED Interrupts enabled OFF + * LED_STACKCREATED Idle stack created ON + * LED_INIRQ In an interrupt No change + * LED_SIGNAL In a signal handler No change + * LED_ASSERTION An assertion failed No change + * LED_PANIC The system has crashed Blinking + * LED_IDLE STM32 is in sleep mode Not used + */ + +#define LED_STARTED 0 +#define LED_HEAPALLOCATE 0 +#define LED_IRQSENABLED 0 +#define LED_STACKCREATED 1 +#define LED_INIRQ 2 +#define LED_SIGNAL 2 +#define LED_ASSERTION 2 +#define LED_PANIC 1 + +/* Button definitions *******************************************************/ + +/* The Nucleo L152RE supports two buttons; only one button is controllable + * by software: + * + * B1 USER: user button connected to the I/O PC13 of the STM32L152RET6. + * B2 RESET: push button connected to NRST is used to RESET the + * STM32L152RET6. + */ + +#define BUTTON_USER 0 +#define NUM_BUTTONS 1 + +#define BUTTON_USER_BIT (1 << BUTTON_USER) + +/* Alternate function pin selections ****************************************/ + +/* USART */ + +/* By default the USART2 is connected to STLINK Virtual COM Port: + * USART2_RX - PA3 + * USART2_TX - PA2 + */ + +#define GPIO_USART2_RX (GPIO_USART2_RX_1|GPIO_SPEED_40MHz) /* PA3 */ +#define GPIO_USART2_TX (GPIO_USART2_TX_1|GPIO_SPEED_40MHz) /* PA2 */ + +/* SPI1 */ + +#define GPIO_SPI1_MOSI GPIO_SPI1_MOSI_2 +#define GPIO_SPI1_MISO GPIO_SPI1_MISO_2 +#define GPIO_SPI1_SCK GPIO_SPI1_SCK_1 + +/* I2C1 */ + +#define GPIO_I2C1_SCL (GPIO_I2C1_SCL_2|GPIO_SPEED_40MHz) /* PB8 CN5 pin 10, D15 */ +#define GPIO_I2C1_SDA (GPIO_I2C1_SDA_2|GPIO_SPEED_40MHz) /* PB9 CN5 pin 9, D14 */ + +#endif /* __BOARDS_ARM_STM32_NUCLEO_L152RE_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32l1/nucleo-l152re/scripts/Make.defs b/boards/arm/stm32l1/nucleo-l152re/scripts/Make.defs new file mode 100644 index 0000000000000..656e9afe07095 --- /dev/null +++ b/boards/arm/stm32l1/nucleo-l152re/scripts/Make.defs @@ -0,0 +1,41 @@ +############################################################################ +# boards/arm/stm32l1/nucleo-l152re/scripts/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/.config +include $(TOPDIR)/tools/Config.mk +include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs + +LDSCRIPT = ld.script +ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) + +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32l1/nucleo-l152re/scripts/ld.script b/boards/arm/stm32l1/nucleo-l152re/scripts/ld.script new file mode 100644 index 0000000000000..747f91401b8a1 --- /dev/null +++ b/boards/arm/stm32l1/nucleo-l152re/scripts/ld.script @@ -0,0 +1,127 @@ +/**************************************************************************** + * boards/arm/stm32l1/nucleo-l152re/scripts/ld.script + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* The STM32L152RET6 has 512Kb of FLASH beginning at address 0x0800:0000, + * 80Kb of SRAM, and 16Kb of EEPROM. + * + * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 + * where the code expects to begin execution by jumping to the entry point in + * the 0x0800:0000 address range. + */ + +MEMORY +{ + flash (rx) : ORIGIN = 0x08000000, LENGTH = 512K + sram (rwx) : ORIGIN = 0x20000000, LENGTH = 80K +} + +OUTPUT_ARCH(arm) +EXTERN(_vectors) +ENTRY(_stext) +SECTIONS +{ + .text : { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > flash + + .init_section : ALIGN(4) { + _sinit = ABSOLUTE(.); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) + _einit = ABSOLUTE(.); + } > flash + + .ARM.extab : ALIGN(4) { + *(.ARM.extab*) + } > flash + + .ARM.exidx : ALIGN(4) { + __exidx_start = ABSOLUTE(.); + *(.ARM.exidx*) + __exidx_end = ABSOLUTE(.); + } > flash + + .tdata : { + _stdata = ABSOLUTE(.); + *(.tdata .tdata.* .gnu.linkonce.td.*); + _etdata = ABSOLUTE(.); + } > flash + + .tbss : { + _stbss = ABSOLUTE(.); + *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); + _etbss = ABSOLUTE(.); + } > flash + + _eronly = ABSOLUTE(.); + + /* The RAM vector table (if present) should lie at the beginning of SRAM */ + + .ram_vectors : { + *(.ram_vectors) + } > sram + + .data : ALIGN(4) { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > sram AT > flash + + .bss : ALIGN(4) { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + _ebss = ABSOLUTE(.); + } > sram + + /* Stabs debugging sections. */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/stm32l1/nucleo-l152re/src/CMakeLists.txt b/boards/arm/stm32l1/nucleo-l152re/src/CMakeLists.txt new file mode 100644 index 0000000000000..9177895b7e42f --- /dev/null +++ b/boards/arm/stm32l1/nucleo-l152re/src/CMakeLists.txt @@ -0,0 +1,49 @@ +# ############################################################################## +# boards/arm/stm32l1/nucleo-l152re/src/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(SRCS stm32_boot.c) + +if(CONFIG_ARCH_LEDS) + list(APPEND SRCS stm32_autoleds.c) +else() + list(APPEND SRCS stm32_userleds.c) +endif() + +if(CONFIG_ARCH_BUTTONS) + list(APPEND SRCS stm32_buttons.c) +endif() + +if(CONFIG_LCD_ILI9341) + list(APPEND SRCS stm32_ili93418b.c) +endif() + +if(CONFIG_MMCSD_SPI) + list(APPEND SRCS stm32_spisd.c) +endif() + +if(CONFIG_STM32_SPI) + list(APPEND SRCS stm32_spi.c) +endif() + +target_sources(board PRIVATE ${SRCS}) + +set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/ld.script") diff --git a/boards/arm/stm32l1/nucleo-l152re/src/Make.defs b/boards/arm/stm32l1/nucleo-l152re/src/Make.defs new file mode 100644 index 0000000000000..b1d374b5b3ed6 --- /dev/null +++ b/boards/arm/stm32l1/nucleo-l152re/src/Make.defs @@ -0,0 +1,51 @@ +############################################################################ +# boards/arm/stm32l1/nucleo-l152re/src/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +CSRCS = stm32_boot.c + +ifeq ($(CONFIG_ARCH_LEDS),y) +CSRCS += stm32_autoleds.c +else +CSRCS += stm32_userleds.c +endif + +ifeq ($(CONFIG_ARCH_BUTTONS),y) +CSRCS += stm32_buttons.c +endif + +ifeq ($(CONFIG_LCD_ILI9341),y) +CSRCS += stm32_ili93418b.c +endif + +ifeq ($(CONFIG_MMCSD_SPI),y) +CSRCS += stm32_spisd.c +endif + +ifeq ($(CONFIG_STM32_SPI),y) +CSRCS += stm32_spi.c +endif + +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/nucleo-l152re/src/nucleo-l152re.h b/boards/arm/stm32l1/nucleo-l152re/src/nucleo-l152re.h similarity index 98% rename from boards/arm/stm32/nucleo-l152re/src/nucleo-l152re.h rename to boards/arm/stm32l1/nucleo-l152re/src/nucleo-l152re.h index dbdcb8cbf1ad8..7533f5860f92f 100644 --- a/boards/arm/stm32/nucleo-l152re/src/nucleo-l152re.h +++ b/boards/arm/stm32l1/nucleo-l152re/src/nucleo-l152re.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-l152re/src/nucleo-l152re.h + * boards/arm/stm32l1/nucleo-l152re/src/nucleo-l152re.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32l1/nucleo-l152re/src/stm32_autoleds.c b/boards/arm/stm32l1/nucleo-l152re/src/stm32_autoleds.c new file mode 100644 index 0000000000000..dcab65cab6df1 --- /dev/null +++ b/boards/arm/stm32l1/nucleo-l152re/src/stm32_autoleds.c @@ -0,0 +1,80 @@ +/**************************************************************************** + * boards/arm/stm32l1/nucleo-l152re/src/stm32_autoleds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "stm32.h" +#include "nucleo-l152re.h" + +#ifdef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_autoled_initialize + ****************************************************************************/ + +void board_autoled_initialize(void) +{ + /* Configure LED1 GPIO for output */ + + stm32_configgpio(GPIO_LED1); +} + +/**************************************************************************** + * Name: board_autoled_on + ****************************************************************************/ + +void board_autoled_on(int led) +{ + if (led == BOARD_LED1) + { + stm32_gpiowrite(GPIO_LED1, true); + } +} + +/**************************************************************************** + * Name: board_autoled_off + ****************************************************************************/ + +void board_autoled_off(int led) +{ + if (led == BOARD_LED1) + { + stm32_gpiowrite(GPIO_LED1, false); + } +} + +#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32l1/nucleo-l152re/src/stm32_boot.c b/boards/arm/stm32l1/nucleo-l152re/src/stm32_boot.c new file mode 100644 index 0000000000000..3545cdbafa058 --- /dev/null +++ b/boards/arm/stm32l1/nucleo-l152re/src/stm32_boot.c @@ -0,0 +1,197 @@ +/**************************************************************************** + * boards/arm/stm32l1/nucleo-l152re/src/stm32_boot.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include +#include +#include + +#include "stm32_i2c.h" + +#include "nucleo-l152re.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#undef HAVE_LEDS +#undef HAVE_DAC + +#if !defined(CONFIG_ARCH_LEDS) && defined(CONFIG_USERLED_LOWER) +# define HAVE_LEDS 1 +#endif + +#if defined(CONFIG_DAC) +# define HAVE_DAC 1 +#endif + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_boardinitialize + * + * Description: + * All STM32 architectures must provide the following entry point. This + * entry point is called early in the initialization -- after all memory + * has been configured and mapped but before any devices have been + * initialized. + * + ****************************************************************************/ + +void stm32_boardinitialize(void) +{ + /* Configure on-board LEDs if LED support has been selected. */ + +#ifdef CONFIG_ARCH_LEDS + board_autoled_initialize(); +#endif +} + +/**************************************************************************** + * Name: board_late_initialize + * + * Description: + * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_late_initialize(). board_late_initialize() will be + * called immediately after up_initialize() is called and just before the + * initial application is started. This additional initialization phase + * may be used, for example, to initialize board-specific device drivers. + * + ****************************************************************************/ + +#ifdef CONFIG_BOARD_LATE_INITIALIZE +void board_late_initialize(void) +{ + int ret; +#ifdef CONFIG_STM32_I2C1 + struct i2c_master_s *i2c1; +#endif +#ifdef CONFIG_STM32_I2C2 + struct i2c_master_s *i2c2; +#endif + +#ifdef CONFIG_STM32_I2C1 + /* Get the I2C lower half instance */ + + i2c1 = stm32_i2cbus_initialize(1); + if (i2c1 == NULL) + { + i2cerr("ERROR: Initialize I2C1: %d\n", ret); + } + else + { + /* Register the I2C character driver */ + + ret = i2c_register(i2c1, 1); + if (ret < 0) + { + i2cerr("ERROR: Failed to register I2C1 device: %d\n", ret); + } + } +#endif + +#ifdef CONFIG_STM32_I2C2 + /* Get the I2C lower half instance */ + + i2c2 = stm32_i2cbus_initialize(2); + if (i2c2 == NULL) + { + i2cerr("ERROR: Initialize I2C2: %d\n", ret); + } + else + { + /* Register the I2C character driver */ + + ret = i2c_register(i2c2, 2); + if (ret < 0) + { + i2cerr("ERROR: Failed to register I2C2 device: %d\n", ret); + } + } +#endif + +#ifdef CONFIG_STM32_SPI + stm32_spiinitialize(); +#endif + +#ifdef HAVE_LEDS + /* Register the LED driver */ + + ret = userled_lower_initialize(LED_DRIVER_PATH); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: userled_lower_initialize() failed: %d\n", ret); + return; + } +#endif + +#ifdef CONFIG_FS_PROCFS + /* Mount the procfs file system */ + + ret = nx_mount(0, STM32_PROCFS_MOUNTPOINT, "procfs", 0, 0); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to mount procfs at %s: %d\n", + STM32_PROCFS_MOUNTPOINT, ret); + } +#endif + +#ifdef CONFIG_MMCSD_SPI + + /* Initialize the MMC/SD SPI driver (SPI1 is used) */ + + ret = stm32_spisd_initialize(1, CONFIG_NSH_MMCSDMINOR); + if (ret < 0) + { + syslog(LOG_ERR, "Failed to initialize SD slot %d: %d\n", + CONFIG_NSH_MMCSDMINOR, ret); + } +#endif + + UNUSED(ret); +} +#endif diff --git a/boards/arm/stm32l1/nucleo-l152re/src/stm32_buttons.c b/boards/arm/stm32l1/nucleo-l152re/src/stm32_buttons.c new file mode 100644 index 0000000000000..645eac093f85a --- /dev/null +++ b/boards/arm/stm32l1/nucleo-l152re/src/stm32_buttons.c @@ -0,0 +1,113 @@ +/**************************************************************************** + * boards/arm/stm32l1/nucleo-l152re/src/stm32_buttons.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "stm32.h" +#include "nucleo-l152re.h" + +#ifdef CONFIG_ARCH_BUTTONS + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_button_initialize + * + * Description: + * board_button_initialize() must be called to initialize button + * resources. After that, board_buttons() may be called to collect the + * current state of all buttons or board_button_irq() may be called to + * register button interrupt handlers. + * + ****************************************************************************/ + +uint32_t board_button_initialize(void) +{ + /* Configure the single button as an input. NOTE that EXTI interrupts are + * also configured for the pin. + */ + + stm32_configgpio(GPIO_BTN_USER); + return NUM_BUTTONS; +} + +/**************************************************************************** + * Name: board_buttons + * + * Description: + * After board_button_initialize() has been called, board_buttons() may be + * called to collect the state of all buttons. board_buttons() returns an + * 32-bit unsigned integer with each bit associated with a button. See the + * BUTTON_*_BIT definitions in board.h for the meaning of each bit. + * + ****************************************************************************/ + +uint32_t board_buttons(void) +{ + /* Check the state of the USER button. A LOW value means that the key is + * pressed. + */ + + return stm32_gpioread(GPIO_BTN_USER) ? 0 : BUTTON_USER_BIT; +} + +/**************************************************************************** + * Name: board_button_irq + * + * Description: + * board_button_irq() may be called to register an interrupt handler that + * will be called when a button is depressed or released. The ID value is + * a button enumeration value that uniquely identifies a button resource. + * See the BUTTON_* definitions in board.h for the meaning of the + * enumeration value. + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_IRQBUTTONS +int board_button_irq(int id, xcpt_t irqhandler, void *arg) +{ + int ret = -EINVAL; + + if (id == BUTTON_USER) + { + ret = stm32_gpiosetevent(GPIO_BTN_USER, true, true, true, irqhandler, + arg); + } + + return ret; +} +#endif + +#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/stm32/nucleo-l152re/src/stm32_ili93418b.c b/boards/arm/stm32l1/nucleo-l152re/src/stm32_ili93418b.c similarity index 99% rename from boards/arm/stm32/nucleo-l152re/src/stm32_ili93418b.c rename to boards/arm/stm32l1/nucleo-l152re/src/stm32_ili93418b.c index 7b8052671c0c5..a07de22023d63 100644 --- a/boards/arm/stm32/nucleo-l152re/src/stm32_ili93418b.c +++ b/boards/arm/stm32l1/nucleo-l152re/src/stm32_ili93418b.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-l152re/src/stm32_ili93418b.c + * boards/arm/stm32l1/nucleo-l152re/src/stm32_ili93418b.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32l1/nucleo-l152re/src/stm32_spi.c b/boards/arm/stm32l1/nucleo-l152re/src/stm32_spi.c new file mode 100644 index 0000000000000..66b5dae214d76 --- /dev/null +++ b/boards/arm/stm32l1/nucleo-l152re/src/stm32_spi.c @@ -0,0 +1,268 @@ +/**************************************************************************** + * boards/arm/stm32l1/nucleo-l152re/src/stm32_spi.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include +#include + +#include "arm_internal.h" +#include "chip.h" +#include "stm32_gpio.h" +#include "stm32_spi.h" + +#include "nucleo-l152re.h" + +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || defined(CONFIG_STM32_SPI3) + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/* Global driver instances */ + +#ifdef CONFIG_STM32_SPI1 + struct spi_dev_s *g_spi1; +#endif +#ifdef CONFIG_STM32_SPI2 + struct spi_dev_s *g_spi2; +#endif +#ifdef CONFIG_STM32_SPI3 + struct spi_dev_s *g_spi3; +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_spiinitialize + * + * Description: + * Called to configure SPI chip select GPIO pins. + * + ****************************************************************************/ + +void weak_function stm32_spiinitialize(void) +{ + int ret; +#ifdef CONFIG_STM32_SPI1 + /* Initialize the SPI1 bus */ + + g_spi1 = stm32_spibus_initialize(1); + if (g_spi1 == NULL) + { + spierr("ERROR: Initialize SPI1: \n"); + } + +#ifdef CONFIG_SPI_DRIVER + /* Register the SPI1 character driver */ + + ret = spi_register(g_spi1, 1); + if (ret < 0) + { + spierr("ERROR: Failed to register SPI1 device: %d\n", ret); + } +#endif +#endif + +#ifdef CONFIG_STM32_SPI2 + /* Initialize the SPI2 bus */ + + g_spi2 = stm32_spibus_initialize(2); + if (g_spi2 == NULL) + { + spierr("ERROR: Initialize SPI2: \n"); + } + +#ifdef CONFIG_SPI_DRIVER + /* Register the SPI2 character driver */ + + ret = spi_register(g_spi2, 2); + if (ret < 0) + { + spierr("ERROR: Failed to register SPI2 device: %d\n", ret); + } +#endif +#endif + +#ifdef CONFIG_STM32_SPI3 + /* Initialize the SPI3 bus */ + + g_spi3 = stm32_spibus_initialize(3); + if (g_spi3 == NULL) + { + spierr("ERROR: Initialize SPI3: \n"); + } + +#ifdef CONFIG_SPI_DRIVER + /* Register the SPI3 character driver */ + + ret = spi_register(g_spi3, 3); + if (ret < 0) + { + spierr("ERROR: Failed to register SPI3 device: %d\n", ret); + } +#endif +#endif +} + +/**************************************************************************** + * Name: stm32_spi1/2/3select and stm32_spi1/2/3status + * + * Description: + * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status + * must be provided by board-specific logic. They are implementations of + * the select and status methods of the SPI interface defined by struct + * spi_ops_s (see include/nuttx/spi/spi.h). All other methods (including + * stm32_spibus_initialize()) are provided by common STM32 logic. To use + * this common SPI logic on your board: + * + * 1. Provide logic in stm32_boardinitialize() to configure SPI chip select + * pins. + * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() functions + * in your board-specific logic. These functions will perform chip + * selection and status operations using GPIOs in the way your board + * is configured. + * 3. Add a calls to stm32_spibus_initialize() in your low level + * application initialization logic + * 4. The handle returned by stm32_spibus_initialize() may then be used to + * bind the SPI driver to higher level logic (e.g., calling + * mmcsd_spislotinitialize(), for example, will bind the SPI driver to + * the SPI MMC/SD driver). + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_SPI1 +void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, + bool selected) +{ + spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : + "de-assert"); + +#if defined(CONFIG_MMCSD_SPI) + if (devid == SPIDEV_MMCSD(0)) + { + stm32_gpiowrite(GPIO_SPI1_CS, !selected); + } +#endif +} + +uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) +{ + uint8_t status = 0; +#if defined(CONFIG_MMCSD_SPI) + if (devid == SPIDEV_MMCSD(0)) + { + status |= SPI_STATUS_PRESENT; + } +#endif + + return status; +} +#endif + +#ifdef CONFIG_STM32_SPI2 +void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid, + bool selected) +{ + spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : + "de-assert"); +} + +uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} +#endif + +#ifdef CONFIG_STM32_SPI3 +void stm32_spi3select(struct spi_dev_s *dev, uint32_t devid, + bool selected) +{ + spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : + "de-assert"); +} + +uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} + +#endif + +/**************************************************************************** + * Name: stm32_spi1cmddata + * + * Description: + * Set or clear the SH1101A A0 or SD1306 D/C n bit to select data (true) + * or command (false). This function must be provided by platform-specific + * logic. This is an implementation of the cmddata method of the SPI + * interface defined by struct spi_ops_s (see include/nuttx/spi/spi.h). + * + * Input Parameters: + * + * spi - SPI device that controls the bus the device that requires the CMD/ + * DATA selection. + * devid - If there are multiple devices on the bus, this selects which one + * to select cmd or data. NOTE: This design restricts, for example, + * one one SPI display per SPI bus. + * cmd - true: select command; false: select data + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_SPI_CMDDATA +#ifdef CONFIG_STM32_SPI1 +int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) +{ + return -ENODEV; +} +#endif + +#ifdef CONFIG_STM32_SPI2 +int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) +{ + return -ENODEV; +} +#endif + +#ifdef CONFIG_STM32_SPI3 +int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) +{ + return -ENODEV; +} +#endif +#endif /* CONFIG_SPI_CMDDATA */ + +#endif /* CONFIG_STM32_SPI1 || CONFIG_STM32_SPI2 || CONFIG_STM32_SPI3 */ diff --git a/boards/arm/stm32/nucleo-l152re/src/stm32_spisd.c b/boards/arm/stm32l1/nucleo-l152re/src/stm32_spisd.c similarity index 98% rename from boards/arm/stm32/nucleo-l152re/src/stm32_spisd.c rename to boards/arm/stm32l1/nucleo-l152re/src/stm32_spisd.c index c08c068b2fb90..9683f10cc4c87 100644 --- a/boards/arm/stm32/nucleo-l152re/src/stm32_spisd.c +++ b/boards/arm/stm32l1/nucleo-l152re/src/stm32_spisd.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-l152re/src/stm32_spisd.c + * boards/arm/stm32l1/nucleo-l152re/src/stm32_spisd.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32l1/nucleo-l152re/src/stm32_userleds.c b/boards/arm/stm32l1/nucleo-l152re/src/stm32_userleds.c new file mode 100644 index 0000000000000..bb9d60e5a2c0b --- /dev/null +++ b/boards/arm/stm32l1/nucleo-l152re/src/stm32_userleds.c @@ -0,0 +1,77 @@ +/**************************************************************************** + * boards/arm/stm32l1/nucleo-l152re/src/stm32_userleds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include + +#include "stm32.h" +#include "nucleo-l152re.h" + +#ifndef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_userled_initialize + ****************************************************************************/ + +uint32_t board_userled_initialize(void) +{ + /* Configure LED1 GPIO for output */ + + stm32_configgpio(GPIO_LED1); + return BOARD_NLEDS; +} + +/**************************************************************************** + * Name: board_userled + ****************************************************************************/ + +void board_userled(int led, bool ledon) +{ + if (led == BOARD_LED1) + { + stm32_gpiowrite(GPIO_LED1, ledon); + } +} + +/**************************************************************************** + * Name: board_userled_all + ****************************************************************************/ + +void board_userled_all(uint32_t ledset) +{ + stm32_gpiowrite(GPIO_LED1, (ledset & BOARD_LED1_BIT) != 0); +} + +#endif /* !CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32l1/stm32ldiscovery/CMakeLists.txt b/boards/arm/stm32l1/stm32ldiscovery/CMakeLists.txt new file mode 100644 index 0000000000000..86a0d6e5493ff --- /dev/null +++ b/boards/arm/stm32l1/stm32ldiscovery/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32l1/stm32ldiscovery/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/arm/stm32/stm32ldiscovery/Kconfig b/boards/arm/stm32l1/stm32ldiscovery/Kconfig similarity index 100% rename from boards/arm/stm32/stm32ldiscovery/Kconfig rename to boards/arm/stm32l1/stm32ldiscovery/Kconfig diff --git a/boards/arm/stm32l1/stm32ldiscovery/configs/chrono/defconfig b/boards/arm/stm32l1/stm32ldiscovery/configs/chrono/defconfig new file mode 100644 index 0000000000000..c965f4dc993bf --- /dev/null +++ b/boards/arm/stm32l1/stm32ldiscovery/configs/chrono/defconfig @@ -0,0 +1,65 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_DISABLEBG is not set +# CONFIG_NSH_DISABLE_EXEC is not set +# CONFIG_NSH_DISABLE_EXIT is not set +# CONFIG_NSH_DISABLE_HEXDUMP is not set +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_NSH_DISABLE_XD is not set +# CONFIG_SERIAL is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32ldiscovery" +CONFIG_ARCH_BOARD_STM32L_DISCOVERY=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32l1" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32L152RB=y +CONFIG_ARCH_CHIP_STM32L1=y +CONFIG_ARCH_IRQBUTTONS=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=2796 +CONFIG_BUILTIN=y +CONFIG_DEFAULT_SMALL=y +CONFIG_DISABLE_MOUNTPOINT=y +CONFIG_ENABLE_ALL_SIGNALS=y +CONFIG_EXAMPLES_CHRONO=y +CONFIG_EXAMPLES_SLCD=y +CONFIG_FILE_STREAM=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=1536 +CONFIG_INPUT=y +CONFIG_INPUT_BUTTONS=y +CONFIG_INPUT_BUTTONS_LOWER=y +CONFIG_INTELHEX_BINARY=y +CONFIG_LCD=y +CONFIG_LIBC_SLCDCODEC=y +CONFIG_LWL_CONSOLE=y +CONFIG_MM_SMALL=y +CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=64 +CONFIG_NUNGET_CHARS=0 +CONFIG_POSIX_SPAWN_DEFAULT_STACKSIZE=1536 +CONFIG_PTHREAD_STACK_DEFAULT=1536 +CONFIG_RAM_SIZE=16384 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_RTC_DATETIME=y +CONFIG_SCHED_WAITPID=y +CONFIG_SLCD=y +CONFIG_START_DAY=19 +CONFIG_START_MONTH=5 +CONFIG_START_YEAR=2013 +CONFIG_STDIO_DISABLE_BUFFERING=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_LCD=y +CONFIG_STM32_PWR=y +CONFIG_STM32_RTC=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 diff --git a/boards/arm/stm32l1/stm32ldiscovery/configs/nsh/defconfig b/boards/arm/stm32l1/stm32ldiscovery/configs/nsh/defconfig new file mode 100644 index 0000000000000..e07f7bfeadc46 --- /dev/null +++ b/boards/arm/stm32l1/stm32ldiscovery/configs/nsh/defconfig @@ -0,0 +1,51 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_DISABLEBG is not set +# CONFIG_NSH_DISABLE_EXEC is not set +# CONFIG_NSH_DISABLE_EXIT is not set +# CONFIG_NSH_DISABLE_HEXDUMP is not set +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_NSH_DISABLE_XD is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32ldiscovery" +CONFIG_ARCH_BOARD_STM32L_DISCOVERY=y +CONFIG_ARCH_CHIP="stm32l1" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32L152RB=y +CONFIG_ARCH_CHIP_STM32L1=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=2796 +CONFIG_DEFAULT_SMALL=y +CONFIG_DISABLE_MOUNTPOINT=y +CONFIG_HOST_WINDOWS=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=1536 +CONFIG_INTELHEX_BINARY=y +CONFIG_MM_SMALL=y +CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 +CONFIG_NSH_FILEIOSIZE=64 +CONFIG_NUNGET_CHARS=0 +CONFIG_POSIX_SPAWN_DEFAULT_STACKSIZE=1536 +CONFIG_PTHREAD_STACK_DEFAULT=1536 +CONFIG_RAM_SIZE=16384 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=19 +CONFIG_START_MONTH=5 +CONFIG_START_YEAR=2013 +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_PWR=y +CONFIG_STM32_USART1=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART1_BAUD=57600 +CONFIG_USART1_RXBUFSIZE=64 +CONFIG_USART1_SERIAL_CONSOLE=y +CONFIG_USART1_TXBUFSIZE=64 diff --git a/boards/arm/stm32l1/stm32ldiscovery/include/board.h b/boards/arm/stm32l1/stm32ldiscovery/include/board.h new file mode 100644 index 0000000000000..9e1c58d534cde --- /dev/null +++ b/boards/arm/stm32l1/stm32ldiscovery/include/board.h @@ -0,0 +1,307 @@ +/**************************************************************************** + * boards/arm/stm32l1/stm32ldiscovery/include/board.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_STM32_STM32LDISCOVERY_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32_STM32LDISCOVERY_INCLUDE_BOARD_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#ifndef __ASSEMBLY__ +# include +#endif + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Clocking *****************************************************************/ + +/* Four different clock sources can be used to drive the system clock + * (SYSCLK): + * + * - HSI high-speed internal oscillator clock + * Generated from an internal 16 MHz RC oscillator + * - HSE high-speed external oscillator clock + * Normally driven by an external crystal (X3). However, this crystal is + * not fitted on the STM32L-Discovery board. + * - PLL clock + * - MSI multispeed internal oscillator clock + * The MSI clock signal is generated from an internal RC oscillator. + * Seven frequency ranges are available: 65.536 kHz, 131.072 kHz, + * 262.144 kHz, 524.288 kHz, 1.048 MHz, 2.097 MHz (default value) and + * 4.194 MHz. + * + * The devices have the following two secondary clock sources + * - LSI low-speed internal RC clock + * Drives the watchdog and RTC. Approximately 37KHz + * - LSE low-speed external oscillator clock + * Driven by 32.768KHz crystal (X2) on the OSC32_IN and OSC32_OUT pins. + */ + +#define STM32_BOARD_XTAL 8000000ul /* X3 on board (not fitted)*/ + +#define STM32_HSI_FREQUENCY 16000000ul /* Approximately 16MHz */ +#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL +#define STM32_MSI_FREQUENCY 2097000 /* Default is approximately 2.097Mhz */ +#define STM32_LSI_FREQUENCY 37000 /* Approximately 37KHz */ +#define STM32_LSE_FREQUENCY 32768 /* X2 on board */ + +/* PLL Configuration + * + * - PLL source is HSI -> 16MHz input (nominal) + * - PLL multiplier is 6 -> 96MHz PLL VCO clock output (for USB) + * - PLL output divider 3 -> 32MHz divided down PLL VCO clock output + * + * Resulting SYSCLK frequency is 16MHz x 6 / 3 = 32MHz + * + * USB/SDIO: + * If the USB or SDIO interface is used in the application, the PLL VCO + * clock (defined by STM32_CFGR_PLLMUL) must be programmed to output a 96 + * MHz frequency. This is required to provide a 48 MHz clock to the USB or + * SDIO (SDIOCLK or USBCLK = PLLVCO/2). + * SYSCLK + * The system clock is derived from the PLL VCO divided by the output + * division factor. + * Limitations: + * 96 MHz as PLLVCO when the product is in range 1 (1.8V), + * 48 MHz as PLLVCO when the product is in range 2 (1.5V), + * 24 MHz when the product is in range 3 (1.2V). + * Output division to avoid exceeding 32 MHz as SYSCLK. + * The minimum input clock frequency for PLL is 2 MHz (when using HSE as + * PLL source). + */ + +#define STM32_CFGR_PLLSRC 0 /* Source is 16MHz HSI */ +#ifdef CONFIG_STM32_USB +# define STM32_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx6 /* PLLMUL = 6 */ +# define STM32_CFGR_PLLDIV RCC_CFGR_PLLDIV_3 /* PLLDIV = 3 */ +# define STM32_PLL_FREQUENCY (6*STM32_HSI_FREQUENCY) /* PLL VCO Frequency is 96MHz */ +#else +# define STM32_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx4 /* PLLMUL = 4 */ +# define STM32_CFGR_PLLDIV RCC_CFGR_PLLDIV_2 /* PLLDIV = 2 */ +# define STM32_PLL_FREQUENCY (4*STM32_HSI_FREQUENCY) /* PLL VCO Frequency is 64MHz */ +#endif + +/* Use the PLL and set the SYSCLK source to be the divided down PLL VCO + * output frequency (STM32_PLL_FREQUENCY divided by the PLLDIV value). + */ + +#define STM32_SYSCLK_SW RCC_CFGR_SW_PLL /* Use the PLL as the SYSCLK */ +#define STM32_SYSCLK_SWS RCC_CFGR_SWS_PLL +#ifdef CONFIG_STM32_USB +# define STM32_SYSCLK_FREQUENCY (STM32_PLL_FREQUENCY/3) /* SYSCLK frequency is 96MHz/PLLDIV = 32MHz */ +#else +# define STM32_SYSCLK_FREQUENCY (STM32_PLL_FREQUENCY/2) /* SYSCLK frequency is 64MHz/PLLDIV = 32MHz */ +#endif + +/* AHB clock (HCLK) is SYSCLK (32MHz) */ + +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY + +/* APB2 clock (PCLK2) is HCLK (32MHz) */ + +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK +#define STM32_PCLK2_FREQUENCY STM32_HCLK_FREQUENCY +#define STM32_APB2_CLKIN (STM32_PCLK2_FREQUENCY) + +/* APB2 timers 9, 10, and 11 will receive PCLK2. */ + +#define STM32_APB2_TIM9_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM10_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM11_CLKIN (STM32_PCLK2_FREQUENCY) + +/* APB1 clock (PCLK1) is HCLK (32MHz) */ + +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY) + +/* APB1 timers 2-7 will receive PCLK1 */ + +#define STM32_APB1_TIM2_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM5_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (STM32_PCLK1_FREQUENCY) + +/* LED definitions **********************************************************/ + +/* The STM32L-Discovery board has four LEDs. Two of these are controlled by + * logic on the board and are not available for software control: + * + * LD1 COM: LD2 default status is red. LD2 turns to green to indicate + * that communications are in progress between the PC and the + * ST-LINK/V2. + * LD2 PWR: Red LED indicates that the board is powered. + * + * And two LEDs can be controlled by software: + * + * User LD3: Green LED is a user LED connected to the I/O PB7 of the + * STM32L152 MCU. + * User LD4: Blue LED is a user LED connected to the I/O PB6 of the + * STM32L152 MCU. + * + * If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs in + * any way. The following definitions are used to access individual LEDs. + */ + +/* LED index values for use with board_userled() */ + +#define BOARD_LED1 0 /* User LD3 */ +#define BOARD_LED2 1 /* User LD4 */ +#define BOARD_NLEDS 2 + +/* LED bits for use with board_userled_all() */ + +#define BOARD_LED1_BIT (1 << BOARD_LED1) +#define BOARD_LED2_BIT (1 << BOARD_LED2) + +/* If CONFIG_ARCH_LEDS is defined, then NuttX will control the 2 LEDs on + * board the STM32L-Discovery. The following definitions describe how NuttX + * controls the LEDs: + * + * SYMBOL Meaning LED state + * LED1 LED2 + * ------------------- ----------------------- -------- -------- + * LED_STARTED NuttX has been started OFF OFF + * LED_HEAPALLOCATE Heap has been allocated OFF OFF + * LED_IRQSENABLED Interrupts enabled OFF OFF + * LED_STACKCREATED Idle stack created ON OFF + * LED_INIRQ In an interrupt No change + * LED_SIGNAL In a signal handler No change + * LED_ASSERTION An assertion failed No change + * LED_PANIC The system has crashed OFF Blinking + * LED_IDLE STM32 is in sleep mode Not used + */ + +#define LED_STARTED 0 +#define LED_HEAPALLOCATE 0 +#define LED_IRQSENABLED 0 +#define LED_STACKCREATED 1 +#define LED_INIRQ 2 +#define LED_SIGNAL 2 +#define LED_ASSERTION 2 +#define LED_PANIC 3 + +/* Button definitions *******************************************************/ + +/* The STM32L-Discovery supports two buttons; only one button is controllable + * by software: + * + * B1 USER: user and wake-up button connected to the I/O PA0 of the + * STM32L152. + * B2 RESET: pushbutton connected to NRST is used to RESET the STM32L152. + */ + +#define BUTTON_USER 0 +#define NUM_BUTTONS 1 + +#define BUTTON_USER_BIT (1 << BUTTON_USER) + +/* Alternate Pin Functions **************************************************/ + +/* The STM32L-Discovery has no on-board RS-232 driver. Further, there + * are no USART pins that do not conflict with the on board resources, in + * particular, the LCD. Most USART pins are available if the LCD is enabled; + * USART2 may be used if either the LCD or the on-board LEDs are disabled. + * + * PA9 USART1_TX LCD glass COM1 P2, pin 22 + * PA10 USART1_RX LCD glass COM2 P2, pin 21 + * PB6 USART1_TX LED Blue P2, pin 8 + * PB7 USART1_RX LED Green P2, pin 7 + * + * PA2 USART2_TX LCD SEG1 P1, pin 17 + * PA3 USART2_RX LCD SEG2 P1, pin 18 + * + * PB10 USART3_TX LCD SEG6 P1, pin 22 + * PB11 USART3_RX LCD SEG7 P1, pin 23 + * PC10 USART3_TX LCD SEG22 P2, pin 15 + * PC11 USART3_RX LCD SEG23 P2, pin 14 + */ + +#if !defined(CONFIG_STM32_LCD) +/* Select PA9 and PA10 if the LCD is not enabled */ + +# define GPIO_USART1_RX (GPIO_USART1_RX_1|GPIO_SPEED_40MHz) /* PA10 */ +# define GPIO_USART1_TX (GPIO_USART1_TX_1|GPIO_SPEED_40MHz) /* PA9 */ + +/* This there are no other options for USART1 on this part */ + +# define GPIO_USART2_RX (GPIO_USART2_RX_1|GPIO_SPEED_40MHz) /* PA3 */ +# define GPIO_USART2_TX (GPIO_USART2_TX_1|GPIO_SPEED_40MHz) /* PA2 */ + +/* Arbitrarily select PB10 and PB11 */ + +# define GPIO_USART3_RX (GPIO_USART3_RX_1|GPIO_SPEED_40MHz) /* PB11 */ +# define GPIO_USART3_TX (GPIO_USART3_TX_1|GPIO_SPEED_40MHz) /* PB10 */ + +#elif !defined(CONFIG_ARCH_LEDS) + +/* Select PB6 and PB7 if the LEDs are not enabled */ + +# define GPIO_USART1_RX (GPIO_USART1_RX_2|GPIO_SPEED_40MHz) /* PB7 */ +# define GPIO_USART1_TX (GPIO_USART1_TX_2|GPIO_SPEED_40MHz) /* PB6 */ + +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +# define EXTERN extern "C" +extern "C" +{ +#else +# define EXTERN extern +#endif + +/**************************************************************************** + * Name: stm32_slcd_initialize + * + * Description: + * Initialize the STM32L-Discovery LCD hardware and register the character + * driver as /dev/slcd0. + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_LCD +int stm32_slcd_initialize(void); +#endif + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __BOARDS_ARM_STM32_STM32LDISCOVERY_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32l1/stm32ldiscovery/scripts/Make.defs b/boards/arm/stm32l1/stm32ldiscovery/scripts/Make.defs new file mode 100644 index 0000000000000..ac42a7137153e --- /dev/null +++ b/boards/arm/stm32l1/stm32ldiscovery/scripts/Make.defs @@ -0,0 +1,46 @@ +############################################################################ +# boards/arm/stm32l1/stm32ldiscovery/scripts/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/.config +include $(TOPDIR)/tools/Config.mk +include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs + +ifeq ($(CONFIG_ARCH_CHIP_STM32L152RB),y) + LDSCRIPT = stm32l152rb.ld +else ifeq ($(CONFIG_ARCH_CHIP_STM32L152RC),y) + LDSCRIPT = stm32l152rc.ld +endif + +ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) + +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32/stm32ldiscovery/scripts/stm32l152rb.ld b/boards/arm/stm32l1/stm32ldiscovery/scripts/stm32l152rb.ld similarity index 98% rename from boards/arm/stm32/stm32ldiscovery/scripts/stm32l152rb.ld rename to boards/arm/stm32l1/stm32ldiscovery/scripts/stm32l152rb.ld index bb8c62933c6cf..184ed2885092f 100644 --- a/boards/arm/stm32/stm32ldiscovery/scripts/stm32l152rb.ld +++ b/boards/arm/stm32l1/stm32ldiscovery/scripts/stm32l152rb.ld @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32ldiscovery/scripts/stm32l152rb.ld + * boards/arm/stm32l1/stm32ldiscovery/scripts/stm32l152rb.ld * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32ldiscovery/scripts/stm32l152rc.ld b/boards/arm/stm32l1/stm32ldiscovery/scripts/stm32l152rc.ld similarity index 98% rename from boards/arm/stm32/stm32ldiscovery/scripts/stm32l152rc.ld rename to boards/arm/stm32l1/stm32ldiscovery/scripts/stm32l152rc.ld index 81b7157ce808e..d295e75c07a35 100644 --- a/boards/arm/stm32/stm32ldiscovery/scripts/stm32l152rc.ld +++ b/boards/arm/stm32l1/stm32ldiscovery/scripts/stm32l152rc.ld @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32ldiscovery/scripts/stm32l152rc.ld + * boards/arm/stm32l1/stm32ldiscovery/scripts/stm32l152rc.ld * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32l1/stm32ldiscovery/src/CMakeLists.txt b/boards/arm/stm32l1/stm32ldiscovery/src/CMakeLists.txt new file mode 100644 index 0000000000000..a496f64f86b20 --- /dev/null +++ b/boards/arm/stm32l1/stm32ldiscovery/src/CMakeLists.txt @@ -0,0 +1,51 @@ +# ############################################################################## +# boards/arm/stm32l1/stm32ldiscovery/src/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(SRCS stm32_boot.c stm32_bringup.c stm32_spi.c) + +if(CONFIG_ARCH_LEDS) + list(APPEND SRCS stm32_autoleds.c) +else() + list(APPEND SRCS stm32_userleds.c) +endif() + +if(CONFIG_ARCH_BUTTONS) + list(APPEND SRCS stm32_buttons.c) +endif() + +if(CONFIG_STM32_LCD) + list(APPEND SRCS stm32_lcd.c) +endif() + +if(CONFIG_PWM) + list(APPEND SRCS stm32_pwm.c) +endif() + +target_sources(board PRIVATE ${SRCS}) + +if(CONFIG_ARCH_CHIP_STM32L152RB) + set_property(GLOBAL PROPERTY LD_SCRIPT + "${NUTTX_BOARD_DIR}/scripts/stm32l152rb.ld") +else() + set_property(GLOBAL PROPERTY LD_SCRIPT + "${NUTTX_BOARD_DIR}/scripts/stm32l152rc.ld") +endif() diff --git a/boards/arm/stm32l1/stm32ldiscovery/src/Make.defs b/boards/arm/stm32l1/stm32ldiscovery/src/Make.defs new file mode 100644 index 0000000000000..f483afc2b244c --- /dev/null +++ b/boards/arm/stm32l1/stm32ldiscovery/src/Make.defs @@ -0,0 +1,47 @@ +############################################################################ +# boards/arm/stm32l1/stm32ldiscovery/src/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +CSRCS = stm32_boot.c stm32_bringup.c stm32_spi.c + +ifeq ($(CONFIG_ARCH_LEDS),y) +CSRCS += stm32_autoleds.c +else +CSRCS += stm32_userleds.c +endif + +ifeq ($(CONFIG_ARCH_BUTTONS),y) +CSRCS += stm32_buttons.c +endif + +ifeq ($(CONFIG_STM32_LCD),y) +CSRCS += stm32_lcd.c +endif + +ifeq ($(CONFIG_PWM),y) +CSRCS += stm32_pwm.c +endif + +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32l1/stm32ldiscovery/src/stm32_autoleds.c b/boards/arm/stm32l1/stm32ldiscovery/src/stm32_autoleds.c new file mode 100644 index 0000000000000..e62f9ed148452 --- /dev/null +++ b/boards/arm/stm32l1/stm32ldiscovery/src/stm32_autoleds.c @@ -0,0 +1,124 @@ +/**************************************************************************** + * boards/arm/stm32l1/stm32ldiscovery/src/stm32_autoleds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "chip.h" +#include "stm32.h" +#include "stm32ldiscovery.h" + +#ifdef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* If CONFIG_ARCH_LEDS is defined, then NuttX will control the 2 LEDs on + * board the STM32L-Discovery. The following definitions describe how NuttX + * controls the LEDs: + * + * SYMBOL Meaning LED state + * LED1 LED2 + * ------------------- ----------------------- -------- -------- + * LED_STARTED NuttX has been started OFF OFF + * LED_HEAPALLOCATE Heap has been allocated OFF OFF + * LED_IRQSENABLED Interrupts enabled OFF OFF + * LED_STACKCREATED Idle stack created ON OFF + * LED_INIRQ In an interrupt No change + * LED_SIGNAL In a signal handler No change + * LED_ASSERTION An assertion failed No change + * LED_PANIC The system has crashed OFF Blinking + * LED_IDLE STM32 is in sleep mode Not used + */ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_autoled_initialize + ****************************************************************************/ + +void board_autoled_initialize(void) +{ + /* Configure LED1-2 GPIOs for output */ + + stm32_configgpio(GPIO_LED1); + stm32_configgpio(GPIO_LED2); +} + +/**************************************************************************** + * Name: board_autoled_on + ****************************************************************************/ + +void board_autoled_on(int led) +{ + bool led1on = false; + bool led2on = false; + + switch (led) + { + case 0: /* LED_STARTED, LED_HEAPALLOCATE, LED_IRQSENABLED */ + break; + + case 1: /* LED_STACKCREATED */ + led1on = true; + break; + + default: + case 2: /* LED_INIRQ, LED_SIGNAL, LED_ASSERTION */ + return; + + case 3: /* LED_PANIC */ + led2on = true; + break; + } + + stm32_gpiowrite(GPIO_LED1, led1on); + stm32_gpiowrite(GPIO_LED2, led2on); +} + +/**************************************************************************** + * Name: board_autoled_off + ****************************************************************************/ + +void board_autoled_off(int led) +{ + if (led != 2) + { + stm32_gpiowrite(GPIO_LED1, false); + stm32_gpiowrite(GPIO_LED2, false); + } +} + +#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32l1/stm32ldiscovery/src/stm32_boot.c b/boards/arm/stm32l1/stm32ldiscovery/src/stm32_boot.c new file mode 100644 index 0000000000000..751e937f7996c --- /dev/null +++ b/boards/arm/stm32l1/stm32ldiscovery/src/stm32_boot.c @@ -0,0 +1,91 @@ +/**************************************************************************** + * boards/arm/stm32l1/stm32ldiscovery/src/stm32_boot.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include +#include + +#include "arm_internal.h" +#include "stm32ldiscovery.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_boardinitialize + * + * Description: + * All STM32 architectures must provide the following entry point. + * This entry point is called early in the initialization -- after all + * memory has been configured and mapped but before any devices have been + * initialized. + * + ****************************************************************************/ + +void stm32_boardinitialize(void) +{ + /* Configure SPI chip selects if 1) SPI is not disabled, and 2) the weak + * function stm32_spidev_initialize() has been brought into the link. + */ + +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || defined(CONFIG_STM32_SPI3) + if (stm32_spidev_initialize) + { + stm32_spidev_initialize(); + } +#endif + + /* Configure on-board LEDs if LED support has been selected. */ + +#ifdef CONFIG_ARCH_LEDS + board_autoled_initialize(); +#endif +} + +/**************************************************************************** + * Name: board_late_initialize + * + * Description: + * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_late_initialize(). board_late_initialize() will + * be called immediately after up_initialize() is called and just before + * the initial application is started. This additional initialization + * phase may be used, for example, to initialize board-specific device + * drivers. + * + ****************************************************************************/ + +#ifdef CONFIG_BOARD_LATE_INITIALIZE +void board_late_initialize(void) +{ + stm32_bringup(); +} +#endif diff --git a/boards/arm/stm32l1/stm32ldiscovery/src/stm32_bringup.c b/boards/arm/stm32l1/stm32ldiscovery/src/stm32_bringup.c new file mode 100644 index 0000000000000..ee512f314b309 --- /dev/null +++ b/boards/arm/stm32l1/stm32ldiscovery/src/stm32_bringup.c @@ -0,0 +1,140 @@ +/**************************************************************************** + * boards/arm/stm32l1/stm32ldiscovery/src/stm32_bringup.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include +#include +#include + +#include + +#include "stm32ldiscovery.h" + +#ifdef CONFIG_SENSORS_QENCODER +# include "board_qencoder.h" +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_bringup + * + * Description: + * Perform architecture-specific initialization + * + * CONFIG_BOARD_LATE_INITIALIZE=y : + * Called from board_late_initialize(). + * + ****************************************************************************/ + +int stm32_bringup(void) +{ + int ret = OK; + +#ifdef CONFIG_FS_PROCFS + /* Mount the procfs file system */ + + ret = nx_mount(NULL, "/proc", "procfs", 0, NULL); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to mount procfs at /proc: %d\n", ret); + } +#endif + +#if defined(CONFIG_USERLED) && !defined(CONFIG_ARCH_LEDS) +#ifdef CONFIG_USERLED_LOWER + /* Register the LED driver */ + + ret = userled_lower_initialize("/dev/userleds"); + if (ret != OK) + { + syslog(LOG_ERR, "ERROR: userled_lower_initialize() failed: %d\n", ret); + } +#else + /* Enable USER LED support for some other purpose */ + + board_userled_initialize(); +#endif /* CONFIG_USERLED_LOWER */ +#endif /* CONFIG_USERLED && !CONFIG_ARCH_LEDS */ + +#ifdef CONFIG_INPUT_BUTTONS +#ifdef CONFIG_INPUT_BUTTONS_LOWER + /* Register the BUTTON driver */ + + ret = btn_lower_initialize("/dev/buttons"); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: btn_lower_initialize() failed: %d\n", ret); + } +#else + /* Enable BUTTON support for some other purpose */ + + board_button_initialize(); +#endif /* CONFIG_INPUT_BUTTONS_LOWER */ +#endif /* CONFIG_INPUT_BUTTONS */ + +#ifdef CONFIG_STM32_LCD + /* Initialize the SLCD and register the SLCD device as /dev/slcd0 */ + + ret = stm32_slcd_initialize(); + if (ret != OK) + { + syslog(LOG_ERR, "ERROR: stm32_slcd_initialize failed: %d\n", ret); + return ret; + } +#endif + +#ifdef CONFIG_PWM + /* Initialize PWM and register the PWM device. */ + + ret = stm32_pwm_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_pwm_setup() failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_SENSORS_QENCODER + /* Initialize and register the qencoder driver */ + + ret = board_qencoder_initialize(0, CONFIG_STM32LDISCO_QETIMER); + if (ret != OK) + { + syslog(LOG_ERR, + "ERROR: Failed to register the qencoder: %d\n", + ret); + } +#endif + + return ret; +} diff --git a/boards/arm/stm32l1/stm32ldiscovery/src/stm32_buttons.c b/boards/arm/stm32l1/stm32ldiscovery/src/stm32_buttons.c new file mode 100644 index 0000000000000..3f0e1ffb3311d --- /dev/null +++ b/boards/arm/stm32l1/stm32ldiscovery/src/stm32_buttons.c @@ -0,0 +1,151 @@ +/**************************************************************************** + * boards/arm/stm32l1/stm32ldiscovery/src/stm32_buttons.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include +#include + +#include "stm32_gpio.h" +#include "stm32ldiscovery.h" + +#ifdef CONFIG_ARCH_BUTTONS + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* Pin configuration for each STM32F3Discovery button. This array is indexed + * by the BUTTON_* definitions in board.h + */ + +static const uint32_t g_buttons[NUM_BUTTONS] = +{ + GPIO_BTN_USER +}; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_button_initialize + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. + * + ****************************************************************************/ + +uint32_t board_button_initialize(void) +{ + int i; + + /* Configure the GPIO pins as inputs. NOTE that EXTI interrupts are + * configured for all pins. + */ + + for (i = 0; i < NUM_BUTTONS; i++) + { + stm32_configgpio(g_buttons[i]); + } + + return NUM_BUTTONS; +} + +/**************************************************************************** + * Name: board_buttons + ****************************************************************************/ + +uint32_t board_buttons(void) +{ + uint32_t ret = 0; + int i; + + /* Check that state of each key */ + + for (i = 0; i < NUM_BUTTONS; i++) + { + /* A LOW value means that the key is pressed. */ + + bool released = stm32_gpioread(g_buttons[i]); + + /* Accumulate the set of depressed (not released) keys */ + + if (!released) + { + ret |= (1 << i); + } + } + + return ret; +} + +/**************************************************************************** + * Button support. + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. + * + * After board_button_initialize() has been called, board_buttons() may be + * called to collect the state of all buttons. board_buttons() returns an + * 32-bit bit set with each bit associated with a button. See the + * BUTTON_*_BIT definitions in board.h for the meaning of each bit. + * + * board_button_irq() may be called to register an interrupt handler that + * will be called when a button is depressed or released. The ID value is a + * button enumeration value that uniquely identifies a button resource. See + * the BUTTON_* definitions in board.h for the meaning of enumeration + * value. + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_IRQBUTTONS +int board_button_irq(int id, xcpt_t irqhandler, void *arg) +{ + int ret = -EINVAL; + + /* The following should be atomic */ + + if (id >= MIN_IRQBUTTON && id <= MAX_IRQBUTTON) + { + ret = stm32_gpiosetevent(g_buttons[id], true, true, true, + irqhandler, arg); + } + + return ret; +} +#endif +#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/stm32l1/stm32ldiscovery/src/stm32_lcd.c b/boards/arm/stm32l1/stm32ldiscovery/src/stm32_lcd.c new file mode 100644 index 0000000000000..379abcfa7bdb2 --- /dev/null +++ b/boards/arm/stm32l1/stm32ldiscovery/src/stm32_lcd.c @@ -0,0 +1,1599 @@ +/**************************************************************************** + * boards/arm/stm32l1/stm32ldiscovery/src/stm32_lcd.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* References: + * - Based on the NuttX LCD1602 driver. + * - "STM32L100xx, STM32L151xx, STM32L152xx and STM32L162xx advanced + * ARM-based 32-bit MCUs", STMicroelectronics, RM0038 + * - "STM32L1 discovery kits: STM32L-DISCOVERY and 32L152CDISCOVERY," + * STMicroelectronics, UM1079 + * - STM32L-Discovery Firmware Pack V1.0.2 (for character encoding) + */ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#include "arm_internal.h" +#include "stm32_gpio.h" +#include "stm32_rcc.h" +#include "hardware/stm32_lcd.h" + +#include "stm32ldiscovery.h" + +#ifdef CONFIG_STM32_LCD + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* Define CONFIG_DEBUG_LCD_INFO to enable detailed LCD debug output. */ + +#ifndef CONFIG_LIBC_SLCDCODEC +# error "This SLCD driver requires CONFIG_LIBC_SLCDCODEC" +#endif + +/* LCD **********************************************************************/ + +/* LCD. The STM32L152RBT6 supports either a 4x32 or 8x28. The STM32L- + * Discovery has an LCD 24 segments, 4 commons. See stm32ldiscovery.h for + * the pin mapping. + */ + +/* Macro to convert an LCD register offset and bit number into a bit-band + * address: + */ + +#define SLCD_OFFSET (STM32_LCD_BASE - STM32_PERIPH_BASE) +#define SLCD_BBADDR(o,b) (STM32_PERIPHBB_BASE + ((SLCD_OFFSET + (o)) << 5) + ((b) << 2)) + +/* Some useful bit-band addresses */ + +#define SLCD_CR_LCDEN_BB SLCD_BBADDR(STM32_LCD_CR_OFFSET,0) +#define SLCD_SR_UDR_BB SLCD_BBADDR(STM32_LCD_SR_OFFSET,2) + +/* LCD characteristics */ + +#define SLCD_NROWS 1 +#define SLCD_NCHARS 6 +#define SLCD_MAXCONTRAST 7 + +/* An ASCII character may need to be decorated with a colon or decimal + * point + */ + +#define SLCD_DP 0x01 +#define SLCD_COLON 0x02 +#define SLCD_NBARS 4 + +/* Macros used for set/reset the LCD bar */ + +#define SLCD_BAR0_ON g_slcdstate.bar[1] |= 8 +#define SLCD_BAR0_OFF g_slcdstate.bar[1] &= ~8 +#define SLCD_BAR1_ON g_slcdstate.bar[0] |= 8 +#define SLCD_BAR1_OFF g_slcdstate.bar[0] &= ~8 +#define SLCD_BAR2_ON g_slcdstate.bar[1] |= 2 +#define SLCD_BAR2_OFF g_slcdstate.bar[1] &= ~2 +#define SLCD_BAR3_ON g_slcdstate.bar[0] |= 2 +#define SLCD_BAR3_OFF g_slcdstate.bar[0] &= ~2 + +/* These definitions support the logic of slcd_writemem() + * + * ---------- ----- ----- ----- ----- ------- + * LCD SIGNAL COM3 COM2 COM1 COM0 RAM BIT + * + * ---------- ----- ----- ----- ----- ------- + * LCD SEG0 1N 1P 1D 1E Bit 0 + * LCD SEG1 1DP 1COL 1C 1M Bit 1 + * LCD SEG2 2N 2P 2D 2E Bit 2 + * LCD SEG3 2DP 2COL 2C 2M Bit 7 + * LCD SEG4 3N 3P 3D 3E Bit 8 + * LCD SEG5 3DP 3COL 3C 3M Bit 9 + * LCD SEG6 4N 4P 4D 4E Bit 10 + * LCD SEG7 4DP 4COL 4C 4M Bit 11 + * LCD SEG8 5N 5P 5D 5E Bit 12 + * LCD SEG9 BAR2 BAR3 5C 5M Bit 13 + * LCD SEG10 6N 6P 6D 6E Bit 14 + * LCD SEG11 BAR0 BAR1 6C 6M Bit 15 + * LCD SEG12 6J 6K 6A 6B Bit 16 + * LCD SEG13 6H 6Q 6F 6G Bit 17 + * LCD SEG14 5J 5K 5A 5B Bit 18 + * LCD SEG15 5H 5Q 5F 5G Bit 19 + * LCD SEG16 4J 4K 4A 4B Bit 20 + * LCD SEG17 4H 4Q 4F 4G Bit 21 + * LCD SEG18 3J 3K 3A 3B Bit 24 + * LCD SEG19 3H 3Q 3F 3G Bit 25 + * LCD SEG20 2J 2K 2A 2B Bit 26 + * LCD SEG21 2H 2Q 2F 2G Bit 27 + * LCD SEG22 1J 1K 1A 1B Bit 28 + * LCD SEG23 1H 1Q 1F 1G Bit 29 + * ---------- ----- ----- ----- ----- -------- + + * ---------------- ------ ------ ------ ------- ------- -------------------- + * LCD CHAR 1 CHAR 2 CHAR 3 CHAR 4 CHAR 5 CHAR 6 MASKS + * SIGNAL 3210 3210 3210 3210 32 10 32 10 + * --------- ------ ------ ------ ------ -- --- -- --- -------------------- + * LCD SEG0 1 0 0 0 0 0 0 0 CHAR 1: 0xcffffffc + * LCD SEG1 0 0 0 0 0 0 0 0 CHAR 1: 0xcffffffc + * LCD SEG2 0 1 0 0 0 0 0 0 CHAR 2: 0xf3ffff7b + * LCD SEG3 0 1 0 0 0 0 0 0 CHAR 2: 0xf3ffff7b + * LCD SEG4 0 0 1 0 0 0 0 0 CHAR 3: 0xfcfffcff + * LCD SEG5 0 0 1 0 0 0 0 0 CHAR 3: 0xfcfffcff + * LCD SEG6 0 0 0 1 0 0 0 0 CHAR 4: 0xffcff3ff + * LCD SEG7 0 0 0 1 0 0 0 0 CHAR 4: 0xffcff3ff + * LCD SEG8 0 0 0 0 1 1 0 0 CHAR 5: 0xfff3cfff/ + * 0xfff3efff + * LCD SEG9 0 0 0 0 0 1 0 0 CHAR 5: 0xfff3cfff/ + * 0xfff3efff + * LCD SEG10 0 0 0 0 0 0 1 1 CHAR 6: 0xfffc3fff/ + * 0xfffcbfff + * LCD SEG11 0 0 0 0 0 0 0 1 CHAR 6: 0xfffc3fff/ + * 0xfffcbfff + * LCD SEG12 0 0 0 0 0 0 1 1 CHAR 6: 0xfffc3fff/ + * 0xfffcbfff + * LCD SEG13 0 0 0 0 0 0 1 1 CHAR 6: 0xfffc3fff/ + * 0xfffcbfff + * LCD SEG14 0 0 0 0 1 1 0 0 CHAR 5: 0xfff3cfff/ + * 0xfff3efff + * LCD SEG15 0 0 0 0 1 1 0 0 CHAR 5: 0xfff3cfff/ + * 0xfff3efff + * LCD SEG16 0 0 0 1 0 0 0 0 CHAR 4: 0xffcff3ff + * LCD SEG17 0 0 0 1 0 0 0 0 CHAR 4: 0xffcff3ff + * LCD SEG18 0 0 1 0 0 0 0 0 CHAR 3: 0xfcfffcff + * LCD SEG19 0 0 1 0 0 0 0 0 CHAR 3: 0xfcfffcff + * LCD SEG20 0 1 0 0 0 0 0 0 CHAR 2: 0xf3ffff7b + * LCD SEG21 0 1 0 0 0 0 0 0 CHAR 2: 0xf3ffff7b + * LCD SEG22 1 0 0 0 0 0 0 0 CHAR 1: 0xcffffffc + * LCD SEG23 1 0 0 0 0 0 0 0 CHAR 1: 0xcffffffc + * --------- ------ ------ ------ ------- ------- --------------------------- + */ + +/* SLCD_CHAR1_MASK COM0-3 0xcffffffc ..11 .... .... .... .... .... .... ..11 + */ + +#define SLCD_CHAR1_MASK0 0xcffffffc +#define SLCD_CHAR1_MASK1 SLCD_CHAR1_MASK0 +#define SLCD_CHAR1_MASK2 SLCD_CHAR1_MASK0 +#define SLCD_CHAR1_MASK3 SLCD_CHAR1_MASK0 +#define SLCD_CHAR1_UPDATE0(s) (((uint32_t)(s) & 0x0c) << 26) | \ + ((uint32_t)(s) & 0x03) +#define SLCD_CHAR1_UPDATE1(s) SLCD_CHAR1_UPDATE0(s) +#define SLCD_CHAR1_UPDATE2(s) SLCD_CHAR1_UPDATE0(s) +#define SLCD_CHAR1_UPDATE3(s) SLCD_CHAR1_UPDATE0(s) + +/* SLCD_CHAR2_MASK COM0-3 0xf3ffff03 .... 22.. .... .... .... .... 2... .2.. + */ + +#define SLCD_CHAR2_MASK0 0xf3ffff7b +#define SLCD_CHAR2_MASK1 SLCD_CHAR2_MASK0 +#define SLCD_CHAR2_MASK2 SLCD_CHAR2_MASK0 +#define SLCD_CHAR2_MASK3 SLCD_CHAR2_MASK0 +#define SLCD_CHAR2_UPDATE0(s) (((uint32_t)(s) & 0x0c) << 24) | \ + (((uint32_t)(s) & 0x02) << 6) | \ + (((uint32_t)(s) & 0x01) << 2) +#define SLCD_CHAR2_UPDATE1(s) SLCD_CHAR2_UPDATE0(s) +#define SLCD_CHAR2_UPDATE2(s) SLCD_CHAR2_UPDATE0(s) +#define SLCD_CHAR2_UPDATE3(s) SLCD_CHAR2_UPDATE0(s) + +/* SLCD_CHAR3_MASK COM0-3 0xfcfffcff .... ..33 .... .... .... ..33 .... .... + */ + +#define SLCD_CHAR3_MASK0 0xfcfffcff +#define SLCD_CHAR3_MASK1 SLCD_CHAR3_MASK0 +#define SLCD_CHAR3_MASK2 SLCD_CHAR3_MASK0 +#define SLCD_CHAR3_MASK3 SLCD_CHAR3_MASK0 +#define SLCD_CHAR3_UPDATE0(s) (((uint32_t)(s) & 0x0c) << 22) | \ + (((uint32_t)(s) & 0x03) << 8) +#define SLCD_CHAR3_UPDATE1(s) SLCD_CHAR3_UPDATE0(s) +#define SLCD_CHAR3_UPDATE2(s) SLCD_CHAR3_UPDATE0(s) +#define SLCD_CHAR3_UPDATE3(s) SLCD_CHAR3_UPDATE0(s) + +/* SLCD_CHAR4_MASK COM0-3 0xffcff3ff .... .... ..44 .... .... 44.. .... .... + */ + +#define SLCD_CHAR4_MASK0 0xffcff3ff +#define SLCD_CHAR4_MASK1 SLCD_CHAR4_MASK0 +#define SLCD_CHAR4_MASK2 SLCD_CHAR4_MASK0 +#define SLCD_CHAR4_MASK3 SLCD_CHAR4_MASK0 +#define SLCD_CHAR4_UPDATE0(s) (((uint32_t)(s) & 0x0c) << 18) | \ + (((uint32_t)(s) & 0x03) << 10) +#define SLCD_CHAR4_UPDATE1(s) SLCD_CHAR4_UPDATE0(s) +#define SLCD_CHAR4_UPDATE2(s) SLCD_CHAR4_UPDATE0(s) +#define SLCD_CHAR4_UPDATE3(s) SLCD_CHAR4_UPDATE0(s) + +/* SLCD_CHAR5_MASK COM0-1 0xfff3cfff .... .... .... 55.. ..55 .... .... .... + * COM2-3 0xfff3efff .... .... .... 55.. ...5 .... .... .... + */ + +#define SLCD_CHAR5_MASK0 0xfff3cfff +#define SLCD_CHAR5_MASK1 SLCD_CHAR5_MASK0 +#define SLCD_CHAR5_MASK2 0xfff3efff +#define SLCD_CHAR5_MASK3 SLCD_CHAR5_MASK2 +#define SLCD_CHAR5_UPDATE0(s) (((uint32_t)(s) & 0x0c) << 16) | \ + (((uint32_t)(s) & 0x03) << 12) +#define SLCD_CHAR5_UPDATE1(s) SLCD_CHAR5_UPDATE0(s) +#define SLCD_CHAR5_UPDATE2(s) (((uint32_t)(s) & 0x0c) << 16) | \ + (((uint32_t)(s) & 0x01) << 12) +#define SLCD_CHAR5_UPDATE3(s) SLCD_CHAR5_UPDATE2(s) + +/* SLCD_CHAR6_MASK COM0-1 0xfffc3fff .... .... .... ..66 66.. .... .... .... + * COM2-3 0xfffc3fff .... .... .... ..66 .6.. .... .... .... + */ + +#define SLCD_CHAR6_MASK0 0xfffc3fff +#define SLCD_CHAR6_MASK1 SLCD_CHAR6_MASK0 +#define SLCD_CHAR6_MASK2 0xfffcbfff +#define SLCD_CHAR6_MASK3 SLCD_CHAR6_MASK2 +#define SLCD_CHAR6_UPDATE0(s) (((uint32_t)(s) & 0x04) << 15) | \ + (((uint32_t)(s) & 0x08) << 13) | \ + (((uint32_t)(s) & 0x03) << 14) +#define SLCD_CHAR6_UPDATE1(s) SLCD_CHAR6_UPDATE0(s) +#define SLCD_CHAR6_UPDATE2(s) (((uint32_t)(s) & 0x04) << 15) | \ + (((uint32_t)(s) & 0x08) << 13) | \ + (((uint32_t)(s) & 0x03) << 14) +#define SLCD_CHAR6_UPDATE3(s) SLCD_CHAR6_UPDATE2(s) + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/* Global SLCD state */ + +struct stm32_slcdstate_s +{ + bool initialized; /* True: Completed initialization sequence */ + uint8_t curpos; /* The current cursor position */ + uint8_t buffer[SLCD_NCHARS]; /* SLCD ASCII content */ + uint8_t options[SLCD_NCHARS]; /* With colon or decimal point decoration */ + uint8_t bar[2]; /* Controls the bars on the far right of the SLCD */ +}; + +/**************************************************************************** + * Private Function Protototypes + ****************************************************************************/ + +/* Debug */ + +#ifdef CONFIG_DEBUG_LCD_INFO +static void slcd_dumpstate(const char *msg); +static void slcd_dumpslcd(const char *msg); +#else +# define slcd_dumpstate(msg) +# define slcd_dumpslcd(msg) +#endif + +/* Internal utilities */ + +static void slcd_clear(void); +static uint8_t slcd_getcontrast(void); +static int slcd_setcontrast(uint8_t contrast); +static void slcd_writebar(void); +static inline uint16_t slcd_mapch(uint8_t ch); +static inline void slcd_writemem(uint16_t segset, int curpos); +static void slcd_writech(uint8_t ch, uint8_t curpos, uint8_t options); +static void slcd_appendch(uint8_t ch, uint8_t options); +static void slcd_action(enum slcdcode_e code, uint8_t count); + +/* Character driver methods */ + +static ssize_t slcd_read(struct file *, char *, size_t); +static ssize_t slcd_write(struct file *, const char *, size_t); +static int slcd_ioctl(struct file *filep, int cmd, unsigned long arg); +static int slcd_poll(struct file *filep, struct pollfd *fds, + bool setup); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* This is the driver state structure (there is no retained state + * information) + */ + +static const struct file_operations g_slcdops = +{ + NULL, /* open */ + NULL, /* close */ + slcd_read, /* read */ + slcd_write, /* write */ + NULL, /* seek */ + slcd_ioctl, /* ioctl */ + NULL, /* mmap */ + NULL, /* truncate */ + slcd_poll /* poll */ +}; + +/* LCD state data */ + +static struct stm32_slcdstate_s g_slcdstate; + +/* LCD Mapping + * + * A + * --------- _ + * |\ |J /| |_| COL + * F| H | K |B + * | \ | / | _ + * --G-- --M-+ |_| COL + * | /| \ | + * E| Q | N |C + * | / |P \| _ + * --------- |_| DP + * D + * + * LCD character 16-bit-encoding: + * { E , D , P , N, M , C , COL , DP, B , A , K , J, G , F , Q , H } + */ + +#warning "Encodings for all punctuation are incomplete" + +/* Space and ASCII punctuation: 0x20-0x2f */ + +static const uint16_t g_slcdpunct1[ASCII_0 - ASCII_SPACE] = +{ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /* ! " # $ % & ' */ + 0x0000, 0x0000, 0xa0dd, 0x0000, 0x0000, 0xa000, 0x0000, 0x00c0 /* () * + , - . / */ +}; + +/* ASCII numerals 0-9: 0x30-0x39 */ + +static const uint16_t g_slcdnummap[ASCII_COLON - ASCII_0] = +{ + 0x5f00, 0x4200, 0xf500, 0x6700, 0xea00, 0xaf00, 0xbf00, 0x4600, /* 0-7 */ + 0xff00, 0xef00 /* 8-9 */ +}; + +/* ASCII punctuation: 0x3a-0x40 */ + +static const uint16_t g_slcdpunct2[ASCII_A - ASCII_COLON] = +{ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000 /* : ; < = > ? @ */ +}; + +/* Upper case letters A-Z: 0x41-0x5a. Also lower case letters a-z: + * 0x61-0x7a + */ + +static const uint16_t g_slcdalphamap[ASCII_LBRACKET - ASCII_A] = +{ + 0xfe00, 0x6714, 0x1d00, 0x4714, 0x9d00, 0x9c00, 0x3f00, 0xfa00, /* A-H */ + 0x0014, 0x5300, 0x9841, 0x1900, 0x5a48, 0x5a09, 0x5f00, 0xfc00, /* I-P */ + 0x5f01, 0xfc01, 0xaf00, 0x0414, 0x5b00, 0x18c0, 0x5a81, 0x00c9, /* Q-X */ + 0x0058, 0x05c0 /* y-Z */ +}; + +/* ASCII punctuation: 0x5b-0x60 */ + +static const uint16_t g_slcdpunct3[ASCII_a - ASCII_LBRACKET] = +{ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000 /* [ \ ] ^ _ */ +}; + +/* ASCII punctuation: 0x7b-0x7e */ + +static const uint16_t g_slcdpunct4[ASCII_DEL - ASCII_LBRACE] = +{ + 0x0000, 0x0000, 0x0000, 0x0000 /* { | } ~ */ +}; + +/* All GPIOs that need to be configured for the STM32L-Discovery LCD */ + +static uint32_t g_slcdgpio[BOARD_SLCD_NGPIOS] = +{ + BOARD_SLCD_COM0, BOARD_SLCD_COM1, BOARD_SLCD_COM2, BOARD_SLCD_COM3, + + BOARD_SLCD_SEG0, BOARD_SLCD_SEG1, BOARD_SLCD_SEG2, BOARD_SLCD_SEG3, + BOARD_SLCD_SEG4, BOARD_SLCD_SEG5, BOARD_SLCD_SEG6, BOARD_SLCD_SEG7, + BOARD_SLCD_SEG8, BOARD_SLCD_SEG9, BOARD_SLCD_SEG10, BOARD_SLCD_SEG11, + BOARD_SLCD_SEG12, BOARD_SLCD_SEG13, BOARD_SLCD_SEG14, BOARD_SLCD_SEG15, + BOARD_SLCD_SEG16, BOARD_SLCD_SEG17, BOARD_SLCD_SEG18, BOARD_SLCD_SEG19, + BOARD_SLCD_SEG20, BOARD_SLCD_SEG21, BOARD_SLCD_SEG22, BOARD_SLCD_SEG23 +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: slcd_dumpstate + ****************************************************************************/ + +#ifdef CONFIG_DEBUG_LCD_INFO +static void slcd_dumpstate(const char *msg) +{ + lcdinfo("%s:\n", msg); + lcdinfo(" curpos: %d\n", + g_slcdstate.curpos); + lcdinfo(" Display: [%c%c%c%c%c%c]\n", + g_slcdstate.buffer[0], g_slcdstate.buffer[1], + g_slcdstate.buffer[2], g_slcdstate.buffer[3], + g_slcdstate.buffer[4], g_slcdstate.buffer[5]); + lcdinfo(" Options: [%d%d%d%d%d%d]\n", + g_slcdstate.options[0], g_slcdstate.options[1], + g_slcdstate.options[2], g_slcdstate.options[3], + g_slcdstate.options[4], g_slcdstate.options[5]); + lcdinfo(" Bar: %02x %02x\n", + g_slcdstate.bar[0], g_slcdstate.bar[1]); +} +#endif + +/**************************************************************************** + * Name: slcd_dumpslcd + ****************************************************************************/ + +#ifdef CONFIG_DEBUG_LCD_INFO +static void slcd_dumpslcd(const char *msg) +{ + lcdinfo("%s:\n", msg); + lcdinfo(" CR: %08x FCR: %08x SR: %08x CLR: %08x\n", + getreg32(STM32_LCD_CR), getreg32(STM32_LCD_FCR), + getreg32(STM32_LCD_SR), getreg32(STM32_LCD_CLR)); + lcdinfo(" RAM0L: %08x RAM1L: %08x RAM2L: %08x RAM3L: %08x\n", + getreg32(STM32_LCD_RAM0L), getreg32(STM32_LCD_RAM1L), + getreg32(STM32_LCD_RAM2L), getreg32(STM32_LCD_RAM3L)); +} +#endif + +/**************************************************************************** + * Name: slcd_clear + ****************************************************************************/ + +static void slcd_clear(void) +{ + uint32_t regaddr; + + linfo("Clearing\n"); + + /* Make sure that any previous transfer is complete. The firmware sets + * the UDR each it modifies the LCD_RAM. The UDR bit stays set until the + * end of the update. During this time the LCD_RAM is write protected. + */ + + while ((getreg32(STM32_LCD_SR) & LCD_SR_UDR) != 0); + + /* Write all zerios in to the LCD RAM */ + + for (regaddr = STM32_LCD_RAML(0); regaddr <= STM32_LCD_RAMH(7); regaddr++) + { + putreg32(0, regaddr); + } + + /* Set all buffered data to undecorated spaces and home the cursor */ + + memset(g_slcdstate.buffer, ' ', SLCD_NCHARS); + memset(g_slcdstate.options, 0, SLCD_NCHARS); + g_slcdstate.curpos = 0; + + /* Set the UDR bit to transfer the updated data to the second level + * buffer. + */ + + putreg32(1, SLCD_SR_UDR_BB); +} + +/**************************************************************************** + * Name: slcd_getcontrast + ****************************************************************************/ + +static uint8_t slcd_getcontrast(void) +{ + return (getreg32(STM32_LCD_FCR) & LCD_FCR_CC_MASK) >> LCD_FCR_CC_SHIFT; +} + +/**************************************************************************** + * Name: slcd_setcontrast + ****************************************************************************/ + +static int slcd_setcontrast(uint8_t contrast) +{ + uint32_t regval; + int ret = OK; + + /* Make sure that the contrast setting is within range */ + + if (contrast > 7) + { + contrast = 7; + ret = -ERANGE; + } + + regval = getreg32(STM32_LCD_FCR); + regval &= ~LCD_FCR_CC_MASK; + regval |= contrast << LCD_FCR_CC_SHIFT; + putreg32(regval, STM32_LCD_FCR); + + lcdinfo("contrast: %" PRId32 " FCR: %08x\n", + getreg32(STM32_LCD_FCR), contrast); + + return ret; +} + +/**************************************************************************** + * Name: slcd_writebar + ****************************************************************************/ + +static void slcd_writebar(void) +{ + uint32_t regval; + + lcdinfo("bar: %02x %02x\n", g_slcdstate.bar[0], g_slcdstate.bar[1]); + slcd_dumpslcd("BEFORE WRITE"); + + /* Make sure that any previous transfer is complete. The firmware sets + * the UDR each it modifies the LCD_RAM. The UDR bit stays set until the + * end of the update. During this time the LCD_RAM is write protected. + */ + + while ((getreg32(STM32_LCD_SR) & LCD_SR_UDR) != 0); + + /* Update the BAR */ + + regval = getreg32(STM32_LCD_RAM2L); + regval &= 0xffff5fff; + regval |= (uint32_t)(g_slcdstate.bar[0] << 12); + putreg32(regval, STM32_LCD_RAM2L); + + regval = getreg32(STM32_LCD_RAM3L); + regval &= 0xffff5fff; + regval |= (uint32_t)(g_slcdstate.bar[1] << 12); + putreg32(regval, STM32_LCD_RAM3L); + + /* Set the UDR bit to transfer the updated data to the second level + * buffer. + */ + + putreg32(1, SLCD_SR_UDR_BB); + slcd_dumpslcd("AFTER WRITE"); +} + +/**************************************************************************** + * Name: slcd_mapch + ****************************************************************************/ + +static inline uint16_t slcd_mapch(uint8_t ch) +{ + /* ASCII control characters, the forward delete character, period, colon, + * and all 8-bit ASCII character have already been handled prior to this + * function. + */ + + /* Return spaces all control characters (this should not happen) */ + + if (ch < ASCII_SPACE) + { + return 0x0000; + } + + /* Handle space and the first block of punctuation */ + + if (ch < ASCII_0) + { + return g_slcdpunct1[(int)ch - ASCII_SPACE]; + } + + /* Handle numbers */ + + else if (ch < ASCII_COLON) + { + return g_slcdnummap[(int)ch - ASCII_0]; + } + + /* Handle the next block of punctuation */ + + else if (ch < ASCII_A) + { + return g_slcdpunct2[(int)ch - ASCII_COLON]; + } + + /* Handle upper case letters */ + + else if (ch < ASCII_LBRACKET) + { + return g_slcdalphamap[(int)ch - ASCII_A]; + } + + /* Handle the next block of punctuation */ + + else if (ch < ASCII_a) + { + return g_slcdpunct3[(int)ch - ASCII_LBRACKET]; + } + + /* Handle lower case letters (by mapping them to upper case */ + + else if (ch < ASCII_LBRACE) + { + return g_slcdalphamap[(int)ch - ASCII_a]; + } + + /* Handle the final block of punctuation */ + + else if (ch < ASCII_DEL) + { + return g_slcdpunct4[(int)ch - ASCII_LBRACE]; + } + + /* Ignore 8-bit ASCII and DEL (this should not happen) */ + + return 0x0000; +} + +/**************************************************************************** + * Name: slcd_writemem + ****************************************************************************/ + +static inline void slcd_writemem(uint16_t segset, int curpos) +{ + uint8_t segments[4]; + uint32_t ram0; + uint32_t ram1; + uint32_t ram2; + uint32_t ram3; + int i; + int j; + + lcdinfo("segset: %04x curpos: %d\n", segset, curpos); + slcd_dumpslcd("BEFORE WRITE"); + + /* Isolate the least significant bits + * + * LCD character 16-bit-encoding: + * { E , D , P , N, M , C , COL , DP, B , A , K , J, G , F , Q , H } + * + * segments[0] = { E , D , P , N } + * segments[1] = { M , C , COL , DP } + * segments[2] = { B , A , K , J } + * segments[3] = { G , F , Q , H } + */ + + for (i = 12, j = 0; j < 4; i -= 4, j++) + { + segments[j] = (segset >> i) & 0x0f; + } + + lcdinfo("segments: %02x %02x %02x %02x\n", + segments[0], segments[1], segments[2], segments[3]); + + /* Make sure that any previous transfer is complete. The firmware sets + * the UDR each it modifies the LCD_RAM. The UDR bit stays set until the + * end of the update. During this time the LCD_RAM is write protected. + */ + + while ((getreg32(STM32_LCD_SR) & LCD_SR_UDR) != 0); + + /* Now update the SLCD memory for the character at this cursor position by + * decoding the bit-mapped value + */ + + ram0 = getreg32(STM32_LCD_RAM0L); + ram1 = getreg32(STM32_LCD_RAM1L); + ram2 = getreg32(STM32_LCD_RAM2L); + ram3 = getreg32(STM32_LCD_RAM3L); + + switch (curpos) + { + case 0: + ram0 &= SLCD_CHAR1_MASK0; + ram0 |= SLCD_CHAR1_UPDATE0(segments[0]); + + ram1 &= SLCD_CHAR1_MASK1; + ram1 |= SLCD_CHAR1_UPDATE1(segments[1]); + + ram2 &= SLCD_CHAR1_MASK2; + ram2 |= SLCD_CHAR1_UPDATE2(segments[2]); + + ram3 &= SLCD_CHAR1_MASK3; + ram3 |= SLCD_CHAR1_UPDATE3(segments[3]); + break; + + case 1: + ram0 &= SLCD_CHAR2_MASK0; + ram0 |= SLCD_CHAR2_UPDATE0(segments[0]); + + ram1 &= SLCD_CHAR2_MASK1; + ram1 |= SLCD_CHAR2_UPDATE1(segments[1]); + + ram2 &= SLCD_CHAR2_MASK2; + ram2 |= SLCD_CHAR2_UPDATE2(segments[2]); + + ram3 &= SLCD_CHAR2_MASK3; + ram3 |= SLCD_CHAR2_UPDATE3(segments[3]); + break; + + case 2: + ram0 &= SLCD_CHAR3_MASK0; + ram0 |= SLCD_CHAR3_UPDATE0(segments[0]); + + ram1 &= SLCD_CHAR3_MASK1; + ram1 |= SLCD_CHAR3_UPDATE1(segments[1]); + + ram2 &= SLCD_CHAR3_MASK2; + ram2 |= SLCD_CHAR3_UPDATE2(segments[2]); + + ram3 &= SLCD_CHAR3_MASK3; + ram3 |= SLCD_CHAR3_UPDATE3(segments[3]); + break; + + case 3: + ram0 &= SLCD_CHAR4_MASK0; + ram0 |= SLCD_CHAR4_UPDATE0(segments[0]); + + ram1 &= SLCD_CHAR4_MASK1; + ram1 |= SLCD_CHAR4_UPDATE1(segments[1]); + + ram2 &= SLCD_CHAR4_MASK2; + ram2 |= SLCD_CHAR4_UPDATE2(segments[2]); + + ram3 &= SLCD_CHAR4_MASK3; + ram3 |= SLCD_CHAR4_UPDATE3(segments[3]); + break; + + case 4: + ram0 &= SLCD_CHAR5_MASK0; + ram0 |= SLCD_CHAR5_UPDATE0(segments[0]); + + ram1 &= SLCD_CHAR5_MASK1; + ram1 |= SLCD_CHAR5_UPDATE1(segments[1]); + + ram2 &= SLCD_CHAR5_MASK2; + ram2 |= SLCD_CHAR5_UPDATE2(segments[2]); + + ram3 &= SLCD_CHAR5_MASK3; + ram3 |= SLCD_CHAR5_UPDATE3(segments[3]); + break; + + case 5: + ram0 &= SLCD_CHAR6_MASK0; + ram0 |= SLCD_CHAR6_UPDATE0(segments[0]); + + ram1 &= SLCD_CHAR6_MASK1; + ram1 |= SLCD_CHAR6_UPDATE1(segments[1]); + + ram2 &= SLCD_CHAR6_MASK2; + ram2 |= SLCD_CHAR6_UPDATE2(segments[2]); + + ram3 &= SLCD_CHAR6_MASK3; + ram3 |= SLCD_CHAR6_UPDATE3(segments[3]); + break; + + default: + return; + } + + putreg32(ram0, STM32_LCD_RAM0L); + putreg32(ram1, STM32_LCD_RAM1L); + putreg32(ram2, STM32_LCD_RAM2L); + putreg32(ram3, STM32_LCD_RAM3L); + + /* Set the UDR bit to transfer the updated data to the second level + * buffer. + */ + + putreg32(1, SLCD_SR_UDR_BB); + slcd_dumpslcd("AFTER WRITE"); +} + +/**************************************************************************** + * Name: slcd_writech + ****************************************************************************/ + +static void slcd_writech(uint8_t ch, uint8_t curpos, uint8_t options) +{ + uint16_t segset; + + /* Map the character code to a 16-bit encoded value */ + + segset = slcd_mapch(ch); + + /* Check if the character should be decorated with a decimal point or + * colon + */ + + if ((options & SLCD_DP) != 0) + { + segset |= 0x0002; + } + else if ((options & SLCD_COLON) != 0) + { + segset |= 0x0020; + } + + lcdinfo("ch: [%c] options: %02x segset: %04x\n", ch, options, segset); + + /* Decode the value and write it to the SLCD segment memory */ + + slcd_writemem(segset, curpos); + + /* Save these values in the state structure */ + + g_slcdstate.buffer[curpos] = ch; + g_slcdstate.options[curpos] = options; + + slcd_dumpstate("AFTER WRITE"); +} + +/**************************************************************************** + * Name: slcd_appendch + ****************************************************************************/ + +static void slcd_appendch(uint8_t ch, uint8_t options) +{ + lcdinfo("ch: [%c] options: %02x\n", ch, options); + + /* Write the character at the current cursor position */ + + slcd_writech(ch, g_slcdstate.curpos, options); + if (g_slcdstate.curpos < (SLCD_NCHARS - 1)) + { + g_slcdstate.curpos++; + } + + slcd_dumpstate("AFTER APPEND"); +} + +/**************************************************************************** + * Name: slcd_action + ****************************************************************************/ + +static void slcd_action(enum slcdcode_e code, uint8_t count) +{ + lcdinfo("Action: %d count: %d\n", code, count); + slcd_dumpstate("BEFORE ACTION"); + + switch (code) + { + /* Erasure */ + + case SLCDCODE_BACKDEL: /* Backspace (backward delete) N characters */ + { + int tmp; + + /* If we are at the home position or if the count is zero, then + * ignore the action + */ + + if (g_slcdstate.curpos < 1 || count < 1) + { + break; + } + + /* Otherwise, BACKDEL is like moving the cursor back N characters + * then doing a forward deletion. Decrement the cursor position + * and fall through. + */ + + tmp = (int)g_slcdstate.curpos - count; + if (tmp < 0) + { + tmp = 0; + count = g_slcdstate.curpos; + } + + /* Save the updated cursor positions */ + + g_slcdstate.curpos = tmp; + } + + case SLCDCODE_FWDDEL: /* DELete (forward delete) N characters moving text */ + if (count > 0) + { + int nchars; + int nmove; + int i; + + /* How many characters are to the right of the cursor position + * (including the one at the cursor position)? Then get the + * number of characters to move. + */ + + nchars = SLCD_NCHARS - g_slcdstate.curpos; + nmove = MIN(nchars, count) - 1; + + /* Move all characters after the current cursor position left + * by 'nmove' characters + */ + + for (i = g_slcdstate.curpos + nmove; i < SLCD_NCHARS - 1; i++) + { + slcd_writech(g_slcdstate.buffer[i - nmove], i, + g_slcdstate.options[i - nmove]); + } + + /* Erase the last 'nmove' characters on the display */ + + for (i = SLCD_NCHARS - nmove; i < SLCD_NCHARS; i++) + { + slcd_writech(' ', i, 0); + } + } + break; + + case SLCDCODE_ERASE: /* Erase N characters from the cursor position */ + if (count > 0) + { + int last; + int i; + + /* Get the last position to clear and make sure that the last + * position is on the SLCD. + */ + + last = g_slcdstate.curpos + count - 1; + if (last >= SLCD_NCHARS) + { + last = SLCD_NCHARS - 1; + } + + /* Erase N characters after the current cursor position left by + * one + */ + + for (i = g_slcdstate.curpos; i < last; i++) + { + slcd_writech(' ', i, 0); + } + } + break; + + case SLCDCODE_CLEAR: /* Home the cursor and erase the entire display */ + { + /* This is like HOME followed by ERASEEOL. Home the cursor and + * fall through. + */ + + g_slcdstate.curpos = 0; + } + + case SLCDCODE_ERASEEOL: /* Erase from the cursor position to the end of line */ + { + int i; + + /* Erase characters after the current cursor position to the end + * of the line + */ + + for (i = g_slcdstate.curpos; i < SLCD_NCHARS; i++) + { + slcd_writech(' ', i, 0); + } + } + break; + + /* Cursor movement */ + + case SLCDCODE_HOME: /* Cursor home */ + { + g_slcdstate.curpos = 0; + } + break; + + case SLCDCODE_END: /* Cursor end */ + { + g_slcdstate.curpos = SLCD_NCHARS - 1; + } + break; + + case SLCDCODE_LEFT: /* Cursor left by N characters */ + { + int tmp = (int)g_slcdstate.curpos - count; + + /* Don't permit movement past the beginning of the SLCD */ + + if (tmp < 0) + { + tmp = 0; + } + + /* Save the new cursor position */ + + g_slcdstate.curpos = (uint8_t)tmp; + } + break; + + case SLCDCODE_RIGHT: /* Cursor right by N characters */ + { + int tmp = (int)g_slcdstate.curpos + count; + + /* Don't permit movement past the end of the SLCD */ + + if (tmp >= SLCD_NCHARS) + { + tmp = SLCD_NCHARS - 1; + } + + /* Save the new cursor position */ + + g_slcdstate.curpos = (uint8_t)tmp; + } + break; + + case SLCDCODE_UP: /* Cursor up by N lines */ + case SLCDCODE_DOWN: /* Cursor down by N lines */ + case SLCDCODE_PAGEUP: /* Cursor up by N pages */ + case SLCDCODE_PAGEDOWN: /* Cursor down by N pages */ + break; /* Not supportable on this SLCD */ + + /* Blinking */ + + case SLCDCODE_BLINKSTART: /* Start blinking with current cursor position */ + case SLCDCODE_BLINKEND: /* End blinking after the current cursor position */ + case SLCDCODE_BLINKOFF: /* Turn blinking off */ + break; /* Not implemented */ + + /* These are actually unreportable errors */ + + default: + case SLCDCODE_NORMAL: /* Not a special keycode */ + break; + } + + slcd_dumpstate("AFTER ACTION"); +} + +/**************************************************************************** + * Name: slcd_read + ****************************************************************************/ + +static ssize_t slcd_read(struct file *filep, char *buffer, + size_t len) +{ + int ret = 0; + int i; + + /* Try to read the entire display. Notice that the seek offset + * (filep->f_pos) is ignored. It probably should be taken into account + * and also updated after each read and write. + */ + + for (i = 0; i < SLCD_NCHARS && ret < len; i++) + { + /* Return the character */ + + *buffer++ = g_slcdstate.buffer[i]; + ret++; + + /* Check if the character is decorated with a following period or + * colon + */ + + if (ret < len && g_slcdstate.buffer[i] != 0) + { + if ((g_slcdstate.buffer[i] & SLCD_DP) != 0) + { + *buffer++ = '.'; + ret++; + } + else if ((g_slcdstate.buffer[i] & SLCD_COLON) != 0) + { + *buffer++ = ':'; + ret++; + } + } + } + + slcd_dumpstate("READ"); + return ret; +} + +/**************************************************************************** + * Name: slcd_write + ****************************************************************************/ + +static ssize_t slcd_write(struct file *filep, + const char *buffer, size_t len) +{ + struct lib_meminstream_s instream; + struct slcdstate_s state; + enum slcdret_e result; + uint8_t ch; + uint8_t count; + uint8_t prev = ' '; + bool valid = false; + + /* Initialize the stream for use with the SLCD CODEC */ + + lib_meminstream(&instream, buffer, len); + + /* Prime the pump. This is messy, but necessary to handle decoration on a + * character based on any following period or colon. + */ + + memset(&state, 0, sizeof(struct slcdstate_s)); + result = slcd_decode(&instream.common, &state, &prev, &count); + + lcdinfo("slcd_decode returned result=%d char=%d count=%d\n", + result, prev, count); + + switch (result) + { + case SLCDRET_CHAR: + valid = true; + break; + + case SLCDRET_SPEC: + { + slcd_action((enum slcdcode_e)prev, count); + prev = ' '; + } + break; + + case SLCDRET_EOF: + return 0; + } + + /* Now decode and process every byte in the input buffer */ + + while ((result = slcd_decode(&instream.common, + &state, &ch, &count)) != SLCDRET_EOF) + { + lcdinfo("slcd_decode returned result=%d char=%d count=%d\n", + result, ch, count); + + if (result == SLCDRET_CHAR) /* A normal character was returned */ + { + /* Check for ASCII control characters */ + + if (ch < ASCII_SPACE) + { + /* All are ignored except for backspace and carriage return */ + + if (ch == ASCII_BS) + { + /* If there is a pending character, then output it now + * before performing the action. + */ + + if (valid) + { + slcd_appendch(prev, 0); + prev = ' '; + valid = false; + } + + /* Then perform the backward deletion */ + + slcd_action(SLCDCODE_BACKDEL, 1); + } + else if (ch == ASCII_CR) + { + /* If there is a pending character, then output it now + * before performing the action. + */ + + if (valid) + { + slcd_appendch(prev, 0); + prev = ' '; + valid = false; + } + + /* Then perform the carriage return */ + + slcd_action(SLCDCODE_HOME, 0); + } + } + + /* Handle characters decoreated with a period or a colon */ + + else if (ch == '.') + { + /* Write the previous character with the decimal point + * appended + */ + + slcd_appendch(prev, SLCD_DP); + prev = ' '; + valid = false; + } + else if (ch == ':') + { + /* Write the previous character with the colon appended */ + + slcd_appendch(prev, SLCD_COLON); + prev = ' '; + valid = false; + } + + /* Handle ASCII_DEL */ + + else if (ch == ASCII_DEL) + { + /* If there is a pending character, then output it now before + * performing the action. + */ + + if (valid) + { + slcd_appendch(prev, 0); + prev = ' '; + valid = false; + } + + /* Then perform the forward deletion */ + + slcd_action(SLCDCODE_FWDDEL, 1); + } + + /* The rest of the 7-bit ASCII characters are fair game */ + + else if (ch < 128) + { + /* Write the previous character if it valid */ + + if (valid) + { + slcd_appendch(prev, 0); + } + + /* There is now a valid output character */ + + prev = ch; + valid = true; + } + } + else /* (result == SLCDRET_SPEC) */ /* A special SLCD action was returned */ + { + /* If there is a pending character, then output it now before + * performing the action. + */ + + if (valid) + { + slcd_appendch(prev, 0); + prev = ' '; + valid = false; + } + + /* Then perform the action */ + + slcd_action((enum slcdcode_e)ch, count); + } + } + + /* Handle any unfinished output */ + + if (valid) + { + slcd_appendch(prev, 0); + } + + /* Assume that the entire input buffer was processed */ + + return (ssize_t)len; +} + +/**************************************************************************** + * Name: slcd_poll + ****************************************************************************/ + +static int slcd_ioctl(struct file *filep, int cmd, unsigned long arg) +{ + switch (cmd) + { + /* SLCDIOC_GETATTRIBUTES: Get the attributes of the SLCD + * + * argument: Pointer to struct slcd_attributes_s in which values + * will be returned + */ + + case SLCDIOC_GETATTRIBUTES: + { + struct slcd_attributes_s *attr = + (struct slcd_attributes_s *)((uintptr_t)arg); + + lcdinfo("SLCDIOC_GETATTRIBUTES:\n"); + + if (!attr) + { + return -EINVAL; + } + + attr->nrows = SLCD_NROWS; + attr->ncolumns = SLCD_NCHARS; + attr->nbars = SLCD_NBARS; + attr->maxcontrast = SLCD_MAXCONTRAST; + attr->maxbrightness = 0; + } + break; + + /* SLCDIOC_CURPOS: Get the SLCD cursor positioni (rows x characters) + * + * argument: Pointer to struct slcd_curpos_s in which values will be + * returned + */ + + case SLCDIOC_CURPOS: + { + struct slcd_curpos_s *curpos = + (struct slcd_curpos_s *)((uintptr_t)arg); + + lcdinfo("SLCDIOC_CURPOS: row=0 column=%d\n", g_slcdstate.curpos); + + if (!curpos) + { + return -EINVAL; + } + + curpos->row = 0; + curpos->column = g_slcdstate.curpos; + } + break; + + /* SLCDIOC_SETBAR: Set bars on a bar display + * + * argument: 32-bit bitset, with each bit corresponding to one bar. + */ + + case SLCDIOC_SETBAR: + { + lcdinfo("SLCDIOC_SETBAR: arg=0x%02lx\n", arg); + + /* Format the bar */ + + g_slcdstate.bar[0] = 0; + g_slcdstate.bar[1] = 0; + + if ((arg & 1) != 0) + { + SLCD_BAR0_ON; + } + + if ((arg & 2) != 0) + { + SLCD_BAR1_ON; + } + + if ((arg & 4) != 0) + { + SLCD_BAR2_ON; + } + + if ((arg & 8) != 0) + { + SLCD_BAR3_ON; + } + + /* Write the bar to SLCD memory */ + + slcd_writebar(); + } + break; + + /* SLCDIOC_GETCONTRAST: Get the current contrast setting + * + * argument: Pointer type int that will receive the current contrast + * setting + */ + + case SLCDIOC_GETCONTRAST: + { + int *contrast = (int *)((uintptr_t)arg); + if (!contrast) + { + return -EINVAL; + } + + *contrast = (int)slcd_getcontrast(); + lcdinfo("SLCDIOC_GETCONTRAST: contrast=%d\n", *contrast); + } + break; + + /* SLCDIOC_SETCONTRAST: Set the contrast to a new value + * + * argument: The new contrast value + */ + + case SLCDIOC_SETCONTRAST: + { + lcdinfo("SLCDIOC_SETCONTRAST: arg=%ld\n", arg); + + if (arg > SLCD_MAXCONTRAST) + { + return -ERANGE; + } + + return slcd_setcontrast((uint8_t)arg); + } + break; + + case SLCDIOC_GETBRIGHTNESS: /* Get the current brightness setting */ + case SLCDIOC_SETBRIGHTNESS: /* Set the brightness to a new value */ + default: + return -ENOTTY; + } + + return OK; +} + +/**************************************************************************** + * Name: slcd_poll + ****************************************************************************/ + +static int slcd_poll(struct file *filep, struct pollfd *fds, + bool setup) +{ + if (setup) + { + /* Data is always available to be read / Data can always be written */ + + poll_notify(&fds, 1, POLLIN | POLLOUT); + } + + return OK; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_slcd_initialize + * + * Description: + * Initialize the STM32L-Discovery LCD hardware and register the character + * driver as /dev/slcd0. + * + ****************************************************************************/ + +int stm32_slcd_initialize(void) +{ + uint32_t regval; + int ret = OK; + int i; + + /* Only initialize the driver once. */ + + if (!g_slcdstate.initialized) + { + lcdinfo("Initializing\n"); + + /* Configure LCD GPIO pins */ + + for (i = 0; i < BOARD_SLCD_NGPIOS; i++) + { + stm32_configgpio(g_slcdgpio[i]); + } + + /* Enable the External Low-Speed (LSE) oscillator and select it as the + * LCD clock source. + * + * NOTE: LCD clocking should already be enabled in the RCC APB1ENR + * register. + */ + + stm32_rcc_enablelse(); + + lcdinfo("APB1ENR: %08" PRIx32 " CSR: %08" PRIx32 "\n", + getreg32(STM32_RCC_APB1ENR), getreg32(STM32_RCC_CSR)); + + /* Set the LCD prescaler and divider values */ + + regval = getreg32(STM32_LCD_FCR); + regval &= ~(LCD_FCR_DIV_MASK | LCD_FCR_PS_MASK); + regval |= (LCD_FCR_PS_DIV1 | LCD_FCR_DIV(31)); + putreg32(regval, STM32_LCD_FCR); + + /* Wait for the FCRSF flag to be set */ + + lcdinfo("Wait for FCRSF, FSR: %08" PRIx32 " SR: %08" PRIx32 "\n", + getreg32(STM32_LCD_FCR), getreg32(STM32_LCD_SR)); + + while ((getreg32(STM32_LCD_SR) & LCD_SR_FCRSF) == 0); + + /* Set the duty (1/4), bias (1/3), and the internal voltage source + * (VSEL=0) + */ + + regval = getreg32(STM32_LCD_CR); + regval &= ~(LCD_CR_BIAS_MASK | LCD_CR_DUTY_MASK | LCD_CR_VSEL); + regval |= (LCD_CR_DUTY_1TO4 | LCD_CR_BIAS_1TO3); + putreg32(regval, STM32_LCD_CR); + + /* SEG[31:28] are multiplexed with SEG[43:40] */ + + regval |= LCD_CR_MUX_SEG; + putreg32(regval, STM32_LCD_CR); + + /* Set the contrast to the mean value */ + + regval = getreg32(STM32_LCD_FCR); + regval &= ~LCD_FCR_CC_MASK; + regval |= LCD_FCR_CC_VLCD(4); + putreg32(regval, STM32_LCD_FCR); + + /* No dead time */ + + regval &= ~LCD_FCR_DEAD_MASK; + putreg32(regval, STM32_LCD_FCR); + + /* Set the pulse-on duration to 4/ck_ps */ + + regval &= ~LCD_FCR_PON_MASK; + regval |= LCD_FCR_PON(4); + putreg32(regval, STM32_LCD_FCR); + + /* Wait Until the LCD FCR register is synchronized */ + + lcdinfo("Wait for FCRSF, FSR: %08" PRIx32 " SR: %08" PRIx32 "\n", + getreg32(STM32_LCD_FCR), getreg32(STM32_LCD_SR)); + + while ((getreg32(STM32_LCD_SR) & LCD_SR_FCRSF) == 0); + + /* Enable LCD peripheral */ + + putreg32(1, SLCD_CR_LCDEN_BB); + + /* Wait Until the LCD is enabled and the LCD booster is ready */ + + lcdinfo("Wait for LCD_SR_ENS and LCD_SR_RDY, " + "CR: %08" PRIx32 " SR: %08" PRIx32 "\n", + getreg32(STM32_LCD_CR), getreg32(STM32_LCD_SR)); + + while ((getreg32(STM32_LCD_SR) & (LCD_SR_ENS | LCD_SR_RDY)) != + (LCD_SR_ENS | LCD_SR_RDY)); + + /* Disable blinking */ + + regval = getreg32(STM32_LCD_FCR); + regval &= ~(LCD_FCR_BLINKF_MASK | LCD_FCR_BLINK_MASK); + regval |= (LCD_FCR_BLINK_DISABLE | LCD_FCR_BLINKF_DIV32); + putreg32(regval, STM32_LCD_FCR); + + slcd_dumpslcd("AFTER INITIALIZATION"); + + /* Register the LCD device driver */ + + ret = register_driver("/dev/slcd0", &g_slcdops, 0644, &g_slcdstate); + g_slcdstate.initialized = true; + + /* Then clear the display */ + + slcd_clear(); + slcd_dumpstate("AFTER INITIALIZATION"); + } + + return ret; +} + +#endif /* CONFIG_STM32_LCD */ diff --git a/boards/arm/stm32l1/stm32ldiscovery/src/stm32_pwm.c b/boards/arm/stm32l1/stm32ldiscovery/src/stm32_pwm.c new file mode 100644 index 0000000000000..d18d9278bddcd --- /dev/null +++ b/boards/arm/stm32l1/stm32ldiscovery/src/stm32_pwm.c @@ -0,0 +1,127 @@ +/**************************************************************************** + * boards/arm/stm32l1/stm32ldiscovery/src/stm32_pwm.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include + +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32_pwm.h" +#include "stm32ldiscovery.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* PWM + * + * The stm32ldiscovery has no real on-board PWM devices, but the board can + * be configured to output a pulse train using TIM4 CH2. + * This pin is used by FSMC is connected to CN5 just for this purpose: + * + * PD13 FSMC_A18 / MC_TIM4_CH2OUT pin 33 (EnB) + * + * FSMC must be disabled in this case! + */ + +#define HAVE_PWM 1 + +#ifndef CONFIG_PWM +# undef HAVE_PWM +#endif + +#ifndef CONFIG_STM32_TIM4 +# undef HAVE_PWM +#endif + +#ifndef CONFIG_STM32_TIM4_PWM +# undef HAVE_PWM +#endif + +#if CONFIG_STM32_TIM4_CHANNEL != STM32F3DISCOVERY_PWMCHANNEL +# undef HAVE_PWM +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_pwm_setup + * + * Description: + * Initialize PWM and register the PWM device. + * + ****************************************************************************/ + +int stm32_pwm_setup(void) +{ +#ifdef HAVE_PWM + static bool initialized = false; + struct pwm_lowerhalf_s *pwm; + int ret; + + /* Have we already initialized? */ + + if (!initialized) + { + /* Call stm32_pwminitialize() to get an instance of the PWM interface */ + + pwm = stm32_pwminitialize(STM32F3DISCOVERY_PWMTIMER); + if (!pwm) + { + _err("ERROR: Failed to get the STM32 PWM lower half\n"); + return -ENODEV; + } + + /* Register the PWM driver at "/dev/pwm0" */ + + ret = pwm_register("/dev/pwm0", pwm); + if (ret < 0) + { + aerr("ERROR: pwm_register failed: %d\n", ret); + return ret; + } + + /* Now we are initialized */ + + initialized = true; + } + + return OK; +#else + return -ENODEV; +#endif +} diff --git a/boards/arm/stm32l1/stm32ldiscovery/src/stm32_spi.c b/boards/arm/stm32l1/stm32ldiscovery/src/stm32_spi.c new file mode 100644 index 0000000000000..3066e34f1d6bb --- /dev/null +++ b/boards/arm/stm32l1/stm32ldiscovery/src/stm32_spi.c @@ -0,0 +1,182 @@ +/**************************************************************************** + * boards/arm/stm32l1/stm32ldiscovery/src/stm32_spi.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include + +#include "arm_internal.h" +#include "chip.h" +#include "stm32.h" +#include "stm32ldiscovery.h" + +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || defined(CONFIG_STM32_SPI3) + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_spidev_initialize + * + * Description: + * Called to configure SPI chip select GPIO pins for the stm32ldiscovery + * board. + * + ****************************************************************************/ + +void weak_function stm32_spidev_initialize(void) +{ +#ifdef CONFIG_STM32_SPI1 + stm32_configgpio(GPIO_MEMS_CS); /* MEMS chip select */ + stm32_configgpio(GPIO_MEMS_INT1); /* MEMS interrupts */ + stm32_configgpio(GPIO_MEMS_INT2); +#endif +} + +/**************************************************************************** + * Name: stm32_spi1/2/3select and stm32_spi1/2/3status + * + * Description: + * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status + * must be provided by board-specific logic. They are implementations of + * the select and status methods of the SPI interface defined by struct + * spi_ops_s (see include/nuttx/spi/spi.h). All other methods + * (including stm32_spibus_initialize()) are provided by common STM32 logic. + * To use this common SPI logic on your board: + * + * 1. Provide logic in stm32_boardinitialize() to configure SPI chip select + * pins. + * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() functions + * in your board-specific logic. These functions will perform chip + * selection and status operations using GPIOs in the way your board is + * configured. + * 3. Add a calls to stm32_spibus_initialize() in your low level + * application initialization logic + * 4. The handle returned by stm32_spibus_initialize() may then be used to + * bind the SPI driver to higher level logic (e.g., calling + * mmcsd_spislotinitialize(), for example, will bind the SPI driver to + * the SPI MMC/SD driver). + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_SPI1 +void stm32_spi1select(struct spi_dev_s *dev, + uint32_t devid, bool selected) +{ + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); + + stm32_gpiowrite(GPIO_MEMS_CS, !selected); +} + +uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} +#endif + +#ifdef CONFIG_STM32_SPI2 +void stm32_spi2select(struct spi_dev_s *dev, + uint32_t devid, bool selected) +{ + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); +} + +uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} +#endif + +#ifdef CONFIG_STM32_SPI3 +void stm32_spi3select(struct spi_dev_s *dev, + uint32_t devid, bool selected) +{ + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); +} + +uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} +#endif + +/**************************************************************************** + * Name: stm32_spi1cmddata + * + * Description: + * Set or clear the SH1101A A0 or SD1306 D/C n bit to select data (true) + * or command (false). This function must be provided by platform-specific + * logic. This is an implementation of the cmddata method of the SPI + * interface defined by struct spi_ops_s (see include/nuttx/spi/spi.h). + * + * Input Parameters: + * + * spi - SPI device that controls the bus the device that requires the CMD/ + * DATA selection. + * devid - If there are multiple devices on the bus, this selects which one + * to select cmd or data. NOTE: This design restricts, for example, + * one one SPI display per SPI bus. + * cmd - true: select command; false: select data + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_SPI_CMDDATA +#ifdef CONFIG_STM32_SPI1 +int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) +{ + return -ENODEV; +} +#endif + +#ifdef CONFIG_STM32_SPI2 +int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) +{ + return -ENODEV; +} +#endif + +#ifdef CONFIG_STM32_SPI3 +int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) +{ + return -ENODEV; +} +#endif +#endif /* CONFIG_SPI_CMDDATA */ + +#endif /* CONFIG_STM32_SPI1 || CONFIG_STM32_SPI2 */ diff --git a/boards/arm/stm32l1/stm32ldiscovery/src/stm32_userleds.c b/boards/arm/stm32l1/stm32ldiscovery/src/stm32_userleds.c new file mode 100644 index 0000000000000..5c6555da52100 --- /dev/null +++ b/boards/arm/stm32l1/stm32ldiscovery/src/stm32_userleds.c @@ -0,0 +1,97 @@ +/**************************************************************************** + * boards/arm/stm32l1/stm32ldiscovery/src/stm32_userleds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include + +#include "chip.h" +#include "stm32.h" +#include "stm32ldiscovery.h" + +#ifndef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_userled_initialize + ****************************************************************************/ + +uint32_t board_userled_initialize(void) +{ + /* Configure LED1-2 GPIOs for output */ + + stm32_configgpio(GPIO_LED1); + stm32_configgpio(GPIO_LED2); + return BOARD_NLEDS; +} + +/**************************************************************************** + * Name: board_userled + ****************************************************************************/ + +void board_userled(int led, bool ledon) +{ + uint32_t ledcfg; + + if (led == BOARD_LED1) + { + ledcfg = GPIO_LED1; + } + else if (led == BOARD_LED2) + { + ledcfg = GPIO_LED2; + } + else + { + return; + } + + stm32_gpiowrite(ledcfg, ledon); +} + +/**************************************************************************** + * Name: board_userled_all + ****************************************************************************/ + +void board_userled_all(uint32_t ledset) +{ + bool ledon; + + ledon = ((ledset & BOARD_LED1_BIT) != 0); + stm32_gpiowrite(GPIO_LED1, ledon); + + ledon = ((ledset & BOARD_LED2_BIT) != 0); + stm32_gpiowrite(GPIO_LED2, ledon); +} + +#endif /* !CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/stm32ldiscovery/src/stm32ldiscovery.h b/boards/arm/stm32l1/stm32ldiscovery/src/stm32ldiscovery.h similarity index 99% rename from boards/arm/stm32/stm32ldiscovery/src/stm32ldiscovery.h rename to boards/arm/stm32l1/stm32ldiscovery/src/stm32ldiscovery.h index a3ef72b726591..7f1afcb12f970 100644 --- a/boards/arm/stm32/stm32ldiscovery/src/stm32ldiscovery.h +++ b/boards/arm/stm32l1/stm32ldiscovery/src/stm32ldiscovery.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32ldiscovery/src/stm32ldiscovery.h + * boards/arm/stm32l1/stm32ldiscovery/src/stm32ldiscovery.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32l4/b-l475e-iot01a/Kconfig b/boards/arm/stm32l4/b-l475e-iot01a/Kconfig index bc12730b68138..43733a0c041cd 100644 --- a/boards/arm/stm32l4/b-l475e-iot01a/Kconfig +++ b/boards/arm/stm32l4/b-l475e-iot01a/Kconfig @@ -8,8 +8,8 @@ if ARCH_BOARD_B_L475E_IOT01A config B_L475E_IOT01A_MTD_FLASH bool "MTD driver for external 64Mbits flash memory" default n - select STM32L4_DMA1 - select STM32L4_QSPI + select STM32_DMA1 + select STM32_QSPI select MTD select MTD_MX25RXX select MTD_SMART diff --git a/boards/arm/stm32l4/b-l475e-iot01a/configs/nsh/defconfig b/boards/arm/stm32l4/b-l475e-iot01a/configs/nsh/defconfig index 7fbc7b18e1f88..39a2d9d018f1f 100644 --- a/boards/arm/stm32l4/b-l475e-iot01a/configs/nsh/defconfig +++ b/boards/arm/stm32l4/b-l475e-iot01a/configs/nsh/defconfig @@ -11,6 +11,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="b-l475e-iot01a" CONFIG_ARCH_BOARD_B_L475E_IOT01A=y CONFIG_ARCH_CHIP="stm32l4" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32L475VG=y CONFIG_ARCH_CHIP_STM32L4=y CONFIG_ARCH_STACKDUMP=y @@ -40,8 +41,8 @@ CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32L4_QSPI_FLASH_SIZE=8388608 -CONFIG_STM32L4_USART1=y +CONFIG_STM32_QSPI_FLASH_SIZE=8388608 +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_USART1_SERIAL_CONSOLE=y CONFIG_WATCHDOG=y diff --git a/boards/arm/stm32l4/b-l475e-iot01a/configs/spirit-6lowpan/defconfig b/boards/arm/stm32l4/b-l475e-iot01a/configs/spirit-6lowpan/defconfig index 180321aac4b50..3ad6b86f7b6a3 100644 --- a/boards/arm/stm32l4/b-l475e-iot01a/configs/spirit-6lowpan/defconfig +++ b/boards/arm/stm32l4/b-l475e-iot01a/configs/spirit-6lowpan/defconfig @@ -14,6 +14,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="b-l475e-iot01a" CONFIG_ARCH_BOARD_B_L475E_IOT01A=y CONFIG_ARCH_CHIP="stm32l4" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32L475VG=y CONFIG_ARCH_CHIP_STM32L4=y CONFIG_ARCH_STACKDUMP=y @@ -85,8 +86,8 @@ CONFIG_SPIRIT_NETDEV=y CONFIG_SPIRIT_PKTLEN=94 CONFIG_START_DAY=2 CONFIG_START_MONTH=8 -CONFIG_STM32L4_SPI3=y -CONFIG_STM32L4_USART1=y +CONFIG_STM32_SPI3=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_SYSTEM_TELNET_CLIENT=y CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32l4/b-l475e-iot01a/configs/spirit-starhub/defconfig b/boards/arm/stm32l4/b-l475e-iot01a/configs/spirit-starhub/defconfig index 63f9c072fd5c6..fe4ac62a657d6 100644 --- a/boards/arm/stm32l4/b-l475e-iot01a/configs/spirit-starhub/defconfig +++ b/boards/arm/stm32l4/b-l475e-iot01a/configs/spirit-starhub/defconfig @@ -14,6 +14,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="b-l475e-iot01a" CONFIG_ARCH_BOARD_B_L475E_IOT01A=y CONFIG_ARCH_CHIP="stm32l4" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32L475VG=y CONFIG_ARCH_CHIP_STM32L4=y CONFIG_ARCH_STACKDUMP=y @@ -76,8 +77,8 @@ CONFIG_SPIRIT_NETDEV=y CONFIG_SPIRIT_PKTLEN=94 CONFIG_START_DAY=2 CONFIG_START_MONTH=8 -CONFIG_STM32L4_SPI3=y -CONFIG_STM32L4_USART1=y +CONFIG_STM32_SPI3=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_SYSTEM_TELNET_CLIENT=y CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32l4/b-l475e-iot01a/configs/spirit-starpoint/defconfig b/boards/arm/stm32l4/b-l475e-iot01a/configs/spirit-starpoint/defconfig index fd31a0624c1b8..de16e10426d22 100644 --- a/boards/arm/stm32l4/b-l475e-iot01a/configs/spirit-starpoint/defconfig +++ b/boards/arm/stm32l4/b-l475e-iot01a/configs/spirit-starpoint/defconfig @@ -14,6 +14,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="b-l475e-iot01a" CONFIG_ARCH_BOARD_B_L475E_IOT01A=y CONFIG_ARCH_CHIP="stm32l4" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32L475VG=y CONFIG_ARCH_CHIP_STM32L4=y CONFIG_ARCH_STACKDUMP=y @@ -87,8 +88,8 @@ CONFIG_SPIRIT_NETDEV=y CONFIG_SPIRIT_PKTLEN=94 CONFIG_START_DAY=2 CONFIG_START_MONTH=8 -CONFIG_STM32L4_SPI3=y -CONFIG_STM32L4_USART1=y +CONFIG_STM32_SPI3=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_SYSTEM_TELNET_CLIENT=y CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32l4/b-l475e-iot01a/include/b-l475e-iot01a_clock.h b/boards/arm/stm32l4/b-l475e-iot01a/include/b-l475e-iot01a_clock.h index 3782cd800783c..508ba420e0d30 100644 --- a/boards/arm/stm32l4/b-l475e-iot01a/include/b-l475e-iot01a_clock.h +++ b/boards/arm/stm32l4/b-l475e-iot01a/include/b-l475e-iot01a_clock.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32L4_B_L475E_IOT01A_INCLUDE_B_L475E_IOT01A_CLOCK_H -#define __BOARDS_ARM_STM32L4_B_L475E_IOT01A_INCLUDE_B_L475E_IOT01A_CLOCK_H +#ifndef __BOARDS_ARM_STM32_B_L475E_IOT01A_INCLUDE_B_L475E_IOT01A_CLOCK_H +#define __BOARDS_ARM_STM32_B_L475E_IOT01A_INCLUDE_B_L475E_IOT01A_CLOCK_H /**************************************************************************** * Included Files @@ -56,20 +56,20 @@ * * System Clock source : PLL (HSI) * SYSCLK(Hz) : 80000000 Determined by PLL configuration - * HCLK(Hz) : 80000000 (STM32L4_RCC_CFGR_HPRE) + * HCLK(Hz) : 80000000 (STM32_RCC_CFGR_HPRE) * (Max 80 MHz) - * AHB Prescaler : 1 (STM32L4_RCC_CFGR_HPRE) + * AHB Prescaler : 1 (STM32_RCC_CFGR_HPRE) * (Max 80 MHz) - * APB1 Prescaler : 1 (STM32L4_RCC_CFGR_PPRE1) + * APB1 Prescaler : 1 (STM32_RCC_CFGR_PPRE1) * (Max 80 MHz) - * APB2 Prescaler : 1 (STM32L4_RCC_CFGR_PPRE2) + * APB2 Prescaler : 1 (STM32_RCC_CFGR_PPRE2) * (Max 80 MHz) * HSI Frequency(Hz) : 16000000 (nominal) - * PLLM : 1 (STM32L4_PLLCFG_PLLM) - * PLLN : 10 (STM32L4_PLLCFG_PLLN) - * PLLP : 0 (STM32L4_PLLCFG_PLLP) - * PLLQ : 0 (STM32L4_PLLCFG_PLLQ) - * PLLR : 2 (STM32L4_PLLCFG_PLLR) + * PLLM : 1 (STM32_PLLCFG_PLLM) + * PLLN : 10 (STM32_PLLCFG_PLLN) + * PLLP : 0 (STM32_PLLCFG_PLLP) + * PLLQ : 0 (STM32_PLLCFG_PLLQ) + * PLLR : 2 (STM32_PLLCFG_PLLR) * PLLSAI1N : 12 * PLLSAI1Q : 4 * Flash Latency(WS) : 4 @@ -85,13 +85,13 @@ * LSE - 32.768 kHz installed */ -#define STM32L4_HSI_FREQUENCY 16000000ul -#define STM32L4_LSI_FREQUENCY 32000 -#define STM32L4_LSE_FREQUENCY 32768 +#define STM32_HSI_FREQUENCY 16000000ul +#define STM32_LSI_FREQUENCY 32000 +#define STM32_LSE_FREQUENCY 32768 #define BOARD_AHB_FREQUENCY 80000000ul -#define STM32L4_BOARD_USEHSI 1 +#define STM32_BOARD_USEHSI 1 /* XXX sysclk mux = pllclk */ @@ -130,7 +130,7 @@ * * PLL source is HSI * - * PLL_REF = STM32L4_HSI_FREQUENCY / PLLM + * PLL_REF = STM32_HSI_FREQUENCY / PLLM * = 16,000,000 / 1 * = 16,000,000 * @@ -149,7 +149,7 @@ * * The clock input and M divider are identical to the main PLL. * However the multiplier and postscalers are independent. - * The PLLSAI1 is configured only if CONFIG_STM32L4_SAI1PLL is defined + * The PLLSAI1 is configured only if CONFIG_STM32_SAI1PLL is defined * * SAI1VCO input frequency = PLL input clock frequency * SAI1VCO output frequency = SAI1VCO input frequency × PLLSAI1N, @@ -175,7 +175,7 @@ * * The clock input and M divider are identical to the main PLL. * However the multiplier and postscalers are independent. - * The PLLSAI2 is configured only if CONFIG_STM32L4_SAI2PLL is defined + * The PLLSAI2 is configured only if CONFIG_STM32_SAI2PLL is defined * * SAI2VCO input frequency = PLL input clock frequency * SAI2VCO output frequency = SAI2VCO input frequency × PLLSAI2N, @@ -225,7 +225,7 @@ * as per comment above HSI) */ -#define STM32L4_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) /* 'main' PLL config; we use this to generate our system clock via the R * output. We set it up as 16 MHz / 1 * 10 / 2 = 80 MHz @@ -235,13 +235,13 @@ * applications may want things done this way. */ -#define STM32L4_PLLCFG_PLLN RCC_PLLCFG_PLLN(10) -#define STM32L4_PLLCFG_PLLP 0 -#undef STM32L4_PLLCFG_PLLP_ENABLED -#define STM32L4_PLLCFG_PLLQ RCC_PLLCFG_PLLQ_2 -#define STM32L4_PLLCFG_PLLQ_ENABLED -#define STM32L4_PLLCFG_PLLR RCC_PLLCFG_PLLR(2) -#define STM32L4_PLLCFG_PLLR_ENABLED +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(10) +#define STM32_PLLCFG_PLLP 0 +#undef STM32_PLLCFG_PLLP_ENABLED +#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ_2 +#define STM32_PLLCFG_PLLQ_ENABLED +#define STM32_PLLCFG_PLLR RCC_PLLCFG_PLLR(2) +#define STM32_PLLCFG_PLLR_ENABLED /* 'SAIPLL1' is used to generate the 48 MHz clock, since we can't * do that with the main PLL's N value. We set N = 12, and enable @@ -255,72 +255,72 @@ * that is selected via a #define here, like all these other params. */ -#define STM32L4_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(12) -#define STM32L4_PLLSAI1CFG_PLLP 0 -#undef STM32L4_PLLSAI1CFG_PLLP_ENABLED -#define STM32L4_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_4 -#define STM32L4_PLLSAI1CFG_PLLQ_ENABLED -#define STM32L4_PLLSAI1CFG_PLLR 0 -#undef STM32L4_PLLSAI1CFG_PLLR_ENABLED +#define STM32_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(12) +#define STM32_PLLSAI1CFG_PLLP 0 +#undef STM32_PLLSAI1CFG_PLLP_ENABLED +#define STM32_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_4 +#define STM32_PLLSAI1CFG_PLLQ_ENABLED +#define STM32_PLLSAI1CFG_PLLR 0 +#undef STM32_PLLSAI1CFG_PLLR_ENABLED /* 'SAIPLL2' is not used in this application */ -#define STM32L4_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) -#define STM32L4_PLLSAI2CFG_PLLP 0 -#undef STM32L4_PLLSAI2CFG_PLLP_ENABLED -#define STM32L4_PLLSAI2CFG_PLLR 0 -#undef STM32L4_PLLSAI2CFG_PLLR_ENABLED +#define STM32_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) +#define STM32_PLLSAI2CFG_PLLP 0 +#undef STM32_PLLSAI2CFG_PLLP_ENABLED +#define STM32_PLLSAI2CFG_PLLR 0 +#undef STM32_PLLSAI2CFG_PLLR_ENABLED -#define STM32L4_SYSCLK_FREQUENCY 80000000ul +#define STM32_SYSCLK_FREQUENCY 80000000ul /* CLK48 will come from PLLSAI1 (implicitly Q) */ -#define STM32L4_USE_CLK48 -#define STM32L4_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 +#define STM32_USE_CLK48 +#define STM32_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 /* enable the LSE oscillator, used automatically trim the MSI, and for RTC */ -#define STM32L4_USE_LSE 1 +#define STM32_USE_LSE 1 /* AHB clock (HCLK) is SYSCLK (80MHz) */ -#define STM32L4_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ -#define STM32L4_HCLK_FREQUENCY STM32L4_SYSCLK_FREQUENCY +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY /* APB1 clock (PCLK1) is HCLK/1 (80MHz) */ -#define STM32L4_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ -#define STM32L4_PCLK1_FREQUENCY (STM32L4_HCLK_FREQUENCY / 1) +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY / 1) /* Timers driven from APB1 will be twice PCLK1, when - * NOT define STM32L4_RCC_CFGR_PPRE1 as RCC_CFGR_PPRE1_HCLK. + * NOT define STM32_RCC_CFGR_PPRE1 as RCC_CFGR_PPRE1_HCLK. */ /* REVISIT : this can be configured */ -#define STM32L4_APB1_TIM2_CLKIN STM32L4_PCLK1_FREQUENCY -#define STM32L4_APB1_TIM3_CLKIN STM32L4_PCLK1_FREQUENCY -#define STM32L4_APB1_TIM4_CLKIN STM32L4_PCLK1_FREQUENCY -#define STM32L4_APB1_TIM5_CLKIN STM32L4_PCLK1_FREQUENCY -#define STM32L4_APB1_TIM6_CLKIN STM32L4_PCLK1_FREQUENCY -#define STM32L4_APB1_TIM7_CLKIN STM32L4_PCLK1_FREQUENCY -#define STM32L4_APB1_LPTIM1_CLKIN STM32L4_PCLK1_FREQUENCY -#define STM32L4_APB1_LPTIM2_CLKIN STM32L4_PCLK1_FREQUENCY +#define STM32_APB1_TIM2_CLKIN STM32_PCLK1_FREQUENCY +#define STM32_APB1_TIM3_CLKIN STM32_PCLK1_FREQUENCY +#define STM32_APB1_TIM4_CLKIN STM32_PCLK1_FREQUENCY +#define STM32_APB1_TIM5_CLKIN STM32_PCLK1_FREQUENCY +#define STM32_APB1_TIM6_CLKIN STM32_PCLK1_FREQUENCY +#define STM32_APB1_TIM7_CLKIN STM32_PCLK1_FREQUENCY +#define STM32_APB1_LPTIM1_CLKIN STM32_PCLK1_FREQUENCY +#define STM32_APB1_LPTIM2_CLKIN STM32_PCLK1_FREQUENCY /* APB2 clock (PCLK2) is HCLK (80MHz) */ -#define STM32L4_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ -#define STM32L4_PCLK2_FREQUENCY (STM32L4_HCLK_FREQUENCY / 1) +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ +#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY / 1) /* Timers driven from APB2 will be twice PCLK2 */ /* REVISIT : this can be configured */ -#define STM32L4_APB2_TIM1_CLKIN STM32L4_PCLK2_FREQUENCY -#define STM32L4_APB2_TIM8_CLKIN STM32L4_PCLK2_FREQUENCY -#define STM32L4_APB2_TIM15_CLKIN STM32L4_PCLK2_FREQUENCY -#define STM32L4_APB2_TIM16_CLKIN STM32L4_PCLK2_FREQUENCY -#define STM32L4_APB2_TIM17_CLKIN STM32L4_PCLK2_FREQUENCY +#define STM32_APB2_TIM1_CLKIN STM32_PCLK2_FREQUENCY +#define STM32_APB2_TIM8_CLKIN STM32_PCLK2_FREQUENCY +#define STM32_APB2_TIM15_CLKIN STM32_PCLK2_FREQUENCY +#define STM32_APB2_TIM16_CLKIN STM32_PCLK2_FREQUENCY +#define STM32_APB2_TIM17_CLKIN STM32_PCLK2_FREQUENCY /* Timer Frequencies, if APBx is set to 1, frequency is same to APBx * otherwise frequency is 2xAPBx. @@ -335,7 +335,7 @@ /* Use the HSE */ -#define STM32L4_BOARD_USEHSE 1 +#define STM32_BOARD_USEHSE 1 /* XXX sysclk mux = pllclk */ @@ -343,78 +343,78 @@ /* Prescaler common to all PLL inputs */ -#define STM32L4_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) /* 'main' PLL config; we use this to generate our system clock */ -#define STM32L4_PLLCFG_PLLN RCC_PLLCFG_PLLN(20) -#define STM32L4_PLLCFG_PLLP 0 -#undef STM32L4_PLLCFG_PLLP_ENABLED -#define STM32L4_PLLCFG_PLLQ 0 -#undef STM32L4_PLLCFG_PLLQ_ENABLED -#define STM32L4_PLLCFG_PLLR RCC_PLLCFG_PLLR_2 -#define STM32L4_PLLCFG_PLLR_ENABLED +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(20) +#define STM32_PLLCFG_PLLP 0 +#undef STM32_PLLCFG_PLLP_ENABLED +#define STM32_PLLCFG_PLLQ 0 +#undef STM32_PLLCFG_PLLQ_ENABLED +#define STM32_PLLCFG_PLLR RCC_PLLCFG_PLLR_2 +#define STM32_PLLCFG_PLLR_ENABLED /* 'SAIPLL1' is used to generate the 48 MHz clock */ -#define STM32L4_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(12) -#define STM32L4_PLLSAI1CFG_PLLP 0 -#undef STM32L4_PLLSAI1CFG_PLLP_ENABLED -#define STM32L4_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_2 -#define STM32L4_PLLSAI1CFG_PLLQ_ENABLED -#define STM32L4_PLLSAI1CFG_PLLR 0 -#undef STM32L4_PLLSAI1CFG_PLLR_ENABLED +#define STM32_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(12) +#define STM32_PLLSAI1CFG_PLLP 0 +#undef STM32_PLLSAI1CFG_PLLP_ENABLED +#define STM32_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_2 +#define STM32_PLLSAI1CFG_PLLQ_ENABLED +#define STM32_PLLSAI1CFG_PLLR 0 +#undef STM32_PLLSAI1CFG_PLLR_ENABLED /* 'SAIPLL2' is not used in this application */ -#define STM32L4_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) -#define STM32L4_PLLSAI2CFG_PLLP 0 -#undef STM32L4_PLLSAI2CFG_PLLP_ENABLED -#define STM32L4_PLLSAI2CFG_PLLR 0 -#undef STM32L4_PLLSAI2CFG_PLLR_ENABLED +#define STM32_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) +#define STM32_PLLSAI2CFG_PLLP 0 +#undef STM32_PLLSAI2CFG_PLLP_ENABLED +#define STM32_PLLSAI2CFG_PLLR 0 +#undef STM32_PLLSAI2CFG_PLLR_ENABLED -#define STM32L4_SYSCLK_FREQUENCY 80000000ul +#define STM32_SYSCLK_FREQUENCY 80000000ul /* Enable CLK48; get it from PLLSAI1 */ -#define STM32L4_USE_CLK48 -#define STM32L4_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 +#define STM32_USE_CLK48 +#define STM32_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 /* Enable LSE (for the RTC) */ -#define STM32L4_USE_LSE 1 +#define STM32_USE_LSE 1 /* Configure the HCLK divisor (for the AHB bus, core, memory, and DMA */ -#define STM32L4_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ -#define STM32L4_HCLK_FREQUENCY STM32L4_SYSCLK_FREQUENCY +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY /* Configure the APB1 prescaler */ -#define STM32L4_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ -#define STM32L4_PCLK1_FREQUENCY (STM32L4_HCLK_FREQUENCY/1) +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/1) -#define STM32L4_APB1_TIM2_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM3_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM4_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM5_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM6_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM7_CLKIN (2*STM32L4_PCLK1_FREQUENCY) +#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) /* Configure the APB2 prescaler */ -#define STM32L4_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ -#define STM32L4_PCLK2_FREQUENCY (STM32L4_HCLK_FREQUENCY/1) +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ +#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/1) -#define STM32L4_APB2_TIM1_CLKIN (2*STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM8_CLKIN (2*STM32L4_PCLK2_FREQUENCY) +#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) #elif defined(MSI_CLOCK_CONFIG) /* Use the MSI; frequ = 4 MHz; autotrim from LSE */ -#define STM32L4_BOARD_USEMSI 1 -#define STM32L4_BOARD_MSIRANGE RCC_CR_MSIRANGE_4M +#define STM32_BOARD_USEMSI 1 +#define STM32_BOARD_MSIRANGE RCC_CR_MSIRANGE_4M /* XXX sysclk mux = pllclk */ @@ -422,71 +422,71 @@ /* prescaler common to all PLL inputs */ -#define STM32L4_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) /* 'main' PLL config; we use this to generate our system clock */ -#define STM32L4_PLLCFG_PLLN RCC_PLLCFG_PLLN(40) -#define STM32L4_PLLCFG_PLLP 0 -#undef STM32L4_PLLCFG_PLLP_ENABLED -#define STM32L4_PLLCFG_PLLQ 0 -#undef STM32L4_PLLCFG_PLLQ_ENABLED -#define STM32L4_PLLCFG_PLLR RCC_PLLCFG_PLLR_2 -#define STM32L4_PLLCFG_PLLR_ENABLED +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(40) +#define STM32_PLLCFG_PLLP 0 +#undef STM32_PLLCFG_PLLP_ENABLED +#define STM32_PLLCFG_PLLQ 0 +#undef STM32_PLLCFG_PLLQ_ENABLED +#define STM32_PLLCFG_PLLR RCC_PLLCFG_PLLR_2 +#define STM32_PLLCFG_PLLR_ENABLED /* 'SAIPLL1' is used to generate the 48 MHz clock */ -#define STM32L4_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(24) -#define STM32L4_PLLSAI1CFG_PLLP 0 -#undef STM32L4_PLLSAI1CFG_PLLP_ENABLED -#define STM32L4_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_2 -#define STM32L4_PLLSAI1CFG_PLLQ_ENABLED -#define STM32L4_PLLSAI1CFG_PLLR 0 -#undef STM32L4_PLLSAI1CFG_PLLR_ENABLED +#define STM32_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(24) +#define STM32_PLLSAI1CFG_PLLP 0 +#undef STM32_PLLSAI1CFG_PLLP_ENABLED +#define STM32_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_2 +#define STM32_PLLSAI1CFG_PLLQ_ENABLED +#define STM32_PLLSAI1CFG_PLLR 0 +#undef STM32_PLLSAI1CFG_PLLR_ENABLED /* 'SAIPLL2' is not used in this application */ -#define STM32L4_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) -#define STM32L4_PLLSAI2CFG_PLLP 0 -#undef STM32L4_PLLSAI2CFG_PLLP_ENABLED -#define STM32L4_PLLSAI2CFG_PLLR 0 -#undef STM32L4_PLLSAI2CFG_PLLR_ENABLED +#define STM32_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) +#define STM32_PLLSAI2CFG_PLLP 0 +#undef STM32_PLLSAI2CFG_PLLP_ENABLED +#define STM32_PLLSAI2CFG_PLLR 0 +#undef STM32_PLLSAI2CFG_PLLR_ENABLED -#define STM32L4_SYSCLK_FREQUENCY 80000000ul +#define STM32_SYSCLK_FREQUENCY 80000000ul /* Enable CLK48; get it from PLLSAI1 */ -#define STM32L4_USE_CLK48 -#define STM32L4_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 +#define STM32_USE_CLK48 +#define STM32_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 /* Enable LSE (for the RTC) */ -#define STM32L4_USE_LSE 1 +#define STM32_USE_LSE 1 /* Configure the HCLK divisor (for the AHB bus, core, memory, and DMA */ -#define STM32L4_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ -#define STM32L4_HCLK_FREQUENCY STM32L4_SYSCLK_FREQUENCY +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY /* Configure the APB1 prescaler */ -#define STM32L4_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ -#define STM32L4_PCLK1_FREQUENCY (STM32L4_HCLK_FREQUENCY/1) +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/1) -#define STM32L4_APB1_TIM2_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM3_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM4_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM5_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM6_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM7_CLKIN (2*STM32L4_PCLK1_FREQUENCY) +#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) /* Configure the APB2 prescaler */ -#define STM32L4_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ -#define STM32L4_PCLK2_FREQUENCY (STM32L4_HCLK_FREQUENCY/1) +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ +#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/1) -#define STM32L4_APB2_TIM1_CLKIN (2*STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM8_CLKIN (2*STM32L4_PCLK2_FREQUENCY) +#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) #endif @@ -495,19 +495,19 @@ * Note: TIM1,8,15,16,17 are on APB2, others on APB1 */ -#define BOARD_TIM1_FREQUENCY STM32L4_APB2_TIM1_CLKIN -#define BOARD_TIM2_FREQUENCY STM32L4_APB1_TIM2_CLKIN -#define BOARD_TIM3_FREQUENCY STM32L4_APB1_TIM3_CLKIN -#define BOARD_TIM4_FREQUENCY STM32L4_APB1_TIM4_CLKIN -#define BOARD_TIM5_FREQUENCY STM32L4_APB1_TIM5_CLKIN -#define BOARD_TIM6_FREQUENCY STM32L4_APB1_TIM6_CLKIN -#define BOARD_TIM7_FREQUENCY STM32L4_APB1_TIM7_CLKIN -#define BOARD_TIM8_FREQUENCY STM32L4_APB2_TIM8_CLKIN -#define BOARD_TIM15_FREQUENCY STM32L4_APB2_TIM15_CLKIN -#define BOARD_TIM16_FREQUENCY STM32L4_APB2_TIM16_CLKIN -#define BOARD_TIM17_FREQUENCY STM32L4_APB2_TIM17_CLKIN -#define BOARD_LPTIM1_FREQUENCY STM32L4_APB1_LPTIM1_CLKIN -#define BOARD_LPTIM2_FREQUENCY STM32L4_APB1_LPTIM2_CLKIN +#define BOARD_TIM1_FREQUENCY STM32_APB2_TIM1_CLKIN +#define BOARD_TIM2_FREQUENCY STM32_APB1_TIM2_CLKIN +#define BOARD_TIM3_FREQUENCY STM32_APB1_TIM3_CLKIN +#define BOARD_TIM4_FREQUENCY STM32_APB1_TIM4_CLKIN +#define BOARD_TIM5_FREQUENCY STM32_APB1_TIM5_CLKIN +#define BOARD_TIM6_FREQUENCY STM32_APB1_TIM6_CLKIN +#define BOARD_TIM7_FREQUENCY STM32_APB1_TIM7_CLKIN +#define BOARD_TIM8_FREQUENCY STM32_APB2_TIM8_CLKIN +#define BOARD_TIM15_FREQUENCY STM32_APB2_TIM15_CLKIN +#define BOARD_TIM16_FREQUENCY STM32_APB2_TIM16_CLKIN +#define BOARD_TIM17_FREQUENCY STM32_APB2_TIM17_CLKIN +#define BOARD_LPTIM1_FREQUENCY STM32_APB1_LPTIM1_CLKIN +#define BOARD_LPTIM2_FREQUENCY STM32_APB1_LPTIM2_CLKIN /**************************************************************************** * Public Data @@ -534,4 +534,4 @@ extern "C" #endif #endif /* __ASSEMBLY__ */ -#endif /* __BOARDS_ARMSTM32L4__B_L475E_IOT01A_INCLUDE_B_L475E_IOT01A_CLOCK */ +#endif /* __BOARDS_ARMSTM32__B_L475E_IOT01A_INCLUDE_B_L475E_IOT01A_CLOCK */ diff --git a/boards/arm/stm32l4/b-l475e-iot01a/include/board.h b/boards/arm/stm32l4/b-l475e-iot01a/include/board.h index c9873219a21fb..57863fae794cd 100644 --- a/boards/arm/stm32l4/b-l475e-iot01a/include/board.h +++ b/boards/arm/stm32l4/b-l475e-iot01a/include/board.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32L4_B_L475E_IOT01A_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32L4_B_L475E_IOT01A_INCLUDE_BOARD_H +#ifndef __BOARDS_ARM_STM32_B_L475E_IOT01A_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32_B_L475E_IOT01A_INCLUDE_BOARD_H /**************************************************************************** * Included Files @@ -188,4 +188,4 @@ extern "C" #endif #endif /* __ASSEMBLY__ */ -#endif /* __BOARDS_ARM_STM32L4_B_L475E_IOT01A_INCLUDE_BOARD_H */ +#endif /* __BOARDS_ARM_STM32_B_L475E_IOT01A_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32l4/b-l475e-iot01a/src/Make.defs b/boards/arm/stm32l4/b-l475e-iot01a/src/Make.defs new file mode 100644 index 0000000000000..f9a89b4acba9c --- /dev/null +++ b/boards/arm/stm32l4/b-l475e-iot01a/src/Make.defs @@ -0,0 +1,39 @@ +############################################################################ +# boards/arm/stm32l4/b-l475e-iot01a/src/Makefile +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +CSRCS = stm32_boot.c stm32_bringup.c stm32_spi.c stm32_timer.c + +ifeq ($(CONFIG_ARCH_LEDS),y) +CSRCS += stm32_autoleds.c +else +CSRCS += stm32_userleds.c +endif + +ifeq ($(CONFIG_SPIRIT_NETDEV),y) +CSRCS += stm32_spirit.c +endif + +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32l4/b-l475e-iot01a/src/Makefile b/boards/arm/stm32l4/b-l475e-iot01a/src/Makefile deleted file mode 100644 index 4b6dba43ad15b..0000000000000 --- a/boards/arm/stm32l4/b-l475e-iot01a/src/Makefile +++ /dev/null @@ -1,37 +0,0 @@ -############################################################################ -# boards/arm/stm32l4/b-l475e-iot01a/src/Makefile -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/Make.defs - -CSRCS = stm32_boot.c stm32_bringup.c stm32_spi.c stm32_timer.c - -ifeq ($(CONFIG_ARCH_LEDS),y) -CSRCS += stm32_autoleds.c -else -CSRCS += stm32_userleds.c -endif - -ifeq ($(CONFIG_SPIRIT_NETDEV),y) -CSRCS += stm32_spirit.c -endif - -include $(TOPDIR)/boards/Board.mk diff --git a/boards/arm/stm32l4/b-l475e-iot01a/src/b-l475e-iot01a.h b/boards/arm/stm32l4/b-l475e-iot01a/src/b-l475e-iot01a.h index 831f891cc5ae0..c18d2e1e4d3e1 100644 --- a/boards/arm/stm32l4/b-l475e-iot01a/src/b-l475e-iot01a.h +++ b/boards/arm/stm32l4/b-l475e-iot01a/src/b-l475e-iot01a.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32L4_B_L475E_IOT01A_SRC_B_L475E_IOT01A_H -#define __BOARDS_ARM_STM32L4_B_L475E_IOT01A_SRC_B_L475E_IOT01A_H +#ifndef __BOARDS_ARM_STM32_B_L475E_IOT01A_SRC_B_L475E_IOT01A_H +#define __BOARDS_ARM_STM32_B_L475E_IOT01A_SRC_B_L475E_IOT01A_H /**************************************************************************** * Included Files @@ -46,7 +46,7 @@ /* SPSGRF support depends on: * - * CONFIG_STM32L4_SPI3 - SPI3 support + * CONFIG_STM32_SPI3 - SPI3 support * CONFIG_WL_SPIRIT - Spirit wireless library * CONFIG_SPIRIT_NETDEV - Spirit network driver * CONFIG_SCHED_HPWORK - HP work queue support @@ -57,7 +57,7 @@ * And probably a few other things. */ -#if !defined(CONFIG_STM32L4_SPI3) +#if !defined(CONFIG_STM32_SPI3) # undef HAVE_SPSGRF #endif @@ -73,7 +73,7 @@ # undef HAVE_SPSGRF #endif -#if !defined(CONFIG_MTD_MX25RXX) || !defined(CONFIG_STM32L4_QSPI) +#if !defined(CONFIG_MTD_MX25RXX) || !defined(CONFIG_STM32_QSPI) # undef HAVE_MX25R6435F #endif @@ -133,7 +133,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_bringup + * Name: stm32_bringup * * Description: * This function initializes and configures all on-board features @@ -142,11 +142,11 @@ ****************************************************************************/ #if defined(CONFIG_BOARDCTL) || defined(CONFIG_BOARD_LATE_INITIALIZE) -int stm32l4_bringup(void); +int stm32_bringup(void); #endif /**************************************************************************** - * Name: stm32l4_spidev_initialize + * Name: stm32_spidev_initialize * * Description: * Called to configure SPI chip select GPIO pins for the Nucleo-F401RE and @@ -154,9 +154,9 @@ int stm32l4_bringup(void); * ****************************************************************************/ -#if defined(CONFIG_STM32L4_SPI1) || defined(CONFIG_STM32L4_SPI2) || \ - defined(CONFIG_STM32L4_SPI3) -void weak_function stm32l4_spidev_initialize(void); +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || \ + defined(CONFIG_STM32_SPI3) +void weak_function stm32_spidev_initialize(void); #endif /**************************************************************************** @@ -175,11 +175,11 @@ void weak_function stm32l4_spidev_initialize(void); ****************************************************************************/ #ifdef CONFIG_TIMER -int stm32l4_timer_driver_setup(void); +int stm32_timer_driver_setup(void); #endif /**************************************************************************** - * Name: stm32l4_spirit_initialize + * Name: stm32_spirit_initialize * * Description: * Initialize the Spirit device. @@ -191,8 +191,8 @@ int stm32l4_timer_driver_setup(void); ****************************************************************************/ #ifdef HAVE_SPSGRF -int stm32l4_spirit_initialize(void); +int stm32_spirit_initialize(void); #endif #endif /* __ASSEMBLY__ */ -#endif /* __BOARDS_ARM_STM32L4_B_L475E_IOT01A_SRC_B_L475E_IOT01A_H */ +#endif /* __BOARDS_ARM_STM32_B_L475E_IOT01A_SRC_B_L475E_IOT01A_H */ diff --git a/boards/arm/stm32l4/b-l475e-iot01a/src/stm32_autoleds.c b/boards/arm/stm32l4/b-l475e-iot01a/src/stm32_autoleds.c index 065c7aca0d09b..269354efbc1fa 100644 --- a/boards/arm/stm32l4/b-l475e-iot01a/src/stm32_autoleds.c +++ b/boards/arm/stm32l4/b-l475e-iot01a/src/stm32_autoleds.c @@ -73,7 +73,7 @@ void board_autoled_initialize(void) { /* Configure LED gpio as output */ - stm32l4_configgpio(GPIO_LED2); + stm32_configgpio(GPIO_LED2); } /**************************************************************************** @@ -84,7 +84,7 @@ void board_autoled_on(int led) { if (led == 1 || led == 3) { - stm32l4_gpiowrite(GPIO_LED2, true); + stm32_gpiowrite(GPIO_LED2, true); } } @@ -96,7 +96,7 @@ void board_autoled_off(int led) { if (led == 3) { - stm32l4_gpiowrite(GPIO_LED2, false); + stm32_gpiowrite(GPIO_LED2, false); } } diff --git a/boards/arm/stm32l4/b-l475e-iot01a/src/stm32_boot.c b/boards/arm/stm32l4/b-l475e-iot01a/src/stm32_boot.c index 27bca5f9baec8..550eb357b23e2 100644 --- a/boards/arm/stm32l4/b-l475e-iot01a/src/stm32_boot.c +++ b/boards/arm/stm32l4/b-l475e-iot01a/src/stm32_boot.c @@ -38,7 +38,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_board_initialize + * Name: stm32_board_initialize * * Description: * All STM32L4 architectures must provide the following entry point. This @@ -48,17 +48,17 @@ * ****************************************************************************/ -void stm32l4_board_initialize(void) +void stm32_board_initialize(void) { -#if defined(CONFIG_STM32L4_SPI1) || defined(CONFIG_STM32L4_SPI2) || defined(CONFIG_STM32L4_SPI3) +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || defined(CONFIG_STM32_SPI3) /* Configure SPI chip selects if * 1) SPI is not disabled, and 2) the weak function - * stm32l4_spidev_initialize() has been brought into the link. + * stm32_spidev_initialize() has been brought into the link. */ - if (stm32l4_spidev_initialize) + if (stm32_spidev_initialize) { - stm32l4_spidev_initialize(); + stm32_spidev_initialize(); } #endif @@ -88,6 +88,6 @@ void board_late_initialize(void) { /* Perform board initialization */ - stm32l4_bringup(); + stm32_bringup(); } #endif /* CONFIG_BOARD_LATE_INITIALIZE */ diff --git a/boards/arm/stm32l4/b-l475e-iot01a/src/stm32_bringup.c b/boards/arm/stm32l4/b-l475e-iot01a/src/stm32_bringup.c index cdbb58f24fbeb..838b4349ff675 100644 --- a/boards/arm/stm32l4/b-l475e-iot01a/src/stm32_bringup.c +++ b/boards/arm/stm32l4/b-l475e-iot01a/src/stm32_bringup.c @@ -49,7 +49,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_bringup + * Name: stm32_bringup * * Description: * This function initializes and configures all on-board features @@ -57,7 +57,7 @@ * ****************************************************************************/ -int stm32l4_bringup(void) +int stm32_bringup(void) { int ret = OK; @@ -95,10 +95,10 @@ int stm32l4_bringup(void) struct qspi_dev_s *g_qspi; struct mtd_dev_s *g_mtd_fs; - g_qspi = stm32l4_qspi_initialize(0); + g_qspi = stm32_qspi_initialize(0); if (g_qspi == NULL) { - syslog(LOG_ERR, "ERROR: stm32l4_qspi_initialize failed\n"); + syslog(LOG_ERR, "ERROR: stm32_qspi_initialize failed\n"); return -EIO; } @@ -222,10 +222,10 @@ int stm32l4_bringup(void) #ifdef HAVE_SPSGRF /* Configure Spirit/SPSGRF wireless */ - ret = stm32l4_spirit_initialize(); + ret = stm32_spirit_initialize(); if (ret < 0) { - syslog(LOG_ERR, "ERROR: stm32l4_spirit_initialize() failed: %d\n", + syslog(LOG_ERR, "ERROR: stm32_spirit_initialize() failed: %d\n", ret); } #endif @@ -233,7 +233,7 @@ int stm32l4_bringup(void) #ifdef CONFIG_TIMER /* Register timer drivers */ - ret = stm32l4_timer_driver_setup(); + ret = stm32_timer_driver_setup(); if (ret < 0) { syslog(LOG_ERR, "ERROR: Failed to setup TIM1 at /dev/timer0: %d\n", diff --git a/boards/arm/stm32l4/b-l475e-iot01a/src/stm32_spi.c b/boards/arm/stm32l4/b-l475e-iot01a/src/stm32_spi.c index d3a2d3b320ed4..dac9cc457eab1 100644 --- a/boards/arm/stm32l4/b-l475e-iot01a/src/stm32_spi.c +++ b/boards/arm/stm32l4/b-l475e-iot01a/src/stm32_spi.c @@ -45,16 +45,16 @@ /* Currently no devices are defined on SPI1 or SPI2 */ -#undef CONFIG_STM32L4_SPI1 -#undef CONFIG_STM32L4_SPI2 +#undef CONFIG_STM32_SPI1 +#undef CONFIG_STM32_SPI2 /* Only the SPSGRF is currently supported on SPI3 */ #ifndef HAVE_SPSGRF -# undef CONFIG_STM32L4_SPI3 +# undef CONFIG_STM32_SPI3 #endif -#if defined(CONFIG_STM32L4_SPI1) || defined(CONFIG_STM32L4_SPI2) || defined(CONFIG_STM32L4_SPI3) +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || defined(CONFIG_STM32_SPI3) /**************************************************************************** * Public Data @@ -62,15 +62,15 @@ /* Global driver instances */ -#ifdef CONFIG_STM32L4_SPI1 +#ifdef CONFIG_STM32_SPI1 struct spi_dev_s *g_spi1; #endif -#ifdef CONFIG_STM32L4_SPI2 +#ifdef CONFIG_STM32_SPI2 struct spi_dev_s *g_spi2; #endif -#ifdef CONFIG_STM32L4_SPI3 +#ifdef CONFIG_STM32_SPI3 struct spi_dev_s *g_spi3; #endif @@ -79,7 +79,7 @@ struct spi_dev_s *g_spi3; ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_spidev_initialize + * Name: stm32_spidev_initialize * * Description: * Called to configure SPI chip select GPIO pins for the Nucleo-F401RE and @@ -87,12 +87,12 @@ struct spi_dev_s *g_spi3; * ****************************************************************************/ -void weak_function stm32l4_spidev_initialize(void) +void weak_function stm32_spidev_initialize(void) { -#ifdef CONFIG_STM32L4_SPI1 +#ifdef CONFIG_STM32_SPI1 /* Configure SPI-based devices */ - g_spi1 = stm32l4_spibus_initialize(1); + g_spi1 = stm32_spibus_initialize(1); if (!g_spi1) { spierr("ERROR: [boot] FAILED to initialize SPI port 1\n"); @@ -101,41 +101,41 @@ void weak_function stm32l4_spidev_initialize(void) /* Configure chip select GPIOs */ #endif -#ifdef CONFIG_STM32L4_SPI2 +#ifdef CONFIG_STM32_SPI2 /* Configure SPI-based devices */ - g_spi2 = stm32l4_spibus_initialize(2); + g_spi2 = stm32_spibus_initialize(2); /* Configure chip select GPIOs */ #endif -#ifdef CONFIG_STM32L4_SPI3 +#ifdef CONFIG_STM32_SPI3 /* Configure SPI-based devices */ - g_spi3 = stm32l4_spibus_initialize(3); + g_spi3 = stm32_spibus_initialize(3); /* Configure chip select GPIOs */ #ifdef HAVE_SPSGRF - stm32l4_configgpio(GPIO_SPSGRF_CS); + stm32_configgpio(GPIO_SPSGRF_CS); #endif #endif } /**************************************************************************** - * Name: stm32l4_spi1/2/3select and stm32l4_spi1/2/3status + * Name: stm32_spi1/2/3select and stm32_spi1/2/3status * * Description: - * The external functions, stm32l4_spi1/2/3select and - * stm32l4_spi1/2/3status must be provided by board-specific logic. + * The external functions, stm32_spi1/2/3select and + * stm32_spi1/2/3status must be provided by board-specific logic. * They are implementations of the select and status methods of the SPI * interface defined by struct spi_ops_s (see include/nuttx/spi/spi.h). * All other methods (including up_spiinitialize()) are provided by * common STM32 logic. To use this common SPI logic on your board: * - * 1. Provide logic in stm32l4_boardinitialize() to configure SPI chip + * 1. Provide logic in stm32_boardinitialize() to configure SPI chip * select pins. - * 2. Provide stm32l4_spi1/2/3select() and stm32l4_spi1/2/3status() + * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() * functions in your board-specific logic. These functions will perform * chip selection and status operations using GPIOs in the way your * board is configured. @@ -148,36 +148,36 @@ void weak_function stm32l4_spidev_initialize(void) * ****************************************************************************/ -#ifdef CONFIG_STM32L4_SPI1 -void stm32l4_spi1select(struct spi_dev_s *dev, +#ifdef CONFIG_STM32_SPI1 +void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, bool selected) { spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); } -uint8_t stm32l4_spi1status(struct spi_dev_s *dev, uint32_t devid) +uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) { return 0; } #endif -#ifdef CONFIG_STM32L4_SPI2 -void stm32l4_spi2select(struct spi_dev_s *dev, +#ifdef CONFIG_STM32_SPI2 +void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid, bool selected) { spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); } -uint8_t stm32l4_spi2status(struct spi_dev_s *dev, uint32_t devid) +uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) { return 0; } #endif -#ifdef CONFIG_STM32L4_SPI3 -void stm32l4_spi3select(struct spi_dev_s *dev, +#ifdef CONFIG_STM32_SPI3 +void stm32_spi3select(struct spi_dev_s *dev, uint32_t devid, bool selected) { spiinfo("devid: %d CS: %s\n", @@ -186,19 +186,19 @@ void stm32l4_spi3select(struct spi_dev_s *dev, #ifdef HAVE_SPSGRF if (devid == SPIDEV_WIRELESS(0)) { - stm32l4_gpiowrite(GPIO_SPSGRF_CS, !selected); + stm32_gpiowrite(GPIO_SPSGRF_CS, !selected); } #endif } -uint8_t stm32l4_spi3status(struct spi_dev_s *dev, uint32_t devid) +uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid) { return 0; } #endif /**************************************************************************** - * Name: stm32l4_spi1cmddata + * Name: stm32_spi1cmddata * * Description: * Set or clear the SH1101A A0 or SD1306 D/C n bit to select data (true) @@ -221,26 +221,26 @@ uint8_t stm32l4_spi3status(struct spi_dev_s *dev, uint32_t devid) ****************************************************************************/ #ifdef CONFIG_SPI_CMDDATA -#ifdef CONFIG_STM32L4_SPI1 -int stm32l4_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) +#ifdef CONFIG_STM32_SPI1 +int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return OK; } #endif -#ifdef CONFIG_STM32L4_SPI2 -int stm32l4_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) +#ifdef CONFIG_STM32_SPI2 +int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return OK; } #endif -#ifdef CONFIG_STM32L4_SPI3 -int stm32l4_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) +#ifdef CONFIG_STM32_SPI3 +int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return OK; } #endif #endif /* CONFIG_SPI_CMDDATA */ -#endif /* CONFIG_STM32L4_SPI1 || CONFIG_STM32L4_SPI2 || CONFIG_STM32L4_SPI3 */ +#endif /* CONFIG_STM32_SPI1 || CONFIG_STM32_SPI2 || CONFIG_STM32_SPI3 */ diff --git a/boards/arm/stm32l4/b-l475e-iot01a/src/stm32_spirit.c b/boards/arm/stm32l4/b-l475e-iot01a/src/stm32_spirit.c index 0adaebb0c1822..9a471bd9f0cbd 100644 --- a/boards/arm/stm32l4/b-l475e-iot01a/src/stm32_spirit.c +++ b/boards/arm/stm32l4/b-l475e-iot01a/src/stm32_spirit.c @@ -59,7 +59,7 @@ * Private Types ****************************************************************************/ -struct stm32l4_priv_s +struct stm32_priv_s { struct spirit_lower_s dev; xcpt_t handler; @@ -77,18 +77,18 @@ struct stm32l4_priv_s * to isolate the Spirit driver from differences in GPIO interrupt handling * varying boards and MCUs. * - * stm32l4_reset - Reset the Spirit part. - * stm32l4_attach_irq - Attach the Spirit interrupt handler to the GPIO + * stm32_reset - Reset the Spirit part. + * stm32_attach_irq - Attach the Spirit interrupt handler to the GPIO * interrupt - * stm32l4_enable_irq - Enable or disable the GPIO interrupt + * stm32_enable_irq - Enable or disable the GPIO interrupt */ -static int stm32l4_reset(const struct spirit_lower_s *lower); -static int stm32l4_attach_irq(const struct spirit_lower_s *lower, +static int stm32_reset(const struct spirit_lower_s *lower); +static int stm32_attach_irq(const struct spirit_lower_s *lower, xcpt_t handler, void *arg); -static void stm32l4_enable_irq(const struct spirit_lower_s *lower, +static void stm32_enable_irq(const struct spirit_lower_s *lower, bool state); -static int stm32l4_spirit_devsetup(struct stm32l4_priv_s *priv); +static int stm32_spirit_devsetup(struct stm32_priv_s *priv); /**************************************************************************** * Private Data @@ -104,11 +104,11 @@ static int stm32l4_spirit_devsetup(struct stm32l4_priv_s *priv); * may modify frequency or X plate resistance values. */ -static struct stm32l4_priv_s g_spirit = +static struct stm32_priv_s g_spirit = { - .dev.reset = stm32l4_reset, - .dev.attach = stm32l4_attach_irq, - .dev.enable = stm32l4_enable_irq, + .dev.reset = stm32_reset, + .dev.attach = stm32_attach_irq, + .dev.enable = stm32_enable_irq, .handler = NULL, .arg = NULL, .intcfg = GPIO_SPSGRF_INT, @@ -122,16 +122,16 @@ static struct stm32l4_priv_s g_spirit = /* Reset the Spirit 1 part */ -static int stm32l4_reset(const struct spirit_lower_s *lower) +static int stm32_reset(const struct spirit_lower_s *lower) { - struct stm32l4_priv_s *priv = (struct stm32l4_priv_s *)lower; + struct stm32_priv_s *priv = (struct stm32_priv_s *)lower; DEBUGASSERT(priv != NULL); /* Reset pulse */ - stm32l4_gpiowrite(priv->sdncfg, true); - stm32l4_gpiowrite(priv->sdncfg, false); + stm32_gpiowrite(priv->sdncfg, true); + stm32_gpiowrite(priv->sdncfg, false); /* Wait minimum 1.5 ms to allow Spirit a proper boot-up sequence */ @@ -145,15 +145,15 @@ static int stm32l4_reset(const struct spirit_lower_s *lower) * interrupts should be configured on both rising and falling edges * so that contact and loss-of-contact events can be detected. * - * stm32l4_attach_irq - Attach the Spirit interrupt handler to the GPIO + * stm32_attach_irq - Attach the Spirit interrupt handler to the GPIO * interrupt - * stm32l4_enable_irq - Enable or disable the GPIO interrupt + * stm32_enable_irq - Enable or disable the GPIO interrupt */ -static int stm32l4_attach_irq(const struct spirit_lower_s *lower, +static int stm32_attach_irq(const struct spirit_lower_s *lower, xcpt_t handler, void *arg) { - struct stm32l4_priv_s *priv = (struct stm32l4_priv_s *)lower; + struct stm32_priv_s *priv = (struct stm32_priv_s *)lower; DEBUGASSERT(priv != NULL); @@ -164,10 +164,10 @@ static int stm32l4_attach_irq(const struct spirit_lower_s *lower, return OK; } -static void stm32l4_enable_irq(const struct spirit_lower_s *lower, +static void stm32_enable_irq(const struct spirit_lower_s *lower, bool state) { - struct stm32l4_priv_s *priv = (struct stm32l4_priv_s *)lower; + struct stm32_priv_s *priv = (struct stm32_priv_s *)lower; /* The caller should not attempt to enable interrupts if the handler * has not yet been 'attached' @@ -183,20 +183,20 @@ static void stm32l4_enable_irq(const struct spirit_lower_s *lower, { /* Enable interrupts on falling edge (active low) */ - stm32l4_gpiosetevent(priv->intcfg, false, true, false, + stm32_gpiosetevent(priv->intcfg, false, true, false, priv->handler, priv->arg); } else { /* Disable interrupts */ - stm32l4_gpiosetevent(priv->intcfg, false, false, false, + stm32_gpiosetevent(priv->intcfg, false, false, false, NULL, NULL); } } /**************************************************************************** - * Name: stm32l4_spirit_devsetup + * Name: stm32_spirit_devsetup * * Description: * Initialize one the Spirit device @@ -207,7 +207,7 @@ static void stm32l4_enable_irq(const struct spirit_lower_s *lower, * ****************************************************************************/ -static int stm32l4_spirit_devsetup(struct stm32l4_priv_s *priv) +static int stm32_spirit_devsetup(struct stm32_priv_s *priv) { struct spi_dev_s *spi; int ret; @@ -216,12 +216,12 @@ static int stm32l4_spirit_devsetup(struct stm32l4_priv_s *priv) * powers down the Spirit. */ - stm32l4_configgpio(priv->intcfg); - stm32l4_configgpio(priv->sdncfg); + stm32_configgpio(priv->intcfg); + stm32_configgpio(priv->sdncfg); /* Initialize the SPI bus and get an instance of the SPI interface */ - spi = stm32l4_spibus_initialize(priv->spidev); + spi = stm32_spibus_initialize(priv->spidev); if (spi == NULL) { wlerr("ERROR: Failed to initialize SPI bus %d\n", priv->spidev); @@ -245,7 +245,7 @@ static int stm32l4_spirit_devsetup(struct stm32l4_priv_s *priv) ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_spirit_initialize + * Name: stm32_spirit_initialize * * Description: * Initialize the Spirit device. @@ -256,13 +256,13 @@ static int stm32l4_spirit_devsetup(struct stm32l4_priv_s *priv) * ****************************************************************************/ -int stm32l4_spirit_initialize(void) +int stm32_spirit_initialize(void) { int ret; wlinfo("Configuring Spirit\n"); - ret = stm32l4_spirit_devsetup(&g_spirit); + ret = stm32_spirit_devsetup(&g_spirit); if (ret < 0) { wlerr("ERROR: Failed to initialize Spirit: %d\n", ret); diff --git a/boards/arm/stm32l4/b-l475e-iot01a/src/stm32_timer.c b/boards/arm/stm32l4/b-l475e-iot01a/src/stm32_timer.c index 36ef0fddd93bf..ecfabfc0424d3 100644 --- a/boards/arm/stm32l4/b-l475e-iot01a/src/stm32_timer.c +++ b/boards/arm/stm32l4/b-l475e-iot01a/src/stm32_timer.c @@ -52,12 +52,12 @@ ****************************************************************************/ #ifdef CONFIG_TIMER -int stm32l4_timer_driver_setup(void) +int stm32_timer_driver_setup(void) { int ret = OK; -#ifdef CONFIG_STM32L4_TIM1 - ret = stm32l4_timer_initialize("/dev/timer0", 1); +#ifdef CONFIG_STM32_TIM1 + ret = stm32_timer_initialize("/dev/timer0", 1); if (ret < 0) { syslog(LOG_ERR, "ERROR: Failed to setup TIM1 at /dev/timer0: %d\n", @@ -65,8 +65,8 @@ int stm32l4_timer_driver_setup(void) } #endif -#ifdef CONFIG_STM32L4_TIM2 - ret = stm32l4_timer_initialize("/dev/timer1", 2); +#ifdef CONFIG_STM32_TIM2 + ret = stm32_timer_initialize("/dev/timer1", 2); if (ret < 0) { syslog(LOG_ERR, "ERROR: Failed to setup TIM2 at /dev/timer1: %d\n", @@ -74,8 +74,8 @@ int stm32l4_timer_driver_setup(void) } #endif -#ifdef CONFIG_STM32L4_TIM3 - ret = stm32l4_timer_initialize("/dev/timer2", 3); +#ifdef CONFIG_STM32_TIM3 + ret = stm32_timer_initialize("/dev/timer2", 3); if (ret < 0) { syslog(LOG_ERR, "ERROR: Failed to setup TIM3 at /dev/timer2: %d\n", @@ -83,8 +83,8 @@ int stm32l4_timer_driver_setup(void) } #endif -#ifdef CONFIG_STM32L4_TIM4 - ret = stm32l4_timer_initialize("/dev/timer3", 4); +#ifdef CONFIG_STM32_TIM4 + ret = stm32_timer_initialize("/dev/timer3", 4); if (ret < 0) { syslog(LOG_ERR, "ERROR: Failed to setup TIM2 at /dev/timer3: %d\n", @@ -92,8 +92,8 @@ int stm32l4_timer_driver_setup(void) } #endif -#ifdef CONFIG_STM32L4_TIM5 - ret = stm32l4_timer_initialize("/dev/timer4", 5); +#ifdef CONFIG_STM32_TIM5 + ret = stm32_timer_initialize("/dev/timer4", 5); if (ret < 0) { syslog(LOG_ERR, "ERROR: Failed to setup TIM5 at /dev/timer4: %d\n", @@ -101,8 +101,8 @@ int stm32l4_timer_driver_setup(void) } #endif -#ifdef CONFIG_STM32L4_TIM6 - ret = stm32l4_timer_initialize("/dev/timer5", 6); +#ifdef CONFIG_STM32_TIM6 + ret = stm32_timer_initialize("/dev/timer5", 6); if (ret < 0) { syslog(LOG_ERR, "ERROR: Failed to setup TIM6 at /dev/timer5: %d\n", @@ -110,8 +110,8 @@ int stm32l4_timer_driver_setup(void) } #endif -#ifdef CONFIG_STM32L4_TIM7 - ret = stm32l4_timer_initialize("/dev/timer6", 7); +#ifdef CONFIG_STM32_TIM7 + ret = stm32_timer_initialize("/dev/timer6", 7); if (ret < 0) { syslog(LOG_ERR, "ERROR: Failed to setup TIM7 at /dev/timer6: %d\n", @@ -119,8 +119,8 @@ int stm32l4_timer_driver_setup(void) } #endif -#ifdef CONFIG_STM32L4_TIM8 - ret = stm32l4_timer_initialize("/dev/timer7", 8); +#ifdef CONFIG_STM32_TIM8 + ret = stm32_timer_initialize("/dev/timer7", 8); if (ret < 0) { syslog(LOG_ERR, "ERROR: Failed to setup TIM8 at /dev/timer7: %d\n", @@ -128,8 +128,8 @@ int stm32l4_timer_driver_setup(void) } #endif -#ifdef CONFIG_STM32L4_TIM15 - ret = stm32l4_timer_initialize("/dev/timer8", 15); +#ifdef CONFIG_STM32_TIM15 + ret = stm32_timer_initialize("/dev/timer8", 15); if (ret < 0) { syslog(LOG_ERR, "ERROR: Failed to setup TIM15 at /dev/time8: %d\n", @@ -137,8 +137,8 @@ int stm32l4_timer_driver_setup(void) } #endif -#ifdef CONFIG_STM32L4_TIM16 - ret = stm32l4_timer_initialize("/dev/timer9", 16); +#ifdef CONFIG_STM32_TIM16 + ret = stm32_timer_initialize("/dev/timer9", 16); if (ret < 0) { syslog(LOG_ERR, "ERROR: Failed to setup TIM16 at /dev/time9: %d\n", @@ -146,8 +146,8 @@ int stm32l4_timer_driver_setup(void) } #endif -#ifdef CONFIG_STM32L4_TIM17 - ret = stm32l4_timer_initialize("/dev/timer10", 17); +#ifdef CONFIG_STM32_TIM17 + ret = stm32_timer_initialize("/dev/timer10", 17); if (ret < 0) { syslog(LOG_ERR, "ERROR: Failed to setup TIM17 at /dev/time10: %d\n", diff --git a/boards/arm/stm32l4/b-l475e-iot01a/src/stm32_userleds.c b/boards/arm/stm32l4/b-l475e-iot01a/src/stm32_userleds.c index e431ebdcee9b6..d4bf80c9c5f30 100644 --- a/boards/arm/stm32l4/b-l475e-iot01a/src/stm32_userleds.c +++ b/boards/arm/stm32l4/b-l475e-iot01a/src/stm32_userleds.c @@ -46,8 +46,8 @@ uint32_t board_userled_initialize(void) { /* Configure LED gpio as output */ - stm32l4_configgpio(GPIO_LED1); - stm32l4_configgpio(GPIO_LED2); + stm32_configgpio(GPIO_LED1); + stm32_configgpio(GPIO_LED2); return BOARD_NLEDS; } @@ -59,11 +59,11 @@ void board_userled(int led, bool ledon) { if (led == BOARD_LED1) { - stm32l4_gpiowrite(GPIO_LED1, ledon); + stm32_gpiowrite(GPIO_LED1, ledon); } else if (led == BOARD_LED2) { - stm32l4_gpiowrite(GPIO_LED2, ledon); + stm32_gpiowrite(GPIO_LED2, ledon); } } @@ -73,8 +73,8 @@ void board_userled(int led, bool ledon) void board_userled_all(uint32_t ledset) { - stm32l4_gpiowrite(GPIO_LED1, !!(ledset & BOARD_LED1_BIT)); - stm32l4_gpiowrite(GPIO_LED2, !!(ledset & BOARD_LED2_BIT)); + stm32_gpiowrite(GPIO_LED1, !!(ledset & BOARD_LED1_BIT)); + stm32_gpiowrite(GPIO_LED2, !!(ledset & BOARD_LED2_BIT)); } #endif /* !CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32l4/common/CMakeLists.txt b/boards/arm/stm32l4/common/CMakeLists.txt new file mode 100644 index 0000000000000..c675d8563e38e --- /dev/null +++ b/boards/arm/stm32l4/common/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32l4/common/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(${NUTTX_DIR}/boards/arm/common/stm32 stm32_common) diff --git a/boards/arm/stm32l4/common/Kconfig b/boards/arm/stm32l4/common/Kconfig new file mode 100644 index 0000000000000..5c48f62a0258b --- /dev/null +++ b/boards/arm/stm32l4/common/Kconfig @@ -0,0 +1,6 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# + +source "boards/arm/common/stm32/Kconfig" diff --git a/boards/arm/stm32l4/common/Makefile b/boards/arm/stm32l4/common/Makefile new file mode 100644 index 0000000000000..af882fa76b3ec --- /dev/null +++ b/boards/arm/stm32l4/common/Makefile @@ -0,0 +1,39 @@ +############################################################################# +# boards/arm/stm32l4/common/Makefile +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################# + +include $(TOPDIR)/Make.defs + +STM32_BOARD_COMMON_DIR := $(TOPDIR)$(DELIM)boards$(DELIM)arm$(DELIM)common$(DELIM)stm32 +STM32_COMMON_SRCDIR := $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)common$(DELIM)stm32 + +include board/Make.defs +include $(STM32_BOARD_COMMON_DIR)$(DELIM)src$(DELIM)Make.defs + +DEPPATH += --dep-path board + +include $(TOPDIR)/boards/Board.mk + +ARCHSRCDIR = $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src +BOARDDIR = $(ARCHSRCDIR)$(DELIM)board +CFLAGS += ${INCDIR_PREFIX}$(BOARDDIR)$(DELIM)include +CFLAGS += ${INCDIR_PREFIX}$(STM32_COMMON_SRCDIR) +CXXFLAGS += ${INCDIR_PREFIX}$(STM32_COMMON_SRCDIR) diff --git a/boards/arm/stm32l4/nucleo-l432kc/Kconfig b/boards/arm/stm32l4/nucleo-l432kc/Kconfig index 7ed758a07d748..ba154e7dd9494 100644 --- a/boards/arm/stm32l4/nucleo-l432kc/Kconfig +++ b/boards/arm/stm32l4/nucleo-l432kc/Kconfig @@ -6,13 +6,13 @@ if ARCH_BOARD_NUCLEO_L432KC menu "U[S]ART Pin Layouts" - depends on STM32L4_USART1 || STM32L4_USART2 || STM32L4_LPUART1 + depends on STM32_USART1 || STM32_USART2 || STM32_LPUART1 comment "USART1 is disabled. (Enable it under: System Type -> STM32L4 Peripheral Support)" - depends on !STM32L4_USART1 + depends on !STM32_USART1 choice - depends on STM32L4_USART1 + depends on STM32_USART1 prompt "USART1 RX pin" default ARCH_BOARD_USART1_RX_PA10 ---help--- @@ -29,7 +29,7 @@ config ARCH_BOARD_USART1_RX_PB7 endchoice choice - depends on STM32L4_USART1 + depends on STM32_USART1 prompt "USART1 TX pin" default ARCH_BOARD_USART1_TX_PA9 ---help--- @@ -46,10 +46,10 @@ config ARCH_BOARD_USART1_TX_PB6 endchoice comment "USART2 is disabled. (Enable it under: System Type -> STM32L4 Peripheral Support)" - depends on !STM32L4_USART2 + depends on !STM32_USART2 choice - depends on STM32L4_USART2 + depends on STM32_USART2 prompt "USART2 RX pin" default ARCH_BOARD_USART2_RX_PA15 ---help--- @@ -66,7 +66,7 @@ config ARCH_BOARD_USART2_RX_PA15 endchoice choice - depends on STM32L4_USART2 + depends on STM32_USART2 prompt "USART2 TX pin" default ARCH_BOARD_USART2_TX_PA2 ---help--- @@ -79,10 +79,10 @@ config ARCH_BOARD_USART2_TX_PA2 endchoice comment "LPUART1 is disabled. (Enable it under: System Type -> STM32L4 Peripheral Support)" - depends on !STM32L4_LPUART1 + depends on !STM32_LPUART1 choice - depends on STM32L4_LPUART1 + depends on STM32_LPUART1 prompt "LPUART1 RX pin" default ARCH_BOARD_LPUART1_RX_PA3 ---help--- @@ -94,7 +94,7 @@ config ARCH_BOARD_LPUART1_RX_PA3 endchoice choice - depends on STM32L4_LPUART1 + depends on STM32_LPUART1 prompt "LPUART1 TX pin" default ARCH_BOARD_LPUART1_TX_PA2 ---help--- @@ -142,7 +142,7 @@ config NUCLEOL432KC_SPWM_PHASE_NUM endif menuconfig NUCLEOL432KC_DAC_WGEN - depends on (STM32L4_DAC_LL_OPS) && (STM32L4_DAC1_DMA) && (STM32L4_TIM2_DAC) + depends on (STM32_DAC_LL_OPS) && (STM32_DAC1_DMA) && (STM32_TIM2_DAC) bool "Sinusoidal DAC wave generator example" default n diff --git a/boards/arm/stm32l4/nucleo-l432kc/configs/nsh/defconfig b/boards/arm/stm32l4/nucleo-l432kc/configs/nsh/defconfig index a897ae2145b2c..dbc3a0ea493d7 100644 --- a/boards/arm/stm32l4/nucleo-l432kc/configs/nsh/defconfig +++ b/boards/arm/stm32l4/nucleo-l432kc/configs/nsh/defconfig @@ -14,6 +14,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-l432kc" CONFIG_ARCH_BOARD_NUCLEO_L432KC=y CONFIG_ARCH_CHIP="stm32l4" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32L432KC=y CONFIG_ARCH_CHIP_STM32L4=y CONFIG_ARCH_INTERRUPTSTACK=2048 @@ -44,15 +45,15 @@ CONFIG_RTC_IOCTL=y CONFIG_RTC_NALARMS=2 CONFIG_SCHED_WAITPID=y CONFIG_SPI=y -CONFIG_STM32L4_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32L4_DMA1=y -CONFIG_STM32L4_DMA2=y -CONFIG_STM32L4_PWR=y -CONFIG_STM32L4_RNG=y -CONFIG_STM32L4_RTC=y -CONFIG_STM32L4_SAI1PLL=y -CONFIG_STM32L4_SRAM2_HEAP=y -CONFIG_STM32L4_USART2=y +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_DMA1=y +CONFIG_STM32_DMA2=y +CONFIG_STM32_PWR=y +CONFIG_STM32_RNG=y +CONFIG_STM32_RTC=y +CONFIG_STM32_SAI1PLL=y +CONFIG_STM32_SRAM2_HEAP=y +CONFIG_STM32_USART2=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_TESTING_OSTEST=y diff --git a/boards/arm/stm32l4/nucleo-l432kc/configs/spwm/defconfig b/boards/arm/stm32l4/nucleo-l432kc/configs/spwm/defconfig index 91ef99032a184..19d272a0fd50e 100644 --- a/boards/arm/stm32l4/nucleo-l432kc/configs/spwm/defconfig +++ b/boards/arm/stm32l4/nucleo-l432kc/configs/spwm/defconfig @@ -5,11 +5,12 @@ # You can then do "make savedefconfig" to generate a new defconfig file that includes your # modifications. # -# CONFIG_STM32L4_SYSCFG is not set +# CONFIG_STM32_SYSCFG is not set CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-l432kc" CONFIG_ARCH_BOARD_NUCLEO_L432KC=y CONFIG_ARCH_CHIP="stm32l4" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32L432KC=y CONFIG_ARCH_CHIP_STM32L4=y CONFIG_ARCH_HIPRI_INTERRUPT=y @@ -36,17 +37,17 @@ CONFIG_RAW_BINARY=y CONFIG_RR_INTERVAL=200 CONFIG_SCHED_WAITPID=y CONFIG_SPI=y -CONFIG_STM32L4_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32L4_DMA1=y -CONFIG_STM32L4_DMA2=y -CONFIG_STM32L4_PWM_LL_OPS=y -CONFIG_STM32L4_SRAM2_HEAP=y -CONFIG_STM32L4_TIM1=y -CONFIG_STM32L4_TIM1_CH1NOUT=y -CONFIG_STM32L4_TIM1_CH1OUT=y -CONFIG_STM32L4_TIM1_PWM=y -CONFIG_STM32L4_TIM6=y -CONFIG_STM32L4_USART2=y +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_DMA1=y +CONFIG_STM32_DMA2=y +CONFIG_STM32_PWM_LL_OPS=y +CONFIG_STM32_SRAM2_HEAP=y +CONFIG_STM32_TIM1=y +CONFIG_STM32_TIM1_CH1NOUT=y +CONFIG_STM32_TIM1_CH1OUT=y +CONFIG_STM32_TIM1_PWM=y +CONFIG_STM32_TIM6=y +CONFIG_STM32_USART2=y CONFIG_SYSTEM_READLINE=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32l4/nucleo-l432kc/configs/wgen/defconfig b/boards/arm/stm32l4/nucleo-l432kc/configs/wgen/defconfig index 433b98f9aab67..498038354779f 100644 --- a/boards/arm/stm32l4/nucleo-l432kc/configs/wgen/defconfig +++ b/boards/arm/stm32l4/nucleo-l432kc/configs/wgen/defconfig @@ -15,6 +15,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-l432kc" CONFIG_ARCH_BOARD_NUCLEO_L432KC=y CONFIG_ARCH_CHIP="stm32l4" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32L432KC=y CONFIG_ARCH_CHIP_STM32L4=y CONFIG_ARCH_INTERRUPTSTACK=2048 @@ -47,23 +48,23 @@ CONFIG_RTC_IOCTL=y CONFIG_RTC_NALARMS=2 CONFIG_SCHED_WAITPID=y CONFIG_SPI=y -CONFIG_STM32L4_DAC1=y -CONFIG_STM32L4_DAC1_DMA=y -CONFIG_STM32L4_DAC1_DMA_BUFFER_SIZE=40 -CONFIG_STM32L4_DAC1_TIMER=2 -CONFIG_STM32L4_DAC1_TIMER_FREQUENCY=2000 -CONFIG_STM32L4_DAC_LL_OPS=y -CONFIG_STM32L4_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32L4_DMA1=y -CONFIG_STM32L4_DMA2=y -CONFIG_STM32L4_PWR=y -CONFIG_STM32L4_RNG=y -CONFIG_STM32L4_RTC=y -CONFIG_STM32L4_SAI1PLL=y -CONFIG_STM32L4_SRAM2_HEAP=y -CONFIG_STM32L4_TIM2=y -CONFIG_STM32L4_TIM2_DAC=y -CONFIG_STM32L4_USART2=y +CONFIG_STM32_DAC1=y +CONFIG_STM32_DAC1_DMA=y +CONFIG_STM32_DAC1_DMA_BUFFER_SIZE=40 +CONFIG_STM32_DAC1_TIMER=2 +CONFIG_STM32_DAC1_TIMER_FREQUENCY=2000 +CONFIG_STM32_DAC_LL_OPS=y +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_DMA1=y +CONFIG_STM32_DMA2=y +CONFIG_STM32_PWR=y +CONFIG_STM32_RNG=y +CONFIG_STM32_RTC=y +CONFIG_STM32_SAI1PLL=y +CONFIG_STM32_SRAM2_HEAP=y +CONFIG_STM32_TIM2=y +CONFIG_STM32_TIM2_DAC=y +CONFIG_STM32_USART2=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_TESTING_OSTEST=y diff --git a/boards/arm/stm32l4/nucleo-l432kc/include/board.h b/boards/arm/stm32l4/nucleo-l432kc/include/board.h index cc2f750933f9c..fc6615cd13082 100644 --- a/boards/arm/stm32l4/nucleo-l432kc/include/board.h +++ b/boards/arm/stm32l4/nucleo-l432kc/include/board.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32L4_NUCLEO_L432KC_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32L4_NUCLEO_L432KC_INCLUDE_BOARD_H +#ifndef __BOARDS_ARM_STM32_NUCLEO_L432KC_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32_NUCLEO_L432KC_INCLUDE_BOARD_H /**************************************************************************** * Included Files @@ -264,8 +264,8 @@ * CH1 | 1(A4) 2(A8) */ -#if defined(CONFIG_STM32L4_LPTIM2_CLK_APB1) -# define STM32L4_LPTIM2_FREQUENCY STM32L4_APB1_LPTIM2_CLKIN +#if defined(CONFIG_STM32_LPTIM2_CLK_APB1) +# define STM32_LPTIM2_FREQUENCY STM32_APB1_LPTIM2_CLKIN #endif #if 1 @@ -294,7 +294,7 @@ extern "C" ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_board_initialize + * Name: stm32_board_initialize * * Description: * All STM32L4 architectures must provide the following entry point. @@ -304,7 +304,7 @@ extern "C" * ****************************************************************************/ -void stm32l4_board_initialize(void); +void stm32_board_initialize(void); #undef EXTERN #if defined(__cplusplus) @@ -312,4 +312,4 @@ void stm32l4_board_initialize(void); #endif #endif /* __ASSEMBLY__ */ -#endif /* __BOARDS_ARM_STM32L4_NUCLEO_L432KC_INCLUDE_BOARD_H */ +#endif /* __BOARDS_ARM_STM32_NUCLEO_L432KC_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32l4/nucleo-l432kc/include/nucleo-l432kc.h b/boards/arm/stm32l4/nucleo-l432kc/include/nucleo-l432kc.h index bc2cd77d6dde7..097de375d1032 100644 --- a/boards/arm/stm32l4/nucleo-l432kc/include/nucleo-l432kc.h +++ b/boards/arm/stm32l4/nucleo-l432kc/include/nucleo-l432kc.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32L4_NUCLEO_L432KC_INCLUDE_NUCLEO_L432KC_H -#define __BOARDS_ARM_STM32L4_NUCLEO_L432KC_INCLUDE_NUCLEO_L432KC_H +#ifndef __BOARDS_ARM_STM32_NUCLEO_L432KC_INCLUDE_NUCLEO_L432KC_H +#define __BOARDS_ARM_STM32_NUCLEO_L432KC_INCLUDE_NUCLEO_L432KC_H /**************************************************************************** * Included Files @@ -57,20 +57,20 @@ * System Clock source : PLL (HSI) * SYSCLK(Hz) : 80000000 Determined by PLL * configuration - * HCLK(Hz) : 80000000 (STM32L4_RCC_CFGR_HPRE) + * HCLK(Hz) : 80000000 (STM32_RCC_CFGR_HPRE) * (Max 80 MHz) - * AHB Prescaler : 1 (STM32L4_RCC_CFGR_HPRE) + * AHB Prescaler : 1 (STM32_RCC_CFGR_HPRE) * (Max 80 MHz) - * APB1 Prescaler : 1 (STM32L4_RCC_CFGR_PPRE1) + * APB1 Prescaler : 1 (STM32_RCC_CFGR_PPRE1) * (Max 80 MHz) - * APB2 Prescaler : 1 (STM32L4_RCC_CFGR_PPRE2) + * APB2 Prescaler : 1 (STM32_RCC_CFGR_PPRE2) * (Max 80 MHz) * HSI Frequency(Hz) : 16000000 (nominal) - * PLLM : 1 (STM32L4_PLLCFG_PLLM) - * PLLN : 10 (STM32L4_PLLCFG_PLLN) - * PLLP : 0 (STM32L4_PLLCFG_PLLP) - * PLLQ : 0 (STM32L4_PLLCFG_PLLQ) - * PLLR : 2 (STM32L4_PLLCFG_PLLR) + * PLLM : 1 (STM32_PLLCFG_PLLM) + * PLLN : 10 (STM32_PLLCFG_PLLN) + * PLLP : 0 (STM32_PLLCFG_PLLP) + * PLLQ : 0 (STM32_PLLCFG_PLLQ) + * PLLR : 2 (STM32_PLLCFG_PLLR) * PLLSAI1N : 12 * PLLSAI1Q : 4 * Flash Latency(WS) : 4 @@ -86,11 +86,11 @@ * LSE - 32.768 kHz installed */ -#define STM32L4_HSI_FREQUENCY 16000000ul -#define STM32L4_LSI_FREQUENCY 32000 -#define STM32L4_LSE_FREQUENCY 32768 +#define STM32_HSI_FREQUENCY 16000000ul +#define STM32_LSI_FREQUENCY 32000 +#define STM32_LSE_FREQUENCY 32768 -#define STM32L4_BOARD_USEHSI 1 +#define STM32_BOARD_USEHSI 1 /* XXX sysclk mux = pllclk */ @@ -127,7 +127,7 @@ * * PLL source is HSI * - * PLL_REF = STM32L4_HSI_FREQUENCY / PLLM + * PLL_REF = STM32_HSI_FREQUENCY / PLLM * = 16,000,000 / 1 * = 16,000,000 * @@ -146,7 +146,7 @@ * * The clock input and M divider are identical to the main PLL. * However the multiplier and postscalers are independent. - * The PLLSAI1 is configured only if CONFIG_STM32L4_SAI1PLL is defined + * The PLLSAI1 is configured only if CONFIG_STM32_SAI1PLL is defined * * SAI1VCO input frequency = PLL input clock frequency * SAI1VCO output frequency = SAI1VCO input frequency × PLLSAI1N, @@ -169,7 +169,7 @@ * * The clock input and M divider are identical to the main PLL. * However the multiplier and postscalers are independent. - * The PLLSAI2 is configured only if CONFIG_STM32L4_SAI2PLL is defined + * The PLLSAI2 is configured only if CONFIG_STM32_SAI2PLL is defined * * SAI2VCO input frequency = PLL input clock frequency * SAI2VCO output frequency = SAI2VCO input frequency × PLLSAI2N, @@ -216,7 +216,7 @@ * as per comment above HSI) */ -#define STM32L4_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) /* 'main' PLL config; we use this to generate our system clock via the R * output. We set it up as 16 MHz / 1 * 10 / 2 = 80 MHz @@ -226,13 +226,13 @@ * applications may want things done this way. */ -#define STM32L4_PLLCFG_PLLN RCC_PLLCFG_PLLN(10) -#define STM32L4_PLLCFG_PLLP 0 -#undef STM32L4_PLLCFG_PLLP_ENABLED -#define STM32L4_PLLCFG_PLLQ RCC_PLLCFG_PLLQ_2 -#define STM32L4_PLLCFG_PLLQ_ENABLED -#define STM32L4_PLLCFG_PLLR RCC_PLLCFG_PLLR(2) -#define STM32L4_PLLCFG_PLLR_ENABLED +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(10) +#define STM32_PLLCFG_PLLP 0 +#undef STM32_PLLCFG_PLLP_ENABLED +#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ_2 +#define STM32_PLLCFG_PLLQ_ENABLED +#define STM32_PLLCFG_PLLR RCC_PLLCFG_PLLR(2) +#define STM32_PLLCFG_PLLR_ENABLED /* 'SAIPLL1' is used to generate the 48 MHz clock, since we can't * do that with the main PLL's N value. We set N = 12, and enable @@ -246,45 +246,45 @@ * that is selected via a #define here, like all these other params. */ -#define STM32L4_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(12) -#define STM32L4_PLLSAI1CFG_PLLP 0 -#undef STM32L4_PLLSAI1CFG_PLLP_ENABLED -#define STM32L4_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_4 -#define STM32L4_PLLSAI1CFG_PLLQ_ENABLED -#define STM32L4_PLLSAI1CFG_PLLR 0 -#undef STM32L4_PLLSAI1CFG_PLLR_ENABLED +#define STM32_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(12) +#define STM32_PLLSAI1CFG_PLLP 0 +#undef STM32_PLLSAI1CFG_PLLP_ENABLED +#define STM32_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_4 +#define STM32_PLLSAI1CFG_PLLQ_ENABLED +#define STM32_PLLSAI1CFG_PLLR 0 +#undef STM32_PLLSAI1CFG_PLLR_ENABLED /* 'SAIPLL2' is not used in this application */ -#define STM32L4_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) -#define STM32L4_PLLSAI2CFG_PLLP 0 -#undef STM32L4_PLLSAI2CFG_PLLP_ENABLED -#define STM32L4_PLLSAI2CFG_PLLR 0 -#undef STM32L4_PLLSAI2CFG_PLLR_ENABLED +#define STM32_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) +#define STM32_PLLSAI2CFG_PLLP 0 +#undef STM32_PLLSAI2CFG_PLLP_ENABLED +#define STM32_PLLSAI2CFG_PLLR 0 +#undef STM32_PLLSAI2CFG_PLLR_ENABLED -#define STM32L4_SYSCLK_FREQUENCY 80000000ul +#define STM32_SYSCLK_FREQUENCY 80000000ul /* CLK48 will come from PLLSAI1 (implicitly Q) */ -#if defined(CONFIG_STM32L4_USBFS) || defined(CONFIG_STM32L4_RNG) -# define STM32L4_USE_CLK48 1 -# define STM32L4_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 -# define STM32L4_HSI48_SYNCSRC SYNCSRC_NONE +#if defined(CONFIG_STM32_USBFS) || defined(CONFIG_STM32_RNG) +# define STM32_USE_CLK48 1 +# define STM32_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 +# define STM32_HSI48_SYNCSRC SYNCSRC_NONE #endif /* enable the LSE oscillator, used automatically trim the MSI, and for RTC */ -#define STM32L4_USE_LSE 1 +#define STM32_USE_LSE 1 /* AHB clock (HCLK) is SYSCLK (80MHz) */ -#define STM32L4_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ -#define STM32L4_HCLK_FREQUENCY STM32L4_SYSCLK_FREQUENCY +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY /* APB1 clock (PCLK1) is HCLK / 1 (80MHz) */ -#define STM32L4_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ -#define STM32L4_PCLK1_FREQUENCY (STM32L4_HCLK_FREQUENCY / 1) +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY / 1) /* The timer clock frequencies are automatically defined by hardware. * If the APB prescaler equals 1, the timer clock frequencies are set to the @@ -293,16 +293,16 @@ * REVISIT : this can be configured */ -#define STM32L4_APB1_TIM2_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM6_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM7_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_LPTIM1_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_LPTIM2_CLKIN (STM32L4_PCLK1_FREQUENCY) +#define STM32_APB1_TIM2_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_LPTIM1_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_LPTIM2_CLKIN (STM32_PCLK1_FREQUENCY) /* APB2 clock (PCLK2) is HCLK (80MHz) */ -#define STM32L4_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ -#define STM32L4_PCLK2_FREQUENCY (STM32L4_HCLK_FREQUENCY / 1) +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ +#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY / 1) /* The timer clock frequencies are automatically defined by hardware. * If the APB prescaler equals 1, the timer clock frequencies are set to the @@ -311,9 +311,9 @@ * REVISIT : this can be configured */ -#define STM32L4_APB2_TIM1_CLKIN (STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM15_CLKIN (STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM16_CLKIN (STM32L4_PCLK2_FREQUENCY) +#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM15_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM16_CLKIN (STM32_PCLK2_FREQUENCY) /* TODO SDMMC */ @@ -321,7 +321,7 @@ /* Use the HSE */ -#define STM32L4_BOARD_USEHSE 1 +#define STM32_BOARD_USEHSE 1 /* XXX sysclk mux = pllclk */ @@ -329,59 +329,59 @@ /* Prescaler common to all PLL inputs */ -#define STM32L4_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) /* 'main' PLL config; we use this to generate our system clock */ -#define STM32L4_PLLCFG_PLLN RCC_PLLCFG_PLLN(20) -#define STM32L4_PLLCFG_PLLP 0 -#undef STM32L4_PLLCFG_PLLP_ENABLED -#define STM32L4_PLLCFG_PLLQ 0 -#undef STM32L4_PLLCFG_PLLQ_ENABLED -#define STM32L4_PLLCFG_PLLR RCC_PLLCFG_PLLR_2 -#define STM32L4_PLLCFG_PLLR_ENABLED +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(20) +#define STM32_PLLCFG_PLLP 0 +#undef STM32_PLLCFG_PLLP_ENABLED +#define STM32_PLLCFG_PLLQ 0 +#undef STM32_PLLCFG_PLLQ_ENABLED +#define STM32_PLLCFG_PLLR RCC_PLLCFG_PLLR_2 +#define STM32_PLLCFG_PLLR_ENABLED /* 'SAIPLL1' is used to generate the 48 MHz clock */ -#define STM32L4_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(12) -#define STM32L4_PLLSAI1CFG_PLLP 0 -#undef STM32L4_PLLSAI1CFG_PLLP_ENABLED -#define STM32L4_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_2 -#define STM32L4_PLLSAI1CFG_PLLQ_ENABLED -#define STM32L4_PLLSAI1CFG_PLLR 0 -#undef STM32L4_PLLSAI1CFG_PLLR_ENABLED +#define STM32_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(12) +#define STM32_PLLSAI1CFG_PLLP 0 +#undef STM32_PLLSAI1CFG_PLLP_ENABLED +#define STM32_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_2 +#define STM32_PLLSAI1CFG_PLLQ_ENABLED +#define STM32_PLLSAI1CFG_PLLR 0 +#undef STM32_PLLSAI1CFG_PLLR_ENABLED /* 'SAIPLL2' is not used in this application */ -#define STM32L4_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) -#define STM32L4_PLLSAI2CFG_PLLP 0 -#undef STM32L4_PLLSAI2CFG_PLLP_ENABLED -#define STM32L4_PLLSAI2CFG_PLLR 0 -#undef STM32L4_PLLSAI2CFG_PLLR_ENABLED +#define STM32_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) +#define STM32_PLLSAI2CFG_PLLP 0 +#undef STM32_PLLSAI2CFG_PLLP_ENABLED +#define STM32_PLLSAI2CFG_PLLR 0 +#undef STM32_PLLSAI2CFG_PLLR_ENABLED -#define STM32L4_SYSCLK_FREQUENCY 80000000ul +#define STM32_SYSCLK_FREQUENCY 80000000ul /* Enable CLK48; get it from PLLSAI1 */ -#if defined(CONFIG_STM32L4_USBFS) || defined(CONFIG_STM32L4_RNG) -# define STM32L4_USE_CLK48 1 -# define STM32L4_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 -# define STM32L4_HSI48_SYNCSRC SYNCSRC_NONE +#if defined(CONFIG_STM32_USBFS) || defined(CONFIG_STM32_RNG) +# define STM32_USE_CLK48 1 +# define STM32_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 +# define STM32_HSI48_SYNCSRC SYNCSRC_NONE #endif /* Enable LSE (for the RTC) */ -#define STM32L4_USE_LSE 1 +#define STM32_USE_LSE 1 /* Configure the HCLK divisor (for the AHB bus, core, memory, and DMA */ -#define STM32L4_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ -#define STM32L4_HCLK_FREQUENCY STM32L4_SYSCLK_FREQUENCY +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY /* Configure the APB1 prescaler */ -#define STM32L4_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ -#define STM32L4_PCLK1_FREQUENCY (STM32L4_HCLK_FREQUENCY / 1) +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY / 1) /* The timer clock frequencies are automatically defined by hardware. * If the APB prescaler equals 1, the timer clock frequencies are set to the @@ -390,14 +390,14 @@ * REVISIT : this can be configured */ -#define STM32L4_APB1_TIM2_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM6_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM7_CLKIN (STM32L4_PCLK1_FREQUENCY) +#define STM32_APB1_TIM2_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (STM32_PCLK1_FREQUENCY) /* Configure the APB2 prescaler */ -#define STM32L4_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ -#define STM32L4_PCLK2_FREQUENCY (STM32L4_HCLK_FREQUENCY / 1) +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ +#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY / 1) /* The timer clock frequencies are automatically defined by hardware. * If the APB prescaler equals 1, the timer clock frequencies are set to the @@ -406,16 +406,16 @@ * REVISIT : this can be configured */ -#define STM32L4_APB2_TIM1_CLKIN (STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM15_CLKIN (STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM16_CLKIN (STM32L4_PCLK2_FREQUENCY) +#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM15_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM16_CLKIN (STM32_PCLK2_FREQUENCY) #elif defined(MSI_CLOCK_CONFIG) /* Use the MSI; frequ = 4 MHz; autotrim from LSE */ -#define STM32L4_BOARD_USEMSI 1 -#define STM32L4_BOARD_MSIRANGE RCC_CR_MSIRANGE_4M +#define STM32_BOARD_USEMSI 1 +#define STM32_BOARD_MSIRANGE RCC_CR_MSIRANGE_4M /* XXX sysclk mux = pllclk */ @@ -423,74 +423,74 @@ /* prescaler common to all PLL inputs */ -#define STM32L4_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) /* 'main' PLL config; we use this to generate our system clock */ -#define STM32L4_PLLCFG_PLLN RCC_PLLCFG_PLLN(40) -#define STM32L4_PLLCFG_PLLP 0 -#undef STM32L4_PLLCFG_PLLP_ENABLED -#define STM32L4_PLLCFG_PLLQ 0 -#undef STM32L4_PLLCFG_PLLQ_ENABLED -#define STM32L4_PLLCFG_PLLR RCC_PLLCFG_PLLR_2 -#define STM32L4_PLLCFG_PLLR_ENABLED +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(40) +#define STM32_PLLCFG_PLLP 0 +#undef STM32_PLLCFG_PLLP_ENABLED +#define STM32_PLLCFG_PLLQ 0 +#undef STM32_PLLCFG_PLLQ_ENABLED +#define STM32_PLLCFG_PLLR RCC_PLLCFG_PLLR_2 +#define STM32_PLLCFG_PLLR_ENABLED /* 'SAIPLL1' is used to generate the 48 MHz clock */ -#define STM32L4_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(24) -#define STM32L4_PLLSAI1CFG_PLLP 0 -#undef STM32L4_PLLSAI1CFG_PLLP_ENABLED -#define STM32L4_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_2 -#define STM32L4_PLLSAI1CFG_PLLQ_ENABLED -#define STM32L4_PLLSAI1CFG_PLLR 0 -#undef STM32L4_PLLSAI1CFG_PLLR_ENABLED +#define STM32_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(24) +#define STM32_PLLSAI1CFG_PLLP 0 +#undef STM32_PLLSAI1CFG_PLLP_ENABLED +#define STM32_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_2 +#define STM32_PLLSAI1CFG_PLLQ_ENABLED +#define STM32_PLLSAI1CFG_PLLR 0 +#undef STM32_PLLSAI1CFG_PLLR_ENABLED /* 'SAIPLL2' is not used in this application */ -#define STM32L4_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) -#define STM32L4_PLLSAI2CFG_PLLP 0 -#undef STM32L4_PLLSAI2CFG_PLLP_ENABLED -#define STM32L4_PLLSAI2CFG_PLLR 0 -#undef STM32L4_PLLSAI2CFG_PLLR_ENABLED +#define STM32_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) +#define STM32_PLLSAI2CFG_PLLP 0 +#undef STM32_PLLSAI2CFG_PLLP_ENABLED +#define STM32_PLLSAI2CFG_PLLR 0 +#undef STM32_PLLSAI2CFG_PLLR_ENABLED -#define STM32L4_SYSCLK_FREQUENCY 80000000ul +#define STM32_SYSCLK_FREQUENCY 80000000ul /* Enable CLK48; get it from PLLSAI1 */ -#if defined(CONFIG_STM32L4_USBFS) || defined(CONFIG_STM32L4_RNG) -# define STM32L4_USE_CLK48 1 -# define STM32L4_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 -# define STM32L4_HSI48_SYNCSRC SYNCSRC_NONE +#if defined(CONFIG_STM32_USBFS) || defined(CONFIG_STM32_RNG) +# define STM32_USE_CLK48 1 +# define STM32_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 +# define STM32_HSI48_SYNCSRC SYNCSRC_NONE #endif /* Enable LSE (for the RTC) */ -#define STM32L4_USE_LSE 1 +#define STM32_USE_LSE 1 /* Configure the HCLK divisor (for the AHB bus, core, memory, and DMA */ -#define STM32L4_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ -#define STM32L4_HCLK_FREQUENCY STM32L4_SYSCLK_FREQUENCY +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY /* Configure the APB1 prescaler */ -#define STM32L4_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ -#define STM32L4_PCLK1_FREQUENCY (STM32L4_HCLK_FREQUENCY / 1) +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY / 1) -#define STM32L4_APB1_TIM2_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM6_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM7_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_LPTIM1_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_LPTIM2_CLKIN (STM32L4_PCLK1_FREQUENCY) +#define STM32_APB1_TIM2_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_LPTIM1_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_LPTIM2_CLKIN (STM32_PCLK1_FREQUENCY) /* Configure the APB2 prescaler */ -#define STM32L4_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ -#define STM32L4_PCLK2_FREQUENCY (STM32L4_HCLK_FREQUENCY / 1) +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ +#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY / 1) -#define STM32L4_APB2_TIM1_CLKIN (STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM15_CLKIN (STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM16_CLKIN (STM32L4_PCLK2_FREQUENCY) +#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM15_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM16_CLKIN (STM32_PCLK2_FREQUENCY) #endif @@ -500,14 +500,14 @@ * Note: TIM1,15,16 are on APB2, others on APB1 */ -#define BOARD_TIM1_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM2_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM6_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM7_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM15_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM16_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_LPTIM1_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_LPTIM2_FREQUENCY STM32L4_HCLK_FREQUENCY +#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM2_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM6_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM7_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM15_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM16_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_LPTIM1_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_LPTIM2_FREQUENCY STM32_HCLK_FREQUENCY /**************************************************************************** * Public Data @@ -534,4 +534,4 @@ extern "C" #endif #endif /* __ASSEMBLY__ */ -#endif /* __BOARDS_ARM_STM32L4_NUCLEO_L432KC_INCLUDE_NUCLEO_L432KC_H */ +#endif /* __BOARDS_ARM_STM32_NUCLEO_L432KC_INCLUDE_NUCLEO_L432KC_H */ diff --git a/boards/arm/stm32l4/nucleo-l432kc/src/CMakeLists.txt b/boards/arm/stm32l4/nucleo-l432kc/src/CMakeLists.txt index 4a419a020455d..374e99abc251b 100644 --- a/boards/arm/stm32l4/nucleo-l432kc/src/CMakeLists.txt +++ b/boards/arm/stm32l4/nucleo-l432kc/src/CMakeLists.txt @@ -36,11 +36,11 @@ if(CONFIG_DEV_GPIO) list(APPEND SRCS stm32_gpio.c) endif() -if(CONFIG_STM32L4_ADC) +if(CONFIG_STM32_ADC) list(APPEND SRCS stm32_adc.c) endif() -if(CONFIG_STM32L4_DAC) +if(CONFIG_STM32_DAC) list(APPEND SRCS stm32_dac.c) endif() diff --git a/boards/arm/stm32l4/nucleo-l432kc/src/Make.defs b/boards/arm/stm32l4/nucleo-l432kc/src/Make.defs new file mode 100644 index 0000000000000..2cccd3b3d3c84 --- /dev/null +++ b/boards/arm/stm32l4/nucleo-l432kc/src/Make.defs @@ -0,0 +1,105 @@ +############################################################################ +# boards/arm/stm32l4/nucleo-l432kc/src/Makefile +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +CSRCS = stm32_boot.c stm32_bringup.c stm32_spi.c + +ifeq ($(CONFIG_ARCH_LEDS),y) +CSRCS += stm32_autoleds.c +else +CSRCS += stm32_userleds.c +endif + +ifeq ($(CONFIG_ARCH_BUTTONS),y) +CSRCS += stm32_buttons.c +endif + +ifeq ($(CONFIG_DEV_GPIO),y) + CSRCS += stm32_gpio.c +endif + +ifeq ($(CONFIG_STM32_ADC),y) +CSRCS += stm32_adc.c +endif + +ifeq ($(CONFIG_STM32_DAC),y) +CSRCS += stm32_dac.c +endif + +ifeq ($(CONFIG_DAC7571),y) +CSRCS += stm32_dac7571.c +endif + +ifeq ($(CONFIG_MTD_AT45DB),y) +CSRCS += stm32_at45db.c +endif + +ifeq ($(CONFIG_SENSORS_INA226),y) +CSRCS += stm32_ina226.c +endif + +ifeq ($(CONFIG_SENSORS_INA219),y) +CSRCS += stm32_ina219.c +endif + +ifeq ($(CONFIG_SENSORS_QENCODER),y) +CSRCS += stm32_qencoder.c +endif + +ifeq ($(CONFIG_PWM),y) +CSRCS += stm32_pwm.c +endif + +ifeq ($(CONFIG_SENSORS_ZEROCROSS),y) + CSRCS += stm32_zerocross.c +endif + +ifeq ($(CONFIG_TIMER),y) +CSRCS += stm32_timer.c +endif + +ifeq ($(CONFIG_BOARDCTL_IOCTL),y) +CSRCS += stm32_ioctl.c +endif + +ifeq ($(CONFIG_BOARDCTL_UNIQUEID),y) +CSRCS += stm32_uid.c +endif + +ifeq ($(CONFIG_NUCLEOL432KC_SPWM),y) +CSRCS += stm32_spwm.c +endif + +ifeq ($(CONFIG_NUCLEOL432KC_DAC_WGEN),y) +CSRCS += stm32_dac_wgen.c +endif + +ifneq ($(CONFIG_STM32_ETHMAC),y) +ifeq ($(CONFIG_NETDEVICES),y) +CSRCS += stm32_netinit.c +endif +endif + +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32l4/nucleo-l432kc/src/Makefile b/boards/arm/stm32l4/nucleo-l432kc/src/Makefile deleted file mode 100644 index 10e16a6729f53..0000000000000 --- a/boards/arm/stm32l4/nucleo-l432kc/src/Makefile +++ /dev/null @@ -1,103 +0,0 @@ -############################################################################ -# boards/arm/stm32l4/nucleo-l432kc/src/Makefile -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/Make.defs - -CSRCS = stm32_boot.c stm32_bringup.c stm32_spi.c - -ifeq ($(CONFIG_ARCH_LEDS),y) -CSRCS += stm32_autoleds.c -else -CSRCS += stm32_userleds.c -endif - -ifeq ($(CONFIG_ARCH_BUTTONS),y) -CSRCS += stm32_buttons.c -endif - -ifeq ($(CONFIG_DEV_GPIO),y) - CSRCS += stm32_gpio.c -endif - -ifeq ($(CONFIG_STM32L4_ADC),y) -CSRCS += stm32_adc.c -endif - -ifeq ($(CONFIG_STM32L4_DAC),y) -CSRCS += stm32_dac.c -endif - -ifeq ($(CONFIG_DAC7571),y) -CSRCS += stm32_dac7571.c -endif - -ifeq ($(CONFIG_MTD_AT45DB),y) -CSRCS += stm32_at45db.c -endif - -ifeq ($(CONFIG_SENSORS_INA226),y) -CSRCS += stm32_ina226.c -endif - -ifeq ($(CONFIG_SENSORS_INA219),y) -CSRCS += stm32_ina219.c -endif - -ifeq ($(CONFIG_SENSORS_QENCODER),y) -CSRCS += stm32_qencoder.c -endif - -ifeq ($(CONFIG_PWM),y) -CSRCS += stm32_pwm.c -endif - -ifeq ($(CONFIG_SENSORS_ZEROCROSS),y) - CSRCS += stm32_zerocross.c -endif - -ifeq ($(CONFIG_TIMER),y) -CSRCS += stm32_timer.c -endif - -ifeq ($(CONFIG_BOARDCTL_IOCTL),y) -CSRCS += stm32_ioctl.c -endif - -ifeq ($(CONFIG_BOARDCTL_UNIQUEID),y) -CSRCS += stm32_uid.c -endif - -ifeq ($(CONFIG_NUCLEOL432KC_SPWM),y) -CSRCS += stm32_spwm.c -endif - -ifeq ($(CONFIG_NUCLEOL432KC_DAC_WGEN),y) -CSRCS += stm32_dac_wgen.c -endif - -ifneq ($(CONFIG_STM32_ETHMAC),y) -ifeq ($(CONFIG_NETDEVICES),y) -CSRCS += stm32_netinit.c -endif -endif - -include $(TOPDIR)/boards/Board.mk diff --git a/boards/arm/stm32l4/nucleo-l432kc/src/nucleo-l432kc.h b/boards/arm/stm32l4/nucleo-l432kc/src/nucleo-l432kc.h index b9f111e886a93..766d7e6528a73 100644 --- a/boards/arm/stm32l4/nucleo-l432kc/src/nucleo-l432kc.h +++ b/boards/arm/stm32l4/nucleo-l432kc/src/nucleo-l432kc.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32L4_NUCLEO_L432KC_SRC_NUCLEO_L432KC_H -#define __BOARDS_ARM_STM32L4_NUCLEO_L432KC_SRC_NUCLEO_L432KC_H +#ifndef __BOARDS_ARM_STM32_NUCLEO_L432KC_SRC_NUCLEO_L432KC_H +#define __BOARDS_ARM_STM32_NUCLEO_L432KC_SRC_NUCLEO_L432KC_H /**************************************************************************** * Included Files @@ -61,7 +61,7 @@ /* Check if we can support AT45DB FLASH file system */ -#if !defined(CONFIG_STM32L4_SPI1) || !defined(CONFIG_MTD_AT45DB) +#if !defined(CONFIG_STM32_SPI1) || !defined(CONFIG_MTD_AT45DB) # undef HAVE_AT45DB #endif @@ -108,10 +108,10 @@ /* Global driver instances */ -#ifdef CONFIG_STM32L4_SPI1 +#ifdef CONFIG_STM32_SPI1 extern struct spi_dev_s *g_spi1; #endif -#ifdef CONFIG_STM32L4_SPI2 +#ifdef CONFIG_STM32_SPI2 extern struct spi_dev_s *g_spi2; #endif @@ -133,7 +133,7 @@ extern struct spi_dev_s *g_spi2; int stm32_bringup(void); /**************************************************************************** - * Name: stm32l4_gpio_initialize + * Name: stm32_gpio_initialize * * Description: * Initialize GPIO drivers for use with /apps/examples/gpio @@ -141,11 +141,11 @@ int stm32_bringup(void); ****************************************************************************/ #ifdef CONFIG_DEV_GPIO -int stm32l4_gpio_initialize(void); +int stm32_gpio_initialize(void); #endif /**************************************************************************** - * Name: stm32l4_spiregister + * Name: stm32_spiregister * * Description: * Called to register spi character driver of initialized @@ -153,30 +153,30 @@ int stm32l4_gpio_initialize(void); * ****************************************************************************/ -void stm32l4_spiregister(void); +void stm32_spiregister(void); /**************************************************************************** - * Name: stm32l4_spiinitialize + * Name: stm32_spiinitialize * * Description: * Called to configure SPI chip select GPIO pins. * ****************************************************************************/ -void stm32l4_spiinitialize(void); +void stm32_spiinitialize(void); /**************************************************************************** - * Name: stm32l4_usbinitialize + * Name: stm32_usbinitialize * * Description: * Called to setup USB-related GPIO pins. * ****************************************************************************/ -void stm32l4_usbinitialize(void); +void stm32_usbinitialize(void); /**************************************************************************** - * Name: stm32l4_pwm_setup + * Name: stm32_pwm_setup * * Description: * Initialize PWM and register the PWM device. @@ -184,11 +184,11 @@ void stm32l4_usbinitialize(void); ****************************************************************************/ #ifdef CONFIG_PWM -int stm32l4_pwm_setup(void); +int stm32_pwm_setup(void); #endif /**************************************************************************** - * Name: stm32l4_adc_setup + * Name: stm32_adc_setup * * Description: * Initialize ADC and register the ADC driver. @@ -196,11 +196,11 @@ int stm32l4_pwm_setup(void); ****************************************************************************/ #ifdef CONFIG_ADC -int stm32l4_adc_setup(void); +int stm32_adc_setup(void); #endif /**************************************************************************** - * Name: stm32l4_dac_setup + * Name: stm32_dac_setup * * Description: * Initialize DAC and register the DAC driver. @@ -208,7 +208,7 @@ int stm32l4_adc_setup(void); ****************************************************************************/ #ifdef CONFIG_DAC -int stm32l4_dac_setup(void); +int stm32_dac_setup(void); #endif /**************************************************************************** @@ -284,7 +284,7 @@ int board_timer_driver_initialize(const char *devpath, int timer); #endif /**************************************************************************** - * Name: stm32l4_qencoder_initialize + * Name: stm32_qencoder_initialize * * Description: * Initialize and register a qencoder @@ -292,7 +292,7 @@ int board_timer_driver_initialize(const char *devpath, int timer); ****************************************************************************/ #ifdef CONFIG_SENSORS_QENCODER -int stm32l4_qencoder_initialize(const char *devpath, int timer); +int stm32_qencoder_initialize(const char *devpath, int timer); #endif -#endif /* __BOARDS_ARM_STM32L4_NUCLEO_L432KC_SRC_NUCLEO_L432KC_H */ +#endif /* __BOARDS_ARM_STM32_NUCLEO_L432KC_SRC_NUCLEO_L432KC_H */ diff --git a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_adc.c b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_adc.c index e7663aef96171..d1dfcba1bf41e 100644 --- a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_adc.c +++ b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_adc.c @@ -38,7 +38,7 @@ #include "stm32l4_adc.h" #include "nucleo-l432kc.h" -#ifdef CONFIG_STM32L4_ADC1 +#ifdef CONFIG_STM32_ADC1 /**************************************************************************** * Pre-processor Definitions @@ -46,7 +46,7 @@ /* The number of ADC channels in the conversion list */ -#ifdef CONFIG_STM32L4_ADC1_DMA +#ifdef CONFIG_STM32_ADC1_DMA # define ADC1_NCHANNELS 2 #else # define ADC1_NCHANNELS 1 @@ -58,7 +58,7 @@ /* Identifying number of each ADC channel. */ -#ifdef CONFIG_STM32L4_ADC1_DMA +#ifdef CONFIG_STM32_ADC1_DMA static const uint8_t g_adc1_chanlist[ADC1_NCHANNELS] = { @@ -87,7 +87,7 @@ static const uint32_t g_adc1_pinlist[ADC1_NCHANNELS] = GPIO_ADC1_IN11_0 }; -#endif /* CONFIG_STM32L4_ADC1_DMA */ +#endif /* CONFIG_STM32_ADC1_DMA */ /**************************************************************************** * Private Functions @@ -98,14 +98,14 @@ static const uint32_t g_adc1_pinlist[ADC1_NCHANNELS] = ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_adc_setup + * Name: stm32_adc_setup * * Description: * Initialize ADC and register the ADC driver. * ****************************************************************************/ -int stm32l4_adc_setup(void) +int stm32_adc_setup(void) { struct adc_dev_s *adc; int ret; @@ -115,12 +115,12 @@ int stm32l4_adc_setup(void) for (i = 0; i < ADC1_NCHANNELS; i++) { - stm32l4_configgpio(g_adc1_pinlist[i]); + stm32_configgpio(g_adc1_pinlist[i]); } - /* Call stm32l4_adc_initialize() to get an instance of the ADC interface */ + /* Call stm32_adc_initialize() to get an instance of the ADC interface */ - adc = stm32l4_adc_initialize(1, g_adc1_chanlist, ADC1_NCHANNELS); + adc = stm32_adc_initialize(1, g_adc1_chanlist, ADC1_NCHANNELS); if (adc == NULL) { aerr("ERROR: Failed to get ADC interface\n"); @@ -139,4 +139,4 @@ int stm32l4_adc_setup(void) return OK; } -#endif /* CONFIG_STM32L4_ADC1 */ +#endif /* CONFIG_STM32_ADC1 */ diff --git a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_at45db.c b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_at45db.c index 9accb5984f080..6c3c1d65e23d4 100644 --- a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_at45db.c +++ b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_at45db.c @@ -42,7 +42,7 @@ * Pre-processor Definitions ****************************************************************************/ -#ifndef CONFIG_STM32L4_SPI1 +#ifndef CONFIG_STM32_SPI1 # error "AT45DB driver requires CONFIG_STM32_SPI1 to be enabled" #endif @@ -79,7 +79,7 @@ int stm32_at45dbinitialize(int minor) finfo("INFO: Initializing AT45DB\n"); - spi = stm32l4_spibus_initialize(AT45DB_SPI_PORT); + spi = stm32_spibus_initialize(AT45DB_SPI_PORT); if (spi == NULL) { ferr("ERROR: Failed to initialize SPI port %d\n", AT45DB_SPI_PORT); diff --git a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_autoleds.c b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_autoleds.c index 1631395cab793..c2f3cff13fb56 100644 --- a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_autoleds.c +++ b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_autoleds.c @@ -35,7 +35,7 @@ #include "chip.h" #include "arm_internal.h" -#include "stm32l4.h" +#include "stm32.h" #include "nucleo-l432kc.h" #ifdef CONFIG_ARCH_LEDS @@ -52,7 +52,7 @@ void board_autoled_initialize(void) { /* Configure LD3 GPIO for output */ - stm32l4_configgpio(GPIO_LD3); + stm32_configgpio(GPIO_LD3); } /**************************************************************************** @@ -63,7 +63,7 @@ void board_autoled_on(int led) { if (led == 1) { - stm32l4_gpiowrite(GPIO_LD3, true); + stm32_gpiowrite(GPIO_LD3, true); } } @@ -75,7 +75,7 @@ void board_autoled_off(int led) { if (led == 1) { - stm32l4_gpiowrite(GPIO_LD3, false); + stm32_gpiowrite(GPIO_LD3, false); } } diff --git a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_boot.c b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_boot.c index 1241ab202ffcd..a370c0e67b145 100644 --- a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_boot.c +++ b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_boot.c @@ -50,7 +50,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_board_initialize + * Name: stm32_board_initialize * * Description: * All STM32L4 architectures must provide the following entry point. @@ -60,7 +60,7 @@ * ****************************************************************************/ -void stm32l4_board_initialize(void) +void stm32_board_initialize(void) { /* Configure on-board LEDs if LED support has been selected. */ @@ -69,21 +69,21 @@ void stm32l4_board_initialize(void) #endif /* Configure SPI chip selects if 1) SP2 is not disabled, and 2) the weak - * function stm32l4_spiinitialize() has been brought into the link. + * function stm32_spiinitialize() has been brought into the link. */ -#if defined(CONFIG_STM32L4_SPI1) || defined(CONFIG_STM32L4_SPI2) || \ - defined(CONFIG_STM32L4_SPI3) - stm32l4_spiinitialize(); +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || \ + defined(CONFIG_STM32_SPI3) + stm32_spiinitialize(); #endif /* Initialize USB is 1) USBDEV is selected, 2) the USB controller is not - * disabled, and 3) the weak function stm32l4_usbinitialize() has been + * disabled, and 3) the weak function stm32_usbinitialize() has been * brought into the build. */ -#if defined(CONFIG_USBDEV) && defined(CONFIG_STM32L4_USB) - stm32l4_usbinitialize(); +#if defined(CONFIG_USBDEV) && defined(CONFIG_STM32_USB) + stm32_usbinitialize(); #endif } diff --git a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_bringup.c b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_bringup.c index d8dead5bc11cc..48ac6fff613b7 100644 --- a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_bringup.c +++ b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_bringup.c @@ -40,7 +40,7 @@ #include #include -#include +#include #include #include @@ -58,7 +58,7 @@ ****************************************************************************/ #undef HAVE_I2C_DRIVER -#if (defined(CONFIG_STM32L4_I2C1) || defined(CONFIG_STM32L4_I2C3)) && defined(CONFIG_I2C_DRIVER) +#if (defined(CONFIG_STM32_I2C1) || defined(CONFIG_STM32_I2C3)) && defined(CONFIG_I2C_DRIVER) # define HAVE_I2C_DRIVER 1 #endif @@ -82,10 +82,10 @@ int stm32_bringup(void) #ifdef HAVE_RTC_DRIVER struct rtc_lowerhalf_s *rtclower; #endif -#ifdef CONFIG_STM32L4_I2C1 +#ifdef CONFIG_STM32_I2C1 struct i2c_master_s *i2c1; #endif -#ifdef CONFIG_STM32L4_I2C3 +#ifdef CONFIG_STM32_I2C3 struct i2c_master_s *i2c3; #endif #ifdef CONFIG_SENSORS_QENCODER @@ -119,7 +119,7 @@ int stm32_bringup(void) #endif #ifdef CONFIG_DEV_GPIO - ret = stm32l4_gpio_initialize(); + ret = stm32_gpio_initialize(); if (ret < 0) { syslog(LOG_ERR, "Failed to initialize GPIO Driver: %d\n", ret); @@ -130,7 +130,7 @@ int stm32_bringup(void) #ifdef HAVE_RTC_DRIVER /* Instantiate the STM32L4 lower-half RTC driver */ - rtclower = stm32l4_rtc_lowerhalf(); + rtclower = stm32_rtc_lowerhalf(); if (!rtclower) { serr("ERROR: Failed to instantiate the RTC lower-half driver\n"); @@ -151,10 +151,10 @@ int stm32_bringup(void) } #endif -#ifdef CONFIG_STM32L4_I2C1 +#ifdef CONFIG_STM32_I2C1 /* Get the I2C lower half instance */ - i2c1 = stm32l4_i2cbus_initialize(1); + i2c1 = stm32_i2cbus_initialize(1); if (i2c1 == NULL) { i2cerr("ERROR: Initialize I2C1: %d\n", ret); @@ -171,10 +171,10 @@ int stm32_bringup(void) } #endif -#ifdef CONFIG_STM32L4_I2C3 +#ifdef CONFIG_STM32_I2C3 /* Get the I2C lower half instance */ - i2c3 = stm32l4_i2cbus_initialize(3); + i2c3 = stm32_i2cbus_initialize(3); if (i2c3 == NULL) { i2cerr("ERROR: Initialize I2C3: %d\n", ret); @@ -192,7 +192,7 @@ int stm32_bringup(void) #endif #ifdef CONFIG_SPI_DRIVER - stm32l4_spiregister(); + stm32_spiregister(); /* If called it during board_init, * registering failed due to heap doesn't be initialized yet. */ @@ -213,30 +213,30 @@ int stm32_bringup(void) #ifdef CONFIG_PWM /* Initialize PWM and register the PWM device. */ - ret = stm32l4_pwm_setup(); + ret = stm32_pwm_setup(); if (ret < 0) { - syslog(LOG_ERR, "ERROR: stm32l4_pwm_setup() failed: %d\n", ret); + syslog(LOG_ERR, "ERROR: stm32_pwm_setup() failed: %d\n", ret); } #endif -#ifdef CONFIG_STM32L4_ADC +#ifdef CONFIG_STM32_ADC /* Initialize ADC and register the ADC driver. */ - ret = stm32l4_adc_setup(); + ret = stm32_adc_setup(); if (ret < 0) { - syslog(LOG_ERR, "ERROR: stm32l4_adc_setup failed: %d\n", ret); + syslog(LOG_ERR, "ERROR: stm32_adc_setup failed: %d\n", ret); } #endif -#ifdef CONFIG_STM32L4_DAC +#ifdef CONFIG_STM32_DAC /* Initialize DAC and register the DAC driver. */ - ret = stm32l4_dac_setup(); + ret = stm32_dac_setup(); if (ret < 0) { - syslog(LOG_ERR, "ERROR: stm32l4_dac_setup failed: %d\n", ret); + syslog(LOG_ERR, "ERROR: stm32_dac_setup failed: %d\n", ret); } #endif @@ -298,9 +298,9 @@ int stm32_bringup(void) index = 0; -#ifdef CONFIG_STM32L4_TIM1_QE +#ifdef CONFIG_STM32_TIM1_QE snprintf(buf, sizeof(buf), "/dev/qe%d", index++); - ret = stm32l4_qencoder_initialize(buf, 1); + ret = stm32_qencoder_initialize(buf, 1); if (ret != OK) { syslog(LOG_ERR, "ERROR: Failed to register the qencoder: %d\n", @@ -309,9 +309,9 @@ int stm32_bringup(void) } #endif -#ifdef CONFIG_STM32L4_TIM2_QE +#ifdef CONFIG_STM32_TIM2_QE snprintf(buf, sizeof(buf), "/dev/qe%d", index++); - ret = stm32l4_qencoder_initialize(buf, 2); + ret = stm32_qencoder_initialize(buf, 2); if (ret != OK) { syslog(LOG_ERR, "ERROR: Failed to register the qencoder: %d\n", @@ -320,9 +320,9 @@ int stm32_bringup(void) } #endif -#ifdef CONFIG_STM32L4_TIM3_QE +#ifdef CONFIG_STM32_TIM3_QE snprintf(buf, sizeof(buf), "/dev/qe%d", index++); - ret = stm32l4_qencoder_initialize(buf, 3); + ret = stm32_qencoder_initialize(buf, 3); if (ret != OK) { syslog(LOG_ERR, "ERROR: Failed to register the qencoder: %d\n", @@ -331,9 +331,9 @@ int stm32_bringup(void) } #endif -#ifdef CONFIG_STM32L4_TIM4_QE +#ifdef CONFIG_STM32_TIM4_QE snprintf(buf, sizeof(buf), "/dev/qe%d", index++); - ret = stm32l4_qencoder_initialize(buf, 4); + ret = stm32_qencoder_initialize(buf, 4); if (ret != OK) { syslog(LOG_ERR, "ERROR: Failed to register the qencoder: %d\n", @@ -342,9 +342,9 @@ int stm32_bringup(void) } #endif -#ifdef CONFIG_STM32L4_TIM5_QE +#ifdef CONFIG_STM32_TIM5_QE snprintf(buf, sizeof(buf), "/dev/qe%d", index++); - ret = stm32l4_qencoder_initialize(buf, 5); + ret = stm32_qencoder_initialize(buf, 5); if (ret != OK) { syslog(LOG_ERR, "ERROR: Failed to register the qencoder: %d\n", @@ -353,9 +353,9 @@ int stm32_bringup(void) } #endif -#ifdef CONFIG_STM32L4_TIM8_QE +#ifdef CONFIG_STM32_TIM8_QE snprintf(buf, sizeof(buf), "/dev/qe%d", index++); - ret = stm32l4_qencoder_initialize(buf, 8); + ret = stm32_qencoder_initialize(buf, 8); if (ret != OK) { syslog(LOG_ERR, "ERROR: Failed to register the qencoder: %d\n", diff --git a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_dac.c b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_dac.c index 4e57f555eb2ca..fd48f855ab3b5 100644 --- a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_dac.c +++ b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_dac.c @@ -41,7 +41,7 @@ * Private Data ****************************************************************************/ -#ifdef CONFIG_STM32L4_DAC1 +#ifdef CONFIG_STM32_DAC1 static struct dac_dev_s *g_dac; #endif @@ -50,19 +50,19 @@ static struct dac_dev_s *g_dac; ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_dac_setup + * Name: stm32_dac_setup ****************************************************************************/ -int stm32l4_dac_setup(void) +int stm32_dac_setup(void) { static bool initialized = false; if (!initialized) { -#ifdef CONFIG_STM32L4_DAC1 +#ifdef CONFIG_STM32_DAC1 int ret; - g_dac = stm32l4_dacinitialize(0); + g_dac = stm32_dacinitialize(0); if (g_dac == NULL) { aerr("ERROR: Failed to get DAC1 interface\n"); diff --git a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_dac7571.c b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_dac7571.c index a62e824fbc014..48cabb1d468bd 100644 --- a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_dac7571.c +++ b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_dac7571.c @@ -36,9 +36,9 @@ #include #include "chip.h" -#include +#include -#if defined(CONFIG_I2C) && defined(CONFIG_STM32L4_I2C1) && \ +#if defined(CONFIG_I2C) && defined(CONFIG_STM32_I2C1) && \ defined(CONFIG_DAC7571) /**************************************************************************** @@ -80,12 +80,12 @@ int stm32_dac7571initialize(const char *devpath) /* Configure D4(PA5) and D5(PA6) as input floating */ - stm32l4_configgpio(GPIO_I2C1_D4); - stm32l4_configgpio(GPIO_I2C1_D5); + stm32_configgpio(GPIO_I2C1_D4); + stm32_configgpio(GPIO_I2C1_D5); /* Get an instance of the I2C1 interface */ - i2c = stm32l4_i2cbus_initialize(1); + i2c = stm32_i2cbus_initialize(1); if (!i2c) { return -ENODEV; @@ -110,7 +110,7 @@ int stm32_dac7571initialize(const char *devpath) return OK; error: - stm32l4_i2cbus_uninitialize(i2c); + stm32_i2cbus_uninitialize(i2c); return ret; } diff --git a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_dac_wgen.c b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_dac_wgen.c index 32d73de778359..140d8488f45b3 100644 --- a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_dac_wgen.c +++ b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_dac_wgen.c @@ -66,19 +66,19 @@ # error "CONFIG_DAC is required" #endif -#ifndef CONFIG_STM32L4_DAC1 -# error "CONFIG_STM32L4_DAC1 is required" +#ifndef CONFIG_STM32_DAC1 +# error "CONFIG_STM32_DAC1 is required" #endif -#ifndef CONFIG_STM32L4_DAC_LL_OPS -# error "CONFIG_STM32L4_DAC_LL_OPS is required" +#ifndef CONFIG_STM32_DAC_LL_OPS +# error "CONFIG_STM32_DAC_LL_OPS is required" #endif -#ifndef CONFIG_STM32L4_DAC1_DMA -# error "CONFIG_STM32L4_DAC1_DMA is required" +#ifndef CONFIG_STM32_DAC1_DMA +# error "CONFIG_STM32_DAC1_DMA is required" #endif -#if (CONFIG_STM32L4_DAC1_DMA_BUFFER_SIZE < CONFIG_NUCLEOL432KC_DAC_WGEN_SAMPLES) +#if (CONFIG_STM32_DAC1_DMA_BUFFER_SIZE < CONFIG_NUCLEOL432KC_DAC_WGEN_SAMPLES) # error "DMA buffer size should be equal or greater than the number of samples." #endif @@ -104,7 +104,7 @@ struct dac_wgen_s static struct dac_wgen_s g_dac_wgen = { .dac = NULL, - .dac_dmabuffer = stm32l4_dac1_dmabuffer, + .dac_dmabuffer = stm32_dac1_dmabuffer, .samples = CONFIG_NUCLEOL432KC_DAC_WGEN_SAMPLES, .waveform_freq = ((float)CONFIG_NUCLEOL432KC_DAC_WGEN_FREQ) }; @@ -199,7 +199,7 @@ int dac_wgen_setup(struct dac_wgen_s *dac_wgen) int ret = OK; - dac = stm32l4_dacinitialize(0); + dac = stm32_dacinitialize(0); if (dac == NULL) { syslog(LOG_ERR, "Failed to get DAC interface\n"); diff --git a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_gpio.c b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_gpio.c index 6b762ea218626..9164fd1db317f 100644 --- a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_gpio.c +++ b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_gpio.c @@ -151,7 +151,7 @@ static int gpin_read(struct gpio_dev_s *dev, bool *value) DEBUGASSERT(stm32gpio->id < BOARD_NGPIOIN); gpioinfo("Reading...\n"); - *value = stm32l4_gpioread(g_gpioinputs[stm32gpio->id]); + *value = stm32_gpioread(g_gpioinputs[stm32gpio->id]); return OK; } #endif @@ -165,7 +165,7 @@ static int gpout_read(struct gpio_dev_s *dev, bool *value) DEBUGASSERT(stm32gpio->id < BOARD_NGPIOOUT); gpioinfo("Reading...\n"); - *value = stm32l4_gpioread(g_gpiooutputs[stm32gpio->id]); + *value = stm32_gpioread(g_gpiooutputs[stm32gpio->id]); return OK; } @@ -177,7 +177,7 @@ static int gpout_write(struct gpio_dev_s *dev, bool value) DEBUGASSERT(stm32gpio->id < BOARD_NGPIOOUT); gpioinfo("Writing %d\n", (int)value); - stm32l4_gpiowrite(g_gpiooutputs[stm32gpio->id], value); + stm32_gpiowrite(g_gpiooutputs[stm32gpio->id], value); return OK; } #endif @@ -205,7 +205,7 @@ static int gpint_read(struct gpio_dev_s *dev, bool *value) DEBUGASSERT(stm32gpint->stm32gpio.id < BOARD_NGPIOINT); gpioinfo("Reading int pin...\n"); - *value = stm32l4_gpioread(g_gpiointinputs[stm32gpint->stm32gpio.id]); + *value = stm32_gpioread(g_gpiointinputs[stm32gpint->stm32gpio.id]); return OK; } @@ -219,7 +219,7 @@ static int gpint_attach(struct gpio_dev_s *dev, /* Make sure the interrupt is disabled */ - stm32l4_gpiosetevent(g_gpiointinputs[stm32gpint->stm32gpio.id], false, + stm32_gpiosetevent(g_gpiointinputs[stm32gpint->stm32gpio.id], false, false, false, NULL, NULL); gpioinfo("Attach %p\n", callback); @@ -240,7 +240,7 @@ static int gpint_enable(struct gpio_dev_s *dev, bool enable) /* Configure the interrupt for rising edge */ - stm32l4_gpiosetevent(g_gpiointinputs[stm32gpint->stm32gpio.id], + stm32_gpiosetevent(g_gpiointinputs[stm32gpint->stm32gpio.id], true, false, false, stm32gpio_interrupt, &g_gpint[stm32gpint->stm32gpio.id]); } @@ -248,7 +248,7 @@ static int gpint_enable(struct gpio_dev_s *dev, bool enable) else { gpioinfo("Disable the interrupt\n"); - stm32l4_gpiosetevent(g_gpiointinputs[stm32gpint->stm32gpio.id], + stm32_gpiosetevent(g_gpiointinputs[stm32gpint->stm32gpio.id], false, false, false, NULL, NULL); } @@ -268,7 +268,7 @@ static int gpint_enable(struct gpio_dev_s *dev, bool enable) * ****************************************************************************/ -int stm32l4_gpio_initialize(void) +int stm32_gpio_initialize(void) { int i; int pincount = 0; @@ -285,7 +285,7 @@ int stm32l4_gpio_initialize(void) /* Configure the pin that will be used as input */ - stm32l4_configgpio(g_gpioinputs[i]); + stm32_configgpio(g_gpioinputs[i]); pincount++; } @@ -303,8 +303,8 @@ int stm32l4_gpio_initialize(void) /* Configure the pin that will be used as output */ - stm32l4_gpiowrite(g_gpiooutputs[i], 0); - stm32l4_configgpio(g_gpiooutputs[i]); + stm32_gpiowrite(g_gpiooutputs[i], 0); + stm32_configgpio(g_gpiooutputs[i]); pincount++; } @@ -322,7 +322,7 @@ int stm32l4_gpio_initialize(void) /* Configure the pin that will be used as interrupt input */ - stm32l4_configgpio(g_gpiointinputs[i]); + stm32_configgpio(g_gpiointinputs[i]); pincount++; } diff --git a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_ina219.c b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_ina219.c index 7a0ca30e193cb..89946981ecefe 100644 --- a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_ina219.c +++ b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_ina219.c @@ -36,9 +36,9 @@ #include #include "chip.h" -#include +#include -#if defined(CONFIG_I2C) && defined(CONFIG_STM32L4_I2C1) && \ +#if defined(CONFIG_I2C) && defined(CONFIG_STM32_I2C1) && \ defined(CONFIG_SENSORS_INA219) /**************************************************************************** @@ -84,12 +84,12 @@ int stm32_ina219initialize(const char *devpath) /* Configure D4(PA5) and D5(PA6) as input floating */ - stm32l4_configgpio(GPIO_I2C1_D4); - stm32l4_configgpio(GPIO_I2C1_D5); + stm32_configgpio(GPIO_I2C1_D4); + stm32_configgpio(GPIO_I2C1_D5); /* Get an instance of the I2C1 interface */ - i2c = stm32l4_i2cbus_initialize(1); + i2c = stm32_i2cbus_initialize(1); if (!i2c) { return -ENODEV; @@ -114,7 +114,7 @@ int stm32_ina219initialize(const char *devpath) return OK; error: - stm32l4_i2cbus_uninitialize(i2c); + stm32_i2cbus_uninitialize(i2c); return ret; } diff --git a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_ina226.c b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_ina226.c index cfa9af0ae10ac..49be6a531d5b3 100644 --- a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_ina226.c +++ b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_ina226.c @@ -36,9 +36,9 @@ #include #include "chip.h" -#include +#include -#if defined(CONFIG_I2C) && defined(CONFIG_STM32L4_I2C1) && \ +#if defined(CONFIG_I2C) && defined(CONFIG_STM32_I2C1) && \ defined(CONFIG_SENSORS_INA226) /**************************************************************************** @@ -84,12 +84,12 @@ int stm32_ina226initialize(const char *devpath) /* Configure A4(PA5) and A5(PA6) as input floating */ - stm32l4_configgpio(GPIO_I2C1_A4); - stm32l4_configgpio(GPIO_I2C1_A5); + stm32_configgpio(GPIO_I2C1_A4); + stm32_configgpio(GPIO_I2C1_A5); /* Get an instance of the I2C1 interface */ - i2c = stm32l4_i2cbus_initialize(1); + i2c = stm32_i2cbus_initialize(1); if (!i2c) { return -ENODEV; @@ -114,7 +114,7 @@ int stm32_ina226initialize(const char *devpath) return OK; error: - stm32l4_i2cbus_uninitialize(i2c); + stm32_i2cbus_uninitialize(i2c); return ret; } diff --git a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_pwm.c b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_pwm.c index fedfb03350873..6997424c27566 100644 --- a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_pwm.c +++ b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_pwm.c @@ -60,14 +60,14 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_pwm_setup + * Name: stm32_pwm_setup * * Description: * Initialize PWM and register the PWM device. * ****************************************************************************/ -int stm32l4_pwm_setup(void) +int stm32_pwm_setup(void) { static bool initialized = false; struct pwm_lowerhalf_s *pwm; @@ -77,7 +77,7 @@ int stm32l4_pwm_setup(void) if (!initialized) { - /* Call stm32l4_pwminitialize() to get an instance of the PWM interface + /* Call stm32_pwminitialize() to get an instance of the PWM interface */ /* PWM @@ -87,8 +87,8 @@ int stm32l4_pwm_setup(void) * (see board.h). Let's figure out which the user has configured. */ -#if defined(CONFIG_STM32L4_TIM1_PWM) - pwm = stm32l4_pwminitialize(1); +#if defined(CONFIG_STM32_TIM1_PWM) + pwm = stm32_pwminitialize(1); if (!pwm) { aerr("ERROR: Failed to get the STM32L4 PWM lower half\n"); @@ -105,8 +105,8 @@ int stm32l4_pwm_setup(void) } #endif -#if defined(CONFIG_STM32L4_TIM2_PWM) - pwm = stm32l4_pwminitialize(2); +#if defined(CONFIG_STM32_TIM2_PWM) + pwm = stm32_pwminitialize(2); if (!pwm) { aerr("ERROR: Failed to get the STM32L4 PWM lower half\n"); @@ -123,8 +123,8 @@ int stm32l4_pwm_setup(void) } #endif -#if defined(CONFIG_STM32L4_TIM15_PWM) - pwm = stm32l4_pwminitialize(15); +#if defined(CONFIG_STM32_TIM15_PWM) + pwm = stm32_pwminitialize(15); if (!pwm) { aerr("ERROR: Failed to get the STM32L4 PWM lower half\n"); @@ -141,8 +141,8 @@ int stm32l4_pwm_setup(void) } #endif -#if defined(CONFIG_STM32L4_TIM16_PWM) - pwm = stm32l4_pwminitialize(16); +#if defined(CONFIG_STM32_TIM16_PWM) + pwm = stm32_pwminitialize(16); if (!pwm) { aerr("ERROR: Failed to get the STM32L4 PWM lower half\n"); @@ -159,8 +159,8 @@ int stm32l4_pwm_setup(void) } #endif -#if defined(CONFIG_STM32L4_LPTIM1_PWM) - pwm = stm32l4_lp_pwminitialize(1); +#if defined(CONFIG_STM32_LPTIM1_PWM) + pwm = stm32_lp_pwminitialize(1); if (!pwm) { aerr("ERROR: Failed to get the STM32L4 PWM lower half\n"); @@ -177,8 +177,8 @@ int stm32l4_pwm_setup(void) } #endif -#if defined(CONFIG_STM32L4_LPTIM2_PWM) - pwm = stm32l4_lp_pwminitialize(2); +#if defined(CONFIG_STM32_LPTIM2_PWM) + pwm = stm32_lp_pwminitialize(2); if (!pwm) { aerr("ERROR: Failed to get the STM32L4 PWM lower half\n"); diff --git a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_qencoder.c b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_qencoder.c index 1a02e18bb8cf8..311955dee90bb 100644 --- a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_qencoder.c +++ b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_qencoder.c @@ -50,17 +50,17 @@ * ****************************************************************************/ -int stm32l4_qencoder_initialize(const char *devpath, int timer) +int stm32_qencoder_initialize(const char *devpath, int timer) { int ret; /* Initialize a quadrature encoder interface. */ sninfo("Initializing the quadrature encoder using TIM%d\n", timer); - ret = stm32l4_qeinitialize(devpath, timer); + ret = stm32_qeinitialize(devpath, timer); if (ret < 0) { - snerr("ERROR: stm32l4_qeinitialize failed: %d\n", ret); + snerr("ERROR: stm32_qeinitialize failed: %d\n", ret); } return ret; diff --git a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_spi.c b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_spi.c index 421a2497b2c3c..f52a6b7bbbfb2 100644 --- a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_spi.c +++ b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_spi.c @@ -36,11 +36,11 @@ #include #include "chip.h" -#include +#include #include "nucleo-l432kc.h" -#if defined(CONFIG_STM32L4_SPI1) || defined(CONFIG_STM32L4_SPI2) +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) /**************************************************************************** * Public Data @@ -48,10 +48,10 @@ /* Global driver instances */ -#ifdef CONFIG_STM32L4_SPI1 +#ifdef CONFIG_STM32_SPI1 struct spi_dev_s *g_spi1; #endif -#ifdef CONFIG_STM32L4_SPI2 +#ifdef CONFIG_STM32_SPI2 struct spi_dev_s *g_spi2; #endif @@ -60,7 +60,7 @@ struct spi_dev_s *g_spi2; ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_spiregister + * Name: stm32_spiregister * * Description: * Called to register spi character driver of @@ -68,9 +68,9 @@ struct spi_dev_s *g_spi2; * ****************************************************************************/ -void stm32l4_spiregister(void) +void stm32_spiregister(void) { -#ifdef CONFIG_STM32L4_SPI1 +#ifdef CONFIG_STM32_SPI1 int ret = spi_register(g_spi1, 1); if (ret < 0) { @@ -78,7 +78,7 @@ void stm32l4_spiregister(void) } #endif -#ifdef CONFIG_STM32L4_SPI2 +#ifdef CONFIG_STM32_SPI2 int ret = spi_register(g_spi2, 2); if (ret < 0) { @@ -88,7 +88,7 @@ void stm32l4_spiregister(void) } /**************************************************************************** - * Name: stm32l4_spiinitialize + * Name: stm32_spiinitialize * * Description: * Called to configure SPI chip select GPIO pins for the Nucleo-L432KC @@ -96,12 +96,12 @@ void stm32l4_spiregister(void) * ****************************************************************************/ -void stm32l4_spiinitialize(void) +void stm32_spiinitialize(void) { -#ifdef CONFIG_STM32L4_SPI1 +#ifdef CONFIG_STM32_SPI1 /* Configure SPI1-based devices */ - g_spi1 = stm32l4_spibus_initialize(1); + g_spi1 = stm32_spibus_initialize(1); if (!g_spi1) { spierr("ERROR: FAILED to initialize SPI port 1\n"); @@ -114,14 +114,14 @@ void stm32l4_spiinitialize(void) /* Setup CS, EN & IRQ line IOs */ #ifdef CONFIG_MTD_AT45DB - stm32l4_configgpio(AT45DB_SPI1_CS); /* FLASH chip select */ + stm32_configgpio(AT45DB_SPI1_CS); /* FLASH chip select */ #endif #endif -#ifdef CONFIG_STM32L4_SPI2 +#ifdef CONFIG_STM32_SPI2 /* Configure SPI2-based devices */ - g_spi2 = stm32l4_spibus_initialize(2); + g_spi2 = stm32_spibus_initialize(2); if (!g_spi2) { spierr("ERROR: FAILED to initialize SPI port 2\n"); @@ -136,19 +136,19 @@ void stm32l4_spiinitialize(void) } /**************************************************************************** - * Name: stm32l4_spi1/2select and stm32l4_spi1/2status + * Name: stm32_spi1/2select and stm32_spi1/2status * * Description: - * The external functions, stm32l4_spi1/2select and stm32l4_spi1/2status + * The external functions, stm32_spi1/2select and stm32_spi1/2status * must be provided by board-specific logic. They are implementations of * the select and status methods of the SPI interface defined by struct * spi_ops_s (see include/nuttx/spi/spi.h). All other methods (including * up_spiinitialize()) are provided by common STM32 logic. To use this * common SPI logic on your board: * - * 1. Provide logic in stm32l4_board_initialize() to configure SPI chip + * 1. Provide logic in stm32_board_initialize() to configure SPI chip * select pins. - * 2. Provide stm32l4_spi1/2select() and stm32l4_spi1/2status() functions + * 2. Provide stm32_spi1/2select() and stm32_spi1/2status() functions * in your board-specific logic. These functions will perform chip * selection and status operations using GPIOs in the way your board is * configured. @@ -161,8 +161,8 @@ void stm32l4_spiinitialize(void) * ****************************************************************************/ -#ifdef CONFIG_STM32L4_SPI1 -void stm32l4_spi1select(struct spi_dev_s *dev, uint32_t devid, +#ifdef CONFIG_STM32_SPI1 +void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, bool selected) { spiinfo("devid: %08X CS: %s\n", (int)devid, @@ -171,33 +171,33 @@ void stm32l4_spi1select(struct spi_dev_s *dev, uint32_t devid, #ifdef CONFIG_MTD_AT45DB if (devid == SPIDEV_FLASH(0)) { - stm32l4_gpiowrite(AT45DB_SPI1_CS, !selected); + stm32_gpiowrite(AT45DB_SPI1_CS, !selected); } #endif } -uint8_t stm32l4_spi1status(struct spi_dev_s *dev, uint32_t devid) +uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) { return 0; } #endif -#ifdef CONFIG_STM32L4_SPI2 -void stm32l4_spi2select(struct spi_dev_s *dev, uint32_t devid, +#ifdef CONFIG_STM32_SPI2 +void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid, bool selected) { spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); } -uint8_t stm32l4_spi2status(struct spi_dev_s *dev, uint32_t devid) +uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) { return 0; } #endif /**************************************************************************** - * Name: stm32l4_spi1cmddata + * Name: stm32_spi1cmddata * * Description: * Set or clear the SH1101A A0 or SD1306 D/C n bit to select data (true) @@ -220,19 +220,19 @@ uint8_t stm32l4_spi2status(struct spi_dev_s *dev, uint32_t devid) ****************************************************************************/ #ifdef CONFIG_SPI_CMDDATA -#ifdef CONFIG_STM32L4_SPI1 -int stm32l4_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) +#ifdef CONFIG_STM32_SPI1 +int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return OK; } #endif -#ifdef CONFIG_STM32L4_SPI2 -int stm32l4_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) +#ifdef CONFIG_STM32_SPI2 +int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return OK; } #endif #endif /* CONFIG_SPI_CMDDATA */ -#endif /* CONFIG_STM32L4_SPI1 || CONFIG_STM32L4_SPI2 */ +#endif /* CONFIG_STM32_SPI1 || CONFIG_STM32_SPI2 */ diff --git a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_spwm.c b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_spwm.c index 63bcbcb47b980..c1842f4e555f5 100644 --- a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_spwm.c +++ b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_spwm.c @@ -81,10 +81,10 @@ /* Phase 1 is TIM1 CH1 */ # if CONFIG_NUCLEOL432KC_SPWM_PHASE_NUM > 0 -# ifndef CONFIG_STM32L4_TIM1_CH1OUT +# ifndef CONFIG_STM32_TIM1_CH1OUT # error # endif -# ifndef CONFIG_STM32L4_TIM6 +# ifndef CONFIG_STM32_TIM6 # error # endif # endif @@ -92,7 +92,7 @@ /* Phase 2 is TIM1 CH2 */ # if CONFIG_NUCLEOL432KC_SPWM_PHASE_NUM > 1 -# ifndef CONFIG_STM32L4_TIM1_CH2OUT +# ifndef CONFIG_STM32_TIM1_CH2OUT # error # endif # endif @@ -100,7 +100,7 @@ /* Phase 3 is TIM1 CH3 */ # if CONFIG_NUCLEOL432KC_SPWM_PHASE_NUM > 2 -# ifndef CONFIG_STM32L4_TIM1_CH3OUT +# ifndef CONFIG_STM32_TIM1_CH3OUT # error # endif # endif @@ -108,7 +108,7 @@ /* Phase 4 is TIM1 CH4 */ # if CONFIG_NUCLEOL432KC_SPWM_PHASE_NUM > 3 -# ifndef CONFIG_STM32L4_TIM1_CH4OUT +# ifndef CONFIG_STM32_TIM1_CH4OUT # error # endif # endif @@ -138,9 +138,9 @@ struct spwm_s { - struct stm32l4_pwm_dev_s *pwm; + struct stm32_pwm_dev_s *pwm; #ifdef CONFIG_NUCLEOL432KC_SPWM_USE_TIM1 - struct stm32l4_tim_dev_s *tim; + struct stm32_tim_dev_s *tim; #endif float waveform[SAMPLES_NUM]; /* Waveform samples */ float phase_step; /* Waveform phase step */ @@ -314,8 +314,8 @@ static int spwm_stop(struct spwm_s *spwm) static void tim6_handler(void) { struct spwm_s *spwm = &g_spwm; - struct stm32l4_pwm_dev_s *pwm = spwm->pwm; - struct stm32l4_tim_dev_s *tim = spwm->tim; + struct stm32_pwm_dev_s *pwm = spwm->pwm; + struct stm32_tim_dev_s *tim = spwm->tim; uint8_t i = 0; for (i = 0; i < spwm->phases; i += 1) @@ -336,7 +336,7 @@ static void tim6_handler(void) /* TODO: Software update */ - STM32L4_TIM_ACKINT(tim, ATIM_SR_UIF); + STM32_TIM_ACKINT(tim, ATIM_SR_UIF); } /**************************************************************************** @@ -345,13 +345,13 @@ static void tim6_handler(void) static int spwm_tim6_setup(struct spwm_s *spwm) { - struct stm32l4_tim_dev_s *tim = NULL; + struct stm32_tim_dev_s *tim = NULL; uint64_t freq = 0; int ret = OK; /* Get TIM6 interface */ - tim = stm32l4_tim_init(6); + tim = stm32_tim_init(6); if (tim == NULL) { printf("ERROR: Failed to get TIM6 interface\n"); @@ -368,12 +368,12 @@ static int spwm_tim6_setup(struct spwm_s *spwm) freq = spwm->samples * spwm->waveform_freq; - STM32L4_TIM_SETFREQ(tim, freq); - STM32L4_TIM_ENABLE(tim); + STM32_TIM_SETFREQ(tim, freq); + STM32_TIM_ENABLE(tim); /* Attach TIM6 ram vector */ - ret = arm_ramvec_attach(STM32L4_IRQ_TIM6, tim6_handler); + ret = arm_ramvec_attach(STM32_IRQ_TIM6, tim6_handler); if (ret < 0) { printf("ERROR: arm_ramvec_attach failed: %d\n", ret); @@ -383,7 +383,7 @@ static int spwm_tim6_setup(struct spwm_s *spwm) /* Set the priority of the TIM6 interrupt vector */ - ret = up_prioritize_irq(STM32L4_IRQ_TIM6, NVIC_SYSH_HIGH_PRIORITY); + ret = up_prioritize_irq(STM32_IRQ_TIM6, NVIC_SYSH_HIGH_PRIORITY); if (ret < 0) { printf("ERROR: up_prioritize_irq failed: %d\n", ret); @@ -403,12 +403,12 @@ static int spwm_tim6_setup(struct spwm_s *spwm) static int spwm_tim6_start(struct spwm_s *spwm) { - struct stm32l4_tim_dev_s *tim = spwm->tim; + struct stm32_tim_dev_s *tim = spwm->tim; /* Enable the timer interrupt at the NVIC and at TIM6 */ - up_enable_irq(STM32L4_IRQ_TIM6); - STM32L4_TIM_ENABLEINT(tim, BTIM_DIER_UIE); + up_enable_irq(STM32_IRQ_TIM6); + STM32_TIM_ENABLEINT(tim, BTIM_DIER_UIE); return OK; } @@ -419,12 +419,12 @@ static int spwm_tim6_start(struct spwm_s *spwm) static int spwm_tim6_stop(struct spwm_s *spwm) { - struct stm32l4_tim_dev_s *tim = spwm->tim; + struct stm32_tim_dev_s *tim = spwm->tim; /* Disable the timer interrupt at the NVIC and at TIM6 */ - up_disable_irq(STM32L4_IRQ_TIM6); - STM32L4_TIM_DISABLEINT(tim, BTIM_DIER_UIE); + up_disable_irq(STM32_IRQ_TIM6); + STM32_TIM_DISABLEINT(tim, BTIM_DIER_UIE); return OK; } @@ -435,12 +435,12 @@ static int spwm_tim6_stop(struct spwm_s *spwm) static int spwm_tim1_setup(struct spwm_s *spwm) { - struct stm32l4_pwm_dev_s *pwm = NULL; + struct stm32_pwm_dev_s *pwm = NULL; int ret = OK; /* Get TIM1 PWM interface */ - pwm = (struct stm32l4_pwm_dev_s *)stm32l4_pwminitialize(1); + pwm = (struct stm32_pwm_dev_s *)stm32_pwminitialize(1); if (pwm == NULL) { printf("ERROR: Failed to get TIM1 PWM interface\n"); @@ -486,7 +486,7 @@ static int spwm_tim1_setup(struct spwm_s *spwm) static int spwm_tim1_start(struct spwm_s *spwm) { - struct stm32l4_pwm_dev_s *pwm = spwm->pwm; + struct stm32_pwm_dev_s *pwm = spwm->pwm; uint16_t outputs = 0; int i = 0; @@ -514,7 +514,7 @@ static int spwm_tim1_start(struct spwm_s *spwm) static int spwm_tim1_stop(struct spwm_s *spwm) { - struct stm32l4_pwm_dev_s *pwm = spwm->pwm; + struct stm32_pwm_dev_s *pwm = spwm->pwm; uint16_t outputs = 0; int i = 0; diff --git a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_timer.c b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_timer.c index d0b9d26524b23..8d7ac77627f2f 100644 --- a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_timer.c +++ b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_timer.c @@ -61,7 +61,7 @@ int board_timer_driver_initialize(const char *devpath, int timer) { - return stm32l4_timer_initialize(devpath, timer); + return stm32_timer_initialize(devpath, timer); } #endif diff --git a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_uid.c b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_uid.c index bf21e6c4ea1c9..6e55610c9f034 100644 --- a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_uid.c +++ b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_uid.c @@ -38,7 +38,7 @@ #include -#include "stm32l4_uid.h" +#include "stm32_uid.h" #include "nucleo-l432kc.h" /**************************************************************************** @@ -56,6 +56,6 @@ int board_uniqueid(uint8_t *uniqueid) return -EINVAL; } - stm32l4_get_uniqueid(uniqueid); + stm32_get_uniqueid(uniqueid); return OK; } diff --git a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_userleds.c b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_userleds.c index c80bd6b70042c..8009c8346e5a8 100644 --- a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_userleds.c +++ b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_userleds.c @@ -36,7 +36,7 @@ #include "chip.h" #include "arm_internal.h" -#include "stm32l4.h" +#include "stm32.h" #include "nucleo-l432kc.h" #ifndef CONFIG_ARCH_LEDS @@ -154,7 +154,7 @@ uint32_t board_userled_initialize(void) { /* Configure LD3 GPIO for output */ - stm32l4_configgpio(GPIO_LD3); + stm32_configgpio(GPIO_LD3); return BOARD_NLEDS; } @@ -166,7 +166,7 @@ void board_userled(int led, bool ledon) { if (led == BOARD_LD3) { - stm32l4_gpiowrite(GPIO_LD3, ledon); + stm32_gpiowrite(GPIO_LD3, ledon); } } @@ -176,7 +176,7 @@ void board_userled(int led, bool ledon) void board_userled_all(uint32_t ledset) { - stm32l4_gpiowrite(GPIO_LD3, (ledset & BOARD_LD3_BIT) != 0); + stm32_gpiowrite(GPIO_LD3, (ledset & BOARD_LD3_BIT) != 0); } /**************************************************************************** diff --git a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_zerocross.c b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_zerocross.c index f717e3049652d..010e9af5d506a 100644 --- a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_zerocross.c +++ b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_zerocross.c @@ -98,7 +98,7 @@ static void zcross_enable(const struct zc_lowerhalf_s *lower, g_zcrossarg = arg; } - stm32l4_gpiosetevent(GPIO_ZEROCROSS, rising, falling, + stm32_gpiosetevent(GPIO_ZEROCROSS, rising, falling, true, zcross_interrupt, NULL); leave_critical_section(flags); @@ -120,7 +120,7 @@ static void zcross_disable(void) flags = enter_critical_section(); - stm32l4_gpiosetevent(GPIO_ZEROCROSS, false, false, false, NULL, NULL); + stm32_gpiosetevent(GPIO_ZEROCROSS, false, false, false, NULL, NULL); leave_critical_section(flags); @@ -164,10 +164,10 @@ static int zcross_interrupt(int irq, void *context, void *arg) int stm32_zerocross_initialize(void) { /* Configure the GPIO pin as input. NOTE: This is unnecessary for - * interrupting pins since it will also be done by stm32l4_gpiosetevent(). + * interrupting pins since it will also be done by stm32_gpiosetevent(). */ - stm32l4_configgpio(GPIO_ZEROCROSS); + stm32_configgpio(GPIO_ZEROCROSS); /* Make sure that all interrupts are disabled */ diff --git a/boards/arm/stm32l4/nucleo-l452re/configs/nsh/defconfig b/boards/arm/stm32l4/nucleo-l452re/configs/nsh/defconfig index 98f401ba27ac3..096df36781741 100644 --- a/boards/arm/stm32l4/nucleo-l452re/configs/nsh/defconfig +++ b/boards/arm/stm32l4/nucleo-l452re/configs/nsh/defconfig @@ -14,6 +14,7 @@ CONFIG_ARCH_BOARD="nucleo-l452re" CONFIG_ARCH_BOARD_NUCLEO_L452RE=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32l4" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32L452RE=y CONFIG_ARCH_CHIP_STM32L4=y CONFIG_ARCH_INTERRUPTSTACK=2048 @@ -56,20 +57,20 @@ CONFIG_RTC_NALARMS=2 CONFIG_SCHED_WAITPID=y CONFIG_SERIAL_TERMIOS=y CONFIG_STACK_COLORATION=y -CONFIG_STM32L4_ADC1=y -CONFIG_STM32L4_ADC1_DMA=y -CONFIG_STM32L4_DAC1=y -CONFIG_STM32L4_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32L4_DMA1=y -CONFIG_STM32L4_DMA2=y -CONFIG_STM32L4_I2C1=y -CONFIG_STM32L4_PWR=y -CONFIG_STM32L4_RNG=y -CONFIG_STM32L4_RTC=y -CONFIG_STM32L4_SAI1PLL=y -CONFIG_STM32L4_SPI1=y -CONFIG_STM32L4_SRAM2_HEAP=y -CONFIG_STM32L4_USART2=y +CONFIG_STM32_ADC1=y +CONFIG_STM32_ADC1_DMA=y +CONFIG_STM32_DAC1=y +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_DMA1=y +CONFIG_STM32_DMA2=y +CONFIG_STM32_I2C1=y +CONFIG_STM32_PWR=y +CONFIG_STM32_RNG=y +CONFIG_STM32_RTC=y +CONFIG_STM32_SAI1PLL=y +CONFIG_STM32_SPI1=y +CONFIG_STM32_SRAM2_HEAP=y +CONFIG_STM32_USART2=y CONFIG_SYSTEM_I2CTOOL=y CONFIG_SYSTEM_NSH=y CONFIG_SYSTEM_STACKMONITOR=y diff --git a/boards/arm/stm32l4/nucleo-l452re/include/board.h b/boards/arm/stm32l4/nucleo-l452re/include/board.h index f4bf2ebf864cd..007a934ca53fb 100644 --- a/boards/arm/stm32l4/nucleo-l452re/include/board.h +++ b/boards/arm/stm32l4/nucleo-l452re/include/board.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32L4_NUCLEO_L452RE_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32L4_NUCLEO_L452RE_INCLUDE_BOARD_H +#ifndef __BOARDS_ARM_STM32_NUCLEO_L452RE_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32_NUCLEO_L452RE_INCLUDE_BOARD_H /**************************************************************************** * Included Files @@ -257,7 +257,7 @@ extern "C" ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_board_initialize + * Name: stm32_board_initialize * * Description: * All STM32L4 architectures must provide the following entry point. @@ -267,7 +267,7 @@ extern "C" * ****************************************************************************/ -void stm32l4_board_initialize(void); +void stm32_board_initialize(void); #undef EXTERN #if defined(__cplusplus) @@ -275,4 +275,4 @@ void stm32l4_board_initialize(void); #endif #endif /* __ASSEMBLY__ */ -#endif /* __BOARDS_ARM_STM32L4_NUCLEO_L452RE_INCLUDE_BOARD_H */ +#endif /* __BOARDS_ARM_STM32_NUCLEO_L452RE_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32l4/nucleo-l452re/include/nucleo-l452re.h b/boards/arm/stm32l4/nucleo-l452re/include/nucleo-l452re.h index 0dd3430e3bda1..1cdf8d97ca8a2 100644 --- a/boards/arm/stm32l4/nucleo-l452re/include/nucleo-l452re.h +++ b/boards/arm/stm32l4/nucleo-l452re/include/nucleo-l452re.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32L4_NUCLEO_L452RE_INCLUDE_NUCLEO_L452RE_H -#define __BOARDS_ARM_STM32L4_NUCLEO_L452RE_INCLUDE_NUCLEO_L452RE_H +#ifndef __BOARDS_ARM_STM32_NUCLEO_L452RE_INCLUDE_NUCLEO_L452RE_H +#define __BOARDS_ARM_STM32_NUCLEO_L452RE_INCLUDE_NUCLEO_L452RE_H /**************************************************************************** * Included Files @@ -44,16 +44,16 @@ * * System Clock source : PLL (HSI) * SYSCLK(Hz) : 80000000 Determined by PLL configuration - * HCLK(Hz) : 80000000 (STM32L4_RCC_CFGR_HPRE) (Max 80 MHz) - * AHB Prescaler : 1 (STM32L4_RCC_CFGR_HPRE) (Max 80 MHz) - * APB1 Prescaler : 1 (STM32L4_RCC_CFGR_PPRE1) (Max 80 MHz) - * APB2 Prescaler : 1 (STM32L4_RCC_CFGR_PPRE2) (Max 80 MHz) + * HCLK(Hz) : 80000000 (STM32_RCC_CFGR_HPRE) (Max 80 MHz) + * AHB Prescaler : 1 (STM32_RCC_CFGR_HPRE) (Max 80 MHz) + * APB1 Prescaler : 1 (STM32_RCC_CFGR_PPRE1) (Max 80 MHz) + * APB2 Prescaler : 1 (STM32_RCC_CFGR_PPRE2) (Max 80 MHz) * HSI Frequency(Hz) : 16000000 (nominal) - * PLLM : 1 (STM32L4_PLLCFG_PLLM) - * PLLN : 10 (STM32L4_PLLCFG_PLLN) - * PLLP : 0 (STM32L4_PLLCFG_PLLP) - * PLLQ : 0 (STM32L4_PLLCFG_PLLQ) - * PLLR : 2 (STM32L4_PLLCFG_PLLR) + * PLLM : 1 (STM32_PLLCFG_PLLM) + * PLLN : 10 (STM32_PLLCFG_PLLN) + * PLLP : 0 (STM32_PLLCFG_PLLP) + * PLLQ : 0 (STM32_PLLCFG_PLLQ) + * PLLR : 2 (STM32_PLLCFG_PLLR) * PLLSAI1N : 12 * PLLSAI1Q : 4 * Flash Latency(WS) : 4 @@ -69,9 +69,9 @@ * LSE - 32.768 kHz installed */ -#define STM32L4_HSI_FREQUENCY 16000000ul -#define STM32L4_LSI_FREQUENCY 32000 -#define STM32L4_LSE_FREQUENCY 32768 +#define STM32_HSI_FREQUENCY 16000000ul +#define STM32_LSI_FREQUENCY 32000 +#define STM32_LSE_FREQUENCY 32768 #if 1 # define HSI_CLOCK_CONFIG /* HSI-16 clock configuration */ @@ -85,7 +85,7 @@ #if defined(HSI_CLOCK_CONFIG) -#define STM32L4_BOARD_USEHSI 1 +#define STM32_BOARD_USEHSI 1 /* XXX sysclk mux = pllclk */ @@ -125,7 +125,7 @@ * * PLL source is HSI * - * PLL_REF = STM32L4_HSI_FREQUENCY / PLLM + * PLL_REF = STM32_HSI_FREQUENCY / PLLM * = 16,000,000 / 1 * = 16,000,000 * @@ -144,7 +144,7 @@ * * The clock input and M divider are identical to the main PLL. * However the multiplier and postscalers are independent. - * The PLLSAI1 is configured only if CONFIG_STM32L4_SAI1PLL is defined + * The PLLSAI1 is configured only if CONFIG_STM32_SAI1PLL is defined * * SAI1VCO input frequency = PLL input clock frequency * SAI1VCO output frequency = SAI1VCO input frequency × PLLSAI1N, @@ -170,7 +170,7 @@ * * The clock input and M divider are identical to the main PLL. * However the multiplier and postscalers are independent. - * The PLLSAI2 is configured only if CONFIG_STM32L4_SAI2PLL is defined + * The PLLSAI2 is configured only if CONFIG_STM32_SAI2PLL is defined * * SAI2VCO input frequency = PLL input clock frequency * SAI2VCO output frequency = SAI2VCO input frequency × PLLSAI2N, @@ -221,7 +221,7 @@ * as per comment above HSI) */ -#define STM32L4_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) /* 'main' PLL config; we use this to generate our system clock via the R * output. We set it up as 16 MHz / 1 * 10 / 2 = 80 MHz @@ -232,55 +232,55 @@ * want things done this way. */ -#define STM32L4_PLLCFG_PLLN RCC_PLLCFG_PLLN(10) -#define STM32L4_PLLCFG_PLLP 0 -#undef STM32L4_PLLCFG_PLLP_ENABLED -#define STM32L4_PLLCFG_PLLQ RCC_PLLCFG_PLLQ_2 -#define STM32L4_PLLCFG_PLLQ_ENABLED -#define STM32L4_PLLCFG_PLLR RCC_PLLCFG_PLLR(2) -#define STM32L4_PLLCFG_PLLR_ENABLED +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(10) +#define STM32_PLLCFG_PLLP 0 +#undef STM32_PLLCFG_PLLP_ENABLED +#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ_2 +#define STM32_PLLCFG_PLLQ_ENABLED +#define STM32_PLLCFG_PLLR RCC_PLLCFG_PLLR(2) +#define STM32_PLLCFG_PLLR_ENABLED /* 'SAIPLL1' is not used in this application */ -#define STM32L4_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(12) -#define STM32L4_PLLSAI1CFG_PLLP 0 -#undef STM32L4_PLLSAI1CFG_PLLP_ENABLED -#define STM32L4_PLLSAI1CFG_PLLQ 0 -#undef STM32L4_PLLSAI1CFG_PLLQ_ENABLED -#define STM32L4_PLLSAI1CFG_PLLR 0 -#undef STM32L4_PLLSAI1CFG_PLLR_ENABLED +#define STM32_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(12) +#define STM32_PLLSAI1CFG_PLLP 0 +#undef STM32_PLLSAI1CFG_PLLP_ENABLED +#define STM32_PLLSAI1CFG_PLLQ 0 +#undef STM32_PLLSAI1CFG_PLLQ_ENABLED +#define STM32_PLLSAI1CFG_PLLR 0 +#undef STM32_PLLSAI1CFG_PLLR_ENABLED /* 'SAIPLL2' is not used in this application */ -#define STM32L4_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) -#define STM32L4_PLLSAI2CFG_PLLP 0 -#undef STM32L4_PLLSAI2CFG_PLLP_ENABLED -#define STM32L4_PLLSAI2CFG_PLLR 0 -#undef STM32L4_PLLSAI2CFG_PLLR_ENABLED +#define STM32_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) +#define STM32_PLLSAI2CFG_PLLP 0 +#undef STM32_PLLSAI2CFG_PLLP_ENABLED +#define STM32_PLLSAI2CFG_PLLR 0 +#undef STM32_PLLSAI2CFG_PLLR_ENABLED -#define STM32L4_SYSCLK_FREQUENCY 80000000ul +#define STM32_SYSCLK_FREQUENCY 80000000ul /* CLK48 will come from HSI48 */ -#if defined(CONFIG_STM32L4_USBFS) || defined(CONFIG_STM32L4_RNG) -# define STM32L4_USE_CLK48 1 -# define STM32L4_CLK48_SEL RCC_CCIPR_CLK48SEL_HSI48 -# define STM32L4_HSI48_SYNCSRC SYNCSRC_NONE +#if defined(CONFIG_STM32_USBFS) || defined(CONFIG_STM32_RNG) +# define STM32_USE_CLK48 1 +# define STM32_CLK48_SEL RCC_CCIPR_CLK48SEL_HSI48 +# define STM32_HSI48_SYNCSRC SYNCSRC_NONE #endif /* enable the LSE oscillator, used automatically trim the MSI, and for RTC */ -#define STM32L4_USE_LSE 1 +#define STM32_USE_LSE 1 /* AHB clock (HCLK) is SYSCLK (80MHz) */ -#define STM32L4_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ -#define STM32L4_HCLK_FREQUENCY STM32L4_SYSCLK_FREQUENCY +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY /* APB1 clock (PCLK1) is HCLK / 1 (80MHz) */ -#define STM32L4_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ -#define STM32L4_PCLK1_FREQUENCY (STM32L4_HCLK_FREQUENCY / 1) +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY / 1) /* The timer clock frequencies are automatically defined by hardware. * If the APB prescaler equals 1, the timer clock frequencies are set to the @@ -289,17 +289,17 @@ * REVISIT : this can be configured */ -#define STM32L4_APB1_TIM2_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM3_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM4_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM5_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM6_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM7_CLKIN (STM32L4_PCLK1_FREQUENCY) +#define STM32_APB1_TIM2_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM5_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (STM32_PCLK1_FREQUENCY) /* APB2 clock (PCLK2) is HCLK (80MHz) */ -#define STM32L4_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ -#define STM32L4_PCLK2_FREQUENCY (STM32L4_HCLK_FREQUENCY / 1) +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ +#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY / 1) /* The timer clock frequencies are automatically defined by hardware. * If the APB prescaler equals 1, the timer clock frequencies are set to the @@ -308,9 +308,9 @@ * REVISIT : this can be configured */ -#define STM32L4_APB2_TIM1_CLKIN (STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM15_CLKIN (STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM16_CLKIN (STM32L4_PCLK2_FREQUENCY) +#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM15_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM16_CLKIN (STM32_PCLK2_FREQUENCY) /* TODO SDMMC */ @@ -318,7 +318,7 @@ /* Use the HSE */ -#define STM32L4_BOARD_USEHSE 1 +#define STM32_BOARD_USEHSE 1 /* XXX sysclk mux = pllclk */ @@ -326,82 +326,82 @@ /* Prescaler common to all PLL inputs */ -#define STM32L4_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) /* 'main' PLL config; we use this to generate our system clock */ -#define STM32L4_PLLCFG_PLLN RCC_PLLCFG_PLLN(20) -#define STM32L4_PLLCFG_PLLP 0 -#undef STM32L4_PLLCFG_PLLP_ENABLED -#define STM32L4_PLLCFG_PLLQ 0 -#undef STM32L4_PLLCFG_PLLQ_ENABLED -#define STM32L4_PLLCFG_PLLR RCC_PLLCFG_PLLR_2 -#define STM32L4_PLLCFG_PLLR_ENABLED +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(20) +#define STM32_PLLCFG_PLLP 0 +#undef STM32_PLLCFG_PLLP_ENABLED +#define STM32_PLLCFG_PLLQ 0 +#undef STM32_PLLCFG_PLLQ_ENABLED +#define STM32_PLLCFG_PLLR RCC_PLLCFG_PLLR_2 +#define STM32_PLLCFG_PLLR_ENABLED /* 'SAIPLL1' is used to generate the 48 MHz clock */ -#define STM32L4_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(12) -#define STM32L4_PLLSAI1CFG_PLLP 0 -#undef STM32L4_PLLSAI1CFG_PLLP_ENABLED -#define STM32L4_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_2 -#define STM32L4_PLLSAI1CFG_PLLQ_ENABLED -#define STM32L4_PLLSAI1CFG_PLLR 0 -#undef STM32L4_PLLSAI1CFG_PLLR_ENABLED +#define STM32_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(12) +#define STM32_PLLSAI1CFG_PLLP 0 +#undef STM32_PLLSAI1CFG_PLLP_ENABLED +#define STM32_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_2 +#define STM32_PLLSAI1CFG_PLLQ_ENABLED +#define STM32_PLLSAI1CFG_PLLR 0 +#undef STM32_PLLSAI1CFG_PLLR_ENABLED /* 'SAIPLL2' is not used in this application */ -#define STM32L4_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) -#define STM32L4_PLLSAI2CFG_PLLP 0 -#undef STM32L4_PLLSAI2CFG_PLLP_ENABLED -#define STM32L4_PLLSAI2CFG_PLLR 0 -#undef STM32L4_PLLSAI2CFG_PLLR_ENABLED +#define STM32_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) +#define STM32_PLLSAI2CFG_PLLP 0 +#undef STM32_PLLSAI2CFG_PLLP_ENABLED +#define STM32_PLLSAI2CFG_PLLR 0 +#undef STM32_PLLSAI2CFG_PLLR_ENABLED -#define STM32L4_SYSCLK_FREQUENCY 80000000ul +#define STM32_SYSCLK_FREQUENCY 80000000ul /* Enable CLK48; get it from PLLSAI1 */ -#if defined(CONFIG_STM32L4_USBFS) || defined(CONFIG_STM32L4_RNG) -# define STM32L4_USE_CLK48 1 -# define STM32L4_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 -# define STM32L4_HSI48_SYNCSRC SYNCSRC_NONE +#if defined(CONFIG_STM32_USBFS) || defined(CONFIG_STM32_RNG) +# define STM32_USE_CLK48 1 +# define STM32_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 +# define STM32_HSI48_SYNCSRC SYNCSRC_NONE #endif /* Enable LSE (for the RTC) */ -#define STM32L4_USE_LSE 1 +#define STM32_USE_LSE 1 /* Configure the HCLK divisor (for the AHB bus, core, memory, and DMA */ -#define STM32L4_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ -#define STM32L4_HCLK_FREQUENCY STM32L4_SYSCLK_FREQUENCY +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY /* Configure the APB1 prescaler */ -#define STM32L4_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ -#define STM32L4_PCLK1_FREQUENCY (STM32L4_HCLK_FREQUENCY / 1) +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY / 1) -#define STM32L4_APB1_TIM2_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM3_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM4_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM5_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM6_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM7_CLKIN (STM32L4_PCLK1_FREQUENCY) +#define STM32_APB1_TIM2_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM5_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (STM32_PCLK1_FREQUENCY) /* Configure the APB2 prescaler */ -#define STM32L4_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ -#define STM32L4_PCLK2_FREQUENCY (STM32L4_HCLK_FREQUENCY / 1) +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ +#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY / 1) -#define STM32L4_APB2_TIM1_CLKIN (STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM15_CLKIN (STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM16_CLKIN (STM32L4_PCLK2_FREQUENCY) +#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM15_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM16_CLKIN (STM32_PCLK2_FREQUENCY) #elif defined(MSI_CLOCK_CONFIG) /* Use the MSI; frequ = 4 MHz; autotrim from LSE */ -#define STM32L4_BOARD_USEMSI 1 -#define STM32L4_BOARD_MSIRANGE RCC_CR_MSIRANGE_4M +#define STM32_BOARD_USEMSI 1 +#define STM32_BOARD_MSIRANGE RCC_CR_MSIRANGE_4M /* XXX sysclk mux = pllclk */ @@ -409,75 +409,75 @@ /* prescaler common to all PLL inputs */ -#define STM32L4_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) /* 'main' PLL config; we use this to generate our system clock */ -#define STM32L4_PLLCFG_PLLN RCC_PLLCFG_PLLN(40) -#define STM32L4_PLLCFG_PLLP 0 -#undef STM32L4_PLLCFG_PLLP_ENABLED -#define STM32L4_PLLCFG_PLLQ 0 -#undef STM32L4_PLLCFG_PLLQ_ENABLED -#define STM32L4_PLLCFG_PLLR RCC_PLLCFG_PLLR_2 -#define STM32L4_PLLCFG_PLLR_ENABLED +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(40) +#define STM32_PLLCFG_PLLP 0 +#undef STM32_PLLCFG_PLLP_ENABLED +#define STM32_PLLCFG_PLLQ 0 +#undef STM32_PLLCFG_PLLQ_ENABLED +#define STM32_PLLCFG_PLLR RCC_PLLCFG_PLLR_2 +#define STM32_PLLCFG_PLLR_ENABLED /* 'SAIPLL1' is not used in this application */ -#define STM32L4_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(24) -#define STM32L4_PLLSAI1CFG_PLLP 0 -#undef STM32L4_PLLSAI1CFG_PLLP_ENABLED -#define STM32L4_PLLSAI1CFG_PLLQ 0 -#undef STM32L4_PLLSAI1CFG_PLLQ_ENABLED -#define STM32L4_PLLSAI1CFG_PLLR 0 -#undef STM32L4_PLLSAI1CFG_PLLR_ENABLED +#define STM32_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(24) +#define STM32_PLLSAI1CFG_PLLP 0 +#undef STM32_PLLSAI1CFG_PLLP_ENABLED +#define STM32_PLLSAI1CFG_PLLQ 0 +#undef STM32_PLLSAI1CFG_PLLQ_ENABLED +#define STM32_PLLSAI1CFG_PLLR 0 +#undef STM32_PLLSAI1CFG_PLLR_ENABLED /* 'SAIPLL2' is not used in this application */ -#define STM32L4_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) -#define STM32L4_PLLSAI2CFG_PLLP 0 -#undef STM32L4_PLLSAI2CFG_PLLP_ENABLED -#define STM32L4_PLLSAI2CFG_PLLR 0 -#undef STM32L4_PLLSAI2CFG_PLLR_ENABLED +#define STM32_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) +#define STM32_PLLSAI2CFG_PLLP 0 +#undef STM32_PLLSAI2CFG_PLLP_ENABLED +#define STM32_PLLSAI2CFG_PLLR 0 +#undef STM32_PLLSAI2CFG_PLLR_ENABLED -#define STM32L4_SYSCLK_FREQUENCY 80000000ul +#define STM32_SYSCLK_FREQUENCY 80000000ul /* Enable CLK48; get it from HSI48 */ -#if defined(CONFIG_STM32L4_USBFS) || defined(CONFIG_STM32L4_RNG) -# define STM32L4_USE_CLK48 1 -# define STM32L4_CLK48_SEL RCC_CCIPR_CLK48SEL_HSI48 -# define STM32L4_HSI48_SYNCSRC SYNCSRC_NONE +#if defined(CONFIG_STM32_USBFS) || defined(CONFIG_STM32_RNG) +# define STM32_USE_CLK48 1 +# define STM32_CLK48_SEL RCC_CCIPR_CLK48SEL_HSI48 +# define STM32_HSI48_SYNCSRC SYNCSRC_NONE #endif /* Enable LSE (for the RTC) */ -#define STM32L4_USE_LSE 1 +#define STM32_USE_LSE 1 /* Configure the HCLK divisor (for the AHB bus, core, memory, and DMA */ -#define STM32L4_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ -#define STM32L4_HCLK_FREQUENCY STM32L4_SYSCLK_FREQUENCY +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY /* Configure the APB1 prescaler */ -#define STM32L4_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ -#define STM32L4_PCLK1_FREQUENCY (STM32L4_HCLK_FREQUENCY / 1) +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY / 1) -#define STM32L4_APB1_TIM2_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM3_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM4_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM5_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM6_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM7_CLKIN (STM32L4_PCLK1_FREQUENCY) +#define STM32_APB1_TIM2_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM5_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (STM32_PCLK1_FREQUENCY) /* Configure the APB2 prescaler */ -#define STM32L4_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ -#define STM32L4_PCLK2_FREQUENCY (STM32L4_HCLK_FREQUENCY / 1) +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ +#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY / 1) -#define STM32L4_APB2_TIM1_CLKIN (STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM15_CLKIN (STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM16_CLKIN (STM32L4_PCLK2_FREQUENCY) +#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM15_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM16_CLKIN (STM32_PCLK2_FREQUENCY) #endif @@ -487,17 +487,17 @@ * Note: TIM1,15,16 are on APB2, others on APB1 */ -#define BOARD_TIM1_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM2_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM3_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM4_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM5_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM6_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM7_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM15_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM16_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_LPTIM1_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_LPTIM2_FREQUENCY STM32L4_HCLK_FREQUENCY +#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM2_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM3_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM4_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM5_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM6_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM7_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM15_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM16_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_LPTIM1_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_LPTIM2_FREQUENCY STM32_HCLK_FREQUENCY /**************************************************************************** * Public Data @@ -524,4 +524,4 @@ extern "C" #endif #endif /* __ASSEMBLY__ */ -#endif /* __BOARDS_ARM_STM32L4_NUCLEO_L452RE_INCLUDE_NUCLEO_L452RE_H */ +#endif /* __BOARDS_ARM_STM32_NUCLEO_L452RE_INCLUDE_NUCLEO_L452RE_H */ diff --git a/boards/arm/stm32l4/nucleo-l452re/src/Make.defs b/boards/arm/stm32l4/nucleo-l452re/src/Make.defs new file mode 100644 index 0000000000000..95d5c9ae297db --- /dev/null +++ b/boards/arm/stm32l4/nucleo-l452re/src/Make.defs @@ -0,0 +1,47 @@ +############################################################################ +# boards/arm/stm32l4/nucleo-l452re/src/Makefile +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +CSRCS = stm32_boot.c stm32_bringup.c stm32_spi.c + +ifeq ($(CONFIG_ARCH_LEDS),y) +CSRCS += stm32_autoleds.c +else +CSRCS += stm32_userleds.c +endif + +ifeq ($(CONFIG_ARCH_BUTTONS),y) +CSRCS += stm32_buttons.c +endif + +ifeq ($(CONFIG_ADC),y) +CSRCS += stm32_adc.c +endif + +ifeq ($(CONFIG_DAC),y) +CSRCS += stm32_dac.c +endif + +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32l4/nucleo-l452re/src/Makefile b/boards/arm/stm32l4/nucleo-l452re/src/Makefile deleted file mode 100644 index 4c04979e48a7b..0000000000000 --- a/boards/arm/stm32l4/nucleo-l452re/src/Makefile +++ /dev/null @@ -1,45 +0,0 @@ -############################################################################ -# boards/arm/stm32l4/nucleo-l452re/src/Makefile -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/Make.defs - -CSRCS = stm32_boot.c stm32_bringup.c stm32_spi.c - -ifeq ($(CONFIG_ARCH_LEDS),y) -CSRCS += stm32_autoleds.c -else -CSRCS += stm32_userleds.c -endif - -ifeq ($(CONFIG_ARCH_BUTTONS),y) -CSRCS += stm32_buttons.c -endif - -ifeq ($(CONFIG_ADC),y) -CSRCS += stm32_adc.c -endif - -ifeq ($(CONFIG_DAC),y) -CSRCS += stm32_dac.c -endif - -include $(TOPDIR)/boards/Board.mk diff --git a/boards/arm/stm32l4/nucleo-l452re/src/nucleo-l452re.h b/boards/arm/stm32l4/nucleo-l452re/src/nucleo-l452re.h index 4ab69149c5d59..f3c2242f39b21 100644 --- a/boards/arm/stm32l4/nucleo-l452re/src/nucleo-l452re.h +++ b/boards/arm/stm32l4/nucleo-l452re/src/nucleo-l452re.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32L4_NUCLEO_L452RE_SRC_NUCLEO_L452RE_H -#define __BOARDS_ARM_STM32L4_NUCLEO_L452RE_SRC_NUCLEO_L452RE_H +#ifndef __BOARDS_ARM_STM32_NUCLEO_L452RE_SRC_NUCLEO_L452RE_H +#define __BOARDS_ARM_STM32_NUCLEO_L452RE_SRC_NUCLEO_L452RE_H /**************************************************************************** * Included Files @@ -58,22 +58,22 @@ # undef HAVE_RTC_DRIVER #endif -#if !defined(CONFIG_STM32L4_SDIO) || !defined(CONFIG_MMCSD) || \ +#if !defined(CONFIG_STM32_SDIO) || !defined(CONFIG_MMCSD) || \ !defined(CONFIG_MMCSD_SDIO) # undef HAVE_MMCSD #endif /* How many SPI modules does this chip support? */ -#if STM32L4_NSPI < 1 -# undef CONFIG_STM32L4_SPI1 -# undef CONFIG_STM32L4_SPI2 -# undef CONFIG_STM32L4_SPI3 -#elif STM32L4_NSPI < 2 -# undef CONFIG_STM32L4_SPI2 -# undef CONFIG_STM32L4_SPI3 -#elif STM32L4_NSPI < 3 -# undef CONFIG_STM32L4_SPI3 +#if STM32_NSPI < 1 +# undef CONFIG_STM32_SPI1 +# undef CONFIG_STM32_SPI2 +# undef CONFIG_STM32_SPI3 +#elif STM32_NSPI < 2 +# undef CONFIG_STM32_SPI2 +# undef CONFIG_STM32_SPI3 +#elif STM32_NSPI < 3 +# undef CONFIG_STM32_SPI3 #endif /* Nucleo-L452RE GPIOs ******************************************************/ @@ -118,36 +118,36 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_adc_setup + * Name: stm32_adc_setup * * Description: * Initialize ADC and register the ADC driver. * ****************************************************************************/ -int stm32l4_adc_setup(void); +int stm32_adc_setup(void); /**************************************************************************** - * Name: stm32l4_adc_measure_voltages + * Name: stm32_adc_measure_voltages * * Description: * Read internal reference voltage, internal VBAT and one external voltage. * ****************************************************************************/ -int stm32l4_adc_measure_voltages(uint32_t *vrefint, +int stm32_adc_measure_voltages(uint32_t *vrefint, uint32_t *vbat, uint32_t *vext); /**************************************************************************** - * Name: stm32l4_dac_setup + * Name: stm32_dac_setup * * Description: * Initialize DAC and register the DAC driver. * ****************************************************************************/ -int stm32l4_dac_setup(void); +int stm32_dac_setup(void); /**************************************************************************** * Name: stm32_bringup @@ -163,4 +163,4 @@ int stm32l4_dac_setup(void); int stm32_bringup(void); #endif /* __ASSEMBLY__ */ -#endif /* __BOARDS_ARM_STM32L4_NUCLEO_L452RE_SRC_NUCLEO_L452RE_H */ +#endif /* __BOARDS_ARM_STM32_NUCLEO_L452RE_SRC_NUCLEO_L452RE_H */ diff --git a/boards/arm/stm32l4/nucleo-l452re/src/stm32_adc.c b/boards/arm/stm32l4/nucleo-l452re/src/stm32_adc.c index 2cd9d75fb259f..cfbe5dedc47e0 100644 --- a/boards/arm/stm32l4/nucleo-l452re/src/stm32_adc.c +++ b/boards/arm/stm32l4/nucleo-l452re/src/stm32_adc.c @@ -114,7 +114,7 @@ #define ADC1_NCHANNELS 4 -#if ADC1_NCHANNELS > 1 && !defined(CONFIG_STM32L4_ADC1_DMA) +#if ADC1_NCHANNELS > 1 && !defined(CONFIG_STM32_ADC1_DMA) # warning "Reading multiple channels without DMA might cause overruns!" #endif @@ -147,14 +147,14 @@ static const uint32_t g_pinlist[ADC1_NCHANNELS] = ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_adc_measure_voltages + * Name: stm32_adc_measure_voltages * * Description: * Read internal reference voltage, internal VBAT and one external voltage. * ****************************************************************************/ -int stm32l4_adc_measure_voltages(uint32_t *vrefint, uint32_t *vbat, +int stm32_adc_measure_voltages(uint32_t *vrefint, uint32_t *vbat, uint32_t *vext) { struct file filestruct; @@ -277,16 +277,16 @@ int stm32l4_adc_measure_voltages(uint32_t *vrefint, uint32_t *vbat, } /**************************************************************************** - * Name: stm32l4_adc_setup + * Name: stm32_adc_setup ****************************************************************************/ -int stm32l4_adc_setup(void) +int stm32_adc_setup(void) { static bool initialized = false; if (!initialized) { -#ifdef CONFIG_STM32L4_ADC1 +#ifdef CONFIG_STM32_ADC1 int ret; int i; @@ -296,15 +296,15 @@ int stm32l4_adc_setup(void) { if (g_pinlist[i] != 0xffffffffu) { - stm32l4_configgpio(g_pinlist[i]); + stm32_configgpio(g_pinlist[i]); } } - /* Call stm32l4_adc_initialize() to get an instance of the ADC + /* Call stm32_adc_initialize() to get an instance of the ADC * interface */ - g_adc = stm32l4_adc_initialize(1, g_chanlist, ADC1_NCHANNELS); + g_adc = stm32_adc_initialize(1, g_chanlist, ADC1_NCHANNELS); if (g_adc == NULL) { aerr("ERROR: Failed to get ADC interface\n"); diff --git a/boards/arm/stm32l4/nucleo-l452re/src/stm32_autoleds.c b/boards/arm/stm32l4/nucleo-l452re/src/stm32_autoleds.c index 86102cae00a88..3abec894bc54d 100644 --- a/boards/arm/stm32l4/nucleo-l452re/src/stm32_autoleds.c +++ b/boards/arm/stm32l4/nucleo-l452re/src/stm32_autoleds.c @@ -53,7 +53,7 @@ void board_autoled_initialize(void) { /* Configure LD2 GPIO for output */ - stm32l4_configgpio(GPIO_LD2); + stm32_configgpio(GPIO_LD2); } /**************************************************************************** @@ -64,7 +64,7 @@ void board_autoled_on(int led) { if (led == 1) { - stm32l4_gpiowrite(GPIO_LD2, true); + stm32_gpiowrite(GPIO_LD2, true); } } @@ -76,7 +76,7 @@ void board_autoled_off(int led) { if (led == 1) { - stm32l4_gpiowrite(GPIO_LD2, false); + stm32_gpiowrite(GPIO_LD2, false); } } diff --git a/boards/arm/stm32l4/nucleo-l452re/src/stm32_boot.c b/boards/arm/stm32l4/nucleo-l452re/src/stm32_boot.c index 94bf0983a8ca9..0031ce09d0548 100644 --- a/boards/arm/stm32l4/nucleo-l452re/src/stm32_boot.c +++ b/boards/arm/stm32l4/nucleo-l452re/src/stm32_boot.c @@ -40,7 +40,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_board_initialize + * Name: stm32_board_initialize * * Description: * All STM32 architectures must provide the following entry point. @@ -50,7 +50,7 @@ * ****************************************************************************/ -void stm32l4_board_initialize(void) +void stm32_board_initialize(void) { #ifdef CONFIG_ARCH_LEDS /* Configure on-board LEDs if LED support has been selected. */ diff --git a/boards/arm/stm32l4/nucleo-l452re/src/stm32_bringup.c b/boards/arm/stm32l4/nucleo-l452re/src/stm32_bringup.c index 31eac2e1376d2..0dcd2af919135 100644 --- a/boards/arm/stm32l4/nucleo-l452re/src/stm32_bringup.c +++ b/boards/arm/stm32l4/nucleo-l452re/src/stm32_bringup.c @@ -45,7 +45,7 @@ ****************************************************************************/ #undef HAVE_I2C_DRIVER -#if defined(CONFIG_STM32L4_I2C1) && defined(CONFIG_I2C_DRIVER) +#if defined(CONFIG_STM32_I2C1) && defined(CONFIG_I2C_DRIVER) # define HAVE_I2C_DRIVER 1 #endif @@ -102,7 +102,7 @@ int stm32_bringup(void) #ifdef HAVE_I2C_DRIVER /* Get the I2C lower half instance */ - i2c = stm32l4_i2cbus_initialize(1); + i2c = stm32_i2cbus_initialize(1); if (i2c == NULL) { i2cerr("ERROR: Initialize I2C1: %d\n", ret); @@ -122,13 +122,13 @@ int stm32_bringup(void) #ifdef CONFIG_DAC ainfo("Initializing DAC\n"); - stm32l4_dac_setup(); + stm32_dac_setup(); #endif #ifdef CONFIG_ADC ainfo("Initializing ADC\n"); - stm32l4_adc_setup(); + stm32_adc_setup(); #endif UNUSED(ret); diff --git a/boards/arm/stm32l4/nucleo-l452re/src/stm32_buttons.c b/boards/arm/stm32l4/nucleo-l452re/src/stm32_buttons.c index 261d03e6f292b..18ea50c5ace2e 100644 --- a/boards/arm/stm32l4/nucleo-l452re/src/stm32_buttons.c +++ b/boards/arm/stm32l4/nucleo-l452re/src/stm32_buttons.c @@ -61,7 +61,7 @@ uint32_t board_button_initialize(void) * also configured for the pin. */ - stm32l4_configgpio(GPIO_BTN_USER); + stm32_configgpio(GPIO_BTN_USER); return NUM_BUTTONS; } @@ -75,7 +75,7 @@ uint32_t board_buttons(void) * pressed. */ - bool released = stm32l4_gpioread(GPIO_BTN_USER); + bool released = stm32_gpioread(GPIO_BTN_USER); return !released; } @@ -108,7 +108,7 @@ int board_button_irq(int id, xcpt_t irqhandler, void *arg) if (id == BUTTON_USER) { - ret = stm32l4_gpiosetevent(GPIO_BTN_USER, true, true, true, + ret = stm32_gpiosetevent(GPIO_BTN_USER, true, true, true, irqhandler, arg); } diff --git a/boards/arm/stm32l4/nucleo-l452re/src/stm32_dac.c b/boards/arm/stm32l4/nucleo-l452re/src/stm32_dac.c index 09b56bc5ff424..91caf4947c310 100644 --- a/boards/arm/stm32l4/nucleo-l452re/src/stm32_dac.c +++ b/boards/arm/stm32l4/nucleo-l452re/src/stm32_dac.c @@ -48,19 +48,19 @@ static struct dac_dev_s *g_dac; ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_dac_setup + * Name: stm32_dac_setup ****************************************************************************/ -int stm32l4_dac_setup(void) +int stm32_dac_setup(void) { static bool initialized = false; if (!initialized) { -#ifdef CONFIG_STM32L4_DAC1 +#ifdef CONFIG_STM32_DAC1 int ret; - g_dac = stm32l4_dacinitialize(0); + g_dac = stm32_dacinitialize(0); if (g_dac == NULL) { aerr("ERROR: Failed to get DAC interface\n"); diff --git a/boards/arm/stm32l4/nucleo-l452re/src/stm32_spi.c b/boards/arm/stm32l4/nucleo-l452re/src/stm32_spi.c index 4c43919bd200c..ab1e9fac9a653 100644 --- a/boards/arm/stm32l4/nucleo-l452re/src/stm32_spi.c +++ b/boards/arm/stm32l4/nucleo-l452re/src/stm32_spi.c @@ -34,13 +34,13 @@ #include #include "chip.h" -#include +#include #include "nucleo-l452re.h" #include -#if defined(CONFIG_STM32L4_SPI1) || defined(CONFIG_STM32L4_SPI2) || defined(CONFIG_STM32L4_SPI3) +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || defined(CONFIG_STM32_SPI3) /**************************************************************************** * Public Data @@ -48,10 +48,10 @@ /* Global driver instances */ -#ifdef CONFIG_STM32L4_SPI1 +#ifdef CONFIG_STM32_SPI1 struct spi_dev_s *g_spi1; #endif -#ifdef CONFIG_STM32L4_SPI2 +#ifdef CONFIG_STM32_SPI2 struct spi_dev_s *g_spi2; #endif @@ -60,33 +60,33 @@ struct spi_dev_s *g_spi2; ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_spiinitialize + * Name: stm32_spiinitialize * * Description: * Called to configure SPI chip select GPIO pins. * ****************************************************************************/ -void weak_function stm32l4_spiinitialize(void) +void weak_function stm32_spiinitialize(void) { -#ifdef CONFIG_STM32L4_SPI1 +#ifdef CONFIG_STM32_SPI1 /* Configure SPI-based devices */ - g_spi1 = stm32l4_spibus_initialize(1); + g_spi1 = stm32_spibus_initialize(1); if (!g_spi1) { spierr("ERROR: FAILED to initialize SPI port 1\n"); } #ifdef HAVE_MMCSD - stm32l4_configgpio(GPIO_SPI_CS_SD_CARD); + stm32_configgpio(GPIO_SPI_CS_SD_CARD); #endif #endif -#ifdef CONFIG_STM32L4_SPI2 +#ifdef CONFIG_STM32_SPI2 /* Configure SPI-based devices */ - g_spi2 = stm32l4_spibus_initialize(2); + g_spi2 = stm32_spibus_initialize(2); if (!g_spi2) { spierr("ERROR: FAILED to initialize SPI port 1\n"); @@ -95,19 +95,19 @@ void weak_function stm32l4_spiinitialize(void) } /**************************************************************************** - * Name: stm32l4_spi1/2/3select and stm32l4_spi1/2/3status + * Name: stm32_spi1/2/3select and stm32_spi1/2/3status * * Description: - * The external functions, stm32l4_spi1/2/3select and - * stm32l4_spi1/2/3status must be provided by board-specific logic. They + * The external functions, stm32_spi1/2/3select and + * stm32_spi1/2/3status must be provided by board-specific logic. They * are implementations of the select and status methods of the SPI * interface defined by struct spi_ops_s (see include/nuttx/spi/spi.h). * All other methods (including up_spiinitialize()) are provided by common * STM32 logic. To use this common SPI logic on your board: * - * 1. Provide logic in stm32l4_board_initialize() to configure SPI chip + * 1. Provide logic in stm32_board_initialize() to configure SPI chip * select pins. - * 2. Provide stm32l4_spi1/2/3select() and stm32l4_spi1/2/3status() + * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() * functions in your board-specific logic. These functions will perform * chip selection and status operations using GPIOs in the way your * board is configured. @@ -120,8 +120,8 @@ void weak_function stm32l4_spiinitialize(void) * ****************************************************************************/ -#ifdef CONFIG_STM32L4_SPI1 -void stm32l4_spi1select(struct spi_dev_s *dev, +#ifdef CONFIG_STM32_SPI1 +void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, bool selected) { spiinfo("devid: %d CS: %s\n", @@ -130,47 +130,47 @@ void stm32l4_spi1select(struct spi_dev_s *dev, #ifdef HAVE_MMCSD if (devid == SPIDEV_MMCSD(0)) { - stm32l4_gpiowrite(GPIO_SPI_CS_SD_CARD, !selected); + stm32_gpiowrite(GPIO_SPI_CS_SD_CARD, !selected); } #endif } -uint8_t stm32l4_spi1status(struct spi_dev_s *dev, uint32_t devid) +uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) { return 0; } #endif -#ifdef CONFIG_STM32L4_SPI2 -void stm32l4_spi2select(struct spi_dev_s *dev, +#ifdef CONFIG_STM32_SPI2 +void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid, bool selected) { spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); } -uint8_t stm32l4_spi2status(struct spi_dev_s *dev, uint32_t devid) +uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) { return 0; } #endif -#ifdef CONFIG_STM32L4_SPI3 -void stm32l4_spi3select(struct spi_dev_s *dev, +#ifdef CONFIG_STM32_SPI3 +void stm32_spi3select(struct spi_dev_s *dev, uint32_t devid, bool selected) { spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); } -uint8_t stm32l4_spi3status(struct spi_dev_s *dev, uint32_t devid) +uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid) { return 0; } #endif /**************************************************************************** - * Name: stm32l4_spi1cmddata + * Name: stm32_spi1cmddata * * Description: * Set or clear the SH1101A A0 or SD1306 D/C n bit to select data (true) @@ -193,26 +193,26 @@ uint8_t stm32l4_spi3status(struct spi_dev_s *dev, uint32_t devid) ****************************************************************************/ #ifdef CONFIG_SPI_CMDDATA -#ifdef CONFIG_STM32L4_SPI1 -int stm32l4_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) +#ifdef CONFIG_STM32_SPI1 +int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return OK; } #endif -#ifdef CONFIG_STM32L4_SPI2 -int stm32l4_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) +#ifdef CONFIG_STM32_SPI2 +int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return OK; } #endif -#ifdef CONFIG_STM32L4_SPI3 -int stm32l4_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) +#ifdef CONFIG_STM32_SPI3 +int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return OK; } #endif #endif /* CONFIG_SPI_CMDDATA */ -#endif /* CONFIG_STM32L4_SPI1 || CONFIG_STM32L4_SPI2 || CONFIG_STM32L4_SPI3 */ +#endif /* CONFIG_STM32_SPI1 || CONFIG_STM32_SPI2 || CONFIG_STM32_SPI3 */ diff --git a/boards/arm/stm32l4/nucleo-l452re/src/stm32_userleds.c b/boards/arm/stm32l4/nucleo-l452re/src/stm32_userleds.c index 6911949d1111a..8344890d1ab10 100644 --- a/boards/arm/stm32l4/nucleo-l452re/src/stm32_userleds.c +++ b/boards/arm/stm32l4/nucleo-l452re/src/stm32_userleds.c @@ -155,7 +155,7 @@ uint32_t board_userled_initialize(void) { /* Configure LD2 GPIO for output */ - stm32l4_configgpio(GPIO_LD2); + stm32_configgpio(GPIO_LD2); return BOARD_NLEDS; } @@ -167,7 +167,7 @@ void board_userled(int led, bool ledon) { if (led == BOARD_LD2) { - stm32l4_gpiowrite(GPIO_LD2, ledon); + stm32_gpiowrite(GPIO_LD2, ledon); } } @@ -177,15 +177,15 @@ void board_userled(int led, bool ledon) void board_userled_all(uint32_t ledset) { - stm32l4_gpiowrite(GPIO_LD2, (ledset & BOARD_LD2_BIT) != 0); + stm32_gpiowrite(GPIO_LD2, (ledset & BOARD_LD2_BIT) != 0); } /**************************************************************************** - * Name: stm32l4_led_pminitialize + * Name: stm32_led_pminitialize ****************************************************************************/ #ifdef CONFIG_PM -void stm32l4_led_pminitialize(void) +void stm32_led_pminitialize(void) { /* Register to receive power management callbacks */ diff --git a/boards/arm/stm32l4/nucleo-l476rg/configs/nsh/defconfig b/boards/arm/stm32l4/nucleo-l476rg/configs/nsh/defconfig index 4850d96906598..09c040793ff80 100644 --- a/boards/arm/stm32l4/nucleo-l476rg/configs/nsh/defconfig +++ b/boards/arm/stm32l4/nucleo-l476rg/configs/nsh/defconfig @@ -14,6 +14,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-l476rg" CONFIG_ARCH_BOARD_NUCLEO_L476RG=y CONFIG_ARCH_CHIP="stm32l4" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32L476RG=y CONFIG_ARCH_CHIP_STM32L4=y CONFIG_ARCH_INTERRUPTSTACK=2048 @@ -44,15 +45,15 @@ CONFIG_RTC_IOCTL=y CONFIG_RTC_NALARMS=2 CONFIG_SCHED_WAITPID=y CONFIG_SPI=y -CONFIG_STM32L4_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32L4_DMA1=y -CONFIG_STM32L4_DMA2=y -CONFIG_STM32L4_PWR=y -CONFIG_STM32L4_RNG=y -CONFIG_STM32L4_RTC=y -CONFIG_STM32L4_SAI1PLL=y -CONFIG_STM32L4_SRAM2_HEAP=y -CONFIG_STM32L4_USART2=y +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_DMA1=y +CONFIG_STM32_DMA2=y +CONFIG_STM32_PWR=y +CONFIG_STM32_RNG=y +CONFIG_STM32_RTC=y +CONFIG_STM32_SAI1PLL=y +CONFIG_STM32_SRAM2_HEAP=y +CONFIG_STM32_USART2=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_TESTING_OSTEST=y diff --git a/boards/arm/stm32l4/nucleo-l476rg/configs/nxdemo/defconfig b/boards/arm/stm32l4/nucleo-l476rg/configs/nxdemo/defconfig index 648c01ff163cf..f71159d49eb92 100644 --- a/boards/arm/stm32l4/nucleo-l476rg/configs/nxdemo/defconfig +++ b/boards/arm/stm32l4/nucleo-l476rg/configs/nxdemo/defconfig @@ -15,6 +15,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-l476rg" CONFIG_ARCH_BOARD_NUCLEO_L476RG=y CONFIG_ARCH_CHIP="stm32l4" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32L476RG=y CONFIG_ARCH_CHIP_STM32L4=y CONFIG_ARCH_INTERRUPTSTACK=2048 @@ -53,16 +54,16 @@ CONFIG_RTC_NALARMS=2 CONFIG_SCHED_WAITPID=y CONFIG_SPI_CMDDATA=y CONFIG_START_YEAR=2017 -CONFIG_STM32L4_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32L4_DMA1=y -CONFIG_STM32L4_DMA2=y -CONFIG_STM32L4_PWR=y -CONFIG_STM32L4_RNG=y -CONFIG_STM32L4_RTC=y -CONFIG_STM32L4_SAI1PLL=y -CONFIG_STM32L4_SPI1=y -CONFIG_STM32L4_SRAM2_HEAP=y -CONFIG_STM32L4_USART2=y +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_DMA1=y +CONFIG_STM32_DMA2=y +CONFIG_STM32_PWR=y +CONFIG_STM32_RNG=y +CONFIG_STM32_RTC=y +CONFIG_STM32_SAI1PLL=y +CONFIG_STM32_SPI1=y +CONFIG_STM32_SRAM2_HEAP=y +CONFIG_STM32_USART2=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32l4/nucleo-l476rg/include/board.h b/boards/arm/stm32l4/nucleo-l476rg/include/board.h index b483107f1ae82..50530a1e0f1bf 100644 --- a/boards/arm/stm32l4/nucleo-l476rg/include/board.h +++ b/boards/arm/stm32l4/nucleo-l476rg/include/board.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32L4_NUCLEO_L476RG_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32L4_NUCLEO_L476RG_INCLUDE_BOARD_H +#ifndef __BOARDS_ARM_STM32_NUCLEO_L476RG_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32_NUCLEO_L476RG_INCLUDE_BOARD_H /**************************************************************************** * Included Files @@ -277,4 +277,4 @@ extern "C" #endif #endif /* __ASSEMBLY__ */ -#endif /* __BOARDS_ARM_STM32L4_NUCLEO_F476RG_INCLUDE_BOARD_H */ +#endif /* __BOARDS_ARM_STM32_NUCLEO_F476RG_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32l4/nucleo-l476rg/include/nucleo-l476rg.h b/boards/arm/stm32l4/nucleo-l476rg/include/nucleo-l476rg.h index 39623ef7e569d..07dd18aa069c8 100644 --- a/boards/arm/stm32l4/nucleo-l476rg/include/nucleo-l476rg.h +++ b/boards/arm/stm32l4/nucleo-l476rg/include/nucleo-l476rg.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32L4_NUCLEO_L476RG_INCLUDE_NUCLEO_L476RG_H -#define __BOARDS_ARM_STM32L4_NUCLEO_L476RG_INCLUDE_NUCLEO_L476RG_H +#ifndef __BOARDS_ARM_STM32_NUCLEO_L476RG_INCLUDE_NUCLEO_L476RG_H +#define __BOARDS_ARM_STM32_NUCLEO_L476RG_INCLUDE_NUCLEO_L476RG_H /**************************************************************************** * Included Files @@ -55,16 +55,16 @@ * * System Clock source : PLL (HSI) * SYSCLK(Hz) : 80000000 Determined by PLL configuration - * HCLK(Hz) : 80000000 (STM32L4_RCC_CFGR_HPRE) (Max 80 MHz) - * AHB Prescaler : 1 (STM32L4_RCC_CFGR_HPRE) (Max 80 MHz) - * APB1 Prescaler : 1 (STM32L4_RCC_CFGR_PPRE1) (Max 80 MHz) - * APB2 Prescaler : 1 (STM32L4_RCC_CFGR_PPRE2) (Max 80 MHz) + * HCLK(Hz) : 80000000 (STM32_RCC_CFGR_HPRE) (Max 80 MHz) + * AHB Prescaler : 1 (STM32_RCC_CFGR_HPRE) (Max 80 MHz) + * APB1 Prescaler : 1 (STM32_RCC_CFGR_PPRE1) (Max 80 MHz) + * APB2 Prescaler : 1 (STM32_RCC_CFGR_PPRE2) (Max 80 MHz) * HSI Frequency(Hz) : 16000000 (nominal) - * PLLM : 1 (STM32L4_PLLCFG_PLLM) - * PLLN : 10 (STM32L4_PLLCFG_PLLN) - * PLLP : 0 (STM32L4_PLLCFG_PLLP) - * PLLQ : 0 (STM32L4_PLLCFG_PLLQ) - * PLLR : 2 (STM32L4_PLLCFG_PLLR) + * PLLM : 1 (STM32_PLLCFG_PLLM) + * PLLN : 10 (STM32_PLLCFG_PLLN) + * PLLP : 0 (STM32_PLLCFG_PLLP) + * PLLQ : 0 (STM32_PLLCFG_PLLQ) + * PLLR : 2 (STM32_PLLCFG_PLLR) * PLLSAI1N : 12 * PLLSAI1Q : 4 * Flash Latency(WS) : 4 @@ -80,11 +80,11 @@ * LSE - 32.768 kHz installed */ -#define STM32L4_HSI_FREQUENCY 16000000ul -#define STM32L4_LSI_FREQUENCY 32000 -#define STM32L4_LSE_FREQUENCY 32768 +#define STM32_HSI_FREQUENCY 16000000ul +#define STM32_LSI_FREQUENCY 32000 +#define STM32_LSE_FREQUENCY 32768 -#define STM32L4_BOARD_USEHSI 1 +#define STM32_BOARD_USEHSI 1 /* XXX sysclk mux = pllclk */ @@ -124,7 +124,7 @@ * * PLL source is HSI * - * PLL_REF = STM32L4_HSI_FREQUENCY / PLLM + * PLL_REF = STM32_HSI_FREQUENCY / PLLM * = 16,000,000 / 1 * = 16,000,000 * @@ -143,7 +143,7 @@ * * The clock input and M divider are identical to the main PLL. * However the multiplier and postscalers are independent. - * The PLLSAI1 is configured only if CONFIG_STM32L4_SAI1PLL is defined + * The PLLSAI1 is configured only if CONFIG_STM32_SAI1PLL is defined * * SAI1VCO input frequency = PLL input clock frequency * SAI1VCO output frequency = SAI1VCO input frequency × PLLSAI1N, @@ -169,7 +169,7 @@ * * The clock input and M divider are identical to the main PLL. * However the multiplier and postscalers are independent. - * The PLLSAI2 is configured only if CONFIG_STM32L4_SAI2PLL is defined + * The PLLSAI2 is configured only if CONFIG_STM32_SAI2PLL is defined * * SAI2VCO input frequency = PLL input clock frequency * SAI2VCO output frequency = SAI2VCO input frequency × PLLSAI2N, @@ -219,7 +219,7 @@ * as per comment above HSI) . */ -#define STM32L4_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) /* 'main' PLL config; we use this to generate our system clock via the R * output. We set it up as 16 MHz / 1 * 10 / 2 = 80 MHz @@ -230,13 +230,13 @@ * applications may want things done this way. */ -#define STM32L4_PLLCFG_PLLN RCC_PLLCFG_PLLN(10) -#define STM32L4_PLLCFG_PLLP 0 -#undef STM32L4_PLLCFG_PLLP_ENABLED -#define STM32L4_PLLCFG_PLLQ RCC_PLLCFG_PLLQ_2 -#define STM32L4_PLLCFG_PLLQ_ENABLED -#define STM32L4_PLLCFG_PLLR RCC_PLLCFG_PLLR(2) -#define STM32L4_PLLCFG_PLLR_ENABLED +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(10) +#define STM32_PLLCFG_PLLP 0 +#undef STM32_PLLCFG_PLLP_ENABLED +#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ_2 +#define STM32_PLLCFG_PLLQ_ENABLED +#define STM32_PLLCFG_PLLR RCC_PLLCFG_PLLR(2) +#define STM32_PLLCFG_PLLR_ENABLED /* 'SAIPLL1' is used to generate the 48 MHz clock, since we can't * do that with the main PLL's N value. We set N = 12, and enable @@ -250,68 +250,68 @@ * that is selected via a #define here, like all these other params. */ -#define STM32L4_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(12) -#define STM32L4_PLLSAI1CFG_PLLP 0 -#undef STM32L4_PLLSAI1CFG_PLLP_ENABLED -#define STM32L4_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_4 -#define STM32L4_PLLSAI1CFG_PLLQ_ENABLED -#define STM32L4_PLLSAI1CFG_PLLR 0 -#undef STM32L4_PLLSAI1CFG_PLLR_ENABLED +#define STM32_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(12) +#define STM32_PLLSAI1CFG_PLLP 0 +#undef STM32_PLLSAI1CFG_PLLP_ENABLED +#define STM32_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_4 +#define STM32_PLLSAI1CFG_PLLQ_ENABLED +#define STM32_PLLSAI1CFG_PLLR 0 +#undef STM32_PLLSAI1CFG_PLLR_ENABLED /* 'SAIPLL2' is not used in this application */ -#define STM32L4_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) -#define STM32L4_PLLSAI2CFG_PLLP 0 -#undef STM32L4_PLLSAI2CFG_PLLP_ENABLED -#define STM32L4_PLLSAI2CFG_PLLR 0 -#undef STM32L4_PLLSAI2CFG_PLLR_ENABLED +#define STM32_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) +#define STM32_PLLSAI2CFG_PLLP 0 +#undef STM32_PLLSAI2CFG_PLLP_ENABLED +#define STM32_PLLSAI2CFG_PLLR 0 +#undef STM32_PLLSAI2CFG_PLLR_ENABLED -#define STM32L4_SYSCLK_FREQUENCY 80000000ul +#define STM32_SYSCLK_FREQUENCY 80000000ul /* CLK48 will come from PLLSAI1 (implicitly Q) */ -#define STM32L4_USE_CLK48 -#define STM32L4_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 +#define STM32_USE_CLK48 +#define STM32_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 /* enable the LSE oscillator, used automatically trim the MSI, and for RTC */ -#define STM32L4_USE_LSE 1 +#define STM32_USE_LSE 1 /* AHB clock (HCLK) is SYSCLK (80MHz) */ -#define STM32L4_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ -#define STM32L4_HCLK_FREQUENCY STM32L4_SYSCLK_FREQUENCY +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY /* APB1 clock (PCLK1) is HCLK/1 (80MHz) */ -#define STM32L4_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ -#define STM32L4_PCLK1_FREQUENCY (STM32L4_HCLK_FREQUENCY / 1) +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY / 1) /* Timers driven from APB1 will be twice PCLK1 */ /* REVISIT : this can be configured */ -#define STM32L4_APB1_TIM2_CLKIN (2 * STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM3_CLKIN (2 * STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM4_CLKIN (2 * STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM5_CLKIN (2 * STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM6_CLKIN (2 * STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM7_CLKIN (2 * STM32L4_PCLK1_FREQUENCY) +#define STM32_APB1_TIM2_CLKIN (2 * STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (2 * STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (2 * STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM5_CLKIN (2 * STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (2 * STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (2 * STM32_PCLK1_FREQUENCY) /* APB2 clock (PCLK2) is HCLK (80MHz) */ -#define STM32L4_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ -#define STM32L4_PCLK2_FREQUENCY (STM32L4_HCLK_FREQUENCY / 1) +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ +#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY / 1) /* Timers driven from APB2 will be twice PCLK2 */ /* REVISIT : this can be configured */ -#define STM32L4_APB2_TIM1_CLKIN (2*STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM8_CLKIN (2*STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM15_CLKIN (2*STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM16_CLKIN (2*STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM17_CLKIN (2*STM32L4_PCLK2_FREQUENCY) +#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM15_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM16_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM17_CLKIN (2*STM32_PCLK2_FREQUENCY) /* Timer Frequencies, if APBx is set to 1, frequency is same to APBx * otherwise frequency is 2xAPBx. @@ -326,7 +326,7 @@ /* Use the HSE */ -#define STM32L4_BOARD_USEHSE 1 +#define STM32_BOARD_USEHSE 1 /* XXX sysclk mux = pllclk */ @@ -334,81 +334,81 @@ /* Prescaler common to all PLL inputs */ -#define STM32L4_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) /* 'main' PLL config; we use this to generate our system clock */ -#define STM32L4_PLLCFG_PLLN RCC_PLLCFG_PLLN(20) -#define STM32L4_PLLCFG_PLLP 0 -#undef STM32L4_PLLCFG_PLLP_ENABLED -#define STM32L4_PLLCFG_PLLQ 0 -#undef STM32L4_PLLCFG_PLLQ_ENABLED -#define STM32L4_PLLCFG_PLLR RCC_PLLCFG_PLLR_2 -#define STM32L4_PLLCFG_PLLR_ENABLED +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(20) +#define STM32_PLLCFG_PLLP 0 +#undef STM32_PLLCFG_PLLP_ENABLED +#define STM32_PLLCFG_PLLQ 0 +#undef STM32_PLLCFG_PLLQ_ENABLED +#define STM32_PLLCFG_PLLR RCC_PLLCFG_PLLR_2 +#define STM32_PLLCFG_PLLR_ENABLED /* 'SAIPLL1' is used to generate the 48 MHz clock */ -#define STM32L4_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(12) -#define STM32L4_PLLSAI1CFG_PLLP 0 -#undef STM32L4_PLLSAI1CFG_PLLP_ENABLED -#define STM32L4_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_2 -#define STM32L4_PLLSAI1CFG_PLLQ_ENABLED -#define STM32L4_PLLSAI1CFG_PLLR 0 -#undef STM32L4_PLLSAI1CFG_PLLR_ENABLED +#define STM32_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(12) +#define STM32_PLLSAI1CFG_PLLP 0 +#undef STM32_PLLSAI1CFG_PLLP_ENABLED +#define STM32_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_2 +#define STM32_PLLSAI1CFG_PLLQ_ENABLED +#define STM32_PLLSAI1CFG_PLLR 0 +#undef STM32_PLLSAI1CFG_PLLR_ENABLED /* 'SAIPLL2' is not used in this application */ -#define STM32L4_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) -#define STM32L4_PLLSAI2CFG_PLLP 0 -#undef STM32L4_PLLSAI2CFG_PLLP_ENABLED -#define STM32L4_PLLSAI2CFG_PLLR 0 -#undef STM32L4_PLLSAI2CFG_PLLR_ENABLED +#define STM32_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) +#define STM32_PLLSAI2CFG_PLLP 0 +#undef STM32_PLLSAI2CFG_PLLP_ENABLED +#define STM32_PLLSAI2CFG_PLLR 0 +#undef STM32_PLLSAI2CFG_PLLR_ENABLED -#define STM32L4_SYSCLK_FREQUENCY 80000000ul +#define STM32_SYSCLK_FREQUENCY 80000000ul /* Enable CLK48; get it from PLLSAI1 */ -#define STM32L4_USE_CLK48 -#define STM32L4_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 +#define STM32_USE_CLK48 +#define STM32_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 /* Enable LSE (for the RTC) */ -#define STM32L4_USE_LSE 1 +#define STM32_USE_LSE 1 /* Configure the HCLK divisor (for the AHB bus, core, memory, and DMA */ -#define STM32L4_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ -#define STM32L4_HCLK_FREQUENCY STM32L4_SYSCLK_FREQUENCY +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY /* Configure the APB1 prescaler */ -#define STM32L4_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ -#define STM32L4_PCLK1_FREQUENCY (STM32L4_HCLK_FREQUENCY/1) +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/1) -#define STM32L4_APB1_TIM2_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM3_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM4_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM5_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM6_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM7_CLKIN (2*STM32L4_PCLK1_FREQUENCY) +#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) /* Configure the APB2 prescaler */ -#define STM32L4_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ -#define STM32L4_PCLK2_FREQUENCY (STM32L4_HCLK_FREQUENCY/1) +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ +#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/1) -#define STM32L4_APB2_TIM1_CLKIN (2*STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM8_CLKIN (2*STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM15_CLKIN (2*STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM16_CLKIN (2*STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM17_CLKIN (2*STM32L4_PCLK2_FREQUENCY) +#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM15_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM16_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM17_CLKIN (2*STM32_PCLK2_FREQUENCY) #elif defined(MSI_CLOCK_CONFIG) /* Use the MSI; frequ = 4 MHz; autotrim from LSE */ -#define STM32L4_BOARD_USEMSI 1 -#define STM32L4_BOARD_MSIRANGE RCC_CR_MSIRANGE_4M +#define STM32_BOARD_USEMSI 1 +#define STM32_BOARD_MSIRANGE RCC_CR_MSIRANGE_4M /* XXX sysclk mux = pllclk */ @@ -416,74 +416,74 @@ /* prescaler common to all PLL inputs */ -#define STM32L4_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) /* 'main' PLL config; we use this to generate our system clock */ -#define STM32L4_PLLCFG_PLLN RCC_PLLCFG_PLLN(40) -#define STM32L4_PLLCFG_PLLP 0 -#undef STM32L4_PLLCFG_PLLP_ENABLED -#define STM32L4_PLLCFG_PLLQ 0 -#undef STM32L4_PLLCFG_PLLQ_ENABLED -#define STM32L4_PLLCFG_PLLR RCC_PLLCFG_PLLR_2 -#define STM32L4_PLLCFG_PLLR_ENABLED +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(40) +#define STM32_PLLCFG_PLLP 0 +#undef STM32_PLLCFG_PLLP_ENABLED +#define STM32_PLLCFG_PLLQ 0 +#undef STM32_PLLCFG_PLLQ_ENABLED +#define STM32_PLLCFG_PLLR RCC_PLLCFG_PLLR_2 +#define STM32_PLLCFG_PLLR_ENABLED /* 'SAIPLL1' is used to generate the 48 MHz clock */ -#define STM32L4_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(24) -#define STM32L4_PLLSAI1CFG_PLLP 0 -#undef STM32L4_PLLSAI1CFG_PLLP_ENABLED -#define STM32L4_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_2 -#define STM32L4_PLLSAI1CFG_PLLQ_ENABLED -#define STM32L4_PLLSAI1CFG_PLLR 0 -#undef STM32L4_PLLSAI1CFG_PLLR_ENABLED +#define STM32_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(24) +#define STM32_PLLSAI1CFG_PLLP 0 +#undef STM32_PLLSAI1CFG_PLLP_ENABLED +#define STM32_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_2 +#define STM32_PLLSAI1CFG_PLLQ_ENABLED +#define STM32_PLLSAI1CFG_PLLR 0 +#undef STM32_PLLSAI1CFG_PLLR_ENABLED /* 'SAIPLL2' is not used in this application */ -#define STM32L4_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) -#define STM32L4_PLLSAI2CFG_PLLP 0 -#undef STM32L4_PLLSAI2CFG_PLLP_ENABLED -#define STM32L4_PLLSAI2CFG_PLLR 0 -#undef STM32L4_PLLSAI2CFG_PLLR_ENABLED +#define STM32_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) +#define STM32_PLLSAI2CFG_PLLP 0 +#undef STM32_PLLSAI2CFG_PLLP_ENABLED +#define STM32_PLLSAI2CFG_PLLR 0 +#undef STM32_PLLSAI2CFG_PLLR_ENABLED -#define STM32L4_SYSCLK_FREQUENCY 80000000ul +#define STM32_SYSCLK_FREQUENCY 80000000ul /* Enable CLK48; get it from PLLSAI1 */ -#define STM32L4_USE_CLK48 -#define STM32L4_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 +#define STM32_USE_CLK48 +#define STM32_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 /* Enable LSE (for the RTC) */ -#define STM32L4_USE_LSE 1 +#define STM32_USE_LSE 1 /* Configure the HCLK divisor (for the AHB bus, core, memory, and DMA */ -#define STM32L4_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ -#define STM32L4_HCLK_FREQUENCY STM32L4_SYSCLK_FREQUENCY +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY /* Configure the APB1 prescaler */ -#define STM32L4_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ -#define STM32L4_PCLK1_FREQUENCY (STM32L4_HCLK_FREQUENCY/1) +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/1) -#define STM32L4_APB1_TIM2_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM3_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM4_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM5_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM6_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM7_CLKIN (2*STM32L4_PCLK1_FREQUENCY) +#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) /* Configure the APB2 prescaler */ -#define STM32L4_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ -#define STM32L4_PCLK2_FREQUENCY (STM32L4_HCLK_FREQUENCY/1) +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ +#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/1) -#define STM32L4_APB2_TIM1_CLKIN (2*STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM8_CLKIN (2*STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM15_CLKIN (2*STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM16_CLKIN (2*STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM17_CLKIN (2*STM32L4_PCLK2_FREQUENCY) +#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM15_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM16_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM17_CLKIN (2*STM32_PCLK2_FREQUENCY) #endif @@ -492,19 +492,19 @@ * Note: TIM1,8,15,16,17 are on APB2, others on APB1 */ -#define BOARD_TIM1_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM2_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2) -#define BOARD_TIM3_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2) -#define BOARD_TIM4_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2) -#define BOARD_TIM5_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2) -#define BOARD_TIM6_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2) -#define BOARD_TIM7_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2) -#define BOARD_TIM8_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM15_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM16_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM17_FREQUENCY STM32L4_HCLK_FREQUENCY -#define STM32L4_LPTIM1_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2) -#define STM32L4_LPTIM2_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2) +#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM2_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM3_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM4_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM5_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM6_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM7_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM15_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM16_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM17_FREQUENCY STM32_HCLK_FREQUENCY +#define STM32_LPTIM1_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define STM32_LPTIM2_FREQUENCY (STM32_HCLK_FREQUENCY / 2) /**************************************************************************** * Public Data @@ -531,4 +531,4 @@ extern "C" #endif #endif /* __ASSEMBLY__ */ -#endif /* __BOARDS_ARM_STM32L4_NUCLEO_L476RG_INCLUDE_NUCLEO_L476RG_H */ +#endif /* __BOARDS_ARM_STM32_NUCLEO_L476RG_INCLUDE_NUCLEO_L476RG_H */ diff --git a/boards/arm/stm32l4/nucleo-l476rg/src/Make.defs b/boards/arm/stm32l4/nucleo-l476rg/src/Make.defs new file mode 100644 index 0000000000000..5950a0e16c516 --- /dev/null +++ b/boards/arm/stm32l4/nucleo-l476rg/src/Make.defs @@ -0,0 +1,122 @@ +############################################################################ +# boards/arm/stm32l4/nucleo-l476rg/src/Makefile +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +CSRCS = stm32_boot.c stm32_bringup.c stm32_spi.c + +ifeq ($(CONFIG_ARCH_LEDS),y) +CSRCS += stm32_autoleds.c +else +CSRCS += stm32_userleds.c +endif + +ifeq ($(CONFIG_ARCH_BUTTONS),y) +CSRCS += stm32_buttons.c +endif + +ifeq ($(CONFIG_WL_CC1101),y) +CSRCS += stm32_cc1101.c +endif + +ifeq ($(CONFIG_ADC),y) +CSRCS += stm32_adc.c +ifeq ($(CONFIG_INPUT_AJOYSTICK),y) +CSRCS += stm32_ajoystick.c +endif +endif + +# Ben vd Veen (DisruptiveNL) -- 31-03-2018 +ifeq ($(CONFIG_DEV_GPIO),y) +CSRCS += stm32_gpio.c +endif + +# Ben vd Veen (DisruptiveNL) -- 31-03-2018 +ifeq ($(CONFIG_CAN),y) +CSRCS += stm32_can.c +endif + +ifeq ($(CONFIG_MMCSD_SPI),y) +CSRCS += stm32_spimmcsd.c +endif + +ifeq ($(CONFIG_LCD_PCD8544),y) +CSRCS += stm32_pcd8544.c +endif + +ifeq ($(CONFIG_SENSORS_QENCODER),y) +CSRCS += stm32_qencoder.c +endif + +ifeq ($(CONFIG_SENSORS_HTS221),y) +CSRCS += stm32_hts221.c +endif + +ifeq ($(CONFIG_SENSORS_LSM6DSL),y) +CSRCS += stm32_lsm6dsl.c +endif + +ifeq ($(CONFIG_SENSORS_LSM303AGR),y) +CSRCS += stm32_lsm303agr.c +endif + +ifeq ($(CONFIG_SENSORS_AS726X),y) +CSRCS += stm32_as726x.c +endif + +ifeq ($(CONFIG_SENSORS_BMP180),y) +CSRCS += stm32_bmp180.c +endif + +ifeq ($(CONFIG_SENSORS_BMP280),y) + CSRCS += stm32_bmp280.c +endif + +ifeq ($(CONFIG_SENSORS_MPU9250),y) + CSRCS += stm32_mpu9250.c +endif + +ifeq ($(CONFIG_PWM),y) +CSRCS += stm32_pwm.c +endif + +ifeq ($(CONFIG_TIMER),y) +CSRCS += stm32_timer.c +endif + +ifeq ($(CONFIG_BOARDCTL_IOCTL),y) +CSRCS += stm32_ioctl.c +endif + +ifeq ($(CONFIG_BOARDCTL_UNIQUEID),y) +CSRCS += stm32_uid.c +endif + +ifneq ($(CONFIG_STM32_ETHMAC),y) +ifeq ($(CONFIG_NETDEVICES),y) +CSRCS += stm32_netinit.c +endif +endif + +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32l4/nucleo-l476rg/src/Makefile b/boards/arm/stm32l4/nucleo-l476rg/src/Makefile deleted file mode 100644 index d51f9740937ce..0000000000000 --- a/boards/arm/stm32l4/nucleo-l476rg/src/Makefile +++ /dev/null @@ -1,120 +0,0 @@ -############################################################################ -# boards/arm/stm32l4/nucleo-l476rg/src/Makefile -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/Make.defs - -CSRCS = stm32_boot.c stm32_bringup.c stm32_spi.c - -ifeq ($(CONFIG_ARCH_LEDS),y) -CSRCS += stm32_autoleds.c -else -CSRCS += stm32_userleds.c -endif - -ifeq ($(CONFIG_ARCH_BUTTONS),y) -CSRCS += stm32_buttons.c -endif - -ifeq ($(CONFIG_WL_CC1101),y) -CSRCS += stm32_cc1101.c -endif - -ifeq ($(CONFIG_ADC),y) -CSRCS += stm32_adc.c -ifeq ($(CONFIG_INPUT_AJOYSTICK),y) -CSRCS += stm32_ajoystick.c -endif -endif - -# Ben vd Veen (DisruptiveNL) -- 31-03-2018 -ifeq ($(CONFIG_DEV_GPIO),y) -CSRCS += stm32_gpio.c -endif - -# Ben vd Veen (DisruptiveNL) -- 31-03-2018 -ifeq ($(CONFIG_CAN),y) -CSRCS += stm32_can.c -endif - -ifeq ($(CONFIG_MMCSD_SPI),y) -CSRCS += stm32_spimmcsd.c -endif - -ifeq ($(CONFIG_LCD_PCD8544),y) -CSRCS += stm32_pcd8544.c -endif - -ifeq ($(CONFIG_SENSORS_QENCODER),y) -CSRCS += stm32_qencoder.c -endif - -ifeq ($(CONFIG_SENSORS_HTS221),y) -CSRCS += stm32_hts221.c -endif - -ifeq ($(CONFIG_SENSORS_LSM6DSL),y) -CSRCS += stm32_lsm6dsl.c -endif - -ifeq ($(CONFIG_SENSORS_LSM303AGR),y) -CSRCS += stm32_lsm303agr.c -endif - -ifeq ($(CONFIG_SENSORS_AS726X),y) -CSRCS += stm32_as726x.c -endif - -ifeq ($(CONFIG_SENSORS_BMP180),y) -CSRCS += stm32_bmp180.c -endif - -ifeq ($(CONFIG_SENSORS_BMP280),y) - CSRCS += stm32_bmp280.c -endif - -ifeq ($(CONFIG_SENSORS_MPU9250),y) - CSRCS += stm32_mpu9250.c -endif - -ifeq ($(CONFIG_PWM),y) -CSRCS += stm32_pwm.c -endif - -ifeq ($(CONFIG_TIMER),y) -CSRCS += stm32_timer.c -endif - -ifeq ($(CONFIG_BOARDCTL_IOCTL),y) -CSRCS += stm32_ioctl.c -endif - -ifeq ($(CONFIG_BOARDCTL_UNIQUEID),y) -CSRCS += stm32_uid.c -endif - -ifneq ($(CONFIG_STM32_ETHMAC),y) -ifeq ($(CONFIG_NETDEVICES),y) -CSRCS += stm32_netinit.c -endif -endif - -include $(TOPDIR)/boards/Board.mk diff --git a/boards/arm/stm32l4/nucleo-l476rg/src/nucleo-l476rg.h b/boards/arm/stm32l4/nucleo-l476rg/src/nucleo-l476rg.h index adf24d58b9ae2..aa3e277de64e1 100644 --- a/boards/arm/stm32l4/nucleo-l476rg/src/nucleo-l476rg.h +++ b/boards/arm/stm32l4/nucleo-l476rg/src/nucleo-l476rg.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32L4_NUCLEO_L476RG_SRC_NUCLEO_L476RG_H -#define __BOARDS_ARM_STM32L4_NUCLEO_L476RG_SRC_NUCLEO_L476RG_H +#ifndef __BOARDS_ARM_STM32_NUCLEO_L476RG_SRC_NUCLEO_L476RG_H +#define __BOARDS_ARM_STM32_NUCLEO_L476RG_SRC_NUCLEO_L476RG_H /**************************************************************************** * Included Files @@ -61,12 +61,12 @@ # undef HAVE_RTC_DRIVER #endif -#if !defined(CONFIG_STM32L4_SPI1) || !defined(CONFIG_MMCSD) || \ +#if !defined(CONFIG_STM32_SPI1) || !defined(CONFIG_MMCSD) || \ !defined(CONFIG_MMCSD_SPI) # undef HAVE_MMCSD_SPI #endif -#if !defined(CONFIG_STM32L4_SDIO) || !defined(CONFIG_MMCSD) || \ +#if !defined(CONFIG_STM32_SDIO) || !defined(CONFIG_MMCSD) || \ !defined(CONFIG_MMCSD_SDIO) # undef HAVE_MMCSD_SDIO #endif @@ -265,10 +265,10 @@ /* Global driver instances */ -#ifdef CONFIG_STM32L4_SPI1 +#ifdef CONFIG_STM32_SPI1 extern struct spi_dev_s *g_spi1; #endif -#ifdef CONFIG_STM32L4_SPI2 +#ifdef CONFIG_STM32_SPI2 extern struct spi_dev_s *g_spi2; #endif #ifdef HAVE_MMCSD_SDIO @@ -293,27 +293,27 @@ extern struct sdio_dev_s *g_sdio; int stm32_bringup(void); /**************************************************************************** - * Name: stm32l4_spiinitialize + * Name: stm32_spiinitialize * * Description: * Called to configure SPI chip select GPIO pins. * ****************************************************************************/ -void stm32l4_spiinitialize(void); +void stm32_spiinitialize(void); /**************************************************************************** - * Name: stm32l4_usbinitialize + * Name: stm32_usbinitialize * * Description: * Called to setup USB-related GPIO pins. * ****************************************************************************/ -void stm32l4_usbinitialize(void); +void stm32_usbinitialize(void); /**************************************************************************** - * Name: stm32l4_gpio_initialize + * Name: stm32_gpio_initialize * * Description: * Initialize GPIO drivers for use with /apps/examples/gpio @@ -322,11 +322,11 @@ void stm32l4_usbinitialize(void); ****************************************************************************/ #ifdef CONFIG_DEV_GPIO -int stm32l4_gpio_initialize(void); +int stm32_gpio_initialize(void); #endif /**************************************************************************** - * Name: stm32l4_can_setup -- DisruptiveNL + * Name: stm32_can_setup -- DisruptiveNL * * Description: * Initialize CAN and register the CAN device. @@ -335,11 +335,11 @@ int stm32l4_gpio_initialize(void); ****************************************************************************/ #ifdef CONFIG_CAN -int stm32l4_can_setup(void); +int stm32_can_setup(void); #endif /**************************************************************************** - * Name: stm32l4_pwm_setup + * Name: stm32_pwm_setup * * Description: * Initialize PWM and register the PWM device. @@ -347,11 +347,11 @@ int stm32l4_can_setup(void); ****************************************************************************/ #ifdef CONFIG_PWM -int stm32l4_pwm_setup(void); +int stm32_pwm_setup(void); #endif /**************************************************************************** - * Name: stm32l4_adc_setup + * Name: stm32_adc_setup * * Description: * Initialize ADC and register the ADC driver. @@ -359,7 +359,7 @@ int stm32l4_pwm_setup(void); ****************************************************************************/ #ifdef CONFIG_ADC -int stm32l4_adc_setup(void); +int stm32_adc_setup(void); #endif /**************************************************************************** @@ -375,7 +375,7 @@ int board_ajoy_initialize(void); #endif /**************************************************************************** - * Name: stm32l4_mmcsd_initialize + * Name: stm32_mmcsd_initialize * * Description: * Initializes SPI-based SD card @@ -383,7 +383,7 @@ int board_ajoy_initialize(void); ****************************************************************************/ #ifdef CONFIG_MMCSD_SPI -int stm32l4_mmcsd_initialize(int minor); +int stm32_mmcsd_initialize(int minor); #endif /**************************************************************************** @@ -399,7 +399,7 @@ int board_timer_driver_initialize(const char *devpath, int timer); #endif /**************************************************************************** - * Name: stm32l4_qencoder_initialize + * Name: stm32_qencoder_initialize * * Description: * Initialize and register a qencoder @@ -407,11 +407,11 @@ int board_timer_driver_initialize(const char *devpath, int timer); ****************************************************************************/ #ifdef CONFIG_SENSORS_QENCODER -int stm32l4_qencoder_initialize(const char *devpath, int timer); +int stm32_qencoder_initialize(const char *devpath, int timer); #endif /**************************************************************************** - * Name: stm32l4_cc1101_initialize + * Name: stm32_cc1101_initialize * * Description: * Initialize and register the cc1101 radio driver @@ -419,7 +419,7 @@ int stm32l4_qencoder_initialize(const char *devpath, int timer); ****************************************************************************/ #ifdef CONFIG_WL_CC1101 -int stm32l4_cc1101_initialize(void); +int stm32_cc1101_initialize(void); #endif /**************************************************************************** @@ -446,4 +446,4 @@ int stm32_as726xinitialize(const char *devpath); int stm32_bmp180initialize(const char *devpath); #endif -#endif /* __BOARDS_ARM_STM32L4_NUCLEO_L476RG_SRC_NUCLEO_L476RG_H */ +#endif /* __BOARDS_ARM_STM32_NUCLEO_L476RG_SRC_NUCLEO_L476RG_H */ diff --git a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_adc.c b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_adc.c index 4fc545de40ef2..d3e99dada1ca7 100644 --- a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_adc.c +++ b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_adc.c @@ -38,7 +38,7 @@ #include "stm32l4_adc.h" #include "nucleo-l476rg.h" -#ifdef CONFIG_STM32L4_ADC1 +#ifdef CONFIG_STM32_ADC1 /**************************************************************************** * Pre-processor Definitions @@ -103,14 +103,14 @@ static const uint32_t g_adc1_pinlist[ADC1_NCHANNELS] = ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_adc_setup + * Name: stm32_adc_setup * * Description: * Initialize ADC and register the ADC driver. * ****************************************************************************/ -int stm32l4_adc_setup(void) +int stm32_adc_setup(void) { struct adc_dev_s *adc; int ret; @@ -120,12 +120,12 @@ int stm32l4_adc_setup(void) for (i = 0; i < ADC1_NCHANNELS; i++) { - stm32l4_configgpio(g_adc1_pinlist[i]); + stm32_configgpio(g_adc1_pinlist[i]); } - /* Call stm32l4_adc_initialize() to get an instance of the ADC interface */ + /* Call stm32_adc_initialize() to get an instance of the ADC interface */ - adc = stm32l4_adc_initialize(1, g_adc1_chanlist, ADC1_NCHANNELS); + adc = stm32_adc_initialize(1, g_adc1_chanlist, ADC1_NCHANNELS); if (adc == NULL) { aerr("ERROR: Failed to get ADC interface\n"); @@ -144,4 +144,4 @@ int stm32l4_adc_setup(void) return OK; } -#endif /* CONFIG_STM32L4_ADC1 */ +#endif /* CONFIG_STM32_ADC1 */ diff --git a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_ajoystick.c b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_ajoystick.c index 4b1f6a776a15e..96fc9df7c48e6 100644 --- a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_ajoystick.c +++ b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_ajoystick.c @@ -51,8 +51,8 @@ # if !defined(CONFIG_ADC) # error CONFIG_ADC is required for the Itead joystick # undef CONFIG_INPUT_AJOYSTICK -# elif !defined(CONFIG_STM32L4_ADC1) -# error CONFIG_STM32L4_ADC1 is required for Itead joystick +# elif !defined(CONFIG_STM32_ADC1) +# error CONFIG_STM32_ADC1 is required for Itead joystick # undef CONFIG_INPUT_AJOYSTICK # endif #endif /* CONFIG_INPUT_AJOYSTICK */ @@ -298,7 +298,7 @@ ajoy_buttons(const struct ajoy_lowerhalf_s *lower) * button is pressed. */ - if (!stm32l4_gpioread(g_joygpio[i])) + if (!stm32_gpioread(g_joygpio[i])) { ret |= (1 << i); } @@ -368,7 +368,7 @@ static void ajoy_enable(const struct ajoy_lowerhalf_s *lower, iinfo("GPIO %d: rising: %d falling: %d\n", i, rising, falling); - stm32l4_gpiosetevent(g_joygpio[i], rising, falling, + stm32_gpiosetevent(g_joygpio[i], rising, falling, true, ajoy_interrupt, NULL); } } @@ -395,7 +395,7 @@ static void ajoy_disable(void) flags = up_irq_save(); for (i = 0; i < AJOY_NGPIOS; i++) { - stm32l4_gpiosetevent(g_joygpio[i], false, false, false, NULL, NULL); + stm32_gpiosetevent(g_joygpio[i], false, false, false, NULL, NULL); } up_irq_restore(flags); @@ -461,14 +461,14 @@ int board_ajoy_initialize(void) /* Configure the GPIO pins as interrupting inputs. NOTE: This is * unnecessary for interrupting pins since it will also be done by - * stm32l4_gpiosetevent(). + * stm32_gpiosetevent(). */ for (i = 0; i < AJOY_NGPIOS; i++) { /* Configure the PIO as an input */ - stm32l4_configgpio(g_joygpio[i]); + stm32_configgpio(g_joygpio[i]); } /* Register the joystick device as /dev/ajoy0 */ diff --git a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_as726x.c b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_as726x.c index 01913bd594e29..12bb3c4aedc8b 100644 --- a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_as726x.c +++ b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_as726x.c @@ -46,7 +46,7 @@ #include #include -#include "stm32l4.h" +#include "stm32.h" #include "stm32l4_i2c.h" #include "nucleo-l476rg.h" @@ -83,7 +83,7 @@ int stm32_as726xinitialize(const char *devpath) /* Initialize I2C */ - i2c = stm32l4_i2cbus_initialize(AS726X_I2C_PORTNO); + i2c = stm32_i2cbus_initialize(AS726X_I2C_PORTNO); if (!i2c) { diff --git a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_autoleds.c b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_autoleds.c index b3af9c5a740ae..fd2c0f744c82c 100644 --- a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_autoleds.c +++ b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_autoleds.c @@ -35,7 +35,7 @@ #include "chip.h" #include "arm_internal.h" -#include "stm32l4.h" +#include "stm32.h" #include "nucleo-l476rg.h" #ifdef CONFIG_ARCH_LEDS @@ -52,7 +52,7 @@ void board_autoled_initialize(void) { /* Configure LD2 GPIO for output */ - stm32l4_configgpio(GPIO_LD2); + stm32_configgpio(GPIO_LD2); } /**************************************************************************** @@ -63,7 +63,7 @@ void board_autoled_on(int led) { if (led == 1) { - stm32l4_gpiowrite(GPIO_LD2, true); + stm32_gpiowrite(GPIO_LD2, true); } } @@ -75,7 +75,7 @@ void board_autoled_off(int led) { if (led == 1) { - stm32l4_gpiowrite(GPIO_LD2, false); + stm32_gpiowrite(GPIO_LD2, false); } } diff --git a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_bmp180.c b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_bmp180.c index d6fb30862285f..208b8c59a337d 100644 --- a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_bmp180.c +++ b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_bmp180.c @@ -32,7 +32,7 @@ #include #include -#include "stm32l4.h" +#include "stm32.h" #include "stm32l4_i2c.h" #include "nucleo-l476rg.h" @@ -65,7 +65,7 @@ int stm32_bmp180initialize(const char *devpath) /* Initialize I2C */ - i2c = stm32l4_i2cbus_initialize(BMP180_I2C_PORTNO); + i2c = stm32_i2cbus_initialize(BMP180_I2C_PORTNO); if (!i2c) { diff --git a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_bmp280.c b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_bmp280.c index b5f07c0a8f03c..55b74b50d38c8 100644 --- a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_bmp280.c +++ b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_bmp280.c @@ -33,7 +33,7 @@ #include #include -#include "stm32l4.h" +#include "stm32.h" #include "stm32l4_i2c.h" #include "stm32_bmp280.h" @@ -89,7 +89,7 @@ int board_bmp280_initialize(int devno, int busno) /* Initialize BMP280 */ - i2c = stm32l4_i2cbus_initialize(busno); + i2c = stm32_i2cbus_initialize(busno); if (i2c) { diff --git a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_bmp280.h b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_bmp280.h index 72b1aa089f8c3..477632532b443 100644 --- a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_bmp280.h +++ b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_bmp280.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32L4_NUCLEO_L476RG_INCLUDE_NUCLEO_L476RG_BMP280_H -#define __BOARDS_ARM_STM32L4_NUCLEO_L476RG_INCLUDE_NUCLEO_L476RG_BMP280_H +#ifndef __BOARDS_ARM_STM32_NUCLEO_L476RG_INCLUDE_NUCLEO_L476RG_BMP280_H +#define __BOARDS_ARM_STM32_NUCLEO_L476RG_INCLUDE_NUCLEO_L476RG_BMP280_H /**************************************************************************** * Included Files @@ -83,4 +83,4 @@ int board_bmp280_initialize(int devno, int busno); } #endif -#endif /* __BOARDS_ARM_STM32L4_NUCLEO_L476RG_INCLUDE_NUCLEO_L476RG_BMP280_H */ +#endif /* __BOARDS_ARM_STM32_NUCLEO_L476RG_INCLUDE_NUCLEO_L476RG_BMP280_H */ diff --git a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_boot.c b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_boot.c index 4800e811aa07e..93bede4772f40 100644 --- a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_boot.c +++ b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_boot.c @@ -42,7 +42,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_board_initialize + * Name: stm32_board_initialize * * Description: * All STM32L4 architectures must provide the following entry point. This @@ -52,7 +52,7 @@ * ****************************************************************************/ -void stm32l4_board_initialize(void) +void stm32_board_initialize(void) { /* Configure on-board LEDs if LED support has been selected. */ @@ -61,20 +61,20 @@ void stm32l4_board_initialize(void) #endif /* Configure SPI chip selects if 1) SP2 is not disabled, and 2) the weak - * function stm32l4_spiinitialize() has been brought into the link. + * function stm32_spiinitialize() has been brought into the link. */ -#if defined(CONFIG_STM32L4_SPI1) || defined(CONFIG_STM32L4_SPI2) || defined(CONFIG_STM32L4_SPI3) - stm32l4_spiinitialize(); +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || defined(CONFIG_STM32_SPI3) + stm32_spiinitialize(); #endif /* Initialize USB is 1) USBDEV is selected, 2) the USB controller is not - * disabled, and 3) the weak function stm32l4_usbinitialize() has been + * disabled, and 3) the weak function stm32_usbinitialize() has been * brought into the build. */ -#if defined(CONFIG_USBDEV) && defined(CONFIG_STM32L4_USB) - stm32l4_usbinitialize(); +#if defined(CONFIG_USBDEV) && defined(CONFIG_STM32_USB) + stm32_usbinitialize(); #endif } diff --git a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_bringup.c b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_bringup.c index 9864ec4040ad8..4b229423773ad 100644 --- a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_bringup.c +++ b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_bringup.c @@ -39,7 +39,7 @@ #include #include -#include +#include #include #include @@ -95,7 +95,7 @@ static void stm32_i2c_register(int bus) struct i2c_master_s *i2c; int ret; - i2c = stm32l4_i2cbus_initialize(bus); + i2c = stm32_i2cbus_initialize(bus); if (i2c == NULL) { syslog(LOG_ERR, "ERROR: Failed to get I2C%d interface\n", bus); @@ -107,7 +107,7 @@ static void stm32_i2c_register(int bus) { syslog(LOG_ERR, "ERROR: Failed to register I2C%d driver: %d\n", bus, ret); - stm32l4_i2cbus_uninitialize(i2c); + stm32_i2cbus_uninitialize(i2c); } } } @@ -178,7 +178,7 @@ int stm32_bringup(void) #ifdef HAVE_RTC_DRIVER /* Instantiate the STM32L4 lower-half RTC driver */ - rtclower = stm32l4_rtc_lowerhalf(); + rtclower = stm32_rtc_lowerhalf(); if (!rtclower) { serr("ERROR: Failed to instantiate the RTC lower-half driver\n"); @@ -261,28 +261,28 @@ int stm32_bringup(void) #ifdef CONFIG_PWM /* Initialize PWM and register the PWM device. */ - ret = stm32l4_pwm_setup(); + ret = stm32_pwm_setup(); if (ret < 0) { - syslog(LOG_ERR, "ERROR: stm32l4_pwm_setup() failed: %d\n", ret); + syslog(LOG_ERR, "ERROR: stm32_pwm_setup() failed: %d\n", ret); } #endif #ifdef CONFIG_ADC /* Initialize ADC and register the ADC driver. */ - ret = stm32l4_adc_setup(); + ret = stm32_adc_setup(); if (ret < 0) { - syslog(LOG_ERR, "ERROR: stm32l4_adc_setup failed: %d\n", ret); + syslog(LOG_ERR, "ERROR: stm32_adc_setup failed: %d\n", ret); } #endif #ifdef CONFIG_CAN - ret = stm32l4_can_setup(); + ret = stm32_can_setup(); if (ret < 0) { - syslog(LOG_ERR, "ERROR: stm32l4_can_setup failed: %d\n", ret); + syslog(LOG_ERR, "ERROR: stm32_can_setup failed: %d\n", ret); return ret; } #endif @@ -290,7 +290,7 @@ int stm32_bringup(void) /* Initialize MMC and register the MMC driver. */ #ifdef HAVE_MMCSD_SPI - ret = stm32l4_mmcsd_initialize(MMCSD_MINOR); + ret = stm32_mmcsd_initialize(MMCSD_MINOR); if (ret < 0) { syslog(LOG_ERR, "Failed to initialize SD slot %d: %d\n", ret); @@ -327,9 +327,9 @@ int stm32_bringup(void) index = 0; -#ifdef CONFIG_STM32L4_TIM1_QE +#ifdef CONFIG_STM32_TIM1_QE snprintf(buf, sizeof(buf), "/dev/qe%d", index++); - ret = stm32l4_qencoder_initialize(buf, 1); + ret = stm32_qencoder_initialize(buf, 1); if (ret < 0) { syslog(LOG_ERR, "ERROR: Failed to register the qencoder: %d\n", @@ -338,9 +338,9 @@ int stm32_bringup(void) } #endif -#ifdef CONFIG_STM32L4_TIM2_QE +#ifdef CONFIG_STM32_TIM2_QE snprintf(buf, sizeof(buf), "/dev/qe%d", index++); - ret = stm32l4_qencoder_initialize(buf, 2); + ret = stm32_qencoder_initialize(buf, 2); if (ret < 0) { syslog(LOG_ERR, "ERROR: Failed to register the qencoder: %d\n", @@ -349,9 +349,9 @@ int stm32_bringup(void) } #endif -#ifdef CONFIG_STM32L4_TIM3_QE +#ifdef CONFIG_STM32_TIM3_QE snprintf(buf, sizeof(buf), "/dev/qe%d", index++); - ret = stm32l4_qencoder_initialize(buf, 3); + ret = stm32_qencoder_initialize(buf, 3); if (ret < 0) { syslog(LOG_ERR, "ERROR: Failed to register the qencoder: %d\n", @@ -360,9 +360,9 @@ int stm32_bringup(void) } #endif -#ifdef CONFIG_STM32L4_TIM4_QE +#ifdef CONFIG_STM32_TIM4_QE snprintf(buf, sizeof(buf), "/dev/qe%d", index++); - ret = stm32l4_qencoder_initialize(buf, 4); + ret = stm32_qencoder_initialize(buf, 4); if (ret < 0) { syslog(LOG_ERR, "ERROR: Failed to register the qencoder: %d\n", @@ -371,9 +371,9 @@ int stm32_bringup(void) } #endif -#ifdef CONFIG_STM32L4_TIM5_QE +#ifdef CONFIG_STM32_TIM5_QE snprintf(buf, sizeof(buf), "/dev/qe%d", index++); - ret = stm32l4_qencoder_initialize(buf, 5); + ret = stm32_qencoder_initialize(buf, 5); if (ret < 0) { syslog(LOG_ERR, "ERROR: Failed to register the qencoder: %d\n", @@ -382,9 +382,9 @@ int stm32_bringup(void) } #endif -#ifdef CONFIG_STM32L4_TIM8_QE +#ifdef CONFIG_STM32_TIM8_QE snprintf(buf, sizeof(buf), "/dev/qe%d", index++); - ret = stm32l4_qencoder_initialize(buf, 8); + ret = stm32_qencoder_initialize(buf, 8); if (ret < 0) { syslog(LOG_ERR, "ERROR: Failed to register the qencoder: %d\n", @@ -395,7 +395,7 @@ int stm32_bringup(void) #endif /* CONFIG_SENSORS_QENCODER */ #ifdef CONFIG_SENSORS_HTS221 - ret = stm32l4_hts221_initialize("/dev/hts221"); + ret = stm32_hts221_initialize("/dev/hts221"); if (ret < 0) { serr("ERROR: Failed to initialize HTC221 driver: %d\n", ret); @@ -403,7 +403,7 @@ int stm32_bringup(void) #endif #ifdef CONFIG_SENSORS_LSM6DSL - ret = stm32l4_lsm6dsl_initialize("/dev/lsm6dsl0"); + ret = stm32_lsm6dsl_initialize("/dev/lsm6dsl0"); if (ret < 0) { serr("ERROR: Failed to initialize LSM6DSL driver: %d\n", ret); @@ -411,7 +411,7 @@ int stm32_bringup(void) #endif #ifdef CONFIG_SENSORS_LSM303AGR - ret = stm32l4_lsm303agr_initialize("/dev/lsm303mag0"); + ret = stm32_lsm303agr_initialize("/dev/lsm303mag0"); if (ret < 0) { serr("ERROR: Failed to initialize LSM303AGR driver: %d\n", ret); @@ -419,7 +419,7 @@ int stm32_bringup(void) #endif #ifdef CONFIG_DEV_GPIO - ret = stm32l4_gpio_initialize(); + ret = stm32_gpio_initialize(); if (ret < 0) { syslog(LOG_ERR, "Failed to initialize GPIO Driver: %d\n", ret); @@ -430,10 +430,10 @@ int stm32_bringup(void) #ifdef CONFIG_WL_CC1101 /* Initialize and register the cc1101 radio */ - ret = stm32l4_cc1101_initialize(); + ret = stm32_cc1101_initialize(); if (ret < 0) { - syslog(LOG_ERR, "ERROR: stm32l4_cc1101_initialize failed: %d\n", + syslog(LOG_ERR, "ERROR: stm32_cc1101_initialize failed: %d\n", ret); return ret; } diff --git a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_buttons.c b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_buttons.c index b44a8deaedc37..efcfb4efe31ce 100644 --- a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_buttons.c +++ b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_buttons.c @@ -58,7 +58,7 @@ uint32_t board_button_initialize(void) * also configured for the pin. */ - stm32l4_configgpio(GPIO_BTN_USER); + stm32_configgpio(GPIO_BTN_USER); return NUM_BUTTONS; } @@ -72,7 +72,7 @@ uint32_t board_buttons(void) * pressed. */ - bool released = stm32l4_gpioread(GPIO_BTN_USER); + bool released = stm32_gpioread(GPIO_BTN_USER); return !released; } @@ -105,7 +105,7 @@ int board_button_irq(int id, xcpt_t irqhandler, void *arg) if (id == BUTTON_USER) { - ret = stm32l4_gpiosetevent(GPIO_BTN_USER, true, true, true, + ret = stm32_gpiosetevent(GPIO_BTN_USER, true, true, true, irqhandler, arg); } diff --git a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_can.c b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_can.c index 7a59c087c87f7..117aa61f8f74c 100644 --- a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_can.c +++ b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_can.c @@ -43,11 +43,11 @@ * Pre-processor Definitions ****************************************************************************/ -#if defined(CONFIG_STM32L4_CAN1) +#if defined(CONFIG_STM32_CAN1) # warning "Both CAN1 and CAN2 are enabled. Only CAN1 is connected." #endif -#ifdef CONFIG_STM32L4_CAN1 +#ifdef CONFIG_STM32_CAN1 # define CAN_PORT 1 #endif @@ -56,22 +56,22 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_can_setup + * Name: stm32_can_setup * * Description: * Initialize CAN and register the CAN device * ****************************************************************************/ -int stm32l4_can_setup(void) +int stm32_can_setup(void) { -#ifdef CONFIG_STM32L4_CAN1 +#ifdef CONFIG_STM32_CAN1 struct can_dev_s *can; int ret; - /* Call stm32l4can_initialize() to get an instance of the CAN interface */ + /* Call stm32_caninitialize() to get an instance of the CAN interface */ - can = stm32l4can_initialize(CAN_PORT); + can = stm32_caninitialize(CAN_PORT); if (can == NULL) { canerr("ERROR: Failed to get CAN interface\n"); diff --git a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_cc1101.c b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_cc1101.c index 6a29402d6dfe2..c1bfb8febdb10 100644 --- a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_cc1101.c +++ b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_cc1101.c @@ -36,7 +36,7 @@ #include #include -#include "stm32l4.h" +#include "stm32.h" #include "nucleo-l476rg.h" #ifdef CONFIG_WL_CC1101 @@ -54,7 +54,7 @@ static void cc1101_wait(struct cc1101_dev_s *dev, uint32_t pin) { - while (stm32l4_gpioread(pin) == true) + while (stm32_gpioread(pin) == true) { } } @@ -70,11 +70,11 @@ static void cc1101_irq(struct cc1101_dev_s *dev, bool enable) { if (enable) { - stm32l4_gpiosetevent(dev->isr_pin, false, true, true, cc1101_isr, dev); + stm32_gpiosetevent(dev->isr_pin, false, true, true, cc1101_isr, dev); } else { - stm32l4_gpiosetevent(dev->isr_pin, false, true, true, NULL, NULL); + stm32_gpiosetevent(dev->isr_pin, false, true, true, NULL, NULL); } } @@ -94,19 +94,19 @@ static void cc1101_pwr(struct cc1101_dev_s *dev, bool enable) ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_cc1101_initialize + * Name: stm32_cc1101_initialize * * Description: * Initialize and register the cc1101 radio driver * ****************************************************************************/ -int stm32l4_cc1101_initialize(void) +int stm32_cc1101_initialize(void) { struct spi_dev_s *spi = NULL; struct cc1101_dev_s *dev = NULL; - spi = stm32l4_spibus_initialize(CONFIG_CC1101_SPIDEV); + spi = stm32_spibus_initialize(CONFIG_CC1101_SPIDEV); if (spi == NULL) { ierr("ERROR: Failed to initialize SPI bus %d\n", CONFIG_CC1101_SPIDEV); diff --git a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_gpio.c b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_gpio.c index f772ef0a32b25..473fc52a0b6aa 100644 --- a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_gpio.c +++ b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_gpio.c @@ -40,7 +40,7 @@ #include "chip.h" -#include +#include #include "nucleo-l476rg.h" #if defined(CONFIG_DEV_GPIO) && !defined(CONFIG_GPIO_LOWER_HALF) @@ -160,7 +160,7 @@ static int gpin_read(struct gpio_dev_s *dev, bool *value) DEBUGASSERT(stm32gpio->id < BOARD_NGPIOIN); gpioinfo("Reading...\n"); - *value = stm32l4_gpioread(g_gpioinputs[stm32gpio->id]); + *value = stm32_gpioread(g_gpioinputs[stm32gpio->id]); return OK; } @@ -173,7 +173,7 @@ static int gpout_read(struct gpio_dev_s *dev, bool *value) DEBUGASSERT(stm32gpio->id < BOARD_NGPIOOUT); gpioinfo("Reading...\n"); - *value = stm32l4_gpioread(g_gpiooutputs[stm32gpio->id]); + *value = stm32_gpioread(g_gpiooutputs[stm32gpio->id]); return OK; } @@ -186,7 +186,7 @@ static int gpout_write(struct gpio_dev_s *dev, bool value) DEBUGASSERT(stm32gpio->id < BOARD_NGPIOOUT); gpioinfo("Writing %d\n", (int)value); - stm32l4_gpiowrite(g_gpiooutputs[stm32gpio->id], value); + stm32_gpiowrite(g_gpiooutputs[stm32gpio->id], value); return OK; } @@ -199,7 +199,7 @@ static int gpint_read(struct gpio_dev_s *dev, bool *value) DEBUGASSERT(stm32gpint->stm32gpio.id < BOARD_NGPIOINT); gpioinfo("Reading int pin...\n"); - *value = stm32l4_gpioread(g_gpiointinputs[stm32gpint->stm32gpio.id]); + *value = stm32_gpioread(g_gpiointinputs[stm32gpint->stm32gpio.id]); return OK; } @@ -213,7 +213,7 @@ static int gpint_attach(struct gpio_dev_s *dev, /* Make sure the interrupt is disabled */ - stm32l4_gpiosetevent(g_gpiointinputs[stm32gpint->stm32gpio.id], false, + stm32_gpiosetevent(g_gpiointinputs[stm32gpint->stm32gpio.id], false, false, false, NULL, NULL); gpioinfo("Attach %p\n", callback); @@ -234,7 +234,7 @@ static int gpint_enable(struct gpio_dev_s *dev, bool enable) /* Configure the interrupt for rising edge */ - stm32l4_gpiosetevent(g_gpiointinputs[stm32gpint->stm32gpio.id], + stm32_gpiosetevent(g_gpiointinputs[stm32gpint->stm32gpio.id], true, false, false, stm32gpio_interrupt, &g_gpint[stm32gpint->stm32gpio.id]); } @@ -243,7 +243,7 @@ static int gpint_enable(struct gpio_dev_s *dev, bool enable) { gpioinfo("Disable the interrupt\n"); - stm32l4_gpiosetevent(g_gpiointinputs[stm32gpint->stm32gpio.id], + stm32_gpiosetevent(g_gpiointinputs[stm32gpint->stm32gpio.id], false, false, false, NULL, NULL); } @@ -255,14 +255,14 @@ static int gpint_enable(struct gpio_dev_s *dev, bool enable) ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_gpio_initialize + * Name: stm32_gpio_initialize * * Description: * Initialize GPIO drivers for use with /apps/examples/gpio * ****************************************************************************/ -int stm32l4_gpio_initialize(void) +int stm32_gpio_initialize(void) { int pincount = 0; int i; @@ -279,7 +279,7 @@ int stm32l4_gpio_initialize(void) /* Configure the pin that will be used as input */ - stm32l4_configgpio(g_gpioinputs[i]); + stm32_configgpio(g_gpioinputs[i]); pincount++; } @@ -297,8 +297,8 @@ int stm32l4_gpio_initialize(void) /* Configure the pin that will be used as output */ - stm32l4_gpiowrite(g_gpiooutputs[i], 0); - stm32l4_configgpio(g_gpiooutputs[i]); + stm32_gpiowrite(g_gpiooutputs[i], 0); + stm32_configgpio(g_gpiooutputs[i]); pincount++; } @@ -316,7 +316,7 @@ int stm32l4_gpio_initialize(void) /* Configure the pin that will be used as interrupt input */ - stm32l4_configgpio(g_gpiointinputs[i]); + stm32_configgpio(g_gpiointinputs[i]); pincount++; } diff --git a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_lsm303agr.c b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_lsm303agr.c index 43b8d711a5c3b..10b19e930042f 100644 --- a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_lsm303agr.c +++ b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_lsm303agr.c @@ -31,7 +31,7 @@ #include #include -#include "stm32l4.h" +#include "stm32.h" #include #include @@ -39,8 +39,8 @@ * Pre-processor Definitions ****************************************************************************/ -#ifndef CONFIG_STM32L4_I2C1 -# error "LSM303AGR driver requires CONFIG_STM32L4_I2C1 to be enabled" +#ifndef CONFIG_STM32_I2C1 +# error "LSM303AGR driver requires CONFIG_STM32_I2C1 to be enabled" #endif /**************************************************************************** @@ -48,21 +48,21 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_lsm303agr_initialize + * Name: stm32_lsm303agr_initialize * * Description: * Initialize I2C-based LSM303AGR. ****************************************************************************/ -int stm32l4_lsm303agr_initialize(char *devpath) +int stm32_lsm303agr_initialize(char *devpath) { struct i2c_master_s *i2c; int ret = OK; sninfo("INFO: Initializing LMS303AGR sensor over I2C\n"); -#if defined(CONFIG_STM32L4_I2C1) - i2c = stm32l4_i2cbus_initialize(1); +#if defined(CONFIG_STM32_I2C1) + i2c = stm32_i2cbus_initialize(1); if (i2c == NULL) { return -ENODEV; diff --git a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_lsm6dsl.c b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_lsm6dsl.c index df404b8147ed6..bda0f7bf9dcdb 100644 --- a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_lsm6dsl.c +++ b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_lsm6dsl.c @@ -31,7 +31,7 @@ #include #include -#include "stm32l4.h" +#include "stm32.h" #include #include @@ -39,8 +39,8 @@ * Pre-processor Definitions ****************************************************************************/ -#ifndef CONFIG_STM32L4_I2C1 -# error "LSM6DSL driver requires CONFIG_STM32L4_I2C1 to be enabled" +#ifndef CONFIG_STM32_I2C1 +# error "LSM6DSL driver requires CONFIG_STM32_I2C1 to be enabled" #endif /**************************************************************************** @@ -48,13 +48,13 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_lsm6dsl_initialize + * Name: stm32_lsm6dsl_initialize * * Description: * Initialize I2C-based LSM6DSL. ****************************************************************************/ -int stm32l4_lsm6dsl_initialize(char *devpath) +int stm32_lsm6dsl_initialize(char *devpath) { struct i2c_master_s *i2c; int ret = OK; @@ -63,10 +63,10 @@ int stm32l4_lsm6dsl_initialize(char *devpath) /* Configure the GPIO interrupt */ - stm32l4_configgpio(GPIO_HTS221_INT); /* IS THE SAME AS HTS221 FOR IKS01_A2 SHIELD */ + stm32_configgpio(GPIO_HTS221_INT); /* IS THE SAME AS HTS221 FOR IKS01_A2 SHIELD */ -#if defined(CONFIG_STM32L4_I2C1) - i2c = stm32l4_i2cbus_initialize(1); +#if defined(CONFIG_STM32_I2C1) + i2c = stm32_i2cbus_initialize(1); if (i2c == NULL) { return -ENODEV; diff --git a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_mpu9250.c b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_mpu9250.c index cd5252a20031a..3211666f237fd 100644 --- a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_mpu9250.c +++ b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_mpu9250.c @@ -33,7 +33,7 @@ #include #include -#include "stm32l4.h" +#include "stm32.h" #include "stm32l4_i2c.h" #include "stm32_mpu9250.h" @@ -94,7 +94,7 @@ int board_mpu9250_initialize(int devno, int busno) /* Initialize MPU9250 */ - i2c = stm32l4_i2cbus_initialize(busno); + i2c = stm32_i2cbus_initialize(busno); if (i2c) { /* Then try to register the IMU sensor in I2Cx */ diff --git a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_mpu9250.h b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_mpu9250.h index 34a3cb06fcee1..694c09478a02c 100644 --- a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_mpu9250.h +++ b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_mpu9250.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32L4_NUCLEO_L476RG_INCLUDE_NUCLEO_L476RG_MPU9250_H -#define __BOARDS_ARM_STM32L4_NUCLEO_L476RG_INCLUDE_NUCLEO_L476RG_MPU9250_H +#ifndef __BOARDS_ARM_STM32_NUCLEO_L476RG_INCLUDE_NUCLEO_L476RG_MPU9250_H +#define __BOARDS_ARM_STM32_NUCLEO_L476RG_INCLUDE_NUCLEO_L476RG_MPU9250_H /**************************************************************************** * Included Files @@ -88,4 +88,4 @@ int board_mpu9250_initialize(int devno, int busno); } #endif -#endif /* __BOARDS_ARM_STM32L4_NUCLEO_L476RG_INCLUDE_NUCLEO_L476RG_MPU9250_H */ +#endif /* __BOARDS_ARM_STM32_NUCLEO_L476RG_INCLUDE_NUCLEO_L476RG_MPU9250_H */ diff --git a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_pcd8544.c b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_pcd8544.c index eb9316cb51fef..ab30d3c77a87a 100644 --- a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_pcd8544.c +++ b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_pcd8544.c @@ -72,12 +72,12 @@ int board_lcd_initialize(void) { /* Configure the GPIO pins */ - stm32l4_configgpio(STM32_LCD_RST); - stm32l4_configgpio(STM32_LCD_CD); - stm32l4_gpiowrite(STM32_LCD_RST, 1); - stm32l4_gpiowrite(STM32_LCD_CD, 1); + stm32_configgpio(STM32_LCD_RST); + stm32_configgpio(STM32_LCD_CD); + stm32_gpiowrite(STM32_LCD_RST, 1); + stm32_gpiowrite(STM32_LCD_CD, 1); - g_spidev = stm32l4_spibus_initialize(LCD_SPI_PORTNO); + g_spidev = stm32_spibus_initialize(LCD_SPI_PORTNO); if (!g_spidev) { @@ -85,9 +85,9 @@ int board_lcd_initialize(void) return -ENODEV; } - stm32l4_gpiowrite(STM32_LCD_RST, 0); + stm32_gpiowrite(STM32_LCD_RST, 0); up_mdelay(10); - stm32l4_gpiowrite(STM32_LCD_RST, 1); + stm32_gpiowrite(STM32_LCD_RST, 1); return OK; } diff --git a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_pwm.c b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_pwm.c index 231a62a88ff71..8cb546fc69d0c 100644 --- a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_pwm.c +++ b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_pwm.c @@ -60,14 +60,14 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_pwm_setup + * Name: stm32_pwm_setup * * Description: * Initialize PWM and register the PWM device. * ****************************************************************************/ -int stm32l4_pwm_setup(void) +int stm32_pwm_setup(void) { static bool initialized = false; struct pwm_lowerhalf_s *pwm; @@ -77,7 +77,7 @@ int stm32l4_pwm_setup(void) if (!initialized) { - /* Call stm32l4_pwminitialize() to get an instance of the PWM + /* Call stm32_pwminitialize() to get an instance of the PWM * interface */ @@ -88,8 +88,8 @@ int stm32l4_pwm_setup(void) * (see board.h). Let's figure out which the user has configured. */ -#if defined(CONFIG_STM32L4_TIM1_PWM) - pwm = stm32l4_pwminitialize(1); +#if defined(CONFIG_STM32_TIM1_PWM) + pwm = stm32_pwminitialize(1); if (!pwm) { aerr("ERROR: Failed to get the STM32L4 PWM lower half\n"); @@ -106,8 +106,8 @@ int stm32l4_pwm_setup(void) } #endif -#if defined(CONFIG_STM32L4_TIM2_PWM) - pwm = stm32l4_pwminitialize(2); +#if defined(CONFIG_STM32_TIM2_PWM) + pwm = stm32_pwminitialize(2); if (!pwm) { aerr("ERROR: Failed to get the STM32L4 PWM lower half\n"); @@ -124,8 +124,8 @@ int stm32l4_pwm_setup(void) } #endif -#if defined(CONFIG_STM32L4_TIM3_PWM) - pwm = stm32l4_pwminitialize(3); +#if defined(CONFIG_STM32_TIM3_PWM) + pwm = stm32_pwminitialize(3); if (!pwm) { aerr("ERROR: Failed to get the STM32L4 PWM lower half\n"); @@ -142,8 +142,8 @@ int stm32l4_pwm_setup(void) } #endif -#if defined(CONFIG_STM32L4_TIM4_PWM) - pwm = stm32l4_pwminitialize(4); +#if defined(CONFIG_STM32_TIM4_PWM) + pwm = stm32_pwminitialize(4); if (!pwm) { aerr("ERROR: Failed to get the STM32L4 PWM lower half\n"); @@ -160,8 +160,8 @@ int stm32l4_pwm_setup(void) } #endif -#if defined(CONFIG_STM32L4_TIM5_PWM) - pwm = stm32l4_pwminitialize(5); +#if defined(CONFIG_STM32_TIM5_PWM) + pwm = stm32_pwminitialize(5); if (!pwm) { aerr("ERROR: Failed to get the STM32L4 PWM lower half\n"); @@ -178,8 +178,8 @@ int stm32l4_pwm_setup(void) } #endif -#if defined(CONFIG_STM32L4_TIM8_PWM) - pwm = stm32l4_pwminitialize(8); +#if defined(CONFIG_STM32_TIM8_PWM) + pwm = stm32_pwminitialize(8); if (!pwm) { aerr("ERROR: Failed to get the STM32L4 PWM lower half\n"); @@ -196,8 +196,8 @@ int stm32l4_pwm_setup(void) } #endif -#if defined(CONFIG_STM32L4_TIM15_PWM) - pwm = stm32l4_pwminitialize(15); +#if defined(CONFIG_STM32_TIM15_PWM) + pwm = stm32_pwminitialize(15); if (!pwm) { aerr("ERROR: Failed to get the STM32L4 PWM lower half\n"); @@ -214,8 +214,8 @@ int stm32l4_pwm_setup(void) } #endif -#if defined(CONFIG_STM32L4_TIM16_PWM) - pwm = stm32l4_pwminitialize(16); +#if defined(CONFIG_STM32_TIM16_PWM) + pwm = stm32_pwminitialize(16); if (!pwm) { aerr("ERROR: Failed to get the STM32L4 PWM lower half\n"); @@ -232,8 +232,8 @@ int stm32l4_pwm_setup(void) } #endif -#if defined(CONFIG_STM32L4_TIM17_PWM) - pwm = stm32l4_pwminitialize(17); +#if defined(CONFIG_STM32_TIM17_PWM) + pwm = stm32_pwminitialize(17); if (!pwm) { aerr("ERROR: Failed to get the STM32L4 PWM lower half\n"); @@ -250,8 +250,8 @@ int stm32l4_pwm_setup(void) } #endif -#if defined(CONFIG_STM32L4_LPTIM1_PWM) - pwm = stm32l4_lp_pwminitialize(1); +#if defined(CONFIG_STM32_LPTIM1_PWM) + pwm = stm32_lp_pwminitialize(1); if (!pwm) { aerr("ERROR: Failed to get the STM32L4 PWM lower half\n"); @@ -268,8 +268,8 @@ int stm32l4_pwm_setup(void) } #endif -#if defined(CONFIG_STM32L4_LPTIM2_PWM) - pwm = stm32l4_lp_pwminitialize(2); +#if defined(CONFIG_STM32_LPTIM2_PWM) + pwm = stm32_lp_pwminitialize(2); if (!pwm) { aerr("ERROR: Failed to get the STM32L4 PWM lower half\n"); diff --git a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_qencoder.c b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_qencoder.c index 9e366385cf07f..a87fc8c891656 100644 --- a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_qencoder.c +++ b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_qencoder.c @@ -50,17 +50,17 @@ * ****************************************************************************/ -int stm32l4_qencoder_initialize(const char *devpath, int timer) +int stm32_qencoder_initialize(const char *devpath, int timer) { int ret; /* Initialize a quadrature encoder interface. */ sninfo("Initializing the quadrature encoder using TIM%d\n", timer); - ret = stm32l4_qeinitialize(devpath, timer); + ret = stm32_qeinitialize(devpath, timer); if (ret < 0) { - snerr("ERROR: stm32l4_qeinitialize failed: %d\n", ret); + snerr("ERROR: stm32_qeinitialize failed: %d\n", ret); } return ret; diff --git a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_spi.c b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_spi.c index a787754741543..5903f519b5c51 100644 --- a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_spi.c +++ b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_spi.c @@ -35,12 +35,12 @@ #include #include "chip.h" -#include +#include #include "nucleo-l476rg.h" -#if defined(CONFIG_STM32L4_SPI1) || defined(CONFIG_STM32L4_SPI2) || \ - defined(CONFIG_STM32L4_SPI3) +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || \ + defined(CONFIG_STM32_SPI3) /**************************************************************************** * Public Data @@ -48,10 +48,10 @@ /* Global driver instances */ -#ifdef CONFIG_STM32L4_SPI1 +#ifdef CONFIG_STM32_SPI1 struct spi_dev_s *g_spi1; #endif -#ifdef CONFIG_STM32L4_SPI2 +#ifdef CONFIG_STM32_SPI2 struct spi_dev_s *g_spi2; #endif @@ -60,7 +60,7 @@ struct spi_dev_s *g_spi2; ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_spiinitialize + * Name: stm32_spiinitialize * * Description: * Called to configure SPI chip select GPIO pins for the Nucleo-L476RG @@ -68,57 +68,57 @@ struct spi_dev_s *g_spi2; * ****************************************************************************/ -void weak_function stm32l4_spiinitialize(void) +void weak_function stm32_spiinitialize(void) { -#ifdef CONFIG_STM32L4_SPI1 +#ifdef CONFIG_STM32_SPI1 /* Configure SPI-based devices */ - g_spi1 = stm32l4_spibus_initialize(1); + g_spi1 = stm32_spibus_initialize(1); if (!g_spi1) { spierr("ERROR: FAILED to initialize SPI port 1\n"); } #ifdef HAVE_MMCSD_SPI - stm32l4_configgpio(GPIO_SPI_CS_SD_CARD); + stm32_configgpio(GPIO_SPI_CS_SD_CARD); #endif #ifdef CONFIG_LCD_PCD8544 - stm32l4_configgpio(STM32_LCD_CS); /* PCD8544 chip select */ + stm32_configgpio(STM32_LCD_CS); /* PCD8544 chip select */ #endif #endif -#ifdef CONFIG_STM32L4_SPI2 +#ifdef CONFIG_STM32_SPI2 /* Configure SPI-based devices */ - g_spi2 = stm32l4_spibus_initialize(2); + g_spi2 = stm32_spibus_initialize(2); #ifdef CONFIG_WL_CC1101 /* Setup CS, IRQ(gdo2) line IOs */ - stm32l4_configgpio(GPIO_CC1101_PWR); - stm32l4_configgpio(GPIO_CC1101_CS); - stm32l4_configgpio(GPIO_CC1101_GDO2); + stm32_configgpio(GPIO_CC1101_PWR); + stm32_configgpio(GPIO_CC1101_CS); + stm32_configgpio(GPIO_CC1101_GDO2); #endif #endif } /**************************************************************************** - * Name: stm32l4_spi1/2/3select and stm32l4_spi1/2/3status + * Name: stm32_spi1/2/3select and stm32_spi1/2/3status * * Description: - * The external functions, stm32l4_spi1/2/3select and - * stm32l4_spi1/2/3status must be provided by board-specific logic. They + * The external functions, stm32_spi1/2/3select and + * stm32_spi1/2/3status must be provided by board-specific logic. They * are implementations of the select and status methods of the SPI * interface defined by struct spi_ops_s (see include/nuttx/spi/spi.h). * All other methods (including up_spiinitialize()) are provided by common * STM32 logic. To use this common SPI logic on your * board: * - * 1. Provide logic in stm32l4_board_initialize() to configure SPI chip + * 1. Provide logic in stm32_board_initialize() to configure SPI chip * select pins. - * 2. Provide stm32l4_spi1/2/3select() and stm32l4_spi1/2/3status() + * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() * functions in your board-specific logic. These functions will perform * chip selection and status operations using GPIOs in the way your * board is configured. @@ -131,8 +131,8 @@ void weak_function stm32l4_spiinitialize(void) * ****************************************************************************/ -#ifdef CONFIG_STM32L4_SPI1 -void stm32l4_spi1select(struct spi_dev_s *dev, +#ifdef CONFIG_STM32_SPI1 +void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, bool selected) { spiinfo("devid: %d CS: %s\n", @@ -141,19 +141,19 @@ void stm32l4_spi1select(struct spi_dev_s *dev, #ifdef HAVE_MMCSD_SPI if (devid == SPIDEV_MMCSD(0)) { - stm32l4_gpiowrite(GPIO_SPI_CS_SD_CARD, !selected); + stm32_gpiowrite(GPIO_SPI_CS_SD_CARD, !selected); } #endif #ifdef CONFIG_LCD_PCD8544 if (devid == SPIDEV_DISPLAY(0)) { - stm32l4_gpiowrite(STM32_LCD_CS, !selected); + stm32_gpiowrite(STM32_LCD_CS, !selected); } #endif } -uint8_t stm32l4_spi1status(struct spi_dev_s *dev, uint32_t devid) +uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) { uint8_t status = 0; @@ -168,8 +168,8 @@ uint8_t stm32l4_spi1status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32L4_SPI2 -void stm32l4_spi2select(struct spi_dev_s *dev, +#ifdef CONFIG_STM32_SPI2 +void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid, bool selected) { spiinfo("devid: %d CS: %s\n", @@ -178,33 +178,33 @@ void stm32l4_spi2select(struct spi_dev_s *dev, #ifdef CONFIG_WL_CC1101 if (devid == SPIDEV_WIRELESS(5)) { - stm32l4_gpiowrite(GPIO_CC1101_CS, !selected); + stm32_gpiowrite(GPIO_CC1101_CS, !selected); } #endif } -uint8_t stm32l4_spi2status(struct spi_dev_s *dev, uint32_t devid) +uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) { return 0; } #endif -#ifdef CONFIG_STM32L4_SPI3 -void stm32l4_spi3select(struct spi_dev_s *dev, +#ifdef CONFIG_STM32_SPI3 +void stm32_spi3select(struct spi_dev_s *dev, uint32_t devid, bool selected) { spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); } -uint8_t stm32l4_spi3status(struct spi_dev_s *dev, uint32_t devid) +uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid) { return 0; } #endif /**************************************************************************** - * Name: stm32l4_spi1cmddata + * Name: stm32_spi1cmddata * * Description: * Set or clear the SH1101A A0 or SD1306 D/C n bit to select data (true) @@ -227,8 +227,8 @@ uint8_t stm32l4_spi3status(struct spi_dev_s *dev, uint32_t devid) ****************************************************************************/ #ifdef CONFIG_SPI_CMDDATA -#ifdef CONFIG_STM32L4_SPI1 -int stm32l4_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) +#ifdef CONFIG_STM32_SPI1 +int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { #ifdef CONFIG_LCD_PCD8544 if (devid == SPIDEV_DISPLAY(0)) @@ -237,7 +237,7 @@ int stm32l4_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) * data bits are data or a command. */ - stm32l4_gpiowrite(STM32_LCD_CD, !cmd); + stm32_gpiowrite(STM32_LCD_CD, !cmd); return OK; } @@ -247,19 +247,19 @@ int stm32l4_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) } #endif -#ifdef CONFIG_STM32L4_SPI2 -int stm32l4_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) +#ifdef CONFIG_STM32_SPI2 +int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return OK; } #endif -#ifdef CONFIG_STM32L4_SPI3 -int stm32l4_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) +#ifdef CONFIG_STM32_SPI3 +int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return OK; } #endif #endif /* CONFIG_SPI_CMDDATA */ -#endif /* CONFIG_STM32L4_SPI1 || CONFIG_STM32L4_SPI2 || CONFIG_STM32L4_SPI3 */ +#endif /* CONFIG_STM32_SPI1 || CONFIG_STM32_SPI2 || CONFIG_STM32_SPI3 */ diff --git a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_spimmcsd.c b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_spimmcsd.c index d41d00e3f60be..fe006549d8153 100644 --- a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_spimmcsd.c +++ b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_spimmcsd.c @@ -33,14 +33,14 @@ #include #include -#include +#include #include "stm32l4_spi.h" /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ -#ifndef CONFIG_STM32L4_SPI1 +#ifndef CONFIG_STM32_SPI1 # error "SD driver requires CONFIG_STM32_SPI1 to be enabled" #endif @@ -68,14 +68,14 @@ static const int SD_SLOT_NO = 0; /* There is only one SD slot */ ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_spi1register + * Name: stm32_spi1register * * Description: * Registers media change callback * ****************************************************************************/ -int stm32l4_spi1register(struct spi_dev_s *dev, spi_mediachange_t callback, +int stm32_spi1register(struct spi_dev_s *dev, spi_mediachange_t callback, void *arg) { spiinfo("INFO: Registering spi1 device\n"); @@ -83,21 +83,21 @@ int stm32l4_spi1register(struct spi_dev_s *dev, spi_mediachange_t callback, } /**************************************************************************** - * Name: stm32l4_mmcsd_initialize + * Name: stm32_mmcsd_initialize * * Description: * Initialize SPI-based SD card and card detect thread. * ****************************************************************************/ -int stm32l4_mmcsd_initialize(int minor) +int stm32_mmcsd_initialize(int minor) { struct spi_dev_s *spi; int rv; mcinfo("INFO: Initializing mmcsd card\n"); - spi = stm32l4_spibus_initialize(SD_SPI_PORT); + spi = stm32_spibus_initialize(SD_SPI_PORT); if (spi == NULL) { mcerr("ERROR: Failed to initialize SPI port %d\n", SD_SPI_PORT); diff --git a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_timer.c b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_timer.c index a0c347aea59c5..7ae7885ca8bfe 100644 --- a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_timer.c +++ b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_timer.c @@ -61,7 +61,7 @@ int board_timer_driver_initialize(const char *devpath, int timer) { - return stm32l4_timer_initialize(devpath, timer); + return stm32_timer_initialize(devpath, timer); } #endif diff --git a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_uid.c b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_uid.c index 278b51f7c2ae3..ee1dedd051040 100644 --- a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_uid.c +++ b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_uid.c @@ -38,7 +38,7 @@ #include -#include "stm32l4_uid.h" +#include "stm32_uid.h" #include "nucleo-l476rg.h" /**************************************************************************** @@ -56,6 +56,6 @@ int board_uniqueid(uint8_t *uniqueid) return -EINVAL; } - stm32l4_get_uniqueid(uniqueid); + stm32_get_uniqueid(uniqueid); return OK; } diff --git a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_userleds.c b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_userleds.c index 92c96b1dc0094..34384cb9dc323 100644 --- a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_userleds.c +++ b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_userleds.c @@ -36,7 +36,7 @@ #include "chip.h" #include "arm_internal.h" -#include "stm32l4.h" +#include "stm32.h" #include "nucleo-l476rg.h" #ifndef CONFIG_ARCH_LEDS @@ -154,7 +154,7 @@ uint32_t board_userled_initialize(void) { /* Configure LD2 GPIO for output */ - stm32l4_configgpio(GPIO_LD2); + stm32_configgpio(GPIO_LD2); return BOARD_NLEDS; } @@ -166,7 +166,7 @@ void board_userled(int led, bool ledon) { if (led == BOARD_LD2) { - stm32l4_gpiowrite(GPIO_LD2, ledon); + stm32_gpiowrite(GPIO_LD2, ledon); } } @@ -176,15 +176,15 @@ void board_userled(int led, bool ledon) void board_userled_all(uint32_t ledset) { - stm32l4_gpiowrite(GPIO_LD2, (ledset & BOARD_LD2_BIT) != 0); + stm32_gpiowrite(GPIO_LD2, (ledset & BOARD_LD2_BIT) != 0); } /**************************************************************************** - * Name: stm32l4_led_pminitialize + * Name: stm32_led_pminitialize ****************************************************************************/ #ifdef CONFIG_PM -void stm32l4_led_pminitialize(void) +void stm32_led_pminitialize(void) { /* Register to receive power management callbacks */ diff --git a/boards/arm/stm32l4/nucleo-l496zg/configs/nsh/defconfig b/boards/arm/stm32l4/nucleo-l496zg/configs/nsh/defconfig index 9a6ea2b69d599..71cee2c8a19c6 100644 --- a/boards/arm/stm32l4/nucleo-l496zg/configs/nsh/defconfig +++ b/boards/arm/stm32l4/nucleo-l496zg/configs/nsh/defconfig @@ -14,6 +14,7 @@ CONFIG_ARCH_BOARD="nucleo-l496zg" CONFIG_ARCH_BOARD_NUCLEO_L496ZG=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32l4" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32L496ZG=y CONFIG_ARCH_CHIP_STM32L4=y CONFIG_ARCH_INTERRUPTSTACK=2048 @@ -57,35 +58,35 @@ CONFIG_RTC_NALARMS=2 CONFIG_SCHED_WAITPID=y CONFIG_SERIAL_TERMIOS=y CONFIG_STACK_COLORATION=y -CONFIG_STM32L4_ADC1=y -CONFIG_STM32L4_ADC1_DMA=y -CONFIG_STM32L4_ADC1_EXTTRIG=1 -CONFIG_STM32L4_ADC1_SAMPLE_FREQUENCY=1000 -CONFIG_STM32L4_ADC2=y -CONFIG_STM32L4_ADC2_DMA=y -CONFIG_STM32L4_ADC3=y -CONFIG_STM32L4_ADC3_DMA=y -CONFIG_STM32L4_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32L4_DMA1=y -CONFIG_STM32L4_DMA2=y -CONFIG_STM32L4_FSMC=y -CONFIG_STM32L4_I2C1=y -CONFIG_STM32L4_I2C2=y -CONFIG_STM32L4_I2C3=y -CONFIG_STM32L4_I2C4=y -CONFIG_STM32L4_LPUART1=y -CONFIG_STM32L4_PWR=y -CONFIG_STM32L4_RNG=y -CONFIG_STM32L4_RTC=y -CONFIG_STM32L4_SAI1PLL=y -CONFIG_STM32L4_SPI1=y -CONFIG_STM32L4_SPI2=y -CONFIG_STM32L4_SPI3=y -CONFIG_STM32L4_SRAM2_HEAP=y -CONFIG_STM32L4_TIM1=y -CONFIG_STM32L4_TIM1_ADC=y -CONFIG_STM32L4_USART2=y -CONFIG_STM32L4_USART3=y +CONFIG_STM32_ADC1=y +CONFIG_STM32_ADC1_DMA=y +CONFIG_STM32_ADC1_EXTTRIG=1 +CONFIG_STM32_ADC1_SAMPLE_FREQUENCY=1000 +CONFIG_STM32_ADC2=y +CONFIG_STM32_ADC2_DMA=y +CONFIG_STM32_ADC3=y +CONFIG_STM32_ADC3_DMA=y +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_DMA1=y +CONFIG_STM32_DMA2=y +CONFIG_STM32_FSMC=y +CONFIG_STM32_I2C1=y +CONFIG_STM32_I2C2=y +CONFIG_STM32_I2C3=y +CONFIG_STM32_I2C4=y +CONFIG_STM32_LPUART1=y +CONFIG_STM32_PWR=y +CONFIG_STM32_RNG=y +CONFIG_STM32_RTC=y +CONFIG_STM32_SAI1PLL=y +CONFIG_STM32_SPI1=y +CONFIG_STM32_SPI2=y +CONFIG_STM32_SPI3=y +CONFIG_STM32_SRAM2_HEAP=y +CONFIG_STM32_TIM1=y +CONFIG_STM32_TIM1_ADC=y +CONFIG_STM32_USART2=y +CONFIG_STM32_USART3=y CONFIG_SYSTEM_I2CTOOL=y CONFIG_SYSTEM_NSH=y CONFIG_SYSTEM_STACKMONITOR=y diff --git a/boards/arm/stm32l4/nucleo-l496zg/include/board.h b/boards/arm/stm32l4/nucleo-l496zg/include/board.h index 7aa8a010e5acd..e753e7f0952cc 100644 --- a/boards/arm/stm32l4/nucleo-l496zg/include/board.h +++ b/boards/arm/stm32l4/nucleo-l496zg/include/board.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32L4_NUCLEO_L496ZG_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32L4_NUCLEO_L496ZG_INCLUDE_BOARD_H +#ifndef __BOARDS_ARM_STM32_NUCLEO_L496ZG_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32_NUCLEO_L496ZG_INCLUDE_BOARD_H /**************************************************************************** * Included Files @@ -55,20 +55,20 @@ * LSE: 32.768 kHz */ -#define STM32L4_HSI_FREQUENCY 16000000ul -#define STM32L4_LSI_FREQUENCY 32000 -#define STM32L4_HSE_FREQUENCY 8000000ul /* 8 MHz from MCO output */ -#define STM32L4_LSE_FREQUENCY 32768 +#define STM32_HSI_FREQUENCY 16000000ul +#define STM32_LSI_FREQUENCY 32000 +#define STM32_HSE_FREQUENCY 8000000ul /* 8 MHz from MCO output */ +#define STM32_LSE_FREQUENCY 32768 #define MSI_CLOCK_CONFIG #if defined(HSI_CLOCK_CONFIG) -#define STM32L4_BOARD_USEHSI +#define STM32_BOARD_USEHSI /* Prescaler common to all PLL inputs; will be 1 */ -#define STM32L4_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) /* 'main' PLL config; we use this to generate our system clock via the R * output. We set it up as 16 MHz / 1 * 10 / 2 = 80 MHz @@ -79,13 +79,13 @@ * applications may want things done this way. */ -#define STM32L4_PLLCFG_PLLN RCC_PLLCFG_PLLN(10) -#define STM32L4_PLLCFG_PLLP 0 -#undef STM32L4_PLLCFG_PLLP_ENABLED -#define STM32L4_PLLCFG_PLLQ RCC_PLLCFG_PLLQ_2 -#define STM32L4_PLLCFG_PLLQ_ENABLED -#define STM32L4_PLLCFG_PLLR RCC_PLLCFG_PLLR_2 -#define STM32L4_PLLCFG_PLLR_ENABLED +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(10) +#define STM32_PLLCFG_PLLP 0 +#undef STM32_PLLCFG_PLLP_ENABLED +#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ_2 +#define STM32_PLLCFG_PLLQ_ENABLED +#define STM32_PLLCFG_PLLR RCC_PLLCFG_PLLR_2 +#define STM32_PLLCFG_PLLR_ENABLED /* 'SAIPLL1' is used to generate the 48 MHz clock, since we can't * do that with the main PLL's N value. We set N = 13, and enable @@ -99,71 +99,71 @@ * that is selected via a #define here, like all these other params. */ -#define STM32L4_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(12) -#define STM32L4_PLLSAI1CFG_PLLP 0 -#undef STM32L4_PLLSAI1CFG_PLLP_ENABLED -#define STM32L4_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_4 -#define STM32L4_PLLSAI1CFG_PLLQ_ENABLED -#define STM32L4_PLLSAI1CFG_PLLR 0 -#undef STM32L4_PLLSAI1CFG_PLLR_ENABLED +#define STM32_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(12) +#define STM32_PLLSAI1CFG_PLLP 0 +#undef STM32_PLLSAI1CFG_PLLP_ENABLED +#define STM32_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_4 +#define STM32_PLLSAI1CFG_PLLQ_ENABLED +#define STM32_PLLSAI1CFG_PLLR 0 +#undef STM32_PLLSAI1CFG_PLLR_ENABLED /* 'SAIPLL2' is not used in this application */ -#define STM32L4_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) -#define STM32L4_PLLSAI2CFG_PLLP 0 -#undef STM32L4_PLLSAI2CFG_PLLP_ENABLED -#define STM32L4_PLLSAI2CFG_PLLR 0 -#undef STM32L4_PLLSAI2CFG_PLLR_ENABLED +#define STM32_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) +#define STM32_PLLSAI2CFG_PLLP 0 +#undef STM32_PLLSAI2CFG_PLLP_ENABLED +#define STM32_PLLSAI2CFG_PLLR 0 +#undef STM32_PLLSAI2CFG_PLLR_ENABLED -#define STM32L4_SYSCLK_FREQUENCY 80000000ul +#define STM32_SYSCLK_FREQUENCY 80000000ul /* CLK48 will come from PLLSAI1 (implicitly Q) */ -#if defined(CONFIG_STM32L4_OTGFS) || defined(STM32L4_SDMMC) || defined(CONFIG_STM32L4_RNG) -# define STM32L4_USE_CLK48 1 -# define STM32L4_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 -# define STM32L4_HSI48_SYNCSRC SYNCSRC_NONE +#if defined(CONFIG_STM32_OTGFS) || defined(STM32_SDMMC) || defined(CONFIG_STM32_RNG) +# define STM32_USE_CLK48 1 +# define STM32_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 +# define STM32_HSI48_SYNCSRC SYNCSRC_NONE #endif /* Enable the LSE oscillator, used automatically trim the MSI, and for RTC */ -#define STM32L4_USE_LSE 1 +#define STM32_USE_LSE 1 /* AHB clock (HCLK) is SYSCLK (80MHz) */ -#define STM32L4_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ -#define STM32L4_HCLK_FREQUENCY STM32L4_SYSCLK_FREQUENCY +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY /* APB1 clock (PCLK1) is HCLK/1 (80MHz) */ -#define STM32L4_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ -#define STM32L4_PCLK1_FREQUENCY (STM32L4_HCLK_FREQUENCY/1) +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/1) /* Timers driven from APB1 will be twice PCLK1 */ /* REVISIT : this can be configured */ -#define STM32L4_APB1_TIM2_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM3_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM4_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM5_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM6_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM7_CLKIN (2*STM32L4_PCLK1_FREQUENCY) +#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) /* APB2 clock (PCLK2) is HCLK (80MHz) */ -#define STM32L4_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ -#define STM32L4_PCLK2_FREQUENCY (STM32L4_HCLK_FREQUENCY/1) +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ +#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/1) /* Timers driven from APB2 will be twice PCLK2 */ /* REVISIT : this can be configured */ -#define STM32L4_APB2_TIM1_CLKIN (2*STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM8_CLKIN (2*STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM15_CLKIN (2*STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM16_CLKIN (2*STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM17_CLKIN (2*STM32L4_PCLK2_FREQUENCY) +#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM15_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM16_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM17_CLKIN (2*STM32_PCLK2_FREQUENCY) /* Timer Frequencies, if APBx is set to 1, frequency is same to APBx * otherwise frequency is 2xAPBx. @@ -174,11 +174,11 @@ #elif defined(HSE_CLOCK_CONFIG) -#define STM32L4_BOARD_USEHSE +#define STM32_BOARD_USEHSE /* Prescaler common to all PLL inputs; will be 1 */ -#define STM32L4_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) /* 'main' PLL config; we use this to generate our system clock via the R * output. We set it up as 8 MHz / 1 * 20 / 2 = 80 MHz @@ -189,13 +189,13 @@ * applications may want things done this way. */ -#define STM32L4_PLLCFG_PLLN RCC_PLLCFG_PLLN(20) -#define STM32L4_PLLCFG_PLLP 0 -#undef STM32L4_PLLCFG_PLLP_ENABLED -#define STM32L4_PLLCFG_PLLQ RCC_PLLCFG_PLLQ_2 -#define STM32L4_PLLCFG_PLLQ_ENABLED -#define STM32L4_PLLCFG_PLLR RCC_PLLCFG_PLLR_2 -#define STM32L4_PLLCFG_PLLR_ENABLED +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(20) +#define STM32_PLLCFG_PLLP 0 +#undef STM32_PLLCFG_PLLP_ENABLED +#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ_2 +#define STM32_PLLCFG_PLLQ_ENABLED +#define STM32_PLLCFG_PLLR RCC_PLLCFG_PLLR_2 +#define STM32_PLLCFG_PLLR_ENABLED /* 'SAIPLL1' is used to generate the 48 MHz clock, since we can't * do that with the main PLL's N value. We set N = 12, and enable @@ -209,71 +209,71 @@ * that is selected via a #define here, like all these other params. */ -#define STM32L4_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(12) -#define STM32L4_PLLSAI1CFG_PLLP 0 -#undef STM32L4_PLLSAI1CFG_PLLP_ENABLED -#define STM32L4_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_2 -#define STM32L4_PLLSAI1CFG_PLLQ_ENABLED -#define STM32L4_PLLSAI1CFG_PLLR 0 -#undef STM32L4_PLLSAI1CFG_PLLR_ENABLED +#define STM32_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(12) +#define STM32_PLLSAI1CFG_PLLP 0 +#undef STM32_PLLSAI1CFG_PLLP_ENABLED +#define STM32_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_2 +#define STM32_PLLSAI1CFG_PLLQ_ENABLED +#define STM32_PLLSAI1CFG_PLLR 0 +#undef STM32_PLLSAI1CFG_PLLR_ENABLED /* 'SAIPLL2' is not used in this application */ -#define STM32L4_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) -#define STM32L4_PLLSAI2CFG_PLLP 0 -#undef STM32L4_PLLSAI2CFG_PLLP_ENABLED -#define STM32L4_PLLSAI2CFG_PLLR 0 -#undef STM32L4_PLLSAI2CFG_PLLR_ENABLED +#define STM32_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) +#define STM32_PLLSAI2CFG_PLLP 0 +#undef STM32_PLLSAI2CFG_PLLP_ENABLED +#define STM32_PLLSAI2CFG_PLLR 0 +#undef STM32_PLLSAI2CFG_PLLR_ENABLED -#define STM32L4_SYSCLK_FREQUENCY 80000000ul +#define STM32_SYSCLK_FREQUENCY 80000000ul /* CLK48 will come from PLLSAI1 (implicitly Q) */ -#if defined(CONFIG_STM32L4_OTGFS) || defined(STM32L4_SDMMC) || defined(CONFIG_STM32L4_RNG) -# define STM32L4_USE_CLK48 1 -# define STM32L4_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 -# define STM32L4_HSI48_SYNCSRC SYNCSRC_NONE +#if defined(CONFIG_STM32_OTGFS) || defined(STM32_SDMMC) || defined(CONFIG_STM32_RNG) +# define STM32_USE_CLK48 1 +# define STM32_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 +# define STM32_HSI48_SYNCSRC SYNCSRC_NONE #endif /* Enable the LSE oscillator, used automatically trim the MSI, and for RTC */ -#define STM32L4_USE_LSE 1 +#define STM32_USE_LSE 1 /* AHB clock (HCLK) is SYSCLK (80MHz) */ -#define STM32L4_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ -#define STM32L4_HCLK_FREQUENCY STM32L4_SYSCLK_FREQUENCY +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY /* APB1 clock (PCLK1) is HCLK/1 (80MHz) */ -#define STM32L4_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ -#define STM32L4_PCLK1_FREQUENCY (STM32L4_HCLK_FREQUENCY/1) +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/1) /* Timers driven from APB1 will be twice PCLK1 */ /* REVISIT : this can be configured */ -#define STM32L4_APB1_TIM2_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM3_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM4_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM5_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM6_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM7_CLKIN (2*STM32L4_PCLK1_FREQUENCY) +#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) /* APB2 clock (PCLK2) is HCLK (80MHz) */ -#define STM32L4_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ -#define STM32L4_PCLK2_FREQUENCY (STM32L4_HCLK_FREQUENCY/1) +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ +#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/1) /* Timers driven from APB2 will be twice PCLK2 */ /* REVISIT : this can be configured */ -#define STM32L4_APB2_TIM1_CLKIN (2*STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM8_CLKIN (2*STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM15_CLKIN (2*STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM16_CLKIN (2*STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM17_CLKIN (2*STM32L4_PCLK2_FREQUENCY) +#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM15_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM16_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM17_CLKIN (2*STM32_PCLK2_FREQUENCY) /* Timer Frequencies, if APBx is set to 1, frequency is same to APBx * otherwise frequency is 2xAPBx. @@ -284,12 +284,12 @@ #elif defined(MSI_CLOCK_CONFIG) -#define STM32L4_BOARD_USEMSI -#define STM32L4_BOARD_MSIRANGE RCC_CR_MSIRANGE_4M +#define STM32_BOARD_USEMSI +#define STM32_BOARD_MSIRANGE RCC_CR_MSIRANGE_4M /* Prescaler common to all PLL inputs; will be 1 */ -#define STM32L4_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) /* 'main' PLL config; we use this to generate our system clock via the R * output. We set it up as 4 MHz / 1 * 40 / 2 = 80 MHz @@ -300,13 +300,13 @@ * applications may want things done this way. */ -#define STM32L4_PLLCFG_PLLN RCC_PLLCFG_PLLN(40) -#define STM32L4_PLLCFG_PLLP 0 -#undef STM32L4_PLLCFG_PLLP_ENABLED -#define STM32L4_PLLCFG_PLLQ RCC_PLLCFG_PLLQ_2 -#define STM32L4_PLLCFG_PLLQ_ENABLED -#define STM32L4_PLLCFG_PLLR RCC_PLLCFG_PLLR_2 -#define STM32L4_PLLCFG_PLLR_ENABLED +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(40) +#define STM32_PLLCFG_PLLP 0 +#undef STM32_PLLCFG_PLLP_ENABLED +#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ_2 +#define STM32_PLLCFG_PLLQ_ENABLED +#define STM32_PLLCFG_PLLR RCC_PLLCFG_PLLR_2 +#define STM32_PLLCFG_PLLR_ENABLED /* 'SAIPLL1' is used to generate the 48 MHz clock, since we can't * do that with the main PLL's N value. We set N = 12, and enable @@ -320,71 +320,71 @@ * that is selected via a #define here, like all these other params. */ -#define STM32L4_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(24) -#define STM32L4_PLLSAI1CFG_PLLP 0 -#undef STM32L4_PLLSAI1CFG_PLLP_ENABLED -#define STM32L4_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_2 -#define STM32L4_PLLSAI1CFG_PLLQ_ENABLED -#define STM32L4_PLLSAI1CFG_PLLR 0 -#undef STM32L4_PLLSAI1CFG_PLLR_ENABLED +#define STM32_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(24) +#define STM32_PLLSAI1CFG_PLLP 0 +#undef STM32_PLLSAI1CFG_PLLP_ENABLED +#define STM32_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_2 +#define STM32_PLLSAI1CFG_PLLQ_ENABLED +#define STM32_PLLSAI1CFG_PLLR 0 +#undef STM32_PLLSAI1CFG_PLLR_ENABLED /* 'SAIPLL2' is not used in this application */ -#define STM32L4_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) -#define STM32L4_PLLSAI2CFG_PLLP 0 -#undef STM32L4_PLLSAI2CFG_PLLP_ENABLED -#define STM32L4_PLLSAI2CFG_PLLR 0 -#undef STM32L4_PLLSAI2CFG_PLLR_ENABLED +#define STM32_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) +#define STM32_PLLSAI2CFG_PLLP 0 +#undef STM32_PLLSAI2CFG_PLLP_ENABLED +#define STM32_PLLSAI2CFG_PLLR 0 +#undef STM32_PLLSAI2CFG_PLLR_ENABLED -#define STM32L4_SYSCLK_FREQUENCY 80000000ul +#define STM32_SYSCLK_FREQUENCY 80000000ul /* CLK48 will come from PLLSAI1 (implicitly Q) */ -#if defined(CONFIG_STM32L4_OTGFS) || defined(STM32L4_SDMMC) || defined(CONFIG_STM32L4_RNG) -# define STM32L4_USE_CLK48 1 -# define STM32L4_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 -# define STM32L4_HSI48_SYNCSRC SYNCSRC_NONE +#if defined(CONFIG_STM32_OTGFS) || defined(STM32_SDMMC) || defined(CONFIG_STM32_RNG) +# define STM32_USE_CLK48 1 +# define STM32_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 +# define STM32_HSI48_SYNCSRC SYNCSRC_NONE #endif /* Enable the LSE oscillator, used automatically trim the MSI, and for RTC */ -#define STM32L4_USE_LSE 1 +#define STM32_USE_LSE 1 /* AHB clock (HCLK) is SYSCLK (80MHz) */ -#define STM32L4_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ -#define STM32L4_HCLK_FREQUENCY STM32L4_SYSCLK_FREQUENCY +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY /* APB1 clock (PCLK1) is HCLK/1 (80MHz) */ -#define STM32L4_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ -#define STM32L4_PCLK1_FREQUENCY (STM32L4_HCLK_FREQUENCY/1) +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/1) /* Timers driven from APB1 will be twice PCLK1 */ /* REVISIT : this can be configured */ -#define STM32L4_APB1_TIM2_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM3_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM4_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM5_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM6_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM7_CLKIN (2*STM32L4_PCLK1_FREQUENCY) +#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) /* APB2 clock (PCLK2) is HCLK (80MHz) */ -#define STM32L4_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ -#define STM32L4_PCLK2_FREQUENCY (STM32L4_HCLK_FREQUENCY/1) +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ +#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/1) /* Timers driven from APB2 will be twice PCLK2 */ /* REVISIT : this can be configured */ -#define STM32L4_APB2_TIM1_CLKIN (2*STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM8_CLKIN (2*STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM15_CLKIN (2*STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM16_CLKIN (2*STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM17_CLKIN (2*STM32L4_PCLK2_FREQUENCY) +#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM15_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM16_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM17_CLKIN (2*STM32_PCLK2_FREQUENCY) /* Timer Frequencies, if APBx is set to 1, frequency is same to APBx * otherwise frequency is 2xAPBx. @@ -400,19 +400,19 @@ * Note: TIM1,8,15,16,17 are on APB2, others on APB1 */ -#define BOARD_TIM1_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM2_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2) -#define BOARD_TIM3_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2) -#define BOARD_TIM4_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2) -#define BOARD_TIM5_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2) -#define BOARD_TIM6_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2) -#define BOARD_TIM7_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2) -#define BOARD_TIM8_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM15_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM16_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM17_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_LPTIM1_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2) -#define BOARD_LPTIM2_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2) +#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM2_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM3_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM4_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM5_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM6_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM7_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM15_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM16_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM17_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_LPTIM1_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_LPTIM2_FREQUENCY (STM32_HCLK_FREQUENCY / 2) /* SDMMC dividers. * Note that slower clocking is required when DMA is disabled @@ -655,7 +655,7 @@ extern "C" ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_board_initialize + * Name: stm32_board_initialize * * Description: * All STM32 architectures must provide the following entry point. This @@ -665,7 +665,7 @@ extern "C" * ****************************************************************************/ -void stm32l4_board_initialize(void); +void stm32_board_initialize(void); #undef EXTERN #if defined(__cplusplus) @@ -673,4 +673,4 @@ void stm32l4_board_initialize(void); #endif #endif /* __ASSEMBLY__ */ -#endif /* __BOARDS_ARM_STM32L4_NUCLEO_L496ZG_INCLUDE_BOARD_H */ +#endif /* __BOARDS_ARM_STM32_NUCLEO_L496ZG_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32l4/nucleo-l496zg/src/CMakeLists.txt b/boards/arm/stm32l4/nucleo-l496zg/src/CMakeLists.txt index 3e922a252e9ef..fb76edca235e3 100644 --- a/boards/arm/stm32l4/nucleo-l496zg/src/CMakeLists.txt +++ b/boards/arm/stm32l4/nucleo-l496zg/src/CMakeLists.txt @@ -42,7 +42,7 @@ endif() if(CONFIG_ADC) list(APPEND SRCS stm32_adc.c) - if(CONFIG_STM32L4_DFSDM) + if(CONFIG_STM32_DFSDM) list(APPEND SRCS stm32_dfsdm.c) endif() endif() @@ -55,7 +55,7 @@ if(CONFIG_MMCSD) list(APPEND SRCS stm32_sdio.c) endif() -if(CONFIG_STM32L4_OTGFS) +if(CONFIG_STM32_OTGFS) list(APPEND SRCS stm32_usb.c) endif() diff --git a/boards/arm/stm32l4/nucleo-l496zg/src/Make.defs b/boards/arm/stm32l4/nucleo-l496zg/src/Make.defs new file mode 100644 index 0000000000000..af3cc615e192c --- /dev/null +++ b/boards/arm/stm32l4/nucleo-l496zg/src/Make.defs @@ -0,0 +1,76 @@ +############################################################################ +# boards/arm/stm32l4/nucleo-l496zg/src/Makefile +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +CSRCS = stm32_boot.c stm32_bringup.c + +ifeq ($(CONFIG_ARCH_LEDS),y) +CSRCS += stm32_autoleds.c +else +CSRCS += stm32_userleds.c +endif + +ifeq ($(CONFIG_ARCH_BUTTONS),y) +CSRCS += stm32_buttons.c +endif + +ifeq ($(CONFIG_BOARDCTL_IOCTL),y) +CSRCS += stm32_ioctl.c +endif + +ifeq ($(CONFIG_SPI),y) +CSRCS += stm32_spi.c +endif + +ifeq ($(CONFIG_ADC),y) +CSRCS += stm32_adc.c + ifeq ($(CONFIG_STM32_DFSDM),y) + CSRCS += stm32_dfsdm.c + endif +endif + +ifeq ($(CONFIG_DAC),y) +CSRCS += stm32_dac.c +endif + +ifeq ($(CONFIG_MMCSD),y) +CSRCS += stm32_sdio.c +endif + +ifeq ($(CONFIG_STM32_OTGFS),y) +CSRCS += stm32_usb.c +endif + +ifeq ($(CONFIG_BOARDCTL_UNIQUEID),y) +CSRCS += stm32_uid.c +endif + +ifneq ($(CONFIG_STM32_ETHMAC),y) +ifeq ($(CONFIG_NETDEVICES),y) +CSRCS += stm32_netinit.c +endif +endif + +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32l4/nucleo-l496zg/src/Makefile b/boards/arm/stm32l4/nucleo-l496zg/src/Makefile deleted file mode 100644 index 5170327a0612b..0000000000000 --- a/boards/arm/stm32l4/nucleo-l496zg/src/Makefile +++ /dev/null @@ -1,74 +0,0 @@ -############################################################################ -# boards/arm/stm32l4/nucleo-l496zg/src/Makefile -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/Make.defs - -CSRCS = stm32_boot.c stm32_bringup.c - -ifeq ($(CONFIG_ARCH_LEDS),y) -CSRCS += stm32_autoleds.c -else -CSRCS += stm32_userleds.c -endif - -ifeq ($(CONFIG_ARCH_BUTTONS),y) -CSRCS += stm32_buttons.c -endif - -ifeq ($(CONFIG_BOARDCTL_IOCTL),y) -CSRCS += stm32_ioctl.c -endif - -ifeq ($(CONFIG_SPI),y) -CSRCS += stm32_spi.c -endif - -ifeq ($(CONFIG_ADC),y) -CSRCS += stm32_adc.c - ifeq ($(CONFIG_STM32L4_DFSDM),y) - CSRCS += stm32_dfsdm.c - endif -endif - -ifeq ($(CONFIG_DAC),y) -CSRCS += stm32_dac.c -endif - -ifeq ($(CONFIG_MMCSD),y) -CSRCS += stm32_sdio.c -endif - -ifeq ($(CONFIG_STM32L4_OTGFS),y) -CSRCS += stm32_usb.c -endif - -ifeq ($(CONFIG_BOARDCTL_UNIQUEID),y) -CSRCS += stm32_uid.c -endif - -ifneq ($(CONFIG_STM32_ETHMAC),y) -ifeq ($(CONFIG_NETDEVICES),y) -CSRCS += stm32_netinit.c -endif -endif - -include $(TOPDIR)/boards/Board.mk diff --git a/boards/arm/stm32l4/nucleo-l496zg/src/nucleo-144.h b/boards/arm/stm32l4/nucleo-l496zg/src/nucleo-144.h index e4e2a78aa0e85..f51b90eb9f764 100644 --- a/boards/arm/stm32l4/nucleo-l496zg/src/nucleo-144.h +++ b/boards/arm/stm32l4/nucleo-l496zg/src/nucleo-144.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32L4_NUCLEO_L496ZG_SRC_NUCLEO_144_H -#define __BOARDS_ARM_STM32L4_NUCLEO_L496ZG_SRC_NUCLEO_144_H +#ifndef __BOARDS_ARM_STM32_NUCLEO_L496ZG_SRC_NUCLEO_144_H +#define __BOARDS_ARM_STM32_NUCLEO_L496ZG_SRC_NUCLEO_144_H /**************************************************************************** * Included Files @@ -103,7 +103,7 @@ #define GPIO_SPI3_CS2 (GPIO_SPI_CS | GPIO_PORTG | GPIO_PIN6) #define GPIO_SPI3_CS3 (GPIO_SPI_CS | GPIO_PORTG | GPIO_PIN7) -#if defined(CONFIG_STM32L4_SDMMC1) || defined(CONFIG_STM32L4_SDMMC2) +#if defined(CONFIG_STM32_SDMMC1) || defined(CONFIG_STM32_SDMMC2) # define HAVE_SDIO #endif @@ -114,7 +114,7 @@ #define SDIO_SLOTNO 0 /* Only one slot */ #ifdef HAVE_SDIO -# if defined(CONFIG_STM32L4_SDMMC1) +# if defined(CONFIG_STM32_SDMMC1) # define GPIO_SDMMC1_NCD (GPIO_INPUT|GPIO_FLOAT|GPIO_EXTI | GPIO_PORTC | GPIO_PIN6) # endif @@ -240,7 +240,7 @@ int stm32_sdio_initialize(void); * ****************************************************************************/ -#ifdef CONFIG_STM32L4_OTGFS +#ifdef CONFIG_STM32_OTGFS void stm32_usbinitialize(void); #endif @@ -276,9 +276,9 @@ int stm32_dac_setup(void); * ****************************************************************************/ -#if defined(CONFIG_ADC) && defined(CONFIG_STM32L4_DFSDM) +#if defined(CONFIG_ADC) && defined(CONFIG_STM32_DFSDM) int stm32_dfsdm_setup(void); #endif #endif /* __ASSEMBLY__ */ -#endif /* __BOARDS_ARM_STM32L4_NUCLEO_L496ZG_SRC_NUCLEO_144_H */ +#endif /* __BOARDS_ARM_STM32_NUCLEO_L496ZG_SRC_NUCLEO_144_H */ diff --git a/boards/arm/stm32l4/nucleo-l496zg/src/stm32_adc.c b/boards/arm/stm32l4/nucleo-l496zg/src/stm32_adc.c index 83b338839af64..e0ba48ff0a776 100644 --- a/boards/arm/stm32l4/nucleo-l496zg/src/stm32_adc.c +++ b/boards/arm/stm32l4/nucleo-l496zg/src/stm32_adc.c @@ -48,19 +48,19 @@ /* Up to 3 ADC interfaces are supported */ -#if STM32L4_NADC < 3 -# undef CONFIG_STM32L4_ADC3 +#if STM32_NADC < 3 +# undef CONFIG_STM32_ADC3 #endif -#if STM32L4_NADC < 2 -# undef CONFIG_STM32L4_ADC2 +#if STM32_NADC < 2 +# undef CONFIG_STM32_ADC2 #endif -#if STM32L4_NADC < 1 -# undef CONFIG_STM32L4_ADC1 +#if STM32_NADC < 1 +# undef CONFIG_STM32_ADC1 #endif -#if defined(CONFIG_STM32L4_ADC1) || defined(CONFIG_STM32L4_ADC2) || defined(CONFIG_STM32L4_ADC3) +#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) || defined(CONFIG_STM32_ADC3) /* The number of ADC channels in the conversion list */ @@ -77,7 +77,7 @@ * {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 15}; */ -#ifdef CONFIG_STM32L4_ADC1 +#ifdef CONFIG_STM32_ADC1 static const uint8_t g_chanlist_adc1[ADC1_NCHANNELS] = { 3 @@ -98,7 +98,7 @@ static const uint32_t g_pinlist_adc1[ADC1_NCHANNELS] = }; #endif -#ifdef CONFIG_STM32L4_ADC2 +#ifdef CONFIG_STM32_ADC2 static const uint8_t g_chanlist_adc2[ADC2_NCHANNELS] = { 4, @@ -111,7 +111,7 @@ static const uint32_t g_pinlist_adc2[ADC2_NCHANNELS] = }; #endif -#ifdef CONFIG_STM32L4_ADC3 +#ifdef CONFIG_STM32_ADC3 static const uint8_t g_chanlist_adc3[ADC3_NCHANNELS] = { 17, @@ -153,42 +153,42 @@ int stm32_adc_setup(void) { /* Configure the pins as analog inputs for the selected channels */ -#ifdef CONFIG_STM32L4_ADC1 +#ifdef CONFIG_STM32_ADC1 for (i = 0; i < ADC1_NCHANNELS; i++) { if (g_pinlist_adc1[i] != 0) { - stm32l4_configgpio(g_pinlist_adc1[i]); + stm32_configgpio(g_pinlist_adc1[i]); } } #endif -#ifdef CONFIG_STM32L4_ADC2 +#ifdef CONFIG_STM32_ADC2 for (i = 0; i < ADC2_NCHANNELS; i++) { if (g_pinlist_adc2[i] != 0) { - stm32l4_configgpio(g_pinlist_adc2[i]); + stm32_configgpio(g_pinlist_adc2[i]); } } #endif -#ifdef CONFIG_STM32L4_ADC3 +#ifdef CONFIG_STM32_ADC3 for (i = 0; i < ADC3_NCHANNELS; i++) { if (g_pinlist_adc3[i] != 0) { - stm32l4_configgpio(g_pinlist_adc3[i]); + stm32_configgpio(g_pinlist_adc3[i]); } } #endif - /* Call stm32l4_adc_initialize() to get an instance of the ADC + /* Call stm32_adc_initialize() to get an instance of the ADC * interface */ -#ifdef CONFIG_STM32L4_ADC1 - adc = stm32l4_adc_initialize(1, g_chanlist_adc1, ADC1_NCHANNELS); +#ifdef CONFIG_STM32_ADC1 + adc = stm32_adc_initialize(1, g_chanlist_adc1, ADC1_NCHANNELS); if (adc == NULL) { aerr("ERROR: Failed to get ADC1 interface\n"); @@ -205,8 +205,8 @@ int stm32_adc_setup(void) } #endif -#ifdef CONFIG_STM32L4_ADC2 - adc = stm32l4_adc_initialize(2, g_chanlist_adc2, ADC2_NCHANNELS); +#ifdef CONFIG_STM32_ADC2 + adc = stm32_adc_initialize(2, g_chanlist_adc2, ADC2_NCHANNELS); if (adc == NULL) { aerr("ERROR: Failed to get ADC2 interface\n"); @@ -223,8 +223,8 @@ int stm32_adc_setup(void) } #endif -#ifdef CONFIG_STM32L4_ADC3 - adc = stm32l4_adc_initialize(3, g_chanlist_adc3, ADC3_NCHANNELS); +#ifdef CONFIG_STM32_ADC3 + adc = stm32_adc_initialize(3, g_chanlist_adc3, ADC3_NCHANNELS); if (adc == NULL) { aerr("ERROR: Failed to get ADC3 interface\n"); @@ -249,5 +249,5 @@ int stm32_adc_setup(void) return OK; } -#endif /* CONFIG_STM32L4_ADC1 || CONFIG_STM32L4_ADC2 || CONFIG_STM32L4_ADC3 */ +#endif /* CONFIG_STM32_ADC1 || CONFIG_STM32_ADC2 || CONFIG_STM32_ADC3 */ #endif /* CONFIG_ADC */ diff --git a/boards/arm/stm32l4/nucleo-l496zg/src/stm32_autoleds.c b/boards/arm/stm32l4/nucleo-l496zg/src/stm32_autoleds.c index f0d57f250feff..1c728a838d81a 100644 --- a/boards/arm/stm32l4/nucleo-l496zg/src/stm32_autoleds.c +++ b/boards/arm/stm32l4/nucleo-l496zg/src/stm32_autoleds.c @@ -61,7 +61,7 @@ static void phy_set_led(int led, bool state) { /* Active High */ - stm32l4_gpiowrite(g_ledmap[led], state); + stm32_gpiowrite(g_ledmap[led], state); } /**************************************************************************** @@ -80,7 +80,7 @@ void board_autoled_initialize(void) for (i = 0; i < nitems(g_ledmap); i++) { - stm32l4_configgpio(g_ledmap[i]); + stm32_configgpio(g_ledmap[i]); } } diff --git a/boards/arm/stm32l4/nucleo-l496zg/src/stm32_boot.c b/boards/arm/stm32l4/nucleo-l496zg/src/stm32_boot.c index a195c97e0191e..4e59599a7e01a 100644 --- a/boards/arm/stm32l4/nucleo-l496zg/src/stm32_boot.c +++ b/boards/arm/stm32l4/nucleo-l496zg/src/stm32_boot.c @@ -46,7 +46,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_board_initialize + * Name: stm32_board_initialize * * Description: * All STM32 architectures must provide the following entry point. @@ -56,7 +56,7 @@ * ****************************************************************************/ -void stm32l4_board_initialize(void) +void stm32_board_initialize(void) { #ifdef CONFIG_ARCH_LEDS /* Configure on-board LEDs if LED support has been selected. */ @@ -64,7 +64,7 @@ void stm32l4_board_initialize(void) board_autoled_initialize(); #endif -#if defined(CONFIG_STM32L4_OTGFS) || defined(CONFIG_STM32L4_HOST) +#if defined(CONFIG_STM32_OTGFS) || defined(CONFIG_STM32_HOST) stm32_usbinitialize(); #endif diff --git a/boards/arm/stm32l4/nucleo-l496zg/src/stm32_bringup.c b/boards/arm/stm32l4/nucleo-l496zg/src/stm32_bringup.c index 06a09421d54df..b9133caa56d83 100644 --- a/boards/arm/stm32l4/nucleo-l496zg/src/stm32_bringup.c +++ b/boards/arm/stm32l4/nucleo-l496zg/src/stm32_bringup.c @@ -40,16 +40,16 @@ * Private Data ****************************************************************************/ -#if defined(CONFIG_STM32L4_I2C1) +#if defined(CONFIG_STM32_I2C1) struct i2c_master_s *i2c1; #endif -#if defined(CONFIG_STM32L4_I2C2) +#if defined(CONFIG_STM32_I2C2) struct i2c_master_s *i2c2; #endif -#if defined(CONFIG_STM32L4_I2C3) +#if defined(CONFIG_STM32_I2C3) struct i2c_master_s *i2c3; #endif -#if defined(CONFIG_STM32L4_I2C4) +#if defined(CONFIG_STM32_I2C4) struct i2c_master_s *i2c4; #endif @@ -102,7 +102,7 @@ int stm32_bringup(void) syslog(LOG_ERR, "ERROR: stm32_adc_setup failed: %d\n", ret); } -#ifdef CONFIG_STM32L4_DFSDM +#ifdef CONFIG_STM32_DFSDM /* Initialize DFSDM and register its filters as additional ADC devices. */ ret = stm32_dfsdm_setup(); @@ -148,7 +148,7 @@ int stm32_bringup(void) /* Initialize the SDIO block driver */ - ret = stm32l4_sdio_initialize(); + ret = stm32_sdio_initialize(); if (ret != OK) { ferr("ERROR: Failed to initialize MMC/SD driver: %d\n", ret); @@ -161,29 +161,29 @@ int stm32_bringup(void) /* REVISIT: this is ugly! */ -#if defined(CONFIG_STM32L4_I2C1) - i2c1 = stm32l4_i2cbus_initialize(1); +#if defined(CONFIG_STM32_I2C1) + i2c1 = stm32_i2cbus_initialize(1); #endif -#if defined(CONFIG_STM32L4_I2C2) - i2c2 = stm32l4_i2cbus_initialize(2); +#if defined(CONFIG_STM32_I2C2) + i2c2 = stm32_i2cbus_initialize(2); #endif -#if defined(CONFIG_STM32L4_I2C3) - i2c3 = stm32l4_i2cbus_initialize(3); +#if defined(CONFIG_STM32_I2C3) + i2c3 = stm32_i2cbus_initialize(3); #endif -#if defined(CONFIG_STM32L4_I2C4) - i2c4 = stm32l4_i2cbus_initialize(4); +#if defined(CONFIG_STM32_I2C4) + i2c4 = stm32_i2cbus_initialize(4); #endif #ifdef CONFIG_I2C_DRIVER -#if defined(CONFIG_STM32L4_I2C1) +#if defined(CONFIG_STM32_I2C1) i2c_register(i2c1, 1); #endif -#if defined(CONFIG_STM32L4_I2C2) +#if defined(CONFIG_STM32_I2C2) i2c_register(i2c2, 2); #endif -#if defined(CONFIG_STM32L4_I2C3) +#if defined(CONFIG_STM32_I2C3) i2c_register(i2c3, 3); #endif -#if defined(CONFIG_STM32L4_I2C4) +#if defined(CONFIG_STM32_I2C4) i2c_register(i2c4, 4); #endif #endif diff --git a/boards/arm/stm32l4/nucleo-l496zg/src/stm32_buttons.c b/boards/arm/stm32l4/nucleo-l496zg/src/stm32_buttons.c index 0238265167266..16d7a80a1cc4c 100644 --- a/boards/arm/stm32l4/nucleo-l496zg/src/stm32_buttons.c +++ b/boards/arm/stm32l4/nucleo-l496zg/src/stm32_buttons.c @@ -56,7 +56,7 @@ uint32_t board_button_initialize(void) { - stm32l4_configgpio(GPIO_BTN_USER); + stm32_configgpio(GPIO_BTN_USER); return NUM_BUTTONS; } @@ -66,7 +66,7 @@ uint32_t board_button_initialize(void) uint32_t board_buttons(void) { - return stm32l4_gpioread(GPIO_BTN_USER) ? 1 : 0; + return stm32_gpioread(GPIO_BTN_USER) ? 1 : 0; } /**************************************************************************** @@ -98,7 +98,7 @@ int board_button_irq(int id, xcpt_t irqhandler, void *arg) if (id == BUTTON_USER) { - ret = stm32l4_gpiosetevent(GPIO_BTN_USER, true, true, true, + ret = stm32_gpiosetevent(GPIO_BTN_USER, true, true, true, irqhandler, arg); } diff --git a/boards/arm/stm32l4/nucleo-l496zg/src/stm32_dac.c b/boards/arm/stm32l4/nucleo-l496zg/src/stm32_dac.c index 9a303be8f8c14..573f956fc5091 100644 --- a/boards/arm/stm32l4/nucleo-l496zg/src/stm32_dac.c +++ b/boards/arm/stm32l4/nucleo-l496zg/src/stm32_dac.c @@ -41,11 +41,11 @@ * Private Data ****************************************************************************/ -#ifdef CONFIG_STM32L4_DAC1 +#ifdef CONFIG_STM32_DAC1 static struct dac_dev_s *g_dac1; #endif -#ifdef CONFIG_STM32L4_DAC2 +#ifdef CONFIG_STM32_DAC2 static struct dac_dev_s *g_dac2; #endif @@ -65,8 +65,8 @@ int stm32_dac_setup(void) { int ret; -#ifdef CONFIG_STM32L4_DAC1 - g_dac1 = stm32l4_dacinitialize(0); +#ifdef CONFIG_STM32_DAC1 + g_dac1 = stm32_dacinitialize(0); if (g_dac1 == NULL) { aerr("ERROR: Failed to get DAC1 interface\n"); @@ -81,8 +81,8 @@ int stm32_dac_setup(void) } #endif -#ifdef CONFIG_STM32L4_DAC2 - g_dac2 = stm32l4_dacinitialize(1); +#ifdef CONFIG_STM32_DAC2 + g_dac2 = stm32_dacinitialize(1); if (g_dac2 == NULL) { aerr("ERROR: Failed to get DAC2 interface\n"); diff --git a/boards/arm/stm32l4/nucleo-l496zg/src/stm32_dfsdm.c b/boards/arm/stm32l4/nucleo-l496zg/src/stm32_dfsdm.c index 39751a7adad50..ab8ee9c843056 100644 --- a/boards/arm/stm32l4/nucleo-l496zg/src/stm32_dfsdm.c +++ b/boards/arm/stm32l4/nucleo-l496zg/src/stm32_dfsdm.c @@ -35,7 +35,7 @@ #include "stm32l4_dfsdm.h" #include "nucleo-144.h" -#if defined(CONFIG_ADC) && defined(CONFIG_STM32L4_DFSDM) +#if defined(CONFIG_ADC) && defined(CONFIG_STM32_DFSDM) /**************************************************************************** * Public Functions @@ -53,28 +53,28 @@ int stm32_dfsdm_setup(void) { int ret; struct adc_dev_s *adc; -#ifdef CONFIG_STM32L4_DFSDM1_FLT0 +#ifdef CONFIG_STM32_DFSDM1_FLT0 const uint8_t chanlist0[1] = { 0 }; #endif -#ifdef CONFIG_STM32L4_DFSDM1_FLT1 +#ifdef CONFIG_STM32_DFSDM1_FLT1 const uint8_t chanlist1[2] = { 0, 1 }; #endif -#ifdef CONFIG_STM32L4_DFSDM1_FLT2 +#ifdef CONFIG_STM32_DFSDM1_FLT2 const uint8_t chanlist2[8] = { 0, 1, 2, 3, 4, 5, 6, 7 }; #endif -#ifdef CONFIG_STM32L4_DFSDM1_FLT3 +#ifdef CONFIG_STM32_DFSDM1_FLT3 const uint8_t chanlist3[4] = { 6, 5, 4, 3 @@ -88,8 +88,8 @@ int stm32_dfsdm_setup(void) * parallel inputs (CPU/DMA/ADC). */ -#ifdef CONFIG_STM32L4_DFSDM1_FLT0 - adc = stm32l4_dfsdm_initialize(0, chanlist0, 1); +#ifdef CONFIG_STM32_DFSDM1_FLT0 + adc = stm32_dfsdm_initialize(0, chanlist0, 1); if (adc == NULL) { aerr("Failed to get DFSDM FLT0 interface\n"); @@ -104,8 +104,8 @@ int stm32_dfsdm_setup(void) } #endif -#ifdef CONFIG_STM32L4_DFSDM1_FLT1 - adc = stm32l4_dfsdm_initialize(1, chanlist1, 2); +#ifdef CONFIG_STM32_DFSDM1_FLT1 + adc = stm32_dfsdm_initialize(1, chanlist1, 2); if (adc == NULL) { aerr("Failed to get DFSDM FLT1 interface\n"); @@ -120,8 +120,8 @@ int stm32_dfsdm_setup(void) } #endif -#ifdef CONFIG_STM32L4_DFSDM1_FLT2 - adc = stm32l4_dfsdm_initialize(2, chanlist2, 8); +#ifdef CONFIG_STM32_DFSDM1_FLT2 + adc = stm32_dfsdm_initialize(2, chanlist2, 8); if (adc == NULL) { aerr("Failed to get DFSDM FLT2 interface\n"); @@ -136,8 +136,8 @@ int stm32_dfsdm_setup(void) } #endif -#ifdef CONFIG_STM32L4_DFSDM1_FLT3 - adc = stm32l4_dfsdm_initialize(3, chanlist3, 4); +#ifdef CONFIG_STM32_DFSDM1_FLT3 + adc = stm32_dfsdm_initialize(3, chanlist3, 4); if (adc == NULL) { aerr("Failed to get DFSDM FLT3 interface\n"); @@ -157,4 +157,4 @@ int stm32_dfsdm_setup(void) return OK; } -#endif /* CONFIG_ADC && CONFIG_STM32L4_DFSDM */ +#endif /* CONFIG_ADC && CONFIG_STM32_DFSDM */ diff --git a/boards/arm/stm32l4/nucleo-l496zg/src/stm32_sdio.c b/boards/arm/stm32l4/nucleo-l496zg/src/stm32_sdio.c index 30d768cbc0fa2..9a7df66b11e84 100644 --- a/boards/arm/stm32l4/nucleo-l496zg/src/stm32_sdio.c +++ b/boards/arm/stm32l4/nucleo-l496zg/src/stm32_sdio.c @@ -76,11 +76,11 @@ static bool g_sd_inserted; ****************************************************************************/ #ifdef HAVE_NCD -static int stm32l4_ncd_interrupt(int irq, void *context) +static int stm32_ncd_interrupt(int irq, void *context) { bool present; - present = !stm32l4_gpioread(GPIO_SDMMC1_NCD); + present = !stm32_gpioread(GPIO_SDMMC1_NCD); if (g_sdio_dev && present != g_sd_inserted) { sdio_mediachange(g_sdio_dev, present); @@ -103,19 +103,19 @@ static int stm32l4_ncd_interrupt(int irq, void *context) * ****************************************************************************/ -int stm32l4_sdio_initialize(void) +int stm32_sdio_initialize(void) { int ret; #ifdef HAVE_NCD /* Configure the card detect GPIO */ - stm32l4_configgpio(GPIO_SDMMC1_NCD); + stm32_configgpio(GPIO_SDMMC1_NCD); /* Register an interrupt handler for the card detect pin */ - stm32l4_gpiosetevent(GPIO_SDMMC1_NCD, true, true, true, - stm32l4_ncd_interrupt, NULL); + stm32_gpiosetevent(GPIO_SDMMC1_NCD, true, true, true, + stm32_ncd_interrupt, NULL); #endif /* Mount the SDIO-based MMC/SD block driver */ @@ -147,7 +147,7 @@ int stm32l4_sdio_initialize(void) #ifdef HAVE_NCD /* Use SD card detect pin to check if a card is g_sd_inserted */ - g_sd_inserted = !stm32l4_gpioread(GPIO_SDMMC1_NCD); + g_sd_inserted = !stm32_gpioread(GPIO_SDMMC1_NCD); finfo("Card detect : %d\n", g_sd_inserted); sdio_mediachange(g_sdio_dev, g_sd_inserted); diff --git a/boards/arm/stm32l4/nucleo-l496zg/src/stm32_spi.c b/boards/arm/stm32l4/nucleo-l496zg/src/stm32_spi.c index 5dc14e26e1459..f39ee47e68997 100644 --- a/boards/arm/stm32l4/nucleo-l496zg/src/stm32_spi.c +++ b/boards/arm/stm32l4/nucleo-l496zg/src/stm32_spi.c @@ -95,7 +95,7 @@ * Private Data ****************************************************************************/ -#if defined(CONFIG_STM32L4_SPI1) +#if defined(CONFIG_STM32_SPI1) static const uint32_t g_spi1gpio[] = { # if defined(GPIO_SPI1_CS0) @@ -121,7 +121,7 @@ static const uint32_t g_spi1gpio[] = }; #endif -#if defined(CONFIG_STM32L4_SPI2) +#if defined(CONFIG_STM32_SPI2) static const uint32_t g_spi2gpio[] = { # if defined(GPIO_SPI2_CS0) @@ -147,7 +147,7 @@ static const uint32_t g_spi2gpio[] = }; #endif -#if defined(CONFIG_STM32L4_SPI3) +#if defined(CONFIG_STM32_SPI3) static const uint32_t g_spi3gpio[] = { # if defined(GPIO_SPI3_CS0) @@ -174,13 +174,13 @@ static const uint32_t g_spi3gpio[] = #endif #if defined(CONFIG_NUCLEO_SPI_TEST) -# if defined(CONFIG_STM32L4_SPI1) +# if defined(CONFIG_STM32_SPI1) struct spi_dev_s *spi1; # endif -# if defined(CONFIG_STM32L4_SPI2) +# if defined(CONFIG_STM32_SPI2) struct spi_dev_s *spi2; # endif -# if defined(CONFIG_STM32L4_SPI3) +# if defined(CONFIG_STM32_SPI3) struct spi_dev_s *spi3; # endif #endif @@ -201,32 +201,32 @@ void weak_function stm32_spidev_initialize(void) { /* Configure SPI CS GPIO for output */ -#if defined(CONFIG_STM32L4_SPI1) +#if defined(CONFIG_STM32_SPI1) for (int i = 0; i < nitems(g_spi1gpio); i++) { if (g_spi1gpio[i] != 0) { - stm32l4_configgpio(g_spi1gpio[i]); + stm32_configgpio(g_spi1gpio[i]); } } #endif -#if defined(CONFIG_STM32L4_SPI2) +#if defined(CONFIG_STM32_SPI2) for (int i = 0; i < nitems(g_spi2gpio); i++) { if (g_spi2gpio[i] != 0) { - stm32l4_configgpio(g_spi2gpio[i]); + stm32_configgpio(g_spi2gpio[i]); } } #endif -#if defined(CONFIG_STM32L4_SPI3) +#if defined(CONFIG_STM32_SPI3) for (int i = 0; i < nitems(g_spi3gpio); i++) { if (g_spi3gpio[i] != 0) { - stm32l4_configgpio(g_spi3gpio[i]); + stm32_configgpio(g_spi3gpio[i]); } } #endif @@ -258,7 +258,7 @@ void weak_function stm32_spidev_initialize(void) * ****************************************************************************/ -#ifdef CONFIG_STM32L4_SPI1 +#ifdef CONFIG_STM32_SPI1 void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -269,7 +269,7 @@ void stm32_spi1select(struct spi_dev_s *dev, if (g_spi1gpio[index] != 0) { - stm32l4_gpiowrite(g_spi1gpio[index], !selected); + stm32_gpiowrite(g_spi1gpio[index], !selected); } } @@ -279,7 +279,7 @@ uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32L4_SPI2 +#ifdef CONFIG_STM32_SPI2 void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -290,7 +290,7 @@ void stm32_spi2select(struct spi_dev_s *dev, if (g_spi2gpio[index] != 0) { - stm32l4_gpiowrite(g_spi2gpio[index], !selected); + stm32_gpiowrite(g_spi2gpio[index], !selected); } } @@ -300,7 +300,7 @@ uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32L4_SPI3 +#ifdef CONFIG_STM32_SPI3 void stm32_spi3select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -311,7 +311,7 @@ void stm32_spi3select(struct spi_dev_s *dev, if (g_spi3gpio[index] != 0) { - stm32l4_gpiowrite(g_spi3gpio[index], !selected); + stm32_gpiowrite(g_spi3gpio[index], !selected); } } @@ -345,21 +345,21 @@ uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid) ****************************************************************************/ #ifdef CONFIG_SPI_CMDDATA -#ifdef CONFIG_STM32L4_SPI1 +#ifdef CONFIG_STM32_SPI1 int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32L4_SPI2 +#ifdef CONFIG_STM32_SPI2 int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32L4_SPI3 +#ifdef CONFIG_STM32_SPI3 int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; @@ -393,7 +393,7 @@ int stm32_spidev_bus_test(void) #endif #if defined(CONFIG_NUCLEO_SPI2_TEST) - spi2 = stm32l4_spibus_initialize(2); + spi2 = stm32_spibus_initialize(2); if (!spi2) { @@ -410,7 +410,7 @@ int stm32_spidev_bus_test(void) #endif #if defined(CONFIG_NUCLEO_SPI3_TEST) - spi3 = stm32l4_spibus_initialize(3); + spi3 = stm32_spibus_initialize(3); if (!spi3) { diff --git a/boards/arm/stm32l4/nucleo-l496zg/src/stm32_uid.c b/boards/arm/stm32l4/nucleo-l496zg/src/stm32_uid.c index 277f8527b9a7e..399675787a61c 100644 --- a/boards/arm/stm32l4/nucleo-l496zg/src/stm32_uid.c +++ b/boards/arm/stm32l4/nucleo-l496zg/src/stm32_uid.c @@ -38,7 +38,7 @@ #include -#include "stm32l4_uid.h" +#include "stm32_uid.h" #include "nucleo-144.h" /**************************************************************************** @@ -56,6 +56,6 @@ int board_uniqueid(uint8_t *uniqueid) return -EINVAL; } - stm32l4_get_uniqueid(uniqueid); + stm32_get_uniqueid(uniqueid); return OK; } diff --git a/boards/arm/stm32l4/nucleo-l496zg/src/stm32_usb.c b/boards/arm/stm32l4/nucleo-l496zg/src/stm32_usb.c index 4e6e5010ed82b..a499ca891ce06 100644 --- a/boards/arm/stm32l4/nucleo-l496zg/src/stm32_usb.c +++ b/boards/arm/stm32l4/nucleo-l496zg/src/stm32_usb.c @@ -45,7 +45,7 @@ #include "stm32l4_otgfs.h" #include "nucleo-144.h" -#ifdef CONFIG_STM32L4_OTGFS +#ifdef CONFIG_STM32_OTGFS /**************************************************************************** * Pre-processor Definitions @@ -138,10 +138,10 @@ void stm32_usbinitialize(void) * Power On, and Overcurrent GPIOs */ -#ifdef CONFIG_STM32L4_OTGFS - stm32l4_configgpio(GPIO_OTGFS_VBUS); - stm32l4_configgpio(GPIO_OTGFS_PWRON); - stm32l4_configgpio(GPIO_OTGFS_OVER); +#ifdef CONFIG_STM32_OTGFS + stm32_configgpio(GPIO_OTGFS_VBUS); + stm32_configgpio(GPIO_OTGFS_PWRON); + stm32_configgpio(GPIO_OTGFS_OVER); #endif } @@ -220,7 +220,7 @@ int stm32_usbhost_initialize(void) /* Then get an instance of the USB host interface */ uinfo("Initialize USB host\n"); - g_usbconn = stm32l4_otgfshost_initialize(0); + g_usbconn = stm32_otgfshost_initialize(0); if (g_usbconn) { /* Start a thread to handle device connection. */ @@ -273,7 +273,7 @@ void stm32_usbhost_vbusdrive(int iface, bool enable) /* Set the Power Switch by driving the active low enable pin */ - stm32l4_gpiowrite(GPIO_OTGFS_PWRON, !enable); + stm32_gpiowrite(GPIO_OTGFS_PWRON, !enable); } #endif @@ -297,7 +297,7 @@ void stm32_usbhost_vbusdrive(int iface, bool enable) #ifdef CONFIG_USBHOST int stm32_setup_overcurrent(xcpt_t handler, void *arg) { - return stm32l4_gpiosetevent(GPIO_OTGFS_OVER, + return stm32_gpiosetevent(GPIO_OTGFS_OVER, true, true, true, handler, arg); } #endif @@ -314,7 +314,7 @@ int stm32_setup_overcurrent(xcpt_t handler, void *arg) ****************************************************************************/ #ifdef CONFIG_USBDEV -void stm32l4_usbsuspend(struct usbdev_s *dev, bool resume) +void stm32_usbsuspend(struct usbdev_s *dev, bool resume) { uinfo("resume: %d\n", resume); } diff --git a/boards/arm/stm32l4/nucleo-l496zg/src/stm32_userleds.c b/boards/arm/stm32l4/nucleo-l496zg/src/stm32_userleds.c index 578fa289a31b2..a981d49c6fbcb 100644 --- a/boards/arm/stm32l4/nucleo-l496zg/src/stm32_userleds.c +++ b/boards/arm/stm32l4/nucleo-l496zg/src/stm32_userleds.c @@ -77,7 +77,7 @@ uint32_t board_userled_initialize(void) for (i = 0; i < nitems(g_ledcfg); i++) { - stm32l4_configgpio(g_ledcfg[i]); + stm32_configgpio(g_ledcfg[i]); } return BOARD_NLEDS; @@ -97,7 +97,7 @@ void board_userled(int led, bool ledon) { if ((unsigned)led < nitems(g_ledcfg)) { - stm32l4_gpiowrite(g_ledcfg[led], ledon); + stm32_gpiowrite(g_ledcfg[led], ledon); } } @@ -120,7 +120,7 @@ void board_userled_all(uint32_t ledset) for (i = 0; i < nitems(g_ledcfg); i++) { - stm32l4_gpiowrite(g_ledcfg[i], (ledset & (1 << i)) != 0); + stm32_gpiowrite(g_ledcfg[i], (ledset & (1 << i)) != 0); } } diff --git a/boards/arm/stm32l4/steval-stlcs01v1/configs/lwl/defconfig b/boards/arm/stm32l4/steval-stlcs01v1/configs/lwl/defconfig index 135cc3d507056..fb9fe5e39144a 100644 --- a/boards/arm/stm32l4/steval-stlcs01v1/configs/lwl/defconfig +++ b/boards/arm/stm32l4/steval-stlcs01v1/configs/lwl/defconfig @@ -14,6 +14,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="steval-stlcs01v1" CONFIG_ARCH_BOARD_STEVAL_STLCS01V1=y CONFIG_ARCH_CHIP="stm32l4" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32L476JG=y CONFIG_ARCH_CHIP_STM32L4=y CONFIG_ARCH_INTERRUPTSTACK=2048 @@ -37,7 +38,7 @@ CONFIG_RAM_START=0x20000000 CONFIG_RAW_BINARY=y CONFIG_RR_INTERVAL=200 CONFIG_SCHED_WAITPID=y -CONFIG_STM32L4_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_TESTING_OSTEST=y diff --git a/boards/arm/stm32l4/steval-stlcs01v1/configs/usbnsh/defconfig b/boards/arm/stm32l4/steval-stlcs01v1/configs/usbnsh/defconfig index 8a7ad6bdecd6c..a5db2db05187d 100644 --- a/boards/arm/stm32l4/steval-stlcs01v1/configs/usbnsh/defconfig +++ b/boards/arm/stm32l4/steval-stlcs01v1/configs/usbnsh/defconfig @@ -14,6 +14,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="steval-stlcs01v1" CONFIG_ARCH_BOARD_STEVAL_STLCS01V1=y CONFIG_ARCH_CHIP="stm32l4" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32L476JG=y CONFIG_ARCH_CHIP_STM32L4=y CONFIG_ARCH_INTERRUPTSTACK=2048 @@ -40,9 +41,9 @@ CONFIG_RAM_START=0x20000000 CONFIG_RAW_BINARY=y CONFIG_RR_INTERVAL=200 CONFIG_SCHED_WAITPID=y -CONFIG_STM32L4_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32L4_OTGFS=y -CONFIG_STM32L4_SAI1PLL=y +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_SAI1PLL=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USBDEV=y diff --git a/boards/arm/stm32l4/steval-stlcs01v1/include/board.h b/boards/arm/stm32l4/steval-stlcs01v1/include/board.h index 7c5ffc6ddfb78..0526495312eb5 100644 --- a/boards/arm/stm32l4/steval-stlcs01v1/include/board.h +++ b/boards/arm/stm32l4/steval-stlcs01v1/include/board.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32L4_STEVAL_STLCS01V1_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32L4_STEVAL_STLCS01V1_INCLUDE_BOARD_H +#ifndef __BOARDS_ARM_STM32_STEVAL_STLCS01V1_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32_STEVAL_STLCS01V1_INCLUDE_BOARD_H /**************************************************************************** * Included Files @@ -37,16 +37,16 @@ /* System Clock source : PLL (HSI) * SYSCLK(Hz) : 80000000 Determined by PLL configuration - * HCLK(Hz) : 80000000 (STM32L4_RCC_CFGR_HPRE) (Max 80 MHz) - * AHB Prescaler : 1 (STM32L4_RCC_CFGR_HPRE) (Max 80 MHz) - * APB1 Prescaler : 1 (STM32L4_RCC_CFGR_PPRE1) (Max 80 MHz) - * APB2 Prescaler : 1 (STM32L4_RCC_CFGR_PPRE2) (Max 80 MHz) + * HCLK(Hz) : 80000000 (STM32_RCC_CFGR_HPRE) (Max 80 MHz) + * AHB Prescaler : 1 (STM32_RCC_CFGR_HPRE) (Max 80 MHz) + * APB1 Prescaler : 1 (STM32_RCC_CFGR_PPRE1) (Max 80 MHz) + * APB2 Prescaler : 1 (STM32_RCC_CFGR_PPRE2) (Max 80 MHz) * HSI Frequency(Hz) : 16000000 (nominal) - * PLLM : 1 (STM32L4_PLLCFG_PLLM) - * PLLN : 10 (STM32L4_PLLCFG_PLLN) - * PLLP : 0 (STM32L4_PLLCFG_PLLP) - * PLLQ : 0 (STM32L4_PLLCFG_PLLQ) - * PLLR : 2 (STM32L4_PLLCFG_PLLR) + * PLLM : 1 (STM32_PLLCFG_PLLM) + * PLLN : 10 (STM32_PLLCFG_PLLN) + * PLLP : 0 (STM32_PLLCFG_PLLP) + * PLLQ : 0 (STM32_PLLCFG_PLLQ) + * PLLR : 2 (STM32_PLLCFG_PLLR) * PLLSAI1N : 12 * PLLSAI1Q : 4 * Flash Latency(WS) : 4 @@ -62,11 +62,11 @@ * LSE - 32.768 kHz installed */ -#define STM32L4_HSI_FREQUENCY 16000000ul -#define STM32L4_LSI_FREQUENCY 32000 -#define STM32L4_LSE_FREQUENCY 32768 +#define STM32_HSI_FREQUENCY 16000000ul +#define STM32_LSI_FREQUENCY 32000 +#define STM32_LSE_FREQUENCY 32768 -#define STM32L4_BOARD_USEHSI 1 +#define STM32_BOARD_USEHSI 1 /* XXX sysclk mux = pllclk */ @@ -106,7 +106,7 @@ * * PLL source is HSI * - * PLL_REF = STM32L4_HSI_FREQUENCY / PLLM + * PLL_REF = STM32_HSI_FREQUENCY / PLLM * = 16,000,000 / 1 * = 16,000,000 * @@ -125,7 +125,7 @@ * * The clock input and M divider are identical to the main PLL. * However the multiplier and postscalers are independent. - * The PLLSAI1 is configured only if CONFIG_STM32L4_SAI1PLL is defined + * The PLLSAI1 is configured only if CONFIG_STM32_SAI1PLL is defined * * SAI1VCO input frequency = PLL input clock frequency * SAI1VCO output frequency = SAI1VCO input frequency × PLLSAI1N, @@ -147,7 +147,7 @@ * * The clock input and M divider are identical to the main PLL. * However the multiplier and postscalers are independent. - * The PLLSAI2 is configured only if CONFIG_STM32L4_SAI2PLL is defined + * The PLLSAI2 is configured only if CONFIG_STM32_SAI2PLL is defined * * SAI2VCO input frequency = PLL input clock frequency * SAI2VCO output frequency = SAI2VCO input frequency × PLLSAI2N, @@ -165,7 +165,7 @@ * as per comment above HSI) . */ -#define STM32L4_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) /* 'main' PLL config; we use this to generate our system clock via the R * output. We set it up as 16 MHz / 1 * 10 / 2 = 80 MHz @@ -176,13 +176,13 @@ * applications may want things done this way. */ -#define STM32L4_PLLCFG_PLLN RCC_PLLCFG_PLLN(10) -#define STM32L4_PLLCFG_PLLP 0 -#undef STM32L4_PLLCFG_PLLP_ENABLED -#define STM32L4_PLLCFG_PLLQ RCC_PLLCFG_PLLQ_2 -#define STM32L4_PLLCFG_PLLQ_ENABLED -#define STM32L4_PLLCFG_PLLR RCC_PLLCFG_PLLR(2) -#define STM32L4_PLLCFG_PLLR_ENABLED +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(10) +#define STM32_PLLCFG_PLLP 0 +#undef STM32_PLLCFG_PLLP_ENABLED +#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ_2 +#define STM32_PLLCFG_PLLQ_ENABLED +#define STM32_PLLCFG_PLLR RCC_PLLCFG_PLLR(2) +#define STM32_PLLCFG_PLLR_ENABLED /* 'SAIPLL1' is used to generate the 48 MHz clock, since we can't * do that with the main PLL's N value. We set N = 12, and enable @@ -196,87 +196,87 @@ * that is selected via a #define here, like all these other params. */ -#define STM32L4_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(12) -#define STM32L4_PLLSAI1CFG_PLLP 0 -#undef STM32L4_PLLSAI1CFG_PLLP_ENABLED -#define STM32L4_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_4 -#define STM32L4_PLLSAI1CFG_PLLQ_ENABLED -#define STM32L4_PLLSAI1CFG_PLLR 0 -#undef STM32L4_PLLSAI1CFG_PLLR_ENABLED +#define STM32_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(12) +#define STM32_PLLSAI1CFG_PLLP 0 +#undef STM32_PLLSAI1CFG_PLLP_ENABLED +#define STM32_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_4 +#define STM32_PLLSAI1CFG_PLLQ_ENABLED +#define STM32_PLLSAI1CFG_PLLR 0 +#undef STM32_PLLSAI1CFG_PLLR_ENABLED /* 'SAIPLL2' is not used in this application */ -#define STM32L4_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) -#define STM32L4_PLLSAI2CFG_PLLP 0 -#undef STM32L4_PLLSAI2CFG_PLLP_ENABLED -#define STM32L4_PLLSAI2CFG_PLLR 0 -#undef STM32L4_PLLSAI2CFG_PLLR_ENABLED +#define STM32_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) +#define STM32_PLLSAI2CFG_PLLP 0 +#undef STM32_PLLSAI2CFG_PLLP_ENABLED +#define STM32_PLLSAI2CFG_PLLR 0 +#undef STM32_PLLSAI2CFG_PLLR_ENABLED -#define STM32L4_SYSCLK_FREQUENCY 80000000ul +#define STM32_SYSCLK_FREQUENCY 80000000ul /* CLK48 will come from PLLSAI1 (implicitly Q) */ -#define STM32L4_USE_CLK48 -#define STM32L4_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 +#define STM32_USE_CLK48 +#define STM32_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 /* enable the LSE oscillator, used automatically trim the MSI, and for RTC */ -#define STM32L4_USE_LSE 1 +#define STM32_USE_LSE 1 /* AHB clock (HCLK) is SYSCLK (80MHz) */ -#define STM32L4_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ -#define STM32L4_HCLK_FREQUENCY STM32L4_SYSCLK_FREQUENCY +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY /* APB1 clock (PCLK1) is HCLK/1 (80MHz) */ -#define STM32L4_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ -#define STM32L4_PCLK1_FREQUENCY (STM32L4_HCLK_FREQUENCY / 1) +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY / 1) /* Timers driven from APB1 will be twice PCLK1 */ /* REVISIT : this can be configured */ -#define STM32L4_APB1_TIM2_CLKIN (2 * STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM3_CLKIN (2 * STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM4_CLKIN (2 * STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM5_CLKIN (2 * STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM6_CLKIN (2 * STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM7_CLKIN (2 * STM32L4_PCLK1_FREQUENCY) +#define STM32_APB1_TIM2_CLKIN (2 * STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (2 * STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (2 * STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM5_CLKIN (2 * STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (2 * STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (2 * STM32_PCLK1_FREQUENCY) /* APB2 clock (PCLK2) is HCLK (80MHz) */ -#define STM32L4_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ -#define STM32L4_PCLK2_FREQUENCY (STM32L4_HCLK_FREQUENCY / 1) +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ +#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY / 1) /* Timers driven from APB2 will be twice PCLK2 */ /* REVISIT : this can be configured */ -#define STM32L4_APB2_TIM1_CLKIN (2*STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM8_CLKIN (2*STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM15_CLKIN (2*STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM16_CLKIN (2*STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM17_CLKIN (2*STM32L4_PCLK2_FREQUENCY) +#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM15_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM16_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM17_CLKIN (2*STM32_PCLK2_FREQUENCY) /* Timer Frequencies, if APBx is set to 1, frequency is same to APBx * otherwise frequency is 2xAPBx. * Note: TIM1,8,15,16,17 are on APB2, others on APB1 */ -#define BOARD_TIM1_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM2_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2) -#define BOARD_TIM3_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2) -#define BOARD_TIM4_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2) -#define BOARD_TIM5_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2) -#define BOARD_TIM6_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2) -#define BOARD_TIM7_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2) -#define BOARD_TIM8_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM15_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM16_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM17_FREQUENCY STM32L4_HCLK_FREQUENCY -#define STM32L4_LPTIM1_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2) -#define STM32L4_LPTIM2_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2) +#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM2_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM3_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM4_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM5_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM6_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM7_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM15_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM16_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM17_FREQUENCY STM32_HCLK_FREQUENCY +#define STM32_LPTIM1_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define STM32_LPTIM2_FREQUENCY (STM32_HCLK_FREQUENCY / 2) /**************************************************************************** * Pre-processor Definitions @@ -357,4 +357,4 @@ #define GPIO_OTGFS_ID GPIO_OTGFS_ID_0 /* PA10 */ #define GPIO_OTGFS_SOF GPIO_OTGFS_SOF_0 /* PA8 */ -#endif /* __BOARDS_ARM_STM32L4_STEVAL_STLCS01V1_INCLUDE_BOARD_H */ +#endif /* __BOARDS_ARM_STM32_STEVAL_STLCS01V1_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32l4/steval-stlcs01v1/src/CMakeLists.txt b/boards/arm/stm32l4/steval-stlcs01v1/src/CMakeLists.txt index 88aa47097ced8..2a3de594681ee 100644 --- a/boards/arm/stm32l4/steval-stlcs01v1/src/CMakeLists.txt +++ b/boards/arm/stm32l4/steval-stlcs01v1/src/CMakeLists.txt @@ -26,7 +26,7 @@ if(CONFIG_ARCH_LEDS) list(APPEND SRCS stm32_autoleds.c) endif() -if(CONFIG_STM32L4_OTGFS) +if(CONFIG_STM32_OTGFS) list(APPEND SRCS stm32_usb.c) endif() diff --git a/boards/arm/stm32l4/steval-stlcs01v1/src/Make.defs b/boards/arm/stm32l4/steval-stlcs01v1/src/Make.defs new file mode 100644 index 0000000000000..e67f020257ee0 --- /dev/null +++ b/boards/arm/stm32l4/steval-stlcs01v1/src/Make.defs @@ -0,0 +1,37 @@ +############################################################################ +# boards/arm/stm32l4/steval-stlcs01v1/src/Makefile +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +CSRCS = stm32_boot.c stm32_bringup.c + +ifeq ($(CONFIG_ARCH_LEDS),y) +CSRCS += stm32_autoleds.c +endif + +ifeq ($(CONFIG_STM32_OTGFS),y) +CSRCS += stm32_usb.c +endif + +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32l4/steval-stlcs01v1/src/Makefile b/boards/arm/stm32l4/steval-stlcs01v1/src/Makefile deleted file mode 100644 index e46d406cb3eb9..0000000000000 --- a/boards/arm/stm32l4/steval-stlcs01v1/src/Makefile +++ /dev/null @@ -1,35 +0,0 @@ -############################################################################ -# boards/arm/stm32l4/steval-stlcs01v1/src/Makefile -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/Make.defs - -CSRCS = stm32_boot.c stm32_bringup.c - -ifeq ($(CONFIG_ARCH_LEDS),y) -CSRCS += stm32_autoleds.c -endif - -ifeq ($(CONFIG_STM32L4_OTGFS),y) -CSRCS += stm32_usb.c -endif - -include $(TOPDIR)/boards/Board.mk diff --git a/boards/arm/stm32l4/steval-stlcs01v1/src/steval-stlcs01v1.h b/boards/arm/stm32l4/steval-stlcs01v1/src/steval-stlcs01v1.h index b206a8d27d897..68917c358af35 100644 --- a/boards/arm/stm32l4/steval-stlcs01v1/src/steval-stlcs01v1.h +++ b/boards/arm/stm32l4/steval-stlcs01v1/src/steval-stlcs01v1.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32L4_STEVAL_STLCS01V1_SRC_STEVAL_STLCS01V1_H -#define __BOARDS_ARM_STM32L4_STEVAL_STLCS01V1_SRC_STEVAL_STLCS01V1_H +#ifndef __BOARDS_ARM_STM32_STEVAL_STLCS01V1_SRC_STEVAL_STLCS01V1_H +#define __BOARDS_ARM_STM32_STEVAL_STLCS01V1_SRC_STEVAL_STLCS01V1_H /**************************************************************************** * Included Files @@ -72,7 +72,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_bringup + * Name: stm32_bringup * * Description: * Perform architecture specific initialization @@ -82,10 +82,10 @@ * ****************************************************************************/ -int stm32l4_bringup(void); +int stm32_bringup(void); /**************************************************************************** - * Name: stm32l4_usbinitialize + * Name: stm32_usbinitialize * * Description: * Called from stm32_usbinitialize very early in initialization to setup @@ -93,8 +93,8 @@ int stm32l4_bringup(void); * ****************************************************************************/ -#ifdef CONFIG_STM32L4_OTGFS -void weak_function stm32l4_usbinitialize(void); +#ifdef CONFIG_STM32_OTGFS +void weak_function stm32_usbinitialize(void); #endif -#endif /* __BOARDS_ARM_STM32L4_STEVAL_STLCS01V1_SRC_STEVAL_STLCS01V1_H */ +#endif /* __BOARDS_ARM_STM32_STEVAL_STLCS01V1_SRC_STEVAL_STLCS01V1_H */ diff --git a/boards/arm/stm32l4/steval-stlcs01v1/src/stm32_autoleds.c b/boards/arm/stm32l4/steval-stlcs01v1/src/stm32_autoleds.c index 577914d757f4f..ea26a99180087 100644 --- a/boards/arm/stm32l4/steval-stlcs01v1/src/stm32_autoleds.c +++ b/boards/arm/stm32l4/steval-stlcs01v1/src/stm32_autoleds.c @@ -31,7 +31,7 @@ #include #include -#include "stm32l4.h" +#include "stm32.h" #include "steval-stlcs01v1.h" @@ -47,7 +47,7 @@ void board_autoled_initialize(void) { /* Configure LD1 GPIO for output */ - stm32l4_configgpio(GPIO_LD1); + stm32_configgpio(GPIO_LD1); } /**************************************************************************** @@ -58,7 +58,7 @@ void board_autoled_on(int led) { if (led == 1) { - stm32l4_gpiowrite(GPIO_LD1, true); + stm32_gpiowrite(GPIO_LD1, true); } } @@ -70,6 +70,6 @@ void board_autoled_off(int led) { if (led == 1) { - stm32l4_gpiowrite(GPIO_LD1, false); + stm32_gpiowrite(GPIO_LD1, false); } } diff --git a/boards/arm/stm32l4/steval-stlcs01v1/src/stm32_boot.c b/boards/arm/stm32l4/steval-stlcs01v1/src/stm32_boot.c index 08d07d743c6cb..5908bb4deac4e 100644 --- a/boards/arm/stm32l4/steval-stlcs01v1/src/stm32_boot.c +++ b/boards/arm/stm32l4/steval-stlcs01v1/src/stm32_boot.c @@ -42,7 +42,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_board_initialize + * Name: stm32_board_initialize * * Description: * All STM32L4 architectures must provide the following entry point. This @@ -52,28 +52,28 @@ * ****************************************************************************/ -void stm32l4_board_initialize(void) +void stm32_board_initialize(void) { /* Initialize USB if the 1) OTG FS controller is in the configuration and - * 2) disabled, and 3) the weak function stm32l4_usbinitialize() has been + * 2) disabled, and 3) the weak function stm32_usbinitialize() has been * brought into the build. Presumably either CONFIG_USBDEV is also * selected. */ -#ifdef CONFIG_STM32L4_OTGFS +#ifdef CONFIG_STM32_OTGFS /* Enable Vddusb - mandatory to use the USB OTG FS peripheral */ - stm32l4_pwr_enableusv(true); + stm32_pwr_enableusv(true); - if (stm32l4_usbinitialize) + if (stm32_usbinitialize) { - stm32l4_usbinitialize(); + stm32_usbinitialize(); } #endif /* Enable Vddio2 - mandatory to use the PG2 - PG15 I/Os. */ - stm32l4_pwr_vddio2_valid(true); + stm32_pwr_vddio2_valid(true); /* Configure on-board LEDs if LED support has been selected. */ @@ -101,6 +101,6 @@ void board_late_initialize(void) { /* Perform board-specific initialization */ - stm32l4_bringup(); + stm32_bringup(); } #endif diff --git a/boards/arm/stm32l4/steval-stlcs01v1/src/stm32_bringup.c b/boards/arm/stm32l4/steval-stlcs01v1/src/stm32_bringup.c index d885272feb37a..108b28ef4905e 100644 --- a/boards/arm/stm32l4/steval-stlcs01v1/src/stm32_bringup.c +++ b/boards/arm/stm32l4/steval-stlcs01v1/src/stm32_bringup.c @@ -36,7 +36,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_bringup + * Name: stm32_bringup * * Description: * Perform architecture-specific initialization @@ -46,7 +46,7 @@ * ****************************************************************************/ -int stm32l4_bringup(void) +int stm32_bringup(void) { int ret = OK; diff --git a/boards/arm/stm32l4/steval-stlcs01v1/src/stm32_usb.c b/boards/arm/stm32l4/steval-stlcs01v1/src/stm32_usb.c index 933115652dbfb..87f30cd3ee766 100644 --- a/boards/arm/stm32l4/steval-stlcs01v1/src/stm32_usb.c +++ b/boards/arm/stm32l4/steval-stlcs01v1/src/stm32_usb.c @@ -35,11 +35,11 @@ #include #include #include -#include "stm32l4.h" +#include "stm32.h" #include "stm32l4_otgfs.h" #include "steval-stlcs01v1.h" -#ifdef CONFIG_STM32L4_OTGFS +#ifdef CONFIG_STM32_OTGFS /**************************************************************************** * Pre-processor Definitions @@ -48,7 +48,7 @@ #if defined(CONFIG_USBDEV) # define HAVE_USB 1 #else -# warning "CONFIG_STM32L4_OTGFS is enabled but not CONFIG_USBDEV" +# warning "CONFIG_STM32_OTGFS is enabled but not CONFIG_USBDEV" # undef HAVE_USB #endif @@ -65,15 +65,15 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_usbinitialize + * Name: stm32_usbinitialize * * Description: - * Called from stm32l4_usbinitialize very early in initialization to setup + * Called from stm32_usbinitialize very early in initialization to setup * USB-related GPIO pins for the board. * ****************************************************************************/ -void stm32l4_usbinitialize(void) +void stm32_usbinitialize(void) { /* The OTG FS has an internal soft pull-up. * No GPIO configuration is required @@ -81,10 +81,10 @@ void stm32l4_usbinitialize(void) } /**************************************************************************** - * Name: stm32l4_usbsuspend + * Name: stm32_usbsuspend * * Description: - * Board logic must provide the stm32l4_usbsuspend logic if the USBDEV + * Board logic must provide the stm32_usbsuspend logic if the USBDEV * driver is used. This function is called whenever the USB enters or * leaves suspend mode. * This is an opportunity for the board logic to shutdown clocks, power, @@ -93,10 +93,10 @@ void stm32l4_usbinitialize(void) ****************************************************************************/ #ifdef CONFIG_USBDEV -void stm32l4_usbsuspend(struct usbdev_s *dev, bool resume) +void stm32_usbsuspend(struct usbdev_s *dev, bool resume) { uinfo("resume: %d\n", resume); } #endif -#endif /* CONFIG_STM32L4_OTGFS */ +#endif /* CONFIG_STM32_OTGFS */ diff --git a/boards/arm/stm32l4/stm32l476-mdk/configs/nsh/defconfig b/boards/arm/stm32l4/stm32l476-mdk/configs/nsh/defconfig index 875e7b30a1792..a3ccc532ef2a9 100644 --- a/boards/arm/stm32l4/stm32l476-mdk/configs/nsh/defconfig +++ b/boards/arm/stm32l4/stm32l476-mdk/configs/nsh/defconfig @@ -13,6 +13,7 @@ CONFIG_ARCH_BOARD="stm32l476-mdk" CONFIG_ARCH_BOARD_STM32L476_MDK=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32l4" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32L476RG=y CONFIG_ARCH_CHIP_STM32L4=y CONFIG_ARCH_INTERRUPTSTACK=2048 @@ -48,14 +49,14 @@ CONFIG_RTC_IOCTL=y CONFIG_RTC_NALARMS=2 CONFIG_SCHED_WAITPID=y CONFIG_SPI=y -CONFIG_STM32L4_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32L4_DMA1=y -CONFIG_STM32L4_DMA2=y -CONFIG_STM32L4_PWR=y -CONFIG_STM32L4_RNG=y -CONFIG_STM32L4_RTC=y -CONFIG_STM32L4_SAI1PLL=y -CONFIG_STM32L4_USART3=y +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_DMA1=y +CONFIG_STM32_DMA2=y +CONFIG_STM32_PWR=y +CONFIG_STM32_RNG=y +CONFIG_STM32_RTC=y +CONFIG_STM32_SAI1PLL=y +CONFIG_STM32_USART3=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART3_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32l4/stm32l476-mdk/include/board.h b/boards/arm/stm32l4/stm32l476-mdk/include/board.h index 679e0d42ce82d..6c4c5b5a525be 100644 --- a/boards/arm/stm32l4/stm32l476-mdk/include/board.h +++ b/boards/arm/stm32l4/stm32l476-mdk/include/board.h @@ -34,8 +34,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32L4_STM32L476_MDK_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32L4_STM32L476_MDK_INCLUDE_BOARD_H +#ifndef __BOARDS_ARM_STM32_STM32L476_MDK_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32_STM32L476_MDK_INCLUDE_BOARD_H /**************************************************************************** * Included Files @@ -200,7 +200,7 @@ extern "C" ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_board_initialize + * Name: stm32_board_initialize * * Description: * All STM32L4 architectures must provide the following entry point. This @@ -210,7 +210,7 @@ extern "C" * ****************************************************************************/ -void stm32l4_board_initialize(void); +void stm32_board_initialize(void); #undef EXTERN #if defined(__cplusplus) @@ -218,4 +218,4 @@ void stm32l4_board_initialize(void); #endif #endif /* __ASSEMBLY__ */ -#endif /* __BOARDS_ARM_STM32L4_STM32L476_MDK_INCLUDE_BOARD_H */ +#endif /* __BOARDS_ARM_STM32_STM32L476_MDK_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32l4/stm32l476-mdk/include/stm32l476-mdk-clocking.h b/boards/arm/stm32l4/stm32l476-mdk/include/stm32l476-mdk-clocking.h index ce9c293eddccf..7522919c39291 100644 --- a/boards/arm/stm32l4/stm32l476-mdk/include/stm32l476-mdk-clocking.h +++ b/boards/arm/stm32l4/stm32l476-mdk/include/stm32l476-mdk-clocking.h @@ -35,8 +35,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32L4_STM32L476_MDK_INCLUDE_STM32L476_MDK_CLOCKING_H -#define __BOARDS_ARM_STM32L4_STM32L476_MDK_INCLUDE_STM32L476_MDK_CLOCKING_H +#ifndef __BOARDS_ARM_STM32_STM32L476_MDK_INCLUDE_STM32L476_MDK_CLOCKING_H +#define __BOARDS_ARM_STM32_STM32L476_MDK_INCLUDE_STM32L476_MDK_CLOCKING_H /**************************************************************************** * Included Files @@ -59,9 +59,9 @@ * LSE - not installed */ -#define STM32L4_HSI_FREQUENCY 16000000ul -#define STM32L4_LSI_FREQUENCY 32000 -#define STM32L4_LSE_FREQUENCY 32768 +#define STM32_HSI_FREQUENCY 16000000ul +#define STM32_LSI_FREQUENCY 32000 +#define STM32_LSE_FREQUENCY 32768 #define BOARD_AHB_FREQUENCY 80000000ul @@ -79,13 +79,13 @@ #if defined(HSI_CLOCK_CONFIG) -#define STM32L4_BOARD_USEHSI 1 +#define STM32_BOARD_USEHSI 1 /* Prescaler common to all PLL inputs; will be 1 (XXX source is implicitly * as per comment above HSI) */ -#define STM32L4_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) /* 'main' PLL config; we use this to generate our system clock via the R * output. We set it up as 16 MHz / 1 * 10 / 2 = 80 MHz @@ -96,13 +96,13 @@ * may want things done this way. */ -#define STM32L4_PLLCFG_PLLN RCC_PLLCFG_PLLN(10) -#define STM32L4_PLLCFG_PLLP 0 -#undef STM32L4_PLLCFG_PLLP_ENABLED -#define STM32L4_PLLCFG_PLLQ RCC_PLLCFG_PLLQ_2 -#define STM32L4_PLLCFG_PLLQ_ENABLED -#define STM32L4_PLLCFG_PLLR RCC_PLLCFG_PLLR_2 -#define STM32L4_PLLCFG_PLLR_ENABLED +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(10) +#define STM32_PLLCFG_PLLP 0 +#undef STM32_PLLCFG_PLLP_ENABLED +#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ_2 +#define STM32_PLLCFG_PLLQ_ENABLED +#define STM32_PLLCFG_PLLR RCC_PLLCFG_PLLR_2 +#define STM32_PLLCFG_PLLR_ENABLED /* 'SAIPLL1' is used to generate the 48 MHz clock, since we can't * do that with the main PLL's N value. We set N = 13, and enable @@ -116,65 +116,65 @@ * that is selected via a #define here, like all these other params. */ -#define STM32L4_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(12) -#define STM32L4_PLLSAI1CFG_PLLP 0 -#undef STM32L4_PLLSAI1CFG_PLLP_ENABLED -#define STM32L4_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_4 -#define STM32L4_PLLSAI1CFG_PLLQ_ENABLED -#define STM32L4_PLLSAI1CFG_PLLR 0 -#undef STM32L4_PLLSAI1CFG_PLLR_ENABLED +#define STM32_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(12) +#define STM32_PLLSAI1CFG_PLLP 0 +#undef STM32_PLLSAI1CFG_PLLP_ENABLED +#define STM32_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_4 +#define STM32_PLLSAI1CFG_PLLQ_ENABLED +#define STM32_PLLSAI1CFG_PLLR 0 +#undef STM32_PLLSAI1CFG_PLLR_ENABLED /* 'SAIPLL2' is not used in this application */ -#define STM32L4_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) -#define STM32L4_PLLSAI2CFG_PLLP 0 -#undef STM32L4_PLLSAI2CFG_PLLP_ENABLED -#define STM32L4_PLLSAI2CFG_PLLR 0 -#undef STM32L4_PLLSAI2CFG_PLLR_ENABLED +#define STM32_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) +#define STM32_PLLSAI2CFG_PLLP 0 +#undef STM32_PLLSAI2CFG_PLLP_ENABLED +#define STM32_PLLSAI2CFG_PLLR 0 +#undef STM32_PLLSAI2CFG_PLLR_ENABLED -#define STM32L4_SYSCLK_FREQUENCY 80000000ul +#define STM32_SYSCLK_FREQUENCY 80000000ul /* CLK48 will come from PLLSAI1 (implicitly Q) */ -#define STM32L4_USE_CLK48 1 -#define STM32L4_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 +#define STM32_USE_CLK48 1 +#define STM32_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 /* Enable the LSE oscillator, used automatically trim the MSI, and for RTC */ -#define STM32L4_USE_LSE 1 +#define STM32_USE_LSE 1 /* AHB clock (HCLK) is SYSCLK (80MHz) */ -#define STM32L4_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ -#define STM32L4_HCLK_FREQUENCY STM32L4_SYSCLK_FREQUENCY +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY /* APB1 clock (PCLK1) is HCLK/1 (80MHz) */ -#define STM32L4_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ -#define STM32L4_PCLK1_FREQUENCY (STM32L4_HCLK_FREQUENCY/1) +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/1) /* Timers driven from APB1 will be twice PCLK1 */ /* REVISIT : this can be configured */ -#define STM32L4_APB1_TIM2_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM3_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM4_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM5_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM6_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM7_CLKIN (2*STM32L4_PCLK1_FREQUENCY) +#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) /* APB2 clock (PCLK2) is HCLK (80MHz) */ -#define STM32L4_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ -#define STM32L4_PCLK2_FREQUENCY (STM32L4_HCLK_FREQUENCY/1) +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ +#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/1) /* Timers driven from APB2 will be twice PCLK2 */ /* REVISIT : this can be configured */ -#define STM32L4_APB2_TIM1_CLKIN (2*STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM8_CLKIN (2*STM32L4_PCLK2_FREQUENCY) +#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) /* Timer Frequencies, if APBx is set to 1, frequency is same to APBx * otherwise frequency is 2xAPBx. @@ -185,76 +185,76 @@ /* Use the MSI; frequ = 4 MHz; autotrim from LSE */ -#define STM32L4_BOARD_USEMSI 1 -#define STM32L4_BOARD_MSIRANGE RCC_CR_MSIRANGE_4M +#define STM32_BOARD_USEMSI 1 +#define STM32_BOARD_MSIRANGE RCC_CR_MSIRANGE_4M /* Prescaler common to all PLL inputs */ -#define STM32L4_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) /* 'main' PLL config; we use this to generate our system clock */ -#define STM32L4_PLLCFG_PLLN RCC_PLLCFG_PLLN(40) -#define STM32L4_PLLCFG_PLLP 0 -#undef STM32L4_PLLCFG_PLLP_ENABLED -#define STM32L4_PLLCFG_PLLQ 0 -#undef STM32L4_PLLCFG_PLLQ_ENABLED -#define STM32L4_PLLCFG_PLLR RCC_PLLCFG_PLLR_2 -#define STM32L4_PLLCFG_PLLR_ENABLED +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(40) +#define STM32_PLLCFG_PLLP 0 +#undef STM32_PLLCFG_PLLP_ENABLED +#define STM32_PLLCFG_PLLQ 0 +#undef STM32_PLLCFG_PLLQ_ENABLED +#define STM32_PLLCFG_PLLR RCC_PLLCFG_PLLR_2 +#define STM32_PLLCFG_PLLR_ENABLED /* 'SAIPLL1' is used to generate the 48 MHz clock */ -#define STM32L4_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(24) -#define STM32L4_PLLSAI1CFG_PLLP 0 -#undef STM32L4_PLLSAI1CFG_PLLP_ENABLED -#define STM32L4_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_2 -#define STM32L4_PLLSAI1CFG_PLLQ_ENABLED -#define STM32L4_PLLSAI1CFG_PLLR 0 -#undef STM32L4_PLLSAI1CFG_PLLR_ENABLED +#define STM32_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(24) +#define STM32_PLLSAI1CFG_PLLP 0 +#undef STM32_PLLSAI1CFG_PLLP_ENABLED +#define STM32_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_2 +#define STM32_PLLSAI1CFG_PLLQ_ENABLED +#define STM32_PLLSAI1CFG_PLLR 0 +#undef STM32_PLLSAI1CFG_PLLR_ENABLED /* 'SAIPLL2' is not used in this application */ -#define STM32L4_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) -#define STM32L4_PLLSAI2CFG_PLLP 0 -#undef STM32L4_PLLSAI2CFG_PLLP_ENABLED -#define STM32L4_PLLSAI2CFG_PLLR 0 -#undef STM32L4_PLLSAI2CFG_PLLR_ENABLED +#define STM32_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) +#define STM32_PLLSAI2CFG_PLLP 0 +#undef STM32_PLLSAI2CFG_PLLP_ENABLED +#define STM32_PLLSAI2CFG_PLLR 0 +#undef STM32_PLLSAI2CFG_PLLR_ENABLED -#define STM32L4_SYSCLK_FREQUENCY 80000000ul +#define STM32_SYSCLK_FREQUENCY 80000000ul /* Enable CLK48; get it from PLLSAI1 */ -#define STM32L4_USE_CLK48 -#define STM32L4_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 +#define STM32_USE_CLK48 +#define STM32_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 /* Disable LSE (for the RTC) */ -#undef STM32L4_USE_LSE +#undef STM32_USE_LSE /* Configure the HCLK divisor (for the AHB bus, core, memory, and DMA */ -#define STM32L4_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ -#define STM32L4_HCLK_FREQUENCY STM32L4_SYSCLK_FREQUENCY +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY /* Configure the APB1 prescaler */ -#define STM32L4_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ -#define STM32L4_PCLK1_FREQUENCY (STM32L4_HCLK_FREQUENCY/1) +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/1) -#define STM32L4_APB1_TIM2_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM3_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM4_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM5_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM6_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM7_CLKIN (2*STM32L4_PCLK1_FREQUENCY) +#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) /* Configure the APB2 prescaler */ -#define STM32L4_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ -#define STM32L4_PCLK2_FREQUENCY (STM32L4_HCLK_FREQUENCY/1) +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ +#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/1) -#define STM32L4_APB2_TIM1_CLKIN (2*STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM8_CLKIN (2*STM32L4_PCLK2_FREQUENCY) +#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) #endif @@ -263,19 +263,19 @@ * Note: TIM1,8,15,16,17 are on APB2, others on APB1 */ -#define BOARD_TIM1_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM2_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2) -#define BOARD_TIM3_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2) -#define BOARD_TIM4_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2) -#define BOARD_TIM5_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2) -#define BOARD_TIM6_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2) -#define BOARD_TIM7_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2) -#define BOARD_TIM8_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM15_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM16_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM17_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_LPTIM1_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2) -#define BOARD_LPTIM2_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2) +#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM2_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM3_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM4_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM5_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM6_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM7_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM15_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM16_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM17_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_LPTIM1_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_LPTIM2_FREQUENCY (STM32_HCLK_FREQUENCY / 2) /**************************************************************************** * Public Data @@ -302,4 +302,4 @@ extern "C" #endif #endif /* __ASSEMBLY__ */ -#endif /* __BOARDS_ARM_STM32L4_STM32L476_MDK_INCLUDE_STM32L476_MDK_CLOCKING_H */ +#endif /* __BOARDS_ARM_STM32_STM32L476_MDK_INCLUDE_STM32L476_MDK_CLOCKING_H */ diff --git a/boards/arm/stm32l4/stm32l476-mdk/src/CMakeLists.txt b/boards/arm/stm32l4/stm32l476-mdk/src/CMakeLists.txt index f47dc052ac4dc..5390a86c1210e 100644 --- a/boards/arm/stm32l4/stm32l476-mdk/src/CMakeLists.txt +++ b/boards/arm/stm32l4/stm32l476-mdk/src/CMakeLists.txt @@ -22,7 +22,7 @@ set(SRCS stm32_boot.c stm32_spi.c stm32_userleds.c) -if(CONFIG_ARCH_BOARD_STM32L4_CUSTOM_CLOCKCONFIG) +if(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) list(APPEND SRCS stm32_clockconfig.c) endif() diff --git a/boards/arm/stm32l4/stm32l476-mdk/src/Make.defs b/boards/arm/stm32l4/stm32l476-mdk/src/Make.defs new file mode 100644 index 0000000000000..4c2a02f3f1bcf --- /dev/null +++ b/boards/arm/stm32l4/stm32l476-mdk/src/Make.defs @@ -0,0 +1,41 @@ +############################################################################ +# boards/arm/stm32l4/stm32l476-mdk/src/Makefile +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +CSRCS = stm32_boot.c stm32_spi.c stm32_userleds.c + +ifeq ($(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG),y) +CSRCS += stm32_clockconfig.c +endif + +ifeq ($(CONFIG_ARCH_LEDS),y) +CSRCS += stm32_autoleds.c +endif + +ifeq ($(CONFIG_ARCH_BUTTONS),y) +CSRCS += stm32_buttons.c +endif + +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32l4/stm32l476-mdk/src/Makefile b/boards/arm/stm32l4/stm32l476-mdk/src/Makefile deleted file mode 100644 index 0aba6ed8c09d0..0000000000000 --- a/boards/arm/stm32l4/stm32l476-mdk/src/Makefile +++ /dev/null @@ -1,39 +0,0 @@ -############################################################################ -# boards/arm/stm32l4/stm32l476-mdk/src/Makefile -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/Make.defs - -CSRCS = stm32_boot.c stm32_spi.c stm32_userleds.c - -ifeq ($(CONFIG_ARCH_BOARD_STM32L4_CUSTOM_CLOCKCONFIG),y) -CSRCS += stm32_clockconfig.c -endif - -ifeq ($(CONFIG_ARCH_LEDS),y) -CSRCS += stm32_autoleds.c -endif - -ifeq ($(CONFIG_ARCH_BUTTONS),y) -CSRCS += stm32_buttons.c -endif - -include $(TOPDIR)/boards/Board.mk diff --git a/boards/arm/stm32l4/stm32l476-mdk/src/stm32_autoleds.c b/boards/arm/stm32l4/stm32l476-mdk/src/stm32_autoleds.c index d4585229ecf6b..990571be0068f 100644 --- a/boards/arm/stm32l4/stm32l476-mdk/src/stm32_autoleds.c +++ b/boards/arm/stm32l4/stm32l476-mdk/src/stm32_autoleds.c @@ -89,9 +89,9 @@ void board_autoled_initialize(void) { /* Configure LED GPIOs for output */ - stm32l4_configgpio(GPIO_LED_RED); - stm32l4_configgpio(GPIO_LED_GREEN); - stm32l4_configgpio(GPIO_LED_WHITE); + stm32_configgpio(GPIO_LED_RED); + stm32_configgpio(GPIO_LED_GREEN); + stm32_configgpio(GPIO_LED_WHITE); } /**************************************************************************** @@ -102,7 +102,7 @@ void board_autoled_on(int led) { if (led == 1 || led == 3) { - stm32l4_gpiowrite(GPIO_LED_WHITE, false); /* Low illuminates */ + stm32_gpiowrite(GPIO_LED_WHITE, false); /* Low illuminates */ } } @@ -114,7 +114,7 @@ void board_autoled_off(int led) { if (led == 3) { - stm32l4_gpiowrite(GPIO_LED_WHITE, true); /* High extinguishes */ + stm32_gpiowrite(GPIO_LED_WHITE, true); /* High extinguishes */ } } diff --git a/boards/arm/stm32l4/stm32l476-mdk/src/stm32_boot.c b/boards/arm/stm32l4/stm32l476-mdk/src/stm32_boot.c index ab4b6b3ddc43a..98d872dd6dd6b 100644 --- a/boards/arm/stm32l4/stm32l476-mdk/src/stm32_boot.c +++ b/boards/arm/stm32l4/stm32l476-mdk/src/stm32_boot.c @@ -43,8 +43,8 @@ #include #include "arm_internal.h" -#include "stm32l4.h" -#include "stm32l4_uid.h" +#include "stm32.h" +#include "stm32_uid.h" #include "stm32l476-mdk.h" /* Conditional logic in stm32l476-mdk.h will determine if certain features @@ -66,7 +66,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_board_initialize + * Name: stm32_board_initialize * * Description: * All STM32L4 architectures must provide the following entry point. This @@ -76,7 +76,7 @@ * ****************************************************************************/ -void stm32l4_board_initialize(void) +void stm32_board_initialize(void) { #ifdef CONFIG_ARCH_LEDS /* Configure on-board LEDs if LED support has been selected. */ @@ -90,7 +90,7 @@ void stm32l4_board_initialize(void) * stm32_spiinitialize() has been brought into the link. */ - stm32l4_spiinitialize(); + stm32_spiinitialize(); #endif } @@ -133,7 +133,7 @@ void board_late_initialize(void) #ifdef HAVE_RTC_DRIVER /* Instantiate the STM32 lower-half RTC driver */ - rtclower = stm32l4_rtc_lowerhalf(); + rtclower = stm32_rtc_lowerhalf(); if (!rtclower) { syslog(LOG_ERR, @@ -181,7 +181,7 @@ int board_uniqueid(uint8_t *uniqueid) return -EINVAL; } - stm32l4_get_uniqueid(uniqueid); + stm32_get_uniqueid(uniqueid); return OK; } #endif diff --git a/boards/arm/stm32l4/stm32l476-mdk/src/stm32_buttons.c b/boards/arm/stm32l4/stm32l476-mdk/src/stm32_buttons.c index a39653988ec36..e8aa789c2fc42 100644 --- a/boards/arm/stm32l4/stm32l476-mdk/src/stm32_buttons.c +++ b/boards/arm/stm32l4/stm32l476-mdk/src/stm32_buttons.c @@ -76,7 +76,7 @@ uint32_t board_button_initialize(void) for (i = 0; i < NUM_BUTTONS; i++) { - stm32l4_configgpio(g_buttons[i]); + stm32_configgpio(g_buttons[i]); } return NUM_BUTTONS; @@ -97,7 +97,7 @@ uint32_t board_buttons(void) { /* A LOW value means that the key is pressed. */ - bool released = stm32l4_gpioread(g_buttons[i]); + bool released = stm32_gpioread(g_buttons[i]); /* Accumulate the set of depressed (not released) keys */ @@ -139,7 +139,7 @@ int board_button_irq(int id, xcpt_t irqhandler, void *arg) if (id >= MIN_IRQBUTTON && id <= MAX_IRQBUTTON) { - ret = stm32l4_gpiosetevent(g_buttons[id], true, true, true, + ret = stm32_gpiosetevent(g_buttons[id], true, true, true, irqhandler, arg); } diff --git a/boards/arm/stm32l4/stm32l476-mdk/src/stm32_clockconfig.c b/boards/arm/stm32l4/stm32l476-mdk/src/stm32_clockconfig.c index 328eb3c834a47..e8ee098c11195 100644 --- a/boards/arm/stm32l4/stm32l476-mdk/src/stm32_clockconfig.c +++ b/boards/arm/stm32l4/stm32l476-mdk/src/stm32_clockconfig.c @@ -52,122 +52,122 @@ * ****************************************************************************/ -#if defined(CONFIG_ARCH_BOARD_STM32L4_CUSTOM_CLOCKCONFIG) -void stm32l4_board_clockconfig(void) +#if defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) +void stm32_board_clockconfig(void) { uint32_t regval; /* Enable Internal High-Speed Clock (HSI) */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_HSION; /* Enable HSI */ - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Wait until the HSI is ready */ - while ((getreg32(STM32L4_RCC_CR) & RCC_CR_HSIRDY) == 0) + while ((getreg32(STM32_RCC_CR) & RCC_CR_HSIRDY) == 0) { } /* Set the HCLK source/divider */ - regval = getreg32(STM32L4_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_HPRE_MASK; - regval |= STM32L4_RCC_CFGR_HPRE; - putreg32(regval, STM32L4_RCC_CFGR); + regval |= STM32_RCC_CFGR_HPRE; + putreg32(regval, STM32_RCC_CFGR); /* Set the PCLK2 divider */ - regval = getreg32(STM32L4_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_PPRE2_MASK; - regval |= STM32L4_RCC_CFGR_PPRE2; - putreg32(regval, STM32L4_RCC_CFGR); + regval |= STM32_RCC_CFGR_PPRE2; + putreg32(regval, STM32_RCC_CFGR); /* Set the PCLK1 divider */ - regval = getreg32(STM32L4_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_PPRE1_MASK; - regval |= STM32L4_RCC_CFGR_PPRE1; - putreg32(regval, STM32L4_RCC_CFGR); + regval |= STM32_RCC_CFGR_PPRE1; + putreg32(regval, STM32_RCC_CFGR); /* Set the PLL source and main divider */ - regval = getreg32(STM32L4_RCC_PLLCFG); + regval = getreg32(STM32_RCC_PLLCFG); /* Configure Main PLL */ /* Set the PLL dividers and multipliers to configure the main PLL */ - regval = (STM32L4_PLLCFG_PLLM | STM32L4_PLLCFG_PLLN | STM32L4_PLLCFG_PLLP - | STM32L4_PLLCFG_PLLQ | STM32L4_PLLCFG_PLLR); + regval = (STM32_PLLCFG_PLLM | STM32_PLLCFG_PLLN | STM32_PLLCFG_PLLP + | STM32_PLLCFG_PLLQ | STM32_PLLCFG_PLLR); regval |= RCC_PLLCFG_PLLQEN; regval |= RCC_PLLCFG_PLLREN; /* XXX The choice of clock source to PLL (all three) is independent - * of the sys clock source choice, review the STM32L4_BOARD_USEHSI + * of the sys clock source choice, review the STM32_BOARD_USEHSI * name; probably split it into two, one for PLL source and one * for sys clock source. */ regval |= RCC_PLLCFG_PLLSRC_HSI; - putreg32(regval, STM32L4_RCC_PLLCFG); + putreg32(regval, STM32_RCC_PLLCFG); /* Enable the main PLL */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_PLLON; - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Wait until the PLL is ready */ - while ((getreg32(STM32L4_RCC_CR) & RCC_CR_PLLRDY) == 0) + while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLRDY) == 0) { } /* Configure SAI1 PLL */ - regval = getreg32(STM32L4_RCC_PLLSAI1CFG); + regval = getreg32(STM32_RCC_PLLSAI1CFG); /* Set the PLL dividers and multipliers to configure the SAI1 PLL */ - regval = (STM32L4_PLLSAI1CFG_PLLN | STM32L4_PLLSAI1CFG_PLLP | - STM32L4_PLLSAI1CFG_PLLQ | STM32L4_PLLSAI1CFG_PLLR); + regval = (STM32_PLLSAI1CFG_PLLN | STM32_PLLSAI1CFG_PLLP | + STM32_PLLSAI1CFG_PLLQ | STM32_PLLSAI1CFG_PLLR); regval |= RCC_PLLSAI1CFG_PLLQEN; - putreg32(regval, STM32L4_RCC_PLLSAI1CFG); + putreg32(regval, STM32_RCC_PLLSAI1CFG); /* Enable the SAI1 PLL */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_PLLSAI1ON; - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Wait until the PLL is ready */ - while ((getreg32(STM32L4_RCC_CR) & RCC_CR_PLLSAI1RDY) == 0) + while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLSAI1RDY) == 0) { } /* Configure SAI2 PLL */ - regval = getreg32(STM32L4_RCC_PLLSAI2CFG); + regval = getreg32(STM32_RCC_PLLSAI2CFG); /* Enable the SAI2 PLL */ /* Set the PLL dividers and multipliers to configure the SAI2 PLL */ - regval = (STM32L4_PLLSAI2CFG_PLLN | STM32L4_PLLSAI2CFG_PLLP | - STM32L4_PLLSAI2CFG_PLLR); - putreg32(regval, STM32L4_RCC_PLLSAI2CFG); + regval = (STM32_PLLSAI2CFG_PLLN | STM32_PLLSAI2CFG_PLLP | + STM32_PLLSAI2CFG_PLLR); + putreg32(regval, STM32_RCC_PLLSAI2CFG); /* Enable the SAI1 PLL */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_PLLSAI2ON; - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Wait until the PLL is ready */ - while ((getreg32(STM32L4_RCC_CR) & RCC_CR_PLLSAI2RDY) == 0) + while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLSAI2RDY) == 0) { } @@ -175,36 +175,36 @@ void stm32l4_board_clockconfig(void) * and 5 wait states */ -#ifdef CONFIG_STM32L4_FLASH_PREFETCH +#ifdef CONFIG_STM32_FLASH_PREFETCH regval = (FLASH_ACR_LATENCY_4 | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_PRFTEN); #else regval = (FLASH_ACR_LATENCY_4 | FLASH_ACR_ICEN | FLASH_ACR_DCEN); #endif - putreg32(regval, STM32L4_FLASH_ACR); + putreg32(regval, STM32_FLASH_ACR); /* Select the main PLL as system clock source */ - regval = getreg32(STM32L4_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_SW_MASK; regval |= RCC_CFGR_SW_PLL; - putreg32(regval, STM32L4_RCC_CFGR); + putreg32(regval, STM32_RCC_CFGR); /* Wait until the PLL source is used as the system clock source */ - while ((getreg32(STM32L4_RCC_CFGR) & RCC_CFGR_SWS_MASK) != + while ((getreg32(STM32_RCC_CFGR) & RCC_CFGR_SWS_MASK) != RCC_CFGR_SWS_PLL) { } -#if defined(CONFIG_STM32L4_IWDG) || defined(CONFIG_STM32L4_RTC_LSICLOCK) +#if defined(CONFIG_STM32_IWDG) || defined(CONFIG_STM32_RTC_LSICLOCK) /* Low speed internal clock source LSI */ - stm32l4_rcc_enablelsi(); + stm32_rcc_enablelsi(); #endif -#if defined(STM32L4_USE_LSE) +#if defined(STM32_USE_LSE) /* Low speed external clock source LSE * @@ -212,8 +212,8 @@ void stm32l4_board_clockconfig(void) * be enabled: if the MCO1 pin selects LSE as source. */ - stm32l4_pwr_enableclk(true); - stm32l4_rcc_enablelse(); + stm32_pwr_enableclk(true); + stm32_rcc_enablelse(); #endif } #endif diff --git a/boards/arm/stm32l4/stm32l476-mdk/src/stm32_spi.c b/boards/arm/stm32l4/stm32l476-mdk/src/stm32_spi.c index 766cd2f1646be..74f0778215770 100644 --- a/boards/arm/stm32l4/stm32l476-mdk/src/stm32_spi.c +++ b/boards/arm/stm32l4/stm32l476-mdk/src/stm32_spi.c @@ -35,7 +35,7 @@ #include #include "chip.h" -#include +#include #include "stm32l476-mdk.h" diff --git a/boards/arm/stm32l4/stm32l476-mdk/src/stm32_userleds.c b/boards/arm/stm32l4/stm32l476-mdk/src/stm32_userleds.c index 19b645de1a0ff..db4d7ded75125 100644 --- a/boards/arm/stm32l4/stm32l476-mdk/src/stm32_userleds.c +++ b/boards/arm/stm32l4/stm32l476-mdk/src/stm32_userleds.c @@ -48,9 +48,9 @@ uint32_t board_userled_initialize(void) #ifndef CONFIG_ARCH_LEDS /* Configure LED GPIOs for output */ - stm32l4_configgpio(GPIO_LED_RED); - stm32l4_configgpio(GPIO_LED_GREEN); - stm32l4_configgpio(GPIO_LED_WHITE); + stm32_configgpio(GPIO_LED_RED); + stm32_configgpio(GPIO_LED_GREEN); + stm32_configgpio(GPIO_LED_WHITE); #endif return BOARD_NLEDS; } @@ -63,16 +63,16 @@ void board_userled(int led, bool ledon) { if (led == BOARD_RED_LED) { - stm32l4_gpiowrite(GPIO_LED_RED, !ledon); /* Low illuminates */ + stm32_gpiowrite(GPIO_LED_RED, !ledon); /* Low illuminates */ } else if (led == BOARD_GREEN_LED) { - stm32l4_gpiowrite(GPIO_LED_GREEN, !ledon); /* Low illuminates */ + stm32_gpiowrite(GPIO_LED_GREEN, !ledon); /* Low illuminates */ } #ifndef CONFIG_ARCH_LEDS else if (led == BOARD_WHITE_LED) { - stm32l4_gpiowrite(GPIO_LED_WHITE, !ledon); /* Low illuminates */ + stm32_gpiowrite(GPIO_LED_WHITE, !ledon); /* Low illuminates */ } #endif } @@ -85,9 +85,9 @@ void board_userled_all(uint32_t ledset) { /* Low illuminates */ - stm32l4_gpiowrite(GPIO_LED_RED, (ledset & BOARD_RED_LED_BIT) == 0); - stm32l4_gpiowrite(GPIO_LED_GREEN, (ledset & BOARD_GREEN_LED_BIT) == 0); + stm32_gpiowrite(GPIO_LED_RED, (ledset & BOARD_RED_LED_BIT) == 0); + stm32_gpiowrite(GPIO_LED_GREEN, (ledset & BOARD_GREEN_LED_BIT) == 0); #ifndef CONFIG_ARCH_LEDS - stm32l4_gpiowrite(GPIO_LED_WHITE, (ledset & BOARD_WHITE_LED_BIT) == 0); + stm32_gpiowrite(GPIO_LED_WHITE, (ledset & BOARD_WHITE_LED_BIT) == 0); #endif } diff --git a/boards/arm/stm32l4/stm32l476-mdk/src/stm32l476-mdk.h b/boards/arm/stm32l4/stm32l476-mdk/src/stm32l476-mdk.h index 31aae781ccc8c..c9995d42afc39 100644 --- a/boards/arm/stm32l4/stm32l476-mdk/src/stm32l476-mdk.h +++ b/boards/arm/stm32l4/stm32l476-mdk/src/stm32l476-mdk.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32L4_STM32L476_MDK_SRC_STM32L476_MDK_H -#define __BOARDS_ARM_STM32L4_STM32L476_MDK_SRC_STM32L476_MDK_H +#ifndef __BOARDS_ARM_STM32_STM32L476_MDK_SRC_STM32L476_MDK_H +#define __BOARDS_ARM_STM32_STM32L476_MDK_SRC_STM32L476_MDK_H /**************************************************************************** * Included Files @@ -154,4 +154,4 @@ int stm32_bringup(void); void stm32_spiinitialize(void); -#endif /* __BOARDS_ARM_STM32L4_STM32L476_MDK_SRC_STM32L476_MDK_H */ +#endif /* __BOARDS_ARM_STM32_STM32L476_MDK_SRC_STM32L476_MDK_H */ diff --git a/boards/arm/stm32l4/stm32l476vg-disco/configs/knsh/defconfig b/boards/arm/stm32l4/stm32l476vg-disco/configs/knsh/defconfig index 9ee1fcccd70b7..8e0327c72286a 100644 --- a/boards/arm/stm32l4/stm32l476vg-disco/configs/knsh/defconfig +++ b/boards/arm/stm32l4/stm32l476vg-disco/configs/knsh/defconfig @@ -14,6 +14,7 @@ CONFIG_ARCH_BOARD="stm32l476vg-disco" CONFIG_ARCH_BOARD_STM32L476VG_DISCO=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32l4" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32L476RG=y CONFIG_ARCH_CHIP_STM32L4=y CONFIG_ARCH_INTERRUPTSTACK=2048 @@ -52,15 +53,15 @@ CONFIG_RTC_IOCTL=y CONFIG_RTC_NALARMS=2 CONFIG_SCHED_WAITPID=y CONFIG_SPI=y -CONFIG_STM32L4_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32L4_DMA1=y -CONFIG_STM32L4_DMA2=y -CONFIG_STM32L4_PWR=y -CONFIG_STM32L4_QSPI=y -CONFIG_STM32L4_RNG=y -CONFIG_STM32L4_RTC=y -CONFIG_STM32L4_SAI1PLL=y -CONFIG_STM32L4_USART2=y +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_DMA1=y +CONFIG_STM32_DMA2=y +CONFIG_STM32_PWR=y +CONFIG_STM32_QSPI=y +CONFIG_STM32_RNG=y +CONFIG_STM32_RTC=y +CONFIG_STM32_SAI1PLL=y +CONFIG_STM32_USART2=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32l4/stm32l476vg-disco/configs/nsh/defconfig b/boards/arm/stm32l4/stm32l476vg-disco/configs/nsh/defconfig index 9bab580b6f0a9..8f07bd33dcf5d 100644 --- a/boards/arm/stm32l4/stm32l476vg-disco/configs/nsh/defconfig +++ b/boards/arm/stm32l4/stm32l476vg-disco/configs/nsh/defconfig @@ -13,6 +13,7 @@ CONFIG_ARCH_BOARD="stm32l476vg-disco" CONFIG_ARCH_BOARD_STM32L476VG_DISCO=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32l4" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32L476RG=y CONFIG_ARCH_CHIP_STM32L4=y CONFIG_ARCH_INTERRUPTSTACK=2048 @@ -55,15 +56,15 @@ CONFIG_RTC_IOCTL=y CONFIG_RTC_NALARMS=2 CONFIG_SCHED_WAITPID=y CONFIG_SPI=y -CONFIG_STM32L4_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32L4_DMA1=y -CONFIG_STM32L4_DMA2=y -CONFIG_STM32L4_PWR=y -CONFIG_STM32L4_QSPI=y -CONFIG_STM32L4_RNG=y -CONFIG_STM32L4_RTC=y -CONFIG_STM32L4_SAI1PLL=y -CONFIG_STM32L4_USART2=y +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_DMA1=y +CONFIG_STM32_DMA2=y +CONFIG_STM32_PWR=y +CONFIG_STM32_QSPI=y +CONFIG_STM32_RNG=y +CONFIG_STM32_RTC=y +CONFIG_STM32_SAI1PLL=y +CONFIG_STM32_USART2=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32l4/stm32l476vg-disco/include/board.h b/boards/arm/stm32l4/stm32l476vg-disco/include/board.h index 1923d5b3055b8..afb63e27460d7 100644 --- a/boards/arm/stm32l4/stm32l476vg-disco/include/board.h +++ b/boards/arm/stm32l4/stm32l476vg-disco/include/board.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32L4_STM32L476VG_DISCO_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32L4_STM32L476VG_DISCO_INCLUDE_BOARD_H +#ifndef __BOARDS_ARM_STM32_STM32L476VG_DISCO_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32_STM32L476VG_DISCO_INCLUDE_BOARD_H /**************************************************************************** * Included Files @@ -281,7 +281,7 @@ extern "C" ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_board_initialize + * Name: stm32_board_initialize * * Description: * All STM32L4 architectures must provide the following entry point. @@ -291,7 +291,7 @@ extern "C" * ****************************************************************************/ -void stm32l4_board_initialize(void); +void stm32_board_initialize(void); #undef EXTERN #if defined(__cplusplus) @@ -299,4 +299,4 @@ void stm32l4_board_initialize(void); #endif #endif /* __ASSEMBLY__ */ -#endif /* __BOARDS_ARM_STM32L4_STM32L476VG_DISCO_INCLUDE_BOARD_H */ +#endif /* __BOARDS_ARM_STM32_STM32L476VG_DISCO_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32l4/stm32l476vg-disco/include/boardctl.h b/boards/arm/stm32l4/stm32l476vg-disco/include/boardctl.h index fcc418943a8c5..63954f61754eb 100644 --- a/boards/arm/stm32l4/stm32l476vg-disco/include/boardctl.h +++ b/boards/arm/stm32l4/stm32l476vg-disco/include/boardctl.h @@ -34,8 +34,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32L4_STM32L476VG_DISCO_INCLUDE_BOARDCTL_H -#define __BOARDS_ARM_STM32L4_STM32L476VG_DISCO_INCLUDE_BOARDCTL_H +#ifndef __BOARDS_ARM_STM32_STM32L476VG_DISCO_INCLUDE_BOARDCTL_H +#define __BOARDS_ARM_STM32_STM32L476VG_DISCO_INCLUDE_BOARDCTL_H /**************************************************************************** * Included Files @@ -50,4 +50,4 @@ #define BIOC_ENTER_MEMMAP BOARDIOC_USER+1 #define BIOC_EXIT_MEMMAP BOARDIOC_USER+2 -#endif /* __BOARDS_ARM_STM32L4_STM32L476VG_DISCO_INCLUDE_BOARDCTL_H */ +#endif /* __BOARDS_ARM_STM32_STM32L476VG_DISCO_INCLUDE_BOARDCTL_H */ diff --git a/boards/arm/stm32l4/stm32l476vg-disco/include/stm32l476vg-disco-clocking.h b/boards/arm/stm32l4/stm32l476vg-disco/include/stm32l476vg-disco-clocking.h index d336955276ea1..95845e26c5e2a 100644 --- a/boards/arm/stm32l4/stm32l476vg-disco/include/stm32l476vg-disco-clocking.h +++ b/boards/arm/stm32l4/stm32l476vg-disco/include/stm32l476vg-disco-clocking.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32L4_STM32L476VG_DISCO_INCLUDE_STM32L476VG_DISCO_CLOCKING_H -#define __BOARDS_ARM_STM32L4_STM32L476VG_DISCO_INCLUDE_STM32L476VG_DISCO_CLOCKING_H +#ifndef __BOARDS_ARM_STM32_STM32L476VG_DISCO_INCLUDE_STM32L476VG_DISCO_CLOCKING_H +#define __BOARDS_ARM_STM32_STM32L476VG_DISCO_INCLUDE_STM32L476VG_DISCO_CLOCKING_H /**************************************************************************** * Included Files @@ -51,9 +51,9 @@ * LSE - 32.768 kHz installed */ -#define STM32L4_HSI_FREQUENCY 16000000ul -#define STM32L4_LSI_FREQUENCY 32000 -#define STM32L4_LSE_FREQUENCY 32768 +#define STM32_HSI_FREQUENCY 16000000ul +#define STM32_LSI_FREQUENCY 32000 +#define STM32_LSE_FREQUENCY 32768 #define BOARD_AHB_FREQUENCY 80000000ul @@ -75,13 +75,13 @@ #if defined(HSI_CLOCK_CONFIG) -#define STM32L4_BOARD_USEHSI 1 +#define STM32_BOARD_USEHSI 1 /* Prescaler common to all PLL inputs; will be 1 (XXX source is implicitly * as per comment above HSI) */ -#define STM32L4_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) /* 'main' PLL config; we use this to generate our system clock via the R * output. We set it up as 16 MHz / 1 * 10 / 2 = 80 MHz @@ -91,13 +91,13 @@ * may want things done this way. */ -#define STM32L4_PLLCFG_PLLN RCC_PLLCFG_PLLN(10) -#define STM32L4_PLLCFG_PLLP 0 -#undef STM32L4_PLLCFG_PLLP_ENABLED -#define STM32L4_PLLCFG_PLLQ RCC_PLLCFG_PLLQ_2 -#define STM32L4_PLLCFG_PLLQ_ENABLED -#define STM32L4_PLLCFG_PLLR RCC_PLLCFG_PLLR_2 -#define STM32L4_PLLCFG_PLLR_ENABLED +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(10) +#define STM32_PLLCFG_PLLP 0 +#undef STM32_PLLCFG_PLLP_ENABLED +#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ_2 +#define STM32_PLLCFG_PLLQ_ENABLED +#define STM32_PLLCFG_PLLR RCC_PLLCFG_PLLR_2 +#define STM32_PLLCFG_PLLR_ENABLED /* 'SAIPLL1' is used to generate the 48 MHz clock, since we can't * do that with the main PLL's N value. We set N = 13, and enable @@ -111,42 +111,42 @@ * that is selected via a #define here, like all these other params. */ -#define STM32L4_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(12) -#define STM32L4_PLLSAI1CFG_PLLP 0 -#undef STM32L4_PLLSAI1CFG_PLLP_ENABLED -#define STM32L4_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_4 -#define STM32L4_PLLSAI1CFG_PLLQ_ENABLED -#define STM32L4_PLLSAI1CFG_PLLR 0 -#undef STM32L4_PLLSAI1CFG_PLLR_ENABLED +#define STM32_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(12) +#define STM32_PLLSAI1CFG_PLLP 0 +#undef STM32_PLLSAI1CFG_PLLP_ENABLED +#define STM32_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_4 +#define STM32_PLLSAI1CFG_PLLQ_ENABLED +#define STM32_PLLSAI1CFG_PLLR 0 +#undef STM32_PLLSAI1CFG_PLLR_ENABLED /* 'SAIPLL2' is not used in this application */ -#define STM32L4_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) -#define STM32L4_PLLSAI2CFG_PLLP 0 -#undef STM32L4_PLLSAI2CFG_PLLP_ENABLED -#define STM32L4_PLLSAI2CFG_PLLR 0 -#undef STM32L4_PLLSAI2CFG_PLLR_ENABLED +#define STM32_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) +#define STM32_PLLSAI2CFG_PLLP 0 +#undef STM32_PLLSAI2CFG_PLLP_ENABLED +#define STM32_PLLSAI2CFG_PLLR 0 +#undef STM32_PLLSAI2CFG_PLLR_ENABLED -#define STM32L4_SYSCLK_FREQUENCY 80000000ul +#define STM32_SYSCLK_FREQUENCY 80000000ul /* CLK48 will come from PLLSAI1 (implicitly Q) */ -#define STM32L4_USE_CLK48 1 -#define STM32L4_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 +#define STM32_USE_CLK48 1 +#define STM32_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 /* Enable the LSE oscillator, used automatically trim the MSI, and for RTC */ -#define STM32L4_USE_LSE 1 +#define STM32_USE_LSE 1 /* AHB clock (HCLK) is SYSCLK (80MHz) */ -#define STM32L4_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ -#define STM32L4_HCLK_FREQUENCY STM32L4_SYSCLK_FREQUENCY +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY /* APB1 clock (PCLK1) is HCLK/1 (80MHz) */ -#define STM32L4_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ -#define STM32L4_PCLK1_FREQUENCY (STM32L4_HCLK_FREQUENCY / 1) +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY / 1) /* The timer clock frequencies are automatically defined by hardware. * If the APB prescaler equals 1, the timer clock frequencies are set to the @@ -155,17 +155,17 @@ * REVISIT : this can be configured */ -#define STM32L4_APB1_TIM2_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM3_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM4_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM5_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM6_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM7_CLKIN (STM32L4_PCLK1_FREQUENCY) +#define STM32_APB1_TIM2_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM5_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (STM32_PCLK1_FREQUENCY) /* APB2 clock (PCLK2) is HCLK (80MHz) */ -#define STM32L4_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ -#define STM32L4_PCLK2_FREQUENCY (STM32L4_HCLK_FREQUENCY / 1) +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ +#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY / 1) /* The timer clock frequencies are automatically defined by hardware. * If the APB prescaler equals 1, the timer clock frequencies are set to the @@ -174,14 +174,14 @@ * REVISIT : this can be configured */ -#define STM32L4_APB2_TIM1_CLKIN (STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM8_CLKIN (STM32L4_PCLK2_FREQUENCY) +#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) #elif defined(HSE_CLOCK_CONFIG) /* Use the HSE */ -#define STM32L4_BOARD_USEHSE 1 +#define STM32_BOARD_USEHSE 1 /* XXX sysclk mux = pllclk */ @@ -189,78 +189,78 @@ /* Prescaler common to all PLL inputs */ -#define STM32L4_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) /* 'main' PLL config; we use this to generate our system clock */ -#define STM32L4_PLLCFG_PLLN RCC_PLLCFG_PLLN(20) -#define STM32L4_PLLCFG_PLLP 0 -#undef STM32L4_PLLCFG_PLLP_ENABLED -#define STM32L4_PLLCFG_PLLQ 0 -#undef STM32L4_PLLCFG_PLLQ_ENABLED -#define STM32L4_PLLCFG_PLLR RCC_PLLCFG_PLLR_2 -#define STM32L4_PLLCFG_PLLR_ENABLED +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(20) +#define STM32_PLLCFG_PLLP 0 +#undef STM32_PLLCFG_PLLP_ENABLED +#define STM32_PLLCFG_PLLQ 0 +#undef STM32_PLLCFG_PLLQ_ENABLED +#define STM32_PLLCFG_PLLR RCC_PLLCFG_PLLR_2 +#define STM32_PLLCFG_PLLR_ENABLED /* 'SAIPLL1' is used to generate the 48 MHz clock */ -#define STM32L4_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(12) -#define STM32L4_PLLSAI1CFG_PLLP 0 -#undef STM32L4_PLLSAI1CFG_PLLP_ENABLED -#define STM32L4_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_2 -#define STM32L4_PLLSAI1CFG_PLLQ_ENABLED -#define STM32L4_PLLSAI1CFG_PLLR 0 -#undef STM32L4_PLLSAI1CFG_PLLR_ENABLED +#define STM32_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(12) +#define STM32_PLLSAI1CFG_PLLP 0 +#undef STM32_PLLSAI1CFG_PLLP_ENABLED +#define STM32_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_2 +#define STM32_PLLSAI1CFG_PLLQ_ENABLED +#define STM32_PLLSAI1CFG_PLLR 0 +#undef STM32_PLLSAI1CFG_PLLR_ENABLED /* 'SAIPLL2' is not used in this application */ -#define STM32L4_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) -#define STM32L4_PLLSAI2CFG_PLLP 0 -#undef STM32L4_PLLSAI2CFG_PLLP_ENABLED -#define STM32L4_PLLSAI2CFG_PLLR 0 -#undef STM32L4_PLLSAI2CFG_PLLR_ENABLED +#define STM32_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) +#define STM32_PLLSAI2CFG_PLLP 0 +#undef STM32_PLLSAI2CFG_PLLP_ENABLED +#define STM32_PLLSAI2CFG_PLLR 0 +#undef STM32_PLLSAI2CFG_PLLR_ENABLED -#define STM32L4_SYSCLK_FREQUENCY 80000000ul +#define STM32_SYSCLK_FREQUENCY 80000000ul /* Enable CLK48; get it from PLLSAI1 */ -#define STM32L4_USE_CLK48 -#define STM32L4_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 +#define STM32_USE_CLK48 +#define STM32_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 /* Enable LSE (for the RTC) */ -#define STM32L4_USE_LSE 1 +#define STM32_USE_LSE 1 /* Configure the HCLK divisor (for the AHB bus, core, memory, and DMA */ -#define STM32L4_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ -#define STM32L4_HCLK_FREQUENCY STM32L4_SYSCLK_FREQUENCY +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY /* Configure the APB1 prescaler */ -#define STM32L4_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ -#define STM32L4_PCLK1_FREQUENCY (STM32L4_HCLK_FREQUENCY / 1) +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY / 1) -#define STM32L4_APB1_TIM2_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM3_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM4_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM5_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM6_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM7_CLKIN (STM32L4_PCLK1_FREQUENCY) +#define STM32_APB1_TIM2_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM5_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (STM32_PCLK1_FREQUENCY) /* Configure the APB2 prescaler */ -#define STM32L4_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ -#define STM32L4_PCLK2_FREQUENCY (STM32L4_HCLK_FREQUENCY / 1) +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ +#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY / 1) -#define STM32L4_APB2_TIM1_CLKIN (STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM8_CLKIN (STM32L4_PCLK2_FREQUENCY) +#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) #elif defined(MSI_CLOCK_CONFIG) /* Use the MSI; frequ = 4 MHz; autotrim from LSE */ -#define STM32L4_BOARD_USEMSI 1 -#define STM32L4_BOARD_MSIRANGE RCC_CR_MSIRANGE_4M +#define STM32_BOARD_USEMSI 1 +#define STM32_BOARD_MSIRANGE RCC_CR_MSIRANGE_4M /* XXX sysclk mux = pllclk */ @@ -268,71 +268,71 @@ /* Prescaler common to all PLL inputs */ -#define STM32L4_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) /* 'main' PLL config; we use this to generate our system clock */ -#define STM32L4_PLLCFG_PLLN RCC_PLLCFG_PLLN(40) -#define STM32L4_PLLCFG_PLLP 0 -#undef STM32L4_PLLCFG_PLLP_ENABLED -#define STM32L4_PLLCFG_PLLQ 0 -#undef STM32L4_PLLCFG_PLLQ_ENABLED -#define STM32L4_PLLCFG_PLLR RCC_PLLCFG_PLLR_2 -#define STM32L4_PLLCFG_PLLR_ENABLED +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(40) +#define STM32_PLLCFG_PLLP 0 +#undef STM32_PLLCFG_PLLP_ENABLED +#define STM32_PLLCFG_PLLQ 0 +#undef STM32_PLLCFG_PLLQ_ENABLED +#define STM32_PLLCFG_PLLR RCC_PLLCFG_PLLR_2 +#define STM32_PLLCFG_PLLR_ENABLED /* 'SAIPLL1' is used to generate the 48 MHz clock */ -#define STM32L4_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(24) -#define STM32L4_PLLSAI1CFG_PLLP 0 -#undef STM32L4_PLLSAI1CFG_PLLP_ENABLED -#define STM32L4_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_2 -#define STM32L4_PLLSAI1CFG_PLLQ_ENABLED -#define STM32L4_PLLSAI1CFG_PLLR 0 -#undef STM32L4_PLLSAI1CFG_PLLR_ENABLED +#define STM32_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(24) +#define STM32_PLLSAI1CFG_PLLP 0 +#undef STM32_PLLSAI1CFG_PLLP_ENABLED +#define STM32_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_2 +#define STM32_PLLSAI1CFG_PLLQ_ENABLED +#define STM32_PLLSAI1CFG_PLLR 0 +#undef STM32_PLLSAI1CFG_PLLR_ENABLED /* 'SAIPLL2' is not used in this application */ -#define STM32L4_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) -#define STM32L4_PLLSAI2CFG_PLLP 0 -#undef STM32L4_PLLSAI2CFG_PLLP_ENABLED -#define STM32L4_PLLSAI2CFG_PLLR 0 -#undef STM32L4_PLLSAI2CFG_PLLR_ENABLED +#define STM32_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) +#define STM32_PLLSAI2CFG_PLLP 0 +#undef STM32_PLLSAI2CFG_PLLP_ENABLED +#define STM32_PLLSAI2CFG_PLLR 0 +#undef STM32_PLLSAI2CFG_PLLR_ENABLED -#define STM32L4_SYSCLK_FREQUENCY 80000000ul +#define STM32_SYSCLK_FREQUENCY 80000000ul /* Enable CLK48; get it from PLLSAI1 */ -#define STM32L4_USE_CLK48 -#define STM32L4_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 +#define STM32_USE_CLK48 +#define STM32_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 /* Enable LSE (for the RTC) */ -#define STM32L4_USE_LSE 1 +#define STM32_USE_LSE 1 /* Configure the HCLK divisor (for the AHB bus, core, memory, and DMA */ -#define STM32L4_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ -#define STM32L4_HCLK_FREQUENCY STM32L4_SYSCLK_FREQUENCY +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY /* Configure the APB1 prescaler */ -#define STM32L4_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ -#define STM32L4_PCLK1_FREQUENCY (STM32L4_HCLK_FREQUENCY / 1) +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY / 1) -#define STM32L4_APB1_TIM2_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM3_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM4_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM5_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM6_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM7_CLKIN (STM32L4_PCLK1_FREQUENCY) +#define STM32_APB1_TIM2_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM5_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (STM32_PCLK1_FREQUENCY) /* Configure the APB2 prescaler */ -#define STM32L4_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ -#define STM32L4_PCLK2_FREQUENCY (STM32L4_HCLK_FREQUENCY / 1) +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ +#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY / 1) -#define STM32L4_APB2_TIM1_CLKIN (STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM8_CLKIN (STM32L4_PCLK2_FREQUENCY) +#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) #endif @@ -343,19 +343,19 @@ * Note: TIM1,8,15,16,17 are on APB2, others on APB1 */ -#define BOARD_TIM1_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM2_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM3_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM4_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM5_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM6_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM7_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM8_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM15_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM16_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM17_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_LPTIM1_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_LPTIM2_FREQUENCY STM32L4_HCLK_FREQUENCY +#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM2_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM3_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM4_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM5_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM6_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM7_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM15_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM16_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM17_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_LPTIM1_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_LPTIM2_FREQUENCY STM32_HCLK_FREQUENCY /**************************************************************************** * Public Data @@ -382,4 +382,4 @@ extern "C" #endif #endif /* __ASSEMBLY__ */ -#endif /* __BOARDS_ARM_STM32L4_STM32L476VG_DISCO_INCLUDE_STM32L476VG_DISCO_CLOCKING_H */ +#endif /* __BOARDS_ARM_STM32_STM32L476VG_DISCO_INCLUDE_STM32L476VG_DISCO_CLOCKING_H */ diff --git a/boards/arm/stm32l4/stm32l476vg-disco/src/Make.defs b/boards/arm/stm32l4/stm32l476vg-disco/src/Make.defs new file mode 100644 index 0000000000000..a2a0313ee246f --- /dev/null +++ b/boards/arm/stm32l4/stm32l476vg-disco/src/Make.defs @@ -0,0 +1,69 @@ +############################################################################ +# boards/arm/stm32l4/stm32l476vg-disco/src/Makefile +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +CSRCS = stm32_boot.c stm32_bringup.c stm32_spi.c + +ifeq ($(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG),y) +CSRCS += stm32_clockconfig.c +endif + +ifeq ($(CONFIG_STM32_OTGFS),y) +CSRCS += stm32_usb.c +endif + +ifeq ($(CONFIG_ARCH_LEDS),y) +CSRCS += stm32_autoleds.c +else +CSRCS += stm32_userleds.c +endif + +ifeq ($(CONFIG_ARCH_BUTTONS),y) +CSRCS += stm32_buttons.c +endif + +ifeq ($(CONFIG_ADC),y) +#CSRCS += stm32_adc.c +endif + +ifeq ($(CONFIG_BOARDCTL_IOCTL),y) +CSRCS += stm32_ioctl.c +endif + +ifeq ($(CONFIG_ETC_ROMFS),y) +CSRCS += etc_romfs.c +endif + +ifeq ($(CONFIG_BOARDCTL_UNIQUEID),y) +CSRCS += stm32_uid.c +endif + +ifneq ($(CONFIG_STM32_ETHMAC),y) +ifeq ($(CONFIG_NETDEVICES),y) +CSRCS += stm32_netinit.c +endif +endif + +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32l4/stm32l476vg-disco/src/Makefile b/boards/arm/stm32l4/stm32l476vg-disco/src/Makefile deleted file mode 100644 index a2438eee63bd8..0000000000000 --- a/boards/arm/stm32l4/stm32l476vg-disco/src/Makefile +++ /dev/null @@ -1,67 +0,0 @@ -############################################################################ -# boards/arm/stm32l4/stm32l476vg-disco/src/Makefile -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/Make.defs - -CSRCS = stm32_boot.c stm32_bringup.c stm32_spi.c - -ifeq ($(CONFIG_ARCH_BOARD_STM32L4_CUSTOM_CLOCKCONFIG),y) -CSRCS += stm32_clockconfig.c -endif - -ifeq ($(CONFIG_STM32L4_OTGFS),y) -CSRCS += stm32_usb.c -endif - -ifeq ($(CONFIG_ARCH_LEDS),y) -CSRCS += stm32_autoleds.c -else -CSRCS += stm32_userleds.c -endif - -ifeq ($(CONFIG_ARCH_BUTTONS),y) -CSRCS += stm32_buttons.c -endif - -ifeq ($(CONFIG_ADC),y) -#CSRCS += stm32_adc.c -endif - -ifeq ($(CONFIG_BOARDCTL_IOCTL),y) -CSRCS += stm32_ioctl.c -endif - -ifeq ($(CONFIG_ETC_ROMFS),y) -CSRCS += etc_romfs.c -endif - -ifeq ($(CONFIG_BOARDCTL_UNIQUEID),y) -CSRCS += stm32_uid.c -endif - -ifneq ($(CONFIG_STM32_ETHMAC),y) -ifeq ($(CONFIG_NETDEVICES),y) -CSRCS += stm32_netinit.c -endif -endif - -include $(TOPDIR)/boards/Board.mk diff --git a/boards/arm/stm32l4/stm32l476vg-disco/src/stm32_autoleds.c b/boards/arm/stm32l4/stm32l476vg-disco/src/stm32_autoleds.c index a5c0dceaba472..bf1c2cd510329 100644 --- a/boards/arm/stm32l4/stm32l476vg-disco/src/stm32_autoleds.c +++ b/boards/arm/stm32l4/stm32l476vg-disco/src/stm32_autoleds.c @@ -35,7 +35,7 @@ #include "chip.h" #include "arm_internal.h" -#include "stm32l4.h" +#include "stm32.h" #include "stm32l476vg-disco.h" #ifdef CONFIG_ARCH_LEDS @@ -52,8 +52,8 @@ void board_autoled_initialize(void) { /* Configure LD4,5 GPIO for output */ - stm32l4_configgpio(GPIO_LED_RED); - stm32l4_configgpio(GPIO_LED_GRN); + stm32_configgpio(GPIO_LED_RED); + stm32_configgpio(GPIO_LED_GRN); } /**************************************************************************** @@ -92,7 +92,7 @@ void board_autoled_on(int led) case LED_INIRQ: case LED_SIGNAL: case LED_ASSERTION: - stm32l4_gpiowrite(GPIO_LED_RED, true); + stm32_gpiowrite(GPIO_LED_RED, true); break; /* 3: LED_PANIC: GPIO_LED_GRN=OFF RX=ON @@ -101,13 +101,13 @@ void board_autoled_on(int led) */ case LED_PANIC: - stm32l4_gpiowrite(GPIO_LED_GRN, false); - stm32l4_gpiowrite(GPIO_LED_RED, true); + stm32_gpiowrite(GPIO_LED_GRN, false); + stm32_gpiowrite(GPIO_LED_RED, true); break; case LED_IDLE: - stm32l4_gpiowrite(GPIO_LED_GRN, true); - stm32l4_gpiowrite(GPIO_LED_RED, false); + stm32_gpiowrite(GPIO_LED_GRN, true); + stm32_gpiowrite(GPIO_LED_RED, false); break; } } @@ -141,7 +141,7 @@ void board_autoled_off(int led) case LED_INIRQ: case LED_SIGNAL: case LED_ASSERTION: - stm32l4_gpiowrite(GPIO_LED_RED, false); + stm32_gpiowrite(GPIO_LED_RED, false); break; /* 3: LED_PANIC: GPIO_LED_GRN=OFF RX=OFF @@ -150,13 +150,13 @@ void board_autoled_off(int led) */ case LED_PANIC: - stm32l4_gpiowrite(GPIO_LED_GRN, false); - stm32l4_gpiowrite(GPIO_LED_RED, false); + stm32_gpiowrite(GPIO_LED_GRN, false); + stm32_gpiowrite(GPIO_LED_RED, false); break; case LED_IDLE: - stm32l4_gpiowrite(GPIO_LED_GRN, false); - stm32l4_gpiowrite(GPIO_LED_RED, false); + stm32_gpiowrite(GPIO_LED_GRN, false); + stm32_gpiowrite(GPIO_LED_RED, false); break; } } diff --git a/boards/arm/stm32l4/stm32l476vg-disco/src/stm32_boot.c b/boards/arm/stm32l4/stm32l476vg-disco/src/stm32_boot.c index 74a290c5550b3..34834af60d0a2 100644 --- a/boards/arm/stm32l4/stm32l476vg-disco/src/stm32_boot.c +++ b/boards/arm/stm32l4/stm32l476vg-disco/src/stm32_boot.c @@ -42,7 +42,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_board_initialize + * Name: stm32_board_initialize * * Description: * All STM32L4 architectures must provide the following entry point. This @@ -52,7 +52,7 @@ * ****************************************************************************/ -void stm32l4_board_initialize(void) +void stm32_board_initialize(void) { /* Configure on-board LEDs if LED support has been selected. */ @@ -65,10 +65,10 @@ void stm32l4_board_initialize(void) */ #if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || defined(CONFIG_STM32_SPI3) - stm32l4_spiinitialize(); + stm32_spiinitialize(); #endif -#ifdef CONFIG_STM32L4_OTGFS +#ifdef CONFIG_STM32_OTGFS /* Initialize USB if the * 1) OTG FS controller is in the configuration and * 2) disabled, and @@ -77,7 +77,7 @@ void stm32l4_board_initialize(void) * selected. */ - stm32l4_usbinitialize(); + stm32_usbinitialize(); #endif } diff --git a/boards/arm/stm32l4/stm32l476vg-disco/src/stm32_bringup.c b/boards/arm/stm32l4/stm32l476vg-disco/src/stm32_bringup.c index f96a416d76178..d2dc6b3d08a9d 100644 --- a/boards/arm/stm32l4/stm32l476vg-disco/src/stm32_bringup.c +++ b/boards/arm/stm32l4/stm32l476vg-disco/src/stm32_bringup.c @@ -37,9 +37,9 @@ #include #include -#include +#include #include -#include +#include #include #include @@ -124,7 +124,7 @@ int stm32_bringup(void) #ifdef HAVE_RTC_DRIVER /* Instantiate the STM32 lower-half RTC driver */ - rtclower = stm32l4_rtc_lowerhalf(); + rtclower = stm32_rtc_lowerhalf(); if (!rtclower) { serr("ERROR: Failed to instantiate the RTC lower-half driver\n"); @@ -148,10 +148,10 @@ int stm32_bringup(void) #ifdef HAVE_N25QXXX /* Create an instance of the STM32L4 QSPI device driver */ - g_qspi = stm32l4_qspi_initialize(0); + g_qspi = stm32_qspi_initialize(0); if (!g_qspi) { - _err("ERROR: stm32l4_qspi_initialize failed\n"); + _err("ERROR: stm32_qspi_initialize failed\n"); return ret; } else @@ -242,11 +242,11 @@ int stm32_bringup(void) #endif #ifdef HAVE_USBHOST - /* Initialize USB host operation. stm32l4_usbhost_initialize() starts a + /* Initialize USB host operation. stm32_usbhost_initialize() starts a * thread that will monitor for USB connection and disconnection events. */ - ret = stm32l4_usbhost_initialize(); + ret = stm32_usbhost_initialize(); if (ret != OK) { udbg("ERROR: Failed to initialize USB host: %d\n", ret); diff --git a/boards/arm/stm32l4/stm32l476vg-disco/src/stm32_buttons.c b/boards/arm/stm32l4/stm32l476vg-disco/src/stm32_buttons.c index 4bc824ac86995..13e713e899838 100644 --- a/boards/arm/stm32l4/stm32l476vg-disco/src/stm32_buttons.c +++ b/boards/arm/stm32l4/stm32l476vg-disco/src/stm32_buttons.c @@ -229,7 +229,7 @@ uint32_t board_button_initialize(void) for (i = 0; i < NUM_BUTTONS; i++) { - stm32l4_configgpio(g_buttons[i]); + stm32_configgpio(g_buttons[i]); /* It's not clear if this is correct; I think so, but then there are * conflicts with the 'buttons' sample app. @@ -260,7 +260,7 @@ uint32_t board_buttons(void) { /* A HIGH value means that the key is pressed. */ - bool pressed = stm32l4_gpioread(g_buttons[i]); + bool pressed = stm32_gpioread(g_buttons[i]); /* Accumulate the set of depressed (not released) keys */ @@ -315,7 +315,7 @@ int board_button_irq(int id, xcpt_t irqhandler, void *arg) if (id >= MIN_IRQBUTTON && id <= MAX_IRQBUTTON) { - ret = stm32l4_gpiosetevent(g_buttons[id], true, true, true, + ret = stm32_gpiosetevent(g_buttons[id], true, true, true, irqhandler, arg); } diff --git a/boards/arm/stm32l4/stm32l476vg-disco/src/stm32_clockconfig.c b/boards/arm/stm32l4/stm32l476vg-disco/src/stm32_clockconfig.c index 5257fe5408b0a..202b4e0dbcc78 100644 --- a/boards/arm/stm32l4/stm32l476vg-disco/src/stm32_clockconfig.c +++ b/boards/arm/stm32l4/stm32l476vg-disco/src/stm32_clockconfig.c @@ -52,122 +52,122 @@ * ****************************************************************************/ -#if defined(CONFIG_ARCH_BOARD_STM32L4_CUSTOM_CLOCKCONFIG) -void stm32l4_board_clockconfig(void) +#if defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) +void stm32_board_clockconfig(void) { uint32_t regval; /* Enable Internal High-Speed Clock (HSI) */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_HSION; /* Enable HSI */ - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Wait until the HSI is ready */ - while ((getreg32(STM32L4_RCC_CR) & RCC_CR_HSIRDY) == 0) + while ((getreg32(STM32_RCC_CR) & RCC_CR_HSIRDY) == 0) { } /* Set the HCLK source/divider */ - regval = getreg32(STM32L4_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_HPRE_MASK; - regval |= STM32L4_RCC_CFGR_HPRE; - putreg32(regval, STM32L4_RCC_CFGR); + regval |= STM32_RCC_CFGR_HPRE; + putreg32(regval, STM32_RCC_CFGR); /* Set the PCLK2 divider */ - regval = getreg32(STM32L4_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_PPRE2_MASK; - regval |= STM32L4_RCC_CFGR_PPRE2; - putreg32(regval, STM32L4_RCC_CFGR); + regval |= STM32_RCC_CFGR_PPRE2; + putreg32(regval, STM32_RCC_CFGR); /* Set the PCLK1 divider */ - regval = getreg32(STM32L4_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_PPRE1_MASK; - regval |= STM32L4_RCC_CFGR_PPRE1; - putreg32(regval, STM32L4_RCC_CFGR); + regval |= STM32_RCC_CFGR_PPRE1; + putreg32(regval, STM32_RCC_CFGR); /* Set the PLL source and main divider */ - regval = getreg32(STM32L4_RCC_PLLCFG); + regval = getreg32(STM32_RCC_PLLCFG); /* Configure Main PLL */ /* Set the PLL dividers and multipliers to configure the main PLL */ - regval = (STM32L4_PLLCFG_PLLM | STM32L4_PLLCFG_PLLN | STM32L4_PLLCFG_PLLP - | STM32L4_PLLCFG_PLLQ | STM32L4_PLLCFG_PLLR); + regval = (STM32_PLLCFG_PLLM | STM32_PLLCFG_PLLN | STM32_PLLCFG_PLLP + | STM32_PLLCFG_PLLQ | STM32_PLLCFG_PLLR); regval |= RCC_PLLCFG_PLLQEN; regval |= RCC_PLLCFG_PLLREN; /* XXX The choice of clock source to PLL (all three) is independent - * of the sys clock source choice, review the STM32L4_BOARD_USEHSI + * of the sys clock source choice, review the STM32_BOARD_USEHSI * name; probably split it into two, one for PLL source and one * for sys clock source. */ regval |= RCC_PLLCFG_PLLSRC_HSI; - putreg32(regval, STM32L4_RCC_PLLCFG); + putreg32(regval, STM32_RCC_PLLCFG); /* Enable the main PLL */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_PLLON; - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Wait until the PLL is ready */ - while ((getreg32(STM32L4_RCC_CR) & RCC_CR_PLLRDY) == 0) + while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLRDY) == 0) { } /* Configure SAI1 PLL */ - regval = getreg32(STM32L4_RCC_PLLSAI1CFG); + regval = getreg32(STM32_RCC_PLLSAI1CFG); /* Set the PLL dividers and multipliers to configure the SAI1 PLL */ - regval = (STM32L4_PLLSAI1CFG_PLLN | STM32L4_PLLSAI1CFG_PLLP | - STM32L4_PLLSAI1CFG_PLLQ | STM32L4_PLLSAI1CFG_PLLR); + regval = (STM32_PLLSAI1CFG_PLLN | STM32_PLLSAI1CFG_PLLP | + STM32_PLLSAI1CFG_PLLQ | STM32_PLLSAI1CFG_PLLR); regval |= RCC_PLLSAI1CFG_PLLQEN; - putreg32(regval, STM32L4_RCC_PLLSAI1CFG); + putreg32(regval, STM32_RCC_PLLSAI1CFG); /* Enable the SAI1 PLL */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_PLLSAI1ON; - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Wait until the PLL is ready */ - while ((getreg32(STM32L4_RCC_CR) & RCC_CR_PLLSAI1RDY) == 0) + while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLSAI1RDY) == 0) { } /* Configure SAI2 PLL */ - regval = getreg32(STM32L4_RCC_PLLSAI2CFG); + regval = getreg32(STM32_RCC_PLLSAI2CFG); /* Enable the SAI2 PLL */ /* Set the PLL dividers and multipliers to configure the SAI2 PLL */ - regval = (STM32L4_PLLSAI2CFG_PLLN | STM32L4_PLLSAI2CFG_PLLP | - STM32L4_PLLSAI2CFG_PLLR); - putreg32(regval, STM32L4_RCC_PLLSAI2CFG); + regval = (STM32_PLLSAI2CFG_PLLN | STM32_PLLSAI2CFG_PLLP | + STM32_PLLSAI2CFG_PLLR); + putreg32(regval, STM32_RCC_PLLSAI2CFG); /* Enable the SAI1 PLL */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_PLLSAI2ON; - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Wait until the PLL is ready */ - while ((getreg32(STM32L4_RCC_CR) & RCC_CR_PLLSAI2RDY) == 0) + while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLSAI2RDY) == 0) { } @@ -175,36 +175,36 @@ void stm32l4_board_clockconfig(void) * and 5 wait states */ -#ifdef CONFIG_STM32L4_FLASH_PREFETCH +#ifdef CONFIG_STM32_FLASH_PREFETCH regval = (FLASH_ACR_LATENCY_4 | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_PRFTEN); #else regval = (FLASH_ACR_LATENCY_4 | FLASH_ACR_ICEN | FLASH_ACR_DCEN); #endif - putreg32(regval, STM32L4_FLASH_ACR); + putreg32(regval, STM32_FLASH_ACR); /* Select the main PLL as system clock source */ - regval = getreg32(STM32L4_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_SW_MASK; regval |= RCC_CFGR_SW_PLL; - putreg32(regval, STM32L4_RCC_CFGR); + putreg32(regval, STM32_RCC_CFGR); /* Wait until the PLL source is used as the system clock source */ - while ((getreg32(STM32L4_RCC_CFGR) & RCC_CFGR_SWS_MASK) != + while ((getreg32(STM32_RCC_CFGR) & RCC_CFGR_SWS_MASK) != RCC_CFGR_SWS_PLL) { } -#if defined(CONFIG_STM32L4_IWDG) || defined(CONFIG_STM32L4_RTC_LSICLOCK) +#if defined(CONFIG_STM32_IWDG) || defined(CONFIG_STM32_RTC_LSICLOCK) /* Low speed internal clock source LSI */ - stm32l4_rcc_enablelsi(); + stm32_rcc_enablelsi(); #endif -#if defined(STM32L4_USE_LSE) +#if defined(STM32_USE_LSE) /* Low speed external clock source LSE * @@ -212,8 +212,8 @@ void stm32l4_board_clockconfig(void) * be enabled: if the MCO1 pin selects LSE as source. */ - stm32l4_pwr_enableclk(true); - stm32l4_rcc_enablelse(); + stm32_pwr_enableclk(true); + stm32_rcc_enablelse(); #endif } #endif diff --git a/boards/arm/stm32l4/stm32l476vg-disco/src/stm32_spi.c b/boards/arm/stm32l4/stm32l476vg-disco/src/stm32_spi.c index fcb4521d78998..dc297132fa986 100644 --- a/boards/arm/stm32l4/stm32l476vg-disco/src/stm32_spi.c +++ b/boards/arm/stm32l4/stm32l476vg-disco/src/stm32_spi.c @@ -35,7 +35,7 @@ #include #include "chip.h" -#include +#include #include "stm32l476vg-disco.h" diff --git a/boards/arm/stm32l4/stm32l476vg-disco/src/stm32_uid.c b/boards/arm/stm32l4/stm32l476vg-disco/src/stm32_uid.c index 7c6da8f1cdc85..6f48da0eaa377 100644 --- a/boards/arm/stm32l4/stm32l476vg-disco/src/stm32_uid.c +++ b/boards/arm/stm32l4/stm32l476vg-disco/src/stm32_uid.c @@ -38,7 +38,7 @@ #include -#include "stm32l4_uid.h" +#include "stm32_uid.h" #include "stm32l476vg-disco.h" /**************************************************************************** @@ -56,6 +56,6 @@ int board_uniqueid(uint8_t *uniqueid) return -EINVAL; } - stm32l4_get_uniqueid(uniqueid); + stm32_get_uniqueid(uniqueid); return OK; } diff --git a/boards/arm/stm32l4/stm32l476vg-disco/src/stm32_usb.c b/boards/arm/stm32l4/stm32l476vg-disco/src/stm32_usb.c index f5aa212e95510..40155f6c84a7e 100644 --- a/boards/arm/stm32l4/stm32l476vg-disco/src/stm32_usb.c +++ b/boards/arm/stm32l4/stm32l476vg-disco/src/stm32_usb.c @@ -40,11 +40,11 @@ #include #include "arm_internal.h" -#include "stm32l4.h" +#include "stm32.h" #include "stm32l4_otgfs.h" #include "stm32l476vg-disco.h" -#ifdef CONFIG_STM32L4_OTGFS +#ifdef CONFIG_STM32_OTGFS /**************************************************************************** * Pre-processor Definitions @@ -53,7 +53,7 @@ #if defined(CONFIG_USBDEV) || defined(CONFIG_USBHOST) # define HAVE_USB 1 #else -# warning "CONFIG_STM32L4_OTGFS is enabled but neither CONFIG_USBDEV nor CONFIG_USBHOST" +# warning "CONFIG_STM32_OTGFS is enabled but neither CONFIG_USBDEV nor CONFIG_USBHOST" # undef HAVE_USB #endif @@ -119,15 +119,15 @@ static int usbhost_waiter(int argc, char *argv[]) ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_usbinitialize + * Name: stm32_usbinitialize * * Description: - * Called from stm32l4_usbinitialize very early in initialization to + * Called from stm32_usbinitialize very early in initialization to * setup USB-related GPIO pins for the STM32L4Discovery board. * ****************************************************************************/ -void stm32l4_usbinitialize(void) +void stm32_usbinitialize(void) { /* The OTG FS has an internal soft pull-up. * No GPIO configuration is required @@ -137,15 +137,15 @@ void stm32l4_usbinitialize(void) * Power On, and Over current GPIOs */ -#ifdef CONFIG_STM32L4_OTGFS - stm32l4_configgpio(GPIO_OTGFS_VBUS); - stm32l4_configgpio(GPIO_OTGFS_PWRON); - stm32l4_configgpio(GPIO_OTGFS_OVER); +#ifdef CONFIG_STM32_OTGFS + stm32_configgpio(GPIO_OTGFS_VBUS); + stm32_configgpio(GPIO_OTGFS_PWRON); + stm32_configgpio(GPIO_OTGFS_OVER); #endif } /**************************************************************************** - * Name: stm32l4_usbhost_initialize + * Name: stm32_usbhost_initialize * * Description: * Called at application startup time to initialize the USB host @@ -156,7 +156,7 @@ void stm32l4_usbinitialize(void) ****************************************************************************/ #ifdef CONFIG_USBHOST -int stm32l4_usbhost_initialize(void) +int stm32_usbhost_initialize(void) { int ret; @@ -219,7 +219,7 @@ int stm32l4_usbhost_initialize(void) /* Then get an instance of the USB host interface */ uvdbg("Initialize USB host\n"); - g_usbconn = stm32l4_otgfshost_initialize(0); + g_usbconn = stm32_otgfshost_initialize(0); if (g_usbconn) { /* Start a thread to handle device connection. */ @@ -237,7 +237,7 @@ int stm32l4_usbhost_initialize(void) #endif /**************************************************************************** - * Name: stm32l4_usbhost_vbusdrive + * Name: stm32_usbhost_vbusdrive * * Description: * Enable/disable driving of VBUS 5V output. This function must be provided @@ -265,7 +265,7 @@ int stm32l4_usbhost_initialize(void) ****************************************************************************/ #ifdef CONFIG_USBHOST -void stm32l4_usbhost_vbusdrive(int iface, bool enable) +void stm32_usbhost_vbusdrive(int iface, bool enable) { DEBUGASSERT(iface == 0); @@ -273,19 +273,19 @@ void stm32l4_usbhost_vbusdrive(int iface, bool enable) { /* Enable the Power Switch by driving the enable pin low */ - stm32l4_gpiowrite(GPIO_OTGFS_PWRON, false); + stm32_gpiowrite(GPIO_OTGFS_PWRON, false); } else { /* Disable the Power Switch by driving the enable pin high */ - stm32l4_gpiowrite(GPIO_OTGFS_PWRON, true); + stm32_gpiowrite(GPIO_OTGFS_PWRON, true); } } #endif /**************************************************************************** - * Name: stm32l4_setup_overcurrent + * Name: stm32_setup_overcurrent * * Description: * Setup to receive an interrupt-level callback if an over current @@ -300,18 +300,18 @@ void stm32l4_usbhost_vbusdrive(int iface, bool enable) ****************************************************************************/ #ifdef CONFIG_USBHOST -xcpt_t stm32l4_setup_overcurrent(xcpt_t handler) +xcpt_t stm32_setup_overcurrent(xcpt_t handler) { - stm32l4_gpiosetevent(GPIO_OTGFS_OVER, true, true, true, handler, NULL); + stm32_gpiosetevent(GPIO_OTGFS_OVER, true, true, true, handler, NULL); return NULL; } #endif /**************************************************************************** - * Name: stm32l4_usbsuspend + * Name: stm32_usbsuspend * * Description: - * Board logic must provide the stm32l4_usbsuspend logic if the USBDEV + * Board logic must provide the stm32_usbsuspend logic if the USBDEV * driver is used. This function is called whenever the USB enters or * leaves suspend mode. This is an opportunity for the board logic to * shutdown clocks, power, etc. while the USB is suspended. @@ -319,10 +319,10 @@ xcpt_t stm32l4_setup_overcurrent(xcpt_t handler) ****************************************************************************/ #ifdef CONFIG_USBDEV -void stm32l4_usbsuspend(struct usbdev_s *dev, bool resume) +void stm32_usbsuspend(struct usbdev_s *dev, bool resume) { uinfo("resume: %d\n", resume); } #endif -#endif /* CONFIG_STM32L4_OTGFS */ +#endif /* CONFIG_STM32_OTGFS */ diff --git a/boards/arm/stm32l4/stm32l476vg-disco/src/stm32_userleds.c b/boards/arm/stm32l4/stm32l476vg-disco/src/stm32_userleds.c index 5ff1fcd886e09..39f749747e450 100644 --- a/boards/arm/stm32l4/stm32l476vg-disco/src/stm32_userleds.c +++ b/boards/arm/stm32l4/stm32l476vg-disco/src/stm32_userleds.c @@ -36,7 +36,7 @@ #include "chip.h" #include "arm_internal.h" -#include "stm32l4.h" +#include "stm32.h" #include "stm32l476vg-disco.h" #ifndef CONFIG_ARCH_LEDS @@ -89,11 +89,11 @@ static void led_pm_notify(struct pm_callback_s *cb, int domain, { /* Restore normal LEDs operation */ - /* stm32l4_gpiowrite(GPIO_LED_RED, + /* stm32_gpiowrite(GPIO_LED_RED, * (ledset & BOARD_LED_RED_BIT) != 0); */ - /* stm32l4_gpiowrite(GPIO_LED_GRN, + /* stm32_gpiowrite(GPIO_LED_GRN, * (ledset & BOARD_LED_GRN_BIT) != 0); */ } @@ -103,8 +103,8 @@ static void led_pm_notify(struct pm_callback_s *cb, int domain, { /* Entering IDLE mode - Turn leds off */ - stm32l4_gpiowrite(GPIO_LED_RED, 0); - stm32l4_gpiowrite(GPIO_LED_GRN, 0); + stm32_gpiowrite(GPIO_LED_RED, 0); + stm32_gpiowrite(GPIO_LED_GRN, 0); } break; @@ -112,8 +112,8 @@ static void led_pm_notify(struct pm_callback_s *cb, int domain, { /* Entering STANDBY mode - Logic for PM_STANDBY goes here */ - stm32l4_gpiowrite(GPIO_LED_RED, 0); - stm32l4_gpiowrite(GPIO_LED_GRN, 0); + stm32_gpiowrite(GPIO_LED_RED, 0); + stm32_gpiowrite(GPIO_LED_GRN, 0); } break; @@ -121,8 +121,8 @@ static void led_pm_notify(struct pm_callback_s *cb, int domain, { /* Entering SLEEP mode - Logic for PM_SLEEP goes here */ - stm32l4_gpiowrite(GPIO_LED_RED, 0); - stm32l4_gpiowrite(GPIO_LED_GRN, 0); + stm32_gpiowrite(GPIO_LED_RED, 0); + stm32_gpiowrite(GPIO_LED_GRN, 0); } break; @@ -171,8 +171,8 @@ uint32_t board_userled_initialize(void) { /* Configure LD4,5 GPIO for output */ - stm32l4_configgpio(GPIO_LED_RED); - stm32l4_configgpio(GPIO_LED_GRN); + stm32_configgpio(GPIO_LED_RED); + stm32_configgpio(GPIO_LED_GRN); return BOARD_NLEDS; } @@ -185,11 +185,11 @@ void board_userled(int led, bool ledon) switch (led) { case BOARD_LED_RED: - stm32l4_gpiowrite(GPIO_LED_RED, ledon); + stm32_gpiowrite(GPIO_LED_RED, ledon); break; case BOARD_LED_GRN: - stm32l4_gpiowrite(GPIO_LED_GRN, ledon); + stm32_gpiowrite(GPIO_LED_GRN, ledon); break; } } @@ -200,8 +200,8 @@ void board_userled(int led, bool ledon) void board_userled_all(uint32_t ledset) { - stm32l4_gpiowrite(GPIO_LED_RED, (ledset & BOARD_LED_RED_BIT) != 0); - stm32l4_gpiowrite(GPIO_LED_GRN, (ledset & BOARD_LED_GRN_BIT) != 0); + stm32_gpiowrite(GPIO_LED_RED, (ledset & BOARD_LED_RED_BIT) != 0); + stm32_gpiowrite(GPIO_LED_GRN, (ledset & BOARD_LED_GRN_BIT) != 0); } /**************************************************************************** diff --git a/boards/arm/stm32l4/stm32l476vg-disco/src/stm32l476vg-disco.h b/boards/arm/stm32l4/stm32l476vg-disco/src/stm32l476vg-disco.h index a8e921a60d079..3a81fb74df2a6 100644 --- a/boards/arm/stm32l4/stm32l476vg-disco/src/stm32l476vg-disco.h +++ b/boards/arm/stm32l4/stm32l476vg-disco/src/stm32l476vg-disco.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32L4_STM32L476VG_DISCO_SRC_STM32L476VG_DISCO_H -#define __BOARDS_ARM_STM32L4_STM32L476VG_DISCO_SRC_STM32L476VG_DISCO_H +#ifndef __BOARDS_ARM_STM32_STM32L476VG_DISCO_SRC_STM32L476VG_DISCO_H +#define __BOARDS_ARM_STM32_STM32L476VG_DISCO_SRC_STM32L476VG_DISCO_H /**************************************************************************** * Included Files @@ -74,7 +74,7 @@ # undef HAVE_N25QXXX_CHARDEV #endif -#ifndef CONFIG_STM32L4_QSPI +#ifndef CONFIG_STM32_QSPI # undef HAVE_N25QXXX # undef HAVE_N25QXXX_NXFFS # undef HAVE_N25QXXX_SMARTFS @@ -116,7 +116,7 @@ /* Can't support USB host or device features if USB OTG FS is not enabled */ -#ifndef CONFIG_STM32L4_OTGFS +#ifndef CONFIG_STM32_OTGFS # undef HAVE_USBDEV # undef HAVE_USBHOST #endif @@ -274,13 +274,13 @@ int stm32_bringup(void); void stm32_spiinitialize(void); /**************************************************************************** - * Name: stm32l4_usbinitialize + * Name: stm32_usbinitialize * * Description: * Called to setup USB-related GPIO pins. * ****************************************************************************/ -void stm32l4_usbinitialize(void); +void stm32_usbinitialize(void); -#endif /* __BOARDS_ARM_STM32L4_STM32L476VG_DISCO_SRC_STM32L476VG_DISCO_H */ +#endif /* __BOARDS_ARM_STM32_STM32L476VG_DISCO_SRC_STM32L476VG_DISCO_H */ diff --git a/boards/arm/stm32l4/stm32l4r9ai-disco/configs/knsh/defconfig b/boards/arm/stm32l4/stm32l4r9ai-disco/configs/knsh/defconfig index 020cf49a74023..9c6cfd36dfa3a 100644 --- a/boards/arm/stm32l4/stm32l4r9ai-disco/configs/knsh/defconfig +++ b/boards/arm/stm32l4/stm32l4r9ai-disco/configs/knsh/defconfig @@ -13,6 +13,7 @@ CONFIG_ARCH_BOARD="stm32l4r9ai-disco" CONFIG_ARCH_BOARD_STM32L4R9AI_DISCO=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32l4" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32L4=y CONFIG_ARCH_CHIP_STM32L4R9AI=y CONFIG_ARCH_INTERRUPTSTACK=2048 @@ -55,17 +56,17 @@ CONFIG_RTC_IOCTL=y CONFIG_RTC_NALARMS=2 CONFIG_SCHED_WAITPID=y CONFIG_SPI_DRIVER=y -CONFIG_STM32L4_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32L4_I2C1=y -CONFIG_STM32L4_I2C3=y -CONFIG_STM32L4_PWR=y -CONFIG_STM32L4_RNG=y -CONFIG_STM32L4_RTC=y -CONFIG_STM32L4_SAI1PLL=y -CONFIG_STM32L4_SPI2=y -CONFIG_STM32L4_SRAM2_HEAP=y -CONFIG_STM32L4_UART4=y -CONFIG_STM32L4_USART2=y +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_I2C1=y +CONFIG_STM32_I2C3=y +CONFIG_STM32_PWR=y +CONFIG_STM32_RNG=y +CONFIG_STM32_RTC=y +CONFIG_STM32_SAI1PLL=y +CONFIG_STM32_SPI2=y +CONFIG_STM32_SRAM2_HEAP=y +CONFIG_STM32_UART4=y +CONFIG_STM32_USART2=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_UART4_BAUD=2000000 diff --git a/boards/arm/stm32l4/stm32l4r9ai-disco/configs/nsh/defconfig b/boards/arm/stm32l4/stm32l4r9ai-disco/configs/nsh/defconfig index b2e29c4a53539..ca695bde26d45 100644 --- a/boards/arm/stm32l4/stm32l4r9ai-disco/configs/nsh/defconfig +++ b/boards/arm/stm32l4/stm32l4r9ai-disco/configs/nsh/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH_BOARD="stm32l4r9ai-disco" CONFIG_ARCH_BOARD_STM32L4R9AI_DISCO=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32l4" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32L4=y CONFIG_ARCH_CHIP_STM32L4R9AI=y CONFIG_ARCH_INTERRUPTSTACK=2048 @@ -56,18 +57,18 @@ CONFIG_RTC_IOCTL=y CONFIG_RTC_NALARMS=2 CONFIG_SCHED_WAITPID=y CONFIG_SPI_DRIVER=y -CONFIG_STM32L4_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32L4_DMA1=y -CONFIG_STM32L4_I2C1=y -CONFIG_STM32L4_I2C3=y -CONFIG_STM32L4_PWR=y -CONFIG_STM32L4_RNG=y -CONFIG_STM32L4_RTC=y -CONFIG_STM32L4_SAI1PLL=y -CONFIG_STM32L4_SPI2=y -CONFIG_STM32L4_SRAM2_HEAP=y -CONFIG_STM32L4_UART4=y -CONFIG_STM32L4_USART2=y +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_DMA1=y +CONFIG_STM32_I2C1=y +CONFIG_STM32_I2C3=y +CONFIG_STM32_PWR=y +CONFIG_STM32_RNG=y +CONFIG_STM32_RTC=y +CONFIG_STM32_SAI1PLL=y +CONFIG_STM32_SPI2=y +CONFIG_STM32_SRAM2_HEAP=y +CONFIG_STM32_UART4=y +CONFIG_STM32_USART2=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_UART4_BAUD=2000000 diff --git a/boards/arm/stm32l4/stm32l4r9ai-disco/include/board.h b/boards/arm/stm32l4/stm32l4r9ai-disco/include/board.h index cabf4cd5f4768..13b58c7980e5a 100644 --- a/boards/arm/stm32l4/stm32l4r9ai-disco/include/board.h +++ b/boards/arm/stm32l4/stm32l4r9ai-disco/include/board.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32L4_STM32L4R9AI_DISCO_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32L4_STM32L4R9AI_DISCO_INCLUDE_BOARD_H +#ifndef __BOARDS_ARM_STM32_STM32L4R9AI_DISCO_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32_STM32L4R9AI_DISCO_INCLUDE_BOARD_H /**************************************************************************** * Included Files @@ -275,7 +275,7 @@ extern "C" ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_board_initialize + * Name: stm32_board_initialize * * Description: * All STM32L4 architectures must provide the following entry point. @@ -285,7 +285,7 @@ extern "C" * ****************************************************************************/ -void stm32l4_board_initialize(void); +void stm32_board_initialize(void); #undef EXTERN #if defined(__cplusplus) @@ -293,4 +293,4 @@ void stm32l4_board_initialize(void); #endif #endif /* __ASSEMBLY__ */ -#endif /* __BOARDS_ARM_STM32L4_STM32L4R9AI_DISCO_INCLUDE_BOARD_H */ +#endif /* __BOARDS_ARM_STM32_STM32L4R9AI_DISCO_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32l4/stm32l4r9ai-disco/include/boardctl.h b/boards/arm/stm32l4/stm32l4r9ai-disco/include/boardctl.h index 30454d90bfb40..286cff6a34e6e 100644 --- a/boards/arm/stm32l4/stm32l4r9ai-disco/include/boardctl.h +++ b/boards/arm/stm32l4/stm32l4r9ai-disco/include/boardctl.h @@ -34,8 +34,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32L4_STM32L4R9AI_DISCO_INCLUDE_BOARDCTL_H -#define __BOARDS_ARM_STM32L4_STM32L4R9AI_DISCO_INCLUDE_BOARDCTL_H +#ifndef __BOARDS_ARM_STM32_STM32L4R9AI_DISCO_INCLUDE_BOARDCTL_H +#define __BOARDS_ARM_STM32_STM32L4R9AI_DISCO_INCLUDE_BOARDCTL_H /**************************************************************************** * Included Files @@ -50,4 +50,4 @@ #define BIOC_ENTER_MEMMAP BOARDIOC_USER+1 #define BIOC_EXIT_MEMMAP BOARDIOC_USER+2 -#endif /* __BOARDS_ARM_STM32L4_STM32L4R9AI_DISCO_INCLUDE_BOARDCTL_H */ +#endif /* __BOARDS_ARM_STM32_STM32L4R9AI_DISCO_INCLUDE_BOARDCTL_H */ diff --git a/boards/arm/stm32l4/stm32l4r9ai-disco/include/stm32l4r9ai-disco-clocking.h b/boards/arm/stm32l4/stm32l4r9ai-disco/include/stm32l4r9ai-disco-clocking.h index ddc8d01fb149e..1ed98a871a886 100644 --- a/boards/arm/stm32l4/stm32l4r9ai-disco/include/stm32l4r9ai-disco-clocking.h +++ b/boards/arm/stm32l4/stm32l4r9ai-disco/include/stm32l4r9ai-disco-clocking.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32L4_STM32L4R9AI_DISCO_INCLUDE_STM32L4R9AI_DISCO_CLOCKING_H -#define __BOARDS_ARM_STM32L4_STM32L4R9AI_DISCO_INCLUDE_STM32L4R9AI_DISCO_CLOCKING_H +#ifndef __BOARDS_ARM_STM32_STM32L4R9AI_DISCO_INCLUDE_STM32L4R9AI_DISCO_CLOCKING_H +#define __BOARDS_ARM_STM32_STM32L4R9AI_DISCO_INCLUDE_STM32L4R9AI_DISCO_CLOCKING_H /**************************************************************************** * Included Files @@ -53,13 +53,13 @@ * LSE - 32.768 kHz installed */ -#define STM32L4_HSI_FREQUENCY 16000000ul -#define STM32L4_LSI_FREQUENCY 32000 -#define STM32L4_LSE_FREQUENCY 32768 -#define STM32L4_HSE_FREQUENCY 16000000ul +#define STM32_HSI_FREQUENCY 16000000ul +#define STM32_LSI_FREQUENCY 32000 +#define STM32_LSE_FREQUENCY 32768 +#define STM32_HSE_FREQUENCY 16000000ul -#define STM32L4_SYSCLK_FREQUENCY 120000000ul -#define BOARD_AHB_FREQUENCY STM32L4_SYSCLK_FREQUENCY +#define STM32_SYSCLK_FREQUENCY 120000000ul +#define BOARD_AHB_FREQUENCY STM32_SYSCLK_FREQUENCY /* Higher SYSCLK requires more flash wait states. */ @@ -81,11 +81,11 @@ #if defined(HSI_CLOCK_CONFIG) -#define STM32L4_BOARD_USEHSI 1 +#define STM32_BOARD_USEHSI 1 /* Prescaler common to all PLL inputs; will be 1 */ -#define STM32L4_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) /* 'main' PLL config; we use this to generate our system clock via the R * output. We set it up as 16 MHz / 1 * 15 / 2 = 120 MHz @@ -96,13 +96,13 @@ * applications may want things done this way. */ -#define STM32L4_PLLCFG_PLLN RCC_PLLCFG_PLLN(15) -#define STM32L4_PLLCFG_PLLP 0 -#undef STM32L4_PLLCFG_PLLP_ENABLED -#define STM32L4_PLLCFG_PLLQ RCC_PLLCFG_PLLQ_2 -#define STM32L4_PLLCFG_PLLQ_ENABLED -#define STM32L4_PLLCFG_PLLR RCC_PLLCFG_PLLR_2 -#define STM32L4_PLLCFG_PLLR_ENABLED +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(15) +#define STM32_PLLCFG_PLLP 0 +#undef STM32_PLLCFG_PLLP_ENABLED +#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ_2 +#define STM32_PLLCFG_PLLQ_ENABLED +#define STM32_PLLCFG_PLLR RCC_PLLCFG_PLLR_2 +#define STM32_PLLCFG_PLLR_ENABLED /* 'SAIPLL1' is used to generate the 48 MHz clock, since we can't * do that with the main PLL's N value. We set N = 13, and enable @@ -116,47 +116,47 @@ * that is selected via a #define here, like all these other params. */ -#define STM32L4_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(12) -#define STM32L4_PLLSAI1CFG_PLLP 0 -#undef STM32L4_PLLSAI1CFG_PLLP_ENABLED -#define STM32L4_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_4 -#define STM32L4_PLLSAI1CFG_PLLQ_ENABLED -#define STM32L4_PLLSAI1CFG_PLLR 0 -#undef STM32L4_PLLSAI1CFG_PLLR_ENABLED +#define STM32_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(12) +#define STM32_PLLSAI1CFG_PLLP 0 +#undef STM32_PLLSAI1CFG_PLLP_ENABLED +#define STM32_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_4 +#define STM32_PLLSAI1CFG_PLLQ_ENABLED +#define STM32_PLLSAI1CFG_PLLR 0 +#undef STM32_PLLSAI1CFG_PLLR_ENABLED /* 'SAIPLL2' is not used in this application */ -#define STM32L4_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) -#define STM32L4_PLLSAI2CFG_PLLP 0 -#undef STM32L4_PLLSAI2CFG_PLLP_ENABLED -#define STM32L4_PLLSAI2CFG_PLLR 0 -#undef STM32L4_PLLSAI2CFG_PLLR_ENABLED +#define STM32_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) +#define STM32_PLLSAI2CFG_PLLP 0 +#undef STM32_PLLSAI2CFG_PLLP_ENABLED +#define STM32_PLLSAI2CFG_PLLR 0 +#undef STM32_PLLSAI2CFG_PLLR_ENABLED /* CLK48 will come from PLLSAI1 (implicitly Q) */ -#if defined(CONFIG_STM32L4_OTGFS) || defined(STM32L4_SDMMC) || defined(CONFIG_STM32L4_RNG) -# define STM32L4_USE_CLK48 1 -# define STM32L4_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 -# define STM32L4_HSI48_SYNCSRC SYNCSRC_NONE +#if defined(CONFIG_STM32_OTGFS) || defined(STM32_SDMMC) || defined(CONFIG_STM32_RNG) +# define STM32_USE_CLK48 1 +# define STM32_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 +# define STM32_HSI48_SYNCSRC SYNCSRC_NONE #endif /* Enable the LSE oscillator, used automatically trim the MSI, and for RTC */ -#define STM32L4_USE_LSE 1 +#define STM32_USE_LSE 1 /* HSI16 used as I2C clock */ -#define STM32L4_I2C_USE_HSI16 1 +#define STM32_I2C_USE_HSI16 1 /* AHB clock (HCLK) is SYSCLK (120 MHz) */ -#define STM32L4_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ -#define STM32L4_HCLK_FREQUENCY STM32L4_SYSCLK_FREQUENCY +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY /* APB1 clock (PCLK1) is HCLK/1 (120 MHz) */ -#define STM32L4_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ -#define STM32L4_PCLK1_FREQUENCY (STM32L4_HCLK_FREQUENCY / 1) +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY / 1) /* The timer clock frequencies are automatically defined by hardware. * If the APB prescaler equals 1, the timer clock frequencies are set to the @@ -165,17 +165,17 @@ * REVISIT : this can be configured */ -#define STM32L4_APB1_TIM2_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM3_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM4_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM5_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM6_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM7_CLKIN (STM32L4_PCLK1_FREQUENCY) +#define STM32_APB1_TIM2_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM5_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (STM32_PCLK1_FREQUENCY) /* APB2 clock (PCLK2) is HCLK (120 MHz) */ -#define STM32L4_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ -#define STM32L4_PCLK2_FREQUENCY (STM32L4_HCLK_FREQUENCY / 1) +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ +#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY / 1) /* The timer clock frequencies are automatically defined by hardware. * If the APB prescaler equals 1, the timer clock frequencies are set to the @@ -184,18 +184,18 @@ * REVISIT : this can be configured */ -#define STM32L4_APB2_TIM1_CLKIN (STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM8_CLKIN (STM32L4_PCLK2_FREQUENCY) +#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) #elif defined(HSE_CLOCK_CONFIG) /* Use the HSE */ -#define STM32L4_BOARD_USEHSE 1 +#define STM32_BOARD_USEHSE 1 /* Prescaler common to all PLL inputs */ -#define STM32L4_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) /* 'main' PLL config; we use this to generate our system clock via the R * output. We set it up as 16 MHz / 1 * 15 / 2 = 120 MHz @@ -206,13 +206,13 @@ * applications may want things done this way. */ -#define STM32L4_PLLCFG_PLLN RCC_PLLCFG_PLLN(15) -#define STM32L4_PLLCFG_PLLP 0 -#undef STM32L4_PLLCFG_PLLP_ENABLED -#define STM32L4_PLLCFG_PLLQ RCC_PLLCFG_PLLQ_2 -#define STM32L4_PLLCFG_PLLQ_ENABLED -#define STM32L4_PLLCFG_PLLR RCC_PLLCFG_PLLR_2 -#define STM32L4_PLLCFG_PLLR_ENABLED +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(15) +#define STM32_PLLCFG_PLLP 0 +#undef STM32_PLLCFG_PLLP_ENABLED +#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ_2 +#define STM32_PLLCFG_PLLQ_ENABLED +#define STM32_PLLCFG_PLLR RCC_PLLCFG_PLLR_2 +#define STM32_PLLCFG_PLLR_ENABLED /* 'SAIPLL1' is used to generate the 48 MHz clock, since we can't * do that with the main PLL's N value. We set N = 12, and enable @@ -226,73 +226,73 @@ * that is selected via a #define here, like all these other params. */ -#define STM32L4_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(12) -#define STM32L4_PLLSAI1CFG_PLLP 0 -#undef STM32L4_PLLSAI1CFG_PLLP_ENABLED -#define STM32L4_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_4 -#define STM32L4_PLLSAI1CFG_PLLQ_ENABLED -#define STM32L4_PLLSAI1CFG_PLLR 0 -#undef STM32L4_PLLSAI1CFG_PLLR_ENABLED +#define STM32_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(12) +#define STM32_PLLSAI1CFG_PLLP 0 +#undef STM32_PLLSAI1CFG_PLLP_ENABLED +#define STM32_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_4 +#define STM32_PLLSAI1CFG_PLLQ_ENABLED +#define STM32_PLLSAI1CFG_PLLR 0 +#undef STM32_PLLSAI1CFG_PLLR_ENABLED /* 'SAIPLL2' is not used in this application */ -#define STM32L4_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) -#define STM32L4_PLLSAI2CFG_PLLP 0 -#undef STM32L4_PLLSAI2CFG_PLLP_ENABLED -#define STM32L4_PLLSAI2CFG_PLLR 0 -#undef STM32L4_PLLSAI2CFG_PLLR_ENABLED +#define STM32_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) +#define STM32_PLLSAI2CFG_PLLP 0 +#undef STM32_PLLSAI2CFG_PLLP_ENABLED +#define STM32_PLLSAI2CFG_PLLR 0 +#undef STM32_PLLSAI2CFG_PLLR_ENABLED /* Enable CLK48; get it from PLLSAI1 */ -#if defined(CONFIG_STM32L4_OTGFS) || defined(STM32L4_SDMMC) || defined(CONFIG_STM32L4_RNG) -# define STM32L4_USE_CLK48 1 -# define STM32L4_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 -# define STM32L4_HSI48_SYNCSRC SYNCSRC_NONE +#if defined(CONFIG_STM32_OTGFS) || defined(STM32_SDMMC) || defined(CONFIG_STM32_RNG) +# define STM32_USE_CLK48 1 +# define STM32_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 +# define STM32_HSI48_SYNCSRC SYNCSRC_NONE #endif /* Enable LSE (for the RTC) */ -#define STM32L4_USE_LSE 1 +#define STM32_USE_LSE 1 /* HSI16 used as I2C clock */ -#define STM32L4_I2C_USE_HSI16 1 +#define STM32_I2C_USE_HSI16 1 /* Configure the HCLK divisor (for the AHB bus, core, memory, and DMA */ -#define STM32L4_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ -#define STM32L4_HCLK_FREQUENCY STM32L4_SYSCLK_FREQUENCY +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY /* Configure the APB1 prescaler */ -#define STM32L4_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ -#define STM32L4_PCLK1_FREQUENCY (STM32L4_HCLK_FREQUENCY / 1) +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY / 1) -#define STM32L4_APB1_TIM2_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM3_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM4_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM5_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM6_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM7_CLKIN (STM32L4_PCLK1_FREQUENCY) +#define STM32_APB1_TIM2_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM5_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (STM32_PCLK1_FREQUENCY) /* Configure the APB2 prescaler */ -#define STM32L4_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ -#define STM32L4_PCLK2_FREQUENCY (STM32L4_HCLK_FREQUENCY / 1) +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ +#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY / 1) -#define STM32L4_APB2_TIM1_CLKIN (STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM8_CLKIN (STM32L4_PCLK2_FREQUENCY) +#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) #elif defined(MSI_CLOCK_CONFIG) /* Use the MSI; frequ = 4 MHz; autotrim from LSE */ -#define STM32L4_BOARD_USEMSI 1 -#define STM32L4_BOARD_MSIRANGE RCC_CR_MSIRANGE_4M +#define STM32_BOARD_USEMSI 1 +#define STM32_BOARD_MSIRANGE RCC_CR_MSIRANGE_4M /* Prescaler common to all PLL inputs */ -#define STM32L4_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) /* 'main' PLL config; we use this to generate our system clock via the R * output. We set it up as 4 MHz / 1 * 60 / 2 = 120 MHz @@ -303,13 +303,13 @@ * applications may want things done this way. */ -#define STM32L4_PLLCFG_PLLN RCC_PLLCFG_PLLN(60) -#define STM32L4_PLLCFG_PLLP 0 -#undef STM32L4_PLLCFG_PLLP_ENABLED -#define STM32L4_PLLCFG_PLLQ RCC_PLLCFG_PLLQ_2 -#define STM32L4_PLLCFG_PLLQ_ENABLED -#define STM32L4_PLLCFG_PLLR RCC_PLLCFG_PLLR_2 -#define STM32L4_PLLCFG_PLLR_ENABLED +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(60) +#define STM32_PLLCFG_PLLP 0 +#undef STM32_PLLCFG_PLLP_ENABLED +#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ_2 +#define STM32_PLLCFG_PLLQ_ENABLED +#define STM32_PLLCFG_PLLR RCC_PLLCFG_PLLR_2 +#define STM32_PLLCFG_PLLR_ENABLED /* 'SAIPLL1' is used to generate the 48 MHz clock, since we can't * do that with the main PLL's N value. We set N = 12, and enable @@ -323,62 +323,62 @@ * that is selected via a #define here, like all these other params. */ -#define STM32L4_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(24) -#define STM32L4_PLLSAI1CFG_PLLP 0 -#undef STM32L4_PLLSAI1CFG_PLLP_ENABLED -#define STM32L4_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_2 -#define STM32L4_PLLSAI1CFG_PLLQ_ENABLED -#define STM32L4_PLLSAI1CFG_PLLR 0 -#undef STM32L4_PLLSAI1CFG_PLLR_ENABLED +#define STM32_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(24) +#define STM32_PLLSAI1CFG_PLLP 0 +#undef STM32_PLLSAI1CFG_PLLP_ENABLED +#define STM32_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_2 +#define STM32_PLLSAI1CFG_PLLQ_ENABLED +#define STM32_PLLSAI1CFG_PLLR 0 +#undef STM32_PLLSAI1CFG_PLLR_ENABLED /* 'SAIPLL2' is not used in this application */ -#define STM32L4_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) -#define STM32L4_PLLSAI2CFG_PLLP 0 -#undef STM32L4_PLLSAI2CFG_PLLP_ENABLED -#define STM32L4_PLLSAI2CFG_PLLR 0 -#undef STM32L4_PLLSAI2CFG_PLLR_ENABLED +#define STM32_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) +#define STM32_PLLSAI2CFG_PLLP 0 +#undef STM32_PLLSAI2CFG_PLLP_ENABLED +#define STM32_PLLSAI2CFG_PLLR 0 +#undef STM32_PLLSAI2CFG_PLLR_ENABLED /* Enable CLK48; get it from PLLSAI1 */ -#if defined(CONFIG_STM32L4_OTGFS) || defined(STM32L4_SDMMC) || defined(CONFIG_STM32L4_RNG) -# define STM32L4_USE_CLK48 1 -# define STM32L4_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 -# define STM32L4_HSI48_SYNCSRC SYNCSRC_NONE +#if defined(CONFIG_STM32_OTGFS) || defined(STM32_SDMMC) || defined(CONFIG_STM32_RNG) +# define STM32_USE_CLK48 1 +# define STM32_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 +# define STM32_HSI48_SYNCSRC SYNCSRC_NONE #endif /* Enable LSE (for the RTC) */ -#define STM32L4_USE_LSE 1 +#define STM32_USE_LSE 1 /* HSI16 used as I2C clock */ -#define STM32L4_I2C_USE_HSI16 1 +#define STM32_I2C_USE_HSI16 1 /* Configure the HCLK divisor (for the AHB bus, core, memory, and DMA */ -#define STM32L4_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ -#define STM32L4_HCLK_FREQUENCY STM32L4_SYSCLK_FREQUENCY +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY /* Configure the APB1 prescaler */ -#define STM32L4_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ -#define STM32L4_PCLK1_FREQUENCY (STM32L4_HCLK_FREQUENCY / 1) +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY / 1) -#define STM32L4_APB1_TIM2_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM3_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM4_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM5_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM6_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM7_CLKIN (STM32L4_PCLK1_FREQUENCY) +#define STM32_APB1_TIM2_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM5_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (STM32_PCLK1_FREQUENCY) /* Configure the APB2 prescaler */ -#define STM32L4_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ -#define STM32L4_PCLK2_FREQUENCY (STM32L4_HCLK_FREQUENCY / 1) +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ +#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY / 1) -#define STM32L4_APB2_TIM1_CLKIN (STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM8_CLKIN (STM32L4_PCLK2_FREQUENCY) +#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) #endif /* clock selection */ @@ -388,19 +388,19 @@ * Note: TIM1,8,15,16,17 are on APB2, others on APB1 */ -#define BOARD_TIM1_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM2_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM3_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM4_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM5_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM6_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM7_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM8_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM15_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM16_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM17_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_LPTIM1_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_LPTIM2_FREQUENCY STM32L4_HCLK_FREQUENCY +#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM2_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM3_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM4_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM5_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM6_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM7_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM15_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM16_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM17_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_LPTIM1_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_LPTIM2_FREQUENCY STM32_HCLK_FREQUENCY /**************************************************************************** * Public Data @@ -427,4 +427,4 @@ extern "C" #endif #endif /* __ASSEMBLY__ */ -#endif /* __BOARDS_ARM_STM32L4_STM32L4R9AI_DISCO_INCLUDE_STM32L4R9AI_DISCO_CLOCKING_H */ +#endif /* __BOARDS_ARM_STM32_STM32L4R9AI_DISCO_INCLUDE_STM32L4R9AI_DISCO_CLOCKING_H */ diff --git a/boards/arm/stm32l4/stm32l4r9ai-disco/src/Make.defs b/boards/arm/stm32l4/stm32l4r9ai-disco/src/Make.defs new file mode 100644 index 0000000000000..fb0302f1b5827 --- /dev/null +++ b/boards/arm/stm32l4/stm32l4r9ai-disco/src/Make.defs @@ -0,0 +1,82 @@ +############################################################################ +# boards/arm/stm32l4/stm32l4r9ai-disco/src/Makefile +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +CSRCS = stm32_boot.c stm32_bringup.c + +ifeq ($(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG),y) +CSRCS += stm32_clockconfig.c +endif + +ifeq ($(CONFIG_ARCH_LEDS),y) +CSRCS += stm32_autoleds.c +else +CSRCS += stm32_userleds.c +endif + +ifeq ($(CONFIG_ARCH_BUTTONS),y) +CSRCS += stm32_buttons.c +endif + +ifeq ($(CONFIG_ADC),y) +ifeq ($(CONFIG_STM32_ADC),y) +CSRCS += stm32_adc.c +endif +ifeq ($(CONFIG_STM32_DFSDM),y) +CSRCS += stm32_dfsdm.c +endif +endif + +ifeq ($(CONFIG_DAC),y) +CSRCS += stm32_dac.c +endif + +ifeq ($(CONFIG_STM32_SPI),y) +CSRCS += stm32_spi.c +endif + +ifeq ($(CONFIG_STM32_OTGFS),y) +CSRCS += stm32_usb.c +endif + +ifeq ($(CONFIG_BOARDCTL_IOCTL),y) +CSRCS += stm32_ioctl.c +endif + +ifeq ($(CONFIG_ETC_ROMFS),y) +CSRCS += etc_romfs.c +endif + +ifeq ($(CONFIG_BOARDCTL_UNIQUEID),y) +CSRCS += stm32_uid.c +endif + +ifneq ($(CONFIG_STM32_ETHMAC),y) +ifeq ($(CONFIG_NETDEVICES),y) +CSRCS += stm32_netinit.c +endif +endif + +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32l4/stm32l4r9ai-disco/src/Makefile b/boards/arm/stm32l4/stm32l4r9ai-disco/src/Makefile deleted file mode 100644 index 47936292ad5fb..0000000000000 --- a/boards/arm/stm32l4/stm32l4r9ai-disco/src/Makefile +++ /dev/null @@ -1,80 +0,0 @@ -############################################################################ -# boards/arm/stm32l4/stm32l4r9ai-disco/src/Makefile -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/Make.defs - -CSRCS = stm32_boot.c stm32_bringup.c - -ifeq ($(CONFIG_ARCH_BOARD_STM32L4_CUSTOM_CLOCKCONFIG),y) -CSRCS += stm32_clockconfig.c -endif - -ifeq ($(CONFIG_ARCH_LEDS),y) -CSRCS += stm32_autoleds.c -else -CSRCS += stm32_userleds.c -endif - -ifeq ($(CONFIG_ARCH_BUTTONS),y) -CSRCS += stm32_buttons.c -endif - -ifeq ($(CONFIG_ADC),y) -ifeq ($(CONFIG_STM32L4_ADC),y) -CSRCS += stm32_adc.c -endif -ifeq ($(CONFIG_STM32L4_DFSDM),y) -CSRCS += stm32_dfsdm.c -endif -endif - -ifeq ($(CONFIG_DAC),y) -CSRCS += stm32_dac.c -endif - -ifeq ($(CONFIG_STM32L4_SPI),y) -CSRCS += stm32_spi.c -endif - -ifeq ($(CONFIG_STM32L4_OTGFS),y) -CSRCS += stm32_usb.c -endif - -ifeq ($(CONFIG_BOARDCTL_IOCTL),y) -CSRCS += stm32_ioctl.c -endif - -ifeq ($(CONFIG_ETC_ROMFS),y) -CSRCS += etc_romfs.c -endif - -ifeq ($(CONFIG_BOARDCTL_UNIQUEID),y) -CSRCS += stm32_uid.c -endif - -ifneq ($(CONFIG_STM32_ETHMAC),y) -ifeq ($(CONFIG_NETDEVICES),y) -CSRCS += stm32_netinit.c -endif -endif - -include $(TOPDIR)/boards/Board.mk diff --git a/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_adc.c b/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_adc.c index 0e26c9ca5e998..f0ed838edef25 100644 --- a/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_adc.c +++ b/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_adc.c @@ -111,7 +111,7 @@ #define ADC1_NCHANNELS 4 -#if ADC1_NCHANNELS > 1 && !defined(CONFIG_STM32L4_ADC1_DMA) +#if ADC1_NCHANNELS > 1 && !defined(CONFIG_STM32_ADC1_DMA) # warning "Reading multiple channels without DMA might cause overruns!" #endif @@ -144,14 +144,14 @@ static const uint32_t g_pinlist[ADC1_NCHANNELS] = ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_adc_measure_voltages + * Name: stm32_adc_measure_voltages * * Description: * Read internal reference voltage, internal VBAT and one external voltage. * ****************************************************************************/ -int stm32l4_adc_measure_voltages(uint32_t *vrefint, uint32_t *vbat, +int stm32_adc_measure_voltages(uint32_t *vrefint, uint32_t *vbat, uint32_t *vext) { struct adc_msg_s sample[ADC1_NCHANNELS]; @@ -265,16 +265,16 @@ int stm32l4_adc_measure_voltages(uint32_t *vrefint, uint32_t *vbat, } /**************************************************************************** - * Name: stm32l4_adc_setup + * Name: stm32_adc_setup ****************************************************************************/ -int stm32l4_adc_setup(void) +int stm32_adc_setup(void) { static bool initialized = false; if (!initialized) { -#ifdef CONFIG_STM32L4_ADC1 +#ifdef CONFIG_STM32_ADC1 int ret; int i; @@ -284,13 +284,13 @@ int stm32l4_adc_setup(void) { if (g_pinlist[i] != 0xffffffffu) { - stm32l4_configgpio(g_pinlist[i]); + stm32_configgpio(g_pinlist[i]); } } - /* Call stm32l4_adc_initialize() to get an instance of the ADC */ + /* Call stm32_adc_initialize() to get an instance of the ADC */ - g_adc = stm32l4_adc_initialize(1, g_chanlist, ADC1_NCHANNELS); + g_adc = stm32_adc_initialize(1, g_chanlist, ADC1_NCHANNELS); if (g_adc == NULL) { aerr("ERROR: Failed to get ADC interface\n"); diff --git a/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_autoleds.c b/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_autoleds.c index a7af9a1dda8ac..fb79f4dbec311 100644 --- a/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_autoleds.c +++ b/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_autoleds.c @@ -35,7 +35,7 @@ #include "chip.h" #include "arm_internal.h" -#include "stm32l4.h" +#include "stm32.h" #include "stm32l4r9ai-disco.h" #ifdef CONFIG_ARCH_LEDS @@ -52,8 +52,8 @@ void board_autoled_initialize(void) { /* Configure LD4,5 GPIO for output */ - stm32l4_configgpio(GPIO_LED_RED); - stm32l4_configgpio(GPIO_LED_GRN); + stm32_configgpio(GPIO_LED_RED); + stm32_configgpio(GPIO_LED_GRN); } /**************************************************************************** @@ -92,7 +92,7 @@ void board_autoled_on(int led) case LED_INIRQ: case LED_SIGNAL: case LED_ASSERTION: - stm32l4_gpiowrite(GPIO_LED_RED, true); + stm32_gpiowrite(GPIO_LED_RED, true); break; /* 3: LED_PANIC: GPIO_LED_GRN=OFF RX=ON @@ -101,13 +101,13 @@ void board_autoled_on(int led) */ case LED_PANIC: - stm32l4_gpiowrite(GPIO_LED_GRN, false); - stm32l4_gpiowrite(GPIO_LED_RED, true); + stm32_gpiowrite(GPIO_LED_GRN, false); + stm32_gpiowrite(GPIO_LED_RED, true); break; case LED_IDLE: - stm32l4_gpiowrite(GPIO_LED_GRN, true); - stm32l4_gpiowrite(GPIO_LED_RED, false); + stm32_gpiowrite(GPIO_LED_GRN, true); + stm32_gpiowrite(GPIO_LED_RED, false); break; } } @@ -141,7 +141,7 @@ void board_autoled_off(int led) case LED_INIRQ: case LED_SIGNAL: case LED_ASSERTION: - stm32l4_gpiowrite(GPIO_LED_RED, false); + stm32_gpiowrite(GPIO_LED_RED, false); break; /* 3: LED_PANIC: GPIO_LED_GRN=OFF RX=OFF @@ -150,13 +150,13 @@ void board_autoled_off(int led) */ case LED_PANIC: - stm32l4_gpiowrite(GPIO_LED_GRN, false); - stm32l4_gpiowrite(GPIO_LED_RED, false); + stm32_gpiowrite(GPIO_LED_GRN, false); + stm32_gpiowrite(GPIO_LED_RED, false); break; case LED_IDLE: - stm32l4_gpiowrite(GPIO_LED_GRN, false); - stm32l4_gpiowrite(GPIO_LED_RED, false); + stm32_gpiowrite(GPIO_LED_GRN, false); + stm32_gpiowrite(GPIO_LED_RED, false); break; } } diff --git a/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_boot.c b/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_boot.c index ccc12956c6a36..98c867d816ae7 100644 --- a/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_boot.c +++ b/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_boot.c @@ -42,7 +42,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_board_initialize + * Name: stm32_board_initialize * * Description: * All STM32L4 architectures must provide the following entry point. This @@ -52,7 +52,7 @@ * ****************************************************************************/ -void stm32l4_board_initialize(void) +void stm32_board_initialize(void) { /* Configure on-board LEDs if LED support has been selected. */ @@ -64,11 +64,11 @@ void stm32l4_board_initialize(void) * function stm32_spiinitialize() has been brought into the link. */ -#ifdef CONFIG_STM32L4_SPI +#ifdef CONFIG_STM32_SPI stm32_spiinitialize(); #endif -#ifdef CONFIG_STM32L4_OTGFS +#ifdef CONFIG_STM32_OTGFS /* Initialize USB if the * 1) OTG FS controller is in the configuration and * 2) disabled, and @@ -77,7 +77,7 @@ void stm32l4_board_initialize(void) * also selected. */ - stm32l4_usbinitialize(); + stm32_usbinitialize(); #endif } diff --git a/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_bringup.c b/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_bringup.c index ae5c959cc3404..bc90f98987735 100644 --- a/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_bringup.c +++ b/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_bringup.c @@ -37,9 +37,9 @@ #include #include -#include +#include #include -#include +#include #include #include @@ -65,10 +65,10 @@ ****************************************************************************/ #ifdef CONFIG_I2C -# ifdef CONFIG_STM32L4_I2C1 +# ifdef CONFIG_STM32_I2C1 static struct i2c_master_s *g_i2c1; # endif -# ifdef CONFIG_STM32L4_I2C3 +# ifdef CONFIG_STM32_I2C3 static struct i2c_master_s *g_i2c3; # endif #endif @@ -112,7 +112,7 @@ int stm32_bringup(void) #ifdef HAVE_RTC_DRIVER /* Instantiate the STM32 lower-half RTC driver */ - rtclower = stm32l4_rtc_lowerhalf(); + rtclower = stm32_rtc_lowerhalf(); if (!rtclower) { serr("ERROR: Failed to instantiate the RTC lower-half driver\n"); @@ -135,15 +135,15 @@ int stm32_bringup(void) #ifdef CONFIG_I2C i2cinfo("Initializing I2C buses\n"); -#ifdef CONFIG_STM32L4_I2C1 - g_i2c1 = stm32l4_i2cbus_initialize(1); +#ifdef CONFIG_STM32_I2C1 + g_i2c1 = stm32_i2cbus_initialize(1); #ifdef CONFIG_I2C_DRIVER i2c_register(g_i2c1, 1); #endif #endif -#ifdef CONFIG_STM32L4_I2C3 - g_i2c3 = stm32l4_i2cbus_initialize(3); +#ifdef CONFIG_STM32_I2C3 + g_i2c3 = stm32_i2cbus_initialize(3); #ifdef CONFIG_I2C_DRIVER i2c_register(g_i2c3, 3); #endif @@ -151,11 +151,11 @@ int stm32_bringup(void) #endif /* CONFIG_I2C */ #ifdef HAVE_USBHOST - /* Initialize USB host operation. stm32l4_usbhost_initialize() starts a + /* Initialize USB host operation. stm32_usbhost_initialize() starts a * thread that will monitor for USB connection and disconnection events. */ - ret = stm32l4_usbhost_initialize(); + ret = stm32_usbhost_initialize(); if (ret != OK) { udbg("ERROR: Failed to initialize USB host: %d\n", ret); @@ -177,8 +177,8 @@ int stm32_bringup(void) #ifdef CONFIG_ADC ainfo("Initializing ADC\n"); - stm32l4_adc_setup(); -#ifdef CONFIG_STM32L4_DFSDM + stm32_adc_setup(); +#ifdef CONFIG_STM32_DFSDM /* Initialize DFSDM and register its filters as additional ADC devices. */ ret = stm32_dfsdm_setup(); @@ -192,7 +192,7 @@ int stm32_bringup(void) #ifdef CONFIG_DAC ainfo("Initializing DAC\n"); - stm32l4_dac_setup(); + stm32_dac_setup(); #endif return ret; diff --git a/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_buttons.c b/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_buttons.c index ba8240c175cd1..3c50102b1315c 100644 --- a/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_buttons.c +++ b/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_buttons.c @@ -229,7 +229,7 @@ uint32_t board_button_initialize(void) for (i = 0; i < NUM_BUTTONS; i++) { - stm32l4_configgpio(g_buttons[i]); + stm32_configgpio(g_buttons[i]); /* It's not clear if this is correct; I think so, but then there are * conflicts with the 'buttons' sample app. @@ -260,7 +260,7 @@ uint32_t board_buttons(void) { /* A HIGH value means that the key is pressed. */ - bool pressed = stm32l4_gpioread(g_buttons[i]); + bool pressed = stm32_gpioread(g_buttons[i]); /* Accumulate the set of depressed (not released) keys */ @@ -315,7 +315,7 @@ int board_button_irq(int id, xcpt_t irqhandler, void *arg) if (id >= MIN_IRQBUTTON && id <= MAX_IRQBUTTON) { - ret = stm32l4_gpiosetevent(g_buttons[id], true, true, true, + ret = stm32_gpiosetevent(g_buttons[id], true, true, true, irqhandler, arg); } diff --git a/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_clockconfig.c b/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_clockconfig.c index e17b57ba7fddf..0aec106529524 100644 --- a/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_clockconfig.c +++ b/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_clockconfig.c @@ -52,122 +52,122 @@ * ****************************************************************************/ -#if defined(CONFIG_ARCH_BOARD_STM32L4_CUSTOM_CLOCKCONFIG) -void stm32l4_board_clockconfig(void) +#if defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) +void stm32_board_clockconfig(void) { uint32_t regval; /* Enable Internal High-Speed Clock (HSI) */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_HSION; /* Enable HSI */ - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Wait until the HSI is ready */ - while ((getreg32(STM32L4_RCC_CR) & RCC_CR_HSIRDY) == 0) + while ((getreg32(STM32_RCC_CR) & RCC_CR_HSIRDY) == 0) { } /* Set the HCLK source/divider */ - regval = getreg32(STM32L4_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_HPRE_MASK; - regval |= STM32L4_RCC_CFGR_HPRE; - putreg32(regval, STM32L4_RCC_CFGR); + regval |= STM32_RCC_CFGR_HPRE; + putreg32(regval, STM32_RCC_CFGR); /* Set the PCLK2 divider */ - regval = getreg32(STM32L4_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_PPRE2_MASK; - regval |= STM32L4_RCC_CFGR_PPRE2; - putreg32(regval, STM32L4_RCC_CFGR); + regval |= STM32_RCC_CFGR_PPRE2; + putreg32(regval, STM32_RCC_CFGR); /* Set the PCLK1 divider */ - regval = getreg32(STM32L4_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_PPRE1_MASK; - regval |= STM32L4_RCC_CFGR_PPRE1; - putreg32(regval, STM32L4_RCC_CFGR); + regval |= STM32_RCC_CFGR_PPRE1; + putreg32(regval, STM32_RCC_CFGR); /* Set the PLL source and main divider */ - regval = getreg32(STM32L4_RCC_PLLCFG); + regval = getreg32(STM32_RCC_PLLCFG); /* Configure Main PLL */ /* Set the PLL dividers and multipliers to configure the main PLL */ - regval = (STM32L4_PLLCFG_PLLM | STM32L4_PLLCFG_PLLN | STM32L4_PLLCFG_PLLP - | STM32L4_PLLCFG_PLLQ | STM32L4_PLLCFG_PLLR); + regval = (STM32_PLLCFG_PLLM | STM32_PLLCFG_PLLN | STM32_PLLCFG_PLLP + | STM32_PLLCFG_PLLQ | STM32_PLLCFG_PLLR); regval |= RCC_PLLCFG_PLLQEN; regval |= RCC_PLLCFG_PLLREN; /* XXX The choice of clock source to PLL (all three) is independent - * of the sys clock source choice, review the STM32L4_BOARD_USEHSI + * of the sys clock source choice, review the STM32_BOARD_USEHSI * name; probably split it into two, one for PLL source and one * for sys clock source. */ regval |= RCC_PLLCFG_PLLSRC_HSI; - putreg32(regval, STM32L4_RCC_PLLCFG); + putreg32(regval, STM32_RCC_PLLCFG); /* Enable the main PLL */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_PLLON; - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Wait until the PLL is ready */ - while ((getreg32(STM32L4_RCC_CR) & RCC_CR_PLLRDY) == 0) + while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLRDY) == 0) { } /* Configure SAI1 PLL */ - regval = getreg32(STM32L4_RCC_PLLSAI1CFG); + regval = getreg32(STM32_RCC_PLLSAI1CFG); /* Set the PLL dividers and multipliers to configure the SAI1 PLL */ - regval = (STM32L4_PLLSAI1CFG_PLLN | STM32L4_PLLSAI1CFG_PLLP | - STM32L4_PLLSAI1CFG_PLLQ | STM32L4_PLLSAI1CFG_PLLR); + regval = (STM32_PLLSAI1CFG_PLLN | STM32_PLLSAI1CFG_PLLP | + STM32_PLLSAI1CFG_PLLQ | STM32_PLLSAI1CFG_PLLR); regval |= RCC_PLLSAI1CFG_PLLQEN; - putreg32(regval, STM32L4_RCC_PLLSAI1CFG); + putreg32(regval, STM32_RCC_PLLSAI1CFG); /* Enable the SAI1 PLL */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_PLLSAI1ON; - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Wait until the PLL is ready */ - while ((getreg32(STM32L4_RCC_CR) & RCC_CR_PLLSAI1RDY) == 0) + while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLSAI1RDY) == 0) { } /* Configure SAI2 PLL */ - regval = getreg32(STM32L4_RCC_PLLSAI2CFG); + regval = getreg32(STM32_RCC_PLLSAI2CFG); /* Enable the SAI2 PLL */ /* Set the PLL dividers and multipliers to configure the SAI2 PLL */ - regval = (STM32L4_PLLSAI2CFG_PLLN | STM32L4_PLLSAI2CFG_PLLP | - STM32L4_PLLSAI2CFG_PLLR); - putreg32(regval, STM32L4_RCC_PLLSAI2CFG); + regval = (STM32_PLLSAI2CFG_PLLN | STM32_PLLSAI2CFG_PLLP | + STM32_PLLSAI2CFG_PLLR); + putreg32(regval, STM32_RCC_PLLSAI2CFG); /* Enable the SAI1 PLL */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_PLLSAI2ON; - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Wait until the PLL is ready */ - while ((getreg32(STM32L4_RCC_CR) & RCC_CR_PLLSAI2RDY) == 0) + while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLSAI2RDY) == 0) { } @@ -175,36 +175,36 @@ void stm32l4_board_clockconfig(void) * data cache, and 5 wait states */ -#ifdef CONFIG_STM32L4_FLASH_PREFETCH +#ifdef CONFIG_STM32_FLASH_PREFETCH regval = (FLASH_ACR_LATENCY_4 | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_PRFTEN); #else regval = (FLASH_ACR_LATENCY_4 | FLASH_ACR_ICEN | FLASH_ACR_DCEN); #endif - putreg32(regval, STM32L4_FLASH_ACR); + putreg32(regval, STM32_FLASH_ACR); /* Select the main PLL as system clock source */ - regval = getreg32(STM32L4_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_SW_MASK; regval |= RCC_CFGR_SW_PLL; - putreg32(regval, STM32L4_RCC_CFGR); + putreg32(regval, STM32_RCC_CFGR); /* Wait until the PLL source is used as the system clock source */ - while ((getreg32(STM32L4_RCC_CFGR) & RCC_CFGR_SWS_MASK) != + while ((getreg32(STM32_RCC_CFGR) & RCC_CFGR_SWS_MASK) != RCC_CFGR_SWS_PLL) { } -#if defined(CONFIG_STM32L4_IWDG) || defined(CONFIG_STM32L4_RTC_LSICLOCK) +#if defined(CONFIG_STM32_IWDG) || defined(CONFIG_STM32_RTC_LSICLOCK) /* Low speed internal clock source LSI */ - stm32l4_rcc_enablelsi(); + stm32_rcc_enablelsi(); #endif -#if defined(STM32L4_USE_LSE) +#if defined(STM32_USE_LSE) /* Low speed external clock source LSE * @@ -212,8 +212,8 @@ void stm32l4_board_clockconfig(void) * be enabled: if the MCO1 pin selects LSE as source. */ - stm32l4_pwr_enableclk(true); - stm32l4_rcc_enablelse(); + stm32_pwr_enableclk(true); + stm32_rcc_enablelse(); #endif } #endif diff --git a/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_dac.c b/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_dac.c index 99e82f4d6d257..63124aab2074b 100644 --- a/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_dac.c +++ b/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_dac.c @@ -48,19 +48,19 @@ static struct dac_dev_s *g_dac; ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_dac_setup + * Name: stm32_dac_setup ****************************************************************************/ -int stm32l4_dac_setup(void) +int stm32_dac_setup(void) { static bool initialized = false; if (!initialized) { -#ifdef CONFIG_STM32L4_DAC1 +#ifdef CONFIG_STM32_DAC1 int ret; - g_dac = stm32l4_dacinitialize(0); + g_dac = stm32_dacinitialize(0); if (g_dac == NULL) { aerr("ERROR: Failed to get DAC interface\n"); diff --git a/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_dfsdm.c b/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_dfsdm.c index ba31c3d3d17ec..641f9dc111565 100644 --- a/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_dfsdm.c +++ b/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_dfsdm.c @@ -38,7 +38,7 @@ #include -#if defined(CONFIG_ADC) && defined(CONFIG_STM32L4_DFSDM) +#if defined(CONFIG_ADC) && defined(CONFIG_STM32_DFSDM) /**************************************************************************** * Public Functions @@ -56,28 +56,28 @@ int stm32_dfsdm_setup(void) { int ret; struct adc_dev_s *adc; -#ifdef CONFIG_STM32L4_DFSDM1_FLT0 +#ifdef CONFIG_STM32_DFSDM1_FLT0 const uint8_t chanlist0[1] = { 0 }; #endif -#ifdef CONFIG_STM32L4_DFSDM1_FLT1 +#ifdef CONFIG_STM32_DFSDM1_FLT1 const uint8_t chanlist1[2] = { 0, 1 }; #endif -#ifdef CONFIG_STM32L4_DFSDM1_FLT2 +#ifdef CONFIG_STM32_DFSDM1_FLT2 const uint8_t chanlist2[8] = { 0, 1, 2, 3, 4, 5, 6, 7 }; #endif -#ifdef CONFIG_STM32L4_DFSDM1_FLT3 +#ifdef CONFIG_STM32_DFSDM1_FLT3 const uint8_t chanlist3[4] = { 6, 5, 4, 3 @@ -91,8 +91,8 @@ int stm32_dfsdm_setup(void) * parallel inputs (CPU/DMA/ADC). */ -#ifdef CONFIG_STM32L4_DFSDM1_FLT0 - adc = stm32l4_dfsdm_initialize(0, chanlist0, 1); +#ifdef CONFIG_STM32_DFSDM1_FLT0 + adc = stm32_dfsdm_initialize(0, chanlist0, 1); if (adc == NULL) { aerr("Failed to get DFSDM FLT0 interface\n"); @@ -107,8 +107,8 @@ int stm32_dfsdm_setup(void) } #endif -#ifdef CONFIG_STM32L4_DFSDM1_FLT1 - adc = stm32l4_dfsdm_initialize(1, chanlist1, 2); +#ifdef CONFIG_STM32_DFSDM1_FLT1 + adc = stm32_dfsdm_initialize(1, chanlist1, 2); if (adc == NULL) { aerr("Failed to get DFSDM FLT1 interface\n"); @@ -123,8 +123,8 @@ int stm32_dfsdm_setup(void) } #endif -#ifdef CONFIG_STM32L4_DFSDM1_FLT2 - adc = stm32l4_dfsdm_initialize(2, chanlist2, 8); +#ifdef CONFIG_STM32_DFSDM1_FLT2 + adc = stm32_dfsdm_initialize(2, chanlist2, 8); if (adc == NULL) { aerr("Failed to get DFSDM FLT2 interface\n"); @@ -139,8 +139,8 @@ int stm32_dfsdm_setup(void) } #endif -#ifdef CONFIG_STM32L4_DFSDM1_FLT3 - adc = stm32l4_dfsdm_initialize(3, chanlist3, 4); +#ifdef CONFIG_STM32_DFSDM1_FLT3 + adc = stm32_dfsdm_initialize(3, chanlist3, 4); if (adc == NULL) { aerr("Failed to get DFSDM FLT3 interface\n"); @@ -160,4 +160,4 @@ int stm32_dfsdm_setup(void) return OK; } -#endif /* CONFIG_ADC && CONFIG_STM32L4_DFSDM */ +#endif /* CONFIG_ADC && CONFIG_STM32_DFSDM */ diff --git a/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_spi.c b/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_spi.c index f86e4621d120c..6d9e8e2bf6d8a 100644 --- a/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_spi.c +++ b/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_spi.c @@ -36,11 +36,11 @@ #include #include "chip.h" -#include +#include #include "stm32l4r9ai-disco.h" -#if defined(CONFIG_STM32L4_SPI1) || defined(CONFIG_STM32L4_SPI2) || defined(CONFIG_STM32L4_SPI3) +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || defined(CONFIG_STM32_SPI3) /**************************************************************************** * Public Data @@ -48,13 +48,13 @@ /* Global driver instances */ -#ifdef CONFIG_STM32L4_SPI1 +#ifdef CONFIG_STM32_SPI1 struct spi_dev_s *g_spi1; #endif -#ifdef CONFIG_STM32L4_SPI2 +#ifdef CONFIG_STM32_SPI2 struct spi_dev_s *g_spi2; #endif -#ifdef CONFIG_STM32L4_SPI3 +#ifdef CONFIG_STM32_SPI3 struct spi_dev_s *g_spi3; #endif @@ -72,10 +72,10 @@ struct spi_dev_s *g_spi3; void weak_function stm32_spiinitialize(void) { -#ifdef CONFIG_STM32L4_SPI1 +#ifdef CONFIG_STM32_SPI1 /* Configure SPI-based devices on SPI1 */ - g_spi1 = stm32l4_spibus_initialize(1); + g_spi1 = stm32_spibus_initialize(1); if (!g_spi1) { spierr("ERROR: [boot] FAILED to initialize SPI port 1\n"); @@ -86,14 +86,14 @@ void weak_function stm32_spiinitialize(void) #endif #ifdef HAVE_MMCSD - stm32l4_configgpio(GPIO_SPI_CS_SD_CARD); + stm32_configgpio(GPIO_SPI_CS_SD_CARD); #endif #endif -#ifdef CONFIG_STM32L4_SPI2 +#ifdef CONFIG_STM32_SPI2 /* Configure SPI-based devices on SPI2 */ - g_spi2 = stm32l4_spibus_initialize(2); + g_spi2 = stm32_spibus_initialize(2); if (!g_spi2) { spierr("ERROR: [boot] FAILED to initialize SPI port 2\n"); @@ -106,10 +106,10 @@ void weak_function stm32_spiinitialize(void) #warning No devices specified on SPI2 #endif -#ifdef CONFIG_STM32L4_SPI3 +#ifdef CONFIG_STM32_SPI3 /* Configure SPI-based devices on SPI3 */ - g_spi3 = stm32l4_spibus_initialize(3); + g_spi3 = stm32_spibus_initialize(3); if (!g_spi3) { spierr("ERROR: [boot] FAILED to initialize SPI port 3\n"); @@ -124,14 +124,14 @@ void weak_function stm32_spiinitialize(void) } /**************************************************************************** - * Name: stm32l4_spi1/2/3select and stm32l4_spi1/2/3status + * Name: stm32_spi1/2/3select and stm32_spi1/2/3status * * Description: * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status * must be provided by board-specific logic. They are implementations of * the select and status methods of the SPI interface defined by struct * spi_ops_s (see include/nuttx/spi/spi.h). All other methods - * (including stm32l4_spibus_initialize()) are provided by common STM32 + * (including stm32_spibus_initialize()) are provided by common STM32 * logic. To use this common SPI logic on your board: * * 1. Provide logic in stm32_boardinitialize() to configure SPI chip select @@ -140,17 +140,17 @@ void weak_function stm32_spiinitialize(void) * in your board-specific logic. These functions will perform chip * selection and status operations using GPIOs in the way your board is * configured. - * 3. Add a calls to stm32l4_spibus_initialize() in your low level + * 3. Add a calls to stm32_spibus_initialize() in your low level * application initialization logic - * 4. The handle returned by stm32l4_spibus_initialize() may then be used + * 4. The handle returned by stm32_spibus_initialize() may then be used * to bind the SPI driver to higher level logic (e.g., calling * mmcsd_spislotinitialize(), for example, will bind the SPI driver to * the SPI MMC/SD driver). * ****************************************************************************/ -#ifdef CONFIG_STM32L4_SPI1 -void stm32l4_spi1select(struct spi_dev_s *dev, +#ifdef CONFIG_STM32_SPI1 +void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, bool selected) { spiinfo("devid: %d CS: %s\n", @@ -159,47 +159,47 @@ void stm32l4_spi1select(struct spi_dev_s *dev, #ifdef HAVE_MMCSD if (devid == SPIDEV_MMCSD(0)) { - stm32l4_gpiowrite(GPIO_SPI_CS_SD_CARD, !selected); + stm32_gpiowrite(GPIO_SPI_CS_SD_CARD, !selected); } #endif } -uint8_t stm32l4_spi1status(struct spi_dev_s *dev, uint32_t devid) +uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) { return 0; } #endif -#ifdef CONFIG_STM32L4_SPI2 -void stm32l4_spi2select(struct spi_dev_s *dev, +#ifdef CONFIG_STM32_SPI2 +void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid, bool selected) { spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); } -uint8_t stm32l4_spi2status(struct spi_dev_s *dev, uint32_t devid) +uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) { return 0; } #endif -#ifdef CONFIG_STM32L4_SPI3 -void stm32l4_spi3select(struct spi_dev_s *dev, +#ifdef CONFIG_STM32_SPI3 +void stm32_spi3select(struct spi_dev_s *dev, uint32_t devid, bool selected) { spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); } -uint8_t stm32l4_spi3status(struct spi_dev_s *dev, uint32_t devid) +uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid) { return 0; } #endif /**************************************************************************** - * Name: stm32l4_spi1/2/3cmddata + * Name: stm32_spi1/2/3cmddata * * Description: * Set or clear the SH1101A A0 or SD1306 D/C n bit to select data (true) @@ -222,26 +222,26 @@ uint8_t stm32l4_spi3status(struct spi_dev_s *dev, uint32_t devid) ****************************************************************************/ #ifdef CONFIG_SPI_CMDDATA -#ifdef CONFIG_STM32L4_SPI1 -int stm32l4_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) +#ifdef CONFIG_STM32_SPI1 +int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return OK; } #endif -#ifdef CONFIG_STM32L4_SPI2 -int stm32l4_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) +#ifdef CONFIG_STM32_SPI2 +int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return OK; } #endif -#ifdef CONFIG_STM32L4_SPI3 -int stm32l4_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) +#ifdef CONFIG_STM32_SPI3 +int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return OK; } #endif #endif /* CONFIG_SPI_CMDDATA */ -#endif /* CONFIG_STM32L4_SPI1 || CONFIG_STM32L4_SPI2 || CONFIG_STM32L4_SPI3 */ +#endif /* CONFIG_STM32_SPI1 || CONFIG_STM32_SPI2 || CONFIG_STM32_SPI3 */ diff --git a/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_uid.c b/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_uid.c index bb1720bae25fd..d0ee15fcd0e0d 100644 --- a/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_uid.c +++ b/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_uid.c @@ -38,7 +38,7 @@ #include -#include "stm32l4_uid.h" +#include "stm32_uid.h" #include "stm32l4r9ai-disco.h" /**************************************************************************** @@ -56,6 +56,6 @@ int board_uniqueid(uint8_t *uniqueid) return -EINVAL; } - stm32l4_get_uniqueid(uniqueid); + stm32_get_uniqueid(uniqueid); return OK; } diff --git a/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_usb.c b/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_usb.c index d36a3b179523a..314bef362e16f 100644 --- a/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_usb.c +++ b/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_usb.c @@ -40,11 +40,11 @@ #include #include "arm_internal.h" -#include "stm32l4.h" +#include "stm32.h" #include "stm32l4_otgfs.h" #include "stm32l4r9ai-disco.h" -#ifdef CONFIG_STM32L4_OTGFS +#ifdef CONFIG_STM32_OTGFS /**************************************************************************** * Pre-processor Definitions @@ -53,7 +53,7 @@ #if defined(CONFIG_USBDEV) || defined(CONFIG_USBHOST) # define HAVE_USB 1 #else -# warning "CONFIG_STM32L4_OTGFS is enabled but neither CONFIG_USBDEV nor CONFIG_USBHOST" +# warning "CONFIG_STM32_OTGFS is enabled but neither CONFIG_USBDEV nor CONFIG_USBHOST" # undef HAVE_USB #endif @@ -119,15 +119,15 @@ static int usbhost_waiter(int argc, char *argv[]) ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_usbinitialize + * Name: stm32_usbinitialize * * Description: - * Called from stm32l4_usbinitialize very early in initialization to setup + * Called from stm32_usbinitialize very early in initialization to setup * USB-related GPIO pins for the STM32L4Discovery board. * ****************************************************************************/ -void stm32l4_usbinitialize(void) +void stm32_usbinitialize(void) { /* The OTG FS has an internal soft pull-up. * No GPIO configuration is required @@ -137,15 +137,15 @@ void stm32l4_usbinitialize(void) * Power On, and Over current GPIOs */ -#ifdef CONFIG_STM32L4_OTGFS - stm32l4_configgpio(GPIO_OTGFS_VBUS); - stm32l4_configgpio(GPIO_OTGFS_PWRON); - stm32l4_configgpio(GPIO_OTGFS_OVER); +#ifdef CONFIG_STM32_OTGFS + stm32_configgpio(GPIO_OTGFS_VBUS); + stm32_configgpio(GPIO_OTGFS_PWRON); + stm32_configgpio(GPIO_OTGFS_OVER); #endif } /**************************************************************************** - * Name: stm32l4_usbhost_initialize + * Name: stm32_usbhost_initialize * * Description: * Called at application startup time to initialize the USB host @@ -156,7 +156,7 @@ void stm32l4_usbinitialize(void) ****************************************************************************/ #ifdef CONFIG_USBHOST -int stm32l4_usbhost_initialize(void) +int stm32_usbhost_initialize(void) { int ret; @@ -219,7 +219,7 @@ int stm32l4_usbhost_initialize(void) /* Then get an instance of the USB host interface */ uvdbg("Initialize USB host\n"); - g_usbconn = stm32l4_otgfshost_initialize(0); + g_usbconn = stm32_otgfshost_initialize(0); if (g_usbconn) { /* Start a thread to handle device connection. */ @@ -237,7 +237,7 @@ int stm32l4_usbhost_initialize(void) #endif /**************************************************************************** - * Name: stm32l4_usbhost_vbusdrive + * Name: stm32_usbhost_vbusdrive * * Description: * Enable/disable driving of VBUS 5V output. This function must be @@ -266,7 +266,7 @@ int stm32l4_usbhost_initialize(void) ****************************************************************************/ #ifdef CONFIG_USBHOST -void stm32l4_usbhost_vbusdrive(int iface, bool enable) +void stm32_usbhost_vbusdrive(int iface, bool enable) { DEBUGASSERT(iface == 0); @@ -274,19 +274,19 @@ void stm32l4_usbhost_vbusdrive(int iface, bool enable) { /* Enable the Power Switch by driving the enable pin low */ - stm32l4_gpiowrite(GPIO_OTGFS_PWRON, false); + stm32_gpiowrite(GPIO_OTGFS_PWRON, false); } else { /* Disable the Power Switch by driving the enable pin high */ - stm32l4_gpiowrite(GPIO_OTGFS_PWRON, true); + stm32_gpiowrite(GPIO_OTGFS_PWRON, true); } } #endif /**************************************************************************** - * Name: stm32l4_setup_overcurrent + * Name: stm32_setup_overcurrent * * Description: * Setup to receive an interrupt-level callback if an over current @@ -301,18 +301,18 @@ void stm32l4_usbhost_vbusdrive(int iface, bool enable) ****************************************************************************/ #ifdef CONFIG_USBHOST -xcpt_t stm32l4_setup_overcurrent(xcpt_t handler) +xcpt_t stm32_setup_overcurrent(xcpt_t handler) { - stm32l4_gpiosetevent(GPIO_OTGFS_OVER, true, true, true, handler, NULL); + stm32_gpiosetevent(GPIO_OTGFS_OVER, true, true, true, handler, NULL); return NULL; } #endif /**************************************************************************** - * Name: stm32l4_usbsuspend + * Name: stm32_usbsuspend * * Description: - * Board logic must provide the stm32l4_usbsuspend logic if the USBDEV + * Board logic must provide the stm32_usbsuspend logic if the USBDEV * driver is used. This function is called whenever the USB enters or * leaves suspend mode. This is an opportunity for the board logic to * shutdown clocks, power, etc. while the USB is suspended. @@ -320,10 +320,10 @@ xcpt_t stm32l4_setup_overcurrent(xcpt_t handler) ****************************************************************************/ #ifdef CONFIG_USBDEV -void stm32l4_usbsuspend(struct usbdev_s *dev, bool resume) +void stm32_usbsuspend(struct usbdev_s *dev, bool resume) { uinfo("resume: %d\n", resume); } #endif -#endif /* CONFIG_STM32L4_OTGFS */ +#endif /* CONFIG_STM32_OTGFS */ diff --git a/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_userleds.c b/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_userleds.c index 557436dade860..5d07a4d35840c 100644 --- a/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_userleds.c +++ b/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_userleds.c @@ -36,7 +36,7 @@ #include "chip.h" #include "arm_internal.h" -#include "stm32l4.h" +#include "stm32.h" #include "stm32l4r9ai-disco.h" #ifndef CONFIG_ARCH_LEDS @@ -89,11 +89,11 @@ static void led_pm_notify(struct pm_callback_s *cb, int domain, { /* Restore normal LEDs operation */ - /* stm32l4_gpiowrite(GPIO_LED_RED, + /* stm32_gpiowrite(GPIO_LED_RED, * (ledset & BOARD_LED_RED_BIT) != 0); */ - /* stm32l4_gpiowrite(GPIO_LED_GRN, + /* stm32_gpiowrite(GPIO_LED_GRN, * (ledset & BOARD_LED_GRN_BIT) != 0); */ } @@ -103,8 +103,8 @@ static void led_pm_notify(struct pm_callback_s *cb, int domain, { /* Entering IDLE mode - Turn leds off */ - stm32l4_gpiowrite(GPIO_LED_RED, 0); - stm32l4_gpiowrite(GPIO_LED_GRN, 0); + stm32_gpiowrite(GPIO_LED_RED, 0); + stm32_gpiowrite(GPIO_LED_GRN, 0); } break; @@ -112,8 +112,8 @@ static void led_pm_notify(struct pm_callback_s *cb, int domain, { /* Entering STANDBY mode - Logic for PM_STANDBY goes here */ - stm32l4_gpiowrite(GPIO_LED_RED, 0); - stm32l4_gpiowrite(GPIO_LED_GRN, 0); + stm32_gpiowrite(GPIO_LED_RED, 0); + stm32_gpiowrite(GPIO_LED_GRN, 0); } break; @@ -121,8 +121,8 @@ static void led_pm_notify(struct pm_callback_s *cb, int domain, { /* Entering SLEEP mode - Logic for PM_SLEEP goes here */ - stm32l4_gpiowrite(GPIO_LED_RED, 0); - stm32l4_gpiowrite(GPIO_LED_GRN, 0); + stm32_gpiowrite(GPIO_LED_RED, 0); + stm32_gpiowrite(GPIO_LED_GRN, 0); } break; @@ -171,8 +171,8 @@ uint32_t board_userled_initialize(void) { /* Configure LD4,5 GPIO for output */ - stm32l4_configgpio(GPIO_LED_RED); - stm32l4_configgpio(GPIO_LED_GRN); + stm32_configgpio(GPIO_LED_RED); + stm32_configgpio(GPIO_LED_GRN); return BOARD_NLEDS; } @@ -185,11 +185,11 @@ void board_userled(int led, bool ledon) switch (led) { case BOARD_LED_RED: - stm32l4_gpiowrite(GPIO_LED_RED, ledon); + stm32_gpiowrite(GPIO_LED_RED, ledon); break; case BOARD_LED_GRN: - stm32l4_gpiowrite(GPIO_LED_GRN, ledon); + stm32_gpiowrite(GPIO_LED_GRN, ledon); break; } } @@ -200,8 +200,8 @@ void board_userled(int led, bool ledon) void board_userled_all(uint32_t ledset) { - stm32l4_gpiowrite(GPIO_LED_RED, (ledset & BOARD_LED_RED_BIT) != 0); - stm32l4_gpiowrite(GPIO_LED_GRN, (ledset & BOARD_LED_GRN_BIT) != 0); + stm32_gpiowrite(GPIO_LED_RED, (ledset & BOARD_LED_RED_BIT) != 0); + stm32_gpiowrite(GPIO_LED_GRN, (ledset & BOARD_LED_GRN_BIT) != 0); } /**************************************************************************** diff --git a/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32l4r9ai-disco.h b/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32l4r9ai-disco.h index b3e2fa0db7fb8..8c23f52d0f041 100644 --- a/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32l4r9ai-disco.h +++ b/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32l4r9ai-disco.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32L4_STM32L4R9AI_DISCO_SRC_STM32L4R9AI_DISCO_H -#define __BOARDS_ARM_STM32L4_STM32L4R9AI_DISCO_SRC_STM32L4R9AI_DISCO_H +#ifndef __BOARDS_ARM_STM32_STM32L4R9AI_DISCO_SRC_STM32L4R9AI_DISCO_H +#define __BOARDS_ARM_STM32_STM32L4R9AI_DISCO_SRC_STM32L4R9AI_DISCO_H /**************************************************************************** * Included Files @@ -67,7 +67,7 @@ /* Can't support USB host or device features if USB OTG FS is not enabled */ -#ifndef CONFIG_STM32L4_OTGFS +#ifndef CONFIG_STM32_OTGFS # undef HAVE_USBDEV # undef HAVE_USBHOST #endif @@ -188,10 +188,10 @@ /* Global driver instances */ -#ifdef CONFIG_STM32L4_SPI1 +#ifdef CONFIG_STM32_SPI1 extern struct spi_dev_s *g_spi1; #endif -#ifdef CONFIG_STM32L4_SPI2 +#ifdef CONFIG_STM32_SPI2 extern struct spi_dev_s *g_spi2; #endif @@ -213,36 +213,36 @@ extern struct spi_dev_s *g_spi2; int stm32_bringup(void); /**************************************************************************** - * Name: stm32l4_adc_setup + * Name: stm32_adc_setup * * Description: * Initialize ADC and register the ADC driver. * ****************************************************************************/ -int stm32l4_adc_setup(void); +int stm32_adc_setup(void); /**************************************************************************** - * Name: stm32l4_adc_measure_voltages + * Name: stm32_adc_measure_voltages * * Description: * Read internal reference voltage, internal VBAT and one external voltage. * ****************************************************************************/ -int stm32l4_adc_measure_voltages(uint32_t *vrefint, +int stm32_adc_measure_voltages(uint32_t *vrefint, uint32_t *vbat, uint32_t *vext); /**************************************************************************** - * Name: stm32l4_dac_setup + * Name: stm32_dac_setup * * Description: * Initialize DAC and register the DAC driver. * ****************************************************************************/ -int stm32l4_dac_setup(void); +int stm32_dac_setup(void); /**************************************************************************** * Name: stm32_dfsdm_setup @@ -252,7 +252,7 @@ int stm32l4_dac_setup(void); * ****************************************************************************/ -#if defined(CONFIG_ADC) && defined(CONFIG_STM32L4_DFSDM) +#if defined(CONFIG_ADC) && defined(CONFIG_STM32_DFSDM) int stm32_dfsdm_setup(void); #endif @@ -267,13 +267,13 @@ int stm32_dfsdm_setup(void); void stm32_spiinitialize(void); /**************************************************************************** - * Name: stm32l4_usbinitialize + * Name: stm32_usbinitialize * * Description: * Called to setup USB-related GPIO pins. * ****************************************************************************/ -void stm32l4_usbinitialize(void); +void stm32_usbinitialize(void); -#endif /* __BOARDS_ARM_STM32L4_STM32L4R9AI_DISCO_SRC_STM32L4R9AI_DISCO_H */ +#endif /* __BOARDS_ARM_STM32_STM32L4R9AI_DISCO_SRC_STM32L4R9AI_DISCO_H */ diff --git a/boards/arm/stm32l5/common/CMakeLists.txt b/boards/arm/stm32l5/common/CMakeLists.txt new file mode 100644 index 0000000000000..98744875f50f2 --- /dev/null +++ b/boards/arm/stm32l5/common/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32l5/common/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(${NUTTX_DIR}/boards/arm/common/stm32 stm32_common) diff --git a/boards/arm/stm32l5/common/Makefile b/boards/arm/stm32l5/common/Makefile new file mode 100644 index 0000000000000..263bee9b75e73 --- /dev/null +++ b/boards/arm/stm32l5/common/Makefile @@ -0,0 +1,36 @@ +############################################################################# +# boards/arm/stm32l5/common/Makefile +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################# + +include $(TOPDIR)/Make.defs + +STM32_BOARD_COMMON_DIR := $(TOPDIR)$(DELIM)boards$(DELIM)arm$(DELIM)common$(DELIM)stm32 + +include board/Make.defs +include $(STM32_BOARD_COMMON_DIR)$(DELIM)src$(DELIM)Make.defs + +DEPPATH += --dep-path board + +include $(TOPDIR)/boards/Board.mk + +ARCHSRCDIR = $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src +BOARDDIR = $(ARCHSRCDIR)$(DELIM)board +CFLAGS += ${INCDIR_PREFIX}$(BOARDDIR)$(DELIM)include diff --git a/boards/arm/stm32l5/nucleo-l552ze/configs/nsh/defconfig b/boards/arm/stm32l5/nucleo-l552ze/configs/nsh/defconfig index 14235ae113610..f92e3c47ba9e2 100644 --- a/boards/arm/stm32l5/nucleo-l552ze/configs/nsh/defconfig +++ b/boards/arm/stm32l5/nucleo-l552ze/configs/nsh/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH_BOARD="nucleo-l552ze" CONFIG_ARCH_BOARD_NUCLEO_L552ZE=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32l5" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32L552ZE=y CONFIG_ARCH_CHIP_STM32L5=y CONFIG_ARCH_INTERRUPTSTACK=2048 @@ -49,9 +50,9 @@ CONFIG_READLINE_TABCOMPLETION=y CONFIG_RR_INTERVAL=200 CONFIG_SCHED_WAITPID=y CONFIG_STACK_COLORATION=y -CONFIG_STM32L5_LPUART1=y -CONFIG_STM32L5_RTC=y -CONFIG_STM32L5_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY=y +CONFIG_STM32_LPUART1=y +CONFIG_STM32_RTC=y +CONFIG_STM32_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY=y CONFIG_SYSTEM_NSH=y CONFIG_SYSTEM_STACKMONITOR=y CONFIG_SYSTEM_TEE=y diff --git a/boards/arm/stm32l5/nucleo-l552ze/include/board.h b/boards/arm/stm32l5/nucleo-l552ze/include/board.h index 1cea1f1689eea..7b8d6d255d865 100644 --- a/boards/arm/stm32l5/nucleo-l552ze/include/board.h +++ b/boards/arm/stm32l5/nucleo-l552ze/include/board.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32L5_NUCLEO_L552ZE_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32L5_NUCLEO_L552ZE_INCLUDE_BOARD_H +#ifndef __BOARDS_ARM_STM32_NUCLEO_L552ZE_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32_NUCLEO_L552ZE_INCLUDE_BOARD_H /**************************************************************************** * Included Files @@ -45,16 +45,16 @@ * * System Clock source : PLL (MSI) * SYSCLK(Hz) : 110000000 Determined by PLL configuration - * HCLK(Hz) : 110000000 (STM32L5_RCC_CFGR_HPRE) (Max 110MHz) - * AHB Prescaler : 1 (STM32L5_RCC_CFGR_HPRE) (Max 110MHz) - * APB1 Prescaler : 1 (STM32L5_RCC_CFGR_PPRE1) (Max 110MHz) - * APB2 Prescaler : 1 (STM32L5_RCC_CFGR_PPRE2) (Max 110MHz) + * HCLK(Hz) : 110000000 (STM32_RCC_CFGR_HPRE) (Max 110MHz) + * AHB Prescaler : 1 (STM32_RCC_CFGR_HPRE) (Max 110MHz) + * APB1 Prescaler : 1 (STM32_RCC_CFGR_PPRE1) (Max 110MHz) + * APB2 Prescaler : 1 (STM32_RCC_CFGR_PPRE2) (Max 110MHz) * MSI Frequency(Hz) : 4000000 (nominal) - * PLLM : 1 (STM32L5_PLLCFG_PLLM) - * PLLN : 55 (STM32L5_PLLCFG_PLLN) - * PLLP : 0 (STM32L5_PLLCFG_PLLP) - * PLLQ : 0 (STM32L5_PLLCFG_PLLQ) - * PLLR : 2 (STM32L5_PLLCFG_PLLR) + * PLLM : 1 (STM32_PLLCFG_PLLM) + * PLLN : 55 (STM32_PLLCFG_PLLN) + * PLLP : 0 (STM32_PLLCFG_PLLP) + * PLLQ : 0 (STM32_PLLCFG_PLLQ) + * PLLR : 2 (STM32_PLLCFG_PLLR) * Flash Latency(WS) : 5 */ @@ -65,84 +65,84 @@ * LSE - 32.768 kHz installed */ -#define STM32L5_HSI_FREQUENCY 16000000ul -#define STM32L5_LSI_FREQUENCY 32000 -#define STM32L5_LSE_FREQUENCY 32768 +#define STM32_HSI_FREQUENCY 16000000ul +#define STM32_LSI_FREQUENCY 32000 +#define STM32_LSE_FREQUENCY 32768 -#define STM32L5_BOARD_USEMSI 1 -#define STM32L5_BOARD_MSIRANGE RCC_CR_MSIRANGE_4M +#define STM32_BOARD_USEMSI 1 +#define STM32_BOARD_MSIRANGE RCC_CR_MSIRANGE_4M /* prescaler common to all PLL inputs */ -#define STM32L5_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) /* 'main' PLL config; we use this to generate our system clock */ -#define STM32L5_PLLCFG_PLLN RCC_PLLCFG_PLLN(55) -#define STM32L5_PLLCFG_PLLP 0 -#undef STM32L5_PLLCFG_PLLP_ENABLED -#define STM32L5_PLLCFG_PLLQ 0 -#undef STM32L5_PLLCFG_PLLQ_ENABLED -#define STM32L5_PLLCFG_PLLR RCC_PLLCFG_PLLR_2 -#define STM32L5_PLLCFG_PLLR_ENABLED +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(55) +#define STM32_PLLCFG_PLLP 0 +#undef STM32_PLLCFG_PLLP_ENABLED +#define STM32_PLLCFG_PLLQ 0 +#undef STM32_PLLCFG_PLLQ_ENABLED +#define STM32_PLLCFG_PLLR RCC_PLLCFG_PLLR_2 +#define STM32_PLLCFG_PLLR_ENABLED /* 'SAIPLL1' is not used in this application */ -#define STM32L5_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(24) -#define STM32L5_PLLSAI1CFG_PLLP 0 -#undef STM32L5_PLLSAI1CFG_PLLP_ENABLED -#define STM32L5_PLLSAI1CFG_PLLQ 0 -#undef STM32L5_PLLSAI1CFG_PLLQ_ENABLED -#define STM32L5_PLLSAI1CFG_PLLR 0 -#undef STM32L5_PLLSAI1CFG_PLLR_ENABLED +#define STM32_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(24) +#define STM32_PLLSAI1CFG_PLLP 0 +#undef STM32_PLLSAI1CFG_PLLP_ENABLED +#define STM32_PLLSAI1CFG_PLLQ 0 +#undef STM32_PLLSAI1CFG_PLLQ_ENABLED +#define STM32_PLLSAI1CFG_PLLR 0 +#undef STM32_PLLSAI1CFG_PLLR_ENABLED /* 'SAIPLL2' is not used in this application */ -#define STM32L5_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) -#define STM32L5_PLLSAI2CFG_PLLP 0 -#undef STM32L5_PLLSAI2CFG_PLLP_ENABLED -#define STM32L5_PLLSAI2CFG_PLLR 0 -#undef STM32L5_PLLSAI2CFG_PLLR_ENABLED +#define STM32_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) +#define STM32_PLLSAI2CFG_PLLP 0 +#undef STM32_PLLSAI2CFG_PLLP_ENABLED +#define STM32_PLLSAI2CFG_PLLR 0 +#undef STM32_PLLSAI2CFG_PLLR_ENABLED -#define STM32L5_SYSCLK_FREQUENCY 110000000ul +#define STM32_SYSCLK_FREQUENCY 110000000ul /* Enable CLK48; get it from HSI48 */ -#if defined(CONFIG_STM32L5_USBFS) || defined(CONFIG_STM32L5_RNG) -# define STM32L5_USE_CLK48 1 -# define STM32L5_CLK48_SEL RCC_CCIPR_CLK48SEL_HSI48 -# define STM32L5_HSI48_SYNCSRC SYNCSRC_NONE +#if defined(CONFIG_STM32_USBFS) || defined(CONFIG_STM32_RNG) +# define STM32_USE_CLK48 1 +# define STM32_CLK48_SEL RCC_CCIPR_CLK48SEL_HSI48 +# define STM32_HSI48_SYNCSRC SYNCSRC_NONE #endif /* Enable LSE (for the RTC and for MSI autotrimming) */ -#define STM32L5_USE_LSE 1 +#define STM32_USE_LSE 1 /* Configure the HCLK divisor (for the AHB bus, core, memory, and DMA */ -#define STM32L5_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ -#define STM32L5_HCLK_FREQUENCY STM32L5_SYSCLK_FREQUENCY +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY /* Configure the APB1 prescaler */ -#define STM32L5_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ -#define STM32L5_PCLK1_FREQUENCY (STM32L5_HCLK_FREQUENCY / 1) +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY / 1) -#define STM32L5_APB1_TIM2_CLKIN (STM32L5_PCLK1_FREQUENCY) -#define STM32L5_APB1_TIM3_CLKIN (STM32L5_PCLK1_FREQUENCY) -#define STM32L5_APB1_TIM4_CLKIN (STM32L5_PCLK1_FREQUENCY) -#define STM32L5_APB1_TIM5_CLKIN (STM32L5_PCLK1_FREQUENCY) -#define STM32L5_APB1_TIM6_CLKIN (STM32L5_PCLK1_FREQUENCY) -#define STM32L5_APB1_TIM7_CLKIN (STM32L5_PCLK1_FREQUENCY) +#define STM32_APB1_TIM2_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM5_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (STM32_PCLK1_FREQUENCY) /* Configure the APB2 prescaler */ -#define STM32L5_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ -#define STM32L5_PCLK2_FREQUENCY (STM32L5_HCLK_FREQUENCY / 1) +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ +#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY / 1) -#define STM32L5_APB2_TIM1_CLKIN (STM32L5_PCLK2_FREQUENCY) -#define STM32L5_APB2_TIM15_CLKIN (STM32L5_PCLK2_FREQUENCY) -#define STM32L5_APB2_TIM16_CLKIN (STM32L5_PCLK2_FREQUENCY) +#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM15_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM16_CLKIN (STM32_PCLK2_FREQUENCY) /* The timer clock frequencies are automatically defined by hardware. If the * APB prescaler equals 1, the timer clock frequencies are set to the same @@ -150,17 +150,17 @@ * Note: TIM1,15,16 are on APB2, others on APB1 */ -#define BOARD_TIM1_FREQUENCY STM32L5_HCLK_FREQUENCY -#define BOARD_TIM2_FREQUENCY STM32L5_HCLK_FREQUENCY -#define BOARD_TIM3_FREQUENCY STM32L5_HCLK_FREQUENCY -#define BOARD_TIM4_FREQUENCY STM32L5_HCLK_FREQUENCY -#define BOARD_TIM5_FREQUENCY STM32L5_HCLK_FREQUENCY -#define BOARD_TIM6_FREQUENCY STM32L5_HCLK_FREQUENCY -#define BOARD_TIM7_FREQUENCY STM32L5_HCLK_FREQUENCY -#define BOARD_TIM15_FREQUENCY STM32L5_HCLK_FREQUENCY -#define BOARD_TIM16_FREQUENCY STM32L5_HCLK_FREQUENCY -#define BOARD_LPTIM1_FREQUENCY STM32L5_HCLK_FREQUENCY -#define BOARD_LPTIM2_FREQUENCY STM32L5_HCLK_FREQUENCY +#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM2_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM3_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM4_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM5_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM6_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM7_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM15_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM16_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_LPTIM1_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_LPTIM2_FREQUENCY STM32_HCLK_FREQUENCY /* DMA Channel/Stream Selections ********************************************/ @@ -262,7 +262,7 @@ extern "C" ****************************************************************************/ /**************************************************************************** - * Name: stm32l5_board_initialize + * Name: stm32_board_initialize * * Description: * All STM32L5 architectures must provide the following entry point. @@ -272,7 +272,7 @@ extern "C" * ****************************************************************************/ -void stm32l5_board_initialize(void); +void stm32_board_initialize(void); #undef EXTERN #if defined(__cplusplus) @@ -280,4 +280,4 @@ void stm32l5_board_initialize(void); #endif #endif /* __ASSEMBLY__ */ -#endif /* __BOARDS_ARM_STM32L5_NUCLEO_L552ZE_INCLUDE_BOARD_H */ +#endif /* __BOARDS_ARM_STM32_NUCLEO_L552ZE_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32l5/nucleo-l552ze/src/Make.defs b/boards/arm/stm32l5/nucleo-l552ze/src/Make.defs new file mode 100644 index 0000000000000..ae55afd1c34b0 --- /dev/null +++ b/boards/arm/stm32l5/nucleo-l552ze/src/Make.defs @@ -0,0 +1,40 @@ +############################################################################## +# boards/arm/stm32l5/nucleo-l552ze/src/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################## + +-include $(TOPDIR)/Make.defs + +ASRCS = +CSRCS = stm32_boot.c stm32_bringup.c + +ifeq ($(CONFIG_ARCH_LEDS),y) +CSRCS += stm32_autoleds.c +else +CSRCS += stm32_userleds.c +endif + +ifeq ($(CONFIG_ARCH_BUTTONS),y) +CSRCS += stm32_buttons.c +endif + +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32l5/nucleo-l552ze/src/Makefile b/boards/arm/stm32l5/nucleo-l552ze/src/Makefile deleted file mode 100644 index 28cdefc9f468d..0000000000000 --- a/boards/arm/stm32l5/nucleo-l552ze/src/Makefile +++ /dev/null @@ -1,38 +0,0 @@ -############################################################################## -# boards/arm/stm32l5/nucleo-l552ze/src/Makefile -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################## - --include $(TOPDIR)/Make.defs - -ASRCS = -CSRCS = stm32_boot.c stm32_bringup.c - -ifeq ($(CONFIG_ARCH_LEDS),y) -CSRCS += stm32_autoleds.c -else -CSRCS += stm32_userleds.c -endif - -ifeq ($(CONFIG_ARCH_BUTTONS),y) -CSRCS += stm32_buttons.c -endif - -include $(TOPDIR)/boards/Board.mk diff --git a/boards/arm/stm32l5/nucleo-l552ze/src/nucleo-l552ze.h b/boards/arm/stm32l5/nucleo-l552ze/src/nucleo-l552ze.h index 847c837138c33..bc0eaf8ef96fb 100644 --- a/boards/arm/stm32l5/nucleo-l552ze/src/nucleo-l552ze.h +++ b/boards/arm/stm32l5/nucleo-l552ze/src/nucleo-l552ze.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32L5_NUCLEO_L552ZE_SRC_NUCLEO_L552ZE_H -#define __BOARDS_ARM_STM32L5_NUCLEO_L552ZE_SRC_NUCLEO_L552ZE_H +#ifndef __BOARDS_ARM_STM32_NUCLEO_L552ZE_SRC_NUCLEO_L552ZE_H +#define __BOARDS_ARM_STM32_NUCLEO_L552ZE_SRC_NUCLEO_L552ZE_H /**************************************************************************** * Included Files @@ -116,4 +116,4 @@ int stm32_bringup(void); #endif /* __ASSEMBLY__ */ -#endif /* __BOARDS_ARM_STM32L5_NUCLEO_L552ZE_SRC_NUCLEO_L552ZE_H */ +#endif /* __BOARDS_ARM_STM32_NUCLEO_L552ZE_SRC_NUCLEO_L552ZE_H */ diff --git a/boards/arm/stm32l5/nucleo-l552ze/src/stm32_autoleds.c b/boards/arm/stm32l5/nucleo-l552ze/src/stm32_autoleds.c index 012f7938fbd00..f27e0286dd99f 100644 --- a/boards/arm/stm32l5/nucleo-l552ze/src/stm32_autoleds.c +++ b/boards/arm/stm32l5/nucleo-l552ze/src/stm32_autoleds.c @@ -64,7 +64,7 @@ static void phy_set_led(int led, bool state) { /* Active High */ - stm32l5_gpiowrite(g_ledmap[led], state); + stm32_gpiowrite(g_ledmap[led], state); } /**************************************************************************** @@ -83,7 +83,7 @@ void board_autoled_initialize(void) for (i = 0; i < nitems(g_ledmap); i++) { - stm32l5_configgpio(g_ledmap[i]); + stm32_configgpio(g_ledmap[i]); } } diff --git a/boards/arm/stm32l5/nucleo-l552ze/src/stm32_boot.c b/boards/arm/stm32l5/nucleo-l552ze/src/stm32_boot.c index 05cd210fce068..7ba2e3c8fab64 100644 --- a/boards/arm/stm32l5/nucleo-l552ze/src/stm32_boot.c +++ b/boards/arm/stm32l5/nucleo-l552ze/src/stm32_boot.c @@ -42,7 +42,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32l5_board_initialize + * Name: stm32_board_initialize * * Description: * All STM32 architectures must provide the following entry point. This @@ -52,18 +52,18 @@ * ****************************************************************************/ -void stm32l5_board_initialize(void) +void stm32_board_initialize(void) { - stm32l5_pwr_vddio2_valid(true); + stm32_pwr_vddio2_valid(true); -#if defined(CONFIG_STM32L5_LPUART1) +#if defined(CONFIG_STM32_LPUART1) /* LPUART1 uses PG7/PG8 which are powered by VDDIO2. The GPIO config in - * stm32l5_lowsetup() runs before VDDIO2 is enabled, so GPIOG writes + * stm32_lowsetup() runs before VDDIO2 is enabled, so GPIOG writes * silently fail. Reconfigure here after VDDIO2 is valid. */ - stm32l5_configgpio(GPIO_LPUART1_TX); - stm32l5_configgpio(GPIO_LPUART1_RX); + stm32_configgpio(GPIO_LPUART1_TX); + stm32_configgpio(GPIO_LPUART1_RX); #endif #ifdef CONFIG_ARCH_LEDS diff --git a/boards/arm/stm32l5/nucleo-l552ze/src/stm32_buttons.c b/boards/arm/stm32l5/nucleo-l552ze/src/stm32_buttons.c index 0ade669c51194..429c818dd1156 100644 --- a/boards/arm/stm32l5/nucleo-l552ze/src/stm32_buttons.c +++ b/boards/arm/stm32l5/nucleo-l552ze/src/stm32_buttons.c @@ -61,7 +61,7 @@ uint32_t board_button_initialize(void) * also configured for the pin. */ - stm32l5_configgpio(GPIO_BTN_USER); + stm32_configgpio(GPIO_BTN_USER); return NUM_BUTTONS; } @@ -73,7 +73,7 @@ uint32_t board_buttons(void) { /* Check the state of the USER button. */ - return stm32l5_gpioread(GPIO_BTN_USER) ? BUTTON_USER_BIT : 0; + return stm32_gpioread(GPIO_BTN_USER) ? BUTTON_USER_BIT : 0; } /**************************************************************************** @@ -105,7 +105,7 @@ int board_button_irq(int id, xcpt_t irqhandler, void *arg) if (id == BUTTON_USER) { - ret = stm32l5_gpiosetevent(GPIO_BTN_USER, true, true, true, irqhandler, + ret = stm32_gpiosetevent(GPIO_BTN_USER, true, true, true, irqhandler, arg); } diff --git a/boards/arm/stm32l5/nucleo-l552ze/src/stm32_userleds.c b/boards/arm/stm32l5/nucleo-l552ze/src/stm32_userleds.c index f13c4b5f62766..8318cb30f2cc5 100644 --- a/boards/arm/stm32l5/nucleo-l552ze/src/stm32_userleds.c +++ b/boards/arm/stm32l5/nucleo-l552ze/src/stm32_userleds.c @@ -77,7 +77,7 @@ uint32_t board_userled_initialize(void) for (i = 0; i < nitems(g_ledcfg); i++) { - stm32l5_configgpio(g_ledcfg[i]); + stm32_configgpio(g_ledcfg[i]); } return BOARD_NLEDS; @@ -97,7 +97,7 @@ void board_userled(int led, bool ledon) { if ((unsigned)led < nitems(g_ledcfg)) { - stm32l5_gpiowrite(g_ledcfg[led], ledon); + stm32_gpiowrite(g_ledcfg[led], ledon); } } @@ -119,7 +119,7 @@ void board_userled_all(uint32_t ledset) for (i = 0; i < nitems(g_ledcfg); i++) { - stm32l5_gpiowrite(g_ledcfg[i], (ledset & (1 << i)) != 0); + stm32_gpiowrite(g_ledcfg[i], (ledset & (1 << i)) != 0); } } diff --git a/boards/arm/stm32l5/stm32l562e-dk/configs/nsh/defconfig b/boards/arm/stm32l5/stm32l562e-dk/configs/nsh/defconfig index 2edfa787c5e64..6f19b7f98747e 100644 --- a/boards/arm/stm32l5/stm32l562e-dk/configs/nsh/defconfig +++ b/boards/arm/stm32l5/stm32l562e-dk/configs/nsh/defconfig @@ -10,9 +10,10 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32l562e-dk" CONFIG_ARCH_BOARD_STM32L562E_DK=y -CONFIG_ARCH_BOARD_STM32L5_CUSTOM_CLOCKCONFIG=y +CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32l5" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32L562QE=y CONFIG_ARCH_CHIP_STM32L5=y CONFIG_ARCH_INTERRUPTSTACK=2048 @@ -44,7 +45,7 @@ CONFIG_READLINE_TABCOMPLETION=y CONFIG_RR_INTERVAL=200 CONFIG_SCHED_WAITPID=y CONFIG_STACK_COLORATION=y -CONFIG_STM32L5_USART1=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_SYSTEM_STACKMONITOR=y CONFIG_SYSTEM_TEE=y diff --git a/boards/arm/stm32l5/stm32l562e-dk/include/board.h b/boards/arm/stm32l5/stm32l562e-dk/include/board.h index 395095c7b9c3e..ec882f5582b2e 100644 --- a/boards/arm/stm32l5/stm32l562e-dk/include/board.h +++ b/boards/arm/stm32l5/stm32l562e-dk/include/board.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32L5_STM32L562E_DK_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32L5_STM32L562E_DK_INCLUDE_BOARD_H +#ifndef __BOARDS_ARM_STM32_STM32L562E_DK_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32_STM32L562E_DK_INCLUDE_BOARD_H /**************************************************************************** * Included Files @@ -67,15 +67,15 @@ * LSE - 32.768 kHz installed */ -#define STM32L5_HSI_FREQUENCY 16000000ul -#define STM32L5_LSI_FREQUENCY 32000 -#define STM32L5_MSI_FREQUENCY 4000000ul -#define STM32L5_LSE_FREQUENCY 32768 +#define STM32_HSI_FREQUENCY 16000000ul +#define STM32_LSI_FREQUENCY 32000 +#define STM32_MSI_FREQUENCY 4000000ul +#define STM32_LSE_FREQUENCY 32768 -#define STM32L5_SYSCLK_FREQUENCY 110000000ul -#define STM32L5_HCLK_FREQUENCY STM32L5_SYSCLK_FREQUENCY -#define STM32L5_PCLK1_FREQUENCY STM32L5_HCLK_FREQUENCY -#define STM32L5_PCLK2_FREQUENCY (STM32L5_HCLK_FREQUENCY / 1) +#define STM32_SYSCLK_FREQUENCY 110000000ul +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY +#define STM32_PCLK1_FREQUENCY STM32_HCLK_FREQUENCY +#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY / 1) /* The timer clock frequencies are automatically defined by hardware. If the * APB prescaler equals 1, the timer clock frequencies are set to the same @@ -83,17 +83,17 @@ * Note: TIM1,15,16 are on APB2, others on APB1 */ -#define BOARD_TIM1_FREQUENCY STM32L5_HCLK_FREQUENCY -#define BOARD_TIM2_FREQUENCY STM32L5_HCLK_FREQUENCY -#define BOARD_TIM3_FREQUENCY STM32L5_HCLK_FREQUENCY -#define BOARD_TIM4_FREQUENCY STM32L5_HCLK_FREQUENCY -#define BOARD_TIM5_FREQUENCY STM32L5_HCLK_FREQUENCY -#define BOARD_TIM6_FREQUENCY STM32L5_HCLK_FREQUENCY -#define BOARD_TIM7_FREQUENCY STM32L5_HCLK_FREQUENCY -#define BOARD_TIM15_FREQUENCY STM32L5_HCLK_FREQUENCY -#define BOARD_TIM16_FREQUENCY STM32L5_HCLK_FREQUENCY -#define BOARD_LPTIM1_FREQUENCY STM32L5_HCLK_FREQUENCY -#define BOARD_LPTIM2_FREQUENCY STM32L5_HCLK_FREQUENCY +#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM2_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM3_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM4_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM5_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM6_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM7_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM15_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM16_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_LPTIM1_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_LPTIM2_FREQUENCY STM32_HCLK_FREQUENCY /* DMA Channel/Stream Selections ********************************************/ @@ -185,7 +185,7 @@ extern "C" ****************************************************************************/ /**************************************************************************** - * Name: stm32l5_board_initialize + * Name: stm32_board_initialize * * Description: * All STM32L5 architectures must provide the following entry point. @@ -195,7 +195,7 @@ extern "C" * ****************************************************************************/ -void stm32l5_board_initialize(void); +void stm32_board_initialize(void); #undef EXTERN #if defined(__cplusplus) @@ -203,4 +203,4 @@ void stm32l5_board_initialize(void); #endif #endif /* __ASSEMBLY__ */ -#endif /* __BOARDS_ARM_STM32L5_STM32L562E_DK_INCLUDE_BOARD_H */ +#endif /* __BOARDS_ARM_STM32_STM32L562E_DK_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32l5/stm32l562e-dk/src/Make.defs b/boards/arm/stm32l5/stm32l562e-dk/src/Make.defs new file mode 100644 index 0000000000000..b0fef85b2252f --- /dev/null +++ b/boards/arm/stm32l5/stm32l562e-dk/src/Make.defs @@ -0,0 +1,40 @@ +############################################################################## +# boards/arm/stm32l5/stm32l562e-dk/src/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################## + +-include $(TOPDIR)/Make.defs + +ASRCS = +CSRCS = stm32_boot.c stm32_bringup.c stm32_clockconfig.c + +ifeq ($(CONFIG_ARCH_LEDS),y) +CSRCS += stm32_autoleds.c +else +CSRCS += stm32_userleds.c +endif + +ifeq ($(CONFIG_ARCH_BUTTONS),y) +CSRCS += stm32_buttons.c +endif + +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32l5/stm32l562e-dk/src/Makefile b/boards/arm/stm32l5/stm32l562e-dk/src/Makefile deleted file mode 100644 index aa38e15db504a..0000000000000 --- a/boards/arm/stm32l5/stm32l562e-dk/src/Makefile +++ /dev/null @@ -1,38 +0,0 @@ -############################################################################## -# boards/arm/stm32l5/stm32l562e-dk/src/Makefile -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################## - --include $(TOPDIR)/Make.defs - -ASRCS = -CSRCS = stm32_boot.c stm32_bringup.c stm32_clockconfig.c - -ifeq ($(CONFIG_ARCH_LEDS),y) -CSRCS += stm32_autoleds.c -else -CSRCS += stm32_userleds.c -endif - -ifeq ($(CONFIG_ARCH_BUTTONS),y) -CSRCS += stm32_buttons.c -endif - -include $(TOPDIR)/boards/Board.mk diff --git a/boards/arm/stm32l5/stm32l562e-dk/src/stm32_autoleds.c b/boards/arm/stm32l5/stm32l562e-dk/src/stm32_autoleds.c index 0206ca6ca4877..4d3dd8249468f 100644 --- a/boards/arm/stm32l5/stm32l562e-dk/src/stm32_autoleds.c +++ b/boards/arm/stm32l5/stm32l562e-dk/src/stm32_autoleds.c @@ -63,7 +63,7 @@ static void phy_set_led(int led, bool state) { /* Active Low */ - stm32l5_gpiowrite(g_ledmap[led], !state); + stm32_gpiowrite(g_ledmap[led], !state); } /**************************************************************************** @@ -82,7 +82,7 @@ void board_autoled_initialize(void) for (i = 0; i < nitems(g_ledmap); i++) { - stm32l5_configgpio(g_ledmap[i]); + stm32_configgpio(g_ledmap[i]); } } diff --git a/boards/arm/stm32l5/stm32l562e-dk/src/stm32_boot.c b/boards/arm/stm32l5/stm32l562e-dk/src/stm32_boot.c index 9f40e9807a750..458aab5873360 100644 --- a/boards/arm/stm32l5/stm32l562e-dk/src/stm32_boot.c +++ b/boards/arm/stm32l5/stm32l562e-dk/src/stm32_boot.c @@ -41,7 +41,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32l5_board_initialize + * Name: stm32_board_initialize * * Description: * All STM32 architectures must provide the following entry point. This @@ -51,7 +51,7 @@ * ****************************************************************************/ -void stm32l5_board_initialize(void) +void stm32_board_initialize(void) { /* On the STM32L562E-DK Vddio2 is supplied by Vdd_mcu. Thus, when the MCU * is running Vddio2 is guaranteed to be valid. LED LD10 is driven by @@ -59,7 +59,7 @@ void stm32l5_board_initialize(void) * Vddio2 to be valid here. */ - stm32l5_pwr_vddio2_valid(true); + stm32_pwr_vddio2_valid(true); #ifdef CONFIG_ARCH_LEDS /* Configure on-board LEDs if LED support has been selected. */ diff --git a/boards/arm/stm32l5/stm32l562e-dk/src/stm32_buttons.c b/boards/arm/stm32l5/stm32l562e-dk/src/stm32_buttons.c index 133fb020e88cb..3091f1790814c 100644 --- a/boards/arm/stm32l5/stm32l562e-dk/src/stm32_buttons.c +++ b/boards/arm/stm32l5/stm32l562e-dk/src/stm32_buttons.c @@ -61,7 +61,7 @@ uint32_t board_button_initialize(void) * also configured for the pin. */ - stm32l5_configgpio(GPIO_BTN_USER); + stm32_configgpio(GPIO_BTN_USER); return NUM_BUTTONS; } @@ -73,7 +73,7 @@ uint32_t board_buttons(void) { /* Check the state of the USER button. */ - return stm32l5_gpioread(GPIO_BTN_USER) ? BUTTON_USER_BIT : 0; + return stm32_gpioread(GPIO_BTN_USER) ? BUTTON_USER_BIT : 0; } /**************************************************************************** @@ -105,7 +105,7 @@ int board_button_irq(int id, xcpt_t irqhandler, void *arg) if (id == BUTTON_USER) { - ret = stm32l5_gpiosetevent(GPIO_BTN_USER, true, true, true, irqhandler, + ret = stm32_gpiosetevent(GPIO_BTN_USER, true, true, true, irqhandler, arg); } diff --git a/boards/arm/stm32l5/stm32l562e-dk/src/stm32_clockconfig.c b/boards/arm/stm32l5/stm32l562e-dk/src/stm32_clockconfig.c index 170aab2fe92d9..79ba04835ac3b 100644 --- a/boards/arm/stm32l5/stm32l562e-dk/src/stm32_clockconfig.c +++ b/boards/arm/stm32l5/stm32l562e-dk/src/stm32_clockconfig.c @@ -37,14 +37,14 @@ * Currently the STM32L562E-DK board support is restricted to running NuttX * in the Non-Secure domain together with TrustedFirmware-M (TFM). In this * setup the clock configuration is done by TFM, not by NuttX. Thus, the - * board's configuration sets CONFIG_ARCH_BOARD_STM32L5_CUSTOM_CLOCKCONFIG + * board's configuration sets CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG * to avoid the standard clock config logic to run and instead do just * nothing in this function. * ****************************************************************************/ -#if defined(CONFIG_ARCH_BOARD_STM32L5_CUSTOM_CLOCKCONFIG) -void stm32l5_board_clockconfig(void) +#if defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) +void stm32_board_clockconfig(void) { } #endif diff --git a/boards/arm/stm32l5/stm32l562e-dk/src/stm32_userleds.c b/boards/arm/stm32l5/stm32l562e-dk/src/stm32_userleds.c index 97342f1dfe8a6..fa01c25726108 100644 --- a/boards/arm/stm32l5/stm32l562e-dk/src/stm32_userleds.c +++ b/boards/arm/stm32l5/stm32l562e-dk/src/stm32_userleds.c @@ -76,7 +76,7 @@ uint32_t board_userled_initialize(void) for (i = 0; i < nitems(g_ledcfg); i++) { - stm32l5_configgpio(g_ledcfg[i]); + stm32_configgpio(g_ledcfg[i]); } return BOARD_NLEDS; @@ -96,7 +96,7 @@ void board_userled(int led, bool ledon) { if ((unsigned)led < nitems(g_ledcfg)) { - stm32l5_gpiowrite(g_ledcfg[led], !ledon); + stm32_gpiowrite(g_ledcfg[led], !ledon); } } @@ -118,7 +118,7 @@ void board_userled_all(uint32_t ledset) for (i = 0; i < nitems(g_ledcfg); i++) { - stm32l5_gpiowrite(g_ledcfg[i], !(ledset & (1 << i))); + stm32_gpiowrite(g_ledcfg[i], !(ledset & (1 << i))); } } diff --git a/boards/arm/stm32l5/stm32l562e-dk/src/stm32l562e-dk.h b/boards/arm/stm32l5/stm32l562e-dk/src/stm32l562e-dk.h index 1352d9c3d8f43..8f6006fb682f4 100644 --- a/boards/arm/stm32l5/stm32l562e-dk/src/stm32l562e-dk.h +++ b/boards/arm/stm32l5/stm32l562e-dk/src/stm32l562e-dk.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32L5_STM32L562E_DK_SRC_STM32L562E_DK_H -#define __BOARDS_ARM_STM32L5_STM32L562E_DK_SRC_STM32L562E_DK_H +#ifndef __BOARDS_ARM_STM32_STM32L562E_DK_SRC_STM32L562E_DK_H +#define __BOARDS_ARM_STM32_STM32L562E_DK_SRC_STM32L562E_DK_H /**************************************************************************** * Included Files @@ -113,4 +113,4 @@ int stm32_bringup(void); #endif /* __ASSEMBLY__ */ -#endif /* __BOARDS_ARM_STM32L5_STM32L562E_DK_SRC_STM32L562E_DK_H */ +#endif /* __BOARDS_ARM_STM32_STM32L562E_DK_SRC_STM32L562E_DK_H */ diff --git a/boards/arm/stm32n6/common/CMakeLists.txt b/boards/arm/stm32n6/common/CMakeLists.txt new file mode 100644 index 0000000000000..1a0aba1198dee --- /dev/null +++ b/boards/arm/stm32n6/common/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32n6/common/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(${NUTTX_DIR}/boards/arm/common/stm32 stm32_common) diff --git a/boards/arm/stm32n6/common/Makefile b/boards/arm/stm32n6/common/Makefile new file mode 100644 index 0000000000000..7026a5e5312d4 --- /dev/null +++ b/boards/arm/stm32n6/common/Makefile @@ -0,0 +1,36 @@ +############################################################################# +# boards/arm/stm32n6/common/Makefile +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################# + +include $(TOPDIR)/Make.defs + +STM32_BOARD_COMMON_DIR := $(TOPDIR)$(DELIM)boards$(DELIM)arm$(DELIM)common$(DELIM)stm32 + +include board/Make.defs +include $(STM32_BOARD_COMMON_DIR)$(DELIM)src$(DELIM)Make.defs + +DEPPATH += --dep-path board + +include $(TOPDIR)/boards/Board.mk + +ARCHSRCDIR = $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src +BOARDDIR = $(ARCHSRCDIR)$(DELIM)board +CFLAGS += ${INCDIR_PREFIX}$(BOARDDIR)$(DELIM)include diff --git a/boards/arm/stm32n6/nucleo-n657x0-q/configs/leds/defconfig b/boards/arm/stm32n6/nucleo-n657x0-q/configs/leds/defconfig index c5fb9d9dcbd32..91975793f411d 100644 --- a/boards/arm/stm32n6/nucleo-n657x0-q/configs/leds/defconfig +++ b/boards/arm/stm32n6/nucleo-n657x0-q/configs/leds/defconfig @@ -10,6 +10,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-n657x0-q" CONFIG_ARCH_BOARD_NUCLEO_N657X0_Q=y CONFIG_ARCH_CHIP="stm32n6" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32N657X0=y CONFIG_ARCH_CHIP_STM32N6=y CONFIG_ARCH_INTERRUPTSTACK=4096 @@ -30,7 +31,7 @@ CONFIG_RAM_START=0x34000400 CONFIG_RAW_BINARY=y CONFIG_RR_INTERVAL=200 CONFIG_SCHED_WAITPID=y -CONFIG_STM32N6_USART1=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_USART1_SERIAL_CONSOLE=y CONFIG_USERLED=y diff --git a/boards/arm/stm32n6/nucleo-n657x0-q/configs/nsh/defconfig b/boards/arm/stm32n6/nucleo-n657x0-q/configs/nsh/defconfig index f18c05e1d6240..0f35eb8c02444 100644 --- a/boards/arm/stm32n6/nucleo-n657x0-q/configs/nsh/defconfig +++ b/boards/arm/stm32n6/nucleo-n657x0-q/configs/nsh/defconfig @@ -9,6 +9,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-n657x0-q" CONFIG_ARCH_BOARD_NUCLEO_N657X0_Q=y CONFIG_ARCH_CHIP="stm32n6" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32N657X0=y CONFIG_ARCH_CHIP_STM32N6=y CONFIG_ARCH_INTERRUPTSTACK=4096 @@ -27,6 +28,6 @@ CONFIG_RAM_START=0x34000400 CONFIG_RAW_BINARY=y CONFIG_RR_INTERVAL=200 CONFIG_SCHED_WAITPID=y -CONFIG_STM32N6_USART1=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32n6/nucleo-n657x0-q/configs/ostest/defconfig b/boards/arm/stm32n6/nucleo-n657x0-q/configs/ostest/defconfig index 9e14513b6c7a4..772fa00937f52 100644 --- a/boards/arm/stm32n6/nucleo-n657x0-q/configs/ostest/defconfig +++ b/boards/arm/stm32n6/nucleo-n657x0-q/configs/ostest/defconfig @@ -9,6 +9,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-n657x0-q" CONFIG_ARCH_BOARD_NUCLEO_N657X0_Q=y CONFIG_ARCH_CHIP="stm32n6" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32N657X0=y CONFIG_ARCH_CHIP_STM32N6=y CONFIG_ARCH_INTERRUPTSTACK=4096 @@ -30,7 +31,7 @@ CONFIG_RR_INTERVAL=200 CONFIG_SCHED_CHILD_STATUS=y CONFIG_SCHED_HAVE_PARENT=y CONFIG_SCHED_WAITPID=y -CONFIG_STM32N6_USART1=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_TESTING_OSTEST=y CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32n6/nucleo-n657x0-q/include/board.h b/boards/arm/stm32n6/nucleo-n657x0-q/include/board.h index 997a4137f557e..18b7c879d3765 100644 --- a/boards/arm/stm32n6/nucleo-n657x0-q/include/board.h +++ b/boards/arm/stm32n6/nucleo-n657x0-q/include/board.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32N6_NUCLEO_N657X0_Q_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32N6_NUCLEO_N657X0_Q_INCLUDE_BOARD_H +#ifndef __BOARDS_ARM_STM32_NUCLEO_N657X0_Q_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32_NUCLEO_N657X0_Q_INCLUDE_BOARD_H /**************************************************************************** * Included Files @@ -181,4 +181,4 @@ void stm32_board_initialize(void); #endif #endif /* __ASSEMBLY__ */ -#endif /* __BOARDS_ARM_STM32N6_NUCLEO_N657X0_Q_INCLUDE_BOARD_H */ +#endif /* __BOARDS_ARM_STM32_NUCLEO_N657X0_Q_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32n6/nucleo-n657x0-q/src/Make.defs b/boards/arm/stm32n6/nucleo-n657x0-q/src/Make.defs new file mode 100644 index 0000000000000..794c50d1b24d1 --- /dev/null +++ b/boards/arm/stm32n6/nucleo-n657x0-q/src/Make.defs @@ -0,0 +1,36 @@ +############################################################################## +# boards/arm/stm32n6/nucleo-n657x0-q/src/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################## + +-include $(TOPDIR)/Make.defs + +ASRCS = +CSRCS = stm32_boot.c stm32_bringup.c + +ifeq ($(CONFIG_ARCH_LEDS),y) +CSRCS += stm32_autoleds.c +else +CSRCS += stm32_userleds.c +endif + +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32n6/nucleo-n657x0-q/src/Makefile b/boards/arm/stm32n6/nucleo-n657x0-q/src/Makefile deleted file mode 100644 index 74f826721e4f7..0000000000000 --- a/boards/arm/stm32n6/nucleo-n657x0-q/src/Makefile +++ /dev/null @@ -1,34 +0,0 @@ -############################################################################## -# boards/arm/stm32n6/nucleo-n657x0-q/src/Makefile -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################## - --include $(TOPDIR)/Make.defs - -ASRCS = -CSRCS = stm32_boot.c stm32_bringup.c - -ifeq ($(CONFIG_ARCH_LEDS),y) -CSRCS += stm32_autoleds.c -else -CSRCS += stm32_userleds.c -endif - -include $(TOPDIR)/boards/Board.mk diff --git a/boards/arm/stm32n6/nucleo-n657x0-q/src/nucleo-n657x0-q.h b/boards/arm/stm32n6/nucleo-n657x0-q/src/nucleo-n657x0-q.h index af0f6bfb37464..62bf8ff273633 100644 --- a/boards/arm/stm32n6/nucleo-n657x0-q/src/nucleo-n657x0-q.h +++ b/boards/arm/stm32n6/nucleo-n657x0-q/src/nucleo-n657x0-q.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32N6_NUCLEO_N657X0_Q_SRC_NUCLEO_N657X0_Q_H -#define __BOARDS_ARM_STM32N6_NUCLEO_N657X0_Q_SRC_NUCLEO_N657X0_Q_H +#ifndef __BOARDS_ARM_STM32_NUCLEO_N657X0_Q_SRC_NUCLEO_N657X0_Q_H +#define __BOARDS_ARM_STM32_NUCLEO_N657X0_Q_SRC_NUCLEO_N657X0_Q_H /**************************************************************************** * Included Files @@ -87,4 +87,4 @@ int stm32_bringup(void); #endif /* __ASSEMBLY__ */ -#endif /* __BOARDS_ARM_STM32N6_NUCLEO_N657X0_Q_SRC_NUCLEO_N657X0_Q_H */ +#endif /* __BOARDS_ARM_STM32_NUCLEO_N657X0_Q_SRC_NUCLEO_N657X0_Q_H */ diff --git a/boards/arm/stm32u5/b-u585i-iot02a/configs/nsh/defconfig b/boards/arm/stm32u5/b-u585i-iot02a/configs/nsh/defconfig index 74b6940237b58..eabf176d3fde5 100644 --- a/boards/arm/stm32u5/b-u585i-iot02a/configs/nsh/defconfig +++ b/boards/arm/stm32u5/b-u585i-iot02a/configs/nsh/defconfig @@ -11,6 +11,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="b-u585i-iot02a" CONFIG_ARCH_BOARD_B_U585I_IOT02A=y CONFIG_ARCH_CHIP="stm32u5" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32U585AI=y CONFIG_ARCH_CHIP_STM32U5=y CONFIG_ARCH_INTERRUPTSTACK=2048 @@ -45,10 +46,10 @@ CONFIG_READLINE_TABCOMPLETION=y CONFIG_RR_INTERVAL=200 CONFIG_SCHED_WAITPID=y CONFIG_STACK_COLORATION=y -CONFIG_STM32U5_PWR=y -CONFIG_STM32U5_SPI1=y -CONFIG_STM32U5_SRAM3=y -CONFIG_STM32U5_USART1=y +CONFIG_STM32_PWR=y +CONFIG_STM32_SPI1=y +CONFIG_STM32_SRAM3=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_SYSTEM_SPITOOL=y CONFIG_SYSTEM_STACKMONITOR=y diff --git a/boards/arm/stm32u5/b-u585i-iot02a/include/board.h b/boards/arm/stm32u5/b-u585i-iot02a/include/board.h index fc900c526b2d9..e0165c42c9d9e 100644 --- a/boards/arm/stm32u5/b-u585i-iot02a/include/board.h +++ b/boards/arm/stm32u5/b-u585i-iot02a/include/board.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32U5_B_U585I_IOT02A_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32U5_B_U585I_IOT02A_INCLUDE_BOARD_H +#ifndef __BOARDS_ARM_STM32_B_U585I_IOT02A_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32_B_U585I_IOT02A_INCLUDE_BOARD_H /**************************************************************************** * Included Files @@ -197,4 +197,4 @@ void stm32_board_initialize(void); #endif #endif /* __ASSEMBLY__ */ -#endif /* __BOARDS_ARM_STM32U5_B_U585I_IOT02A_INCLUDE_BOARD_H */ +#endif /* __BOARDS_ARM_STM32_B_U585I_IOT02A_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32u5/b-u585i-iot02a/src/CMakeLists.txt b/boards/arm/stm32u5/b-u585i-iot02a/src/CMakeLists.txt index a845f39aefe01..150aef2e64720 100644 --- a/boards/arm/stm32u5/b-u585i-iot02a/src/CMakeLists.txt +++ b/boards/arm/stm32u5/b-u585i-iot02a/src/CMakeLists.txt @@ -22,7 +22,7 @@ set(SRCS stm32_boot.c stm32_bringup.c stm32_spi.c) -if(CONFIG_ARCH_BOARD_STM32U5_CUSTOM_CLOCKCONFIG) +if(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) list(APPEND SRCS stm32_clockconfig.c) endif() diff --git a/boards/arm/stm32u5/b-u585i-iot02a/src/Make.defs b/boards/arm/stm32u5/b-u585i-iot02a/src/Make.defs new file mode 100644 index 0000000000000..f17f63d09794b --- /dev/null +++ b/boards/arm/stm32u5/b-u585i-iot02a/src/Make.defs @@ -0,0 +1,34 @@ +############################################################################## +# boards/arm/stm32u5/b-u585i-iot02a/src/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################## + +-include $(TOPDIR)/Make.defs + +ASRCS = +CSRCS = stm32_boot.c stm32_bringup.c stm32_spi.c + +ifeq ($(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG),y) +CSRCS += stm32_clockconfig.c +endif + +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32u5/b-u585i-iot02a/src/Makefile b/boards/arm/stm32u5/b-u585i-iot02a/src/Makefile deleted file mode 100644 index 0a32978916af9..0000000000000 --- a/boards/arm/stm32u5/b-u585i-iot02a/src/Makefile +++ /dev/null @@ -1,32 +0,0 @@ -############################################################################## -# boards/arm/stm32u5/b-u585i-iot02a/src/Makefile -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################## - --include $(TOPDIR)/Make.defs - -ASRCS = -CSRCS = stm32_boot.c stm32_bringup.c stm32_spi.c - -ifeq ($(CONFIG_ARCH_BOARD_STM32U5_CUSTOM_CLOCKCONFIG),y) -CSRCS += stm32_clockconfig.c -endif - -include $(TOPDIR)/boards/Board.mk diff --git a/boards/arm/stm32u5/b-u585i-iot02a/src/b-u585i-iot02a.h b/boards/arm/stm32u5/b-u585i-iot02a/src/b-u585i-iot02a.h index 7e383e0bbf388..be0c769b5364e 100644 --- a/boards/arm/stm32u5/b-u585i-iot02a/src/b-u585i-iot02a.h +++ b/boards/arm/stm32u5/b-u585i-iot02a/src/b-u585i-iot02a.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32U5_B_U585I_IOT02A_SRC_B_U585I_IOT02A_H -#define __BOARDS_ARM_STM32U5_B_U585I_IOT02A_SRC_B_U585I_IOT02A_H +#ifndef __BOARDS_ARM_STM32_B_U585I_IOT02A_SRC_B_U585I_IOT02A_H +#define __BOARDS_ARM_STM32_B_U585I_IOT02A_SRC_B_U585I_IOT02A_H /**************************************************************************** * Included Files @@ -97,4 +97,4 @@ void stm32_spidev_initialize(void); int stm32_bringup(void); #endif /* __ASSEMBLY__ */ -#endif /* __BOARDS_ARM_STM32U5_B_U585I_IOT02A_SRC_B_U585I_IOT02A_H */ +#endif /* __BOARDS_ARM_STM32_B_U585I_IOT02A_SRC_B_U585I_IOT02A_H */ diff --git a/boards/arm/stm32u5/b-u585i-iot02a/src/stm32_clockconfig.c b/boards/arm/stm32u5/b-u585i-iot02a/src/stm32_clockconfig.c index b6aa7c6a37197..378c5ec51c799 100644 --- a/boards/arm/stm32u5/b-u585i-iot02a/src/stm32_clockconfig.c +++ b/boards/arm/stm32u5/b-u585i-iot02a/src/stm32_clockconfig.c @@ -38,12 +38,12 @@ * NuttX in the Non-Secure domain together with TrustedFirmware-M (TFM). * In this setup the clock configuration is done by TFM, not by NuttX. * Thus, the board's configuration sets - * CONFIG_ARCH_BOARD_STM32L5_CUSTOM_CLOCKCONFIG to avoid the standard clock + * CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG to avoid the standard clock * config logic to run and instead do just nothing in this function. * ****************************************************************************/ -#if defined(CONFIG_ARCH_BOARD_STM32U5_CUSTOM_CLOCKCONFIG) +#if defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) void stm32_board_clockconfig(void) { } diff --git a/boards/arm/stm32u5/b-u585i-iot02a/src/stm32_spi.c b/boards/arm/stm32u5/b-u585i-iot02a/src/stm32_spi.c index 4bea93db07188..13bd3f7989538 100644 --- a/boards/arm/stm32u5/b-u585i-iot02a/src/stm32_spi.c +++ b/boards/arm/stm32u5/b-u585i-iot02a/src/stm32_spi.c @@ -41,7 +41,7 @@ #include "b-u585i-iot02a.h" #include -#ifdef CONFIG_STM32U5_SPI +#ifdef CONFIG_STM32_SPI /**************************************************************************** * Public Functions @@ -64,7 +64,7 @@ void stm32_spidev_initialize(void) * architecture. */ -#ifdef CONFIG_STM32U5_SPI1 +#ifdef CONFIG_STM32_SPI1 stm32_configgpio(GPIO_SPI1_NSS); #endif } @@ -95,7 +95,7 @@ void stm32_spidev_initialize(void) * ****************************************************************************/ -#ifdef CONFIG_STM32U5_SPI1 +#ifdef CONFIG_STM32_SPI1 void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -111,7 +111,7 @@ uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32U5_SPI2 +#ifdef CONFIG_STM32_SPI2 void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -125,7 +125,7 @@ uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32U5_SPI3 +#ifdef CONFIG_STM32_SPI3 void stm32_spi3select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -162,25 +162,25 @@ uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid) ****************************************************************************/ #ifdef CONFIG_SPI_CMDDATA -#ifdef CONFIG_STM32U5_SPI1 +#ifdef CONFIG_STM32_SPI1 int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32U5_SPI2 +#ifdef CONFIG_STM32_SPI2 int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32U5_SPI3 +#ifdef CONFIG_STM32_SPI3 int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif #endif /* CONFIG_SPI_CMDDATA */ -#endif /* CONFIG_STM32U5_SPI */ +#endif /* CONFIG_STM32_SPI */ diff --git a/boards/arm/stm32u5/common/CMakeLists.txt b/boards/arm/stm32u5/common/CMakeLists.txt new file mode 100644 index 0000000000000..aac8d57d3e903 --- /dev/null +++ b/boards/arm/stm32u5/common/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32u5/common/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(${NUTTX_DIR}/boards/arm/common/stm32 stm32_common) diff --git a/boards/arm/stm32u5/common/Makefile b/boards/arm/stm32u5/common/Makefile new file mode 100644 index 0000000000000..9688ec685c992 --- /dev/null +++ b/boards/arm/stm32u5/common/Makefile @@ -0,0 +1,36 @@ +############################################################################# +# boards/arm/stm32u5/common/Makefile +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################# + +include $(TOPDIR)/Make.defs + +STM32_BOARD_COMMON_DIR := $(TOPDIR)$(DELIM)boards$(DELIM)arm$(DELIM)common$(DELIM)stm32 + +include board/Make.defs +include $(STM32_BOARD_COMMON_DIR)$(DELIM)src$(DELIM)Make.defs + +DEPPATH += --dep-path board + +include $(TOPDIR)/boards/Board.mk + +ARCHSRCDIR = $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src +BOARDDIR = $(ARCHSRCDIR)$(DELIM)board +CFLAGS += ${INCDIR_PREFIX}$(BOARDDIR)$(DELIM)include diff --git a/boards/arm/stm32u5/nucleo-u5a5zj-q/configs/nsh/defconfig b/boards/arm/stm32u5/nucleo-u5a5zj-q/configs/nsh/defconfig index a489a5a0284cf..62d5aa14537ff 100644 --- a/boards/arm/stm32u5/nucleo-u5a5zj-q/configs/nsh/defconfig +++ b/boards/arm/stm32u5/nucleo-u5a5zj-q/configs/nsh/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-u5a5zj-q" CONFIG_ARCH_BOARD_NUCLEO_U5A5ZJ_Q=y CONFIG_ARCH_CHIP="stm32u5" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32U5=y CONFIG_ARCH_CHIP_STM32U5A5ZJT=y CONFIG_ARCH_INTERRUPTSTACK=2048 @@ -47,14 +48,14 @@ CONFIG_READLINE_TABCOMPLETION=y CONFIG_RR_INTERVAL=200 CONFIG_SCHED_WAITPID=y CONFIG_STACK_COLORATION=y -CONFIG_STM32U5_PWR=y -CONFIG_STM32U5_SRAM2=y -CONFIG_STM32U5_SRAM2_HEAP=y -CONFIG_STM32U5_SRAM3=y -CONFIG_STM32U5_SRAM3_HEAP=y -CONFIG_STM32U5_SRAM5=y -CONFIG_STM32U5_SRAM5_HEAP=y -CONFIG_STM32U5_USART1=y +CONFIG_STM32_PWR=y +CONFIG_STM32_SRAM2=y +CONFIG_STM32_SRAM2_HEAP=y +CONFIG_STM32_SRAM3=y +CONFIG_STM32_SRAM3_HEAP=y +CONFIG_STM32_SRAM5=y +CONFIG_STM32_SRAM5_HEAP=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_SYSTEM_NSH_STACKSIZE=2048 CONFIG_SYSTEM_TEE=y diff --git a/boards/arm/stm32u5/nucleo-u5a5zj-q/include/board.h b/boards/arm/stm32u5/nucleo-u5a5zj-q/include/board.h index e8636105d0a17..3ba1bc1f1346b 100644 --- a/boards/arm/stm32u5/nucleo-u5a5zj-q/include/board.h +++ b/boards/arm/stm32u5/nucleo-u5a5zj-q/include/board.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32U5_NUCLEO_U5A5ZJ_Q_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32U5_NUCLEO_U5A5ZJ_Q_INCLUDE_BOARD_H +#ifndef __BOARDS_ARM_STM32_NUCLEO_U5A5ZJ_Q_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32_NUCLEO_U5A5ZJ_Q_INCLUDE_BOARD_H /**************************************************************************** * Included Files @@ -203,4 +203,4 @@ void stm32_board_initialize(void); #endif #endif /* __ASSEMBLY__ */ -#endif /* __BOARDS_ARM_STM32U5_NUCLEO_U5A5ZJ_Q_INCLUDE_BOARD_H */ +#endif /* __BOARDS_ARM_STM32_NUCLEO_U5A5ZJ_Q_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32u5/nucleo-u5a5zj-q/src/CMakeLists.txt b/boards/arm/stm32u5/nucleo-u5a5zj-q/src/CMakeLists.txt index fa6b58b12dc9d..0ab477f594668 100644 --- a/boards/arm/stm32u5/nucleo-u5a5zj-q/src/CMakeLists.txt +++ b/boards/arm/stm32u5/nucleo-u5a5zj-q/src/CMakeLists.txt @@ -22,7 +22,7 @@ set(SRCS stm32_boot.c stm32_bringup.c stm32_spi.c) -if(CONFIG_ARCH_BOARD_STM32U5_CUSTOM_CLOCKCONFIG) +if(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) list(APPEND SRCS stm32_clockconfig.c) endif() diff --git a/boards/arm/stm32u5/nucleo-u5a5zj-q/src/Make.defs b/boards/arm/stm32u5/nucleo-u5a5zj-q/src/Make.defs new file mode 100644 index 0000000000000..4f7e99fa88e4f --- /dev/null +++ b/boards/arm/stm32u5/nucleo-u5a5zj-q/src/Make.defs @@ -0,0 +1,38 @@ +############################################################################## +# boards/arm/stm32u5/nucleo-u5a5zj-q/src/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################## + +-include $(TOPDIR)/Make.defs + +ASRCS = +CSRCS = stm32_boot.c stm32_bringup.c stm32_spi.c + +ifeq ($(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG),y) +CSRCS += stm32_clockconfig.c +endif + +ifeq ($(CONFIG_USBDEV),y) +CSRCS += stm32_usb.c +endif + +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32u5/nucleo-u5a5zj-q/src/Makefile b/boards/arm/stm32u5/nucleo-u5a5zj-q/src/Makefile deleted file mode 100644 index 1fa94c46e61d5..0000000000000 --- a/boards/arm/stm32u5/nucleo-u5a5zj-q/src/Makefile +++ /dev/null @@ -1,36 +0,0 @@ -############################################################################## -# boards/arm/stm32u5/nucleo-u5a5zj-q/src/Makefile -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################## - --include $(TOPDIR)/Make.defs - -ASRCS = -CSRCS = stm32_boot.c stm32_bringup.c stm32_spi.c - -ifeq ($(CONFIG_ARCH_BOARD_STM32U5_CUSTOM_CLOCKCONFIG),y) -CSRCS += stm32_clockconfig.c -endif - -ifeq ($(CONFIG_USBDEV),y) -CSRCS += stm32_usb.c -endif - -include $(TOPDIR)/boards/Board.mk diff --git a/boards/arm/stm32u5/nucleo-u5a5zj-q/src/nucleo-u5a5zj-q.h b/boards/arm/stm32u5/nucleo-u5a5zj-q/src/nucleo-u5a5zj-q.h index 2fa799df2c3e5..3d1752c0fb169 100644 --- a/boards/arm/stm32u5/nucleo-u5a5zj-q/src/nucleo-u5a5zj-q.h +++ b/boards/arm/stm32u5/nucleo-u5a5zj-q/src/nucleo-u5a5zj-q.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32U5_NUCLEO_U5A5ZJ_Q_SRC_NUCLEO_U5A5ZJ_Q_H -#define __BOARDS_ARM_STM32U5_NUCLEO_U5A5ZJ_Q_SRC_NUCLEO_U5A5ZJ_Q_H +#ifndef __BOARDS_ARM_STM32_NUCLEO_U5A5ZJ_Q_SRC_NUCLEO_U5A5ZJ_Q_H +#define __BOARDS_ARM_STM32_NUCLEO_U5A5ZJ_Q_SRC_NUCLEO_U5A5ZJ_Q_H /**************************************************************************** * Included Files @@ -97,4 +97,4 @@ void stm32_spidev_initialize(void); int stm32_bringup(void); #endif /* __ASSEMBLY__ */ -#endif /* __BOARDS_ARM_STM32U5_NUCLEO_U5A5ZJ_Q_SRC_NUCLEO_U5A5ZJ_Q_H */ +#endif /* __BOARDS_ARM_STM32_NUCLEO_U5A5ZJ_Q_SRC_NUCLEO_U5A5ZJ_Q_H */ diff --git a/boards/arm/stm32u5/nucleo-u5a5zj-q/src/stm32_bringup.c b/boards/arm/stm32u5/nucleo-u5a5zj-q/src/stm32_bringup.c index 2d246c3377f45..5cde87263ab16 100644 --- a/boards/arm/stm32u5/nucleo-u5a5zj-q/src/stm32_bringup.c +++ b/boards/arm/stm32u5/nucleo-u5a5zj-q/src/stm32_bringup.c @@ -118,7 +118,7 @@ int stm32_bringup(void) return -1; } -#if defined(STM32U5_I2C2) +#if defined(STM32_I2C2) i2c2_m = stm32_i2cbus_initialize(2); if (i2c2_m == NULL) { diff --git a/boards/arm/stm32u5/nucleo-u5a5zj-q/src/stm32_clockconfig.c b/boards/arm/stm32u5/nucleo-u5a5zj-q/src/stm32_clockconfig.c index 24afdb388badf..976a515f7b4e3 100644 --- a/boards/arm/stm32u5/nucleo-u5a5zj-q/src/stm32_clockconfig.c +++ b/boards/arm/stm32u5/nucleo-u5a5zj-q/src/stm32_clockconfig.c @@ -38,12 +38,12 @@ * NuttX in the Non-Secure domain together with TrustedFirmware-M (TFM). * In this setup the clock configuration is done by TFM, not by NuttX. * Thus, the board's configuration sets - * CONFIG_ARCH_BOARD_STM32L5_CUSTOM_CLOCKCONFIG to avoid the standard clock + * CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG to avoid the standard clock * config logic to run and instead do just nothing in this function. * ****************************************************************************/ -#if defined(CONFIG_ARCH_BOARD_STM32U5_CUSTOM_CLOCKCONFIG) +#if defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) void stm32_board_clockconfig(void) { } diff --git a/boards/arm/stm32u5/nucleo-u5a5zj-q/src/stm32_spi.c b/boards/arm/stm32u5/nucleo-u5a5zj-q/src/stm32_spi.c index efae2e53942f8..34e5a5352dd6b 100644 --- a/boards/arm/stm32u5/nucleo-u5a5zj-q/src/stm32_spi.c +++ b/boards/arm/stm32u5/nucleo-u5a5zj-q/src/stm32_spi.c @@ -41,7 +41,7 @@ #include "nucleo-u5a5zj-q.h" #include -#ifdef CONFIG_STM32U5_SPI +#ifdef CONFIG_STM32_SPI /**************************************************************************** * Public Functions @@ -64,7 +64,7 @@ void stm32_spidev_initialize(void) * architecture. */ -#ifdef CONFIG_STM32U5_SPI1 +#ifdef CONFIG_STM32_SPI1 stm32_configgpio(GPIO_SPI1_NSS); #endif } @@ -95,7 +95,7 @@ void stm32_spidev_initialize(void) * ****************************************************************************/ -#ifdef CONFIG_STM32U5_SPI1 +#ifdef CONFIG_STM32_SPI1 void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -111,7 +111,7 @@ uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32U5_SPI2 +#ifdef CONFIG_STM32_SPI2 void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -125,7 +125,7 @@ uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32U5_SPI3 +#ifdef CONFIG_STM32_SPI3 void stm32_spi3select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -162,25 +162,25 @@ uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid) ****************************************************************************/ #ifdef CONFIG_SPI_CMDDATA -#ifdef CONFIG_STM32U5_SPI1 +#ifdef CONFIG_STM32_SPI1 int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32U5_SPI2 +#ifdef CONFIG_STM32_SPI2 int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32U5_SPI3 +#ifdef CONFIG_STM32_SPI3 int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif #endif /* CONFIG_SPI_CMDDATA */ -#endif /* CONFIG_STM32U5_SPI */ +#endif /* CONFIG_STM32_SPI */ diff --git a/boards/arm/stm32wb/common/CMakeLists.txt b/boards/arm/stm32wb/common/CMakeLists.txt new file mode 100644 index 0000000000000..db8921e4f1c9d --- /dev/null +++ b/boards/arm/stm32wb/common/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32wb/common/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(${NUTTX_DIR}/boards/arm/common/stm32 stm32_common) diff --git a/boards/arm/stm32wb/common/Makefile b/boards/arm/stm32wb/common/Makefile new file mode 100644 index 0000000000000..37068a4128551 --- /dev/null +++ b/boards/arm/stm32wb/common/Makefile @@ -0,0 +1,36 @@ +############################################################################# +# boards/arm/stm32wb/common/Makefile +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################# + +include $(TOPDIR)/Make.defs + +STM32_BOARD_COMMON_DIR := $(TOPDIR)$(DELIM)boards$(DELIM)arm$(DELIM)common$(DELIM)stm32 + +include board/Make.defs +include $(STM32_BOARD_COMMON_DIR)$(DELIM)src$(DELIM)Make.defs + +DEPPATH += --dep-path board + +include $(TOPDIR)/boards/Board.mk + +ARCHSRCDIR = $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src +BOARDDIR = $(ARCHSRCDIR)$(DELIM)board +CFLAGS += ${INCDIR_PREFIX}$(BOARDDIR)$(DELIM)include diff --git a/boards/arm/stm32wb/flipperzero/configs/nsh/defconfig b/boards/arm/stm32wb/flipperzero/configs/nsh/defconfig index c127e72875f9b..d1a1619b32a13 100644 --- a/boards/arm/stm32wb/flipperzero/configs/nsh/defconfig +++ b/boards/arm/stm32wb/flipperzero/configs/nsh/defconfig @@ -11,6 +11,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="flipperzero" CONFIG_ARCH_BOARD_FLIPPERZERO=y CONFIG_ARCH_CHIP="stm32wb" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32WB55RG=y CONFIG_ARCH_CHIP_STM32WB=y CONFIG_ARCH_INTERRUPTSTACK=2048 @@ -46,11 +47,11 @@ CONFIG_RAW_BINARY=y CONFIG_RR_INTERVAL=200 CONFIG_SCHED_WAITPID=y CONFIG_ST7565_MIRROR_Y=y -CONFIG_STM32WB_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32WB_DMA1=y -CONFIG_STM32WB_PWR=y -CONFIG_STM32WB_SPI2=y -CONFIG_STM32WB_USART1=y +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_DMA1=y +CONFIG_STM32_PWR=y +CONFIG_STM32_SPI2=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_TESTING_OSTEST=y diff --git a/boards/arm/stm32wb/flipperzero/include/board.h b/boards/arm/stm32wb/flipperzero/include/board.h index e00cf8ce7ae94..a0119be94cd06 100644 --- a/boards/arm/stm32wb/flipperzero/include/board.h +++ b/boards/arm/stm32wb/flipperzero/include/board.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32WB_FLIPPERZERO_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32WB_FLIPPERZERO_INCLUDE_BOARD_H +#ifndef __BOARDS_ARM_STM32_FLIPPERZERO_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32_FLIPPERZERO_INCLUDE_BOARD_H /**************************************************************************** * Included Files @@ -84,13 +84,13 @@ /* LCD */ -#define STM32WB_LCD_SPINO 2 /* SPI2 */ +#define STM32_LCD_SPINO 2 /* SPI2 */ -#define STM32WB_LCD_CS (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_5MHz |\ +#define STM32_LCD_CS (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_5MHz |\ GPIO_OUTPUT_SET | GPIO_PORTC | GPIO_PIN11) -#define STM32WB_LCD_RST (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_5MHz |\ +#define STM32_LCD_RST (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_5MHz |\ GPIO_OUTPUT_SET | GPIO_PORTB | GPIO_PIN0) -#define STM32WB_LCD_A0 (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_5MHz |\ +#define STM32_LCD_A0 (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_5MHz |\ GPIO_OUTPUT_SET | GPIO_PORTB | GPIO_PIN1) /**************************************************************************** @@ -113,7 +113,7 @@ extern "C" ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_board_initialize + * Name: stm32_board_initialize * * Description: * All STM32WB architectures must provide the following entry point. @@ -123,7 +123,7 @@ extern "C" * ****************************************************************************/ -void stm32wb_board_initialize(void); +void stm32_board_initialize(void); #undef EXTERN #if defined(__cplusplus) @@ -131,4 +131,4 @@ void stm32wb_board_initialize(void); #endif #endif /* __ASSEMBLY__ */ -#endif /* __BOARDS_ARM_STM32WB_FLIPPERZERO_INCLUDE_BOARD_H */ +#endif /* __BOARDS_ARM_STM32_FLIPPERZERO_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32wb/flipperzero/include/flipperzero-clocking.h b/boards/arm/stm32wb/flipperzero/include/flipperzero-clocking.h index ce6734fd5a602..a2ac79cd543a2 100644 --- a/boards/arm/stm32wb/flipperzero/include/flipperzero-clocking.h +++ b/boards/arm/stm32wb/flipperzero/include/flipperzero-clocking.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32WB_FLIPPERZERO_INCLUDE_FLIPPERZERO_CLOCKING_H -#define __BOARDS_ARM_STM32WB_FLIPPERZERO_INCLUDE_FLIPPERZERO_CLOCKING_H +#ifndef __BOARDS_ARM_STM32_FLIPPERZERO_INCLUDE_FLIPPERZERO_CLOCKING_H +#define __BOARDS_ARM_STM32_FLIPPERZERO_INCLUDE_FLIPPERZERO_CLOCKING_H /**************************************************************************** * Included Files @@ -51,10 +51,10 @@ * HSI48 - 48 MHz fine-granularity trimmable RC with CRS */ -#define STM32WB_HSI_FREQUENCY 16000000ul -#define STM32WB_LSI_FREQUENCY 32000 -#define STM32WB_LSE_FREQUENCY 32768 -#define STM32WB_HSE_FREQUENCY 32000000ul +#define STM32_HSI_FREQUENCY 16000000ul +#define STM32_LSI_FREQUENCY 32000 +#define STM32_LSE_FREQUENCY 32768 +#define STM32_HSE_FREQUENCY 32000000ul /* XXX there needs to be independent selections for the System Clock Mux and * the PLL Source Mux; currently System Clock Mux always is PLL, and PLL @@ -71,145 +71,145 @@ #endif #if 0 -# define STM32WB_BOARD_RFWKP_USEHSE 1 /* CPU2 use HSE/1024 on RF wakeup */ +# define STM32_BOARD_RFWKP_USEHSE 1 /* CPU2 use HSE/1024 on RF wakeup */ #elif 1 -# define STM32WB_BOARD_RFWKP_USELSE 1 /* CPU2 use LSE on RF wakeup */ +# define STM32_BOARD_RFWKP_USELSE 1 /* CPU2 use LSE on RF wakeup */ #endif #if defined(HSI_CLOCK_CONFIG) -#define STM32WB_BOARD_USEHSI 1 +#define STM32_BOARD_USEHSI 1 -#define STM32WB_SYSCLK_FREQUENCY 64000000ul +#define STM32_SYSCLK_FREQUENCY 64000000ul /* Prescaler common to all PLL inputs; will be 1 */ -#define STM32WB_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) /* 'main' PLL config; we use this to generate our system clock via the R * output. We set it up as (((16MHz / 1) * 8) / 2) = 64MHz */ -#define STM32WB_PLLCFG_PLLN RCC_PLLCFG_PLLN(8) -#define STM32WB_PLLCFG_PLLR_ENABLED -#define STM32WB_PLLCFG_PLLR RCC_PLLCFG_PLLR(2) +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(8) +#define STM32_PLLCFG_PLLR_ENABLED +#define STM32_PLLCFG_PLLR RCC_PLLCFG_PLLR(2) /* 'SAIPLL1' is not used */ -#define STM32WB_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(8) +#define STM32_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(8) /* CLK48 will come from HSI48 */ -#define STM32WB_USE_CLK48 1 -#define STM32WB_CLK48_SEL RCC_CCIPR_CLK48SEL_HSI48 -#define STM32WB_HSI48_SYNCSRC SYNCSRC_LSE +#define STM32_USE_CLK48 1 +#define STM32_CLK48_SEL RCC_CCIPR_CLK48SEL_HSI48 +#define STM32_HSI48_SYNCSRC SYNCSRC_LSE /* Enable LSE oscillator, used automatically trim the HSI48, and for RTC */ -#define STM32WB_USE_LSE 1 +#define STM32_USE_LSE 1 #elif defined(HSE_CLOCK_CONFIG) /* Use the HSE */ -#define STM32WB_BOARD_USEHSE 1 +#define STM32_BOARD_USEHSE 1 -#define STM32WB_SYSCLK_FREQUENCY 64000000ul +#define STM32_SYSCLK_FREQUENCY 64000000ul /* Prescaler common to all PLL inputs; will be 2 */ -#define STM32WB_PLLCFG_PLLM RCC_PLLCFG_PLLM(2) +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(2) /* 'main' PLL config; we use this to generate our system clock via the R * output. We set it up as (((32MHz / 2) * 12) / 3) = 64MHz * And the Q output is set as (((32MHz / 2) * 12) / 4) = 48MHz */ -#define STM32WB_PLLCFG_PLLN RCC_PLLCFG_PLLN(12) -#define STM32WB_PLLCFG_PLLR_ENABLED -#define STM32WB_PLLCFG_PLLR RCC_PLLCFG_PLLR(3) -#define STM32WB_PLLCFG_PLLQ_ENABLED -#define STM32WB_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(4) +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(12) +#define STM32_PLLCFG_PLLR_ENABLED +#define STM32_PLLCFG_PLLR RCC_PLLCFG_PLLR(3) +#define STM32_PLLCFG_PLLQ_ENABLED +#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(4) /* 'SAIPLL1' is not used */ -#define STM32WB_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(8) +#define STM32_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(8) /* CLK48 will come from the PLLMAIN via the Q output */ -#define STM32WB_USE_CLK48 1 -#define STM32WB_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLMAIN -#define STM32WB_HSI48_SYNCSRC SYNCSRC_NONE +#define STM32_USE_CLK48 1 +#define STM32_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLMAIN +#define STM32_HSI48_SYNCSRC SYNCSRC_NONE /* Enable LSE (for the RTC) */ -#define STM32WB_USE_LSE 1 +#define STM32_USE_LSE 1 #elif defined(MSI_CLOCK_CONFIG) /* Use the MSI */ -#define STM32WB_BOARD_USEMSI 1 +#define STM32_BOARD_USEMSI 1 -#define STM32WB_BOARD_MSIRANGE RCC_CR_MSIRANGE_4M +#define STM32_BOARD_MSIRANGE RCC_CR_MSIRANGE_4M -#define STM32WB_SYSCLK_FREQUENCY 64000000ul +#define STM32_SYSCLK_FREQUENCY 64000000ul /* Prescaler common to all PLL inputs; will be 1 */ -#define STM32WB_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) /* 'main' PLL config; we use this to generate our system clock via the R * output. We set it up as (((4MHz / 1) * 48) / 3) = 64MHz * And the Q output is set as (((4MHz / 1) * 48) / 4) = 48MHz */ -#define STM32WB_PLLCFG_PLLN RCC_PLLCFG_PLLN(48) -#define STM32WB_PLLCFG_PLLR_ENABLED -#define STM32WB_PLLCFG_PLLR RCC_PLLCFG_PLLR(3) -#define STM32WB_PLLCFG_PLLQ_ENABLED -#define STM32WB_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(4) +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(48) +#define STM32_PLLCFG_PLLR_ENABLED +#define STM32_PLLCFG_PLLR RCC_PLLCFG_PLLR(3) +#define STM32_PLLCFG_PLLQ_ENABLED +#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(4) /* 'SAIPLL1' is not used */ -#define STM32WB_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(8) +#define STM32_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(8) /* CLK48 will come from the PLLMAIN via the Q output */ -#define STM32WB_USE_CLK48 1 -#define STM32WB_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLMAIN -#define STM32WB_HSI48_SYNCSRC SYNCSRC_NONE +#define STM32_USE_CLK48 1 +#define STM32_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLMAIN +#define STM32_HSI48_SYNCSRC SYNCSRC_NONE /* Enable the LSE oscillator, used automatically trim the MSI, and for RTC */ -#define STM32WB_USE_LSE 1 +#define STM32_USE_LSE 1 #endif /* AHB clock (HCLK) is SYSCLK (64MHz) */ -#define BOARD_AHB_FREQUENCY STM32WB_SYSCLK_FREQUENCY +#define BOARD_AHB_FREQUENCY STM32_SYSCLK_FREQUENCY -#define STM32WB_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK -#define STM32WB_HCLK_FREQUENCY STM32WB_SYSCLK_FREQUENCY +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY /* CPU2 clock (HCLK2) is SYSCLK/2 (32MHz) */ -#define STM32WB_RCC_EXTCFGR_C2HPRE RCC_EXTCFGR_C2HPRE_2 +#define STM32_RCC_EXTCFGR_C2HPRE RCC_EXTCFGR_C2HPRE_2 /* AHB4 clock (HCLK4) is SYSCLK (64MHz) */ -#define STM32WB_RCC_EXTCFGR_SHDHPRE RCC_EXTCFGR_SHDHPRE_1 +#define STM32_RCC_EXTCFGR_SHDHPRE RCC_EXTCFGR_SHDHPRE_1 /* APB1 clock (PCLK1) is HCLK/1 (64MHz) */ -#define STM32WB_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK1 -#define STM32WB_PCLK1_FREQUENCY (STM32WB_HCLK_FREQUENCY / 1) +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK1 +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY / 1) /* APB2 clock (PCLK2) is HCLK/1 (64MHz) */ -#define STM32WB_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK1 -#define STM32WB_PCLK2_FREQUENCY (STM32WB_HCLK_FREQUENCY / 1) +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK1 +#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY / 1) /* Timer Frequencies, if APB prescaler is set to 1, frequency is same to APBx * otherwise frequency is 2xAPBx. @@ -218,18 +218,18 @@ /* Timers driven from APB1 will be the same frequency as PCLK1 */ -#define STM32WB_APB1_TIM2_CLKIN (1 * STM32WB_PCLK1_FREQUENCY) +#define STM32_APB1_TIM2_CLKIN (1 * STM32_PCLK1_FREQUENCY) /* Timers driven from APB2 will be the same frequency as PCLK2 */ -#define STM32WB_APB2_TIM1_CLKIN (1 * STM32WB_PCLK2_FREQUENCY) -#define STM32WB_APB2_TIM16_CLKIN (1 * STM32WB_PCLK2_FREQUENCY) -#define STM32WB_APB2_TIM17_CLKIN (1 * STM32WB_PCLK2_FREQUENCY) +#define STM32_APB2_TIM1_CLKIN (1 * STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM16_CLKIN (1 * STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM17_CLKIN (1 * STM32_PCLK2_FREQUENCY) -#define BOARD_TIM1_FREQUENCY STM32WB_APB2_TIM1_CLKIN -#define BOARD_TIM2_FREQUENCY STM32WB_APB1_TIM2_CLKIN -#define BOARD_TIM16_FREQUENCY STM32WB_APB2_TIM16_CLKIN -#define BOARD_TIM17_FREQUENCY STM32WB_APB2_TIM17_CLKIN +#define BOARD_TIM1_FREQUENCY STM32_APB2_TIM1_CLKIN +#define BOARD_TIM2_FREQUENCY STM32_APB1_TIM2_CLKIN +#define BOARD_TIM16_FREQUENCY STM32_APB2_TIM16_CLKIN +#define BOARD_TIM17_FREQUENCY STM32_APB2_TIM17_CLKIN /* Higher SYSCLK requires more flash wait states. */ @@ -260,4 +260,4 @@ extern "C" #endif #endif /* __ASSEMBLY__ */ -#endif /* __BOARDS_ARM_STM32WB_FLIPPERZERO_INCLUDE_FLIPPERZERO_CLOCKING_H */ +#endif /* __BOARDS_ARM_STM32_FLIPPERZERO_INCLUDE_FLIPPERZERO_CLOCKING_H */ diff --git a/boards/arm/stm32wb/flipperzero/src/Make.defs b/boards/arm/stm32wb/flipperzero/src/Make.defs new file mode 100644 index 0000000000000..08de31cb0ab35 --- /dev/null +++ b/boards/arm/stm32wb/flipperzero/src/Make.defs @@ -0,0 +1,37 @@ +############################################################################ +# boards/arm/stm32wb/flipperzero/src/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +CSRCS = stm32_boot.c + +ifeq ($(CONFIG_SPI),y) +CSRCS += stm32_spi.c +endif + +ifeq ($(CONFIG_LCD_ST7565),y) +CSRCS += stm32_lcd_st7565.c +endif + +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32wb/flipperzero/src/Makefile b/boards/arm/stm32wb/flipperzero/src/Makefile deleted file mode 100644 index 716d6b290016b..0000000000000 --- a/boards/arm/stm32wb/flipperzero/src/Makefile +++ /dev/null @@ -1,35 +0,0 @@ -############################################################################ -# boards/arm/stm32wb/flipperzero/src/Makefile -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/Make.defs - -CSRCS = stm32_boot.c - -ifeq ($(CONFIG_SPI),y) -CSRCS += stm32_spi.c -endif - -ifeq ($(CONFIG_LCD_ST7565),y) -CSRCS += stm32_lcd_st7565.c -endif - -include $(TOPDIR)/boards/Board.mk diff --git a/boards/arm/stm32wb/flipperzero/src/flipperzero.h b/boards/arm/stm32wb/flipperzero/src/flipperzero.h index b7b1015a42424..6bb7850aefdd5 100644 --- a/boards/arm/stm32wb/flipperzero/src/flipperzero.h +++ b/boards/arm/stm32wb/flipperzero/src/flipperzero.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32WB_FLIPPERZERO_SRC_FLIPPERZERO_H -#define __BOARDS_ARM_STM32WB_FLIPPERZERO_SRC_FLIPPERZERO_H +#ifndef __BOARDS_ARM_STM32_FLIPPERZERO_SRC_FLIPPERZERO_H +#define __BOARDS_ARM_STM32_FLIPPERZERO_SRC_FLIPPERZERO_H /**************************************************************************** * Included Files @@ -82,7 +82,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_spidev_initialize + * Name: stm32_spidev_initialize * * Description: * Called to configure SPI chip select GPIO pins. @@ -90,8 +90,8 @@ ****************************************************************************/ #ifdef CONFIG_SPI -void weak_function stm32wb_spidev_initialize(void); +void weak_function stm32_spidev_initialize(void); #endif #endif /* __ASSEMBLY__ */ -#endif /* __BOARDS_ARM_STM32WB_FLIPPERZERO_SRC_FLIPPERZERO_H */ +#endif /* __BOARDS_ARM_STM32_FLIPPERZERO_SRC_FLIPPERZERO_H */ diff --git a/boards/arm/stm32wb/flipperzero/src/stm32_boot.c b/boards/arm/stm32wb/flipperzero/src/stm32_boot.c index b83f7f7bab36d..2f549b32aac0a 100644 --- a/boards/arm/stm32wb/flipperzero/src/stm32_boot.c +++ b/boards/arm/stm32wb/flipperzero/src/stm32_boot.c @@ -47,7 +47,7 @@ # include "stm32wb_rtc.h" #endif -#ifdef CONFIG_STM32WB_BLE +#ifdef CONFIG_STM32_BLE # include "stm32wb_blehci.h" #endif @@ -58,7 +58,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_board_initialize + * Name: stm32_board_initialize * * Description: * All STM32WB architectures must provide the following entry point. This @@ -68,16 +68,16 @@ * ****************************************************************************/ -void stm32wb_board_initialize(void) +void stm32_board_initialize(void) { /* Configure SPI chip selects if 1) SPI is not disabled, and 2) the weak * function stm32_spidev_initialize() has been brought into the link. */ #ifdef CONFIG_SPI - if (stm32wb_spidev_initialize) + if (stm32_spidev_initialize) { - stm32wb_spidev_initialize(); + stm32_spidev_initialize(); } #endif @@ -142,7 +142,7 @@ void board_late_initialize(void) #ifdef CONFIG_RTC_DRIVER /* Instantiate the STM32WB lower-half RTC driver */ - rtclower = stm32wb_rtc_lowerhalf(); + rtclower = stm32_rtc_lowerhalf(); if (!rtclower) { serr("ERROR: Failed to instantiate the RTC lower-half driver\n"); @@ -166,7 +166,7 @@ void board_late_initialize(void) #ifdef CONFIG_TIMER /* Initialize and register the timer driver */ - ret = stm32wb_timer_initialize("/dev/timer0", 1); + ret = stm32_timer_initialize("/dev/timer0", 1); if (ret < 0) { syslog(LOG_ERR, "ERROR: Failed to register the timer driver: %d\n", @@ -183,10 +183,10 @@ void board_late_initialize(void) } #endif -#ifdef CONFIG_STM32WB_BLE +#ifdef CONFIG_STM32_BLE /* Initialize and register BLE HCI driver */ - stm32wb_blehci_initialize(); + stm32_blehci_initialize(); #endif } #endif @@ -206,7 +206,7 @@ int board_uniqueid(uint8_t *uniqueid) return -EINVAL; } - stm32wb_get_uniqueid(uniqueid); + stm32_get_uniqueid(uniqueid); return OK; } #endif diff --git a/boards/arm/stm32wb/flipperzero/src/stm32_lcd_st7565.c b/boards/arm/stm32wb/flipperzero/src/stm32_lcd_st7565.c index ed22e8917b2cb..de3771d606233 100644 --- a/boards/arm/stm32wb/flipperzero/src/stm32_lcd_st7565.c +++ b/boards/arm/stm32wb/flipperzero/src/stm32_lcd_st7565.c @@ -55,14 +55,14 @@ * Private Function Prototypes ****************************************************************************/ -static void stm32wb_st7565_reset(struct st7565_lcd_s *lcd, bool on); -static void stm32wb_st7565_select(struct st7565_lcd_s *lcd); -static void stm32wb_st7565_deselect(struct st7565_lcd_s *lcd); -static void stm32wb_st7565_cmddata(struct st7565_lcd_s *lcd, +static void stm32_st7565_reset(struct st7565_lcd_s *lcd, bool on); +static void stm32_st7565_select(struct st7565_lcd_s *lcd); +static void stm32_st7565_deselect(struct st7565_lcd_s *lcd); +static void stm32_st7565_cmddata(struct st7565_lcd_s *lcd, const uint8_t cmd); -static int stm32wb_st7565_senddata(struct st7565_lcd_s *lcd, +static int stm32_st7565_senddata(struct st7565_lcd_s *lcd, const uint8_t *data, int size); -static int stm32wb_st7565_backlight(struct st7565_lcd_s *lcd, int level); +static int stm32_st7565_backlight(struct st7565_lcd_s *lcd, int level); /**************************************************************************** * Private Data @@ -73,43 +73,43 @@ static struct lcd_dev_s *g_lcddev; static struct st7565_lcd_s g_st7565_dev = { - .reset = stm32wb_st7565_reset, - .select = stm32wb_st7565_select, - .deselect = stm32wb_st7565_deselect, - .cmddata = stm32wb_st7565_cmddata, - .senddata = stm32wb_st7565_senddata, - .backlight = stm32wb_st7565_backlight + .reset = stm32_st7565_reset, + .select = stm32_st7565_select, + .deselect = stm32_st7565_deselect, + .cmddata = stm32_st7565_cmddata, + .senddata = stm32_st7565_senddata, + .backlight = stm32_st7565_backlight }; -static void stm32wb_st7565_reset(struct st7565_lcd_s *lcd, bool on) +static void stm32_st7565_reset(struct st7565_lcd_s *lcd, bool on) { - stm32wb_gpiowrite(STM32WB_LCD_RST, !on); + stm32_gpiowrite(STM32_LCD_RST, !on); } -static void stm32wb_st7565_select(struct st7565_lcd_s *lcd) +static void stm32_st7565_select(struct st7565_lcd_s *lcd) { - stm32wb_gpiowrite(STM32WB_LCD_CS, 0); + stm32_gpiowrite(STM32_LCD_CS, 0); } -static void stm32wb_st7565_deselect(struct st7565_lcd_s *lcd) +static void stm32_st7565_deselect(struct st7565_lcd_s *lcd) { - stm32wb_gpiowrite(STM32WB_LCD_CS, 1); + stm32_gpiowrite(STM32_LCD_CS, 1); } -static void stm32wb_st7565_cmddata(struct st7565_lcd_s *lcd, +static void stm32_st7565_cmddata(struct st7565_lcd_s *lcd, const uint8_t cmd) { - stm32wb_gpiowrite(STM32WB_LCD_A0, !cmd); + stm32_gpiowrite(STM32_LCD_A0, !cmd); } -static int stm32wb_st7565_senddata(struct st7565_lcd_s *lcd, +static int stm32_st7565_senddata(struct st7565_lcd_s *lcd, const uint8_t *data, int size) { SPI_SNDBLOCK(g_spidev, data, size); return 0; } -static int stm32wb_st7565_backlight(struct st7565_lcd_s *lcd, int level) +static int stm32_st7565_backlight(struct st7565_lcd_s *lcd, int level) { return 0; } @@ -124,14 +124,14 @@ static int stm32wb_st7565_backlight(struct st7565_lcd_s *lcd, int level) int board_lcd_initialize(void) { - stm32wb_configgpio(STM32WB_LCD_RST); - stm32wb_configgpio(STM32WB_LCD_A0); + stm32_configgpio(STM32_LCD_RST); + stm32_configgpio(STM32_LCD_A0); - g_spidev = stm32wb_spibus_initialize(STM32WB_LCD_SPINO); + g_spidev = stm32_spibus_initialize(STM32_LCD_SPINO); if (!g_spidev) { - lcderr("ERROR: Failed to initialize SPI port %d\n", STM32WB_LCD_SPINO); + lcderr("ERROR: Failed to initialize SPI port %d\n", STM32_LCD_SPINO); return -ENODEV; } @@ -139,9 +139,9 @@ int board_lcd_initialize(void) g_spidev->ops->setbits(g_spidev, 8); g_spidev->ops->setfrequency(g_spidev, 1000000); - stm32wb_gpiowrite(STM32WB_LCD_RST, 0); + stm32_gpiowrite(STM32_LCD_RST, 0); up_mdelay(1); - stm32wb_gpiowrite(STM32WB_LCD_RST, 1); + stm32_gpiowrite(STM32_LCD_RST, 1); return OK; } @@ -156,12 +156,12 @@ struct lcd_dev_s *board_lcd_getdev(int lcddev) if (!g_lcddev) { lcderr("ERROR: Failed to bind SPI port %d to LCD %d\n", - STM32WB_LCD_SPINO, lcddev); + STM32_LCD_SPINO, lcddev); } else { lcdinfo("SPI port %d bound to LCD %d\n", - STM32WB_LCD_SPINO, lcddev); + STM32_LCD_SPINO, lcddev); /* And turn the LCD on (CONFIG_LCD_MAXPOWER should be 1) */ diff --git a/boards/arm/stm32wb/flipperzero/src/stm32_spi.c b/boards/arm/stm32wb/flipperzero/src/stm32_spi.c index a655b0f4f624c..fedf459eceed2 100644 --- a/boards/arm/stm32wb/flipperzero/src/stm32_spi.c +++ b/boards/arm/stm32wb/flipperzero/src/stm32_spi.c @@ -40,63 +40,63 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_spidev_initialize + * Name: stm32_spidev_initialize * * Description: * Called to configure SPI chip select GPIO pins. * ****************************************************************************/ -void weak_function stm32wb_spidev_initialize(void) +void weak_function stm32_spidev_initialize(void) { - /* NOTE: Clocking was already provided in stm32wb_rcc.c. + /* NOTE: Clocking was already provided in stm32_rcc.c. * Here, we only initialize chip select pins unique to the board * architecture. */ #ifdef CONFIG_LCD_ST7565 - stm32wb_configgpio(STM32WB_LCD_CS); /* ST7565 chip select */ + stm32_configgpio(STM32_LCD_CS); /* ST7565 chip select */ #endif } /**************************************************************************** - * Name: stm32wb_spi1/2select and stm32wb_spi1/2status + * Name: stm32_spi1/2select and stm32_spi1/2status * * Description: - * The external functions, stm32wb_spi1/2select and stm32wb_spi1/2status + * The external functions, stm32_spi1/2select and stm32_spi1/2status * must be provided by board-specific logic. They are implementations of * the select and status methods of the SPI interface defined by struct * spi_ops_s (see include/nuttx/spi/spi.h). All other methods (including - * stm32wb_spibus_initialize()) are provided by common STM32 logic. + * stm32_spibus_initialize()) are provided by common STM32 logic. * To use this common SPI logic on your board: * - * 1. Provide logic in stm32wb_boardinitialize() to configure SPI chip + * 1. Provide logic in stm32_boardinitialize() to configure SPI chip * select pins. - * 2. Provide stm32wb_spi1/2select() and stm32wb_spi1/2status() functions + * 2. Provide stm32_spi1/2select() and stm32_spi1/2status() functions * in your board-specific logic. These functions will perform chip * selection and status operations using GPIOs in the way your board is * configured. - * 3. Add a calls to stm32wb_spibus_initialize() in your low level + * 3. Add a calls to stm32_spibus_initialize() in your low level * application initialization logic - * 4. The handle returned by stm32wb_spibus_initialize() may then be used + * 4. The handle returned by stm32_spibus_initialize() may then be used * to bind the SPI driver to higher level logic (e.g., calling * mmcsd_spislotinitialize(), for example, will bind the SPI driver to * the SPI MMC/SD driver). * ****************************************************************************/ -#ifdef CONFIG_STM32WB_SPI2 -void stm32wb_spi2select(struct spi_dev_s *dev, uint32_t devid, bool selected) +#ifdef CONFIG_STM32_SPI2 +void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid, bool selected) { #ifdef CONFIG_LCD_ST7565 if (devid == SPIDEV_DISPLAY(0)) { - stm32wb_gpiowrite(STM32WB_LCD_CS, !selected); + stm32_gpiowrite(STM32_LCD_CS, !selected); } #endif } -uint8_t stm32wb_spi2status(struct spi_dev_s *dev, uint32_t devid) +uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) { return 0; } diff --git a/boards/arm/stm32wb/nucleo-wb55rg/configs/ble/defconfig b/boards/arm/stm32wb/nucleo-wb55rg/configs/ble/defconfig index ff3325b96d84c..cb0bc5bb9134e 100644 --- a/boards/arm/stm32wb/nucleo-wb55rg/configs/ble/defconfig +++ b/boards/arm/stm32wb/nucleo-wb55rg/configs/ble/defconfig @@ -11,6 +11,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-wb55rg" CONFIG_ARCH_BOARD_NUCLEO_WB55RG=y CONFIG_ARCH_CHIP="stm32wb" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32WB55RG=y CONFIG_ARCH_CHIP_STM32WB=y CONFIG_ARCH_INTERRUPTSTACK=2048 @@ -41,11 +42,11 @@ CONFIG_RAM_START=0x20000000 CONFIG_RAW_BINARY=y CONFIG_RR_INTERVAL=200 CONFIG_SCHED_WAITPID=y -CONFIG_STM32WB_BLE=y -CONFIG_STM32WB_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32WB_DMA1=y -CONFIG_STM32WB_PWR=y -CONFIG_STM32WB_USART1=y +CONFIG_STM32_BLE=y +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_DMA1=y +CONFIG_STM32_PWR=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_TESTING_OSTEST=y diff --git a/boards/arm/stm32wb/nucleo-wb55rg/configs/nimble/defconfig b/boards/arm/stm32wb/nucleo-wb55rg/configs/nimble/defconfig index 7e9dcb33872da..73b3510b415fa 100644 --- a/boards/arm/stm32wb/nucleo-wb55rg/configs/nimble/defconfig +++ b/boards/arm/stm32wb/nucleo-wb55rg/configs/nimble/defconfig @@ -13,6 +13,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-wb55rg" CONFIG_ARCH_BOARD_NUCLEO_WB55RG=y CONFIG_ARCH_CHIP="stm32wb" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32WB55RG=y CONFIG_ARCH_CHIP_STM32WB=y CONFIG_ARCH_INTERRUPTSTACK=2048 @@ -46,11 +47,11 @@ CONFIG_RAW_BINARY=y CONFIG_RR_INTERVAL=200 CONFIG_SCHED_WAITPID=y CONFIG_SIG_EVTHREAD=y -CONFIG_STM32WB_BLE=y -CONFIG_STM32WB_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32WB_DMA1=y -CONFIG_STM32WB_PWR=y -CONFIG_STM32WB_USART1=y +CONFIG_STM32_BLE=y +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_DMA1=y +CONFIG_STM32_PWR=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_TESTING_OSTEST=y diff --git a/boards/arm/stm32wb/nucleo-wb55rg/configs/nsh/defconfig b/boards/arm/stm32wb/nucleo-wb55rg/configs/nsh/defconfig index 0738f6cea5820..cdd024ed73b32 100644 --- a/boards/arm/stm32wb/nucleo-wb55rg/configs/nsh/defconfig +++ b/boards/arm/stm32wb/nucleo-wb55rg/configs/nsh/defconfig @@ -9,6 +9,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-wb55rg" CONFIG_ARCH_BOARD_NUCLEO_WB55RG=y CONFIG_ARCH_CHIP="stm32wb" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32WB55RG=y CONFIG_ARCH_CHIP_STM32WB=y CONFIG_ARCH_INTERRUPTSTACK=2048 @@ -30,10 +31,10 @@ CONFIG_RAM_START=0x20000000 CONFIG_RAW_BINARY=y CONFIG_RR_INTERVAL=200 CONFIG_SCHED_WAITPID=y -CONFIG_STM32WB_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32WB_DMA1=y -CONFIG_STM32WB_PWR=y -CONFIG_STM32WB_USART1=y +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_DMA1=y +CONFIG_STM32_PWR=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_TESTING_OSTEST=y diff --git a/boards/arm/stm32wb/nucleo-wb55rg/include/board.h b/boards/arm/stm32wb/nucleo-wb55rg/include/board.h index 328fba31d5f0a..479d2c17f7aec 100644 --- a/boards/arm/stm32wb/nucleo-wb55rg/include/board.h +++ b/boards/arm/stm32wb/nucleo-wb55rg/include/board.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32WB_NUCLEO_WB55RG_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32WB_NUCLEO_WB55RG_INCLUDE_BOARD_H +#ifndef __BOARDS_ARM_STM32_NUCLEO_WB55RG_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32_NUCLEO_WB55RG_INCLUDE_BOARD_H /**************************************************************************** * Included Files @@ -183,7 +183,7 @@ extern "C" ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_board_initialize + * Name: stm32_board_initialize * * Description: * All STM32WB architectures must provide the following entry point. @@ -193,7 +193,7 @@ extern "C" * ****************************************************************************/ -void stm32wb_board_initialize(void); +void stm32_board_initialize(void); #undef EXTERN #if defined(__cplusplus) @@ -201,4 +201,4 @@ void stm32wb_board_initialize(void); #endif #endif /* __ASSEMBLY__ */ -#endif /* __BOARDS_ARM_STM32WB_NUCLEO_WB55RG_INCLUDE_BOARD_H */ +#endif /* __BOARDS_ARM_STM32_NUCLEO_WB55RG_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32wb/nucleo-wb55rg/include/nucleo-wb55rg.h b/boards/arm/stm32wb/nucleo-wb55rg/include/nucleo-wb55rg.h index d48843b2736c3..8c3ef4e018927 100644 --- a/boards/arm/stm32wb/nucleo-wb55rg/include/nucleo-wb55rg.h +++ b/boards/arm/stm32wb/nucleo-wb55rg/include/nucleo-wb55rg.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32WB_NUCLEO_WB55RG_INCLUDE_NUCLEO_WB55RG_H -#define __BOARDS_ARM_STM32WB_NUCLEO_WB55RG_INCLUDE_NUCLEO_WB55RG_H +#ifndef __BOARDS_ARM_STM32_NUCLEO_WB55RG_INCLUDE_NUCLEO_WB55RG_H +#define __BOARDS_ARM_STM32_NUCLEO_WB55RG_INCLUDE_NUCLEO_WB55RG_H /**************************************************************************** * Included Files @@ -52,10 +52,10 @@ * HSI48 - 48 MHz fine-granularity trimmable RC with CRS */ -#define STM32WB_HSI_FREQUENCY 16000000ul -#define STM32WB_LSI_FREQUENCY 32000 -#define STM32WB_LSE_FREQUENCY 32768 -#define STM32WB_HSE_FREQUENCY 32000000ul +#define STM32_HSI_FREQUENCY 16000000ul +#define STM32_LSI_FREQUENCY 32000 +#define STM32_LSE_FREQUENCY 32768 +#define STM32_HSE_FREQUENCY 32000000ul /* XXX there needs to be independent selections for the System Clock Mux and * the PLL Source Mux; currently System Clock Mux always is PLL, and PLL @@ -72,145 +72,145 @@ #endif #if 0 -# define STM32WB_BOARD_RFWKP_USEHSE 1 /* CPU2 use HSE/1024 on RF wakeup */ +# define STM32_BOARD_RFWKP_USEHSE 1 /* CPU2 use HSE/1024 on RF wakeup */ #elif 1 -# define STM32WB_BOARD_RFWKP_USELSE 1 /* CPU2 use LSE on RF wakeup */ +# define STM32_BOARD_RFWKP_USELSE 1 /* CPU2 use LSE on RF wakeup */ #endif #if defined(HSI_CLOCK_CONFIG) -#define STM32WB_BOARD_USEHSI 1 +#define STM32_BOARD_USEHSI 1 -#define STM32WB_SYSCLK_FREQUENCY 64000000ul +#define STM32_SYSCLK_FREQUENCY 64000000ul /* Prescaler common to all PLL inputs; will be 1 */ -#define STM32WB_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) /* 'main' PLL config; we use this to generate our system clock via the R * output. We set it up as (((16MHz / 1) * 8) / 2) = 64MHz */ -#define STM32WB_PLLCFG_PLLN RCC_PLLCFG_PLLN(8) -#define STM32WB_PLLCFG_PLLR_ENABLED -#define STM32WB_PLLCFG_PLLR RCC_PLLCFG_PLLR(2) +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(8) +#define STM32_PLLCFG_PLLR_ENABLED +#define STM32_PLLCFG_PLLR RCC_PLLCFG_PLLR(2) /* 'SAIPLL1' is not used */ -#define STM32WB_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(8) +#define STM32_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(8) /* CLK48 will come from HSI48 */ -#define STM32WB_USE_CLK48 1 -#define STM32WB_CLK48_SEL RCC_CCIPR_CLK48SEL_HSI48 -#define STM32WB_HSI48_SYNCSRC SYNCSRC_LSE +#define STM32_USE_CLK48 1 +#define STM32_CLK48_SEL RCC_CCIPR_CLK48SEL_HSI48 +#define STM32_HSI48_SYNCSRC SYNCSRC_LSE /* Enable LSE oscillator, used automatically trim the HSI48, and for RTC */ -#define STM32WB_USE_LSE 1 +#define STM32_USE_LSE 1 #elif defined(HSE_CLOCK_CONFIG) /* Use the HSE */ -#define STM32WB_BOARD_USEHSE 1 +#define STM32_BOARD_USEHSE 1 -#define STM32WB_SYSCLK_FREQUENCY 64000000ul +#define STM32_SYSCLK_FREQUENCY 64000000ul /* Prescaler common to all PLL inputs; will be 2 */ -#define STM32WB_PLLCFG_PLLM RCC_PLLCFG_PLLM(2) +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(2) /* 'main' PLL config; we use this to generate our system clock via the R * output. We set it up as (((32MHz / 2) * 12) / 3) = 64MHz * And the Q output is set as (((32MHz / 2) * 12) / 4) = 48MHz */ -#define STM32WB_PLLCFG_PLLN RCC_PLLCFG_PLLN(12) -#define STM32WB_PLLCFG_PLLR_ENABLED -#define STM32WB_PLLCFG_PLLR RCC_PLLCFG_PLLR(3) -#define STM32WB_PLLCFG_PLLQ_ENABLED -#define STM32WB_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(4) +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(12) +#define STM32_PLLCFG_PLLR_ENABLED +#define STM32_PLLCFG_PLLR RCC_PLLCFG_PLLR(3) +#define STM32_PLLCFG_PLLQ_ENABLED +#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(4) /* 'SAIPLL1' is not used */ -#define STM32WB_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(8) +#define STM32_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(8) /* CLK48 will come from the PLLMAIN via the Q output */ -#define STM32WB_USE_CLK48 1 -#define STM32WB_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLMAIN -#define STM32WB_HSI48_SYNCSRC SYNCSRC_NONE +#define STM32_USE_CLK48 1 +#define STM32_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLMAIN +#define STM32_HSI48_SYNCSRC SYNCSRC_NONE /* Enable LSE (for the RTC) */ -#define STM32WB_USE_LSE 1 +#define STM32_USE_LSE 1 #elif defined(MSI_CLOCK_CONFIG) /* Use the MSI */ -#define STM32WB_BOARD_USEMSI 1 +#define STM32_BOARD_USEMSI 1 -#define STM32WB_BOARD_MSIRANGE RCC_CR_MSIRANGE_4M +#define STM32_BOARD_MSIRANGE RCC_CR_MSIRANGE_4M -#define STM32WB_SYSCLK_FREQUENCY 64000000ul +#define STM32_SYSCLK_FREQUENCY 64000000ul /* Prescaler common to all PLL inputs; will be 1 */ -#define STM32WB_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) /* 'main' PLL config; we use this to generate our system clock via the R * output. We set it up as (((4MHz / 1) * 48) / 3) = 64MHz * And the Q output is set as (((4MHz / 1) * 48) / 4) = 48MHz */ -#define STM32WB_PLLCFG_PLLN RCC_PLLCFG_PLLN(48) -#define STM32WB_PLLCFG_PLLR_ENABLED -#define STM32WB_PLLCFG_PLLR RCC_PLLCFG_PLLR(3) -#define STM32WB_PLLCFG_PLLQ_ENABLED -#define STM32WB_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(4) +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(48) +#define STM32_PLLCFG_PLLR_ENABLED +#define STM32_PLLCFG_PLLR RCC_PLLCFG_PLLR(3) +#define STM32_PLLCFG_PLLQ_ENABLED +#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(4) /* 'SAIPLL1' is not used */ -#define STM32WB_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(8) +#define STM32_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(8) /* CLK48 will come from the PLLMAIN via the Q output */ -#define STM32WB_USE_CLK48 1 -#define STM32WB_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLMAIN -#define STM32WB_HSI48_SYNCSRC SYNCSRC_NONE +#define STM32_USE_CLK48 1 +#define STM32_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLMAIN +#define STM32_HSI48_SYNCSRC SYNCSRC_NONE /* Enable the LSE oscillator, used automatically trim the MSI, and for RTC */ -#define STM32WB_USE_LSE 1 +#define STM32_USE_LSE 1 #endif /* AHB clock (HCLK) is SYSCLK (64MHz) */ -#define BOARD_AHB_FREQUENCY STM32WB_SYSCLK_FREQUENCY +#define BOARD_AHB_FREQUENCY STM32_SYSCLK_FREQUENCY -#define STM32WB_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK -#define STM32WB_HCLK_FREQUENCY STM32WB_SYSCLK_FREQUENCY +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY /* CPU2 clock (HCLK2) is SYSCLK/2 (32MHz) */ -#define STM32WB_RCC_EXTCFGR_C2HPRE RCC_EXTCFGR_C2HPRE_2 +#define STM32_RCC_EXTCFGR_C2HPRE RCC_EXTCFGR_C2HPRE_2 /* AHB4 clock (HCLK4) is SYSCLK (64MHz) */ -#define STM32WB_RCC_EXTCFGR_SHDHPRE RCC_EXTCFGR_SHDHPRE_1 +#define STM32_RCC_EXTCFGR_SHDHPRE RCC_EXTCFGR_SHDHPRE_1 /* APB1 clock (PCLK1) is HCLK/1 (64MHz) */ -#define STM32WB_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK1 -#define STM32WB_PCLK1_FREQUENCY (STM32WB_HCLK_FREQUENCY / 1) +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK1 +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY / 1) /* APB2 clock (PCLK2) is HCLK/1 (64MHz) */ -#define STM32WB_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK1 -#define STM32WB_PCLK2_FREQUENCY (STM32WB_HCLK_FREQUENCY / 1) +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK1 +#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY / 1) /* Timer Frequencies, if APB prescaler is set to 1, frequency is same to APBx * otherwise frequency is 2xAPBx. @@ -219,18 +219,18 @@ /* Timers driven from APB1 will be the same frequency as PCLK1 */ -#define STM32WB_APB1_TIM2_CLKIN (1 * STM32WB_PCLK1_FREQUENCY) +#define STM32_APB1_TIM2_CLKIN (1 * STM32_PCLK1_FREQUENCY) /* Timers driven from APB2 will be the same frequency as PCLK2 */ -#define STM32WB_APB2_TIM1_CLKIN (1 * STM32WB_PCLK2_FREQUENCY) -#define STM32WB_APB2_TIM16_CLKIN (1 * STM32WB_PCLK2_FREQUENCY) -#define STM32WB_APB2_TIM17_CLKIN (1 * STM32WB_PCLK2_FREQUENCY) +#define STM32_APB2_TIM1_CLKIN (1 * STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM16_CLKIN (1 * STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM17_CLKIN (1 * STM32_PCLK2_FREQUENCY) -#define BOARD_TIM1_FREQUENCY STM32WB_APB2_TIM1_CLKIN -#define BOARD_TIM2_FREQUENCY STM32WB_APB1_TIM2_CLKIN -#define BOARD_TIM16_FREQUENCY STM32WB_APB2_TIM16_CLKIN -#define BOARD_TIM17_FREQUENCY STM32WB_APB2_TIM17_CLKIN +#define BOARD_TIM1_FREQUENCY STM32_APB2_TIM1_CLKIN +#define BOARD_TIM2_FREQUENCY STM32_APB1_TIM2_CLKIN +#define BOARD_TIM16_FREQUENCY STM32_APB2_TIM16_CLKIN +#define BOARD_TIM17_FREQUENCY STM32_APB2_TIM17_CLKIN /* Higher SYSCLK requires more flash wait states. */ @@ -261,4 +261,4 @@ extern "C" #endif #endif /* __ASSEMBLY__ */ -#endif /* __BOARDS_ARM_STM32WB_NUCLEO_WB55RG_INCLUDE_NUCLEO_WB55RG_H */ +#endif /* __BOARDS_ARM_STM32_NUCLEO_WB55RG_INCLUDE_NUCLEO_WB55RG_H */ diff --git a/boards/arm/stm32wb/nucleo-wb55rg/src/Make.defs b/boards/arm/stm32wb/nucleo-wb55rg/src/Make.defs new file mode 100644 index 0000000000000..6b303424bf7dd --- /dev/null +++ b/boards/arm/stm32wb/nucleo-wb55rg/src/Make.defs @@ -0,0 +1,35 @@ +############################################################################ +# boards/arm/stm32wb/nucleo-wb55rg/src/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +CSRCS = stm32_boot.c + +ifeq ($(CONFIG_ARCH_LEDS),y) +CSRCS += stm32_autoleds.c +else +CSRCS += stm32_userleds.c +endif + +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32wb/nucleo-wb55rg/src/Makefile b/boards/arm/stm32wb/nucleo-wb55rg/src/Makefile deleted file mode 100644 index 11d004aa68c5c..0000000000000 --- a/boards/arm/stm32wb/nucleo-wb55rg/src/Makefile +++ /dev/null @@ -1,33 +0,0 @@ -############################################################################ -# boards/arm/stm32wb/nucleo-wb55rg/src/Makefile -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/Make.defs - -CSRCS = stm32_boot.c - -ifeq ($(CONFIG_ARCH_LEDS),y) -CSRCS += stm32_autoleds.c -else -CSRCS += stm32_userleds.c -endif - -include $(TOPDIR)/boards/Board.mk diff --git a/boards/arm/stm32wb/nucleo-wb55rg/src/nucleo-wb55rg.h b/boards/arm/stm32wb/nucleo-wb55rg/src/nucleo-wb55rg.h index 3a3dc06255c92..89179756bec40 100644 --- a/boards/arm/stm32wb/nucleo-wb55rg/src/nucleo-wb55rg.h +++ b/boards/arm/stm32wb/nucleo-wb55rg/src/nucleo-wb55rg.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32WB_NUCLEO_WB55RG_SRC_NUCLEO_WB55RG_H -#define __BOARDS_ARM_STM32WB_NUCLEO_WB55RG_SRC_NUCLEO_WB55RG_H +#ifndef __BOARDS_ARM_STM32_NUCLEO_WB55RG_SRC_NUCLEO_WB55RG_H +#define __BOARDS_ARM_STM32_NUCLEO_WB55RG_SRC_NUCLEO_WB55RG_H /**************************************************************************** * Included Files @@ -97,4 +97,4 @@ ****************************************************************************/ #endif /* __ASSEMBLY__ */ -#endif /* __BOARDS_ARM_STM32WB_NUCLEO_WB55RG_SRC_NUCLEO_WB55RG_H */ +#endif /* __BOARDS_ARM_STM32_NUCLEO_WB55RG_SRC_NUCLEO_WB55RG_H */ diff --git a/boards/arm/stm32wb/nucleo-wb55rg/src/stm32_autoleds.c b/boards/arm/stm32wb/nucleo-wb55rg/src/stm32_autoleds.c index 1b81d27c678ea..61ff88b7ea0cd 100644 --- a/boards/arm/stm32wb/nucleo-wb55rg/src/stm32_autoleds.c +++ b/boards/arm/stm32wb/nucleo-wb55rg/src/stm32_autoleds.c @@ -34,7 +34,7 @@ #include "chip.h" #include "arm_internal.h" -#include "stm32wb.h" +#include "stm32.h" #include "nucleo-wb55rg.h" #ifdef CONFIG_ARCH_LEDS @@ -51,9 +51,9 @@ void board_autoled_initialize(void) { /* Configure LEDs GPIO for output. Initial state is OFF */ - stm32wb_configgpio(GPIO_LED1); - stm32wb_configgpio(GPIO_LED2); - stm32wb_configgpio(GPIO_LED3); + stm32_configgpio(GPIO_LED1); + stm32_configgpio(GPIO_LED2); + stm32_configgpio(GPIO_LED3); } /**************************************************************************** @@ -68,15 +68,15 @@ void board_autoled_on(int led) break; case BOARD_LED1: - stm32wb_gpiowrite(GPIO_LED1, true); + stm32_gpiowrite(GPIO_LED1, true); break; case BOARD_LED2: - stm32wb_gpiowrite(GPIO_LED2, true); + stm32_gpiowrite(GPIO_LED2, true); break; case BOARD_LED3: - stm32wb_gpiowrite(GPIO_LED3, true); + stm32_gpiowrite(GPIO_LED3, true); break; } } @@ -93,15 +93,15 @@ void board_autoled_off(int led) break; case BOARD_LED1: - stm32wb_gpiowrite(GPIO_LED1, false); + stm32_gpiowrite(GPIO_LED1, false); break; case BOARD_LED2: - stm32wb_gpiowrite(GPIO_LED2, false); + stm32_gpiowrite(GPIO_LED2, false); break; case BOARD_LED3: - stm32wb_gpiowrite(GPIO_LED3, false); + stm32_gpiowrite(GPIO_LED3, false); break; } } diff --git a/boards/arm/stm32wb/nucleo-wb55rg/src/stm32_boot.c b/boards/arm/stm32wb/nucleo-wb55rg/src/stm32_boot.c index a8199219abe59..ff849aff0dbc2 100644 --- a/boards/arm/stm32wb/nucleo-wb55rg/src/stm32_boot.c +++ b/boards/arm/stm32wb/nucleo-wb55rg/src/stm32_boot.c @@ -47,7 +47,7 @@ # include "stm32wb_rtc.h" #endif -#ifdef CONFIG_STM32WB_BLE +#ifdef CONFIG_STM32_BLE # include "stm32wb_blehci.h" #endif @@ -58,7 +58,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_board_initialize + * Name: stm32_board_initialize * * Description: * All STM32WB architectures must provide the following entry point. This @@ -68,7 +68,7 @@ * ****************************************************************************/ -void stm32wb_board_initialize(void) +void stm32_board_initialize(void) { /* Configure on-board LEDs if LED support has been selected. */ @@ -131,7 +131,7 @@ void board_late_initialize(void) #ifdef CONFIG_RTC_DRIVER /* Instantiate the STM32WB lower-half RTC driver */ - rtclower = stm32wb_rtc_lowerhalf(); + rtclower = stm32_rtc_lowerhalf(); if (!rtclower) { serr("ERROR: Failed to instantiate the RTC lower-half driver\n"); @@ -155,7 +155,7 @@ void board_late_initialize(void) #ifdef CONFIG_TIMER /* Initialize and register the timer driver */ - ret = stm32wb_timer_initialize("/dev/timer0", 1); + ret = stm32_timer_initialize("/dev/timer0", 1); if (ret < 0) { syslog(LOG_ERR, "ERROR: Failed to register the timer driver: %d\n", @@ -164,10 +164,10 @@ void board_late_initialize(void) } #endif -#ifdef CONFIG_STM32WB_BLE +#ifdef CONFIG_STM32_BLE /* Initialize and register BLE HCI driver */ - stm32wb_blehci_initialize(); + stm32_blehci_initialize(); #endif UNUSED(ret); } @@ -188,7 +188,7 @@ int board_uniqueid(uint8_t *uniqueid) return -EINVAL; } - stm32wb_get_uniqueid(uniqueid); + stm32_get_uniqueid(uniqueid); return OK; } #endif diff --git a/boards/arm/stm32wb/nucleo-wb55rg/src/stm32_userleds.c b/boards/arm/stm32wb/nucleo-wb55rg/src/stm32_userleds.c index 054482588dfb5..6c911a423c868 100644 --- a/boards/arm/stm32wb/nucleo-wb55rg/src/stm32_userleds.c +++ b/boards/arm/stm32wb/nucleo-wb55rg/src/stm32_userleds.c @@ -35,7 +35,7 @@ #include "chip.h" #include "arm_internal.h" -#include "stm32wb.h" +#include "stm32.h" #include "nucleo-wb55rg.h" #ifndef CONFIG_ARCH_LEDS @@ -94,8 +94,8 @@ static void led_pm_notify(struct pm_callback_s *cb, int domain, { /* Entering IDLE mode - Turn leds off */ - stm32wb_gpiowrite(GPIO_LED_RED, 0); - stm32wb_gpiowrite(GPIO_LED_GREEN, 0); + stm32_gpiowrite(GPIO_LED_RED, 0); + stm32_gpiowrite(GPIO_LED_GREEN, 0); } break; @@ -103,8 +103,8 @@ static void led_pm_notify(struct pm_callback_s *cb, int domain, { /* Entering STANDBY mode - Logic for PM_STANDBY goes here */ - stm32wb_gpiowrite(GPIO_LED_RED, 0); - stm32wb_gpiowrite(GPIO_LED_GREEN, 0); + stm32_gpiowrite(GPIO_LED_RED, 0); + stm32_gpiowrite(GPIO_LED_GREEN, 0); } break; @@ -112,8 +112,8 @@ static void led_pm_notify(struct pm_callback_s *cb, int domain, { /* Entering SLEEP mode - Logic for PM_SLEEP goes here */ - stm32wb_gpiowrite(GPIO_LED_RED, 0); - stm32wb_gpiowrite(GPIO_LED_GREEN, 0); + stm32_gpiowrite(GPIO_LED_RED, 0); + stm32_gpiowrite(GPIO_LED_GREEN, 0); } break; @@ -160,9 +160,9 @@ static int led_pm_prepare(struct pm_callback_s *cb, int domain, uint32_t board_userled_initialize(void) { - stm32wb_configgpio(GPIO_LED_RED); - stm32wb_configgpio(GPIO_LED_GREEN); - stm32wb_configgpio(GPIO_LED_BLUE); + stm32_configgpio(GPIO_LED_RED); + stm32_configgpio(GPIO_LED_GREEN); + stm32_configgpio(GPIO_LED_BLUE); return BOARD_NLEDS; } @@ -178,15 +178,15 @@ void board_userled(int led, bool ledon) break; case BOARD_LED_RED: - stm32wb_gpiowrite(GPIO_LED_RED, ledon); + stm32_gpiowrite(GPIO_LED_RED, ledon); break; case GPIO_LED_GREEN: - stm32wb_gpiowrite(GPIO_LED_GREEN, ledon); + stm32_gpiowrite(GPIO_LED_GREEN, ledon); break; case GPIO_LED_BLUE: - stm32wb_gpiowrite(GPIO_LED_BLUE, ledon); + stm32_gpiowrite(GPIO_LED_BLUE, ledon); break; } } @@ -197,9 +197,9 @@ void board_userled(int led, bool ledon) void board_userled_all(uint32_t ledset) { - stm32wb_gpiowrite(GPIO_LED1, (ledset & BOARD_LED1_BIT) != 0); - stm32wb_gpiowrite(GPIO_LED2, (ledset & BOARD_LED2_BIT) != 0); - stm32wb_gpiowrite(GPIO_LED3, (ledset & BOARD_LED3_BIT) != 0); + stm32_gpiowrite(GPIO_LED1, (ledset & BOARD_LED1_BIT) != 0); + stm32_gpiowrite(GPIO_LED2, (ledset & BOARD_LED2_BIT) != 0); + stm32_gpiowrite(GPIO_LED3, (ledset & BOARD_LED3_BIT) != 0); } /**************************************************************************** diff --git a/boards/arm/stm32wl5/common/CMakeLists.txt b/boards/arm/stm32wl5/common/CMakeLists.txt new file mode 100644 index 0000000000000..1d22b5ae29426 --- /dev/null +++ b/boards/arm/stm32wl5/common/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32wl5/common/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(${NUTTX_DIR}/boards/arm/common/stm32 stm32_common) diff --git a/boards/arm/stm32wl5/common/Makefile b/boards/arm/stm32wl5/common/Makefile new file mode 100644 index 0000000000000..6eef4c90d504f --- /dev/null +++ b/boards/arm/stm32wl5/common/Makefile @@ -0,0 +1,36 @@ +############################################################################# +# boards/arm/stm32wl5/common/Makefile +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################# + +include $(TOPDIR)/Make.defs + +STM32_BOARD_COMMON_DIR := $(TOPDIR)$(DELIM)boards$(DELIM)arm$(DELIM)common$(DELIM)stm32 + +include board/Make.defs +include $(STM32_BOARD_COMMON_DIR)$(DELIM)src$(DELIM)Make.defs + +DEPPATH += --dep-path board + +include $(TOPDIR)/boards/Board.mk + +ARCHSRCDIR = $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src +BOARDDIR = $(ARCHSRCDIR)$(DELIM)board +CFLAGS += ${INCDIR_PREFIX}$(BOARDDIR)$(DELIM)include diff --git a/boards/arm/stm32wl5/nucleo-wl55jc/Kconfig b/boards/arm/stm32wl5/nucleo-wl55jc/Kconfig index 411801e17de7f..f66ff2ef2e61f 100644 --- a/boards/arm/stm32wl5/nucleo-wl55jc/Kconfig +++ b/boards/arm/stm32wl5/nucleo-wl55jc/Kconfig @@ -24,7 +24,7 @@ config ARCH_BOARD_ENABLE_CPU2 menuconfig ARCH_BOARD_IPCC bool "Enabled IPCC" select IPCC - select STM32WL5_IPCC + select STM32_IPCC default n ---help--- Enables IPCC (inter processor communication controller) @@ -52,7 +52,7 @@ config ARCH_BOARD_IPCC_CHAN1_TXBUF config ARCH_BOARD_IPCC_CHAN2 bool "Enable channel 2" default n - select STM32WL5_IPCC_CHAN2 + select STM32_IPCC_CHAN2 if ARCH_BOARD_IPCC_CHAN2 @@ -69,7 +69,7 @@ config ARCH_BOARD_IPCC_CHAN2_TXBUF config ARCH_BOARD_IPCC_CHAN3 bool "Enable channel 3" default n - select STM32WL5_IPCC_CHAN3 + select STM32_IPCC_CHAN3 if ARCH_BOARD_IPCC_CHAN3 @@ -86,7 +86,7 @@ config ARCH_BOARD_IPCC_CHAN3_TXBUF config ARCH_BOARD_IPCC_CHAN4 bool "Enable channel 4" default n - select STM32WL5_IPCC_CHAN4 + select STM32_IPCC_CHAN4 if ARCH_BOARD_IPCC_CHAN4 @@ -103,7 +103,7 @@ config ARCH_BOARD_IPCC_CHAN4_TXBUF config ARCH_BOARD_IPCC_CHAN5 bool "Enable channel 5" default n - select STM32WL5_IPCC_CHAN5 + select STM32_IPCC_CHAN5 if ARCH_BOARD_IPCC_CHAN5 @@ -120,7 +120,7 @@ config ARCH_BOARD_IPCC_CHAN5_TXBUF config ARCH_BOARD_IPCC_CHAN6 bool "Enable channel 6" default n - select STM32WL5_IPCC_CHAN6 + select STM32_IPCC_CHAN6 if ARCH_BOARD_IPCC_CHAN6 diff --git a/boards/arm/stm32wl5/nucleo-wl55jc/configs/demo/defconfig b/boards/arm/stm32wl5/nucleo-wl55jc/configs/demo/defconfig index 1074e1f8d0ba1..7a097b223f4bc 100644 --- a/boards/arm/stm32wl5/nucleo-wl55jc/configs/demo/defconfig +++ b/boards/arm/stm32wl5/nucleo-wl55jc/configs/demo/defconfig @@ -28,6 +28,7 @@ CONFIG_ARCH_BOARD_NUCLEO_WL55JC=y CONFIG_ARCH_BOARD_NUCLEO_WL55JC_DEMO_LED_IRQ=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32wl5" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32WL55JC_CPU1=y CONFIG_ARCH_CHIP_STM32WL5=y CONFIG_ARCH_IRQBUTTONS=y @@ -48,7 +49,7 @@ CONFIG_NSH_BUILTIN_APPS=y CONFIG_RAM_SIZE=32768 CONFIG_RAM_START=0x20000000 CONFIG_RAW_BINARY=y -CONFIG_STM32WL5_LPUART1=y +CONFIG_STM32_LPUART1=y CONFIG_SYSTEM_CFGDATA=y CONFIG_SYSTEM_NSH=y CONFIG_USERLED=y diff --git a/boards/arm/stm32wl5/nucleo-wl55jc/configs/fb/defconfig b/boards/arm/stm32wl5/nucleo-wl55jc/configs/fb/defconfig index 3c5150dc6a9f5..ebc8bd12c3a94 100644 --- a/boards/arm/stm32wl5/nucleo-wl55jc/configs/fb/defconfig +++ b/boards/arm/stm32wl5/nucleo-wl55jc/configs/fb/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH_BOARD_COMMON=y CONFIG_ARCH_BOARD_NUCLEO_WL55JC=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32wl5" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32WL55JC_CPU1=y CONFIG_ARCH_CHIP_STM32WL5=y CONFIG_BOARD_LOOPSPERMSEC=0 @@ -33,9 +34,9 @@ CONFIG_RAM_START=0x20000000 CONFIG_RAW_BINARY=y CONFIG_SPI=y CONFIG_SPI_DRIVER=y -CONFIG_STM32WL5_LPUART1=y -CONFIG_STM32WL5_SPI1=y -CONFIG_STM32WL5_SPI2S2=y -CONFIG_STM32WL5_USART1=y +CONFIG_STM32_LPUART1=y +CONFIG_STM32_SPI1=y +CONFIG_STM32_SPI2S2=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_VIDEO_FB=y diff --git a/boards/arm/stm32wl5/nucleo-wl55jc/configs/nsh/defconfig b/boards/arm/stm32wl5/nucleo-wl55jc/configs/nsh/defconfig index 9318532b4a1d9..7a7e9b2a68bc1 100644 --- a/boards/arm/stm32wl5/nucleo-wl55jc/configs/nsh/defconfig +++ b/boards/arm/stm32wl5/nucleo-wl55jc/configs/nsh/defconfig @@ -11,6 +11,7 @@ CONFIG_ARCH_BOARD="nucleo-wl55jc" CONFIG_ARCH_BOARD_NUCLEO_WL55JC=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32wl5" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32WL55JC_CPU1=y CONFIG_ARCH_CHIP_STM32WL5=y CONFIG_BOARD_LOOPSPERMSEC=0 @@ -20,5 +21,5 @@ CONFIG_LPUART1_SERIAL_CONSOLE=y CONFIG_RAM_SIZE=32768 CONFIG_RAM_START=0x20000000 CONFIG_RAW_BINARY=y -CONFIG_STM32WL5_LPUART1=y +CONFIG_STM32_LPUART1=y CONFIG_SYSTEM_NSH=y diff --git a/boards/arm/stm32wl5/nucleo-wl55jc/include/board.h b/boards/arm/stm32wl5/nucleo-wl55jc/include/board.h index 673b0232ecb88..9616e510d43d0 100644 --- a/boards/arm/stm32wl5/nucleo-wl55jc/include/board.h +++ b/boards/arm/stm32wl5/nucleo-wl55jc/include/board.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32WL5_NUCLEO_WL55JC_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32WL5_NUCLEO_WL55JC_INCLUDE_BOARD_H +#ifndef __BOARDS_ARM_STM32_NUCLEO_WL55JC_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32_NUCLEO_WL55JC_INCLUDE_BOARD_H /**************************************************************************** * Included Files @@ -36,72 +36,72 @@ /* nucleo-wl55jc has installed 32Mhz HSE oscillator */ -#define STM32WL5_XTAL_FREQ 32000000ul +#define STM32_XTAL_FREQ 32000000ul /* Use the HSE */ -#define STM32WL5_BOARD_USEHSE 1 +#define STM32_BOARD_USEHSE 1 /* HSE source is a TCXO crystal which needs to be first powered on */ -#define STM32WL5_BOARD_USETCXO +#define STM32_BOARD_USETCXO /* Prescaler common to all PLL inputs */ -#define STM32WL5_PLLCFG_PLLM RCC_PLLCFG_PLLM(2) /* 32MHz / 2 = 16MHz */ +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(2) /* 32MHz / 2 = 16MHz */ /* 'main' PLL config; we use this to generate our system clock */ /* disable unused pll clocks */ -#define STM32WL5_PLLCFG_PLLP 0 -#undef STM32WL5_PLLCFG_PLLP_ENABLED -#define STM32WL5_PLLCFG_PLLQ 0 -#undef STM32WL5_PLLCFG_PLLQ_ENABLED +#define STM32_PLLCFG_PLLP 0 +#undef STM32_PLLCFG_PLLP_ENABLED +#define STM32_PLLCFG_PLLQ 0 +#undef STM32_PLLCFG_PLLQ_ENABLED /* further multiplicate source for system clock */ -#define STM32WL5_PLLCFG_PLLN RCC_PLLCFG_PLLN(6) /* 16MHz * 6 = 96MHz */ -#define STM32WL5_PLLCFG_PLLR RCC_PLLCFG_PLLR(2) /* 96MHz / 2 = 48MHz */ -#define STM32WL5_PLLCFG_PLLR_ENABLED +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(6) /* 16MHz * 6 = 96MHz */ +#define STM32_PLLCFG_PLLR RCC_PLLCFG_PLLR(2) /* 96MHz / 2 = 48MHz */ +#define STM32_PLLCFG_PLLR_ENABLED /* Resulting system clock is 48MHz */ -#define STM32WL5_SYSCLK_FREQUENCY 48000000ul +#define STM32_SYSCLK_FREQUENCY 48000000ul /* Configure the HCLK divisor (for the AHB bus, core, memory, and DMA */ -#define STM32WL5_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ -#define STM32WL5_HCLK_FREQUENCY STM32WL5_SYSCLK_FREQUENCY +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY /* Configure the HCLK3 divisor (for flash and sram2) */ -#define STM32WL5_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK3 = SYSCLK / 1 */ -#define STM32WL5_HCLK3_FREQUENCY STM32WL5_SYSCLK_FREQUENCY +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK3 = SYSCLK / 1 */ +#define STM32_HCLK3_FREQUENCY STM32_SYSCLK_FREQUENCY /* Configure the APB1 prescaler */ -#define STM32WL5_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ -#define STM32WL5_PCLK1_FREQUENCY (STM32WL5_HCLK_FREQUENCY / 1) +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY / 1) /* The timer clock frequencies are automatically defined by hardware. * If the APB prescaler equals 1, the timer clock frequencies are set to the * same frequency as that of the APB domain. Otherwise they are set to twice. */ -#define STM32WL5_APB1_TIM2_CLKIN (STM32WL5_PCLK1_FREQUENCY) +#define STM32_APB1_TIM2_CLKIN (STM32_PCLK1_FREQUENCY) /* Configure the APB2 prescaler */ -#define STM32WL5_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ -#define STM32WL5_PCLK2_FREQUENCY (STM32WL5_HCLK_FREQUENCY / 1) +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ +#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY / 1) /* The timer clock frequencies are automatically defined by hardware. * If the APB prescaler equals 1, the timer clock frequencies are set to the * same frequency as that of the APB domain. Otherwise they are set to twice. */ -#define STM32WL5_APB2_TIM1_CLKIN STM32WL5_PCLK2_FREQUENCY -#define STM32WL5_APB2_TIM16_CLKIN STM32WL5_PCLK2_FREQUENCY -#define STM32WL5_APB2_TIM17_CLKIN STM32WL5_PCLK2_FREQUENCY +#define STM32_APB2_TIM1_CLKIN STM32_PCLK2_FREQUENCY +#define STM32_APB2_TIM16_CLKIN STM32_PCLK2_FREQUENCY +#define STM32_APB2_TIM17_CLKIN STM32_PCLK2_FREQUENCY /* The timer clock frequencies are automatically defined by hardware. If the * APB prescaler equals 1, the timer clock frequencies are set to the same @@ -109,13 +109,13 @@ * Note: TIM1,15,16 are on APB2, others on APB1 */ -#define BOARD_TIM1_FREQUENCY STM32WL5_HCLK_FREQUENCY -#define BOARD_TIM2_FREQUENCY STM32WL5_HCLK_FREQUENCY -#define BOARD_TIM16_FREQUENCY STM32WL5_HCLK_FREQUENCY -#define BOARD_TIM17_FREQUENCY STM32WL5_HCLK_FREQUENCY -#define BOARD_LPTIM1_FREQUENCY STM32WL5_HCLK_FREQUENCY -#define BOARD_LPTIM2_FREQUENCY STM32WL5_HCLK_FREQUENCY -#define BOARD_LPTIM3_FREQUENCY STM32WL5_HCLK_FREQUENCY +#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM2_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM16_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM17_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_LPTIM1_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_LPTIM2_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_LPTIM3_FREQUENCY STM32_HCLK_FREQUENCY /**************************************************************************** * Pre-processor Definitions @@ -231,7 +231,7 @@ extern "C" ****************************************************************************/ /**************************************************************************** - * Name: stm32wl5_board_initialize + * Name: stm32_board_initialize * * Description: * All STM32WL5 architectures must provide the following entry point. @@ -241,7 +241,7 @@ extern "C" * ****************************************************************************/ -void stm32wl5_board_initialize(void); +void stm32_board_initialize(void); #undef EXTERN #if defined(__cplusplus) @@ -249,4 +249,4 @@ void stm32wl5_board_initialize(void); #endif #endif /* __ASSEMBLY__ */ -#endif /* __BOARDS_ARM_STM32WL5_NUCLEO_WL55JC_INCLUDE_BOARD_H */ +#endif /* __BOARDS_ARM_STM32_NUCLEO_WL55JC_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32wl5/nucleo-wl55jc/src/Make.defs b/boards/arm/stm32wl5/nucleo-wl55jc/src/Make.defs new file mode 100644 index 0000000000000..6f8be0ff7f864 --- /dev/null +++ b/boards/arm/stm32wl5/nucleo-wl55jc/src/Make.defs @@ -0,0 +1,42 @@ +############################################################################ +# boards/arm/stm32wl5/nucleo-wl55jc/src/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +CSRCS = stm32_boot.c stm32_leds.c + +CSRCS-$(CONFIG_ARCH_BUTTONS) += stm32_buttons.c +CSRCS-$(CONFIG_ARCH_BOARD_FLASH_MOUNT) += stm32_flash.c +CSRCS-$(CONFIG_SPI_DRIVER) += stm32_spi.c +CSRCS-$(CONFIG_ARCH_BOARD_IPCC) += stm32_ipcc.c + +ifeq ($(CONFIG_VIDEO_FB),y) +ifeq ($(CONFIG_LCD_SSD1680),y) + CSRCS += stm32_ssd1680.c +endif +endif + +CSRCS += $(CSRCS-y) + +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32wl5/nucleo-wl55jc/src/Makefile b/boards/arm/stm32wl5/nucleo-wl55jc/src/Makefile deleted file mode 100644 index 1c280874bc539..0000000000000 --- a/boards/arm/stm32wl5/nucleo-wl55jc/src/Makefile +++ /dev/null @@ -1,40 +0,0 @@ -############################################################################ -# boards/arm/stm32wl5/nucleo-wl55jc/src/Makefile -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/Make.defs - -CSRCS = stm32_boot.c stm32_leds.c - -CSRCS-$(CONFIG_ARCH_BUTTONS) += stm32_buttons.c -CSRCS-$(CONFIG_ARCH_BOARD_FLASH_MOUNT) += stm32_flash.c -CSRCS-$(CONFIG_SPI_DRIVER) += stm32_spi.c -CSRCS-$(CONFIG_ARCH_BOARD_IPCC) += stm32_ipcc.c - -ifeq ($(CONFIG_VIDEO_FB),y) -ifeq ($(CONFIG_LCD_SSD1680),y) - CSRCS += stm32_ssd1680.c -endif -endif - -CSRCS += $(CSRCS-y) - -include $(TOPDIR)/boards/Board.mk diff --git a/boards/arm/stm32wl5/nucleo-wl55jc/src/nucleo-wl55jc.h b/boards/arm/stm32wl5/nucleo-wl55jc/src/nucleo-wl55jc.h index c25831b622ef4..adce7b8ed71aa 100644 --- a/boards/arm/stm32wl5/nucleo-wl55jc/src/nucleo-wl55jc.h +++ b/boards/arm/stm32wl5/nucleo-wl55jc/src/nucleo-wl55jc.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32WL5_NUCLEO_WL55JC_SRC_NUCLEO_WL55JC_H -#define __BOARDS_ARM_STM32WL5_NUCLEO_WL55JC_SRC_NUCLEO_WL55JC_H +#ifndef __BOARDS_ARM_STM32_NUCLEO_WL55JC_SRC_NUCLEO_WL55JC_H +#define __BOARDS_ARM_STM32_NUCLEO_WL55JC_SRC_NUCLEO_WL55JC_H /**************************************************************************** * Included Files @@ -31,7 +31,7 @@ #include #include -#include +#include /**************************************************************************** * Pre-processor Definitions @@ -148,24 +148,24 @@ void board_leds_initialize(void); /**************************************************************************** - * Name: stm32wl5_flash_init + * Name: stm32_flash_init * * Description: * Initialize on-board FLASH partition table * ****************************************************************************/ -int stm32wl5_flash_init(void); +int stm32_flash_init(void); /**************************************************************************** - * Name: stm32wl5_spidev_initialize + * Name: stm32_spidev_initialize * * Description: * Initialize SPIs * ****************************************************************************/ -void stm32wl5_spidev_initialize(void); +void stm32_spidev_initialize(void); /**************************************************************************** * Name: ipcc_init @@ -177,4 +177,4 @@ void stm32wl5_spidev_initialize(void); int ipcc_init(void); -#endif /* __BOARDS_ARM_STM32WL5_NUCLEO_WL55JC_SRC_NUCLEO_WL55JC_H */ +#endif /* __BOARDS_ARM_STM32_NUCLEO_WL55JC_SRC_NUCLEO_WL55JC_H */ diff --git a/boards/arm/stm32wl5/nucleo-wl55jc/src/stm32_boot.c b/boards/arm/stm32wl5/nucleo-wl55jc/src/stm32_boot.c index b823f818470ad..86454d000626f 100644 --- a/boards/arm/stm32wl5/nucleo-wl55jc/src/stm32_boot.c +++ b/boards/arm/stm32wl5/nucleo-wl55jc/src/stm32_boot.c @@ -47,7 +47,7 @@ #include #endif -#include +#include #include #include @@ -73,7 +73,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32wl5_board_initialize + * Name: stm32_board_initialize * * Description: * All STM32WL5 architectures must provide the following entry point. @@ -83,7 +83,7 @@ * ****************************************************************************/ -void stm32wl5_board_initialize(void) +void stm32_board_initialize(void) { /* Configure on-board LEDs, which are always enabled */ @@ -108,8 +108,8 @@ void board_late_initialize(void) { int ret; -#if defined(CONFIG_STM32WL5_SPI1) || defined(CONFIG_STM32WL5_SPI2S2) - stm32wl5_spidev_initialize(); +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2S2) + stm32_spidev_initialize(); #endif #if defined(CONFIG_LCD_SSD1680) && !defined(CONFIG_VIDEO_FB) @@ -161,10 +161,10 @@ void board_late_initialize(void) #if defined(CONFIG_ARCH_BOARD_FLASH_MOUNT) /* Register partition table for on-board FLASH memory */ - ret = stm32wl5_flash_init(); + ret = stm32_flash_init(); if (ret < 0) { - syslog(LOG_ERR, "ERROR: stm32wl5_flash_init() failed: %d\n", ret); + syslog(LOG_ERR, "ERROR: stm32_flash_init() failed: %d\n", ret); } #endif @@ -181,7 +181,7 @@ void board_late_initialize(void) #if defined(CONFIG_ARCH_BOARD_ENABLE_CPU2) /* Start second CPU */ - stm32wl5_pwr_boot_c2(); + stm32_pwr_boot_c2(); #endif UNUSED(ret); @@ -203,7 +203,7 @@ int board_uniqueid(uint8_t *uniqueid) return -EINVAL; } - stm32wl5_get_uniqueid(uniqueid); + stm32_get_uniqueid(uniqueid); return OK; } #endif diff --git a/boards/arm/stm32wl5/nucleo-wl55jc/src/stm32_buttons.c b/boards/arm/stm32wl5/nucleo-wl55jc/src/stm32_buttons.c index adf9448398ce6..1ef9e8a33d030 100644 --- a/boards/arm/stm32wl5/nucleo-wl55jc/src/stm32_buttons.c +++ b/boards/arm/stm32wl5/nucleo-wl55jc/src/stm32_buttons.c @@ -57,10 +57,10 @@ uint32_t board_button_initialize(void) * also configured for the pin. */ - stm32wl5_configgpio(GPIO_BUTTON1); - stm32wl5_configgpio(GPIO_BUTTON2); + stm32_configgpio(GPIO_BUTTON1); + stm32_configgpio(GPIO_BUTTON2); #ifndef CONFIG_ARCH_BOARD_NUCLEO_WL55JC_DEMO_LED_IRQ - stm32wl5_configgpio(GPIO_BUTTON3); + stm32_configgpio(GPIO_BUTTON3); return 3; /* number of buttons */ #else return 2; /* number of buttons */ @@ -81,18 +81,18 @@ uint32_t board_buttons(void) state = 0; - if (stm32wl5_gpioread(GPIO_BUTTON1) == 0) + if (stm32_gpioread(GPIO_BUTTON1) == 0) { state |= BUTTON1_BIT; } - if (stm32wl5_gpioread(GPIO_BUTTON2) == 0) + if (stm32_gpioread(GPIO_BUTTON2) == 0) { state |= BUTTON2_BIT; } #ifndef CONFIG_ARCH_BOARD_NUCLEO_WL55JC_DEMO_LED_IRQ - if (stm32wl5_gpioread(GPIO_BUTTON3) == 0) + if (stm32_gpioread(GPIO_BUTTON3) == 0) { state |= BUTTON3_BIT; } @@ -130,20 +130,20 @@ int board_button_irq(int id, xcpt_t irqhandler, void *arg) if (id == BOARD_BUTTON1) { - ret = stm32wl5_gpiosetevent(GPIO_BUTTON1, true, true, false, + ret = stm32_gpiosetevent(GPIO_BUTTON1, true, true, false, irqhandler, arg); } if (id == BOARD_BUTTON2) { - ret = stm32wl5_gpiosetevent(GPIO_BUTTON2, true, true, false, + ret = stm32_gpiosetevent(GPIO_BUTTON2, true, true, false, irqhandler, arg); } #ifndef CONFIG_ARCH_BOARD_NUCLEO_WL55JC_DEMO_LED_IRQ if (id == BOARD_BUTTON3) { - ret = stm32wl5_gpiosetevent(GPIO_BUTTON3, true, true, false, + ret = stm32_gpiosetevent(GPIO_BUTTON3, true, true, false, irqhandler, arg); } #endif diff --git a/boards/arm/stm32wl5/nucleo-wl55jc/src/stm32_flash.c b/boards/arm/stm32wl5/nucleo-wl55jc/src/stm32_flash.c index ec04c1555a604..4ae514cd0c60a 100644 --- a/boards/arm/stm32wl5/nucleo-wl55jc/src/stm32_flash.c +++ b/boards/arm/stm32wl5/nucleo-wl55jc/src/stm32_flash.c @@ -91,7 +91,7 @@ # warning "There is unused space on flash" #endif -#define FLASH_PAGE_SIZE STM32WL5_FLASH_PAGESIZE +#define FLASH_PAGE_SIZE STM32_FLASH_PAGESIZE /**************************************************************************** * Private Definitions @@ -173,7 +173,7 @@ static const struct part_table part_table[] = * Public Functions ****************************************************************************/ -int stm32wl5_flash_init(void) +int stm32_flash_init(void) { struct mtd_dev_s *mtd; struct mtd_dev_s *mtd_part; diff --git a/boards/arm/stm32wl5/nucleo-wl55jc/src/stm32_ipcc.c b/boards/arm/stm32wl5/nucleo-wl55jc/src/stm32_ipcc.c index 8d6b8f1d913c4..de0cce3e3a1d2 100644 --- a/boards/arm/stm32wl5/nucleo-wl55jc/src/stm32_ipcc.c +++ b/boards/arm/stm32wl5/nucleo-wl55jc/src/stm32_ipcc.c @@ -116,9 +116,9 @@ static int init_ipcc(int chan, size_t rxbuflen, size_t txbuflen) struct ipcc_lower_s *ipcc; int ret; - if ((ipcc = stm32wl5_ipcc_init(chan)) == NULL) + if ((ipcc = stm32_ipcc_init(chan)) == NULL) { - syslog(LOG_ERR, "ERROR: stm32wl5_ipcc_init(%d) failed\n", chan); + syslog(LOG_ERR, "ERROR: stm32_ipcc_init(%d) failed\n", chan); return -1; } diff --git a/boards/arm/stm32wl5/nucleo-wl55jc/src/stm32_leds.c b/boards/arm/stm32wl5/nucleo-wl55jc/src/stm32_leds.c index a0a23318bfd58..c276a1c52c056 100644 --- a/boards/arm/stm32wl5/nucleo-wl55jc/src/stm32_leds.c +++ b/boards/arm/stm32wl5/nucleo-wl55jc/src/stm32_leds.c @@ -35,7 +35,7 @@ #include "chip.h" #include "arm_internal.h" -#include "stm32wl5.h" +#include "stm32.h" #include "nucleo-wl55jc.h" #include @@ -64,17 +64,17 @@ static void led_state(int state, unsigned int leds) { if (leds & BOARD_LED_BLUE_BIT) { - stm32wl5_gpiowrite(GPIO_LED_BLUE, state); + stm32_gpiowrite(GPIO_LED_BLUE, state); } if (leds & BOARD_LED_RED_BIT) { - stm32wl5_gpiowrite(GPIO_LED_RED, state); + stm32_gpiowrite(GPIO_LED_RED, state); } if (leds & BOARD_LED_GREEN_BIT) { - stm32wl5_gpiowrite(GPIO_LED_GREEN, state); + stm32_gpiowrite(GPIO_LED_GREEN, state); } } @@ -93,12 +93,12 @@ static int button3_led(int irq, void *context, void *arg) (void)arg; int state; - state = stm32wl5_gpioread(GPIO_LED_RED); + state = stm32_gpioread(GPIO_LED_RED); /* toggle state */ state = !state; - stm32wl5_gpiowrite(GPIO_LED_RED, state); + stm32_gpiowrite(GPIO_LED_RED, state); return 0; } #endif @@ -113,9 +113,9 @@ static int button3_led(int irq, void *context, void *arg) void board_leds_initialize(void) { - stm32wl5_configgpio(GPIO_LED_BLUE); - stm32wl5_configgpio(GPIO_LED_RED); - stm32wl5_configgpio(GPIO_LED_GREEN); + stm32_configgpio(GPIO_LED_BLUE); + stm32_configgpio(GPIO_LED_RED); + stm32_configgpio(GPIO_LED_GREEN); } /**************************************************************************** @@ -222,7 +222,7 @@ uint32_t board_userled_initialize(void) #ifdef CONFIG_ARCH_BOARD_NUCLEO_WL55JC_DEMO_LED_IRQ /* Configure B3 button to fire an interrupt on falling edge (on press) */ - stm32wl5_gpiosetevent(GPIO_BUTTON3, false, true, false, button3_led, NULL); + stm32_gpiosetevent(GPIO_BUTTON3, false, true, false, button3_led, NULL); #endif return BOARD_NLEDS; diff --git a/boards/arm/stm32wl5/nucleo-wl55jc/src/stm32_spi.c b/boards/arm/stm32wl5/nucleo-wl55jc/src/stm32_spi.c index 1e1275e2ce4be..a3748c2db24e9 100644 --- a/boards/arm/stm32wl5/nucleo-wl55jc/src/stm32_spi.c +++ b/boards/arm/stm32wl5/nucleo-wl55jc/src/stm32_spi.c @@ -37,10 +37,10 @@ #include "arm_internal.h" #include "chip.h" -#include "stm32wl5.h" +#include "stm32.h" #include "nucleo-wl55jc.h" -#if defined(CONFIG_STM32WL5_SPI1) || defined(CONFIG_STM32WL5_SPI2S2) +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2S2) /**************************************************************************** * Public Data @@ -48,10 +48,10 @@ /* Global driver instances */ -#ifdef CONFIG_STM32WL5_SPI1 +#ifdef CONFIG_STM32_SPI1 struct spi_dev_s *g_spi1; #endif -#ifdef CONFIG_STM32WL5_SPI2S2 +#ifdef CONFIG_STM32_SPI2S2 struct spi_dev_s *g_spi2; #endif @@ -68,12 +68,12 @@ struct spi_dev_s *g_spi2; * ****************************************************************************/ -void weak_function stm32wl5_spidev_initialize(void) +void weak_function stm32_spidev_initialize(void) { -#ifdef CONFIG_STM32WL5_SPI1 +#ifdef CONFIG_STM32_SPI1 /* Configure SPI-based devices */ - g_spi1 = stm32wl5_spibus_initialize(1); + g_spi1 = stm32_spibus_initialize(1); if (!g_spi1) { spierr("ERROR: FAILED to initialize SPI port 1\n"); @@ -82,10 +82,10 @@ void weak_function stm32wl5_spidev_initialize(void) #ifdef CONFIG_LCD_SSD1680 spiinfo("Preparing additional lines for SSD1680 device\n"); - stm32wl5_configgpio(GPIO_SSD1680_CS); /* SSD1680 chip select */ - stm32wl5_configgpio(GPIO_SSD1680_CMD); /* SSD1680 data/!command */ - stm32wl5_configgpio(GPIO_SSD1680_RST); /* SSD1680 reset */ - stm32wl5_configgpio(GPIO_SSD1680_BUSY); /* SSD1680 busy */ + stm32_configgpio(GPIO_SSD1680_CS); /* SSD1680 chip select */ + stm32_configgpio(GPIO_SSD1680_CMD); /* SSD1680 data/!command */ + stm32_configgpio(GPIO_SSD1680_RST); /* SSD1680 reset */ + stm32_configgpio(GPIO_SSD1680_BUSY); /* SSD1680 busy */ #endif #endif @@ -105,7 +105,7 @@ void weak_function stm32wl5_spidev_initialize(void) * must be provided by board-specific logic. They are implementations of * the select and status methods of the SPI interface defined by struct * spi_ops_s (see include/nuttx/spi/spi.h). All other methods (including - * stm32wl5_spibus_initialize()) are provided by common STM32 logic. + * stm32_spibus_initialize()) are provided by common STM32 logic. * To use this common SPI logic on your board: * * 1. Provide logic in stm32_boardinitialize() to configure SPI chip select @@ -114,17 +114,17 @@ void weak_function stm32wl5_spidev_initialize(void) * in your board-specific logic. These functions will perform chip * selection and status operations using GPIOs in the way your board is * configured. - * 3. Add a calls to stm32wl5_spibus_initialize() in your low level + * 3. Add a calls to stm32_spibus_initialize() in your low level * application initialization logic - * 4. The handle returned by stm32wl5_spibus_initialize() may then be used + * 4. The handle returned by stm32_spibus_initialize() may then be used * to bind the SPI driver to higher level logic (e.g., calling * mmcsd_spislotinitialize(), for example, will bind the SPI driver to * the SPI MMC/SD driver). * ****************************************************************************/ -#ifdef CONFIG_STM32WL5_SPI1 -void stm32wl5_spi1select(struct spi_dev_s *dev, uint32_t devid, +#ifdef CONFIG_STM32_SPI1 +void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, bool selected) { spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : @@ -133,26 +133,26 @@ void stm32wl5_spi1select(struct spi_dev_s *dev, uint32_t devid, #if defined(CONFIG_LCD_SSD1680) if (devid == SPIDEV_DISPLAY(0)) { - stm32wl5_gpiowrite(GPIO_SSD1680_CS, !selected); + stm32_gpiowrite(GPIO_SSD1680_CS, !selected); } #endif #if defined(CONFIG_CAN_MCP2515) if (devid == SPIDEV_CANBUS(0)) { - stm32wl5_gpiowrite(GPIO_MCP2515_CS, !selected); + stm32_gpiowrite(GPIO_MCP2515_CS, !selected); } #endif #ifdef HAVE_MMCSD if (devid == SPIDEV_MMCSD(0)) { - stm32wl5_gpiowrite(GPIO_SPI_CS_SD_CARD, !selected); + stm32_gpiowrite(GPIO_SPI_CS_SD_CARD, !selected); } #endif } -uint8_t stm32wl5_spi1status(struct spi_dev_s *dev, uint32_t devid) +uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) { #if defined(CONFIG_LCD_SSD1680) if (devid == SPIDEV_DISPLAY(0)) @@ -164,12 +164,12 @@ uint8_t stm32wl5_spi1status(struct spi_dev_s *dev, uint32_t devid) return 0; } -int stm32wl5_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) +int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { #if defined(CONFIG_LCD_SSD1680) if (devid == SPIDEV_DISPLAY(0)) { - stm32wl5_gpiowrite(GPIO_SSD1680_CMD, !cmd); + stm32_gpiowrite(GPIO_SSD1680_CMD, !cmd); } #endif @@ -178,77 +178,24 @@ int stm32wl5_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) #endif -#ifdef CONFIG_STM32WL5_SPI2S2 -void stm32wl5_spi2s2select(struct spi_dev_s *dev, uint32_t devid, +#ifdef CONFIG_STM32_SPI2S2 +void stm32_spi2s2select(struct spi_dev_s *dev, uint32_t devid, bool selected) { spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); } -uint8_t stm32wl5_spi2s2status(struct spi_dev_s *dev, uint32_t devid) +uint8_t stm32_spi2s2status(struct spi_dev_s *dev, uint32_t devid) { return 0; } -int stm32wl5_spi2s2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) +int stm32_spi2s2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return OK; } #endif -/**************************************************************************** - * Name: stm32_spi1cmddata - * - * Description: - * Set or clear the SH1101A A0 or SD1306 D/C n bit to select data (true) - * or command (false). This function must be provided by platform-specific - * logic. This is an implementation of the cmddata method of the SPI - * interface defined by struct spi_ops_s (see include/nuttx/spi/spi.h). - * - * Input Parameters: - * - * spi - SPI device that controls the bus the device that requires the CMD/ - * DATA selection. - * devid - If there are multiple devices on the bus, this selects which one - * to select cmd or data. NOTE: This design restricts, for example, - * one one SPI display per SPI bus. - * cmd - true: select command; false: select data - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef CONFIG_SPI_CMDDATA -#ifdef CONFIG_STM32_SPI1 -int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) -{ -#if defined(CONFIG_LCD_SSD16800) - if (devid == SPIDEV_DISPLAY(0)) - { - stm32_gpiowrite(GPIO_SSD1680_CMD, !cmd); - } -#endif - - return OK; -} -#endif - -#ifdef CONFIG_STM32_SPI2 -int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) -{ - return OK; -} -#endif - -#ifdef CONFIG_STM32_SPI3 -int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) -{ - return OK; -} -#endif -#endif /* CONFIG_SPI_CMDDATA */ - -#endif /* CONFIG_STM32_SPI1 || CONFIG_STM32_SPI2 || CONFIG_STM32_SPI3 */ +#endif /* CONFIG_STM32_SPI1 || CONFIG_STM32_SPI2S2 */ diff --git a/boards/arm/stm32wl5/nucleo-wl55jc/src/stm32_ssd1680.c b/boards/arm/stm32wl5/nucleo-wl55jc/src/stm32_ssd1680.c index d57e2c42bfba4..289609b19b4f8 100644 --- a/boards/arm/stm32wl5/nucleo-wl55jc/src/stm32_ssd1680.c +++ b/boards/arm/stm32wl5/nucleo-wl55jc/src/stm32_ssd1680.c @@ -33,7 +33,7 @@ #include #include -#include "stm32wl5.h" +#include "stm32.h" #include "nucleo-wl55jc.h" #include "stm32wl5_gpio.h" #include "stm32wl5_ssd1680.h" @@ -59,7 +59,7 @@ static bool ssd1680_set_vcc(bool state) #if defined(CONFIG_SSD1680_GPIO_PIN_RST) static bool ssd1680_set_rst(bool state) { - stm32wl5_gpiowrite(GPIO_SSD1680_RST, state); + stm32_gpiowrite(GPIO_SSD1680_RST, state); return true; } #endif @@ -67,7 +67,7 @@ static bool ssd1680_set_rst(bool state) #if defined(CONFIG_SSD1680_GPIO_PIN_BUSY) static bool ssd1680_check_busy(void) { - return stm32wl5_gpioread(GPIO_SSD1680_BUSY); + return stm32_gpioread(GPIO_SSD1680_BUSY); } #endif @@ -106,20 +106,20 @@ int board_lcd_initialize(void) /* Initialize additional I/O for e-ink display */ #if defined(GPIO_SSD1680_PWR) - stm32wl5_configgpio(GPIO_SSD1680_PWR); /* SSD1680 pwr */ + stm32_configgpio(GPIO_SSD1680_PWR); /* SSD1680 pwr */ lcdinfo("SSD1680 power line is available (0x%08x)\n", GPIO_SSD1680_PWR); #else lcdinfo("PWR control line is disabled\n"); #endif #if defined(GPIO_SSD1680_RST) - stm32wl5_configgpio(GPIO_SSD1680_RST); /* SSD1680 reset */ + stm32_configgpio(GPIO_SSD1680_RST); /* SSD1680 reset */ lcdinfo("SSD1680 reset line is available (0x%08x)\n", GPIO_SSD1680_RST); #elif lcdinfo("SSD1680 RESET line is disabled\n"); #endif #if defined(GPIO_SSD1680_BUSY) - stm32wl5_configgpio(GPIO_SSD1680_BUSY); /* SSD1680 busy */ + stm32_configgpio(GPIO_SSD1680_BUSY); /* SSD1680 busy */ lcdinfo("SSD1680 Line for reading busy state is available (0x%08x)\n", GPIO_SSD1680_BUSY); #elif @@ -128,7 +128,7 @@ int board_lcd_initialize(void) /* Initialize SPI */ - spi = stm32wl5_spibus_initialize(CONFIG_SSD1680_SPI_BUS); + spi = stm32_spibus_initialize(CONFIG_SSD1680_SPI_BUS); if (!spi) { lcderr("ERROR: Failed to initialize SPI port %d\n", diff --git a/boards/arm/stm32wl5/nucleo-wl55jc/src/stm32wl5_ssd1680.h b/boards/arm/stm32wl5/nucleo-wl55jc/src/stm32wl5_ssd1680.h index 104118bba9e4e..10e86617cbf77 100644 --- a/boards/arm/stm32wl5/nucleo-wl55jc/src/stm32wl5_ssd1680.h +++ b/boards/arm/stm32wl5/nucleo-wl55jc/src/stm32wl5_ssd1680.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STMWL5_NUCLEO_WL55JC_INCLUDE_STM32WL5_SSD1680_H -#define __BOARDS_ARM_STMWL5_NUCLEO_WL55JC_INCLUDE_STM32WL5_SSD1680_H +#ifndef __BOARDS_ARM_STMWL5_NUCLEO_WL55JC_INCLUDE_STM32_SSD1680_H +#define __BOARDS_ARM_STMWL5_NUCLEO_WL55JC_INCLUDE_STM32_SSD1680_H /**************************************************************************** * Included Files @@ -63,4 +63,4 @@ struct lcd_dev_s *board_ssd1680_getdev(void); } #endif -#endif /* __BOARDS_ARM_STMWL5_NUCLEO_WL55JC_INCLUDE_STM32WL5_SSD1680_H */ \ No newline at end of file +#endif /* __BOARDS_ARM_STMWL5_NUCLEO_WL55JC_INCLUDE_STM32_SSD1680_H */ \ No newline at end of file diff --git a/include/nuttx/analog/ioctl.h b/include/nuttx/analog/ioctl.h index 25e759e26c057..19bcaad40e2e8 100644 --- a/include/nuttx/analog/ioctl.h +++ b/include/nuttx/analog/ioctl.h @@ -93,12 +93,12 @@ /* See arch/arm/src/stm32l4/stm32l4_adc.h */ -#define AN_STM32L4_FIRST (AN_ADS7828_FIRST + AN_ADS7828_NCMDS) -#define AN_STM32L4_NCMDS 2 +#define AN_STM32_FIRST (AN_ADS7828_FIRST + AN_ADS7828_NCMDS) +#define AN_STM32_NCMDS 2 /* See include/nuttx/analog/max1161x.h */ -#define AN_MAX1161X_FIRST (AN_STM32L4_FIRST + AN_STM32L4_NCMDS) +#define AN_MAX1161X_FIRST (AN_STM32_FIRST + AN_STM32_NCMDS) #define AN_MAX1161X_NCMDS 8 /* See include/nuttx/analog/mcp48xx.h */ diff --git a/tools/ci/testlist/arm-08.dat b/tools/ci/testlist/arm-08.dat index dda347b33d86d..b6354c5200c45 100644 --- a/tools/ci/testlist/arm-08.dat +++ b/tools/ci/testlist/arm-08.dat @@ -1,10 +1,25 @@ -/arm/stm32/[a-m]*,CONFIG_ARM_TOOLCHAIN_GNU_EABI - -/arm/stm32/nucleo-f1*,CONFIG_ARM_TOOLCHAIN_CLANG - -/arm/stm32/nucleo-f2*,CONFIG_ARM_TOOLCHAIN_CLANG - -/arm/stm32/nucleo-f30*,CONFIG_ARM_TOOLCHAIN_GNU_EABI +/arm/stm32c0/[a-m]*,CONFIG_ARM_TOOLCHAIN_GNU_EABI +/arm/stm32f0/[a-m]*,CONFIG_ARM_TOOLCHAIN_GNU_EABI +/arm/stm32f1/[a-m]*,CONFIG_ARM_TOOLCHAIN_GNU_EABI +/arm/stm32f2/[a-m]*,CONFIG_ARM_TOOLCHAIN_GNU_EABI +/arm/stm32f3/[a-m]*,CONFIG_ARM_TOOLCHAIN_GNU_EABI +/arm/stm32f4/[a-m]*,CONFIG_ARM_TOOLCHAIN_GNU_EABI +/arm/stm32f7/[a-m]*,CONFIG_ARM_TOOLCHAIN_GNU_EABI +/arm/stm32g0/[a-m]*,CONFIG_ARM_TOOLCHAIN_GNU_EABI +/arm/stm32g4/[a-m]*,CONFIG_ARM_TOOLCHAIN_GNU_EABI +/arm/stm32h7/[a-m]*,CONFIG_ARM_TOOLCHAIN_GNU_EABI +/arm/stm32l0/[a-m]*,CONFIG_ARM_TOOLCHAIN_GNU_EABI +/arm/stm32l1/[a-m]*,CONFIG_ARM_TOOLCHAIN_GNU_EABI +/arm/stm32l4/[a-m]*,CONFIG_ARM_TOOLCHAIN_GNU_EABI +/arm/stm32l5/[a-m]*,CONFIG_ARM_TOOLCHAIN_GNU_EABI +/arm/stm32u5/[a-m]*,CONFIG_ARM_TOOLCHAIN_GNU_EABI +/arm/stm32wb/[a-m]*,CONFIG_ARM_TOOLCHAIN_GNU_EABI + +/arm/stm32f1/nucleo-f1*,CONFIG_ARM_TOOLCHAIN_CLANG + +/arm/stm32f2/nucleo-f2*,CONFIG_ARM_TOOLCHAIN_CLANG + +/arm/stm32f3/nucleo-f30*,CONFIG_ARM_TOOLCHAIN_GNU_EABI # Boards build by CMake diff --git a/tools/ci/testlist/arm-09.dat b/tools/ci/testlist/arm-09.dat index cd9c27d5fdb28..82448d0a9ab47 100644 --- a/tools/ci/testlist/arm-09.dat +++ b/tools/ci/testlist/arm-09.dat @@ -1,12 +1,18 @@ -/arm/stm32/nucleo-f33*,CONFIG_ARM_TOOLCHAIN_CLANG +/arm/stm32f3/nucleo-f33*,CONFIG_ARM_TOOLCHAIN_CLANG -/arm/stm32/nucleo-f4*,CONFIG_ARM_TOOLCHAIN_CLANG +/arm/stm32f4/nucleo-f4*,CONFIG_ARM_TOOLCHAIN_CLANG -/arm/stm32/nucleo-g*,CONFIG_ARM_TOOLCHAIN_GNU_EABI +/arm/stm32g0/nucleo-g*,CONFIG_ARM_TOOLCHAIN_GNU_EABI +/arm/stm32g4/nucleo-g*,CONFIG_ARM_TOOLCHAIN_GNU_EABI -/arm/stm32/nucleo-l*,CONFIG_ARM_TOOLCHAIN_CLANG +/arm/stm32l0/nucleo-l*,CONFIG_ARM_TOOLCHAIN_CLANG +/arm/stm32l1/nucleo-l*,CONFIG_ARM_TOOLCHAIN_CLANG +/arm/stm32l4/nucleo-l*,CONFIG_ARM_TOOLCHAIN_CLANG +/arm/stm32l5/nucleo-l*,CONFIG_ARM_TOOLCHAIN_CLANG -/arm/stm32/olimex-*,CONFIG_ARM_TOOLCHAIN_GNU_EABI +/arm/stm32f1/olimex-*,CONFIG_ARM_TOOLCHAIN_GNU_EABI +/arm/stm32f2/olimex-*,CONFIG_ARM_TOOLCHAIN_GNU_EABI +/arm/stm32f4/olimex-*,CONFIG_ARM_TOOLCHAIN_GNU_EABI # Boards build by CMake diff --git a/tools/ci/testlist/arm-10.dat b/tools/ci/testlist/arm-10.dat index 1e45e9365cdc2..30d56951ccd7e 100644 --- a/tools/ci/testlist/arm-10.dat +++ b/tools/ci/testlist/arm-10.dat @@ -1,15 +1,15 @@ -/arm/stm32/olimexino-stm32,CONFIG_ARM_TOOLCHAIN_CLANG +/arm/stm32f1/olimexino-stm32,CONFIG_ARM_TOOLCHAIN_CLANG -/arm/stm32/omnibusf4,CONFIG_ARM_TOOLCHAIN_CLANG +/arm/stm32f4/omnibusf4,CONFIG_ARM_TOOLCHAIN_CLANG -/arm/stm32/photon,CONFIG_ARM_TOOLCHAIN_GNU_EABI +/arm/stm32f2/photon,CONFIG_ARM_TOOLCHAIN_GNU_EABI -/arm/stm32/shenzhou,CONFIG_ARM_TOOLCHAIN_CLANG +/arm/stm32f1/shenzhou,CONFIG_ARM_TOOLCHAIN_CLANG -shenzhou:thttpd -/arm/stm32/stm3210e-eval,CONFIG_ARM_TOOLCHAIN_CLANG +/arm/stm32f1/stm3210e-eval,CONFIG_ARM_TOOLCHAIN_CLANG -/arm/stm32/stm3220g-eval,CONFIG_ARM_TOOLCHAIN_GNU_EABI +/arm/stm32f2/stm3220g-eval,CONFIG_ARM_TOOLCHAIN_GNU_EABI -/arm/stm32/stm3240g-eval,CONFIG_ARM_TOOLCHAIN_GNU_EABI +/arm/stm32f4/stm3240g-eval,CONFIG_ARM_TOOLCHAIN_GNU_EABI -stm3240g-eval:knxwm diff --git a/tools/ci/testlist/arm-11.dat b/tools/ci/testlist/arm-11.dat index 6af3cdbfa51ad..2564b8be8e00e 100644 --- a/tools/ci/testlist/arm-11.dat +++ b/tools/ci/testlist/arm-11.dat @@ -1,18 +1,18 @@ -/arm/stm32/stm32_tiny,CONFIG_ARM_TOOLCHAIN_CLANG +/arm/stm32f1/stm32_tiny,CONFIG_ARM_TOOLCHAIN_CLANG -/arm/stm32/stm32butterfly2,CONFIG_ARM_TOOLCHAIN_CLANG +/arm/stm32f1/stm32butterfly2,CONFIG_ARM_TOOLCHAIN_CLANG -/arm/stm32/stm32f103-minimum,CONFIG_ARM_TOOLCHAIN_GNU_EABI +/arm/stm32f1/stm32f103-minimum,CONFIG_ARM_TOOLCHAIN_GNU_EABI -/arm/stm32/stm32f334-disco,CONFIG_ARM_TOOLCHAIN_CLANG +/arm/stm32f3/stm32f334-disco,CONFIG_ARM_TOOLCHAIN_CLANG -/arm/stm32/stm32f3discovery,CONFIG_ARM_TOOLCHAIN_CLANG +/arm/stm32f3/stm32f3discovery,CONFIG_ARM_TOOLCHAIN_CLANG -/arm/stm32/stm32f411-minimum,CONFIG_ARM_TOOLCHAIN_CLANG +/arm/stm32f4/stm32f411-minimum,CONFIG_ARM_TOOLCHAIN_CLANG -/arm/stm32/stm32f411e-disco,CONFIG_ARM_TOOLCHAIN_CLANG +/arm/stm32f4/stm32f411e-disco,CONFIG_ARM_TOOLCHAIN_CLANG -/arm/stm32/stm32f429i-disco,CONFIG_ARM_TOOLCHAIN_CLANG +/arm/stm32f4/stm32f429i-disco,CONFIG_ARM_TOOLCHAIN_CLANG # Boards build by CMake diff --git a/tools/ci/testlist/arm-12.dat b/tools/ci/testlist/arm-12.dat index caf7755437587..e9e1aa7a42b30 100644 --- a/tools/ci/testlist/arm-12.dat +++ b/tools/ci/testlist/arm-12.dat @@ -1,11 +1,11 @@ -/arm/stm32/stm32f4discovery,CONFIG_ARM_TOOLCHAIN_GNU_EABI +/arm/stm32f4/stm32f4discovery,CONFIG_ARM_TOOLCHAIN_GNU_EABI -stm32f4discovery:winbuild -/arm/stm32/stm32ldiscovery,CONFIG_ARM_TOOLCHAIN_CLANG +/arm/stm32l1/stm32ldiscovery,CONFIG_ARM_TOOLCHAIN_CLANG -/arm/stm32/stm32vldiscovery,CONFIG_ARM_TOOLCHAIN_CLANG +/arm/stm32f1/stm32vldiscovery,CONFIG_ARM_TOOLCHAIN_CLANG -/arm/stm32/viewtool-stm32f107,CONFIG_ARM_TOOLCHAIN_CLANG +/arm/stm32f1/viewtool-stm32f107,CONFIG_ARM_TOOLCHAIN_CLANG # cURL error 60 SSL certificate expired -stm32f4discovery:cxxtest diff --git a/tools/ci/testlist/arm-13.dat b/tools/ci/testlist/arm-13.dat index ed3b7bb940144..411f2ed1ea230 100644 --- a/tools/ci/testlist/arm-13.dat +++ b/tools/ci/testlist/arm-13.dat @@ -1,6 +1,7 @@ -/arm/stm32f*,CONFIG_ARM_TOOLCHAIN_CLANG +/arm/stm32f7,CONFIG_ARM_TOOLCHAIN_CLANG -/arm/stm32h*,CONFIG_ARM_TOOLCHAIN_CLANG +/arm/stm32h5,CONFIG_ARM_TOOLCHAIN_CLANG +/arm/stm32h7,CONFIG_ARM_TOOLCHAIN_CLANG # Boards build by CMake diff --git a/tools/ci/testlist/macos.dat b/tools/ci/testlist/macos.dat index 70c05ee29dbcf..6c442b5026a20 100644 --- a/tools/ci/testlist/macos.dat +++ b/tools/ci/testlist/macos.dat @@ -3,7 +3,7 @@ # ARM -/arm/stm32/stm32f4discovery/configs/nsh,CONFIG_ARM_TOOLCHAIN_GNU_EABI +/arm/stm32f4/stm32f4discovery/configs/nsh,CONFIG_ARM_TOOLCHAIN_GNU_EABI # ARM64 diff --git a/tools/ci/testlist/msys2.dat b/tools/ci/testlist/msys2.dat index 542b59af41900..1996dff9c3c68 100644 --- a/tools/ci/testlist/msys2.dat +++ b/tools/ci/testlist/msys2.dat @@ -3,9 +3,9 @@ # ARM -/arm/stm32/nucleo-l152re/configs/nsh,CONFIG_ARM_TOOLCHAIN_GNU_EABI +/arm/stm32l1/nucleo-l152re/configs/nsh,CONFIG_ARM_TOOLCHAIN_GNU_EABI -/arm/stm32/nucleo-f411re/configs/nsh,CONFIG_ARM_TOOLCHAIN_GNU_EABI +/arm/stm32f4/nucleo-f411re/configs/nsh,CONFIG_ARM_TOOLCHAIN_GNU_EABI # ARM64 diff --git a/tools/ci/testlist/windows.dat b/tools/ci/testlist/windows.dat index ec54d4f82bb57..15d7c21b1ae7b 100644 --- a/tools/ci/testlist/windows.dat +++ b/tools/ci/testlist/windows.dat @@ -2,9 +2,9 @@ # ARM -/arm/stm32/nucleo-l152re/configs/nsh,CONFIG_ARM_TOOLCHAIN_GNU_EABI +/arm/stm32l1/nucleo-l152re/configs/nsh,CONFIG_ARM_TOOLCHAIN_GNU_EABI -/arm/stm32/nucleo-f411re/configs/nsh,CONFIG_ARM_TOOLCHAIN_CLANG +/arm/stm32f4/nucleo-f411re/configs/nsh,CONFIG_ARM_TOOLCHAIN_CLANG /arm/rp2040/raspberrypi-pico/configs/nsh,CONFIG_ARM_TOOLCHAIN_GNU_EABI